FinishedHEADmaster

1291 files changed, 360473 insertions, 0 deletions

diff --git a/README.me b/README.me
new file mode 100644
index 0000000..56e9511
--- /dev/null
+++ b/README.me
@@ -0,0 +1 @@
+# Sobel Filter Catapult
diff --git a/Sobel.ccs b/Sobel.ccs
new file mode 100644
index 0000000..ce69ce8
--- /dev/null
+++ b/Sobel.ccs
@@ -0,0 +1,23 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+if {[info script] != {} && [file isdirectory [file rootname [info script]]]} {
+  project load [file rootname [info script]] 2011a
+} elseif { [file isdirectory {//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel}] } {
+  project load {//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel} 2011a
+} else {
+  error {unable to locate project directory 'Sobel'}
+}
+
diff --git a/Sobel/SIF/project.sif b/Sobel/SIF/project.sif
new file mode 100644
index 0000000..023ddec
--- /dev/null
+++ b/Sobel/SIF/project.sif
diff --git a/Sobel/SIF/sid10__allocate.sif b/Sobel/SIF/sid10__allocate.sif
new file mode 100644
index 0000000..68b00c9
--- /dev/null
+++ b/Sobel/SIF/sid10__allocate.sif
diff --git a/Sobel/SIF/sid10__analyze.il b/Sobel/SIF/sid10__analyze.il
new file mode 100644
index 0000000..041f34f
--- /dev/null
+++ b/Sobel/SIF/sid10__analyze.il
diff --git a/Sobel/SIF/sid10__architect.sif b/Sobel/SIF/sid10__architect.sif
new file mode 100644
index 0000000..b53f469
--- /dev/null
+++ b/Sobel/SIF/sid10__architect.sif
diff --git a/Sobel/SIF/sid10__assembly.sif b/Sobel/SIF/sid10__assembly.sif
new file mode 100644
index 0000000..bf7e14a
--- /dev/null
+++ b/Sobel/SIF/sid10__assembly.sif
diff --git a/Sobel/SIF/sid10__compile.sif b/Sobel/SIF/sid10__compile.sif
new file mode 100644
index 0000000..bf7e14a
--- /dev/null
+++ b/Sobel/SIF/sid10__compile.sif
diff --git a/Sobel/SIF/sid10__dpfsm.sif b/Sobel/SIF/sid10__dpfsm.sif
new file mode 100644
index 0000000..e8167c2
--- /dev/null
+++ b/Sobel/SIF/sid10__dpfsm.sif
diff --git a/Sobel/SIF/sid10__extract.sif b/Sobel/SIF/sid10__extract.sif
new file mode 100644
index 0000000..44e86a8
--- /dev/null
+++ b/Sobel/SIF/sid10__extract.sif
diff --git a/Sobel/SIF/sid10__instance.sif b/Sobel/SIF/sid10__instance.sif
new file mode 100644
index 0000000..8ca2d6f
--- /dev/null
+++ b/Sobel/SIF/sid10__instance.sif
diff --git a/Sobel/SIF/sid10__loops.sif b/Sobel/SIF/sid10__loops.sif
new file mode 100644
index 0000000..bb5054c
--- /dev/null
+++ b/Sobel/SIF/sid10__loops.sif
diff --git a/Sobel/SIF/sid10__memories.sif b/Sobel/SIF/sid10__memories.sif
new file mode 100644
index 0000000..93daad4
--- /dev/null
+++ b/Sobel/SIF/sid10__memories.sif
diff --git a/Sobel/SIF/sid10__schedule.sif b/Sobel/SIF/sid10__schedule.sif
new file mode 100644
index 0000000..4743b58
--- /dev/null
+++ b/Sobel/SIF/sid10__schedule.sif
diff --git a/Sobel/SIF/sid11__allocate.sif b/Sobel/SIF/sid11__allocate.sif
new file mode 100644
index 0000000..56e88dc
--- /dev/null
+++ b/Sobel/SIF/sid11__allocate.sif
diff --git a/Sobel/SIF/sid11__analyze.il b/Sobel/SIF/sid11__analyze.il
new file mode 100644
index 0000000..877df05
--- /dev/null
+++ b/Sobel/SIF/sid11__analyze.il
diff --git a/Sobel/SIF/sid11__architect.sif b/Sobel/SIF/sid11__architect.sif
new file mode 100644
index 0000000..35bf110
--- /dev/null
+++ b/Sobel/SIF/sid11__architect.sif
diff --git a/Sobel/SIF/sid11__assembly.sif b/Sobel/SIF/sid11__assembly.sif
new file mode 100644
index 0000000..43bf964
--- /dev/null
+++ b/Sobel/SIF/sid11__assembly.sif
diff --git a/Sobel/SIF/sid11__compile.sif b/Sobel/SIF/sid11__compile.sif
new file mode 100644
index 0000000..43bf964
--- /dev/null
+++ b/Sobel/SIF/sid11__compile.sif
diff --git a/Sobel/SIF/sid11__dpfsm.sif b/Sobel/SIF/sid11__dpfsm.sif
new file mode 100644
index 0000000..331bec8
--- /dev/null
+++ b/Sobel/SIF/sid11__dpfsm.sif
diff --git a/Sobel/SIF/sid11__extract.sif b/Sobel/SIF/sid11__extract.sif
new file mode 100644
index 0000000..09465dc
--- /dev/null
+++ b/Sobel/SIF/sid11__extract.sif
diff --git a/Sobel/SIF/sid11__instance.sif b/Sobel/SIF/sid11__instance.sif
new file mode 100644
index 0000000..c2bdff6
--- /dev/null
+++ b/Sobel/SIF/sid11__instance.sif
diff --git a/Sobel/SIF/sid11__loops.sif b/Sobel/SIF/sid11__loops.sif
new file mode 100644
index 0000000..f682ec6
--- /dev/null
+++ b/Sobel/SIF/sid11__loops.sif
diff --git a/Sobel/SIF/sid11__memories.sif b/Sobel/SIF/sid11__memories.sif
new file mode 100644
index 0000000..816e5a0
--- /dev/null
+++ b/Sobel/SIF/sid11__memories.sif
diff --git a/Sobel/SIF/sid11__schedule.sif b/Sobel/SIF/sid11__schedule.sif
new file mode 100644
index 0000000..6b86b7f
--- /dev/null
+++ b/Sobel/SIF/sid11__schedule.sif
diff --git a/Sobel/SIF/sid12__allocate.sif b/Sobel/SIF/sid12__allocate.sif
new file mode 100644
index 0000000..7dedbd5
--- /dev/null
+++ b/Sobel/SIF/sid12__allocate.sif
diff --git a/Sobel/SIF/sid12__analyze.il b/Sobel/SIF/sid12__analyze.il
new file mode 100644
index 0000000..1d3fdcc
--- /dev/null
+++ b/Sobel/SIF/sid12__analyze.il
diff --git a/Sobel/SIF/sid12__architect.sif b/Sobel/SIF/sid12__architect.sif
new file mode 100644
index 0000000..5fed06d
--- /dev/null
+++ b/Sobel/SIF/sid12__architect.sif
diff --git a/Sobel/SIF/sid12__assembly.sif b/Sobel/SIF/sid12__assembly.sif
new file mode 100644
index 0000000..118d4a6
--- /dev/null
+++ b/Sobel/SIF/sid12__assembly.sif
diff --git a/Sobel/SIF/sid12__compile.sif b/Sobel/SIF/sid12__compile.sif
new file mode 100644
index 0000000..118d4a6
--- /dev/null
+++ b/Sobel/SIF/sid12__compile.sif
diff --git a/Sobel/SIF/sid12__dpfsm.sif b/Sobel/SIF/sid12__dpfsm.sif
new file mode 100644
index 0000000..89d5344
--- /dev/null
+++ b/Sobel/SIF/sid12__dpfsm.sif
diff --git a/Sobel/SIF/sid12__extract.sif b/Sobel/SIF/sid12__extract.sif
new file mode 100644
index 0000000..ae194d2
--- /dev/null
+++ b/Sobel/SIF/sid12__extract.sif
diff --git a/Sobel/SIF/sid12__instance.sif b/Sobel/SIF/sid12__instance.sif
new file mode 100644
index 0000000..5ce65cf
--- /dev/null
+++ b/Sobel/SIF/sid12__instance.sif
diff --git a/Sobel/SIF/sid12__loops.sif b/Sobel/SIF/sid12__loops.sif
new file mode 100644
index 0000000..ba2d3f5
--- /dev/null
+++ b/Sobel/SIF/sid12__loops.sif
diff --git a/Sobel/SIF/sid12__memories.sif b/Sobel/SIF/sid12__memories.sif
new file mode 100644
index 0000000..dc2b578
--- /dev/null
+++ b/Sobel/SIF/sid12__memories.sif
diff --git a/Sobel/SIF/sid12__schedule.sif b/Sobel/SIF/sid12__schedule.sif
new file mode 100644
index 0000000..f5d84f8
--- /dev/null
+++ b/Sobel/SIF/sid12__schedule.sif
diff --git a/Sobel/SIF/sid14__allocate.sif b/Sobel/SIF/sid14__allocate.sif
new file mode 100644
index 0000000..219356e
--- /dev/null
+++ b/Sobel/SIF/sid14__allocate.sif
diff --git a/Sobel/SIF/sid14__analyze.il b/Sobel/SIF/sid14__analyze.il
new file mode 100644
index 0000000..b64a7c8
--- /dev/null
+++ b/Sobel/SIF/sid14__analyze.il
diff --git a/Sobel/SIF/sid14__architect.sif b/Sobel/SIF/sid14__architect.sif
new file mode 100644
index 0000000..00ca854
--- /dev/null
+++ b/Sobel/SIF/sid14__architect.sif
diff --git a/Sobel/SIF/sid14__assembly.sif b/Sobel/SIF/sid14__assembly.sif
new file mode 100644
index 0000000..57d3d77
--- /dev/null
+++ b/Sobel/SIF/sid14__assembly.sif
diff --git a/Sobel/SIF/sid14__compile.sif b/Sobel/SIF/sid14__compile.sif
new file mode 100644
index 0000000..57d3d77
--- /dev/null
+++ b/Sobel/SIF/sid14__compile.sif
diff --git a/Sobel/SIF/sid14__dpfsm.sif b/Sobel/SIF/sid14__dpfsm.sif
new file mode 100644
index 0000000..da524f6
--- /dev/null
+++ b/Sobel/SIF/sid14__dpfsm.sif
diff --git a/Sobel/SIF/sid14__extract.sif b/Sobel/SIF/sid14__extract.sif
new file mode 100644
index 0000000..b5bd3d7
--- /dev/null
+++ b/Sobel/SIF/sid14__extract.sif
diff --git a/Sobel/SIF/sid14__instance.sif b/Sobel/SIF/sid14__instance.sif
new file mode 100644
index 0000000..cf2e22e
--- /dev/null
+++ b/Sobel/SIF/sid14__instance.sif
diff --git a/Sobel/SIF/sid14__loops.sif b/Sobel/SIF/sid14__loops.sif
new file mode 100644
index 0000000..57e696c
--- /dev/null
+++ b/Sobel/SIF/sid14__loops.sif
diff --git a/Sobel/SIF/sid14__memories.sif b/Sobel/SIF/sid14__memories.sif
new file mode 100644
index 0000000..15d8587
--- /dev/null
+++ b/Sobel/SIF/sid14__memories.sif
diff --git a/Sobel/SIF/sid14__schedule.sif b/Sobel/SIF/sid14__schedule.sif
new file mode 100644
index 0000000..59cbde6
--- /dev/null
+++ b/Sobel/SIF/sid14__schedule.sif
diff --git a/Sobel/SIF/sid1__allocate.sif b/Sobel/SIF/sid1__allocate.sif
new file mode 100644
index 0000000..74707e5
--- /dev/null
+++ b/Sobel/SIF/sid1__allocate.sif
diff --git a/Sobel/SIF/sid1__analyze.il b/Sobel/SIF/sid1__analyze.il
new file mode 100644
index 0000000..7df3703
--- /dev/null
+++ b/Sobel/SIF/sid1__analyze.il
diff --git a/Sobel/SIF/sid1__architect.sif b/Sobel/SIF/sid1__architect.sif
new file mode 100644
index 0000000..2510822
--- /dev/null
+++ b/Sobel/SIF/sid1__architect.sif
diff --git a/Sobel/SIF/sid1__assembly.sif b/Sobel/SIF/sid1__assembly.sif
new file mode 100644
index 0000000..cf04d2e
--- /dev/null
+++ b/Sobel/SIF/sid1__assembly.sif
diff --git a/Sobel/SIF/sid1__compile.sif b/Sobel/SIF/sid1__compile.sif
new file mode 100644
index 0000000..cf04d2e
--- /dev/null
+++ b/Sobel/SIF/sid1__compile.sif
diff --git a/Sobel/SIF/sid1__dpfsm.sif b/Sobel/SIF/sid1__dpfsm.sif
new file mode 100644
index 0000000..86d6d81
--- /dev/null
+++ b/Sobel/SIF/sid1__dpfsm.sif
diff --git a/Sobel/SIF/sid1__extract.sif b/Sobel/SIF/sid1__extract.sif
new file mode 100644
index 0000000..247db25
--- /dev/null
+++ b/Sobel/SIF/sid1__extract.sif
diff --git a/Sobel/SIF/sid1__instance.sif b/Sobel/SIF/sid1__instance.sif
new file mode 100644
index 0000000..200e3f2
--- /dev/null
+++ b/Sobel/SIF/sid1__instance.sif
diff --git a/Sobel/SIF/sid1__loops.sif b/Sobel/SIF/sid1__loops.sif
new file mode 100644
index 0000000..0f14a45
--- /dev/null
+++ b/Sobel/SIF/sid1__loops.sif
diff --git a/Sobel/SIF/sid1__memories.sif b/Sobel/SIF/sid1__memories.sif
new file mode 100644
index 0000000..58e232e
--- /dev/null
+++ b/Sobel/SIF/sid1__memories.sif
diff --git a/Sobel/SIF/sid1__schedule.sif b/Sobel/SIF/sid1__schedule.sif
new file mode 100644
index 0000000..e2c54b3
--- /dev/null
+++ b/Sobel/SIF/sid1__schedule.sif
diff --git a/Sobel/SIF/sid2__allocate.sif b/Sobel/SIF/sid2__allocate.sif
new file mode 100644
index 0000000..7491ee8
--- /dev/null
+++ b/Sobel/SIF/sid2__allocate.sif
diff --git a/Sobel/SIF/sid2__analyze.il b/Sobel/SIF/sid2__analyze.il
new file mode 100644
index 0000000..5483ef4
--- /dev/null
+++ b/Sobel/SIF/sid2__analyze.il
diff --git a/Sobel/SIF/sid2__architect.sif b/Sobel/SIF/sid2__architect.sif
new file mode 100644
index 0000000..24e4908
--- /dev/null
+++ b/Sobel/SIF/sid2__architect.sif
diff --git a/Sobel/SIF/sid2__assembly.sif b/Sobel/SIF/sid2__assembly.sif
new file mode 100644
index 0000000..6324aa5
--- /dev/null
+++ b/Sobel/SIF/sid2__assembly.sif
diff --git a/Sobel/SIF/sid2__compile.sif b/Sobel/SIF/sid2__compile.sif
new file mode 100644
index 0000000..6324aa5
--- /dev/null
+++ b/Sobel/SIF/sid2__compile.sif
diff --git a/Sobel/SIF/sid2__dpfsm.sif b/Sobel/SIF/sid2__dpfsm.sif
new file mode 100644
index 0000000..ff8ca7e
--- /dev/null
+++ b/Sobel/SIF/sid2__dpfsm.sif
diff --git a/Sobel/SIF/sid2__extract.sif b/Sobel/SIF/sid2__extract.sif
new file mode 100644
index 0000000..b8ed791
--- /dev/null
+++ b/Sobel/SIF/sid2__extract.sif
diff --git a/Sobel/SIF/sid2__instance.sif b/Sobel/SIF/sid2__instance.sif
new file mode 100644
index 0000000..9846514
--- /dev/null
+++ b/Sobel/SIF/sid2__instance.sif
diff --git a/Sobel/SIF/sid2__loops.sif b/Sobel/SIF/sid2__loops.sif
new file mode 100644
index 0000000..dbb0513
--- /dev/null
+++ b/Sobel/SIF/sid2__loops.sif
diff --git a/Sobel/SIF/sid2__memories.sif b/Sobel/SIF/sid2__memories.sif
new file mode 100644
index 0000000..d0708c4
--- /dev/null
+++ b/Sobel/SIF/sid2__memories.sif
diff --git a/Sobel/SIF/sid2__schedule.sif b/Sobel/SIF/sid2__schedule.sif
new file mode 100644
index 0000000..20067f7
--- /dev/null
+++ b/Sobel/SIF/sid2__schedule.sif
diff --git a/Sobel/SIF/sid4__allocate.sif b/Sobel/SIF/sid4__allocate.sif
new file mode 100644
index 0000000..523e772
--- /dev/null
+++ b/Sobel/SIF/sid4__allocate.sif
diff --git a/Sobel/SIF/sid4__analyze.il b/Sobel/SIF/sid4__analyze.il
new file mode 100644
index 0000000..b0ca38c
--- /dev/null
+++ b/Sobel/SIF/sid4__analyze.il
diff --git a/Sobel/SIF/sid4__architect.sif b/Sobel/SIF/sid4__architect.sif
new file mode 100644
index 0000000..97fca3b
--- /dev/null
+++ b/Sobel/SIF/sid4__architect.sif
diff --git a/Sobel/SIF/sid4__assembly.sif b/Sobel/SIF/sid4__assembly.sif
new file mode 100644
index 0000000..621cdae
--- /dev/null
+++ b/Sobel/SIF/sid4__assembly.sif
diff --git a/Sobel/SIF/sid4__compile.sif b/Sobel/SIF/sid4__compile.sif
new file mode 100644
index 0000000..621cdae
--- /dev/null
+++ b/Sobel/SIF/sid4__compile.sif
diff --git a/Sobel/SIF/sid4__dpfsm.sif b/Sobel/SIF/sid4__dpfsm.sif
new file mode 100644
index 0000000..92eeaa6
--- /dev/null
+++ b/Sobel/SIF/sid4__dpfsm.sif
diff --git a/Sobel/SIF/sid4__extract.sif b/Sobel/SIF/sid4__extract.sif
new file mode 100644
index 0000000..fb3d35f
--- /dev/null
+++ b/Sobel/SIF/sid4__extract.sif
diff --git a/Sobel/SIF/sid4__instance.sif b/Sobel/SIF/sid4__instance.sif
new file mode 100644
index 0000000..67fc6a8
--- /dev/null
+++ b/Sobel/SIF/sid4__instance.sif
diff --git a/Sobel/SIF/sid4__loops.sif b/Sobel/SIF/sid4__loops.sif
new file mode 100644
index 0000000..f31292f
--- /dev/null
+++ b/Sobel/SIF/sid4__loops.sif
diff --git a/Sobel/SIF/sid4__memories.sif b/Sobel/SIF/sid4__memories.sif
new file mode 100644
index 0000000..f714176
--- /dev/null
+++ b/Sobel/SIF/sid4__memories.sif
diff --git a/Sobel/SIF/sid4__schedule.sif b/Sobel/SIF/sid4__schedule.sif
new file mode 100644
index 0000000..2dae98e
--- /dev/null
+++ b/Sobel/SIF/sid4__schedule.sif
diff --git a/Sobel/SIF/sid5__allocate.sif b/Sobel/SIF/sid5__allocate.sif
new file mode 100644
index 0000000..b075733
--- /dev/null
+++ b/Sobel/SIF/sid5__allocate.sif
diff --git a/Sobel/SIF/sid5__analyze.il b/Sobel/SIF/sid5__analyze.il
new file mode 100644
index 0000000..ec8f2af
--- /dev/null
+++ b/Sobel/SIF/sid5__analyze.il
diff --git a/Sobel/SIF/sid5__architect.sif b/Sobel/SIF/sid5__architect.sif
new file mode 100644
index 0000000..e784a37
--- /dev/null
+++ b/Sobel/SIF/sid5__architect.sif
diff --git a/Sobel/SIF/sid5__assembly.sif b/Sobel/SIF/sid5__assembly.sif
new file mode 100644
index 0000000..8f49e76
--- /dev/null
+++ b/Sobel/SIF/sid5__assembly.sif
diff --git a/Sobel/SIF/sid5__compile.sif b/Sobel/SIF/sid5__compile.sif
new file mode 100644
index 0000000..8f49e76
--- /dev/null
+++ b/Sobel/SIF/sid5__compile.sif
diff --git a/Sobel/SIF/sid5__dpfsm.sif b/Sobel/SIF/sid5__dpfsm.sif
new file mode 100644
index 0000000..5839f67
--- /dev/null
+++ b/Sobel/SIF/sid5__dpfsm.sif
diff --git a/Sobel/SIF/sid5__extract.sif b/Sobel/SIF/sid5__extract.sif
new file mode 100644
index 0000000..e8d6a6a
--- /dev/null
+++ b/Sobel/SIF/sid5__extract.sif
diff --git a/Sobel/SIF/sid5__instance.sif b/Sobel/SIF/sid5__instance.sif
new file mode 100644
index 0000000..103788a
--- /dev/null
+++ b/Sobel/SIF/sid5__instance.sif
diff --git a/Sobel/SIF/sid5__loops.sif b/Sobel/SIF/sid5__loops.sif
new file mode 100644
index 0000000..cc86107
--- /dev/null
+++ b/Sobel/SIF/sid5__loops.sif
diff --git a/Sobel/SIF/sid5__memories.sif b/Sobel/SIF/sid5__memories.sif
new file mode 100644
index 0000000..18c6380
--- /dev/null
+++ b/Sobel/SIF/sid5__memories.sif
diff --git a/Sobel/SIF/sid5__schedule.sif b/Sobel/SIF/sid5__schedule.sif
new file mode 100644
index 0000000..15b7d19
--- /dev/null
+++ b/Sobel/SIF/sid5__schedule.sif
diff --git a/Sobel/SIF/sid6__allocate.sif b/Sobel/SIF/sid6__allocate.sif
new file mode 100644
index 0000000..c9ed387
--- /dev/null
+++ b/Sobel/SIF/sid6__allocate.sif
diff --git a/Sobel/SIF/sid6__analyze.il b/Sobel/SIF/sid6__analyze.il
new file mode 100644
index 0000000..69af00f
--- /dev/null
+++ b/Sobel/SIF/sid6__analyze.il
diff --git a/Sobel/SIF/sid6__architect.sif b/Sobel/SIF/sid6__architect.sif
new file mode 100644
index 0000000..577fa43
--- /dev/null
+++ b/Sobel/SIF/sid6__architect.sif
diff --git a/Sobel/SIF/sid6__assembly.sif b/Sobel/SIF/sid6__assembly.sif
new file mode 100644
index 0000000..dea2929
--- /dev/null
+++ b/Sobel/SIF/sid6__assembly.sif
diff --git a/Sobel/SIF/sid6__compile.sif b/Sobel/SIF/sid6__compile.sif
new file mode 100644
index 0000000..dea2929
--- /dev/null
+++ b/Sobel/SIF/sid6__compile.sif
diff --git a/Sobel/SIF/sid6__dpfsm.sif b/Sobel/SIF/sid6__dpfsm.sif
new file mode 100644
index 0000000..2655115
--- /dev/null
+++ b/Sobel/SIF/sid6__dpfsm.sif
diff --git a/Sobel/SIF/sid6__extract.sif b/Sobel/SIF/sid6__extract.sif
new file mode 100644
index 0000000..9851a9e
--- /dev/null
+++ b/Sobel/SIF/sid6__extract.sif
diff --git a/Sobel/SIF/sid6__instance.sif b/Sobel/SIF/sid6__instance.sif
new file mode 100644
index 0000000..7afe0d5
--- /dev/null
+++ b/Sobel/SIF/sid6__instance.sif
diff --git a/Sobel/SIF/sid6__loops.sif b/Sobel/SIF/sid6__loops.sif
new file mode 100644
index 0000000..d713e7e
--- /dev/null
+++ b/Sobel/SIF/sid6__loops.sif
diff --git a/Sobel/SIF/sid6__memories.sif b/Sobel/SIF/sid6__memories.sif
new file mode 100644
index 0000000..8d3d8df
--- /dev/null
+++ b/Sobel/SIF/sid6__memories.sif
diff --git a/Sobel/SIF/sid6__schedule.sif b/Sobel/SIF/sid6__schedule.sif
new file mode 100644
index 0000000..0f9bcbd
--- /dev/null
+++ b/Sobel/SIF/sid6__schedule.sif
diff --git a/Sobel/SIF/sid7__allocate.sif b/Sobel/SIF/sid7__allocate.sif
new file mode 100644
index 0000000..a6ab4bf
--- /dev/null
+++ b/Sobel/SIF/sid7__allocate.sif
diff --git a/Sobel/SIF/sid7__analyze.il b/Sobel/SIF/sid7__analyze.il
new file mode 100644
index 0000000..21f6790
--- /dev/null
+++ b/Sobel/SIF/sid7__analyze.il
diff --git a/Sobel/SIF/sid7__architect.sif b/Sobel/SIF/sid7__architect.sif
new file mode 100644
index 0000000..db9c30a
--- /dev/null
+++ b/Sobel/SIF/sid7__architect.sif
diff --git a/Sobel/SIF/sid7__assembly.sif b/Sobel/SIF/sid7__assembly.sif
new file mode 100644
index 0000000..c8d3940
--- /dev/null
+++ b/Sobel/SIF/sid7__assembly.sif
diff --git a/Sobel/SIF/sid7__compile.sif b/Sobel/SIF/sid7__compile.sif
new file mode 100644
index 0000000..c8d3940
--- /dev/null
+++ b/Sobel/SIF/sid7__compile.sif
diff --git a/Sobel/SIF/sid7__dpfsm.sif b/Sobel/SIF/sid7__dpfsm.sif
new file mode 100644
index 0000000..5e754a8
--- /dev/null
+++ b/Sobel/SIF/sid7__dpfsm.sif
diff --git a/Sobel/SIF/sid7__extract.sif b/Sobel/SIF/sid7__extract.sif
new file mode 100644
index 0000000..85df462
--- /dev/null
+++ b/Sobel/SIF/sid7__extract.sif
diff --git a/Sobel/SIF/sid7__instance.sif b/Sobel/SIF/sid7__instance.sif
new file mode 100644
index 0000000..4986a35
--- /dev/null
+++ b/Sobel/SIF/sid7__instance.sif
diff --git a/Sobel/SIF/sid7__loops.sif b/Sobel/SIF/sid7__loops.sif
new file mode 100644
index 0000000..0664028
--- /dev/null
+++ b/Sobel/SIF/sid7__loops.sif
diff --git a/Sobel/SIF/sid7__memories.sif b/Sobel/SIF/sid7__memories.sif
new file mode 100644
index 0000000..efcd04c
--- /dev/null
+++ b/Sobel/SIF/sid7__memories.sif
diff --git a/Sobel/SIF/sid7__schedule.sif b/Sobel/SIF/sid7__schedule.sif
new file mode 100644
index 0000000..de590c0
--- /dev/null
+++ b/Sobel/SIF/sid7__schedule.sif
diff --git a/Sobel/SIF/sid8__allocate.sif b/Sobel/SIF/sid8__allocate.sif
new file mode 100644
index 0000000..4175ad7
--- /dev/null
+++ b/Sobel/SIF/sid8__allocate.sif
diff --git a/Sobel/SIF/sid8__analyze.il b/Sobel/SIF/sid8__analyze.il
new file mode 100644
index 0000000..12403df
--- /dev/null
+++ b/Sobel/SIF/sid8__analyze.il
diff --git a/Sobel/SIF/sid8__architect.sif b/Sobel/SIF/sid8__architect.sif
new file mode 100644
index 0000000..bcbb195
--- /dev/null
+++ b/Sobel/SIF/sid8__architect.sif
diff --git a/Sobel/SIF/sid8__assembly.sif b/Sobel/SIF/sid8__assembly.sif
new file mode 100644
index 0000000..1ce213c
--- /dev/null
+++ b/Sobel/SIF/sid8__assembly.sif
diff --git a/Sobel/SIF/sid8__compile.sif b/Sobel/SIF/sid8__compile.sif
new file mode 100644
index 0000000..1ce213c
--- /dev/null
+++ b/Sobel/SIF/sid8__compile.sif
diff --git a/Sobel/SIF/sid8__dpfsm.sif b/Sobel/SIF/sid8__dpfsm.sif
new file mode 100644
index 0000000..d40650c
--- /dev/null
+++ b/Sobel/SIF/sid8__dpfsm.sif
diff --git a/Sobel/SIF/sid8__extract.sif b/Sobel/SIF/sid8__extract.sif
new file mode 100644
index 0000000..aa916d5
--- /dev/null
+++ b/Sobel/SIF/sid8__extract.sif
diff --git a/Sobel/SIF/sid8__instance.sif b/Sobel/SIF/sid8__instance.sif
new file mode 100644
index 0000000..80e8c45
--- /dev/null
+++ b/Sobel/SIF/sid8__instance.sif
diff --git a/Sobel/SIF/sid8__loops.sif b/Sobel/SIF/sid8__loops.sif
new file mode 100644
index 0000000..c104c4f
--- /dev/null
+++ b/Sobel/SIF/sid8__loops.sif
diff --git a/Sobel/SIF/sid8__memories.sif b/Sobel/SIF/sid8__memories.sif
new file mode 100644
index 0000000..f9005dc
--- /dev/null
+++ b/Sobel/SIF/sid8__memories.sif
diff --git a/Sobel/SIF/sid8__schedule.sif b/Sobel/SIF/sid8__schedule.sif
new file mode 100644
index 0000000..82eca3b
--- /dev/null
+++ b/Sobel/SIF/sid8__schedule.sif
diff --git a/Sobel/SIF/sid9__allocate.sif b/Sobel/SIF/sid9__allocate.sif
new file mode 100644
index 0000000..ab34df1
--- /dev/null
+++ b/Sobel/SIF/sid9__allocate.sif
diff --git a/Sobel/SIF/sid9__analyze.il b/Sobel/SIF/sid9__analyze.il
new file mode 100644
index 0000000..23b51cb
--- /dev/null
+++ b/Sobel/SIF/sid9__analyze.il
diff --git a/Sobel/SIF/sid9__architect.sif b/Sobel/SIF/sid9__architect.sif
new file mode 100644
index 0000000..a715af5
--- /dev/null
+++ b/Sobel/SIF/sid9__architect.sif
diff --git a/Sobel/SIF/sid9__assembly.sif b/Sobel/SIF/sid9__assembly.sif
new file mode 100644
index 0000000..668fa75
--- /dev/null
+++ b/Sobel/SIF/sid9__assembly.sif
diff --git a/Sobel/SIF/sid9__compile.sif b/Sobel/SIF/sid9__compile.sif
new file mode 100644
index 0000000..668fa75
--- /dev/null
+++ b/Sobel/SIF/sid9__compile.sif
diff --git a/Sobel/SIF/sid9__dpfsm.sif b/Sobel/SIF/sid9__dpfsm.sif
new file mode 100644
index 0000000..c339055
--- /dev/null
+++ b/Sobel/SIF/sid9__dpfsm.sif
diff --git a/Sobel/SIF/sid9__extract.sif b/Sobel/SIF/sid9__extract.sif
new file mode 100644
index 0000000..0842fed
--- /dev/null
+++ b/Sobel/SIF/sid9__extract.sif
diff --git a/Sobel/SIF/sid9__instance.sif b/Sobel/SIF/sid9__instance.sif
new file mode 100644
index 0000000..ad25f32
--- /dev/null
+++ b/Sobel/SIF/sid9__instance.sif
diff --git a/Sobel/SIF/sid9__loops.sif b/Sobel/SIF/sid9__loops.sif
new file mode 100644
index 0000000..6713377
--- /dev/null
+++ b/Sobel/SIF/sid9__loops.sif
diff --git a/Sobel/SIF/sid9__memories.sif b/Sobel/SIF/sid9__memories.sif
new file mode 100644
index 0000000..856b7bf
--- /dev/null
+++ b/Sobel/SIF/sid9__memories.sif
diff --git a/Sobel/SIF/sid9__schedule.sif b/Sobel/SIF/sid9__schedule.sif
new file mode 100644
index 0000000..6d84627
--- /dev/null
+++ b/Sobel/SIF/sid9__schedule.sif
diff --git a/Sobel/Sobel Quartus/db/add_sub_dfh.tdf b/Sobel/Sobel Quartus/db/add_sub_dfh.tdf
new file mode 100644
index 0000000..95c127d
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/add_sub_dfh.tdf
@@ -0,0 +1,31 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone III" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=13 ONE_INPUT_IS_CONSTANT="YES" dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = lut 13 
+SUBDESIGN add_sub_dfh
+( 
+	dataa[12..0]	:	input;
+	datab[12..0]	:	input;
+	result[12..0]	:	output;
+) 
+BEGIN 
+	result[] = dataa[] + datab[];
+END;
+--VALID FILE
diff --git a/Sobel/Sobel Quartus/db/add_sub_gfh.tdf b/Sobel/Sobel Quartus/db/add_sub_gfh.tdf
new file mode 100644
index 0000000..29d5762
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/add_sub_gfh.tdf
@@ -0,0 +1,35 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone III" LPM_PIPELINE=0 LPM_REPRESENTATION="SIGNED" LPM_WIDTH=13 ONE_INPUT_IS_CONSTANT="NO" cin dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = lut 13 
+SUBDESIGN add_sub_gfh
+( 
+	cin	:	input;
+	dataa[12..0]	:	input;
+	datab[12..0]	:	input;
+	result[12..0]	:	output;
+) 
+VARIABLE
+	result_int[13..0]	:	WIRE;
+BEGIN 
+	result_int[] = (dataa[], cin) + (datab[], cin);
+	result[] = result_int[13..1];
+END;
+--VALID FILE
diff --git a/Sobel/Sobel Quartus/db/add_sub_hfh.tdf b/Sobel/Sobel Quartus/db/add_sub_hfh.tdf
new file mode 100644
index 0000000..758e702
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/add_sub_hfh.tdf
@@ -0,0 +1,31 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone III" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=17 ONE_INPUT_IS_CONSTANT="YES" dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = lut 17 
+SUBDESIGN add_sub_hfh
+( 
+	dataa[16..0]	:	input;
+	datab[16..0]	:	input;
+	result[16..0]	:	output;
+) 
+BEGIN 
+	result[] = dataa[] + datab[];
+END;
+--VALID FILE
diff --git a/Sobel/Sobel Quartus/db/logic_util_heursitic.dat b/Sobel/Sobel Quartus/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..9afe0af
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/logic_util_heursitic.dat
diff --git a/Sobel/Sobel Quartus/db/prev_cmp_sobel.qmsg b/Sobel/Sobel Quartus/db/prev_cmp_sobel.qmsg
new file mode 100644
index 0000000..29e061f
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/prev_cmp_sobel.qmsg
@@ -0,0 +1,156 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1457454100457 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457454100462 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:21:39 2016 " "Processing started: Tue Mar 08 16:21:39 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457454100462 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1457454100462 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sobel -c sobel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sobel -c sobel" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1457454100462 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1457454102791 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "//icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel.v12/rtl_mgc_ioport.v 20 20 " "Found 20 design units, including 20 entities, in source file //icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel.v12/rtl_mgc_ioport.v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_in_wire " "Found entity 1: mgc_in_wire" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 13 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_in_wire_en " "Found entity 2: mgc_in_wire_en" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_in_wire_wait " "Found entity 3: mgc_in_wire_wait" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_chan_in " "Found entity 4: mgc_chan_in" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 72 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_stdreg " "Found entity 5: mgc_out_stdreg" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 109 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_stdreg_en " "Found entity 6: mgc_out_stdreg_en" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 125 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_out_stdreg_wait " "Found entity 7: mgc_out_stdreg_wait" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 145 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "8 mgc_out_prereg_en " "Found entity 8: mgc_out_prereg_en" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 169 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "9 mgc_inout_stdreg_en " "Found entity 9: mgc_inout_stdreg_en" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 191 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "10 hid_tribuf " "Found entity 10: hid_tribuf" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 217 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "11 mgc_inout_stdreg_wait " "Found entity 11: mgc_inout_stdreg_wait" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 229 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "12 mgc_inout_buf_wait " "Found entity 12: mgc_inout_buf_wait" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 269 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "13 mgc_inout_fifo_wait " "Found entity 13: mgc_inout_fifo_wait" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 339 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "14 mgc_io_sync " "Found entity 14: mgc_io_sync" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 419 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "15 mgc_bsync_rdy " "Found entity 15: mgc_bsync_rdy" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 428 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "16 mgc_bsync_vld " "Found entity 16: mgc_bsync_vld" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 443 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "17 mgc_bsync_rv " "Found entity 17: mgc_bsync_rv" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 458 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "18 mgc_sync " "Found entity 18: mgc_sync" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 479 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "19 funccall_inout " "Found entity 19: funccall_inout" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 498 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "20 modulario_en_in " "Found entity 20: modulario_en_in" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 526 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""}
+{ "Warning" "WSGN_SEARCH_FILE" "sobel.v 2 2 " "Using design file sobel.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sobel_core " "Found entity 1: sobel_core" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454106833 ""} { "Info" "ISGN_ENTITY_NAME" "2 sobel " "Found entity 2: sobel" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1573 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454106833 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1457454106833 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "sobel " "Elaborating entity \"sobel\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1457454106866 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire mgc_in_wire:vin_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"mgc_in_wire:vin_rsc_mgc_in_wire\"" {  } { { "sobel.v" "vin_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1593 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454107431 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_out_stdreg mgc_out_stdreg:vout_rsc_mgc_out_stdreg " "Elaborating entity \"mgc_out_stdreg\" for hierarchy \"mgc_out_stdreg:vout_rsc_mgc_out_stdreg\"" {  } { { "sobel.v" "vout_rsc_mgc_out_stdreg" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1598 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454107609 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sobel_core sobel_core:sobel_core_inst " "Elaborating entity \"sobel_core\" for hierarchy \"sobel_core:sobel_core_inst\"" {  } { { "sobel.v" "sobel_core_inst" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1605 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454107701 ""}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "9 " "Inferred 9 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult0\"" {  } { { "sobel.v" "Mult0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult1\"" {  } { { "sobel.v" "Mult1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult7 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult7\"" {  } { { "sobel.v" "Mult7" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult5 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult5\"" {  } { { "sobel.v" "Mult5" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult2 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult2\"" {  } { { "sobel.v" "Mult2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult3 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult3\"" {  } { { "sobel.v" "Mult3" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult6 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult6\"" {  } { { "sobel.v" "Mult6" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult4 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult4\"" {  } { { "sobel.v" "Mult4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult8 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult8\"" {  } { { "sobel.v" "Mult8" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 784 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1457454109046 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109318 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 11 " "Parameter \"LPM_WIDTHP\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 11 " "Parameter \"LPM_WIDTHR\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454109325 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109548 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109693 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult0\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109848 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109920 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 3 " "Parameter \"LPM_WIDTHA\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 6 " "Parameter \"LPM_WIDTHB\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 9 " "Parameter \"LPM_WIDTHP\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 9 " "Parameter \"LPM_WIDTHR\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454109922 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109944 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109960 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult1\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109977 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 13 " "Parameter \"LPM_WIDTHB\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 15 " "Parameter \"LPM_WIDTHP\" = \"15\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 15 " "Parameter \"LPM_WIDTHR\" = \"15\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110056 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110090 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110113 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult7\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110133 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 13 " "Parameter \"LPM_WIDTHP\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 13 " "Parameter \"LPM_WIDTHR\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110207 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110255 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110280 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult5\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110312 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 14 " "Parameter \"LPM_WIDTHB\" = \"14\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 16 " "Parameter \"LPM_WIDTHP\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 16 " "Parameter \"LPM_WIDTHR\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110367 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110399 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110432 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult2\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110466 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 5 " "Parameter \"LPM_WIDTHB\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 9 " "Parameter \"LPM_WIDTHP\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 9 " "Parameter \"LPM_WIDTHR\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110541 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110584 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110603 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 3 " "Parameter \"LPM_WIDTHA\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 7 " "Parameter \"LPM_WIDTHB\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 10 " "Parameter \"LPM_WIDTHP\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 10 " "Parameter \"LPM_WIDTHR\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110696 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110756 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110815 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult6\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110848 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 7 " "Parameter \"LPM_WIDTHB\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 11 " "Parameter \"LPM_WIDTHP\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 11 " "Parameter \"LPM_WIDTHR\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110915 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110956 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110985 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1457454112691 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1457454114662 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454114662 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "2188 " "Implemented 2188 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "93 " "Implemented 93 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1457454115182 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1457454115182 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2065 " "Implemented 2065 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1457454115182 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1457454115182 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "499 " "Peak virtual memory: 499 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454115376 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:21:55 2016 " "Processing ended: Tue Mar 08 16:21:55 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454115376 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454115376 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454115376 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457454115376 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1457454119614 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457454119629 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:21:57 2016 " "Processing started: Tue Mar 08 16:21:57 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457454119629 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1457454119629 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off sobel -c sobel " "Command: quartus_fit --read_settings_files=off --write_settings_files=off sobel -c sobel" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1457454119634 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1457454119714 ""}
+{ "Info" "0" "" "Project  = sobel" {  } {  } 0 0 "Project  = sobel" 0 0 "Fitter" 0 0 1457454119714 ""}
+{ "Info" "0" "" "Revision = sobel" {  } {  } 0 0 "Revision = sobel" 0 0 "Fitter" 0 0 1457454119715 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1457454121042 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "sobel EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"sobel\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1457454121441 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457454121498 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457454121499 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457454121499 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1457454121600 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457454121802 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457454121802 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457454121802 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1457454121802 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4364 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4366 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4368 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4370 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4372 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1457454121811 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1457454121816 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "123 123 " "No exact pin location assignment(s) for 123 pins of 123 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[0\] " "Pin vout_rsc_z\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[0] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 107 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[1\] " "Pin vout_rsc_z\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[1] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 108 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[2\] " "Pin vout_rsc_z\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[2] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 109 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[3\] " "Pin vout_rsc_z\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[3] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 110 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[4\] " "Pin vout_rsc_z\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[4] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 111 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[5\] " "Pin vout_rsc_z\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[5] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 112 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[6\] " "Pin vout_rsc_z\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[6] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 113 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[7\] " "Pin vout_rsc_z\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[7] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 114 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[8\] " "Pin vout_rsc_z\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[8] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 115 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[9\] " "Pin vout_rsc_z\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[9] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 116 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[10\] " "Pin vout_rsc_z\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[10] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 117 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[11\] " "Pin vout_rsc_z\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[11] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 118 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[12\] " "Pin vout_rsc_z\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[12] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 119 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[13\] " "Pin vout_rsc_z\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[13] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 120 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[14\] " "Pin vout_rsc_z\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[14] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 121 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[15\] " "Pin vout_rsc_z\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[15] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 122 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[16\] " "Pin vout_rsc_z\[16\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[16] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 123 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[17\] " "Pin vout_rsc_z\[17\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[17] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 124 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[18\] " "Pin vout_rsc_z\[18\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[18] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 125 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[19\] " "Pin vout_rsc_z\[19\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[19] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 126 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[20\] " "Pin vout_rsc_z\[20\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[20] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 127 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[21\] " "Pin vout_rsc_z\[21\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[21] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 128 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[22\] " "Pin vout_rsc_z\[22\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[22] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 129 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[23\] " "Pin vout_rsc_z\[23\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[23] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 130 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[24\] " "Pin vout_rsc_z\[24\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[24] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 131 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[25\] " "Pin vout_rsc_z\[25\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[25] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 132 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[26\] " "Pin vout_rsc_z\[26\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[26] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 133 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[27\] " "Pin vout_rsc_z\[27\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[27] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 134 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[28\] " "Pin vout_rsc_z\[28\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[28] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 135 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[29\] " "Pin vout_rsc_z\[29\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[29] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 136 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Pin clk not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clk } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1578 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 137 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "arst_n " "Pin arst_n not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { arst_n } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1580 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { arst_n } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 139 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "en " "Pin en not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { en } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1579 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 138 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[57\] " "Pin vin_rsc_z\[57\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[57] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[57] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 74 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[56\] " "Pin vin_rsc_z\[56\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[56] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[56] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 73 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[55\] " "Pin vin_rsc_z\[55\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[55] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[55] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 72 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[54\] " "Pin vin_rsc_z\[54\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[54] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[54] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 71 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[53\] " "Pin vin_rsc_z\[53\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[53] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[53] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 70 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[52\] " "Pin vin_rsc_z\[52\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[52] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[52] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 69 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[51\] " "Pin vin_rsc_z\[51\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[51] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[51] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 68 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[50\] " "Pin vin_rsc_z\[50\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[50] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[50] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 67 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[47\] " "Pin vin_rsc_z\[47\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[47] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[47] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 64 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[37\] " "Pin vin_rsc_z\[37\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[37] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[37] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 54 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[46\] " "Pin vin_rsc_z\[46\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[46] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[46] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 63 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[36\] " "Pin vin_rsc_z\[36\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[36] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[36] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 53 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[45\] " "Pin vin_rsc_z\[45\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[45] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[45] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 62 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[35\] " "Pin vin_rsc_z\[35\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[35] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[35] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 52 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[44\] " "Pin vin_rsc_z\[44\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[44] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[44] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 61 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[34\] " "Pin vin_rsc_z\[34\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[34] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[34] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 51 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[43\] " "Pin vin_rsc_z\[43\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[43] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[43] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 60 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[33\] " "Pin vin_rsc_z\[33\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[33] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 50 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[42\] " "Pin vin_rsc_z\[42\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[42] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[42] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 59 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[32\] " "Pin vin_rsc_z\[32\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[32] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 49 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[41\] " "Pin vin_rsc_z\[41\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[41] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[41] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 58 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[31\] " "Pin vin_rsc_z\[31\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[31] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 48 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[40\] " "Pin vin_rsc_z\[40\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[40] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[40] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 57 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[30\] " "Pin vin_rsc_z\[30\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[30] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 47 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[78\] " "Pin vin_rsc_z\[78\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[78] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[78] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 95 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[68\] " "Pin vin_rsc_z\[68\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[68] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[68] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 85 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[77\] " "Pin vin_rsc_z\[77\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[77] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[77] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 94 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[67\] " "Pin vin_rsc_z\[67\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[67] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[67] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 84 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[76\] " "Pin vin_rsc_z\[76\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[76] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[76] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 93 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[66\] " "Pin vin_rsc_z\[66\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[66] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[66] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 83 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[75\] " "Pin vin_rsc_z\[75\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[75] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[75] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 92 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[65\] " "Pin vin_rsc_z\[65\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[65] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[65] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 82 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[74\] " "Pin vin_rsc_z\[74\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[74] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[74] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 91 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[64\] " "Pin vin_rsc_z\[64\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[64] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[64] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 81 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[73\] " "Pin vin_rsc_z\[73\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[73] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[73] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 90 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[63\] " "Pin vin_rsc_z\[63\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[63] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[63] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 80 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[72\] " "Pin vin_rsc_z\[72\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[72] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[72] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 89 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[62\] " "Pin vin_rsc_z\[62\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[62] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[62] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 79 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[71\] " "Pin vin_rsc_z\[71\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[71] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[71] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 88 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[61\] " "Pin vin_rsc_z\[61\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[61] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[61] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 78 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[70\] " "Pin vin_rsc_z\[70\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[70] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[70] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 87 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[60\] " "Pin vin_rsc_z\[60\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[60] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[60] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 77 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[88\] " "Pin vin_rsc_z\[88\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[88] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[88] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 105 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[87\] " "Pin vin_rsc_z\[87\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[87] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[87] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 104 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[86\] " "Pin vin_rsc_z\[86\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[86] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[86] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 103 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[85\] " "Pin vin_rsc_z\[85\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[85] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[85] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 102 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[84\] " "Pin vin_rsc_z\[84\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[84] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[84] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 101 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[83\] " "Pin vin_rsc_z\[83\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[83] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[83] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 100 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[82\] " "Pin vin_rsc_z\[82\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[82] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[82] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 99 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[81\] " "Pin vin_rsc_z\[81\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[81] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[81] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 98 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[80\] " "Pin vin_rsc_z\[80\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[80] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[80] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 97 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[8\] " "Pin vin_rsc_z\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[8] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 25 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[7\] " "Pin vin_rsc_z\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[7] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 24 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[6\] " "Pin vin_rsc_z\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[6] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 23 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[5\] " "Pin vin_rsc_z\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[5] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 22 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[4\] " "Pin vin_rsc_z\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[4] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 21 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[3\] " "Pin vin_rsc_z\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[3] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 20 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[2\] " "Pin vin_rsc_z\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[2] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 19 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[1\] " "Pin vin_rsc_z\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[1] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 18 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[0\] " "Pin vin_rsc_z\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[0] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 17 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[28\] " "Pin vin_rsc_z\[28\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[28] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 45 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[18\] " "Pin vin_rsc_z\[18\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[18] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 35 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[27\] " "Pin vin_rsc_z\[27\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[27] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 44 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[17\] " "Pin vin_rsc_z\[17\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[17] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 34 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[26\] " "Pin vin_rsc_z\[26\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[26] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 43 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[16\] " "Pin vin_rsc_z\[16\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[16] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 33 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[25\] " "Pin vin_rsc_z\[25\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[25] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 42 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[15\] " "Pin vin_rsc_z\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[15] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 32 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[24\] " "Pin vin_rsc_z\[24\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[24] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 41 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[14\] " "Pin vin_rsc_z\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[14] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 31 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[23\] " "Pin vin_rsc_z\[23\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[23] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 40 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[13\] " "Pin vin_rsc_z\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[13] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 30 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[22\] " "Pin vin_rsc_z\[22\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[22] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 39 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[12\] " "Pin vin_rsc_z\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[12] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 29 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[21\] " "Pin vin_rsc_z\[21\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[21] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 38 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[11\] " "Pin vin_rsc_z\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[11] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 28 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[20\] " "Pin vin_rsc_z\[20\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[20] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 37 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[10\] " "Pin vin_rsc_z\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[10] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 27 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[9\] " "Pin vin_rsc_z\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[9] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 26 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[29\] " "Pin vin_rsc_z\[29\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[29] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 46 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[19\] " "Pin vin_rsc_z\[19\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[19] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 36 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[79\] " "Pin vin_rsc_z\[79\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[79] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[79] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 96 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[69\] " "Pin vin_rsc_z\[69\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[69] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[69] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 86 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[89\] " "Pin vin_rsc_z\[89\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[89] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[89] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 106 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[59\] " "Pin vin_rsc_z\[59\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[59] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[59] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 76 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[58\] " "Pin vin_rsc_z\[58\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[58] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[58] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 75 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[49\] " "Pin vin_rsc_z\[49\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[49] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[49] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 66 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[39\] " "Pin vin_rsc_z\[39\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[39] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[39] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 56 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[48\] " "Pin vin_rsc_z\[48\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[48] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[48] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 65 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[38\] " "Pin vin_rsc_z\[38\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[38] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[38] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 55 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1457454122506 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "sobel.sdc " "Synopsys Design Constraints File file not found: 'sobel.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1457454123211 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1457454123214 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1457454123232 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1457454123235 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1457454123241 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN G2 (CLK0, DIFFCLK_0p)) " "Automatically promoted node clk~input (placed in PIN G2 (CLK0, DIFFCLK_0p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454123323 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1578 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4267 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454123323 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "arst_n~input (placed in PIN G1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node arst_n~input (placed in PIN G1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454123326 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1580 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { arst_n~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4268 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454123326 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1457454123973 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1457454123976 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1457454123979 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1457454123983 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1457454123987 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1457454123990 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1457454123993 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1457454123997 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1457454124047 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1457454124053 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1457454124053 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "121 unused 2.5V 91 30 0 " "Number of I/O pins in group: 121 (unused VREF, 2.5V VCCIO, 91 input, 30 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1457454124065 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1457454124065 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1457454124065 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 6 27 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 6 total pin(s) used --  27 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1457454124070 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1457454124070 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454124156 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1457454125133 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454125463 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1457454125477 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1457454128060 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454128062 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1457454128891 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 " "Router estimated average interconnect usage is 3% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "15 X21_Y10 X30_Y19 " "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19" {  } { { "loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} 21 10 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1457454129768 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1457454129768 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454131138 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1457454131144 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1457454131144 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.87 " "Total time spent on timing analysis during the Fitter is 0.87 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1457454131183 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1457454131274 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1457454131732 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1457454131806 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1457454132115 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454132876 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/output_files/sobel.fit.smsg " "Generated suppressed messages file /EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/output_files/sobel.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1457454133803 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1146 " "Peak virtual memory: 1146 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454135965 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:22:15 2016 " "Processing ended: Tue Mar 08 16:22:15 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454135965 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454135965 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454135965 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1457454135965 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1457454142874 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457454142879 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:22:22 2016 " "Processing started: Tue Mar 08 16:22:22 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457454142879 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1457454142879 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off sobel -c sobel " "Command: quartus_asm --read_settings_files=off --write_settings_files=off sobel -c sobel" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1457454142879 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1457454144620 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1457454144661 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "441 " "Peak virtual memory: 441 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454145417 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:22:25 2016 " "Processing ended: Tue Mar 08 16:22:25 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454145417 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454145417 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454145417 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1457454145417 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1457454146313 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1457454147871 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457454147881 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:22:26 2016 " "Processing started: Tue Mar 08 16:22:26 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457454147881 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1457454147881 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta sobel -c sobel " "Command: quartus_sta sobel -c sobel" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1457454147884 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1457454147941 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1457454149057 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457454149060 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457454149107 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457454149108 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "sobel.sdc " "Synopsys Design Constraints File file not found: 'sobel.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1457454149748 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1457454149751 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1457454149764 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1457454149764 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1457454149784 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1457454149787 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1457454149805 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1457454149884 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457454150090 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457454150090 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -21.345 " "Worst-case setup slack is -21.345" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150125 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150125 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -21.345     -1510.709 clk  " "  -21.345     -1510.709 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150125 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454150125 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.516 " "Worst-case hold slack is 0.516" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150163 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150163 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.516         0.000 clk  " "    0.516         0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150163 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454150163 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454150196 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454150226 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000      -287.000 clk  " "   -3.000      -287.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150253 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454150253 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1457454150501 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1457454150526 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1457454151095 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151302 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457454151423 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457454151423 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.828 " "Worst-case setup slack is -18.828" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151479 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151479 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -18.828     -1326.336 clk  " "  -18.828     -1326.336 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151479 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454151479 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.466 " "Worst-case hold slack is 0.466" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.466         0.000 clk  " "    0.466         0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151548 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454151548 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454151583 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454151618 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000      -287.000 clk  " "   -3.000      -287.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151673 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454151673 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1457454152064 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152466 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457454152469 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457454152469 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -11.400 " "Worst-case setup slack is -11.400" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -11.400      -781.716 clk  " "  -11.400      -781.716 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152492 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454152492 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.268 " "Worst-case hold slack is 0.268" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.268         0.000 clk  " "    0.268         0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152523 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454152523 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454152550 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454152581 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152610 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152610 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000      -303.956 clk  " "   -3.000      -303.956 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152610 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454152610 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1457454153329 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1457454153339 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "522 " "Peak virtual memory: 522 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454153827 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:22:33 2016 " "Processing ended: Tue Mar 08 16:22:33 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454153827 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454153827 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454153827 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457454153827 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 8 s " "Quartus II Full Compilation was successful. 0 errors, 8 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457454159451 ""}
diff --git a/Sobel/Sobel Quartus/db/sobel.(0).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(0).cnf.cdb
new file mode 100644
index 0000000..5a0ee9e
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(0).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(0).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(0).cnf.hdb
new file mode 100644
index 0000000..9ccee7c
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(0).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(1).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(1).cnf.cdb
new file mode 100644
index 0000000..0c027b1
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(1).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(1).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(1).cnf.hdb
new file mode 100644
index 0000000..821304c
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(1).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(10).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(10).cnf.cdb
new file mode 100644
index 0000000..4904560
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(10).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(10).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(10).cnf.hdb
new file mode 100644
index 0000000..eee52d1
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(10).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(11).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(11).cnf.cdb
new file mode 100644
index 0000000..e296dc5
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(11).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(11).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(11).cnf.hdb
new file mode 100644
index 0000000..bceb365
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(11).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(12).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(12).cnf.cdb
new file mode 100644
index 0000000..c736f1e
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(12).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(12).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(12).cnf.hdb
new file mode 100644
index 0000000..926adfc
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(12).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(13).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(13).cnf.cdb
new file mode 100644
index 0000000..217cdef
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(13).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(13).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(13).cnf.hdb
new file mode 100644
index 0000000..b7c1305
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(13).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(14).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(14).cnf.cdb
new file mode 100644
index 0000000..0c027b1
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(14).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(14).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(14).cnf.hdb
new file mode 100644
index 0000000..4995c48
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(14).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(15).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(15).cnf.cdb
new file mode 100644
index 0000000..be07ab1
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(15).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(15).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(15).cnf.hdb
new file mode 100644
index 0000000..cc7f0f8
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(15).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(16).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(16).cnf.cdb
new file mode 100644
index 0000000..59386de
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(16).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(16).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(16).cnf.hdb
new file mode 100644
index 0000000..cc7f0f8
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(16).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(17).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(17).cnf.cdb
new file mode 100644
index 0000000..ce7a95a
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(17).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(17).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(17).cnf.hdb
new file mode 100644
index 0000000..f7bca10
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(17).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(18).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(18).cnf.cdb
new file mode 100644
index 0000000..0c7463e
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(18).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(18).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(18).cnf.hdb
new file mode 100644
index 0000000..68ce5ee
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(18).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(19).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(19).cnf.cdb
new file mode 100644
index 0000000..5e372df
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(19).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(19).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(19).cnf.hdb
new file mode 100644
index 0000000..8e8ee92
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(19).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(2).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(2).cnf.cdb
new file mode 100644
index 0000000..a919e88
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(2).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(2).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(2).cnf.hdb
new file mode 100644
index 0000000..84f0a3f
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(2).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(20).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(20).cnf.cdb
new file mode 100644
index 0000000..bafdd65
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(20).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(20).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(20).cnf.hdb
new file mode 100644
index 0000000..dc2f295
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(20).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(21).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(21).cnf.cdb
new file mode 100644
index 0000000..890f1f5
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(21).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(21).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(21).cnf.hdb
new file mode 100644
index 0000000..a9015e9
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(21).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(22).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(22).cnf.cdb
new file mode 100644
index 0000000..a85ad7c
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(22).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(22).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(22).cnf.hdb
new file mode 100644
index 0000000..a7207bd
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(22).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(23).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(23).cnf.cdb
new file mode 100644
index 0000000..2ff3dde
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(23).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(23).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(23).cnf.hdb
new file mode 100644
index 0000000..5a55a1c
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(23).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(24).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(24).cnf.cdb
new file mode 100644
index 0000000..d5cba61
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(24).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(24).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(24).cnf.hdb
new file mode 100644
index 0000000..5a55a1c
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(24).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(25).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(25).cnf.cdb
new file mode 100644
index 0000000..a1fa016
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(25).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(25).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(25).cnf.hdb
new file mode 100644
index 0000000..c127c7c
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(25).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(26).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(26).cnf.cdb
new file mode 100644
index 0000000..6ed5ecf
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(26).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(26).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(26).cnf.hdb
new file mode 100644
index 0000000..f7bca10
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(26).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(27).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(27).cnf.cdb
new file mode 100644
index 0000000..217cdef
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(27).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(27).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(27).cnf.hdb
new file mode 100644
index 0000000..b125973
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(27).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(28).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(28).cnf.cdb
new file mode 100644
index 0000000..0c027b1
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(28).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(28).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(28).cnf.hdb
new file mode 100644
index 0000000..fe2cebc
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(28).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(29).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(29).cnf.cdb
new file mode 100644
index 0000000..b3d25ad
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(29).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(29).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(29).cnf.hdb
new file mode 100644
index 0000000..10a1ca1
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(29).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(3).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(3).cnf.cdb
new file mode 100644
index 0000000..2d7ba90
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(3).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(3).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(3).cnf.hdb
new file mode 100644
index 0000000..f422a70
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(3).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(30).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(30).cnf.cdb
new file mode 100644
index 0000000..4816f3d
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(30).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(30).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(30).cnf.hdb
new file mode 100644
index 0000000..d8f989c
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(30).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(31).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(31).cnf.cdb
new file mode 100644
index 0000000..816ad98
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(31).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(31).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(31).cnf.hdb
new file mode 100644
index 0000000..8843e43
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(31).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(32).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(32).cnf.cdb
new file mode 100644
index 0000000..225bc74
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(32).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(32).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(32).cnf.hdb
new file mode 100644
index 0000000..1bf30ff
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(32).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(33).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(33).cnf.cdb
new file mode 100644
index 0000000..4189f86
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(33).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(33).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(33).cnf.hdb
new file mode 100644
index 0000000..a809e4f
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(33).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(34).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(34).cnf.cdb
new file mode 100644
index 0000000..a0d2cb6
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(34).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(34).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(34).cnf.hdb
new file mode 100644
index 0000000..d6895fc
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(34).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(35).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(35).cnf.cdb
new file mode 100644
index 0000000..b5d5ea3
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(35).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(35).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(35).cnf.hdb
new file mode 100644
index 0000000..bd512c6
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(35).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(36).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(36).cnf.cdb
new file mode 100644
index 0000000..ec30eb0
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(36).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(36).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(36).cnf.hdb
new file mode 100644
index 0000000..cb3a44d
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(36).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(37).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(37).cnf.cdb
new file mode 100644
index 0000000..4fd0e9f
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(37).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(37).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(37).cnf.hdb
new file mode 100644
index 0000000..8596ca9
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(37).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(38).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(38).cnf.cdb
new file mode 100644
index 0000000..747c488
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(38).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(38).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(38).cnf.hdb
new file mode 100644
index 0000000..14e8cf2
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(38).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(39).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(39).cnf.cdb
new file mode 100644
index 0000000..7d6d9aa
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(39).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(39).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(39).cnf.hdb
new file mode 100644
index 0000000..e122df9
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(39).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(4).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(4).cnf.cdb
new file mode 100644
index 0000000..505c0a7
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(4).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(4).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(4).cnf.hdb
new file mode 100644
index 0000000..926adfc
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(4).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(40).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(40).cnf.cdb
new file mode 100644
index 0000000..42ac66b
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(40).cnf.cdb
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--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(75).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(76).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(76).cnf.cdb
new file mode 100644
index 0000000..1325864
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(76).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(76).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(76).cnf.hdb
new file mode 100644
index 0000000..b5f7bfd
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(76).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(77).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(77).cnf.cdb
new file mode 100644
index 0000000..0a43cdf
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(77).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(77).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(77).cnf.hdb
new file mode 100644
index 0000000..3ae9b4b
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(77).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(78).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(78).cnf.cdb
new file mode 100644
index 0000000..1c3d2c1
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(78).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(78).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(78).cnf.hdb
new file mode 100644
index 0000000..11a43a9
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(78).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(79).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(79).cnf.cdb
new file mode 100644
index 0000000..b4c25db
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(79).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(79).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(79).cnf.hdb
new file mode 100644
index 0000000..b338c9f
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(79).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(8).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(8).cnf.cdb
new file mode 100644
index 0000000..c96871c
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(8).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(8).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(8).cnf.hdb
new file mode 100644
index 0000000..cf3a0da
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(8).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(80).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(80).cnf.cdb
new file mode 100644
index 0000000..50462eb
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(80).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(80).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(80).cnf.hdb
new file mode 100644
index 0000000..961a07b
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(80).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(81).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(81).cnf.cdb
new file mode 100644
index 0000000..edda266
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(81).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(81).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(81).cnf.hdb
new file mode 100644
index 0000000..a9690e9
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(81).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(82).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(82).cnf.cdb
new file mode 100644
index 0000000..2bdb1e9
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(82).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(82).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(82).cnf.hdb
new file mode 100644
index 0000000..a0dc9ad
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(82).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(83).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(83).cnf.cdb
new file mode 100644
index 0000000..754f7a1
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(83).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(83).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(83).cnf.hdb
new file mode 100644
index 0000000..b338c9f
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(83).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(84).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(84).cnf.cdb
new file mode 100644
index 0000000..217cdef
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(84).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(84).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(84).cnf.hdb
new file mode 100644
index 0000000..619363a
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(84).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(85).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(85).cnf.cdb
new file mode 100644
index 0000000..61b71c3
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(85).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(85).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(85).cnf.hdb
new file mode 100644
index 0000000..f9eb20b
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(85).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(9).cnf.cdb b/Sobel/Sobel Quartus/db/sobel.(9).cnf.cdb
new file mode 100644
index 0000000..11d8575
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(9).cnf.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.(9).cnf.hdb b/Sobel/Sobel Quartus/db/sobel.(9).cnf.hdb
new file mode 100644
index 0000000..9b5c88a
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.(9).cnf.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.ace_cmp.bpm b/Sobel/Sobel Quartus/db/sobel.ace_cmp.bpm
new file mode 100644
index 0000000..208c2e3
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.ace_cmp.bpm
diff --git a/Sobel/Sobel Quartus/db/sobel.ace_cmp.cdb b/Sobel/Sobel Quartus/db/sobel.ace_cmp.cdb
new file mode 100644
index 0000000..d898d64
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.ace_cmp.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.ace_cmp.hdb b/Sobel/Sobel Quartus/db/sobel.ace_cmp.hdb
new file mode 100644
index 0000000..da1b908
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.ace_cmp.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.asm.qmsg b/Sobel/Sobel Quartus/db/sobel.asm.qmsg
new file mode 100644
index 0000000..5bca0ac
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1457454142874 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457454142879 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:22:22 2016 " "Processing started: Tue Mar 08 16:22:22 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457454142879 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1457454142879 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off sobel -c sobel " "Command: quartus_asm --read_settings_files=off --write_settings_files=off sobel -c sobel" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1457454142879 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1457454144620 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1457454144661 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "441 " "Peak virtual memory: 441 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454145417 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:22:25 2016 " "Processing ended: Tue Mar 08 16:22:25 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454145417 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454145417 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454145417 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1457454145417 ""}
diff --git a/Sobel/Sobel Quartus/db/sobel.asm.rdb b/Sobel/Sobel Quartus/db/sobel.asm.rdb
new file mode 100644
index 0000000..361cc6a
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.asm.rdb
diff --git a/Sobel/Sobel Quartus/db/sobel.asm_labs.ddb b/Sobel/Sobel Quartus/db/sobel.asm_labs.ddb
new file mode 100644
index 0000000..393839c
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.asm_labs.ddb
diff --git a/Sobel/Sobel Quartus/db/sobel.cbx.xml b/Sobel/Sobel Quartus/db/sobel.cbx.xml
new file mode 100644
index 0000000..d759ca6
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="sobel">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/Sobel/Sobel Quartus/db/sobel.cmp.bpm b/Sobel/Sobel Quartus/db/sobel.cmp.bpm
new file mode 100644
index 0000000..208c2e3
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.cmp.bpm
diff --git a/Sobel/Sobel Quartus/db/sobel.cmp.cdb b/Sobel/Sobel Quartus/db/sobel.cmp.cdb
new file mode 100644
index 0000000..d898d64
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.cmp.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.cmp.hdb b/Sobel/Sobel Quartus/db/sobel.cmp.hdb
new file mode 100644
index 0000000..da1b908
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.cmp.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.cmp.idb b/Sobel/Sobel Quartus/db/sobel.cmp.idb
new file mode 100644
index 0000000..c6fcc43
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.cmp.idb
diff --git a/Sobel/Sobel Quartus/db/sobel.cmp.kpt b/Sobel/Sobel Quartus/db/sobel.cmp.kpt
new file mode 100644
index 0000000..e9dc0ec
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.cmp.kpt
diff --git a/Sobel/Sobel Quartus/db/sobel.cmp.logdb b/Sobel/Sobel Quartus/db/sobel.cmp.logdb
new file mode 100644
index 0000000..742e0b7
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.cmp.logdb
@@ -0,0 +1,165 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;123;0;0;123;123;0;30;0;0;93;0;30;93;0;0;0;30;0;0;0;0;0;123;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,123;123;123;123;123;0;123;123;0;0;123;93;123;123;30;123;93;30;123;123;123;93;123;123;123;123;123;0;123;123,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,vout_rsc_z[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[16],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[17],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[18],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[19],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[20],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[21],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[22],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[23],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[24],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[25],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[26],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[27],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[28],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vout_rsc_z[29],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,clk,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,arst_n,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,en,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[57],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[56],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[55],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[54],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[53],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[52],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[51],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[50],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[47],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[37],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[46],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[36],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[45],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[35],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[44],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[34],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[43],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[33],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[42],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[32],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[41],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[31],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[40],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[30],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[78],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[68],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[77],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[67],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[76],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[66],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[75],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[65],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[74],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[64],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[73],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[63],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[72],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[62],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[71],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[61],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[70],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[60],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[88],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[87],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[86],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[85],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[84],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[83],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[82],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[81],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[80],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[28],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[18],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[27],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[17],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[26],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[16],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[25],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[24],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[23],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[22],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[21],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[20],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[29],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[19],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[79],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[69],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[89],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[59],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[58],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[49],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[39],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[48],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,vin_rsc_z[38],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
diff --git a/Sobel/Sobel Quartus/db/sobel.cmp.rdb b/Sobel/Sobel Quartus/db/sobel.cmp.rdb
new file mode 100644
index 0000000..758feaf
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.cmp.rdb
diff --git a/Sobel/Sobel Quartus/db/sobel.cmp_merge.kpt b/Sobel/Sobel Quartus/db/sobel.cmp_merge.kpt
new file mode 100644
index 0000000..aa4d057
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.cmp_merge.kpt
diff --git a/Sobel/Sobel Quartus/db/sobel.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/Sobel/Sobel Quartus/db/sobel.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..c86ea3e
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/Sobel/Sobel Quartus/db/sobel.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/Sobel/Sobel Quartus/db/sobel.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..ab8d5bc
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/Sobel/Sobel Quartus/db/sobel.db_info b/Sobel/Sobel Quartus/db/sobel.db_info
new file mode 100644
index 0000000..60d28da
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Mar 08 15:39:15 2016
diff --git a/Sobel/Sobel Quartus/db/sobel.eco.cdb b/Sobel/Sobel Quartus/db/sobel.eco.cdb
new file mode 100644
index 0000000..74d5728
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.eco.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.fit.qmsg b/Sobel/Sobel Quartus/db/sobel.fit.qmsg
new file mode 100644
index 0000000..07aeade
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.fit.qmsg
@@ -0,0 +1,47 @@
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1457454121042 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "sobel EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"sobel\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1457454121441 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457454121498 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457454121499 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457454121499 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1457454121600 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457454121802 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457454121802 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457454121802 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1457454121802 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4364 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4366 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4368 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4370 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4372 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454121811 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1457454121811 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1457454121816 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "123 123 " "No exact pin location assignment(s) for 123 pins of 123 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[0\] " "Pin vout_rsc_z\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[0] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 107 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[1\] " "Pin vout_rsc_z\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[1] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 108 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[2\] " "Pin vout_rsc_z\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[2] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 109 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[3\] " "Pin vout_rsc_z\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[3] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 110 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[4\] " "Pin vout_rsc_z\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[4] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 111 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[5\] " "Pin vout_rsc_z\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[5] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 112 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[6\] " "Pin vout_rsc_z\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[6] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 113 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[7\] " "Pin vout_rsc_z\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[7] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 114 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[8\] " "Pin vout_rsc_z\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[8] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 115 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[9\] " "Pin vout_rsc_z\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[9] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 116 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[10\] " "Pin vout_rsc_z\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[10] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 117 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[11\] " "Pin vout_rsc_z\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[11] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 118 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[12\] " "Pin vout_rsc_z\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[12] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 119 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[13\] " "Pin vout_rsc_z\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[13] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 120 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[14\] " "Pin vout_rsc_z\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[14] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 121 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[15\] " "Pin vout_rsc_z\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[15] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 122 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[16\] " "Pin vout_rsc_z\[16\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[16] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 123 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[17\] " "Pin vout_rsc_z\[17\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[17] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 124 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[18\] " "Pin vout_rsc_z\[18\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[18] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 125 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[19\] " "Pin vout_rsc_z\[19\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[19] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 126 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[20\] " "Pin vout_rsc_z\[20\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[20] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 127 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[21\] " "Pin vout_rsc_z\[21\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[21] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 128 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[22\] " "Pin vout_rsc_z\[22\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[22] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 129 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[23\] " "Pin vout_rsc_z\[23\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[23] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 130 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[24\] " "Pin vout_rsc_z\[24\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[24] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 131 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[25\] " "Pin vout_rsc_z\[25\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[25] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 132 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[26\] " "Pin vout_rsc_z\[26\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[26] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 133 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[27\] " "Pin vout_rsc_z\[27\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[27] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 134 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[28\] " "Pin vout_rsc_z\[28\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[28] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 135 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vout_rsc_z\[29\] " "Pin vout_rsc_z\[29\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vout_rsc_z[29] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1577 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vout_rsc_z[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 136 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Pin clk not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clk } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1578 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 137 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "arst_n " "Pin arst_n not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { arst_n } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1580 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { arst_n } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 139 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "en " "Pin en not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { en } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1579 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 138 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[57\] " "Pin vin_rsc_z\[57\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[57] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[57] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 74 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[56\] " "Pin vin_rsc_z\[56\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[56] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[56] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 73 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[55\] " "Pin vin_rsc_z\[55\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[55] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[55] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 72 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[54\] " "Pin vin_rsc_z\[54\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[54] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[54] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 71 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[53\] " "Pin vin_rsc_z\[53\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[53] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[53] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 70 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[52\] " "Pin vin_rsc_z\[52\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[52] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[52] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 69 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[51\] " "Pin vin_rsc_z\[51\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[51] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[51] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 68 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[50\] " "Pin vin_rsc_z\[50\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[50] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[50] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 67 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[47\] " "Pin vin_rsc_z\[47\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[47] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[47] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 64 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[37\] " "Pin vin_rsc_z\[37\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[37] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[37] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 54 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[46\] " "Pin vin_rsc_z\[46\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[46] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[46] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 63 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[36\] " "Pin vin_rsc_z\[36\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[36] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[36] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 53 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[45\] " "Pin vin_rsc_z\[45\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[45] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[45] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 62 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[35\] " "Pin vin_rsc_z\[35\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[35] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[35] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 52 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[44\] " "Pin vin_rsc_z\[44\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[44] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[44] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 61 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[34\] " "Pin vin_rsc_z\[34\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[34] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[34] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 51 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[43\] " "Pin vin_rsc_z\[43\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[43] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[43] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 60 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[33\] " "Pin vin_rsc_z\[33\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[33] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 50 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[42\] " "Pin vin_rsc_z\[42\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[42] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[42] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 59 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[32\] " "Pin vin_rsc_z\[32\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[32] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 49 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[41\] " "Pin vin_rsc_z\[41\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[41] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[41] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 58 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[31\] " "Pin vin_rsc_z\[31\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[31] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 48 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[40\] " "Pin vin_rsc_z\[40\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[40] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[40] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 57 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[30\] " "Pin vin_rsc_z\[30\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[30] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 47 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[78\] " "Pin vin_rsc_z\[78\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[78] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[78] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 95 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[68\] " "Pin vin_rsc_z\[68\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[68] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[68] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 85 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[77\] " "Pin vin_rsc_z\[77\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[77] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[77] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 94 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[67\] " "Pin vin_rsc_z\[67\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[67] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[67] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 84 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[76\] " "Pin vin_rsc_z\[76\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[76] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[76] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 93 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[66\] " "Pin vin_rsc_z\[66\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[66] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[66] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 83 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[75\] " "Pin vin_rsc_z\[75\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[75] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[75] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 92 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[65\] " "Pin vin_rsc_z\[65\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[65] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[65] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 82 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[74\] " "Pin vin_rsc_z\[74\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[74] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[74] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 91 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[64\] " "Pin vin_rsc_z\[64\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[64] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[64] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 81 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[73\] " "Pin vin_rsc_z\[73\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[73] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[73] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 90 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[63\] " "Pin vin_rsc_z\[63\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[63] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[63] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 80 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[72\] " "Pin vin_rsc_z\[72\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[72] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[72] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 89 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[62\] " "Pin vin_rsc_z\[62\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[62] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[62] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 79 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[71\] " "Pin vin_rsc_z\[71\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[71] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[71] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 88 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[61\] " "Pin vin_rsc_z\[61\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[61] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[61] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 78 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[70\] " "Pin vin_rsc_z\[70\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[70] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[70] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 87 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[60\] " "Pin vin_rsc_z\[60\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[60] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[60] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 77 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[88\] " "Pin vin_rsc_z\[88\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[88] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[88] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 105 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[87\] " "Pin vin_rsc_z\[87\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[87] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[87] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 104 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[86\] " "Pin vin_rsc_z\[86\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[86] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[86] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 103 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[85\] " "Pin vin_rsc_z\[85\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[85] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[85] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 102 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[84\] " "Pin vin_rsc_z\[84\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[84] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[84] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 101 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[83\] " "Pin vin_rsc_z\[83\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[83] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[83] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 100 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[82\] " "Pin vin_rsc_z\[82\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[82] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[82] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 99 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[81\] " "Pin vin_rsc_z\[81\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[81] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[81] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 98 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[80\] " "Pin vin_rsc_z\[80\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[80] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[80] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 97 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[8\] " "Pin vin_rsc_z\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[8] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 25 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[7\] " "Pin vin_rsc_z\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[7] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 24 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[6\] " "Pin vin_rsc_z\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[6] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 23 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[5\] " "Pin vin_rsc_z\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[5] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 22 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[4\] " "Pin vin_rsc_z\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[4] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 21 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[3\] " "Pin vin_rsc_z\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[3] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 20 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[2\] " "Pin vin_rsc_z\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[2] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 19 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[1\] " "Pin vin_rsc_z\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[1] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 18 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[0\] " "Pin vin_rsc_z\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[0] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 17 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[28\] " "Pin vin_rsc_z\[28\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[28] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 45 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[18\] " "Pin vin_rsc_z\[18\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[18] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 35 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[27\] " "Pin vin_rsc_z\[27\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[27] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 44 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[17\] " "Pin vin_rsc_z\[17\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[17] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 34 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[26\] " "Pin vin_rsc_z\[26\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[26] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 43 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[16\] " "Pin vin_rsc_z\[16\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[16] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 33 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[25\] " "Pin vin_rsc_z\[25\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[25] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 42 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[15\] " "Pin vin_rsc_z\[15\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[15] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 32 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[24\] " "Pin vin_rsc_z\[24\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[24] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 41 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[14\] " "Pin vin_rsc_z\[14\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[14] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 31 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[23\] " "Pin vin_rsc_z\[23\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[23] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 40 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[13\] " "Pin vin_rsc_z\[13\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[13] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 30 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[22\] " "Pin vin_rsc_z\[22\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[22] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 39 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[12\] " "Pin vin_rsc_z\[12\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[12] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 29 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[21\] " "Pin vin_rsc_z\[21\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[21] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 38 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[11\] " "Pin vin_rsc_z\[11\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[11] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 28 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[20\] " "Pin vin_rsc_z\[20\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[20] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 37 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[10\] " "Pin vin_rsc_z\[10\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[10] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 27 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[9\] " "Pin vin_rsc_z\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[9] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 26 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[29\] " "Pin vin_rsc_z\[29\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[29] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 46 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[19\] " "Pin vin_rsc_z\[19\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[19] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 36 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[79\] " "Pin vin_rsc_z\[79\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[79] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[79] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 96 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[69\] " "Pin vin_rsc_z\[69\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[69] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[69] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 86 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[89\] " "Pin vin_rsc_z\[89\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[89] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[89] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 106 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[59\] " "Pin vin_rsc_z\[59\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[59] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[59] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 76 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[58\] " "Pin vin_rsc_z\[58\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[58] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[58] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 75 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[49\] " "Pin vin_rsc_z\[49\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[49] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[49] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 66 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[39\] " "Pin vin_rsc_z\[39\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[39] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[39] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 56 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[48\] " "Pin vin_rsc_z\[48\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[48] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[48] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 65 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "vin_rsc_z\[38\] " "Pin vin_rsc_z\[38\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { vin_rsc_z[38] } } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1576 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { vin_rsc_z[38] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 55 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454122506 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1457454122506 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "sobel.sdc " "Synopsys Design Constraints File file not found: 'sobel.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1457454123211 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1457454123214 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1457454123232 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1457454123235 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1457454123241 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN G2 (CLK0, DIFFCLK_0p)) " "Automatically promoted node clk~input (placed in PIN G2 (CLK0, DIFFCLK_0p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454123323 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1578 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4267 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454123323 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "arst_n~input (placed in PIN G1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node arst_n~input (placed in PIN G1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454123326 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1580 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { arst_n~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 0 { 0 ""} 0 4268 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454123326 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1457454123973 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1457454123976 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1457454123979 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1457454123983 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1457454123987 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1457454123990 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1457454123993 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1457454123997 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1457454124047 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1457454124053 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1457454124053 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "121 unused 2.5V 91 30 0 " "Number of I/O pins in group: 121 (unused VREF, 2.5V VCCIO, 91 input, 30 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1457454124065 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1457454124065 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1457454124065 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 6 27 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 6 total pin(s) used --  27 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454124070 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1457454124070 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1457454124070 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454124156 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1457454125133 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454125463 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1457454125477 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1457454128060 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454128062 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1457454128891 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 " "Router estimated average interconnect usage is 3% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "15 X21_Y10 X30_Y19 " "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19" {  } { { "loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} 21 10 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1457454129768 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1457454129768 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454131138 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1457454131144 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1457454131144 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.87 " "Total time spent on timing analysis during the Fitter is 0.87 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1457454131183 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1457454131274 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1457454131732 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1457454131806 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1457454132115 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454132876 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/output_files/sobel.fit.smsg " "Generated suppressed messages file /EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/output_files/sobel.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1457454133803 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1146 " "Peak virtual memory: 1146 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454135965 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:22:15 2016 " "Processing ended: Tue Mar 08 16:22:15 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454135965 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454135965 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454135965 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1457454135965 ""}
diff --git a/Sobel/Sobel Quartus/db/sobel.hier_info b/Sobel/Sobel Quartus/db/sobel.hier_info
new file mode 100644
index 0000000..d25342e
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.hier_info
@@ -0,0 +1,1481 @@
+|sobel
+vin_rsc_z[0] => vin_rsc_z[0].IN1
+vin_rsc_z[1] => vin_rsc_z[1].IN1
+vin_rsc_z[2] => vin_rsc_z[2].IN1
+vin_rsc_z[3] => vin_rsc_z[3].IN1
+vin_rsc_z[4] => vin_rsc_z[4].IN1
+vin_rsc_z[5] => vin_rsc_z[5].IN1
+vin_rsc_z[6] => vin_rsc_z[6].IN1
+vin_rsc_z[7] => vin_rsc_z[7].IN1
+vin_rsc_z[8] => vin_rsc_z[8].IN1
+vin_rsc_z[9] => vin_rsc_z[9].IN1
+vin_rsc_z[10] => vin_rsc_z[10].IN1
+vin_rsc_z[11] => vin_rsc_z[11].IN1
+vin_rsc_z[12] => vin_rsc_z[12].IN1
+vin_rsc_z[13] => vin_rsc_z[13].IN1
+vin_rsc_z[14] => vin_rsc_z[14].IN1
+vin_rsc_z[15] => vin_rsc_z[15].IN1
+vin_rsc_z[16] => vin_rsc_z[16].IN1
+vin_rsc_z[17] => vin_rsc_z[17].IN1
+vin_rsc_z[18] => vin_rsc_z[18].IN1
+vin_rsc_z[19] => vin_rsc_z[19].IN1
+vin_rsc_z[20] => vin_rsc_z[20].IN1
+vin_rsc_z[21] => vin_rsc_z[21].IN1
+vin_rsc_z[22] => vin_rsc_z[22].IN1
+vin_rsc_z[23] => vin_rsc_z[23].IN1
+vin_rsc_z[24] => vin_rsc_z[24].IN1
+vin_rsc_z[25] => vin_rsc_z[25].IN1
+vin_rsc_z[26] => vin_rsc_z[26].IN1
+vin_rsc_z[27] => vin_rsc_z[27].IN1
+vin_rsc_z[28] => vin_rsc_z[28].IN1
+vin_rsc_z[29] => vin_rsc_z[29].IN1
+vin_rsc_z[30] => vin_rsc_z[30].IN1
+vin_rsc_z[31] => vin_rsc_z[31].IN1
+vin_rsc_z[32] => vin_rsc_z[32].IN1
+vin_rsc_z[33] => vin_rsc_z[33].IN1
+vin_rsc_z[34] => vin_rsc_z[34].IN1
+vin_rsc_z[35] => vin_rsc_z[35].IN1
+vin_rsc_z[36] => vin_rsc_z[36].IN1
+vin_rsc_z[37] => vin_rsc_z[37].IN1
+vin_rsc_z[38] => vin_rsc_z[38].IN1
+vin_rsc_z[39] => vin_rsc_z[39].IN1
+vin_rsc_z[40] => vin_rsc_z[40].IN1
+vin_rsc_z[41] => vin_rsc_z[41].IN1
+vin_rsc_z[42] => vin_rsc_z[42].IN1
+vin_rsc_z[43] => vin_rsc_z[43].IN1
+vin_rsc_z[44] => vin_rsc_z[44].IN1
+vin_rsc_z[45] => vin_rsc_z[45].IN1
+vin_rsc_z[46] => vin_rsc_z[46].IN1
+vin_rsc_z[47] => vin_rsc_z[47].IN1
+vin_rsc_z[48] => vin_rsc_z[48].IN1
+vin_rsc_z[49] => vin_rsc_z[49].IN1
+vin_rsc_z[50] => vin_rsc_z[50].IN1
+vin_rsc_z[51] => vin_rsc_z[51].IN1
+vin_rsc_z[52] => vin_rsc_z[52].IN1
+vin_rsc_z[53] => vin_rsc_z[53].IN1
+vin_rsc_z[54] => vin_rsc_z[54].IN1
+vin_rsc_z[55] => vin_rsc_z[55].IN1
+vin_rsc_z[56] => vin_rsc_z[56].IN1
+vin_rsc_z[57] => vin_rsc_z[57].IN1
+vin_rsc_z[58] => vin_rsc_z[58].IN1
+vin_rsc_z[59] => vin_rsc_z[59].IN1
+vin_rsc_z[60] => vin_rsc_z[60].IN1
+vin_rsc_z[61] => vin_rsc_z[61].IN1
+vin_rsc_z[62] => vin_rsc_z[62].IN1
+vin_rsc_z[63] => vin_rsc_z[63].IN1
+vin_rsc_z[64] => vin_rsc_z[64].IN1
+vin_rsc_z[65] => vin_rsc_z[65].IN1
+vin_rsc_z[66] => vin_rsc_z[66].IN1
+vin_rsc_z[67] => vin_rsc_z[67].IN1
+vin_rsc_z[68] => vin_rsc_z[68].IN1
+vin_rsc_z[69] => vin_rsc_z[69].IN1
+vin_rsc_z[70] => vin_rsc_z[70].IN1
+vin_rsc_z[71] => vin_rsc_z[71].IN1
+vin_rsc_z[72] => vin_rsc_z[72].IN1
+vin_rsc_z[73] => vin_rsc_z[73].IN1
+vin_rsc_z[74] => vin_rsc_z[74].IN1
+vin_rsc_z[75] => vin_rsc_z[75].IN1
+vin_rsc_z[76] => vin_rsc_z[76].IN1
+vin_rsc_z[77] => vin_rsc_z[77].IN1
+vin_rsc_z[78] => vin_rsc_z[78].IN1
+vin_rsc_z[79] => vin_rsc_z[79].IN1
+vin_rsc_z[80] => vin_rsc_z[80].IN1
+vin_rsc_z[81] => vin_rsc_z[81].IN1
+vin_rsc_z[82] => vin_rsc_z[82].IN1
+vin_rsc_z[83] => vin_rsc_z[83].IN1
+vin_rsc_z[84] => vin_rsc_z[84].IN1
+vin_rsc_z[85] => vin_rsc_z[85].IN1
+vin_rsc_z[86] => vin_rsc_z[86].IN1
+vin_rsc_z[87] => vin_rsc_z[87].IN1
+vin_rsc_z[88] => vin_rsc_z[88].IN1
+vin_rsc_z[89] => vin_rsc_z[89].IN1
+vout_rsc_z[0] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[1] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[2] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[3] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[4] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[5] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[6] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[7] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[8] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[9] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[10] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[11] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[12] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[13] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[14] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[15] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[16] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[17] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[18] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[19] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[20] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[21] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[22] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[23] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[24] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[25] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[26] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[27] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[28] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[29] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+clk => clk.IN1
+en => en.IN1
+arst_n => arst_n.IN1
+
+
+|sobel|mgc_in_wire:vin_rsc_mgc_in_wire
+d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE
+d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE
+d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE
+d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE
+d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE
+d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE
+d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE
+d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE
+d[8] <= z[8].DB_MAX_OUTPUT_PORT_TYPE
+d[9] <= z[9].DB_MAX_OUTPUT_PORT_TYPE
+d[10] <= z[10].DB_MAX_OUTPUT_PORT_TYPE
+d[11] <= z[11].DB_MAX_OUTPUT_PORT_TYPE
+d[12] <= z[12].DB_MAX_OUTPUT_PORT_TYPE
+d[13] <= z[13].DB_MAX_OUTPUT_PORT_TYPE
+d[14] <= z[14].DB_MAX_OUTPUT_PORT_TYPE
+d[15] <= z[15].DB_MAX_OUTPUT_PORT_TYPE
+d[16] <= z[16].DB_MAX_OUTPUT_PORT_TYPE
+d[17] <= z[17].DB_MAX_OUTPUT_PORT_TYPE
+d[18] <= z[18].DB_MAX_OUTPUT_PORT_TYPE
+d[19] <= z[19].DB_MAX_OUTPUT_PORT_TYPE
+d[20] <= z[20].DB_MAX_OUTPUT_PORT_TYPE
+d[21] <= z[21].DB_MAX_OUTPUT_PORT_TYPE
+d[22] <= z[22].DB_MAX_OUTPUT_PORT_TYPE
+d[23] <= z[23].DB_MAX_OUTPUT_PORT_TYPE
+d[24] <= z[24].DB_MAX_OUTPUT_PORT_TYPE
+d[25] <= z[25].DB_MAX_OUTPUT_PORT_TYPE
+d[26] <= z[26].DB_MAX_OUTPUT_PORT_TYPE
+d[27] <= z[27].DB_MAX_OUTPUT_PORT_TYPE
+d[28] <= z[28].DB_MAX_OUTPUT_PORT_TYPE
+d[29] <= z[29].DB_MAX_OUTPUT_PORT_TYPE
+d[30] <= z[30].DB_MAX_OUTPUT_PORT_TYPE
+d[31] <= z[31].DB_MAX_OUTPUT_PORT_TYPE
+d[32] <= z[32].DB_MAX_OUTPUT_PORT_TYPE
+d[33] <= z[33].DB_MAX_OUTPUT_PORT_TYPE
+d[34] <= z[34].DB_MAX_OUTPUT_PORT_TYPE
+d[35] <= z[35].DB_MAX_OUTPUT_PORT_TYPE
+d[36] <= z[36].DB_MAX_OUTPUT_PORT_TYPE
+d[37] <= z[37].DB_MAX_OUTPUT_PORT_TYPE
+d[38] <= z[38].DB_MAX_OUTPUT_PORT_TYPE
+d[39] <= z[39].DB_MAX_OUTPUT_PORT_TYPE
+d[40] <= z[40].DB_MAX_OUTPUT_PORT_TYPE
+d[41] <= z[41].DB_MAX_OUTPUT_PORT_TYPE
+d[42] <= z[42].DB_MAX_OUTPUT_PORT_TYPE
+d[43] <= z[43].DB_MAX_OUTPUT_PORT_TYPE
+d[44] <= z[44].DB_MAX_OUTPUT_PORT_TYPE
+d[45] <= z[45].DB_MAX_OUTPUT_PORT_TYPE
+d[46] <= z[46].DB_MAX_OUTPUT_PORT_TYPE
+d[47] <= z[47].DB_MAX_OUTPUT_PORT_TYPE
+d[48] <= z[48].DB_MAX_OUTPUT_PORT_TYPE
+d[49] <= z[49].DB_MAX_OUTPUT_PORT_TYPE
+d[50] <= z[50].DB_MAX_OUTPUT_PORT_TYPE
+d[51] <= z[51].DB_MAX_OUTPUT_PORT_TYPE
+d[52] <= z[52].DB_MAX_OUTPUT_PORT_TYPE
+d[53] <= z[53].DB_MAX_OUTPUT_PORT_TYPE
+d[54] <= z[54].DB_MAX_OUTPUT_PORT_TYPE
+d[55] <= z[55].DB_MAX_OUTPUT_PORT_TYPE
+d[56] <= z[56].DB_MAX_OUTPUT_PORT_TYPE
+d[57] <= z[57].DB_MAX_OUTPUT_PORT_TYPE
+d[58] <= z[58].DB_MAX_OUTPUT_PORT_TYPE
+d[59] <= z[59].DB_MAX_OUTPUT_PORT_TYPE
+d[60] <= z[60].DB_MAX_OUTPUT_PORT_TYPE
+d[61] <= z[61].DB_MAX_OUTPUT_PORT_TYPE
+d[62] <= z[62].DB_MAX_OUTPUT_PORT_TYPE
+d[63] <= z[63].DB_MAX_OUTPUT_PORT_TYPE
+d[64] <= z[64].DB_MAX_OUTPUT_PORT_TYPE
+d[65] <= z[65].DB_MAX_OUTPUT_PORT_TYPE
+d[66] <= z[66].DB_MAX_OUTPUT_PORT_TYPE
+d[67] <= z[67].DB_MAX_OUTPUT_PORT_TYPE
+d[68] <= z[68].DB_MAX_OUTPUT_PORT_TYPE
+d[69] <= z[69].DB_MAX_OUTPUT_PORT_TYPE
+d[70] <= z[70].DB_MAX_OUTPUT_PORT_TYPE
+d[71] <= z[71].DB_MAX_OUTPUT_PORT_TYPE
+d[72] <= z[72].DB_MAX_OUTPUT_PORT_TYPE
+d[73] <= z[73].DB_MAX_OUTPUT_PORT_TYPE
+d[74] <= z[74].DB_MAX_OUTPUT_PORT_TYPE
+d[75] <= z[75].DB_MAX_OUTPUT_PORT_TYPE
+d[76] <= z[76].DB_MAX_OUTPUT_PORT_TYPE
+d[77] <= z[77].DB_MAX_OUTPUT_PORT_TYPE
+d[78] <= z[78].DB_MAX_OUTPUT_PORT_TYPE
+d[79] <= z[79].DB_MAX_OUTPUT_PORT_TYPE
+d[80] <= z[80].DB_MAX_OUTPUT_PORT_TYPE
+d[81] <= z[81].DB_MAX_OUTPUT_PORT_TYPE
+d[82] <= z[82].DB_MAX_OUTPUT_PORT_TYPE
+d[83] <= z[83].DB_MAX_OUTPUT_PORT_TYPE
+d[84] <= z[84].DB_MAX_OUTPUT_PORT_TYPE
+d[85] <= z[85].DB_MAX_OUTPUT_PORT_TYPE
+d[86] <= z[86].DB_MAX_OUTPUT_PORT_TYPE
+d[87] <= z[87].DB_MAX_OUTPUT_PORT_TYPE
+d[88] <= z[88].DB_MAX_OUTPUT_PORT_TYPE
+d[89] <= z[89].DB_MAX_OUTPUT_PORT_TYPE
+z[0] => d[0].DATAIN
+z[1] => d[1].DATAIN
+z[2] => d[2].DATAIN
+z[3] => d[3].DATAIN
+z[4] => d[4].DATAIN
+z[5] => d[5].DATAIN
+z[6] => d[6].DATAIN
+z[7] => d[7].DATAIN
+z[8] => d[8].DATAIN
+z[9] => d[9].DATAIN
+z[10] => d[10].DATAIN
+z[11] => d[11].DATAIN
+z[12] => d[12].DATAIN
+z[13] => d[13].DATAIN
+z[14] => d[14].DATAIN
+z[15] => d[15].DATAIN
+z[16] => d[16].DATAIN
+z[17] => d[17].DATAIN
+z[18] => d[18].DATAIN
+z[19] => d[19].DATAIN
+z[20] => d[20].DATAIN
+z[21] => d[21].DATAIN
+z[22] => d[22].DATAIN
+z[23] => d[23].DATAIN
+z[24] => d[24].DATAIN
+z[25] => d[25].DATAIN
+z[26] => d[26].DATAIN
+z[27] => d[27].DATAIN
+z[28] => d[28].DATAIN
+z[29] => d[29].DATAIN
+z[30] => d[30].DATAIN
+z[31] => d[31].DATAIN
+z[32] => d[32].DATAIN
+z[33] => d[33].DATAIN
+z[34] => d[34].DATAIN
+z[35] => d[35].DATAIN
+z[36] => d[36].DATAIN
+z[37] => d[37].DATAIN
+z[38] => d[38].DATAIN
+z[39] => d[39].DATAIN
+z[40] => d[40].DATAIN
+z[41] => d[41].DATAIN
+z[42] => d[42].DATAIN
+z[43] => d[43].DATAIN
+z[44] => d[44].DATAIN
+z[45] => d[45].DATAIN
+z[46] => d[46].DATAIN
+z[47] => d[47].DATAIN
+z[48] => d[48].DATAIN
+z[49] => d[49].DATAIN
+z[50] => d[50].DATAIN
+z[51] => d[51].DATAIN
+z[52] => d[52].DATAIN
+z[53] => d[53].DATAIN
+z[54] => d[54].DATAIN
+z[55] => d[55].DATAIN
+z[56] => d[56].DATAIN
+z[57] => d[57].DATAIN
+z[58] => d[58].DATAIN
+z[59] => d[59].DATAIN
+z[60] => d[60].DATAIN
+z[61] => d[61].DATAIN
+z[62] => d[62].DATAIN
+z[63] => d[63].DATAIN
+z[64] => d[64].DATAIN
+z[65] => d[65].DATAIN
+z[66] => d[66].DATAIN
+z[67] => d[67].DATAIN
+z[68] => d[68].DATAIN
+z[69] => d[69].DATAIN
+z[70] => d[70].DATAIN
+z[71] => d[71].DATAIN
+z[72] => d[72].DATAIN
+z[73] => d[73].DATAIN
+z[74] => d[74].DATAIN
+z[75] => d[75].DATAIN
+z[76] => d[76].DATAIN
+z[77] => d[77].DATAIN
+z[78] => d[78].DATAIN
+z[79] => d[79].DATAIN
+z[80] => d[80].DATAIN
+z[81] => d[81].DATAIN
+z[82] => d[82].DATAIN
+z[83] => d[83].DATAIN
+z[84] => d[84].DATAIN
+z[85] => d[85].DATAIN
+z[86] => d[86].DATAIN
+z[87] => d[87].DATAIN
+z[88] => d[88].DATAIN
+z[89] => d[89].DATAIN
+
+
+|sobel|mgc_out_stdreg:vout_rsc_mgc_out_stdreg
+d[0] => z[0].DATAIN
+d[1] => z[1].DATAIN
+d[2] => z[2].DATAIN
+d[3] => z[3].DATAIN
+d[4] => z[4].DATAIN
+d[5] => z[5].DATAIN
+d[6] => z[6].DATAIN
+d[7] => z[7].DATAIN
+d[8] => z[8].DATAIN
+d[9] => z[9].DATAIN
+d[10] => z[10].DATAIN
+d[11] => z[11].DATAIN
+d[12] => z[12].DATAIN
+d[13] => z[13].DATAIN
+d[14] => z[14].DATAIN
+d[15] => z[15].DATAIN
+d[16] => z[16].DATAIN
+d[17] => z[17].DATAIN
+d[18] => z[18].DATAIN
+d[19] => z[19].DATAIN
+d[20] => z[20].DATAIN
+d[21] => z[21].DATAIN
+d[22] => z[22].DATAIN
+d[23] => z[23].DATAIN
+d[24] => z[24].DATAIN
+d[25] => z[25].DATAIN
+d[26] => z[26].DATAIN
+d[27] => z[27].DATAIN
+d[28] => z[28].DATAIN
+d[29] => z[29].DATAIN
+z[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
+z[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
+z[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
+z[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
+z[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
+z[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
+z[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE
+z[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE
+z[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE
+z[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE
+z[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE
+z[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE
+z[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE
+z[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE
+z[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE
+z[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE
+z[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE
+z[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE
+z[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE
+z[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE
+z[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE
+z[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE
+z[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE
+z[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE
+z[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE
+z[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE
+z[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE
+z[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE
+z[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE
+z[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|sobel|sobel_core:sobel_core_inst
+clk => reg_regs_regs_0_sva_cse[0].CLK
+clk => reg_regs_regs_0_sva_cse[1].CLK
+clk => reg_regs_regs_0_sva_cse[2].CLK
+clk => reg_regs_regs_0_sva_cse[3].CLK
+clk => reg_regs_regs_0_sva_cse[4].CLK
+clk => reg_regs_regs_0_sva_cse[5].CLK
+clk => reg_regs_regs_0_sva_cse[6].CLK
+clk => reg_regs_regs_0_sva_cse[7].CLK
+clk => reg_regs_regs_0_sva_cse[8].CLK
+clk => reg_regs_regs_0_sva_cse[9].CLK
+clk => reg_regs_regs_0_sva_cse[10].CLK
+clk => reg_regs_regs_0_sva_cse[11].CLK
+clk => reg_regs_regs_0_sva_cse[12].CLK
+clk => reg_regs_regs_0_sva_cse[13].CLK
+clk => reg_regs_regs_0_sva_cse[14].CLK
+clk => reg_regs_regs_0_sva_cse[15].CLK
+clk => reg_regs_regs_0_sva_cse[16].CLK
+clk => reg_regs_regs_0_sva_cse[17].CLK
+clk => reg_regs_regs_0_sva_cse[18].CLK
+clk => reg_regs_regs_0_sva_cse[19].CLK
+clk => reg_regs_regs_0_sva_cse[20].CLK
+clk => reg_regs_regs_0_sva_cse[21].CLK
+clk => reg_regs_regs_0_sva_cse[22].CLK
+clk => reg_regs_regs_0_sva_cse[23].CLK
+clk => reg_regs_regs_0_sva_cse[24].CLK
+clk => reg_regs_regs_0_sva_cse[25].CLK
+clk => reg_regs_regs_0_sva_cse[26].CLK
+clk => reg_regs_regs_0_sva_cse[27].CLK
+clk => reg_regs_regs_0_sva_cse[28].CLK
+clk => reg_regs_regs_0_sva_cse[29].CLK
+clk => reg_regs_regs_0_sva_cse[30].CLK
+clk => reg_regs_regs_0_sva_cse[31].CLK
+clk => reg_regs_regs_0_sva_cse[32].CLK
+clk => reg_regs_regs_0_sva_cse[33].CLK
+clk => reg_regs_regs_0_sva_cse[34].CLK
+clk => reg_regs_regs_0_sva_cse[35].CLK
+clk => reg_regs_regs_0_sva_cse[36].CLK
+clk => reg_regs_regs_0_sva_cse[37].CLK
+clk => reg_regs_regs_0_sva_cse[38].CLK
+clk => reg_regs_regs_0_sva_cse[39].CLK
+clk => reg_regs_regs_0_sva_cse[40].CLK
+clk => reg_regs_regs_0_sva_cse[41].CLK
+clk => reg_regs_regs_0_sva_cse[42].CLK
+clk => reg_regs_regs_0_sva_cse[43].CLK
+clk => reg_regs_regs_0_sva_cse[44].CLK
+clk => reg_regs_regs_0_sva_cse[45].CLK
+clk => reg_regs_regs_0_sva_cse[46].CLK
+clk => reg_regs_regs_0_sva_cse[47].CLK
+clk => reg_regs_regs_0_sva_cse[48].CLK
+clk => reg_regs_regs_0_sva_cse[49].CLK
+clk => reg_regs_regs_0_sva_cse[50].CLK
+clk => reg_regs_regs_0_sva_cse[51].CLK
+clk => reg_regs_regs_0_sva_cse[52].CLK
+clk => reg_regs_regs_0_sva_cse[53].CLK
+clk => reg_regs_regs_0_sva_cse[54].CLK
+clk => reg_regs_regs_0_sva_cse[55].CLK
+clk => reg_regs_regs_0_sva_cse[56].CLK
+clk => reg_regs_regs_0_sva_cse[57].CLK
+clk => reg_regs_regs_0_sva_cse[58].CLK
+clk => reg_regs_regs_0_sva_cse[59].CLK
+clk => reg_regs_regs_0_sva_cse[60].CLK
+clk => reg_regs_regs_0_sva_cse[61].CLK
+clk => reg_regs_regs_0_sva_cse[62].CLK
+clk => reg_regs_regs_0_sva_cse[63].CLK
+clk => reg_regs_regs_0_sva_cse[64].CLK
+clk => reg_regs_regs_0_sva_cse[65].CLK
+clk => reg_regs_regs_0_sva_cse[66].CLK
+clk => reg_regs_regs_0_sva_cse[67].CLK
+clk => reg_regs_regs_0_sva_cse[68].CLK
+clk => reg_regs_regs_0_sva_cse[69].CLK
+clk => reg_regs_regs_0_sva_cse[70].CLK
+clk => reg_regs_regs_0_sva_cse[71].CLK
+clk => reg_regs_regs_0_sva_cse[72].CLK
+clk => reg_regs_regs_0_sva_cse[73].CLK
+clk => reg_regs_regs_0_sva_cse[74].CLK
+clk => reg_regs_regs_0_sva_cse[75].CLK
+clk => reg_regs_regs_0_sva_cse[76].CLK
+clk => reg_regs_regs_0_sva_cse[77].CLK
+clk => reg_regs_regs_0_sva_cse[78].CLK
+clk => reg_regs_regs_0_sva_cse[79].CLK
+clk => reg_regs_regs_0_sva_cse[80].CLK
+clk => reg_regs_regs_0_sva_cse[81].CLK
+clk => reg_regs_regs_0_sva_cse[82].CLK
+clk => reg_regs_regs_0_sva_cse[83].CLK
+clk => reg_regs_regs_0_sva_cse[84].CLK
+clk => reg_regs_regs_0_sva_cse[85].CLK
+clk => reg_regs_regs_0_sva_cse[86].CLK
+clk => reg_regs_regs_0_sva_cse[87].CLK
+clk => reg_regs_regs_0_sva_cse[88].CLK
+clk => reg_regs_regs_0_sva_cse[89].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[9].CLK
+clk => main_stage_0_2.CLK
+clk => ACC1_acc_655_itm_1[0].CLK
+clk => ACC1_acc_655_itm_1[1].CLK
+clk => ACC1_acc_655_itm_1[2].CLK
+clk => ACC1_acc_655_itm_1[3].CLK
+clk => ACC1_acc_655_itm_1[4].CLK
+clk => ACC1_acc_655_itm_1[5].CLK
+clk => ACC1_acc_655_itm_1[6].CLK
+clk => ACC1_acc_655_itm_1[7].CLK
+clk => ACC1_acc_655_itm_1[8].CLK
+clk => ACC1_acc_655_itm_1[9].CLK
+clk => ACC1_acc_655_itm_1[10].CLK
+clk => ACC1_acc_655_itm_1[11].CLK
+clk => ACC1_acc_652_itm_1[0].CLK
+clk => ACC1_acc_652_itm_1[1].CLK
+clk => ACC1_acc_652_itm_1[2].CLK
+clk => ACC1_acc_652_itm_1[3].CLK
+clk => ACC1_acc_652_itm_1[4].CLK
+clk => ACC1_acc_652_itm_1[5].CLK
+clk => ACC1_acc_652_itm_1[6].CLK
+clk => ACC1_acc_652_itm_1[7].CLK
+clk => ACC1_acc_652_itm_1[8].CLK
+clk => ACC1_acc_652_itm_1[9].CLK
+clk => ACC1_acc_652_itm_1[10].CLK
+clk => ACC1_3_slc_acc_10_psp_62_itm_1.CLK
+clk => ACC1_slc_ACC1_acc_228_psp_55_itm_1.CLK
+clk => slc_acc_20_psp_1_93_itm_1.CLK
+clk => ACC1_mul_57_itm_2[0].CLK
+clk => ACC1_mul_57_itm_2[1].CLK
+clk => ACC1_mul_57_itm_1_sg2[0].CLK
+clk => ACC1_mul_57_itm_1_sg2[1].CLK
+clk => ACC1_mul_57_itm_1_sg2[2].CLK
+clk => ACC1_mul_57_itm_1_sg2[3].CLK
+clk => ACC1_mul_57_itm_1_sg2[4].CLK
+clk => ACC1_acc_661_itm_1[0].CLK
+clk => ACC1_acc_661_itm_1[1].CLK
+clk => ACC1_acc_661_itm_1[2].CLK
+clk => ACC1_acc_661_itm_1[3].CLK
+clk => ACC1_acc_661_itm_1[4].CLK
+clk => ACC1_acc_661_itm_1[5].CLK
+clk => ACC1_acc_661_itm_1[6].CLK
+clk => ACC1_acc_661_itm_1[7].CLK
+clk => ACC1_acc_661_itm_1[8].CLK
+clk => ACC1_acc_661_itm_1[9].CLK
+clk => ACC1_acc_661_itm_1[10].CLK
+clk => ACC1_acc_661_itm_1[11].CLK
+clk => ACC1_acc_661_itm_1[12].CLK
+clk => ACC1_acc_661_itm_1[13].CLK
+clk => ACC1_acc_658_itm_1[0].CLK
+clk => ACC1_acc_658_itm_1[1].CLK
+clk => ACC1_acc_658_itm_1[2].CLK
+clk => ACC1_acc_658_itm_1[3].CLK
+clk => ACC1_acc_658_itm_1[4].CLK
+clk => ACC1_acc_658_itm_1[5].CLK
+clk => ACC1_acc_658_itm_1[6].CLK
+clk => ACC1_acc_658_itm_1[7].CLK
+clk => ACC1_acc_658_itm_1[8].CLK
+clk => ACC1_acc_658_itm_1[9].CLK
+clk => ACC1_acc_658_itm_1[10].CLK
+clk => ACC1_acc_658_itm_1[11].CLK
+clk => ACC1_acc_658_itm_1[12].CLK
+clk => ACC1_acc_659_itm_1[0].CLK
+clk => ACC1_acc_659_itm_1[1].CLK
+clk => ACC1_acc_659_itm_1[2].CLK
+clk => ACC1_acc_659_itm_1[3].CLK
+clk => ACC1_acc_659_itm_1[4].CLK
+clk => ACC1_acc_659_itm_1[5].CLK
+clk => ACC1_acc_659_itm_1[6].CLK
+clk => ACC1_acc_659_itm_1[7].CLK
+clk => ACC1_acc_659_itm_1[8].CLK
+clk => ACC1_acc_659_itm_1[9].CLK
+clk => ACC1_acc_659_itm_1[10].CLK
+clk => ACC1_acc_659_itm_1[11].CLK
+clk => ACC1_acc_659_itm_1[12].CLK
+clk => vout_rsc_mgc_out_stdreg_d[0]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[1]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[2]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[3]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[4]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[5]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[6]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[7]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[8]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[9]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[10]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[11]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[12]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[13]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[14]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[15]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[16]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[17]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[18]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[19]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[20]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[21]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[22]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[23]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[24]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[25]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[26]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[27]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[28]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[29]~reg0.CLK
+en => reg_regs_regs_0_sva_cse[0].ENA
+en => vout_rsc_mgc_out_stdreg_d[29]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[28]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[27]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[26]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[25]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[24]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[23]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[22]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[21]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[20]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[19]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[18]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[17]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[16]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[15]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[14]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[13]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[12]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[11]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[10]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[9]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[8]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[7]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[6]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[5]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[4]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[3]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[2]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[1]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[0]~reg0.ENA
+en => ACC1_acc_659_itm_1[12].ENA
+en => ACC1_acc_659_itm_1[11].ENA
+en => ACC1_acc_659_itm_1[10].ENA
+en => ACC1_acc_659_itm_1[9].ENA
+en => ACC1_acc_659_itm_1[8].ENA
+en => ACC1_acc_659_itm_1[7].ENA
+en => ACC1_acc_659_itm_1[6].ENA
+en => ACC1_acc_659_itm_1[5].ENA
+en => ACC1_acc_659_itm_1[4].ENA
+en => ACC1_acc_659_itm_1[3].ENA
+en => ACC1_acc_659_itm_1[2].ENA
+en => ACC1_acc_659_itm_1[1].ENA
+en => ACC1_acc_659_itm_1[0].ENA
+en => ACC1_acc_658_itm_1[12].ENA
+en => ACC1_acc_658_itm_1[11].ENA
+en => ACC1_acc_658_itm_1[10].ENA
+en => ACC1_acc_658_itm_1[9].ENA
+en => ACC1_acc_658_itm_1[8].ENA
+en => ACC1_acc_658_itm_1[7].ENA
+en => ACC1_acc_658_itm_1[6].ENA
+en => ACC1_acc_658_itm_1[5].ENA
+en => ACC1_acc_658_itm_1[4].ENA
+en => ACC1_acc_658_itm_1[3].ENA
+en => ACC1_acc_658_itm_1[2].ENA
+en => ACC1_acc_658_itm_1[1].ENA
+en => ACC1_acc_658_itm_1[0].ENA
+en => ACC1_acc_661_itm_1[13].ENA
+en => ACC1_acc_661_itm_1[12].ENA
+en => ACC1_acc_661_itm_1[11].ENA
+en => ACC1_acc_661_itm_1[10].ENA
+en => ACC1_acc_661_itm_1[9].ENA
+en => ACC1_acc_661_itm_1[8].ENA
+en => ACC1_acc_661_itm_1[7].ENA
+en => ACC1_acc_661_itm_1[6].ENA
+en => ACC1_acc_661_itm_1[5].ENA
+en => ACC1_acc_661_itm_1[4].ENA
+en => ACC1_acc_661_itm_1[3].ENA
+en => ACC1_acc_661_itm_1[2].ENA
+en => ACC1_acc_661_itm_1[1].ENA
+en => ACC1_acc_661_itm_1[0].ENA
+en => ACC1_mul_57_itm_1_sg2[4].ENA
+en => ACC1_mul_57_itm_1_sg2[3].ENA
+en => ACC1_mul_57_itm_1_sg2[2].ENA
+en => ACC1_mul_57_itm_1_sg2[1].ENA
+en => ACC1_mul_57_itm_1_sg2[0].ENA
+en => ACC1_mul_57_itm_2[1].ENA
+en => ACC1_mul_57_itm_2[0].ENA
+en => slc_acc_20_psp_1_93_itm_1.ENA
+en => ACC1_slc_ACC1_acc_228_psp_55_itm_1.ENA
+en => ACC1_3_slc_acc_10_psp_62_itm_1.ENA
+en => ACC1_acc_652_itm_1[10].ENA
+en => ACC1_acc_652_itm_1[9].ENA
+en => ACC1_acc_652_itm_1[8].ENA
+en => ACC1_acc_652_itm_1[7].ENA
+en => ACC1_acc_652_itm_1[6].ENA
+en => ACC1_acc_652_itm_1[5].ENA
+en => ACC1_acc_652_itm_1[4].ENA
+en => ACC1_acc_652_itm_1[3].ENA
+en => ACC1_acc_652_itm_1[2].ENA
+en => ACC1_acc_652_itm_1[1].ENA
+en => ACC1_acc_652_itm_1[0].ENA
+en => ACC1_acc_655_itm_1[11].ENA
+en => ACC1_acc_655_itm_1[10].ENA
+en => ACC1_acc_655_itm_1[9].ENA
+en => ACC1_acc_655_itm_1[8].ENA
+en => ACC1_acc_655_itm_1[7].ENA
+en => ACC1_acc_655_itm_1[6].ENA
+en => ACC1_acc_655_itm_1[5].ENA
+en => ACC1_acc_655_itm_1[4].ENA
+en => ACC1_acc_655_itm_1[3].ENA
+en => ACC1_acc_655_itm_1[2].ENA
+en => ACC1_acc_655_itm_1[1].ENA
+en => ACC1_acc_655_itm_1[0].ENA
+en => main_stage_0_2.ENA
+en => regs_regs_slc_regs_regs_2_10_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[0].ENA
+en => reg_regs_regs_0_sva_cse[89].ENA
+en => reg_regs_regs_0_sva_cse[88].ENA
+en => reg_regs_regs_0_sva_cse[87].ENA
+en => reg_regs_regs_0_sva_cse[86].ENA
+en => reg_regs_regs_0_sva_cse[85].ENA
+en => reg_regs_regs_0_sva_cse[84].ENA
+en => reg_regs_regs_0_sva_cse[83].ENA
+en => reg_regs_regs_0_sva_cse[82].ENA
+en => reg_regs_regs_0_sva_cse[81].ENA
+en => reg_regs_regs_0_sva_cse[80].ENA
+en => reg_regs_regs_0_sva_cse[79].ENA
+en => reg_regs_regs_0_sva_cse[78].ENA
+en => reg_regs_regs_0_sva_cse[77].ENA
+en => reg_regs_regs_0_sva_cse[76].ENA
+en => reg_regs_regs_0_sva_cse[75].ENA
+en => reg_regs_regs_0_sva_cse[74].ENA
+en => reg_regs_regs_0_sva_cse[73].ENA
+en => reg_regs_regs_0_sva_cse[72].ENA
+en => reg_regs_regs_0_sva_cse[71].ENA
+en => reg_regs_regs_0_sva_cse[70].ENA
+en => reg_regs_regs_0_sva_cse[69].ENA
+en => reg_regs_regs_0_sva_cse[68].ENA
+en => reg_regs_regs_0_sva_cse[67].ENA
+en => reg_regs_regs_0_sva_cse[66].ENA
+en => reg_regs_regs_0_sva_cse[65].ENA
+en => reg_regs_regs_0_sva_cse[64].ENA
+en => reg_regs_regs_0_sva_cse[63].ENA
+en => reg_regs_regs_0_sva_cse[62].ENA
+en => reg_regs_regs_0_sva_cse[61].ENA
+en => reg_regs_regs_0_sva_cse[60].ENA
+en => reg_regs_regs_0_sva_cse[59].ENA
+en => reg_regs_regs_0_sva_cse[58].ENA
+en => reg_regs_regs_0_sva_cse[57].ENA
+en => reg_regs_regs_0_sva_cse[56].ENA
+en => reg_regs_regs_0_sva_cse[55].ENA
+en => reg_regs_regs_0_sva_cse[54].ENA
+en => reg_regs_regs_0_sva_cse[53].ENA
+en => reg_regs_regs_0_sva_cse[52].ENA
+en => reg_regs_regs_0_sva_cse[51].ENA
+en => reg_regs_regs_0_sva_cse[50].ENA
+en => reg_regs_regs_0_sva_cse[49].ENA
+en => reg_regs_regs_0_sva_cse[48].ENA
+en => reg_regs_regs_0_sva_cse[47].ENA
+en => reg_regs_regs_0_sva_cse[46].ENA
+en => reg_regs_regs_0_sva_cse[45].ENA
+en => reg_regs_regs_0_sva_cse[44].ENA
+en => reg_regs_regs_0_sva_cse[43].ENA
+en => reg_regs_regs_0_sva_cse[42].ENA
+en => reg_regs_regs_0_sva_cse[41].ENA
+en => reg_regs_regs_0_sva_cse[40].ENA
+en => reg_regs_regs_0_sva_cse[39].ENA
+en => reg_regs_regs_0_sva_cse[38].ENA
+en => reg_regs_regs_0_sva_cse[37].ENA
+en => reg_regs_regs_0_sva_cse[36].ENA
+en => reg_regs_regs_0_sva_cse[35].ENA
+en => reg_regs_regs_0_sva_cse[34].ENA
+en => reg_regs_regs_0_sva_cse[33].ENA
+en => reg_regs_regs_0_sva_cse[32].ENA
+en => reg_regs_regs_0_sva_cse[31].ENA
+en => reg_regs_regs_0_sva_cse[30].ENA
+en => reg_regs_regs_0_sva_cse[29].ENA
+en => reg_regs_regs_0_sva_cse[28].ENA
+en => reg_regs_regs_0_sva_cse[27].ENA
+en => reg_regs_regs_0_sva_cse[26].ENA
+en => reg_regs_regs_0_sva_cse[25].ENA
+en => reg_regs_regs_0_sva_cse[24].ENA
+en => reg_regs_regs_0_sva_cse[23].ENA
+en => reg_regs_regs_0_sva_cse[22].ENA
+en => reg_regs_regs_0_sva_cse[21].ENA
+en => reg_regs_regs_0_sva_cse[20].ENA
+en => reg_regs_regs_0_sva_cse[19].ENA
+en => reg_regs_regs_0_sva_cse[18].ENA
+en => reg_regs_regs_0_sva_cse[17].ENA
+en => reg_regs_regs_0_sva_cse[16].ENA
+en => reg_regs_regs_0_sva_cse[15].ENA
+en => reg_regs_regs_0_sva_cse[14].ENA
+en => reg_regs_regs_0_sva_cse[13].ENA
+en => reg_regs_regs_0_sva_cse[12].ENA
+en => reg_regs_regs_0_sva_cse[11].ENA
+en => reg_regs_regs_0_sva_cse[10].ENA
+en => reg_regs_regs_0_sva_cse[9].ENA
+en => reg_regs_regs_0_sva_cse[8].ENA
+en => reg_regs_regs_0_sva_cse[7].ENA
+en => reg_regs_regs_0_sva_cse[6].ENA
+en => reg_regs_regs_0_sva_cse[5].ENA
+en => reg_regs_regs_0_sva_cse[4].ENA
+en => reg_regs_regs_0_sva_cse[3].ENA
+en => reg_regs_regs_0_sva_cse[2].ENA
+en => reg_regs_regs_0_sva_cse[1].ENA
+arst_n => reg_regs_regs_0_sva_cse[0].ACLR
+arst_n => reg_regs_regs_0_sva_cse[1].ACLR
+arst_n => reg_regs_regs_0_sva_cse[2].ACLR
+arst_n => reg_regs_regs_0_sva_cse[3].ACLR
+arst_n => reg_regs_regs_0_sva_cse[4].ACLR
+arst_n => reg_regs_regs_0_sva_cse[5].ACLR
+arst_n => reg_regs_regs_0_sva_cse[6].ACLR
+arst_n => reg_regs_regs_0_sva_cse[7].ACLR
+arst_n => reg_regs_regs_0_sva_cse[8].ACLR
+arst_n => reg_regs_regs_0_sva_cse[9].ACLR
+arst_n => reg_regs_regs_0_sva_cse[10].ACLR
+arst_n => reg_regs_regs_0_sva_cse[11].ACLR
+arst_n => reg_regs_regs_0_sva_cse[12].ACLR
+arst_n => reg_regs_regs_0_sva_cse[13].ACLR
+arst_n => reg_regs_regs_0_sva_cse[14].ACLR
+arst_n => reg_regs_regs_0_sva_cse[15].ACLR
+arst_n => reg_regs_regs_0_sva_cse[16].ACLR
+arst_n => reg_regs_regs_0_sva_cse[17].ACLR
+arst_n => reg_regs_regs_0_sva_cse[18].ACLR
+arst_n => reg_regs_regs_0_sva_cse[19].ACLR
+arst_n => reg_regs_regs_0_sva_cse[20].ACLR
+arst_n => reg_regs_regs_0_sva_cse[21].ACLR
+arst_n => reg_regs_regs_0_sva_cse[22].ACLR
+arst_n => reg_regs_regs_0_sva_cse[23].ACLR
+arst_n => reg_regs_regs_0_sva_cse[24].ACLR
+arst_n => reg_regs_regs_0_sva_cse[25].ACLR
+arst_n => reg_regs_regs_0_sva_cse[26].ACLR
+arst_n => reg_regs_regs_0_sva_cse[27].ACLR
+arst_n => reg_regs_regs_0_sva_cse[28].ACLR
+arst_n => reg_regs_regs_0_sva_cse[29].ACLR
+arst_n => reg_regs_regs_0_sva_cse[30].ACLR
+arst_n => reg_regs_regs_0_sva_cse[31].ACLR
+arst_n => reg_regs_regs_0_sva_cse[32].ACLR
+arst_n => reg_regs_regs_0_sva_cse[33].ACLR
+arst_n => reg_regs_regs_0_sva_cse[34].ACLR
+arst_n => reg_regs_regs_0_sva_cse[35].ACLR
+arst_n => reg_regs_regs_0_sva_cse[36].ACLR
+arst_n => reg_regs_regs_0_sva_cse[37].ACLR
+arst_n => reg_regs_regs_0_sva_cse[38].ACLR
+arst_n => reg_regs_regs_0_sva_cse[39].ACLR
+arst_n => reg_regs_regs_0_sva_cse[40].ACLR
+arst_n => reg_regs_regs_0_sva_cse[41].ACLR
+arst_n => reg_regs_regs_0_sva_cse[42].ACLR
+arst_n => reg_regs_regs_0_sva_cse[43].ACLR
+arst_n => reg_regs_regs_0_sva_cse[44].ACLR
+arst_n => reg_regs_regs_0_sva_cse[45].ACLR
+arst_n => reg_regs_regs_0_sva_cse[46].ACLR
+arst_n => reg_regs_regs_0_sva_cse[47].ACLR
+arst_n => reg_regs_regs_0_sva_cse[48].ACLR
+arst_n => reg_regs_regs_0_sva_cse[49].ACLR
+arst_n => reg_regs_regs_0_sva_cse[50].ACLR
+arst_n => reg_regs_regs_0_sva_cse[51].ACLR
+arst_n => reg_regs_regs_0_sva_cse[52].ACLR
+arst_n => reg_regs_regs_0_sva_cse[53].ACLR
+arst_n => reg_regs_regs_0_sva_cse[54].ACLR
+arst_n => reg_regs_regs_0_sva_cse[55].ACLR
+arst_n => reg_regs_regs_0_sva_cse[56].ACLR
+arst_n => reg_regs_regs_0_sva_cse[57].ACLR
+arst_n => reg_regs_regs_0_sva_cse[58].ACLR
+arst_n => reg_regs_regs_0_sva_cse[59].ACLR
+arst_n => reg_regs_regs_0_sva_cse[60].ACLR
+arst_n => reg_regs_regs_0_sva_cse[61].ACLR
+arst_n => reg_regs_regs_0_sva_cse[62].ACLR
+arst_n => reg_regs_regs_0_sva_cse[63].ACLR
+arst_n => reg_regs_regs_0_sva_cse[64].ACLR
+arst_n => reg_regs_regs_0_sva_cse[65].ACLR
+arst_n => reg_regs_regs_0_sva_cse[66].ACLR
+arst_n => reg_regs_regs_0_sva_cse[67].ACLR
+arst_n => reg_regs_regs_0_sva_cse[68].ACLR
+arst_n => reg_regs_regs_0_sva_cse[69].ACLR
+arst_n => reg_regs_regs_0_sva_cse[70].ACLR
+arst_n => reg_regs_regs_0_sva_cse[71].ACLR
+arst_n => reg_regs_regs_0_sva_cse[72].ACLR
+arst_n => reg_regs_regs_0_sva_cse[73].ACLR
+arst_n => reg_regs_regs_0_sva_cse[74].ACLR
+arst_n => reg_regs_regs_0_sva_cse[75].ACLR
+arst_n => reg_regs_regs_0_sva_cse[76].ACLR
+arst_n => reg_regs_regs_0_sva_cse[77].ACLR
+arst_n => reg_regs_regs_0_sva_cse[78].ACLR
+arst_n => reg_regs_regs_0_sva_cse[79].ACLR
+arst_n => reg_regs_regs_0_sva_cse[80].ACLR
+arst_n => reg_regs_regs_0_sva_cse[81].ACLR
+arst_n => reg_regs_regs_0_sva_cse[82].ACLR
+arst_n => reg_regs_regs_0_sva_cse[83].ACLR
+arst_n => reg_regs_regs_0_sva_cse[84].ACLR
+arst_n => reg_regs_regs_0_sva_cse[85].ACLR
+arst_n => reg_regs_regs_0_sva_cse[86].ACLR
+arst_n => reg_regs_regs_0_sva_cse[87].ACLR
+arst_n => reg_regs_regs_0_sva_cse[88].ACLR
+arst_n => reg_regs_regs_0_sva_cse[89].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[9].ACLR
+arst_n => main_stage_0_2.ACLR
+arst_n => ACC1_acc_655_itm_1[0].ACLR
+arst_n => ACC1_acc_655_itm_1[1].ACLR
+arst_n => ACC1_acc_655_itm_1[2].ACLR
+arst_n => ACC1_acc_655_itm_1[3].ACLR
+arst_n => ACC1_acc_655_itm_1[4].ACLR
+arst_n => ACC1_acc_655_itm_1[5].ACLR
+arst_n => ACC1_acc_655_itm_1[6].ACLR
+arst_n => ACC1_acc_655_itm_1[7].ACLR
+arst_n => ACC1_acc_655_itm_1[8].ACLR
+arst_n => ACC1_acc_655_itm_1[9].ACLR
+arst_n => ACC1_acc_655_itm_1[10].ACLR
+arst_n => ACC1_acc_655_itm_1[11].ACLR
+arst_n => ACC1_acc_652_itm_1[0].ACLR
+arst_n => ACC1_acc_652_itm_1[1].ACLR
+arst_n => ACC1_acc_652_itm_1[2].ACLR
+arst_n => ACC1_acc_652_itm_1[3].ACLR
+arst_n => ACC1_acc_652_itm_1[4].ACLR
+arst_n => ACC1_acc_652_itm_1[5].ACLR
+arst_n => ACC1_acc_652_itm_1[6].ACLR
+arst_n => ACC1_acc_652_itm_1[7].ACLR
+arst_n => ACC1_acc_652_itm_1[8].ACLR
+arst_n => ACC1_acc_652_itm_1[9].ACLR
+arst_n => ACC1_acc_652_itm_1[10].ACLR
+arst_n => ACC1_3_slc_acc_10_psp_62_itm_1.ACLR
+arst_n => ACC1_slc_ACC1_acc_228_psp_55_itm_1.ACLR
+arst_n => slc_acc_20_psp_1_93_itm_1.ACLR
+arst_n => ACC1_mul_57_itm_2[0].ACLR
+arst_n => ACC1_mul_57_itm_2[1].ACLR
+arst_n => ACC1_mul_57_itm_1_sg2[0].ACLR
+arst_n => ACC1_mul_57_itm_1_sg2[1].ACLR
+arst_n => ACC1_mul_57_itm_1_sg2[2].ACLR
+arst_n => ACC1_mul_57_itm_1_sg2[3].ACLR
+arst_n => ACC1_mul_57_itm_1_sg2[4].ACLR
+arst_n => ACC1_acc_661_itm_1[0].ACLR
+arst_n => ACC1_acc_661_itm_1[1].ACLR
+arst_n => ACC1_acc_661_itm_1[2].ACLR
+arst_n => ACC1_acc_661_itm_1[3].ACLR
+arst_n => ACC1_acc_661_itm_1[4].ACLR
+arst_n => ACC1_acc_661_itm_1[5].ACLR
+arst_n => ACC1_acc_661_itm_1[6].ACLR
+arst_n => ACC1_acc_661_itm_1[7].ACLR
+arst_n => ACC1_acc_661_itm_1[8].ACLR
+arst_n => ACC1_acc_661_itm_1[9].ACLR
+arst_n => ACC1_acc_661_itm_1[10].ACLR
+arst_n => ACC1_acc_661_itm_1[11].ACLR
+arst_n => ACC1_acc_661_itm_1[12].ACLR
+arst_n => ACC1_acc_661_itm_1[13].ACLR
+arst_n => ACC1_acc_658_itm_1[0].ACLR
+arst_n => ACC1_acc_658_itm_1[1].ACLR
+arst_n => ACC1_acc_658_itm_1[2].ACLR
+arst_n => ACC1_acc_658_itm_1[3].ACLR
+arst_n => ACC1_acc_658_itm_1[4].ACLR
+arst_n => ACC1_acc_658_itm_1[5].ACLR
+arst_n => ACC1_acc_658_itm_1[6].ACLR
+arst_n => ACC1_acc_658_itm_1[7].ACLR
+arst_n => ACC1_acc_658_itm_1[8].ACLR
+arst_n => ACC1_acc_658_itm_1[9].ACLR
+arst_n => ACC1_acc_658_itm_1[10].ACLR
+arst_n => ACC1_acc_658_itm_1[11].ACLR
+arst_n => ACC1_acc_658_itm_1[12].ACLR
+arst_n => ACC1_acc_659_itm_1[0].ACLR
+arst_n => ACC1_acc_659_itm_1[1].ACLR
+arst_n => ACC1_acc_659_itm_1[2].ACLR
+arst_n => ACC1_acc_659_itm_1[3].ACLR
+arst_n => ACC1_acc_659_itm_1[4].ACLR
+arst_n => ACC1_acc_659_itm_1[5].ACLR
+arst_n => ACC1_acc_659_itm_1[6].ACLR
+arst_n => ACC1_acc_659_itm_1[7].ACLR
+arst_n => ACC1_acc_659_itm_1[8].ACLR
+arst_n => ACC1_acc_659_itm_1[9].ACLR
+arst_n => ACC1_acc_659_itm_1[10].ACLR
+arst_n => ACC1_acc_659_itm_1[11].ACLR
+arst_n => ACC1_acc_659_itm_1[12].ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[0]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[1]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[2]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[3]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[4]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[5]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[6]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[7]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[8]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[9]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[10]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[11]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[12]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[13]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[14]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[15]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[16]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[17]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[18]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[19]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[20]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[21]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[22]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[23]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[24]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[25]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[26]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[27]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[28]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[29]~reg0.ACLR
+vin_rsc_mgc_in_wire_d[0] => Add43.IN22
+vin_rsc_mgc_in_wire_d[0] => reg_regs_regs_0_sva_cse[0].DATAIN
+vin_rsc_mgc_in_wire_d[1] => Add43.IN21
+vin_rsc_mgc_in_wire_d[1] => reg_regs_regs_0_sva_cse[1].DATAIN
+vin_rsc_mgc_in_wire_d[2] => Add43.IN20
+vin_rsc_mgc_in_wire_d[2] => reg_regs_regs_0_sva_cse[2].DATAIN
+vin_rsc_mgc_in_wire_d[3] => Add43.IN19
+vin_rsc_mgc_in_wire_d[3] => reg_regs_regs_0_sva_cse[3].DATAIN
+vin_rsc_mgc_in_wire_d[4] => Add43.IN18
+vin_rsc_mgc_in_wire_d[4] => reg_regs_regs_0_sva_cse[4].DATAIN
+vin_rsc_mgc_in_wire_d[5] => Add43.IN17
+vin_rsc_mgc_in_wire_d[5] => reg_regs_regs_0_sva_cse[5].DATAIN
+vin_rsc_mgc_in_wire_d[6] => Add43.IN16
+vin_rsc_mgc_in_wire_d[6] => reg_regs_regs_0_sva_cse[6].DATAIN
+vin_rsc_mgc_in_wire_d[7] => Add43.IN15
+vin_rsc_mgc_in_wire_d[7] => reg_regs_regs_0_sva_cse[7].DATAIN
+vin_rsc_mgc_in_wire_d[8] => Add43.IN14
+vin_rsc_mgc_in_wire_d[8] => reg_regs_regs_0_sva_cse[8].DATAIN
+vin_rsc_mgc_in_wire_d[9] => Add43.IN12
+vin_rsc_mgc_in_wire_d[9] => Add43.IN13
+vin_rsc_mgc_in_wire_d[9] => reg_regs_regs_0_sva_cse[9].DATAIN
+vin_rsc_mgc_in_wire_d[10] => Add42.IN22
+vin_rsc_mgc_in_wire_d[10] => reg_regs_regs_0_sva_cse[10].DATAIN
+vin_rsc_mgc_in_wire_d[11] => Add42.IN21
+vin_rsc_mgc_in_wire_d[11] => reg_regs_regs_0_sva_cse[11].DATAIN
+vin_rsc_mgc_in_wire_d[12] => Add42.IN20
+vin_rsc_mgc_in_wire_d[12] => reg_regs_regs_0_sva_cse[12].DATAIN
+vin_rsc_mgc_in_wire_d[13] => Add42.IN19
+vin_rsc_mgc_in_wire_d[13] => reg_regs_regs_0_sva_cse[13].DATAIN
+vin_rsc_mgc_in_wire_d[14] => Add42.IN18
+vin_rsc_mgc_in_wire_d[14] => reg_regs_regs_0_sva_cse[14].DATAIN
+vin_rsc_mgc_in_wire_d[15] => Add42.IN17
+vin_rsc_mgc_in_wire_d[15] => reg_regs_regs_0_sva_cse[15].DATAIN
+vin_rsc_mgc_in_wire_d[16] => Add42.IN16
+vin_rsc_mgc_in_wire_d[16] => reg_regs_regs_0_sva_cse[16].DATAIN
+vin_rsc_mgc_in_wire_d[17] => Add42.IN15
+vin_rsc_mgc_in_wire_d[17] => reg_regs_regs_0_sva_cse[17].DATAIN
+vin_rsc_mgc_in_wire_d[18] => Add42.IN14
+vin_rsc_mgc_in_wire_d[18] => reg_regs_regs_0_sva_cse[18].DATAIN
+vin_rsc_mgc_in_wire_d[19] => Add42.IN12
+vin_rsc_mgc_in_wire_d[19] => Add42.IN13
+vin_rsc_mgc_in_wire_d[19] => reg_regs_regs_0_sva_cse[19].DATAIN
+vin_rsc_mgc_in_wire_d[20] => Add42.IN11
+vin_rsc_mgc_in_wire_d[20] => reg_regs_regs_0_sva_cse[20].DATAIN
+vin_rsc_mgc_in_wire_d[21] => Add42.IN10
+vin_rsc_mgc_in_wire_d[21] => reg_regs_regs_0_sva_cse[21].DATAIN
+vin_rsc_mgc_in_wire_d[22] => Add42.IN9
+vin_rsc_mgc_in_wire_d[22] => reg_regs_regs_0_sva_cse[22].DATAIN
+vin_rsc_mgc_in_wire_d[23] => Add42.IN8
+vin_rsc_mgc_in_wire_d[23] => reg_regs_regs_0_sva_cse[23].DATAIN
+vin_rsc_mgc_in_wire_d[24] => Add42.IN7
+vin_rsc_mgc_in_wire_d[24] => reg_regs_regs_0_sva_cse[24].DATAIN
+vin_rsc_mgc_in_wire_d[25] => Add42.IN6
+vin_rsc_mgc_in_wire_d[25] => reg_regs_regs_0_sva_cse[25].DATAIN
+vin_rsc_mgc_in_wire_d[26] => Add42.IN5
+vin_rsc_mgc_in_wire_d[26] => reg_regs_regs_0_sva_cse[26].DATAIN
+vin_rsc_mgc_in_wire_d[27] => Add42.IN4
+vin_rsc_mgc_in_wire_d[27] => reg_regs_regs_0_sva_cse[27].DATAIN
+vin_rsc_mgc_in_wire_d[28] => Add42.IN3
+vin_rsc_mgc_in_wire_d[28] => reg_regs_regs_0_sva_cse[28].DATAIN
+vin_rsc_mgc_in_wire_d[29] => Add42.IN1
+vin_rsc_mgc_in_wire_d[29] => Add42.IN2
+vin_rsc_mgc_in_wire_d[29] => reg_regs_regs_0_sva_cse[29].DATAIN
+vin_rsc_mgc_in_wire_d[30] => Add45.IN11
+vin_rsc_mgc_in_wire_d[30] => reg_regs_regs_0_sva_cse[30].DATAIN
+vin_rsc_mgc_in_wire_d[31] => Add45.IN10
+vin_rsc_mgc_in_wire_d[31] => reg_regs_regs_0_sva_cse[31].DATAIN
+vin_rsc_mgc_in_wire_d[32] => Add45.IN9
+vin_rsc_mgc_in_wire_d[32] => reg_regs_regs_0_sva_cse[32].DATAIN
+vin_rsc_mgc_in_wire_d[33] => Add45.IN8
+vin_rsc_mgc_in_wire_d[33] => reg_regs_regs_0_sva_cse[33].DATAIN
+vin_rsc_mgc_in_wire_d[34] => Add45.IN7
+vin_rsc_mgc_in_wire_d[34] => reg_regs_regs_0_sva_cse[34].DATAIN
+vin_rsc_mgc_in_wire_d[35] => Add45.IN6
+vin_rsc_mgc_in_wire_d[35] => reg_regs_regs_0_sva_cse[35].DATAIN
+vin_rsc_mgc_in_wire_d[36] => Add45.IN5
+vin_rsc_mgc_in_wire_d[36] => reg_regs_regs_0_sva_cse[36].DATAIN
+vin_rsc_mgc_in_wire_d[37] => Add45.IN4
+vin_rsc_mgc_in_wire_d[37] => reg_regs_regs_0_sva_cse[37].DATAIN
+vin_rsc_mgc_in_wire_d[38] => Add45.IN3
+vin_rsc_mgc_in_wire_d[38] => reg_regs_regs_0_sva_cse[38].DATAIN
+vin_rsc_mgc_in_wire_d[39] => Add45.IN1
+vin_rsc_mgc_in_wire_d[39] => Add45.IN2
+vin_rsc_mgc_in_wire_d[39] => reg_regs_regs_0_sva_cse[39].DATAIN
+vin_rsc_mgc_in_wire_d[40] => Add45.IN22
+vin_rsc_mgc_in_wire_d[40] => reg_regs_regs_0_sva_cse[40].DATAIN
+vin_rsc_mgc_in_wire_d[41] => Add45.IN21
+vin_rsc_mgc_in_wire_d[41] => reg_regs_regs_0_sva_cse[41].DATAIN
+vin_rsc_mgc_in_wire_d[42] => Add45.IN20
+vin_rsc_mgc_in_wire_d[42] => reg_regs_regs_0_sva_cse[42].DATAIN
+vin_rsc_mgc_in_wire_d[43] => Add45.IN19
+vin_rsc_mgc_in_wire_d[43] => reg_regs_regs_0_sva_cse[43].DATAIN
+vin_rsc_mgc_in_wire_d[44] => Add45.IN18
+vin_rsc_mgc_in_wire_d[44] => reg_regs_regs_0_sva_cse[44].DATAIN
+vin_rsc_mgc_in_wire_d[45] => Add45.IN17
+vin_rsc_mgc_in_wire_d[45] => reg_regs_regs_0_sva_cse[45].DATAIN
+vin_rsc_mgc_in_wire_d[46] => Add45.IN16
+vin_rsc_mgc_in_wire_d[46] => reg_regs_regs_0_sva_cse[46].DATAIN
+vin_rsc_mgc_in_wire_d[47] => Add45.IN15
+vin_rsc_mgc_in_wire_d[47] => reg_regs_regs_0_sva_cse[47].DATAIN
+vin_rsc_mgc_in_wire_d[48] => Add45.IN14
+vin_rsc_mgc_in_wire_d[48] => reg_regs_regs_0_sva_cse[48].DATAIN
+vin_rsc_mgc_in_wire_d[49] => Add45.IN12
+vin_rsc_mgc_in_wire_d[49] => Add45.IN13
+vin_rsc_mgc_in_wire_d[49] => reg_regs_regs_0_sva_cse[49].DATAIN
+vin_rsc_mgc_in_wire_d[50] => Add46.IN22
+vin_rsc_mgc_in_wire_d[50] => reg_regs_regs_0_sva_cse[50].DATAIN
+vin_rsc_mgc_in_wire_d[51] => Add46.IN21
+vin_rsc_mgc_in_wire_d[51] => reg_regs_regs_0_sva_cse[51].DATAIN
+vin_rsc_mgc_in_wire_d[52] => Add46.IN20
+vin_rsc_mgc_in_wire_d[52] => reg_regs_regs_0_sva_cse[52].DATAIN
+vin_rsc_mgc_in_wire_d[53] => Add46.IN19
+vin_rsc_mgc_in_wire_d[53] => reg_regs_regs_0_sva_cse[53].DATAIN
+vin_rsc_mgc_in_wire_d[54] => Add46.IN18
+vin_rsc_mgc_in_wire_d[54] => reg_regs_regs_0_sva_cse[54].DATAIN
+vin_rsc_mgc_in_wire_d[55] => Add46.IN17
+vin_rsc_mgc_in_wire_d[55] => reg_regs_regs_0_sva_cse[55].DATAIN
+vin_rsc_mgc_in_wire_d[56] => Add46.IN16
+vin_rsc_mgc_in_wire_d[56] => reg_regs_regs_0_sva_cse[56].DATAIN
+vin_rsc_mgc_in_wire_d[57] => Add46.IN15
+vin_rsc_mgc_in_wire_d[57] => reg_regs_regs_0_sva_cse[57].DATAIN
+vin_rsc_mgc_in_wire_d[58] => Add46.IN14
+vin_rsc_mgc_in_wire_d[58] => reg_regs_regs_0_sva_cse[58].DATAIN
+vin_rsc_mgc_in_wire_d[59] => Add46.IN12
+vin_rsc_mgc_in_wire_d[59] => Add46.IN13
+vin_rsc_mgc_in_wire_d[59] => reg_regs_regs_0_sva_cse[59].DATAIN
+vin_rsc_mgc_in_wire_d[60] => Add25.IN22
+vin_rsc_mgc_in_wire_d[60] => Add131.IN22
+vin_rsc_mgc_in_wire_d[60] => reg_regs_regs_0_sva_cse[60].DATAIN
+vin_rsc_mgc_in_wire_d[61] => Add25.IN21
+vin_rsc_mgc_in_wire_d[61] => Add131.IN21
+vin_rsc_mgc_in_wire_d[61] => reg_regs_regs_0_sva_cse[61].DATAIN
+vin_rsc_mgc_in_wire_d[62] => Add25.IN20
+vin_rsc_mgc_in_wire_d[62] => Add131.IN20
+vin_rsc_mgc_in_wire_d[62] => reg_regs_regs_0_sva_cse[62].DATAIN
+vin_rsc_mgc_in_wire_d[63] => Add25.IN19
+vin_rsc_mgc_in_wire_d[63] => Add131.IN19
+vin_rsc_mgc_in_wire_d[63] => reg_regs_regs_0_sva_cse[63].DATAIN
+vin_rsc_mgc_in_wire_d[64] => Add25.IN18
+vin_rsc_mgc_in_wire_d[64] => Add131.IN18
+vin_rsc_mgc_in_wire_d[64] => reg_regs_regs_0_sva_cse[64].DATAIN
+vin_rsc_mgc_in_wire_d[65] => Add25.IN17
+vin_rsc_mgc_in_wire_d[65] => Add131.IN17
+vin_rsc_mgc_in_wire_d[65] => reg_regs_regs_0_sva_cse[65].DATAIN
+vin_rsc_mgc_in_wire_d[66] => Add25.IN16
+vin_rsc_mgc_in_wire_d[66] => Add131.IN16
+vin_rsc_mgc_in_wire_d[66] => reg_regs_regs_0_sva_cse[66].DATAIN
+vin_rsc_mgc_in_wire_d[67] => Add25.IN15
+vin_rsc_mgc_in_wire_d[67] => Add131.IN15
+vin_rsc_mgc_in_wire_d[67] => reg_regs_regs_0_sva_cse[67].DATAIN
+vin_rsc_mgc_in_wire_d[68] => Add25.IN14
+vin_rsc_mgc_in_wire_d[68] => Add131.IN14
+vin_rsc_mgc_in_wire_d[68] => reg_regs_regs_0_sva_cse[68].DATAIN
+vin_rsc_mgc_in_wire_d[69] => Add25.IN12
+vin_rsc_mgc_in_wire_d[69] => Add25.IN13
+vin_rsc_mgc_in_wire_d[69] => Add131.IN12
+vin_rsc_mgc_in_wire_d[69] => Add131.IN13
+vin_rsc_mgc_in_wire_d[69] => reg_regs_regs_0_sva_cse[69].DATAIN
+vin_rsc_mgc_in_wire_d[70] => Add25.IN11
+vin_rsc_mgc_in_wire_d[70] => Add130.IN22
+vin_rsc_mgc_in_wire_d[70] => reg_regs_regs_0_sva_cse[70].DATAIN
+vin_rsc_mgc_in_wire_d[71] => Add25.IN10
+vin_rsc_mgc_in_wire_d[71] => Add130.IN21
+vin_rsc_mgc_in_wire_d[71] => reg_regs_regs_0_sva_cse[71].DATAIN
+vin_rsc_mgc_in_wire_d[72] => Add25.IN9
+vin_rsc_mgc_in_wire_d[72] => Add130.IN20
+vin_rsc_mgc_in_wire_d[72] => reg_regs_regs_0_sva_cse[72].DATAIN
+vin_rsc_mgc_in_wire_d[73] => Add25.IN8
+vin_rsc_mgc_in_wire_d[73] => Add130.IN19
+vin_rsc_mgc_in_wire_d[73] => reg_regs_regs_0_sva_cse[73].DATAIN
+vin_rsc_mgc_in_wire_d[74] => Add25.IN7
+vin_rsc_mgc_in_wire_d[74] => Add130.IN18
+vin_rsc_mgc_in_wire_d[74] => reg_regs_regs_0_sva_cse[74].DATAIN
+vin_rsc_mgc_in_wire_d[75] => Add25.IN6
+vin_rsc_mgc_in_wire_d[75] => Add130.IN17
+vin_rsc_mgc_in_wire_d[75] => reg_regs_regs_0_sva_cse[75].DATAIN
+vin_rsc_mgc_in_wire_d[76] => Add25.IN5
+vin_rsc_mgc_in_wire_d[76] => Add130.IN16
+vin_rsc_mgc_in_wire_d[76] => reg_regs_regs_0_sva_cse[76].DATAIN
+vin_rsc_mgc_in_wire_d[77] => Add25.IN4
+vin_rsc_mgc_in_wire_d[77] => Add130.IN15
+vin_rsc_mgc_in_wire_d[77] => reg_regs_regs_0_sva_cse[77].DATAIN
+vin_rsc_mgc_in_wire_d[78] => Add25.IN3
+vin_rsc_mgc_in_wire_d[78] => Add130.IN14
+vin_rsc_mgc_in_wire_d[78] => reg_regs_regs_0_sva_cse[78].DATAIN
+vin_rsc_mgc_in_wire_d[79] => Add25.IN1
+vin_rsc_mgc_in_wire_d[79] => Add25.IN2
+vin_rsc_mgc_in_wire_d[79] => Add130.IN12
+vin_rsc_mgc_in_wire_d[79] => Add130.IN13
+vin_rsc_mgc_in_wire_d[79] => reg_regs_regs_0_sva_cse[79].DATAIN
+vin_rsc_mgc_in_wire_d[80] => Add26.IN26
+vin_rsc_mgc_in_wire_d[80] => Add130.IN11
+vin_rsc_mgc_in_wire_d[80] => reg_regs_regs_0_sva_cse[80].DATAIN
+vin_rsc_mgc_in_wire_d[81] => Add26.IN25
+vin_rsc_mgc_in_wire_d[81] => Add130.IN10
+vin_rsc_mgc_in_wire_d[81] => reg_regs_regs_0_sva_cse[81].DATAIN
+vin_rsc_mgc_in_wire_d[82] => Add26.IN24
+vin_rsc_mgc_in_wire_d[82] => Add130.IN9
+vin_rsc_mgc_in_wire_d[82] => reg_regs_regs_0_sva_cse[82].DATAIN
+vin_rsc_mgc_in_wire_d[83] => Add26.IN23
+vin_rsc_mgc_in_wire_d[83] => Add130.IN8
+vin_rsc_mgc_in_wire_d[83] => reg_regs_regs_0_sva_cse[83].DATAIN
+vin_rsc_mgc_in_wire_d[84] => Add26.IN22
+vin_rsc_mgc_in_wire_d[84] => Add130.IN7
+vin_rsc_mgc_in_wire_d[84] => reg_regs_regs_0_sva_cse[84].DATAIN
+vin_rsc_mgc_in_wire_d[85] => Add26.IN21
+vin_rsc_mgc_in_wire_d[85] => Add130.IN6
+vin_rsc_mgc_in_wire_d[85] => reg_regs_regs_0_sva_cse[85].DATAIN
+vin_rsc_mgc_in_wire_d[86] => Add26.IN20
+vin_rsc_mgc_in_wire_d[86] => Add130.IN5
+vin_rsc_mgc_in_wire_d[86] => reg_regs_regs_0_sva_cse[86].DATAIN
+vin_rsc_mgc_in_wire_d[87] => Add26.IN19
+vin_rsc_mgc_in_wire_d[87] => Add130.IN4
+vin_rsc_mgc_in_wire_d[87] => reg_regs_regs_0_sva_cse[87].DATAIN
+vin_rsc_mgc_in_wire_d[88] => Add26.IN18
+vin_rsc_mgc_in_wire_d[88] => Add130.IN3
+vin_rsc_mgc_in_wire_d[88] => reg_regs_regs_0_sva_cse[88].DATAIN
+vin_rsc_mgc_in_wire_d[89] => Add26.IN14
+vin_rsc_mgc_in_wire_d[89] => Add26.IN15
+vin_rsc_mgc_in_wire_d[89] => Add26.IN16
+vin_rsc_mgc_in_wire_d[89] => Add26.IN17
+vin_rsc_mgc_in_wire_d[89] => Add130.IN1
+vin_rsc_mgc_in_wire_d[89] => Add130.IN2
+vin_rsc_mgc_in_wire_d[89] => reg_regs_regs_0_sva_cse[89].DATAIN
+vout_rsc_mgc_out_stdreg_d[0] <= vout_rsc_mgc_out_stdreg_d[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[1] <= vout_rsc_mgc_out_stdreg_d[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[2] <= vout_rsc_mgc_out_stdreg_d[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[3] <= vout_rsc_mgc_out_stdreg_d[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[4] <= vout_rsc_mgc_out_stdreg_d[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[5] <= vout_rsc_mgc_out_stdreg_d[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[6] <= vout_rsc_mgc_out_stdreg_d[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[7] <= vout_rsc_mgc_out_stdreg_d[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[8] <= vout_rsc_mgc_out_stdreg_d[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[9] <= vout_rsc_mgc_out_stdreg_d[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[10] <= vout_rsc_mgc_out_stdreg_d[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[11] <= vout_rsc_mgc_out_stdreg_d[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[12] <= vout_rsc_mgc_out_stdreg_d[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[13] <= vout_rsc_mgc_out_stdreg_d[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[14] <= vout_rsc_mgc_out_stdreg_d[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[15] <= vout_rsc_mgc_out_stdreg_d[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[16] <= vout_rsc_mgc_out_stdreg_d[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[17] <= vout_rsc_mgc_out_stdreg_d[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[18] <= vout_rsc_mgc_out_stdreg_d[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[19] <= vout_rsc_mgc_out_stdreg_d[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[20] <= vout_rsc_mgc_out_stdreg_d[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[21] <= vout_rsc_mgc_out_stdreg_d[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[22] <= vout_rsc_mgc_out_stdreg_d[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[23] <= vout_rsc_mgc_out_stdreg_d[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[24] <= vout_rsc_mgc_out_stdreg_d[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[25] <= vout_rsc_mgc_out_stdreg_d[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[26] <= vout_rsc_mgc_out_stdreg_d[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[27] <= vout_rsc_mgc_out_stdreg_d[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[28] <= vout_rsc_mgc_out_stdreg_d[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[29] <= vout_rsc_mgc_out_stdreg_d[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/Sobel/Sobel Quartus/db/sobel.hif b/Sobel/Sobel Quartus/db/sobel.hif
new file mode 100644
index 0000000..89a4b5c
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.hif
diff --git a/Sobel/Sobel Quartus/db/sobel.ipinfo b/Sobel/Sobel Quartus/db/sobel.ipinfo
new file mode 100644
index 0000000..3560eab
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.ipinfo
diff --git a/Sobel/Sobel Quartus/db/sobel.lpc.html b/Sobel/Sobel Quartus/db/sobel.lpc.html
new file mode 100644
index 0000000..74beee8
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.lpc.html
@@ -0,0 +1,66 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >sobel_core_inst</TD>
+<TD >93</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vout_rsc_mgc_out_stdreg</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vin_rsc_mgc_in_wire</TD>
+<TD >90</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >90</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/Sobel/Sobel Quartus/db/sobel.lpc.rdb b/Sobel/Sobel Quartus/db/sobel.lpc.rdb
new file mode 100644
index 0000000..17426fa
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.lpc.rdb
diff --git a/Sobel/Sobel Quartus/db/sobel.lpc.txt b/Sobel/Sobel Quartus/db/sobel.lpc.txt
new file mode 100644
index 0000000..d0a772a
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.lpc.txt
@@ -0,0 +1,9 @@
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                   ;
++-------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy               ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; sobel_core_inst         ; 93    ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vout_rsc_mgc_out_stdreg ; 30    ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vin_rsc_mgc_in_wire     ; 90    ; 0              ; 0            ; 0              ; 90     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/Sobel/Sobel Quartus/db/sobel.map.ammdb b/Sobel/Sobel Quartus/db/sobel.map.ammdb
new file mode 100644
index 0000000..8b8ff04
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.map.ammdb
diff --git a/Sobel/Sobel Quartus/db/sobel.map.bpm b/Sobel/Sobel Quartus/db/sobel.map.bpm
new file mode 100644
index 0000000..e0ac409
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.map.bpm
diff --git a/Sobel/Sobel Quartus/db/sobel.map.cdb b/Sobel/Sobel Quartus/db/sobel.map.cdb
new file mode 100644
index 0000000..fd6ecec
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.map.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.map.hdb b/Sobel/Sobel Quartus/db/sobel.map.hdb
new file mode 100644
index 0000000..8ac19a9
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.map.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.map.kpt b/Sobel/Sobel Quartus/db/sobel.map.kpt
new file mode 100644
index 0000000..656dc43
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.map.kpt
diff --git a/Sobel/Sobel Quartus/db/sobel.map.logdb b/Sobel/Sobel Quartus/db/sobel.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Sobel/Sobel Quartus/db/sobel.map.qmsg b/Sobel/Sobel Quartus/db/sobel.map.qmsg
new file mode 100644
index 0000000..fca1c8a
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.map.qmsg
@@ -0,0 +1,53 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1457454100457 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457454100462 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:21:39 2016 " "Processing started: Tue Mar 08 16:21:39 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457454100462 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1457454100462 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sobel -c sobel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sobel -c sobel" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1457454100462 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1457454102791 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "//icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel.v12/rtl_mgc_ioport.v 20 20 " "Found 20 design units, including 20 entities, in source file //icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel.v12/rtl_mgc_ioport.v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_in_wire " "Found entity 1: mgc_in_wire" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 13 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_in_wire_en " "Found entity 2: mgc_in_wire_en" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_in_wire_wait " "Found entity 3: mgc_in_wire_wait" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_chan_in " "Found entity 4: mgc_chan_in" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 72 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_stdreg " "Found entity 5: mgc_out_stdreg" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 109 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_stdreg_en " "Found entity 6: mgc_out_stdreg_en" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 125 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_out_stdreg_wait " "Found entity 7: mgc_out_stdreg_wait" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 145 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "8 mgc_out_prereg_en " "Found entity 8: mgc_out_prereg_en" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 169 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "9 mgc_inout_stdreg_en " "Found entity 9: mgc_inout_stdreg_en" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 191 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "10 hid_tribuf " "Found entity 10: hid_tribuf" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 217 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "11 mgc_inout_stdreg_wait " "Found entity 11: mgc_inout_stdreg_wait" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 229 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "12 mgc_inout_buf_wait " "Found entity 12: mgc_inout_buf_wait" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 269 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "13 mgc_inout_fifo_wait " "Found entity 13: mgc_inout_fifo_wait" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 339 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "14 mgc_io_sync " "Found entity 14: mgc_io_sync" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 419 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "15 mgc_bsync_rdy " "Found entity 15: mgc_bsync_rdy" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 428 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "16 mgc_bsync_vld " "Found entity 16: mgc_bsync_vld" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 443 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "17 mgc_bsync_rv " "Found entity 17: mgc_bsync_rv" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 458 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "18 mgc_sync " "Found entity 18: mgc_sync" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 479 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "19 funccall_inout " "Found entity 19: funccall_inout" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 498 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""} { "Info" "ISGN_ENTITY_NAME" "20 modulario_en_in " "Found entity 20: modulario_en_in" {  } { { "../sobel.v12/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v" 526 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454102897 ""}
+{ "Warning" "WSGN_SEARCH_FILE" "sobel.v 2 2 " "Using design file sobel.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sobel_core " "Found entity 1: sobel_core" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454106833 ""} { "Info" "ISGN_ENTITY_NAME" "2 sobel " "Found entity 2: sobel" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1573 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454106833 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1457454106833 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "sobel " "Elaborating entity \"sobel\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1457454106866 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire mgc_in_wire:vin_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"mgc_in_wire:vin_rsc_mgc_in_wire\"" {  } { { "sobel.v" "vin_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1593 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454107431 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_out_stdreg mgc_out_stdreg:vout_rsc_mgc_out_stdreg " "Elaborating entity \"mgc_out_stdreg\" for hierarchy \"mgc_out_stdreg:vout_rsc_mgc_out_stdreg\"" {  } { { "sobel.v" "vout_rsc_mgc_out_stdreg" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1598 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454107609 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sobel_core sobel_core:sobel_core_inst " "Elaborating entity \"sobel_core\" for hierarchy \"sobel_core:sobel_core_inst\"" {  } { { "sobel.v" "sobel_core_inst" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1605 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454107701 ""}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "9 " "Inferred 9 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult0\"" {  } { { "sobel.v" "Mult0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult1\"" {  } { { "sobel.v" "Mult1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult7 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult7\"" {  } { { "sobel.v" "Mult7" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult5 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult5\"" {  } { { "sobel.v" "Mult5" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult2 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult2\"" {  } { { "sobel.v" "Mult2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult3 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult3\"" {  } { { "sobel.v" "Mult3" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult6 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult6\"" {  } { { "sobel.v" "Mult6" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult4 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult4\"" {  } { { "sobel.v" "Mult4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel_core:sobel_core_inst\|Mult8 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel_core:sobel_core_inst\|Mult8\"" {  } { { "sobel.v" "Mult8" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 784 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109046 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1457454109046 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109318 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 11 " "Parameter \"LPM_WIDTHP\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 11 " "Parameter \"LPM_WIDTHR\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109325 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454109325 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109548 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109693 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult0\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109848 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454109920 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 3 " "Parameter \"LPM_WIDTHA\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 6 " "Parameter \"LPM_WIDTHB\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 9 " "Parameter \"LPM_WIDTHP\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 9 " "Parameter \"LPM_WIDTHR\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109922 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454109922 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109944 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109960 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult1\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454109977 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 13 " "Parameter \"LPM_WIDTHB\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 15 " "Parameter \"LPM_WIDTHP\" = \"15\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 15 " "Parameter \"LPM_WIDTHR\" = \"15\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110056 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110056 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110090 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110113 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult7\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110133 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 13 " "Parameter \"LPM_WIDTHP\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 13 " "Parameter \"LPM_WIDTHR\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110207 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110207 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110255 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110280 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult5\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110312 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 14 " "Parameter \"LPM_WIDTHB\" = \"14\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 16 " "Parameter \"LPM_WIDTHP\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 16 " "Parameter \"LPM_WIDTHR\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110367 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110367 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110399 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110432 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult2\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110466 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 5 " "Parameter \"LPM_WIDTHB\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 9 " "Parameter \"LPM_WIDTHP\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 9 " "Parameter \"LPM_WIDTHR\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110541 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110541 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110584 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult3\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110603 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 3 " "Parameter \"LPM_WIDTHA\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 7 " "Parameter \"LPM_WIDTHB\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 10 " "Parameter \"LPM_WIDTHP\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 10 " "Parameter \"LPM_WIDTHR\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110696 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110696 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110756 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110815 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult6\|altshift:external_latency_ffs sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110848 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\"" {  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Instantiated megafunction \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 7 " "Parameter \"LPM_WIDTHB\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 11 " "Parameter \"LPM_WIDTHP\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 11 " "Parameter \"LPM_WIDTHR\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110915 ""}  } { { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454110915 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110956 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core\|mpar_add:padder sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Elaborated megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel_core:sobel_core_inst\|lpm_mult:Mult4\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454110985 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1457454112691 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1457454114662 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454114662 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "2188 " "Implemented 2188 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "93 " "Implemented 93 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1457454115182 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1457454115182 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2065 " "Implemented 2065 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1457454115182 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1457454115182 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "499 " "Peak virtual memory: 499 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454115376 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:21:55 2016 " "Processing ended: Tue Mar 08 16:21:55 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454115376 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454115376 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454115376 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457454115376 ""}
diff --git a/Sobel/Sobel Quartus/db/sobel.map.rdb b/Sobel/Sobel Quartus/db/sobel.map.rdb
new file mode 100644
index 0000000..1051fe1
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.map.rdb
diff --git a/Sobel/Sobel Quartus/db/sobel.map_bb.cdb b/Sobel/Sobel Quartus/db/sobel.map_bb.cdb
new file mode 100644
index 0000000..4c00092
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.map_bb.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.map_bb.hdb b/Sobel/Sobel Quartus/db/sobel.map_bb.hdb
new file mode 100644
index 0000000..2c08910
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.map_bb.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.map_bb.logdb b/Sobel/Sobel Quartus/db/sobel.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Sobel/Sobel Quartus/db/sobel.pre_map.hdb b/Sobel/Sobel Quartus/db/sobel.pre_map.hdb
new file mode 100644
index 0000000..9577ef9
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.pre_map.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.pti_db_list.ddb b/Sobel/Sobel Quartus/db/sobel.pti_db_list.ddb
new file mode 100644
index 0000000..4c5fa0d
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.pti_db_list.ddb
diff --git a/Sobel/Sobel Quartus/db/sobel.root_partition.map.reg_db.cdb b/Sobel/Sobel Quartus/db/sobel.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..82b2985
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.root_partition.map.reg_db.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.routing.rdb b/Sobel/Sobel Quartus/db/sobel.routing.rdb
new file mode 100644
index 0000000..bd144b3
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.routing.rdb
diff --git a/Sobel/Sobel Quartus/db/sobel.rtlv.hdb b/Sobel/Sobel Quartus/db/sobel.rtlv.hdb
new file mode 100644
index 0000000..1dd1288
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.rtlv.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.rtlv_sg.cdb b/Sobel/Sobel Quartus/db/sobel.rtlv_sg.cdb
new file mode 100644
index 0000000..81d5438
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.rtlv_sg.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.rtlv_sg_swap.cdb b/Sobel/Sobel Quartus/db/sobel.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..430e7f5
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.rtlv_sg_swap.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.sgdiff.cdb b/Sobel/Sobel Quartus/db/sobel.sgdiff.cdb
new file mode 100644
index 0000000..05e8861
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.sgdiff.cdb
diff --git a/Sobel/Sobel Quartus/db/sobel.sgdiff.hdb b/Sobel/Sobel Quartus/db/sobel.sgdiff.hdb
new file mode 100644
index 0000000..dafee32
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.sgdiff.hdb
diff --git a/Sobel/Sobel Quartus/db/sobel.sld_design_entry.sci b/Sobel/Sobel Quartus/db/sobel.sld_design_entry.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.sld_design_entry.sci
diff --git a/Sobel/Sobel Quartus/db/sobel.sld_design_entry_dsc.sci b/Sobel/Sobel Quartus/db/sobel.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.sld_design_entry_dsc.sci
diff --git a/Sobel/Sobel Quartus/db/sobel.smart_action.txt b/Sobel/Sobel Quartus/db/sobel.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/Sobel/Sobel Quartus/db/sobel.sta.qmsg b/Sobel/Sobel Quartus/db/sobel.sta.qmsg
new file mode 100644
index 0000000..28653bf
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.sta.qmsg
@@ -0,0 +1,42 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1457454147871 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457454147881 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:22:26 2016 " "Processing started: Tue Mar 08 16:22:26 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457454147881 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1457454147881 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta sobel -c sobel " "Command: quartus_sta sobel -c sobel" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1457454147884 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1457454147941 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1457454149057 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457454149060 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457454149107 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457454149108 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "sobel.sdc " "Synopsys Design Constraints File file not found: 'sobel.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1457454149748 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1457454149751 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1457454149764 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1457454149764 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1457454149784 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1457454149787 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1457454149805 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1457454149884 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457454150090 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457454150090 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -21.345 " "Worst-case setup slack is -21.345" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150125 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150125 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -21.345     -1510.709 clk  " "  -21.345     -1510.709 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150125 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454150125 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.516 " "Worst-case hold slack is 0.516" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150163 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150163 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.516         0.000 clk  " "    0.516         0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150163 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454150163 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454150196 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454150226 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000      -287.000 clk  " "   -3.000      -287.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454150253 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454150253 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1457454150501 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1457454150526 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1457454151095 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151302 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457454151423 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457454151423 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -18.828 " "Worst-case setup slack is -18.828" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151479 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151479 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -18.828     -1326.336 clk  " "  -18.828     -1326.336 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151479 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454151479 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.466 " "Worst-case hold slack is 0.466" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.466         0.000 clk  " "    0.466         0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151548 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454151548 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454151583 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454151618 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000      -287.000 clk  " "   -3.000      -287.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454151673 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454151673 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1457454152064 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152466 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457454152469 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457454152469 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -11.400 " "Worst-case setup slack is -11.400" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -11.400      -781.716 clk  " "  -11.400      -781.716 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152492 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454152492 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.268 " "Worst-case hold slack is 0.268" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.268         0.000 clk  " "    0.268         0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152523 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454152523 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454152550 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1457454152581 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152610 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152610 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000      -303.956 clk  " "   -3.000      -303.956 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454152610 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454152610 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1457454153329 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1457454153339 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "522 " "Peak virtual memory: 522 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454153827 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:22:33 2016 " "Processing ended: Tue Mar 08 16:22:33 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454153827 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454153827 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454153827 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457454153827 ""}
diff --git a/Sobel/Sobel Quartus/db/sobel.sta.rdb b/Sobel/Sobel Quartus/db/sobel.sta.rdb
new file mode 100644
index 0000000..4860124
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.sta.rdb
diff --git a/Sobel/Sobel Quartus/db/sobel.sta_cmp.6_slow_1200mv_85c.tdb b/Sobel/Sobel Quartus/db/sobel.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..7e7300f
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/Sobel/Sobel Quartus/db/sobel.syn_hier_info b/Sobel/Sobel Quartus/db/sobel.syn_hier_info
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.syn_hier_info
diff --git a/Sobel/Sobel Quartus/db/sobel.tis_db_list.ddb b/Sobel/Sobel Quartus/db/sobel.tis_db_list.ddb
new file mode 100644
index 0000000..ba46866
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.tis_db_list.ddb
diff --git a/Sobel/Sobel Quartus/db/sobel.tiscmp.fast_1200mv_0c.ddb b/Sobel/Sobel Quartus/db/sobel.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..7c2c248
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.tiscmp.fast_1200mv_0c.ddb
diff --git a/Sobel/Sobel Quartus/db/sobel.tiscmp.slow_1200mv_0c.ddb b/Sobel/Sobel Quartus/db/sobel.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..d442422
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.tiscmp.slow_1200mv_0c.ddb
diff --git a/Sobel/Sobel Quartus/db/sobel.tiscmp.slow_1200mv_85c.ddb b/Sobel/Sobel Quartus/db/sobel.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..2cdf91b
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.tiscmp.slow_1200mv_85c.ddb
diff --git a/Sobel/Sobel Quartus/db/sobel.tmw_info b/Sobel/Sobel Quartus/db/sobel.tmw_info
new file mode 100644
index 0000000..c659508
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:01:01
+start_analysis_synthesis:s:00:00:19-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:25-start_full_compilation
+start_assembler:s:00:00:04-start_full_compilation
+start_timing_analyzer:s:00:00:13-start_full_compilation
diff --git a/Sobel/Sobel Quartus/db/sobel.vpr.ammdb b/Sobel/Sobel Quartus/db/sobel.vpr.ammdb
new file mode 100644
index 0000000..bee5243
--- /dev/null
+++ b/Sobel/Sobel Quartus/db/sobel.vpr.ammdb
diff --git a/Sobel/Sobel Quartus/incremental_db/README b/Sobel/Sobel Quartus/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.db_info b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.db_info
new file mode 100644
index 0000000..4fbd361
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Mar 08 13:59:33 2016
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.ammdb b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.ammdb
new file mode 100644
index 0000000..ec782de
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.ammdb
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.cdb b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.cdb
new file mode 100644
index 0000000..e92dca5
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.cdb
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.dfp b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.dfp
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.hdb b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.hdb
new file mode 100644
index 0000000..e5724bb
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.hdb
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.kpt b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.kpt
new file mode 100644
index 0000000..b1479c0
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.kpt
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.logdb b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.rcfdb b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..2dfb05c
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.cmp.rcfdb
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.cdb b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.cdb
new file mode 100644
index 0000000..bda8e49
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.cdb
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.dpi b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.dpi
new file mode 100644
index 0000000..ad1f0bc
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.dpi
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hbdb.cdb b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..9ec254d
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hbdb.cdb
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hbdb.hb_info b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hbdb.hb_info
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hbdb.hdb b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..38bdb88
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hbdb.hdb
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hbdb.sig b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..ef58eaa
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hdb b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hdb
new file mode 100644
index 0000000..e5564d5
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.hdb
diff --git a/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.kpt b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.kpt
new file mode 100644
index 0000000..7624991
--- /dev/null
+++ b/Sobel/Sobel Quartus/incremental_db/compiled_partitions/sobel.root_partition.map.kpt
diff --git a/Sobel/Sobel Quartus/output_files/Chain3.cdf b/Sobel/Sobel Quartus/output_files/Chain3.cdf
new file mode 100644
index 0000000..a5eb1a3
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/Chain3.cdf
@@ -0,0 +1,13 @@
+/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP3C16F484) Path("//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/") File("DE0_D5M.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/Sobel/Sobel Quartus/output_files/Chain7.cdf b/Sobel/Sobel Quartus/output_files/Chain7.cdf
new file mode 100644
index 0000000..a5eb1a3
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/Chain7.cdf
@@ -0,0 +1,13 @@
+/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP3C16F484) Path("//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/") File("DE0_D5M.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/Sobel/Sobel Quartus/output_files/sobel.asm.rpt b/Sobel/Sobel Quartus/output_files/sobel.asm.rpt
new file mode 100644
index 0000000..f704b14
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for sobel
+Tue Mar 08 16:22:25 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: /EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/output_files/sobel.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Mar 08 16:22:25 2016 ;
+; Revision Name         ; sobel                                 ;
+; Top-level Entity Name ; sobel                                 ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Assembler Generated Files                                                   ;
++-----------------------------------------------------------------------------+
+; File Name                                                                   ;
++-----------------------------------------------------------------------------+
+; /EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/output_files/sobel.sof ;
++-----------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: /EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/output_files/sobel.sof ;
++----------------+--------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                              ;
++----------------+--------------------------------------------------------------------------------------+
+; Device         ; EP3C16F484C6                                                                         ;
+; JTAG usercode  ; 0x001C8103                                                                           ;
+; Checksum       ; 0x001C8103                                                                           ;
++----------------+--------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 08 16:22:22 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off sobel -c sobel
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 441 megabytes
+    Info: Processing ended: Tue Mar 08 16:22:25 2016
+    Info: Elapsed time: 00:00:03
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/Sobel/Sobel Quartus/output_files/sobel.done b/Sobel/Sobel Quartus/output_files/sobel.done
new file mode 100644
index 0000000..942d2f7
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.done
@@ -0,0 +1 @@
+Tue Mar 08 16:22:59 2016
diff --git a/Sobel/Sobel Quartus/output_files/sobel.fit.rpt b/Sobel/Sobel Quartus/output_files/sobel.fit.rpt
new file mode 100644
index 0000000..6f10b3f
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.fit.rpt
@@ -0,0 +1,3260 @@
+Fitter report for sobel
+Tue Mar 08 16:22:13 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Control Signals
+ 21. Global & Other Fast Signals
+ 22. Non-Global High Fan-Out Signals
+ 23. Other Routing Usage Summary
+ 24. LAB Logic Elements
+ 25. LAB-wide Signals
+ 26. LAB Signals Sourced
+ 27. LAB Signals Sourced Out
+ 28. LAB Distinct Inputs
+ 29. I/O Rules Summary
+ 30. I/O Rules Details
+ 31. I/O Rules Matrix
+ 32. Fitter Device Options
+ 33. Operating Settings and Conditions
+ 34. Fitter Messages
+ 35. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Fitter Summary                                                                        ;
++------------------------------------+--------------------------------------------------+
+; Fitter Status                      ; Successful - Tue Mar 08 16:22:13 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; sobel                                            ;
+; Top-level Entity Name              ; sobel                                            ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 1,923 / 15,408 ( 12 % )                          ;
+;     Total combinational functions  ; 1,847 / 15,408 ( 12 % )                          ;
+;     Dedicated logic registers      ; 284 / 15,408 ( 2 % )                             ;
+; Total registers                    ; 284                                              ;
+; Total pins                         ; 123 / 347 ( 35 % )                               ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.69        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;  23.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++------------------------------------------------+
+; I/O Assignment Warnings                        ;
++----------------+-------------------------------+
+; Pin Name       ; Reason                        ;
++----------------+-------------------------------+
+; vout_rsc_z[0]  ; Incomplete set of assignments ;
+; vout_rsc_z[1]  ; Incomplete set of assignments ;
+; vout_rsc_z[2]  ; Incomplete set of assignments ;
+; vout_rsc_z[3]  ; Incomplete set of assignments ;
+; vout_rsc_z[4]  ; Incomplete set of assignments ;
+; vout_rsc_z[5]  ; Incomplete set of assignments ;
+; vout_rsc_z[6]  ; Incomplete set of assignments ;
+; vout_rsc_z[7]  ; Incomplete set of assignments ;
+; vout_rsc_z[8]  ; Incomplete set of assignments ;
+; vout_rsc_z[9]  ; Incomplete set of assignments ;
+; vout_rsc_z[10] ; Incomplete set of assignments ;
+; vout_rsc_z[11] ; Incomplete set of assignments ;
+; vout_rsc_z[12] ; Incomplete set of assignments ;
+; vout_rsc_z[13] ; Incomplete set of assignments ;
+; vout_rsc_z[14] ; Incomplete set of assignments ;
+; vout_rsc_z[15] ; Incomplete set of assignments ;
+; vout_rsc_z[16] ; Incomplete set of assignments ;
+; vout_rsc_z[17] ; Incomplete set of assignments ;
+; vout_rsc_z[18] ; Incomplete set of assignments ;
+; vout_rsc_z[19] ; Incomplete set of assignments ;
+; vout_rsc_z[20] ; Incomplete set of assignments ;
+; vout_rsc_z[21] ; Incomplete set of assignments ;
+; vout_rsc_z[22] ; Incomplete set of assignments ;
+; vout_rsc_z[23] ; Incomplete set of assignments ;
+; vout_rsc_z[24] ; Incomplete set of assignments ;
+; vout_rsc_z[25] ; Incomplete set of assignments ;
+; vout_rsc_z[26] ; Incomplete set of assignments ;
+; vout_rsc_z[27] ; Incomplete set of assignments ;
+; vout_rsc_z[28] ; Incomplete set of assignments ;
+; vout_rsc_z[29] ; Incomplete set of assignments ;
+; clk            ; Incomplete set of assignments ;
+; arst_n         ; Incomplete set of assignments ;
+; en             ; Incomplete set of assignments ;
+; vin_rsc_z[57]  ; Incomplete set of assignments ;
+; vin_rsc_z[56]  ; Incomplete set of assignments ;
+; vin_rsc_z[55]  ; Incomplete set of assignments ;
+; vin_rsc_z[54]  ; Incomplete set of assignments ;
+; vin_rsc_z[53]  ; Incomplete set of assignments ;
+; vin_rsc_z[52]  ; Incomplete set of assignments ;
+; vin_rsc_z[51]  ; Incomplete set of assignments ;
+; vin_rsc_z[50]  ; Incomplete set of assignments ;
+; vin_rsc_z[47]  ; Incomplete set of assignments ;
+; vin_rsc_z[37]  ; Incomplete set of assignments ;
+; vin_rsc_z[46]  ; Incomplete set of assignments ;
+; vin_rsc_z[36]  ; Incomplete set of assignments ;
+; vin_rsc_z[45]  ; Incomplete set of assignments ;
+; vin_rsc_z[35]  ; Incomplete set of assignments ;
+; vin_rsc_z[44]  ; Incomplete set of assignments ;
+; vin_rsc_z[34]  ; Incomplete set of assignments ;
+; vin_rsc_z[43]  ; Incomplete set of assignments ;
+; vin_rsc_z[33]  ; Incomplete set of assignments ;
+; vin_rsc_z[42]  ; Incomplete set of assignments ;
+; vin_rsc_z[32]  ; Incomplete set of assignments ;
+; vin_rsc_z[41]  ; Incomplete set of assignments ;
+; vin_rsc_z[31]  ; Incomplete set of assignments ;
+; vin_rsc_z[40]  ; Incomplete set of assignments ;
+; vin_rsc_z[30]  ; Incomplete set of assignments ;
+; vin_rsc_z[78]  ; Incomplete set of assignments ;
+; vin_rsc_z[68]  ; Incomplete set of assignments ;
+; vin_rsc_z[77]  ; Incomplete set of assignments ;
+; vin_rsc_z[67]  ; Incomplete set of assignments ;
+; vin_rsc_z[76]  ; Incomplete set of assignments ;
+; vin_rsc_z[66]  ; Incomplete set of assignments ;
+; vin_rsc_z[75]  ; Incomplete set of assignments ;
+; vin_rsc_z[65]  ; Incomplete set of assignments ;
+; vin_rsc_z[74]  ; Incomplete set of assignments ;
+; vin_rsc_z[64]  ; Incomplete set of assignments ;
+; vin_rsc_z[73]  ; Incomplete set of assignments ;
+; vin_rsc_z[63]  ; Incomplete set of assignments ;
+; vin_rsc_z[72]  ; Incomplete set of assignments ;
+; vin_rsc_z[62]  ; Incomplete set of assignments ;
+; vin_rsc_z[71]  ; Incomplete set of assignments ;
+; vin_rsc_z[61]  ; Incomplete set of assignments ;
+; vin_rsc_z[70]  ; Incomplete set of assignments ;
+; vin_rsc_z[60]  ; Incomplete set of assignments ;
+; vin_rsc_z[88]  ; Incomplete set of assignments ;
+; vin_rsc_z[87]  ; Incomplete set of assignments ;
+; vin_rsc_z[86]  ; Incomplete set of assignments ;
+; vin_rsc_z[85]  ; Incomplete set of assignments ;
+; vin_rsc_z[84]  ; Incomplete set of assignments ;
+; vin_rsc_z[83]  ; Incomplete set of assignments ;
+; vin_rsc_z[82]  ; Incomplete set of assignments ;
+; vin_rsc_z[81]  ; Incomplete set of assignments ;
+; vin_rsc_z[80]  ; Incomplete set of assignments ;
+; vin_rsc_z[8]   ; Incomplete set of assignments ;
+; vin_rsc_z[7]   ; Incomplete set of assignments ;
+; vin_rsc_z[6]   ; Incomplete set of assignments ;
+; vin_rsc_z[5]   ; Incomplete set of assignments ;
+; vin_rsc_z[4]   ; Incomplete set of assignments ;
+; vin_rsc_z[3]   ; Incomplete set of assignments ;
+; vin_rsc_z[2]   ; Incomplete set of assignments ;
+; vin_rsc_z[1]   ; Incomplete set of assignments ;
+; vin_rsc_z[0]   ; Incomplete set of assignments ;
+; vin_rsc_z[28]  ; Incomplete set of assignments ;
+; vin_rsc_z[18]  ; Incomplete set of assignments ;
+; vin_rsc_z[27]  ; Incomplete set of assignments ;
+; vin_rsc_z[17]  ; Incomplete set of assignments ;
+; vin_rsc_z[26]  ; Incomplete set of assignments ;
+; vin_rsc_z[16]  ; Incomplete set of assignments ;
+; vin_rsc_z[25]  ; Incomplete set of assignments ;
+; vin_rsc_z[15]  ; Incomplete set of assignments ;
+; vin_rsc_z[24]  ; Incomplete set of assignments ;
+; vin_rsc_z[14]  ; Incomplete set of assignments ;
+; vin_rsc_z[23]  ; Incomplete set of assignments ;
+; vin_rsc_z[13]  ; Incomplete set of assignments ;
+; vin_rsc_z[22]  ; Incomplete set of assignments ;
+; vin_rsc_z[12]  ; Incomplete set of assignments ;
+; vin_rsc_z[21]  ; Incomplete set of assignments ;
+; vin_rsc_z[11]  ; Incomplete set of assignments ;
+; vin_rsc_z[20]  ; Incomplete set of assignments ;
+; vin_rsc_z[10]  ; Incomplete set of assignments ;
+; vin_rsc_z[9]   ; Incomplete set of assignments ;
+; vin_rsc_z[29]  ; Incomplete set of assignments ;
+; vin_rsc_z[19]  ; Incomplete set of assignments ;
+; vin_rsc_z[79]  ; Incomplete set of assignments ;
+; vin_rsc_z[69]  ; Incomplete set of assignments ;
+; vin_rsc_z[89]  ; Incomplete set of assignments ;
+; vin_rsc_z[59]  ; Incomplete set of assignments ;
+; vin_rsc_z[58]  ; Incomplete set of assignments ;
+; vin_rsc_z[49]  ; Incomplete set of assignments ;
+; vin_rsc_z[39]  ; Incomplete set of assignments ;
+; vin_rsc_z[48]  ; Incomplete set of assignments ;
+; vin_rsc_z[38]  ; Incomplete set of assignments ;
++----------------+-------------------------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+------------------------+
+; Type                ; Value                  ;
++---------------------+------------------------+
+; Placement (by node) ;                        ;
+;     -- Requested    ; 0 / 2389 ( 0.00 % )    ;
+;     -- Achieved     ; 0 / 2389 ( 0.00 % )    ;
+;                     ;                        ;
+; Routing (by net)    ;                        ;
+;     -- Requested    ; 0 / 0 ( 0.00 % )       ;
+;     -- Achieved     ; 0 / 0 ( 0.00 % )       ;
++---------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                             ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name                 ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Top                            ; 2379    ; 0                 ; N/A                     ; Source File       ;
+; hard_block:auto_generated_inst ; 10      ; 0                 ; N/A                     ; Source File       ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/output_files/sobel.pin.
+
+
++-----------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                         ;
++---------------------------------------------+-------------------------+
+; Resource                                    ; Usage                   ;
++---------------------------------------------+-------------------------+
+; Total logic elements                        ; 1,923 / 15,408 ( 12 % ) ;
+;     -- Combinational with no register       ; 1639                    ;
+;     -- Register only                        ; 76                      ;
+;     -- Combinational with a register        ; 208                     ;
+;                                             ;                         ;
+; Logic element usage by number of LUT inputs ;                         ;
+;     -- 4 input functions                    ; 172                     ;
+;     -- 3 input functions                    ; 1167                    ;
+;     -- <=2 input functions                  ; 508                     ;
+;     -- Register only                        ; 76                      ;
+;                                             ;                         ;
+; Logic elements by mode                      ;                         ;
+;     -- normal mode                          ; 630                     ;
+;     -- arithmetic mode                      ; 1217                    ;
+;                                             ;                         ;
+; Total registers*                            ; 284 / 17,068 ( 2 % )    ;
+;     -- Dedicated logic registers            ; 284 / 15,408 ( 2 % )    ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )       ;
+;                                             ;                         ;
+; Total LABs:  partially or completely used   ; 142 / 963 ( 15 % )      ;
+; Virtual pins                                ; 0                       ;
+; I/O pins                                    ; 123 / 347 ( 35 % )      ;
+;     -- Clock pins                           ; 3 / 8 ( 38 % )          ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )           ;
+;                                             ;                         ;
+; Global signals                              ; 2                       ;
+; M9Ks                                        ; 0 / 56 ( 0 % )          ;
+; Total block memory bits                     ; 0 / 516,096 ( 0 % )     ;
+; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )     ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )         ;
+; PLLs                                        ; 0 / 4 ( 0 % )           ;
+; Global clocks                               ; 2 / 20 ( 10 % )         ;
+; JTAGs                                       ; 0 / 1 ( 0 % )           ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )           ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )           ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )           ;
+; Average interconnect usage (total/H/V)      ; 3% / 3% / 3%            ;
+; Peak interconnect usage (total/H/V)         ; 16% / 15% / 18%         ;
+; Maximum fan-out                             ; 284                     ;
+; Highest non-global fan-out                  ; 255                     ;
+; Total fan-out                               ; 6309                    ;
+; Average fan-out                             ; 2.58                    ;
++---------------------------------------------+-------------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                          ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                   ; Top                   ; hard_block:auto_generated_inst ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                   ; Low                            ;
+;                                             ;                       ;                                ;
+; Total logic elements                        ; 1923 / 15408 ( 12 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 1639                  ; 0                              ;
+;     -- Register only                        ; 76                    ; 0                              ;
+;     -- Combinational with a register        ; 208                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic element usage by number of LUT inputs ;                       ;                                ;
+;     -- 4 input functions                    ; 172                   ; 0                              ;
+;     -- 3 input functions                    ; 1167                  ; 0                              ;
+;     -- <=2 input functions                  ; 508                   ; 0                              ;
+;     -- Register only                        ; 76                    ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic elements by mode                      ;                       ;                                ;
+;     -- normal mode                          ; 630                   ; 0                              ;
+;     -- arithmetic mode                      ; 1217                  ; 0                              ;
+;                                             ;                       ;                                ;
+; Total registers                             ; 284                   ; 0                              ;
+;     -- Dedicated logic registers            ; 284 / 15408 ( 2 % )   ; 0 / 15408 ( 0 % )              ;
+;                                             ;                       ;                                ;
+; Total LABs:  partially or completely used   ; 142 / 963 ( 15 % )    ; 0 / 963 ( 0 % )                ;
+;                                             ;                       ;                                ;
+; Virtual pins                                ; 0                     ; 0                              ;
+; I/O pins                                    ; 123                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 0                     ; 0                              ;
+; Total RAM block bits                        ; 0                     ; 0                              ;
+; Clock control block                         ; 2 / 24 ( 8 % )        ; 0 / 24 ( 0 % )                 ;
+;                                             ;                       ;                                ;
+; Connections                                 ;                       ;                                ;
+;     -- Input Connections                    ; 0                     ; 0                              ;
+;     -- Registered Input Connections         ; 0                     ; 0                              ;
+;     -- Output Connections                   ; 0                     ; 0                              ;
+;     -- Registered Output Connections        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Internal Connections                        ;                       ;                                ;
+;     -- Total Connections                    ; 6304                  ; 5                              ;
+;     -- Registered Connections               ; 419                   ; 0                              ;
+;                                             ;                       ;                                ;
+; External Connections                        ;                       ;                                ;
+;     -- Top                                  ; 0                     ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Partition Interface                         ;                       ;                                ;
+;     -- Input Ports                          ; 93                    ; 0                              ;
+;     -- Output Ports                         ; 30                    ; 0                              ;
+;     -- Bidir Ports                          ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Registered Ports                            ;                       ;                                ;
+;     -- Registered Input Ports               ; 0                     ; 0                              ;
+;     -- Registered Output Ports              ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Port Connectivity                           ;                       ;                                ;
+;     -- Input Ports driven by GND            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                     ; 0                              ;
++---------------------------------------------+-----------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                         ;
++---------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name          ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++---------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; arst_n        ; G1    ; 1        ; 0            ; 14           ; 7            ; 284                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; clk           ; G2    ; 1        ; 0            ; 14           ; 0            ; 284                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; en            ; T2    ; 2        ; 0            ; 14           ; 14           ; 255                   ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[0]  ; H12   ; 7        ; 26           ; 29           ; 0            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[10] ; N22   ; 5        ; 41           ; 13           ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[11] ; K19   ; 6        ; 41           ; 18           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[12] ; AB13  ; 4        ; 23           ; 0            ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[13] ; A15   ; 7        ; 26           ; 29           ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[14] ; B16   ; 7        ; 28           ; 29           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[15] ; Y10   ; 3        ; 19           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[16] ; M22   ; 5        ; 41           ; 13           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[17] ; M20   ; 5        ; 41           ; 14           ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[18] ; E13   ; 7        ; 23           ; 29           ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[19] ; AA10  ; 3        ; 19           ; 0            ; 0            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[1]  ; T12   ; 4        ; 28           ; 0            ; 28           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[20] ; A14   ; 7        ; 23           ; 29           ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[21] ; J15   ; 6        ; 41           ; 19           ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[22] ; G12   ; 7        ; 26           ; 29           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[23] ; L15   ; 6        ; 41           ; 17           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[24] ; K15   ; 6        ; 41           ; 18           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[25] ; C13   ; 7        ; 23           ; 29           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[26] ; N18   ; 5        ; 41           ; 13           ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[27] ; AA16  ; 4        ; 28           ; 0            ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[28] ; H22   ; 6        ; 41           ; 20           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[29] ; D13   ; 7        ; 23           ; 29           ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[2]  ; N21   ; 5        ; 41           ; 13           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[30] ; M5    ; 2        ; 0            ; 11           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[31] ; E11   ; 7        ; 21           ; 29           ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[32] ; P2    ; 2        ; 0            ; 11           ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[33] ; B9    ; 8        ; 14           ; 29           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[34] ; T11   ; 3        ; 16           ; 0            ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[35] ; AB9   ; 3        ; 16           ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[36] ; A8    ; 8        ; 14           ; 29           ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[37] ; G11   ; 8        ; 14           ; 29           ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[38] ; AA11  ; 3        ; 21           ; 0            ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[39] ; AA9   ; 3        ; 16           ; 0            ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[3]  ; M19   ; 5        ; 41           ; 14           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[40] ; E12   ; 7        ; 21           ; 29           ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[41] ; P1    ; 2        ; 0            ; 11           ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[42] ; P4    ; 2        ; 0            ; 10           ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[43] ; A9    ; 8        ; 16           ; 29           ; 28           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[44] ; D10   ; 8        ; 16           ; 29           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[45] ; A13   ; 7        ; 21           ; 29           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[46] ; E10   ; 8        ; 16           ; 29           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[47] ; B8    ; 8        ; 14           ; 29           ; 28           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[48] ; AA8   ; 3        ; 16           ; 0            ; 28           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[49] ; B10   ; 8        ; 16           ; 29           ; 21           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[4]  ; M21   ; 5        ; 41           ; 14           ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[50] ; A10   ; 8        ; 16           ; 29           ; 14           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[51] ; V11   ; 3        ; 19           ; 0            ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[52] ; W10   ; 3        ; 19           ; 0            ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[53] ; F11   ; 7        ; 21           ; 29           ; 28           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[54] ; U11   ; 3        ; 19           ; 0            ; 28           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[55] ; J22   ; 6        ; 41           ; 19           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[56] ; K21   ; 6        ; 41           ; 19           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[57] ; T1    ; 2        ; 0            ; 14           ; 21           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[58] ; L8    ; 1        ; 0            ; 22           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[59] ; H11   ; 8        ; 19           ; 29           ; 28           ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[5]  ; AB10  ; 3        ; 21           ; 0            ; 28           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[60] ; R22   ; 5        ; 41           ; 10           ; 14           ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[61] ; AA15  ; 4        ; 26           ; 0            ; 14           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[62] ; AB16  ; 4        ; 28           ; 0            ; 14           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[63] ; P20   ; 5        ; 41           ; 10           ; 0            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[64] ; R18   ; 5        ; 41           ; 9            ; 21           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[65] ; AB17  ; 4        ; 28           ; 0            ; 0            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[66] ; AA17  ; 4        ; 28           ; 0            ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[67] ; N5    ; 2        ; 0            ; 10           ; 14           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[68] ; R19   ; 5        ; 41           ; 9            ; 14           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[69] ; V12   ; 4        ; 23           ; 0            ; 0            ; 7                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[6]  ; W14   ; 4        ; 30           ; 0            ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[70] ; AB14  ; 4        ; 23           ; 0            ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[71] ; R21   ; 5        ; 41           ; 10           ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[72] ; AA13  ; 4        ; 23           ; 0            ; 28           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[73] ; AB15  ; 4        ; 26           ; 0            ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[74] ; L21   ; 6        ; 41           ; 18           ; 14           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[75] ; F13   ; 7        ; 26           ; 29           ; 14           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[76] ; AA14  ; 4        ; 23           ; 0            ; 14           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[77] ; R2    ; 2        ; 0            ; 10           ; 0            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[78] ; N16   ; 5        ; 41           ; 10           ; 21           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[79] ; B14   ; 7        ; 23           ; 29           ; 28           ; 6                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[7]  ; B13   ; 7        ; 21           ; 29           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[80] ; Y13   ; 4        ; 26           ; 0            ; 21           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[81] ; P22   ; 5        ; 41           ; 11           ; 0            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[82] ; N17   ; 5        ; 41           ; 12           ; 0            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[83] ; P21   ; 5        ; 41           ; 12           ; 21           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[84] ; N19   ; 5        ; 41           ; 12           ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[85] ; W13   ; 4        ; 26           ; 0            ; 28           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[86] ; U12   ; 4        ; 26           ; 0            ; 0            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[87] ; L7    ; 2        ; 0            ; 11           ; 0            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[88] ; N20   ; 5        ; 41           ; 12           ; 14           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[89] ; B15   ; 7        ; 26           ; 29           ; 28           ; 6                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[8]  ; L16   ; 6        ; 41           ; 17           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; vin_rsc_z[9]  ; M16   ; 5        ; 41           ; 14           ; 0            ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
++---------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++----------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name           ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++----------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; vout_rsc_z[0]  ; K7    ; 1        ; 0            ; 22           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[10] ; K8    ; 1        ; 0            ; 22           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[11] ; B4    ; 8        ; 5            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[12] ; E3    ; 1        ; 0            ; 26           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[13] ; J7    ; 1        ; 0            ; 22           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[14] ; M2    ; 2        ; 0            ; 13           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[15] ; H6    ; 1        ; 0            ; 25           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[16] ; F1    ; 1        ; 0            ; 23           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[17] ; H7    ; 1        ; 0            ; 25           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[18] ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[19] ; G3    ; 1        ; 0            ; 23           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[1]  ; J4    ; 1        ; 0            ; 21           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[20] ; M6    ; 2        ; 0            ; 13           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[21] ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[22] ; M1    ; 2        ; 0            ; 13           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[23] ; G4    ; 1        ; 0            ; 23           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[24] ; N1    ; 2        ; 0            ; 12           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[25] ; M3    ; 2        ; 0            ; 12           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[26] ; P3    ; 2        ; 0            ; 9            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[27] ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[28] ; L6    ; 2        ; 0            ; 13           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[29] ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[2]  ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[3]  ; J6    ; 1        ; 0            ; 24           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[4]  ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[5]  ; N2    ; 2        ; 0            ; 12           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[6]  ; D2    ; 1        ; 0            ; 25           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[7]  ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[8]  ; H2    ; 1        ; 0            ; 21           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; vout_rsc_z[9]  ; M4    ; 2        ; 0            ; 12           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
++----------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                                      ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                                 ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; D1       ; DIFFIO_L4n, DATA1, ASDO                  ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO              ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                                     ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                                    ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                                      ; -                        ; -                       ; Dedicated Programming Pin ;
+; N22      ; DIFFIO_R21n, DEV_OE                      ; Use as regular IO        ; vin_rsc_z[10]           ; Dual Purpose Pin          ;
+; N21      ; DIFFIO_R21p, DEV_CLRn                    ; Use as regular IO        ; vin_rsc_z[2]            ; Dual Purpose Pin          ;
+; M18      ; CONF_DONE                                ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L21      ; DIFFIO_R17p, CRC_ERROR                   ; Use as regular IO        ; vin_rsc_z[74]           ; Dual Purpose Pin          ;
+; K22      ; DIFFIO_R16n, nCEO                        ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
+; K21      ; DIFFIO_R16p, CLKUSR                      ; Use as regular IO        ; vin_rsc_z[56]           ; Dual Purpose Pin          ;
+; F13      ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8    ; Use as regular IO        ; vin_rsc_z[75]           ; Dual Purpose Pin          ;
+; A15      ; DIFFIO_T20n, PADD5                       ; Use as regular IO        ; vin_rsc_z[13]           ; Dual Purpose Pin          ;
+; B15      ; DIFFIO_T20p, PADD6                       ; Use as regular IO        ; vin_rsc_z[89]           ; Dual Purpose Pin          ;
+; C13      ; DIFFIO_T19n, PADD7                       ; Use as regular IO        ; vin_rsc_z[25]           ; Dual Purpose Pin          ;
+; D13      ; DIFFIO_T19p, PADD8                       ; Use as regular IO        ; vin_rsc_z[29]           ; Dual Purpose Pin          ;
+; A14      ; DIFFIO_T18n, PADD9                       ; Use as regular IO        ; vin_rsc_z[20]           ; Dual Purpose Pin          ;
+; B14      ; DIFFIO_T18p, PADD10                      ; Use as regular IO        ; vin_rsc_z[79]           ; Dual Purpose Pin          ;
+; A13      ; DIFFIO_T17n, PADD11                      ; Use as regular IO        ; vin_rsc_z[45]           ; Dual Purpose Pin          ;
+; B13      ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9   ; Use as regular IO        ; vin_rsc_z[7]            ; Dual Purpose Pin          ;
+; E11      ; DIFFIO_T16n, PADD13                      ; Use as regular IO        ; vin_rsc_z[31]           ; Dual Purpose Pin          ;
+; F11      ; DIFFIO_T16p, PADD14                      ; Use as regular IO        ; vin_rsc_z[53]           ; Dual Purpose Pin          ;
+; B10      ; DIFFIO_T14p, PADD15                      ; Use as regular IO        ; vin_rsc_z[49]           ; Dual Purpose Pin          ;
+; A9       ; DIFFIO_T13n, PADD16                      ; Use as regular IO        ; vin_rsc_z[43]           ; Dual Purpose Pin          ;
+; B9       ; DIFFIO_T13p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO        ; vin_rsc_z[33]           ; Dual Purpose Pin          ;
+; A8       ; DIFFIO_T12n, DATA2                       ; Use as regular IO        ; vin_rsc_z[36]           ; Dual Purpose Pin          ;
+; B8       ; DIFFIO_T12p, DATA3                       ; Use as regular IO        ; vin_rsc_z[47]           ; Dual Purpose Pin          ;
+; B4       ; DIFFIO_T5p, DATA8                        ; Use as regular IO        ; vout_rsc_z[11]          ; Dual Purpose Pin          ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 27 / 33 ( 82 % ) ; 2.5V          ; --           ;
+; 2        ; 18 / 48 ( 38 % ) ; 2.5V          ; --           ;
+; 3        ; 11 / 46 ( 24 % ) ; 2.5V          ; --           ;
+; 4        ; 16 / 41 ( 39 % ) ; 2.5V          ; --           ;
+; 5        ; 19 / 46 ( 41 % ) ; 2.5V          ; --           ;
+; 6        ; 10 / 43 ( 23 % ) ; 2.5V          ; --           ;
+; 7        ; 16 / 47 ( 34 % ) ; 2.5V          ; --           ;
+; 8        ; 11 / 43 ( 26 % ) ; 2.5V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 332        ; 8        ; vin_rsc_z[36]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; A9       ; 328        ; 8        ; vin_rsc_z[43]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; A10      ; 326        ; 8        ; vin_rsc_z[50]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; vin_rsc_z[45]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; A14      ; 312        ; 7        ; vin_rsc_z[20]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; A15      ; 307        ; 7        ; vin_rsc_z[13]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA8      ; 123        ; 3        ; vin_rsc_z[48]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AA9      ; 126        ; 3        ; vin_rsc_z[39]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AA10     ; 132        ; 3        ; vin_rsc_z[19]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AA11     ; 134        ; 3        ; vin_rsc_z[38]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; vin_rsc_z[72]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AA14     ; 140        ; 4        ; vin_rsc_z[76]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AA15     ; 145        ; 4        ; vin_rsc_z[61]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AA16     ; 149        ; 4        ; vin_rsc_z[27]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AA17     ; 151        ; 4        ; vin_rsc_z[66]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; vin_rsc_z[35]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AB10     ; 133        ; 3        ; vin_rsc_z[5]                                              ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; vin_rsc_z[12]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AB14     ; 141        ; 4        ; vin_rsc_z[70]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AB15     ; 146        ; 4        ; vin_rsc_z[73]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AB16     ; 150        ; 4        ; vin_rsc_z[62]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AB17     ; 152        ; 4        ; vin_rsc_z[65]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B2       ; 1          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B4       ; 351        ; 8        ; vout_rsc_z[11]                                            ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B8       ; 333        ; 8        ; vin_rsc_z[47]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; B9       ; 329        ; 8        ; vin_rsc_z[33]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; B10      ; 327        ; 8        ; vin_rsc_z[49]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; vin_rsc_z[7]                                              ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; B14      ; 313        ; 7        ; vin_rsc_z[79]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; B15      ; 308        ; 7        ; vin_rsc_z[89]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; B16      ; 299        ; 7        ; vin_rsc_z[14]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; vout_rsc_z[29]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; C2       ; 6          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; vin_rsc_z[25]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; vout_rsc_z[6]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; vin_rsc_z[44]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; vin_rsc_z[29]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; vout_rsc_z[27]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; vout_rsc_z[12]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; E4       ; 4          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E10      ; 325        ; 8        ; vin_rsc_z[46]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; E11      ; 317        ; 7        ; vin_rsc_z[31]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; E12      ; 316        ; 7        ; vin_rsc_z[40]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; E13      ; 311        ; 7        ; vin_rsc_z[18]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; vout_rsc_z[16]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F2       ; 15         ; 1        ; vout_rsc_z[4]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F11      ; 318        ; 7        ; vin_rsc_z[53]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F13      ; 306        ; 7        ; vin_rsc_z[75]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; arst_n                                                    ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; G2       ; 38         ; 1        ; clk                                                       ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; G3       ; 18         ; 1        ; vout_rsc_z[19]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; G4       ; 17         ; 1        ; vout_rsc_z[23]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; G5       ; 3          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G11      ; 331        ; 8        ; vin_rsc_z[37]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; G12      ; 305        ; 7        ; vin_rsc_z[22]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; vout_rsc_z[21]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; vout_rsc_z[8]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H6       ; 11         ; 1        ; vout_rsc_z[15]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; H7       ; 10         ; 1        ; vout_rsc_z[17]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H11      ; 323        ; 8        ; vin_rsc_z[59]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; H12      ; 304        ; 7        ; vin_rsc_z[0]                                              ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H22      ; 245        ; 6        ; vin_rsc_z[28]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; J1       ; 29         ; 1        ; vout_rsc_z[2]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; vout_rsc_z[7]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; vout_rsc_z[18]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; vout_rsc_z[1]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; vout_rsc_z[3]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; J7       ; 22         ; 1        ; vout_rsc_z[13]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; vin_rsc_z[21]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J22      ; 241        ; 6        ; vin_rsc_z[55]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; vout_rsc_z[0]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K8       ; 21         ; 1        ; vout_rsc_z[10]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; vin_rsc_z[24]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K19      ; 237        ; 6        ; vin_rsc_z[11]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; vin_rsc_z[56]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; vout_rsc_z[28]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L7       ; 50         ; 2        ; vin_rsc_z[87]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L8       ; 20         ; 1        ; vin_rsc_z[58]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; vin_rsc_z[23]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L16      ; 232        ; 6        ; vin_rsc_z[8]                                              ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; vin_rsc_z[74]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ; 45         ; 2        ; vout_rsc_z[22]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M2       ; 44         ; 2        ; vout_rsc_z[14]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M3       ; 47         ; 2        ; vout_rsc_z[25]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M4       ; 46         ; 2        ; vout_rsc_z[9]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M5       ; 51         ; 2        ; vin_rsc_z[30]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M6       ; 43         ; 2        ; vout_rsc_z[20]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; vin_rsc_z[9]                                              ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; vin_rsc_z[3]                                              ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M20      ; 220        ; 5        ; vin_rsc_z[17]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M21      ; 219        ; 5        ; vin_rsc_z[4]                                              ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M22      ; 218        ; 5        ; vin_rsc_z[16]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N1       ; 49         ; 2        ; vout_rsc_z[24]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N2       ; 48         ; 2        ; vout_rsc_z[5]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; vin_rsc_z[67]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; vin_rsc_z[78]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N17      ; 214        ; 5        ; vin_rsc_z[82]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N18      ; 215        ; 5        ; vin_rsc_z[26]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N19      ; 213        ; 5        ; vin_rsc_z[84]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N20      ; 212        ; 5        ; vin_rsc_z[88]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N21      ; 217        ; 5        ; vin_rsc_z[2]                                              ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N22      ; 216        ; 5        ; vin_rsc_z[10]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; P1       ; 53         ; 2        ; vin_rsc_z[41]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; P2       ; 52         ; 2        ; vin_rsc_z[32]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; P3       ; 58         ; 2        ; vout_rsc_z[26]                                            ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; P4       ; 57         ; 2        ; vin_rsc_z[42]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; vin_rsc_z[63]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; P21      ; 211        ; 5        ; vin_rsc_z[83]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; P22      ; 210        ; 5        ; vin_rsc_z[81]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; vin_rsc_z[77]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; vin_rsc_z[64]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; R19      ; 204        ; 5        ; vin_rsc_z[68]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; vin_rsc_z[71]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; R22      ; 206        ; 5        ; vin_rsc_z[60]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; T1       ; 41         ; 2        ; vin_rsc_z[57]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; T2       ; 40         ; 2        ; en                                                        ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T11      ; 125        ; 3        ; vin_rsc_z[34]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; T12      ; 148        ; 4        ; vin_rsc_z[1]                                              ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U11      ; 128        ; 3        ; vin_rsc_z[54]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; U12      ; 147        ; 4        ; vin_rsc_z[86]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; vin_rsc_z[51]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; V12      ; 142        ; 4        ; vin_rsc_z[69]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; vin_rsc_z[52]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; vin_rsc_z[85]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; W14      ; 155        ; 4        ; vin_rsc_z[6]                                              ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; vin_rsc_z[15]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; vin_rsc_z[80]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                ;
++---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node      ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                 ; Library Name ;
++---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------+--------------+
+; |sobel                          ; 1923 (0)    ; 284 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 123  ; 0            ; 1639 (0)     ; 76 (0)            ; 208 (0)          ; |sobel                                                              ; work         ;
+;    |sobel_core:sobel_core_inst| ; 1923 (1885) ; 284 (284)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1639 (1601)  ; 76 (76)           ; 208 (207)        ; |sobel|sobel_core:sobel_core_inst                                   ; work         ;
+;       |lpm_mult:Mult0|          ; 2 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult0                    ; work         ;
+;          |multcore:mult_core|   ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult0|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult1|          ; 5 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult1                    ; work         ;
+;          |multcore:mult_core|   ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult1|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult2|          ; 2 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 1 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult2                    ; work         ;
+;          |multcore:mult_core|   ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult2|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult3|          ; 6 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult3                    ; work         ;
+;          |multcore:mult_core|   ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult4|          ; 6 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult4                    ; work         ;
+;          |multcore:mult_core|   ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult5|          ; 6 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult5                    ; work         ;
+;          |multcore:mult_core|   ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult6|          ; 4 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (0)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult6                    ; work         ;
+;          |multcore:mult_core|   ; 4 (4)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult7|          ; 2 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult7                    ; work         ;
+;          |multcore:mult_core|   ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult7|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult8|          ; 6 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult8                    ; work         ;
+;          |multcore:mult_core|   ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult8|multcore:mult_core ; work         ;
++---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                            ;
++----------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name           ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++----------------+----------+---------------+---------------+-----------------------+-----+------+
+; vout_rsc_z[0]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[1]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[2]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[3]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[4]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[5]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[6]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[7]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[8]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[9]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[10] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[11] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[12] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[13] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[14] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[15] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[16] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[17] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[18] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[19] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[20] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[21] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[22] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[23] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[24] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[25] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[26] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[27] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[28] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; vout_rsc_z[29] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; clk            ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; arst_n         ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; en             ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[57]  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[56]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[55]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[54]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[53]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[52]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[51]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[50]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[47]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[37]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[46]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[36]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[45]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[35]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[44]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[34]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[43]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[33]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[42]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[32]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[41]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[31]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[40]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[30]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[78]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[68]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[77]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[67]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[76]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[66]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[75]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[65]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[74]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[64]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[73]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[63]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[72]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[62]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[71]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[61]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[70]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[60]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[88]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[87]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[86]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[85]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[84]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[83]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[82]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[81]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[80]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[8]   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[7]   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[6]   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[5]   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[4]   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[3]   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[2]   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[1]   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[0]   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[28]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[18]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[27]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[17]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[26]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[16]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[25]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[15]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[24]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[14]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[23]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[13]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[22]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[12]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[21]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[11]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[20]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[10]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[9]   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[29]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[19]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[79]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[69]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[89]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[59]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[58]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[49]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[39]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; vin_rsc_z[48]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; vin_rsc_z[38]  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
++----------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                                     ;
++----------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                                  ; Pad To Core Index ; Setting ;
++----------------------------------------------------------------------+-------------------+---------+
+; clk                                                                  ;                   ;         ;
+; arst_n                                                               ;                   ;         ;
+; en                                                                   ;                   ;         ;
+; vin_rsc_z[57]                                                        ;                   ;         ;
+; vin_rsc_z[56]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add46~12                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[56]        ; 0                 ; 6       ;
+; vin_rsc_z[55]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add46~10                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[55]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[54]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add46~8                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[54]        ; 0                 ; 6       ;
+; vin_rsc_z[53]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add46~6                            ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[53]        ; 1                 ; 6       ;
+; vin_rsc_z[52]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add46~4                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[52]        ; 0                 ; 6       ;
+; vin_rsc_z[51]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add46~2                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[51]        ; 0                 ; 6       ;
+; vin_rsc_z[50]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[0]~0     ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add46~1                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[50]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[47]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~14                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[47]        ; 1                 ; 6       ;
+; vin_rsc_z[37]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~14                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[37]        ; 0                 ; 6       ;
+; vin_rsc_z[46]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~12                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[46]        ; 0                 ; 6       ;
+; vin_rsc_z[36]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~12                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[36]~feeder ; 1                 ; 6       ;
+; vin_rsc_z[45]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~10                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[45]        ; 1                 ; 6       ;
+; vin_rsc_z[35]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~10                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[35]        ; 1                 ; 6       ;
+; vin_rsc_z[44]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~8                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[44]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[34]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~8                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[34]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[43]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~6                            ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[43]~feeder ; 1                 ; 6       ;
+; vin_rsc_z[33]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~6                            ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[33]        ; 1                 ; 6       ;
+; vin_rsc_z[42]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~4                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[42]        ; 0                 ; 6       ;
+; vin_rsc_z[32]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~4                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[32]        ; 0                 ; 6       ;
+; vin_rsc_z[41]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~2                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[41]        ; 0                 ; 6       ;
+; vin_rsc_z[31]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~2                            ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[31]        ; 1                 ; 6       ;
+; vin_rsc_z[40]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~0                            ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[40]        ; 1                 ; 6       ;
+; vin_rsc_z[30]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~0                            ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[30]        ; 1                 ; 6       ;
+; vin_rsc_z[78]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add25~16                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~16                          ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[78]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[68]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add25~16                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add131~16                          ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[68]        ; 0                 ; 6       ;
+; vin_rsc_z[77]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[77]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~14                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~14                          ; 0                 ; 6       ;
+; vin_rsc_z[67]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[67]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~14                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add131~14                          ; 0                 ; 6       ;
+; vin_rsc_z[76]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[76]        ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~12                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~12                          ; 1                 ; 6       ;
+; vin_rsc_z[66]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add25~12                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add131~12                          ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[66]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[75]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[75]        ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~10                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~10                          ; 1                 ; 6       ;
+; vin_rsc_z[65]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[65]        ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~10                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add131~10                          ; 1                 ; 6       ;
+; vin_rsc_z[74]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add25~8                            ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~8                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[74]~feeder ; 1                 ; 6       ;
+; vin_rsc_z[64]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[64]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~8                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add131~8                           ; 0                 ; 6       ;
+; vin_rsc_z[73]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[73]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~6                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~6                           ; 0                 ; 6       ;
+; vin_rsc_z[63]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[63]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~6                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add131~6                           ; 0                 ; 6       ;
+; vin_rsc_z[72]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[72]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~4                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~4                           ; 0                 ; 6       ;
+; vin_rsc_z[62]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[62]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~4                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add131~4                           ; 0                 ; 6       ;
+; vin_rsc_z[71]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add25~2                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~2                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[71]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[61]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add25~2                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add131~2                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[61]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[70]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add130~0                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~0                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[70]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[60]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add132~0                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~0                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add131~1                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[60]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[88]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add26~16                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~16                          ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[88]        ; 0                 ; 6       ;
+; vin_rsc_z[87]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[87]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add26~14                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~14                          ; 0                 ; 6       ;
+; vin_rsc_z[86]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[86]        ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add26~12                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~12                          ; 1                 ; 6       ;
+; vin_rsc_z[85]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[85]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add26~10                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~10                          ; 0                 ; 6       ;
+; vin_rsc_z[84]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[84]        ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add26~8                            ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~8                           ; 1                 ; 6       ;
+; vin_rsc_z[83]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[83]        ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add26~6                            ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~6                           ; 1                 ; 6       ;
+; vin_rsc_z[82]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[82]        ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add26~4                            ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~4                           ; 1                 ; 6       ;
+; vin_rsc_z[81]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[81]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add26~2                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~2                           ; 0                 ; 6       ;
+; vin_rsc_z[80]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[80]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add26~0                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~0                           ; 0                 ; 6       ;
+; vin_rsc_z[8]                                                         ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add43~16                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[8]         ; 0                 ; 6       ;
+; vin_rsc_z[7]                                                         ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[7]         ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add43~14                           ; 0                 ; 6       ;
+; vin_rsc_z[6]                                                         ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[6]         ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add43~12                           ; 1                 ; 6       ;
+; vin_rsc_z[5]                                                         ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[5]         ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add43~10                           ; 0                 ; 6       ;
+; vin_rsc_z[4]                                                         ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[4]         ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add43~8                            ; 1                 ; 6       ;
+; vin_rsc_z[3]                                                         ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[3]         ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add43~6                            ; 0                 ; 6       ;
+; vin_rsc_z[2]                                                         ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add43~4                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[2]~feeder  ; 0                 ; 6       ;
+; vin_rsc_z[1]                                                         ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[1]         ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add43~2                            ; 0                 ; 6       ;
+; vin_rsc_z[0]                                                         ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[0]         ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add44~0                            ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add43~1                            ; 1                 ; 6       ;
+; vin_rsc_z[28]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add42~16                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[28]        ; 1                 ; 6       ;
+; vin_rsc_z[18]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add42~16                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[18]        ; 1                 ; 6       ;
+; vin_rsc_z[27]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[27]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~14                           ; 0                 ; 6       ;
+; vin_rsc_z[17]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[17]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~14                           ; 0                 ; 6       ;
+; vin_rsc_z[26]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[26]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~12                           ; 0                 ; 6       ;
+; vin_rsc_z[16]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[16]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~12                           ; 0                 ; 6       ;
+; vin_rsc_z[25]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[25]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~10                           ; 0                 ; 6       ;
+; vin_rsc_z[15]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[15]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~10                           ; 0                 ; 6       ;
+; vin_rsc_z[24]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[24]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~8                            ; 0                 ; 6       ;
+; vin_rsc_z[14]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[14]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~8                            ; 0                 ; 6       ;
+; vin_rsc_z[23]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[23]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~6                            ; 0                 ; 6       ;
+; vin_rsc_z[13]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[13]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~6                            ; 0                 ; 6       ;
+; vin_rsc_z[22]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add42~4                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[22]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[12]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add42~4                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[12]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[21]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[21]        ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~2                            ; 1                 ; 6       ;
+; vin_rsc_z[11]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add42~2                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[11]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[20]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[20]        ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~0                            ; 0                 ; 6       ;
+; vin_rsc_z[10]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add42~0                            ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[10]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[9]                                                         ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add43~22                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add43~20                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add43~18                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[9]         ; 0                 ; 6       ;
+; vin_rsc_z[29]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add42~20                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~18                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[29]        ; 1                 ; 6       ;
+; vin_rsc_z[19]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add42~20                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add42~18                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[19]        ; 1                 ; 6       ;
+; vin_rsc_z[79]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add25~20                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~22                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~18                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~20                          ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~18                          ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[79]        ; 0                 ; 6       ;
+; vin_rsc_z[69]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add25~20                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~22                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add25~18                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add131~22                          ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add131~20                          ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add131~18                          ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[69]        ; 1                 ; 6       ;
+; vin_rsc_z[89]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add26~20                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add26~22                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add26~18                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~20                          ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add130~18                          ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[89]        ; 0                 ; 6       ;
+; vin_rsc_z[59]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add46~18                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add46~22                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add46~20                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[59]~feeder ; 0                 ; 6       ;
+; vin_rsc_z[58]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add46~16                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[58]        ; 1                 ; 6       ;
+; vin_rsc_z[49]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~18                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add45~20                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[49]~feeder ; 1                 ; 6       ;
+; vin_rsc_z[39]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~18                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|Add45~20                           ; 1                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[39]        ; 1                 ; 6       ;
+; vin_rsc_z[48]                                                        ;                   ;         ;
+;      - sobel_core:sobel_core_inst|Add45~16                           ; 0                 ; 6       ;
+;      - sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[48]        ; 0                 ; 6       ;
+; vin_rsc_z[38]                                                        ;                   ;         ;
++----------------------------------------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                        ;
++-----------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; Name                                                      ; Location           ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-----------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; arst_n                                                    ; PIN_G1             ; 284     ; Async. clear ; yes    ; Global Clock         ; GCLK2            ; --                        ;
+; clk                                                       ; PIN_G2             ; 284     ; Clock        ; yes    ; Global Clock         ; GCLK4            ; --                        ;
+; en                                                        ; PIN_T2             ; 255     ; Clock enable ; no     ; --                   ; --               ; --                        ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[0]~0 ; LCCOMB_X14_Y20_N10 ; 30      ; Clock enable ; no     ; --                   ; --               ; --                        ;
++-----------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                              ;
++--------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name   ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++--------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; arst_n ; PIN_G1   ; 284     ; 0                                    ; Global Clock         ; GCLK2            ; --                        ;
+; clk    ; PIN_G2   ; 284     ; 33                                   ; Global Clock         ; GCLK4            ; --                        ;
++--------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals                                                        ;
++------------------------------------------------------------------------------+---------+
+; Name                                                                         ; Fan-Out ;
++------------------------------------------------------------------------------+---------+
+; en~input                                                                     ; 255     ;
+; sobel_core:sobel_core_inst|Add44~22                                          ; 53      ;
+; sobel_core:sobel_core_inst|Add29~22                                          ; 41      ;
+; sobel_core:sobel_core_inst|Add21~22                                          ; 37      ;
+; sobel_core:sobel_core_inst|Add26~22                                          ; 34      ;
+; sobel_core:sobel_core_inst|ACC1_acc_516_cse[1]~0                             ; 34      ;
+; sobel_core:sobel_core_inst|Add34~22                                          ; 34      ;
+; sobel_core:sobel_core_inst|ACC1_acc_553_ncse[2]~0                            ; 33      ;
+; sobel_core:sobel_core_inst|ACC1_acc_724_cse[1]~0                             ; 33      ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[11]~22                  ; 31      ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[0]~0                    ; 30      ;
+; sobel_core:sobel_core_inst|Add132~22                                         ; 30      ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_2_sva[3]~6                    ; 17      ;
+; sobel_core:sobel_core_inst|Add44~14                                          ; 15      ;
+; sobel_core:sobel_core_inst|Add44~18                                          ; 13      ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_2_sva[3]~6                    ; 12      ;
+; sobel_core:sobel_core_inst|Add21~18                                          ; 12      ;
+; sobel_core:sobel_core_inst|Add21~14                                          ; 12      ;
+; sobel_core:sobel_core_inst|Add13~28                                          ; 12      ;
+; sobel_core:sobel_core_inst|Add125~0                                          ; 11      ;
+; sobel_core:sobel_core_inst|nl_ACC1_3_acc_212_psp_sva[3]~6                    ; 11      ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_384_itm[4]~6                          ; 11      ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_375_itm[4]~6                          ; 11      ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_375_itm[2]~2                          ; 11      ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_412_itm[3]~4                          ; 11      ;
+; sobel_core:sobel_core_inst|Add44~6                                           ; 11      ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_346_itm[4]~6                          ; 10      ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[8]~16                     ; 10      ;
+; sobel_core:sobel_core_inst|nl_ACC1_1_acc_208_psp_sva[2]~4                    ; 10      ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_1_sva[3]~6                    ; 10      ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_2_sva[2]~4                    ; 10      ;
+; sobel_core:sobel_core_inst|Add44~8                                           ; 10      ;
+; sobel_core:sobel_core_inst|nl_ACC1_3_acc_212_psp_sva[2]~4                    ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_384_itm[3]~4                          ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_384_itm[2]~2                          ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[10]~20                    ; 9       ;
+; sobel_core:sobel_core_inst|Add132~14                                         ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[8]~16                   ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_1_acc_208_psp_sva[3]~6                    ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_375_itm[3]~4                          ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[10]~20                    ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[8]~16                     ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_2_sva[1]~2                    ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_412_itm[4]~6                          ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_412_itm[2]~2                          ; 9       ;
+; sobel_core:sobel_core_inst|Add44~16                                          ; 9       ;
+; sobel_core:sobel_core_inst|Add44~10                                          ; 9       ;
+; sobel_core:sobel_core_inst|Add34~14                                          ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[6]~12                   ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[6]~12                     ; 9       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[4]~8                      ; 9       ;
+; sobel_core:sobel_core_inst|Add57~0                                           ; 8       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_346_itm[3]~4                          ; 8       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_346_itm[2]~2                          ; 8       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[10]~20                  ; 8       ;
+; sobel_core:sobel_core_inst|Add132~18                                         ; 8       ;
+; sobel_core:sobel_core_inst|nl_ACC1_1_acc_208_psp_sva[1]~2                    ; 8       ;
+; sobel_core:sobel_core_inst|Add21~12                                          ; 8       ;
+; sobel_core:sobel_core_inst|Add21~10                                          ; 8       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_375_itm[1]~0                          ; 8       ;
+; sobel_core:sobel_core_inst|Add44~20                                          ; 8       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_412_itm[1]~0                          ; 8       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[10]~20                    ; 8       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_1_sva[3]~6                    ; 8       ;
+; sobel_core:sobel_core_inst|Add44~2                                           ; 8       ;
+; sobel_core:sobel_core_inst|Add26~14                                          ; 8       ;
+; sobel_core:sobel_core_inst|Add29~14                                          ; 8       ;
+; sobel_core:sobel_core_inst|Add29~10                                          ; 8       ;
+; sobel_core:sobel_core_inst|Add13~20                                          ; 8       ;
+; vin_rsc_z[69]~input                                                          ; 7       ;
+; sobel_core:sobel_core_inst|Add262~0                                          ; 7       ;
+; sobel_core:sobel_core_inst|Add98~0                                           ; 7       ;
+; sobel_core:sobel_core_inst|nl_ACC1_3_acc_212_psp_sva[1]~2                    ; 7       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_2_sva[1]~2                    ; 7       ;
+; sobel_core:sobel_core_inst|Add132~16                                         ; 7       ;
+; sobel_core:sobel_core_inst|nl_ACC1_1_acc_208_psp_sva[0]~0                    ; 7       ;
+; sobel_core:sobel_core_inst|Add26~18                                          ; 7       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_1_sva[2]~4                    ; 7       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_1_sva[1]~2                    ; 7       ;
+; sobel_core:sobel_core_inst|Add21~16                                          ; 7       ;
+; sobel_core:sobel_core_inst|Add29~18                                          ; 7       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_2_sva[0]~0                    ; 7       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[8]~16                     ; 7       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_1_sva[2]~4                    ; 7       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_1_sva[1]~2                    ; 7       ;
+; sobel_core:sobel_core_inst|Add34~18                                          ; 7       ;
+; sobel_core:sobel_core_inst|Add44~12                                          ; 7       ;
+; sobel_core:sobel_core_inst|Add44~4                                           ; 7       ;
+; sobel_core:sobel_core_inst|Add26~10                                          ; 7       ;
+; sobel_core:sobel_core_inst|Add34~10                                          ; 7       ;
+; sobel_core:sobel_core_inst|Add13~26                                          ; 7       ;
+; sobel_core:sobel_core_inst|Add13~22                                          ; 7       ;
+; vin_rsc_z[89]~input                                                          ; 6       ;
+; vin_rsc_z[79]~input                                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add416~2                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add418~1                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add418~0                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add150~1                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add148~1                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add150~0                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add229~2                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add231~1                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add231~0                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add125~1                                          ; 6       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[9]                ; 6       ;
+; sobel_core:sobel_core_inst|Add221~2                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add223~1                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add223~0                                          ; 6       ;
+; sobel_core:sobel_core_inst|nl_ACC1_3_acc_212_psp_sva[0]~0                    ; 6       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_384_itm[1]~0                          ; 6       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_2_sva[2]~4                    ; 6       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_2_sva[0]~0                    ; 6       ;
+; sobel_core:sobel_core_inst|Add132~20                                         ; 6       ;
+; sobel_core:sobel_core_inst|Add132~8                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add132~6                                          ; 6       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_1_sva[0]~0                    ; 6       ;
+; sobel_core:sobel_core_inst|Add21~20                                          ; 6       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_1_sva[0]~0                    ; 6       ;
+; sobel_core:sobel_core_inst|Add26~16                                          ; 6       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[6]~12                     ; 6       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[4]~8                      ; 6       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[6]~12                     ; 6       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[4]~8                      ; 6       ;
+; sobel_core:sobel_core_inst|Add34~16                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add29~16                                          ; 6       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[4]~8                    ; 6       ;
+; sobel_core:sobel_core_inst|Add13~24                                          ; 6       ;
+; sobel_core:sobel_core_inst|Add148~2                                          ; 5       ;
+; sobel_core:sobel_core_inst|Add318~0                                          ; 5       ;
+; sobel_core:sobel_core_inst|Add319~0                                          ; 5       ;
+; sobel_core:sobel_core_inst|Add94~1                                           ; 5       ;
+; sobel_core:sobel_core_inst|Add58~0                                           ; 5       ;
+; sobel_core:sobel_core_inst|Add96~0                                           ; 5       ;
+; sobel_core:sobel_core_inst|Add416~1                                          ; 5       ;
+; sobel_core:sobel_core_inst|Add238~1                                          ; 5       ;
+; sobel_core:sobel_core_inst|ACC1_1_and_3_cse_sva~0                            ; 5       ;
+; sobel_core:sobel_core_inst|Add229~1                                          ; 5       ;
+; sobel_core:sobel_core_inst|Add85~0                                           ; 5       ;
+; sobel_core:sobel_core_inst|Add212~1                                          ; 5       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[9]                  ; 5       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[9]                ; 5       ;
+; sobel_core:sobel_core_inst|Add221~1                                          ; 5       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_346_itm[1]~0                          ; 5       ;
+; sobel_core:sobel_core_inst|Add132~12                                         ; 5       ;
+; sobel_core:sobel_core_inst|Add132~10                                         ; 5       ;
+; sobel_core:sobel_core_inst|Add26~12                                          ; 5       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[3]~6                      ; 5       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[1]~2                      ; 5       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[5]~10                     ; 5       ;
+; sobel_core:sobel_core_inst|Add34~12                                          ; 5       ;
+; sobel_core:sobel_core_inst|Add29~12                                          ; 5       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[5]~10                   ; 5       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[5]~10                     ; 5       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[3]~6                      ; 5       ;
+; vin_rsc_z[59]~input                                                          ; 4       ;
+; vin_rsc_z[9]~input                                                           ; 4       ;
+; vin_rsc_z[60]~input                                                          ; 4       ;
+; sobel_core:sobel_core_inst|Add317~0                                          ; 4       ;
+; sobel_core:sobel_core_inst|Add103~0                                          ; 4       ;
+; sobel_core:sobel_core_inst|Add91~0                                           ; 4       ;
+; sobel_core:sobel_core_inst|Add100~0                                          ; 4       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core|romout[0][1]~0  ; 4       ;
+; sobel_core:sobel_core_inst|Add238~0                                          ; 4       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core|romout[0][3]~1  ; 4       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[89]                       ; 4       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[79]                       ; 4       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[69]                       ; 4       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[29]                       ; 4       ;
+; sobel_core:sobel_core_inst|Add129~0                                          ; 4       ;
+; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1                         ; 4       ;
+; sobel_core:sobel_core_inst|Add168~14                                         ; 4       ;
+; sobel_core:sobel_core_inst|Add192~14                                         ; 4       ;
+; sobel_core:sobel_core_inst|Add216~18                                         ; 4       ;
+; sobel_core:sobel_core_inst|Add214~12                                         ; 4       ;
+; sobel_core:sobel_core_inst|Add132~2                                          ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[9]~18                   ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[9]~18                     ; 4       ;
+; sobel_core:sobel_core_inst|Add26~20                                          ; 4       ;
+; sobel_core:sobel_core_inst|Add21~8                                           ; 4       ;
+; sobel_core:sobel_core_inst|Add21~6                                           ; 4       ;
+; sobel_core:sobel_core_inst|Add21~2                                           ; 4       ;
+; sobel_core:sobel_core_inst|Add29~20                                          ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[9]~18                     ; 4       ;
+; sobel_core:sobel_core_inst|Add34~20                                          ; 4       ;
+; sobel_core:sobel_core_inst|Add26~8                                           ; 4       ;
+; sobel_core:sobel_core_inst|Add26~6                                           ; 4       ;
+; sobel_core:sobel_core_inst|Add26~2                                           ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[5]~10                     ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[2]~4                      ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[0]~0                      ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[7]~14                     ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[3]~6                      ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[2]~4                      ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[0]~0                      ; 4       ;
+; sobel_core:sobel_core_inst|Add34~8                                           ; 4       ;
+; sobel_core:sobel_core_inst|Add34~6                                           ; 4       ;
+; sobel_core:sobel_core_inst|Add34~2                                           ; 4       ;
+; sobel_core:sobel_core_inst|Add29~8                                           ; 4       ;
+; sobel_core:sobel_core_inst|Add29~6                                           ; 4       ;
+; sobel_core:sobel_core_inst|Add29~2                                           ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[7]~14                   ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[3]~6                    ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[2]~4                    ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[0]~0                    ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[7]~14                     ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[2]~4                      ; 4       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[0]~0                      ; 4       ;
+; sobel_core:sobel_core_inst|Add4~12                                           ; 4       ;
+; sobel_core:sobel_core_inst|nl_acc_imod_24_sva[5]~10                          ; 4       ;
+; vin_rsc_z[39]~input                                                          ; 3       ;
+; vin_rsc_z[49]~input                                                          ; 3       ;
+; vin_rsc_z[19]~input                                                          ; 3       ;
+; vin_rsc_z[29]~input                                                          ; 3       ;
+; vin_rsc_z[0]~input                                                           ; 3       ;
+; vin_rsc_z[80]~input                                                          ; 3       ;
+; vin_rsc_z[81]~input                                                          ; 3       ;
+; vin_rsc_z[82]~input                                                          ; 3       ;
+; vin_rsc_z[83]~input                                                          ; 3       ;
+; vin_rsc_z[84]~input                                                          ; 3       ;
+; vin_rsc_z[85]~input                                                          ; 3       ;
+; vin_rsc_z[86]~input                                                          ; 3       ;
+; vin_rsc_z[87]~input                                                          ; 3       ;
+; vin_rsc_z[88]~input                                                          ; 3       ;
+; vin_rsc_z[70]~input                                                          ; 3       ;
+; vin_rsc_z[61]~input                                                          ; 3       ;
+; vin_rsc_z[71]~input                                                          ; 3       ;
+; vin_rsc_z[62]~input                                                          ; 3       ;
+; vin_rsc_z[72]~input                                                          ; 3       ;
+; vin_rsc_z[63]~input                                                          ; 3       ;
+; vin_rsc_z[73]~input                                                          ; 3       ;
+; vin_rsc_z[64]~input                                                          ; 3       ;
+; vin_rsc_z[74]~input                                                          ; 3       ;
+; vin_rsc_z[65]~input                                                          ; 3       ;
+; vin_rsc_z[75]~input                                                          ; 3       ;
+; vin_rsc_z[66]~input                                                          ; 3       ;
+; vin_rsc_z[76]~input                                                          ; 3       ;
+; vin_rsc_z[67]~input                                                          ; 3       ;
+; vin_rsc_z[77]~input                                                          ; 3       ;
+; vin_rsc_z[68]~input                                                          ; 3       ;
+; vin_rsc_z[78]~input                                                          ; 3       ;
+; vin_rsc_z[50]~input                                                          ; 3       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core|romout[0][6]~2  ; 3       ;
+; sobel_core:sobel_core_inst|Add121~1                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add92~1                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add255~0                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add265~0                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add104~0                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add348~1                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add48~0                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add49~0                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add400~0                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add73~0                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add407~1                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add407~0                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add102~0                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add406~0                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add86~0                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add414~1                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add146~0                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add35~0                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add143~0                                          ; 3       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core|romout[0][4]~0  ; 3       ;
+; sobel_core:sobel_core_inst|Add227~1                                          ; 3       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core|romout[0][3]~1  ; 3       ;
+; sobel_core:sobel_core_inst|Add119~0                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add123~0                                          ; 3       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[9]                ; 3       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[9]               ; 3       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[9]               ; 3       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[19]                       ; 3       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[9]                        ; 3       ;
+; sobel_core:sobel_core_inst|Add67~0                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add127~1                                          ; 3       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[9]                ; 3       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[9]                ; 3       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[9]                ; 3       ;
+; sobel_core:sobel_core_inst|Add61~1                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add219~1                                          ; 3       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[20]                       ; 3       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[0]                ; 3       ;
+; sobel_core:sobel_core_inst|Add15~2                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add15~1                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add175~16                                         ; 3       ;
+; sobel_core:sobel_core_inst|Add199~16                                         ; 3       ;
+; sobel_core:sobel_core_inst|Add383~16                                         ; 3       ;
+; sobel_core:sobel_core_inst|Add167~10                                         ; 3       ;
+; sobel_core:sobel_core_inst|Add191~10                                         ; 3       ;
+; sobel_core:sobel_core_inst|Add165~6                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add189~6                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add132~4                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add21~4                                           ; 3       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[9]~18                     ; 3       ;
+; sobel_core:sobel_core_inst|Add26~4                                           ; 3       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[7]~14                     ; 3       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[1]~2                      ; 3       ;
+; sobel_core:sobel_core_inst|Add34~4                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add29~4                                           ; 3       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[1]~2                    ; 3       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[1]~2                      ; 3       ;
+; sobel_core:sobel_core_inst|Add7~18                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add5~18                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add7~16                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add7~14                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add7~12                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add7~10                                           ; 3       ;
+; sobel_core:sobel_core_inst|Add7~8                                            ; 3       ;
+; sobel_core:sobel_core_inst|Add3~8                                            ; 3       ;
+; sobel_core:sobel_core_inst|Add7~6                                            ; 3       ;
+; sobel_core:sobel_core_inst|Add7~4                                            ; 3       ;
+; sobel_core:sobel_core_inst|Add10~22                                          ; 3       ;
+; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[11]                            ; 3       ;
+; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[12]                            ; 3       ;
+; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[12]                            ; 3       ;
+; sobel_core:sobel_core_inst|Add13~18                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add13~16                                          ; 3       ;
+; sobel_core:sobel_core_inst|Add13~14                                          ; 3       ;
+; vin_rsc_z[38]~input                                                          ; 2       ;
+; vin_rsc_z[48]~input                                                          ; 2       ;
+; vin_rsc_z[58]~input                                                          ; 2       ;
+; vin_rsc_z[10]~input                                                          ; 2       ;
+; vin_rsc_z[20]~input                                                          ; 2       ;
+; vin_rsc_z[11]~input                                                          ; 2       ;
+; vin_rsc_z[21]~input                                                          ; 2       ;
+; vin_rsc_z[12]~input                                                          ; 2       ;
+; vin_rsc_z[22]~input                                                          ; 2       ;
+; vin_rsc_z[13]~input                                                          ; 2       ;
+; vin_rsc_z[23]~input                                                          ; 2       ;
+; vin_rsc_z[14]~input                                                          ; 2       ;
+; vin_rsc_z[24]~input                                                          ; 2       ;
+; vin_rsc_z[15]~input                                                          ; 2       ;
+; vin_rsc_z[25]~input                                                          ; 2       ;
+; vin_rsc_z[16]~input                                                          ; 2       ;
+; vin_rsc_z[26]~input                                                          ; 2       ;
+; vin_rsc_z[17]~input                                                          ; 2       ;
+; vin_rsc_z[27]~input                                                          ; 2       ;
+; vin_rsc_z[18]~input                                                          ; 2       ;
+; vin_rsc_z[28]~input                                                          ; 2       ;
+; vin_rsc_z[1]~input                                                           ; 2       ;
+; vin_rsc_z[2]~input                                                           ; 2       ;
+; vin_rsc_z[3]~input                                                           ; 2       ;
+; vin_rsc_z[4]~input                                                           ; 2       ;
+; vin_rsc_z[5]~input                                                           ; 2       ;
+; vin_rsc_z[6]~input                                                           ; 2       ;
+; vin_rsc_z[7]~input                                                           ; 2       ;
+; vin_rsc_z[8]~input                                                           ; 2       ;
+; vin_rsc_z[30]~input                                                          ; 2       ;
+; vin_rsc_z[40]~input                                                          ; 2       ;
+; vin_rsc_z[31]~input                                                          ; 2       ;
+; vin_rsc_z[41]~input                                                          ; 2       ;
+; vin_rsc_z[32]~input                                                          ; 2       ;
+; vin_rsc_z[42]~input                                                          ; 2       ;
+; vin_rsc_z[33]~input                                                          ; 2       ;
+; vin_rsc_z[43]~input                                                          ; 2       ;
+; vin_rsc_z[34]~input                                                          ; 2       ;
+; vin_rsc_z[44]~input                                                          ; 2       ;
+; vin_rsc_z[35]~input                                                          ; 2       ;
+; vin_rsc_z[45]~input                                                          ; 2       ;
+; vin_rsc_z[36]~input                                                          ; 2       ;
+; vin_rsc_z[46]~input                                                          ; 2       ;
+; vin_rsc_z[37]~input                                                          ; 2       ;
+; vin_rsc_z[47]~input                                                          ; 2       ;
+; vin_rsc_z[51]~input                                                          ; 2       ;
+; vin_rsc_z[52]~input                                                          ; 2       ;
+; vin_rsc_z[53]~input                                                          ; 2       ;
+; vin_rsc_z[54]~input                                                          ; 2       ;
+; vin_rsc_z[55]~input                                                          ; 2       ;
+; vin_rsc_z[56]~input                                                          ; 2       ;
+; vin_rsc_z[57]~input                                                          ; 2       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult7|multcore:mult_core|romout[0][12]   ; 2       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core|romout[0][5]~2  ; 2       ;
+; sobel_core:sobel_core_inst|Add121~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_652_itm_1~5                           ; 2       ;
+; sobel_core:sobel_core_inst|Add103~1                                          ; 2       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_652_itm_1~4                           ; 2       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_652_itm_1~2                           ; 2       ;
+; sobel_core:sobel_core_inst|Add106~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add30~1                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add326~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add30~0                                           ; 2       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_655_itm_1~2                           ; 2       ;
+; sobel_core:sobel_core_inst|Add49~1                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add237~1                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add237~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add85~1                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add84~0                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add92~0                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add94~0                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add78~0                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add96~1                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add98~1                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add403~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add404~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add74~1                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add73~1                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add102~1                                          ; 2       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_655_itm_1~0                           ; 2       ;
+; sobel_core:sobel_core_inst|Add87~1                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add86~1                                           ; 2       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult8|multcore:mult_core|romout[0][3]~1  ; 2       ;
+; sobel_core:sobel_core_inst|Add415~1                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add416~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add414~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add413~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add415~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add148~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add146~1                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add145~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add147~1                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add147~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add348~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add133~2                                          ; 2       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_659_itm_1~0                           ; 2       ;
+; sobel_core:sobel_core_inst|Add133~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add135~2                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add228~1                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add229~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add227~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add226~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add228~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[88]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[78]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[68]                       ; 2       ;
+; sobel_core:sobel_core_inst|Add202~5                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add51~1                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add119~2                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add113~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add202~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add210~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add68~1                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add67~1                                           ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[18]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[8]                        ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[28]                       ; 2       ;
+; sobel_core:sobel_core_inst|Add36~1                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add212~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add128~1                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add128~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add62~0                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add61~0                                           ; 2       ;
+; sobel_core:sobel_core_inst|Add127~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add107~2                                          ; 2       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core|romout[0][4]~0  ; 2       ;
+; sobel_core:sobel_core_inst|Add220~1                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add221~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add219~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[0]                        ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[10]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[11]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[1]                        ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[12]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[2]                        ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[13]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[3]                        ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[14]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[4]                        ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[15]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[5]                        ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[16]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[6]                        ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[17]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[7]                        ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[21]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[22]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[23]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[24]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[25]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[26]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[27]                       ; 2       ;
+; sobel_core:sobel_core_inst|Add218~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[0]                  ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[0]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[1]                  ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[1]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[2]                  ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[2]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[3]                  ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[3]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[4]                  ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[4]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[5]                  ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[5]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[6]                  ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[6]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[7]                  ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[7]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[8]                  ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[8]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[1]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[2]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[3]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[4]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[5]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[6]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[7]                ; 2       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[8]                ; 2       ;
+; sobel_core:sobel_core_inst|Add220~0                                          ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[80]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[81]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[82]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[83]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[84]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[85]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[86]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[87]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[70]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[60]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[71]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[61]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[72]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[62]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[73]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[63]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[74]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[64]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[75]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[65]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[76]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[66]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[77]                       ; 2       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[67]                       ; 2       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d~2                       ; 2       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d~1                       ; 2       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult0|multcore:mult_core|_~1             ; 2       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult0|multcore:mult_core|_~0             ; 2       ;
+; sobel_core:sobel_core_inst|Add15~0                                           ; 2       ;
+; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1                    ; 2       ;
+; sobel_core:sobel_core_inst|Add384~20                                         ; 2       ;
+; sobel_core:sobel_core_inst|Add236~24                                         ; 2       ;
+; sobel_core:sobel_core_inst|Add151~22                                         ; 2       ;
+; sobel_core:sobel_core_inst|Add335~14                                         ; 2       ;
+; sobel_core:sobel_core_inst|Add409~10                                         ; 2       ;
+; sobel_core:sobel_core_inst|Add211~10                                         ; 2       ;
+; sobel_core:sobel_core_inst|Add405~8                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add45~20                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add163~4                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add187~4                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add130~20                                         ; 2       ;
+; sobel_core:sobel_core_inst|Add22~20                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add27~20                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add42~20                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add7~2                                            ; 2       ;
+; sobel_core:sobel_core_inst|Add7~0                                            ; 2       ;
+; sobel_core:sobel_core_inst|nl_acc_imod_24_sva[4]~8                           ; 2       ;
+; sobel_core:sobel_core_inst|nl_acc_imod_24_sva[3]~6                           ; 2       ;
+; sobel_core:sobel_core_inst|Add12~26                                          ; 2       ;
+; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[13]                            ; 2       ;
+; sobel_core:sobel_core_inst|Add13~12                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add13~10                                          ; 2       ;
+; sobel_core:sobel_core_inst|Add13~8                                           ; 2       ;
+; sobel_core:sobel_core_inst|main_stage_0_2~feeder                             ; 1       ;
+; sobel_core:sobel_core_inst|Add263~7                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add263~6                                          ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[59]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[49]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[39]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[58]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[48]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[38]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[50]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[51]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[52]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[53]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[54]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[55]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[56]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[57]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[40]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[30]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[41]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[31]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[42]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[32]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[43]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[33]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[44]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[34]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[45]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[35]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[46]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[36]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[47]                       ; 1       ;
+; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[37]                       ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult2|multcore:mult_core|romout[0][13]   ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult2|multcore:mult_core|romout[0][12]~0 ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult7|multcore:mult_core|romout[0][11]~0 ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core|_~0             ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core|romout[0][7]~5  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core|romout[0][10]~5 ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core|romout[0][11]~4 ; 1       ;
+; sobel_core:sobel_core_inst|Add317~4                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add317~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add318~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add319~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add303~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add303~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add308~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add310~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add308~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add310~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult8|multcore:mult_core|romout[0][6]~5  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult8|multcore:mult_core|romout[0][7]~4  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core|romout[0][2]~4  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core|romout[0][4]~3  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core|romout[0][6]~1  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core|romout[0][8]~5  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core|romout[0][9]~4  ; 1       ;
+; sobel_core:sobel_core_inst|Add317~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add317~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add318~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add319~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add318~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add319~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add304~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add304~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add304~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add303~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add303~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add246~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add246~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add246~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add248~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add248~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add248~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add251~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add251~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add251~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add251~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add255~4                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add255~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add255~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add255~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add259~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add259~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add259~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add265~4                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add265~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add265~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add265~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add262~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add263~5                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add263~4                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add104~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add262~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add262~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add274~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add105~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_652_itm_1~3                           ; 1       ;
+; sobel_core:sobel_core_inst|Add272~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add272~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add272~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add278~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add278~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add281~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add281~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add281~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_652_itm_1~1                           ; 1       ;
+; sobel_core:sobel_core_inst|Add106~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add72~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_652_itm_1~0                           ; 1       ;
+; sobel_core:sobel_core_inst|Add66~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add309~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add311~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add309~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add311~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add346~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add331~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add332~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add332~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add323~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add324~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add325~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add325~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add325~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add343~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add344~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add343~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add346~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add348~4                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add347~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add348~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add347~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add348~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add347~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add340~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add340~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add336~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add336~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add336~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add340~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add340~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add352~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add352~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add355~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add355~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add355~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add358~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add358~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add358~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add358~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_655_itm_1~5                           ; 1       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_655_itm_1~4                           ; 1       ;
+; sobel_core:sobel_core_inst|Add362~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add362~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add362~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add369~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add369~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_655_itm_1~3                           ; 1       ;
+; sobel_core:sobel_core_inst|Add366~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add366~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add366~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add366~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add373~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add373~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add373~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_655_itm_1~1                           ; 1       ;
+; sobel_core:sobel_core_inst|Add57~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add377~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add377~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add377~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add385~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add388~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add386~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add387~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add387~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add389~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add388~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add396~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add396~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add395~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add395~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add35~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add72~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add399~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add400~4                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add399~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add400~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add398~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add400~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add398~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add400~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add80~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add81~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add80~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add81~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add78~2                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add78~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add403~4                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add404~4                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add403~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add404~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add403~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add403~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add404~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add404~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add74~2                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add75~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add75~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add74~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add407~4                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add406~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add407~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add406~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add407~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add406~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add87~2                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add88~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add88~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add87~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult8|multcore:mult_core|romout[0][1]~3  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult8|multcore:mult_core|romout[0][2]~2  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult8|multcore:mult_core|romout[0][4]~0  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core|romout[0][0]~1  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core|romout[0][1]~0  ; 1       ;
+; sobel_core:sobel_core_inst|Add158~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add158~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add124~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add166~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add162~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add162~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add162~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add166~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add169~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add169~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add143~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add170~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add170~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add182~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add182~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add182~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add141~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add190~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add186~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add142~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add186~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add186~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add190~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add193~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add193~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add133~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add135~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add135~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add137~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add138~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add137~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add138~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add194~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add194~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core|romout[0][1]~3  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core|romout[0][2]~2  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core|romout[0][1]~3  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core|romout[0][2]~2  ; 1       ;
+; sobel_core:sobel_core_inst|Add50~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add51~2                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add53~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add54~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add51~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add53~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add54~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add123~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|nl_ACC1_acc_658_itm_1~0                           ; 1       ;
+; sobel_core:sobel_core_inst|Add119~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add115~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add116~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add115~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add116~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add113~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add113~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[5]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[6]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[7]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[8]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[5]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[5]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[6]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[6]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[7]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[7]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[8]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[8]               ; 1       ;
+; sobel_core:sobel_core_inst|Add202~4                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add202~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add202~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[0]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[1]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[2]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[3]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[4]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[0]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[0]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[1]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[1]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[2]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[2]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[3]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[3]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[4]               ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[4]               ; 1       ;
+; sobel_core:sobel_core_inst|Add202~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add210~4                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add210~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add210~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add210~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add68~2                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add69~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add69~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add68~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add36~2                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add38~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add39~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add36~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add38~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add39~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add212~3                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add212~2                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add62~2                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add62~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add63~1                                           ; 1       ;
+; sobel_core:sobel_core_inst|Add63~0                                           ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[8]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[8]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[8]                ; 1       ;
+; sobel_core:sobel_core_inst|Add107~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add107~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add109~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add110~1                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add109~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|Add110~0                                          ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[0]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[1]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[2]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[3]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[4]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[5]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[6]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[7]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[0]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[0]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[1]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[1]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[2]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[2]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[3]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[3]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[4]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[4]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[5]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[5]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[6]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[6]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[7]                ; 1       ;
+; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[7]                ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult1|multcore:mult_core|romout[0][8]~4  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult1|multcore:mult_core|romout[0][7]~3  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult1|multcore:mult_core|romout[0][6]~2  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult1|multcore:mult_core|romout[0][5]~1  ; 1       ;
+; sobel_core:sobel_core_inst|lpm_mult:Mult1|multcore:mult_core|romout[0][4]~0  ; 1       ;
+; sobel_core:sobel_core_inst|main_stage_0_2                                    ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[4]                          ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[1]                          ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[2]                          ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[3]                          ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[0]                          ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_mul_57_itm_2[0]                              ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_mul_57_itm_2[1]                              ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1                ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[29]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[28]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[27]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[25]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[24]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[23]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[22]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[17]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[16]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[15]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[14]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[13]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[12]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10]                     ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]                      ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]                      ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[7]                      ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]                      ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[5]                      ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[4]                      ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[3]                      ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[2]                      ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[1]                      ; 1       ;
+; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[0]                      ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[13]~40                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[10]~31                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[11]~34                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[10]~33                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[10]~32                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[12]~39                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[12]~38                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[11]~37                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[11]~36                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[10]~35                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[10]~34                         ; 1       ;
+; sobel_core:sobel_core_inst|Add236~23                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add236~22                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add236~21                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add236~20                                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[12]~37                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[11]~36                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[11]~35                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[10]~34                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[10]~33                         ; 1       ;
+; sobel_core:sobel_core_inst|Add151~21                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add151~20                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add200~24                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add200~23                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add200~22                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add200~21                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add200~20                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add174~20                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add173~20                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add198~20                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add197~20                                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[12]~37                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[11]~36                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[11]~35                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[10]~34                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[10]~33                         ; 1       ;
+; sobel_core:sobel_core_inst|Add224~24                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add224~23                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add224~22                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add224~21                                         ; 1       ;
+; sobel_core:sobel_core_inst|Add224~20                                         ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]~30                          ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]~29                          ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[8]~28                          ; 1       ;
+; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[8]~27                          ; 1       ;
++------------------------------------------------------------------------------+---------+
+
+
++------------------------------------------------------+
+; Other Routing Usage Summary                          ;
++-----------------------------+------------------------+
+; Other Routing Resource Type ; Usage                  ;
++-----------------------------+------------------------+
+; Block interconnects         ; 2,219 / 47,787 ( 5 % ) ;
+; C16 interconnects           ; 82 / 1,804 ( 5 % )     ;
+; C4 interconnects            ; 1,049 / 31,272 ( 3 % ) ;
+; Direct links                ; 552 / 47,787 ( 1 % )   ;
+; Global clocks               ; 2 / 20 ( 10 % )        ;
+; Local interconnects         ; 636 / 15,408 ( 4 % )   ;
+; R24 interconnects           ; 63 / 1,775 ( 4 % )     ;
+; R4 interconnects            ; 1,271 / 41,310 ( 3 % ) ;
++-----------------------------+------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Logic Elements                                                          ;
++---------------------------------------------+-------------------------------+
+; Number of Logic Elements  (Average = 13.54) ; Number of LABs  (Total = 142) ;
++---------------------------------------------+-------------------------------+
+; 1                                           ; 2                             ;
+; 2                                           ; 5                             ;
+; 3                                           ; 0                             ;
+; 4                                           ; 3                             ;
+; 5                                           ; 2                             ;
+; 6                                           ; 0                             ;
+; 7                                           ; 0                             ;
+; 8                                           ; 3                             ;
+; 9                                           ; 2                             ;
+; 10                                          ; 3                             ;
+; 11                                          ; 9                             ;
+; 12                                          ; 7                             ;
+; 13                                          ; 7                             ;
+; 14                                          ; 11                            ;
+; 15                                          ; 19                            ;
+; 16                                          ; 69                            ;
++---------------------------------------------+-------------------------------+
+
+
++--------------------------------------------------------------------+
+; LAB-wide Signals                                                   ;
++------------------------------------+-------------------------------+
+; LAB-wide Signals  (Average = 0.67) ; Number of LABs  (Total = 142) ;
++------------------------------------+-------------------------------+
+; 1 Async. clear                     ; 32                            ;
+; 1 Clock                            ; 32                            ;
+; 1 Clock enable                     ; 31                            ;
++------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Signals Sourced                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Signals Sourced  (Average = 15.13) ; Number of LABs  (Total = 142) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 2                             ;
+; 2                                            ; 1                             ;
+; 3                                            ; 2                             ;
+; 4                                            ; 5                             ;
+; 5                                            ; 2                             ;
+; 6                                            ; 1                             ;
+; 7                                            ; 1                             ;
+; 8                                            ; 2                             ;
+; 9                                            ; 1                             ;
+; 10                                           ; 5                             ;
+; 11                                           ; 9                             ;
+; 12                                           ; 6                             ;
+; 13                                           ; 6                             ;
+; 14                                           ; 16                            ;
+; 15                                           ; 24                            ;
+; 16                                           ; 32                            ;
+; 17                                           ; 4                             ;
+; 18                                           ; 1                             ;
+; 19                                           ; 0                             ;
+; 20                                           ; 3                             ;
+; 21                                           ; 1                             ;
+; 22                                           ; 0                             ;
+; 23                                           ; 1                             ;
+; 24                                           ; 0                             ;
+; 25                                           ; 5                             ;
+; 26                                           ; 1                             ;
+; 27                                           ; 0                             ;
+; 28                                           ; 2                             ;
+; 29                                           ; 2                             ;
+; 30                                           ; 1                             ;
+; 31                                           ; 1                             ;
+; 32                                           ; 5                             ;
++----------------------------------------------+-------------------------------+
+
+
++----------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                          ;
++--------------------------------------------------+-------------------------------+
+; Number of Signals Sourced Out  (Average = 10.39) ; Number of LABs  (Total = 142) ;
++--------------------------------------------------+-------------------------------+
+; 0                                                ; 0                             ;
+; 1                                                ; 3                             ;
+; 2                                                ; 4                             ;
+; 3                                                ; 2                             ;
+; 4                                                ; 4                             ;
+; 5                                                ; 4                             ;
+; 6                                                ; 14                            ;
+; 7                                                ; 14                            ;
+; 8                                                ; 12                            ;
+; 9                                                ; 8                             ;
+; 10                                               ; 17                            ;
+; 11                                               ; 11                            ;
+; 12                                               ; 9                             ;
+; 13                                               ; 6                             ;
+; 14                                               ; 9                             ;
+; 15                                               ; 10                            ;
+; 16                                               ; 5                             ;
+; 17                                               ; 0                             ;
+; 18                                               ; 1                             ;
+; 19                                               ; 0                             ;
+; 20                                               ; 1                             ;
+; 21                                               ; 0                             ;
+; 22                                               ; 0                             ;
+; 23                                               ; 3                             ;
+; 24                                               ; 1                             ;
+; 25                                               ; 0                             ;
+; 26                                               ; 1                             ;
+; 27                                               ; 2                             ;
+; 28                                               ; 1                             ;
++--------------------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Distinct Inputs  (Average = 14.74) ; Number of LABs  (Total = 142) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 0                             ;
+; 2                                            ; 2                             ;
+; 3                                            ; 3                             ;
+; 4                                            ; 2                             ;
+; 5                                            ; 6                             ;
+; 6                                            ; 4                             ;
+; 7                                            ; 2                             ;
+; 8                                            ; 6                             ;
+; 9                                            ; 12                            ;
+; 10                                           ; 11                            ;
+; 11                                           ; 5                             ;
+; 12                                           ; 4                             ;
+; 13                                           ; 9                             ;
+; 14                                           ; 11                            ;
+; 15                                           ; 6                             ;
+; 16                                           ; 9                             ;
+; 17                                           ; 5                             ;
+; 18                                           ; 3                             ;
+; 19                                           ; 3                             ;
+; 20                                           ; 5                             ;
+; 21                                           ; 2                             ;
+; 22                                           ; 4                             ;
+; 23                                           ; 12                            ;
+; 24                                           ; 2                             ;
+; 25                                           ; 4                             ;
+; 26                                           ; 3                             ;
+; 27                                           ; 2                             ;
+; 28                                           ; 1                             ;
+; 29                                           ; 1                             ;
+; 30                                           ; 2                             ;
+; 31                                           ; 1                             ;
++----------------------------------------------+-------------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 9     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 21    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 123       ; 0            ; 0            ; 123       ; 123       ; 0            ; 30           ; 0            ; 0            ; 93           ; 0            ; 30           ; 93           ; 0            ; 0            ; 0            ; 30           ; 0            ; 0            ; 0            ; 0            ; 0            ; 123       ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 123          ; 123          ; 123          ; 123          ; 123          ; 0         ; 123          ; 123          ; 0         ; 0         ; 123          ; 93           ; 123          ; 123          ; 30           ; 123          ; 93           ; 30           ; 123          ; 123          ; 123          ; 93           ; 123          ; 123          ; 123          ; 123          ; 123          ; 0         ; 123          ; 123          ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; vout_rsc_z[0]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[1]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[2]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[3]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[4]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[5]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[6]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[7]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[8]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[9]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[10]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[11]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[12]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[13]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[14]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[15]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[16]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[17]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[18]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[19]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[20]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[21]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[22]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[23]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[24]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[25]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[26]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[27]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[28]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vout_rsc_z[29]     ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; clk                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; arst_n             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; en                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[57]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[56]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[55]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[54]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[53]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[52]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[51]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[50]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[47]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[37]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[46]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[36]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[45]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[35]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[44]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[34]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[43]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[33]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[42]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[32]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[41]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[31]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[40]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[30]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[78]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[68]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[77]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[67]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[76]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[66]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[75]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[65]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[74]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[64]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[73]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[63]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[72]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[62]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[71]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[61]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[70]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[60]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[88]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[87]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[86]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[85]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[84]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[83]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[82]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[81]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[80]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[8]       ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[7]       ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[6]       ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[5]       ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[4]       ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[3]       ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[2]       ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[1]       ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[0]       ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[28]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[18]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[27]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[17]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[26]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[16]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[25]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[15]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[24]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[14]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[23]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[13]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[22]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[12]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[21]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[11]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[20]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[10]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[9]       ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[29]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[19]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[79]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[69]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[89]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[59]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[58]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[49]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[39]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[48]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; vin_rsc_z[38]      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; As output driving ground ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16F484C6 for design "sobel"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 123 pins of 123 total pins
+    Info (169086): Pin vout_rsc_z[0] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[1] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[2] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[3] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[4] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[5] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[6] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[7] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[8] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[9] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[10] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[11] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[12] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[13] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[14] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[15] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[16] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[17] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[18] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[19] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[20] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[21] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[22] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[23] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[24] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[25] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[26] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[27] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[28] not assigned to an exact location on the device
+    Info (169086): Pin vout_rsc_z[29] not assigned to an exact location on the device
+    Info (169086): Pin clk not assigned to an exact location on the device
+    Info (169086): Pin arst_n not assigned to an exact location on the device
+    Info (169086): Pin en not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[57] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[56] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[55] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[54] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[53] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[52] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[51] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[50] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[47] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[37] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[46] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[36] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[45] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[35] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[44] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[34] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[43] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[33] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[42] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[32] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[41] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[31] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[40] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[30] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[78] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[68] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[77] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[67] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[76] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[66] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[75] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[65] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[74] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[64] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[73] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[63] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[72] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[62] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[71] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[61] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[70] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[60] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[88] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[87] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[86] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[85] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[84] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[83] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[82] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[81] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[80] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[8] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[7] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[6] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[5] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[4] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[3] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[2] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[1] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[0] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[28] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[18] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[27] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[17] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[26] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[16] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[25] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[15] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[24] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[14] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[23] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[13] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[22] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[12] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[21] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[11] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[20] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[10] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[9] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[29] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[19] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[79] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[69] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[89] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[59] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[58] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[49] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[39] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[48] not assigned to an exact location on the device
+    Info (169086): Pin vin_rsc_z[38] not assigned to an exact location on the device
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'sobel.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176353): Automatically promoted node clk~input (placed in PIN G2 (CLK0, DIFFCLK_0p))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
+Info (176353): Automatically promoted node arst_n~input (placed in PIN G1 (CLK1, DIFFCLK_0n))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 121 (unused VREF, 2.5V VCCIO, 91 input, 30 output, 0 bidirectional)
+        Info (176212): I/O standards used: 2.5 V.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 6 total pin(s) used --  27 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:03
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:03
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 3% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:02
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.87 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Info (144001): Generated suppressed messages file /EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/output_files/sobel.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings
+    Info: Peak virtual memory: 1146 megabytes
+    Info: Processing ended: Tue Mar 08 16:22:15 2016
+    Info: Elapsed time: 00:00:18
+    Info: Total CPU time (on all processors): 00:00:15
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/output_files/sobel.fit.smsg.
+
+
diff --git a/Sobel/Sobel Quartus/output_files/sobel.fit.smsg b/Sobel/Sobel Quartus/output_files/sobel.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/Sobel/Sobel Quartus/output_files/sobel.fit.summary b/Sobel/Sobel Quartus/output_files/sobel.fit.summary
new file mode 100644
index 0000000..5000619
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Tue Mar 08 16:22:13 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : sobel
+Top-level Entity Name : sobel
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 1,923 / 15,408 ( 12 % )
+    Total combinational functions : 1,847 / 15,408 ( 12 % )
+    Dedicated logic registers : 284 / 15,408 ( 2 % )
+Total registers : 284
+Total pins : 123 / 347 ( 35 % )
+Total virtual pins : 0
+Total memory bits : 0 / 516,096 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/Sobel/Sobel Quartus/output_files/sobel.flow.rpt b/Sobel/Sobel Quartus/output_files/sobel.flow.rpt
new file mode 100644
index 0000000..1ef3a69
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.flow.rpt
@@ -0,0 +1,125 @@
+Flow report for sobel
+Tue Mar 08 16:22:33 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Flow Summary                                                                          ;
++------------------------------------+--------------------------------------------------+
+; Flow Status                        ; Successful - Tue Mar 08 16:22:25 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; sobel                                            ;
+; Top-level Entity Name              ; sobel                                            ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 1,923 / 15,408 ( 12 % )                          ;
+;     Total combinational functions  ; 1,847 / 15,408 ( 12 % )                          ;
+;     Dedicated logic registers      ; 284 / 15,408 ( 2 % )                             ;
+; Total registers                    ; 284                                              ;
+; Total pins                         ; 123 / 347 ( 35 % )                               ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 03/08/2016 16:21:42 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; sobel               ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                       ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 260248564575767.145745410208916       ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                                  ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:14     ; 1.0                     ; 499 MB              ; 00:00:06                           ;
+; Fitter                    ; 00:00:16     ; 1.7                     ; 1146 MB             ; 00:00:14                           ;
+; Assembler                 ; 00:00:03     ; 1.0                     ; 441 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:07     ; 1.0                     ; 522 MB              ; 00:00:03                           ;
+; Total                     ; 00:00:40     ; --                      ; --                  ; 00:00:24                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-013     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-013     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-013     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-013     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off sobel -c sobel
+quartus_fit --read_settings_files=off --write_settings_files=off sobel -c sobel
+quartus_asm --read_settings_files=off --write_settings_files=off sobel -c sobel
+quartus_sta sobel -c sobel
+
+
+
diff --git a/Sobel/Sobel Quartus/output_files/sobel.jdi b/Sobel/Sobel Quartus/output_files/sobel.jdi
new file mode 100644
index 0000000..4855bcc
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="8b406448c713dde4ef30"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="sobel.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/Sobel/Sobel Quartus/output_files/sobel.map.rpt b/Sobel/Sobel Quartus/output_files/sobel.map.rpt
new file mode 100644
index 0000000..1c4f2e0
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.map.rpt
@@ -0,0 +1,903 @@
+Analysis & Synthesis report for sobel
+Tue Mar 08 16:21:55 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Parameter Settings for User Entity Instance: mgc_in_wire:vin_rsc_mgc_in_wire
+ 10. Parameter Settings for User Entity Instance: mgc_out_stdreg:vout_rsc_mgc_out_stdreg
+ 11. Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult0
+ 12. Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult1
+ 13. Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult7
+ 14. Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult5
+ 15. Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult2
+ 16. Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult3
+ 17. Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult6
+ 18. Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult4
+ 19. Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult8
+ 20. lpm_mult Parameter Settings by Entity Instance
+ 21. Elapsed Time Per Partition
+ 22. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                          ;
++------------------------------------+--------------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Tue Mar 08 16:21:55 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; sobel                                            ;
+; Top-level Entity Name              ; sobel                                            ;
+; Family                             ; Cyclone III                                      ;
+; Total logic elements               ; 2,048                                            ;
+;     Total combinational functions  ; 1,846                                            ;
+;     Dedicated logic registers      ; 284                                              ;
+; Total registers                    ; 284                                              ;
+; Total pins                         ; 123                                              ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0                                                ;
+; Embedded Multiplier 9-bit elements ; 0                                                ;
+; Total PLLs                         ; 0                                                ;
++------------------------------------+--------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6       ;                    ;
+; Top-level entity name                                                      ; sobel              ; sobel              ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                     ;
++----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                                 ; Library ;
++----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------------+---------+
+; ../sobel.v12/rtl_mgc_ioport.v    ; yes             ; User Verilog HDL File        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v ;         ;
+; sobel.v                          ; yes             ; Auto-Found Verilog HDL File  ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v      ;         ;
+; lpm_mult.tdf                     ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf                               ;         ;
+; aglobal130.inc                   ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc                             ;         ;
+; lpm_add_sub.inc                  ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc                            ;         ;
+; multcore.inc                     ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.inc                               ;         ;
+; bypassff.inc                     ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/bypassff.inc                               ;         ;
+; altshift.inc                     ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.inc                               ;         ;
+; multcore.tdf                     ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf                               ;         ;
+; csa_add.inc                      ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/csa_add.inc                                ;         ;
+; mpar_add.inc                     ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.inc                               ;         ;
+; muleabz.inc                      ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/muleabz.inc                                ;         ;
+; mul_lfrg.inc                     ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mul_lfrg.inc                               ;         ;
+; mul_boothc.inc                   ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mul_boothc.inc                             ;         ;
+; alt_ded_mult.inc                 ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_ded_mult.inc                           ;         ;
+; alt_ded_mult_y.inc               ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_ded_mult_y.inc                         ;         ;
+; dffpipe.inc                      ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/dffpipe.inc                                ;         ;
+; mpar_add.tdf                     ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf                               ;         ;
+; altshift.tdf                     ; yes             ; Megafunction                 ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.tdf                               ;         ;
++----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------------+---------+
+
+
++---------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary             ;
++---------------------------------------------+-----------+
+; Resource                                    ; Usage     ;
++---------------------------------------------+-----------+
+; Estimated Total logic elements              ; 2,048     ;
+;                                             ;           ;
+; Total combinational functions               ; 1846      ;
+; Logic element usage by number of LUT inputs ;           ;
+;     -- 4 input functions                    ; 172       ;
+;     -- 3 input functions                    ; 1167      ;
+;     -- <=2 input functions                  ; 507       ;
+;                                             ;           ;
+; Logic elements by mode                      ;           ;
+;     -- normal mode                          ; 629       ;
+;     -- arithmetic mode                      ; 1217      ;
+;                                             ;           ;
+; Total registers                             ; 284       ;
+;     -- Dedicated logic registers            ; 284       ;
+;     -- I/O registers                        ; 0         ;
+;                                             ;           ;
+; I/O pins                                    ; 123       ;
+; Embedded Multiplier 9-bit elements          ; 0         ;
+; Maximum fan-out node                        ; clk~input ;
+; Maximum fan-out                             ; 284       ;
+; Total fan-out                               ; 6240      ;
+; Average fan-out                             ; 2.63      ;
++---------------------------------------------+-----------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                              ;
++---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node      ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                 ; Library Name ;
++---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------+--------------+
+; |sobel                          ; 1846 (0)          ; 284 (0)      ; 0           ; 0            ; 0       ; 0         ; 123  ; 0            ; |sobel                                                              ; work         ;
+;    |sobel_core:sobel_core_inst| ; 1846 (1807)       ; 284 (284)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst                                   ; work         ;
+;       |lpm_mult:Mult0|          ; 2 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult0                    ; work         ;
+;          |multcore:mult_core|   ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult0|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult1|          ; 5 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult1                    ; work         ;
+;          |multcore:mult_core|   ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult1|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult2|          ; 2 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult2                    ; work         ;
+;          |multcore:mult_core|   ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult2|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult3|          ; 6 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult3                    ; work         ;
+;          |multcore:mult_core|   ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult4|          ; 6 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult4                    ; work         ;
+;          |multcore:mult_core|   ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult5|          ; 6 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult5                    ; work         ;
+;          |multcore:mult_core|   ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult6|          ; 4 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult6                    ; work         ;
+;          |multcore:mult_core|   ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult7|          ; 2 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult7                    ; work         ;
+;          |multcore:mult_core|   ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult7|multcore:mult_core ; work         ;
+;       |lpm_mult:Mult8|          ; 6 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult8                    ; work         ;
+;          |multcore:mult_core|   ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sobel|sobel_core:sobel_core_inst|lpm_mult:Mult8|multcore:mult_core ; work         ;
++---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 284   ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 284   ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 284   ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: mgc_in_wire:vin_rsc_mgc_in_wire ;
++----------------+-------+-----------------------------------------------------+
+; Parameter Name ; Value ; Type                                                ;
++----------------+-------+-----------------------------------------------------+
+; rscid          ; 1     ; Signed Integer                                      ;
+; width          ; 90    ; Signed Integer                                      ;
++----------------+-------+-----------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: mgc_out_stdreg:vout_rsc_mgc_out_stdreg ;
++----------------+-------+------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                       ;
++----------------+-------+------------------------------------------------------------+
+; rscid          ; 2     ; Signed Integer                                             ;
+; width          ; 30    ; Signed Integer                                             ;
++----------------+-------+------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult0 ;
++------------------------------------------------+-------------+-----------------------------+
+; Parameter Name                                 ; Value       ; Type                        ;
++------------------------------------------------+-------------+-----------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                  ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE              ;
+; LPM_WIDTHA                                     ; 2           ; Untyped                     ;
+; LPM_WIDTHB                                     ; 9           ; Untyped                     ;
+; LPM_WIDTHP                                     ; 11          ; Untyped                     ;
+; LPM_WIDTHR                                     ; 11          ; Untyped                     ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                     ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                     ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                     ;
+; LATENCY                                        ; 0           ; Untyped                     ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                     ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                     ;
+; USE_EAB                                        ; OFF         ; Untyped                     ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                     ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                     ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                     ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K         ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                     ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                     ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                     ;
++------------------------------------------------+-------------+-----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult1 ;
++------------------------------------------------+-------------+-----------------------------+
+; Parameter Name                                 ; Value       ; Type                        ;
++------------------------------------------------+-------------+-----------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                  ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE              ;
+; LPM_WIDTHA                                     ; 3           ; Untyped                     ;
+; LPM_WIDTHB                                     ; 6           ; Untyped                     ;
+; LPM_WIDTHP                                     ; 9           ; Untyped                     ;
+; LPM_WIDTHR                                     ; 9           ; Untyped                     ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                     ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                     ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                     ;
+; LATENCY                                        ; 0           ; Untyped                     ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                     ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                     ;
+; USE_EAB                                        ; OFF         ; Untyped                     ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                     ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                     ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                     ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K         ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                     ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                     ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                     ;
++------------------------------------------------+-------------+-----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult7 ;
++------------------------------------------------+-------------+-----------------------------+
+; Parameter Name                                 ; Value       ; Type                        ;
++------------------------------------------------+-------------+-----------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                  ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE              ;
+; LPM_WIDTHA                                     ; 2           ; Untyped                     ;
+; LPM_WIDTHB                                     ; 13          ; Untyped                     ;
+; LPM_WIDTHP                                     ; 15          ; Untyped                     ;
+; LPM_WIDTHR                                     ; 15          ; Untyped                     ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                     ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                     ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                     ;
+; LATENCY                                        ; 0           ; Untyped                     ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                     ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                     ;
+; USE_EAB                                        ; OFF         ; Untyped                     ;
+; MAXIMIZE_SPEED                                 ; 6           ; Untyped                     ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                     ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                     ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K         ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                     ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                     ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                     ;
++------------------------------------------------+-------------+-----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult5 ;
++------------------------------------------------+-------------+-----------------------------+
+; Parameter Name                                 ; Value       ; Type                        ;
++------------------------------------------------+-------------+-----------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                  ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE              ;
+; LPM_WIDTHA                                     ; 4           ; Untyped                     ;
+; LPM_WIDTHB                                     ; 9           ; Untyped                     ;
+; LPM_WIDTHP                                     ; 13          ; Untyped                     ;
+; LPM_WIDTHR                                     ; 13          ; Untyped                     ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                     ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                     ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                     ;
+; LATENCY                                        ; 0           ; Untyped                     ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                     ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                     ;
+; USE_EAB                                        ; OFF         ; Untyped                     ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                     ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                     ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                     ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K         ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                     ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                     ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                     ;
++------------------------------------------------+-------------+-----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult2 ;
++------------------------------------------------+-------------+-----------------------------+
+; Parameter Name                                 ; Value       ; Type                        ;
++------------------------------------------------+-------------+-----------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                  ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE              ;
+; LPM_WIDTHA                                     ; 2           ; Untyped                     ;
+; LPM_WIDTHB                                     ; 14          ; Untyped                     ;
+; LPM_WIDTHP                                     ; 16          ; Untyped                     ;
+; LPM_WIDTHR                                     ; 16          ; Untyped                     ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                     ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                     ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                     ;
+; LATENCY                                        ; 0           ; Untyped                     ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                     ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                     ;
+; USE_EAB                                        ; OFF         ; Untyped                     ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                     ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                     ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                     ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K         ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                     ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                     ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                     ;
++------------------------------------------------+-------------+-----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult3 ;
++------------------------------------------------+-------------+-----------------------------+
+; Parameter Name                                 ; Value       ; Type                        ;
++------------------------------------------------+-------------+-----------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                  ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE              ;
+; LPM_WIDTHA                                     ; 4           ; Untyped                     ;
+; LPM_WIDTHB                                     ; 5           ; Untyped                     ;
+; LPM_WIDTHP                                     ; 9           ; Untyped                     ;
+; LPM_WIDTHR                                     ; 9           ; Untyped                     ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                     ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                     ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                     ;
+; LATENCY                                        ; 0           ; Untyped                     ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                     ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                     ;
+; USE_EAB                                        ; OFF         ; Untyped                     ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                     ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                     ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                     ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K         ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                     ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                     ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                     ;
++------------------------------------------------+-------------+-----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult6 ;
++------------------------------------------------+-------------+-----------------------------+
+; Parameter Name                                 ; Value       ; Type                        ;
++------------------------------------------------+-------------+-----------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                  ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE              ;
+; LPM_WIDTHA                                     ; 3           ; Untyped                     ;
+; LPM_WIDTHB                                     ; 7           ; Untyped                     ;
+; LPM_WIDTHP                                     ; 10          ; Untyped                     ;
+; LPM_WIDTHR                                     ; 10          ; Untyped                     ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                     ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                     ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                     ;
+; LATENCY                                        ; 0           ; Untyped                     ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                     ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                     ;
+; USE_EAB                                        ; OFF         ; Untyped                     ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                     ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                     ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                     ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K         ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                     ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                     ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                     ;
++------------------------------------------------+-------------+-----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult4 ;
++------------------------------------------------+-------------+-----------------------------+
+; Parameter Name                                 ; Value       ; Type                        ;
++------------------------------------------------+-------------+-----------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                  ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE              ;
+; LPM_WIDTHA                                     ; 4           ; Untyped                     ;
+; LPM_WIDTHB                                     ; 7           ; Untyped                     ;
+; LPM_WIDTHP                                     ; 11          ; Untyped                     ;
+; LPM_WIDTHR                                     ; 11          ; Untyped                     ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                     ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                     ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                     ;
+; LATENCY                                        ; 0           ; Untyped                     ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                     ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                     ;
+; USE_EAB                                        ; OFF         ; Untyped                     ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                     ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                     ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                     ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K         ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                     ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                     ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                     ;
++------------------------------------------------+-------------+-----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel_core:sobel_core_inst|lpm_mult:Mult8 ;
++------------------------------------------------+-------------+-----------------------------+
+; Parameter Name                                 ; Value       ; Type                        ;
++------------------------------------------------+-------------+-----------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                  ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE              ;
+; LPM_WIDTHA                                     ; 4           ; Untyped                     ;
+; LPM_WIDTHB                                     ; 5           ; Untyped                     ;
+; LPM_WIDTHP                                     ; 9           ; Untyped                     ;
+; LPM_WIDTHR                                     ; 9           ; Untyped                     ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                     ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                     ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                     ;
+; LATENCY                                        ; 0           ; Untyped                     ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                     ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                     ;
+; USE_EAB                                        ; OFF         ; Untyped                     ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                     ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                     ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                     ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K         ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                     ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                     ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                     ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                     ;
++------------------------------------------------+-------------+-----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------+
+; lpm_mult Parameter Settings by Entity Instance                                    ;
++---------------------------------------+-------------------------------------------+
+; Name                                  ; Value                                     ;
++---------------------------------------+-------------------------------------------+
+; Number of entity instances            ; 9                                         ;
+; Entity Instance                       ; sobel_core:sobel_core_inst|lpm_mult:Mult0 ;
+;     -- LPM_WIDTHA                     ; 2                                         ;
+;     -- LPM_WIDTHB                     ; 9                                         ;
+;     -- LPM_WIDTHP                     ; 11                                        ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                  ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                        ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                       ;
+;     -- USE_EAB                        ; OFF                                       ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                      ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                        ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                        ;
+; Entity Instance                       ; sobel_core:sobel_core_inst|lpm_mult:Mult1 ;
+;     -- LPM_WIDTHA                     ; 3                                         ;
+;     -- LPM_WIDTHB                     ; 6                                         ;
+;     -- LPM_WIDTHP                     ; 9                                         ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                  ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                        ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                       ;
+;     -- USE_EAB                        ; OFF                                       ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                      ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                        ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                        ;
+; Entity Instance                       ; sobel_core:sobel_core_inst|lpm_mult:Mult7 ;
+;     -- LPM_WIDTHA                     ; 2                                         ;
+;     -- LPM_WIDTHB                     ; 13                                        ;
+;     -- LPM_WIDTHP                     ; 15                                        ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                  ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                        ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                       ;
+;     -- USE_EAB                        ; OFF                                       ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                      ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                        ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                        ;
+; Entity Instance                       ; sobel_core:sobel_core_inst|lpm_mult:Mult5 ;
+;     -- LPM_WIDTHA                     ; 4                                         ;
+;     -- LPM_WIDTHB                     ; 9                                         ;
+;     -- LPM_WIDTHP                     ; 13                                        ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                  ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                        ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                       ;
+;     -- USE_EAB                        ; OFF                                       ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                      ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                        ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                        ;
+; Entity Instance                       ; sobel_core:sobel_core_inst|lpm_mult:Mult2 ;
+;     -- LPM_WIDTHA                     ; 2                                         ;
+;     -- LPM_WIDTHB                     ; 14                                        ;
+;     -- LPM_WIDTHP                     ; 16                                        ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                  ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                        ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                       ;
+;     -- USE_EAB                        ; OFF                                       ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                      ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                        ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                        ;
+; Entity Instance                       ; sobel_core:sobel_core_inst|lpm_mult:Mult3 ;
+;     -- LPM_WIDTHA                     ; 4                                         ;
+;     -- LPM_WIDTHB                     ; 5                                         ;
+;     -- LPM_WIDTHP                     ; 9                                         ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                  ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                        ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                       ;
+;     -- USE_EAB                        ; OFF                                       ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                      ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                        ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                        ;
+; Entity Instance                       ; sobel_core:sobel_core_inst|lpm_mult:Mult6 ;
+;     -- LPM_WIDTHA                     ; 3                                         ;
+;     -- LPM_WIDTHB                     ; 7                                         ;
+;     -- LPM_WIDTHP                     ; 10                                        ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                  ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                        ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                       ;
+;     -- USE_EAB                        ; OFF                                       ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                      ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                        ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                        ;
+; Entity Instance                       ; sobel_core:sobel_core_inst|lpm_mult:Mult4 ;
+;     -- LPM_WIDTHA                     ; 4                                         ;
+;     -- LPM_WIDTHB                     ; 7                                         ;
+;     -- LPM_WIDTHP                     ; 11                                        ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                  ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                        ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                       ;
+;     -- USE_EAB                        ; OFF                                       ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                      ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                        ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                        ;
+; Entity Instance                       ; sobel_core:sobel_core_inst|lpm_mult:Mult8 ;
+;     -- LPM_WIDTHA                     ; 4                                         ;
+;     -- LPM_WIDTHB                     ; 5                                         ;
+;     -- LPM_WIDTHP                     ; 9                                         ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                  ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                        ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                       ;
+;     -- USE_EAB                        ; OFF                                       ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                      ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                        ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                        ;
++---------------------------------------+-------------------------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:04     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 08 16:21:39 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sobel -c sobel
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 20 design units, including 20 entities, in source file //icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel.v12/rtl_mgc_ioport.v
+    Info (12023): Found entity 1: mgc_in_wire
+    Info (12023): Found entity 2: mgc_in_wire_en
+    Info (12023): Found entity 3: mgc_in_wire_wait
+    Info (12023): Found entity 4: mgc_chan_in
+    Info (12023): Found entity 5: mgc_out_stdreg
+    Info (12023): Found entity 6: mgc_out_stdreg_en
+    Info (12023): Found entity 7: mgc_out_stdreg_wait
+    Info (12023): Found entity 8: mgc_out_prereg_en
+    Info (12023): Found entity 9: mgc_inout_stdreg_en
+    Info (12023): Found entity 10: hid_tribuf
+    Info (12023): Found entity 11: mgc_inout_stdreg_wait
+    Info (12023): Found entity 12: mgc_inout_buf_wait
+    Info (12023): Found entity 13: mgc_inout_fifo_wait
+    Info (12023): Found entity 14: mgc_io_sync
+    Info (12023): Found entity 15: mgc_bsync_rdy
+    Info (12023): Found entity 16: mgc_bsync_vld
+    Info (12023): Found entity 17: mgc_bsync_rv
+    Info (12023): Found entity 18: mgc_sync
+    Info (12023): Found entity 19: funccall_inout
+    Info (12023): Found entity 20: modulario_en_in
+Warning (12125): Using design file sobel.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project
+    Info (12023): Found entity 1: sobel_core
+    Info (12023): Found entity 2: sobel
+Info (12127): Elaborating entity "sobel" for the top level hierarchy
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "mgc_in_wire:vin_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_out_stdreg" for hierarchy "mgc_out_stdreg:vout_rsc_mgc_out_stdreg"
+Info (12128): Elaborating entity "sobel_core" for hierarchy "sobel_core:sobel_core_inst"
+Info (278001): Inferred 9 megafunctions from design logic
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel_core:sobel_core_inst|Mult0"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel_core:sobel_core_inst|Mult1"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel_core:sobel_core_inst|Mult7"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel_core:sobel_core_inst|Mult5"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel_core:sobel_core_inst|Mult2"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel_core:sobel_core_inst|Mult3"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel_core:sobel_core_inst|Mult6"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel_core:sobel_core_inst|Mult4"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel_core:sobel_core_inst|Mult8"
+Info (12130): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult0"
+Info (12133): Instantiated megafunction "sobel_core:sobel_core_inst|lpm_mult:Mult0" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "2"
+    Info (12134): Parameter "LPM_WIDTHB" = "9"
+    Info (12134): Parameter "LPM_WIDTHP" = "11"
+    Info (12134): Parameter "LPM_WIDTHR" = "11"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult0|multcore:mult_core", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult0"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult0"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult0|altshift:external_latency_ffs", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult0"
+Info (12130): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult1"
+Info (12133): Instantiated megafunction "sobel_core:sobel_core_inst|lpm_mult:Mult1" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "3"
+    Info (12134): Parameter "LPM_WIDTHB" = "6"
+    Info (12134): Parameter "LPM_WIDTHP" = "9"
+    Info (12134): Parameter "LPM_WIDTHR" = "9"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult1|multcore:mult_core", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult1"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult1"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult1|altshift:external_latency_ffs", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult1"
+Info (12130): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult7"
+Info (12133): Instantiated megafunction "sobel_core:sobel_core_inst|lpm_mult:Mult7" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "2"
+    Info (12134): Parameter "LPM_WIDTHB" = "13"
+    Info (12134): Parameter "LPM_WIDTHP" = "15"
+    Info (12134): Parameter "LPM_WIDTHR" = "15"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "6"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult7|multcore:mult_core", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult7"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult7|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult7"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult7|altshift:external_latency_ffs", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult7"
+Info (12130): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult5"
+Info (12133): Instantiated megafunction "sobel_core:sobel_core_inst|lpm_mult:Mult5" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "4"
+    Info (12134): Parameter "LPM_WIDTHB" = "9"
+    Info (12134): Parameter "LPM_WIDTHP" = "13"
+    Info (12134): Parameter "LPM_WIDTHR" = "13"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult5"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult5"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult5|altshift:external_latency_ffs", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult5"
+Info (12130): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult2"
+Info (12133): Instantiated megafunction "sobel_core:sobel_core_inst|lpm_mult:Mult2" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "2"
+    Info (12134): Parameter "LPM_WIDTHB" = "14"
+    Info (12134): Parameter "LPM_WIDTHP" = "16"
+    Info (12134): Parameter "LPM_WIDTHR" = "16"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult2|multcore:mult_core", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult2"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult2"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult2|altshift:external_latency_ffs", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult2"
+Info (12130): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult3"
+Info (12133): Instantiated megafunction "sobel_core:sobel_core_inst|lpm_mult:Mult3" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "4"
+    Info (12134): Parameter "LPM_WIDTHB" = "5"
+    Info (12134): Parameter "LPM_WIDTHP" = "9"
+    Info (12134): Parameter "LPM_WIDTHR" = "9"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult3"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult3"
+Info (12130): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult6"
+Info (12133): Instantiated megafunction "sobel_core:sobel_core_inst|lpm_mult:Mult6" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "3"
+    Info (12134): Parameter "LPM_WIDTHB" = "7"
+    Info (12134): Parameter "LPM_WIDTHP" = "10"
+    Info (12134): Parameter "LPM_WIDTHR" = "10"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult6"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult6"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult6|altshift:external_latency_ffs", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult6"
+Info (12130): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult4"
+Info (12133): Instantiated megafunction "sobel_core:sobel_core_inst|lpm_mult:Mult4" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "4"
+    Info (12134): Parameter "LPM_WIDTHB" = "7"
+    Info (12134): Parameter "LPM_WIDTHP" = "11"
+    Info (12134): Parameter "LPM_WIDTHR" = "11"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult4"
+Info (12131): Elaborated megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel_core:sobel_core_inst|lpm_mult:Mult4"
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 2188 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 93 input pins
+    Info (21059): Implemented 30 output pins
+    Info (21061): Implemented 2065 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 499 megabytes
+    Info: Processing ended: Tue Mar 08 16:21:55 2016
+    Info: Elapsed time: 00:00:16
+    Info: Total CPU time (on all processors): 00:00:07
+
+
diff --git a/Sobel/Sobel Quartus/output_files/sobel.map.smsg b/Sobel/Sobel Quartus/output_files/sobel.map.smsg
new file mode 100644
index 0000000..b20d3c9
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.map.smsg
@@ -0,0 +1 @@
+Warning (10268): Verilog HDL information at cycle.v(30): always construct contains both blocking and non-blocking assignments
diff --git a/Sobel/Sobel Quartus/output_files/sobel.map.summary b/Sobel/Sobel Quartus/output_files/sobel.map.summary
new file mode 100644
index 0000000..cf60495
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Tue Mar 08 16:21:55 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : sobel
+Top-level Entity Name : sobel
+Family : Cyclone III
+Total logic elements : 2,048
+    Total combinational functions : 1,846
+    Dedicated logic registers : 284
+Total registers : 284
+Total pins : 123
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/Sobel/Sobel Quartus/output_files/sobel.pin b/Sobel/Sobel Quartus/output_files/sobel.pin
new file mode 100644
index 0000000..fe9c438
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		2.5V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+CHIP  "sobel"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+vin_rsc_z[36]                : A8        : input  : 2.5 V             :         : 8         : N              
+vin_rsc_z[43]                : A9        : input  : 2.5 V             :         : 8         : N              
+vin_rsc_z[50]                : A10       : input  : 2.5 V             :         : 8         : N              
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+vin_rsc_z[45]                : A13       : input  : 2.5 V             :         : 7         : N              
+vin_rsc_z[20]                : A14       : input  : 2.5 V             :         : 7         : N              
+vin_rsc_z[13]                : A15       : input  : 2.5 V             :         : 7         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
+vin_rsc_z[48]                : AA8       : input  : 2.5 V             :         : 3         : N              
+vin_rsc_z[39]                : AA9       : input  : 2.5 V             :         : 3         : N              
+vin_rsc_z[19]                : AA10      : input  : 2.5 V             :         : 3         : N              
+vin_rsc_z[38]                : AA11      : input  : 2.5 V             :         : 3         : N              
+GND+                         : AA12      :        :                   :         : 4         :                
+vin_rsc_z[72]                : AA13      : input  : 2.5 V             :         : 4         : N              
+vin_rsc_z[76]                : AA14      : input  : 2.5 V             :         : 4         : N              
+vin_rsc_z[61]                : AA15      : input  : 2.5 V             :         : 4         : N              
+vin_rsc_z[27]                : AA16      : input  : 2.5 V             :         : 4         : N              
+vin_rsc_z[66]                : AA17      : input  : 2.5 V             :         : 4         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+vin_rsc_z[35]                : AB9       : input  : 2.5 V             :         : 3         : N              
+vin_rsc_z[5]                 : AB10      : input  : 2.5 V             :         : 3         : N              
+GND+                         : AB11      :        :                   :         : 3         :                
+GND+                         : AB12      :        :                   :         : 4         :                
+vin_rsc_z[12]                : AB13      : input  : 2.5 V             :         : 4         : N              
+vin_rsc_z[70]                : AB14      : input  : 2.5 V             :         : 4         : N              
+vin_rsc_z[73]                : AB15      : input  : 2.5 V             :         : 4         : N              
+vin_rsc_z[62]                : AB16      : input  : 2.5 V             :         : 4         : N              
+vin_rsc_z[65]                : AB17      : input  : 2.5 V             :         : 4         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+vout_rsc_z[11]               : B4        : output : 2.5 V             :         : 8         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+vin_rsc_z[47]                : B8        : input  : 2.5 V             :         : 8         : N              
+vin_rsc_z[33]                : B9        : input  : 2.5 V             :         : 8         : N              
+vin_rsc_z[49]                : B10       : input  : 2.5 V             :         : 8         : N              
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+vin_rsc_z[7]                 : B13       : input  : 2.5 V             :         : 7         : N              
+vin_rsc_z[79]                : B14       : input  : 2.5 V             :         : 7         : N              
+vin_rsc_z[89]                : B15       : input  : 2.5 V             :         : 7         : N              
+vin_rsc_z[14]                : B16       : input  : 2.5 V             :         : 7         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+vout_rsc_z[29]               : C1        : output : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+vin_rsc_z[25]                : C13       : input  : 2.5 V             :         : 7         : N              
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
+vout_rsc_z[6]                : D2        : output : 2.5 V             :         : 1         : N              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
+vin_rsc_z[44]                : D10       : input  : 2.5 V             :         : 8         : N              
+VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
+vin_rsc_z[29]                : D13       : input  : 2.5 V             :         : 7         : N              
+VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
+VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+vout_rsc_z[27]               : E1        : output : 2.5 V             :         : 1         : N              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
+vout_rsc_z[12]               : E3        : output : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
+vin_rsc_z[46]                : E10       : input  : 2.5 V             :         : 8         : N              
+vin_rsc_z[31]                : E11       : input  : 2.5 V             :         : 7         : N              
+vin_rsc_z[40]                : E12       : input  : 2.5 V             :         : 7         : N              
+vin_rsc_z[18]                : E13       : input  : 2.5 V             :         : 7         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+vout_rsc_z[16]               : F1        : output : 2.5 V             :         : 1         : N              
+vout_rsc_z[4]                : F2        : output : 2.5 V             :         : 1         : N              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
+vin_rsc_z[53]                : F11       : input  : 2.5 V             :         : 7         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7         :                
+vin_rsc_z[75]                : F13       : input  : 2.5 V             :         : 7         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+arst_n                       : G1        : input  : 2.5 V             :         : 1         : N              
+clk                          : G2        : input  : 2.5 V             :         : 1         : N              
+vout_rsc_z[19]               : G3        : output : 2.5 V             :         : 1         : N              
+vout_rsc_z[23]               : G4        : output : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G5        :        :                   :         : 1         :                
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
+vin_rsc_z[37]                : G11       : input  : 2.5 V             :         : 8         : N              
+vin_rsc_z[22]                : G12       : input  : 2.5 V             :         : 7         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+GND+                         : G21       :        :                   :         : 6         :                
+GND+                         : G22       :        :                   :         : 6         :                
+vout_rsc_z[21]               : H1        : output : 2.5 V             :         : 1         : N              
+vout_rsc_z[8]                : H2        : output : 2.5 V             :         : 1         : N              
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H5        :        :                   :         : 1         :                
+vout_rsc_z[15]               : H6        : output : 2.5 V             :         : 1         : N              
+vout_rsc_z[17]               : H7        : output : 2.5 V             :         : 1         : N              
+GND                          : H8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
+vin_rsc_z[59]                : H11       : input  : 2.5 V             :         : 8         : N              
+vin_rsc_z[0]                 : H12       : input  : 2.5 V             :         : 7         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
+vin_rsc_z[28]                : H22       : input  : 2.5 V             :         : 6         : N              
+vout_rsc_z[2]                : J1        : output : 2.5 V             :         : 1         : N              
+vout_rsc_z[7]                : J2        : output : 2.5 V             :         : 1         : N              
+vout_rsc_z[18]               : J3        : output : 2.5 V             :         : 1         : N              
+vout_rsc_z[1]                : J4        : output : 2.5 V             :         : 1         : N              
+GND                          : J5        : gnd    :                   :         :           :                
+vout_rsc_z[3]                : J6        : output : 2.5 V             :         : 1         : N              
+vout_rsc_z[13]               : J7        : output : 2.5 V             :         : 1         : N              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+vin_rsc_z[21]                : J15       : input  : 2.5 V             :         : 6         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
+vin_rsc_z[55]                : J22       : input  : 2.5 V             :         : 6         : N              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+vout_rsc_z[0]                : K7        : output : 2.5 V             :         : 1         : N              
+vout_rsc_z[10]               : K8        : output : 2.5 V             :         : 1         : N              
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+vin_rsc_z[24]                : K15       : input  : 2.5 V             :         : 6         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
+vin_rsc_z[11]                : K19       : input  : 2.5 V             :         : 6         : N              
+MSEL3                        : K20       :        :                   :         : 6         :                
+vin_rsc_z[56]                : K21       : input  : 2.5 V             :         : 6         : N              
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+vout_rsc_z[28]               : L6        : output : 2.5 V             :         : 2         : N              
+vin_rsc_z[87]                : L7        : input  : 2.5 V             :         : 2         : N              
+vin_rsc_z[58]                : L8        : input  : 2.5 V             :         : 1         : N              
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+vin_rsc_z[23]                : L15       : input  : 2.5 V             :         : 6         : N              
+vin_rsc_z[8]                 : L16       : input  : 2.5 V             :         : 6         : N              
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+vin_rsc_z[74]                : L21       : input  : 2.5 V             :         : 6         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
+vout_rsc_z[22]               : M1        : output : 2.5 V             :         : 2         : N              
+vout_rsc_z[14]               : M2        : output : 2.5 V             :         : 2         : N              
+vout_rsc_z[25]               : M3        : output : 2.5 V             :         : 2         : N              
+vout_rsc_z[9]                : M4        : output : 2.5 V             :         : 2         : N              
+vin_rsc_z[30]                : M5        : input  : 2.5 V             :         : 2         : N              
+vout_rsc_z[20]               : M6        : output : 2.5 V             :         : 2         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+vin_rsc_z[9]                 : M16       : input  : 2.5 V             :         : 5         : N              
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+vin_rsc_z[3]                 : M19       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[17]                : M20       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[4]                 : M21       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[16]                : M22       : input  : 2.5 V             :         : 5         : N              
+vout_rsc_z[24]               : N1        : output : 2.5 V             :         : 2         : N              
+vout_rsc_z[5]                : N2        : output : 2.5 V             :         : 2         : N              
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
+vin_rsc_z[67]                : N5        : input  : 2.5 V             :         : 2         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+vin_rsc_z[78]                : N16       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[82]                : N17       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[26]                : N18       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[84]                : N19       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[88]                : N20       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[2]                 : N21       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[10]                : N22       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[41]                : P1        : input  : 2.5 V             :         : 2         : N              
+vin_rsc_z[32]                : P2        : input  : 2.5 V             :         : 2         : N              
+vout_rsc_z[26]               : P3        : output : 2.5 V             :         : 2         : N              
+vin_rsc_z[42]                : P4        : input  : 2.5 V             :         : 2         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+vin_rsc_z[63]                : P20       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[83]                : P21       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[81]                : P22       : input  : 2.5 V             :         : 5         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+vin_rsc_z[77]                : R2        : input  : 2.5 V             :         : 2         : N              
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+vin_rsc_z[64]                : R18       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[68]                : R19       : input  : 2.5 V             :         : 5         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+vin_rsc_z[71]                : R21       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[60]                : R22       : input  : 2.5 V             :         : 5         : N              
+vin_rsc_z[57]                : T1        : input  : 2.5 V             :         : 2         : N              
+en                           : T2        : input  : 2.5 V             :         : 2         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
+vin_rsc_z[34]                : T11       : input  : 2.5 V             :         : 3         : N              
+vin_rsc_z[1]                 : T12       : input  : 2.5 V             :         : 4         : N              
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
+vin_rsc_z[54]                : U11       : input  : 2.5 V             :         : 3         : N              
+vin_rsc_z[86]                : U12       : input  : 2.5 V             :         : 4         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+vin_rsc_z[51]                : V11       : input  : 2.5 V             :         : 3         : N              
+vin_rsc_z[69]                : V12       : input  : 2.5 V             :         : 4         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
+vin_rsc_z[52]                : W10       : input  : 2.5 V             :         : 3         : N              
+VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+vin_rsc_z[85]                : W13       : input  : 2.5 V             :         : 4         : N              
+vin_rsc_z[6]                 : W14       : input  : 2.5 V             :         : 4         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+vin_rsc_z[15]                : Y10       : input  : 2.5 V             :         : 3         : N              
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+vin_rsc_z[80]                : Y13       : input  : 2.5 V             :         : 4         : N              
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/Sobel/Sobel Quartus/output_files/sobel.sof b/Sobel/Sobel Quartus/output_files/sobel.sof
new file mode 100644
index 0000000..355283c
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.sof
diff --git a/Sobel/Sobel Quartus/output_files/sobel.sta.rpt b/Sobel/Sobel Quartus/output_files/sobel.sta.rpt
new file mode 100644
index 0000000..3f89117
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.sta.rpt
@@ -0,0 +1,2742 @@
+TimeQuest Timing Analyzer report for sobel
+Tue Mar 08 16:22:33 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Setup: 'clk'
+ 13. Slow 1200mV 85C Model Hold: 'clk'
+ 14. Slow 1200mV 85C Model Minimum Pulse Width: 'clk'
+ 15. Setup Times
+ 16. Hold Times
+ 17. Clock to Output Times
+ 18. Minimum Clock to Output Times
+ 19. Slow 1200mV 85C Model Metastability Report
+ 20. Slow 1200mV 0C Model Fmax Summary
+ 21. Slow 1200mV 0C Model Setup Summary
+ 22. Slow 1200mV 0C Model Hold Summary
+ 23. Slow 1200mV 0C Model Recovery Summary
+ 24. Slow 1200mV 0C Model Removal Summary
+ 25. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 26. Slow 1200mV 0C Model Setup: 'clk'
+ 27. Slow 1200mV 0C Model Hold: 'clk'
+ 28. Slow 1200mV 0C Model Minimum Pulse Width: 'clk'
+ 29. Setup Times
+ 30. Hold Times
+ 31. Clock to Output Times
+ 32. Minimum Clock to Output Times
+ 33. Slow 1200mV 0C Model Metastability Report
+ 34. Fast 1200mV 0C Model Setup Summary
+ 35. Fast 1200mV 0C Model Hold Summary
+ 36. Fast 1200mV 0C Model Recovery Summary
+ 37. Fast 1200mV 0C Model Removal Summary
+ 38. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 39. Fast 1200mV 0C Model Setup: 'clk'
+ 40. Fast 1200mV 0C Model Hold: 'clk'
+ 41. Fast 1200mV 0C Model Minimum Pulse Width: 'clk'
+ 42. Setup Times
+ 43. Hold Times
+ 44. Clock to Output Times
+ 45. Minimum Clock to Output Times
+ 46. Fast 1200mV 0C Model Metastability Report
+ 47. Multicorner Timing Analysis Summary
+ 48. Setup Times
+ 49. Hold Times
+ 50. Clock to Output Times
+ 51. Minimum Clock to Output Times
+ 52. Board Trace Model Assignments
+ 53. Input Transition Times
+ 54. Slow Corner Signal Integrity Metrics
+ 55. Fast Corner Signal Integrity Metrics
+ 56. Setup Transfers
+ 57. Hold Transfers
+ 58. Report TCCS
+ 59. Report RSKM
+ 60. Unconstrained Paths
+ 61. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                       ;
++--------------------+--------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ;
+; Revision Name      ; sobel                                                              ;
+; Device Family      ; Cyclone III                                                        ;
+; Device Name        ; EP3C16F484C6                                                       ;
+; Timing Models      ; Final                                                              ;
+; Delay Model        ; Combined                                                           ;
+; Rise/Fall Delays   ; Enabled                                                            ;
++--------------------+--------------------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                          ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+; clk        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk } ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+
+
++-------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary              ;
++-----------+-----------------+------------+------+
+; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
++-----------+-----------------+------------+------+
+; 44.75 MHz ; 44.75 MHz       ; clk        ;      ;
++-----------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++-------------------------------------+
+; Slow 1200mV 85C Model Setup Summary ;
++-------+---------+-------------------+
+; Clock ; Slack   ; End Point TNS     ;
++-------+---------+-------------------+
+; clk   ; -21.345 ; -1510.709         ;
++-------+---------+-------------------+
+
+
++------------------------------------+
+; Slow 1200mV 85C Model Hold Summary ;
++-------+-------+--------------------+
+; Clock ; Slack ; End Point TNS      ;
++-------+-------+--------------------+
+; clk   ; 0.516 ; 0.000              ;
++-------+-------+--------------------+
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
++-------+--------+----------------------------------+
+; Clock ; Slack  ; End Point TNS                    ;
++-------+--------+----------------------------------+
+; clk   ; -3.000 ; -287.000                         ;
++-------+--------+----------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'clk'                                                                                                                                                                       ;
++---------+---------------------------------------------------------------+----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                     ; To Node                                                  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------+----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -21.345 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.634     ;
+; -21.294 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.583     ;
+; -21.178 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.467     ;
+; -21.158 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.447     ;
+; -21.077 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.285      ; 22.357     ;
+; -21.068 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.285      ; 22.348     ;
+; -21.067 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.356     ;
+; -21.022 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.311     ;
+; -21.012 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.301     ;
+; -20.988 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.285      ; 22.268     ;
+; -20.971 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.260     ;
+; -20.948 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.285      ; 22.228     ;
+; -20.934 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.285      ; 22.214     ;
+; -20.901 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.190     ;
+; -20.890 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.294      ; 22.179     ;
+; -20.890 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.179     ;
+; -20.855 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.144     ;
+; -20.850 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.139     ;
+; -20.839 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.294      ; 22.128     ;
+; -20.839 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.128     ;
+; -20.835 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.124     ;
+; -20.824 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.113     ;
+; -20.754 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.285      ; 22.034     ;
+; -20.745 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.285      ; 22.025     ;
+; -20.744 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.033     ;
+; -20.743 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[8]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.032     ;
+; -20.737 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.026     ;
+; -20.736 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.294      ; 22.025     ;
+; -20.734 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.023     ;
+; -20.723 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.294      ; 22.012     ;
+; -20.723 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.012     ;
+; -20.714 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.003     ;
+; -20.711 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.294      ; 22.000     ;
+; -20.703 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.992     ;
+; -20.703 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.992     ;
+; -20.689 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.978     ;
+; -20.686 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.975     ;
+; -20.685 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.974     ;
+; -20.665 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.945     ;
+; -20.660 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.949     ;
+; -20.633 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.913     ;
+; -20.625 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.905     ;
+; -20.624 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.904     ;
+; -20.623 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.912     ;
+; -20.622 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.285      ; 21.902     ;
+; -20.622 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.902     ;
+; -20.613 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.285      ; 21.893     ;
+; -20.613 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.893     ;
+; -20.612 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.901     ;
+; -20.612 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.901     ;
+; -20.611 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.891     ;
+; -20.590 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.879     ;
+; -20.588 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.877     ;
+; -20.570 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.859     ;
+; -20.569 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.858     ;
+; -20.568 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.857     ;
+; -20.557 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.846     ;
+; -20.557 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.846     ;
+; -20.550 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.839     ;
+; -20.549 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.838     ;
+; -20.544 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.833     ;
+; -20.544 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.824     ;
+; -20.539 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.828     ;
+; -20.537 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.826     ;
+; -20.533 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.285      ; 21.813     ;
+; -20.533 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.813     ;
+; -20.524 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.813     ;
+; -20.504 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.784     ;
+; -20.501 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.790     ;
+; -20.493 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.285      ; 21.773     ;
+; -20.493 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.773     ;
+; -20.490 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.770     ;
+; -20.482 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[17] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.771     ;
+; -20.481 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[7]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.770     ;
+; -20.479 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.285      ; 21.759     ;
+; -20.479 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.759     ;
+; -20.469 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.749     ;
+; -20.468 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.285      ; 21.748     ;
+; -20.460 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.740     ;
+; -20.459 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.748     ;
+; -20.459 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.285      ; 21.739     ;
+; -20.458 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.747     ;
+; -20.443 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.723     ;
+; -20.438 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[10]             ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.727     ;
+; -20.434 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.714     ;
+; -20.433 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.722     ;
+; -20.431 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[17] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.720     ;
+; -20.430 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[7]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.719     ;
+; -20.423 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.712     ;
+; -20.421 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.710     ;
+; -20.420 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[8]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.709     ;
+; -20.404 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.693     ;
+; -20.403 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.692     ;
+; -20.403 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.692     ;
+; -20.401 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.690     ;
+; -20.380 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.669     ;
+; -20.380 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.285      ; 21.660     ;
+; -20.379 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.285      ; 21.659     ;
+; -20.378 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.294      ; 21.667     ;
+; -20.369 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.294      ; 21.658     ;
++---------+---------------------------------------------------------------+----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'clk'                                                                                                                                                                     ;
++-------+--------------------------------------------------------+----------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                              ; To Node                                                        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------------------------------------+----------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.516 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[57] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[7]  ; clk          ; clk         ; 0.000        ; 0.062      ; 0.735      ;
+; 0.518 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[51] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[1]  ; clk          ; clk         ; 0.000        ; 0.062      ; 0.737      ;
+; 0.518 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[35] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[5]  ; clk          ; clk         ; 0.000        ; 0.061      ; 0.736      ;
+; 0.519 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[34] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[4]  ; clk          ; clk         ; 0.000        ; 0.062      ; 0.738      ;
+; 0.534 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[61] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[1] ; clk          ; clk         ; 0.000        ; 0.062      ; 0.753      ;
+; 0.538 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[78] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[8] ; clk          ; clk         ; 0.000        ; 0.062      ; 0.757      ;
+; 0.550 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[70] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[0] ; clk          ; clk         ; 0.000        ; 0.062      ; 0.769      ;
+; 0.553 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[63] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[3] ; clk          ; clk         ; 0.000        ; 0.062      ; 0.772      ;
+; 0.660 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[30] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[0]  ; clk          ; clk         ; 0.000        ; 0.061      ; 0.878      ;
+; 0.662 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[52] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[2]  ; clk          ; clk         ; 0.000        ; 0.062      ; 0.881      ;
+; 0.673 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[79] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[9] ; clk          ; clk         ; 0.000        ; 0.062      ; 0.892      ;
+; 0.674 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[64] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[4] ; clk          ; clk         ; 0.000        ; 0.062      ; 0.893      ;
+; 0.682 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[53] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[3]  ; clk          ; clk         ; 0.000        ; 0.062      ; 0.901      ;
+; 0.688 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[73] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[3] ; clk          ; clk         ; 0.000        ; 0.062      ; 0.907      ;
+; 0.703 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[75] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[5] ; clk          ; clk         ; 0.000        ; 0.062      ; 0.922      ;
+; 0.706 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[60] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[0] ; clk          ; clk         ; 0.000        ; 0.062      ; 0.925      ;
+; 0.706 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[71] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[1] ; clk          ; clk         ; 0.000        ; 0.062      ; 0.925      ;
+; 0.725 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[31] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[1]  ; clk          ; clk         ; 0.000        ; 0.062      ; 0.944      ;
+; 0.727 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[42] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[2]  ; clk          ; clk         ; 0.000        ; 0.062      ; 0.946      ;
+; 0.733 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[2]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[2]  ; clk          ; clk         ; 0.000        ; 0.061      ; 0.951      ;
+; 0.733 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[16] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[6]  ; clk          ; clk         ; 0.000        ; 0.061      ; 0.951      ;
+; 0.734 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[13] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[3]  ; clk          ; clk         ; 0.000        ; 0.061      ; 0.952      ;
+; 0.736 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[33] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[3]  ; clk          ; clk         ; 0.000        ; 0.062      ; 0.955      ;
+; 0.743 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[67] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[7] ; clk          ; clk         ; 0.000        ; -0.289     ; 0.611      ;
+; 0.754 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[62] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[2] ; clk          ; clk         ; 0.000        ; 0.062      ; 0.973      ;
+; 0.782 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[76] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[6] ; clk          ; clk         ; 0.000        ; 0.069      ; 1.008      ;
+; 0.803 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[59] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[9]  ; clk          ; clk         ; 0.000        ; 0.053      ; 1.013      ;
+; 0.847 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[39] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[9]  ; clk          ; clk         ; 0.000        ; 0.062      ; 1.066      ;
+; 0.868 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[10] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[0]  ; clk          ; clk         ; 0.000        ; 0.061      ; 1.086      ;
+; 0.870 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[48] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[8]  ; clk          ; clk         ; 0.000        ; 0.062      ; 1.089      ;
+; 0.872 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[11] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[1]  ; clk          ; clk         ; 0.000        ; 0.061      ; 1.090      ;
+; 0.872 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[43] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[3]  ; clk          ; clk         ; 0.000        ; 0.062      ; 1.091      ;
+; 0.875 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[4]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[4]  ; clk          ; clk         ; 0.000        ; 0.061      ; 1.093      ;
+; 0.875 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[14] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[4]  ; clk          ; clk         ; 0.000        ; 0.061      ; 1.093      ;
+; 0.875 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[47] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[7]  ; clk          ; clk         ; 0.000        ; 0.062      ; 1.094      ;
+; 0.877 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[12] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[2]  ; clk          ; clk         ; 0.000        ; 0.061      ; 1.095      ;
+; 0.882 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[40] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[0]  ; clk          ; clk         ; 0.000        ; 0.062      ; 1.101      ;
+; 0.882 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[37] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[7]  ; clk          ; clk         ; 0.000        ; 0.061      ; 1.100      ;
+; 0.884 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[68] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[8] ; clk          ; clk         ; 0.000        ; 0.062      ; 1.103      ;
+; 0.897 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[0]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[0]  ; clk          ; clk         ; 0.000        ; 0.061      ; 1.115      ;
+; 0.897 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[18] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[8]  ; clk          ; clk         ; 0.000        ; 0.061      ; 1.115      ;
+; 0.899 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[72] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[2] ; clk          ; clk         ; 0.000        ; 0.062      ; 1.118      ;
+; 0.911 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[32] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[2]  ; clk          ; clk         ; 0.000        ; 0.062      ; 1.130      ;
+; 0.913 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[41] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[1]  ; clk          ; clk         ; 0.000        ; 0.062      ; 1.132      ;
+; 0.916 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[56] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[6]  ; clk          ; clk         ; 0.000        ; 0.053      ; 1.126      ;
+; 0.926 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[6]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[6]  ; clk          ; clk         ; 0.000        ; 0.061      ; 1.144      ;
+; 0.932 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[66] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[6] ; clk          ; clk         ; 0.000        ; 0.065      ; 1.154      ;
+; 0.949 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[50] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[0]  ; clk          ; clk         ; 0.000        ; 0.053      ; 1.159      ;
+; 0.975 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[46] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[6]  ; clk          ; clk         ; 0.000        ; 0.062      ; 1.194      ;
+; 0.996 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[23] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[3]    ; clk          ; clk         ; 0.000        ; 0.087      ; 1.240      ;
+; 0.997 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[21] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[1]    ; clk          ; clk         ; 0.000        ; 0.086      ; 1.240      ;
+; 1.049 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[74] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[4] ; clk          ; clk         ; 0.000        ; 0.072      ; 1.278      ;
+; 1.096 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[77] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[7] ; clk          ; clk         ; 0.000        ; 0.062      ; 1.315      ;
+; 1.113 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[8]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[8]  ; clk          ; clk         ; 0.000        ; 0.060      ; 1.330      ;
+; 1.120 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[17] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[7]  ; clk          ; clk         ; 0.000        ; 0.061      ; 1.338      ;
+; 1.127 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[55] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[5]  ; clk          ; clk         ; 0.000        ; 0.053      ; 1.337      ;
+; 1.133 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[24] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[4]    ; clk          ; clk         ; 0.000        ; 0.086      ; 1.376      ;
+; 1.133 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[28] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[8]    ; clk          ; clk         ; 0.000        ; 0.086      ; 1.376      ;
+; 1.140 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[1]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[1]  ; clk          ; clk         ; 0.000        ; 0.060      ; 1.357      ;
+; 1.151 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[25] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[5]    ; clk          ; clk         ; 0.000        ; 0.086      ; 1.394      ;
+; 1.152 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[7]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[7]  ; clk          ; clk         ; 0.000        ; 0.060      ; 1.369      ;
+; 1.153 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[54] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[4]  ; clk          ; clk         ; 0.000        ; 0.053      ; 1.363      ;
+; 1.156 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[65] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[5] ; clk          ; clk         ; 0.000        ; 0.062      ; 1.375      ;
+; 1.204 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[84] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[4]  ; clk          ; clk         ; 0.000        ; -0.289     ; 1.072      ;
+; 1.222 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[80] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[0]  ; clk          ; clk         ; 0.000        ; -0.289     ; 1.090      ;
+; 1.233 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[86] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[6]  ; clk          ; clk         ; 0.000        ; -0.289     ; 1.101      ;
+; 1.251 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[5]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[5]  ; clk          ; clk         ; 0.000        ; 0.060      ; 1.468      ;
+; 1.257 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[3]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[3]  ; clk          ; clk         ; 0.000        ; 0.060      ; 1.474      ;
+; 1.267 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[88] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[8]  ; clk          ; clk         ; 0.000        ; -0.289     ; 1.135      ;
+; 1.282 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[83] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[3]  ; clk          ; clk         ; 0.000        ; -0.289     ; 1.150      ;
+; 1.362 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[22] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[2]    ; clk          ; clk         ; 0.000        ; 0.086      ; 1.605      ;
+; 1.374 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[27] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[7]    ; clk          ; clk         ; 0.000        ; 0.086      ; 1.617      ;
+; 1.378 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[26] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[6]    ; clk          ; clk         ; 0.000        ; 0.086      ; 1.621      ;
+; 1.384 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[20] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[0]    ; clk          ; clk         ; 0.000        ; 0.086      ; 1.627      ;
+; 1.389 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[29] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[9]    ; clk          ; clk         ; 0.000        ; 0.086      ; 1.632      ;
+; 1.408 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[85] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[5]  ; clk          ; clk         ; 0.000        ; -0.289     ; 1.276      ;
+; 1.434 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[36] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[6]  ; clk          ; clk         ; 0.000        ; 0.062      ; 1.653      ;
+; 1.455 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[38] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[8]  ; clk          ; clk         ; 0.000        ; -0.289     ; 1.323      ;
+; 1.457 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[44] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[4]  ; clk          ; clk         ; 0.000        ; -0.296     ; 1.318      ;
+; 1.471 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[45] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[5]  ; clk          ; clk         ; 0.000        ; 0.053      ; 1.681      ;
+; 1.549 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[58] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[8]  ; clk          ; clk         ; 0.000        ; 0.053      ; 1.759      ;
+; 1.557 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[49] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[9]  ; clk          ; clk         ; 0.000        ; 0.062      ; 1.776      ;
+; 1.594 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[9]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[9]  ; clk          ; clk         ; 0.000        ; 0.061      ; 1.812      ;
+; 1.626 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]        ; clk          ; clk         ; 0.000        ; 0.434      ; 2.217      ;
+; 1.626 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10]       ; clk          ; clk         ; 0.000        ; 0.434      ; 2.217      ;
+; 1.626 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11]       ; clk          ; clk         ; 0.000        ; 0.434      ; 2.217      ;
+; 1.626 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[16]       ; clk          ; clk         ; 0.000        ; 0.434      ; 2.217      ;
+; 1.626 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18]       ; clk          ; clk         ; 0.000        ; 0.434      ; 2.217      ;
+; 1.626 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20]       ; clk          ; clk         ; 0.000        ; 0.434      ; 2.217      ;
+; 1.626 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21]       ; clk          ; clk         ; 0.000        ; 0.434      ; 2.217      ;
+; 1.626 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[27]       ; clk          ; clk         ; 0.000        ; 0.434      ; 2.217      ;
+; 1.626 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[28]       ; clk          ; clk         ; 0.000        ; 0.434      ; 2.217      ;
+; 1.626 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[29]       ; clk          ; clk         ; 0.000        ; 0.434      ; 2.217      ;
+; 1.629 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[5]        ; clk          ; clk         ; 0.000        ; 0.434      ; 2.220      ;
+; 1.629 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]        ; clk          ; clk         ; 0.000        ; 0.434      ; 2.220      ;
+; 1.629 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[7]        ; clk          ; clk         ; 0.000        ; 0.434      ; 2.220      ;
+; 1.629 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]        ; clk          ; clk         ; 0.000        ; 0.434      ; 2.220      ;
+; 1.629 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[17]       ; clk          ; clk         ; 0.000        ; 0.434      ; 2.220      ;
+; 1.629 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19]       ; clk          ; clk         ; 0.000        ; 0.434      ; 2.220      ;
+; 1.629 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[25]       ; clk          ; clk         ; 0.000        ; 0.434      ; 2.220      ;
++-------+--------------------------------------------------------+----------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'clk'                                                                                         ;
++--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type       ; Clock ; Clock Edge ; Target                                                        ;
++--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; clk   ; Rise       ; clk                                                           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[11]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[11]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[12]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[11]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[12]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[11]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[12]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[13]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[0]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[1]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[2]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[3]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[4]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_2[0]               ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_2[1]               ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|main_stage_0_2                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[0]         ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[10]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[11]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[12]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[13]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[14]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[15]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[16]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[17]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[18]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[19]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[1]         ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[20]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[21]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[22]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[23]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[24]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[25]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[26]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[27]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[28]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[29]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[2]         ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[30]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[31]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[32]        ;
++--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------+
+; Setup Times                                                                  ;
++----------------+------------+--------+--------+------------+-----------------+
+; Data Port      ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++----------------+------------+--------+--------+------------+-----------------+
+; en             ; clk        ; 2.702  ; 2.727  ; Rise       ; clk             ;
+; vin_rsc_z[*]   ; clk        ; 24.641 ; 25.299 ; Rise       ; clk             ;
+;  vin_rsc_z[0]  ; clk        ; 23.788 ; 24.281 ; Rise       ; clk             ;
+;  vin_rsc_z[1]  ; clk        ; 23.558 ; 23.820 ; Rise       ; clk             ;
+;  vin_rsc_z[2]  ; clk        ; 23.481 ; 23.940 ; Rise       ; clk             ;
+;  vin_rsc_z[3]  ; clk        ; 23.493 ; 23.716 ; Rise       ; clk             ;
+;  vin_rsc_z[4]  ; clk        ; 23.315 ; 23.765 ; Rise       ; clk             ;
+;  vin_rsc_z[5]  ; clk        ; 23.699 ; 24.042 ; Rise       ; clk             ;
+;  vin_rsc_z[6]  ; clk        ; 22.802 ; 23.457 ; Rise       ; clk             ;
+;  vin_rsc_z[7]  ; clk        ; 23.105 ; 23.515 ; Rise       ; clk             ;
+;  vin_rsc_z[8]  ; clk        ; 22.872 ; 23.500 ; Rise       ; clk             ;
+;  vin_rsc_z[9]  ; clk        ; 22.722 ; 22.949 ; Rise       ; clk             ;
+;  vin_rsc_z[10] ; clk        ; 23.605 ; 24.117 ; Rise       ; clk             ;
+;  vin_rsc_z[11] ; clk        ; 23.616 ; 23.947 ; Rise       ; clk             ;
+;  vin_rsc_z[12] ; clk        ; 23.709 ; 24.278 ; Rise       ; clk             ;
+;  vin_rsc_z[13] ; clk        ; 23.713 ; 24.006 ; Rise       ; clk             ;
+;  vin_rsc_z[14] ; clk        ; 23.397 ; 24.030 ; Rise       ; clk             ;
+;  vin_rsc_z[15] ; clk        ; 23.492 ; 23.808 ; Rise       ; clk             ;
+;  vin_rsc_z[16] ; clk        ; 22.771 ; 23.282 ; Rise       ; clk             ;
+;  vin_rsc_z[17] ; clk        ; 22.814 ; 23.108 ; Rise       ; clk             ;
+;  vin_rsc_z[18] ; clk        ; 22.797 ; 23.346 ; Rise       ; clk             ;
+;  vin_rsc_z[19] ; clk        ; 22.937 ; 23.255 ; Rise       ; clk             ;
+;  vin_rsc_z[20] ; clk        ; 23.768 ; 24.318 ; Rise       ; clk             ;
+;  vin_rsc_z[21] ; clk        ; 23.934 ; 24.231 ; Rise       ; clk             ;
+;  vin_rsc_z[22] ; clk        ; 23.370 ; 23.940 ; Rise       ; clk             ;
+;  vin_rsc_z[23] ; clk        ; 23.733 ; 23.983 ; Rise       ; clk             ;
+;  vin_rsc_z[24] ; clk        ; 23.179 ; 23.780 ; Rise       ; clk             ;
+;  vin_rsc_z[25] ; clk        ; 23.423 ; 23.711 ; Rise       ; clk             ;
+;  vin_rsc_z[26] ; clk        ; 22.868 ; 23.356 ; Rise       ; clk             ;
+;  vin_rsc_z[27] ; clk        ; 22.761 ; 23.085 ; Rise       ; clk             ;
+;  vin_rsc_z[28] ; clk        ; 22.935 ; 23.501 ; Rise       ; clk             ;
+;  vin_rsc_z[29] ; clk        ; 22.790 ; 23.076 ; Rise       ; clk             ;
+;  vin_rsc_z[30] ; clk        ; 24.641 ; 25.299 ; Rise       ; clk             ;
+;  vin_rsc_z[31] ; clk        ; 24.355 ; 24.800 ; Rise       ; clk             ;
+;  vin_rsc_z[32] ; clk        ; 24.384 ; 25.042 ; Rise       ; clk             ;
+;  vin_rsc_z[33] ; clk        ; 23.600 ; 24.015 ; Rise       ; clk             ;
+;  vin_rsc_z[34] ; clk        ; 23.423 ; 23.960 ; Rise       ; clk             ;
+;  vin_rsc_z[35] ; clk        ; 23.186 ; 23.565 ; Rise       ; clk             ;
+;  vin_rsc_z[36] ; clk        ; 22.876 ; 23.459 ; Rise       ; clk             ;
+;  vin_rsc_z[37] ; clk        ; 22.877 ; 23.219 ; Rise       ; clk             ;
+;  vin_rsc_z[38] ; clk        ; 20.964 ; 21.256 ; Rise       ; clk             ;
+;  vin_rsc_z[39] ; clk        ; 22.787 ; 23.071 ; Rise       ; clk             ;
+;  vin_rsc_z[40] ; clk        ; 24.489 ; 25.171 ; Rise       ; clk             ;
+;  vin_rsc_z[41] ; clk        ; 24.418 ; 24.854 ; Rise       ; clk             ;
+;  vin_rsc_z[42] ; clk        ; 24.207 ; 24.869 ; Rise       ; clk             ;
+;  vin_rsc_z[43] ; clk        ; 23.571 ; 24.005 ; Rise       ; clk             ;
+;  vin_rsc_z[44] ; clk        ; 23.087 ; 23.640 ; Rise       ; clk             ;
+;  vin_rsc_z[45] ; clk        ; 23.356 ; 23.713 ; Rise       ; clk             ;
+;  vin_rsc_z[46] ; clk        ; 22.881 ; 23.451 ; Rise       ; clk             ;
+;  vin_rsc_z[47] ; clk        ; 22.887 ; 23.239 ; Rise       ; clk             ;
+;  vin_rsc_z[48] ; clk        ; 22.779 ; 23.453 ; Rise       ; clk             ;
+;  vin_rsc_z[49] ; clk        ; 22.641 ; 22.912 ; Rise       ; clk             ;
+;  vin_rsc_z[50] ; clk        ; 24.425 ; 25.082 ; Rise       ; clk             ;
+;  vin_rsc_z[51] ; clk        ; 24.464 ; 24.902 ; Rise       ; clk             ;
+;  vin_rsc_z[52] ; clk        ; 24.313 ; 24.972 ; Rise       ; clk             ;
+;  vin_rsc_z[53] ; clk        ; 23.987 ; 24.442 ; Rise       ; clk             ;
+;  vin_rsc_z[54] ; clk        ; 23.694 ; 24.379 ; Rise       ; clk             ;
+;  vin_rsc_z[55] ; clk        ; 23.635 ; 24.030 ; Rise       ; clk             ;
+;  vin_rsc_z[56] ; clk        ; 23.402 ; 24.064 ; Rise       ; clk             ;
+;  vin_rsc_z[57] ; clk        ; 21.643 ; 21.716 ; Rise       ; clk             ;
+;  vin_rsc_z[58] ; clk        ; 23.306 ; 23.951 ; Rise       ; clk             ;
+;  vin_rsc_z[59] ; clk        ; 22.797 ; 23.282 ; Rise       ; clk             ;
+;  vin_rsc_z[60] ; clk        ; 23.536 ; 23.819 ; Rise       ; clk             ;
+;  vin_rsc_z[61] ; clk        ; 23.378 ; 24.000 ; Rise       ; clk             ;
+;  vin_rsc_z[62] ; clk        ; 23.417 ; 23.763 ; Rise       ; clk             ;
+;  vin_rsc_z[63] ; clk        ; 23.088 ; 23.662 ; Rise       ; clk             ;
+;  vin_rsc_z[64] ; clk        ; 23.188 ; 23.621 ; Rise       ; clk             ;
+;  vin_rsc_z[65] ; clk        ; 23.321 ; 24.040 ; Rise       ; clk             ;
+;  vin_rsc_z[66] ; clk        ; 22.965 ; 23.342 ; Rise       ; clk             ;
+;  vin_rsc_z[67] ; clk        ; 22.921 ; 23.422 ; Rise       ; clk             ;
+;  vin_rsc_z[68] ; clk        ; 22.506 ; 23.023 ; Rise       ; clk             ;
+;  vin_rsc_z[69] ; clk        ; 22.713 ; 22.984 ; Rise       ; clk             ;
+;  vin_rsc_z[70] ; clk        ; 23.664 ; 23.985 ; Rise       ; clk             ;
+;  vin_rsc_z[71] ; clk        ; 23.267 ; 23.855 ; Rise       ; clk             ;
+;  vin_rsc_z[72] ; clk        ; 23.096 ; 23.593 ; Rise       ; clk             ;
+;  vin_rsc_z[73] ; clk        ; 23.288 ; 23.911 ; Rise       ; clk             ;
+;  vin_rsc_z[74] ; clk        ; 23.400 ; 23.880 ; Rise       ; clk             ;
+;  vin_rsc_z[75] ; clk        ; 23.348 ; 24.069 ; Rise       ; clk             ;
+;  vin_rsc_z[76] ; clk        ; 22.709 ; 23.109 ; Rise       ; clk             ;
+;  vin_rsc_z[77] ; clk        ; 22.730 ; 23.450 ; Rise       ; clk             ;
+;  vin_rsc_z[78] ; clk        ; 22.319 ; 22.822 ; Rise       ; clk             ;
+;  vin_rsc_z[79] ; clk        ; 22.558 ; 23.208 ; Rise       ; clk             ;
+;  vin_rsc_z[80] ; clk        ; 23.295 ; 23.860 ; Rise       ; clk             ;
+;  vin_rsc_z[81] ; clk        ; 22.975 ; 23.281 ; Rise       ; clk             ;
+;  vin_rsc_z[82] ; clk        ; 22.833 ; 23.376 ; Rise       ; clk             ;
+;  vin_rsc_z[83] ; clk        ; 22.915 ; 23.127 ; Rise       ; clk             ;
+;  vin_rsc_z[84] ; clk        ; 22.730 ; 23.175 ; Rise       ; clk             ;
+;  vin_rsc_z[85] ; clk        ; 22.689 ; 22.971 ; Rise       ; clk             ;
+;  vin_rsc_z[86] ; clk        ; 22.297 ; 22.840 ; Rise       ; clk             ;
+;  vin_rsc_z[87] ; clk        ; 22.609 ; 22.924 ; Rise       ; clk             ;
+;  vin_rsc_z[88] ; clk        ; 22.763 ; 23.264 ; Rise       ; clk             ;
+;  vin_rsc_z[89] ; clk        ; 22.473 ; 22.760 ; Rise       ; clk             ;
++----------------+------------+--------+--------+------------+-----------------+
+
+
++------------------------------------------------------------------------------+
+; Hold Times                                                                   ;
++----------------+------------+--------+--------+------------+-----------------+
+; Data Port      ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++----------------+------------+--------+--------+------------+-----------------+
+; en             ; clk        ; 0.247  ; 0.169  ; Rise       ; clk             ;
+; vin_rsc_z[*]   ; clk        ; 0.732  ; 0.645  ; Rise       ; clk             ;
+;  vin_rsc_z[0]  ; clk        ; -1.690 ; -2.186 ; Rise       ; clk             ;
+;  vin_rsc_z[1]  ; clk        ; -1.699 ; -2.208 ; Rise       ; clk             ;
+;  vin_rsc_z[2]  ; clk        ; -1.630 ; -2.063 ; Rise       ; clk             ;
+;  vin_rsc_z[3]  ; clk        ; -1.461 ; -1.892 ; Rise       ; clk             ;
+;  vin_rsc_z[4]  ; clk        ; -1.426 ; -1.840 ; Rise       ; clk             ;
+;  vin_rsc_z[5]  ; clk        ; -1.615 ; -2.132 ; Rise       ; clk             ;
+;  vin_rsc_z[6]  ; clk        ; -1.814 ; -2.352 ; Rise       ; clk             ;
+;  vin_rsc_z[7]  ; clk        ; -1.799 ; -2.298 ; Rise       ; clk             ;
+;  vin_rsc_z[8]  ; clk        ; -1.667 ; -2.136 ; Rise       ; clk             ;
+;  vin_rsc_z[9]  ; clk        ; -1.624 ; -2.029 ; Rise       ; clk             ;
+;  vin_rsc_z[10] ; clk        ; -1.378 ; -1.784 ; Rise       ; clk             ;
+;  vin_rsc_z[11] ; clk        ; -1.358 ; -1.787 ; Rise       ; clk             ;
+;  vin_rsc_z[12] ; clk        ; -1.734 ; -2.209 ; Rise       ; clk             ;
+;  vin_rsc_z[13] ; clk        ; -1.899 ; -2.414 ; Rise       ; clk             ;
+;  vin_rsc_z[14] ; clk        ; -1.831 ; -2.350 ; Rise       ; clk             ;
+;  vin_rsc_z[15] ; clk        ; -1.656 ; -2.137 ; Rise       ; clk             ;
+;  vin_rsc_z[16] ; clk        ; -1.479 ; -1.899 ; Rise       ; clk             ;
+;  vin_rsc_z[17] ; clk        ; -1.439 ; -1.855 ; Rise       ; clk             ;
+;  vin_rsc_z[18] ; clk        ; -1.570 ; -2.035 ; Rise       ; clk             ;
+;  vin_rsc_z[19] ; clk        ; -1.379 ; -1.834 ; Rise       ; clk             ;
+;  vin_rsc_z[20] ; clk        ; -1.601 ; -2.070 ; Rise       ; clk             ;
+;  vin_rsc_z[21] ; clk        ; -1.741 ; -2.183 ; Rise       ; clk             ;
+;  vin_rsc_z[22] ; clk        ; -1.494 ; -1.969 ; Rise       ; clk             ;
+;  vin_rsc_z[23] ; clk        ; -1.455 ; -1.891 ; Rise       ; clk             ;
+;  vin_rsc_z[24] ; clk        ; -1.686 ; -2.148 ; Rise       ; clk             ;
+;  vin_rsc_z[25] ; clk        ; -1.905 ; -2.410 ; Rise       ; clk             ;
+;  vin_rsc_z[26] ; clk        ; -1.741 ; -2.184 ; Rise       ; clk             ;
+;  vin_rsc_z[27] ; clk        ; -1.951 ; -2.477 ; Rise       ; clk             ;
+;  vin_rsc_z[28] ; clk        ; -1.792 ; -2.218 ; Rise       ; clk             ;
+;  vin_rsc_z[29] ; clk        ; -2.115 ; -2.568 ; Rise       ; clk             ;
+;  vin_rsc_z[30] ; clk        ; -1.641 ; -2.080 ; Rise       ; clk             ;
+;  vin_rsc_z[31] ; clk        ; -1.666 ; -2.138 ; Rise       ; clk             ;
+;  vin_rsc_z[32] ; clk        ; -1.847 ; -2.295 ; Rise       ; clk             ;
+;  vin_rsc_z[33] ; clk        ; -1.354 ; -1.820 ; Rise       ; clk             ;
+;  vin_rsc_z[34] ; clk        ; -1.368 ; -1.798 ; Rise       ; clk             ;
+;  vin_rsc_z[35] ; clk        ; -1.455 ; -1.937 ; Rise       ; clk             ;
+;  vin_rsc_z[36] ; clk        ; -1.178 ; -1.619 ; Rise       ; clk             ;
+;  vin_rsc_z[37] ; clk        ; -1.271 ; -1.723 ; Rise       ; clk             ;
+;  vin_rsc_z[38] ; clk        ; 0.732  ; 0.645  ; Rise       ; clk             ;
+;  vin_rsc_z[39] ; clk        ; -1.530 ; -2.002 ; Rise       ; clk             ;
+;  vin_rsc_z[40] ; clk        ; -1.609 ; -2.090 ; Rise       ; clk             ;
+;  vin_rsc_z[41] ; clk        ; -1.736 ; -2.190 ; Rise       ; clk             ;
+;  vin_rsc_z[42] ; clk        ; -1.678 ; -2.131 ; Rise       ; clk             ;
+;  vin_rsc_z[43] ; clk        ; -1.192 ; -1.646 ; Rise       ; clk             ;
+;  vin_rsc_z[44] ; clk        ; -1.063 ; -1.508 ; Rise       ; clk             ;
+;  vin_rsc_z[45] ; clk        ; -1.607 ; -2.069 ; Rise       ; clk             ;
+;  vin_rsc_z[46] ; clk        ; -1.309 ; -1.746 ; Rise       ; clk             ;
+;  vin_rsc_z[47] ; clk        ; -1.320 ; -1.772 ; Rise       ; clk             ;
+;  vin_rsc_z[48] ; clk        ; -1.408 ; -1.871 ; Rise       ; clk             ;
+;  vin_rsc_z[49] ; clk        ; -1.246 ; -1.690 ; Rise       ; clk             ;
+;  vin_rsc_z[50] ; clk        ; -1.413 ; -1.843 ; Rise       ; clk             ;
+;  vin_rsc_z[51] ; clk        ; -1.607 ; -2.088 ; Rise       ; clk             ;
+;  vin_rsc_z[52] ; clk        ; -2.082 ; -2.512 ; Rise       ; clk             ;
+;  vin_rsc_z[53] ; clk        ; -1.589 ; -2.055 ; Rise       ; clk             ;
+;  vin_rsc_z[54] ; clk        ; -1.603 ; -2.075 ; Rise       ; clk             ;
+;  vin_rsc_z[55] ; clk        ; -1.368 ; -1.777 ; Rise       ; clk             ;
+;  vin_rsc_z[56] ; clk        ; -1.437 ; -1.887 ; Rise       ; clk             ;
+;  vin_rsc_z[57] ; clk        ; 0.292  ; 0.148  ; Rise       ; clk             ;
+;  vin_rsc_z[58] ; clk        ; -1.459 ; -1.894 ; Rise       ; clk             ;
+;  vin_rsc_z[59] ; clk        ; -1.158 ; -1.586 ; Rise       ; clk             ;
+;  vin_rsc_z[60] ; clk        ; -1.632 ; -2.040 ; Rise       ; clk             ;
+;  vin_rsc_z[61] ; clk        ; -1.549 ; -1.991 ; Rise       ; clk             ;
+;  vin_rsc_z[62] ; clk        ; -1.675 ; -2.113 ; Rise       ; clk             ;
+;  vin_rsc_z[63] ; clk        ; -1.432 ; -1.851 ; Rise       ; clk             ;
+;  vin_rsc_z[64] ; clk        ; -1.445 ; -1.861 ; Rise       ; clk             ;
+;  vin_rsc_z[65] ; clk        ; -1.647 ; -2.130 ; Rise       ; clk             ;
+;  vin_rsc_z[66] ; clk        ; -1.701 ; -2.112 ; Rise       ; clk             ;
+;  vin_rsc_z[67] ; clk        ; -1.780 ; -2.213 ; Rise       ; clk             ;
+;  vin_rsc_z[68] ; clk        ; -1.671 ; -2.086 ; Rise       ; clk             ;
+;  vin_rsc_z[69] ; clk        ; -1.590 ; -2.044 ; Rise       ; clk             ;
+;  vin_rsc_z[70] ; clk        ; -1.242 ; -1.680 ; Rise       ; clk             ;
+;  vin_rsc_z[71] ; clk        ; -1.571 ; -1.983 ; Rise       ; clk             ;
+;  vin_rsc_z[72] ; clk        ; -1.292 ; -1.744 ; Rise       ; clk             ;
+;  vin_rsc_z[73] ; clk        ; -1.394 ; -1.864 ; Rise       ; clk             ;
+;  vin_rsc_z[74] ; clk        ; -1.873 ; -2.319 ; Rise       ; clk             ;
+;  vin_rsc_z[75] ; clk        ; -1.865 ; -2.368 ; Rise       ; clk             ;
+;  vin_rsc_z[76] ; clk        ; -1.366 ; -1.837 ; Rise       ; clk             ;
+;  vin_rsc_z[77] ; clk        ; -1.991 ; -2.451 ; Rise       ; clk             ;
+;  vin_rsc_z[78] ; clk        ; -1.331 ; -1.734 ; Rise       ; clk             ;
+;  vin_rsc_z[79] ; clk        ; -1.603 ; -2.070 ; Rise       ; clk             ;
+;  vin_rsc_z[80] ; clk        ; -1.781 ; -2.244 ; Rise       ; clk             ;
+;  vin_rsc_z[81] ; clk        ; -1.065 ; -1.483 ; Rise       ; clk             ;
+;  vin_rsc_z[82] ; clk        ; -1.118 ; -1.540 ; Rise       ; clk             ;
+;  vin_rsc_z[83] ; clk        ; -1.079 ; -1.492 ; Rise       ; clk             ;
+;  vin_rsc_z[84] ; clk        ; -1.300 ; -1.689 ; Rise       ; clk             ;
+;  vin_rsc_z[85] ; clk        ; -0.964 ; -1.422 ; Rise       ; clk             ;
+;  vin_rsc_z[86] ; clk        ; -1.580 ; -2.030 ; Rise       ; clk             ;
+;  vin_rsc_z[87] ; clk        ; -1.333 ; -1.789 ; Rise       ; clk             ;
+;  vin_rsc_z[88] ; clk        ; -1.323 ; -1.737 ; Rise       ; clk             ;
+;  vin_rsc_z[89] ; clk        ; -2.153 ; -2.648 ; Rise       ; clk             ;
++----------------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------------+
+; Clock to Output Times                                                       ;
++-----------------+------------+-------+-------+------------+-----------------+
+; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------------+------------+-------+-------+------------+-----------------+
+; vout_rsc_z[*]   ; clk        ; 7.528 ; 7.681 ; Rise       ; clk             ;
+;  vout_rsc_z[0]  ; clk        ; 5.667 ; 5.681 ; Rise       ; clk             ;
+;  vout_rsc_z[1]  ; clk        ; 5.561 ; 5.556 ; Rise       ; clk             ;
+;  vout_rsc_z[2]  ; clk        ; 5.396 ; 5.422 ; Rise       ; clk             ;
+;  vout_rsc_z[3]  ; clk        ; 5.815 ; 5.854 ; Rise       ; clk             ;
+;  vout_rsc_z[4]  ; clk        ; 5.837 ; 5.876 ; Rise       ; clk             ;
+;  vout_rsc_z[5]  ; clk        ; 6.150 ; 6.186 ; Rise       ; clk             ;
+;  vout_rsc_z[6]  ; clk        ; 6.104 ; 6.157 ; Rise       ; clk             ;
+;  vout_rsc_z[7]  ; clk        ; 5.760 ; 5.787 ; Rise       ; clk             ;
+;  vout_rsc_z[8]  ; clk        ; 6.020 ; 6.049 ; Rise       ; clk             ;
+;  vout_rsc_z[9]  ; clk        ; 6.134 ; 6.167 ; Rise       ; clk             ;
+;  vout_rsc_z[10] ; clk        ; 6.206 ; 6.228 ; Rise       ; clk             ;
+;  vout_rsc_z[11] ; clk        ; 6.223 ; 6.220 ; Rise       ; clk             ;
+;  vout_rsc_z[12] ; clk        ; 5.812 ; 5.836 ; Rise       ; clk             ;
+;  vout_rsc_z[13] ; clk        ; 5.700 ; 5.730 ; Rise       ; clk             ;
+;  vout_rsc_z[14] ; clk        ; 5.785 ; 5.806 ; Rise       ; clk             ;
+;  vout_rsc_z[15] ; clk        ; 6.135 ; 6.138 ; Rise       ; clk             ;
+;  vout_rsc_z[16] ; clk        ; 6.191 ; 6.227 ; Rise       ; clk             ;
+;  vout_rsc_z[17] ; clk        ; 7.528 ; 7.681 ; Rise       ; clk             ;
+;  vout_rsc_z[18] ; clk        ; 7.251 ; 7.392 ; Rise       ; clk             ;
+;  vout_rsc_z[19] ; clk        ; 6.041 ; 6.089 ; Rise       ; clk             ;
+;  vout_rsc_z[20] ; clk        ; 6.112 ; 6.143 ; Rise       ; clk             ;
+;  vout_rsc_z[21] ; clk        ; 6.044 ; 6.061 ; Rise       ; clk             ;
+;  vout_rsc_z[22] ; clk        ; 5.802 ; 5.836 ; Rise       ; clk             ;
+;  vout_rsc_z[23] ; clk        ; 5.651 ; 5.695 ; Rise       ; clk             ;
+;  vout_rsc_z[24] ; clk        ; 5.801 ; 5.834 ; Rise       ; clk             ;
+;  vout_rsc_z[25] ; clk        ; 6.134 ; 6.163 ; Rise       ; clk             ;
+;  vout_rsc_z[26] ; clk        ; 6.306 ; 6.370 ; Rise       ; clk             ;
+;  vout_rsc_z[27] ; clk        ; 6.238 ; 6.251 ; Rise       ; clk             ;
+;  vout_rsc_z[28] ; clk        ; 6.120 ; 6.149 ; Rise       ; clk             ;
+;  vout_rsc_z[29] ; clk        ; 6.456 ; 6.491 ; Rise       ; clk             ;
++-----------------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                               ;
++-----------------+------------+-------+-------+------------+-----------------+
+; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------------+------------+-------+-------+------------+-----------------+
+; vout_rsc_z[*]   ; clk        ; 5.291 ; 5.315 ; Rise       ; clk             ;
+;  vout_rsc_z[0]  ; clk        ; 5.551 ; 5.564 ; Rise       ; clk             ;
+;  vout_rsc_z[1]  ; clk        ; 5.445 ; 5.439 ; Rise       ; clk             ;
+;  vout_rsc_z[2]  ; clk        ; 5.291 ; 5.315 ; Rise       ; clk             ;
+;  vout_rsc_z[3]  ; clk        ; 5.692 ; 5.730 ; Rise       ; clk             ;
+;  vout_rsc_z[4]  ; clk        ; 5.715 ; 5.752 ; Rise       ; clk             ;
+;  vout_rsc_z[5]  ; clk        ; 6.014 ; 6.049 ; Rise       ; clk             ;
+;  vout_rsc_z[6]  ; clk        ; 5.972 ; 6.022 ; Rise       ; clk             ;
+;  vout_rsc_z[7]  ; clk        ; 5.640 ; 5.665 ; Rise       ; clk             ;
+;  vout_rsc_z[8]  ; clk        ; 5.889 ; 5.917 ; Rise       ; clk             ;
+;  vout_rsc_z[9]  ; clk        ; 5.998 ; 6.030 ; Rise       ; clk             ;
+;  vout_rsc_z[10] ; clk        ; 6.068 ; 6.089 ; Rise       ; clk             ;
+;  vout_rsc_z[11] ; clk        ; 6.080 ; 6.074 ; Rise       ; clk             ;
+;  vout_rsc_z[12] ; clk        ; 5.690 ; 5.713 ; Rise       ; clk             ;
+;  vout_rsc_z[13] ; clk        ; 5.583 ; 5.611 ; Rise       ; clk             ;
+;  vout_rsc_z[14] ; clk        ; 5.664 ; 5.683 ; Rise       ; clk             ;
+;  vout_rsc_z[15] ; clk        ; 6.000 ; 6.003 ; Rise       ; clk             ;
+;  vout_rsc_z[16] ; clk        ; 6.055 ; 6.089 ; Rise       ; clk             ;
+;  vout_rsc_z[17] ; clk        ; 7.385 ; 7.536 ; Rise       ; clk             ;
+;  vout_rsc_z[18] ; clk        ; 7.119 ; 7.259 ; Rise       ; clk             ;
+;  vout_rsc_z[19] ; clk        ; 5.910 ; 5.956 ; Rise       ; clk             ;
+;  vout_rsc_z[20] ; clk        ; 5.977 ; 6.007 ; Rise       ; clk             ;
+;  vout_rsc_z[21] ; clk        ; 5.913 ; 5.928 ; Rise       ; clk             ;
+;  vout_rsc_z[22] ; clk        ; 5.681 ; 5.712 ; Rise       ; clk             ;
+;  vout_rsc_z[23] ; clk        ; 5.536 ; 5.577 ; Rise       ; clk             ;
+;  vout_rsc_z[24] ; clk        ; 5.680 ; 5.711 ; Rise       ; clk             ;
+;  vout_rsc_z[25] ; clk        ; 5.999 ; 6.026 ; Rise       ; clk             ;
+;  vout_rsc_z[26] ; clk        ; 6.164 ; 6.225 ; Rise       ; clk             ;
+;  vout_rsc_z[27] ; clk        ; 6.100 ; 6.112 ; Rise       ; clk             ;
+;  vout_rsc_z[28] ; clk        ; 5.985 ; 6.012 ; Rise       ; clk             ;
+;  vout_rsc_z[29] ; clk        ; 6.309 ; 6.342 ; Rise       ; clk             ;
++-----------------+------------+-------+-------+------------+-----------------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary               ;
++-----------+-----------------+------------+------+
+; Fmax      ; Restricted Fmax ; Clock Name ; Note ;
++-----------+-----------------+------------+------+
+; 50.43 MHz ; 50.43 MHz       ; clk        ;      ;
++-----------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------+
+; Slow 1200mV 0C Model Setup Summary ;
++-------+---------+------------------+
+; Clock ; Slack   ; End Point TNS    ;
++-------+---------+------------------+
+; clk   ; -18.828 ; -1326.336        ;
++-------+---------+------------------+
+
+
++-----------------------------------+
+; Slow 1200mV 0C Model Hold Summary ;
++-------+-------+-------------------+
+; Clock ; Slack ; End Point TNS     ;
++-------+-------+-------------------+
+; clk   ; 0.466 ; 0.000             ;
++-------+-------+-------------------+
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
++-------+--------+---------------------------------+
+; Clock ; Slack  ; End Point TNS                   ;
++-------+--------+---------------------------------+
+; clk   ; -3.000 ; -287.000                        ;
++-------+--------+---------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'clk'                                                                                                                                                                        ;
++---------+---------------------------------------------------------------+----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                     ; To Node                                                  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------+----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -18.828 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.267      ; 20.090     ;
+; -18.810 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.267      ; 20.072     ;
+; -18.699 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.961     ;
+; -18.666 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.928     ;
+; -18.589 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.851     ;
+; -18.574 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.826     ;
+; -18.570 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.832     ;
+; -18.565 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.817     ;
+; -18.530 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.782     ;
+; -18.529 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.791     ;
+; -18.511 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.773     ;
+; -18.500 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.752     ;
+; -18.461 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.713     ;
+; -18.444 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.706     ;
+; -18.443 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.267      ; 19.705     ;
+; -18.443 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.705     ;
+; -18.426 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.688     ;
+; -18.425 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.267      ; 19.687     ;
+; -18.425 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.687     ;
+; -18.400 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.662     ;
+; -18.367 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.629     ;
+; -18.355 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.617     ;
+; -18.315 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.577     ;
+; -18.314 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.267      ; 19.576     ;
+; -18.314 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.576     ;
+; -18.296 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[8]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.558     ;
+; -18.290 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.552     ;
+; -18.282 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.544     ;
+; -18.281 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.267      ; 19.543     ;
+; -18.281 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.543     ;
+; -18.275 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.527     ;
+; -18.272 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.268      ; 19.535     ;
+; -18.271 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.533     ;
+; -18.269 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.268      ; 19.532     ;
+; -18.266 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.518     ;
+; -18.254 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.268      ; 19.517     ;
+; -18.251 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.513     ;
+; -18.251 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.268      ; 19.514     ;
+; -18.233 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.495     ;
+; -18.231 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.483     ;
+; -18.205 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.467     ;
+; -18.204 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.267      ; 19.466     ;
+; -18.204 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.466     ;
+; -18.201 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.453     ;
+; -18.190 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.442     ;
+; -18.189 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.257      ; 19.441     ;
+; -18.189 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.441     ;
+; -18.186 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.448     ;
+; -18.185 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.267      ; 19.447     ;
+; -18.185 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.447     ;
+; -18.181 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.433     ;
+; -18.180 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.257      ; 19.432     ;
+; -18.180 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.432     ;
+; -18.162 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.414     ;
+; -18.149 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]  ; clk          ; clk         ; 1.000        ; 0.268      ; 19.412     ;
+; -18.149 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26] ; clk          ; clk         ; 1.000        ; 0.268      ; 19.412     ;
+; -18.146 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.398     ;
+; -18.145 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.257      ; 19.397     ;
+; -18.145 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.397     ;
+; -18.143 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.268      ; 19.406     ;
+; -18.140 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.268      ; 19.403     ;
+; -18.131 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]  ; clk          ; clk         ; 1.000        ; 0.268      ; 19.394     ;
+; -18.131 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26] ; clk          ; clk         ; 1.000        ; 0.268      ; 19.394     ;
+; -18.122 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.384     ;
+; -18.116 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.368     ;
+; -18.115 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.257      ; 19.367     ;
+; -18.115 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.367     ;
+; -18.110 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.268      ; 19.373     ;
+; -18.107 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.268      ; 19.370     ;
+; -18.089 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.351     ;
+; -18.077 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.329     ;
+; -18.076 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.257      ; 19.328     ;
+; -18.076 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.328     ;
+; -18.075 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[10]             ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.337     ;
+; -18.072 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[17] ; clk          ; clk         ; 1.000        ; 0.268      ; 19.335     ;
+; -18.070 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[7]  ; clk          ; clk         ; 1.000        ; 0.268      ; 19.333     ;
+; -18.056 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.318     ;
+; -18.054 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[17] ; clk          ; clk         ; 1.000        ; 0.268      ; 19.317     ;
+; -18.052 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[7]  ; clk          ; clk         ; 1.000        ; 0.268      ; 19.315     ;
+; -18.033 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.268      ; 19.296     ;
+; -18.030 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.268      ; 19.293     ;
+; -18.020 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]  ; clk          ; clk         ; 1.000        ; 0.268      ; 19.283     ;
+; -18.020 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26] ; clk          ; clk         ; 1.000        ; 0.268      ; 19.283     ;
+; -18.018 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.258      ; 19.271     ;
+; -18.015 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.258      ; 19.268     ;
+; -18.014 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.268      ; 19.277     ;
+; -18.012 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.274     ;
+; -18.011 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.268      ; 19.274     ;
+; -18.009 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.258      ; 19.262     ;
+; -18.006 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.258      ; 19.259     ;
+; -17.997 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[8]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.259     ;
+; -17.997 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.249     ;
+; -17.993 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.255     ;
+; -17.988 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.257      ; 19.240     ;
+; -17.987 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]  ; clk          ; clk         ; 1.000        ; 0.268      ; 19.250     ;
+; -17.987 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26] ; clk          ; clk         ; 1.000        ; 0.268      ; 19.250     ;
+; -17.974 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.258      ; 19.227     ;
+; -17.971 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.267      ; 19.233     ;
+; -17.971 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.258      ; 19.224     ;
+; -17.970 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.267      ; 19.232     ;
++---------+---------------------------------------------------------------+----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'clk'                                                                                                                                                                      ;
++-------+--------------------------------------------------------+----------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                              ; To Node                                                        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------------------------------------+----------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.466 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[35] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[5]  ; clk          ; clk         ; 0.000        ; 0.055      ; 0.665      ;
+; 0.467 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[57] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[7]  ; clk          ; clk         ; 0.000        ; 0.054      ; 0.665      ;
+; 0.468 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[51] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[1]  ; clk          ; clk         ; 0.000        ; 0.054      ; 0.666      ;
+; 0.469 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[34] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[4]  ; clk          ; clk         ; 0.000        ; 0.054      ; 0.667      ;
+; 0.485 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[78] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[8] ; clk          ; clk         ; 0.000        ; 0.055      ; 0.684      ;
+; 0.494 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[61] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[1] ; clk          ; clk         ; 0.000        ; 0.056      ; 0.694      ;
+; 0.506 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[70] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[0] ; clk          ; clk         ; 0.000        ; 0.056      ; 0.706      ;
+; 0.510 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[63] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[3] ; clk          ; clk         ; 0.000        ; 0.056      ; 0.710      ;
+; 0.602 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[30] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[0]  ; clk          ; clk         ; 0.000        ; 0.054      ; 0.800      ;
+; 0.605 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[52] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[2]  ; clk          ; clk         ; 0.000        ; 0.054      ; 0.803      ;
+; 0.616 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[79] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[9] ; clk          ; clk         ; 0.000        ; 0.056      ; 0.816      ;
+; 0.617 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[64] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[4] ; clk          ; clk         ; 0.000        ; 0.056      ; 0.817      ;
+; 0.621 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[53] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[3]  ; clk          ; clk         ; 0.000        ; 0.054      ; 0.819      ;
+; 0.631 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[73] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[3] ; clk          ; clk         ; 0.000        ; 0.056      ; 0.831      ;
+; 0.646 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[75] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[5] ; clk          ; clk         ; 0.000        ; 0.056      ; 0.846      ;
+; 0.648 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[71] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[1] ; clk          ; clk         ; 0.000        ; 0.056      ; 0.848      ;
+; 0.649 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[60] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[0] ; clk          ; clk         ; 0.000        ; 0.056      ; 0.849      ;
+; 0.668 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[67] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[7] ; clk          ; clk         ; 0.000        ; -0.258     ; 0.554      ;
+; 0.668 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[31] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[1]  ; clk          ; clk         ; 0.000        ; 0.056      ; 0.868      ;
+; 0.674 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[16] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[6]  ; clk          ; clk         ; 0.000        ; 0.054      ; 0.872      ;
+; 0.674 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[42] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[2]  ; clk          ; clk         ; 0.000        ; 0.056      ; 0.874      ;
+; 0.675 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[33] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[3]  ; clk          ; clk         ; 0.000        ; 0.056      ; 0.875      ;
+; 0.678 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[13] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[3]  ; clk          ; clk         ; 0.000        ; 0.054      ; 0.876      ;
+; 0.679 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[2]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[2]  ; clk          ; clk         ; 0.000        ; 0.054      ; 0.877      ;
+; 0.689 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[62] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[2] ; clk          ; clk         ; 0.000        ; 0.056      ; 0.889      ;
+; 0.719 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[76] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[6] ; clk          ; clk         ; 0.000        ; 0.061      ; 0.924      ;
+; 0.735 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[59] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[9]  ; clk          ; clk         ; 0.000        ; 0.044      ; 0.923      ;
+; 0.778 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[39] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[9]  ; clk          ; clk         ; 0.000        ; 0.056      ; 0.978      ;
+; 0.795 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[48] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[8]  ; clk          ; clk         ; 0.000        ; 0.056      ; 0.995      ;
+; 0.803 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[10] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[0]  ; clk          ; clk         ; 0.000        ; 0.054      ; 1.001      ;
+; 0.803 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[43] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[3]  ; clk          ; clk         ; 0.000        ; 0.056      ; 1.003      ;
+; 0.803 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[47] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[7]  ; clk          ; clk         ; 0.000        ; 0.056      ; 1.003      ;
+; 0.804 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[11] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[1]  ; clk          ; clk         ; 0.000        ; 0.054      ; 1.002      ;
+; 0.805 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[12] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[2]  ; clk          ; clk         ; 0.000        ; 0.054      ; 1.003      ;
+; 0.809 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[14] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[4]  ; clk          ; clk         ; 0.000        ; 0.054      ; 1.007      ;
+; 0.809 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[37] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[7]  ; clk          ; clk         ; 0.000        ; 0.055      ; 1.008      ;
+; 0.810 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[4]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[4]  ; clk          ; clk         ; 0.000        ; 0.054      ; 1.008      ;
+; 0.811 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[40] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[0]  ; clk          ; clk         ; 0.000        ; 0.056      ; 1.011      ;
+; 0.813 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[68] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[8] ; clk          ; clk         ; 0.000        ; 0.056      ; 1.013      ;
+; 0.822 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[72] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[2] ; clk          ; clk         ; 0.000        ; 0.056      ; 1.022      ;
+; 0.822 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[0]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[0]  ; clk          ; clk         ; 0.000        ; 0.054      ; 1.020      ;
+; 0.826 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[18] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[8]  ; clk          ; clk         ; 0.000        ; 0.054      ; 1.024      ;
+; 0.832 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[41] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[1]  ; clk          ; clk         ; 0.000        ; 0.056      ; 1.032      ;
+; 0.840 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[56] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[6]  ; clk          ; clk         ; 0.000        ; 0.044      ; 1.028      ;
+; 0.841 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[32] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[2]  ; clk          ; clk         ; 0.000        ; 0.056      ; 1.041      ;
+; 0.844 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[6]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[6]  ; clk          ; clk         ; 0.000        ; 0.054      ; 1.042      ;
+; 0.860 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[66] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[6] ; clk          ; clk         ; 0.000        ; 0.058      ; 1.062      ;
+; 0.877 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[50] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[0]  ; clk          ; clk         ; 0.000        ; 0.044      ; 1.065      ;
+; 0.881 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[46] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[6]  ; clk          ; clk         ; 0.000        ; 0.056      ; 1.081      ;
+; 0.908 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[23] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[3]    ; clk          ; clk         ; 0.000        ; 0.078      ; 1.130      ;
+; 0.918 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[21] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[1]    ; clk          ; clk         ; 0.000        ; 0.078      ; 1.140      ;
+; 0.976 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[74] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[4] ; clk          ; clk         ; 0.000        ; 0.063      ; 1.183      ;
+; 1.000 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[77] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[7] ; clk          ; clk         ; 0.000        ; 0.056      ; 1.200      ;
+; 1.027 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[8]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[8]  ; clk          ; clk         ; 0.000        ; 0.053      ; 1.224      ;
+; 1.028 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[17] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[7]  ; clk          ; clk         ; 0.000        ; 0.054      ; 1.226      ;
+; 1.037 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[28] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[8]    ; clk          ; clk         ; 0.000        ; 0.078      ; 1.259      ;
+; 1.041 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[55] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[5]  ; clk          ; clk         ; 0.000        ; 0.044      ; 1.229      ;
+; 1.045 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[24] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[4]    ; clk          ; clk         ; 0.000        ; 0.078      ; 1.267      ;
+; 1.048 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[1]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[1]  ; clk          ; clk         ; 0.000        ; 0.053      ; 1.245      ;
+; 1.055 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[54] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[4]  ; clk          ; clk         ; 0.000        ; 0.044      ; 1.243      ;
+; 1.058 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[25] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[5]    ; clk          ; clk         ; 0.000        ; 0.078      ; 1.280      ;
+; 1.058 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[7]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[7]  ; clk          ; clk         ; 0.000        ; 0.053      ; 1.255      ;
+; 1.061 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[65] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[5] ; clk          ; clk         ; 0.000        ; 0.056      ; 1.261      ;
+; 1.102 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[84] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[4]  ; clk          ; clk         ; 0.000        ; -0.257     ; 0.989      ;
+; 1.120 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[86] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[6]  ; clk          ; clk         ; 0.000        ; -0.257     ; 1.007      ;
+; 1.122 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[80] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[0]  ; clk          ; clk         ; 0.000        ; -0.257     ; 1.009      ;
+; 1.146 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[3]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[3]  ; clk          ; clk         ; 0.000        ; 0.053      ; 1.343      ;
+; 1.148 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[88] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[8]  ; clk          ; clk         ; 0.000        ; -0.257     ; 1.035      ;
+; 1.154 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[5]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[5]  ; clk          ; clk         ; 0.000        ; 0.053      ; 1.351      ;
+; 1.165 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[83] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[3]  ; clk          ; clk         ; 0.000        ; -0.257     ; 1.052      ;
+; 1.255 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[22] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[2]    ; clk          ; clk         ; 0.000        ; 0.078      ; 1.477      ;
+; 1.261 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[27] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[7]    ; clk          ; clk         ; 0.000        ; 0.078      ; 1.483      ;
+; 1.269 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[26] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[6]    ; clk          ; clk         ; 0.000        ; 0.078      ; 1.491      ;
+; 1.274 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[20] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[0]    ; clk          ; clk         ; 0.000        ; 0.078      ; 1.496      ;
+; 1.278 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[29] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[9]    ; clk          ; clk         ; 0.000        ; 0.078      ; 1.500      ;
+; 1.280 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[85] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[5]  ; clk          ; clk         ; 0.000        ; -0.257     ; 1.167      ;
+; 1.313 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[36] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[6]  ; clk          ; clk         ; 0.000        ; 0.056      ; 1.513      ;
+; 1.335 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[38] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[8]  ; clk          ; clk         ; 0.000        ; -0.265     ; 1.214      ;
+; 1.339 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[44] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[4]  ; clk          ; clk         ; 0.000        ; -0.272     ; 1.211      ;
+; 1.364 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[45] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[5]  ; clk          ; clk         ; 0.000        ; 0.045      ; 1.553      ;
+; 1.418 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[58] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[8]  ; clk          ; clk         ; 0.000        ; 0.044      ; 1.606      ;
+; 1.424 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[49] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[9]  ; clk          ; clk         ; 0.000        ; 0.056      ; 1.624      ;
+; 1.468 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[9]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[9]  ; clk          ; clk         ; 0.000        ; 0.054      ; 1.666      ;
+; 1.479 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]        ; clk          ; clk         ; 0.000        ; 0.393      ; 2.016      ;
+; 1.479 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10]       ; clk          ; clk         ; 0.000        ; 0.393      ; 2.016      ;
+; 1.479 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11]       ; clk          ; clk         ; 0.000        ; 0.393      ; 2.016      ;
+; 1.479 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[16]       ; clk          ; clk         ; 0.000        ; 0.393      ; 2.016      ;
+; 1.479 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18]       ; clk          ; clk         ; 0.000        ; 0.393      ; 2.016      ;
+; 1.479 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20]       ; clk          ; clk         ; 0.000        ; 0.393      ; 2.016      ;
+; 1.479 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21]       ; clk          ; clk         ; 0.000        ; 0.393      ; 2.016      ;
+; 1.479 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[27]       ; clk          ; clk         ; 0.000        ; 0.393      ; 2.016      ;
+; 1.479 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[28]       ; clk          ; clk         ; 0.000        ; 0.393      ; 2.016      ;
+; 1.479 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[29]       ; clk          ; clk         ; 0.000        ; 0.393      ; 2.016      ;
+; 1.484 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[5]        ; clk          ; clk         ; 0.000        ; 0.393      ; 2.021      ;
+; 1.484 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]        ; clk          ; clk         ; 0.000        ; 0.393      ; 2.021      ;
+; 1.484 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[7]        ; clk          ; clk         ; 0.000        ; 0.393      ; 2.021      ;
+; 1.484 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]        ; clk          ; clk         ; 0.000        ; 0.393      ; 2.021      ;
+; 1.484 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[17]       ; clk          ; clk         ; 0.000        ; 0.393      ; 2.021      ;
+; 1.484 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19]       ; clk          ; clk         ; 0.000        ; 0.393      ; 2.021      ;
+; 1.484 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[25]       ; clk          ; clk         ; 0.000        ; 0.393      ; 2.021      ;
++-------+--------------------------------------------------------+----------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'clk'                                                                                          ;
++--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type       ; Clock ; Clock Edge ; Target                                                        ;
++--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; clk   ; Rise       ; clk                                                           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[11]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[11]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[12]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[11]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[12]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[11]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[12]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[13]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[0]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[1]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[2]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[3]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[4]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_2[0]               ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_2[1]               ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|main_stage_0_2                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[0]         ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[10]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[11]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[12]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[13]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[14]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[15]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[16]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[17]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[18]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[19]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[1]         ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[20]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[21]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[22]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[23]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[24]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[25]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[26]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[27]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[28]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[29]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[2]         ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[30]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[31]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[32]        ;
++--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------+
+; Setup Times                                                                  ;
++----------------+------------+--------+--------+------------+-----------------+
+; Data Port      ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++----------------+------------+--------+--------+------------+-----------------+
+; en             ; clk        ; 2.535  ; 2.531  ; Rise       ; clk             ;
+; vin_rsc_z[*]   ; clk        ; 22.014 ; 22.575 ; Rise       ; clk             ;
+;  vin_rsc_z[0]  ; clk        ; 21.092 ; 21.488 ; Rise       ; clk             ;
+;  vin_rsc_z[1]  ; clk        ; 20.880 ; 21.107 ; Rise       ; clk             ;
+;  vin_rsc_z[2]  ; clk        ; 20.824 ; 21.195 ; Rise       ; clk             ;
+;  vin_rsc_z[3]  ; clk        ; 20.832 ; 21.009 ; Rise       ; clk             ;
+;  vin_rsc_z[4]  ; clk        ; 20.684 ; 21.047 ; Rise       ; clk             ;
+;  vin_rsc_z[5]  ; clk        ; 21.042 ; 21.318 ; Rise       ; clk             ;
+;  vin_rsc_z[6]  ; clk        ; 20.201 ; 20.719 ; Rise       ; clk             ;
+;  vin_rsc_z[7]  ; clk        ; 20.474 ; 20.773 ; Rise       ; clk             ;
+;  vin_rsc_z[8]  ; clk        ; 20.268 ; 20.756 ; Rise       ; clk             ;
+;  vin_rsc_z[9]  ; clk        ; 20.119 ; 20.301 ; Rise       ; clk             ;
+;  vin_rsc_z[10] ; clk        ; 20.922 ; 21.388 ; Rise       ; clk             ;
+;  vin_rsc_z[11] ; clk        ; 20.935 ; 21.240 ; Rise       ; clk             ;
+;  vin_rsc_z[12] ; clk        ; 21.026 ; 21.539 ; Rise       ; clk             ;
+;  vin_rsc_z[13] ; clk        ; 21.034 ; 21.253 ; Rise       ; clk             ;
+;  vin_rsc_z[14] ; clk        ; 20.754 ; 21.321 ; Rise       ; clk             ;
+;  vin_rsc_z[15] ; clk        ; 20.837 ; 21.083 ; Rise       ; clk             ;
+;  vin_rsc_z[16] ; clk        ; 20.166 ; 20.558 ; Rise       ; clk             ;
+;  vin_rsc_z[17] ; clk        ; 20.192 ; 20.420 ; Rise       ; clk             ;
+;  vin_rsc_z[18] ; clk        ; 20.189 ; 20.621 ; Rise       ; clk             ;
+;  vin_rsc_z[19] ; clk        ; 20.319 ; 20.555 ; Rise       ; clk             ;
+;  vin_rsc_z[20] ; clk        ; 21.077 ; 21.567 ; Rise       ; clk             ;
+;  vin_rsc_z[21] ; clk        ; 21.221 ; 21.516 ; Rise       ; clk             ;
+;  vin_rsc_z[22] ; clk        ; 20.724 ; 21.230 ; Rise       ; clk             ;
+;  vin_rsc_z[23] ; clk        ; 21.050 ; 21.222 ; Rise       ; clk             ;
+;  vin_rsc_z[24] ; clk        ; 20.560 ; 21.090 ; Rise       ; clk             ;
+;  vin_rsc_z[25] ; clk        ; 20.767 ; 20.996 ; Rise       ; clk             ;
+;  vin_rsc_z[26] ; clk        ; 20.255 ; 20.614 ; Rise       ; clk             ;
+;  vin_rsc_z[27] ; clk        ; 20.151 ; 20.411 ; Rise       ; clk             ;
+;  vin_rsc_z[28] ; clk        ; 20.334 ; 20.759 ; Rise       ; clk             ;
+;  vin_rsc_z[29] ; clk        ; 20.184 ; 20.399 ; Rise       ; clk             ;
+;  vin_rsc_z[30] ; clk        ; 22.014 ; 22.575 ; Rise       ; clk             ;
+;  vin_rsc_z[31] ; clk        ; 21.774 ; 22.143 ; Rise       ; clk             ;
+;  vin_rsc_z[32] ; clk        ; 21.807 ; 22.386 ; Rise       ; clk             ;
+;  vin_rsc_z[33] ; clk        ; 21.113 ; 21.442 ; Rise       ; clk             ;
+;  vin_rsc_z[34] ; clk        ; 20.947 ; 21.392 ; Rise       ; clk             ;
+;  vin_rsc_z[35] ; clk        ; 20.699 ; 21.020 ; Rise       ; clk             ;
+;  vin_rsc_z[36] ; clk        ; 20.427 ; 20.902 ; Rise       ; clk             ;
+;  vin_rsc_z[37] ; clk        ; 20.415 ; 20.686 ; Rise       ; clk             ;
+;  vin_rsc_z[38] ; clk        ; 18.793 ; 19.101 ; Rise       ; clk             ;
+;  vin_rsc_z[39] ; clk        ; 20.297 ; 20.557 ; Rise       ; clk             ;
+;  vin_rsc_z[40] ; clk        ; 21.871 ; 22.443 ; Rise       ; clk             ;
+;  vin_rsc_z[41] ; clk        ; 21.834 ; 22.207 ; Rise       ; clk             ;
+;  vin_rsc_z[42] ; clk        ; 21.651 ; 22.187 ; Rise       ; clk             ;
+;  vin_rsc_z[43] ; clk        ; 21.078 ; 21.431 ; Rise       ; clk             ;
+;  vin_rsc_z[44] ; clk        ; 20.635 ; 21.118 ; Rise       ; clk             ;
+;  vin_rsc_z[45] ; clk        ; 20.854 ; 21.137 ; Rise       ; clk             ;
+;  vin_rsc_z[46] ; clk        ; 20.422 ; 20.892 ; Rise       ; clk             ;
+;  vin_rsc_z[47] ; clk        ; 20.428 ; 20.714 ; Rise       ; clk             ;
+;  vin_rsc_z[48] ; clk        ; 20.333 ; 20.911 ; Rise       ; clk             ;
+;  vin_rsc_z[49] ; clk        ; 20.153 ; 20.426 ; Rise       ; clk             ;
+;  vin_rsc_z[50] ; clk        ; 21.817 ; 22.366 ; Rise       ; clk             ;
+;  vin_rsc_z[51] ; clk        ; 21.851 ; 22.225 ; Rise       ; clk             ;
+;  vin_rsc_z[52] ; clk        ; 21.717 ; 22.285 ; Rise       ; clk             ;
+;  vin_rsc_z[53] ; clk        ; 21.481 ; 21.814 ; Rise       ; clk             ;
+;  vin_rsc_z[54] ; clk        ; 21.127 ; 21.693 ; Rise       ; clk             ;
+;  vin_rsc_z[55] ; clk        ; 21.070 ; 21.400 ; Rise       ; clk             ;
+;  vin_rsc_z[56] ; clk        ; 20.877 ; 21.418 ; Rise       ; clk             ;
+;  vin_rsc_z[57] ; clk        ; 19.370 ; 19.506 ; Rise       ; clk             ;
+;  vin_rsc_z[58] ; clk        ; 20.789 ; 21.324 ; Rise       ; clk             ;
+;  vin_rsc_z[59] ; clk        ; 20.325 ; 20.752 ; Rise       ; clk             ;
+;  vin_rsc_z[60] ; clk        ; 20.907 ; 21.131 ; Rise       ; clk             ;
+;  vin_rsc_z[61] ; clk        ; 20.781 ; 21.306 ; Rise       ; clk             ;
+;  vin_rsc_z[62] ; clk        ; 20.805 ; 21.101 ; Rise       ; clk             ;
+;  vin_rsc_z[63] ; clk        ; 20.518 ; 21.008 ; Rise       ; clk             ;
+;  vin_rsc_z[64] ; clk        ; 20.605 ; 20.945 ; Rise       ; clk             ;
+;  vin_rsc_z[65] ; clk        ; 20.760 ; 21.340 ; Rise       ; clk             ;
+;  vin_rsc_z[66] ; clk        ; 20.435 ; 20.729 ; Rise       ; clk             ;
+;  vin_rsc_z[67] ; clk        ; 20.380 ; 20.834 ; Rise       ; clk             ;
+;  vin_rsc_z[68] ; clk        ; 20.010 ; 20.413 ; Rise       ; clk             ;
+;  vin_rsc_z[69] ; clk        ; 20.182 ; 20.391 ; Rise       ; clk             ;
+;  vin_rsc_z[70] ; clk        ; 21.021 ; 21.276 ; Rise       ; clk             ;
+;  vin_rsc_z[71] ; clk        ; 20.677 ; 21.178 ; Rise       ; clk             ;
+;  vin_rsc_z[72] ; clk        ; 20.508 ; 20.880 ; Rise       ; clk             ;
+;  vin_rsc_z[73] ; clk        ; 20.706 ; 21.223 ; Rise       ; clk             ;
+;  vin_rsc_z[74] ; clk        ; 20.804 ; 21.181 ; Rise       ; clk             ;
+;  vin_rsc_z[75] ; clk        ; 20.783 ; 21.365 ; Rise       ; clk             ;
+;  vin_rsc_z[76] ; clk        ; 20.202 ; 20.560 ; Rise       ; clk             ;
+;  vin_rsc_z[77] ; clk        ; 20.264 ; 20.858 ; Rise       ; clk             ;
+;  vin_rsc_z[78] ; clk        ; 19.847 ; 20.219 ; Rise       ; clk             ;
+;  vin_rsc_z[79] ; clk        ; 20.044 ; 20.617 ; Rise       ; clk             ;
+;  vin_rsc_z[80] ; clk        ; 20.699 ; 21.116 ; Rise       ; clk             ;
+;  vin_rsc_z[81] ; clk        ; 20.393 ; 20.617 ; Rise       ; clk             ;
+;  vin_rsc_z[82] ; clk        ; 20.285 ; 20.698 ; Rise       ; clk             ;
+;  vin_rsc_z[83] ; clk        ; 20.349 ; 20.514 ; Rise       ; clk             ;
+;  vin_rsc_z[84] ; clk        ; 20.197 ; 20.547 ; Rise       ; clk             ;
+;  vin_rsc_z[85] ; clk        ; 20.147 ; 20.369 ; Rise       ; clk             ;
+;  vin_rsc_z[86] ; clk        ; 19.799 ; 20.231 ; Rise       ; clk             ;
+;  vin_rsc_z[87] ; clk        ; 20.095 ; 20.311 ; Rise       ; clk             ;
+;  vin_rsc_z[88] ; clk        ; 20.246 ; 20.607 ; Rise       ; clk             ;
+;  vin_rsc_z[89] ; clk        ; 19.963 ; 20.188 ; Rise       ; clk             ;
++----------------+------------+--------+--------+------------+-----------------+
+
+
++------------------------------------------------------------------------------+
+; Hold Times                                                                   ;
++----------------+------------+--------+--------+------------+-----------------+
+; Data Port      ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++----------------+------------+--------+--------+------------+-----------------+
+; en             ; clk        ; 0.214  ; 0.080  ; Rise       ; clk             ;
+; vin_rsc_z[*]   ; clk        ; 0.648  ; 0.524  ; Rise       ; clk             ;
+;  vin_rsc_z[0]  ; clk        ; -1.446 ; -1.870 ; Rise       ; clk             ;
+;  vin_rsc_z[1]  ; clk        ; -1.464 ; -1.889 ; Rise       ; clk             ;
+;  vin_rsc_z[2]  ; clk        ; -1.392 ; -1.736 ; Rise       ; clk             ;
+;  vin_rsc_z[3]  ; clk        ; -1.242 ; -1.597 ; Rise       ; clk             ;
+;  vin_rsc_z[4]  ; clk        ; -1.209 ; -1.553 ; Rise       ; clk             ;
+;  vin_rsc_z[5]  ; clk        ; -1.384 ; -1.819 ; Rise       ; clk             ;
+;  vin_rsc_z[6]  ; clk        ; -1.564 ; -2.011 ; Rise       ; clk             ;
+;  vin_rsc_z[7]  ; clk        ; -1.552 ; -1.962 ; Rise       ; clk             ;
+;  vin_rsc_z[8]  ; clk        ; -1.434 ; -1.823 ; Rise       ; clk             ;
+;  vin_rsc_z[9]  ; clk        ; -1.389 ; -1.714 ; Rise       ; clk             ;
+;  vin_rsc_z[10] ; clk        ; -1.163 ; -1.497 ; Rise       ; clk             ;
+;  vin_rsc_z[11] ; clk        ; -1.143 ; -1.495 ; Rise       ; clk             ;
+;  vin_rsc_z[12] ; clk        ; -1.500 ; -1.874 ; Rise       ; clk             ;
+;  vin_rsc_z[13] ; clk        ; -1.659 ; -2.058 ; Rise       ; clk             ;
+;  vin_rsc_z[14] ; clk        ; -1.577 ; -2.028 ; Rise       ; clk             ;
+;  vin_rsc_z[15] ; clk        ; -1.427 ; -1.822 ; Rise       ; clk             ;
+;  vin_rsc_z[16] ; clk        ; -1.259 ; -1.599 ; Rise       ; clk             ;
+;  vin_rsc_z[17] ; clk        ; -1.220 ; -1.562 ; Rise       ; clk             ;
+;  vin_rsc_z[18] ; clk        ; -1.336 ; -1.726 ; Rise       ; clk             ;
+;  vin_rsc_z[19] ; clk        ; -1.157 ; -1.539 ; Rise       ; clk             ;
+;  vin_rsc_z[20] ; clk        ; -1.372 ; -1.756 ; Rise       ; clk             ;
+;  vin_rsc_z[21] ; clk        ; -1.506 ; -1.868 ; Rise       ; clk             ;
+;  vin_rsc_z[22] ; clk        ; -1.273 ; -1.665 ; Rise       ; clk             ;
+;  vin_rsc_z[23] ; clk        ; -1.239 ; -1.606 ; Rise       ; clk             ;
+;  vin_rsc_z[24] ; clk        ; -1.449 ; -1.823 ; Rise       ; clk             ;
+;  vin_rsc_z[25] ; clk        ; -1.655 ; -2.053 ; Rise       ; clk             ;
+;  vin_rsc_z[26] ; clk        ; -1.496 ; -1.866 ; Rise       ; clk             ;
+;  vin_rsc_z[27] ; clk        ; -1.698 ; -2.115 ; Rise       ; clk             ;
+;  vin_rsc_z[28] ; clk        ; -1.544 ; -1.904 ; Rise       ; clk             ;
+;  vin_rsc_z[29] ; clk        ; -1.842 ; -2.190 ; Rise       ; clk             ;
+;  vin_rsc_z[30] ; clk        ; -1.408 ; -1.758 ; Rise       ; clk             ;
+;  vin_rsc_z[31] ; clk        ; -1.432 ; -1.818 ; Rise       ; clk             ;
+;  vin_rsc_z[32] ; clk        ; -1.588 ; -1.989 ; Rise       ; clk             ;
+;  vin_rsc_z[33] ; clk        ; -1.145 ; -1.528 ; Rise       ; clk             ;
+;  vin_rsc_z[34] ; clk        ; -1.158 ; -1.502 ; Rise       ; clk             ;
+;  vin_rsc_z[35] ; clk        ; -1.238 ; -1.655 ; Rise       ; clk             ;
+;  vin_rsc_z[36] ; clk        ; -0.982 ; -1.346 ; Rise       ; clk             ;
+;  vin_rsc_z[37] ; clk        ; -1.060 ; -1.437 ; Rise       ; clk             ;
+;  vin_rsc_z[38] ; clk        ; 0.648  ; 0.524  ; Rise       ; clk             ;
+;  vin_rsc_z[39] ; clk        ; -1.308 ; -1.691 ; Rise       ; clk             ;
+;  vin_rsc_z[40] ; clk        ; -1.372 ; -1.772 ; Rise       ; clk             ;
+;  vin_rsc_z[41] ; clk        ; -1.497 ; -1.880 ; Rise       ; clk             ;
+;  vin_rsc_z[42] ; clk        ; -1.443 ; -1.801 ; Rise       ; clk             ;
+;  vin_rsc_z[43] ; clk        ; -0.993 ; -1.365 ; Rise       ; clk             ;
+;  vin_rsc_z[44] ; clk        ; -0.885 ; -1.247 ; Rise       ; clk             ;
+;  vin_rsc_z[45] ; clk        ; -1.375 ; -1.755 ; Rise       ; clk             ;
+;  vin_rsc_z[46] ; clk        ; -1.091 ; -1.462 ; Rise       ; clk             ;
+;  vin_rsc_z[47] ; clk        ; -1.114 ; -1.484 ; Rise       ; clk             ;
+;  vin_rsc_z[48] ; clk        ; -1.191 ; -1.589 ; Rise       ; clk             ;
+;  vin_rsc_z[49] ; clk        ; -1.037 ; -1.418 ; Rise       ; clk             ;
+;  vin_rsc_z[50] ; clk        ; -1.193 ; -1.543 ; Rise       ; clk             ;
+;  vin_rsc_z[51] ; clk        ; -1.373 ; -1.760 ; Rise       ; clk             ;
+;  vin_rsc_z[52] ; clk        ; -1.814 ; -2.157 ; Rise       ; clk             ;
+;  vin_rsc_z[53] ; clk        ; -1.355 ; -1.756 ; Rise       ; clk             ;
+;  vin_rsc_z[54] ; clk        ; -1.362 ; -1.749 ; Rise       ; clk             ;
+;  vin_rsc_z[55] ; clk        ; -1.152 ; -1.487 ; Rise       ; clk             ;
+;  vin_rsc_z[56] ; clk        ; -1.224 ; -1.583 ; Rise       ; clk             ;
+;  vin_rsc_z[57] ; clk        ; 0.222  ; 0.065  ; Rise       ; clk             ;
+;  vin_rsc_z[58] ; clk        ; -1.235 ; -1.594 ; Rise       ; clk             ;
+;  vin_rsc_z[59] ; clk        ; -0.949 ; -1.323 ; Rise       ; clk             ;
+;  vin_rsc_z[60] ; clk        ; -1.390 ; -1.720 ; Rise       ; clk             ;
+;  vin_rsc_z[61] ; clk        ; -1.321 ; -1.677 ; Rise       ; clk             ;
+;  vin_rsc_z[62] ; clk        ; -1.433 ; -1.787 ; Rise       ; clk             ;
+;  vin_rsc_z[63] ; clk        ; -1.216 ; -1.554 ; Rise       ; clk             ;
+;  vin_rsc_z[64] ; clk        ; -1.227 ; -1.580 ; Rise       ; clk             ;
+;  vin_rsc_z[65] ; clk        ; -1.420 ; -1.799 ; Rise       ; clk             ;
+;  vin_rsc_z[66] ; clk        ; -1.455 ; -1.804 ; Rise       ; clk             ;
+;  vin_rsc_z[67] ; clk        ; -1.543 ; -1.872 ; Rise       ; clk             ;
+;  vin_rsc_z[68] ; clk        ; -1.434 ; -1.783 ; Rise       ; clk             ;
+;  vin_rsc_z[69] ; clk        ; -1.349 ; -1.719 ; Rise       ; clk             ;
+;  vin_rsc_z[70] ; clk        ; -1.033 ; -1.400 ; Rise       ; clk             ;
+;  vin_rsc_z[71] ; clk        ; -1.348 ; -1.659 ; Rise       ; clk             ;
+;  vin_rsc_z[72] ; clk        ; -1.080 ; -1.462 ; Rise       ; clk             ;
+;  vin_rsc_z[73] ; clk        ; -1.176 ; -1.574 ; Rise       ; clk             ;
+;  vin_rsc_z[74] ; clk        ; -1.622 ; -1.971 ; Rise       ; clk             ;
+;  vin_rsc_z[75] ; clk        ; -1.606 ; -2.008 ; Rise       ; clk             ;
+;  vin_rsc_z[76] ; clk        ; -1.149 ; -1.546 ; Rise       ; clk             ;
+;  vin_rsc_z[77] ; clk        ; -1.729 ; -2.098 ; Rise       ; clk             ;
+;  vin_rsc_z[78] ; clk        ; -1.120 ; -1.451 ; Rise       ; clk             ;
+;  vin_rsc_z[79] ; clk        ; -1.367 ; -1.745 ; Rise       ; clk             ;
+;  vin_rsc_z[80] ; clk        ; -1.538 ; -1.901 ; Rise       ; clk             ;
+;  vin_rsc_z[81] ; clk        ; -0.889 ; -1.232 ; Rise       ; clk             ;
+;  vin_rsc_z[82] ; clk        ; -0.930 ; -1.279 ; Rise       ; clk             ;
+;  vin_rsc_z[83] ; clk        ; -0.901 ; -1.235 ; Rise       ; clk             ;
+;  vin_rsc_z[84] ; clk        ; -1.099 ; -1.413 ; Rise       ; clk             ;
+;  vin_rsc_z[85] ; clk        ; -0.796 ; -1.176 ; Rise       ; clk             ;
+;  vin_rsc_z[86] ; clk        ; -1.354 ; -1.730 ; Rise       ; clk             ;
+;  vin_rsc_z[87] ; clk        ; -1.131 ; -1.502 ; Rise       ; clk             ;
+;  vin_rsc_z[88] ; clk        ; -1.125 ; -1.451 ; Rise       ; clk             ;
+;  vin_rsc_z[89] ; clk        ; -1.875 ; -2.253 ; Rise       ; clk             ;
++----------------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------------+
+; Clock to Output Times                                                       ;
++-----------------+------------+-------+-------+------------+-----------------+
+; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------------+------------+-------+-------+------------+-----------------+
+; vout_rsc_z[*]   ; clk        ; 7.193 ; 7.299 ; Rise       ; clk             ;
+;  vout_rsc_z[0]  ; clk        ; 5.393 ; 5.389 ; Rise       ; clk             ;
+;  vout_rsc_z[1]  ; clk        ; 5.289 ; 5.254 ; Rise       ; clk             ;
+;  vout_rsc_z[2]  ; clk        ; 5.149 ; 5.151 ; Rise       ; clk             ;
+;  vout_rsc_z[3]  ; clk        ; 5.538 ; 5.522 ; Rise       ; clk             ;
+;  vout_rsc_z[4]  ; clk        ; 5.563 ; 5.544 ; Rise       ; clk             ;
+;  vout_rsc_z[5]  ; clk        ; 5.841 ; 5.825 ; Rise       ; clk             ;
+;  vout_rsc_z[6]  ; clk        ; 5.796 ; 5.816 ; Rise       ; clk             ;
+;  vout_rsc_z[7]  ; clk        ; 5.478 ; 5.482 ; Rise       ; clk             ;
+;  vout_rsc_z[8]  ; clk        ; 5.713 ; 5.712 ; Rise       ; clk             ;
+;  vout_rsc_z[9]  ; clk        ; 5.822 ; 5.807 ; Rise       ; clk             ;
+;  vout_rsc_z[10] ; clk        ; 5.898 ; 5.866 ; Rise       ; clk             ;
+;  vout_rsc_z[11] ; clk        ; 5.890 ; 5.857 ; Rise       ; clk             ;
+;  vout_rsc_z[12] ; clk        ; 5.537 ; 5.513 ; Rise       ; clk             ;
+;  vout_rsc_z[13] ; clk        ; 5.425 ; 5.421 ; Rise       ; clk             ;
+;  vout_rsc_z[14] ; clk        ; 5.512 ; 5.492 ; Rise       ; clk             ;
+;  vout_rsc_z[15] ; clk        ; 5.836 ; 5.807 ; Rise       ; clk             ;
+;  vout_rsc_z[16] ; clk        ; 5.879 ; 5.862 ; Rise       ; clk             ;
+;  vout_rsc_z[17] ; clk        ; 7.193 ; 7.299 ; Rise       ; clk             ;
+;  vout_rsc_z[18] ; clk        ; 6.945 ; 7.054 ; Rise       ; clk             ;
+;  vout_rsc_z[19] ; clk        ; 5.733 ; 5.738 ; Rise       ; clk             ;
+;  vout_rsc_z[20] ; clk        ; 5.804 ; 5.792 ; Rise       ; clk             ;
+;  vout_rsc_z[21] ; clk        ; 5.735 ; 5.723 ; Rise       ; clk             ;
+;  vout_rsc_z[22] ; clk        ; 5.524 ; 5.502 ; Rise       ; clk             ;
+;  vout_rsc_z[23] ; clk        ; 5.384 ; 5.393 ; Rise       ; clk             ;
+;  vout_rsc_z[24] ; clk        ; 5.523 ; 5.512 ; Rise       ; clk             ;
+;  vout_rsc_z[25] ; clk        ; 5.821 ; 5.820 ; Rise       ; clk             ;
+;  vout_rsc_z[26] ; clk        ; 5.992 ; 5.992 ; Rise       ; clk             ;
+;  vout_rsc_z[27] ; clk        ; 5.930 ; 5.903 ; Rise       ; clk             ;
+;  vout_rsc_z[28] ; clk        ; 5.809 ; 5.797 ; Rise       ; clk             ;
+;  vout_rsc_z[29] ; clk        ; 6.133 ; 6.104 ; Rise       ; clk             ;
++-----------------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                               ;
++-----------------+------------+-------+-------+------------+-----------------+
+; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------------+------------+-------+-------+------------+-----------------+
+; vout_rsc_z[*]   ; clk        ; 5.055 ; 5.057 ; Rise       ; clk             ;
+;  vout_rsc_z[0]  ; clk        ; 5.290 ; 5.285 ; Rise       ; clk             ;
+;  vout_rsc_z[1]  ; clk        ; 5.186 ; 5.151 ; Rise       ; clk             ;
+;  vout_rsc_z[2]  ; clk        ; 5.055 ; 5.057 ; Rise       ; clk             ;
+;  vout_rsc_z[3]  ; clk        ; 5.429 ; 5.413 ; Rise       ; clk             ;
+;  vout_rsc_z[4]  ; clk        ; 5.453 ; 5.434 ; Rise       ; clk             ;
+;  vout_rsc_z[5]  ; clk        ; 5.720 ; 5.704 ; Rise       ; clk             ;
+;  vout_rsc_z[6]  ; clk        ; 5.678 ; 5.696 ; Rise       ; clk             ;
+;  vout_rsc_z[7]  ; clk        ; 5.372 ; 5.374 ; Rise       ; clk             ;
+;  vout_rsc_z[8]  ; clk        ; 5.596 ; 5.594 ; Rise       ; clk             ;
+;  vout_rsc_z[9]  ; clk        ; 5.701 ; 5.686 ; Rise       ; clk             ;
+;  vout_rsc_z[10] ; clk        ; 5.774 ; 5.743 ; Rise       ; clk             ;
+;  vout_rsc_z[11] ; clk        ; 5.761 ; 5.727 ; Rise       ; clk             ;
+;  vout_rsc_z[12] ; clk        ; 5.428 ; 5.404 ; Rise       ; clk             ;
+;  vout_rsc_z[13] ; clk        ; 5.320 ; 5.315 ; Rise       ; clk             ;
+;  vout_rsc_z[14] ; clk        ; 5.403 ; 5.384 ; Rise       ; clk             ;
+;  vout_rsc_z[15] ; clk        ; 5.714 ; 5.686 ; Rise       ; clk             ;
+;  vout_rsc_z[16] ; clk        ; 5.756 ; 5.740 ; Rise       ; clk             ;
+;  vout_rsc_z[17] ; clk        ; 7.065 ; 7.171 ; Rise       ; clk             ;
+;  vout_rsc_z[18] ; clk        ; 6.827 ; 6.935 ; Rise       ; clk             ;
+;  vout_rsc_z[19] ; clk        ; 5.616 ; 5.621 ; Rise       ; clk             ;
+;  vout_rsc_z[20] ; clk        ; 5.683 ; 5.671 ; Rise       ; clk             ;
+;  vout_rsc_z[21] ; clk        ; 5.618 ; 5.605 ; Rise       ; clk             ;
+;  vout_rsc_z[22] ; clk        ; 5.415 ; 5.394 ; Rise       ; clk             ;
+;  vout_rsc_z[23] ; clk        ; 5.281 ; 5.289 ; Rise       ; clk             ;
+;  vout_rsc_z[24] ; clk        ; 5.415 ; 5.404 ; Rise       ; clk             ;
+;  vout_rsc_z[25] ; clk        ; 5.700 ; 5.699 ; Rise       ; clk             ;
+;  vout_rsc_z[26] ; clk        ; 5.865 ; 5.865 ; Rise       ; clk             ;
+;  vout_rsc_z[27] ; clk        ; 5.805 ; 5.778 ; Rise       ; clk             ;
+;  vout_rsc_z[28] ; clk        ; 5.688 ; 5.676 ; Rise       ; clk             ;
+;  vout_rsc_z[29] ; clk        ; 6.000 ; 5.972 ; Rise       ; clk             ;
++-----------------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------+
+; Fast 1200mV 0C Model Setup Summary ;
++-------+---------+------------------+
+; Clock ; Slack   ; End Point TNS    ;
++-------+---------+------------------+
+; clk   ; -11.400 ; -781.716         ;
++-------+---------+------------------+
+
+
++-----------------------------------+
+; Fast 1200mV 0C Model Hold Summary ;
++-------+-------+-------------------+
+; Clock ; Slack ; End Point TNS     ;
++-------+-------+-------------------+
+; clk   ; 0.268 ; 0.000             ;
++-------+-------+-------------------+
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
++-------+--------+---------------------------------+
+; Clock ; Slack  ; End Point TNS                   ;
++-------+--------+---------------------------------+
+; clk   ; -3.000 ; -303.956                        ;
++-------+--------+---------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'clk'                                                                                                                                                                        ;
++---------+---------------------------------------------------------------+----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack   ; From Node                                                     ; To Node                                                  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++---------+---------------------------------------------------------------+----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -11.400 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.540     ;
+; -11.356 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.496     ;
+; -11.306 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.446     ;
+; -11.275 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.415     ;
+; -11.234 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.374     ;
+; -11.227 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.362     ;
+; -11.222 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.357     ;
+; -11.204 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.344     ;
+; -11.204 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.339     ;
+; -11.198 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.338     ;
+; -11.160 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.300     ;
+; -11.158 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.298     ;
+; -11.151 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.286     ;
+; -11.147 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.282     ;
+; -11.133 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.153      ; 12.273     ;
+; -11.133 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.273     ;
+; -11.114 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.254     ;
+; -11.110 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.250     ;
+; -11.093 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.233     ;
+; -11.089 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.153      ; 12.229     ;
+; -11.089 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.229     ;
+; -11.079 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.219     ;
+; -11.064 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.204     ;
+; -11.051 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.154      ; 12.192     ;
+; -11.050 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.154      ; 12.191     ;
+; -11.048 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[8]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.188     ;
+; -11.039 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.153      ; 12.179     ;
+; -11.039 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.179     ;
+; -11.038 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.178     ;
+; -11.033 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.173     ;
+; -11.031 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.171     ;
+; -11.031 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.166     ;
+; -11.026 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.161     ;
+; -11.008 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.153      ; 12.148     ;
+; -11.008 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.148     ;
+; -11.008 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.143     ;
+; -11.007 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.154      ; 12.148     ;
+; -11.006 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.154      ; 12.147     ;
+; -11.002 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.142     ;
+; -10.992 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.132     ;
+; -10.987 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.127     ;
+; -10.985 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.120     ;
+; -10.980 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.115     ;
+; -10.967 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.153      ; 12.107     ;
+; -10.967 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.107     ;
+; -10.965 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26] ; clk          ; clk         ; 1.000        ; 0.154      ; 12.106     ;
+; -10.964 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]  ; clk          ; clk         ; 1.000        ; 0.154      ; 12.105     ;
+; -10.962 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.097     ;
+; -10.960 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.148      ; 12.095     ;
+; -10.960 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.095     ;
+; -10.957 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.154      ; 12.098     ;
+; -10.956 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.096     ;
+; -10.956 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.154      ; 12.097     ;
+; -10.955 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.090     ;
+; -10.955 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.148      ; 12.090     ;
+; -10.955 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.090     ;
+; -10.951 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.086     ;
+; -10.937 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.077     ;
+; -10.937 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.148      ; 12.072     ;
+; -10.937 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.072     ;
+; -10.931 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.153      ; 12.071     ;
+; -10.931 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.071     ;
+; -10.926 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.154      ; 12.067     ;
+; -10.925 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.154      ; 12.066     ;
+; -10.921 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26] ; clk          ; clk         ; 1.000        ; 0.154      ; 12.062     ;
+; -10.920 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]  ; clk          ; clk         ; 1.000        ; 0.154      ; 12.061     ;
+; -10.909 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[17] ; clk          ; clk         ; 1.000        ; 0.154      ; 12.050     ;
+; -10.909 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.044     ;
+; -10.906 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.046     ;
+; -10.905 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[7]  ; clk          ; clk         ; 1.000        ; 0.154      ; 12.046     ;
+; -10.905 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.040     ;
+; -10.897 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.037     ;
+; -10.885 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.154      ; 12.026     ;
+; -10.884 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.148      ; 12.019     ;
+; -10.884 ; sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1          ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.019     ;
+; -10.884 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.154      ; 12.025     ;
+; -10.880 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]  ; clk          ; clk         ; 1.000        ; 0.148      ; 12.015     ;
+; -10.880 ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18] ; clk          ; clk         ; 1.000        ; 0.148      ; 12.015     ;
+; -10.878 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.149      ; 12.014     ;
+; -10.877 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.149      ; 12.013     ;
+; -10.873 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.149      ; 12.009     ;
+; -10.872 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.149      ; 12.008     ;
+; -10.871 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26] ; clk          ; clk         ; 1.000        ; 0.154      ; 12.012     ;
+; -10.870 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]  ; clk          ; clk         ; 1.000        ; 0.154      ; 12.011     ;
+; -10.865 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.153      ; 12.005     ;
+; -10.865 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[17] ; clk          ; clk         ; 1.000        ; 0.154      ; 12.006     ;
+; -10.861 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[7]  ; clk          ; clk         ; 1.000        ; 0.154      ; 12.002     ;
+; -10.858 ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.148      ; 11.993     ;
+; -10.855 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.149      ; 11.991     ;
+; -10.854 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.149      ; 11.990     ;
+; -10.853 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.148      ; 11.988     ;
+; -10.852 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[10]             ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21] ; clk          ; clk         ; 1.000        ; 0.153      ; 11.992     ;
+; -10.852 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[8]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20] ; clk          ; clk         ; 1.000        ; 0.153      ; 11.992     ;
+; -10.851 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11] ; clk          ; clk         ; 1.000        ; 0.153      ; 11.991     ;
+; -10.849 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[19] ; clk          ; clk         ; 1.000        ; 0.154      ; 11.990     ;
+; -10.848 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]  ; clk          ; clk         ; 1.000        ; 0.154      ; 11.989     ;
+; -10.840 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26] ; clk          ; clk         ; 1.000        ; 0.154      ; 11.981     ;
+; -10.839 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]  ; clk          ; clk         ; 1.000        ; 0.154      ; 11.980     ;
+; -10.835 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.148      ; 11.970     ;
+; -10.829 ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10] ; clk          ; clk         ; 1.000        ; 0.153      ; 11.969     ;
++---------+---------------------------------------------------------------+----------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'clk'                                                                                                                                                                      ;
++-------+--------------------------------------------------------+----------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                              ; To Node                                                        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+--------------------------------------------------------+----------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.268 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[57] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[7]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.387      ;
+; 0.269 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[35] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[5]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.388      ;
+; 0.270 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[51] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[1]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.389      ;
+; 0.271 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[34] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[4]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.390      ;
+; 0.275 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[61] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[1] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.396      ;
+; 0.281 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[70] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[0] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.402      ;
+; 0.281 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[63] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[3] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.402      ;
+; 0.282 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[78] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[8] ; clk          ; clk         ; 0.000        ; 0.035      ; 0.401      ;
+; 0.338 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[30] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[0]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.457      ;
+; 0.342 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[52] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[2]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.461      ;
+; 0.345 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[64] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[4] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.466      ;
+; 0.345 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[79] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[9] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.466      ;
+; 0.348 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[53] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[3]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.467      ;
+; 0.349 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[73] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[3] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.470      ;
+; 0.358 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[75] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[5] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.479      ;
+; 0.360 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[60] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[0] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.481      ;
+; 0.361 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[71] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[1] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.482      ;
+; 0.379 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[2]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[2]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.498      ;
+; 0.379 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[33] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[3]  ; clk          ; clk         ; 0.000        ; 0.036      ; 0.499      ;
+; 0.381 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[31] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[1]  ; clk          ; clk         ; 0.000        ; 0.036      ; 0.501      ;
+; 0.381 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[42] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[2]  ; clk          ; clk         ; 0.000        ; 0.036      ; 0.501      ;
+; 0.382 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[13] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[3]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.501      ;
+; 0.383 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[16] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[6]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.502      ;
+; 0.384 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[62] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[2] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.505      ;
+; 0.393 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[67] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[7] ; clk          ; clk         ; 0.000        ; -0.153     ; 0.324      ;
+; 0.407 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[76] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[6] ; clk          ; clk         ; 0.000        ; 0.042      ; 0.533      ;
+; 0.425 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[59] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[9]  ; clk          ; clk         ; 0.000        ; 0.031      ; 0.540      ;
+; 0.442 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[39] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[9]  ; clk          ; clk         ; 0.000        ; 0.036      ; 0.562      ;
+; 0.450 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[37] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[7]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.569      ;
+; 0.451 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[48] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[8]  ; clk          ; clk         ; 0.000        ; 0.036      ; 0.571      ;
+; 0.453 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[10] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[0]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.572      ;
+; 0.453 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[43] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[3]  ; clk          ; clk         ; 0.000        ; 0.036      ; 0.573      ;
+; 0.454 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[68] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[8] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.575      ;
+; 0.454 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[4]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[4]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.573      ;
+; 0.456 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[11] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[1]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.575      ;
+; 0.458 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[72] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[2] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.579      ;
+; 0.458 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[12] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[2]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.577      ;
+; 0.458 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[47] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[7]  ; clk          ; clk         ; 0.000        ; 0.036      ; 0.578      ;
+; 0.459 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[14] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[4]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.578      ;
+; 0.461 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[40] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[0]  ; clk          ; clk         ; 0.000        ; 0.036      ; 0.581      ;
+; 0.465 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[18] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[8]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.584      ;
+; 0.468 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[0]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[0]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.587      ;
+; 0.474 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[41] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[1]  ; clk          ; clk         ; 0.000        ; 0.036      ; 0.594      ;
+; 0.475 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[32] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[2]  ; clk          ; clk         ; 0.000        ; 0.036      ; 0.595      ;
+; 0.478 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[6]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[6]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.597      ;
+; 0.485 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[56] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[6]  ; clk          ; clk         ; 0.000        ; 0.031      ; 0.600      ;
+; 0.492 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[66] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[6] ; clk          ; clk         ; 0.000        ; 0.039      ; 0.615      ;
+; 0.500 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[50] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[0]  ; clk          ; clk         ; 0.000        ; 0.031      ; 0.615      ;
+; 0.502 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[46] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[6]  ; clk          ; clk         ; 0.000        ; 0.036      ; 0.622      ;
+; 0.527 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[23] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[3]    ; clk          ; clk         ; 0.000        ; 0.051      ; 0.662      ;
+; 0.532 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[21] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[1]    ; clk          ; clk         ; 0.000        ; 0.051      ; 0.667      ;
+; 0.561 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[74] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[4] ; clk          ; clk         ; 0.000        ; 0.044      ; 0.689      ;
+; 0.568 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[77] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[7] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.689      ;
+; 0.579 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[17] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[7]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.698      ;
+; 0.596 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[8]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[8]  ; clk          ; clk         ; 0.000        ; 0.034      ; 0.714      ;
+; 0.597 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[65] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[5] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.718      ;
+; 0.597 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[54] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[4]  ; clk          ; clk         ; 0.000        ; 0.031      ; 0.712      ;
+; 0.599 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[28] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[8]    ; clk          ; clk         ; 0.000        ; 0.051      ; 0.734      ;
+; 0.602 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[55] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[5]  ; clk          ; clk         ; 0.000        ; 0.031      ; 0.717      ;
+; 0.606 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[24] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[4]    ; clk          ; clk         ; 0.000        ; 0.051      ; 0.741      ;
+; 0.615 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[25] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[5]    ; clk          ; clk         ; 0.000        ; 0.051      ; 0.750      ;
+; 0.616 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[1]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[1]  ; clk          ; clk         ; 0.000        ; 0.034      ; 0.734      ;
+; 0.620 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[7]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[7]  ; clk          ; clk         ; 0.000        ; 0.034      ; 0.738      ;
+; 0.633 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[84] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[4]  ; clk          ; clk         ; 0.000        ; -0.152     ; 0.565      ;
+; 0.643 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[80] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[0]  ; clk          ; clk         ; 0.000        ; -0.152     ; 0.575      ;
+; 0.645 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[86] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[6]  ; clk          ; clk         ; 0.000        ; -0.152     ; 0.577      ;
+; 0.657 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[88] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[8]  ; clk          ; clk         ; 0.000        ; -0.152     ; 0.589      ;
+; 0.667 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[83] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[3]  ; clk          ; clk         ; 0.000        ; -0.152     ; 0.599      ;
+; 0.675 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[5]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[5]  ; clk          ; clk         ; 0.000        ; 0.034      ; 0.793      ;
+; 0.689 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[3]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[3]  ; clk          ; clk         ; 0.000        ; 0.034      ; 0.807      ;
+; 0.714 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[22] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[2]    ; clk          ; clk         ; 0.000        ; 0.051      ; 0.849      ;
+; 0.724 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[27] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[7]    ; clk          ; clk         ; 0.000        ; 0.051      ; 0.859      ;
+; 0.731 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[20] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[0]    ; clk          ; clk         ; 0.000        ; 0.051      ; 0.866      ;
+; 0.732 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[26] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[6]    ; clk          ; clk         ; 0.000        ; 0.051      ; 0.867      ;
+; 0.737 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[85] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[5]  ; clk          ; clk         ; 0.000        ; -0.152     ; 0.669      ;
+; 0.741 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[29] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[9]    ; clk          ; clk         ; 0.000        ; 0.051      ; 0.876      ;
+; 0.766 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[36] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[6]  ; clk          ; clk         ; 0.000        ; 0.036      ; 0.886      ;
+; 0.779 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[44] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[4]  ; clk          ; clk         ; 0.000        ; -0.158     ; 0.705      ;
+; 0.785 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[45] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[5]  ; clk          ; clk         ; 0.000        ; 0.031      ; 0.900      ;
+; 0.792 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[38] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[8]  ; clk          ; clk         ; 0.000        ; -0.155     ; 0.721      ;
+; 0.829 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[49] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[9]  ; clk          ; clk         ; 0.000        ; 0.036      ; 0.949      ;
+; 0.830 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[58] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[8]  ; clk          ; clk         ; 0.000        ; 0.031      ; 0.945      ;
+; 0.862 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[9]  ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[9]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.981      ;
+; 0.865 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[19] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[9]  ; clk          ; clk         ; 0.000        ; 0.035      ; 0.984      ;
+; 0.878 ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[69] ; sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[9] ; clk          ; clk         ; 0.000        ; 0.037      ; 0.999      ;
+; 0.881 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8]        ; clk          ; clk         ; 0.000        ; 0.236      ; 1.201      ;
+; 0.881 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[10]       ; clk          ; clk         ; 0.000        ; 0.236      ; 1.201      ;
+; 0.881 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[11]       ; clk          ; clk         ; 0.000        ; 0.236      ; 1.201      ;
+; 0.881 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[16]       ; clk          ; clk         ; 0.000        ; 0.236      ; 1.201      ;
+; 0.881 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[18]       ; clk          ; clk         ; 0.000        ; 0.236      ; 1.201      ;
+; 0.881 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[20]       ; clk          ; clk         ; 0.000        ; 0.236      ; 1.201      ;
+; 0.881 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[21]       ; clk          ; clk         ; 0.000        ; 0.236      ; 1.201      ;
+; 0.881 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[27]       ; clk          ; clk         ; 0.000        ; 0.236      ; 1.201      ;
+; 0.881 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[28]       ; clk          ; clk         ; 0.000        ; 0.236      ; 1.201      ;
+; 0.881 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[29]       ; clk          ; clk         ; 0.000        ; 0.236      ; 1.201      ;
+; 0.884 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[5]        ; clk          ; clk         ; 0.000        ; 0.236      ; 1.204      ;
+; 0.884 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6]        ; clk          ; clk         ; 0.000        ; 0.236      ; 1.204      ;
+; 0.884 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[7]        ; clk          ; clk         ; 0.000        ; 0.236      ; 1.204      ;
+; 0.884 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9]        ; clk          ; clk         ; 0.000        ; 0.236      ; 1.204      ;
+; 0.884 ; sobel_core:sobel_core_inst|main_stage_0_2              ; sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[17]       ; clk          ; clk         ; 0.000        ; 0.236      ; 1.204      ;
++-------+--------------------------------------------------------+----------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'clk'                                                                                          ;
++--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type       ; Clock ; Clock Edge ; Target                                                        ;
++--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate  ; clk   ; Rise       ; clk                                                           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[11]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[11]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[12]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[11]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[12]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[10]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[11]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[12]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[13]             ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[4]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[5]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[6]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[7]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[8]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[9]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[0]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[1]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[2]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[3]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[4]           ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_2[0]               ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_mul_57_itm_2[1]               ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|main_stage_0_2                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[0]         ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[10]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[11]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[12]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[13]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[14]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[15]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[16]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[17]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[18]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[19]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[1]         ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[20]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[21]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[22]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[23]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[24]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[25]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[26]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[27]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[28]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[29]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[2]         ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[30]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[31]        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period ; clk   ; Rise       ; sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[32]        ;
++--------+--------------+----------------+------------+-------+------------+---------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------+
+; Setup Times                                                                  ;
++----------------+------------+--------+--------+------------+-----------------+
+; Data Port      ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++----------------+------------+--------+--------+------------+-----------------+
+; en             ; clk        ; 1.475  ; 1.850  ; Rise       ; clk             ;
+; vin_rsc_z[*]   ; clk        ; 13.931 ; 14.683 ; Rise       ; clk             ;
+;  vin_rsc_z[0]  ; clk        ; 13.539 ; 14.210 ; Rise       ; clk             ;
+;  vin_rsc_z[1]  ; clk        ; 13.427 ; 13.960 ; Rise       ; clk             ;
+;  vin_rsc_z[2]  ; clk        ; 13.370 ; 14.011 ; Rise       ; clk             ;
+;  vin_rsc_z[3]  ; clk        ; 13.373 ; 13.867 ; Rise       ; clk             ;
+;  vin_rsc_z[4]  ; clk        ; 13.274 ; 13.898 ; Rise       ; clk             ;
+;  vin_rsc_z[5]  ; clk        ; 13.545 ; 14.124 ; Rise       ; clk             ;
+;  vin_rsc_z[6]  ; clk        ; 13.007 ; 13.759 ; Rise       ; clk             ;
+;  vin_rsc_z[7]  ; clk        ; 13.183 ; 13.798 ; Rise       ; clk             ;
+;  vin_rsc_z[8]  ; clk        ; 13.032 ; 13.763 ; Rise       ; clk             ;
+;  vin_rsc_z[9]  ; clk        ; 12.892 ; 13.389 ; Rise       ; clk             ;
+;  vin_rsc_z[10] ; clk        ; 13.443 ; 14.140 ; Rise       ; clk             ;
+;  vin_rsc_z[11] ; clk        ; 13.471 ; 14.038 ; Rise       ; clk             ;
+;  vin_rsc_z[12] ; clk        ; 13.539 ; 14.277 ; Rise       ; clk             ;
+;  vin_rsc_z[13] ; clk        ; 13.519 ; 14.064 ; Rise       ; clk             ;
+;  vin_rsc_z[14] ; clk        ; 13.359 ; 14.129 ; Rise       ; clk             ;
+;  vin_rsc_z[15] ; clk        ; 13.413 ; 13.983 ; Rise       ; clk             ;
+;  vin_rsc_z[16] ; clk        ; 12.938 ; 13.633 ; Rise       ; clk             ;
+;  vin_rsc_z[17] ; clk        ; 12.960 ; 13.531 ; Rise       ; clk             ;
+;  vin_rsc_z[18] ; clk        ; 12.953 ; 13.689 ; Rise       ; clk             ;
+;  vin_rsc_z[19] ; clk        ; 13.064 ; 13.613 ; Rise       ; clk             ;
+;  vin_rsc_z[20] ; clk        ; 13.550 ; 14.273 ; Rise       ; clk             ;
+;  vin_rsc_z[21] ; clk        ; 13.636 ; 14.233 ; Rise       ; clk             ;
+;  vin_rsc_z[22] ; clk        ; 13.327 ; 14.042 ; Rise       ; clk             ;
+;  vin_rsc_z[23] ; clk        ; 13.528 ; 14.035 ; Rise       ; clk             ;
+;  vin_rsc_z[24] ; clk        ; 13.220 ; 13.941 ; Rise       ; clk             ;
+;  vin_rsc_z[25] ; clk        ; 13.352 ; 13.895 ; Rise       ; clk             ;
+;  vin_rsc_z[26] ; clk        ; 12.976 ; 13.671 ; Rise       ; clk             ;
+;  vin_rsc_z[27] ; clk        ; 12.976 ; 13.555 ; Rise       ; clk             ;
+;  vin_rsc_z[28] ; clk        ; 13.037 ; 13.771 ; Rise       ; clk             ;
+;  vin_rsc_z[29] ; clk        ; 12.958 ; 13.481 ; Rise       ; clk             ;
+;  vin_rsc_z[30] ; clk        ; 13.931 ; 14.683 ; Rise       ; clk             ;
+;  vin_rsc_z[31] ; clk        ; 13.767 ; 14.415 ; Rise       ; clk             ;
+;  vin_rsc_z[32] ; clk        ; 13.793 ; 14.560 ; Rise       ; clk             ;
+;  vin_rsc_z[33] ; clk        ; 13.312 ; 13.948 ; Rise       ; clk             ;
+;  vin_rsc_z[34] ; clk        ; 13.235 ; 13.841 ; Rise       ; clk             ;
+;  vin_rsc_z[35] ; clk        ; 13.079 ; 13.647 ; Rise       ; clk             ;
+;  vin_rsc_z[36] ; clk        ; 12.893 ; 13.558 ; Rise       ; clk             ;
+;  vin_rsc_z[37] ; clk        ; 12.865 ; 13.396 ; Rise       ; clk             ;
+;  vin_rsc_z[38] ; clk        ; 11.825 ; 12.179 ; Rise       ; clk             ;
+;  vin_rsc_z[39] ; clk        ; 12.899 ; 13.419 ; Rise       ; clk             ;
+;  vin_rsc_z[40] ; clk        ; 13.832 ; 14.595 ; Rise       ; clk             ;
+;  vin_rsc_z[41] ; clk        ; 13.828 ; 14.437 ; Rise       ; clk             ;
+;  vin_rsc_z[42] ; clk        ; 13.708 ; 14.429 ; Rise       ; clk             ;
+;  vin_rsc_z[43] ; clk        ; 13.310 ; 13.934 ; Rise       ; clk             ;
+;  vin_rsc_z[44] ; clk        ; 13.070 ; 13.675 ; Rise       ; clk             ;
+;  vin_rsc_z[45] ; clk        ; 13.152 ; 13.717 ; Rise       ; clk             ;
+;  vin_rsc_z[46] ; clk        ; 12.884 ; 13.541 ; Rise       ; clk             ;
+;  vin_rsc_z[47] ; clk        ; 12.897 ; 13.424 ; Rise       ; clk             ;
+;  vin_rsc_z[48] ; clk        ; 12.847 ; 13.578 ; Rise       ; clk             ;
+;  vin_rsc_z[49] ; clk        ; 12.835 ; 13.355 ; Rise       ; clk             ;
+;  vin_rsc_z[50] ; clk        ; 13.824 ; 14.572 ; Rise       ; clk             ;
+;  vin_rsc_z[51] ; clk        ; 13.844 ; 14.449 ; Rise       ; clk             ;
+;  vin_rsc_z[52] ; clk        ; 13.741 ; 14.482 ; Rise       ; clk             ;
+;  vin_rsc_z[53] ; clk        ; 13.537 ; 14.202 ; Rise       ; clk             ;
+;  vin_rsc_z[54] ; clk        ; 13.357 ; 14.111 ; Rise       ; clk             ;
+;  vin_rsc_z[55] ; clk        ; 13.300 ; 13.893 ; Rise       ; clk             ;
+;  vin_rsc_z[56] ; clk        ; 13.185 ; 13.909 ; Rise       ; clk             ;
+;  vin_rsc_z[57] ; clk        ; 12.238 ; 12.497 ; Rise       ; clk             ;
+;  vin_rsc_z[58] ; clk        ; 13.137 ; 13.846 ; Rise       ; clk             ;
+;  vin_rsc_z[59] ; clk        ; 12.880 ; 13.481 ; Rise       ; clk             ;
+;  vin_rsc_z[60] ; clk        ; 13.436 ; 13.966 ; Rise       ; clk             ;
+;  vin_rsc_z[61] ; clk        ; 13.356 ; 14.039 ; Rise       ; clk             ;
+;  vin_rsc_z[62] ; clk        ; 13.369 ; 13.922 ; Rise       ; clk             ;
+;  vin_rsc_z[63] ; clk        ; 13.163 ; 13.842 ; Rise       ; clk             ;
+;  vin_rsc_z[64] ; clk        ; 13.230 ; 13.785 ; Rise       ; clk             ;
+;  vin_rsc_z[65] ; clk        ; 13.282 ; 14.072 ; Rise       ; clk             ;
+;  vin_rsc_z[66] ; clk        ; 12.994 ; 13.636 ; Rise       ; clk             ;
+;  vin_rsc_z[67] ; clk        ; 12.923 ; 13.557 ; Rise       ; clk             ;
+;  vin_rsc_z[68] ; clk        ; 12.704 ; 13.407 ; Rise       ; clk             ;
+;  vin_rsc_z[69] ; clk        ; 12.805 ; 13.347 ; Rise       ; clk             ;
+;  vin_rsc_z[70] ; clk        ; 13.517 ; 14.083 ; Rise       ; clk             ;
+;  vin_rsc_z[71] ; clk        ; 13.265 ; 13.940 ; Rise       ; clk             ;
+;  vin_rsc_z[72] ; clk        ; 13.196 ; 13.732 ; Rise       ; clk             ;
+;  vin_rsc_z[73] ; clk        ; 13.324 ; 14.016 ; Rise       ; clk             ;
+;  vin_rsc_z[74] ; clk        ; 13.347 ; 13.907 ; Rise       ; clk             ;
+;  vin_rsc_z[75] ; clk        ; 13.268 ; 14.073 ; Rise       ; clk             ;
+;  vin_rsc_z[76] ; clk        ; 12.895 ; 13.473 ; Rise       ; clk             ;
+;  vin_rsc_z[77] ; clk        ; 12.821 ; 13.593 ; Rise       ; clk             ;
+;  vin_rsc_z[78] ; clk        ; 12.584 ; 13.272 ; Rise       ; clk             ;
+;  vin_rsc_z[79] ; clk        ; 12.731 ; 13.484 ; Rise       ; clk             ;
+;  vin_rsc_z[80] ; clk        ; 13.138 ; 13.880 ; Rise       ; clk             ;
+;  vin_rsc_z[81] ; clk        ; 12.939 ; 13.529 ; Rise       ; clk             ;
+;  vin_rsc_z[82] ; clk        ; 12.875 ; 13.598 ; Rise       ; clk             ;
+;  vin_rsc_z[83] ; clk        ; 12.903 ; 13.403 ; Rise       ; clk             ;
+;  vin_rsc_z[84] ; clk        ; 12.801 ; 13.427 ; Rise       ; clk             ;
+;  vin_rsc_z[85] ; clk        ; 12.802 ; 13.313 ; Rise       ; clk             ;
+;  vin_rsc_z[86] ; clk        ; 12.589 ; 13.300 ; Rise       ; clk             ;
+;  vin_rsc_z[87] ; clk        ; 12.740 ; 13.320 ; Rise       ; clk             ;
+;  vin_rsc_z[88] ; clk        ; 12.831 ; 13.535 ; Rise       ; clk             ;
+;  vin_rsc_z[89] ; clk        ; 12.678 ; 13.217 ; Rise       ; clk             ;
++----------------+------------+--------+--------+------------+-----------------+
+
+
++------------------------------------------------------------------------------+
+; Hold Times                                                                   ;
++----------------+------------+--------+--------+------------+-----------------+
+; Data Port      ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++----------------+------------+--------+--------+------------+-----------------+
+; en             ; clk        ; 0.126  ; -0.161 ; Rise       ; clk             ;
+; vin_rsc_z[*]   ; clk        ; 0.378  ; 0.119  ; Rise       ; clk             ;
+;  vin_rsc_z[0]  ; clk        ; -0.952 ; -1.594 ; Rise       ; clk             ;
+;  vin_rsc_z[1]  ; clk        ; -0.969 ; -1.607 ; Rise       ; clk             ;
+;  vin_rsc_z[2]  ; clk        ; -0.887 ; -1.514 ; Rise       ; clk             ;
+;  vin_rsc_z[3]  ; clk        ; -0.790 ; -1.391 ; Rise       ; clk             ;
+;  vin_rsc_z[4]  ; clk        ; -0.767 ; -1.361 ; Rise       ; clk             ;
+;  vin_rsc_z[5]  ; clk        ; -0.941 ; -1.595 ; Rise       ; clk             ;
+;  vin_rsc_z[6]  ; clk        ; -1.028 ; -1.716 ; Rise       ; clk             ;
+;  vin_rsc_z[7]  ; clk        ; -1.012 ; -1.674 ; Rise       ; clk             ;
+;  vin_rsc_z[8]  ; clk        ; -0.947 ; -1.574 ; Rise       ; clk             ;
+;  vin_rsc_z[9]  ; clk        ; -0.853 ; -1.458 ; Rise       ; clk             ;
+;  vin_rsc_z[10] ; clk        ; -0.756 ; -1.357 ; Rise       ; clk             ;
+;  vin_rsc_z[11] ; clk        ; -0.750 ; -1.347 ; Rise       ; clk             ;
+;  vin_rsc_z[12] ; clk        ; -0.974 ; -1.628 ; Rise       ; clk             ;
+;  vin_rsc_z[13] ; clk        ; -1.063 ; -1.737 ; Rise       ; clk             ;
+;  vin_rsc_z[14] ; clk        ; -1.048 ; -1.718 ; Rise       ; clk             ;
+;  vin_rsc_z[15] ; clk        ; -0.930 ; -1.576 ; Rise       ; clk             ;
+;  vin_rsc_z[16] ; clk        ; -0.806 ; -1.401 ; Rise       ; clk             ;
+;  vin_rsc_z[17] ; clk        ; -0.772 ; -1.358 ; Rise       ; clk             ;
+;  vin_rsc_z[18] ; clk        ; -0.850 ; -1.490 ; Rise       ; clk             ;
+;  vin_rsc_z[19] ; clk        ; -0.761 ; -1.369 ; Rise       ; clk             ;
+;  vin_rsc_z[20] ; clk        ; -0.877 ; -1.496 ; Rise       ; clk             ;
+;  vin_rsc_z[21] ; clk        ; -0.943 ; -1.570 ; Rise       ; clk             ;
+;  vin_rsc_z[22] ; clk        ; -0.840 ; -1.467 ; Rise       ; clk             ;
+;  vin_rsc_z[23] ; clk        ; -0.809 ; -1.399 ; Rise       ; clk             ;
+;  vin_rsc_z[24] ; clk        ; -0.927 ; -1.554 ; Rise       ; clk             ;
+;  vin_rsc_z[25] ; clk        ; -1.058 ; -1.706 ; Rise       ; clk             ;
+;  vin_rsc_z[26] ; clk        ; -0.955 ; -1.567 ; Rise       ; clk             ;
+;  vin_rsc_z[27] ; clk        ; -1.123 ; -1.781 ; Rise       ; clk             ;
+;  vin_rsc_z[28] ; clk        ; -0.991 ; -1.622 ; Rise       ; clk             ;
+;  vin_rsc_z[29] ; clk        ; -1.140 ; -1.809 ; Rise       ; clk             ;
+;  vin_rsc_z[30] ; clk        ; -0.898 ; -1.498 ; Rise       ; clk             ;
+;  vin_rsc_z[31] ; clk        ; -0.916 ; -1.569 ; Rise       ; clk             ;
+;  vin_rsc_z[32] ; clk        ; -1.024 ; -1.662 ; Rise       ; clk             ;
+;  vin_rsc_z[33] ; clk        ; -0.748 ; -1.364 ; Rise       ; clk             ;
+;  vin_rsc_z[34] ; clk        ; -0.748 ; -1.351 ; Rise       ; clk             ;
+;  vin_rsc_z[35] ; clk        ; -0.820 ; -1.451 ; Rise       ; clk             ;
+;  vin_rsc_z[36] ; clk        ; -0.658 ; -1.259 ; Rise       ; clk             ;
+;  vin_rsc_z[37] ; clk        ; -0.679 ; -1.278 ; Rise       ; clk             ;
+;  vin_rsc_z[38] ; clk        ; 0.378  ; 0.119  ; Rise       ; clk             ;
+;  vin_rsc_z[39] ; clk        ; -0.836 ; -1.445 ; Rise       ; clk             ;
+;  vin_rsc_z[40] ; clk        ; -0.874 ; -1.515 ; Rise       ; clk             ;
+;  vin_rsc_z[41] ; clk        ; -0.976 ; -1.590 ; Rise       ; clk             ;
+;  vin_rsc_z[42] ; clk        ; -0.944 ; -1.540 ; Rise       ; clk             ;
+;  vin_rsc_z[43] ; clk        ; -0.677 ; -1.275 ; Rise       ; clk             ;
+;  vin_rsc_z[44] ; clk        ; -0.581 ; -1.219 ; Rise       ; clk             ;
+;  vin_rsc_z[45] ; clk        ; -0.901 ; -1.526 ; Rise       ; clk             ;
+;  vin_rsc_z[46] ; clk        ; -0.714 ; -1.299 ; Rise       ; clk             ;
+;  vin_rsc_z[47] ; clk        ; -0.728 ; -1.328 ; Rise       ; clk             ;
+;  vin_rsc_z[48] ; clk        ; -0.804 ; -1.411 ; Rise       ; clk             ;
+;  vin_rsc_z[49] ; clk        ; -0.702 ; -1.309 ; Rise       ; clk             ;
+;  vin_rsc_z[50] ; clk        ; -0.789 ; -1.406 ; Rise       ; clk             ;
+;  vin_rsc_z[51] ; clk        ; -0.888 ; -1.506 ; Rise       ; clk             ;
+;  vin_rsc_z[52] ; clk        ; -1.134 ; -1.775 ; Rise       ; clk             ;
+;  vin_rsc_z[53] ; clk        ; -0.884 ; -1.499 ; Rise       ; clk             ;
+;  vin_rsc_z[54] ; clk        ; -0.884 ; -1.508 ; Rise       ; clk             ;
+;  vin_rsc_z[55] ; clk        ; -0.737 ; -1.340 ; Rise       ; clk             ;
+;  vin_rsc_z[56] ; clk        ; -0.781 ; -1.380 ; Rise       ; clk             ;
+;  vin_rsc_z[57] ; clk        ; 0.140  ; -0.147 ; Rise       ; clk             ;
+;  vin_rsc_z[58] ; clk        ; -0.803 ; -1.387 ; Rise       ; clk             ;
+;  vin_rsc_z[59] ; clk        ; -0.627 ; -1.234 ; Rise       ; clk             ;
+;  vin_rsc_z[60] ; clk        ; -0.881 ; -1.494 ; Rise       ; clk             ;
+;  vin_rsc_z[61] ; clk        ; -0.857 ; -1.512 ; Rise       ; clk             ;
+;  vin_rsc_z[62] ; clk        ; -0.914 ; -1.556 ; Rise       ; clk             ;
+;  vin_rsc_z[63] ; clk        ; -0.775 ; -1.368 ; Rise       ; clk             ;
+;  vin_rsc_z[64] ; clk        ; -0.803 ; -1.386 ; Rise       ; clk             ;
+;  vin_rsc_z[65] ; clk        ; -0.934 ; -1.564 ; Rise       ; clk             ;
+;  vin_rsc_z[66] ; clk        ; -0.947 ; -1.590 ; Rise       ; clk             ;
+;  vin_rsc_z[67] ; clk        ; -0.954 ; -1.597 ; Rise       ; clk             ;
+;  vin_rsc_z[68] ; clk        ; -0.916 ; -1.515 ; Rise       ; clk             ;
+;  vin_rsc_z[69] ; clk        ; -0.861 ; -1.482 ; Rise       ; clk             ;
+;  vin_rsc_z[70] ; clk        ; -0.691 ; -1.304 ; Rise       ; clk             ;
+;  vin_rsc_z[71] ; clk        ; -0.865 ; -1.465 ; Rise       ; clk             ;
+;  vin_rsc_z[72] ; clk        ; -0.702 ; -1.297 ; Rise       ; clk             ;
+;  vin_rsc_z[73] ; clk        ; -0.776 ; -1.407 ; Rise       ; clk             ;
+;  vin_rsc_z[74] ; clk        ; -1.043 ; -1.677 ; Rise       ; clk             ;
+;  vin_rsc_z[75] ; clk        ; -1.036 ; -1.696 ; Rise       ; clk             ;
+;  vin_rsc_z[76] ; clk        ; -0.748 ; -1.371 ; Rise       ; clk             ;
+;  vin_rsc_z[77] ; clk        ; -1.106 ; -1.742 ; Rise       ; clk             ;
+;  vin_rsc_z[78] ; clk        ; -0.723 ; -1.319 ; Rise       ; clk             ;
+;  vin_rsc_z[79] ; clk        ; -0.874 ; -1.495 ; Rise       ; clk             ;
+;  vin_rsc_z[80] ; clk        ; -0.972 ; -1.636 ; Rise       ; clk             ;
+;  vin_rsc_z[81] ; clk        ; -0.575 ; -1.175 ; Rise       ; clk             ;
+;  vin_rsc_z[82] ; clk        ; -0.603 ; -1.204 ; Rise       ; clk             ;
+;  vin_rsc_z[83] ; clk        ; -0.585 ; -1.174 ; Rise       ; clk             ;
+;  vin_rsc_z[84] ; clk        ; -0.695 ; -1.295 ; Rise       ; clk             ;
+;  vin_rsc_z[85] ; clk        ; -0.531 ; -1.151 ; Rise       ; clk             ;
+;  vin_rsc_z[86] ; clk        ; -0.881 ; -1.541 ; Rise       ; clk             ;
+;  vin_rsc_z[87] ; clk        ; -0.709 ; -1.339 ; Rise       ; clk             ;
+;  vin_rsc_z[88] ; clk        ; -0.716 ; -1.318 ; Rise       ; clk             ;
+;  vin_rsc_z[89] ; clk        ; -1.184 ; -1.902 ; Rise       ; clk             ;
++----------------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------------+
+; Clock to Output Times                                                       ;
++-----------------+------------+-------+-------+------------+-----------------+
+; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------------+------------+-------+-------+------------+-----------------+
+; vout_rsc_z[*]   ; clk        ; 4.606 ; 4.827 ; Rise       ; clk             ;
+;  vout_rsc_z[0]  ; clk        ; 3.434 ; 3.473 ; Rise       ; clk             ;
+;  vout_rsc_z[1]  ; clk        ; 3.300 ; 3.384 ; Rise       ; clk             ;
+;  vout_rsc_z[2]  ; clk        ; 3.275 ; 3.305 ; Rise       ; clk             ;
+;  vout_rsc_z[3]  ; clk        ; 3.511 ; 3.562 ; Rise       ; clk             ;
+;  vout_rsc_z[4]  ; clk        ; 3.524 ; 3.585 ; Rise       ; clk             ;
+;  vout_rsc_z[5]  ; clk        ; 3.696 ; 3.749 ; Rise       ; clk             ;
+;  vout_rsc_z[6]  ; clk        ; 3.697 ; 3.747 ; Rise       ; clk             ;
+;  vout_rsc_z[7]  ; clk        ; 3.470 ; 3.500 ; Rise       ; clk             ;
+;  vout_rsc_z[8]  ; clk        ; 3.618 ; 3.668 ; Rise       ; clk             ;
+;  vout_rsc_z[9]  ; clk        ; 3.679 ; 3.732 ; Rise       ; clk             ;
+;  vout_rsc_z[10] ; clk        ; 3.713 ; 3.767 ; Rise       ; clk             ;
+;  vout_rsc_z[11] ; clk        ; 3.687 ; 3.764 ; Rise       ; clk             ;
+;  vout_rsc_z[12] ; clk        ; 3.492 ; 3.545 ; Rise       ; clk             ;
+;  vout_rsc_z[13] ; clk        ; 3.437 ; 3.497 ; Rise       ; clk             ;
+;  vout_rsc_z[14] ; clk        ; 3.504 ; 3.552 ; Rise       ; clk             ;
+;  vout_rsc_z[15] ; clk        ; 3.675 ; 3.758 ; Rise       ; clk             ;
+;  vout_rsc_z[16] ; clk        ; 3.720 ; 3.774 ; Rise       ; clk             ;
+;  vout_rsc_z[17] ; clk        ; 4.606 ; 4.827 ; Rise       ; clk             ;
+;  vout_rsc_z[18] ; clk        ; 4.449 ; 4.647 ; Rise       ; clk             ;
+;  vout_rsc_z[19] ; clk        ; 3.640 ; 3.686 ; Rise       ; clk             ;
+;  vout_rsc_z[20] ; clk        ; 3.676 ; 3.724 ; Rise       ; clk             ;
+;  vout_rsc_z[21] ; clk        ; 3.636 ; 3.676 ; Rise       ; clk             ;
+;  vout_rsc_z[22] ; clk        ; 3.511 ; 3.564 ; Rise       ; clk             ;
+;  vout_rsc_z[23] ; clk        ; 3.431 ; 3.478 ; Rise       ; clk             ;
+;  vout_rsc_z[24] ; clk        ; 3.518 ; 3.572 ; Rise       ; clk             ;
+;  vout_rsc_z[25] ; clk        ; 3.684 ; 3.733 ; Rise       ; clk             ;
+;  vout_rsc_z[26] ; clk        ; 3.765 ; 3.853 ; Rise       ; clk             ;
+;  vout_rsc_z[27] ; clk        ; 3.738 ; 3.796 ; Rise       ; clk             ;
+;  vout_rsc_z[28] ; clk        ; 3.679 ; 3.727 ; Rise       ; clk             ;
+;  vout_rsc_z[29] ; clk        ; 3.882 ; 3.954 ; Rise       ; clk             ;
++-----------------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                               ;
++-----------------+------------+-------+-------+------------+-----------------+
+; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------------+------------+-------+-------+------------+-----------------+
+; vout_rsc_z[*]   ; clk        ; 3.213 ; 3.241 ; Rise       ; clk             ;
+;  vout_rsc_z[0]  ; clk        ; 3.366 ; 3.404 ; Rise       ; clk             ;
+;  vout_rsc_z[1]  ; clk        ; 3.234 ; 3.315 ; Rise       ; clk             ;
+;  vout_rsc_z[2]  ; clk        ; 3.213 ; 3.241 ; Rise       ; clk             ;
+;  vout_rsc_z[3]  ; clk        ; 3.440 ; 3.488 ; Rise       ; clk             ;
+;  vout_rsc_z[4]  ; clk        ; 3.454 ; 3.512 ; Rise       ; clk             ;
+;  vout_rsc_z[5]  ; clk        ; 3.618 ; 3.668 ; Rise       ; clk             ;
+;  vout_rsc_z[6]  ; clk        ; 3.621 ; 3.668 ; Rise       ; clk             ;
+;  vout_rsc_z[7]  ; clk        ; 3.401 ; 3.429 ; Rise       ; clk             ;
+;  vout_rsc_z[8]  ; clk        ; 3.543 ; 3.590 ; Rise       ; clk             ;
+;  vout_rsc_z[9]  ; clk        ; 3.601 ; 3.652 ; Rise       ; clk             ;
+;  vout_rsc_z[10] ; clk        ; 3.634 ; 3.685 ; Rise       ; clk             ;
+;  vout_rsc_z[11] ; clk        ; 3.603 ; 3.678 ; Rise       ; clk             ;
+;  vout_rsc_z[12] ; clk        ; 3.422 ; 3.472 ; Rise       ; clk             ;
+;  vout_rsc_z[13] ; clk        ; 3.369 ; 3.425 ; Rise       ; clk             ;
+;  vout_rsc_z[14] ; clk        ; 3.433 ; 3.478 ; Rise       ; clk             ;
+;  vout_rsc_z[15] ; clk        ; 3.598 ; 3.677 ; Rise       ; clk             ;
+;  vout_rsc_z[16] ; clk        ; 3.641 ; 3.692 ; Rise       ; clk             ;
+;  vout_rsc_z[17] ; clk        ; 4.524 ; 4.742 ; Rise       ; clk             ;
+;  vout_rsc_z[18] ; clk        ; 4.373 ; 4.568 ; Rise       ; clk             ;
+;  vout_rsc_z[19] ; clk        ; 3.564 ; 3.608 ; Rise       ; clk             ;
+;  vout_rsc_z[20] ; clk        ; 3.597 ; 3.643 ; Rise       ; clk             ;
+;  vout_rsc_z[21] ; clk        ; 3.560 ; 3.598 ; Rise       ; clk             ;
+;  vout_rsc_z[22] ; clk        ; 3.439 ; 3.490 ; Rise       ; clk             ;
+;  vout_rsc_z[23] ; clk        ; 3.363 ; 3.407 ; Rise       ; clk             ;
+;  vout_rsc_z[24] ; clk        ; 3.447 ; 3.498 ; Rise       ; clk             ;
+;  vout_rsc_z[25] ; clk        ; 3.606 ; 3.653 ; Rise       ; clk             ;
+;  vout_rsc_z[26] ; clk        ; 3.684 ; 3.769 ; Rise       ; clk             ;
+;  vout_rsc_z[27] ; clk        ; 3.659 ; 3.713 ; Rise       ; clk             ;
+;  vout_rsc_z[28] ; clk        ; 3.601 ; 3.646 ; Rise       ; clk             ;
+;  vout_rsc_z[29] ; clk        ; 3.797 ; 3.865 ; Rise       ; clk             ;
++-----------------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++---------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                             ;
++------------------+-----------+-------+----------+---------+---------------------+
+; Clock            ; Setup     ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-----------+-------+----------+---------+---------------------+
+; Worst-case Slack ; -21.345   ; 0.268 ; N/A      ; N/A     ; -3.000              ;
+;  clk             ; -21.345   ; 0.268 ; N/A      ; N/A     ; -3.000              ;
+; Design-wide TNS  ; -1510.709 ; 0.0   ; 0.0      ; 0.0     ; -303.956            ;
+;  clk             ; -1510.709 ; 0.000 ; N/A      ; N/A     ; -303.956            ;
++------------------+-----------+-------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------+
+; Setup Times                                                                  ;
++----------------+------------+--------+--------+------------+-----------------+
+; Data Port      ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++----------------+------------+--------+--------+------------+-----------------+
+; en             ; clk        ; 2.702  ; 2.727  ; Rise       ; clk             ;
+; vin_rsc_z[*]   ; clk        ; 24.641 ; 25.299 ; Rise       ; clk             ;
+;  vin_rsc_z[0]  ; clk        ; 23.788 ; 24.281 ; Rise       ; clk             ;
+;  vin_rsc_z[1]  ; clk        ; 23.558 ; 23.820 ; Rise       ; clk             ;
+;  vin_rsc_z[2]  ; clk        ; 23.481 ; 23.940 ; Rise       ; clk             ;
+;  vin_rsc_z[3]  ; clk        ; 23.493 ; 23.716 ; Rise       ; clk             ;
+;  vin_rsc_z[4]  ; clk        ; 23.315 ; 23.765 ; Rise       ; clk             ;
+;  vin_rsc_z[5]  ; clk        ; 23.699 ; 24.042 ; Rise       ; clk             ;
+;  vin_rsc_z[6]  ; clk        ; 22.802 ; 23.457 ; Rise       ; clk             ;
+;  vin_rsc_z[7]  ; clk        ; 23.105 ; 23.515 ; Rise       ; clk             ;
+;  vin_rsc_z[8]  ; clk        ; 22.872 ; 23.500 ; Rise       ; clk             ;
+;  vin_rsc_z[9]  ; clk        ; 22.722 ; 22.949 ; Rise       ; clk             ;
+;  vin_rsc_z[10] ; clk        ; 23.605 ; 24.117 ; Rise       ; clk             ;
+;  vin_rsc_z[11] ; clk        ; 23.616 ; 23.947 ; Rise       ; clk             ;
+;  vin_rsc_z[12] ; clk        ; 23.709 ; 24.278 ; Rise       ; clk             ;
+;  vin_rsc_z[13] ; clk        ; 23.713 ; 24.006 ; Rise       ; clk             ;
+;  vin_rsc_z[14] ; clk        ; 23.397 ; 24.030 ; Rise       ; clk             ;
+;  vin_rsc_z[15] ; clk        ; 23.492 ; 23.808 ; Rise       ; clk             ;
+;  vin_rsc_z[16] ; clk        ; 22.771 ; 23.282 ; Rise       ; clk             ;
+;  vin_rsc_z[17] ; clk        ; 22.814 ; 23.108 ; Rise       ; clk             ;
+;  vin_rsc_z[18] ; clk        ; 22.797 ; 23.346 ; Rise       ; clk             ;
+;  vin_rsc_z[19] ; clk        ; 22.937 ; 23.255 ; Rise       ; clk             ;
+;  vin_rsc_z[20] ; clk        ; 23.768 ; 24.318 ; Rise       ; clk             ;
+;  vin_rsc_z[21] ; clk        ; 23.934 ; 24.231 ; Rise       ; clk             ;
+;  vin_rsc_z[22] ; clk        ; 23.370 ; 23.940 ; Rise       ; clk             ;
+;  vin_rsc_z[23] ; clk        ; 23.733 ; 23.983 ; Rise       ; clk             ;
+;  vin_rsc_z[24] ; clk        ; 23.179 ; 23.780 ; Rise       ; clk             ;
+;  vin_rsc_z[25] ; clk        ; 23.423 ; 23.711 ; Rise       ; clk             ;
+;  vin_rsc_z[26] ; clk        ; 22.868 ; 23.356 ; Rise       ; clk             ;
+;  vin_rsc_z[27] ; clk        ; 22.761 ; 23.085 ; Rise       ; clk             ;
+;  vin_rsc_z[28] ; clk        ; 22.935 ; 23.501 ; Rise       ; clk             ;
+;  vin_rsc_z[29] ; clk        ; 22.790 ; 23.076 ; Rise       ; clk             ;
+;  vin_rsc_z[30] ; clk        ; 24.641 ; 25.299 ; Rise       ; clk             ;
+;  vin_rsc_z[31] ; clk        ; 24.355 ; 24.800 ; Rise       ; clk             ;
+;  vin_rsc_z[32] ; clk        ; 24.384 ; 25.042 ; Rise       ; clk             ;
+;  vin_rsc_z[33] ; clk        ; 23.600 ; 24.015 ; Rise       ; clk             ;
+;  vin_rsc_z[34] ; clk        ; 23.423 ; 23.960 ; Rise       ; clk             ;
+;  vin_rsc_z[35] ; clk        ; 23.186 ; 23.565 ; Rise       ; clk             ;
+;  vin_rsc_z[36] ; clk        ; 22.876 ; 23.459 ; Rise       ; clk             ;
+;  vin_rsc_z[37] ; clk        ; 22.877 ; 23.219 ; Rise       ; clk             ;
+;  vin_rsc_z[38] ; clk        ; 20.964 ; 21.256 ; Rise       ; clk             ;
+;  vin_rsc_z[39] ; clk        ; 22.787 ; 23.071 ; Rise       ; clk             ;
+;  vin_rsc_z[40] ; clk        ; 24.489 ; 25.171 ; Rise       ; clk             ;
+;  vin_rsc_z[41] ; clk        ; 24.418 ; 24.854 ; Rise       ; clk             ;
+;  vin_rsc_z[42] ; clk        ; 24.207 ; 24.869 ; Rise       ; clk             ;
+;  vin_rsc_z[43] ; clk        ; 23.571 ; 24.005 ; Rise       ; clk             ;
+;  vin_rsc_z[44] ; clk        ; 23.087 ; 23.640 ; Rise       ; clk             ;
+;  vin_rsc_z[45] ; clk        ; 23.356 ; 23.713 ; Rise       ; clk             ;
+;  vin_rsc_z[46] ; clk        ; 22.881 ; 23.451 ; Rise       ; clk             ;
+;  vin_rsc_z[47] ; clk        ; 22.887 ; 23.239 ; Rise       ; clk             ;
+;  vin_rsc_z[48] ; clk        ; 22.779 ; 23.453 ; Rise       ; clk             ;
+;  vin_rsc_z[49] ; clk        ; 22.641 ; 22.912 ; Rise       ; clk             ;
+;  vin_rsc_z[50] ; clk        ; 24.425 ; 25.082 ; Rise       ; clk             ;
+;  vin_rsc_z[51] ; clk        ; 24.464 ; 24.902 ; Rise       ; clk             ;
+;  vin_rsc_z[52] ; clk        ; 24.313 ; 24.972 ; Rise       ; clk             ;
+;  vin_rsc_z[53] ; clk        ; 23.987 ; 24.442 ; Rise       ; clk             ;
+;  vin_rsc_z[54] ; clk        ; 23.694 ; 24.379 ; Rise       ; clk             ;
+;  vin_rsc_z[55] ; clk        ; 23.635 ; 24.030 ; Rise       ; clk             ;
+;  vin_rsc_z[56] ; clk        ; 23.402 ; 24.064 ; Rise       ; clk             ;
+;  vin_rsc_z[57] ; clk        ; 21.643 ; 21.716 ; Rise       ; clk             ;
+;  vin_rsc_z[58] ; clk        ; 23.306 ; 23.951 ; Rise       ; clk             ;
+;  vin_rsc_z[59] ; clk        ; 22.797 ; 23.282 ; Rise       ; clk             ;
+;  vin_rsc_z[60] ; clk        ; 23.536 ; 23.819 ; Rise       ; clk             ;
+;  vin_rsc_z[61] ; clk        ; 23.378 ; 24.000 ; Rise       ; clk             ;
+;  vin_rsc_z[62] ; clk        ; 23.417 ; 23.763 ; Rise       ; clk             ;
+;  vin_rsc_z[63] ; clk        ; 23.088 ; 23.662 ; Rise       ; clk             ;
+;  vin_rsc_z[64] ; clk        ; 23.188 ; 23.621 ; Rise       ; clk             ;
+;  vin_rsc_z[65] ; clk        ; 23.321 ; 24.040 ; Rise       ; clk             ;
+;  vin_rsc_z[66] ; clk        ; 22.965 ; 23.342 ; Rise       ; clk             ;
+;  vin_rsc_z[67] ; clk        ; 22.921 ; 23.422 ; Rise       ; clk             ;
+;  vin_rsc_z[68] ; clk        ; 22.506 ; 23.023 ; Rise       ; clk             ;
+;  vin_rsc_z[69] ; clk        ; 22.713 ; 22.984 ; Rise       ; clk             ;
+;  vin_rsc_z[70] ; clk        ; 23.664 ; 23.985 ; Rise       ; clk             ;
+;  vin_rsc_z[71] ; clk        ; 23.267 ; 23.855 ; Rise       ; clk             ;
+;  vin_rsc_z[72] ; clk        ; 23.096 ; 23.593 ; Rise       ; clk             ;
+;  vin_rsc_z[73] ; clk        ; 23.288 ; 23.911 ; Rise       ; clk             ;
+;  vin_rsc_z[74] ; clk        ; 23.400 ; 23.880 ; Rise       ; clk             ;
+;  vin_rsc_z[75] ; clk        ; 23.348 ; 24.069 ; Rise       ; clk             ;
+;  vin_rsc_z[76] ; clk        ; 22.709 ; 23.109 ; Rise       ; clk             ;
+;  vin_rsc_z[77] ; clk        ; 22.730 ; 23.450 ; Rise       ; clk             ;
+;  vin_rsc_z[78] ; clk        ; 22.319 ; 22.822 ; Rise       ; clk             ;
+;  vin_rsc_z[79] ; clk        ; 22.558 ; 23.208 ; Rise       ; clk             ;
+;  vin_rsc_z[80] ; clk        ; 23.295 ; 23.860 ; Rise       ; clk             ;
+;  vin_rsc_z[81] ; clk        ; 22.975 ; 23.281 ; Rise       ; clk             ;
+;  vin_rsc_z[82] ; clk        ; 22.833 ; 23.376 ; Rise       ; clk             ;
+;  vin_rsc_z[83] ; clk        ; 22.915 ; 23.127 ; Rise       ; clk             ;
+;  vin_rsc_z[84] ; clk        ; 22.730 ; 23.175 ; Rise       ; clk             ;
+;  vin_rsc_z[85] ; clk        ; 22.689 ; 22.971 ; Rise       ; clk             ;
+;  vin_rsc_z[86] ; clk        ; 22.297 ; 22.840 ; Rise       ; clk             ;
+;  vin_rsc_z[87] ; clk        ; 22.609 ; 22.924 ; Rise       ; clk             ;
+;  vin_rsc_z[88] ; clk        ; 22.763 ; 23.264 ; Rise       ; clk             ;
+;  vin_rsc_z[89] ; clk        ; 22.473 ; 22.760 ; Rise       ; clk             ;
++----------------+------------+--------+--------+------------+-----------------+
+
+
++------------------------------------------------------------------------------+
+; Hold Times                                                                   ;
++----------------+------------+--------+--------+------------+-----------------+
+; Data Port      ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++----------------+------------+--------+--------+------------+-----------------+
+; en             ; clk        ; 0.247  ; 0.169  ; Rise       ; clk             ;
+; vin_rsc_z[*]   ; clk        ; 0.732  ; 0.645  ; Rise       ; clk             ;
+;  vin_rsc_z[0]  ; clk        ; -0.952 ; -1.594 ; Rise       ; clk             ;
+;  vin_rsc_z[1]  ; clk        ; -0.969 ; -1.607 ; Rise       ; clk             ;
+;  vin_rsc_z[2]  ; clk        ; -0.887 ; -1.514 ; Rise       ; clk             ;
+;  vin_rsc_z[3]  ; clk        ; -0.790 ; -1.391 ; Rise       ; clk             ;
+;  vin_rsc_z[4]  ; clk        ; -0.767 ; -1.361 ; Rise       ; clk             ;
+;  vin_rsc_z[5]  ; clk        ; -0.941 ; -1.595 ; Rise       ; clk             ;
+;  vin_rsc_z[6]  ; clk        ; -1.028 ; -1.716 ; Rise       ; clk             ;
+;  vin_rsc_z[7]  ; clk        ; -1.012 ; -1.674 ; Rise       ; clk             ;
+;  vin_rsc_z[8]  ; clk        ; -0.947 ; -1.574 ; Rise       ; clk             ;
+;  vin_rsc_z[9]  ; clk        ; -0.853 ; -1.458 ; Rise       ; clk             ;
+;  vin_rsc_z[10] ; clk        ; -0.756 ; -1.357 ; Rise       ; clk             ;
+;  vin_rsc_z[11] ; clk        ; -0.750 ; -1.347 ; Rise       ; clk             ;
+;  vin_rsc_z[12] ; clk        ; -0.974 ; -1.628 ; Rise       ; clk             ;
+;  vin_rsc_z[13] ; clk        ; -1.063 ; -1.737 ; Rise       ; clk             ;
+;  vin_rsc_z[14] ; clk        ; -1.048 ; -1.718 ; Rise       ; clk             ;
+;  vin_rsc_z[15] ; clk        ; -0.930 ; -1.576 ; Rise       ; clk             ;
+;  vin_rsc_z[16] ; clk        ; -0.806 ; -1.401 ; Rise       ; clk             ;
+;  vin_rsc_z[17] ; clk        ; -0.772 ; -1.358 ; Rise       ; clk             ;
+;  vin_rsc_z[18] ; clk        ; -0.850 ; -1.490 ; Rise       ; clk             ;
+;  vin_rsc_z[19] ; clk        ; -0.761 ; -1.369 ; Rise       ; clk             ;
+;  vin_rsc_z[20] ; clk        ; -0.877 ; -1.496 ; Rise       ; clk             ;
+;  vin_rsc_z[21] ; clk        ; -0.943 ; -1.570 ; Rise       ; clk             ;
+;  vin_rsc_z[22] ; clk        ; -0.840 ; -1.467 ; Rise       ; clk             ;
+;  vin_rsc_z[23] ; clk        ; -0.809 ; -1.399 ; Rise       ; clk             ;
+;  vin_rsc_z[24] ; clk        ; -0.927 ; -1.554 ; Rise       ; clk             ;
+;  vin_rsc_z[25] ; clk        ; -1.058 ; -1.706 ; Rise       ; clk             ;
+;  vin_rsc_z[26] ; clk        ; -0.955 ; -1.567 ; Rise       ; clk             ;
+;  vin_rsc_z[27] ; clk        ; -1.123 ; -1.781 ; Rise       ; clk             ;
+;  vin_rsc_z[28] ; clk        ; -0.991 ; -1.622 ; Rise       ; clk             ;
+;  vin_rsc_z[29] ; clk        ; -1.140 ; -1.809 ; Rise       ; clk             ;
+;  vin_rsc_z[30] ; clk        ; -0.898 ; -1.498 ; Rise       ; clk             ;
+;  vin_rsc_z[31] ; clk        ; -0.916 ; -1.569 ; Rise       ; clk             ;
+;  vin_rsc_z[32] ; clk        ; -1.024 ; -1.662 ; Rise       ; clk             ;
+;  vin_rsc_z[33] ; clk        ; -0.748 ; -1.364 ; Rise       ; clk             ;
+;  vin_rsc_z[34] ; clk        ; -0.748 ; -1.351 ; Rise       ; clk             ;
+;  vin_rsc_z[35] ; clk        ; -0.820 ; -1.451 ; Rise       ; clk             ;
+;  vin_rsc_z[36] ; clk        ; -0.658 ; -1.259 ; Rise       ; clk             ;
+;  vin_rsc_z[37] ; clk        ; -0.679 ; -1.278 ; Rise       ; clk             ;
+;  vin_rsc_z[38] ; clk        ; 0.732  ; 0.645  ; Rise       ; clk             ;
+;  vin_rsc_z[39] ; clk        ; -0.836 ; -1.445 ; Rise       ; clk             ;
+;  vin_rsc_z[40] ; clk        ; -0.874 ; -1.515 ; Rise       ; clk             ;
+;  vin_rsc_z[41] ; clk        ; -0.976 ; -1.590 ; Rise       ; clk             ;
+;  vin_rsc_z[42] ; clk        ; -0.944 ; -1.540 ; Rise       ; clk             ;
+;  vin_rsc_z[43] ; clk        ; -0.677 ; -1.275 ; Rise       ; clk             ;
+;  vin_rsc_z[44] ; clk        ; -0.581 ; -1.219 ; Rise       ; clk             ;
+;  vin_rsc_z[45] ; clk        ; -0.901 ; -1.526 ; Rise       ; clk             ;
+;  vin_rsc_z[46] ; clk        ; -0.714 ; -1.299 ; Rise       ; clk             ;
+;  vin_rsc_z[47] ; clk        ; -0.728 ; -1.328 ; Rise       ; clk             ;
+;  vin_rsc_z[48] ; clk        ; -0.804 ; -1.411 ; Rise       ; clk             ;
+;  vin_rsc_z[49] ; clk        ; -0.702 ; -1.309 ; Rise       ; clk             ;
+;  vin_rsc_z[50] ; clk        ; -0.789 ; -1.406 ; Rise       ; clk             ;
+;  vin_rsc_z[51] ; clk        ; -0.888 ; -1.506 ; Rise       ; clk             ;
+;  vin_rsc_z[52] ; clk        ; -1.134 ; -1.775 ; Rise       ; clk             ;
+;  vin_rsc_z[53] ; clk        ; -0.884 ; -1.499 ; Rise       ; clk             ;
+;  vin_rsc_z[54] ; clk        ; -0.884 ; -1.508 ; Rise       ; clk             ;
+;  vin_rsc_z[55] ; clk        ; -0.737 ; -1.340 ; Rise       ; clk             ;
+;  vin_rsc_z[56] ; clk        ; -0.781 ; -1.380 ; Rise       ; clk             ;
+;  vin_rsc_z[57] ; clk        ; 0.292  ; 0.148  ; Rise       ; clk             ;
+;  vin_rsc_z[58] ; clk        ; -0.803 ; -1.387 ; Rise       ; clk             ;
+;  vin_rsc_z[59] ; clk        ; -0.627 ; -1.234 ; Rise       ; clk             ;
+;  vin_rsc_z[60] ; clk        ; -0.881 ; -1.494 ; Rise       ; clk             ;
+;  vin_rsc_z[61] ; clk        ; -0.857 ; -1.512 ; Rise       ; clk             ;
+;  vin_rsc_z[62] ; clk        ; -0.914 ; -1.556 ; Rise       ; clk             ;
+;  vin_rsc_z[63] ; clk        ; -0.775 ; -1.368 ; Rise       ; clk             ;
+;  vin_rsc_z[64] ; clk        ; -0.803 ; -1.386 ; Rise       ; clk             ;
+;  vin_rsc_z[65] ; clk        ; -0.934 ; -1.564 ; Rise       ; clk             ;
+;  vin_rsc_z[66] ; clk        ; -0.947 ; -1.590 ; Rise       ; clk             ;
+;  vin_rsc_z[67] ; clk        ; -0.954 ; -1.597 ; Rise       ; clk             ;
+;  vin_rsc_z[68] ; clk        ; -0.916 ; -1.515 ; Rise       ; clk             ;
+;  vin_rsc_z[69] ; clk        ; -0.861 ; -1.482 ; Rise       ; clk             ;
+;  vin_rsc_z[70] ; clk        ; -0.691 ; -1.304 ; Rise       ; clk             ;
+;  vin_rsc_z[71] ; clk        ; -0.865 ; -1.465 ; Rise       ; clk             ;
+;  vin_rsc_z[72] ; clk        ; -0.702 ; -1.297 ; Rise       ; clk             ;
+;  vin_rsc_z[73] ; clk        ; -0.776 ; -1.407 ; Rise       ; clk             ;
+;  vin_rsc_z[74] ; clk        ; -1.043 ; -1.677 ; Rise       ; clk             ;
+;  vin_rsc_z[75] ; clk        ; -1.036 ; -1.696 ; Rise       ; clk             ;
+;  vin_rsc_z[76] ; clk        ; -0.748 ; -1.371 ; Rise       ; clk             ;
+;  vin_rsc_z[77] ; clk        ; -1.106 ; -1.742 ; Rise       ; clk             ;
+;  vin_rsc_z[78] ; clk        ; -0.723 ; -1.319 ; Rise       ; clk             ;
+;  vin_rsc_z[79] ; clk        ; -0.874 ; -1.495 ; Rise       ; clk             ;
+;  vin_rsc_z[80] ; clk        ; -0.972 ; -1.636 ; Rise       ; clk             ;
+;  vin_rsc_z[81] ; clk        ; -0.575 ; -1.175 ; Rise       ; clk             ;
+;  vin_rsc_z[82] ; clk        ; -0.603 ; -1.204 ; Rise       ; clk             ;
+;  vin_rsc_z[83] ; clk        ; -0.585 ; -1.174 ; Rise       ; clk             ;
+;  vin_rsc_z[84] ; clk        ; -0.695 ; -1.295 ; Rise       ; clk             ;
+;  vin_rsc_z[85] ; clk        ; -0.531 ; -1.151 ; Rise       ; clk             ;
+;  vin_rsc_z[86] ; clk        ; -0.881 ; -1.541 ; Rise       ; clk             ;
+;  vin_rsc_z[87] ; clk        ; -0.709 ; -1.339 ; Rise       ; clk             ;
+;  vin_rsc_z[88] ; clk        ; -0.716 ; -1.318 ; Rise       ; clk             ;
+;  vin_rsc_z[89] ; clk        ; -1.184 ; -1.902 ; Rise       ; clk             ;
++----------------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------------+
+; Clock to Output Times                                                       ;
++-----------------+------------+-------+-------+------------+-----------------+
+; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------------+------------+-------+-------+------------+-----------------+
+; vout_rsc_z[*]   ; clk        ; 7.528 ; 7.681 ; Rise       ; clk             ;
+;  vout_rsc_z[0]  ; clk        ; 5.667 ; 5.681 ; Rise       ; clk             ;
+;  vout_rsc_z[1]  ; clk        ; 5.561 ; 5.556 ; Rise       ; clk             ;
+;  vout_rsc_z[2]  ; clk        ; 5.396 ; 5.422 ; Rise       ; clk             ;
+;  vout_rsc_z[3]  ; clk        ; 5.815 ; 5.854 ; Rise       ; clk             ;
+;  vout_rsc_z[4]  ; clk        ; 5.837 ; 5.876 ; Rise       ; clk             ;
+;  vout_rsc_z[5]  ; clk        ; 6.150 ; 6.186 ; Rise       ; clk             ;
+;  vout_rsc_z[6]  ; clk        ; 6.104 ; 6.157 ; Rise       ; clk             ;
+;  vout_rsc_z[7]  ; clk        ; 5.760 ; 5.787 ; Rise       ; clk             ;
+;  vout_rsc_z[8]  ; clk        ; 6.020 ; 6.049 ; Rise       ; clk             ;
+;  vout_rsc_z[9]  ; clk        ; 6.134 ; 6.167 ; Rise       ; clk             ;
+;  vout_rsc_z[10] ; clk        ; 6.206 ; 6.228 ; Rise       ; clk             ;
+;  vout_rsc_z[11] ; clk        ; 6.223 ; 6.220 ; Rise       ; clk             ;
+;  vout_rsc_z[12] ; clk        ; 5.812 ; 5.836 ; Rise       ; clk             ;
+;  vout_rsc_z[13] ; clk        ; 5.700 ; 5.730 ; Rise       ; clk             ;
+;  vout_rsc_z[14] ; clk        ; 5.785 ; 5.806 ; Rise       ; clk             ;
+;  vout_rsc_z[15] ; clk        ; 6.135 ; 6.138 ; Rise       ; clk             ;
+;  vout_rsc_z[16] ; clk        ; 6.191 ; 6.227 ; Rise       ; clk             ;
+;  vout_rsc_z[17] ; clk        ; 7.528 ; 7.681 ; Rise       ; clk             ;
+;  vout_rsc_z[18] ; clk        ; 7.251 ; 7.392 ; Rise       ; clk             ;
+;  vout_rsc_z[19] ; clk        ; 6.041 ; 6.089 ; Rise       ; clk             ;
+;  vout_rsc_z[20] ; clk        ; 6.112 ; 6.143 ; Rise       ; clk             ;
+;  vout_rsc_z[21] ; clk        ; 6.044 ; 6.061 ; Rise       ; clk             ;
+;  vout_rsc_z[22] ; clk        ; 5.802 ; 5.836 ; Rise       ; clk             ;
+;  vout_rsc_z[23] ; clk        ; 5.651 ; 5.695 ; Rise       ; clk             ;
+;  vout_rsc_z[24] ; clk        ; 5.801 ; 5.834 ; Rise       ; clk             ;
+;  vout_rsc_z[25] ; clk        ; 6.134 ; 6.163 ; Rise       ; clk             ;
+;  vout_rsc_z[26] ; clk        ; 6.306 ; 6.370 ; Rise       ; clk             ;
+;  vout_rsc_z[27] ; clk        ; 6.238 ; 6.251 ; Rise       ; clk             ;
+;  vout_rsc_z[28] ; clk        ; 6.120 ; 6.149 ; Rise       ; clk             ;
+;  vout_rsc_z[29] ; clk        ; 6.456 ; 6.491 ; Rise       ; clk             ;
++-----------------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                               ;
++-----------------+------------+-------+-------+------------+-----------------+
+; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------------+------------+-------+-------+------------+-----------------+
+; vout_rsc_z[*]   ; clk        ; 3.213 ; 3.241 ; Rise       ; clk             ;
+;  vout_rsc_z[0]  ; clk        ; 3.366 ; 3.404 ; Rise       ; clk             ;
+;  vout_rsc_z[1]  ; clk        ; 3.234 ; 3.315 ; Rise       ; clk             ;
+;  vout_rsc_z[2]  ; clk        ; 3.213 ; 3.241 ; Rise       ; clk             ;
+;  vout_rsc_z[3]  ; clk        ; 3.440 ; 3.488 ; Rise       ; clk             ;
+;  vout_rsc_z[4]  ; clk        ; 3.454 ; 3.512 ; Rise       ; clk             ;
+;  vout_rsc_z[5]  ; clk        ; 3.618 ; 3.668 ; Rise       ; clk             ;
+;  vout_rsc_z[6]  ; clk        ; 3.621 ; 3.668 ; Rise       ; clk             ;
+;  vout_rsc_z[7]  ; clk        ; 3.401 ; 3.429 ; Rise       ; clk             ;
+;  vout_rsc_z[8]  ; clk        ; 3.543 ; 3.590 ; Rise       ; clk             ;
+;  vout_rsc_z[9]  ; clk        ; 3.601 ; 3.652 ; Rise       ; clk             ;
+;  vout_rsc_z[10] ; clk        ; 3.634 ; 3.685 ; Rise       ; clk             ;
+;  vout_rsc_z[11] ; clk        ; 3.603 ; 3.678 ; Rise       ; clk             ;
+;  vout_rsc_z[12] ; clk        ; 3.422 ; 3.472 ; Rise       ; clk             ;
+;  vout_rsc_z[13] ; clk        ; 3.369 ; 3.425 ; Rise       ; clk             ;
+;  vout_rsc_z[14] ; clk        ; 3.433 ; 3.478 ; Rise       ; clk             ;
+;  vout_rsc_z[15] ; clk        ; 3.598 ; 3.677 ; Rise       ; clk             ;
+;  vout_rsc_z[16] ; clk        ; 3.641 ; 3.692 ; Rise       ; clk             ;
+;  vout_rsc_z[17] ; clk        ; 4.524 ; 4.742 ; Rise       ; clk             ;
+;  vout_rsc_z[18] ; clk        ; 4.373 ; 4.568 ; Rise       ; clk             ;
+;  vout_rsc_z[19] ; clk        ; 3.564 ; 3.608 ; Rise       ; clk             ;
+;  vout_rsc_z[20] ; clk        ; 3.597 ; 3.643 ; Rise       ; clk             ;
+;  vout_rsc_z[21] ; clk        ; 3.560 ; 3.598 ; Rise       ; clk             ;
+;  vout_rsc_z[22] ; clk        ; 3.439 ; 3.490 ; Rise       ; clk             ;
+;  vout_rsc_z[23] ; clk        ; 3.363 ; 3.407 ; Rise       ; clk             ;
+;  vout_rsc_z[24] ; clk        ; 3.447 ; 3.498 ; Rise       ; clk             ;
+;  vout_rsc_z[25] ; clk        ; 3.606 ; 3.653 ; Rise       ; clk             ;
+;  vout_rsc_z[26] ; clk        ; 3.684 ; 3.769 ; Rise       ; clk             ;
+;  vout_rsc_z[27] ; clk        ; 3.659 ; 3.713 ; Rise       ; clk             ;
+;  vout_rsc_z[28] ; clk        ; 3.601 ; 3.646 ; Rise       ; clk             ;
+;  vout_rsc_z[29] ; clk        ; 3.797 ; 3.865 ; Rise       ; clk             ;
++-----------------+------------+-------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
++----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; vout_rsc_z[0]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[1]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[2]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[3]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[4]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[5]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[6]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[7]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[8]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[9]  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[10] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[11] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[12] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[13] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[14] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[15] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[16] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[17] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[18] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[19] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[20] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[21] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[22] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[23] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[24] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[25] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[26] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[27] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[28] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; vout_rsc_z[29] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_nCEO~  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; clk                     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; arst_n                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; en                      ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[57]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[56]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[55]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[54]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[53]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[52]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[51]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[50]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[47]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[37]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[46]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[36]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[45]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[35]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[44]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[34]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[43]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[33]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[42]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[32]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[41]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[31]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[40]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[30]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[78]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[68]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[77]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[67]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[76]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[66]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[75]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[65]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[74]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[64]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[73]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[63]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[72]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[62]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[71]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[61]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[70]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[60]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[88]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[87]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[86]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[85]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[84]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[83]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[82]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[81]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[80]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[8]            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[7]            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[6]            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[5]            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[4]            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[3]            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[2]            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[1]            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[0]            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[28]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[18]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[27]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[17]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[26]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[16]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[25]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[15]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[24]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[14]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[23]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[13]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[22]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[12]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[21]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[11]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[20]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[10]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[9]            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[29]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[19]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[79]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[69]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[89]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[59]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[58]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[49]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[39]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[48]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; vin_rsc_z[38]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
++----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; vout_rsc_z[0]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[1]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.36 V              ; -0.00946 V          ; 0.111 V                              ; 0.027 V                              ; 6.46e-10 s                  ; 6.2e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.36 V             ; -0.00946 V         ; 0.111 V                             ; 0.027 V                             ; 6.46e-10 s                 ; 6.2e-10 s                  ; Yes                       ; Yes                       ;
+; vout_rsc_z[2]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[3]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[4]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[5]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[6]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[7]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[8]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[9]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[10] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[11] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[12] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[13] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[14] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[15] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[16] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[17] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.33 V              ; -0.00317 V          ; 0.162 V                              ; 0.063 V                              ; 3.54e-09 s                  ; 3.41e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.33 V             ; -0.00317 V         ; 0.162 V                             ; 0.063 V                             ; 3.54e-09 s                 ; 3.41e-09 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[18] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.33 V              ; -0.00317 V          ; 0.162 V                              ; 0.063 V                              ; 3.54e-09 s                  ; 3.41e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.33 V             ; -0.00317 V         ; 0.162 V                             ; 0.063 V                             ; 3.54e-09 s                 ; 3.41e-09 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[19] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[20] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[21] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[22] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[23] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[24] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[25] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[26] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[27] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[28] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[29] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_nCEO~  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
++----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
++----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; vout_rsc_z[0]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[1]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[2]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[3]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[4]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[5]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[6]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[7]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[8]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[9]  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[10] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[11] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; vout_rsc_z[12] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[13] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[14] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[15] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[16] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[17] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[18] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[19] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[20] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[21] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[22] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[23] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[24] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[25] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[26] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[27] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[28] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; vout_rsc_z[29] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_nCEO~  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
++----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Setup Transfers                                                       ;
++------------+----------+--------------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths     ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+--------------+----------+----------+----------+
+; clk        ; clk      ; > 2147483647 ; 0        ; 0        ; 0        ;
++------------+----------+--------------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-----------------------------------------------------------------------+
+; Hold Transfers                                                        ;
++------------+----------+--------------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths     ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+--------------+----------+----------+----------+
+; clk        ; clk      ; > 2147483647 ; 0        ; 0        ; 0        ;
++------------+----------+--------------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 92    ; 92   ;
+; Unconstrained Input Port Paths  ; 5908  ; 5908 ;
+; Unconstrained Output Ports      ; 30    ; 30   ;
+; Unconstrained Output Port Paths ; 30    ; 30   ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 08 16:22:26 2016
+Info: Command: quartus_sta sobel -c sobel
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'sobel.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name clk clk
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -21.345
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):   -21.345     -1510.709 clk 
+Info (332146): Worst-case hold slack is 0.516
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.516         0.000 clk 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000      -287.000 clk 
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -18.828
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):   -18.828     -1326.336 clk 
+Info (332146): Worst-case hold slack is 0.466
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.466         0.000 clk 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000      -287.000 clk 
+Info: Analyzing Fast 1200mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -11.400
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):   -11.400      -781.716 clk 
+Info (332146): Worst-case hold slack is 0.268
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.268         0.000 clk 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000      -303.956 clk 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 522 megabytes
+    Info: Processing ended: Tue Mar 08 16:22:33 2016
+    Info: Elapsed time: 00:00:07
+    Info: Total CPU time (on all processors): 00:00:03
+
+
diff --git a/Sobel/Sobel Quartus/output_files/sobel.sta.summary b/Sobel/Sobel Quartus/output_files/sobel.sta.summary
new file mode 100644
index 0000000..b1bad66
--- /dev/null
+++ b/Sobel/Sobel Quartus/output_files/sobel.sta.summary
@@ -0,0 +1,41 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'clk'
+Slack : -21.345
+TNS   : -1510.709
+
+Type  : Slow 1200mV 85C Model Hold 'clk'
+Slack : 0.516
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'clk'
+Slack : -3.000
+TNS   : -287.000
+
+Type  : Slow 1200mV 0C Model Setup 'clk'
+Slack : -18.828
+TNS   : -1326.336
+
+Type  : Slow 1200mV 0C Model Hold 'clk'
+Slack : 0.466
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'clk'
+Slack : -3.000
+TNS   : -287.000
+
+Type  : Fast 1200mV 0C Model Setup 'clk'
+Slack : -11.400
+TNS   : -781.716
+
+Type  : Fast 1200mV 0C Model Hold 'clk'
+Slack : 0.268
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'clk'
+Slack : -3.000
+TNS   : -303.956
+
+------------------------------------------------------------
diff --git a/Sobel/Sobel Quartus/sobel.bsf b/Sobel/Sobel Quartus/sobel.bsf
new file mode 100644
index 0000000..87f2864
--- /dev/null
+++ b/Sobel/Sobel Quartus/sobel.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 256 128)
+	(text "sobel" (rect 5 0 25 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "vin_rsc_z[89..0]" (rect 0 0 64 12)(font "Arial" ))
+		(text "vin_rsc_z[89..0]" (rect 21 27 85 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 43 31 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 59 30 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 75 46 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 240 32)
+		(output)
+		(text "vout_rsc_z[29..0]" (rect 0 0 70 12)(font "Arial" ))
+		(text "vout_rsc_z[29..0]" (rect 149 27 219 39)(font "Arial" ))
+		(line (pt 240 32)(pt 224 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 224 96)(line_width 1))
+	)
+)
diff --git a/Sobel/Sobel Quartus/sobel.qpf b/Sobel/Sobel Quartus/sobel.qpf
new file mode 100644
index 0000000..4106245
--- /dev/null
+++ b/Sobel/Sobel Quartus/sobel.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 13:55:47  March 08, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "13:55:47  March 08, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "sobel"
diff --git a/Sobel/Sobel Quartus/sobel.qsf b/Sobel/Sobel Quartus/sobel.qsf
new file mode 100644
index 0000000..a09de45
--- /dev/null
+++ b/Sobel/Sobel Quartus/sobel.qsf
@@ -0,0 +1,56 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 13:55:47  March 08, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		sobel_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY sobel
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:55:47  MARCH 08, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE ../sobel.v12/rtl_mgc_ioport.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Sobel/Sobel Quartus/sobel.qws b/Sobel/Sobel Quartus/sobel.qws
new file mode 100644
index 0000000..9b0318a
--- /dev/null
+++ b/Sobel/Sobel Quartus/sobel.qws
diff --git a/Sobel/Sobel Quartus/sobel.v b/Sobel/Sobel Quartus/sobel.v
new file mode 100644
index 0000000..261a927
--- /dev/null
+++ b/Sobel/Sobel Quartus/sobel.v
@@ -0,0 +1,1609 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 16:19:43 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] regs_regs_slc_regs_regs_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_1_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_4_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_5_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_3_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_10_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_11_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_9_itm;
+  reg [12:0] ACC1_acc_659_itm_1;
+  wire [14:0] nl_ACC1_acc_659_itm_1;
+  reg [12:0] ACC1_acc_658_itm_1;
+  wire [13:0] nl_ACC1_acc_658_itm_1;
+  reg [13:0] ACC1_acc_661_itm_1;
+  wire [14:0] nl_ACC1_acc_661_itm_1;
+  reg slc_acc_20_psp_1_93_itm_1;
+  reg ACC1_slc_ACC1_acc_228_psp_55_itm_1;
+  reg ACC1_3_slc_acc_10_psp_62_itm_1;
+  reg [10:0] ACC1_acc_652_itm_1;
+  wire [11:0] nl_ACC1_acc_652_itm_1;
+  reg [11:0] ACC1_acc_655_itm_1;
+  wire [12:0] nl_ACC1_acc_655_itm_1;
+  reg main_stage_0_2;
+  reg [4:0] ACC1_mul_57_itm_1_sg2;
+  reg [1:0] ACC1_mul_57_itm_2;
+  reg [89:0] reg_regs_regs_0_sva_cse;
+  wire [11:0] FRAME_acc_2_psp_sva;
+  wire [13:0] nl_FRAME_acc_2_psp_sva;
+  wire [5:0] acc_imod_24_sva;
+  wire [7:0] nl_acc_imod_24_sva;
+  wire [11:0] acc_20_psp_1_sva;
+  wire [12:0] nl_acc_20_psp_1_sva;
+  wire [11:0] ACC1_acc_228_psp_sva;
+  wire [12:0] nl_ACC1_acc_228_psp_sva;
+  wire [11:0] ACC1_1_acc_25_psp_sva;
+  wire [12:0] nl_ACC1_1_acc_25_psp_sva;
+  wire [2:0] ACC1_acc_509_cse;
+  wire [3:0] nl_ACC1_acc_509_cse;
+  wire [11:0] ACC1_acc_227_psp_sva;
+  wire [12:0] nl_ACC1_acc_227_psp_sva;
+  wire [2:0] ACC1_acc_506_cse;
+  wire [3:0] nl_ACC1_acc_506_cse;
+  wire [3:0] ACC1_acc_562_ncse;
+  wire [4:0] nl_ACC1_acc_562_ncse;
+  wire [2:0] ACC1_acc_502_cse;
+  wire [3:0] nl_ACC1_acc_502_cse;
+  wire [2:0] ACC1_acc_489_cse;
+  wire [3:0] nl_ACC1_acc_489_cse;
+  wire [11:0] ACC1_acc_226_psp_sva;
+  wire [12:0] nl_ACC1_acc_226_psp_sva;
+  wire [3:0] ACC1_acc_553_ncse;
+  wire [4:0] nl_ACC1_acc_553_ncse;
+  wire ACC1_1_and_3_cse_sva;
+  wire ACC1_1_nand_1_cse_sva;
+  wire [11:0] acc_psp_1_sva;
+  wire [12:0] nl_acc_psp_1_sva;
+  wire [3:0] ACC1_acc_210_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_210_psp_2_sva;
+  wire [11:0] acc_psp_2_sva;
+  wire [12:0] nl_acc_psp_2_sva;
+  wire [11:0] ACC1_acc_224_psp_1_sva;
+  wire [12:0] nl_ACC1_acc_224_psp_1_sva;
+  wire [3:0] ACC1_1_acc_208_psp_sva;
+  wire [4:0] nl_ACC1_1_acc_208_psp_sva;
+  wire [11:0] ACC1_acc_224_psp_sva;
+  wire [12:0] nl_ACC1_acc_224_psp_sva;
+  wire [2:0] ACC1_acc_516_cse;
+  wire [3:0] nl_ACC1_acc_516_cse;
+  wire [3:0] ACC1_3_acc_212_psp_sva;
+  wire [4:0] nl_ACC1_3_acc_212_psp_sva;
+  wire [2:0] ACC1_acc_221_psp_sva;
+  wire [3:0] nl_ACC1_acc_221_psp_sva;
+  wire [2:0] ACC1_acc_221_psp_2_sva;
+  wire [3:0] nl_ACC1_acc_221_psp_2_sva;
+  wire [2:0] ACC1_acc_219_psp_2_sva;
+  wire [3:0] nl_ACC1_acc_219_psp_2_sva;
+  wire [2:0] ACC1_acc_222_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_222_psp_1_sva;
+  wire [2:0] ACC1_acc_219_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_219_psp_1_sva;
+  wire [3:0] ACC1_acc_210_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_210_psp_1_sva;
+  wire [3:0] ACC1_acc_217_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_217_psp_1_sva;
+  wire [2:0] ACC1_acc_724_cse;
+  wire [3:0] nl_ACC1_acc_724_cse;
+  wire [13:0] ACC1_mul_57_itm;
+  wire [27:0] nl_ACC1_mul_57_itm;
+  wire [2:0] ACC1_acc_223_psp_sva;
+  wire [3:0] nl_ACC1_acc_223_psp_sva;
+  wire [2:0] ACC1_acc_220_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_220_psp_1_sva;
+  wire [2:0] ACC1_acc_220_psp_sva;
+  wire [3:0] nl_ACC1_acc_220_psp_sva;
+  wire [2:0] ACC1_acc_222_psp_sva;
+  wire [3:0] nl_ACC1_acc_222_psp_sva;
+  wire [2:0] ACC1_acc_673_cse;
+  wire [3:0] nl_ACC1_acc_673_cse;
+  wire [11:0] acc_20_psp_2_sva;
+  wire [12:0] nl_acc_20_psp_2_sva;
+  wire [3:0] ACC1_acc_217_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_217_psp_2_sva;
+  wire [2:0] ACC1_acc_223_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_223_psp_1_sva;
+  wire [2:0] ACC1_acc_699_cse;
+  wire [3:0] nl_ACC1_acc_699_cse;
+  wire [14:0] ACC1_acc_itm;
+  wire [16:0] nl_ACC1_acc_itm;
+  wire [3:0] ACC1_acc_338_itm;
+  wire [4:0] nl_ACC1_acc_338_itm;
+  wire [2:0] ACC1_acc_406_itm;
+  wire [3:0] nl_ACC1_acc_406_itm;
+  wire [2:0] ACC1_acc_368_itm;
+  wire [3:0] nl_ACC1_acc_368_itm;
+  wire [3:0] ACC1_acc_367_itm;
+  wire [4:0] nl_ACC1_acc_367_itm;
+  wire [2:0] ACC1_acc_349_itm;
+  wire [3:0] nl_ACC1_acc_349_itm;
+  wire [3:0] ACC1_acc_348_itm;
+  wire [4:0] nl_ACC1_acc_348_itm;
+  wire [4:0] ACC1_acc_412_itm;
+  wire [5:0] nl_ACC1_acc_412_itm;
+  wire [3:0] ACC1_acc_423_itm;
+  wire [4:0] nl_ACC1_acc_423_itm;
+  wire [4:0] ACC1_acc_375_itm;
+  wire [5:0] nl_ACC1_acc_375_itm;
+  wire [3:0] ACC1_acc_395_itm;
+  wire [4:0] nl_ACC1_acc_395_itm;
+  wire [4:0] ACC1_acc_384_itm;
+  wire [5:0] nl_ACC1_acc_384_itm;
+  wire [3:0] ACC1_acc_414_itm;
+  wire [4:0] nl_ACC1_acc_414_itm;
+  wire [3:0] ACC1_acc_377_itm;
+  wire [4:0] nl_ACC1_acc_377_itm;
+  wire [4:0] ACC1_acc_346_itm;
+  wire [5:0] nl_ACC1_acc_346_itm;
+  wire [3:0] ACC1_acc_386_itm;
+  wire [4:0] nl_ACC1_acc_386_itm;
+  wire [3:0] ACC1_acc_405_itm;
+  wire [4:0] nl_ACC1_acc_405_itm;
+  wire [2:0] ACC1_acc_387_itm;
+  wire [3:0] nl_ACC1_acc_387_itm;
+  wire [2:0] ACC1_acc_378_itm;
+  wire [3:0] nl_ACC1_acc_378_itm;
+  wire [2:0] ACC1_acc_415_itm;
+  wire [3:0] nl_ACC1_acc_415_itm;
+  wire [2:0] ACC1_acc_396_itm;
+  wire [3:0] nl_ACC1_acc_396_itm;
+  wire [2:0] ACC1_acc_424_itm;
+  wire [3:0] nl_ACC1_acc_424_itm;
+  wire [2:0] ACC1_acc_359_itm;
+  wire [3:0] nl_ACC1_acc_359_itm;
+  wire [3:0] ACC1_acc_358_itm;
+  wire [4:0] nl_ACC1_acc_358_itm;
+  wire [2:0] ACC1_acc_339_itm;
+  wire [3:0] nl_ACC1_acc_339_itm;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_2_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(ACC1_acc_itm[14:13])
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_itm[12:10])
+      * 9'b111001)) + conv_s2s_7_10(conv_u2s_6_7(ACC1_acc_itm[9:4]) + conv_s2s_5_7(({4'b1001
+      , (acc_imod_24_sva[5])}) + conv_u2s_4_5((conv_u2u_3_4({(~ (acc_imod_24_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_24_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_24_sva[5:3])) , (~ (acc_imod_24_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_24_sva[4:3]))
+      + conv_u2u_3_4(~ (ACC1_acc_itm[9:7]))))))) + conv_u2u_11_12(signext_11_9({(ACC1_acc_itm[14])
+      , 3'b0 , (signext_3_1(ACC1_acc_itm[14])) , 1'b0 , (ACC1_acc_itm[14])}));
+  assign FRAME_acc_2_psp_sva = nl_FRAME_acc_2_psp_sva[11:0];
+  assign nl_ACC1_acc_itm = (conv_s2s_14_15(conv_s2s_13_14(ACC1_acc_659_itm_1) + conv_s2s_13_14(ACC1_acc_658_itm_1))
+      + conv_s2s_14_15(ACC1_acc_661_itm_1)) + conv_s2s_14_15(({ACC1_mul_57_itm_1_sg2
+      , 7'b0 , ACC1_mul_57_itm_2}) + conv_s2s_13_14(conv_s2s_12_13(({slc_acc_20_psp_1_93_itm_1
+      , 2'b0 , slc_acc_20_psp_1_93_itm_1 , 1'b0 , slc_acc_20_psp_1_93_itm_1 , 1'b0
+      , slc_acc_20_psp_1_93_itm_1 , ACC1_slc_ACC1_acc_228_psp_55_itm_1 , 1'b0 , ({{1{ACC1_3_slc_acc_10_psp_62_itm_1}},
+      ACC1_3_slc_acc_10_psp_62_itm_1})}) + conv_u2s_11_12(ACC1_acc_652_itm_1)) +
+      conv_s2s_12_13(ACC1_acc_655_itm_1)));
+  assign ACC1_acc_itm = nl_ACC1_acc_itm[14:0];
+  assign nl_acc_imod_24_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~ (ACC1_acc_itm[14]))
+      , 1'b1 , (~ (ACC1_acc_itm[14]))}) + conv_u2u_2_4(ACC1_acc_itm[14:13]))) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_itm[3:1])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[6:4])))) + 6'b101011;
+  assign acc_imod_24_sva = nl_acc_imod_24_sva[5:0];
+  assign nl_acc_20_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_10_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_11_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_9_itm);
+  assign acc_20_psp_1_sva = nl_acc_20_psp_1_sva[11:0];
+  assign nl_ACC1_acc_228_psp_sva = conv_s2u_11_12(conv_s2s_10_11(~ (reg_regs_regs_0_sva_cse[9:0]))
+      + conv_s2s_10_11(~ (reg_regs_regs_0_sva_cse[19:10]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (reg_regs_regs_0_sva_cse[29:20])) + 11'b11);
+  assign ACC1_acc_228_psp_sva = nl_ACC1_acc_228_psp_sva[11:0];
+  assign nl_ACC1_1_acc_25_psp_sva = conv_s2s_11_12(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[79:70])
+      + conv_s2s_10_11(vin_rsc_mgc_in_wire_d[69:60])) + conv_s2s_10_12(vin_rsc_mgc_in_wire_d[89:80]);
+  assign ACC1_1_acc_25_psp_sva = nl_ACC1_1_acc_25_psp_sva[11:0];
+  assign nl_ACC1_acc_509_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]));
+  assign ACC1_acc_509_cse = nl_ACC1_acc_509_cse[2:0];
+  assign nl_ACC1_acc_227_psp_sva = conv_s2s_11_12(conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_itm)
+      + conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_1_itm)) + conv_s2s_11_12(conv_s2s_10_11(~
+      regs_regs_slc_regs_regs_2_2_itm) + 11'b11);
+  assign ACC1_acc_227_psp_sva = nl_ACC1_acc_227_psp_sva[11:0];
+  assign nl_ACC1_acc_506_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+  assign ACC1_acc_506_cse = nl_ACC1_acc_506_cse[2:0];
+  assign nl_ACC1_acc_562_ncse = conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(ACC1_acc_506_cse);
+  assign ACC1_acc_562_ncse = nl_ACC1_acc_562_ncse[3:0];
+  assign nl_ACC1_acc_502_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[5])) + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+  assign ACC1_acc_502_cse = nl_ACC1_acc_502_cse[2:0];
+  assign nl_ACC1_acc_489_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]));
+  assign ACC1_acc_489_cse = nl_ACC1_acc_489_cse[2:0];
+  assign nl_ACC1_acc_226_psp_sva = conv_s2u_11_12(conv_s2s_10_11(reg_regs_regs_0_sva_cse[79:70])
+      + conv_s2s_10_11(reg_regs_regs_0_sva_cse[69:60])) + conv_s2u_10_12(reg_regs_regs_0_sva_cse[89:80]);
+  assign ACC1_acc_226_psp_sva = nl_ACC1_acc_226_psp_sva[11:0];
+  assign nl_ACC1_acc_553_ncse = conv_u2u_3_4(ACC1_acc_489_cse) + conv_u2u_3_4(ACC1_acc_489_cse);
+  assign ACC1_acc_553_ncse = nl_ACC1_acc_553_ncse[3:0];
+  assign ACC1_1_and_3_cse_sva = (acc_psp_2_sva[11]) & (~ (ACC1_acc_339_itm[2])) &
+      (ACC1_acc_339_itm[1]);
+  assign ACC1_1_nand_1_cse_sva = ~((ACC1_acc_339_itm[2]) & (~ (acc_psp_2_sva[11])));
+  assign nl_acc_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_1_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_2_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_itm);
+  assign acc_psp_1_sva = nl_acc_psp_1_sva[11:0];
+  assign nl_ACC1_acc_338_itm = conv_s2s_3_4({(~ (ACC1_acc_220_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_220_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_338_itm = nl_ACC1_acc_338_itm[3:0];
+  assign nl_ACC1_acc_210_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_2_sva[1])) , (acc_psp_2_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_2_sva[0]) , (acc_psp_2_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[3])) , (~ (acc_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[5])) , (acc_psp_2_sva[6])})))) ,
+      (~ (acc_psp_2_sva[9]))}))));
+  assign ACC1_acc_210_psp_2_sva = nl_ACC1_acc_210_psp_2_sva[3:0];
+  assign nl_acc_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[29:20]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[19:10]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[9:0])) + 11'b11);
+  assign acc_psp_2_sva = nl_acc_psp_2_sva[11:0];
+  assign nl_ACC1_acc_224_psp_1_sva = conv_s2u_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[39:30]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[49:40]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[59:50])) + 11'b11);
+  assign ACC1_acc_224_psp_1_sva = nl_ACC1_acc_224_psp_1_sva[11:0];
+  assign nl_ACC1_acc_406_itm = ({1'b1 , (ACC1_acc_405_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_405_itm[2])) , (~ (ACC1_acc_405_itm[3]))});
+  assign ACC1_acc_406_itm = nl_ACC1_acc_406_itm[2:0];
+  assign nl_ACC1_acc_368_itm = ({1'b1 , (ACC1_acc_367_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_367_itm[2])) , (~ (ACC1_acc_367_itm[3]))});
+  assign ACC1_acc_368_itm = nl_ACC1_acc_368_itm[2:0];
+  assign nl_ACC1_acc_367_itm = conv_s2s_3_4({(~ (ACC1_acc_219_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_367_itm = nl_ACC1_acc_367_itm[3:0];
+  assign nl_ACC1_1_acc_208_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (ACC1_1_acc_25_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_1_acc_25_psp_sva[1]))
+      , (ACC1_1_acc_25_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (ACC1_1_acc_25_psp_sva[0])
+      , (ACC1_1_acc_25_psp_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[3])) , (~ (ACC1_1_acc_25_psp_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[5])) , (ACC1_1_acc_25_psp_sva[6])}))))
+      , (~ (ACC1_1_acc_25_psp_sva[9]))}))));
+  assign ACC1_1_acc_208_psp_sva = nl_ACC1_1_acc_208_psp_sva[3:0];
+  assign nl_ACC1_acc_349_itm = ({1'b1 , (ACC1_acc_348_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_348_itm[2])) , (~ (ACC1_acc_348_itm[3]))});
+  assign ACC1_acc_349_itm = nl_ACC1_acc_349_itm[2:0];
+  assign nl_ACC1_acc_348_itm = conv_s2s_3_4({(~ (ACC1_acc_222_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_222_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_348_itm = nl_ACC1_acc_348_itm[3:0];
+  assign nl_ACC1_acc_224_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_4_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_5_itm)) + conv_s2u_10_12(regs_regs_slc_regs_regs_2_3_itm);
+  assign ACC1_acc_224_psp_sva = nl_ACC1_acc_224_psp_sva[11:0];
+  assign nl_ACC1_acc_516_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]));
+  assign ACC1_acc_516_cse = nl_ACC1_acc_516_cse[2:0];
+  assign nl_ACC1_acc_412_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_224_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[2])) , (~ (ACC1_acc_224_psp_sva[6]))}))))
+      , (~ (ACC1_acc_224_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[4])) , (ACC1_acc_224_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_sva[11:10])) , (ACC1_acc_224_psp_sva[7])}))))
+      , (ACC1_acc_224_psp_sva[9])});
+  assign ACC1_acc_412_itm = nl_ACC1_acc_412_itm[4:0];
+  assign nl_ACC1_acc_423_itm = conv_s2s_3_4({(~ (ACC1_acc_223_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_223_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_423_itm = nl_ACC1_acc_423_itm[3:0];
+  assign nl_ACC1_acc_375_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_228_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[2])) , (~ (ACC1_acc_228_psp_sva[6]))}))))
+      , (~ (ACC1_acc_228_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[4])) , (ACC1_acc_228_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_228_psp_sva[11:10])) , (ACC1_acc_228_psp_sva[7])}))))
+      , (ACC1_acc_228_psp_sva[9])});
+  assign ACC1_acc_375_itm = nl_ACC1_acc_375_itm[4:0];
+  assign nl_ACC1_acc_395_itm = conv_s2s_3_4({(~ (ACC1_acc_220_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_220_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_395_itm = nl_ACC1_acc_395_itm[3:0];
+  assign nl_ACC1_acc_384_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_226_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[2])) , (~ (ACC1_acc_226_psp_sva[6]))}))))
+      , (~ (ACC1_acc_226_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[4])) , (ACC1_acc_226_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_226_psp_sva[11:10])) , (ACC1_acc_226_psp_sva[7])}))))
+      , (ACC1_acc_226_psp_sva[9])});
+  assign ACC1_acc_384_itm = nl_ACC1_acc_384_itm[4:0];
+  assign nl_ACC1_3_acc_212_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (ACC1_acc_227_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_acc_227_psp_sva[1]))
+      , (ACC1_acc_227_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (ACC1_acc_227_psp_sva[0])
+      , (ACC1_acc_227_psp_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[3])) , (~ (ACC1_acc_227_psp_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[5])) , (ACC1_acc_227_psp_sva[6])}))))
+      , (~ (ACC1_acc_227_psp_sva[9]))}))));
+  assign ACC1_3_acc_212_psp_sva = nl_ACC1_3_acc_212_psp_sva[3:0];
+  assign nl_ACC1_acc_414_itm = conv_s2s_3_4({(~ (ACC1_acc_222_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_222_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_414_itm = nl_ACC1_acc_414_itm[3:0];
+  assign nl_ACC1_acc_377_itm = conv_s2s_3_4({(~ (ACC1_acc_221_psp_2_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_221_psp_2_sva[0]) , 1'b1});
+  assign ACC1_acc_377_itm = nl_ACC1_acc_377_itm[3:0];
+  assign nl_ACC1_acc_346_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_224_psp_1_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[2])) , (~ (ACC1_acc_224_psp_1_sva[6]))}))))
+      , (~ (ACC1_acc_224_psp_1_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[4])) , (ACC1_acc_224_psp_1_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_1_sva[11:10])) , (ACC1_acc_224_psp_1_sva[7])}))))
+      , (ACC1_acc_224_psp_1_sva[9])});
+  assign ACC1_acc_346_itm = nl_ACC1_acc_346_itm[4:0];
+  assign nl_ACC1_acc_386_itm = conv_s2s_3_4({(~ (ACC1_acc_219_psp_2_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_2_sva[0]) , 1'b1});
+  assign ACC1_acc_386_itm = nl_ACC1_acc_386_itm[3:0];
+  assign nl_ACC1_acc_405_itm = conv_s2s_3_4({(~ (ACC1_acc_221_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_221_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_405_itm = nl_ACC1_acc_405_itm[3:0];
+  assign nl_ACC1_acc_221_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_3_acc_212_psp_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_3_acc_212_psp_sva[1])) , (ACC1_3_acc_212_psp_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_3_acc_212_psp_sva[3]));
+  assign ACC1_acc_221_psp_sva = nl_ACC1_acc_221_psp_sva[2:0];
+  assign nl_ACC1_acc_221_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_375_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_375_itm[2])) , (ACC1_acc_375_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_375_itm[4]));
+  assign ACC1_acc_221_psp_2_sva = nl_ACC1_acc_221_psp_2_sva[2:0];
+  assign nl_ACC1_acc_219_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_384_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_384_itm[2])) , (ACC1_acc_384_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_384_itm[4]));
+  assign ACC1_acc_219_psp_2_sva = nl_ACC1_acc_219_psp_2_sva[2:0];
+  assign nl_ACC1_acc_222_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_346_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_346_itm[2])) , (ACC1_acc_346_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_346_itm[4]));
+  assign ACC1_acc_222_psp_1_sva = nl_ACC1_acc_222_psp_1_sva[2:0];
+  assign nl_ACC1_acc_219_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_208_psp_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_208_psp_sva[1])) , (ACC1_1_acc_208_psp_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_1_acc_208_psp_sva[3]));
+  assign ACC1_acc_219_psp_1_sva = nl_ACC1_acc_219_psp_1_sva[2:0];
+  assign nl_ACC1_acc_387_itm = ({1'b1 , (ACC1_acc_386_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_386_itm[2])) , (~ (ACC1_acc_386_itm[3]))});
+  assign ACC1_acc_387_itm = nl_ACC1_acc_387_itm[2:0];
+  assign nl_ACC1_acc_378_itm = ({1'b1 , (ACC1_acc_377_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_377_itm[2])) , (~ (ACC1_acc_377_itm[3]))});
+  assign ACC1_acc_378_itm = nl_ACC1_acc_378_itm[2:0];
+  assign nl_ACC1_acc_415_itm = ({1'b1 , (ACC1_acc_414_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_414_itm[2])) , (~ (ACC1_acc_414_itm[3]))});
+  assign ACC1_acc_415_itm = nl_ACC1_acc_415_itm[2:0];
+  assign nl_ACC1_acc_396_itm = ({1'b1 , (ACC1_acc_395_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_395_itm[2])) , (~ (ACC1_acc_395_itm[3]))});
+  assign ACC1_acc_396_itm = nl_ACC1_acc_396_itm[2:0];
+  assign nl_ACC1_acc_210_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_1_sva[1])) , (acc_psp_1_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_1_sva[0]) , (acc_psp_1_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[3])) , (~ (acc_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[5])) , (acc_psp_1_sva[6])})))) ,
+      (~ (acc_psp_1_sva[9]))}))));
+  assign ACC1_acc_210_psp_1_sva = nl_ACC1_acc_210_psp_1_sva[3:0];
+  assign nl_ACC1_acc_217_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_20_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_1_sva[1]))
+      , (acc_20_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_1_sva[0])
+      , (acc_20_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[3])) , (~ (acc_20_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[5])) , (acc_20_psp_1_sva[6])}))))
+      , (~ (acc_20_psp_1_sva[9]))}))));
+  assign ACC1_acc_217_psp_1_sva = nl_ACC1_acc_217_psp_1_sva[3:0];
+  assign nl_ACC1_acc_424_itm = ({1'b1 , (ACC1_acc_423_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_423_itm[2])) , (~ (ACC1_acc_423_itm[3]))});
+  assign ACC1_acc_424_itm = nl_ACC1_acc_424_itm[2:0];
+  assign nl_ACC1_acc_724_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]));
+  assign ACC1_acc_724_cse = nl_ACC1_acc_724_cse[2:0];
+  assign nl_ACC1_mul_57_itm = conv_u2s_2_14((conv_u2u_1_2(ACC1_acc_224_psp_sva[11])
+      + conv_u2u_1_2(ACC1_acc_228_psp_sva[11])) + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[11]))
+      * 14'b11101000000001;
+  assign ACC1_mul_57_itm = nl_ACC1_mul_57_itm[13:0];
+  assign nl_ACC1_acc_223_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_1_sva[1])) , (ACC1_acc_217_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_217_psp_1_sva[3]));
+  assign ACC1_acc_223_psp_sva = nl_ACC1_acc_223_psp_sva[2:0];
+  assign nl_ACC1_acc_220_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_2_sva[1])) , (ACC1_acc_210_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_210_psp_2_sva[3]));
+  assign ACC1_acc_220_psp_1_sva = nl_ACC1_acc_220_psp_1_sva[2:0];
+  assign nl_ACC1_acc_220_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_1_sva[1])) , (ACC1_acc_210_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_210_psp_1_sva[3]));
+  assign ACC1_acc_220_psp_sva = nl_ACC1_acc_220_psp_sva[2:0];
+  assign nl_ACC1_acc_222_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_412_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_412_itm[2])) , (ACC1_acc_412_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_412_itm[4]));
+  assign ACC1_acc_222_psp_sva = nl_ACC1_acc_222_psp_sva[2:0];
+  assign nl_ACC1_acc_673_cse = conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11]));
+  assign ACC1_acc_673_cse = nl_ACC1_acc_673_cse[2:0];
+  assign nl_acc_20_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[89:80]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[79:70]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[69:60])) + 11'b11);
+  assign acc_20_psp_2_sva = nl_acc_20_psp_2_sva[11:0];
+  assign nl_ACC1_acc_359_itm = ({1'b1 , (ACC1_acc_358_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_358_itm[2])) , (~ (ACC1_acc_358_itm[3]))});
+  assign ACC1_acc_359_itm = nl_ACC1_acc_359_itm[2:0];
+  assign nl_ACC1_acc_358_itm = conv_s2s_3_4({(~ (ACC1_acc_223_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_223_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_358_itm = nl_ACC1_acc_358_itm[3:0];
+  assign nl_ACC1_acc_217_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_20_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_2_sva[1]))
+      , (acc_20_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_2_sva[0])
+      , (acc_20_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[3])) , (~ (acc_20_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[5])) , (acc_20_psp_2_sva[6])}))))
+      , (~ (acc_20_psp_2_sva[9]))}))));
+  assign ACC1_acc_217_psp_2_sva = nl_ACC1_acc_217_psp_2_sva[3:0];
+  assign nl_ACC1_acc_223_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_2_sva[1])) , (ACC1_acc_217_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_217_psp_2_sva[3]));
+  assign ACC1_acc_223_psp_1_sva = nl_ACC1_acc_223_psp_1_sva[2:0];
+  assign nl_ACC1_acc_699_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11]));
+  assign ACC1_acc_699_cse = nl_ACC1_acc_699_cse[2:0];
+  assign nl_ACC1_acc_339_itm = ({1'b1 , (ACC1_acc_338_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_338_itm[2])) , (~ (ACC1_acc_338_itm[3]))});
+  assign ACC1_acc_339_itm = nl_ACC1_acc_339_itm[2:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      ACC1_acc_659_itm_1 <= 13'b0;
+      ACC1_acc_658_itm_1 <= 13'b0;
+      ACC1_acc_661_itm_1 <= 14'b0;
+      ACC1_mul_57_itm_1_sg2 <= 5'b0;
+      ACC1_mul_57_itm_2 <= 2'b0;
+      slc_acc_20_psp_1_93_itm_1 <= 1'b0;
+      ACC1_slc_ACC1_acc_228_psp_55_itm_1 <= 1'b0;
+      ACC1_3_slc_acc_10_psp_62_itm_1 <= 1'b0;
+      ACC1_acc_652_itm_1 <= 11'b0;
+      ACC1_acc_655_itm_1 <= 12'b0;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_slc_regs_regs_2_10_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_11_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_9_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_4_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_5_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_3_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_1_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_2_itm <= 10'b0;
+      reg_regs_regs_0_sva_cse <= 90'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({vout_rsc_mgc_out_stdreg_d , ({((FRAME_acc_2_psp_sva[9:0])
+            | ({8'b0 , (FRAME_acc_2_psp_sva[11:10])})) , (FRAME_acc_2_psp_sva[9:6])
+            , ((FRAME_acc_2_psp_sva[5:0]) | ({4'b0 , (FRAME_acc_2_psp_sva[11:10])}))
+            , (FRAME_acc_2_psp_sva[9:0])})}, main_stage_0_2);
+        ACC1_acc_659_itm_1 <= nl_ACC1_acc_659_itm_1[12:0];
+        ACC1_acc_658_itm_1 <= nl_ACC1_acc_658_itm_1[12:0];
+        ACC1_acc_661_itm_1 <= nl_ACC1_acc_661_itm_1[13:0];
+        ACC1_mul_57_itm_1_sg2 <= ACC1_mul_57_itm[13:9];
+        ACC1_mul_57_itm_2 <= ACC1_mul_57_itm[1:0];
+        slc_acc_20_psp_1_93_itm_1 <= acc_20_psp_1_sva[11];
+        ACC1_slc_ACC1_acc_228_psp_55_itm_1 <= ACC1_acc_228_psp_sva[6];
+        ACC1_3_slc_acc_10_psp_62_itm_1 <= ACC1_acc_224_psp_sva[8];
+        ACC1_acc_652_itm_1 <= nl_ACC1_acc_652_itm_1[10:0];
+        ACC1_acc_655_itm_1 <= nl_ACC1_acc_655_itm_1[11:0];
+        main_stage_0_2 <= 1'b1;
+        regs_regs_slc_regs_regs_2_10_itm <= reg_regs_regs_0_sva_cse[79:70];
+        regs_regs_slc_regs_regs_2_11_itm <= reg_regs_regs_0_sva_cse[69:60];
+        regs_regs_slc_regs_regs_2_9_itm <= reg_regs_regs_0_sva_cse[89:80];
+        regs_regs_slc_regs_regs_2_4_itm <= reg_regs_regs_0_sva_cse[49:40];
+        regs_regs_slc_regs_regs_2_5_itm <= reg_regs_regs_0_sva_cse[39:30];
+        regs_regs_slc_regs_regs_2_3_itm <= reg_regs_regs_0_sva_cse[59:50];
+        regs_regs_slc_regs_regs_2_itm <= reg_regs_regs_0_sva_cse[29:20];
+        regs_regs_slc_regs_regs_2_1_itm <= reg_regs_regs_0_sva_cse[19:10];
+        regs_regs_slc_regs_regs_2_2_itm <= reg_regs_regs_0_sva_cse[9:0];
+        reg_regs_regs_0_sva_cse <= vin_rsc_mgc_in_wire_d;
+      end
+    end
+  end
+  assign nl_ACC1_acc_659_itm_1  = conv_s2s_12_13(conv_s2s_11_12({(ACC1_1_acc_25_psp_sva[11])
+      , 2'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11]) ,
+      1'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_224_psp_sva[0])})
+      + conv_u2s_11_12({conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[9])
+      + conv_u2u_1_2(acc_psp_1_sva[9])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[8]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[8])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[8]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[8])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[9]))
+      + conv_u2u_1_4(acc_psp_2_sva[9])) * 8'b10101) , (ACC1_acc_227_psp_sva[4]) ,
+      (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_s2s_12_13(conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_psp_2_sva[9]) , 1'b0
+      , (acc_psp_2_sva[9]) , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_2_sva[7]) , 1'b0 , (acc_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~ (ACC1_acc_338_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_338_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_210_psp_2_sva[3]) ,
+      (acc_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_220_psp_1_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_2_sva[3])
+      , (acc_psp_2_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_210_psp_2_sva[3]) ,
+      (acc_psp_2_sva[2]) , (ACC1_acc_210_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_2_sva[7])
+      , (acc_psp_2_sva[4]) , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_673_cse)))
+      + conv_u2s_7_8({(acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])
+      , 1'b0 , (acc_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_2_sva[6])
+      , 1'b0 , (acc_psp_2_sva[6]) , 1'b0 , (acc_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_673_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , ACC1_1_and_3_cse_sva}))))))))))
+      + ({(acc_psp_2_sva[11]) , 2'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11])
+      , 1'b0 , (acc_psp_2_sva[11]) , (conv_u2u_1_3(acc_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])))}))
+      + conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_20_psp_2_sva[10]) , 1'b0
+      , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10])
+      , 1'b0 , (acc_20_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_20_psp_2_sva[9]) ,
+      1'b0 , (acc_20_psp_2_sva[9]) , 1'b0 , (acc_20_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_20_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_20_psp_2_sva[7]) , 1'b0 , (acc_20_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_20_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~((ACC1_acc_359_itm[2])
+      & (~ (acc_20_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~ (ACC1_acc_358_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (ACC1_acc_358_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (ACC1_acc_217_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_20_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_217_psp_2_sva[3])
+      , (acc_20_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_223_psp_1_sva[2:1])) +
+      (readslicef_5_4_1((conv_u2s_3_5({(acc_20_psp_2_sva[3]) , (acc_20_psp_2_sva[1])
+      , 1'b1}) + conv_s2s_3_5({(ACC1_acc_217_psp_2_sva[3]) , (acc_20_psp_2_sva[2])
+      , (ACC1_acc_217_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_20_psp_2_sva[7])
+      , (acc_20_psp_2_sva[4]) , (signext_2_1(acc_20_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_699_cse)))
+      + conv_u2s_7_8({(acc_20_psp_2_sva[8]) , 1'b0 , (acc_20_psp_2_sva[8]) , 1'b0
+      , (acc_20_psp_2_sva[8]) , 1'b0 , (acc_20_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_20_psp_2_sva[11])
+      , (signext_2_1(acc_20_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_20_psp_2_sva[6])
+      , 1'b0 , (acc_20_psp_2_sva[6]) , 1'b0 , (acc_20_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_699_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[9]) , ((acc_20_psp_2_sva[11])
+      & (~ (ACC1_acc_359_itm[2])) & (ACC1_acc_359_itm[1]))})))))))))) + ({(acc_20_psp_2_sva[11])
+      , 2'b0 , (acc_20_psp_2_sva[11]) , 1'b0 , (acc_20_psp_2_sva[11]) , 1'b0 , (acc_20_psp_2_sva[11])
+      , (conv_u2u_1_3(acc_20_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])))})));
+  assign nl_ACC1_acc_658_itm_1  = conv_s2s_12_13(conv_s2s_10_12(conv_s2s_9_10(conv_u2s_7_9(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(ACC1_acc_224_psp_1_sva[6])
+      , (ACC1_acc_228_psp_sva[3]) , (signext_2_1(ACC1_acc_224_psp_sva[11]))}) + conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[5])
+      , (ACC1_acc_226_psp_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})) +
+      conv_u2u_5_6(conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[7]) , (ACC1_acc_224_psp_1_sva[3])
+      , (signext_2_1(ACC1_acc_228_psp_sva[11]))}) + conv_u2u_4_5({(acc_20_psp_1_sva[4])
+      , (ACC1_1_acc_25_psp_sva[4]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(~ (ACC1_acc_217_psp_1_sva[3])) ,
+      (~ (ACC1_acc_210_psp_1_sva[3])) , 1'b1 , (~ (ACC1_acc_367_itm[3]))}) + conv_u2u_4_5({(acc_psp_2_sva[5])
+      , (acc_20_psp_1_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})) + conv_s2u_5_6(conv_u2s_3_5(readslicef_4_3_1((conv_u2u_3_4({((acc_20_psp_1_sva[11])
+      & (~ (ACC1_acc_424_itm[2])) & (ACC1_acc_424_itm[1])) , (ACC1_acc_224_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_3_4({(acc_psp_2_sva[3]) , (ACC1_acc_224_psp_1_sva[2]) ,
+      (ACC1_1_acc_25_psp_sva[2])})))) + conv_s2s_3_5({(ACC1_acc_223_psp_sva[2:1])
+      , (ACC1_acc_224_psp_1_sva[3])})))) + conv_s2s_7_9(conv_s2s_6_7(conv_s2s_4_6(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_s2s_3_5({(ACC1_acc_220_psp_1_sva[2:1]) , (ACC1_acc_377_itm[2])}))))
+      + conv_u2s_4_6({(ACC1_acc_224_psp_1_sva[4]) , (ACC1_acc_224_psp_sva[3]) , (signext_2_1(ACC1_acc_224_psp_sva[11]))}))
+      + conv_s2s_6_7(conv_u2s_4_6({(acc_psp_2_sva[7]) , (acc_psp_2_sva[4]) , (signext_2_1(ACC1_acc_228_psp_sva[6]))})
+      + conv_s2s_3_6(conv_s2s_2_3(ACC1_acc_220_psp_sva[2:1]) + conv_s2s_2_3(ACC1_acc_222_psp_sva[2:1])))))
+      + conv_u2s_9_10({(acc_20_psp_1_sva[9]) , 1'b0 , (acc_20_psp_1_sva[9]) , 1'b0
+      , (acc_20_psp_1_sva[9]) , (ACC1_acc_228_psp_sva[4]) , 1'b0 , (signext_2_1(ACC1_acc_224_psp_sva[6]))}))
+      + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_4_10(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[8])
+      + conv_u2u_1_2(acc_psp_1_sva[8])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[7]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[7])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[7]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[7])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[8]))
+      + conv_u2u_1_4(acc_psp_2_sva[8])) * 10'b1010101))) + conv_u2s_12_14(conv_u2s_24_13(conv_u2u_4_12(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[10])
+      + conv_u2u_1_2(acc_psp_1_sva[10])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[9]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[9])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[9]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[9])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[10]))
+      + conv_u2u_1_4(acc_psp_2_sva[10])) * 12'b101010101));
+  assign nl_ACC1_acc_661_itm_1  = conv_s2s_13_14(conv_s2s_12_13({(ACC1_acc_226_psp_sva[11])
+      , 1'b0 , (ACC1_acc_226_psp_sva[11]) , 7'b0 , (ACC1_acc_226_psp_sva[11]) , (acc_psp_1_sva[2])})
+      + conv_u2s_12_13({conv_u2u_18_9(conv_u2u_3_9(conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_224_psp_sva[10])
+      + conv_u2u_1_2(ACC1_acc_228_psp_sva[10])) + conv_u2u_1_2(ACC1_acc_226_psp_sva[10]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[10])) * 9'b1010101) , (acc_psp_1_sva[4])
+      , (signext_2_1(ACC1_acc_224_psp_sva[4]))})) + conv_s2s_13_14(conv_s2s_26_13(conv_u2s_2_13((conv_u2u_1_2(ACC1_acc_227_psp_sva[11])
+      + conv_u2u_1_2(acc_psp_1_sva[11])) + conv_u2u_1_2(acc_psp_2_sva[11])) * 13'b1110010101001));
+  assign nl_ACC1_acc_652_itm_1  = conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[4])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[3])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_405_itm[2])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_3_acc_212_psp_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[5]) , (ACC1_3_acc_212_psp_sva[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_3_acc_212_psp_sva[1])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[9]) , ((ACC1_acc_226_psp_sva[11])
+      & (~ (ACC1_acc_387_itm[2])) & (ACC1_acc_387_itm[1]))})))))))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (~((ACC1_acc_387_itm[2])
+      & (~ (ACC1_acc_226_psp_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11]) , (ACC1_acc_386_itm[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11]) , (ACC1_acc_384_itm[4])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[5])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_384_itm[3])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (ACC1_acc_384_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , ((ACC1_acc_228_psp_sva[11])
+      & (~ (ACC1_acc_378_itm[2])) & (ACC1_acc_378_itm[1]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (~((ACC1_acc_378_itm[2])
+      & (~ (ACC1_acc_228_psp_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_375_itm[4])})))))))))
+      + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_375_itm[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , (ACC1_acc_375_itm[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ((ACC1_acc_224_psp_sva[11])
+      & (~ (ACC1_acc_415_itm[2])) & (ACC1_acc_415_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~((ACC1_acc_415_itm[2])
+      & (~ (ACC1_acc_224_psp_sva[11]))))}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_414_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_412_itm[4])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[5]) , (ACC1_acc_412_itm[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_412_itm[2])}))))))))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_227_psp_sva[3])
+      , (ACC1_acc_227_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(acc_psp_1_sva[3]) , (ACC1_acc_227_psp_sva[2])
+      , ((acc_psp_1_sva[11]) & (~ (ACC1_acc_396_itm[2])) & (ACC1_acc_396_itm[1]))}))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_224_psp_sva[2]) ,
+      (ACC1_acc_227_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[2])
+      , (ACC1_acc_227_psp_sva[4]) , (~((ACC1_acc_396_itm[2]) & (~ (acc_psp_1_sva[11]))))})))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_226_psp_sva[2])
+      , (acc_psp_1_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_224_psp_1_sva[2]) ,
+      (acc_psp_1_sva[3]) , (ACC1_acc_395_itm[2])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_1_acc_25_psp_sva[3])
+      , (acc_psp_1_sva[4]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[1]) , (ACC1_acc_224_psp_sva[1])
+      , (ACC1_acc_210_psp_1_sva[3])})))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[2])
+      , (ACC1_acc_224_psp_sva[2]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[3])
+      , (ACC1_acc_224_psp_sva[3]) , (ACC1_acc_210_psp_1_sva[2])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[4])
+      , (ACC1_acc_228_psp_sva[0]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[1])
+      , (ACC1_acc_226_psp_sva[0]) , (ACC1_acc_210_psp_1_sva[1])}))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[2])
+      , (ACC1_acc_226_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[3])
+      , (ACC1_acc_226_psp_sva[2]) , (ACC1_1_acc_25_psp_sva[4])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_423_itm[2])
+      , (ACC1_acc_226_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(~((ACC1_acc_424_itm[2])
+      & (~ (acc_20_psp_1_sva[11])))) , (ACC1_acc_224_psp_1_sva[0]) , (ACC1_1_acc_25_psp_sva[3])})))))))))
+      + conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_3_4({(acc_20_psp_1_sva[6]) , 1'b0 ,
+      (acc_20_psp_1_sva[6])}) + conv_u2u_3_4({(acc_psp_1_sva[7]) , (acc_20_psp_1_sva[5])
+      , (ACC1_acc_226_psp_sva[4])})) , (conv_u2u_2_3({(acc_20_psp_1_sva[6]) , (ACC1_acc_228_psp_sva[1])})
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[10])))}) + conv_u2u_7_8({(conv_u2u_3_4({(ACC1_acc_224_psp_sva[6])
+      , (acc_20_psp_1_sva[7]) , (ACC1_acc_226_psp_sva[6])}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[6])
+      , 1'b0 , (ACC1_acc_227_psp_sva[5])})) , ACC1_acc_724_cse}))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_1_2(ACC1_acc_226_psp_sva[6])
+      + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[6])) , (conv_u2u_1_2(ACC1_acc_227_psp_sva[7])
+      + conv_u2u_1_2(acc_psp_1_sva[5])) , ACC1_acc_724_cse}) + conv_u2u_7_8({(conv_u2u_1_2(ACC1_1_acc_25_psp_sva[7])
+      + conv_u2u_1_2(acc_psp_2_sva[7])) , (conv_u2u_1_2(acc_psp_1_sva[7]) + conv_u2u_1_2(ACC1_acc_224_psp_sva[4]))
+      , ACC1_acc_724_cse})) + conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_227_psp_sva[11])
+      , (signext_2_1(ACC1_acc_227_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_1_sva[11])
+      , (signext_2_1(acc_psp_1_sva[11]))}))))) + conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_sva[11])
+      , (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_228_psp_sva[11])
+      , (signext_2_1(ACC1_acc_228_psp_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(acc_20_psp_1_sva[11])
+      , 1'b0 , (signext_2_1(acc_20_psp_1_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_20_psp_1_sva[11])
+      , (signext_2_1(acc_20_psp_1_sva[11]))})))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_acc_226_psp_sva[11])
+      , 1'b0 , (signext_2_1(ACC1_acc_226_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_1_sva[11])
+      , (signext_2_1(ACC1_acc_224_psp_1_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b0 , (signext_2_1(ACC1_1_acc_25_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})))));
+  assign nl_ACC1_acc_655_itm_1  = conv_s2s_11_12(conv_u2s_10_11({(acc_20_psp_1_sva[10])
+      , 1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10])
+      , 1'b0 , (acc_20_psp_1_sva[10]) , (ACC1_acc_228_psp_sva[3])}) + conv_s2s_9_11(conv_s2s_8_9(({7'b1011011
+      , (ACC1_1_acc_25_psp_sva[1])}) + conv_u2s_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse)
+      + conv_u2u_3_4(ACC1_acc_509_cse)) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[5]))) + conv_u2u_3_4(ACC1_acc_506_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+      + conv_u2u_3_4(ACC1_acc_502_cse)))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+      + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[7]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[9]))
+      + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))))) + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+      + conv_u2u_4_5(ACC1_acc_562_ncse))))) + conv_u2s_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_502_cse)
+      + conv_u2u_3_4(ACC1_acc_506_cse)) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+      + conv_u2u_3_4(ACC1_acc_489_cse))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[6]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[8]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[10]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_u2u_4_5(ACC1_acc_553_ncse)))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_553_ncse) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_489_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[9]) , ACC1_1_and_3_cse_sva}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_338_itm[2])})))))))))
+      + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[1])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[9]) , (acc_psp_2_sva[4])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (acc_psp_2_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (acc_psp_2_sva[1])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , ((ACC1_acc_227_psp_sva[11])
+      & (~ (ACC1_acc_406_itm[2])) & (ACC1_acc_406_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[6])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[8]) , (~((ACC1_acc_406_itm[2])
+      & (~ (ACC1_acc_227_psp_sva[11]))))})))))))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[10])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , ((ACC1_1_acc_25_psp_sva[11])
+      & (~ (ACC1_acc_368_itm[2])) & (ACC1_acc_368_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (~((ACC1_acc_368_itm[2])
+      & (~ (ACC1_1_acc_25_psp_sva[11]))))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_acc_367_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_1_acc_208_psp_sva[3])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[4]) , (ACC1_1_acc_208_psp_sva[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_1_acc_208_psp_sva[1])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (~((ACC1_acc_349_itm[2])
+      & (~ (ACC1_acc_224_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[9]) , (ACC1_acc_348_itm[2])}))))))))))))
+      + conv_u2s_10_12(conv_u2u_8_10((conv_u2u_7_8({(acc_20_psp_1_sva[7]) , (ACC1_acc_227_psp_sva[7])
+      , 1'b0 , (ACC1_acc_224_psp_sva[6]) , 1'b0 , (signext_2_1(ACC1_acc_224_psp_sva[11]))})
+      + conv_u2u_6_8(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[10]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+      + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_516_cse) + conv_u2u_3_4(ACC1_acc_516_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+      + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))))))) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_412_itm[4])) , (~ (ACC1_acc_423_itm[3])) , (~ (ACC1_acc_338_itm[3]))})
+      + conv_u2u_3_4({(~ (ACC1_acc_375_itm[4])) , 1'b1 , (~ (ACC1_acc_395_itm[3]))}))
+      + conv_u2u_4_5({(readslicef_3_2_1((conv_u2u_2_3({(~ (ACC1_acc_384_itm[4]))
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_3_acc_212_psp_sva[3])) , 1'b1})))) , (({1'b1
+      , (~ (ACC1_acc_414_itm[3]))}) + ({1'b1 , (~ (ACC1_acc_377_itm[3]))}))})) +
+      conv_u2u_5_6(conv_u2u_4_5({(readslicef_3_2_1((conv_u2u_2_3({(~ (ACC1_acc_346_itm[4]))
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_208_psp_sva[3])) , 1'b1})))) , (({1'b1
+      , (~ (ACC1_acc_386_itm[3]))}) + ({1'b1 , (~ (ACC1_acc_405_itm[3]))}))}) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_210_psp_2_sva[3])) , 1'b1 , (~ (ACC1_acc_348_itm[3]))}) + conv_s2u_2_4(ACC1_acc_221_psp_sva[2:1]))))
+      + conv_s2u_6_7(conv_s2s_5_6(conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_221_psp_2_sva[2:1])
+      + conv_u2s_2_4(signext_2_1(ACC1_acc_228_psp_sva[8]))) + conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_219_psp_2_sva[2:1])
+      + conv_u2s_2_4(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_s2s_5_6(conv_s2s_4_5(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_s2s_3_5({(ACC1_acc_222_psp_1_sva[2:1]) , (acc_psp_2_sva[2])}))))
+      + conv_s2s_4_5(readslicef_5_4_1((conv_s2s_3_5({(ACC1_acc_219_psp_1_sva[2:1])
+      , 1'b1}) + conv_u2s_3_5(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , ((ACC1_acc_224_psp_1_sva[11])
+      & (~ (ACC1_acc_349_itm[2])) & (ACC1_acc_349_itm[1]))}))))))))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[6])
+      + conv_u2u_1_2(acc_psp_1_sva[6])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[5]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[5])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[5]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[5])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[6]))
+      + conv_u2u_1_4(acc_psp_2_sva[6])) * 8'b10101)) + conv_u2u_8_9({(acc_20_psp_1_sva[8])
+      , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0 , (acc_20_psp_1_sva[8])
+      , (ACC1_acc_228_psp_sva[2])})));
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [2:0] signext_3_2;
+    input [1:0] vector;
+  begin
+    signext_3_2= {{1{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_3;
+    input [2:0] vector;
+  begin
+    signext_7_3= {{4{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_4;
+    input [3:0] vector;
+  begin
+    signext_7_4= {{3{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_7_10 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_10 = {{3{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [14:0] conv_s2s_14_15 ;
+    input signed [13:0]  vector ;
+  begin
+    conv_s2s_14_15 = {vector[13], vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_13_14 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_14 = {vector[12], vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_2_14 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_14 = {{12{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_4_8 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_8 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_1_4 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_4 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_6_8 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_8 = {{2{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_9_10 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_10 = {vector[8], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_s2u_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2u_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_3_6 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_6 = {{3{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_4_10 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_10 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_24_13 ;
+    input [23:0]  vector ;
+  begin
+    conv_u2s_24_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_4_12 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_12 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_26_13 ;
+    input signed [25:0]  vector ;
+  begin
+    conv_s2s_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_9_11 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_11 = {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_8_9 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_9 = {vector[7], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_s2u_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2u_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_s2u_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2u_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/Sobel Quartus/sobel.v.bak b/Sobel/Sobel Quartus/sobel.v.bak
new file mode 100644
index 0000000..75c0023
--- /dev/null
+++ b/Sobel/Sobel Quartus/sobel.v.bak
@@ -0,0 +1,565 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 13:49:49 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [89:0] regs_regs_1_sva;
+  reg [9:0] ACC1_slc_regs_regs_2_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_9_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_10_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_11_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_12_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_13_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_14_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_15_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_16_itm;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  wire [11:0] nl_reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  reg [3:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_1;
+  reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_2;
+  reg reg_vout_rsc_mgc_out_stdreg_d_tmp_3;
+  reg [8:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_4;
+  reg reg_vout_rsc_mgc_out_stdreg_d_tmp_5;
+  wire [12:0] ACC1_acc_psp_sva;
+  wire [13:0] nl_ACC1_acc_psp_sva;
+  wire [6:0] FRAME_acc_41_sdt;
+  wire [7:0] nl_FRAME_acc_41_sdt;
+  wire [11:0] FRAME_acc_psp;
+  wire [12:0] nl_FRAME_acc_psp;
+  wire [11:0] FRAME_acc_24_sdt;
+  wire [12:0] nl_FRAME_acc_24_sdt;
+  wire [11:0] FRAME_acc_61_psp;
+  wire [12:0] nl_FRAME_acc_61_psp;
+  wire [11:0] FRAME_acc_37_sdt;
+  wire [12:0] nl_FRAME_acc_37_sdt;
+  wire [4:0] FRAME_acc_47_psp;
+  wire [5:0] nl_FRAME_acc_47_psp;
+  wire [5:0] FRAME_acc_13_sdt;
+  wire [6:0] nl_FRAME_acc_13_sdt;
+  wire [12:0] ACC1_acc_43_psp_sva;
+  wire [13:0] nl_ACC1_acc_43_psp_sva;
+  wire [4:0] FRAME_acc_55_psp;
+  wire [5:0] nl_FRAME_acc_55_psp;
+  wire [5:0] FRAME_acc_31_sdt;
+  wire [6:0] nl_FRAME_acc_31_sdt;
+  wire [12:0] ACC1_acc_42_psp_sva;
+  wire [13:0] nl_ACC1_acc_42_psp_sva;
+  wire [4:0] FRAME_acc_49_psp;
+  wire [5:0] nl_FRAME_acc_49_psp;
+  wire [5:0] FRAME_acc_18_sdt;
+  wire [6:0] nl_FRAME_acc_18_sdt;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign vout_rsc_mgc_out_stdreg_d = {reg_vout_rsc_mgc_out_stdreg_d_tmp , reg_vout_rsc_mgc_out_stdreg_d_tmp_1
+      , reg_vout_rsc_mgc_out_stdreg_d_tmp_2 , reg_vout_rsc_mgc_out_stdreg_d_tmp_3
+      , reg_vout_rsc_mgc_out_stdreg_d_tmp_4 , reg_vout_rsc_mgc_out_stdreg_d_tmp_5};
+  assign nl_ACC1_acc_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_itm
+      , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_9_itm , 1'b1})))) , 1'b1})
+      + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[29:20]))
+      , 1'b1}) + conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[89:80])) , 1'b1})))) ,
+      1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_10_itm) +
+      conv_s2u_10_11(~ (vin_rsc_mgc_in_wire_d[59:50]))) , 1'b1});
+  assign ACC1_acc_psp_sva = nl_ACC1_acc_psp_sva[12:0];
+  assign nl_FRAME_acc_41_sdt = conv_s2s_5_7(readslicef_6_5_1((conv_s2s_5_6({1'b1
+      , (~ (ACC1_acc_psp_sva[8:6])) , 1'b1}) + conv_s2s_4_6({(FRAME_acc_47_psp[4:2])
+      , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_47_psp[1:0]) , (FRAME_acc_13_sdt[0])
+      , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_47_psp[4:2])) , (~ (FRAME_acc_47_psp[4]))})))))}))))
+      + conv_u2s_5_7(signext_5_3({(ACC1_acc_psp_sva[12]) , (ACC1_acc_psp_sva[12])
+      , (FRAME_acc_47_psp[4])}));
+  assign FRAME_acc_41_sdt = nl_FRAME_acc_41_sdt[6:0];
+  assign nl_FRAME_acc_psp = ({(conv_u2u_3_4(signext_3_1(ACC1_acc_42_psp_sva[12]))
+      + conv_u2u_2_4(signext_2_1(ACC1_acc_42_psp_sva[12]))) , (ACC1_acc_42_psp_sva[12])
+      , 1'b0 , (conv_u2u_2_4(signext_2_1(ACC1_acc_42_psp_sva[12])) + conv_u2u_3_4({(ACC1_acc_42_psp_sva[12])
+      , (ACC1_acc_42_psp_sva[12]) , (ACC1_acc_42_psp_sva[12])})) , (ACC1_acc_42_psp_sva[12])
+      , (ACC1_acc_42_psp_sva[12])}) + conv_s2u_11_12(FRAME_acc_24_sdt[11:1]);
+  assign FRAME_acc_psp = nl_FRAME_acc_psp[11:0];
+  assign nl_FRAME_acc_24_sdt = conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(signext_2_1(ACC1_acc_42_psp_sva[12]))
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_42_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_42_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (FRAME_acc_49_psp[4])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_49_psp[1:0])
+      , (FRAME_acc_18_sdt[0]) , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_49_psp[4:2]))
+      , (~ (FRAME_acc_49_psp[4]))})))))}) + conv_u2u_2_4(FRAME_acc_49_psp[3:2]))
+      + conv_u2u_3_5(~ (ACC1_acc_42_psp_sva[8:6]))) + ({4'b1001 , (FRAME_acc_49_psp[4])}))));
+  assign FRAME_acc_24_sdt = nl_FRAME_acc_24_sdt[11:0];
+  assign nl_FRAME_acc_61_psp = ({(conv_u2u_3_4(signext_3_1(ACC1_acc_43_psp_sva[12]))
+      + conv_u2u_2_4(signext_2_1(ACC1_acc_43_psp_sva[12]))) , (ACC1_acc_43_psp_sva[12])
+      , 1'b0 , (conv_u2u_2_4(signext_2_1(ACC1_acc_43_psp_sva[12])) + conv_u2u_3_4({(ACC1_acc_43_psp_sva[12])
+      , (ACC1_acc_43_psp_sva[12]) , (ACC1_acc_43_psp_sva[12])})) , (ACC1_acc_43_psp_sva[12])
+      , (ACC1_acc_43_psp_sva[12])}) + conv_s2u_11_12(FRAME_acc_37_sdt[11:1]);
+  assign FRAME_acc_61_psp = nl_FRAME_acc_61_psp[11:0];
+  assign nl_FRAME_acc_37_sdt = conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(signext_2_1(ACC1_acc_43_psp_sva[12]))
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_43_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_43_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (FRAME_acc_55_psp[4])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_55_psp[1:0])
+      , (FRAME_acc_31_sdt[0]) , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_55_psp[4:2]))
+      , (~ (FRAME_acc_55_psp[4]))})))))}) + conv_u2u_2_4(FRAME_acc_55_psp[3:2]))
+      + conv_u2u_3_5(~ (ACC1_acc_43_psp_sva[8:6]))) + ({4'b1001 , (FRAME_acc_55_psp[4])}))));
+  assign FRAME_acc_37_sdt = nl_FRAME_acc_37_sdt[11:0];
+  assign nl_FRAME_acc_47_psp = (FRAME_acc_13_sdt[5:1]) + 5'b10101;
+  assign FRAME_acc_47_psp = nl_FRAME_acc_47_psp[4:0];
+  assign nl_FRAME_acc_13_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_psp_sva[8:6])
+      + conv_u2u_3_4(~ (ACC1_acc_psp_sva[11:9]))) + conv_u2u_4_5({(~ (ACC1_acc_psp_sva[12]))
+      , (~ (ACC1_acc_psp_sva[5:3]))})) + conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_psp_sva[12])
+      , 1'b0 , (ACC1_acc_psp_sva[12])}) + conv_u2u_3_4(ACC1_acc_psp_sva[2:0]));
+  assign FRAME_acc_13_sdt = nl_FRAME_acc_13_sdt[5:0];
+  assign nl_ACC1_acc_43_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_14_itm
+      , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_15_itm , 1'b1})))) , 1'b1})
+      + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[9:0]))
+      , 1'b1}) + conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[69:60])) , 1'b1})))) ,
+      1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_16_itm) +
+      conv_s2u_10_11(~ (vin_rsc_mgc_in_wire_d[39:30]))) , 1'b1});
+  assign ACC1_acc_43_psp_sva = nl_ACC1_acc_43_psp_sva[12:0];
+  assign nl_FRAME_acc_55_psp = (FRAME_acc_31_sdt[5:1]) + 5'b10101;
+  assign FRAME_acc_55_psp = nl_FRAME_acc_55_psp[4:0];
+  assign nl_FRAME_acc_31_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_43_psp_sva[8:6])
+      + conv_u2u_3_4(~ (ACC1_acc_43_psp_sva[11:9]))) + conv_u2u_4_5({(~ (ACC1_acc_43_psp_sva[12]))
+      , (~ (ACC1_acc_43_psp_sva[5:3]))})) + conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_43_psp_sva[12])
+      , 1'b0 , (ACC1_acc_43_psp_sva[12])}) + conv_u2u_3_4(ACC1_acc_43_psp_sva[2:0]));
+  assign FRAME_acc_31_sdt = nl_FRAME_acc_31_sdt[5:0];
+  assign nl_ACC1_acc_42_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_11_itm
+      , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_12_itm , 1'b1})))) , 1'b1})
+      + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[19:10]))
+      , 1'b1}) + conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[79:70])) , 1'b1})))) ,
+      1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_13_itm) +
+      conv_s2u_10_11(~ (vin_rsc_mgc_in_wire_d[49:40]))) , 1'b1});
+  assign ACC1_acc_42_psp_sva = nl_ACC1_acc_42_psp_sva[12:0];
+  assign nl_FRAME_acc_49_psp = (FRAME_acc_18_sdt[5:1]) + 5'b10101;
+  assign FRAME_acc_49_psp = nl_FRAME_acc_49_psp[4:0];
+  assign nl_FRAME_acc_18_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_42_psp_sva[8:6])
+      + conv_u2u_3_4(~ (ACC1_acc_42_psp_sva[11:9]))) + conv_u2u_4_5({(~ (ACC1_acc_42_psp_sva[12]))
+      , (~ (ACC1_acc_42_psp_sva[5:3]))})) + conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_42_psp_sva[12])
+      , 1'b0 , (ACC1_acc_42_psp_sva[12])}) + conv_u2u_3_4(ACC1_acc_42_psp_sva[2:0]));
+  assign FRAME_acc_18_sdt = nl_FRAME_acc_18_sdt[5:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      ACC1_slc_regs_regs_2_14_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_15_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_16_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_11_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_12_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_13_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_9_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_10_itm <= 10'b0;
+      regs_regs_1_sva <= 90'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= 4'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= 5'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= 1'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_4 <= 9'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_5 <= 1'b0;
+    end
+    else begin
+      if ( en ) begin
+        ACC1_slc_regs_regs_2_14_itm <= regs_regs_1_sva[9:0];
+        ACC1_slc_regs_regs_2_15_itm <= regs_regs_1_sva[69:60];
+        ACC1_slc_regs_regs_2_16_itm <= regs_regs_1_sva[39:30];
+        ACC1_slc_regs_regs_2_11_itm <= regs_regs_1_sva[19:10];
+        ACC1_slc_regs_regs_2_12_itm <= regs_regs_1_sva[79:70];
+        ACC1_slc_regs_regs_2_13_itm <= regs_regs_1_sva[49:40];
+        ACC1_slc_regs_regs_2_itm <= regs_regs_1_sva[29:20];
+        ACC1_slc_regs_regs_2_9_itm <= regs_regs_1_sva[89:80];
+        ACC1_slc_regs_regs_2_10_itm <= regs_regs_1_sva[59:50];
+        regs_regs_1_sva <= vin_rsc_mgc_in_wire_d;
+        reg_vout_rsc_mgc_out_stdreg_d_tmp <= ((conv_u2u_20_10(conv_u2u_2_10(signext_2_1(ACC1_acc_psp_sva[12]))
+            * 10'b111000111) + conv_u2u_9_10(conv_u2u_18_9(conv_u2u_3_9(ACC1_acc_psp_sva[11:9])
+            * 9'b111001))) + (conv_u2s_9_10({(ACC1_acc_psp_sva[12]) , 2'b0 , (signext_6_4({(ACC1_acc_psp_sva[12])
+            , (ACC1_acc_psp_sva[5:3])}))}) + conv_s2s_8_10({(conv_s2u_4_5(FRAME_acc_41_sdt[6:3])
+            + conv_u2u_3_5(ACC1_acc_psp_sva[8:6])) , (FRAME_acc_41_sdt[2:0])})))
+            | ({7'b0 , (FRAME_acc_psp[11:9])});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= FRAME_acc_psp[8:5];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= (FRAME_acc_psp[4:0]) | ({3'b0 , (FRAME_acc_61_psp[11:10])});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= (FRAME_acc_24_sdt[0]) | (FRAME_acc_61_psp[9]);
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_4 <= FRAME_acc_61_psp[8:0];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_5 <= FRAME_acc_37_sdt[0];
+      end
+    end
+  end
+
+  function [11:0] readslicef_13_12_1;
+    input [12:0] vector;
+    reg [12:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_13_12_1 = tmp[11:0];
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [4:0] readslicef_6_5_1;
+    input [5:0] vector;
+    reg [5:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_6_5_1 = tmp[4:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [5:0] signext_6_4;
+    input [3:0] vector;
+  begin
+    signext_6_4= {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_s2u_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2u_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/Sobel Quartus/sobel_core.bsf b/Sobel/Sobel Quartus/sobel_core.bsf
new file mode 100644
index 0000000..a604827
--- /dev/null
+++ b/Sobel/Sobel Quartus/sobel_core.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 384 128)
+	(text "sobel_core" (rect 5 0 48 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 43 30 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 59 46 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "vin_rsc_mgc_in_wire_d[89..0]" (rect 0 0 122 12)(font "Arial" ))
+		(text "vin_rsc_mgc_in_wire_d[89..0]" (rect 21 75 143 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 368 32)
+		(output)
+		(text "vout_rsc_mgc_out_stdreg_d[29..0]" (rect 0 0 143 12)(font "Arial" ))
+		(text "vout_rsc_mgc_out_stdreg_d[29..0]" (rect 204 27 347 39)(font "Arial" ))
+		(line (pt 368 32)(pt 352 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 352 96)(line_width 1))
+	)
+)
diff --git a/Sobel/sobel.v1/concat_rtl.v b/Sobel/sobel.v1/concat_rtl.v
new file mode 100644
index 0000000..460927c
--- /dev/null
+++ b/Sobel/sobel.v1/concat_rtl.v
@@ -0,0 +1,1813 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 13:49:49 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [89:0] regs_regs_1_sva;
+  reg [9:0] ACC1_slc_regs_regs_2_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_9_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_10_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_11_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_12_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_13_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_14_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_15_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_16_itm;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  wire [11:0] nl_reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  reg [3:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_1;
+  reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_2;
+  reg reg_vout_rsc_mgc_out_stdreg_d_tmp_3;
+  reg [8:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_4;
+  reg reg_vout_rsc_mgc_out_stdreg_d_tmp_5;
+  wire [12:0] ACC1_acc_psp_sva;
+  wire [13:0] nl_ACC1_acc_psp_sva;
+  wire [6:0] FRAME_acc_41_sdt;
+  wire [7:0] nl_FRAME_acc_41_sdt;
+  wire [11:0] FRAME_acc_psp;
+  wire [12:0] nl_FRAME_acc_psp;
+  wire [11:0] FRAME_acc_24_sdt;
+  wire [12:0] nl_FRAME_acc_24_sdt;
+  wire [11:0] FRAME_acc_61_psp;
+  wire [12:0] nl_FRAME_acc_61_psp;
+  wire [11:0] FRAME_acc_37_sdt;
+  wire [12:0] nl_FRAME_acc_37_sdt;
+  wire [4:0] FRAME_acc_47_psp;
+  wire [5:0] nl_FRAME_acc_47_psp;
+  wire [5:0] FRAME_acc_13_sdt;
+  wire [6:0] nl_FRAME_acc_13_sdt;
+  wire [12:0] ACC1_acc_43_psp_sva;
+  wire [13:0] nl_ACC1_acc_43_psp_sva;
+  wire [4:0] FRAME_acc_55_psp;
+  wire [5:0] nl_FRAME_acc_55_psp;
+  wire [5:0] FRAME_acc_31_sdt;
+  wire [6:0] nl_FRAME_acc_31_sdt;
+  wire [12:0] ACC1_acc_42_psp_sva;
+  wire [13:0] nl_ACC1_acc_42_psp_sva;
+  wire [4:0] FRAME_acc_49_psp;
+  wire [5:0] nl_FRAME_acc_49_psp;
+  wire [5:0] FRAME_acc_18_sdt;
+  wire [6:0] nl_FRAME_acc_18_sdt;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign vout_rsc_mgc_out_stdreg_d = {reg_vout_rsc_mgc_out_stdreg_d_tmp , reg_vout_rsc_mgc_out_stdreg_d_tmp_1
+      , reg_vout_rsc_mgc_out_stdreg_d_tmp_2 , reg_vout_rsc_mgc_out_stdreg_d_tmp_3
+      , reg_vout_rsc_mgc_out_stdreg_d_tmp_4 , reg_vout_rsc_mgc_out_stdreg_d_tmp_5};
+  assign nl_ACC1_acc_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_itm
+      , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_9_itm , 1'b1})))) , 1'b1})
+      + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[29:20]))
+      , 1'b1}) + conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[89:80])) , 1'b1})))) ,
+      1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_10_itm) +
+      conv_s2u_10_11(~ (vin_rsc_mgc_in_wire_d[59:50]))) , 1'b1});
+  assign ACC1_acc_psp_sva = nl_ACC1_acc_psp_sva[12:0];
+  assign nl_FRAME_acc_41_sdt = conv_s2s_5_7(readslicef_6_5_1((conv_s2s_5_6({1'b1
+      , (~ (ACC1_acc_psp_sva[8:6])) , 1'b1}) + conv_s2s_4_6({(FRAME_acc_47_psp[4:2])
+      , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_47_psp[1:0]) , (FRAME_acc_13_sdt[0])
+      , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_47_psp[4:2])) , (~ (FRAME_acc_47_psp[4]))})))))}))))
+      + conv_u2s_5_7(signext_5_3({(ACC1_acc_psp_sva[12]) , (ACC1_acc_psp_sva[12])
+      , (FRAME_acc_47_psp[4])}));
+  assign FRAME_acc_41_sdt = nl_FRAME_acc_41_sdt[6:0];
+  assign nl_FRAME_acc_psp = ({(conv_u2u_3_4(signext_3_1(ACC1_acc_42_psp_sva[12]))
+      + conv_u2u_2_4(signext_2_1(ACC1_acc_42_psp_sva[12]))) , (ACC1_acc_42_psp_sva[12])
+      , 1'b0 , (conv_u2u_2_4(signext_2_1(ACC1_acc_42_psp_sva[12])) + conv_u2u_3_4({(ACC1_acc_42_psp_sva[12])
+      , (ACC1_acc_42_psp_sva[12]) , (ACC1_acc_42_psp_sva[12])})) , (ACC1_acc_42_psp_sva[12])
+      , (ACC1_acc_42_psp_sva[12])}) + conv_s2u_11_12(FRAME_acc_24_sdt[11:1]);
+  assign FRAME_acc_psp = nl_FRAME_acc_psp[11:0];
+  assign nl_FRAME_acc_24_sdt = conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(signext_2_1(ACC1_acc_42_psp_sva[12]))
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_42_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_42_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (FRAME_acc_49_psp[4])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_49_psp[1:0])
+      , (FRAME_acc_18_sdt[0]) , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_49_psp[4:2]))
+      , (~ (FRAME_acc_49_psp[4]))})))))}) + conv_u2u_2_4(FRAME_acc_49_psp[3:2]))
+      + conv_u2u_3_5(~ (ACC1_acc_42_psp_sva[8:6]))) + ({4'b1001 , (FRAME_acc_49_psp[4])}))));
+  assign FRAME_acc_24_sdt = nl_FRAME_acc_24_sdt[11:0];
+  assign nl_FRAME_acc_61_psp = ({(conv_u2u_3_4(signext_3_1(ACC1_acc_43_psp_sva[12]))
+      + conv_u2u_2_4(signext_2_1(ACC1_acc_43_psp_sva[12]))) , (ACC1_acc_43_psp_sva[12])
+      , 1'b0 , (conv_u2u_2_4(signext_2_1(ACC1_acc_43_psp_sva[12])) + conv_u2u_3_4({(ACC1_acc_43_psp_sva[12])
+      , (ACC1_acc_43_psp_sva[12]) , (ACC1_acc_43_psp_sva[12])})) , (ACC1_acc_43_psp_sva[12])
+      , (ACC1_acc_43_psp_sva[12])}) + conv_s2u_11_12(FRAME_acc_37_sdt[11:1]);
+  assign FRAME_acc_61_psp = nl_FRAME_acc_61_psp[11:0];
+  assign nl_FRAME_acc_37_sdt = conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(signext_2_1(ACC1_acc_43_psp_sva[12]))
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_43_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_43_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (FRAME_acc_55_psp[4])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_55_psp[1:0])
+      , (FRAME_acc_31_sdt[0]) , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_55_psp[4:2]))
+      , (~ (FRAME_acc_55_psp[4]))})))))}) + conv_u2u_2_4(FRAME_acc_55_psp[3:2]))
+      + conv_u2u_3_5(~ (ACC1_acc_43_psp_sva[8:6]))) + ({4'b1001 , (FRAME_acc_55_psp[4])}))));
+  assign FRAME_acc_37_sdt = nl_FRAME_acc_37_sdt[11:0];
+  assign nl_FRAME_acc_47_psp = (FRAME_acc_13_sdt[5:1]) + 5'b10101;
+  assign FRAME_acc_47_psp = nl_FRAME_acc_47_psp[4:0];
+  assign nl_FRAME_acc_13_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_psp_sva[8:6])
+      + conv_u2u_3_4(~ (ACC1_acc_psp_sva[11:9]))) + conv_u2u_4_5({(~ (ACC1_acc_psp_sva[12]))
+      , (~ (ACC1_acc_psp_sva[5:3]))})) + conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_psp_sva[12])
+      , 1'b0 , (ACC1_acc_psp_sva[12])}) + conv_u2u_3_4(ACC1_acc_psp_sva[2:0]));
+  assign FRAME_acc_13_sdt = nl_FRAME_acc_13_sdt[5:0];
+  assign nl_ACC1_acc_43_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_14_itm
+      , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_15_itm , 1'b1})))) , 1'b1})
+      + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[9:0]))
+      , 1'b1}) + conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[69:60])) , 1'b1})))) ,
+      1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_16_itm) +
+      conv_s2u_10_11(~ (vin_rsc_mgc_in_wire_d[39:30]))) , 1'b1});
+  assign ACC1_acc_43_psp_sva = nl_ACC1_acc_43_psp_sva[12:0];
+  assign nl_FRAME_acc_55_psp = (FRAME_acc_31_sdt[5:1]) + 5'b10101;
+  assign FRAME_acc_55_psp = nl_FRAME_acc_55_psp[4:0];
+  assign nl_FRAME_acc_31_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_43_psp_sva[8:6])
+      + conv_u2u_3_4(~ (ACC1_acc_43_psp_sva[11:9]))) + conv_u2u_4_5({(~ (ACC1_acc_43_psp_sva[12]))
+      , (~ (ACC1_acc_43_psp_sva[5:3]))})) + conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_43_psp_sva[12])
+      , 1'b0 , (ACC1_acc_43_psp_sva[12])}) + conv_u2u_3_4(ACC1_acc_43_psp_sva[2:0]));
+  assign FRAME_acc_31_sdt = nl_FRAME_acc_31_sdt[5:0];
+  assign nl_ACC1_acc_42_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_11_itm
+      , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_12_itm , 1'b1})))) , 1'b1})
+      + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[19:10]))
+      , 1'b1}) + conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[79:70])) , 1'b1})))) ,
+      1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_13_itm) +
+      conv_s2u_10_11(~ (vin_rsc_mgc_in_wire_d[49:40]))) , 1'b1});
+  assign ACC1_acc_42_psp_sva = nl_ACC1_acc_42_psp_sva[12:0];
+  assign nl_FRAME_acc_49_psp = (FRAME_acc_18_sdt[5:1]) + 5'b10101;
+  assign FRAME_acc_49_psp = nl_FRAME_acc_49_psp[4:0];
+  assign nl_FRAME_acc_18_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_42_psp_sva[8:6])
+      + conv_u2u_3_4(~ (ACC1_acc_42_psp_sva[11:9]))) + conv_u2u_4_5({(~ (ACC1_acc_42_psp_sva[12]))
+      , (~ (ACC1_acc_42_psp_sva[5:3]))})) + conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_42_psp_sva[12])
+      , 1'b0 , (ACC1_acc_42_psp_sva[12])}) + conv_u2u_3_4(ACC1_acc_42_psp_sva[2:0]));
+  assign FRAME_acc_18_sdt = nl_FRAME_acc_18_sdt[5:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      ACC1_slc_regs_regs_2_14_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_15_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_16_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_11_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_12_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_13_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_9_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_10_itm <= 10'b0;
+      regs_regs_1_sva <= 90'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= 4'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= 5'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= 1'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_4 <= 9'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_5 <= 1'b0;
+    end
+    else begin
+      if ( en ) begin
+        ACC1_slc_regs_regs_2_14_itm <= regs_regs_1_sva[9:0];
+        ACC1_slc_regs_regs_2_15_itm <= regs_regs_1_sva[69:60];
+        ACC1_slc_regs_regs_2_16_itm <= regs_regs_1_sva[39:30];
+        ACC1_slc_regs_regs_2_11_itm <= regs_regs_1_sva[19:10];
+        ACC1_slc_regs_regs_2_12_itm <= regs_regs_1_sva[79:70];
+        ACC1_slc_regs_regs_2_13_itm <= regs_regs_1_sva[49:40];
+        ACC1_slc_regs_regs_2_itm <= regs_regs_1_sva[29:20];
+        ACC1_slc_regs_regs_2_9_itm <= regs_regs_1_sva[89:80];
+        ACC1_slc_regs_regs_2_10_itm <= regs_regs_1_sva[59:50];
+        regs_regs_1_sva <= vin_rsc_mgc_in_wire_d;
+        reg_vout_rsc_mgc_out_stdreg_d_tmp <= ((conv_u2u_20_10(conv_u2u_2_10(signext_2_1(ACC1_acc_psp_sva[12]))
+            * 10'b111000111) + conv_u2u_9_10(conv_u2u_18_9(conv_u2u_3_9(ACC1_acc_psp_sva[11:9])
+            * 9'b111001))) + (conv_u2s_9_10({(ACC1_acc_psp_sva[12]) , 2'b0 , (signext_6_4({(ACC1_acc_psp_sva[12])
+            , (ACC1_acc_psp_sva[5:3])}))}) + conv_s2s_8_10({(conv_s2u_4_5(FRAME_acc_41_sdt[6:3])
+            + conv_u2u_3_5(ACC1_acc_psp_sva[8:6])) , (FRAME_acc_41_sdt[2:0])})))
+            | ({7'b0 , (FRAME_acc_psp[11:9])});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= FRAME_acc_psp[8:5];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= (FRAME_acc_psp[4:0]) | ({3'b0 , (FRAME_acc_61_psp[11:10])});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= (FRAME_acc_24_sdt[0]) | (FRAME_acc_61_psp[9]);
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_4 <= FRAME_acc_61_psp[8:0];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_5 <= FRAME_acc_37_sdt[0];
+      end
+    end
+  end
+
+  function [11:0] readslicef_13_12_1;
+    input [12:0] vector;
+    reg [12:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_13_12_1 = tmp[11:0];
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [4:0] readslicef_6_5_1;
+    input [5:0] vector;
+    reg [5:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_6_5_1 = tmp[4:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [5:0] signext_6_4;
+    input [3:0] vector;
+  begin
+    signext_6_4= {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_s2u_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2u_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v1/cycle.rpt b/Sobel/sobel.v1/cycle.rpt
new file mode 100644
index 0000000..39140c4
--- /dev/null
+++ b/Sobel/sobel.v1/cycle.rpt
@@ -0,0 +1,85 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 13:49:35 +0000 2016                      
+
+Solution Settings: sobel.v1
+  Current state: schedule
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       105  307200     307200            0  1          
+    Design Total:                     105  307200     307200            0  0          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /sobel/core              
+    
+  I/O Data Ranges
+    Port       Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ---------- ---- -------- --------- --------- ------- -------- --------
+    vin:rsc.z  IN   Unsigned        90                                     
+    clk        IN   Unsigned         1                                     
+    en         IN   Unsigned         1                                     
+    arst_n     IN   Unsigned         1                                     
+    vout:rsc.z OUT  Unsigned        30                                     
+    
+  Memory Resources
+    Resource Name: /sobel/vin:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 90
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable   Indices Phys Memory Address     
+      ---------- ------- -----------------------
+      /sobel/vin    0:89 00000000-00000000 (0-0) 
+      
+    Resource Name: /sobel/vout:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 30
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable    Indices Phys Memory Address     
+      ----------- ------- -----------------------
+      /sobel/vout    0:29 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process     Loop             Iterations C-Steps Total Cycles  Duration  Unroll Init Comments 
+    ----------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
+    /sobel/core core:rlp           Infinite       0       307201   6.14 ms                       
+    /sobel/core   main             Infinite       2       307201   6.14 ms            1          
+    
+  Loop Execution Profile
+    Process     Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------- ---------------- ------------ -------------------------- ----------------- --------
+    /sobel/core core:rlp                   0                        0.00           307200           
+    /sobel/core   main                307201                      100.00           307200           
+    
+  End of Report
diff --git a/Sobel/sobel.v1/cycle.v b/Sobel/sobel.v1/cycle.v
new file mode 100644
index 0000000..b4faa60
--- /dev/null
+++ b/Sobel/sobel.v1/cycle.v
@@ -0,0 +1,602 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 13:49:35 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg [89:0] regs_regs_1_sva;
+    reg [89:0] regs_regs_0_sva;
+    reg [89:0] regs_regs_0_sva_1;
+    reg [12:0] ACC1_acc_psp_sva;
+    reg [12:0] ACC1_acc_42_psp_sva;
+    reg [12:0] ACC1_acc_43_psp_sva;
+    reg [9:0] ACC1_slc_regs_regs_2_itm;
+    reg [9:0] ACC1_slc_regs_regs_2_9_itm;
+    reg [9:0] ACC1_slc_regs_regs_2_10_itm;
+    reg [9:0] ACC1_slc_regs_regs_2_11_itm;
+    reg [9:0] ACC1_slc_regs_regs_2_12_itm;
+    reg [9:0] ACC1_slc_regs_regs_2_13_itm;
+    reg [9:0] ACC1_slc_regs_regs_2_14_itm;
+    reg [9:0] ACC1_slc_regs_regs_2_15_itm;
+    reg [9:0] ACC1_slc_regs_regs_2_16_itm;
+    reg [5:0] FRAME_acc_13_sdt;
+    reg [5:0] FRAME_acc_18_sdt;
+    reg [11:0] FRAME_acc_24_sdt;
+    reg [5:0] FRAME_acc_31_sdt;
+    reg [11:0] FRAME_acc_37_sdt;
+    reg [6:0] FRAME_acc_41_sdt;
+    reg [4:0] FRAME_acc_49_psp;
+    reg [4:0] FRAME_acc_55_psp;
+    reg [4:0] FRAME_acc_47_psp;
+    reg [11:0] FRAME_acc_psp;
+    reg [11:0] FRAME_acc_61_psp;
+
+    begin : core_rlpExit
+      forever begin : core_rlp
+        // C-Step 0 of Loop 'core_rlp'
+        regs_regs_1_sva = 90'b0;
+        regs_regs_0_sva = 90'b0;
+        begin : mainExit
+          forever begin : main
+            // C-Step 0 of Loop 'main'
+            ACC1_slc_regs_regs_2_itm = regs_regs_1_sva[29:20];
+            ACC1_slc_regs_regs_2_9_itm = regs_regs_1_sva[89:80];
+            ACC1_slc_regs_regs_2_10_itm = regs_regs_1_sva[59:50];
+            ACC1_slc_regs_regs_2_11_itm = regs_regs_1_sva[19:10];
+            ACC1_slc_regs_regs_2_12_itm = regs_regs_1_sva[79:70];
+            ACC1_slc_regs_regs_2_13_itm = regs_regs_1_sva[49:40];
+            ACC1_slc_regs_regs_2_14_itm = regs_regs_1_sva[9:0];
+            ACC1_slc_regs_regs_2_15_itm = regs_regs_1_sva[69:60];
+            ACC1_slc_regs_regs_2_16_itm = regs_regs_1_sva[39:30];
+            regs_regs_1_sva = regs_regs_0_sva;
+            begin : waitLoop0Exit
+              forever begin : waitLoop0
+                @(posedge clk or negedge ( arst_n ));
+                if ( ~ arst_n )
+                  disable core_rlpExit;
+                if ( en )
+                  disable waitLoop0Exit;
+              end
+            end
+            // C-Step 1 of Loop 'main'
+            regs_regs_0_sva_1 = vin_rsc_mgc_in_wire_d;
+            ACC1_acc_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_itm
+                , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_9_itm , 1'b1}))))
+                , 1'b1}) + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~
+                (regs_regs_0_sva_1[29:20])) , 1'b1}) + conv_s2s_11_12({(~ (regs_regs_0_sva_1[89:80]))
+                , 1'b1})))) , 1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_10_itm)
+                + conv_s2u_10_11(~ (regs_regs_0_sva_1[59:50]))) , 1'b1});
+            ACC1_acc_42_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_11_itm
+                , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_12_itm , 1'b1}))))
+                , 1'b1}) + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~
+                (regs_regs_0_sva_1[19:10])) , 1'b1}) + conv_s2s_11_12({(~ (regs_regs_0_sva_1[79:70]))
+                , 1'b1})))) , 1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_13_itm)
+                + conv_s2u_10_11(~ (regs_regs_0_sva_1[49:40]))) , 1'b1});
+            ACC1_acc_43_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_14_itm
+                , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_15_itm , 1'b1}))))
+                , 1'b1}) + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~
+                (regs_regs_0_sva_1[9:0])) , 1'b1}) + conv_s2s_11_12({(~ (regs_regs_0_sva_1[69:60]))
+                , 1'b1})))) , 1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_16_itm)
+                + conv_s2u_10_11(~ (regs_regs_0_sva_1[39:30]))) , 1'b1});
+            FRAME_acc_13_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_psp_sva[8:6])
+                + conv_u2u_3_4(~ (ACC1_acc_psp_sva[11:9]))) + conv_u2u_4_5({(~ (ACC1_acc_psp_sva[12]))
+                , (~ (ACC1_acc_psp_sva[5:3]))})) + conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_psp_sva[12])
+                , 1'b0 , (ACC1_acc_psp_sva[12])}) + conv_u2u_3_4(ACC1_acc_psp_sva[2:0]));
+            FRAME_acc_47_psp = (FRAME_acc_13_sdt[5:1]) + 5'b10101;
+            FRAME_acc_18_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_42_psp_sva[8:6])
+                + conv_u2u_3_4(~ (ACC1_acc_42_psp_sva[11:9]))) + conv_u2u_4_5({(~
+                (ACC1_acc_42_psp_sva[12])) , (~ (ACC1_acc_42_psp_sva[5:3]))})) +
+                conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_42_psp_sva[12]) , 1'b0 , (ACC1_acc_42_psp_sva[12])})
+                + conv_u2u_3_4(ACC1_acc_42_psp_sva[2:0]));
+            FRAME_acc_49_psp = (FRAME_acc_18_sdt[5:1]) + 5'b10101;
+            FRAME_acc_24_sdt = conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(signext_2_1(ACC1_acc_42_psp_sva[12]))
+                * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_42_psp_sva[11:9])
+                * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_42_psp_sva[8:3])
+                + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~ (FRAME_acc_49_psp[4]))
+                , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_49_psp[1:0]) ,
+                (FRAME_acc_18_sdt[0]) , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_49_psp[4:2]))
+                , (~ (FRAME_acc_49_psp[4]))})))))}) + conv_u2u_2_4(FRAME_acc_49_psp[3:2]))
+                + conv_u2u_3_5(~ (ACC1_acc_42_psp_sva[8:6]))) + ({4'b1001 , (FRAME_acc_49_psp[4])}))));
+            FRAME_acc_psp = conv_u2u_8_12({(ACC1_acc_42_psp_sva[12]) , 5'b0 , (signext_2_1(ACC1_acc_42_psp_sva[12]))})
+                + conv_u2u_10_12(signext_10_9({(ACC1_acc_42_psp_sva[12]) , 3'b0 ,
+                (signext_3_1(ACC1_acc_42_psp_sva[12])) , 2'b0})) + conv_s2u_11_12(FRAME_acc_24_sdt[11:1])
+                + conv_u2u_11_12(signext_11_9({(ACC1_acc_42_psp_sva[12]) , 4'b0 ,
+                (signext_2_1(ACC1_acc_42_psp_sva[12])) , 2'b0}));
+            FRAME_acc_31_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_43_psp_sva[8:6])
+                + conv_u2u_3_4(~ (ACC1_acc_43_psp_sva[11:9]))) + conv_u2u_4_5({(~
+                (ACC1_acc_43_psp_sva[12])) , (~ (ACC1_acc_43_psp_sva[5:3]))})) +
+                conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_43_psp_sva[12]) , 1'b0 , (ACC1_acc_43_psp_sva[12])})
+                + conv_u2u_3_4(ACC1_acc_43_psp_sva[2:0]));
+            FRAME_acc_55_psp = (FRAME_acc_31_sdt[5:1]) + 5'b10101;
+            FRAME_acc_37_sdt = conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(signext_2_1(ACC1_acc_43_psp_sva[12]))
+                * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_43_psp_sva[11:9])
+                * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_43_psp_sva[8:3])
+                + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~ (FRAME_acc_55_psp[4]))
+                , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_55_psp[1:0]) ,
+                (FRAME_acc_31_sdt[0]) , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_55_psp[4:2]))
+                , (~ (FRAME_acc_55_psp[4]))})))))}) + conv_u2u_2_4(FRAME_acc_55_psp[3:2]))
+                + conv_u2u_3_5(~ (ACC1_acc_43_psp_sva[8:6]))) + ({4'b1001 , (FRAME_acc_55_psp[4])}))));
+            FRAME_acc_61_psp = conv_u2u_8_12({(ACC1_acc_43_psp_sva[12]) , 5'b0 ,
+                (signext_2_1(ACC1_acc_43_psp_sva[12]))}) + conv_u2u_10_12(signext_10_9({(ACC1_acc_43_psp_sva[12])
+                , 3'b0 , (signext_3_1(ACC1_acc_43_psp_sva[12])) , 2'b0})) + conv_s2u_11_12(FRAME_acc_37_sdt[11:1])
+                + conv_u2u_11_12(signext_11_9({(ACC1_acc_43_psp_sva[12]) , 4'b0 ,
+                (signext_2_1(ACC1_acc_43_psp_sva[12])) , 2'b0}));
+            FRAME_acc_41_sdt = conv_s2s_5_7(readslicef_6_5_1((conv_s2s_5_6({1'b1
+                , (~ (ACC1_acc_psp_sva[8:6])) , 1'b1}) + conv_s2s_4_6({(FRAME_acc_47_psp[4:2])
+                , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_47_psp[1:0]) , (FRAME_acc_13_sdt[0])
+                , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_47_psp[4:2])) , (~ (FRAME_acc_47_psp[4]))})))))}))))
+                + conv_u2s_5_7(signext_5_3({(ACC1_acc_psp_sva[12]) , (ACC1_acc_psp_sva[12])
+                , (FRAME_acc_47_psp[4])}));
+            vout_rsc_mgc_out_stdreg_d <= {(((conv_u2u_20_10(conv_u2u_2_10(signext_2_1(ACC1_acc_psp_sva[12]))
+                * 10'b111000111) + conv_u2u_9_10(conv_u2u_18_9(conv_u2u_3_9(ACC1_acc_psp_sva[11:9])
+                * 9'b111001))) + (conv_u2s_9_10({(ACC1_acc_psp_sva[12]) , 2'b0 ,
+                (signext_6_4({(ACC1_acc_psp_sva[12]) , (ACC1_acc_psp_sva[5:3])}))})
+                + conv_s2s_8_10({(conv_s2u_4_5(FRAME_acc_41_sdt[6:3]) + conv_u2u_3_5(ACC1_acc_psp_sva[8:6]))
+                , (FRAME_acc_41_sdt[2:0])}))) | ({7'b0, FRAME_acc_psp[11:9]})) ,
+                (FRAME_acc_psp[8:5]) , (({(FRAME_acc_psp[4:0]) , (FRAME_acc_24_sdt[0])})
+                | ({3'b0, FRAME_acc_61_psp[11:9]})) , (FRAME_acc_61_psp[8:0]) , (FRAME_acc_37_sdt[0])};
+            regs_regs_0_sva = regs_regs_0_sva_1;
+          end
+        end
+      end
+    end
+    FRAME_acc_61_psp = 12'b0;
+    FRAME_acc_psp = 12'b0;
+    FRAME_acc_47_psp = 5'b0;
+    FRAME_acc_55_psp = 5'b0;
+    FRAME_acc_49_psp = 5'b0;
+    FRAME_acc_41_sdt = 7'b0;
+    FRAME_acc_37_sdt = 12'b0;
+    FRAME_acc_31_sdt = 6'b0;
+    FRAME_acc_24_sdt = 12'b0;
+    FRAME_acc_18_sdt = 6'b0;
+    FRAME_acc_13_sdt = 6'b0;
+    ACC1_slc_regs_regs_2_16_itm = 10'b0;
+    ACC1_slc_regs_regs_2_15_itm = 10'b0;
+    ACC1_slc_regs_regs_2_14_itm = 10'b0;
+    ACC1_slc_regs_regs_2_13_itm = 10'b0;
+    ACC1_slc_regs_regs_2_12_itm = 10'b0;
+    ACC1_slc_regs_regs_2_11_itm = 10'b0;
+    ACC1_slc_regs_regs_2_10_itm = 10'b0;
+    ACC1_slc_regs_regs_2_9_itm = 10'b0;
+    ACC1_slc_regs_regs_2_itm = 10'b0;
+    ACC1_acc_43_psp_sva = 13'b0;
+    ACC1_acc_42_psp_sva = 13'b0;
+    ACC1_acc_psp_sva = 13'b0;
+    regs_regs_0_sva_1 = 90'b0;
+    regs_regs_0_sva = 90'b0;
+    regs_regs_1_sva = 90'b0;
+    vout_rsc_mgc_out_stdreg_d <= 30'b0;
+  end
+
+
+  function [11:0] readslicef_13_12_1;
+    input [12:0] vector;
+    reg [12:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_13_12_1 = tmp[11:0];
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] signext_10_9;
+    input [8:0] vector;
+  begin
+    signext_10_9= {{1{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [4:0] readslicef_6_5_1;
+    input [5:0] vector;
+    reg [5:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_6_5_1 = tmp[4:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [5:0] signext_6_4;
+    input [3:0] vector;
+  begin
+    signext_6_4= {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_8_12 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_12 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_s2u_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2u_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v1/cycle_mgc_ioport.v b/Sobel/sobel.v1/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v1/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v1/cycle_mgc_ioport_v2001.v b/Sobel/sobel.v1/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v1/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v1/cycle_set.tcl b/Sobel/sobel.v1/cycle_set.tcl
new file mode 100644
index 0000000..1b8ebe2
--- /dev/null
+++ b/Sobel/sobel.v1/cycle_set.tcl
@@ -0,0 +1,79 @@
+
+# Loop constraints
+directive set /sobel/core/core:rlp CSTEPS_FROM {{. == 0}}
+directive set /sobel/core/core:rlp/main CSTEPS_FROM {{. == 2} {.. == 0}}
+
+# IO operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:io_read(vin:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:io_write(vout:rsc.d) CSTEPS_FROM {{.. == 1}}
+
+# Real operation constraints
+directive set /sobel/core/core:rlp/main/ACC1:acc#45 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#44 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#47 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#46 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#49 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#48 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#51 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#50 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#42 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#53 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#52 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#55 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#54 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#43 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#12 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#9 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#11 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#13 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#15 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#17 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#18 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#26 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#19 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#20 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#21 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#22 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#23 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#24 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#28 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#30 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#27 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#29 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#31 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#38 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#39 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#32 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#33 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#34 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#35 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#36 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#37 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#44 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#45 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#40 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#41 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#42 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#43 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:or CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:or#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc CSTEPS_FROM {{.. == 1}}
diff --git a/Sobel/sobel.v1/directives.tcl b/Sobel/sobel.v1/directives.tcl
new file mode 100644
index 0000000..504c4bb
--- /dev/null
+++ b/Sobel/sobel.v1/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
+go extract
diff --git a/Sobel/sobel.v1/messages.txt b/Sobel/sobel.v1/messages.txt
new file mode 100644
index 0000000..33496d1
--- /dev/null
+++ b/Sobel/sobel.v1/messages.txt
@@ -0,0 +1,232 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v1': elapsed time 2.95 seconds, memory usage 161640kB, peak memory usage 279044kB (SOL-9)
+$PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.cpp(129): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+
+# Messages from "go compile"
+
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49)
+Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'sobel' specified by directive (CIN-52)
+Synthesizing routine 'sobel' (CIN-13)
+Inlining routine 'sobel' (CIN-14)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Optimizing block '/sobel' ... (CIN-4)
+Inout port 'vin' is only used as an input. (OPT-10)
+Inout port 'vout' is only used as an output. (OPT-11)
+Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+Design 'sobel' was read (SOL-1)
+Optimizing partition '/sobel': (Total ops = 383, Real ops = 92, Vars = 82) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 383, Real ops = 92, Vars = 80) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 363, Real ops = 88, Vars = 83) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 363, Real ops = 88, Vars = 85) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 363, Real ops = 88, Vars = 85) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 363, Real ops = 88, Vars = 83) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 318, Real ops = 87, Vars = 66) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 302, Real ops = 87, Vars = 65) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 302, Real ops = 87, Vars = 65) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 302, Real ops = 87, Vars = 67) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 302, Real ops = 87, Vars = 67) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 291, Real ops = 85, Vars = 94) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 306, Real ops = 85, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 306, Real ops = 85, Vars = 23) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 306, Real ops = 85, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 306, Real ops = 85, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 306, Real ops = 85, Vars = 23) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 306, Real ops = 85, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 306, Real ops = 85, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 306, Real ops = 85, Vars = 23) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 306, Real ops = 85, Vars = 21) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 325, Real ops = 85, Vars = 21) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 272, Real ops = 81, Vars = 20) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 272, Real ops = 81, Vars = 22) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 268, Real ops = 81, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 266, Real ops = 81, Vars = 20) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 266, Real ops = 81, Vars = 22) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 266, Real ops = 81, Vars = 20) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 266, Real ops = 81, Vars = 22) (SOL-10)
+Completed transformation 'compile' on solution 'sobel.v1': elapsed time 1.64 seconds, memory usage 173676kB, peak memory usage 279044kB (SOL-9)
+Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'sobel.v1' (SOL-8)
+Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+Loop '/sobel/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/sobel/core': (Total ops = 455, Real ops = 144, Vars = 20) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 265, Real ops = 81, Vars = 14) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 262, Real ops = 81, Vars = 13) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 262, Real ops = 81, Vars = 13) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 268, Real ops = 81, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 250, Real ops = 81, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 244, Real ops = 75, Vars = 19) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 244, Real ops = 75, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 244, Real ops = 75, Vars = 19) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 244, Real ops = 75, Vars = 24) (SOL-10)
+I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+Optimizing partition '/sobel': (Total ops = 244, Real ops = 75, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 244, Real ops = 75, Vars = 19) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 244, Real ops = 75, Vars = 19) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 244, Real ops = 75, Vars = 24) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 238, Real ops = 75, Vars = 32) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 241, Real ops = 75, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 198, Real ops = 54, Vars = 12) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 199, Real ops = 56, Vars = 12) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 199, Real ops = 56, Vars = 17) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 199, Real ops = 56, Vars = 12) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 199, Real ops = 56, Vars = 17) (SOL-10)
+Design 'sobel' contains '104' real operations. (SOL-11)
+Optimizing partition '/sobel/core': (Total ops = 202, Real ops = 56, Vars = 13) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 307, Real ops = 60, Vars = 76) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 206, Real ops = 58, Vars = 16) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 205, Real ops = 58, Vars = 15) (SOL-10)
+Completed transformation 'architect' on solution 'sobel.v1': elapsed time 2.11 seconds, memory usage 174460kB, peak memory usage 279044kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'sobel.v1' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 307200, Area (Datapath, Register, Total) = 2560.33, 0.00, 2560.33 (CRAAS-11)
+Optimized LOOP 'main': Latency = 307200, Area (Datapath, Register, Total) = 2559.59, 0.00, 2559.59 (CRAAS-10)
+Optimized LOOP 'main': Latency = 307200, Area (Datapath, Register, Total) = 2531.89, 0.00, 2531.89 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 307200, Area (Datapath, Register, Total) = 2531.89, 0.00, 2531.89 (CRAAS-12)
+Completed transformation 'allocate' on solution 'sobel.v1': elapsed time 0.33 seconds, memory usage 174920kB, peak memory usage 279044kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'sobel.v1' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 332, Real ops = 105, Vars = 40) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 322, Real ops = 104, Vars = 32) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 317, Real ops = 104, Vars = 27) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 282, Real ops = 94, Vars = 26) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 296, Real ops = 94, Vars = 38) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 287, Real ops = 94, Vars = 31) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 282, Real ops = 94, Vars = 26) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 296, Real ops = 94, Vars = 38) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 287, Real ops = 94, Vars = 31) (SOL-10)
+Completed transformation 'schedule' on solution 'sobel.v1': elapsed time 0.98 seconds, memory usage 184552kB, peak memory usage 279044kB (SOL-9)
+Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'sobel.v1' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 437, Real ops = 102, Vars = 215) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 428, Real ops = 102, Vars = 208) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 526, Real ops = 104, Vars = 36) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 517, Real ops = 104, Vars = 29) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 307, Real ops = 110, Vars = 42) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 298, Real ops = 110, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 307, Real ops = 110, Vars = 42) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 298, Real ops = 110, Vars = 35) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 298, Real ops = 110, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 307, Real ops = 110, Vars = 42) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 307, Real ops = 110, Vars = 42) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 298, Real ops = 110, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 307, Real ops = 110, Vars = 42) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 298, Real ops = 110, Vars = 35) (SOL-10)
+Completed transformation 'dpfsm' on solution 'sobel.v1': elapsed time 0.33 seconds, memory usage 184552kB, peak memory usage 279044kB (SOL-9)
+
+# Messages from "go extract"
+
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'sobel.v1' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 308) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 301) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 50) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 43) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 308) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 301) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 308) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 301) (SOL-10)
+Reassigned operation FRAME:acc:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,11,1,12) (ASG-1)
+Reassigned operation FRAME:acc#61:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,11,1,12) (ASG-1)
+Reassigned operation FRAME:acc#47:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5) (ASG-1)
+Reassigned operation FRAME:acc#55:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5) (ASG-1)
+Reassigned operation FRAME:acc#49:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5) (ASG-1)
+Reassigned operation FRAME:acc#60:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add_pipe(16,1,16,0,17,1,1,0,0,0,2,0,0,0) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,3,0,5) (ASG-1)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 308) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 301) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 48) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 41) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+Completed transformation 'extract' on solution 'sobel.v1': elapsed time 3.39 seconds, memory usage 184552kB, peak memory usage 279044kB (SOL-9)
diff --git a/Sobel/sobel.v1/reg_sharing.tcl b/Sobel/sobel.v1/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v1/reg_sharing.tcl
diff --git a/Sobel/sobel.v1/res_sharing.tcl b/Sobel/sobel.v1/res_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v1/res_sharing.tcl
diff --git a/Sobel/sobel.v1/rtl.rpt b/Sobel/sobel.v1/rtl.rpt
new file mode 100644
index 0000000..3bdb058
--- /dev/null
+++ b/Sobel/sobel.v1/rtl.rpt
@@ -0,0 +1,878 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 13:49:49 +0000 2016                      
+
+Solution Settings: sobel.v1
+  Current state: extract
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       105  307200     307200            0  1          
+    Design Total:                     105  307200     307200            0  0          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(10,0,10,0,10)                       11.241                       0.000     11.241 1.301          2           2 
+    mgc_add(10,1,10,1,11)                       11.000                       0.000     11.000 1.139          0           3 
+    mgc_add(11,0,10,1,12)                       12.000                       0.000     12.000 1.208          2           2 
+    mgc_add(11,1,11,1,12)                       12.000                       0.000     12.000 1.206          6           6 
+    mgc_add(12,0,11,0,13)                       13.228                       0.000     13.228 1.436          2           0 
+    mgc_add(12,0,11,1,12)                       13.000                       0.000     13.000 1.436          0           2 
+    mgc_add(12,1,12,1,13)                       13.000                       0.000     13.000 1.272          9           6 
+    mgc_add(13,0,12,1,13)                       14.000                       0.000     14.000 1.501          2           0 
+    mgc_add(19,0,2,1,19)                        20.000                       0.000     20.000 1.908          1           0 
+    mgc_add(2,0,2,0,3)                           3.311                       0.000      3.311 0.653          3           0 
+    mgc_add(3,0,2,0,4)                           4.306                       0.000      4.306 0.764          0           4 
+    mgc_add(3,0,3,0,4)                           4.302                       0.000      4.302 0.761          8           8 
+    mgc_add(4,0,4,0,5)                           5.293                       0.000      5.293 0.854          5           5 
+    mgc_add(4,1,3,0,5)                           6.000                       0.000      6.000 0.856          0           1 
+    mgc_add(5,0,5,0,5)                           6.285                       0.000      6.285 0.938          0           3 
+    mgc_add(5,0,5,1,7)                           6.000                       0.000      6.000 0.613          9           9 
+    mgc_add(5,1,4,1,6)                           6.000                       0.000      6.000 0.778          1           1 
+    mgc_add(6,0,5,1,8)                           7.000                       0.000      7.000 0.693          2           2 
+    mgc_add(6,0,6,0,6)                           7.276                       0.000      7.276 1.016          3           0 
+    mgc_add(7,1,6,0,8)                           9.000                       0.000      9.000 1.093          1           0 
+    mgc_add(8,0,7,0,8)                           9.262                       0.000      9.262 1.165          1           0 
+    mgc_add(9,0,8,1,10)                         10.000                       0.000     10.000 1.072          3           3 
+    mgc_and(19,2)                               13.867                       0.000     13.867 0.263          1           0 
+    mgc_mul(2,0,9,0,11)                        330.250                       2.000     10.250 3.044          3           3 
+    mgc_mul(3,0,6,0,9)                         330.250                       2.000     10.250 2.846          3           3 
+    mgc_not(1)                                   0.000                       0.000      0.000 0.000          0          11 
+    mgc_not(10)                                  0.000                       0.000      0.000 0.000          0           9 
+    mgc_not(3)                                   0.000                       0.000      0.000 0.000          0          12 
+    mgc_or(1,2)                                  0.730                       0.000      0.730 0.268          0           1 
+    mgc_or(10,2)                                 7.298                       0.000      7.298 0.268          1           1 
+    mgc_or(5,2)                                  3.649                       0.000      3.649 0.268          0           1 
+    mgc_or(6,2)                                  4.379                       0.000      4.379 0.268          1           0 
+    mgc_reg_pos(1,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(10,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0          10 
+    mgc_reg_pos(4,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(5,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(9,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(90,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,90)                            0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(2,30)                         0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):            2455.620                      12.000    536.000                              
+    
+  Area Scores
+                      Post-Scheduling   Post-DP & FSM Post-Assignment 
+    ----------------- --------------- --------------- ---------------
+    Total Area Score:   2531.9          2479.4          2455.6        
+    Total Reg:             0.0             0.0             0.0        
+                                                                      
+    DataPath:           2531.9 (100%)   2479.4 (100%)   2455.6 (100%) 
+      MUX:                 0.0             0.0             0.0        
+      FUNC:             2506.3  (99%)   2467.7 (100%)   2443.9 (100%) 
+      LOGIC:              25.5   (1%)     11.7   (0%)     11.7   (0%) 
+      BUFFER:              0.0             0.0             0.0        
+      MEM:                 0.0             0.0             0.0        
+      ROM:                 0.0             0.0             0.0        
+      REG:                 0.0             0.0             0.0        
+                                                                      
+    
+    FSM:                   0.0             0.0             0.0        
+      FSM-REG:             0.0             0.0             0.0        
+      FSM-COMB:            0.0             0.0             0.0        
+                                                                      
+    
+  Register-to-Variable Mappings
+    Register                             Size(bits) Gated Register CG Opt Done Variables                                             
+    ------------------------------------ ---------- -------------- ----------- -----------------------------------------------------
+    regs.regs(1).sva                             90         Y                  regs.regs(1).sva                                      
+    ACC1:slc(regs.regs(2))#10.itm                10         Y                  ACC1:slc(regs.regs(2))#10.itm                         
+    ACC1:slc(regs.regs(2))#11.itm                10         Y                  ACC1:slc(regs.regs(2))#11.itm                         
+    ACC1:slc(regs.regs(2))#12.itm                10         Y                  ACC1:slc(regs.regs(2))#12.itm                         
+    ACC1:slc(regs.regs(2))#13.itm                10         Y                  ACC1:slc(regs.regs(2))#13.itm                         
+    ACC1:slc(regs.regs(2))#14.itm                10         Y                  ACC1:slc(regs.regs(2))#14.itm                         
+    ACC1:slc(regs.regs(2))#15.itm                10         Y                  ACC1:slc(regs.regs(2))#15.itm                         
+    ACC1:slc(regs.regs(2))#16.itm                10         Y                  ACC1:slc(regs.regs(2))#16.itm                         
+    ACC1:slc(regs.regs(2))#9.itm                 10         Y                  ACC1:slc(regs.regs(2))#9.itm                          
+    ACC1:slc(regs.regs(2)).itm                   10         Y                  ACC1:slc(regs.regs(2)).itm                            
+    reg(vout:rsc:mgc_out_stdreg.d).tmp           10         Y                  reg(vout:rsc:mgc_out_stdreg.d).tmp                    
+    reg(vout:rsc:mgc_out_stdreg.d).tmp#4          9         Y                  reg(vout:rsc:mgc_out_stdreg.d).tmp#4                  
+    reg(vout:rsc:mgc_out_stdreg.d).tmp#2          5         Y                  reg(vout:rsc:mgc_out_stdreg.d).tmp#2                  
+    reg(vout:rsc:mgc_out_stdreg.d).tmp#1          4         Y                  reg(vout:rsc:mgc_out_stdreg.d).tmp#1                  
+    reg(vout:rsc:mgc_out_stdreg.d).tmp#3          1         Y                  reg(vout:rsc:mgc_out_stdreg.d).tmp#3                  
+    reg(vout:rsc:mgc_out_stdreg.d).tmp#5          1         Y                  reg(vout:rsc:mgc_out_stdreg.d).tmp#5                  
+                                                                                                                                     
+    Total:                                      210            210           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  14.431315999999997
+      Slack:      5.568684000000003
+      
+      Path                                            Startpoint                                    Endpoint                                    Delay   Slack   
+      ----------------------------------------------- --------------------------------------------- ------------------------------------------- ------- -------
+      1                                               sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)   14.4313 5.5687  
+                                                                                                                                                                
+        Instance                                      Component                                                                                 Delta   Delay   
+        --------                                      ---------                                                                                 -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) mgc_reg_pos_10_1_0_0_0_1_1                                                                0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2))#11.itm                                                                                                0.0000  0.0000  
+        sobel:core/conc#139                                                                                                                     0.0000  0.0000  
+        sobel:core/conc#139.itm                                                                                                                 0.0000  0.0000  
+        sobel:core/ACC1:acc#49                        mgc_add_11_1_11_1_12                                                                      1.2059  1.2059  
+        sobel:core/ACC1:acc#49.itm                                                                                                              0.0000  1.2059  
+        sobel:core/ACC1:slc#5                                                                                                                   0.0000  1.2059  
+        sobel:core/ACC1:slc#5.itm                                                                                                               0.0000  1.2059  
+        sobel:core/conc#138                                                                                                                     0.0000  1.2059  
+        sobel:core/conc#138.itm                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:acc#51                        mgc_add_12_1_12_1_13                                                                      1.2718  2.4777  
+        sobel:core/ACC1:acc#51.itm                                                                                                              0.0000  2.4777  
+        sobel:core/ACC1:slc#7                                                                                                                   0.0000  2.4777  
+        sobel:core/ACC1:slc#7.itm                                                                                                               0.0000  2.4777  
+        sobel:core/ACC1:acc#42                        mgc_add_12_1_12_1_13                                                                      1.2718  3.7496  
+        sobel:core/ACC1:acc#42.psp.sva                                                                                                          0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#7                                                                                                   0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm                                                                                               0.0000  3.7496  
+        sobel:core/FRAME:acc#15                       mgc_add_3_0_3_0_4                                                                         0.7609  4.5105  
+        sobel:core/FRAME:acc#15.itm                                                                                                             0.0000  4.5105  
+        sobel:core/FRAME:acc#17                       mgc_add_4_0_4_0_5                                                                         0.8536  5.3640  
+        sobel:core/FRAME:acc#17.itm                                                                                                             0.0000  5.3640  
+        sobel:core/FRAME:acc#18                       mgc_add_5_0_5_1_7                                                                         0.6126  5.9766  
+        sobel:core/FRAME:acc#18.sdt                                                                                                             0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1                                                                                                      0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1.itm                                                                                                  0.0000  5.9766  
+        sobel:core/FRAME:acc#49                       mgc_add_5_0_5_0_5                                                                         0.9376  6.9142  
+        sobel:core/FRAME:acc#49.psp                                                                                                             0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#1                                                                                                      0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#1.itm                                                                                                  0.0000  6.9142  
+        sobel:core/conc#118                                                                                                                     0.0000  6.9142  
+        sobel:core/conc#118.itm                                                                                                                 0.0000  6.9142  
+        sobel:core/FRAME:acc#26                       mgc_add_5_0_5_1_7                                                                         0.6126  7.5269  
+        sobel:core/FRAME:acc#26.itm                                                                                                             0.0000  7.5269  
+        sobel:core/FRAME:slc#5                                                                                                                  0.0000  7.5269  
+        sobel:core/FRAME:slc#5.itm                                                                                                              0.0000  7.5269  
+        sobel:core/FRAME:not#52                       mgc_not_1                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:not#52.itm                                                                                                             0.0000  7.5269  
+        sobel:core/conc#117                                                                                                                     0.0000  7.5269  
+        sobel:core/conc#117.itm                                                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:acc#19                       mgc_add_3_0_3_0_4                                                                         0.7609  8.2878  
+        sobel:core/FRAME:acc#19.itm                                                                                                             0.0000  8.2878  
+        sobel:core/FRAME:acc#20                       mgc_add_4_0_4_0_5                                                                         0.8536  9.1413  
+        sobel:core/FRAME:acc#20.itm                                                                                                             0.0000  9.1413  
+        sobel:core/FRAME:acc#21                       mgc_add_5_0_5_1_7                                                                         0.6126  9.7540  
+        sobel:core/FRAME:acc#21.itm                                                                                                             0.0000  9.7540  
+        sobel:core/FRAME:acc#22                       mgc_add_6_0_5_1_8                                                                         0.6934  10.4474 
+        sobel:core/FRAME:acc#22.itm                                                                                                             0.0000  10.4474 
+        sobel:core/FRAME:acc#23                       mgc_add_9_0_8_1_10                                                                        1.0725  11.5198 
+        sobel:core/FRAME:acc#23.itm                                                                                                             0.0000  11.5198 
+        sobel:core/FRAME:acc#24                       mgc_add_11_0_10_1_12                                                                      1.2076  12.7275 
+        sobel:core/FRAME:acc#24.sdt                                                                                                             0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1                                                                                                      0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1.itm                                                                                                  0.0000  12.7275 
+        sobel:core/FRAME:acc                          mgc_add_12_0_11_1_12                                                                      1.4360  14.1634 
+        sobel:core/FRAME:acc.psp                                                                                                                0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp)                                                                                                           0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp).itm                                                                                                       0.0000  14.1634 
+        sobel:core/conc#147                                                                                                                     0.0000  14.1634 
+        sobel:core/conc#147.itm                                                                                                                 0.0000  14.1634 
+        sobel:core/FRAME:or                           mgc_or_10_2                                                                               0.2679  14.4313 
+        sobel:core/FRAME:or.itm                                                                                                                 0.0000  14.4313 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)     mgc_reg_pos_10_1_0_0_0_1_1                                                                0.0000  14.4313 
+                                                                                                                                                                
+      2                                               sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4313 5.5687  
+                                                                                                                                                                
+        Instance                                      Component                                                                                 Delta   Delay   
+        --------                                      ---------                                                                                 -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) mgc_reg_pos_10_1_0_0_0_1_1                                                                0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2))#11.itm                                                                                                0.0000  0.0000  
+        sobel:core/conc#139                                                                                                                     0.0000  0.0000  
+        sobel:core/conc#139.itm                                                                                                                 0.0000  0.0000  
+        sobel:core/ACC1:acc#49                        mgc_add_11_1_11_1_12                                                                      1.2059  1.2059  
+        sobel:core/ACC1:acc#49.itm                                                                                                              0.0000  1.2059  
+        sobel:core/ACC1:slc#5                                                                                                                   0.0000  1.2059  
+        sobel:core/ACC1:slc#5.itm                                                                                                               0.0000  1.2059  
+        sobel:core/conc#138                                                                                                                     0.0000  1.2059  
+        sobel:core/conc#138.itm                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:acc#51                        mgc_add_12_1_12_1_13                                                                      1.2718  2.4777  
+        sobel:core/ACC1:acc#51.itm                                                                                                              0.0000  2.4777  
+        sobel:core/ACC1:slc#7                                                                                                                   0.0000  2.4777  
+        sobel:core/ACC1:slc#7.itm                                                                                                               0.0000  2.4777  
+        sobel:core/ACC1:acc#42                        mgc_add_12_1_12_1_13                                                                      1.2718  3.7496  
+        sobel:core/ACC1:acc#42.psp.sva                                                                                                          0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#7                                                                                                   0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm                                                                                               0.0000  3.7496  
+        sobel:core/FRAME:acc#15                       mgc_add_3_0_3_0_4                                                                         0.7609  4.5105  
+        sobel:core/FRAME:acc#15.itm                                                                                                             0.0000  4.5105  
+        sobel:core/FRAME:acc#17                       mgc_add_4_0_4_0_5                                                                         0.8536  5.3640  
+        sobel:core/FRAME:acc#17.itm                                                                                                             0.0000  5.3640  
+        sobel:core/FRAME:acc#18                       mgc_add_5_0_5_1_7                                                                         0.6126  5.9766  
+        sobel:core/FRAME:acc#18.sdt                                                                                                             0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1                                                                                                      0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1.itm                                                                                                  0.0000  5.9766  
+        sobel:core/FRAME:acc#49                       mgc_add_5_0_5_0_5                                                                         0.9376  6.9142  
+        sobel:core/FRAME:acc#49.psp                                                                                                             0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#1                                                                                                      0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#1.itm                                                                                                  0.0000  6.9142  
+        sobel:core/conc#118                                                                                                                     0.0000  6.9142  
+        sobel:core/conc#118.itm                                                                                                                 0.0000  6.9142  
+        sobel:core/FRAME:acc#26                       mgc_add_5_0_5_1_7                                                                         0.6126  7.5269  
+        sobel:core/FRAME:acc#26.itm                                                                                                             0.0000  7.5269  
+        sobel:core/FRAME:slc#5                                                                                                                  0.0000  7.5269  
+        sobel:core/FRAME:slc#5.itm                                                                                                              0.0000  7.5269  
+        sobel:core/FRAME:not#52                       mgc_not_1                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:not#52.itm                                                                                                             0.0000  7.5269  
+        sobel:core/conc#117                                                                                                                     0.0000  7.5269  
+        sobel:core/conc#117.itm                                                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:acc#19                       mgc_add_3_0_3_0_4                                                                         0.7609  8.2878  
+        sobel:core/FRAME:acc#19.itm                                                                                                             0.0000  8.2878  
+        sobel:core/FRAME:acc#20                       mgc_add_4_0_4_0_5                                                                         0.8536  9.1413  
+        sobel:core/FRAME:acc#20.itm                                                                                                             0.0000  9.1413  
+        sobel:core/FRAME:acc#21                       mgc_add_5_0_5_1_7                                                                         0.6126  9.7540  
+        sobel:core/FRAME:acc#21.itm                                                                                                             0.0000  9.7540  
+        sobel:core/FRAME:acc#22                       mgc_add_6_0_5_1_8                                                                         0.6934  10.4474 
+        sobel:core/FRAME:acc#22.itm                                                                                                             0.0000  10.4474 
+        sobel:core/FRAME:acc#23                       mgc_add_9_0_8_1_10                                                                        1.0725  11.5198 
+        sobel:core/FRAME:acc#23.itm                                                                                                             0.0000  11.5198 
+        sobel:core/FRAME:acc#24                       mgc_add_11_0_10_1_12                                                                      1.2076  12.7275 
+        sobel:core/FRAME:acc#24.sdt                                                                                                             0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1                                                                                                      0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1.itm                                                                                                  0.0000  12.7275 
+        sobel:core/FRAME:acc                          mgc_add_12_0_11_1_12                                                                      1.4360  14.1634 
+        sobel:core/FRAME:acc.psp                                                                                                                0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp)#2                                                                                                         0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp)#2.itm                                                                                                     0.0000  14.1634 
+        sobel:core/FRAME:or#3                         mgc_or_5_2                                                                                0.2679  14.4313 
+        sobel:core/FRAME:or#3.itm                                                                                                               0.0000  14.4313 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2   mgc_reg_pos_5_1_0_0_0_1_1                                                                 0.0000  14.4313 
+                                                                                                                                                                
+      3                                               sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3 14.4313 5.5687  
+                                                                                                                                                                
+        Instance                                      Component                                                                                 Delta   Delay   
+        --------                                      ---------                                                                                 -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) mgc_reg_pos_10_1_0_0_0_1_1                                                                0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2))#14.itm                                                                                                0.0000  0.0000  
+        sobel:core/conc#131                                                                                                                     0.0000  0.0000  
+        sobel:core/conc#131.itm                                                                                                                 0.0000  0.0000  
+        sobel:core/ACC1:acc#53                        mgc_add_11_1_11_1_12                                                                      1.2059  1.2059  
+        sobel:core/ACC1:acc#53.itm                                                                                                              0.0000  1.2059  
+        sobel:core/ACC1:slc#9                                                                                                                   0.0000  1.2059  
+        sobel:core/ACC1:slc#9.itm                                                                                                               0.0000  1.2059  
+        sobel:core/conc#130                                                                                                                     0.0000  1.2059  
+        sobel:core/conc#130.itm                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:acc#55                        mgc_add_12_1_12_1_13                                                                      1.2718  2.4777  
+        sobel:core/ACC1:acc#55.itm                                                                                                              0.0000  2.4777  
+        sobel:core/ACC1:slc#11                                                                                                                  0.0000  2.4777  
+        sobel:core/ACC1:slc#11.itm                                                                                                              0.0000  2.4777  
+        sobel:core/ACC1:acc#43                        mgc_add_12_1_12_1_13                                                                      1.2718  3.7496  
+        sobel:core/ACC1:acc#43.psp.sva                                                                                                          0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#43.psp.sva)#7                                                                                                   0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#43.psp.sva)#7.itm                                                                                               0.0000  3.7496  
+        sobel:core/FRAME:acc#28                       mgc_add_3_0_3_0_4                                                                         0.7609  4.5105  
+        sobel:core/FRAME:acc#28.itm                                                                                                             0.0000  4.5105  
+        sobel:core/FRAME:acc#30                       mgc_add_4_0_4_0_5                                                                         0.8536  5.3640  
+        sobel:core/FRAME:acc#30.itm                                                                                                             0.0000  5.3640  
+        sobel:core/FRAME:acc#31                       mgc_add_5_0_5_1_7                                                                         0.6126  5.9766  
+        sobel:core/FRAME:acc#31.sdt                                                                                                             0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#31.sdt)#1                                                                                                      0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#31.sdt)#1.itm                                                                                                  0.0000  5.9766  
+        sobel:core/FRAME:acc#55                       mgc_add_5_0_5_0_5                                                                         0.9376  6.9142  
+        sobel:core/FRAME:acc#55.psp                                                                                                             0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#55.psp)#1                                                                                                      0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#55.psp)#1.itm                                                                                                  0.0000  6.9142  
+        sobel:core/conc#127                                                                                                                     0.0000  6.9142  
+        sobel:core/conc#127.itm                                                                                                                 0.0000  6.9142  
+        sobel:core/FRAME:acc#39                       mgc_add_5_0_5_1_7                                                                         0.6126  7.5269  
+        sobel:core/FRAME:acc#39.itm                                                                                                             0.0000  7.5269  
+        sobel:core/FRAME:slc#6                                                                                                                  0.0000  7.5269  
+        sobel:core/FRAME:slc#6.itm                                                                                                              0.0000  7.5269  
+        sobel:core/FRAME:not#54                       mgc_not_1                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:not#54.itm                                                                                                             0.0000  7.5269  
+        sobel:core/conc#126                                                                                                                     0.0000  7.5269  
+        sobel:core/conc#126.itm                                                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:acc#32                       mgc_add_3_0_3_0_4                                                                         0.7609  8.2878  
+        sobel:core/FRAME:acc#32.itm                                                                                                             0.0000  8.2878  
+        sobel:core/FRAME:acc#33                       mgc_add_4_0_4_0_5                                                                         0.8536  9.1413  
+        sobel:core/FRAME:acc#33.itm                                                                                                             0.0000  9.1413  
+        sobel:core/FRAME:acc#34                       mgc_add_5_0_5_1_7                                                                         0.6126  9.7540  
+        sobel:core/FRAME:acc#34.itm                                                                                                             0.0000  9.7540  
+        sobel:core/FRAME:acc#35                       mgc_add_6_0_5_1_8                                                                         0.6934  10.4474 
+        sobel:core/FRAME:acc#35.itm                                                                                                             0.0000  10.4474 
+        sobel:core/FRAME:acc#36                       mgc_add_9_0_8_1_10                                                                        1.0725  11.5198 
+        sobel:core/FRAME:acc#36.itm                                                                                                             0.0000  11.5198 
+        sobel:core/FRAME:acc#37                       mgc_add_11_0_10_1_12                                                                      1.2076  12.7275 
+        sobel:core/FRAME:acc#37.sdt                                                                                                             0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#37.sdt)#1                                                                                                      0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#37.sdt)#1.itm                                                                                                  0.0000  12.7275 
+        sobel:core/FRAME:acc#61                       mgc_add_12_0_11_1_12                                                                      1.4360  14.1634 
+        sobel:core/FRAME:acc#61.psp                                                                                                             0.0000  14.1634 
+        sobel:core/slc(FRAME:acc#61.psp)#2                                                                                                      0.0000  14.1634 
+        sobel:core/slc(FRAME:acc#61.psp)#2.itm                                                                                                  0.0000  14.1634 
+        sobel:core/FRAME:or#4                         mgc_or_1_2                                                                                0.2679  14.4313 
+        sobel:core/FRAME:or#4.itm                                                                                                               0.0000  14.4313 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3   mgc_reg_pos_1_1_0_0_0_1_1                                                                 0.0000  14.4313 
+                                                                                                                                                                
+      4                                               sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4313 5.5687  
+                                                                                                                                                                
+        Instance                                      Component                                                                                 Delta   Delay   
+        --------                                      ---------                                                                                 -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) mgc_reg_pos_10_1_0_0_0_1_1                                                                0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2))#11.itm                                                                                                0.0000  0.0000  
+        sobel:core/conc#139                                                                                                                     0.0000  0.0000  
+        sobel:core/conc#139.itm                                                                                                                 0.0000  0.0000  
+        sobel:core/ACC1:acc#49                        mgc_add_11_1_11_1_12                                                                      1.2059  1.2059  
+        sobel:core/ACC1:acc#49.itm                                                                                                              0.0000  1.2059  
+        sobel:core/ACC1:slc#5                                                                                                                   0.0000  1.2059  
+        sobel:core/ACC1:slc#5.itm                                                                                                               0.0000  1.2059  
+        sobel:core/conc#138                                                                                                                     0.0000  1.2059  
+        sobel:core/conc#138.itm                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:acc#51                        mgc_add_12_1_12_1_13                                                                      1.2718  2.4777  
+        sobel:core/ACC1:acc#51.itm                                                                                                              0.0000  2.4777  
+        sobel:core/ACC1:slc#7                                                                                                                   0.0000  2.4777  
+        sobel:core/ACC1:slc#7.itm                                                                                                               0.0000  2.4777  
+        sobel:core/ACC1:acc#42                        mgc_add_12_1_12_1_13                                                                      1.2718  3.7496  
+        sobel:core/ACC1:acc#42.psp.sva                                                                                                          0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#7                                                                                                   0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm                                                                                               0.0000  3.7496  
+        sobel:core/FRAME:acc#15                       mgc_add_3_0_3_0_4                                                                         0.7609  4.5105  
+        sobel:core/FRAME:acc#15.itm                                                                                                             0.0000  4.5105  
+        sobel:core/FRAME:acc#17                       mgc_add_4_0_4_0_5                                                                         0.8536  5.3640  
+        sobel:core/FRAME:acc#17.itm                                                                                                             0.0000  5.3640  
+        sobel:core/FRAME:acc#18                       mgc_add_5_0_5_1_7                                                                         0.6126  5.9766  
+        sobel:core/FRAME:acc#18.sdt                                                                                                             0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1                                                                                                      0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1.itm                                                                                                  0.0000  5.9766  
+        sobel:core/FRAME:acc#49                       mgc_add_5_0_5_0_5                                                                         0.9376  6.9142  
+        sobel:core/FRAME:acc#49.psp                                                                                                             0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#2                                                                                                      0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#2.itm                                                                                                  0.0000  6.9142  
+        sobel:core/FRAME:not#15                       mgc_not_3                                                                                 0.0000  6.9142  
+        sobel:core/FRAME:not#15.itm                                                                                                             0.0000  6.9142  
+        sobel:core/FRAME:conc#42                                                                                                                0.0000  6.9142  
+        sobel:core/FRAME:conc#42.itm                                                                                                            0.0000  6.9142  
+        sobel:core/FRAME:acc#26                       mgc_add_5_0_5_1_7                                                                         0.6126  7.5269  
+        sobel:core/FRAME:acc#26.itm                                                                                                             0.0000  7.5269  
+        sobel:core/FRAME:slc#5                                                                                                                  0.0000  7.5269  
+        sobel:core/FRAME:slc#5.itm                                                                                                              0.0000  7.5269  
+        sobel:core/FRAME:not#52                       mgc_not_1                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:not#52.itm                                                                                                             0.0000  7.5269  
+        sobel:core/conc#117                                                                                                                     0.0000  7.5269  
+        sobel:core/conc#117.itm                                                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:acc#19                       mgc_add_3_0_3_0_4                                                                         0.7609  8.2878  
+        sobel:core/FRAME:acc#19.itm                                                                                                             0.0000  8.2878  
+        sobel:core/FRAME:acc#20                       mgc_add_4_0_4_0_5                                                                         0.8536  9.1413  
+        sobel:core/FRAME:acc#20.itm                                                                                                             0.0000  9.1413  
+        sobel:core/FRAME:acc#21                       mgc_add_5_0_5_1_7                                                                         0.6126  9.7540  
+        sobel:core/FRAME:acc#21.itm                                                                                                             0.0000  9.7540  
+        sobel:core/FRAME:acc#22                       mgc_add_6_0_5_1_8                                                                         0.6934  10.4474 
+        sobel:core/FRAME:acc#22.itm                                                                                                             0.0000  10.4474 
+        sobel:core/FRAME:acc#23                       mgc_add_9_0_8_1_10                                                                        1.0725  11.5198 
+        sobel:core/FRAME:acc#23.itm                                                                                                             0.0000  11.5198 
+        sobel:core/FRAME:acc#24                       mgc_add_11_0_10_1_12                                                                      1.2076  12.7275 
+        sobel:core/FRAME:acc#24.sdt                                                                                                             0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1                                                                                                      0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1.itm                                                                                                  0.0000  12.7275 
+        sobel:core/FRAME:acc                          mgc_add_12_0_11_1_12                                                                      1.4360  14.1634 
+        sobel:core/FRAME:acc.psp                                                                                                                0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp)#2                                                                                                         0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp)#2.itm                                                                                                     0.0000  14.1634 
+        sobel:core/FRAME:or#3                         mgc_or_5_2                                                                                0.2679  14.4313 
+        sobel:core/FRAME:or#3.itm                                                                                                               0.0000  14.4313 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2   mgc_reg_pos_5_1_0_0_0_1_1                                                                 0.0000  14.4313 
+                                                                                                                                                                
+      5                                               sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4313 5.5687  
+                                                                                                                                                                
+        Instance                                      Component                                                                                 Delta   Delay   
+        --------                                      ---------                                                                                 -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) mgc_reg_pos_10_1_0_0_0_1_1                                                                0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2))#11.itm                                                                                                0.0000  0.0000  
+        sobel:core/conc#139                                                                                                                     0.0000  0.0000  
+        sobel:core/conc#139.itm                                                                                                                 0.0000  0.0000  
+        sobel:core/ACC1:acc#49                        mgc_add_11_1_11_1_12                                                                      1.2059  1.2059  
+        sobel:core/ACC1:acc#49.itm                                                                                                              0.0000  1.2059  
+        sobel:core/ACC1:slc#5                                                                                                                   0.0000  1.2059  
+        sobel:core/ACC1:slc#5.itm                                                                                                               0.0000  1.2059  
+        sobel:core/conc#138                                                                                                                     0.0000  1.2059  
+        sobel:core/conc#138.itm                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:acc#51                        mgc_add_12_1_12_1_13                                                                      1.2718  2.4777  
+        sobel:core/ACC1:acc#51.itm                                                                                                              0.0000  2.4777  
+        sobel:core/ACC1:slc#7                                                                                                                   0.0000  2.4777  
+        sobel:core/ACC1:slc#7.itm                                                                                                               0.0000  2.4777  
+        sobel:core/ACC1:acc#42                        mgc_add_12_1_12_1_13                                                                      1.2718  3.7496  
+        sobel:core/ACC1:acc#42.psp.sva                                                                                                          0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#7                                                                                                   0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm                                                                                               0.0000  3.7496  
+        sobel:core/FRAME:acc#15                       mgc_add_3_0_3_0_4                                                                         0.7609  4.5105  
+        sobel:core/FRAME:acc#15.itm                                                                                                             0.0000  4.5105  
+        sobel:core/FRAME:acc#17                       mgc_add_4_0_4_0_5                                                                         0.8536  5.3640  
+        sobel:core/FRAME:acc#17.itm                                                                                                             0.0000  5.3640  
+        sobel:core/FRAME:acc#18                       mgc_add_5_0_5_1_7                                                                         0.6126  5.9766  
+        sobel:core/FRAME:acc#18.sdt                                                                                                             0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1                                                                                                      0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1.itm                                                                                                  0.0000  5.9766  
+        sobel:core/FRAME:acc#49                       mgc_add_5_0_5_0_5                                                                         0.9376  6.9142  
+        sobel:core/FRAME:acc#49.psp                                                                                                             0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#4                                                                                                      0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#4.itm                                                                                                  0.0000  6.9142  
+        sobel:core/FRAME:not#47                       mgc_not_1                                                                                 0.0000  6.9142  
+        sobel:core/FRAME:not#47.itm                                                                                                             0.0000  6.9142  
+        sobel:core/FRAME:conc#42                                                                                                                0.0000  6.9142  
+        sobel:core/FRAME:conc#42.itm                                                                                                            0.0000  6.9142  
+        sobel:core/FRAME:acc#26                       mgc_add_5_0_5_1_7                                                                         0.6126  7.5269  
+        sobel:core/FRAME:acc#26.itm                                                                                                             0.0000  7.5269  
+        sobel:core/FRAME:slc#5                                                                                                                  0.0000  7.5269  
+        sobel:core/FRAME:slc#5.itm                                                                                                              0.0000  7.5269  
+        sobel:core/FRAME:not#52                       mgc_not_1                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:not#52.itm                                                                                                             0.0000  7.5269  
+        sobel:core/conc#117                                                                                                                     0.0000  7.5269  
+        sobel:core/conc#117.itm                                                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:acc#19                       mgc_add_3_0_3_0_4                                                                         0.7609  8.2878  
+        sobel:core/FRAME:acc#19.itm                                                                                                             0.0000  8.2878  
+        sobel:core/FRAME:acc#20                       mgc_add_4_0_4_0_5                                                                         0.8536  9.1413  
+        sobel:core/FRAME:acc#20.itm                                                                                                             0.0000  9.1413  
+        sobel:core/FRAME:acc#21                       mgc_add_5_0_5_1_7                                                                         0.6126  9.7540  
+        sobel:core/FRAME:acc#21.itm                                                                                                             0.0000  9.7540  
+        sobel:core/FRAME:acc#22                       mgc_add_6_0_5_1_8                                                                         0.6934  10.4474 
+        sobel:core/FRAME:acc#22.itm                                                                                                             0.0000  10.4474 
+        sobel:core/FRAME:acc#23                       mgc_add_9_0_8_1_10                                                                        1.0725  11.5198 
+        sobel:core/FRAME:acc#23.itm                                                                                                             0.0000  11.5198 
+        sobel:core/FRAME:acc#24                       mgc_add_11_0_10_1_12                                                                      1.2076  12.7275 
+        sobel:core/FRAME:acc#24.sdt                                                                                                             0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1                                                                                                      0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1.itm                                                                                                  0.0000  12.7275 
+        sobel:core/FRAME:acc                          mgc_add_12_0_11_1_12                                                                      1.4360  14.1634 
+        sobel:core/FRAME:acc.psp                                                                                                                0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp)#2                                                                                                         0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp)#2.itm                                                                                                     0.0000  14.1634 
+        sobel:core/FRAME:or#3                         mgc_or_5_2                                                                                0.2679  14.4313 
+        sobel:core/FRAME:or#3.itm                                                                                                               0.0000  14.4313 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2   mgc_reg_pos_5_1_0_0_0_1_1                                                                 0.0000  14.4313 
+                                                                                                                                                                
+      6                                               sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3 14.4313 5.5687  
+                                                                                                                                                                
+        Instance                                      Component                                                                                 Delta   Delay   
+        --------                                      ---------                                                                                 -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) mgc_reg_pos_10_1_0_0_0_1_1                                                                0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2))#14.itm                                                                                                0.0000  0.0000  
+        sobel:core/conc#131                                                                                                                     0.0000  0.0000  
+        sobel:core/conc#131.itm                                                                                                                 0.0000  0.0000  
+        sobel:core/ACC1:acc#53                        mgc_add_11_1_11_1_12                                                                      1.2059  1.2059  
+        sobel:core/ACC1:acc#53.itm                                                                                                              0.0000  1.2059  
+        sobel:core/ACC1:slc#9                                                                                                                   0.0000  1.2059  
+        sobel:core/ACC1:slc#9.itm                                                                                                               0.0000  1.2059  
+        sobel:core/conc#130                                                                                                                     0.0000  1.2059  
+        sobel:core/conc#130.itm                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:acc#55                        mgc_add_12_1_12_1_13                                                                      1.2718  2.4777  
+        sobel:core/ACC1:acc#55.itm                                                                                                              0.0000  2.4777  
+        sobel:core/ACC1:slc#11                                                                                                                  0.0000  2.4777  
+        sobel:core/ACC1:slc#11.itm                                                                                                              0.0000  2.4777  
+        sobel:core/ACC1:acc#43                        mgc_add_12_1_12_1_13                                                                      1.2718  3.7496  
+        sobel:core/ACC1:acc#43.psp.sva                                                                                                          0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#43.psp.sva)#7                                                                                                   0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#43.psp.sva)#7.itm                                                                                               0.0000  3.7496  
+        sobel:core/FRAME:acc#28                       mgc_add_3_0_3_0_4                                                                         0.7609  4.5105  
+        sobel:core/FRAME:acc#28.itm                                                                                                             0.0000  4.5105  
+        sobel:core/FRAME:acc#30                       mgc_add_4_0_4_0_5                                                                         0.8536  5.3640  
+        sobel:core/FRAME:acc#30.itm                                                                                                             0.0000  5.3640  
+        sobel:core/FRAME:acc#31                       mgc_add_5_0_5_1_7                                                                         0.6126  5.9766  
+        sobel:core/FRAME:acc#31.sdt                                                                                                             0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#31.sdt)#1                                                                                                      0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#31.sdt)#1.itm                                                                                                  0.0000  5.9766  
+        sobel:core/FRAME:acc#55                       mgc_add_5_0_5_0_5                                                                         0.9376  6.9142  
+        sobel:core/FRAME:acc#55.psp                                                                                                             0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#55.psp)#2                                                                                                      0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#55.psp)#2.itm                                                                                                  0.0000  6.9142  
+        sobel:core/FRAME:not#24                       mgc_not_3                                                                                 0.0000  6.9142  
+        sobel:core/FRAME:not#24.itm                                                                                                             0.0000  6.9142  
+        sobel:core/FRAME:conc#46                                                                                                                0.0000  6.9142  
+        sobel:core/FRAME:conc#46.itm                                                                                                            0.0000  6.9142  
+        sobel:core/FRAME:acc#39                       mgc_add_5_0_5_1_7                                                                         0.6126  7.5269  
+        sobel:core/FRAME:acc#39.itm                                                                                                             0.0000  7.5269  
+        sobel:core/FRAME:slc#6                                                                                                                  0.0000  7.5269  
+        sobel:core/FRAME:slc#6.itm                                                                                                              0.0000  7.5269  
+        sobel:core/FRAME:not#54                       mgc_not_1                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:not#54.itm                                                                                                             0.0000  7.5269  
+        sobel:core/conc#126                                                                                                                     0.0000  7.5269  
+        sobel:core/conc#126.itm                                                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:acc#32                       mgc_add_3_0_3_0_4                                                                         0.7609  8.2878  
+        sobel:core/FRAME:acc#32.itm                                                                                                             0.0000  8.2878  
+        sobel:core/FRAME:acc#33                       mgc_add_4_0_4_0_5                                                                         0.8536  9.1413  
+        sobel:core/FRAME:acc#33.itm                                                                                                             0.0000  9.1413  
+        sobel:core/FRAME:acc#34                       mgc_add_5_0_5_1_7                                                                         0.6126  9.7540  
+        sobel:core/FRAME:acc#34.itm                                                                                                             0.0000  9.7540  
+        sobel:core/FRAME:acc#35                       mgc_add_6_0_5_1_8                                                                         0.6934  10.4474 
+        sobel:core/FRAME:acc#35.itm                                                                                                             0.0000  10.4474 
+        sobel:core/FRAME:acc#36                       mgc_add_9_0_8_1_10                                                                        1.0725  11.5198 
+        sobel:core/FRAME:acc#36.itm                                                                                                             0.0000  11.5198 
+        sobel:core/FRAME:acc#37                       mgc_add_11_0_10_1_12                                                                      1.2076  12.7275 
+        sobel:core/FRAME:acc#37.sdt                                                                                                             0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#37.sdt)#1                                                                                                      0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#37.sdt)#1.itm                                                                                                  0.0000  12.7275 
+        sobel:core/FRAME:acc#61                       mgc_add_12_0_11_1_12                                                                      1.4360  14.1634 
+        sobel:core/FRAME:acc#61.psp                                                                                                             0.0000  14.1634 
+        sobel:core/slc(FRAME:acc#61.psp)#2                                                                                                      0.0000  14.1634 
+        sobel:core/slc(FRAME:acc#61.psp)#2.itm                                                                                                  0.0000  14.1634 
+        sobel:core/FRAME:or#4                         mgc_or_1_2                                                                                0.2679  14.4313 
+        sobel:core/FRAME:or#4.itm                                                                                                               0.0000  14.4313 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3   mgc_reg_pos_1_1_0_0_0_1_1                                                                 0.0000  14.4313 
+                                                                                                                                                                
+      7                                               sobel:core/reg(ACC1:slc(regs.regs(2))#12.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4313 5.5687  
+                                                                                                                                                                
+        Instance                                      Component                                                                                 Delta   Delay   
+        --------                                      ---------                                                                                 -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2))#12.itm) mgc_reg_pos_10_1_0_0_0_1_1                                                                0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2))#12.itm                                                                                                0.0000  0.0000  
+        sobel:core/conc#140                                                                                                                     0.0000  0.0000  
+        sobel:core/conc#140.itm                                                                                                                 0.0000  0.0000  
+        sobel:core/ACC1:acc#49                        mgc_add_11_1_11_1_12                                                                      1.2059  1.2059  
+        sobel:core/ACC1:acc#49.itm                                                                                                              0.0000  1.2059  
+        sobel:core/ACC1:slc#5                                                                                                                   0.0000  1.2059  
+        sobel:core/ACC1:slc#5.itm                                                                                                               0.0000  1.2059  
+        sobel:core/conc#138                                                                                                                     0.0000  1.2059  
+        sobel:core/conc#138.itm                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:acc#51                        mgc_add_12_1_12_1_13                                                                      1.2718  2.4777  
+        sobel:core/ACC1:acc#51.itm                                                                                                              0.0000  2.4777  
+        sobel:core/ACC1:slc#7                                                                                                                   0.0000  2.4777  
+        sobel:core/ACC1:slc#7.itm                                                                                                               0.0000  2.4777  
+        sobel:core/ACC1:acc#42                        mgc_add_12_1_12_1_13                                                                      1.2718  3.7496  
+        sobel:core/ACC1:acc#42.psp.sva                                                                                                          0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#7                                                                                                   0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm                                                                                               0.0000  3.7496  
+        sobel:core/FRAME:acc#15                       mgc_add_3_0_3_0_4                                                                         0.7609  4.5105  
+        sobel:core/FRAME:acc#15.itm                                                                                                             0.0000  4.5105  
+        sobel:core/FRAME:acc#17                       mgc_add_4_0_4_0_5                                                                         0.8536  5.3640  
+        sobel:core/FRAME:acc#17.itm                                                                                                             0.0000  5.3640  
+        sobel:core/FRAME:acc#18                       mgc_add_5_0_5_1_7                                                                         0.6126  5.9766  
+        sobel:core/FRAME:acc#18.sdt                                                                                                             0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1                                                                                                      0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1.itm                                                                                                  0.0000  5.9766  
+        sobel:core/FRAME:acc#49                       mgc_add_5_0_5_0_5                                                                         0.9376  6.9142  
+        sobel:core/FRAME:acc#49.psp                                                                                                             0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#4                                                                                                      0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#4.itm                                                                                                  0.0000  6.9142  
+        sobel:core/FRAME:not#47                       mgc_not_1                                                                                 0.0000  6.9142  
+        sobel:core/FRAME:not#47.itm                                                                                                             0.0000  6.9142  
+        sobel:core/FRAME:conc#42                                                                                                                0.0000  6.9142  
+        sobel:core/FRAME:conc#42.itm                                                                                                            0.0000  6.9142  
+        sobel:core/FRAME:acc#26                       mgc_add_5_0_5_1_7                                                                         0.6126  7.5269  
+        sobel:core/FRAME:acc#26.itm                                                                                                             0.0000  7.5269  
+        sobel:core/FRAME:slc#5                                                                                                                  0.0000  7.5269  
+        sobel:core/FRAME:slc#5.itm                                                                                                              0.0000  7.5269  
+        sobel:core/FRAME:not#52                       mgc_not_1                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:not#52.itm                                                                                                             0.0000  7.5269  
+        sobel:core/conc#117                                                                                                                     0.0000  7.5269  
+        sobel:core/conc#117.itm                                                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:acc#19                       mgc_add_3_0_3_0_4                                                                         0.7609  8.2878  
+        sobel:core/FRAME:acc#19.itm                                                                                                             0.0000  8.2878  
+        sobel:core/FRAME:acc#20                       mgc_add_4_0_4_0_5                                                                         0.8536  9.1413  
+        sobel:core/FRAME:acc#20.itm                                                                                                             0.0000  9.1413  
+        sobel:core/FRAME:acc#21                       mgc_add_5_0_5_1_7                                                                         0.6126  9.7540  
+        sobel:core/FRAME:acc#21.itm                                                                                                             0.0000  9.7540  
+        sobel:core/FRAME:acc#22                       mgc_add_6_0_5_1_8                                                                         0.6934  10.4474 
+        sobel:core/FRAME:acc#22.itm                                                                                                             0.0000  10.4474 
+        sobel:core/FRAME:acc#23                       mgc_add_9_0_8_1_10                                                                        1.0725  11.5198 
+        sobel:core/FRAME:acc#23.itm                                                                                                             0.0000  11.5198 
+        sobel:core/FRAME:acc#24                       mgc_add_11_0_10_1_12                                                                      1.2076  12.7275 
+        sobel:core/FRAME:acc#24.sdt                                                                                                             0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1                                                                                                      0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1.itm                                                                                                  0.0000  12.7275 
+        sobel:core/FRAME:acc                          mgc_add_12_0_11_1_12                                                                      1.4360  14.1634 
+        sobel:core/FRAME:acc.psp                                                                                                                0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp)#2                                                                                                         0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp)#2.itm                                                                                                     0.0000  14.1634 
+        sobel:core/FRAME:or#3                         mgc_or_5_2                                                                                0.2679  14.4313 
+        sobel:core/FRAME:or#3.itm                                                                                                               0.0000  14.4313 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2   mgc_reg_pos_5_1_0_0_0_1_1                                                                 0.0000  14.4313 
+                                                                                                                                                                
+      8                                               sobel:core/vin:rsc:mgc_in_wire.d              sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4313 5.5687  
+                                                                                                                                                                
+        Instance                                      Component                                                                                 Delta   Delay   
+        --------                                      ---------                                                                                 -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                                        0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#4)                                                                                                      0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#4).itm                                                                                                  0.0000  0.0000  
+        sobel:core/ACC1:not#22                        mgc_not_10                                                                                0.0000  0.0000  
+        sobel:core/ACC1:not#22.itm                                                                                                              0.0000  0.0000  
+        sobel:core/conc#142                                                                                                                     0.0000  0.0000  
+        sobel:core/conc#142.itm                                                                                                                 0.0000  0.0000  
+        sobel:core/ACC1:acc#48                        mgc_add_11_1_11_1_12                                                                      1.2059  1.2059  
+        sobel:core/ACC1:acc#48.itm                                                                                                              0.0000  1.2059  
+        sobel:core/ACC1:slc#4                                                                                                                   0.0000  1.2059  
+        sobel:core/ACC1:slc#4.itm                                                                                                               0.0000  1.2059  
+        sobel:core/conc#141                                                                                                                     0.0000  1.2059  
+        sobel:core/conc#141.itm                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:acc#51                        mgc_add_12_1_12_1_13                                                                      1.2718  2.4777  
+        sobel:core/ACC1:acc#51.itm                                                                                                              0.0000  2.4777  
+        sobel:core/ACC1:slc#7                                                                                                                   0.0000  2.4777  
+        sobel:core/ACC1:slc#7.itm                                                                                                               0.0000  2.4777  
+        sobel:core/ACC1:acc#42                        mgc_add_12_1_12_1_13                                                                      1.2718  3.7496  
+        sobel:core/ACC1:acc#42.psp.sva                                                                                                          0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#7                                                                                                   0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm                                                                                               0.0000  3.7496  
+        sobel:core/FRAME:acc#15                       mgc_add_3_0_3_0_4                                                                         0.7609  4.5105  
+        sobel:core/FRAME:acc#15.itm                                                                                                             0.0000  4.5105  
+        sobel:core/FRAME:acc#17                       mgc_add_4_0_4_0_5                                                                         0.8536  5.3640  
+        sobel:core/FRAME:acc#17.itm                                                                                                             0.0000  5.3640  
+        sobel:core/FRAME:acc#18                       mgc_add_5_0_5_1_7                                                                         0.6126  5.9766  
+        sobel:core/FRAME:acc#18.sdt                                                                                                             0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1                                                                                                      0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1.itm                                                                                                  0.0000  5.9766  
+        sobel:core/FRAME:acc#49                       mgc_add_5_0_5_0_5                                                                         0.9376  6.9142  
+        sobel:core/FRAME:acc#49.psp                                                                                                             0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#4                                                                                                      0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#4.itm                                                                                                  0.0000  6.9142  
+        sobel:core/FRAME:not#47                       mgc_not_1                                                                                 0.0000  6.9142  
+        sobel:core/FRAME:not#47.itm                                                                                                             0.0000  6.9142  
+        sobel:core/FRAME:conc#42                                                                                                                0.0000  6.9142  
+        sobel:core/FRAME:conc#42.itm                                                                                                            0.0000  6.9142  
+        sobel:core/FRAME:acc#26                       mgc_add_5_0_5_1_7                                                                         0.6126  7.5269  
+        sobel:core/FRAME:acc#26.itm                                                                                                             0.0000  7.5269  
+        sobel:core/FRAME:slc#5                                                                                                                  0.0000  7.5269  
+        sobel:core/FRAME:slc#5.itm                                                                                                              0.0000  7.5269  
+        sobel:core/FRAME:not#52                       mgc_not_1                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:not#52.itm                                                                                                             0.0000  7.5269  
+        sobel:core/conc#117                                                                                                                     0.0000  7.5269  
+        sobel:core/conc#117.itm                                                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:acc#19                       mgc_add_3_0_3_0_4                                                                         0.7609  8.2878  
+        sobel:core/FRAME:acc#19.itm                                                                                                             0.0000  8.2878  
+        sobel:core/FRAME:acc#20                       mgc_add_4_0_4_0_5                                                                         0.8536  9.1413  
+        sobel:core/FRAME:acc#20.itm                                                                                                             0.0000  9.1413  
+        sobel:core/FRAME:acc#21                       mgc_add_5_0_5_1_7                                                                         0.6126  9.7540  
+        sobel:core/FRAME:acc#21.itm                                                                                                             0.0000  9.7540  
+        sobel:core/FRAME:acc#22                       mgc_add_6_0_5_1_8                                                                         0.6934  10.4474 
+        sobel:core/FRAME:acc#22.itm                                                                                                             0.0000  10.4474 
+        sobel:core/FRAME:acc#23                       mgc_add_9_0_8_1_10                                                                        1.0725  11.5198 
+        sobel:core/FRAME:acc#23.itm                                                                                                             0.0000  11.5198 
+        sobel:core/FRAME:acc#24                       mgc_add_11_0_10_1_12                                                                      1.2076  12.7275 
+        sobel:core/FRAME:acc#24.sdt                                                                                                             0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1                                                                                                      0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1.itm                                                                                                  0.0000  12.7275 
+        sobel:core/FRAME:acc                          mgc_add_12_0_11_1_12                                                                      1.4360  14.1634 
+        sobel:core/FRAME:acc.psp                                                                                                                0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp)#2                                                                                                         0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp)#2.itm                                                                                                     0.0000  14.1634 
+        sobel:core/FRAME:or#3                         mgc_or_5_2                                                                                0.2679  14.4313 
+        sobel:core/FRAME:or#3.itm                                                                                                               0.0000  14.4313 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2   mgc_reg_pos_5_1_0_0_0_1_1                                                                 0.0000  14.4313 
+                                                                                                                                                                
+      9                                               sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3 14.4313 5.5687  
+                                                                                                                                                                
+        Instance                                      Component                                                                                 Delta   Delay   
+        --------                                      ---------                                                                                 -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) mgc_reg_pos_10_1_0_0_0_1_1                                                                0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2))#14.itm                                                                                                0.0000  0.0000  
+        sobel:core/conc#131                                                                                                                     0.0000  0.0000  
+        sobel:core/conc#131.itm                                                                                                                 0.0000  0.0000  
+        sobel:core/ACC1:acc#53                        mgc_add_11_1_11_1_12                                                                      1.2059  1.2059  
+        sobel:core/ACC1:acc#53.itm                                                                                                              0.0000  1.2059  
+        sobel:core/ACC1:slc#9                                                                                                                   0.0000  1.2059  
+        sobel:core/ACC1:slc#9.itm                                                                                                               0.0000  1.2059  
+        sobel:core/conc#130                                                                                                                     0.0000  1.2059  
+        sobel:core/conc#130.itm                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:acc#55                        mgc_add_12_1_12_1_13                                                                      1.2718  2.4777  
+        sobel:core/ACC1:acc#55.itm                                                                                                              0.0000  2.4777  
+        sobel:core/ACC1:slc#11                                                                                                                  0.0000  2.4777  
+        sobel:core/ACC1:slc#11.itm                                                                                                              0.0000  2.4777  
+        sobel:core/ACC1:acc#43                        mgc_add_12_1_12_1_13                                                                      1.2718  3.7496  
+        sobel:core/ACC1:acc#43.psp.sva                                                                                                          0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#43.psp.sva)#8                                                                                                   0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#43.psp.sva)#8.itm                                                                                               0.0000  3.7496  
+        sobel:core/FRAME:not#35                       mgc_not_3                                                                                 0.0000  3.7496  
+        sobel:core/FRAME:not#35.itm                                                                                                             0.0000  3.7496  
+        sobel:core/FRAME:acc#28                       mgc_add_3_0_3_0_4                                                                         0.7609  4.5105  
+        sobel:core/FRAME:acc#28.itm                                                                                                             0.0000  4.5105  
+        sobel:core/FRAME:acc#30                       mgc_add_4_0_4_0_5                                                                         0.8536  5.3640  
+        sobel:core/FRAME:acc#30.itm                                                                                                             0.0000  5.3640  
+        sobel:core/FRAME:acc#31                       mgc_add_5_0_5_1_7                                                                         0.6126  5.9766  
+        sobel:core/FRAME:acc#31.sdt                                                                                                             0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#31.sdt)#1                                                                                                      0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#31.sdt)#1.itm                                                                                                  0.0000  5.9766  
+        sobel:core/FRAME:acc#55                       mgc_add_5_0_5_0_5                                                                         0.9376  6.9142  
+        sobel:core/FRAME:acc#55.psp                                                                                                             0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#55.psp)#2                                                                                                      0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#55.psp)#2.itm                                                                                                  0.0000  6.9142  
+        sobel:core/FRAME:not#24                       mgc_not_3                                                                                 0.0000  6.9142  
+        sobel:core/FRAME:not#24.itm                                                                                                             0.0000  6.9142  
+        sobel:core/FRAME:conc#46                                                                                                                0.0000  6.9142  
+        sobel:core/FRAME:conc#46.itm                                                                                                            0.0000  6.9142  
+        sobel:core/FRAME:acc#39                       mgc_add_5_0_5_1_7                                                                         0.6126  7.5269  
+        sobel:core/FRAME:acc#39.itm                                                                                                             0.0000  7.5269  
+        sobel:core/FRAME:slc#6                                                                                                                  0.0000  7.5269  
+        sobel:core/FRAME:slc#6.itm                                                                                                              0.0000  7.5269  
+        sobel:core/FRAME:not#54                       mgc_not_1                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:not#54.itm                                                                                                             0.0000  7.5269  
+        sobel:core/conc#126                                                                                                                     0.0000  7.5269  
+        sobel:core/conc#126.itm                                                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:acc#32                       mgc_add_3_0_3_0_4                                                                         0.7609  8.2878  
+        sobel:core/FRAME:acc#32.itm                                                                                                             0.0000  8.2878  
+        sobel:core/FRAME:acc#33                       mgc_add_4_0_4_0_5                                                                         0.8536  9.1413  
+        sobel:core/FRAME:acc#33.itm                                                                                                             0.0000  9.1413  
+        sobel:core/FRAME:acc#34                       mgc_add_5_0_5_1_7                                                                         0.6126  9.7540  
+        sobel:core/FRAME:acc#34.itm                                                                                                             0.0000  9.7540  
+        sobel:core/FRAME:acc#35                       mgc_add_6_0_5_1_8                                                                         0.6934  10.4474 
+        sobel:core/FRAME:acc#35.itm                                                                                                             0.0000  10.4474 
+        sobel:core/FRAME:acc#36                       mgc_add_9_0_8_1_10                                                                        1.0725  11.5198 
+        sobel:core/FRAME:acc#36.itm                                                                                                             0.0000  11.5198 
+        sobel:core/FRAME:acc#37                       mgc_add_11_0_10_1_12                                                                      1.2076  12.7275 
+        sobel:core/FRAME:acc#37.sdt                                                                                                             0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#37.sdt)#1                                                                                                      0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#37.sdt)#1.itm                                                                                                  0.0000  12.7275 
+        sobel:core/FRAME:acc#61                       mgc_add_12_0_11_1_12                                                                      1.4360  14.1634 
+        sobel:core/FRAME:acc#61.psp                                                                                                             0.0000  14.1634 
+        sobel:core/slc(FRAME:acc#61.psp)#2                                                                                                      0.0000  14.1634 
+        sobel:core/slc(FRAME:acc#61.psp)#2.itm                                                                                                  0.0000  14.1634 
+        sobel:core/FRAME:or#4                         mgc_or_1_2                                                                                0.2679  14.4313 
+        sobel:core/FRAME:or#4.itm                                                                                                               0.0000  14.4313 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3   mgc_reg_pos_1_1_0_0_0_1_1                                                                 0.0000  14.4313 
+                                                                                                                                                                
+      10                                              sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4313 5.5687  
+                                                                                                                                                                
+        Instance                                      Component                                                                                 Delta   Delay   
+        --------                                      ---------                                                                                 -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) mgc_reg_pos_10_1_0_0_0_1_1                                                                0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2))#11.itm                                                                                                0.0000  0.0000  
+        sobel:core/conc#139                                                                                                                     0.0000  0.0000  
+        sobel:core/conc#139.itm                                                                                                                 0.0000  0.0000  
+        sobel:core/ACC1:acc#49                        mgc_add_11_1_11_1_12                                                                      1.2059  1.2059  
+        sobel:core/ACC1:acc#49.itm                                                                                                              0.0000  1.2059  
+        sobel:core/ACC1:slc#5                                                                                                                   0.0000  1.2059  
+        sobel:core/ACC1:slc#5.itm                                                                                                               0.0000  1.2059  
+        sobel:core/conc#138                                                                                                                     0.0000  1.2059  
+        sobel:core/conc#138.itm                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:acc#51                        mgc_add_12_1_12_1_13                                                                      1.2718  2.4777  
+        sobel:core/ACC1:acc#51.itm                                                                                                              0.0000  2.4777  
+        sobel:core/ACC1:slc#7                                                                                                                   0.0000  2.4777  
+        sobel:core/ACC1:slc#7.itm                                                                                                               0.0000  2.4777  
+        sobel:core/ACC1:acc#42                        mgc_add_12_1_12_1_13                                                                      1.2718  3.7496  
+        sobel:core/ACC1:acc#42.psp.sva                                                                                                          0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#8                                                                                                   0.0000  3.7496  
+        sobel:core/slc(ACC1:acc#42.psp.sva)#8.itm                                                                                               0.0000  3.7496  
+        sobel:core/FRAME:not#33                       mgc_not_3                                                                                 0.0000  3.7496  
+        sobel:core/FRAME:not#33.itm                                                                                                             0.0000  3.7496  
+        sobel:core/FRAME:acc#15                       mgc_add_3_0_3_0_4                                                                         0.7609  4.5105  
+        sobel:core/FRAME:acc#15.itm                                                                                                             0.0000  4.5105  
+        sobel:core/FRAME:acc#17                       mgc_add_4_0_4_0_5                                                                         0.8536  5.3640  
+        sobel:core/FRAME:acc#17.itm                                                                                                             0.0000  5.3640  
+        sobel:core/FRAME:acc#18                       mgc_add_5_0_5_1_7                                                                         0.6126  5.9766  
+        sobel:core/FRAME:acc#18.sdt                                                                                                             0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1                                                                                                      0.0000  5.9766  
+        sobel:core/slc(FRAME:acc#18.sdt)#1.itm                                                                                                  0.0000  5.9766  
+        sobel:core/FRAME:acc#49                       mgc_add_5_0_5_0_5                                                                         0.9376  6.9142  
+        sobel:core/FRAME:acc#49.psp                                                                                                             0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#4                                                                                                      0.0000  6.9142  
+        sobel:core/slc(FRAME:acc#49.psp)#4.itm                                                                                                  0.0000  6.9142  
+        sobel:core/FRAME:not#47                       mgc_not_1                                                                                 0.0000  6.9142  
+        sobel:core/FRAME:not#47.itm                                                                                                             0.0000  6.9142  
+        sobel:core/FRAME:conc#42                                                                                                                0.0000  6.9142  
+        sobel:core/FRAME:conc#42.itm                                                                                                            0.0000  6.9142  
+        sobel:core/FRAME:acc#26                       mgc_add_5_0_5_1_7                                                                         0.6126  7.5269  
+        sobel:core/FRAME:acc#26.itm                                                                                                             0.0000  7.5269  
+        sobel:core/FRAME:slc#5                                                                                                                  0.0000  7.5269  
+        sobel:core/FRAME:slc#5.itm                                                                                                              0.0000  7.5269  
+        sobel:core/FRAME:not#52                       mgc_not_1                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:not#52.itm                                                                                                             0.0000  7.5269  
+        sobel:core/conc#117                                                                                                                     0.0000  7.5269  
+        sobel:core/conc#117.itm                                                                                                                 0.0000  7.5269  
+        sobel:core/FRAME:acc#19                       mgc_add_3_0_3_0_4                                                                         0.7609  8.2878  
+        sobel:core/FRAME:acc#19.itm                                                                                                             0.0000  8.2878  
+        sobel:core/FRAME:acc#20                       mgc_add_4_0_4_0_5                                                                         0.8536  9.1413  
+        sobel:core/FRAME:acc#20.itm                                                                                                             0.0000  9.1413  
+        sobel:core/FRAME:acc#21                       mgc_add_5_0_5_1_7                                                                         0.6126  9.7540  
+        sobel:core/FRAME:acc#21.itm                                                                                                             0.0000  9.7540  
+        sobel:core/FRAME:acc#22                       mgc_add_6_0_5_1_8                                                                         0.6934  10.4474 
+        sobel:core/FRAME:acc#22.itm                                                                                                             0.0000  10.4474 
+        sobel:core/FRAME:acc#23                       mgc_add_9_0_8_1_10                                                                        1.0725  11.5198 
+        sobel:core/FRAME:acc#23.itm                                                                                                             0.0000  11.5198 
+        sobel:core/FRAME:acc#24                       mgc_add_11_0_10_1_12                                                                      1.2076  12.7275 
+        sobel:core/FRAME:acc#24.sdt                                                                                                             0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1                                                                                                      0.0000  12.7275 
+        sobel:core/slc(FRAME:acc#24.sdt)#1.itm                                                                                                  0.0000  12.7275 
+        sobel:core/FRAME:acc                          mgc_add_12_0_11_1_12                                                                      1.4360  14.1634 
+        sobel:core/FRAME:acc.psp                                                                                                                0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp)#2                                                                                                         0.0000  14.1634 
+        sobel:core/slc(FRAME:acc.psp)#2.itm                                                                                                     0.0000  14.1634 
+        sobel:core/FRAME:or#3                         mgc_or_5_2                                                                                0.2679  14.4313 
+        sobel:core/FRAME:or#3.itm                                                                                                               0.0000  14.4313 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2   mgc_reg_pos_5_1_0_0_0_1_1                                                                 0.0000  14.4313 
+                                                                                                                                                                
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                      Port                          Slack (Delay) Messages 
+      --------------------------------------------- --------------------------- ------- ------- --------
+      sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm) slc(regs.regs(1).sva)#2.itm 20.0000  0.0000          
+      sobel:core/reg(ACC1:slc(regs.regs(2))#15.itm) slc(regs.regs(1).sva)#1.itm 20.0000  0.0000          
+      sobel:core/reg(ACC1:slc(regs.regs(2))#16.itm) slc(regs.regs(1).sva).itm   20.0000  0.0000          
+      sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm) slc(regs.regs(1).sva)#5.itm 20.0000  0.0000          
+      sobel:core/reg(ACC1:slc(regs.regs(2))#12.itm) slc(regs.regs(1).sva)#4.itm 20.0000  0.0000          
+      sobel:core/reg(ACC1:slc(regs.regs(2))#13.itm) slc(regs.regs(1).sva)#3.itm 20.0000  0.0000          
+      sobel:core/reg(ACC1:slc(regs.regs(2)).itm)    slc(regs.regs(1).sva)#8.itm 20.0000  0.0000          
+      sobel:core/reg(ACC1:slc(regs.regs(2))#9.itm)  slc(regs.regs(1).sva)#7.itm 20.0000  0.0000          
+      sobel:core/reg(ACC1:slc(regs.regs(2))#10.itm) slc(regs.regs(1).sva)#6.itm 20.0000  0.0000          
+      sobel:core/reg(regs.regs(1).sva)              vin:rsc:mgc_in_wire.d        5.5687 14.4313          
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)     FRAME:or.itm                 5.5687 14.4313          
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#1   slc(FRAME:acc.psp)#1.itm     5.8366 14.1634          
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2   FRAME:or#3.itm               5.5687 14.4313          
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3   FRAME:or#4.itm               5.5687 14.4313          
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#4   slc(FRAME:acc#61.psp)#1.itm  5.8366 14.1634          
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#5   slc(FRAME:acc#37.sdt).itm    7.2725 12.7275          
+      sobel                                         vout:rsc.z                  20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                   13     6 
+    -                   12    10 
+    -                   11     3 
+    -                   10     5 
+    -                    8     2 
+    -                    7     9 
+    -                    6     1 
+    -                    5     9 
+    -                    4    12 
+    mul                          
+    -                   11     3 
+    -                    9     3 
+    not                          
+    -                   10     9 
+    -                    3    12 
+    -                    1    11 
+    or                           
+    -                    2     3 
+    read_port                    
+    -                   90     1 
+    reg                          
+    -                   90     1 
+    -                   10    10 
+    -                    9     1 
+    -                    5     1 
+    -                    4     1 
+    -                    1     2 
+    write_port                   
+    -                   30     1 
+    
+  End of Report
diff --git a/Sobel/sobel.v1/rtl.v b/Sobel/sobel.v1/rtl.v
new file mode 100644
index 0000000..75c0023
--- /dev/null
+++ b/Sobel/sobel.v1/rtl.v
@@ -0,0 +1,565 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 13:49:49 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [89:0] regs_regs_1_sva;
+  reg [9:0] ACC1_slc_regs_regs_2_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_9_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_10_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_11_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_12_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_13_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_14_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_15_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_16_itm;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  wire [11:0] nl_reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  reg [3:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_1;
+  reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_2;
+  reg reg_vout_rsc_mgc_out_stdreg_d_tmp_3;
+  reg [8:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_4;
+  reg reg_vout_rsc_mgc_out_stdreg_d_tmp_5;
+  wire [12:0] ACC1_acc_psp_sva;
+  wire [13:0] nl_ACC1_acc_psp_sva;
+  wire [6:0] FRAME_acc_41_sdt;
+  wire [7:0] nl_FRAME_acc_41_sdt;
+  wire [11:0] FRAME_acc_psp;
+  wire [12:0] nl_FRAME_acc_psp;
+  wire [11:0] FRAME_acc_24_sdt;
+  wire [12:0] nl_FRAME_acc_24_sdt;
+  wire [11:0] FRAME_acc_61_psp;
+  wire [12:0] nl_FRAME_acc_61_psp;
+  wire [11:0] FRAME_acc_37_sdt;
+  wire [12:0] nl_FRAME_acc_37_sdt;
+  wire [4:0] FRAME_acc_47_psp;
+  wire [5:0] nl_FRAME_acc_47_psp;
+  wire [5:0] FRAME_acc_13_sdt;
+  wire [6:0] nl_FRAME_acc_13_sdt;
+  wire [12:0] ACC1_acc_43_psp_sva;
+  wire [13:0] nl_ACC1_acc_43_psp_sva;
+  wire [4:0] FRAME_acc_55_psp;
+  wire [5:0] nl_FRAME_acc_55_psp;
+  wire [5:0] FRAME_acc_31_sdt;
+  wire [6:0] nl_FRAME_acc_31_sdt;
+  wire [12:0] ACC1_acc_42_psp_sva;
+  wire [13:0] nl_ACC1_acc_42_psp_sva;
+  wire [4:0] FRAME_acc_49_psp;
+  wire [5:0] nl_FRAME_acc_49_psp;
+  wire [5:0] FRAME_acc_18_sdt;
+  wire [6:0] nl_FRAME_acc_18_sdt;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign vout_rsc_mgc_out_stdreg_d = {reg_vout_rsc_mgc_out_stdreg_d_tmp , reg_vout_rsc_mgc_out_stdreg_d_tmp_1
+      , reg_vout_rsc_mgc_out_stdreg_d_tmp_2 , reg_vout_rsc_mgc_out_stdreg_d_tmp_3
+      , reg_vout_rsc_mgc_out_stdreg_d_tmp_4 , reg_vout_rsc_mgc_out_stdreg_d_tmp_5};
+  assign nl_ACC1_acc_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_itm
+      , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_9_itm , 1'b1})))) , 1'b1})
+      + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[29:20]))
+      , 1'b1}) + conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[89:80])) , 1'b1})))) ,
+      1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_10_itm) +
+      conv_s2u_10_11(~ (vin_rsc_mgc_in_wire_d[59:50]))) , 1'b1});
+  assign ACC1_acc_psp_sva = nl_ACC1_acc_psp_sva[12:0];
+  assign nl_FRAME_acc_41_sdt = conv_s2s_5_7(readslicef_6_5_1((conv_s2s_5_6({1'b1
+      , (~ (ACC1_acc_psp_sva[8:6])) , 1'b1}) + conv_s2s_4_6({(FRAME_acc_47_psp[4:2])
+      , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_47_psp[1:0]) , (FRAME_acc_13_sdt[0])
+      , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_47_psp[4:2])) , (~ (FRAME_acc_47_psp[4]))})))))}))))
+      + conv_u2s_5_7(signext_5_3({(ACC1_acc_psp_sva[12]) , (ACC1_acc_psp_sva[12])
+      , (FRAME_acc_47_psp[4])}));
+  assign FRAME_acc_41_sdt = nl_FRAME_acc_41_sdt[6:0];
+  assign nl_FRAME_acc_psp = ({(conv_u2u_3_4(signext_3_1(ACC1_acc_42_psp_sva[12]))
+      + conv_u2u_2_4(signext_2_1(ACC1_acc_42_psp_sva[12]))) , (ACC1_acc_42_psp_sva[12])
+      , 1'b0 , (conv_u2u_2_4(signext_2_1(ACC1_acc_42_psp_sva[12])) + conv_u2u_3_4({(ACC1_acc_42_psp_sva[12])
+      , (ACC1_acc_42_psp_sva[12]) , (ACC1_acc_42_psp_sva[12])})) , (ACC1_acc_42_psp_sva[12])
+      , (ACC1_acc_42_psp_sva[12])}) + conv_s2u_11_12(FRAME_acc_24_sdt[11:1]);
+  assign FRAME_acc_psp = nl_FRAME_acc_psp[11:0];
+  assign nl_FRAME_acc_24_sdt = conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(signext_2_1(ACC1_acc_42_psp_sva[12]))
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_42_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_42_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (FRAME_acc_49_psp[4])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_49_psp[1:0])
+      , (FRAME_acc_18_sdt[0]) , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_49_psp[4:2]))
+      , (~ (FRAME_acc_49_psp[4]))})))))}) + conv_u2u_2_4(FRAME_acc_49_psp[3:2]))
+      + conv_u2u_3_5(~ (ACC1_acc_42_psp_sva[8:6]))) + ({4'b1001 , (FRAME_acc_49_psp[4])}))));
+  assign FRAME_acc_24_sdt = nl_FRAME_acc_24_sdt[11:0];
+  assign nl_FRAME_acc_61_psp = ({(conv_u2u_3_4(signext_3_1(ACC1_acc_43_psp_sva[12]))
+      + conv_u2u_2_4(signext_2_1(ACC1_acc_43_psp_sva[12]))) , (ACC1_acc_43_psp_sva[12])
+      , 1'b0 , (conv_u2u_2_4(signext_2_1(ACC1_acc_43_psp_sva[12])) + conv_u2u_3_4({(ACC1_acc_43_psp_sva[12])
+      , (ACC1_acc_43_psp_sva[12]) , (ACC1_acc_43_psp_sva[12])})) , (ACC1_acc_43_psp_sva[12])
+      , (ACC1_acc_43_psp_sva[12])}) + conv_s2u_11_12(FRAME_acc_37_sdt[11:1]);
+  assign FRAME_acc_61_psp = nl_FRAME_acc_61_psp[11:0];
+  assign nl_FRAME_acc_37_sdt = conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(signext_2_1(ACC1_acc_43_psp_sva[12]))
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_43_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_43_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (FRAME_acc_55_psp[4])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_55_psp[1:0])
+      , (FRAME_acc_31_sdt[0]) , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_55_psp[4:2]))
+      , (~ (FRAME_acc_55_psp[4]))})))))}) + conv_u2u_2_4(FRAME_acc_55_psp[3:2]))
+      + conv_u2u_3_5(~ (ACC1_acc_43_psp_sva[8:6]))) + ({4'b1001 , (FRAME_acc_55_psp[4])}))));
+  assign FRAME_acc_37_sdt = nl_FRAME_acc_37_sdt[11:0];
+  assign nl_FRAME_acc_47_psp = (FRAME_acc_13_sdt[5:1]) + 5'b10101;
+  assign FRAME_acc_47_psp = nl_FRAME_acc_47_psp[4:0];
+  assign nl_FRAME_acc_13_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_psp_sva[8:6])
+      + conv_u2u_3_4(~ (ACC1_acc_psp_sva[11:9]))) + conv_u2u_4_5({(~ (ACC1_acc_psp_sva[12]))
+      , (~ (ACC1_acc_psp_sva[5:3]))})) + conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_psp_sva[12])
+      , 1'b0 , (ACC1_acc_psp_sva[12])}) + conv_u2u_3_4(ACC1_acc_psp_sva[2:0]));
+  assign FRAME_acc_13_sdt = nl_FRAME_acc_13_sdt[5:0];
+  assign nl_ACC1_acc_43_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_14_itm
+      , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_15_itm , 1'b1})))) , 1'b1})
+      + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[9:0]))
+      , 1'b1}) + conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[69:60])) , 1'b1})))) ,
+      1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_16_itm) +
+      conv_s2u_10_11(~ (vin_rsc_mgc_in_wire_d[39:30]))) , 1'b1});
+  assign ACC1_acc_43_psp_sva = nl_ACC1_acc_43_psp_sva[12:0];
+  assign nl_FRAME_acc_55_psp = (FRAME_acc_31_sdt[5:1]) + 5'b10101;
+  assign FRAME_acc_55_psp = nl_FRAME_acc_55_psp[4:0];
+  assign nl_FRAME_acc_31_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_43_psp_sva[8:6])
+      + conv_u2u_3_4(~ (ACC1_acc_43_psp_sva[11:9]))) + conv_u2u_4_5({(~ (ACC1_acc_43_psp_sva[12]))
+      , (~ (ACC1_acc_43_psp_sva[5:3]))})) + conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_43_psp_sva[12])
+      , 1'b0 , (ACC1_acc_43_psp_sva[12])}) + conv_u2u_3_4(ACC1_acc_43_psp_sva[2:0]));
+  assign FRAME_acc_31_sdt = nl_FRAME_acc_31_sdt[5:0];
+  assign nl_ACC1_acc_42_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_11_itm
+      , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_12_itm , 1'b1})))) , 1'b1})
+      + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[19:10]))
+      , 1'b1}) + conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[79:70])) , 1'b1})))) ,
+      1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_13_itm) +
+      conv_s2u_10_11(~ (vin_rsc_mgc_in_wire_d[49:40]))) , 1'b1});
+  assign ACC1_acc_42_psp_sva = nl_ACC1_acc_42_psp_sva[12:0];
+  assign nl_FRAME_acc_49_psp = (FRAME_acc_18_sdt[5:1]) + 5'b10101;
+  assign FRAME_acc_49_psp = nl_FRAME_acc_49_psp[4:0];
+  assign nl_FRAME_acc_18_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_42_psp_sva[8:6])
+      + conv_u2u_3_4(~ (ACC1_acc_42_psp_sva[11:9]))) + conv_u2u_4_5({(~ (ACC1_acc_42_psp_sva[12]))
+      , (~ (ACC1_acc_42_psp_sva[5:3]))})) + conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_42_psp_sva[12])
+      , 1'b0 , (ACC1_acc_42_psp_sva[12])}) + conv_u2u_3_4(ACC1_acc_42_psp_sva[2:0]));
+  assign FRAME_acc_18_sdt = nl_FRAME_acc_18_sdt[5:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      ACC1_slc_regs_regs_2_14_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_15_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_16_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_11_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_12_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_13_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_9_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_10_itm <= 10'b0;
+      regs_regs_1_sva <= 90'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= 4'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= 5'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= 1'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_4 <= 9'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_5 <= 1'b0;
+    end
+    else begin
+      if ( en ) begin
+        ACC1_slc_regs_regs_2_14_itm <= regs_regs_1_sva[9:0];
+        ACC1_slc_regs_regs_2_15_itm <= regs_regs_1_sva[69:60];
+        ACC1_slc_regs_regs_2_16_itm <= regs_regs_1_sva[39:30];
+        ACC1_slc_regs_regs_2_11_itm <= regs_regs_1_sva[19:10];
+        ACC1_slc_regs_regs_2_12_itm <= regs_regs_1_sva[79:70];
+        ACC1_slc_regs_regs_2_13_itm <= regs_regs_1_sva[49:40];
+        ACC1_slc_regs_regs_2_itm <= regs_regs_1_sva[29:20];
+        ACC1_slc_regs_regs_2_9_itm <= regs_regs_1_sva[89:80];
+        ACC1_slc_regs_regs_2_10_itm <= regs_regs_1_sva[59:50];
+        regs_regs_1_sva <= vin_rsc_mgc_in_wire_d;
+        reg_vout_rsc_mgc_out_stdreg_d_tmp <= ((conv_u2u_20_10(conv_u2u_2_10(signext_2_1(ACC1_acc_psp_sva[12]))
+            * 10'b111000111) + conv_u2u_9_10(conv_u2u_18_9(conv_u2u_3_9(ACC1_acc_psp_sva[11:9])
+            * 9'b111001))) + (conv_u2s_9_10({(ACC1_acc_psp_sva[12]) , 2'b0 , (signext_6_4({(ACC1_acc_psp_sva[12])
+            , (ACC1_acc_psp_sva[5:3])}))}) + conv_s2s_8_10({(conv_s2u_4_5(FRAME_acc_41_sdt[6:3])
+            + conv_u2u_3_5(ACC1_acc_psp_sva[8:6])) , (FRAME_acc_41_sdt[2:0])})))
+            | ({7'b0 , (FRAME_acc_psp[11:9])});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= FRAME_acc_psp[8:5];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= (FRAME_acc_psp[4:0]) | ({3'b0 , (FRAME_acc_61_psp[11:10])});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= (FRAME_acc_24_sdt[0]) | (FRAME_acc_61_psp[9]);
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_4 <= FRAME_acc_61_psp[8:0];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_5 <= FRAME_acc_37_sdt[0];
+      end
+    end
+  end
+
+  function [11:0] readslicef_13_12_1;
+    input [12:0] vector;
+    reg [12:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_13_12_1 = tmp[11:0];
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [4:0] readslicef_6_5_1;
+    input [5:0] vector;
+    reg [5:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_6_5_1 = tmp[4:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [5:0] signext_6_4;
+    input [3:0] vector;
+  begin
+    signext_6_4= {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_s2u_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2u_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v1/rtl.v.psr b/Sobel/sobel.v1/rtl.v.psr
new file mode 100644
index 0000000..59b05aa
--- /dev/null
+++ b/Sobel/sobel.v1/rtl.v.psr
@@ -0,0 +1,289 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v1/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v1/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v1/rtl.v}} -format verilog
+   setup_design -design=sobel
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'sobel': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'sobel': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'sobel'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'sobel'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to vout_rsc_z(29:0)
+   report_timing -from en -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from vin_rsc_z(89:0) -to vout_rsc_z(29:0)
+   report_timing -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock clk] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock en] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'sobel'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'sobel'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v1 mapped.v]
+          puts "-- Writing mapped netlist for 'sobel' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v1 gate.v]
+          set gate_sdf [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v1 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/Sobel/sobel.v1/rtl.v.psr_timing b/Sobel/sobel.v1/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/Sobel/sobel.v1/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/Sobel/sobel.v1/rtl.v_order.txt b/Sobel/sobel.v1/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/Sobel/sobel.v1/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/Sobel/sobel.v1/rtl_mgc_ioport.v b/Sobel/sobel.v1/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v1/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v1/rtl_mgc_ioport_v2001.v b/Sobel/sobel.v1/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v1/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v1/schedule.gnt b/Sobel/sobel.v1/schedule.gnt
new file mode 100644
index 0000000..3f14d21
--- /dev/null
+++ b/Sobel/sobel.v1/schedule.gnt
@@ -0,0 +1,322 @@
+set a(0-17) {NAME FRAME:p:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-16 XREFS 772 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-21 {}}} SUCCS {{258 0 0-21 {}}} CYCLES {}}
+set a(0-18) {NAME asn(regs.regs(1))#1 TYPE ASSIGN PAR 0-16 XREFS 773 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-21 {}}} SUCCS {{258 0 0-21 {}}} CYCLES {}}
+set a(0-19) {NAME asn(regs.regs(0))#1 TYPE ASSIGN PAR 0-16 XREFS 774 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-21 {}}} SUCCS {{258 0 0-21 {}}} CYCLES {}}
+set a(0-20) {NAME FRAME:asn(exit:FRAME) TYPE ASSIGN PAR 0-16 XREFS 775 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-21 {}}} SUCCS {{259 0 0-21 {}}} CYCLES {}}
+set a(0-22) {NAME FRAME:asn TYPE ASSIGN PAR 0-21 XREFS 776 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-331 {}}} SUCCS {{259 0 0-23 {}} {256 0 0-331 {}}} CYCLES {}}
+set a(0-23) {NAME FRAME:select TYPE SELECT PAR 0-21 XREFS 777 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{259 0 0-22 {}}} SUCCS {} CYCLES {}}
+set a(0-24) {NAME SHIFT:if:else:else:else:asn(regs.regs(1)) TYPE ASSIGN PAR 0-21 XREFS 778 LOC {0 1.0 0 1.0 0 1.0 2 0.089073775} PREDS {{262 0 0-324 {}}} SUCCS {{256 0 0-324 {}} {258 0 0-325 {}}} CYCLES {}}
+set a(0-25) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,90) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_read(vin:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-21 XREFS 779 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {} SUCCS {{258 0 0-35 {}} {258 0 0-38 {}} {258 0 0-50 {}} {258 0 0-66 {}} {258 0 0-69 {}} {258 0 0-81 {}} {258 0 0-97 {}} {258 0 0-100 {}} {258 0 0-112 {}} {258 0 0-324 {}}} CYCLES {}}
+set a(0-26) {NAME ACC1:asn TYPE ASSIGN PAR 0-21 XREFS 780 LOC {0 1.0 0 1.0 0 1.0 1 0.2043437} PREDS {{262 0 0-325 {}}} SUCCS {{259 0 0-27 {}} {256 0 0-325 {}}} CYCLES {}}
+set a(0-27) {NAME ACC1:slc(regs.regs(2)) TYPE READSLICE PAR 0-21 XREFS 781 LOC {0 1.0 0 1.0 0 1.0 1 0.2043437} PREDS {{259 0 0-26 {}}} SUCCS {{259 0 0-28 {}}} CYCLES {}}
+set a(0-28) {NAME ACC1:conc#33 TYPE CONCATENATE PAR 0-21 XREFS 782 LOC {0 1.0 1 0.2043437 1 0.2043437 1 0.2043437} PREDS {{259 0 0-27 {}}} SUCCS {{258 0 0-32 {}}} CYCLES {}}
+set a(0-29) {NAME ACC1:asn#11 TYPE ASSIGN PAR 0-21 XREFS 783 LOC {0 1.0 0 1.0 0 1.0 1 0.2043437} PREDS {{262 0 0-325 {}}} SUCCS {{259 0 0-30 {}} {256 0 0-325 {}}} CYCLES {}}
+set a(0-30) {NAME ACC1:slc(regs.regs(2))#9 TYPE READSLICE PAR 0-21 XREFS 784 LOC {0 1.0 0 1.0 0 1.0 1 0.2043437} PREDS {{259 0 0-29 {}}} SUCCS {{259 0 0-31 {}}} CYCLES {}}
+set a(0-31) {NAME ACC1:conc#34 TYPE CONCATENATE PAR 0-21 XREFS 785 LOC {0 1.0 1 0.2043437 1 0.2043437 1 0.2043437} PREDS {{259 0 0-30 {}}} SUCCS {{259 0 0-32 {}}} CYCLES {}}
+set a(0-32) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#45 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-21 XREFS 786 LOC {1 0.0 1 0.2043437 1 0.2043437 1 0.27971445637342834 1 0.27971445637342834} PREDS {{258 0 0-28 {}} {259 0 0-31 {}}} SUCCS {{259 0 0-33 {}}} CYCLES {}}
+set a(0-33) {NAME ACC1:slc#1 TYPE READSLICE PAR 0-21 XREFS 787 LOC {1 0.0753708 1 0.2797145 1 0.2797145 1 0.2797145} PREDS {{259 0 0-32 {}}} SUCCS {{259 0 0-34 {}}} CYCLES {}}
+set a(0-34) {NAME ACC1:conc#37 TYPE CONCATENATE PAR 0-21 XREFS 788 LOC {1 0.0753708 1 0.2797145 1 0.2797145 1 0.2797145} PREDS {{259 0 0-33 {}}} SUCCS {{258 0 0-44 {}}} CYCLES {}}
+set a(0-35) {NAME ACC1:slc(regs.regs(0)) TYPE READSLICE PAR 0-21 XREFS 789 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.2043437} PREDS {{258 0 0-25 {}}} SUCCS {{259 0 0-36 {}}} CYCLES {}}
+set a(0-36) {NAME ACC1:not TYPE NOT PAR 0-21 XREFS 790 LOC {1 0.0 1 0.2043437 1 0.2043437 1 0.2043437} PREDS {{259 0 0-35 {}}} SUCCS {{259 0 0-37 {}}} CYCLES {}}
+set a(0-37) {NAME ACC1:conc#31 TYPE CONCATENATE PAR 0-21 XREFS 791 LOC {1 0.0 1 0.2043437 1 0.2043437 1 0.2043437} PREDS {{259 0 0-36 {}}} SUCCS {{258 0 0-41 {}}} CYCLES {}}
+set a(0-38) {NAME ACC1:slc(regs.regs(0))#9 TYPE READSLICE PAR 0-21 XREFS 792 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.2043437} PREDS {{258 0 0-25 {}}} SUCCS {{259 0 0-39 {}}} CYCLES {}}
+set a(0-39) {NAME ACC1:not#20 TYPE NOT PAR 0-21 XREFS 793 LOC {1 0.0 1 0.2043437 1 0.2043437 1 0.2043437} PREDS {{259 0 0-38 {}}} SUCCS {{259 0 0-40 {}}} CYCLES {}}
+set a(0-40) {NAME ACC1:conc#32 TYPE CONCATENATE PAR 0-21 XREFS 794 LOC {1 0.0 1 0.2043437 1 0.2043437 1 0.2043437} PREDS {{259 0 0-39 {}}} SUCCS {{259 0 0-41 {}}} CYCLES {}}
+set a(0-41) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#44 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-21 XREFS 795 LOC {1 0.0 1 0.2043437 1 0.2043437 1 0.27971445637342834 1 0.27971445637342834} PREDS {{258 0 0-37 {}} {259 0 0-40 {}}} SUCCS {{259 0 0-42 {}}} CYCLES {}}
+set a(0-42) {NAME ACC1:slc#3 TYPE READSLICE PAR 0-21 XREFS 796 LOC {1 0.0753708 1 0.2797145 1 0.2797145 1 0.2797145} PREDS {{259 0 0-41 {}}} SUCCS {{259 0 0-43 {}}} CYCLES {}}
+set a(0-43) {NAME ACC1:conc#38 TYPE CONCATENATE PAR 0-21 XREFS 797 LOC {1 0.0753708 1 0.2797145 1 0.2797145 1 0.2797145} PREDS {{259 0 0-42 {}}} SUCCS {{259 0 0-44 {}}} CYCLES {}}
+set a(0-44) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 9 NAME ACC1:acc#47 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-21 XREFS 798 LOC {1 0.0753708 1 0.2797145 1 0.2797145 1 0.3592027034997777 1 0.3592027034997777} PREDS {{258 0 0-34 {}} {259 0 0-43 {}}} SUCCS {{259 0 0-45 {}}} CYCLES {}}
+set a(0-45) {NAME ACC1:slc TYPE READSLICE PAR 0-21 XREFS 799 LOC {1 0.15485905 1 0.35920274999999996 1 0.35920274999999996 1 0.35920274999999996} PREDS {{259 0 0-44 {}}} SUCCS {{258 0 0-56 {}}} CYCLES {}}
+set a(0-46) {NAME ACC1:asn#12 TYPE ASSIGN PAR 0-21 XREFS 800 LOC {0 1.0 0 1.0 0 1.0 1 0.2797145} PREDS {{262 0 0-325 {}}} SUCCS {{259 0 0-47 {}} {256 0 0-325 {}}} CYCLES {}}
+set a(0-47) {NAME ACC1:slc(regs.regs(2))#10 TYPE READSLICE PAR 0-21 XREFS 801 LOC {0 1.0 0 1.0 0 1.0 1 0.2797145} PREDS {{259 0 0-46 {}}} SUCCS {{259 0 0-48 {}}} CYCLES {}}
+set a(0-48) {NAME ACC1:conc#35 TYPE CONCATENATE PAR 0-21 XREFS 802 LOC {0 1.0 1 0.2797145 1 0.2797145 1 0.2797145} PREDS {{259 0 0-47 {}}} SUCCS {{259 0 0-49 {}}} CYCLES {}}
+set a(0-49) {NAME ACC1:conc TYPE CONCATENATE PAR 0-21 XREFS 803 LOC {0 1.0 1 0.2797145 1 0.2797145 1 0.2797145} PREDS {{259 0 0-48 {}}} SUCCS {{258 0 0-54 {}}} CYCLES {}}
+set a(0-50) {NAME ACC1:slc(regs.regs(0))#10 TYPE READSLICE PAR 0-21 XREFS 804 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.2797145} PREDS {{258 0 0-25 {}}} SUCCS {{259 0 0-51 {}}} CYCLES {}}
+set a(0-51) {NAME ACC1:not#21 TYPE NOT PAR 0-21 XREFS 805 LOC {1 0.0 1 0.2797145 1 0.2797145 1 0.2797145} PREDS {{259 0 0-50 {}}} SUCCS {{259 0 0-52 {}}} CYCLES {}}
+set a(0-52) {NAME ACC1:conc#26 TYPE CONCATENATE PAR 0-21 XREFS 806 LOC {1 0.0 1 0.2797145 1 0.2797145 1 0.2797145} PREDS {{259 0 0-51 {}}} SUCCS {{259 0 0-53 {}}} CYCLES {}}
+set a(0-53) {NAME ACC1:conc#36 TYPE CONCATENATE PAR 0-21 XREFS 807 LOC {1 0.0 1 0.2797145 1 0.2797145 1 0.2797145} PREDS {{259 0 0-52 {}}} SUCCS {{259 0 0-54 {}}} CYCLES {}}
+set a(0-54) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 9 NAME ACC1:acc#46 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-21 XREFS 808 LOC {1 0.0 1 0.2797145 1 0.2797145 1 0.3592027034997777 1 0.3592027034997777} PREDS {{258 0 0-49 {}} {259 0 0-53 {}}} SUCCS {{259 0 0-55 {}}} CYCLES {}}
+set a(0-55) {NAME ACC1:slc#2 TYPE READSLICE PAR 0-21 XREFS 809 LOC {1 0.07948825 1 0.35920274999999996 1 0.35920274999999996 1 0.35920274999999996} PREDS {{259 0 0-54 {}}} SUCCS {{259 0 0-56 {}}} CYCLES {}}
+set a(0-56) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 9 NAME ACC1:acc TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-21 XREFS 810 LOC {1 0.15485905 1 0.35920274999999996 1 0.35920274999999996 1 0.4386909534997776 1 0.4386909534997776} PREDS {{258 0 0-45 {}} {259 0 0-55 {}}} SUCCS {{258 0 0-119 {}} {258 0 0-120 {}} {258 0 0-123 {}} {258 0 0-125 {}} {258 0 0-129 {}} {258 0 0-131 {}} {258 0 0-134 {}} {258 0 0-266 {}} {258 0 0-269 {}} {258 0 0-272 {}} {258 0 0-273 {}} {258 0 0-274 {}} {258 0 0-278 {}} {258 0 0-297 {}} {258 0 0-298 {}} {258 0 0-303 {}}} CYCLES {}}
+set a(0-57) {NAME ACC1:asn#13 TYPE ASSIGN PAR 0-21 XREFS 811 LOC {0 1.0 0 1.0 0 1.0 1 0.089073775} PREDS {{262 0 0-325 {}}} SUCCS {{259 0 0-58 {}} {256 0 0-325 {}}} CYCLES {}}
+set a(0-58) {NAME ACC1:slc(regs.regs(2))#11 TYPE READSLICE PAR 0-21 XREFS 812 LOC {0 1.0 0 1.0 0 1.0 1 0.089073775} PREDS {{259 0 0-57 {}}} SUCCS {{259 0 0-59 {}}} CYCLES {}}
+set a(0-59) {NAME ACC1:conc#41 TYPE CONCATENATE PAR 0-21 XREFS 813 LOC {0 1.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{259 0 0-58 {}}} SUCCS {{258 0 0-63 {}}} CYCLES {}}
+set a(0-60) {NAME ACC1:asn#14 TYPE ASSIGN PAR 0-21 XREFS 814 LOC {0 1.0 0 1.0 0 1.0 1 0.089073775} PREDS {{262 0 0-325 {}}} SUCCS {{259 0 0-61 {}} {256 0 0-325 {}}} CYCLES {}}
+set a(0-61) {NAME ACC1:slc(regs.regs(2))#12 TYPE READSLICE PAR 0-21 XREFS 815 LOC {0 1.0 0 1.0 0 1.0 1 0.089073775} PREDS {{259 0 0-60 {}}} SUCCS {{259 0 0-62 {}}} CYCLES {}}
+set a(0-62) {NAME ACC1:conc#42 TYPE CONCATENATE PAR 0-21 XREFS 816 LOC {0 1.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{259 0 0-61 {}}} SUCCS {{259 0 0-63 {}}} CYCLES {}}
+set a(0-63) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#49 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-21 XREFS 817 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.16444453137342835 1 0.16444453137342835} PREDS {{258 0 0-59 {}} {259 0 0-62 {}}} SUCCS {{259 0 0-64 {}}} CYCLES {}}
+set a(0-64) {NAME ACC1:slc#5 TYPE READSLICE PAR 0-21 XREFS 818 LOC {1 0.0753708 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-63 {}}} SUCCS {{259 0 0-65 {}}} CYCLES {}}
+set a(0-65) {NAME ACC1:conc#45 TYPE CONCATENATE PAR 0-21 XREFS 819 LOC {1 0.0753708 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-64 {}}} SUCCS {{258 0 0-75 {}}} CYCLES {}}
+set a(0-66) {NAME ACC1:slc(regs.regs(0))#11 TYPE READSLICE PAR 0-21 XREFS 820 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{258 0 0-25 {}}} SUCCS {{259 0 0-67 {}}} CYCLES {}}
+set a(0-67) {NAME ACC1:not#22 TYPE NOT PAR 0-21 XREFS 821 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{259 0 0-66 {}}} SUCCS {{259 0 0-68 {}}} CYCLES {}}
+set a(0-68) {NAME ACC1:conc#39 TYPE CONCATENATE PAR 0-21 XREFS 822 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{259 0 0-67 {}}} SUCCS {{258 0 0-72 {}}} CYCLES {}}
+set a(0-69) {NAME ACC1:slc(regs.regs(0))#12 TYPE READSLICE PAR 0-21 XREFS 823 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{258 0 0-25 {}}} SUCCS {{259 0 0-70 {}}} CYCLES {}}
+set a(0-70) {NAME ACC1:not#23 TYPE NOT PAR 0-21 XREFS 824 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{259 0 0-69 {}}} SUCCS {{259 0 0-71 {}}} CYCLES {}}
+set a(0-71) {NAME ACC1:conc#40 TYPE CONCATENATE PAR 0-21 XREFS 825 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{259 0 0-70 {}}} SUCCS {{259 0 0-72 {}}} CYCLES {}}
+set a(0-72) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#48 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-21 XREFS 826 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.16444453137342835 1 0.16444453137342835} PREDS {{258 0 0-68 {}} {259 0 0-71 {}}} SUCCS {{259 0 0-73 {}}} CYCLES {}}
+set a(0-73) {NAME ACC1:slc#4 TYPE READSLICE PAR 0-21 XREFS 827 LOC {1 0.0753708 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-72 {}}} SUCCS {{259 0 0-74 {}}} CYCLES {}}
+set a(0-74) {NAME ACC1:conc#46 TYPE CONCATENATE PAR 0-21 XREFS 828 LOC {1 0.0753708 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-73 {}}} SUCCS {{259 0 0-75 {}}} CYCLES {}}
+set a(0-75) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 9 NAME ACC1:acc#51 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-21 XREFS 829 LOC {1 0.0753708 1 0.16444457499999998 1 0.16444457499999998 1 0.24393277849977765 1 0.24393277849977765} PREDS {{258 0 0-65 {}} {259 0 0-74 {}}} SUCCS {{259 0 0-76 {}}} CYCLES {}}
+set a(0-76) {NAME ACC1:slc#7 TYPE READSLICE PAR 0-21 XREFS 830 LOC {1 0.15485905 1 0.243932825 1 0.243932825 1 0.243932825} PREDS {{259 0 0-75 {}}} SUCCS {{258 0 0-87 {}}} CYCLES {}}
+set a(0-77) {NAME ACC1:asn#15 TYPE ASSIGN PAR 0-21 XREFS 831 LOC {0 1.0 0 1.0 0 1.0 1 0.16444457499999998} PREDS {{262 0 0-325 {}}} SUCCS {{259 0 0-78 {}} {256 0 0-325 {}}} CYCLES {}}
+set a(0-78) {NAME ACC1:slc(regs.regs(2))#13 TYPE READSLICE PAR 0-21 XREFS 832 LOC {0 1.0 0 1.0 0 1.0 1 0.16444457499999998} PREDS {{259 0 0-77 {}}} SUCCS {{259 0 0-79 {}}} CYCLES {}}
+set a(0-79) {NAME ACC1:conc#27 TYPE CONCATENATE PAR 0-21 XREFS 833 LOC {0 1.0 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-78 {}}} SUCCS {{259 0 0-80 {}}} CYCLES {}}
+set a(0-80) {NAME ACC1:conc#43 TYPE CONCATENATE PAR 0-21 XREFS 834 LOC {0 1.0 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-79 {}}} SUCCS {{258 0 0-85 {}}} CYCLES {}}
+set a(0-81) {NAME ACC1:slc(regs.regs(0))#13 TYPE READSLICE PAR 0-21 XREFS 835 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.16444457499999998} PREDS {{258 0 0-25 {}}} SUCCS {{259 0 0-82 {}}} CYCLES {}}
+set a(0-82) {NAME ACC1:not#24 TYPE NOT PAR 0-21 XREFS 836 LOC {1 0.0 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-81 {}}} SUCCS {{259 0 0-83 {}}} CYCLES {}}
+set a(0-83) {NAME ACC1:conc#28 TYPE CONCATENATE PAR 0-21 XREFS 837 LOC {1 0.0 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-82 {}}} SUCCS {{259 0 0-84 {}}} CYCLES {}}
+set a(0-84) {NAME ACC1:conc#44 TYPE CONCATENATE PAR 0-21 XREFS 838 LOC {1 0.0 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-83 {}}} SUCCS {{259 0 0-85 {}}} CYCLES {}}
+set a(0-85) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 9 NAME ACC1:acc#50 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-21 XREFS 839 LOC {1 0.0 1 0.16444457499999998 1 0.16444457499999998 1 0.24393277849977765 1 0.24393277849977765} PREDS {{258 0 0-80 {}} {259 0 0-84 {}}} SUCCS {{259 0 0-86 {}}} CYCLES {}}
+set a(0-86) {NAME ACC1:slc#6 TYPE READSLICE PAR 0-21 XREFS 840 LOC {1 0.07948825 1 0.243932825 1 0.243932825 1 0.243932825} PREDS {{259 0 0-85 {}}} SUCCS {{259 0 0-87 {}}} CYCLES {}}
+set a(0-87) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 9 NAME ACC1:acc#42 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-21 XREFS 841 LOC {1 0.15485905 1 0.243932825 1 0.243932825 1 0.32342102849977766 1 0.32342102849977766} PREDS {{258 0 0-76 {}} {259 0 0-86 {}}} SUCCS {{258 0 0-138 {}} {258 0 0-139 {}} {258 0 0-142 {}} {258 0 0-144 {}} {258 0 0-148 {}} {258 0 0-150 {}} {258 0 0-153 {}} {258 0 0-157 {}} {258 0 0-158 {}} {258 0 0-160 {}} {258 0 0-163 {}} {258 0 0-164 {}} {258 0 0-166 {}} {258 0 0-170 {}} {258 0 0-173 {}} {258 0 0-175 {}} {258 0 0-192 {}}} CYCLES {}}
+set a(0-88) {NAME ACC1:asn#16 TYPE ASSIGN PAR 0-21 XREFS 842 LOC {0 1.0 0 1.0 0 1.0 1 0.089073775} PREDS {{262 0 0-325 {}}} SUCCS {{259 0 0-89 {}} {256 0 0-325 {}}} CYCLES {}}
+set a(0-89) {NAME ACC1:slc(regs.regs(2))#14 TYPE READSLICE PAR 0-21 XREFS 843 LOC {0 1.0 0 1.0 0 1.0 1 0.089073775} PREDS {{259 0 0-88 {}}} SUCCS {{259 0 0-90 {}}} CYCLES {}}
+set a(0-90) {NAME ACC1:conc#49 TYPE CONCATENATE PAR 0-21 XREFS 844 LOC {0 1.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{259 0 0-89 {}}} SUCCS {{258 0 0-94 {}}} CYCLES {}}
+set a(0-91) {NAME ACC1:asn#17 TYPE ASSIGN PAR 0-21 XREFS 845 LOC {0 1.0 0 1.0 0 1.0 1 0.089073775} PREDS {{262 0 0-325 {}}} SUCCS {{259 0 0-92 {}} {256 0 0-325 {}}} CYCLES {}}
+set a(0-92) {NAME ACC1:slc(regs.regs(2))#15 TYPE READSLICE PAR 0-21 XREFS 846 LOC {0 1.0 0 1.0 0 1.0 1 0.089073775} PREDS {{259 0 0-91 {}}} SUCCS {{259 0 0-93 {}}} CYCLES {}}
+set a(0-93) {NAME ACC1:conc#50 TYPE CONCATENATE PAR 0-21 XREFS 847 LOC {0 1.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{259 0 0-92 {}}} SUCCS {{259 0 0-94 {}}} CYCLES {}}
+set a(0-94) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#53 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-21 XREFS 848 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.16444453137342835 1 0.16444453137342835} PREDS {{258 0 0-90 {}} {259 0 0-93 {}}} SUCCS {{259 0 0-95 {}}} CYCLES {}}
+set a(0-95) {NAME ACC1:slc#9 TYPE READSLICE PAR 0-21 XREFS 849 LOC {1 0.0753708 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-94 {}}} SUCCS {{259 0 0-96 {}}} CYCLES {}}
+set a(0-96) {NAME ACC1:conc#53 TYPE CONCATENATE PAR 0-21 XREFS 850 LOC {1 0.0753708 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-95 {}}} SUCCS {{258 0 0-106 {}}} CYCLES {}}
+set a(0-97) {NAME ACC1:slc(regs.regs(0))#14 TYPE READSLICE PAR 0-21 XREFS 851 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{258 0 0-25 {}}} SUCCS {{259 0 0-98 {}}} CYCLES {}}
+set a(0-98) {NAME ACC1:not#25 TYPE NOT PAR 0-21 XREFS 852 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{259 0 0-97 {}}} SUCCS {{259 0 0-99 {}}} CYCLES {}}
+set a(0-99) {NAME ACC1:conc#47 TYPE CONCATENATE PAR 0-21 XREFS 853 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{259 0 0-98 {}}} SUCCS {{258 0 0-103 {}}} CYCLES {}}
+set a(0-100) {NAME ACC1:slc(regs.regs(0))#15 TYPE READSLICE PAR 0-21 XREFS 854 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{258 0 0-25 {}}} SUCCS {{259 0 0-101 {}}} CYCLES {}}
+set a(0-101) {NAME ACC1:not#26 TYPE NOT PAR 0-21 XREFS 855 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{259 0 0-100 {}}} SUCCS {{259 0 0-102 {}}} CYCLES {}}
+set a(0-102) {NAME ACC1:conc#48 TYPE CONCATENATE PAR 0-21 XREFS 856 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.089073775} PREDS {{259 0 0-101 {}}} SUCCS {{259 0 0-103 {}}} CYCLES {}}
+set a(0-103) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#52 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-21 XREFS 857 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.16444453137342835 1 0.16444453137342835} PREDS {{258 0 0-99 {}} {259 0 0-102 {}}} SUCCS {{259 0 0-104 {}}} CYCLES {}}
+set a(0-104) {NAME ACC1:slc#8 TYPE READSLICE PAR 0-21 XREFS 858 LOC {1 0.0753708 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-103 {}}} SUCCS {{259 0 0-105 {}}} CYCLES {}}
+set a(0-105) {NAME ACC1:conc#54 TYPE CONCATENATE PAR 0-21 XREFS 859 LOC {1 0.0753708 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-104 {}}} SUCCS {{259 0 0-106 {}}} CYCLES {}}
+set a(0-106) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 9 NAME ACC1:acc#55 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-21 XREFS 860 LOC {1 0.0753708 1 0.16444457499999998 1 0.16444457499999998 1 0.24393277849977765 1 0.24393277849977765} PREDS {{258 0 0-96 {}} {259 0 0-105 {}}} SUCCS {{259 0 0-107 {}}} CYCLES {}}
+set a(0-107) {NAME ACC1:slc#11 TYPE READSLICE PAR 0-21 XREFS 861 LOC {1 0.15485905 1 0.243932825 1 0.243932825 1 0.243932825} PREDS {{259 0 0-106 {}}} SUCCS {{258 0 0-118 {}}} CYCLES {}}
+set a(0-108) {NAME ACC1:asn#18 TYPE ASSIGN PAR 0-21 XREFS 862 LOC {0 1.0 0 1.0 0 1.0 1 0.16444457499999998} PREDS {{262 0 0-325 {}}} SUCCS {{259 0 0-109 {}} {256 0 0-325 {}}} CYCLES {}}
+set a(0-109) {NAME ACC1:slc(regs.regs(2))#16 TYPE READSLICE PAR 0-21 XREFS 863 LOC {0 1.0 0 1.0 0 1.0 1 0.16444457499999998} PREDS {{259 0 0-108 {}}} SUCCS {{259 0 0-110 {}}} CYCLES {}}
+set a(0-110) {NAME ACC1:conc#29 TYPE CONCATENATE PAR 0-21 XREFS 864 LOC {0 1.0 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-109 {}}} SUCCS {{259 0 0-111 {}}} CYCLES {}}
+set a(0-111) {NAME ACC1:conc#51 TYPE CONCATENATE PAR 0-21 XREFS 865 LOC {0 1.0 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-110 {}}} SUCCS {{258 0 0-116 {}}} CYCLES {}}
+set a(0-112) {NAME ACC1:slc(regs.regs(0))#16 TYPE READSLICE PAR 0-21 XREFS 866 LOC {1 0.0 1 0.089073775 1 0.089073775 1 0.16444457499999998} PREDS {{258 0 0-25 {}}} SUCCS {{259 0 0-113 {}}} CYCLES {}}
+set a(0-113) {NAME ACC1:not#27 TYPE NOT PAR 0-21 XREFS 867 LOC {1 0.0 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-112 {}}} SUCCS {{259 0 0-114 {}}} CYCLES {}}
+set a(0-114) {NAME ACC1:conc#30 TYPE CONCATENATE PAR 0-21 XREFS 868 LOC {1 0.0 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-113 {}}} SUCCS {{259 0 0-115 {}}} CYCLES {}}
+set a(0-115) {NAME ACC1:conc#52 TYPE CONCATENATE PAR 0-21 XREFS 869 LOC {1 0.0 1 0.16444457499999998 1 0.16444457499999998 1 0.16444457499999998} PREDS {{259 0 0-114 {}}} SUCCS {{259 0 0-116 {}}} CYCLES {}}
+set a(0-116) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 9 NAME ACC1:acc#54 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-21 XREFS 870 LOC {1 0.0 1 0.16444457499999998 1 0.16444457499999998 1 0.24393277849977765 1 0.24393277849977765} PREDS {{258 0 0-111 {}} {259 0 0-115 {}}} SUCCS {{259 0 0-117 {}}} CYCLES {}}
+set a(0-117) {NAME ACC1:slc#10 TYPE READSLICE PAR 0-21 XREFS 871 LOC {1 0.07948825 1 0.243932825 1 0.243932825 1 0.243932825} PREDS {{259 0 0-116 {}}} SUCCS {{259 0 0-118 {}}} CYCLES {}}
+set a(0-118) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 9 NAME ACC1:acc#43 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-21 XREFS 872 LOC {1 0.15485905 1 0.243932825 1 0.243932825 1 0.32342102849977766 1 0.32342102849977766} PREDS {{258 0 0-107 {}} {259 0 0-117 {}}} SUCCS {{258 0 0-202 {}} {258 0 0-203 {}} {258 0 0-206 {}} {258 0 0-208 {}} {258 0 0-212 {}} {258 0 0-214 {}} {258 0 0-217 {}} {258 0 0-221 {}} {258 0 0-222 {}} {258 0 0-224 {}} {258 0 0-227 {}} {258 0 0-228 {}} {258 0 0-230 {}} {258 0 0-234 {}} {258 0 0-237 {}} {258 0 0-239 {}} {258 0 0-256 {}}} CYCLES {}}
+set a(0-119) {NAME FRAME:slc(ACC1:acc.psp)#2 TYPE READSLICE PAR 0-21 XREFS 873 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.438691} PREDS {{258 0 0-56 {}}} SUCCS {{258 0 0-122 {}}} CYCLES {}}
+set a(0-120) {NAME FRAME:slc(ACC1:acc.psp)#3 TYPE READSLICE PAR 0-21 XREFS 874 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.438691} PREDS {{258 0 0-56 {}}} SUCCS {{259 0 0-121 {}}} CYCLES {}}
+set a(0-121) {NAME FRAME:not#31 TYPE NOT PAR 0-21 XREFS 875 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.438691} PREDS {{259 0 0-120 {}}} SUCCS {{259 0 0-122 {}}} CYCLES {}}
+set a(0-122) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 8 NAME FRAME:acc#10 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-21 XREFS 876 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.4862471270708272 1 0.4862471270708272} PREDS {{258 0 0-119 {}} {259 0 0-121 {}}} SUCCS {{258 0 0-128 {}}} CYCLES {}}
+set a(0-123) {NAME FRAME:slc(ACC1:acc.psp)#4 TYPE READSLICE PAR 0-21 XREFS 877 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.486247175} PREDS {{258 0 0-56 {}}} SUCCS {{259 0 0-124 {}}} CYCLES {}}
+set a(0-124) {NAME FRAME:not#32 TYPE NOT PAR 0-21 XREFS 878 LOC {1 0.23434729999999998 1 0.486247175 1 0.486247175 1 0.486247175} PREDS {{259 0 0-123 {}}} SUCCS {{258 0 0-127 {}}} CYCLES {}}
+set a(0-125) {NAME FRAME:slc(ACC1:acc.psp)#5 TYPE READSLICE PAR 0-21 XREFS 879 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.486247175} PREDS {{258 0 0-56 {}}} SUCCS {{259 0 0-126 {}}} CYCLES {}}
+set a(0-126) {NAME FRAME:not#40 TYPE NOT PAR 0-21 XREFS 880 LOC {1 0.23434729999999998 1 0.486247175 1 0.486247175 1 0.486247175} PREDS {{259 0 0-125 {}}} SUCCS {{259 0 0-127 {}}} CYCLES {}}
+set a(0-127) {NAME FRAME:conc#34 TYPE CONCATENATE PAR 0-21 XREFS 881 LOC {1 0.23434729999999998 1 0.486247175 1 0.486247175 1 0.486247175} PREDS {{258 0 0-124 {}} {259 0 0-126 {}}} SUCCS {{259 0 0-128 {}}} CYCLES {}}
+set a(0-128) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 5 NAME FRAME:acc#12 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-21 XREFS 882 LOC {1 0.281903475 1 0.486247175 1 0.486247175 1 0.5395941951789505 1 0.5395941951789505} PREDS {{258 0 0-122 {}} {259 0 0-127 {}}} SUCCS {{258 0 0-136 {}}} CYCLES {}}
+set a(0-129) {NAME FRAME:slc(red)#1 TYPE READSLICE PAR 0-21 XREFS 883 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.451255025} PREDS {{258 0 0-56 {}}} SUCCS {{259 0 0-130 {}}} CYCLES {}}
+set a(0-130) {NAME FRAME:exs TYPE SIGNEXTEND PAR 0-21 XREFS 884 LOC {1 0.23434729999999998 1 0.451255025 1 0.451255025 1 0.451255025} PREDS {{259 0 0-129 {}}} SUCCS {{258 0 0-133 {}}} CYCLES {}}
+set a(0-131) {NAME FRAME:slc(ACC1:acc.psp) TYPE READSLICE PAR 0-21 XREFS 885 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.451255025} PREDS {{258 0 0-56 {}}} SUCCS {{259 0 0-132 {}}} CYCLES {}}
+set a(0-132) {NAME FRAME:conc TYPE CONCATENATE PAR 0-21 XREFS 886 LOC {1 0.23434729999999998 1 0.451255025 1 0.451255025 1 0.451255025} PREDS {{259 0 0-131 {}}} SUCCS {{259 0 0-133 {}}} CYCLES {}}
+set a(0-133) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 3 NAME FRAME:acc#9 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-21 XREFS 887 LOC {1 0.23434729999999998 1 0.451255025 1 0.451255025 1 0.4920380350894752 1 0.4920380350894752} PREDS {{258 0 0-130 {}} {259 0 0-132 {}}} SUCCS {{258 0 0-135 {}}} CYCLES {}}
+set a(0-134) {NAME FRAME:slc(ACC1:acc.psp)#1 TYPE READSLICE PAR 0-21 XREFS 888 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.49203807499999996} PREDS {{258 0 0-56 {}}} SUCCS {{259 0 0-135 {}}} CYCLES {}}
+set a(0-135) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 8 NAME FRAME:acc#11 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-21 XREFS 889 LOC {1 0.27513034999999997 1 0.49203807499999996 1 0.49203807499999996 1 0.5395942020708271 1 0.5395942020708271} PREDS {{258 0 0-133 {}} {259 0 0-134 {}}} SUCCS {{259 0 0-136 {}}} CYCLES {}}
+set a(0-136) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#13 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-21 XREFS 890 LOC {1 0.33525055 1 0.5395942499999999 1 0.5395942499999999 1 0.577883709496936 1 0.577883709496936} PREDS {{258 0 0-128 {}} {259 0 0-135 {}}} SUCCS {{259 0 0-137 {}}} CYCLES {}}
+set a(0-137) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-21 XREFS 891 LOC {1 0.37354004999999996 1 0.57788375 1 0.57788375 1 0.6413957234103025 1 0.6413957234103025} PREDS {{259 0 0-136 {}}} SUCCS {{258 0 0-282 {}} {258 0 0-283 {}} {258 0 0-285 {}} {258 0 0-287 {}} {258 0 0-299 {}}} CYCLES {}}
+set a(0-138) {NAME FRAME:slc(ACC1:acc#42.psp)#2 TYPE READSLICE PAR 0-21 XREFS 892 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.323421075} PREDS {{258 0 0-87 {}}} SUCCS {{258 0 0-141 {}}} CYCLES {}}
+set a(0-139) {NAME FRAME:slc(ACC1:acc#42.psp)#3 TYPE READSLICE PAR 0-21 XREFS 893 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.323421075} PREDS {{258 0 0-87 {}}} SUCCS {{259 0 0-140 {}}} CYCLES {}}
+set a(0-140) {NAME FRAME:not#33 TYPE NOT PAR 0-21 XREFS 894 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.323421075} PREDS {{259 0 0-139 {}}} SUCCS {{259 0 0-141 {}}} CYCLES {}}
+set a(0-141) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 8 NAME FRAME:acc#15 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-21 XREFS 895 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.3709772020708272 1 0.3709772020708272} PREDS {{258 0 0-138 {}} {259 0 0-140 {}}} SUCCS {{258 0 0-147 {}}} CYCLES {}}
+set a(0-142) {NAME FRAME:slc(ACC1:acc#42.psp)#4 TYPE READSLICE PAR 0-21 XREFS 896 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.37097725} PREDS {{258 0 0-87 {}}} SUCCS {{259 0 0-143 {}}} CYCLES {}}
+set a(0-143) {NAME FRAME:not#34 TYPE NOT PAR 0-21 XREFS 897 LOC {1 0.23434729999999998 1 0.37097725 1 0.37097725 1 0.37097725} PREDS {{259 0 0-142 {}}} SUCCS {{258 0 0-146 {}}} CYCLES {}}
+set a(0-144) {NAME FRAME:slc(ACC1:acc#42.psp)#5 TYPE READSLICE PAR 0-21 XREFS 898 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.37097725} PREDS {{258 0 0-87 {}}} SUCCS {{259 0 0-145 {}}} CYCLES {}}
+set a(0-145) {NAME FRAME:not#41 TYPE NOT PAR 0-21 XREFS 899 LOC {1 0.23434729999999998 1 0.37097725 1 0.37097725 1 0.37097725} PREDS {{259 0 0-144 {}}} SUCCS {{259 0 0-146 {}}} CYCLES {}}
+set a(0-146) {NAME FRAME:conc#35 TYPE CONCATENATE PAR 0-21 XREFS 900 LOC {1 0.23434729999999998 1 0.37097725 1 0.37097725 1 0.37097725} PREDS {{258 0 0-143 {}} {259 0 0-145 {}}} SUCCS {{259 0 0-147 {}}} CYCLES {}}
+set a(0-147) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 5 NAME FRAME:acc#17 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-21 XREFS 901 LOC {1 0.281903475 1 0.37097725 1 0.37097725 1 0.42432427017895047 1 0.42432427017895047} PREDS {{258 0 0-141 {}} {259 0 0-146 {}}} SUCCS {{258 0 0-155 {}}} CYCLES {}}
+set a(0-148) {NAME FRAME:slc(green)#1 TYPE READSLICE PAR 0-21 XREFS 902 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.3359851} PREDS {{258 0 0-87 {}}} SUCCS {{259 0 0-149 {}}} CYCLES {}}
+set a(0-149) {NAME FRAME:exs#12 TYPE SIGNEXTEND PAR 0-21 XREFS 903 LOC {1 0.23434729999999998 1 0.3359851 1 0.3359851 1 0.3359851} PREDS {{259 0 0-148 {}}} SUCCS {{258 0 0-152 {}}} CYCLES {}}
+set a(0-150) {NAME FRAME:slc(ACC1:acc#42.psp) TYPE READSLICE PAR 0-21 XREFS 904 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.3359851} PREDS {{258 0 0-87 {}}} SUCCS {{259 0 0-151 {}}} CYCLES {}}
+set a(0-151) {NAME FRAME:conc#26 TYPE CONCATENATE PAR 0-21 XREFS 905 LOC {1 0.23434729999999998 1 0.3359851 1 0.3359851 1 0.3359851} PREDS {{259 0 0-150 {}}} SUCCS {{259 0 0-152 {}}} CYCLES {}}
+set a(0-152) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 3 NAME FRAME:acc#14 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-21 XREFS 906 LOC {1 0.23434729999999998 1 0.3359851 1 0.3359851 1 0.3767681100894752 1 0.3767681100894752} PREDS {{258 0 0-149 {}} {259 0 0-151 {}}} SUCCS {{258 0 0-154 {}}} CYCLES {}}
+set a(0-153) {NAME FRAME:slc(ACC1:acc#42.psp)#1 TYPE READSLICE PAR 0-21 XREFS 907 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.37676814999999997} PREDS {{258 0 0-87 {}}} SUCCS {{259 0 0-154 {}}} CYCLES {}}
+set a(0-154) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 8 NAME FRAME:acc#16 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-21 XREFS 908 LOC {1 0.27513034999999997 1 0.37676814999999997 1 0.37676814999999997 1 0.42432427707082715 1 0.42432427707082715} PREDS {{258 0 0-152 {}} {259 0 0-153 {}}} SUCCS {{259 0 0-155 {}}} CYCLES {}}
+set a(0-155) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#18 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-21 XREFS 909 LOC {1 0.33525055 1 0.424324325 1 0.424324325 1 0.4626137844969361 1 0.4626137844969361} PREDS {{258 0 0-147 {}} {259 0 0-154 {}}} SUCCS {{259 0 0-156 {}}} CYCLES {}}
+set a(0-156) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc#2 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-21 XREFS 910 LOC {1 0.37354004999999996 1 0.462613825 1 0.462613825 1 0.5261257984103024 1 0.5261257984103024} PREDS {{259 0 0-155 {}}} SUCCS {{258 0 0-176 {}} {258 0 0-178 {}} {258 0 0-180 {}} {258 0 0-182 {}} {258 0 0-190 {}} {258 0 0-195 {}}} CYCLES {}}
+set a(0-157) {NAME slc(green)#4 TYPE READSLICE PAR 0-21 XREFS 911 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.799706975} PREDS {{258 0 0-87 {}}} SUCCS {{258 0 0-161 {}}} CYCLES {}}
+set a(0-158) {NAME slc(green)#5 TYPE READSLICE PAR 0-21 XREFS 912 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.799706975} PREDS {{258 0 0-87 {}}} SUCCS {{259 0 0-159 {}}} CYCLES {}}
+set a(0-159) {NAME FRAME:exs#7 TYPE SIGNEXTEND PAR 0-21 XREFS 913 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.799706975} PREDS {{259 0 0-158 {}}} SUCCS {{258 0 0-161 {}}} CYCLES {}}
+set a(0-160) {NAME slc(green)#1 TYPE READSLICE PAR 0-21 XREFS 914 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.799706975} PREDS {{258 0 0-87 {}}} SUCCS {{259 0 0-161 {}}} CYCLES {}}
+set a(0-161) {NAME FRAME:conc#8 TYPE CONCATENATE PAR 0-21 XREFS 915 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.799706975} PREDS {{258 0 0-159 {}} {258 0 0-157 {}} {259 0 0-160 {}}} SUCCS {{259 0 0-162 {}}} CYCLES {}}
+set a(0-162) {NAME FRAME:exs#6 TYPE SIGNEXTEND PAR 0-21 XREFS 916 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.799706975} PREDS {{259 0 0-161 {}}} SUCCS {{258 0 0-169 {}}} CYCLES {}}
+set a(0-163) {NAME slc(green)#2 TYPE READSLICE PAR 0-21 XREFS 917 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.799706975} PREDS {{258 0 0-87 {}}} SUCCS {{258 0 0-167 {}}} CYCLES {}}
+set a(0-164) {NAME slc(green)#3 TYPE READSLICE PAR 0-21 XREFS 918 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.799706975} PREDS {{258 0 0-87 {}}} SUCCS {{259 0 0-165 {}}} CYCLES {}}
+set a(0-165) {NAME FRAME:exs#5 TYPE SIGNEXTEND PAR 0-21 XREFS 919 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.799706975} PREDS {{259 0 0-164 {}}} SUCCS {{258 0 0-167 {}}} CYCLES {}}
+set a(0-166) {NAME slc(green) TYPE READSLICE PAR 0-21 XREFS 920 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.799706975} PREDS {{258 0 0-87 {}}} SUCCS {{259 0 0-167 {}}} CYCLES {}}
+set a(0-167) {NAME FRAME:conc#7 TYPE CONCATENATE PAR 0-21 XREFS 921 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.799706975} PREDS {{258 0 0-165 {}} {258 0 0-163 {}} {259 0 0-166 {}}} SUCCS {{259 0 0-168 {}}} CYCLES {}}
+set a(0-168) {NAME FRAME:exs#4 TYPE SIGNEXTEND PAR 0-21 XREFS 922 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.799706975} PREDS {{259 0 0-167 {}}} SUCCS {{259 0 0-169 {}}} CYCLES {}}
+set a(0-169) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,11,0,13) AREA_SCORE 13.23 QUANTITY 2 NAME FRAME:acc#25 TYPE ACCU DELAY {1.44 ns} LIBRARY_DELAY {1.44 ns} PAR 0-21 XREFS 923 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.8894538066459019 1 0.8894538066459019} PREDS {{258 0 0-162 {}} {259 0 0-168 {}}} SUCCS {{258 0 0-201 {}}} CYCLES {}}
+set a(0-170) {NAME FRAME:slc(green)#8 TYPE READSLICE PAR 0-21 XREFS 924 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.6237165} PREDS {{258 0 0-87 {}}} SUCCS {{259 0 0-171 {}}} CYCLES {}}
+set a(0-171) {NAME FRAME:exs#13 TYPE SIGNEXTEND PAR 0-21 XREFS 925 LOC {1 0.23434729999999998 1 0.6237165 1 0.6237165 1 0.6237165} PREDS {{259 0 0-170 {}}} SUCCS {{259 0 0-172 {}}} CYCLES {}}
+set a(0-172) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#2 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-21 XREFS 926 LOC {1 0.23434729999999998 1 0.6237165 1 0.6237165 1 0.81397648125 1 0.81397648125} PREDS {{259 0 0-171 {}}} SUCCS {{258 0 0-200 {}}} CYCLES {}}
+set a(0-173) {NAME FRAME:slc(green)#10 TYPE READSLICE PAR 0-21 XREFS 927 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.569066275} PREDS {{258 0 0-87 {}}} SUCCS {{259 0 0-174 {}}} CYCLES {}}
+set a(0-174) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#3 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-21 XREFS 928 LOC {1 0.23434729999999998 1 0.569066275 1 0.569066275 1 0.7469480671744312 1 0.7469480671744312} PREDS {{259 0 0-173 {}}} SUCCS {{258 0 0-199 {}}} CYCLES {}}
+set a(0-175) {NAME FRAME:slc(green)#11 TYPE READSLICE PAR 0-21 XREFS 929 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.7036081} PREDS {{258 0 0-87 {}}} SUCCS {{258 0 0-198 {}}} CYCLES {}}
+set a(0-176) {NAME FRAME:slc(acc.imod#2)#6 TYPE READSLICE PAR 0-21 XREFS 930 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.56441535} PREDS {{258 0 0-156 {}}} SUCCS {{259 0 0-177 {}}} CYCLES {}}
+set a(0-177) {NAME FRAME:not#17 TYPE NOT PAR 0-21 XREFS 931 LOC {1 0.437052075 1 0.56441535 1 0.56441535 1 0.56441535} PREDS {{259 0 0-176 {}}} SUCCS {{258 0 0-189 {}}} CYCLES {}}
+set a(0-178) {NAME FRAME:slc(acc.imod#2)#1 TYPE READSLICE PAR 0-21 XREFS 932 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{258 0 0-156 {}}} SUCCS {{259 0 0-179 {}}} CYCLES {}}
+set a(0-179) {NAME FRAME:conc#41 TYPE CONCATENATE PAR 0-21 XREFS 933 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{259 0 0-178 {}}} SUCCS {{258 0 0-185 {}}} CYCLES {}}
+set a(0-180) {NAME FRAME:slc(acc.imod#2)#2 TYPE READSLICE PAR 0-21 XREFS 934 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{258 0 0-156 {}}} SUCCS {{259 0 0-181 {}}} CYCLES {}}
+set a(0-181) {NAME FRAME:not#15 TYPE NOT PAR 0-21 XREFS 935 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{259 0 0-180 {}}} SUCCS {{258 0 0-184 {}}} CYCLES {}}
+set a(0-182) {NAME FRAME:slc(acc.imod#2) TYPE READSLICE PAR 0-21 XREFS 936 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{258 0 0-156 {}}} SUCCS {{259 0 0-183 {}}} CYCLES {}}
+set a(0-183) {NAME FRAME:not#14 TYPE NOT PAR 0-21 XREFS 937 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{259 0 0-182 {}}} SUCCS {{259 0 0-184 {}}} CYCLES {}}
+set a(0-184) {NAME FRAME:conc#42 TYPE CONCATENATE PAR 0-21 XREFS 938 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{258 0 0-181 {}} {259 0 0-183 {}}} SUCCS {{259 0 0-185 {}}} CYCLES {}}
+set a(0-185) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#26 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-21 XREFS 939 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.5644153094969361 1 0.5644153094969361} PREDS {{258 0 0-179 {}} {259 0 0-184 {}}} SUCCS {{259 0 0-186 {}}} CYCLES {}}
+set a(0-186) {NAME FRAME:slc#5 TYPE READSLICE PAR 0-21 XREFS 940 LOC {1 0.47534157499999996 1 0.56441535 1 0.56441535 1 0.56441535} PREDS {{259 0 0-185 {}}} SUCCS {{259 0 0-187 {}}} CYCLES {}}
+set a(0-187) {NAME FRAME:slc#3 TYPE READSLICE PAR 0-21 XREFS 941 LOC {1 0.47534157499999996 1 0.56441535 1 0.56441535 1 0.56441535} PREDS {{259 0 0-186 {}}} SUCCS {{259 0 0-188 {}}} CYCLES {}}
+set a(0-188) {NAME FRAME:not#18 TYPE NOT PAR 0-21 XREFS 942 LOC {1 0.47534157499999996 1 0.56441535 1 0.56441535 1 0.56441535} PREDS {{259 0 0-187 {}}} SUCCS {{259 0 0-189 {}}} CYCLES {}}
+set a(0-189) {NAME FRAME:conc#9 TYPE CONCATENATE PAR 0-21 XREFS 943 LOC {1 0.47534157499999996 1 0.56441535 1 0.56441535 1 0.56441535} PREDS {{258 0 0-177 {}} {259 0 0-188 {}}} SUCCS {{258 0 0-191 {}}} CYCLES {}}
+set a(0-190) {NAME FRAME:slc(acc.imod#2)#5 TYPE READSLICE PAR 0-21 XREFS 944 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.56441535} PREDS {{258 0 0-156 {}}} SUCCS {{259 0 0-191 {}}} CYCLES {}}
+set a(0-191) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 8 NAME FRAME:acc#19 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-21 XREFS 945 LOC {1 0.47534157499999996 1 0.56441535 1 0.56441535 1 0.6119714770708271 1 0.6119714770708271} PREDS {{258 0 0-189 {}} {259 0 0-190 {}}} SUCCS {{258 0 0-194 {}}} CYCLES {}}
+set a(0-192) {NAME FRAME:slc(green)#9 TYPE READSLICE PAR 0-21 XREFS 946 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.611971525} PREDS {{258 0 0-87 {}}} SUCCS {{259 0 0-193 {}}} CYCLES {}}
+set a(0-193) {NAME FRAME:not#16 TYPE NOT PAR 0-21 XREFS 947 LOC {1 0.23434729999999998 1 0.611971525 1 0.611971525 1 0.611971525} PREDS {{259 0 0-192 {}}} SUCCS {{259 0 0-194 {}}} CYCLES {}}
+set a(0-194) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 5 NAME FRAME:acc#20 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-21 XREFS 948 LOC {1 0.5228977499999999 1 0.611971525 1 0.611971525 1 0.6653185451789505 1 0.6653185451789505} PREDS {{258 0 0-191 {}} {259 0 0-193 {}}} SUCCS {{258 0 0-197 {}}} CYCLES {}}
+set a(0-195) {NAME FRAME:slc(acc.imod#2)#4 TYPE READSLICE PAR 0-21 XREFS 949 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.6653186} PREDS {{258 0 0-156 {}}} SUCCS {{259 0 0-196 {}}} CYCLES {}}
+set a(0-196) {NAME FRAME:conc#39 TYPE CONCATENATE PAR 0-21 XREFS 950 LOC {1 0.437052075 1 0.6653186 1 0.6653186 1 0.6653186} PREDS {{259 0 0-195 {}}} SUCCS {{259 0 0-197 {}}} CYCLES {}}
+set a(0-197) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#21 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-21 XREFS 951 LOC {1 0.576244825 1 0.6653186 1 0.6653186 1 0.7036080594969361 1 0.7036080594969361} PREDS {{258 0 0-194 {}} {259 0 0-196 {}}} SUCCS {{259 0 0-198 {}}} CYCLES {}}
+set a(0-198) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 2 NAME FRAME:acc#22 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-21 XREFS 952 LOC {1 0.6145343249999999 1 0.7036081 1 0.7036081 1 0.7469480657468814 1 0.7469480657468814} PREDS {{258 0 0-175 {}} {259 0 0-197 {}}} SUCCS {{259 0 0-199 {}}} CYCLES {}}
+set a(0-199) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#23 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-21 XREFS 953 LOC {1 0.6578743499999999 1 0.746948125 1 0.746948125 1 0.8139764818650199 1 0.8139764818650199} PREDS {{258 0 0-174 {}} {259 0 0-198 {}}} SUCCS {{259 0 0-200 {}}} CYCLES {}}
+set a(0-200) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,10,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME FRAME:acc#24 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-21 XREFS 954 LOC {1 0.7249027499999999 1 0.813976525 1 0.813976525 1 0.8894538093138832 1 0.8894538093138832} PREDS {{258 0 0-172 {}} {259 0 0-199 {}}} SUCCS {{259 0 0-201 {}}} CYCLES {}}
+set a(0-201) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,0,12,1,13) AREA_SCORE 14.00 QUANTITY 2 NAME FRAME:acc#3 TYPE ACCU DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-21 XREFS 955 LOC {1 0.800380075 1 0.88945385 1 0.88945385 1 0.9832574752166912 1 0.9832574752166912} PREDS {{258 0 0-169 {}} {259 0 0-200 {}}} SUCCS {{258 0 0-308 {}} {258 0 0-311 {}} {258 0 0-312 {}}} CYCLES {}}
+set a(0-202) {NAME FRAME:slc(ACC1:acc#43.psp)#2 TYPE READSLICE PAR 0-21 XREFS 956 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.323421075} PREDS {{258 0 0-118 {}}} SUCCS {{258 0 0-205 {}}} CYCLES {}}
+set a(0-203) {NAME FRAME:slc(ACC1:acc#43.psp)#3 TYPE READSLICE PAR 0-21 XREFS 957 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.323421075} PREDS {{258 0 0-118 {}}} SUCCS {{259 0 0-204 {}}} CYCLES {}}
+set a(0-204) {NAME FRAME:not#35 TYPE NOT PAR 0-21 XREFS 958 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.323421075} PREDS {{259 0 0-203 {}}} SUCCS {{259 0 0-205 {}}} CYCLES {}}
+set a(0-205) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 8 NAME FRAME:acc#28 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-21 XREFS 959 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.3709772020708272 1 0.3709772020708272} PREDS {{258 0 0-202 {}} {259 0 0-204 {}}} SUCCS {{258 0 0-211 {}}} CYCLES {}}
+set a(0-206) {NAME FRAME:slc(ACC1:acc#43.psp)#4 TYPE READSLICE PAR 0-21 XREFS 960 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.37097725} PREDS {{258 0 0-118 {}}} SUCCS {{259 0 0-207 {}}} CYCLES {}}
+set a(0-207) {NAME FRAME:not#36 TYPE NOT PAR 0-21 XREFS 961 LOC {1 0.23434729999999998 1 0.37097725 1 0.37097725 1 0.37097725} PREDS {{259 0 0-206 {}}} SUCCS {{258 0 0-210 {}}} CYCLES {}}
+set a(0-208) {NAME FRAME:slc(ACC1:acc#43.psp)#5 TYPE READSLICE PAR 0-21 XREFS 962 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.37097725} PREDS {{258 0 0-118 {}}} SUCCS {{259 0 0-209 {}}} CYCLES {}}
+set a(0-209) {NAME FRAME:not#42 TYPE NOT PAR 0-21 XREFS 963 LOC {1 0.23434729999999998 1 0.37097725 1 0.37097725 1 0.37097725} PREDS {{259 0 0-208 {}}} SUCCS {{259 0 0-210 {}}} CYCLES {}}
+set a(0-210) {NAME FRAME:conc#36 TYPE CONCATENATE PAR 0-21 XREFS 964 LOC {1 0.23434729999999998 1 0.37097725 1 0.37097725 1 0.37097725} PREDS {{258 0 0-207 {}} {259 0 0-209 {}}} SUCCS {{259 0 0-211 {}}} CYCLES {}}
+set a(0-211) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 5 NAME FRAME:acc#30 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-21 XREFS 965 LOC {1 0.281903475 1 0.37097725 1 0.37097725 1 0.42432427017895047 1 0.42432427017895047} PREDS {{258 0 0-205 {}} {259 0 0-210 {}}} SUCCS {{258 0 0-219 {}}} CYCLES {}}
+set a(0-212) {NAME FRAME:slc(blue)#1 TYPE READSLICE PAR 0-21 XREFS 966 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.3359851} PREDS {{258 0 0-118 {}}} SUCCS {{259 0 0-213 {}}} CYCLES {}}
+set a(0-213) {NAME FRAME:exs#14 TYPE SIGNEXTEND PAR 0-21 XREFS 967 LOC {1 0.23434729999999998 1 0.3359851 1 0.3359851 1 0.3359851} PREDS {{259 0 0-212 {}}} SUCCS {{258 0 0-216 {}}} CYCLES {}}
+set a(0-214) {NAME FRAME:slc(ACC1:acc#43.psp) TYPE READSLICE PAR 0-21 XREFS 968 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.3359851} PREDS {{258 0 0-118 {}}} SUCCS {{259 0 0-215 {}}} CYCLES {}}
+set a(0-215) {NAME FRAME:conc#28 TYPE CONCATENATE PAR 0-21 XREFS 969 LOC {1 0.23434729999999998 1 0.3359851 1 0.3359851 1 0.3359851} PREDS {{259 0 0-214 {}}} SUCCS {{259 0 0-216 {}}} CYCLES {}}
+set a(0-216) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 3 NAME FRAME:acc#27 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-21 XREFS 970 LOC {1 0.23434729999999998 1 0.3359851 1 0.3359851 1 0.3767681100894752 1 0.3767681100894752} PREDS {{258 0 0-213 {}} {259 0 0-215 {}}} SUCCS {{258 0 0-218 {}}} CYCLES {}}
+set a(0-217) {NAME FRAME:slc(ACC1:acc#43.psp)#1 TYPE READSLICE PAR 0-21 XREFS 971 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.37676814999999997} PREDS {{258 0 0-118 {}}} SUCCS {{259 0 0-218 {}}} CYCLES {}}
+set a(0-218) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 8 NAME FRAME:acc#29 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-21 XREFS 972 LOC {1 0.27513034999999997 1 0.37676814999999997 1 0.37676814999999997 1 0.42432427707082715 1 0.42432427707082715} PREDS {{258 0 0-216 {}} {259 0 0-217 {}}} SUCCS {{259 0 0-219 {}}} CYCLES {}}
+set a(0-219) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#31 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-21 XREFS 973 LOC {1 0.33525055 1 0.424324325 1 0.424324325 1 0.4626137844969361 1 0.4626137844969361} PREDS {{258 0 0-211 {}} {259 0 0-218 {}}} SUCCS {{259 0 0-220 {}}} CYCLES {}}
+set a(0-220) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc#4 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-21 XREFS 974 LOC {1 0.37354004999999996 1 0.462613825 1 0.462613825 1 0.5261257984103024 1 0.5261257984103024} PREDS {{259 0 0-219 {}}} SUCCS {{258 0 0-240 {}} {258 0 0-242 {}} {258 0 0-244 {}} {258 0 0-246 {}} {258 0 0-254 {}} {258 0 0-259 {}}} CYCLES {}}
+set a(0-221) {NAME slc(blue)#4 TYPE READSLICE PAR 0-21 XREFS 975 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.799706975} PREDS {{258 0 0-118 {}}} SUCCS {{258 0 0-225 {}}} CYCLES {}}
+set a(0-222) {NAME slc(blue)#5 TYPE READSLICE PAR 0-21 XREFS 976 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.799706975} PREDS {{258 0 0-118 {}}} SUCCS {{259 0 0-223 {}}} CYCLES {}}
+set a(0-223) {NAME FRAME:exs#11 TYPE SIGNEXTEND PAR 0-21 XREFS 977 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.799706975} PREDS {{259 0 0-222 {}}} SUCCS {{258 0 0-225 {}}} CYCLES {}}
+set a(0-224) {NAME slc(blue)#1 TYPE READSLICE PAR 0-21 XREFS 978 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.799706975} PREDS {{258 0 0-118 {}}} SUCCS {{259 0 0-225 {}}} CYCLES {}}
+set a(0-225) {NAME FRAME:conc#13 TYPE CONCATENATE PAR 0-21 XREFS 979 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.799706975} PREDS {{258 0 0-223 {}} {258 0 0-221 {}} {259 0 0-224 {}}} SUCCS {{259 0 0-226 {}}} CYCLES {}}
+set a(0-226) {NAME FRAME:exs#10 TYPE SIGNEXTEND PAR 0-21 XREFS 980 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.799706975} PREDS {{259 0 0-225 {}}} SUCCS {{258 0 0-233 {}}} CYCLES {}}
+set a(0-227) {NAME slc(blue)#2 TYPE READSLICE PAR 0-21 XREFS 981 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.799706975} PREDS {{258 0 0-118 {}}} SUCCS {{258 0 0-231 {}}} CYCLES {}}
+set a(0-228) {NAME slc(blue)#3 TYPE READSLICE PAR 0-21 XREFS 982 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.799706975} PREDS {{258 0 0-118 {}}} SUCCS {{259 0 0-229 {}}} CYCLES {}}
+set a(0-229) {NAME FRAME:exs#9 TYPE SIGNEXTEND PAR 0-21 XREFS 983 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.799706975} PREDS {{259 0 0-228 {}}} SUCCS {{258 0 0-231 {}}} CYCLES {}}
+set a(0-230) {NAME slc(blue) TYPE READSLICE PAR 0-21 XREFS 984 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.799706975} PREDS {{258 0 0-118 {}}} SUCCS {{259 0 0-231 {}}} CYCLES {}}
+set a(0-231) {NAME FRAME:conc#12 TYPE CONCATENATE PAR 0-21 XREFS 985 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.799706975} PREDS {{258 0 0-229 {}} {258 0 0-227 {}} {259 0 0-230 {}}} SUCCS {{259 0 0-232 {}}} CYCLES {}}
+set a(0-232) {NAME FRAME:exs#8 TYPE SIGNEXTEND PAR 0-21 XREFS 986 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.799706975} PREDS {{259 0 0-231 {}}} SUCCS {{259 0 0-233 {}}} CYCLES {}}
+set a(0-233) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,11,0,13) AREA_SCORE 13.23 QUANTITY 2 NAME FRAME:acc#38 TYPE ACCU DELAY {1.44 ns} LIBRARY_DELAY {1.44 ns} PAR 0-21 XREFS 987 LOC {1 0.23434729999999998 1 0.799706975 1 0.799706975 1 0.8894538066459019 1 0.8894538066459019} PREDS {{258 0 0-226 {}} {259 0 0-232 {}}} SUCCS {{258 0 0-265 {}}} CYCLES {}}
+set a(0-234) {NAME FRAME:slc(blue)#8 TYPE READSLICE PAR 0-21 XREFS 988 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.6237165} PREDS {{258 0 0-118 {}}} SUCCS {{259 0 0-235 {}}} CYCLES {}}
+set a(0-235) {NAME FRAME:exs#15 TYPE SIGNEXTEND PAR 0-21 XREFS 989 LOC {1 0.23434729999999998 1 0.6237165 1 0.6237165 1 0.6237165} PREDS {{259 0 0-234 {}}} SUCCS {{259 0 0-236 {}}} CYCLES {}}
+set a(0-236) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#4 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-21 XREFS 990 LOC {1 0.23434729999999998 1 0.6237165 1 0.6237165 1 0.81397648125 1 0.81397648125} PREDS {{259 0 0-235 {}}} SUCCS {{258 0 0-264 {}}} CYCLES {}}
+set a(0-237) {NAME FRAME:slc(blue)#10 TYPE READSLICE PAR 0-21 XREFS 991 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.569066275} PREDS {{258 0 0-118 {}}} SUCCS {{259 0 0-238 {}}} CYCLES {}}
+set a(0-238) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#5 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-21 XREFS 992 LOC {1 0.23434729999999998 1 0.569066275 1 0.569066275 1 0.7469480671744312 1 0.7469480671744312} PREDS {{259 0 0-237 {}}} SUCCS {{258 0 0-263 {}}} CYCLES {}}
+set a(0-239) {NAME FRAME:slc(blue)#11 TYPE READSLICE PAR 0-21 XREFS 993 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.7036081} PREDS {{258 0 0-118 {}}} SUCCS {{258 0 0-262 {}}} CYCLES {}}
+set a(0-240) {NAME FRAME:slc(acc.imod#4)#6 TYPE READSLICE PAR 0-21 XREFS 994 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.56441535} PREDS {{258 0 0-220 {}}} SUCCS {{259 0 0-241 {}}} CYCLES {}}
+set a(0-241) {NAME FRAME:not#26 TYPE NOT PAR 0-21 XREFS 995 LOC {1 0.437052075 1 0.56441535 1 0.56441535 1 0.56441535} PREDS {{259 0 0-240 {}}} SUCCS {{258 0 0-253 {}}} CYCLES {}}
+set a(0-242) {NAME FRAME:slc(acc.imod#4)#1 TYPE READSLICE PAR 0-21 XREFS 996 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{258 0 0-220 {}}} SUCCS {{259 0 0-243 {}}} CYCLES {}}
+set a(0-243) {NAME FRAME:conc#45 TYPE CONCATENATE PAR 0-21 XREFS 997 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{259 0 0-242 {}}} SUCCS {{258 0 0-249 {}}} CYCLES {}}
+set a(0-244) {NAME FRAME:slc(acc.imod#4)#2 TYPE READSLICE PAR 0-21 XREFS 998 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{258 0 0-220 {}}} SUCCS {{259 0 0-245 {}}} CYCLES {}}
+set a(0-245) {NAME FRAME:not#24 TYPE NOT PAR 0-21 XREFS 999 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{259 0 0-244 {}}} SUCCS {{258 0 0-248 {}}} CYCLES {}}
+set a(0-246) {NAME FRAME:slc(acc.imod#4) TYPE READSLICE PAR 0-21 XREFS 1000 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{258 0 0-220 {}}} SUCCS {{259 0 0-247 {}}} CYCLES {}}
+set a(0-247) {NAME FRAME:not#23 TYPE NOT PAR 0-21 XREFS 1001 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{259 0 0-246 {}}} SUCCS {{259 0 0-248 {}}} CYCLES {}}
+set a(0-248) {NAME FRAME:conc#46 TYPE CONCATENATE PAR 0-21 XREFS 1002 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.52612585} PREDS {{258 0 0-245 {}} {259 0 0-247 {}}} SUCCS {{259 0 0-249 {}}} CYCLES {}}
+set a(0-249) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#39 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-21 XREFS 1003 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.5644153094969361 1 0.5644153094969361} PREDS {{258 0 0-243 {}} {259 0 0-248 {}}} SUCCS {{259 0 0-250 {}}} CYCLES {}}
+set a(0-250) {NAME FRAME:slc#6 TYPE READSLICE PAR 0-21 XREFS 1004 LOC {1 0.47534157499999996 1 0.56441535 1 0.56441535 1 0.56441535} PREDS {{259 0 0-249 {}}} SUCCS {{259 0 0-251 {}}} CYCLES {}}
+set a(0-251) {NAME FRAME:slc#4 TYPE READSLICE PAR 0-21 XREFS 1005 LOC {1 0.47534157499999996 1 0.56441535 1 0.56441535 1 0.56441535} PREDS {{259 0 0-250 {}}} SUCCS {{259 0 0-252 {}}} CYCLES {}}
+set a(0-252) {NAME FRAME:not#27 TYPE NOT PAR 0-21 XREFS 1006 LOC {1 0.47534157499999996 1 0.56441535 1 0.56441535 1 0.56441535} PREDS {{259 0 0-251 {}}} SUCCS {{259 0 0-253 {}}} CYCLES {}}
+set a(0-253) {NAME FRAME:conc#14 TYPE CONCATENATE PAR 0-21 XREFS 1007 LOC {1 0.47534157499999996 1 0.56441535 1 0.56441535 1 0.56441535} PREDS {{258 0 0-241 {}} {259 0 0-252 {}}} SUCCS {{258 0 0-255 {}}} CYCLES {}}
+set a(0-254) {NAME FRAME:slc(acc.imod#4)#5 TYPE READSLICE PAR 0-21 XREFS 1008 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.56441535} PREDS {{258 0 0-220 {}}} SUCCS {{259 0 0-255 {}}} CYCLES {}}
+set a(0-255) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 8 NAME FRAME:acc#32 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-21 XREFS 1009 LOC {1 0.47534157499999996 1 0.56441535 1 0.56441535 1 0.6119714770708271 1 0.6119714770708271} PREDS {{258 0 0-253 {}} {259 0 0-254 {}}} SUCCS {{258 0 0-258 {}}} CYCLES {}}
+set a(0-256) {NAME FRAME:slc(blue)#9 TYPE READSLICE PAR 0-21 XREFS 1010 LOC {1 0.23434729999999998 1 0.323421075 1 0.323421075 1 0.611971525} PREDS {{258 0 0-118 {}}} SUCCS {{259 0 0-257 {}}} CYCLES {}}
+set a(0-257) {NAME FRAME:not#25 TYPE NOT PAR 0-21 XREFS 1011 LOC {1 0.23434729999999998 1 0.611971525 1 0.611971525 1 0.611971525} PREDS {{259 0 0-256 {}}} SUCCS {{259 0 0-258 {}}} CYCLES {}}
+set a(0-258) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 5 NAME FRAME:acc#33 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-21 XREFS 1012 LOC {1 0.5228977499999999 1 0.611971525 1 0.611971525 1 0.6653185451789505 1 0.6653185451789505} PREDS {{258 0 0-255 {}} {259 0 0-257 {}}} SUCCS {{258 0 0-261 {}}} CYCLES {}}
+set a(0-259) {NAME FRAME:slc(acc.imod#4)#4 TYPE READSLICE PAR 0-21 XREFS 1013 LOC {1 0.437052075 1 0.52612585 1 0.52612585 1 0.6653186} PREDS {{258 0 0-220 {}}} SUCCS {{259 0 0-260 {}}} CYCLES {}}
+set a(0-260) {NAME FRAME:conc#43 TYPE CONCATENATE PAR 0-21 XREFS 1014 LOC {1 0.437052075 1 0.6653186 1 0.6653186 1 0.6653186} PREDS {{259 0 0-259 {}}} SUCCS {{259 0 0-261 {}}} CYCLES {}}
+set a(0-261) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#34 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-21 XREFS 1015 LOC {1 0.576244825 1 0.6653186 1 0.6653186 1 0.7036080594969361 1 0.7036080594969361} PREDS {{258 0 0-258 {}} {259 0 0-260 {}}} SUCCS {{259 0 0-262 {}}} CYCLES {}}
+set a(0-262) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 2 NAME FRAME:acc#35 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-21 XREFS 1016 LOC {1 0.6145343249999999 1 0.7036081 1 0.7036081 1 0.7469480657468814 1 0.7469480657468814} PREDS {{258 0 0-239 {}} {259 0 0-261 {}}} SUCCS {{259 0 0-263 {}}} CYCLES {}}
+set a(0-263) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#36 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-21 XREFS 1017 LOC {1 0.6578743499999999 1 0.746948125 1 0.746948125 1 0.8139764818650199 1 0.8139764818650199} PREDS {{258 0 0-238 {}} {259 0 0-262 {}}} SUCCS {{259 0 0-264 {}}} CYCLES {}}
+set a(0-264) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,10,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME FRAME:acc#37 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-21 XREFS 1018 LOC {1 0.7249027499999999 1 0.813976525 1 0.813976525 1 0.8894538093138832 1 0.8894538093138832} PREDS {{258 0 0-236 {}} {259 0 0-263 {}}} SUCCS {{259 0 0-265 {}}} CYCLES {}}
+set a(0-265) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,0,12,1,13) AREA_SCORE 14.00 QUANTITY 2 NAME FRAME:acc#4 TYPE ACCU DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-21 XREFS 1019 LOC {1 0.800380075 1 0.88945385 1 0.88945385 1 0.9832574752166912 1 0.9832574752166912} PREDS {{258 0 0-233 {}} {259 0 0-264 {}}} SUCCS {{258 0 0-313 {}} {258 0 0-316 {}}} CYCLES {}}
+set a(0-266) {NAME FRAME:slc(red)#8 TYPE READSLICE PAR 0-21 XREFS 1020 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.6303189499999999} PREDS {{258 0 0-56 {}}} SUCCS {{259 0 0-267 {}}} CYCLES {}}
+set a(0-267) {NAME FRAME:exs#16 TYPE SIGNEXTEND PAR 0-21 XREFS 1021 LOC {1 0.23434729999999998 1 0.6303189499999999 1 0.6303189499999999 1 0.6303189499999999} PREDS {{259 0 0-266 {}}} SUCCS {{259 0 0-268 {}}} CYCLES {}}
+set a(0-268) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-21 XREFS 1022 LOC {1 0.23434729999999998 1 0.6303189499999999 1 0.6303189499999999 1 0.8205789312499999 1 0.8205789312499999} PREDS {{259 0 0-267 {}}} SUCCS {{258 0 0-271 {}}} CYCLES {}}
+set a(0-269) {NAME FRAME:slc(ACC1:acc.psp)#13 TYPE READSLICE PAR 0-21 XREFS 1023 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.642697125} PREDS {{258 0 0-56 {}}} SUCCS {{259 0 0-270 {}}} CYCLES {}}
+set a(0-270) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#7 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-21 XREFS 1024 LOC {1 0.23434729999999998 1 0.642697125 1 0.642697125 1 0.8205789171744312 1 0.8205789171744312} PREDS {{259 0 0-269 {}}} SUCCS {{259 0 0-271 {}}} CYCLES {}}
+set a(0-271) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,10) AREA_SCORE 11.24 QUANTITY 2 NAME FRAME:acc#44 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-21 XREFS 1025 LOC {1 0.424607325 1 0.820578975 1 0.820578975 1 0.9019182033364113 1 0.9019182033364113} PREDS {{258 0 0-268 {}} {259 0 0-270 {}}} SUCCS {{258 0 0-307 {}}} CYCLES {}}
+set a(0-272) {NAME FRAME:slc(ACC1:acc.psp)#15 TYPE READSLICE PAR 0-21 XREFS 1026 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.8348898499999999} PREDS {{258 0 0-56 {}}} SUCCS {{258 0 0-277 {}}} CYCLES {}}
+set a(0-273) {NAME slc(red)#5 TYPE READSLICE PAR 0-21 XREFS 1027 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.8348898499999999} PREDS {{258 0 0-56 {}}} SUCCS {{258 0 0-275 {}}} CYCLES {}}
+set a(0-274) {NAME FRAME:slc(ACC1:acc.psp)#9 TYPE READSLICE PAR 0-21 XREFS 1028 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.8348898499999999} PREDS {{258 0 0-56 {}}} SUCCS {{259 0 0-275 {}}} CYCLES {}}
+set a(0-275) {NAME FRAME:conc#32 TYPE CONCATENATE PAR 0-21 XREFS 1029 LOC {1 0.23434729999999998 1 0.8348898499999999 1 0.8348898499999999 1 0.8348898499999999} PREDS {{258 0 0-273 {}} {259 0 0-274 {}}} SUCCS {{259 0 0-276 {}}} CYCLES {}}
+set a(0-276) {NAME FRAME:exs#18 TYPE SIGNEXTEND PAR 0-21 XREFS 1030 LOC {1 0.23434729999999998 1 0.8348898499999999 1 0.8348898499999999 1 0.8348898499999999} PREDS {{259 0 0-275 {}}} SUCCS {{259 0 0-277 {}}} CYCLES {}}
+set a(0-277) {NAME FRAME:conc#38 TYPE CONCATENATE PAR 0-21 XREFS 1031 LOC {1 0.23434729999999998 1 0.8348898499999999 1 0.8348898499999999 1 0.8348898499999999} PREDS {{258 0 0-272 {}} {259 0 0-276 {}}} SUCCS {{258 0 0-306 {}}} CYCLES {}}
+set a(0-278) {NAME FRAME:slc(ACC1:acc.psp)#12 TYPE READSLICE PAR 0-21 XREFS 1032 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.679685275} PREDS {{258 0 0-56 {}}} SUCCS {{259 0 0-279 {}}} CYCLES {}}
+set a(0-279) {NAME FRAME:not#44 TYPE NOT PAR 0-21 XREFS 1033 LOC {1 0.23434729999999998 1 0.679685275 1 0.679685275 1 0.679685275} PREDS {{259 0 0-278 {}}} SUCCS {{259 0 0-280 {}}} CYCLES {}}
+set a(0-280) {NAME FRAME:conc#47 TYPE CONCATENATE PAR 0-21 XREFS 1034 LOC {1 0.23434729999999998 1 0.679685275 1 0.679685275 1 0.679685275} PREDS {{259 0 0-279 {}}} SUCCS {{259 0 0-281 {}}} CYCLES {}}
+set a(0-281) {NAME FRAME:conc#48 TYPE CONCATENATE PAR 0-21 XREFS 1035 LOC {1 0.23434729999999998 1 0.679685275 1 0.679685275 1 0.679685275} PREDS {{259 0 0-280 {}}} SUCCS {{258 0 0-295 {}}} CYCLES {}}
+set a(0-282) {NAME FRAME:slc(acc.imod) TYPE READSLICE PAR 0-21 XREFS 1036 LOC {1 0.437052075 1 0.641395775 1 0.641395775 1 0.679685275} PREDS {{258 0 0-137 {}}} SUCCS {{258 0 0-294 {}}} CYCLES {}}
+set a(0-283) {NAME FRAME:slc(acc.imod)#1 TYPE READSLICE PAR 0-21 XREFS 1037 LOC {1 0.437052075 1 0.641395775 1 0.641395775 1 0.641395775} PREDS {{258 0 0-137 {}}} SUCCS {{259 0 0-284 {}}} CYCLES {}}
+set a(0-284) {NAME FRAME:conc#51 TYPE CONCATENATE PAR 0-21 XREFS 1038 LOC {1 0.437052075 1 0.641395775 1 0.641395775 1 0.641395775} PREDS {{259 0 0-283 {}}} SUCCS {{258 0 0-290 {}}} CYCLES {}}
+set a(0-285) {NAME FRAME:slc(acc.imod)#2 TYPE READSLICE PAR 0-21 XREFS 1039 LOC {1 0.437052075 1 0.641395775 1 0.641395775 1 0.641395775} PREDS {{258 0 0-137 {}}} SUCCS {{259 0 0-286 {}}} CYCLES {}}
+set a(0-286) {NAME FRAME:not#6 TYPE NOT PAR 0-21 XREFS 1040 LOC {1 0.437052075 1 0.641395775 1 0.641395775 1 0.641395775} PREDS {{259 0 0-285 {}}} SUCCS {{258 0 0-289 {}}} CYCLES {}}
+set a(0-287) {NAME FRAME:slc(acc.imod)#7 TYPE READSLICE PAR 0-21 XREFS 1041 LOC {1 0.437052075 1 0.641395775 1 0.641395775 1 0.641395775} PREDS {{258 0 0-137 {}}} SUCCS {{259 0 0-288 {}}} CYCLES {}}
+set a(0-288) {NAME FRAME:not#5 TYPE NOT PAR 0-21 XREFS 1042 LOC {1 0.437052075 1 0.641395775 1 0.641395775 1 0.641395775} PREDS {{259 0 0-287 {}}} SUCCS {{259 0 0-289 {}}} CYCLES {}}
+set a(0-289) {NAME FRAME:conc#52 TYPE CONCATENATE PAR 0-21 XREFS 1043 LOC {1 0.437052075 1 0.641395775 1 0.641395775 1 0.641395775} PREDS {{258 0 0-286 {}} {259 0 0-288 {}}} SUCCS {{259 0 0-290 {}}} CYCLES {}}
+set a(0-290) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#45 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-21 XREFS 1044 LOC {1 0.437052075 1 0.641395775 1 0.641395775 1 0.6796852344969361 1 0.6796852344969361} PREDS {{258 0 0-284 {}} {259 0 0-289 {}}} SUCCS {{259 0 0-291 {}}} CYCLES {}}
+set a(0-291) {NAME FRAME:slc#8 TYPE READSLICE PAR 0-21 XREFS 1045 LOC {1 0.47534157499999996 1 0.679685275 1 0.679685275 1 0.679685275} PREDS {{259 0 0-290 {}}} SUCCS {{259 0 0-292 {}}} CYCLES {}}
+set a(0-292) {NAME FRAME:slc#2 TYPE READSLICE PAR 0-21 XREFS 1046 LOC {1 0.47534157499999996 1 0.679685275 1 0.679685275 1 0.679685275} PREDS {{259 0 0-291 {}}} SUCCS {{259 0 0-293 {}}} CYCLES {}}
+set a(0-293) {NAME FRAME:not#43 TYPE NOT PAR 0-21 XREFS 1047 LOC {1 0.47534157499999996 1 0.679685275 1 0.679685275 1 0.679685275} PREDS {{259 0 0-292 {}}} SUCCS {{259 0 0-294 {}}} CYCLES {}}
+set a(0-294) {NAME FRAME:conc#49 TYPE CONCATENATE PAR 0-21 XREFS 1048 LOC {1 0.47534157499999996 1 0.679685275 1 0.679685275 1 0.679685275} PREDS {{258 0 0-282 {}} {259 0 0-293 {}}} SUCCS {{259 0 0-295 {}}} CYCLES {}}
+set a(0-295) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,1,4,1,6) AREA_SCORE 6.00 QUANTITY 1 NAME FRAME:acc#40 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-21 XREFS 1049 LOC {1 0.47534157499999996 1 0.679685275 1 0.679685275 1 0.7282829808637015 1 0.7282829808637015} PREDS {{258 0 0-281 {}} {259 0 0-294 {}}} SUCCS {{259 0 0-296 {}}} CYCLES {}}
+set a(0-296) {NAME FRAME:slc#7 TYPE READSLICE PAR 0-21 XREFS 1050 LOC {1 0.523939325 1 0.728283025 1 0.728283025 1 0.728283025} PREDS {{259 0 0-295 {}}} SUCCS {{258 0 0-302 {}}} CYCLES {}}
+set a(0-297) {NAME slc(red)#3 TYPE READSLICE PAR 0-21 XREFS 1051 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.728283025} PREDS {{258 0 0-56 {}}} SUCCS {{258 0 0-300 {}}} CYCLES {}}
+set a(0-298) {NAME FRAME:slc(ACC1:acc.psp)#8 TYPE READSLICE PAR 0-21 XREFS 1052 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.728283025} PREDS {{258 0 0-56 {}}} SUCCS {{258 0 0-300 {}}} CYCLES {}}
+set a(0-299) {NAME FRAME:slc(acc.imod)#8 TYPE READSLICE PAR 0-21 XREFS 1053 LOC {1 0.437052075 1 0.641395775 1 0.641395775 1 0.728283025} PREDS {{258 0 0-137 {}}} SUCCS {{259 0 0-300 {}}} CYCLES {}}
+set a(0-300) {NAME FRAME:conc#31 TYPE CONCATENATE PAR 0-21 XREFS 1054 LOC {1 0.437052075 1 0.728283025 1 0.728283025 1 0.728283025} PREDS {{258 0 0-298 {}} {258 0 0-297 {}} {259 0 0-299 {}}} SUCCS {{259 0 0-301 {}}} CYCLES {}}
+set a(0-301) {NAME FRAME:exs#17 TYPE SIGNEXTEND PAR 0-21 XREFS 1055 LOC {1 0.437052075 1 0.728283025 1 0.728283025 1 0.728283025} PREDS {{259 0 0-300 {}}} SUCCS {{259 0 0-302 {}}} CYCLES {}}
+set a(0-302) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#41 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-21 XREFS 1056 LOC {1 0.523939325 1 0.728283025 1 0.728283025 1 0.766572484496936 1 0.766572484496936} PREDS {{258 0 0-296 {}} {259 0 0-301 {}}} SUCCS {{258 0 0-305 {}}} CYCLES {}}
+set a(0-303) {NAME FRAME:slc(ACC1:acc.psp)#14 TYPE READSLICE PAR 0-21 XREFS 1057 LOC {1 0.23434729999999998 1 0.438691 1 0.438691 1 0.766572525} PREDS {{258 0 0-56 {}}} SUCCS {{259 0 0-304 {}}} CYCLES {}}
+set a(0-304) {NAME FRAME:conc#37 TYPE CONCATENATE PAR 0-21 XREFS 1058 LOC {1 0.23434729999999998 1 0.766572525 1 0.766572525 1 0.766572525} PREDS {{259 0 0-303 {}}} SUCCS {{259 0 0-305 {}}} CYCLES {}}
+set a(0-305) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,1,6,0,8) AREA_SCORE 9.00 QUANTITY 1 NAME FRAME:acc#42 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-21 XREFS 1059 LOC {1 0.5622288249999999 1 0.766572525 1 0.766572525 1 0.8348898123898488 1 0.8348898123898488} PREDS {{258 0 0-302 {}} {259 0 0-304 {}}} SUCCS {{259 0 0-306 {}}} CYCLES {}}
+set a(0-306) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#43 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-21 XREFS 1060 LOC {1 0.6305461499999999 1 0.8348898499999999 1 0.8348898499999999 1 0.9019182068650199 1 0.9019182068650199} PREDS {{258 0 0-277 {}} {259 0 0-305 {}}} SUCCS {{259 0 0-307 {}}} CYCLES {}}
+set a(0-307) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,10) AREA_SCORE 11.24 QUANTITY 2 NAME FRAME:acc#8 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-21 XREFS 1061 LOC {1 0.69757455 1 0.9019182499999999 1 0.9019182499999999 1 0.9832574783364112 1 0.9832574783364112} PREDS {{258 0 0-271 {}} {259 0 0-306 {}}} SUCCS {{258 0 0-310 {}}} CYCLES {}}
+set a(0-308) {NAME green:slc(green) TYPE READSLICE PAR 0-21 XREFS 1062 LOC {1 0.8941837499999999 1 0.983257525 1 0.983257525 1 0.983257525} PREDS {{258 0 0-201 {}}} SUCCS {{259 0 0-309 {}}} CYCLES {}}
+set a(0-309) {NAME FRAME:exu TYPE PADZEROES PAR 0-21 XREFS 1063 LOC {1 0.8941837499999999 1 0.983257525 1 0.983257525 1 0.983257525} PREDS {{259 0 0-308 {}}} SUCCS {{259 0 0-310 {}}} CYCLES {}}
+set a(0-310) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(10,2) AREA_SCORE 7.30 QUANTITY 1 NAME FRAME:or TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-21 XREFS 1064 LOC {1 0.8941837499999999 1 0.983257525 1 0.983257525 1 0.9999999561077388 1 0.9999999561077388} PREDS {{258 0 0-307 {}} {259 0 0-309 {}}} SUCCS {{258 0 0-317 {}}} CYCLES {}}
+set a(0-311) {NAME green:slc(green)#1 TYPE READSLICE PAR 0-21 XREFS 1065 LOC {1 0.8941837499999999 1 0.983257525 1 0.983257525 1 1.0} PREDS {{258 0 0-201 {}}} SUCCS {{258 0 0-317 {}}} CYCLES {}}
+set a(0-312) {NAME green:slc(green)#2 TYPE READSLICE PAR 0-21 XREFS 1066 LOC {1 0.8941837499999999 1 0.983257525 1 0.983257525 1 0.983257525} PREDS {{258 0 0-201 {}}} SUCCS {{258 0 0-315 {}}} CYCLES {}}
+set a(0-313) {NAME blue:slc(blue) TYPE READSLICE PAR 0-21 XREFS 1067 LOC {1 0.8941837499999999 1 0.983257525 1 0.983257525 1 0.983257525} PREDS {{258 0 0-265 {}}} SUCCS {{259 0 0-314 {}}} CYCLES {}}
+set a(0-314) {NAME FRAME:exu#10 TYPE PADZEROES PAR 0-21 XREFS 1068 LOC {1 0.8941837499999999 1 0.983257525 1 0.983257525 1 0.983257525} PREDS {{259 0 0-313 {}}} SUCCS {{259 0 0-315 {}}} CYCLES {}}
+set a(0-315) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(6,2) AREA_SCORE 4.38 QUANTITY 1 NAME FRAME:or#3 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-21 XREFS 1069 LOC {1 0.8941837499999999 1 0.983257525 1 0.983257525 1 0.9999999561077388 1 0.9999999561077388} PREDS {{258 0 0-312 {}} {259 0 0-314 {}}} SUCCS {{258 0 0-317 {}}} CYCLES {}}
+set a(0-316) {NAME blue:slc(blue)#1 TYPE READSLICE PAR 0-21 XREFS 1070 LOC {1 0.8941837499999999 1 0.983257525 1 0.983257525 1 1.0} PREDS {{258 0 0-265 {}}} SUCCS {{259 0 0-317 {}}} CYCLES {}}
+set a(0-317) {NAME FRAME:conc#24 TYPE CONCATENATE PAR 0-21 XREFS 1071 LOC {1 0.910926225 1 1.0 1 1.0 1 1.0} PREDS {{258 0 0-315 {}} {258 0 0-311 {}} {258 0 0-310 {}} {259 0 0-316 {}}} SUCCS {{259 0 0-318 {}}} CYCLES {}}
+set a(0-318) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(2,30) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_write(vout:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-21 XREFS 1072 LOC {1 1.0 1 1.0 1 1.0 2 0.0 1 0.9999} PREDS {{260 0 0-318 {}} {259 0 0-317 {}}} SUCCS {{260 0 0-318 {}}} CYCLES {}}
+set a(0-319) {NAME FRAME:asn#3 TYPE ASSIGN PAR 0-21 XREFS 1073 LOC {0 1.0 1 0.79151865 1 0.79151865 2 0.79151865} PREDS {{262 0 0-331 {}}} SUCCS {{259 0 0-320 {}} {256 0 0-331 {}}} CYCLES {}}
+set a(0-320) {NAME FRAME:not#45 TYPE NOT PAR 0-21 XREFS 1074 LOC {1 0.0 1 0.79151865 1 0.79151865 2 0.79151865} PREDS {{259 0 0-319 {}}} SUCCS {{259 0 0-321 {}}} CYCLES {}}
+set a(0-321) {NAME FRAME:exs#19 TYPE SIGNEXTEND PAR 0-21 XREFS 1075 LOC {1 0.0 1 0.79151865 1 0.79151865 2 0.79151865} PREDS {{259 0 0-320 {}}} SUCCS {{259 0 0-322 {}}} CYCLES {}}
+set a(0-322) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(19,2) AREA_SCORE 13.87 QUANTITY 1 NAME FRAME:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-21 XREFS 1076 LOC {1 0.0 1 0.79151865 1 0.79151865 1 0.8079253812638539 2 0.8079253812638539} PREDS {{262 0 0-326 {}} {259 0 0-321 {}}} SUCCS {{259 0 0-323 {}} {256 0 0-326 {}}} CYCLES {}}
+set a(0-323) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(19,0,2,1,19) AREA_SCORE 20.00 QUANTITY 1 NAME FRAME:acc#6 TYPE ACCU DELAY {1.91 ns} LIBRARY_DELAY {1.91 ns} PAR 0-21 XREFS 1077 LOC {1 0.016406775 1 0.807925425 1 0.807925425 1 0.9271847410815965 2 0.9271847410815965} PREDS {{259 0 0-322 {}}} SUCCS {{258 0 0-326 {}} {258 0 0-327 {}}} CYCLES {}}
+set a(0-324) {NAME FRAME:asn(regs.regs(0).sva) TYPE ASSIGN PAR 0-21 XREFS 1078 LOC {1 0.0 1 0.089073775 1 0.089073775 2 1.0} PREDS {{260 0 0-324 {}} {256 0 0-24 {}} {258 0 0-25 {}}} SUCCS {{262 0 0-24 {}} {260 0 0-324 {}}} CYCLES {}}
+set a(0-325) {NAME FRAME:asn(regs.regs(1).sva) TYPE ASSIGN PAR 0-21 XREFS 1079 LOC {0 1.0 0 1.0 0 1.0 2 0.089073775} PREDS {{260 0 0-325 {}} {256 0 0-26 {}} {256 0 0-29 {}} {256 0 0-46 {}} {256 0 0-57 {}} {256 0 0-60 {}} {256 0 0-77 {}} {256 0 0-88 {}} {256 0 0-91 {}} {256 0 0-108 {}} {258 0 0-24 {}}} SUCCS {{262 0 0-26 {}} {262 0 0-29 {}} {262 0 0-46 {}} {262 0 0-57 {}} {262 0 0-60 {}} {262 0 0-77 {}} {262 0 0-88 {}} {262 0 0-91 {}} {262 0 0-108 {}} {260 0 0-325 {}}} CYCLES {}}
+set a(0-326) {NAME FRAME:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-21 XREFS 1080 LOC {1 0.13566614999999999 1 0.9271847999999999 1 0.9271847999999999 2 1.0} PREDS {{260 0 0-326 {}} {256 0 0-322 {}} {258 0 0-323 {}}} SUCCS {{262 0 0-322 {}} {260 0 0-326 {}}} CYCLES {}}
+set a(0-327) {NAME FRAME:p:slc(FRAME:p)#1 TYPE READSLICE PAR 0-21 XREFS 1081 LOC {1 0.13566614999999999 1 0.9271847999999999 1 0.9271847999999999 2 0.9271847999999999} PREDS {{258 0 0-323 {}}} SUCCS {{259 0 0-328 {}}} CYCLES {}}
+set a(0-328) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,7,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME FRAME:acc TYPE ACCU DELAY {1.17 ns} LIBRARY_DELAY {1.17 ns} PAR 0-21 XREFS 1082 LOC {1 0.13566614999999999 1 0.9271847999999999 1 0.9271847999999999 1 0.9999999617915235 2 0.9999999617915235} PREDS {{259 0 0-327 {}}} SUCCS {{259 0 0-329 {}}} CYCLES {}}
+set a(0-329) {NAME FRAME:slc TYPE READSLICE PAR 0-21 XREFS 1083 LOC {1 0.20848134999999998 1 1.0 1 1.0 2 1.0} PREDS {{259 0 0-328 {}}} SUCCS {{259 0 0-330 {}}} CYCLES {}}
+set a(0-330) {NAME FRAME:not TYPE NOT PAR 0-21 XREFS 1084 LOC {1 0.20848134999999998 1 1.0 1 1.0 2 1.0} PREDS {{259 0 0-329 {}}} SUCCS {{259 0 0-331 {}}} CYCLES {}}
+set a(0-331) {NAME FRAME:asn#4 TYPE ASSIGN PAR 0-21 XREFS 1085 LOC {1 0.20848134999999998 1 1.0 1 1.0 2 1.0} PREDS {{260 0 0-331 {}} {256 0 0-22 {}} {256 0 0-319 {}} {259 0 0-330 {}}} SUCCS {{262 0 0-22 {}} {262 0 0-319 {}} {260 0 0-331 {}}} CYCLES {}}
+set a(0-21) {CHI {0-22 0-23 0-24 0-25 0-26 0-27 0-28 0-29 0-30 0-31 0-32 0-33 0-34 0-35 0-36 0-37 0-38 0-39 0-40 0-41 0-42 0-43 0-44 0-45 0-46 0-47 0-48 0-49 0-50 0-51 0-52 0-53 0-54 0-55 0-56 0-57 0-58 0-59 0-60 0-61 0-62 0-63 0-64 0-65 0-66 0-67 0-68 0-69 0-70 0-71 0-72 0-73 0-74 0-75 0-76 0-77 0-78 0-79 0-80 0-81 0-82 0-83 0-84 0-85 0-86 0-87 0-88 0-89 0-90 0-91 0-92 0-93 0-94 0-95 0-96 0-97 0-98 0-99 0-100 0-101 0-102 0-103 0-104 0-105 0-106 0-107 0-108 0-109 0-110 0-111 0-112 0-113 0-114 0-115 0-116 0-117 0-118 0-119 0-120 0-121 0-122 0-123 0-124 0-125 0-126 0-127 0-128 0-129 0-130 0-131 0-132 0-133 0-134 0-135 0-136 0-137 0-138 0-139 0-140 0-141 0-142 0-143 0-144 0-145 0-146 0-147 0-148 0-149 0-150 0-151 0-152 0-153 0-154 0-155 0-156 0-157 0-158 0-159 0-160 0-161 0-162 0-163 0-164 0-165 0-166 0-167 0-168 0-169 0-170 0-171 0-172 0-173 0-174 0-175 0-176 0-177 0-178 0-179 0-180 0-181 0-182 0-183 0-184 0-185 0-186 0-187 0-188 0-189 0-190 0-191 0-192 0-193 0-194 0-195 0-196 0-197 0-198 0-199 0-200 0-201 0-202 0-203 0-204 0-205 0-206 0-207 0-208 0-209 0-210 0-211 0-212 0-213 0-214 0-215 0-216 0-217 0-218 0-219 0-220 0-221 0-222 0-223 0-224 0-225 0-226 0-227 0-228 0-229 0-230 0-231 0-232 0-233 0-234 0-235 0-236 0-237 0-238 0-239 0-240 0-241 0-242 0-243 0-244 0-245 0-246 0-247 0-248 0-249 0-250 0-251 0-252 0-253 0-254 0-255 0-256 0-257 0-258 0-259 0-260 0-261 0-262 0-263 0-264 0-265 0-266 0-267 0-268 0-269 0-270 0-271 0-272 0-273 0-274 0-275 0-276 0-277 0-278 0-279 0-280 0-281 0-282 0-283 0-284 0-285 0-286 0-287 0-288 0-289 0-290 0-291 0-292 0-293 0-294 0-295 0-296 0-297 0-298 0-299 0-300 0-301 0-302 0-303 0-304 0-305 0-306 0-307 0-308 0-309 0-310 0-311 0-312 0-313 0-314 0-315 0-316 0-317 0-318 0-319 0-320 0-321 0-322 0-323 0-324 0-325 0-326 0-327 0-328 0-329 0-330 0-331} ITERATIONS Infinite LATENCY 307200 RESET_LATENCY 0 CSTEPS 2 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 307200 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 2.0 CYCLES_IN 307201 TOTAL_CYCLES_IN 307201 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 307201 NAME main TYPE LOOP DELAY {6144040.00 ns} PAR 0-16 XREFS 1086 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{258 0 0-17 {}} {258 0 0-18 {}} {258 0 0-19 {}} {259 0 0-20 {}}} SUCCS {{772 0 0-17 {}} {772 0 0-18 {}} {772 0 0-19 {}} {772 0 0-20 {}}} CYCLES {}}
+set a(0-16) {CHI {0-17 0-18 0-19 0-20 0-21} ITERATIONS Infinite LATENCY 307200 RESET_LATENCY 0 CSTEPS 0 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 307200 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 0 TOTAL_CYCLES_IN 0 TOTAL_CYCLES_UNDER 307201 TOTAL_CYCLES 307201 NAME core:rlp TYPE LOOP DELAY {6144040.00 ns} PAR {} XREFS 1087 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-16-TOTALCYCLES) {307201}
+set a(0-16-QMOD) {mgc_ioport.mgc_in_wire(1,90) 0-25 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12) {0-32 0-41 0-63 0-72 0-94 0-103} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) {0-44 0-54 0-56 0-75 0-85 0-87 0-106 0-116 0-118} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4) {0-122 0-135 0-141 0-154 0-191 0-205 0-218 0-255} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5) {0-128 0-147 0-194 0-211 0-258} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3) {0-133 0-152 0-216} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7) {0-136 0-155 0-185 0-197 0-219 0-249 0-261 0-290 0-302} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6) {0-137 0-156 0-220} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,11,0,13) {0-169 0-233} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11) {0-172 0-236 0-268} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9) {0-174 0-238 0-270} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8) {0-198 0-262} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10) {0-199 0-263 0-306} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12) {0-200 0-264} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,0,12,1,13) {0-201 0-265} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,10) {0-271 0-307} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,1,4,1,6) 0-295 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,1,6,0,8) 0-305 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2) 0-310 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2) 0-315 mgc_ioport.mgc_out_stdreg(2,30) 0-318 mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2) 0-322 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19) 0-323 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,7,0,8) 0-328}
+set a(0-16-PROC_NAME) {core}
+set a(0-16-HIER_NAME) {/sobel/core}
+set a(TOP) {0-16}
+
diff --git a/Sobel/sobel.v1/schematic.nlv b/Sobel/sobel.v1/schematic.nlv
new file mode 100644
index 0000000..1c21c95
--- /dev/null
+++ b/Sobel/sobel.v1/schematic.nlv
@@ -0,0 +1,5589 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "sobel:core" "orig"
+load port {clk} input -attr xrf 1616 -attr oid 1 -attr vt d -attr @path {/sobel/sobel:core/clk}
+load port {en} input -attr xrf 1617 -attr oid 2 -attr vt d -attr @path {/sobel/sobel:core/en}
+load port {arst_n} input -attr xrf 1618 -attr oid 3 -attr vt d -attr @path {/sobel/sobel:core/arst_n}
+load portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} -attr xrf 1619 -attr oid 4 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} -attr xrf 1620 -attr oid 5 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load symbol "reg(10,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(9:0)} input 10 {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(9:0)} input 10 {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(90,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(89:0)} input 90 {D(89)} {D(88)} {D(87)} {D(86)} {D(85)} {D(84)} {D(83)} {D(82)} {D(81)} {D(80)} {D(79)} {D(78)} {D(77)} {D(76)} {D(75)} {D(74)} {D(73)} {D(72)} {D(71)} {D(70)} {D(69)} {D(68)} {D(67)} {D(66)} {D(65)} {D(64)} {D(63)} {D(62)} {D(61)} {D(60)} {D(59)} {D(58)} {D(57)} {D(56)} {D(55)} {D(54)} {D(53)} {D(52)} {D(51)} {D(50)} {D(49)} {D(48)} {D(47)} {D(46)} {D(45)} {D(44)} {D(43)} {D(42)} {D(41)} {D(40)} {D(39)} {D(38)} {D(37)} {D(36)} {D(35)} {D(34)} {D(33)} {D(32)} {D(31)} {D(30)} {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(89:0)} input 90 {DRa(89)} {DRa(88)} {DRa(87)} {DRa(86)} {DRa(85)} {DRa(84)} {DRa(83)} {DRa(82)} {DRa(81)} {DRa(80)} {DRa(79)} {DRa(78)} {DRa(77)} {DRa(76)} {DRa(75)} {DRa(74)} {DRa(73)} {DRa(72)} {DRa(71)} {DRa(70)} {DRa(69)} {DRa(68)} {DRa(67)} {DRa(66)} {DRa(65)} {DRa(64)} {DRa(63)} {DRa(62)} {DRa(61)} {DRa(60)} {DRa(59)} {DRa(58)} {DRa(57)} {DRa(56)} {DRa(55)} {DRa(54)} {DRa(53)} {DRa(52)} {DRa(51)} {DRa(50)} {DRa(49)} {DRa(48)} {DRa(47)} {DRa(46)} {DRa(45)} {DRa(44)} {DRa(43)} {DRa(42)} {DRa(41)} {DRa(40)} {DRa(39)} {DRa(38)} {DRa(37)} {DRa(36)} {DRa(35)} {DRa(34)} {DRa(33)} {DRa(32)} {DRa(31)} {DRa(30)} {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,11,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(10)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,1,12,1,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,10,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(3)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(5,-1,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,1,4,1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,1,5,0,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,-1,11,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,6,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,0,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,10)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,-1,9,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,-1,10,-1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,10)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(4,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(3:0)} input 4 {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(3:0)} input 4 {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,5)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(4:0)} input 5 {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(4:0)} input 5 {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(5,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(4:0)} input 5 {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(4:0)} input 5 {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "reg(1,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(0:0)} input 1 {D(0)} \
+     portBus {DRa(0:0)} input 1 {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "reg(9,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(8:0)} input 9 {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(8:0)} input 9 {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load net {regs.regs(1).sva(0)} -attr vt d
+load net {regs.regs(1).sva(1)} -attr vt d
+load net {regs.regs(1).sva(2)} -attr vt d
+load net {regs.regs(1).sva(3)} -attr vt d
+load net {regs.regs(1).sva(4)} -attr vt d
+load net {regs.regs(1).sva(5)} -attr vt d
+load net {regs.regs(1).sva(6)} -attr vt d
+load net {regs.regs(1).sva(7)} -attr vt d
+load net {regs.regs(1).sva(8)} -attr vt d
+load net {regs.regs(1).sva(9)} -attr vt d
+load net {regs.regs(1).sva(10)} -attr vt d
+load net {regs.regs(1).sva(11)} -attr vt d
+load net {regs.regs(1).sva(12)} -attr vt d
+load net {regs.regs(1).sva(13)} -attr vt d
+load net {regs.regs(1).sva(14)} -attr vt d
+load net {regs.regs(1).sva(15)} -attr vt d
+load net {regs.regs(1).sva(16)} -attr vt d
+load net {regs.regs(1).sva(17)} -attr vt d
+load net {regs.regs(1).sva(18)} -attr vt d
+load net {regs.regs(1).sva(19)} -attr vt d
+load net {regs.regs(1).sva(20)} -attr vt d
+load net {regs.regs(1).sva(21)} -attr vt d
+load net {regs.regs(1).sva(22)} -attr vt d
+load net {regs.regs(1).sva(23)} -attr vt d
+load net {regs.regs(1).sva(24)} -attr vt d
+load net {regs.regs(1).sva(25)} -attr vt d
+load net {regs.regs(1).sva(26)} -attr vt d
+load net {regs.regs(1).sva(27)} -attr vt d
+load net {regs.regs(1).sva(28)} -attr vt d
+load net {regs.regs(1).sva(29)} -attr vt d
+load net {regs.regs(1).sva(30)} -attr vt d
+load net {regs.regs(1).sva(31)} -attr vt d
+load net {regs.regs(1).sva(32)} -attr vt d
+load net {regs.regs(1).sva(33)} -attr vt d
+load net {regs.regs(1).sva(34)} -attr vt d
+load net {regs.regs(1).sva(35)} -attr vt d
+load net {regs.regs(1).sva(36)} -attr vt d
+load net {regs.regs(1).sva(37)} -attr vt d
+load net {regs.regs(1).sva(38)} -attr vt d
+load net {regs.regs(1).sva(39)} -attr vt d
+load net {regs.regs(1).sva(40)} -attr vt d
+load net {regs.regs(1).sva(41)} -attr vt d
+load net {regs.regs(1).sva(42)} -attr vt d
+load net {regs.regs(1).sva(43)} -attr vt d
+load net {regs.regs(1).sva(44)} -attr vt d
+load net {regs.regs(1).sva(45)} -attr vt d
+load net {regs.regs(1).sva(46)} -attr vt d
+load net {regs.regs(1).sva(47)} -attr vt d
+load net {regs.regs(1).sva(48)} -attr vt d
+load net {regs.regs(1).sva(49)} -attr vt d
+load net {regs.regs(1).sva(50)} -attr vt d
+load net {regs.regs(1).sva(51)} -attr vt d
+load net {regs.regs(1).sva(52)} -attr vt d
+load net {regs.regs(1).sva(53)} -attr vt d
+load net {regs.regs(1).sva(54)} -attr vt d
+load net {regs.regs(1).sva(55)} -attr vt d
+load net {regs.regs(1).sva(56)} -attr vt d
+load net {regs.regs(1).sva(57)} -attr vt d
+load net {regs.regs(1).sva(58)} -attr vt d
+load net {regs.regs(1).sva(59)} -attr vt d
+load net {regs.regs(1).sva(60)} -attr vt d
+load net {regs.regs(1).sva(61)} -attr vt d
+load net {regs.regs(1).sva(62)} -attr vt d
+load net {regs.regs(1).sva(63)} -attr vt d
+load net {regs.regs(1).sva(64)} -attr vt d
+load net {regs.regs(1).sva(65)} -attr vt d
+load net {regs.regs(1).sva(66)} -attr vt d
+load net {regs.regs(1).sva(67)} -attr vt d
+load net {regs.regs(1).sva(68)} -attr vt d
+load net {regs.regs(1).sva(69)} -attr vt d
+load net {regs.regs(1).sva(70)} -attr vt d
+load net {regs.regs(1).sva(71)} -attr vt d
+load net {regs.regs(1).sva(72)} -attr vt d
+load net {regs.regs(1).sva(73)} -attr vt d
+load net {regs.regs(1).sva(74)} -attr vt d
+load net {regs.regs(1).sva(75)} -attr vt d
+load net {regs.regs(1).sva(76)} -attr vt d
+load net {regs.regs(1).sva(77)} -attr vt d
+load net {regs.regs(1).sva(78)} -attr vt d
+load net {regs.regs(1).sva(79)} -attr vt d
+load net {regs.regs(1).sva(80)} -attr vt d
+load net {regs.regs(1).sva(81)} -attr vt d
+load net {regs.regs(1).sva(82)} -attr vt d
+load net {regs.regs(1).sva(83)} -attr vt d
+load net {regs.regs(1).sva(84)} -attr vt d
+load net {regs.regs(1).sva(85)} -attr vt d
+load net {regs.regs(1).sva(86)} -attr vt d
+load net {regs.regs(1).sva(87)} -attr vt d
+load net {regs.regs(1).sva(88)} -attr vt d
+load net {regs.regs(1).sva(89)} -attr vt d
+load netBundle {regs.regs(1).sva} 90 {regs.regs(1).sva(0)} {regs.regs(1).sva(1)} {regs.regs(1).sva(2)} {regs.regs(1).sva(3)} {regs.regs(1).sva(4)} {regs.regs(1).sva(5)} {regs.regs(1).sva(6)} {regs.regs(1).sva(7)} {regs.regs(1).sva(8)} {regs.regs(1).sva(9)} {regs.regs(1).sva(10)} {regs.regs(1).sva(11)} {regs.regs(1).sva(12)} {regs.regs(1).sva(13)} {regs.regs(1).sva(14)} {regs.regs(1).sva(15)} {regs.regs(1).sva(16)} {regs.regs(1).sva(17)} {regs.regs(1).sva(18)} {regs.regs(1).sva(19)} {regs.regs(1).sva(20)} {regs.regs(1).sva(21)} {regs.regs(1).sva(22)} {regs.regs(1).sva(23)} {regs.regs(1).sva(24)} {regs.regs(1).sva(25)} {regs.regs(1).sva(26)} {regs.regs(1).sva(27)} {regs.regs(1).sva(28)} {regs.regs(1).sva(29)} {regs.regs(1).sva(30)} {regs.regs(1).sva(31)} {regs.regs(1).sva(32)} {regs.regs(1).sva(33)} {regs.regs(1).sva(34)} {regs.regs(1).sva(35)} {regs.regs(1).sva(36)} {regs.regs(1).sva(37)} {regs.regs(1).sva(38)} {regs.regs(1).sva(39)} {regs.regs(1).sva(40)} {regs.regs(1).sva(41)} {regs.regs(1).sva(42)} {regs.regs(1).sva(43)} {regs.regs(1).sva(44)} {regs.regs(1).sva(45)} {regs.regs(1).sva(46)} {regs.regs(1).sva(47)} {regs.regs(1).sva(48)} {regs.regs(1).sva(49)} {regs.regs(1).sva(50)} {regs.regs(1).sva(51)} {regs.regs(1).sva(52)} {regs.regs(1).sva(53)} {regs.regs(1).sva(54)} {regs.regs(1).sva(55)} {regs.regs(1).sva(56)} {regs.regs(1).sva(57)} {regs.regs(1).sva(58)} {regs.regs(1).sva(59)} {regs.regs(1).sva(60)} {regs.regs(1).sva(61)} {regs.regs(1).sva(62)} {regs.regs(1).sva(63)} {regs.regs(1).sva(64)} {regs.regs(1).sva(65)} {regs.regs(1).sva(66)} {regs.regs(1).sva(67)} {regs.regs(1).sva(68)} {regs.regs(1).sva(69)} {regs.regs(1).sva(70)} {regs.regs(1).sva(71)} {regs.regs(1).sva(72)} {regs.regs(1).sva(73)} {regs.regs(1).sva(74)} {regs.regs(1).sva(75)} {regs.regs(1).sva(76)} {regs.regs(1).sva(77)} {regs.regs(1).sva(78)} {regs.regs(1).sva(79)} {regs.regs(1).sva(80)} {regs.regs(1).sva(81)} {regs.regs(1).sva(82)} {regs.regs(1).sva(83)} {regs.regs(1).sva(84)} {regs.regs(1).sva(85)} {regs.regs(1).sva(86)} {regs.regs(1).sva(87)} {regs.regs(1).sva(88)} {regs.regs(1).sva(89)} -attr xrf 1621 -attr oid 6 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {ACC1:slc(regs.regs(2)).itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2)).itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2)).itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2)).itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2)).itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2)).itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2)).itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2)).itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2)).itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2)).itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2)).itm} 10 {ACC1:slc(regs.regs(2)).itm(0)} {ACC1:slc(regs.regs(2)).itm(1)} {ACC1:slc(regs.regs(2)).itm(2)} {ACC1:slc(regs.regs(2)).itm(3)} {ACC1:slc(regs.regs(2)).itm(4)} {ACC1:slc(regs.regs(2)).itm(5)} {ACC1:slc(regs.regs(2)).itm(6)} {ACC1:slc(regs.regs(2)).itm(7)} {ACC1:slc(regs.regs(2)).itm(8)} {ACC1:slc(regs.regs(2)).itm(9)} -attr xrf 1622 -attr oid 7 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)).itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#9.itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#9.itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#9.itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#9.itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#9.itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#9.itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#9.itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#9.itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#9.itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2))#9.itm} 10 {ACC1:slc(regs.regs(2))#9.itm(0)} {ACC1:slc(regs.regs(2))#9.itm(1)} {ACC1:slc(regs.regs(2))#9.itm(2)} {ACC1:slc(regs.regs(2))#9.itm(3)} {ACC1:slc(regs.regs(2))#9.itm(4)} {ACC1:slc(regs.regs(2))#9.itm(5)} {ACC1:slc(regs.regs(2))#9.itm(6)} {ACC1:slc(regs.regs(2))#9.itm(7)} {ACC1:slc(regs.regs(2))#9.itm(8)} {ACC1:slc(regs.regs(2))#9.itm(9)} -attr xrf 1623 -attr oid 8 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#9.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#10.itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#10.itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#10.itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#10.itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#10.itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#10.itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#10.itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#10.itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#10.itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2))#10.itm} 10 {ACC1:slc(regs.regs(2))#10.itm(0)} {ACC1:slc(regs.regs(2))#10.itm(1)} {ACC1:slc(regs.regs(2))#10.itm(2)} {ACC1:slc(regs.regs(2))#10.itm(3)} {ACC1:slc(regs.regs(2))#10.itm(4)} {ACC1:slc(regs.regs(2))#10.itm(5)} {ACC1:slc(regs.regs(2))#10.itm(6)} {ACC1:slc(regs.regs(2))#10.itm(7)} {ACC1:slc(regs.regs(2))#10.itm(8)} {ACC1:slc(regs.regs(2))#10.itm(9)} -attr xrf 1624 -attr oid 9 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#11.itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#11.itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#11.itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#11.itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#11.itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#11.itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#11.itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#11.itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#11.itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2))#11.itm} 10 {ACC1:slc(regs.regs(2))#11.itm(0)} {ACC1:slc(regs.regs(2))#11.itm(1)} {ACC1:slc(regs.regs(2))#11.itm(2)} {ACC1:slc(regs.regs(2))#11.itm(3)} {ACC1:slc(regs.regs(2))#11.itm(4)} {ACC1:slc(regs.regs(2))#11.itm(5)} {ACC1:slc(regs.regs(2))#11.itm(6)} {ACC1:slc(regs.regs(2))#11.itm(7)} {ACC1:slc(regs.regs(2))#11.itm(8)} {ACC1:slc(regs.regs(2))#11.itm(9)} -attr xrf 1625 -attr oid 10 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#11.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#12.itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#12.itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#12.itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#12.itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#12.itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#12.itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#12.itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#12.itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#12.itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2))#12.itm} 10 {ACC1:slc(regs.regs(2))#12.itm(0)} {ACC1:slc(regs.regs(2))#12.itm(1)} {ACC1:slc(regs.regs(2))#12.itm(2)} {ACC1:slc(regs.regs(2))#12.itm(3)} {ACC1:slc(regs.regs(2))#12.itm(4)} {ACC1:slc(regs.regs(2))#12.itm(5)} {ACC1:slc(regs.regs(2))#12.itm(6)} {ACC1:slc(regs.regs(2))#12.itm(7)} {ACC1:slc(regs.regs(2))#12.itm(8)} {ACC1:slc(regs.regs(2))#12.itm(9)} -attr xrf 1626 -attr oid 11 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#12.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#13.itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#13.itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#13.itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#13.itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#13.itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#13.itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#13.itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#13.itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#13.itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2))#13.itm} 10 {ACC1:slc(regs.regs(2))#13.itm(0)} {ACC1:slc(regs.regs(2))#13.itm(1)} {ACC1:slc(regs.regs(2))#13.itm(2)} {ACC1:slc(regs.regs(2))#13.itm(3)} {ACC1:slc(regs.regs(2))#13.itm(4)} {ACC1:slc(regs.regs(2))#13.itm(5)} {ACC1:slc(regs.regs(2))#13.itm(6)} {ACC1:slc(regs.regs(2))#13.itm(7)} {ACC1:slc(regs.regs(2))#13.itm(8)} {ACC1:slc(regs.regs(2))#13.itm(9)} -attr xrf 1627 -attr oid 12 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#14.itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#14.itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#14.itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#14.itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#14.itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#14.itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#14.itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#14.itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#14.itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2))#14.itm} 10 {ACC1:slc(regs.regs(2))#14.itm(0)} {ACC1:slc(regs.regs(2))#14.itm(1)} {ACC1:slc(regs.regs(2))#14.itm(2)} {ACC1:slc(regs.regs(2))#14.itm(3)} {ACC1:slc(regs.regs(2))#14.itm(4)} {ACC1:slc(regs.regs(2))#14.itm(5)} {ACC1:slc(regs.regs(2))#14.itm(6)} {ACC1:slc(regs.regs(2))#14.itm(7)} {ACC1:slc(regs.regs(2))#14.itm(8)} {ACC1:slc(regs.regs(2))#14.itm(9)} -attr xrf 1628 -attr oid 13 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#14.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#15.itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#15.itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#15.itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#15.itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#15.itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#15.itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#15.itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#15.itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#15.itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2))#15.itm} 10 {ACC1:slc(regs.regs(2))#15.itm(0)} {ACC1:slc(regs.regs(2))#15.itm(1)} {ACC1:slc(regs.regs(2))#15.itm(2)} {ACC1:slc(regs.regs(2))#15.itm(3)} {ACC1:slc(regs.regs(2))#15.itm(4)} {ACC1:slc(regs.regs(2))#15.itm(5)} {ACC1:slc(regs.regs(2))#15.itm(6)} {ACC1:slc(regs.regs(2))#15.itm(7)} {ACC1:slc(regs.regs(2))#15.itm(8)} {ACC1:slc(regs.regs(2))#15.itm(9)} -attr xrf 1629 -attr oid 14 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#15.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#16.itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#16.itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#16.itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#16.itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#16.itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#16.itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#16.itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#16.itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2))#16.itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2))#16.itm} 10 {ACC1:slc(regs.regs(2))#16.itm(0)} {ACC1:slc(regs.regs(2))#16.itm(1)} {ACC1:slc(regs.regs(2))#16.itm(2)} {ACC1:slc(regs.regs(2))#16.itm(3)} {ACC1:slc(regs.regs(2))#16.itm(4)} {ACC1:slc(regs.regs(2))#16.itm(5)} {ACC1:slc(regs.regs(2))#16.itm(6)} {ACC1:slc(regs.regs(2))#16.itm(7)} {ACC1:slc(regs.regs(2))#16.itm(8)} {ACC1:slc(regs.regs(2))#16.itm(9)} -attr xrf 1630 -attr oid 15 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(0)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(1)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(2)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(3)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(4)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(5)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(6)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(7)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(8)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(9)} -attr vt d
+load netBundle {reg(vout:rsc:mgc_out_stdreg.d).tmp} 10 {reg(vout:rsc:mgc_out_stdreg.d).tmp(0)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(1)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(2)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(3)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(4)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(5)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(6)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(7)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(8)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(9)} -attr xrf 1631 -attr oid 16 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(0)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(1)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(2)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(3)} -attr vt d
+load netBundle {reg(vout:rsc:mgc_out_stdreg.d).tmp#1} 4 {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(0)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(1)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(2)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(3)} -attr xrf 1632 -attr oid 17 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#1}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(0)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(1)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(2)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(3)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(4)} -attr vt d
+load netBundle {reg(vout:rsc:mgc_out_stdreg.d).tmp#2} 5 {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(0)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(1)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(2)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(3)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(4)} -attr xrf 1633 -attr oid 18 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#2}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(0)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(1)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(2)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(3)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(4)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(5)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(6)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(7)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(8)} -attr vt d
+load netBundle {reg(vout:rsc:mgc_out_stdreg.d).tmp#4} 9 {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(0)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(1)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(2)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(3)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(4)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(5)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(6)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(7)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(8)} -attr xrf 1634 -attr oid 19 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#4}
+load net {ACC1:acc.psp.sva(0)} -attr vt d
+load net {ACC1:acc.psp.sva(1)} -attr vt d
+load net {ACC1:acc.psp.sva(2)} -attr vt d
+load net {ACC1:acc.psp.sva(3)} -attr vt d
+load net {ACC1:acc.psp.sva(4)} -attr vt d
+load net {ACC1:acc.psp.sva(5)} -attr vt d
+load net {ACC1:acc.psp.sva(6)} -attr vt d
+load net {ACC1:acc.psp.sva(7)} -attr vt d
+load net {ACC1:acc.psp.sva(8)} -attr vt d
+load net {ACC1:acc.psp.sva(9)} -attr vt d
+load net {ACC1:acc.psp.sva(10)} -attr vt d
+load net {ACC1:acc.psp.sva(11)} -attr vt d
+load net {ACC1:acc.psp.sva(12)} -attr vt d
+load netBundle {ACC1:acc.psp.sva} 13 {ACC1:acc.psp.sva(0)} {ACC1:acc.psp.sva(1)} {ACC1:acc.psp.sva(2)} {ACC1:acc.psp.sva(3)} {ACC1:acc.psp.sva(4)} {ACC1:acc.psp.sva(5)} {ACC1:acc.psp.sva(6)} {ACC1:acc.psp.sva(7)} {ACC1:acc.psp.sva(8)} {ACC1:acc.psp.sva(9)} {ACC1:acc.psp.sva(10)} {ACC1:acc.psp.sva(11)} {ACC1:acc.psp.sva(12)} -attr xrf 1635 -attr oid 20 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load net {FRAME:acc#41.sdt(0)} -attr vt d
+load net {FRAME:acc#41.sdt(1)} -attr vt d
+load net {FRAME:acc#41.sdt(2)} -attr vt d
+load net {FRAME:acc#41.sdt(3)} -attr vt d
+load net {FRAME:acc#41.sdt(4)} -attr vt d
+load net {FRAME:acc#41.sdt(5)} -attr vt d
+load net {FRAME:acc#41.sdt(6)} -attr vt d
+load netBundle {FRAME:acc#41.sdt} 7 {FRAME:acc#41.sdt(0)} {FRAME:acc#41.sdt(1)} {FRAME:acc#41.sdt(2)} {FRAME:acc#41.sdt(3)} {FRAME:acc#41.sdt(4)} {FRAME:acc#41.sdt(5)} {FRAME:acc#41.sdt(6)} -attr xrf 1636 -attr oid 21 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.sdt}
+load net {FRAME:acc.psp(0)} -attr vt d
+load net {FRAME:acc.psp(1)} -attr vt d
+load net {FRAME:acc.psp(2)} -attr vt d
+load net {FRAME:acc.psp(3)} -attr vt d
+load net {FRAME:acc.psp(4)} -attr vt d
+load net {FRAME:acc.psp(5)} -attr vt d
+load net {FRAME:acc.psp(6)} -attr vt d
+load net {FRAME:acc.psp(7)} -attr vt d
+load net {FRAME:acc.psp(8)} -attr vt d
+load net {FRAME:acc.psp(9)} -attr vt d
+load net {FRAME:acc.psp(10)} -attr vt d
+load net {FRAME:acc.psp(11)} -attr vt d
+load netBundle {FRAME:acc.psp} 12 {FRAME:acc.psp(0)} {FRAME:acc.psp(1)} {FRAME:acc.psp(2)} {FRAME:acc.psp(3)} {FRAME:acc.psp(4)} {FRAME:acc.psp(5)} {FRAME:acc.psp(6)} {FRAME:acc.psp(7)} {FRAME:acc.psp(8)} {FRAME:acc.psp(9)} {FRAME:acc.psp(10)} {FRAME:acc.psp(11)} -attr xrf 1637 -attr oid 22 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.psp}
+load net {FRAME:acc#24.sdt(0)} -attr vt d
+load net {FRAME:acc#24.sdt(1)} -attr vt d
+load net {FRAME:acc#24.sdt(2)} -attr vt d
+load net {FRAME:acc#24.sdt(3)} -attr vt d
+load net {FRAME:acc#24.sdt(4)} -attr vt d
+load net {FRAME:acc#24.sdt(5)} -attr vt d
+load net {FRAME:acc#24.sdt(6)} -attr vt d
+load net {FRAME:acc#24.sdt(7)} -attr vt d
+load net {FRAME:acc#24.sdt(8)} -attr vt d
+load net {FRAME:acc#24.sdt(9)} -attr vt d
+load net {FRAME:acc#24.sdt(10)} -attr vt d
+load net {FRAME:acc#24.sdt(11)} -attr vt d
+load netBundle {FRAME:acc#24.sdt} 12 {FRAME:acc#24.sdt(0)} {FRAME:acc#24.sdt(1)} {FRAME:acc#24.sdt(2)} {FRAME:acc#24.sdt(3)} {FRAME:acc#24.sdt(4)} {FRAME:acc#24.sdt(5)} {FRAME:acc#24.sdt(6)} {FRAME:acc#24.sdt(7)} {FRAME:acc#24.sdt(8)} {FRAME:acc#24.sdt(9)} {FRAME:acc#24.sdt(10)} {FRAME:acc#24.sdt(11)} -attr xrf 1638 -attr oid 23 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.sdt}
+load net {FRAME:acc#61.psp(0)} -attr vt d
+load net {FRAME:acc#61.psp(1)} -attr vt d
+load net {FRAME:acc#61.psp(2)} -attr vt d
+load net {FRAME:acc#61.psp(3)} -attr vt d
+load net {FRAME:acc#61.psp(4)} -attr vt d
+load net {FRAME:acc#61.psp(5)} -attr vt d
+load net {FRAME:acc#61.psp(6)} -attr vt d
+load net {FRAME:acc#61.psp(7)} -attr vt d
+load net {FRAME:acc#61.psp(8)} -attr vt d
+load net {FRAME:acc#61.psp(9)} -attr vt d
+load net {FRAME:acc#61.psp(10)} -attr vt d
+load net {FRAME:acc#61.psp(11)} -attr vt d
+load netBundle {FRAME:acc#61.psp} 12 {FRAME:acc#61.psp(0)} {FRAME:acc#61.psp(1)} {FRAME:acc#61.psp(2)} {FRAME:acc#61.psp(3)} {FRAME:acc#61.psp(4)} {FRAME:acc#61.psp(5)} {FRAME:acc#61.psp(6)} {FRAME:acc#61.psp(7)} {FRAME:acc#61.psp(8)} {FRAME:acc#61.psp(9)} {FRAME:acc#61.psp(10)} {FRAME:acc#61.psp(11)} -attr xrf 1639 -attr oid 24 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61.psp}
+load net {FRAME:acc#37.sdt(0)} -attr vt d
+load net {FRAME:acc#37.sdt(1)} -attr vt d
+load net {FRAME:acc#37.sdt(2)} -attr vt d
+load net {FRAME:acc#37.sdt(3)} -attr vt d
+load net {FRAME:acc#37.sdt(4)} -attr vt d
+load net {FRAME:acc#37.sdt(5)} -attr vt d
+load net {FRAME:acc#37.sdt(6)} -attr vt d
+load net {FRAME:acc#37.sdt(7)} -attr vt d
+load net {FRAME:acc#37.sdt(8)} -attr vt d
+load net {FRAME:acc#37.sdt(9)} -attr vt d
+load net {FRAME:acc#37.sdt(10)} -attr vt d
+load net {FRAME:acc#37.sdt(11)} -attr vt d
+load netBundle {FRAME:acc#37.sdt} 12 {FRAME:acc#37.sdt(0)} {FRAME:acc#37.sdt(1)} {FRAME:acc#37.sdt(2)} {FRAME:acc#37.sdt(3)} {FRAME:acc#37.sdt(4)} {FRAME:acc#37.sdt(5)} {FRAME:acc#37.sdt(6)} {FRAME:acc#37.sdt(7)} {FRAME:acc#37.sdt(8)} {FRAME:acc#37.sdt(9)} {FRAME:acc#37.sdt(10)} {FRAME:acc#37.sdt(11)} -attr xrf 1640 -attr oid 25 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.sdt}
+load net {FRAME:acc#47.psp(0)} -attr vt d
+load net {FRAME:acc#47.psp(1)} -attr vt d
+load net {FRAME:acc#47.psp(2)} -attr vt d
+load net {FRAME:acc#47.psp(3)} -attr vt d
+load net {FRAME:acc#47.psp(4)} -attr vt d
+load netBundle {FRAME:acc#47.psp} 5 {FRAME:acc#47.psp(0)} {FRAME:acc#47.psp(1)} {FRAME:acc#47.psp(2)} {FRAME:acc#47.psp(3)} {FRAME:acc#47.psp(4)} -attr xrf 1641 -attr oid 26 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#47.psp}
+load net {FRAME:acc#13.sdt(0)} -attr vt d
+load net {FRAME:acc#13.sdt(1)} -attr vt d
+load net {FRAME:acc#13.sdt(2)} -attr vt d
+load net {FRAME:acc#13.sdt(3)} -attr vt d
+load net {FRAME:acc#13.sdt(4)} -attr vt d
+load net {FRAME:acc#13.sdt(5)} -attr vt d
+load netBundle {FRAME:acc#13.sdt} 6 {FRAME:acc#13.sdt(0)} {FRAME:acc#13.sdt(1)} {FRAME:acc#13.sdt(2)} {FRAME:acc#13.sdt(3)} {FRAME:acc#13.sdt(4)} {FRAME:acc#13.sdt(5)} -attr xrf 1642 -attr oid 27 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.sdt}
+load net {ACC1:acc#43.psp.sva(0)} -attr vt d
+load net {ACC1:acc#43.psp.sva(1)} -attr vt d
+load net {ACC1:acc#43.psp.sva(2)} -attr vt d
+load net {ACC1:acc#43.psp.sva(3)} -attr vt d
+load net {ACC1:acc#43.psp.sva(4)} -attr vt d
+load net {ACC1:acc#43.psp.sva(5)} -attr vt d
+load net {ACC1:acc#43.psp.sva(6)} -attr vt d
+load net {ACC1:acc#43.psp.sva(7)} -attr vt d
+load net {ACC1:acc#43.psp.sva(8)} -attr vt d
+load net {ACC1:acc#43.psp.sva(9)} -attr vt d
+load net {ACC1:acc#43.psp.sva(10)} -attr vt d
+load net {ACC1:acc#43.psp.sva(11)} -attr vt d
+load net {ACC1:acc#43.psp.sva(12)} -attr vt d
+load netBundle {ACC1:acc#43.psp.sva} 13 {ACC1:acc#43.psp.sva(0)} {ACC1:acc#43.psp.sva(1)} {ACC1:acc#43.psp.sva(2)} {ACC1:acc#43.psp.sva(3)} {ACC1:acc#43.psp.sva(4)} {ACC1:acc#43.psp.sva(5)} {ACC1:acc#43.psp.sva(6)} {ACC1:acc#43.psp.sva(7)} {ACC1:acc#43.psp.sva(8)} {ACC1:acc#43.psp.sva(9)} {ACC1:acc#43.psp.sva(10)} {ACC1:acc#43.psp.sva(11)} {ACC1:acc#43.psp.sva(12)} -attr xrf 1643 -attr oid 28 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load net {FRAME:acc#55.psp(0)} -attr vt d
+load net {FRAME:acc#55.psp(1)} -attr vt d
+load net {FRAME:acc#55.psp(2)} -attr vt d
+load net {FRAME:acc#55.psp(3)} -attr vt d
+load net {FRAME:acc#55.psp(4)} -attr vt d
+load netBundle {FRAME:acc#55.psp} 5 {FRAME:acc#55.psp(0)} {FRAME:acc#55.psp(1)} {FRAME:acc#55.psp(2)} {FRAME:acc#55.psp(3)} {FRAME:acc#55.psp(4)} -attr xrf 1644 -attr oid 29 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#55.psp}
+load net {FRAME:acc#31.sdt(0)} -attr vt d
+load net {FRAME:acc#31.sdt(1)} -attr vt d
+load net {FRAME:acc#31.sdt(2)} -attr vt d
+load net {FRAME:acc#31.sdt(3)} -attr vt d
+load net {FRAME:acc#31.sdt(4)} -attr vt d
+load net {FRAME:acc#31.sdt(5)} -attr vt d
+load netBundle {FRAME:acc#31.sdt} 6 {FRAME:acc#31.sdt(0)} {FRAME:acc#31.sdt(1)} {FRAME:acc#31.sdt(2)} {FRAME:acc#31.sdt(3)} {FRAME:acc#31.sdt(4)} {FRAME:acc#31.sdt(5)} -attr xrf 1645 -attr oid 30 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#31.sdt}
+load net {ACC1:acc#42.psp.sva(0)} -attr vt d
+load net {ACC1:acc#42.psp.sva(1)} -attr vt d
+load net {ACC1:acc#42.psp.sva(2)} -attr vt d
+load net {ACC1:acc#42.psp.sva(3)} -attr vt d
+load net {ACC1:acc#42.psp.sva(4)} -attr vt d
+load net {ACC1:acc#42.psp.sva(5)} -attr vt d
+load net {ACC1:acc#42.psp.sva(6)} -attr vt d
+load net {ACC1:acc#42.psp.sva(7)} -attr vt d
+load net {ACC1:acc#42.psp.sva(8)} -attr vt d
+load net {ACC1:acc#42.psp.sva(9)} -attr vt d
+load net {ACC1:acc#42.psp.sva(10)} -attr vt d
+load net {ACC1:acc#42.psp.sva(11)} -attr vt d
+load net {ACC1:acc#42.psp.sva(12)} -attr vt d
+load netBundle {ACC1:acc#42.psp.sva} 13 {ACC1:acc#42.psp.sva(0)} {ACC1:acc#42.psp.sva(1)} {ACC1:acc#42.psp.sva(2)} {ACC1:acc#42.psp.sva(3)} {ACC1:acc#42.psp.sva(4)} {ACC1:acc#42.psp.sva(5)} {ACC1:acc#42.psp.sva(6)} {ACC1:acc#42.psp.sva(7)} {ACC1:acc#42.psp.sva(8)} {ACC1:acc#42.psp.sva(9)} {ACC1:acc#42.psp.sva(10)} {ACC1:acc#42.psp.sva(11)} {ACC1:acc#42.psp.sva(12)} -attr xrf 1646 -attr oid 31 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load net {FRAME:acc#49.psp(0)} -attr vt d
+load net {FRAME:acc#49.psp(1)} -attr vt d
+load net {FRAME:acc#49.psp(2)} -attr vt d
+load net {FRAME:acc#49.psp(3)} -attr vt d
+load net {FRAME:acc#49.psp(4)} -attr vt d
+load netBundle {FRAME:acc#49.psp} 5 {FRAME:acc#49.psp(0)} {FRAME:acc#49.psp(1)} {FRAME:acc#49.psp(2)} {FRAME:acc#49.psp(3)} {FRAME:acc#49.psp(4)} -attr xrf 1647 -attr oid 32 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#49.psp}
+load net {FRAME:acc#18.sdt(0)} -attr vt d
+load net {FRAME:acc#18.sdt(1)} -attr vt d
+load net {FRAME:acc#18.sdt(2)} -attr vt d
+load net {FRAME:acc#18.sdt(3)} -attr vt d
+load net {FRAME:acc#18.sdt(4)} -attr vt d
+load net {FRAME:acc#18.sdt(5)} -attr vt d
+load netBundle {FRAME:acc#18.sdt} 6 {FRAME:acc#18.sdt(0)} {FRAME:acc#18.sdt(1)} {FRAME:acc#18.sdt(2)} {FRAME:acc#18.sdt(3)} {FRAME:acc#18.sdt(4)} {FRAME:acc#18.sdt(5)} -attr xrf 1648 -attr oid 33 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.sdt}
+load net {slc(regs.regs(1).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#2.itm} 10 {slc(regs.regs(1).sva)#2.itm(0)} {slc(regs.regs(1).sva)#2.itm(1)} {slc(regs.regs(1).sva)#2.itm(2)} {slc(regs.regs(1).sva)#2.itm(3)} {slc(regs.regs(1).sva)#2.itm(4)} {slc(regs.regs(1).sva)#2.itm(5)} {slc(regs.regs(1).sva)#2.itm(6)} {slc(regs.regs(1).sva)#2.itm(7)} {slc(regs.regs(1).sva)#2.itm(8)} {slc(regs.regs(1).sva)#2.itm(9)} -attr xrf 1649 -attr oid 34 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {slc(regs.regs(1).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#1.itm} 10 {slc(regs.regs(1).sva)#1.itm(0)} {slc(regs.regs(1).sva)#1.itm(1)} {slc(regs.regs(1).sva)#1.itm(2)} {slc(regs.regs(1).sva)#1.itm(3)} {slc(regs.regs(1).sva)#1.itm(4)} {slc(regs.regs(1).sva)#1.itm(5)} {slc(regs.regs(1).sva)#1.itm(6)} {slc(regs.regs(1).sva)#1.itm(7)} {slc(regs.regs(1).sva)#1.itm(8)} {slc(regs.regs(1).sva)#1.itm(9)} -attr xrf 1650 -attr oid 35 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {slc(regs.regs(1).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva).itm} 10 {slc(regs.regs(1).sva).itm(0)} {slc(regs.regs(1).sva).itm(1)} {slc(regs.regs(1).sva).itm(2)} {slc(regs.regs(1).sva).itm(3)} {slc(regs.regs(1).sva).itm(4)} {slc(regs.regs(1).sva).itm(5)} {slc(regs.regs(1).sva).itm(6)} {slc(regs.regs(1).sva).itm(7)} {slc(regs.regs(1).sva).itm(8)} {slc(regs.regs(1).sva).itm(9)} -attr xrf 1651 -attr oid 36 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {slc(regs.regs(1).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#5.itm} 10 {slc(regs.regs(1).sva)#5.itm(0)} {slc(regs.regs(1).sva)#5.itm(1)} {slc(regs.regs(1).sva)#5.itm(2)} {slc(regs.regs(1).sva)#5.itm(3)} {slc(regs.regs(1).sva)#5.itm(4)} {slc(regs.regs(1).sva)#5.itm(5)} {slc(regs.regs(1).sva)#5.itm(6)} {slc(regs.regs(1).sva)#5.itm(7)} {slc(regs.regs(1).sva)#5.itm(8)} {slc(regs.regs(1).sva)#5.itm(9)} -attr xrf 1652 -attr oid 37 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {slc(regs.regs(1).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#4.itm} 10 {slc(regs.regs(1).sva)#4.itm(0)} {slc(regs.regs(1).sva)#4.itm(1)} {slc(regs.regs(1).sva)#4.itm(2)} {slc(regs.regs(1).sva)#4.itm(3)} {slc(regs.regs(1).sva)#4.itm(4)} {slc(regs.regs(1).sva)#4.itm(5)} {slc(regs.regs(1).sva)#4.itm(6)} {slc(regs.regs(1).sva)#4.itm(7)} {slc(regs.regs(1).sva)#4.itm(8)} {slc(regs.regs(1).sva)#4.itm(9)} -attr xrf 1653 -attr oid 38 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {slc(regs.regs(1).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#3.itm} 10 {slc(regs.regs(1).sva)#3.itm(0)} {slc(regs.regs(1).sva)#3.itm(1)} {slc(regs.regs(1).sva)#3.itm(2)} {slc(regs.regs(1).sva)#3.itm(3)} {slc(regs.regs(1).sva)#3.itm(4)} {slc(regs.regs(1).sva)#3.itm(5)} {slc(regs.regs(1).sva)#3.itm(6)} {slc(regs.regs(1).sva)#3.itm(7)} {slc(regs.regs(1).sva)#3.itm(8)} {slc(regs.regs(1).sva)#3.itm(9)} -attr xrf 1654 -attr oid 39 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {slc(regs.regs(1).sva)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#8.itm} 10 {slc(regs.regs(1).sva)#8.itm(0)} {slc(regs.regs(1).sva)#8.itm(1)} {slc(regs.regs(1).sva)#8.itm(2)} {slc(regs.regs(1).sva)#8.itm(3)} {slc(regs.regs(1).sva)#8.itm(4)} {slc(regs.regs(1).sva)#8.itm(5)} {slc(regs.regs(1).sva)#8.itm(6)} {slc(regs.regs(1).sva)#8.itm(7)} {slc(regs.regs(1).sva)#8.itm(8)} {slc(regs.regs(1).sva)#8.itm(9)} -attr xrf 1655 -attr oid 40 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {slc(regs.regs(1).sva)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#7.itm} 10 {slc(regs.regs(1).sva)#7.itm(0)} {slc(regs.regs(1).sva)#7.itm(1)} {slc(regs.regs(1).sva)#7.itm(2)} {slc(regs.regs(1).sva)#7.itm(3)} {slc(regs.regs(1).sva)#7.itm(4)} {slc(regs.regs(1).sva)#7.itm(5)} {slc(regs.regs(1).sva)#7.itm(6)} {slc(regs.regs(1).sva)#7.itm(7)} {slc(regs.regs(1).sva)#7.itm(8)} {slc(regs.regs(1).sva)#7.itm(9)} -attr xrf 1656 -attr oid 41 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {slc(regs.regs(1).sva)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#6.itm} 10 {slc(regs.regs(1).sva)#6.itm(0)} {slc(regs.regs(1).sva)#6.itm(1)} {slc(regs.regs(1).sva)#6.itm(2)} {slc(regs.regs(1).sva)#6.itm(3)} {slc(regs.regs(1).sva)#6.itm(4)} {slc(regs.regs(1).sva)#6.itm(5)} {slc(regs.regs(1).sva)#6.itm(6)} {slc(regs.regs(1).sva)#6.itm(7)} {slc(regs.regs(1).sva)#6.itm(8)} {slc(regs.regs(1).sva)#6.itm(9)} -attr xrf 1657 -attr oid 42 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {ACC1:slc.itm(0)} -attr vt d
+load net {ACC1:slc.itm(1)} -attr vt d
+load net {ACC1:slc.itm(2)} -attr vt d
+load net {ACC1:slc.itm(3)} -attr vt d
+load net {ACC1:slc.itm(4)} -attr vt d
+load net {ACC1:slc.itm(5)} -attr vt d
+load net {ACC1:slc.itm(6)} -attr vt d
+load net {ACC1:slc.itm(7)} -attr vt d
+load net {ACC1:slc.itm(8)} -attr vt d
+load net {ACC1:slc.itm(9)} -attr vt d
+load net {ACC1:slc.itm(10)} -attr vt d
+load net {ACC1:slc.itm(11)} -attr vt d
+load netBundle {ACC1:slc.itm} 12 {ACC1:slc.itm(0)} {ACC1:slc.itm(1)} {ACC1:slc.itm(2)} {ACC1:slc.itm(3)} {ACC1:slc.itm(4)} {ACC1:slc.itm(5)} {ACC1:slc.itm(6)} {ACC1:slc.itm(7)} {ACC1:slc.itm(8)} {ACC1:slc.itm(9)} {ACC1:slc.itm(10)} {ACC1:slc.itm(11)} -attr xrf 1658 -attr oid 43 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#47.itm(0)} -attr vt d
+load net {ACC1:acc#47.itm(1)} -attr vt d
+load net {ACC1:acc#47.itm(2)} -attr vt d
+load net {ACC1:acc#47.itm(3)} -attr vt d
+load net {ACC1:acc#47.itm(4)} -attr vt d
+load net {ACC1:acc#47.itm(5)} -attr vt d
+load net {ACC1:acc#47.itm(6)} -attr vt d
+load net {ACC1:acc#47.itm(7)} -attr vt d
+load net {ACC1:acc#47.itm(8)} -attr vt d
+load net {ACC1:acc#47.itm(9)} -attr vt d
+load net {ACC1:acc#47.itm(10)} -attr vt d
+load net {ACC1:acc#47.itm(11)} -attr vt d
+load net {ACC1:acc#47.itm(12)} -attr vt d
+load netBundle {ACC1:acc#47.itm} 13 {ACC1:acc#47.itm(0)} {ACC1:acc#47.itm(1)} {ACC1:acc#47.itm(2)} {ACC1:acc#47.itm(3)} {ACC1:acc#47.itm(4)} {ACC1:acc#47.itm(5)} {ACC1:acc#47.itm(6)} {ACC1:acc#47.itm(7)} {ACC1:acc#47.itm(8)} {ACC1:acc#47.itm(9)} {ACC1:acc#47.itm(10)} {ACC1:acc#47.itm(11)} {ACC1:acc#47.itm(12)} -attr xrf 1659 -attr oid 44 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {conc.itm(0)} -attr vt d
+load net {conc.itm(1)} -attr vt d
+load net {conc.itm(2)} -attr vt d
+load net {conc.itm(3)} -attr vt d
+load net {conc.itm(4)} -attr vt d
+load net {conc.itm(5)} -attr vt d
+load net {conc.itm(6)} -attr vt d
+load net {conc.itm(7)} -attr vt d
+load net {conc.itm(8)} -attr vt d
+load net {conc.itm(9)} -attr vt d
+load net {conc.itm(10)} -attr vt d
+load net {conc.itm(11)} -attr vt d
+load netBundle {conc.itm} 12 {conc.itm(0)} {conc.itm(1)} {conc.itm(2)} {conc.itm(3)} {conc.itm(4)} {conc.itm(5)} {conc.itm(6)} {conc.itm(7)} {conc.itm(8)} {conc.itm(9)} {conc.itm(10)} {conc.itm(11)} -attr xrf 1660 -attr oid 45 -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:slc#1.itm(0)} -attr vt d
+load net {ACC1:slc#1.itm(1)} -attr vt d
+load net {ACC1:slc#1.itm(2)} -attr vt d
+load net {ACC1:slc#1.itm(3)} -attr vt d
+load net {ACC1:slc#1.itm(4)} -attr vt d
+load net {ACC1:slc#1.itm(5)} -attr vt d
+load net {ACC1:slc#1.itm(6)} -attr vt d
+load net {ACC1:slc#1.itm(7)} -attr vt d
+load net {ACC1:slc#1.itm(8)} -attr vt d
+load net {ACC1:slc#1.itm(9)} -attr vt d
+load net {ACC1:slc#1.itm(10)} -attr vt d
+load netBundle {ACC1:slc#1.itm} 11 {ACC1:slc#1.itm(0)} {ACC1:slc#1.itm(1)} {ACC1:slc#1.itm(2)} {ACC1:slc#1.itm(3)} {ACC1:slc#1.itm(4)} {ACC1:slc#1.itm(5)} {ACC1:slc#1.itm(6)} {ACC1:slc#1.itm(7)} {ACC1:slc#1.itm(8)} {ACC1:slc#1.itm(9)} {ACC1:slc#1.itm(10)} -attr xrf 1661 -attr oid 46 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc#45.itm(0)} -attr vt d
+load net {ACC1:acc#45.itm(1)} -attr vt d
+load net {ACC1:acc#45.itm(2)} -attr vt d
+load net {ACC1:acc#45.itm(3)} -attr vt d
+load net {ACC1:acc#45.itm(4)} -attr vt d
+load net {ACC1:acc#45.itm(5)} -attr vt d
+load net {ACC1:acc#45.itm(6)} -attr vt d
+load net {ACC1:acc#45.itm(7)} -attr vt d
+load net {ACC1:acc#45.itm(8)} -attr vt d
+load net {ACC1:acc#45.itm(9)} -attr vt d
+load net {ACC1:acc#45.itm(10)} -attr vt d
+load net {ACC1:acc#45.itm(11)} -attr vt d
+load netBundle {ACC1:acc#45.itm} 12 {ACC1:acc#45.itm(0)} {ACC1:acc#45.itm(1)} {ACC1:acc#45.itm(2)} {ACC1:acc#45.itm(3)} {ACC1:acc#45.itm(4)} {ACC1:acc#45.itm(5)} {ACC1:acc#45.itm(6)} {ACC1:acc#45.itm(7)} {ACC1:acc#45.itm(8)} {ACC1:acc#45.itm(9)} {ACC1:acc#45.itm(10)} {ACC1:acc#45.itm(11)} -attr xrf 1662 -attr oid 47 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {conc#103.itm(0)} -attr vt d
+load net {conc#103.itm(1)} -attr vt d
+load net {conc#103.itm(2)} -attr vt d
+load net {conc#103.itm(3)} -attr vt d
+load net {conc#103.itm(4)} -attr vt d
+load net {conc#103.itm(5)} -attr vt d
+load net {conc#103.itm(6)} -attr vt d
+load net {conc#103.itm(7)} -attr vt d
+load net {conc#103.itm(8)} -attr vt d
+load net {conc#103.itm(9)} -attr vt d
+load net {conc#103.itm(10)} -attr vt d
+load netBundle {conc#103.itm} 11 {conc#103.itm(0)} {conc#103.itm(1)} {conc#103.itm(2)} {conc#103.itm(3)} {conc#103.itm(4)} {conc#103.itm(5)} {conc#103.itm(6)} {conc#103.itm(7)} {conc#103.itm(8)} {conc#103.itm(9)} {conc#103.itm(10)} -attr xrf 1663 -attr oid 48 -attr vt d -attr @path {/sobel/sobel:core/conc#103.itm}
+load net {conc#104.itm(0)} -attr vt d
+load net {conc#104.itm(1)} -attr vt d
+load net {conc#104.itm(2)} -attr vt d
+load net {conc#104.itm(3)} -attr vt d
+load net {conc#104.itm(4)} -attr vt d
+load net {conc#104.itm(5)} -attr vt d
+load net {conc#104.itm(6)} -attr vt d
+load net {conc#104.itm(7)} -attr vt d
+load net {conc#104.itm(8)} -attr vt d
+load net {conc#104.itm(9)} -attr vt d
+load net {conc#104.itm(10)} -attr vt d
+load netBundle {conc#104.itm} 11 {conc#104.itm(0)} {conc#104.itm(1)} {conc#104.itm(2)} {conc#104.itm(3)} {conc#104.itm(4)} {conc#104.itm(5)} {conc#104.itm(6)} {conc#104.itm(7)} {conc#104.itm(8)} {conc#104.itm(9)} {conc#104.itm(10)} -attr xrf 1664 -attr oid 49 -attr vt d -attr @path {/sobel/sobel:core/conc#104.itm}
+load net {conc#105.itm(0)} -attr vt d
+load net {conc#105.itm(1)} -attr vt d
+load net {conc#105.itm(2)} -attr vt d
+load net {conc#105.itm(3)} -attr vt d
+load net {conc#105.itm(4)} -attr vt d
+load net {conc#105.itm(5)} -attr vt d
+load net {conc#105.itm(6)} -attr vt d
+load net {conc#105.itm(7)} -attr vt d
+load net {conc#105.itm(8)} -attr vt d
+load net {conc#105.itm(9)} -attr vt d
+load net {conc#105.itm(10)} -attr vt d
+load net {conc#105.itm(11)} -attr vt d
+load netBundle {conc#105.itm} 12 {conc#105.itm(0)} {conc#105.itm(1)} {conc#105.itm(2)} {conc#105.itm(3)} {conc#105.itm(4)} {conc#105.itm(5)} {conc#105.itm(6)} {conc#105.itm(7)} {conc#105.itm(8)} {conc#105.itm(9)} {conc#105.itm(10)} {conc#105.itm(11)} -attr xrf 1665 -attr oid 50 -attr vt d -attr @path {/sobel/sobel:core/conc#105.itm}
+load net {ACC1:slc#3.itm(0)} -attr vt d
+load net {ACC1:slc#3.itm(1)} -attr vt d
+load net {ACC1:slc#3.itm(2)} -attr vt d
+load net {ACC1:slc#3.itm(3)} -attr vt d
+load net {ACC1:slc#3.itm(4)} -attr vt d
+load net {ACC1:slc#3.itm(5)} -attr vt d
+load net {ACC1:slc#3.itm(6)} -attr vt d
+load net {ACC1:slc#3.itm(7)} -attr vt d
+load net {ACC1:slc#3.itm(8)} -attr vt d
+load net {ACC1:slc#3.itm(9)} -attr vt d
+load net {ACC1:slc#3.itm(10)} -attr vt d
+load netBundle {ACC1:slc#3.itm} 11 {ACC1:slc#3.itm(0)} {ACC1:slc#3.itm(1)} {ACC1:slc#3.itm(2)} {ACC1:slc#3.itm(3)} {ACC1:slc#3.itm(4)} {ACC1:slc#3.itm(5)} {ACC1:slc#3.itm(6)} {ACC1:slc#3.itm(7)} {ACC1:slc#3.itm(8)} {ACC1:slc#3.itm(9)} {ACC1:slc#3.itm(10)} -attr xrf 1666 -attr oid 51 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#44.itm(0)} -attr vt d
+load net {ACC1:acc#44.itm(1)} -attr vt d
+load net {ACC1:acc#44.itm(2)} -attr vt d
+load net {ACC1:acc#44.itm(3)} -attr vt d
+load net {ACC1:acc#44.itm(4)} -attr vt d
+load net {ACC1:acc#44.itm(5)} -attr vt d
+load net {ACC1:acc#44.itm(6)} -attr vt d
+load net {ACC1:acc#44.itm(7)} -attr vt d
+load net {ACC1:acc#44.itm(8)} -attr vt d
+load net {ACC1:acc#44.itm(9)} -attr vt d
+load net {ACC1:acc#44.itm(10)} -attr vt d
+load net {ACC1:acc#44.itm(11)} -attr vt d
+load netBundle {ACC1:acc#44.itm} 12 {ACC1:acc#44.itm(0)} {ACC1:acc#44.itm(1)} {ACC1:acc#44.itm(2)} {ACC1:acc#44.itm(3)} {ACC1:acc#44.itm(4)} {ACC1:acc#44.itm(5)} {ACC1:acc#44.itm(6)} {ACC1:acc#44.itm(7)} {ACC1:acc#44.itm(8)} {ACC1:acc#44.itm(9)} {ACC1:acc#44.itm(10)} {ACC1:acc#44.itm(11)} -attr xrf 1667 -attr oid 52 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {conc#106.itm(0)} -attr vt d
+load net {conc#106.itm(1)} -attr vt d
+load net {conc#106.itm(2)} -attr vt d
+load net {conc#106.itm(3)} -attr vt d
+load net {conc#106.itm(4)} -attr vt d
+load net {conc#106.itm(5)} -attr vt d
+load net {conc#106.itm(6)} -attr vt d
+load net {conc#106.itm(7)} -attr vt d
+load net {conc#106.itm(8)} -attr vt d
+load net {conc#106.itm(9)} -attr vt d
+load net {conc#106.itm(10)} -attr vt d
+load netBundle {conc#106.itm} 11 {conc#106.itm(0)} {conc#106.itm(1)} {conc#106.itm(2)} {conc#106.itm(3)} {conc#106.itm(4)} {conc#106.itm(5)} {conc#106.itm(6)} {conc#106.itm(7)} {conc#106.itm(8)} {conc#106.itm(9)} {conc#106.itm(10)} -attr xrf 1668 -attr oid 53 -attr vt d -attr @path {/sobel/sobel:core/conc#106.itm}
+load net {ACC1:not.itm(0)} -attr vt d
+load net {ACC1:not.itm(1)} -attr vt d
+load net {ACC1:not.itm(2)} -attr vt d
+load net {ACC1:not.itm(3)} -attr vt d
+load net {ACC1:not.itm(4)} -attr vt d
+load net {ACC1:not.itm(5)} -attr vt d
+load net {ACC1:not.itm(6)} -attr vt d
+load net {ACC1:not.itm(7)} -attr vt d
+load net {ACC1:not.itm(8)} -attr vt d
+load net {ACC1:not.itm(9)} -attr vt d
+load netBundle {ACC1:not.itm} 10 {ACC1:not.itm(0)} {ACC1:not.itm(1)} {ACC1:not.itm(2)} {ACC1:not.itm(3)} {ACC1:not.itm(4)} {ACC1:not.itm(5)} {ACC1:not.itm(6)} {ACC1:not.itm(7)} {ACC1:not.itm(8)} {ACC1:not.itm(9)} -attr xrf 1669 -attr oid 54 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {slc(regs.regs(0).sva#7).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#7).itm} 10 {slc(regs.regs(0).sva#7).itm(0)} {slc(regs.regs(0).sva#7).itm(1)} {slc(regs.regs(0).sva#7).itm(2)} {slc(regs.regs(0).sva#7).itm(3)} {slc(regs.regs(0).sva#7).itm(4)} {slc(regs.regs(0).sva#7).itm(5)} {slc(regs.regs(0).sva#7).itm(6)} {slc(regs.regs(0).sva#7).itm(7)} {slc(regs.regs(0).sva#7).itm(8)} {slc(regs.regs(0).sva#7).itm(9)} -attr xrf 1670 -attr oid 55 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {conc#107.itm(0)} -attr vt d
+load net {conc#107.itm(1)} -attr vt d
+load net {conc#107.itm(2)} -attr vt d
+load net {conc#107.itm(3)} -attr vt d
+load net {conc#107.itm(4)} -attr vt d
+load net {conc#107.itm(5)} -attr vt d
+load net {conc#107.itm(6)} -attr vt d
+load net {conc#107.itm(7)} -attr vt d
+load net {conc#107.itm(8)} -attr vt d
+load net {conc#107.itm(9)} -attr vt d
+load net {conc#107.itm(10)} -attr vt d
+load netBundle {conc#107.itm} 11 {conc#107.itm(0)} {conc#107.itm(1)} {conc#107.itm(2)} {conc#107.itm(3)} {conc#107.itm(4)} {conc#107.itm(5)} {conc#107.itm(6)} {conc#107.itm(7)} {conc#107.itm(8)} {conc#107.itm(9)} {conc#107.itm(10)} -attr xrf 1671 -attr oid 56 -attr vt d -attr @path {/sobel/sobel:core/conc#107.itm}
+load net {ACC1:not#20.itm(0)} -attr vt d
+load net {ACC1:not#20.itm(1)} -attr vt d
+load net {ACC1:not#20.itm(2)} -attr vt d
+load net {ACC1:not#20.itm(3)} -attr vt d
+load net {ACC1:not#20.itm(4)} -attr vt d
+load net {ACC1:not#20.itm(5)} -attr vt d
+load net {ACC1:not#20.itm(6)} -attr vt d
+load net {ACC1:not#20.itm(7)} -attr vt d
+load net {ACC1:not#20.itm(8)} -attr vt d
+load net {ACC1:not#20.itm(9)} -attr vt d
+load netBundle {ACC1:not#20.itm} 10 {ACC1:not#20.itm(0)} {ACC1:not#20.itm(1)} {ACC1:not#20.itm(2)} {ACC1:not#20.itm(3)} {ACC1:not#20.itm(4)} {ACC1:not#20.itm(5)} {ACC1:not#20.itm(6)} {ACC1:not#20.itm(7)} {ACC1:not#20.itm(8)} {ACC1:not#20.itm(9)} -attr xrf 1672 -attr oid 57 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#20.itm}
+load net {slc(regs.regs(0).sva#8).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#8).itm} 10 {slc(regs.regs(0).sva#8).itm(0)} {slc(regs.regs(0).sva#8).itm(1)} {slc(regs.regs(0).sva#8).itm(2)} {slc(regs.regs(0).sva#8).itm(3)} {slc(regs.regs(0).sva#8).itm(4)} {slc(regs.regs(0).sva#8).itm(5)} {slc(regs.regs(0).sva#8).itm(6)} {slc(regs.regs(0).sva#8).itm(7)} {slc(regs.regs(0).sva#8).itm(8)} {slc(regs.regs(0).sva#8).itm(9)} -attr xrf 1673 -attr oid 58 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {conc#108.itm(0)} -attr vt d
+load net {conc#108.itm(1)} -attr vt d
+load net {conc#108.itm(2)} -attr vt d
+load net {conc#108.itm(3)} -attr vt d
+load net {conc#108.itm(4)} -attr vt d
+load net {conc#108.itm(5)} -attr vt d
+load net {conc#108.itm(6)} -attr vt d
+load net {conc#108.itm(7)} -attr vt d
+load net {conc#108.itm(8)} -attr vt d
+load net {conc#108.itm(9)} -attr vt d
+load net {conc#108.itm(10)} -attr vt d
+load net {conc#108.itm(11)} -attr vt d
+load netBundle {conc#108.itm} 12 {conc#108.itm(0)} {conc#108.itm(1)} {conc#108.itm(2)} {conc#108.itm(3)} {conc#108.itm(4)} {conc#108.itm(5)} {conc#108.itm(6)} {conc#108.itm(7)} {conc#108.itm(8)} {conc#108.itm(9)} {conc#108.itm(10)} {conc#108.itm(11)} -attr xrf 1674 -attr oid 59 -attr vt d -attr @path {/sobel/sobel:core/conc#108.itm}
+load net {ACC1:acc#56.itm(0)} -attr vt d
+load net {ACC1:acc#56.itm(1)} -attr vt d
+load net {ACC1:acc#56.itm(2)} -attr vt d
+load net {ACC1:acc#56.itm(3)} -attr vt d
+load net {ACC1:acc#56.itm(4)} -attr vt d
+load net {ACC1:acc#56.itm(5)} -attr vt d
+load net {ACC1:acc#56.itm(6)} -attr vt d
+load net {ACC1:acc#56.itm(7)} -attr vt d
+load net {ACC1:acc#56.itm(8)} -attr vt d
+load net {ACC1:acc#56.itm(9)} -attr vt d
+load net {ACC1:acc#56.itm(10)} -attr vt d
+load netBundle {ACC1:acc#56.itm} 11 {ACC1:acc#56.itm(0)} {ACC1:acc#56.itm(1)} {ACC1:acc#56.itm(2)} {ACC1:acc#56.itm(3)} {ACC1:acc#56.itm(4)} {ACC1:acc#56.itm(5)} {ACC1:acc#56.itm(6)} {ACC1:acc#56.itm(7)} {ACC1:acc#56.itm(8)} {ACC1:acc#56.itm(9)} {ACC1:acc#56.itm(10)} -attr xrf 1675 -attr oid 60 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#56.itm}
+load net {ACC1:not#21.itm(0)} -attr vt d
+load net {ACC1:not#21.itm(1)} -attr vt d
+load net {ACC1:not#21.itm(2)} -attr vt d
+load net {ACC1:not#21.itm(3)} -attr vt d
+load net {ACC1:not#21.itm(4)} -attr vt d
+load net {ACC1:not#21.itm(5)} -attr vt d
+load net {ACC1:not#21.itm(6)} -attr vt d
+load net {ACC1:not#21.itm(7)} -attr vt d
+load net {ACC1:not#21.itm(8)} -attr vt d
+load net {ACC1:not#21.itm(9)} -attr vt d
+load netBundle {ACC1:not#21.itm} 10 {ACC1:not#21.itm(0)} {ACC1:not#21.itm(1)} {ACC1:not#21.itm(2)} {ACC1:not#21.itm(3)} {ACC1:not#21.itm(4)} {ACC1:not#21.itm(5)} {ACC1:not#21.itm(6)} {ACC1:not#21.itm(7)} {ACC1:not#21.itm(8)} {ACC1:not#21.itm(9)} -attr xrf 1676 -attr oid 61 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {slc(regs.regs(0).sva#9).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#9).itm} 10 {slc(regs.regs(0).sva#9).itm(0)} {slc(regs.regs(0).sva#9).itm(1)} {slc(regs.regs(0).sva#9).itm(2)} {slc(regs.regs(0).sva#9).itm(3)} {slc(regs.regs(0).sva#9).itm(4)} {slc(regs.regs(0).sva#9).itm(5)} {slc(regs.regs(0).sva#9).itm(6)} {slc(regs.regs(0).sva#9).itm(7)} {slc(regs.regs(0).sva#9).itm(8)} {slc(regs.regs(0).sva#9).itm(9)} -attr xrf 1677 -attr oid 62 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {FRAME:slc#7.itm(0)} -attr vt d
+load net {FRAME:slc#7.itm(1)} -attr vt d
+load net {FRAME:slc#7.itm(2)} -attr vt d
+load net {FRAME:slc#7.itm(3)} -attr vt d
+load net {FRAME:slc#7.itm(4)} -attr vt d
+load netBundle {FRAME:slc#7.itm} 5 {FRAME:slc#7.itm(0)} {FRAME:slc#7.itm(1)} {FRAME:slc#7.itm(2)} {FRAME:slc#7.itm(3)} {FRAME:slc#7.itm(4)} -attr xrf 1678 -attr oid 63 -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:acc#40.itm(0)} -attr vt d
+load net {FRAME:acc#40.itm(1)} -attr vt d
+load net {FRAME:acc#40.itm(2)} -attr vt d
+load net {FRAME:acc#40.itm(3)} -attr vt d
+load net {FRAME:acc#40.itm(4)} -attr vt d
+load net {FRAME:acc#40.itm(5)} -attr vt d
+load netBundle {FRAME:acc#40.itm} 6 {FRAME:acc#40.itm(0)} {FRAME:acc#40.itm(1)} {FRAME:acc#40.itm(2)} {FRAME:acc#40.itm(3)} {FRAME:acc#40.itm(4)} {FRAME:acc#40.itm(5)} -attr xrf 1679 -attr oid 64 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {conc#109.itm(0)} -attr vt d
+load net {conc#109.itm(1)} -attr vt d
+load net {conc#109.itm(2)} -attr vt d
+load net {conc#109.itm(3)} -attr vt d
+load net {conc#109.itm(4)} -attr vt d
+load netBundle {conc#109.itm} 5 {conc#109.itm(0)} {conc#109.itm(1)} {conc#109.itm(2)} {conc#109.itm(3)} {conc#109.itm(4)} -attr xrf 1680 -attr oid 65 -attr vt d -attr @path {/sobel/sobel:core/conc#109.itm}
+load net {FRAME:not#44.itm(0)} -attr vt d
+load net {FRAME:not#44.itm(1)} -attr vt d
+load net {FRAME:not#44.itm(2)} -attr vt d
+load netBundle {FRAME:not#44.itm} 3 {FRAME:not#44.itm(0)} {FRAME:not#44.itm(1)} {FRAME:not#44.itm(2)} -attr xrf 1681 -attr oid 66 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#44.itm}
+load net {slc(ACC1:acc.psp.sva)#5.itm(0)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#5.itm(1)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc.psp.sva)#5.itm} 3 {slc(ACC1:acc.psp.sva)#5.itm(0)} {slc(ACC1:acc.psp.sva)#5.itm(1)} {slc(ACC1:acc.psp.sva)#5.itm(2)} -attr xrf 1682 -attr oid 67 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#5.itm}
+load net {FRAME:conc#49.itm(0)} -attr vt d
+load net {FRAME:conc#49.itm(1)} -attr vt d
+load net {FRAME:conc#49.itm(2)} -attr vt d
+load net {FRAME:conc#49.itm(3)} -attr vt d
+load netBundle {FRAME:conc#49.itm} 4 {FRAME:conc#49.itm(0)} {FRAME:conc#49.itm(1)} {FRAME:conc#49.itm(2)} {FRAME:conc#49.itm(3)} -attr xrf 1683 -attr oid 68 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#49.itm}
+load net {slc(FRAME:acc#47.psp)#3.itm(0)} -attr vt d
+load net {slc(FRAME:acc#47.psp)#3.itm(1)} -attr vt d
+load net {slc(FRAME:acc#47.psp)#3.itm(2)} -attr vt d
+load netBundle {slc(FRAME:acc#47.psp)#3.itm} 3 {slc(FRAME:acc#47.psp)#3.itm(0)} {slc(FRAME:acc#47.psp)#3.itm(1)} {slc(FRAME:acc#47.psp)#3.itm(2)} -attr xrf 1684 -attr oid 69 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#47.psp)#3.itm}
+load net {conc#110.itm(0)} -attr vt d
+load net {conc#110.itm(1)} -attr vt d
+load net {conc#110.itm(2)} -attr vt d
+load net {conc#110.itm(3)} -attr vt d
+load net {conc#110.itm(4)} -attr vt d
+load netBundle {conc#110.itm} 5 {conc#110.itm(0)} {conc#110.itm(1)} {conc#110.itm(2)} {conc#110.itm(3)} {conc#110.itm(4)} -attr xrf 1685 -attr oid 70 -attr vt d -attr @path {/sobel/sobel:core/conc#110.itm}
+load net {slc(FRAME:acc#47.psp)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#47.psp)#1.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#47.psp)#1.itm} 2 {slc(FRAME:acc#47.psp)#1.itm(0)} {slc(FRAME:acc#47.psp)#1.itm(1)} -attr xrf 1686 -attr oid 71 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#47.psp)#1.itm}
+load net {FRAME:conc#52.itm(0)} -attr vt d
+load net {FRAME:conc#52.itm(1)} -attr vt d
+load net {FRAME:conc#52.itm(2)} -attr vt d
+load net {FRAME:conc#52.itm(3)} -attr vt d
+load netBundle {FRAME:conc#52.itm} 4 {FRAME:conc#52.itm(0)} {FRAME:conc#52.itm(1)} {FRAME:conc#52.itm(2)} {FRAME:conc#52.itm(3)} -attr xrf 1687 -attr oid 72 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#52.itm}
+load net {FRAME:not#6.itm(0)} -attr vt d
+load net {FRAME:not#6.itm(1)} -attr vt d
+load net {FRAME:not#6.itm(2)} -attr vt d
+load netBundle {FRAME:not#6.itm} 3 {FRAME:not#6.itm(0)} {FRAME:not#6.itm(1)} {FRAME:not#6.itm(2)} -attr xrf 1688 -attr oid 73 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {slc(FRAME:acc#47.psp).itm(0)} -attr vt d
+load net {slc(FRAME:acc#47.psp).itm(1)} -attr vt d
+load net {slc(FRAME:acc#47.psp).itm(2)} -attr vt d
+load netBundle {slc(FRAME:acc#47.psp).itm} 3 {slc(FRAME:acc#47.psp).itm(0)} {slc(FRAME:acc#47.psp).itm(1)} {slc(FRAME:acc#47.psp).itm(2)} -attr xrf 1689 -attr oid 74 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#47.psp).itm}
+load net {FRAME:exs#17.itm(0)} -attr vt d
+load net {FRAME:exs#17.itm(1)} -attr vt d
+load net {FRAME:exs#17.itm(2)} -attr vt d
+load net {FRAME:exs#17.itm(3)} -attr vt d
+load net {FRAME:exs#17.itm(4)} -attr vt d
+load netBundle {FRAME:exs#17.itm} 5 {FRAME:exs#17.itm(0)} {FRAME:exs#17.itm(1)} {FRAME:exs#17.itm(2)} {FRAME:exs#17.itm(3)} {FRAME:exs#17.itm(4)} -attr xrf 1690 -attr oid 75 -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#17.itm}
+load net {FRAME:conc#31.itm(0)} -attr vt d
+load net {FRAME:conc#31.itm(1)} -attr vt d
+load net {FRAME:conc#31.itm(2)} -attr vt d
+load netBundle {FRAME:conc#31.itm} 3 {FRAME:conc#31.itm(0)} {FRAME:conc#31.itm(1)} {FRAME:conc#31.itm(2)} -attr xrf 1691 -attr oid 76 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#31.itm}
+load net {conc#154.itm(0)} -attr vt d
+load net {conc#154.itm(1)} -attr vt d
+load net {conc#154.itm(2)} -attr vt d
+load net {conc#154.itm(3)} -attr vt d
+load net {conc#154.itm(4)} -attr vt d
+load net {conc#154.itm(5)} -attr vt d
+load net {conc#154.itm(6)} -attr vt d
+load net {conc#154.itm(7)} -attr vt d
+load net {conc#154.itm(8)} -attr vt d
+load net {conc#154.itm(9)} -attr vt d
+load net {conc#154.itm(10)} -attr vt d
+load net {conc#154.itm(11)} -attr vt d
+load netBundle {conc#154.itm} 12 {conc#154.itm(0)} {conc#154.itm(1)} {conc#154.itm(2)} {conc#154.itm(3)} {conc#154.itm(4)} {conc#154.itm(5)} {conc#154.itm(6)} {conc#154.itm(7)} {conc#154.itm(8)} {conc#154.itm(9)} {conc#154.itm(10)} {conc#154.itm(11)} -attr xrf 1692 -attr oid 77 -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {acc.itm(0)} -attr vt d
+load net {acc.itm(1)} -attr vt d
+load net {acc.itm(2)} -attr vt d
+load net {acc.itm(3)} -attr vt d
+load netBundle {acc.itm} 4 {acc.itm(0)} {acc.itm(1)} {acc.itm(2)} {acc.itm(3)} -attr xrf 1693 -attr oid 78 -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {exs#2.itm(0)} -attr vt d
+load net {exs#2.itm(1)} -attr vt d
+load net {exs#2.itm(2)} -attr vt d
+load netBundle {exs#2.itm} 3 {exs#2.itm(0)} {exs#2.itm(1)} {exs#2.itm(2)} -attr xrf 1694 -attr oid 79 -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {exs#14.itm(0)} -attr vt d
+load net {exs#14.itm(1)} -attr vt d
+load netBundle {exs#14.itm} 2 {exs#14.itm(0)} {exs#14.itm(1)} -attr xrf 1695 -attr oid 80 -attr vt d -attr @path {/sobel/sobel:core/exs#14.itm}
+load net {acc#4.itm(0)} -attr vt d
+load net {acc#4.itm(1)} -attr vt d
+load net {acc#4.itm(2)} -attr vt d
+load net {acc#4.itm(3)} -attr vt d
+load netBundle {acc#4.itm} 4 {acc#4.itm(0)} {acc#4.itm(1)} {acc#4.itm(2)} {acc#4.itm(3)} -attr xrf 1696 -attr oid 81 -attr vt d -attr @path {/sobel/sobel:core/acc#4.itm}
+load net {exs#3.itm(0)} -attr vt d
+load net {exs#3.itm(1)} -attr vt d
+load netBundle {exs#3.itm} 2 {exs#3.itm(0)} {exs#3.itm(1)} -attr xrf 1697 -attr oid 82 -attr vt d -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {conc#159.itm(0)} -attr vt d
+load net {conc#159.itm(1)} -attr vt d
+load net {conc#159.itm(2)} -attr vt d
+load netBundle {conc#159.itm} 3 {conc#159.itm(0)} {conc#159.itm(1)} {conc#159.itm(2)} -attr xrf 1698 -attr oid 83 -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {slc(FRAME:acc#24.sdt)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#24.sdt)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#24.sdt)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#24.sdt)#1.itm(3)} -attr vt d
+load net {slc(FRAME:acc#24.sdt)#1.itm(4)} -attr vt d
+load net {slc(FRAME:acc#24.sdt)#1.itm(5)} -attr vt d
+load net {slc(FRAME:acc#24.sdt)#1.itm(6)} -attr vt d
+load net {slc(FRAME:acc#24.sdt)#1.itm(7)} -attr vt d
+load net {slc(FRAME:acc#24.sdt)#1.itm(8)} -attr vt d
+load net {slc(FRAME:acc#24.sdt)#1.itm(9)} -attr vt d
+load net {slc(FRAME:acc#24.sdt)#1.itm(10)} -attr vt d
+load netBundle {slc(FRAME:acc#24.sdt)#1.itm} 11 {slc(FRAME:acc#24.sdt)#1.itm(0)} {slc(FRAME:acc#24.sdt)#1.itm(1)} {slc(FRAME:acc#24.sdt)#1.itm(2)} {slc(FRAME:acc#24.sdt)#1.itm(3)} {slc(FRAME:acc#24.sdt)#1.itm(4)} {slc(FRAME:acc#24.sdt)#1.itm(5)} {slc(FRAME:acc#24.sdt)#1.itm(6)} {slc(FRAME:acc#24.sdt)#1.itm(7)} {slc(FRAME:acc#24.sdt)#1.itm(8)} {slc(FRAME:acc#24.sdt)#1.itm(9)} {slc(FRAME:acc#24.sdt)#1.itm(10)} -attr xrf 1699 -attr oid 84 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#24.sdt)#1.itm}
+load net {FRAME:mul#2.itm(0)} -attr vt d
+load net {FRAME:mul#2.itm(1)} -attr vt d
+load net {FRAME:mul#2.itm(2)} -attr vt d
+load net {FRAME:mul#2.itm(3)} -attr vt d
+load net {FRAME:mul#2.itm(4)} -attr vt d
+load net {FRAME:mul#2.itm(5)} -attr vt d
+load net {FRAME:mul#2.itm(6)} -attr vt d
+load net {FRAME:mul#2.itm(7)} -attr vt d
+load net {FRAME:mul#2.itm(8)} -attr vt d
+load net {FRAME:mul#2.itm(9)} -attr vt d
+load net {FRAME:mul#2.itm(10)} -attr vt d
+load netBundle {FRAME:mul#2.itm} 11 {FRAME:mul#2.itm(0)} {FRAME:mul#2.itm(1)} {FRAME:mul#2.itm(2)} {FRAME:mul#2.itm(3)} {FRAME:mul#2.itm(4)} {FRAME:mul#2.itm(5)} {FRAME:mul#2.itm(6)} {FRAME:mul#2.itm(7)} {FRAME:mul#2.itm(8)} {FRAME:mul#2.itm(9)} {FRAME:mul#2.itm(10)} -attr xrf 1700 -attr oid 85 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:exs#13.itm(0)} -attr vt d
+load net {FRAME:exs#13.itm(1)} -attr vt d
+load netBundle {FRAME:exs#13.itm} 2 {FRAME:exs#13.itm(0)} {FRAME:exs#13.itm(1)} -attr xrf 1701 -attr oid 86 -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#13.itm}
+load net {FRAME:acc#23.itm(0)} -attr vt d
+load net {FRAME:acc#23.itm(1)} -attr vt d
+load net {FRAME:acc#23.itm(2)} -attr vt d
+load net {FRAME:acc#23.itm(3)} -attr vt d
+load net {FRAME:acc#23.itm(4)} -attr vt d
+load net {FRAME:acc#23.itm(5)} -attr vt d
+load net {FRAME:acc#23.itm(6)} -attr vt d
+load net {FRAME:acc#23.itm(7)} -attr vt d
+load net {FRAME:acc#23.itm(8)} -attr vt d
+load net {FRAME:acc#23.itm(9)} -attr vt d
+load netBundle {FRAME:acc#23.itm} 10 {FRAME:acc#23.itm(0)} {FRAME:acc#23.itm(1)} {FRAME:acc#23.itm(2)} {FRAME:acc#23.itm(3)} {FRAME:acc#23.itm(4)} {FRAME:acc#23.itm(5)} {FRAME:acc#23.itm(6)} {FRAME:acc#23.itm(7)} {FRAME:acc#23.itm(8)} {FRAME:acc#23.itm(9)} -attr xrf 1702 -attr oid 87 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:mul#3.itm(0)} -attr vt d
+load net {FRAME:mul#3.itm(1)} -attr vt d
+load net {FRAME:mul#3.itm(2)} -attr vt d
+load net {FRAME:mul#3.itm(3)} -attr vt d
+load net {FRAME:mul#3.itm(4)} -attr vt d
+load net {FRAME:mul#3.itm(5)} -attr vt d
+load net {FRAME:mul#3.itm(6)} -attr vt d
+load net {FRAME:mul#3.itm(7)} -attr vt d
+load net {FRAME:mul#3.itm(8)} -attr vt d
+load netBundle {FRAME:mul#3.itm} 9 {FRAME:mul#3.itm(0)} {FRAME:mul#3.itm(1)} {FRAME:mul#3.itm(2)} {FRAME:mul#3.itm(3)} {FRAME:mul#3.itm(4)} {FRAME:mul#3.itm(5)} {FRAME:mul#3.itm(6)} {FRAME:mul#3.itm(7)} {FRAME:mul#3.itm(8)} -attr xrf 1703 -attr oid 88 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {slc(ACC1:acc#42.psp.sva)#4.itm(0)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#4.itm(1)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#4.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#42.psp.sva)#4.itm} 3 {slc(ACC1:acc#42.psp.sva)#4.itm(0)} {slc(ACC1:acc#42.psp.sva)#4.itm(1)} {slc(ACC1:acc#42.psp.sva)#4.itm(2)} -attr xrf 1704 -attr oid 89 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#4.itm}
+load net {FRAME:acc#22.itm(0)} -attr vt d
+load net {FRAME:acc#22.itm(1)} -attr vt d
+load net {FRAME:acc#22.itm(2)} -attr vt d
+load net {FRAME:acc#22.itm(3)} -attr vt d
+load net {FRAME:acc#22.itm(4)} -attr vt d
+load net {FRAME:acc#22.itm(5)} -attr vt d
+load net {FRAME:acc#22.itm(6)} -attr vt d
+load net {FRAME:acc#22.itm(7)} -attr vt d
+load netBundle {FRAME:acc#22.itm} 8 {FRAME:acc#22.itm(0)} {FRAME:acc#22.itm(1)} {FRAME:acc#22.itm(2)} {FRAME:acc#22.itm(3)} {FRAME:acc#22.itm(4)} {FRAME:acc#22.itm(5)} {FRAME:acc#22.itm(6)} {FRAME:acc#22.itm(7)} -attr xrf 1705 -attr oid 90 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {slc(ACC1:acc#42.psp.sva)#5.itm(0)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#5.itm(1)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#5.itm(2)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#5.itm(3)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#5.itm(4)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#5.itm(5)} -attr vt d
+load netBundle {slc(ACC1:acc#42.psp.sva)#5.itm} 6 {slc(ACC1:acc#42.psp.sva)#5.itm(0)} {slc(ACC1:acc#42.psp.sva)#5.itm(1)} {slc(ACC1:acc#42.psp.sva)#5.itm(2)} {slc(ACC1:acc#42.psp.sva)#5.itm(3)} {slc(ACC1:acc#42.psp.sva)#5.itm(4)} {slc(ACC1:acc#42.psp.sva)#5.itm(5)} -attr xrf 1706 -attr oid 91 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#5.itm}
+load net {FRAME:acc#21.itm(0)} -attr vt d
+load net {FRAME:acc#21.itm(1)} -attr vt d
+load net {FRAME:acc#21.itm(2)} -attr vt d
+load net {FRAME:acc#21.itm(3)} -attr vt d
+load net {FRAME:acc#21.itm(4)} -attr vt d
+load netBundle {FRAME:acc#21.itm} 5 {FRAME:acc#21.itm(0)} {FRAME:acc#21.itm(1)} {FRAME:acc#21.itm(2)} {FRAME:acc#21.itm(3)} {FRAME:acc#21.itm(4)} -attr xrf 1707 -attr oid 92 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#20.itm(0)} -attr vt d
+load net {FRAME:acc#20.itm(1)} -attr vt d
+load net {FRAME:acc#20.itm(2)} -attr vt d
+load net {FRAME:acc#20.itm(3)} -attr vt d
+load net {FRAME:acc#20.itm(4)} -attr vt d
+load netBundle {FRAME:acc#20.itm} 5 {FRAME:acc#20.itm(0)} {FRAME:acc#20.itm(1)} {FRAME:acc#20.itm(2)} {FRAME:acc#20.itm(3)} {FRAME:acc#20.itm(4)} -attr xrf 1708 -attr oid 93 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#19.itm(0)} -attr vt d
+load net {FRAME:acc#19.itm(1)} -attr vt d
+load net {FRAME:acc#19.itm(2)} -attr vt d
+load net {FRAME:acc#19.itm(3)} -attr vt d
+load netBundle {FRAME:acc#19.itm} 4 {FRAME:acc#19.itm(0)} {FRAME:acc#19.itm(1)} {FRAME:acc#19.itm(2)} {FRAME:acc#19.itm(3)} -attr xrf 1709 -attr oid 94 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {conc#117.itm(0)} -attr vt d
+load net {conc#117.itm(1)} -attr vt d
+load net {conc#117.itm(2)} -attr vt d
+load netBundle {conc#117.itm} 3 {conc#117.itm(0)} {conc#117.itm(1)} {conc#117.itm(2)} -attr xrf 1710 -attr oid 95 -attr vt d -attr @path {/sobel/sobel:core/conc#117.itm}
+load net {conc#118.itm(0)} -attr vt d
+load net {conc#118.itm(1)} -attr vt d
+load net {conc#118.itm(2)} -attr vt d
+load net {conc#118.itm(3)} -attr vt d
+load net {conc#118.itm(4)} -attr vt d
+load netBundle {conc#118.itm} 5 {conc#118.itm(0)} {conc#118.itm(1)} {conc#118.itm(2)} {conc#118.itm(3)} {conc#118.itm(4)} -attr xrf 1711 -attr oid 96 -attr vt d -attr @path {/sobel/sobel:core/conc#118.itm}
+load net {slc(FRAME:acc#49.psp)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#49.psp)#1.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#49.psp)#1.itm} 2 {slc(FRAME:acc#49.psp)#1.itm(0)} {slc(FRAME:acc#49.psp)#1.itm(1)} -attr xrf 1712 -attr oid 97 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#49.psp)#1.itm}
+load net {FRAME:conc#42.itm(0)} -attr vt d
+load net {FRAME:conc#42.itm(1)} -attr vt d
+load net {FRAME:conc#42.itm(2)} -attr vt d
+load net {FRAME:conc#42.itm(3)} -attr vt d
+load netBundle {FRAME:conc#42.itm} 4 {FRAME:conc#42.itm(0)} {FRAME:conc#42.itm(1)} {FRAME:conc#42.itm(2)} {FRAME:conc#42.itm(3)} -attr xrf 1713 -attr oid 98 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#42.itm}
+load net {FRAME:not#15.itm(0)} -attr vt d
+load net {FRAME:not#15.itm(1)} -attr vt d
+load net {FRAME:not#15.itm(2)} -attr vt d
+load netBundle {FRAME:not#15.itm} 3 {FRAME:not#15.itm(0)} {FRAME:not#15.itm(1)} {FRAME:not#15.itm(2)} -attr xrf 1714 -attr oid 99 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#15.itm}
+load net {slc(FRAME:acc#49.psp)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#49.psp)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#49.psp)#2.itm(2)} -attr vt d
+load netBundle {slc(FRAME:acc#49.psp)#2.itm} 3 {slc(FRAME:acc#49.psp)#2.itm(0)} {slc(FRAME:acc#49.psp)#2.itm(1)} {slc(FRAME:acc#49.psp)#2.itm(2)} -attr xrf 1715 -attr oid 100 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#49.psp)#2.itm}
+load net {slc(FRAME:acc#49.psp)#3.itm(0)} -attr vt d
+load net {slc(FRAME:acc#49.psp)#3.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#49.psp)#3.itm} 2 {slc(FRAME:acc#49.psp)#3.itm(0)} {slc(FRAME:acc#49.psp)#3.itm(1)} -attr xrf 1716 -attr oid 101 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#49.psp)#3.itm}
+load net {FRAME:not#16.itm(0)} -attr vt d
+load net {FRAME:not#16.itm(1)} -attr vt d
+load net {FRAME:not#16.itm(2)} -attr vt d
+load netBundle {FRAME:not#16.itm} 3 {FRAME:not#16.itm(0)} {FRAME:not#16.itm(1)} {FRAME:not#16.itm(2)} -attr xrf 1717 -attr oid 102 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load net {slc(ACC1:acc#42.psp.sva)#6.itm(0)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#6.itm(1)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#42.psp.sva)#6.itm} 3 {slc(ACC1:acc#42.psp.sva)#6.itm(0)} {slc(ACC1:acc#42.psp.sva)#6.itm(1)} {slc(ACC1:acc#42.psp.sva)#6.itm(2)} -attr xrf 1718 -attr oid 103 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#6.itm}
+load net {conc#119.itm(0)} -attr vt d
+load net {conc#119.itm(1)} -attr vt d
+load net {conc#119.itm(2)} -attr vt d
+load net {conc#119.itm(3)} -attr vt d
+load net {conc#119.itm(4)} -attr vt d
+load netBundle {conc#119.itm} 5 {conc#119.itm(0)} {conc#119.itm(1)} {conc#119.itm(2)} {conc#119.itm(3)} {conc#119.itm(4)} -attr xrf 1719 -attr oid 104 -attr vt d -attr @path {/sobel/sobel:core/conc#119.itm}
+load net {conc#156.itm(0)} -attr vt d
+load net {conc#156.itm(1)} -attr vt d
+load net {conc#156.itm(2)} -attr vt d
+load net {conc#156.itm(3)} -attr vt d
+load net {conc#156.itm(4)} -attr vt d
+load net {conc#156.itm(5)} -attr vt d
+load net {conc#156.itm(6)} -attr vt d
+load net {conc#156.itm(7)} -attr vt d
+load net {conc#156.itm(8)} -attr vt d
+load net {conc#156.itm(9)} -attr vt d
+load net {conc#156.itm(10)} -attr vt d
+load net {conc#156.itm(11)} -attr vt d
+load netBundle {conc#156.itm} 12 {conc#156.itm(0)} {conc#156.itm(1)} {conc#156.itm(2)} {conc#156.itm(3)} {conc#156.itm(4)} {conc#156.itm(5)} {conc#156.itm(6)} {conc#156.itm(7)} {conc#156.itm(8)} {conc#156.itm(9)} {conc#156.itm(10)} {conc#156.itm(11)} -attr xrf 1720 -attr oid 105 -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {acc#5.itm(0)} -attr vt d
+load net {acc#5.itm(1)} -attr vt d
+load net {acc#5.itm(2)} -attr vt d
+load net {acc#5.itm(3)} -attr vt d
+load netBundle {acc#5.itm} 4 {acc#5.itm(0)} {acc#5.itm(1)} {acc#5.itm(2)} {acc#5.itm(3)} -attr xrf 1721 -attr oid 106 -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {exs#6.itm(0)} -attr vt d
+load net {exs#6.itm(1)} -attr vt d
+load net {exs#6.itm(2)} -attr vt d
+load netBundle {exs#6.itm} 3 {exs#6.itm(0)} {exs#6.itm(1)} {exs#6.itm(2)} -attr xrf 1722 -attr oid 107 -attr vt d -attr @path {/sobel/sobel:core/exs#6.itm}
+load net {exs.itm(0)} -attr vt d
+load net {exs.itm(1)} -attr vt d
+load netBundle {exs.itm} 2 {exs.itm(0)} {exs.itm(1)} -attr xrf 1723 -attr oid 108 -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {acc#6.itm(0)} -attr vt d
+load net {acc#6.itm(1)} -attr vt d
+load net {acc#6.itm(2)} -attr vt d
+load net {acc#6.itm(3)} -attr vt d
+load netBundle {acc#6.itm} 4 {acc#6.itm(0)} {acc#6.itm(1)} {acc#6.itm(2)} {acc#6.itm(3)} -attr xrf 1724 -attr oid 109 -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {exs#7.itm(0)} -attr vt d
+load net {exs#7.itm(1)} -attr vt d
+load netBundle {exs#7.itm} 2 {exs#7.itm(0)} {exs#7.itm(1)} -attr xrf 1725 -attr oid 110 -attr vt d -attr @path {/sobel/sobel:core/exs#7.itm}
+load net {conc#162.itm(0)} -attr vt d
+load net {conc#162.itm(1)} -attr vt d
+load net {conc#162.itm(2)} -attr vt d
+load netBundle {conc#162.itm} 3 {conc#162.itm(0)} {conc#162.itm(1)} {conc#162.itm(2)} -attr xrf 1726 -attr oid 111 -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {slc(FRAME:acc#37.sdt)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#37.sdt)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#37.sdt)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#37.sdt)#1.itm(3)} -attr vt d
+load net {slc(FRAME:acc#37.sdt)#1.itm(4)} -attr vt d
+load net {slc(FRAME:acc#37.sdt)#1.itm(5)} -attr vt d
+load net {slc(FRAME:acc#37.sdt)#1.itm(6)} -attr vt d
+load net {slc(FRAME:acc#37.sdt)#1.itm(7)} -attr vt d
+load net {slc(FRAME:acc#37.sdt)#1.itm(8)} -attr vt d
+load net {slc(FRAME:acc#37.sdt)#1.itm(9)} -attr vt d
+load net {slc(FRAME:acc#37.sdt)#1.itm(10)} -attr vt d
+load netBundle {slc(FRAME:acc#37.sdt)#1.itm} 11 {slc(FRAME:acc#37.sdt)#1.itm(0)} {slc(FRAME:acc#37.sdt)#1.itm(1)} {slc(FRAME:acc#37.sdt)#1.itm(2)} {slc(FRAME:acc#37.sdt)#1.itm(3)} {slc(FRAME:acc#37.sdt)#1.itm(4)} {slc(FRAME:acc#37.sdt)#1.itm(5)} {slc(FRAME:acc#37.sdt)#1.itm(6)} {slc(FRAME:acc#37.sdt)#1.itm(7)} {slc(FRAME:acc#37.sdt)#1.itm(8)} {slc(FRAME:acc#37.sdt)#1.itm(9)} {slc(FRAME:acc#37.sdt)#1.itm(10)} -attr xrf 1727 -attr oid 112 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#37.sdt)#1.itm}
+load net {FRAME:mul#4.itm(0)} -attr vt d
+load net {FRAME:mul#4.itm(1)} -attr vt d
+load net {FRAME:mul#4.itm(2)} -attr vt d
+load net {FRAME:mul#4.itm(3)} -attr vt d
+load net {FRAME:mul#4.itm(4)} -attr vt d
+load net {FRAME:mul#4.itm(5)} -attr vt d
+load net {FRAME:mul#4.itm(6)} -attr vt d
+load net {FRAME:mul#4.itm(7)} -attr vt d
+load net {FRAME:mul#4.itm(8)} -attr vt d
+load net {FRAME:mul#4.itm(9)} -attr vt d
+load net {FRAME:mul#4.itm(10)} -attr vt d
+load netBundle {FRAME:mul#4.itm} 11 {FRAME:mul#4.itm(0)} {FRAME:mul#4.itm(1)} {FRAME:mul#4.itm(2)} {FRAME:mul#4.itm(3)} {FRAME:mul#4.itm(4)} {FRAME:mul#4.itm(5)} {FRAME:mul#4.itm(6)} {FRAME:mul#4.itm(7)} {FRAME:mul#4.itm(8)} {FRAME:mul#4.itm(9)} {FRAME:mul#4.itm(10)} -attr xrf 1728 -attr oid 113 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:exs#15.itm(0)} -attr vt d
+load net {FRAME:exs#15.itm(1)} -attr vt d
+load netBundle {FRAME:exs#15.itm} 2 {FRAME:exs#15.itm(0)} {FRAME:exs#15.itm(1)} -attr xrf 1729 -attr oid 114 -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#15.itm}
+load net {FRAME:acc#36.itm(0)} -attr vt d
+load net {FRAME:acc#36.itm(1)} -attr vt d
+load net {FRAME:acc#36.itm(2)} -attr vt d
+load net {FRAME:acc#36.itm(3)} -attr vt d
+load net {FRAME:acc#36.itm(4)} -attr vt d
+load net {FRAME:acc#36.itm(5)} -attr vt d
+load net {FRAME:acc#36.itm(6)} -attr vt d
+load net {FRAME:acc#36.itm(7)} -attr vt d
+load net {FRAME:acc#36.itm(8)} -attr vt d
+load net {FRAME:acc#36.itm(9)} -attr vt d
+load netBundle {FRAME:acc#36.itm} 10 {FRAME:acc#36.itm(0)} {FRAME:acc#36.itm(1)} {FRAME:acc#36.itm(2)} {FRAME:acc#36.itm(3)} {FRAME:acc#36.itm(4)} {FRAME:acc#36.itm(5)} {FRAME:acc#36.itm(6)} {FRAME:acc#36.itm(7)} {FRAME:acc#36.itm(8)} {FRAME:acc#36.itm(9)} -attr xrf 1730 -attr oid 115 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:mul#5.itm(0)} -attr vt d
+load net {FRAME:mul#5.itm(1)} -attr vt d
+load net {FRAME:mul#5.itm(2)} -attr vt d
+load net {FRAME:mul#5.itm(3)} -attr vt d
+load net {FRAME:mul#5.itm(4)} -attr vt d
+load net {FRAME:mul#5.itm(5)} -attr vt d
+load net {FRAME:mul#5.itm(6)} -attr vt d
+load net {FRAME:mul#5.itm(7)} -attr vt d
+load net {FRAME:mul#5.itm(8)} -attr vt d
+load netBundle {FRAME:mul#5.itm} 9 {FRAME:mul#5.itm(0)} {FRAME:mul#5.itm(1)} {FRAME:mul#5.itm(2)} {FRAME:mul#5.itm(3)} {FRAME:mul#5.itm(4)} {FRAME:mul#5.itm(5)} {FRAME:mul#5.itm(6)} {FRAME:mul#5.itm(7)} {FRAME:mul#5.itm(8)} -attr xrf 1731 -attr oid 116 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {slc(ACC1:acc#43.psp.sva)#4.itm(0)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#4.itm(1)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#4.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#43.psp.sva)#4.itm} 3 {slc(ACC1:acc#43.psp.sva)#4.itm(0)} {slc(ACC1:acc#43.psp.sva)#4.itm(1)} {slc(ACC1:acc#43.psp.sva)#4.itm(2)} -attr xrf 1732 -attr oid 117 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#4.itm}
+load net {FRAME:acc#35.itm(0)} -attr vt d
+load net {FRAME:acc#35.itm(1)} -attr vt d
+load net {FRAME:acc#35.itm(2)} -attr vt d
+load net {FRAME:acc#35.itm(3)} -attr vt d
+load net {FRAME:acc#35.itm(4)} -attr vt d
+load net {FRAME:acc#35.itm(5)} -attr vt d
+load net {FRAME:acc#35.itm(6)} -attr vt d
+load net {FRAME:acc#35.itm(7)} -attr vt d
+load netBundle {FRAME:acc#35.itm} 8 {FRAME:acc#35.itm(0)} {FRAME:acc#35.itm(1)} {FRAME:acc#35.itm(2)} {FRAME:acc#35.itm(3)} {FRAME:acc#35.itm(4)} {FRAME:acc#35.itm(5)} {FRAME:acc#35.itm(6)} {FRAME:acc#35.itm(7)} -attr xrf 1733 -attr oid 118 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {slc(ACC1:acc#43.psp.sva)#5.itm(0)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#5.itm(1)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#5.itm(2)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#5.itm(3)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#5.itm(4)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#5.itm(5)} -attr vt d
+load netBundle {slc(ACC1:acc#43.psp.sva)#5.itm} 6 {slc(ACC1:acc#43.psp.sva)#5.itm(0)} {slc(ACC1:acc#43.psp.sva)#5.itm(1)} {slc(ACC1:acc#43.psp.sva)#5.itm(2)} {slc(ACC1:acc#43.psp.sva)#5.itm(3)} {slc(ACC1:acc#43.psp.sva)#5.itm(4)} {slc(ACC1:acc#43.psp.sva)#5.itm(5)} -attr xrf 1734 -attr oid 119 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#5.itm}
+load net {FRAME:acc#34.itm(0)} -attr vt d
+load net {FRAME:acc#34.itm(1)} -attr vt d
+load net {FRAME:acc#34.itm(2)} -attr vt d
+load net {FRAME:acc#34.itm(3)} -attr vt d
+load net {FRAME:acc#34.itm(4)} -attr vt d
+load netBundle {FRAME:acc#34.itm} 5 {FRAME:acc#34.itm(0)} {FRAME:acc#34.itm(1)} {FRAME:acc#34.itm(2)} {FRAME:acc#34.itm(3)} {FRAME:acc#34.itm(4)} -attr xrf 1735 -attr oid 120 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#33.itm(0)} -attr vt d
+load net {FRAME:acc#33.itm(1)} -attr vt d
+load net {FRAME:acc#33.itm(2)} -attr vt d
+load net {FRAME:acc#33.itm(3)} -attr vt d
+load net {FRAME:acc#33.itm(4)} -attr vt d
+load netBundle {FRAME:acc#33.itm} 5 {FRAME:acc#33.itm(0)} {FRAME:acc#33.itm(1)} {FRAME:acc#33.itm(2)} {FRAME:acc#33.itm(3)} {FRAME:acc#33.itm(4)} -attr xrf 1736 -attr oid 121 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#32.itm(0)} -attr vt d
+load net {FRAME:acc#32.itm(1)} -attr vt d
+load net {FRAME:acc#32.itm(2)} -attr vt d
+load net {FRAME:acc#32.itm(3)} -attr vt d
+load netBundle {FRAME:acc#32.itm} 4 {FRAME:acc#32.itm(0)} {FRAME:acc#32.itm(1)} {FRAME:acc#32.itm(2)} {FRAME:acc#32.itm(3)} -attr xrf 1737 -attr oid 122 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {conc#126.itm(0)} -attr vt d
+load net {conc#126.itm(1)} -attr vt d
+load net {conc#126.itm(2)} -attr vt d
+load netBundle {conc#126.itm} 3 {conc#126.itm(0)} {conc#126.itm(1)} {conc#126.itm(2)} -attr xrf 1738 -attr oid 123 -attr vt d -attr @path {/sobel/sobel:core/conc#126.itm}
+load net {conc#127.itm(0)} -attr vt d
+load net {conc#127.itm(1)} -attr vt d
+load net {conc#127.itm(2)} -attr vt d
+load net {conc#127.itm(3)} -attr vt d
+load net {conc#127.itm(4)} -attr vt d
+load netBundle {conc#127.itm} 5 {conc#127.itm(0)} {conc#127.itm(1)} {conc#127.itm(2)} {conc#127.itm(3)} {conc#127.itm(4)} -attr xrf 1739 -attr oid 124 -attr vt d -attr @path {/sobel/sobel:core/conc#127.itm}
+load net {slc(FRAME:acc#55.psp)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#55.psp)#1.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#55.psp)#1.itm} 2 {slc(FRAME:acc#55.psp)#1.itm(0)} {slc(FRAME:acc#55.psp)#1.itm(1)} -attr xrf 1740 -attr oid 125 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#55.psp)#1.itm}
+load net {FRAME:conc#46.itm(0)} -attr vt d
+load net {FRAME:conc#46.itm(1)} -attr vt d
+load net {FRAME:conc#46.itm(2)} -attr vt d
+load net {FRAME:conc#46.itm(3)} -attr vt d
+load netBundle {FRAME:conc#46.itm} 4 {FRAME:conc#46.itm(0)} {FRAME:conc#46.itm(1)} {FRAME:conc#46.itm(2)} {FRAME:conc#46.itm(3)} -attr xrf 1741 -attr oid 126 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#46.itm}
+load net {FRAME:not#24.itm(0)} -attr vt d
+load net {FRAME:not#24.itm(1)} -attr vt d
+load net {FRAME:not#24.itm(2)} -attr vt d
+load netBundle {FRAME:not#24.itm} 3 {FRAME:not#24.itm(0)} {FRAME:not#24.itm(1)} {FRAME:not#24.itm(2)} -attr xrf 1742 -attr oid 127 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#24.itm}
+load net {slc(FRAME:acc#55.psp)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#55.psp)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#55.psp)#2.itm(2)} -attr vt d
+load netBundle {slc(FRAME:acc#55.psp)#2.itm} 3 {slc(FRAME:acc#55.psp)#2.itm(0)} {slc(FRAME:acc#55.psp)#2.itm(1)} {slc(FRAME:acc#55.psp)#2.itm(2)} -attr xrf 1743 -attr oid 128 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#55.psp)#2.itm}
+load net {slc(FRAME:acc#55.psp)#3.itm(0)} -attr vt d
+load net {slc(FRAME:acc#55.psp)#3.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#55.psp)#3.itm} 2 {slc(FRAME:acc#55.psp)#3.itm(0)} {slc(FRAME:acc#55.psp)#3.itm(1)} -attr xrf 1744 -attr oid 129 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#55.psp)#3.itm}
+load net {FRAME:not#25.itm(0)} -attr vt d
+load net {FRAME:not#25.itm(1)} -attr vt d
+load net {FRAME:not#25.itm(2)} -attr vt d
+load netBundle {FRAME:not#25.itm} 3 {FRAME:not#25.itm(0)} {FRAME:not#25.itm(1)} {FRAME:not#25.itm(2)} -attr xrf 1745 -attr oid 130 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {slc(ACC1:acc#43.psp.sva)#6.itm(0)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#6.itm(1)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#43.psp.sva)#6.itm} 3 {slc(ACC1:acc#43.psp.sva)#6.itm(0)} {slc(ACC1:acc#43.psp.sva)#6.itm(1)} {slc(ACC1:acc#43.psp.sva)#6.itm(2)} -attr xrf 1746 -attr oid 131 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#6.itm}
+load net {conc#128.itm(0)} -attr vt d
+load net {conc#128.itm(1)} -attr vt d
+load net {conc#128.itm(2)} -attr vt d
+load net {conc#128.itm(3)} -attr vt d
+load net {conc#128.itm(4)} -attr vt d
+load netBundle {conc#128.itm} 5 {conc#128.itm(0)} {conc#128.itm(1)} {conc#128.itm(2)} {conc#128.itm(3)} {conc#128.itm(4)} -attr xrf 1747 -attr oid 132 -attr vt d -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {slc(FRAME:acc#13.sdt)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#13.sdt)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#13.sdt)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#13.sdt)#1.itm(3)} -attr vt d
+load net {slc(FRAME:acc#13.sdt)#1.itm(4)} -attr vt d
+load netBundle {slc(FRAME:acc#13.sdt)#1.itm} 5 {slc(FRAME:acc#13.sdt)#1.itm(0)} {slc(FRAME:acc#13.sdt)#1.itm(1)} {slc(FRAME:acc#13.sdt)#1.itm(2)} {slc(FRAME:acc#13.sdt)#1.itm(3)} {slc(FRAME:acc#13.sdt)#1.itm(4)} -attr xrf 1748 -attr oid 133 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#13.sdt)#1.itm}
+load net {FRAME:acc#12.itm(0)} -attr vt d
+load net {FRAME:acc#12.itm(1)} -attr vt d
+load net {FRAME:acc#12.itm(2)} -attr vt d
+load net {FRAME:acc#12.itm(3)} -attr vt d
+load net {FRAME:acc#12.itm(4)} -attr vt d
+load netBundle {FRAME:acc#12.itm} 5 {FRAME:acc#12.itm(0)} {FRAME:acc#12.itm(1)} {FRAME:acc#12.itm(2)} {FRAME:acc#12.itm(3)} {FRAME:acc#12.itm(4)} -attr xrf 1749 -attr oid 134 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#10.itm(0)} -attr vt d
+load net {FRAME:acc#10.itm(1)} -attr vt d
+load net {FRAME:acc#10.itm(2)} -attr vt d
+load net {FRAME:acc#10.itm(3)} -attr vt d
+load netBundle {FRAME:acc#10.itm} 4 {FRAME:acc#10.itm(0)} {FRAME:acc#10.itm(1)} {FRAME:acc#10.itm(2)} {FRAME:acc#10.itm(3)} -attr xrf 1750 -attr oid 135 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {slc(ACC1:acc.psp.sva)#4.itm(0)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#4.itm(1)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#4.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc.psp.sva)#4.itm} 3 {slc(ACC1:acc.psp.sva)#4.itm(0)} {slc(ACC1:acc.psp.sva)#4.itm(1)} {slc(ACC1:acc.psp.sva)#4.itm(2)} -attr xrf 1751 -attr oid 136 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#4.itm}
+load net {FRAME:not#31.itm(0)} -attr vt d
+load net {FRAME:not#31.itm(1)} -attr vt d
+load net {FRAME:not#31.itm(2)} -attr vt d
+load netBundle {FRAME:not#31.itm} 3 {FRAME:not#31.itm(0)} {FRAME:not#31.itm(1)} {FRAME:not#31.itm(2)} -attr xrf 1752 -attr oid 137 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#31.itm}
+load net {slc(ACC1:acc.psp.sva)#6.itm(0)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#6.itm(1)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc.psp.sva)#6.itm} 3 {slc(ACC1:acc.psp.sva)#6.itm(0)} {slc(ACC1:acc.psp.sva)#6.itm(1)} {slc(ACC1:acc.psp.sva)#6.itm(2)} -attr xrf 1753 -attr oid 138 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#6.itm}
+load net {FRAME:conc#34.itm(0)} -attr vt d
+load net {FRAME:conc#34.itm(1)} -attr vt d
+load net {FRAME:conc#34.itm(2)} -attr vt d
+load net {FRAME:conc#34.itm(3)} -attr vt d
+load netBundle {FRAME:conc#34.itm} 4 {FRAME:conc#34.itm(0)} {FRAME:conc#34.itm(1)} {FRAME:conc#34.itm(2)} {FRAME:conc#34.itm(3)} -attr xrf 1754 -attr oid 139 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34.itm}
+load net {FRAME:not#40.itm(0)} -attr vt d
+load net {FRAME:not#40.itm(1)} -attr vt d
+load net {FRAME:not#40.itm(2)} -attr vt d
+load netBundle {FRAME:not#40.itm} 3 {FRAME:not#40.itm(0)} {FRAME:not#40.itm(1)} {FRAME:not#40.itm(2)} -attr xrf 1755 -attr oid 140 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#40.itm}
+load net {slc(ACC1:acc.psp.sva)#3.itm(0)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#3.itm(1)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc.psp.sva)#3.itm} 3 {slc(ACC1:acc.psp.sva)#3.itm(0)} {slc(ACC1:acc.psp.sva)#3.itm(1)} {slc(ACC1:acc.psp.sva)#3.itm(2)} -attr xrf 1756 -attr oid 141 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#3.itm}
+load net {FRAME:acc#11.itm(0)} -attr vt d
+load net {FRAME:acc#11.itm(1)} -attr vt d
+load net {FRAME:acc#11.itm(2)} -attr vt d
+load net {FRAME:acc#11.itm(3)} -attr vt d
+load netBundle {FRAME:acc#11.itm} 4 {FRAME:acc#11.itm(0)} {FRAME:acc#11.itm(1)} {FRAME:acc#11.itm(2)} {FRAME:acc#11.itm(3)} -attr xrf 1757 -attr oid 142 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {conc#129.itm(0)} -attr vt d
+load net {conc#129.itm(1)} -attr vt d
+load net {conc#129.itm(2)} -attr vt d
+load netBundle {conc#129.itm} 3 {conc#129.itm(0)} {conc#129.itm(1)} {conc#129.itm(2)} -attr xrf 1758 -attr oid 143 -attr vt d -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {slc(ACC1:acc.psp.sva)#7.itm(0)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#7.itm(1)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc.psp.sva)#7.itm} 3 {slc(ACC1:acc.psp.sva)#7.itm(0)} {slc(ACC1:acc.psp.sva)#7.itm(1)} {slc(ACC1:acc.psp.sva)#7.itm(2)} -attr xrf 1759 -attr oid 144 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#7.itm}
+load net {ACC1:slc#11.itm(0)} -attr vt d
+load net {ACC1:slc#11.itm(1)} -attr vt d
+load net {ACC1:slc#11.itm(2)} -attr vt d
+load net {ACC1:slc#11.itm(3)} -attr vt d
+load net {ACC1:slc#11.itm(4)} -attr vt d
+load net {ACC1:slc#11.itm(5)} -attr vt d
+load net {ACC1:slc#11.itm(6)} -attr vt d
+load net {ACC1:slc#11.itm(7)} -attr vt d
+load net {ACC1:slc#11.itm(8)} -attr vt d
+load net {ACC1:slc#11.itm(9)} -attr vt d
+load net {ACC1:slc#11.itm(10)} -attr vt d
+load net {ACC1:slc#11.itm(11)} -attr vt d
+load netBundle {ACC1:slc#11.itm} 12 {ACC1:slc#11.itm(0)} {ACC1:slc#11.itm(1)} {ACC1:slc#11.itm(2)} {ACC1:slc#11.itm(3)} {ACC1:slc#11.itm(4)} {ACC1:slc#11.itm(5)} {ACC1:slc#11.itm(6)} {ACC1:slc#11.itm(7)} {ACC1:slc#11.itm(8)} {ACC1:slc#11.itm(9)} {ACC1:slc#11.itm(10)} {ACC1:slc#11.itm(11)} -attr xrf 1760 -attr oid 145 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#55.itm(0)} -attr vt d
+load net {ACC1:acc#55.itm(1)} -attr vt d
+load net {ACC1:acc#55.itm(2)} -attr vt d
+load net {ACC1:acc#55.itm(3)} -attr vt d
+load net {ACC1:acc#55.itm(4)} -attr vt d
+load net {ACC1:acc#55.itm(5)} -attr vt d
+load net {ACC1:acc#55.itm(6)} -attr vt d
+load net {ACC1:acc#55.itm(7)} -attr vt d
+load net {ACC1:acc#55.itm(8)} -attr vt d
+load net {ACC1:acc#55.itm(9)} -attr vt d
+load net {ACC1:acc#55.itm(10)} -attr vt d
+load net {ACC1:acc#55.itm(11)} -attr vt d
+load net {ACC1:acc#55.itm(12)} -attr vt d
+load netBundle {ACC1:acc#55.itm} 13 {ACC1:acc#55.itm(0)} {ACC1:acc#55.itm(1)} {ACC1:acc#55.itm(2)} {ACC1:acc#55.itm(3)} {ACC1:acc#55.itm(4)} {ACC1:acc#55.itm(5)} {ACC1:acc#55.itm(6)} {ACC1:acc#55.itm(7)} {ACC1:acc#55.itm(8)} {ACC1:acc#55.itm(9)} {ACC1:acc#55.itm(10)} {ACC1:acc#55.itm(11)} {ACC1:acc#55.itm(12)} -attr xrf 1761 -attr oid 146 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load net {conc#130.itm(0)} -attr vt d
+load net {conc#130.itm(1)} -attr vt d
+load net {conc#130.itm(2)} -attr vt d
+load net {conc#130.itm(3)} -attr vt d
+load net {conc#130.itm(4)} -attr vt d
+load net {conc#130.itm(5)} -attr vt d
+load net {conc#130.itm(6)} -attr vt d
+load net {conc#130.itm(7)} -attr vt d
+load net {conc#130.itm(8)} -attr vt d
+load net {conc#130.itm(9)} -attr vt d
+load net {conc#130.itm(10)} -attr vt d
+load net {conc#130.itm(11)} -attr vt d
+load netBundle {conc#130.itm} 12 {conc#130.itm(0)} {conc#130.itm(1)} {conc#130.itm(2)} {conc#130.itm(3)} {conc#130.itm(4)} {conc#130.itm(5)} {conc#130.itm(6)} {conc#130.itm(7)} {conc#130.itm(8)} {conc#130.itm(9)} {conc#130.itm(10)} {conc#130.itm(11)} -attr xrf 1762 -attr oid 147 -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {ACC1:slc#9.itm(0)} -attr vt d
+load net {ACC1:slc#9.itm(1)} -attr vt d
+load net {ACC1:slc#9.itm(2)} -attr vt d
+load net {ACC1:slc#9.itm(3)} -attr vt d
+load net {ACC1:slc#9.itm(4)} -attr vt d
+load net {ACC1:slc#9.itm(5)} -attr vt d
+load net {ACC1:slc#9.itm(6)} -attr vt d
+load net {ACC1:slc#9.itm(7)} -attr vt d
+load net {ACC1:slc#9.itm(8)} -attr vt d
+load net {ACC1:slc#9.itm(9)} -attr vt d
+load net {ACC1:slc#9.itm(10)} -attr vt d
+load netBundle {ACC1:slc#9.itm} 11 {ACC1:slc#9.itm(0)} {ACC1:slc#9.itm(1)} {ACC1:slc#9.itm(2)} {ACC1:slc#9.itm(3)} {ACC1:slc#9.itm(4)} {ACC1:slc#9.itm(5)} {ACC1:slc#9.itm(6)} {ACC1:slc#9.itm(7)} {ACC1:slc#9.itm(8)} {ACC1:slc#9.itm(9)} {ACC1:slc#9.itm(10)} -attr xrf 1763 -attr oid 148 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#9.itm}
+load net {ACC1:acc#53.itm(0)} -attr vt d
+load net {ACC1:acc#53.itm(1)} -attr vt d
+load net {ACC1:acc#53.itm(2)} -attr vt d
+load net {ACC1:acc#53.itm(3)} -attr vt d
+load net {ACC1:acc#53.itm(4)} -attr vt d
+load net {ACC1:acc#53.itm(5)} -attr vt d
+load net {ACC1:acc#53.itm(6)} -attr vt d
+load net {ACC1:acc#53.itm(7)} -attr vt d
+load net {ACC1:acc#53.itm(8)} -attr vt d
+load net {ACC1:acc#53.itm(9)} -attr vt d
+load net {ACC1:acc#53.itm(10)} -attr vt d
+load net {ACC1:acc#53.itm(11)} -attr vt d
+load netBundle {ACC1:acc#53.itm} 12 {ACC1:acc#53.itm(0)} {ACC1:acc#53.itm(1)} {ACC1:acc#53.itm(2)} {ACC1:acc#53.itm(3)} {ACC1:acc#53.itm(4)} {ACC1:acc#53.itm(5)} {ACC1:acc#53.itm(6)} {ACC1:acc#53.itm(7)} {ACC1:acc#53.itm(8)} {ACC1:acc#53.itm(9)} {ACC1:acc#53.itm(10)} {ACC1:acc#53.itm(11)} -attr xrf 1764 -attr oid 149 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53.itm}
+load net {conc#131.itm(0)} -attr vt d
+load net {conc#131.itm(1)} -attr vt d
+load net {conc#131.itm(2)} -attr vt d
+load net {conc#131.itm(3)} -attr vt d
+load net {conc#131.itm(4)} -attr vt d
+load net {conc#131.itm(5)} -attr vt d
+load net {conc#131.itm(6)} -attr vt d
+load net {conc#131.itm(7)} -attr vt d
+load net {conc#131.itm(8)} -attr vt d
+load net {conc#131.itm(9)} -attr vt d
+load net {conc#131.itm(10)} -attr vt d
+load netBundle {conc#131.itm} 11 {conc#131.itm(0)} {conc#131.itm(1)} {conc#131.itm(2)} {conc#131.itm(3)} {conc#131.itm(4)} {conc#131.itm(5)} {conc#131.itm(6)} {conc#131.itm(7)} {conc#131.itm(8)} {conc#131.itm(9)} {conc#131.itm(10)} -attr xrf 1765 -attr oid 150 -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {conc#132.itm(0)} -attr vt d
+load net {conc#132.itm(1)} -attr vt d
+load net {conc#132.itm(2)} -attr vt d
+load net {conc#132.itm(3)} -attr vt d
+load net {conc#132.itm(4)} -attr vt d
+load net {conc#132.itm(5)} -attr vt d
+load net {conc#132.itm(6)} -attr vt d
+load net {conc#132.itm(7)} -attr vt d
+load net {conc#132.itm(8)} -attr vt d
+load net {conc#132.itm(9)} -attr vt d
+load net {conc#132.itm(10)} -attr vt d
+load netBundle {conc#132.itm} 11 {conc#132.itm(0)} {conc#132.itm(1)} {conc#132.itm(2)} {conc#132.itm(3)} {conc#132.itm(4)} {conc#132.itm(5)} {conc#132.itm(6)} {conc#132.itm(7)} {conc#132.itm(8)} {conc#132.itm(9)} {conc#132.itm(10)} -attr xrf 1766 -attr oid 151 -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {conc#133.itm(0)} -attr vt d
+load net {conc#133.itm(1)} -attr vt d
+load net {conc#133.itm(2)} -attr vt d
+load net {conc#133.itm(3)} -attr vt d
+load net {conc#133.itm(4)} -attr vt d
+load net {conc#133.itm(5)} -attr vt d
+load net {conc#133.itm(6)} -attr vt d
+load net {conc#133.itm(7)} -attr vt d
+load net {conc#133.itm(8)} -attr vt d
+load net {conc#133.itm(9)} -attr vt d
+load net {conc#133.itm(10)} -attr vt d
+load net {conc#133.itm(11)} -attr vt d
+load netBundle {conc#133.itm} 12 {conc#133.itm(0)} {conc#133.itm(1)} {conc#133.itm(2)} {conc#133.itm(3)} {conc#133.itm(4)} {conc#133.itm(5)} {conc#133.itm(6)} {conc#133.itm(7)} {conc#133.itm(8)} {conc#133.itm(9)} {conc#133.itm(10)} {conc#133.itm(11)} -attr xrf 1767 -attr oid 152 -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {ACC1:slc#8.itm(0)} -attr vt d
+load net {ACC1:slc#8.itm(1)} -attr vt d
+load net {ACC1:slc#8.itm(2)} -attr vt d
+load net {ACC1:slc#8.itm(3)} -attr vt d
+load net {ACC1:slc#8.itm(4)} -attr vt d
+load net {ACC1:slc#8.itm(5)} -attr vt d
+load net {ACC1:slc#8.itm(6)} -attr vt d
+load net {ACC1:slc#8.itm(7)} -attr vt d
+load net {ACC1:slc#8.itm(8)} -attr vt d
+load net {ACC1:slc#8.itm(9)} -attr vt d
+load net {ACC1:slc#8.itm(10)} -attr vt d
+load netBundle {ACC1:slc#8.itm} 11 {ACC1:slc#8.itm(0)} {ACC1:slc#8.itm(1)} {ACC1:slc#8.itm(2)} {ACC1:slc#8.itm(3)} {ACC1:slc#8.itm(4)} {ACC1:slc#8.itm(5)} {ACC1:slc#8.itm(6)} {ACC1:slc#8.itm(7)} {ACC1:slc#8.itm(8)} {ACC1:slc#8.itm(9)} {ACC1:slc#8.itm(10)} -attr xrf 1768 -attr oid 153 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#8.itm}
+load net {ACC1:acc#52.itm(0)} -attr vt d
+load net {ACC1:acc#52.itm(1)} -attr vt d
+load net {ACC1:acc#52.itm(2)} -attr vt d
+load net {ACC1:acc#52.itm(3)} -attr vt d
+load net {ACC1:acc#52.itm(4)} -attr vt d
+load net {ACC1:acc#52.itm(5)} -attr vt d
+load net {ACC1:acc#52.itm(6)} -attr vt d
+load net {ACC1:acc#52.itm(7)} -attr vt d
+load net {ACC1:acc#52.itm(8)} -attr vt d
+load net {ACC1:acc#52.itm(9)} -attr vt d
+load net {ACC1:acc#52.itm(10)} -attr vt d
+load net {ACC1:acc#52.itm(11)} -attr vt d
+load netBundle {ACC1:acc#52.itm} 12 {ACC1:acc#52.itm(0)} {ACC1:acc#52.itm(1)} {ACC1:acc#52.itm(2)} {ACC1:acc#52.itm(3)} {ACC1:acc#52.itm(4)} {ACC1:acc#52.itm(5)} {ACC1:acc#52.itm(6)} {ACC1:acc#52.itm(7)} {ACC1:acc#52.itm(8)} {ACC1:acc#52.itm(9)} {ACC1:acc#52.itm(10)} {ACC1:acc#52.itm(11)} -attr xrf 1769 -attr oid 154 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {conc#134.itm(0)} -attr vt d
+load net {conc#134.itm(1)} -attr vt d
+load net {conc#134.itm(2)} -attr vt d
+load net {conc#134.itm(3)} -attr vt d
+load net {conc#134.itm(4)} -attr vt d
+load net {conc#134.itm(5)} -attr vt d
+load net {conc#134.itm(6)} -attr vt d
+load net {conc#134.itm(7)} -attr vt d
+load net {conc#134.itm(8)} -attr vt d
+load net {conc#134.itm(9)} -attr vt d
+load net {conc#134.itm(10)} -attr vt d
+load netBundle {conc#134.itm} 11 {conc#134.itm(0)} {conc#134.itm(1)} {conc#134.itm(2)} {conc#134.itm(3)} {conc#134.itm(4)} {conc#134.itm(5)} {conc#134.itm(6)} {conc#134.itm(7)} {conc#134.itm(8)} {conc#134.itm(9)} {conc#134.itm(10)} -attr xrf 1770 -attr oid 155 -attr vt d -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {ACC1:not#25.itm(0)} -attr vt d
+load net {ACC1:not#25.itm(1)} -attr vt d
+load net {ACC1:not#25.itm(2)} -attr vt d
+load net {ACC1:not#25.itm(3)} -attr vt d
+load net {ACC1:not#25.itm(4)} -attr vt d
+load net {ACC1:not#25.itm(5)} -attr vt d
+load net {ACC1:not#25.itm(6)} -attr vt d
+load net {ACC1:not#25.itm(7)} -attr vt d
+load net {ACC1:not#25.itm(8)} -attr vt d
+load net {ACC1:not#25.itm(9)} -attr vt d
+load netBundle {ACC1:not#25.itm} 10 {ACC1:not#25.itm(0)} {ACC1:not#25.itm(1)} {ACC1:not#25.itm(2)} {ACC1:not#25.itm(3)} {ACC1:not#25.itm(4)} {ACC1:not#25.itm(5)} {ACC1:not#25.itm(6)} {ACC1:not#25.itm(7)} {ACC1:not#25.itm(8)} {ACC1:not#25.itm(9)} -attr xrf 1771 -attr oid 156 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#25.itm}
+load net {slc(regs.regs(0).sva#1).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#1).itm} 10 {slc(regs.regs(0).sva#1).itm(0)} {slc(regs.regs(0).sva#1).itm(1)} {slc(regs.regs(0).sva#1).itm(2)} {slc(regs.regs(0).sva#1).itm(3)} {slc(regs.regs(0).sva#1).itm(4)} {slc(regs.regs(0).sva#1).itm(5)} {slc(regs.regs(0).sva#1).itm(6)} {slc(regs.regs(0).sva#1).itm(7)} {slc(regs.regs(0).sva#1).itm(8)} {slc(regs.regs(0).sva#1).itm(9)} -attr xrf 1772 -attr oid 157 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {conc#135.itm(0)} -attr vt d
+load net {conc#135.itm(1)} -attr vt d
+load net {conc#135.itm(2)} -attr vt d
+load net {conc#135.itm(3)} -attr vt d
+load net {conc#135.itm(4)} -attr vt d
+load net {conc#135.itm(5)} -attr vt d
+load net {conc#135.itm(6)} -attr vt d
+load net {conc#135.itm(7)} -attr vt d
+load net {conc#135.itm(8)} -attr vt d
+load net {conc#135.itm(9)} -attr vt d
+load net {conc#135.itm(10)} -attr vt d
+load netBundle {conc#135.itm} 11 {conc#135.itm(0)} {conc#135.itm(1)} {conc#135.itm(2)} {conc#135.itm(3)} {conc#135.itm(4)} {conc#135.itm(5)} {conc#135.itm(6)} {conc#135.itm(7)} {conc#135.itm(8)} {conc#135.itm(9)} {conc#135.itm(10)} -attr xrf 1773 -attr oid 158 -attr vt d -attr @path {/sobel/sobel:core/conc#135.itm}
+load net {ACC1:not#26.itm(0)} -attr vt d
+load net {ACC1:not#26.itm(1)} -attr vt d
+load net {ACC1:not#26.itm(2)} -attr vt d
+load net {ACC1:not#26.itm(3)} -attr vt d
+load net {ACC1:not#26.itm(4)} -attr vt d
+load net {ACC1:not#26.itm(5)} -attr vt d
+load net {ACC1:not#26.itm(6)} -attr vt d
+load net {ACC1:not#26.itm(7)} -attr vt d
+load net {ACC1:not#26.itm(8)} -attr vt d
+load net {ACC1:not#26.itm(9)} -attr vt d
+load netBundle {ACC1:not#26.itm} 10 {ACC1:not#26.itm(0)} {ACC1:not#26.itm(1)} {ACC1:not#26.itm(2)} {ACC1:not#26.itm(3)} {ACC1:not#26.itm(4)} {ACC1:not#26.itm(5)} {ACC1:not#26.itm(6)} {ACC1:not#26.itm(7)} {ACC1:not#26.itm(8)} {ACC1:not#26.itm(9)} -attr xrf 1774 -attr oid 159 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#26.itm}
+load net {slc(regs.regs(0).sva#2).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#2).itm} 10 {slc(regs.regs(0).sva#2).itm(0)} {slc(regs.regs(0).sva#2).itm(1)} {slc(regs.regs(0).sva#2).itm(2)} {slc(regs.regs(0).sva#2).itm(3)} {slc(regs.regs(0).sva#2).itm(4)} {slc(regs.regs(0).sva#2).itm(5)} {slc(regs.regs(0).sva#2).itm(6)} {slc(regs.regs(0).sva#2).itm(7)} {slc(regs.regs(0).sva#2).itm(8)} {slc(regs.regs(0).sva#2).itm(9)} -attr xrf 1775 -attr oid 160 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {conc#136.itm(0)} -attr vt d
+load net {conc#136.itm(1)} -attr vt d
+load net {conc#136.itm(2)} -attr vt d
+load net {conc#136.itm(3)} -attr vt d
+load net {conc#136.itm(4)} -attr vt d
+load net {conc#136.itm(5)} -attr vt d
+load net {conc#136.itm(6)} -attr vt d
+load net {conc#136.itm(7)} -attr vt d
+load net {conc#136.itm(8)} -attr vt d
+load net {conc#136.itm(9)} -attr vt d
+load net {conc#136.itm(10)} -attr vt d
+load net {conc#136.itm(11)} -attr vt d
+load netBundle {conc#136.itm} 12 {conc#136.itm(0)} {conc#136.itm(1)} {conc#136.itm(2)} {conc#136.itm(3)} {conc#136.itm(4)} {conc#136.itm(5)} {conc#136.itm(6)} {conc#136.itm(7)} {conc#136.itm(8)} {conc#136.itm(9)} {conc#136.itm(10)} {conc#136.itm(11)} -attr xrf 1776 -attr oid 161 -attr vt d -attr @path {/sobel/sobel:core/conc#136.itm}
+load net {ACC1:acc#58.itm(0)} -attr vt d
+load net {ACC1:acc#58.itm(1)} -attr vt d
+load net {ACC1:acc#58.itm(2)} -attr vt d
+load net {ACC1:acc#58.itm(3)} -attr vt d
+load net {ACC1:acc#58.itm(4)} -attr vt d
+load net {ACC1:acc#58.itm(5)} -attr vt d
+load net {ACC1:acc#58.itm(6)} -attr vt d
+load net {ACC1:acc#58.itm(7)} -attr vt d
+load net {ACC1:acc#58.itm(8)} -attr vt d
+load net {ACC1:acc#58.itm(9)} -attr vt d
+load net {ACC1:acc#58.itm(10)} -attr vt d
+load netBundle {ACC1:acc#58.itm} 11 {ACC1:acc#58.itm(0)} {ACC1:acc#58.itm(1)} {ACC1:acc#58.itm(2)} {ACC1:acc#58.itm(3)} {ACC1:acc#58.itm(4)} {ACC1:acc#58.itm(5)} {ACC1:acc#58.itm(6)} {ACC1:acc#58.itm(7)} {ACC1:acc#58.itm(8)} {ACC1:acc#58.itm(9)} {ACC1:acc#58.itm(10)} -attr xrf 1777 -attr oid 162 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load net {ACC1:not#27.itm(0)} -attr vt d
+load net {ACC1:not#27.itm(1)} -attr vt d
+load net {ACC1:not#27.itm(2)} -attr vt d
+load net {ACC1:not#27.itm(3)} -attr vt d
+load net {ACC1:not#27.itm(4)} -attr vt d
+load net {ACC1:not#27.itm(5)} -attr vt d
+load net {ACC1:not#27.itm(6)} -attr vt d
+load net {ACC1:not#27.itm(7)} -attr vt d
+load net {ACC1:not#27.itm(8)} -attr vt d
+load net {ACC1:not#27.itm(9)} -attr vt d
+load netBundle {ACC1:not#27.itm} 10 {ACC1:not#27.itm(0)} {ACC1:not#27.itm(1)} {ACC1:not#27.itm(2)} {ACC1:not#27.itm(3)} {ACC1:not#27.itm(4)} {ACC1:not#27.itm(5)} {ACC1:not#27.itm(6)} {ACC1:not#27.itm(7)} {ACC1:not#27.itm(8)} {ACC1:not#27.itm(9)} -attr xrf 1778 -attr oid 163 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {slc(regs.regs(0).sva#3).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#3).itm} 10 {slc(regs.regs(0).sva#3).itm(0)} {slc(regs.regs(0).sva#3).itm(1)} {slc(regs.regs(0).sva#3).itm(2)} {slc(regs.regs(0).sva#3).itm(3)} {slc(regs.regs(0).sva#3).itm(4)} {slc(regs.regs(0).sva#3).itm(5)} {slc(regs.regs(0).sva#3).itm(6)} {slc(regs.regs(0).sva#3).itm(7)} {slc(regs.regs(0).sva#3).itm(8)} {slc(regs.regs(0).sva#3).itm(9)} -attr xrf 1779 -attr oid 164 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {slc(FRAME:acc#31.sdt)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#31.sdt)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#31.sdt)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#31.sdt)#1.itm(3)} -attr vt d
+load net {slc(FRAME:acc#31.sdt)#1.itm(4)} -attr vt d
+load netBundle {slc(FRAME:acc#31.sdt)#1.itm} 5 {slc(FRAME:acc#31.sdt)#1.itm(0)} {slc(FRAME:acc#31.sdt)#1.itm(1)} {slc(FRAME:acc#31.sdt)#1.itm(2)} {slc(FRAME:acc#31.sdt)#1.itm(3)} {slc(FRAME:acc#31.sdt)#1.itm(4)} -attr xrf 1780 -attr oid 165 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#31.sdt)#1.itm}
+load net {FRAME:acc#30.itm(0)} -attr vt d
+load net {FRAME:acc#30.itm(1)} -attr vt d
+load net {FRAME:acc#30.itm(2)} -attr vt d
+load net {FRAME:acc#30.itm(3)} -attr vt d
+load net {FRAME:acc#30.itm(4)} -attr vt d
+load netBundle {FRAME:acc#30.itm} 5 {FRAME:acc#30.itm(0)} {FRAME:acc#30.itm(1)} {FRAME:acc#30.itm(2)} {FRAME:acc#30.itm(3)} {FRAME:acc#30.itm(4)} -attr xrf 1781 -attr oid 166 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#28.itm(0)} -attr vt d
+load net {FRAME:acc#28.itm(1)} -attr vt d
+load net {FRAME:acc#28.itm(2)} -attr vt d
+load net {FRAME:acc#28.itm(3)} -attr vt d
+load netBundle {FRAME:acc#28.itm} 4 {FRAME:acc#28.itm(0)} {FRAME:acc#28.itm(1)} {FRAME:acc#28.itm(2)} {FRAME:acc#28.itm(3)} -attr xrf 1782 -attr oid 167 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {slc(ACC1:acc#43.psp.sva)#7.itm(0)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#7.itm(1)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#43.psp.sva)#7.itm} 3 {slc(ACC1:acc#43.psp.sva)#7.itm(0)} {slc(ACC1:acc#43.psp.sva)#7.itm(1)} {slc(ACC1:acc#43.psp.sva)#7.itm(2)} -attr xrf 1783 -attr oid 168 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#7.itm}
+load net {FRAME:not#35.itm(0)} -attr vt d
+load net {FRAME:not#35.itm(1)} -attr vt d
+load net {FRAME:not#35.itm(2)} -attr vt d
+load netBundle {FRAME:not#35.itm} 3 {FRAME:not#35.itm(0)} {FRAME:not#35.itm(1)} {FRAME:not#35.itm(2)} -attr xrf 1784 -attr oid 169 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#35.itm}
+load net {slc(ACC1:acc#43.psp.sva)#8.itm(0)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#8.itm(1)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#8.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#43.psp.sva)#8.itm} 3 {slc(ACC1:acc#43.psp.sva)#8.itm(0)} {slc(ACC1:acc#43.psp.sva)#8.itm(1)} {slc(ACC1:acc#43.psp.sva)#8.itm(2)} -attr xrf 1785 -attr oid 170 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#8.itm}
+load net {FRAME:conc#36.itm(0)} -attr vt d
+load net {FRAME:conc#36.itm(1)} -attr vt d
+load net {FRAME:conc#36.itm(2)} -attr vt d
+load net {FRAME:conc#36.itm(3)} -attr vt d
+load netBundle {FRAME:conc#36.itm} 4 {FRAME:conc#36.itm(0)} {FRAME:conc#36.itm(1)} {FRAME:conc#36.itm(2)} {FRAME:conc#36.itm(3)} -attr xrf 1786 -attr oid 171 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:not#42.itm(0)} -attr vt d
+load net {FRAME:not#42.itm(1)} -attr vt d
+load net {FRAME:not#42.itm(2)} -attr vt d
+load netBundle {FRAME:not#42.itm} 3 {FRAME:not#42.itm(0)} {FRAME:not#42.itm(1)} {FRAME:not#42.itm(2)} -attr xrf 1787 -attr oid 172 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#42.itm}
+load net {slc(ACC1:acc#43.psp.sva)#9.itm(0)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#9.itm(1)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#43.psp.sva)#9.itm} 3 {slc(ACC1:acc#43.psp.sva)#9.itm(0)} {slc(ACC1:acc#43.psp.sva)#9.itm(1)} {slc(ACC1:acc#43.psp.sva)#9.itm(2)} -attr xrf 1788 -attr oid 173 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#9.itm}
+load net {FRAME:acc#29.itm(0)} -attr vt d
+load net {FRAME:acc#29.itm(1)} -attr vt d
+load net {FRAME:acc#29.itm(2)} -attr vt d
+load net {FRAME:acc#29.itm(3)} -attr vt d
+load netBundle {FRAME:acc#29.itm} 4 {FRAME:acc#29.itm(0)} {FRAME:acc#29.itm(1)} {FRAME:acc#29.itm(2)} {FRAME:acc#29.itm(3)} -attr xrf 1789 -attr oid 174 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {conc#137.itm(0)} -attr vt d
+load net {conc#137.itm(1)} -attr vt d
+load net {conc#137.itm(2)} -attr vt d
+load netBundle {conc#137.itm} 3 {conc#137.itm(0)} {conc#137.itm(1)} {conc#137.itm(2)} -attr xrf 1790 -attr oid 175 -attr vt d -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {slc(ACC1:acc#43.psp.sva)#10.itm(0)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#10.itm(1)} -attr vt d
+load net {slc(ACC1:acc#43.psp.sva)#10.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#43.psp.sva)#10.itm} 3 {slc(ACC1:acc#43.psp.sva)#10.itm(0)} {slc(ACC1:acc#43.psp.sva)#10.itm(1)} {slc(ACC1:acc#43.psp.sva)#10.itm(2)} -attr xrf 1791 -attr oid 176 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#10.itm}
+load net {ACC1:slc#7.itm(0)} -attr vt d
+load net {ACC1:slc#7.itm(1)} -attr vt d
+load net {ACC1:slc#7.itm(2)} -attr vt d
+load net {ACC1:slc#7.itm(3)} -attr vt d
+load net {ACC1:slc#7.itm(4)} -attr vt d
+load net {ACC1:slc#7.itm(5)} -attr vt d
+load net {ACC1:slc#7.itm(6)} -attr vt d
+load net {ACC1:slc#7.itm(7)} -attr vt d
+load net {ACC1:slc#7.itm(8)} -attr vt d
+load net {ACC1:slc#7.itm(9)} -attr vt d
+load net {ACC1:slc#7.itm(10)} -attr vt d
+load net {ACC1:slc#7.itm(11)} -attr vt d
+load netBundle {ACC1:slc#7.itm} 12 {ACC1:slc#7.itm(0)} {ACC1:slc#7.itm(1)} {ACC1:slc#7.itm(2)} {ACC1:slc#7.itm(3)} {ACC1:slc#7.itm(4)} {ACC1:slc#7.itm(5)} {ACC1:slc#7.itm(6)} {ACC1:slc#7.itm(7)} {ACC1:slc#7.itm(8)} {ACC1:slc#7.itm(9)} {ACC1:slc#7.itm(10)} {ACC1:slc#7.itm(11)} -attr xrf 1792 -attr oid 177 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#51.itm(0)} -attr vt d
+load net {ACC1:acc#51.itm(1)} -attr vt d
+load net {ACC1:acc#51.itm(2)} -attr vt d
+load net {ACC1:acc#51.itm(3)} -attr vt d
+load net {ACC1:acc#51.itm(4)} -attr vt d
+load net {ACC1:acc#51.itm(5)} -attr vt d
+load net {ACC1:acc#51.itm(6)} -attr vt d
+load net {ACC1:acc#51.itm(7)} -attr vt d
+load net {ACC1:acc#51.itm(8)} -attr vt d
+load net {ACC1:acc#51.itm(9)} -attr vt d
+load net {ACC1:acc#51.itm(10)} -attr vt d
+load net {ACC1:acc#51.itm(11)} -attr vt d
+load net {ACC1:acc#51.itm(12)} -attr vt d
+load netBundle {ACC1:acc#51.itm} 13 {ACC1:acc#51.itm(0)} {ACC1:acc#51.itm(1)} {ACC1:acc#51.itm(2)} {ACC1:acc#51.itm(3)} {ACC1:acc#51.itm(4)} {ACC1:acc#51.itm(5)} {ACC1:acc#51.itm(6)} {ACC1:acc#51.itm(7)} {ACC1:acc#51.itm(8)} {ACC1:acc#51.itm(9)} {ACC1:acc#51.itm(10)} {ACC1:acc#51.itm(11)} {ACC1:acc#51.itm(12)} -attr xrf 1793 -attr oid 178 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {conc#138.itm(0)} -attr vt d
+load net {conc#138.itm(1)} -attr vt d
+load net {conc#138.itm(2)} -attr vt d
+load net {conc#138.itm(3)} -attr vt d
+load net {conc#138.itm(4)} -attr vt d
+load net {conc#138.itm(5)} -attr vt d
+load net {conc#138.itm(6)} -attr vt d
+load net {conc#138.itm(7)} -attr vt d
+load net {conc#138.itm(8)} -attr vt d
+load net {conc#138.itm(9)} -attr vt d
+load net {conc#138.itm(10)} -attr vt d
+load net {conc#138.itm(11)} -attr vt d
+load netBundle {conc#138.itm} 12 {conc#138.itm(0)} {conc#138.itm(1)} {conc#138.itm(2)} {conc#138.itm(3)} {conc#138.itm(4)} {conc#138.itm(5)} {conc#138.itm(6)} {conc#138.itm(7)} {conc#138.itm(8)} {conc#138.itm(9)} {conc#138.itm(10)} {conc#138.itm(11)} -attr xrf 1794 -attr oid 179 -attr vt d -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {ACC1:slc#5.itm(0)} -attr vt d
+load net {ACC1:slc#5.itm(1)} -attr vt d
+load net {ACC1:slc#5.itm(2)} -attr vt d
+load net {ACC1:slc#5.itm(3)} -attr vt d
+load net {ACC1:slc#5.itm(4)} -attr vt d
+load net {ACC1:slc#5.itm(5)} -attr vt d
+load net {ACC1:slc#5.itm(6)} -attr vt d
+load net {ACC1:slc#5.itm(7)} -attr vt d
+load net {ACC1:slc#5.itm(8)} -attr vt d
+load net {ACC1:slc#5.itm(9)} -attr vt d
+load net {ACC1:slc#5.itm(10)} -attr vt d
+load netBundle {ACC1:slc#5.itm} 11 {ACC1:slc#5.itm(0)} {ACC1:slc#5.itm(1)} {ACC1:slc#5.itm(2)} {ACC1:slc#5.itm(3)} {ACC1:slc#5.itm(4)} {ACC1:slc#5.itm(5)} {ACC1:slc#5.itm(6)} {ACC1:slc#5.itm(7)} {ACC1:slc#5.itm(8)} {ACC1:slc#5.itm(9)} {ACC1:slc#5.itm(10)} -attr xrf 1795 -attr oid 180 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#5.itm}
+load net {ACC1:acc#49.itm(0)} -attr vt d
+load net {ACC1:acc#49.itm(1)} -attr vt d
+load net {ACC1:acc#49.itm(2)} -attr vt d
+load net {ACC1:acc#49.itm(3)} -attr vt d
+load net {ACC1:acc#49.itm(4)} -attr vt d
+load net {ACC1:acc#49.itm(5)} -attr vt d
+load net {ACC1:acc#49.itm(6)} -attr vt d
+load net {ACC1:acc#49.itm(7)} -attr vt d
+load net {ACC1:acc#49.itm(8)} -attr vt d
+load net {ACC1:acc#49.itm(9)} -attr vt d
+load net {ACC1:acc#49.itm(10)} -attr vt d
+load net {ACC1:acc#49.itm(11)} -attr vt d
+load netBundle {ACC1:acc#49.itm} 12 {ACC1:acc#49.itm(0)} {ACC1:acc#49.itm(1)} {ACC1:acc#49.itm(2)} {ACC1:acc#49.itm(3)} {ACC1:acc#49.itm(4)} {ACC1:acc#49.itm(5)} {ACC1:acc#49.itm(6)} {ACC1:acc#49.itm(7)} {ACC1:acc#49.itm(8)} {ACC1:acc#49.itm(9)} {ACC1:acc#49.itm(10)} {ACC1:acc#49.itm(11)} -attr xrf 1796 -attr oid 181 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {conc#139.itm(0)} -attr vt d
+load net {conc#139.itm(1)} -attr vt d
+load net {conc#139.itm(2)} -attr vt d
+load net {conc#139.itm(3)} -attr vt d
+load net {conc#139.itm(4)} -attr vt d
+load net {conc#139.itm(5)} -attr vt d
+load net {conc#139.itm(6)} -attr vt d
+load net {conc#139.itm(7)} -attr vt d
+load net {conc#139.itm(8)} -attr vt d
+load net {conc#139.itm(9)} -attr vt d
+load net {conc#139.itm(10)} -attr vt d
+load netBundle {conc#139.itm} 11 {conc#139.itm(0)} {conc#139.itm(1)} {conc#139.itm(2)} {conc#139.itm(3)} {conc#139.itm(4)} {conc#139.itm(5)} {conc#139.itm(6)} {conc#139.itm(7)} {conc#139.itm(8)} {conc#139.itm(9)} {conc#139.itm(10)} -attr xrf 1797 -attr oid 182 -attr vt d -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {conc#140.itm(0)} -attr vt d
+load net {conc#140.itm(1)} -attr vt d
+load net {conc#140.itm(2)} -attr vt d
+load net {conc#140.itm(3)} -attr vt d
+load net {conc#140.itm(4)} -attr vt d
+load net {conc#140.itm(5)} -attr vt d
+load net {conc#140.itm(6)} -attr vt d
+load net {conc#140.itm(7)} -attr vt d
+load net {conc#140.itm(8)} -attr vt d
+load net {conc#140.itm(9)} -attr vt d
+load net {conc#140.itm(10)} -attr vt d
+load netBundle {conc#140.itm} 11 {conc#140.itm(0)} {conc#140.itm(1)} {conc#140.itm(2)} {conc#140.itm(3)} {conc#140.itm(4)} {conc#140.itm(5)} {conc#140.itm(6)} {conc#140.itm(7)} {conc#140.itm(8)} {conc#140.itm(9)} {conc#140.itm(10)} -attr xrf 1798 -attr oid 183 -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {conc#141.itm(0)} -attr vt d
+load net {conc#141.itm(1)} -attr vt d
+load net {conc#141.itm(2)} -attr vt d
+load net {conc#141.itm(3)} -attr vt d
+load net {conc#141.itm(4)} -attr vt d
+load net {conc#141.itm(5)} -attr vt d
+load net {conc#141.itm(6)} -attr vt d
+load net {conc#141.itm(7)} -attr vt d
+load net {conc#141.itm(8)} -attr vt d
+load net {conc#141.itm(9)} -attr vt d
+load net {conc#141.itm(10)} -attr vt d
+load net {conc#141.itm(11)} -attr vt d
+load netBundle {conc#141.itm} 12 {conc#141.itm(0)} {conc#141.itm(1)} {conc#141.itm(2)} {conc#141.itm(3)} {conc#141.itm(4)} {conc#141.itm(5)} {conc#141.itm(6)} {conc#141.itm(7)} {conc#141.itm(8)} {conc#141.itm(9)} {conc#141.itm(10)} {conc#141.itm(11)} -attr xrf 1799 -attr oid 184 -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC1:slc#4.itm(0)} -attr vt d
+load net {ACC1:slc#4.itm(1)} -attr vt d
+load net {ACC1:slc#4.itm(2)} -attr vt d
+load net {ACC1:slc#4.itm(3)} -attr vt d
+load net {ACC1:slc#4.itm(4)} -attr vt d
+load net {ACC1:slc#4.itm(5)} -attr vt d
+load net {ACC1:slc#4.itm(6)} -attr vt d
+load net {ACC1:slc#4.itm(7)} -attr vt d
+load net {ACC1:slc#4.itm(8)} -attr vt d
+load net {ACC1:slc#4.itm(9)} -attr vt d
+load net {ACC1:slc#4.itm(10)} -attr vt d
+load netBundle {ACC1:slc#4.itm} 11 {ACC1:slc#4.itm(0)} {ACC1:slc#4.itm(1)} {ACC1:slc#4.itm(2)} {ACC1:slc#4.itm(3)} {ACC1:slc#4.itm(4)} {ACC1:slc#4.itm(5)} {ACC1:slc#4.itm(6)} {ACC1:slc#4.itm(7)} {ACC1:slc#4.itm(8)} {ACC1:slc#4.itm(9)} {ACC1:slc#4.itm(10)} -attr xrf 1800 -attr oid 185 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#4.itm}
+load net {ACC1:acc#48.itm(0)} -attr vt d
+load net {ACC1:acc#48.itm(1)} -attr vt d
+load net {ACC1:acc#48.itm(2)} -attr vt d
+load net {ACC1:acc#48.itm(3)} -attr vt d
+load net {ACC1:acc#48.itm(4)} -attr vt d
+load net {ACC1:acc#48.itm(5)} -attr vt d
+load net {ACC1:acc#48.itm(6)} -attr vt d
+load net {ACC1:acc#48.itm(7)} -attr vt d
+load net {ACC1:acc#48.itm(8)} -attr vt d
+load net {ACC1:acc#48.itm(9)} -attr vt d
+load net {ACC1:acc#48.itm(10)} -attr vt d
+load net {ACC1:acc#48.itm(11)} -attr vt d
+load netBundle {ACC1:acc#48.itm} 12 {ACC1:acc#48.itm(0)} {ACC1:acc#48.itm(1)} {ACC1:acc#48.itm(2)} {ACC1:acc#48.itm(3)} {ACC1:acc#48.itm(4)} {ACC1:acc#48.itm(5)} {ACC1:acc#48.itm(6)} {ACC1:acc#48.itm(7)} {ACC1:acc#48.itm(8)} {ACC1:acc#48.itm(9)} {ACC1:acc#48.itm(10)} {ACC1:acc#48.itm(11)} -attr xrf 1801 -attr oid 186 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {conc#142.itm(0)} -attr vt d
+load net {conc#142.itm(1)} -attr vt d
+load net {conc#142.itm(2)} -attr vt d
+load net {conc#142.itm(3)} -attr vt d
+load net {conc#142.itm(4)} -attr vt d
+load net {conc#142.itm(5)} -attr vt d
+load net {conc#142.itm(6)} -attr vt d
+load net {conc#142.itm(7)} -attr vt d
+load net {conc#142.itm(8)} -attr vt d
+load net {conc#142.itm(9)} -attr vt d
+load net {conc#142.itm(10)} -attr vt d
+load netBundle {conc#142.itm} 11 {conc#142.itm(0)} {conc#142.itm(1)} {conc#142.itm(2)} {conc#142.itm(3)} {conc#142.itm(4)} {conc#142.itm(5)} {conc#142.itm(6)} {conc#142.itm(7)} {conc#142.itm(8)} {conc#142.itm(9)} {conc#142.itm(10)} -attr xrf 1802 -attr oid 187 -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {ACC1:not#22.itm(0)} -attr vt d
+load net {ACC1:not#22.itm(1)} -attr vt d
+load net {ACC1:not#22.itm(2)} -attr vt d
+load net {ACC1:not#22.itm(3)} -attr vt d
+load net {ACC1:not#22.itm(4)} -attr vt d
+load net {ACC1:not#22.itm(5)} -attr vt d
+load net {ACC1:not#22.itm(6)} -attr vt d
+load net {ACC1:not#22.itm(7)} -attr vt d
+load net {ACC1:not#22.itm(8)} -attr vt d
+load net {ACC1:not#22.itm(9)} -attr vt d
+load netBundle {ACC1:not#22.itm} 10 {ACC1:not#22.itm(0)} {ACC1:not#22.itm(1)} {ACC1:not#22.itm(2)} {ACC1:not#22.itm(3)} {ACC1:not#22.itm(4)} {ACC1:not#22.itm(5)} {ACC1:not#22.itm(6)} {ACC1:not#22.itm(7)} {ACC1:not#22.itm(8)} {ACC1:not#22.itm(9)} -attr xrf 1803 -attr oid 188 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#22.itm}
+load net {slc(regs.regs(0).sva#4).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#4).itm} 10 {slc(regs.regs(0).sva#4).itm(0)} {slc(regs.regs(0).sva#4).itm(1)} {slc(regs.regs(0).sva#4).itm(2)} {slc(regs.regs(0).sva#4).itm(3)} {slc(regs.regs(0).sva#4).itm(4)} {slc(regs.regs(0).sva#4).itm(5)} {slc(regs.regs(0).sva#4).itm(6)} {slc(regs.regs(0).sva#4).itm(7)} {slc(regs.regs(0).sva#4).itm(8)} {slc(regs.regs(0).sva#4).itm(9)} -attr xrf 1804 -attr oid 189 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {conc#143.itm(0)} -attr vt d
+load net {conc#143.itm(1)} -attr vt d
+load net {conc#143.itm(2)} -attr vt d
+load net {conc#143.itm(3)} -attr vt d
+load net {conc#143.itm(4)} -attr vt d
+load net {conc#143.itm(5)} -attr vt d
+load net {conc#143.itm(6)} -attr vt d
+load net {conc#143.itm(7)} -attr vt d
+load net {conc#143.itm(8)} -attr vt d
+load net {conc#143.itm(9)} -attr vt d
+load net {conc#143.itm(10)} -attr vt d
+load netBundle {conc#143.itm} 11 {conc#143.itm(0)} {conc#143.itm(1)} {conc#143.itm(2)} {conc#143.itm(3)} {conc#143.itm(4)} {conc#143.itm(5)} {conc#143.itm(6)} {conc#143.itm(7)} {conc#143.itm(8)} {conc#143.itm(9)} {conc#143.itm(10)} -attr xrf 1805 -attr oid 190 -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#23.itm(0)} -attr vt d
+load net {ACC1:not#23.itm(1)} -attr vt d
+load net {ACC1:not#23.itm(2)} -attr vt d
+load net {ACC1:not#23.itm(3)} -attr vt d
+load net {ACC1:not#23.itm(4)} -attr vt d
+load net {ACC1:not#23.itm(5)} -attr vt d
+load net {ACC1:not#23.itm(6)} -attr vt d
+load net {ACC1:not#23.itm(7)} -attr vt d
+load net {ACC1:not#23.itm(8)} -attr vt d
+load net {ACC1:not#23.itm(9)} -attr vt d
+load netBundle {ACC1:not#23.itm} 10 {ACC1:not#23.itm(0)} {ACC1:not#23.itm(1)} {ACC1:not#23.itm(2)} {ACC1:not#23.itm(3)} {ACC1:not#23.itm(4)} {ACC1:not#23.itm(5)} {ACC1:not#23.itm(6)} {ACC1:not#23.itm(7)} {ACC1:not#23.itm(8)} {ACC1:not#23.itm(9)} -attr xrf 1806 -attr oid 191 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#23.itm}
+load net {slc(regs.regs(0).sva#5).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#5).itm} 10 {slc(regs.regs(0).sva#5).itm(0)} {slc(regs.regs(0).sva#5).itm(1)} {slc(regs.regs(0).sva#5).itm(2)} {slc(regs.regs(0).sva#5).itm(3)} {slc(regs.regs(0).sva#5).itm(4)} {slc(regs.regs(0).sva#5).itm(5)} {slc(regs.regs(0).sva#5).itm(6)} {slc(regs.regs(0).sva#5).itm(7)} {slc(regs.regs(0).sva#5).itm(8)} {slc(regs.regs(0).sva#5).itm(9)} -attr xrf 1807 -attr oid 192 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {conc#144.itm(0)} -attr vt d
+load net {conc#144.itm(1)} -attr vt d
+load net {conc#144.itm(2)} -attr vt d
+load net {conc#144.itm(3)} -attr vt d
+load net {conc#144.itm(4)} -attr vt d
+load net {conc#144.itm(5)} -attr vt d
+load net {conc#144.itm(6)} -attr vt d
+load net {conc#144.itm(7)} -attr vt d
+load net {conc#144.itm(8)} -attr vt d
+load net {conc#144.itm(9)} -attr vt d
+load net {conc#144.itm(10)} -attr vt d
+load net {conc#144.itm(11)} -attr vt d
+load netBundle {conc#144.itm} 12 {conc#144.itm(0)} {conc#144.itm(1)} {conc#144.itm(2)} {conc#144.itm(3)} {conc#144.itm(4)} {conc#144.itm(5)} {conc#144.itm(6)} {conc#144.itm(7)} {conc#144.itm(8)} {conc#144.itm(9)} {conc#144.itm(10)} {conc#144.itm(11)} -attr xrf 1808 -attr oid 193 -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC1:acc#57.itm(0)} -attr vt d
+load net {ACC1:acc#57.itm(1)} -attr vt d
+load net {ACC1:acc#57.itm(2)} -attr vt d
+load net {ACC1:acc#57.itm(3)} -attr vt d
+load net {ACC1:acc#57.itm(4)} -attr vt d
+load net {ACC1:acc#57.itm(5)} -attr vt d
+load net {ACC1:acc#57.itm(6)} -attr vt d
+load net {ACC1:acc#57.itm(7)} -attr vt d
+load net {ACC1:acc#57.itm(8)} -attr vt d
+load net {ACC1:acc#57.itm(9)} -attr vt d
+load net {ACC1:acc#57.itm(10)} -attr vt d
+load netBundle {ACC1:acc#57.itm} 11 {ACC1:acc#57.itm(0)} {ACC1:acc#57.itm(1)} {ACC1:acc#57.itm(2)} {ACC1:acc#57.itm(3)} {ACC1:acc#57.itm(4)} {ACC1:acc#57.itm(5)} {ACC1:acc#57.itm(6)} {ACC1:acc#57.itm(7)} {ACC1:acc#57.itm(8)} {ACC1:acc#57.itm(9)} {ACC1:acc#57.itm(10)} -attr xrf 1809 -attr oid 194 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#57.itm}
+load net {ACC1:not#24.itm(0)} -attr vt d
+load net {ACC1:not#24.itm(1)} -attr vt d
+load net {ACC1:not#24.itm(2)} -attr vt d
+load net {ACC1:not#24.itm(3)} -attr vt d
+load net {ACC1:not#24.itm(4)} -attr vt d
+load net {ACC1:not#24.itm(5)} -attr vt d
+load net {ACC1:not#24.itm(6)} -attr vt d
+load net {ACC1:not#24.itm(7)} -attr vt d
+load net {ACC1:not#24.itm(8)} -attr vt d
+load net {ACC1:not#24.itm(9)} -attr vt d
+load netBundle {ACC1:not#24.itm} 10 {ACC1:not#24.itm(0)} {ACC1:not#24.itm(1)} {ACC1:not#24.itm(2)} {ACC1:not#24.itm(3)} {ACC1:not#24.itm(4)} {ACC1:not#24.itm(5)} {ACC1:not#24.itm(6)} {ACC1:not#24.itm(7)} {ACC1:not#24.itm(8)} {ACC1:not#24.itm(9)} -attr xrf 1810 -attr oid 195 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {slc(regs.regs(0).sva#6).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#6).itm} 10 {slc(regs.regs(0).sva#6).itm(0)} {slc(regs.regs(0).sva#6).itm(1)} {slc(regs.regs(0).sva#6).itm(2)} {slc(regs.regs(0).sva#6).itm(3)} {slc(regs.regs(0).sva#6).itm(4)} {slc(regs.regs(0).sva#6).itm(5)} {slc(regs.regs(0).sva#6).itm(6)} {slc(regs.regs(0).sva#6).itm(7)} {slc(regs.regs(0).sva#6).itm(8)} {slc(regs.regs(0).sva#6).itm(9)} -attr xrf 1811 -attr oid 196 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {slc(FRAME:acc#18.sdt)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#18.sdt)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#18.sdt)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#18.sdt)#1.itm(3)} -attr vt d
+load net {slc(FRAME:acc#18.sdt)#1.itm(4)} -attr vt d
+load netBundle {slc(FRAME:acc#18.sdt)#1.itm} 5 {slc(FRAME:acc#18.sdt)#1.itm(0)} {slc(FRAME:acc#18.sdt)#1.itm(1)} {slc(FRAME:acc#18.sdt)#1.itm(2)} {slc(FRAME:acc#18.sdt)#1.itm(3)} {slc(FRAME:acc#18.sdt)#1.itm(4)} -attr xrf 1812 -attr oid 197 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#18.sdt)#1.itm}
+load net {FRAME:acc#17.itm(0)} -attr vt d
+load net {FRAME:acc#17.itm(1)} -attr vt d
+load net {FRAME:acc#17.itm(2)} -attr vt d
+load net {FRAME:acc#17.itm(3)} -attr vt d
+load net {FRAME:acc#17.itm(4)} -attr vt d
+load netBundle {FRAME:acc#17.itm} 5 {FRAME:acc#17.itm(0)} {FRAME:acc#17.itm(1)} {FRAME:acc#17.itm(2)} {FRAME:acc#17.itm(3)} {FRAME:acc#17.itm(4)} -attr xrf 1813 -attr oid 198 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#15.itm(0)} -attr vt d
+load net {FRAME:acc#15.itm(1)} -attr vt d
+load net {FRAME:acc#15.itm(2)} -attr vt d
+load net {FRAME:acc#15.itm(3)} -attr vt d
+load netBundle {FRAME:acc#15.itm} 4 {FRAME:acc#15.itm(0)} {FRAME:acc#15.itm(1)} {FRAME:acc#15.itm(2)} {FRAME:acc#15.itm(3)} -attr xrf 1814 -attr oid 199 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {slc(ACC1:acc#42.psp.sva)#7.itm(0)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#7.itm(1)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#42.psp.sva)#7.itm} 3 {slc(ACC1:acc#42.psp.sva)#7.itm(0)} {slc(ACC1:acc#42.psp.sva)#7.itm(1)} {slc(ACC1:acc#42.psp.sva)#7.itm(2)} -attr xrf 1815 -attr oid 200 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm}
+load net {FRAME:not#33.itm(0)} -attr vt d
+load net {FRAME:not#33.itm(1)} -attr vt d
+load net {FRAME:not#33.itm(2)} -attr vt d
+load netBundle {FRAME:not#33.itm} 3 {FRAME:not#33.itm(0)} {FRAME:not#33.itm(1)} {FRAME:not#33.itm(2)} -attr xrf 1816 -attr oid 201 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#33.itm}
+load net {slc(ACC1:acc#42.psp.sva)#8.itm(0)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#8.itm(1)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#8.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#42.psp.sva)#8.itm} 3 {slc(ACC1:acc#42.psp.sva)#8.itm(0)} {slc(ACC1:acc#42.psp.sva)#8.itm(1)} {slc(ACC1:acc#42.psp.sva)#8.itm(2)} -attr xrf 1817 -attr oid 202 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#8.itm}
+load net {FRAME:conc#35.itm(0)} -attr vt d
+load net {FRAME:conc#35.itm(1)} -attr vt d
+load net {FRAME:conc#35.itm(2)} -attr vt d
+load net {FRAME:conc#35.itm(3)} -attr vt d
+load netBundle {FRAME:conc#35.itm} 4 {FRAME:conc#35.itm(0)} {FRAME:conc#35.itm(1)} {FRAME:conc#35.itm(2)} {FRAME:conc#35.itm(3)} -attr xrf 1818 -attr oid 203 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#35.itm}
+load net {FRAME:not#41.itm(0)} -attr vt d
+load net {FRAME:not#41.itm(1)} -attr vt d
+load net {FRAME:not#41.itm(2)} -attr vt d
+load netBundle {FRAME:not#41.itm} 3 {FRAME:not#41.itm(0)} {FRAME:not#41.itm(1)} {FRAME:not#41.itm(2)} -attr xrf 1819 -attr oid 204 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#41.itm}
+load net {slc(ACC1:acc#42.psp.sva)#9.itm(0)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#9.itm(1)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#42.psp.sva)#9.itm} 3 {slc(ACC1:acc#42.psp.sva)#9.itm(0)} {slc(ACC1:acc#42.psp.sva)#9.itm(1)} {slc(ACC1:acc#42.psp.sva)#9.itm(2)} -attr xrf 1820 -attr oid 205 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#9.itm}
+load net {FRAME:acc#16.itm(0)} -attr vt d
+load net {FRAME:acc#16.itm(1)} -attr vt d
+load net {FRAME:acc#16.itm(2)} -attr vt d
+load net {FRAME:acc#16.itm(3)} -attr vt d
+load netBundle {FRAME:acc#16.itm} 4 {FRAME:acc#16.itm(0)} {FRAME:acc#16.itm(1)} {FRAME:acc#16.itm(2)} {FRAME:acc#16.itm(3)} -attr xrf 1821 -attr oid 206 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {conc#145.itm(0)} -attr vt d
+load net {conc#145.itm(1)} -attr vt d
+load net {conc#145.itm(2)} -attr vt d
+load netBundle {conc#145.itm} 3 {conc#145.itm(0)} {conc#145.itm(1)} {conc#145.itm(2)} -attr xrf 1822 -attr oid 207 -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {slc(ACC1:acc#42.psp.sva)#10.itm(0)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#10.itm(1)} -attr vt d
+load net {slc(ACC1:acc#42.psp.sva)#10.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#42.psp.sva)#10.itm} 3 {slc(ACC1:acc#42.psp.sva)#10.itm(0)} {slc(ACC1:acc#42.psp.sva)#10.itm(1)} {slc(ACC1:acc#42.psp.sva)#10.itm(2)} -attr xrf 1823 -attr oid 208 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#10.itm}
+load net {FRAME:or.itm(0)} -attr vt d
+load net {FRAME:or.itm(1)} -attr vt d
+load net {FRAME:or.itm(2)} -attr vt d
+load net {FRAME:or.itm(3)} -attr vt d
+load net {FRAME:or.itm(4)} -attr vt d
+load net {FRAME:or.itm(5)} -attr vt d
+load net {FRAME:or.itm(6)} -attr vt d
+load net {FRAME:or.itm(7)} -attr vt d
+load net {FRAME:or.itm(8)} -attr vt d
+load net {FRAME:or.itm(9)} -attr vt d
+load netBundle {FRAME:or.itm} 10 {FRAME:or.itm(0)} {FRAME:or.itm(1)} {FRAME:or.itm(2)} {FRAME:or.itm(3)} {FRAME:or.itm(4)} {FRAME:or.itm(5)} {FRAME:or.itm(6)} {FRAME:or.itm(7)} {FRAME:or.itm(8)} {FRAME:or.itm(9)} -attr xrf 1824 -attr oid 209 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:acc#8.itm(0)} -attr vt d
+load net {FRAME:acc#8.itm(1)} -attr vt d
+load net {FRAME:acc#8.itm(2)} -attr vt d
+load net {FRAME:acc#8.itm(3)} -attr vt d
+load net {FRAME:acc#8.itm(4)} -attr vt d
+load net {FRAME:acc#8.itm(5)} -attr vt d
+load net {FRAME:acc#8.itm(6)} -attr vt d
+load net {FRAME:acc#8.itm(7)} -attr vt d
+load net {FRAME:acc#8.itm(8)} -attr vt d
+load net {FRAME:acc#8.itm(9)} -attr vt d
+load netBundle {FRAME:acc#8.itm} 10 {FRAME:acc#8.itm(0)} {FRAME:acc#8.itm(1)} {FRAME:acc#8.itm(2)} {FRAME:acc#8.itm(3)} {FRAME:acc#8.itm(4)} {FRAME:acc#8.itm(5)} {FRAME:acc#8.itm(6)} {FRAME:acc#8.itm(7)} {FRAME:acc#8.itm(8)} {FRAME:acc#8.itm(9)} -attr xrf 1825 -attr oid 210 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#44.itm(0)} -attr vt d
+load net {FRAME:acc#44.itm(1)} -attr vt d
+load net {FRAME:acc#44.itm(2)} -attr vt d
+load net {FRAME:acc#44.itm(3)} -attr vt d
+load net {FRAME:acc#44.itm(4)} -attr vt d
+load net {FRAME:acc#44.itm(5)} -attr vt d
+load net {FRAME:acc#44.itm(6)} -attr vt d
+load net {FRAME:acc#44.itm(7)} -attr vt d
+load net {FRAME:acc#44.itm(8)} -attr vt d
+load net {FRAME:acc#44.itm(9)} -attr vt d
+load netBundle {FRAME:acc#44.itm} 10 {FRAME:acc#44.itm(0)} {FRAME:acc#44.itm(1)} {FRAME:acc#44.itm(2)} {FRAME:acc#44.itm(3)} {FRAME:acc#44.itm(4)} {FRAME:acc#44.itm(5)} {FRAME:acc#44.itm(6)} {FRAME:acc#44.itm(7)} {FRAME:acc#44.itm(8)} {FRAME:acc#44.itm(9)} -attr xrf 1826 -attr oid 211 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:mul.itm(0)} -attr vt d
+load net {FRAME:mul.itm(1)} -attr vt d
+load net {FRAME:mul.itm(2)} -attr vt d
+load net {FRAME:mul.itm(3)} -attr vt d
+load net {FRAME:mul.itm(4)} -attr vt d
+load net {FRAME:mul.itm(5)} -attr vt d
+load net {FRAME:mul.itm(6)} -attr vt d
+load net {FRAME:mul.itm(7)} -attr vt d
+load net {FRAME:mul.itm(8)} -attr vt d
+load net {FRAME:mul.itm(9)} -attr vt d
+load netBundle {FRAME:mul.itm} 10 {FRAME:mul.itm(0)} {FRAME:mul.itm(1)} {FRAME:mul.itm(2)} {FRAME:mul.itm(3)} {FRAME:mul.itm(4)} {FRAME:mul.itm(5)} {FRAME:mul.itm(6)} {FRAME:mul.itm(7)} {FRAME:mul.itm(8)} {FRAME:mul.itm(9)} -attr xrf 1827 -attr oid 212 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:exs#16.itm(0)} -attr vt d
+load net {FRAME:exs#16.itm(1)} -attr vt d
+load netBundle {FRAME:exs#16.itm} 2 {FRAME:exs#16.itm(0)} {FRAME:exs#16.itm(1)} -attr xrf 1828 -attr oid 213 -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#16.itm}
+load net {FRAME:mul#7.itm(0)} -attr vt d
+load net {FRAME:mul#7.itm(1)} -attr vt d
+load net {FRAME:mul#7.itm(2)} -attr vt d
+load net {FRAME:mul#7.itm(3)} -attr vt d
+load net {FRAME:mul#7.itm(4)} -attr vt d
+load net {FRAME:mul#7.itm(5)} -attr vt d
+load net {FRAME:mul#7.itm(6)} -attr vt d
+load net {FRAME:mul#7.itm(7)} -attr vt d
+load net {FRAME:mul#7.itm(8)} -attr vt d
+load netBundle {FRAME:mul#7.itm} 9 {FRAME:mul#7.itm(0)} {FRAME:mul#7.itm(1)} {FRAME:mul#7.itm(2)} {FRAME:mul#7.itm(3)} {FRAME:mul#7.itm(4)} {FRAME:mul#7.itm(5)} {FRAME:mul#7.itm(6)} {FRAME:mul#7.itm(7)} {FRAME:mul#7.itm(8)} -attr xrf 1829 -attr oid 214 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {slc(ACC1:acc.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#1.itm(1)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc.psp.sva)#1.itm} 3 {slc(ACC1:acc.psp.sva)#1.itm(0)} {slc(ACC1:acc.psp.sva)#1.itm(1)} {slc(ACC1:acc.psp.sva)#1.itm(2)} -attr xrf 1830 -attr oid 215 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#1.itm}
+load net {FRAME:acc#43.itm(0)} -attr vt d
+load net {FRAME:acc#43.itm(1)} -attr vt d
+load net {FRAME:acc#43.itm(2)} -attr vt d
+load net {FRAME:acc#43.itm(3)} -attr vt d
+load net {FRAME:acc#43.itm(4)} -attr vt d
+load net {FRAME:acc#43.itm(5)} -attr vt d
+load net {FRAME:acc#43.itm(6)} -attr vt d
+load net {FRAME:acc#43.itm(7)} -attr vt d
+load net {FRAME:acc#43.itm(8)} -attr vt d
+load net {FRAME:acc#43.itm(9)} -attr vt d
+load netBundle {FRAME:acc#43.itm} 10 {FRAME:acc#43.itm(0)} {FRAME:acc#43.itm(1)} {FRAME:acc#43.itm(2)} {FRAME:acc#43.itm(3)} {FRAME:acc#43.itm(4)} {FRAME:acc#43.itm(5)} {FRAME:acc#43.itm(6)} {FRAME:acc#43.itm(7)} {FRAME:acc#43.itm(8)} {FRAME:acc#43.itm(9)} -attr xrf 1831 -attr oid 216 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {conc#146.itm(0)} -attr vt d
+load net {conc#146.itm(1)} -attr vt d
+load net {conc#146.itm(2)} -attr vt d
+load net {conc#146.itm(3)} -attr vt d
+load net {conc#146.itm(4)} -attr vt d
+load net {conc#146.itm(5)} -attr vt d
+load net {conc#146.itm(6)} -attr vt d
+load net {conc#146.itm(7)} -attr vt d
+load net {conc#146.itm(8)} -attr vt d
+load netBundle {conc#146.itm} 9 {conc#146.itm(0)} {conc#146.itm(1)} {conc#146.itm(2)} {conc#146.itm(3)} {conc#146.itm(4)} {conc#146.itm(5)} {conc#146.itm(6)} {conc#146.itm(7)} {conc#146.itm(8)} -attr xrf 1832 -attr oid 217 -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {FRAME:exs#50.itm(0)} -attr vt d
+load net {FRAME:exs#50.itm(1)} -attr vt d
+load net {FRAME:exs#50.itm(2)} -attr vt d
+load net {FRAME:exs#50.itm(3)} -attr vt d
+load net {FRAME:exs#50.itm(4)} -attr vt d
+load net {FRAME:exs#50.itm(5)} -attr vt d
+load netBundle {FRAME:exs#50.itm} 6 {FRAME:exs#50.itm(0)} {FRAME:exs#50.itm(1)} {FRAME:exs#50.itm(2)} {FRAME:exs#50.itm(3)} {FRAME:exs#50.itm(4)} {FRAME:exs#50.itm(5)} -attr xrf 1833 -attr oid 218 -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#50.itm}
+load net {FRAME:conc#32.itm(0)} -attr vt d
+load net {FRAME:conc#32.itm(1)} -attr vt d
+load net {FRAME:conc#32.itm(2)} -attr vt d
+load net {FRAME:conc#32.itm(3)} -attr vt d
+load netBundle {FRAME:conc#32.itm} 4 {FRAME:conc#32.itm(0)} {FRAME:conc#32.itm(1)} {FRAME:conc#32.itm(2)} {FRAME:conc#32.itm(3)} -attr xrf 1834 -attr oid 219 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#32.itm}
+load net {slc(ACC1:acc.psp.sva)#20.itm(0)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#20.itm(1)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#20.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc.psp.sva)#20.itm} 3 {slc(ACC1:acc.psp.sva)#20.itm(0)} {slc(ACC1:acc.psp.sva)#20.itm(1)} {slc(ACC1:acc.psp.sva)#20.itm(2)} -attr xrf 1835 -attr oid 220 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#20.itm}
+load net {FRAME:conc#64.itm(0)} -attr vt d
+load net {FRAME:conc#64.itm(1)} -attr vt d
+load net {FRAME:conc#64.itm(2)} -attr vt d
+load net {FRAME:conc#64.itm(3)} -attr vt d
+load net {FRAME:conc#64.itm(4)} -attr vt d
+load net {FRAME:conc#64.itm(5)} -attr vt d
+load net {FRAME:conc#64.itm(6)} -attr vt d
+load net {FRAME:conc#64.itm(7)} -attr vt d
+load netBundle {FRAME:conc#64.itm} 8 {FRAME:conc#64.itm(0)} {FRAME:conc#64.itm(1)} {FRAME:conc#64.itm(2)} {FRAME:conc#64.itm(3)} {FRAME:conc#64.itm(4)} {FRAME:conc#64.itm(5)} {FRAME:conc#64.itm(6)} {FRAME:conc#64.itm(7)} -attr xrf 1836 -attr oid 221 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#64.itm}
+load net {FRAME:acc#60.itm(0)} -attr vt d
+load net {FRAME:acc#60.itm(1)} -attr vt d
+load net {FRAME:acc#60.itm(2)} -attr vt d
+load net {FRAME:acc#60.itm(3)} -attr vt d
+load net {FRAME:acc#60.itm(4)} -attr vt d
+load netBundle {FRAME:acc#60.itm} 5 {FRAME:acc#60.itm(0)} {FRAME:acc#60.itm(1)} {FRAME:acc#60.itm(2)} {FRAME:acc#60.itm(3)} {FRAME:acc#60.itm(4)} -attr xrf 1837 -attr oid 222 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#60.itm}
+load net {slc(FRAME:acc#41.sdt).itm(0)} -attr vt d
+load net {slc(FRAME:acc#41.sdt).itm(1)} -attr vt d
+load net {slc(FRAME:acc#41.sdt).itm(2)} -attr vt d
+load net {slc(FRAME:acc#41.sdt).itm(3)} -attr vt d
+load netBundle {slc(FRAME:acc#41.sdt).itm} 4 {slc(FRAME:acc#41.sdt).itm(0)} {slc(FRAME:acc#41.sdt).itm(1)} {slc(FRAME:acc#41.sdt).itm(2)} {slc(FRAME:acc#41.sdt).itm(3)} -attr xrf 1838 -attr oid 223 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#41.sdt).itm}
+load net {slc(ACC1:acc.psp.sva)#15.itm(0)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#15.itm(1)} -attr vt d
+load net {slc(ACC1:acc.psp.sva)#15.itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc.psp.sva)#15.itm} 3 {slc(ACC1:acc.psp.sva)#15.itm(0)} {slc(ACC1:acc.psp.sva)#15.itm(1)} {slc(ACC1:acc.psp.sva)#15.itm(2)} -attr xrf 1839 -attr oid 224 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#15.itm}
+load net {slc(FRAME:acc#41.sdt)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#41.sdt)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#41.sdt)#1.itm(2)} -attr vt d
+load netBundle {slc(FRAME:acc#41.sdt)#1.itm} 3 {slc(FRAME:acc#41.sdt)#1.itm(0)} {slc(FRAME:acc#41.sdt)#1.itm(1)} {slc(FRAME:acc#41.sdt)#1.itm(2)} -attr xrf 1840 -attr oid 225 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#41.sdt)#1.itm}
+load net {conc#147.itm(0)} -attr vt d
+load net {conc#147.itm(1)} -attr vt d
+load net {conc#147.itm(2)} -attr vt d
+load net {conc#147.itm(3)} -attr vt d
+load net {conc#147.itm(4)} -attr vt d
+load net {conc#147.itm(5)} -attr vt d
+load net {conc#147.itm(6)} -attr vt d
+load net {conc#147.itm(7)} -attr vt d
+load net {conc#147.itm(8)} -attr vt d
+load net {conc#147.itm(9)} -attr vt d
+load netBundle {conc#147.itm} 10 {conc#147.itm(0)} {conc#147.itm(1)} {conc#147.itm(2)} {conc#147.itm(3)} {conc#147.itm(4)} {conc#147.itm(5)} {conc#147.itm(6)} {conc#147.itm(7)} {conc#147.itm(8)} {conc#147.itm(9)} -attr xrf 1841 -attr oid 226 -attr vt d -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {slc(FRAME:acc.psp).itm(0)} -attr vt d
+load net {slc(FRAME:acc.psp).itm(1)} -attr vt d
+load net {slc(FRAME:acc.psp).itm(2)} -attr vt d
+load netBundle {slc(FRAME:acc.psp).itm} 3 {slc(FRAME:acc.psp).itm(0)} {slc(FRAME:acc.psp).itm(1)} {slc(FRAME:acc.psp).itm(2)} -attr xrf 1842 -attr oid 227 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc.psp).itm}
+load net {slc(FRAME:acc.psp)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc.psp)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc.psp)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc.psp)#1.itm(3)} -attr vt d
+load netBundle {slc(FRAME:acc.psp)#1.itm} 4 {slc(FRAME:acc.psp)#1.itm(0)} {slc(FRAME:acc.psp)#1.itm(1)} {slc(FRAME:acc.psp)#1.itm(2)} {slc(FRAME:acc.psp)#1.itm(3)} -attr xrf 1843 -attr oid 228 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc.psp)#1.itm}
+load net {FRAME:or#3.itm(0)} -attr vt d
+load net {FRAME:or#3.itm(1)} -attr vt d
+load net {FRAME:or#3.itm(2)} -attr vt d
+load net {FRAME:or#3.itm(3)} -attr vt d
+load net {FRAME:or#3.itm(4)} -attr vt d
+load netBundle {FRAME:or#3.itm} 5 {FRAME:or#3.itm(0)} {FRAME:or#3.itm(1)} {FRAME:or#3.itm(2)} {FRAME:or#3.itm(3)} {FRAME:or#3.itm(4)} -attr xrf 1844 -attr oid 229 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {slc(FRAME:acc.psp)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc.psp)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc.psp)#2.itm(2)} -attr vt d
+load net {slc(FRAME:acc.psp)#2.itm(3)} -attr vt d
+load net {slc(FRAME:acc.psp)#2.itm(4)} -attr vt d
+load netBundle {slc(FRAME:acc.psp)#2.itm} 5 {slc(FRAME:acc.psp)#2.itm(0)} {slc(FRAME:acc.psp)#2.itm(1)} {slc(FRAME:acc.psp)#2.itm(2)} {slc(FRAME:acc.psp)#2.itm(3)} {slc(FRAME:acc.psp)#2.itm(4)} -attr xrf 1845 -attr oid 230 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc.psp)#2.itm}
+load net {conc#148.itm(0)} -attr vt d
+load net {conc#148.itm(1)} -attr vt d
+load net {conc#148.itm(2)} -attr vt d
+load net {conc#148.itm(3)} -attr vt d
+load net {conc#148.itm(4)} -attr vt d
+load netBundle {conc#148.itm} 5 {conc#148.itm(0)} {conc#148.itm(1)} {conc#148.itm(2)} {conc#148.itm(3)} {conc#148.itm(4)} -attr xrf 1846 -attr oid 231 -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {slc(FRAME:acc#61.psp).itm(0)} -attr vt d
+load net {slc(FRAME:acc#61.psp).itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#61.psp).itm} 2 {slc(FRAME:acc#61.psp).itm(0)} {slc(FRAME:acc#61.psp).itm(1)} -attr xrf 1847 -attr oid 232 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#61.psp).itm}
+load net {slc(FRAME:acc#61.psp)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#61.psp)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#61.psp)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#61.psp)#1.itm(3)} -attr vt d
+load net {slc(FRAME:acc#61.psp)#1.itm(4)} -attr vt d
+load net {slc(FRAME:acc#61.psp)#1.itm(5)} -attr vt d
+load net {slc(FRAME:acc#61.psp)#1.itm(6)} -attr vt d
+load net {slc(FRAME:acc#61.psp)#1.itm(7)} -attr vt d
+load net {slc(FRAME:acc#61.psp)#1.itm(8)} -attr vt d
+load netBundle {slc(FRAME:acc#61.psp)#1.itm} 9 {slc(FRAME:acc#61.psp)#1.itm(0)} {slc(FRAME:acc#61.psp)#1.itm(1)} {slc(FRAME:acc#61.psp)#1.itm(2)} {slc(FRAME:acc#61.psp)#1.itm(3)} {slc(FRAME:acc#61.psp)#1.itm(4)} {slc(FRAME:acc#61.psp)#1.itm(5)} {slc(FRAME:acc#61.psp)#1.itm(6)} {slc(FRAME:acc#61.psp)#1.itm(7)} {slc(FRAME:acc#61.psp)#1.itm(8)} -attr xrf 1848 -attr oid 233 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#61.psp)#1.itm}
+load net {clk} -attr xrf 1849 -attr oid 234
+load net {clk} -port {clk} -attr xrf 1850 -attr oid 235
+load net {en} -attr xrf 1851 -attr oid 236
+load net {en} -port {en} -attr xrf 1852 -attr oid 237
+load net {arst_n} -attr xrf 1853 -attr oid 238
+load net {arst_n} -port {arst_n} -attr xrf 1854 -attr oid 239
+load net {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 1855 -attr oid 240 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(0)} -port {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -port {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -port {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -port {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -port {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -port {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -port {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -port {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -port {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -port {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -port {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -port {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -port {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -port {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -port {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -port {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -port {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -port {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -port {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -port {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -port {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -port {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -port {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -port {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -port {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -port {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -port {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -port {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -port {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -port {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -port {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -port {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -port {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -port {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -port {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -port {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -port {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -port {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -port {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -port {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -port {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -port {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -port {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -port {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -port {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -port {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -port {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -port {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -port {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -port {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -port {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -port {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -port {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -port {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -port {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -port {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -port {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -port {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -port {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -port {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -port {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -port {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -port {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -port {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -port {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -port {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -port {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -port {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -port {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -port {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -port {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -port {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -port {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -port {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -port {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -port {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -port {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -port {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -port {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -port {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -port {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -port {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -port {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -port {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -port {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -port {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -port {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -port {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -port {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -port {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 1856 -attr oid 241 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d} 30 {vout:rsc:mgc_out_stdreg.d(0)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(29)} -attr xrf 1857 -attr oid 242 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#5} -port {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(0)} -port {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(1)} -port {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(2)} -port {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(3)} -port {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(4)} -port {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(5)} -port {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(6)} -port {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(7)} -port {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(8)} -port {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3} -port {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(0)} -port {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(1)} -port {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(2)} -port {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(3)} -port {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(4)} -port {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(0)} -port {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(1)} -port {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(2)} -port {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(3)} -port {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(0)} -port {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(1)} -port {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(2)} -port {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(3)} -port {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(4)} -port {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(5)} -port {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(6)} -port {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(7)} -port {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(8)} -port {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(9)} -port {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "reg(ACC1:slc(regs.regs(2))#14.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 1858 -attr oid 243 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2))#14.itm)}
+load net {regs.regs(1).sva(0)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(1)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(2)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(3)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(4)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(5)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(6)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(7)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(8)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(9)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {clk} -attr xrf 1859 -attr oid 244 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2))#14.itm(0)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#14.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(1)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#14.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(2)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#14.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(3)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#14.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(4)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#14.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(5)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#14.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(6)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#14.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(7)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#14.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(8)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#14.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(9)} -pin  "reg(ACC1:slc(regs.regs(2))#14.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#14.itm}
+load inst "reg(ACC1:slc(regs.regs(2))#15.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 1860 -attr oid 245 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2))#15.itm)}
+load net {regs.regs(1).sva(60)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(61)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(62)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(63)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(64)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(65)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(66)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(67)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(68)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(69)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {clk} -attr xrf 1861 -attr oid 246 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2))#15.itm(0)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#15.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(1)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#15.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(2)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#15.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(3)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#15.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(4)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#15.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(5)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#15.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(6)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#15.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(7)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#15.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(8)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#15.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(9)} -pin  "reg(ACC1:slc(regs.regs(2))#15.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#15.itm}
+load inst "reg(ACC1:slc(regs.regs(2))#16.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 1862 -attr oid 247 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2))#16.itm)}
+load net {regs.regs(1).sva(30)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(31)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(32)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(33)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(34)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(35)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(36)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(37)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(38)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(39)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {clk} -attr xrf 1863 -attr oid 248 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2))#16.itm(0)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(1)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(2)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(3)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(4)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(5)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(6)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(7)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(8)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(9)} -pin  "reg(ACC1:slc(regs.regs(2))#16.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load inst "reg(ACC1:slc(regs.regs(2))#11.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 1864 -attr oid 249 -attr vt dc -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2))#11.itm)}
+load net {regs.regs(1).sva(10)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(11)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(12)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(13)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(14)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(15)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(16)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(17)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(18)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(19)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {clk} -attr xrf 1865 -attr oid 250 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2))#11.itm(0)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#11.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(1)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#11.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(2)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#11.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(3)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#11.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(4)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#11.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(5)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#11.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(6)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#11.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(7)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#11.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(8)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#11.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(9)} -pin  "reg(ACC1:slc(regs.regs(2))#11.itm)" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#11.itm}
+load inst "reg(ACC1:slc(regs.regs(2))#12.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 1866 -attr oid 251 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2))#12.itm)}
+load net {regs.regs(1).sva(70)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(71)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(72)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(73)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(74)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(75)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(76)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(77)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(78)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(79)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {clk} -attr xrf 1867 -attr oid 252 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2))#12.itm(0)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#12.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(1)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#12.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(2)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#12.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(3)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#12.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(4)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#12.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(5)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#12.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(6)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#12.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(7)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#12.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(8)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#12.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(9)} -pin  "reg(ACC1:slc(regs.regs(2))#12.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#12.itm}
+load inst "reg(ACC1:slc(regs.regs(2))#13.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 1868 -attr oid 253 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2))#13.itm)}
+load net {regs.regs(1).sva(40)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(41)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(42)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(43)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(44)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(45)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(46)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(47)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(48)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(49)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {clk} -attr xrf 1869 -attr oid 254 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2))#13.itm(0)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(1)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(2)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(3)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(4)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(5)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(6)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(7)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(8)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(9)} -pin  "reg(ACC1:slc(regs.regs(2))#13.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load inst "reg(ACC1:slc(regs.regs(2)).itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 1870 -attr oid 255 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2)).itm)}
+load net {regs.regs(1).sva(20)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(21)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(22)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(23)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(24)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(25)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(26)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(27)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(28)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(29)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {clk} -attr xrf 1871 -attr oid 256 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2)).itm(0)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)).itm}
+load net {ACC1:slc(regs.regs(2)).itm(1)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)).itm}
+load net {ACC1:slc(regs.regs(2)).itm(2)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)).itm}
+load net {ACC1:slc(regs.regs(2)).itm(3)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)).itm}
+load net {ACC1:slc(regs.regs(2)).itm(4)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)).itm}
+load net {ACC1:slc(regs.regs(2)).itm(5)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)).itm}
+load net {ACC1:slc(regs.regs(2)).itm(6)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)).itm}
+load net {ACC1:slc(regs.regs(2)).itm(7)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)).itm}
+load net {ACC1:slc(regs.regs(2)).itm(8)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)).itm}
+load net {ACC1:slc(regs.regs(2)).itm(9)} -pin  "reg(ACC1:slc(regs.regs(2)).itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)).itm}
+load inst "reg(ACC1:slc(regs.regs(2))#9.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 1872 -attr oid 257 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2))#9.itm)}
+load net {regs.regs(1).sva(80)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(81)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(82)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(83)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(84)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(85)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(86)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(87)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(88)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(89)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {clk} -attr xrf 1873 -attr oid 258 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2))#9.itm(0)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#9.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(1)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#9.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(2)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#9.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(3)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#9.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(4)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#9.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(5)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#9.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(6)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#9.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(7)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#9.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(8)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#9.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(9)} -pin  "reg(ACC1:slc(regs.regs(2))#9.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#9.itm}
+load inst "reg(ACC1:slc(regs.regs(2))#10.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 1874 -attr oid 259 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2))#10.itm)}
+load net {regs.regs(1).sva(50)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(51)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(52)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(53)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(54)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(55)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(56)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(57)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(58)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(59)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {clk} -attr xrf 1875 -attr oid 260 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2))#10.itm(0)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(1)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(2)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(3)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(4)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(5)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(6)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(7)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(8)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(9)} -pin  "reg(ACC1:slc(regs.regs(2))#10.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load inst "reg(regs.regs(1).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 1876 -attr oid 261 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(1).sva)}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "reg(regs.regs(1).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "reg(regs.regs(1).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "reg(regs.regs(1).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "reg(regs.regs(1).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "reg(regs.regs(1).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "reg(regs.regs(1).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "reg(regs.regs(1).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "reg(regs.regs(1).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "reg(regs.regs(1).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "reg(regs.regs(1).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "reg(regs.regs(1).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "reg(regs.regs(1).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "reg(regs.regs(1).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "reg(regs.regs(1).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "reg(regs.regs(1).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "reg(regs.regs(1).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "reg(regs.regs(1).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "reg(regs.regs(1).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "reg(regs.regs(1).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "reg(regs.regs(1).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "reg(regs.regs(1).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "reg(regs.regs(1).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "reg(regs.regs(1).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "reg(regs.regs(1).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "reg(regs.regs(1).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "reg(regs.regs(1).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "reg(regs.regs(1).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "reg(regs.regs(1).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "reg(regs.regs(1).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "reg(regs.regs(1).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "reg(regs.regs(1).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "reg(regs.regs(1).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "reg(regs.regs(1).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "reg(regs.regs(1).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "reg(regs.regs(1).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "reg(regs.regs(1).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "reg(regs.regs(1).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "reg(regs.regs(1).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "reg(regs.regs(1).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "reg(regs.regs(1).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "reg(regs.regs(1).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "reg(regs.regs(1).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "reg(regs.regs(1).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "reg(regs.regs(1).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "reg(regs.regs(1).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "reg(regs.regs(1).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "reg(regs.regs(1).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "reg(regs.regs(1).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "reg(regs.regs(1).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "reg(regs.regs(1).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "reg(regs.regs(1).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "reg(regs.regs(1).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "reg(regs.regs(1).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "reg(regs.regs(1).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "reg(regs.regs(1).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "reg(regs.regs(1).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "reg(regs.regs(1).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "reg(regs.regs(1).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "reg(regs.regs(1).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "reg(regs.regs(1).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "reg(regs.regs(1).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "reg(regs.regs(1).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "reg(regs.regs(1).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "reg(regs.regs(1).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "reg(regs.regs(1).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "reg(regs.regs(1).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "reg(regs.regs(1).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "reg(regs.regs(1).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "reg(regs.regs(1).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "reg(regs.regs(1).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "reg(regs.regs(1).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "reg(regs.regs(1).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "reg(regs.regs(1).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "reg(regs.regs(1).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "reg(regs.regs(1).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "reg(regs.regs(1).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "reg(regs.regs(1).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "reg(regs.regs(1).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "reg(regs.regs(1).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "reg(regs.regs(1).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "reg(regs.regs(1).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "reg(regs.regs(1).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "reg(regs.regs(1).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "reg(regs.regs(1).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "reg(regs.regs(1).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "reg(regs.regs(1).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "reg(regs.regs(1).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "reg(regs.regs(1).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "reg(regs.regs(1).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "reg(regs.regs(1).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/C0_90#1}
+load net {clk} -pin  "reg(regs.regs(1).sva)" {clk} -attr xrf 1877 -attr oid 262 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(1).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(1).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(1).sva(0)} -pin  "reg(regs.regs(1).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "reg(regs.regs(1).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "reg(regs.regs(1).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "reg(regs.regs(1).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "reg(regs.regs(1).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "reg(regs.regs(1).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "reg(regs.regs(1).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "reg(regs.regs(1).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "reg(regs.regs(1).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "reg(regs.regs(1).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "reg(regs.regs(1).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "reg(regs.regs(1).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "reg(regs.regs(1).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "reg(regs.regs(1).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "reg(regs.regs(1).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "reg(regs.regs(1).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "reg(regs.regs(1).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "reg(regs.regs(1).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "reg(regs.regs(1).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "reg(regs.regs(1).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "reg(regs.regs(1).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "reg(regs.regs(1).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "reg(regs.regs(1).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "reg(regs.regs(1).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "reg(regs.regs(1).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "reg(regs.regs(1).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "reg(regs.regs(1).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "reg(regs.regs(1).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "reg(regs.regs(1).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "reg(regs.regs(1).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "reg(regs.regs(1).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "reg(regs.regs(1).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "reg(regs.regs(1).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "reg(regs.regs(1).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "reg(regs.regs(1).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "reg(regs.regs(1).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "reg(regs.regs(1).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "reg(regs.regs(1).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "reg(regs.regs(1).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "reg(regs.regs(1).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "reg(regs.regs(1).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "reg(regs.regs(1).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "reg(regs.regs(1).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "reg(regs.regs(1).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "reg(regs.regs(1).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "reg(regs.regs(1).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "reg(regs.regs(1).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "reg(regs.regs(1).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "reg(regs.regs(1).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "reg(regs.regs(1).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "reg(regs.regs(1).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "reg(regs.regs(1).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "reg(regs.regs(1).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "reg(regs.regs(1).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "reg(regs.regs(1).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "reg(regs.regs(1).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "reg(regs.regs(1).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "reg(regs.regs(1).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "reg(regs.regs(1).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "reg(regs.regs(1).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "reg(regs.regs(1).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "reg(regs.regs(1).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "reg(regs.regs(1).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "reg(regs.regs(1).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "reg(regs.regs(1).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "reg(regs.regs(1).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "reg(regs.regs(1).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "reg(regs.regs(1).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "reg(regs.regs(1).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "reg(regs.regs(1).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "reg(regs.regs(1).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "reg(regs.regs(1).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "reg(regs.regs(1).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "reg(regs.regs(1).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "reg(regs.regs(1).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "reg(regs.regs(1).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "reg(regs.regs(1).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "reg(regs.regs(1).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "reg(regs.regs(1).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "reg(regs.regs(1).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "reg(regs.regs(1).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "reg(regs.regs(1).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "reg(regs.regs(1).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "reg(regs.regs(1).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "reg(regs.regs(1).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "reg(regs.regs(1).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "reg(regs.regs(1).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "reg(regs.regs(1).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "reg(regs.regs(1).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "reg(regs.regs(1).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load inst "ACC1:acc#45" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 1878 -attr oid 263 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#45" {A(0)} -attr @path {/sobel/sobel:core/conc#103.itm}
+load net {ACC1:slc(regs.regs(2)).itm(0)} -pin  "ACC1:acc#45" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#103.itm}
+load net {ACC1:slc(regs.regs(2)).itm(1)} -pin  "ACC1:acc#45" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#103.itm}
+load net {ACC1:slc(regs.regs(2)).itm(2)} -pin  "ACC1:acc#45" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#103.itm}
+load net {ACC1:slc(regs.regs(2)).itm(3)} -pin  "ACC1:acc#45" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#103.itm}
+load net {ACC1:slc(regs.regs(2)).itm(4)} -pin  "ACC1:acc#45" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#103.itm}
+load net {ACC1:slc(regs.regs(2)).itm(5)} -pin  "ACC1:acc#45" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#103.itm}
+load net {ACC1:slc(regs.regs(2)).itm(6)} -pin  "ACC1:acc#45" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#103.itm}
+load net {ACC1:slc(regs.regs(2)).itm(7)} -pin  "ACC1:acc#45" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#103.itm}
+load net {ACC1:slc(regs.regs(2)).itm(8)} -pin  "ACC1:acc#45" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#103.itm}
+load net {ACC1:slc(regs.regs(2)).itm(9)} -pin  "ACC1:acc#45" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#103.itm}
+load net {PWR} -pin  "ACC1:acc#45" {B(0)} -attr @path {/sobel/sobel:core/conc#104.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(0)} -pin  "ACC1:acc#45" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#104.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(1)} -pin  "ACC1:acc#45" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#104.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(2)} -pin  "ACC1:acc#45" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#104.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(3)} -pin  "ACC1:acc#45" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#104.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(4)} -pin  "ACC1:acc#45" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#104.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(5)} -pin  "ACC1:acc#45" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#104.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(6)} -pin  "ACC1:acc#45" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#104.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(7)} -pin  "ACC1:acc#45" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#104.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(8)} -pin  "ACC1:acc#45" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#104.itm}
+load net {ACC1:slc(regs.regs(2))#9.itm(9)} -pin  "ACC1:acc#45" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#104.itm}
+load net {ACC1:acc#45.itm(0)} -pin  "ACC1:acc#45" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(1)} -pin  "ACC1:acc#45" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(2)} -pin  "ACC1:acc#45" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(3)} -pin  "ACC1:acc#45" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(4)} -pin  "ACC1:acc#45" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(5)} -pin  "ACC1:acc#45" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(6)} -pin  "ACC1:acc#45" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(7)} -pin  "ACC1:acc#45" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(8)} -pin  "ACC1:acc#45" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(9)} -pin  "ACC1:acc#45" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(10)} -pin  "ACC1:acc#45" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "ACC1:acc#45" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load inst "ACC1:not" "not(10)" "INTERFACE" -attr xrf 1879 -attr oid 264 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "ACC1:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "ACC1:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "ACC1:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "ACC1:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "ACC1:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "ACC1:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "ACC1:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "ACC1:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "ACC1:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load inst "ACC1:not#20" "not(10)" "INTERFACE" -attr xrf 1880 -attr oid 265 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#20} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "ACC1:not#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "ACC1:not#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "ACC1:not#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "ACC1:not#20" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "ACC1:not#20" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "ACC1:not#20" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "ACC1:not#20" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "ACC1:not#20" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "ACC1:not#20" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1:not#20" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {ACC1:not#20.itm(0)} -pin  "ACC1:not#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#20.itm}
+load net {ACC1:not#20.itm(1)} -pin  "ACC1:not#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#20.itm}
+load net {ACC1:not#20.itm(2)} -pin  "ACC1:not#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#20.itm}
+load net {ACC1:not#20.itm(3)} -pin  "ACC1:not#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#20.itm}
+load net {ACC1:not#20.itm(4)} -pin  "ACC1:not#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#20.itm}
+load net {ACC1:not#20.itm(5)} -pin  "ACC1:not#20" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#20.itm}
+load net {ACC1:not#20.itm(6)} -pin  "ACC1:not#20" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#20.itm}
+load net {ACC1:not#20.itm(7)} -pin  "ACC1:not#20" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#20.itm}
+load net {ACC1:not#20.itm(8)} -pin  "ACC1:not#20" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#20.itm}
+load net {ACC1:not#20.itm(9)} -pin  "ACC1:not#20" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#20.itm}
+load inst "ACC1:acc#44" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 1881 -attr oid 266 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#44" {A(0)} -attr @path {/sobel/sobel:core/conc#106.itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:acc#44" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#106.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:acc#44" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#106.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:acc#44" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#106.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:acc#44" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#106.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:acc#44" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#106.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:acc#44" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#106.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:acc#44" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#106.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:acc#44" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#106.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:acc#44" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#106.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:acc#44" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#106.itm}
+load net {PWR} -pin  "ACC1:acc#44" {B(0)} -attr @path {/sobel/sobel:core/conc#107.itm}
+load net {ACC1:not#20.itm(0)} -pin  "ACC1:acc#44" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#107.itm}
+load net {ACC1:not#20.itm(1)} -pin  "ACC1:acc#44" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#107.itm}
+load net {ACC1:not#20.itm(2)} -pin  "ACC1:acc#44" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#107.itm}
+load net {ACC1:not#20.itm(3)} -pin  "ACC1:acc#44" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#107.itm}
+load net {ACC1:not#20.itm(4)} -pin  "ACC1:acc#44" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#107.itm}
+load net {ACC1:not#20.itm(5)} -pin  "ACC1:acc#44" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#107.itm}
+load net {ACC1:not#20.itm(6)} -pin  "ACC1:acc#44" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#107.itm}
+load net {ACC1:not#20.itm(7)} -pin  "ACC1:acc#44" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#107.itm}
+load net {ACC1:not#20.itm(8)} -pin  "ACC1:acc#44" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#107.itm}
+load net {ACC1:not#20.itm(9)} -pin  "ACC1:acc#44" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#107.itm}
+load net {ACC1:acc#44.itm(0)} -pin  "ACC1:acc#44" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(1)} -pin  "ACC1:acc#44" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(2)} -pin  "ACC1:acc#44" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(3)} -pin  "ACC1:acc#44" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(4)} -pin  "ACC1:acc#44" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(5)} -pin  "ACC1:acc#44" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(6)} -pin  "ACC1:acc#44" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(7)} -pin  "ACC1:acc#44" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(8)} -pin  "ACC1:acc#44" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(9)} -pin  "ACC1:acc#44" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(10)} -pin  "ACC1:acc#44" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(11)} -pin  "ACC1:acc#44" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load inst "ACC1:acc#47" "add(12,1,12,1,13)" "INTERFACE" -attr xrf 1882 -attr oid 267 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {PWR} -pin  "ACC1:acc#47" {A(0)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:acc#45.itm(1)} -pin  "ACC1:acc#47" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:acc#45.itm(2)} -pin  "ACC1:acc#47" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:acc#45.itm(3)} -pin  "ACC1:acc#47" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:acc#45.itm(4)} -pin  "ACC1:acc#47" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:acc#45.itm(5)} -pin  "ACC1:acc#47" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:acc#45.itm(6)} -pin  "ACC1:acc#47" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:acc#45.itm(7)} -pin  "ACC1:acc#47" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:acc#45.itm(8)} -pin  "ACC1:acc#47" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:acc#45.itm(9)} -pin  "ACC1:acc#47" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:acc#45.itm(10)} -pin  "ACC1:acc#47" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "ACC1:acc#47" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {PWR} -pin  "ACC1:acc#47" {B(0)} -attr @path {/sobel/sobel:core/conc#105.itm}
+load net {ACC1:acc#44.itm(1)} -pin  "ACC1:acc#47" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#105.itm}
+load net {ACC1:acc#44.itm(2)} -pin  "ACC1:acc#47" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#105.itm}
+load net {ACC1:acc#44.itm(3)} -pin  "ACC1:acc#47" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#105.itm}
+load net {ACC1:acc#44.itm(4)} -pin  "ACC1:acc#47" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#105.itm}
+load net {ACC1:acc#44.itm(5)} -pin  "ACC1:acc#47" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#105.itm}
+load net {ACC1:acc#44.itm(6)} -pin  "ACC1:acc#47" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#105.itm}
+load net {ACC1:acc#44.itm(7)} -pin  "ACC1:acc#47" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#105.itm}
+load net {ACC1:acc#44.itm(8)} -pin  "ACC1:acc#47" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#105.itm}
+load net {ACC1:acc#44.itm(9)} -pin  "ACC1:acc#47" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#105.itm}
+load net {ACC1:acc#44.itm(10)} -pin  "ACC1:acc#47" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#105.itm}
+load net {ACC1:acc#44.itm(11)} -pin  "ACC1:acc#47" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#105.itm}
+load net {ACC1:acc#47.itm(0)} -pin  "ACC1:acc#47" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(1)} -pin  "ACC1:acc#47" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(2)} -pin  "ACC1:acc#47" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(3)} -pin  "ACC1:acc#47" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(4)} -pin  "ACC1:acc#47" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(5)} -pin  "ACC1:acc#47" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(6)} -pin  "ACC1:acc#47" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(7)} -pin  "ACC1:acc#47" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(8)} -pin  "ACC1:acc#47" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(9)} -pin  "ACC1:acc#47" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(10)} -pin  "ACC1:acc#47" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(11)} -pin  "ACC1:acc#47" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(12)} -pin  "ACC1:acc#47" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load inst "ACC1:not#21" "not(10)" "INTERFACE" -attr xrf 1883 -attr oid 268 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "ACC1:not#21" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "ACC1:not#21" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "ACC1:not#21" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "ACC1:not#21" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "ACC1:not#21" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "ACC1:not#21" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "ACC1:not#21" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "ACC1:not#21" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "ACC1:not#21" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "ACC1:not#21" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {ACC1:not#21.itm(0)} -pin  "ACC1:not#21" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(1)} -pin  "ACC1:not#21" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(2)} -pin  "ACC1:not#21" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(3)} -pin  "ACC1:not#21" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(4)} -pin  "ACC1:not#21" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(5)} -pin  "ACC1:not#21" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(6)} -pin  "ACC1:not#21" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(7)} -pin  "ACC1:not#21" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(8)} -pin  "ACC1:not#21" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(9)} -pin  "ACC1:not#21" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load inst "ACC1:acc#56" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 1884 -attr oid 269 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#56} -attr area 11.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:slc(regs.regs(2))#10.itm(0)} -pin  "ACC1:acc#56" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(1)} -pin  "ACC1:acc#56" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(2)} -pin  "ACC1:acc#56" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(3)} -pin  "ACC1:acc#56" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(4)} -pin  "ACC1:acc#56" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(5)} -pin  "ACC1:acc#56" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(6)} -pin  "ACC1:acc#56" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(7)} -pin  "ACC1:acc#56" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(8)} -pin  "ACC1:acc#56" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:slc(regs.regs(2))#10.itm(9)} -pin  "ACC1:acc#56" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#10.itm}
+load net {ACC1:not#21.itm(0)} -pin  "ACC1:acc#56" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(1)} -pin  "ACC1:acc#56" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(2)} -pin  "ACC1:acc#56" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(3)} -pin  "ACC1:acc#56" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(4)} -pin  "ACC1:acc#56" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(5)} -pin  "ACC1:acc#56" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(6)} -pin  "ACC1:acc#56" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(7)} -pin  "ACC1:acc#56" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(8)} -pin  "ACC1:acc#56" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:not#21.itm(9)} -pin  "ACC1:acc#56" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#21.itm}
+load net {ACC1:acc#56.itm(0)} -pin  "ACC1:acc#56" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#56.itm}
+load net {ACC1:acc#56.itm(1)} -pin  "ACC1:acc#56" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#56.itm}
+load net {ACC1:acc#56.itm(2)} -pin  "ACC1:acc#56" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#56.itm}
+load net {ACC1:acc#56.itm(3)} -pin  "ACC1:acc#56" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#56.itm}
+load net {ACC1:acc#56.itm(4)} -pin  "ACC1:acc#56" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#56.itm}
+load net {ACC1:acc#56.itm(5)} -pin  "ACC1:acc#56" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#56.itm}
+load net {ACC1:acc#56.itm(6)} -pin  "ACC1:acc#56" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#56.itm}
+load net {ACC1:acc#56.itm(7)} -pin  "ACC1:acc#56" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#56.itm}
+load net {ACC1:acc#56.itm(8)} -pin  "ACC1:acc#56" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#56.itm}
+load net {ACC1:acc#56.itm(9)} -pin  "ACC1:acc#56" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#56.itm}
+load net {ACC1:acc#56.itm(10)} -pin  "ACC1:acc#56" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#56.itm}
+load inst "ACC1:acc" "add(12,1,12,1,13)" "INTERFACE" -attr xrf 1885 -attr oid 270 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1:acc#47.itm(1)} -pin  "ACC1:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#47.itm(2)} -pin  "ACC1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#47.itm(3)} -pin  "ACC1:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#47.itm(4)} -pin  "ACC1:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#47.itm(5)} -pin  "ACC1:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#47.itm(6)} -pin  "ACC1:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#47.itm(7)} -pin  "ACC1:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#47.itm(8)} -pin  "ACC1:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#47.itm(9)} -pin  "ACC1:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#47.itm(10)} -pin  "ACC1:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#47.itm(11)} -pin  "ACC1:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#47.itm(12)} -pin  "ACC1:acc" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {PWR} -pin  "ACC1:acc" {B(0)} -attr @path {/sobel/sobel:core/conc#108.itm}
+load net {ACC1:acc#56.itm(0)} -pin  "ACC1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#108.itm}
+load net {ACC1:acc#56.itm(1)} -pin  "ACC1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#108.itm}
+load net {ACC1:acc#56.itm(2)} -pin  "ACC1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#108.itm}
+load net {ACC1:acc#56.itm(3)} -pin  "ACC1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#108.itm}
+load net {ACC1:acc#56.itm(4)} -pin  "ACC1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#108.itm}
+load net {ACC1:acc#56.itm(5)} -pin  "ACC1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#108.itm}
+load net {ACC1:acc#56.itm(6)} -pin  "ACC1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#108.itm}
+load net {ACC1:acc#56.itm(7)} -pin  "ACC1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#108.itm}
+load net {ACC1:acc#56.itm(8)} -pin  "ACC1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#108.itm}
+load net {ACC1:acc#56.itm(9)} -pin  "ACC1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#108.itm}
+load net {ACC1:acc#56.itm(10)} -pin  "ACC1:acc" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#108.itm}
+load net {ACC1:acc.psp.sva(0)} -pin  "ACC1:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load net {ACC1:acc.psp.sva(1)} -pin  "ACC1:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load net {ACC1:acc.psp.sva(2)} -pin  "ACC1:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load net {ACC1:acc.psp.sva(3)} -pin  "ACC1:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load net {ACC1:acc.psp.sva(4)} -pin  "ACC1:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load net {ACC1:acc.psp.sva(5)} -pin  "ACC1:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load net {ACC1:acc.psp.sva(6)} -pin  "ACC1:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load net {ACC1:acc.psp.sva(7)} -pin  "ACC1:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load net {ACC1:acc.psp.sva(8)} -pin  "ACC1:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load net {ACC1:acc.psp.sva(9)} -pin  "ACC1:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load net {ACC1:acc.psp.sva(10)} -pin  "ACC1:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load net {ACC1:acc.psp.sva(11)} -pin  "ACC1:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load net {ACC1:acc.psp.sva(12)} -pin  "ACC1:acc" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.psp.sva}
+load inst "FRAME:not#44" "not(3)" "INTERFACE" -attr xrf 1886 -attr oid 271 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#44} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.psp.sva(6)} -pin  "FRAME:not#44" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#5.itm}
+load net {ACC1:acc.psp.sva(7)} -pin  "FRAME:not#44" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#5.itm}
+load net {ACC1:acc.psp.sva(8)} -pin  "FRAME:not#44" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#5.itm}
+load net {FRAME:not#44.itm(0)} -pin  "FRAME:not#44" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#44.itm}
+load net {FRAME:not#44.itm(1)} -pin  "FRAME:not#44" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#44.itm}
+load net {FRAME:not#44.itm(2)} -pin  "FRAME:not#44" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#44.itm}
+load inst "FRAME:not#6" "not(3)" "INTERFACE" -attr xrf 1887 -attr oid 272 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {FRAME:acc#47.psp(2)} -pin  "FRAME:not#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#47.psp).itm}
+load net {FRAME:acc#47.psp(3)} -pin  "FRAME:not#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#47.psp).itm}
+load net {FRAME:acc#47.psp(4)} -pin  "FRAME:not#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#47.psp).itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:not#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:not#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:not#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load inst "FRAME:not#5" "not(1)" "INTERFACE" -attr xrf 1888 -attr oid 273 -attr @path {/sobel/sobel:core/FRAME:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#47.psp(4)} -pin  "FRAME:not#5" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#47.psp)#4.itm}
+load net {FRAME:not#5.itm} -pin  "FRAME:not#5" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load inst "FRAME:acc#45" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 1889 -attr oid 274 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#45} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "FRAME:acc#45" {A(0)} -attr @path {/sobel/sobel:core/conc#110.itm}
+load net {FRAME:acc#13.sdt(0)} -pin  "FRAME:acc#45" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#110.itm}
+load net {FRAME:acc#47.psp(0)} -pin  "FRAME:acc#45" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#110.itm}
+load net {FRAME:acc#47.psp(1)} -pin  "FRAME:acc#45" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#110.itm}
+load net {PWR} -pin  "FRAME:acc#45" {A(4)} -attr @path {/sobel/sobel:core/conc#110.itm}
+load net {FRAME:not#5.itm} -pin  "FRAME:acc#45" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#52.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:acc#45" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#52.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:acc#45" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#52.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:acc#45" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#52.itm}
+load net {FRAME:acc#45.itm(0)} -pin  "FRAME:acc#45" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#45.itm}
+load net {FRAME:acc#45.itm(1)} -pin  "FRAME:acc#45" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#45.itm}
+load net {FRAME:acc#45.itm(2)} -pin  "FRAME:acc#45" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#45.itm}
+load net {FRAME:acc#45.itm(3)} -pin  "FRAME:acc#45" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#45.itm}
+load net {FRAME:acc#45.itm(4)} -pin  "FRAME:acc#45" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#45.itm}
+load inst "FRAME:not#43" "not(1)" "INTERFACE" -attr xrf 1890 -attr oid 275 -attr @path {/sobel/sobel:core/FRAME:not#43} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#45.itm(4)} -pin  "FRAME:not#43" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#8.itm}
+load net {FRAME:not#43.itm} -pin  "FRAME:not#43" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#43.itm}
+load inst "FRAME:acc#40" "add(5,1,4,1,6)" "INTERFACE" -attr xrf 1891 -attr oid 276 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,1,4,1,6)"
+load net {PWR} -pin  "FRAME:acc#40" {A(0)} -attr @path {/sobel/sobel:core/conc#109.itm}
+load net {FRAME:not#44.itm(0)} -pin  "FRAME:acc#40" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#109.itm}
+load net {FRAME:not#44.itm(1)} -pin  "FRAME:acc#40" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#109.itm}
+load net {FRAME:not#44.itm(2)} -pin  "FRAME:acc#40" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#109.itm}
+load net {PWR} -pin  "FRAME:acc#40" {A(4)} -attr @path {/sobel/sobel:core/conc#109.itm}
+load net {FRAME:not#43.itm} -pin  "FRAME:acc#40" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#49.itm}
+load net {FRAME:acc#47.psp(2)} -pin  "FRAME:acc#40" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#49.itm}
+load net {FRAME:acc#47.psp(3)} -pin  "FRAME:acc#40" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#49.itm}
+load net {FRAME:acc#47.psp(4)} -pin  "FRAME:acc#40" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#49.itm}
+load net {FRAME:acc#40.itm(0)} -pin  "FRAME:acc#40" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(1)} -pin  "FRAME:acc#40" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(2)} -pin  "FRAME:acc#40" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(3)} -pin  "FRAME:acc#40" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(4)} -pin  "FRAME:acc#40" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(5)} -pin  "FRAME:acc#40" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load inst "FRAME:acc#41" "add(5,1,5,0,7)" "INTERFACE" -attr xrf 1892 -attr oid 277 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {FRAME:acc#40.itm(1)} -pin  "FRAME:acc#41" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:acc#40.itm(2)} -pin  "FRAME:acc#41" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:acc#40.itm(3)} -pin  "FRAME:acc#41" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:acc#40.itm(4)} -pin  "FRAME:acc#41" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:acc#40.itm(5)} -pin  "FRAME:acc#41" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:acc#47.psp(4)} -pin  "FRAME:acc#41" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#17.itm}
+load net {ACC1:acc.psp.sva(12)} -pin  "FRAME:acc#41" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#17.itm}
+load net {ACC1:acc.psp.sva(12)} -pin  "FRAME:acc#41" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#17.itm}
+load net {ACC1:acc.psp.sva(12)} -pin  "FRAME:acc#41" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#17.itm}
+load net {ACC1:acc.psp.sva(12)} -pin  "FRAME:acc#41" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#17.itm}
+load net {FRAME:acc#41.sdt(0)} -pin  "FRAME:acc#41" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.sdt}
+load net {FRAME:acc#41.sdt(1)} -pin  "FRAME:acc#41" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.sdt}
+load net {FRAME:acc#41.sdt(2)} -pin  "FRAME:acc#41" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.sdt}
+load net {FRAME:acc#41.sdt(3)} -pin  "FRAME:acc#41" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.sdt}
+load net {FRAME:acc#41.sdt(4)} -pin  "FRAME:acc#41" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.sdt}
+load net {FRAME:acc#41.sdt(5)} -pin  "FRAME:acc#41" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.sdt}
+load net {FRAME:acc#41.sdt(6)} -pin  "FRAME:acc#41" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.sdt}
+load inst "acc" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 1893 -attr oid 278 -attr vt d -attr @path {/sobel/sobel:core/acc} -attr area 4.306828 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,0,4)"
+load net {ACC1:acc#42.psp.sva(12)} -pin  "acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {ACC1:acc#42.psp.sva(12)} -pin  "acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {ACC1:acc#42.psp.sva(12)} -pin  "acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {ACC1:acc#42.psp.sva(12)} -pin  "acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#14.itm}
+load net {ACC1:acc#42.psp.sva(12)} -pin  "acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#14.itm}
+load net {acc.itm(0)} -pin  "acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(1)} -pin  "acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(2)} -pin  "acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(3)} -pin  "acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load inst "acc#4" "add(2,0,3,0,4)" "INTERFACE" -attr xrf 1894 -attr oid 279 -attr vt d -attr @path {/sobel/sobel:core/acc#4} -attr area 4.306828 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,0,4)"
+load net {ACC1:acc#42.psp.sva(12)} -pin  "acc#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {ACC1:acc#42.psp.sva(12)} -pin  "acc#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {ACC1:acc#42.psp.sva(12)} -pin  "acc#4" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:acc#42.psp.sva(12)} -pin  "acc#4" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:acc#42.psp.sva(12)} -pin  "acc#4" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {acc#4.itm(0)} -pin  "acc#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#4.itm}
+load net {acc#4.itm(1)} -pin  "acc#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#4.itm}
+load net {acc#4.itm(2)} -pin  "acc#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#4.itm}
+load net {acc#4.itm(3)} -pin  "acc#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#4.itm}
+load inst "FRAME:acc" "add(12,-1,11,1,12)" "INTERFACE" -attr xrf 1895 -attr oid 280 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc} -attr area 13.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,11,1,12)"
+load net {ACC1:acc#42.psp.sva(12)} -pin  "FRAME:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:acc#42.psp.sva(12)} -pin  "FRAME:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {acc#4.itm(0)} -pin  "FRAME:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {acc#4.itm(1)} -pin  "FRAME:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {acc#4.itm(2)} -pin  "FRAME:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {acc#4.itm(3)} -pin  "FRAME:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {GND} -pin  "FRAME:acc" {A(6)} -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:acc#42.psp.sva(12)} -pin  "FRAME:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {acc.itm(0)} -pin  "FRAME:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {acc.itm(1)} -pin  "FRAME:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {acc.itm(2)} -pin  "FRAME:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {acc.itm(3)} -pin  "FRAME:acc" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {FRAME:acc#24.sdt(1)} -pin  "FRAME:acc" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#24.sdt)#1.itm}
+load net {FRAME:acc#24.sdt(2)} -pin  "FRAME:acc" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#24.sdt)#1.itm}
+load net {FRAME:acc#24.sdt(3)} -pin  "FRAME:acc" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#24.sdt)#1.itm}
+load net {FRAME:acc#24.sdt(4)} -pin  "FRAME:acc" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#24.sdt)#1.itm}
+load net {FRAME:acc#24.sdt(5)} -pin  "FRAME:acc" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#24.sdt)#1.itm}
+load net {FRAME:acc#24.sdt(6)} -pin  "FRAME:acc" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#24.sdt)#1.itm}
+load net {FRAME:acc#24.sdt(7)} -pin  "FRAME:acc" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#24.sdt)#1.itm}
+load net {FRAME:acc#24.sdt(8)} -pin  "FRAME:acc" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#24.sdt)#1.itm}
+load net {FRAME:acc#24.sdt(9)} -pin  "FRAME:acc" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#24.sdt)#1.itm}
+load net {FRAME:acc#24.sdt(10)} -pin  "FRAME:acc" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#24.sdt)#1.itm}
+load net {FRAME:acc#24.sdt(11)} -pin  "FRAME:acc" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#24.sdt)#1.itm}
+load net {FRAME:acc.psp(0)} -pin  "FRAME:acc" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc.psp}
+load net {FRAME:acc.psp(1)} -pin  "FRAME:acc" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc.psp}
+load net {FRAME:acc.psp(2)} -pin  "FRAME:acc" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc.psp}
+load net {FRAME:acc.psp(3)} -pin  "FRAME:acc" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc.psp}
+load net {FRAME:acc.psp(4)} -pin  "FRAME:acc" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc.psp}
+load net {FRAME:acc.psp(5)} -pin  "FRAME:acc" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc.psp}
+load net {FRAME:acc.psp(6)} -pin  "FRAME:acc" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc.psp}
+load net {FRAME:acc.psp(7)} -pin  "FRAME:acc" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc.psp}
+load net {FRAME:acc.psp(8)} -pin  "FRAME:acc" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc.psp}
+load net {FRAME:acc.psp(9)} -pin  "FRAME:acc" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc.psp}
+load net {FRAME:acc.psp(10)} -pin  "FRAME:acc" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc.psp}
+load net {FRAME:acc.psp(11)} -pin  "FRAME:acc" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc.psp}
+load inst "FRAME:mul#2" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 1896 -attr oid 281 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC1:acc#42.psp.sva(12)} -pin  "FRAME:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#13.itm}
+load net {ACC1:acc#42.psp.sva(12)} -pin  "FRAME:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#13.itm}
+load net {PWR} -pin  "FRAME:mul#2" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#2.itm(0)} -pin  "FRAME:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(1)} -pin  "FRAME:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(2)} -pin  "FRAME:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(3)} -pin  "FRAME:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(4)} -pin  "FRAME:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(5)} -pin  "FRAME:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(6)} -pin  "FRAME:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(7)} -pin  "FRAME:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(8)} -pin  "FRAME:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(9)} -pin  "FRAME:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(10)} -pin  "FRAME:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load inst "FRAME:mul#3" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 1897 -attr oid 282 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc#42.psp.sva(9)} -pin  "FRAME:mul#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#4.itm}
+load net {ACC1:acc#42.psp.sva(10)} -pin  "FRAME:mul#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#4.itm}
+load net {ACC1:acc#42.psp.sva(11)} -pin  "FRAME:mul#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#4.itm}
+load net {PWR} -pin  "FRAME:mul#3" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#3" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#3" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#3.itm(0)} -pin  "FRAME:mul#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "FRAME:mul#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "FRAME:mul#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "FRAME:mul#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "FRAME:mul#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "FRAME:mul#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "FRAME:mul#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "FRAME:mul#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "FRAME:mul#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load inst "FRAME:not#50" "not(1)" "INTERFACE" -attr xrf 1898 -attr oid 283 -attr @path {/sobel/sobel:core/FRAME:not#50} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#49.psp(4)} -pin  "FRAME:not#50" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#49.psp)#6.itm}
+load net {FRAME:not#50.itm} -pin  "FRAME:not#50" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#50.itm}
+load inst "FRAME:not#15" "not(3)" "INTERFACE" -attr xrf 1899 -attr oid 284 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#15} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {FRAME:acc#49.psp(2)} -pin  "FRAME:not#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#49.psp)#2.itm}
+load net {FRAME:acc#49.psp(3)} -pin  "FRAME:not#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#49.psp)#2.itm}
+load net {FRAME:acc#49.psp(4)} -pin  "FRAME:not#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#49.psp)#2.itm}
+load net {FRAME:not#15.itm(0)} -pin  "FRAME:not#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#15.itm}
+load net {FRAME:not#15.itm(1)} -pin  "FRAME:not#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#15.itm}
+load net {FRAME:not#15.itm(2)} -pin  "FRAME:not#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#15.itm}
+load inst "FRAME:not#47" "not(1)" "INTERFACE" -attr xrf 1900 -attr oid 285 -attr @path {/sobel/sobel:core/FRAME:not#47} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#49.psp(4)} -pin  "FRAME:not#47" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#49.psp)#4.itm}
+load net {FRAME:not#47.itm} -pin  "FRAME:not#47" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#47.itm}
+load inst "FRAME:acc#26" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 1901 -attr oid 286 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#26} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "FRAME:acc#26" {A(0)} -attr @path {/sobel/sobel:core/conc#118.itm}
+load net {FRAME:acc#18.sdt(0)} -pin  "FRAME:acc#26" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#118.itm}
+load net {FRAME:acc#49.psp(0)} -pin  "FRAME:acc#26" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#118.itm}
+load net {FRAME:acc#49.psp(1)} -pin  "FRAME:acc#26" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/conc#118.itm}
+load net {PWR} -pin  "FRAME:acc#26" {A(4)} -attr @path {/sobel/sobel:core/conc#118.itm}
+load net {FRAME:not#47.itm} -pin  "FRAME:acc#26" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#42.itm}
+load net {FRAME:not#15.itm(0)} -pin  "FRAME:acc#26" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#42.itm}
+load net {FRAME:not#15.itm(1)} -pin  "FRAME:acc#26" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#42.itm}
+load net {FRAME:not#15.itm(2)} -pin  "FRAME:acc#26" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#42.itm}
+load net {FRAME:acc#26.itm(0)} -pin  "FRAME:acc#26" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(1)} -pin  "FRAME:acc#26" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(2)} -pin  "FRAME:acc#26" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(3)} -pin  "FRAME:acc#26" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(4)} -pin  "FRAME:acc#26" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load inst "FRAME:not#52" "not(1)" "INTERFACE" -attr xrf 1902 -attr oid 287 -attr vt c -attr @path {/sobel/sobel:core/FRAME:not#52} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#26.itm(4)} -pin  "FRAME:not#52" {A(0)} -attr vt c -attr @path {/sobel/sobel:core/FRAME:slc#5.itm}
+load net {FRAME:not#52.itm} -pin  "FRAME:not#52" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/FRAME:not#52.itm}
+load inst "FRAME:acc#19" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 1903 -attr oid 288 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#19} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#52.itm} -pin  "FRAME:acc#19" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/conc#117.itm}
+load net {PWR} -pin  "FRAME:acc#19" {A(1)} -attr @path {/sobel/sobel:core/conc#117.itm}
+load net {FRAME:not#50.itm} -pin  "FRAME:acc#19" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#117.itm}
+load net {FRAME:acc#49.psp(2)} -pin  "FRAME:acc#19" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#49.psp)#3.itm}
+load net {FRAME:acc#49.psp(3)} -pin  "FRAME:acc#19" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#49.psp)#3.itm}
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#19" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#19" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#19" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(3)} -pin  "FRAME:acc#19" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load inst "FRAME:not#16" "not(3)" "INTERFACE" -attr xrf 1904 -attr oid 289 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#42.psp.sva(6)} -pin  "FRAME:not#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#6.itm}
+load net {ACC1:acc#42.psp.sva(7)} -pin  "FRAME:not#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#6.itm}
+load net {ACC1:acc#42.psp.sva(8)} -pin  "FRAME:not#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#6.itm}
+load net {FRAME:not#16.itm(0)} -pin  "FRAME:not#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load net {FRAME:not#16.itm(1)} -pin  "FRAME:not#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load net {FRAME:not#16.itm(2)} -pin  "FRAME:not#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load inst "FRAME:acc#20" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 1905 -attr oid 290 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#20" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#20" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#20" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(3)} -pin  "FRAME:acc#20" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:not#16.itm(0)} -pin  "FRAME:acc#20" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load net {FRAME:not#16.itm(1)} -pin  "FRAME:acc#20" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load net {FRAME:not#16.itm(2)} -pin  "FRAME:acc#20" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load net {FRAME:acc#20.itm(0)} -pin  "FRAME:acc#20" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(1)} -pin  "FRAME:acc#20" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(2)} -pin  "FRAME:acc#20" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(3)} -pin  "FRAME:acc#20" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(4)} -pin  "FRAME:acc#20" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load inst "FRAME:acc#21" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 1906 -attr oid 291 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {FRAME:acc#20.itm(0)} -pin  "FRAME:acc#21" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(1)} -pin  "FRAME:acc#21" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(2)} -pin  "FRAME:acc#21" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(3)} -pin  "FRAME:acc#21" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(4)} -pin  "FRAME:acc#21" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#49.psp(4)} -pin  "FRAME:acc#21" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#119.itm}
+load net {PWR} -pin  "FRAME:acc#21" {B(1)} -attr @path {/sobel/sobel:core/conc#119.itm}
+load net {GND} -pin  "FRAME:acc#21" {B(2)} -attr @path {/sobel/sobel:core/conc#119.itm}
+load net {GND} -pin  "FRAME:acc#21" {B(3)} -attr @path {/sobel/sobel:core/conc#119.itm}
+load net {PWR} -pin  "FRAME:acc#21" {B(4)} -attr @path {/sobel/sobel:core/conc#119.itm}
+load net {FRAME:acc#21.itm(0)} -pin  "FRAME:acc#21" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(1)} -pin  "FRAME:acc#21" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(2)} -pin  "FRAME:acc#21" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(3)} -pin  "FRAME:acc#21" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(4)} -pin  "FRAME:acc#21" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load inst "FRAME:acc#22" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 1907 -attr oid 292 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {ACC1:acc#42.psp.sva(3)} -pin  "FRAME:acc#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#5.itm}
+load net {ACC1:acc#42.psp.sva(4)} -pin  "FRAME:acc#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#5.itm}
+load net {ACC1:acc#42.psp.sva(5)} -pin  "FRAME:acc#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#5.itm}
+load net {ACC1:acc#42.psp.sva(6)} -pin  "FRAME:acc#22" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#5.itm}
+load net {ACC1:acc#42.psp.sva(7)} -pin  "FRAME:acc#22" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#5.itm}
+load net {ACC1:acc#42.psp.sva(8)} -pin  "FRAME:acc#22" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#5.itm}
+load net {FRAME:acc#21.itm(0)} -pin  "FRAME:acc#22" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(1)} -pin  "FRAME:acc#22" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(2)} -pin  "FRAME:acc#22" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(3)} -pin  "FRAME:acc#22" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(4)} -pin  "FRAME:acc#22" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#22.itm(0)} -pin  "FRAME:acc#22" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(1)} -pin  "FRAME:acc#22" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(2)} -pin  "FRAME:acc#22" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(3)} -pin  "FRAME:acc#22" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(4)} -pin  "FRAME:acc#22" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(5)} -pin  "FRAME:acc#22" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(6)} -pin  "FRAME:acc#22" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(7)} -pin  "FRAME:acc#22" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load inst "FRAME:acc#23" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 1908 -attr oid 293 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul#3.itm(0)} -pin  "FRAME:acc#23" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "FRAME:acc#23" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "FRAME:acc#23" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "FRAME:acc#23" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "FRAME:acc#23" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "FRAME:acc#23" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "FRAME:acc#23" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "FRAME:acc#23" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "FRAME:acc#23" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:acc#22.itm(0)} -pin  "FRAME:acc#23" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(1)} -pin  "FRAME:acc#23" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(2)} -pin  "FRAME:acc#23" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(3)} -pin  "FRAME:acc#23" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(4)} -pin  "FRAME:acc#23" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(5)} -pin  "FRAME:acc#23" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(6)} -pin  "FRAME:acc#23" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(7)} -pin  "FRAME:acc#23" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#23.itm(0)} -pin  "FRAME:acc#23" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(1)} -pin  "FRAME:acc#23" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(2)} -pin  "FRAME:acc#23" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(3)} -pin  "FRAME:acc#23" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(4)} -pin  "FRAME:acc#23" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(5)} -pin  "FRAME:acc#23" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(6)} -pin  "FRAME:acc#23" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(7)} -pin  "FRAME:acc#23" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(8)} -pin  "FRAME:acc#23" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(9)} -pin  "FRAME:acc#23" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load inst "FRAME:acc#24" "add(11,0,10,1,12)" "INTERFACE" -attr xrf 1909 -attr oid 294 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#24} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12)"
+load net {FRAME:mul#2.itm(0)} -pin  "FRAME:acc#24" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(1)} -pin  "FRAME:acc#24" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(2)} -pin  "FRAME:acc#24" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(3)} -pin  "FRAME:acc#24" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(4)} -pin  "FRAME:acc#24" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(5)} -pin  "FRAME:acc#24" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(6)} -pin  "FRAME:acc#24" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(7)} -pin  "FRAME:acc#24" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(8)} -pin  "FRAME:acc#24" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(9)} -pin  "FRAME:acc#24" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(10)} -pin  "FRAME:acc#24" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:acc#23.itm(0)} -pin  "FRAME:acc#24" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(1)} -pin  "FRAME:acc#24" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(2)} -pin  "FRAME:acc#24" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(3)} -pin  "FRAME:acc#24" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(4)} -pin  "FRAME:acc#24" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(5)} -pin  "FRAME:acc#24" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(6)} -pin  "FRAME:acc#24" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(7)} -pin  "FRAME:acc#24" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(8)} -pin  "FRAME:acc#24" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(9)} -pin  "FRAME:acc#24" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#24.sdt(0)} -pin  "FRAME:acc#24" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#24.sdt}
+load net {FRAME:acc#24.sdt(1)} -pin  "FRAME:acc#24" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#24.sdt}
+load net {FRAME:acc#24.sdt(2)} -pin  "FRAME:acc#24" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#24.sdt}
+load net {FRAME:acc#24.sdt(3)} -pin  "FRAME:acc#24" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#24.sdt}
+load net {FRAME:acc#24.sdt(4)} -pin  "FRAME:acc#24" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#24.sdt}
+load net {FRAME:acc#24.sdt(5)} -pin  "FRAME:acc#24" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#24.sdt}
+load net {FRAME:acc#24.sdt(6)} -pin  "FRAME:acc#24" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#24.sdt}
+load net {FRAME:acc#24.sdt(7)} -pin  "FRAME:acc#24" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#24.sdt}
+load net {FRAME:acc#24.sdt(8)} -pin  "FRAME:acc#24" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#24.sdt}
+load net {FRAME:acc#24.sdt(9)} -pin  "FRAME:acc#24" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#24.sdt}
+load net {FRAME:acc#24.sdt(10)} -pin  "FRAME:acc#24" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#24.sdt}
+load net {FRAME:acc#24.sdt(11)} -pin  "FRAME:acc#24" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#24.sdt}
+load inst "acc#5" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 1910 -attr oid 295 -attr vt d -attr @path {/sobel/sobel:core/acc#5} -attr area 4.306828 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,0,4)"
+load net {ACC1:acc#43.psp.sva(12)} -pin  "acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#6.itm}
+load net {ACC1:acc#43.psp.sva(12)} -pin  "acc#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#6.itm}
+load net {ACC1:acc#43.psp.sva(12)} -pin  "acc#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#6.itm}
+load net {ACC1:acc#43.psp.sva(12)} -pin  "acc#5" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {ACC1:acc#43.psp.sva(12)} -pin  "acc#5" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {acc#5.itm(0)} -pin  "acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(1)} -pin  "acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(2)} -pin  "acc#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(3)} -pin  "acc#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load inst "acc#6" "add(2,0,3,0,4)" "INTERFACE" -attr xrf 1911 -attr oid 296 -attr vt d -attr @path {/sobel/sobel:core/acc#6} -attr area 4.306828 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,0,4)"
+load net {ACC1:acc#43.psp.sva(12)} -pin  "acc#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#7.itm}
+load net {ACC1:acc#43.psp.sva(12)} -pin  "acc#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#7.itm}
+load net {ACC1:acc#43.psp.sva(12)} -pin  "acc#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:acc#43.psp.sva(12)} -pin  "acc#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:acc#43.psp.sva(12)} -pin  "acc#6" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {acc#6.itm(0)} -pin  "acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(1)} -pin  "acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(2)} -pin  "acc#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(3)} -pin  "acc#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load inst "FRAME:acc#61" "add(12,-1,11,1,12)" "INTERFACE" -attr xrf 1912 -attr oid 297 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61} -attr area 13.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,11,1,12)"
+load net {ACC1:acc#43.psp.sva(12)} -pin  "FRAME:acc#61" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {ACC1:acc#43.psp.sva(12)} -pin  "FRAME:acc#61" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {acc#6.itm(0)} -pin  "FRAME:acc#61" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {acc#6.itm(1)} -pin  "FRAME:acc#61" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {acc#6.itm(2)} -pin  "FRAME:acc#61" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {acc#6.itm(3)} -pin  "FRAME:acc#61" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {GND} -pin  "FRAME:acc#61" {A(6)} -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {ACC1:acc#43.psp.sva(12)} -pin  "FRAME:acc#61" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {acc#5.itm(0)} -pin  "FRAME:acc#61" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {acc#5.itm(1)} -pin  "FRAME:acc#61" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {acc#5.itm(2)} -pin  "FRAME:acc#61" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {acc#5.itm(3)} -pin  "FRAME:acc#61" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {FRAME:acc#37.sdt(1)} -pin  "FRAME:acc#61" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#37.sdt)#1.itm}
+load net {FRAME:acc#37.sdt(2)} -pin  "FRAME:acc#61" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#37.sdt)#1.itm}
+load net {FRAME:acc#37.sdt(3)} -pin  "FRAME:acc#61" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#37.sdt)#1.itm}
+load net {FRAME:acc#37.sdt(4)} -pin  "FRAME:acc#61" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#37.sdt)#1.itm}
+load net {FRAME:acc#37.sdt(5)} -pin  "FRAME:acc#61" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#37.sdt)#1.itm}
+load net {FRAME:acc#37.sdt(6)} -pin  "FRAME:acc#61" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#37.sdt)#1.itm}
+load net {FRAME:acc#37.sdt(7)} -pin  "FRAME:acc#61" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#37.sdt)#1.itm}
+load net {FRAME:acc#37.sdt(8)} -pin  "FRAME:acc#61" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#37.sdt)#1.itm}
+load net {FRAME:acc#37.sdt(9)} -pin  "FRAME:acc#61" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#37.sdt)#1.itm}
+load net {FRAME:acc#37.sdt(10)} -pin  "FRAME:acc#61" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#37.sdt)#1.itm}
+load net {FRAME:acc#37.sdt(11)} -pin  "FRAME:acc#61" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#37.sdt)#1.itm}
+load net {FRAME:acc#61.psp(0)} -pin  "FRAME:acc#61" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61.psp}
+load net {FRAME:acc#61.psp(1)} -pin  "FRAME:acc#61" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61.psp}
+load net {FRAME:acc#61.psp(2)} -pin  "FRAME:acc#61" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61.psp}
+load net {FRAME:acc#61.psp(3)} -pin  "FRAME:acc#61" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61.psp}
+load net {FRAME:acc#61.psp(4)} -pin  "FRAME:acc#61" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61.psp}
+load net {FRAME:acc#61.psp(5)} -pin  "FRAME:acc#61" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61.psp}
+load net {FRAME:acc#61.psp(6)} -pin  "FRAME:acc#61" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61.psp}
+load net {FRAME:acc#61.psp(7)} -pin  "FRAME:acc#61" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61.psp}
+load net {FRAME:acc#61.psp(8)} -pin  "FRAME:acc#61" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61.psp}
+load net {FRAME:acc#61.psp(9)} -pin  "FRAME:acc#61" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61.psp}
+load net {FRAME:acc#61.psp(10)} -pin  "FRAME:acc#61" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61.psp}
+load net {FRAME:acc#61.psp(11)} -pin  "FRAME:acc#61" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#61.psp}
+load inst "FRAME:mul#4" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 1913 -attr oid 298 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC1:acc#43.psp.sva(12)} -pin  "FRAME:mul#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#15.itm}
+load net {ACC1:acc#43.psp.sva(12)} -pin  "FRAME:mul#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#15.itm}
+load net {PWR} -pin  "FRAME:mul#4" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#4.itm(0)} -pin  "FRAME:mul#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(1)} -pin  "FRAME:mul#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(2)} -pin  "FRAME:mul#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(3)} -pin  "FRAME:mul#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(4)} -pin  "FRAME:mul#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(5)} -pin  "FRAME:mul#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(6)} -pin  "FRAME:mul#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(7)} -pin  "FRAME:mul#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(8)} -pin  "FRAME:mul#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(9)} -pin  "FRAME:mul#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(10)} -pin  "FRAME:mul#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load inst "FRAME:mul#5" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 1914 -attr oid 299 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc#43.psp.sva(9)} -pin  "FRAME:mul#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#4.itm}
+load net {ACC1:acc#43.psp.sva(10)} -pin  "FRAME:mul#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#4.itm}
+load net {ACC1:acc#43.psp.sva(11)} -pin  "FRAME:mul#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#4.itm}
+load net {PWR} -pin  "FRAME:mul#5" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#5" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#5" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#5.itm(0)} -pin  "FRAME:mul#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(1)} -pin  "FRAME:mul#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(2)} -pin  "FRAME:mul#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(3)} -pin  "FRAME:mul#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(4)} -pin  "FRAME:mul#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(5)} -pin  "FRAME:mul#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(6)} -pin  "FRAME:mul#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(7)} -pin  "FRAME:mul#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(8)} -pin  "FRAME:mul#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load inst "FRAME:not#49" "not(1)" "INTERFACE" -attr xrf 1915 -attr oid 300 -attr @path {/sobel/sobel:core/FRAME:not#49} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#55.psp(4)} -pin  "FRAME:not#49" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#55.psp)#6.itm}
+load net {FRAME:not#49.itm} -pin  "FRAME:not#49" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#49.itm}
+load inst "FRAME:not#24" "not(3)" "INTERFACE" -attr xrf 1916 -attr oid 301 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#24} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {FRAME:acc#55.psp(2)} -pin  "FRAME:not#24" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#55.psp)#2.itm}
+load net {FRAME:acc#55.psp(3)} -pin  "FRAME:not#24" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#55.psp)#2.itm}
+load net {FRAME:acc#55.psp(4)} -pin  "FRAME:not#24" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#55.psp)#2.itm}
+load net {FRAME:not#24.itm(0)} -pin  "FRAME:not#24" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#24.itm}
+load net {FRAME:not#24.itm(1)} -pin  "FRAME:not#24" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#24.itm}
+load net {FRAME:not#24.itm(2)} -pin  "FRAME:not#24" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#24.itm}
+load inst "FRAME:not#45" "not(1)" "INTERFACE" -attr xrf 1917 -attr oid 302 -attr @path {/sobel/sobel:core/FRAME:not#45} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#55.psp(4)} -pin  "FRAME:not#45" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#55.psp)#4.itm}
+load net {FRAME:not#45.itm} -pin  "FRAME:not#45" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#45.itm}
+load inst "FRAME:acc#39" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 1918 -attr oid 303 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "FRAME:acc#39" {A(0)} -attr @path {/sobel/sobel:core/conc#127.itm}
+load net {FRAME:acc#31.sdt(0)} -pin  "FRAME:acc#39" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#127.itm}
+load net {FRAME:acc#55.psp(0)} -pin  "FRAME:acc#39" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#127.itm}
+load net {FRAME:acc#55.psp(1)} -pin  "FRAME:acc#39" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#127.itm}
+load net {PWR} -pin  "FRAME:acc#39" {A(4)} -attr @path {/sobel/sobel:core/conc#127.itm}
+load net {FRAME:not#45.itm} -pin  "FRAME:acc#39" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#46.itm}
+load net {FRAME:not#24.itm(0)} -pin  "FRAME:acc#39" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#46.itm}
+load net {FRAME:not#24.itm(1)} -pin  "FRAME:acc#39" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#46.itm}
+load net {FRAME:not#24.itm(2)} -pin  "FRAME:acc#39" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#46.itm}
+load net {FRAME:acc#39.itm(0)} -pin  "FRAME:acc#39" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(1)} -pin  "FRAME:acc#39" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(2)} -pin  "FRAME:acc#39" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(3)} -pin  "FRAME:acc#39" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(4)} -pin  "FRAME:acc#39" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load inst "FRAME:not#54" "not(1)" "INTERFACE" -attr xrf 1919 -attr oid 304 -attr @path {/sobel/sobel:core/FRAME:not#54} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#39.itm(4)} -pin  "FRAME:not#54" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#6.itm}
+load net {FRAME:not#54.itm} -pin  "FRAME:not#54" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#54.itm}
+load inst "FRAME:acc#32" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 1920 -attr oid 305 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#54.itm} -pin  "FRAME:acc#32" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#126.itm}
+load net {PWR} -pin  "FRAME:acc#32" {A(1)} -attr @path {/sobel/sobel:core/conc#126.itm}
+load net {FRAME:not#49.itm} -pin  "FRAME:acc#32" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#126.itm}
+load net {FRAME:acc#55.psp(2)} -pin  "FRAME:acc#32" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#55.psp)#3.itm}
+load net {FRAME:acc#55.psp(3)} -pin  "FRAME:acc#32" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#55.psp)#3.itm}
+load net {FRAME:acc#32.itm(0)} -pin  "FRAME:acc#32" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(1)} -pin  "FRAME:acc#32" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(2)} -pin  "FRAME:acc#32" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(3)} -pin  "FRAME:acc#32" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load inst "FRAME:not#25" "not(3)" "INTERFACE" -attr xrf 1921 -attr oid 306 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#43.psp.sva(6)} -pin  "FRAME:not#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#6.itm}
+load net {ACC1:acc#43.psp.sva(7)} -pin  "FRAME:not#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#6.itm}
+load net {ACC1:acc#43.psp.sva(8)} -pin  "FRAME:not#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#6.itm}
+load net {FRAME:not#25.itm(0)} -pin  "FRAME:not#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:not#25.itm(1)} -pin  "FRAME:not#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:not#25.itm(2)} -pin  "FRAME:not#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load inst "FRAME:acc#33" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 1922 -attr oid 307 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#32.itm(0)} -pin  "FRAME:acc#33" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(1)} -pin  "FRAME:acc#33" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(2)} -pin  "FRAME:acc#33" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(3)} -pin  "FRAME:acc#33" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:not#25.itm(0)} -pin  "FRAME:acc#33" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:not#25.itm(1)} -pin  "FRAME:acc#33" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:not#25.itm(2)} -pin  "FRAME:acc#33" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:acc#33.itm(0)} -pin  "FRAME:acc#33" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(1)} -pin  "FRAME:acc#33" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(2)} -pin  "FRAME:acc#33" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(3)} -pin  "FRAME:acc#33" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(4)} -pin  "FRAME:acc#33" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load inst "FRAME:acc#34" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 1923 -attr oid 308 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {FRAME:acc#33.itm(0)} -pin  "FRAME:acc#34" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(1)} -pin  "FRAME:acc#34" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(2)} -pin  "FRAME:acc#34" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(3)} -pin  "FRAME:acc#34" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(4)} -pin  "FRAME:acc#34" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#55.psp(4)} -pin  "FRAME:acc#34" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {PWR} -pin  "FRAME:acc#34" {B(1)} -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {GND} -pin  "FRAME:acc#34" {B(2)} -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {GND} -pin  "FRAME:acc#34" {B(3)} -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {PWR} -pin  "FRAME:acc#34" {B(4)} -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {FRAME:acc#34.itm(0)} -pin  "FRAME:acc#34" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(1)} -pin  "FRAME:acc#34" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(2)} -pin  "FRAME:acc#34" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(3)} -pin  "FRAME:acc#34" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(4)} -pin  "FRAME:acc#34" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load inst "FRAME:acc#35" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 1924 -attr oid 309 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {ACC1:acc#43.psp.sva(3)} -pin  "FRAME:acc#35" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#5.itm}
+load net {ACC1:acc#43.psp.sva(4)} -pin  "FRAME:acc#35" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#5.itm}
+load net {ACC1:acc#43.psp.sva(5)} -pin  "FRAME:acc#35" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#5.itm}
+load net {ACC1:acc#43.psp.sva(6)} -pin  "FRAME:acc#35" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#5.itm}
+load net {ACC1:acc#43.psp.sva(7)} -pin  "FRAME:acc#35" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#5.itm}
+load net {ACC1:acc#43.psp.sva(8)} -pin  "FRAME:acc#35" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#5.itm}
+load net {FRAME:acc#34.itm(0)} -pin  "FRAME:acc#35" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(1)} -pin  "FRAME:acc#35" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(2)} -pin  "FRAME:acc#35" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(3)} -pin  "FRAME:acc#35" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(4)} -pin  "FRAME:acc#35" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#35.itm(0)} -pin  "FRAME:acc#35" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(1)} -pin  "FRAME:acc#35" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(2)} -pin  "FRAME:acc#35" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(3)} -pin  "FRAME:acc#35" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(4)} -pin  "FRAME:acc#35" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(5)} -pin  "FRAME:acc#35" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(6)} -pin  "FRAME:acc#35" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(7)} -pin  "FRAME:acc#35" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load inst "FRAME:acc#36" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 1925 -attr oid 310 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul#5.itm(0)} -pin  "FRAME:acc#36" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(1)} -pin  "FRAME:acc#36" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(2)} -pin  "FRAME:acc#36" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(3)} -pin  "FRAME:acc#36" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(4)} -pin  "FRAME:acc#36" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(5)} -pin  "FRAME:acc#36" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(6)} -pin  "FRAME:acc#36" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(7)} -pin  "FRAME:acc#36" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(8)} -pin  "FRAME:acc#36" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:acc#35.itm(0)} -pin  "FRAME:acc#36" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(1)} -pin  "FRAME:acc#36" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(2)} -pin  "FRAME:acc#36" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(3)} -pin  "FRAME:acc#36" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(4)} -pin  "FRAME:acc#36" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(5)} -pin  "FRAME:acc#36" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(6)} -pin  "FRAME:acc#36" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(7)} -pin  "FRAME:acc#36" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#36.itm(0)} -pin  "FRAME:acc#36" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(1)} -pin  "FRAME:acc#36" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(2)} -pin  "FRAME:acc#36" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(3)} -pin  "FRAME:acc#36" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(4)} -pin  "FRAME:acc#36" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(5)} -pin  "FRAME:acc#36" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(6)} -pin  "FRAME:acc#36" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(7)} -pin  "FRAME:acc#36" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(8)} -pin  "FRAME:acc#36" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(9)} -pin  "FRAME:acc#36" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load inst "FRAME:acc#37" "add(11,0,10,1,12)" "INTERFACE" -attr xrf 1926 -attr oid 311 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12)"
+load net {FRAME:mul#4.itm(0)} -pin  "FRAME:acc#37" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(1)} -pin  "FRAME:acc#37" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(2)} -pin  "FRAME:acc#37" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(3)} -pin  "FRAME:acc#37" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(4)} -pin  "FRAME:acc#37" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(5)} -pin  "FRAME:acc#37" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(6)} -pin  "FRAME:acc#37" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(7)} -pin  "FRAME:acc#37" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(8)} -pin  "FRAME:acc#37" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(9)} -pin  "FRAME:acc#37" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(10)} -pin  "FRAME:acc#37" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:acc#36.itm(0)} -pin  "FRAME:acc#37" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(1)} -pin  "FRAME:acc#37" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(2)} -pin  "FRAME:acc#37" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(3)} -pin  "FRAME:acc#37" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(4)} -pin  "FRAME:acc#37" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(5)} -pin  "FRAME:acc#37" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(6)} -pin  "FRAME:acc#37" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(7)} -pin  "FRAME:acc#37" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(8)} -pin  "FRAME:acc#37" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(9)} -pin  "FRAME:acc#37" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#37.sdt(0)} -pin  "FRAME:acc#37" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.sdt}
+load net {FRAME:acc#37.sdt(1)} -pin  "FRAME:acc#37" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.sdt}
+load net {FRAME:acc#37.sdt(2)} -pin  "FRAME:acc#37" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.sdt}
+load net {FRAME:acc#37.sdt(3)} -pin  "FRAME:acc#37" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.sdt}
+load net {FRAME:acc#37.sdt(4)} -pin  "FRAME:acc#37" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.sdt}
+load net {FRAME:acc#37.sdt(5)} -pin  "FRAME:acc#37" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.sdt}
+load net {FRAME:acc#37.sdt(6)} -pin  "FRAME:acc#37" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.sdt}
+load net {FRAME:acc#37.sdt(7)} -pin  "FRAME:acc#37" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.sdt}
+load net {FRAME:acc#37.sdt(8)} -pin  "FRAME:acc#37" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.sdt}
+load net {FRAME:acc#37.sdt(9)} -pin  "FRAME:acc#37" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.sdt}
+load net {FRAME:acc#37.sdt(10)} -pin  "FRAME:acc#37" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.sdt}
+load net {FRAME:acc#37.sdt(11)} -pin  "FRAME:acc#37" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.sdt}
+load inst "FRAME:acc#47" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 1927 -attr oid 312 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#47} -attr area 6.285690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {FRAME:acc#13.sdt(1)} -pin  "FRAME:acc#47" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#13.sdt)#1.itm}
+load net {FRAME:acc#13.sdt(2)} -pin  "FRAME:acc#47" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#13.sdt)#1.itm}
+load net {FRAME:acc#13.sdt(3)} -pin  "FRAME:acc#47" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#13.sdt)#1.itm}
+load net {FRAME:acc#13.sdt(4)} -pin  "FRAME:acc#47" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#13.sdt)#1.itm}
+load net {FRAME:acc#13.sdt(5)} -pin  "FRAME:acc#47" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#13.sdt)#1.itm}
+load net {PWR} -pin  "FRAME:acc#47" {B(0)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {GND} -pin  "FRAME:acc#47" {B(1)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {PWR} -pin  "FRAME:acc#47" {B(2)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {GND} -pin  "FRAME:acc#47" {B(3)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {PWR} -pin  "FRAME:acc#47" {B(4)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {FRAME:acc#47.psp(0)} -pin  "FRAME:acc#47" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#47.psp}
+load net {FRAME:acc#47.psp(1)} -pin  "FRAME:acc#47" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#47.psp}
+load net {FRAME:acc#47.psp(2)} -pin  "FRAME:acc#47" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#47.psp}
+load net {FRAME:acc#47.psp(3)} -pin  "FRAME:acc#47" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#47.psp}
+load net {FRAME:acc#47.psp(4)} -pin  "FRAME:acc#47" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#47.psp}
+load inst "FRAME:not#31" "not(3)" "INTERFACE" -attr xrf 1928 -attr oid 313 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#31} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.psp.sva(9)} -pin  "FRAME:not#31" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#6.itm}
+load net {ACC1:acc.psp.sva(10)} -pin  "FRAME:not#31" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#6.itm}
+load net {ACC1:acc.psp.sva(11)} -pin  "FRAME:not#31" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#6.itm}
+load net {FRAME:not#31.itm(0)} -pin  "FRAME:not#31" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#31.itm}
+load net {FRAME:not#31.itm(1)} -pin  "FRAME:not#31" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#31.itm}
+load net {FRAME:not#31.itm(2)} -pin  "FRAME:not#31" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#31.itm}
+load inst "FRAME:acc#10" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 1929 -attr oid 314 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc.psp.sva(6)} -pin  "FRAME:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#4.itm}
+load net {ACC1:acc.psp.sva(7)} -pin  "FRAME:acc#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#4.itm}
+load net {ACC1:acc.psp.sva(8)} -pin  "FRAME:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#4.itm}
+load net {FRAME:not#31.itm(0)} -pin  "FRAME:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#31.itm}
+load net {FRAME:not#31.itm(1)} -pin  "FRAME:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#31.itm}
+load net {FRAME:not#31.itm(2)} -pin  "FRAME:acc#10" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#31.itm}
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load inst "FRAME:not#32" "not(1)" "INTERFACE" -attr xrf 1930 -attr oid 315 -attr @path {/sobel/sobel:core/FRAME:not#32} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc.psp.sva(12)} -pin  "FRAME:not#32" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#2.itm}
+load net {FRAME:not#32.itm} -pin  "FRAME:not#32" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#32.itm}
+load inst "FRAME:not#40" "not(3)" "INTERFACE" -attr xrf 1931 -attr oid 316 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#40} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.psp.sva(3)} -pin  "FRAME:not#40" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#3.itm}
+load net {ACC1:acc.psp.sva(4)} -pin  "FRAME:not#40" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#3.itm}
+load net {ACC1:acc.psp.sva(5)} -pin  "FRAME:not#40" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#3.itm}
+load net {FRAME:not#40.itm(0)} -pin  "FRAME:not#40" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#40.itm}
+load net {FRAME:not#40.itm(1)} -pin  "FRAME:not#40" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#40.itm}
+load net {FRAME:not#40.itm(2)} -pin  "FRAME:not#40" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#40.itm}
+load inst "FRAME:acc#12" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 1932 -attr oid 317 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:not#40.itm(0)} -pin  "FRAME:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34.itm}
+load net {FRAME:not#40.itm(1)} -pin  "FRAME:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34.itm}
+load net {FRAME:not#40.itm(2)} -pin  "FRAME:acc#12" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34.itm}
+load net {FRAME:not#32.itm} -pin  "FRAME:acc#12" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(4)} -pin  "FRAME:acc#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load inst "FRAME:acc#11" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 1933 -attr oid 318 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc.psp.sva(12)} -pin  "FRAME:acc#11" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {GND} -pin  "FRAME:acc#11" {A(1)} -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {ACC1:acc.psp.sva(12)} -pin  "FRAME:acc#11" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {ACC1:acc.psp.sva(0)} -pin  "FRAME:acc#11" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#7.itm}
+load net {ACC1:acc.psp.sva(1)} -pin  "FRAME:acc#11" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#7.itm}
+load net {ACC1:acc.psp.sva(2)} -pin  "FRAME:acc#11" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#7.itm}
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#11" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#11" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#11" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#11" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load inst "FRAME:acc#13" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 1934 -attr oid 319 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#13" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(4)} -pin  "FRAME:acc#13" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#13" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#13" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#13" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#13" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#13.sdt(0)} -pin  "FRAME:acc#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.sdt}
+load net {FRAME:acc#13.sdt(1)} -pin  "FRAME:acc#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.sdt}
+load net {FRAME:acc#13.sdt(2)} -pin  "FRAME:acc#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.sdt}
+load net {FRAME:acc#13.sdt(3)} -pin  "FRAME:acc#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.sdt}
+load net {FRAME:acc#13.sdt(4)} -pin  "FRAME:acc#13" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.sdt}
+load net {FRAME:acc#13.sdt(5)} -pin  "FRAME:acc#13" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.sdt}
+load inst "ACC1:acc#53" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 1935 -attr oid 320 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#53" {A(0)} -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(0)} -pin  "ACC1:acc#53" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(1)} -pin  "ACC1:acc#53" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(2)} -pin  "ACC1:acc#53" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(3)} -pin  "ACC1:acc#53" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(4)} -pin  "ACC1:acc#53" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(5)} -pin  "ACC1:acc#53" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(6)} -pin  "ACC1:acc#53" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(7)} -pin  "ACC1:acc#53" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(8)} -pin  "ACC1:acc#53" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {ACC1:slc(regs.regs(2))#14.itm(9)} -pin  "ACC1:acc#53" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {PWR} -pin  "ACC1:acc#53" {B(0)} -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(0)} -pin  "ACC1:acc#53" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(1)} -pin  "ACC1:acc#53" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(2)} -pin  "ACC1:acc#53" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(3)} -pin  "ACC1:acc#53" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(4)} -pin  "ACC1:acc#53" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(5)} -pin  "ACC1:acc#53" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(6)} -pin  "ACC1:acc#53" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(7)} -pin  "ACC1:acc#53" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(8)} -pin  "ACC1:acc#53" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {ACC1:slc(regs.regs(2))#15.itm(9)} -pin  "ACC1:acc#53" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {ACC1:acc#53.itm(0)} -pin  "ACC1:acc#53" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53.itm}
+load net {ACC1:acc#53.itm(1)} -pin  "ACC1:acc#53" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53.itm}
+load net {ACC1:acc#53.itm(2)} -pin  "ACC1:acc#53" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53.itm}
+load net {ACC1:acc#53.itm(3)} -pin  "ACC1:acc#53" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53.itm}
+load net {ACC1:acc#53.itm(4)} -pin  "ACC1:acc#53" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53.itm}
+load net {ACC1:acc#53.itm(5)} -pin  "ACC1:acc#53" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53.itm}
+load net {ACC1:acc#53.itm(6)} -pin  "ACC1:acc#53" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53.itm}
+load net {ACC1:acc#53.itm(7)} -pin  "ACC1:acc#53" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53.itm}
+load net {ACC1:acc#53.itm(8)} -pin  "ACC1:acc#53" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53.itm}
+load net {ACC1:acc#53.itm(9)} -pin  "ACC1:acc#53" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53.itm}
+load net {ACC1:acc#53.itm(10)} -pin  "ACC1:acc#53" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53.itm}
+load net {ACC1:acc#53.itm(11)} -pin  "ACC1:acc#53" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#53.itm}
+load inst "ACC1:not#25" "not(10)" "INTERFACE" -attr xrf 1936 -attr oid 321 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#25} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "ACC1:not#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "ACC1:not#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "ACC1:not#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "ACC1:not#25" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "ACC1:not#25" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "ACC1:not#25" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "ACC1:not#25" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "ACC1:not#25" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "ACC1:not#25" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:not#25" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {ACC1:not#25.itm(0)} -pin  "ACC1:not#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#25.itm}
+load net {ACC1:not#25.itm(1)} -pin  "ACC1:not#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#25.itm}
+load net {ACC1:not#25.itm(2)} -pin  "ACC1:not#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#25.itm}
+load net {ACC1:not#25.itm(3)} -pin  "ACC1:not#25" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#25.itm}
+load net {ACC1:not#25.itm(4)} -pin  "ACC1:not#25" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#25.itm}
+load net {ACC1:not#25.itm(5)} -pin  "ACC1:not#25" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#25.itm}
+load net {ACC1:not#25.itm(6)} -pin  "ACC1:not#25" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#25.itm}
+load net {ACC1:not#25.itm(7)} -pin  "ACC1:not#25" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#25.itm}
+load net {ACC1:not#25.itm(8)} -pin  "ACC1:not#25" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#25.itm}
+load net {ACC1:not#25.itm(9)} -pin  "ACC1:not#25" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#25.itm}
+load inst "ACC1:not#26" "not(10)" "INTERFACE" -attr xrf 1937 -attr oid 322 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#26} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "ACC1:not#26" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "ACC1:not#26" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "ACC1:not#26" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "ACC1:not#26" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "ACC1:not#26" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "ACC1:not#26" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "ACC1:not#26" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "ACC1:not#26" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "ACC1:not#26" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:not#26" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {ACC1:not#26.itm(0)} -pin  "ACC1:not#26" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#26.itm}
+load net {ACC1:not#26.itm(1)} -pin  "ACC1:not#26" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#26.itm}
+load net {ACC1:not#26.itm(2)} -pin  "ACC1:not#26" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#26.itm}
+load net {ACC1:not#26.itm(3)} -pin  "ACC1:not#26" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#26.itm}
+load net {ACC1:not#26.itm(4)} -pin  "ACC1:not#26" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#26.itm}
+load net {ACC1:not#26.itm(5)} -pin  "ACC1:not#26" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#26.itm}
+load net {ACC1:not#26.itm(6)} -pin  "ACC1:not#26" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#26.itm}
+load net {ACC1:not#26.itm(7)} -pin  "ACC1:not#26" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#26.itm}
+load net {ACC1:not#26.itm(8)} -pin  "ACC1:not#26" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#26.itm}
+load net {ACC1:not#26.itm(9)} -pin  "ACC1:not#26" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#26.itm}
+load inst "ACC1:acc#52" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 1938 -attr oid 323 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#52" {A(0)} -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {ACC1:not#25.itm(0)} -pin  "ACC1:acc#52" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {ACC1:not#25.itm(1)} -pin  "ACC1:acc#52" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {ACC1:not#25.itm(2)} -pin  "ACC1:acc#52" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {ACC1:not#25.itm(3)} -pin  "ACC1:acc#52" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {ACC1:not#25.itm(4)} -pin  "ACC1:acc#52" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {ACC1:not#25.itm(5)} -pin  "ACC1:acc#52" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {ACC1:not#25.itm(6)} -pin  "ACC1:acc#52" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {ACC1:not#25.itm(7)} -pin  "ACC1:acc#52" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {ACC1:not#25.itm(8)} -pin  "ACC1:acc#52" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {ACC1:not#25.itm(9)} -pin  "ACC1:acc#52" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {PWR} -pin  "ACC1:acc#52" {B(0)} -attr @path {/sobel/sobel:core/conc#135.itm}
+load net {ACC1:not#26.itm(0)} -pin  "ACC1:acc#52" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#135.itm}
+load net {ACC1:not#26.itm(1)} -pin  "ACC1:acc#52" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#135.itm}
+load net {ACC1:not#26.itm(2)} -pin  "ACC1:acc#52" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#135.itm}
+load net {ACC1:not#26.itm(3)} -pin  "ACC1:acc#52" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#135.itm}
+load net {ACC1:not#26.itm(4)} -pin  "ACC1:acc#52" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#135.itm}
+load net {ACC1:not#26.itm(5)} -pin  "ACC1:acc#52" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#135.itm}
+load net {ACC1:not#26.itm(6)} -pin  "ACC1:acc#52" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#135.itm}
+load net {ACC1:not#26.itm(7)} -pin  "ACC1:acc#52" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#135.itm}
+load net {ACC1:not#26.itm(8)} -pin  "ACC1:acc#52" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#135.itm}
+load net {ACC1:not#26.itm(9)} -pin  "ACC1:acc#52" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#135.itm}
+load net {ACC1:acc#52.itm(0)} -pin  "ACC1:acc#52" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(1)} -pin  "ACC1:acc#52" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(2)} -pin  "ACC1:acc#52" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(3)} -pin  "ACC1:acc#52" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(4)} -pin  "ACC1:acc#52" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(5)} -pin  "ACC1:acc#52" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(6)} -pin  "ACC1:acc#52" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(7)} -pin  "ACC1:acc#52" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(8)} -pin  "ACC1:acc#52" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(9)} -pin  "ACC1:acc#52" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(10)} -pin  "ACC1:acc#52" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "ACC1:acc#52" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load inst "ACC1:acc#55" "add(12,1,12,1,13)" "INTERFACE" -attr xrf 1939 -attr oid 324 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {PWR} -pin  "ACC1:acc#55" {A(0)} -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {ACC1:acc#53.itm(1)} -pin  "ACC1:acc#55" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {ACC1:acc#53.itm(2)} -pin  "ACC1:acc#55" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {ACC1:acc#53.itm(3)} -pin  "ACC1:acc#55" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {ACC1:acc#53.itm(4)} -pin  "ACC1:acc#55" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {ACC1:acc#53.itm(5)} -pin  "ACC1:acc#55" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {ACC1:acc#53.itm(6)} -pin  "ACC1:acc#55" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {ACC1:acc#53.itm(7)} -pin  "ACC1:acc#55" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {ACC1:acc#53.itm(8)} -pin  "ACC1:acc#55" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {ACC1:acc#53.itm(9)} -pin  "ACC1:acc#55" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {ACC1:acc#53.itm(10)} -pin  "ACC1:acc#55" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {ACC1:acc#53.itm(11)} -pin  "ACC1:acc#55" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {PWR} -pin  "ACC1:acc#55" {B(0)} -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {ACC1:acc#52.itm(1)} -pin  "ACC1:acc#55" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {ACC1:acc#52.itm(2)} -pin  "ACC1:acc#55" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {ACC1:acc#52.itm(3)} -pin  "ACC1:acc#55" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {ACC1:acc#52.itm(4)} -pin  "ACC1:acc#55" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {ACC1:acc#52.itm(5)} -pin  "ACC1:acc#55" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {ACC1:acc#52.itm(6)} -pin  "ACC1:acc#55" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {ACC1:acc#52.itm(7)} -pin  "ACC1:acc#55" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {ACC1:acc#52.itm(8)} -pin  "ACC1:acc#55" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {ACC1:acc#52.itm(9)} -pin  "ACC1:acc#55" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {ACC1:acc#52.itm(10)} -pin  "ACC1:acc#55" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "ACC1:acc#55" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {ACC1:acc#55.itm(0)} -pin  "ACC1:acc#55" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load net {ACC1:acc#55.itm(1)} -pin  "ACC1:acc#55" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load net {ACC1:acc#55.itm(2)} -pin  "ACC1:acc#55" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load net {ACC1:acc#55.itm(3)} -pin  "ACC1:acc#55" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load net {ACC1:acc#55.itm(4)} -pin  "ACC1:acc#55" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load net {ACC1:acc#55.itm(5)} -pin  "ACC1:acc#55" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load net {ACC1:acc#55.itm(6)} -pin  "ACC1:acc#55" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load net {ACC1:acc#55.itm(7)} -pin  "ACC1:acc#55" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load net {ACC1:acc#55.itm(8)} -pin  "ACC1:acc#55" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load net {ACC1:acc#55.itm(9)} -pin  "ACC1:acc#55" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load net {ACC1:acc#55.itm(10)} -pin  "ACC1:acc#55" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load net {ACC1:acc#55.itm(11)} -pin  "ACC1:acc#55" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load net {ACC1:acc#55.itm(12)} -pin  "ACC1:acc#55" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#55.itm}
+load inst "ACC1:not#27" "not(10)" "INTERFACE" -attr xrf 1940 -attr oid 325 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "ACC1:not#27" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "ACC1:not#27" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "ACC1:not#27" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "ACC1:not#27" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "ACC1:not#27" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "ACC1:not#27" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "ACC1:not#27" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "ACC1:not#27" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "ACC1:not#27" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "ACC1:not#27" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {ACC1:not#27.itm(0)} -pin  "ACC1:not#27" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(1)} -pin  "ACC1:not#27" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(2)} -pin  "ACC1:not#27" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(3)} -pin  "ACC1:not#27" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(4)} -pin  "ACC1:not#27" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(5)} -pin  "ACC1:not#27" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(6)} -pin  "ACC1:not#27" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(7)} -pin  "ACC1:not#27" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(8)} -pin  "ACC1:not#27" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(9)} -pin  "ACC1:not#27" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load inst "ACC1:acc#58" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 1941 -attr oid 326 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58} -attr area 11.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:slc(regs.regs(2))#16.itm(0)} -pin  "ACC1:acc#58" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(1)} -pin  "ACC1:acc#58" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(2)} -pin  "ACC1:acc#58" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(3)} -pin  "ACC1:acc#58" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(4)} -pin  "ACC1:acc#58" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(5)} -pin  "ACC1:acc#58" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(6)} -pin  "ACC1:acc#58" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(7)} -pin  "ACC1:acc#58" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(8)} -pin  "ACC1:acc#58" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:slc(regs.regs(2))#16.itm(9)} -pin  "ACC1:acc#58" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#16.itm}
+load net {ACC1:not#27.itm(0)} -pin  "ACC1:acc#58" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(1)} -pin  "ACC1:acc#58" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(2)} -pin  "ACC1:acc#58" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(3)} -pin  "ACC1:acc#58" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(4)} -pin  "ACC1:acc#58" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(5)} -pin  "ACC1:acc#58" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(6)} -pin  "ACC1:acc#58" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(7)} -pin  "ACC1:acc#58" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(8)} -pin  "ACC1:acc#58" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:not#27.itm(9)} -pin  "ACC1:acc#58" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#27.itm}
+load net {ACC1:acc#58.itm(0)} -pin  "ACC1:acc#58" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load net {ACC1:acc#58.itm(1)} -pin  "ACC1:acc#58" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load net {ACC1:acc#58.itm(2)} -pin  "ACC1:acc#58" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load net {ACC1:acc#58.itm(3)} -pin  "ACC1:acc#58" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load net {ACC1:acc#58.itm(4)} -pin  "ACC1:acc#58" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load net {ACC1:acc#58.itm(5)} -pin  "ACC1:acc#58" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load net {ACC1:acc#58.itm(6)} -pin  "ACC1:acc#58" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load net {ACC1:acc#58.itm(7)} -pin  "ACC1:acc#58" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load net {ACC1:acc#58.itm(8)} -pin  "ACC1:acc#58" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load net {ACC1:acc#58.itm(9)} -pin  "ACC1:acc#58" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load net {ACC1:acc#58.itm(10)} -pin  "ACC1:acc#58" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load inst "ACC1:acc#43" "add(12,1,12,1,13)" "INTERFACE" -attr xrf 1942 -attr oid 327 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1:acc#55.itm(1)} -pin  "ACC1:acc#43" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#55.itm(2)} -pin  "ACC1:acc#43" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#55.itm(3)} -pin  "ACC1:acc#43" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#55.itm(4)} -pin  "ACC1:acc#43" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#55.itm(5)} -pin  "ACC1:acc#43" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#55.itm(6)} -pin  "ACC1:acc#43" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#55.itm(7)} -pin  "ACC1:acc#43" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#55.itm(8)} -pin  "ACC1:acc#43" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#55.itm(9)} -pin  "ACC1:acc#43" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#55.itm(10)} -pin  "ACC1:acc#43" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#55.itm(11)} -pin  "ACC1:acc#43" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#55.itm(12)} -pin  "ACC1:acc#43" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {PWR} -pin  "ACC1:acc#43" {B(0)} -attr @path {/sobel/sobel:core/conc#136.itm}
+load net {ACC1:acc#58.itm(0)} -pin  "ACC1:acc#43" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#136.itm}
+load net {ACC1:acc#58.itm(1)} -pin  "ACC1:acc#43" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#136.itm}
+load net {ACC1:acc#58.itm(2)} -pin  "ACC1:acc#43" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#136.itm}
+load net {ACC1:acc#58.itm(3)} -pin  "ACC1:acc#43" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#136.itm}
+load net {ACC1:acc#58.itm(4)} -pin  "ACC1:acc#43" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#136.itm}
+load net {ACC1:acc#58.itm(5)} -pin  "ACC1:acc#43" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#136.itm}
+load net {ACC1:acc#58.itm(6)} -pin  "ACC1:acc#43" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#136.itm}
+load net {ACC1:acc#58.itm(7)} -pin  "ACC1:acc#43" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#136.itm}
+load net {ACC1:acc#58.itm(8)} -pin  "ACC1:acc#43" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#136.itm}
+load net {ACC1:acc#58.itm(9)} -pin  "ACC1:acc#43" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#136.itm}
+load net {ACC1:acc#58.itm(10)} -pin  "ACC1:acc#43" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#136.itm}
+load net {ACC1:acc#43.psp.sva(0)} -pin  "ACC1:acc#43" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load net {ACC1:acc#43.psp.sva(1)} -pin  "ACC1:acc#43" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load net {ACC1:acc#43.psp.sva(2)} -pin  "ACC1:acc#43" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load net {ACC1:acc#43.psp.sva(3)} -pin  "ACC1:acc#43" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load net {ACC1:acc#43.psp.sva(4)} -pin  "ACC1:acc#43" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load net {ACC1:acc#43.psp.sva(5)} -pin  "ACC1:acc#43" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load net {ACC1:acc#43.psp.sva(6)} -pin  "ACC1:acc#43" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load net {ACC1:acc#43.psp.sva(7)} -pin  "ACC1:acc#43" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load net {ACC1:acc#43.psp.sva(8)} -pin  "ACC1:acc#43" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load net {ACC1:acc#43.psp.sva(9)} -pin  "ACC1:acc#43" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load net {ACC1:acc#43.psp.sva(10)} -pin  "ACC1:acc#43" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load net {ACC1:acc#43.psp.sva(11)} -pin  "ACC1:acc#43" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load net {ACC1:acc#43.psp.sva(12)} -pin  "ACC1:acc#43" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.psp.sva}
+load inst "FRAME:acc#55" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 1943 -attr oid 328 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#55} -attr area 6.285690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {FRAME:acc#31.sdt(1)} -pin  "FRAME:acc#55" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#31.sdt)#1.itm}
+load net {FRAME:acc#31.sdt(2)} -pin  "FRAME:acc#55" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#31.sdt)#1.itm}
+load net {FRAME:acc#31.sdt(3)} -pin  "FRAME:acc#55" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#31.sdt)#1.itm}
+load net {FRAME:acc#31.sdt(4)} -pin  "FRAME:acc#55" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#31.sdt)#1.itm}
+load net {FRAME:acc#31.sdt(5)} -pin  "FRAME:acc#55" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#31.sdt)#1.itm}
+load net {PWR} -pin  "FRAME:acc#55" {B(0)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {GND} -pin  "FRAME:acc#55" {B(1)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {PWR} -pin  "FRAME:acc#55" {B(2)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {GND} -pin  "FRAME:acc#55" {B(3)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {PWR} -pin  "FRAME:acc#55" {B(4)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {FRAME:acc#55.psp(0)} -pin  "FRAME:acc#55" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#55.psp}
+load net {FRAME:acc#55.psp(1)} -pin  "FRAME:acc#55" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#55.psp}
+load net {FRAME:acc#55.psp(2)} -pin  "FRAME:acc#55" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#55.psp}
+load net {FRAME:acc#55.psp(3)} -pin  "FRAME:acc#55" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#55.psp}
+load net {FRAME:acc#55.psp(4)} -pin  "FRAME:acc#55" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#55.psp}
+load inst "FRAME:not#35" "not(3)" "INTERFACE" -attr xrf 1944 -attr oid 329 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#35} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#43.psp.sva(9)} -pin  "FRAME:not#35" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#8.itm}
+load net {ACC1:acc#43.psp.sva(10)} -pin  "FRAME:not#35" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#8.itm}
+load net {ACC1:acc#43.psp.sva(11)} -pin  "FRAME:not#35" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#8.itm}
+load net {FRAME:not#35.itm(0)} -pin  "FRAME:not#35" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#35.itm}
+load net {FRAME:not#35.itm(1)} -pin  "FRAME:not#35" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#35.itm}
+load net {FRAME:not#35.itm(2)} -pin  "FRAME:not#35" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#35.itm}
+load inst "FRAME:acc#28" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 1945 -attr oid 330 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#43.psp.sva(6)} -pin  "FRAME:acc#28" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#7.itm}
+load net {ACC1:acc#43.psp.sva(7)} -pin  "FRAME:acc#28" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#7.itm}
+load net {ACC1:acc#43.psp.sva(8)} -pin  "FRAME:acc#28" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#7.itm}
+load net {FRAME:not#35.itm(0)} -pin  "FRAME:acc#28" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#35.itm}
+load net {FRAME:not#35.itm(1)} -pin  "FRAME:acc#28" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#35.itm}
+load net {FRAME:not#35.itm(2)} -pin  "FRAME:acc#28" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#35.itm}
+load net {FRAME:acc#28.itm(0)} -pin  "FRAME:acc#28" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(1)} -pin  "FRAME:acc#28" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(2)} -pin  "FRAME:acc#28" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(3)} -pin  "FRAME:acc#28" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load inst "FRAME:not#36" "not(1)" "INTERFACE" -attr xrf 1946 -attr oid 331 -attr @path {/sobel/sobel:core/FRAME:not#36} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#43.psp.sva(12)} -pin  "FRAME:not#36" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#2.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:not#36" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#36.itm}
+load inst "FRAME:not#42" "not(3)" "INTERFACE" -attr xrf 1947 -attr oid 332 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#42} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#43.psp.sva(3)} -pin  "FRAME:not#42" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#9.itm}
+load net {ACC1:acc#43.psp.sva(4)} -pin  "FRAME:not#42" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#9.itm}
+load net {ACC1:acc#43.psp.sva(5)} -pin  "FRAME:not#42" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#9.itm}
+load net {FRAME:not#42.itm(0)} -pin  "FRAME:not#42" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#42.itm}
+load net {FRAME:not#42.itm(1)} -pin  "FRAME:not#42" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#42.itm}
+load net {FRAME:not#42.itm(2)} -pin  "FRAME:not#42" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#42.itm}
+load inst "FRAME:acc#30" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 1948 -attr oid 333 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#28.itm(0)} -pin  "FRAME:acc#30" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(1)} -pin  "FRAME:acc#30" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(2)} -pin  "FRAME:acc#30" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(3)} -pin  "FRAME:acc#30" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:not#42.itm(0)} -pin  "FRAME:acc#30" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:not#42.itm(1)} -pin  "FRAME:acc#30" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:not#42.itm(2)} -pin  "FRAME:acc#30" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:acc#30" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#30.itm(0)} -pin  "FRAME:acc#30" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(1)} -pin  "FRAME:acc#30" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(2)} -pin  "FRAME:acc#30" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(3)} -pin  "FRAME:acc#30" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(4)} -pin  "FRAME:acc#30" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load inst "FRAME:acc#29" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 1949 -attr oid 334 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#43.psp.sva(12)} -pin  "FRAME:acc#29" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:acc#29" {A(1)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {ACC1:acc#43.psp.sva(12)} -pin  "FRAME:acc#29" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {ACC1:acc#43.psp.sva(0)} -pin  "FRAME:acc#29" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#10.itm}
+load net {ACC1:acc#43.psp.sva(1)} -pin  "FRAME:acc#29" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#10.itm}
+load net {ACC1:acc#43.psp.sva(2)} -pin  "FRAME:acc#29" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#43.psp.sva)#10.itm}
+load net {FRAME:acc#29.itm(0)} -pin  "FRAME:acc#29" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(1)} -pin  "FRAME:acc#29" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(2)} -pin  "FRAME:acc#29" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(3)} -pin  "FRAME:acc#29" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load inst "FRAME:acc#31" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 1950 -attr oid 335 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#31} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {FRAME:acc#30.itm(0)} -pin  "FRAME:acc#31" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(1)} -pin  "FRAME:acc#31" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(2)} -pin  "FRAME:acc#31" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(3)} -pin  "FRAME:acc#31" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(4)} -pin  "FRAME:acc#31" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#29.itm(0)} -pin  "FRAME:acc#31" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(1)} -pin  "FRAME:acc#31" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(2)} -pin  "FRAME:acc#31" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(3)} -pin  "FRAME:acc#31" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#31.sdt(0)} -pin  "FRAME:acc#31" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#31.sdt}
+load net {FRAME:acc#31.sdt(1)} -pin  "FRAME:acc#31" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#31.sdt}
+load net {FRAME:acc#31.sdt(2)} -pin  "FRAME:acc#31" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#31.sdt}
+load net {FRAME:acc#31.sdt(3)} -pin  "FRAME:acc#31" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#31.sdt}
+load net {FRAME:acc#31.sdt(4)} -pin  "FRAME:acc#31" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#31.sdt}
+load net {FRAME:acc#31.sdt(5)} -pin  "FRAME:acc#31" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#31.sdt}
+load inst "ACC1:acc#49" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 1951 -attr oid 336 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#49} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#49" {A(0)} -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(0)} -pin  "ACC1:acc#49" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(1)} -pin  "ACC1:acc#49" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(2)} -pin  "ACC1:acc#49" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(3)} -pin  "ACC1:acc#49" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(4)} -pin  "ACC1:acc#49" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(5)} -pin  "ACC1:acc#49" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(6)} -pin  "ACC1:acc#49" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(7)} -pin  "ACC1:acc#49" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(8)} -pin  "ACC1:acc#49" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {ACC1:slc(regs.regs(2))#11.itm(9)} -pin  "ACC1:acc#49" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {PWR} -pin  "ACC1:acc#49" {B(0)} -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(0)} -pin  "ACC1:acc#49" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(1)} -pin  "ACC1:acc#49" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(2)} -pin  "ACC1:acc#49" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(3)} -pin  "ACC1:acc#49" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(4)} -pin  "ACC1:acc#49" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(5)} -pin  "ACC1:acc#49" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(6)} -pin  "ACC1:acc#49" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(7)} -pin  "ACC1:acc#49" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(8)} -pin  "ACC1:acc#49" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {ACC1:slc(regs.regs(2))#12.itm(9)} -pin  "ACC1:acc#49" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {ACC1:acc#49.itm(0)} -pin  "ACC1:acc#49" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(1)} -pin  "ACC1:acc#49" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(2)} -pin  "ACC1:acc#49" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(3)} -pin  "ACC1:acc#49" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(4)} -pin  "ACC1:acc#49" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(5)} -pin  "ACC1:acc#49" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(6)} -pin  "ACC1:acc#49" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(7)} -pin  "ACC1:acc#49" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(8)} -pin  "ACC1:acc#49" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(9)} -pin  "ACC1:acc#49" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(10)} -pin  "ACC1:acc#49" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "ACC1:acc#49" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load inst "ACC1:not#22" "not(10)" "INTERFACE" -attr xrf 1952 -attr oid 337 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#22} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "ACC1:not#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "ACC1:not#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "ACC1:not#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "ACC1:not#22" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "ACC1:not#22" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "ACC1:not#22" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "ACC1:not#22" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "ACC1:not#22" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "ACC1:not#22" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:not#22" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:not#22.itm(0)} -pin  "ACC1:not#22" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#22.itm}
+load net {ACC1:not#22.itm(1)} -pin  "ACC1:not#22" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#22.itm}
+load net {ACC1:not#22.itm(2)} -pin  "ACC1:not#22" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#22.itm}
+load net {ACC1:not#22.itm(3)} -pin  "ACC1:not#22" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#22.itm}
+load net {ACC1:not#22.itm(4)} -pin  "ACC1:not#22" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#22.itm}
+load net {ACC1:not#22.itm(5)} -pin  "ACC1:not#22" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#22.itm}
+load net {ACC1:not#22.itm(6)} -pin  "ACC1:not#22" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#22.itm}
+load net {ACC1:not#22.itm(7)} -pin  "ACC1:not#22" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#22.itm}
+load net {ACC1:not#22.itm(8)} -pin  "ACC1:not#22" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#22.itm}
+load net {ACC1:not#22.itm(9)} -pin  "ACC1:not#22" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#22.itm}
+load inst "ACC1:not#23" "not(10)" "INTERFACE" -attr xrf 1953 -attr oid 338 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#23} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "ACC1:not#23" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "ACC1:not#23" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "ACC1:not#23" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "ACC1:not#23" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "ACC1:not#23" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "ACC1:not#23" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "ACC1:not#23" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "ACC1:not#23" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "ACC1:not#23" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:not#23" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {ACC1:not#23.itm(0)} -pin  "ACC1:not#23" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#23.itm}
+load net {ACC1:not#23.itm(1)} -pin  "ACC1:not#23" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#23.itm}
+load net {ACC1:not#23.itm(2)} -pin  "ACC1:not#23" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#23.itm}
+load net {ACC1:not#23.itm(3)} -pin  "ACC1:not#23" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#23.itm}
+load net {ACC1:not#23.itm(4)} -pin  "ACC1:not#23" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#23.itm}
+load net {ACC1:not#23.itm(5)} -pin  "ACC1:not#23" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#23.itm}
+load net {ACC1:not#23.itm(6)} -pin  "ACC1:not#23" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#23.itm}
+load net {ACC1:not#23.itm(7)} -pin  "ACC1:not#23" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#23.itm}
+load net {ACC1:not#23.itm(8)} -pin  "ACC1:not#23" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#23.itm}
+load net {ACC1:not#23.itm(9)} -pin  "ACC1:not#23" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#23.itm}
+load inst "ACC1:acc#48" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 1954 -attr oid 339 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#48" {A(0)} -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {ACC1:not#22.itm(0)} -pin  "ACC1:acc#48" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {ACC1:not#22.itm(1)} -pin  "ACC1:acc#48" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {ACC1:not#22.itm(2)} -pin  "ACC1:acc#48" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {ACC1:not#22.itm(3)} -pin  "ACC1:acc#48" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {ACC1:not#22.itm(4)} -pin  "ACC1:acc#48" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {ACC1:not#22.itm(5)} -pin  "ACC1:acc#48" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {ACC1:not#22.itm(6)} -pin  "ACC1:acc#48" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {ACC1:not#22.itm(7)} -pin  "ACC1:acc#48" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {ACC1:not#22.itm(8)} -pin  "ACC1:acc#48" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {ACC1:not#22.itm(9)} -pin  "ACC1:acc#48" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {PWR} -pin  "ACC1:acc#48" {B(0)} -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#23.itm(0)} -pin  "ACC1:acc#48" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#23.itm(1)} -pin  "ACC1:acc#48" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#23.itm(2)} -pin  "ACC1:acc#48" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#23.itm(3)} -pin  "ACC1:acc#48" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#23.itm(4)} -pin  "ACC1:acc#48" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#23.itm(5)} -pin  "ACC1:acc#48" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#23.itm(6)} -pin  "ACC1:acc#48" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#23.itm(7)} -pin  "ACC1:acc#48" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#23.itm(8)} -pin  "ACC1:acc#48" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#23.itm(9)} -pin  "ACC1:acc#48" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:acc#48.itm(0)} -pin  "ACC1:acc#48" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(1)} -pin  "ACC1:acc#48" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(2)} -pin  "ACC1:acc#48" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(3)} -pin  "ACC1:acc#48" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(4)} -pin  "ACC1:acc#48" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(5)} -pin  "ACC1:acc#48" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(6)} -pin  "ACC1:acc#48" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(7)} -pin  "ACC1:acc#48" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(8)} -pin  "ACC1:acc#48" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(9)} -pin  "ACC1:acc#48" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(10)} -pin  "ACC1:acc#48" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "ACC1:acc#48" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load inst "ACC1:acc#51" "add(12,1,12,1,13)" "INTERFACE" -attr xrf 1955 -attr oid 340 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {PWR} -pin  "ACC1:acc#51" {A(0)} -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {ACC1:acc#49.itm(1)} -pin  "ACC1:acc#51" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {ACC1:acc#49.itm(2)} -pin  "ACC1:acc#51" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {ACC1:acc#49.itm(3)} -pin  "ACC1:acc#51" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {ACC1:acc#49.itm(4)} -pin  "ACC1:acc#51" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {ACC1:acc#49.itm(5)} -pin  "ACC1:acc#51" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {ACC1:acc#49.itm(6)} -pin  "ACC1:acc#51" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {ACC1:acc#49.itm(7)} -pin  "ACC1:acc#51" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {ACC1:acc#49.itm(8)} -pin  "ACC1:acc#51" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {ACC1:acc#49.itm(9)} -pin  "ACC1:acc#51" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {ACC1:acc#49.itm(10)} -pin  "ACC1:acc#51" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "ACC1:acc#51" {A(11)} -attr vt dc -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {PWR} -pin  "ACC1:acc#51" {B(0)} -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC1:acc#48.itm(1)} -pin  "ACC1:acc#51" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC1:acc#48.itm(2)} -pin  "ACC1:acc#51" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC1:acc#48.itm(3)} -pin  "ACC1:acc#51" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC1:acc#48.itm(4)} -pin  "ACC1:acc#51" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC1:acc#48.itm(5)} -pin  "ACC1:acc#51" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC1:acc#48.itm(6)} -pin  "ACC1:acc#51" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC1:acc#48.itm(7)} -pin  "ACC1:acc#51" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC1:acc#48.itm(8)} -pin  "ACC1:acc#51" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC1:acc#48.itm(9)} -pin  "ACC1:acc#51" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC1:acc#48.itm(10)} -pin  "ACC1:acc#51" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "ACC1:acc#51" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC1:acc#51.itm(0)} -pin  "ACC1:acc#51" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(1)} -pin  "ACC1:acc#51" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(2)} -pin  "ACC1:acc#51" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(3)} -pin  "ACC1:acc#51" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(4)} -pin  "ACC1:acc#51" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(5)} -pin  "ACC1:acc#51" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(6)} -pin  "ACC1:acc#51" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(7)} -pin  "ACC1:acc#51" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(8)} -pin  "ACC1:acc#51" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(9)} -pin  "ACC1:acc#51" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(10)} -pin  "ACC1:acc#51" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "ACC1:acc#51" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(12)} -pin  "ACC1:acc#51" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load inst "ACC1:not#24" "not(10)" "INTERFACE" -attr xrf 1956 -attr oid 341 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "ACC1:not#24" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "ACC1:not#24" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "ACC1:not#24" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "ACC1:not#24" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "ACC1:not#24" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "ACC1:not#24" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "ACC1:not#24" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "ACC1:not#24" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "ACC1:not#24" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "ACC1:not#24" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:not#24.itm(0)} -pin  "ACC1:not#24" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(1)} -pin  "ACC1:not#24" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(2)} -pin  "ACC1:not#24" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(3)} -pin  "ACC1:not#24" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(4)} -pin  "ACC1:not#24" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(5)} -pin  "ACC1:not#24" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(6)} -pin  "ACC1:not#24" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(7)} -pin  "ACC1:not#24" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(8)} -pin  "ACC1:not#24" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(9)} -pin  "ACC1:not#24" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load inst "ACC1:acc#57" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 1957 -attr oid 342 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#57} -attr area 11.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:slc(regs.regs(2))#13.itm(0)} -pin  "ACC1:acc#57" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(1)} -pin  "ACC1:acc#57" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(2)} -pin  "ACC1:acc#57" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(3)} -pin  "ACC1:acc#57" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(4)} -pin  "ACC1:acc#57" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(5)} -pin  "ACC1:acc#57" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(6)} -pin  "ACC1:acc#57" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(7)} -pin  "ACC1:acc#57" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(8)} -pin  "ACC1:acc#57" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:slc(regs.regs(2))#13.itm(9)} -pin  "ACC1:acc#57" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2))#13.itm}
+load net {ACC1:not#24.itm(0)} -pin  "ACC1:acc#57" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(1)} -pin  "ACC1:acc#57" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(2)} -pin  "ACC1:acc#57" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(3)} -pin  "ACC1:acc#57" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(4)} -pin  "ACC1:acc#57" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(5)} -pin  "ACC1:acc#57" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(6)} -pin  "ACC1:acc#57" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(7)} -pin  "ACC1:acc#57" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(8)} -pin  "ACC1:acc#57" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:not#24.itm(9)} -pin  "ACC1:acc#57" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#24.itm}
+load net {ACC1:acc#57.itm(0)} -pin  "ACC1:acc#57" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#57.itm}
+load net {ACC1:acc#57.itm(1)} -pin  "ACC1:acc#57" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#57.itm}
+load net {ACC1:acc#57.itm(2)} -pin  "ACC1:acc#57" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#57.itm}
+load net {ACC1:acc#57.itm(3)} -pin  "ACC1:acc#57" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#57.itm}
+load net {ACC1:acc#57.itm(4)} -pin  "ACC1:acc#57" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#57.itm}
+load net {ACC1:acc#57.itm(5)} -pin  "ACC1:acc#57" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#57.itm}
+load net {ACC1:acc#57.itm(6)} -pin  "ACC1:acc#57" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#57.itm}
+load net {ACC1:acc#57.itm(7)} -pin  "ACC1:acc#57" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#57.itm}
+load net {ACC1:acc#57.itm(8)} -pin  "ACC1:acc#57" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#57.itm}
+load net {ACC1:acc#57.itm(9)} -pin  "ACC1:acc#57" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#57.itm}
+load net {ACC1:acc#57.itm(10)} -pin  "ACC1:acc#57" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#57.itm}
+load inst "ACC1:acc#42" "add(12,1,12,1,13)" "INTERFACE" -attr xrf 1958 -attr oid 343 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1:acc#51.itm(1)} -pin  "ACC1:acc#42" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#51.itm(2)} -pin  "ACC1:acc#42" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#51.itm(3)} -pin  "ACC1:acc#42" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#51.itm(4)} -pin  "ACC1:acc#42" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#51.itm(5)} -pin  "ACC1:acc#42" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#51.itm(6)} -pin  "ACC1:acc#42" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#51.itm(7)} -pin  "ACC1:acc#42" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#51.itm(8)} -pin  "ACC1:acc#42" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#51.itm(9)} -pin  "ACC1:acc#42" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#51.itm(10)} -pin  "ACC1:acc#42" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "ACC1:acc#42" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#51.itm(12)} -pin  "ACC1:acc#42" {A(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {PWR} -pin  "ACC1:acc#42" {B(0)} -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC1:acc#57.itm(0)} -pin  "ACC1:acc#42" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC1:acc#57.itm(1)} -pin  "ACC1:acc#42" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC1:acc#57.itm(2)} -pin  "ACC1:acc#42" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC1:acc#57.itm(3)} -pin  "ACC1:acc#42" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC1:acc#57.itm(4)} -pin  "ACC1:acc#42" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC1:acc#57.itm(5)} -pin  "ACC1:acc#42" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC1:acc#57.itm(6)} -pin  "ACC1:acc#42" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC1:acc#57.itm(7)} -pin  "ACC1:acc#42" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC1:acc#57.itm(8)} -pin  "ACC1:acc#42" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC1:acc#57.itm(9)} -pin  "ACC1:acc#42" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC1:acc#57.itm(10)} -pin  "ACC1:acc#42" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC1:acc#42.psp.sva(0)} -pin  "ACC1:acc#42" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load net {ACC1:acc#42.psp.sva(1)} -pin  "ACC1:acc#42" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load net {ACC1:acc#42.psp.sva(2)} -pin  "ACC1:acc#42" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load net {ACC1:acc#42.psp.sva(3)} -pin  "ACC1:acc#42" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load net {ACC1:acc#42.psp.sva(4)} -pin  "ACC1:acc#42" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load net {ACC1:acc#42.psp.sva(5)} -pin  "ACC1:acc#42" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load net {ACC1:acc#42.psp.sva(6)} -pin  "ACC1:acc#42" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load net {ACC1:acc#42.psp.sva(7)} -pin  "ACC1:acc#42" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load net {ACC1:acc#42.psp.sva(8)} -pin  "ACC1:acc#42" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load net {ACC1:acc#42.psp.sva(9)} -pin  "ACC1:acc#42" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load net {ACC1:acc#42.psp.sva(10)} -pin  "ACC1:acc#42" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load net {ACC1:acc#42.psp.sva(11)} -pin  "ACC1:acc#42" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load net {ACC1:acc#42.psp.sva(12)} -pin  "ACC1:acc#42" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#42.psp.sva}
+load inst "FRAME:acc#49" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 1959 -attr oid 344 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#49} -attr area 6.285690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {FRAME:acc#18.sdt(1)} -pin  "FRAME:acc#49" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#18.sdt)#1.itm}
+load net {FRAME:acc#18.sdt(2)} -pin  "FRAME:acc#49" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#18.sdt)#1.itm}
+load net {FRAME:acc#18.sdt(3)} -pin  "FRAME:acc#49" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#18.sdt)#1.itm}
+load net {FRAME:acc#18.sdt(4)} -pin  "FRAME:acc#49" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#18.sdt)#1.itm}
+load net {FRAME:acc#18.sdt(5)} -pin  "FRAME:acc#49" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(FRAME:acc#18.sdt)#1.itm}
+load net {PWR} -pin  "FRAME:acc#49" {B(0)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {GND} -pin  "FRAME:acc#49" {B(1)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {PWR} -pin  "FRAME:acc#49" {B(2)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {GND} -pin  "FRAME:acc#49" {B(3)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {PWR} -pin  "FRAME:acc#49" {B(4)} -attr @path {/sobel/sobel:core/Cn11_5}
+load net {FRAME:acc#49.psp(0)} -pin  "FRAME:acc#49" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#49.psp}
+load net {FRAME:acc#49.psp(1)} -pin  "FRAME:acc#49" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#49.psp}
+load net {FRAME:acc#49.psp(2)} -pin  "FRAME:acc#49" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#49.psp}
+load net {FRAME:acc#49.psp(3)} -pin  "FRAME:acc#49" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#49.psp}
+load net {FRAME:acc#49.psp(4)} -pin  "FRAME:acc#49" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#49.psp}
+load inst "FRAME:not#33" "not(3)" "INTERFACE" -attr xrf 1960 -attr oid 345 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#33} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#42.psp.sva(9)} -pin  "FRAME:not#33" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#8.itm}
+load net {ACC1:acc#42.psp.sva(10)} -pin  "FRAME:not#33" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#8.itm}
+load net {ACC1:acc#42.psp.sva(11)} -pin  "FRAME:not#33" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#8.itm}
+load net {FRAME:not#33.itm(0)} -pin  "FRAME:not#33" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#33.itm}
+load net {FRAME:not#33.itm(1)} -pin  "FRAME:not#33" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#33.itm}
+load net {FRAME:not#33.itm(2)} -pin  "FRAME:not#33" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#33.itm}
+load inst "FRAME:acc#15" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 1961 -attr oid 346 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#42.psp.sva(6)} -pin  "FRAME:acc#15" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm}
+load net {ACC1:acc#42.psp.sva(7)} -pin  "FRAME:acc#15" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm}
+load net {ACC1:acc#42.psp.sva(8)} -pin  "FRAME:acc#15" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#7.itm}
+load net {FRAME:not#33.itm(0)} -pin  "FRAME:acc#15" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#33.itm}
+load net {FRAME:not#33.itm(1)} -pin  "FRAME:acc#15" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#33.itm}
+load net {FRAME:not#33.itm(2)} -pin  "FRAME:acc#15" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#33.itm}
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#15" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#15" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#15" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#15" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load inst "FRAME:not#34" "not(1)" "INTERFACE" -attr xrf 1962 -attr oid 347 -attr @path {/sobel/sobel:core/FRAME:not#34} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#42.psp.sva(12)} -pin  "FRAME:not#34" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#2.itm}
+load net {FRAME:not#34.itm} -pin  "FRAME:not#34" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#34.itm}
+load inst "FRAME:not#41" "not(3)" "INTERFACE" -attr xrf 1963 -attr oid 348 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#41} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#42.psp.sva(3)} -pin  "FRAME:not#41" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#9.itm}
+load net {ACC1:acc#42.psp.sva(4)} -pin  "FRAME:not#41" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#9.itm}
+load net {ACC1:acc#42.psp.sva(5)} -pin  "FRAME:not#41" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#9.itm}
+load net {FRAME:not#41.itm(0)} -pin  "FRAME:not#41" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#41.itm}
+load net {FRAME:not#41.itm(1)} -pin  "FRAME:not#41" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#41.itm}
+load net {FRAME:not#41.itm(2)} -pin  "FRAME:not#41" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#41.itm}
+load inst "FRAME:acc#17" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 1964 -attr oid 349 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#17" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#17" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#17" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#17" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:not#41.itm(0)} -pin  "FRAME:acc#17" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#35.itm}
+load net {FRAME:not#41.itm(1)} -pin  "FRAME:acc#17" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#35.itm}
+load net {FRAME:not#41.itm(2)} -pin  "FRAME:acc#17" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#35.itm}
+load net {FRAME:not#34.itm} -pin  "FRAME:acc#17" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#35.itm}
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#17" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#17" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:acc#17" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:acc#17" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(4)} -pin  "FRAME:acc#17" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load inst "FRAME:acc#16" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 1965 -attr oid 350 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#42.psp.sva(12)} -pin  "FRAME:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {GND} -pin  "FRAME:acc#16" {A(1)} -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {ACC1:acc#42.psp.sva(12)} -pin  "FRAME:acc#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {ACC1:acc#42.psp.sva(0)} -pin  "FRAME:acc#16" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#10.itm}
+load net {ACC1:acc#42.psp.sva(1)} -pin  "FRAME:acc#16" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#10.itm}
+load net {ACC1:acc#42.psp.sva(2)} -pin  "FRAME:acc#16" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#42.psp.sva)#10.itm}
+load net {FRAME:acc#16.itm(0)} -pin  "FRAME:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "FRAME:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "FRAME:acc#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "FRAME:acc#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load inst "FRAME:acc#18" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 1966 -attr oid 351 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#18" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#18" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:acc#18" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:acc#18" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(4)} -pin  "FRAME:acc#18" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#16.itm(0)} -pin  "FRAME:acc#18" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "FRAME:acc#18" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "FRAME:acc#18" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "FRAME:acc#18" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#18.sdt(0)} -pin  "FRAME:acc#18" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18.sdt}
+load net {FRAME:acc#18.sdt(1)} -pin  "FRAME:acc#18" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18.sdt}
+load net {FRAME:acc#18.sdt(2)} -pin  "FRAME:acc#18" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18.sdt}
+load net {FRAME:acc#18.sdt(3)} -pin  "FRAME:acc#18" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18.sdt}
+load net {FRAME:acc#18.sdt(4)} -pin  "FRAME:acc#18" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18.sdt}
+load net {FRAME:acc#18.sdt(5)} -pin  "FRAME:acc#18" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18.sdt}
+load inst "FRAME:mul" "mul(2,0,9,0,10)" "INTERFACE" -attr xrf 1967 -attr oid 352 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC1:acc.psp.sva(12)} -pin  "FRAME:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#16.itm}
+load net {ACC1:acc.psp.sva(12)} -pin  "FRAME:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#16.itm}
+load net {PWR} -pin  "FRAME:mul" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul.itm(0)} -pin  "FRAME:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(1)} -pin  "FRAME:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(2)} -pin  "FRAME:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(3)} -pin  "FRAME:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(4)} -pin  "FRAME:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(5)} -pin  "FRAME:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(6)} -pin  "FRAME:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(7)} -pin  "FRAME:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(8)} -pin  "FRAME:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(9)} -pin  "FRAME:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load inst "FRAME:mul#7" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 1968 -attr oid 353 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc.psp.sva(9)} -pin  "FRAME:mul#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#1.itm}
+load net {ACC1:acc.psp.sva(10)} -pin  "FRAME:mul#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#1.itm}
+load net {ACC1:acc.psp.sva(11)} -pin  "FRAME:mul#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#1.itm}
+load net {PWR} -pin  "FRAME:mul#7" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#7" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#7" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#7" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#7" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#7" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#7.itm(0)} -pin  "FRAME:mul#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(1)} -pin  "FRAME:mul#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(2)} -pin  "FRAME:mul#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(3)} -pin  "FRAME:mul#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(4)} -pin  "FRAME:mul#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(5)} -pin  "FRAME:mul#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(6)} -pin  "FRAME:mul#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(7)} -pin  "FRAME:mul#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(8)} -pin  "FRAME:mul#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load inst "FRAME:acc#44" "add(10,-1,9,0,10)" "INTERFACE" -attr xrf 1969 -attr oid 354 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44} -attr area 11.241230 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,10)"
+load net {FRAME:mul.itm(0)} -pin  "FRAME:acc#44" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(1)} -pin  "FRAME:acc#44" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(2)} -pin  "FRAME:acc#44" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(3)} -pin  "FRAME:acc#44" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(4)} -pin  "FRAME:acc#44" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(5)} -pin  "FRAME:acc#44" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(6)} -pin  "FRAME:acc#44" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(7)} -pin  "FRAME:acc#44" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(8)} -pin  "FRAME:acc#44" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(9)} -pin  "FRAME:acc#44" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul#7.itm(0)} -pin  "FRAME:acc#44" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(1)} -pin  "FRAME:acc#44" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(2)} -pin  "FRAME:acc#44" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(3)} -pin  "FRAME:acc#44" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(4)} -pin  "FRAME:acc#44" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(5)} -pin  "FRAME:acc#44" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(6)} -pin  "FRAME:acc#44" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(7)} -pin  "FRAME:acc#44" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(8)} -pin  "FRAME:acc#44" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:acc#44.itm(0)} -pin  "FRAME:acc#44" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(1)} -pin  "FRAME:acc#44" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
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+load net {FRAME:acc#44.itm(9)} -pin  "FRAME:acc#44" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
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+load net {FRAME:acc#41.sdt(4)} -pin  "FRAME:acc#60" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#41.sdt).itm}
+load net {FRAME:acc#41.sdt(5)} -pin  "FRAME:acc#60" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#41.sdt).itm}
+load net {FRAME:acc#41.sdt(6)} -pin  "FRAME:acc#60" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#41.sdt).itm}
+load net {ACC1:acc.psp.sva(6)} -pin  "FRAME:acc#60" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#15.itm}
+load net {ACC1:acc.psp.sva(7)} -pin  "FRAME:acc#60" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#15.itm}
+load net {ACC1:acc.psp.sva(8)} -pin  "FRAME:acc#60" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc.psp.sva)#15.itm}
+load net {FRAME:acc#60.itm(0)} -pin  "FRAME:acc#60" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#60.itm}
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+load net {ACC1:acc.psp.sva(3)} -pin  "FRAME:acc#43" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {ACC1:acc.psp.sva(4)} -pin  "FRAME:acc#43" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
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+load net {FRAME:acc#41.sdt(1)} -pin  "FRAME:acc#43" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#64.itm}
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+load net {FRAME:acc#8.itm(5)} -pin  "FRAME:acc#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
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+load net {FRAME:acc#8.itm(7)} -pin  "FRAME:acc#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(8)} -pin  "FRAME:acc#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(9)} -pin  "FRAME:acc#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load inst "FRAME:or" "or(2,10)" "INTERFACE" -attr xrf 1973 -attr oid 358 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or} -attr area 7.298324 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2)"
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:or" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:or" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
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+load net {FRAME:acc#8.itm(7)} -pin  "FRAME:or" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
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+load net {FRAME:acc#8.itm(9)} -pin  "FRAME:or" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc.psp(9)} -pin  "FRAME:or" {A1(0)} -attr vt dc -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {FRAME:acc.psp(10)} -pin  "FRAME:or" {A1(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {FRAME:acc.psp(11)} -pin  "FRAME:or" {A1(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {GND} -pin  "FRAME:or" {A1(3)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {GND} -pin  "FRAME:or" {A1(4)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {GND} -pin  "FRAME:or" {A1(5)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {GND} -pin  "FRAME:or" {A1(6)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {GND} -pin  "FRAME:or" {A1(7)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {GND} -pin  "FRAME:or" {A1(8)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {GND} -pin  "FRAME:or" {A1(9)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {FRAME:or.itm(0)} -pin  "FRAME:or" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(1)} -pin  "FRAME:or" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(2)} -pin  "FRAME:or" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(3)} -pin  "FRAME:or" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(4)} -pin  "FRAME:or" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(5)} -pin  "FRAME:or" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(6)} -pin  "FRAME:or" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(7)} -pin  "FRAME:or" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(8)} -pin  "FRAME:or" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(9)} -pin  "FRAME:or" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 1974 -attr oid 359 -attr vt dc -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)}
+load net {FRAME:or.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30#1}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30#1}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30#1}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30#1}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30#1}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30#1}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30#1}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30#1}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30#1}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30#1}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 1975 -attr oid 360 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)#1" "reg(4,1,1,-1,0)" "INTERFACE" -attr xrf 1976 -attr oid 361 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#1}
+load net {FRAME:acc.psp(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc.psp)#1.itm}
+load net {FRAME:acc.psp(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc.psp)#1.itm}
+load net {FRAME:acc.psp(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc.psp)#1.itm}
+load net {FRAME:acc.psp(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc.psp)#1.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30#2}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30#2}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30#2}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30#2}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {clk} -attr xrf 1977 -attr oid 362 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#1}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#1}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#1}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#1(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#1}
+load inst "FRAME:or#3" "or(2,5)" "INTERFACE" -attr xrf 1978 -attr oid 363 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3} -attr area 3.650162 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(5,2)"
+load net {FRAME:acc.psp(0)} -pin  "FRAME:or#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc.psp)#2.itm}
+load net {FRAME:acc.psp(1)} -pin  "FRAME:or#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc.psp)#2.itm}
+load net {FRAME:acc.psp(2)} -pin  "FRAME:or#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc.psp)#2.itm}
+load net {FRAME:acc.psp(3)} -pin  "FRAME:or#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc.psp)#2.itm}
+load net {FRAME:acc.psp(4)} -pin  "FRAME:or#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc.psp)#2.itm}
+load net {FRAME:acc#61.psp(10)} -pin  "FRAME:or#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {FRAME:acc#61.psp(11)} -pin  "FRAME:or#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(2)} -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(3)} -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(4)} -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {FRAME:or#3.itm(0)} -pin  "FRAME:or#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(1)} -pin  "FRAME:or#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(2)} -pin  "FRAME:or#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(3)} -pin  "FRAME:or#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(4)} -pin  "FRAME:or#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)#2" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 1979 -attr oid 364 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2}
+load net {FRAME:or#3.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30#3}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30#3}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30#3}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30#3}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30#3}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {clk} -attr xrf 1980 -attr oid 365 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#2}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#2}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#2}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#2}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#2}
+load inst "FRAME:or#4" "or(2,1)" "INTERFACE" -attr xrf 1981 -attr oid 366 -attr @path {/sobel/sobel:core/FRAME:or#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {FRAME:acc#24.sdt(0)} -pin  "FRAME:or#4" {A0(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#24.sdt).itm}
+load net {FRAME:acc#61.psp(9)} -pin  "FRAME:or#4" {A1(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#61.psp)#2.itm}
+load net {FRAME:or#4.itm} -pin  "FRAME:or#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:or#4.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)#3" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 1982 -attr oid 367 -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3}
+load net {FRAME:or#4.itm} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {D(0)} -attr @path {/sobel/sobel:core/FRAME:or#4.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30#4}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {clk} -attr xrf 1983 -attr oid 368 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {Z(0)} -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#3}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)#4" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 1984 -attr oid 369 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#4}
+load net {FRAME:acc#61.psp(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#61.psp)#1.itm}
+load net {FRAME:acc#61.psp(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#61.psp)#1.itm}
+load net {FRAME:acc#61.psp(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#61.psp)#1.itm}
+load net {FRAME:acc#61.psp(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#61.psp)#1.itm}
+load net {FRAME:acc#61.psp(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#61.psp)#1.itm}
+load net {FRAME:acc#61.psp(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#61.psp)#1.itm}
+load net {FRAME:acc#61.psp(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#61.psp)#1.itm}
+load net {FRAME:acc#61.psp(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#61.psp)#1.itm}
+load net {FRAME:acc#61.psp(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#61.psp)#1.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30#5}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30#5}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30#5}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30#5}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30#5}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30#5}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30#5}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30#5}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30#5}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {clk} -attr xrf 1985 -attr oid 370 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#4}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#4}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#4}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#4}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#4}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#4}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#4}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#4}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#4(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#4}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)#5" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 1986 -attr oid 371 -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#5}
+load net {FRAME:acc#37.sdt(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#5" {D(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#37.sdt).itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#5" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30#6}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#5" {clk} -attr xrf 1987 -attr oid 372 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#5" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#5" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#5} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#5" {Z(0)} -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#5}
+### END MODULE 
+
+module new "sobel" "orig"
+load portBus {vin:rsc.z(89:0)} input 90 {vin:rsc.z(89)} {vin:rsc.z(88)} {vin:rsc.z(87)} {vin:rsc.z(86)} {vin:rsc.z(85)} {vin:rsc.z(84)} {vin:rsc.z(83)} {vin:rsc.z(82)} {vin:rsc.z(81)} {vin:rsc.z(80)} {vin:rsc.z(79)} {vin:rsc.z(78)} {vin:rsc.z(77)} {vin:rsc.z(76)} {vin:rsc.z(75)} {vin:rsc.z(74)} {vin:rsc.z(73)} {vin:rsc.z(72)} {vin:rsc.z(71)} {vin:rsc.z(70)} {vin:rsc.z(69)} {vin:rsc.z(68)} {vin:rsc.z(67)} {vin:rsc.z(66)} {vin:rsc.z(65)} {vin:rsc.z(64)} {vin:rsc.z(63)} {vin:rsc.z(62)} {vin:rsc.z(61)} {vin:rsc.z(60)} {vin:rsc.z(59)} {vin:rsc.z(58)} {vin:rsc.z(57)} {vin:rsc.z(56)} {vin:rsc.z(55)} {vin:rsc.z(54)} {vin:rsc.z(53)} {vin:rsc.z(52)} {vin:rsc.z(51)} {vin:rsc.z(50)} {vin:rsc.z(49)} {vin:rsc.z(48)} {vin:rsc.z(47)} {vin:rsc.z(46)} {vin:rsc.z(45)} {vin:rsc.z(44)} {vin:rsc.z(43)} {vin:rsc.z(42)} {vin:rsc.z(41)} {vin:rsc.z(40)} {vin:rsc.z(39)} {vin:rsc.z(38)} {vin:rsc.z(37)} {vin:rsc.z(36)} {vin:rsc.z(35)} {vin:rsc.z(34)} {vin:rsc.z(33)} {vin:rsc.z(32)} {vin:rsc.z(31)} {vin:rsc.z(30)} {vin:rsc.z(29)} {vin:rsc.z(28)} {vin:rsc.z(27)} {vin:rsc.z(26)} {vin:rsc.z(25)} {vin:rsc.z(24)} {vin:rsc.z(23)} {vin:rsc.z(22)} {vin:rsc.z(21)} {vin:rsc.z(20)} {vin:rsc.z(19)} {vin:rsc.z(18)} {vin:rsc.z(17)} {vin:rsc.z(16)} {vin:rsc.z(15)} {vin:rsc.z(14)} {vin:rsc.z(13)} {vin:rsc.z(12)} {vin:rsc.z(11)} {vin:rsc.z(10)} {vin:rsc.z(9)} {vin:rsc.z(8)} {vin:rsc.z(7)} {vin:rsc.z(6)} {vin:rsc.z(5)} {vin:rsc.z(4)} {vin:rsc.z(3)} {vin:rsc.z(2)} {vin:rsc.z(1)} {vin:rsc.z(0)} -attr xrf 1988 -attr oid 373 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load portBus {vout:rsc.z(29:0)} output 30 {vout:rsc.z(29)} {vout:rsc.z(28)} {vout:rsc.z(27)} {vout:rsc.z(26)} {vout:rsc.z(25)} {vout:rsc.z(24)} {vout:rsc.z(23)} {vout:rsc.z(22)} {vout:rsc.z(21)} {vout:rsc.z(20)} {vout:rsc.z(19)} {vout:rsc.z(18)} {vout:rsc.z(17)} {vout:rsc.z(16)} {vout:rsc.z(15)} {vout:rsc.z(14)} {vout:rsc.z(13)} {vout:rsc.z(12)} {vout:rsc.z(11)} {vout:rsc.z(10)} {vout:rsc.z(9)} {vout:rsc.z(8)} {vout:rsc.z(7)} {vout:rsc.z(6)} {vout:rsc.z(5)} {vout:rsc.z(4)} {vout:rsc.z(3)} {vout:rsc.z(2)} {vout:rsc.z(1)} {vout:rsc.z(0)} -attr xrf 1989 -attr oid 374 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load port {clk} input -attr xrf 1990 -attr oid 375 -attr vt d -attr @path {/sobel/clk}
+load port {en} input -attr xrf 1991 -attr oid 376 -attr vt d -attr @path {/sobel/en}
+load port {arst_n} input -attr xrf 1992 -attr oid 377 -attr vt d -attr @path {/sobel/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(89:0)} output 90 {d(89)} {d(88)} {d(87)} {d(86)} {d(85)} {d(84)} {d(83)} {d(82)} {d(81)} {d(80)} {d(79)} {d(78)} {d(77)} {d(76)} {d(75)} {d(74)} {d(73)} {d(72)} {d(71)} {d(70)} {d(69)} {d(68)} {d(67)} {d(66)} {d(65)} {d(64)} {d(63)} {d(62)} {d(61)} {d(60)} {d(59)} {d(58)} {d(57)} {d(56)} {d(55)} {d(54)} {d(53)} {d(52)} {d(51)} {d(50)} {d(49)} {d(48)} {d(47)} {d(46)} {d(45)} {d(44)} {d(43)} {d(42)} {d(41)} {d(40)} {d(39)} {d(38)} {d(37)} {d(36)} {d(35)} {d(34)} {d(33)} {d(32)} {d(31)} {d(30)} {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(89:0)} input 90 {z(89)} {z(88)} {z(87)} {z(86)} {z(85)} {z(84)} {z(83)} {z(82)} {z(81)} {z(80)} {z(79)} {z(78)} {z(77)} {z(76)} {z(75)} {z(74)} {z(73)} {z(72)} {z(71)} {z(70)} {z(69)} {z(68)} {z(67)} {z(66)} {z(65)} {z(64)} {z(63)} {z(62)} {z(61)} {z(60)} {z(59)} {z(58)} {z(57)} {z(56)} {z(55)} {z(54)} {z(53)} {z(52)} {z(51)} {z(50)} {z(49)} {z(48)} {z(47)} {z(46)} {z(45)} {z(44)} {z(43)} {z(42)} {z(41)} {z(40)} {z(39)} {z(38)} {z(37)} {z(36)} {z(35)} {z(34)} {z(33)} {z(32)} {z(31)} {z(30)} {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(29:0)} input 30 {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(29:0)} output 30 {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "sobel:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} \
+     portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} \
+
+load net {vin:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d#1} 90 {vin:rsc:mgc_in_wire.d#1(0)} {vin:rsc:mgc_in_wire.d#1(1)} {vin:rsc:mgc_in_wire.d#1(2)} {vin:rsc:mgc_in_wire.d#1(3)} {vin:rsc:mgc_in_wire.d#1(4)} {vin:rsc:mgc_in_wire.d#1(5)} {vin:rsc:mgc_in_wire.d#1(6)} {vin:rsc:mgc_in_wire.d#1(7)} {vin:rsc:mgc_in_wire.d#1(8)} {vin:rsc:mgc_in_wire.d#1(9)} {vin:rsc:mgc_in_wire.d#1(10)} {vin:rsc:mgc_in_wire.d#1(11)} {vin:rsc:mgc_in_wire.d#1(12)} {vin:rsc:mgc_in_wire.d#1(13)} {vin:rsc:mgc_in_wire.d#1(14)} {vin:rsc:mgc_in_wire.d#1(15)} {vin:rsc:mgc_in_wire.d#1(16)} {vin:rsc:mgc_in_wire.d#1(17)} {vin:rsc:mgc_in_wire.d#1(18)} {vin:rsc:mgc_in_wire.d#1(19)} {vin:rsc:mgc_in_wire.d#1(20)} {vin:rsc:mgc_in_wire.d#1(21)} {vin:rsc:mgc_in_wire.d#1(22)} {vin:rsc:mgc_in_wire.d#1(23)} {vin:rsc:mgc_in_wire.d#1(24)} {vin:rsc:mgc_in_wire.d#1(25)} {vin:rsc:mgc_in_wire.d#1(26)} {vin:rsc:mgc_in_wire.d#1(27)} {vin:rsc:mgc_in_wire.d#1(28)} {vin:rsc:mgc_in_wire.d#1(29)} {vin:rsc:mgc_in_wire.d#1(30)} {vin:rsc:mgc_in_wire.d#1(31)} {vin:rsc:mgc_in_wire.d#1(32)} {vin:rsc:mgc_in_wire.d#1(33)} {vin:rsc:mgc_in_wire.d#1(34)} {vin:rsc:mgc_in_wire.d#1(35)} {vin:rsc:mgc_in_wire.d#1(36)} {vin:rsc:mgc_in_wire.d#1(37)} {vin:rsc:mgc_in_wire.d#1(38)} {vin:rsc:mgc_in_wire.d#1(39)} {vin:rsc:mgc_in_wire.d#1(40)} {vin:rsc:mgc_in_wire.d#1(41)} {vin:rsc:mgc_in_wire.d#1(42)} {vin:rsc:mgc_in_wire.d#1(43)} {vin:rsc:mgc_in_wire.d#1(44)} {vin:rsc:mgc_in_wire.d#1(45)} {vin:rsc:mgc_in_wire.d#1(46)} {vin:rsc:mgc_in_wire.d#1(47)} {vin:rsc:mgc_in_wire.d#1(48)} {vin:rsc:mgc_in_wire.d#1(49)} {vin:rsc:mgc_in_wire.d#1(50)} {vin:rsc:mgc_in_wire.d#1(51)} {vin:rsc:mgc_in_wire.d#1(52)} {vin:rsc:mgc_in_wire.d#1(53)} {vin:rsc:mgc_in_wire.d#1(54)} {vin:rsc:mgc_in_wire.d#1(55)} {vin:rsc:mgc_in_wire.d#1(56)} {vin:rsc:mgc_in_wire.d#1(57)} {vin:rsc:mgc_in_wire.d#1(58)} {vin:rsc:mgc_in_wire.d#1(59)} {vin:rsc:mgc_in_wire.d#1(60)} {vin:rsc:mgc_in_wire.d#1(61)} {vin:rsc:mgc_in_wire.d#1(62)} {vin:rsc:mgc_in_wire.d#1(63)} {vin:rsc:mgc_in_wire.d#1(64)} {vin:rsc:mgc_in_wire.d#1(65)} {vin:rsc:mgc_in_wire.d#1(66)} {vin:rsc:mgc_in_wire.d#1(67)} {vin:rsc:mgc_in_wire.d#1(68)} {vin:rsc:mgc_in_wire.d#1(69)} {vin:rsc:mgc_in_wire.d#1(70)} {vin:rsc:mgc_in_wire.d#1(71)} {vin:rsc:mgc_in_wire.d#1(72)} {vin:rsc:mgc_in_wire.d#1(73)} {vin:rsc:mgc_in_wire.d#1(74)} {vin:rsc:mgc_in_wire.d#1(75)} {vin:rsc:mgc_in_wire.d#1(76)} {vin:rsc:mgc_in_wire.d#1(77)} {vin:rsc:mgc_in_wire.d#1(78)} {vin:rsc:mgc_in_wire.d#1(79)} {vin:rsc:mgc_in_wire.d#1(80)} {vin:rsc:mgc_in_wire.d#1(81)} {vin:rsc:mgc_in_wire.d#1(82)} {vin:rsc:mgc_in_wire.d#1(83)} {vin:rsc:mgc_in_wire.d#1(84)} {vin:rsc:mgc_in_wire.d#1(85)} {vin:rsc:mgc_in_wire.d#1(86)} {vin:rsc:mgc_in_wire.d#1(87)} {vin:rsc:mgc_in_wire.d#1(88)} {vin:rsc:mgc_in_wire.d#1(89)} -attr xrf 1993 -attr oid 378 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d#1} 30 {vout:rsc:mgc_out_stdreg.d#1(0)} {vout:rsc:mgc_out_stdreg.d#1(1)} {vout:rsc:mgc_out_stdreg.d#1(2)} {vout:rsc:mgc_out_stdreg.d#1(3)} {vout:rsc:mgc_out_stdreg.d#1(4)} {vout:rsc:mgc_out_stdreg.d#1(5)} {vout:rsc:mgc_out_stdreg.d#1(6)} {vout:rsc:mgc_out_stdreg.d#1(7)} {vout:rsc:mgc_out_stdreg.d#1(8)} {vout:rsc:mgc_out_stdreg.d#1(9)} {vout:rsc:mgc_out_stdreg.d#1(10)} {vout:rsc:mgc_out_stdreg.d#1(11)} {vout:rsc:mgc_out_stdreg.d#1(12)} {vout:rsc:mgc_out_stdreg.d#1(13)} {vout:rsc:mgc_out_stdreg.d#1(14)} {vout:rsc:mgc_out_stdreg.d#1(15)} {vout:rsc:mgc_out_stdreg.d#1(16)} {vout:rsc:mgc_out_stdreg.d#1(17)} {vout:rsc:mgc_out_stdreg.d#1(18)} {vout:rsc:mgc_out_stdreg.d#1(19)} {vout:rsc:mgc_out_stdreg.d#1(20)} {vout:rsc:mgc_out_stdreg.d#1(21)} {vout:rsc:mgc_out_stdreg.d#1(22)} {vout:rsc:mgc_out_stdreg.d#1(23)} {vout:rsc:mgc_out_stdreg.d#1(24)} {vout:rsc:mgc_out_stdreg.d#1(25)} {vout:rsc:mgc_out_stdreg.d#1(26)} {vout:rsc:mgc_out_stdreg.d#1(27)} {vout:rsc:mgc_out_stdreg.d#1(28)} {vout:rsc:mgc_out_stdreg.d#1(29)} -attr xrf 1994 -attr oid 379 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -attr vt d
+load net {vin:rsc.z(13)} -attr vt d
+load net {vin:rsc.z(14)} -attr vt d
+load net {vin:rsc.z(15)} -attr vt d
+load net {vin:rsc.z(16)} -attr vt d
+load net {vin:rsc.z(17)} -attr vt d
+load net {vin:rsc.z(18)} -attr vt d
+load net {vin:rsc.z(19)} -attr vt d
+load net {vin:rsc.z(20)} -attr vt d
+load net {vin:rsc.z(21)} -attr vt d
+load net {vin:rsc.z(22)} -attr vt d
+load net {vin:rsc.z(23)} -attr vt d
+load net {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -attr vt d
+load net {vin:rsc.z(28)} -attr vt d
+load net {vin:rsc.z(29)} -attr vt d
+load net {vin:rsc.z(30)} -attr vt d
+load net {vin:rsc.z(31)} -attr vt d
+load net {vin:rsc.z(32)} -attr vt d
+load net {vin:rsc.z(33)} -attr vt d
+load net {vin:rsc.z(34)} -attr vt d
+load net {vin:rsc.z(35)} -attr vt d
+load net {vin:rsc.z(36)} -attr vt d
+load net {vin:rsc.z(37)} -attr vt d
+load net {vin:rsc.z(38)} -attr vt d
+load net {vin:rsc.z(39)} -attr vt d
+load net {vin:rsc.z(40)} -attr vt d
+load net {vin:rsc.z(41)} -attr vt d
+load net {vin:rsc.z(42)} -attr vt d
+load net {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -attr vt d
+load net {vin:rsc.z(45)} -attr vt d
+load net {vin:rsc.z(46)} -attr vt d
+load net {vin:rsc.z(47)} -attr vt d
+load net {vin:rsc.z(48)} -attr vt d
+load net {vin:rsc.z(49)} -attr vt d
+load net {vin:rsc.z(50)} -attr vt d
+load net {vin:rsc.z(51)} -attr vt d
+load net {vin:rsc.z(52)} -attr vt d
+load net {vin:rsc.z(53)} -attr vt d
+load net {vin:rsc.z(54)} -attr vt d
+load net {vin:rsc.z(55)} -attr vt d
+load net {vin:rsc.z(56)} -attr vt d
+load net {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -attr vt d
+load net {vin:rsc.z(63)} -attr vt d
+load net {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -attr vt d
+load net {vin:rsc.z(68)} -attr vt d
+load net {vin:rsc.z(69)} -attr vt d
+load net {vin:rsc.z(70)} -attr vt d
+load net {vin:rsc.z(71)} -attr vt d
+load net {vin:rsc.z(72)} -attr vt d
+load net {vin:rsc.z(73)} -attr vt d
+load net {vin:rsc.z(74)} -attr vt d
+load net {vin:rsc.z(75)} -attr vt d
+load net {vin:rsc.z(76)} -attr vt d
+load net {vin:rsc.z(77)} -attr vt d
+load net {vin:rsc.z(78)} -attr vt d
+load net {vin:rsc.z(79)} -attr vt d
+load net {vin:rsc.z(80)} -attr vt d
+load net {vin:rsc.z(81)} -attr vt d
+load net {vin:rsc.z(82)} -attr vt d
+load net {vin:rsc.z(83)} -attr vt d
+load net {vin:rsc.z(84)} -attr vt d
+load net {vin:rsc.z(85)} -attr vt d
+load net {vin:rsc.z(86)} -attr vt d
+load net {vin:rsc.z(87)} -attr vt d
+load net {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 1995 -attr oid 380 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(0)} -port {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -port {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -port {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -port {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -port {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -port {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -port {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -port {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -port {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -port {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -port {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -port {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -port {vin:rsc.z(12)} -attr vt d
+load net {vin:rsc.z(13)} -port {vin:rsc.z(13)} -attr vt d
+load net {vin:rsc.z(14)} -port {vin:rsc.z(14)} -attr vt d
+load net {vin:rsc.z(15)} -port {vin:rsc.z(15)} -attr vt d
+load net {vin:rsc.z(16)} -port {vin:rsc.z(16)} -attr vt d
+load net {vin:rsc.z(17)} -port {vin:rsc.z(17)} -attr vt d
+load net {vin:rsc.z(18)} -port {vin:rsc.z(18)} -attr vt d
+load net {vin:rsc.z(19)} -port {vin:rsc.z(19)} -attr vt d
+load net {vin:rsc.z(20)} -port {vin:rsc.z(20)} -attr vt d
+load net {vin:rsc.z(21)} -port {vin:rsc.z(21)} -attr vt d
+load net {vin:rsc.z(22)} -port {vin:rsc.z(22)} -attr vt d
+load net {vin:rsc.z(23)} -port {vin:rsc.z(23)} -attr vt d
+load net {vin:rsc.z(24)} -port {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -port {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -port {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -port {vin:rsc.z(27)} -attr vt d
+load net {vin:rsc.z(28)} -port {vin:rsc.z(28)} -attr vt d
+load net {vin:rsc.z(29)} -port {vin:rsc.z(29)} -attr vt d
+load net {vin:rsc.z(30)} -port {vin:rsc.z(30)} -attr vt d
+load net {vin:rsc.z(31)} -port {vin:rsc.z(31)} -attr vt d
+load net {vin:rsc.z(32)} -port {vin:rsc.z(32)} -attr vt d
+load net {vin:rsc.z(33)} -port {vin:rsc.z(33)} -attr vt d
+load net {vin:rsc.z(34)} -port {vin:rsc.z(34)} -attr vt d
+load net {vin:rsc.z(35)} -port {vin:rsc.z(35)} -attr vt d
+load net {vin:rsc.z(36)} -port {vin:rsc.z(36)} -attr vt d
+load net {vin:rsc.z(37)} -port {vin:rsc.z(37)} -attr vt d
+load net {vin:rsc.z(38)} -port {vin:rsc.z(38)} -attr vt d
+load net {vin:rsc.z(39)} -port {vin:rsc.z(39)} -attr vt d
+load net {vin:rsc.z(40)} -port {vin:rsc.z(40)} -attr vt d
+load net {vin:rsc.z(41)} -port {vin:rsc.z(41)} -attr vt d
+load net {vin:rsc.z(42)} -port {vin:rsc.z(42)} -attr vt d
+load net {vin:rsc.z(43)} -port {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -port {vin:rsc.z(44)} -attr vt d
+load net {vin:rsc.z(45)} -port {vin:rsc.z(45)} -attr vt d
+load net {vin:rsc.z(46)} -port {vin:rsc.z(46)} -attr vt d
+load net {vin:rsc.z(47)} -port {vin:rsc.z(47)} -attr vt d
+load net {vin:rsc.z(48)} -port {vin:rsc.z(48)} -attr vt d
+load net {vin:rsc.z(49)} -port {vin:rsc.z(49)} -attr vt d
+load net {vin:rsc.z(50)} -port {vin:rsc.z(50)} -attr vt d
+load net {vin:rsc.z(51)} -port {vin:rsc.z(51)} -attr vt d
+load net {vin:rsc.z(52)} -port {vin:rsc.z(52)} -attr vt d
+load net {vin:rsc.z(53)} -port {vin:rsc.z(53)} -attr vt d
+load net {vin:rsc.z(54)} -port {vin:rsc.z(54)} -attr vt d
+load net {vin:rsc.z(55)} -port {vin:rsc.z(55)} -attr vt d
+load net {vin:rsc.z(56)} -port {vin:rsc.z(56)} -attr vt d
+load net {vin:rsc.z(57)} -port {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -port {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -port {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -port {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -port {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -port {vin:rsc.z(62)} -attr vt d
+load net {vin:rsc.z(63)} -port {vin:rsc.z(63)} -attr vt d
+load net {vin:rsc.z(64)} -port {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -port {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -port {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -port {vin:rsc.z(67)} -attr vt d
+load net {vin:rsc.z(68)} -port {vin:rsc.z(68)} -attr vt d
+load net {vin:rsc.z(69)} -port {vin:rsc.z(69)} -attr vt d
+load net {vin:rsc.z(70)} -port {vin:rsc.z(70)} -attr vt d
+load net {vin:rsc.z(71)} -port {vin:rsc.z(71)} -attr vt d
+load net {vin:rsc.z(72)} -port {vin:rsc.z(72)} -attr vt d
+load net {vin:rsc.z(73)} -port {vin:rsc.z(73)} -attr vt d
+load net {vin:rsc.z(74)} -port {vin:rsc.z(74)} -attr vt d
+load net {vin:rsc.z(75)} -port {vin:rsc.z(75)} -attr vt d
+load net {vin:rsc.z(76)} -port {vin:rsc.z(76)} -attr vt d
+load net {vin:rsc.z(77)} -port {vin:rsc.z(77)} -attr vt d
+load net {vin:rsc.z(78)} -port {vin:rsc.z(78)} -attr vt d
+load net {vin:rsc.z(79)} -port {vin:rsc.z(79)} -attr vt d
+load net {vin:rsc.z(80)} -port {vin:rsc.z(80)} -attr vt d
+load net {vin:rsc.z(81)} -port {vin:rsc.z(81)} -attr vt d
+load net {vin:rsc.z(82)} -port {vin:rsc.z(82)} -attr vt d
+load net {vin:rsc.z(83)} -port {vin:rsc.z(83)} -attr vt d
+load net {vin:rsc.z(84)} -port {vin:rsc.z(84)} -attr vt d
+load net {vin:rsc.z(85)} -port {vin:rsc.z(85)} -attr vt d
+load net {vin:rsc.z(86)} -port {vin:rsc.z(86)} -attr vt d
+load net {vin:rsc.z(87)} -port {vin:rsc.z(87)} -attr vt d
+load net {vin:rsc.z(88)} -port {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -port {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 1996 -attr oid 381 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vout:rsc.z(0)} -attr vt d
+load net {vout:rsc.z(1)} -attr vt d
+load net {vout:rsc.z(2)} -attr vt d
+load net {vout:rsc.z(3)} -attr vt d
+load net {vout:rsc.z(4)} -attr vt d
+load net {vout:rsc.z(5)} -attr vt d
+load net {vout:rsc.z(6)} -attr vt d
+load net {vout:rsc.z(7)} -attr vt d
+load net {vout:rsc.z(8)} -attr vt d
+load net {vout:rsc.z(9)} -attr vt d
+load net {vout:rsc.z(10)} -attr vt d
+load net {vout:rsc.z(11)} -attr vt d
+load net {vout:rsc.z(12)} -attr vt d
+load net {vout:rsc.z(13)} -attr vt d
+load net {vout:rsc.z(14)} -attr vt d
+load net {vout:rsc.z(15)} -attr vt d
+load net {vout:rsc.z(16)} -attr vt d
+load net {vout:rsc.z(17)} -attr vt d
+load net {vout:rsc.z(18)} -attr vt d
+load net {vout:rsc.z(19)} -attr vt d
+load net {vout:rsc.z(20)} -attr vt d
+load net {vout:rsc.z(21)} -attr vt d
+load net {vout:rsc.z(22)} -attr vt d
+load net {vout:rsc.z(23)} -attr vt d
+load net {vout:rsc.z(24)} -attr vt d
+load net {vout:rsc.z(25)} -attr vt d
+load net {vout:rsc.z(26)} -attr vt d
+load net {vout:rsc.z(27)} -attr vt d
+load net {vout:rsc.z(28)} -attr vt d
+load net {vout:rsc.z(29)} -attr vt d
+load netBundle {vout:rsc.z} 30 {vout:rsc.z(0)} {vout:rsc.z(1)} {vout:rsc.z(2)} {vout:rsc.z(3)} {vout:rsc.z(4)} {vout:rsc.z(5)} {vout:rsc.z(6)} {vout:rsc.z(7)} {vout:rsc.z(8)} {vout:rsc.z(9)} {vout:rsc.z(10)} {vout:rsc.z(11)} {vout:rsc.z(12)} {vout:rsc.z(13)} {vout:rsc.z(14)} {vout:rsc.z(15)} {vout:rsc.z(16)} {vout:rsc.z(17)} {vout:rsc.z(18)} {vout:rsc.z(19)} {vout:rsc.z(20)} {vout:rsc.z(21)} {vout:rsc.z(22)} {vout:rsc.z(23)} {vout:rsc.z(24)} {vout:rsc.z(25)} {vout:rsc.z(26)} {vout:rsc.z(27)} {vout:rsc.z(28)} {vout:rsc.z(29)} -attr xrf 1997 -attr oid 382 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(0)} -port {vout:rsc.z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -port {vout:rsc.z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -port {vout:rsc.z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -port {vout:rsc.z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -port {vout:rsc.z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -port {vout:rsc.z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -port {vout:rsc.z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -port {vout:rsc.z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -port {vout:rsc.z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -port {vout:rsc.z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -port {vout:rsc.z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -port {vout:rsc.z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -port {vout:rsc.z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -port {vout:rsc.z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -port {vout:rsc.z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -port {vout:rsc.z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -port {vout:rsc.z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -port {vout:rsc.z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -port {vout:rsc.z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -port {vout:rsc.z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -port {vout:rsc.z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -port {vout:rsc.z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -port {vout:rsc.z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -port {vout:rsc.z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -port {vout:rsc.z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -port {vout:rsc.z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -port {vout:rsc.z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -port {vout:rsc.z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -port {vout:rsc.z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -port {vout:rsc.z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {clk} -attr xrf 1998 -attr oid 383
+load net {clk} -port {clk} -attr xrf 1999 -attr oid 384
+load net {en} -attr xrf 2000 -attr oid 385
+load net {en} -port {en} -attr xrf 2001 -attr oid 386
+load net {arst_n} -attr xrf 2002 -attr oid 387
+load net {arst_n} -port {arst_n} -attr xrf 2003 -attr oid 388
+load inst "sobel:core:inst" "sobel:core" "orig" -attr xrf 2004 -attr oid 389 -attr vt dc -attr @path {/sobel/sobel:core:inst} -attr area 2455.667196 -attr delay 14.431319 -attr hier "/sobel/sobel:core" -pg 1 -lvl 3
+load net {clk} -pin  "sobel:core:inst" {clk#1} -attr xrf 2005 -attr oid 390 -attr @path {/sobel/clk}
+load net {en} -pin  "sobel:core:inst" {en#1} -attr xrf 2006 -attr oid 391 -attr @path {/sobel/en}
+load net {arst_n} -pin  "sobel:core:inst" {arst_n#1} -attr xrf 2007 -attr oid 392 -attr @path {/sobel/arst_n}
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(8)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(9)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(10)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(11)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(12)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(13)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(14)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(15)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(16)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(17)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(18)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(19)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(20)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(21)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(22)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(23)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(24)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(25)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(26)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(27)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(28)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(29)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(30)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(31)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(32)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(33)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(34)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(35)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(36)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(37)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(38)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(39)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(40)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(41)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(42)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(43)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(44)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(45)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(46)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(47)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(48)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(49)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(50)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(51)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(52)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(53)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(54)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(55)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(56)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(57)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(58)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(59)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(60)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(61)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(62)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(63)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(64)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(65)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(66)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(67)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(68)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(69)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(70)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(71)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(72)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(73)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(74)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(75)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(76)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(77)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(78)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(79)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(80)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(81)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(82)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(83)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(84)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(85)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(86)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(87)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(88)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(89)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(8)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(9)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(10)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(11)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(12)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(13)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(14)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(15)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(16)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(17)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(18)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(19)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(20)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(21)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(22)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(23)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(24)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(25)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(26)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(27)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(28)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(29)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load inst "vin:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" -attr xrf 2008 -attr oid 393 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,90)" -pg 1 -lvl 1
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "vin:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "vin:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "vin:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "vin:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "vin:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "vin:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "vin:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "vin:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "vin:rsc:mgc_in_wire" {d(8)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "vin:rsc:mgc_in_wire" {d(9)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "vin:rsc:mgc_in_wire" {d(10)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "vin:rsc:mgc_in_wire" {d(11)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "vin:rsc:mgc_in_wire" {d(12)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "vin:rsc:mgc_in_wire" {d(13)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "vin:rsc:mgc_in_wire" {d(14)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "vin:rsc:mgc_in_wire" {d(15)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "vin:rsc:mgc_in_wire" {d(16)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "vin:rsc:mgc_in_wire" {d(17)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "vin:rsc:mgc_in_wire" {d(18)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "vin:rsc:mgc_in_wire" {d(19)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "vin:rsc:mgc_in_wire" {d(20)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "vin:rsc:mgc_in_wire" {d(21)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "vin:rsc:mgc_in_wire" {d(22)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "vin:rsc:mgc_in_wire" {d(23)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "vin:rsc:mgc_in_wire" {d(24)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "vin:rsc:mgc_in_wire" {d(25)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "vin:rsc:mgc_in_wire" {d(26)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "vin:rsc:mgc_in_wire" {d(27)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "vin:rsc:mgc_in_wire" {d(28)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "vin:rsc:mgc_in_wire" {d(29)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "vin:rsc:mgc_in_wire" {d(30)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "vin:rsc:mgc_in_wire" {d(31)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "vin:rsc:mgc_in_wire" {d(32)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "vin:rsc:mgc_in_wire" {d(33)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "vin:rsc:mgc_in_wire" {d(34)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "vin:rsc:mgc_in_wire" {d(35)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "vin:rsc:mgc_in_wire" {d(36)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "vin:rsc:mgc_in_wire" {d(37)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "vin:rsc:mgc_in_wire" {d(38)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "vin:rsc:mgc_in_wire" {d(39)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "vin:rsc:mgc_in_wire" {d(40)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "vin:rsc:mgc_in_wire" {d(41)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "vin:rsc:mgc_in_wire" {d(42)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "vin:rsc:mgc_in_wire" {d(43)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "vin:rsc:mgc_in_wire" {d(44)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "vin:rsc:mgc_in_wire" {d(45)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "vin:rsc:mgc_in_wire" {d(46)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "vin:rsc:mgc_in_wire" {d(47)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "vin:rsc:mgc_in_wire" {d(48)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "vin:rsc:mgc_in_wire" {d(49)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "vin:rsc:mgc_in_wire" {d(50)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "vin:rsc:mgc_in_wire" {d(51)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "vin:rsc:mgc_in_wire" {d(52)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "vin:rsc:mgc_in_wire" {d(53)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "vin:rsc:mgc_in_wire" {d(54)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "vin:rsc:mgc_in_wire" {d(55)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "vin:rsc:mgc_in_wire" {d(56)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "vin:rsc:mgc_in_wire" {d(57)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "vin:rsc:mgc_in_wire" {d(58)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "vin:rsc:mgc_in_wire" {d(59)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "vin:rsc:mgc_in_wire" {d(60)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "vin:rsc:mgc_in_wire" {d(61)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "vin:rsc:mgc_in_wire" {d(62)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "vin:rsc:mgc_in_wire" {d(63)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "vin:rsc:mgc_in_wire" {d(64)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "vin:rsc:mgc_in_wire" {d(65)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "vin:rsc:mgc_in_wire" {d(66)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "vin:rsc:mgc_in_wire" {d(67)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "vin:rsc:mgc_in_wire" {d(68)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "vin:rsc:mgc_in_wire" {d(69)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "vin:rsc:mgc_in_wire" {d(70)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "vin:rsc:mgc_in_wire" {d(71)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "vin:rsc:mgc_in_wire" {d(72)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "vin:rsc:mgc_in_wire" {d(73)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "vin:rsc:mgc_in_wire" {d(74)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "vin:rsc:mgc_in_wire" {d(75)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "vin:rsc:mgc_in_wire" {d(76)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "vin:rsc:mgc_in_wire" {d(77)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "vin:rsc:mgc_in_wire" {d(78)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "vin:rsc:mgc_in_wire" {d(79)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "vin:rsc:mgc_in_wire" {d(80)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "vin:rsc:mgc_in_wire" {d(81)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "vin:rsc:mgc_in_wire" {d(82)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "vin:rsc:mgc_in_wire" {d(83)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "vin:rsc:mgc_in_wire" {d(84)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "vin:rsc:mgc_in_wire" {d(85)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "vin:rsc:mgc_in_wire" {d(86)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "vin:rsc:mgc_in_wire" {d(87)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "vin:rsc:mgc_in_wire" {d(88)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "vin:rsc:mgc_in_wire" {d(89)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc.z(0)} -pin  "vin:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(1)} -pin  "vin:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(2)} -pin  "vin:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(3)} -pin  "vin:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(4)} -pin  "vin:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(5)} -pin  "vin:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(6)} -pin  "vin:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(7)} -pin  "vin:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(8)} -pin  "vin:rsc:mgc_in_wire" {z(8)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(9)} -pin  "vin:rsc:mgc_in_wire" {z(9)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(10)} -pin  "vin:rsc:mgc_in_wire" {z(10)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(11)} -pin  "vin:rsc:mgc_in_wire" {z(11)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(12)} -pin  "vin:rsc:mgc_in_wire" {z(12)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(13)} -pin  "vin:rsc:mgc_in_wire" {z(13)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(14)} -pin  "vin:rsc:mgc_in_wire" {z(14)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(15)} -pin  "vin:rsc:mgc_in_wire" {z(15)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(16)} -pin  "vin:rsc:mgc_in_wire" {z(16)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(17)} -pin  "vin:rsc:mgc_in_wire" {z(17)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(18)} -pin  "vin:rsc:mgc_in_wire" {z(18)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(19)} -pin  "vin:rsc:mgc_in_wire" {z(19)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(20)} -pin  "vin:rsc:mgc_in_wire" {z(20)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(21)} -pin  "vin:rsc:mgc_in_wire" {z(21)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(22)} -pin  "vin:rsc:mgc_in_wire" {z(22)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(23)} -pin  "vin:rsc:mgc_in_wire" {z(23)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(24)} -pin  "vin:rsc:mgc_in_wire" {z(24)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(25)} -pin  "vin:rsc:mgc_in_wire" {z(25)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(26)} -pin  "vin:rsc:mgc_in_wire" {z(26)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(27)} -pin  "vin:rsc:mgc_in_wire" {z(27)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(28)} -pin  "vin:rsc:mgc_in_wire" {z(28)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(29)} -pin  "vin:rsc:mgc_in_wire" {z(29)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(30)} -pin  "vin:rsc:mgc_in_wire" {z(30)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(31)} -pin  "vin:rsc:mgc_in_wire" {z(31)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(32)} -pin  "vin:rsc:mgc_in_wire" {z(32)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(33)} -pin  "vin:rsc:mgc_in_wire" {z(33)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(34)} -pin  "vin:rsc:mgc_in_wire" {z(34)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(35)} -pin  "vin:rsc:mgc_in_wire" {z(35)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(36)} -pin  "vin:rsc:mgc_in_wire" {z(36)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(37)} -pin  "vin:rsc:mgc_in_wire" {z(37)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(38)} -pin  "vin:rsc:mgc_in_wire" {z(38)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(39)} -pin  "vin:rsc:mgc_in_wire" {z(39)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(40)} -pin  "vin:rsc:mgc_in_wire" {z(40)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(41)} -pin  "vin:rsc:mgc_in_wire" {z(41)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(42)} -pin  "vin:rsc:mgc_in_wire" {z(42)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(43)} -pin  "vin:rsc:mgc_in_wire" {z(43)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(44)} -pin  "vin:rsc:mgc_in_wire" {z(44)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(45)} -pin  "vin:rsc:mgc_in_wire" {z(45)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(46)} -pin  "vin:rsc:mgc_in_wire" {z(46)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(47)} -pin  "vin:rsc:mgc_in_wire" {z(47)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(48)} -pin  "vin:rsc:mgc_in_wire" {z(48)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(49)} -pin  "vin:rsc:mgc_in_wire" {z(49)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(50)} -pin  "vin:rsc:mgc_in_wire" {z(50)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(51)} -pin  "vin:rsc:mgc_in_wire" {z(51)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(52)} -pin  "vin:rsc:mgc_in_wire" {z(52)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(53)} -pin  "vin:rsc:mgc_in_wire" {z(53)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(54)} -pin  "vin:rsc:mgc_in_wire" {z(54)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(55)} -pin  "vin:rsc:mgc_in_wire" {z(55)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(56)} -pin  "vin:rsc:mgc_in_wire" {z(56)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(57)} -pin  "vin:rsc:mgc_in_wire" {z(57)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(58)} -pin  "vin:rsc:mgc_in_wire" {z(58)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(59)} -pin  "vin:rsc:mgc_in_wire" {z(59)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(60)} -pin  "vin:rsc:mgc_in_wire" {z(60)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(61)} -pin  "vin:rsc:mgc_in_wire" {z(61)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(62)} -pin  "vin:rsc:mgc_in_wire" {z(62)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(63)} -pin  "vin:rsc:mgc_in_wire" {z(63)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(64)} -pin  "vin:rsc:mgc_in_wire" {z(64)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(65)} -pin  "vin:rsc:mgc_in_wire" {z(65)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(66)} -pin  "vin:rsc:mgc_in_wire" {z(66)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(67)} -pin  "vin:rsc:mgc_in_wire" {z(67)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(68)} -pin  "vin:rsc:mgc_in_wire" {z(68)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(69)} -pin  "vin:rsc:mgc_in_wire" {z(69)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(70)} -pin  "vin:rsc:mgc_in_wire" {z(70)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(71)} -pin  "vin:rsc:mgc_in_wire" {z(71)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(72)} -pin  "vin:rsc:mgc_in_wire" {z(72)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(73)} -pin  "vin:rsc:mgc_in_wire" {z(73)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(74)} -pin  "vin:rsc:mgc_in_wire" {z(74)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(75)} -pin  "vin:rsc:mgc_in_wire" {z(75)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(76)} -pin  "vin:rsc:mgc_in_wire" {z(76)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(77)} -pin  "vin:rsc:mgc_in_wire" {z(77)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(78)} -pin  "vin:rsc:mgc_in_wire" {z(78)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(79)} -pin  "vin:rsc:mgc_in_wire" {z(79)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(80)} -pin  "vin:rsc:mgc_in_wire" {z(80)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(81)} -pin  "vin:rsc:mgc_in_wire" {z(81)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(82)} -pin  "vin:rsc:mgc_in_wire" {z(82)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(83)} -pin  "vin:rsc:mgc_in_wire" {z(83)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(84)} -pin  "vin:rsc:mgc_in_wire" {z(84)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(85)} -pin  "vin:rsc:mgc_in_wire" {z(85)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(86)} -pin  "vin:rsc:mgc_in_wire" {z(86)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(87)} -pin  "vin:rsc:mgc_in_wire" {z(87)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(88)} -pin  "vin:rsc:mgc_in_wire" {z(88)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(89)} -pin  "vin:rsc:mgc_in_wire" {z(89)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load inst "vout:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" -attr xrf 2009 -attr oid 394 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(2,30)" -pg 1 -lvl 1002
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "vout:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "vout:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "vout:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "vout:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "vout:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "vout:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "vout:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "vout:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "vout:rsc:mgc_out_stdreg" {d(8)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "vout:rsc:mgc_out_stdreg" {d(9)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "vout:rsc:mgc_out_stdreg" {d(10)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "vout:rsc:mgc_out_stdreg" {d(11)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "vout:rsc:mgc_out_stdreg" {d(12)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "vout:rsc:mgc_out_stdreg" {d(13)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "vout:rsc:mgc_out_stdreg" {d(14)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "vout:rsc:mgc_out_stdreg" {d(15)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "vout:rsc:mgc_out_stdreg" {d(16)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "vout:rsc:mgc_out_stdreg" {d(17)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "vout:rsc:mgc_out_stdreg" {d(18)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "vout:rsc:mgc_out_stdreg" {d(19)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "vout:rsc:mgc_out_stdreg" {d(20)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "vout:rsc:mgc_out_stdreg" {d(21)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "vout:rsc:mgc_out_stdreg" {d(22)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "vout:rsc:mgc_out_stdreg" {d(23)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "vout:rsc:mgc_out_stdreg" {d(24)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "vout:rsc:mgc_out_stdreg" {d(25)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "vout:rsc:mgc_out_stdreg" {d(26)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "vout:rsc:mgc_out_stdreg" {d(27)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "vout:rsc:mgc_out_stdreg" {d(28)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "vout:rsc:mgc_out_stdreg" {d(29)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc.z(0)} -pin  "vout:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -pin  "vout:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -pin  "vout:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -pin  "vout:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -pin  "vout:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -pin  "vout:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -pin  "vout:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -pin  "vout:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -pin  "vout:rsc:mgc_out_stdreg" {z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -pin  "vout:rsc:mgc_out_stdreg" {z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -pin  "vout:rsc:mgc_out_stdreg" {z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -pin  "vout:rsc:mgc_out_stdreg" {z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -pin  "vout:rsc:mgc_out_stdreg" {z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -pin  "vout:rsc:mgc_out_stdreg" {z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -pin  "vout:rsc:mgc_out_stdreg" {z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -pin  "vout:rsc:mgc_out_stdreg" {z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -pin  "vout:rsc:mgc_out_stdreg" {z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -pin  "vout:rsc:mgc_out_stdreg" {z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -pin  "vout:rsc:mgc_out_stdreg" {z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -pin  "vout:rsc:mgc_out_stdreg" {z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -pin  "vout:rsc:mgc_out_stdreg" {z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -pin  "vout:rsc:mgc_out_stdreg" {z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -pin  "vout:rsc:mgc_out_stdreg" {z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -pin  "vout:rsc:mgc_out_stdreg" {z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -pin  "vout:rsc:mgc_out_stdreg" {z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -pin  "vout:rsc:mgc_out_stdreg" {z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -pin  "vout:rsc:mgc_out_stdreg" {z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -pin  "vout:rsc:mgc_out_stdreg" {z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -pin  "vout:rsc:mgc_out_stdreg" {z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -pin  "vout:rsc:mgc_out_stdreg" {z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+### END MODULE 
+
diff --git a/Sobel/sobel.v10/concat_rtl.v b/Sobel/sobel.v10/concat_rtl.v
new file mode 100644
index 0000000..557e0ec
--- /dev/null
+++ b/Sobel/sobel.v10/concat_rtl.v
@@ -0,0 +1,2160 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 15:50:39 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  wire and_dcpl_1;
+  wire or_dcpl_2;
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [14:0] b_1_sg1_lpi_1;
+  reg [15:0] b_0_lpi_1;
+  reg [15:0] b_2_lpi_1;
+  reg [14:0] g_1_sg1_lpi_1;
+  reg [15:0] g_0_lpi_1;
+  reg [15:0] g_2_lpi_1;
+  reg [14:0] r_1_sg1_lpi_1;
+  reg [15:0] r_0_lpi_1;
+  reg [15:0] r_2_lpi_1;
+  reg [1:0] i_6_lpi_1;
+  reg exit_FRAME_for_lpi_1;
+  reg [1:0] i_7_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [89:0] regs_regs_2_lpi_1_dfm;
+  reg exit_FRAME_lpi_1_dfm_2;
+  reg exit_FRAME_for_1_lpi_1_dfm_4;
+  reg [10:0] FRAME_mul_2_itm_1;
+  wire [21:0] nl_FRAME_mul_2_itm_1;
+  reg [8:0] FRAME_mul_3_itm_1;
+  wire [17:0] nl_FRAME_mul_3_itm_1;
+  reg [5:0] green_slc_green_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_18_itm_1;
+  wire [5:0] nl_FRAME_acc_18_itm_1;
+  reg FRAME_slc_acc_imod_11_4_itm_1;
+  reg green_slc_green_2_sg1_12_itm_1;
+  reg [10:0] FRAME_mul_4_itm_1;
+  wire [21:0] nl_FRAME_mul_4_itm_1;
+  reg [8:0] FRAME_mul_5_itm_1;
+  wire [17:0] nl_FRAME_mul_5_itm_1;
+  reg [5:0] blue_slc_blue_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_30_itm_1;
+  wire [5:0] nl_FRAME_acc_30_itm_1;
+  reg FRAME_slc_acc_imod_13_4_itm_1;
+  reg blue_slc_blue_2_sg1_12_itm_1;
+  reg [8:0] FRAME_mul_1_itm_1;
+  wire [17:0] nl_FRAME_mul_1_itm_1;
+  reg [5:0] red_slc_red_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_37_itm_1;
+  wire [5:0] nl_FRAME_acc_37_itm_1;
+  reg FRAME_slc_acc_imod_9_4_itm_1;
+  reg exit_FRAME_for_lpi_1_dfm_st_1;
+  reg exit_FRAME_for_1_sva_2_st_1;
+  reg main_stage_0_2;
+  reg [1:0] FRAME_acc_41_itm_1_sg2;
+  wire [2:0] nl_FRAME_acc_41_itm_1_sg2;
+  reg [1:0] FRAME_acc_41_itm_1_sg1;
+  reg [5:0] FRAME_acc_41_itm_3;
+  wire [6:0] nl_FRAME_acc_41_itm_3;
+  wire or_4_cse;
+  wire or_9_cse;
+  wire exit_FRAME_for_1_lpi_1_dfm_5;
+  wire [1:0] FRAME_for_1_acc_itm;
+  wire [2:0] nl_FRAME_for_1_acc_itm;
+  wire [7:0] FRAME_acc_itm;
+  wire [8:0] nl_FRAME_acc_itm;
+  wire [11:0] FRAME_acc_3_psp_sva;
+  wire [13:0] nl_FRAME_acc_3_psp_sva;
+  wire [11:0] FRAME_acc_4_psp_sva;
+  wire [13:0] nl_FRAME_acc_4_psp_sva;
+  wire exit_FRAME_for_lpi_1_dfm;
+  wire [1:0] i_7_sva;
+  wire [2:0] nl_i_7_sva;
+  wire exit_FRAME_for_1_lpi_1_dfm_4_mx0;
+  wire [89:0] regs_regs_2_lpi_1_dfm_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire exit_FRAME_lpi_1_dfm_2_mx0;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [5:0] acc_imod_9_sva;
+  wire [7:0] nl_acc_imod_9_sva;
+  wire [9:0] FRAME_mul_sdt;
+  wire [19:0] nl_FRAME_mul_sdt;
+  wire [5:0] acc_imod_13_sva;
+  wire [7:0] nl_acc_imod_13_sva;
+  wire [5:0] acc_imod_11_sva;
+  wire [7:0] nl_acc_imod_11_sva;
+  wire [14:0] b_1_sg1_lpi_1_dfm;
+  wire [15:0] b_2_sva_1;
+  wire [16:0] nl_b_2_sva_1;
+  wire [15:0] b_0_sva_1;
+  wire [16:0] nl_b_0_sva_1;
+  wire [14:0] g_1_sg1_lpi_1_dfm;
+  wire [15:0] g_2_sva_1;
+  wire [16:0] nl_g_2_sva_1;
+  wire [15:0] g_0_sva_1;
+  wire [16:0] nl_g_0_sva_1;
+  wire [14:0] r_1_sg1_lpi_1_dfm;
+  wire [15:0] r_2_sva_1;
+  wire [16:0] nl_r_2_sva_1;
+  wire [15:0] r_0_sva_1;
+  wire [16:0] nl_r_0_sva_1;
+  wire [15:0] b_2_lpi_1_dfm;
+  wire FRAME_for_1_nor_cse;
+  wire [15:0] g_2_lpi_1_dfm;
+  wire [15:0] r_2_lpi_1_dfm;
+  wire [15:0] b_0_lpi_1_dfm;
+  wire [15:0] g_0_lpi_1_dfm;
+  wire [15:0] r_0_lpi_1_dfm;
+  wire [1:0] i_6_sva_1;
+  wire [2:0] nl_i_6_sva_1;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire FRAME_for_nor_cse;
+  wire FRAME_for_and_18_seb;
+  wire [1:0] FRAME_for_acc_5_tmp;
+  wire [2:0] nl_FRAME_for_acc_5_tmp;
+  wire not_24;
+  wire [15:0] ACC2_3_acc_1_itm;
+  wire [16:0] nl_ACC2_3_acc_1_itm;
+  wire [15:0] ACC2_3_acc_3_itm;
+  wire [16:0] nl_ACC2_3_acc_3_itm;
+  wire [15:0] ACC2_3_acc_2_itm;
+  wire [16:0] nl_ACC2_3_acc_2_itm;
+  wire FRAME_for_1_or_1_itm;
+  wire FRAME_for_1_or_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_itm;
+  wire FRAME_for_or_5_itm;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+
+  wire[9:0] regs_operator_35_mux_nl;
+  wire[9:0] regs_operator_29_mux_nl;
+  wire[9:0] regs_operator_34_mux_nl;
+  wire[9:0] regs_operator_28_mux_nl;
+  wire[9:0] regs_operator_33_mux_nl;
+  wire[9:0] regs_operator_27_mux_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_3_psp_sva = (conv_u2s_11_12(FRAME_mul_2_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_3_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(green_slc_green_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_18_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_11_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({green_slc_green_2_sg1_12_itm_1
+      , 3'b0 , ({{2{green_slc_green_2_sg1_12_itm_1}}, green_slc_green_2_sg1_12_itm_1})
+      , 1'b0 , green_slc_green_2_sg1_12_itm_1}));
+  assign FRAME_acc_3_psp_sva = nl_FRAME_acc_3_psp_sva[11:0];
+  assign nl_FRAME_acc_4_psp_sva = (conv_u2s_11_12(FRAME_mul_4_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_5_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(blue_slc_blue_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_30_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_13_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({blue_slc_blue_2_sg1_12_itm_1
+      , 3'b0 , ({{2{blue_slc_blue_2_sg1_12_itm_1}}, blue_slc_blue_2_sg1_12_itm_1})
+      , 1'b0 , blue_slc_blue_2_sg1_12_itm_1}));
+  assign FRAME_acc_4_psp_sva = nl_FRAME_acc_4_psp_sva[11:0];
+  assign nl_FRAME_for_1_acc_itm = i_7_sva + 2'b1;
+  assign FRAME_for_1_acc_itm = nl_FRAME_for_1_acc_itm[1:0];
+  assign exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_lpi_1 & not_24;
+  assign nl_i_7_sva = i_7_lpi_1 + 2'b1;
+  assign i_7_sva = nl_i_7_sva[1:0];
+  assign exit_FRAME_for_1_lpi_1_dfm_4_mx0 = MUX_s_1_2_2({(exit_FRAME_for_1_lpi_1_dfm_5
+      | (FRAME_acc_itm[7])) , exit_FRAME_for_1_lpi_1_dfm_5}, or_9_cse);
+  assign regs_regs_2_lpi_1_dfm_mx0 = MUX_v_90_2_2({regs_regs_1_sva , regs_regs_2_lpi_1_dfm},
+      and_dcpl_1);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_dcpl_1);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_dcpl_1);
+  assign nl_FRAME_acc_itm = conv_u2s_7_8(FRAME_p_1_sva_1[18:12]) + 8'b10110101;
+  assign FRAME_acc_itm = nl_FRAME_acc_itm[7:0];
+  assign exit_FRAME_lpi_1_dfm_2_mx0 = MUX_s_1_2_2({(~ (FRAME_acc_itm[7])) , (exit_FRAME_lpi_1_dfm_2
+      & not_24)}, or_9_cse);
+  assign exit_FRAME_for_1_lpi_1_dfm_5 = (~ (FRAME_for_1_acc_itm[1])) & exit_FRAME_for_lpi_1_dfm;
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign nl_acc_imod_9_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC2_3_acc_1_itm[9:7])
+      + conv_u2u_3_4(~ (ACC2_3_acc_1_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC2_3_acc_1_itm[15])) , 1'b1 , (~ (ACC2_3_acc_1_itm[15]))}) + conv_u2u_2_4(ACC2_3_acc_1_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC2_3_acc_1_itm[3:1]) + conv_u2u_3_4(~ (ACC2_3_acc_1_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_9_sva = nl_acc_imod_9_sva[5:0];
+  assign nl_ACC2_3_acc_1_itm = ({(r_1_sg1_lpi_1_dfm + (r_2_sva_1[15:1])) , (r_2_sva_1[0])})
+      + r_0_sva_1;
+  assign ACC2_3_acc_1_itm = nl_ACC2_3_acc_1_itm[15:0];
+  assign nl_FRAME_mul_sdt = conv_u2u_2_10(ACC2_3_acc_1_itm[14:13]) * 10'b111000111;
+  assign FRAME_mul_sdt = nl_FRAME_mul_sdt[9:0];
+  assign nl_ACC2_3_acc_3_itm = ({(b_1_sg1_lpi_1_dfm + (b_2_sva_1[15:1])) , (b_2_sva_1[0])})
+      + b_0_sva_1;
+  assign ACC2_3_acc_3_itm = nl_ACC2_3_acc_3_itm[15:0];
+  assign nl_acc_imod_13_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC2_3_acc_3_itm[9:7])
+      + conv_u2u_3_4(~ (ACC2_3_acc_3_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC2_3_acc_3_itm[15])) , 1'b1 , (~ (ACC2_3_acc_3_itm[15]))}) + conv_u2u_2_4(ACC2_3_acc_3_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC2_3_acc_3_itm[3:1]) + conv_u2u_3_4(~ (ACC2_3_acc_3_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_13_sva = nl_acc_imod_13_sva[5:0];
+  assign nl_ACC2_3_acc_2_itm = ({(g_1_sg1_lpi_1_dfm + (g_2_sva_1[15:1])) , (g_2_sva_1[0])})
+      + g_0_sva_1;
+  assign ACC2_3_acc_2_itm = nl_ACC2_3_acc_2_itm[15:0];
+  assign nl_acc_imod_11_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC2_3_acc_2_itm[9:7])
+      + conv_u2u_3_4(~ (ACC2_3_acc_2_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC2_3_acc_2_itm[15])) , 1'b1 , (~ (ACC2_3_acc_2_itm[15]))}) + conv_u2u_2_4(ACC2_3_acc_2_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC2_3_acc_2_itm[3:1]) + conv_u2u_3_4(~ (ACC2_3_acc_2_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_11_sva = nl_acc_imod_11_sva[5:0];
+  assign b_1_sg1_lpi_1_dfm = b_1_sg1_lpi_1 & ({{14{not_24}}, not_24});
+  assign regs_operator_35_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[69:60]) , (regs_regs_1_sva[69:60])
+      , (regs_regs_2_lpi_1_dfm[69:60]) , 10'b0}, i_7_lpi_1);
+  assign nl_b_2_sva_1 = b_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_35_mux_nl)
+      * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_or_1_itm})));
+  assign b_2_sva_1 = nl_b_2_sva_1[15:0];
+  assign regs_operator_29_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[9:0]) , (regs_regs_1_sva[9:0])
+      , (regs_regs_2_lpi_1_dfm[9:0]) , 10'b0}, i_7_lpi_1);
+  assign nl_b_0_sva_1 = b_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_29_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_1_or_itm})));
+  assign b_0_sva_1 = nl_b_0_sva_1[15:0];
+  assign g_1_sg1_lpi_1_dfm = g_1_sg1_lpi_1 & ({{14{not_24}}, not_24});
+  assign regs_operator_34_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[79:70]) , (regs_regs_1_sva[79:70])
+      , (regs_regs_2_lpi_1_dfm[79:70]) , 10'b0}, i_7_lpi_1);
+  assign nl_g_2_sva_1 = g_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_34_mux_nl)
+      * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_or_1_itm})));
+  assign g_2_sva_1 = nl_g_2_sva_1[15:0];
+  assign regs_operator_28_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[19:10]) , (regs_regs_1_sva[19:10])
+      , (regs_regs_2_lpi_1_dfm[19:10]) , 10'b0}, i_7_lpi_1);
+  assign nl_g_0_sva_1 = g_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_28_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_1_or_itm})));
+  assign g_0_sva_1 = nl_g_0_sva_1[15:0];
+  assign r_1_sg1_lpi_1_dfm = r_1_sg1_lpi_1 & ({{14{not_24}}, not_24});
+  assign regs_operator_33_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[89:80]) , (regs_regs_1_sva[89:80])
+      , (regs_regs_2_lpi_1_dfm[89:80]) , 10'b0}, i_7_lpi_1);
+  assign nl_r_2_sva_1 = r_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_33_mux_nl)
+      * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_or_1_itm})));
+  assign r_2_sva_1 = nl_r_2_sva_1[15:0];
+  assign regs_operator_27_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[29:20]) , (regs_regs_1_sva[29:20])
+      , (regs_regs_2_lpi_1_dfm[29:20]) , 10'b0}, i_7_lpi_1);
+  assign nl_r_0_sva_1 = r_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_27_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_1_or_itm})));
+  assign r_0_sva_1 = nl_r_0_sva_1[15:0];
+  assign b_2_lpi_1_dfm = b_2_lpi_1 & ({{15{not_24}}, not_24});
+  assign FRAME_for_1_nor_cse = ~((i_7_lpi_1[1]) | (i_7_lpi_1[0]));
+  assign g_2_lpi_1_dfm = g_2_lpi_1 & ({{15{not_24}}, not_24});
+  assign r_2_lpi_1_dfm = r_2_lpi_1 & ({{15{not_24}}, not_24});
+  assign b_0_lpi_1_dfm = b_0_lpi_1 & ({{15{not_24}}, not_24});
+  assign g_0_lpi_1_dfm = g_0_lpi_1 & ({{15{not_24}}, not_24});
+  assign r_0_lpi_1_dfm = r_0_lpi_1 & ({{15{not_24}}, not_24});
+  assign nl_i_6_sva_1 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_1 = nl_i_6_sva_1[1:0];
+  assign i_6_lpi_1_dfm = i_6_lpi_1 & ({{1{not_24}}, not_24});
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_and_18_seb = (FRAME_for_acc_5_tmp[1]) & (FRAME_for_acc_5_tmp[0]);
+  assign nl_FRAME_for_acc_5_tmp = i_6_lpi_1_dfm + 2'b11;
+  assign FRAME_for_acc_5_tmp = nl_FRAME_for_acc_5_tmp[1:0];
+  assign not_24 = ~(exit_FRAME_for_1_lpi_1_dfm_4 | exit_FRAME_1_sva);
+  assign FRAME_for_1_or_1_itm = (~((~ (i_7_lpi_1[1])) & (i_7_lpi_1[0]))) | FRAME_for_1_nor_cse;
+  assign FRAME_for_1_or_itm = (~((i_7_lpi_1[0]) & (~ (i_7_lpi_1[1])))) | FRAME_for_1_nor_cse
+      | ((i_7_lpi_1[1]) & (~ (i_7_lpi_1[0])));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) | FRAME_for_nor_cse;
+  assign FRAME_for_or_5_itm = (FRAME_for_acc_5_tmp[1]) | (FRAME_for_acc_5_tmp[0])
+      | FRAME_for_and_18_seb;
+  assign and_dcpl_1 = ~(exit_FRAME_1_sva | exit_FRAME_for_1_lpi_1_dfm_4);
+  assign or_dcpl_2 = exit_FRAME_1_sva | exit_FRAME_for_1_lpi_1_dfm_4;
+  assign or_4_cse = or_dcpl_2 | (~ exit_FRAME_for_lpi_1);
+  assign or_9_cse = or_dcpl_2 | (~ exit_FRAME_for_lpi_1) | (FRAME_for_1_acc_itm[1]);
+  assign nl_FRAME_for_acc_itm = i_6_sva_1 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      FRAME_acc_41_itm_1_sg2 <= 2'b0;
+      FRAME_acc_41_itm_1_sg1 <= 2'b0;
+      FRAME_acc_41_itm_3 <= 6'b0;
+      FRAME_mul_1_itm_1 <= 9'b0;
+      red_slc_red_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_37_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_9_4_itm_1 <= 1'b0;
+      FRAME_mul_4_itm_1 <= 11'b0;
+      FRAME_mul_5_itm_1 <= 9'b0;
+      blue_slc_blue_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_30_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_13_4_itm_1 <= 1'b0;
+      blue_slc_blue_2_sg1_12_itm_1 <= 1'b0;
+      FRAME_mul_2_itm_1 <= 11'b0;
+      FRAME_mul_3_itm_1 <= 9'b0;
+      green_slc_green_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_18_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_11_4_itm_1 <= 1'b0;
+      green_slc_green_2_sg1_12_itm_1 <= 1'b0;
+      exit_FRAME_for_1_sva_2_st_1 <= 1'b0;
+      exit_FRAME_for_lpi_1_dfm_st_1 <= 1'b0;
+      i_7_lpi_1 <= 2'b0;
+      exit_FRAME_for_lpi_1 <= 1'b0;
+      exit_FRAME_for_1_lpi_1_dfm_4 <= 1'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_2_lpi_1_dfm <= 90'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_2 <= 1'b0;
+      b_1_sg1_lpi_1 <= 15'b0;
+      g_1_sg1_lpi_1 <= 15'b0;
+      r_1_sg1_lpi_1 <= 15'b0;
+      i_6_lpi_1 <= 2'b0;
+      b_2_lpi_1 <= 16'b0;
+      b_0_lpi_1 <= 16'b0;
+      g_2_lpi_1 <= 16'b0;
+      g_0_lpi_1 <= 16'b0;
+      r_2_lpi_1 <= 16'b0;
+      r_0_lpi_1 <= 16'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({({((({FRAME_acc_41_itm_1_sg2 ,
+            FRAME_acc_41_itm_1_sg1 , FRAME_acc_41_itm_3}) + (conv_u2s_9_10(FRAME_mul_1_itm_1)
+            + conv_s2s_8_10(conv_u2s_6_8(red_slc_red_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_37_itm_1
+            + ({4'b1001 , FRAME_slc_acc_imod_9_4_itm_1}))))) | ({8'b0 , (FRAME_acc_3_psp_sva[11:10])}))
+            , (FRAME_acc_3_psp_sva[9:6]) , ((FRAME_acc_3_psp_sva[5:0]) | ({4'b0 ,
+            (FRAME_acc_4_psp_sva[11:10])})) , (FRAME_acc_4_psp_sva[9:0])}) , vout_rsc_mgc_out_stdreg_d},
+            ~(exit_FRAME_for_1_sva_2_st_1 & exit_FRAME_for_lpi_1_dfm_st_1 & main_stage_0_2));
+        FRAME_acc_41_itm_1_sg2 <= nl_FRAME_acc_41_itm_1_sg2[1:0];
+        FRAME_acc_41_itm_1_sg1 <= FRAME_mul_sdt[7:6];
+        FRAME_acc_41_itm_3 <= nl_FRAME_acc_41_itm_3[5:0];
+        FRAME_mul_1_itm_1 <= nl_FRAME_mul_1_itm_1[8:0];
+        red_slc_red_2_sg1_itm_1 <= ACC2_3_acc_1_itm[9:4];
+        FRAME_acc_37_itm_1 <= nl_FRAME_acc_37_itm_1[4:0];
+        FRAME_slc_acc_imod_9_4_itm_1 <= acc_imod_9_sva[5];
+        FRAME_mul_4_itm_1 <= nl_FRAME_mul_4_itm_1[10:0];
+        FRAME_mul_5_itm_1 <= nl_FRAME_mul_5_itm_1[8:0];
+        blue_slc_blue_2_sg1_itm_1 <= ACC2_3_acc_3_itm[9:4];
+        FRAME_acc_30_itm_1 <= nl_FRAME_acc_30_itm_1[4:0];
+        FRAME_slc_acc_imod_13_4_itm_1 <= acc_imod_13_sva[5];
+        blue_slc_blue_2_sg1_12_itm_1 <= ACC2_3_acc_3_itm[15];
+        FRAME_mul_2_itm_1 <= nl_FRAME_mul_2_itm_1[10:0];
+        FRAME_mul_3_itm_1 <= nl_FRAME_mul_3_itm_1[8:0];
+        green_slc_green_2_sg1_itm_1 <= ACC2_3_acc_2_itm[9:4];
+        FRAME_acc_18_itm_1 <= nl_FRAME_acc_18_itm_1[4:0];
+        FRAME_slc_acc_imod_11_4_itm_1 <= acc_imod_11_sva[5];
+        green_slc_green_2_sg1_12_itm_1 <= ACC2_3_acc_2_itm[15];
+        exit_FRAME_for_1_sva_2_st_1 <= ~ (FRAME_for_1_acc_itm[1]);
+        exit_FRAME_for_lpi_1_dfm_st_1 <= exit_FRAME_for_lpi_1_dfm;
+        i_7_lpi_1 <= MUX_v_2_2_2({i_7_sva , (i_7_lpi_1 & (signext_2_1(FRAME_for_acc_itm[1])))},
+            or_4_cse);
+        exit_FRAME_for_lpi_1 <= MUX_s_1_2_2({exit_FRAME_for_lpi_1_dfm , (~ (FRAME_for_acc_itm[1]))},
+            or_4_cse);
+        exit_FRAME_for_1_lpi_1_dfm_4 <= exit_FRAME_for_1_lpi_1_dfm_4_mx0;
+        exit_FRAME_1_sva <= exit_FRAME_for_1_lpi_1_dfm_4_mx0 & exit_FRAME_lpi_1_dfm_2_mx0;
+        main_stage_0_2 <= 1'b1;
+        regs_regs_2_lpi_1_dfm <= regs_regs_2_lpi_1_dfm_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_2 <= exit_FRAME_lpi_1_dfm_2_mx0;
+        b_1_sg1_lpi_1 <= MUX_v_15_2_2({b_1_sg1_lpi_1_dfm , (b_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[39:30])
+            , (regs_regs_1_sva_dfm_mx0[39:30]) , (regs_regs_2_lpi_1_dfm_mx0[39:30])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_or_5_itm}))))},
+            or_4_cse);
+        g_1_sg1_lpi_1 <= MUX_v_15_2_2({g_1_sg1_lpi_1_dfm , (g_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[49:40])
+            , (regs_regs_1_sva_dfm_mx0[49:40]) , (regs_regs_2_lpi_1_dfm_mx0[49:40])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_or_5_itm}))))},
+            or_4_cse);
+        r_1_sg1_lpi_1 <= MUX_v_15_2_2({r_1_sg1_lpi_1_dfm , (r_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[59:50])
+            , (regs_regs_1_sva_dfm_mx0[59:50]) , (regs_regs_2_lpi_1_dfm_mx0[59:50])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_or_5_itm}))))},
+            or_4_cse);
+        i_6_lpi_1 <= MUX_v_2_2_2({i_6_lpi_1_dfm , i_6_sva_1}, or_4_cse);
+        b_2_lpi_1 <= MUX_v_16_2_2({b_2_sva_1 , (b_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+            , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_mx0[69:60])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))},
+            or_4_cse);
+        b_0_lpi_1 <= MUX_v_16_2_2({b_0_sva_1 , (b_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0])
+            , (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_mx0[9:0]) ,
+            10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_itm}))))},
+            or_4_cse);
+        g_2_lpi_1 <= MUX_v_16_2_2({g_2_sva_1 , (g_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+            , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_mx0[79:70])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))},
+            or_4_cse);
+        g_0_lpi_1 <= MUX_v_16_2_2({g_0_sva_1 , (g_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+            , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_mx0[19:10])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_itm}))))},
+            or_4_cse);
+        r_2_lpi_1 <= MUX_v_16_2_2({r_2_sva_1 , (r_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+            , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_mx0[89:80])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))},
+            or_4_cse);
+        r_0_lpi_1 <= MUX_v_16_2_2({r_0_sva_1 , (r_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+            , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_mx0[29:20])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_itm}))))},
+            or_4_cse);
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_lpi_1_dfm , FRAME_p_1_sva_1},
+            and_dcpl_1 & exit_FRAME_for_lpi_1 & (~ (FRAME_for_1_acc_itm[1])));
+      end
+    end
+  end
+  assign nl_FRAME_acc_41_itm_1_sg2  = (FRAME_mul_sdt[9:8]) + conv_s2u_1_2(ACC2_3_acc_1_itm[15]);
+  assign nl_FRAME_acc_41_itm_3  = conv_u2u_5_6(FRAME_mul_sdt[4:0]) + conv_u2u_5_6(signext_5_3({(ACC2_3_acc_1_itm[15])
+      , 1'b0 , (ACC2_3_acc_1_itm[15])}));
+  assign nl_FRAME_mul_1_itm_1  = conv_u2u_3_9(ACC2_3_acc_1_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_37_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_9_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_9_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_9_sva[5:3])) , (~ (acc_imod_9_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_9_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC2_3_acc_1_itm[9:7]));
+  assign nl_FRAME_mul_4_itm_1  = conv_u2u_2_11(ACC2_3_acc_3_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_5_itm_1  = conv_u2u_3_9(ACC2_3_acc_3_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_30_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_13_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_13_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_13_sva[5:3])) , (~ (acc_imod_13_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_13_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC2_3_acc_3_itm[9:7]));
+  assign nl_FRAME_mul_2_itm_1  = conv_u2u_2_11(ACC2_3_acc_2_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_3_itm_1  = conv_u2u_3_9(ACC2_3_acc_2_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_18_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_11_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_11_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_11_sva[5:3])) , (~ (acc_imod_11_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_11_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC2_3_acc_2_itm[9:7]));
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] MUX_v_2_2_2;
+    input [3:0] inputs;
+    input [0:0] sel;
+    reg [1:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[3:2];
+      end
+      1'b1 : begin
+        result = inputs[1:0];
+      end
+      default : begin
+        result = inputs[3:2];
+      end
+    endcase
+    MUX_v_2_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [14:0] MUX_v_15_2_2;
+    input [29:0] inputs;
+    input [0:0] sel;
+    reg [14:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[29:15];
+      end
+      1'b1 : begin
+        result = inputs[14:0];
+      end
+      default : begin
+        result = inputs[29:15];
+      end
+    endcase
+    MUX_v_15_2_2 = result;
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_11_15 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_15 = {{4{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_s2u_1_2 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_2 = {vector[0], vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v10/cycle.rpt b/Sobel/sobel.v10/cycle.rpt
new file mode 100644
index 0000000..4694937
--- /dev/null
+++ b/Sobel/sobel.v10/cycle.rpt
@@ -0,0 +1,85 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 15:50:02 +0000 2016                      
+
+Solution Settings: sobel.v10
+  Current state: schedule
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       220 1843201    1843200            0  1          
+    Design Total:                     220 1843201    1843200            0  0          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /sobel/core              
+    
+  I/O Data Ranges
+    Port       Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ---------- ---- -------- --------- --------- ------- -------- --------
+    vin:rsc.z  IN   Unsigned        90                                     
+    clk        IN   Unsigned         1                                     
+    en         IN   Unsigned         1                                     
+    arst_n     IN   Unsigned         1                                     
+    vout:rsc.z OUT  Unsigned        30                                     
+    
+  Memory Resources
+    Resource Name: /sobel/vin:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 90
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable   Indices Phys Memory Address     
+      ---------- ------- -----------------------
+      /sobel/vin    0:89 00000000-00000000 (0-0) 
+      
+    Resource Name: /sobel/vout:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 30
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable    Indices Phys Memory Address     
+      ----------- ------- -----------------------
+      /sobel/vout    0:29 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process     Loop             Iterations C-Steps Total Cycles  Duration  Unroll Init Comments 
+    ----------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
+    /sobel/core core:rlp           Infinite       0      1843202  36.86 ms                       
+    /sobel/core   main             Infinite       3      1843202  36.86 ms            1          
+    
+  Loop Execution Profile
+    Process     Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------- ---------------- ------------ -------------------------- ----------------- --------
+    /sobel/core core:rlp                   0                        0.00          1843200           
+    /sobel/core   main               1843202                      100.00          1843200           
+    
+  End of Report
diff --git a/Sobel/sobel.v10/cycle.v b/Sobel/sobel.v10/cycle.v
new file mode 100644
index 0000000..f9ee836
--- /dev/null
+++ b/Sobel/sobel.v10/cycle.v
@@ -0,0 +1,1129 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 15:50:02 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg [18:0] FRAME_p_1_lpi_1;
+    reg [14:0] b_1_sg1_lpi_1;
+    reg [15:0] b_0_lpi_1;
+    reg [15:0] b_2_lpi_1;
+    reg [14:0] g_1_sg1_lpi_1;
+    reg [15:0] g_0_lpi_1;
+    reg [15:0] g_2_lpi_1;
+    reg [14:0] r_1_sg1_lpi_1;
+    reg [15:0] r_0_lpi_1;
+    reg [15:0] r_2_lpi_1;
+    reg [1:0] i_6_lpi_1;
+    reg exit_FRAME_for_lpi_1;
+    reg [1:0] i_7_lpi_1;
+    reg [89:0] regs_regs_1_sva;
+    reg [89:0] regs_regs_0_sva;
+    reg exit_FRAME_1_sva;
+    reg [18:0] FRAME_p_1_lpi_1_dfm;
+    reg exit_FRAME_for_1_lpi_1_dfm;
+    reg [89:0] regs_regs_0_sva_dfm;
+    reg [89:0] regs_regs_1_sva_dfm;
+    reg [89:0] regs_regs_2_lpi_1_dfm;
+    reg [15:0] r_0_lpi_1_dfm;
+    reg [15:0] r_2_lpi_1_dfm;
+    reg [15:0] g_0_lpi_1_dfm;
+    reg [15:0] g_2_lpi_1_dfm;
+    reg [15:0] b_0_lpi_1_dfm;
+    reg [15:0] b_2_lpi_1_dfm;
+    reg [1:0] i_6_lpi_1_dfm;
+    reg [14:0] r_1_sg1_lpi_1_dfm;
+    reg [14:0] g_1_sg1_lpi_1_dfm;
+    reg [14:0] b_1_sg1_lpi_1_dfm;
+    reg exit_FRAME_lpi_1_dfm;
+    reg exit_FRAME_for_lpi_1_dfm;
+    reg FRAME_for_1_slc_YMATRIX_rom_11_psp_sva;
+    reg [15:0] r_0_sva_1;
+    reg [15:0] g_0_sva_1;
+    reg [15:0] b_0_sva_1;
+    reg [15:0] r_2_sva_1;
+    reg [15:0] g_2_sva_1;
+    reg [15:0] b_2_sva_1;
+    reg [1:0] i_7_sva;
+    reg exit_FRAME_for_1_sva_2;
+    reg [14:0] red_2_sg1_sva;
+    reg [14:0] green_2_sg1_sva;
+    reg [14:0] blue_2_sg1_sva;
+    reg [5:0] acc_imod_9_sva;
+    reg [5:0] acc_imod_11_sva;
+    reg [11:0] FRAME_acc_3_psp_sva;
+    reg [5:0] acc_imod_13_sva;
+    reg [11:0] FRAME_acc_4_psp_sva;
+    reg [18:0] FRAME_p_1_sva_1;
+    reg [15:0] r_0_sva_2;
+    reg [15:0] g_0_sva_2;
+    reg [15:0] b_0_sva_2;
+    reg [14:0] r_1_sg1_sva_1;
+    reg [14:0] g_1_sg1_sva_1;
+    reg [14:0] b_1_sg1_sva_1;
+    reg [15:0] r_2_sva_2;
+    reg [15:0] g_2_sva_2;
+    reg [15:0] b_2_sva_2;
+    reg [1:0] i_6_sva_1;
+    reg exit_FRAME_for_sva_1;
+    reg [1:0] i_7_lpi_1_dfm;
+    reg exit_FRAME_lpi_1_dfm_2;
+    reg exit_FRAME_for_1_lpi_1_dfm_2;
+    reg exit_FRAME_for_1_lpi_1_dfm_4;
+    reg [1:0] FRAME_for_acc_5_tmp;
+    reg exit_FRAME_for_1_sva_2_st;
+    reg [10:0] FRAME_mul_2_itm;
+    reg [10:0] FRAME_mul_2_itm_1;
+    reg [8:0] FRAME_mul_3_itm;
+    reg [8:0] FRAME_mul_3_itm_1;
+    reg [5:0] green_slc_green_2_sg1_itm;
+    reg [5:0] green_slc_green_2_sg1_itm_1;
+    reg [4:0] FRAME_acc_18_itm;
+    reg [4:0] FRAME_acc_18_itm_1;
+    reg FRAME_slc_acc_imod_11_4_itm;
+    reg FRAME_slc_acc_imod_11_4_itm_1;
+    reg green_slc_green_2_sg1_12_itm;
+    reg green_slc_green_2_sg1_12_itm_1;
+    reg green_slc_green_2_sg1_13_itm;
+    reg green_slc_green_2_sg1_13_itm_1;
+    reg green_slc_green_2_sg1_8_itm;
+    reg green_slc_green_2_sg1_8_itm_1;
+    reg [10:0] FRAME_mul_4_itm;
+    reg [10:0] FRAME_mul_4_itm_1;
+    reg [8:0] FRAME_mul_5_itm;
+    reg [8:0] FRAME_mul_5_itm_1;
+    reg [5:0] blue_slc_blue_2_sg1_itm;
+    reg [5:0] blue_slc_blue_2_sg1_itm_1;
+    reg [4:0] FRAME_acc_30_itm;
+    reg [4:0] FRAME_acc_30_itm_1;
+    reg FRAME_slc_acc_imod_13_4_itm;
+    reg FRAME_slc_acc_imod_13_4_itm_1;
+    reg blue_slc_blue_2_sg1_12_itm;
+    reg blue_slc_blue_2_sg1_12_itm_1;
+    reg blue_slc_blue_2_sg1_13_itm;
+    reg blue_slc_blue_2_sg1_13_itm_1;
+    reg blue_slc_blue_2_sg1_8_itm;
+    reg blue_slc_blue_2_sg1_8_itm_1;
+    reg [8:0] FRAME_mul_1_itm;
+    reg [8:0] FRAME_mul_1_itm_1;
+    reg [5:0] red_slc_red_2_sg1_itm;
+    reg [5:0] red_slc_red_2_sg1_itm_1;
+    reg [4:0] FRAME_acc_37_itm;
+    reg [4:0] FRAME_acc_37_itm_1;
+    reg FRAME_slc_acc_imod_9_4_itm;
+    reg FRAME_slc_acc_imod_9_4_itm_1;
+    reg exit_FRAME_for_lpi_1_dfm_st_1;
+    reg exit_FRAME_for_1_sva_2_st_1;
+    reg main_stage_0_2;
+    reg [9:0] FRAME_mul_sdt;
+    reg FRAME_for_1_nor_cse;
+    reg FRAME_for_nor_cse;
+    reg FRAME_for_1_slc_XMATRIX_rom_11_psp_sva_1;
+    reg FRAME_for_slc_XMATRIX_rom_11_psp_sva_1;
+    reg FRAME_for_and_18_seb;
+    reg FRAME_for_slc_XMATRIX_rom_11_1_psp_sva_1;
+    reg FRAME_for_slc_XMATRIX_rom_11_2_psp_sva_1;
+    reg [1:0] FRAME_acc_41_itm_sg2;
+    reg [1:0] FRAME_acc_41_itm_sg1;
+    reg [5:0] FRAME_acc_41_itm_2;
+    reg [1:0] FRAME_acc_41_itm_1_sg2;
+    reg [1:0] FRAME_acc_41_itm_1_sg1;
+    reg [5:0] FRAME_acc_41_itm_3;
+
+    reg[9:0] regs_operator_27_mux_nl;
+    reg[9:0] regs_operator_28_mux_nl;
+    reg[9:0] regs_operator_29_mux_nl;
+    reg[9:0] regs_operator_33_mux_nl;
+    reg[9:0] regs_operator_34_mux_nl;
+    reg[9:0] regs_operator_35_mux_nl;
+    reg[9:0] regs_operator_18_mux_nl;
+    reg[9:0] regs_operator_19_mux_nl;
+    reg[9:0] regs_operator_20_mux_nl;
+    reg[9:0] regs_operator_21_mux_nl;
+    reg[9:0] regs_operator_22_mux_nl;
+    reg[9:0] regs_operator_23_mux_nl;
+    reg[9:0] regs_operator_24_mux_nl;
+    reg[9:0] regs_operator_25_mux_nl;
+    reg[9:0] regs_operator_26_mux_nl;
+    begin : core_rlpExit
+      forever begin : core_rlp
+        // C-Step 0 of Loop 'core_rlp'
+        i_7_lpi_1 = 2'b0;
+        exit_FRAME_for_lpi_1 = 1'b0;
+        i_6_lpi_1 = 2'b0;
+        r_2_lpi_1 = 16'b0;
+        r_0_lpi_1 = 16'b0;
+        r_1_sg1_lpi_1 = 15'b0;
+        g_2_lpi_1 = 16'b0;
+        g_0_lpi_1 = 16'b0;
+        g_1_sg1_lpi_1 = 15'b0;
+        b_2_lpi_1 = 16'b0;
+        b_0_lpi_1 = 16'b0;
+        b_1_sg1_lpi_1 = 15'b0;
+        FRAME_p_1_lpi_1 = 19'b0;
+        regs_regs_1_sva = 90'b0;
+        regs_regs_0_sva = 90'b0;
+        exit_FRAME_1_sva = 1'b1;
+        main_stage_0_2 = 1'b0;
+        begin : mainExit
+          forever begin : main
+            // C-Step 0 of Loop 'main'
+            begin : waitLoop0Exit
+              forever begin : waitLoop0
+                @(posedge clk or negedge ( arst_n ));
+                if ( ~ arst_n )
+                  disable core_rlpExit;
+                if ( en )
+                  disable waitLoop0Exit;
+              end
+            end
+            // C-Step 1 of Loop 'main'
+            if ( main_stage_0_2 ) begin
+              if ( exit_FRAME_for_lpi_1_dfm_st_1 ) begin
+                if ( exit_FRAME_for_1_sva_2_st_1 ) begin
+                  FRAME_acc_3_psp_sva = (conv_u2s_11_12(FRAME_mul_2_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_3_itm_1)
+                      + conv_s2s_8_10(conv_u2s_6_8(green_slc_green_2_sg1_itm_1) +
+                      conv_s2s_5_8(FRAME_acc_18_itm_1 + ({4'b1001 , FRAME_slc_acc_imod_11_4_itm_1})))))
+                      + conv_u2u_11_12(signext_11_9({green_slc_green_2_sg1_12_itm_1
+                      , 3'b0 , ({{2{green_slc_green_2_sg1_13_itm_1}}, green_slc_green_2_sg1_13_itm_1})
+                      , 1'b0 , green_slc_green_2_sg1_8_itm_1}));
+                  FRAME_acc_4_psp_sva = (conv_u2s_11_12(FRAME_mul_4_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_5_itm_1)
+                      + conv_s2s_8_10(conv_u2s_6_8(blue_slc_blue_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_30_itm_1
+                      + ({4'b1001 , FRAME_slc_acc_imod_13_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({blue_slc_blue_2_sg1_12_itm_1
+                      , 3'b0 , ({{2{blue_slc_blue_2_sg1_13_itm_1}}, blue_slc_blue_2_sg1_13_itm_1})
+                      , 1'b0 , blue_slc_blue_2_sg1_8_itm_1}));
+                  vout_rsc_mgc_out_stdreg_d <= {((({FRAME_acc_41_itm_1_sg2 , FRAME_acc_41_itm_1_sg1
+                      , FRAME_acc_41_itm_3}) + (conv_u2s_9_10(FRAME_mul_1_itm_1)
+                      + conv_s2s_8_10(conv_u2s_6_8(red_slc_red_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_37_itm_1
+                      + ({4'b1001 , FRAME_slc_acc_imod_9_4_itm_1}))))) | ({8'b0,
+                      FRAME_acc_3_psp_sva[11:10]})) , (FRAME_acc_3_psp_sva[9:6])
+                      , ((FRAME_acc_3_psp_sva[5:0]) | ({4'b0, FRAME_acc_4_psp_sva[11:10]}))
+                      , (FRAME_acc_4_psp_sva[9:0])};
+                end
+              end
+            end
+            i_7_lpi_1_dfm = 2'b0;
+            exit_FRAME_for_sva_1 = 1'b0;
+            i_6_sva_1 = 2'b0;
+            b_2_sva_2 = 16'b0;
+            g_2_sva_2 = 16'b0;
+            r_2_sva_2 = 16'b0;
+            b_1_sg1_sva_1 = 15'b0;
+            g_1_sg1_sva_1 = 15'b0;
+            r_1_sg1_sva_1 = 15'b0;
+            b_0_sva_2 = 16'b0;
+            g_0_sva_2 = 16'b0;
+            r_0_sva_2 = 16'b0;
+            FRAME_p_1_sva_1 = 19'b0;
+            exit_FRAME_for_1_sva_2 = 1'b0;
+            i_7_sva = 2'b0;
+            b_2_sva_1 = 16'b0;
+            g_2_sva_1 = 16'b0;
+            r_2_sva_1 = 16'b0;
+            b_0_sva_1 = 16'b0;
+            g_0_sva_1 = 16'b0;
+            r_0_sva_1 = 16'b0;
+            FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+            exit_FRAME_for_1_lpi_1_dfm = exit_FRAME_for_1_lpi_1_dfm_4 | exit_FRAME_1_sva;
+            if ( exit_FRAME_for_1_lpi_1_dfm ) begin
+              regs_regs_0_sva_dfm = vin_rsc_mgc_in_wire_d;
+              regs_regs_1_sva_dfm = regs_regs_0_sva;
+              regs_regs_2_lpi_1_dfm = regs_regs_1_sva;
+            end
+            else begin
+              regs_regs_0_sva_dfm = regs_regs_0_sva;
+              regs_regs_1_sva_dfm = regs_regs_1_sva;
+            end
+            r_0_lpi_1_dfm = r_0_lpi_1 & (signext_16_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            r_2_lpi_1_dfm = r_2_lpi_1 & (signext_16_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            g_0_lpi_1_dfm = g_0_lpi_1 & (signext_16_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            g_2_lpi_1_dfm = g_2_lpi_1 & (signext_16_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            b_0_lpi_1_dfm = b_0_lpi_1 & (signext_16_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            b_2_lpi_1_dfm = b_2_lpi_1 & (signext_16_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            i_6_lpi_1_dfm = i_6_lpi_1 & (signext_2_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            r_1_sg1_lpi_1_dfm = r_1_sg1_lpi_1 & (signext_15_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            g_1_sg1_lpi_1_dfm = g_1_sg1_lpi_1 & (signext_15_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            b_1_sg1_lpi_1_dfm = b_1_sg1_lpi_1 & (signext_15_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            exit_FRAME_lpi_1_dfm = exit_FRAME_lpi_1_dfm_2 & (~ exit_FRAME_for_1_lpi_1_dfm);
+            exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_lpi_1 & (~ exit_FRAME_for_1_lpi_1_dfm);
+            if ( exit_FRAME_for_lpi_1_dfm ) begin
+              FRAME_for_1_nor_cse = ~((i_7_lpi_1[1]) | (i_7_lpi_1[0]));
+              FRAME_for_1_slc_YMATRIX_rom_11_psp_sva = (~((i_7_lpi_1[0]) & (~ (i_7_lpi_1[1]))))
+                  | FRAME_for_1_nor_cse | ((i_7_lpi_1[1]) & (~ (i_7_lpi_1[0])));
+              regs_operator_27_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[29:20])
+                  , (regs_regs_1_sva_dfm[29:20]) , (regs_regs_2_lpi_1_dfm[29:20])
+                  , 10'b0}, i_7_lpi_1);
+              r_0_sva_1 = r_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_27_mux_nl)
+                  * conv_s2s_2_12({1'b1 , FRAME_for_1_slc_YMATRIX_rom_11_psp_sva})));
+              regs_operator_28_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[19:10])
+                  , (regs_regs_1_sva_dfm[19:10]) , (regs_regs_2_lpi_1_dfm[19:10])
+                  , 10'b0}, i_7_lpi_1);
+              g_0_sva_1 = g_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_28_mux_nl)
+                  * conv_s2s_2_12({1'b1 , FRAME_for_1_slc_YMATRIX_rom_11_psp_sva})));
+              regs_operator_29_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[9:0])
+                  , (regs_regs_1_sva_dfm[9:0]) , (regs_regs_2_lpi_1_dfm[9:0]) , 10'b0},
+                  i_7_lpi_1);
+              b_0_sva_1 = b_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_29_mux_nl)
+                  * conv_s2s_2_12({1'b1 , FRAME_for_1_slc_YMATRIX_rom_11_psp_sva})));
+              FRAME_for_1_slc_XMATRIX_rom_11_psp_sva_1 = (~((~ (i_7_lpi_1[1])) &
+                  (i_7_lpi_1[0]))) | FRAME_for_1_nor_cse;
+              regs_operator_33_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[89:80])
+                  , (regs_regs_1_sva_dfm[89:80]) , (regs_regs_2_lpi_1_dfm[89:80])
+                  , 10'b0}, i_7_lpi_1);
+              r_2_sva_1 = r_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_33_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_slc_XMATRIX_rom_11_psp_sva_1})));
+              regs_operator_34_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[79:70])
+                  , (regs_regs_1_sva_dfm[79:70]) , (regs_regs_2_lpi_1_dfm[79:70])
+                  , 10'b0}, i_7_lpi_1);
+              g_2_sva_1 = g_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_34_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_slc_XMATRIX_rom_11_psp_sva_1})));
+              regs_operator_35_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[69:60])
+                  , (regs_regs_1_sva_dfm[69:60]) , (regs_regs_2_lpi_1_dfm[69:60])
+                  , 10'b0}, i_7_lpi_1);
+              b_2_sva_1 = b_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_35_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_slc_XMATRIX_rom_11_psp_sva_1})));
+              i_7_sva = i_7_lpi_1 + 2'b1;
+              exit_FRAME_for_1_sva_2 = ~ (readslicef_3_1_2((({1'b1 , i_7_sva}) +
+                  3'b1)));
+              exit_FRAME_for_1_sva_2_st = exit_FRAME_for_1_sva_2;
+              if ( exit_FRAME_for_1_sva_2 ) begin
+                red_2_sg1_sva = readslicef_16_15_1((({(r_1_sg1_lpi_1_dfm + (r_2_sva_1[15:1]))
+                    , (r_2_sva_1[0])}) + r_0_sva_1));
+                green_2_sg1_sva = readslicef_16_15_1((({(g_1_sg1_lpi_1_dfm + (g_2_sva_1[15:1]))
+                    , (g_2_sva_1[0])}) + g_0_sva_1));
+                blue_2_sg1_sva = readslicef_16_15_1((({(b_1_sg1_lpi_1_dfm + (b_2_sva_1[15:1]))
+                    , (b_2_sva_1[0])}) + b_0_sva_1));
+                acc_imod_9_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(red_2_sg1_sva[8:6])
+                    + conv_u2u_3_4(~ (red_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                    (red_2_sg1_sva[14])) , 1'b1 , (~ (red_2_sg1_sva[14]))}) + conv_u2u_2_4(red_2_sg1_sva[13:12])))
+                    + conv_u2u_4_6(conv_u2u_3_4(red_2_sg1_sva[2:0]) + conv_u2u_3_4(~
+                    (red_2_sg1_sva[5:3])))) + 6'b101011;
+                acc_imod_11_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(green_2_sg1_sva[8:6])
+                    + conv_u2u_3_4(~ (green_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                    (green_2_sg1_sva[14])) , 1'b1 , (~ (green_2_sg1_sva[14]))}) +
+                    conv_u2u_2_4(green_2_sg1_sva[13:12]))) + conv_u2u_4_6(conv_u2u_3_4(green_2_sg1_sva[2:0])
+                    + conv_u2u_3_4(~ (green_2_sg1_sva[5:3])))) + 6'b101011;
+                FRAME_mul_2_itm = conv_u2u_22_11(conv_u2u_2_11(green_2_sg1_sva[13:12])
+                    * 11'b111000111);
+                FRAME_mul_3_itm = conv_u2u_18_9(conv_u2u_3_9(green_2_sg1_sva[11:9])
+                    * 9'b111001);
+                green_slc_green_2_sg1_itm = green_2_sg1_sva[8:3];
+                FRAME_acc_18_itm = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_11_sva[5]))
+                    , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_11_sva[2:0])
+                    , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_11_sva[5:3])) , (~ (acc_imod_11_sva[5]))})))))})
+                    + conv_u2u_2_4(acc_imod_11_sva[4:3])) + conv_u2u_3_5(~ (green_2_sg1_sva[8:6]));
+                FRAME_slc_acc_imod_11_4_itm = acc_imod_11_sva[5];
+                green_slc_green_2_sg1_12_itm = green_2_sg1_sva[14];
+                green_slc_green_2_sg1_13_itm = green_2_sg1_sva[14];
+                green_slc_green_2_sg1_8_itm = green_2_sg1_sva[14];
+                acc_imod_13_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(blue_2_sg1_sva[8:6])
+                    + conv_u2u_3_4(~ (blue_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                    (blue_2_sg1_sva[14])) , 1'b1 , (~ (blue_2_sg1_sva[14]))}) + conv_u2u_2_4(blue_2_sg1_sva[13:12])))
+                    + conv_u2u_4_6(conv_u2u_3_4(blue_2_sg1_sva[2:0]) + conv_u2u_3_4(~
+                    (blue_2_sg1_sva[5:3])))) + 6'b101011;
+                FRAME_mul_4_itm = conv_u2u_22_11(conv_u2u_2_11(blue_2_sg1_sva[13:12])
+                    * 11'b111000111);
+                FRAME_mul_5_itm = conv_u2u_18_9(conv_u2u_3_9(blue_2_sg1_sva[11:9])
+                    * 9'b111001);
+                blue_slc_blue_2_sg1_itm = blue_2_sg1_sva[8:3];
+                FRAME_acc_30_itm = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_13_sva[5]))
+                    , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_13_sva[2:0])
+                    , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_13_sva[5:3])) , (~ (acc_imod_13_sva[5]))})))))})
+                    + conv_u2u_2_4(acc_imod_13_sva[4:3])) + conv_u2u_3_5(~ (blue_2_sg1_sva[8:6]));
+                FRAME_slc_acc_imod_13_4_itm = acc_imod_13_sva[5];
+                blue_slc_blue_2_sg1_12_itm = blue_2_sg1_sva[14];
+                blue_slc_blue_2_sg1_13_itm = blue_2_sg1_sva[14];
+                blue_slc_blue_2_sg1_8_itm = blue_2_sg1_sva[14];
+                FRAME_mul_sdt = conv_u2u_20_10(conv_u2u_2_10(red_2_sg1_sva[13:12])
+                    * 10'b111000111);
+                FRAME_acc_41_itm_sg1 = FRAME_mul_sdt[7:6];
+                FRAME_acc_41_itm_2 = conv_u2u_5_6(FRAME_mul_sdt[4:0]) + conv_u2u_5_6(signext_5_3({(red_2_sg1_sva[14])
+                    , 1'b0 , (red_2_sg1_sva[14])}));
+                FRAME_acc_41_itm_sg2 = (FRAME_mul_sdt[9:8]) + conv_s2u_1_2(red_2_sg1_sva[14]);
+                FRAME_mul_1_itm = conv_u2u_18_9(conv_u2u_3_9(red_2_sg1_sva[11:9])
+                    * 9'b111001);
+                red_slc_red_2_sg1_itm = red_2_sg1_sva[8:3];
+                FRAME_acc_37_itm = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_9_sva[5]))
+                    , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_9_sva[2:0])
+                    , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_9_sva[5:3])) , (~ (acc_imod_9_sva[5]))})))))})
+                    + conv_u2u_2_4(acc_imod_9_sva[4:3])) + conv_u2u_3_5(~ (red_2_sg1_sva[8:6]));
+                FRAME_slc_acc_imod_9_4_itm = acc_imod_9_sva[5];
+                FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+                exit_FRAME_lpi_1_dfm_2 = ~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+                    + 8'b10110101)));
+              end
+              else begin
+                exit_FRAME_lpi_1_dfm_2 = exit_FRAME_lpi_1_dfm;
+              end
+            end
+            else begin
+              FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+              FRAME_for_slc_XMATRIX_rom_11_psp_sva_1 = (~((i_6_lpi_1_dfm[0]) & (~
+                  (i_6_lpi_1_dfm[1])))) | FRAME_for_nor_cse;
+              regs_operator_18_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[29:20])
+                  , (regs_regs_1_sva_dfm[29:20]) , (regs_regs_2_lpi_1_dfm[29:20])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              r_0_sva_2 = r_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_18_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+              regs_operator_19_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[19:10])
+                  , (regs_regs_1_sva_dfm[19:10]) , (regs_regs_2_lpi_1_dfm[19:10])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              g_0_sva_2 = g_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_19_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+              regs_operator_20_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[9:0])
+                  , (regs_regs_1_sva_dfm[9:0]) , (regs_regs_2_lpi_1_dfm[9:0]) , 10'b0},
+                  i_6_lpi_1_dfm);
+              b_0_sva_2 = b_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_20_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+              FRAME_for_acc_5_tmp = i_6_lpi_1_dfm + 2'b11;
+              FRAME_for_and_18_seb = (FRAME_for_acc_5_tmp[1]) & (FRAME_for_acc_5_tmp[0]);
+              FRAME_for_slc_XMATRIX_rom_11_1_psp_sva_1 = (FRAME_for_acc_5_tmp[1])
+                  | (FRAME_for_acc_5_tmp[0]) | FRAME_for_and_18_seb;
+              regs_operator_21_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[59:50])
+                  , (regs_regs_1_sva_dfm[59:50]) , (regs_regs_2_lpi_1_dfm[59:50])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              r_1_sg1_sva_1 = r_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(regs_operator_21_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_slc_XMATRIX_rom_11_1_psp_sva_1})));
+              regs_operator_22_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[49:40])
+                  , (regs_regs_1_sva_dfm[49:40]) , (regs_regs_2_lpi_1_dfm[49:40])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              g_1_sg1_sva_1 = g_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(regs_operator_22_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_slc_XMATRIX_rom_11_1_psp_sva_1})));
+              regs_operator_23_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[39:30])
+                  , (regs_regs_1_sva_dfm[39:30]) , (regs_regs_2_lpi_1_dfm[39:30])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              b_1_sg1_sva_1 = b_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(regs_operator_23_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_slc_XMATRIX_rom_11_1_psp_sva_1})));
+              FRAME_for_slc_XMATRIX_rom_11_2_psp_sva_1 = (~((~ (i_6_lpi_1_dfm[1]))
+                  & (i_6_lpi_1_dfm[0]))) | FRAME_for_nor_cse;
+              regs_operator_24_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[89:80])
+                  , (regs_regs_1_sva_dfm[89:80]) , (regs_regs_2_lpi_1_dfm[89:80])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              r_2_sva_2 = r_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_24_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_2_psp_sva_1})));
+              regs_operator_25_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[79:70])
+                  , (regs_regs_1_sva_dfm[79:70]) , (regs_regs_2_lpi_1_dfm[79:70])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              g_2_sva_2 = g_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_25_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_2_psp_sva_1})));
+              regs_operator_26_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[69:60])
+                  , (regs_regs_1_sva_dfm[69:60]) , (regs_regs_2_lpi_1_dfm[69:60])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              b_2_sva_2 = b_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_26_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_2_psp_sva_1})));
+              i_6_sva_1 = i_6_lpi_1_dfm + 2'b1;
+              exit_FRAME_for_sva_1 = ~ (readslicef_3_1_2((({1'b1 , i_6_sva_1}) +
+                  3'b1)));
+              i_7_lpi_1_dfm = i_7_lpi_1 & (signext_2_1(~ exit_FRAME_for_sva_1));
+              exit_FRAME_lpi_1_dfm_2 = exit_FRAME_lpi_1_dfm;
+            end
+            exit_FRAME_for_1_lpi_1_dfm_2 = exit_FRAME_for_1_sva_2 & exit_FRAME_for_lpi_1_dfm;
+            exit_FRAME_for_1_lpi_1_dfm_4 = MUX_s_1_2_2({exit_FRAME_for_1_lpi_1_dfm_2
+                , (exit_FRAME_for_1_lpi_1_dfm_2 | (~ exit_FRAME_lpi_1_dfm_2))}, exit_FRAME_for_1_lpi_1_dfm_2);
+            regs_regs_0_sva = regs_regs_0_sva_dfm;
+            regs_regs_1_sva = regs_regs_1_sva_dfm;
+            r_0_lpi_1 = MUX_v_16_2_2({r_0_sva_2 , r_0_sva_1}, exit_FRAME_for_lpi_1_dfm);
+            r_2_lpi_1 = MUX_v_16_2_2({r_2_sva_2 , r_2_sva_1}, exit_FRAME_for_lpi_1_dfm);
+            g_0_lpi_1 = MUX_v_16_2_2({g_0_sva_2 , g_0_sva_1}, exit_FRAME_for_lpi_1_dfm);
+            g_2_lpi_1 = MUX_v_16_2_2({g_2_sva_2 , g_2_sva_1}, exit_FRAME_for_lpi_1_dfm);
+            b_0_lpi_1 = MUX_v_16_2_2({b_0_sva_2 , b_0_sva_1}, exit_FRAME_for_lpi_1_dfm);
+            b_2_lpi_1 = MUX_v_16_2_2({b_2_sva_2 , b_2_sva_1}, exit_FRAME_for_lpi_1_dfm);
+            FRAME_p_1_lpi_1 = MUX_v_19_2_2({FRAME_p_1_sva_1 , FRAME_p_1_lpi_1_dfm},
+                ~(exit_FRAME_for_1_sva_2 & exit_FRAME_for_lpi_1_dfm));
+            i_6_lpi_1 = MUX_v_2_2_2({i_6_sva_1 , i_6_lpi_1_dfm}, exit_FRAME_for_lpi_1_dfm);
+            i_7_lpi_1 = MUX_v_2_2_2({i_7_lpi_1_dfm , i_7_sva}, exit_FRAME_for_lpi_1_dfm);
+            r_1_sg1_lpi_1 = MUX_v_15_2_2({r_1_sg1_sva_1 , r_1_sg1_lpi_1_dfm}, exit_FRAME_for_lpi_1_dfm);
+            g_1_sg1_lpi_1 = MUX_v_15_2_2({g_1_sg1_sva_1 , g_1_sg1_lpi_1_dfm}, exit_FRAME_for_lpi_1_dfm);
+            b_1_sg1_lpi_1 = MUX_v_15_2_2({b_1_sg1_sva_1 , b_1_sg1_lpi_1_dfm}, exit_FRAME_for_lpi_1_dfm);
+            exit_FRAME_for_lpi_1 = MUX_s_1_2_2({exit_FRAME_for_sva_1 , exit_FRAME_for_lpi_1_dfm},
+                exit_FRAME_for_lpi_1_dfm);
+            exit_FRAME_1_sva = exit_FRAME_for_1_lpi_1_dfm_4 & exit_FRAME_lpi_1_dfm_2;
+            FRAME_mul_2_itm_1 = FRAME_mul_2_itm;
+            FRAME_mul_3_itm_1 = FRAME_mul_3_itm;
+            green_slc_green_2_sg1_itm_1 = green_slc_green_2_sg1_itm;
+            FRAME_acc_18_itm_1 = FRAME_acc_18_itm;
+            FRAME_slc_acc_imod_11_4_itm_1 = FRAME_slc_acc_imod_11_4_itm;
+            green_slc_green_2_sg1_12_itm_1 = green_slc_green_2_sg1_12_itm;
+            green_slc_green_2_sg1_13_itm_1 = green_slc_green_2_sg1_13_itm;
+            green_slc_green_2_sg1_8_itm_1 = green_slc_green_2_sg1_8_itm;
+            FRAME_mul_4_itm_1 = FRAME_mul_4_itm;
+            FRAME_mul_5_itm_1 = FRAME_mul_5_itm;
+            blue_slc_blue_2_sg1_itm_1 = blue_slc_blue_2_sg1_itm;
+            FRAME_acc_30_itm_1 = FRAME_acc_30_itm;
+            FRAME_slc_acc_imod_13_4_itm_1 = FRAME_slc_acc_imod_13_4_itm;
+            blue_slc_blue_2_sg1_12_itm_1 = blue_slc_blue_2_sg1_12_itm;
+            blue_slc_blue_2_sg1_13_itm_1 = blue_slc_blue_2_sg1_13_itm;
+            blue_slc_blue_2_sg1_8_itm_1 = blue_slc_blue_2_sg1_8_itm;
+            FRAME_acc_41_itm_1_sg1 = FRAME_acc_41_itm_sg1;
+            FRAME_acc_41_itm_3 = FRAME_acc_41_itm_2;
+            FRAME_acc_41_itm_1_sg2 = FRAME_acc_41_itm_sg2;
+            FRAME_mul_1_itm_1 = FRAME_mul_1_itm;
+            red_slc_red_2_sg1_itm_1 = red_slc_red_2_sg1_itm;
+            FRAME_acc_37_itm_1 = FRAME_acc_37_itm;
+            FRAME_slc_acc_imod_9_4_itm_1 = FRAME_slc_acc_imod_9_4_itm;
+            exit_FRAME_for_lpi_1_dfm_st_1 = exit_FRAME_for_lpi_1_dfm;
+            exit_FRAME_for_1_sva_2_st_1 = exit_FRAME_for_1_sva_2_st;
+            main_stage_0_2 = 1'b1;
+          end
+        end
+      end
+    end
+    FRAME_acc_41_itm_3 = 6'b0;
+    FRAME_acc_41_itm_1_sg1 = 2'b0;
+    FRAME_acc_41_itm_1_sg2 = 2'b0;
+    FRAME_acc_41_itm_2 = 6'b0;
+    FRAME_acc_41_itm_sg1 = 2'b0;
+    FRAME_acc_41_itm_sg2 = 2'b0;
+    FRAME_for_slc_XMATRIX_rom_11_2_psp_sva_1 = 1'b0;
+    FRAME_for_slc_XMATRIX_rom_11_1_psp_sva_1 = 1'b0;
+    FRAME_for_and_18_seb = 1'b0;
+    FRAME_for_slc_XMATRIX_rom_11_psp_sva_1 = 1'b0;
+    FRAME_for_1_slc_XMATRIX_rom_11_psp_sva_1 = 1'b0;
+    FRAME_for_nor_cse = 1'b0;
+    FRAME_for_1_nor_cse = 1'b0;
+    FRAME_mul_sdt = 10'b0;
+    main_stage_0_2 = 1'b0;
+    exit_FRAME_for_1_sva_2_st_1 = 1'b0;
+    exit_FRAME_for_lpi_1_dfm_st_1 = 1'b0;
+    FRAME_slc_acc_imod_9_4_itm_1 = 1'b0;
+    FRAME_slc_acc_imod_9_4_itm = 1'b0;
+    FRAME_acc_37_itm_1 = 5'b0;
+    FRAME_acc_37_itm = 5'b0;
+    red_slc_red_2_sg1_itm_1 = 6'b0;
+    red_slc_red_2_sg1_itm = 6'b0;
+    FRAME_mul_1_itm_1 = 9'b0;
+    FRAME_mul_1_itm = 9'b0;
+    blue_slc_blue_2_sg1_8_itm_1 = 1'b0;
+    blue_slc_blue_2_sg1_8_itm = 1'b0;
+    blue_slc_blue_2_sg1_13_itm_1 = 1'b0;
+    blue_slc_blue_2_sg1_13_itm = 1'b0;
+    blue_slc_blue_2_sg1_12_itm_1 = 1'b0;
+    blue_slc_blue_2_sg1_12_itm = 1'b0;
+    FRAME_slc_acc_imod_13_4_itm_1 = 1'b0;
+    FRAME_slc_acc_imod_13_4_itm = 1'b0;
+    FRAME_acc_30_itm_1 = 5'b0;
+    FRAME_acc_30_itm = 5'b0;
+    blue_slc_blue_2_sg1_itm_1 = 6'b0;
+    blue_slc_blue_2_sg1_itm = 6'b0;
+    FRAME_mul_5_itm_1 = 9'b0;
+    FRAME_mul_5_itm = 9'b0;
+    FRAME_mul_4_itm_1 = 11'b0;
+    FRAME_mul_4_itm = 11'b0;
+    green_slc_green_2_sg1_8_itm_1 = 1'b0;
+    green_slc_green_2_sg1_8_itm = 1'b0;
+    green_slc_green_2_sg1_13_itm_1 = 1'b0;
+    green_slc_green_2_sg1_13_itm = 1'b0;
+    green_slc_green_2_sg1_12_itm_1 = 1'b0;
+    green_slc_green_2_sg1_12_itm = 1'b0;
+    FRAME_slc_acc_imod_11_4_itm_1 = 1'b0;
+    FRAME_slc_acc_imod_11_4_itm = 1'b0;
+    FRAME_acc_18_itm_1 = 5'b0;
+    FRAME_acc_18_itm = 5'b0;
+    green_slc_green_2_sg1_itm_1 = 6'b0;
+    green_slc_green_2_sg1_itm = 6'b0;
+    FRAME_mul_3_itm_1 = 9'b0;
+    FRAME_mul_3_itm = 9'b0;
+    FRAME_mul_2_itm_1 = 11'b0;
+    FRAME_mul_2_itm = 11'b0;
+    exit_FRAME_for_1_sva_2_st = 1'b0;
+    FRAME_for_acc_5_tmp = 2'b0;
+    exit_FRAME_for_1_lpi_1_dfm_4 = 1'b0;
+    exit_FRAME_for_1_lpi_1_dfm_2 = 1'b0;
+    exit_FRAME_lpi_1_dfm_2 = 1'b0;
+    i_7_lpi_1_dfm = 2'b0;
+    exit_FRAME_for_sva_1 = 1'b0;
+    i_6_sva_1 = 2'b0;
+    b_2_sva_2 = 16'b0;
+    g_2_sva_2 = 16'b0;
+    r_2_sva_2 = 16'b0;
+    b_1_sg1_sva_1 = 15'b0;
+    g_1_sg1_sva_1 = 15'b0;
+    r_1_sg1_sva_1 = 15'b0;
+    b_0_sva_2 = 16'b0;
+    g_0_sva_2 = 16'b0;
+    r_0_sva_2 = 16'b0;
+    FRAME_p_1_sva_1 = 19'b0;
+    FRAME_acc_4_psp_sva = 12'b0;
+    acc_imod_13_sva = 6'b0;
+    FRAME_acc_3_psp_sva = 12'b0;
+    acc_imod_11_sva = 6'b0;
+    acc_imod_9_sva = 6'b0;
+    blue_2_sg1_sva = 15'b0;
+    green_2_sg1_sva = 15'b0;
+    red_2_sg1_sva = 15'b0;
+    exit_FRAME_for_1_sva_2 = 1'b0;
+    i_7_sva = 2'b0;
+    b_2_sva_1 = 16'b0;
+    g_2_sva_1 = 16'b0;
+    r_2_sva_1 = 16'b0;
+    b_0_sva_1 = 16'b0;
+    g_0_sva_1 = 16'b0;
+    r_0_sva_1 = 16'b0;
+    FRAME_for_1_slc_YMATRIX_rom_11_psp_sva = 1'b0;
+    exit_FRAME_for_lpi_1_dfm = 1'b0;
+    exit_FRAME_lpi_1_dfm = 1'b0;
+    b_1_sg1_lpi_1_dfm = 15'b0;
+    g_1_sg1_lpi_1_dfm = 15'b0;
+    r_1_sg1_lpi_1_dfm = 15'b0;
+    i_6_lpi_1_dfm = 2'b0;
+    b_2_lpi_1_dfm = 16'b0;
+    b_0_lpi_1_dfm = 16'b0;
+    g_2_lpi_1_dfm = 16'b0;
+    g_0_lpi_1_dfm = 16'b0;
+    r_2_lpi_1_dfm = 16'b0;
+    r_0_lpi_1_dfm = 16'b0;
+    regs_regs_2_lpi_1_dfm = 90'b0;
+    regs_regs_1_sva_dfm = 90'b0;
+    regs_regs_0_sva_dfm = 90'b0;
+    exit_FRAME_for_1_lpi_1_dfm = 1'b0;
+    FRAME_p_1_lpi_1_dfm = 19'b0;
+    exit_FRAME_1_sva = 1'b0;
+    regs_regs_0_sva = 90'b0;
+    regs_regs_1_sva = 90'b0;
+    i_7_lpi_1 = 2'b0;
+    exit_FRAME_for_lpi_1 = 1'b0;
+    i_6_lpi_1 = 2'b0;
+    r_2_lpi_1 = 16'b0;
+    r_0_lpi_1 = 16'b0;
+    r_1_sg1_lpi_1 = 15'b0;
+    g_2_lpi_1 = 16'b0;
+    g_0_lpi_1 = 16'b0;
+    g_1_sg1_lpi_1 = 15'b0;
+    b_2_lpi_1 = 16'b0;
+    b_0_lpi_1 = 16'b0;
+    b_1_sg1_lpi_1 = 15'b0;
+    FRAME_p_1_lpi_1 = 19'b0;
+    vout_rsc_mgc_out_stdreg_d <= 30'b0;
+  end
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [15:0] signext_16_1;
+    input [0:0] vector;
+  begin
+    signext_16_1= {{15{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [14:0] signext_15_1;
+    input [0:0] vector;
+  begin
+    signext_15_1= {{14{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_3_1_2;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 2;
+    readslicef_3_1_2 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [14:0] readslicef_16_15_1;
+    input [15:0] vector;
+    reg [15:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_16_15_1 = tmp[14:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] MUX_v_2_2_2;
+    input [3:0] inputs;
+    input [0:0] sel;
+    reg [1:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[3:2];
+      end
+      1'b1 : begin
+        result = inputs[1:0];
+      end
+      default : begin
+        result = inputs[3:2];
+      end
+    endcase
+    MUX_v_2_2_2 = result;
+  end
+  endfunction
+
+
+  function [14:0] MUX_v_15_2_2;
+    input [29:0] inputs;
+    input [0:0] sel;
+    reg [14:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[29:15];
+      end
+      1'b1 : begin
+        result = inputs[14:0];
+      end
+      default : begin
+        result = inputs[29:15];
+      end
+    endcase
+    MUX_v_15_2_2 = result;
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_22_11 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_s2u_1_2 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_2 = {vector[0], vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_11_15 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_15 = {{4{vector[10]}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v10/cycle_mgc_ioport.v b/Sobel/sobel.v10/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v10/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v10/cycle_mgc_ioport_v2001.v b/Sobel/sobel.v10/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v10/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v10/cycle_set.tcl b/Sobel/sobel.v10/cycle_set.tcl
new file mode 100644
index 0000000..5748cd6
--- /dev/null
+++ b/Sobel/sobel.v10/cycle_set.tcl
@@ -0,0 +1,157 @@
+
+# Loop constraints
+directive set /sobel/core/core:rlp CSTEPS_FROM {{. == 0}}
+directive set /sobel/core/core:rlp/main CSTEPS_FROM {{. == 3} {.. == 0}}
+
+# IO operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:io_read(vin:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:io_write(vout:rsc.d) CSTEPS_FROM {{.. == 2}}
+
+# Real operation constraints
+directive set /sobel/core/core:rlp/main/and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#9 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#27:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#1 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#28:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mul#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#2 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#29:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:and#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:or#1 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#33:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mul#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#34:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mul#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#12 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#35:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mul#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2-3:acc#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2-3:acc#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2-3:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#9 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#11 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc#9 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#13 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#12 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#15 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc#11 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#23 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#17 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#18 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#19 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#20 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#21 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#22 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#24 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#27 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#26 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#28 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc#13 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#35 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#29 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#30 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#31 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#32 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#33 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#34 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#4 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#41 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#42 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#36 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#37 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#38 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#39 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#40 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#2 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:or CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#18:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#1 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#19:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#2 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#20:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#17 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:or#2 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#21:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#26 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#22:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#27 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#23:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#28 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#19 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:or#4 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#24:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#25:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#12 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#26:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#13 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mux#9 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#42 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#46 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#20 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#21 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#22 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#23 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#24 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#33 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#34 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#35 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#39 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#40 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#41 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#44 CSTEPS_FROM {{.. == 1}}
diff --git a/Sobel/sobel.v10/directives.tcl b/Sobel/sobel.v10/directives.tcl
new file mode 100644
index 0000000..504c4bb
--- /dev/null
+++ b/Sobel/sobel.v10/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
+go extract
diff --git a/Sobel/sobel.v10/messages.txt b/Sobel/sobel.v10/messages.txt
new file mode 100644
index 0000000..beab98c
--- /dev/null
+++ b/Sobel/sobel.v10/messages.txt
@@ -0,0 +1,265 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.07 seconds, memory usage 351284kB, peak memory usage 448912kB (SOL-9)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.cpp(168): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+
+# Messages from "go compile"
+
+Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'sobel' specified by directive (CIN-52)
+Synthesizing routine 'sobel' (CIN-13)
+Inlining routine 'sobel' (CIN-14)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Optimizing block '/sobel' ... (CIN-4)
+Inout port 'vin' is only used as an input. (OPT-10)
+Inout port 'vout' is only used as an output. (OPT-11)
+Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME:for#1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+Design 'sobel' was read (SOL-1)
+Optimizing partition '/sobel': (Total ops = 910, Real ops = 188, Vars = 204) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 910, Real ops = 188, Vars = 202) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 870, Real ops = 180, Vars = 208) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 870, Real ops = 180, Vars = 210) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 870, Real ops = 180, Vars = 210) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 870, Real ops = 180, Vars = 208) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 405, Real ops = 110, Vars = 97) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 380, Real ops = 110, Vars = 96) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 380, Real ops = 110, Vars = 96) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 380, Real ops = 110, Vars = 98) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 380, Real ops = 110, Vars = 98) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 360, Real ops = 108, Vars = 146) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 32) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 392, Real ops = 104, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 303, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 303, Real ops = 94, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 298, Real ops = 94, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+Completed transformation 'compile' on solution 'sobel.v10': elapsed time 5.01 seconds, memory usage 326452kB, peak memory usage 448912kB (SOL-9)
+Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'sobel.v10' (SOL-8)
+Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+Loop '/sobel/core/FRAME:for#1' is left rolled. (LOOP-4)
+Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+Loop '/sobel/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/sobel/core': (Total ops = 346, Real ops = 111, Vars = 23) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 21) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 20) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 20) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 283, Real ops = 90, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 23) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 283, Real ops = 90, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 34) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 237, Real ops = 105, Vars = 28) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 237, Real ops = 105, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 237, Real ops = 105, Vars = 28) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 237, Real ops = 105, Vars = 33) (SOL-10)
+Design 'sobel' contains '216' real operations. (SOL-11)
+Optimizing partition '/sobel/core': (Total ops = 247, Real ops = 106, Vars = 32) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 640, Real ops = 174, Vars = 263) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 331, Real ops = 155, Vars = 76) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 330, Real ops = 155, Vars = 75) (SOL-10)
+Completed transformation 'architect' on solution 'sobel.v10': elapsed time 12.37 seconds, memory usage 326652kB, peak memory usage 448912kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'sobel.v10' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 1843201, Area (Datapath, Register, Total) = 6576.18, 0.00, 6576.18 (CRAAS-11)
+Optimized LOOP 'main': Latency = 1843201, Area (Datapath, Register, Total) = 6570.04, 0.00, 6570.04 (CRAAS-10)
+Optimized LOOP 'main': Latency = 1843201, Area (Datapath, Register, Total) = 6519.24, 0.00, 6519.24 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 1843201, Area (Datapath, Register, Total) = 6519.24, 0.00, 6519.24 (CRAAS-12)
+Completed transformation 'allocate' on solution 'sobel.v10': elapsed time 1.64 seconds, memory usage 326776kB, peak memory usage 448912kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'sobel.v10' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 484, Real ops = 217, Vars = 158) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 474, Real ops = 216, Vars = 150) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 463, Real ops = 216, Vars = 149) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 441, Real ops = 208, Vars = 119) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 434, Real ops = 205, Vars = 120) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 448, Real ops = 205, Vars = 132) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 439, Real ops = 205, Vars = 125) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 443, Real ops = 204, Vars = 135) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 439, Real ops = 204, Vars = 125) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 453, Real ops = 204, Vars = 137) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 444, Real ops = 204, Vars = 130) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 439, Real ops = 204, Vars = 125) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 453, Real ops = 204, Vars = 137) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 444, Real ops = 204, Vars = 130) (SOL-10)
+Completed transformation 'schedule' on solution 'sobel.v10': elapsed time 2.39 seconds, memory usage 327016kB, peak memory usage 448912kB (SOL-9)
+Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'sobel.v10' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 805, Real ops = 328, Vars = 743) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 796, Real ops = 328, Vars = 736) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 647, Real ops = 236, Vars = 109) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 638, Real ops = 236, Vars = 102) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 390, Real ops = 215, Vars = 108) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 381, Real ops = 215, Vars = 101) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+Completed transformation 'dpfsm' on solution 'sobel.v10': elapsed time 0.81 seconds, memory usage 327628kB, peak memory usage 448912kB (SOL-9)
+
+# Messages from "go extract"
+
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'sobel.v10' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 481, Real ops = 250, Vars = 478) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 472, Real ops = 250, Vars = 471) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 109) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 102) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 461, Real ops = 247, Vars = 458) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 452, Real ops = 247, Vars = 451) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 461, Real ops = 247, Vars = 458) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 452, Real ops = 247, Vars = 451) (SOL-10)
+Reassigned operation FRAME:for#1:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/sobel': (Total ops = 461, Real ops = 247, Vars = 458) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 452, Real ops = 247, Vars = 451) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 356, Real ops = 209, Vars = 109) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 347, Real ops = 209, Vars = 102) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 356, Real ops = 209, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 347, Real ops = 209, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 356, Real ops = 209, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 347, Real ops = 209, Vars = 99) (SOL-10)
+Completed transformation 'extract' on solution 'sobel.v10': elapsed time 9.19 seconds, memory usage 327636kB, peak memory usage 448912kB (SOL-9)
diff --git a/Sobel/sobel.v10/reg_sharing.tcl b/Sobel/sobel.v10/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v10/reg_sharing.tcl
diff --git a/Sobel/sobel.v10/res_sharing.tcl b/Sobel/sobel.v10/res_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v10/res_sharing.tcl
diff --git a/Sobel/sobel.v10/rtl.rpt b/Sobel/sobel.v10/rtl.rpt
new file mode 100644
index 0000000..9f9b890
--- /dev/null
+++ b/Sobel/sobel.v10/rtl.rpt
@@ -0,0 +1,825 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 15:50:38 +0000 2016                      
+
+Solution Settings: sobel.v10
+  Current state: extract
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       220 1843201    1843200            0  1          
+    Design Total:                     220 1843201    1843200            0  0          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(10,0,10,0,10)                       11.241                       0.000     11.241 1.301          1           1 
+    mgc_add(10,0,9,1,10)                        11.000                       0.000     11.000 1.303          1           0 
+    mgc_add(11,0,10,1,12)                       12.000                       0.000     12.000 1.208          2           2 
+    mgc_add(12,0,11,0,12)                       13.228                       0.000     13.228 1.436          2           2 
+    mgc_add(15,0,11,1,15)                       16.000                       0.000     16.000 1.633          3           3 
+    mgc_add(15,0,15,0,15)                       16.198                       0.000     16.198 1.627          0           3 
+    mgc_add(16,0,12,1,16)                       17.000                       0.000     17.000 1.696         12          12 
+    mgc_add(16,0,16,0,16)                       17.189                       0.000     17.189 1.690          6           3 
+    mgc_add(19,0,2,1,19)                        20.000                       0.000     20.000 1.908          1           1 
+    mgc_add(2,0,1,0,2)                           3.315                       0.000      3.315 0.658          0           2 
+    mgc_add(2,0,1,1,2)                           3.000                       0.000      3.000 0.658          1           2 
+    mgc_add(2,0,2,0,2)                           3.311                       0.000      3.311 0.653          2           2 
+    mgc_add(3,0,3,0,3)                           4.302                       0.000      4.302 0.761          2           0 
+    mgc_add(3,0,3,0,4)                           4.302                       0.000      4.302 0.761         12          12 
+    mgc_add(4,0,4,0,5)                           5.293                       0.000      5.293 0.854          6           6 
+    mgc_add(5,0,4,0,6)                           6.288                       0.000      6.288 0.940          3           3 
+    mgc_add(5,0,5,0,5)                           6.285                       0.000      6.285 0.938          6           6 
+    mgc_add(5,0,5,0,6)                           6.285                       0.000      6.285 0.938          0           1 
+    mgc_add(6,0,5,1,8)                           7.000                       0.000      7.000 0.693          3           3 
+    mgc_add(6,0,6,0,6)                           7.276                       0.000      7.276 1.016          3           3 
+    mgc_add(8,0,7,0,8)                           9.262                       0.000      9.262 1.165          1           1 
+    mgc_add(9,0,8,1,10)                         10.000                       0.000     10.000 1.072          3           3 
+    mgc_and(1,2)                                 0.730                       0.000      0.730 0.263          0           6 
+    mgc_and(1,3)                                 1.054                       0.000      1.054 0.416          0           1 
+    mgc_and(15,2)                               10.947                       0.000     10.947 0.263          3           3 
+    mgc_and(16,2)                               11.677                       0.000     11.677 0.263          6           6 
+    mgc_and(19,2)                               13.867                       0.000     13.867 0.263          1           1 
+    mgc_and(2,2)                                 1.460                       0.000      1.460 0.263          6           2 
+    mgc_mul(2,0,9,0,11)                        330.250                       2.000     10.250 3.044          3           3 
+    mgc_mul(2,1,10,1,12)                       330.000                       2.000     10.000 3.087          9          15 
+    mgc_mul(3,0,6,0,9)                         330.250                       2.000     10.250 2.846          3           3 
+    mgc_mux(1,1,2)                               0.919                       0.000      0.919 0.369          4           3 
+    mgc_mux(10,2,4)                             22.259                       0.000     22.259 0.936         15          15 
+    mgc_mux(15,1,2)                             13.791                       0.000     13.791 0.369          3           3 
+    mgc_mux(16,1,2)                             14.711                       0.000     14.711 0.369          6           6 
+    mgc_mux(19,1,2)                             17.469                       0.000     17.469 0.369          1           1 
+    mgc_mux(2,1,2)                               1.839                       0.000      1.839 0.369          2           2 
+    mgc_mux(30,1,2)                             27.583                       0.000     27.583 0.369          0           1 
+    mgc_mux(90,1,2)                             82.748                       0.000     82.748 0.369          3           3 
+    mgc_nand(1,2)                                0.730                       0.000      0.730 0.268          0           4 
+    mgc_nand(1,3)                                1.054                       0.000      1.054 0.425          0           1 
+    mgc_nor(1,2)                                 0.730                       0.000      0.730 0.263          0           4 
+    mgc_not(1)                                   0.000                       0.000      0.000 0.000          0          28 
+    mgc_not(3)                                   0.000                       0.000      0.000 0.000          0          12 
+    mgc_or(1,2)                                  0.730                       0.000      0.730 0.268          0           6 
+    mgc_or(1,3)                                  1.054                       0.000      1.054 0.425          0           3 
+    mgc_or(10,2)                                 7.298                       0.000      7.298 0.268          1           1 
+    mgc_or(2,2)                                  1.460                       0.000      1.460 0.268          4           0 
+    mgc_or(6,2)                                  4.379                       0.000      4.379 0.268          1           1 
+    mgc_reg_pos(1,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0          12 
+    mgc_reg_pos(11,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(15,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(16,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           6 
+    mgc_reg_pos(19,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(2,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_reg_pos(30,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(5,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(6,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_reg_pos(9,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(90,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           3 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,90)                            0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(2,30)                         0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):            8527.433                      42.000   1807.000                              
+    
+  Area Scores
+                      Post-Scheduling   Post-DP & FSM Post-Assignment 
+    ----------------- --------------- --------------- ---------------
+    Total Area Score:   6519.2          8702.1          8527.4        
+    Total Reg:             0.0             0.0             0.0        
+                                                                      
+    DataPath:           6519.2 (100%)   8702.1 (100%)   8527.4 (100%) 
+      MUX:               736.6  (11%)    935.3  (11%)    763.3   (9%) 
+      FUNC:             5639.6  (87%)   7614.9  (88%)   7612.9  (89%) 
+      LOGIC:             143.0   (2%)    152.0   (2%)    151.2   (2%) 
+      BUFFER:              0.0             0.0             0.0        
+      MEM:                 0.0             0.0             0.0        
+      ROM:                 0.0             0.0             0.0        
+      REG:                 0.0             0.0             0.0        
+                                                                      
+    
+    FSM:                   0.0             0.0             0.0        
+      FSM-REG:             0.0             0.0             0.0        
+      FSM-COMB:            0.0             0.0             0.0        
+                                                                      
+    
+  Register-to-Variable Mappings
+    Register                        Size(bits) Gated Register CG Opt Done Variables                                             
+    ------------------------------- ---------- -------------- ----------- -----------------------------------------------------
+    regs.regs(0).sva                        90         Y                  regs.regs(0).sva                                      
+    regs.regs(1).sva                        90         Y                  regs.regs(1).sva                                      
+    regs.regs(2).lpi#1.dfm                  90         Y                  regs.regs(2).lpi#1.dfm                                
+    vout:rsc:mgc_out_stdreg.d               30         Y                  vout:rsc:mgc_out_stdreg.d                             
+    FRAME:p#1.lpi#1                         19         Y                  FRAME:p#1.lpi#1                                       
+    b(0).lpi#1                              16         Y                  b(0).lpi#1                                            
+    b(2).lpi#1                              16         Y                  b(2).lpi#1                                            
+    g(0).lpi#1                              16         Y                  g(0).lpi#1                                            
+    g(2).lpi#1                              16         Y                  g(2).lpi#1                                            
+    r(0).lpi#1                              16         Y                  r(0).lpi#1                                            
+    r(2).lpi#1                              16         Y                  r(2).lpi#1                                            
+    b(1).sg1.lpi#1                          15         Y                  b(1).sg1.lpi#1                                        
+    g(1).sg1.lpi#1                          15         Y                  g(1).sg1.lpi#1                                        
+    r(1).sg1.lpi#1                          15         Y                  r(1).sg1.lpi#1                                        
+    FRAME:mul#2.itm#1                       11         Y                  FRAME:mul#2.itm#1                                     
+    FRAME:mul#4.itm#1                       11         Y                  FRAME:mul#4.itm#1                                     
+    FRAME:mul#1.itm#1                        9         Y                  FRAME:mul#1.itm#1                                     
+    FRAME:mul#3.itm#1                        9         Y                  FRAME:mul#3.itm#1                                     
+    FRAME:mul#5.itm#1                        9         Y                  FRAME:mul#5.itm#1                                     
+    FRAME:acc#41.itm#3                       6         Y                  FRAME:acc#41.itm#3                                    
+    blue:slc(blue#2.sg1).itm#1               6         Y                  blue:slc(blue#2.sg1).itm#1                            
+    green:slc(green#2.sg1).itm#1             6         Y                  green:slc(green#2.sg1).itm#1                          
+    red:slc(red#2.sg1).itm#1                 6         Y                  red:slc(red#2.sg1).itm#1                              
+    FRAME:acc#18.itm#1                       5         Y                  FRAME:acc#18.itm#1                                    
+    FRAME:acc#30.itm#1                       5         Y                  FRAME:acc#30.itm#1                                    
+    FRAME:acc#37.itm#1                       5         Y                  FRAME:acc#37.itm#1                                    
+    FRAME:acc#41.itm#1.sg1                   2         Y                  FRAME:acc#41.itm#1.sg1                                
+    FRAME:acc#41.itm#1.sg2                   2         Y                  FRAME:acc#41.itm#1.sg2                                
+    i#6.lpi#1                                2         Y                  i#6.lpi#1                                             
+    i#7.lpi#1                                2         Y                  i#7.lpi#1                                             
+    FRAME:slc(acc.imod#11)#4.itm#1           1         Y                  FRAME:slc(acc.imod#11)#4.itm#1                        
+    FRAME:slc(acc.imod#13)#4.itm#1           1         Y                  FRAME:slc(acc.imod#13)#4.itm#1                        
+    FRAME:slc(acc.imod#9)#4.itm#1            1         Y                  FRAME:slc(acc.imod#9)#4.itm#1                         
+    blue:slc(blue#2.sg1)#12.itm#1            1         Y                  blue:slc(blue#2.sg1)#12.itm#1                         
+    exit:FRAME#1.sva                         1         Y                  exit:FRAME#1.sva                                      
+    exit:FRAME.lpi#1.dfm#2                   1         Y                  exit:FRAME.lpi#1.dfm#2                                
+    exit:FRAME:for#1.lpi#1.dfm#4             1         Y                  exit:FRAME:for#1.lpi#1.dfm#4                          
+    exit:FRAME:for#1.sva#2.st#1              1         Y                  exit:FRAME:for#1.sva#2.st#1                           
+    exit:FRAME:for.lpi#1                     1         Y                  exit:FRAME:for.lpi#1                                  
+    exit:FRAME:for.lpi#1.dfm.st#1            1         Y                  exit:FRAME:for.lpi#1.dfm.st#1                         
+    green:slc(green#2.sg1)#12.itm#1          1         Y                  green:slc(green#2.sg1)#12.itm#1                       
+    main.stage_0#2                           1         Y                  main.stage_0#2                                        
+                                                                                                                                
+    Total:                                 568            568           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  15.158629
+      Slack:      4.8413710000000005
+      
+      Path                                           Startpoint                             Endpoint                           Delay   Slack   
+      ---------------------------------------------- -------------------------------------- ---------------------------------- ------- -------
+      1                                              sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#37.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(2).lpi#1.dfm)       mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(2).lpi#1.dfm                                                                                      0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)#2                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#33:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#33:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#6                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#6.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#10                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/r(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(r(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(r(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc                          mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc.itm                                                                                                0.0000  7.3461  
+        sobel:core/ACC2:conc                                                                                                   0.0000  7.3461  
+        sobel:core/ACC2:conc.itm                                                                                               0.0000  7.3461  
+        sobel:core/ACC2-3:acc#1                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#1.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc                                                                                                    0.0000  9.0359  
+        sobel:core/red#2.sg1.sva                                                                                               0.0000  9.0359  
+        sobel:core/slc(red#2.sg1.sva)                                                                                          0.0000  9.0359  
+        sobel:core/slc(red#2.sg1.sva).itm                                                                                      0.0000  9.0359  
+        sobel:core/FRAME:acc#8                       mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#8.itm                                                                                             0.0000  9.7968  
+        sobel:core/FRAME:acc#10                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#10.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#11                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#11.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#9                             mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#9.sva                                                                                              0.0000  12.6066 
+        sobel:core/slc(acc.imod#9.sva)#1                                                                                       0.0000  12.6066 
+        sobel:core/slc(acc.imod#9.sva)#1.itm                                                                                   0.0000  12.6066 
+        sobel:core/conc#142                                                                                                    0.0000  12.6066 
+        sobel:core/conc#142.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#42                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#42.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#7                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#7.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#39                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#39.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#141                                                                                                    0.0000  13.5442 
+        sobel:core/conc#141.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#36                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#36.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#37                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#37.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#37.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      2                                              sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(2).lpi#1.dfm)       mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(2).lpi#1.dfm                                                                                      0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)#1                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#34:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#34:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#7                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#7.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#12                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/g(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#7                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#7.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#1                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#1.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#2                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#2.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#1                                                                                                  0.0000  9.0359  
+        sobel:core/green#2.sg1.sva                                                                                             0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#1                                                                                      0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#1.itm                                                                                  0.0000  9.0359  
+        sobel:core/FRAME:acc#13                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#13.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#15                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#15.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#16                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#16.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#11                            mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#11.sva                                                                                             0.0000  12.6066 
+        sobel:core/slc(acc.imod#11.sva)#1                                                                                      0.0000  12.6066 
+        sobel:core/slc(acc.imod#11.sva)#1.itm                                                                                  0.0000  12.6066 
+        sobel:core/conc#146                                                                                                    0.0000  12.6066 
+        sobel:core/conc#146.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#23                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#23.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#5                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#5.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#43                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#43.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#145                                                                                                    0.0000  13.5442 
+        sobel:core/conc#145.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#17                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#17.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#18                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#18.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#18.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      3                                              sobel:core/reg(regs.regs(1).sva)       sobel:core/reg(FRAME:acc#37.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(1).sva)             mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(1).sva                                                                                            0.0000  0.0000  
+        sobel:core/slc(regs.regs(1).sva)#2                                                                                     0.0000  0.0000  
+        sobel:core/slc(regs.regs(1).sva)#2.itm                                                                                 0.0000  0.0000  
+        sobel:core/regs.operator[]#33:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#33:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#6                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#6.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#10                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/r(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(r(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(r(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc                          mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc.itm                                                                                                0.0000  7.3461  
+        sobel:core/ACC2:conc                                                                                                   0.0000  7.3461  
+        sobel:core/ACC2:conc.itm                                                                                               0.0000  7.3461  
+        sobel:core/ACC2-3:acc#1                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#1.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc                                                                                                    0.0000  9.0359  
+        sobel:core/red#2.sg1.sva                                                                                               0.0000  9.0359  
+        sobel:core/slc(red#2.sg1.sva)                                                                                          0.0000  9.0359  
+        sobel:core/slc(red#2.sg1.sva).itm                                                                                      0.0000  9.0359  
+        sobel:core/FRAME:acc#8                       mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#8.itm                                                                                             0.0000  9.7968  
+        sobel:core/FRAME:acc#10                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#10.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#11                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#11.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#9                             mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#9.sva                                                                                              0.0000  12.6066 
+        sobel:core/slc(acc.imod#9.sva)#1                                                                                       0.0000  12.6066 
+        sobel:core/slc(acc.imod#9.sva)#1.itm                                                                                   0.0000  12.6066 
+        sobel:core/conc#142                                                                                                    0.0000  12.6066 
+        sobel:core/conc#142.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#42                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#42.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#7                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#7.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#39                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#39.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#141                                                                                                    0.0000  13.5442 
+        sobel:core/conc#141.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#36                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#36.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#37                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#37.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#37.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      4                                              sobel:core/reg(regs.regs(0).sva)       sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(0).sva)             mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(0).sva                                                                                            0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva)#1                                                                                     0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva)#1.itm                                                                                 0.0000  0.0000  
+        sobel:core/regs.operator[]#34:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#34:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#7                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#7.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#12                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/g(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#7                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#7.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#1                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#1.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#2                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#2.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#1                                                                                                  0.0000  9.0359  
+        sobel:core/green#2.sg1.sva                                                                                             0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#1                                                                                      0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#1.itm                                                                                  0.0000  9.0359  
+        sobel:core/FRAME:acc#13                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#13.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#15                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#15.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#16                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#16.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#11                            mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#11.sva                                                                                             0.0000  12.6066 
+        sobel:core/slc(acc.imod#11.sva)#1                                                                                      0.0000  12.6066 
+        sobel:core/slc(acc.imod#11.sva)#1.itm                                                                                  0.0000  12.6066 
+        sobel:core/conc#146                                                                                                    0.0000  12.6066 
+        sobel:core/conc#146.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#23                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#23.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#5                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#5.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#43                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#43.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#145                                                                                                    0.0000  13.5442 
+        sobel:core/conc#145.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#17                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#17.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#18                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#18.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#18.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      5                                              sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(2).lpi#1.dfm)       mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(2).lpi#1.dfm                                                                                      0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)#1                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#34:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#34:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#7                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#7.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#12                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/g(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#7                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#7.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#1                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#1.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#2                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#2.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#1                                                                                                  0.0000  9.0359  
+        sobel:core/green#2.sg1.sva                                                                                             0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#12                                                                                     0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#12.itm                                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#37                      mgc_not_1                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#37.itm                                                                                            0.0000  9.0359  
+        sobel:core/conc#155                                                                                                    0.0000  9.0359  
+        sobel:core/conc#155.itm                                                                                                0.0000  9.0359  
+        sobel:core/FRAME:acc#12                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#12.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#15                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#15.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#16                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#16.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#11                            mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#11.sva                                                                                             0.0000  12.6066 
+        sobel:core/slc(acc.imod#11.sva)#1                                                                                      0.0000  12.6066 
+        sobel:core/slc(acc.imod#11.sva)#1.itm                                                                                  0.0000  12.6066 
+        sobel:core/conc#146                                                                                                    0.0000  12.6066 
+        sobel:core/conc#146.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#23                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#23.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#5                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#5.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#43                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#43.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#145                                                                                                    0.0000  13.5442 
+        sobel:core/conc#145.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#17                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#17.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#18                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#18.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#18.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      6                                              sobel:core/reg(regs.regs(0).sva)       sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(0).sva)             mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(0).sva                                                                                            0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva)#1                                                                                     0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva)#1.itm                                                                                 0.0000  0.0000  
+        sobel:core/regs.operator[]#34:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#34:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#7                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#7.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#12                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/g(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#7                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#7.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#1                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#1.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#2                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#2.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#1                                                                                                  0.0000  9.0359  
+        sobel:core/green#2.sg1.sva                                                                                             0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#12                                                                                     0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#12.itm                                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#37                      mgc_not_1                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#37.itm                                                                                            0.0000  9.0359  
+        sobel:core/conc#155                                                                                                    0.0000  9.0359  
+        sobel:core/conc#155.itm                                                                                                0.0000  9.0359  
+        sobel:core/FRAME:acc#12                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#12.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#15                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#15.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#16                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#16.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#11                            mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#11.sva                                                                                             0.0000  12.6066 
+        sobel:core/slc(acc.imod#11.sva)#1                                                                                      0.0000  12.6066 
+        sobel:core/slc(acc.imod#11.sva)#1.itm                                                                                  0.0000  12.6066 
+        sobel:core/conc#146                                                                                                    0.0000  12.6066 
+        sobel:core/conc#146.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#23                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#23.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#5                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#5.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#43                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#43.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#145                                                                                                    0.0000  13.5442 
+        sobel:core/conc#145.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#17                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#17.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#18                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#18.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#18.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      7                                              sobel:core/reg(regs.regs(1).sva)       sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(1).sva)             mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(1).sva                                                                                            0.0000  0.0000  
+        sobel:core/slc(regs.regs(1).sva)#1                                                                                     0.0000  0.0000  
+        sobel:core/slc(regs.regs(1).sva)#1.itm                                                                                 0.0000  0.0000  
+        sobel:core/regs.operator[]#34:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#34:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#7                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#7.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#12                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/g(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#7                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#7.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#1                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#1.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#2                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#2.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#1                                                                                                  0.0000  9.0359  
+        sobel:core/green#2.sg1.sva                                                                                             0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#12                                                                                     0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#12.itm                                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#37                      mgc_not_1                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#37.itm                                                                                            0.0000  9.0359  
+        sobel:core/conc#155                                                                                                    0.0000  9.0359  
+        sobel:core/conc#155.itm                                                                                                0.0000  9.0359  
+        sobel:core/FRAME:acc#12                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#12.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#15                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#15.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#16                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#16.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#11                            mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#11.sva                                                                                             0.0000  12.6066 
+        sobel:core/slc(acc.imod#11.sva)#1                                                                                      0.0000  12.6066 
+        sobel:core/slc(acc.imod#11.sva)#1.itm                                                                                  0.0000  12.6066 
+        sobel:core/conc#146                                                                                                    0.0000  12.6066 
+        sobel:core/conc#146.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#23                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#23.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#5                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#5.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#43                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#43.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#145                                                                                                    0.0000  13.5442 
+        sobel:core/conc#145.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#17                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#17.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#18                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#18.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#18.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      8                                              sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#30.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(2).lpi#1.dfm)       mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(2).lpi#1.dfm                                                                                      0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm).itm                                                                             0.0000  0.0000  
+        sobel:core/regs.operator[]#35:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#35:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#8                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#8.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#14                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/b(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(b(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(b(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#8                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#8.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#2                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#2.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#3                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#3.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#2                                                                                                  0.0000  9.0359  
+        sobel:core/blue#2.sg1.sva                                                                                              0.0000  9.0359  
+        sobel:core/slc(blue#2.sg1.sva)#1                                                                                       0.0000  9.0359  
+        sobel:core/slc(blue#2.sg1.sva)#1.itm                                                                                   0.0000  9.0359  
+        sobel:core/FRAME:acc#25                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#25.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#27                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#27.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#28                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#28.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#13                            mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#13.sva                                                                                             0.0000  12.6066 
+        sobel:core/slc(acc.imod#13.sva)#1                                                                                      0.0000  12.6066 
+        sobel:core/slc(acc.imod#13.sva)#1.itm                                                                                  0.0000  12.6066 
+        sobel:core/conc#144                                                                                                    0.0000  12.6066 
+        sobel:core/conc#144.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#35                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#35.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#6                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#6.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#41                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#41.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#143                                                                                                    0.0000  13.5442 
+        sobel:core/conc#143.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#29                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#29.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#30                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#30.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#30.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      9                                              sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#30.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(2).lpi#1.dfm)       mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(2).lpi#1.dfm                                                                                      0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm).itm                                                                             0.0000  0.0000  
+        sobel:core/regs.operator[]#35:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#35:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#8                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#8.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#14                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/b(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(b(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(b(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#8                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#8.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#2                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#2.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#3                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#3.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#2                                                                                                  0.0000  9.0359  
+        sobel:core/blue#2.sg1.sva                                                                                              0.0000  9.0359  
+        sobel:core/slc(blue#2.sg1.sva)#1                                                                                       0.0000  9.0359  
+        sobel:core/slc(blue#2.sg1.sva)#1.itm                                                                                   0.0000  9.0359  
+        sobel:core/FRAME:acc#25                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#25.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#27                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#27.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#28                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#28.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#13                            mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#13.sva                                                                                             0.0000  12.6066 
+        sobel:core/slc(acc.imod#13.sva)#2                                                                                      0.0000  12.6066 
+        sobel:core/slc(acc.imod#13.sva)#2.itm                                                                                  0.0000  12.6066 
+        sobel:core/FRAME:not#21                      mgc_not_3                                                                 0.0000  12.6066 
+        sobel:core/FRAME:not#21.itm                                                                                            0.0000  12.6066 
+        sobel:core/FRAME:conc#29                                                                                               0.0000  12.6066 
+        sobel:core/FRAME:conc#29.itm                                                                                           0.0000  12.6066 
+        sobel:core/FRAME:acc#35                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#35.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#6                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#6.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#41                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#41.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#143                                                                                                    0.0000  13.5442 
+        sobel:core/conc#143.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#29                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#29.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#30                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#30.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#30.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      10                                             sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#30.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(2).lpi#1.dfm)       mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(2).lpi#1.dfm                                                                                      0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm).itm                                                                             0.0000  0.0000  
+        sobel:core/regs.operator[]#35:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#35:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#8                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#8.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#14                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/b(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(b(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(b(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#8                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#8.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#2                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#2.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#3                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#3.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#2                                                                                                  0.0000  9.0359  
+        sobel:core/blue#2.sg1.sva                                                                                              0.0000  9.0359  
+        sobel:core/slc(blue#2.sg1.sva)#3                                                                                       0.0000  9.0359  
+        sobel:core/slc(blue#2.sg1.sva)#3.itm                                                                                   0.0000  9.0359  
+        sobel:core/FRAME:not#18                      mgc_not_3                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#18.itm                                                                                            0.0000  9.0359  
+        sobel:core/FRAME:acc#25                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#25.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#27                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#27.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#28                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#28.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#13                            mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#13.sva                                                                                             0.0000  12.6066 
+        sobel:core/slc(acc.imod#13.sva)#2                                                                                      0.0000  12.6066 
+        sobel:core/slc(acc.imod#13.sva)#2.itm                                                                                  0.0000  12.6066 
+        sobel:core/FRAME:not#21                      mgc_not_3                                                                 0.0000  12.6066 
+        sobel:core/FRAME:not#21.itm                                                                                            0.0000  12.6066 
+        sobel:core/FRAME:conc#29                                                                                               0.0000  12.6066 
+        sobel:core/FRAME:conc#29.itm                                                                                           0.0000  12.6066 
+        sobel:core/FRAME:acc#35                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#35.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#6                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#6.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#41                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#41.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#143                                                                                                    0.0000  13.5442 
+        sobel:core/conc#143.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#29                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#29.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#30                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#30.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#30.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                        Port                               Slack (Delay) Messages 
+      ----------------------------------------------- -------------------------------- ------- ------- --------
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)       mux.itm                          14.0161  5.9839          
+      sobel:core/reg(FRAME:acc#41.itm#1.sg2)          FRAME:acc#43.itm                  7.2622 12.7378          
+      sobel:core/reg(FRAME:acc#41.itm#1.sg1)          slc(FRAME:mul.sdt)#2.itm          7.9199 12.0801          
+      sobel:core/reg(FRAME:acc#41.itm#3)              FRAME:acc#44.itm                  6.9824 13.0176          
+      sobel:core/reg(FRAME:mul#1.itm#1)               FRAME:mul#1.itm                   8.1180 11.8820          
+      sobel:core/reg(red:slc(red#2.sg1).itm#1)        slc(red#2.sg1.sva)#1.itm         10.9641  9.0359          
+      sobel:core/reg(FRAME:acc#37.itm#1)              FRAME:acc#37.itm                  4.8414 15.1586          
+      sobel:core/reg(FRAME:slc(acc.imod#9)#4.itm#1)   slc(acc.imod#9.sva).itm           7.3934 12.6066          
+      sobel:core/reg(FRAME:mul#4.itm#1)               FRAME:mul#4.itm                   7.9199 12.0801          
+      sobel:core/reg(FRAME:mul#5.itm#1)               FRAME:mul#5.itm                   8.1180 11.8820          
+      sobel:core/reg(blue:slc(blue#2.sg1).itm#1)      slc(blue#2.sg1.sva)#2.itm        10.9641  9.0359          
+      sobel:core/reg(FRAME:acc#30.itm#1)              FRAME:acc#30.itm                  4.8414 15.1586          
+      sobel:core/reg(FRAME:slc(acc.imod#13)#4.itm#1)  slc(acc.imod#13.sva).itm          7.3934 12.6066          
+      sobel:core/reg(blue:slc(blue#2.sg1)#12.itm#1)   slc(blue#2.sg1.sva).itm          10.9641  9.0359          
+      sobel:core/reg(FRAME:mul#2.itm#1)               FRAME:mul#2.itm                   7.9199 12.0801          
+      sobel:core/reg(FRAME:mul#3.itm#1)               FRAME:mul#3.itm                   8.1180 11.8820          
+      sobel:core/reg(green:slc(green#2.sg1).itm#1)    slc(green#2.sg1.sva)#2.itm       10.9641  9.0359          
+      sobel:core/reg(FRAME:acc#18.itm#1)              FRAME:acc#18.itm                  4.8414 15.1586          
+      sobel:core/reg(FRAME:slc(acc.imod#11)#4.itm#1)  slc(acc.imod#11.sva).itm          7.3934 12.6066          
+      sobel:core/reg(green:slc(green#2.sg1)#12.itm#1) slc(green#2.sg1.sva).itm         10.9641  9.0359          
+      sobel:core/reg(exit:FRAME:for#1.sva#2.st#1)     FRAME:for#1:not#7.itm            18.6898  1.3102          
+      sobel:core/reg(exit:FRAME:for.lpi#1.dfm.st#1)   exit:FRAME:for.lpi#1.dfm         18.3131  1.6869          
+      sobel:core/reg(i#7.lpi#1)                       mux#1.itm                        17.5333  2.4667          
+      sobel:core/reg(exit:FRAME:for.lpi#1)            mux#2.itm                        17.7958  2.2042          
+      sobel:core/reg(exit:FRAME:for#1.lpi#1.dfm#4)    exit:FRAME:for#1.lpi#1.dfm#4:mx0 15.7649  4.2351          
+      sobel:core/reg(exit:FRAME#1.sva)                FRAME:and.itm                    15.7649  4.2351          
+      sobel:core/reg(main.stage_0#2)                  Cn1_1#4                          20.0000  0.0000          
+      sobel:core/reg(regs.regs(2).lpi#1.dfm)          regs.regs(2).lpi#1.dfm:mx0       13.2803  6.7197          
+      sobel:core/reg(regs.regs(1).sva)                regs.regs(1).sva.dfm:mx0         13.2803  6.7197          
+      sobel:core/reg(regs.regs(0).sva)                regs.regs(0).sva.dfm:mx0         13.2803  6.7197          
+      sobel:core/reg(exit:FRAME.lpi#1.dfm#2)          exit:FRAME.lpi#1.dfm#2:mx0       16.0328  3.9672          
+      sobel:core/reg(b(1).sg1.lpi#1)                  mux#8.itm                        13.0411  6.9589          
+      sobel:core/reg(g(1).sg1.lpi#1)                  mux#9.itm                        13.0411  6.9589          
+      sobel:core/reg(r(1).sg1.lpi#1)                  mux#10.itm                       13.0411  6.9589          
+      sobel:core/reg(i#6.lpi#1)                       mux#11.itm                       18.4535  1.5465          
+      sobel:core/reg(b(2).lpi#1)                      mux#12.itm                       13.2803  6.7197          
+      sobel:core/reg(b(0).lpi#1)                      mux#13.itm                       13.2803  6.7197          
+      sobel:core/reg(g(2).lpi#1)                      mux#14.itm                       13.2803  6.7197          
+      sobel:core/reg(g(0).lpi#1)                      mux#15.itm                       13.2803  6.7197          
+      sobel:core/reg(r(2).lpi#1)                      mux#16.itm                       13.2803  6.7197          
+      sobel:core/reg(r(0).lpi#1)                      mux#17.itm                       13.2803  6.7197          
+      sobel:core/reg(FRAME:p#1.lpi#1)                 mux#18.itm                       17.4604  2.5396          
+      sobel                                           vout:rsc.z                       20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                   19     1 
+    -                   16    15 
+    -                   15     6 
+    -                   12     4 
+    -                   10     4 
+    -                    8     4 
+    -                    6     7 
+    -                    5    12 
+    -                    4    12 
+    -                    2     6 
+    and                          
+    -                    3     1 
+    -                    2    18 
+    mul                          
+    -                   12    15 
+    -                   11     3 
+    -                    9     3 
+    mux                          
+    -                    2    15 
+    -                    1    19 
+    nand                         
+    -                    3     1 
+    -                    2     4 
+    nor                          
+    -                    2     4 
+    not                          
+    -                    3    12 
+    -                    1    28 
+    or                           
+    -                    3     3 
+    -                    2     8 
+    read_port                    
+    -                   90     1 
+    reg                          
+    -                   90     3 
+    -                   30     1 
+    -                   19     1 
+    -                   16     6 
+    -                   15     3 
+    -                   11     2 
+    -                    9     3 
+    -                    6     4 
+    -                    5     3 
+    -                    2     4 
+    -                    1    12 
+    write_port                   
+    -                   30     1 
+    
+  End of Report
diff --git a/Sobel/sobel.v10/rtl.v b/Sobel/sobel.v10/rtl.v
new file mode 100644
index 0000000..8310e1c
--- /dev/null
+++ b/Sobel/sobel.v10/rtl.v
@@ -0,0 +1,912 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 15:50:39 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  wire and_dcpl_1;
+  wire or_dcpl_2;
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [14:0] b_1_sg1_lpi_1;
+  reg [15:0] b_0_lpi_1;
+  reg [15:0] b_2_lpi_1;
+  reg [14:0] g_1_sg1_lpi_1;
+  reg [15:0] g_0_lpi_1;
+  reg [15:0] g_2_lpi_1;
+  reg [14:0] r_1_sg1_lpi_1;
+  reg [15:0] r_0_lpi_1;
+  reg [15:0] r_2_lpi_1;
+  reg [1:0] i_6_lpi_1;
+  reg exit_FRAME_for_lpi_1;
+  reg [1:0] i_7_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [89:0] regs_regs_2_lpi_1_dfm;
+  reg exit_FRAME_lpi_1_dfm_2;
+  reg exit_FRAME_for_1_lpi_1_dfm_4;
+  reg [10:0] FRAME_mul_2_itm_1;
+  wire [21:0] nl_FRAME_mul_2_itm_1;
+  reg [8:0] FRAME_mul_3_itm_1;
+  wire [17:0] nl_FRAME_mul_3_itm_1;
+  reg [5:0] green_slc_green_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_18_itm_1;
+  wire [5:0] nl_FRAME_acc_18_itm_1;
+  reg FRAME_slc_acc_imod_11_4_itm_1;
+  reg green_slc_green_2_sg1_12_itm_1;
+  reg [10:0] FRAME_mul_4_itm_1;
+  wire [21:0] nl_FRAME_mul_4_itm_1;
+  reg [8:0] FRAME_mul_5_itm_1;
+  wire [17:0] nl_FRAME_mul_5_itm_1;
+  reg [5:0] blue_slc_blue_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_30_itm_1;
+  wire [5:0] nl_FRAME_acc_30_itm_1;
+  reg FRAME_slc_acc_imod_13_4_itm_1;
+  reg blue_slc_blue_2_sg1_12_itm_1;
+  reg [8:0] FRAME_mul_1_itm_1;
+  wire [17:0] nl_FRAME_mul_1_itm_1;
+  reg [5:0] red_slc_red_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_37_itm_1;
+  wire [5:0] nl_FRAME_acc_37_itm_1;
+  reg FRAME_slc_acc_imod_9_4_itm_1;
+  reg exit_FRAME_for_lpi_1_dfm_st_1;
+  reg exit_FRAME_for_1_sva_2_st_1;
+  reg main_stage_0_2;
+  reg [1:0] FRAME_acc_41_itm_1_sg2;
+  wire [2:0] nl_FRAME_acc_41_itm_1_sg2;
+  reg [1:0] FRAME_acc_41_itm_1_sg1;
+  reg [5:0] FRAME_acc_41_itm_3;
+  wire [6:0] nl_FRAME_acc_41_itm_3;
+  wire or_4_cse;
+  wire or_9_cse;
+  wire exit_FRAME_for_1_lpi_1_dfm_5;
+  wire [1:0] FRAME_for_1_acc_itm;
+  wire [2:0] nl_FRAME_for_1_acc_itm;
+  wire [7:0] FRAME_acc_itm;
+  wire [8:0] nl_FRAME_acc_itm;
+  wire [11:0] FRAME_acc_3_psp_sva;
+  wire [13:0] nl_FRAME_acc_3_psp_sva;
+  wire [11:0] FRAME_acc_4_psp_sva;
+  wire [13:0] nl_FRAME_acc_4_psp_sva;
+  wire exit_FRAME_for_lpi_1_dfm;
+  wire [1:0] i_7_sva;
+  wire [2:0] nl_i_7_sva;
+  wire exit_FRAME_for_1_lpi_1_dfm_4_mx0;
+  wire [89:0] regs_regs_2_lpi_1_dfm_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire exit_FRAME_lpi_1_dfm_2_mx0;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [5:0] acc_imod_9_sva;
+  wire [7:0] nl_acc_imod_9_sva;
+  wire [9:0] FRAME_mul_sdt;
+  wire [19:0] nl_FRAME_mul_sdt;
+  wire [5:0] acc_imod_13_sva;
+  wire [7:0] nl_acc_imod_13_sva;
+  wire [5:0] acc_imod_11_sva;
+  wire [7:0] nl_acc_imod_11_sva;
+  wire [14:0] b_1_sg1_lpi_1_dfm;
+  wire [15:0] b_2_sva_1;
+  wire [16:0] nl_b_2_sva_1;
+  wire [15:0] b_0_sva_1;
+  wire [16:0] nl_b_0_sva_1;
+  wire [14:0] g_1_sg1_lpi_1_dfm;
+  wire [15:0] g_2_sva_1;
+  wire [16:0] nl_g_2_sva_1;
+  wire [15:0] g_0_sva_1;
+  wire [16:0] nl_g_0_sva_1;
+  wire [14:0] r_1_sg1_lpi_1_dfm;
+  wire [15:0] r_2_sva_1;
+  wire [16:0] nl_r_2_sva_1;
+  wire [15:0] r_0_sva_1;
+  wire [16:0] nl_r_0_sva_1;
+  wire [15:0] b_2_lpi_1_dfm;
+  wire FRAME_for_1_nor_cse;
+  wire [15:0] g_2_lpi_1_dfm;
+  wire [15:0] r_2_lpi_1_dfm;
+  wire [15:0] b_0_lpi_1_dfm;
+  wire [15:0] g_0_lpi_1_dfm;
+  wire [15:0] r_0_lpi_1_dfm;
+  wire [1:0] i_6_sva_1;
+  wire [2:0] nl_i_6_sva_1;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire FRAME_for_nor_cse;
+  wire FRAME_for_and_18_seb;
+  wire [1:0] FRAME_for_acc_5_tmp;
+  wire [2:0] nl_FRAME_for_acc_5_tmp;
+  wire not_24;
+  wire [15:0] ACC2_3_acc_1_itm;
+  wire [16:0] nl_ACC2_3_acc_1_itm;
+  wire [15:0] ACC2_3_acc_3_itm;
+  wire [16:0] nl_ACC2_3_acc_3_itm;
+  wire [15:0] ACC2_3_acc_2_itm;
+  wire [16:0] nl_ACC2_3_acc_2_itm;
+  wire FRAME_for_1_or_1_itm;
+  wire FRAME_for_1_or_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_itm;
+  wire FRAME_for_or_5_itm;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+
+  wire[9:0] regs_operator_35_mux_nl;
+  wire[9:0] regs_operator_29_mux_nl;
+  wire[9:0] regs_operator_34_mux_nl;
+  wire[9:0] regs_operator_28_mux_nl;
+  wire[9:0] regs_operator_33_mux_nl;
+  wire[9:0] regs_operator_27_mux_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_3_psp_sva = (conv_u2s_11_12(FRAME_mul_2_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_3_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(green_slc_green_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_18_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_11_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({green_slc_green_2_sg1_12_itm_1
+      , 3'b0 , ({{2{green_slc_green_2_sg1_12_itm_1}}, green_slc_green_2_sg1_12_itm_1})
+      , 1'b0 , green_slc_green_2_sg1_12_itm_1}));
+  assign FRAME_acc_3_psp_sva = nl_FRAME_acc_3_psp_sva[11:0];
+  assign nl_FRAME_acc_4_psp_sva = (conv_u2s_11_12(FRAME_mul_4_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_5_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(blue_slc_blue_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_30_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_13_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({blue_slc_blue_2_sg1_12_itm_1
+      , 3'b0 , ({{2{blue_slc_blue_2_sg1_12_itm_1}}, blue_slc_blue_2_sg1_12_itm_1})
+      , 1'b0 , blue_slc_blue_2_sg1_12_itm_1}));
+  assign FRAME_acc_4_psp_sva = nl_FRAME_acc_4_psp_sva[11:0];
+  assign nl_FRAME_for_1_acc_itm = i_7_sva + 2'b1;
+  assign FRAME_for_1_acc_itm = nl_FRAME_for_1_acc_itm[1:0];
+  assign exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_lpi_1 & not_24;
+  assign nl_i_7_sva = i_7_lpi_1 + 2'b1;
+  assign i_7_sva = nl_i_7_sva[1:0];
+  assign exit_FRAME_for_1_lpi_1_dfm_4_mx0 = MUX_s_1_2_2({(exit_FRAME_for_1_lpi_1_dfm_5
+      | (FRAME_acc_itm[7])) , exit_FRAME_for_1_lpi_1_dfm_5}, or_9_cse);
+  assign regs_regs_2_lpi_1_dfm_mx0 = MUX_v_90_2_2({regs_regs_1_sva , regs_regs_2_lpi_1_dfm},
+      and_dcpl_1);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_dcpl_1);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_dcpl_1);
+  assign nl_FRAME_acc_itm = conv_u2s_7_8(FRAME_p_1_sva_1[18:12]) + 8'b10110101;
+  assign FRAME_acc_itm = nl_FRAME_acc_itm[7:0];
+  assign exit_FRAME_lpi_1_dfm_2_mx0 = MUX_s_1_2_2({(~ (FRAME_acc_itm[7])) , (exit_FRAME_lpi_1_dfm_2
+      & not_24)}, or_9_cse);
+  assign exit_FRAME_for_1_lpi_1_dfm_5 = (~ (FRAME_for_1_acc_itm[1])) & exit_FRAME_for_lpi_1_dfm;
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign nl_acc_imod_9_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC2_3_acc_1_itm[9:7])
+      + conv_u2u_3_4(~ (ACC2_3_acc_1_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC2_3_acc_1_itm[15])) , 1'b1 , (~ (ACC2_3_acc_1_itm[15]))}) + conv_u2u_2_4(ACC2_3_acc_1_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC2_3_acc_1_itm[3:1]) + conv_u2u_3_4(~ (ACC2_3_acc_1_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_9_sva = nl_acc_imod_9_sva[5:0];
+  assign nl_ACC2_3_acc_1_itm = ({(r_1_sg1_lpi_1_dfm + (r_2_sva_1[15:1])) , (r_2_sva_1[0])})
+      + r_0_sva_1;
+  assign ACC2_3_acc_1_itm = nl_ACC2_3_acc_1_itm[15:0];
+  assign nl_FRAME_mul_sdt = conv_u2u_2_10(ACC2_3_acc_1_itm[14:13]) * 10'b111000111;
+  assign FRAME_mul_sdt = nl_FRAME_mul_sdt[9:0];
+  assign nl_ACC2_3_acc_3_itm = ({(b_1_sg1_lpi_1_dfm + (b_2_sva_1[15:1])) , (b_2_sva_1[0])})
+      + b_0_sva_1;
+  assign ACC2_3_acc_3_itm = nl_ACC2_3_acc_3_itm[15:0];
+  assign nl_acc_imod_13_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC2_3_acc_3_itm[9:7])
+      + conv_u2u_3_4(~ (ACC2_3_acc_3_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC2_3_acc_3_itm[15])) , 1'b1 , (~ (ACC2_3_acc_3_itm[15]))}) + conv_u2u_2_4(ACC2_3_acc_3_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC2_3_acc_3_itm[3:1]) + conv_u2u_3_4(~ (ACC2_3_acc_3_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_13_sva = nl_acc_imod_13_sva[5:0];
+  assign nl_ACC2_3_acc_2_itm = ({(g_1_sg1_lpi_1_dfm + (g_2_sva_1[15:1])) , (g_2_sva_1[0])})
+      + g_0_sva_1;
+  assign ACC2_3_acc_2_itm = nl_ACC2_3_acc_2_itm[15:0];
+  assign nl_acc_imod_11_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC2_3_acc_2_itm[9:7])
+      + conv_u2u_3_4(~ (ACC2_3_acc_2_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC2_3_acc_2_itm[15])) , 1'b1 , (~ (ACC2_3_acc_2_itm[15]))}) + conv_u2u_2_4(ACC2_3_acc_2_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC2_3_acc_2_itm[3:1]) + conv_u2u_3_4(~ (ACC2_3_acc_2_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_11_sva = nl_acc_imod_11_sva[5:0];
+  assign b_1_sg1_lpi_1_dfm = b_1_sg1_lpi_1 & ({{14{not_24}}, not_24});
+  assign regs_operator_35_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[69:60]) , (regs_regs_1_sva[69:60])
+      , (regs_regs_2_lpi_1_dfm[69:60]) , 10'b0}, i_7_lpi_1);
+  assign nl_b_2_sva_1 = b_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_35_mux_nl)
+      * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_or_1_itm})));
+  assign b_2_sva_1 = nl_b_2_sva_1[15:0];
+  assign regs_operator_29_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[9:0]) , (regs_regs_1_sva[9:0])
+      , (regs_regs_2_lpi_1_dfm[9:0]) , 10'b0}, i_7_lpi_1);
+  assign nl_b_0_sva_1 = b_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_29_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_1_or_itm})));
+  assign b_0_sva_1 = nl_b_0_sva_1[15:0];
+  assign g_1_sg1_lpi_1_dfm = g_1_sg1_lpi_1 & ({{14{not_24}}, not_24});
+  assign regs_operator_34_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[79:70]) , (regs_regs_1_sva[79:70])
+      , (regs_regs_2_lpi_1_dfm[79:70]) , 10'b0}, i_7_lpi_1);
+  assign nl_g_2_sva_1 = g_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_34_mux_nl)
+      * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_or_1_itm})));
+  assign g_2_sva_1 = nl_g_2_sva_1[15:0];
+  assign regs_operator_28_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[19:10]) , (regs_regs_1_sva[19:10])
+      , (regs_regs_2_lpi_1_dfm[19:10]) , 10'b0}, i_7_lpi_1);
+  assign nl_g_0_sva_1 = g_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_28_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_1_or_itm})));
+  assign g_0_sva_1 = nl_g_0_sva_1[15:0];
+  assign r_1_sg1_lpi_1_dfm = r_1_sg1_lpi_1 & ({{14{not_24}}, not_24});
+  assign regs_operator_33_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[89:80]) , (regs_regs_1_sva[89:80])
+      , (regs_regs_2_lpi_1_dfm[89:80]) , 10'b0}, i_7_lpi_1);
+  assign nl_r_2_sva_1 = r_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_33_mux_nl)
+      * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_or_1_itm})));
+  assign r_2_sva_1 = nl_r_2_sva_1[15:0];
+  assign regs_operator_27_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[29:20]) , (regs_regs_1_sva[29:20])
+      , (regs_regs_2_lpi_1_dfm[29:20]) , 10'b0}, i_7_lpi_1);
+  assign nl_r_0_sva_1 = r_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_27_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_1_or_itm})));
+  assign r_0_sva_1 = nl_r_0_sva_1[15:0];
+  assign b_2_lpi_1_dfm = b_2_lpi_1 & ({{15{not_24}}, not_24});
+  assign FRAME_for_1_nor_cse = ~((i_7_lpi_1[1]) | (i_7_lpi_1[0]));
+  assign g_2_lpi_1_dfm = g_2_lpi_1 & ({{15{not_24}}, not_24});
+  assign r_2_lpi_1_dfm = r_2_lpi_1 & ({{15{not_24}}, not_24});
+  assign b_0_lpi_1_dfm = b_0_lpi_1 & ({{15{not_24}}, not_24});
+  assign g_0_lpi_1_dfm = g_0_lpi_1 & ({{15{not_24}}, not_24});
+  assign r_0_lpi_1_dfm = r_0_lpi_1 & ({{15{not_24}}, not_24});
+  assign nl_i_6_sva_1 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_1 = nl_i_6_sva_1[1:0];
+  assign i_6_lpi_1_dfm = i_6_lpi_1 & ({{1{not_24}}, not_24});
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_and_18_seb = (FRAME_for_acc_5_tmp[1]) & (FRAME_for_acc_5_tmp[0]);
+  assign nl_FRAME_for_acc_5_tmp = i_6_lpi_1_dfm + 2'b11;
+  assign FRAME_for_acc_5_tmp = nl_FRAME_for_acc_5_tmp[1:0];
+  assign not_24 = ~(exit_FRAME_for_1_lpi_1_dfm_4 | exit_FRAME_1_sva);
+  assign FRAME_for_1_or_1_itm = (~((~ (i_7_lpi_1[1])) & (i_7_lpi_1[0]))) | FRAME_for_1_nor_cse;
+  assign FRAME_for_1_or_itm = (~((i_7_lpi_1[0]) & (~ (i_7_lpi_1[1])))) | FRAME_for_1_nor_cse
+      | ((i_7_lpi_1[1]) & (~ (i_7_lpi_1[0])));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) | FRAME_for_nor_cse;
+  assign FRAME_for_or_5_itm = (FRAME_for_acc_5_tmp[1]) | (FRAME_for_acc_5_tmp[0])
+      | FRAME_for_and_18_seb;
+  assign and_dcpl_1 = ~(exit_FRAME_1_sva | exit_FRAME_for_1_lpi_1_dfm_4);
+  assign or_dcpl_2 = exit_FRAME_1_sva | exit_FRAME_for_1_lpi_1_dfm_4;
+  assign or_4_cse = or_dcpl_2 | (~ exit_FRAME_for_lpi_1);
+  assign or_9_cse = or_dcpl_2 | (~ exit_FRAME_for_lpi_1) | (FRAME_for_1_acc_itm[1]);
+  assign nl_FRAME_for_acc_itm = i_6_sva_1 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      FRAME_acc_41_itm_1_sg2 <= 2'b0;
+      FRAME_acc_41_itm_1_sg1 <= 2'b0;
+      FRAME_acc_41_itm_3 <= 6'b0;
+      FRAME_mul_1_itm_1 <= 9'b0;
+      red_slc_red_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_37_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_9_4_itm_1 <= 1'b0;
+      FRAME_mul_4_itm_1 <= 11'b0;
+      FRAME_mul_5_itm_1 <= 9'b0;
+      blue_slc_blue_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_30_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_13_4_itm_1 <= 1'b0;
+      blue_slc_blue_2_sg1_12_itm_1 <= 1'b0;
+      FRAME_mul_2_itm_1 <= 11'b0;
+      FRAME_mul_3_itm_1 <= 9'b0;
+      green_slc_green_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_18_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_11_4_itm_1 <= 1'b0;
+      green_slc_green_2_sg1_12_itm_1 <= 1'b0;
+      exit_FRAME_for_1_sva_2_st_1 <= 1'b0;
+      exit_FRAME_for_lpi_1_dfm_st_1 <= 1'b0;
+      i_7_lpi_1 <= 2'b0;
+      exit_FRAME_for_lpi_1 <= 1'b0;
+      exit_FRAME_for_1_lpi_1_dfm_4 <= 1'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_2_lpi_1_dfm <= 90'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_2 <= 1'b0;
+      b_1_sg1_lpi_1 <= 15'b0;
+      g_1_sg1_lpi_1 <= 15'b0;
+      r_1_sg1_lpi_1 <= 15'b0;
+      i_6_lpi_1 <= 2'b0;
+      b_2_lpi_1 <= 16'b0;
+      b_0_lpi_1 <= 16'b0;
+      g_2_lpi_1 <= 16'b0;
+      g_0_lpi_1 <= 16'b0;
+      r_2_lpi_1 <= 16'b0;
+      r_0_lpi_1 <= 16'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({({((({FRAME_acc_41_itm_1_sg2 ,
+            FRAME_acc_41_itm_1_sg1 , FRAME_acc_41_itm_3}) + (conv_u2s_9_10(FRAME_mul_1_itm_1)
+            + conv_s2s_8_10(conv_u2s_6_8(red_slc_red_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_37_itm_1
+            + ({4'b1001 , FRAME_slc_acc_imod_9_4_itm_1}))))) | ({8'b0 , (FRAME_acc_3_psp_sva[11:10])}))
+            , (FRAME_acc_3_psp_sva[9:6]) , ((FRAME_acc_3_psp_sva[5:0]) | ({4'b0 ,
+            (FRAME_acc_4_psp_sva[11:10])})) , (FRAME_acc_4_psp_sva[9:0])}) , vout_rsc_mgc_out_stdreg_d},
+            ~(exit_FRAME_for_1_sva_2_st_1 & exit_FRAME_for_lpi_1_dfm_st_1 & main_stage_0_2));
+        FRAME_acc_41_itm_1_sg2 <= nl_FRAME_acc_41_itm_1_sg2[1:0];
+        FRAME_acc_41_itm_1_sg1 <= FRAME_mul_sdt[7:6];
+        FRAME_acc_41_itm_3 <= nl_FRAME_acc_41_itm_3[5:0];
+        FRAME_mul_1_itm_1 <= nl_FRAME_mul_1_itm_1[8:0];
+        red_slc_red_2_sg1_itm_1 <= ACC2_3_acc_1_itm[9:4];
+        FRAME_acc_37_itm_1 <= nl_FRAME_acc_37_itm_1[4:0];
+        FRAME_slc_acc_imod_9_4_itm_1 <= acc_imod_9_sva[5];
+        FRAME_mul_4_itm_1 <= nl_FRAME_mul_4_itm_1[10:0];
+        FRAME_mul_5_itm_1 <= nl_FRAME_mul_5_itm_1[8:0];
+        blue_slc_blue_2_sg1_itm_1 <= ACC2_3_acc_3_itm[9:4];
+        FRAME_acc_30_itm_1 <= nl_FRAME_acc_30_itm_1[4:0];
+        FRAME_slc_acc_imod_13_4_itm_1 <= acc_imod_13_sva[5];
+        blue_slc_blue_2_sg1_12_itm_1 <= ACC2_3_acc_3_itm[15];
+        FRAME_mul_2_itm_1 <= nl_FRAME_mul_2_itm_1[10:0];
+        FRAME_mul_3_itm_1 <= nl_FRAME_mul_3_itm_1[8:0];
+        green_slc_green_2_sg1_itm_1 <= ACC2_3_acc_2_itm[9:4];
+        FRAME_acc_18_itm_1 <= nl_FRAME_acc_18_itm_1[4:0];
+        FRAME_slc_acc_imod_11_4_itm_1 <= acc_imod_11_sva[5];
+        green_slc_green_2_sg1_12_itm_1 <= ACC2_3_acc_2_itm[15];
+        exit_FRAME_for_1_sva_2_st_1 <= ~ (FRAME_for_1_acc_itm[1]);
+        exit_FRAME_for_lpi_1_dfm_st_1 <= exit_FRAME_for_lpi_1_dfm;
+        i_7_lpi_1 <= MUX_v_2_2_2({i_7_sva , (i_7_lpi_1 & (signext_2_1(FRAME_for_acc_itm[1])))},
+            or_4_cse);
+        exit_FRAME_for_lpi_1 <= MUX_s_1_2_2({exit_FRAME_for_lpi_1_dfm , (~ (FRAME_for_acc_itm[1]))},
+            or_4_cse);
+        exit_FRAME_for_1_lpi_1_dfm_4 <= exit_FRAME_for_1_lpi_1_dfm_4_mx0;
+        exit_FRAME_1_sva <= exit_FRAME_for_1_lpi_1_dfm_4_mx0 & exit_FRAME_lpi_1_dfm_2_mx0;
+        main_stage_0_2 <= 1'b1;
+        regs_regs_2_lpi_1_dfm <= regs_regs_2_lpi_1_dfm_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_2 <= exit_FRAME_lpi_1_dfm_2_mx0;
+        b_1_sg1_lpi_1 <= MUX_v_15_2_2({b_1_sg1_lpi_1_dfm , (b_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[39:30])
+            , (regs_regs_1_sva_dfm_mx0[39:30]) , (regs_regs_2_lpi_1_dfm_mx0[39:30])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_or_5_itm}))))},
+            or_4_cse);
+        g_1_sg1_lpi_1 <= MUX_v_15_2_2({g_1_sg1_lpi_1_dfm , (g_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[49:40])
+            , (regs_regs_1_sva_dfm_mx0[49:40]) , (regs_regs_2_lpi_1_dfm_mx0[49:40])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_or_5_itm}))))},
+            or_4_cse);
+        r_1_sg1_lpi_1 <= MUX_v_15_2_2({r_1_sg1_lpi_1_dfm , (r_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[59:50])
+            , (regs_regs_1_sva_dfm_mx0[59:50]) , (regs_regs_2_lpi_1_dfm_mx0[59:50])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_or_5_itm}))))},
+            or_4_cse);
+        i_6_lpi_1 <= MUX_v_2_2_2({i_6_lpi_1_dfm , i_6_sva_1}, or_4_cse);
+        b_2_lpi_1 <= MUX_v_16_2_2({b_2_sva_1 , (b_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+            , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_mx0[69:60])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))},
+            or_4_cse);
+        b_0_lpi_1 <= MUX_v_16_2_2({b_0_sva_1 , (b_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0])
+            , (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_mx0[9:0]) ,
+            10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_itm}))))},
+            or_4_cse);
+        g_2_lpi_1 <= MUX_v_16_2_2({g_2_sva_1 , (g_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+            , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_mx0[79:70])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))},
+            or_4_cse);
+        g_0_lpi_1 <= MUX_v_16_2_2({g_0_sva_1 , (g_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+            , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_mx0[19:10])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_itm}))))},
+            or_4_cse);
+        r_2_lpi_1 <= MUX_v_16_2_2({r_2_sva_1 , (r_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+            , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_mx0[89:80])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))},
+            or_4_cse);
+        r_0_lpi_1 <= MUX_v_16_2_2({r_0_sva_1 , (r_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+            , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_mx0[29:20])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_itm}))))},
+            or_4_cse);
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_lpi_1_dfm , FRAME_p_1_sva_1},
+            and_dcpl_1 & exit_FRAME_for_lpi_1 & (~ (FRAME_for_1_acc_itm[1])));
+      end
+    end
+  end
+  assign nl_FRAME_acc_41_itm_1_sg2  = (FRAME_mul_sdt[9:8]) + conv_s2u_1_2(ACC2_3_acc_1_itm[15]);
+  assign nl_FRAME_acc_41_itm_3  = conv_u2u_5_6(FRAME_mul_sdt[4:0]) + conv_u2u_5_6(signext_5_3({(ACC2_3_acc_1_itm[15])
+      , 1'b0 , (ACC2_3_acc_1_itm[15])}));
+  assign nl_FRAME_mul_1_itm_1  = conv_u2u_3_9(ACC2_3_acc_1_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_37_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_9_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_9_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_9_sva[5:3])) , (~ (acc_imod_9_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_9_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC2_3_acc_1_itm[9:7]));
+  assign nl_FRAME_mul_4_itm_1  = conv_u2u_2_11(ACC2_3_acc_3_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_5_itm_1  = conv_u2u_3_9(ACC2_3_acc_3_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_30_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_13_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_13_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_13_sva[5:3])) , (~ (acc_imod_13_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_13_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC2_3_acc_3_itm[9:7]));
+  assign nl_FRAME_mul_2_itm_1  = conv_u2u_2_11(ACC2_3_acc_2_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_3_itm_1  = conv_u2u_3_9(ACC2_3_acc_2_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_18_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_11_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_11_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_11_sva[5:3])) , (~ (acc_imod_11_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_11_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC2_3_acc_2_itm[9:7]));
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] MUX_v_2_2_2;
+    input [3:0] inputs;
+    input [0:0] sel;
+    reg [1:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[3:2];
+      end
+      1'b1 : begin
+        result = inputs[1:0];
+      end
+      default : begin
+        result = inputs[3:2];
+      end
+    endcase
+    MUX_v_2_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [14:0] MUX_v_15_2_2;
+    input [29:0] inputs;
+    input [0:0] sel;
+    reg [14:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[29:15];
+      end
+      1'b1 : begin
+        result = inputs[14:0];
+      end
+      default : begin
+        result = inputs[29:15];
+      end
+    endcase
+    MUX_v_15_2_2 = result;
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_11_15 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_15 = {{4{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_s2u_1_2 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_2 = {vector[0], vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v10/rtl.v.psr b/Sobel/sobel.v10/rtl.v.psr
new file mode 100644
index 0000000..b7f7825
--- /dev/null
+++ b/Sobel/sobel.v10/rtl.v.psr
@@ -0,0 +1,289 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v10/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v10/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v10/rtl.v}} -format verilog
+   setup_design -design=sobel
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'sobel': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'sobel': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'sobel'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'sobel'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to vout_rsc_z(29:0)
+   report_timing -from en -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from vin_rsc_z(89:0) -to vout_rsc_z(29:0)
+   report_timing -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock clk] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock en] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'sobel'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'sobel'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v10 mapped.v]
+          puts "-- Writing mapped netlist for 'sobel' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v10 gate.v]
+          set gate_sdf [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v10 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/Sobel/sobel.v10/rtl.v.psr_timing b/Sobel/sobel.v10/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/Sobel/sobel.v10/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/Sobel/sobel.v10/rtl.v_order.txt b/Sobel/sobel.v10/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/Sobel/sobel.v10/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/Sobel/sobel.v10/rtl_mgc_ioport.v b/Sobel/sobel.v10/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v10/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v10/rtl_mgc_ioport_v2001.v b/Sobel/sobel.v10/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v10/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v10/schedule.gnt b/Sobel/sobel.v10/schedule.gnt
new file mode 100644
index 0000000..35246c3
--- /dev/null
+++ b/Sobel/sobel.v10/schedule.gnt
@@ -0,0 +1,501 @@
+set a(0-6498) {NAME i:asn(i#7.lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42303 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6499) {NAME FRAME:for:asn(exit:FRAME:for.lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42304 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6500) {NAME i:asn(i#6.lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42305 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6501) {NAME regs.regs:asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42306 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6502) {NAME r:asn(r(2).lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42307 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6503) {NAME r:asn(r(0).lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42308 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6504) {NAME r:asn(r(1).sg1.lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42309 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6505) {NAME g:asn(g(2).lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42310 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6506) {NAME g:asn(g(0).lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42311 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6507) {NAME g:asn(g(1).sg1.lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42312 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6508) {NAME b:asn(b(2).lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42313 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6509) {NAME b:asn(b(0).lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42314 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6510) {NAME b:asn(b(1).sg1.lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42315 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6511) {NAME FRAME:asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42316 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6512) {NAME FRAME:for#1:asn(exit:FRAME:for#1.lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42317 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6513) {NAME FRAME:p:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-6497 XREFS 42318 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6514) {NAME asn(regs.regs(1))#1 TYPE ASSIGN PAR 0-6497 XREFS 42319 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6515) {NAME asn(regs.regs(0))#1 TYPE ASSIGN PAR 0-6497 XREFS 42320 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{258 0 0-6517 {}}} CYCLES {}}
+set a(0-6516) {NAME asn(exit:FRAME#1)#2 TYPE ASSIGN PAR 0-6497 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6517 {}}} SUCCS {{259 0 0-6517 {}}} CYCLES {}}
+set a(0-6518) {NAME FRAME:for:asn(i#7.lpi#1.dfm) TYPE ASSIGN PAR 0-6517 XREFS 42321 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 2 0.619485875} PREDS {} SUCCS {{258 0 0-6983 {}}} CYCLES {}}
+set a(0-6519) {NAME FRAME:for:asn(exit:FRAME:for.sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42322 LOC {0 1.0 1 0.9605326249999999 1 0.9605326249999999 2 0.619485875} PREDS {} SUCCS {{258 0 0-6989 {}}} CYCLES {}}
+set a(0-6520) {NAME i:asn(i#6.sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42323 LOC {0 1.0 1 0.9129764499999999 1 0.9129764499999999 3 0.457609925} PREDS {} SUCCS {{258 0 0-6982 {}}} CYCLES {}}
+set a(0-6521) {NAME b:asn(b(2).sva#2) TYPE ASSIGN PAR 0-6517 XREFS 42324 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 2 0.854530825} PREDS {} SUCCS {{258 0 0-6979 {}}} CYCLES {}}
+set a(0-6522) {NAME g:asn(g(2).sva#2) TYPE ASSIGN PAR 0-6517 XREFS 42325 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 2 0.854530825} PREDS {} SUCCS {{258 0 0-6977 {}}} CYCLES {}}
+set a(0-6523) {NAME r:asn(r(2).sva#2) TYPE ASSIGN PAR 0-6517 XREFS 42326 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 2 0.9769393999999999} PREDS {} SUCCS {{258 0 0-6975 {}}} CYCLES {}}
+set a(0-6524) {NAME b:asn(b(1).sg1.sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42327 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 3 0.015707075} PREDS {} SUCCS {{258 0 0-6986 {}}} CYCLES {}}
+set a(0-6525) {NAME g:asn(g(1).sg1.sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42328 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 3 0.015707075} PREDS {} SUCCS {{258 0 0-6985 {}}} CYCLES {}}
+set a(0-6526) {NAME r:asn(r(1).sg1.sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42329 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 3 0.099592} PREDS {} SUCCS {{258 0 0-6984 {}}} CYCLES {}}
+set a(0-6527) {NAME b:asn(b(0).sva#2) TYPE ASSIGN PAR 0-6517 XREFS 42330 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 3 0.015315049999999998} PREDS {} SUCCS {{258 0 0-6978 {}}} CYCLES {}}
+set a(0-6528) {NAME g:asn(g(0).sva#2) TYPE ASSIGN PAR 0-6517 XREFS 42331 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 3 0.015315049999999998} PREDS {} SUCCS {{258 0 0-6976 {}}} CYCLES {}}
+set a(0-6529) {NAME r:asn(r(0).sva#2) TYPE ASSIGN PAR 0-6517 XREFS 42332 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 3 0.099199975} PREDS {} SUCCS {{258 0 0-6974 {}}} CYCLES {}}
+set a(0-6530) {NAME FRAME:asn(exit:FRAME.sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42333 LOC {0 1.0 1 0.9308181999999999 1 0.9308181999999999 2 0.550304075} PREDS {} SUCCS {{258 0 0-6965 {}}} CYCLES {}}
+set a(0-6531) {NAME FRAME:p:asn(FRAME:p#1.sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42334 LOC {0 1.0 1 0.858003 1 0.858003 3 0.318762125} PREDS {} SUCCS {{258 0 0-6981 {}}} CYCLES {}}
+set a(0-6532) {NAME FRAME:for#1:asn(exit:FRAME:for#1.sva#2) TYPE ASSIGN PAR 0-6517 XREFS 42335 LOC {0 1.0 1 0.4061093 1 0.4061093 2 0.550304075} PREDS {} SUCCS {{258 0 0-6965 {}} {258 0 0-6967 {}} {258 0 0-6980 {}}} CYCLES {}}
+set a(0-6533) {NAME i:asn(i#7.sva) TYPE ASSIGN PAR 0-6517 XREFS 42336 LOC {0 1.0 1 0.358553125 1 0.358553125 2 0.619485875} PREDS {} SUCCS {{258 0 0-6983 {}}} CYCLES {}}
+set a(0-6534) {NAME b:asn(b(2).sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42337 LOC {0 1.0 1 0.4061093 1 0.4061093 2 0.854530825} PREDS {} SUCCS {{258 0 0-6979 {}}} CYCLES {}}
+set a(0-6535) {NAME g:asn(g(2).sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42338 LOC {0 1.0 1 0.4061093 1 0.4061093 2 0.854530825} PREDS {} SUCCS {{258 0 0-6977 {}}} CYCLES {}}
+set a(0-6536) {NAME r:asn(r(2).sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42339 LOC {0 1.0 1 0.4061093 1 0.4061093 2 0.9769393999999999} PREDS {} SUCCS {{258 0 0-6975 {}}} CYCLES {}}
+set a(0-6537) {NAME b:asn(b(0).sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42340 LOC {0 1.0 1 0.511719075 1 0.511719075 3 0.015315049999999998} PREDS {} SUCCS {{258 0 0-6978 {}}} CYCLES {}}
+set a(0-6538) {NAME g:asn(g(0).sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42341 LOC {0 1.0 1 0.511719075 1 0.511719075 3 0.015315049999999998} PREDS {} SUCCS {{258 0 0-6976 {}}} CYCLES {}}
+set a(0-6539) {NAME r:asn(r(0).sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42342 LOC {0 1.0 1 0.511719075 1 0.511719075 3 0.099199975} PREDS {} SUCCS {{258 0 0-6974 {}}} CYCLES {}}
+set a(0-6540) {NAME regs.regs:asn(regs.regs(0).sva#1) TYPE ASSIGN PAR 0-6517 XREFS 42343 LOC {0 1.0 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {} SUCCS {{258 0 0-6552 {}}} CYCLES {}}
+set a(0-6541) {NAME asn#213 TYPE ASSIGN PAR 0-6517 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-6991 {}}} SUCCS {{259 0 0-6542 {}} {256 0 0-6991 {}}} CYCLES {}}
+set a(0-6542) {NAME select TYPE SELECT PAR 0-6517 LOC {0 1.0 0 1.0 0 1.0 3 1.0} PREDS {{259 0 0-6541 {}}} SUCCS {} CYCLES {}}
+set a(0-6543) {NAME FRAME:asn TYPE ASSIGN PAR 0-6517 XREFS 42344 LOC {0 1.0 1 0.7223368499999999 1 0.7223368499999999 2 0.341822725} PREDS {{262 0 0-6991 {}}} SUCCS {{259 0 0-6544 {}} {256 0 0-6991 {}}} CYCLES {}}
+set a(0-6544) {NAME FRAME:not#28 TYPE NOT PAR 0-6517 XREFS 42345 LOC {1 0.0 1 0.7223368499999999 1 0.7223368499999999 2 0.341822725} PREDS {{259 0 0-6543 {}}} SUCCS {{259 0 0-6545 {}}} CYCLES {}}
+set a(0-6545) {NAME exs TYPE SIGNEXTEND PAR 0-6517 LOC {1 0.0 1 0.7223368499999999 1 0.7223368499999999 2 0.341822725} PREDS {{259 0 0-6544 {}}} SUCCS {{259 0 0-6546 {}}} CYCLES {}}
+set a(0-6546) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(19,2) AREA_SCORE 13.87 QUANTITY 1 NAME and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 LOC {1 0.0 1 0.7223368499999999 1 0.7223368499999999 1 0.7387435812638539 2 0.3582294562638539} PREDS {{262 0 0-6981 {}} {259 0 0-6545 {}}} SUCCS {{258 0 0-6856 {}} {258 0 0-6981 {}}} CYCLES {}}
+set a(0-6547) {NAME asn#214 TYPE ASSIGN PAR 0-6517 LOC {0 1.0 1 0.0 1 0.0 1 0.619485875} PREDS {{262 0 0-6991 {}}} SUCCS {{259 0 0-6548 {}} {256 0 0-6991 {}}} CYCLES {}}
+set a(0-6548) {NAME or TYPE OR PAR 0-6517 LOC {1 0.0 1 0.0 1 0.0 1 0.619485875} PREDS {{262 0 0-6988 {}} {259 0 0-6547 {}}} SUCCS {{259 0 0-6549 {}} {258 0 0-6552 {}} {258 0 0-6555 {}} {258 0 0-6557 {}} {258 0 0-6558 {}} {258 0 0-6561 {}} {258 0 0-6564 {}} {258 0 0-6567 {}} {258 0 0-6570 {}} {258 0 0-6573 {}} {258 0 0-6576 {}} {258 0 0-6579 {}} {258 0 0-6582 {}} {258 0 0-6585 {}} {258 0 0-6588 {}} {258 0 0-6590 {}} {256 0 0-6988 {}}} CYCLES {}}
+set a(0-6549) {NAME FRAME:for:select TYPE SELECT PAR 0-6517 XREFS 42346 LOC {1 0.0 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {{259 0 0-6548 {}}} SUCCS {{146 0 0-6550 {}}} CYCLES {}}
+set a(0-6550) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,90) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_read(vin:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-6517 XREFS 42347 LOC {1 0.0 1 0.025595174999999998 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {{146 0 0-6549 {}}} SUCCS {{258 0 0-6552 {}}} CYCLES {}}
+set a(0-6551) {NAME FRAME:for:asn TYPE ASSIGN PAR 0-6517 XREFS 42348 LOC {0 1.0 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {{262 0 0-6971 {}}} SUCCS {{259 0 0-6552 {}} {256 0 0-6971 {}}} CYCLES {}}
+set a(0-6552) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42349 LOC {1 0.0 1 0.025595174999999998 1 0.025595174999999998 1 0.0486557375 1 0.6425464375} PREDS {{258 0 0-6548 {}} {258 0 0-6550 {}} {258 0 0-6540 {}} {259 0 0-6551 {}}} SUCCS {{258 0 0-6608 {}} {258 0 0-6615 {}} {258 0 0-6622 {}} {258 0 0-6646 {}} {258 0 0-6652 {}} {258 0 0-6658 {}} {258 0 0-6876 {}} {258 0 0-6882 {}} {258 0 0-6888 {}} {258 0 0-6905 {}} {258 0 0-6911 {}} {258 0 0-6917 {}} {258 0 0-6940 {}} {258 0 0-6946 {}} {258 0 0-6952 {}} {258 0 0-6971 {}}} CYCLES {}}
+set a(0-6553) {NAME FRAME:for:asn#10 TYPE ASSIGN PAR 0-6517 XREFS 42350 LOC {0 1.0 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {{262 0 0-6971 {}}} SUCCS {{258 0 0-6555 {}} {256 0 0-6971 {}}} CYCLES {}}
+set a(0-6554) {NAME FRAME:for:asn#11 TYPE ASSIGN PAR 0-6517 XREFS 42351 LOC {0 1.0 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {{262 0 0-6972 {}}} SUCCS {{259 0 0-6555 {}} {256 0 0-6972 {}}} CYCLES {}}
+set a(0-6555) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#1 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42352 LOC {1 0.0 1 0.025595174999999998 1 0.025595174999999998 1 0.0486557375 1 0.6425464375} PREDS {{258 0 0-6548 {}} {258 0 0-6553 {}} {259 0 0-6554 {}}} SUCCS {{258 0 0-6607 {}} {258 0 0-6614 {}} {258 0 0-6621 {}} {258 0 0-6645 {}} {258 0 0-6651 {}} {258 0 0-6657 {}} {258 0 0-6875 {}} {258 0 0-6881 {}} {258 0 0-6887 {}} {258 0 0-6904 {}} {258 0 0-6910 {}} {258 0 0-6916 {}} {258 0 0-6939 {}} {258 0 0-6945 {}} {258 0 0-6951 {}} {258 0 0-6972 {}}} CYCLES {}}
+set a(0-6556) {NAME FRAME:for:asn#12 TYPE ASSIGN PAR 0-6517 XREFS 42353 LOC {0 1.0 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {{262 0 0-6972 {}}} SUCCS {{259 0 0-6557 {}} {256 0 0-6972 {}}} CYCLES {}}
+set a(0-6557) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#2 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42354 LOC {1 0.0 1 0.025595174999999998 1 0.025595174999999998 1 0.0486557375 1 0.6425464375} PREDS {{258 0 0-6548 {}} {262 0 0-6973 {}} {259 0 0-6556 {}}} SUCCS {{258 0 0-6606 {}} {258 0 0-6613 {}} {258 0 0-6620 {}} {258 0 0-6644 {}} {258 0 0-6650 {}} {258 0 0-6656 {}} {258 0 0-6874 {}} {258 0 0-6880 {}} {258 0 0-6886 {}} {258 0 0-6903 {}} {258 0 0-6909 {}} {258 0 0-6915 {}} {258 0 0-6938 {}} {258 0 0-6944 {}} {258 0 0-6950 {}} {258 0 0-6973 {}}} CYCLES {}}
+set a(0-6558) {NAME not#12 TYPE NOT PAR 0-6517 XREFS 42355 LOC {1 0.0 1 0.3893105 1 0.3893105 2 0.122260575} PREDS {{258 0 0-6548 {}}} SUCCS {{259 0 0-6559 {}}} CYCLES {}}
+set a(0-6559) {NAME FRAME:for:exs TYPE SIGNEXTEND PAR 0-6517 XREFS 42356 LOC {1 0.0 1 0.3893105 1 0.3893105 2 0.122260575} PREDS {{259 0 0-6558 {}}} SUCCS {{259 0 0-6560 {}}} CYCLES {}}
+set a(0-6560) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(16,2) AREA_SCORE 11.68 QUANTITY 6 NAME FRAME:for:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42357 LOC {1 0.0 1 0.3893105 1 0.3893105 1 0.4057172312638539 2 0.1386673062638539} PREDS {{262 0 0-6974 {}} {259 0 0-6559 {}}} SUCCS {{258 0 0-6612 {}} {258 0 0-6879 {}} {256 0 0-6974 {}}} CYCLES {}}
+set a(0-6561) {NAME not#13 TYPE NOT PAR 0-6517 XREFS 42358 LOC {1 0.0 1 0.283700725 1 0.283700725 2 0.0166508} PREDS {{258 0 0-6548 {}}} SUCCS {{259 0 0-6562 {}}} CYCLES {}}
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+set a(0-6563) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(16,2) AREA_SCORE 11.68 QUANTITY 6 NAME FRAME:for:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42360 LOC {1 0.0 1 0.283700725 1 0.283700725 1 0.3001074562638539 2 0.03305753126385391} PREDS {{262 0 0-6975 {}} {259 0 0-6562 {}}} SUCCS {{258 0 0-6649 {}} {258 0 0-6943 {}} {256 0 0-6975 {}}} CYCLES {}}
+set a(0-6564) {NAME not#14 TYPE NOT PAR 0-6517 XREFS 42361 LOC {1 0.0 1 0.3893105 1 0.3893105 2 0.03837565} PREDS {{258 0 0-6548 {}}} SUCCS {{259 0 0-6565 {}}} CYCLES {}}
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+set a(0-6566) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(16,2) AREA_SCORE 11.68 QUANTITY 6 NAME FRAME:for:and#2 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42363 LOC {1 0.0 1 0.3893105 1 0.3893105 1 0.4057172312638539 2 0.0547823812638539} PREDS {{262 0 0-6976 {}} {259 0 0-6565 {}}} SUCCS {{258 0 0-6619 {}} {258 0 0-6885 {}} {256 0 0-6976 {}}} CYCLES {}}
+set a(0-6567) {NAME not#15 TYPE NOT PAR 0-6517 XREFS 42364 LOC {1 0.0 1 0.283700725 1 0.283700725 1 0.877591425} PREDS {{258 0 0-6548 {}}} SUCCS {{259 0 0-6568 {}}} CYCLES {}}
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+set a(0-6569) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(16,2) AREA_SCORE 11.68 QUANTITY 6 NAME FRAME:for:and#3 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42366 LOC {1 0.0 1 0.283700725 1 0.283700725 1 0.3001074562638539 1 0.8939981562638539} PREDS {{262 0 0-6977 {}} {259 0 0-6568 {}}} SUCCS {{258 0 0-6655 {}} {258 0 0-6949 {}} {256 0 0-6977 {}}} CYCLES {}}
+set a(0-6570) {NAME not#16 TYPE NOT PAR 0-6517 XREFS 42367 LOC {1 0.0 1 0.3893105 1 0.3893105 2 0.03837565} PREDS {{258 0 0-6548 {}}} SUCCS {{259 0 0-6571 {}}} CYCLES {}}
+set a(0-6571) {NAME FRAME:for:exs#24 TYPE SIGNEXTEND PAR 0-6517 XREFS 42368 LOC {1 0.0 1 0.3893105 1 0.3893105 2 0.03837565} PREDS {{259 0 0-6570 {}}} SUCCS {{259 0 0-6572 {}}} CYCLES {}}
+set a(0-6572) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(16,2) AREA_SCORE 11.68 QUANTITY 6 NAME FRAME:for:and#4 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42369 LOC {1 0.0 1 0.3893105 1 0.3893105 1 0.4057172312638539 2 0.0547823812638539} PREDS {{262 0 0-6978 {}} {259 0 0-6571 {}}} SUCCS {{258 0 0-6626 {}} {258 0 0-6891 {}} {256 0 0-6978 {}}} CYCLES {}}
+set a(0-6573) {NAME not#17 TYPE NOT PAR 0-6517 XREFS 42370 LOC {1 0.0 1 0.283700725 1 0.283700725 1 0.877591425} PREDS {{258 0 0-6548 {}}} SUCCS {{259 0 0-6574 {}}} CYCLES {}}
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+set a(0-6575) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(16,2) AREA_SCORE 11.68 QUANTITY 6 NAME FRAME:for:and#5 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42372 LOC {1 0.0 1 0.283700725 1 0.283700725 1 0.3001074562638539 1 0.8939981562638539} PREDS {{262 0 0-6979 {}} {259 0 0-6574 {}}} SUCCS {{258 0 0-6661 {}} {258 0 0-6955 {}} {256 0 0-6979 {}}} CYCLES {}}
+set a(0-6576) {NAME not#18 TYPE NOT PAR 0-6517 XREFS 42373 LOC {1 0.0 1 0.591272 1 0.591272 2 0.48067052499999996} PREDS {{258 0 0-6548 {}}} SUCCS {{259 0 0-6577 {}}} CYCLES {}}
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+set a(0-6578) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 6 NAME FRAME:for:and#6 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42375 LOC {1 0.0 1 0.591272 1 0.591272 1 0.607678731263854 2 0.49707725626385385} PREDS {{262 0 0-6982 {}} {259 0 0-6577 {}}} SUCCS {{258 0 0-6861 {}} {258 0 0-6862 {}} {258 0 0-6863 {}} {258 0 0-6864 {}} {258 0 0-6865 {}} {258 0 0-6870 {}} {258 0 0-6877 {}} {258 0 0-6883 {}} {258 0 0-6889 {}} {258 0 0-6892 {}} {258 0 0-6906 {}} {258 0 0-6912 {}} {258 0 0-6918 {}} {258 0 0-6921 {}} {258 0 0-6923 {}} {258 0 0-6941 {}} {258 0 0-6947 {}} {258 0 0-6953 {}} {258 0 0-6956 {}} {258 0 0-6982 {}}} CYCLES {}}
+set a(0-6579) {NAME not#19 TYPE NOT PAR 0-6517 XREFS 42376 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 2 0.1226526} PREDS {{258 0 0-6548 {}}} SUCCS {{259 0 0-6580 {}}} CYCLES {}}
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+set a(0-6581) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(15,2) AREA_SCORE 10.95 QUANTITY 3 NAME FRAME:for:and#7 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42378 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 1 0.40610925626385386 2 0.13905933126385392} PREDS {{262 0 0-6984 {}} {259 0 0-6580 {}}} SUCCS {{258 0 0-6669 {}} {258 0 0-6908 {}} {258 0 0-6984 {}}} CYCLES {}}
+set a(0-6582) {NAME not#20 TYPE NOT PAR 0-6517 XREFS 42379 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 2 0.038767675} PREDS {{258 0 0-6548 {}}} SUCCS {{259 0 0-6583 {}}} CYCLES {}}
+set a(0-6583) {NAME FRAME:for:exs#28 TYPE SIGNEXTEND PAR 0-6517 XREFS 42380 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 2 0.038767675} PREDS {{259 0 0-6582 {}}} SUCCS {{259 0 0-6584 {}}} CYCLES {}}
+set a(0-6584) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(15,2) AREA_SCORE 10.95 QUANTITY 3 NAME FRAME:for:and#8 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42381 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 1 0.40610925626385386 2 0.055174406263853906} PREDS {{262 0 0-6985 {}} {259 0 0-6583 {}}} SUCCS {{258 0 0-6673 {}} {258 0 0-6914 {}} {258 0 0-6985 {}}} CYCLES {}}
+set a(0-6585) {NAME not#21 TYPE NOT PAR 0-6517 XREFS 42382 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 2 0.038767675} PREDS {{258 0 0-6548 {}}} SUCCS {{259 0 0-6586 {}}} CYCLES {}}
+set a(0-6586) {NAME FRAME:for:exs#29 TYPE SIGNEXTEND PAR 0-6517 XREFS 42383 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 2 0.038767675} PREDS {{259 0 0-6585 {}}} SUCCS {{259 0 0-6587 {}}} CYCLES {}}
+set a(0-6587) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(15,2) AREA_SCORE 10.95 QUANTITY 3 NAME FRAME:for:and#9 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42384 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 1 0.40610925626385386 2 0.055174406263853906} PREDS {{262 0 0-6986 {}} {259 0 0-6586 {}}} SUCCS {{258 0 0-6677 {}} {258 0 0-6920 {}} {258 0 0-6986 {}}} CYCLES {}}
+set a(0-6588) {NAME not#22 TYPE NOT PAR 0-6517 XREFS 42385 LOC {1 0.0 1 0.0 1 0.0 2 0.550304075} PREDS {{258 0 0-6548 {}}} SUCCS {{259 0 0-6589 {}}} CYCLES {}}
+set a(0-6589) {NAME FRAME:for:and#10 TYPE AND PAR 0-6517 XREFS 42386 LOC {1 0.0 1 0.0 1 0.0 2 0.550304075} PREDS {{262 0 0-6987 {}} {259 0 0-6588 {}}} SUCCS {{258 0 0-6965 {}} {258 0 0-6966 {}} {256 0 0-6987 {}}} CYCLES {}}
+set a(0-6590) {NAME not#1 TYPE NOT PAR 0-6517 XREFS 42387 LOC {1 0.0 1 0.0 1 0.0 1 0.642546475} PREDS {{258 0 0-6548 {}}} SUCCS {{259 0 0-6591 {}}} CYCLES {}}
+set a(0-6591) {NAME FRAME:for:and#12 TYPE AND PAR 0-6517 XREFS 42388 LOC {1 0.0 1 0.0 1 0.0 1 0.642546475} PREDS {{262 0 0-6989 {}} {259 0 0-6590 {}}} SUCCS {{259 0 0-6592 {}} {258 0 0-6966 {}} {258 0 0-6967 {}} {258 0 0-6974 {}} {258 0 0-6975 {}} {258 0 0-6976 {}} {258 0 0-6977 {}} {258 0 0-6978 {}} {258 0 0-6979 {}} {258 0 0-6980 {}} {258 0 0-6982 {}} {258 0 0-6983 {}} {258 0 0-6984 {}} {258 0 0-6985 {}} {258 0 0-6986 {}} {258 0 0-6989 {}}} CYCLES {}}
+set a(0-6592) {NAME FRAME:for:select#1 TYPE SELECT PAR 0-6517 XREFS 42389 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{259 0 0-6591 {}}} SUCCS {{146 0 0-6593 {}} {146 0 0-6594 {}} {146 0 0-6595 {}} {146 0 0-6596 {}} {146 0 0-6597 {}} {146 0 0-6598 {}} {146 0 0-6599 {}} {146 0 0-6600 {}} {146 0 0-6601 {}} {146 0 0-6602 {}} {146 0 0-6603 {}} {146 0 0-6604 {}} {146 0 0-6605 {}} {146 0 0-6606 {}} {146 0 0-6607 {}} {146 0 0-6608 {}} {146 0 0-6609 {}} {146 0 0-6610 {}} {146 0 0-6611 {}} {146 0 0-6612 {}} {146 0 0-6613 {}} {146 0 0-6614 {}} {146 0 0-6615 {}} {146 0 0-6616 {}} {146 0 0-6617 {}} {146 0 0-6618 {}} {146 0 0-6619 {}} {146 0 0-6620 {}} {146 0 0-6621 {}} {146 0 0-6622 {}} {146 0 0-6623 {}} {146 0 0-6624 {}} {146 0 0-6625 {}} {146 0 0-6626 {}} {146 0 0-6627 {}} {146 0 0-6628 {}} {146 0 0-6629 {}} {146 0 0-6630 {}} {146 0 0-6631 {}} {146 0 0-6632 {}} {146 0 0-6633 {}} {146 0 0-6634 {}} {146 0 0-6635 {}} {146 0 0-6636 {}} {146 0 0-6637 {}} {146 0 0-6638 {}} {146 0 0-6639 {}} {146 0 0-6640 {}} {146 0 0-6641 {}} {146 0 0-6642 {}} {146 0 0-6643 {}} {146 0 0-6644 {}} {146 0 0-6645 {}} {146 0 0-6646 {}} {146 0 0-6647 {}} {146 0 0-6648 {}} {146 0 0-6649 {}} {146 0 0-6650 {}} {146 0 0-6651 {}} {146 0 0-6652 {}} {146 0 0-6653 {}} {146 0 0-6654 {}} {146 0 0-6655 {}} {146 0 0-6656 {}} {146 0 0-6657 {}} {146 0 0-6658 {}} {146 0 0-6659 {}} {146 0 0-6660 {}} {146 0 0-6661 {}} {146 0 0-6662 {}} {146 0 0-6663 {}} {146 0 0-6664 {}} {146 0 0-6665 {}} {146 0 0-6666 {}} {146 0 0-6667 {}} {130 0 0-6668 {}} {146 0 0-6861 {}} {146 0 0-6862 {}} {146 0 0-6863 {}} {146 0 0-6864 {}} {146 0 0-6865 {}} {146 0 0-6866 {}} {146 0 0-6867 {}} {146 0 0-6868 {}} {146 0 0-6869 {}} {146 0 0-6870 {}} {146 0 0-6871 {}} {146 0 0-6872 {}} {146 0 0-6873 {}} {146 0 0-6874 {}} {146 0 0-6875 {}} {146 0 0-6876 {}} {146 0 0-6877 {}} {146 0 0-6878 {}} {146 0 0-6879 {}} {146 0 0-6880 {}} {146 0 0-6881 {}} {146 0 0-6882 {}} {146 0 0-6883 {}} {146 0 0-6884 {}} {146 0 0-6885 {}} {146 0 0-6886 {}} {146 0 0-6887 {}} {146 0 0-6888 {}} {146 0 0-6889 {}} {146 0 0-6890 {}} {146 0 0-6891 {}} {146 0 0-6892 {}} {146 0 0-6893 {}} {146 0 0-6894 {}} {146 0 0-6895 {}} {146 0 0-6896 {}} {146 0 0-6897 {}} {146 0 0-6898 {}} {146 0 0-6899 {}} {146 0 0-6900 {}} {146 0 0-6901 {}} {146 0 0-6902 {}} {146 0 0-6903 {}} {146 0 0-6904 {}} {146 0 0-6905 {}} {146 0 0-6906 {}} {146 0 0-6907 {}} {146 0 0-6908 {}} {146 0 0-6909 {}} {146 0 0-6910 {}} {146 0 0-6911 {}} {146 0 0-6912 {}} {146 0 0-6913 {}} {146 0 0-6914 {}} {146 0 0-6915 {}} {146 0 0-6916 {}} {146 0 0-6917 {}} {146 0 0-6918 {}} {146 0 0-6919 {}} {146 0 0-6920 {}} {146 0 0-6921 {}} {146 0 0-6922 {}} {146 0 0-6923 {}} {146 0 0-6924 {}} {146 0 0-6925 {}} {146 0 0-6926 {}} {146 0 0-6927 {}} {146 0 0-6928 {}} {146 0 0-6929 {}} {146 0 0-6930 {}} {146 0 0-6931 {}} {146 0 0-6932 {}} {146 0 0-6933 {}} {146 0 0-6934 {}} {146 0 0-6935 {}} {146 0 0-6936 {}} {146 0 0-6937 {}} {146 0 0-6938 {}} {146 0 0-6939 {}} {146 0 0-6940 {}} {146 0 0-6941 {}} {146 0 0-6942 {}} {146 0 0-6943 {}} {146 0 0-6944 {}} {146 0 0-6945 {}} {146 0 0-6946 {}} {146 0 0-6947 {}} {146 0 0-6948 {}} {146 0 0-6949 {}} {146 0 0-6950 {}} {146 0 0-6951 {}} {146 0 0-6952 {}} {146 0 0-6953 {}} {146 0 0-6954 {}} {146 0 0-6955 {}} {146 0 0-6956 {}} {146 0 0-6957 {}} {146 0 0-6958 {}} {146 0 0-6959 {}} {146 0 0-6960 {}} {146 0 0-6961 {}} {146 0 0-6962 {}} {146 0 0-6963 {}} {146 0 0-6964 {}}} CYCLES {}}
+set a(0-6593) {NAME slc(i#7.lpi#1) TYPE READSLICE PAR 0-6517 XREFS 42390 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}}} SUCCS {{258 0 0-6601 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6594) {NAME slc(i#7.lpi#1)#1 TYPE READSLICE PAR 0-6517 XREFS 42391 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}}} SUCCS {{258 0 0-6598 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6595) {NAME slc(i#7.lpi#1)#2 TYPE READSLICE PAR 0-6517 XREFS 42392 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}}} SUCCS {{258 0 0-6604 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6596) {NAME slc(i#7.lpi#1)#3 TYPE READSLICE PAR 0-6517 XREFS 42393 LOC {1 0.0 1 0.048655775 1 0.048655775 2 1.0} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}}} SUCCS {{256 0 0-6983 {}}} CYCLES {}}
+set a(0-6597) {NAME FRAME:for#1:slc(i#7.lpi#1) TYPE READSLICE PAR 0-6517 XREFS 42394 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}}} SUCCS {{258 0 0-6599 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6598) {NAME FRAME:for#1:not#1 TYPE NOT PAR 0-6517 XREFS 42395 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6592 {}} {258 0 0-6594 {}}} SUCCS {{259 0 0-6599 {}}} CYCLES {}}
+set a(0-6599) {NAME FRAME:for#1:nand TYPE NAND PAR 0-6517 XREFS 42396 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6592 {}} {258 0 0-6597 {}} {259 0 0-6598 {}}} SUCCS {{258 0 0-6605 {}}} CYCLES {}}
+set a(0-6600) {NAME FRAME:for#1:slc(i#7.lpi#1)#1 TYPE READSLICE PAR 0-6517 XREFS 42397 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}}} SUCCS {{259 0 0-6601 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6601) {NAME FRAME:for#1:nor TYPE NOR PAR 0-6517 XREFS 42398 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6592 {}} {258 0 0-6593 {}} {259 0 0-6600 {}}} SUCCS {{258 0 0-6605 {}}} CYCLES {}}
+set a(0-6602) {NAME FRAME:for#1:slc(i#7.lpi#1)#2 TYPE READSLICE PAR 0-6517 XREFS 42399 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}}} SUCCS {{259 0 0-6603 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6603) {NAME FRAME:for#1:not#2 TYPE NOT PAR 0-6517 XREFS 42400 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6592 {}} {259 0 0-6602 {}}} SUCCS {{259 0 0-6604 {}}} CYCLES {}}
+set a(0-6604) {NAME FRAME:for#1:and TYPE AND PAR 0-6517 XREFS 42401 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6592 {}} {258 0 0-6595 {}} {259 0 0-6603 {}}} SUCCS {{259 0 0-6605 {}}} CYCLES {}}
+set a(0-6605) {NAME FRAME:for#1:or TYPE OR PAR 0-6517 XREFS 42402 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6592 {}} {258 0 0-6601 {}} {258 0 0-6599 {}} {259 0 0-6604 {}}} SUCCS {{258 0 0-6610 {}} {258 0 0-6617 {}} {258 0 0-6624 {}}} CYCLES {}}
+set a(0-6606) {NAME {regs.operator[]#27:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42403 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6609 {}}} CYCLES {}}
+set a(0-6607) {NAME {regs.operator[]#27:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42404 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6609 {}}} CYCLES {}}
+set a(0-6608) {NAME {regs.operator[]#27:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42405 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6609 {}}} CYCLES {}}
+set a(0-6609) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#27:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42406 LOC {1 0.0230606 1 0.15426555 1 0.15426555 1 0.2127933 1 0.807076025} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}} {258 0 0-6607 {}} {258 0 0-6606 {}} {259 0 0-6608 {}}} SUCCS {{258 0 0-6611 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6610) {NAME FRAME:for#1:conc#5 TYPE CONCATENATE PAR 0-6517 XREFS 42407 LOC {1 0.0 1 0.21279335 1 0.21279335 1 0.807076075} PREDS {{146 0 0-6592 {}} {258 0 0-6605 {}}} SUCCS {{259 0 0-6611 {}}} CYCLES {}}
+set a(0-6611) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for#1:mul TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42408 LOC {1 0.08158839999999999 1 0.21279335 1 0.21279335 1 0.4057172125 1 0.9999999374999999} PREDS {{146 0 0-6592 {}} {258 0 0-6609 {}} {259 0 0-6610 {}}} SUCCS {{259 0 0-6612 {}}} CYCLES {}}
+set a(0-6612) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for#1:acc#1 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6517 XREFS 42409 LOC {1 0.274512325 1 0.405717275 1 0.405717275 1 0.5117190163378799 2 0.24466909133787984} PREDS {{146 0 0-6592 {}} {258 0 0-6560 {}} {259 0 0-6611 {}}} SUCCS {{258 0 0-6671 {}} {258 0 0-6974 {}}} CYCLES {}}
+set a(0-6613) {NAME {regs.operator[]#28:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42410 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6616 {}}} CYCLES {}}
+set a(0-6614) {NAME {regs.operator[]#28:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42411 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6616 {}}} CYCLES {}}
+set a(0-6615) {NAME {regs.operator[]#28:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42412 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6616 {}}} CYCLES {}}
+set a(0-6616) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#28:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42413 LOC {1 0.0230606 1 0.15426555 1 0.15426555 1 0.2127933 1 0.807076025} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}} {258 0 0-6614 {}} {258 0 0-6613 {}} {259 0 0-6615 {}}} SUCCS {{258 0 0-6618 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6617) {NAME FRAME:for#1:conc#6 TYPE CONCATENATE PAR 0-6517 XREFS 42414 LOC {1 0.0 1 0.21279335 1 0.21279335 1 0.807076075} PREDS {{146 0 0-6592 {}} {258 0 0-6605 {}}} SUCCS {{259 0 0-6618 {}}} CYCLES {}}
+set a(0-6618) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for#1:mul#1 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42415 LOC {1 0.08158839999999999 1 0.21279335 1 0.21279335 1 0.4057172125 1 0.9999999374999999} PREDS {{146 0 0-6592 {}} {258 0 0-6616 {}} {259 0 0-6617 {}}} SUCCS {{259 0 0-6619 {}}} CYCLES {}}
+set a(0-6619) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for#1:acc#2 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6517 XREFS 42416 LOC {1 0.274512325 1 0.405717275 1 0.405717275 1 0.5117190163378799 2 0.16078416633787984} PREDS {{146 0 0-6592 {}} {258 0 0-6566 {}} {259 0 0-6618 {}}} SUCCS {{258 0 0-6675 {}} {258 0 0-6976 {}}} CYCLES {}}
+set a(0-6620) {NAME {regs.operator[]#29:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42417 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6623 {}}} CYCLES {}}
+set a(0-6621) {NAME {regs.operator[]#29:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42418 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6623 {}}} CYCLES {}}
+set a(0-6622) {NAME {regs.operator[]#29:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42419 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6623 {}}} CYCLES {}}
+set a(0-6623) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#29:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42420 LOC {1 0.0230606 1 0.15426555 1 0.15426555 1 0.2127933 1 0.807076025} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}} {258 0 0-6621 {}} {258 0 0-6620 {}} {259 0 0-6622 {}}} SUCCS {{258 0 0-6625 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6624) {NAME FRAME:for#1:conc#7 TYPE CONCATENATE PAR 0-6517 XREFS 42421 LOC {1 0.0 1 0.21279335 1 0.21279335 1 0.807076075} PREDS {{146 0 0-6592 {}} {258 0 0-6605 {}}} SUCCS {{259 0 0-6625 {}}} CYCLES {}}
+set a(0-6625) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for#1:mul#2 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42422 LOC {1 0.08158839999999999 1 0.21279335 1 0.21279335 1 0.4057172125 1 0.9999999374999999} PREDS {{146 0 0-6592 {}} {258 0 0-6623 {}} {259 0 0-6624 {}}} SUCCS {{259 0 0-6626 {}}} CYCLES {}}
+set a(0-6626) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for#1:acc#3 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6517 XREFS 42423 LOC {1 0.274512325 1 0.405717275 1 0.405717275 1 0.5117190163378799 2 0.16078416633787984} PREDS {{146 0 0-6592 {}} {258 0 0-6572 {}} {259 0 0-6625 {}}} SUCCS {{258 0 0-6679 {}} {258 0 0-6978 {}}} CYCLES {}}
+set a(0-6627) {NAME i:slc(i#4)#1 TYPE READSLICE PAR 0-6517 XREFS 42424 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}}} SUCCS {{259 0 0-6628 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6628) {NAME FRAME:for#1:not#4 TYPE NOT PAR 0-6517 XREFS 42425 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6592 {}} {259 0 0-6627 {}}} SUCCS {{258 0 0-6630 {}}} CYCLES {}}
+set a(0-6629) {NAME i:slc(i#4)#2 TYPE READSLICE PAR 0-6517 XREFS 42426 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}}} SUCCS {{259 0 0-6630 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6630) {NAME FRAME:for#1:conc TYPE CONCATENATE PAR 0-6517 XREFS 42427 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6592 {}} {258 0 0-6628 {}} {259 0 0-6629 {}}} SUCCS {{259 0 0-6631 {}} {258 0 0-6632 {}} {258 0 0-6633 {}} {258 0 0-6634 {}} {258 0 0-6635 {}} {258 0 0-6639 {}}} CYCLES {}}
+set a(0-6631) {NAME slc(FRAME:for#1:conc.tmp) TYPE READSLICE PAR 0-6517 XREFS 42428 LOC {1 0.0 1 0.048655775 1 0.048655775 3 1.0} PREDS {{146 0 0-6592 {}} {259 0 0-6630 {}}} SUCCS {} CYCLES {}}
+set a(0-6632) {NAME slc(FRAME:for#1:conc.tmp)#1 TYPE READSLICE PAR 0-6517 XREFS 42429 LOC {1 0.0 1 0.048655775 1 0.048655775 3 1.0} PREDS {{146 0 0-6592 {}} {258 0 0-6630 {}}} SUCCS {} CYCLES {}}
+set a(0-6633) {NAME slc(FRAME:for#1:conc.tmp)#2 TYPE READSLICE PAR 0-6517 XREFS 42430 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.6843317999999999} PREDS {{146 0 0-6592 {}} {258 0 0-6630 {}}} SUCCS {{258 0 0-6641 {}}} CYCLES {}}
+set a(0-6634) {NAME slc(FRAME:for#1:conc.tmp)#3 TYPE READSLICE PAR 0-6517 XREFS 42431 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6592 {}} {258 0 0-6630 {}}} SUCCS {{258 0 0-6636 {}}} CYCLES {}}
+set a(0-6635) {NAME FRAME:for#1:slc(FRAME:for#1:conc.tmp) TYPE READSLICE PAR 0-6517 XREFS 42432 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6592 {}} {258 0 0-6630 {}}} SUCCS {{259 0 0-6636 {}}} CYCLES {}}
+set a(0-6636) {NAME FRAME:for#1:nand#1 TYPE NAND PAR 0-6517 XREFS 42433 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6592 {}} {258 0 0-6634 {}} {259 0 0-6635 {}}} SUCCS {{259 0 0-6637 {}}} CYCLES {}}
+set a(0-6637) {NAME FRAME:for#1:exs TYPE SIGNEXTEND PAR 0-6517 XREFS 42434 LOC {1 0.0 1 0.074034325 1 0.074034325 1 0.667925025} PREDS {{146 0 0-6592 {}} {259 0 0-6636 {}}} SUCCS {{259 0 0-6638 {}}} CYCLES {}}
+set a(0-6638) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 6 NAME FRAME:for#1:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42435 LOC {1 0.0 1 0.074034325 1 0.074034325 1 0.0904410562638539 1 0.6843317562638539} PREDS {{146 0 0-6592 {}} {259 0 0-6637 {}}} SUCCS {{258 0 0-6643 {}}} CYCLES {}}
+set a(0-6639) {NAME FRAME:for#1:slc(FRAME:for#1:conc.tmp)#1 TYPE READSLICE PAR 0-6517 XREFS 42436 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.6843317999999999} PREDS {{146 0 0-6592 {}} {258 0 0-6630 {}}} SUCCS {{259 0 0-6640 {}}} CYCLES {}}
+set a(0-6640) {NAME FRAME:for#1:not#3 TYPE NOT PAR 0-6517 XREFS 42437 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.6843317999999999} PREDS {{146 0 0-6592 {}} {259 0 0-6639 {}}} SUCCS {{259 0 0-6641 {}}} CYCLES {}}
+set a(0-6641) {NAME FRAME:for#1:and#2 TYPE AND PAR 0-6517 XREFS 42438 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.6843317999999999} PREDS {{146 0 0-6592 {}} {258 0 0-6633 {}} {259 0 0-6640 {}}} SUCCS {{259 0 0-6642 {}}} CYCLES {}}
+set a(0-6642) {NAME FRAME:for#1:exs#19 TYPE SIGNEXTEND PAR 0-6517 XREFS 42439 LOC {1 0.0 1 0.0904411 1 0.0904411 1 0.6843317999999999} PREDS {{146 0 0-6592 {}} {259 0 0-6641 {}}} SUCCS {{259 0 0-6643 {}}} CYCLES {}}
+set a(0-6643) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(2,2) AREA_SCORE 1.46 QUANTITY 4 NAME FRAME:for#1:or#1 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-6517 XREFS 42440 LOC {1 0.016406775 1 0.0904411 1 0.0904411 1 0.10718353110773884 1 0.7010742311077388} PREDS {{146 0 0-6592 {}} {258 0 0-6638 {}} {259 0 0-6642 {}}} SUCCS {{258 0 0-6648 {}} {258 0 0-6654 {}} {258 0 0-6660 {}}} CYCLES {}}
+set a(0-6644) {NAME {regs.operator[]#33:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42441 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6647 {}}} CYCLES {}}
+set a(0-6645) {NAME {regs.operator[]#33:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42442 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6647 {}}} CYCLES {}}
+set a(0-6646) {NAME {regs.operator[]#33:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42443 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6647 {}}} CYCLES {}}
+set a(0-6647) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#33:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42444 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.107183525 1 0.807076025} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}} {258 0 0-6645 {}} {258 0 0-6644 {}} {259 0 0-6646 {}}} SUCCS {{259 0 0-6648 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6648) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for#1:mul#6 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42445 LOC {1 0.08158839999999999 1 0.10718357499999999 1 0.10718357499999999 1 0.30010743749999996 1 0.9999999374999999} PREDS {{146 0 0-6592 {}} {258 0 0-6643 {}} {259 0 0-6647 {}}} SUCCS {{259 0 0-6649 {}}} CYCLES {}}
+set a(0-6649) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for#1:acc#10 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6517 XREFS 42446 LOC {1 0.274512325 1 0.30010749999999997 1 0.30010749999999997 1 0.40610924133787984 2 0.13905931633787985} PREDS {{146 0 0-6592 {}} {258 0 0-6563 {}} {259 0 0-6648 {}}} SUCCS {{258 0 0-6670 {}} {258 0 0-6975 {}}} CYCLES {}}
+set a(0-6650) {NAME {regs.operator[]#34:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42447 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6653 {}}} CYCLES {}}
+set a(0-6651) {NAME {regs.operator[]#34:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42448 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6653 {}}} CYCLES {}}
+set a(0-6652) {NAME {regs.operator[]#34:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42449 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6653 {}}} CYCLES {}}
+set a(0-6653) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#34:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42450 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.107183525 1 0.7010742249999999} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}} {258 0 0-6651 {}} {258 0 0-6650 {}} {259 0 0-6652 {}}} SUCCS {{259 0 0-6654 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6654) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for#1:mul#7 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42451 LOC {1 0.08158839999999999 1 0.10718357499999999 1 0.10718357499999999 1 0.30010743749999996 1 0.8939981374999999} PREDS {{146 0 0-6592 {}} {258 0 0-6643 {}} {259 0 0-6653 {}}} SUCCS {{259 0 0-6655 {}}} CYCLES {}}
+set a(0-6655) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for#1:acc#12 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6517 XREFS 42452 LOC {1 0.274512325 1 0.30010749999999997 1 0.30010749999999997 1 0.40610924133787984 1 0.9999999413378798} PREDS {{146 0 0-6592 {}} {258 0 0-6569 {}} {259 0 0-6654 {}}} SUCCS {{258 0 0-6674 {}} {258 0 0-6977 {}}} CYCLES {}}
+set a(0-6656) {NAME {regs.operator[]#35:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42453 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6659 {}}} CYCLES {}}
+set a(0-6657) {NAME {regs.operator[]#35:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42454 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6659 {}}} CYCLES {}}
+set a(0-6658) {NAME {regs.operator[]#35:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42455 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6659 {}}} CYCLES {}}
+set a(0-6659) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#35:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42456 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.107183525 1 0.7010742249999999} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}} {258 0 0-6657 {}} {258 0 0-6656 {}} {259 0 0-6658 {}}} SUCCS {{259 0 0-6660 {}} {256 0 0-6983 {}}} CYCLES {}}
+set a(0-6660) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for#1:mul#8 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42457 LOC {1 0.08158839999999999 1 0.10718357499999999 1 0.10718357499999999 1 0.30010743749999996 1 0.8939981374999999} PREDS {{146 0 0-6592 {}} {258 0 0-6643 {}} {259 0 0-6659 {}}} SUCCS {{259 0 0-6661 {}}} CYCLES {}}
+set a(0-6661) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for#1:acc#14 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6517 XREFS 42458 LOC {1 0.274512325 1 0.30010749999999997 1 0.30010749999999997 1 0.40610924133787984 1 0.9999999413378798} PREDS {{146 0 0-6592 {}} {258 0 0-6575 {}} {259 0 0-6660 {}}} SUCCS {{258 0 0-6678 {}} {258 0 0-6979 {}}} CYCLES {}}
+set a(0-6662) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,2) AREA_SCORE 3.31 QUANTITY 2 NAME FRAME:for#1:acc#16 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-6517 XREFS 42459 LOC {1 0.0 1 0.317770075 1 0.317770075 1 0.35855308508947525 1 0.9999999600894752} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}}} SUCCS {{259 0 0-6663 {}} {258 0 0-6983 {}}} CYCLES {}}
+set a(0-6663) {NAME FRAME:for#1:asn#2 TYPE ASSIGN PAR 0-6517 XREFS 42460 LOC {1 0.04078305 1 0.358553125 1 0.358553125 2 0.007618275} PREDS {{146 0 0-6592 {}} {259 0 0-6662 {}}} SUCCS {{259 0 0-6664 {}}} CYCLES {}}
+set a(0-6664) {NAME FRAME:for#1:conc#11 TYPE CONCATENATE PAR 0-6517 XREFS 42461 LOC {1 0.04078305 1 0.358553125 1 0.358553125 2 0.007618275} PREDS {{146 0 0-6592 {}} {259 0 0-6663 {}}} SUCCS {{259 0 0-6665 {}}} CYCLES {}}
+set a(0-6665) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,3) AREA_SCORE 4.30 QUANTITY 2 NAME FRAME:for#1:acc TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42462 LOC {1 0.04078305 1 0.358553125 1 0.358553125 1 0.40610925207082715 2 0.055174402070827175} PREDS {{146 0 0-6592 {}} {259 0 0-6664 {}}} SUCCS {{259 0 0-6666 {}}} CYCLES {}}
+set a(0-6666) {NAME FRAME:for#1:slc TYPE READSLICE PAR 0-6517 XREFS 42463 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.05517445} PREDS {{146 0 0-6592 {}} {259 0 0-6665 {}}} SUCCS {{259 0 0-6667 {}}} CYCLES {}}
+set a(0-6667) {NAME FRAME:for#1:not TYPE NOT PAR 0-6517 XREFS 42464 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.05517445} PREDS {{146 0 0-6592 {}} {259 0 0-6666 {}}} SUCCS {{259 0 0-6668 {}} {258 0 0-6965 {}} {258 0 0-6967 {}} {258 0 0-6980 {}}} CYCLES {}}
+set a(0-6668) {NAME FRAME:for#1:select TYPE SELECT PAR 0-6517 XREFS 42465 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.05517445} PREDS {{130 0 0-6592 {}} {259 0 0-6667 {}}} SUCCS {{146 0 0-6669 {}} {146 0 0-6670 {}} {146 0 0-6671 {}} {146 0 0-6672 {}} {146 0 0-6673 {}} {146 0 0-6674 {}} {146 0 0-6675 {}} {146 0 0-6676 {}} {146 0 0-6677 {}} {146 0 0-6678 {}} {146 0 0-6679 {}} {146 0 0-6680 {}} {146 0 0-6681 {}} {146 0 0-6682 {}} {146 0 0-6683 {}} {146 0 0-6684 {}} {146 0 0-6685 {}} {146 0 0-6686 {}} {146 0 0-6687 {}} {146 0 0-6688 {}} {146 0 0-6689 {}} {146 0 0-6690 {}} {146 0 0-6691 {}} {146 0 0-6692 {}} {146 0 0-6693 {}} {146 0 0-6694 {}} {146 0 0-6695 {}} {146 0 0-6696 {}} {146 0 0-6697 {}} {146 0 0-6698 {}} {146 0 0-6699 {}} {146 0 0-6700 {}} {146 0 0-6701 {}} {146 0 0-6702 {}} {146 0 0-6703 {}} {146 0 0-6704 {}} {146 0 0-6705 {}} {146 0 0-6706 {}} {146 0 0-6707 {}} {146 0 0-6708 {}} {146 0 0-6709 {}} {146 0 0-6710 {}} {146 0 0-6711 {}} {146 0 0-6712 {}} {146 0 0-6713 {}} {146 0 0-6714 {}} {146 0 0-6715 {}} {146 0 0-6716 {}} {146 0 0-6717 {}} {146 0 0-6718 {}} {146 0 0-6719 {}} {146 0 0-6720 {}} {146 0 0-6721 {}} {146 0 0-6722 {}} {146 0 0-6723 {}} {146 0 0-6724 {}} {146 0 0-6725 {}} {146 0 0-6726 {}} {146 0 0-6727 {}} {146 0 0-6728 {}} {146 0 0-6729 {}} {146 0 0-6730 {}} {146 0 0-6731 {}} {146 0 0-6732 {}} {146 0 0-6733 {}} {146 0 0-6734 {}} {146 0 0-6735 {}} {146 0 0-6736 {}} {146 0 0-6737 {}} {146 0 0-6738 {}} {146 0 0-6739 {}} {146 0 0-6740 {}} {146 0 0-6741 {}} {146 0 0-6742 {}} {146 0 0-6743 {}} {146 0 0-6744 {}} {146 0 0-6745 {}} {146 0 0-6746 {}} {146 0 0-6747 {}} {146 0 0-6748 {}} {146 0 0-6749 {}} {146 0 0-6750 {}} {146 0 0-6751 {}} {146 0 0-6752 {}} {146 0 0-6753 {}} {146 0 0-6754 {}} {146 0 0-6755 {}} {146 0 0-6756 {}} {146 0 0-6757 {}} {146 0 0-6758 {}} {146 0 0-6759 {}} {146 0 0-6760 {}} {146 0 0-6761 {}} {146 0 0-6762 {}} {146 0 0-6763 {}} {146 0 0-6764 {}} {146 0 0-6765 {}} {146 0 0-6766 {}} {146 0 0-6767 {}} {146 0 0-6768 {}} {146 0 0-6769 {}} {146 0 0-6770 {}} {146 0 0-6771 {}} {146 0 0-6772 {}} {146 0 0-6773 {}} {146 0 0-6774 {}} {146 0 0-6775 {}} {146 0 0-6776 {}} {146 0 0-6777 {}} {146 0 0-6778 {}} {146 0 0-6779 {}} {146 0 0-6780 {}} {146 0 0-6781 {}} {146 0 0-6782 {}} {146 0 0-6783 {}} {146 0 0-6784 {}} {146 0 0-6785 {}} {146 0 0-6786 {}} {146 0 0-6787 {}} {146 0 0-6788 {}} {146 0 0-6789 {}} {146 0 0-6790 {}} {146 0 0-6791 {}} {146 0 0-6792 {}} {146 0 0-6793 {}} {146 0 0-6794 {}} {146 0 0-6795 {}} {146 0 0-6796 {}} {146 0 0-6797 {}} {146 0 0-6798 {}} {146 0 0-6799 {}} {146 0 0-6800 {}} {146 0 0-6801 {}} {146 0 0-6802 {}} {146 0 0-6803 {}} {146 0 0-6804 {}} {146 0 0-6805 {}} {146 0 0-6806 {}} {146 0 0-6807 {}} {146 0 0-6808 {}} {146 0 0-6809 {}} {146 0 0-6810 {}} {146 0 0-6811 {}} {146 0 0-6812 {}} {146 0 0-6813 {}} {146 0 0-6814 {}} {146 0 0-6815 {}} {146 0 0-6816 {}} {146 0 0-6817 {}} {146 0 0-6818 {}} {146 0 0-6819 {}} {146 0 0-6820 {}} {146 0 0-6821 {}} {146 0 0-6822 {}} {146 0 0-6823 {}} {146 0 0-6824 {}} {146 0 0-6825 {}} {146 0 0-6826 {}} {146 0 0-6827 {}} {146 0 0-6828 {}} {146 0 0-6829 {}} {146 0 0-6830 {}} {146 0 0-6831 {}} {146 0 0-6832 {}} {146 0 0-6833 {}} {146 0 0-6834 {}} {146 0 0-6835 {}} {146 0 0-6836 {}} {146 0 0-6837 {}} {146 0 0-6838 {}} {146 0 0-6839 {}} {146 0 0-6840 {}} {146 0 0-6841 {}} {146 0 0-6842 {}} {146 0 0-6843 {}} {146 0 0-6844 {}} {146 0 0-6845 {}} {146 0 0-6846 {}} {146 0 0-6847 {}} {146 0 0-6848 {}} {146 0 0-6849 {}} {146 0 0-6850 {}} {146 0 0-6851 {}} {146 0 0-6852 {}} {146 0 0-6853 {}} {146 0 0-6854 {}} {130 0 0-6855 {}} {146 0 0-6856 {}} {146 0 0-6857 {}} {146 0 0-6858 {}} {146 0 0-6859 {}} {146 0 0-6860 {}}} CYCLES {}}
+set a(0-6669) {NAME r:conc TYPE CONCATENATE PAR 0-6517 XREFS 42466 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.13905937499999999} PREDS {{146 0 0-6668 {}} {258 0 0-6581 {}}} SUCCS {{259 0 0-6670 {}}} CYCLES {}}
+set a(0-6670) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 6 NAME ACC2:acc TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-6517 XREFS 42467 LOC {1 0.380514125 1 0.4061093 1 0.4061093 1 0.511719030357901 2 0.24466910535790098} PREDS {{146 0 0-6668 {}} {258 0 0-6649 {}} {259 0 0-6669 {}}} SUCCS {{259 0 0-6671 {}}} CYCLES {}}
+set a(0-6671) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 6 NAME ACC2-3:acc#1 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-6517 XREFS 42468 LOC {1 0.4861239 1 0.511719075 1 0.511719075 1 0.617328805357901 2 0.350278880357901} PREDS {{146 0 0-6668 {}} {258 0 0-6612 {}} {259 0 0-6670 {}}} SUCCS {{259 0 0-6672 {}}} CYCLES {}}
+set a(0-6672) {NAME ACC2:slc TYPE READSLICE PAR 0-6517 XREFS 42469 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6668 {}} {259 0 0-6671 {}}} SUCCS {{258 0 0-6681 {}} {258 0 0-6682 {}} {258 0 0-6685 {}} {258 0 0-6687 {}} {258 0 0-6690 {}} {258 0 0-6693 {}} {258 0 0-6694 {}} {258 0 0-6809 {}} {258 0 0-6811 {}} {258 0 0-6812 {}} {258 0 0-6814 {}} {258 0 0-6817 {}} {258 0 0-6819 {}} {258 0 0-6836 {}}} CYCLES {}}
+set a(0-6673) {NAME g:conc TYPE CONCATENATE PAR 0-6517 XREFS 42470 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.05517445} PREDS {{146 0 0-6668 {}} {258 0 0-6584 {}}} SUCCS {{259 0 0-6674 {}}} CYCLES {}}
+set a(0-6674) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 6 NAME ACC2:acc#5 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-6517 XREFS 42471 LOC {1 0.380514125 1 0.4061093 1 0.4061093 1 0.511719030357901 2 0.16078418035790099} PREDS {{146 0 0-6668 {}} {258 0 0-6655 {}} {259 0 0-6673 {}}} SUCCS {{259 0 0-6675 {}}} CYCLES {}}
+set a(0-6675) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 6 NAME ACC2-3:acc#2 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-6517 XREFS 42472 LOC {1 0.4861239 1 0.511719075 1 0.511719075 1 0.617328805357901 2 0.266393955357901} PREDS {{146 0 0-6668 {}} {258 0 0-6619 {}} {259 0 0-6674 {}}} SUCCS {{259 0 0-6676 {}}} CYCLES {}}
+set a(0-6676) {NAME ACC2:slc#1 TYPE READSLICE PAR 0-6517 XREFS 42473 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {259 0 0-6675 {}}} SUCCS {{258 0 0-6699 {}} {258 0 0-6700 {}} {258 0 0-6703 {}} {258 0 0-6705 {}} {258 0 0-6708 {}} {258 0 0-6711 {}} {258 0 0-6712 {}} {258 0 0-6717 {}} {258 0 0-6719 {}} {258 0 0-6721 {}} {258 0 0-6738 {}} {258 0 0-6747 {}} {258 0 0-6748 {}} {258 0 0-6750 {}}} CYCLES {}}
+set a(0-6677) {NAME b:conc TYPE CONCATENATE PAR 0-6517 XREFS 42474 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.05517445} PREDS {{146 0 0-6668 {}} {258 0 0-6587 {}}} SUCCS {{259 0 0-6678 {}}} CYCLES {}}
+set a(0-6678) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 6 NAME ACC2:acc#6 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-6517 XREFS 42475 LOC {1 0.380514125 1 0.4061093 1 0.4061093 1 0.511719030357901 2 0.16078418035790099} PREDS {{146 0 0-6668 {}} {258 0 0-6661 {}} {259 0 0-6677 {}}} SUCCS {{259 0 0-6679 {}}} CYCLES {}}
+set a(0-6679) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 6 NAME ACC2-3:acc#3 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-6517 XREFS 42476 LOC {1 0.4861239 1 0.511719075 1 0.511719075 1 0.617328805357901 2 0.266393955357901} PREDS {{146 0 0-6668 {}} {258 0 0-6626 {}} {259 0 0-6678 {}}} SUCCS {{259 0 0-6680 {}}} CYCLES {}}
+set a(0-6680) {NAME ACC2:slc#2 TYPE READSLICE PAR 0-6517 XREFS 42477 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {259 0 0-6679 {}}} SUCCS {{258 0 0-6754 {}} {258 0 0-6755 {}} {258 0 0-6758 {}} {258 0 0-6760 {}} {258 0 0-6763 {}} {258 0 0-6766 {}} {258 0 0-6767 {}} {258 0 0-6772 {}} {258 0 0-6774 {}} {258 0 0-6776 {}} {258 0 0-6793 {}} {258 0 0-6802 {}} {258 0 0-6803 {}} {258 0 0-6805 {}}} CYCLES {}}
+set a(0-6681) {NAME red:slc(red#2.sg1)#4 TYPE READSLICE PAR 0-6517 XREFS 42478 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{258 0 0-6684 {}}} CYCLES {}}
+set a(0-6682) {NAME red:slc(red#2.sg1)#5 TYPE READSLICE PAR 0-6517 XREFS 42479 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{259 0 0-6683 {}}} CYCLES {}}
+set a(0-6683) {NAME FRAME:not#2 TYPE NOT PAR 0-6517 XREFS 42480 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6668 {}} {259 0 0-6682 {}}} SUCCS {{259 0 0-6684 {}}} CYCLES {}}
+set a(0-6684) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#8 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42481 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.39783505207082714} PREDS {{146 0 0-6668 {}} {258 0 0-6681 {}} {259 0 0-6683 {}}} SUCCS {{258 0 0-6692 {}}} CYCLES {}}
+set a(0-6685) {NAME red:slc(red#2.sg1)#6 TYPE READSLICE PAR 0-6517 XREFS 42482 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{259 0 0-6686 {}}} CYCLES {}}
+set a(0-6686) {NAME FRAME:not#3 TYPE NOT PAR 0-6517 XREFS 42483 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6668 {}} {259 0 0-6685 {}}} SUCCS {{258 0 0-6689 {}}} CYCLES {}}
+set a(0-6687) {NAME red:slc(red#2.sg1)#7 TYPE READSLICE PAR 0-6517 XREFS 42484 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{259 0 0-6688 {}}} CYCLES {}}
+set a(0-6688) {NAME FRAME:not#25 TYPE NOT PAR 0-6517 XREFS 42485 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6668 {}} {259 0 0-6687 {}}} SUCCS {{259 0 0-6689 {}}} CYCLES {}}
+set a(0-6689) {NAME FRAME:conc TYPE CONCATENATE PAR 0-6517 XREFS 42486 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6668 {}} {258 0 0-6686 {}} {259 0 0-6688 {}}} SUCCS {{258 0 0-6691 {}}} CYCLES {}}
+set a(0-6690) {NAME red:slc(red#2.sg1)#1 TYPE READSLICE PAR 0-6517 XREFS 42487 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{259 0 0-6691 {}}} CYCLES {}}
+set a(0-6691) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#7 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42488 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.39783505207082714} PREDS {{146 0 0-6668 {}} {258 0 0-6689 {}} {259 0 0-6690 {}}} SUCCS {{259 0 0-6692 {}}} CYCLES {}}
+set a(0-6692) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#10 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-6517 XREFS 42489 LOC {1 0.6392898499999999 1 0.664885025 1 0.664885025 1 0.7182320451789506 2 0.4511821201789505} PREDS {{146 0 0-6668 {}} {258 0 0-6684 {}} {259 0 0-6691 {}}} SUCCS {{258 0 0-6697 {}}} CYCLES {}}
+set a(0-6693) {NAME red:slc(red#2.sg1)#2 TYPE READSLICE PAR 0-6517 XREFS 42490 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.403626} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{258 0 0-6696 {}}} CYCLES {}}
+set a(0-6694) {NAME red:slc(red#2.sg1)#3 TYPE READSLICE PAR 0-6517 XREFS 42491 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.403626} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{259 0 0-6695 {}}} CYCLES {}}
+set a(0-6695) {NAME FRAME:not#1 TYPE NOT PAR 0-6517 XREFS 42492 LOC {1 0.591733675 1 0.670675925 1 0.670675925 2 0.403626} PREDS {{146 0 0-6668 {}} {259 0 0-6694 {}}} SUCCS {{259 0 0-6696 {}}} CYCLES {}}
+set a(0-6696) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#9 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42493 LOC {1 0.591733675 1 0.670675925 1 0.670675925 1 0.7182320520708271 2 0.45118212707082717} PREDS {{146 0 0-6668 {}} {258 0 0-6693 {}} {259 0 0-6695 {}}} SUCCS {{259 0 0-6697 {}}} CYCLES {}}
+set a(0-6697) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,4,0,6) AREA_SCORE 6.29 QUANTITY 3 NAME FRAME:acc#11 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42494 LOC {1 0.692636925 1 0.7182320999999999 1 0.7182320999999999 1 0.7769849308637015 2 0.5099350058637016} PREDS {{146 0 0-6668 {}} {258 0 0-6692 {}} {259 0 0-6696 {}}} SUCCS {{259 0 0-6698 {}}} CYCLES {}}
+set a(0-6698) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc#9 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-6517 XREFS 42495 LOC {1 0.7513898 1 0.776984975 1 0.776984975 1 0.8404969484103024 2 0.5734470234103024} PREDS {{146 0 0-6668 {}} {259 0 0-6697 {}}} SUCCS {{258 0 0-6820 {}} {258 0 0-6822 {}} {258 0 0-6824 {}} {258 0 0-6826 {}} {258 0 0-6834 {}} {258 0 0-6839 {}}} CYCLES {}}
+set a(0-6699) {NAME green:slc(green#2.sg1)#4 TYPE READSLICE PAR 0-6517 XREFS 42496 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{258 0 0-6702 {}}} CYCLES {}}
+set a(0-6700) {NAME green:slc(green#2.sg1)#5 TYPE READSLICE PAR 0-6517 XREFS 42497 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{259 0 0-6701 {}}} CYCLES {}}
+set a(0-6701) {NAME FRAME:not#10 TYPE NOT PAR 0-6517 XREFS 42498 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {259 0 0-6700 {}}} SUCCS {{259 0 0-6702 {}}} CYCLES {}}
+set a(0-6702) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#13 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42499 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.31395012707082715} PREDS {{146 0 0-6668 {}} {258 0 0-6699 {}} {259 0 0-6701 {}}} SUCCS {{258 0 0-6710 {}}} CYCLES {}}
+set a(0-6703) {NAME green:slc(green#2.sg1)#6 TYPE READSLICE PAR 0-6517 XREFS 42500 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{259 0 0-6704 {}}} CYCLES {}}
+set a(0-6704) {NAME FRAME:not#11 TYPE NOT PAR 0-6517 XREFS 42501 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {259 0 0-6703 {}}} SUCCS {{258 0 0-6707 {}}} CYCLES {}}
+set a(0-6705) {NAME green:slc(green#2.sg1)#7 TYPE READSLICE PAR 0-6517 XREFS 42502 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{259 0 0-6706 {}}} CYCLES {}}
+set a(0-6706) {NAME FRAME:not#26 TYPE NOT PAR 0-6517 XREFS 42503 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {259 0 0-6705 {}}} SUCCS {{259 0 0-6707 {}}} CYCLES {}}
+set a(0-6707) {NAME FRAME:conc#16 TYPE CONCATENATE PAR 0-6517 XREFS 42504 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {258 0 0-6704 {}} {259 0 0-6706 {}}} SUCCS {{258 0 0-6709 {}}} CYCLES {}}
+set a(0-6708) {NAME green:slc(green#2.sg1)#1 TYPE READSLICE PAR 0-6517 XREFS 42505 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{259 0 0-6709 {}}} CYCLES {}}
+set a(0-6709) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#12 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42506 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.31395012707082715} PREDS {{146 0 0-6668 {}} {258 0 0-6707 {}} {259 0 0-6708 {}}} SUCCS {{259 0 0-6710 {}}} CYCLES {}}
+set a(0-6710) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#15 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-6517 XREFS 42507 LOC {1 0.6392898499999999 1 0.664885025 1 0.664885025 1 0.7182320451789506 2 0.3672971951789505} PREDS {{146 0 0-6668 {}} {258 0 0-6702 {}} {259 0 0-6709 {}}} SUCCS {{258 0 0-6715 {}}} CYCLES {}}
+set a(0-6711) {NAME green:slc(green#2.sg1)#2 TYPE READSLICE PAR 0-6517 XREFS 42508 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.319741075} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{258 0 0-6714 {}}} CYCLES {}}
+set a(0-6712) {NAME green:slc(green#2.sg1)#3 TYPE READSLICE PAR 0-6517 XREFS 42509 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.319741075} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{259 0 0-6713 {}}} CYCLES {}}
+set a(0-6713) {NAME FRAME:not#9 TYPE NOT PAR 0-6517 XREFS 42510 LOC {1 0.591733675 1 0.670675925 1 0.670675925 2 0.319741075} PREDS {{146 0 0-6668 {}} {259 0 0-6712 {}}} SUCCS {{259 0 0-6714 {}}} CYCLES {}}
+set a(0-6714) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#14 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42511 LOC {1 0.591733675 1 0.670675925 1 0.670675925 1 0.7182320520708271 2 0.36729720207082717} PREDS {{146 0 0-6668 {}} {258 0 0-6711 {}} {259 0 0-6713 {}}} SUCCS {{259 0 0-6715 {}}} CYCLES {}}
+set a(0-6715) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,4,0,6) AREA_SCORE 6.29 QUANTITY 3 NAME FRAME:acc#16 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42512 LOC {1 0.692636925 1 0.7182320999999999 1 0.7182320999999999 1 0.7769849308637015 2 0.4260500808637015} PREDS {{146 0 0-6668 {}} {258 0 0-6710 {}} {259 0 0-6714 {}}} SUCCS {{259 0 0-6716 {}}} CYCLES {}}
+set a(0-6716) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc#11 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-6517 XREFS 42513 LOC {1 0.7513898 1 0.776984975 1 0.776984975 1 0.8404969484103024 2 0.4895620984103024} PREDS {{146 0 0-6668 {}} {259 0 0-6715 {}}} SUCCS {{258 0 0-6722 {}} {258 0 0-6724 {}} {258 0 0-6726 {}} {258 0 0-6728 {}} {258 0 0-6736 {}} {258 0 0-6741 {}}} CYCLES {}}
+set a(0-6717) {NAME green:slc(green#2.sg1)#9 TYPE READSLICE PAR 0-6517 XREFS 42514 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.6277733} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{259 0 0-6718 {}}} CYCLES {}}
+set a(0-6718) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#2 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-6517 XREFS 42515 LOC {1 0.591733675 1 0.809739975 1 0.809739975 1 0.9999999562499999 2 0.81803328125} PREDS {{146 0 0-6668 {}} {259 0 0-6717 {}}} SUCCS {{258 0 0-6746 {}}} CYCLES {}}
+set a(0-6719) {NAME green:slc(green#2.sg1)#11 TYPE READSLICE PAR 0-6517 XREFS 42516 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.5731230749999999} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{259 0 0-6720 {}}} CYCLES {}}
+set a(0-6720) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#3 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-6517 XREFS 42517 LOC {1 0.591733675 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.7510048671744312} PREDS {{146 0 0-6668 {}} {259 0 0-6719 {}}} SUCCS {{258 0 0-6745 {}}} CYCLES {}}
+set a(0-6721) {NAME green:slc(green#2.sg1) TYPE READSLICE PAR 0-6517 XREFS 42518 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.7076648999999999} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{258 0 0-6744 {}}} CYCLES {}}
+set a(0-6722) {NAME FRAME:slc(acc.imod#11)#6 TYPE READSLICE PAR 0-6517 XREFS 42519 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.5481619} PREDS {{146 0 0-6668 {}} {258 0 0-6716 {}}} SUCCS {{259 0 0-6723 {}}} CYCLES {}}
+set a(0-6723) {NAME FRAME:not#15 TYPE NOT PAR 0-6517 XREFS 42520 LOC {1 0.814901825 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6668 {}} {259 0 0-6722 {}}} SUCCS {{258 0 0-6735 {}}} CYCLES {}}
+set a(0-6724) {NAME FRAME:slc(acc.imod#11)#1 TYPE READSLICE PAR 0-6517 XREFS 42521 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {258 0 0-6716 {}}} SUCCS {{259 0 0-6725 {}}} CYCLES {}}
+set a(0-6725) {NAME FRAME:conc#24 TYPE CONCATENATE PAR 0-6517 XREFS 42522 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {259 0 0-6724 {}}} SUCCS {{258 0 0-6731 {}}} CYCLES {}}
+set a(0-6726) {NAME FRAME:slc(acc.imod#11)#2 TYPE READSLICE PAR 0-6517 XREFS 42523 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {258 0 0-6716 {}}} SUCCS {{259 0 0-6727 {}}} CYCLES {}}
+set a(0-6727) {NAME FRAME:not#13 TYPE NOT PAR 0-6517 XREFS 42524 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {259 0 0-6726 {}}} SUCCS {{258 0 0-6730 {}}} CYCLES {}}
+set a(0-6728) {NAME FRAME:slc(acc.imod#11) TYPE READSLICE PAR 0-6517 XREFS 42525 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {258 0 0-6716 {}}} SUCCS {{259 0 0-6729 {}}} CYCLES {}}
+set a(0-6729) {NAME FRAME:not#12 TYPE NOT PAR 0-6517 XREFS 42526 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {259 0 0-6728 {}}} SUCCS {{259 0 0-6730 {}}} CYCLES {}}
+set a(0-6730) {NAME FRAME:conc#25 TYPE CONCATENATE PAR 0-6517 XREFS 42527 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {258 0 0-6727 {}} {259 0 0-6729 {}}} SUCCS {{259 0 0-6731 {}}} CYCLES {}}
+set a(0-6731) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#23 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42528 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 1 0.899096709496936 2 0.5481618594969361} PREDS {{146 0 0-6668 {}} {258 0 0-6725 {}} {259 0 0-6730 {}}} SUCCS {{259 0 0-6732 {}}} CYCLES {}}
+set a(0-6732) {NAME FRAME:slc#5 TYPE READSLICE PAR 0-6517 XREFS 42529 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6668 {}} {259 0 0-6731 {}}} SUCCS {{259 0 0-6733 {}}} CYCLES {}}
+set a(0-6733) {NAME FRAME:slc#3 TYPE READSLICE PAR 0-6517 XREFS 42530 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6668 {}} {259 0 0-6732 {}}} SUCCS {{259 0 0-6734 {}}} CYCLES {}}
+set a(0-6734) {NAME FRAME:not#16 TYPE NOT PAR 0-6517 XREFS 42531 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6668 {}} {259 0 0-6733 {}}} SUCCS {{259 0 0-6735 {}}} CYCLES {}}
+set a(0-6735) {NAME FRAME:conc#7 TYPE CONCATENATE PAR 0-6517 XREFS 42532 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6668 {}} {258 0 0-6723 {}} {259 0 0-6734 {}}} SUCCS {{258 0 0-6737 {}}} CYCLES {}}
+set a(0-6736) {NAME FRAME:slc(acc.imod#11)#5 TYPE READSLICE PAR 0-6517 XREFS 42533 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.5481619} PREDS {{146 0 0-6668 {}} {258 0 0-6716 {}}} SUCCS {{259 0 0-6737 {}}} CYCLES {}}
+set a(0-6737) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#17 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42534 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 1 0.9466528770708271 2 0.5957180270708271} PREDS {{146 0 0-6668 {}} {258 0 0-6735 {}} {259 0 0-6736 {}}} SUCCS {{258 0 0-6740 {}}} CYCLES {}}
+set a(0-6738) {NAME green:slc(green#2.sg1)#10 TYPE READSLICE PAR 0-6517 XREFS 42535 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.595718075} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{259 0 0-6739 {}}} CYCLES {}}
+set a(0-6739) {NAME FRAME:not#14 TYPE NOT PAR 0-6517 XREFS 42536 LOC {1 0.591733675 1 0.946652925 1 0.946652925 2 0.595718075} PREDS {{146 0 0-6668 {}} {259 0 0-6738 {}}} SUCCS {{259 0 0-6740 {}}} CYCLES {}}
+set a(0-6740) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#18 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-6517 XREFS 42537 LOC {1 0.92105775 1 0.946652925 1 0.946652925 1 0.9999999451789505 2 0.6490650951789505} PREDS {{146 0 0-6668 {}} {258 0 0-6737 {}} {259 0 0-6739 {}}} SUCCS {{258 0 0-6743 {}}} CYCLES {}}
+set a(0-6741) {NAME FRAME:slc(acc.imod#11)#4 TYPE READSLICE PAR 0-6517 XREFS 42538 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.64906515} PREDS {{146 0 0-6668 {}} {258 0 0-6716 {}}} SUCCS {{259 0 0-6742 {}}} CYCLES {}}
+set a(0-6742) {NAME FRAME:conc#22 TYPE CONCATENATE PAR 0-6517 XREFS 42539 LOC {1 0.814901825 2 0.64906515 2 0.64906515 2 0.64906515} PREDS {{146 0 0-6668 {}} {259 0 0-6741 {}}} SUCCS {{259 0 0-6743 {}}} CYCLES {}}
+set a(0-6743) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#19 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42540 LOC {2 0.0 2 0.64906515 2 0.64906515 2 0.707664859496936 2 0.707664859496936} PREDS {{146 0 0-6668 {}} {258 0 0-6740 {}} {259 0 0-6742 {}}} SUCCS {{259 0 0-6744 {}}} CYCLES {}}
+set a(0-6744) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#20 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-6517 XREFS 42541 LOC {2 0.05859975 2 0.7076648999999999 2 0.7076648999999999 2 0.7510048657468814 2 0.7510048657468814} PREDS {{146 0 0-6668 {}} {258 0 0-6721 {}} {259 0 0-6743 {}}} SUCCS {{259 0 0-6745 {}}} CYCLES {}}
+set a(0-6745) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#21 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-6517 XREFS 42542 LOC {2 0.101939775 2 0.7510049249999999 2 0.7510049249999999 2 0.8180332818650199 2 0.8180332818650199} PREDS {{146 0 0-6668 {}} {258 0 0-6720 {}} {259 0 0-6744 {}}} SUCCS {{259 0 0-6746 {}}} CYCLES {}}
+set a(0-6746) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,10,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME FRAME:acc#22 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-6517 XREFS 42543 LOC {2 0.168968175 2 0.8180333249999999 2 0.8180333249999999 2 0.8935106093138832 2 0.8935106093138832} PREDS {{146 0 0-6668 {}} {258 0 0-6718 {}} {259 0 0-6745 {}}} SUCCS {{258 0 0-6753 {}}} CYCLES {}}
+set a(0-6747) {NAME green:slc(green#2.sg1)#12 TYPE READSLICE PAR 0-6517 XREFS 42544 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.89351065} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{258 0 0-6751 {}}} CYCLES {}}
+set a(0-6748) {NAME green:slc(green#2.sg1)#13 TYPE READSLICE PAR 0-6517 XREFS 42545 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.89351065} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{259 0 0-6749 {}}} CYCLES {}}
+set a(0-6749) {NAME FRAME:exs#3 TYPE SIGNEXTEND PAR 0-6517 XREFS 42546 LOC {1 0.591733675 2 0.89351065 2 0.89351065 2 0.89351065} PREDS {{146 0 0-6668 {}} {259 0 0-6748 {}}} SUCCS {{258 0 0-6751 {}}} CYCLES {}}
+set a(0-6750) {NAME green:slc(green#2.sg1)#8 TYPE READSLICE PAR 0-6517 XREFS 42547 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.89351065} PREDS {{146 0 0-6668 {}} {258 0 0-6676 {}}} SUCCS {{259 0 0-6751 {}}} CYCLES {}}
+set a(0-6751) {NAME FRAME:conc#6 TYPE CONCATENATE PAR 0-6517 XREFS 42548 LOC {1 0.591733675 2 0.89351065 2 0.89351065 2 0.89351065} PREDS {{146 0 0-6668 {}} {258 0 0-6749 {}} {258 0 0-6747 {}} {259 0 0-6750 {}}} SUCCS {{259 0 0-6752 {}}} CYCLES {}}
+set a(0-6752) {NAME FRAME:exs#2 TYPE SIGNEXTEND PAR 0-6517 XREFS 42549 LOC {1 0.591733675 2 0.89351065 2 0.89351065 2 0.89351065} PREDS {{146 0 0-6668 {}} {259 0 0-6751 {}}} SUCCS {{259 0 0-6753 {}}} CYCLES {}}
+set a(0-6753) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,11,0,12) AREA_SCORE 13.23 QUANTITY 2 NAME FRAME:acc#3 TYPE ACCU DELAY {1.44 ns} LIBRARY_DELAY {1.44 ns} PAR 0-6517 XREFS 42550 LOC {2 0.24444549999999998 2 0.89351065 2 0.89351065 2 0.9832574816459019 2 0.9832574816459019} PREDS {{146 0 0-6668 {}} {258 0 0-6746 {}} {259 0 0-6752 {}}} SUCCS {{258 0 0-6845 {}} {258 0 0-6848 {}} {258 0 0-6849 {}}} CYCLES {}}
+set a(0-6754) {NAME blue:slc(blue#2.sg1)#4 TYPE READSLICE PAR 0-6517 XREFS 42551 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{258 0 0-6757 {}}} CYCLES {}}
+set a(0-6755) {NAME blue:slc(blue#2.sg1)#5 TYPE READSLICE PAR 0-6517 XREFS 42552 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{259 0 0-6756 {}}} CYCLES {}}
+set a(0-6756) {NAME FRAME:not#18 TYPE NOT PAR 0-6517 XREFS 42553 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {259 0 0-6755 {}}} SUCCS {{259 0 0-6757 {}}} CYCLES {}}
+set a(0-6757) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#25 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42554 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.31395012707082715} PREDS {{146 0 0-6668 {}} {258 0 0-6754 {}} {259 0 0-6756 {}}} SUCCS {{258 0 0-6765 {}}} CYCLES {}}
+set a(0-6758) {NAME blue:slc(blue#2.sg1)#6 TYPE READSLICE PAR 0-6517 XREFS 42555 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{259 0 0-6759 {}}} CYCLES {}}
+set a(0-6759) {NAME FRAME:not#19 TYPE NOT PAR 0-6517 XREFS 42556 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {259 0 0-6758 {}}} SUCCS {{258 0 0-6762 {}}} CYCLES {}}
+set a(0-6760) {NAME blue:slc(blue#2.sg1)#7 TYPE READSLICE PAR 0-6517 XREFS 42557 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{259 0 0-6761 {}}} CYCLES {}}
+set a(0-6761) {NAME FRAME:not#27 TYPE NOT PAR 0-6517 XREFS 42558 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {259 0 0-6760 {}}} SUCCS {{259 0 0-6762 {}}} CYCLES {}}
+set a(0-6762) {NAME FRAME:conc#17 TYPE CONCATENATE PAR 0-6517 XREFS 42559 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {258 0 0-6759 {}} {259 0 0-6761 {}}} SUCCS {{258 0 0-6764 {}}} CYCLES {}}
+set a(0-6763) {NAME blue:slc(blue#2.sg1)#1 TYPE READSLICE PAR 0-6517 XREFS 42560 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{259 0 0-6764 {}}} CYCLES {}}
+set a(0-6764) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#24 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42561 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.31395012707082715} PREDS {{146 0 0-6668 {}} {258 0 0-6762 {}} {259 0 0-6763 {}}} SUCCS {{259 0 0-6765 {}}} CYCLES {}}
+set a(0-6765) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#27 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-6517 XREFS 42562 LOC {1 0.6392898499999999 1 0.664885025 1 0.664885025 1 0.7182320451789506 2 0.3672971951789505} PREDS {{146 0 0-6668 {}} {258 0 0-6757 {}} {259 0 0-6764 {}}} SUCCS {{258 0 0-6770 {}}} CYCLES {}}
+set a(0-6766) {NAME blue:slc(blue#2.sg1)#2 TYPE READSLICE PAR 0-6517 XREFS 42563 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.319741075} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{258 0 0-6769 {}}} CYCLES {}}
+set a(0-6767) {NAME blue:slc(blue#2.sg1)#3 TYPE READSLICE PAR 0-6517 XREFS 42564 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.319741075} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{259 0 0-6768 {}}} CYCLES {}}
+set a(0-6768) {NAME FRAME:not#17 TYPE NOT PAR 0-6517 XREFS 42565 LOC {1 0.591733675 1 0.670675925 1 0.670675925 2 0.319741075} PREDS {{146 0 0-6668 {}} {259 0 0-6767 {}}} SUCCS {{259 0 0-6769 {}}} CYCLES {}}
+set a(0-6769) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#26 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42566 LOC {1 0.591733675 1 0.670675925 1 0.670675925 1 0.7182320520708271 2 0.36729720207082717} PREDS {{146 0 0-6668 {}} {258 0 0-6766 {}} {259 0 0-6768 {}}} SUCCS {{259 0 0-6770 {}}} CYCLES {}}
+set a(0-6770) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,4,0,6) AREA_SCORE 6.29 QUANTITY 3 NAME FRAME:acc#28 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42567 LOC {1 0.692636925 1 0.7182320999999999 1 0.7182320999999999 1 0.7769849308637015 2 0.4260500808637015} PREDS {{146 0 0-6668 {}} {258 0 0-6765 {}} {259 0 0-6769 {}}} SUCCS {{259 0 0-6771 {}}} CYCLES {}}
+set a(0-6771) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc#13 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-6517 XREFS 42568 LOC {1 0.7513898 1 0.776984975 1 0.776984975 1 0.8404969484103024 2 0.4895620984103024} PREDS {{146 0 0-6668 {}} {259 0 0-6770 {}}} SUCCS {{258 0 0-6777 {}} {258 0 0-6779 {}} {258 0 0-6781 {}} {258 0 0-6783 {}} {258 0 0-6791 {}} {258 0 0-6796 {}}} CYCLES {}}
+set a(0-6772) {NAME blue:slc(blue#2.sg1)#9 TYPE READSLICE PAR 0-6517 XREFS 42569 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.6277733} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{259 0 0-6773 {}}} CYCLES {}}
+set a(0-6773) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#4 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-6517 XREFS 42570 LOC {1 0.591733675 1 0.809739975 1 0.809739975 1 0.9999999562499999 2 0.81803328125} PREDS {{146 0 0-6668 {}} {259 0 0-6772 {}}} SUCCS {{258 0 0-6801 {}}} CYCLES {}}
+set a(0-6774) {NAME blue:slc(blue#2.sg1)#11 TYPE READSLICE PAR 0-6517 XREFS 42571 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.5731230749999999} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{259 0 0-6775 {}}} CYCLES {}}
+set a(0-6775) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#5 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-6517 XREFS 42572 LOC {1 0.591733675 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.7510048671744312} PREDS {{146 0 0-6668 {}} {259 0 0-6774 {}}} SUCCS {{258 0 0-6800 {}}} CYCLES {}}
+set a(0-6776) {NAME blue:slc(blue#2.sg1) TYPE READSLICE PAR 0-6517 XREFS 42573 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.7076648999999999} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{258 0 0-6799 {}}} CYCLES {}}
+set a(0-6777) {NAME FRAME:slc(acc.imod#13)#6 TYPE READSLICE PAR 0-6517 XREFS 42574 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.5481619} PREDS {{146 0 0-6668 {}} {258 0 0-6771 {}}} SUCCS {{259 0 0-6778 {}}} CYCLES {}}
+set a(0-6778) {NAME FRAME:not#23 TYPE NOT PAR 0-6517 XREFS 42575 LOC {1 0.814901825 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6668 {}} {259 0 0-6777 {}}} SUCCS {{258 0 0-6790 {}}} CYCLES {}}
+set a(0-6779) {NAME FRAME:slc(acc.imod#13)#1 TYPE READSLICE PAR 0-6517 XREFS 42576 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {258 0 0-6771 {}}} SUCCS {{259 0 0-6780 {}}} CYCLES {}}
+set a(0-6780) {NAME FRAME:conc#28 TYPE CONCATENATE PAR 0-6517 XREFS 42577 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {259 0 0-6779 {}}} SUCCS {{258 0 0-6786 {}}} CYCLES {}}
+set a(0-6781) {NAME FRAME:slc(acc.imod#13)#2 TYPE READSLICE PAR 0-6517 XREFS 42578 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {258 0 0-6771 {}}} SUCCS {{259 0 0-6782 {}}} CYCLES {}}
+set a(0-6782) {NAME FRAME:not#21 TYPE NOT PAR 0-6517 XREFS 42579 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {259 0 0-6781 {}}} SUCCS {{258 0 0-6785 {}}} CYCLES {}}
+set a(0-6783) {NAME FRAME:slc(acc.imod#13) TYPE READSLICE PAR 0-6517 XREFS 42580 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {258 0 0-6771 {}}} SUCCS {{259 0 0-6784 {}}} CYCLES {}}
+set a(0-6784) {NAME FRAME:not#20 TYPE NOT PAR 0-6517 XREFS 42581 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {259 0 0-6783 {}}} SUCCS {{259 0 0-6785 {}}} CYCLES {}}
+set a(0-6785) {NAME FRAME:conc#29 TYPE CONCATENATE PAR 0-6517 XREFS 42582 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6668 {}} {258 0 0-6782 {}} {259 0 0-6784 {}}} SUCCS {{259 0 0-6786 {}}} CYCLES {}}
+set a(0-6786) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#35 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42583 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 1 0.899096709496936 2 0.5481618594969361} PREDS {{146 0 0-6668 {}} {258 0 0-6780 {}} {259 0 0-6785 {}}} SUCCS {{259 0 0-6787 {}}} CYCLES {}}
+set a(0-6787) {NAME FRAME:slc#6 TYPE READSLICE PAR 0-6517 XREFS 42584 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6668 {}} {259 0 0-6786 {}}} SUCCS {{259 0 0-6788 {}}} CYCLES {}}
+set a(0-6788) {NAME FRAME:slc#4 TYPE READSLICE PAR 0-6517 XREFS 42585 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6668 {}} {259 0 0-6787 {}}} SUCCS {{259 0 0-6789 {}}} CYCLES {}}
+set a(0-6789) {NAME FRAME:not#24 TYPE NOT PAR 0-6517 XREFS 42586 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6668 {}} {259 0 0-6788 {}}} SUCCS {{259 0 0-6790 {}}} CYCLES {}}
+set a(0-6790) {NAME FRAME:conc#11 TYPE CONCATENATE PAR 0-6517 XREFS 42587 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6668 {}} {258 0 0-6778 {}} {259 0 0-6789 {}}} SUCCS {{258 0 0-6792 {}}} CYCLES {}}
+set a(0-6791) {NAME FRAME:slc(acc.imod#13)#5 TYPE READSLICE PAR 0-6517 XREFS 42588 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.5481619} PREDS {{146 0 0-6668 {}} {258 0 0-6771 {}}} SUCCS {{259 0 0-6792 {}}} CYCLES {}}
+set a(0-6792) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#29 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42589 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 1 0.9466528770708271 2 0.5957180270708271} PREDS {{146 0 0-6668 {}} {258 0 0-6790 {}} {259 0 0-6791 {}}} SUCCS {{258 0 0-6795 {}}} CYCLES {}}
+set a(0-6793) {NAME blue:slc(blue#2.sg1)#10 TYPE READSLICE PAR 0-6517 XREFS 42590 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.595718075} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{259 0 0-6794 {}}} CYCLES {}}
+set a(0-6794) {NAME FRAME:not#22 TYPE NOT PAR 0-6517 XREFS 42591 LOC {1 0.591733675 1 0.946652925 1 0.946652925 2 0.595718075} PREDS {{146 0 0-6668 {}} {259 0 0-6793 {}}} SUCCS {{259 0 0-6795 {}}} CYCLES {}}
+set a(0-6795) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#30 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-6517 XREFS 42592 LOC {1 0.92105775 1 0.946652925 1 0.946652925 1 0.9999999451789505 2 0.6490650951789505} PREDS {{146 0 0-6668 {}} {258 0 0-6792 {}} {259 0 0-6794 {}}} SUCCS {{258 0 0-6798 {}}} CYCLES {}}
+set a(0-6796) {NAME FRAME:slc(acc.imod#13)#4 TYPE READSLICE PAR 0-6517 XREFS 42593 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.64906515} PREDS {{146 0 0-6668 {}} {258 0 0-6771 {}}} SUCCS {{259 0 0-6797 {}}} CYCLES {}}
+set a(0-6797) {NAME FRAME:conc#26 TYPE CONCATENATE PAR 0-6517 XREFS 42594 LOC {1 0.814901825 2 0.64906515 2 0.64906515 2 0.64906515} PREDS {{146 0 0-6668 {}} {259 0 0-6796 {}}} SUCCS {{259 0 0-6798 {}}} CYCLES {}}
+set a(0-6798) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#31 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42595 LOC {2 0.0 2 0.64906515 2 0.64906515 2 0.707664859496936 2 0.707664859496936} PREDS {{146 0 0-6668 {}} {258 0 0-6795 {}} {259 0 0-6797 {}}} SUCCS {{259 0 0-6799 {}}} CYCLES {}}
+set a(0-6799) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#32 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-6517 XREFS 42596 LOC {2 0.05859975 2 0.7076648999999999 2 0.7076648999999999 2 0.7510048657468814 2 0.7510048657468814} PREDS {{146 0 0-6668 {}} {258 0 0-6776 {}} {259 0 0-6798 {}}} SUCCS {{259 0 0-6800 {}}} CYCLES {}}
+set a(0-6800) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#33 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-6517 XREFS 42597 LOC {2 0.101939775 2 0.7510049249999999 2 0.7510049249999999 2 0.8180332818650199 2 0.8180332818650199} PREDS {{146 0 0-6668 {}} {258 0 0-6775 {}} {259 0 0-6799 {}}} SUCCS {{259 0 0-6801 {}}} CYCLES {}}
+set a(0-6801) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,10,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME FRAME:acc#34 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-6517 XREFS 42598 LOC {2 0.168968175 2 0.8180333249999999 2 0.8180333249999999 2 0.8935106093138832 2 0.8935106093138832} PREDS {{146 0 0-6668 {}} {258 0 0-6773 {}} {259 0 0-6800 {}}} SUCCS {{258 0 0-6808 {}}} CYCLES {}}
+set a(0-6802) {NAME blue:slc(blue#2.sg1)#12 TYPE READSLICE PAR 0-6517 XREFS 42599 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.89351065} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{258 0 0-6806 {}}} CYCLES {}}
+set a(0-6803) {NAME blue:slc(blue#2.sg1)#13 TYPE READSLICE PAR 0-6517 XREFS 42600 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.89351065} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{259 0 0-6804 {}}} CYCLES {}}
+set a(0-6804) {NAME FRAME:exs#5 TYPE SIGNEXTEND PAR 0-6517 XREFS 42601 LOC {1 0.591733675 2 0.89351065 2 0.89351065 2 0.89351065} PREDS {{146 0 0-6668 {}} {259 0 0-6803 {}}} SUCCS {{258 0 0-6806 {}}} CYCLES {}}
+set a(0-6805) {NAME blue:slc(blue#2.sg1)#8 TYPE READSLICE PAR 0-6517 XREFS 42602 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.89351065} PREDS {{146 0 0-6668 {}} {258 0 0-6680 {}}} SUCCS {{259 0 0-6806 {}}} CYCLES {}}
+set a(0-6806) {NAME FRAME:conc#10 TYPE CONCATENATE PAR 0-6517 XREFS 42603 LOC {1 0.591733675 2 0.89351065 2 0.89351065 2 0.89351065} PREDS {{146 0 0-6668 {}} {258 0 0-6804 {}} {258 0 0-6802 {}} {259 0 0-6805 {}}} SUCCS {{259 0 0-6807 {}}} CYCLES {}}
+set a(0-6807) {NAME FRAME:exs#4 TYPE SIGNEXTEND PAR 0-6517 XREFS 42604 LOC {1 0.591733675 2 0.89351065 2 0.89351065 2 0.89351065} PREDS {{146 0 0-6668 {}} {259 0 0-6806 {}}} SUCCS {{259 0 0-6808 {}}} CYCLES {}}
+set a(0-6808) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,11,0,12) AREA_SCORE 13.23 QUANTITY 2 NAME FRAME:acc#4 TYPE ACCU DELAY {1.44 ns} LIBRARY_DELAY {1.44 ns} PAR 0-6517 XREFS 42605 LOC {2 0.24444549999999998 2 0.89351065 2 0.89351065 2 0.9832574816459019 2 0.9832574816459019} PREDS {{146 0 0-6668 {}} {258 0 0-6801 {}} {259 0 0-6807 {}}} SUCCS {{258 0 0-6850 {}} {258 0 0-6853 {}}} CYCLES {}}
+set a(0-6809) {NAME red:slc(red#2.sg1)#13 TYPE READSLICE PAR 0-6517 XREFS 42606 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.63020875} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{259 0 0-6810 {}}} CYCLES {}}
+set a(0-6810) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-6517 XREFS 42607 LOC {1 0.591733675 1 0.7282905 1 0.7282905 1 0.9185504812499999 2 0.82046873125} PREDS {{146 0 0-6668 {}} {259 0 0-6809 {}}} SUCCS {{258 0 0-6816 {}}} CYCLES {}}
+set a(0-6811) {NAME red:slc(red#2.sg1)#11 TYPE READSLICE PAR 0-6517 XREFS 42608 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.8204687749999999} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{258 0 0-6815 {}}} CYCLES {}}
+set a(0-6812) {NAME red:slc(red#2.sg1)#12 TYPE READSLICE PAR 0-6517 XREFS 42609 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.8204687749999999} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{259 0 0-6813 {}}} CYCLES {}}
+set a(0-6813) {NAME FRAME:exs#1 TYPE SIGNEXTEND PAR 0-6517 XREFS 42610 LOC {1 0.591733675 1 0.918550525 1 0.918550525 2 0.8204687749999999} PREDS {{146 0 0-6668 {}} {259 0 0-6812 {}}} SUCCS {{258 0 0-6815 {}}} CYCLES {}}
+set a(0-6814) {NAME red:slc(red#2.sg1)#8 TYPE READSLICE PAR 0-6517 XREFS 42611 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.8204687749999999} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{259 0 0-6815 {}}} CYCLES {}}
+set a(0-6815) {NAME FRAME:conc#2 TYPE CONCATENATE PAR 0-6517 XREFS 42612 LOC {1 0.591733675 1 0.918550525 1 0.918550525 2 0.8204687749999999} PREDS {{146 0 0-6668 {}} {258 0 0-6813 {}} {258 0 0-6811 {}} {259 0 0-6814 {}}} SUCCS {{259 0 0-6816 {}}} CYCLES {}}
+set a(0-6816) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,9,1,10) AREA_SCORE 11.00 QUANTITY 1 NAME FRAME:acc#41 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-6517 XREFS 42613 LOC {1 0.7819937 1 0.918550525 1 0.918550525 1 0.9999999444798112 2 0.9019181944798111} PREDS {{146 0 0-6668 {}} {258 0 0-6810 {}} {259 0 0-6815 {}}} SUCCS {{258 0 0-6844 {}}} CYCLES {}}
+set a(0-6817) {NAME red:slc(red#2.sg1)#10 TYPE READSLICE PAR 0-6517 XREFS 42614 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.6570079999999999} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{259 0 0-6818 {}}} CYCLES {}}
+set a(0-6818) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#1 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-6517 XREFS 42615 LOC {1 0.591733675 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.8348897921744312} PREDS {{146 0 0-6668 {}} {259 0 0-6817 {}}} SUCCS {{258 0 0-6843 {}}} CYCLES {}}
+set a(0-6819) {NAME red:slc(red#2.sg1) TYPE READSLICE PAR 0-6517 XREFS 42616 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.7915498249999999} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{258 0 0-6842 {}}} CYCLES {}}
+set a(0-6820) {NAME FRAME:slc(acc.imod#9)#6 TYPE READSLICE PAR 0-6517 XREFS 42617 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.632046825} PREDS {{146 0 0-6668 {}} {258 0 0-6698 {}}} SUCCS {{259 0 0-6821 {}}} CYCLES {}}
+set a(0-6821) {NAME FRAME:not#7 TYPE NOT PAR 0-6517 XREFS 42618 LOC {1 0.814901825 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-6668 {}} {259 0 0-6820 {}}} SUCCS {{258 0 0-6833 {}}} CYCLES {}}
+set a(0-6822) {NAME FRAME:slc(acc.imod#9)#1 TYPE READSLICE PAR 0-6517 XREFS 42619 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6668 {}} {258 0 0-6698 {}}} SUCCS {{259 0 0-6823 {}}} CYCLES {}}
+set a(0-6823) {NAME FRAME:conc#32 TYPE CONCATENATE PAR 0-6517 XREFS 42620 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6668 {}} {259 0 0-6822 {}}} SUCCS {{258 0 0-6829 {}}} CYCLES {}}
+set a(0-6824) {NAME FRAME:slc(acc.imod#9)#2 TYPE READSLICE PAR 0-6517 XREFS 42621 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6668 {}} {258 0 0-6698 {}}} SUCCS {{259 0 0-6825 {}}} CYCLES {}}
+set a(0-6825) {NAME FRAME:not#5 TYPE NOT PAR 0-6517 XREFS 42622 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6668 {}} {259 0 0-6824 {}}} SUCCS {{258 0 0-6828 {}}} CYCLES {}}
+set a(0-6826) {NAME FRAME:slc(acc.imod#9) TYPE READSLICE PAR 0-6517 XREFS 42623 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6668 {}} {258 0 0-6698 {}}} SUCCS {{259 0 0-6827 {}}} CYCLES {}}
+set a(0-6827) {NAME FRAME:not#4 TYPE NOT PAR 0-6517 XREFS 42624 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6668 {}} {259 0 0-6826 {}}} SUCCS {{259 0 0-6828 {}}} CYCLES {}}
+set a(0-6828) {NAME FRAME:conc#33 TYPE CONCATENATE PAR 0-6517 XREFS 42625 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6668 {}} {258 0 0-6825 {}} {259 0 0-6827 {}}} SUCCS {{259 0 0-6829 {}}} CYCLES {}}
+set a(0-6829) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#42 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42626 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 1 0.899096709496936 2 0.6320467844969361} PREDS {{146 0 0-6668 {}} {258 0 0-6823 {}} {259 0 0-6828 {}}} SUCCS {{259 0 0-6830 {}}} CYCLES {}}
+set a(0-6830) {NAME FRAME:slc#7 TYPE READSLICE PAR 0-6517 XREFS 42627 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-6668 {}} {259 0 0-6829 {}}} SUCCS {{259 0 0-6831 {}}} CYCLES {}}
+set a(0-6831) {NAME FRAME:slc#2 TYPE READSLICE PAR 0-6517 XREFS 42628 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-6668 {}} {259 0 0-6830 {}}} SUCCS {{259 0 0-6832 {}}} CYCLES {}}
+set a(0-6832) {NAME FRAME:not#8 TYPE NOT PAR 0-6517 XREFS 42629 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-6668 {}} {259 0 0-6831 {}}} SUCCS {{259 0 0-6833 {}}} CYCLES {}}
+set a(0-6833) {NAME FRAME:conc#3 TYPE CONCATENATE PAR 0-6517 XREFS 42630 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-6668 {}} {258 0 0-6821 {}} {259 0 0-6832 {}}} SUCCS {{258 0 0-6835 {}}} CYCLES {}}
+set a(0-6834) {NAME FRAME:slc(acc.imod#9)#5 TYPE READSLICE PAR 0-6517 XREFS 42631 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.632046825} PREDS {{146 0 0-6668 {}} {258 0 0-6698 {}}} SUCCS {{259 0 0-6835 {}}} CYCLES {}}
+set a(0-6835) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#36 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42632 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 1 0.9466528770708271 2 0.6796029520708271} PREDS {{146 0 0-6668 {}} {258 0 0-6833 {}} {259 0 0-6834 {}}} SUCCS {{258 0 0-6838 {}}} CYCLES {}}
+set a(0-6836) {NAME red:slc(red#2.sg1)#9 TYPE READSLICE PAR 0-6517 XREFS 42633 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.679603} PREDS {{146 0 0-6668 {}} {258 0 0-6672 {}}} SUCCS {{259 0 0-6837 {}}} CYCLES {}}
+set a(0-6837) {NAME FRAME:not#6 TYPE NOT PAR 0-6517 XREFS 42634 LOC {1 0.591733675 1 0.946652925 1 0.946652925 2 0.679603} PREDS {{146 0 0-6668 {}} {259 0 0-6836 {}}} SUCCS {{259 0 0-6838 {}}} CYCLES {}}
+set a(0-6838) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#37 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-6517 XREFS 42635 LOC {1 0.92105775 1 0.946652925 1 0.946652925 1 0.9999999451789505 2 0.7329500201789505} PREDS {{146 0 0-6668 {}} {258 0 0-6835 {}} {259 0 0-6837 {}}} SUCCS {{258 0 0-6841 {}}} CYCLES {}}
+set a(0-6839) {NAME FRAME:slc(acc.imod#9)#4 TYPE READSLICE PAR 0-6517 XREFS 42636 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.732950075} PREDS {{146 0 0-6668 {}} {258 0 0-6698 {}}} SUCCS {{259 0 0-6840 {}}} CYCLES {}}
+set a(0-6840) {NAME FRAME:conc#30 TYPE CONCATENATE PAR 0-6517 XREFS 42637 LOC {1 0.814901825 2 0.732950075 2 0.732950075 2 0.732950075} PREDS {{146 0 0-6668 {}} {259 0 0-6839 {}}} SUCCS {{259 0 0-6841 {}}} CYCLES {}}
+set a(0-6841) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#38 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42638 LOC {2 0.0 2 0.732950075 2 0.732950075 2 0.791549784496936 2 0.791549784496936} PREDS {{146 0 0-6668 {}} {258 0 0-6838 {}} {259 0 0-6840 {}}} SUCCS {{259 0 0-6842 {}}} CYCLES {}}
+set a(0-6842) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#39 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-6517 XREFS 42639 LOC {2 0.05859975 2 0.7915498249999999 2 0.7915498249999999 2 0.8348897907468814 2 0.8348897907468814} PREDS {{146 0 0-6668 {}} {258 0 0-6819 {}} {259 0 0-6841 {}}} SUCCS {{259 0 0-6843 {}}} CYCLES {}}
+set a(0-6843) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#40 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-6517 XREFS 42640 LOC {2 0.101939775 2 0.8348898499999999 2 0.8348898499999999 2 0.9019182068650199 2 0.9019182068650199} PREDS {{146 0 0-6668 {}} {258 0 0-6818 {}} {259 0 0-6842 {}}} SUCCS {{259 0 0-6844 {}}} CYCLES {}}
+set a(0-6844) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,10) AREA_SCORE 11.24 QUANTITY 1 NAME FRAME:acc#2 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-6517 XREFS 42641 LOC {2 0.168968175 2 0.9019182499999999 2 0.9019182499999999 2 0.9832574783364112 2 0.9832574783364112} PREDS {{146 0 0-6668 {}} {258 0 0-6816 {}} {259 0 0-6843 {}}} SUCCS {{258 0 0-6847 {}}} CYCLES {}}
+set a(0-6845) {NAME green:slc(green) TYPE READSLICE PAR 0-6517 XREFS 42642 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-6668 {}} {258 0 0-6753 {}}} SUCCS {{259 0 0-6846 {}}} CYCLES {}}
+set a(0-6846) {NAME FRAME:exu TYPE PADZEROES PAR 0-6517 XREFS 42643 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-6668 {}} {259 0 0-6845 {}}} SUCCS {{259 0 0-6847 {}}} CYCLES {}}
+set a(0-6847) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(10,2) AREA_SCORE 7.30 QUANTITY 1 NAME FRAME:or TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-6517 XREFS 42644 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{146 0 0-6668 {}} {258 0 0-6844 {}} {259 0 0-6846 {}}} SUCCS {{258 0 0-6854 {}}} CYCLES {}}
+set a(0-6848) {NAME green:slc(green)#1 TYPE READSLICE PAR 0-6517 XREFS 42645 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 1.0} PREDS {{146 0 0-6668 {}} {258 0 0-6753 {}}} SUCCS {{258 0 0-6854 {}}} CYCLES {}}
+set a(0-6849) {NAME green:slc(green)#2 TYPE READSLICE PAR 0-6517 XREFS 42646 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-6668 {}} {258 0 0-6753 {}}} SUCCS {{258 0 0-6852 {}}} CYCLES {}}
+set a(0-6850) {NAME blue:slc(blue) TYPE READSLICE PAR 0-6517 XREFS 42647 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-6668 {}} {258 0 0-6808 {}}} SUCCS {{259 0 0-6851 {}}} CYCLES {}}
+set a(0-6851) {NAME FRAME:exu#10 TYPE PADZEROES PAR 0-6517 XREFS 42648 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-6668 {}} {259 0 0-6850 {}}} SUCCS {{259 0 0-6852 {}}} CYCLES {}}
+set a(0-6852) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(6,2) AREA_SCORE 4.38 QUANTITY 1 NAME FRAME:or#3 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-6517 XREFS 42649 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{146 0 0-6668 {}} {258 0 0-6849 {}} {259 0 0-6851 {}}} SUCCS {{258 0 0-6854 {}}} CYCLES {}}
+set a(0-6853) {NAME blue:slc(blue)#1 TYPE READSLICE PAR 0-6517 XREFS 42650 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 1.0} PREDS {{146 0 0-6668 {}} {258 0 0-6808 {}}} SUCCS {{259 0 0-6854 {}}} CYCLES {}}
+set a(0-6854) {NAME FRAME:conc#21 TYPE CONCATENATE PAR 0-6517 XREFS 42651 LOC {2 0.35093484999999996 2 1.0 2 1.0 2 1.0} PREDS {{146 0 0-6668 {}} {258 0 0-6852 {}} {258 0 0-6848 {}} {258 0 0-6847 {}} {259 0 0-6853 {}}} SUCCS {{259 0 0-6855 {}}} CYCLES {}}
+set a(0-6855) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(2,30) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_write(vout:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-6517 XREFS 42652 LOC {2 1.0 2 1.0 2 1.0 3 0.0 2 0.9999} PREDS {{130 0 0-6668 {}} {260 0 0-6855 {}} {259 0 0-6854 {}}} SUCCS {{260 0 0-6855 {}}} CYCLES {}}
+set a(0-6856) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(19,0,2,1,19) AREA_SCORE 20.00 QUANTITY 1 NAME FRAME:acc#6 TYPE ACCU DELAY {1.91 ns} LIBRARY_DELAY {1.91 ns} PAR 0-6517 XREFS 42653 LOC {1 0.088339225 1 0.738743625 1 0.738743625 1 0.8580029410815966 2 0.4774888160815965} PREDS {{146 0 0-6668 {}} {258 0 0-6546 {}}} SUCCS {{259 0 0-6857 {}} {258 0 0-6981 {}}} CYCLES {}}
+set a(0-6857) {NAME FRAME:p:slc(FRAME:p)#1 TYPE READSLICE PAR 0-6517 XREFS 42654 LOC {1 0.2075986 1 0.858003 1 0.858003 2 0.477488875} PREDS {{146 0 0-6668 {}} {259 0 0-6856 {}}} SUCCS {{259 0 0-6858 {}}} CYCLES {}}
+set a(0-6858) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,7,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME FRAME:acc TYPE ACCU DELAY {1.17 ns} LIBRARY_DELAY {1.17 ns} PAR 0-6517 XREFS 42655 LOC {1 0.2075986 1 0.858003 1 0.858003 1 0.9308181617915235 2 0.5503040367915236} PREDS {{146 0 0-6668 {}} {259 0 0-6857 {}}} SUCCS {{259 0 0-6859 {}}} CYCLES {}}
+set a(0-6859) {NAME FRAME:slc TYPE READSLICE PAR 0-6517 XREFS 42656 LOC {1 0.2804138 1 0.9308181999999999 1 0.9308181999999999 2 0.550304075} PREDS {{146 0 0-6668 {}} {259 0 0-6858 {}}} SUCCS {{259 0 0-6860 {}}} CYCLES {}}
+set a(0-6860) {NAME FRAME:not TYPE NOT PAR 0-6517 XREFS 42657 LOC {1 0.2804138 1 0.9308181999999999 1 0.9308181999999999 2 0.550304075} PREDS {{146 0 0-6668 {}} {259 0 0-6859 {}}} SUCCS {{259 0 0-6965 {}}} CYCLES {}}
+set a(0-6861) {NAME slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-6517 XREFS 42658 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.6843317999999999} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}}} SUCCS {{258 0 0-6871 {}}} CYCLES {}}
+set a(0-6862) {NAME slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-6517 XREFS 42659 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.667925025} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}}} SUCCS {{258 0 0-6866 {}}} CYCLES {}}
+set a(0-6863) {NAME slc(i#6.lpi#1.dfm)#2 TYPE READSLICE PAR 0-6517 XREFS 42660 LOC {1 0.016406775 1 0.607678775 1 0.607678775 3 1.0} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}}} SUCCS {} CYCLES {}}
+set a(0-6864) {NAME slc(i#6.lpi#1.dfm)#3 TYPE READSLICE PAR 0-6517 XREFS 42661 LOC {1 0.016406775 1 0.607678775 1 0.607678775 3 1.0} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}}} SUCCS {} CYCLES {}}
+set a(0-6865) {NAME FRAME:for:slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-6517 XREFS 42662 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.667925025} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}}} SUCCS {{258 0 0-6867 {}}} CYCLES {}}
+set a(0-6866) {NAME FRAME:for:not#1 TYPE NOT PAR 0-6517 XREFS 42663 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.667925025} PREDS {{146 0 0-6592 {}} {258 0 0-6862 {}}} SUCCS {{259 0 0-6867 {}}} CYCLES {}}
+set a(0-6867) {NAME FRAME:for:nand#2 TYPE NAND PAR 0-6517 XREFS 42664 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.667925025} PREDS {{146 0 0-6592 {}} {258 0 0-6865 {}} {259 0 0-6866 {}}} SUCCS {{259 0 0-6868 {}}} CYCLES {}}
+set a(0-6868) {NAME FRAME:for:exs#31 TYPE SIGNEXTEND PAR 0-6517 XREFS 42665 LOC {1 0.016406775 1 0.644864425 1 0.644864425 2 0.667925025} PREDS {{146 0 0-6592 {}} {259 0 0-6867 {}}} SUCCS {{259 0 0-6869 {}}} CYCLES {}}
+set a(0-6869) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 6 NAME FRAME:for:and#16 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42666 LOC {1 0.016406775 1 0.644864425 1 0.644864425 1 0.6612711562638539 2 0.6843317562638539} PREDS {{146 0 0-6592 {}} {259 0 0-6868 {}}} SUCCS {{258 0 0-6873 {}}} CYCLES {}}
+set a(0-6870) {NAME FRAME:for:slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-6517 XREFS 42667 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.6843317999999999} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}}} SUCCS {{259 0 0-6871 {}}} CYCLES {}}
+set a(0-6871) {NAME FRAME:for:nor TYPE NOR PAR 0-6517 XREFS 42668 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.6843317999999999} PREDS {{146 0 0-6592 {}} {258 0 0-6861 {}} {259 0 0-6870 {}}} SUCCS {{259 0 0-6872 {}}} CYCLES {}}
+set a(0-6872) {NAME FRAME:for:exs#32 TYPE SIGNEXTEND PAR 0-6517 XREFS 42669 LOC {1 0.016406775 1 0.6612712 1 0.6612712 2 0.6843317999999999} PREDS {{146 0 0-6592 {}} {259 0 0-6871 {}}} SUCCS {{259 0 0-6873 {}}} CYCLES {}}
+set a(0-6873) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(2,2) AREA_SCORE 1.46 QUANTITY 4 NAME FRAME:for:or TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-6517 XREFS 42670 LOC {1 0.03281355 1 0.6612712 1 0.6612712 1 0.6780136311077388 2 0.7010742311077388} PREDS {{146 0 0-6592 {}} {258 0 0-6869 {}} {259 0 0-6872 {}}} SUCCS {{258 0 0-6878 {}} {258 0 0-6884 {}} {258 0 0-6890 {}}} CYCLES {}}
+set a(0-6874) {NAME {regs.operator[]#18:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42671 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6877 {}}} CYCLES {}}
+set a(0-6875) {NAME {regs.operator[]#18:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42672 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6877 {}}} CYCLES {}}
+set a(0-6876) {NAME {regs.operator[]#18:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42673 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6877 {}}} CYCLES {}}
+set a(0-6877) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#18:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42674 LOC {1 0.0230606 1 0.619485875 1 0.619485875 1 0.678013625 2 0.7010742249999999} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}} {258 0 0-6875 {}} {258 0 0-6874 {}} {259 0 0-6876 {}}} SUCCS {{259 0 0-6878 {}}} CYCLES {}}
+set a(0-6878) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42675 LOC {1 0.08158839999999999 1 0.678013675 1 0.678013675 1 0.8709375374999999 2 0.8939981374999999} PREDS {{146 0 0-6592 {}} {258 0 0-6873 {}} {259 0 0-6877 {}}} SUCCS {{259 0 0-6879 {}}} CYCLES {}}
+set a(0-6879) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for:acc#1 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6517 XREFS 42676 LOC {1 0.274512325 1 0.8709376 1 0.8709376 1 0.9769393413378799 2 0.9999999413378798} PREDS {{146 0 0-6592 {}} {258 0 0-6560 {}} {259 0 0-6878 {}}} SUCCS {{258 0 0-6974 {}}} CYCLES {}}
+set a(0-6880) {NAME {regs.operator[]#19:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42677 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6883 {}}} CYCLES {}}
+set a(0-6881) {NAME {regs.operator[]#19:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42678 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6883 {}}} CYCLES {}}
+set a(0-6882) {NAME {regs.operator[]#19:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42679 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6883 {}}} CYCLES {}}
+set a(0-6883) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#19:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42680 LOC {1 0.0230606 1 0.619485875 1 0.619485875 1 0.678013625 2 0.7010742249999999} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}} {258 0 0-6881 {}} {258 0 0-6880 {}} {259 0 0-6882 {}}} SUCCS {{259 0 0-6884 {}}} CYCLES {}}
+set a(0-6884) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#1 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42681 LOC {1 0.08158839999999999 1 0.678013675 1 0.678013675 1 0.8709375374999999 2 0.8939981374999999} PREDS {{146 0 0-6592 {}} {258 0 0-6873 {}} {259 0 0-6883 {}}} SUCCS {{259 0 0-6885 {}}} CYCLES {}}
+set a(0-6885) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for:acc#2 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6517 XREFS 42682 LOC {1 0.274512325 1 0.8709376 1 0.8709376 1 0.9769393413378799 2 0.9999999413378798} PREDS {{146 0 0-6592 {}} {258 0 0-6566 {}} {259 0 0-6884 {}}} SUCCS {{258 0 0-6976 {}}} CYCLES {}}
+set a(0-6886) {NAME {regs.operator[]#20:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42683 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6889 {}}} CYCLES {}}
+set a(0-6887) {NAME {regs.operator[]#20:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42684 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6889 {}}} CYCLES {}}
+set a(0-6888) {NAME {regs.operator[]#20:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42685 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6889 {}}} CYCLES {}}
+set a(0-6889) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#20:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42686 LOC {1 0.0230606 1 0.619485875 1 0.619485875 1 0.678013625 2 0.7010742249999999} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}} {258 0 0-6887 {}} {258 0 0-6886 {}} {259 0 0-6888 {}}} SUCCS {{259 0 0-6890 {}}} CYCLES {}}
+set a(0-6890) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#2 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42687 LOC {1 0.08158839999999999 1 0.678013675 1 0.678013675 1 0.8709375374999999 2 0.8939981374999999} PREDS {{146 0 0-6592 {}} {258 0 0-6873 {}} {259 0 0-6889 {}}} SUCCS {{259 0 0-6891 {}}} CYCLES {}}
+set a(0-6891) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for:acc#3 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6517 XREFS 42688 LOC {1 0.274512325 1 0.8709376 1 0.8709376 1 0.9769393413378799 2 0.9999999413378798} PREDS {{146 0 0-6592 {}} {258 0 0-6572 {}} {259 0 0-6890 {}}} SUCCS {{258 0 0-6978 {}}} CYCLES {}}
+set a(0-6892) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,1,1,2) AREA_SCORE 3.00 QUANTITY 1 NAME FRAME:for:acc#5 TYPE ACCU DELAY {0.66 ns} LIBRARY_DELAY {0.66 ns} PAR 0-6517 XREFS 42689 LOC {1 0.016406775 1 0.607678775 1 0.607678775 1 0.6487862160227986 2 0.6718468160227986} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}}} SUCCS {{259 0 0-6893 {}} {258 0 0-6894 {}} {258 0 0-6898 {}} {258 0 0-6899 {}}} CYCLES {}}
+set a(0-6893) {NAME FRAME:for:slc(FRAME:for:acc#5.tmp) TYPE READSLICE PAR 0-6517 XREFS 42690 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.671846875} PREDS {{146 0 0-6592 {}} {259 0 0-6892 {}}} SUCCS {{258 0 0-6895 {}}} CYCLES {}}
+set a(0-6894) {NAME FRAME:for:slc(FRAME:for:acc#5.tmp)#1 TYPE READSLICE PAR 0-6517 XREFS 42691 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.671846875} PREDS {{146 0 0-6592 {}} {258 0 0-6892 {}}} SUCCS {{259 0 0-6895 {}}} CYCLES {}}
+set a(0-6895) {NAME FRAME:for:or#3 TYPE OR PAR 0-6517 XREFS 42692 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.671846875} PREDS {{146 0 0-6592 {}} {258 0 0-6893 {}} {259 0 0-6894 {}}} SUCCS {{259 0 0-6896 {}}} CYCLES {}}
+set a(0-6896) {NAME FRAME:for:exs#33 TYPE SIGNEXTEND PAR 0-6517 XREFS 42693 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.671846875} PREDS {{146 0 0-6592 {}} {259 0 0-6895 {}}} SUCCS {{259 0 0-6897 {}}} CYCLES {}}
+set a(0-6897) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 6 NAME FRAME:for:and#17 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42694 LOC {1 0.057514275 1 0.648786275 1 0.648786275 1 0.6651930062638539 2 0.6882536062638539} PREDS {{146 0 0-6592 {}} {259 0 0-6896 {}}} SUCCS {{258 0 0-6902 {}}} CYCLES {}}
+set a(0-6898) {NAME FRAME:for:slc(FRAME:for:acc#5.tmp)#2 TYPE READSLICE PAR 0-6517 XREFS 42695 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.6882536499999999} PREDS {{146 0 0-6592 {}} {258 0 0-6892 {}}} SUCCS {{258 0 0-6900 {}}} CYCLES {}}
+set a(0-6899) {NAME FRAME:for:slc(FRAME:for:acc#5.tmp)#3 TYPE READSLICE PAR 0-6517 XREFS 42696 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.6882536499999999} PREDS {{146 0 0-6592 {}} {258 0 0-6892 {}}} SUCCS {{259 0 0-6900 {}}} CYCLES {}}
+set a(0-6900) {NAME FRAME:for:and#18 TYPE AND PAR 0-6517 XREFS 42697 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.6882536499999999} PREDS {{146 0 0-6592 {}} {258 0 0-6898 {}} {259 0 0-6899 {}}} SUCCS {{259 0 0-6901 {}}} CYCLES {}}
+set a(0-6901) {NAME FRAME:for:exs#34 TYPE SIGNEXTEND PAR 0-6517 XREFS 42698 LOC {1 0.057514275 1 0.66519305 1 0.66519305 2 0.6882536499999999} PREDS {{146 0 0-6592 {}} {259 0 0-6900 {}}} SUCCS {{259 0 0-6902 {}}} CYCLES {}}
+set a(0-6902) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(2,2) AREA_SCORE 1.46 QUANTITY 4 NAME FRAME:for:or#2 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-6517 XREFS 42699 LOC {1 0.07392105 1 0.66519305 1 0.66519305 1 0.6819354811077388 2 0.7049960811077388} PREDS {{146 0 0-6592 {}} {258 0 0-6897 {}} {259 0 0-6901 {}}} SUCCS {{258 0 0-6907 {}} {258 0 0-6913 {}} {258 0 0-6919 {}}} CYCLES {}}
+set a(0-6903) {NAME {regs.operator[]#21:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42700 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6906 {}}} CYCLES {}}
+set a(0-6904) {NAME {regs.operator[]#21:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42701 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6906 {}}} CYCLES {}}
+set a(0-6905) {NAME {regs.operator[]#21:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42702 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6906 {}}} CYCLES {}}
+set a(0-6906) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#21:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42703 LOC {1 0.0230606 1 0.623407725 1 0.623407725 1 0.681935475 2 0.7049960749999999} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}} {258 0 0-6904 {}} {258 0 0-6903 {}} {259 0 0-6905 {}}} SUCCS {{259 0 0-6907 {}}} CYCLES {}}
+set a(0-6907) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#3 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42704 LOC {1 0.090663525 1 0.681935525 1 0.681935525 1 0.8748593874999999 2 0.8979199874999999} PREDS {{146 0 0-6592 {}} {258 0 0-6902 {}} {259 0 0-6906 {}}} SUCCS {{259 0 0-6908 {}}} CYCLES {}}
+set a(0-6908) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(15,0,11,1,15) AREA_SCORE 16.00 QUANTITY 3 NAME FRAME:for:acc#26 TYPE ACCU DELAY {1.63 ns} LIBRARY_DELAY {1.63 ns} PAR 0-6517 XREFS 42705 LOC {1 0.28358744999999996 1 0.87485945 1 0.87485945 1 0.9769393423306529 2 0.9999999423306529} PREDS {{146 0 0-6592 {}} {258 0 0-6581 {}} {259 0 0-6907 {}}} SUCCS {{258 0 0-6984 {}}} CYCLES {}}
+set a(0-6909) {NAME {regs.operator[]#22:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42706 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6912 {}}} CYCLES {}}
+set a(0-6910) {NAME {regs.operator[]#22:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42707 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6912 {}}} CYCLES {}}
+set a(0-6911) {NAME {regs.operator[]#22:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42708 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6912 {}}} CYCLES {}}
+set a(0-6912) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#22:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42709 LOC {1 0.0230606 1 0.623407725 1 0.623407725 1 0.681935475 2 0.7049960749999999} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}} {258 0 0-6910 {}} {258 0 0-6909 {}} {259 0 0-6911 {}}} SUCCS {{259 0 0-6913 {}}} CYCLES {}}
+set a(0-6913) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#4 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42710 LOC {1 0.090663525 1 0.681935525 1 0.681935525 1 0.8748593874999999 2 0.8979199874999999} PREDS {{146 0 0-6592 {}} {258 0 0-6902 {}} {259 0 0-6912 {}}} SUCCS {{259 0 0-6914 {}}} CYCLES {}}
+set a(0-6914) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(15,0,11,1,15) AREA_SCORE 16.00 QUANTITY 3 NAME FRAME:for:acc#27 TYPE ACCU DELAY {1.63 ns} LIBRARY_DELAY {1.63 ns} PAR 0-6517 XREFS 42711 LOC {1 0.28358744999999996 1 0.87485945 1 0.87485945 1 0.9769393423306529 2 0.9999999423306529} PREDS {{146 0 0-6592 {}} {258 0 0-6584 {}} {259 0 0-6913 {}}} SUCCS {{258 0 0-6985 {}}} CYCLES {}}
+set a(0-6915) {NAME {regs.operator[]#23:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42712 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6918 {}}} CYCLES {}}
+set a(0-6916) {NAME {regs.operator[]#23:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42713 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6918 {}}} CYCLES {}}
+set a(0-6917) {NAME {regs.operator[]#23:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42714 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6918 {}}} CYCLES {}}
+set a(0-6918) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#23:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42715 LOC {1 0.0230606 1 0.623407725 1 0.623407725 1 0.681935475 2 0.7049960749999999} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}} {258 0 0-6916 {}} {258 0 0-6915 {}} {259 0 0-6917 {}}} SUCCS {{259 0 0-6919 {}}} CYCLES {}}
+set a(0-6919) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#5 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42716 LOC {1 0.090663525 1 0.681935525 1 0.681935525 1 0.8748593874999999 2 0.8979199874999999} PREDS {{146 0 0-6592 {}} {258 0 0-6902 {}} {259 0 0-6918 {}}} SUCCS {{259 0 0-6920 {}}} CYCLES {}}
+set a(0-6920) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(15,0,11,1,15) AREA_SCORE 16.00 QUANTITY 3 NAME FRAME:for:acc#28 TYPE ACCU DELAY {1.63 ns} LIBRARY_DELAY {1.63 ns} PAR 0-6517 XREFS 42717 LOC {1 0.28358744999999996 1 0.87485945 1 0.87485945 1 0.9769393423306529 2 0.9999999423306529} PREDS {{146 0 0-6592 {}} {258 0 0-6587 {}} {259 0 0-6919 {}}} SUCCS {{258 0 0-6986 {}}} CYCLES {}}
+set a(0-6921) {NAME i:slc(i#3)#1 TYPE READSLICE PAR 0-6517 XREFS 42718 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}}} SUCCS {{259 0 0-6922 {}}} CYCLES {}}
+set a(0-6922) {NAME FRAME:for:not#3 TYPE NOT PAR 0-6517 XREFS 42719 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6592 {}} {259 0 0-6921 {}}} SUCCS {{258 0 0-6924 {}}} CYCLES {}}
+set a(0-6923) {NAME i:slc(i#3)#2 TYPE READSLICE PAR 0-6517 XREFS 42720 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}}} SUCCS {{259 0 0-6924 {}}} CYCLES {}}
+set a(0-6924) {NAME FRAME:for:conc TYPE CONCATENATE PAR 0-6517 XREFS 42721 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6592 {}} {258 0 0-6922 {}} {259 0 0-6923 {}}} SUCCS {{259 0 0-6925 {}} {258 0 0-6926 {}} {258 0 0-6927 {}} {258 0 0-6928 {}} {258 0 0-6929 {}} {258 0 0-6933 {}}} CYCLES {}}
+set a(0-6925) {NAME slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-6517 XREFS 42722 LOC {1 0.016406775 1 0.607678775 1 0.607678775 3 1.0} PREDS {{146 0 0-6592 {}} {259 0 0-6924 {}}} SUCCS {} CYCLES {}}
+set a(0-6926) {NAME slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-6517 XREFS 42723 LOC {1 0.016406775 1 0.607678775 1 0.607678775 3 1.0} PREDS {{146 0 0-6592 {}} {258 0 0-6924 {}}} SUCCS {} CYCLES {}}
+set a(0-6927) {NAME slc(FRAME:for:conc.tmp)#2 TYPE READSLICE PAR 0-6517 XREFS 42724 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5388626249999999} PREDS {{146 0 0-6592 {}} {258 0 0-6924 {}}} SUCCS {{258 0 0-6935 {}}} CYCLES {}}
+set a(0-6928) {NAME slc(FRAME:for:conc.tmp)#3 TYPE READSLICE PAR 0-6517 XREFS 42725 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6592 {}} {258 0 0-6924 {}}} SUCCS {{258 0 0-6930 {}}} CYCLES {}}
+set a(0-6929) {NAME FRAME:for:slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-6517 XREFS 42726 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6592 {}} {258 0 0-6924 {}}} SUCCS {{259 0 0-6930 {}}} CYCLES {}}
+set a(0-6930) {NAME FRAME:for:nand#3 TYPE NAND PAR 0-6517 XREFS 42727 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6592 {}} {258 0 0-6928 {}} {259 0 0-6929 {}}} SUCCS {{259 0 0-6931 {}}} CYCLES {}}
+set a(0-6931) {NAME FRAME:for:exs#35 TYPE SIGNEXTEND PAR 0-6517 XREFS 42728 LOC {1 0.016406775 1 0.644864425 1 0.644864425 2 0.5224558499999999} PREDS {{146 0 0-6592 {}} {259 0 0-6930 {}}} SUCCS {{259 0 0-6932 {}}} CYCLES {}}
+set a(0-6932) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 6 NAME FRAME:for:and#19 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42729 LOC {1 0.016406775 1 0.644864425 1 0.644864425 1 0.6612711562638539 2 0.5388625812638539} PREDS {{146 0 0-6592 {}} {259 0 0-6931 {}}} SUCCS {{258 0 0-6937 {}}} CYCLES {}}
+set a(0-6933) {NAME FRAME:for:slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-6517 XREFS 42730 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5388626249999999} PREDS {{146 0 0-6592 {}} {258 0 0-6924 {}}} SUCCS {{259 0 0-6934 {}}} CYCLES {}}
+set a(0-6934) {NAME FRAME:for:not#2 TYPE NOT PAR 0-6517 XREFS 42731 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5388626249999999} PREDS {{146 0 0-6592 {}} {259 0 0-6933 {}}} SUCCS {{259 0 0-6935 {}}} CYCLES {}}
+set a(0-6935) {NAME FRAME:for:and#20 TYPE AND PAR 0-6517 XREFS 42732 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5388626249999999} PREDS {{146 0 0-6592 {}} {258 0 0-6927 {}} {259 0 0-6934 {}}} SUCCS {{259 0 0-6936 {}}} CYCLES {}}
+set a(0-6936) {NAME FRAME:for:exs#36 TYPE SIGNEXTEND PAR 0-6517 XREFS 42733 LOC {1 0.016406775 1 0.6612712 1 0.6612712 2 0.5388626249999999} PREDS {{146 0 0-6592 {}} {259 0 0-6935 {}}} SUCCS {{259 0 0-6937 {}}} CYCLES {}}
+set a(0-6937) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(2,2) AREA_SCORE 1.46 QUANTITY 4 NAME FRAME:for:or#4 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-6517 XREFS 42734 LOC {1 0.03281355 1 0.6612712 1 0.6612712 1 0.6780136311077388 2 0.5556050561077388} PREDS {{146 0 0-6592 {}} {258 0 0-6932 {}} {259 0 0-6936 {}}} SUCCS {{258 0 0-6942 {}} {258 0 0-6948 {}} {258 0 0-6954 {}}} CYCLES {}}
+set a(0-6938) {NAME {regs.operator[]#24:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42735 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.619485875} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6941 {}}} CYCLES {}}
+set a(0-6939) {NAME {regs.operator[]#24:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42736 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.619485875} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6941 {}}} CYCLES {}}
+set a(0-6940) {NAME {regs.operator[]#24:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42737 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.619485875} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6941 {}}} CYCLES {}}
+set a(0-6941) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#24:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42738 LOC {1 0.0230606 1 0.619485875 1 0.619485875 1 0.678013625 2 0.678013625} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}} {258 0 0-6939 {}} {258 0 0-6938 {}} {259 0 0-6940 {}}} SUCCS {{259 0 0-6942 {}}} CYCLES {}}
+set a(0-6942) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#6 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42739 LOC {1 0.08158839999999999 1 0.678013675 1 0.678013675 1 0.8709375374999999 2 0.8709375374999999} PREDS {{146 0 0-6592 {}} {258 0 0-6937 {}} {259 0 0-6941 {}}} SUCCS {{259 0 0-6943 {}}} CYCLES {}}
+set a(0-6943) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for:acc#10 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6517 XREFS 42740 LOC {1 0.274512325 1 0.8709376 1 0.8709376 1 0.9769393413378799 2 0.9769393413378799} PREDS {{146 0 0-6592 {}} {258 0 0-6563 {}} {259 0 0-6942 {}}} SUCCS {{258 0 0-6975 {}}} CYCLES {}}
+set a(0-6944) {NAME {regs.operator[]#25:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42741 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.4970773} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6947 {}}} CYCLES {}}
+set a(0-6945) {NAME {regs.operator[]#25:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42742 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.4970773} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6947 {}}} CYCLES {}}
+set a(0-6946) {NAME {regs.operator[]#25:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42743 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.4970773} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6947 {}}} CYCLES {}}
+set a(0-6947) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#25:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42744 LOC {1 0.0230606 1 0.619485875 1 0.619485875 1 0.678013625 2 0.55560505} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}} {258 0 0-6945 {}} {258 0 0-6944 {}} {259 0 0-6946 {}}} SUCCS {{259 0 0-6948 {}}} CYCLES {}}
+set a(0-6948) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#7 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42745 LOC {1 0.08158839999999999 1 0.678013675 1 0.678013675 1 0.8709375374999999 2 0.7485289625} PREDS {{146 0 0-6592 {}} {258 0 0-6937 {}} {259 0 0-6947 {}}} SUCCS {{259 0 0-6949 {}}} CYCLES {}}
+set a(0-6949) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for:acc#12 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6517 XREFS 42746 LOC {1 0.274512325 1 0.8709376 1 0.8709376 1 0.9769393413378799 2 0.8545307663378798} PREDS {{146 0 0-6592 {}} {258 0 0-6569 {}} {259 0 0-6948 {}}} SUCCS {{258 0 0-6977 {}}} CYCLES {}}
+set a(0-6950) {NAME {regs.operator[]#26:slc(regs.regs(2))} TYPE READSLICE PAR 0-6517 XREFS 42747 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.4970773} PREDS {{146 0 0-6592 {}} {258 0 0-6557 {}}} SUCCS {{258 0 0-6953 {}}} CYCLES {}}
+set a(0-6951) {NAME {regs.operator[]#26:slc(regs.regs(1))} TYPE READSLICE PAR 0-6517 XREFS 42748 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.4970773} PREDS {{146 0 0-6592 {}} {258 0 0-6555 {}}} SUCCS {{258 0 0-6953 {}}} CYCLES {}}
+set a(0-6952) {NAME {regs.operator[]#26:slc(regs.regs(0))} TYPE READSLICE PAR 0-6517 XREFS 42749 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.4970773} PREDS {{146 0 0-6592 {}} {258 0 0-6552 {}}} SUCCS {{259 0 0-6953 {}}} CYCLES {}}
+set a(0-6953) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#26:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6517 XREFS 42750 LOC {1 0.0230606 1 0.619485875 1 0.619485875 1 0.678013625 2 0.55560505} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}} {258 0 0-6951 {}} {258 0 0-6950 {}} {259 0 0-6952 {}}} SUCCS {{259 0 0-6954 {}}} CYCLES {}}
+set a(0-6954) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#8 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6517 XREFS 42751 LOC {1 0.08158839999999999 1 0.678013675 1 0.678013675 1 0.8709375374999999 2 0.7485289625} PREDS {{146 0 0-6592 {}} {258 0 0-6937 {}} {259 0 0-6953 {}}} SUCCS {{259 0 0-6955 {}}} CYCLES {}}
+set a(0-6955) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for:acc#14 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6517 XREFS 42752 LOC {1 0.274512325 1 0.8709376 1 0.8709376 1 0.9769393413378799 2 0.8545307663378798} PREDS {{146 0 0-6592 {}} {258 0 0-6575 {}} {259 0 0-6954 {}}} SUCCS {{258 0 0-6979 {}}} CYCLES {}}
+set a(0-6956) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,2) AREA_SCORE 3.31 QUANTITY 2 NAME FRAME:for:acc#16 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-6517 XREFS 42753 LOC {1 0.016406775 1 0.8721934 1 0.8721934 1 0.9129764100894753 2 0.5555228850894752} PREDS {{146 0 0-6592 {}} {258 0 0-6578 {}}} SUCCS {{259 0 0-6957 {}} {258 0 0-6982 {}}} CYCLES {}}
+set a(0-6957) {NAME FRAME:for:asn#3 TYPE ASSIGN PAR 0-6517 XREFS 42754 LOC {1 0.057189825 1 0.9129764499999999 1 0.9129764499999999 2 0.555522925} PREDS {{146 0 0-6592 {}} {259 0 0-6956 {}}} SUCCS {{259 0 0-6958 {}}} CYCLES {}}
+set a(0-6958) {NAME FRAME:for:conc#16 TYPE CONCATENATE PAR 0-6517 XREFS 42755 LOC {1 0.057189825 1 0.9129764499999999 1 0.9129764499999999 2 0.555522925} PREDS {{146 0 0-6592 {}} {259 0 0-6957 {}}} SUCCS {{259 0 0-6959 {}}} CYCLES {}}
+set a(0-6959) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,3) AREA_SCORE 4.30 QUANTITY 2 NAME FRAME:for:acc TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6517 XREFS 42756 LOC {1 0.057189825 1 0.9129764499999999 1 0.9129764499999999 1 0.9605325770708271 2 0.6030790520708271} PREDS {{146 0 0-6592 {}} {259 0 0-6958 {}}} SUCCS {{259 0 0-6960 {}}} CYCLES {}}
+set a(0-6960) {NAME FRAME:for:slc TYPE READSLICE PAR 0-6517 XREFS 42757 LOC {1 0.10474599999999999 1 0.9605326249999999 1 0.9605326249999999 2 0.6030791} PREDS {{146 0 0-6592 {}} {259 0 0-6959 {}}} SUCCS {{259 0 0-6961 {}}} CYCLES {}}
+set a(0-6961) {NAME FRAME:for:not TYPE NOT PAR 0-6517 XREFS 42758 LOC {1 0.10474599999999999 1 0.9605326249999999 1 0.9605326249999999 2 0.6030791} PREDS {{146 0 0-6592 {}} {259 0 0-6960 {}}} SUCCS {{259 0 0-6962 {}} {258 0 0-6989 {}}} CYCLES {}}
+set a(0-6962) {NAME not#4 TYPE NOT PAR 0-6517 XREFS 42759 LOC {1 0.10474599999999999 1 0.9605326249999999 1 0.9605326249999999 2 0.6030791} PREDS {{146 0 0-6592 {}} {259 0 0-6961 {}}} SUCCS {{259 0 0-6963 {}}} CYCLES {}}
+set a(0-6963) {NAME FRAME:for:exs#30 TYPE SIGNEXTEND PAR 0-6517 XREFS 42760 LOC {1 0.10474599999999999 1 0.9605326249999999 1 0.9605326249999999 2 0.6030791} PREDS {{146 0 0-6592 {}} {259 0 0-6962 {}}} SUCCS {{259 0 0-6964 {}}} CYCLES {}}
+set a(0-6964) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 6 NAME FRAME:for:and#13 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6517 XREFS 42761 LOC {1 0.10474599999999999 1 0.9605326249999999 1 0.9605326249999999 1 0.9769393562638539 2 0.6194858312638539} PREDS {{146 0 0-6592 {}} {262 0 0-6983 {}} {259 0 0-6963 {}}} SUCCS {{258 0 0-6983 {}}} CYCLES {}}
+set a(0-6965) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 4 NAME FRAME:for#1:mux#9 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42762 LOC {1 0.2804138 1 0.9308181999999999 1 0.9308181999999999 1 0.9538787624999999 2 0.5733646375} PREDS {{258 0 0-6667 {}} {258 0 0-6532 {}} {258 0 0-6589 {}} {258 0 0-6530 {}} {259 0 0-6860 {}}} SUCCS {{259 0 0-6966 {}}} CYCLES {}}
+set a(0-6966) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 4 NAME FRAME:for:mux#42 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42763 LOC {1 0.3034744 1 0.9538787999999999 1 0.9538787999999999 1 0.9769393624999999 2 0.5964252375} PREDS {{258 0 0-6591 {}} {258 0 0-6589 {}} {259 0 0-6965 {}}} SUCCS {{258 0 0-6968 {}} {258 0 0-6987 {}} {258 0 0-6990 {}}} CYCLES {}}
+set a(0-6967) {NAME FRAME:for:and#15 TYPE AND PAR 0-6517 XREFS 42764 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.596425275} PREDS {{258 0 0-6591 {}} {258 0 0-6667 {}} {258 0 0-6532 {}}} SUCCS {{258 0 0-6969 {}} {258 0 0-6970 {}}} CYCLES {}}
+set a(0-6968) {NAME not#5 TYPE NOT PAR 0-6517 XREFS 42765 LOC {1 0.32653499999999996 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {{258 0 0-6966 {}}} SUCCS {{259 0 0-6969 {}}} CYCLES {}}
+set a(0-6969) {NAME FRAME:for:or#1 TYPE OR PAR 0-6517 XREFS 42766 LOC {1 0.32653499999999996 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {{258 0 0-6967 {}} {259 0 0-6968 {}}} SUCCS {{259 0 0-6970 {}}} CYCLES {}}
+set a(0-6970) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 4 NAME FRAME:for:mux#46 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42767 LOC {1 0.32653499999999996 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.6194858375} PREDS {{258 0 0-6967 {}} {259 0 0-6969 {}}} SUCCS {{258 0 0-6988 {}} {258 0 0-6990 {}}} CYCLES {}}
+set a(0-6971) {NAME asn(regs.regs(0).sva) TYPE ASSIGN PAR 0-6517 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.619485875} PREDS {{260 0 0-6971 {}} {256 0 0-6551 {}} {256 0 0-6553 {}} {258 0 0-6552 {}}} SUCCS {{262 0 0-6551 {}} {262 0 0-6553 {}} {260 0 0-6971 {}}} CYCLES {}}
+set a(0-6972) {NAME asn(regs.regs(1).sva) TYPE ASSIGN PAR 0-6517 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.619485875} PREDS {{260 0 0-6972 {}} {256 0 0-6554 {}} {256 0 0-6556 {}} {258 0 0-6555 {}}} SUCCS {{262 0 0-6554 {}} {262 0 0-6556 {}} {260 0 0-6972 {}}} CYCLES {}}
+set a(0-6973) {NAME asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-6517 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.619485875} PREDS {{260 0 0-6973 {}} {258 0 0-6557 {}}} SUCCS {{262 0 0-6557 {}} {260 0 0-6973 {}}} CYCLES {}}
+set a(0-6974) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#20 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42768 LOC {1 0.380514125 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.12226053749999999} PREDS {{260 0 0-6974 {}} {256 0 0-6560 {}} {258 0 0-6591 {}} {258 0 0-6529 {}} {258 0 0-6879 {}} {258 0 0-6612 {}} {258 0 0-6539 {}}} SUCCS {{262 0 0-6560 {}} {260 0 0-6974 {}}} CYCLES {}}
+set a(0-6975) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#21 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42769 LOC {1 0.380514125 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.9999999624999999} PREDS {{260 0 0-6975 {}} {256 0 0-6563 {}} {258 0 0-6591 {}} {258 0 0-6523 {}} {258 0 0-6943 {}} {258 0 0-6649 {}} {258 0 0-6536 {}}} SUCCS {{262 0 0-6563 {}} {260 0 0-6975 {}}} CYCLES {}}
+set a(0-6976) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#22 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42770 LOC {1 0.380514125 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.038375612499999996} PREDS {{260 0 0-6976 {}} {256 0 0-6566 {}} {258 0 0-6591 {}} {258 0 0-6528 {}} {258 0 0-6885 {}} {258 0 0-6619 {}} {258 0 0-6538 {}}} SUCCS {{262 0 0-6566 {}} {260 0 0-6976 {}}} CYCLES {}}
+set a(0-6977) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#23 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42771 LOC {1 0.380514125 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.8775913875} PREDS {{260 0 0-6977 {}} {256 0 0-6569 {}} {258 0 0-6591 {}} {258 0 0-6522 {}} {258 0 0-6949 {}} {258 0 0-6655 {}} {258 0 0-6535 {}}} SUCCS {{262 0 0-6569 {}} {260 0 0-6977 {}}} CYCLES {}}
+set a(0-6978) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#24 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42772 LOC {1 0.380514125 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.038375612499999996} PREDS {{260 0 0-6978 {}} {256 0 0-6572 {}} {258 0 0-6591 {}} {258 0 0-6527 {}} {258 0 0-6891 {}} {258 0 0-6626 {}} {258 0 0-6537 {}}} SUCCS {{262 0 0-6572 {}} {260 0 0-6978 {}}} CYCLES {}}
+set a(0-6979) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#25 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42773 LOC {1 0.380514125 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.8775913875} PREDS {{260 0 0-6979 {}} {256 0 0-6575 {}} {258 0 0-6591 {}} {258 0 0-6521 {}} {258 0 0-6955 {}} {258 0 0-6661 {}} {258 0 0-6534 {}}} SUCCS {{262 0 0-6575 {}} {260 0 0-6979 {}}} CYCLES {}}
+set a(0-6980) {NAME FRAME:for:nand TYPE NAND PAR 0-6517 XREFS 42774 LOC {1 0.088339225 1 0.4061093 1 0.4061093 3 0.318762125} PREDS {{258 0 0-6591 {}} {258 0 0-6667 {}} {258 0 0-6532 {}}} SUCCS {{259 0 0-6981 {}}} CYCLES {}}
+set a(0-6981) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(19,1,2) AREA_SCORE 17.47 QUANTITY 1 NAME FRAME:for:mux#33 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42775 LOC {1 0.2075986 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.3418226875} PREDS {{260 0 0-6981 {}} {258 0 0-6856 {}} {258 0 0-6531 {}} {258 0 0-6546 {}} {259 0 0-6980 {}}} SUCCS {{262 0 0-6546 {}} {260 0 0-6981 {}}} CYCLES {}}
+set a(0-6982) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(2,1,2) AREA_SCORE 1.84 QUANTITY 2 NAME FRAME:for:mux#34 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42776 LOC {1 0.057189825 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.48067048749999997} PREDS {{260 0 0-6982 {}} {258 0 0-6591 {}} {258 0 0-6520 {}} {258 0 0-6956 {}} {258 0 0-6578 {}}} SUCCS {{262 0 0-6578 {}} {260 0 0-6982 {}}} CYCLES {}}
+set a(0-6983) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(2,1,2) AREA_SCORE 1.84 QUANTITY 2 NAME FRAME:for:mux#35 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42777 LOC {1 0.12115277499999999 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.6425464375} PREDS {{260 0 0-6983 {}} {256 0 0-6593 {}} {256 0 0-6594 {}} {256 0 0-6595 {}} {256 0 0-6596 {}} {256 0 0-6597 {}} {256 0 0-6600 {}} {256 0 0-6602 {}} {256 0 0-6609 {}} {256 0 0-6616 {}} {256 0 0-6623 {}} {256 0 0-6627 {}} {256 0 0-6629 {}} {256 0 0-6647 {}} {256 0 0-6653 {}} {256 0 0-6659 {}} {258 0 0-6591 {}} {258 0 0-6518 {}} {258 0 0-6964 {}} {258 0 0-6662 {}} {258 0 0-6533 {}}} SUCCS {{262 0 0-6593 {}} {262 0 0-6594 {}} {262 0 0-6595 {}} {262 0 0-6596 {}} {262 0 0-6597 {}} {262 0 0-6600 {}} {262 0 0-6602 {}} {262 0 0-6609 {}} {262 0 0-6616 {}} {262 0 0-6623 {}} {262 0 0-6627 {}} {262 0 0-6629 {}} {262 0 0-6647 {}} {262 0 0-6653 {}} {262 0 0-6659 {}} {262 0 0-6662 {}} {262 0 0-6964 {}} {260 0 0-6983 {}}} CYCLES {}}
+set a(0-6984) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(15,1,2) AREA_SCORE 13.79 QUANTITY 3 NAME FRAME:for:mux#39 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42778 LOC {1 0.3856674 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.1226525625} PREDS {{260 0 0-6984 {}} {258 0 0-6591 {}} {258 0 0-6526 {}} {258 0 0-6908 {}} {258 0 0-6581 {}}} SUCCS {{262 0 0-6581 {}} {260 0 0-6984 {}}} CYCLES {}}
+set a(0-6985) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(15,1,2) AREA_SCORE 13.79 QUANTITY 3 NAME FRAME:for:mux#40 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42779 LOC {1 0.3856674 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.0387676375} PREDS {{260 0 0-6985 {}} {258 0 0-6591 {}} {258 0 0-6525 {}} {258 0 0-6914 {}} {258 0 0-6584 {}}} SUCCS {{262 0 0-6584 {}} {260 0 0-6985 {}}} CYCLES {}}
+set a(0-6986) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(15,1,2) AREA_SCORE 13.79 QUANTITY 3 NAME FRAME:for:mux#41 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42780 LOC {1 0.3856674 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.0387676375} PREDS {{260 0 0-6986 {}} {258 0 0-6591 {}} {258 0 0-6524 {}} {258 0 0-6920 {}} {258 0 0-6587 {}}} SUCCS {{262 0 0-6587 {}} {260 0 0-6986 {}}} CYCLES {}}
+set a(0-6987) {NAME asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-6517 LOC {1 0.32653499999999996 1 0.9769393999999999 1 0.9769393999999999 3 0.550304075} PREDS {{260 0 0-6987 {}} {256 0 0-6589 {}} {258 0 0-6966 {}}} SUCCS {{262 0 0-6589 {}} {260 0 0-6987 {}}} CYCLES {}}
+set a(0-6988) {NAME asn(exit:FRAME:for#1.lpi#1) TYPE ASSIGN PAR 0-6517 LOC {1 0.3495956 1 1.0 1 1.0 2 0.619485875} PREDS {{260 0 0-6988 {}} {256 0 0-6548 {}} {258 0 0-6970 {}}} SUCCS {{262 0 0-6548 {}} {260 0 0-6988 {}}} CYCLES {}}
+set a(0-6989) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 4 NAME FRAME:for:mux#44 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6517 XREFS 42781 LOC {1 0.10474599999999999 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.6425464375} PREDS {{260 0 0-6989 {}} {258 0 0-6519 {}} {258 0 0-6961 {}} {258 0 0-6591 {}}} SUCCS {{262 0 0-6591 {}} {260 0 0-6989 {}}} CYCLES {}}
+set a(0-6990) {NAME FRAME:and TYPE AND PAR 0-6517 XREFS 42782 LOC {1 0.3495956 1 1.0 1 1.0 2 0.619485875} PREDS {{258 0 0-6966 {}} {258 0 0-6970 {}}} SUCCS {{259 0 0-6991 {}}} CYCLES {}}
+set a(0-6991) {NAME FRAME:asn#3 TYPE ASSIGN PAR 0-6517 XREFS 42783 LOC {1 0.3495956 1 1.0 1 1.0 2 0.619485875} PREDS {{260 0 0-6991 {}} {256 0 0-6541 {}} {256 0 0-6543 {}} {256 0 0-6547 {}} {259 0 0-6990 {}}} SUCCS {{262 0 0-6541 {}} {262 0 0-6543 {}} {262 0 0-6547 {}} {260 0 0-6991 {}}} CYCLES {}}
+set a(0-6517) {CHI {0-6518 0-6519 0-6520 0-6521 0-6522 0-6523 0-6524 0-6525 0-6526 0-6527 0-6528 0-6529 0-6530 0-6531 0-6532 0-6533 0-6534 0-6535 0-6536 0-6537 0-6538 0-6539 0-6540 0-6541 0-6542 0-6543 0-6544 0-6545 0-6546 0-6547 0-6548 0-6549 0-6550 0-6551 0-6552 0-6553 0-6554 0-6555 0-6556 0-6557 0-6558 0-6559 0-6560 0-6561 0-6562 0-6563 0-6564 0-6565 0-6566 0-6567 0-6568 0-6569 0-6570 0-6571 0-6572 0-6573 0-6574 0-6575 0-6576 0-6577 0-6578 0-6579 0-6580 0-6581 0-6582 0-6583 0-6584 0-6585 0-6586 0-6587 0-6588 0-6589 0-6590 0-6591 0-6592 0-6593 0-6594 0-6595 0-6596 0-6597 0-6598 0-6599 0-6600 0-6601 0-6602 0-6603 0-6604 0-6605 0-6606 0-6607 0-6608 0-6609 0-6610 0-6611 0-6612 0-6613 0-6614 0-6615 0-6616 0-6617 0-6618 0-6619 0-6620 0-6621 0-6622 0-6623 0-6624 0-6625 0-6626 0-6627 0-6628 0-6629 0-6630 0-6631 0-6632 0-6633 0-6634 0-6635 0-6636 0-6637 0-6638 0-6639 0-6640 0-6641 0-6642 0-6643 0-6644 0-6645 0-6646 0-6647 0-6648 0-6649 0-6650 0-6651 0-6652 0-6653 0-6654 0-6655 0-6656 0-6657 0-6658 0-6659 0-6660 0-6661 0-6662 0-6663 0-6664 0-6665 0-6666 0-6667 0-6668 0-6669 0-6670 0-6671 0-6672 0-6673 0-6674 0-6675 0-6676 0-6677 0-6678 0-6679 0-6680 0-6681 0-6682 0-6683 0-6684 0-6685 0-6686 0-6687 0-6688 0-6689 0-6690 0-6691 0-6692 0-6693 0-6694 0-6695 0-6696 0-6697 0-6698 0-6699 0-6700 0-6701 0-6702 0-6703 0-6704 0-6705 0-6706 0-6707 0-6708 0-6709 0-6710 0-6711 0-6712 0-6713 0-6714 0-6715 0-6716 0-6717 0-6718 0-6719 0-6720 0-6721 0-6722 0-6723 0-6724 0-6725 0-6726 0-6727 0-6728 0-6729 0-6730 0-6731 0-6732 0-6733 0-6734 0-6735 0-6736 0-6737 0-6738 0-6739 0-6740 0-6741 0-6742 0-6743 0-6744 0-6745 0-6746 0-6747 0-6748 0-6749 0-6750 0-6751 0-6752 0-6753 0-6754 0-6755 0-6756 0-6757 0-6758 0-6759 0-6760 0-6761 0-6762 0-6763 0-6764 0-6765 0-6766 0-6767 0-6768 0-6769 0-6770 0-6771 0-6772 0-6773 0-6774 0-6775 0-6776 0-6777 0-6778 0-6779 0-6780 0-6781 0-6782 0-6783 0-6784 0-6785 0-6786 0-6787 0-6788 0-6789 0-6790 0-6791 0-6792 0-6793 0-6794 0-6795 0-6796 0-6797 0-6798 0-6799 0-6800 0-6801 0-6802 0-6803 0-6804 0-6805 0-6806 0-6807 0-6808 0-6809 0-6810 0-6811 0-6812 0-6813 0-6814 0-6815 0-6816 0-6817 0-6818 0-6819 0-6820 0-6821 0-6822 0-6823 0-6824 0-6825 0-6826 0-6827 0-6828 0-6829 0-6830 0-6831 0-6832 0-6833 0-6834 0-6835 0-6836 0-6837 0-6838 0-6839 0-6840 0-6841 0-6842 0-6843 0-6844 0-6845 0-6846 0-6847 0-6848 0-6849 0-6850 0-6851 0-6852 0-6853 0-6854 0-6855 0-6856 0-6857 0-6858 0-6859 0-6860 0-6861 0-6862 0-6863 0-6864 0-6865 0-6866 0-6867 0-6868 0-6869 0-6870 0-6871 0-6872 0-6873 0-6874 0-6875 0-6876 0-6877 0-6878 0-6879 0-6880 0-6881 0-6882 0-6883 0-6884 0-6885 0-6886 0-6887 0-6888 0-6889 0-6890 0-6891 0-6892 0-6893 0-6894 0-6895 0-6896 0-6897 0-6898 0-6899 0-6900 0-6901 0-6902 0-6903 0-6904 0-6905 0-6906 0-6907 0-6908 0-6909 0-6910 0-6911 0-6912 0-6913 0-6914 0-6915 0-6916 0-6917 0-6918 0-6919 0-6920 0-6921 0-6922 0-6923 0-6924 0-6925 0-6926 0-6927 0-6928 0-6929 0-6930 0-6931 0-6932 0-6933 0-6934 0-6935 0-6936 0-6937 0-6938 0-6939 0-6940 0-6941 0-6942 0-6943 0-6944 0-6945 0-6946 0-6947 0-6948 0-6949 0-6950 0-6951 0-6952 0-6953 0-6954 0-6955 0-6956 0-6957 0-6958 0-6959 0-6960 0-6961 0-6962 0-6963 0-6964 0-6965 0-6966 0-6967 0-6968 0-6969 0-6970 0-6971 0-6972 0-6973 0-6974 0-6975 0-6976 0-6977 0-6978 0-6979 0-6980 0-6981 0-6982 0-6983 0-6984 0-6985 0-6986 0-6987 0-6988 0-6989 0-6990 0-6991} ITERATIONS Infinite LATENCY 1843201 RESET_LATENCY 0 CSTEPS 3 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 1843200 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 3.0 CYCLES_IN 1843202 TOTAL_CYCLES_IN 1843202 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 1843202 NAME main TYPE LOOP DELAY {36864060.00 ns} PAR 0-6497 XREFS 42784 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{258 0 0-6498 {}} {258 0 0-6499 {}} {258 0 0-6511 {}} {258 0 0-6510 {}} {258 0 0-6507 {}} {258 0 0-6504 {}} {258 0 0-6500 {}} {258 0 0-6508 {}} {258 0 0-6509 {}} {258 0 0-6505 {}} {258 0 0-6506 {}} {258 0 0-6502 {}} {258 0 0-6503 {}} {258 0 0-6501 {}} {258 0 0-6514 {}} {258 0 0-6515 {}} {258 0 0-6512 {}} {258 0 0-6513 {}} {259 0 0-6516 {}}} SUCCS {{772 0 0-6498 {}} {772 0 0-6499 {}} {772 0 0-6500 {}} {772 0 0-6501 {}} {772 0 0-6502 {}} {772 0 0-6503 {}} {772 0 0-6504 {}} {772 0 0-6505 {}} {772 0 0-6506 {}} {772 0 0-6507 {}} {772 0 0-6508 {}} {772 0 0-6509 {}} {772 0 0-6510 {}} {772 0 0-6511 {}} {772 0 0-6512 {}} {772 0 0-6513 {}} {772 0 0-6514 {}} {772 0 0-6515 {}} {772 0 0-6516 {}}} CYCLES {}}
+set a(0-6497) {CHI {0-6498 0-6499 0-6500 0-6501 0-6502 0-6503 0-6504 0-6505 0-6506 0-6507 0-6508 0-6509 0-6510 0-6511 0-6512 0-6513 0-6514 0-6515 0-6516 0-6517} ITERATIONS Infinite LATENCY 1843201 RESET_LATENCY 0 CSTEPS 0 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 1843200 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 0 TOTAL_CYCLES_IN 0 TOTAL_CYCLES_UNDER 1843202 TOTAL_CYCLES 1843202 NAME core:rlp TYPE LOOP DELAY {36864060.00 ns} PAR {} XREFS 42785 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-6497-TOTALCYCLES) {1843202}
+set a(0-6497-QMOD) {mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2) 0-6546 mgc_ioport.mgc_in_wire(1,90) 0-6550 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2) {0-6552 0-6555 0-6557} mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2) {0-6560 0-6563 0-6566 0-6569 0-6572 0-6575} mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2) {0-6578 0-6638 0-6869 0-6897 0-6932 0-6964} mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(15,2) {0-6581 0-6584 0-6587} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4) {0-6609 0-6616 0-6623 0-6647 0-6653 0-6659 0-6877 0-6883 0-6889 0-6906 0-6912 0-6918 0-6941 0-6947 0-6953} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12) {0-6611 0-6618 0-6625 0-6648 0-6654 0-6660 0-6878 0-6884 0-6890 0-6907 0-6913 0-6919 0-6942 0-6948 0-6954} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16) {0-6612 0-6619 0-6626 0-6649 0-6655 0-6661 0-6879 0-6885 0-6891 0-6943 0-6949 0-6955} mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(2,2) {0-6643 0-6873 0-6902 0-6937} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2) {0-6662 0-6956} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) {0-6665 0-6959} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16) {0-6670 0-6671 0-6674 0-6675 0-6678 0-6679} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4) {0-6684 0-6691 0-6696 0-6702 0-6709 0-6714 0-6737 0-6757 0-6764 0-6769 0-6792 0-6835} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5) {0-6692 0-6710 0-6740 0-6765 0-6795 0-6838} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6) {0-6697 0-6715 0-6770} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6) {0-6698 0-6716 0-6771} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11) {0-6718 0-6773 0-6810} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9) {0-6720 0-6775 0-6818} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5) {0-6731 0-6743 0-6786 0-6798 0-6829 0-6841} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8) {0-6744 0-6799 0-6842} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10) {0-6745 0-6800 0-6843} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12) {0-6746 0-6801} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,11,0,12) {0-6753 0-6808} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,9,1,10) 0-6816 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,10) 0-6844 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2) 0-6847 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2) 0-6852 mgc_ioport.mgc_out_stdreg(2,30) 0-6855 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19) 0-6856 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,7,0,8) 0-6858 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) 0-6892 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) {0-6908 0-6914 0-6920} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2) {0-6965 0-6966 0-6970 0-6989} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2) {0-6974 0-6975 0-6976 0-6977 0-6978 0-6979} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2) 0-6981 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2) {0-6982 0-6983} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(15,1,2) {0-6984 0-6985 0-6986}}
+set a(0-6497-PROC_NAME) {core}
+set a(0-6497-HIER_NAME) {/sobel/core}
+set a(TOP) {0-6497}
+
diff --git a/Sobel/sobel.v10/schematic.nlv b/Sobel/sobel.v10/schematic.nlv
new file mode 100644
index 0000000..1bbff8d
--- /dev/null
+++ b/Sobel/sobel.v10/schematic.nlv
@@ -0,0 +1,12161 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "sobel:core" "orig"
+load port {clk} input -attr xrf 44125 -attr oid 1 -attr vt d -attr @path {/sobel/sobel:core/clk}
+load port {en} input -attr xrf 44126 -attr oid 2 -attr vt d -attr @path {/sobel/sobel:core/en}
+load port {arst_n} input -attr xrf 44127 -attr oid 3 -attr vt d -attr @path {/sobel/sobel:core/arst_n}
+load portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} -attr xrf 44128 -attr oid 4 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} -attr xrf 44129 -attr oid 5 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load symbol "add(5,-1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,-1,10,-1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,10)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,6)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(5:0)} input 6 {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(5:0)} input 6 {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nand(3,1)" "INTERFACE" NAND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,30)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(29:0)} input 30 {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(29:0)} input 30 {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(30,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(29:0)} input 30 {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(29:0)} input 30 {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,1,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "reg(2,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(1:0)} input 2 {D(1)} {D(0)} \
+     portBus {DRa(1:0)} input 2 {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(6,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(5:0)} input 6 {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(5:0)} input 6 {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,6,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(9,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(8:0)} input 9 {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(8:0)} input 9 {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "not(3)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(5,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(4:0)} input 5 {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(4:0)} input 5 {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(1,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(0:0)} input 1 {D(0)} \
+     portBus {DRa(0:0)} input 1 {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mul(2,0,9,0,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(11,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(10:0)} input 11 {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(10:0)} input 11 {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,2)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(1:0)} input 2 {A0(1)} {A0(0)} \
+     portBus {A1(1:0)} input 2 {A1(1)} {A1(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "mux(2,2)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(1:0)} input 2 {A0(1)} {A0(0)} \
+     portBus {A1(1:0)} input 2 {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "mux(2,1)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "and(2,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "reg(90,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(89:0)} input 90 {D(89)} {D(88)} {D(87)} {D(86)} {D(85)} {D(84)} {D(83)} {D(82)} {D(81)} {D(80)} {D(79)} {D(78)} {D(77)} {D(76)} {D(75)} {D(74)} {D(73)} {D(72)} {D(71)} {D(70)} {D(69)} {D(68)} {D(67)} {D(66)} {D(65)} {D(64)} {D(63)} {D(62)} {D(61)} {D(60)} {D(59)} {D(58)} {D(57)} {D(56)} {D(55)} {D(54)} {D(53)} {D(52)} {D(51)} {D(50)} {D(49)} {D(48)} {D(47)} {D(46)} {D(45)} {D(44)} {D(43)} {D(42)} {D(41)} {D(40)} {D(39)} {D(38)} {D(37)} {D(36)} {D(35)} {D(34)} {D(33)} {D(32)} {D(31)} {D(30)} {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(89:0)} input 90 {DRa(89)} {DRa(88)} {DRa(87)} {DRa(86)} {DRa(85)} {DRa(84)} {DRa(83)} {DRa(82)} {DRa(81)} {DRa(80)} {DRa(79)} {DRa(78)} {DRa(77)} {DRa(76)} {DRa(75)} {DRa(74)} {DRa(73)} {DRa(72)} {DRa(71)} {DRa(70)} {DRa(69)} {DRa(68)} {DRa(67)} {DRa(66)} {DRa(65)} {DRa(64)} {DRa(63)} {DRa(62)} {DRa(61)} {DRa(60)} {DRa(59)} {DRa(58)} {DRa(57)} {DRa(56)} {DRa(55)} {DRa(54)} {DRa(53)} {DRa(52)} {DRa(51)} {DRa(50)} {DRa(49)} {DRa(48)} {DRa(47)} {DRa(46)} {DRa(45)} {DRa(44)} {DRa(43)} {DRa(42)} {DRa(41)} {DRa(40)} {DRa(39)} {DRa(38)} {DRa(37)} {DRa(36)} {DRa(35)} {DRa(34)} {DRa(33)} {DRa(32)} {DRa(31)} {DRa(30)} {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(4,10)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {A2(9:0)} input 10 {A2(9)} {A2(8)} {A2(7)} {A2(6)} {A2(5)} {A2(4)} {A2(3)} {A2(2)} {A2(1)} {A2(0)} \
+     portBus {A3(9:0)} input 10 {A3(9)} {A3(8)} {A3(7)} {A3(6)} {A3(5)} {A3(4)} {A3(3)} {A3(2)} {A3(1)} {A3(0)} \
+     portBus {S(1:0)} input.top 2 {S(1)} {S(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(15,-1,11,1,15)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(14:0)} input 15 {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,15)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(14:0)} input 15 {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(14:0)} input 15 {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(15,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(14:0)} input 15 {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(14:0)} input 15 {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,11,1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,16)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(15:0)} input 16 {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(15:0)} input 16 {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(16,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(15:0)} input 16 {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(15:0)} input 16 {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(3,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,19)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(19,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(18:0)} input 19 {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(18:0)} input 19 {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,0,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,-1,11,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "or(2,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,90)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(89:0)} input 90 {A0(89)} {A0(88)} {A0(87)} {A0(86)} {A0(85)} {A0(84)} {A0(83)} {A0(82)} {A0(81)} {A0(80)} {A0(79)} {A0(78)} {A0(77)} {A0(76)} {A0(75)} {A0(74)} {A0(73)} {A0(72)} {A0(71)} {A0(70)} {A0(69)} {A0(68)} {A0(67)} {A0(66)} {A0(65)} {A0(64)} {A0(63)} {A0(62)} {A0(61)} {A0(60)} {A0(59)} {A0(58)} {A0(57)} {A0(56)} {A0(55)} {A0(54)} {A0(53)} {A0(52)} {A0(51)} {A0(50)} {A0(49)} {A0(48)} {A0(47)} {A0(46)} {A0(45)} {A0(44)} {A0(43)} {A0(42)} {A0(41)} {A0(40)} {A0(39)} {A0(38)} {A0(37)} {A0(36)} {A0(35)} {A0(34)} {A0(33)} {A0(32)} {A0(31)} {A0(30)} {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(89:0)} input 90 {A1(89)} {A1(88)} {A1(87)} {A1(86)} {A1(85)} {A1(84)} {A1(83)} {A1(82)} {A1(81)} {A1(80)} {A1(79)} {A1(78)} {A1(77)} {A1(76)} {A1(75)} {A1(74)} {A1(73)} {A1(72)} {A1(71)} {A1(70)} {A1(69)} {A1(68)} {A1(67)} {A1(66)} {A1(65)} {A1(64)} {A1(63)} {A1(62)} {A1(61)} {A1(60)} {A1(59)} {A1(58)} {A1(57)} {A1(56)} {A1(55)} {A1(54)} {A1(53)} {A1(52)} {A1(51)} {A1(50)} {A1(49)} {A1(48)} {A1(47)} {A1(46)} {A1(45)} {A1(44)} {A1(43)} {A1(42)} {A1(41)} {A1(40)} {A1(39)} {A1(38)} {A1(37)} {A1(36)} {A1(35)} {A1(34)} {A1(33)} {A1(32)} {A1(31)} {A1(30)} {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,8,-1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(19,-1,1,0,19)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(18:0)} input 19 {A(18)} {A(17)} {A(16)} {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,19)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,-1,6,-1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(15,-1,15,-1,15)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(14:0)} input 15 {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(14:0)} input 15 {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,16,-1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,10)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,15)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(14:0)} input 15 {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(14:0)} input 15 {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,12)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,12,1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,16)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(15:0)} input 16 {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(15:0)} input 16 {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nor(2,1)" "INTERFACE" NOR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "nand(2,1)" "INTERFACE" NAND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "or(3,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load net {FRAME:p#1.lpi#1(0)} -attr vt d
+load net {FRAME:p#1.lpi#1(1)} -attr vt d
+load net {FRAME:p#1.lpi#1(2)} -attr vt d
+load net {FRAME:p#1.lpi#1(3)} -attr vt d
+load net {FRAME:p#1.lpi#1(4)} -attr vt d
+load net {FRAME:p#1.lpi#1(5)} -attr vt d
+load net {FRAME:p#1.lpi#1(6)} -attr vt d
+load net {FRAME:p#1.lpi#1(7)} -attr vt d
+load net {FRAME:p#1.lpi#1(8)} -attr vt d
+load net {FRAME:p#1.lpi#1(9)} -attr vt d
+load net {FRAME:p#1.lpi#1(10)} -attr vt d
+load net {FRAME:p#1.lpi#1(11)} -attr vt d
+load net {FRAME:p#1.lpi#1(12)} -attr vt d
+load net {FRAME:p#1.lpi#1(13)} -attr vt d
+load net {FRAME:p#1.lpi#1(14)} -attr vt d
+load net {FRAME:p#1.lpi#1(15)} -attr vt d
+load net {FRAME:p#1.lpi#1(16)} -attr vt d
+load net {FRAME:p#1.lpi#1(17)} -attr vt d
+load net {FRAME:p#1.lpi#1(18)} -attr vt d
+load netBundle {FRAME:p#1.lpi#1} 19 {FRAME:p#1.lpi#1(0)} {FRAME:p#1.lpi#1(1)} {FRAME:p#1.lpi#1(2)} {FRAME:p#1.lpi#1(3)} {FRAME:p#1.lpi#1(4)} {FRAME:p#1.lpi#1(5)} {FRAME:p#1.lpi#1(6)} {FRAME:p#1.lpi#1(7)} {FRAME:p#1.lpi#1(8)} {FRAME:p#1.lpi#1(9)} {FRAME:p#1.lpi#1(10)} {FRAME:p#1.lpi#1(11)} {FRAME:p#1.lpi#1(12)} {FRAME:p#1.lpi#1(13)} {FRAME:p#1.lpi#1(14)} {FRAME:p#1.lpi#1(15)} {FRAME:p#1.lpi#1(16)} {FRAME:p#1.lpi#1(17)} {FRAME:p#1.lpi#1(18)} -attr xrf 44130 -attr oid 6 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {b(1).sg1.lpi#1(0)} -attr vt d
+load net {b(1).sg1.lpi#1(1)} -attr vt d
+load net {b(1).sg1.lpi#1(2)} -attr vt d
+load net {b(1).sg1.lpi#1(3)} -attr vt d
+load net {b(1).sg1.lpi#1(4)} -attr vt d
+load net {b(1).sg1.lpi#1(5)} -attr vt d
+load net {b(1).sg1.lpi#1(6)} -attr vt d
+load net {b(1).sg1.lpi#1(7)} -attr vt d
+load net {b(1).sg1.lpi#1(8)} -attr vt d
+load net {b(1).sg1.lpi#1(9)} -attr vt d
+load net {b(1).sg1.lpi#1(10)} -attr vt d
+load net {b(1).sg1.lpi#1(11)} -attr vt d
+load net {b(1).sg1.lpi#1(12)} -attr vt d
+load net {b(1).sg1.lpi#1(13)} -attr vt d
+load net {b(1).sg1.lpi#1(14)} -attr vt d
+load netBundle {b(1).sg1.lpi#1} 15 {b(1).sg1.lpi#1(0)} {b(1).sg1.lpi#1(1)} {b(1).sg1.lpi#1(2)} {b(1).sg1.lpi#1(3)} {b(1).sg1.lpi#1(4)} {b(1).sg1.lpi#1(5)} {b(1).sg1.lpi#1(6)} {b(1).sg1.lpi#1(7)} {b(1).sg1.lpi#1(8)} {b(1).sg1.lpi#1(9)} {b(1).sg1.lpi#1(10)} {b(1).sg1.lpi#1(11)} {b(1).sg1.lpi#1(12)} {b(1).sg1.lpi#1(13)} {b(1).sg1.lpi#1(14)} -attr xrf 44131 -attr oid 7 -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(0).lpi#1(0)} -attr vt d
+load net {b(0).lpi#1(1)} -attr vt d
+load net {b(0).lpi#1(2)} -attr vt d
+load net {b(0).lpi#1(3)} -attr vt d
+load net {b(0).lpi#1(4)} -attr vt d
+load net {b(0).lpi#1(5)} -attr vt d
+load net {b(0).lpi#1(6)} -attr vt d
+load net {b(0).lpi#1(7)} -attr vt d
+load net {b(0).lpi#1(8)} -attr vt d
+load net {b(0).lpi#1(9)} -attr vt d
+load net {b(0).lpi#1(10)} -attr vt d
+load net {b(0).lpi#1(11)} -attr vt d
+load net {b(0).lpi#1(12)} -attr vt d
+load net {b(0).lpi#1(13)} -attr vt d
+load net {b(0).lpi#1(14)} -attr vt d
+load net {b(0).lpi#1(15)} -attr vt d
+load netBundle {b(0).lpi#1} 16 {b(0).lpi#1(0)} {b(0).lpi#1(1)} {b(0).lpi#1(2)} {b(0).lpi#1(3)} {b(0).lpi#1(4)} {b(0).lpi#1(5)} {b(0).lpi#1(6)} {b(0).lpi#1(7)} {b(0).lpi#1(8)} {b(0).lpi#1(9)} {b(0).lpi#1(10)} {b(0).lpi#1(11)} {b(0).lpi#1(12)} {b(0).lpi#1(13)} {b(0).lpi#1(14)} {b(0).lpi#1(15)} -attr xrf 44132 -attr oid 8 -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(2).lpi#1(0)} -attr vt d
+load net {b(2).lpi#1(1)} -attr vt d
+load net {b(2).lpi#1(2)} -attr vt d
+load net {b(2).lpi#1(3)} -attr vt d
+load net {b(2).lpi#1(4)} -attr vt d
+load net {b(2).lpi#1(5)} -attr vt d
+load net {b(2).lpi#1(6)} -attr vt d
+load net {b(2).lpi#1(7)} -attr vt d
+load net {b(2).lpi#1(8)} -attr vt d
+load net {b(2).lpi#1(9)} -attr vt d
+load net {b(2).lpi#1(10)} -attr vt d
+load net {b(2).lpi#1(11)} -attr vt d
+load net {b(2).lpi#1(12)} -attr vt d
+load net {b(2).lpi#1(13)} -attr vt d
+load net {b(2).lpi#1(14)} -attr vt d
+load net {b(2).lpi#1(15)} -attr vt d
+load netBundle {b(2).lpi#1} 16 {b(2).lpi#1(0)} {b(2).lpi#1(1)} {b(2).lpi#1(2)} {b(2).lpi#1(3)} {b(2).lpi#1(4)} {b(2).lpi#1(5)} {b(2).lpi#1(6)} {b(2).lpi#1(7)} {b(2).lpi#1(8)} {b(2).lpi#1(9)} {b(2).lpi#1(10)} {b(2).lpi#1(11)} {b(2).lpi#1(12)} {b(2).lpi#1(13)} {b(2).lpi#1(14)} {b(2).lpi#1(15)} -attr xrf 44133 -attr oid 9 -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {g(1).sg1.lpi#1(0)} -attr vt d
+load net {g(1).sg1.lpi#1(1)} -attr vt d
+load net {g(1).sg1.lpi#1(2)} -attr vt d
+load net {g(1).sg1.lpi#1(3)} -attr vt d
+load net {g(1).sg1.lpi#1(4)} -attr vt d
+load net {g(1).sg1.lpi#1(5)} -attr vt d
+load net {g(1).sg1.lpi#1(6)} -attr vt d
+load net {g(1).sg1.lpi#1(7)} -attr vt d
+load net {g(1).sg1.lpi#1(8)} -attr vt d
+load net {g(1).sg1.lpi#1(9)} -attr vt d
+load net {g(1).sg1.lpi#1(10)} -attr vt d
+load net {g(1).sg1.lpi#1(11)} -attr vt d
+load net {g(1).sg1.lpi#1(12)} -attr vt d
+load net {g(1).sg1.lpi#1(13)} -attr vt d
+load net {g(1).sg1.lpi#1(14)} -attr vt d
+load netBundle {g(1).sg1.lpi#1} 15 {g(1).sg1.lpi#1(0)} {g(1).sg1.lpi#1(1)} {g(1).sg1.lpi#1(2)} {g(1).sg1.lpi#1(3)} {g(1).sg1.lpi#1(4)} {g(1).sg1.lpi#1(5)} {g(1).sg1.lpi#1(6)} {g(1).sg1.lpi#1(7)} {g(1).sg1.lpi#1(8)} {g(1).sg1.lpi#1(9)} {g(1).sg1.lpi#1(10)} {g(1).sg1.lpi#1(11)} {g(1).sg1.lpi#1(12)} {g(1).sg1.lpi#1(13)} {g(1).sg1.lpi#1(14)} -attr xrf 44134 -attr oid 10 -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(0).lpi#1(0)} -attr vt d
+load net {g(0).lpi#1(1)} -attr vt d
+load net {g(0).lpi#1(2)} -attr vt d
+load net {g(0).lpi#1(3)} -attr vt d
+load net {g(0).lpi#1(4)} -attr vt d
+load net {g(0).lpi#1(5)} -attr vt d
+load net {g(0).lpi#1(6)} -attr vt d
+load net {g(0).lpi#1(7)} -attr vt d
+load net {g(0).lpi#1(8)} -attr vt d
+load net {g(0).lpi#1(9)} -attr vt d
+load net {g(0).lpi#1(10)} -attr vt d
+load net {g(0).lpi#1(11)} -attr vt d
+load net {g(0).lpi#1(12)} -attr vt d
+load net {g(0).lpi#1(13)} -attr vt d
+load net {g(0).lpi#1(14)} -attr vt d
+load net {g(0).lpi#1(15)} -attr vt d
+load netBundle {g(0).lpi#1} 16 {g(0).lpi#1(0)} {g(0).lpi#1(1)} {g(0).lpi#1(2)} {g(0).lpi#1(3)} {g(0).lpi#1(4)} {g(0).lpi#1(5)} {g(0).lpi#1(6)} {g(0).lpi#1(7)} {g(0).lpi#1(8)} {g(0).lpi#1(9)} {g(0).lpi#1(10)} {g(0).lpi#1(11)} {g(0).lpi#1(12)} {g(0).lpi#1(13)} {g(0).lpi#1(14)} {g(0).lpi#1(15)} -attr xrf 44135 -attr oid 11 -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(2).lpi#1(0)} -attr vt d
+load net {g(2).lpi#1(1)} -attr vt d
+load net {g(2).lpi#1(2)} -attr vt d
+load net {g(2).lpi#1(3)} -attr vt d
+load net {g(2).lpi#1(4)} -attr vt d
+load net {g(2).lpi#1(5)} -attr vt d
+load net {g(2).lpi#1(6)} -attr vt d
+load net {g(2).lpi#1(7)} -attr vt d
+load net {g(2).lpi#1(8)} -attr vt d
+load net {g(2).lpi#1(9)} -attr vt d
+load net {g(2).lpi#1(10)} -attr vt d
+load net {g(2).lpi#1(11)} -attr vt d
+load net {g(2).lpi#1(12)} -attr vt d
+load net {g(2).lpi#1(13)} -attr vt d
+load net {g(2).lpi#1(14)} -attr vt d
+load net {g(2).lpi#1(15)} -attr vt d
+load netBundle {g(2).lpi#1} 16 {g(2).lpi#1(0)} {g(2).lpi#1(1)} {g(2).lpi#1(2)} {g(2).lpi#1(3)} {g(2).lpi#1(4)} {g(2).lpi#1(5)} {g(2).lpi#1(6)} {g(2).lpi#1(7)} {g(2).lpi#1(8)} {g(2).lpi#1(9)} {g(2).lpi#1(10)} {g(2).lpi#1(11)} {g(2).lpi#1(12)} {g(2).lpi#1(13)} {g(2).lpi#1(14)} {g(2).lpi#1(15)} -attr xrf 44136 -attr oid 12 -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {r(1).sg1.lpi#1(0)} -attr vt d
+load net {r(1).sg1.lpi#1(1)} -attr vt d
+load net {r(1).sg1.lpi#1(2)} -attr vt d
+load net {r(1).sg1.lpi#1(3)} -attr vt d
+load net {r(1).sg1.lpi#1(4)} -attr vt d
+load net {r(1).sg1.lpi#1(5)} -attr vt d
+load net {r(1).sg1.lpi#1(6)} -attr vt d
+load net {r(1).sg1.lpi#1(7)} -attr vt d
+load net {r(1).sg1.lpi#1(8)} -attr vt d
+load net {r(1).sg1.lpi#1(9)} -attr vt d
+load net {r(1).sg1.lpi#1(10)} -attr vt d
+load net {r(1).sg1.lpi#1(11)} -attr vt d
+load net {r(1).sg1.lpi#1(12)} -attr vt d
+load net {r(1).sg1.lpi#1(13)} -attr vt d
+load net {r(1).sg1.lpi#1(14)} -attr vt d
+load netBundle {r(1).sg1.lpi#1} 15 {r(1).sg1.lpi#1(0)} {r(1).sg1.lpi#1(1)} {r(1).sg1.lpi#1(2)} {r(1).sg1.lpi#1(3)} {r(1).sg1.lpi#1(4)} {r(1).sg1.lpi#1(5)} {r(1).sg1.lpi#1(6)} {r(1).sg1.lpi#1(7)} {r(1).sg1.lpi#1(8)} {r(1).sg1.lpi#1(9)} {r(1).sg1.lpi#1(10)} {r(1).sg1.lpi#1(11)} {r(1).sg1.lpi#1(12)} {r(1).sg1.lpi#1(13)} {r(1).sg1.lpi#1(14)} -attr xrf 44137 -attr oid 13 -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(0).lpi#1(0)} -attr vt d
+load net {r(0).lpi#1(1)} -attr vt d
+load net {r(0).lpi#1(2)} -attr vt d
+load net {r(0).lpi#1(3)} -attr vt d
+load net {r(0).lpi#1(4)} -attr vt d
+load net {r(0).lpi#1(5)} -attr vt d
+load net {r(0).lpi#1(6)} -attr vt d
+load net {r(0).lpi#1(7)} -attr vt d
+load net {r(0).lpi#1(8)} -attr vt d
+load net {r(0).lpi#1(9)} -attr vt d
+load net {r(0).lpi#1(10)} -attr vt d
+load net {r(0).lpi#1(11)} -attr vt d
+load net {r(0).lpi#1(12)} -attr vt d
+load net {r(0).lpi#1(13)} -attr vt d
+load net {r(0).lpi#1(14)} -attr vt d
+load net {r(0).lpi#1(15)} -attr vt d
+load netBundle {r(0).lpi#1} 16 {r(0).lpi#1(0)} {r(0).lpi#1(1)} {r(0).lpi#1(2)} {r(0).lpi#1(3)} {r(0).lpi#1(4)} {r(0).lpi#1(5)} {r(0).lpi#1(6)} {r(0).lpi#1(7)} {r(0).lpi#1(8)} {r(0).lpi#1(9)} {r(0).lpi#1(10)} {r(0).lpi#1(11)} {r(0).lpi#1(12)} {r(0).lpi#1(13)} {r(0).lpi#1(14)} {r(0).lpi#1(15)} -attr xrf 44138 -attr oid 14 -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(2).lpi#1(0)} -attr vt d
+load net {r(2).lpi#1(1)} -attr vt d
+load net {r(2).lpi#1(2)} -attr vt d
+load net {r(2).lpi#1(3)} -attr vt d
+load net {r(2).lpi#1(4)} -attr vt d
+load net {r(2).lpi#1(5)} -attr vt d
+load net {r(2).lpi#1(6)} -attr vt d
+load net {r(2).lpi#1(7)} -attr vt d
+load net {r(2).lpi#1(8)} -attr vt d
+load net {r(2).lpi#1(9)} -attr vt d
+load net {r(2).lpi#1(10)} -attr vt d
+load net {r(2).lpi#1(11)} -attr vt d
+load net {r(2).lpi#1(12)} -attr vt d
+load net {r(2).lpi#1(13)} -attr vt d
+load net {r(2).lpi#1(14)} -attr vt d
+load net {r(2).lpi#1(15)} -attr vt d
+load netBundle {r(2).lpi#1} 16 {r(2).lpi#1(0)} {r(2).lpi#1(1)} {r(2).lpi#1(2)} {r(2).lpi#1(3)} {r(2).lpi#1(4)} {r(2).lpi#1(5)} {r(2).lpi#1(6)} {r(2).lpi#1(7)} {r(2).lpi#1(8)} {r(2).lpi#1(9)} {r(2).lpi#1(10)} {r(2).lpi#1(11)} {r(2).lpi#1(12)} {r(2).lpi#1(13)} {r(2).lpi#1(14)} {r(2).lpi#1(15)} -attr xrf 44139 -attr oid 15 -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {i#6.lpi#1(0)} -attr vt d
+load net {i#6.lpi#1(1)} -attr vt d
+load netBundle {i#6.lpi#1} 2 {i#6.lpi#1(0)} {i#6.lpi#1(1)} -attr xrf 44140 -attr oid 16 -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1}
+load net {i#7.lpi#1(0)} -attr vt d
+load net {i#7.lpi#1(1)} -attr vt d
+load netBundle {i#7.lpi#1} 2 {i#7.lpi#1(0)} {i#7.lpi#1(1)} -attr xrf 44141 -attr oid 17 -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.regs(1).sva(0)} -attr vt d
+load net {regs.regs(1).sva(1)} -attr vt d
+load net {regs.regs(1).sva(2)} -attr vt d
+load net {regs.regs(1).sva(3)} -attr vt d
+load net {regs.regs(1).sva(4)} -attr vt d
+load net {regs.regs(1).sva(5)} -attr vt d
+load net {regs.regs(1).sva(6)} -attr vt d
+load net {regs.regs(1).sva(7)} -attr vt d
+load net {regs.regs(1).sva(8)} -attr vt d
+load net {regs.regs(1).sva(9)} -attr vt d
+load net {regs.regs(1).sva(10)} -attr vt d
+load net {regs.regs(1).sva(11)} -attr vt d
+load net {regs.regs(1).sva(12)} -attr vt d
+load net {regs.regs(1).sva(13)} -attr vt d
+load net {regs.regs(1).sva(14)} -attr vt d
+load net {regs.regs(1).sva(15)} -attr vt d
+load net {regs.regs(1).sva(16)} -attr vt d
+load net {regs.regs(1).sva(17)} -attr vt d
+load net {regs.regs(1).sva(18)} -attr vt d
+load net {regs.regs(1).sva(19)} -attr vt d
+load net {regs.regs(1).sva(20)} -attr vt d
+load net {regs.regs(1).sva(21)} -attr vt d
+load net {regs.regs(1).sva(22)} -attr vt d
+load net {regs.regs(1).sva(23)} -attr vt d
+load net {regs.regs(1).sva(24)} -attr vt d
+load net {regs.regs(1).sva(25)} -attr vt d
+load net {regs.regs(1).sva(26)} -attr vt d
+load net {regs.regs(1).sva(27)} -attr vt d
+load net {regs.regs(1).sva(28)} -attr vt d
+load net {regs.regs(1).sva(29)} -attr vt d
+load net {regs.regs(1).sva(30)} -attr vt d
+load net {regs.regs(1).sva(31)} -attr vt d
+load net {regs.regs(1).sva(32)} -attr vt d
+load net {regs.regs(1).sva(33)} -attr vt d
+load net {regs.regs(1).sva(34)} -attr vt d
+load net {regs.regs(1).sva(35)} -attr vt d
+load net {regs.regs(1).sva(36)} -attr vt d
+load net {regs.regs(1).sva(37)} -attr vt d
+load net {regs.regs(1).sva(38)} -attr vt d
+load net {regs.regs(1).sva(39)} -attr vt d
+load net {regs.regs(1).sva(40)} -attr vt d
+load net {regs.regs(1).sva(41)} -attr vt d
+load net {regs.regs(1).sva(42)} -attr vt d
+load net {regs.regs(1).sva(43)} -attr vt d
+load net {regs.regs(1).sva(44)} -attr vt d
+load net {regs.regs(1).sva(45)} -attr vt d
+load net {regs.regs(1).sva(46)} -attr vt d
+load net {regs.regs(1).sva(47)} -attr vt d
+load net {regs.regs(1).sva(48)} -attr vt d
+load net {regs.regs(1).sva(49)} -attr vt d
+load net {regs.regs(1).sva(50)} -attr vt d
+load net {regs.regs(1).sva(51)} -attr vt d
+load net {regs.regs(1).sva(52)} -attr vt d
+load net {regs.regs(1).sva(53)} -attr vt d
+load net {regs.regs(1).sva(54)} -attr vt d
+load net {regs.regs(1).sva(55)} -attr vt d
+load net {regs.regs(1).sva(56)} -attr vt d
+load net {regs.regs(1).sva(57)} -attr vt d
+load net {regs.regs(1).sva(58)} -attr vt d
+load net {regs.regs(1).sva(59)} -attr vt d
+load net {regs.regs(1).sva(60)} -attr vt d
+load net {regs.regs(1).sva(61)} -attr vt d
+load net {regs.regs(1).sva(62)} -attr vt d
+load net {regs.regs(1).sva(63)} -attr vt d
+load net {regs.regs(1).sva(64)} -attr vt d
+load net {regs.regs(1).sva(65)} -attr vt d
+load net {regs.regs(1).sva(66)} -attr vt d
+load net {regs.regs(1).sva(67)} -attr vt d
+load net {regs.regs(1).sva(68)} -attr vt d
+load net {regs.regs(1).sva(69)} -attr vt d
+load net {regs.regs(1).sva(70)} -attr vt d
+load net {regs.regs(1).sva(71)} -attr vt d
+load net {regs.regs(1).sva(72)} -attr vt d
+load net {regs.regs(1).sva(73)} -attr vt d
+load net {regs.regs(1).sva(74)} -attr vt d
+load net {regs.regs(1).sva(75)} -attr vt d
+load net {regs.regs(1).sva(76)} -attr vt d
+load net {regs.regs(1).sva(77)} -attr vt d
+load net {regs.regs(1).sva(78)} -attr vt d
+load net {regs.regs(1).sva(79)} -attr vt d
+load net {regs.regs(1).sva(80)} -attr vt d
+load net {regs.regs(1).sva(81)} -attr vt d
+load net {regs.regs(1).sva(82)} -attr vt d
+load net {regs.regs(1).sva(83)} -attr vt d
+load net {regs.regs(1).sva(84)} -attr vt d
+load net {regs.regs(1).sva(85)} -attr vt d
+load net {regs.regs(1).sva(86)} -attr vt d
+load net {regs.regs(1).sva(87)} -attr vt d
+load net {regs.regs(1).sva(88)} -attr vt d
+load net {regs.regs(1).sva(89)} -attr vt d
+load netBundle {regs.regs(1).sva} 90 {regs.regs(1).sva(0)} {regs.regs(1).sva(1)} {regs.regs(1).sva(2)} {regs.regs(1).sva(3)} {regs.regs(1).sva(4)} {regs.regs(1).sva(5)} {regs.regs(1).sva(6)} {regs.regs(1).sva(7)} {regs.regs(1).sva(8)} {regs.regs(1).sva(9)} {regs.regs(1).sva(10)} {regs.regs(1).sva(11)} {regs.regs(1).sva(12)} {regs.regs(1).sva(13)} {regs.regs(1).sva(14)} {regs.regs(1).sva(15)} {regs.regs(1).sva(16)} {regs.regs(1).sva(17)} {regs.regs(1).sva(18)} {regs.regs(1).sva(19)} {regs.regs(1).sva(20)} {regs.regs(1).sva(21)} {regs.regs(1).sva(22)} {regs.regs(1).sva(23)} {regs.regs(1).sva(24)} {regs.regs(1).sva(25)} {regs.regs(1).sva(26)} {regs.regs(1).sva(27)} {regs.regs(1).sva(28)} {regs.regs(1).sva(29)} {regs.regs(1).sva(30)} {regs.regs(1).sva(31)} {regs.regs(1).sva(32)} {regs.regs(1).sva(33)} {regs.regs(1).sva(34)} {regs.regs(1).sva(35)} {regs.regs(1).sva(36)} {regs.regs(1).sva(37)} {regs.regs(1).sva(38)} {regs.regs(1).sva(39)} {regs.regs(1).sva(40)} {regs.regs(1).sva(41)} {regs.regs(1).sva(42)} {regs.regs(1).sva(43)} {regs.regs(1).sva(44)} {regs.regs(1).sva(45)} {regs.regs(1).sva(46)} {regs.regs(1).sva(47)} {regs.regs(1).sva(48)} {regs.regs(1).sva(49)} {regs.regs(1).sva(50)} {regs.regs(1).sva(51)} {regs.regs(1).sva(52)} {regs.regs(1).sva(53)} {regs.regs(1).sva(54)} {regs.regs(1).sva(55)} {regs.regs(1).sva(56)} {regs.regs(1).sva(57)} {regs.regs(1).sva(58)} {regs.regs(1).sva(59)} {regs.regs(1).sva(60)} {regs.regs(1).sva(61)} {regs.regs(1).sva(62)} {regs.regs(1).sva(63)} {regs.regs(1).sva(64)} {regs.regs(1).sva(65)} {regs.regs(1).sva(66)} {regs.regs(1).sva(67)} {regs.regs(1).sva(68)} {regs.regs(1).sva(69)} {regs.regs(1).sva(70)} {regs.regs(1).sva(71)} {regs.regs(1).sva(72)} {regs.regs(1).sva(73)} {regs.regs(1).sva(74)} {regs.regs(1).sva(75)} {regs.regs(1).sva(76)} {regs.regs(1).sva(77)} {regs.regs(1).sva(78)} {regs.regs(1).sva(79)} {regs.regs(1).sva(80)} {regs.regs(1).sva(81)} {regs.regs(1).sva(82)} {regs.regs(1).sva(83)} {regs.regs(1).sva(84)} {regs.regs(1).sva(85)} {regs.regs(1).sva(86)} {regs.regs(1).sva(87)} {regs.regs(1).sva(88)} {regs.regs(1).sva(89)} -attr xrf 44142 -attr oid 18 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -attr vt d
+load net {regs.regs(0).sva(1)} -attr vt d
+load net {regs.regs(0).sva(2)} -attr vt d
+load net {regs.regs(0).sva(3)} -attr vt d
+load net {regs.regs(0).sva(4)} -attr vt d
+load net {regs.regs(0).sva(5)} -attr vt d
+load net {regs.regs(0).sva(6)} -attr vt d
+load net {regs.regs(0).sva(7)} -attr vt d
+load net {regs.regs(0).sva(8)} -attr vt d
+load net {regs.regs(0).sva(9)} -attr vt d
+load net {regs.regs(0).sva(10)} -attr vt d
+load net {regs.regs(0).sva(11)} -attr vt d
+load net {regs.regs(0).sva(12)} -attr vt d
+load net {regs.regs(0).sva(13)} -attr vt d
+load net {regs.regs(0).sva(14)} -attr vt d
+load net {regs.regs(0).sva(15)} -attr vt d
+load net {regs.regs(0).sva(16)} -attr vt d
+load net {regs.regs(0).sva(17)} -attr vt d
+load net {regs.regs(0).sva(18)} -attr vt d
+load net {regs.regs(0).sva(19)} -attr vt d
+load net {regs.regs(0).sva(20)} -attr vt d
+load net {regs.regs(0).sva(21)} -attr vt d
+load net {regs.regs(0).sva(22)} -attr vt d
+load net {regs.regs(0).sva(23)} -attr vt d
+load net {regs.regs(0).sva(24)} -attr vt d
+load net {regs.regs(0).sva(25)} -attr vt d
+load net {regs.regs(0).sva(26)} -attr vt d
+load net {regs.regs(0).sva(27)} -attr vt d
+load net {regs.regs(0).sva(28)} -attr vt d
+load net {regs.regs(0).sva(29)} -attr vt d
+load net {regs.regs(0).sva(30)} -attr vt d
+load net {regs.regs(0).sva(31)} -attr vt d
+load net {regs.regs(0).sva(32)} -attr vt d
+load net {regs.regs(0).sva(33)} -attr vt d
+load net {regs.regs(0).sva(34)} -attr vt d
+load net {regs.regs(0).sva(35)} -attr vt d
+load net {regs.regs(0).sva(36)} -attr vt d
+load net {regs.regs(0).sva(37)} -attr vt d
+load net {regs.regs(0).sva(38)} -attr vt d
+load net {regs.regs(0).sva(39)} -attr vt d
+load net {regs.regs(0).sva(40)} -attr vt d
+load net {regs.regs(0).sva(41)} -attr vt d
+load net {regs.regs(0).sva(42)} -attr vt d
+load net {regs.regs(0).sva(43)} -attr vt d
+load net {regs.regs(0).sva(44)} -attr vt d
+load net {regs.regs(0).sva(45)} -attr vt d
+load net {regs.regs(0).sva(46)} -attr vt d
+load net {regs.regs(0).sva(47)} -attr vt d
+load net {regs.regs(0).sva(48)} -attr vt d
+load net {regs.regs(0).sva(49)} -attr vt d
+load net {regs.regs(0).sva(50)} -attr vt d
+load net {regs.regs(0).sva(51)} -attr vt d
+load net {regs.regs(0).sva(52)} -attr vt d
+load net {regs.regs(0).sva(53)} -attr vt d
+load net {regs.regs(0).sva(54)} -attr vt d
+load net {regs.regs(0).sva(55)} -attr vt d
+load net {regs.regs(0).sva(56)} -attr vt d
+load net {regs.regs(0).sva(57)} -attr vt d
+load net {regs.regs(0).sva(58)} -attr vt d
+load net {regs.regs(0).sva(59)} -attr vt d
+load net {regs.regs(0).sva(60)} -attr vt d
+load net {regs.regs(0).sva(61)} -attr vt d
+load net {regs.regs(0).sva(62)} -attr vt d
+load net {regs.regs(0).sva(63)} -attr vt d
+load net {regs.regs(0).sva(64)} -attr vt d
+load net {regs.regs(0).sva(65)} -attr vt d
+load net {regs.regs(0).sva(66)} -attr vt d
+load net {regs.regs(0).sva(67)} -attr vt d
+load net {regs.regs(0).sva(68)} -attr vt d
+load net {regs.regs(0).sva(69)} -attr vt d
+load net {regs.regs(0).sva(70)} -attr vt d
+load net {regs.regs(0).sva(71)} -attr vt d
+load net {regs.regs(0).sva(72)} -attr vt d
+load net {regs.regs(0).sva(73)} -attr vt d
+load net {regs.regs(0).sva(74)} -attr vt d
+load net {regs.regs(0).sva(75)} -attr vt d
+load net {regs.regs(0).sva(76)} -attr vt d
+load net {regs.regs(0).sva(77)} -attr vt d
+load net {regs.regs(0).sva(78)} -attr vt d
+load net {regs.regs(0).sva(79)} -attr vt d
+load net {regs.regs(0).sva(80)} -attr vt d
+load net {regs.regs(0).sva(81)} -attr vt d
+load net {regs.regs(0).sva(82)} -attr vt d
+load net {regs.regs(0).sva(83)} -attr vt d
+load net {regs.regs(0).sva(84)} -attr vt d
+load net {regs.regs(0).sva(85)} -attr vt d
+load net {regs.regs(0).sva(86)} -attr vt d
+load net {regs.regs(0).sva(87)} -attr vt d
+load net {regs.regs(0).sva(88)} -attr vt d
+load net {regs.regs(0).sva(89)} -attr vt d
+load netBundle {regs.regs(0).sva} 90 {regs.regs(0).sva(0)} {regs.regs(0).sva(1)} {regs.regs(0).sva(2)} {regs.regs(0).sva(3)} {regs.regs(0).sva(4)} {regs.regs(0).sva(5)} {regs.regs(0).sva(6)} {regs.regs(0).sva(7)} {regs.regs(0).sva(8)} {regs.regs(0).sva(9)} {regs.regs(0).sva(10)} {regs.regs(0).sva(11)} {regs.regs(0).sva(12)} {regs.regs(0).sva(13)} {regs.regs(0).sva(14)} {regs.regs(0).sva(15)} {regs.regs(0).sva(16)} {regs.regs(0).sva(17)} {regs.regs(0).sva(18)} {regs.regs(0).sva(19)} {regs.regs(0).sva(20)} {regs.regs(0).sva(21)} {regs.regs(0).sva(22)} {regs.regs(0).sva(23)} {regs.regs(0).sva(24)} {regs.regs(0).sva(25)} {regs.regs(0).sva(26)} {regs.regs(0).sva(27)} {regs.regs(0).sva(28)} {regs.regs(0).sva(29)} {regs.regs(0).sva(30)} {regs.regs(0).sva(31)} {regs.regs(0).sva(32)} {regs.regs(0).sva(33)} {regs.regs(0).sva(34)} {regs.regs(0).sva(35)} {regs.regs(0).sva(36)} {regs.regs(0).sva(37)} {regs.regs(0).sva(38)} {regs.regs(0).sva(39)} {regs.regs(0).sva(40)} {regs.regs(0).sva(41)} {regs.regs(0).sva(42)} {regs.regs(0).sva(43)} {regs.regs(0).sva(44)} {regs.regs(0).sva(45)} {regs.regs(0).sva(46)} {regs.regs(0).sva(47)} {regs.regs(0).sva(48)} {regs.regs(0).sva(49)} {regs.regs(0).sva(50)} {regs.regs(0).sva(51)} {regs.regs(0).sva(52)} {regs.regs(0).sva(53)} {regs.regs(0).sva(54)} {regs.regs(0).sva(55)} {regs.regs(0).sva(56)} {regs.regs(0).sva(57)} {regs.regs(0).sva(58)} {regs.regs(0).sva(59)} {regs.regs(0).sva(60)} {regs.regs(0).sva(61)} {regs.regs(0).sva(62)} {regs.regs(0).sva(63)} {regs.regs(0).sva(64)} {regs.regs(0).sva(65)} {regs.regs(0).sva(66)} {regs.regs(0).sva(67)} {regs.regs(0).sva(68)} {regs.regs(0).sva(69)} {regs.regs(0).sva(70)} {regs.regs(0).sva(71)} {regs.regs(0).sva(72)} {regs.regs(0).sva(73)} {regs.regs(0).sva(74)} {regs.regs(0).sva(75)} {regs.regs(0).sva(76)} {regs.regs(0).sva(77)} {regs.regs(0).sva(78)} {regs.regs(0).sva(79)} {regs.regs(0).sva(80)} {regs.regs(0).sva(81)} {regs.regs(0).sva(82)} {regs.regs(0).sva(83)} {regs.regs(0).sva(84)} {regs.regs(0).sva(85)} {regs.regs(0).sva(86)} {regs.regs(0).sva(87)} {regs.regs(0).sva(88)} {regs.regs(0).sva(89)} -attr xrf 44143 -attr oid 19 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(2).lpi#1.dfm(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(29)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(30)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(31)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(32)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(33)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(34)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(35)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(36)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(37)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(38)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(39)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(40)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(41)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(42)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(43)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(44)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(45)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(46)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(47)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(48)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(49)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(50)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(51)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(52)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(53)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(54)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(55)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(56)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(57)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(58)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(59)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(60)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(61)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(62)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(63)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(64)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(65)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(66)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(67)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(68)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(69)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(70)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(71)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(72)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(73)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(74)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(75)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(76)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(77)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(78)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(79)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(80)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(81)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(82)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(83)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(84)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(85)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(86)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(87)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(88)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(89)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm} 90 {regs.regs(2).lpi#1.dfm(0)} {regs.regs(2).lpi#1.dfm(1)} {regs.regs(2).lpi#1.dfm(2)} {regs.regs(2).lpi#1.dfm(3)} {regs.regs(2).lpi#1.dfm(4)} {regs.regs(2).lpi#1.dfm(5)} {regs.regs(2).lpi#1.dfm(6)} {regs.regs(2).lpi#1.dfm(7)} {regs.regs(2).lpi#1.dfm(8)} {regs.regs(2).lpi#1.dfm(9)} {regs.regs(2).lpi#1.dfm(10)} {regs.regs(2).lpi#1.dfm(11)} {regs.regs(2).lpi#1.dfm(12)} {regs.regs(2).lpi#1.dfm(13)} {regs.regs(2).lpi#1.dfm(14)} {regs.regs(2).lpi#1.dfm(15)} {regs.regs(2).lpi#1.dfm(16)} {regs.regs(2).lpi#1.dfm(17)} {regs.regs(2).lpi#1.dfm(18)} {regs.regs(2).lpi#1.dfm(19)} {regs.regs(2).lpi#1.dfm(20)} {regs.regs(2).lpi#1.dfm(21)} {regs.regs(2).lpi#1.dfm(22)} {regs.regs(2).lpi#1.dfm(23)} {regs.regs(2).lpi#1.dfm(24)} {regs.regs(2).lpi#1.dfm(25)} {regs.regs(2).lpi#1.dfm(26)} {regs.regs(2).lpi#1.dfm(27)} {regs.regs(2).lpi#1.dfm(28)} {regs.regs(2).lpi#1.dfm(29)} {regs.regs(2).lpi#1.dfm(30)} {regs.regs(2).lpi#1.dfm(31)} {regs.regs(2).lpi#1.dfm(32)} {regs.regs(2).lpi#1.dfm(33)} {regs.regs(2).lpi#1.dfm(34)} {regs.regs(2).lpi#1.dfm(35)} {regs.regs(2).lpi#1.dfm(36)} {regs.regs(2).lpi#1.dfm(37)} {regs.regs(2).lpi#1.dfm(38)} {regs.regs(2).lpi#1.dfm(39)} {regs.regs(2).lpi#1.dfm(40)} {regs.regs(2).lpi#1.dfm(41)} {regs.regs(2).lpi#1.dfm(42)} {regs.regs(2).lpi#1.dfm(43)} {regs.regs(2).lpi#1.dfm(44)} {regs.regs(2).lpi#1.dfm(45)} {regs.regs(2).lpi#1.dfm(46)} {regs.regs(2).lpi#1.dfm(47)} {regs.regs(2).lpi#1.dfm(48)} {regs.regs(2).lpi#1.dfm(49)} {regs.regs(2).lpi#1.dfm(50)} {regs.regs(2).lpi#1.dfm(51)} {regs.regs(2).lpi#1.dfm(52)} {regs.regs(2).lpi#1.dfm(53)} {regs.regs(2).lpi#1.dfm(54)} {regs.regs(2).lpi#1.dfm(55)} {regs.regs(2).lpi#1.dfm(56)} {regs.regs(2).lpi#1.dfm(57)} {regs.regs(2).lpi#1.dfm(58)} {regs.regs(2).lpi#1.dfm(59)} {regs.regs(2).lpi#1.dfm(60)} {regs.regs(2).lpi#1.dfm(61)} {regs.regs(2).lpi#1.dfm(62)} {regs.regs(2).lpi#1.dfm(63)} {regs.regs(2).lpi#1.dfm(64)} {regs.regs(2).lpi#1.dfm(65)} {regs.regs(2).lpi#1.dfm(66)} {regs.regs(2).lpi#1.dfm(67)} {regs.regs(2).lpi#1.dfm(68)} {regs.regs(2).lpi#1.dfm(69)} {regs.regs(2).lpi#1.dfm(70)} {regs.regs(2).lpi#1.dfm(71)} {regs.regs(2).lpi#1.dfm(72)} {regs.regs(2).lpi#1.dfm(73)} {regs.regs(2).lpi#1.dfm(74)} {regs.regs(2).lpi#1.dfm(75)} {regs.regs(2).lpi#1.dfm(76)} {regs.regs(2).lpi#1.dfm(77)} {regs.regs(2).lpi#1.dfm(78)} {regs.regs(2).lpi#1.dfm(79)} {regs.regs(2).lpi#1.dfm(80)} {regs.regs(2).lpi#1.dfm(81)} {regs.regs(2).lpi#1.dfm(82)} {regs.regs(2).lpi#1.dfm(83)} {regs.regs(2).lpi#1.dfm(84)} {regs.regs(2).lpi#1.dfm(85)} {regs.regs(2).lpi#1.dfm(86)} {regs.regs(2).lpi#1.dfm(87)} {regs.regs(2).lpi#1.dfm(88)} {regs.regs(2).lpi#1.dfm(89)} -attr xrf 44144 -attr oid 20 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {FRAME:mul#2.itm#1(0)} -attr vt d
+load net {FRAME:mul#2.itm#1(1)} -attr vt d
+load net {FRAME:mul#2.itm#1(2)} -attr vt d
+load net {FRAME:mul#2.itm#1(3)} -attr vt d
+load net {FRAME:mul#2.itm#1(4)} -attr vt d
+load net {FRAME:mul#2.itm#1(5)} -attr vt d
+load net {FRAME:mul#2.itm#1(6)} -attr vt d
+load net {FRAME:mul#2.itm#1(7)} -attr vt d
+load net {FRAME:mul#2.itm#1(8)} -attr vt d
+load net {FRAME:mul#2.itm#1(9)} -attr vt d
+load net {FRAME:mul#2.itm#1(10)} -attr vt d
+load netBundle {FRAME:mul#2.itm#1} 11 {FRAME:mul#2.itm#1(0)} {FRAME:mul#2.itm#1(1)} {FRAME:mul#2.itm#1(2)} {FRAME:mul#2.itm#1(3)} {FRAME:mul#2.itm#1(4)} {FRAME:mul#2.itm#1(5)} {FRAME:mul#2.itm#1(6)} {FRAME:mul#2.itm#1(7)} {FRAME:mul#2.itm#1(8)} {FRAME:mul#2.itm#1(9)} {FRAME:mul#2.itm#1(10)} -attr xrf 44145 -attr oid 21 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#3.itm#1(0)} -attr vt d
+load net {FRAME:mul#3.itm#1(1)} -attr vt d
+load net {FRAME:mul#3.itm#1(2)} -attr vt d
+load net {FRAME:mul#3.itm#1(3)} -attr vt d
+load net {FRAME:mul#3.itm#1(4)} -attr vt d
+load net {FRAME:mul#3.itm#1(5)} -attr vt d
+load net {FRAME:mul#3.itm#1(6)} -attr vt d
+load net {FRAME:mul#3.itm#1(7)} -attr vt d
+load net {FRAME:mul#3.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#3.itm#1} 9 {FRAME:mul#3.itm#1(0)} {FRAME:mul#3.itm#1(1)} {FRAME:mul#3.itm#1(2)} {FRAME:mul#3.itm#1(3)} {FRAME:mul#3.itm#1(4)} {FRAME:mul#3.itm#1(5)} {FRAME:mul#3.itm#1(6)} {FRAME:mul#3.itm#1(7)} {FRAME:mul#3.itm#1(8)} -attr xrf 44146 -attr oid 22 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {green:slc(green#2.sg1).itm#1(0)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(1)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(2)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(3)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(4)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(5)} -attr vt d
+load netBundle {green:slc(green#2.sg1).itm#1} 6 {green:slc(green#2.sg1).itm#1(0)} {green:slc(green#2.sg1).itm#1(1)} {green:slc(green#2.sg1).itm#1(2)} {green:slc(green#2.sg1).itm#1(3)} {green:slc(green#2.sg1).itm#1(4)} {green:slc(green#2.sg1).itm#1(5)} -attr xrf 44147 -attr oid 23 -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {FRAME:acc#18.itm#1(0)} -attr vt d
+load net {FRAME:acc#18.itm#1(1)} -attr vt d
+load net {FRAME:acc#18.itm#1(2)} -attr vt d
+load net {FRAME:acc#18.itm#1(3)} -attr vt d
+load net {FRAME:acc#18.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#18.itm#1} 5 {FRAME:acc#18.itm#1(0)} {FRAME:acc#18.itm#1(1)} {FRAME:acc#18.itm#1(2)} {FRAME:acc#18.itm#1(3)} {FRAME:acc#18.itm#1(4)} -attr xrf 44148 -attr oid 24 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:mul#4.itm#1(0)} -attr vt d
+load net {FRAME:mul#4.itm#1(1)} -attr vt d
+load net {FRAME:mul#4.itm#1(2)} -attr vt d
+load net {FRAME:mul#4.itm#1(3)} -attr vt d
+load net {FRAME:mul#4.itm#1(4)} -attr vt d
+load net {FRAME:mul#4.itm#1(5)} -attr vt d
+load net {FRAME:mul#4.itm#1(6)} -attr vt d
+load net {FRAME:mul#4.itm#1(7)} -attr vt d
+load net {FRAME:mul#4.itm#1(8)} -attr vt d
+load net {FRAME:mul#4.itm#1(9)} -attr vt d
+load net {FRAME:mul#4.itm#1(10)} -attr vt d
+load netBundle {FRAME:mul#4.itm#1} 11 {FRAME:mul#4.itm#1(0)} {FRAME:mul#4.itm#1(1)} {FRAME:mul#4.itm#1(2)} {FRAME:mul#4.itm#1(3)} {FRAME:mul#4.itm#1(4)} {FRAME:mul#4.itm#1(5)} {FRAME:mul#4.itm#1(6)} {FRAME:mul#4.itm#1(7)} {FRAME:mul#4.itm#1(8)} {FRAME:mul#4.itm#1(9)} {FRAME:mul#4.itm#1(10)} -attr xrf 44149 -attr oid 25 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#5.itm#1(0)} -attr vt d
+load net {FRAME:mul#5.itm#1(1)} -attr vt d
+load net {FRAME:mul#5.itm#1(2)} -attr vt d
+load net {FRAME:mul#5.itm#1(3)} -attr vt d
+load net {FRAME:mul#5.itm#1(4)} -attr vt d
+load net {FRAME:mul#5.itm#1(5)} -attr vt d
+load net {FRAME:mul#5.itm#1(6)} -attr vt d
+load net {FRAME:mul#5.itm#1(7)} -attr vt d
+load net {FRAME:mul#5.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#5.itm#1} 9 {FRAME:mul#5.itm#1(0)} {FRAME:mul#5.itm#1(1)} {FRAME:mul#5.itm#1(2)} {FRAME:mul#5.itm#1(3)} {FRAME:mul#5.itm#1(4)} {FRAME:mul#5.itm#1(5)} {FRAME:mul#5.itm#1(6)} {FRAME:mul#5.itm#1(7)} {FRAME:mul#5.itm#1(8)} -attr xrf 44150 -attr oid 26 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(0)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(1)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(2)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(3)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(4)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(5)} -attr vt d
+load netBundle {blue:slc(blue#2.sg1).itm#1} 6 {blue:slc(blue#2.sg1).itm#1(0)} {blue:slc(blue#2.sg1).itm#1(1)} {blue:slc(blue#2.sg1).itm#1(2)} {blue:slc(blue#2.sg1).itm#1(3)} {blue:slc(blue#2.sg1).itm#1(4)} {blue:slc(blue#2.sg1).itm#1(5)} -attr xrf 44151 -attr oid 27 -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {FRAME:acc#30.itm#1(0)} -attr vt d
+load net {FRAME:acc#30.itm#1(1)} -attr vt d
+load net {FRAME:acc#30.itm#1(2)} -attr vt d
+load net {FRAME:acc#30.itm#1(3)} -attr vt d
+load net {FRAME:acc#30.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#30.itm#1} 5 {FRAME:acc#30.itm#1(0)} {FRAME:acc#30.itm#1(1)} {FRAME:acc#30.itm#1(2)} {FRAME:acc#30.itm#1(3)} {FRAME:acc#30.itm#1(4)} -attr xrf 44152 -attr oid 28 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:mul#1.itm#1(0)} -attr vt d
+load net {FRAME:mul#1.itm#1(1)} -attr vt d
+load net {FRAME:mul#1.itm#1(2)} -attr vt d
+load net {FRAME:mul#1.itm#1(3)} -attr vt d
+load net {FRAME:mul#1.itm#1(4)} -attr vt d
+load net {FRAME:mul#1.itm#1(5)} -attr vt d
+load net {FRAME:mul#1.itm#1(6)} -attr vt d
+load net {FRAME:mul#1.itm#1(7)} -attr vt d
+load net {FRAME:mul#1.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#1.itm#1} 9 {FRAME:mul#1.itm#1(0)} {FRAME:mul#1.itm#1(1)} {FRAME:mul#1.itm#1(2)} {FRAME:mul#1.itm#1(3)} {FRAME:mul#1.itm#1(4)} {FRAME:mul#1.itm#1(5)} {FRAME:mul#1.itm#1(6)} {FRAME:mul#1.itm#1(7)} {FRAME:mul#1.itm#1(8)} -attr xrf 44153 -attr oid 29 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {red:slc(red#2.sg1).itm#1(0)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(1)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(2)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(3)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(4)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(5)} -attr vt d
+load netBundle {red:slc(red#2.sg1).itm#1} 6 {red:slc(red#2.sg1).itm#1(0)} {red:slc(red#2.sg1).itm#1(1)} {red:slc(red#2.sg1).itm#1(2)} {red:slc(red#2.sg1).itm#1(3)} {red:slc(red#2.sg1).itm#1(4)} {red:slc(red#2.sg1).itm#1(5)} -attr xrf 44154 -attr oid 30 -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {FRAME:acc#37.itm#1(0)} -attr vt d
+load net {FRAME:acc#37.itm#1(1)} -attr vt d
+load net {FRAME:acc#37.itm#1(2)} -attr vt d
+load net {FRAME:acc#37.itm#1(3)} -attr vt d
+load net {FRAME:acc#37.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#37.itm#1} 5 {FRAME:acc#37.itm#1(0)} {FRAME:acc#37.itm#1(1)} {FRAME:acc#37.itm#1(2)} {FRAME:acc#37.itm#1(3)} {FRAME:acc#37.itm#1(4)} -attr xrf 44155 -attr oid 31 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#41.itm#1.sg2(0)} -attr vt d
+load net {FRAME:acc#41.itm#1.sg2(1)} -attr vt d
+load netBundle {FRAME:acc#41.itm#1.sg2} 2 {FRAME:acc#41.itm#1.sg2(0)} {FRAME:acc#41.itm#1.sg2(1)} -attr xrf 44156 -attr oid 32 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg2}
+load net {FRAME:acc#41.itm#1.sg1(0)} -attr vt d
+load net {FRAME:acc#41.itm#1.sg1(1)} -attr vt d
+load netBundle {FRAME:acc#41.itm#1.sg1} 2 {FRAME:acc#41.itm#1.sg1(0)} {FRAME:acc#41.itm#1.sg1(1)} -attr xrf 44157 -attr oid 33 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg1}
+load net {FRAME:acc#41.itm#3(0)} -attr vt d
+load net {FRAME:acc#41.itm#3(1)} -attr vt d
+load net {FRAME:acc#41.itm#3(2)} -attr vt d
+load net {FRAME:acc#41.itm#3(3)} -attr vt d
+load net {FRAME:acc#41.itm#3(4)} -attr vt d
+load net {FRAME:acc#41.itm#3(5)} -attr vt d
+load netBundle {FRAME:acc#41.itm#3} 6 {FRAME:acc#41.itm#3(0)} {FRAME:acc#41.itm#3(1)} {FRAME:acc#41.itm#3(2)} {FRAME:acc#41.itm#3(3)} {FRAME:acc#41.itm#3(4)} {FRAME:acc#41.itm#3(5)} -attr xrf 44158 -attr oid 34 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#3.psp.sva(0)} -attr vt d
+load net {FRAME:acc#3.psp.sva(1)} -attr vt d
+load net {FRAME:acc#3.psp.sva(2)} -attr vt d
+load net {FRAME:acc#3.psp.sva(3)} -attr vt d
+load net {FRAME:acc#3.psp.sva(4)} -attr vt d
+load net {FRAME:acc#3.psp.sva(5)} -attr vt d
+load net {FRAME:acc#3.psp.sva(6)} -attr vt d
+load net {FRAME:acc#3.psp.sva(7)} -attr vt d
+load net {FRAME:acc#3.psp.sva(8)} -attr vt d
+load net {FRAME:acc#3.psp.sva(9)} -attr vt d
+load net {FRAME:acc#3.psp.sva(10)} -attr vt d
+load net {FRAME:acc#3.psp.sva(11)} -attr vt d
+load netBundle {FRAME:acc#3.psp.sva} 12 {FRAME:acc#3.psp.sva(0)} {FRAME:acc#3.psp.sva(1)} {FRAME:acc#3.psp.sva(2)} {FRAME:acc#3.psp.sva(3)} {FRAME:acc#3.psp.sva(4)} {FRAME:acc#3.psp.sva(5)} {FRAME:acc#3.psp.sva(6)} {FRAME:acc#3.psp.sva(7)} {FRAME:acc#3.psp.sva(8)} {FRAME:acc#3.psp.sva(9)} {FRAME:acc#3.psp.sva(10)} {FRAME:acc#3.psp.sva(11)} -attr xrf 44159 -attr oid 35 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#4.psp.sva(0)} -attr vt d
+load net {FRAME:acc#4.psp.sva(1)} -attr vt d
+load net {FRAME:acc#4.psp.sva(2)} -attr vt d
+load net {FRAME:acc#4.psp.sva(3)} -attr vt d
+load net {FRAME:acc#4.psp.sva(4)} -attr vt d
+load net {FRAME:acc#4.psp.sva(5)} -attr vt d
+load net {FRAME:acc#4.psp.sva(6)} -attr vt d
+load net {FRAME:acc#4.psp.sva(7)} -attr vt d
+load net {FRAME:acc#4.psp.sva(8)} -attr vt d
+load net {FRAME:acc#4.psp.sva(9)} -attr vt d
+load net {FRAME:acc#4.psp.sva(10)} -attr vt d
+load net {FRAME:acc#4.psp.sva(11)} -attr vt d
+load netBundle {FRAME:acc#4.psp.sva} 12 {FRAME:acc#4.psp.sva(0)} {FRAME:acc#4.psp.sva(1)} {FRAME:acc#4.psp.sva(2)} {FRAME:acc#4.psp.sva(3)} {FRAME:acc#4.psp.sva(4)} {FRAME:acc#4.psp.sva(5)} {FRAME:acc#4.psp.sva(6)} {FRAME:acc#4.psp.sva(7)} {FRAME:acc#4.psp.sva(8)} {FRAME:acc#4.psp.sva(9)} {FRAME:acc#4.psp.sva(10)} {FRAME:acc#4.psp.sva(11)} -attr xrf 44160 -attr oid 36 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {i#7.sva(0)} -attr vt d
+load net {i#7.sva(1)} -attr vt d
+load netBundle {i#7.sva} 2 {i#7.sva(0)} {i#7.sva(1)} -attr xrf 44161 -attr oid 37 -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm:mx0} 90 {regs.regs(2).lpi#1.dfm:mx0(0)} {regs.regs(2).lpi#1.dfm:mx0(1)} {regs.regs(2).lpi#1.dfm:mx0(2)} {regs.regs(2).lpi#1.dfm:mx0(3)} {regs.regs(2).lpi#1.dfm:mx0(4)} {regs.regs(2).lpi#1.dfm:mx0(5)} {regs.regs(2).lpi#1.dfm:mx0(6)} {regs.regs(2).lpi#1.dfm:mx0(7)} {regs.regs(2).lpi#1.dfm:mx0(8)} {regs.regs(2).lpi#1.dfm:mx0(9)} {regs.regs(2).lpi#1.dfm:mx0(10)} {regs.regs(2).lpi#1.dfm:mx0(11)} {regs.regs(2).lpi#1.dfm:mx0(12)} {regs.regs(2).lpi#1.dfm:mx0(13)} {regs.regs(2).lpi#1.dfm:mx0(14)} {regs.regs(2).lpi#1.dfm:mx0(15)} {regs.regs(2).lpi#1.dfm:mx0(16)} {regs.regs(2).lpi#1.dfm:mx0(17)} {regs.regs(2).lpi#1.dfm:mx0(18)} {regs.regs(2).lpi#1.dfm:mx0(19)} {regs.regs(2).lpi#1.dfm:mx0(20)} {regs.regs(2).lpi#1.dfm:mx0(21)} {regs.regs(2).lpi#1.dfm:mx0(22)} {regs.regs(2).lpi#1.dfm:mx0(23)} {regs.regs(2).lpi#1.dfm:mx0(24)} {regs.regs(2).lpi#1.dfm:mx0(25)} {regs.regs(2).lpi#1.dfm:mx0(26)} {regs.regs(2).lpi#1.dfm:mx0(27)} {regs.regs(2).lpi#1.dfm:mx0(28)} {regs.regs(2).lpi#1.dfm:mx0(29)} {regs.regs(2).lpi#1.dfm:mx0(30)} {regs.regs(2).lpi#1.dfm:mx0(31)} {regs.regs(2).lpi#1.dfm:mx0(32)} {regs.regs(2).lpi#1.dfm:mx0(33)} {regs.regs(2).lpi#1.dfm:mx0(34)} {regs.regs(2).lpi#1.dfm:mx0(35)} {regs.regs(2).lpi#1.dfm:mx0(36)} {regs.regs(2).lpi#1.dfm:mx0(37)} {regs.regs(2).lpi#1.dfm:mx0(38)} {regs.regs(2).lpi#1.dfm:mx0(39)} {regs.regs(2).lpi#1.dfm:mx0(40)} {regs.regs(2).lpi#1.dfm:mx0(41)} {regs.regs(2).lpi#1.dfm:mx0(42)} {regs.regs(2).lpi#1.dfm:mx0(43)} {regs.regs(2).lpi#1.dfm:mx0(44)} {regs.regs(2).lpi#1.dfm:mx0(45)} {regs.regs(2).lpi#1.dfm:mx0(46)} {regs.regs(2).lpi#1.dfm:mx0(47)} {regs.regs(2).lpi#1.dfm:mx0(48)} {regs.regs(2).lpi#1.dfm:mx0(49)} {regs.regs(2).lpi#1.dfm:mx0(50)} {regs.regs(2).lpi#1.dfm:mx0(51)} {regs.regs(2).lpi#1.dfm:mx0(52)} {regs.regs(2).lpi#1.dfm:mx0(53)} {regs.regs(2).lpi#1.dfm:mx0(54)} {regs.regs(2).lpi#1.dfm:mx0(55)} {regs.regs(2).lpi#1.dfm:mx0(56)} {regs.regs(2).lpi#1.dfm:mx0(57)} {regs.regs(2).lpi#1.dfm:mx0(58)} {regs.regs(2).lpi#1.dfm:mx0(59)} {regs.regs(2).lpi#1.dfm:mx0(60)} {regs.regs(2).lpi#1.dfm:mx0(61)} {regs.regs(2).lpi#1.dfm:mx0(62)} {regs.regs(2).lpi#1.dfm:mx0(63)} {regs.regs(2).lpi#1.dfm:mx0(64)} {regs.regs(2).lpi#1.dfm:mx0(65)} {regs.regs(2).lpi#1.dfm:mx0(66)} {regs.regs(2).lpi#1.dfm:mx0(67)} {regs.regs(2).lpi#1.dfm:mx0(68)} {regs.regs(2).lpi#1.dfm:mx0(69)} {regs.regs(2).lpi#1.dfm:mx0(70)} {regs.regs(2).lpi#1.dfm:mx0(71)} {regs.regs(2).lpi#1.dfm:mx0(72)} {regs.regs(2).lpi#1.dfm:mx0(73)} {regs.regs(2).lpi#1.dfm:mx0(74)} {regs.regs(2).lpi#1.dfm:mx0(75)} {regs.regs(2).lpi#1.dfm:mx0(76)} {regs.regs(2).lpi#1.dfm:mx0(77)} {regs.regs(2).lpi#1.dfm:mx0(78)} {regs.regs(2).lpi#1.dfm:mx0(79)} {regs.regs(2).lpi#1.dfm:mx0(80)} {regs.regs(2).lpi#1.dfm:mx0(81)} {regs.regs(2).lpi#1.dfm:mx0(82)} {regs.regs(2).lpi#1.dfm:mx0(83)} {regs.regs(2).lpi#1.dfm:mx0(84)} {regs.regs(2).lpi#1.dfm:mx0(85)} {regs.regs(2).lpi#1.dfm:mx0(86)} {regs.regs(2).lpi#1.dfm:mx0(87)} {regs.regs(2).lpi#1.dfm:mx0(88)} {regs.regs(2).lpi#1.dfm:mx0(89)} -attr xrf 44162 -attr oid 38 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(1).sva.dfm:mx0} 90 {regs.regs(1).sva.dfm:mx0(0)} {regs.regs(1).sva.dfm:mx0(1)} {regs.regs(1).sva.dfm:mx0(2)} {regs.regs(1).sva.dfm:mx0(3)} {regs.regs(1).sva.dfm:mx0(4)} {regs.regs(1).sva.dfm:mx0(5)} {regs.regs(1).sva.dfm:mx0(6)} {regs.regs(1).sva.dfm:mx0(7)} {regs.regs(1).sva.dfm:mx0(8)} {regs.regs(1).sva.dfm:mx0(9)} {regs.regs(1).sva.dfm:mx0(10)} {regs.regs(1).sva.dfm:mx0(11)} {regs.regs(1).sva.dfm:mx0(12)} {regs.regs(1).sva.dfm:mx0(13)} {regs.regs(1).sva.dfm:mx0(14)} {regs.regs(1).sva.dfm:mx0(15)} {regs.regs(1).sva.dfm:mx0(16)} {regs.regs(1).sva.dfm:mx0(17)} {regs.regs(1).sva.dfm:mx0(18)} {regs.regs(1).sva.dfm:mx0(19)} {regs.regs(1).sva.dfm:mx0(20)} {regs.regs(1).sva.dfm:mx0(21)} {regs.regs(1).sva.dfm:mx0(22)} {regs.regs(1).sva.dfm:mx0(23)} {regs.regs(1).sva.dfm:mx0(24)} {regs.regs(1).sva.dfm:mx0(25)} {regs.regs(1).sva.dfm:mx0(26)} {regs.regs(1).sva.dfm:mx0(27)} {regs.regs(1).sva.dfm:mx0(28)} {regs.regs(1).sva.dfm:mx0(29)} {regs.regs(1).sva.dfm:mx0(30)} {regs.regs(1).sva.dfm:mx0(31)} {regs.regs(1).sva.dfm:mx0(32)} {regs.regs(1).sva.dfm:mx0(33)} {regs.regs(1).sva.dfm:mx0(34)} {regs.regs(1).sva.dfm:mx0(35)} {regs.regs(1).sva.dfm:mx0(36)} {regs.regs(1).sva.dfm:mx0(37)} {regs.regs(1).sva.dfm:mx0(38)} {regs.regs(1).sva.dfm:mx0(39)} {regs.regs(1).sva.dfm:mx0(40)} {regs.regs(1).sva.dfm:mx0(41)} {regs.regs(1).sva.dfm:mx0(42)} {regs.regs(1).sva.dfm:mx0(43)} {regs.regs(1).sva.dfm:mx0(44)} {regs.regs(1).sva.dfm:mx0(45)} {regs.regs(1).sva.dfm:mx0(46)} {regs.regs(1).sva.dfm:mx0(47)} {regs.regs(1).sva.dfm:mx0(48)} {regs.regs(1).sva.dfm:mx0(49)} {regs.regs(1).sva.dfm:mx0(50)} {regs.regs(1).sva.dfm:mx0(51)} {regs.regs(1).sva.dfm:mx0(52)} {regs.regs(1).sva.dfm:mx0(53)} {regs.regs(1).sva.dfm:mx0(54)} {regs.regs(1).sva.dfm:mx0(55)} {regs.regs(1).sva.dfm:mx0(56)} {regs.regs(1).sva.dfm:mx0(57)} {regs.regs(1).sva.dfm:mx0(58)} {regs.regs(1).sva.dfm:mx0(59)} {regs.regs(1).sva.dfm:mx0(60)} {regs.regs(1).sva.dfm:mx0(61)} {regs.regs(1).sva.dfm:mx0(62)} {regs.regs(1).sva.dfm:mx0(63)} {regs.regs(1).sva.dfm:mx0(64)} {regs.regs(1).sva.dfm:mx0(65)} {regs.regs(1).sva.dfm:mx0(66)} {regs.regs(1).sva.dfm:mx0(67)} {regs.regs(1).sva.dfm:mx0(68)} {regs.regs(1).sva.dfm:mx0(69)} {regs.regs(1).sva.dfm:mx0(70)} {regs.regs(1).sva.dfm:mx0(71)} {regs.regs(1).sva.dfm:mx0(72)} {regs.regs(1).sva.dfm:mx0(73)} {regs.regs(1).sva.dfm:mx0(74)} {regs.regs(1).sva.dfm:mx0(75)} {regs.regs(1).sva.dfm:mx0(76)} {regs.regs(1).sva.dfm:mx0(77)} {regs.regs(1).sva.dfm:mx0(78)} {regs.regs(1).sva.dfm:mx0(79)} {regs.regs(1).sva.dfm:mx0(80)} {regs.regs(1).sva.dfm:mx0(81)} {regs.regs(1).sva.dfm:mx0(82)} {regs.regs(1).sva.dfm:mx0(83)} {regs.regs(1).sva.dfm:mx0(84)} {regs.regs(1).sva.dfm:mx0(85)} {regs.regs(1).sva.dfm:mx0(86)} {regs.regs(1).sva.dfm:mx0(87)} {regs.regs(1).sva.dfm:mx0(88)} {regs.regs(1).sva.dfm:mx0(89)} -attr xrf 44163 -attr oid 39 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(0).sva.dfm:mx0} 90 {regs.regs(0).sva.dfm:mx0(0)} {regs.regs(0).sva.dfm:mx0(1)} {regs.regs(0).sva.dfm:mx0(2)} {regs.regs(0).sva.dfm:mx0(3)} {regs.regs(0).sva.dfm:mx0(4)} {regs.regs(0).sva.dfm:mx0(5)} {regs.regs(0).sva.dfm:mx0(6)} {regs.regs(0).sva.dfm:mx0(7)} {regs.regs(0).sva.dfm:mx0(8)} {regs.regs(0).sva.dfm:mx0(9)} {regs.regs(0).sva.dfm:mx0(10)} {regs.regs(0).sva.dfm:mx0(11)} {regs.regs(0).sva.dfm:mx0(12)} {regs.regs(0).sva.dfm:mx0(13)} {regs.regs(0).sva.dfm:mx0(14)} {regs.regs(0).sva.dfm:mx0(15)} {regs.regs(0).sva.dfm:mx0(16)} {regs.regs(0).sva.dfm:mx0(17)} {regs.regs(0).sva.dfm:mx0(18)} {regs.regs(0).sva.dfm:mx0(19)} {regs.regs(0).sva.dfm:mx0(20)} {regs.regs(0).sva.dfm:mx0(21)} {regs.regs(0).sva.dfm:mx0(22)} {regs.regs(0).sva.dfm:mx0(23)} {regs.regs(0).sva.dfm:mx0(24)} {regs.regs(0).sva.dfm:mx0(25)} {regs.regs(0).sva.dfm:mx0(26)} {regs.regs(0).sva.dfm:mx0(27)} {regs.regs(0).sva.dfm:mx0(28)} {regs.regs(0).sva.dfm:mx0(29)} {regs.regs(0).sva.dfm:mx0(30)} {regs.regs(0).sva.dfm:mx0(31)} {regs.regs(0).sva.dfm:mx0(32)} {regs.regs(0).sva.dfm:mx0(33)} {regs.regs(0).sva.dfm:mx0(34)} {regs.regs(0).sva.dfm:mx0(35)} {regs.regs(0).sva.dfm:mx0(36)} {regs.regs(0).sva.dfm:mx0(37)} {regs.regs(0).sva.dfm:mx0(38)} {regs.regs(0).sva.dfm:mx0(39)} {regs.regs(0).sva.dfm:mx0(40)} {regs.regs(0).sva.dfm:mx0(41)} {regs.regs(0).sva.dfm:mx0(42)} {regs.regs(0).sva.dfm:mx0(43)} {regs.regs(0).sva.dfm:mx0(44)} {regs.regs(0).sva.dfm:mx0(45)} {regs.regs(0).sva.dfm:mx0(46)} {regs.regs(0).sva.dfm:mx0(47)} {regs.regs(0).sva.dfm:mx0(48)} {regs.regs(0).sva.dfm:mx0(49)} {regs.regs(0).sva.dfm:mx0(50)} {regs.regs(0).sva.dfm:mx0(51)} {regs.regs(0).sva.dfm:mx0(52)} {regs.regs(0).sva.dfm:mx0(53)} {regs.regs(0).sva.dfm:mx0(54)} {regs.regs(0).sva.dfm:mx0(55)} {regs.regs(0).sva.dfm:mx0(56)} {regs.regs(0).sva.dfm:mx0(57)} {regs.regs(0).sva.dfm:mx0(58)} {regs.regs(0).sva.dfm:mx0(59)} {regs.regs(0).sva.dfm:mx0(60)} {regs.regs(0).sva.dfm:mx0(61)} {regs.regs(0).sva.dfm:mx0(62)} {regs.regs(0).sva.dfm:mx0(63)} {regs.regs(0).sva.dfm:mx0(64)} {regs.regs(0).sva.dfm:mx0(65)} {regs.regs(0).sva.dfm:mx0(66)} {regs.regs(0).sva.dfm:mx0(67)} {regs.regs(0).sva.dfm:mx0(68)} {regs.regs(0).sva.dfm:mx0(69)} {regs.regs(0).sva.dfm:mx0(70)} {regs.regs(0).sva.dfm:mx0(71)} {regs.regs(0).sva.dfm:mx0(72)} {regs.regs(0).sva.dfm:mx0(73)} {regs.regs(0).sva.dfm:mx0(74)} {regs.regs(0).sva.dfm:mx0(75)} {regs.regs(0).sva.dfm:mx0(76)} {regs.regs(0).sva.dfm:mx0(77)} {regs.regs(0).sva.dfm:mx0(78)} {regs.regs(0).sva.dfm:mx0(79)} {regs.regs(0).sva.dfm:mx0(80)} {regs.regs(0).sva.dfm:mx0(81)} {regs.regs(0).sva.dfm:mx0(82)} {regs.regs(0).sva.dfm:mx0(83)} {regs.regs(0).sva.dfm:mx0(84)} {regs.regs(0).sva.dfm:mx0(85)} {regs.regs(0).sva.dfm:mx0(86)} {regs.regs(0).sva.dfm:mx0(87)} {regs.regs(0).sva.dfm:mx0(88)} {regs.regs(0).sva.dfm:mx0(89)} -attr xrf 44164 -attr oid 40 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {FRAME:p#1.sva#1(0)} -attr vt d
+load net {FRAME:p#1.sva#1(1)} -attr vt d
+load net {FRAME:p#1.sva#1(2)} -attr vt d
+load net {FRAME:p#1.sva#1(3)} -attr vt d
+load net {FRAME:p#1.sva#1(4)} -attr vt d
+load net {FRAME:p#1.sva#1(5)} -attr vt d
+load net {FRAME:p#1.sva#1(6)} -attr vt d
+load net {FRAME:p#1.sva#1(7)} -attr vt d
+load net {FRAME:p#1.sva#1(8)} -attr vt d
+load net {FRAME:p#1.sva#1(9)} -attr vt d
+load net {FRAME:p#1.sva#1(10)} -attr vt d
+load net {FRAME:p#1.sva#1(11)} -attr vt d
+load net {FRAME:p#1.sva#1(12)} -attr vt d
+load net {FRAME:p#1.sva#1(13)} -attr vt d
+load net {FRAME:p#1.sva#1(14)} -attr vt d
+load net {FRAME:p#1.sva#1(15)} -attr vt d
+load net {FRAME:p#1.sva#1(16)} -attr vt d
+load net {FRAME:p#1.sva#1(17)} -attr vt d
+load net {FRAME:p#1.sva#1(18)} -attr vt d
+load netBundle {FRAME:p#1.sva#1} 19 {FRAME:p#1.sva#1(0)} {FRAME:p#1.sva#1(1)} {FRAME:p#1.sva#1(2)} {FRAME:p#1.sva#1(3)} {FRAME:p#1.sva#1(4)} {FRAME:p#1.sva#1(5)} {FRAME:p#1.sva#1(6)} {FRAME:p#1.sva#1(7)} {FRAME:p#1.sva#1(8)} {FRAME:p#1.sva#1(9)} {FRAME:p#1.sva#1(10)} {FRAME:p#1.sva#1(11)} {FRAME:p#1.sva#1(12)} {FRAME:p#1.sva#1(13)} {FRAME:p#1.sva#1(14)} {FRAME:p#1.sva#1(15)} {FRAME:p#1.sva#1(16)} {FRAME:p#1.sva#1(17)} {FRAME:p#1.sva#1(18)} -attr xrf 44165 -attr oid 41 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.lpi#1.dfm(0)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(1)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(2)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(3)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(4)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(5)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(6)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(7)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(8)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(9)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(10)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(11)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(12)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(13)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(14)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(15)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(16)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(17)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(18)} -attr vt d
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+load net {b(2).lpi#1.dfm(0)} -attr vt d
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+load netBundle {b(2).lpi#1.dfm} 16 {b(2).lpi#1.dfm(0)} {b(2).lpi#1.dfm(1)} {b(2).lpi#1.dfm(2)} {b(2).lpi#1.dfm(3)} {b(2).lpi#1.dfm(4)} {b(2).lpi#1.dfm(5)} {b(2).lpi#1.dfm(6)} {b(2).lpi#1.dfm(7)} {b(2).lpi#1.dfm(8)} {b(2).lpi#1.dfm(9)} {b(2).lpi#1.dfm(10)} {b(2).lpi#1.dfm(11)} {b(2).lpi#1.dfm(12)} {b(2).lpi#1.dfm(13)} {b(2).lpi#1.dfm(14)} {b(2).lpi#1.dfm(15)} -attr xrf 44183 -attr oid 59 -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(0)} -attr vt d
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+load net {r(2).lpi#1.dfm(0)} -attr vt d
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+load net {b(0).lpi#1.dfm(0)} -attr vt d
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+load netBundle {b(0).lpi#1.dfm} 16 {b(0).lpi#1.dfm(0)} {b(0).lpi#1.dfm(1)} {b(0).lpi#1.dfm(2)} {b(0).lpi#1.dfm(3)} {b(0).lpi#1.dfm(4)} {b(0).lpi#1.dfm(5)} {b(0).lpi#1.dfm(6)} {b(0).lpi#1.dfm(7)} {b(0).lpi#1.dfm(8)} {b(0).lpi#1.dfm(9)} {b(0).lpi#1.dfm(10)} {b(0).lpi#1.dfm(11)} {b(0).lpi#1.dfm(12)} {b(0).lpi#1.dfm(13)} {b(0).lpi#1.dfm(14)} {b(0).lpi#1.dfm(15)} -attr xrf 44186 -attr oid 62 -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(0)} -attr vt d
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+load net {g(0).lpi#1.dfm(15)} -attr vt d
+load netBundle {g(0).lpi#1.dfm} 16 {g(0).lpi#1.dfm(0)} {g(0).lpi#1.dfm(1)} {g(0).lpi#1.dfm(2)} {g(0).lpi#1.dfm(3)} {g(0).lpi#1.dfm(4)} {g(0).lpi#1.dfm(5)} {g(0).lpi#1.dfm(6)} {g(0).lpi#1.dfm(7)} {g(0).lpi#1.dfm(8)} {g(0).lpi#1.dfm(9)} {g(0).lpi#1.dfm(10)} {g(0).lpi#1.dfm(11)} {g(0).lpi#1.dfm(12)} {g(0).lpi#1.dfm(13)} {g(0).lpi#1.dfm(14)} {g(0).lpi#1.dfm(15)} -attr xrf 44187 -attr oid 63 -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(0)} -attr vt d
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+load netBundle {r(0).lpi#1.dfm} 16 {r(0).lpi#1.dfm(0)} {r(0).lpi#1.dfm(1)} {r(0).lpi#1.dfm(2)} {r(0).lpi#1.dfm(3)} {r(0).lpi#1.dfm(4)} {r(0).lpi#1.dfm(5)} {r(0).lpi#1.dfm(6)} {r(0).lpi#1.dfm(7)} {r(0).lpi#1.dfm(8)} {r(0).lpi#1.dfm(9)} {r(0).lpi#1.dfm(10)} {r(0).lpi#1.dfm(11)} {r(0).lpi#1.dfm(12)} {r(0).lpi#1.dfm(13)} {r(0).lpi#1.dfm(14)} {r(0).lpi#1.dfm(15)} -attr xrf 44188 -attr oid 64 -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {i#6.sva#1(0)} -attr vt d
+load net {i#6.sva#1(1)} -attr vt d
+load netBundle {i#6.sva#1} 2 {i#6.sva#1(0)} {i#6.sva#1(1)} -attr xrf 44189 -attr oid 65 -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.lpi#1.dfm(0)} -attr vt d
+load net {i#6.lpi#1.dfm(1)} -attr vt d
+load netBundle {i#6.lpi#1.dfm} 2 {i#6.lpi#1.dfm(0)} {i#6.lpi#1.dfm(1)} -attr xrf 44190 -attr oid 66 -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {FRAME:for#1:conc#16(0)} -attr vt d
+load net {FRAME:for#1:conc#16(1)} -attr vt d
+load netBundle {FRAME:for#1:conc#16} 2 {FRAME:for#1:conc#16(0)} {FRAME:for#1:conc#16(1)} -attr xrf 44191 -attr oid 67 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for:conc#28(0)} -attr vt d
+load net {FRAME:for:conc#28(1)} -attr vt d
+load netBundle {FRAME:for:conc#28} 2 {FRAME:for:conc#28(0)} {FRAME:for:conc#28(1)} -attr xrf 44192 -attr oid 68 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:conc#30(0)} -attr vt d
+load net {FRAME:for:conc#30(1)} -attr vt d
+load netBundle {FRAME:for:conc#30} 2 {FRAME:for:conc#30(0)} {FRAME:for:conc#30(1)} -attr xrf 44193 -attr oid 69 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#30}
+load net {FRAME:for:conc#32(0)} -attr vt d
+load net {FRAME:for:conc#32(1)} -attr vt d
+load netBundle {FRAME:for:conc#32} 2 {FRAME:for:conc#32(0)} {FRAME:for:conc#32(1)} -attr xrf 44194 -attr oid 70 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#32}
+load net {mux.itm(0)} -attr vt d
+load net {mux.itm(1)} -attr vt d
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+load netBundle {mux.itm} 30 {mux.itm(0)} {mux.itm(1)} {mux.itm(2)} {mux.itm(3)} {mux.itm(4)} {mux.itm(5)} {mux.itm(6)} {mux.itm(7)} {mux.itm(8)} {mux.itm(9)} {mux.itm(10)} {mux.itm(11)} {mux.itm(12)} {mux.itm(13)} {mux.itm(14)} {mux.itm(15)} {mux.itm(16)} {mux.itm(17)} {mux.itm(18)} {mux.itm(19)} {mux.itm(20)} {mux.itm(21)} {mux.itm(22)} {mux.itm(23)} {mux.itm(24)} {mux.itm(25)} {mux.itm(26)} {mux.itm(27)} {mux.itm(28)} {mux.itm(29)} -attr xrf 44195 -attr oid 71 -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {FRAME:conc#21.itm(0)} -attr vt d
+load net {FRAME:conc#21.itm(1)} -attr vt d
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+load net {FRAME:conc#21.itm(29)} -attr vt d
+load netBundle {FRAME:conc#21.itm} 30 {FRAME:conc#21.itm(0)} {FRAME:conc#21.itm(1)} {FRAME:conc#21.itm(2)} {FRAME:conc#21.itm(3)} {FRAME:conc#21.itm(4)} {FRAME:conc#21.itm(5)} {FRAME:conc#21.itm(6)} {FRAME:conc#21.itm(7)} {FRAME:conc#21.itm(8)} {FRAME:conc#21.itm(9)} {FRAME:conc#21.itm(10)} {FRAME:conc#21.itm(11)} {FRAME:conc#21.itm(12)} {FRAME:conc#21.itm(13)} {FRAME:conc#21.itm(14)} {FRAME:conc#21.itm(15)} {FRAME:conc#21.itm(16)} {FRAME:conc#21.itm(17)} {FRAME:conc#21.itm(18)} {FRAME:conc#21.itm(19)} {FRAME:conc#21.itm(20)} {FRAME:conc#21.itm(21)} {FRAME:conc#21.itm(22)} {FRAME:conc#21.itm(23)} {FRAME:conc#21.itm(24)} {FRAME:conc#21.itm(25)} {FRAME:conc#21.itm(26)} {FRAME:conc#21.itm(27)} {FRAME:conc#21.itm(28)} {FRAME:conc#21.itm(29)} -attr xrf 44196 -attr oid 72 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(0)} -attr vt d
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+load net {FRAME:or.itm(8)} -attr vt d
+load net {FRAME:or.itm(9)} -attr vt d
+load netBundle {FRAME:or.itm} 10 {FRAME:or.itm(0)} {FRAME:or.itm(1)} {FRAME:or.itm(2)} {FRAME:or.itm(3)} {FRAME:or.itm(4)} {FRAME:or.itm(5)} {FRAME:or.itm(6)} {FRAME:or.itm(7)} {FRAME:or.itm(8)} {FRAME:or.itm(9)} -attr xrf 44197 -attr oid 73 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:acc#2.itm(0)} -attr vt d
+load net {FRAME:acc#2.itm(1)} -attr vt d
+load net {FRAME:acc#2.itm(2)} -attr vt d
+load net {FRAME:acc#2.itm(3)} -attr vt d
+load net {FRAME:acc#2.itm(4)} -attr vt d
+load net {FRAME:acc#2.itm(5)} -attr vt d
+load net {FRAME:acc#2.itm(6)} -attr vt d
+load net {FRAME:acc#2.itm(7)} -attr vt d
+load net {FRAME:acc#2.itm(8)} -attr vt d
+load net {FRAME:acc#2.itm(9)} -attr vt d
+load netBundle {FRAME:acc#2.itm} 10 {FRAME:acc#2.itm(0)} {FRAME:acc#2.itm(1)} {FRAME:acc#2.itm(2)} {FRAME:acc#2.itm(3)} {FRAME:acc#2.itm(4)} {FRAME:acc#2.itm(5)} {FRAME:acc#2.itm(6)} {FRAME:acc#2.itm(7)} {FRAME:acc#2.itm(8)} {FRAME:acc#2.itm(9)} -attr xrf 44198 -attr oid 74 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:conc#36.itm(0)} -attr vt d
+load net {FRAME:conc#36.itm(1)} -attr vt d
+load net {FRAME:conc#36.itm(2)} -attr vt d
+load net {FRAME:conc#36.itm(3)} -attr vt d
+load net {FRAME:conc#36.itm(4)} -attr vt d
+load net {FRAME:conc#36.itm(5)} -attr vt d
+load net {FRAME:conc#36.itm(6)} -attr vt d
+load net {FRAME:conc#36.itm(7)} -attr vt d
+load net {FRAME:conc#36.itm(8)} -attr vt d
+load net {FRAME:conc#36.itm(9)} -attr vt d
+load netBundle {FRAME:conc#36.itm} 10 {FRAME:conc#36.itm(0)} {FRAME:conc#36.itm(1)} {FRAME:conc#36.itm(2)} {FRAME:conc#36.itm(3)} {FRAME:conc#36.itm(4)} {FRAME:conc#36.itm(5)} {FRAME:conc#36.itm(6)} {FRAME:conc#36.itm(7)} {FRAME:conc#36.itm(8)} {FRAME:conc#36.itm(9)} -attr xrf 44199 -attr oid 75 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#40.itm(0)} -attr vt d
+load net {FRAME:acc#40.itm(1)} -attr vt d
+load net {FRAME:acc#40.itm(2)} -attr vt d
+load net {FRAME:acc#40.itm(3)} -attr vt d
+load net {FRAME:acc#40.itm(4)} -attr vt d
+load net {FRAME:acc#40.itm(5)} -attr vt d
+load net {FRAME:acc#40.itm(6)} -attr vt d
+load net {FRAME:acc#40.itm(7)} -attr vt d
+load net {FRAME:acc#40.itm(8)} -attr vt d
+load net {FRAME:acc#40.itm(9)} -attr vt d
+load netBundle {FRAME:acc#40.itm} 10 {FRAME:acc#40.itm(0)} {FRAME:acc#40.itm(1)} {FRAME:acc#40.itm(2)} {FRAME:acc#40.itm(3)} {FRAME:acc#40.itm(4)} {FRAME:acc#40.itm(5)} {FRAME:acc#40.itm(6)} {FRAME:acc#40.itm(7)} {FRAME:acc#40.itm(8)} {FRAME:acc#40.itm(9)} -attr xrf 44200 -attr oid 76 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#39.itm(0)} -attr vt d
+load net {FRAME:acc#39.itm(1)} -attr vt d
+load net {FRAME:acc#39.itm(2)} -attr vt d
+load net {FRAME:acc#39.itm(3)} -attr vt d
+load net {FRAME:acc#39.itm(4)} -attr vt d
+load net {FRAME:acc#39.itm(5)} -attr vt d
+load net {FRAME:acc#39.itm(6)} -attr vt d
+load net {FRAME:acc#39.itm(7)} -attr vt d
+load netBundle {FRAME:acc#39.itm} 8 {FRAME:acc#39.itm(0)} {FRAME:acc#39.itm(1)} {FRAME:acc#39.itm(2)} {FRAME:acc#39.itm(3)} {FRAME:acc#39.itm(4)} {FRAME:acc#39.itm(5)} {FRAME:acc#39.itm(6)} {FRAME:acc#39.itm(7)} -attr xrf 44201 -attr oid 77 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#38.itm(0)} -attr vt d
+load net {FRAME:acc#38.itm(1)} -attr vt d
+load net {FRAME:acc#38.itm(2)} -attr vt d
+load net {FRAME:acc#38.itm(3)} -attr vt d
+load net {FRAME:acc#38.itm(4)} -attr vt d
+load netBundle {FRAME:acc#38.itm} 5 {FRAME:acc#38.itm(0)} {FRAME:acc#38.itm(1)} {FRAME:acc#38.itm(2)} {FRAME:acc#38.itm(3)} {FRAME:acc#38.itm(4)} -attr xrf 44202 -attr oid 78 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {conc.itm(0)} -attr vt d
+load net {conc.itm(1)} -attr vt d
+load net {conc.itm(2)} -attr vt d
+load net {conc.itm(3)} -attr vt d
+load net {conc.itm(4)} -attr vt d
+load netBundle {conc.itm} 5 {conc.itm(0)} {conc.itm(1)} {conc.itm(2)} {conc.itm(3)} {conc.itm(4)} -attr xrf 44203 -attr oid 79 -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {conc#137.itm(0)} -attr vt d
+load net {conc#137.itm(1)} -attr vt d
+load net {conc#137.itm(2)} -attr vt d
+load net {conc#137.itm(3)} -attr vt d
+load net {conc#137.itm(4)} -attr vt d
+load net {conc#137.itm(5)} -attr vt d
+load net {conc#137.itm(6)} -attr vt d
+load net {conc#137.itm(7)} -attr vt d
+load net {conc#137.itm(8)} -attr vt d
+load net {conc#137.itm(9)} -attr vt d
+load netBundle {conc#137.itm} 10 {conc#137.itm(0)} {conc#137.itm(1)} {conc#137.itm(2)} {conc#137.itm(3)} {conc#137.itm(4)} {conc#137.itm(5)} {conc#137.itm(6)} {conc#137.itm(7)} {conc#137.itm(8)} {conc#137.itm(9)} -attr xrf 44204 -attr oid 80 -attr vt d -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {slc(FRAME:acc#3.psp.sva).itm(0)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#3.psp.sva).itm} 2 {slc(FRAME:acc#3.psp.sva).itm(0)} {slc(FRAME:acc#3.psp.sva).itm(1)} -attr xrf 44205 -attr oid 81 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva).itm}
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(3)} -attr vt d
+load netBundle {slc(FRAME:acc#3.psp.sva)#1.itm} 4 {slc(FRAME:acc#3.psp.sva)#1.itm(0)} {slc(FRAME:acc#3.psp.sva)#1.itm(1)} {slc(FRAME:acc#3.psp.sva)#1.itm(2)} {slc(FRAME:acc#3.psp.sva)#1.itm(3)} -attr xrf 44206 -attr oid 82 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#1.itm}
+load net {FRAME:or#3.itm(0)} -attr vt d
+load net {FRAME:or#3.itm(1)} -attr vt d
+load net {FRAME:or#3.itm(2)} -attr vt d
+load net {FRAME:or#3.itm(3)} -attr vt d
+load net {FRAME:or#3.itm(4)} -attr vt d
+load net {FRAME:or#3.itm(5)} -attr vt d
+load netBundle {FRAME:or#3.itm} 6 {FRAME:or#3.itm(0)} {FRAME:or#3.itm(1)} {FRAME:or#3.itm(2)} {FRAME:or#3.itm(3)} {FRAME:or#3.itm(4)} {FRAME:or#3.itm(5)} -attr xrf 44207 -attr oid 83 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(2)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(3)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(4)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(FRAME:acc#3.psp.sva)#2.itm} 6 {slc(FRAME:acc#3.psp.sva)#2.itm(0)} {slc(FRAME:acc#3.psp.sva)#2.itm(1)} {slc(FRAME:acc#3.psp.sva)#2.itm(2)} {slc(FRAME:acc#3.psp.sva)#2.itm(3)} {slc(FRAME:acc#3.psp.sva)#2.itm(4)} {slc(FRAME:acc#3.psp.sva)#2.itm(5)} -attr xrf 44208 -attr oid 84 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {conc#138.itm(0)} -attr vt d
+load net {conc#138.itm(1)} -attr vt d
+load net {conc#138.itm(2)} -attr vt d
+load net {conc#138.itm(3)} -attr vt d
+load net {conc#138.itm(4)} -attr vt d
+load net {conc#138.itm(5)} -attr vt d
+load netBundle {conc#138.itm} 6 {conc#138.itm(0)} {conc#138.itm(1)} {conc#138.itm(2)} {conc#138.itm(3)} {conc#138.itm(4)} {conc#138.itm(5)} -attr xrf 44209 -attr oid 85 -attr vt d -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {slc(FRAME:acc#4.psp.sva).itm(0)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#4.psp.sva).itm} 2 {slc(FRAME:acc#4.psp.sva).itm(0)} {slc(FRAME:acc#4.psp.sva).itm(1)} -attr xrf 44210 -attr oid 86 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#4.psp.sva).itm}
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(3)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(4)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(5)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(6)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(7)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(8)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(9)} -attr vt d
+load netBundle {slc(FRAME:acc#4.psp.sva)#1.itm} 10 {slc(FRAME:acc#4.psp.sva)#1.itm(0)} {slc(FRAME:acc#4.psp.sva)#1.itm(1)} {slc(FRAME:acc#4.psp.sva)#1.itm(2)} {slc(FRAME:acc#4.psp.sva)#1.itm(3)} {slc(FRAME:acc#4.psp.sva)#1.itm(4)} {slc(FRAME:acc#4.psp.sva)#1.itm(5)} {slc(FRAME:acc#4.psp.sva)#1.itm(6)} {slc(FRAME:acc#4.psp.sva)#1.itm(7)} {slc(FRAME:acc#4.psp.sva)#1.itm(8)} {slc(FRAME:acc#4.psp.sva)#1.itm(9)} -attr xrf 44211 -attr oid 87 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#4.psp.sva)#1.itm}
+load net {FRAME:acc#43.itm(0)} -attr vt d
+load net {FRAME:acc#43.itm(1)} -attr vt d
+load netBundle {FRAME:acc#43.itm} 2 {FRAME:acc#43.itm(0)} {FRAME:acc#43.itm(1)} -attr xrf 44212 -attr oid 88 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {slc(FRAME:mul.sdt).itm(0)} -attr vt d
+load net {slc(FRAME:mul.sdt).itm(1)} -attr vt d
+load netBundle {slc(FRAME:mul.sdt).itm} 2 {slc(FRAME:mul.sdt).itm(0)} {slc(FRAME:mul.sdt).itm(1)} -attr xrf 44213 -attr oid 89 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt).itm}
+load net {slc(FRAME:mul.sdt)#2.itm(0)} -attr vt d
+load net {slc(FRAME:mul.sdt)#2.itm(1)} -attr vt d
+load netBundle {slc(FRAME:mul.sdt)#2.itm} 2 {slc(FRAME:mul.sdt)#2.itm(0)} {slc(FRAME:mul.sdt)#2.itm(1)} -attr xrf 44214 -attr oid 90 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#2.itm}
+load net {FRAME:acc#44.itm(0)} -attr vt d
+load net {FRAME:acc#44.itm(1)} -attr vt d
+load net {FRAME:acc#44.itm(2)} -attr vt d
+load net {FRAME:acc#44.itm(3)} -attr vt d
+load net {FRAME:acc#44.itm(4)} -attr vt d
+load net {FRAME:acc#44.itm(5)} -attr vt d
+load netBundle {FRAME:acc#44.itm} 6 {FRAME:acc#44.itm(0)} {FRAME:acc#44.itm(1)} {FRAME:acc#44.itm(2)} {FRAME:acc#44.itm(3)} {FRAME:acc#44.itm(4)} {FRAME:acc#44.itm(5)} -attr xrf 44215 -attr oid 91 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {slc(FRAME:mul.sdt)#1.itm(0)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(1)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(2)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(3)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(4)} -attr vt d
+load netBundle {slc(FRAME:mul.sdt)#1.itm} 5 {slc(FRAME:mul.sdt)#1.itm(0)} {slc(FRAME:mul.sdt)#1.itm(1)} {slc(FRAME:mul.sdt)#1.itm(2)} {slc(FRAME:mul.sdt)#1.itm(3)} {slc(FRAME:mul.sdt)#1.itm(4)} -attr xrf 44216 -attr oid 92 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {exs#3.itm(0)} -attr vt d
+load net {exs#3.itm(1)} -attr vt d
+load net {exs#3.itm(2)} -attr vt d
+load net {exs#3.itm(3)} -attr vt d
+load net {exs#3.itm(4)} -attr vt d
+load netBundle {exs#3.itm} 5 {exs#3.itm(0)} {exs#3.itm(1)} {exs#3.itm(2)} {exs#3.itm(3)} {exs#3.itm(4)} -attr xrf 44217 -attr oid 93 -attr vt d -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {conc#139.itm(0)} -attr vt d
+load net {conc#139.itm(1)} -attr vt d
+load net {conc#139.itm(2)} -attr vt d
+load netBundle {conc#139.itm} 3 {conc#139.itm(0)} {conc#139.itm(1)} {conc#139.itm(2)} -attr xrf 44218 -attr oid 94 -attr vt d -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {FRAME:mul#1.itm(0)} -attr vt d
+load net {FRAME:mul#1.itm(1)} -attr vt d
+load net {FRAME:mul#1.itm(2)} -attr vt d
+load net {FRAME:mul#1.itm(3)} -attr vt d
+load net {FRAME:mul#1.itm(4)} -attr vt d
+load net {FRAME:mul#1.itm(5)} -attr vt d
+load net {FRAME:mul#1.itm(6)} -attr vt d
+load net {FRAME:mul#1.itm(7)} -attr vt d
+load net {FRAME:mul#1.itm(8)} -attr vt d
+load netBundle {FRAME:mul#1.itm} 9 {FRAME:mul#1.itm(0)} {FRAME:mul#1.itm(1)} {FRAME:mul#1.itm(2)} {FRAME:mul#1.itm(3)} {FRAME:mul#1.itm(4)} {FRAME:mul#1.itm(5)} {FRAME:mul#1.itm(6)} {FRAME:mul#1.itm(7)} {FRAME:mul#1.itm(8)} -attr xrf 44219 -attr oid 95 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {slc(red#2.sg1.sva)#13.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#13.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#13.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#13.itm} 3 {slc(red#2.sg1.sva)#13.itm(0)} {slc(red#2.sg1.sva)#13.itm(1)} {slc(red#2.sg1.sva)#13.itm(2)} -attr xrf 44220 -attr oid 96 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {slc(red#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(2)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(3)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(4)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(5)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#1.itm} 6 {slc(red#2.sg1.sva)#1.itm(0)} {slc(red#2.sg1.sva)#1.itm(1)} {slc(red#2.sg1.sva)#1.itm(2)} {slc(red#2.sg1.sva)#1.itm(3)} {slc(red#2.sg1.sva)#1.itm(4)} {slc(red#2.sg1.sva)#1.itm(5)} -attr xrf 44221 -attr oid 97 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {FRAME:acc#37.itm(0)} -attr vt d
+load net {FRAME:acc#37.itm(1)} -attr vt d
+load net {FRAME:acc#37.itm(2)} -attr vt d
+load net {FRAME:acc#37.itm(3)} -attr vt d
+load net {FRAME:acc#37.itm(4)} -attr vt d
+load netBundle {FRAME:acc#37.itm} 5 {FRAME:acc#37.itm(0)} {FRAME:acc#37.itm(1)} {FRAME:acc#37.itm(2)} {FRAME:acc#37.itm(3)} {FRAME:acc#37.itm(4)} -attr xrf 44222 -attr oid 98 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#36.itm(0)} -attr vt d
+load net {FRAME:acc#36.itm(1)} -attr vt d
+load net {FRAME:acc#36.itm(2)} -attr vt d
+load net {FRAME:acc#36.itm(3)} -attr vt d
+load netBundle {FRAME:acc#36.itm} 4 {FRAME:acc#36.itm(0)} {FRAME:acc#36.itm(1)} {FRAME:acc#36.itm(2)} {FRAME:acc#36.itm(3)} -attr xrf 44223 -attr oid 99 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {conc#141.itm(0)} -attr vt d
+load net {conc#141.itm(1)} -attr vt d
+load net {conc#141.itm(2)} -attr vt d
+load netBundle {conc#141.itm} 3 {conc#141.itm(0)} {conc#141.itm(1)} {conc#141.itm(2)} -attr xrf 44224 -attr oid 100 -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {conc#142.itm(0)} -attr vt d
+load net {conc#142.itm(1)} -attr vt d
+load net {conc#142.itm(2)} -attr vt d
+load net {conc#142.itm(3)} -attr vt d
+load net {conc#142.itm(4)} -attr vt d
+load netBundle {conc#142.itm} 5 {conc#142.itm(0)} {conc#142.itm(1)} {conc#142.itm(2)} {conc#142.itm(3)} {conc#142.itm(4)} -attr xrf 44225 -attr oid 101 -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {slc(acc.imod#9.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#9.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#9.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#9.sva)#1.itm} 3 {slc(acc.imod#9.sva)#1.itm(0)} {slc(acc.imod#9.sva)#1.itm(1)} {slc(acc.imod#9.sva)#1.itm(2)} -attr xrf 44226 -attr oid 102 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#9.sva)#1.itm}
+load net {FRAME:conc#33.itm(0)} -attr vt d
+load net {FRAME:conc#33.itm(1)} -attr vt d
+load net {FRAME:conc#33.itm(2)} -attr vt d
+load net {FRAME:conc#33.itm(3)} -attr vt d
+load netBundle {FRAME:conc#33.itm} 4 {FRAME:conc#33.itm(0)} {FRAME:conc#33.itm(1)} {FRAME:conc#33.itm(2)} {FRAME:conc#33.itm(3)} -attr xrf 44227 -attr oid 103 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(0)} -attr vt d
+load net {FRAME:not#5.itm(1)} -attr vt d
+load net {FRAME:not#5.itm(2)} -attr vt d
+load netBundle {FRAME:not#5.itm} 3 {FRAME:not#5.itm(0)} {FRAME:not#5.itm(1)} {FRAME:not#5.itm(2)} -attr xrf 44228 -attr oid 104 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {slc(acc.imod#9.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#9.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#9.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#9.sva)#2.itm} 3 {slc(acc.imod#9.sva)#2.itm(0)} {slc(acc.imod#9.sva)#2.itm(1)} {slc(acc.imod#9.sva)#2.itm(2)} -attr xrf 44229 -attr oid 105 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#9.sva)#2.itm}
+load net {slc(acc.imod#9.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#9.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#9.sva)#4.itm} 2 {slc(acc.imod#9.sva)#4.itm(0)} {slc(acc.imod#9.sva)#4.itm(1)} -attr xrf 44230 -attr oid 106 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#9.sva)#4.itm}
+load net {FRAME:not#6.itm(0)} -attr vt d
+load net {FRAME:not#6.itm(1)} -attr vt d
+load net {FRAME:not#6.itm(2)} -attr vt d
+load netBundle {FRAME:not#6.itm} 3 {FRAME:not#6.itm(0)} {FRAME:not#6.itm(1)} {FRAME:not#6.itm(2)} -attr xrf 44231 -attr oid 107 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {slc(red#2.sg1.sva)#8.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#8.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#8.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#8.itm} 3 {slc(red#2.sg1.sva)#8.itm(0)} {slc(red#2.sg1.sva)#8.itm(1)} {slc(red#2.sg1.sva)#8.itm(2)} -attr xrf 44232 -attr oid 108 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {FRAME:mul#4.itm(0)} -attr vt d
+load net {FRAME:mul#4.itm(1)} -attr vt d
+load net {FRAME:mul#4.itm(2)} -attr vt d
+load net {FRAME:mul#4.itm(3)} -attr vt d
+load net {FRAME:mul#4.itm(4)} -attr vt d
+load net {FRAME:mul#4.itm(5)} -attr vt d
+load net {FRAME:mul#4.itm(6)} -attr vt d
+load net {FRAME:mul#4.itm(7)} -attr vt d
+load net {FRAME:mul#4.itm(8)} -attr vt d
+load net {FRAME:mul#4.itm(9)} -attr vt d
+load net {FRAME:mul#4.itm(10)} -attr vt d
+load netBundle {FRAME:mul#4.itm} 11 {FRAME:mul#4.itm(0)} {FRAME:mul#4.itm(1)} {FRAME:mul#4.itm(2)} {FRAME:mul#4.itm(3)} {FRAME:mul#4.itm(4)} {FRAME:mul#4.itm(5)} {FRAME:mul#4.itm(6)} {FRAME:mul#4.itm(7)} {FRAME:mul#4.itm(8)} {FRAME:mul#4.itm(9)} {FRAME:mul#4.itm(10)} -attr xrf 44233 -attr oid 109 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {slc(blue#2.sg1.sva)#10.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#10.itm(1)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#10.itm} 2 {slc(blue#2.sg1.sva)#10.itm(0)} {slc(blue#2.sg1.sva)#10.itm(1)} -attr xrf 44234 -attr oid 110 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#10.itm}
+load net {FRAME:mul#5.itm(0)} -attr vt d
+load net {FRAME:mul#5.itm(1)} -attr vt d
+load net {FRAME:mul#5.itm(2)} -attr vt d
+load net {FRAME:mul#5.itm(3)} -attr vt d
+load net {FRAME:mul#5.itm(4)} -attr vt d
+load net {FRAME:mul#5.itm(5)} -attr vt d
+load net {FRAME:mul#5.itm(6)} -attr vt d
+load net {FRAME:mul#5.itm(7)} -attr vt d
+load net {FRAME:mul#5.itm(8)} -attr vt d
+load netBundle {FRAME:mul#5.itm} 9 {FRAME:mul#5.itm(0)} {FRAME:mul#5.itm(1)} {FRAME:mul#5.itm(2)} {FRAME:mul#5.itm(3)} {FRAME:mul#5.itm(4)} {FRAME:mul#5.itm(5)} {FRAME:mul#5.itm(6)} {FRAME:mul#5.itm(7)} {FRAME:mul#5.itm(8)} -attr xrf 44235 -attr oid 111 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {slc(blue#2.sg1.sva)#11.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#11.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#11.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#11.itm} 3 {slc(blue#2.sg1.sva)#11.itm(0)} {slc(blue#2.sg1.sva)#11.itm(1)} {slc(blue#2.sg1.sva)#11.itm(2)} -attr xrf 44236 -attr oid 112 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {slc(blue#2.sg1.sva)#2.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(2)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(3)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(4)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#2.itm} 6 {slc(blue#2.sg1.sva)#2.itm(0)} {slc(blue#2.sg1.sva)#2.itm(1)} {slc(blue#2.sg1.sva)#2.itm(2)} {slc(blue#2.sg1.sva)#2.itm(3)} {slc(blue#2.sg1.sva)#2.itm(4)} {slc(blue#2.sg1.sva)#2.itm(5)} -attr xrf 44237 -attr oid 113 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {FRAME:acc#30.itm(0)} -attr vt d
+load net {FRAME:acc#30.itm(1)} -attr vt d
+load net {FRAME:acc#30.itm(2)} -attr vt d
+load net {FRAME:acc#30.itm(3)} -attr vt d
+load net {FRAME:acc#30.itm(4)} -attr vt d
+load netBundle {FRAME:acc#30.itm} 5 {FRAME:acc#30.itm(0)} {FRAME:acc#30.itm(1)} {FRAME:acc#30.itm(2)} {FRAME:acc#30.itm(3)} {FRAME:acc#30.itm(4)} -attr xrf 44238 -attr oid 114 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#29.itm(0)} -attr vt d
+load net {FRAME:acc#29.itm(1)} -attr vt d
+load net {FRAME:acc#29.itm(2)} -attr vt d
+load net {FRAME:acc#29.itm(3)} -attr vt d
+load netBundle {FRAME:acc#29.itm} 4 {FRAME:acc#29.itm(0)} {FRAME:acc#29.itm(1)} {FRAME:acc#29.itm(2)} {FRAME:acc#29.itm(3)} -attr xrf 44239 -attr oid 115 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {conc#143.itm(0)} -attr vt d
+load net {conc#143.itm(1)} -attr vt d
+load net {conc#143.itm(2)} -attr vt d
+load netBundle {conc#143.itm} 3 {conc#143.itm(0)} {conc#143.itm(1)} {conc#143.itm(2)} -attr xrf 44240 -attr oid 116 -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {conc#144.itm(0)} -attr vt d
+load net {conc#144.itm(1)} -attr vt d
+load net {conc#144.itm(2)} -attr vt d
+load net {conc#144.itm(3)} -attr vt d
+load net {conc#144.itm(4)} -attr vt d
+load netBundle {conc#144.itm} 5 {conc#144.itm(0)} {conc#144.itm(1)} {conc#144.itm(2)} {conc#144.itm(3)} {conc#144.itm(4)} -attr xrf 44241 -attr oid 117 -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {slc(acc.imod#13.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#13.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#13.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#13.sva)#1.itm} 3 {slc(acc.imod#13.sva)#1.itm(0)} {slc(acc.imod#13.sva)#1.itm(1)} {slc(acc.imod#13.sva)#1.itm(2)} -attr xrf 44242 -attr oid 118 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#13.sva)#1.itm}
+load net {FRAME:conc#29.itm(0)} -attr vt d
+load net {FRAME:conc#29.itm(1)} -attr vt d
+load net {FRAME:conc#29.itm(2)} -attr vt d
+load net {FRAME:conc#29.itm(3)} -attr vt d
+load netBundle {FRAME:conc#29.itm} 4 {FRAME:conc#29.itm(0)} {FRAME:conc#29.itm(1)} {FRAME:conc#29.itm(2)} {FRAME:conc#29.itm(3)} -attr xrf 44243 -attr oid 119 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(0)} -attr vt d
+load net {FRAME:not#21.itm(1)} -attr vt d
+load net {FRAME:not#21.itm(2)} -attr vt d
+load netBundle {FRAME:not#21.itm} 3 {FRAME:not#21.itm(0)} {FRAME:not#21.itm(1)} {FRAME:not#21.itm(2)} -attr xrf 44244 -attr oid 120 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {slc(acc.imod#13.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#13.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#13.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#13.sva)#2.itm} 3 {slc(acc.imod#13.sva)#2.itm(0)} {slc(acc.imod#13.sva)#2.itm(1)} {slc(acc.imod#13.sva)#2.itm(2)} -attr xrf 44245 -attr oid 121 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#13.sva)#2.itm}
+load net {slc(acc.imod#13.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#13.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#13.sva)#4.itm} 2 {slc(acc.imod#13.sva)#4.itm(0)} {slc(acc.imod#13.sva)#4.itm(1)} -attr xrf 44246 -attr oid 122 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#13.sva)#4.itm}
+load net {FRAME:not#22.itm(0)} -attr vt d
+load net {FRAME:not#22.itm(1)} -attr vt d
+load net {FRAME:not#22.itm(2)} -attr vt d
+load netBundle {FRAME:not#22.itm} 3 {FRAME:not#22.itm(0)} {FRAME:not#22.itm(1)} {FRAME:not#22.itm(2)} -attr xrf 44247 -attr oid 123 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {slc(blue#2.sg1.sva)#9.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#9.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#9.itm} 3 {slc(blue#2.sg1.sva)#9.itm(0)} {slc(blue#2.sg1.sva)#9.itm(1)} {slc(blue#2.sg1.sva)#9.itm(2)} -attr xrf 44248 -attr oid 124 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {FRAME:mul#2.itm(0)} -attr vt d
+load net {FRAME:mul#2.itm(1)} -attr vt d
+load net {FRAME:mul#2.itm(2)} -attr vt d
+load net {FRAME:mul#2.itm(3)} -attr vt d
+load net {FRAME:mul#2.itm(4)} -attr vt d
+load net {FRAME:mul#2.itm(5)} -attr vt d
+load net {FRAME:mul#2.itm(6)} -attr vt d
+load net {FRAME:mul#2.itm(7)} -attr vt d
+load net {FRAME:mul#2.itm(8)} -attr vt d
+load net {FRAME:mul#2.itm(9)} -attr vt d
+load net {FRAME:mul#2.itm(10)} -attr vt d
+load netBundle {FRAME:mul#2.itm} 11 {FRAME:mul#2.itm(0)} {FRAME:mul#2.itm(1)} {FRAME:mul#2.itm(2)} {FRAME:mul#2.itm(3)} {FRAME:mul#2.itm(4)} {FRAME:mul#2.itm(5)} {FRAME:mul#2.itm(6)} {FRAME:mul#2.itm(7)} {FRAME:mul#2.itm(8)} {FRAME:mul#2.itm(9)} {FRAME:mul#2.itm(10)} -attr xrf 44249 -attr oid 125 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {slc(green#2.sg1.sva)#10.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#10.itm(1)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#10.itm} 2 {slc(green#2.sg1.sva)#10.itm(0)} {slc(green#2.sg1.sva)#10.itm(1)} -attr xrf 44250 -attr oid 126 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#10.itm}
+load net {FRAME:mul#3.itm(0)} -attr vt d
+load net {FRAME:mul#3.itm(1)} -attr vt d
+load net {FRAME:mul#3.itm(2)} -attr vt d
+load net {FRAME:mul#3.itm(3)} -attr vt d
+load net {FRAME:mul#3.itm(4)} -attr vt d
+load net {FRAME:mul#3.itm(5)} -attr vt d
+load net {FRAME:mul#3.itm(6)} -attr vt d
+load net {FRAME:mul#3.itm(7)} -attr vt d
+load net {FRAME:mul#3.itm(8)} -attr vt d
+load netBundle {FRAME:mul#3.itm} 9 {FRAME:mul#3.itm(0)} {FRAME:mul#3.itm(1)} {FRAME:mul#3.itm(2)} {FRAME:mul#3.itm(3)} {FRAME:mul#3.itm(4)} {FRAME:mul#3.itm(5)} {FRAME:mul#3.itm(6)} {FRAME:mul#3.itm(7)} {FRAME:mul#3.itm(8)} -attr xrf 44251 -attr oid 127 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {slc(green#2.sg1.sva)#11.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#11.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#11.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#11.itm} 3 {slc(green#2.sg1.sva)#11.itm(0)} {slc(green#2.sg1.sva)#11.itm(1)} {slc(green#2.sg1.sva)#11.itm(2)} -attr xrf 44252 -attr oid 128 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {slc(green#2.sg1.sva)#2.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(2)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(3)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(4)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#2.itm} 6 {slc(green#2.sg1.sva)#2.itm(0)} {slc(green#2.sg1.sva)#2.itm(1)} {slc(green#2.sg1.sva)#2.itm(2)} {slc(green#2.sg1.sva)#2.itm(3)} {slc(green#2.sg1.sva)#2.itm(4)} {slc(green#2.sg1.sva)#2.itm(5)} -attr xrf 44253 -attr oid 129 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {FRAME:acc#18.itm(0)} -attr vt d
+load net {FRAME:acc#18.itm(1)} -attr vt d
+load net {FRAME:acc#18.itm(2)} -attr vt d
+load net {FRAME:acc#18.itm(3)} -attr vt d
+load net {FRAME:acc#18.itm(4)} -attr vt d
+load netBundle {FRAME:acc#18.itm} 5 {FRAME:acc#18.itm(0)} {FRAME:acc#18.itm(1)} {FRAME:acc#18.itm(2)} {FRAME:acc#18.itm(3)} {FRAME:acc#18.itm(4)} -attr xrf 44254 -attr oid 130 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#17.itm(0)} -attr vt d
+load net {FRAME:acc#17.itm(1)} -attr vt d
+load net {FRAME:acc#17.itm(2)} -attr vt d
+load net {FRAME:acc#17.itm(3)} -attr vt d
+load netBundle {FRAME:acc#17.itm} 4 {FRAME:acc#17.itm(0)} {FRAME:acc#17.itm(1)} {FRAME:acc#17.itm(2)} {FRAME:acc#17.itm(3)} -attr xrf 44255 -attr oid 131 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {conc#145.itm(0)} -attr vt d
+load net {conc#145.itm(1)} -attr vt d
+load net {conc#145.itm(2)} -attr vt d
+load netBundle {conc#145.itm} 3 {conc#145.itm(0)} {conc#145.itm(1)} {conc#145.itm(2)} -attr xrf 44256 -attr oid 132 -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {conc#146.itm(0)} -attr vt d
+load net {conc#146.itm(1)} -attr vt d
+load net {conc#146.itm(2)} -attr vt d
+load net {conc#146.itm(3)} -attr vt d
+load net {conc#146.itm(4)} -attr vt d
+load netBundle {conc#146.itm} 5 {conc#146.itm(0)} {conc#146.itm(1)} {conc#146.itm(2)} {conc#146.itm(3)} {conc#146.itm(4)} -attr xrf 44257 -attr oid 133 -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {slc(acc.imod#11.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#11.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#11.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#11.sva)#1.itm} 3 {slc(acc.imod#11.sva)#1.itm(0)} {slc(acc.imod#11.sva)#1.itm(1)} {slc(acc.imod#11.sva)#1.itm(2)} -attr xrf 44258 -attr oid 134 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#1.itm}
+load net {FRAME:conc#25.itm(0)} -attr vt d
+load net {FRAME:conc#25.itm(1)} -attr vt d
+load net {FRAME:conc#25.itm(2)} -attr vt d
+load net {FRAME:conc#25.itm(3)} -attr vt d
+load netBundle {FRAME:conc#25.itm} 4 {FRAME:conc#25.itm(0)} {FRAME:conc#25.itm(1)} {FRAME:conc#25.itm(2)} {FRAME:conc#25.itm(3)} -attr xrf 44259 -attr oid 135 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(0)} -attr vt d
+load net {FRAME:not#13.itm(1)} -attr vt d
+load net {FRAME:not#13.itm(2)} -attr vt d
+load netBundle {FRAME:not#13.itm} 3 {FRAME:not#13.itm(0)} {FRAME:not#13.itm(1)} {FRAME:not#13.itm(2)} -attr xrf 44260 -attr oid 136 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {slc(acc.imod#11.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#11.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#11.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#11.sva)#2.itm} 3 {slc(acc.imod#11.sva)#2.itm(0)} {slc(acc.imod#11.sva)#2.itm(1)} {slc(acc.imod#11.sva)#2.itm(2)} -attr xrf 44261 -attr oid 137 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#2.itm}
+load net {slc(acc.imod#11.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#11.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#11.sva)#4.itm} 2 {slc(acc.imod#11.sva)#4.itm(0)} {slc(acc.imod#11.sva)#4.itm(1)} -attr xrf 44262 -attr oid 138 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#4.itm}
+load net {FRAME:not#14.itm(0)} -attr vt d
+load net {FRAME:not#14.itm(1)} -attr vt d
+load net {FRAME:not#14.itm(2)} -attr vt d
+load netBundle {FRAME:not#14.itm} 3 {FRAME:not#14.itm(0)} {FRAME:not#14.itm(1)} {FRAME:not#14.itm(2)} -attr xrf 44263 -attr oid 139 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {slc(green#2.sg1.sva)#9.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#9.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#9.itm} 3 {slc(green#2.sg1.sva)#9.itm(0)} {slc(green#2.sg1.sva)#9.itm(1)} {slc(green#2.sg1.sva)#9.itm(2)} -attr xrf 44264 -attr oid 140 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {mux#1.itm(0)} -attr vt d
+load net {mux#1.itm(1)} -attr vt d
+load netBundle {mux#1.itm} 2 {mux#1.itm(0)} {mux#1.itm(1)} -attr xrf 44265 -attr oid 141 -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {FRAME:for:and#13.itm(0)} -attr vt d
+load net {FRAME:for:and#13.itm(1)} -attr vt d
+load netBundle {FRAME:for:and#13.itm} 2 {FRAME:for:and#13.itm(0)} {FRAME:for:and#13.itm(1)} -attr xrf 44266 -attr oid 142 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#13.itm}
+load net {FRAME:for:exs#30.itm(0)} -attr vt d
+load net {FRAME:for:exs#30.itm(1)} -attr vt d
+load netBundle {FRAME:for:exs#30.itm} 2 {FRAME:for:exs#30.itm(0)} {FRAME:for:exs#30.itm(1)} -attr xrf 44267 -attr oid 143 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#30.itm}
+load net {mux#8.itm(0)} -attr vt d
+load net {mux#8.itm(1)} -attr vt d
+load net {mux#8.itm(2)} -attr vt d
+load net {mux#8.itm(3)} -attr vt d
+load net {mux#8.itm(4)} -attr vt d
+load net {mux#8.itm(5)} -attr vt d
+load net {mux#8.itm(6)} -attr vt d
+load net {mux#8.itm(7)} -attr vt d
+load net {mux#8.itm(8)} -attr vt d
+load net {mux#8.itm(9)} -attr vt d
+load net {mux#8.itm(10)} -attr vt d
+load net {mux#8.itm(11)} -attr vt d
+load net {mux#8.itm(12)} -attr vt d
+load net {mux#8.itm(13)} -attr vt d
+load net {mux#8.itm(14)} -attr vt d
+load netBundle {mux#8.itm} 15 {mux#8.itm(0)} {mux#8.itm(1)} {mux#8.itm(2)} {mux#8.itm(3)} {mux#8.itm(4)} {mux#8.itm(5)} {mux#8.itm(6)} {mux#8.itm(7)} {mux#8.itm(8)} {mux#8.itm(9)} {mux#8.itm(10)} {mux#8.itm(11)} {mux#8.itm(12)} {mux#8.itm(13)} {mux#8.itm(14)} -attr xrf 44268 -attr oid 144 -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {FRAME:for:acc#28.itm(0)} -attr vt d
+load net {FRAME:for:acc#28.itm(1)} -attr vt d
+load net {FRAME:for:acc#28.itm(2)} -attr vt d
+load net {FRAME:for:acc#28.itm(3)} -attr vt d
+load net {FRAME:for:acc#28.itm(4)} -attr vt d
+load net {FRAME:for:acc#28.itm(5)} -attr vt d
+load net {FRAME:for:acc#28.itm(6)} -attr vt d
+load net {FRAME:for:acc#28.itm(7)} -attr vt d
+load net {FRAME:for:acc#28.itm(8)} -attr vt d
+load net {FRAME:for:acc#28.itm(9)} -attr vt d
+load net {FRAME:for:acc#28.itm(10)} -attr vt d
+load net {FRAME:for:acc#28.itm(11)} -attr vt d
+load net {FRAME:for:acc#28.itm(12)} -attr vt d
+load net {FRAME:for:acc#28.itm(13)} -attr vt d
+load net {FRAME:for:acc#28.itm(14)} -attr vt d
+load netBundle {FRAME:for:acc#28.itm} 15 {FRAME:for:acc#28.itm(0)} {FRAME:for:acc#28.itm(1)} {FRAME:for:acc#28.itm(2)} {FRAME:for:acc#28.itm(3)} {FRAME:for:acc#28.itm(4)} {FRAME:for:acc#28.itm(5)} {FRAME:for:acc#28.itm(6)} {FRAME:for:acc#28.itm(7)} {FRAME:for:acc#28.itm(8)} {FRAME:for:acc#28.itm(9)} {FRAME:for:acc#28.itm(10)} {FRAME:for:acc#28.itm(11)} {FRAME:for:acc#28.itm(12)} {FRAME:for:acc#28.itm(13)} {FRAME:for:acc#28.itm(14)} -attr xrf 44269 -attr oid 145 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:mul#5.itm(0)} -attr vt d
+load net {FRAME:for:mul#5.itm(1)} -attr vt d
+load net {FRAME:for:mul#5.itm(2)} -attr vt d
+load net {FRAME:for:mul#5.itm(3)} -attr vt d
+load net {FRAME:for:mul#5.itm(4)} -attr vt d
+load net {FRAME:for:mul#5.itm(5)} -attr vt d
+load net {FRAME:for:mul#5.itm(6)} -attr vt d
+load net {FRAME:for:mul#5.itm(7)} -attr vt d
+load net {FRAME:for:mul#5.itm(8)} -attr vt d
+load net {FRAME:for:mul#5.itm(9)} -attr vt d
+load net {FRAME:for:mul#5.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#5.itm} 11 {FRAME:for:mul#5.itm(0)} {FRAME:for:mul#5.itm(1)} {FRAME:for:mul#5.itm(2)} {FRAME:for:mul#5.itm(3)} {FRAME:for:mul#5.itm(4)} {FRAME:for:mul#5.itm(5)} {FRAME:for:mul#5.itm(6)} {FRAME:for:mul#5.itm(7)} {FRAME:for:mul#5.itm(8)} {FRAME:for:mul#5.itm(9)} {FRAME:for:mul#5.itm(10)} -attr xrf 44270 -attr oid 146 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {regs.operator[]#23:mux.itm(0)} -attr vt d
+load net {regs.operator[]#23:mux.itm(1)} -attr vt d
+load net {regs.operator[]#23:mux.itm(2)} -attr vt d
+load net {regs.operator[]#23:mux.itm(3)} -attr vt d
+load net {regs.operator[]#23:mux.itm(4)} -attr vt d
+load net {regs.operator[]#23:mux.itm(5)} -attr vt d
+load net {regs.operator[]#23:mux.itm(6)} -attr vt d
+load net {regs.operator[]#23:mux.itm(7)} -attr vt d
+load net {regs.operator[]#23:mux.itm(8)} -attr vt d
+load net {regs.operator[]#23:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#23:mux.itm} 10 {regs.operator[]#23:mux.itm(0)} {regs.operator[]#23:mux.itm(1)} {regs.operator[]#23:mux.itm(2)} {regs.operator[]#23:mux.itm(3)} {regs.operator[]#23:mux.itm(4)} {regs.operator[]#23:mux.itm(5)} {regs.operator[]#23:mux.itm(6)} {regs.operator[]#23:mux.itm(7)} {regs.operator[]#23:mux.itm(8)} {regs.operator[]#23:mux.itm(9)} -attr xrf 44271 -attr oid 147 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(9)} -attr xrf 44272 -attr oid 148 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr xrf 44273 -attr oid 149 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr xrf 44274 -attr oid 150 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {mux#9.itm(0)} -attr vt d
+load net {mux#9.itm(1)} -attr vt d
+load net {mux#9.itm(2)} -attr vt d
+load net {mux#9.itm(3)} -attr vt d
+load net {mux#9.itm(4)} -attr vt d
+load net {mux#9.itm(5)} -attr vt d
+load net {mux#9.itm(6)} -attr vt d
+load net {mux#9.itm(7)} -attr vt d
+load net {mux#9.itm(8)} -attr vt d
+load net {mux#9.itm(9)} -attr vt d
+load net {mux#9.itm(10)} -attr vt d
+load net {mux#9.itm(11)} -attr vt d
+load net {mux#9.itm(12)} -attr vt d
+load net {mux#9.itm(13)} -attr vt d
+load net {mux#9.itm(14)} -attr vt d
+load netBundle {mux#9.itm} 15 {mux#9.itm(0)} {mux#9.itm(1)} {mux#9.itm(2)} {mux#9.itm(3)} {mux#9.itm(4)} {mux#9.itm(5)} {mux#9.itm(6)} {mux#9.itm(7)} {mux#9.itm(8)} {mux#9.itm(9)} {mux#9.itm(10)} {mux#9.itm(11)} {mux#9.itm(12)} {mux#9.itm(13)} {mux#9.itm(14)} -attr xrf 44275 -attr oid 151 -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {FRAME:for:acc#27.itm(0)} -attr vt d
+load net {FRAME:for:acc#27.itm(1)} -attr vt d
+load net {FRAME:for:acc#27.itm(2)} -attr vt d
+load net {FRAME:for:acc#27.itm(3)} -attr vt d
+load net {FRAME:for:acc#27.itm(4)} -attr vt d
+load net {FRAME:for:acc#27.itm(5)} -attr vt d
+load net {FRAME:for:acc#27.itm(6)} -attr vt d
+load net {FRAME:for:acc#27.itm(7)} -attr vt d
+load net {FRAME:for:acc#27.itm(8)} -attr vt d
+load net {FRAME:for:acc#27.itm(9)} -attr vt d
+load net {FRAME:for:acc#27.itm(10)} -attr vt d
+load net {FRAME:for:acc#27.itm(11)} -attr vt d
+load net {FRAME:for:acc#27.itm(12)} -attr vt d
+load net {FRAME:for:acc#27.itm(13)} -attr vt d
+load net {FRAME:for:acc#27.itm(14)} -attr vt d
+load netBundle {FRAME:for:acc#27.itm} 15 {FRAME:for:acc#27.itm(0)} {FRAME:for:acc#27.itm(1)} {FRAME:for:acc#27.itm(2)} {FRAME:for:acc#27.itm(3)} {FRAME:for:acc#27.itm(4)} {FRAME:for:acc#27.itm(5)} {FRAME:for:acc#27.itm(6)} {FRAME:for:acc#27.itm(7)} {FRAME:for:acc#27.itm(8)} {FRAME:for:acc#27.itm(9)} {FRAME:for:acc#27.itm(10)} {FRAME:for:acc#27.itm(11)} {FRAME:for:acc#27.itm(12)} {FRAME:for:acc#27.itm(13)} {FRAME:for:acc#27.itm(14)} -attr xrf 44276 -attr oid 152 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:mul#4.itm(0)} -attr vt d
+load net {FRAME:for:mul#4.itm(1)} -attr vt d
+load net {FRAME:for:mul#4.itm(2)} -attr vt d
+load net {FRAME:for:mul#4.itm(3)} -attr vt d
+load net {FRAME:for:mul#4.itm(4)} -attr vt d
+load net {FRAME:for:mul#4.itm(5)} -attr vt d
+load net {FRAME:for:mul#4.itm(6)} -attr vt d
+load net {FRAME:for:mul#4.itm(7)} -attr vt d
+load net {FRAME:for:mul#4.itm(8)} -attr vt d
+load net {FRAME:for:mul#4.itm(9)} -attr vt d
+load net {FRAME:for:mul#4.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#4.itm} 11 {FRAME:for:mul#4.itm(0)} {FRAME:for:mul#4.itm(1)} {FRAME:for:mul#4.itm(2)} {FRAME:for:mul#4.itm(3)} {FRAME:for:mul#4.itm(4)} {FRAME:for:mul#4.itm(5)} {FRAME:for:mul#4.itm(6)} {FRAME:for:mul#4.itm(7)} {FRAME:for:mul#4.itm(8)} {FRAME:for:mul#4.itm(9)} {FRAME:for:mul#4.itm(10)} -attr xrf 44277 -attr oid 153 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {regs.operator[]#22:mux.itm(0)} -attr vt d
+load net {regs.operator[]#22:mux.itm(1)} -attr vt d
+load net {regs.operator[]#22:mux.itm(2)} -attr vt d
+load net {regs.operator[]#22:mux.itm(3)} -attr vt d
+load net {regs.operator[]#22:mux.itm(4)} -attr vt d
+load net {regs.operator[]#22:mux.itm(5)} -attr vt d
+load net {regs.operator[]#22:mux.itm(6)} -attr vt d
+load net {regs.operator[]#22:mux.itm(7)} -attr vt d
+load net {regs.operator[]#22:mux.itm(8)} -attr vt d
+load net {regs.operator[]#22:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#22:mux.itm} 10 {regs.operator[]#22:mux.itm(0)} {regs.operator[]#22:mux.itm(1)} {regs.operator[]#22:mux.itm(2)} {regs.operator[]#22:mux.itm(3)} {regs.operator[]#22:mux.itm(4)} {regs.operator[]#22:mux.itm(5)} {regs.operator[]#22:mux.itm(6)} {regs.operator[]#22:mux.itm(7)} {regs.operator[]#22:mux.itm(8)} {regs.operator[]#22:mux.itm(9)} -attr xrf 44278 -attr oid 154 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(9)} -attr xrf 44279 -attr oid 155 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr xrf 44280 -attr oid 156 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr xrf 44281 -attr oid 157 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {mux#10.itm(0)} -attr vt d
+load net {mux#10.itm(1)} -attr vt d
+load net {mux#10.itm(2)} -attr vt d
+load net {mux#10.itm(3)} -attr vt d
+load net {mux#10.itm(4)} -attr vt d
+load net {mux#10.itm(5)} -attr vt d
+load net {mux#10.itm(6)} -attr vt d
+load net {mux#10.itm(7)} -attr vt d
+load net {mux#10.itm(8)} -attr vt d
+load net {mux#10.itm(9)} -attr vt d
+load net {mux#10.itm(10)} -attr vt d
+load net {mux#10.itm(11)} -attr vt d
+load net {mux#10.itm(12)} -attr vt d
+load net {mux#10.itm(13)} -attr vt d
+load net {mux#10.itm(14)} -attr vt d
+load netBundle {mux#10.itm} 15 {mux#10.itm(0)} {mux#10.itm(1)} {mux#10.itm(2)} {mux#10.itm(3)} {mux#10.itm(4)} {mux#10.itm(5)} {mux#10.itm(6)} {mux#10.itm(7)} {mux#10.itm(8)} {mux#10.itm(9)} {mux#10.itm(10)} {mux#10.itm(11)} {mux#10.itm(12)} {mux#10.itm(13)} {mux#10.itm(14)} -attr xrf 44282 -attr oid 158 -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {FRAME:for:acc#26.itm(0)} -attr vt d
+load net {FRAME:for:acc#26.itm(1)} -attr vt d
+load net {FRAME:for:acc#26.itm(2)} -attr vt d
+load net {FRAME:for:acc#26.itm(3)} -attr vt d
+load net {FRAME:for:acc#26.itm(4)} -attr vt d
+load net {FRAME:for:acc#26.itm(5)} -attr vt d
+load net {FRAME:for:acc#26.itm(6)} -attr vt d
+load net {FRAME:for:acc#26.itm(7)} -attr vt d
+load net {FRAME:for:acc#26.itm(8)} -attr vt d
+load net {FRAME:for:acc#26.itm(9)} -attr vt d
+load net {FRAME:for:acc#26.itm(10)} -attr vt d
+load net {FRAME:for:acc#26.itm(11)} -attr vt d
+load net {FRAME:for:acc#26.itm(12)} -attr vt d
+load net {FRAME:for:acc#26.itm(13)} -attr vt d
+load net {FRAME:for:acc#26.itm(14)} -attr vt d
+load netBundle {FRAME:for:acc#26.itm} 15 {FRAME:for:acc#26.itm(0)} {FRAME:for:acc#26.itm(1)} {FRAME:for:acc#26.itm(2)} {FRAME:for:acc#26.itm(3)} {FRAME:for:acc#26.itm(4)} {FRAME:for:acc#26.itm(5)} {FRAME:for:acc#26.itm(6)} {FRAME:for:acc#26.itm(7)} {FRAME:for:acc#26.itm(8)} {FRAME:for:acc#26.itm(9)} {FRAME:for:acc#26.itm(10)} {FRAME:for:acc#26.itm(11)} {FRAME:for:acc#26.itm(12)} {FRAME:for:acc#26.itm(13)} {FRAME:for:acc#26.itm(14)} -attr xrf 44283 -attr oid 159 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:mul#3.itm(0)} -attr vt d
+load net {FRAME:for:mul#3.itm(1)} -attr vt d
+load net {FRAME:for:mul#3.itm(2)} -attr vt d
+load net {FRAME:for:mul#3.itm(3)} -attr vt d
+load net {FRAME:for:mul#3.itm(4)} -attr vt d
+load net {FRAME:for:mul#3.itm(5)} -attr vt d
+load net {FRAME:for:mul#3.itm(6)} -attr vt d
+load net {FRAME:for:mul#3.itm(7)} -attr vt d
+load net {FRAME:for:mul#3.itm(8)} -attr vt d
+load net {FRAME:for:mul#3.itm(9)} -attr vt d
+load net {FRAME:for:mul#3.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#3.itm} 11 {FRAME:for:mul#3.itm(0)} {FRAME:for:mul#3.itm(1)} {FRAME:for:mul#3.itm(2)} {FRAME:for:mul#3.itm(3)} {FRAME:for:mul#3.itm(4)} {FRAME:for:mul#3.itm(5)} {FRAME:for:mul#3.itm(6)} {FRAME:for:mul#3.itm(7)} {FRAME:for:mul#3.itm(8)} {FRAME:for:mul#3.itm(9)} {FRAME:for:mul#3.itm(10)} -attr xrf 44284 -attr oid 160 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {regs.operator[]#21:mux.itm(0)} -attr vt d
+load net {regs.operator[]#21:mux.itm(1)} -attr vt d
+load net {regs.operator[]#21:mux.itm(2)} -attr vt d
+load net {regs.operator[]#21:mux.itm(3)} -attr vt d
+load net {regs.operator[]#21:mux.itm(4)} -attr vt d
+load net {regs.operator[]#21:mux.itm(5)} -attr vt d
+load net {regs.operator[]#21:mux.itm(6)} -attr vt d
+load net {regs.operator[]#21:mux.itm(7)} -attr vt d
+load net {regs.operator[]#21:mux.itm(8)} -attr vt d
+load net {regs.operator[]#21:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#21:mux.itm} 10 {regs.operator[]#21:mux.itm(0)} {regs.operator[]#21:mux.itm(1)} {regs.operator[]#21:mux.itm(2)} {regs.operator[]#21:mux.itm(3)} {regs.operator[]#21:mux.itm(4)} {regs.operator[]#21:mux.itm(5)} {regs.operator[]#21:mux.itm(6)} {regs.operator[]#21:mux.itm(7)} {regs.operator[]#21:mux.itm(8)} {regs.operator[]#21:mux.itm(9)} -attr xrf 44285 -attr oid 161 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(9)} -attr xrf 44286 -attr oid 162 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr xrf 44287 -attr oid 163 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr xrf 44288 -attr oid 164 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {mux#11.itm(0)} -attr vt d
+load net {mux#11.itm(1)} -attr vt d
+load netBundle {mux#11.itm} 2 {mux#11.itm(0)} {mux#11.itm(1)} -attr xrf 44289 -attr oid 165 -attr vt d -attr @path {/sobel/sobel:core/mux#11.itm}
+load net {mux#12.itm(0)} -attr vt d
+load net {mux#12.itm(1)} -attr vt d
+load net {mux#12.itm(2)} -attr vt d
+load net {mux#12.itm(3)} -attr vt d
+load net {mux#12.itm(4)} -attr vt d
+load net {mux#12.itm(5)} -attr vt d
+load net {mux#12.itm(6)} -attr vt d
+load net {mux#12.itm(7)} -attr vt d
+load net {mux#12.itm(8)} -attr vt d
+load net {mux#12.itm(9)} -attr vt d
+load net {mux#12.itm(10)} -attr vt d
+load net {mux#12.itm(11)} -attr vt d
+load net {mux#12.itm(12)} -attr vt d
+load net {mux#12.itm(13)} -attr vt d
+load net {mux#12.itm(14)} -attr vt d
+load net {mux#12.itm(15)} -attr vt d
+load netBundle {mux#12.itm} 16 {mux#12.itm(0)} {mux#12.itm(1)} {mux#12.itm(2)} {mux#12.itm(3)} {mux#12.itm(4)} {mux#12.itm(5)} {mux#12.itm(6)} {mux#12.itm(7)} {mux#12.itm(8)} {mux#12.itm(9)} {mux#12.itm(10)} {mux#12.itm(11)} {mux#12.itm(12)} {mux#12.itm(13)} {mux#12.itm(14)} {mux#12.itm(15)} -attr xrf 44290 -attr oid 166 -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {FRAME:for:acc#14.itm(0)} -attr vt d
+load net {FRAME:for:acc#14.itm(1)} -attr vt d
+load net {FRAME:for:acc#14.itm(2)} -attr vt d
+load net {FRAME:for:acc#14.itm(3)} -attr vt d
+load net {FRAME:for:acc#14.itm(4)} -attr vt d
+load net {FRAME:for:acc#14.itm(5)} -attr vt d
+load net {FRAME:for:acc#14.itm(6)} -attr vt d
+load net {FRAME:for:acc#14.itm(7)} -attr vt d
+load net {FRAME:for:acc#14.itm(8)} -attr vt d
+load net {FRAME:for:acc#14.itm(9)} -attr vt d
+load net {FRAME:for:acc#14.itm(10)} -attr vt d
+load net {FRAME:for:acc#14.itm(11)} -attr vt d
+load net {FRAME:for:acc#14.itm(12)} -attr vt d
+load net {FRAME:for:acc#14.itm(13)} -attr vt d
+load net {FRAME:for:acc#14.itm(14)} -attr vt d
+load net {FRAME:for:acc#14.itm(15)} -attr vt d
+load netBundle {FRAME:for:acc#14.itm} 16 {FRAME:for:acc#14.itm(0)} {FRAME:for:acc#14.itm(1)} {FRAME:for:acc#14.itm(2)} {FRAME:for:acc#14.itm(3)} {FRAME:for:acc#14.itm(4)} {FRAME:for:acc#14.itm(5)} {FRAME:for:acc#14.itm(6)} {FRAME:for:acc#14.itm(7)} {FRAME:for:acc#14.itm(8)} {FRAME:for:acc#14.itm(9)} {FRAME:for:acc#14.itm(10)} {FRAME:for:acc#14.itm(11)} {FRAME:for:acc#14.itm(12)} {FRAME:for:acc#14.itm(13)} {FRAME:for:acc#14.itm(14)} {FRAME:for:acc#14.itm(15)} -attr xrf 44291 -attr oid 167 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:mul#8.itm(0)} -attr vt d
+load net {FRAME:for:mul#8.itm(1)} -attr vt d
+load net {FRAME:for:mul#8.itm(2)} -attr vt d
+load net {FRAME:for:mul#8.itm(3)} -attr vt d
+load net {FRAME:for:mul#8.itm(4)} -attr vt d
+load net {FRAME:for:mul#8.itm(5)} -attr vt d
+load net {FRAME:for:mul#8.itm(6)} -attr vt d
+load net {FRAME:for:mul#8.itm(7)} -attr vt d
+load net {FRAME:for:mul#8.itm(8)} -attr vt d
+load net {FRAME:for:mul#8.itm(9)} -attr vt d
+load net {FRAME:for:mul#8.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#8.itm} 11 {FRAME:for:mul#8.itm(0)} {FRAME:for:mul#8.itm(1)} {FRAME:for:mul#8.itm(2)} {FRAME:for:mul#8.itm(3)} {FRAME:for:mul#8.itm(4)} {FRAME:for:mul#8.itm(5)} {FRAME:for:mul#8.itm(6)} {FRAME:for:mul#8.itm(7)} {FRAME:for:mul#8.itm(8)} {FRAME:for:mul#8.itm(9)} {FRAME:for:mul#8.itm(10)} -attr xrf 44292 -attr oid 168 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {regs.operator[]#26:mux.itm(0)} -attr vt d
+load net {regs.operator[]#26:mux.itm(1)} -attr vt d
+load net {regs.operator[]#26:mux.itm(2)} -attr vt d
+load net {regs.operator[]#26:mux.itm(3)} -attr vt d
+load net {regs.operator[]#26:mux.itm(4)} -attr vt d
+load net {regs.operator[]#26:mux.itm(5)} -attr vt d
+load net {regs.operator[]#26:mux.itm(6)} -attr vt d
+load net {regs.operator[]#26:mux.itm(7)} -attr vt d
+load net {regs.operator[]#26:mux.itm(8)} -attr vt d
+load net {regs.operator[]#26:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#26:mux.itm} 10 {regs.operator[]#26:mux.itm(0)} {regs.operator[]#26:mux.itm(1)} {regs.operator[]#26:mux.itm(2)} {regs.operator[]#26:mux.itm(3)} {regs.operator[]#26:mux.itm(4)} {regs.operator[]#26:mux.itm(5)} {regs.operator[]#26:mux.itm(6)} {regs.operator[]#26:mux.itm(7)} {regs.operator[]#26:mux.itm(8)} {regs.operator[]#26:mux.itm(9)} -attr xrf 44293 -attr oid 169 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0).itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0).itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(9)} -attr xrf 44294 -attr oid 170 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0).itm} 10 {slc(regs.regs(1).sva.dfm:mx0).itm(0)} {slc(regs.regs(1).sva.dfm:mx0).itm(1)} {slc(regs.regs(1).sva.dfm:mx0).itm(2)} {slc(regs.regs(1).sva.dfm:mx0).itm(3)} {slc(regs.regs(1).sva.dfm:mx0).itm(4)} {slc(regs.regs(1).sva.dfm:mx0).itm(5)} {slc(regs.regs(1).sva.dfm:mx0).itm(6)} {slc(regs.regs(1).sva.dfm:mx0).itm(7)} {slc(regs.regs(1).sva.dfm:mx0).itm(8)} {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr xrf 44295 -attr oid 171 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0).itm} 10 {slc(regs.regs(0).sva.dfm:mx0).itm(0)} {slc(regs.regs(0).sva.dfm:mx0).itm(1)} {slc(regs.regs(0).sva.dfm:mx0).itm(2)} {slc(regs.regs(0).sva.dfm:mx0).itm(3)} {slc(regs.regs(0).sva.dfm:mx0).itm(4)} {slc(regs.regs(0).sva.dfm:mx0).itm(5)} {slc(regs.regs(0).sva.dfm:mx0).itm(6)} {slc(regs.regs(0).sva.dfm:mx0).itm(7)} {slc(regs.regs(0).sva.dfm:mx0).itm(8)} {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr xrf 44296 -attr oid 172 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {mux#13.itm(0)} -attr vt d
+load net {mux#13.itm(1)} -attr vt d
+load net {mux#13.itm(2)} -attr vt d
+load net {mux#13.itm(3)} -attr vt d
+load net {mux#13.itm(4)} -attr vt d
+load net {mux#13.itm(5)} -attr vt d
+load net {mux#13.itm(6)} -attr vt d
+load net {mux#13.itm(7)} -attr vt d
+load net {mux#13.itm(8)} -attr vt d
+load net {mux#13.itm(9)} -attr vt d
+load net {mux#13.itm(10)} -attr vt d
+load net {mux#13.itm(11)} -attr vt d
+load net {mux#13.itm(12)} -attr vt d
+load net {mux#13.itm(13)} -attr vt d
+load net {mux#13.itm(14)} -attr vt d
+load net {mux#13.itm(15)} -attr vt d
+load netBundle {mux#13.itm} 16 {mux#13.itm(0)} {mux#13.itm(1)} {mux#13.itm(2)} {mux#13.itm(3)} {mux#13.itm(4)} {mux#13.itm(5)} {mux#13.itm(6)} {mux#13.itm(7)} {mux#13.itm(8)} {mux#13.itm(9)} {mux#13.itm(10)} {mux#13.itm(11)} {mux#13.itm(12)} {mux#13.itm(13)} {mux#13.itm(14)} {mux#13.itm(15)} -attr xrf 44297 -attr oid 173 -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {FRAME:for:acc#3.itm(0)} -attr vt d
+load net {FRAME:for:acc#3.itm(1)} -attr vt d
+load net {FRAME:for:acc#3.itm(2)} -attr vt d
+load net {FRAME:for:acc#3.itm(3)} -attr vt d
+load net {FRAME:for:acc#3.itm(4)} -attr vt d
+load net {FRAME:for:acc#3.itm(5)} -attr vt d
+load net {FRAME:for:acc#3.itm(6)} -attr vt d
+load net {FRAME:for:acc#3.itm(7)} -attr vt d
+load net {FRAME:for:acc#3.itm(8)} -attr vt d
+load net {FRAME:for:acc#3.itm(9)} -attr vt d
+load net {FRAME:for:acc#3.itm(10)} -attr vt d
+load net {FRAME:for:acc#3.itm(11)} -attr vt d
+load net {FRAME:for:acc#3.itm(12)} -attr vt d
+load net {FRAME:for:acc#3.itm(13)} -attr vt d
+load net {FRAME:for:acc#3.itm(14)} -attr vt d
+load net {FRAME:for:acc#3.itm(15)} -attr vt d
+load netBundle {FRAME:for:acc#3.itm} 16 {FRAME:for:acc#3.itm(0)} {FRAME:for:acc#3.itm(1)} {FRAME:for:acc#3.itm(2)} {FRAME:for:acc#3.itm(3)} {FRAME:for:acc#3.itm(4)} {FRAME:for:acc#3.itm(5)} {FRAME:for:acc#3.itm(6)} {FRAME:for:acc#3.itm(7)} {FRAME:for:acc#3.itm(8)} {FRAME:for:acc#3.itm(9)} {FRAME:for:acc#3.itm(10)} {FRAME:for:acc#3.itm(11)} {FRAME:for:acc#3.itm(12)} {FRAME:for:acc#3.itm(13)} {FRAME:for:acc#3.itm(14)} {FRAME:for:acc#3.itm(15)} -attr xrf 44298 -attr oid 174 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:mul#2.itm(0)} -attr vt d
+load net {FRAME:for:mul#2.itm(1)} -attr vt d
+load net {FRAME:for:mul#2.itm(2)} -attr vt d
+load net {FRAME:for:mul#2.itm(3)} -attr vt d
+load net {FRAME:for:mul#2.itm(4)} -attr vt d
+load net {FRAME:for:mul#2.itm(5)} -attr vt d
+load net {FRAME:for:mul#2.itm(6)} -attr vt d
+load net {FRAME:for:mul#2.itm(7)} -attr vt d
+load net {FRAME:for:mul#2.itm(8)} -attr vt d
+load net {FRAME:for:mul#2.itm(9)} -attr vt d
+load net {FRAME:for:mul#2.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#2.itm} 11 {FRAME:for:mul#2.itm(0)} {FRAME:for:mul#2.itm(1)} {FRAME:for:mul#2.itm(2)} {FRAME:for:mul#2.itm(3)} {FRAME:for:mul#2.itm(4)} {FRAME:for:mul#2.itm(5)} {FRAME:for:mul#2.itm(6)} {FRAME:for:mul#2.itm(7)} {FRAME:for:mul#2.itm(8)} {FRAME:for:mul#2.itm(9)} {FRAME:for:mul#2.itm(10)} -attr xrf 44299 -attr oid 175 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {regs.operator[]#20:mux.itm(0)} -attr vt d
+load net {regs.operator[]#20:mux.itm(1)} -attr vt d
+load net {regs.operator[]#20:mux.itm(2)} -attr vt d
+load net {regs.operator[]#20:mux.itm(3)} -attr vt d
+load net {regs.operator[]#20:mux.itm(4)} -attr vt d
+load net {regs.operator[]#20:mux.itm(5)} -attr vt d
+load net {regs.operator[]#20:mux.itm(6)} -attr vt d
+load net {regs.operator[]#20:mux.itm(7)} -attr vt d
+load net {regs.operator[]#20:mux.itm(8)} -attr vt d
+load net {regs.operator[]#20:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#20:mux.itm} 10 {regs.operator[]#20:mux.itm(0)} {regs.operator[]#20:mux.itm(1)} {regs.operator[]#20:mux.itm(2)} {regs.operator[]#20:mux.itm(3)} {regs.operator[]#20:mux.itm(4)} {regs.operator[]#20:mux.itm(5)} {regs.operator[]#20:mux.itm(6)} {regs.operator[]#20:mux.itm(7)} {regs.operator[]#20:mux.itm(8)} {regs.operator[]#20:mux.itm(9)} -attr xrf 44300 -attr oid 176 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(9)} -attr xrf 44301 -attr oid 177 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#6.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#6.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(9)} -attr xrf 44302 -attr oid 178 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#6.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#6.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(9)} -attr xrf 44303 -attr oid 179 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {mux#14.itm(0)} -attr vt d
+load net {mux#14.itm(1)} -attr vt d
+load net {mux#14.itm(2)} -attr vt d
+load net {mux#14.itm(3)} -attr vt d
+load net {mux#14.itm(4)} -attr vt d
+load net {mux#14.itm(5)} -attr vt d
+load net {mux#14.itm(6)} -attr vt d
+load net {mux#14.itm(7)} -attr vt d
+load net {mux#14.itm(8)} -attr vt d
+load net {mux#14.itm(9)} -attr vt d
+load net {mux#14.itm(10)} -attr vt d
+load net {mux#14.itm(11)} -attr vt d
+load net {mux#14.itm(12)} -attr vt d
+load net {mux#14.itm(13)} -attr vt d
+load net {mux#14.itm(14)} -attr vt d
+load net {mux#14.itm(15)} -attr vt d
+load netBundle {mux#14.itm} 16 {mux#14.itm(0)} {mux#14.itm(1)} {mux#14.itm(2)} {mux#14.itm(3)} {mux#14.itm(4)} {mux#14.itm(5)} {mux#14.itm(6)} {mux#14.itm(7)} {mux#14.itm(8)} {mux#14.itm(9)} {mux#14.itm(10)} {mux#14.itm(11)} {mux#14.itm(12)} {mux#14.itm(13)} {mux#14.itm(14)} {mux#14.itm(15)} -attr xrf 44304 -attr oid 180 -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {FRAME:for:acc#12.itm(0)} -attr vt d
+load net {FRAME:for:acc#12.itm(1)} -attr vt d
+load net {FRAME:for:acc#12.itm(2)} -attr vt d
+load net {FRAME:for:acc#12.itm(3)} -attr vt d
+load net {FRAME:for:acc#12.itm(4)} -attr vt d
+load net {FRAME:for:acc#12.itm(5)} -attr vt d
+load net {FRAME:for:acc#12.itm(6)} -attr vt d
+load net {FRAME:for:acc#12.itm(7)} -attr vt d
+load net {FRAME:for:acc#12.itm(8)} -attr vt d
+load net {FRAME:for:acc#12.itm(9)} -attr vt d
+load net {FRAME:for:acc#12.itm(10)} -attr vt d
+load net {FRAME:for:acc#12.itm(11)} -attr vt d
+load net {FRAME:for:acc#12.itm(12)} -attr vt d
+load net {FRAME:for:acc#12.itm(13)} -attr vt d
+load net {FRAME:for:acc#12.itm(14)} -attr vt d
+load net {FRAME:for:acc#12.itm(15)} -attr vt d
+load netBundle {FRAME:for:acc#12.itm} 16 {FRAME:for:acc#12.itm(0)} {FRAME:for:acc#12.itm(1)} {FRAME:for:acc#12.itm(2)} {FRAME:for:acc#12.itm(3)} {FRAME:for:acc#12.itm(4)} {FRAME:for:acc#12.itm(5)} {FRAME:for:acc#12.itm(6)} {FRAME:for:acc#12.itm(7)} {FRAME:for:acc#12.itm(8)} {FRAME:for:acc#12.itm(9)} {FRAME:for:acc#12.itm(10)} {FRAME:for:acc#12.itm(11)} {FRAME:for:acc#12.itm(12)} {FRAME:for:acc#12.itm(13)} {FRAME:for:acc#12.itm(14)} {FRAME:for:acc#12.itm(15)} -attr xrf 44305 -attr oid 181 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:mul#7.itm(0)} -attr vt d
+load net {FRAME:for:mul#7.itm(1)} -attr vt d
+load net {FRAME:for:mul#7.itm(2)} -attr vt d
+load net {FRAME:for:mul#7.itm(3)} -attr vt d
+load net {FRAME:for:mul#7.itm(4)} -attr vt d
+load net {FRAME:for:mul#7.itm(5)} -attr vt d
+load net {FRAME:for:mul#7.itm(6)} -attr vt d
+load net {FRAME:for:mul#7.itm(7)} -attr vt d
+load net {FRAME:for:mul#7.itm(8)} -attr vt d
+load net {FRAME:for:mul#7.itm(9)} -attr vt d
+load net {FRAME:for:mul#7.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#7.itm} 11 {FRAME:for:mul#7.itm(0)} {FRAME:for:mul#7.itm(1)} {FRAME:for:mul#7.itm(2)} {FRAME:for:mul#7.itm(3)} {FRAME:for:mul#7.itm(4)} {FRAME:for:mul#7.itm(5)} {FRAME:for:mul#7.itm(6)} {FRAME:for:mul#7.itm(7)} {FRAME:for:mul#7.itm(8)} {FRAME:for:mul#7.itm(9)} {FRAME:for:mul#7.itm(10)} -attr xrf 44306 -attr oid 182 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {regs.operator[]#25:mux.itm(0)} -attr vt d
+load net {regs.operator[]#25:mux.itm(1)} -attr vt d
+load net {regs.operator[]#25:mux.itm(2)} -attr vt d
+load net {regs.operator[]#25:mux.itm(3)} -attr vt d
+load net {regs.operator[]#25:mux.itm(4)} -attr vt d
+load net {regs.operator[]#25:mux.itm(5)} -attr vt d
+load net {regs.operator[]#25:mux.itm(6)} -attr vt d
+load net {regs.operator[]#25:mux.itm(7)} -attr vt d
+load net {regs.operator[]#25:mux.itm(8)} -attr vt d
+load net {regs.operator[]#25:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#25:mux.itm} 10 {regs.operator[]#25:mux.itm(0)} {regs.operator[]#25:mux.itm(1)} {regs.operator[]#25:mux.itm(2)} {regs.operator[]#25:mux.itm(3)} {regs.operator[]#25:mux.itm(4)} {regs.operator[]#25:mux.itm(5)} {regs.operator[]#25:mux.itm(6)} {regs.operator[]#25:mux.itm(7)} {regs.operator[]#25:mux.itm(8)} {regs.operator[]#25:mux.itm(9)} -attr xrf 44307 -attr oid 183 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(9)} -attr xrf 44308 -attr oid 184 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr xrf 44309 -attr oid 185 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr xrf 44310 -attr oid 186 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {mux#15.itm(0)} -attr vt d
+load net {mux#15.itm(1)} -attr vt d
+load net {mux#15.itm(2)} -attr vt d
+load net {mux#15.itm(3)} -attr vt d
+load net {mux#15.itm(4)} -attr vt d
+load net {mux#15.itm(5)} -attr vt d
+load net {mux#15.itm(6)} -attr vt d
+load net {mux#15.itm(7)} -attr vt d
+load net {mux#15.itm(8)} -attr vt d
+load net {mux#15.itm(9)} -attr vt d
+load net {mux#15.itm(10)} -attr vt d
+load net {mux#15.itm(11)} -attr vt d
+load net {mux#15.itm(12)} -attr vt d
+load net {mux#15.itm(13)} -attr vt d
+load net {mux#15.itm(14)} -attr vt d
+load net {mux#15.itm(15)} -attr vt d
+load netBundle {mux#15.itm} 16 {mux#15.itm(0)} {mux#15.itm(1)} {mux#15.itm(2)} {mux#15.itm(3)} {mux#15.itm(4)} {mux#15.itm(5)} {mux#15.itm(6)} {mux#15.itm(7)} {mux#15.itm(8)} {mux#15.itm(9)} {mux#15.itm(10)} {mux#15.itm(11)} {mux#15.itm(12)} {mux#15.itm(13)} {mux#15.itm(14)} {mux#15.itm(15)} -attr xrf 44311 -attr oid 187 -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {FRAME:for:acc#2.itm(0)} -attr vt d
+load net {FRAME:for:acc#2.itm(1)} -attr vt d
+load net {FRAME:for:acc#2.itm(2)} -attr vt d
+load net {FRAME:for:acc#2.itm(3)} -attr vt d
+load net {FRAME:for:acc#2.itm(4)} -attr vt d
+load net {FRAME:for:acc#2.itm(5)} -attr vt d
+load net {FRAME:for:acc#2.itm(6)} -attr vt d
+load net {FRAME:for:acc#2.itm(7)} -attr vt d
+load net {FRAME:for:acc#2.itm(8)} -attr vt d
+load net {FRAME:for:acc#2.itm(9)} -attr vt d
+load net {FRAME:for:acc#2.itm(10)} -attr vt d
+load net {FRAME:for:acc#2.itm(11)} -attr vt d
+load net {FRAME:for:acc#2.itm(12)} -attr vt d
+load net {FRAME:for:acc#2.itm(13)} -attr vt d
+load net {FRAME:for:acc#2.itm(14)} -attr vt d
+load net {FRAME:for:acc#2.itm(15)} -attr vt d
+load netBundle {FRAME:for:acc#2.itm} 16 {FRAME:for:acc#2.itm(0)} {FRAME:for:acc#2.itm(1)} {FRAME:for:acc#2.itm(2)} {FRAME:for:acc#2.itm(3)} {FRAME:for:acc#2.itm(4)} {FRAME:for:acc#2.itm(5)} {FRAME:for:acc#2.itm(6)} {FRAME:for:acc#2.itm(7)} {FRAME:for:acc#2.itm(8)} {FRAME:for:acc#2.itm(9)} {FRAME:for:acc#2.itm(10)} {FRAME:for:acc#2.itm(11)} {FRAME:for:acc#2.itm(12)} {FRAME:for:acc#2.itm(13)} {FRAME:for:acc#2.itm(14)} {FRAME:for:acc#2.itm(15)} -attr xrf 44312 -attr oid 188 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:mul#1.itm(0)} -attr vt d
+load net {FRAME:for:mul#1.itm(1)} -attr vt d
+load net {FRAME:for:mul#1.itm(2)} -attr vt d
+load net {FRAME:for:mul#1.itm(3)} -attr vt d
+load net {FRAME:for:mul#1.itm(4)} -attr vt d
+load net {FRAME:for:mul#1.itm(5)} -attr vt d
+load net {FRAME:for:mul#1.itm(6)} -attr vt d
+load net {FRAME:for:mul#1.itm(7)} -attr vt d
+load net {FRAME:for:mul#1.itm(8)} -attr vt d
+load net {FRAME:for:mul#1.itm(9)} -attr vt d
+load net {FRAME:for:mul#1.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#1.itm} 11 {FRAME:for:mul#1.itm(0)} {FRAME:for:mul#1.itm(1)} {FRAME:for:mul#1.itm(2)} {FRAME:for:mul#1.itm(3)} {FRAME:for:mul#1.itm(4)} {FRAME:for:mul#1.itm(5)} {FRAME:for:mul#1.itm(6)} {FRAME:for:mul#1.itm(7)} {FRAME:for:mul#1.itm(8)} {FRAME:for:mul#1.itm(9)} {FRAME:for:mul#1.itm(10)} -attr xrf 44313 -attr oid 189 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {regs.operator[]#19:mux.itm(0)} -attr vt d
+load net {regs.operator[]#19:mux.itm(1)} -attr vt d
+load net {regs.operator[]#19:mux.itm(2)} -attr vt d
+load net {regs.operator[]#19:mux.itm(3)} -attr vt d
+load net {regs.operator[]#19:mux.itm(4)} -attr vt d
+load net {regs.operator[]#19:mux.itm(5)} -attr vt d
+load net {regs.operator[]#19:mux.itm(6)} -attr vt d
+load net {regs.operator[]#19:mux.itm(7)} -attr vt d
+load net {regs.operator[]#19:mux.itm(8)} -attr vt d
+load net {regs.operator[]#19:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#19:mux.itm} 10 {regs.operator[]#19:mux.itm(0)} {regs.operator[]#19:mux.itm(1)} {regs.operator[]#19:mux.itm(2)} {regs.operator[]#19:mux.itm(3)} {regs.operator[]#19:mux.itm(4)} {regs.operator[]#19:mux.itm(5)} {regs.operator[]#19:mux.itm(6)} {regs.operator[]#19:mux.itm(7)} {regs.operator[]#19:mux.itm(8)} {regs.operator[]#19:mux.itm(9)} -attr xrf 44314 -attr oid 190 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(9)} -attr xrf 44315 -attr oid 191 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#7.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#7.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(9)} -attr xrf 44316 -attr oid 192 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#7.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#7.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(9)} -attr xrf 44317 -attr oid 193 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {mux#16.itm(0)} -attr vt d
+load net {mux#16.itm(1)} -attr vt d
+load net {mux#16.itm(2)} -attr vt d
+load net {mux#16.itm(3)} -attr vt d
+load net {mux#16.itm(4)} -attr vt d
+load net {mux#16.itm(5)} -attr vt d
+load net {mux#16.itm(6)} -attr vt d
+load net {mux#16.itm(7)} -attr vt d
+load net {mux#16.itm(8)} -attr vt d
+load net {mux#16.itm(9)} -attr vt d
+load net {mux#16.itm(10)} -attr vt d
+load net {mux#16.itm(11)} -attr vt d
+load net {mux#16.itm(12)} -attr vt d
+load net {mux#16.itm(13)} -attr vt d
+load net {mux#16.itm(14)} -attr vt d
+load net {mux#16.itm(15)} -attr vt d
+load netBundle {mux#16.itm} 16 {mux#16.itm(0)} {mux#16.itm(1)} {mux#16.itm(2)} {mux#16.itm(3)} {mux#16.itm(4)} {mux#16.itm(5)} {mux#16.itm(6)} {mux#16.itm(7)} {mux#16.itm(8)} {mux#16.itm(9)} {mux#16.itm(10)} {mux#16.itm(11)} {mux#16.itm(12)} {mux#16.itm(13)} {mux#16.itm(14)} {mux#16.itm(15)} -attr xrf 44318 -attr oid 194 -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {FRAME:for:acc#10.itm(0)} -attr vt d
+load net {FRAME:for:acc#10.itm(1)} -attr vt d
+load net {FRAME:for:acc#10.itm(2)} -attr vt d
+load net {FRAME:for:acc#10.itm(3)} -attr vt d
+load net {FRAME:for:acc#10.itm(4)} -attr vt d
+load net {FRAME:for:acc#10.itm(5)} -attr vt d
+load net {FRAME:for:acc#10.itm(6)} -attr vt d
+load net {FRAME:for:acc#10.itm(7)} -attr vt d
+load net {FRAME:for:acc#10.itm(8)} -attr vt d
+load net {FRAME:for:acc#10.itm(9)} -attr vt d
+load net {FRAME:for:acc#10.itm(10)} -attr vt d
+load net {FRAME:for:acc#10.itm(11)} -attr vt d
+load net {FRAME:for:acc#10.itm(12)} -attr vt d
+load net {FRAME:for:acc#10.itm(13)} -attr vt d
+load net {FRAME:for:acc#10.itm(14)} -attr vt d
+load net {FRAME:for:acc#10.itm(15)} -attr vt d
+load netBundle {FRAME:for:acc#10.itm} 16 {FRAME:for:acc#10.itm(0)} {FRAME:for:acc#10.itm(1)} {FRAME:for:acc#10.itm(2)} {FRAME:for:acc#10.itm(3)} {FRAME:for:acc#10.itm(4)} {FRAME:for:acc#10.itm(5)} {FRAME:for:acc#10.itm(6)} {FRAME:for:acc#10.itm(7)} {FRAME:for:acc#10.itm(8)} {FRAME:for:acc#10.itm(9)} {FRAME:for:acc#10.itm(10)} {FRAME:for:acc#10.itm(11)} {FRAME:for:acc#10.itm(12)} {FRAME:for:acc#10.itm(13)} {FRAME:for:acc#10.itm(14)} {FRAME:for:acc#10.itm(15)} -attr xrf 44319 -attr oid 195 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:mul#6.itm(0)} -attr vt d
+load net {FRAME:for:mul#6.itm(1)} -attr vt d
+load net {FRAME:for:mul#6.itm(2)} -attr vt d
+load net {FRAME:for:mul#6.itm(3)} -attr vt d
+load net {FRAME:for:mul#6.itm(4)} -attr vt d
+load net {FRAME:for:mul#6.itm(5)} -attr vt d
+load net {FRAME:for:mul#6.itm(6)} -attr vt d
+load net {FRAME:for:mul#6.itm(7)} -attr vt d
+load net {FRAME:for:mul#6.itm(8)} -attr vt d
+load net {FRAME:for:mul#6.itm(9)} -attr vt d
+load net {FRAME:for:mul#6.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#6.itm} 11 {FRAME:for:mul#6.itm(0)} {FRAME:for:mul#6.itm(1)} {FRAME:for:mul#6.itm(2)} {FRAME:for:mul#6.itm(3)} {FRAME:for:mul#6.itm(4)} {FRAME:for:mul#6.itm(5)} {FRAME:for:mul#6.itm(6)} {FRAME:for:mul#6.itm(7)} {FRAME:for:mul#6.itm(8)} {FRAME:for:mul#6.itm(9)} {FRAME:for:mul#6.itm(10)} -attr xrf 44320 -attr oid 196 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {regs.operator[]#24:mux.itm(0)} -attr vt d
+load net {regs.operator[]#24:mux.itm(1)} -attr vt d
+load net {regs.operator[]#24:mux.itm(2)} -attr vt d
+load net {regs.operator[]#24:mux.itm(3)} -attr vt d
+load net {regs.operator[]#24:mux.itm(4)} -attr vt d
+load net {regs.operator[]#24:mux.itm(5)} -attr vt d
+load net {regs.operator[]#24:mux.itm(6)} -attr vt d
+load net {regs.operator[]#24:mux.itm(7)} -attr vt d
+load net {regs.operator[]#24:mux.itm(8)} -attr vt d
+load net {regs.operator[]#24:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#24:mux.itm} 10 {regs.operator[]#24:mux.itm(0)} {regs.operator[]#24:mux.itm(1)} {regs.operator[]#24:mux.itm(2)} {regs.operator[]#24:mux.itm(3)} {regs.operator[]#24:mux.itm(4)} {regs.operator[]#24:mux.itm(5)} {regs.operator[]#24:mux.itm(6)} {regs.operator[]#24:mux.itm(7)} {regs.operator[]#24:mux.itm(8)} {regs.operator[]#24:mux.itm(9)} -attr xrf 44321 -attr oid 197 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(9)} -attr xrf 44322 -attr oid 198 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr xrf 44323 -attr oid 199 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr xrf 44324 -attr oid 200 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {mux#17.itm(0)} -attr vt d
+load net {mux#17.itm(1)} -attr vt d
+load net {mux#17.itm(2)} -attr vt d
+load net {mux#17.itm(3)} -attr vt d
+load net {mux#17.itm(4)} -attr vt d
+load net {mux#17.itm(5)} -attr vt d
+load net {mux#17.itm(6)} -attr vt d
+load net {mux#17.itm(7)} -attr vt d
+load net {mux#17.itm(8)} -attr vt d
+load net {mux#17.itm(9)} -attr vt d
+load net {mux#17.itm(10)} -attr vt d
+load net {mux#17.itm(11)} -attr vt d
+load net {mux#17.itm(12)} -attr vt d
+load net {mux#17.itm(13)} -attr vt d
+load net {mux#17.itm(14)} -attr vt d
+load net {mux#17.itm(15)} -attr vt d
+load netBundle {mux#17.itm} 16 {mux#17.itm(0)} {mux#17.itm(1)} {mux#17.itm(2)} {mux#17.itm(3)} {mux#17.itm(4)} {mux#17.itm(5)} {mux#17.itm(6)} {mux#17.itm(7)} {mux#17.itm(8)} {mux#17.itm(9)} {mux#17.itm(10)} {mux#17.itm(11)} {mux#17.itm(12)} {mux#17.itm(13)} {mux#17.itm(14)} {mux#17.itm(15)} -attr xrf 44325 -attr oid 201 -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {FRAME:for:acc#1.itm(0)} -attr vt d
+load net {FRAME:for:acc#1.itm(1)} -attr vt d
+load net {FRAME:for:acc#1.itm(2)} -attr vt d
+load net {FRAME:for:acc#1.itm(3)} -attr vt d
+load net {FRAME:for:acc#1.itm(4)} -attr vt d
+load net {FRAME:for:acc#1.itm(5)} -attr vt d
+load net {FRAME:for:acc#1.itm(6)} -attr vt d
+load net {FRAME:for:acc#1.itm(7)} -attr vt d
+load net {FRAME:for:acc#1.itm(8)} -attr vt d
+load net {FRAME:for:acc#1.itm(9)} -attr vt d
+load net {FRAME:for:acc#1.itm(10)} -attr vt d
+load net {FRAME:for:acc#1.itm(11)} -attr vt d
+load net {FRAME:for:acc#1.itm(12)} -attr vt d
+load net {FRAME:for:acc#1.itm(13)} -attr vt d
+load net {FRAME:for:acc#1.itm(14)} -attr vt d
+load net {FRAME:for:acc#1.itm(15)} -attr vt d
+load netBundle {FRAME:for:acc#1.itm} 16 {FRAME:for:acc#1.itm(0)} {FRAME:for:acc#1.itm(1)} {FRAME:for:acc#1.itm(2)} {FRAME:for:acc#1.itm(3)} {FRAME:for:acc#1.itm(4)} {FRAME:for:acc#1.itm(5)} {FRAME:for:acc#1.itm(6)} {FRAME:for:acc#1.itm(7)} {FRAME:for:acc#1.itm(8)} {FRAME:for:acc#1.itm(9)} {FRAME:for:acc#1.itm(10)} {FRAME:for:acc#1.itm(11)} {FRAME:for:acc#1.itm(12)} {FRAME:for:acc#1.itm(13)} {FRAME:for:acc#1.itm(14)} {FRAME:for:acc#1.itm(15)} -attr xrf 44326 -attr oid 202 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:mul.itm(0)} -attr vt d
+load net {FRAME:for:mul.itm(1)} -attr vt d
+load net {FRAME:for:mul.itm(2)} -attr vt d
+load net {FRAME:for:mul.itm(3)} -attr vt d
+load net {FRAME:for:mul.itm(4)} -attr vt d
+load net {FRAME:for:mul.itm(5)} -attr vt d
+load net {FRAME:for:mul.itm(6)} -attr vt d
+load net {FRAME:for:mul.itm(7)} -attr vt d
+load net {FRAME:for:mul.itm(8)} -attr vt d
+load net {FRAME:for:mul.itm(9)} -attr vt d
+load net {FRAME:for:mul.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul.itm} 11 {FRAME:for:mul.itm(0)} {FRAME:for:mul.itm(1)} {FRAME:for:mul.itm(2)} {FRAME:for:mul.itm(3)} {FRAME:for:mul.itm(4)} {FRAME:for:mul.itm(5)} {FRAME:for:mul.itm(6)} {FRAME:for:mul.itm(7)} {FRAME:for:mul.itm(8)} {FRAME:for:mul.itm(9)} {FRAME:for:mul.itm(10)} -attr xrf 44327 -attr oid 203 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {regs.operator[]#18:mux.itm(0)} -attr vt d
+load net {regs.operator[]#18:mux.itm(1)} -attr vt d
+load net {regs.operator[]#18:mux.itm(2)} -attr vt d
+load net {regs.operator[]#18:mux.itm(3)} -attr vt d
+load net {regs.operator[]#18:mux.itm(4)} -attr vt d
+load net {regs.operator[]#18:mux.itm(5)} -attr vt d
+load net {regs.operator[]#18:mux.itm(6)} -attr vt d
+load net {regs.operator[]#18:mux.itm(7)} -attr vt d
+load net {regs.operator[]#18:mux.itm(8)} -attr vt d
+load net {regs.operator[]#18:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#18:mux.itm} 10 {regs.operator[]#18:mux.itm(0)} {regs.operator[]#18:mux.itm(1)} {regs.operator[]#18:mux.itm(2)} {regs.operator[]#18:mux.itm(3)} {regs.operator[]#18:mux.itm(4)} {regs.operator[]#18:mux.itm(5)} {regs.operator[]#18:mux.itm(6)} {regs.operator[]#18:mux.itm(7)} {regs.operator[]#18:mux.itm(8)} {regs.operator[]#18:mux.itm(9)} -attr xrf 44328 -attr oid 204 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(9)} -attr xrf 44329 -attr oid 205 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#8.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#8.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(9)} -attr xrf 44330 -attr oid 206 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#8.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#8.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(9)} -attr xrf 44331 -attr oid 207 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {mux#18.itm(0)} -attr vt d
+load net {mux#18.itm(1)} -attr vt d
+load net {mux#18.itm(2)} -attr vt d
+load net {mux#18.itm(3)} -attr vt d
+load net {mux#18.itm(4)} -attr vt d
+load net {mux#18.itm(5)} -attr vt d
+load net {mux#18.itm(6)} -attr vt d
+load net {mux#18.itm(7)} -attr vt d
+load net {mux#18.itm(8)} -attr vt d
+load net {mux#18.itm(9)} -attr vt d
+load net {mux#18.itm(10)} -attr vt d
+load net {mux#18.itm(11)} -attr vt d
+load net {mux#18.itm(12)} -attr vt d
+load net {mux#18.itm(13)} -attr vt d
+load net {mux#18.itm(14)} -attr vt d
+load net {mux#18.itm(15)} -attr vt d
+load net {mux#18.itm(16)} -attr vt d
+load net {mux#18.itm(17)} -attr vt d
+load net {mux#18.itm(18)} -attr vt d
+load netBundle {mux#18.itm} 19 {mux#18.itm(0)} {mux#18.itm(1)} {mux#18.itm(2)} {mux#18.itm(3)} {mux#18.itm(4)} {mux#18.itm(5)} {mux#18.itm(6)} {mux#18.itm(7)} {mux#18.itm(8)} {mux#18.itm(9)} {mux#18.itm(10)} {mux#18.itm(11)} {mux#18.itm(12)} {mux#18.itm(13)} {mux#18.itm(14)} {mux#18.itm(15)} {mux#18.itm(16)} {mux#18.itm(17)} {mux#18.itm(18)} -attr xrf 44332 -attr oid 208 -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {FRAME:acc#22.itm(0)} -attr vt d
+load net {FRAME:acc#22.itm(1)} -attr vt d
+load net {FRAME:acc#22.itm(2)} -attr vt d
+load net {FRAME:acc#22.itm(3)} -attr vt d
+load net {FRAME:acc#22.itm(4)} -attr vt d
+load net {FRAME:acc#22.itm(5)} -attr vt d
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+load netBundle {slc(red#2.sg1.sva)#6.itm} 3 {slc(red#2.sg1.sva)#6.itm(0)} {slc(red#2.sg1.sva)#6.itm(1)} {slc(red#2.sg1.sva)#6.itm(2)} -attr xrf 44360 -attr oid 236 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {FRAME:not#1.itm(0)} -attr vt d
+load net {FRAME:not#1.itm(1)} -attr vt d
+load net {FRAME:not#1.itm(2)} -attr vt d
+load netBundle {FRAME:not#1.itm} 3 {FRAME:not#1.itm(0)} {FRAME:not#1.itm(1)} {FRAME:not#1.itm(2)} -attr xrf 44361 -attr oid 237 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {slc(red#2.sg1.sva)#7.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#7.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#7.itm} 3 {slc(red#2.sg1.sva)#7.itm(0)} {slc(red#2.sg1.sva)#7.itm(1)} {slc(red#2.sg1.sva)#7.itm(2)} -attr xrf 44362 -attr oid 238 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {ACC2-3:acc#1.itm(0)} -attr vt d
+load net {ACC2-3:acc#1.itm(1)} -attr vt d
+load net {ACC2-3:acc#1.itm(2)} -attr vt d
+load net {ACC2-3:acc#1.itm(3)} -attr vt d
+load net {ACC2-3:acc#1.itm(4)} -attr vt d
+load net {ACC2-3:acc#1.itm(5)} -attr vt d
+load net {ACC2-3:acc#1.itm(6)} -attr vt d
+load net {ACC2-3:acc#1.itm(7)} -attr vt d
+load net {ACC2-3:acc#1.itm(8)} -attr vt d
+load net {ACC2-3:acc#1.itm(9)} -attr vt d
+load net {ACC2-3:acc#1.itm(10)} -attr vt d
+load net {ACC2-3:acc#1.itm(11)} -attr vt d
+load net {ACC2-3:acc#1.itm(12)} -attr vt d
+load net {ACC2-3:acc#1.itm(13)} -attr vt d
+load net {ACC2-3:acc#1.itm(14)} -attr vt d
+load net {ACC2-3:acc#1.itm(15)} -attr vt d
+load netBundle {ACC2-3:acc#1.itm} 16 {ACC2-3:acc#1.itm(0)} {ACC2-3:acc#1.itm(1)} {ACC2-3:acc#1.itm(2)} {ACC2-3:acc#1.itm(3)} {ACC2-3:acc#1.itm(4)} {ACC2-3:acc#1.itm(5)} {ACC2-3:acc#1.itm(6)} {ACC2-3:acc#1.itm(7)} {ACC2-3:acc#1.itm(8)} {ACC2-3:acc#1.itm(9)} {ACC2-3:acc#1.itm(10)} {ACC2-3:acc#1.itm(11)} {ACC2-3:acc#1.itm(12)} {ACC2-3:acc#1.itm(13)} {ACC2-3:acc#1.itm(14)} {ACC2-3:acc#1.itm(15)} -attr xrf 44363 -attr oid 239 -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2:conc.itm(0)} -attr vt d
+load net {ACC2:conc.itm(1)} -attr vt d
+load net {ACC2:conc.itm(2)} -attr vt d
+load net {ACC2:conc.itm(3)} -attr vt d
+load net {ACC2:conc.itm(4)} -attr vt d
+load net {ACC2:conc.itm(5)} -attr vt d
+load net {ACC2:conc.itm(6)} -attr vt d
+load net {ACC2:conc.itm(7)} -attr vt d
+load net {ACC2:conc.itm(8)} -attr vt d
+load net {ACC2:conc.itm(9)} -attr vt d
+load net {ACC2:conc.itm(10)} -attr vt d
+load net {ACC2:conc.itm(11)} -attr vt d
+load net {ACC2:conc.itm(12)} -attr vt d
+load net {ACC2:conc.itm(13)} -attr vt d
+load net {ACC2:conc.itm(14)} -attr vt d
+load net {ACC2:conc.itm(15)} -attr vt d
+load netBundle {ACC2:conc.itm} 16 {ACC2:conc.itm(0)} {ACC2:conc.itm(1)} {ACC2:conc.itm(2)} {ACC2:conc.itm(3)} {ACC2:conc.itm(4)} {ACC2:conc.itm(5)} {ACC2:conc.itm(6)} {ACC2:conc.itm(7)} {ACC2:conc.itm(8)} {ACC2:conc.itm(9)} {ACC2:conc.itm(10)} {ACC2:conc.itm(11)} {ACC2:conc.itm(12)} {ACC2:conc.itm(13)} {ACC2:conc.itm(14)} {ACC2:conc.itm(15)} -attr xrf 44364 -attr oid 240 -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(0)} -attr vt d
+load net {ACC2:acc.itm(1)} -attr vt d
+load net {ACC2:acc.itm(2)} -attr vt d
+load net {ACC2:acc.itm(3)} -attr vt d
+load net {ACC2:acc.itm(4)} -attr vt d
+load net {ACC2:acc.itm(5)} -attr vt d
+load net {ACC2:acc.itm(6)} -attr vt d
+load net {ACC2:acc.itm(7)} -attr vt d
+load net {ACC2:acc.itm(8)} -attr vt d
+load net {ACC2:acc.itm(9)} -attr vt d
+load net {ACC2:acc.itm(10)} -attr vt d
+load net {ACC2:acc.itm(11)} -attr vt d
+load net {ACC2:acc.itm(12)} -attr vt d
+load net {ACC2:acc.itm(13)} -attr vt d
+load net {ACC2:acc.itm(14)} -attr vt d
+load netBundle {ACC2:acc.itm} 15 {ACC2:acc.itm(0)} {ACC2:acc.itm(1)} {ACC2:acc.itm(2)} {ACC2:acc.itm(3)} {ACC2:acc.itm(4)} {ACC2:acc.itm(5)} {ACC2:acc.itm(6)} {ACC2:acc.itm(7)} {ACC2:acc.itm(8)} {ACC2:acc.itm(9)} {ACC2:acc.itm(10)} {ACC2:acc.itm(11)} {ACC2:acc.itm(12)} {ACC2:acc.itm(13)} {ACC2:acc.itm(14)} -attr xrf 44365 -attr oid 241 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {slc(r(2).sva#1).itm(0)} -attr vt d
+load net {slc(r(2).sva#1).itm(1)} -attr vt d
+load net {slc(r(2).sva#1).itm(2)} -attr vt d
+load net {slc(r(2).sva#1).itm(3)} -attr vt d
+load net {slc(r(2).sva#1).itm(4)} -attr vt d
+load net {slc(r(2).sva#1).itm(5)} -attr vt d
+load net {slc(r(2).sva#1).itm(6)} -attr vt d
+load net {slc(r(2).sva#1).itm(7)} -attr vt d
+load net {slc(r(2).sva#1).itm(8)} -attr vt d
+load net {slc(r(2).sva#1).itm(9)} -attr vt d
+load net {slc(r(2).sva#1).itm(10)} -attr vt d
+load net {slc(r(2).sva#1).itm(11)} -attr vt d
+load net {slc(r(2).sva#1).itm(12)} -attr vt d
+load net {slc(r(2).sva#1).itm(13)} -attr vt d
+load net {slc(r(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(r(2).sva#1).itm} 15 {slc(r(2).sva#1).itm(0)} {slc(r(2).sva#1).itm(1)} {slc(r(2).sva#1).itm(2)} {slc(r(2).sva#1).itm(3)} {slc(r(2).sva#1).itm(4)} {slc(r(2).sva#1).itm(5)} {slc(r(2).sva#1).itm(6)} {slc(r(2).sva#1).itm(7)} {slc(r(2).sva#1).itm(8)} {slc(r(2).sva#1).itm(9)} {slc(r(2).sva#1).itm(10)} {slc(r(2).sva#1).itm(11)} {slc(r(2).sva#1).itm(12)} {slc(r(2).sva#1).itm(13)} {slc(r(2).sva#1).itm(14)} -attr xrf 44366 -attr oid 242 -attr vt d -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {slc(red#2.sg1.sva)#12.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#12.itm(1)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#12.itm} 2 {slc(red#2.sg1.sva)#12.itm(0)} {slc(red#2.sg1.sva)#12.itm(1)} -attr xrf 44367 -attr oid 243 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#12.itm}
+load net {ACC2-3:acc#3.itm(0)} -attr vt d
+load net {ACC2-3:acc#3.itm(1)} -attr vt d
+load net {ACC2-3:acc#3.itm(2)} -attr vt d
+load net {ACC2-3:acc#3.itm(3)} -attr vt d
+load net {ACC2-3:acc#3.itm(4)} -attr vt d
+load net {ACC2-3:acc#3.itm(5)} -attr vt d
+load net {ACC2-3:acc#3.itm(6)} -attr vt d
+load net {ACC2-3:acc#3.itm(7)} -attr vt d
+load net {ACC2-3:acc#3.itm(8)} -attr vt d
+load net {ACC2-3:acc#3.itm(9)} -attr vt d
+load net {ACC2-3:acc#3.itm(10)} -attr vt d
+load net {ACC2-3:acc#3.itm(11)} -attr vt d
+load net {ACC2-3:acc#3.itm(12)} -attr vt d
+load net {ACC2-3:acc#3.itm(13)} -attr vt d
+load net {ACC2-3:acc#3.itm(14)} -attr vt d
+load net {ACC2-3:acc#3.itm(15)} -attr vt d
+load netBundle {ACC2-3:acc#3.itm} 16 {ACC2-3:acc#3.itm(0)} {ACC2-3:acc#3.itm(1)} {ACC2-3:acc#3.itm(2)} {ACC2-3:acc#3.itm(3)} {ACC2-3:acc#3.itm(4)} {ACC2-3:acc#3.itm(5)} {ACC2-3:acc#3.itm(6)} {ACC2-3:acc#3.itm(7)} {ACC2-3:acc#3.itm(8)} {ACC2-3:acc#3.itm(9)} {ACC2-3:acc#3.itm(10)} {ACC2-3:acc#3.itm(11)} {ACC2-3:acc#3.itm(12)} {ACC2-3:acc#3.itm(13)} {ACC2-3:acc#3.itm(14)} {ACC2-3:acc#3.itm(15)} -attr xrf 44368 -attr oid 244 -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2:conc#2.itm(0)} -attr vt d
+load net {ACC2:conc#2.itm(1)} -attr vt d
+load net {ACC2:conc#2.itm(2)} -attr vt d
+load net {ACC2:conc#2.itm(3)} -attr vt d
+load net {ACC2:conc#2.itm(4)} -attr vt d
+load net {ACC2:conc#2.itm(5)} -attr vt d
+load net {ACC2:conc#2.itm(6)} -attr vt d
+load net {ACC2:conc#2.itm(7)} -attr vt d
+load net {ACC2:conc#2.itm(8)} -attr vt d
+load net {ACC2:conc#2.itm(9)} -attr vt d
+load net {ACC2:conc#2.itm(10)} -attr vt d
+load net {ACC2:conc#2.itm(11)} -attr vt d
+load net {ACC2:conc#2.itm(12)} -attr vt d
+load net {ACC2:conc#2.itm(13)} -attr vt d
+load net {ACC2:conc#2.itm(14)} -attr vt d
+load net {ACC2:conc#2.itm(15)} -attr vt d
+load netBundle {ACC2:conc#2.itm} 16 {ACC2:conc#2.itm(0)} {ACC2:conc#2.itm(1)} {ACC2:conc#2.itm(2)} {ACC2:conc#2.itm(3)} {ACC2:conc#2.itm(4)} {ACC2:conc#2.itm(5)} {ACC2:conc#2.itm(6)} {ACC2:conc#2.itm(7)} {ACC2:conc#2.itm(8)} {ACC2:conc#2.itm(9)} {ACC2:conc#2.itm(10)} {ACC2:conc#2.itm(11)} {ACC2:conc#2.itm(12)} {ACC2:conc#2.itm(13)} {ACC2:conc#2.itm(14)} {ACC2:conc#2.itm(15)} -attr xrf 44369 -attr oid 245 -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(0)} -attr vt d
+load net {ACC2:acc#8.itm(1)} -attr vt d
+load net {ACC2:acc#8.itm(2)} -attr vt d
+load net {ACC2:acc#8.itm(3)} -attr vt d
+load net {ACC2:acc#8.itm(4)} -attr vt d
+load net {ACC2:acc#8.itm(5)} -attr vt d
+load net {ACC2:acc#8.itm(6)} -attr vt d
+load net {ACC2:acc#8.itm(7)} -attr vt d
+load net {ACC2:acc#8.itm(8)} -attr vt d
+load net {ACC2:acc#8.itm(9)} -attr vt d
+load net {ACC2:acc#8.itm(10)} -attr vt d
+load net {ACC2:acc#8.itm(11)} -attr vt d
+load net {ACC2:acc#8.itm(12)} -attr vt d
+load net {ACC2:acc#8.itm(13)} -attr vt d
+load net {ACC2:acc#8.itm(14)} -attr vt d
+load netBundle {ACC2:acc#8.itm} 15 {ACC2:acc#8.itm(0)} {ACC2:acc#8.itm(1)} {ACC2:acc#8.itm(2)} {ACC2:acc#8.itm(3)} {ACC2:acc#8.itm(4)} {ACC2:acc#8.itm(5)} {ACC2:acc#8.itm(6)} {ACC2:acc#8.itm(7)} {ACC2:acc#8.itm(8)} {ACC2:acc#8.itm(9)} {ACC2:acc#8.itm(10)} {ACC2:acc#8.itm(11)} {ACC2:acc#8.itm(12)} {ACC2:acc#8.itm(13)} {ACC2:acc#8.itm(14)} -attr xrf 44370 -attr oid 246 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {slc(b(2).sva#1).itm(0)} -attr vt d
+load net {slc(b(2).sva#1).itm(1)} -attr vt d
+load net {slc(b(2).sva#1).itm(2)} -attr vt d
+load net {slc(b(2).sva#1).itm(3)} -attr vt d
+load net {slc(b(2).sva#1).itm(4)} -attr vt d
+load net {slc(b(2).sva#1).itm(5)} -attr vt d
+load net {slc(b(2).sva#1).itm(6)} -attr vt d
+load net {slc(b(2).sva#1).itm(7)} -attr vt d
+load net {slc(b(2).sva#1).itm(8)} -attr vt d
+load net {slc(b(2).sva#1).itm(9)} -attr vt d
+load net {slc(b(2).sva#1).itm(10)} -attr vt d
+load net {slc(b(2).sva#1).itm(11)} -attr vt d
+load net {slc(b(2).sva#1).itm(12)} -attr vt d
+load net {slc(b(2).sva#1).itm(13)} -attr vt d
+load net {slc(b(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(b(2).sva#1).itm} 15 {slc(b(2).sva#1).itm(0)} {slc(b(2).sva#1).itm(1)} {slc(b(2).sva#1).itm(2)} {slc(b(2).sva#1).itm(3)} {slc(b(2).sva#1).itm(4)} {slc(b(2).sva#1).itm(5)} {slc(b(2).sva#1).itm(6)} {slc(b(2).sva#1).itm(7)} {slc(b(2).sva#1).itm(8)} {slc(b(2).sva#1).itm(9)} {slc(b(2).sva#1).itm(10)} {slc(b(2).sva#1).itm(11)} {slc(b(2).sva#1).itm(12)} {slc(b(2).sva#1).itm(13)} {slc(b(2).sva#1).itm(14)} -attr xrf 44371 -attr oid 247 -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {FRAME:acc#28.itm(0)} -attr vt d
+load net {FRAME:acc#28.itm(1)} -attr vt d
+load net {FRAME:acc#28.itm(2)} -attr vt d
+load net {FRAME:acc#28.itm(3)} -attr vt d
+load net {FRAME:acc#28.itm(4)} -attr vt d
+load net {FRAME:acc#28.itm(5)} -attr vt d
+load netBundle {FRAME:acc#28.itm} 6 {FRAME:acc#28.itm(0)} {FRAME:acc#28.itm(1)} {FRAME:acc#28.itm(2)} {FRAME:acc#28.itm(3)} {FRAME:acc#28.itm(4)} {FRAME:acc#28.itm(5)} -attr xrf 44372 -attr oid 248 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#27.itm(0)} -attr vt d
+load net {FRAME:acc#27.itm(1)} -attr vt d
+load net {FRAME:acc#27.itm(2)} -attr vt d
+load net {FRAME:acc#27.itm(3)} -attr vt d
+load net {FRAME:acc#27.itm(4)} -attr vt d
+load netBundle {FRAME:acc#27.itm} 5 {FRAME:acc#27.itm(0)} {FRAME:acc#27.itm(1)} {FRAME:acc#27.itm(2)} {FRAME:acc#27.itm(3)} {FRAME:acc#27.itm(4)} -attr xrf 44373 -attr oid 249 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#25.itm(0)} -attr vt d
+load net {FRAME:acc#25.itm(1)} -attr vt d
+load net {FRAME:acc#25.itm(2)} -attr vt d
+load net {FRAME:acc#25.itm(3)} -attr vt d
+load netBundle {FRAME:acc#25.itm} 4 {FRAME:acc#25.itm(0)} {FRAME:acc#25.itm(1)} {FRAME:acc#25.itm(2)} {FRAME:acc#25.itm(3)} -attr xrf 44374 -attr oid 250 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {slc(blue#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#1.itm} 3 {slc(blue#2.sg1.sva)#1.itm(0)} {slc(blue#2.sg1.sva)#1.itm(1)} {slc(blue#2.sg1.sva)#1.itm(2)} -attr xrf 44375 -attr oid 251 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {FRAME:not#18.itm(0)} -attr vt d
+load net {FRAME:not#18.itm(1)} -attr vt d
+load net {FRAME:not#18.itm(2)} -attr vt d
+load netBundle {FRAME:not#18.itm} 3 {FRAME:not#18.itm(0)} {FRAME:not#18.itm(1)} {FRAME:not#18.itm(2)} -attr xrf 44376 -attr oid 252 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {slc(blue#2.sg1.sva)#3.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#3.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#3.itm} 3 {slc(blue#2.sg1.sva)#3.itm(0)} {slc(blue#2.sg1.sva)#3.itm(1)} {slc(blue#2.sg1.sva)#3.itm(2)} -attr xrf 44377 -attr oid 253 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {FRAME:acc#24.itm(0)} -attr vt d
+load net {FRAME:acc#24.itm(1)} -attr vt d
+load net {FRAME:acc#24.itm(2)} -attr vt d
+load net {FRAME:acc#24.itm(3)} -attr vt d
+load netBundle {FRAME:acc#24.itm} 4 {FRAME:acc#24.itm(0)} {FRAME:acc#24.itm(1)} {FRAME:acc#24.itm(2)} {FRAME:acc#24.itm(3)} -attr xrf 44378 -attr oid 254 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {conc#154.itm(0)} -attr vt d
+load net {conc#154.itm(1)} -attr vt d
+load net {conc#154.itm(2)} -attr vt d
+load netBundle {conc#154.itm} 3 {conc#154.itm(0)} {conc#154.itm(1)} {conc#154.itm(2)} -attr xrf 44379 -attr oid 255 -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {slc(blue#2.sg1.sva)#4.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#4.itm} 2 {slc(blue#2.sg1.sva)#4.itm(0)} {slc(blue#2.sg1.sva)#4.itm(1)} -attr xrf 44380 -attr oid 256 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#4.itm}
+load net {FRAME:acc#26.itm(0)} -attr vt d
+load net {FRAME:acc#26.itm(1)} -attr vt d
+load net {FRAME:acc#26.itm(2)} -attr vt d
+load net {FRAME:acc#26.itm(3)} -attr vt d
+load netBundle {FRAME:acc#26.itm} 4 {FRAME:acc#26.itm(0)} {FRAME:acc#26.itm(1)} {FRAME:acc#26.itm(2)} {FRAME:acc#26.itm(3)} -attr xrf 44381 -attr oid 257 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {slc(blue#2.sg1.sva)#5.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#5.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#5.itm} 3 {slc(blue#2.sg1.sva)#5.itm(0)} {slc(blue#2.sg1.sva)#5.itm(1)} {slc(blue#2.sg1.sva)#5.itm(2)} -attr xrf 44382 -attr oid 258 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {FRAME:not#17.itm(0)} -attr vt d
+load net {FRAME:not#17.itm(1)} -attr vt d
+load net {FRAME:not#17.itm(2)} -attr vt d
+load netBundle {FRAME:not#17.itm} 3 {FRAME:not#17.itm(0)} {FRAME:not#17.itm(1)} {FRAME:not#17.itm(2)} -attr xrf 44383 -attr oid 259 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {slc(blue#2.sg1.sva)#6.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#6.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#6.itm} 3 {slc(blue#2.sg1.sva)#6.itm(0)} {slc(blue#2.sg1.sva)#6.itm(1)} {slc(blue#2.sg1.sva)#6.itm(2)} -attr xrf 44384 -attr oid 260 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#2.itm(0)} -attr vt d
+load net {ACC2-3:acc#2.itm(1)} -attr vt d
+load net {ACC2-3:acc#2.itm(2)} -attr vt d
+load net {ACC2-3:acc#2.itm(3)} -attr vt d
+load net {ACC2-3:acc#2.itm(4)} -attr vt d
+load net {ACC2-3:acc#2.itm(5)} -attr vt d
+load net {ACC2-3:acc#2.itm(6)} -attr vt d
+load net {ACC2-3:acc#2.itm(7)} -attr vt d
+load net {ACC2-3:acc#2.itm(8)} -attr vt d
+load net {ACC2-3:acc#2.itm(9)} -attr vt d
+load net {ACC2-3:acc#2.itm(10)} -attr vt d
+load net {ACC2-3:acc#2.itm(11)} -attr vt d
+load net {ACC2-3:acc#2.itm(12)} -attr vt d
+load net {ACC2-3:acc#2.itm(13)} -attr vt d
+load net {ACC2-3:acc#2.itm(14)} -attr vt d
+load net {ACC2-3:acc#2.itm(15)} -attr vt d
+load netBundle {ACC2-3:acc#2.itm} 16 {ACC2-3:acc#2.itm(0)} {ACC2-3:acc#2.itm(1)} {ACC2-3:acc#2.itm(2)} {ACC2-3:acc#2.itm(3)} {ACC2-3:acc#2.itm(4)} {ACC2-3:acc#2.itm(5)} {ACC2-3:acc#2.itm(6)} {ACC2-3:acc#2.itm(7)} {ACC2-3:acc#2.itm(8)} {ACC2-3:acc#2.itm(9)} {ACC2-3:acc#2.itm(10)} {ACC2-3:acc#2.itm(11)} {ACC2-3:acc#2.itm(12)} {ACC2-3:acc#2.itm(13)} {ACC2-3:acc#2.itm(14)} {ACC2-3:acc#2.itm(15)} -attr xrf 44385 -attr oid 261 -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2:conc#1.itm(0)} -attr vt d
+load net {ACC2:conc#1.itm(1)} -attr vt d
+load net {ACC2:conc#1.itm(2)} -attr vt d
+load net {ACC2:conc#1.itm(3)} -attr vt d
+load net {ACC2:conc#1.itm(4)} -attr vt d
+load net {ACC2:conc#1.itm(5)} -attr vt d
+load net {ACC2:conc#1.itm(6)} -attr vt d
+load net {ACC2:conc#1.itm(7)} -attr vt d
+load net {ACC2:conc#1.itm(8)} -attr vt d
+load net {ACC2:conc#1.itm(9)} -attr vt d
+load net {ACC2:conc#1.itm(10)} -attr vt d
+load net {ACC2:conc#1.itm(11)} -attr vt d
+load net {ACC2:conc#1.itm(12)} -attr vt d
+load net {ACC2:conc#1.itm(13)} -attr vt d
+load net {ACC2:conc#1.itm(14)} -attr vt d
+load net {ACC2:conc#1.itm(15)} -attr vt d
+load netBundle {ACC2:conc#1.itm} 16 {ACC2:conc#1.itm(0)} {ACC2:conc#1.itm(1)} {ACC2:conc#1.itm(2)} {ACC2:conc#1.itm(3)} {ACC2:conc#1.itm(4)} {ACC2:conc#1.itm(5)} {ACC2:conc#1.itm(6)} {ACC2:conc#1.itm(7)} {ACC2:conc#1.itm(8)} {ACC2:conc#1.itm(9)} {ACC2:conc#1.itm(10)} {ACC2:conc#1.itm(11)} {ACC2:conc#1.itm(12)} {ACC2:conc#1.itm(13)} {ACC2:conc#1.itm(14)} {ACC2:conc#1.itm(15)} -attr xrf 44386 -attr oid 262 -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(0)} -attr vt d
+load net {ACC2:acc#7.itm(1)} -attr vt d
+load net {ACC2:acc#7.itm(2)} -attr vt d
+load net {ACC2:acc#7.itm(3)} -attr vt d
+load net {ACC2:acc#7.itm(4)} -attr vt d
+load net {ACC2:acc#7.itm(5)} -attr vt d
+load net {ACC2:acc#7.itm(6)} -attr vt d
+load net {ACC2:acc#7.itm(7)} -attr vt d
+load net {ACC2:acc#7.itm(8)} -attr vt d
+load net {ACC2:acc#7.itm(9)} -attr vt d
+load net {ACC2:acc#7.itm(10)} -attr vt d
+load net {ACC2:acc#7.itm(11)} -attr vt d
+load net {ACC2:acc#7.itm(12)} -attr vt d
+load net {ACC2:acc#7.itm(13)} -attr vt d
+load net {ACC2:acc#7.itm(14)} -attr vt d
+load netBundle {ACC2:acc#7.itm} 15 {ACC2:acc#7.itm(0)} {ACC2:acc#7.itm(1)} {ACC2:acc#7.itm(2)} {ACC2:acc#7.itm(3)} {ACC2:acc#7.itm(4)} {ACC2:acc#7.itm(5)} {ACC2:acc#7.itm(6)} {ACC2:acc#7.itm(7)} {ACC2:acc#7.itm(8)} {ACC2:acc#7.itm(9)} {ACC2:acc#7.itm(10)} {ACC2:acc#7.itm(11)} {ACC2:acc#7.itm(12)} {ACC2:acc#7.itm(13)} {ACC2:acc#7.itm(14)} -attr xrf 44387 -attr oid 263 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {slc(g(2).sva#1).itm(0)} -attr vt d
+load net {slc(g(2).sva#1).itm(1)} -attr vt d
+load net {slc(g(2).sva#1).itm(2)} -attr vt d
+load net {slc(g(2).sva#1).itm(3)} -attr vt d
+load net {slc(g(2).sva#1).itm(4)} -attr vt d
+load net {slc(g(2).sva#1).itm(5)} -attr vt d
+load net {slc(g(2).sva#1).itm(6)} -attr vt d
+load net {slc(g(2).sva#1).itm(7)} -attr vt d
+load net {slc(g(2).sva#1).itm(8)} -attr vt d
+load net {slc(g(2).sva#1).itm(9)} -attr vt d
+load net {slc(g(2).sva#1).itm(10)} -attr vt d
+load net {slc(g(2).sva#1).itm(11)} -attr vt d
+load net {slc(g(2).sva#1).itm(12)} -attr vt d
+load net {slc(g(2).sva#1).itm(13)} -attr vt d
+load net {slc(g(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(g(2).sva#1).itm} 15 {slc(g(2).sva#1).itm(0)} {slc(g(2).sva#1).itm(1)} {slc(g(2).sva#1).itm(2)} {slc(g(2).sva#1).itm(3)} {slc(g(2).sva#1).itm(4)} {slc(g(2).sva#1).itm(5)} {slc(g(2).sva#1).itm(6)} {slc(g(2).sva#1).itm(7)} {slc(g(2).sva#1).itm(8)} {slc(g(2).sva#1).itm(9)} {slc(g(2).sva#1).itm(10)} {slc(g(2).sva#1).itm(11)} {slc(g(2).sva#1).itm(12)} {slc(g(2).sva#1).itm(13)} {slc(g(2).sva#1).itm(14)} -attr xrf 44388 -attr oid 264 -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {FRAME:acc#16.itm(0)} -attr vt d
+load net {FRAME:acc#16.itm(1)} -attr vt d
+load net {FRAME:acc#16.itm(2)} -attr vt d
+load net {FRAME:acc#16.itm(3)} -attr vt d
+load net {FRAME:acc#16.itm(4)} -attr vt d
+load net {FRAME:acc#16.itm(5)} -attr vt d
+load netBundle {FRAME:acc#16.itm} 6 {FRAME:acc#16.itm(0)} {FRAME:acc#16.itm(1)} {FRAME:acc#16.itm(2)} {FRAME:acc#16.itm(3)} {FRAME:acc#16.itm(4)} {FRAME:acc#16.itm(5)} -attr xrf 44389 -attr oid 265 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#15.itm(0)} -attr vt d
+load net {FRAME:acc#15.itm(1)} -attr vt d
+load net {FRAME:acc#15.itm(2)} -attr vt d
+load net {FRAME:acc#15.itm(3)} -attr vt d
+load net {FRAME:acc#15.itm(4)} -attr vt d
+load netBundle {FRAME:acc#15.itm} 5 {FRAME:acc#15.itm(0)} {FRAME:acc#15.itm(1)} {FRAME:acc#15.itm(2)} {FRAME:acc#15.itm(3)} {FRAME:acc#15.itm(4)} -attr xrf 44390 -attr oid 266 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#13.itm(0)} -attr vt d
+load net {FRAME:acc#13.itm(1)} -attr vt d
+load net {FRAME:acc#13.itm(2)} -attr vt d
+load net {FRAME:acc#13.itm(3)} -attr vt d
+load netBundle {FRAME:acc#13.itm} 4 {FRAME:acc#13.itm(0)} {FRAME:acc#13.itm(1)} {FRAME:acc#13.itm(2)} {FRAME:acc#13.itm(3)} -attr xrf 44391 -attr oid 267 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {slc(green#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#1.itm} 3 {slc(green#2.sg1.sva)#1.itm(0)} {slc(green#2.sg1.sva)#1.itm(1)} {slc(green#2.sg1.sva)#1.itm(2)} -attr xrf 44392 -attr oid 268 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {FRAME:not#10.itm(0)} -attr vt d
+load net {FRAME:not#10.itm(1)} -attr vt d
+load net {FRAME:not#10.itm(2)} -attr vt d
+load netBundle {FRAME:not#10.itm} 3 {FRAME:not#10.itm(0)} {FRAME:not#10.itm(1)} {FRAME:not#10.itm(2)} -attr xrf 44393 -attr oid 269 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {slc(green#2.sg1.sva)#3.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#3.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#3.itm} 3 {slc(green#2.sg1.sva)#3.itm(0)} {slc(green#2.sg1.sva)#3.itm(1)} {slc(green#2.sg1.sva)#3.itm(2)} -attr xrf 44394 -attr oid 270 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {FRAME:acc#12.itm(0)} -attr vt d
+load net {FRAME:acc#12.itm(1)} -attr vt d
+load net {FRAME:acc#12.itm(2)} -attr vt d
+load net {FRAME:acc#12.itm(3)} -attr vt d
+load netBundle {FRAME:acc#12.itm} 4 {FRAME:acc#12.itm(0)} {FRAME:acc#12.itm(1)} {FRAME:acc#12.itm(2)} {FRAME:acc#12.itm(3)} -attr xrf 44395 -attr oid 271 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {conc#155.itm(0)} -attr vt d
+load net {conc#155.itm(1)} -attr vt d
+load net {conc#155.itm(2)} -attr vt d
+load netBundle {conc#155.itm} 3 {conc#155.itm(0)} {conc#155.itm(1)} {conc#155.itm(2)} -attr xrf 44396 -attr oid 272 -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {slc(green#2.sg1.sva)#4.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#4.itm} 2 {slc(green#2.sg1.sva)#4.itm(0)} {slc(green#2.sg1.sva)#4.itm(1)} -attr xrf 44397 -attr oid 273 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#4.itm}
+load net {FRAME:acc#14.itm(0)} -attr vt d
+load net {FRAME:acc#14.itm(1)} -attr vt d
+load net {FRAME:acc#14.itm(2)} -attr vt d
+load net {FRAME:acc#14.itm(3)} -attr vt d
+load netBundle {FRAME:acc#14.itm} 4 {FRAME:acc#14.itm(0)} {FRAME:acc#14.itm(1)} {FRAME:acc#14.itm(2)} {FRAME:acc#14.itm(3)} -attr xrf 44398 -attr oid 274 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {slc(green#2.sg1.sva)#5.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#5.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#5.itm} 3 {slc(green#2.sg1.sva)#5.itm(0)} {slc(green#2.sg1.sva)#5.itm(1)} {slc(green#2.sg1.sva)#5.itm(2)} -attr xrf 44399 -attr oid 275 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {FRAME:not#9.itm(0)} -attr vt d
+load net {FRAME:not#9.itm(1)} -attr vt d
+load net {FRAME:not#9.itm(2)} -attr vt d
+load netBundle {FRAME:not#9.itm} 3 {FRAME:not#9.itm(0)} {FRAME:not#9.itm(1)} {FRAME:not#9.itm(2)} -attr xrf 44400 -attr oid 276 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {slc(green#2.sg1.sva)#6.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#6.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#6.itm} 3 {slc(green#2.sg1.sva)#6.itm(0)} {slc(green#2.sg1.sva)#6.itm(1)} {slc(green#2.sg1.sva)#6.itm(2)} -attr xrf 44401 -attr oid 277 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {FRAME:for:exs#35.itm(0)} -attr vt d
+load net {FRAME:for:exs#35.itm(1)} -attr vt d
+load net {FRAME:for:exs#35.itm(2)} -attr vt d
+load net {FRAME:for:exs#35.itm(3)} -attr vt d
+load net {FRAME:for:exs#35.itm(4)} -attr vt d
+load net {FRAME:for:exs#35.itm(5)} -attr vt d
+load net {FRAME:for:exs#35.itm(6)} -attr vt d
+load net {FRAME:for:exs#35.itm(7)} -attr vt d
+load net {FRAME:for:exs#35.itm(8)} -attr vt d
+load net {FRAME:for:exs#35.itm(9)} -attr vt d
+load net {FRAME:for:exs#35.itm(10)} -attr vt d
+load net {FRAME:for:exs#35.itm(11)} -attr vt d
+load net {FRAME:for:exs#35.itm(12)} -attr vt d
+load net {FRAME:for:exs#35.itm(13)} -attr vt d
+load net {FRAME:for:exs#35.itm(14)} -attr vt d
+load netBundle {FRAME:for:exs#35.itm} 15 {FRAME:for:exs#35.itm(0)} {FRAME:for:exs#35.itm(1)} {FRAME:for:exs#35.itm(2)} {FRAME:for:exs#35.itm(3)} {FRAME:for:exs#35.itm(4)} {FRAME:for:exs#35.itm(5)} {FRAME:for:exs#35.itm(6)} {FRAME:for:exs#35.itm(7)} {FRAME:for:exs#35.itm(8)} {FRAME:for:exs#35.itm(9)} {FRAME:for:exs#35.itm(10)} {FRAME:for:exs#35.itm(11)} {FRAME:for:exs#35.itm(12)} {FRAME:for:exs#35.itm(13)} {FRAME:for:exs#35.itm(14)} -attr xrf 44402 -attr oid 278 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {FRAME:for#1:mul#8.itm(0)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(1)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(2)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(3)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(4)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(5)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(6)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(7)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(8)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(9)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(10)} -attr vt d
+load netBundle {FRAME:for#1:mul#8.itm} 11 {FRAME:for#1:mul#8.itm(0)} {FRAME:for#1:mul#8.itm(1)} {FRAME:for#1:mul#8.itm(2)} {FRAME:for#1:mul#8.itm(3)} {FRAME:for#1:mul#8.itm(4)} {FRAME:for#1:mul#8.itm(5)} {FRAME:for#1:mul#8.itm(6)} {FRAME:for#1:mul#8.itm(7)} {FRAME:for#1:mul#8.itm(8)} {FRAME:for#1:mul#8.itm(9)} {FRAME:for#1:mul#8.itm(10)} -attr xrf 44403 -attr oid 279 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {regs.operator[]#35:mux.itm(0)} -attr vt d
+load net {regs.operator[]#35:mux.itm(1)} -attr vt d
+load net {regs.operator[]#35:mux.itm(2)} -attr vt d
+load net {regs.operator[]#35:mux.itm(3)} -attr vt d
+load net {regs.operator[]#35:mux.itm(4)} -attr vt d
+load net {regs.operator[]#35:mux.itm(5)} -attr vt d
+load net {regs.operator[]#35:mux.itm(6)} -attr vt d
+load net {regs.operator[]#35:mux.itm(7)} -attr vt d
+load net {regs.operator[]#35:mux.itm(8)} -attr vt d
+load net {regs.operator[]#35:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#35:mux.itm} 10 {regs.operator[]#35:mux.itm(0)} {regs.operator[]#35:mux.itm(1)} {regs.operator[]#35:mux.itm(2)} {regs.operator[]#35:mux.itm(3)} {regs.operator[]#35:mux.itm(4)} {regs.operator[]#35:mux.itm(5)} {regs.operator[]#35:mux.itm(6)} {regs.operator[]#35:mux.itm(7)} {regs.operator[]#35:mux.itm(8)} {regs.operator[]#35:mux.itm(9)} -attr xrf 44404 -attr oid 280 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm).itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm).itm} 10 {slc(regs.regs(2).lpi#1.dfm).itm(0)} {slc(regs.regs(2).lpi#1.dfm).itm(1)} {slc(regs.regs(2).lpi#1.dfm).itm(2)} {slc(regs.regs(2).lpi#1.dfm).itm(3)} {slc(regs.regs(2).lpi#1.dfm).itm(4)} {slc(regs.regs(2).lpi#1.dfm).itm(5)} {slc(regs.regs(2).lpi#1.dfm).itm(6)} {slc(regs.regs(2).lpi#1.dfm).itm(7)} {slc(regs.regs(2).lpi#1.dfm).itm(8)} {slc(regs.regs(2).lpi#1.dfm).itm(9)} -attr xrf 44405 -attr oid 281 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {slc(regs.regs(1).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva).itm} 10 {slc(regs.regs(1).sva).itm(0)} {slc(regs.regs(1).sva).itm(1)} {slc(regs.regs(1).sva).itm(2)} {slc(regs.regs(1).sva).itm(3)} {slc(regs.regs(1).sva).itm(4)} {slc(regs.regs(1).sva).itm(5)} {slc(regs.regs(1).sva).itm(6)} {slc(regs.regs(1).sva).itm(7)} {slc(regs.regs(1).sva).itm(8)} {slc(regs.regs(1).sva).itm(9)} -attr xrf 44406 -attr oid 282 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {slc(regs.regs(0).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva).itm} 10 {slc(regs.regs(0).sva).itm(0)} {slc(regs.regs(0).sva).itm(1)} {slc(regs.regs(0).sva).itm(2)} {slc(regs.regs(0).sva).itm(3)} {slc(regs.regs(0).sva).itm(4)} {slc(regs.regs(0).sva).itm(5)} {slc(regs.regs(0).sva).itm(6)} {slc(regs.regs(0).sva).itm(7)} {slc(regs.regs(0).sva).itm(8)} {slc(regs.regs(0).sva).itm(9)} -attr xrf 44407 -attr oid 283 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {FRAME:for#1:mul#2.itm(0)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(1)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(2)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(3)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(4)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(5)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(6)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(7)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(8)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(9)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(10)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(11)} -attr vt d
+load netBundle {FRAME:for#1:mul#2.itm} 12 {FRAME:for#1:mul#2.itm(0)} {FRAME:for#1:mul#2.itm(1)} {FRAME:for#1:mul#2.itm(2)} {FRAME:for#1:mul#2.itm(3)} {FRAME:for#1:mul#2.itm(4)} {FRAME:for#1:mul#2.itm(5)} {FRAME:for#1:mul#2.itm(6)} {FRAME:for#1:mul#2.itm(7)} {FRAME:for#1:mul#2.itm(8)} {FRAME:for#1:mul#2.itm(9)} {FRAME:for#1:mul#2.itm(10)} {FRAME:for#1:mul#2.itm(11)} -attr xrf 44408 -attr oid 284 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {regs.operator[]#29:mux.itm(0)} -attr vt d
+load net {regs.operator[]#29:mux.itm(1)} -attr vt d
+load net {regs.operator[]#29:mux.itm(2)} -attr vt d
+load net {regs.operator[]#29:mux.itm(3)} -attr vt d
+load net {regs.operator[]#29:mux.itm(4)} -attr vt d
+load net {regs.operator[]#29:mux.itm(5)} -attr vt d
+load net {regs.operator[]#29:mux.itm(6)} -attr vt d
+load net {regs.operator[]#29:mux.itm(7)} -attr vt d
+load net {regs.operator[]#29:mux.itm(8)} -attr vt d
+load net {regs.operator[]#29:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#29:mux.itm} 10 {regs.operator[]#29:mux.itm(0)} {regs.operator[]#29:mux.itm(1)} {regs.operator[]#29:mux.itm(2)} {regs.operator[]#29:mux.itm(3)} {regs.operator[]#29:mux.itm(4)} {regs.operator[]#29:mux.itm(5)} {regs.operator[]#29:mux.itm(6)} {regs.operator[]#29:mux.itm(7)} {regs.operator[]#29:mux.itm(8)} {regs.operator[]#29:mux.itm(9)} -attr xrf 44409 -attr oid 285 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm)#3.itm} 10 {slc(regs.regs(2).lpi#1.dfm)#3.itm(0)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(1)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(2)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(3)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(4)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(5)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(6)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(7)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(8)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(9)} -attr xrf 44410 -attr oid 286 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {slc(regs.regs(1).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#3.itm} 10 {slc(regs.regs(1).sva)#3.itm(0)} {slc(regs.regs(1).sva)#3.itm(1)} {slc(regs.regs(1).sva)#3.itm(2)} {slc(regs.regs(1).sva)#3.itm(3)} {slc(regs.regs(1).sva)#3.itm(4)} {slc(regs.regs(1).sva)#3.itm(5)} {slc(regs.regs(1).sva)#3.itm(6)} {slc(regs.regs(1).sva)#3.itm(7)} {slc(regs.regs(1).sva)#3.itm(8)} {slc(regs.regs(1).sva)#3.itm(9)} -attr xrf 44411 -attr oid 287 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {slc(regs.regs(0).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#3.itm} 10 {slc(regs.regs(0).sva)#3.itm(0)} {slc(regs.regs(0).sva)#3.itm(1)} {slc(regs.regs(0).sva)#3.itm(2)} {slc(regs.regs(0).sva)#3.itm(3)} {slc(regs.regs(0).sva)#3.itm(4)} {slc(regs.regs(0).sva)#3.itm(5)} {slc(regs.regs(0).sva)#3.itm(6)} {slc(regs.regs(0).sva)#3.itm(7)} {slc(regs.regs(0).sva)#3.itm(8)} {slc(regs.regs(0).sva)#3.itm(9)} -attr xrf 44412 -attr oid 288 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {conc#156.itm(0)} -attr vt d
+load net {conc#156.itm(1)} -attr vt d
+load netBundle {conc#156.itm} 2 {conc#156.itm(0)} {conc#156.itm(1)} -attr xrf 44413 -attr oid 289 -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {FRAME:for:exs#36.itm(0)} -attr vt d
+load net {FRAME:for:exs#36.itm(1)} -attr vt d
+load net {FRAME:for:exs#36.itm(2)} -attr vt d
+load net {FRAME:for:exs#36.itm(3)} -attr vt d
+load net {FRAME:for:exs#36.itm(4)} -attr vt d
+load net {FRAME:for:exs#36.itm(5)} -attr vt d
+load net {FRAME:for:exs#36.itm(6)} -attr vt d
+load net {FRAME:for:exs#36.itm(7)} -attr vt d
+load net {FRAME:for:exs#36.itm(8)} -attr vt d
+load net {FRAME:for:exs#36.itm(9)} -attr vt d
+load net {FRAME:for:exs#36.itm(10)} -attr vt d
+load net {FRAME:for:exs#36.itm(11)} -attr vt d
+load net {FRAME:for:exs#36.itm(12)} -attr vt d
+load net {FRAME:for:exs#36.itm(13)} -attr vt d
+load net {FRAME:for:exs#36.itm(14)} -attr vt d
+load netBundle {FRAME:for:exs#36.itm} 15 {FRAME:for:exs#36.itm(0)} {FRAME:for:exs#36.itm(1)} {FRAME:for:exs#36.itm(2)} {FRAME:for:exs#36.itm(3)} {FRAME:for:exs#36.itm(4)} {FRAME:for:exs#36.itm(5)} {FRAME:for:exs#36.itm(6)} {FRAME:for:exs#36.itm(7)} {FRAME:for:exs#36.itm(8)} {FRAME:for:exs#36.itm(9)} {FRAME:for:exs#36.itm(10)} {FRAME:for:exs#36.itm(11)} {FRAME:for:exs#36.itm(12)} {FRAME:for:exs#36.itm(13)} {FRAME:for:exs#36.itm(14)} -attr xrf 44414 -attr oid 290 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {FRAME:for#1:mul#7.itm(0)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(1)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(2)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(3)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(4)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(5)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(6)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(7)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(8)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(9)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(10)} -attr vt d
+load netBundle {FRAME:for#1:mul#7.itm} 11 {FRAME:for#1:mul#7.itm(0)} {FRAME:for#1:mul#7.itm(1)} {FRAME:for#1:mul#7.itm(2)} {FRAME:for#1:mul#7.itm(3)} {FRAME:for#1:mul#7.itm(4)} {FRAME:for#1:mul#7.itm(5)} {FRAME:for#1:mul#7.itm(6)} {FRAME:for#1:mul#7.itm(7)} {FRAME:for#1:mul#7.itm(8)} {FRAME:for#1:mul#7.itm(9)} {FRAME:for#1:mul#7.itm(10)} -attr xrf 44415 -attr oid 291 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {regs.operator[]#34:mux.itm(0)} -attr vt d
+load net {regs.operator[]#34:mux.itm(1)} -attr vt d
+load net {regs.operator[]#34:mux.itm(2)} -attr vt d
+load net {regs.operator[]#34:mux.itm(3)} -attr vt d
+load net {regs.operator[]#34:mux.itm(4)} -attr vt d
+load net {regs.operator[]#34:mux.itm(5)} -attr vt d
+load net {regs.operator[]#34:mux.itm(6)} -attr vt d
+load net {regs.operator[]#34:mux.itm(7)} -attr vt d
+load net {regs.operator[]#34:mux.itm(8)} -attr vt d
+load net {regs.operator[]#34:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#34:mux.itm} 10 {regs.operator[]#34:mux.itm(0)} {regs.operator[]#34:mux.itm(1)} {regs.operator[]#34:mux.itm(2)} {regs.operator[]#34:mux.itm(3)} {regs.operator[]#34:mux.itm(4)} {regs.operator[]#34:mux.itm(5)} {regs.operator[]#34:mux.itm(6)} {regs.operator[]#34:mux.itm(7)} {regs.operator[]#34:mux.itm(8)} {regs.operator[]#34:mux.itm(9)} -attr xrf 44416 -attr oid 292 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm)#1.itm} 10 {slc(regs.regs(2).lpi#1.dfm)#1.itm(0)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(1)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(2)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(3)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(4)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(5)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(6)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(7)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(8)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(9)} -attr xrf 44417 -attr oid 293 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {slc(regs.regs(1).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#1.itm} 10 {slc(regs.regs(1).sva)#1.itm(0)} {slc(regs.regs(1).sva)#1.itm(1)} {slc(regs.regs(1).sva)#1.itm(2)} {slc(regs.regs(1).sva)#1.itm(3)} {slc(regs.regs(1).sva)#1.itm(4)} {slc(regs.regs(1).sva)#1.itm(5)} {slc(regs.regs(1).sva)#1.itm(6)} {slc(regs.regs(1).sva)#1.itm(7)} {slc(regs.regs(1).sva)#1.itm(8)} {slc(regs.regs(1).sva)#1.itm(9)} -attr xrf 44418 -attr oid 294 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {slc(regs.regs(0).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#1.itm} 10 {slc(regs.regs(0).sva)#1.itm(0)} {slc(regs.regs(0).sva)#1.itm(1)} {slc(regs.regs(0).sva)#1.itm(2)} {slc(regs.regs(0).sva)#1.itm(3)} {slc(regs.regs(0).sva)#1.itm(4)} {slc(regs.regs(0).sva)#1.itm(5)} {slc(regs.regs(0).sva)#1.itm(6)} {slc(regs.regs(0).sva)#1.itm(7)} {slc(regs.regs(0).sva)#1.itm(8)} {slc(regs.regs(0).sva)#1.itm(9)} -attr xrf 44419 -attr oid 295 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {FRAME:for#1:mul#1.itm(0)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(1)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(2)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(3)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(4)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(5)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(6)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(7)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(8)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(9)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(10)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(11)} -attr vt d
+load netBundle {FRAME:for#1:mul#1.itm} 12 {FRAME:for#1:mul#1.itm(0)} {FRAME:for#1:mul#1.itm(1)} {FRAME:for#1:mul#1.itm(2)} {FRAME:for#1:mul#1.itm(3)} {FRAME:for#1:mul#1.itm(4)} {FRAME:for#1:mul#1.itm(5)} {FRAME:for#1:mul#1.itm(6)} {FRAME:for#1:mul#1.itm(7)} {FRAME:for#1:mul#1.itm(8)} {FRAME:for#1:mul#1.itm(9)} {FRAME:for#1:mul#1.itm(10)} {FRAME:for#1:mul#1.itm(11)} -attr xrf 44420 -attr oid 296 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {regs.operator[]#28:mux.itm(0)} -attr vt d
+load net {regs.operator[]#28:mux.itm(1)} -attr vt d
+load net {regs.operator[]#28:mux.itm(2)} -attr vt d
+load net {regs.operator[]#28:mux.itm(3)} -attr vt d
+load net {regs.operator[]#28:mux.itm(4)} -attr vt d
+load net {regs.operator[]#28:mux.itm(5)} -attr vt d
+load net {regs.operator[]#28:mux.itm(6)} -attr vt d
+load net {regs.operator[]#28:mux.itm(7)} -attr vt d
+load net {regs.operator[]#28:mux.itm(8)} -attr vt d
+load net {regs.operator[]#28:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#28:mux.itm} 10 {regs.operator[]#28:mux.itm(0)} {regs.operator[]#28:mux.itm(1)} {regs.operator[]#28:mux.itm(2)} {regs.operator[]#28:mux.itm(3)} {regs.operator[]#28:mux.itm(4)} {regs.operator[]#28:mux.itm(5)} {regs.operator[]#28:mux.itm(6)} {regs.operator[]#28:mux.itm(7)} {regs.operator[]#28:mux.itm(8)} {regs.operator[]#28:mux.itm(9)} -attr xrf 44421 -attr oid 297 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm)#4.itm} 10 {slc(regs.regs(2).lpi#1.dfm)#4.itm(0)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(1)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(2)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(3)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(4)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(5)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(6)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(7)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(8)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(9)} -attr xrf 44422 -attr oid 298 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {slc(regs.regs(1).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#4.itm} 10 {slc(regs.regs(1).sva)#4.itm(0)} {slc(regs.regs(1).sva)#4.itm(1)} {slc(regs.regs(1).sva)#4.itm(2)} {slc(regs.regs(1).sva)#4.itm(3)} {slc(regs.regs(1).sva)#4.itm(4)} {slc(regs.regs(1).sva)#4.itm(5)} {slc(regs.regs(1).sva)#4.itm(6)} {slc(regs.regs(1).sva)#4.itm(7)} {slc(regs.regs(1).sva)#4.itm(8)} {slc(regs.regs(1).sva)#4.itm(9)} -attr xrf 44423 -attr oid 299 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {slc(regs.regs(0).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#4.itm} 10 {slc(regs.regs(0).sva)#4.itm(0)} {slc(regs.regs(0).sva)#4.itm(1)} {slc(regs.regs(0).sva)#4.itm(2)} {slc(regs.regs(0).sva)#4.itm(3)} {slc(regs.regs(0).sva)#4.itm(4)} {slc(regs.regs(0).sva)#4.itm(5)} {slc(regs.regs(0).sva)#4.itm(6)} {slc(regs.regs(0).sva)#4.itm(7)} {slc(regs.regs(0).sva)#4.itm(8)} {slc(regs.regs(0).sva)#4.itm(9)} -attr xrf 44424 -attr oid 300 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {conc#157.itm(0)} -attr vt d
+load net {conc#157.itm(1)} -attr vt d
+load netBundle {conc#157.itm} 2 {conc#157.itm(0)} {conc#157.itm(1)} -attr xrf 44425 -attr oid 301 -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {FRAME:for:exs#31.itm(0)} -attr vt d
+load net {FRAME:for:exs#31.itm(1)} -attr vt d
+load net {FRAME:for:exs#31.itm(2)} -attr vt d
+load net {FRAME:for:exs#31.itm(3)} -attr vt d
+load net {FRAME:for:exs#31.itm(4)} -attr vt d
+load net {FRAME:for:exs#31.itm(5)} -attr vt d
+load net {FRAME:for:exs#31.itm(6)} -attr vt d
+load net {FRAME:for:exs#31.itm(7)} -attr vt d
+load net {FRAME:for:exs#31.itm(8)} -attr vt d
+load net {FRAME:for:exs#31.itm(9)} -attr vt d
+load net {FRAME:for:exs#31.itm(10)} -attr vt d
+load net {FRAME:for:exs#31.itm(11)} -attr vt d
+load net {FRAME:for:exs#31.itm(12)} -attr vt d
+load net {FRAME:for:exs#31.itm(13)} -attr vt d
+load net {FRAME:for:exs#31.itm(14)} -attr vt d
+load netBundle {FRAME:for:exs#31.itm} 15 {FRAME:for:exs#31.itm(0)} {FRAME:for:exs#31.itm(1)} {FRAME:for:exs#31.itm(2)} {FRAME:for:exs#31.itm(3)} {FRAME:for:exs#31.itm(4)} {FRAME:for:exs#31.itm(5)} {FRAME:for:exs#31.itm(6)} {FRAME:for:exs#31.itm(7)} {FRAME:for:exs#31.itm(8)} {FRAME:for:exs#31.itm(9)} {FRAME:for:exs#31.itm(10)} {FRAME:for:exs#31.itm(11)} {FRAME:for:exs#31.itm(12)} {FRAME:for:exs#31.itm(13)} {FRAME:for:exs#31.itm(14)} -attr xrf 44426 -attr oid 302 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {FRAME:for#1:mul#6.itm(0)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(1)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(2)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(3)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(4)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(5)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(6)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(7)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(8)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(9)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(10)} -attr vt d
+load netBundle {FRAME:for#1:mul#6.itm} 11 {FRAME:for#1:mul#6.itm(0)} {FRAME:for#1:mul#6.itm(1)} {FRAME:for#1:mul#6.itm(2)} {FRAME:for#1:mul#6.itm(3)} {FRAME:for#1:mul#6.itm(4)} {FRAME:for#1:mul#6.itm(5)} {FRAME:for#1:mul#6.itm(6)} {FRAME:for#1:mul#6.itm(7)} {FRAME:for#1:mul#6.itm(8)} {FRAME:for#1:mul#6.itm(9)} {FRAME:for#1:mul#6.itm(10)} -attr xrf 44427 -attr oid 303 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {regs.operator[]#33:mux.itm(0)} -attr vt d
+load net {regs.operator[]#33:mux.itm(1)} -attr vt d
+load net {regs.operator[]#33:mux.itm(2)} -attr vt d
+load net {regs.operator[]#33:mux.itm(3)} -attr vt d
+load net {regs.operator[]#33:mux.itm(4)} -attr vt d
+load net {regs.operator[]#33:mux.itm(5)} -attr vt d
+load net {regs.operator[]#33:mux.itm(6)} -attr vt d
+load net {regs.operator[]#33:mux.itm(7)} -attr vt d
+load net {regs.operator[]#33:mux.itm(8)} -attr vt d
+load net {regs.operator[]#33:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#33:mux.itm} 10 {regs.operator[]#33:mux.itm(0)} {regs.operator[]#33:mux.itm(1)} {regs.operator[]#33:mux.itm(2)} {regs.operator[]#33:mux.itm(3)} {regs.operator[]#33:mux.itm(4)} {regs.operator[]#33:mux.itm(5)} {regs.operator[]#33:mux.itm(6)} {regs.operator[]#33:mux.itm(7)} {regs.operator[]#33:mux.itm(8)} {regs.operator[]#33:mux.itm(9)} -attr xrf 44428 -attr oid 304 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm)#2.itm} 10 {slc(regs.regs(2).lpi#1.dfm)#2.itm(0)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(1)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(2)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(3)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(4)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(5)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(6)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(7)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(8)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(9)} -attr xrf 44429 -attr oid 305 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {slc(regs.regs(1).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#2.itm} 10 {slc(regs.regs(1).sva)#2.itm(0)} {slc(regs.regs(1).sva)#2.itm(1)} {slc(regs.regs(1).sva)#2.itm(2)} {slc(regs.regs(1).sva)#2.itm(3)} {slc(regs.regs(1).sva)#2.itm(4)} {slc(regs.regs(1).sva)#2.itm(5)} {slc(regs.regs(1).sva)#2.itm(6)} {slc(regs.regs(1).sva)#2.itm(7)} {slc(regs.regs(1).sva)#2.itm(8)} {slc(regs.regs(1).sva)#2.itm(9)} -attr xrf 44430 -attr oid 306 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {slc(regs.regs(0).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#2.itm} 10 {slc(regs.regs(0).sva)#2.itm(0)} {slc(regs.regs(0).sva)#2.itm(1)} {slc(regs.regs(0).sva)#2.itm(2)} {slc(regs.regs(0).sva)#2.itm(3)} {slc(regs.regs(0).sva)#2.itm(4)} {slc(regs.regs(0).sva)#2.itm(5)} {slc(regs.regs(0).sva)#2.itm(6)} {slc(regs.regs(0).sva)#2.itm(7)} {slc(regs.regs(0).sva)#2.itm(8)} {slc(regs.regs(0).sva)#2.itm(9)} -attr xrf 44431 -attr oid 307 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {FRAME:for#1:mul.itm(0)} -attr vt d
+load net {FRAME:for#1:mul.itm(1)} -attr vt d
+load net {FRAME:for#1:mul.itm(2)} -attr vt d
+load net {FRAME:for#1:mul.itm(3)} -attr vt d
+load net {FRAME:for#1:mul.itm(4)} -attr vt d
+load net {FRAME:for#1:mul.itm(5)} -attr vt d
+load net {FRAME:for#1:mul.itm(6)} -attr vt d
+load net {FRAME:for#1:mul.itm(7)} -attr vt d
+load net {FRAME:for#1:mul.itm(8)} -attr vt d
+load net {FRAME:for#1:mul.itm(9)} -attr vt d
+load net {FRAME:for#1:mul.itm(10)} -attr vt d
+load net {FRAME:for#1:mul.itm(11)} -attr vt d
+load netBundle {FRAME:for#1:mul.itm} 12 {FRAME:for#1:mul.itm(0)} {FRAME:for#1:mul.itm(1)} {FRAME:for#1:mul.itm(2)} {FRAME:for#1:mul.itm(3)} {FRAME:for#1:mul.itm(4)} {FRAME:for#1:mul.itm(5)} {FRAME:for#1:mul.itm(6)} {FRAME:for#1:mul.itm(7)} {FRAME:for#1:mul.itm(8)} {FRAME:for#1:mul.itm(9)} {FRAME:for#1:mul.itm(10)} {FRAME:for#1:mul.itm(11)} -attr xrf 44432 -attr oid 308 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {regs.operator[]#27:mux.itm(0)} -attr vt d
+load net {regs.operator[]#27:mux.itm(1)} -attr vt d
+load net {regs.operator[]#27:mux.itm(2)} -attr vt d
+load net {regs.operator[]#27:mux.itm(3)} -attr vt d
+load net {regs.operator[]#27:mux.itm(4)} -attr vt d
+load net {regs.operator[]#27:mux.itm(5)} -attr vt d
+load net {regs.operator[]#27:mux.itm(6)} -attr vt d
+load net {regs.operator[]#27:mux.itm(7)} -attr vt d
+load net {regs.operator[]#27:mux.itm(8)} -attr vt d
+load net {regs.operator[]#27:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#27:mux.itm} 10 {regs.operator[]#27:mux.itm(0)} {regs.operator[]#27:mux.itm(1)} {regs.operator[]#27:mux.itm(2)} {regs.operator[]#27:mux.itm(3)} {regs.operator[]#27:mux.itm(4)} {regs.operator[]#27:mux.itm(5)} {regs.operator[]#27:mux.itm(6)} {regs.operator[]#27:mux.itm(7)} {regs.operator[]#27:mux.itm(8)} {regs.operator[]#27:mux.itm(9)} -attr xrf 44433 -attr oid 309 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm)#5.itm} 10 {slc(regs.regs(2).lpi#1.dfm)#5.itm(0)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(1)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(2)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(3)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(4)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(5)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(6)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(7)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(8)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(9)} -attr xrf 44434 -attr oid 310 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {slc(regs.regs(1).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#5.itm} 10 {slc(regs.regs(1).sva)#5.itm(0)} {slc(regs.regs(1).sva)#5.itm(1)} {slc(regs.regs(1).sva)#5.itm(2)} {slc(regs.regs(1).sva)#5.itm(3)} {slc(regs.regs(1).sva)#5.itm(4)} {slc(regs.regs(1).sva)#5.itm(5)} {slc(regs.regs(1).sva)#5.itm(6)} {slc(regs.regs(1).sva)#5.itm(7)} {slc(regs.regs(1).sva)#5.itm(8)} {slc(regs.regs(1).sva)#5.itm(9)} -attr xrf 44435 -attr oid 311 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {slc(regs.regs(0).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#5.itm} 10 {slc(regs.regs(0).sva)#5.itm(0)} {slc(regs.regs(0).sva)#5.itm(1)} {slc(regs.regs(0).sva)#5.itm(2)} {slc(regs.regs(0).sva)#5.itm(3)} {slc(regs.regs(0).sva)#5.itm(4)} {slc(regs.regs(0).sva)#5.itm(5)} {slc(regs.regs(0).sva)#5.itm(6)} {slc(regs.regs(0).sva)#5.itm(7)} {slc(regs.regs(0).sva)#5.itm(8)} {slc(regs.regs(0).sva)#5.itm(9)} -attr xrf 44436 -attr oid 312 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {conc#158.itm(0)} -attr vt d
+load net {conc#158.itm(1)} -attr vt d
+load netBundle {conc#158.itm} 2 {conc#158.itm(0)} {conc#158.itm(1)} -attr xrf 44437 -attr oid 313 -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {FRAME:for:exs#37.itm(0)} -attr vt d
+load net {FRAME:for:exs#37.itm(1)} -attr vt d
+load net {FRAME:for:exs#37.itm(2)} -attr vt d
+load net {FRAME:for:exs#37.itm(3)} -attr vt d
+load net {FRAME:for:exs#37.itm(4)} -attr vt d
+load net {FRAME:for:exs#37.itm(5)} -attr vt d
+load net {FRAME:for:exs#37.itm(6)} -attr vt d
+load net {FRAME:for:exs#37.itm(7)} -attr vt d
+load net {FRAME:for:exs#37.itm(8)} -attr vt d
+load net {FRAME:for:exs#37.itm(9)} -attr vt d
+load net {FRAME:for:exs#37.itm(10)} -attr vt d
+load net {FRAME:for:exs#37.itm(11)} -attr vt d
+load net {FRAME:for:exs#37.itm(12)} -attr vt d
+load net {FRAME:for:exs#37.itm(13)} -attr vt d
+load net {FRAME:for:exs#37.itm(14)} -attr vt d
+load net {FRAME:for:exs#37.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#37.itm} 16 {FRAME:for:exs#37.itm(0)} {FRAME:for:exs#37.itm(1)} {FRAME:for:exs#37.itm(2)} {FRAME:for:exs#37.itm(3)} {FRAME:for:exs#37.itm(4)} {FRAME:for:exs#37.itm(5)} {FRAME:for:exs#37.itm(6)} {FRAME:for:exs#37.itm(7)} {FRAME:for:exs#37.itm(8)} {FRAME:for:exs#37.itm(9)} {FRAME:for:exs#37.itm(10)} {FRAME:for:exs#37.itm(11)} {FRAME:for:exs#37.itm(12)} {FRAME:for:exs#37.itm(13)} {FRAME:for:exs#37.itm(14)} {FRAME:for:exs#37.itm(15)} -attr xrf 44438 -attr oid 314 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {FRAME:for:exs#39.itm(0)} -attr vt d
+load net {FRAME:for:exs#39.itm(1)} -attr vt d
+load net {FRAME:for:exs#39.itm(2)} -attr vt d
+load net {FRAME:for:exs#39.itm(3)} -attr vt d
+load net {FRAME:for:exs#39.itm(4)} -attr vt d
+load net {FRAME:for:exs#39.itm(5)} -attr vt d
+load net {FRAME:for:exs#39.itm(6)} -attr vt d
+load net {FRAME:for:exs#39.itm(7)} -attr vt d
+load net {FRAME:for:exs#39.itm(8)} -attr vt d
+load net {FRAME:for:exs#39.itm(9)} -attr vt d
+load net {FRAME:for:exs#39.itm(10)} -attr vt d
+load net {FRAME:for:exs#39.itm(11)} -attr vt d
+load net {FRAME:for:exs#39.itm(12)} -attr vt d
+load net {FRAME:for:exs#39.itm(13)} -attr vt d
+load net {FRAME:for:exs#39.itm(14)} -attr vt d
+load net {FRAME:for:exs#39.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#39.itm} 16 {FRAME:for:exs#39.itm(0)} {FRAME:for:exs#39.itm(1)} {FRAME:for:exs#39.itm(2)} {FRAME:for:exs#39.itm(3)} {FRAME:for:exs#39.itm(4)} {FRAME:for:exs#39.itm(5)} {FRAME:for:exs#39.itm(6)} {FRAME:for:exs#39.itm(7)} {FRAME:for:exs#39.itm(8)} {FRAME:for:exs#39.itm(9)} {FRAME:for:exs#39.itm(10)} {FRAME:for:exs#39.itm(11)} {FRAME:for:exs#39.itm(12)} {FRAME:for:exs#39.itm(13)} {FRAME:for:exs#39.itm(14)} {FRAME:for:exs#39.itm(15)} -attr xrf 44439 -attr oid 315 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {FRAME:for:exs#41.itm(0)} -attr vt d
+load net {FRAME:for:exs#41.itm(1)} -attr vt d
+load net {FRAME:for:exs#41.itm(2)} -attr vt d
+load net {FRAME:for:exs#41.itm(3)} -attr vt d
+load net {FRAME:for:exs#41.itm(4)} -attr vt d
+load net {FRAME:for:exs#41.itm(5)} -attr vt d
+load net {FRAME:for:exs#41.itm(6)} -attr vt d
+load net {FRAME:for:exs#41.itm(7)} -attr vt d
+load net {FRAME:for:exs#41.itm(8)} -attr vt d
+load net {FRAME:for:exs#41.itm(9)} -attr vt d
+load net {FRAME:for:exs#41.itm(10)} -attr vt d
+load net {FRAME:for:exs#41.itm(11)} -attr vt d
+load net {FRAME:for:exs#41.itm(12)} -attr vt d
+load net {FRAME:for:exs#41.itm(13)} -attr vt d
+load net {FRAME:for:exs#41.itm(14)} -attr vt d
+load net {FRAME:for:exs#41.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#41.itm} 16 {FRAME:for:exs#41.itm(0)} {FRAME:for:exs#41.itm(1)} {FRAME:for:exs#41.itm(2)} {FRAME:for:exs#41.itm(3)} {FRAME:for:exs#41.itm(4)} {FRAME:for:exs#41.itm(5)} {FRAME:for:exs#41.itm(6)} {FRAME:for:exs#41.itm(7)} {FRAME:for:exs#41.itm(8)} {FRAME:for:exs#41.itm(9)} {FRAME:for:exs#41.itm(10)} {FRAME:for:exs#41.itm(11)} {FRAME:for:exs#41.itm(12)} {FRAME:for:exs#41.itm(13)} {FRAME:for:exs#41.itm(14)} {FRAME:for:exs#41.itm(15)} -attr xrf 44440 -attr oid 316 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {FRAME:for:exs#38.itm(0)} -attr vt d
+load net {FRAME:for:exs#38.itm(1)} -attr vt d
+load net {FRAME:for:exs#38.itm(2)} -attr vt d
+load net {FRAME:for:exs#38.itm(3)} -attr vt d
+load net {FRAME:for:exs#38.itm(4)} -attr vt d
+load net {FRAME:for:exs#38.itm(5)} -attr vt d
+load net {FRAME:for:exs#38.itm(6)} -attr vt d
+load net {FRAME:for:exs#38.itm(7)} -attr vt d
+load net {FRAME:for:exs#38.itm(8)} -attr vt d
+load net {FRAME:for:exs#38.itm(9)} -attr vt d
+load net {FRAME:for:exs#38.itm(10)} -attr vt d
+load net {FRAME:for:exs#38.itm(11)} -attr vt d
+load net {FRAME:for:exs#38.itm(12)} -attr vt d
+load net {FRAME:for:exs#38.itm(13)} -attr vt d
+load net {FRAME:for:exs#38.itm(14)} -attr vt d
+load net {FRAME:for:exs#38.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#38.itm} 16 {FRAME:for:exs#38.itm(0)} {FRAME:for:exs#38.itm(1)} {FRAME:for:exs#38.itm(2)} {FRAME:for:exs#38.itm(3)} {FRAME:for:exs#38.itm(4)} {FRAME:for:exs#38.itm(5)} {FRAME:for:exs#38.itm(6)} {FRAME:for:exs#38.itm(7)} {FRAME:for:exs#38.itm(8)} {FRAME:for:exs#38.itm(9)} {FRAME:for:exs#38.itm(10)} {FRAME:for:exs#38.itm(11)} {FRAME:for:exs#38.itm(12)} {FRAME:for:exs#38.itm(13)} {FRAME:for:exs#38.itm(14)} {FRAME:for:exs#38.itm(15)} -attr xrf 44441 -attr oid 317 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {FRAME:for:exs#40.itm(0)} -attr vt d
+load net {FRAME:for:exs#40.itm(1)} -attr vt d
+load net {FRAME:for:exs#40.itm(2)} -attr vt d
+load net {FRAME:for:exs#40.itm(3)} -attr vt d
+load net {FRAME:for:exs#40.itm(4)} -attr vt d
+load net {FRAME:for:exs#40.itm(5)} -attr vt d
+load net {FRAME:for:exs#40.itm(6)} -attr vt d
+load net {FRAME:for:exs#40.itm(7)} -attr vt d
+load net {FRAME:for:exs#40.itm(8)} -attr vt d
+load net {FRAME:for:exs#40.itm(9)} -attr vt d
+load net {FRAME:for:exs#40.itm(10)} -attr vt d
+load net {FRAME:for:exs#40.itm(11)} -attr vt d
+load net {FRAME:for:exs#40.itm(12)} -attr vt d
+load net {FRAME:for:exs#40.itm(13)} -attr vt d
+load net {FRAME:for:exs#40.itm(14)} -attr vt d
+load net {FRAME:for:exs#40.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#40.itm} 16 {FRAME:for:exs#40.itm(0)} {FRAME:for:exs#40.itm(1)} {FRAME:for:exs#40.itm(2)} {FRAME:for:exs#40.itm(3)} {FRAME:for:exs#40.itm(4)} {FRAME:for:exs#40.itm(5)} {FRAME:for:exs#40.itm(6)} {FRAME:for:exs#40.itm(7)} {FRAME:for:exs#40.itm(8)} {FRAME:for:exs#40.itm(9)} {FRAME:for:exs#40.itm(10)} {FRAME:for:exs#40.itm(11)} {FRAME:for:exs#40.itm(12)} {FRAME:for:exs#40.itm(13)} {FRAME:for:exs#40.itm(14)} {FRAME:for:exs#40.itm(15)} -attr xrf 44442 -attr oid 318 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {FRAME:for:exs#33.itm(0)} -attr vt d
+load net {FRAME:for:exs#33.itm(1)} -attr vt d
+load net {FRAME:for:exs#33.itm(2)} -attr vt d
+load net {FRAME:for:exs#33.itm(3)} -attr vt d
+load net {FRAME:for:exs#33.itm(4)} -attr vt d
+load net {FRAME:for:exs#33.itm(5)} -attr vt d
+load net {FRAME:for:exs#33.itm(6)} -attr vt d
+load net {FRAME:for:exs#33.itm(7)} -attr vt d
+load net {FRAME:for:exs#33.itm(8)} -attr vt d
+load net {FRAME:for:exs#33.itm(9)} -attr vt d
+load net {FRAME:for:exs#33.itm(10)} -attr vt d
+load net {FRAME:for:exs#33.itm(11)} -attr vt d
+load net {FRAME:for:exs#33.itm(12)} -attr vt d
+load net {FRAME:for:exs#33.itm(13)} -attr vt d
+load net {FRAME:for:exs#33.itm(14)} -attr vt d
+load net {FRAME:for:exs#33.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#33.itm} 16 {FRAME:for:exs#33.itm(0)} {FRAME:for:exs#33.itm(1)} {FRAME:for:exs#33.itm(2)} {FRAME:for:exs#33.itm(3)} {FRAME:for:exs#33.itm(4)} {FRAME:for:exs#33.itm(5)} {FRAME:for:exs#33.itm(6)} {FRAME:for:exs#33.itm(7)} {FRAME:for:exs#33.itm(8)} {FRAME:for:exs#33.itm(9)} {FRAME:for:exs#33.itm(10)} {FRAME:for:exs#33.itm(11)} {FRAME:for:exs#33.itm(12)} {FRAME:for:exs#33.itm(13)} {FRAME:for:exs#33.itm(14)} {FRAME:for:exs#33.itm(15)} -attr xrf 44443 -attr oid 319 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {FRAME:for:exs#26.itm(0)} -attr vt d
+load net {FRAME:for:exs#26.itm(1)} -attr vt d
+load netBundle {FRAME:for:exs#26.itm} 2 {FRAME:for:exs#26.itm(0)} {FRAME:for:exs#26.itm(1)} -attr xrf 44444 -attr oid 320 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#26.itm}
+load net {clk} -attr xrf 44445 -attr oid 321
+load net {clk} -port {clk} -attr xrf 44446 -attr oid 322
+load net {en} -attr xrf 44447 -attr oid 323
+load net {en} -port {en} -attr xrf 44448 -attr oid 324
+load net {arst_n} -attr xrf 44449 -attr oid 325
+load net {arst_n} -port {arst_n} -attr xrf 44450 -attr oid 326
+load net {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 44451 -attr oid 327 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(0)} -port {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -port {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -port {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -port {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -port {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -port {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -port {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -port {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -port {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -port {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -port {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -port {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -port {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -port {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -port {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -port {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -port {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -port {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -port {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -port {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -port {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -port {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -port {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -port {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -port {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -port {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -port {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -port {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -port {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -port {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -port {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -port {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -port {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -port {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -port {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -port {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -port {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -port {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -port {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -port {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -port {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -port {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -port {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -port {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -port {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -port {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -port {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -port {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -port {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -port {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -port {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -port {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -port {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -port {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -port {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -port {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -port {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -port {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -port {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -port {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -port {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -port {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -port {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -port {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -port {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -port {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -port {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -port {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -port {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -port {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -port {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -port {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -port {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -port {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -port {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -port {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -port {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -port {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -port {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -port {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -port {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -port {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -port {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -port {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -port {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -port {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -port {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -port {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -port {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -port {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 44452 -attr oid 328 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d} 30 {vout:rsc:mgc_out_stdreg.d(0)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(29)} -attr xrf 44453 -attr oid 329 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -port {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -port {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -port {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -port {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -port {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -port {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -port {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -port {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -port {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -port {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -port {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -port {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -port {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -port {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -port {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -port {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -port {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -port {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -port {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -port {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -port {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -port {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -port {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -port {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -port {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -port {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -port {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -port {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -port {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -port {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:acc#38" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 44454 -attr oid 330 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {FRAME:acc#37.itm#1(0)} -pin  "FRAME:acc#38" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(1)} -pin  "FRAME:acc#38" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(2)} -pin  "FRAME:acc#38" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(3)} -pin  "FRAME:acc#38" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(4)} -pin  "FRAME:acc#38" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:slc(acc.imod#9)#4.itm#1} -pin  "FRAME:acc#38" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {PWR} -pin  "FRAME:acc#38" {B(1)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:acc#38" {B(2)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:acc#38" {B(3)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {PWR} -pin  "FRAME:acc#38" {B(4)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {FRAME:acc#38.itm(0)} -pin  "FRAME:acc#38" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(1)} -pin  "FRAME:acc#38" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(2)} -pin  "FRAME:acc#38" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(3)} -pin  "FRAME:acc#38" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(4)} -pin  "FRAME:acc#38" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load inst "FRAME:acc#39" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 44455 -attr oid 331 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {red:slc(red#2.sg1).itm#1(0)} -pin  "FRAME:acc#39" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(1)} -pin  "FRAME:acc#39" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(2)} -pin  "FRAME:acc#39" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(3)} -pin  "FRAME:acc#39" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(4)} -pin  "FRAME:acc#39" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(5)} -pin  "FRAME:acc#39" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {FRAME:acc#38.itm(0)} -pin  "FRAME:acc#39" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(1)} -pin  "FRAME:acc#39" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(2)} -pin  "FRAME:acc#39" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(3)} -pin  "FRAME:acc#39" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(4)} -pin  "FRAME:acc#39" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#39.itm(0)} -pin  "FRAME:acc#39" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(1)} -pin  "FRAME:acc#39" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(2)} -pin  "FRAME:acc#39" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(3)} -pin  "FRAME:acc#39" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(4)} -pin  "FRAME:acc#39" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(5)} -pin  "FRAME:acc#39" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(6)} -pin  "FRAME:acc#39" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(7)} -pin  "FRAME:acc#39" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load inst "FRAME:acc#40" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 44456 -attr oid 332 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul#1.itm#1(0)} -pin  "FRAME:acc#40" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(1)} -pin  "FRAME:acc#40" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(2)} -pin  "FRAME:acc#40" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(3)} -pin  "FRAME:acc#40" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(4)} -pin  "FRAME:acc#40" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(5)} -pin  "FRAME:acc#40" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(6)} -pin  "FRAME:acc#40" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(7)} -pin  "FRAME:acc#40" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(8)} -pin  "FRAME:acc#40" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:acc#39.itm(0)} -pin  "FRAME:acc#40" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(1)} -pin  "FRAME:acc#40" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(2)} -pin  "FRAME:acc#40" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(3)} -pin  "FRAME:acc#40" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(4)} -pin  "FRAME:acc#40" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(5)} -pin  "FRAME:acc#40" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(6)} -pin  "FRAME:acc#40" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(7)} -pin  "FRAME:acc#40" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#40.itm(0)} -pin  "FRAME:acc#40" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(1)} -pin  "FRAME:acc#40" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(2)} -pin  "FRAME:acc#40" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(3)} -pin  "FRAME:acc#40" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(4)} -pin  "FRAME:acc#40" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(5)} -pin  "FRAME:acc#40" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(6)} -pin  "FRAME:acc#40" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(7)} -pin  "FRAME:acc#40" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(8)} -pin  "FRAME:acc#40" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(9)} -pin  "FRAME:acc#40" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load inst "FRAME:acc#2" "add(10,-1,10,-1,10)" "INTERFACE" -attr xrf 44457 -attr oid 333 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2} -attr area 11.241230 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,10)"
+load net {FRAME:acc#41.itm#3(0)} -pin  "FRAME:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#3(1)} -pin  "FRAME:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#3(2)} -pin  "FRAME:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#3(3)} -pin  "FRAME:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#3(4)} -pin  "FRAME:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#3(5)} -pin  "FRAME:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#1.sg1(0)} -pin  "FRAME:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#1.sg1(1)} -pin  "FRAME:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#1.sg2(0)} -pin  "FRAME:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#1.sg2(1)} -pin  "FRAME:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#40.itm(0)} -pin  "FRAME:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(1)} -pin  "FRAME:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(2)} -pin  "FRAME:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(3)} -pin  "FRAME:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(4)} -pin  "FRAME:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(5)} -pin  "FRAME:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(6)} -pin  "FRAME:acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(7)} -pin  "FRAME:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(8)} -pin  "FRAME:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(9)} -pin  "FRAME:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#2.itm(0)} -pin  "FRAME:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(1)} -pin  "FRAME:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(2)} -pin  "FRAME:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(3)} -pin  "FRAME:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(4)} -pin  "FRAME:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(5)} -pin  "FRAME:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(6)} -pin  "FRAME:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(7)} -pin  "FRAME:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(8)} -pin  "FRAME:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(9)} -pin  "FRAME:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load inst "FRAME:or" "or(2,10)" "INTERFACE" -attr xrf 44458 -attr oid 334 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or} -attr area 7.298324 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2)"
+load net {FRAME:acc#2.itm(0)} -pin  "FRAME:or" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(1)} -pin  "FRAME:or" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(2)} -pin  "FRAME:or" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(3)} -pin  "FRAME:or" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(4)} -pin  "FRAME:or" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(5)} -pin  "FRAME:or" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(6)} -pin  "FRAME:or" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(7)} -pin  "FRAME:or" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(8)} -pin  "FRAME:or" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(9)} -pin  "FRAME:or" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#3.psp.sva(10)} -pin  "FRAME:or" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {FRAME:acc#3.psp.sva(11)} -pin  "FRAME:or" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(2)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(3)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(4)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(5)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(6)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(7)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(8)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(9)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {FRAME:or.itm(0)} -pin  "FRAME:or" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(1)} -pin  "FRAME:or" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(2)} -pin  "FRAME:or" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(3)} -pin  "FRAME:or" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(4)} -pin  "FRAME:or" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(5)} -pin  "FRAME:or" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(6)} -pin  "FRAME:or" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(7)} -pin  "FRAME:or" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(8)} -pin  "FRAME:or" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(9)} -pin  "FRAME:or" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load inst "FRAME:or#3" "or(2,6)" "INTERFACE" -attr xrf 44459 -attr oid 335 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3} -attr area 4.378994 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2)"
+load net {FRAME:acc#3.psp.sva(0)} -pin  "FRAME:or#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {FRAME:acc#3.psp.sva(1)} -pin  "FRAME:or#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {FRAME:acc#3.psp.sva(2)} -pin  "FRAME:or#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {FRAME:acc#3.psp.sva(3)} -pin  "FRAME:or#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {FRAME:acc#3.psp.sva(4)} -pin  "FRAME:or#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {FRAME:acc#3.psp.sva(5)} -pin  "FRAME:or#3" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {FRAME:acc#4.psp.sva(10)} -pin  "FRAME:or#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {FRAME:acc#4.psp.sva(11)} -pin  "FRAME:or#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(2)} -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(3)} -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(4)} -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(5)} -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {FRAME:or#3.itm(0)} -pin  "FRAME:or#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(1)} -pin  "FRAME:or#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(2)} -pin  "FRAME:or#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(3)} -pin  "FRAME:or#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(4)} -pin  "FRAME:or#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(5)} -pin  "FRAME:or#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load inst "nand" "nand(3,1)" "INTERFACE" -attr @path {/sobel/sobel:core/nand} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,3)"
+load net {exit:FRAME:for#1.sva#2.st#1} -pin  "nand" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.sva#2.st#1}
+load net {exit:FRAME:for.lpi#1.dfm.st#1} -pin  "nand" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm.st#1}
+load net {main.stage_0#2} -pin  "nand" {A2(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {nand.itm} -pin  "nand" {Z(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load inst "mux" "mux(2,30)" "INTERFACE" -attr xrf 44460 -attr oid 336 -attr vt d -attr @path {/sobel/sobel:core/mux} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "mux" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "mux" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "mux" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "mux" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "mux" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "mux" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "mux" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "mux" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "mux" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "mux" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "mux" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "mux" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "mux" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "mux" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "mux" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "mux" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "mux" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "mux" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "mux" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "mux" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "mux" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "mux" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "mux" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "mux" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "mux" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "mux" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "mux" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "mux" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "mux" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "mux" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {FRAME:acc#4.psp.sva(0)} -pin  "mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(1)} -pin  "mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(2)} -pin  "mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(3)} -pin  "mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(4)} -pin  "mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(5)} -pin  "mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(6)} -pin  "mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(7)} -pin  "mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(8)} -pin  "mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(9)} -pin  "mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(0)} -pin  "mux" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(1)} -pin  "mux" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(2)} -pin  "mux" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(3)} -pin  "mux" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(4)} -pin  "mux" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(5)} -pin  "mux" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(6)} -pin  "mux" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(7)} -pin  "mux" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(8)} -pin  "mux" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(9)} -pin  "mux" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(0)} -pin  "mux" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(1)} -pin  "mux" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(2)} -pin  "mux" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(3)} -pin  "mux" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(4)} -pin  "mux" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(5)} -pin  "mux" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(6)} -pin  "mux" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(7)} -pin  "mux" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(8)} -pin  "mux" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(9)} -pin  "mux" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {nand.itm} -pin  "mux" {S(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load net {mux.itm(0)} -pin  "mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "mux" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "mux" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "mux" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "mux" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "mux" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "mux" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "mux" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "mux" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "mux" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "mux" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "mux" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "mux" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "mux" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "mux" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "mux" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "mux" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "mux" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "mux" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "mux" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "mux" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 44461 -attr oid 337 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)}
+load net {mux.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 44462 -attr oid 338 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:acc#43" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 44463 -attr oid 339 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {FRAME:mul.sdt(8)} -pin  "FRAME:acc#43" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt).itm}
+load net {FRAME:mul.sdt(9)} -pin  "FRAME:acc#43" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt).itm}
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:acc#43" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#3.itm}
+load net {FRAME:acc#43.itm(0)} -pin  "FRAME:acc#43" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {FRAME:acc#43.itm(1)} -pin  "FRAME:acc#43" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load inst "reg(FRAME:acc#41.itm#1.sg2)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 44464 -attr oid 340 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#41.itm#1.sg2)}
+load net {FRAME:acc#43.itm(0)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {FRAME:acc#43.itm(1)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {clk} -attr xrf 44465 -attr oid 341 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#41.itm#1.sg2(0)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg2}
+load net {FRAME:acc#41.itm#1.sg2(1)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg2}
+load inst "reg(FRAME:acc#41.itm#1.sg1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 44466 -attr oid 342 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#41.itm#1.sg1)}
+load net {FRAME:mul.sdt(6)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#2.itm}
+load net {FRAME:mul.sdt(7)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#2.itm}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {clk} -attr xrf 44467 -attr oid 343 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#41.itm#1.sg1(0)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg1}
+load net {FRAME:acc#41.itm#1.sg1(1)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg1}
+load inst "FRAME:acc#44" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 44468 -attr oid 344 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44} -attr area 6.285690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {FRAME:mul.sdt(0)} -pin  "FRAME:acc#44" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(1)} -pin  "FRAME:acc#44" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(2)} -pin  "FRAME:acc#44" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(3)} -pin  "FRAME:acc#44" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(4)} -pin  "FRAME:acc#44" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:acc#44" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {GND} -pin  "FRAME:acc#44" {B(1)} -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:acc#44" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:acc#44" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:acc#44" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {FRAME:acc#44.itm(0)} -pin  "FRAME:acc#44" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(1)} -pin  "FRAME:acc#44" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(2)} -pin  "FRAME:acc#44" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(3)} -pin  "FRAME:acc#44" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(4)} -pin  "FRAME:acc#44" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(5)} -pin  "FRAME:acc#44" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load inst "reg(FRAME:acc#41.itm#3)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 44469 -attr oid 345 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#41.itm#3)}
+load net {FRAME:acc#44.itm(0)} -pin  "reg(FRAME:acc#41.itm#3)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(1)} -pin  "reg(FRAME:acc#41.itm#3)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(2)} -pin  "reg(FRAME:acc#41.itm#3)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(3)} -pin  "reg(FRAME:acc#41.itm#3)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(4)} -pin  "reg(FRAME:acc#41.itm#3)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(5)} -pin  "reg(FRAME:acc#41.itm#3)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(FRAME:acc#41.itm#3)" {clk} -attr xrf 44470 -attr oid 346 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#41.itm#3)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#41.itm#3)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#41.itm#3(0)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(1)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(2)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(3)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(4)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(5)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load inst "FRAME:mul#1" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 44471 -attr oid 347 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC2-3:acc#1.itm(10)} -pin  "FRAME:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {ACC2-3:acc#1.itm(11)} -pin  "FRAME:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {ACC2-3:acc#1.itm(12)} -pin  "FRAME:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {PWR} -pin  "FRAME:mul#1" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#1.itm(0)} -pin  "FRAME:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "FRAME:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "FRAME:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "FRAME:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "FRAME:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "FRAME:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "FRAME:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "FRAME:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "FRAME:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load inst "reg(FRAME:mul#1.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 44472 -attr oid 348 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#1.itm#1)}
+load net {FRAME:mul#1.itm(0)} -pin  "reg(FRAME:mul#1.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "reg(FRAME:mul#1.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "reg(FRAME:mul#1.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "reg(FRAME:mul#1.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "reg(FRAME:mul#1.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "reg(FRAME:mul#1.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "reg(FRAME:mul#1.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "reg(FRAME:mul#1.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "reg(FRAME:mul#1.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#1.itm#1)" {clk} -attr xrf 44473 -attr oid 349 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#1.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#1.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#1.itm#1(0)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(1)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(2)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(3)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(4)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(5)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(6)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(7)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(8)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load inst "reg(red:slc(red#2.sg1).itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 44474 -attr oid 350 -attr vt d -attr @path {/sobel/sobel:core/reg(red:slc(red#2.sg1).itm#1)}
+load net {ACC2-3:acc#1.itm(4)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#1.itm(5)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#1.itm(6)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#1.itm(7)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#1.itm(8)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#1.itm(9)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(red:slc(red#2.sg1).itm#1)" {clk} -attr xrf 44475 -attr oid 351 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(red:slc(red#2.sg1).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {red:slc(red#2.sg1).itm#1(0)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(1)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(2)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(3)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(4)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(5)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load inst "FRAME:not#7" "not(1)" "INTERFACE" -attr xrf 44476 -attr oid 352 -attr @path {/sobel/sobel:core/FRAME:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#9.sva(5)} -pin  "FRAME:not#7" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#9.sva)#6.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load inst "FRAME:not#5" "not(3)" "INTERFACE" -attr xrf 44477 -attr oid 353 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#9.sva(3)} -pin  "FRAME:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#9.sva)#2.itm}
+load net {acc.imod#9.sva(4)} -pin  "FRAME:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#9.sva)#2.itm}
+load net {acc.imod#9.sva(5)} -pin  "FRAME:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#9.sva)#2.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load inst "FRAME:not#4" "not(1)" "INTERFACE" -attr xrf 44478 -attr oid 354 -attr @path {/sobel/sobel:core/FRAME:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#9.sva(5)} -pin  "FRAME:not#4" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#9.sva)#3.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:not#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#4.itm}
+load inst "FRAME:acc#42" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 44479 -attr oid 355 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {PWR} -pin  "FRAME:acc#42" {A(0)} -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {acc.imod#9.sva(0)} -pin  "FRAME:acc#42" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {acc.imod#9.sva(1)} -pin  "FRAME:acc#42" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {acc.imod#9.sva(2)} -pin  "FRAME:acc#42" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {PWR} -pin  "FRAME:acc#42" {A(4)} -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:acc#42" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:acc#42" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:acc#42" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:acc#42" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:acc#42.itm(0)} -pin  "FRAME:acc#42" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(1)} -pin  "FRAME:acc#42" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(2)} -pin  "FRAME:acc#42" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(3)} -pin  "FRAME:acc#42" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(4)} -pin  "FRAME:acc#42" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load inst "FRAME:not#39" "not(1)" "INTERFACE" -attr xrf 44480 -attr oid 356 -attr vt c -attr @path {/sobel/sobel:core/FRAME:not#39} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#42.itm(4)} -pin  "FRAME:not#39" {A(0)} -attr vt c -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:not#39.itm} -pin  "FRAME:not#39" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/FRAME:not#39.itm}
+load inst "FRAME:acc#36" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 44481 -attr oid 357 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#39.itm} -pin  "FRAME:acc#36" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {PWR} -pin  "FRAME:acc#36" {A(1)} -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:acc#36" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {acc.imod#9.sva(3)} -pin  "FRAME:acc#36" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#9.sva)#4.itm}
+load net {acc.imod#9.sva(4)} -pin  "FRAME:acc#36" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#9.sva)#4.itm}
+load net {FRAME:acc#36.itm(0)} -pin  "FRAME:acc#36" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(1)} -pin  "FRAME:acc#36" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(2)} -pin  "FRAME:acc#36" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(3)} -pin  "FRAME:acc#36" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load inst "FRAME:not#6" "not(3)" "INTERFACE" -attr xrf 44482 -attr oid 358 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#1.itm(7)} -pin  "FRAME:not#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {ACC2-3:acc#1.itm(8)} -pin  "FRAME:not#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {ACC2-3:acc#1.itm(9)} -pin  "FRAME:not#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:not#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:not#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:not#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load inst "FRAME:acc#37" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 44483 -attr oid 359 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#36.itm(0)} -pin  "FRAME:acc#37" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(1)} -pin  "FRAME:acc#37" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(2)} -pin  "FRAME:acc#37" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(3)} -pin  "FRAME:acc#37" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:acc#37" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:acc#37" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:acc#37" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:acc#37.itm(0)} -pin  "FRAME:acc#37" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(1)} -pin  "FRAME:acc#37" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(2)} -pin  "FRAME:acc#37" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(3)} -pin  "FRAME:acc#37" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(4)} -pin  "FRAME:acc#37" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load inst "reg(FRAME:acc#37.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 44484 -attr oid 360 -attr vt dc -attr @path {/sobel/sobel:core/reg(FRAME:acc#37.itm#1)}
+load net {FRAME:acc#37.itm(0)} -pin  "reg(FRAME:acc#37.itm#1)" {D(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(1)} -pin  "reg(FRAME:acc#37.itm#1)" {D(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(2)} -pin  "reg(FRAME:acc#37.itm#1)" {D(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(3)} -pin  "reg(FRAME:acc#37.itm#1)" {D(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(4)} -pin  "reg(FRAME:acc#37.itm#1)" {D(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#37.itm#1)" {clk} -attr xrf 44485 -attr oid 361 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#37.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#37.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#37.itm#1(0)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(1)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(2)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(3)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(4)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load inst "reg(FRAME:slc(acc.imod#9)#4.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 44486 -attr oid 362 -attr @path {/sobel/sobel:core/reg(FRAME:slc(acc.imod#9)#4.itm#1)}
+load net {acc.imod#9.sva(5)} -pin  "reg(FRAME:slc(acc.imod#9)#4.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#9.sva).itm}
+load net {GND} -pin  "reg(FRAME:slc(acc.imod#9)#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(FRAME:slc(acc.imod#9)#4.itm#1)" {clk} -attr xrf 44487 -attr oid 363 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(acc.imod#9)#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(acc.imod#9)#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(acc.imod#9)#4.itm#1} -pin  "reg(FRAME:slc(acc.imod#9)#4.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:slc(acc.imod#9)#4.itm#1}
+load inst "FRAME:mul#4" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 44488 -attr oid 364 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC2-3:acc#3.itm(13)} -pin  "FRAME:mul#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#10.itm}
+load net {ACC2-3:acc#3.itm(14)} -pin  "FRAME:mul#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#10.itm}
+load net {PWR} -pin  "FRAME:mul#4" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#4.itm(0)} -pin  "FRAME:mul#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(1)} -pin  "FRAME:mul#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(2)} -pin  "FRAME:mul#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(3)} -pin  "FRAME:mul#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(4)} -pin  "FRAME:mul#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(5)} -pin  "FRAME:mul#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(6)} -pin  "FRAME:mul#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(7)} -pin  "FRAME:mul#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(8)} -pin  "FRAME:mul#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(9)} -pin  "FRAME:mul#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(10)} -pin  "FRAME:mul#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load inst "reg(FRAME:mul#4.itm#1)" "reg(11,1,1,-1,0)" "INTERFACE" -attr xrf 44489 -attr oid 365 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#4.itm#1)}
+load net {FRAME:mul#4.itm(0)} -pin  "reg(FRAME:mul#4.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(1)} -pin  "reg(FRAME:mul#4.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(2)} -pin  "reg(FRAME:mul#4.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(3)} -pin  "reg(FRAME:mul#4.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(4)} -pin  "reg(FRAME:mul#4.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(5)} -pin  "reg(FRAME:mul#4.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(6)} -pin  "reg(FRAME:mul#4.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(7)} -pin  "reg(FRAME:mul#4.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(8)} -pin  "reg(FRAME:mul#4.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(9)} -pin  "reg(FRAME:mul#4.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(10)} -pin  "reg(FRAME:mul#4.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_11}
+load net {clk} -pin  "reg(FRAME:mul#4.itm#1)" {clk} -attr xrf 44490 -attr oid 366 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#4.itm#1(0)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(1)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(2)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(3)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(4)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(5)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(6)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(7)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(8)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(9)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(10)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load inst "FRAME:mul#5" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 44491 -attr oid 367 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC2-3:acc#3.itm(10)} -pin  "FRAME:mul#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {ACC2-3:acc#3.itm(11)} -pin  "FRAME:mul#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {ACC2-3:acc#3.itm(12)} -pin  "FRAME:mul#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {PWR} -pin  "FRAME:mul#5" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#5" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#5" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#5.itm(0)} -pin  "FRAME:mul#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(1)} -pin  "FRAME:mul#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(2)} -pin  "FRAME:mul#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(3)} -pin  "FRAME:mul#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(4)} -pin  "FRAME:mul#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(5)} -pin  "FRAME:mul#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(6)} -pin  "FRAME:mul#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(7)} -pin  "FRAME:mul#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(8)} -pin  "FRAME:mul#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load inst "reg(FRAME:mul#5.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 44492 -attr oid 368 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#5.itm#1)}
+load net {FRAME:mul#5.itm(0)} -pin  "reg(FRAME:mul#5.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(1)} -pin  "reg(FRAME:mul#5.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(2)} -pin  "reg(FRAME:mul#5.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(3)} -pin  "reg(FRAME:mul#5.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(4)} -pin  "reg(FRAME:mul#5.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(5)} -pin  "reg(FRAME:mul#5.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(6)} -pin  "reg(FRAME:mul#5.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(7)} -pin  "reg(FRAME:mul#5.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(8)} -pin  "reg(FRAME:mul#5.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#5.itm#1)" {clk} -attr xrf 44493 -attr oid 369 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#5.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#5.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#5.itm#1(0)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(1)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(2)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(3)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(4)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(5)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(6)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(7)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(8)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load inst "reg(blue:slc(blue#2.sg1).itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 44494 -attr oid 370 -attr vt d -attr @path {/sobel/sobel:core/reg(blue:slc(blue#2.sg1).itm#1)}
+load net {ACC2-3:acc#3.itm(4)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#3.itm(5)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#3.itm(6)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#3.itm(7)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#3.itm(8)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#3.itm(9)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {clk} -attr xrf 44495 -attr oid 371 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {blue:slc(blue#2.sg1).itm#1(0)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(1)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(2)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(3)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(4)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(5)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load inst "FRAME:not#23" "not(1)" "INTERFACE" -attr xrf 44496 -attr oid 372 -attr @path {/sobel/sobel:core/FRAME:not#23} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#13.sva(5)} -pin  "FRAME:not#23" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#13.sva)#6.itm}
+load net {FRAME:not#23.itm} -pin  "FRAME:not#23" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#23.itm}
+load inst "FRAME:not#21" "not(3)" "INTERFACE" -attr xrf 44497 -attr oid 373 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#13.sva(3)} -pin  "FRAME:not#21" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#13.sva)#2.itm}
+load net {acc.imod#13.sva(4)} -pin  "FRAME:not#21" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#13.sva)#2.itm}
+load net {acc.imod#13.sva(5)} -pin  "FRAME:not#21" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#13.sva)#2.itm}
+load net {FRAME:not#21.itm(0)} -pin  "FRAME:not#21" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {FRAME:not#21.itm(1)} -pin  "FRAME:not#21" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {FRAME:not#21.itm(2)} -pin  "FRAME:not#21" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load inst "FRAME:not#20" "not(1)" "INTERFACE" -attr xrf 44498 -attr oid 374 -attr @path {/sobel/sobel:core/FRAME:not#20} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#13.sva(5)} -pin  "FRAME:not#20" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#13.sva)#3.itm}
+load net {FRAME:not#20.itm} -pin  "FRAME:not#20" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load inst "FRAME:acc#35" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 44499 -attr oid 375 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {PWR} -pin  "FRAME:acc#35" {A(0)} -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {acc.imod#13.sva(0)} -pin  "FRAME:acc#35" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {acc.imod#13.sva(1)} -pin  "FRAME:acc#35" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {acc.imod#13.sva(2)} -pin  "FRAME:acc#35" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {PWR} -pin  "FRAME:acc#35" {A(4)} -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {FRAME:not#20.itm} -pin  "FRAME:acc#35" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(0)} -pin  "FRAME:acc#35" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(1)} -pin  "FRAME:acc#35" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(2)} -pin  "FRAME:acc#35" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:acc#35.itm(0)} -pin  "FRAME:acc#35" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(1)} -pin  "FRAME:acc#35" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(2)} -pin  "FRAME:acc#35" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(3)} -pin  "FRAME:acc#35" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(4)} -pin  "FRAME:acc#35" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load inst "FRAME:not#41" "not(1)" "INTERFACE" -attr xrf 44500 -attr oid 376 -attr @path {/sobel/sobel:core/FRAME:not#41} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#35.itm(4)} -pin  "FRAME:not#41" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#6.itm}
+load net {FRAME:not#41.itm} -pin  "FRAME:not#41" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#41.itm}
+load inst "FRAME:acc#29" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 44501 -attr oid 377 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#41.itm} -pin  "FRAME:acc#29" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {PWR} -pin  "FRAME:acc#29" {A(1)} -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {FRAME:not#23.itm} -pin  "FRAME:acc#29" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {acc.imod#13.sva(3)} -pin  "FRAME:acc#29" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#13.sva)#4.itm}
+load net {acc.imod#13.sva(4)} -pin  "FRAME:acc#29" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#13.sva)#4.itm}
+load net {FRAME:acc#29.itm(0)} -pin  "FRAME:acc#29" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(1)} -pin  "FRAME:acc#29" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(2)} -pin  "FRAME:acc#29" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(3)} -pin  "FRAME:acc#29" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load inst "FRAME:not#22" "not(3)" "INTERFACE" -attr xrf 44502 -attr oid 378 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#3.itm(7)} -pin  "FRAME:not#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {ACC2-3:acc#3.itm(8)} -pin  "FRAME:not#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {ACC2-3:acc#3.itm(9)} -pin  "FRAME:not#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {FRAME:not#22.itm(0)} -pin  "FRAME:not#22" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(1)} -pin  "FRAME:not#22" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(2)} -pin  "FRAME:not#22" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load inst "FRAME:acc#30" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 44503 -attr oid 379 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#29.itm(0)} -pin  "FRAME:acc#30" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(1)} -pin  "FRAME:acc#30" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(2)} -pin  "FRAME:acc#30" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(3)} -pin  "FRAME:acc#30" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:not#22.itm(0)} -pin  "FRAME:acc#30" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(1)} -pin  "FRAME:acc#30" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(2)} -pin  "FRAME:acc#30" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:acc#30.itm(0)} -pin  "FRAME:acc#30" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(1)} -pin  "FRAME:acc#30" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(2)} -pin  "FRAME:acc#30" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(3)} -pin  "FRAME:acc#30" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(4)} -pin  "FRAME:acc#30" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load inst "reg(FRAME:acc#30.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 44504 -attr oid 380 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#30.itm#1)}
+load net {FRAME:acc#30.itm(0)} -pin  "reg(FRAME:acc#30.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(1)} -pin  "reg(FRAME:acc#30.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(2)} -pin  "reg(FRAME:acc#30.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(3)} -pin  "reg(FRAME:acc#30.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(4)} -pin  "reg(FRAME:acc#30.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#30.itm#1)" {clk} -attr xrf 44505 -attr oid 381 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#30.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#30.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#30.itm#1(0)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(1)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(2)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(3)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(4)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load inst "reg(FRAME:slc(acc.imod#13)#4.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 44506 -attr oid 382 -attr @path {/sobel/sobel:core/reg(FRAME:slc(acc.imod#13)#4.itm#1)}
+load net {acc.imod#13.sva(5)} -pin  "reg(FRAME:slc(acc.imod#13)#4.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#13.sva).itm}
+load net {GND} -pin  "reg(FRAME:slc(acc.imod#13)#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(FRAME:slc(acc.imod#13)#4.itm#1)" {clk} -attr xrf 44507 -attr oid 383 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(acc.imod#13)#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(acc.imod#13)#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(acc.imod#13)#4.itm#1} -pin  "reg(FRAME:slc(acc.imod#13)#4.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:slc(acc.imod#13)#4.itm#1}
+load inst "reg(blue:slc(blue#2.sg1)#12.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 44508 -attr oid 384 -attr @path {/sobel/sobel:core/reg(blue:slc(blue#2.sg1)#12.itm#1)}
+load net {ACC2-3:acc#3.itm(15)} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva).itm}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {clk} -attr xrf 44509 -attr oid 385 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1)#12.itm#1}
+load inst "FRAME:mul#2" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 44510 -attr oid 386 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC2-3:acc#2.itm(13)} -pin  "FRAME:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#10.itm}
+load net {ACC2-3:acc#2.itm(14)} -pin  "FRAME:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#10.itm}
+load net {PWR} -pin  "FRAME:mul#2" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#2.itm(0)} -pin  "FRAME:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(1)} -pin  "FRAME:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(2)} -pin  "FRAME:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(3)} -pin  "FRAME:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(4)} -pin  "FRAME:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(5)} -pin  "FRAME:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(6)} -pin  "FRAME:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(7)} -pin  "FRAME:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(8)} -pin  "FRAME:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(9)} -pin  "FRAME:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(10)} -pin  "FRAME:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load inst "reg(FRAME:mul#2.itm#1)" "reg(11,1,1,-1,0)" "INTERFACE" -attr xrf 44511 -attr oid 387 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#2.itm#1)}
+load net {FRAME:mul#2.itm(0)} -pin  "reg(FRAME:mul#2.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(1)} -pin  "reg(FRAME:mul#2.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(2)} -pin  "reg(FRAME:mul#2.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(3)} -pin  "reg(FRAME:mul#2.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(4)} -pin  "reg(FRAME:mul#2.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(5)} -pin  "reg(FRAME:mul#2.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(6)} -pin  "reg(FRAME:mul#2.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(7)} -pin  "reg(FRAME:mul#2.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(8)} -pin  "reg(FRAME:mul#2.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(9)} -pin  "reg(FRAME:mul#2.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(10)} -pin  "reg(FRAME:mul#2.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_11}
+load net {clk} -pin  "reg(FRAME:mul#2.itm#1)" {clk} -attr xrf 44512 -attr oid 388 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#2.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#2.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#2.itm#1(0)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(1)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(2)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(3)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(4)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(5)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(6)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(7)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(8)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(9)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(10)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load inst "FRAME:mul#3" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 44513 -attr oid 389 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC2-3:acc#2.itm(10)} -pin  "FRAME:mul#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {ACC2-3:acc#2.itm(11)} -pin  "FRAME:mul#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {ACC2-3:acc#2.itm(12)} -pin  "FRAME:mul#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {PWR} -pin  "FRAME:mul#3" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#3" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#3" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#3.itm(0)} -pin  "FRAME:mul#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "FRAME:mul#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "FRAME:mul#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "FRAME:mul#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "FRAME:mul#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "FRAME:mul#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "FRAME:mul#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "FRAME:mul#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "FRAME:mul#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load inst "reg(FRAME:mul#3.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 44514 -attr oid 390 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#3.itm#1)}
+load net {FRAME:mul#3.itm(0)} -pin  "reg(FRAME:mul#3.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "reg(FRAME:mul#3.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "reg(FRAME:mul#3.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "reg(FRAME:mul#3.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "reg(FRAME:mul#3.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "reg(FRAME:mul#3.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "reg(FRAME:mul#3.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "reg(FRAME:mul#3.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "reg(FRAME:mul#3.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#3.itm#1)" {clk} -attr xrf 44515 -attr oid 391 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#3.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#3.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#3.itm#1(0)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(1)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(2)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(3)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(4)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(5)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(6)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(7)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(8)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load inst "reg(green:slc(green#2.sg1).itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 44516 -attr oid 392 -attr vt d -attr @path {/sobel/sobel:core/reg(green:slc(green#2.sg1).itm#1)}
+load net {ACC2-3:acc#2.itm(4)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#2.itm(5)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#2.itm(6)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#2.itm(7)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#2.itm(8)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#2.itm(9)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(green:slc(green#2.sg1).itm#1)" {clk} -attr xrf 44517 -attr oid 393 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(green:slc(green#2.sg1).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {green:slc(green#2.sg1).itm#1(0)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(1)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(2)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(3)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(4)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(5)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load inst "FRAME:not#15" "not(1)" "INTERFACE" -attr xrf 44518 -attr oid 394 -attr @path {/sobel/sobel:core/FRAME:not#15} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#11.sva(5)} -pin  "FRAME:not#15" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#6.itm}
+load net {FRAME:not#15.itm} -pin  "FRAME:not#15" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#15.itm}
+load inst "FRAME:not#13" "not(3)" "INTERFACE" -attr xrf 44519 -attr oid 395 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#11.sva(3)} -pin  "FRAME:not#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#2.itm}
+load net {acc.imod#11.sva(4)} -pin  "FRAME:not#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#2.itm}
+load net {acc.imod#11.sva(5)} -pin  "FRAME:not#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#2.itm}
+load net {FRAME:not#13.itm(0)} -pin  "FRAME:not#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {FRAME:not#13.itm(1)} -pin  "FRAME:not#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {FRAME:not#13.itm(2)} -pin  "FRAME:not#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load inst "FRAME:not#12" "not(1)" "INTERFACE" -attr xrf 44520 -attr oid 396 -attr @path {/sobel/sobel:core/FRAME:not#12} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#11.sva(5)} -pin  "FRAME:not#12" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#3.itm}
+load net {FRAME:not#12.itm} -pin  "FRAME:not#12" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#12.itm}
+load inst "FRAME:acc#23" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 44521 -attr oid 397 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {PWR} -pin  "FRAME:acc#23" {A(0)} -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {acc.imod#11.sva(0)} -pin  "FRAME:acc#23" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {acc.imod#11.sva(1)} -pin  "FRAME:acc#23" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {acc.imod#11.sva(2)} -pin  "FRAME:acc#23" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {PWR} -pin  "FRAME:acc#23" {A(4)} -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {FRAME:not#12.itm} -pin  "FRAME:acc#23" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(0)} -pin  "FRAME:acc#23" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(1)} -pin  "FRAME:acc#23" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(2)} -pin  "FRAME:acc#23" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:acc#23.itm(0)} -pin  "FRAME:acc#23" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(1)} -pin  "FRAME:acc#23" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(2)} -pin  "FRAME:acc#23" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(3)} -pin  "FRAME:acc#23" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(4)} -pin  "FRAME:acc#23" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load inst "FRAME:not#43" "not(1)" "INTERFACE" -attr xrf 44522 -attr oid 398 -attr @path {/sobel/sobel:core/FRAME:not#43} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#23.itm(4)} -pin  "FRAME:not#43" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#5.itm}
+load net {FRAME:not#43.itm} -pin  "FRAME:not#43" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#43.itm}
+load inst "FRAME:acc#17" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 44523 -attr oid 399 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#43.itm} -pin  "FRAME:acc#17" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {PWR} -pin  "FRAME:acc#17" {A(1)} -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {FRAME:not#15.itm} -pin  "FRAME:acc#17" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {acc.imod#11.sva(3)} -pin  "FRAME:acc#17" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#4.itm}
+load net {acc.imod#11.sva(4)} -pin  "FRAME:acc#17" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#4.itm}
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:acc#17" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:acc#17" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load inst "FRAME:not#14" "not(3)" "INTERFACE" -attr xrf 44524 -attr oid 400 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#2.itm(7)} -pin  "FRAME:not#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {ACC2-3:acc#2.itm(8)} -pin  "FRAME:not#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {ACC2-3:acc#2.itm(9)} -pin  "FRAME:not#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {FRAME:not#14.itm(0)} -pin  "FRAME:not#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(1)} -pin  "FRAME:not#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(2)} -pin  "FRAME:not#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load inst "FRAME:acc#18" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 44525 -attr oid 401 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:acc#18" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:acc#18" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:not#14.itm(0)} -pin  "FRAME:acc#18" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(1)} -pin  "FRAME:acc#18" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(2)} -pin  "FRAME:acc#18" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:acc#18.itm(0)} -pin  "FRAME:acc#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(1)} -pin  "FRAME:acc#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(2)} -pin  "FRAME:acc#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(3)} -pin  "FRAME:acc#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(4)} -pin  "FRAME:acc#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load inst "reg(FRAME:acc#18.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 44526 -attr oid 402 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#18.itm#1)}
+load net {FRAME:acc#18.itm(0)} -pin  "reg(FRAME:acc#18.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(1)} -pin  "reg(FRAME:acc#18.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(2)} -pin  "reg(FRAME:acc#18.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(3)} -pin  "reg(FRAME:acc#18.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(4)} -pin  "reg(FRAME:acc#18.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#18.itm#1)" {clk} -attr xrf 44527 -attr oid 403 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#18.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#18.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#18.itm#1(0)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(1)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(2)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(3)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(4)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load inst "reg(FRAME:slc(acc.imod#11)#4.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 44528 -attr oid 404 -attr @path {/sobel/sobel:core/reg(FRAME:slc(acc.imod#11)#4.itm#1)}
+load net {acc.imod#11.sva(5)} -pin  "reg(FRAME:slc(acc.imod#11)#4.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva).itm}
+load net {GND} -pin  "reg(FRAME:slc(acc.imod#11)#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(FRAME:slc(acc.imod#11)#4.itm#1)" {clk} -attr xrf 44529 -attr oid 405 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(acc.imod#11)#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(acc.imod#11)#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(acc.imod#11)#4.itm#1} -pin  "reg(FRAME:slc(acc.imod#11)#4.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:slc(acc.imod#11)#4.itm#1}
+load inst "reg(green:slc(green#2.sg1)#12.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 44530 -attr oid 406 -attr @path {/sobel/sobel:core/reg(green:slc(green#2.sg1)#12.itm#1)}
+load net {ACC2-3:acc#2.itm(15)} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva).itm}
+load net {GND} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {clk} -attr xrf 44531 -attr oid 407 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {green:slc(green#2.sg1)#12.itm#1} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/green:slc(green#2.sg1)#12.itm#1}
+load inst "FRAME:for#1:not#7" "not(1)" "INTERFACE" -attr xrf 44532 -attr oid 408 -attr @path {/sobel/sobel:core/FRAME:for#1:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for#1:acc.itm(1)} -pin  "FRAME:for#1:not#7" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:slc.itm}
+load net {FRAME:for#1:not#7.itm} -pin  "FRAME:for#1:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#7.itm}
+load inst "reg(exit:FRAME:for#1.sva#2.st#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 44533 -attr oid 409 -attr @path {/sobel/sobel:core/reg(exit:FRAME:for#1.sva#2.st#1)}
+load net {FRAME:for#1:not#7.itm} -pin  "reg(exit:FRAME:for#1.sva#2.st#1)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#7.itm}
+load net {GND} -pin  "reg(exit:FRAME:for#1.sva#2.st#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME:for#1.sva#2.st#1)" {clk} -attr xrf 44534 -attr oid 410 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for#1.sva#2.st#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for#1.sva#2.st#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for#1.sva#2.st#1} -pin  "reg(exit:FRAME:for#1.sva#2.st#1)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.sva#2.st#1}
+load inst "reg(exit:FRAME:for.lpi#1.dfm.st#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 44535 -attr oid 411 -attr @path {/sobel/sobel:core/reg(exit:FRAME:for.lpi#1.dfm.st#1)}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "reg(exit:FRAME:for.lpi#1.dfm.st#1)" {D(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {GND} -pin  "reg(exit:FRAME:for.lpi#1.dfm.st#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME:for.lpi#1.dfm.st#1)" {clk} -attr xrf 44536 -attr oid 412 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for.lpi#1.dfm.st#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for.lpi#1.dfm.st#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for.lpi#1.dfm.st#1} -pin  "reg(exit:FRAME:for.lpi#1.dfm.st#1)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm.st#1}
+load inst "FRAME:for:and#13" "and(2,2)" "INTERFACE" -attr xrf 44537 -attr oid 413 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#13} -attr area 1.459665 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2)"
+load net {i#7.lpi#1(0)} -pin  "FRAME:for:and#13" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "FRAME:for:and#13" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:and#13" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#30.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:and#13" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#30.itm}
+load net {FRAME:for:and#13.itm(0)} -pin  "FRAME:for:and#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#13.itm}
+load net {FRAME:for:and#13.itm(1)} -pin  "FRAME:for:and#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#13.itm}
+load inst "mux#1" "mux(2,2)" "INTERFACE" -attr xrf 44538 -attr oid 414 -attr vt d -attr @path {/sobel/sobel:core/mux#1} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {FRAME:for:and#13.itm(0)} -pin  "mux#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#13.itm}
+load net {FRAME:for:and#13.itm(1)} -pin  "mux#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#13.itm}
+load net {i#7.sva(0)} -pin  "mux#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load net {i#7.sva(1)} -pin  "mux#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load net {or#4.cse} -pin  "mux#1" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#1.itm(0)} -pin  "mux#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(1)} -pin  "mux#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load inst "reg(i#7.lpi#1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 44539 -attr oid 415 -attr vt d -attr @path {/sobel/sobel:core/reg(i#7.lpi#1)}
+load net {mux#1.itm(0)} -pin  "reg(i#7.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(1)} -pin  "reg(i#7.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {GND} -pin  "reg(i#7.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(i#7.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(i#7.lpi#1)" {clk} -attr xrf 44540 -attr oid 416 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(i#7.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(i#7.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {i#7.lpi#1(0)} -pin  "reg(i#7.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "reg(i#7.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load inst "FRAME:for:not" "not(1)" "INTERFACE" -attr xrf 44541 -attr oid 417 -attr @path {/sobel/sobel:core/FRAME:for:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:not" {A(0)} -attr @path {/sobel/sobel:core/xor_cse#2}
+load net {FRAME:for:not.itm} -pin  "FRAME:for:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load inst "mux#2" "mux(2,1)" "INTERFACE" -attr xrf 44542 -attr oid 418 -attr @path {/sobel/sobel:core/mux#2} -attr area 0.920423 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2)"
+load net {FRAME:for:not.itm} -pin  "mux#2" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "mux#2" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {or#4.cse} -pin  "mux#2" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#2.itm} -pin  "mux#2" {Z(0)} -attr @path {/sobel/sobel:core/mux#2.itm}
+load inst "reg(exit:FRAME:for.lpi#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 44543 -attr oid 419 -attr @path {/sobel/sobel:core/reg(exit:FRAME:for.lpi#1)}
+load net {mux#2.itm} -pin  "reg(exit:FRAME:for.lpi#1)" {D(0)} -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {GND} -pin  "reg(exit:FRAME:for.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME:for.lpi#1)" {clk} -attr xrf 44544 -attr oid 420 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for.lpi#1} -pin  "reg(exit:FRAME:for.lpi#1)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1}
+load inst "reg(exit:FRAME:for#1.lpi#1.dfm#4)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 44545 -attr oid 421 -attr @path {/sobel/sobel:core/reg(exit:FRAME:for#1.lpi#1.dfm#4)}
+load net {exit:FRAME:for#1.lpi#1.dfm#4:mx0} -pin  "reg(exit:FRAME:for#1.lpi#1.dfm#4)" {D(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4:mx0}
+load net {GND} -pin  "reg(exit:FRAME:for#1.lpi#1.dfm#4)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME:for#1.lpi#1.dfm#4)" {clk} -attr xrf 44546 -attr oid 422 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for#1.lpi#1.dfm#4)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for#1.lpi#1.dfm#4)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for#1.lpi#1.dfm#4} -pin  "reg(exit:FRAME:for#1.lpi#1.dfm#4)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4}
+load inst "FRAME:and" "and(2,1)" "INTERFACE" -attr xrf 44547 -attr oid 423 -attr @path {/sobel/sobel:core/FRAME:and} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {exit:FRAME:for#1.lpi#1.dfm#4:mx0} -pin  "FRAME:and" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4:mx0}
+load net {exit:FRAME.lpi#1.dfm#2:mx0} -pin  "FRAME:and" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#2:mx0}
+load net {FRAME:and.itm} -pin  "FRAME:and" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load inst "reg(exit:FRAME#1.sva)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 44548 -attr oid 424 -attr @path {/sobel/sobel:core/reg(exit:FRAME#1.sva)}
+load net {FRAME:and.itm} -pin  "reg(exit:FRAME#1.sva)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load net {PWR} -pin  "reg(exit:FRAME#1.sva)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1_Not}
+load net {clk} -pin  "reg(exit:FRAME#1.sva)" {clk} -attr xrf 44549 -attr oid 425 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME#1.sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME#1.sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME#1.sva} -pin  "reg(exit:FRAME#1.sva)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load inst "reg(main.stage_0#2)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 44550 -attr oid 426 -attr @path {/sobel/sobel:core/reg(main.stage_0#2)}
+load net {PWR} -pin  "reg(main.stage_0#2)" {D(0)} -attr @path {/sobel/sobel:core/Cn1_1#4}
+load net {GND} -pin  "reg(main.stage_0#2)" {DRa(0)} -attr @path {/sobel/sobel:core/Cn2_2#8}
+load net {clk} -pin  "reg(main.stage_0#2)" {clk} -attr xrf 44551 -attr oid 427 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(main.stage_0#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(main.stage_0#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {main.stage_0#2} -pin  "reg(main.stage_0#2)" {Z(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load inst "reg(regs.regs(2).lpi#1.dfm)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 44552 -attr oid 428 -attr vt dc -attr @path {/sobel/sobel:core/reg(regs.regs(2).lpi#1.dfm)}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(30)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(31)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(32)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(33)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(34)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(35)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(36)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(37)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(38)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(39)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(40)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(41)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(42)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(43)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(44)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(45)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(46)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(47)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(48)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(49)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(50)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(51)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(52)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(53)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(54)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(55)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(56)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(57)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(58)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(59)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(60)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(61)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(62)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(63)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(64)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(65)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(66)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(67)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(68)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(69)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(70)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(71)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(72)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(73)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(74)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(75)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(76)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(77)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(78)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(79)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(80)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(81)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(82)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(83)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(84)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(85)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(86)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(87)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(88)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(89)} -attr @path {/sobel/sobel:core/C0_90}
+load net {clk} -pin  "reg(regs.regs(2).lpi#1.dfm)" {clk} -attr xrf 44553 -attr oid 429 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(2).lpi#1.dfm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(2).lpi#1.dfm(0)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(1)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(2)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(3)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(4)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(5)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(6)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(7)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(8)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(9)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(10)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(11)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(12)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(13)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(14)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(15)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(16)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(16)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(17)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(17)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(18)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(18)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(19)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(19)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(20)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(20)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(21)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(21)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(22)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(22)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(23)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(23)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(24)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(24)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(25)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(25)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(26)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(26)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(27)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(27)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(28)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(28)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(29)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(29)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(30)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(30)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(31)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(31)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(32)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(32)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(33)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(33)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(34)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(34)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(35)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(35)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(36)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(36)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(37)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(37)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(38)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(38)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(39)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(39)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(40)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(40)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(41)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(41)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(42)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(42)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(43)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(43)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(44)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(44)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(45)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(45)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(46)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(46)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(47)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(47)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(48)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(48)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(49)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(49)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(50)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(50)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(51)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(51)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(52)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(52)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(53)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(53)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(54)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(54)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(55)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(55)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(56)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(56)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(57)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(57)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(58)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(58)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(59)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(59)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(60)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(60)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(61)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(61)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(62)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(62)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(63)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(63)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(64)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(64)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(65)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(65)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(66)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(66)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(67)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(67)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(68)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(68)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(69)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(69)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(70)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(70)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(71)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(71)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(72)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(72)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(73)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(73)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(74)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(74)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(75)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(75)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(76)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(76)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(77)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(77)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(78)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(78)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(79)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(79)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(80)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(80)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(81)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(81)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(82)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(82)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(83)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(83)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(84)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(84)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(85)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(85)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(86)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(86)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(87)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(87)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(88)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(88)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(89)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(89)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load inst "reg(regs.regs(1).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 44554 -attr oid 430 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(1).sva)}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "reg(regs.regs(1).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "reg(regs.regs(1).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "reg(regs.regs(1).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "reg(regs.regs(1).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "reg(regs.regs(1).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "reg(regs.regs(1).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "reg(regs.regs(1).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "reg(regs.regs(1).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "reg(regs.regs(1).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "reg(regs.regs(1).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "reg(regs.regs(1).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "reg(regs.regs(1).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "reg(regs.regs(1).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "reg(regs.regs(1).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "reg(regs.regs(1).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "reg(regs.regs(1).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "reg(regs.regs(1).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "reg(regs.regs(1).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "reg(regs.regs(1).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "reg(regs.regs(1).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "reg(regs.regs(1).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "reg(regs.regs(1).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "reg(regs.regs(1).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "reg(regs.regs(1).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "reg(regs.regs(1).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "reg(regs.regs(1).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "reg(regs.regs(1).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "reg(regs.regs(1).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "reg(regs.regs(1).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "reg(regs.regs(1).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "reg(regs.regs(1).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "reg(regs.regs(1).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "reg(regs.regs(1).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "reg(regs.regs(1).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "reg(regs.regs(1).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "reg(regs.regs(1).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "reg(regs.regs(1).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "reg(regs.regs(1).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "reg(regs.regs(1).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "reg(regs.regs(1).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "reg(regs.regs(1).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "reg(regs.regs(1).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "reg(regs.regs(1).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "reg(regs.regs(1).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "reg(regs.regs(1).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "reg(regs.regs(1).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "reg(regs.regs(1).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "reg(regs.regs(1).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "reg(regs.regs(1).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "reg(regs.regs(1).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "reg(regs.regs(1).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "reg(regs.regs(1).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "reg(regs.regs(1).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "reg(regs.regs(1).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "reg(regs.regs(1).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "reg(regs.regs(1).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "reg(regs.regs(1).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "reg(regs.regs(1).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "reg(regs.regs(1).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "reg(regs.regs(1).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "reg(regs.regs(1).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "reg(regs.regs(1).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "reg(regs.regs(1).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "reg(regs.regs(1).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "reg(regs.regs(1).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "reg(regs.regs(1).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "reg(regs.regs(1).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "reg(regs.regs(1).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "reg(regs.regs(1).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "reg(regs.regs(1).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "reg(regs.regs(1).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "reg(regs.regs(1).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "reg(regs.regs(1).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "reg(regs.regs(1).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "reg(regs.regs(1).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "reg(regs.regs(1).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "reg(regs.regs(1).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "reg(regs.regs(1).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "reg(regs.regs(1).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "reg(regs.regs(1).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "reg(regs.regs(1).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "reg(regs.regs(1).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "reg(regs.regs(1).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "reg(regs.regs(1).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "reg(regs.regs(1).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "reg(regs.regs(1).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "reg(regs.regs(1).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "reg(regs.regs(1).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "reg(regs.regs(1).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "reg(regs.regs(1).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {clk} -pin  "reg(regs.regs(1).sva)" {clk} -attr xrf 44555 -attr oid 431 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(1).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(1).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(1).sva(0)} -pin  "reg(regs.regs(1).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "reg(regs.regs(1).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "reg(regs.regs(1).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "reg(regs.regs(1).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "reg(regs.regs(1).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "reg(regs.regs(1).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "reg(regs.regs(1).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "reg(regs.regs(1).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "reg(regs.regs(1).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "reg(regs.regs(1).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "reg(regs.regs(1).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "reg(regs.regs(1).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "reg(regs.regs(1).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "reg(regs.regs(1).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "reg(regs.regs(1).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "reg(regs.regs(1).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "reg(regs.regs(1).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "reg(regs.regs(1).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "reg(regs.regs(1).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "reg(regs.regs(1).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "reg(regs.regs(1).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "reg(regs.regs(1).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "reg(regs.regs(1).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "reg(regs.regs(1).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "reg(regs.regs(1).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "reg(regs.regs(1).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "reg(regs.regs(1).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "reg(regs.regs(1).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "reg(regs.regs(1).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "reg(regs.regs(1).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "reg(regs.regs(1).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "reg(regs.regs(1).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "reg(regs.regs(1).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "reg(regs.regs(1).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "reg(regs.regs(1).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "reg(regs.regs(1).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "reg(regs.regs(1).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "reg(regs.regs(1).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "reg(regs.regs(1).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "reg(regs.regs(1).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "reg(regs.regs(1).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "reg(regs.regs(1).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "reg(regs.regs(1).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "reg(regs.regs(1).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "reg(regs.regs(1).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "reg(regs.regs(1).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "reg(regs.regs(1).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "reg(regs.regs(1).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "reg(regs.regs(1).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "reg(regs.regs(1).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "reg(regs.regs(1).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "reg(regs.regs(1).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "reg(regs.regs(1).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "reg(regs.regs(1).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "reg(regs.regs(1).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "reg(regs.regs(1).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "reg(regs.regs(1).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "reg(regs.regs(1).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "reg(regs.regs(1).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "reg(regs.regs(1).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "reg(regs.regs(1).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "reg(regs.regs(1).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "reg(regs.regs(1).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "reg(regs.regs(1).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "reg(regs.regs(1).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "reg(regs.regs(1).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "reg(regs.regs(1).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "reg(regs.regs(1).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "reg(regs.regs(1).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "reg(regs.regs(1).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "reg(regs.regs(1).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "reg(regs.regs(1).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "reg(regs.regs(1).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "reg(regs.regs(1).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "reg(regs.regs(1).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "reg(regs.regs(1).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "reg(regs.regs(1).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "reg(regs.regs(1).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "reg(regs.regs(1).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "reg(regs.regs(1).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "reg(regs.regs(1).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "reg(regs.regs(1).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "reg(regs.regs(1).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "reg(regs.regs(1).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "reg(regs.regs(1).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "reg(regs.regs(1).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "reg(regs.regs(1).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "reg(regs.regs(1).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "reg(regs.regs(1).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "reg(regs.regs(1).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load inst "reg(regs.regs(0).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 44556 -attr oid 432 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva)}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "reg(regs.regs(0).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "reg(regs.regs(0).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "reg(regs.regs(0).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "reg(regs.regs(0).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "reg(regs.regs(0).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "reg(regs.regs(0).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "reg(regs.regs(0).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "reg(regs.regs(0).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "reg(regs.regs(0).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "reg(regs.regs(0).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "reg(regs.regs(0).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "reg(regs.regs(0).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "reg(regs.regs(0).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "reg(regs.regs(0).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "reg(regs.regs(0).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "reg(regs.regs(0).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "reg(regs.regs(0).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "reg(regs.regs(0).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "reg(regs.regs(0).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "reg(regs.regs(0).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "reg(regs.regs(0).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "reg(regs.regs(0).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "reg(regs.regs(0).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "reg(regs.regs(0).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "reg(regs.regs(0).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "reg(regs.regs(0).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "reg(regs.regs(0).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "reg(regs.regs(0).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "reg(regs.regs(0).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "reg(regs.regs(0).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "reg(regs.regs(0).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "reg(regs.regs(0).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "reg(regs.regs(0).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "reg(regs.regs(0).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "reg(regs.regs(0).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "reg(regs.regs(0).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "reg(regs.regs(0).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "reg(regs.regs(0).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "reg(regs.regs(0).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "reg(regs.regs(0).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "reg(regs.regs(0).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "reg(regs.regs(0).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "reg(regs.regs(0).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "reg(regs.regs(0).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "reg(regs.regs(0).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "reg(regs.regs(0).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "reg(regs.regs(0).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "reg(regs.regs(0).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "reg(regs.regs(0).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "reg(regs.regs(0).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "reg(regs.regs(0).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "reg(regs.regs(0).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "reg(regs.regs(0).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "reg(regs.regs(0).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "reg(regs.regs(0).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "reg(regs.regs(0).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "reg(regs.regs(0).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "reg(regs.regs(0).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "reg(regs.regs(0).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "reg(regs.regs(0).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "reg(regs.regs(0).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "reg(regs.regs(0).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "reg(regs.regs(0).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "reg(regs.regs(0).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "reg(regs.regs(0).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "reg(regs.regs(0).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "reg(regs.regs(0).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "reg(regs.regs(0).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "reg(regs.regs(0).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "reg(regs.regs(0).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "reg(regs.regs(0).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "reg(regs.regs(0).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "reg(regs.regs(0).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "reg(regs.regs(0).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "reg(regs.regs(0).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "reg(regs.regs(0).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "reg(regs.regs(0).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "reg(regs.regs(0).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "reg(regs.regs(0).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "reg(regs.regs(0).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "reg(regs.regs(0).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "reg(regs.regs(0).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "reg(regs.regs(0).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "reg(regs.regs(0).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "reg(regs.regs(0).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "reg(regs.regs(0).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "reg(regs.regs(0).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "reg(regs.regs(0).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "reg(regs.regs(0).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "reg(regs.regs(0).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {clk} -pin  "reg(regs.regs(0).sva)" {clk} -attr xrf 44557 -attr oid 433 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(0).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(0).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(0).sva(0)} -pin  "reg(regs.regs(0).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "reg(regs.regs(0).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "reg(regs.regs(0).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "reg(regs.regs(0).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "reg(regs.regs(0).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "reg(regs.regs(0).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "reg(regs.regs(0).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "reg(regs.regs(0).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "reg(regs.regs(0).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "reg(regs.regs(0).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "reg(regs.regs(0).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "reg(regs.regs(0).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "reg(regs.regs(0).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "reg(regs.regs(0).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "reg(regs.regs(0).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "reg(regs.regs(0).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "reg(regs.regs(0).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "reg(regs.regs(0).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "reg(regs.regs(0).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "reg(regs.regs(0).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "reg(regs.regs(0).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "reg(regs.regs(0).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "reg(regs.regs(0).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "reg(regs.regs(0).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "reg(regs.regs(0).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "reg(regs.regs(0).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "reg(regs.regs(0).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "reg(regs.regs(0).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "reg(regs.regs(0).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "reg(regs.regs(0).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "reg(regs.regs(0).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "reg(regs.regs(0).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "reg(regs.regs(0).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "reg(regs.regs(0).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "reg(regs.regs(0).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "reg(regs.regs(0).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "reg(regs.regs(0).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "reg(regs.regs(0).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "reg(regs.regs(0).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "reg(regs.regs(0).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "reg(regs.regs(0).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "reg(regs.regs(0).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "reg(regs.regs(0).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "reg(regs.regs(0).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "reg(regs.regs(0).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "reg(regs.regs(0).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "reg(regs.regs(0).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "reg(regs.regs(0).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "reg(regs.regs(0).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "reg(regs.regs(0).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "reg(regs.regs(0).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "reg(regs.regs(0).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "reg(regs.regs(0).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "reg(regs.regs(0).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "reg(regs.regs(0).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "reg(regs.regs(0).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "reg(regs.regs(0).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "reg(regs.regs(0).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "reg(regs.regs(0).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "reg(regs.regs(0).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "reg(regs.regs(0).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "reg(regs.regs(0).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "reg(regs.regs(0).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "reg(regs.regs(0).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "reg(regs.regs(0).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "reg(regs.regs(0).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "reg(regs.regs(0).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "reg(regs.regs(0).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "reg(regs.regs(0).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "reg(regs.regs(0).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "reg(regs.regs(0).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "reg(regs.regs(0).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "reg(regs.regs(0).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "reg(regs.regs(0).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "reg(regs.regs(0).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "reg(regs.regs(0).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "reg(regs.regs(0).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "reg(regs.regs(0).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "reg(regs.regs(0).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "reg(regs.regs(0).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "reg(regs.regs(0).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "reg(regs.regs(0).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "reg(regs.regs(0).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "reg(regs.regs(0).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "reg(regs.regs(0).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "reg(regs.regs(0).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "reg(regs.regs(0).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "reg(regs.regs(0).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "reg(regs.regs(0).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "reg(regs.regs(0).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load inst "reg(exit:FRAME.lpi#1.dfm#2)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 44558 -attr oid 434 -attr @path {/sobel/sobel:core/reg(exit:FRAME.lpi#1.dfm#2)}
+load net {exit:FRAME.lpi#1.dfm#2:mx0} -pin  "reg(exit:FRAME.lpi#1.dfm#2)" {D(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#2:mx0}
+load net {GND} -pin  "reg(exit:FRAME.lpi#1.dfm#2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME.lpi#1.dfm#2)" {clk} -attr xrf 44559 -attr oid 435 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME.lpi#1.dfm#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME.lpi#1.dfm#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME.lpi#1.dfm#2} -pin  "reg(exit:FRAME.lpi#1.dfm#2)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#2}
+load inst "regs.operator[]#23:mux" "mux(4,10)" "INTERFACE" -attr xrf 44560 -attr oid 436 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "regs.operator[]#23:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "regs.operator[]#23:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "regs.operator[]#23:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "regs.operator[]#23:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "regs.operator[]#23:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "regs.operator[]#23:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "regs.operator[]#23:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "regs.operator[]#23:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "regs.operator[]#23:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "regs.operator[]#23:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "regs.operator[]#23:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "regs.operator[]#23:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "regs.operator[]#23:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "regs.operator[]#23:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "regs.operator[]#23:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "regs.operator[]#23:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "regs.operator[]#23:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "regs.operator[]#23:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "regs.operator[]#23:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "regs.operator[]#23:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "regs.operator[]#23:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "regs.operator[]#23:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "regs.operator[]#23:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "regs.operator[]#23:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "regs.operator[]#23:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "regs.operator[]#23:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "regs.operator[]#23:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "regs.operator[]#23:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "regs.operator[]#23:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "regs.operator[]#23:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#23:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#23:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#23:mux.itm(0)} -pin  "regs.operator[]#23:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(1)} -pin  "regs.operator[]#23:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(2)} -pin  "regs.operator[]#23:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(3)} -pin  "regs.operator[]#23:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(4)} -pin  "regs.operator[]#23:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(5)} -pin  "regs.operator[]#23:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(6)} -pin  "regs.operator[]#23:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(7)} -pin  "regs.operator[]#23:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(8)} -pin  "regs.operator[]#23:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(9)} -pin  "regs.operator[]#23:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load inst "FRAME:for:mul#5" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 44561 -attr oid 437 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#23:mux.itm(0)} -pin  "FRAME:for:mul#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(1)} -pin  "FRAME:for:mul#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(2)} -pin  "FRAME:for:mul#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(3)} -pin  "FRAME:for:mul#5" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(4)} -pin  "FRAME:for:mul#5" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(5)} -pin  "FRAME:for:mul#5" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(6)} -pin  "FRAME:for:mul#5" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(7)} -pin  "FRAME:for:mul#5" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(8)} -pin  "FRAME:for:mul#5" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(9)} -pin  "FRAME:for:mul#5" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {FRAME:for:or#5.itm} -pin  "FRAME:for:mul#5" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#32}
+load net {FRAME:for:and#18.seb} -pin  "FRAME:for:mul#5" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#32}
+load net {FRAME:for:mul#5.itm(0)} -pin  "FRAME:for:mul#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(1)} -pin  "FRAME:for:mul#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(2)} -pin  "FRAME:for:mul#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(3)} -pin  "FRAME:for:mul#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(4)} -pin  "FRAME:for:mul#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(5)} -pin  "FRAME:for:mul#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(6)} -pin  "FRAME:for:mul#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(7)} -pin  "FRAME:for:mul#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(8)} -pin  "FRAME:for:mul#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(9)} -pin  "FRAME:for:mul#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(10)} -pin  "FRAME:for:mul#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load inst "FRAME:for:acc#28" "add(15,-1,11,1,15)" "INTERFACE" -attr xrf 44562 -attr oid 438 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28} -attr area 16.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {b(1).sg1.lpi#1.dfm(0)} -pin  "FRAME:for:acc#28" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(1)} -pin  "FRAME:for:acc#28" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(2)} -pin  "FRAME:for:acc#28" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(3)} -pin  "FRAME:for:acc#28" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(4)} -pin  "FRAME:for:acc#28" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(5)} -pin  "FRAME:for:acc#28" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(6)} -pin  "FRAME:for:acc#28" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(7)} -pin  "FRAME:for:acc#28" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(8)} -pin  "FRAME:for:acc#28" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(9)} -pin  "FRAME:for:acc#28" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(10)} -pin  "FRAME:for:acc#28" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(11)} -pin  "FRAME:for:acc#28" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(12)} -pin  "FRAME:for:acc#28" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(13)} -pin  "FRAME:for:acc#28" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(14)} -pin  "FRAME:for:acc#28" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {FRAME:for:mul#5.itm(0)} -pin  "FRAME:for:acc#28" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(1)} -pin  "FRAME:for:acc#28" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(2)} -pin  "FRAME:for:acc#28" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(3)} -pin  "FRAME:for:acc#28" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(4)} -pin  "FRAME:for:acc#28" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(5)} -pin  "FRAME:for:acc#28" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(6)} -pin  "FRAME:for:acc#28" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(7)} -pin  "FRAME:for:acc#28" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(8)} -pin  "FRAME:for:acc#28" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(9)} -pin  "FRAME:for:acc#28" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(10)} -pin  "FRAME:for:acc#28" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:acc#28.itm(0)} -pin  "FRAME:for:acc#28" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(1)} -pin  "FRAME:for:acc#28" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(2)} -pin  "FRAME:for:acc#28" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(3)} -pin  "FRAME:for:acc#28" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(4)} -pin  "FRAME:for:acc#28" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(5)} -pin  "FRAME:for:acc#28" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(6)} -pin  "FRAME:for:acc#28" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(7)} -pin  "FRAME:for:acc#28" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(8)} -pin  "FRAME:for:acc#28" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(9)} -pin  "FRAME:for:acc#28" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(10)} -pin  "FRAME:for:acc#28" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(11)} -pin  "FRAME:for:acc#28" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(12)} -pin  "FRAME:for:acc#28" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(13)} -pin  "FRAME:for:acc#28" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(14)} -pin  "FRAME:for:acc#28" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load inst "mux#8" "mux(2,15)" "INTERFACE" -attr xrf 44563 -attr oid 439 -attr vt d -attr @path {/sobel/sobel:core/mux#8} -attr area 13.792345 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(15,1,2)"
+load net {FRAME:for:acc#28.itm(0)} -pin  "mux#8" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(1)} -pin  "mux#8" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(2)} -pin  "mux#8" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(3)} -pin  "mux#8" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(4)} -pin  "mux#8" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(5)} -pin  "mux#8" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(6)} -pin  "mux#8" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(7)} -pin  "mux#8" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(8)} -pin  "mux#8" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(9)} -pin  "mux#8" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(10)} -pin  "mux#8" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(11)} -pin  "mux#8" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(12)} -pin  "mux#8" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(13)} -pin  "mux#8" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(14)} -pin  "mux#8" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {b(1).sg1.lpi#1.dfm(0)} -pin  "mux#8" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(1)} -pin  "mux#8" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(2)} -pin  "mux#8" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(3)} -pin  "mux#8" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(4)} -pin  "mux#8" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(5)} -pin  "mux#8" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(6)} -pin  "mux#8" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(7)} -pin  "mux#8" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(8)} -pin  "mux#8" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(9)} -pin  "mux#8" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(10)} -pin  "mux#8" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(11)} -pin  "mux#8" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(12)} -pin  "mux#8" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(13)} -pin  "mux#8" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(14)} -pin  "mux#8" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {or#4.cse} -pin  "mux#8" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#8.itm(0)} -pin  "mux#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(1)} -pin  "mux#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(2)} -pin  "mux#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(3)} -pin  "mux#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(4)} -pin  "mux#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(5)} -pin  "mux#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(6)} -pin  "mux#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(7)} -pin  "mux#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(8)} -pin  "mux#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(9)} -pin  "mux#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(10)} -pin  "mux#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(11)} -pin  "mux#8" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(12)} -pin  "mux#8" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(13)} -pin  "mux#8" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(14)} -pin  "mux#8" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load inst "reg(b(1).sg1.lpi#1)" "reg(15,1,1,-1,0)" "INTERFACE" -attr xrf 44564 -attr oid 440 -attr vt d -attr @path {/sobel/sobel:core/reg(b(1).sg1.lpi#1)}
+load net {mux#8.itm(0)} -pin  "reg(b(1).sg1.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(1)} -pin  "reg(b(1).sg1.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(2)} -pin  "reg(b(1).sg1.lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(3)} -pin  "reg(b(1).sg1.lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(4)} -pin  "reg(b(1).sg1.lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(5)} -pin  "reg(b(1).sg1.lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(6)} -pin  "reg(b(1).sg1.lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(7)} -pin  "reg(b(1).sg1.lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(8)} -pin  "reg(b(1).sg1.lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(9)} -pin  "reg(b(1).sg1.lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(10)} -pin  "reg(b(1).sg1.lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(11)} -pin  "reg(b(1).sg1.lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(12)} -pin  "reg(b(1).sg1.lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(13)} -pin  "reg(b(1).sg1.lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(14)} -pin  "reg(b(1).sg1.lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_15}
+load net {clk} -pin  "reg(b(1).sg1.lpi#1)" {clk} -attr xrf 44565 -attr oid 441 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(b(1).sg1.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(b(1).sg1.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {b(1).sg1.lpi#1(0)} -pin  "reg(b(1).sg1.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(1)} -pin  "reg(b(1).sg1.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(2)} -pin  "reg(b(1).sg1.lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(3)} -pin  "reg(b(1).sg1.lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(4)} -pin  "reg(b(1).sg1.lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(5)} -pin  "reg(b(1).sg1.lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(6)} -pin  "reg(b(1).sg1.lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(7)} -pin  "reg(b(1).sg1.lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(8)} -pin  "reg(b(1).sg1.lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(9)} -pin  "reg(b(1).sg1.lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(10)} -pin  "reg(b(1).sg1.lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(11)} -pin  "reg(b(1).sg1.lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(12)} -pin  "reg(b(1).sg1.lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(13)} -pin  "reg(b(1).sg1.lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(14)} -pin  "reg(b(1).sg1.lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load inst "regs.operator[]#22:mux" "mux(4,10)" "INTERFACE" -attr xrf 44566 -attr oid 442 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "regs.operator[]#22:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "regs.operator[]#22:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "regs.operator[]#22:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "regs.operator[]#22:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "regs.operator[]#22:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "regs.operator[]#22:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "regs.operator[]#22:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "regs.operator[]#22:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "regs.operator[]#22:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "regs.operator[]#22:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "regs.operator[]#22:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "regs.operator[]#22:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "regs.operator[]#22:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "regs.operator[]#22:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "regs.operator[]#22:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "regs.operator[]#22:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "regs.operator[]#22:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "regs.operator[]#22:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "regs.operator[]#22:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "regs.operator[]#22:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "regs.operator[]#22:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "regs.operator[]#22:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "regs.operator[]#22:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "regs.operator[]#22:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "regs.operator[]#22:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "regs.operator[]#22:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "regs.operator[]#22:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "regs.operator[]#22:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "regs.operator[]#22:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "regs.operator[]#22:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#22:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#22:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#22:mux.itm(0)} -pin  "regs.operator[]#22:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(1)} -pin  "regs.operator[]#22:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(2)} -pin  "regs.operator[]#22:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(3)} -pin  "regs.operator[]#22:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(4)} -pin  "regs.operator[]#22:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(5)} -pin  "regs.operator[]#22:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(6)} -pin  "regs.operator[]#22:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(7)} -pin  "regs.operator[]#22:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(8)} -pin  "regs.operator[]#22:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(9)} -pin  "regs.operator[]#22:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load inst "FRAME:for:mul#4" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 44567 -attr oid 443 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#22:mux.itm(0)} -pin  "FRAME:for:mul#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(1)} -pin  "FRAME:for:mul#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(2)} -pin  "FRAME:for:mul#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(3)} -pin  "FRAME:for:mul#4" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(4)} -pin  "FRAME:for:mul#4" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(5)} -pin  "FRAME:for:mul#4" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(6)} -pin  "FRAME:for:mul#4" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(7)} -pin  "FRAME:for:mul#4" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(8)} -pin  "FRAME:for:mul#4" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(9)} -pin  "FRAME:for:mul#4" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {FRAME:for:or#5.itm} -pin  "FRAME:for:mul#4" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#32}
+load net {FRAME:for:and#18.seb} -pin  "FRAME:for:mul#4" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#32}
+load net {FRAME:for:mul#4.itm(0)} -pin  "FRAME:for:mul#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(1)} -pin  "FRAME:for:mul#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(2)} -pin  "FRAME:for:mul#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(3)} -pin  "FRAME:for:mul#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(4)} -pin  "FRAME:for:mul#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(5)} -pin  "FRAME:for:mul#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(6)} -pin  "FRAME:for:mul#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(7)} -pin  "FRAME:for:mul#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(8)} -pin  "FRAME:for:mul#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(9)} -pin  "FRAME:for:mul#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(10)} -pin  "FRAME:for:mul#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load inst "FRAME:for:acc#27" "add(15,-1,11,1,15)" "INTERFACE" -attr xrf 44568 -attr oid 444 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27} -attr area 16.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {g(1).sg1.lpi#1.dfm(0)} -pin  "FRAME:for:acc#27" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(1)} -pin  "FRAME:for:acc#27" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(2)} -pin  "FRAME:for:acc#27" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(3)} -pin  "FRAME:for:acc#27" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(4)} -pin  "FRAME:for:acc#27" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(5)} -pin  "FRAME:for:acc#27" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(6)} -pin  "FRAME:for:acc#27" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(7)} -pin  "FRAME:for:acc#27" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(8)} -pin  "FRAME:for:acc#27" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(9)} -pin  "FRAME:for:acc#27" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(10)} -pin  "FRAME:for:acc#27" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(11)} -pin  "FRAME:for:acc#27" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(12)} -pin  "FRAME:for:acc#27" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(13)} -pin  "FRAME:for:acc#27" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(14)} -pin  "FRAME:for:acc#27" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {FRAME:for:mul#4.itm(0)} -pin  "FRAME:for:acc#27" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(1)} -pin  "FRAME:for:acc#27" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(2)} -pin  "FRAME:for:acc#27" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(3)} -pin  "FRAME:for:acc#27" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(4)} -pin  "FRAME:for:acc#27" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(5)} -pin  "FRAME:for:acc#27" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(6)} -pin  "FRAME:for:acc#27" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(7)} -pin  "FRAME:for:acc#27" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(8)} -pin  "FRAME:for:acc#27" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(9)} -pin  "FRAME:for:acc#27" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(10)} -pin  "FRAME:for:acc#27" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:acc#27.itm(0)} -pin  "FRAME:for:acc#27" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(1)} -pin  "FRAME:for:acc#27" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(2)} -pin  "FRAME:for:acc#27" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(3)} -pin  "FRAME:for:acc#27" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(4)} -pin  "FRAME:for:acc#27" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(5)} -pin  "FRAME:for:acc#27" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(6)} -pin  "FRAME:for:acc#27" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(7)} -pin  "FRAME:for:acc#27" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(8)} -pin  "FRAME:for:acc#27" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(9)} -pin  "FRAME:for:acc#27" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(10)} -pin  "FRAME:for:acc#27" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(11)} -pin  "FRAME:for:acc#27" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(12)} -pin  "FRAME:for:acc#27" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(13)} -pin  "FRAME:for:acc#27" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(14)} -pin  "FRAME:for:acc#27" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load inst "mux#9" "mux(2,15)" "INTERFACE" -attr xrf 44569 -attr oid 445 -attr vt d -attr @path {/sobel/sobel:core/mux#9} -attr area 13.792345 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(15,1,2)"
+load net {FRAME:for:acc#27.itm(0)} -pin  "mux#9" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(1)} -pin  "mux#9" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(2)} -pin  "mux#9" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(3)} -pin  "mux#9" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(4)} -pin  "mux#9" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(5)} -pin  "mux#9" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(6)} -pin  "mux#9" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(7)} -pin  "mux#9" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(8)} -pin  "mux#9" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(9)} -pin  "mux#9" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(10)} -pin  "mux#9" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(11)} -pin  "mux#9" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(12)} -pin  "mux#9" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(13)} -pin  "mux#9" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(14)} -pin  "mux#9" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {g(1).sg1.lpi#1.dfm(0)} -pin  "mux#9" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(1)} -pin  "mux#9" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(2)} -pin  "mux#9" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(3)} -pin  "mux#9" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(4)} -pin  "mux#9" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(5)} -pin  "mux#9" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(6)} -pin  "mux#9" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(7)} -pin  "mux#9" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(8)} -pin  "mux#9" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(9)} -pin  "mux#9" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(10)} -pin  "mux#9" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(11)} -pin  "mux#9" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(12)} -pin  "mux#9" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(13)} -pin  "mux#9" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(14)} -pin  "mux#9" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {or#4.cse} -pin  "mux#9" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#9.itm(0)} -pin  "mux#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(1)} -pin  "mux#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(2)} -pin  "mux#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(3)} -pin  "mux#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(4)} -pin  "mux#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(5)} -pin  "mux#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(6)} -pin  "mux#9" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(7)} -pin  "mux#9" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(8)} -pin  "mux#9" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(9)} -pin  "mux#9" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(10)} -pin  "mux#9" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(11)} -pin  "mux#9" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(12)} -pin  "mux#9" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(13)} -pin  "mux#9" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(14)} -pin  "mux#9" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load inst "reg(g(1).sg1.lpi#1)" "reg(15,1,1,-1,0)" "INTERFACE" -attr xrf 44570 -attr oid 446 -attr vt d -attr @path {/sobel/sobel:core/reg(g(1).sg1.lpi#1)}
+load net {mux#9.itm(0)} -pin  "reg(g(1).sg1.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(1)} -pin  "reg(g(1).sg1.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(2)} -pin  "reg(g(1).sg1.lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(3)} -pin  "reg(g(1).sg1.lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(4)} -pin  "reg(g(1).sg1.lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(5)} -pin  "reg(g(1).sg1.lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(6)} -pin  "reg(g(1).sg1.lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(7)} -pin  "reg(g(1).sg1.lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(8)} -pin  "reg(g(1).sg1.lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(9)} -pin  "reg(g(1).sg1.lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(10)} -pin  "reg(g(1).sg1.lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(11)} -pin  "reg(g(1).sg1.lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(12)} -pin  "reg(g(1).sg1.lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(13)} -pin  "reg(g(1).sg1.lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(14)} -pin  "reg(g(1).sg1.lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_15}
+load net {clk} -pin  "reg(g(1).sg1.lpi#1)" {clk} -attr xrf 44571 -attr oid 447 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(g(1).sg1.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(g(1).sg1.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {g(1).sg1.lpi#1(0)} -pin  "reg(g(1).sg1.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(1)} -pin  "reg(g(1).sg1.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(2)} -pin  "reg(g(1).sg1.lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(3)} -pin  "reg(g(1).sg1.lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(4)} -pin  "reg(g(1).sg1.lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(5)} -pin  "reg(g(1).sg1.lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(6)} -pin  "reg(g(1).sg1.lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(7)} -pin  "reg(g(1).sg1.lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(8)} -pin  "reg(g(1).sg1.lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(9)} -pin  "reg(g(1).sg1.lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(10)} -pin  "reg(g(1).sg1.lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(11)} -pin  "reg(g(1).sg1.lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(12)} -pin  "reg(g(1).sg1.lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(13)} -pin  "reg(g(1).sg1.lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(14)} -pin  "reg(g(1).sg1.lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load inst "regs.operator[]#21:mux" "mux(4,10)" "INTERFACE" -attr xrf 44572 -attr oid 448 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "regs.operator[]#21:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "regs.operator[]#21:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "regs.operator[]#21:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "regs.operator[]#21:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "regs.operator[]#21:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "regs.operator[]#21:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "regs.operator[]#21:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "regs.operator[]#21:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "regs.operator[]#21:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "regs.operator[]#21:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "regs.operator[]#21:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "regs.operator[]#21:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "regs.operator[]#21:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "regs.operator[]#21:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "regs.operator[]#21:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "regs.operator[]#21:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "regs.operator[]#21:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "regs.operator[]#21:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "regs.operator[]#21:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "regs.operator[]#21:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "regs.operator[]#21:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "regs.operator[]#21:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "regs.operator[]#21:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "regs.operator[]#21:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "regs.operator[]#21:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "regs.operator[]#21:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "regs.operator[]#21:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "regs.operator[]#21:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "regs.operator[]#21:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "regs.operator[]#21:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#21:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#21:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#21:mux.itm(0)} -pin  "regs.operator[]#21:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(1)} -pin  "regs.operator[]#21:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(2)} -pin  "regs.operator[]#21:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(3)} -pin  "regs.operator[]#21:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(4)} -pin  "regs.operator[]#21:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(5)} -pin  "regs.operator[]#21:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(6)} -pin  "regs.operator[]#21:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(7)} -pin  "regs.operator[]#21:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(8)} -pin  "regs.operator[]#21:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(9)} -pin  "regs.operator[]#21:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load inst "FRAME:for:mul#3" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 44573 -attr oid 449 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#21:mux.itm(0)} -pin  "FRAME:for:mul#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(1)} -pin  "FRAME:for:mul#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(2)} -pin  "FRAME:for:mul#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(3)} -pin  "FRAME:for:mul#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(4)} -pin  "FRAME:for:mul#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(5)} -pin  "FRAME:for:mul#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(6)} -pin  "FRAME:for:mul#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(7)} -pin  "FRAME:for:mul#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(8)} -pin  "FRAME:for:mul#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(9)} -pin  "FRAME:for:mul#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {FRAME:for:or#5.itm} -pin  "FRAME:for:mul#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#32}
+load net {FRAME:for:and#18.seb} -pin  "FRAME:for:mul#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#32}
+load net {FRAME:for:mul#3.itm(0)} -pin  "FRAME:for:mul#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(1)} -pin  "FRAME:for:mul#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(2)} -pin  "FRAME:for:mul#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(3)} -pin  "FRAME:for:mul#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(4)} -pin  "FRAME:for:mul#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(5)} -pin  "FRAME:for:mul#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(6)} -pin  "FRAME:for:mul#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(7)} -pin  "FRAME:for:mul#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(8)} -pin  "FRAME:for:mul#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(9)} -pin  "FRAME:for:mul#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(10)} -pin  "FRAME:for:mul#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load inst "FRAME:for:acc#26" "add(15,-1,11,1,15)" "INTERFACE" -attr xrf 44574 -attr oid 450 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26} -attr area 16.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {r(1).sg1.lpi#1.dfm(0)} -pin  "FRAME:for:acc#26" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(1)} -pin  "FRAME:for:acc#26" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(2)} -pin  "FRAME:for:acc#26" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(3)} -pin  "FRAME:for:acc#26" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(4)} -pin  "FRAME:for:acc#26" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(5)} -pin  "FRAME:for:acc#26" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(6)} -pin  "FRAME:for:acc#26" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(7)} -pin  "FRAME:for:acc#26" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(8)} -pin  "FRAME:for:acc#26" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(9)} -pin  "FRAME:for:acc#26" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(10)} -pin  "FRAME:for:acc#26" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(11)} -pin  "FRAME:for:acc#26" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(12)} -pin  "FRAME:for:acc#26" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(13)} -pin  "FRAME:for:acc#26" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(14)} -pin  "FRAME:for:acc#26" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {FRAME:for:mul#3.itm(0)} -pin  "FRAME:for:acc#26" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(1)} -pin  "FRAME:for:acc#26" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(2)} -pin  "FRAME:for:acc#26" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(3)} -pin  "FRAME:for:acc#26" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(4)} -pin  "FRAME:for:acc#26" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(5)} -pin  "FRAME:for:acc#26" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(6)} -pin  "FRAME:for:acc#26" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(7)} -pin  "FRAME:for:acc#26" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(8)} -pin  "FRAME:for:acc#26" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(9)} -pin  "FRAME:for:acc#26" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(10)} -pin  "FRAME:for:acc#26" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:acc#26.itm(0)} -pin  "FRAME:for:acc#26" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(1)} -pin  "FRAME:for:acc#26" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(2)} -pin  "FRAME:for:acc#26" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(3)} -pin  "FRAME:for:acc#26" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(4)} -pin  "FRAME:for:acc#26" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(5)} -pin  "FRAME:for:acc#26" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(6)} -pin  "FRAME:for:acc#26" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(7)} -pin  "FRAME:for:acc#26" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(8)} -pin  "FRAME:for:acc#26" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(9)} -pin  "FRAME:for:acc#26" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(10)} -pin  "FRAME:for:acc#26" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(11)} -pin  "FRAME:for:acc#26" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(12)} -pin  "FRAME:for:acc#26" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(13)} -pin  "FRAME:for:acc#26" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(14)} -pin  "FRAME:for:acc#26" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load inst "mux#10" "mux(2,15)" "INTERFACE" -attr xrf 44575 -attr oid 451 -attr vt d -attr @path {/sobel/sobel:core/mux#10} -attr area 13.792345 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(15,1,2)"
+load net {FRAME:for:acc#26.itm(0)} -pin  "mux#10" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(1)} -pin  "mux#10" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(2)} -pin  "mux#10" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(3)} -pin  "mux#10" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(4)} -pin  "mux#10" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(5)} -pin  "mux#10" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(6)} -pin  "mux#10" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(7)} -pin  "mux#10" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(8)} -pin  "mux#10" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(9)} -pin  "mux#10" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(10)} -pin  "mux#10" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(11)} -pin  "mux#10" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(12)} -pin  "mux#10" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(13)} -pin  "mux#10" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(14)} -pin  "mux#10" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {r(1).sg1.lpi#1.dfm(0)} -pin  "mux#10" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(1)} -pin  "mux#10" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(2)} -pin  "mux#10" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(3)} -pin  "mux#10" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(4)} -pin  "mux#10" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(5)} -pin  "mux#10" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(6)} -pin  "mux#10" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(7)} -pin  "mux#10" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(8)} -pin  "mux#10" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(9)} -pin  "mux#10" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(10)} -pin  "mux#10" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(11)} -pin  "mux#10" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(12)} -pin  "mux#10" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(13)} -pin  "mux#10" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(14)} -pin  "mux#10" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {or#4.cse} -pin  "mux#10" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#10.itm(0)} -pin  "mux#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(1)} -pin  "mux#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(2)} -pin  "mux#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(3)} -pin  "mux#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(4)} -pin  "mux#10" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(5)} -pin  "mux#10" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(6)} -pin  "mux#10" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(7)} -pin  "mux#10" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(8)} -pin  "mux#10" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(9)} -pin  "mux#10" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(10)} -pin  "mux#10" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(11)} -pin  "mux#10" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(12)} -pin  "mux#10" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(13)} -pin  "mux#10" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(14)} -pin  "mux#10" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load inst "reg(r(1).sg1.lpi#1)" "reg(15,1,1,-1,0)" "INTERFACE" -attr xrf 44576 -attr oid 452 -attr vt d -attr @path {/sobel/sobel:core/reg(r(1).sg1.lpi#1)}
+load net {mux#10.itm(0)} -pin  "reg(r(1).sg1.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(1)} -pin  "reg(r(1).sg1.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(2)} -pin  "reg(r(1).sg1.lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(3)} -pin  "reg(r(1).sg1.lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(4)} -pin  "reg(r(1).sg1.lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(5)} -pin  "reg(r(1).sg1.lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(6)} -pin  "reg(r(1).sg1.lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(7)} -pin  "reg(r(1).sg1.lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(8)} -pin  "reg(r(1).sg1.lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(9)} -pin  "reg(r(1).sg1.lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(10)} -pin  "reg(r(1).sg1.lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(11)} -pin  "reg(r(1).sg1.lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(12)} -pin  "reg(r(1).sg1.lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(13)} -pin  "reg(r(1).sg1.lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(14)} -pin  "reg(r(1).sg1.lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_15}
+load net {clk} -pin  "reg(r(1).sg1.lpi#1)" {clk} -attr xrf 44577 -attr oid 453 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(r(1).sg1.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(r(1).sg1.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {r(1).sg1.lpi#1(0)} -pin  "reg(r(1).sg1.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(1)} -pin  "reg(r(1).sg1.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(2)} -pin  "reg(r(1).sg1.lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(3)} -pin  "reg(r(1).sg1.lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(4)} -pin  "reg(r(1).sg1.lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(5)} -pin  "reg(r(1).sg1.lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(6)} -pin  "reg(r(1).sg1.lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(7)} -pin  "reg(r(1).sg1.lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(8)} -pin  "reg(r(1).sg1.lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(9)} -pin  "reg(r(1).sg1.lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(10)} -pin  "reg(r(1).sg1.lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(11)} -pin  "reg(r(1).sg1.lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(12)} -pin  "reg(r(1).sg1.lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(13)} -pin  "reg(r(1).sg1.lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(14)} -pin  "reg(r(1).sg1.lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load inst "mux#11" "mux(2,2)" "INTERFACE" -attr xrf 44578 -attr oid 454 -attr vt d -attr @path {/sobel/sobel:core/mux#11} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {i#6.sva#1(0)} -pin  "mux#11" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "mux#11" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.lpi#1.dfm(0)} -pin  "mux#11" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "mux#11" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {or#4.cse} -pin  "mux#11" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#11.itm(0)} -pin  "mux#11" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#11.itm}
+load net {mux#11.itm(1)} -pin  "mux#11" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#11.itm}
+load inst "reg(i#6.lpi#1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 44579 -attr oid 455 -attr vt d -attr @path {/sobel/sobel:core/reg(i#6.lpi#1)}
+load net {mux#11.itm(0)} -pin  "reg(i#6.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#11.itm}
+load net {mux#11.itm(1)} -pin  "reg(i#6.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#11.itm}
+load net {GND} -pin  "reg(i#6.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(i#6.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(i#6.lpi#1)" {clk} -attr xrf 44580 -attr oid 456 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(i#6.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(i#6.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {i#6.lpi#1(0)} -pin  "reg(i#6.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1}
+load net {i#6.lpi#1(1)} -pin  "reg(i#6.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1}
+load inst "regs.operator[]#26:mux" "mux(4,10)" "INTERFACE" -attr xrf 44581 -attr oid 457 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#26:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#26:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#26:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#26:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#26:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#26:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#26:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#26:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#26:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#26:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "regs.operator[]#26:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "regs.operator[]#26:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "regs.operator[]#26:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "regs.operator[]#26:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "regs.operator[]#26:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "regs.operator[]#26:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "regs.operator[]#26:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "regs.operator[]#26:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "regs.operator[]#26:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "regs.operator[]#26:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "regs.operator[]#26:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "regs.operator[]#26:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "regs.operator[]#26:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "regs.operator[]#26:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "regs.operator[]#26:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "regs.operator[]#26:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "regs.operator[]#26:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "regs.operator[]#26:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "regs.operator[]#26:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "regs.operator[]#26:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "regs.operator[]#26:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "regs.operator[]#26:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "regs.operator[]#26:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "regs.operator[]#26:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "regs.operator[]#26:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "regs.operator[]#26:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "regs.operator[]#26:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "regs.operator[]#26:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "regs.operator[]#26:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "regs.operator[]#26:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#26:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#26:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#26:mux.itm(0)} -pin  "regs.operator[]#26:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(1)} -pin  "regs.operator[]#26:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(2)} -pin  "regs.operator[]#26:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(3)} -pin  "regs.operator[]#26:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(4)} -pin  "regs.operator[]#26:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(5)} -pin  "regs.operator[]#26:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(6)} -pin  "regs.operator[]#26:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(7)} -pin  "regs.operator[]#26:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(8)} -pin  "regs.operator[]#26:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(9)} -pin  "regs.operator[]#26:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load inst "FRAME:for:mul#8" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 44582 -attr oid 458 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#26:mux.itm(0)} -pin  "FRAME:for:mul#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(1)} -pin  "FRAME:for:mul#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(2)} -pin  "FRAME:for:mul#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(3)} -pin  "FRAME:for:mul#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(4)} -pin  "FRAME:for:mul#8" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(5)} -pin  "FRAME:for:mul#8" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(6)} -pin  "FRAME:for:mul#8" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(7)} -pin  "FRAME:for:mul#8" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(8)} -pin  "FRAME:for:mul#8" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {regs.operator[]#26:mux.itm(9)} -pin  "FRAME:for:mul#8" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#26:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:mul#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:mul#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:mul#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:mul#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:mul#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:mul#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:mul#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:mul#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:mul#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:mul#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:mul#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load inst "FRAME:for:acc#14" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 44583 -attr oid 459 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {b(2).lpi#1.dfm(0)} -pin  "FRAME:for:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(1)} -pin  "FRAME:for:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(2)} -pin  "FRAME:for:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(3)} -pin  "FRAME:for:acc#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(4)} -pin  "FRAME:for:acc#14" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(5)} -pin  "FRAME:for:acc#14" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(6)} -pin  "FRAME:for:acc#14" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(7)} -pin  "FRAME:for:acc#14" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(8)} -pin  "FRAME:for:acc#14" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(9)} -pin  "FRAME:for:acc#14" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(10)} -pin  "FRAME:for:acc#14" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(11)} -pin  "FRAME:for:acc#14" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(12)} -pin  "FRAME:for:acc#14" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(13)} -pin  "FRAME:for:acc#14" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(14)} -pin  "FRAME:for:acc#14" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(15)} -pin  "FRAME:for:acc#14" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:acc#14" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:acc#14" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:acc#14" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:acc#14" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:acc#14" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:acc#14" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:acc#14" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:acc#14" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:acc#14.itm(0)} -pin  "FRAME:for:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(1)} -pin  "FRAME:for:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(2)} -pin  "FRAME:for:acc#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(3)} -pin  "FRAME:for:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(4)} -pin  "FRAME:for:acc#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(5)} -pin  "FRAME:for:acc#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(6)} -pin  "FRAME:for:acc#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(7)} -pin  "FRAME:for:acc#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(8)} -pin  "FRAME:for:acc#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(9)} -pin  "FRAME:for:acc#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(10)} -pin  "FRAME:for:acc#14" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(11)} -pin  "FRAME:for:acc#14" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(12)} -pin  "FRAME:for:acc#14" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(13)} -pin  "FRAME:for:acc#14" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(14)} -pin  "FRAME:for:acc#14" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(15)} -pin  "FRAME:for:acc#14" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load inst "mux#12" "mux(2,16)" "INTERFACE" -attr xrf 44584 -attr oid 460 -attr vt d -attr @path {/sobel/sobel:core/mux#12} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:acc#14.itm(0)} -pin  "mux#12" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(1)} -pin  "mux#12" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(2)} -pin  "mux#12" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(3)} -pin  "mux#12" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(4)} -pin  "mux#12" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(5)} -pin  "mux#12" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(6)} -pin  "mux#12" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(7)} -pin  "mux#12" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(8)} -pin  "mux#12" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(9)} -pin  "mux#12" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(10)} -pin  "mux#12" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(11)} -pin  "mux#12" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(12)} -pin  "mux#12" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(13)} -pin  "mux#12" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(14)} -pin  "mux#12" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(15)} -pin  "mux#12" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {b(2).sva#1(0)} -pin  "mux#12" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(1)} -pin  "mux#12" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(2)} -pin  "mux#12" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(3)} -pin  "mux#12" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(4)} -pin  "mux#12" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(5)} -pin  "mux#12" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(6)} -pin  "mux#12" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(7)} -pin  "mux#12" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(8)} -pin  "mux#12" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(9)} -pin  "mux#12" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(10)} -pin  "mux#12" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(11)} -pin  "mux#12" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(12)} -pin  "mux#12" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(13)} -pin  "mux#12" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(14)} -pin  "mux#12" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(15)} -pin  "mux#12" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {or#4.cse} -pin  "mux#12" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#12.itm(0)} -pin  "mux#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(1)} -pin  "mux#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(2)} -pin  "mux#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(3)} -pin  "mux#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(4)} -pin  "mux#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(5)} -pin  "mux#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(6)} -pin  "mux#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(7)} -pin  "mux#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(8)} -pin  "mux#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(9)} -pin  "mux#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(10)} -pin  "mux#12" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(11)} -pin  "mux#12" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(12)} -pin  "mux#12" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(13)} -pin  "mux#12" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(14)} -pin  "mux#12" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(15)} -pin  "mux#12" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load inst "reg(b(2).lpi#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 44585 -attr oid 461 -attr vt d -attr @path {/sobel/sobel:core/reg(b(2).lpi#1)}
+load net {mux#12.itm(0)} -pin  "reg(b(2).lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(1)} -pin  "reg(b(2).lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(2)} -pin  "reg(b(2).lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(3)} -pin  "reg(b(2).lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(4)} -pin  "reg(b(2).lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(5)} -pin  "reg(b(2).lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(6)} -pin  "reg(b(2).lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(7)} -pin  "reg(b(2).lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(8)} -pin  "reg(b(2).lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(9)} -pin  "reg(b(2).lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(10)} -pin  "reg(b(2).lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(11)} -pin  "reg(b(2).lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(12)} -pin  "reg(b(2).lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(13)} -pin  "reg(b(2).lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(14)} -pin  "reg(b(2).lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(15)} -pin  "reg(b(2).lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(b(2).lpi#1)" {clk} -attr xrf 44586 -attr oid 462 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(b(2).lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(b(2).lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {b(2).lpi#1(0)} -pin  "reg(b(2).lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(1)} -pin  "reg(b(2).lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(2)} -pin  "reg(b(2).lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(3)} -pin  "reg(b(2).lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(4)} -pin  "reg(b(2).lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(5)} -pin  "reg(b(2).lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(6)} -pin  "reg(b(2).lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(7)} -pin  "reg(b(2).lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(8)} -pin  "reg(b(2).lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(9)} -pin  "reg(b(2).lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(10)} -pin  "reg(b(2).lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(11)} -pin  "reg(b(2).lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(12)} -pin  "reg(b(2).lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(13)} -pin  "reg(b(2).lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(14)} -pin  "reg(b(2).lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(15)} -pin  "reg(b(2).lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load inst "regs.operator[]#20:mux" "mux(4,10)" "INTERFACE" -attr xrf 44587 -attr oid 463 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#20:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#20:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#20:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#20:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#20:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#20:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#20:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#20:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#20:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#20:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "regs.operator[]#20:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "regs.operator[]#20:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "regs.operator[]#20:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "regs.operator[]#20:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "regs.operator[]#20:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "regs.operator[]#20:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "regs.operator[]#20:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "regs.operator[]#20:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "regs.operator[]#20:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "regs.operator[]#20:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "regs.operator[]#20:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "regs.operator[]#20:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "regs.operator[]#20:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "regs.operator[]#20:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "regs.operator[]#20:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "regs.operator[]#20:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "regs.operator[]#20:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "regs.operator[]#20:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "regs.operator[]#20:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "regs.operator[]#20:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "regs.operator[]#20:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "regs.operator[]#20:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "regs.operator[]#20:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "regs.operator[]#20:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "regs.operator[]#20:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "regs.operator[]#20:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "regs.operator[]#20:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "regs.operator[]#20:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "regs.operator[]#20:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "regs.operator[]#20:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#20:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#20:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#20:mux.itm(0)} -pin  "regs.operator[]#20:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(1)} -pin  "regs.operator[]#20:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(2)} -pin  "regs.operator[]#20:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(3)} -pin  "regs.operator[]#20:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(4)} -pin  "regs.operator[]#20:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(5)} -pin  "regs.operator[]#20:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(6)} -pin  "regs.operator[]#20:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(7)} -pin  "regs.operator[]#20:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(8)} -pin  "regs.operator[]#20:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(9)} -pin  "regs.operator[]#20:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load inst "FRAME:for:mul#2" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 44588 -attr oid 464 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#20:mux.itm(0)} -pin  "FRAME:for:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(1)} -pin  "FRAME:for:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(2)} -pin  "FRAME:for:mul#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(3)} -pin  "FRAME:for:mul#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(4)} -pin  "FRAME:for:mul#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(5)} -pin  "FRAME:for:mul#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(6)} -pin  "FRAME:for:mul#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(7)} -pin  "FRAME:for:mul#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(8)} -pin  "FRAME:for:mul#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {regs.operator[]#20:mux.itm(9)} -pin  "FRAME:for:mul#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#20:mux.itm}
+load net {FRAME:for:or.itm} -pin  "FRAME:for:mul#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#30}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#30}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load inst "FRAME:for:acc#3" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 44589 -attr oid 465 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {b(0).lpi#1.dfm(0)} -pin  "FRAME:for:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(1)} -pin  "FRAME:for:acc#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(2)} -pin  "FRAME:for:acc#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(3)} -pin  "FRAME:for:acc#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(4)} -pin  "FRAME:for:acc#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(5)} -pin  "FRAME:for:acc#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(6)} -pin  "FRAME:for:acc#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(7)} -pin  "FRAME:for:acc#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(8)} -pin  "FRAME:for:acc#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(9)} -pin  "FRAME:for:acc#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(10)} -pin  "FRAME:for:acc#3" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(11)} -pin  "FRAME:for:acc#3" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(12)} -pin  "FRAME:for:acc#3" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(13)} -pin  "FRAME:for:acc#3" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(14)} -pin  "FRAME:for:acc#3" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(15)} -pin  "FRAME:for:acc#3" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:acc#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:acc#3" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:acc#3" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:acc#3" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:acc#3" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:acc#3" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:acc#3" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:acc#3" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:acc#3" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:acc#3" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:acc#3.itm(0)} -pin  "FRAME:for:acc#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(1)} -pin  "FRAME:for:acc#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(2)} -pin  "FRAME:for:acc#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(3)} -pin  "FRAME:for:acc#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(4)} -pin  "FRAME:for:acc#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(5)} -pin  "FRAME:for:acc#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(6)} -pin  "FRAME:for:acc#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(7)} -pin  "FRAME:for:acc#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(8)} -pin  "FRAME:for:acc#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(9)} -pin  "FRAME:for:acc#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(10)} -pin  "FRAME:for:acc#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(11)} -pin  "FRAME:for:acc#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(12)} -pin  "FRAME:for:acc#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(13)} -pin  "FRAME:for:acc#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(14)} -pin  "FRAME:for:acc#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(15)} -pin  "FRAME:for:acc#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load inst "mux#13" "mux(2,16)" "INTERFACE" -attr xrf 44590 -attr oid 466 -attr vt d -attr @path {/sobel/sobel:core/mux#13} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:acc#3.itm(0)} -pin  "mux#13" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(1)} -pin  "mux#13" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(2)} -pin  "mux#13" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(3)} -pin  "mux#13" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(4)} -pin  "mux#13" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(5)} -pin  "mux#13" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(6)} -pin  "mux#13" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(7)} -pin  "mux#13" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(8)} -pin  "mux#13" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(9)} -pin  "mux#13" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(10)} -pin  "mux#13" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(11)} -pin  "mux#13" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(12)} -pin  "mux#13" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(13)} -pin  "mux#13" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(14)} -pin  "mux#13" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(15)} -pin  "mux#13" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {b(0).sva#1(0)} -pin  "mux#13" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(1)} -pin  "mux#13" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(2)} -pin  "mux#13" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(3)} -pin  "mux#13" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(4)} -pin  "mux#13" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(5)} -pin  "mux#13" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(6)} -pin  "mux#13" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(7)} -pin  "mux#13" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(8)} -pin  "mux#13" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(9)} -pin  "mux#13" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(10)} -pin  "mux#13" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(11)} -pin  "mux#13" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(12)} -pin  "mux#13" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(13)} -pin  "mux#13" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(14)} -pin  "mux#13" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(15)} -pin  "mux#13" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {or#4.cse} -pin  "mux#13" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#13.itm(0)} -pin  "mux#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(1)} -pin  "mux#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(2)} -pin  "mux#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(3)} -pin  "mux#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(4)} -pin  "mux#13" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(5)} -pin  "mux#13" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(6)} -pin  "mux#13" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(7)} -pin  "mux#13" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(8)} -pin  "mux#13" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(9)} -pin  "mux#13" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(10)} -pin  "mux#13" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(11)} -pin  "mux#13" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(12)} -pin  "mux#13" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(13)} -pin  "mux#13" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(14)} -pin  "mux#13" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(15)} -pin  "mux#13" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load inst "reg(b(0).lpi#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 44591 -attr oid 467 -attr vt d -attr @path {/sobel/sobel:core/reg(b(0).lpi#1)}
+load net {mux#13.itm(0)} -pin  "reg(b(0).lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(1)} -pin  "reg(b(0).lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(2)} -pin  "reg(b(0).lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(3)} -pin  "reg(b(0).lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(4)} -pin  "reg(b(0).lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(5)} -pin  "reg(b(0).lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(6)} -pin  "reg(b(0).lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(7)} -pin  "reg(b(0).lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(8)} -pin  "reg(b(0).lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(9)} -pin  "reg(b(0).lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(10)} -pin  "reg(b(0).lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(11)} -pin  "reg(b(0).lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(12)} -pin  "reg(b(0).lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(13)} -pin  "reg(b(0).lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(14)} -pin  "reg(b(0).lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(15)} -pin  "reg(b(0).lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(b(0).lpi#1)" {clk} -attr xrf 44592 -attr oid 468 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(b(0).lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(b(0).lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {b(0).lpi#1(0)} -pin  "reg(b(0).lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(1)} -pin  "reg(b(0).lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(2)} -pin  "reg(b(0).lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(3)} -pin  "reg(b(0).lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(4)} -pin  "reg(b(0).lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(5)} -pin  "reg(b(0).lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(6)} -pin  "reg(b(0).lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(7)} -pin  "reg(b(0).lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(8)} -pin  "reg(b(0).lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(9)} -pin  "reg(b(0).lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(10)} -pin  "reg(b(0).lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(11)} -pin  "reg(b(0).lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(12)} -pin  "reg(b(0).lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(13)} -pin  "reg(b(0).lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(14)} -pin  "reg(b(0).lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(15)} -pin  "reg(b(0).lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load inst "regs.operator[]#25:mux" "mux(4,10)" "INTERFACE" -attr xrf 44593 -attr oid 469 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#25:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#25:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#25:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#25:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#25:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#25:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#25:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#25:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#25:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#25:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "regs.operator[]#25:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "regs.operator[]#25:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "regs.operator[]#25:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "regs.operator[]#25:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "regs.operator[]#25:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "regs.operator[]#25:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "regs.operator[]#25:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "regs.operator[]#25:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "regs.operator[]#25:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "regs.operator[]#25:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "regs.operator[]#25:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "regs.operator[]#25:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "regs.operator[]#25:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "regs.operator[]#25:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "regs.operator[]#25:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "regs.operator[]#25:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "regs.operator[]#25:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "regs.operator[]#25:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "regs.operator[]#25:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "regs.operator[]#25:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "regs.operator[]#25:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "regs.operator[]#25:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "regs.operator[]#25:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "regs.operator[]#25:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "regs.operator[]#25:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "regs.operator[]#25:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "regs.operator[]#25:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "regs.operator[]#25:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "regs.operator[]#25:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "regs.operator[]#25:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#25:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#25:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#25:mux.itm(0)} -pin  "regs.operator[]#25:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(1)} -pin  "regs.operator[]#25:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(2)} -pin  "regs.operator[]#25:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(3)} -pin  "regs.operator[]#25:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(4)} -pin  "regs.operator[]#25:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(5)} -pin  "regs.operator[]#25:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(6)} -pin  "regs.operator[]#25:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(7)} -pin  "regs.operator[]#25:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(8)} -pin  "regs.operator[]#25:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(9)} -pin  "regs.operator[]#25:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load inst "FRAME:for:mul#7" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 44594 -attr oid 470 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#25:mux.itm(0)} -pin  "FRAME:for:mul#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(1)} -pin  "FRAME:for:mul#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(2)} -pin  "FRAME:for:mul#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(3)} -pin  "FRAME:for:mul#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(4)} -pin  "FRAME:for:mul#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(5)} -pin  "FRAME:for:mul#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(6)} -pin  "FRAME:for:mul#7" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(7)} -pin  "FRAME:for:mul#7" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(8)} -pin  "FRAME:for:mul#7" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {regs.operator[]#25:mux.itm(9)} -pin  "FRAME:for:mul#7" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#25:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:mul#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:mul#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:mul#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:mul#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:mul#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:mul#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:mul#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:mul#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:mul#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:mul#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:mul#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load inst "FRAME:for:acc#12" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 44595 -attr oid 471 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {g(2).lpi#1.dfm(0)} -pin  "FRAME:for:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(1)} -pin  "FRAME:for:acc#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(2)} -pin  "FRAME:for:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(3)} -pin  "FRAME:for:acc#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(4)} -pin  "FRAME:for:acc#12" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(5)} -pin  "FRAME:for:acc#12" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(6)} -pin  "FRAME:for:acc#12" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(7)} -pin  "FRAME:for:acc#12" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(8)} -pin  "FRAME:for:acc#12" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(9)} -pin  "FRAME:for:acc#12" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(10)} -pin  "FRAME:for:acc#12" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(11)} -pin  "FRAME:for:acc#12" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(12)} -pin  "FRAME:for:acc#12" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(13)} -pin  "FRAME:for:acc#12" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(14)} -pin  "FRAME:for:acc#12" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(15)} -pin  "FRAME:for:acc#12" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:acc#12" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:acc#12" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:acc#12" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:acc#12" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:acc#12" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:acc#12" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:acc#12" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:acc#12" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:acc#12" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:acc#12.itm(0)} -pin  "FRAME:for:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(1)} -pin  "FRAME:for:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(2)} -pin  "FRAME:for:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(3)} -pin  "FRAME:for:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(4)} -pin  "FRAME:for:acc#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(5)} -pin  "FRAME:for:acc#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(6)} -pin  "FRAME:for:acc#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(7)} -pin  "FRAME:for:acc#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(8)} -pin  "FRAME:for:acc#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(9)} -pin  "FRAME:for:acc#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(10)} -pin  "FRAME:for:acc#12" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(11)} -pin  "FRAME:for:acc#12" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(12)} -pin  "FRAME:for:acc#12" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(13)} -pin  "FRAME:for:acc#12" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(14)} -pin  "FRAME:for:acc#12" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(15)} -pin  "FRAME:for:acc#12" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load inst "mux#14" "mux(2,16)" "INTERFACE" -attr xrf 44596 -attr oid 472 -attr vt d -attr @path {/sobel/sobel:core/mux#14} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:acc#12.itm(0)} -pin  "mux#14" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(1)} -pin  "mux#14" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(2)} -pin  "mux#14" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(3)} -pin  "mux#14" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(4)} -pin  "mux#14" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(5)} -pin  "mux#14" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(6)} -pin  "mux#14" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(7)} -pin  "mux#14" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(8)} -pin  "mux#14" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(9)} -pin  "mux#14" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(10)} -pin  "mux#14" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(11)} -pin  "mux#14" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(12)} -pin  "mux#14" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(13)} -pin  "mux#14" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(14)} -pin  "mux#14" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(15)} -pin  "mux#14" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {g(2).sva#1(0)} -pin  "mux#14" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(1)} -pin  "mux#14" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(2)} -pin  "mux#14" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(3)} -pin  "mux#14" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(4)} -pin  "mux#14" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(5)} -pin  "mux#14" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(6)} -pin  "mux#14" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(7)} -pin  "mux#14" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(8)} -pin  "mux#14" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(9)} -pin  "mux#14" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(10)} -pin  "mux#14" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(11)} -pin  "mux#14" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(12)} -pin  "mux#14" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(13)} -pin  "mux#14" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(14)} -pin  "mux#14" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(15)} -pin  "mux#14" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {or#4.cse} -pin  "mux#14" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#14.itm(0)} -pin  "mux#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(1)} -pin  "mux#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(2)} -pin  "mux#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(3)} -pin  "mux#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(4)} -pin  "mux#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(5)} -pin  "mux#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(6)} -pin  "mux#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(7)} -pin  "mux#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(8)} -pin  "mux#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(9)} -pin  "mux#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(10)} -pin  "mux#14" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(11)} -pin  "mux#14" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(12)} -pin  "mux#14" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(13)} -pin  "mux#14" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(14)} -pin  "mux#14" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(15)} -pin  "mux#14" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load inst "reg(g(2).lpi#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 44597 -attr oid 473 -attr vt d -attr @path {/sobel/sobel:core/reg(g(2).lpi#1)}
+load net {mux#14.itm(0)} -pin  "reg(g(2).lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(1)} -pin  "reg(g(2).lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(2)} -pin  "reg(g(2).lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(3)} -pin  "reg(g(2).lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(4)} -pin  "reg(g(2).lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(5)} -pin  "reg(g(2).lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(6)} -pin  "reg(g(2).lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(7)} -pin  "reg(g(2).lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(8)} -pin  "reg(g(2).lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(9)} -pin  "reg(g(2).lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(10)} -pin  "reg(g(2).lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(11)} -pin  "reg(g(2).lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(12)} -pin  "reg(g(2).lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(13)} -pin  "reg(g(2).lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(14)} -pin  "reg(g(2).lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(15)} -pin  "reg(g(2).lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(g(2).lpi#1)" {clk} -attr xrf 44598 -attr oid 474 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(g(2).lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(g(2).lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {g(2).lpi#1(0)} -pin  "reg(g(2).lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(1)} -pin  "reg(g(2).lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(2)} -pin  "reg(g(2).lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(3)} -pin  "reg(g(2).lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(4)} -pin  "reg(g(2).lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(5)} -pin  "reg(g(2).lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(6)} -pin  "reg(g(2).lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(7)} -pin  "reg(g(2).lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(8)} -pin  "reg(g(2).lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(9)} -pin  "reg(g(2).lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(10)} -pin  "reg(g(2).lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(11)} -pin  "reg(g(2).lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(12)} -pin  "reg(g(2).lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(13)} -pin  "reg(g(2).lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(14)} -pin  "reg(g(2).lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(15)} -pin  "reg(g(2).lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load inst "regs.operator[]#19:mux" "mux(4,10)" "INTERFACE" -attr xrf 44599 -attr oid 475 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#19:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#19:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#19:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#19:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#19:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#19:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#19:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#19:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#19:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#19:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "regs.operator[]#19:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "regs.operator[]#19:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "regs.operator[]#19:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "regs.operator[]#19:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "regs.operator[]#19:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "regs.operator[]#19:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "regs.operator[]#19:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "regs.operator[]#19:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "regs.operator[]#19:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "regs.operator[]#19:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "regs.operator[]#19:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "regs.operator[]#19:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "regs.operator[]#19:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "regs.operator[]#19:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "regs.operator[]#19:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "regs.operator[]#19:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "regs.operator[]#19:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "regs.operator[]#19:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "regs.operator[]#19:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "regs.operator[]#19:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "regs.operator[]#19:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "regs.operator[]#19:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "regs.operator[]#19:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "regs.operator[]#19:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "regs.operator[]#19:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "regs.operator[]#19:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "regs.operator[]#19:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "regs.operator[]#19:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "regs.operator[]#19:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "regs.operator[]#19:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#19:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#19:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#19:mux.itm(0)} -pin  "regs.operator[]#19:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(1)} -pin  "regs.operator[]#19:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(2)} -pin  "regs.operator[]#19:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(3)} -pin  "regs.operator[]#19:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(4)} -pin  "regs.operator[]#19:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(5)} -pin  "regs.operator[]#19:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(6)} -pin  "regs.operator[]#19:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(7)} -pin  "regs.operator[]#19:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(8)} -pin  "regs.operator[]#19:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(9)} -pin  "regs.operator[]#19:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load inst "FRAME:for:mul#1" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 44600 -attr oid 476 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#19:mux.itm(0)} -pin  "FRAME:for:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(1)} -pin  "FRAME:for:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(2)} -pin  "FRAME:for:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(3)} -pin  "FRAME:for:mul#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(4)} -pin  "FRAME:for:mul#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(5)} -pin  "FRAME:for:mul#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(6)} -pin  "FRAME:for:mul#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(7)} -pin  "FRAME:for:mul#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(8)} -pin  "FRAME:for:mul#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {regs.operator[]#19:mux.itm(9)} -pin  "FRAME:for:mul#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#19:mux.itm}
+load net {FRAME:for:or.itm} -pin  "FRAME:for:mul#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#30}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#1" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#30}
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:mul#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:mul#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load inst "FRAME:for:acc#2" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 44601 -attr oid 477 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {g(0).lpi#1.dfm(0)} -pin  "FRAME:for:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(1)} -pin  "FRAME:for:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(2)} -pin  "FRAME:for:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(3)} -pin  "FRAME:for:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(4)} -pin  "FRAME:for:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(5)} -pin  "FRAME:for:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(6)} -pin  "FRAME:for:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(7)} -pin  "FRAME:for:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(8)} -pin  "FRAME:for:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(9)} -pin  "FRAME:for:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(10)} -pin  "FRAME:for:acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(11)} -pin  "FRAME:for:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(12)} -pin  "FRAME:for:acc#2" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(13)} -pin  "FRAME:for:acc#2" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(14)} -pin  "FRAME:for:acc#2" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(15)} -pin  "FRAME:for:acc#2" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:acc#2.itm(0)} -pin  "FRAME:for:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(1)} -pin  "FRAME:for:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(2)} -pin  "FRAME:for:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(3)} -pin  "FRAME:for:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(4)} -pin  "FRAME:for:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(5)} -pin  "FRAME:for:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(6)} -pin  "FRAME:for:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(7)} -pin  "FRAME:for:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(8)} -pin  "FRAME:for:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(9)} -pin  "FRAME:for:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(10)} -pin  "FRAME:for:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(11)} -pin  "FRAME:for:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(12)} -pin  "FRAME:for:acc#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(13)} -pin  "FRAME:for:acc#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(14)} -pin  "FRAME:for:acc#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(15)} -pin  "FRAME:for:acc#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load inst "mux#15" "mux(2,16)" "INTERFACE" -attr xrf 44602 -attr oid 478 -attr vt d -attr @path {/sobel/sobel:core/mux#15} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:acc#2.itm(0)} -pin  "mux#15" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(1)} -pin  "mux#15" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(2)} -pin  "mux#15" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(3)} -pin  "mux#15" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(4)} -pin  "mux#15" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(5)} -pin  "mux#15" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(6)} -pin  "mux#15" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(7)} -pin  "mux#15" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(8)} -pin  "mux#15" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(9)} -pin  "mux#15" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(10)} -pin  "mux#15" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(11)} -pin  "mux#15" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(12)} -pin  "mux#15" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(13)} -pin  "mux#15" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(14)} -pin  "mux#15" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(15)} -pin  "mux#15" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {g(0).sva#1(0)} -pin  "mux#15" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(1)} -pin  "mux#15" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(2)} -pin  "mux#15" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(3)} -pin  "mux#15" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(4)} -pin  "mux#15" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(5)} -pin  "mux#15" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(6)} -pin  "mux#15" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(7)} -pin  "mux#15" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(8)} -pin  "mux#15" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(9)} -pin  "mux#15" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(10)} -pin  "mux#15" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(11)} -pin  "mux#15" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(12)} -pin  "mux#15" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(13)} -pin  "mux#15" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(14)} -pin  "mux#15" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(15)} -pin  "mux#15" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {or#4.cse} -pin  "mux#15" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#15.itm(0)} -pin  "mux#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(1)} -pin  "mux#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(2)} -pin  "mux#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(3)} -pin  "mux#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(4)} -pin  "mux#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(5)} -pin  "mux#15" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(6)} -pin  "mux#15" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(7)} -pin  "mux#15" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(8)} -pin  "mux#15" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(9)} -pin  "mux#15" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(10)} -pin  "mux#15" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(11)} -pin  "mux#15" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(12)} -pin  "mux#15" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(13)} -pin  "mux#15" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(14)} -pin  "mux#15" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(15)} -pin  "mux#15" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load inst "reg(g(0).lpi#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 44603 -attr oid 479 -attr vt d -attr @path {/sobel/sobel:core/reg(g(0).lpi#1)}
+load net {mux#15.itm(0)} -pin  "reg(g(0).lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(1)} -pin  "reg(g(0).lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(2)} -pin  "reg(g(0).lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(3)} -pin  "reg(g(0).lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(4)} -pin  "reg(g(0).lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(5)} -pin  "reg(g(0).lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(6)} -pin  "reg(g(0).lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(7)} -pin  "reg(g(0).lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(8)} -pin  "reg(g(0).lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(9)} -pin  "reg(g(0).lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(10)} -pin  "reg(g(0).lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(11)} -pin  "reg(g(0).lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(12)} -pin  "reg(g(0).lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(13)} -pin  "reg(g(0).lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(14)} -pin  "reg(g(0).lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(15)} -pin  "reg(g(0).lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(g(0).lpi#1)" {clk} -attr xrf 44604 -attr oid 480 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(g(0).lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(g(0).lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {g(0).lpi#1(0)} -pin  "reg(g(0).lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(1)} -pin  "reg(g(0).lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(2)} -pin  "reg(g(0).lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(3)} -pin  "reg(g(0).lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(4)} -pin  "reg(g(0).lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(5)} -pin  "reg(g(0).lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(6)} -pin  "reg(g(0).lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(7)} -pin  "reg(g(0).lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(8)} -pin  "reg(g(0).lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(9)} -pin  "reg(g(0).lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(10)} -pin  "reg(g(0).lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(11)} -pin  "reg(g(0).lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(12)} -pin  "reg(g(0).lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(13)} -pin  "reg(g(0).lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(14)} -pin  "reg(g(0).lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(15)} -pin  "reg(g(0).lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load inst "regs.operator[]#24:mux" "mux(4,10)" "INTERFACE" -attr xrf 44605 -attr oid 481 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#24:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#24:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#24:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#24:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#24:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#24:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#24:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#24:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#24:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#24:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "regs.operator[]#24:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "regs.operator[]#24:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "regs.operator[]#24:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "regs.operator[]#24:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "regs.operator[]#24:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "regs.operator[]#24:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "regs.operator[]#24:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "regs.operator[]#24:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "regs.operator[]#24:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "regs.operator[]#24:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "regs.operator[]#24:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "regs.operator[]#24:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "regs.operator[]#24:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "regs.operator[]#24:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "regs.operator[]#24:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "regs.operator[]#24:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "regs.operator[]#24:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "regs.operator[]#24:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "regs.operator[]#24:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "regs.operator[]#24:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "regs.operator[]#24:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "regs.operator[]#24:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "regs.operator[]#24:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "regs.operator[]#24:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "regs.operator[]#24:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "regs.operator[]#24:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "regs.operator[]#24:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "regs.operator[]#24:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "regs.operator[]#24:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "regs.operator[]#24:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#24:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#24:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#24:mux.itm(0)} -pin  "regs.operator[]#24:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(1)} -pin  "regs.operator[]#24:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(2)} -pin  "regs.operator[]#24:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(3)} -pin  "regs.operator[]#24:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(4)} -pin  "regs.operator[]#24:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(5)} -pin  "regs.operator[]#24:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(6)} -pin  "regs.operator[]#24:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(7)} -pin  "regs.operator[]#24:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(8)} -pin  "regs.operator[]#24:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(9)} -pin  "regs.operator[]#24:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load inst "FRAME:for:mul#6" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 44606 -attr oid 482 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#24:mux.itm(0)} -pin  "FRAME:for:mul#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(1)} -pin  "FRAME:for:mul#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(2)} -pin  "FRAME:for:mul#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(3)} -pin  "FRAME:for:mul#6" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(4)} -pin  "FRAME:for:mul#6" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(5)} -pin  "FRAME:for:mul#6" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(6)} -pin  "FRAME:for:mul#6" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(7)} -pin  "FRAME:for:mul#6" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(8)} -pin  "FRAME:for:mul#6" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {regs.operator[]#24:mux.itm(9)} -pin  "FRAME:for:mul#6" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#24:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:mul#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:mul#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:mul#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:mul#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:mul#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:mul#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:mul#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:mul#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:mul#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:mul#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:mul#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load inst "FRAME:for:acc#10" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 44607 -attr oid 483 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {r(2).lpi#1.dfm(0)} -pin  "FRAME:for:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(1)} -pin  "FRAME:for:acc#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(2)} -pin  "FRAME:for:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(3)} -pin  "FRAME:for:acc#10" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(4)} -pin  "FRAME:for:acc#10" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(5)} -pin  "FRAME:for:acc#10" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(6)} -pin  "FRAME:for:acc#10" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(7)} -pin  "FRAME:for:acc#10" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(8)} -pin  "FRAME:for:acc#10" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(9)} -pin  "FRAME:for:acc#10" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(10)} -pin  "FRAME:for:acc#10" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(11)} -pin  "FRAME:for:acc#10" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(12)} -pin  "FRAME:for:acc#10" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(13)} -pin  "FRAME:for:acc#10" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(14)} -pin  "FRAME:for:acc#10" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(15)} -pin  "FRAME:for:acc#10" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:acc#10" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:acc#10" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:acc#10" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:acc#10" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:acc#10" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:acc#10" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:acc#10" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:acc#10" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:acc#10" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:acc#10.itm(0)} -pin  "FRAME:for:acc#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(1)} -pin  "FRAME:for:acc#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(2)} -pin  "FRAME:for:acc#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(3)} -pin  "FRAME:for:acc#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(4)} -pin  "FRAME:for:acc#10" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(5)} -pin  "FRAME:for:acc#10" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(6)} -pin  "FRAME:for:acc#10" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(7)} -pin  "FRAME:for:acc#10" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(8)} -pin  "FRAME:for:acc#10" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(9)} -pin  "FRAME:for:acc#10" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(10)} -pin  "FRAME:for:acc#10" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(11)} -pin  "FRAME:for:acc#10" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(12)} -pin  "FRAME:for:acc#10" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(13)} -pin  "FRAME:for:acc#10" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(14)} -pin  "FRAME:for:acc#10" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(15)} -pin  "FRAME:for:acc#10" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load inst "mux#16" "mux(2,16)" "INTERFACE" -attr xrf 44608 -attr oid 484 -attr vt d -attr @path {/sobel/sobel:core/mux#16} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:acc#10.itm(0)} -pin  "mux#16" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(1)} -pin  "mux#16" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(2)} -pin  "mux#16" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(3)} -pin  "mux#16" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(4)} -pin  "mux#16" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(5)} -pin  "mux#16" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(6)} -pin  "mux#16" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(7)} -pin  "mux#16" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(8)} -pin  "mux#16" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(9)} -pin  "mux#16" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(10)} -pin  "mux#16" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(11)} -pin  "mux#16" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(12)} -pin  "mux#16" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(13)} -pin  "mux#16" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(14)} -pin  "mux#16" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(15)} -pin  "mux#16" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {r(2).sva#1(0)} -pin  "mux#16" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(1)} -pin  "mux#16" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(2)} -pin  "mux#16" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(3)} -pin  "mux#16" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(4)} -pin  "mux#16" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(5)} -pin  "mux#16" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(6)} -pin  "mux#16" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(7)} -pin  "mux#16" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(8)} -pin  "mux#16" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(9)} -pin  "mux#16" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(10)} -pin  "mux#16" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(11)} -pin  "mux#16" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(12)} -pin  "mux#16" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(13)} -pin  "mux#16" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(14)} -pin  "mux#16" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(15)} -pin  "mux#16" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {or#4.cse} -pin  "mux#16" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#16.itm(0)} -pin  "mux#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(1)} -pin  "mux#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(2)} -pin  "mux#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(3)} -pin  "mux#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(4)} -pin  "mux#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(5)} -pin  "mux#16" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(6)} -pin  "mux#16" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(7)} -pin  "mux#16" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(8)} -pin  "mux#16" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(9)} -pin  "mux#16" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(10)} -pin  "mux#16" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(11)} -pin  "mux#16" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(12)} -pin  "mux#16" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(13)} -pin  "mux#16" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(14)} -pin  "mux#16" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(15)} -pin  "mux#16" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load inst "reg(r(2).lpi#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 44609 -attr oid 485 -attr vt d -attr @path {/sobel/sobel:core/reg(r(2).lpi#1)}
+load net {mux#16.itm(0)} -pin  "reg(r(2).lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(1)} -pin  "reg(r(2).lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(2)} -pin  "reg(r(2).lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(3)} -pin  "reg(r(2).lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(4)} -pin  "reg(r(2).lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(5)} -pin  "reg(r(2).lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(6)} -pin  "reg(r(2).lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(7)} -pin  "reg(r(2).lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(8)} -pin  "reg(r(2).lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(9)} -pin  "reg(r(2).lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(10)} -pin  "reg(r(2).lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(11)} -pin  "reg(r(2).lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(12)} -pin  "reg(r(2).lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(13)} -pin  "reg(r(2).lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(14)} -pin  "reg(r(2).lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(15)} -pin  "reg(r(2).lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(r(2).lpi#1)" {clk} -attr xrf 44610 -attr oid 486 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(r(2).lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(r(2).lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {r(2).lpi#1(0)} -pin  "reg(r(2).lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(1)} -pin  "reg(r(2).lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(2)} -pin  "reg(r(2).lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(3)} -pin  "reg(r(2).lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(4)} -pin  "reg(r(2).lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(5)} -pin  "reg(r(2).lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(6)} -pin  "reg(r(2).lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(7)} -pin  "reg(r(2).lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(8)} -pin  "reg(r(2).lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(9)} -pin  "reg(r(2).lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(10)} -pin  "reg(r(2).lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(11)} -pin  "reg(r(2).lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(12)} -pin  "reg(r(2).lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(13)} -pin  "reg(r(2).lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(14)} -pin  "reg(r(2).lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(15)} -pin  "reg(r(2).lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load inst "regs.operator[]#18:mux" "mux(4,10)" "INTERFACE" -attr xrf 44611 -attr oid 487 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#18:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#18:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#18:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#18:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#18:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#18:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#18:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#18:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#18:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#18:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "regs.operator[]#18:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "regs.operator[]#18:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "regs.operator[]#18:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "regs.operator[]#18:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "regs.operator[]#18:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "regs.operator[]#18:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "regs.operator[]#18:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "regs.operator[]#18:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "regs.operator[]#18:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "regs.operator[]#18:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "regs.operator[]#18:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "regs.operator[]#18:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "regs.operator[]#18:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "regs.operator[]#18:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "regs.operator[]#18:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "regs.operator[]#18:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "regs.operator[]#18:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "regs.operator[]#18:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "regs.operator[]#18:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "regs.operator[]#18:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "regs.operator[]#18:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "regs.operator[]#18:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "regs.operator[]#18:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "regs.operator[]#18:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "regs.operator[]#18:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "regs.operator[]#18:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "regs.operator[]#18:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "regs.operator[]#18:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "regs.operator[]#18:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "regs.operator[]#18:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#18:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#18:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#18:mux.itm(0)} -pin  "regs.operator[]#18:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(1)} -pin  "regs.operator[]#18:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(2)} -pin  "regs.operator[]#18:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(3)} -pin  "regs.operator[]#18:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(4)} -pin  "regs.operator[]#18:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(5)} -pin  "regs.operator[]#18:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(6)} -pin  "regs.operator[]#18:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(7)} -pin  "regs.operator[]#18:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(8)} -pin  "regs.operator[]#18:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(9)} -pin  "regs.operator[]#18:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load inst "FRAME:for:mul" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 44612 -attr oid 488 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#18:mux.itm(0)} -pin  "FRAME:for:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(1)} -pin  "FRAME:for:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(2)} -pin  "FRAME:for:mul" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(3)} -pin  "FRAME:for:mul" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(4)} -pin  "FRAME:for:mul" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(5)} -pin  "FRAME:for:mul" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(6)} -pin  "FRAME:for:mul" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(7)} -pin  "FRAME:for:mul" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(8)} -pin  "FRAME:for:mul" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {regs.operator[]#18:mux.itm(9)} -pin  "FRAME:for:mul" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#18:mux.itm}
+load net {FRAME:for:or.itm} -pin  "FRAME:for:mul" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#30}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#30}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load inst "FRAME:for:acc#1" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 44613 -attr oid 489 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {r(0).lpi#1.dfm(0)} -pin  "FRAME:for:acc#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(1)} -pin  "FRAME:for:acc#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(2)} -pin  "FRAME:for:acc#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(3)} -pin  "FRAME:for:acc#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(4)} -pin  "FRAME:for:acc#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(5)} -pin  "FRAME:for:acc#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(6)} -pin  "FRAME:for:acc#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(7)} -pin  "FRAME:for:acc#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(8)} -pin  "FRAME:for:acc#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(9)} -pin  "FRAME:for:acc#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(10)} -pin  "FRAME:for:acc#1" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(11)} -pin  "FRAME:for:acc#1" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(12)} -pin  "FRAME:for:acc#1" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(13)} -pin  "FRAME:for:acc#1" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(14)} -pin  "FRAME:for:acc#1" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(15)} -pin  "FRAME:for:acc#1" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:acc#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:acc#1" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:acc#1" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:acc#1" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:acc#1" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:acc#1" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:acc#1" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:acc#1" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:acc#1" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:acc#1" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:acc#1" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:acc#1.itm(0)} -pin  "FRAME:for:acc#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(1)} -pin  "FRAME:for:acc#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(2)} -pin  "FRAME:for:acc#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(3)} -pin  "FRAME:for:acc#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(4)} -pin  "FRAME:for:acc#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(5)} -pin  "FRAME:for:acc#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(6)} -pin  "FRAME:for:acc#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(7)} -pin  "FRAME:for:acc#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(8)} -pin  "FRAME:for:acc#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(9)} -pin  "FRAME:for:acc#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(10)} -pin  "FRAME:for:acc#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(11)} -pin  "FRAME:for:acc#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(12)} -pin  "FRAME:for:acc#1" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(13)} -pin  "FRAME:for:acc#1" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(14)} -pin  "FRAME:for:acc#1" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(15)} -pin  "FRAME:for:acc#1" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load inst "mux#17" "mux(2,16)" "INTERFACE" -attr xrf 44614 -attr oid 490 -attr vt d -attr @path {/sobel/sobel:core/mux#17} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:acc#1.itm(0)} -pin  "mux#17" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(1)} -pin  "mux#17" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(2)} -pin  "mux#17" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(3)} -pin  "mux#17" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(4)} -pin  "mux#17" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(5)} -pin  "mux#17" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(6)} -pin  "mux#17" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(7)} -pin  "mux#17" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(8)} -pin  "mux#17" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(9)} -pin  "mux#17" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(10)} -pin  "mux#17" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(11)} -pin  "mux#17" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(12)} -pin  "mux#17" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(13)} -pin  "mux#17" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(14)} -pin  "mux#17" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(15)} -pin  "mux#17" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {r(0).sva#1(0)} -pin  "mux#17" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(1)} -pin  "mux#17" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(2)} -pin  "mux#17" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(3)} -pin  "mux#17" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(4)} -pin  "mux#17" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(5)} -pin  "mux#17" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(6)} -pin  "mux#17" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(7)} -pin  "mux#17" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(8)} -pin  "mux#17" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(9)} -pin  "mux#17" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(10)} -pin  "mux#17" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(11)} -pin  "mux#17" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(12)} -pin  "mux#17" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(13)} -pin  "mux#17" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(14)} -pin  "mux#17" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(15)} -pin  "mux#17" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {or#4.cse} -pin  "mux#17" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#17.itm(0)} -pin  "mux#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(1)} -pin  "mux#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(2)} -pin  "mux#17" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(3)} -pin  "mux#17" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(4)} -pin  "mux#17" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(5)} -pin  "mux#17" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(6)} -pin  "mux#17" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(7)} -pin  "mux#17" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(8)} -pin  "mux#17" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(9)} -pin  "mux#17" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(10)} -pin  "mux#17" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(11)} -pin  "mux#17" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(12)} -pin  "mux#17" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(13)} -pin  "mux#17" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(14)} -pin  "mux#17" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(15)} -pin  "mux#17" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load inst "reg(r(0).lpi#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 44615 -attr oid 491 -attr vt d -attr @path {/sobel/sobel:core/reg(r(0).lpi#1)}
+load net {mux#17.itm(0)} -pin  "reg(r(0).lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(1)} -pin  "reg(r(0).lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(2)} -pin  "reg(r(0).lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(3)} -pin  "reg(r(0).lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(4)} -pin  "reg(r(0).lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(5)} -pin  "reg(r(0).lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(6)} -pin  "reg(r(0).lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(7)} -pin  "reg(r(0).lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(8)} -pin  "reg(r(0).lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(9)} -pin  "reg(r(0).lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(10)} -pin  "reg(r(0).lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(11)} -pin  "reg(r(0).lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(12)} -pin  "reg(r(0).lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(13)} -pin  "reg(r(0).lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(14)} -pin  "reg(r(0).lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(15)} -pin  "reg(r(0).lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(r(0).lpi#1)" {clk} -attr xrf 44616 -attr oid 492 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(r(0).lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(r(0).lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {r(0).lpi#1(0)} -pin  "reg(r(0).lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(1)} -pin  "reg(r(0).lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(2)} -pin  "reg(r(0).lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(3)} -pin  "reg(r(0).lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(4)} -pin  "reg(r(0).lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(5)} -pin  "reg(r(0).lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(6)} -pin  "reg(r(0).lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(7)} -pin  "reg(r(0).lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(8)} -pin  "reg(r(0).lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(9)} -pin  "reg(r(0).lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(10)} -pin  "reg(r(0).lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(11)} -pin  "reg(r(0).lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(12)} -pin  "reg(r(0).lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(13)} -pin  "reg(r(0).lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(14)} -pin  "reg(r(0).lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(15)} -pin  "reg(r(0).lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load inst "not" "not(1)" "INTERFACE" -attr @path {/sobel/sobel:core/not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for#1:acc.itm(1)} -pin  "not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:slc#2.itm}
+load net {not.itm} -pin  "not" {Z(0)} -attr @path {/sobel/sobel:core/not.itm}
+load inst "and#3" "and(3,1)" "INTERFACE" -attr @path {/sobel/sobel:core/and#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {and.dcpl#1} -pin  "and#3" {A0(0)} -attr @path {/sobel/sobel:core/and.dcpl#1}
+load net {exit:FRAME:for.lpi#1} -pin  "and#3" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1}
+load net {not.itm} -pin  "and#3" {A2(0)} -attr @path {/sobel/sobel:core/not.itm}
+load net {and#3.itm} -pin  "and#3" {Z(0)} -attr @path {/sobel/sobel:core/and#3.itm}
+load inst "mux#18" "mux(2,19)" "INTERFACE" -attr xrf 44617 -attr oid 493 -attr vt d -attr @path {/sobel/sobel:core/mux#18} -attr area 17.470037 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2)"
+load net {FRAME:p#1.sva#1(0)} -pin  "mux#18" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "mux#18" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "mux#18" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "mux#18" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "mux#18" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "mux#18" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "mux#18" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "mux#18" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "mux#18" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "mux#18" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "mux#18" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "mux#18" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "mux#18" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "mux#18" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "mux#18" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "mux#18" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "mux#18" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "mux#18" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "mux#18" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "mux#18" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "mux#18" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "mux#18" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "mux#18" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "mux#18" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "mux#18" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "mux#18" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "mux#18" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "mux#18" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "mux#18" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "mux#18" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "mux#18" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "mux#18" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "mux#18" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "mux#18" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "mux#18" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "mux#18" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "mux#18" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "mux#18" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {and#3.itm} -pin  "mux#18" {S(0)} -attr @path {/sobel/sobel:core/and#3.itm}
+load net {mux#18.itm(0)} -pin  "mux#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(1)} -pin  "mux#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(2)} -pin  "mux#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(3)} -pin  "mux#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(4)} -pin  "mux#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(5)} -pin  "mux#18" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(6)} -pin  "mux#18" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(7)} -pin  "mux#18" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(8)} -pin  "mux#18" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(9)} -pin  "mux#18" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(10)} -pin  "mux#18" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(11)} -pin  "mux#18" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(12)} -pin  "mux#18" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(13)} -pin  "mux#18" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(14)} -pin  "mux#18" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(15)} -pin  "mux#18" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(16)} -pin  "mux#18" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(17)} -pin  "mux#18" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(18)} -pin  "mux#18" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load inst "reg(FRAME:p#1.lpi#1)" "reg(19,1,1,-1,0)" "INTERFACE" -attr xrf 44618 -attr oid 494 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:p#1.lpi#1)}
+load net {mux#18.itm(0)} -pin  "reg(FRAME:p#1.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(1)} -pin  "reg(FRAME:p#1.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(2)} -pin  "reg(FRAME:p#1.lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(3)} -pin  "reg(FRAME:p#1.lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(4)} -pin  "reg(FRAME:p#1.lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(5)} -pin  "reg(FRAME:p#1.lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(6)} -pin  "reg(FRAME:p#1.lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(7)} -pin  "reg(FRAME:p#1.lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(8)} -pin  "reg(FRAME:p#1.lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(9)} -pin  "reg(FRAME:p#1.lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(10)} -pin  "reg(FRAME:p#1.lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(11)} -pin  "reg(FRAME:p#1.lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(12)} -pin  "reg(FRAME:p#1.lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(13)} -pin  "reg(FRAME:p#1.lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(14)} -pin  "reg(FRAME:p#1.lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(15)} -pin  "reg(FRAME:p#1.lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(16)} -pin  "reg(FRAME:p#1.lpi#1)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(17)} -pin  "reg(FRAME:p#1.lpi#1)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(18)} -pin  "reg(FRAME:p#1.lpi#1)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_19}
+load net {clk} -pin  "reg(FRAME:p#1.lpi#1)" {clk} -attr xrf 44619 -attr oid 495 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:p#1.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:p#1.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:p#1.lpi#1(0)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load inst "FRAME:acc#19" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 44620 -attr oid 496 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {FRAME:acc#18.itm#1(0)} -pin  "FRAME:acc#19" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(1)} -pin  "FRAME:acc#19" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(2)} -pin  "FRAME:acc#19" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(3)} -pin  "FRAME:acc#19" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(4)} -pin  "FRAME:acc#19" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:slc(acc.imod#11)#4.itm#1} -pin  "FRAME:acc#19" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {PWR} -pin  "FRAME:acc#19" {B(1)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {GND} -pin  "FRAME:acc#19" {B(2)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {GND} -pin  "FRAME:acc#19" {B(3)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {PWR} -pin  "FRAME:acc#19" {B(4)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#19" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#19" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#19" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(3)} -pin  "FRAME:acc#19" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(4)} -pin  "FRAME:acc#19" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load inst "FRAME:acc#20" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 44621 -attr oid 497 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {green:slc(green#2.sg1).itm#1(0)} -pin  "FRAME:acc#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(1)} -pin  "FRAME:acc#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(2)} -pin  "FRAME:acc#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(3)} -pin  "FRAME:acc#20" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(4)} -pin  "FRAME:acc#20" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(5)} -pin  "FRAME:acc#20" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#20" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#20" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#20" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(3)} -pin  "FRAME:acc#20" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(4)} -pin  "FRAME:acc#20" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#20.itm(0)} -pin  "FRAME:acc#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(1)} -pin  "FRAME:acc#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(2)} -pin  "FRAME:acc#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(3)} -pin  "FRAME:acc#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(4)} -pin  "FRAME:acc#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(5)} -pin  "FRAME:acc#20" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(6)} -pin  "FRAME:acc#20" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(7)} -pin  "FRAME:acc#20" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load inst "FRAME:acc#21" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 44622 -attr oid 498 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul#3.itm#1(0)} -pin  "FRAME:acc#21" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(1)} -pin  "FRAME:acc#21" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(2)} -pin  "FRAME:acc#21" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(3)} -pin  "FRAME:acc#21" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(4)} -pin  "FRAME:acc#21" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(5)} -pin  "FRAME:acc#21" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(6)} -pin  "FRAME:acc#21" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(7)} -pin  "FRAME:acc#21" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(8)} -pin  "FRAME:acc#21" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
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+load inst "FRAME:acc#33" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 44627 -attr oid 503 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul#5.itm#1(0)} -pin  "FRAME:acc#33" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(1)} -pin  "FRAME:acc#33" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(2)} -pin  "FRAME:acc#33" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(3)} -pin  "FRAME:acc#33" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(4)} -pin  "FRAME:acc#33" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(5)} -pin  "FRAME:acc#33" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(6)} -pin  "FRAME:acc#33" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(7)} -pin  "FRAME:acc#33" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(8)} -pin  "FRAME:acc#33" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:acc#32.itm(0)} -pin  "FRAME:acc#33" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(1)} -pin  "FRAME:acc#33" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(2)} -pin  "FRAME:acc#33" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(3)} -pin  "FRAME:acc#33" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(4)} -pin  "FRAME:acc#33" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(5)} -pin  "FRAME:acc#33" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(6)} -pin  "FRAME:acc#33" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(7)} -pin  "FRAME:acc#33" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#33.itm(0)} -pin  "FRAME:acc#33" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(1)} -pin  "FRAME:acc#33" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(2)} -pin  "FRAME:acc#33" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(3)} -pin  "FRAME:acc#33" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(4)} -pin  "FRAME:acc#33" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(5)} -pin  "FRAME:acc#33" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(6)} -pin  "FRAME:acc#33" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(7)} -pin  "FRAME:acc#33" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(8)} -pin  "FRAME:acc#33" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(9)} -pin  "FRAME:acc#33" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load inst "FRAME:acc#34" "add(11,0,10,1,12)" "INTERFACE" -attr xrf 44628 -attr oid 504 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12)"
+load net {FRAME:mul#4.itm#1(0)} -pin  "FRAME:acc#34" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(1)} -pin  "FRAME:acc#34" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(2)} -pin  "FRAME:acc#34" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(3)} -pin  "FRAME:acc#34" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(4)} -pin  "FRAME:acc#34" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(5)} -pin  "FRAME:acc#34" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(6)} -pin  "FRAME:acc#34" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(7)} -pin  "FRAME:acc#34" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(8)} -pin  "FRAME:acc#34" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(9)} -pin  "FRAME:acc#34" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(10)} -pin  "FRAME:acc#34" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:acc#33.itm(0)} -pin  "FRAME:acc#34" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(1)} -pin  "FRAME:acc#34" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(2)} -pin  "FRAME:acc#34" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(3)} -pin  "FRAME:acc#34" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(4)} -pin  "FRAME:acc#34" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(5)} -pin  "FRAME:acc#34" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(6)} -pin  "FRAME:acc#34" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(7)} -pin  "FRAME:acc#34" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(8)} -pin  "FRAME:acc#34" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(9)} -pin  "FRAME:acc#34" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#34.itm(0)} -pin  "FRAME:acc#34" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(1)} -pin  "FRAME:acc#34" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(2)} -pin  "FRAME:acc#34" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(3)} -pin  "FRAME:acc#34" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(4)} -pin  "FRAME:acc#34" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(5)} -pin  "FRAME:acc#34" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(6)} -pin  "FRAME:acc#34" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(7)} -pin  "FRAME:acc#34" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(8)} -pin  "FRAME:acc#34" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(9)} -pin  "FRAME:acc#34" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(10)} -pin  "FRAME:acc#34" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(11)} -pin  "FRAME:acc#34" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load inst "FRAME:acc#4" "add(12,-1,11,0,12)" "INTERFACE" -attr xrf 44629 -attr oid 505 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4} -attr area 13.227600 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,11,0,12)"
+load net {FRAME:acc#34.itm(0)} -pin  "FRAME:acc#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(1)} -pin  "FRAME:acc#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(2)} -pin  "FRAME:acc#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(3)} -pin  "FRAME:acc#4" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(4)} -pin  "FRAME:acc#4" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(5)} -pin  "FRAME:acc#4" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(6)} -pin  "FRAME:acc#4" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(7)} -pin  "FRAME:acc#4" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(8)} -pin  "FRAME:acc#4" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(9)} -pin  "FRAME:acc#4" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(10)} -pin  "FRAME:acc#4" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(11)} -pin  "FRAME:acc#4" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(1)} -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(5)} -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(6)} -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(7)} -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {FRAME:acc#4.psp.sva(0)} -pin  "FRAME:acc#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(1)} -pin  "FRAME:acc#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(2)} -pin  "FRAME:acc#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(3)} -pin  "FRAME:acc#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(4)} -pin  "FRAME:acc#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(5)} -pin  "FRAME:acc#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(6)} -pin  "FRAME:acc#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(7)} -pin  "FRAME:acc#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(8)} -pin  "FRAME:acc#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(9)} -pin  "FRAME:acc#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(10)} -pin  "FRAME:acc#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(11)} -pin  "FRAME:acc#4" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load inst "FRAME:for#1:acc" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 44630 -attr oid 506 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2)"
+load net {i#7.sva(0)} -pin  "FRAME:for#1:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load net {i#7.sva(1)} -pin  "FRAME:for#1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load net {PWR} -pin  "FRAME:for#1:acc" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:for#1:acc.itm(0)} -pin  "FRAME:for#1:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc.itm}
+load net {FRAME:for#1:acc.itm(1)} -pin  "FRAME:for#1:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc.itm}
+load inst "FRAME:for:and#12" "and(2,1)" "INTERFACE" -attr xrf 44631 -attr oid 507 -attr @path {/sobel/sobel:core/FRAME:for:and#12} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {exit:FRAME:for.lpi#1} -pin  "FRAME:for:and#12" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1}
+load net {not#24} -pin  "FRAME:for:and#12" {A1(0)} -attr @path {/sobel/sobel:core/not#24}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:and#12" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load inst "FRAME:for#1:acc#16" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 44632 -attr oid 508 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc#16} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2)"
+load net {i#7.lpi#1(0)} -pin  "FRAME:for#1:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "FRAME:for#1:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {PWR} -pin  "FRAME:for#1:acc#16" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {i#7.sva(0)} -pin  "FRAME:for#1:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load net {i#7.sva(1)} -pin  "FRAME:for#1:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load inst "FRAME:for:or#2" "or(2,1)" "INTERFACE" -attr xrf 44633 -attr oid 509 -attr @path {/sobel/sobel:core/FRAME:for:or#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {exit:FRAME:for#1.lpi#1.dfm#5} -pin  "FRAME:for:or#2" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#5}
+load net {FRAME:acc.itm(7)} -pin  "FRAME:for:or#2" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:slc.itm}
+load net {FRAME:for:or#2.itm} -pin  "FRAME:for:or#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#2.itm}
+load inst "mux#3" "mux(2,1)" "INTERFACE" -attr xrf 44634 -attr oid 510 -attr @path {/sobel/sobel:core/mux#3} -attr area 0.920423 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2)"
+load net {exit:FRAME:for#1.lpi#1.dfm#5} -pin  "mux#3" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#5}
+load net {FRAME:for:or#2.itm} -pin  "mux#3" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#2.itm}
+load net {or#9.cse} -pin  "mux#3" {S(0)} -attr @path {/sobel/sobel:core/or#9.cse}
+load net {exit:FRAME:for#1.lpi#1.dfm#4:mx0} -pin  "mux#3" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4:mx0}
+load inst "mux#4" "mux(2,90)" "INTERFACE" -attr xrf 44635 -attr oid 511 -attr vt d -attr @path {/sobel/sobel:core/mux#4} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(2).lpi#1.dfm(0)} -pin  "mux#4" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(1)} -pin  "mux#4" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(2)} -pin  "mux#4" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(3)} -pin  "mux#4" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(4)} -pin  "mux#4" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(5)} -pin  "mux#4" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(6)} -pin  "mux#4" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(7)} -pin  "mux#4" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(8)} -pin  "mux#4" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(9)} -pin  "mux#4" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(10)} -pin  "mux#4" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(11)} -pin  "mux#4" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(12)} -pin  "mux#4" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(13)} -pin  "mux#4" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(14)} -pin  "mux#4" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(15)} -pin  "mux#4" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(16)} -pin  "mux#4" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(17)} -pin  "mux#4" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(18)} -pin  "mux#4" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(19)} -pin  "mux#4" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(20)} -pin  "mux#4" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(21)} -pin  "mux#4" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(22)} -pin  "mux#4" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(23)} -pin  "mux#4" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(24)} -pin  "mux#4" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(25)} -pin  "mux#4" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(26)} -pin  "mux#4" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(27)} -pin  "mux#4" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(28)} -pin  "mux#4" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(29)} -pin  "mux#4" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(30)} -pin  "mux#4" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(31)} -pin  "mux#4" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(32)} -pin  "mux#4" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(33)} -pin  "mux#4" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(34)} -pin  "mux#4" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(35)} -pin  "mux#4" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(36)} -pin  "mux#4" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(37)} -pin  "mux#4" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(38)} -pin  "mux#4" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(39)} -pin  "mux#4" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(40)} -pin  "mux#4" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(41)} -pin  "mux#4" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(42)} -pin  "mux#4" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(43)} -pin  "mux#4" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(44)} -pin  "mux#4" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(45)} -pin  "mux#4" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(46)} -pin  "mux#4" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(47)} -pin  "mux#4" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(48)} -pin  "mux#4" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(49)} -pin  "mux#4" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(50)} -pin  "mux#4" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(51)} -pin  "mux#4" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(52)} -pin  "mux#4" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(53)} -pin  "mux#4" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(54)} -pin  "mux#4" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(55)} -pin  "mux#4" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(56)} -pin  "mux#4" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(57)} -pin  "mux#4" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(58)} -pin  "mux#4" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(59)} -pin  "mux#4" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(60)} -pin  "mux#4" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(61)} -pin  "mux#4" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(62)} -pin  "mux#4" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(63)} -pin  "mux#4" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(64)} -pin  "mux#4" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(65)} -pin  "mux#4" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(66)} -pin  "mux#4" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(67)} -pin  "mux#4" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(68)} -pin  "mux#4" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(69)} -pin  "mux#4" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(70)} -pin  "mux#4" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(71)} -pin  "mux#4" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(72)} -pin  "mux#4" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(73)} -pin  "mux#4" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(74)} -pin  "mux#4" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(75)} -pin  "mux#4" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(76)} -pin  "mux#4" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(77)} -pin  "mux#4" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(78)} -pin  "mux#4" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(79)} -pin  "mux#4" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(80)} -pin  "mux#4" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(81)} -pin  "mux#4" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(82)} -pin  "mux#4" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(83)} -pin  "mux#4" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(84)} -pin  "mux#4" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(85)} -pin  "mux#4" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(86)} -pin  "mux#4" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(87)} -pin  "mux#4" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(88)} -pin  "mux#4" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(89)} -pin  "mux#4" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(1).sva(0)} -pin  "mux#4" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "mux#4" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "mux#4" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "mux#4" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "mux#4" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "mux#4" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "mux#4" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "mux#4" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "mux#4" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "mux#4" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "mux#4" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "mux#4" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "mux#4" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "mux#4" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "mux#4" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "mux#4" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "mux#4" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "mux#4" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "mux#4" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "mux#4" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "mux#4" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "mux#4" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "mux#4" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "mux#4" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "mux#4" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "mux#4" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "mux#4" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "mux#4" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "mux#4" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "mux#4" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "mux#4" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "mux#4" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "mux#4" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "mux#4" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "mux#4" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "mux#4" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "mux#4" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "mux#4" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "mux#4" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "mux#4" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "mux#4" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "mux#4" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "mux#4" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "mux#4" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "mux#4" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "mux#4" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "mux#4" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "mux#4" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "mux#4" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "mux#4" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "mux#4" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "mux#4" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "mux#4" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "mux#4" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "mux#4" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "mux#4" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "mux#4" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "mux#4" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "mux#4" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "mux#4" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "mux#4" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "mux#4" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "mux#4" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "mux#4" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "mux#4" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "mux#4" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "mux#4" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "mux#4" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "mux#4" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "mux#4" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "mux#4" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "mux#4" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "mux#4" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "mux#4" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "mux#4" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "mux#4" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "mux#4" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "mux#4" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "mux#4" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "mux#4" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "mux#4" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "mux#4" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "mux#4" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "mux#4" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "mux#4" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "mux#4" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "mux#4" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "mux#4" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "mux#4" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "mux#4" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {and.dcpl#1} -pin  "mux#4" {S(0)} -attr @path {/sobel/sobel:core/and.dcpl#1}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "mux#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "mux#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "mux#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "mux#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "mux#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "mux#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "mux#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "mux#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "mux#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "mux#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "mux#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "mux#4" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "mux#4" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "mux#4" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "mux#4" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "mux#4" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "mux#4" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "mux#4" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "mux#4" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "mux#4" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "mux#4" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "mux#4" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "mux#4" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "mux#4" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "mux#4" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "mux#4" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "mux#4" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "mux#4" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "mux#4" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "mux#4" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "mux#4" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "mux#4" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "mux#4" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "mux#4" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "mux#4" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "mux#4" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "mux#4" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "mux#4" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "mux#4" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "mux#4" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "mux#4" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "mux#4" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "mux#4" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "mux#4" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "mux#4" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "mux#4" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "mux#4" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "mux#4" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "mux#4" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "mux#4" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "mux#4" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "mux#4" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "mux#4" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "mux#4" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "mux#4" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "mux#4" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "mux#4" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "mux#4" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "mux#4" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "mux#4" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "mux#4" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "mux#4" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "mux#4" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "mux#4" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "mux#4" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "mux#4" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "mux#4" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "mux#4" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "mux#4" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "mux#4" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "mux#4" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "mux#4" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "mux#4" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "mux#4" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "mux#4" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "mux#4" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "mux#4" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "mux#4" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "mux#4" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "mux#4" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "mux#4" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "mux#4" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "mux#4" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "mux#4" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "mux#4" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "mux#4" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "mux#4" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "mux#4" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "mux#4" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "mux#4" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load inst "mux#5" "mux(2,90)" "INTERFACE" -attr xrf 44636 -attr oid 512 -attr vt d -attr @path {/sobel/sobel:core/mux#5} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(1).sva(0)} -pin  "mux#5" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "mux#5" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "mux#5" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "mux#5" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "mux#5" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "mux#5" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "mux#5" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "mux#5" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "mux#5" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "mux#5" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "mux#5" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "mux#5" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "mux#5" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "mux#5" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "mux#5" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "mux#5" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "mux#5" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "mux#5" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "mux#5" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "mux#5" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "mux#5" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "mux#5" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "mux#5" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "mux#5" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "mux#5" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "mux#5" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "mux#5" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "mux#5" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "mux#5" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "mux#5" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "mux#5" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "mux#5" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "mux#5" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "mux#5" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "mux#5" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "mux#5" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "mux#5" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "mux#5" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "mux#5" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "mux#5" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "mux#5" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "mux#5" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "mux#5" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "mux#5" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "mux#5" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "mux#5" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "mux#5" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "mux#5" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "mux#5" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "mux#5" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "mux#5" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "mux#5" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "mux#5" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "mux#5" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "mux#5" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "mux#5" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "mux#5" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "mux#5" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "mux#5" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "mux#5" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "mux#5" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "mux#5" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "mux#5" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "mux#5" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "mux#5" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "mux#5" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "mux#5" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "mux#5" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "mux#5" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "mux#5" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "mux#5" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "mux#5" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "mux#5" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "mux#5" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "mux#5" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "mux#5" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "mux#5" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "mux#5" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "mux#5" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "mux#5" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "mux#5" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "mux#5" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "mux#5" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "mux#5" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "mux#5" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "mux#5" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "mux#5" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "mux#5" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "mux#5" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "mux#5" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -pin  "mux#5" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#5" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#5" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#5" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#5" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#5" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#5" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#5" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#5" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#5" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#5" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#5" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#5" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#5" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#5" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#5" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#5" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#5" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#5" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#5" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#5" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#5" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#5" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#5" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#5" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#5" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#5" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#5" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#5" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#5" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#5" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#5" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#5" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#5" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#5" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#5" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#5" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#5" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#5" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#5" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#5" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#5" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#5" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#5" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#5" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#5" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#5" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#5" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#5" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#5" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#5" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#5" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#5" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#5" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#5" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#5" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#5" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#5" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#5" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#5" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#5" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#5" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#5" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#5" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#5" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#5" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#5" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#5" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#5" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#5" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#5" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#5" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#5" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#5" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#5" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#5" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#5" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#5" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#5" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#5" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#5" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#5" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#5" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#5" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#5" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#5" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#5" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#5" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#5" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#5" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {and.dcpl#1} -pin  "mux#5" {S(0)} -attr @path {/sobel/sobel:core/and.dcpl#1}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "mux#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "mux#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "mux#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "mux#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "mux#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "mux#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "mux#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "mux#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "mux#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "mux#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "mux#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "mux#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "mux#5" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "mux#5" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "mux#5" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "mux#5" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "mux#5" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "mux#5" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "mux#5" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "mux#5" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "mux#5" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "mux#5" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "mux#5" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "mux#5" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "mux#5" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "mux#5" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "mux#5" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "mux#5" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "mux#5" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "mux#5" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "mux#5" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "mux#5" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "mux#5" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "mux#5" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "mux#5" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "mux#5" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "mux#5" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "mux#5" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "mux#5" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "mux#5" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "mux#5" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "mux#5" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "mux#5" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "mux#5" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "mux#5" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "mux#5" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "mux#5" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "mux#5" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "mux#5" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "mux#5" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "mux#5" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "mux#5" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "mux#5" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "mux#5" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "mux#5" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "mux#5" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "mux#5" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "mux#5" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "mux#5" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "mux#5" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "mux#5" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "mux#5" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "mux#5" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "mux#5" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "mux#5" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "mux#5" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "mux#5" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "mux#5" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "mux#5" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "mux#5" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "mux#5" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "mux#5" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "mux#5" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "mux#5" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "mux#5" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "mux#5" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "mux#5" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "mux#5" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "mux#5" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "mux#5" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "mux#5" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "mux#5" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "mux#5" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "mux#5" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "mux#5" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "mux#5" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "mux#5" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "mux#5" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "mux#5" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "mux#5" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load inst "mux#6" "mux(2,90)" "INTERFACE" -attr xrf 44637 -attr oid 513 -attr vt d -attr @path {/sobel/sobel:core/mux#6} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(0).sva(0)} -pin  "mux#6" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#6" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#6" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#6" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#6" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#6" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#6" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#6" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#6" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#6" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#6" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#6" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#6" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#6" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#6" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#6" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#6" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#6" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#6" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#6" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#6" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#6" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#6" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#6" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#6" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#6" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#6" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#6" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#6" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#6" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#6" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#6" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#6" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#6" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#6" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#6" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#6" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#6" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#6" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#6" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#6" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#6" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#6" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#6" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#6" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#6" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#6" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#6" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#6" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#6" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#6" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#6" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#6" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#6" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#6" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#6" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#6" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#6" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#6" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#6" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#6" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#6" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#6" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#6" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#6" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#6" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#6" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#6" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#6" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#6" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#6" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#6" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#6" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#6" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#6" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#6" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#6" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#6" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#6" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#6" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#6" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#6" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#6" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#6" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#6" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#6" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#6" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#6" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#6" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#6" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "mux#6" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "mux#6" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "mux#6" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "mux#6" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "mux#6" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "mux#6" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "mux#6" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "mux#6" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "mux#6" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "mux#6" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "mux#6" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "mux#6" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "mux#6" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "mux#6" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "mux#6" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "mux#6" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "mux#6" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "mux#6" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "mux#6" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "mux#6" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "mux#6" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "mux#6" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "mux#6" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "mux#6" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "mux#6" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "mux#6" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "mux#6" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "mux#6" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "mux#6" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "mux#6" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "mux#6" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "mux#6" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "mux#6" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "mux#6" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "mux#6" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "mux#6" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "mux#6" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "mux#6" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "mux#6" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "mux#6" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "mux#6" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "mux#6" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "mux#6" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "mux#6" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "mux#6" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "mux#6" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "mux#6" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "mux#6" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "mux#6" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "mux#6" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "mux#6" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "mux#6" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "mux#6" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "mux#6" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "mux#6" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "mux#6" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "mux#6" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "mux#6" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "mux#6" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "mux#6" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "mux#6" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "mux#6" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "mux#6" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "mux#6" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "mux#6" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "mux#6" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "mux#6" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "mux#6" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "mux#6" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "mux#6" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "mux#6" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "mux#6" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "mux#6" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "mux#6" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "mux#6" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "mux#6" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "mux#6" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "mux#6" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "mux#6" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "mux#6" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "mux#6" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "mux#6" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "mux#6" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "mux#6" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "mux#6" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "mux#6" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "mux#6" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "mux#6" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "mux#6" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "mux#6" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {and.dcpl#1} -pin  "mux#6" {S(0)} -attr @path {/sobel/sobel:core/and.dcpl#1}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "mux#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "mux#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "mux#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "mux#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "mux#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "mux#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "mux#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "mux#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "mux#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "mux#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "mux#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "mux#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "mux#6" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "mux#6" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "mux#6" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "mux#6" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "mux#6" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "mux#6" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "mux#6" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "mux#6" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "mux#6" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "mux#6" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "mux#6" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "mux#6" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "mux#6" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "mux#6" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "mux#6" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "mux#6" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "mux#6" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "mux#6" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "mux#6" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "mux#6" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "mux#6" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "mux#6" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "mux#6" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "mux#6" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "mux#6" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "mux#6" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "mux#6" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "mux#6" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "mux#6" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "mux#6" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "mux#6" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "mux#6" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "mux#6" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "mux#6" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "mux#6" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "mux#6" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "mux#6" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "mux#6" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "mux#6" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "mux#6" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "mux#6" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "mux#6" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "mux#6" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "mux#6" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "mux#6" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "mux#6" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "mux#6" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "mux#6" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "mux#6" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "mux#6" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "mux#6" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "mux#6" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "mux#6" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "mux#6" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "mux#6" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "mux#6" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "mux#6" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "mux#6" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "mux#6" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "mux#6" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "mux#6" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "mux#6" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "mux#6" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "mux#6" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "mux#6" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "mux#6" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "mux#6" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "mux#6" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "mux#6" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "mux#6" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "mux#6" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "mux#6" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "mux#6" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "mux#6" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "mux#6" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "mux#6" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "mux#6" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "mux#6" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load inst "FRAME:acc" "add(7,0,8,-1,8)" "INTERFACE" -attr xrf 44638 -attr oid 514 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc} -attr area 9.262368 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,7,0,8)"
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {PWR} -pin  "FRAME:acc" {B(0)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(1)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(2)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(3)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(4)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(5)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(6)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(7)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {FRAME:acc.itm(0)} -pin  "FRAME:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(1)} -pin  "FRAME:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(2)} -pin  "FRAME:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(3)} -pin  "FRAME:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(4)} -pin  "FRAME:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(5)} -pin  "FRAME:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(6)} -pin  "FRAME:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(7)} -pin  "FRAME:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load inst "FRAME:for:and#10" "and(2,1)" "INTERFACE" -attr xrf 44639 -attr oid 515 -attr @path {/sobel/sobel:core/FRAME:for:and#10} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {exit:FRAME.lpi#1.dfm#2} -pin  "FRAME:for:and#10" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#2}
+load net {not#24} -pin  "FRAME:for:and#10" {A1(0)} -attr @path {/sobel/sobel:core/not#24}
+load net {FRAME:for:and#10.itm} -pin  "FRAME:for:and#10" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#10.itm}
+load inst "FRAME:not" "not(1)" "INTERFACE" -attr xrf 44640 -attr oid 516 -attr @path {/sobel/sobel:core/FRAME:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc.itm(7)} -pin  "FRAME:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#8.itm}
+load net {FRAME:not.itm} -pin  "FRAME:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load inst "mux#7" "mux(2,1)" "INTERFACE" -attr xrf 44641 -attr oid 517 -attr @path {/sobel/sobel:core/mux#7} -attr area 0.920423 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2)"
+load net {FRAME:for:and#10.itm} -pin  "mux#7" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#10.itm}
+load net {FRAME:not.itm} -pin  "mux#7" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load net {or#9.cse} -pin  "mux#7" {S(0)} -attr @path {/sobel/sobel:core/or#9.cse}
+load net {exit:FRAME.lpi#1.dfm#2:mx0} -pin  "mux#7" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#2:mx0}
+load inst "FRAME:for#1:not" "not(1)" "INTERFACE" -attr xrf 44642 -attr oid 518 -attr @path {/sobel/sobel:core/FRAME:for#1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for#1:acc.itm(1)} -pin  "FRAME:for#1:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:slc#1.itm}
+load net {FRAME:for#1:not.itm} -pin  "FRAME:for#1:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not.itm}
+load inst "FRAME:for:and#15" "and(2,1)" "INTERFACE" -attr xrf 44643 -attr oid 519 -attr @path {/sobel/sobel:core/FRAME:for:and#15} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {FRAME:for#1:not.itm} -pin  "FRAME:for:and#15" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not.itm}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:and#15" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {exit:FRAME:for#1.lpi#1.dfm#5} -pin  "FRAME:for:and#15" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#5}
+load inst "FRAME:acc#6" "add(19,-1,1,0,19)" "INTERFACE" -attr xrf 44644 -attr oid 520 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6} -attr area 20.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19)"
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "FRAME:acc#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "FRAME:acc#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "FRAME:acc#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "FRAME:acc#6" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "FRAME:acc#6" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "FRAME:acc#6" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "FRAME:acc#6" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "FRAME:acc#6" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "FRAME:acc#6" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "FRAME:acc#6" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "FRAME:acc#6" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "FRAME:acc#6" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "FRAME:acc#6" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "FRAME:acc#6" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "FRAME:acc#6" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "FRAME:acc#6" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "FRAME:acc#6" {A(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "FRAME:acc#6" {A(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "FRAME:acc#6" {A(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:acc#6" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:p#1.sva#1(0)} -pin  "FRAME:acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "FRAME:acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "FRAME:acc#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "FRAME:acc#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "FRAME:acc#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "FRAME:acc#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "FRAME:acc#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "FRAME:acc#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "FRAME:acc#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "FRAME:acc#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "FRAME:acc#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "FRAME:acc#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc#6" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc#6" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc#6" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc#6" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc#6" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc#6" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc#6" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load inst "FRAME:not#28" "not(1)" "INTERFACE" -attr xrf 44645 -attr oid 521 -attr @path {/sobel/sobel:core/FRAME:not#28} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME#1.sva} -pin  "FRAME:not#28" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {FRAME:not#28.itm} -pin  "FRAME:not#28" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#28.itm}
+load inst "and" "and(2,19)" "INTERFACE" -attr vt d -attr @path {/sobel/sobel:core/and} -attr area 13.866816 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2)"
+load net {FRAME:p#1.lpi#1(0)} -pin  "and" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "and" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "and" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "and" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "and" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "and" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "and" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "and" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "and" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "and" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "and" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "and" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "and" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "and" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "and" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "and" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "and" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "and" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "and" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:not#28.itm} -pin  "and" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "and" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "and" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "and" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "and" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "and" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "and" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "and" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "and" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "and" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "and" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "and" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "and" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "and" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "and" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "and" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "and" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "and" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "and" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "and" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load inst "FRAME:not#2" "not(3)" "INTERFACE" -attr xrf 44646 -attr oid 522 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#1.itm(10)} -pin  "FRAME:not#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#1.itm(11)} -pin  "FRAME:not#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#1.itm(12)} -pin  "FRAME:not#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#2.itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:not#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:not#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:not#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load inst "FRAME:acc#8" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 44647 -attr oid 523 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC2-3:acc#1.itm(7)} -pin  "FRAME:acc#8" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva).itm}
+load net {ACC2-3:acc#1.itm(8)} -pin  "FRAME:acc#8" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva).itm}
+load net {ACC2-3:acc#1.itm(9)} -pin  "FRAME:acc#8" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva).itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:acc#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:acc#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:acc#8" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#8" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#8" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#8" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#8" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load inst "FRAME:not#35" "not(1)" "INTERFACE" -attr xrf 44648 -attr oid 524 -attr @path {/sobel/sobel:core/FRAME:not#35} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:not#35" {A(0)} -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#20.itm}
+load net {FRAME:not#35.itm} -pin  "FRAME:not#35" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#35.itm}
+load inst "FRAME:not#45" "not(1)" "INTERFACE" -attr xrf 44649 -attr oid 525 -attr @path {/sobel/sobel:core/FRAME:not#45} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:not#45" {A(0)} -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#10.itm}
+load net {FRAME:not#45.itm} -pin  "FRAME:not#45" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#45.itm}
+load inst "FRAME:acc#7" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 44650 -attr oid 526 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#45.itm} -pin  "FRAME:acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {PWR} -pin  "FRAME:acc#7" {A(1)} -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {FRAME:not#35.itm} -pin  "FRAME:acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {ACC2-3:acc#1.itm(13)} -pin  "FRAME:acc#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#5.itm}
+load net {ACC2-3:acc#1.itm(14)} -pin  "FRAME:acc#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#5.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load inst "FRAME:acc#10" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 44651 -attr oid 527 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#10" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#10" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#10" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#10" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#10" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#10" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#10" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#10" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#10" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#10" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(4)} -pin  "FRAME:acc#10" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load inst "FRAME:not#1" "not(3)" "INTERFACE" -attr xrf 44652 -attr oid 528 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#1.itm(4)} -pin  "FRAME:not#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {ACC2-3:acc#1.itm(5)} -pin  "FRAME:not#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {ACC2-3:acc#1.itm(6)} -pin  "FRAME:not#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:not#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:not#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:not#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load inst "FRAME:acc#9" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 44653 -attr oid 529 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC2-3:acc#1.itm(1)} -pin  "FRAME:acc#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#1.itm(2)} -pin  "FRAME:acc#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#1.itm(3)} -pin  "FRAME:acc#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:acc#9" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:acc#9" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:acc#9" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load inst "FRAME:acc#11" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 44654 -attr oid 530 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11} -attr area 6.288444 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6)"
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#11" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#11" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#11" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#11" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(4)} -pin  "FRAME:acc#11" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#11" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#11" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#11" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#11" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#11" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#11" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#11" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#11" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "FRAME:acc#11" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(5)} -pin  "FRAME:acc#11" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load inst "acc#9" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 44655 -attr oid 531 -attr vt dc -attr @path {/sobel/sobel:core/acc#9} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {FRAME:acc#11.itm(0)} -pin  "acc#9" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "acc#9" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "acc#9" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "acc#9" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "acc#9" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(5)} -pin  "acc#9" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {PWR} -pin  "acc#9" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#9" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#9" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#9" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#9" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#9" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#9.sva(0)} -pin  "acc#9" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod#9.sva}
+load net {acc.imod#9.sva(1)} -pin  "acc#9" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod#9.sva}
+load net {acc.imod#9.sva(2)} -pin  "acc#9" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod#9.sva}
+load net {acc.imod#9.sva(3)} -pin  "acc#9" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod#9.sva}
+load net {acc.imod#9.sva(4)} -pin  "acc#9" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod#9.sva}
+load net {acc.imod#9.sva(5)} -pin  "acc#9" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod#9.sva}
+load inst "ACC2:acc" "add(15,-1,15,-1,15)" "INTERFACE" -attr xrf 44656 -attr oid 532 -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc} -attr area 16.198770 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,15,0,15)"
+load net {r(1).sg1.lpi#1.dfm(0)} -pin  "ACC2:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(1)} -pin  "ACC2:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(2)} -pin  "ACC2:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(3)} -pin  "ACC2:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(4)} -pin  "ACC2:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(5)} -pin  "ACC2:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(6)} -pin  "ACC2:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(7)} -pin  "ACC2:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(8)} -pin  "ACC2:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(9)} -pin  "ACC2:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(10)} -pin  "ACC2:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(11)} -pin  "ACC2:acc" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(12)} -pin  "ACC2:acc" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(13)} -pin  "ACC2:acc" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(14)} -pin  "ACC2:acc" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(2).sva#1(1)} -pin  "ACC2:acc" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(2)} -pin  "ACC2:acc" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(3)} -pin  "ACC2:acc" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(4)} -pin  "ACC2:acc" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(5)} -pin  "ACC2:acc" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(6)} -pin  "ACC2:acc" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(7)} -pin  "ACC2:acc" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(8)} -pin  "ACC2:acc" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(9)} -pin  "ACC2:acc" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(10)} -pin  "ACC2:acc" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(11)} -pin  "ACC2:acc" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(12)} -pin  "ACC2:acc" {B(11)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(13)} -pin  "ACC2:acc" {B(12)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(14)} -pin  "ACC2:acc" {B(13)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(15)} -pin  "ACC2:acc" {B(14)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {ACC2:acc.itm(0)} -pin  "ACC2:acc" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(1)} -pin  "ACC2:acc" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(2)} -pin  "ACC2:acc" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(3)} -pin  "ACC2:acc" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(4)} -pin  "ACC2:acc" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(5)} -pin  "ACC2:acc" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(6)} -pin  "ACC2:acc" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(7)} -pin  "ACC2:acc" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(8)} -pin  "ACC2:acc" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(9)} -pin  "ACC2:acc" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(10)} -pin  "ACC2:acc" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(11)} -pin  "ACC2:acc" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(12)} -pin  "ACC2:acc" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(13)} -pin  "ACC2:acc" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(14)} -pin  "ACC2:acc" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load inst "ACC2-3:acc#1" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 44657 -attr oid 533 -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {r(2).sva#1(0)} -pin  "ACC2-3:acc#1" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(0)} -pin  "ACC2-3:acc#1" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(1)} -pin  "ACC2-3:acc#1" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(2)} -pin  "ACC2-3:acc#1" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(3)} -pin  "ACC2-3:acc#1" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(4)} -pin  "ACC2-3:acc#1" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(5)} -pin  "ACC2-3:acc#1" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(6)} -pin  "ACC2-3:acc#1" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(7)} -pin  "ACC2-3:acc#1" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(8)} -pin  "ACC2-3:acc#1" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(9)} -pin  "ACC2-3:acc#1" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(10)} -pin  "ACC2-3:acc#1" {A(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(11)} -pin  "ACC2-3:acc#1" {A(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(12)} -pin  "ACC2-3:acc#1" {A(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(13)} -pin  "ACC2-3:acc#1" {A(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(14)} -pin  "ACC2-3:acc#1" {A(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {r(0).sva#1(0)} -pin  "ACC2-3:acc#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(1)} -pin  "ACC2-3:acc#1" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(2)} -pin  "ACC2-3:acc#1" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(3)} -pin  "ACC2-3:acc#1" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(4)} -pin  "ACC2-3:acc#1" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(5)} -pin  "ACC2-3:acc#1" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(6)} -pin  "ACC2-3:acc#1" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(7)} -pin  "ACC2-3:acc#1" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(8)} -pin  "ACC2-3:acc#1" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(9)} -pin  "ACC2-3:acc#1" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(10)} -pin  "ACC2-3:acc#1" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(11)} -pin  "ACC2-3:acc#1" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(12)} -pin  "ACC2-3:acc#1" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(13)} -pin  "ACC2-3:acc#1" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(14)} -pin  "ACC2-3:acc#1" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(15)} -pin  "ACC2-3:acc#1" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {ACC2-3:acc#1.itm(0)} -pin  "ACC2-3:acc#1" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(1)} -pin  "ACC2-3:acc#1" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(2)} -pin  "ACC2-3:acc#1" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(3)} -pin  "ACC2-3:acc#1" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(4)} -pin  "ACC2-3:acc#1" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(5)} -pin  "ACC2-3:acc#1" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(6)} -pin  "ACC2-3:acc#1" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(7)} -pin  "ACC2-3:acc#1" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(8)} -pin  "ACC2-3:acc#1" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(9)} -pin  "ACC2-3:acc#1" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(10)} -pin  "ACC2-3:acc#1" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(11)} -pin  "ACC2-3:acc#1" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(12)} -pin  "ACC2-3:acc#1" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(13)} -pin  "ACC2-3:acc#1" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(14)} -pin  "ACC2-3:acc#1" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(15)} -pin  "ACC2-3:acc#1" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load inst "FRAME:mul" "mul(2,0,9,0,10)" "INTERFACE" -attr xrf 44658 -attr oid 534 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC2-3:acc#1.itm(13)} -pin  "FRAME:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#12.itm}
+load net {ACC2-3:acc#1.itm(14)} -pin  "FRAME:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#12.itm}
+load net {PWR} -pin  "FRAME:mul" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul.sdt(0)} -pin  "FRAME:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(1)} -pin  "FRAME:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(2)} -pin  "FRAME:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(3)} -pin  "FRAME:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(4)} -pin  "FRAME:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(5)} -pin  "FRAME:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(6)} -pin  "FRAME:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(7)} -pin  "FRAME:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(8)} -pin  "FRAME:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(9)} -pin  "FRAME:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load inst "ACC2:acc#8" "add(15,-1,15,-1,15)" "INTERFACE" -attr xrf 44659 -attr oid 535 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8} -attr area 16.198770 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,15,0,15)"
+load net {b(1).sg1.lpi#1.dfm(0)} -pin  "ACC2:acc#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(1)} -pin  "ACC2:acc#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(2)} -pin  "ACC2:acc#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(3)} -pin  "ACC2:acc#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(4)} -pin  "ACC2:acc#8" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(5)} -pin  "ACC2:acc#8" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(6)} -pin  "ACC2:acc#8" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(7)} -pin  "ACC2:acc#8" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(8)} -pin  "ACC2:acc#8" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(9)} -pin  "ACC2:acc#8" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(10)} -pin  "ACC2:acc#8" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(11)} -pin  "ACC2:acc#8" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(12)} -pin  "ACC2:acc#8" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(13)} -pin  "ACC2:acc#8" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(14)} -pin  "ACC2:acc#8" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(2).sva#1(1)} -pin  "ACC2:acc#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(2)} -pin  "ACC2:acc#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(3)} -pin  "ACC2:acc#8" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(4)} -pin  "ACC2:acc#8" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(5)} -pin  "ACC2:acc#8" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(6)} -pin  "ACC2:acc#8" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(7)} -pin  "ACC2:acc#8" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(8)} -pin  "ACC2:acc#8" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(9)} -pin  "ACC2:acc#8" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(10)} -pin  "ACC2:acc#8" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(11)} -pin  "ACC2:acc#8" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(12)} -pin  "ACC2:acc#8" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(13)} -pin  "ACC2:acc#8" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(14)} -pin  "ACC2:acc#8" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(15)} -pin  "ACC2:acc#8" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {ACC2:acc#8.itm(0)} -pin  "ACC2:acc#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(1)} -pin  "ACC2:acc#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(2)} -pin  "ACC2:acc#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(3)} -pin  "ACC2:acc#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(4)} -pin  "ACC2:acc#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(5)} -pin  "ACC2:acc#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(6)} -pin  "ACC2:acc#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(7)} -pin  "ACC2:acc#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(8)} -pin  "ACC2:acc#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(9)} -pin  "ACC2:acc#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(10)} -pin  "ACC2:acc#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(11)} -pin  "ACC2:acc#8" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(12)} -pin  "ACC2:acc#8" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(13)} -pin  "ACC2:acc#8" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(14)} -pin  "ACC2:acc#8" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load inst "ACC2-3:acc#3" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 44660 -attr oid 536 -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {b(2).sva#1(0)} -pin  "ACC2-3:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(0)} -pin  "ACC2-3:acc#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(1)} -pin  "ACC2-3:acc#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(2)} -pin  "ACC2-3:acc#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(3)} -pin  "ACC2-3:acc#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(4)} -pin  "ACC2-3:acc#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(5)} -pin  "ACC2-3:acc#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(6)} -pin  "ACC2-3:acc#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(7)} -pin  "ACC2-3:acc#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(8)} -pin  "ACC2-3:acc#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(9)} -pin  "ACC2-3:acc#3" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(10)} -pin  "ACC2-3:acc#3" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(11)} -pin  "ACC2-3:acc#3" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(12)} -pin  "ACC2-3:acc#3" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(13)} -pin  "ACC2-3:acc#3" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(14)} -pin  "ACC2-3:acc#3" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {b(0).sva#1(0)} -pin  "ACC2-3:acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(1)} -pin  "ACC2-3:acc#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(2)} -pin  "ACC2-3:acc#3" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(3)} -pin  "ACC2-3:acc#3" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(4)} -pin  "ACC2-3:acc#3" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(5)} -pin  "ACC2-3:acc#3" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(6)} -pin  "ACC2-3:acc#3" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(7)} -pin  "ACC2-3:acc#3" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(8)} -pin  "ACC2-3:acc#3" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(9)} -pin  "ACC2-3:acc#3" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(10)} -pin  "ACC2-3:acc#3" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(11)} -pin  "ACC2-3:acc#3" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(12)} -pin  "ACC2-3:acc#3" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(13)} -pin  "ACC2-3:acc#3" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(14)} -pin  "ACC2-3:acc#3" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(15)} -pin  "ACC2-3:acc#3" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {ACC2-3:acc#3.itm(0)} -pin  "ACC2-3:acc#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(1)} -pin  "ACC2-3:acc#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(2)} -pin  "ACC2-3:acc#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(3)} -pin  "ACC2-3:acc#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(4)} -pin  "ACC2-3:acc#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(5)} -pin  "ACC2-3:acc#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(6)} -pin  "ACC2-3:acc#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(7)} -pin  "ACC2-3:acc#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(8)} -pin  "ACC2-3:acc#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(9)} -pin  "ACC2-3:acc#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(10)} -pin  "ACC2-3:acc#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(11)} -pin  "ACC2-3:acc#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(12)} -pin  "ACC2-3:acc#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(13)} -pin  "ACC2-3:acc#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(14)} -pin  "ACC2-3:acc#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(15)} -pin  "ACC2-3:acc#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load inst "FRAME:not#18" "not(3)" "INTERFACE" -attr xrf 44661 -attr oid 537 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#3.itm(10)} -pin  "FRAME:not#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {ACC2-3:acc#3.itm(11)} -pin  "FRAME:not#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {ACC2-3:acc#3.itm(12)} -pin  "FRAME:not#18" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {FRAME:not#18.itm(0)} -pin  "FRAME:not#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(1)} -pin  "FRAME:not#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(2)} -pin  "FRAME:not#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load inst "FRAME:acc#25" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 44662 -attr oid 538 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC2-3:acc#3.itm(7)} -pin  "FRAME:acc#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#3.itm(8)} -pin  "FRAME:acc#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#3.itm(9)} -pin  "FRAME:acc#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {FRAME:not#18.itm(0)} -pin  "FRAME:acc#25" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(1)} -pin  "FRAME:acc#25" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(2)} -pin  "FRAME:acc#25" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:acc#25.itm(0)} -pin  "FRAME:acc#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(1)} -pin  "FRAME:acc#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(2)} -pin  "FRAME:acc#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(3)} -pin  "FRAME:acc#25" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load inst "FRAME:not#36" "not(1)" "INTERFACE" -attr xrf 44663 -attr oid 539 -attr @path {/sobel/sobel:core/FRAME:not#36} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC2-3:acc#3.itm(15)} -pin  "FRAME:not#36" {A(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#12.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:not#36" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#36.itm}
+load inst "FRAME:not#47" "not(1)" "INTERFACE" -attr xrf 44664 -attr oid 540 -attr @path {/sobel/sobel:core/FRAME:not#47} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC2-3:acc#3.itm(15)} -pin  "FRAME:not#47" {A(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#7.itm}
+load net {FRAME:not#47.itm} -pin  "FRAME:not#47" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#47.itm}
+load inst "FRAME:acc#24" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 44665 -attr oid 541 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#47.itm} -pin  "FRAME:acc#24" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {PWR} -pin  "FRAME:acc#24" {A(1)} -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:acc#24" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC2-3:acc#3.itm(13)} -pin  "FRAME:acc#24" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#4.itm}
+load net {ACC2-3:acc#3.itm(14)} -pin  "FRAME:acc#24" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#4.itm}
+load net {FRAME:acc#24.itm(0)} -pin  "FRAME:acc#24" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(1)} -pin  "FRAME:acc#24" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(2)} -pin  "FRAME:acc#24" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(3)} -pin  "FRAME:acc#24" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load inst "FRAME:acc#27" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 44666 -attr oid 542 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#25.itm(0)} -pin  "FRAME:acc#27" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(1)} -pin  "FRAME:acc#27" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(2)} -pin  "FRAME:acc#27" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(3)} -pin  "FRAME:acc#27" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#24.itm(0)} -pin  "FRAME:acc#27" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(1)} -pin  "FRAME:acc#27" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(2)} -pin  "FRAME:acc#27" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(3)} -pin  "FRAME:acc#27" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#27.itm(0)} -pin  "FRAME:acc#27" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(1)} -pin  "FRAME:acc#27" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(2)} -pin  "FRAME:acc#27" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(3)} -pin  "FRAME:acc#27" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(4)} -pin  "FRAME:acc#27" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load inst "FRAME:not#17" "not(3)" "INTERFACE" -attr xrf 44667 -attr oid 543 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#3.itm(4)} -pin  "FRAME:not#17" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#3.itm(5)} -pin  "FRAME:not#17" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#3.itm(6)} -pin  "FRAME:not#17" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {FRAME:not#17.itm(0)} -pin  "FRAME:not#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(1)} -pin  "FRAME:not#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(2)} -pin  "FRAME:not#17" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load inst "FRAME:acc#26" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 44668 -attr oid 544 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC2-3:acc#3.itm(1)} -pin  "FRAME:acc#26" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {ACC2-3:acc#3.itm(2)} -pin  "FRAME:acc#26" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {ACC2-3:acc#3.itm(3)} -pin  "FRAME:acc#26" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {FRAME:not#17.itm(0)} -pin  "FRAME:acc#26" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(1)} -pin  "FRAME:acc#26" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(2)} -pin  "FRAME:acc#26" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:acc#26.itm(0)} -pin  "FRAME:acc#26" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(1)} -pin  "FRAME:acc#26" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(2)} -pin  "FRAME:acc#26" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(3)} -pin  "FRAME:acc#26" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load inst "FRAME:acc#28" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 44669 -attr oid 545 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28} -attr area 6.288444 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6)"
+load net {FRAME:acc#27.itm(0)} -pin  "FRAME:acc#28" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(1)} -pin  "FRAME:acc#28" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(2)} -pin  "FRAME:acc#28" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(3)} -pin  "FRAME:acc#28" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(4)} -pin  "FRAME:acc#28" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#26.itm(0)} -pin  "FRAME:acc#28" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(1)} -pin  "FRAME:acc#28" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(2)} -pin  "FRAME:acc#28" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(3)} -pin  "FRAME:acc#28" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#28.itm(0)} -pin  "FRAME:acc#28" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(1)} -pin  "FRAME:acc#28" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(2)} -pin  "FRAME:acc#28" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(3)} -pin  "FRAME:acc#28" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(4)} -pin  "FRAME:acc#28" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(5)} -pin  "FRAME:acc#28" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load inst "acc#13" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 44670 -attr oid 546 -attr vt d -attr @path {/sobel/sobel:core/acc#13} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {FRAME:acc#28.itm(0)} -pin  "acc#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(1)} -pin  "acc#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(2)} -pin  "acc#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(3)} -pin  "acc#13" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(4)} -pin  "acc#13" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(5)} -pin  "acc#13" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {PWR} -pin  "acc#13" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#13" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#13" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#13" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#13" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#13" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#13.sva(0)} -pin  "acc#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#13.sva}
+load net {acc.imod#13.sva(1)} -pin  "acc#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#13.sva}
+load net {acc.imod#13.sva(2)} -pin  "acc#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#13.sva}
+load net {acc.imod#13.sva(3)} -pin  "acc#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#13.sva}
+load net {acc.imod#13.sva(4)} -pin  "acc#13" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#13.sva}
+load net {acc.imod#13.sva(5)} -pin  "acc#13" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#13.sva}
+load inst "ACC2:acc#7" "add(15,-1,15,-1,15)" "INTERFACE" -attr xrf 44671 -attr oid 547 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7} -attr area 16.198770 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,15,0,15)"
+load net {g(1).sg1.lpi#1.dfm(0)} -pin  "ACC2:acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(1)} -pin  "ACC2:acc#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(2)} -pin  "ACC2:acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(3)} -pin  "ACC2:acc#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(4)} -pin  "ACC2:acc#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(5)} -pin  "ACC2:acc#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(6)} -pin  "ACC2:acc#7" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(7)} -pin  "ACC2:acc#7" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(8)} -pin  "ACC2:acc#7" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(9)} -pin  "ACC2:acc#7" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(10)} -pin  "ACC2:acc#7" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(11)} -pin  "ACC2:acc#7" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(12)} -pin  "ACC2:acc#7" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(13)} -pin  "ACC2:acc#7" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(14)} -pin  "ACC2:acc#7" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(2).sva#1(1)} -pin  "ACC2:acc#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(2)} -pin  "ACC2:acc#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(3)} -pin  "ACC2:acc#7" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(4)} -pin  "ACC2:acc#7" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(5)} -pin  "ACC2:acc#7" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(6)} -pin  "ACC2:acc#7" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(7)} -pin  "ACC2:acc#7" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(8)} -pin  "ACC2:acc#7" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(9)} -pin  "ACC2:acc#7" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(10)} -pin  "ACC2:acc#7" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(11)} -pin  "ACC2:acc#7" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(12)} -pin  "ACC2:acc#7" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(13)} -pin  "ACC2:acc#7" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(14)} -pin  "ACC2:acc#7" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(15)} -pin  "ACC2:acc#7" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {ACC2:acc#7.itm(0)} -pin  "ACC2:acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(1)} -pin  "ACC2:acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(2)} -pin  "ACC2:acc#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(3)} -pin  "ACC2:acc#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(4)} -pin  "ACC2:acc#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(5)} -pin  "ACC2:acc#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(6)} -pin  "ACC2:acc#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(7)} -pin  "ACC2:acc#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(8)} -pin  "ACC2:acc#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(9)} -pin  "ACC2:acc#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(10)} -pin  "ACC2:acc#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(11)} -pin  "ACC2:acc#7" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(12)} -pin  "ACC2:acc#7" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(13)} -pin  "ACC2:acc#7" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(14)} -pin  "ACC2:acc#7" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load inst "ACC2-3:acc#2" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 44672 -attr oid 548 -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {g(2).sva#1(0)} -pin  "ACC2-3:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(0)} -pin  "ACC2-3:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(1)} -pin  "ACC2-3:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(2)} -pin  "ACC2-3:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(3)} -pin  "ACC2-3:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(4)} -pin  "ACC2-3:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(5)} -pin  "ACC2-3:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(6)} -pin  "ACC2-3:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(7)} -pin  "ACC2-3:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(8)} -pin  "ACC2-3:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(9)} -pin  "ACC2-3:acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(10)} -pin  "ACC2-3:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(11)} -pin  "ACC2-3:acc#2" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(12)} -pin  "ACC2-3:acc#2" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(13)} -pin  "ACC2-3:acc#2" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(14)} -pin  "ACC2-3:acc#2" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {g(0).sva#1(0)} -pin  "ACC2-3:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(1)} -pin  "ACC2-3:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(2)} -pin  "ACC2-3:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(3)} -pin  "ACC2-3:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(4)} -pin  "ACC2-3:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(5)} -pin  "ACC2-3:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(6)} -pin  "ACC2-3:acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(7)} -pin  "ACC2-3:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(8)} -pin  "ACC2-3:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(9)} -pin  "ACC2-3:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(10)} -pin  "ACC2-3:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(11)} -pin  "ACC2-3:acc#2" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(12)} -pin  "ACC2-3:acc#2" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(13)} -pin  "ACC2-3:acc#2" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(14)} -pin  "ACC2-3:acc#2" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(15)} -pin  "ACC2-3:acc#2" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {ACC2-3:acc#2.itm(0)} -pin  "ACC2-3:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(1)} -pin  "ACC2-3:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(2)} -pin  "ACC2-3:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(3)} -pin  "ACC2-3:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(4)} -pin  "ACC2-3:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(5)} -pin  "ACC2-3:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(6)} -pin  "ACC2-3:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(7)} -pin  "ACC2-3:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(8)} -pin  "ACC2-3:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(9)} -pin  "ACC2-3:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(10)} -pin  "ACC2-3:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(11)} -pin  "ACC2-3:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(12)} -pin  "ACC2-3:acc#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(13)} -pin  "ACC2-3:acc#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(14)} -pin  "ACC2-3:acc#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(15)} -pin  "ACC2-3:acc#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load inst "FRAME:not#10" "not(3)" "INTERFACE" -attr xrf 44673 -attr oid 549 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#2.itm(10)} -pin  "FRAME:not#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {ACC2-3:acc#2.itm(11)} -pin  "FRAME:not#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {ACC2-3:acc#2.itm(12)} -pin  "FRAME:not#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {FRAME:not#10.itm(0)} -pin  "FRAME:not#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(1)} -pin  "FRAME:not#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(2)} -pin  "FRAME:not#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load inst "FRAME:acc#13" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 44674 -attr oid 550 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC2-3:acc#2.itm(7)} -pin  "FRAME:acc#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#2.itm(8)} -pin  "FRAME:acc#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#2.itm(9)} -pin  "FRAME:acc#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {FRAME:not#10.itm(0)} -pin  "FRAME:acc#13" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(1)} -pin  "FRAME:acc#13" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(2)} -pin  "FRAME:acc#13" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load inst "FRAME:not#37" "not(1)" "INTERFACE" -attr xrf 44675 -attr oid 551 -attr @path {/sobel/sobel:core/FRAME:not#37} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC2-3:acc#2.itm(15)} -pin  "FRAME:not#37" {A(0)} -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#12.itm}
+load net {FRAME:not#37.itm} -pin  "FRAME:not#37" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#37.itm}
+load inst "FRAME:not#49" "not(1)" "INTERFACE" -attr xrf 44676 -attr oid 552 -attr @path {/sobel/sobel:core/FRAME:not#49} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC2-3:acc#2.itm(15)} -pin  "FRAME:not#49" {A(0)} -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#7.itm}
+load net {FRAME:not#49.itm} -pin  "FRAME:not#49" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#49.itm}
+load inst "FRAME:acc#12" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 44677 -attr oid 553 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#49.itm} -pin  "FRAME:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {PWR} -pin  "FRAME:acc#12" {A(1)} -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {FRAME:not#37.itm} -pin  "FRAME:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC2-3:acc#2.itm(13)} -pin  "FRAME:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#4.itm}
+load net {ACC2-3:acc#2.itm(14)} -pin  "FRAME:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#4.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load inst "FRAME:acc#15" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 44678 -attr oid 554 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#15" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#15" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#15" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#15" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#15" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load inst "FRAME:not#9" "not(3)" "INTERFACE" -attr xrf 44679 -attr oid 555 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#2.itm(4)} -pin  "FRAME:not#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#2.itm(5)} -pin  "FRAME:not#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#2.itm(6)} -pin  "FRAME:not#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {FRAME:not#9.itm(0)} -pin  "FRAME:not#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(1)} -pin  "FRAME:not#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(2)} -pin  "FRAME:not#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load inst "FRAME:acc#14" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 44680 -attr oid 556 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC2-3:acc#2.itm(1)} -pin  "FRAME:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {ACC2-3:acc#2.itm(2)} -pin  "FRAME:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {ACC2-3:acc#2.itm(3)} -pin  "FRAME:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {FRAME:not#9.itm(0)} -pin  "FRAME:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(1)} -pin  "FRAME:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(2)} -pin  "FRAME:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load inst "FRAME:acc#16" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 44681 -attr oid 557 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16} -attr area 6.288444 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6)"
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#16" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#16" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#16" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#16" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#16" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#16" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#16.itm(0)} -pin  "FRAME:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "FRAME:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "FRAME:acc#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "FRAME:acc#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:acc#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(5)} -pin  "FRAME:acc#16" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load inst "acc#11" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 44682 -attr oid 558 -attr vt d -attr @path {/sobel/sobel:core/acc#11} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {FRAME:acc#16.itm(0)} -pin  "acc#11" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "acc#11" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "acc#11" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "acc#11" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "acc#11" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(5)} -pin  "acc#11" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {PWR} -pin  "acc#11" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#11" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#11" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#11" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#11" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#11" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#11.sva(0)} -pin  "acc#11" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#11.sva}
+load net {acc.imod#11.sva(1)} -pin  "acc#11" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#11.sva}
+load net {acc.imod#11.sva(2)} -pin  "acc#11" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#11.sva}
+load net {acc.imod#11.sva(3)} -pin  "acc#11" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#11.sva}
+load net {acc.imod#11.sva(4)} -pin  "acc#11" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#11.sva}
+load net {acc.imod#11.sva(5)} -pin  "acc#11" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#11.sva}
+load inst "FRAME:for:and#9" "and(2,15)" "INTERFACE" -attr xrf 44683 -attr oid 559 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#9} -attr area 10.947486 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(15,2)"
+load net {b(1).sg1.lpi#1(0)} -pin  "FRAME:for:and#9" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(1)} -pin  "FRAME:for:and#9" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(2)} -pin  "FRAME:for:and#9" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(3)} -pin  "FRAME:for:and#9" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(4)} -pin  "FRAME:for:and#9" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(5)} -pin  "FRAME:for:and#9" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(6)} -pin  "FRAME:for:and#9" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(7)} -pin  "FRAME:for:and#9" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(8)} -pin  "FRAME:for:and#9" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(9)} -pin  "FRAME:for:and#9" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(10)} -pin  "FRAME:for:and#9" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(11)} -pin  "FRAME:for:and#9" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(12)} -pin  "FRAME:for:and#9" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(13)} -pin  "FRAME:for:and#9" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(14)} -pin  "FRAME:for:and#9" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {b(1).sg1.lpi#1.dfm(0)} -pin  "FRAME:for:and#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(1)} -pin  "FRAME:for:and#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(2)} -pin  "FRAME:for:and#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(3)} -pin  "FRAME:for:and#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(4)} -pin  "FRAME:for:and#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(5)} -pin  "FRAME:for:and#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(6)} -pin  "FRAME:for:and#9" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(7)} -pin  "FRAME:for:and#9" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(8)} -pin  "FRAME:for:and#9" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(9)} -pin  "FRAME:for:and#9" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(10)} -pin  "FRAME:for:and#9" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(11)} -pin  "FRAME:for:and#9" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(12)} -pin  "FRAME:for:and#9" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(13)} -pin  "FRAME:for:and#9" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(14)} -pin  "FRAME:for:and#9" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load inst "regs.operator[]#35:mux" "mux(4,10)" "INTERFACE" -attr xrf 44684 -attr oid 560 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#35:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#35:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#35:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#35:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#35:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#35:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#35:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#35:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#35:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#35:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm(60)} -pin  "regs.operator[]#35:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(61)} -pin  "regs.operator[]#35:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(62)} -pin  "regs.operator[]#35:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(63)} -pin  "regs.operator[]#35:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(64)} -pin  "regs.operator[]#35:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(65)} -pin  "regs.operator[]#35:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(66)} -pin  "regs.operator[]#35:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(67)} -pin  "regs.operator[]#35:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(68)} -pin  "regs.operator[]#35:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(69)} -pin  "regs.operator[]#35:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(1).sva(60)} -pin  "regs.operator[]#35:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(61)} -pin  "regs.operator[]#35:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(62)} -pin  "regs.operator[]#35:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(63)} -pin  "regs.operator[]#35:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(64)} -pin  "regs.operator[]#35:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(65)} -pin  "regs.operator[]#35:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(66)} -pin  "regs.operator[]#35:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(67)} -pin  "regs.operator[]#35:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(68)} -pin  "regs.operator[]#35:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(69)} -pin  "regs.operator[]#35:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(0).sva(60)} -pin  "regs.operator[]#35:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(61)} -pin  "regs.operator[]#35:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(62)} -pin  "regs.operator[]#35:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(63)} -pin  "regs.operator[]#35:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(64)} -pin  "regs.operator[]#35:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(65)} -pin  "regs.operator[]#35:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(66)} -pin  "regs.operator[]#35:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(67)} -pin  "regs.operator[]#35:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(68)} -pin  "regs.operator[]#35:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(69)} -pin  "regs.operator[]#35:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {i#7.lpi#1(0)} -pin  "regs.operator[]#35:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "regs.operator[]#35:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.operator[]#35:mux.itm(0)} -pin  "regs.operator[]#35:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(1)} -pin  "regs.operator[]#35:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(2)} -pin  "regs.operator[]#35:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(3)} -pin  "regs.operator[]#35:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(4)} -pin  "regs.operator[]#35:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(5)} -pin  "regs.operator[]#35:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(6)} -pin  "regs.operator[]#35:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(7)} -pin  "regs.operator[]#35:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(8)} -pin  "regs.operator[]#35:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(9)} -pin  "regs.operator[]#35:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load inst "FRAME:for#1:mul#8" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 44685 -attr oid 561 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#35:mux.itm(0)} -pin  "FRAME:for#1:mul#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(1)} -pin  "FRAME:for#1:mul#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(2)} -pin  "FRAME:for#1:mul#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(3)} -pin  "FRAME:for#1:mul#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(4)} -pin  "FRAME:for#1:mul#8" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(5)} -pin  "FRAME:for#1:mul#8" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(6)} -pin  "FRAME:for#1:mul#8" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(7)} -pin  "FRAME:for#1:mul#8" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(8)} -pin  "FRAME:for#1:mul#8" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {regs.operator[]#35:mux.itm(9)} -pin  "FRAME:for#1:mul#8" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#35:mux.itm}
+load net {FRAME:for#1:or#1.itm} -pin  "FRAME:for#1:mul#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for#1:nor.cse} -pin  "FRAME:for#1:mul#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for#1:mul#8.itm(0)} -pin  "FRAME:for#1:mul#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(1)} -pin  "FRAME:for#1:mul#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(2)} -pin  "FRAME:for#1:mul#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(3)} -pin  "FRAME:for#1:mul#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(4)} -pin  "FRAME:for#1:mul#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(5)} -pin  "FRAME:for#1:mul#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(6)} -pin  "FRAME:for#1:mul#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(7)} -pin  "FRAME:for#1:mul#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(8)} -pin  "FRAME:for#1:mul#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(9)} -pin  "FRAME:for#1:mul#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(10)} -pin  "FRAME:for#1:mul#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load inst "FRAME:for#1:acc#14" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 44686 -attr oid 562 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc#14} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {b(2).lpi#1.dfm(0)} -pin  "FRAME:for#1:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(1)} -pin  "FRAME:for#1:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(2)} -pin  "FRAME:for#1:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(3)} -pin  "FRAME:for#1:acc#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(4)} -pin  "FRAME:for#1:acc#14" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(5)} -pin  "FRAME:for#1:acc#14" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(6)} -pin  "FRAME:for#1:acc#14" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(7)} -pin  "FRAME:for#1:acc#14" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(8)} -pin  "FRAME:for#1:acc#14" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(9)} -pin  "FRAME:for#1:acc#14" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(10)} -pin  "FRAME:for#1:acc#14" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(11)} -pin  "FRAME:for#1:acc#14" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(12)} -pin  "FRAME:for#1:acc#14" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(13)} -pin  "FRAME:for#1:acc#14" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(14)} -pin  "FRAME:for#1:acc#14" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(15)} -pin  "FRAME:for#1:acc#14" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {FRAME:for#1:mul#8.itm(0)} -pin  "FRAME:for#1:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(1)} -pin  "FRAME:for#1:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(2)} -pin  "FRAME:for#1:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(3)} -pin  "FRAME:for#1:acc#14" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(4)} -pin  "FRAME:for#1:acc#14" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(5)} -pin  "FRAME:for#1:acc#14" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(6)} -pin  "FRAME:for#1:acc#14" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(7)} -pin  "FRAME:for#1:acc#14" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(8)} -pin  "FRAME:for#1:acc#14" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(9)} -pin  "FRAME:for#1:acc#14" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(10)} -pin  "FRAME:for#1:acc#14" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {b(2).sva#1(0)} -pin  "FRAME:for#1:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(1)} -pin  "FRAME:for#1:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(2)} -pin  "FRAME:for#1:acc#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(3)} -pin  "FRAME:for#1:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(4)} -pin  "FRAME:for#1:acc#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(5)} -pin  "FRAME:for#1:acc#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(6)} -pin  "FRAME:for#1:acc#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(7)} -pin  "FRAME:for#1:acc#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(8)} -pin  "FRAME:for#1:acc#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(9)} -pin  "FRAME:for#1:acc#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(10)} -pin  "FRAME:for#1:acc#14" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(11)} -pin  "FRAME:for#1:acc#14" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(12)} -pin  "FRAME:for#1:acc#14" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(13)} -pin  "FRAME:for#1:acc#14" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(14)} -pin  "FRAME:for#1:acc#14" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(15)} -pin  "FRAME:for#1:acc#14" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load inst "regs.operator[]#29:mux" "mux(4,10)" "INTERFACE" -attr xrf 44687 -attr oid 563 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#29:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#29:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#29:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#29:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#29:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#29:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#29:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#29:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#29:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#29:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm(0)} -pin  "regs.operator[]#29:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(1)} -pin  "regs.operator[]#29:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(2)} -pin  "regs.operator[]#29:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(3)} -pin  "regs.operator[]#29:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(4)} -pin  "regs.operator[]#29:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(5)} -pin  "regs.operator[]#29:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(6)} -pin  "regs.operator[]#29:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(7)} -pin  "regs.operator[]#29:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(8)} -pin  "regs.operator[]#29:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(9)} -pin  "regs.operator[]#29:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(1).sva(0)} -pin  "regs.operator[]#29:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(1)} -pin  "regs.operator[]#29:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(2)} -pin  "regs.operator[]#29:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(3)} -pin  "regs.operator[]#29:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(4)} -pin  "regs.operator[]#29:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(5)} -pin  "regs.operator[]#29:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(6)} -pin  "regs.operator[]#29:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(7)} -pin  "regs.operator[]#29:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(8)} -pin  "regs.operator[]#29:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(9)} -pin  "regs.operator[]#29:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(0).sva(0)} -pin  "regs.operator[]#29:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(1)} -pin  "regs.operator[]#29:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(2)} -pin  "regs.operator[]#29:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(3)} -pin  "regs.operator[]#29:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(4)} -pin  "regs.operator[]#29:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(5)} -pin  "regs.operator[]#29:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(6)} -pin  "regs.operator[]#29:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(7)} -pin  "regs.operator[]#29:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(8)} -pin  "regs.operator[]#29:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(9)} -pin  "regs.operator[]#29:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {i#7.lpi#1(0)} -pin  "regs.operator[]#29:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "regs.operator[]#29:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.operator[]#29:mux.itm(0)} -pin  "regs.operator[]#29:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(1)} -pin  "regs.operator[]#29:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(2)} -pin  "regs.operator[]#29:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(3)} -pin  "regs.operator[]#29:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(4)} -pin  "regs.operator[]#29:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(5)} -pin  "regs.operator[]#29:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(6)} -pin  "regs.operator[]#29:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(7)} -pin  "regs.operator[]#29:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(8)} -pin  "regs.operator[]#29:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(9)} -pin  "regs.operator[]#29:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load inst "FRAME:for#1:mul#2" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 44688 -attr oid 564 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#29:mux.itm(0)} -pin  "FRAME:for#1:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(1)} -pin  "FRAME:for#1:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(2)} -pin  "FRAME:for#1:mul#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(3)} -pin  "FRAME:for#1:mul#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(4)} -pin  "FRAME:for#1:mul#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(5)} -pin  "FRAME:for#1:mul#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(6)} -pin  "FRAME:for#1:mul#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(7)} -pin  "FRAME:for#1:mul#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(8)} -pin  "FRAME:for#1:mul#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {regs.operator[]#29:mux.itm(9)} -pin  "FRAME:for#1:mul#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#29:mux.itm}
+load net {FRAME:for#1:or.itm} -pin  "FRAME:for#1:mul#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {PWR} -pin  "FRAME:for#1:mul#2" {B(1)} -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {FRAME:for#1:mul#2.itm(0)} -pin  "FRAME:for#1:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(1)} -pin  "FRAME:for#1:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(2)} -pin  "FRAME:for#1:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(3)} -pin  "FRAME:for#1:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(4)} -pin  "FRAME:for#1:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(5)} -pin  "FRAME:for#1:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(6)} -pin  "FRAME:for#1:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(7)} -pin  "FRAME:for#1:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(8)} -pin  "FRAME:for#1:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(9)} -pin  "FRAME:for#1:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(10)} -pin  "FRAME:for#1:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(11)} -pin  "FRAME:for#1:mul#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load inst "FRAME:for#1:acc#3" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 44689 -attr oid 565 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc#3} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {b(0).lpi#1.dfm(0)} -pin  "FRAME:for#1:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(1)} -pin  "FRAME:for#1:acc#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(2)} -pin  "FRAME:for#1:acc#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(3)} -pin  "FRAME:for#1:acc#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(4)} -pin  "FRAME:for#1:acc#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(5)} -pin  "FRAME:for#1:acc#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(6)} -pin  "FRAME:for#1:acc#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(7)} -pin  "FRAME:for#1:acc#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(8)} -pin  "FRAME:for#1:acc#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(9)} -pin  "FRAME:for#1:acc#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(10)} -pin  "FRAME:for#1:acc#3" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(11)} -pin  "FRAME:for#1:acc#3" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(12)} -pin  "FRAME:for#1:acc#3" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(13)} -pin  "FRAME:for#1:acc#3" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(14)} -pin  "FRAME:for#1:acc#3" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(15)} -pin  "FRAME:for#1:acc#3" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {FRAME:for#1:mul#2.itm(0)} -pin  "FRAME:for#1:acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(1)} -pin  "FRAME:for#1:acc#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(2)} -pin  "FRAME:for#1:acc#3" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(3)} -pin  "FRAME:for#1:acc#3" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(4)} -pin  "FRAME:for#1:acc#3" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(5)} -pin  "FRAME:for#1:acc#3" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(6)} -pin  "FRAME:for#1:acc#3" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(7)} -pin  "FRAME:for#1:acc#3" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(8)} -pin  "FRAME:for#1:acc#3" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(9)} -pin  "FRAME:for#1:acc#3" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(10)} -pin  "FRAME:for#1:acc#3" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(11)} -pin  "FRAME:for#1:acc#3" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {b(0).sva#1(0)} -pin  "FRAME:for#1:acc#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(1)} -pin  "FRAME:for#1:acc#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(2)} -pin  "FRAME:for#1:acc#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(3)} -pin  "FRAME:for#1:acc#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(4)} -pin  "FRAME:for#1:acc#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(5)} -pin  "FRAME:for#1:acc#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(6)} -pin  "FRAME:for#1:acc#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(7)} -pin  "FRAME:for#1:acc#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(8)} -pin  "FRAME:for#1:acc#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(9)} -pin  "FRAME:for#1:acc#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(10)} -pin  "FRAME:for#1:acc#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(11)} -pin  "FRAME:for#1:acc#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(12)} -pin  "FRAME:for#1:acc#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(13)} -pin  "FRAME:for#1:acc#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(14)} -pin  "FRAME:for#1:acc#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(15)} -pin  "FRAME:for#1:acc#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load inst "FRAME:for:and#8" "and(2,15)" "INTERFACE" -attr xrf 44690 -attr oid 566 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#8} -attr area 10.947486 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(15,2)"
+load net {g(1).sg1.lpi#1(0)} -pin  "FRAME:for:and#8" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(1)} -pin  "FRAME:for:and#8" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(2)} -pin  "FRAME:for:and#8" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(3)} -pin  "FRAME:for:and#8" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(4)} -pin  "FRAME:for:and#8" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(5)} -pin  "FRAME:for:and#8" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(6)} -pin  "FRAME:for:and#8" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(7)} -pin  "FRAME:for:and#8" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(8)} -pin  "FRAME:for:and#8" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(9)} -pin  "FRAME:for:and#8" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(10)} -pin  "FRAME:for:and#8" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(11)} -pin  "FRAME:for:and#8" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(12)} -pin  "FRAME:for:and#8" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(13)} -pin  "FRAME:for:and#8" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(14)} -pin  "FRAME:for:and#8" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {g(1).sg1.lpi#1.dfm(0)} -pin  "FRAME:for:and#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(1)} -pin  "FRAME:for:and#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(2)} -pin  "FRAME:for:and#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(3)} -pin  "FRAME:for:and#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(4)} -pin  "FRAME:for:and#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(5)} -pin  "FRAME:for:and#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(6)} -pin  "FRAME:for:and#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(7)} -pin  "FRAME:for:and#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(8)} -pin  "FRAME:for:and#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(9)} -pin  "FRAME:for:and#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(10)} -pin  "FRAME:for:and#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(11)} -pin  "FRAME:for:and#8" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(12)} -pin  "FRAME:for:and#8" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(13)} -pin  "FRAME:for:and#8" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(14)} -pin  "FRAME:for:and#8" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load inst "regs.operator[]#34:mux" "mux(4,10)" "INTERFACE" -attr xrf 44691 -attr oid 567 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#34:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#34:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#34:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#34:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#34:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#34:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#34:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#34:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#34:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#34:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm(70)} -pin  "regs.operator[]#34:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(71)} -pin  "regs.operator[]#34:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(72)} -pin  "regs.operator[]#34:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(73)} -pin  "regs.operator[]#34:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(74)} -pin  "regs.operator[]#34:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(75)} -pin  "regs.operator[]#34:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(76)} -pin  "regs.operator[]#34:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(77)} -pin  "regs.operator[]#34:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(78)} -pin  "regs.operator[]#34:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(79)} -pin  "regs.operator[]#34:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(1).sva(70)} -pin  "regs.operator[]#34:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(71)} -pin  "regs.operator[]#34:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(72)} -pin  "regs.operator[]#34:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(73)} -pin  "regs.operator[]#34:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(74)} -pin  "regs.operator[]#34:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(75)} -pin  "regs.operator[]#34:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(76)} -pin  "regs.operator[]#34:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(77)} -pin  "regs.operator[]#34:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(78)} -pin  "regs.operator[]#34:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(79)} -pin  "regs.operator[]#34:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(0).sva(70)} -pin  "regs.operator[]#34:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(71)} -pin  "regs.operator[]#34:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(72)} -pin  "regs.operator[]#34:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(73)} -pin  "regs.operator[]#34:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(74)} -pin  "regs.operator[]#34:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(75)} -pin  "regs.operator[]#34:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(76)} -pin  "regs.operator[]#34:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(77)} -pin  "regs.operator[]#34:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(78)} -pin  "regs.operator[]#34:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(79)} -pin  "regs.operator[]#34:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {i#7.lpi#1(0)} -pin  "regs.operator[]#34:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "regs.operator[]#34:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.operator[]#34:mux.itm(0)} -pin  "regs.operator[]#34:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(1)} -pin  "regs.operator[]#34:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(2)} -pin  "regs.operator[]#34:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(3)} -pin  "regs.operator[]#34:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(4)} -pin  "regs.operator[]#34:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(5)} -pin  "regs.operator[]#34:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(6)} -pin  "regs.operator[]#34:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(7)} -pin  "regs.operator[]#34:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(8)} -pin  "regs.operator[]#34:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(9)} -pin  "regs.operator[]#34:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load inst "FRAME:for#1:mul#7" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 44692 -attr oid 568 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#34:mux.itm(0)} -pin  "FRAME:for#1:mul#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(1)} -pin  "FRAME:for#1:mul#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(2)} -pin  "FRAME:for#1:mul#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(3)} -pin  "FRAME:for#1:mul#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(4)} -pin  "FRAME:for#1:mul#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(5)} -pin  "FRAME:for#1:mul#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(6)} -pin  "FRAME:for#1:mul#7" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(7)} -pin  "FRAME:for#1:mul#7" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(8)} -pin  "FRAME:for#1:mul#7" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {regs.operator[]#34:mux.itm(9)} -pin  "FRAME:for#1:mul#7" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#34:mux.itm}
+load net {FRAME:for#1:or#1.itm} -pin  "FRAME:for#1:mul#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for#1:nor.cse} -pin  "FRAME:for#1:mul#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for#1:mul#7.itm(0)} -pin  "FRAME:for#1:mul#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(1)} -pin  "FRAME:for#1:mul#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(2)} -pin  "FRAME:for#1:mul#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(3)} -pin  "FRAME:for#1:mul#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(4)} -pin  "FRAME:for#1:mul#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(5)} -pin  "FRAME:for#1:mul#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(6)} -pin  "FRAME:for#1:mul#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(7)} -pin  "FRAME:for#1:mul#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(8)} -pin  "FRAME:for#1:mul#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(9)} -pin  "FRAME:for#1:mul#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(10)} -pin  "FRAME:for#1:mul#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load inst "FRAME:for#1:acc#12" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 44693 -attr oid 569 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc#12} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {g(2).lpi#1.dfm(0)} -pin  "FRAME:for#1:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(1)} -pin  "FRAME:for#1:acc#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(2)} -pin  "FRAME:for#1:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(3)} -pin  "FRAME:for#1:acc#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(4)} -pin  "FRAME:for#1:acc#12" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(5)} -pin  "FRAME:for#1:acc#12" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(6)} -pin  "FRAME:for#1:acc#12" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(7)} -pin  "FRAME:for#1:acc#12" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(8)} -pin  "FRAME:for#1:acc#12" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(9)} -pin  "FRAME:for#1:acc#12" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(10)} -pin  "FRAME:for#1:acc#12" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(11)} -pin  "FRAME:for#1:acc#12" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(12)} -pin  "FRAME:for#1:acc#12" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(13)} -pin  "FRAME:for#1:acc#12" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(14)} -pin  "FRAME:for#1:acc#12" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(15)} -pin  "FRAME:for#1:acc#12" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {FRAME:for#1:mul#7.itm(0)} -pin  "FRAME:for#1:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(1)} -pin  "FRAME:for#1:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(2)} -pin  "FRAME:for#1:acc#12" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(3)} -pin  "FRAME:for#1:acc#12" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(4)} -pin  "FRAME:for#1:acc#12" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(5)} -pin  "FRAME:for#1:acc#12" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(6)} -pin  "FRAME:for#1:acc#12" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(7)} -pin  "FRAME:for#1:acc#12" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(8)} -pin  "FRAME:for#1:acc#12" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(9)} -pin  "FRAME:for#1:acc#12" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(10)} -pin  "FRAME:for#1:acc#12" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {g(2).sva#1(0)} -pin  "FRAME:for#1:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(1)} -pin  "FRAME:for#1:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(2)} -pin  "FRAME:for#1:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(3)} -pin  "FRAME:for#1:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(4)} -pin  "FRAME:for#1:acc#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(5)} -pin  "FRAME:for#1:acc#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(6)} -pin  "FRAME:for#1:acc#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(7)} -pin  "FRAME:for#1:acc#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(8)} -pin  "FRAME:for#1:acc#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(9)} -pin  "FRAME:for#1:acc#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(10)} -pin  "FRAME:for#1:acc#12" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(11)} -pin  "FRAME:for#1:acc#12" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(12)} -pin  "FRAME:for#1:acc#12" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(13)} -pin  "FRAME:for#1:acc#12" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(14)} -pin  "FRAME:for#1:acc#12" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(15)} -pin  "FRAME:for#1:acc#12" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load inst "regs.operator[]#28:mux" "mux(4,10)" "INTERFACE" -attr xrf 44694 -attr oid 570 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#28:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#28:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#28:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#28:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#28:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#28:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#28:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#28:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#28:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#28:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm(10)} -pin  "regs.operator[]#28:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(11)} -pin  "regs.operator[]#28:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(12)} -pin  "regs.operator[]#28:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(13)} -pin  "regs.operator[]#28:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(14)} -pin  "regs.operator[]#28:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(15)} -pin  "regs.operator[]#28:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(16)} -pin  "regs.operator[]#28:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(17)} -pin  "regs.operator[]#28:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(18)} -pin  "regs.operator[]#28:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(19)} -pin  "regs.operator[]#28:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(1).sva(10)} -pin  "regs.operator[]#28:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(11)} -pin  "regs.operator[]#28:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(12)} -pin  "regs.operator[]#28:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(13)} -pin  "regs.operator[]#28:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(14)} -pin  "regs.operator[]#28:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(15)} -pin  "regs.operator[]#28:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(16)} -pin  "regs.operator[]#28:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(17)} -pin  "regs.operator[]#28:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(18)} -pin  "regs.operator[]#28:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(19)} -pin  "regs.operator[]#28:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(0).sva(10)} -pin  "regs.operator[]#28:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(11)} -pin  "regs.operator[]#28:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(12)} -pin  "regs.operator[]#28:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(13)} -pin  "regs.operator[]#28:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(14)} -pin  "regs.operator[]#28:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(15)} -pin  "regs.operator[]#28:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(16)} -pin  "regs.operator[]#28:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(17)} -pin  "regs.operator[]#28:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(18)} -pin  "regs.operator[]#28:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(19)} -pin  "regs.operator[]#28:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {i#7.lpi#1(0)} -pin  "regs.operator[]#28:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "regs.operator[]#28:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.operator[]#28:mux.itm(0)} -pin  "regs.operator[]#28:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(1)} -pin  "regs.operator[]#28:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(2)} -pin  "regs.operator[]#28:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(3)} -pin  "regs.operator[]#28:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(4)} -pin  "regs.operator[]#28:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(5)} -pin  "regs.operator[]#28:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(6)} -pin  "regs.operator[]#28:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(7)} -pin  "regs.operator[]#28:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(8)} -pin  "regs.operator[]#28:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(9)} -pin  "regs.operator[]#28:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load inst "FRAME:for#1:mul#1" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 44695 -attr oid 571 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#28:mux.itm(0)} -pin  "FRAME:for#1:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(1)} -pin  "FRAME:for#1:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(2)} -pin  "FRAME:for#1:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(3)} -pin  "FRAME:for#1:mul#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(4)} -pin  "FRAME:for#1:mul#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(5)} -pin  "FRAME:for#1:mul#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(6)} -pin  "FRAME:for#1:mul#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(7)} -pin  "FRAME:for#1:mul#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(8)} -pin  "FRAME:for#1:mul#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {regs.operator[]#28:mux.itm(9)} -pin  "FRAME:for#1:mul#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#28:mux.itm}
+load net {FRAME:for#1:or.itm} -pin  "FRAME:for#1:mul#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {PWR} -pin  "FRAME:for#1:mul#1" {B(1)} -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {FRAME:for#1:mul#1.itm(0)} -pin  "FRAME:for#1:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(1)} -pin  "FRAME:for#1:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(2)} -pin  "FRAME:for#1:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(3)} -pin  "FRAME:for#1:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(4)} -pin  "FRAME:for#1:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(5)} -pin  "FRAME:for#1:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(6)} -pin  "FRAME:for#1:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(7)} -pin  "FRAME:for#1:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(8)} -pin  "FRAME:for#1:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(9)} -pin  "FRAME:for#1:mul#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(10)} -pin  "FRAME:for#1:mul#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(11)} -pin  "FRAME:for#1:mul#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load inst "FRAME:for#1:acc#2" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 44696 -attr oid 572 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc#2} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {g(0).lpi#1.dfm(0)} -pin  "FRAME:for#1:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(1)} -pin  "FRAME:for#1:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(2)} -pin  "FRAME:for#1:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(3)} -pin  "FRAME:for#1:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(4)} -pin  "FRAME:for#1:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(5)} -pin  "FRAME:for#1:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(6)} -pin  "FRAME:for#1:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(7)} -pin  "FRAME:for#1:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(8)} -pin  "FRAME:for#1:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(9)} -pin  "FRAME:for#1:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(10)} -pin  "FRAME:for#1:acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(11)} -pin  "FRAME:for#1:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(12)} -pin  "FRAME:for#1:acc#2" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(13)} -pin  "FRAME:for#1:acc#2" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(14)} -pin  "FRAME:for#1:acc#2" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(15)} -pin  "FRAME:for#1:acc#2" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {FRAME:for#1:mul#1.itm(0)} -pin  "FRAME:for#1:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(1)} -pin  "FRAME:for#1:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(2)} -pin  "FRAME:for#1:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(3)} -pin  "FRAME:for#1:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(4)} -pin  "FRAME:for#1:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(5)} -pin  "FRAME:for#1:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(6)} -pin  "FRAME:for#1:acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(7)} -pin  "FRAME:for#1:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(8)} -pin  "FRAME:for#1:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(9)} -pin  "FRAME:for#1:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(10)} -pin  "FRAME:for#1:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(11)} -pin  "FRAME:for#1:acc#2" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {g(0).sva#1(0)} -pin  "FRAME:for#1:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(1)} -pin  "FRAME:for#1:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(2)} -pin  "FRAME:for#1:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(3)} -pin  "FRAME:for#1:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(4)} -pin  "FRAME:for#1:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(5)} -pin  "FRAME:for#1:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(6)} -pin  "FRAME:for#1:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(7)} -pin  "FRAME:for#1:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(8)} -pin  "FRAME:for#1:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(9)} -pin  "FRAME:for#1:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(10)} -pin  "FRAME:for#1:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(11)} -pin  "FRAME:for#1:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(12)} -pin  "FRAME:for#1:acc#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(13)} -pin  "FRAME:for#1:acc#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(14)} -pin  "FRAME:for#1:acc#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(15)} -pin  "FRAME:for#1:acc#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load inst "FRAME:for:and#7" "and(2,15)" "INTERFACE" -attr xrf 44697 -attr oid 573 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#7} -attr area 10.947486 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(15,2)"
+load net {r(1).sg1.lpi#1(0)} -pin  "FRAME:for:and#7" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(1)} -pin  "FRAME:for:and#7" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(2)} -pin  "FRAME:for:and#7" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(3)} -pin  "FRAME:for:and#7" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(4)} -pin  "FRAME:for:and#7" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(5)} -pin  "FRAME:for:and#7" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(6)} -pin  "FRAME:for:and#7" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(7)} -pin  "FRAME:for:and#7" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(8)} -pin  "FRAME:for:and#7" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(9)} -pin  "FRAME:for:and#7" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(10)} -pin  "FRAME:for:and#7" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(11)} -pin  "FRAME:for:and#7" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(12)} -pin  "FRAME:for:and#7" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(13)} -pin  "FRAME:for:and#7" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(14)} -pin  "FRAME:for:and#7" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {r(1).sg1.lpi#1.dfm(0)} -pin  "FRAME:for:and#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(1)} -pin  "FRAME:for:and#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(2)} -pin  "FRAME:for:and#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(3)} -pin  "FRAME:for:and#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(4)} -pin  "FRAME:for:and#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(5)} -pin  "FRAME:for:and#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(6)} -pin  "FRAME:for:and#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(7)} -pin  "FRAME:for:and#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(8)} -pin  "FRAME:for:and#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(9)} -pin  "FRAME:for:and#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(10)} -pin  "FRAME:for:and#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(11)} -pin  "FRAME:for:and#7" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(12)} -pin  "FRAME:for:and#7" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(13)} -pin  "FRAME:for:and#7" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(14)} -pin  "FRAME:for:and#7" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load inst "regs.operator[]#33:mux" "mux(4,10)" "INTERFACE" -attr xrf 44698 -attr oid 574 -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#33:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#33:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#33:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#33:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#33:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#33:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#33:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#33:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#33:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#33:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm(80)} -pin  "regs.operator[]#33:mux" {A1(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(81)} -pin  "regs.operator[]#33:mux" {A1(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(82)} -pin  "regs.operator[]#33:mux" {A1(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(83)} -pin  "regs.operator[]#33:mux" {A1(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(84)} -pin  "regs.operator[]#33:mux" {A1(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(85)} -pin  "regs.operator[]#33:mux" {A1(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(86)} -pin  "regs.operator[]#33:mux" {A1(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(87)} -pin  "regs.operator[]#33:mux" {A1(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(88)} -pin  "regs.operator[]#33:mux" {A1(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(89)} -pin  "regs.operator[]#33:mux" {A1(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(1).sva(80)} -pin  "regs.operator[]#33:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(81)} -pin  "regs.operator[]#33:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(82)} -pin  "regs.operator[]#33:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(83)} -pin  "regs.operator[]#33:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(84)} -pin  "regs.operator[]#33:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(85)} -pin  "regs.operator[]#33:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(86)} -pin  "regs.operator[]#33:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(87)} -pin  "regs.operator[]#33:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(88)} -pin  "regs.operator[]#33:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(89)} -pin  "regs.operator[]#33:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(0).sva(80)} -pin  "regs.operator[]#33:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(81)} -pin  "regs.operator[]#33:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(82)} -pin  "regs.operator[]#33:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(83)} -pin  "regs.operator[]#33:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(84)} -pin  "regs.operator[]#33:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(85)} -pin  "regs.operator[]#33:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(86)} -pin  "regs.operator[]#33:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(87)} -pin  "regs.operator[]#33:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(88)} -pin  "regs.operator[]#33:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(89)} -pin  "regs.operator[]#33:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {i#7.lpi#1(0)} -pin  "regs.operator[]#33:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "regs.operator[]#33:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.operator[]#33:mux.itm(0)} -pin  "regs.operator[]#33:mux" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(1)} -pin  "regs.operator[]#33:mux" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(2)} -pin  "regs.operator[]#33:mux" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(3)} -pin  "regs.operator[]#33:mux" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(4)} -pin  "regs.operator[]#33:mux" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(5)} -pin  "regs.operator[]#33:mux" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(6)} -pin  "regs.operator[]#33:mux" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(7)} -pin  "regs.operator[]#33:mux" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(8)} -pin  "regs.operator[]#33:mux" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(9)} -pin  "regs.operator[]#33:mux" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load inst "FRAME:for#1:mul#6" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 44699 -attr oid 575 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#33:mux.itm(0)} -pin  "FRAME:for#1:mul#6" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(1)} -pin  "FRAME:for#1:mul#6" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(2)} -pin  "FRAME:for#1:mul#6" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(3)} -pin  "FRAME:for#1:mul#6" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(4)} -pin  "FRAME:for#1:mul#6" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(5)} -pin  "FRAME:for#1:mul#6" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(6)} -pin  "FRAME:for#1:mul#6" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(7)} -pin  "FRAME:for#1:mul#6" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(8)} -pin  "FRAME:for#1:mul#6" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {regs.operator[]#33:mux.itm(9)} -pin  "FRAME:for#1:mul#6" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#33:mux.itm}
+load net {FRAME:for#1:or#1.itm} -pin  "FRAME:for#1:mul#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for#1:nor.cse} -pin  "FRAME:for#1:mul#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for#1:mul#6.itm(0)} -pin  "FRAME:for#1:mul#6" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(1)} -pin  "FRAME:for#1:mul#6" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(2)} -pin  "FRAME:for#1:mul#6" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(3)} -pin  "FRAME:for#1:mul#6" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(4)} -pin  "FRAME:for#1:mul#6" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(5)} -pin  "FRAME:for#1:mul#6" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(6)} -pin  "FRAME:for#1:mul#6" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(7)} -pin  "FRAME:for#1:mul#6" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(8)} -pin  "FRAME:for#1:mul#6" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(9)} -pin  "FRAME:for#1:mul#6" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(10)} -pin  "FRAME:for#1:mul#6" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load inst "FRAME:for#1:acc#10" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 44700 -attr oid 576 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:acc#10} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {r(2).lpi#1.dfm(0)} -pin  "FRAME:for#1:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(1)} -pin  "FRAME:for#1:acc#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(2)} -pin  "FRAME:for#1:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(3)} -pin  "FRAME:for#1:acc#10" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(4)} -pin  "FRAME:for#1:acc#10" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(5)} -pin  "FRAME:for#1:acc#10" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(6)} -pin  "FRAME:for#1:acc#10" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(7)} -pin  "FRAME:for#1:acc#10" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(8)} -pin  "FRAME:for#1:acc#10" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(9)} -pin  "FRAME:for#1:acc#10" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(10)} -pin  "FRAME:for#1:acc#10" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(11)} -pin  "FRAME:for#1:acc#10" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(12)} -pin  "FRAME:for#1:acc#10" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(13)} -pin  "FRAME:for#1:acc#10" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(14)} -pin  "FRAME:for#1:acc#10" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(15)} -pin  "FRAME:for#1:acc#10" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {FRAME:for#1:mul#6.itm(0)} -pin  "FRAME:for#1:acc#10" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(1)} -pin  "FRAME:for#1:acc#10" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(2)} -pin  "FRAME:for#1:acc#10" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(3)} -pin  "FRAME:for#1:acc#10" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(4)} -pin  "FRAME:for#1:acc#10" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(5)} -pin  "FRAME:for#1:acc#10" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(6)} -pin  "FRAME:for#1:acc#10" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(7)} -pin  "FRAME:for#1:acc#10" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(8)} -pin  "FRAME:for#1:acc#10" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(9)} -pin  "FRAME:for#1:acc#10" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(10)} -pin  "FRAME:for#1:acc#10" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {r(2).sva#1(0)} -pin  "FRAME:for#1:acc#10" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(1)} -pin  "FRAME:for#1:acc#10" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(2)} -pin  "FRAME:for#1:acc#10" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(3)} -pin  "FRAME:for#1:acc#10" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(4)} -pin  "FRAME:for#1:acc#10" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(5)} -pin  "FRAME:for#1:acc#10" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(6)} -pin  "FRAME:for#1:acc#10" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(7)} -pin  "FRAME:for#1:acc#10" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(8)} -pin  "FRAME:for#1:acc#10" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(9)} -pin  "FRAME:for#1:acc#10" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(10)} -pin  "FRAME:for#1:acc#10" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(11)} -pin  "FRAME:for#1:acc#10" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(12)} -pin  "FRAME:for#1:acc#10" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(13)} -pin  "FRAME:for#1:acc#10" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(14)} -pin  "FRAME:for#1:acc#10" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(15)} -pin  "FRAME:for#1:acc#10" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load inst "regs.operator[]#27:mux" "mux(4,10)" "INTERFACE" -attr xrf 44701 -attr oid 577 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#27:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#27:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#27:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#27:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#27:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#27:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#27:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#27:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#27:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#27:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm(20)} -pin  "regs.operator[]#27:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(21)} -pin  "regs.operator[]#27:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(22)} -pin  "regs.operator[]#27:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(23)} -pin  "regs.operator[]#27:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(24)} -pin  "regs.operator[]#27:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(25)} -pin  "regs.operator[]#27:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(26)} -pin  "regs.operator[]#27:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(27)} -pin  "regs.operator[]#27:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(28)} -pin  "regs.operator[]#27:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(29)} -pin  "regs.operator[]#27:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(1).sva(20)} -pin  "regs.operator[]#27:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(21)} -pin  "regs.operator[]#27:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(22)} -pin  "regs.operator[]#27:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(23)} -pin  "regs.operator[]#27:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(24)} -pin  "regs.operator[]#27:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(25)} -pin  "regs.operator[]#27:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(26)} -pin  "regs.operator[]#27:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(27)} -pin  "regs.operator[]#27:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(28)} -pin  "regs.operator[]#27:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(29)} -pin  "regs.operator[]#27:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(0).sva(20)} -pin  "regs.operator[]#27:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(21)} -pin  "regs.operator[]#27:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(22)} -pin  "regs.operator[]#27:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(23)} -pin  "regs.operator[]#27:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(24)} -pin  "regs.operator[]#27:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(25)} -pin  "regs.operator[]#27:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(26)} -pin  "regs.operator[]#27:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(27)} -pin  "regs.operator[]#27:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(28)} -pin  "regs.operator[]#27:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(29)} -pin  "regs.operator[]#27:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {i#7.lpi#1(0)} -pin  "regs.operator[]#27:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "regs.operator[]#27:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.operator[]#27:mux.itm(0)} -pin  "regs.operator[]#27:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(1)} -pin  "regs.operator[]#27:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(2)} -pin  "regs.operator[]#27:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(3)} -pin  "regs.operator[]#27:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(4)} -pin  "regs.operator[]#27:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(5)} -pin  "regs.operator[]#27:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(6)} -pin  "regs.operator[]#27:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(7)} -pin  "regs.operator[]#27:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(8)} -pin  "regs.operator[]#27:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(9)} -pin  "regs.operator[]#27:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load inst "FRAME:for#1:mul" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 44702 -attr oid 578 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#27:mux.itm(0)} -pin  "FRAME:for#1:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(1)} -pin  "FRAME:for#1:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(2)} -pin  "FRAME:for#1:mul" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(3)} -pin  "FRAME:for#1:mul" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(4)} -pin  "FRAME:for#1:mul" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(5)} -pin  "FRAME:for#1:mul" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(6)} -pin  "FRAME:for#1:mul" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(7)} -pin  "FRAME:for#1:mul" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(8)} -pin  "FRAME:for#1:mul" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {regs.operator[]#27:mux.itm(9)} -pin  "FRAME:for#1:mul" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#27:mux.itm}
+load net {FRAME:for#1:or.itm} -pin  "FRAME:for#1:mul" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {PWR} -pin  "FRAME:for#1:mul" {B(1)} -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {FRAME:for#1:mul.itm(0)} -pin  "FRAME:for#1:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(1)} -pin  "FRAME:for#1:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(2)} -pin  "FRAME:for#1:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(3)} -pin  "FRAME:for#1:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(4)} -pin  "FRAME:for#1:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(5)} -pin  "FRAME:for#1:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(6)} -pin  "FRAME:for#1:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(7)} -pin  "FRAME:for#1:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(8)} -pin  "FRAME:for#1:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(9)} -pin  "FRAME:for#1:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(10)} -pin  "FRAME:for#1:mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(11)} -pin  "FRAME:for#1:mul" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load inst "FRAME:for#1:acc#1" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 44703 -attr oid 579 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc#1} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {r(0).lpi#1.dfm(0)} -pin  "FRAME:for#1:acc#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(1)} -pin  "FRAME:for#1:acc#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(2)} -pin  "FRAME:for#1:acc#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(3)} -pin  "FRAME:for#1:acc#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(4)} -pin  "FRAME:for#1:acc#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(5)} -pin  "FRAME:for#1:acc#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(6)} -pin  "FRAME:for#1:acc#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(7)} -pin  "FRAME:for#1:acc#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(8)} -pin  "FRAME:for#1:acc#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(9)} -pin  "FRAME:for#1:acc#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(10)} -pin  "FRAME:for#1:acc#1" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(11)} -pin  "FRAME:for#1:acc#1" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(12)} -pin  "FRAME:for#1:acc#1" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(13)} -pin  "FRAME:for#1:acc#1" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(14)} -pin  "FRAME:for#1:acc#1" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(15)} -pin  "FRAME:for#1:acc#1" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {FRAME:for#1:mul.itm(0)} -pin  "FRAME:for#1:acc#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(1)} -pin  "FRAME:for#1:acc#1" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(2)} -pin  "FRAME:for#1:acc#1" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(3)} -pin  "FRAME:for#1:acc#1" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(4)} -pin  "FRAME:for#1:acc#1" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(5)} -pin  "FRAME:for#1:acc#1" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(6)} -pin  "FRAME:for#1:acc#1" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(7)} -pin  "FRAME:for#1:acc#1" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(8)} -pin  "FRAME:for#1:acc#1" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(9)} -pin  "FRAME:for#1:acc#1" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(10)} -pin  "FRAME:for#1:acc#1" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(11)} -pin  "FRAME:for#1:acc#1" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {r(0).sva#1(0)} -pin  "FRAME:for#1:acc#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(1)} -pin  "FRAME:for#1:acc#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(2)} -pin  "FRAME:for#1:acc#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(3)} -pin  "FRAME:for#1:acc#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(4)} -pin  "FRAME:for#1:acc#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(5)} -pin  "FRAME:for#1:acc#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(6)} -pin  "FRAME:for#1:acc#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(7)} -pin  "FRAME:for#1:acc#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(8)} -pin  "FRAME:for#1:acc#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(9)} -pin  "FRAME:for#1:acc#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(10)} -pin  "FRAME:for#1:acc#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(11)} -pin  "FRAME:for#1:acc#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(12)} -pin  "FRAME:for#1:acc#1" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(13)} -pin  "FRAME:for#1:acc#1" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(14)} -pin  "FRAME:for#1:acc#1" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(15)} -pin  "FRAME:for#1:acc#1" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load inst "FRAME:for:and#5" "and(2,16)" "INTERFACE" -attr xrf 44704 -attr oid 580 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#5} -attr area 11.677318 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2)"
+load net {b(2).lpi#1(0)} -pin  "FRAME:for:and#5" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(1)} -pin  "FRAME:for:and#5" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(2)} -pin  "FRAME:for:and#5" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(3)} -pin  "FRAME:for:and#5" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(4)} -pin  "FRAME:for:and#5" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(5)} -pin  "FRAME:for:and#5" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(6)} -pin  "FRAME:for:and#5" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(7)} -pin  "FRAME:for:and#5" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(8)} -pin  "FRAME:for:and#5" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(9)} -pin  "FRAME:for:and#5" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(10)} -pin  "FRAME:for:and#5" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(11)} -pin  "FRAME:for:and#5" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(12)} -pin  "FRAME:for:and#5" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(13)} -pin  "FRAME:for:and#5" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(14)} -pin  "FRAME:for:and#5" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(15)} -pin  "FRAME:for:and#5" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {b(2).lpi#1.dfm(0)} -pin  "FRAME:for:and#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(1)} -pin  "FRAME:for:and#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(2)} -pin  "FRAME:for:and#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(3)} -pin  "FRAME:for:and#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(4)} -pin  "FRAME:for:and#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(5)} -pin  "FRAME:for:and#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(6)} -pin  "FRAME:for:and#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(7)} -pin  "FRAME:for:and#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(8)} -pin  "FRAME:for:and#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(9)} -pin  "FRAME:for:and#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(10)} -pin  "FRAME:for:and#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(11)} -pin  "FRAME:for:and#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(12)} -pin  "FRAME:for:and#5" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(13)} -pin  "FRAME:for:and#5" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(14)} -pin  "FRAME:for:and#5" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(15)} -pin  "FRAME:for:and#5" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load inst "FRAME:for#1:nor" "nor(2,1)" "INTERFACE" -attr xrf 44705 -attr oid 581 -attr @path {/sobel/sobel:core/FRAME:for#1:nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {i#7.lpi#1(1)} -pin  "FRAME:for#1:nor" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#3.itm}
+load net {i#7.lpi#1(0)} -pin  "FRAME:for#1:nor" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#4.itm}
+load net {FRAME:for#1:nor.cse} -pin  "FRAME:for#1:nor" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nor.cse}
+load inst "FRAME:for:and#3" "and(2,16)" "INTERFACE" -attr xrf 44706 -attr oid 582 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#3} -attr area 11.677318 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2)"
+load net {g(2).lpi#1(0)} -pin  "FRAME:for:and#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(1)} -pin  "FRAME:for:and#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(2)} -pin  "FRAME:for:and#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(3)} -pin  "FRAME:for:and#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(4)} -pin  "FRAME:for:and#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(5)} -pin  "FRAME:for:and#3" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(6)} -pin  "FRAME:for:and#3" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(7)} -pin  "FRAME:for:and#3" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(8)} -pin  "FRAME:for:and#3" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(9)} -pin  "FRAME:for:and#3" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(10)} -pin  "FRAME:for:and#3" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(11)} -pin  "FRAME:for:and#3" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(12)} -pin  "FRAME:for:and#3" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(13)} -pin  "FRAME:for:and#3" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(14)} -pin  "FRAME:for:and#3" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(15)} -pin  "FRAME:for:and#3" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {g(2).lpi#1.dfm(0)} -pin  "FRAME:for:and#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(1)} -pin  "FRAME:for:and#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(2)} -pin  "FRAME:for:and#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(3)} -pin  "FRAME:for:and#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(4)} -pin  "FRAME:for:and#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(5)} -pin  "FRAME:for:and#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(6)} -pin  "FRAME:for:and#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(7)} -pin  "FRAME:for:and#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(8)} -pin  "FRAME:for:and#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(9)} -pin  "FRAME:for:and#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(10)} -pin  "FRAME:for:and#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(11)} -pin  "FRAME:for:and#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(12)} -pin  "FRAME:for:and#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(13)} -pin  "FRAME:for:and#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(14)} -pin  "FRAME:for:and#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(15)} -pin  "FRAME:for:and#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load inst "FRAME:for:and#1" "and(2,16)" "INTERFACE" -attr xrf 44707 -attr oid 583 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#1} -attr area 11.677318 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2)"
+load net {r(2).lpi#1(0)} -pin  "FRAME:for:and#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(1)} -pin  "FRAME:for:and#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(2)} -pin  "FRAME:for:and#1" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(3)} -pin  "FRAME:for:and#1" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(4)} -pin  "FRAME:for:and#1" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(5)} -pin  "FRAME:for:and#1" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(6)} -pin  "FRAME:for:and#1" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(7)} -pin  "FRAME:for:and#1" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(8)} -pin  "FRAME:for:and#1" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(9)} -pin  "FRAME:for:and#1" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(10)} -pin  "FRAME:for:and#1" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(11)} -pin  "FRAME:for:and#1" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(12)} -pin  "FRAME:for:and#1" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(13)} -pin  "FRAME:for:and#1" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(14)} -pin  "FRAME:for:and#1" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(15)} -pin  "FRAME:for:and#1" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {r(2).lpi#1.dfm(0)} -pin  "FRAME:for:and#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(1)} -pin  "FRAME:for:and#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(2)} -pin  "FRAME:for:and#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(3)} -pin  "FRAME:for:and#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(4)} -pin  "FRAME:for:and#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(5)} -pin  "FRAME:for:and#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(6)} -pin  "FRAME:for:and#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(7)} -pin  "FRAME:for:and#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(8)} -pin  "FRAME:for:and#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(9)} -pin  "FRAME:for:and#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(10)} -pin  "FRAME:for:and#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(11)} -pin  "FRAME:for:and#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(12)} -pin  "FRAME:for:and#1" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(13)} -pin  "FRAME:for:and#1" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(14)} -pin  "FRAME:for:and#1" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(15)} -pin  "FRAME:for:and#1" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load inst "FRAME:for:and#4" "and(2,16)" "INTERFACE" -attr xrf 44708 -attr oid 584 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#4} -attr area 11.677318 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2)"
+load net {b(0).lpi#1(0)} -pin  "FRAME:for:and#4" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(1)} -pin  "FRAME:for:and#4" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(2)} -pin  "FRAME:for:and#4" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(3)} -pin  "FRAME:for:and#4" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(4)} -pin  "FRAME:for:and#4" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(5)} -pin  "FRAME:for:and#4" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(6)} -pin  "FRAME:for:and#4" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(7)} -pin  "FRAME:for:and#4" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(8)} -pin  "FRAME:for:and#4" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(9)} -pin  "FRAME:for:and#4" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(10)} -pin  "FRAME:for:and#4" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(11)} -pin  "FRAME:for:and#4" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(12)} -pin  "FRAME:for:and#4" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(13)} -pin  "FRAME:for:and#4" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(14)} -pin  "FRAME:for:and#4" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(15)} -pin  "FRAME:for:and#4" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {b(0).lpi#1.dfm(0)} -pin  "FRAME:for:and#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(1)} -pin  "FRAME:for:and#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(2)} -pin  "FRAME:for:and#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(3)} -pin  "FRAME:for:and#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(4)} -pin  "FRAME:for:and#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(5)} -pin  "FRAME:for:and#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(6)} -pin  "FRAME:for:and#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(7)} -pin  "FRAME:for:and#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(8)} -pin  "FRAME:for:and#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(9)} -pin  "FRAME:for:and#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(10)} -pin  "FRAME:for:and#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(11)} -pin  "FRAME:for:and#4" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(12)} -pin  "FRAME:for:and#4" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(13)} -pin  "FRAME:for:and#4" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(14)} -pin  "FRAME:for:and#4" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(15)} -pin  "FRAME:for:and#4" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load inst "FRAME:for:and#2" "and(2,16)" "INTERFACE" -attr xrf 44709 -attr oid 585 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#2} -attr area 11.677318 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2)"
+load net {g(0).lpi#1(0)} -pin  "FRAME:for:and#2" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(1)} -pin  "FRAME:for:and#2" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(2)} -pin  "FRAME:for:and#2" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(3)} -pin  "FRAME:for:and#2" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(4)} -pin  "FRAME:for:and#2" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(5)} -pin  "FRAME:for:and#2" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(6)} -pin  "FRAME:for:and#2" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(7)} -pin  "FRAME:for:and#2" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(8)} -pin  "FRAME:for:and#2" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(9)} -pin  "FRAME:for:and#2" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(10)} -pin  "FRAME:for:and#2" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(11)} -pin  "FRAME:for:and#2" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(12)} -pin  "FRAME:for:and#2" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(13)} -pin  "FRAME:for:and#2" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(14)} -pin  "FRAME:for:and#2" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(15)} -pin  "FRAME:for:and#2" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {g(0).lpi#1.dfm(0)} -pin  "FRAME:for:and#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(1)} -pin  "FRAME:for:and#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(2)} -pin  "FRAME:for:and#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(3)} -pin  "FRAME:for:and#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(4)} -pin  "FRAME:for:and#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(5)} -pin  "FRAME:for:and#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(6)} -pin  "FRAME:for:and#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(7)} -pin  "FRAME:for:and#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(8)} -pin  "FRAME:for:and#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(9)} -pin  "FRAME:for:and#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(10)} -pin  "FRAME:for:and#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(11)} -pin  "FRAME:for:and#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(12)} -pin  "FRAME:for:and#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(13)} -pin  "FRAME:for:and#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(14)} -pin  "FRAME:for:and#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(15)} -pin  "FRAME:for:and#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load inst "FRAME:for:and" "and(2,16)" "INTERFACE" -attr xrf 44710 -attr oid 586 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and} -attr area 11.677318 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2)"
+load net {r(0).lpi#1(0)} -pin  "FRAME:for:and" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(1)} -pin  "FRAME:for:and" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(2)} -pin  "FRAME:for:and" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(3)} -pin  "FRAME:for:and" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(4)} -pin  "FRAME:for:and" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(5)} -pin  "FRAME:for:and" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(6)} -pin  "FRAME:for:and" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(7)} -pin  "FRAME:for:and" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(8)} -pin  "FRAME:for:and" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(9)} -pin  "FRAME:for:and" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(10)} -pin  "FRAME:for:and" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(11)} -pin  "FRAME:for:and" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(12)} -pin  "FRAME:for:and" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(13)} -pin  "FRAME:for:and" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(14)} -pin  "FRAME:for:and" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(15)} -pin  "FRAME:for:and" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {not#24} -pin  "FRAME:for:and" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {r(0).lpi#1.dfm(0)} -pin  "FRAME:for:and" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(1)} -pin  "FRAME:for:and" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(2)} -pin  "FRAME:for:and" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(3)} -pin  "FRAME:for:and" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(4)} -pin  "FRAME:for:and" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(5)} -pin  "FRAME:for:and" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(6)} -pin  "FRAME:for:and" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(7)} -pin  "FRAME:for:and" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(8)} -pin  "FRAME:for:and" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(9)} -pin  "FRAME:for:and" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(10)} -pin  "FRAME:for:and" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(11)} -pin  "FRAME:for:and" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(12)} -pin  "FRAME:for:and" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(13)} -pin  "FRAME:for:and" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(14)} -pin  "FRAME:for:and" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(15)} -pin  "FRAME:for:and" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load inst "FRAME:for:acc#16" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 44711 -attr oid 587 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#16} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:for:acc#16" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {i#6.sva#1(0)} -pin  "FRAME:for:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "FRAME:for:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load inst "FRAME:for:and#6" "and(2,2)" "INTERFACE" -attr xrf 44712 -attr oid 588 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#6} -attr area 1.459665 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2)"
+load net {i#6.lpi#1(0)} -pin  "FRAME:for:and#6" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1}
+load net {i#6.lpi#1(1)} -pin  "FRAME:for:and#6" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1}
+load net {not#24} -pin  "FRAME:for:and#6" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#26.itm}
+load net {not#24} -pin  "FRAME:for:and#6" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#26.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:and#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:and#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load inst "FRAME:for:nor" "nor(2,1)" "INTERFACE" -attr xrf 44713 -attr oid 589 -attr @path {/sobel/sobel:core/FRAME:for:nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:nor" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#2.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nor" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#3.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:nor" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load inst "FRAME:for:and#18" "and(2,1)" "INTERFACE" -attr xrf 44714 -attr oid 590 -attr @path {/sobel/sobel:core/FRAME:for:and#18} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {FRAME:for:acc#5.tmp(1)} -pin  "FRAME:for:and#18" {A0(0)} -attr @path {/sobel/sobel:core/slc(FRAME:for:acc#5.tmp).itm}
+load net {FRAME:for:acc#5.tmp(0)} -pin  "FRAME:for:and#18" {A1(0)} -attr @path {/sobel/sobel:core/slc(FRAME:for:acc#5.tmp)#1.itm}
+load net {FRAME:for:and#18.seb} -pin  "FRAME:for:and#18" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#18.seb}
+load inst "FRAME:for:acc#5" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 44715 -attr oid 591 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#5} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:acc#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:for:acc#5" {B(0)} -attr @path {/sobel/sobel:core/Cn1_1}
+load net {FRAME:for:acc#5.tmp(0)} -pin  "FRAME:for:acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#5.tmp}
+load net {FRAME:for:acc#5.tmp(1)} -pin  "FRAME:for:acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#5.tmp}
+load inst "nor#2" "nor(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/nor#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {exit:FRAME:for#1.lpi#1.dfm#4} -pin  "nor#2" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4}
+load net {exit:FRAME#1.sva} -pin  "nor#2" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {not#24} -pin  "nor#2" {Z(0)} -attr @path {/sobel/sobel:core/not#24}
+load inst "FRAME:for#1:not#8" "not(1)" "INTERFACE" -attr xrf 44716 -attr oid 592 -attr @path {/sobel/sobel:core/FRAME:for#1:not#8} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#7.lpi#1(1)} -pin  "FRAME:for#1:not#8" {A(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#7.itm}
+load net {FRAME:for#1:not#8.itm} -pin  "FRAME:for#1:not#8" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#8.itm}
+load inst "FRAME:for#1:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 44717 -attr oid 593 -attr @path {/sobel/sobel:core/FRAME:for#1:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {FRAME:for#1:not#8.itm} -pin  "FRAME:for#1:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#8.itm}
+load net {i#7.lpi#1(0)} -pin  "FRAME:for#1:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#8.itm}
+load net {FRAME:for#1:nand#1.itm} -pin  "FRAME:for#1:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nand#1.itm}
+load inst "FRAME:for#1:or#1" "or(2,1)" "INTERFACE" -attr xrf 44718 -attr oid 594 -attr @path {/sobel/sobel:core/FRAME:for#1:or#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {FRAME:for#1:nand#1.itm} -pin  "FRAME:for#1:or#1" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nand#1.itm}
+load net {FRAME:for#1:nor.cse} -pin  "FRAME:for#1:or#1" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nor.cse}
+load net {FRAME:for#1:or#1.itm} -pin  "FRAME:for#1:or#1" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:or#1.itm}
+load inst "FRAME:for#1:not#5" "not(1)" "INTERFACE" -attr xrf 44719 -attr oid 595 -attr @path {/sobel/sobel:core/FRAME:for#1:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#7.lpi#1(1)} -pin  "FRAME:for#1:not#5" {A(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#5.itm}
+load net {FRAME:for#1:not#5.itm} -pin  "FRAME:for#1:not#5" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#5.itm}
+load inst "FRAME:for#1:nand" "nand(2,1)" "INTERFACE" -attr xrf 44720 -attr oid 596 -attr @path {/sobel/sobel:core/FRAME:for#1:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {i#7.lpi#1(0)} -pin  "FRAME:for#1:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#9.itm}
+load net {FRAME:for#1:not#5.itm} -pin  "FRAME:for#1:nand" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#5.itm}
+load net {FRAME:for#1:nand.itm} -pin  "FRAME:for#1:nand" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nand.itm}
+load inst "FRAME:for#1:not#2" "not(1)" "INTERFACE" -attr xrf 44721 -attr oid 597 -attr @path {/sobel/sobel:core/FRAME:for#1:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#7.lpi#1(0)} -pin  "FRAME:for#1:not#2" {A(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#10.itm}
+load net {FRAME:for#1:not#2.itm} -pin  "FRAME:for#1:not#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#2.itm}
+load inst "FRAME:for#1:and" "and(2,1)" "INTERFACE" -attr xrf 44722 -attr oid 598 -attr @path {/sobel/sobel:core/FRAME:for#1:and} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {i#7.lpi#1(1)} -pin  "FRAME:for#1:and" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#6.itm}
+load net {FRAME:for#1:not#2.itm} -pin  "FRAME:for#1:and" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#2.itm}
+load net {FRAME:for#1:and.itm} -pin  "FRAME:for#1:and" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:and.itm}
+load inst "FRAME:for#1:or" "or(3,1)" "INTERFACE" -attr xrf 44723 -attr oid 599 -attr @path {/sobel/sobel:core/FRAME:for#1:or} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,3)"
+load net {FRAME:for#1:nand.itm} -pin  "FRAME:for#1:or" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nand.itm}
+load net {FRAME:for#1:nor.cse} -pin  "FRAME:for#1:or" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nor.cse}
+load net {FRAME:for#1:and.itm} -pin  "FRAME:for#1:or" {A2(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:and.itm}
+load net {FRAME:for#1:or.itm} -pin  "FRAME:for#1:or" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:or.itm}
+load inst "FRAME:for:not#6" "not(1)" "INTERFACE" -attr xrf 44724 -attr oid 600 -attr @path {/sobel/sobel:core/FRAME:for:not#6} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#6" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#5.itm}
+load net {FRAME:for:not#6.itm} -pin  "FRAME:for:not#6" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#6.itm}
+load inst "FRAME:for:nand#3" "nand(2,1)" "INTERFACE" -attr xrf 44725 -attr oid 601 -attr @path {/sobel/sobel:core/FRAME:for:nand#3} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {FRAME:for:not#6.itm} -pin  "FRAME:for:nand#3" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#6.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand#3" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#6.itm}
+load net {FRAME:for:nand#3.itm} -pin  "FRAME:for:nand#3" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#3.itm}
+load inst "FRAME:for:or#4" "or(2,1)" "INTERFACE" -attr xrf 44726 -attr oid 602 -attr @path {/sobel/sobel:core/FRAME:for:or#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {FRAME:for:nand#3.itm} -pin  "FRAME:for:or#4" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#3.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or#4" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:or#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#4.itm}
+load inst "FRAME:for:not#4" "not(1)" "INTERFACE" -attr xrf 44727 -attr oid 603 -attr @path {/sobel/sobel:core/FRAME:for:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#4" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#4.itm}
+load net {FRAME:for:not#4.itm} -pin  "FRAME:for:not#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#4.itm}
+load inst "FRAME:for:nand#2" "nand(2,1)" "INTERFACE" -attr xrf 44728 -attr oid 604 -attr @path {/sobel/sobel:core/FRAME:for:nand#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand#2" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#7.itm}
+load net {FRAME:for:not#4.itm} -pin  "FRAME:for:nand#2" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#4.itm}
+load net {FRAME:for:nand#2.itm} -pin  "FRAME:for:nand#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#2.itm}
+load inst "FRAME:for:or" "or(2,1)" "INTERFACE" -attr xrf 44729 -attr oid 605 -attr @path {/sobel/sobel:core/FRAME:for:or} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {FRAME:for:nand#2.itm} -pin  "FRAME:for:or" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#2.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:or.itm} -pin  "FRAME:for:or" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or.itm}
+load inst "FRAME:for:or#5" "or(3,1)" "INTERFACE" -attr xrf 44730 -attr oid 606 -attr @path {/sobel/sobel:core/FRAME:for:or#5} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,3)"
+load net {FRAME:for:acc#5.tmp(1)} -pin  "FRAME:for:or#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(FRAME:for:acc#5.tmp)#2.itm}
+load net {FRAME:for:acc#5.tmp(0)} -pin  "FRAME:for:or#5" {A1(0)} -attr @path {/sobel/sobel:core/slc(FRAME:for:acc#5.tmp)#3.itm}
+load net {FRAME:for:and#18.seb} -pin  "FRAME:for:or#5" {A2(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#18.seb}
+load net {FRAME:for:or#5.itm} -pin  "FRAME:for:or#5" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#5.itm}
+load inst "nor" "nor(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {exit:FRAME#1.sva} -pin  "nor" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {exit:FRAME:for#1.lpi#1.dfm#4} -pin  "nor" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4}
+load net {and.dcpl#1} -pin  "nor" {Z(0)} -attr @path {/sobel/sobel:core/and.dcpl#1}
+load inst "or#3" "or(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/or#3} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {exit:FRAME#1.sva} -pin  "or#3" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {exit:FRAME:for#1.lpi#1.dfm#4} -pin  "or#3" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4}
+load net {or.dcpl#2} -pin  "or#3" {Z(0)} -attr @path {/sobel/sobel:core/or.dcpl#2}
+load inst "not#35" "not(1)" "INTERFACE" -attr @path {/sobel/sobel:core/not#35} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1} -pin  "not#35" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1}
+load net {not#35.itm} -pin  "not#35" {Z(0)} -attr @path {/sobel/sobel:core/not#35.itm}
+load inst "or#4" "or(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/or#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {or.dcpl#2} -pin  "or#4" {A0(0)} -attr @path {/sobel/sobel:core/or.dcpl#2}
+load net {not#35.itm} -pin  "or#4" {A1(0)} -attr @path {/sobel/sobel:core/not#35.itm}
+load net {or#4.cse} -pin  "or#4" {Z(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load inst "not#31" "not(1)" "INTERFACE" -attr @path {/sobel/sobel:core/not#31} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1} -pin  "not#31" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1}
+load net {not#31.itm} -pin  "not#31" {Z(0)} -attr @path {/sobel/sobel:core/not#31.itm}
+load inst "or#9" "or(3,1)" "INTERFACE" -attr @path {/sobel/sobel:core/or#9} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,3)"
+load net {or.dcpl#2} -pin  "or#9" {A0(0)} -attr @path {/sobel/sobel:core/or.dcpl#2}
+load net {not#31.itm} -pin  "or#9" {A1(0)} -attr @path {/sobel/sobel:core/not#31.itm}
+load net {FRAME:for#1:acc.itm(1)} -pin  "or#9" {A2(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:slc#3.itm}
+load net {or#9.cse} -pin  "or#9" {Z(0)} -attr @path {/sobel/sobel:core/or#9.cse}
+load inst "FRAME:for:acc" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 44731 -attr oid 607 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2)"
+load net {i#6.sva#1(0)} -pin  "FRAME:for:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "FRAME:for:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {PWR} -pin  "FRAME:for:acc" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:for:acc.itm(0)} -pin  "FRAME:for:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+### END MODULE 
+
+module new "sobel" "orig"
+load portBus {vin:rsc.z(89:0)} input 90 {vin:rsc.z(89)} {vin:rsc.z(88)} {vin:rsc.z(87)} {vin:rsc.z(86)} {vin:rsc.z(85)} {vin:rsc.z(84)} {vin:rsc.z(83)} {vin:rsc.z(82)} {vin:rsc.z(81)} {vin:rsc.z(80)} {vin:rsc.z(79)} {vin:rsc.z(78)} {vin:rsc.z(77)} {vin:rsc.z(76)} {vin:rsc.z(75)} {vin:rsc.z(74)} {vin:rsc.z(73)} {vin:rsc.z(72)} {vin:rsc.z(71)} {vin:rsc.z(70)} {vin:rsc.z(69)} {vin:rsc.z(68)} {vin:rsc.z(67)} {vin:rsc.z(66)} {vin:rsc.z(65)} {vin:rsc.z(64)} {vin:rsc.z(63)} {vin:rsc.z(62)} {vin:rsc.z(61)} {vin:rsc.z(60)} {vin:rsc.z(59)} {vin:rsc.z(58)} {vin:rsc.z(57)} {vin:rsc.z(56)} {vin:rsc.z(55)} {vin:rsc.z(54)} {vin:rsc.z(53)} {vin:rsc.z(52)} {vin:rsc.z(51)} {vin:rsc.z(50)} {vin:rsc.z(49)} {vin:rsc.z(48)} {vin:rsc.z(47)} {vin:rsc.z(46)} {vin:rsc.z(45)} {vin:rsc.z(44)} {vin:rsc.z(43)} {vin:rsc.z(42)} {vin:rsc.z(41)} {vin:rsc.z(40)} {vin:rsc.z(39)} {vin:rsc.z(38)} {vin:rsc.z(37)} {vin:rsc.z(36)} {vin:rsc.z(35)} {vin:rsc.z(34)} {vin:rsc.z(33)} {vin:rsc.z(32)} {vin:rsc.z(31)} {vin:rsc.z(30)} {vin:rsc.z(29)} {vin:rsc.z(28)} {vin:rsc.z(27)} {vin:rsc.z(26)} {vin:rsc.z(25)} {vin:rsc.z(24)} {vin:rsc.z(23)} {vin:rsc.z(22)} {vin:rsc.z(21)} {vin:rsc.z(20)} {vin:rsc.z(19)} {vin:rsc.z(18)} {vin:rsc.z(17)} {vin:rsc.z(16)} {vin:rsc.z(15)} {vin:rsc.z(14)} {vin:rsc.z(13)} {vin:rsc.z(12)} {vin:rsc.z(11)} {vin:rsc.z(10)} {vin:rsc.z(9)} {vin:rsc.z(8)} {vin:rsc.z(7)} {vin:rsc.z(6)} {vin:rsc.z(5)} {vin:rsc.z(4)} {vin:rsc.z(3)} {vin:rsc.z(2)} {vin:rsc.z(1)} {vin:rsc.z(0)} -attr xrf 44732 -attr oid 608 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load portBus {vout:rsc.z(29:0)} output 30 {vout:rsc.z(29)} {vout:rsc.z(28)} {vout:rsc.z(27)} {vout:rsc.z(26)} {vout:rsc.z(25)} {vout:rsc.z(24)} {vout:rsc.z(23)} {vout:rsc.z(22)} {vout:rsc.z(21)} {vout:rsc.z(20)} {vout:rsc.z(19)} {vout:rsc.z(18)} {vout:rsc.z(17)} {vout:rsc.z(16)} {vout:rsc.z(15)} {vout:rsc.z(14)} {vout:rsc.z(13)} {vout:rsc.z(12)} {vout:rsc.z(11)} {vout:rsc.z(10)} {vout:rsc.z(9)} {vout:rsc.z(8)} {vout:rsc.z(7)} {vout:rsc.z(6)} {vout:rsc.z(5)} {vout:rsc.z(4)} {vout:rsc.z(3)} {vout:rsc.z(2)} {vout:rsc.z(1)} {vout:rsc.z(0)} -attr xrf 44733 -attr oid 609 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load port {clk} input -attr xrf 44734 -attr oid 610 -attr vt d -attr @path {/sobel/clk}
+load port {en} input -attr xrf 44735 -attr oid 611 -attr vt d -attr @path {/sobel/en}
+load port {arst_n} input -attr xrf 44736 -attr oid 612 -attr vt d -attr @path {/sobel/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(89:0)} output 90 {d(89)} {d(88)} {d(87)} {d(86)} {d(85)} {d(84)} {d(83)} {d(82)} {d(81)} {d(80)} {d(79)} {d(78)} {d(77)} {d(76)} {d(75)} {d(74)} {d(73)} {d(72)} {d(71)} {d(70)} {d(69)} {d(68)} {d(67)} {d(66)} {d(65)} {d(64)} {d(63)} {d(62)} {d(61)} {d(60)} {d(59)} {d(58)} {d(57)} {d(56)} {d(55)} {d(54)} {d(53)} {d(52)} {d(51)} {d(50)} {d(49)} {d(48)} {d(47)} {d(46)} {d(45)} {d(44)} {d(43)} {d(42)} {d(41)} {d(40)} {d(39)} {d(38)} {d(37)} {d(36)} {d(35)} {d(34)} {d(33)} {d(32)} {d(31)} {d(30)} {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(89:0)} input 90 {z(89)} {z(88)} {z(87)} {z(86)} {z(85)} {z(84)} {z(83)} {z(82)} {z(81)} {z(80)} {z(79)} {z(78)} {z(77)} {z(76)} {z(75)} {z(74)} {z(73)} {z(72)} {z(71)} {z(70)} {z(69)} {z(68)} {z(67)} {z(66)} {z(65)} {z(64)} {z(63)} {z(62)} {z(61)} {z(60)} {z(59)} {z(58)} {z(57)} {z(56)} {z(55)} {z(54)} {z(53)} {z(52)} {z(51)} {z(50)} {z(49)} {z(48)} {z(47)} {z(46)} {z(45)} {z(44)} {z(43)} {z(42)} {z(41)} {z(40)} {z(39)} {z(38)} {z(37)} {z(36)} {z(35)} {z(34)} {z(33)} {z(32)} {z(31)} {z(30)} {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(29:0)} input 30 {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(29:0)} output 30 {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "sobel:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} \
+     portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} \
+
+load net {vin:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d#1} 90 {vin:rsc:mgc_in_wire.d#1(0)} {vin:rsc:mgc_in_wire.d#1(1)} {vin:rsc:mgc_in_wire.d#1(2)} {vin:rsc:mgc_in_wire.d#1(3)} {vin:rsc:mgc_in_wire.d#1(4)} {vin:rsc:mgc_in_wire.d#1(5)} {vin:rsc:mgc_in_wire.d#1(6)} {vin:rsc:mgc_in_wire.d#1(7)} {vin:rsc:mgc_in_wire.d#1(8)} {vin:rsc:mgc_in_wire.d#1(9)} {vin:rsc:mgc_in_wire.d#1(10)} {vin:rsc:mgc_in_wire.d#1(11)} {vin:rsc:mgc_in_wire.d#1(12)} {vin:rsc:mgc_in_wire.d#1(13)} {vin:rsc:mgc_in_wire.d#1(14)} {vin:rsc:mgc_in_wire.d#1(15)} {vin:rsc:mgc_in_wire.d#1(16)} {vin:rsc:mgc_in_wire.d#1(17)} {vin:rsc:mgc_in_wire.d#1(18)} {vin:rsc:mgc_in_wire.d#1(19)} {vin:rsc:mgc_in_wire.d#1(20)} {vin:rsc:mgc_in_wire.d#1(21)} {vin:rsc:mgc_in_wire.d#1(22)} {vin:rsc:mgc_in_wire.d#1(23)} {vin:rsc:mgc_in_wire.d#1(24)} {vin:rsc:mgc_in_wire.d#1(25)} {vin:rsc:mgc_in_wire.d#1(26)} {vin:rsc:mgc_in_wire.d#1(27)} {vin:rsc:mgc_in_wire.d#1(28)} {vin:rsc:mgc_in_wire.d#1(29)} {vin:rsc:mgc_in_wire.d#1(30)} {vin:rsc:mgc_in_wire.d#1(31)} {vin:rsc:mgc_in_wire.d#1(32)} {vin:rsc:mgc_in_wire.d#1(33)} {vin:rsc:mgc_in_wire.d#1(34)} {vin:rsc:mgc_in_wire.d#1(35)} {vin:rsc:mgc_in_wire.d#1(36)} {vin:rsc:mgc_in_wire.d#1(37)} {vin:rsc:mgc_in_wire.d#1(38)} {vin:rsc:mgc_in_wire.d#1(39)} {vin:rsc:mgc_in_wire.d#1(40)} {vin:rsc:mgc_in_wire.d#1(41)} {vin:rsc:mgc_in_wire.d#1(42)} {vin:rsc:mgc_in_wire.d#1(43)} {vin:rsc:mgc_in_wire.d#1(44)} {vin:rsc:mgc_in_wire.d#1(45)} {vin:rsc:mgc_in_wire.d#1(46)} {vin:rsc:mgc_in_wire.d#1(47)} {vin:rsc:mgc_in_wire.d#1(48)} {vin:rsc:mgc_in_wire.d#1(49)} {vin:rsc:mgc_in_wire.d#1(50)} {vin:rsc:mgc_in_wire.d#1(51)} {vin:rsc:mgc_in_wire.d#1(52)} {vin:rsc:mgc_in_wire.d#1(53)} {vin:rsc:mgc_in_wire.d#1(54)} {vin:rsc:mgc_in_wire.d#1(55)} {vin:rsc:mgc_in_wire.d#1(56)} {vin:rsc:mgc_in_wire.d#1(57)} {vin:rsc:mgc_in_wire.d#1(58)} {vin:rsc:mgc_in_wire.d#1(59)} {vin:rsc:mgc_in_wire.d#1(60)} {vin:rsc:mgc_in_wire.d#1(61)} {vin:rsc:mgc_in_wire.d#1(62)} {vin:rsc:mgc_in_wire.d#1(63)} {vin:rsc:mgc_in_wire.d#1(64)} {vin:rsc:mgc_in_wire.d#1(65)} {vin:rsc:mgc_in_wire.d#1(66)} {vin:rsc:mgc_in_wire.d#1(67)} {vin:rsc:mgc_in_wire.d#1(68)} {vin:rsc:mgc_in_wire.d#1(69)} {vin:rsc:mgc_in_wire.d#1(70)} {vin:rsc:mgc_in_wire.d#1(71)} {vin:rsc:mgc_in_wire.d#1(72)} {vin:rsc:mgc_in_wire.d#1(73)} {vin:rsc:mgc_in_wire.d#1(74)} {vin:rsc:mgc_in_wire.d#1(75)} {vin:rsc:mgc_in_wire.d#1(76)} {vin:rsc:mgc_in_wire.d#1(77)} {vin:rsc:mgc_in_wire.d#1(78)} {vin:rsc:mgc_in_wire.d#1(79)} {vin:rsc:mgc_in_wire.d#1(80)} {vin:rsc:mgc_in_wire.d#1(81)} {vin:rsc:mgc_in_wire.d#1(82)} {vin:rsc:mgc_in_wire.d#1(83)} {vin:rsc:mgc_in_wire.d#1(84)} {vin:rsc:mgc_in_wire.d#1(85)} {vin:rsc:mgc_in_wire.d#1(86)} {vin:rsc:mgc_in_wire.d#1(87)} {vin:rsc:mgc_in_wire.d#1(88)} {vin:rsc:mgc_in_wire.d#1(89)} -attr xrf 44737 -attr oid 613 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -attr vt d
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+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -attr vt d
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+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d#1} 30 {vout:rsc:mgc_out_stdreg.d#1(0)} {vout:rsc:mgc_out_stdreg.d#1(1)} {vout:rsc:mgc_out_stdreg.d#1(2)} {vout:rsc:mgc_out_stdreg.d#1(3)} {vout:rsc:mgc_out_stdreg.d#1(4)} {vout:rsc:mgc_out_stdreg.d#1(5)} {vout:rsc:mgc_out_stdreg.d#1(6)} {vout:rsc:mgc_out_stdreg.d#1(7)} {vout:rsc:mgc_out_stdreg.d#1(8)} {vout:rsc:mgc_out_stdreg.d#1(9)} {vout:rsc:mgc_out_stdreg.d#1(10)} {vout:rsc:mgc_out_stdreg.d#1(11)} {vout:rsc:mgc_out_stdreg.d#1(12)} {vout:rsc:mgc_out_stdreg.d#1(13)} {vout:rsc:mgc_out_stdreg.d#1(14)} {vout:rsc:mgc_out_stdreg.d#1(15)} {vout:rsc:mgc_out_stdreg.d#1(16)} {vout:rsc:mgc_out_stdreg.d#1(17)} {vout:rsc:mgc_out_stdreg.d#1(18)} {vout:rsc:mgc_out_stdreg.d#1(19)} {vout:rsc:mgc_out_stdreg.d#1(20)} {vout:rsc:mgc_out_stdreg.d#1(21)} {vout:rsc:mgc_out_stdreg.d#1(22)} {vout:rsc:mgc_out_stdreg.d#1(23)} {vout:rsc:mgc_out_stdreg.d#1(24)} {vout:rsc:mgc_out_stdreg.d#1(25)} {vout:rsc:mgc_out_stdreg.d#1(26)} {vout:rsc:mgc_out_stdreg.d#1(27)} {vout:rsc:mgc_out_stdreg.d#1(28)} {vout:rsc:mgc_out_stdreg.d#1(29)} -attr xrf 44738 -attr oid 614 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vin:rsc.z(0)} -attr vt d
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+load net {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 44739 -attr oid 615 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(0)} -port {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -port {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -port {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -port {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -port {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -port {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -port {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -port {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -port {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -port {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -port {vin:rsc.z(10)} -attr vt d
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+load net {vin:rsc.z(20)} -port {vin:rsc.z(20)} -attr vt d
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+load net {vin:rsc.z(59)} -port {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -port {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -port {vin:rsc.z(61)} -attr vt d
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+load net {vin:rsc.z(64)} -port {vin:rsc.z(64)} -attr vt d
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+load net {vin:rsc.z(66)} -port {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -port {vin:rsc.z(67)} -attr vt d
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+load net {vin:rsc.z(89)} -port {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 44740 -attr oid 616 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vout:rsc.z(0)} -attr vt d
+load net {vout:rsc.z(1)} -attr vt d
+load net {vout:rsc.z(2)} -attr vt d
+load net {vout:rsc.z(3)} -attr vt d
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+load net {vout:rsc.z(5)} -attr vt d
+load net {vout:rsc.z(6)} -attr vt d
+load net {vout:rsc.z(7)} -attr vt d
+load net {vout:rsc.z(8)} -attr vt d
+load net {vout:rsc.z(9)} -attr vt d
+load net {vout:rsc.z(10)} -attr vt d
+load net {vout:rsc.z(11)} -attr vt d
+load net {vout:rsc.z(12)} -attr vt d
+load net {vout:rsc.z(13)} -attr vt d
+load net {vout:rsc.z(14)} -attr vt d
+load net {vout:rsc.z(15)} -attr vt d
+load net {vout:rsc.z(16)} -attr vt d
+load net {vout:rsc.z(17)} -attr vt d
+load net {vout:rsc.z(18)} -attr vt d
+load net {vout:rsc.z(19)} -attr vt d
+load net {vout:rsc.z(20)} -attr vt d
+load net {vout:rsc.z(21)} -attr vt d
+load net {vout:rsc.z(22)} -attr vt d
+load net {vout:rsc.z(23)} -attr vt d
+load net {vout:rsc.z(24)} -attr vt d
+load net {vout:rsc.z(25)} -attr vt d
+load net {vout:rsc.z(26)} -attr vt d
+load net {vout:rsc.z(27)} -attr vt d
+load net {vout:rsc.z(28)} -attr vt d
+load net {vout:rsc.z(29)} -attr vt d
+load netBundle {vout:rsc.z} 30 {vout:rsc.z(0)} {vout:rsc.z(1)} {vout:rsc.z(2)} {vout:rsc.z(3)} {vout:rsc.z(4)} {vout:rsc.z(5)} {vout:rsc.z(6)} {vout:rsc.z(7)} {vout:rsc.z(8)} {vout:rsc.z(9)} {vout:rsc.z(10)} {vout:rsc.z(11)} {vout:rsc.z(12)} {vout:rsc.z(13)} {vout:rsc.z(14)} {vout:rsc.z(15)} {vout:rsc.z(16)} {vout:rsc.z(17)} {vout:rsc.z(18)} {vout:rsc.z(19)} {vout:rsc.z(20)} {vout:rsc.z(21)} {vout:rsc.z(22)} {vout:rsc.z(23)} {vout:rsc.z(24)} {vout:rsc.z(25)} {vout:rsc.z(26)} {vout:rsc.z(27)} {vout:rsc.z(28)} {vout:rsc.z(29)} -attr xrf 44741 -attr oid 617 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(0)} -port {vout:rsc.z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -port {vout:rsc.z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -port {vout:rsc.z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -port {vout:rsc.z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -port {vout:rsc.z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -port {vout:rsc.z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -port {vout:rsc.z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -port {vout:rsc.z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -port {vout:rsc.z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -port {vout:rsc.z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -port {vout:rsc.z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -port {vout:rsc.z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -port {vout:rsc.z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -port {vout:rsc.z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -port {vout:rsc.z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -port {vout:rsc.z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -port {vout:rsc.z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -port {vout:rsc.z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -port {vout:rsc.z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -port {vout:rsc.z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -port {vout:rsc.z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -port {vout:rsc.z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -port {vout:rsc.z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -port {vout:rsc.z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -port {vout:rsc.z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -port {vout:rsc.z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -port {vout:rsc.z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -port {vout:rsc.z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -port {vout:rsc.z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -port {vout:rsc.z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {clk} -attr xrf 44742 -attr oid 618
+load net {clk} -port {clk} -attr xrf 44743 -attr oid 619
+load net {en} -attr xrf 44744 -attr oid 620
+load net {en} -port {en} -attr xrf 44745 -attr oid 621
+load net {arst_n} -attr xrf 44746 -attr oid 622
+load net {arst_n} -port {arst_n} -attr xrf 44747 -attr oid 623
+load inst "sobel:core:inst" "sobel:core" "orig" -attr xrf 44748 -attr oid 624 -attr vt dc -attr @path {/sobel/sobel:core:inst} -attr area 8527.523639 -attr delay 15.158629 -attr hier "/sobel/sobel:core" -pg 1 -lvl 3
+load net {clk} -pin  "sobel:core:inst" {clk#1} -attr xrf 44749 -attr oid 625 -attr @path {/sobel/clk}
+load net {en} -pin  "sobel:core:inst" {en#1} -attr xrf 44750 -attr oid 626 -attr @path {/sobel/en}
+load net {arst_n} -pin  "sobel:core:inst" {arst_n#1} -attr xrf 44751 -attr oid 627 -attr @path {/sobel/arst_n}
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(8)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(9)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(10)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(11)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(12)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(13)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(14)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(15)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(16)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(17)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(18)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(19)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(20)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(21)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(22)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(23)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(24)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(25)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(26)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(27)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(28)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(29)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(30)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(31)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(32)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(33)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(34)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(35)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(36)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(37)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(38)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(39)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(40)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(41)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(42)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(43)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(44)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(45)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(46)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(47)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(48)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(49)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(50)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(51)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(52)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(53)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(54)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(55)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(56)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(57)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(58)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(59)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(60)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(61)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(62)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(63)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(64)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(65)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(66)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(67)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(68)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(69)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(70)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(71)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(72)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(73)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(74)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(75)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(76)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(77)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(78)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(79)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(80)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(81)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(82)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(83)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(84)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(85)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(86)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(87)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(88)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(89)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(8)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(9)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(10)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(11)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(12)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(13)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(14)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(15)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(16)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(17)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(18)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(19)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(20)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(21)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(22)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(23)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(24)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(25)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(26)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(27)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(28)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(29)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load inst "vin:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" -attr xrf 44752 -attr oid 628 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,90)" -pg 1 -lvl 1
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "vin:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "vin:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "vin:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "vin:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "vin:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "vin:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "vin:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "vin:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "vin:rsc:mgc_in_wire" {d(8)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "vin:rsc:mgc_in_wire" {d(9)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "vin:rsc:mgc_in_wire" {d(10)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "vin:rsc:mgc_in_wire" {d(11)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "vin:rsc:mgc_in_wire" {d(12)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "vin:rsc:mgc_in_wire" {d(13)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "vin:rsc:mgc_in_wire" {d(14)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "vin:rsc:mgc_in_wire" {d(15)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "vin:rsc:mgc_in_wire" {d(16)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "vin:rsc:mgc_in_wire" {d(17)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "vin:rsc:mgc_in_wire" {d(18)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "vin:rsc:mgc_in_wire" {d(19)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "vin:rsc:mgc_in_wire" {d(20)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "vin:rsc:mgc_in_wire" {d(21)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "vin:rsc:mgc_in_wire" {d(22)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "vin:rsc:mgc_in_wire" {d(23)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "vin:rsc:mgc_in_wire" {d(24)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "vin:rsc:mgc_in_wire" {d(25)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "vin:rsc:mgc_in_wire" {d(26)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "vin:rsc:mgc_in_wire" {d(27)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "vin:rsc:mgc_in_wire" {d(28)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "vin:rsc:mgc_in_wire" {d(29)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "vin:rsc:mgc_in_wire" {d(30)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "vin:rsc:mgc_in_wire" {d(31)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "vin:rsc:mgc_in_wire" {d(32)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "vin:rsc:mgc_in_wire" {d(33)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "vin:rsc:mgc_in_wire" {d(34)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "vin:rsc:mgc_in_wire" {d(35)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "vin:rsc:mgc_in_wire" {d(36)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "vin:rsc:mgc_in_wire" {d(37)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "vin:rsc:mgc_in_wire" {d(38)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "vin:rsc:mgc_in_wire" {d(39)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "vin:rsc:mgc_in_wire" {d(40)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "vin:rsc:mgc_in_wire" {d(41)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "vin:rsc:mgc_in_wire" {d(42)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "vin:rsc:mgc_in_wire" {d(43)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "vin:rsc:mgc_in_wire" {d(44)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "vin:rsc:mgc_in_wire" {d(45)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "vin:rsc:mgc_in_wire" {d(46)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "vin:rsc:mgc_in_wire" {d(47)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "vin:rsc:mgc_in_wire" {d(48)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "vin:rsc:mgc_in_wire" {d(49)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "vin:rsc:mgc_in_wire" {d(50)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "vin:rsc:mgc_in_wire" {d(51)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "vin:rsc:mgc_in_wire" {d(52)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "vin:rsc:mgc_in_wire" {d(53)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "vin:rsc:mgc_in_wire" {d(54)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "vin:rsc:mgc_in_wire" {d(55)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "vin:rsc:mgc_in_wire" {d(56)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "vin:rsc:mgc_in_wire" {d(57)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "vin:rsc:mgc_in_wire" {d(58)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "vin:rsc:mgc_in_wire" {d(59)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "vin:rsc:mgc_in_wire" {d(60)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "vin:rsc:mgc_in_wire" {d(61)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "vin:rsc:mgc_in_wire" {d(62)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "vin:rsc:mgc_in_wire" {d(63)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "vin:rsc:mgc_in_wire" {d(64)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "vin:rsc:mgc_in_wire" {d(65)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "vin:rsc:mgc_in_wire" {d(66)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "vin:rsc:mgc_in_wire" {d(67)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "vin:rsc:mgc_in_wire" {d(68)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "vin:rsc:mgc_in_wire" {d(69)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "vin:rsc:mgc_in_wire" {d(70)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "vin:rsc:mgc_in_wire" {d(71)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "vin:rsc:mgc_in_wire" {d(72)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "vin:rsc:mgc_in_wire" {d(73)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "vin:rsc:mgc_in_wire" {d(74)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "vin:rsc:mgc_in_wire" {d(75)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "vin:rsc:mgc_in_wire" {d(76)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "vin:rsc:mgc_in_wire" {d(77)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "vin:rsc:mgc_in_wire" {d(78)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "vin:rsc:mgc_in_wire" {d(79)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "vin:rsc:mgc_in_wire" {d(80)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "vin:rsc:mgc_in_wire" {d(81)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "vin:rsc:mgc_in_wire" {d(82)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "vin:rsc:mgc_in_wire" {d(83)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "vin:rsc:mgc_in_wire" {d(84)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "vin:rsc:mgc_in_wire" {d(85)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "vin:rsc:mgc_in_wire" {d(86)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "vin:rsc:mgc_in_wire" {d(87)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "vin:rsc:mgc_in_wire" {d(88)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "vin:rsc:mgc_in_wire" {d(89)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc.z(0)} -pin  "vin:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(1)} -pin  "vin:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(2)} -pin  "vin:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(3)} -pin  "vin:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(4)} -pin  "vin:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(5)} -pin  "vin:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(6)} -pin  "vin:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(7)} -pin  "vin:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(8)} -pin  "vin:rsc:mgc_in_wire" {z(8)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(9)} -pin  "vin:rsc:mgc_in_wire" {z(9)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(10)} -pin  "vin:rsc:mgc_in_wire" {z(10)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(11)} -pin  "vin:rsc:mgc_in_wire" {z(11)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(12)} -pin  "vin:rsc:mgc_in_wire" {z(12)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(13)} -pin  "vin:rsc:mgc_in_wire" {z(13)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(14)} -pin  "vin:rsc:mgc_in_wire" {z(14)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(15)} -pin  "vin:rsc:mgc_in_wire" {z(15)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(16)} -pin  "vin:rsc:mgc_in_wire" {z(16)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(17)} -pin  "vin:rsc:mgc_in_wire" {z(17)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(18)} -pin  "vin:rsc:mgc_in_wire" {z(18)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(19)} -pin  "vin:rsc:mgc_in_wire" {z(19)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(20)} -pin  "vin:rsc:mgc_in_wire" {z(20)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(21)} -pin  "vin:rsc:mgc_in_wire" {z(21)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(22)} -pin  "vin:rsc:mgc_in_wire" {z(22)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(23)} -pin  "vin:rsc:mgc_in_wire" {z(23)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(24)} -pin  "vin:rsc:mgc_in_wire" {z(24)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(25)} -pin  "vin:rsc:mgc_in_wire" {z(25)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(26)} -pin  "vin:rsc:mgc_in_wire" {z(26)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(27)} -pin  "vin:rsc:mgc_in_wire" {z(27)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(28)} -pin  "vin:rsc:mgc_in_wire" {z(28)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(29)} -pin  "vin:rsc:mgc_in_wire" {z(29)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(30)} -pin  "vin:rsc:mgc_in_wire" {z(30)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(31)} -pin  "vin:rsc:mgc_in_wire" {z(31)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(32)} -pin  "vin:rsc:mgc_in_wire" {z(32)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(33)} -pin  "vin:rsc:mgc_in_wire" {z(33)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(34)} -pin  "vin:rsc:mgc_in_wire" {z(34)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(35)} -pin  "vin:rsc:mgc_in_wire" {z(35)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(36)} -pin  "vin:rsc:mgc_in_wire" {z(36)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(37)} -pin  "vin:rsc:mgc_in_wire" {z(37)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(38)} -pin  "vin:rsc:mgc_in_wire" {z(38)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(39)} -pin  "vin:rsc:mgc_in_wire" {z(39)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(40)} -pin  "vin:rsc:mgc_in_wire" {z(40)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(41)} -pin  "vin:rsc:mgc_in_wire" {z(41)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(42)} -pin  "vin:rsc:mgc_in_wire" {z(42)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(43)} -pin  "vin:rsc:mgc_in_wire" {z(43)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(44)} -pin  "vin:rsc:mgc_in_wire" {z(44)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(45)} -pin  "vin:rsc:mgc_in_wire" {z(45)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(46)} -pin  "vin:rsc:mgc_in_wire" {z(46)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(47)} -pin  "vin:rsc:mgc_in_wire" {z(47)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(48)} -pin  "vin:rsc:mgc_in_wire" {z(48)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(49)} -pin  "vin:rsc:mgc_in_wire" {z(49)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(50)} -pin  "vin:rsc:mgc_in_wire" {z(50)} -attr vt d -attr @path {/sobel/vin:rsc.z}
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+load net {vin:rsc.z(52)} -pin  "vin:rsc:mgc_in_wire" {z(52)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(53)} -pin  "vin:rsc:mgc_in_wire" {z(53)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(54)} -pin  "vin:rsc:mgc_in_wire" {z(54)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(55)} -pin  "vin:rsc:mgc_in_wire" {z(55)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(56)} -pin  "vin:rsc:mgc_in_wire" {z(56)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(57)} -pin  "vin:rsc:mgc_in_wire" {z(57)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(58)} -pin  "vin:rsc:mgc_in_wire" {z(58)} -attr vt d -attr @path {/sobel/vin:rsc.z}
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+load net {vin:rsc.z(65)} -pin  "vin:rsc:mgc_in_wire" {z(65)} -attr vt d -attr @path {/sobel/vin:rsc.z}
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+load net {vin:rsc.z(74)} -pin  "vin:rsc:mgc_in_wire" {z(74)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(75)} -pin  "vin:rsc:mgc_in_wire" {z(75)} -attr vt d -attr @path {/sobel/vin:rsc.z}
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+load net {vin:rsc.z(78)} -pin  "vin:rsc:mgc_in_wire" {z(78)} -attr vt d -attr @path {/sobel/vin:rsc.z}
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+load net {vin:rsc.z(80)} -pin  "vin:rsc:mgc_in_wire" {z(80)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(81)} -pin  "vin:rsc:mgc_in_wire" {z(81)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(82)} -pin  "vin:rsc:mgc_in_wire" {z(82)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(83)} -pin  "vin:rsc:mgc_in_wire" {z(83)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(84)} -pin  "vin:rsc:mgc_in_wire" {z(84)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(85)} -pin  "vin:rsc:mgc_in_wire" {z(85)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(86)} -pin  "vin:rsc:mgc_in_wire" {z(86)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(87)} -pin  "vin:rsc:mgc_in_wire" {z(87)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(88)} -pin  "vin:rsc:mgc_in_wire" {z(88)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(89)} -pin  "vin:rsc:mgc_in_wire" {z(89)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load inst "vout:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" -attr xrf 44753 -attr oid 629 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(2,30)" -pg 1 -lvl 1002
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "vout:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "vout:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "vout:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "vout:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "vout:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "vout:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "vout:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "vout:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "vout:rsc:mgc_out_stdreg" {d(8)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "vout:rsc:mgc_out_stdreg" {d(9)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "vout:rsc:mgc_out_stdreg" {d(10)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "vout:rsc:mgc_out_stdreg" {d(11)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "vout:rsc:mgc_out_stdreg" {d(12)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "vout:rsc:mgc_out_stdreg" {d(13)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "vout:rsc:mgc_out_stdreg" {d(14)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "vout:rsc:mgc_out_stdreg" {d(15)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "vout:rsc:mgc_out_stdreg" {d(16)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "vout:rsc:mgc_out_stdreg" {d(17)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "vout:rsc:mgc_out_stdreg" {d(18)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "vout:rsc:mgc_out_stdreg" {d(19)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "vout:rsc:mgc_out_stdreg" {d(20)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "vout:rsc:mgc_out_stdreg" {d(21)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "vout:rsc:mgc_out_stdreg" {d(22)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "vout:rsc:mgc_out_stdreg" {d(23)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "vout:rsc:mgc_out_stdreg" {d(24)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "vout:rsc:mgc_out_stdreg" {d(25)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "vout:rsc:mgc_out_stdreg" {d(26)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "vout:rsc:mgc_out_stdreg" {d(27)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "vout:rsc:mgc_out_stdreg" {d(28)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "vout:rsc:mgc_out_stdreg" {d(29)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc.z(0)} -pin  "vout:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -pin  "vout:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -pin  "vout:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -pin  "vout:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -pin  "vout:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -pin  "vout:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -pin  "vout:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -pin  "vout:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -pin  "vout:rsc:mgc_out_stdreg" {z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -pin  "vout:rsc:mgc_out_stdreg" {z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -pin  "vout:rsc:mgc_out_stdreg" {z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -pin  "vout:rsc:mgc_out_stdreg" {z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -pin  "vout:rsc:mgc_out_stdreg" {z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -pin  "vout:rsc:mgc_out_stdreg" {z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -pin  "vout:rsc:mgc_out_stdreg" {z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -pin  "vout:rsc:mgc_out_stdreg" {z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -pin  "vout:rsc:mgc_out_stdreg" {z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -pin  "vout:rsc:mgc_out_stdreg" {z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -pin  "vout:rsc:mgc_out_stdreg" {z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -pin  "vout:rsc:mgc_out_stdreg" {z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -pin  "vout:rsc:mgc_out_stdreg" {z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -pin  "vout:rsc:mgc_out_stdreg" {z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -pin  "vout:rsc:mgc_out_stdreg" {z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -pin  "vout:rsc:mgc_out_stdreg" {z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -pin  "vout:rsc:mgc_out_stdreg" {z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -pin  "vout:rsc:mgc_out_stdreg" {z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -pin  "vout:rsc:mgc_out_stdreg" {z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -pin  "vout:rsc:mgc_out_stdreg" {z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -pin  "vout:rsc:mgc_out_stdreg" {z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -pin  "vout:rsc:mgc_out_stdreg" {z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+### END MODULE 
+
diff --git a/Sobel/sobel.v11/concat_rtl.v b/Sobel/sobel.v11/concat_rtl.v
new file mode 100644
index 0000000..f45e19d
--- /dev/null
+++ b/Sobel/sobel.v11/concat_rtl.v
@@ -0,0 +1,2857 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 16:15:58 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] regs_regs_slc_regs_regs_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_1_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_4_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_5_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_3_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_10_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_11_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_9_itm;
+  reg [12:0] ACC1_acc_659_itm_1;
+  wire [14:0] nl_ACC1_acc_659_itm_1;
+  reg [12:0] ACC1_acc_658_itm_1;
+  wire [13:0] nl_ACC1_acc_658_itm_1;
+  reg [13:0] ACC1_acc_661_itm_1;
+  wire [14:0] nl_ACC1_acc_661_itm_1;
+  reg slc_acc_20_psp_1_93_itm_1;
+  reg ACC1_slc_ACC1_acc_228_psp_55_itm_1;
+  reg ACC1_3_slc_acc_10_psp_62_itm_1;
+  reg [10:0] ACC1_acc_652_itm_1;
+  wire [11:0] nl_ACC1_acc_652_itm_1;
+  reg [11:0] ACC1_acc_655_itm_1;
+  wire [12:0] nl_ACC1_acc_655_itm_1;
+  reg main_stage_0_2;
+  reg [4:0] ACC1_mul_57_itm_1_sg2;
+  reg [1:0] ACC1_mul_57_itm_2;
+  reg [89:0] reg_regs_regs_0_sva_cse;
+  wire [11:0] FRAME_acc_2_psp_sva;
+  wire [13:0] nl_FRAME_acc_2_psp_sva;
+  wire [5:0] acc_imod_24_sva;
+  wire [7:0] nl_acc_imod_24_sva;
+  wire [11:0] acc_20_psp_1_sva;
+  wire [12:0] nl_acc_20_psp_1_sva;
+  wire [11:0] ACC1_acc_228_psp_sva;
+  wire [12:0] nl_ACC1_acc_228_psp_sva;
+  wire [11:0] ACC1_1_acc_25_psp_sva;
+  wire [12:0] nl_ACC1_1_acc_25_psp_sva;
+  wire [2:0] ACC1_acc_509_cse;
+  wire [3:0] nl_ACC1_acc_509_cse;
+  wire [11:0] ACC1_acc_227_psp_sva;
+  wire [12:0] nl_ACC1_acc_227_psp_sva;
+  wire [2:0] ACC1_acc_506_cse;
+  wire [3:0] nl_ACC1_acc_506_cse;
+  wire [3:0] ACC1_acc_562_ncse;
+  wire [4:0] nl_ACC1_acc_562_ncse;
+  wire [2:0] ACC1_acc_502_cse;
+  wire [3:0] nl_ACC1_acc_502_cse;
+  wire [2:0] ACC1_acc_489_cse;
+  wire [3:0] nl_ACC1_acc_489_cse;
+  wire [11:0] ACC1_acc_226_psp_sva;
+  wire [12:0] nl_ACC1_acc_226_psp_sva;
+  wire [3:0] ACC1_acc_553_ncse;
+  wire [4:0] nl_ACC1_acc_553_ncse;
+  wire ACC1_1_and_3_cse_sva;
+  wire ACC1_1_nand_1_cse_sva;
+  wire [11:0] acc_psp_1_sva;
+  wire [12:0] nl_acc_psp_1_sva;
+  wire [3:0] ACC1_acc_210_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_210_psp_2_sva;
+  wire [11:0] acc_psp_2_sva;
+  wire [12:0] nl_acc_psp_2_sva;
+  wire [11:0] ACC1_acc_224_psp_1_sva;
+  wire [12:0] nl_ACC1_acc_224_psp_1_sva;
+  wire [3:0] ACC1_1_acc_208_psp_sva;
+  wire [4:0] nl_ACC1_1_acc_208_psp_sva;
+  wire [11:0] ACC1_acc_224_psp_sva;
+  wire [12:0] nl_ACC1_acc_224_psp_sva;
+  wire [2:0] ACC1_acc_516_cse;
+  wire [3:0] nl_ACC1_acc_516_cse;
+  wire [3:0] ACC1_3_acc_212_psp_sva;
+  wire [4:0] nl_ACC1_3_acc_212_psp_sva;
+  wire [2:0] ACC1_acc_221_psp_sva;
+  wire [3:0] nl_ACC1_acc_221_psp_sva;
+  wire [2:0] ACC1_acc_221_psp_2_sva;
+  wire [3:0] nl_ACC1_acc_221_psp_2_sva;
+  wire [2:0] ACC1_acc_219_psp_2_sva;
+  wire [3:0] nl_ACC1_acc_219_psp_2_sva;
+  wire [2:0] ACC1_acc_222_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_222_psp_1_sva;
+  wire [2:0] ACC1_acc_219_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_219_psp_1_sva;
+  wire [3:0] ACC1_acc_210_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_210_psp_1_sva;
+  wire [3:0] ACC1_acc_217_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_217_psp_1_sva;
+  wire [2:0] ACC1_acc_724_cse;
+  wire [3:0] nl_ACC1_acc_724_cse;
+  wire [13:0] ACC1_mul_57_itm;
+  wire [27:0] nl_ACC1_mul_57_itm;
+  wire [2:0] ACC1_acc_223_psp_sva;
+  wire [3:0] nl_ACC1_acc_223_psp_sva;
+  wire [2:0] ACC1_acc_220_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_220_psp_1_sva;
+  wire [2:0] ACC1_acc_220_psp_sva;
+  wire [3:0] nl_ACC1_acc_220_psp_sva;
+  wire [2:0] ACC1_acc_222_psp_sva;
+  wire [3:0] nl_ACC1_acc_222_psp_sva;
+  wire [2:0] ACC1_acc_673_cse;
+  wire [3:0] nl_ACC1_acc_673_cse;
+  wire [11:0] acc_20_psp_2_sva;
+  wire [12:0] nl_acc_20_psp_2_sva;
+  wire [3:0] ACC1_acc_217_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_217_psp_2_sva;
+  wire [2:0] ACC1_acc_223_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_223_psp_1_sva;
+  wire [2:0] ACC1_acc_699_cse;
+  wire [3:0] nl_ACC1_acc_699_cse;
+  wire [14:0] ACC1_acc_itm;
+  wire [16:0] nl_ACC1_acc_itm;
+  wire [3:0] ACC1_acc_338_itm;
+  wire [4:0] nl_ACC1_acc_338_itm;
+  wire [2:0] ACC1_acc_406_itm;
+  wire [3:0] nl_ACC1_acc_406_itm;
+  wire [2:0] ACC1_acc_368_itm;
+  wire [3:0] nl_ACC1_acc_368_itm;
+  wire [3:0] ACC1_acc_367_itm;
+  wire [4:0] nl_ACC1_acc_367_itm;
+  wire [2:0] ACC1_acc_349_itm;
+  wire [3:0] nl_ACC1_acc_349_itm;
+  wire [3:0] ACC1_acc_348_itm;
+  wire [4:0] nl_ACC1_acc_348_itm;
+  wire [4:0] ACC1_acc_412_itm;
+  wire [5:0] nl_ACC1_acc_412_itm;
+  wire [3:0] ACC1_acc_423_itm;
+  wire [4:0] nl_ACC1_acc_423_itm;
+  wire [4:0] ACC1_acc_375_itm;
+  wire [5:0] nl_ACC1_acc_375_itm;
+  wire [3:0] ACC1_acc_395_itm;
+  wire [4:0] nl_ACC1_acc_395_itm;
+  wire [4:0] ACC1_acc_384_itm;
+  wire [5:0] nl_ACC1_acc_384_itm;
+  wire [3:0] ACC1_acc_414_itm;
+  wire [4:0] nl_ACC1_acc_414_itm;
+  wire [3:0] ACC1_acc_377_itm;
+  wire [4:0] nl_ACC1_acc_377_itm;
+  wire [4:0] ACC1_acc_346_itm;
+  wire [5:0] nl_ACC1_acc_346_itm;
+  wire [3:0] ACC1_acc_386_itm;
+  wire [4:0] nl_ACC1_acc_386_itm;
+  wire [3:0] ACC1_acc_405_itm;
+  wire [4:0] nl_ACC1_acc_405_itm;
+  wire [2:0] ACC1_acc_387_itm;
+  wire [3:0] nl_ACC1_acc_387_itm;
+  wire [2:0] ACC1_acc_378_itm;
+  wire [3:0] nl_ACC1_acc_378_itm;
+  wire [2:0] ACC1_acc_415_itm;
+  wire [3:0] nl_ACC1_acc_415_itm;
+  wire [2:0] ACC1_acc_396_itm;
+  wire [3:0] nl_ACC1_acc_396_itm;
+  wire [2:0] ACC1_acc_424_itm;
+  wire [3:0] nl_ACC1_acc_424_itm;
+  wire [2:0] ACC1_acc_359_itm;
+  wire [3:0] nl_ACC1_acc_359_itm;
+  wire [3:0] ACC1_acc_358_itm;
+  wire [4:0] nl_ACC1_acc_358_itm;
+  wire [2:0] ACC1_acc_339_itm;
+  wire [3:0] nl_ACC1_acc_339_itm;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_2_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(ACC1_acc_itm[14:13])
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_itm[12:10])
+      * 9'b111001)) + conv_s2s_7_10(conv_u2s_6_7(ACC1_acc_itm[9:4]) + conv_s2s_5_7(({4'b1001
+      , (acc_imod_24_sva[5])}) + conv_u2s_4_5((conv_u2u_3_4({(~ (acc_imod_24_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_24_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_24_sva[5:3])) , (~ (acc_imod_24_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_24_sva[4:3]))
+      + conv_u2u_3_4(~ (ACC1_acc_itm[9:7]))))))) + conv_u2u_11_12(signext_11_9({(ACC1_acc_itm[14])
+      , 3'b0 , (signext_3_1(ACC1_acc_itm[14])) , 1'b0 , (ACC1_acc_itm[14])}));
+  assign FRAME_acc_2_psp_sva = nl_FRAME_acc_2_psp_sva[11:0];
+  assign nl_ACC1_acc_itm = (conv_s2s_14_15(conv_s2s_13_14(ACC1_acc_659_itm_1) + conv_s2s_13_14(ACC1_acc_658_itm_1))
+      + conv_s2s_14_15(ACC1_acc_661_itm_1)) + conv_s2s_14_15(({ACC1_mul_57_itm_1_sg2
+      , 7'b0 , ACC1_mul_57_itm_2}) + conv_s2s_13_14(conv_s2s_12_13(({slc_acc_20_psp_1_93_itm_1
+      , 2'b0 , slc_acc_20_psp_1_93_itm_1 , 1'b0 , slc_acc_20_psp_1_93_itm_1 , 1'b0
+      , slc_acc_20_psp_1_93_itm_1 , ACC1_slc_ACC1_acc_228_psp_55_itm_1 , 1'b0 , ({{1{ACC1_3_slc_acc_10_psp_62_itm_1}},
+      ACC1_3_slc_acc_10_psp_62_itm_1})}) + conv_u2s_11_12(ACC1_acc_652_itm_1)) +
+      conv_s2s_12_13(ACC1_acc_655_itm_1)));
+  assign ACC1_acc_itm = nl_ACC1_acc_itm[14:0];
+  assign nl_acc_imod_24_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~ (ACC1_acc_itm[14]))
+      , 1'b1 , (~ (ACC1_acc_itm[14]))}) + conv_u2u_2_4(ACC1_acc_itm[14:13]))) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_itm[3:1])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[6:4])))) + 6'b101011;
+  assign acc_imod_24_sva = nl_acc_imod_24_sva[5:0];
+  assign nl_acc_20_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_10_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_11_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_9_itm);
+  assign acc_20_psp_1_sva = nl_acc_20_psp_1_sva[11:0];
+  assign nl_ACC1_acc_228_psp_sva = conv_s2u_11_12(conv_s2s_10_11(~ (reg_regs_regs_0_sva_cse[9:0]))
+      + conv_s2s_10_11(~ (reg_regs_regs_0_sva_cse[19:10]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (reg_regs_regs_0_sva_cse[29:20])) + 11'b11);
+  assign ACC1_acc_228_psp_sva = nl_ACC1_acc_228_psp_sva[11:0];
+  assign nl_ACC1_1_acc_25_psp_sva = conv_s2s_11_12(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[79:70])
+      + conv_s2s_10_11(vin_rsc_mgc_in_wire_d[69:60])) + conv_s2s_10_12(vin_rsc_mgc_in_wire_d[89:80]);
+  assign ACC1_1_acc_25_psp_sva = nl_ACC1_1_acc_25_psp_sva[11:0];
+  assign nl_ACC1_acc_509_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]));
+  assign ACC1_acc_509_cse = nl_ACC1_acc_509_cse[2:0];
+  assign nl_ACC1_acc_227_psp_sva = conv_s2s_11_12(conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_itm)
+      + conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_1_itm)) + conv_s2s_11_12(conv_s2s_10_11(~
+      regs_regs_slc_regs_regs_2_2_itm) + 11'b11);
+  assign ACC1_acc_227_psp_sva = nl_ACC1_acc_227_psp_sva[11:0];
+  assign nl_ACC1_acc_506_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+  assign ACC1_acc_506_cse = nl_ACC1_acc_506_cse[2:0];
+  assign nl_ACC1_acc_562_ncse = conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(ACC1_acc_506_cse);
+  assign ACC1_acc_562_ncse = nl_ACC1_acc_562_ncse[3:0];
+  assign nl_ACC1_acc_502_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[5])) + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+  assign ACC1_acc_502_cse = nl_ACC1_acc_502_cse[2:0];
+  assign nl_ACC1_acc_489_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]));
+  assign ACC1_acc_489_cse = nl_ACC1_acc_489_cse[2:0];
+  assign nl_ACC1_acc_226_psp_sva = conv_s2u_11_12(conv_s2s_10_11(reg_regs_regs_0_sva_cse[79:70])
+      + conv_s2s_10_11(reg_regs_regs_0_sva_cse[69:60])) + conv_s2u_10_12(reg_regs_regs_0_sva_cse[89:80]);
+  assign ACC1_acc_226_psp_sva = nl_ACC1_acc_226_psp_sva[11:0];
+  assign nl_ACC1_acc_553_ncse = conv_u2u_3_4(ACC1_acc_489_cse) + conv_u2u_3_4(ACC1_acc_489_cse);
+  assign ACC1_acc_553_ncse = nl_ACC1_acc_553_ncse[3:0];
+  assign ACC1_1_and_3_cse_sva = (acc_psp_2_sva[11]) & (~ (ACC1_acc_339_itm[2])) &
+      (ACC1_acc_339_itm[1]);
+  assign ACC1_1_nand_1_cse_sva = ~((ACC1_acc_339_itm[2]) & (~ (acc_psp_2_sva[11])));
+  assign nl_acc_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_1_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_2_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_itm);
+  assign acc_psp_1_sva = nl_acc_psp_1_sva[11:0];
+  assign nl_ACC1_acc_338_itm = conv_s2s_3_4({(~ (ACC1_acc_220_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_220_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_338_itm = nl_ACC1_acc_338_itm[3:0];
+  assign nl_ACC1_acc_210_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_2_sva[1])) , (acc_psp_2_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_2_sva[0]) , (acc_psp_2_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[3])) , (~ (acc_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[5])) , (acc_psp_2_sva[6])})))) ,
+      (~ (acc_psp_2_sva[9]))}))));
+  assign ACC1_acc_210_psp_2_sva = nl_ACC1_acc_210_psp_2_sva[3:0];
+  assign nl_acc_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[29:20]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[19:10]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[9:0])) + 11'b11);
+  assign acc_psp_2_sva = nl_acc_psp_2_sva[11:0];
+  assign nl_ACC1_acc_224_psp_1_sva = conv_s2u_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[39:30]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[49:40]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[59:50])) + 11'b11);
+  assign ACC1_acc_224_psp_1_sva = nl_ACC1_acc_224_psp_1_sva[11:0];
+  assign nl_ACC1_acc_406_itm = ({1'b1 , (ACC1_acc_405_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_405_itm[2])) , (~ (ACC1_acc_405_itm[3]))});
+  assign ACC1_acc_406_itm = nl_ACC1_acc_406_itm[2:0];
+  assign nl_ACC1_acc_368_itm = ({1'b1 , (ACC1_acc_367_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_367_itm[2])) , (~ (ACC1_acc_367_itm[3]))});
+  assign ACC1_acc_368_itm = nl_ACC1_acc_368_itm[2:0];
+  assign nl_ACC1_acc_367_itm = conv_s2s_3_4({(~ (ACC1_acc_219_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_367_itm = nl_ACC1_acc_367_itm[3:0];
+  assign nl_ACC1_1_acc_208_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (ACC1_1_acc_25_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_1_acc_25_psp_sva[1]))
+      , (ACC1_1_acc_25_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (ACC1_1_acc_25_psp_sva[0])
+      , (ACC1_1_acc_25_psp_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[3])) , (~ (ACC1_1_acc_25_psp_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[5])) , (ACC1_1_acc_25_psp_sva[6])}))))
+      , (~ (ACC1_1_acc_25_psp_sva[9]))}))));
+  assign ACC1_1_acc_208_psp_sva = nl_ACC1_1_acc_208_psp_sva[3:0];
+  assign nl_ACC1_acc_349_itm = ({1'b1 , (ACC1_acc_348_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_348_itm[2])) , (~ (ACC1_acc_348_itm[3]))});
+  assign ACC1_acc_349_itm = nl_ACC1_acc_349_itm[2:0];
+  assign nl_ACC1_acc_348_itm = conv_s2s_3_4({(~ (ACC1_acc_222_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_222_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_348_itm = nl_ACC1_acc_348_itm[3:0];
+  assign nl_ACC1_acc_224_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_4_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_5_itm)) + conv_s2u_10_12(regs_regs_slc_regs_regs_2_3_itm);
+  assign ACC1_acc_224_psp_sva = nl_ACC1_acc_224_psp_sva[11:0];
+  assign nl_ACC1_acc_516_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]));
+  assign ACC1_acc_516_cse = nl_ACC1_acc_516_cse[2:0];
+  assign nl_ACC1_acc_412_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_224_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[2])) , (~ (ACC1_acc_224_psp_sva[6]))}))))
+      , (~ (ACC1_acc_224_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[4])) , (ACC1_acc_224_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_sva[11:10])) , (ACC1_acc_224_psp_sva[7])}))))
+      , (ACC1_acc_224_psp_sva[9])});
+  assign ACC1_acc_412_itm = nl_ACC1_acc_412_itm[4:0];
+  assign nl_ACC1_acc_423_itm = conv_s2s_3_4({(~ (ACC1_acc_223_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_223_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_423_itm = nl_ACC1_acc_423_itm[3:0];
+  assign nl_ACC1_acc_375_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_228_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[2])) , (~ (ACC1_acc_228_psp_sva[6]))}))))
+      , (~ (ACC1_acc_228_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[4])) , (ACC1_acc_228_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_228_psp_sva[11:10])) , (ACC1_acc_228_psp_sva[7])}))))
+      , (ACC1_acc_228_psp_sva[9])});
+  assign ACC1_acc_375_itm = nl_ACC1_acc_375_itm[4:0];
+  assign nl_ACC1_acc_395_itm = conv_s2s_3_4({(~ (ACC1_acc_220_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_220_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_395_itm = nl_ACC1_acc_395_itm[3:0];
+  assign nl_ACC1_acc_384_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_226_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[2])) , (~ (ACC1_acc_226_psp_sva[6]))}))))
+      , (~ (ACC1_acc_226_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[4])) , (ACC1_acc_226_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_226_psp_sva[11:10])) , (ACC1_acc_226_psp_sva[7])}))))
+      , (ACC1_acc_226_psp_sva[9])});
+  assign ACC1_acc_384_itm = nl_ACC1_acc_384_itm[4:0];
+  assign nl_ACC1_3_acc_212_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (ACC1_acc_227_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_acc_227_psp_sva[1]))
+      , (ACC1_acc_227_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (ACC1_acc_227_psp_sva[0])
+      , (ACC1_acc_227_psp_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[3])) , (~ (ACC1_acc_227_psp_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[5])) , (ACC1_acc_227_psp_sva[6])}))))
+      , (~ (ACC1_acc_227_psp_sva[9]))}))));
+  assign ACC1_3_acc_212_psp_sva = nl_ACC1_3_acc_212_psp_sva[3:0];
+  assign nl_ACC1_acc_414_itm = conv_s2s_3_4({(~ (ACC1_acc_222_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_222_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_414_itm = nl_ACC1_acc_414_itm[3:0];
+  assign nl_ACC1_acc_377_itm = conv_s2s_3_4({(~ (ACC1_acc_221_psp_2_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_221_psp_2_sva[0]) , 1'b1});
+  assign ACC1_acc_377_itm = nl_ACC1_acc_377_itm[3:0];
+  assign nl_ACC1_acc_346_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_224_psp_1_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[2])) , (~ (ACC1_acc_224_psp_1_sva[6]))}))))
+      , (~ (ACC1_acc_224_psp_1_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[4])) , (ACC1_acc_224_psp_1_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_1_sva[11:10])) , (ACC1_acc_224_psp_1_sva[7])}))))
+      , (ACC1_acc_224_psp_1_sva[9])});
+  assign ACC1_acc_346_itm = nl_ACC1_acc_346_itm[4:0];
+  assign nl_ACC1_acc_386_itm = conv_s2s_3_4({(~ (ACC1_acc_219_psp_2_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_2_sva[0]) , 1'b1});
+  assign ACC1_acc_386_itm = nl_ACC1_acc_386_itm[3:0];
+  assign nl_ACC1_acc_405_itm = conv_s2s_3_4({(~ (ACC1_acc_221_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_221_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_405_itm = nl_ACC1_acc_405_itm[3:0];
+  assign nl_ACC1_acc_221_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_3_acc_212_psp_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_3_acc_212_psp_sva[1])) , (ACC1_3_acc_212_psp_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_3_acc_212_psp_sva[3]));
+  assign ACC1_acc_221_psp_sva = nl_ACC1_acc_221_psp_sva[2:0];
+  assign nl_ACC1_acc_221_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_375_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_375_itm[2])) , (ACC1_acc_375_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_375_itm[4]));
+  assign ACC1_acc_221_psp_2_sva = nl_ACC1_acc_221_psp_2_sva[2:0];
+  assign nl_ACC1_acc_219_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_384_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_384_itm[2])) , (ACC1_acc_384_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_384_itm[4]));
+  assign ACC1_acc_219_psp_2_sva = nl_ACC1_acc_219_psp_2_sva[2:0];
+  assign nl_ACC1_acc_222_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_346_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_346_itm[2])) , (ACC1_acc_346_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_346_itm[4]));
+  assign ACC1_acc_222_psp_1_sva = nl_ACC1_acc_222_psp_1_sva[2:0];
+  assign nl_ACC1_acc_219_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_208_psp_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_208_psp_sva[1])) , (ACC1_1_acc_208_psp_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_1_acc_208_psp_sva[3]));
+  assign ACC1_acc_219_psp_1_sva = nl_ACC1_acc_219_psp_1_sva[2:0];
+  assign nl_ACC1_acc_387_itm = ({1'b1 , (ACC1_acc_386_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_386_itm[2])) , (~ (ACC1_acc_386_itm[3]))});
+  assign ACC1_acc_387_itm = nl_ACC1_acc_387_itm[2:0];
+  assign nl_ACC1_acc_378_itm = ({1'b1 , (ACC1_acc_377_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_377_itm[2])) , (~ (ACC1_acc_377_itm[3]))});
+  assign ACC1_acc_378_itm = nl_ACC1_acc_378_itm[2:0];
+  assign nl_ACC1_acc_415_itm = ({1'b1 , (ACC1_acc_414_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_414_itm[2])) , (~ (ACC1_acc_414_itm[3]))});
+  assign ACC1_acc_415_itm = nl_ACC1_acc_415_itm[2:0];
+  assign nl_ACC1_acc_396_itm = ({1'b1 , (ACC1_acc_395_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_395_itm[2])) , (~ (ACC1_acc_395_itm[3]))});
+  assign ACC1_acc_396_itm = nl_ACC1_acc_396_itm[2:0];
+  assign nl_ACC1_acc_210_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_1_sva[1])) , (acc_psp_1_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_1_sva[0]) , (acc_psp_1_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[3])) , (~ (acc_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[5])) , (acc_psp_1_sva[6])})))) ,
+      (~ (acc_psp_1_sva[9]))}))));
+  assign ACC1_acc_210_psp_1_sva = nl_ACC1_acc_210_psp_1_sva[3:0];
+  assign nl_ACC1_acc_217_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_20_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_1_sva[1]))
+      , (acc_20_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_1_sva[0])
+      , (acc_20_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[3])) , (~ (acc_20_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[5])) , (acc_20_psp_1_sva[6])}))))
+      , (~ (acc_20_psp_1_sva[9]))}))));
+  assign ACC1_acc_217_psp_1_sva = nl_ACC1_acc_217_psp_1_sva[3:0];
+  assign nl_ACC1_acc_424_itm = ({1'b1 , (ACC1_acc_423_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_423_itm[2])) , (~ (ACC1_acc_423_itm[3]))});
+  assign ACC1_acc_424_itm = nl_ACC1_acc_424_itm[2:0];
+  assign nl_ACC1_acc_724_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]));
+  assign ACC1_acc_724_cse = nl_ACC1_acc_724_cse[2:0];
+  assign nl_ACC1_mul_57_itm = conv_u2s_2_14((conv_u2u_1_2(ACC1_acc_224_psp_sva[11])
+      + conv_u2u_1_2(ACC1_acc_228_psp_sva[11])) + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[11]))
+      * 14'b11101000000001;
+  assign ACC1_mul_57_itm = nl_ACC1_mul_57_itm[13:0];
+  assign nl_ACC1_acc_223_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_1_sva[1])) , (ACC1_acc_217_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_217_psp_1_sva[3]));
+  assign ACC1_acc_223_psp_sva = nl_ACC1_acc_223_psp_sva[2:0];
+  assign nl_ACC1_acc_220_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_2_sva[1])) , (ACC1_acc_210_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_210_psp_2_sva[3]));
+  assign ACC1_acc_220_psp_1_sva = nl_ACC1_acc_220_psp_1_sva[2:0];
+  assign nl_ACC1_acc_220_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_1_sva[1])) , (ACC1_acc_210_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_210_psp_1_sva[3]));
+  assign ACC1_acc_220_psp_sva = nl_ACC1_acc_220_psp_sva[2:0];
+  assign nl_ACC1_acc_222_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_412_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_412_itm[2])) , (ACC1_acc_412_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_412_itm[4]));
+  assign ACC1_acc_222_psp_sva = nl_ACC1_acc_222_psp_sva[2:0];
+  assign nl_ACC1_acc_673_cse = conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11]));
+  assign ACC1_acc_673_cse = nl_ACC1_acc_673_cse[2:0];
+  assign nl_acc_20_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[89:80]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[79:70]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[69:60])) + 11'b11);
+  assign acc_20_psp_2_sva = nl_acc_20_psp_2_sva[11:0];
+  assign nl_ACC1_acc_359_itm = ({1'b1 , (ACC1_acc_358_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_358_itm[2])) , (~ (ACC1_acc_358_itm[3]))});
+  assign ACC1_acc_359_itm = nl_ACC1_acc_359_itm[2:0];
+  assign nl_ACC1_acc_358_itm = conv_s2s_3_4({(~ (ACC1_acc_223_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_223_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_358_itm = nl_ACC1_acc_358_itm[3:0];
+  assign nl_ACC1_acc_217_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_20_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_2_sva[1]))
+      , (acc_20_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_2_sva[0])
+      , (acc_20_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[3])) , (~ (acc_20_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[5])) , (acc_20_psp_2_sva[6])}))))
+      , (~ (acc_20_psp_2_sva[9]))}))));
+  assign ACC1_acc_217_psp_2_sva = nl_ACC1_acc_217_psp_2_sva[3:0];
+  assign nl_ACC1_acc_223_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_2_sva[1])) , (ACC1_acc_217_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_217_psp_2_sva[3]));
+  assign ACC1_acc_223_psp_1_sva = nl_ACC1_acc_223_psp_1_sva[2:0];
+  assign nl_ACC1_acc_699_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11]));
+  assign ACC1_acc_699_cse = nl_ACC1_acc_699_cse[2:0];
+  assign nl_ACC1_acc_339_itm = ({1'b1 , (ACC1_acc_338_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_338_itm[2])) , (~ (ACC1_acc_338_itm[3]))});
+  assign ACC1_acc_339_itm = nl_ACC1_acc_339_itm[2:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      ACC1_acc_659_itm_1 <= 13'b0;
+      ACC1_acc_658_itm_1 <= 13'b0;
+      ACC1_acc_661_itm_1 <= 14'b0;
+      ACC1_mul_57_itm_1_sg2 <= 5'b0;
+      ACC1_mul_57_itm_2 <= 2'b0;
+      slc_acc_20_psp_1_93_itm_1 <= 1'b0;
+      ACC1_slc_ACC1_acc_228_psp_55_itm_1 <= 1'b0;
+      ACC1_3_slc_acc_10_psp_62_itm_1 <= 1'b0;
+      ACC1_acc_652_itm_1 <= 11'b0;
+      ACC1_acc_655_itm_1 <= 12'b0;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_slc_regs_regs_2_10_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_11_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_9_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_4_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_5_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_3_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_1_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_2_itm <= 10'b0;
+      reg_regs_regs_0_sva_cse <= 90'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({vout_rsc_mgc_out_stdreg_d , ({((FRAME_acc_2_psp_sva[9:0])
+            | ({8'b0 , (FRAME_acc_2_psp_sva[11:10])})) , (FRAME_acc_2_psp_sva[9:6])
+            , ((FRAME_acc_2_psp_sva[5:0]) | ({4'b0 , (FRAME_acc_2_psp_sva[11:10])}))
+            , (FRAME_acc_2_psp_sva[9:0])})}, main_stage_0_2);
+        ACC1_acc_659_itm_1 <= nl_ACC1_acc_659_itm_1[12:0];
+        ACC1_acc_658_itm_1 <= nl_ACC1_acc_658_itm_1[12:0];
+        ACC1_acc_661_itm_1 <= nl_ACC1_acc_661_itm_1[13:0];
+        ACC1_mul_57_itm_1_sg2 <= ACC1_mul_57_itm[13:9];
+        ACC1_mul_57_itm_2 <= ACC1_mul_57_itm[1:0];
+        slc_acc_20_psp_1_93_itm_1 <= acc_20_psp_1_sva[11];
+        ACC1_slc_ACC1_acc_228_psp_55_itm_1 <= ACC1_acc_228_psp_sva[6];
+        ACC1_3_slc_acc_10_psp_62_itm_1 <= ACC1_acc_224_psp_sva[8];
+        ACC1_acc_652_itm_1 <= nl_ACC1_acc_652_itm_1[10:0];
+        ACC1_acc_655_itm_1 <= nl_ACC1_acc_655_itm_1[11:0];
+        main_stage_0_2 <= 1'b1;
+        regs_regs_slc_regs_regs_2_10_itm <= reg_regs_regs_0_sva_cse[79:70];
+        regs_regs_slc_regs_regs_2_11_itm <= reg_regs_regs_0_sva_cse[69:60];
+        regs_regs_slc_regs_regs_2_9_itm <= reg_regs_regs_0_sva_cse[89:80];
+        regs_regs_slc_regs_regs_2_4_itm <= reg_regs_regs_0_sva_cse[49:40];
+        regs_regs_slc_regs_regs_2_5_itm <= reg_regs_regs_0_sva_cse[39:30];
+        regs_regs_slc_regs_regs_2_3_itm <= reg_regs_regs_0_sva_cse[59:50];
+        regs_regs_slc_regs_regs_2_itm <= reg_regs_regs_0_sva_cse[29:20];
+        regs_regs_slc_regs_regs_2_1_itm <= reg_regs_regs_0_sva_cse[19:10];
+        regs_regs_slc_regs_regs_2_2_itm <= reg_regs_regs_0_sva_cse[9:0];
+        reg_regs_regs_0_sva_cse <= vin_rsc_mgc_in_wire_d;
+      end
+    end
+  end
+  assign nl_ACC1_acc_659_itm_1  = conv_s2s_12_13(conv_s2s_11_12({(ACC1_1_acc_25_psp_sva[11])
+      , 2'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11]) ,
+      1'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_224_psp_sva[0])})
+      + conv_u2s_11_12({conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[9])
+      + conv_u2u_1_2(acc_psp_1_sva[9])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[8]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[8])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[8]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[8])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[9]))
+      + conv_u2u_1_4(acc_psp_2_sva[9])) * 8'b10101) , (ACC1_acc_227_psp_sva[4]) ,
+      (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_s2s_12_13(conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_psp_2_sva[9]) , 1'b0
+      , (acc_psp_2_sva[9]) , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_2_sva[7]) , 1'b0 , (acc_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~ (ACC1_acc_338_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_338_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_210_psp_2_sva[3]) ,
+      (acc_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_220_psp_1_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_2_sva[3])
+      , (acc_psp_2_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_210_psp_2_sva[3]) ,
+      (acc_psp_2_sva[2]) , (ACC1_acc_210_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_2_sva[7])
+      , (acc_psp_2_sva[4]) , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_673_cse)))
+      + conv_u2s_7_8({(acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])
+      , 1'b0 , (acc_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_2_sva[6])
+      , 1'b0 , (acc_psp_2_sva[6]) , 1'b0 , (acc_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_673_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , ACC1_1_and_3_cse_sva}))))))))))
+      + ({(acc_psp_2_sva[11]) , 2'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11])
+      , 1'b0 , (acc_psp_2_sva[11]) , (conv_u2u_1_3(acc_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])))}))
+      + conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_20_psp_2_sva[10]) , 1'b0
+      , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10])
+      , 1'b0 , (acc_20_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_20_psp_2_sva[9]) ,
+      1'b0 , (acc_20_psp_2_sva[9]) , 1'b0 , (acc_20_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_20_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_20_psp_2_sva[7]) , 1'b0 , (acc_20_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_20_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~((ACC1_acc_359_itm[2])
+      & (~ (acc_20_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~ (ACC1_acc_358_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (ACC1_acc_358_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (ACC1_acc_217_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_20_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_217_psp_2_sva[3])
+      , (acc_20_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_223_psp_1_sva[2:1])) +
+      (readslicef_5_4_1((conv_u2s_3_5({(acc_20_psp_2_sva[3]) , (acc_20_psp_2_sva[1])
+      , 1'b1}) + conv_s2s_3_5({(ACC1_acc_217_psp_2_sva[3]) , (acc_20_psp_2_sva[2])
+      , (ACC1_acc_217_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_20_psp_2_sva[7])
+      , (acc_20_psp_2_sva[4]) , (signext_2_1(acc_20_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_699_cse)))
+      + conv_u2s_7_8({(acc_20_psp_2_sva[8]) , 1'b0 , (acc_20_psp_2_sva[8]) , 1'b0
+      , (acc_20_psp_2_sva[8]) , 1'b0 , (acc_20_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_20_psp_2_sva[11])
+      , (signext_2_1(acc_20_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_20_psp_2_sva[6])
+      , 1'b0 , (acc_20_psp_2_sva[6]) , 1'b0 , (acc_20_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_699_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[9]) , ((acc_20_psp_2_sva[11])
+      & (~ (ACC1_acc_359_itm[2])) & (ACC1_acc_359_itm[1]))})))))))))) + ({(acc_20_psp_2_sva[11])
+      , 2'b0 , (acc_20_psp_2_sva[11]) , 1'b0 , (acc_20_psp_2_sva[11]) , 1'b0 , (acc_20_psp_2_sva[11])
+      , (conv_u2u_1_3(acc_20_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])))})));
+  assign nl_ACC1_acc_658_itm_1  = conv_s2s_12_13(conv_s2s_10_12(conv_s2s_9_10(conv_u2s_7_9(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(ACC1_acc_224_psp_1_sva[6])
+      , (ACC1_acc_228_psp_sva[3]) , (signext_2_1(ACC1_acc_224_psp_sva[11]))}) + conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[5])
+      , (ACC1_acc_226_psp_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})) +
+      conv_u2u_5_6(conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[7]) , (ACC1_acc_224_psp_1_sva[3])
+      , (signext_2_1(ACC1_acc_228_psp_sva[11]))}) + conv_u2u_4_5({(acc_20_psp_1_sva[4])
+      , (ACC1_1_acc_25_psp_sva[4]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(~ (ACC1_acc_217_psp_1_sva[3])) ,
+      (~ (ACC1_acc_210_psp_1_sva[3])) , 1'b1 , (~ (ACC1_acc_367_itm[3]))}) + conv_u2u_4_5({(acc_psp_2_sva[5])
+      , (acc_20_psp_1_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})) + conv_s2u_5_6(conv_u2s_3_5(readslicef_4_3_1((conv_u2u_3_4({((acc_20_psp_1_sva[11])
+      & (~ (ACC1_acc_424_itm[2])) & (ACC1_acc_424_itm[1])) , (ACC1_acc_224_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_3_4({(acc_psp_2_sva[3]) , (ACC1_acc_224_psp_1_sva[2]) ,
+      (ACC1_1_acc_25_psp_sva[2])})))) + conv_s2s_3_5({(ACC1_acc_223_psp_sva[2:1])
+      , (ACC1_acc_224_psp_1_sva[3])})))) + conv_s2s_7_9(conv_s2s_6_7(conv_s2s_4_6(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_s2s_3_5({(ACC1_acc_220_psp_1_sva[2:1]) , (ACC1_acc_377_itm[2])}))))
+      + conv_u2s_4_6({(ACC1_acc_224_psp_1_sva[4]) , (ACC1_acc_224_psp_sva[3]) , (signext_2_1(ACC1_acc_224_psp_sva[11]))}))
+      + conv_s2s_6_7(conv_u2s_4_6({(acc_psp_2_sva[7]) , (acc_psp_2_sva[4]) , (signext_2_1(ACC1_acc_228_psp_sva[6]))})
+      + conv_s2s_3_6(conv_s2s_2_3(ACC1_acc_220_psp_sva[2:1]) + conv_s2s_2_3(ACC1_acc_222_psp_sva[2:1])))))
+      + conv_u2s_9_10({(acc_20_psp_1_sva[9]) , 1'b0 , (acc_20_psp_1_sva[9]) , 1'b0
+      , (acc_20_psp_1_sva[9]) , (ACC1_acc_228_psp_sva[4]) , 1'b0 , (signext_2_1(ACC1_acc_224_psp_sva[6]))}))
+      + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_4_10(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[8])
+      + conv_u2u_1_2(acc_psp_1_sva[8])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[7]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[7])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[7]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[7])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[8]))
+      + conv_u2u_1_4(acc_psp_2_sva[8])) * 10'b1010101))) + conv_u2s_12_14(conv_u2s_24_13(conv_u2u_4_12(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[10])
+      + conv_u2u_1_2(acc_psp_1_sva[10])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[9]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[9])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[9]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[9])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[10]))
+      + conv_u2u_1_4(acc_psp_2_sva[10])) * 12'b101010101));
+  assign nl_ACC1_acc_661_itm_1  = conv_s2s_13_14(conv_s2s_12_13({(ACC1_acc_226_psp_sva[11])
+      , 1'b0 , (ACC1_acc_226_psp_sva[11]) , 7'b0 , (ACC1_acc_226_psp_sva[11]) , (acc_psp_1_sva[2])})
+      + conv_u2s_12_13({conv_u2u_18_9(conv_u2u_3_9(conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_224_psp_sva[10])
+      + conv_u2u_1_2(ACC1_acc_228_psp_sva[10])) + conv_u2u_1_2(ACC1_acc_226_psp_sva[10]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[10])) * 9'b1010101) , (acc_psp_1_sva[4])
+      , (signext_2_1(ACC1_acc_224_psp_sva[4]))})) + conv_s2s_13_14(conv_s2s_26_13(conv_u2s_2_13((conv_u2u_1_2(ACC1_acc_227_psp_sva[11])
+      + conv_u2u_1_2(acc_psp_1_sva[11])) + conv_u2u_1_2(acc_psp_2_sva[11])) * 13'b1110010101001));
+  assign nl_ACC1_acc_652_itm_1  = conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[4])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[3])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_405_itm[2])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_3_acc_212_psp_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[5]) , (ACC1_3_acc_212_psp_sva[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_3_acc_212_psp_sva[1])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[9]) , ((ACC1_acc_226_psp_sva[11])
+      & (~ (ACC1_acc_387_itm[2])) & (ACC1_acc_387_itm[1]))})))))))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (~((ACC1_acc_387_itm[2])
+      & (~ (ACC1_acc_226_psp_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11]) , (ACC1_acc_386_itm[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11]) , (ACC1_acc_384_itm[4])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[5])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_384_itm[3])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (ACC1_acc_384_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , ((ACC1_acc_228_psp_sva[11])
+      & (~ (ACC1_acc_378_itm[2])) & (ACC1_acc_378_itm[1]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (~((ACC1_acc_378_itm[2])
+      & (~ (ACC1_acc_228_psp_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_375_itm[4])})))))))))
+      + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_375_itm[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , (ACC1_acc_375_itm[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ((ACC1_acc_224_psp_sva[11])
+      & (~ (ACC1_acc_415_itm[2])) & (ACC1_acc_415_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~((ACC1_acc_415_itm[2])
+      & (~ (ACC1_acc_224_psp_sva[11]))))}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_414_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_412_itm[4])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[5]) , (ACC1_acc_412_itm[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_412_itm[2])}))))))))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_227_psp_sva[3])
+      , (ACC1_acc_227_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(acc_psp_1_sva[3]) , (ACC1_acc_227_psp_sva[2])
+      , ((acc_psp_1_sva[11]) & (~ (ACC1_acc_396_itm[2])) & (ACC1_acc_396_itm[1]))}))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_224_psp_sva[2]) ,
+      (ACC1_acc_227_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[2])
+      , (ACC1_acc_227_psp_sva[4]) , (~((ACC1_acc_396_itm[2]) & (~ (acc_psp_1_sva[11]))))})))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_226_psp_sva[2])
+      , (acc_psp_1_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_224_psp_1_sva[2]) ,
+      (acc_psp_1_sva[3]) , (ACC1_acc_395_itm[2])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_1_acc_25_psp_sva[3])
+      , (acc_psp_1_sva[4]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[1]) , (ACC1_acc_224_psp_sva[1])
+      , (ACC1_acc_210_psp_1_sva[3])})))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[2])
+      , (ACC1_acc_224_psp_sva[2]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[3])
+      , (ACC1_acc_224_psp_sva[3]) , (ACC1_acc_210_psp_1_sva[2])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[4])
+      , (ACC1_acc_228_psp_sva[0]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[1])
+      , (ACC1_acc_226_psp_sva[0]) , (ACC1_acc_210_psp_1_sva[1])}))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[2])
+      , (ACC1_acc_226_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[3])
+      , (ACC1_acc_226_psp_sva[2]) , (ACC1_1_acc_25_psp_sva[4])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_423_itm[2])
+      , (ACC1_acc_226_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(~((ACC1_acc_424_itm[2])
+      & (~ (acc_20_psp_1_sva[11])))) , (ACC1_acc_224_psp_1_sva[0]) , (ACC1_1_acc_25_psp_sva[3])})))))))))
+      + conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_3_4({(acc_20_psp_1_sva[6]) , 1'b0 ,
+      (acc_20_psp_1_sva[6])}) + conv_u2u_3_4({(acc_psp_1_sva[7]) , (acc_20_psp_1_sva[5])
+      , (ACC1_acc_226_psp_sva[4])})) , (conv_u2u_2_3({(acc_20_psp_1_sva[6]) , (ACC1_acc_228_psp_sva[1])})
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[10])))}) + conv_u2u_7_8({(conv_u2u_3_4({(ACC1_acc_224_psp_sva[6])
+      , (acc_20_psp_1_sva[7]) , (ACC1_acc_226_psp_sva[6])}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[6])
+      , 1'b0 , (ACC1_acc_227_psp_sva[5])})) , ACC1_acc_724_cse}))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_1_2(ACC1_acc_226_psp_sva[6])
+      + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[6])) , (conv_u2u_1_2(ACC1_acc_227_psp_sva[7])
+      + conv_u2u_1_2(acc_psp_1_sva[5])) , ACC1_acc_724_cse}) + conv_u2u_7_8({(conv_u2u_1_2(ACC1_1_acc_25_psp_sva[7])
+      + conv_u2u_1_2(acc_psp_2_sva[7])) , (conv_u2u_1_2(acc_psp_1_sva[7]) + conv_u2u_1_2(ACC1_acc_224_psp_sva[4]))
+      , ACC1_acc_724_cse})) + conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_227_psp_sva[11])
+      , (signext_2_1(ACC1_acc_227_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_1_sva[11])
+      , (signext_2_1(acc_psp_1_sva[11]))}))))) + conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_sva[11])
+      , (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_228_psp_sva[11])
+      , (signext_2_1(ACC1_acc_228_psp_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(acc_20_psp_1_sva[11])
+      , 1'b0 , (signext_2_1(acc_20_psp_1_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_20_psp_1_sva[11])
+      , (signext_2_1(acc_20_psp_1_sva[11]))})))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_acc_226_psp_sva[11])
+      , 1'b0 , (signext_2_1(ACC1_acc_226_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_1_sva[11])
+      , (signext_2_1(ACC1_acc_224_psp_1_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b0 , (signext_2_1(ACC1_1_acc_25_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})))));
+  assign nl_ACC1_acc_655_itm_1  = conv_s2s_11_12(conv_u2s_10_11({(acc_20_psp_1_sva[10])
+      , 1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10])
+      , 1'b0 , (acc_20_psp_1_sva[10]) , (ACC1_acc_228_psp_sva[3])}) + conv_s2s_9_11(conv_s2s_8_9(({7'b1011011
+      , (ACC1_1_acc_25_psp_sva[1])}) + conv_u2s_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse)
+      + conv_u2u_3_4(ACC1_acc_509_cse)) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[5]))) + conv_u2u_3_4(ACC1_acc_506_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+      + conv_u2u_3_4(ACC1_acc_502_cse)))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+      + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[7]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[9]))
+      + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))))) + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+      + conv_u2u_4_5(ACC1_acc_562_ncse))))) + conv_u2s_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_502_cse)
+      + conv_u2u_3_4(ACC1_acc_506_cse)) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+      + conv_u2u_3_4(ACC1_acc_489_cse))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[6]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[8]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[10]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_u2u_4_5(ACC1_acc_553_ncse)))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_553_ncse) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_489_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[9]) , ACC1_1_and_3_cse_sva}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_338_itm[2])})))))))))
+      + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[1])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[9]) , (acc_psp_2_sva[4])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (acc_psp_2_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (acc_psp_2_sva[1])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , ((ACC1_acc_227_psp_sva[11])
+      & (~ (ACC1_acc_406_itm[2])) & (ACC1_acc_406_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[6])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[8]) , (~((ACC1_acc_406_itm[2])
+      & (~ (ACC1_acc_227_psp_sva[11]))))})))))))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[10])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , ((ACC1_1_acc_25_psp_sva[11])
+      & (~ (ACC1_acc_368_itm[2])) & (ACC1_acc_368_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (~((ACC1_acc_368_itm[2])
+      & (~ (ACC1_1_acc_25_psp_sva[11]))))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_acc_367_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_1_acc_208_psp_sva[3])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[4]) , (ACC1_1_acc_208_psp_sva[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_1_acc_208_psp_sva[1])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (~((ACC1_acc_349_itm[2])
+      & (~ (ACC1_acc_224_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[9]) , (ACC1_acc_348_itm[2])}))))))))))))
+      + conv_u2s_10_12(conv_u2u_8_10((conv_u2u_7_8({(acc_20_psp_1_sva[7]) , (ACC1_acc_227_psp_sva[7])
+      , 1'b0 , (ACC1_acc_224_psp_sva[6]) , 1'b0 , (signext_2_1(ACC1_acc_224_psp_sva[11]))})
+      + conv_u2u_6_8(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[10]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+      + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_516_cse) + conv_u2u_3_4(ACC1_acc_516_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+      + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))))))) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_412_itm[4])) , (~ (ACC1_acc_423_itm[3])) , (~ (ACC1_acc_338_itm[3]))})
+      + conv_u2u_3_4({(~ (ACC1_acc_375_itm[4])) , 1'b1 , (~ (ACC1_acc_395_itm[3]))}))
+      + conv_u2u_4_5({(readslicef_3_2_1((conv_u2u_2_3({(~ (ACC1_acc_384_itm[4]))
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_3_acc_212_psp_sva[3])) , 1'b1})))) , (({1'b1
+      , (~ (ACC1_acc_414_itm[3]))}) + ({1'b1 , (~ (ACC1_acc_377_itm[3]))}))})) +
+      conv_u2u_5_6(conv_u2u_4_5({(readslicef_3_2_1((conv_u2u_2_3({(~ (ACC1_acc_346_itm[4]))
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_208_psp_sva[3])) , 1'b1})))) , (({1'b1
+      , (~ (ACC1_acc_386_itm[3]))}) + ({1'b1 , (~ (ACC1_acc_405_itm[3]))}))}) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_210_psp_2_sva[3])) , 1'b1 , (~ (ACC1_acc_348_itm[3]))}) + conv_s2u_2_4(ACC1_acc_221_psp_sva[2:1]))))
+      + conv_s2u_6_7(conv_s2s_5_6(conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_221_psp_2_sva[2:1])
+      + conv_u2s_2_4(signext_2_1(ACC1_acc_228_psp_sva[8]))) + conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_219_psp_2_sva[2:1])
+      + conv_u2s_2_4(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_s2s_5_6(conv_s2s_4_5(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_s2s_3_5({(ACC1_acc_222_psp_1_sva[2:1]) , (acc_psp_2_sva[2])}))))
+      + conv_s2s_4_5(readslicef_5_4_1((conv_s2s_3_5({(ACC1_acc_219_psp_1_sva[2:1])
+      , 1'b1}) + conv_u2s_3_5(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , ((ACC1_acc_224_psp_1_sva[11])
+      & (~ (ACC1_acc_349_itm[2])) & (ACC1_acc_349_itm[1]))}))))))))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[6])
+      + conv_u2u_1_2(acc_psp_1_sva[6])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[5]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[5])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[5]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[5])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[6]))
+      + conv_u2u_1_4(acc_psp_2_sva[6])) * 8'b10101)) + conv_u2u_8_9({(acc_20_psp_1_sva[8])
+      , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0 , (acc_20_psp_1_sva[8])
+      , (ACC1_acc_228_psp_sva[2])})));
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [2:0] signext_3_2;
+    input [1:0] vector;
+  begin
+    signext_3_2= {{1{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_3;
+    input [2:0] vector;
+  begin
+    signext_7_3= {{4{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_4;
+    input [3:0] vector;
+  begin
+    signext_7_4= {{3{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_7_10 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_10 = {{3{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [14:0] conv_s2s_14_15 ;
+    input signed [13:0]  vector ;
+  begin
+    conv_s2s_14_15 = {vector[13], vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_13_14 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_14 = {vector[12], vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_2_14 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_14 = {{12{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_4_8 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_8 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_1_4 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_4 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_6_8 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_8 = {{2{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_9_10 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_10 = {vector[8], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_s2u_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2u_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_3_6 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_6 = {{3{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_4_10 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_10 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_24_13 ;
+    input [23:0]  vector ;
+  begin
+    conv_u2s_24_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_4_12 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_12 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_26_13 ;
+    input signed [25:0]  vector ;
+  begin
+    conv_s2s_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_9_11 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_11 = {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_8_9 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_9 = {vector[7], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_s2u_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2u_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_s2u_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2u_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v11/cycle.rpt b/Sobel/sobel.v11/cycle.rpt
new file mode 100644
index 0000000..8ca73a7
--- /dev/null
+++ b/Sobel/sobel.v11/cycle.rpt
@@ -0,0 +1,85 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 16:15:02 +0000 2016                      
+
+Solution Settings: sobel.v11
+  Current state: schedule
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       677  307201     307200            0  1          
+    Design Total:                     677  307201     307200            0  0          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /sobel/core              
+    
+  I/O Data Ranges
+    Port       Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ---------- ---- -------- --------- --------- ------- -------- --------
+    vin:rsc.z  IN   Unsigned        90                                     
+    clk        IN   Unsigned         1                                     
+    en         IN   Unsigned         1                                     
+    arst_n     IN   Unsigned         1                                     
+    vout:rsc.z OUT  Unsigned        30                                     
+    
+  Memory Resources
+    Resource Name: /sobel/vin:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 90
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable   Indices Phys Memory Address     
+      ---------- ------- -----------------------
+      /sobel/vin    0:89 00000000-00000000 (0-0) 
+      
+    Resource Name: /sobel/vout:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 30
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable    Indices Phys Memory Address     
+      ----------- ------- -----------------------
+      /sobel/vout    0:29 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process     Loop             Iterations C-Steps Total Cycles  Duration  Unroll Init Comments 
+    ----------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
+    /sobel/core core:rlp           Infinite       0       307202   6.14 ms                       
+    /sobel/core   main             Infinite       3       307202   6.14 ms            1          
+    
+  Loop Execution Profile
+    Process     Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------- ---------------- ------------ -------------------------- ----------------- --------
+    /sobel/core core:rlp                   0                        0.00           307200           
+    /sobel/core   main                307202                      100.00           307200           
+    
+  End of Report
diff --git a/Sobel/sobel.v11/cycle.v b/Sobel/sobel.v11/cycle.v
new file mode 100644
index 0000000..0b71fde
--- /dev/null
+++ b/Sobel/sobel.v11/cycle.v
@@ -0,0 +1,1598 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 16:15:04 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg [89:0] regs_regs_1_sva;
+    reg [89:0] regs_regs_0_sva;
+    reg [89:0] regs_regs_0_sva_1;
+    reg [11:0] acc_psp_2_sva;
+    reg [3:0] ACC1_acc_210_psp_2_sva;
+    reg [2:0] ACC1_acc_220_psp_1_sva;
+    reg [2:0] acc_imod_26_sva;
+    reg [1:0] acc_imod_32_sva;
+    reg ACC1_1_nand_1_cse_sva;
+    reg ACC1_1_and_3_cse_sva;
+    reg [11:0] ACC1_acc_224_psp_1_sva;
+    reg [3:0] ACC1_acc_214_psp_2_sva;
+    reg [2:0] ACC1_acc_222_psp_1_sva;
+    reg [2:0] acc_imod_34_sva;
+    reg [1:0] acc_imod_36_sva;
+    reg [11:0] acc_20_psp_2_sva;
+    reg [3:0] ACC1_acc_217_psp_2_sva;
+    reg [2:0] ACC1_acc_223_psp_1_sva;
+    reg [2:0] acc_imod_38_sva;
+    reg [1:0] acc_imod_40_sva;
+    reg [11:0] ACC1_1_acc_25_psp_sva;
+    reg [3:0] ACC1_1_acc_208_psp_sva;
+    reg [2:0] ACC1_acc_219_psp_1_sva;
+    reg [2:0] acc_imod_42_sva;
+    reg [1:0] acc_imod_44_sva;
+    reg [11:0] ACC1_acc_228_psp_sva;
+    reg [3:0] ACC1_2_acc_212_psp_sva;
+    reg [2:0] ACC1_acc_221_psp_2_sva;
+    reg [2:0] acc_imod_31_sva;
+    reg [1:0] acc_imod_33_sva;
+    reg [11:0] ACC1_acc_226_psp_sva;
+    reg [3:0] ACC1_2_acc_208_psp_sva;
+    reg [2:0] ACC1_acc_219_psp_2_sva;
+    reg [2:0] acc_imod_43_sva;
+    reg [1:0] acc_imod_45_sva;
+    reg [11:0] acc_psp_1_sva;
+    reg [3:0] ACC1_acc_210_psp_1_sva;
+    reg [2:0] ACC1_acc_220_psp_sva;
+    reg [2:0] acc_imod_2_sva;
+    reg [1:0] acc_imod_3_sva;
+    reg [11:0] ACC1_acc_227_psp_sva;
+    reg [3:0] ACC1_3_acc_212_psp_sva;
+    reg [2:0] ACC1_acc_221_psp_sva;
+    reg [2:0] acc_imod_6_sva;
+    reg [1:0] acc_imod_7_sva;
+    reg [11:0] ACC1_acc_224_psp_sva;
+    reg [3:0] ACC1_acc_214_psp_1_sva;
+    reg [2:0] ACC1_acc_222_psp_sva;
+    reg [2:0] acc_imod_10_sva;
+    reg [1:0] acc_imod_11_sva;
+    reg [11:0] acc_20_psp_1_sva;
+    reg [3:0] ACC1_acc_217_psp_1_sva;
+    reg [2:0] ACC1_acc_223_psp_sva;
+    reg [2:0] acc_imod_18_sva;
+    reg [1:0] acc_imod_19_sva;
+    reg [13:0] ACC1_slc_psp_sva;
+    reg [5:0] acc_imod_24_sva;
+    reg [11:0] FRAME_acc_2_psp_sva;
+    reg [9:0] regs_regs_slc_regs_regs_2_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_1_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_2_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_4_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_5_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_3_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_10_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_11_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_9_itm;
+    reg [12:0] ACC1_acc_659_itm_1;
+    reg [12:0] ACC1_acc_658_itm_1;
+    reg [13:0] ACC1_acc_661_itm_1;
+    reg [13:0] ACC1_mul_57_itm;
+    reg slc_acc_20_psp_1_93_itm_1;
+    reg slc_acc_20_psp_1_94_itm_1;
+    reg slc_acc_20_psp_1_95_itm_1;
+    reg slc_acc_20_psp_1_81_itm_1;
+    reg ACC1_slc_ACC1_acc_228_psp_55_itm_1;
+    reg ACC1_3_slc_acc_10_psp_62_itm_1;
+    reg [10:0] ACC1_acc_652_itm_1;
+    reg [11:0] ACC1_acc_655_itm_1;
+    reg main_stage_0_2;
+    reg [2:0] ACC1_acc_673_cse;
+    reg [2:0] ACC1_acc_699_cse;
+    reg [2:0] ACC1_acc_724_cse;
+    reg [2:0] ACC1_acc_509_cse;
+    reg [2:0] ACC1_acc_506_cse;
+    reg [2:0] ACC1_acc_502_cse;
+    reg [2:0] ACC1_acc_489_cse;
+    reg [2:0] ACC1_acc_516_cse;
+    reg [3:0] ACC1_acc_562_ncse;
+    reg [3:0] ACC1_acc_553_ncse;
+    reg [4:0] ACC1_mul_57_itm_1_sg2;
+    reg [1:0] ACC1_mul_57_itm_2;
+
+    begin : core_rlpExit
+      forever begin : core_rlp
+        // C-Step 0 of Loop 'core_rlp'
+        regs_regs_1_sva = 90'b0;
+        regs_regs_0_sva = 90'b0;
+        main_stage_0_2 = 1'b0;
+        begin : mainExit
+          forever begin : main
+            // C-Step 0 of Loop 'main'
+            regs_regs_slc_regs_regs_2_itm = regs_regs_1_sva[29:20];
+            regs_regs_slc_regs_regs_2_1_itm = regs_regs_1_sva[19:10];
+            regs_regs_slc_regs_regs_2_2_itm = regs_regs_1_sva[9:0];
+            regs_regs_slc_regs_regs_2_4_itm = regs_regs_1_sva[49:40];
+            regs_regs_slc_regs_regs_2_5_itm = regs_regs_1_sva[39:30];
+            regs_regs_slc_regs_regs_2_3_itm = regs_regs_1_sva[59:50];
+            regs_regs_slc_regs_regs_2_10_itm = regs_regs_1_sva[79:70];
+            regs_regs_slc_regs_regs_2_11_itm = regs_regs_1_sva[69:60];
+            regs_regs_slc_regs_regs_2_9_itm = regs_regs_1_sva[89:80];
+            regs_regs_1_sva = regs_regs_0_sva;
+            begin : waitLoop0Exit
+              forever begin : waitLoop0
+                @(posedge clk or negedge ( arst_n ));
+                if ( ~ arst_n )
+                  disable core_rlpExit;
+                if ( en )
+                  disable waitLoop0Exit;
+              end
+            end
+            // C-Step 1 of Loop 'main'
+            if ( main_stage_0_2 ) begin
+              ACC1_slc_psp_sva = readslicef_15_14_1(((conv_s2s_14_15(conv_s2s_13_14(ACC1_acc_659_itm_1)
+                  + conv_s2s_13_14(ACC1_acc_658_itm_1)) + conv_s2s_14_15(ACC1_acc_661_itm_1))
+                  + conv_s2s_14_15(({ACC1_mul_57_itm_1_sg2 , 7'b0 , ACC1_mul_57_itm_2})
+                  + conv_s2s_13_14(conv_s2s_12_13(({slc_acc_20_psp_1_93_itm_1 , 2'b0
+                  , slc_acc_20_psp_1_94_itm_1 , 1'b0 , slc_acc_20_psp_1_95_itm_1
+                  , 1'b0 , slc_acc_20_psp_1_81_itm_1 , ACC1_slc_ACC1_acc_228_psp_55_itm_1
+                  , 1'b0 , ({{1{ACC1_3_slc_acc_10_psp_62_itm_1}}, ACC1_3_slc_acc_10_psp_62_itm_1})})
+                  + conv_u2s_11_12(ACC1_acc_652_itm_1)) + conv_s2s_12_13(ACC1_acc_655_itm_1)))));
+              acc_imod_24_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_slc_psp_sva[8:6])
+                  + conv_u2u_3_4(~ (ACC1_slc_psp_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                  (ACC1_slc_psp_sva[13])) , 1'b1 , (~ (ACC1_slc_psp_sva[13]))}) +
+                  conv_u2u_2_4(ACC1_slc_psp_sva[13:12]))) + conv_u2u_4_6(conv_u2u_3_4(ACC1_slc_psp_sva[2:0])
+                  + conv_u2u_3_4(~ (ACC1_slc_psp_sva[5:3])))) + 6'b101011;
+              FRAME_acc_2_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(ACC1_slc_psp_sva[13:12])
+                  * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_slc_psp_sva[11:9])
+                  * 9'b111001)) + conv_s2s_7_10(conv_u2s_6_7(ACC1_slc_psp_sva[8:3])
+                  + conv_s2s_5_7(({4'b1001 , (acc_imod_24_sva[5])}) + conv_u2s_4_5((conv_u2u_3_4({(~
+                  (acc_imod_24_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_24_sva[2:0])
+                  , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_24_sva[5:3])) , (~ (acc_imod_24_sva[5]))})))))})
+                  + conv_u2u_2_4(acc_imod_24_sva[4:3])) + conv_u2u_3_4(~ (ACC1_slc_psp_sva[8:6])))))))
+                  + conv_u2u_11_12(signext_11_9({(ACC1_slc_psp_sva[13]) , 3'b0 ,
+                  (signext_3_1(ACC1_slc_psp_sva[13])) , 1'b0 , (ACC1_slc_psp_sva[13])}));
+              vout_rsc_mgc_out_stdreg_d <= {((FRAME_acc_2_psp_sva[9:0]) | ({8'b0,
+                  FRAME_acc_2_psp_sva[11:10]})) , (FRAME_acc_2_psp_sva[9:6]) , ((FRAME_acc_2_psp_sva[5:0])
+                  | ({4'b0, FRAME_acc_2_psp_sva[11:10]})) , (FRAME_acc_2_psp_sva[9:0])};
+            end
+            regs_regs_0_sva_1 = vin_rsc_mgc_in_wire_d;
+            acc_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (regs_regs_0_sva_1[29:20]))
+                + conv_s2s_10_11(~ (regs_regs_0_sva_1[19:10]))) + conv_s2s_11_12(conv_s2s_10_11(~
+                (regs_regs_0_sva_1[9:0])) + 11'b11);
+            ACC1_acc_210_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                (acc_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_2_sva[1]))
+                , (acc_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_2_sva[0])
+                , (acc_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[3])) , (~ (acc_psp_2_sva[7]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[5])) , (acc_psp_2_sva[6])}))))
+                , (~ (acc_psp_2_sva[9]))}))));
+            ACC1_acc_220_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_2_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_2_sva[1])) , (ACC1_acc_210_psp_2_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_acc_210_psp_2_sva[3]));
+            acc_imod_26_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_220_psp_1_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_220_psp_1_sva[0]) , 1'b1})));
+            acc_imod_32_sva = readslicef_3_2_1((({1'b1 , (acc_imod_26_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_26_sva[1])) , (~ (acc_imod_26_sva[2]))})));
+            ACC1_1_nand_1_cse_sva = ~((acc_imod_32_sva[1]) & (~ (acc_psp_2_sva[11])));
+            ACC1_1_and_3_cse_sva = (acc_psp_2_sva[11]) & (~ (acc_imod_32_sva[1]))
+                & (acc_imod_32_sva[0]);
+            ACC1_acc_224_psp_1_sva = conv_s2u_11_12(conv_s2s_10_11(~ (regs_regs_0_sva_1[39:30]))
+                + conv_s2s_10_11(~ (regs_regs_0_sva_1[49:40]))) + conv_s2u_11_12(conv_s2s_10_11(~
+                (regs_regs_0_sva_1[59:50])) + 11'b11);
+            ACC1_acc_214_psp_2_sva = readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((({2'b10
+                , (~ (ACC1_acc_224_psp_1_sva[0])) , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[1])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[2])) , (~ (ACC1_acc_224_psp_1_sva[6]))}))))
+                , (~ (ACC1_acc_224_psp_1_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[3])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[4])) , (ACC1_acc_224_psp_1_sva[5])}))))
+                , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_1_sva[11:10])) , (ACC1_acc_224_psp_1_sva[7])}))))
+                , (ACC1_acc_224_psp_1_sva[9])})));
+            ACC1_acc_222_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_214_psp_2_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_214_psp_2_sva[1])) , (ACC1_acc_214_psp_2_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_acc_214_psp_2_sva[3]));
+            acc_imod_34_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_222_psp_1_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_222_psp_1_sva[0]) , 1'b1})));
+            acc_imod_36_sva = readslicef_3_2_1((({1'b1 , (acc_imod_34_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_34_sva[1])) , (~ (acc_imod_34_sva[2]))})));
+            acc_20_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (regs_regs_0_sva_1[89:80]))
+                + conv_s2s_10_11(~ (regs_regs_0_sva_1[79:70]))) + conv_s2s_11_12(conv_s2s_10_11(~
+                (regs_regs_0_sva_1[69:60])) + 11'b11);
+            ACC1_acc_217_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                (acc_20_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_2_sva[1]))
+                , (acc_20_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_2_sva[0])
+                , (acc_20_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[3])) , (~ (acc_20_psp_2_sva[7]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[5])) , (acc_20_psp_2_sva[6])}))))
+                , (~ (acc_20_psp_2_sva[9]))}))));
+            ACC1_acc_223_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_2_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_2_sva[1])) , (ACC1_acc_217_psp_2_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_acc_217_psp_2_sva[3]));
+            acc_imod_38_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_223_psp_1_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_223_psp_1_sva[0]) , 1'b1})));
+            acc_imod_40_sva = readslicef_3_2_1((({1'b1 , (acc_imod_38_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_38_sva[1])) , (~ (acc_imod_38_sva[2]))})));
+            ACC1_1_acc_25_psp_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_0_sva_1[79:70])
+                + conv_s2s_10_11(regs_regs_0_sva_1[69:60])) + conv_s2s_10_12(regs_regs_0_sva_1[89:80]);
+            ACC1_1_acc_208_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                (ACC1_1_acc_25_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_1_acc_25_psp_sva[1]))
+                , (ACC1_1_acc_25_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10
+                , (ACC1_1_acc_25_psp_sva[0]) , (ACC1_1_acc_25_psp_sva[10])})))) +
+                conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[3])) , (~ (ACC1_1_acc_25_psp_sva[7]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[5])) , (ACC1_1_acc_25_psp_sva[6])}))))
+                , (~ (ACC1_1_acc_25_psp_sva[9]))}))));
+            ACC1_acc_219_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_208_psp_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_208_psp_sva[1])) , (ACC1_1_acc_208_psp_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_1_acc_208_psp_sva[3]));
+            acc_imod_42_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_219_psp_1_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_1_sva[0]) , 1'b1})));
+            acc_imod_44_sva = readslicef_3_2_1((({1'b1 , (acc_imod_42_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_42_sva[1])) , (~ (acc_imod_42_sva[2]))})));
+            ACC1_acc_228_psp_sva = conv_s2u_11_12(conv_s2s_10_11(~ (regs_regs_0_sva[9:0]))
+                + conv_s2s_10_11(~ (regs_regs_0_sva[19:10]))) + conv_s2u_11_12(conv_s2s_10_11(~
+                (regs_regs_0_sva[29:20])) + 11'b11);
+            ACC1_2_acc_212_psp_sva = readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((({2'b10
+                , (~ (ACC1_acc_228_psp_sva[0])) , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[1])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[2])) , (~ (ACC1_acc_228_psp_sva[6]))}))))
+                , (~ (ACC1_acc_228_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[3])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[4])) , (ACC1_acc_228_psp_sva[5])}))))
+                , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_228_psp_sva[11:10])) , (ACC1_acc_228_psp_sva[7])}))))
+                , (ACC1_acc_228_psp_sva[9])})));
+            ACC1_acc_221_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_2_acc_212_psp_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_2_acc_212_psp_sva[1])) , (ACC1_2_acc_212_psp_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_2_acc_212_psp_sva[3]));
+            acc_imod_31_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_221_psp_2_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_221_psp_2_sva[0]) , 1'b1})));
+            acc_imod_33_sva = readslicef_3_2_1((({1'b1 , (acc_imod_31_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_31_sva[1])) , (~ (acc_imod_31_sva[2]))})));
+            ACC1_acc_226_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_0_sva[79:70])
+                + conv_s2s_10_11(regs_regs_0_sva[69:60])) + conv_s2u_10_12(regs_regs_0_sva[89:80]);
+            ACC1_2_acc_208_psp_sva = readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((({2'b10
+                , (~ (ACC1_acc_226_psp_sva[0])) , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[1])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[2])) , (~ (ACC1_acc_226_psp_sva[6]))}))))
+                , (~ (ACC1_acc_226_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[3])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[4])) , (ACC1_acc_226_psp_sva[5])}))))
+                , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_226_psp_sva[11:10])) , (ACC1_acc_226_psp_sva[7])}))))
+                , (ACC1_acc_226_psp_sva[9])})));
+            ACC1_acc_219_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_2_acc_208_psp_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_2_acc_208_psp_sva[1])) , (ACC1_2_acc_208_psp_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_2_acc_208_psp_sva[3]));
+            acc_imod_43_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_219_psp_2_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_2_sva[0]) , 1'b1})));
+            acc_imod_45_sva = readslicef_3_2_1((({1'b1 , (acc_imod_43_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_43_sva[1])) , (~ (acc_imod_43_sva[2]))})));
+            acc_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_1_itm)
+                + conv_s2s_10_11(regs_regs_slc_regs_regs_2_2_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_itm);
+            ACC1_acc_210_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                (acc_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_1_sva[1]))
+                , (acc_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_1_sva[0])
+                , (acc_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[3])) , (~ (acc_psp_1_sva[7]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[5])) , (acc_psp_1_sva[6])}))))
+                , (~ (acc_psp_1_sva[9]))}))));
+            ACC1_acc_220_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_1_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_1_sva[1])) , (ACC1_acc_210_psp_1_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_acc_210_psp_1_sva[3]));
+            acc_imod_2_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_220_psp_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_220_psp_sva[0]) , 1'b1})));
+            acc_imod_3_sva = readslicef_3_2_1((({1'b1 , (acc_imod_2_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_2_sva[1])) , (~ (acc_imod_2_sva[2]))})));
+            ACC1_acc_227_psp_sva = conv_s2s_11_12(conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_itm)
+                + conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_1_itm)) + conv_s2s_11_12(conv_s2s_10_11(~
+                regs_regs_slc_regs_regs_2_2_itm) + 11'b11);
+            ACC1_3_acc_212_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                (ACC1_acc_227_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_acc_227_psp_sva[1]))
+                , (ACC1_acc_227_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 ,
+                (ACC1_acc_227_psp_sva[0]) , (ACC1_acc_227_psp_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[3])) , (~ (ACC1_acc_227_psp_sva[7]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[5])) , (ACC1_acc_227_psp_sva[6])}))))
+                , (~ (ACC1_acc_227_psp_sva[9]))}))));
+            ACC1_acc_221_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_3_acc_212_psp_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_3_acc_212_psp_sva[1])) , (ACC1_3_acc_212_psp_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_3_acc_212_psp_sva[3]));
+            acc_imod_6_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_221_psp_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_221_psp_sva[0]) , 1'b1})));
+            acc_imod_7_sva = readslicef_3_2_1((({1'b1 , (acc_imod_6_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_6_sva[1])) , (~ (acc_imod_6_sva[2]))})));
+            ACC1_acc_224_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_4_itm)
+                + conv_s2s_10_11(regs_regs_slc_regs_regs_2_5_itm)) + conv_s2u_10_12(regs_regs_slc_regs_regs_2_3_itm);
+            ACC1_acc_214_psp_1_sva = readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((({2'b10
+                , (~ (ACC1_acc_224_psp_sva[0])) , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[1])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[2])) , (~ (ACC1_acc_224_psp_sva[6]))}))))
+                , (~ (ACC1_acc_224_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[3])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[4])) , (ACC1_acc_224_psp_sva[5])}))))
+                , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_sva[11:10])) , (ACC1_acc_224_psp_sva[7])}))))
+                , (ACC1_acc_224_psp_sva[9])})));
+            ACC1_acc_222_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_214_psp_1_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_214_psp_1_sva[1])) , (ACC1_acc_214_psp_1_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_acc_214_psp_1_sva[3]));
+            acc_imod_10_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_222_psp_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_222_psp_sva[0]) , 1'b1})));
+            acc_imod_11_sva = readslicef_3_2_1((({1'b1 , (acc_imod_10_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_10_sva[1])) , (~ (acc_imod_10_sva[2]))})));
+            acc_20_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_10_itm)
+                + conv_s2s_10_11(regs_regs_slc_regs_regs_2_11_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_9_itm);
+            ACC1_acc_217_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                (acc_20_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_1_sva[1]))
+                , (acc_20_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_1_sva[0])
+                , (acc_20_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[3])) , (~ (acc_20_psp_1_sva[7]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[5])) , (acc_20_psp_1_sva[6])}))))
+                , (~ (acc_20_psp_1_sva[9]))}))));
+            ACC1_acc_223_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_1_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_1_sva[1])) , (ACC1_acc_217_psp_1_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_acc_217_psp_1_sva[3]));
+            acc_imod_18_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_223_psp_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_223_psp_sva[0]) , 1'b1})));
+            acc_imod_19_sva = readslicef_3_2_1((({1'b1 , (acc_imod_18_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_18_sva[1])) , (~ (acc_imod_18_sva[2]))})));
+            ACC1_acc_673_cse = conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11]));
+            ACC1_acc_699_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])) +
+                conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11]));
+            ACC1_mul_57_itm = conv_s2u_28_14(conv_u2s_2_14((conv_u2u_1_2(ACC1_acc_224_psp_sva[11])
+                + conv_u2u_1_2(ACC1_acc_228_psp_sva[11])) + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[11]))
+                * 14'b11101000000001);
+            ACC1_acc_724_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]));
+            ACC1_acc_509_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]));
+            ACC1_acc_506_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11])) +
+                conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+            ACC1_acc_502_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[5])) + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+            ACC1_acc_489_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]));
+            ACC1_acc_516_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]));
+            ACC1_acc_562_ncse = conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(ACC1_acc_506_cse);
+            ACC1_acc_553_ncse = conv_u2u_3_4(ACC1_acc_489_cse) + conv_u2u_3_4(ACC1_acc_489_cse);
+            regs_regs_0_sva = regs_regs_0_sva_1;
+            ACC1_acc_659_itm_1 = conv_s2s_12_13(conv_s2s_11_12({(ACC1_1_acc_25_psp_sva[11])
+                , 2'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11])
+                , 1'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11])
+                , (ACC1_acc_224_psp_sva[0])}) + conv_u2s_11_12({conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[9])
+                + conv_u2u_1_2(acc_psp_1_sva[9])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[8]))
+                + conv_u2u_1_3(ACC1_acc_228_psp_sva[8])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[8]))
+                + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[8])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[9]))
+                + conv_u2u_1_4(acc_psp_2_sva[9])) * 8'b10101) , (ACC1_acc_227_psp_sva[4])
+                , (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_s2s_12_13(conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_psp_2_sva[10])
+                , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10]) , 1'b0
+                , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_psp_2_sva[9])
+                , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 ,
+                (signext_2_1(acc_psp_2_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_2_sva[7])
+                , 1'b0 , (acc_psp_2_sva[5]) , 1'b0 , (signext_2_1(acc_psp_2_sva[11]))})
+                + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~ (acc_imod_26_sva[2]))}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (acc_imod_26_sva[1])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))))))
+                + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+                , (acc_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_210_psp_2_sva[3])
+                , (acc_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_220_psp_1_sva[2:1]))
+                + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_2_sva[3]) , (acc_psp_2_sva[1])
+                , 1'b1}) + conv_s2s_3_5({(ACC1_acc_210_psp_2_sva[3]) , (acc_psp_2_sva[2])
+                , (ACC1_acc_210_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_2_sva[7])
+                , (acc_psp_2_sva[4]) , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_673_cse)))
+                + conv_u2s_7_8({(acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8]) ,
+                1'b0 , (acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+                , (signext_2_1(acc_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_2_sva[6])
+                , 1'b0 , (acc_psp_2_sva[6]) , 1'b0 , (acc_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_673_cse)
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , ACC1_1_and_3_cse_sva}))))))))))
+                + ({(acc_psp_2_sva[11]) , 2'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11])
+                , 1'b0 , (acc_psp_2_sva[11]) , (conv_u2u_1_3(acc_psp_2_sva[11]) +
+                conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])))})) + conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_20_psp_2_sva[10])
+                , 1'b0 , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10]) ,
+                1'b0 , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10])}) +
+                conv_u2u_8_10(({(acc_20_psp_2_sva[9]) , 1'b0 , (acc_20_psp_2_sva[9])
+                , 1'b0 , (acc_20_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_20_psp_2_sva[5]))})
+                + conv_u2u_7_8(conv_u2u_6_7({(acc_20_psp_2_sva[7]) , 1'b0 , (acc_20_psp_2_sva[5])
+                , 1'b0 , (signext_2_1(acc_20_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~((acc_imod_40_sva[1])
+                & (~ (acc_20_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~
+                (acc_imod_38_sva[2]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (acc_imod_38_sva[1])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (ACC1_acc_217_psp_2_sva[2])}))))))))))
+                + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+                , (acc_20_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_217_psp_2_sva[3])
+                , (acc_20_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_223_psp_1_sva[2:1]))
+                + (readslicef_5_4_1((conv_u2s_3_5({(acc_20_psp_2_sva[3]) , (acc_20_psp_2_sva[1])
+                , 1'b1}) + conv_s2s_3_5({(ACC1_acc_217_psp_2_sva[3]) , (acc_20_psp_2_sva[2])
+                , (ACC1_acc_217_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_20_psp_2_sva[7])
+                , (acc_20_psp_2_sva[4]) , (signext_2_1(acc_20_psp_2_sva[11]))}) +
+                conv_u2u_3_5(ACC1_acc_699_cse))) + conv_u2s_7_8({(acc_20_psp_2_sva[8])
+                , 1'b0 , (acc_20_psp_2_sva[8]) , 1'b0 , (acc_20_psp_2_sva[8]) , 1'b0
+                , (acc_20_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_20_psp_2_sva[11])
+                , (signext_2_1(acc_20_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_20_psp_2_sva[6])
+                , 1'b0 , (acc_20_psp_2_sva[6]) , 1'b0 , (acc_20_psp_2_sva[6])}) +
+                conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_699_cse) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[9]) , ((acc_20_psp_2_sva[11])
+                & (~ (acc_imod_40_sva[1])) & (acc_imod_40_sva[0]))})))))))))) + ({(acc_20_psp_2_sva[11])
+                , 2'b0 , (acc_20_psp_2_sva[11]) , 1'b0 , (acc_20_psp_2_sva[11]) ,
+                1'b0 , (acc_20_psp_2_sva[11]) , (conv_u2u_1_3(acc_20_psp_2_sva[11])
+                + conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])))})));
+            ACC1_acc_658_itm_1 = conv_s2s_12_13(conv_s2s_10_12(conv_s2s_9_10(conv_u2s_7_9(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(ACC1_acc_224_psp_1_sva[6])
+                , (ACC1_acc_228_psp_sva[3]) , (signext_2_1(ACC1_acc_224_psp_sva[11]))})
+                + conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[5]) , (ACC1_acc_226_psp_sva[3])
+                , (signext_2_1(ACC1_acc_228_psp_sva[11]))})) + conv_u2u_5_6(conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[7])
+                , (ACC1_acc_224_psp_1_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})
+                + conv_u2u_4_5({(acc_20_psp_1_sva[4]) , (ACC1_1_acc_25_psp_sva[4])
+                , (signext_2_1(ACC1_acc_228_psp_sva[11]))}))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(~
+                (ACC1_acc_217_psp_1_sva[3])) , (~ (ACC1_acc_210_psp_1_sva[3])) ,
+                1'b1 , (~ (acc_imod_42_sva[2]))}) + conv_u2u_4_5({(acc_psp_2_sva[5])
+                , (acc_20_psp_1_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))}))
+                + conv_s2u_5_6(conv_u2s_3_5(readslicef_4_3_1((conv_u2u_3_4({((acc_20_psp_1_sva[11])
+                & (~ (acc_imod_19_sva[1])) & (acc_imod_19_sva[0])) , (ACC1_acc_224_psp_1_sva[1])
+                , 1'b1}) + conv_u2u_3_4({(acc_psp_2_sva[3]) , (ACC1_acc_224_psp_1_sva[2])
+                , (ACC1_1_acc_25_psp_sva[2])})))) + conv_s2s_3_5({(ACC1_acc_223_psp_sva[2:1])
+                , (ACC1_acc_224_psp_1_sva[3])})))) + conv_s2s_7_9(conv_s2s_6_7(conv_s2s_4_6(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , 1'b1})) + conv_s2s_3_5({(ACC1_acc_220_psp_1_sva[2:1]) , (acc_imod_31_sva[1])}))))
+                + conv_u2s_4_6({(ACC1_acc_224_psp_1_sva[4]) , (ACC1_acc_224_psp_sva[3])
+                , (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_s2s_6_7(conv_u2s_4_6({(acc_psp_2_sva[7])
+                , (acc_psp_2_sva[4]) , (signext_2_1(ACC1_acc_228_psp_sva[6]))}) +
+                conv_s2s_3_6(conv_s2s_2_3(ACC1_acc_220_psp_sva[2:1]) + conv_s2s_2_3(ACC1_acc_222_psp_sva[2:1])))))
+                + conv_u2s_9_10({(acc_20_psp_1_sva[9]) , 1'b0 , (acc_20_psp_1_sva[9])
+                , 1'b0 , (acc_20_psp_1_sva[9]) , (ACC1_acc_228_psp_sva[4]) , 1'b0
+                , (signext_2_1(ACC1_acc_224_psp_sva[6]))})) + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_4_10(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[8])
+                + conv_u2u_1_2(acc_psp_1_sva[8])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[7]))
+                + conv_u2u_1_3(ACC1_acc_228_psp_sva[7])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[7]))
+                + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[7])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[8]))
+                + conv_u2u_1_4(acc_psp_2_sva[8])) * 10'b1010101))) + conv_u2s_12_14(conv_u2s_24_13(conv_u2u_4_12(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[10])
+                + conv_u2u_1_2(acc_psp_1_sva[10])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[9]))
+                + conv_u2u_1_3(ACC1_acc_228_psp_sva[9])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[9]))
+                + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[9])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[10]))
+                + conv_u2u_1_4(acc_psp_2_sva[10])) * 12'b101010101));
+            ACC1_acc_661_itm_1 = conv_s2s_13_14(conv_s2s_12_13({(ACC1_acc_226_psp_sva[11])
+                , 1'b0 , (ACC1_acc_226_psp_sva[11]) , 7'b0 , (ACC1_acc_226_psp_sva[11])
+                , (acc_psp_1_sva[2])}) + conv_u2s_12_13({conv_u2u_18_9(conv_u2u_3_9(conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_224_psp_sva[10])
+                + conv_u2u_1_2(ACC1_acc_228_psp_sva[10])) + conv_u2u_1_2(ACC1_acc_226_psp_sva[10]))
+                + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[10])) * 9'b1010101) , (acc_psp_1_sva[4])
+                , (signext_2_1(ACC1_acc_224_psp_sva[4]))})) + conv_s2s_13_14(conv_s2s_26_13(conv_u2s_2_13((conv_u2u_1_2(ACC1_acc_227_psp_sva[11])
+                + conv_u2u_1_2(acc_psp_1_sva[11])) + conv_u2u_1_2(acc_psp_2_sva[11]))
+                * 13'b1110010101001));
+            ACC1_mul_57_itm_2 = ACC1_mul_57_itm[1:0];
+            ACC1_mul_57_itm_1_sg2 = ACC1_mul_57_itm[13:9];
+            slc_acc_20_psp_1_93_itm_1 = acc_20_psp_1_sva[11];
+            slc_acc_20_psp_1_94_itm_1 = acc_20_psp_1_sva[11];
+            slc_acc_20_psp_1_95_itm_1 = acc_20_psp_1_sva[11];
+            slc_acc_20_psp_1_81_itm_1 = acc_20_psp_1_sva[11];
+            ACC1_slc_ACC1_acc_228_psp_55_itm_1 = ACC1_acc_228_psp_sva[6];
+            ACC1_3_slc_acc_10_psp_62_itm_1 = ACC1_acc_224_psp_sva[8];
+            ACC1_acc_652_itm_1 = conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (ACC1_acc_214_psp_2_sva[3])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (ACC1_acc_214_psp_2_sva[2])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (ACC1_acc_214_psp_2_sva[1])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (acc_imod_6_sva[1])}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (ACC1_3_acc_212_psp_sva[3])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[5])
+                , (ACC1_3_acc_212_psp_sva[2])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (ACC1_3_acc_212_psp_sva[1])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[9]) ,
+                ((ACC1_acc_226_psp_sva[11]) & (~ (acc_imod_45_sva[1])) & (acc_imod_45_sva[0]))}))))))))
+                + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , (~((acc_imod_45_sva[1]) & (~ (ACC1_acc_226_psp_sva[11]))))})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+                , (acc_imod_43_sva[1])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+                , (ACC1_2_acc_208_psp_sva[3])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[5])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_2_acc_208_psp_sva[2])})))))))
+                + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , (ACC1_2_acc_208_psp_sva[1])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , ((ACC1_acc_228_psp_sva[11]) & (~ (acc_imod_33_sva[1])) & (acc_imod_33_sva[0]))}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , (~((acc_imod_33_sva[1]) & (~ (ACC1_acc_228_psp_sva[11]))))})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_2_acc_212_psp_sva[3])})))))))))
+                + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_2_acc_212_psp_sva[2])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , (ACC1_2_acc_212_psp_sva[1])}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ((ACC1_acc_224_psp_sva[11])
+                & (~ (acc_imod_11_sva[1])) & (acc_imod_11_sva[0]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~((acc_imod_11_sva[1])
+                & (~ (ACC1_acc_224_psp_sva[11]))))}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (acc_imod_10_sva[1])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_214_psp_1_sva[3])}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[5]) , (ACC1_acc_214_psp_1_sva[2])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_214_psp_1_sva[1])}))))))))
+                + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_227_psp_sva[3])
+                , (ACC1_acc_227_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(acc_psp_1_sva[3])
+                , (ACC1_acc_227_psp_sva[2]) , ((acc_psp_1_sva[11]) & (~ (acc_imod_3_sva[1]))
+                & (acc_imod_3_sva[0]))})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_224_psp_sva[2])
+                , (ACC1_acc_227_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[2])
+                , (ACC1_acc_227_psp_sva[4]) , (~((acc_imod_3_sva[1]) & (~ (acc_psp_1_sva[11]))))})))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_226_psp_sva[2])
+                , (acc_psp_1_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_224_psp_1_sva[2])
+                , (acc_psp_1_sva[3]) , (acc_imod_2_sva[1])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_1_acc_25_psp_sva[3])
+                , (acc_psp_1_sva[4]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[1])
+                , (ACC1_acc_224_psp_sva[1]) , (ACC1_acc_210_psp_1_sva[3])}))))))
+                + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[2])
+                , (ACC1_acc_224_psp_sva[2]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[3])
+                , (ACC1_acc_224_psp_sva[3]) , (ACC1_acc_210_psp_1_sva[2])})))) +
+                conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[4])
+                , (ACC1_acc_228_psp_sva[0]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[1])
+                , (ACC1_acc_226_psp_sva[0]) , (ACC1_acc_210_psp_1_sva[1])}))))) +
+                conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[2])
+                , (ACC1_acc_226_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[3])
+                , (ACC1_acc_226_psp_sva[2]) , (ACC1_1_acc_25_psp_sva[4])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_imod_18_sva[1])
+                , (ACC1_acc_226_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(~((acc_imod_19_sva[1])
+                & (~ (acc_20_psp_1_sva[11])))) , (ACC1_acc_224_psp_1_sva[0]) , (ACC1_1_acc_25_psp_sva[3])})))))))))
+                + conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_3_4({(acc_20_psp_1_sva[6])
+                , 1'b0 , (acc_20_psp_1_sva[6])}) + conv_u2u_3_4({(acc_psp_1_sva[7])
+                , (acc_20_psp_1_sva[5]) , (ACC1_acc_226_psp_sva[4])})) , (conv_u2u_2_3({(acc_20_psp_1_sva[6])
+                , (ACC1_acc_228_psp_sva[1])}) + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[10])))})
+                + conv_u2u_7_8({(conv_u2u_3_4({(ACC1_acc_224_psp_sva[6]) , (acc_20_psp_1_sva[7])
+                , (ACC1_acc_226_psp_sva[6])}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[6])
+                , 1'b0 , (ACC1_acc_227_psp_sva[5])})) , ACC1_acc_724_cse}))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_1_2(ACC1_acc_226_psp_sva[6])
+                + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[6])) , (conv_u2u_1_2(ACC1_acc_227_psp_sva[7])
+                + conv_u2u_1_2(acc_psp_1_sva[5])) , ACC1_acc_724_cse}) + conv_u2u_7_8({(conv_u2u_1_2(ACC1_1_acc_25_psp_sva[7])
+                + conv_u2u_1_2(acc_psp_2_sva[7])) , (conv_u2u_1_2(acc_psp_1_sva[7])
+                + conv_u2u_1_2(ACC1_acc_224_psp_sva[4])) , ACC1_acc_724_cse})) +
+                conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_227_psp_sva[11])
+                , (signext_2_1(ACC1_acc_227_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_1_sva[11])
+                , (signext_2_1(acc_psp_1_sva[11]))}))))) + conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_sva[11])
+                , (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_228_psp_sva[11])
+                , (signext_2_1(ACC1_acc_228_psp_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(acc_20_psp_1_sva[11])
+                , 1'b0 , (signext_2_1(acc_20_psp_1_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_20_psp_1_sva[11])
+                , (signext_2_1(acc_20_psp_1_sva[11]))})))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_acc_226_psp_sva[11])
+                , 1'b0 , (signext_2_1(ACC1_acc_226_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_1_sva[11])
+                , (signext_2_1(ACC1_acc_224_psp_1_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b0 , (signext_2_1(ACC1_1_acc_25_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+                , (signext_2_1(acc_psp_2_sva[11]))})))));
+            ACC1_acc_655_itm_1 = conv_s2s_11_12(conv_u2s_10_11({(acc_20_psp_1_sva[10])
+                , 1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10]) ,
+                1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10]) , (ACC1_acc_228_psp_sva[3])})
+                + conv_s2s_9_11(conv_s2s_8_9(({7'b1011011 , (ACC1_1_acc_25_psp_sva[1])})
+                + conv_u2s_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse)
+                + conv_u2u_3_4(ACC1_acc_509_cse)) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[5]))) + conv_u2u_3_4(ACC1_acc_506_cse)))
+                + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+                + conv_u2u_3_4(ACC1_acc_502_cse)))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+                + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))
+                + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[7]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[9]))
+                + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))))) + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+                + conv_u2u_4_5(ACC1_acc_562_ncse))))) + conv_u2s_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_502_cse)
+                + conv_u2u_3_4(ACC1_acc_506_cse)) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+                + conv_u2u_3_4(ACC1_acc_489_cse))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[6]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[8]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[10]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_u2u_4_5(ACC1_acc_553_ncse)))
+                + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_553_ncse) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_489_cse)))
+                + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[9]) , ACC1_1_and_3_cse_sva}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (acc_imod_26_sva[1])})))))))))
+                + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[3])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[1])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[9]) , (acc_psp_2_sva[4])})))))))
+                + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (acc_psp_2_sva[3])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , (acc_psp_2_sva[1])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , ((ACC1_acc_227_psp_sva[11]) & (~ (acc_imod_7_sva[1])) & (acc_imod_7_sva[0]))})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[6])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[8])
+                , (~((acc_imod_7_sva[1]) & (~ (ACC1_acc_227_psp_sva[11]))))}))))))))
+                + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[10])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , ((ACC1_1_acc_25_psp_sva[11]) & (~ (acc_imod_44_sva[1])) & (acc_imod_44_sva[0]))})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , (~((acc_imod_44_sva[1]) & (~ (ACC1_1_acc_25_psp_sva[11]))))}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , (acc_imod_42_sva[1])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , (ACC1_1_acc_208_psp_sva[3])}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[4])
+                , (ACC1_1_acc_208_psp_sva[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , (ACC1_1_acc_208_psp_sva[1])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (~((acc_imod_36_sva[1]) & (~ (ACC1_acc_224_psp_1_sva[11]))))})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[9])
+                , (acc_imod_34_sva[1])})))))))))))) + conv_u2s_10_12(conv_u2u_8_10((conv_u2u_7_8({(acc_20_psp_1_sva[7])
+                , (ACC1_acc_227_psp_sva[7]) , 1'b0 , (ACC1_acc_224_psp_sva[6]) ,
+                1'b0 , (signext_2_1(ACC1_acc_224_psp_sva[11]))}) + conv_u2u_6_8(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[10]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+                + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_516_cse) + conv_u2u_3_4(ACC1_acc_516_cse)))
+                + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+                + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))
+                + conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))))))) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4({(~
+                (ACC1_acc_214_psp_1_sva[3])) , (~ (acc_imod_18_sva[2])) , (~ (acc_imod_26_sva[2]))})
+                + conv_u2u_3_4({(~ (ACC1_2_acc_212_psp_sva[3])) , 1'b1 , (~ (acc_imod_2_sva[2]))}))
+                + conv_u2u_4_5({(conv_u2u_1_2(~ (ACC1_2_acc_208_psp_sva[3])) + conv_u2u_1_2(~
+                (ACC1_3_acc_212_psp_sva[3])) + 2'b1) , (({1'b1 , (~ (acc_imod_10_sva[2]))})
+                + ({1'b1 , (~ (acc_imod_31_sva[2]))}))})) + conv_u2u_5_6(conv_u2u_4_5({(conv_u2u_1_2(~
+                (ACC1_acc_214_psp_2_sva[3])) + conv_u2u_1_2(~ (ACC1_1_acc_208_psp_sva[3]))
+                + 2'b1) , (({1'b1 , (~ (acc_imod_43_sva[2]))}) + ({1'b1 , (~ (acc_imod_6_sva[2]))}))})
+                + conv_u2u_4_5(conv_u2u_3_4({(~ (ACC1_acc_210_psp_2_sva[3])) , 1'b1
+                , (~ (acc_imod_34_sva[2]))}) + conv_s2u_2_4(ACC1_acc_221_psp_sva[2:1]))))
+                + conv_s2u_6_7(conv_s2s_5_6(conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_221_psp_2_sva[2:1])
+                + conv_u2s_2_4(signext_2_1(ACC1_acc_228_psp_sva[8]))) + conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_219_psp_2_sva[2:1])
+                + conv_u2s_2_4(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_s2s_5_6(conv_s2s_4_5(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_s2s_3_5({(ACC1_acc_222_psp_1_sva[2:1]) , (acc_psp_2_sva[2])}))))
+                + conv_s2s_4_5(readslicef_5_4_1((conv_s2s_3_5({(ACC1_acc_219_psp_1_sva[2:1])
+                , 1'b1}) + conv_u2s_3_5(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , ((ACC1_acc_224_psp_1_sva[11]) & (~ (acc_imod_36_sva[1])) & (acc_imod_36_sva[0]))})))))))))
+                + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[6])
+                + conv_u2u_1_2(acc_psp_1_sva[6])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[5]))
+                + conv_u2u_1_3(ACC1_acc_228_psp_sva[5])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[5]))
+                + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[5])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[6]))
+                + conv_u2u_1_4(acc_psp_2_sva[6])) * 8'b10101)) + conv_u2u_8_9({(acc_20_psp_1_sva[8])
+                , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0
+                , (acc_20_psp_1_sva[8]) , (ACC1_acc_228_psp_sva[2])})));
+            main_stage_0_2 = 1'b1;
+          end
+        end
+      end
+    end
+    ACC1_mul_57_itm_2 = 2'b0;
+    ACC1_mul_57_itm_1_sg2 = 5'b0;
+    ACC1_acc_553_ncse = 4'b0;
+    ACC1_acc_562_ncse = 4'b0;
+    ACC1_acc_516_cse = 3'b0;
+    ACC1_acc_489_cse = 3'b0;
+    ACC1_acc_502_cse = 3'b0;
+    ACC1_acc_506_cse = 3'b0;
+    ACC1_acc_509_cse = 3'b0;
+    ACC1_acc_724_cse = 3'b0;
+    ACC1_acc_699_cse = 3'b0;
+    ACC1_acc_673_cse = 3'b0;
+    main_stage_0_2 = 1'b0;
+    ACC1_acc_655_itm_1 = 12'b0;
+    ACC1_acc_652_itm_1 = 11'b0;
+    ACC1_3_slc_acc_10_psp_62_itm_1 = 1'b0;
+    ACC1_slc_ACC1_acc_228_psp_55_itm_1 = 1'b0;
+    slc_acc_20_psp_1_81_itm_1 = 1'b0;
+    slc_acc_20_psp_1_95_itm_1 = 1'b0;
+    slc_acc_20_psp_1_94_itm_1 = 1'b0;
+    slc_acc_20_psp_1_93_itm_1 = 1'b0;
+    ACC1_mul_57_itm = 14'b0;
+    ACC1_acc_661_itm_1 = 14'b0;
+    ACC1_acc_658_itm_1 = 13'b0;
+    ACC1_acc_659_itm_1 = 13'b0;
+    regs_regs_slc_regs_regs_2_9_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_11_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_10_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_3_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_5_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_4_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_2_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_1_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_itm = 10'b0;
+    FRAME_acc_2_psp_sva = 12'b0;
+    acc_imod_24_sva = 6'b0;
+    ACC1_slc_psp_sva = 14'b0;
+    acc_imod_19_sva = 2'b0;
+    acc_imod_18_sva = 3'b0;
+    ACC1_acc_223_psp_sva = 3'b0;
+    ACC1_acc_217_psp_1_sva = 4'b0;
+    acc_20_psp_1_sva = 12'b0;
+    acc_imod_11_sva = 2'b0;
+    acc_imod_10_sva = 3'b0;
+    ACC1_acc_222_psp_sva = 3'b0;
+    ACC1_acc_214_psp_1_sva = 4'b0;
+    ACC1_acc_224_psp_sva = 12'b0;
+    acc_imod_7_sva = 2'b0;
+    acc_imod_6_sva = 3'b0;
+    ACC1_acc_221_psp_sva = 3'b0;
+    ACC1_3_acc_212_psp_sva = 4'b0;
+    ACC1_acc_227_psp_sva = 12'b0;
+    acc_imod_3_sva = 2'b0;
+    acc_imod_2_sva = 3'b0;
+    ACC1_acc_220_psp_sva = 3'b0;
+    ACC1_acc_210_psp_1_sva = 4'b0;
+    acc_psp_1_sva = 12'b0;
+    acc_imod_45_sva = 2'b0;
+    acc_imod_43_sva = 3'b0;
+    ACC1_acc_219_psp_2_sva = 3'b0;
+    ACC1_2_acc_208_psp_sva = 4'b0;
+    ACC1_acc_226_psp_sva = 12'b0;
+    acc_imod_33_sva = 2'b0;
+    acc_imod_31_sva = 3'b0;
+    ACC1_acc_221_psp_2_sva = 3'b0;
+    ACC1_2_acc_212_psp_sva = 4'b0;
+    ACC1_acc_228_psp_sva = 12'b0;
+    acc_imod_44_sva = 2'b0;
+    acc_imod_42_sva = 3'b0;
+    ACC1_acc_219_psp_1_sva = 3'b0;
+    ACC1_1_acc_208_psp_sva = 4'b0;
+    ACC1_1_acc_25_psp_sva = 12'b0;
+    acc_imod_40_sva = 2'b0;
+    acc_imod_38_sva = 3'b0;
+    ACC1_acc_223_psp_1_sva = 3'b0;
+    ACC1_acc_217_psp_2_sva = 4'b0;
+    acc_20_psp_2_sva = 12'b0;
+    acc_imod_36_sva = 2'b0;
+    acc_imod_34_sva = 3'b0;
+    ACC1_acc_222_psp_1_sva = 3'b0;
+    ACC1_acc_214_psp_2_sva = 4'b0;
+    ACC1_acc_224_psp_1_sva = 12'b0;
+    ACC1_1_and_3_cse_sva = 1'b0;
+    ACC1_1_nand_1_cse_sva = 1'b0;
+    acc_imod_32_sva = 2'b0;
+    acc_imod_26_sva = 3'b0;
+    ACC1_acc_220_psp_1_sva = 3'b0;
+    ACC1_acc_210_psp_2_sva = 4'b0;
+    acc_psp_2_sva = 12'b0;
+    regs_regs_0_sva_1 = 90'b0;
+    regs_regs_0_sva = 90'b0;
+    regs_regs_1_sva = 90'b0;
+    vout_rsc_mgc_out_stdreg_d <= 30'b0;
+  end
+
+
+  function [13:0] readslicef_15_14_1;
+    input [14:0] vector;
+    reg [14:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_15_14_1 = tmp[13:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_2;
+    input [1:0] vector;
+  begin
+    signext_3_2= {{1{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_3;
+    input [2:0] vector;
+  begin
+    signext_7_3= {{4{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_4;
+    input [3:0] vector;
+  begin
+    signext_7_4= {{3{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [14:0] conv_s2s_14_15 ;
+    input signed [13:0]  vector ;
+  begin
+    conv_s2s_14_15 = {vector[13], vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_13_14 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_14 = {vector[12], vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_7_10 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_10 = {{3{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_s2u_28_14 ;
+    input signed [27:0]  vector ;
+  begin
+    conv_s2u_28_14 = vector[13:0];
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_2_14 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_14 = {{12{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_4_8 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_8 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_1_4 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_4 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_6_8 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_8 = {{2{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_9_10 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_10 = {vector[8], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_s2u_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2u_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_3_6 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_6 = {{3{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_4_10 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_10 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_24_13 ;
+    input [23:0]  vector ;
+  begin
+    conv_u2s_24_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_4_12 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_12 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_26_13 ;
+    input signed [25:0]  vector ;
+  begin
+    conv_s2s_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_9_11 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_11 = {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_8_9 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_9 = {vector[7], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_s2u_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2u_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_s2u_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2u_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v11/cycle_mgc_ioport.v b/Sobel/sobel.v11/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v11/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v11/cycle_mgc_ioport_v2001.v b/Sobel/sobel.v11/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v11/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v11/cycle_set.tcl b/Sobel/sobel.v11/cycle_set.tcl
new file mode 100644
index 0000000..1afb9a0
--- /dev/null
+++ b/Sobel/sobel.v11/cycle_set.tcl
@@ -0,0 +1,489 @@
+
+# Loop constraints
+directive set /sobel/core/core:rlp CSTEPS_FROM {{. == 0}}
+directive set /sobel/core/core:rlp/main CSTEPS_FROM {{. == 3} {.. == 0}}
+
+# IO operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:io_read(vin:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:io_write(vout:rsc.d) CSTEPS_FROM {{.. == 2}}
+
+# Real operation constraints
+directive set /sobel/core/core:rlp/main/ACC1:acc#331 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#330 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#334 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#336 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#333 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#332 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#335 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#210 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#337 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#220 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#338 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#339 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#341 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#340 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#224 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#343 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#345 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#342 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#344 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#346 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#347 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#225 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#348 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#349 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#351 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#350 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#20 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#354 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#356 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#353 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#352 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#355 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#217 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#357 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#223 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#358 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#359 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#360 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#363 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#365 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#362 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#361 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#364 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#208 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#366 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#219 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#367 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#368 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#370 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#369 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#228 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#372 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#374 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#371 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#373 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#375 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#376 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-2:acc#221 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#377 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#378 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#379 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#226 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#381 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#383 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#380 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#382 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#384 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#385 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-2:acc#219 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#386 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#387 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#388 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#391 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#393 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#390 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#389 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#392 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#210 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#394 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#220 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#395 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#396 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#398 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#397 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#227 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#401 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#403 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#400 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#399 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#402 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#212 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#404 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#221 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#405 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#406 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#407 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#224 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#409 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#411 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#408 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#410 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#412 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#413 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#225 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#414 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#415 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#416 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#20 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#419 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#421 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#418 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#417 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#420 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#217 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#422 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#223 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#423 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#424 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#326 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#325 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#324 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#323 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#322 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#321 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#320 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#58 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#654 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#670 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#669 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#676 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#668 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#667 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#675 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#680 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#683 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#686 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#688 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#665 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#674 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#666 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#679 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#673 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#678 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#682 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#685 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#672 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#671 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#677 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#681 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#684 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#687 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#690 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#689 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#696 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#695 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#702 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#694 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#693 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#701 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#706 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#709 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#712 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#714 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#691 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#700 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#692 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#705 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#699 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#704 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#708 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#711 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#698 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#697 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#703 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#707 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#710 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#713 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#716 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#715 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#27 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#653 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#659 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#572 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#571 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#601 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#570 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#425 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#524 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#600 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#620 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#443 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#573 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#519 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#569 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#619 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#635 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#646 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#308 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#307 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#306 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#305 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#304 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#303 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#302 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#54 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#651 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#315 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#314 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#313 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#312 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#311 CSTEPS_FROM {{.. == 1}}
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+directive set /sobel/core/core:rlp/main/ACC1:acc#299 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#298 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#297 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#296 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#295 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#639 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#647 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#655 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#660 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#663 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#6 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#5 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#8 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#7 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#9 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/acc#30 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#1 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#16 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#10 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#11 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#12 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#13 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#14 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#15 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#2 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc CSTEPS_FROM {{.. == 1}}
diff --git a/Sobel/sobel.v11/directives.tcl b/Sobel/sobel.v11/directives.tcl
new file mode 100644
index 0000000..504c4bb
--- /dev/null
+++ b/Sobel/sobel.v11/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
+go extract
diff --git a/Sobel/sobel.v11/messages.txt b/Sobel/sobel.v11/messages.txt
new file mode 100644
index 0000000..ba788fa
--- /dev/null
+++ b/Sobel/sobel.v11/messages.txt
@@ -0,0 +1,243 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.17 seconds, memory usage 353576kB, peak memory usage 457688kB (SOL-9)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.cpp(121): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+
+# Messages from "go compile"
+
+Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'sobel' specified by directive (CIN-52)
+Synthesizing routine 'sobel' (CIN-13)
+Inlining routine 'sobel' (CIN-14)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Optimizing block '/sobel' ... (CIN-4)
+Inout port 'vin' is only used as an input. (OPT-10)
+Inout port 'vout' is only used as an output. (OPT-11)
+Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+Detected constant initialization of array 'inte', optimizing loop 'RESET' (LOOP-12)
+Design 'sobel' was read (SOL-1)
+Optimizing partition '/sobel': (Total ops = 1693, Real ops = 337, Vars = 368) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1693, Real ops = 337, Vars = 366) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1658, Real ops = 327, Vars = 372) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1658, Real ops = 327, Vars = 374) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1658, Real ops = 327, Vars = 374) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1658, Real ops = 327, Vars = 372) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1602, Real ops = 326, Vars = 359) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1577, Real ops = 326, Vars = 358) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1577, Real ops = 326, Vars = 358) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1577, Real ops = 326, Vars = 360) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1577, Real ops = 326, Vars = 360) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1556, Real ops = 324, Vars = 402) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 57) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1177, Real ops = 184, Vars = 60) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 848, Real ops = 155, Vars = 50) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 846, Real ops = 155, Vars = 50) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 846, Real ops = 155, Vars = 52) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 842, Real ops = 155, Vars = 54) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 840, Real ops = 155, Vars = 50) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 840, Real ops = 155, Vars = 52) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 840, Real ops = 155, Vars = 50) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 840, Real ops = 155, Vars = 52) (SOL-10)
+Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'sobel.v11' (SOL-8)
+Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+Loop '/sobel/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/sobel/core': (Total ops = 2387, Real ops = 428, Vars = 50) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1805, Real ops = 303, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1797, Real ops = 303, Vars = 73) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1797, Real ops = 303, Vars = 73) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1701, Real ops = 260, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1548, Real ops = 285, Vars = 61) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1519, Real ops = 295, Vars = 59) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1519, Real ops = 295, Vars = 64) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 60) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1516, Real ops = 295, Vars = 68) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1516, Real ops = 295, Vars = 63) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1489, Real ops = 300, Vars = 59) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1489, Real ops = 300, Vars = 64) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1489, Real ops = 300, Vars = 59) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1489, Real ops = 300, Vars = 64) (SOL-10)
+Design 'sobel' contains '676' real operations. (SOL-11)
+Optimizing partition '/sobel/core': (Total ops = 1492, Real ops = 300, Vars = 60) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1926, Real ops = 304, Vars = 311) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1496, Real ops = 302, Vars = 63) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1495, Real ops = 302, Vars = 62) (SOL-10)
+Completed transformation 'architect' on solution 'sobel.v11': elapsed time 21.20 seconds, memory usage 336332kB, peak memory usage 457688kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'sobel.v11' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 307201, Area (Datapath, Register, Total) = 5750.29, 0.00, 5750.29 (CRAAS-11)
+Optimized LOOP 'main': Latency = 307201, Area (Datapath, Register, Total) = 5558.68, 0.00, 5558.68 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 307201, Area (Datapath, Register, Total) = 5558.68, 0.00, 5558.68 (CRAAS-12)
+Completed transformation 'allocate' on solution 'sobel.v11': elapsed time 15.13 seconds, memory usage 338928kB, peak memory usage 457688kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'sobel.v11' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 2382, Real ops = 677, Vars = 121) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2372, Real ops = 676, Vars = 113) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 2367, Real ops = 676, Vars = 108) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 2174, Real ops = 648, Vars = 96) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 2158, Real ops = 648, Vars = 91) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2172, Real ops = 648, Vars = 103) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2163, Real ops = 648, Vars = 96) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 2155, Real ops = 648, Vars = 93) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 2155, Real ops = 648, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2169, Real ops = 648, Vars = 104) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2160, Real ops = 648, Vars = 97) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 2155, Real ops = 648, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2169, Real ops = 648, Vars = 104) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2160, Real ops = 648, Vars = 97) (SOL-10)
+Completed transformation 'schedule' on solution 'sobel.v11': elapsed time 7.44 seconds, memory usage 363120kB, peak memory usage 457688kB (SOL-9)
+Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'sobel.v11' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 2428, Real ops = 663, Vars = 1568) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2419, Real ops = 663, Vars = 1561) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 3946, Real ops = 670, Vars = 100) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 3937, Real ops = 670, Vars = 93) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+Completed transformation 'dpfsm' on solution 'sobel.v11': elapsed time 3.82 seconds, memory usage 364816kB, peak memory usage 457688kB (SOL-9)
+
+# Messages from "go extract"
+
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'sobel.v11' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2151, Real ops = 668, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2142, Real ops = 668, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2151, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2142, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2151, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2142, Real ops = 668, Vars = 92) (SOL-10)
+Completed transformation 'extract' on solution 'sobel.v11': elapsed time 17.32 seconds, memory usage 368816kB, peak memory usage 457688kB (SOL-9)
diff --git a/Sobel/sobel.v11/reg_sharing.tcl b/Sobel/sobel.v11/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v11/reg_sharing.tcl
diff --git a/Sobel/sobel.v11/res_sharing.tcl b/Sobel/sobel.v11/res_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v11/res_sharing.tcl
diff --git a/Sobel/sobel.v11/rtl.rpt b/Sobel/sobel.v11/rtl.rpt
new file mode 100644
index 0000000..cbbd632
--- /dev/null
+++ b/Sobel/sobel.v11/rtl.rpt
@@ -0,0 +1,1144 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 16:15:57 +0000 2016                      
+
+Solution Settings: sobel.v11
+  Current state: extract
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       677  307201     307200            0  1          
+    Design Total:                     677  307201     307200            0  0          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(1,0,1,0,2)                           2.319                       0.000      2.319 0.506          7          11 
+    mgc_add(10,0,10,0,11)                       11.241                       0.000     11.241 1.301          3           1 
+    mgc_add(10,0,10,1,12)                       11.000                       0.000     11.000 0.976          4           4 
+    mgc_add(10,1,10,1,11)                       11.000                       0.000     11.000 1.139         15          15 
+    mgc_add(11,0,11,1,12)                       12.000                       0.000     12.000 1.206          2           2 
+    mgc_add(11,1,11,1,12)                       12.000                       0.000     12.000 1.206         14          14 
+    mgc_add(12,0,12,1,13)                       13.000                       0.000     13.000 1.272          2           2 
+    mgc_add(12,1,12,1,13)                       13.000                       0.000     13.000 1.272          4           4 
+    mgc_add(13,1,13,1,14)                       14.000                       0.000     14.000 1.337          2           2 
+    mgc_add(14,1,14,1,15)                       15.000                       0.000     15.000 1.401          2           2 
+    mgc_add(15,0,14,1,15)                       16.000                       0.000     16.000 1.628          1           1 
+    mgc_add(19,0,2,1,19)                        20.000                       0.000     20.000 1.908          1           0 
+    mgc_add(2,0,1,0,3)                           3.315                       0.000      3.315 0.658          0           2 
+    mgc_add(2,0,2,0,2)                           3.311                       0.000      3.311 0.653          0           2 
+    mgc_add(2,0,2,0,3)                           3.311                       0.000      3.311 0.653         71          50 
+    mgc_add(2,0,2,1,4)                           3.000                       0.000      3.000 0.328         30          30 
+    mgc_add(2,1,2,1,3)                           3.000                       0.000      3.000 0.490          1           1 
+    mgc_add(3,0,3,0,4)                           4.302                       0.000      4.302 0.761        123         119 
+    mgc_add(3,0,3,1,5)                           4.000                       0.000      4.000 0.436         49          49 
+    mgc_add(3,1,2,1,4)                           4.000                       0.000      4.000 0.602          4           4 
+    mgc_add(4,0,4,0,5)                           5.293                       0.000      5.293 0.854         30          30 
+    mgc_add(4,0,4,1,6)                           5.000                       0.000      5.000 0.529         15          15 
+    mgc_add(4,1,4,1,5)                           5.000                       0.000      5.000 0.691         10          10 
+    mgc_add(5,0,5,0,6)                           6.285                       0.000      6.285 0.938         13          13 
+    mgc_add(5,0,5,1,7)                           6.000                       0.000      6.000 0.613         12          12 
+    mgc_add(5,1,5,1,6)                           6.000                       0.000      6.000 0.775          1           1 
+    mgc_add(6,0,6,0,7)                           7.276                       0.000      7.276 1.016         10           6 
+    mgc_add(6,0,6,1,8)                           7.000                       0.000      7.000 0.691          5           5 
+    mgc_add(6,1,6,1,7)                           7.000                       0.000      7.000 0.854          1           1 
+    mgc_add(7,0,7,0,8)                           8.267                       0.000      8.267 1.091          9           9 
+    mgc_add(7,0,7,1,9)                           8.000                       0.000      8.000 0.766          6           6 
+    mgc_add(8,0,8,0,9)                           9.259                       0.000      9.259 1.163          5           5 
+    mgc_add(8,0,8,1,10)                          9.000                       0.000      9.000 0.838          8           7 
+    mgc_add(9,0,9,0,10)                         10.250                       0.000     10.250 1.233          2           2 
+    mgc_add(9,0,9,1,11)                         10.000                       0.000     10.000 0.908          5           5 
+    mgc_and(1,3)                                 1.054                       0.000      1.054 0.416          0          10 
+    mgc_and(19,2)                               13.867                       0.000     13.867 0.263          1           0 
+    mgc_mul(2,0,11,1,13)                       330.000                       2.000     10.000 3.129          2           2 
+    mgc_mul(2,0,12,1,14)                       330.000                       2.000     10.000 3.172          1           1 
+    mgc_mul(3,0,6,0,9)                         330.250                       2.000     10.250 2.846          1           1 
+    mgc_mul(4,0,5,0,8)                         330.250                       2.000     10.250 2.715          2           2 
+    mgc_mul(4,0,7,0,10)                        330.250                       2.000     10.250 2.850          2           2 
+    mgc_mul(4,0,9,0,12)                        330.250                       2.000     10.250 2.985          1           1 
+    mgc_mux(30,1,2)                             27.583                       0.000     27.583 0.369          0           1 
+    mgc_nand(1,2)                                0.730                       0.000      0.730 0.268          0          10 
+    mgc_not(1)                                   0.000                       0.000      0.000 0.000          0         141 
+    mgc_not(10)                                  0.000                       0.000      0.000 0.000          0          15 
+    mgc_not(2)                                   0.000                       0.000      0.000 0.000          0          14 
+    mgc_not(3)                                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_or(10,2)                                 7.298                       0.000      7.298 0.268          1           1 
+    mgc_or(6,2)                                  4.379                       0.000      4.379 0.268          1           1 
+    mgc_reg_pos(1,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_reg_pos(10,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           9 
+    mgc_reg_pos(11,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(12,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(13,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(14,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(2,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(30,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(5,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(90,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,90)                            0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(2,30)                         0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):            5445.451                      18.000   2565.000                              
+    
+  Area Scores
+                      Post-Scheduling   Post-DP & FSM Post-Assignment 
+    ----------------- --------------- --------------- ---------------
+    Total Area Score:   5558.7          5445.5          5445.5        
+    Total Reg:             0.0             0.0             0.0        
+                                                                      
+    DataPath:           5558.7 (100%)   5445.5 (100%)   5445.5 (100%) 
+      MUX:                 0.0            27.6   (1%)     27.6   (1%) 
+      FUNC:             5533.1 (100%)   5388.3  (99%)   5388.3  (99%) 
+      LOGIC:              25.5   (0%)     29.5   (1%)     29.5   (1%) 
+      BUFFER:              0.0             0.0             0.0        
+      MEM:                 0.0             0.0             0.0        
+      ROM:                 0.0             0.0             0.0        
+      REG:                 0.0             0.0             0.0        
+                                                                      
+    
+    FSM:                   0.0             0.0             0.0        
+      FSM-REG:             0.0             0.0             0.0        
+      FSM-COMB:            0.0             0.0             0.0        
+                                                                      
+    
+  Register-to-Variable Mappings
+    Register                            Size(bits) Gated Register CG Opt Done Variables                                             
+    ----------------------------------- ---------- -------------- ----------- -----------------------------------------------------
+    reg(regs.regs(0).sva).cse                   90         Y                  reg(regs.regs(0).sva).cse                             
+    vout:rsc:mgc_out_stdreg.d                   30         Y                  vout:rsc:mgc_out_stdreg.d                             
+    ACC1:acc#661.itm#1                          14         Y                  ACC1:acc#661.itm#1                                    
+    ACC1:acc#658.itm#1                          13         Y                  ACC1:acc#658.itm#1                                    
+    ACC1:acc#659.itm#1                          13         Y                  ACC1:acc#659.itm#1                                    
+    ACC1:acc#655.itm#1                          12         Y                  ACC1:acc#655.itm#1                                    
+    ACC1:acc#652.itm#1                          11         Y                  ACC1:acc#652.itm#1                                    
+    regs.regs:slc(regs.regs(2))#1.itm           10         Y                  regs.regs:slc(regs.regs(2))#1.itm                     
+    regs.regs:slc(regs.regs(2))#10.itm          10         Y                  regs.regs:slc(regs.regs(2))#10.itm                    
+    regs.regs:slc(regs.regs(2))#11.itm          10         Y                  regs.regs:slc(regs.regs(2))#11.itm                    
+    regs.regs:slc(regs.regs(2))#2.itm           10         Y                  regs.regs:slc(regs.regs(2))#2.itm                     
+    regs.regs:slc(regs.regs(2))#3.itm           10         Y                  regs.regs:slc(regs.regs(2))#3.itm                     
+    regs.regs:slc(regs.regs(2))#4.itm           10         Y                  regs.regs:slc(regs.regs(2))#4.itm                     
+    regs.regs:slc(regs.regs(2))#5.itm           10         Y                  regs.regs:slc(regs.regs(2))#5.itm                     
+    regs.regs:slc(regs.regs(2))#9.itm           10         Y                  regs.regs:slc(regs.regs(2))#9.itm                     
+    regs.regs:slc(regs.regs(2)).itm             10         Y                  regs.regs:slc(regs.regs(2)).itm                       
+    ACC1:mul#57.itm#1.sg2                        5         Y                  ACC1:mul#57.itm#1.sg2                                 
+    ACC1:mul#57.itm#2                            2         Y                  ACC1:mul#57.itm#2                                     
+    ACC1-3:slc(acc#10.psp)#62.itm#1              1         Y                  ACC1-3:slc(acc#10.psp)#62.itm#1                       
+    ACC1:slc(ACC1:acc#228.psp)#55.itm#1          1         Y                  ACC1:slc(ACC1:acc#228.psp)#55.itm#1                   
+    main.stage_0#2                               1         Y                  main.stage_0#2                                        
+    slc(acc#20.psp#1)#93.itm#1                   1         Y                  slc(acc#20.psp#1)#93.itm#1                            
+                                                                                                                                    
+    Total:                                     284            284           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  15.879753
+      Slack:      4.120247000000001
+      
+      Path                                           Startpoint                       Endpoint                           Delay   Slack   
+      ---------------------------------------------- -------------------------------- ---------------------------------- ------- -------
+      1                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]:not               mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]:not.itm                                                                               0.0000  0.0000  
+        sobel:core/ACC1:acc#331                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#331.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc                        mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                         0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3                                                                                  0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3.itm                                                                              0.0000  2.3449  
+        sobel:core/conc#1010                                                                                             0.0000  2.3449  
+        sobel:core/conc#1010.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#333                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#333.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#14                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#14.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1009                                                                                             0.0000  2.9974  
+        sobel:core/conc#1009.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#335                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#335.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#16                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#16.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#210                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#210.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4.itm                                                                     0.0000  4.2869  
+        sobel:core/conc#1086                                                                                             0.0000  4.2869  
+        sobel:core/conc#1086.itm                                                                                         0.0000  4.2869  
+        sobel:core/ACC1:acc#337                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#337.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#18                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#18.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#220                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#220.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)                                                                           0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva).itm                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#293                    mgc_not_2                                                           0.0000  5.2670  
+        sobel:core/ACC1-1:not#293.itm                                                                                    0.0000  5.2670  
+        sobel:core/conc#1004                                                                                             0.0000  5.2670  
+        sobel:core/conc#1004.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#338                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#338.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#19                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#26.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/conc#1099                                                                                             0.0000  5.7029  
+        sobel:core/conc#1099.itm                                                                                         0.0000  5.7029  
+        sobel:core/ACC1:acc#339                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#339.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#20                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#32.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva)                                                                                  0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva).itm                                                                              0.0000  6.1389  
+        sobel:core/ACC1-1:nand#1                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#1.cse.sva                                                                                 0.0000  6.4067  
+        sobel:core/ACC1:conc#1430                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1430.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1474                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1474.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#670                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#670.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#153                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#153.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#676                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#676.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#680                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#680.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#683                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#683.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#686                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#686.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#688                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#688.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#690                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#690.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#2                      mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#2.itm                                                                                      0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      2                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not            mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not.itm                                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#351                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#351.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc#20                     mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc#20.psp#2.sva                                                                                      0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17                                                                              0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17.itm                                                                          0.0000  2.3449  
+        sobel:core/conc#1096                                                                                             0.0000  2.3449  
+        sobel:core/conc#1096.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#353                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#353.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#30                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#30.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1095                                                                                             0.0000  2.9974  
+        sobel:core/conc#1095.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#355                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#355.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#32                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#32.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#217                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#217.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)#3                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)#3.itm                                                                     0.0000  4.2869  
+        sobel:core/conc#1098                                                                                             0.0000  4.2869  
+        sobel:core/conc#1098.itm                                                                                         0.0000  4.2869  
+        sobel:core/ACC1:acc#357                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#357.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#34                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#34.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#223                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#223.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva)                                                                           0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva).itm                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#299                    mgc_not_2                                                           0.0000  5.2670  
+        sobel:core/ACC1-1:not#299.itm                                                                                    0.0000  5.2670  
+        sobel:core/conc#1090                                                                                             0.0000  5.2670  
+        sobel:core/conc#1090.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#358                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#358.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#35                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#38.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#2                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#2.itm                                                                            0.0000  5.7029  
+        sobel:core/conc#1089                                                                                             0.0000  5.7029  
+        sobel:core/conc#1089.itm                                                                                         0.0000  5.7029  
+        sobel:core/ACC1:acc#359                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#359.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#36                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#40.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2                                                                                0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2.itm                                                                            0.0000  6.1389  
+        sobel:core/ACC1-1:nand#4                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#4.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#1445                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1445.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1485                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1485.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#696                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#696.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#160                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#160.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#702                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#702.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#706                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#706.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#709                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#709.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#712                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#712.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#714                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#714.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#716                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#716.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#27                     mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#27.itm                                                                                     0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      3                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]:not               mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]:not.itm                                                                               0.0000  0.0000  
+        sobel:core/ACC1:acc#331                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#331.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc                        mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                         0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3                                                                                  0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3.itm                                                                              0.0000  2.3449  
+        sobel:core/conc#1010                                                                                             0.0000  2.3449  
+        sobel:core/conc#1010.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#333                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#333.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#14                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#14.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1009                                                                                             0.0000  2.9974  
+        sobel:core/conc#1009.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#335                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#335.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#16                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#16.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#210                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#210.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4.itm                                                                     0.0000  4.2869  
+        sobel:core/conc#1086                                                                                             0.0000  4.2869  
+        sobel:core/conc#1086.itm                                                                                         0.0000  4.2869  
+        sobel:core/ACC1:acc#337                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#337.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#18                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#18.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#220                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#220.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1.itm                                                                     0.0000  5.2670  
+        sobel:core/conc#1005                                                                                             0.0000  5.2670  
+        sobel:core/conc#1005.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#338                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#338.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#19                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#26.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/conc#1099                                                                                             0.0000  5.7029  
+        sobel:core/conc#1099.itm                                                                                         0.0000  5.7029  
+        sobel:core/ACC1:acc#339                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#339.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#20                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#32.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva)                                                                                  0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva).itm                                                                              0.0000  6.1389  
+        sobel:core/ACC1-1:nand#1                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#1.cse.sva                                                                                 0.0000  6.4067  
+        sobel:core/ACC1:conc#1430                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1430.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1474                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1474.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#670                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#670.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#153                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#153.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#676                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#676.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#680                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#680.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#683                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#683.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#686                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#686.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#688                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#688.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#690                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#690.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#2                      mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#2.itm                                                                                      0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      4                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#8)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#8).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#1:not             mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]#1:not.itm                                                                             0.0000  0.0000  
+        sobel:core/ACC1:acc#331                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#331.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc                        mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                         0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3                                                                                  0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3.itm                                                                              0.0000  2.3449  
+        sobel:core/conc#1010                                                                                             0.0000  2.3449  
+        sobel:core/conc#1010.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#333                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#333.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#14                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#14.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1009                                                                                             0.0000  2.9974  
+        sobel:core/conc#1009.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#335                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#335.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#16                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#16.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#210                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#210.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4.itm                                                                     0.0000  4.2869  
+        sobel:core/conc#1086                                                                                             0.0000  4.2869  
+        sobel:core/conc#1086.itm                                                                                         0.0000  4.2869  
+        sobel:core/ACC1:acc#337                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#337.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#18                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#18.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#220                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#220.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1.itm                                                                     0.0000  5.2670  
+        sobel:core/conc#1005                                                                                             0.0000  5.2670  
+        sobel:core/conc#1005.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#338                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#338.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#19                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#26.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/conc#1099                                                                                             0.0000  5.7029  
+        sobel:core/conc#1099.itm                                                                                         0.0000  5.7029  
+        sobel:core/ACC1:acc#339                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#339.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#20                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#32.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva)                                                                                  0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva).itm                                                                              0.0000  6.1389  
+        sobel:core/ACC1-1:nand#1                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#1.cse.sva                                                                                 0.0000  6.4067  
+        sobel:core/ACC1:conc#1430                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1430.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1474                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1474.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#670                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#670.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#153                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#153.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#676                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#676.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#680                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#680.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#683                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#683.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#686                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#686.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#688                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#688.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#690                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#690.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#2                      mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#2.itm                                                                                      0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      5                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not            mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not.itm                                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#351                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#351.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc#20                     mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc#20.psp#2.sva                                                                                      0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17                                                                              0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17.itm                                                                          0.0000  2.3449  
+        sobel:core/conc#1096                                                                                             0.0000  2.3449  
+        sobel:core/conc#1096.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#353                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#353.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#30                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#30.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1095                                                                                             0.0000  2.9974  
+        sobel:core/conc#1095.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#355                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#355.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#32                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#32.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#217                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#217.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)#3                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)#3.itm                                                                     0.0000  4.2869  
+        sobel:core/conc#1098                                                                                             0.0000  4.2869  
+        sobel:core/conc#1098.itm                                                                                         0.0000  4.2869  
+        sobel:core/ACC1:acc#357                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#357.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#34                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#34.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#223                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#223.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva)                                                                           0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva).itm                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#299                    mgc_not_2                                                           0.0000  5.2670  
+        sobel:core/ACC1-1:not#299.itm                                                                                    0.0000  5.2670  
+        sobel:core/conc#1090                                                                                             0.0000  5.2670  
+        sobel:core/conc#1090.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#358                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#358.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#35                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#38.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/ACC1-1:not#153                    mgc_not_1                                                           0.0000  5.7029  
+        sobel:core/ACC1-1:not#153.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:conc#1180                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:conc#1180.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:acc#359                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#359.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#36                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#40.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2                                                                                0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2.itm                                                                            0.0000  6.1389  
+        sobel:core/ACC1-1:nand#4                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#4.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#1445                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1445.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1485                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1485.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#696                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#696.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#160                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#160.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#702                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#702.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#706                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#706.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#709                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#709.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#712                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#712.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#714                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#714.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#716                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#716.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#27                     mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#27.itm                                                                                     0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      6                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not            mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not.itm                                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#351                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#351.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc#20                     mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc#20.psp#2.sva                                                                                      0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17                                                                              0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17.itm                                                                          0.0000  2.3449  
+        sobel:core/conc#1096                                                                                             0.0000  2.3449  
+        sobel:core/conc#1096.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#353                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#353.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#30                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#30.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1095                                                                                             0.0000  2.9974  
+        sobel:core/conc#1095.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#355                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#355.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#32                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#32.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#217                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#217.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)#4                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)#4.itm                                                                     0.0000  4.2869  
+        sobel:core/ACC1-1:not#287                    mgc_not_1                                                           0.0000  4.2869  
+        sobel:core/ACC1-1:not#287.itm                                                                                    0.0000  4.2869  
+        sobel:core/ACC1:conc#1175                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:conc#1175.itm                                                                                    0.0000  4.2869  
+        sobel:core/ACC1:acc#357                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#357.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#34                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#34.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#223                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#223.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva)                                                                           0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva).itm                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#299                    mgc_not_2                                                           0.0000  5.2670  
+        sobel:core/ACC1-1:not#299.itm                                                                                    0.0000  5.2670  
+        sobel:core/conc#1090                                                                                             0.0000  5.2670  
+        sobel:core/conc#1090.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#358                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#358.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#35                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#38.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/ACC1-1:not#153                    mgc_not_1                                                           0.0000  5.7029  
+        sobel:core/ACC1-1:not#153.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:conc#1180                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:conc#1180.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:acc#359                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#359.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#36                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#40.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2                                                                                0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2.itm                                                                            0.0000  6.1389  
+        sobel:core/ACC1-1:nand#4                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#4.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#1445                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1445.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1485                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1485.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#696                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#696.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#160                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#160.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#702                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#702.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#706                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#706.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#709                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#709.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#712                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#712.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#714                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#714.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#716                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#716.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#27                     mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#27.itm                                                                                     0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      7                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]:not               mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]:not.itm                                                                               0.0000  0.0000  
+        sobel:core/ACC1:acc#331                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#331.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc                        mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                         0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3                                                                                  0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3.itm                                                                              0.0000  2.3449  
+        sobel:core/conc#1010                                                                                             0.0000  2.3449  
+        sobel:core/conc#1010.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#333                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#333.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#14                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#14.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1009                                                                                             0.0000  2.9974  
+        sobel:core/conc#1009.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#335                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#335.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#16                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#16.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#210                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#210.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#5                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#5.itm                                                                     0.0000  4.2869  
+        sobel:core/ACC1-1:not#273                    mgc_not_1                                                           0.0000  4.2869  
+        sobel:core/ACC1-1:not#273.itm                                                                                    0.0000  4.2869  
+        sobel:core/ACC1:conc#1139                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:conc#1139.itm                                                                                    0.0000  4.2869  
+        sobel:core/ACC1:acc#337                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#337.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#18                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#18.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#220                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#220.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1.itm                                                                     0.0000  5.2670  
+        sobel:core/conc#1005                                                                                             0.0000  5.2670  
+        sobel:core/conc#1005.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#338                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#338.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#19                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#26.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/conc#1099                                                                                             0.0000  5.7029  
+        sobel:core/conc#1099.itm                                                                                         0.0000  5.7029  
+        sobel:core/ACC1:acc#339                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#339.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#20                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#32.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva)                                                                                  0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva).itm                                                                              0.0000  6.1389  
+        sobel:core/ACC1-1:nand#1                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#1.cse.sva                                                                                 0.0000  6.4067  
+        sobel:core/ACC1:conc#1430                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1430.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1474                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1474.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#670                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#670.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#153                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#153.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#676                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#676.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#680                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#680.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#683                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#683.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#686                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#686.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#688                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#688.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#690                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#690.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#2                      mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#2.itm                                                                                      0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      8                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not            mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not.itm                                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#351                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#351.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc#20                     mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc#20.psp#2.sva                                                                                      0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17                                                                              0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17.itm                                                                          0.0000  2.3449  
+        sobel:core/conc#1096                                                                                             0.0000  2.3449  
+        sobel:core/conc#1096.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#353                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#353.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#30                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#30.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1095                                                                                             0.0000  2.9974  
+        sobel:core/conc#1095.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#355                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#355.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#32                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#32.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#217                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#217.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)                                                                           0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva).itm                                                                       0.0000  4.2869  
+        sobel:core/ACC1:conc#1175                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:conc#1175.itm                                                                                    0.0000  4.2869  
+        sobel:core/ACC1:acc#357                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#357.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#34                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#34.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#223                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#223.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva)                                                                           0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva).itm                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#299                    mgc_not_2                                                           0.0000  5.2670  
+        sobel:core/ACC1-1:not#299.itm                                                                                    0.0000  5.2670  
+        sobel:core/conc#1090                                                                                             0.0000  5.2670  
+        sobel:core/conc#1090.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#358                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#358.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#35                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#38.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/ACC1-1:not#153                    mgc_not_1                                                           0.0000  5.7029  
+        sobel:core/ACC1-1:not#153.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:conc#1180                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:conc#1180.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:acc#359                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#359.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#36                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#40.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2                                                                                0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2.itm                                                                            0.0000  6.1389  
+        sobel:core/ACC1-1:nand#4                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#4.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#1445                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1445.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1485                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1485.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#696                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#696.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#160                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#160.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#702                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#702.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#706                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#706.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#709                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#709.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#712                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#712.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#714                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#714.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#716                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#716.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#27                     mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#27.itm                                                                                     0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      9                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]:not               mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]:not.itm                                                                               0.0000  0.0000  
+        sobel:core/ACC1:acc#331                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#331.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc                        mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                         0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3                                                                                  0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3.itm                                                                              0.0000  2.3449  
+        sobel:core/conc#1010                                                                                             0.0000  2.3449  
+        sobel:core/conc#1010.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#333                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#333.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#14                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#14.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1009                                                                                             0.0000  2.9974  
+        sobel:core/conc#1009.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#335                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#335.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#16                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#16.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#210                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#210.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#1                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#1.itm                                                                     0.0000  4.2869  
+        sobel:core/ACC1:conc#1139                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:conc#1139.itm                                                                                    0.0000  4.2869  
+        sobel:core/ACC1:acc#337                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#337.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#18                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#18.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#220                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#220.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1.itm                                                                     0.0000  5.2670  
+        sobel:core/conc#1005                                                                                             0.0000  5.2670  
+        sobel:core/conc#1005.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#338                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#338.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#19                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#26.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/conc#1099                                                                                             0.0000  5.7029  
+        sobel:core/conc#1099.itm                                                                                         0.0000  5.7029  
+        sobel:core/ACC1:acc#339                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#339.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#20                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#32.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva)                                                                                  0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva).itm                                                                              0.0000  6.1389  
+        sobel:core/ACC1-1:nand#1                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#1.cse.sva                                                                                 0.0000  6.4067  
+        sobel:core/ACC1:conc#1430                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1430.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1474                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1474.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#670                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#670.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#153                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#153.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#676                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#676.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#680                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#680.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#683                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#683.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#686                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#686.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#688                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#688.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#690                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#690.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#2                      mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#2.itm                                                                                      0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      10                                             sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]:not               mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]:not.itm                                                                               0.0000  0.0000  
+        sobel:core/ACC1:acc#331                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#331.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc                        mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                         0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3                                                                                  0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3.itm                                                                              0.0000  2.3449  
+        sobel:core/conc#1010                                                                                             0.0000  2.3449  
+        sobel:core/conc#1010.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#333                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#333.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#14                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#14.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1009                                                                                             0.0000  2.9974  
+        sobel:core/conc#1009.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#335                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#335.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#16                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#16.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#210                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#210.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4.itm                                                                     0.0000  4.2869  
+        sobel:core/conc#1086                                                                                             0.0000  4.2869  
+        sobel:core/conc#1086.itm                                                                                         0.0000  4.2869  
+        sobel:core/ACC1:acc#337                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#337.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#18                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#18.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#220                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#220.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)                                                                           0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva).itm                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#293                    mgc_not_2                                                           0.0000  5.2670  
+        sobel:core/ACC1-1:not#293.itm                                                                                    0.0000  5.2670  
+        sobel:core/conc#1004                                                                                             0.0000  5.2670  
+        sobel:core/conc#1004.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#338                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#338.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#19                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#26.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#4                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#4.itm                                                                            0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                     mgc_not_1                                                           0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                     0.0000  5.7029  
+        sobel:core/ACC1:conc#1144                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:conc#1144.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:acc#339                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#339.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#20                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#32.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva)                                                                                  0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva).itm                                                                              0.0000  6.1389  
+        sobel:core/ACC1-1:nand#1                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#1.cse.sva                                                                                 0.0000  6.4067  
+        sobel:core/ACC1:conc#1430                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1430.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1474                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1474.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#670                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#670.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#153                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#153.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#676                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#676.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#680                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#680.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#683                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#683.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#686                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#686.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#688                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#688.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#690                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#690.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#2                      mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#2.itm                                                                                      0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                            Port                               Slack (Delay) Messages 
+      --------------------------------------------------- -------------------------------- ------- ------- --------
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)           mux.itm                           4.6050 15.3950          
+      sobel:core/reg(ACC1:acc#659.itm#1)                  ACC1:acc#659.itm                  4.1202 15.8798          
+      sobel:core/reg(ACC1:acc#658.itm#1)                  ACC1:acc#658.itm                  6.6969 13.3031          
+      sobel:core/reg(ACC1:acc#661.itm#1)                  ACC1:acc#661.itm                 11.0359  8.9641          
+      sobel:core/reg(ACC1:mul#57.itm#1.sg2)               slc(ACC1:mul#57.itm)#2.itm       13.6498  6.3502          
+      sobel:core/reg(ACC1:mul#57.itm#2)                   slc(ACC1:mul#57.itm)#3.itm       13.6498  6.3502          
+      sobel:core/reg(slc(acc#20.psp#1)#93.itm#1)          slc(acc#20.psp#1.sva)#12.itm     17.6551  2.3449          
+      sobel:core/reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1) slc(ACC1:acc#228.psp.sva)#14.itm 17.6551  2.3449          
+      sobel:core/reg(ACC1-3:slc(acc#10.psp)#62.itm#1)     slc(ACC1:acc#224.psp.sva)#16.itm 17.6551  2.3449          
+      sobel:core/reg(ACC1:acc#652.itm#1)                  ACC1:acc#652.itm                  4.3273 15.6727          
+      sobel:core/reg(ACC1:acc#655.itm#1)                  ACC1:acc#655.itm                  5.0044 14.9956          
+      sobel:core/reg(main.stage_0#2)                      C0_10#10_Not                     20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#10.itm)  slc(regs.regs(1).sva)#2.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#11.itm)  slc(regs.regs(1).sva)#1.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#9.itm)   slc(regs.regs(1).sva).itm        20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#4.itm)   slc(regs.regs(1).sva)#5.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#5.itm)   slc(regs.regs(1).sva)#4.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#3.itm)   slc(regs.regs(1).sva)#3.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2)).itm)     slc(regs.regs(1).sva)#8.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#1.itm)   slc(regs.regs(1).sva)#7.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#2.itm)   slc(regs.regs(1).sva)#6.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs(0).sva)                    vin:rsc:mgc_in_wire.d             4.1202 15.8798          
+      sobel                                               vout:rsc.z                       20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                   15     3 
+    -                   14     2 
+    -                   13     6 
+    -                   12    20 
+    -                   11    21 
+    -                   10     9 
+    -                    9    11 
+    -                    8    14 
+    -                    7    19 
+    -                    6    29 
+    -                    5    89 
+    -                    4   153 
+    -                    3    53 
+    -                    2    13 
+    and                          
+    -                    3    10 
+    mul                          
+    -                   14     1 
+    -                   13     2 
+    -                   12     1 
+    -                   10     2 
+    -                    9     1 
+    -                    8     2 
+    mux                          
+    -                    1     1 
+    nand                         
+    -                    2    10 
+    not                          
+    -                   10    15 
+    -                    3     4 
+    -                    2    14 
+    -                    1   141 
+    or                           
+    -                    2     2 
+    read_port                    
+    -                   90     1 
+    reg                          
+    -                   90     1 
+    -                   30     1 
+    -                   14     1 
+    -                   13     2 
+    -                   12     1 
+    -                   11     1 
+    -                   10     9 
+    -                    5     1 
+    -                    2     1 
+    -                    1     4 
+    write_port                   
+    -                   30     1 
+    
+  End of Report
diff --git a/Sobel/sobel.v11/rtl.v b/Sobel/sobel.v11/rtl.v
new file mode 100644
index 0000000..2326a1a
--- /dev/null
+++ b/Sobel/sobel.v11/rtl.v
@@ -0,0 +1,1609 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 16:15:58 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] regs_regs_slc_regs_regs_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_1_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_4_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_5_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_3_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_10_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_11_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_9_itm;
+  reg [12:0] ACC1_acc_659_itm_1;
+  wire [14:0] nl_ACC1_acc_659_itm_1;
+  reg [12:0] ACC1_acc_658_itm_1;
+  wire [13:0] nl_ACC1_acc_658_itm_1;
+  reg [13:0] ACC1_acc_661_itm_1;
+  wire [14:0] nl_ACC1_acc_661_itm_1;
+  reg slc_acc_20_psp_1_93_itm_1;
+  reg ACC1_slc_ACC1_acc_228_psp_55_itm_1;
+  reg ACC1_3_slc_acc_10_psp_62_itm_1;
+  reg [10:0] ACC1_acc_652_itm_1;
+  wire [11:0] nl_ACC1_acc_652_itm_1;
+  reg [11:0] ACC1_acc_655_itm_1;
+  wire [12:0] nl_ACC1_acc_655_itm_1;
+  reg main_stage_0_2;
+  reg [4:0] ACC1_mul_57_itm_1_sg2;
+  reg [1:0] ACC1_mul_57_itm_2;
+  reg [89:0] reg_regs_regs_0_sva_cse;
+  wire [11:0] FRAME_acc_2_psp_sva;
+  wire [13:0] nl_FRAME_acc_2_psp_sva;
+  wire [5:0] acc_imod_24_sva;
+  wire [7:0] nl_acc_imod_24_sva;
+  wire [11:0] acc_20_psp_1_sva;
+  wire [12:0] nl_acc_20_psp_1_sva;
+  wire [11:0] ACC1_acc_228_psp_sva;
+  wire [12:0] nl_ACC1_acc_228_psp_sva;
+  wire [11:0] ACC1_1_acc_25_psp_sva;
+  wire [12:0] nl_ACC1_1_acc_25_psp_sva;
+  wire [2:0] ACC1_acc_509_cse;
+  wire [3:0] nl_ACC1_acc_509_cse;
+  wire [11:0] ACC1_acc_227_psp_sva;
+  wire [12:0] nl_ACC1_acc_227_psp_sva;
+  wire [2:0] ACC1_acc_506_cse;
+  wire [3:0] nl_ACC1_acc_506_cse;
+  wire [3:0] ACC1_acc_562_ncse;
+  wire [4:0] nl_ACC1_acc_562_ncse;
+  wire [2:0] ACC1_acc_502_cse;
+  wire [3:0] nl_ACC1_acc_502_cse;
+  wire [2:0] ACC1_acc_489_cse;
+  wire [3:0] nl_ACC1_acc_489_cse;
+  wire [11:0] ACC1_acc_226_psp_sva;
+  wire [12:0] nl_ACC1_acc_226_psp_sva;
+  wire [3:0] ACC1_acc_553_ncse;
+  wire [4:0] nl_ACC1_acc_553_ncse;
+  wire ACC1_1_and_3_cse_sva;
+  wire ACC1_1_nand_1_cse_sva;
+  wire [11:0] acc_psp_1_sva;
+  wire [12:0] nl_acc_psp_1_sva;
+  wire [3:0] ACC1_acc_210_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_210_psp_2_sva;
+  wire [11:0] acc_psp_2_sva;
+  wire [12:0] nl_acc_psp_2_sva;
+  wire [11:0] ACC1_acc_224_psp_1_sva;
+  wire [12:0] nl_ACC1_acc_224_psp_1_sva;
+  wire [3:0] ACC1_1_acc_208_psp_sva;
+  wire [4:0] nl_ACC1_1_acc_208_psp_sva;
+  wire [11:0] ACC1_acc_224_psp_sva;
+  wire [12:0] nl_ACC1_acc_224_psp_sva;
+  wire [2:0] ACC1_acc_516_cse;
+  wire [3:0] nl_ACC1_acc_516_cse;
+  wire [3:0] ACC1_3_acc_212_psp_sva;
+  wire [4:0] nl_ACC1_3_acc_212_psp_sva;
+  wire [2:0] ACC1_acc_221_psp_sva;
+  wire [3:0] nl_ACC1_acc_221_psp_sva;
+  wire [2:0] ACC1_acc_221_psp_2_sva;
+  wire [3:0] nl_ACC1_acc_221_psp_2_sva;
+  wire [2:0] ACC1_acc_219_psp_2_sva;
+  wire [3:0] nl_ACC1_acc_219_psp_2_sva;
+  wire [2:0] ACC1_acc_222_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_222_psp_1_sva;
+  wire [2:0] ACC1_acc_219_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_219_psp_1_sva;
+  wire [3:0] ACC1_acc_210_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_210_psp_1_sva;
+  wire [3:0] ACC1_acc_217_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_217_psp_1_sva;
+  wire [2:0] ACC1_acc_724_cse;
+  wire [3:0] nl_ACC1_acc_724_cse;
+  wire [13:0] ACC1_mul_57_itm;
+  wire [27:0] nl_ACC1_mul_57_itm;
+  wire [2:0] ACC1_acc_223_psp_sva;
+  wire [3:0] nl_ACC1_acc_223_psp_sva;
+  wire [2:0] ACC1_acc_220_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_220_psp_1_sva;
+  wire [2:0] ACC1_acc_220_psp_sva;
+  wire [3:0] nl_ACC1_acc_220_psp_sva;
+  wire [2:0] ACC1_acc_222_psp_sva;
+  wire [3:0] nl_ACC1_acc_222_psp_sva;
+  wire [2:0] ACC1_acc_673_cse;
+  wire [3:0] nl_ACC1_acc_673_cse;
+  wire [11:0] acc_20_psp_2_sva;
+  wire [12:0] nl_acc_20_psp_2_sva;
+  wire [3:0] ACC1_acc_217_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_217_psp_2_sva;
+  wire [2:0] ACC1_acc_223_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_223_psp_1_sva;
+  wire [2:0] ACC1_acc_699_cse;
+  wire [3:0] nl_ACC1_acc_699_cse;
+  wire [14:0] ACC1_acc_itm;
+  wire [16:0] nl_ACC1_acc_itm;
+  wire [3:0] ACC1_acc_338_itm;
+  wire [4:0] nl_ACC1_acc_338_itm;
+  wire [2:0] ACC1_acc_406_itm;
+  wire [3:0] nl_ACC1_acc_406_itm;
+  wire [2:0] ACC1_acc_368_itm;
+  wire [3:0] nl_ACC1_acc_368_itm;
+  wire [3:0] ACC1_acc_367_itm;
+  wire [4:0] nl_ACC1_acc_367_itm;
+  wire [2:0] ACC1_acc_349_itm;
+  wire [3:0] nl_ACC1_acc_349_itm;
+  wire [3:0] ACC1_acc_348_itm;
+  wire [4:0] nl_ACC1_acc_348_itm;
+  wire [4:0] ACC1_acc_412_itm;
+  wire [5:0] nl_ACC1_acc_412_itm;
+  wire [3:0] ACC1_acc_423_itm;
+  wire [4:0] nl_ACC1_acc_423_itm;
+  wire [4:0] ACC1_acc_375_itm;
+  wire [5:0] nl_ACC1_acc_375_itm;
+  wire [3:0] ACC1_acc_395_itm;
+  wire [4:0] nl_ACC1_acc_395_itm;
+  wire [4:0] ACC1_acc_384_itm;
+  wire [5:0] nl_ACC1_acc_384_itm;
+  wire [3:0] ACC1_acc_414_itm;
+  wire [4:0] nl_ACC1_acc_414_itm;
+  wire [3:0] ACC1_acc_377_itm;
+  wire [4:0] nl_ACC1_acc_377_itm;
+  wire [4:0] ACC1_acc_346_itm;
+  wire [5:0] nl_ACC1_acc_346_itm;
+  wire [3:0] ACC1_acc_386_itm;
+  wire [4:0] nl_ACC1_acc_386_itm;
+  wire [3:0] ACC1_acc_405_itm;
+  wire [4:0] nl_ACC1_acc_405_itm;
+  wire [2:0] ACC1_acc_387_itm;
+  wire [3:0] nl_ACC1_acc_387_itm;
+  wire [2:0] ACC1_acc_378_itm;
+  wire [3:0] nl_ACC1_acc_378_itm;
+  wire [2:0] ACC1_acc_415_itm;
+  wire [3:0] nl_ACC1_acc_415_itm;
+  wire [2:0] ACC1_acc_396_itm;
+  wire [3:0] nl_ACC1_acc_396_itm;
+  wire [2:0] ACC1_acc_424_itm;
+  wire [3:0] nl_ACC1_acc_424_itm;
+  wire [2:0] ACC1_acc_359_itm;
+  wire [3:0] nl_ACC1_acc_359_itm;
+  wire [3:0] ACC1_acc_358_itm;
+  wire [4:0] nl_ACC1_acc_358_itm;
+  wire [2:0] ACC1_acc_339_itm;
+  wire [3:0] nl_ACC1_acc_339_itm;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_2_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(ACC1_acc_itm[14:13])
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_itm[12:10])
+      * 9'b111001)) + conv_s2s_7_10(conv_u2s_6_7(ACC1_acc_itm[9:4]) + conv_s2s_5_7(({4'b1001
+      , (acc_imod_24_sva[5])}) + conv_u2s_4_5((conv_u2u_3_4({(~ (acc_imod_24_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_24_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_24_sva[5:3])) , (~ (acc_imod_24_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_24_sva[4:3]))
+      + conv_u2u_3_4(~ (ACC1_acc_itm[9:7]))))))) + conv_u2u_11_12(signext_11_9({(ACC1_acc_itm[14])
+      , 3'b0 , (signext_3_1(ACC1_acc_itm[14])) , 1'b0 , (ACC1_acc_itm[14])}));
+  assign FRAME_acc_2_psp_sva = nl_FRAME_acc_2_psp_sva[11:0];
+  assign nl_ACC1_acc_itm = (conv_s2s_14_15(conv_s2s_13_14(ACC1_acc_659_itm_1) + conv_s2s_13_14(ACC1_acc_658_itm_1))
+      + conv_s2s_14_15(ACC1_acc_661_itm_1)) + conv_s2s_14_15(({ACC1_mul_57_itm_1_sg2
+      , 7'b0 , ACC1_mul_57_itm_2}) + conv_s2s_13_14(conv_s2s_12_13(({slc_acc_20_psp_1_93_itm_1
+      , 2'b0 , slc_acc_20_psp_1_93_itm_1 , 1'b0 , slc_acc_20_psp_1_93_itm_1 , 1'b0
+      , slc_acc_20_psp_1_93_itm_1 , ACC1_slc_ACC1_acc_228_psp_55_itm_1 , 1'b0 , ({{1{ACC1_3_slc_acc_10_psp_62_itm_1}},
+      ACC1_3_slc_acc_10_psp_62_itm_1})}) + conv_u2s_11_12(ACC1_acc_652_itm_1)) +
+      conv_s2s_12_13(ACC1_acc_655_itm_1)));
+  assign ACC1_acc_itm = nl_ACC1_acc_itm[14:0];
+  assign nl_acc_imod_24_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~ (ACC1_acc_itm[14]))
+      , 1'b1 , (~ (ACC1_acc_itm[14]))}) + conv_u2u_2_4(ACC1_acc_itm[14:13]))) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_itm[3:1])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[6:4])))) + 6'b101011;
+  assign acc_imod_24_sva = nl_acc_imod_24_sva[5:0];
+  assign nl_acc_20_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_10_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_11_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_9_itm);
+  assign acc_20_psp_1_sva = nl_acc_20_psp_1_sva[11:0];
+  assign nl_ACC1_acc_228_psp_sva = conv_s2u_11_12(conv_s2s_10_11(~ (reg_regs_regs_0_sva_cse[9:0]))
+      + conv_s2s_10_11(~ (reg_regs_regs_0_sva_cse[19:10]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (reg_regs_regs_0_sva_cse[29:20])) + 11'b11);
+  assign ACC1_acc_228_psp_sva = nl_ACC1_acc_228_psp_sva[11:0];
+  assign nl_ACC1_1_acc_25_psp_sva = conv_s2s_11_12(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[79:70])
+      + conv_s2s_10_11(vin_rsc_mgc_in_wire_d[69:60])) + conv_s2s_10_12(vin_rsc_mgc_in_wire_d[89:80]);
+  assign ACC1_1_acc_25_psp_sva = nl_ACC1_1_acc_25_psp_sva[11:0];
+  assign nl_ACC1_acc_509_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]));
+  assign ACC1_acc_509_cse = nl_ACC1_acc_509_cse[2:0];
+  assign nl_ACC1_acc_227_psp_sva = conv_s2s_11_12(conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_itm)
+      + conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_1_itm)) + conv_s2s_11_12(conv_s2s_10_11(~
+      regs_regs_slc_regs_regs_2_2_itm) + 11'b11);
+  assign ACC1_acc_227_psp_sva = nl_ACC1_acc_227_psp_sva[11:0];
+  assign nl_ACC1_acc_506_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+  assign ACC1_acc_506_cse = nl_ACC1_acc_506_cse[2:0];
+  assign nl_ACC1_acc_562_ncse = conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(ACC1_acc_506_cse);
+  assign ACC1_acc_562_ncse = nl_ACC1_acc_562_ncse[3:0];
+  assign nl_ACC1_acc_502_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[5])) + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+  assign ACC1_acc_502_cse = nl_ACC1_acc_502_cse[2:0];
+  assign nl_ACC1_acc_489_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]));
+  assign ACC1_acc_489_cse = nl_ACC1_acc_489_cse[2:0];
+  assign nl_ACC1_acc_226_psp_sva = conv_s2u_11_12(conv_s2s_10_11(reg_regs_regs_0_sva_cse[79:70])
+      + conv_s2s_10_11(reg_regs_regs_0_sva_cse[69:60])) + conv_s2u_10_12(reg_regs_regs_0_sva_cse[89:80]);
+  assign ACC1_acc_226_psp_sva = nl_ACC1_acc_226_psp_sva[11:0];
+  assign nl_ACC1_acc_553_ncse = conv_u2u_3_4(ACC1_acc_489_cse) + conv_u2u_3_4(ACC1_acc_489_cse);
+  assign ACC1_acc_553_ncse = nl_ACC1_acc_553_ncse[3:0];
+  assign ACC1_1_and_3_cse_sva = (acc_psp_2_sva[11]) & (~ (ACC1_acc_339_itm[2])) &
+      (ACC1_acc_339_itm[1]);
+  assign ACC1_1_nand_1_cse_sva = ~((ACC1_acc_339_itm[2]) & (~ (acc_psp_2_sva[11])));
+  assign nl_acc_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_1_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_2_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_itm);
+  assign acc_psp_1_sva = nl_acc_psp_1_sva[11:0];
+  assign nl_ACC1_acc_338_itm = conv_s2s_3_4({(~ (ACC1_acc_220_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_220_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_338_itm = nl_ACC1_acc_338_itm[3:0];
+  assign nl_ACC1_acc_210_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_2_sva[1])) , (acc_psp_2_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_2_sva[0]) , (acc_psp_2_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[3])) , (~ (acc_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[5])) , (acc_psp_2_sva[6])})))) ,
+      (~ (acc_psp_2_sva[9]))}))));
+  assign ACC1_acc_210_psp_2_sva = nl_ACC1_acc_210_psp_2_sva[3:0];
+  assign nl_acc_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[29:20]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[19:10]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[9:0])) + 11'b11);
+  assign acc_psp_2_sva = nl_acc_psp_2_sva[11:0];
+  assign nl_ACC1_acc_224_psp_1_sva = conv_s2u_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[39:30]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[49:40]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[59:50])) + 11'b11);
+  assign ACC1_acc_224_psp_1_sva = nl_ACC1_acc_224_psp_1_sva[11:0];
+  assign nl_ACC1_acc_406_itm = ({1'b1 , (ACC1_acc_405_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_405_itm[2])) , (~ (ACC1_acc_405_itm[3]))});
+  assign ACC1_acc_406_itm = nl_ACC1_acc_406_itm[2:0];
+  assign nl_ACC1_acc_368_itm = ({1'b1 , (ACC1_acc_367_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_367_itm[2])) , (~ (ACC1_acc_367_itm[3]))});
+  assign ACC1_acc_368_itm = nl_ACC1_acc_368_itm[2:0];
+  assign nl_ACC1_acc_367_itm = conv_s2s_3_4({(~ (ACC1_acc_219_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_367_itm = nl_ACC1_acc_367_itm[3:0];
+  assign nl_ACC1_1_acc_208_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (ACC1_1_acc_25_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_1_acc_25_psp_sva[1]))
+      , (ACC1_1_acc_25_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (ACC1_1_acc_25_psp_sva[0])
+      , (ACC1_1_acc_25_psp_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[3])) , (~ (ACC1_1_acc_25_psp_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[5])) , (ACC1_1_acc_25_psp_sva[6])}))))
+      , (~ (ACC1_1_acc_25_psp_sva[9]))}))));
+  assign ACC1_1_acc_208_psp_sva = nl_ACC1_1_acc_208_psp_sva[3:0];
+  assign nl_ACC1_acc_349_itm = ({1'b1 , (ACC1_acc_348_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_348_itm[2])) , (~ (ACC1_acc_348_itm[3]))});
+  assign ACC1_acc_349_itm = nl_ACC1_acc_349_itm[2:0];
+  assign nl_ACC1_acc_348_itm = conv_s2s_3_4({(~ (ACC1_acc_222_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_222_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_348_itm = nl_ACC1_acc_348_itm[3:0];
+  assign nl_ACC1_acc_224_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_4_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_5_itm)) + conv_s2u_10_12(regs_regs_slc_regs_regs_2_3_itm);
+  assign ACC1_acc_224_psp_sva = nl_ACC1_acc_224_psp_sva[11:0];
+  assign nl_ACC1_acc_516_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]));
+  assign ACC1_acc_516_cse = nl_ACC1_acc_516_cse[2:0];
+  assign nl_ACC1_acc_412_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_224_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[2])) , (~ (ACC1_acc_224_psp_sva[6]))}))))
+      , (~ (ACC1_acc_224_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[4])) , (ACC1_acc_224_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_sva[11:10])) , (ACC1_acc_224_psp_sva[7])}))))
+      , (ACC1_acc_224_psp_sva[9])});
+  assign ACC1_acc_412_itm = nl_ACC1_acc_412_itm[4:0];
+  assign nl_ACC1_acc_423_itm = conv_s2s_3_4({(~ (ACC1_acc_223_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_223_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_423_itm = nl_ACC1_acc_423_itm[3:0];
+  assign nl_ACC1_acc_375_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_228_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[2])) , (~ (ACC1_acc_228_psp_sva[6]))}))))
+      , (~ (ACC1_acc_228_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[4])) , (ACC1_acc_228_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_228_psp_sva[11:10])) , (ACC1_acc_228_psp_sva[7])}))))
+      , (ACC1_acc_228_psp_sva[9])});
+  assign ACC1_acc_375_itm = nl_ACC1_acc_375_itm[4:0];
+  assign nl_ACC1_acc_395_itm = conv_s2s_3_4({(~ (ACC1_acc_220_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_220_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_395_itm = nl_ACC1_acc_395_itm[3:0];
+  assign nl_ACC1_acc_384_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_226_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[2])) , (~ (ACC1_acc_226_psp_sva[6]))}))))
+      , (~ (ACC1_acc_226_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[4])) , (ACC1_acc_226_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_226_psp_sva[11:10])) , (ACC1_acc_226_psp_sva[7])}))))
+      , (ACC1_acc_226_psp_sva[9])});
+  assign ACC1_acc_384_itm = nl_ACC1_acc_384_itm[4:0];
+  assign nl_ACC1_3_acc_212_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (ACC1_acc_227_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_acc_227_psp_sva[1]))
+      , (ACC1_acc_227_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (ACC1_acc_227_psp_sva[0])
+      , (ACC1_acc_227_psp_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[3])) , (~ (ACC1_acc_227_psp_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[5])) , (ACC1_acc_227_psp_sva[6])}))))
+      , (~ (ACC1_acc_227_psp_sva[9]))}))));
+  assign ACC1_3_acc_212_psp_sva = nl_ACC1_3_acc_212_psp_sva[3:0];
+  assign nl_ACC1_acc_414_itm = conv_s2s_3_4({(~ (ACC1_acc_222_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_222_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_414_itm = nl_ACC1_acc_414_itm[3:0];
+  assign nl_ACC1_acc_377_itm = conv_s2s_3_4({(~ (ACC1_acc_221_psp_2_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_221_psp_2_sva[0]) , 1'b1});
+  assign ACC1_acc_377_itm = nl_ACC1_acc_377_itm[3:0];
+  assign nl_ACC1_acc_346_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_224_psp_1_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[2])) , (~ (ACC1_acc_224_psp_1_sva[6]))}))))
+      , (~ (ACC1_acc_224_psp_1_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[4])) , (ACC1_acc_224_psp_1_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_1_sva[11:10])) , (ACC1_acc_224_psp_1_sva[7])}))))
+      , (ACC1_acc_224_psp_1_sva[9])});
+  assign ACC1_acc_346_itm = nl_ACC1_acc_346_itm[4:0];
+  assign nl_ACC1_acc_386_itm = conv_s2s_3_4({(~ (ACC1_acc_219_psp_2_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_2_sva[0]) , 1'b1});
+  assign ACC1_acc_386_itm = nl_ACC1_acc_386_itm[3:0];
+  assign nl_ACC1_acc_405_itm = conv_s2s_3_4({(~ (ACC1_acc_221_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_221_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_405_itm = nl_ACC1_acc_405_itm[3:0];
+  assign nl_ACC1_acc_221_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_3_acc_212_psp_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_3_acc_212_psp_sva[1])) , (ACC1_3_acc_212_psp_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_3_acc_212_psp_sva[3]));
+  assign ACC1_acc_221_psp_sva = nl_ACC1_acc_221_psp_sva[2:0];
+  assign nl_ACC1_acc_221_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_375_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_375_itm[2])) , (ACC1_acc_375_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_375_itm[4]));
+  assign ACC1_acc_221_psp_2_sva = nl_ACC1_acc_221_psp_2_sva[2:0];
+  assign nl_ACC1_acc_219_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_384_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_384_itm[2])) , (ACC1_acc_384_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_384_itm[4]));
+  assign ACC1_acc_219_psp_2_sva = nl_ACC1_acc_219_psp_2_sva[2:0];
+  assign nl_ACC1_acc_222_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_346_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_346_itm[2])) , (ACC1_acc_346_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_346_itm[4]));
+  assign ACC1_acc_222_psp_1_sva = nl_ACC1_acc_222_psp_1_sva[2:0];
+  assign nl_ACC1_acc_219_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_208_psp_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_208_psp_sva[1])) , (ACC1_1_acc_208_psp_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_1_acc_208_psp_sva[3]));
+  assign ACC1_acc_219_psp_1_sva = nl_ACC1_acc_219_psp_1_sva[2:0];
+  assign nl_ACC1_acc_387_itm = ({1'b1 , (ACC1_acc_386_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_386_itm[2])) , (~ (ACC1_acc_386_itm[3]))});
+  assign ACC1_acc_387_itm = nl_ACC1_acc_387_itm[2:0];
+  assign nl_ACC1_acc_378_itm = ({1'b1 , (ACC1_acc_377_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_377_itm[2])) , (~ (ACC1_acc_377_itm[3]))});
+  assign ACC1_acc_378_itm = nl_ACC1_acc_378_itm[2:0];
+  assign nl_ACC1_acc_415_itm = ({1'b1 , (ACC1_acc_414_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_414_itm[2])) , (~ (ACC1_acc_414_itm[3]))});
+  assign ACC1_acc_415_itm = nl_ACC1_acc_415_itm[2:0];
+  assign nl_ACC1_acc_396_itm = ({1'b1 , (ACC1_acc_395_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_395_itm[2])) , (~ (ACC1_acc_395_itm[3]))});
+  assign ACC1_acc_396_itm = nl_ACC1_acc_396_itm[2:0];
+  assign nl_ACC1_acc_210_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_1_sva[1])) , (acc_psp_1_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_1_sva[0]) , (acc_psp_1_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[3])) , (~ (acc_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[5])) , (acc_psp_1_sva[6])})))) ,
+      (~ (acc_psp_1_sva[9]))}))));
+  assign ACC1_acc_210_psp_1_sva = nl_ACC1_acc_210_psp_1_sva[3:0];
+  assign nl_ACC1_acc_217_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_20_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_1_sva[1]))
+      , (acc_20_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_1_sva[0])
+      , (acc_20_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[3])) , (~ (acc_20_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[5])) , (acc_20_psp_1_sva[6])}))))
+      , (~ (acc_20_psp_1_sva[9]))}))));
+  assign ACC1_acc_217_psp_1_sva = nl_ACC1_acc_217_psp_1_sva[3:0];
+  assign nl_ACC1_acc_424_itm = ({1'b1 , (ACC1_acc_423_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_423_itm[2])) , (~ (ACC1_acc_423_itm[3]))});
+  assign ACC1_acc_424_itm = nl_ACC1_acc_424_itm[2:0];
+  assign nl_ACC1_acc_724_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]));
+  assign ACC1_acc_724_cse = nl_ACC1_acc_724_cse[2:0];
+  assign nl_ACC1_mul_57_itm = conv_u2s_2_14((conv_u2u_1_2(ACC1_acc_224_psp_sva[11])
+      + conv_u2u_1_2(ACC1_acc_228_psp_sva[11])) + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[11]))
+      * 14'b11101000000001;
+  assign ACC1_mul_57_itm = nl_ACC1_mul_57_itm[13:0];
+  assign nl_ACC1_acc_223_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_1_sva[1])) , (ACC1_acc_217_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_217_psp_1_sva[3]));
+  assign ACC1_acc_223_psp_sva = nl_ACC1_acc_223_psp_sva[2:0];
+  assign nl_ACC1_acc_220_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_2_sva[1])) , (ACC1_acc_210_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_210_psp_2_sva[3]));
+  assign ACC1_acc_220_psp_1_sva = nl_ACC1_acc_220_psp_1_sva[2:0];
+  assign nl_ACC1_acc_220_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_1_sva[1])) , (ACC1_acc_210_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_210_psp_1_sva[3]));
+  assign ACC1_acc_220_psp_sva = nl_ACC1_acc_220_psp_sva[2:0];
+  assign nl_ACC1_acc_222_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_412_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_412_itm[2])) , (ACC1_acc_412_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_412_itm[4]));
+  assign ACC1_acc_222_psp_sva = nl_ACC1_acc_222_psp_sva[2:0];
+  assign nl_ACC1_acc_673_cse = conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11]));
+  assign ACC1_acc_673_cse = nl_ACC1_acc_673_cse[2:0];
+  assign nl_acc_20_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[89:80]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[79:70]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[69:60])) + 11'b11);
+  assign acc_20_psp_2_sva = nl_acc_20_psp_2_sva[11:0];
+  assign nl_ACC1_acc_359_itm = ({1'b1 , (ACC1_acc_358_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_358_itm[2])) , (~ (ACC1_acc_358_itm[3]))});
+  assign ACC1_acc_359_itm = nl_ACC1_acc_359_itm[2:0];
+  assign nl_ACC1_acc_358_itm = conv_s2s_3_4({(~ (ACC1_acc_223_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_223_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_358_itm = nl_ACC1_acc_358_itm[3:0];
+  assign nl_ACC1_acc_217_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_20_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_2_sva[1]))
+      , (acc_20_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_2_sva[0])
+      , (acc_20_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[3])) , (~ (acc_20_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[5])) , (acc_20_psp_2_sva[6])}))))
+      , (~ (acc_20_psp_2_sva[9]))}))));
+  assign ACC1_acc_217_psp_2_sva = nl_ACC1_acc_217_psp_2_sva[3:0];
+  assign nl_ACC1_acc_223_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_2_sva[1])) , (ACC1_acc_217_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_217_psp_2_sva[3]));
+  assign ACC1_acc_223_psp_1_sva = nl_ACC1_acc_223_psp_1_sva[2:0];
+  assign nl_ACC1_acc_699_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11]));
+  assign ACC1_acc_699_cse = nl_ACC1_acc_699_cse[2:0];
+  assign nl_ACC1_acc_339_itm = ({1'b1 , (ACC1_acc_338_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_338_itm[2])) , (~ (ACC1_acc_338_itm[3]))});
+  assign ACC1_acc_339_itm = nl_ACC1_acc_339_itm[2:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      ACC1_acc_659_itm_1 <= 13'b0;
+      ACC1_acc_658_itm_1 <= 13'b0;
+      ACC1_acc_661_itm_1 <= 14'b0;
+      ACC1_mul_57_itm_1_sg2 <= 5'b0;
+      ACC1_mul_57_itm_2 <= 2'b0;
+      slc_acc_20_psp_1_93_itm_1 <= 1'b0;
+      ACC1_slc_ACC1_acc_228_psp_55_itm_1 <= 1'b0;
+      ACC1_3_slc_acc_10_psp_62_itm_1 <= 1'b0;
+      ACC1_acc_652_itm_1 <= 11'b0;
+      ACC1_acc_655_itm_1 <= 12'b0;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_slc_regs_regs_2_10_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_11_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_9_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_4_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_5_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_3_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_1_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_2_itm <= 10'b0;
+      reg_regs_regs_0_sva_cse <= 90'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({vout_rsc_mgc_out_stdreg_d , ({((FRAME_acc_2_psp_sva[9:0])
+            | ({8'b0 , (FRAME_acc_2_psp_sva[11:10])})) , (FRAME_acc_2_psp_sva[9:6])
+            , ((FRAME_acc_2_psp_sva[5:0]) | ({4'b0 , (FRAME_acc_2_psp_sva[11:10])}))
+            , (FRAME_acc_2_psp_sva[9:0])})}, main_stage_0_2);
+        ACC1_acc_659_itm_1 <= nl_ACC1_acc_659_itm_1[12:0];
+        ACC1_acc_658_itm_1 <= nl_ACC1_acc_658_itm_1[12:0];
+        ACC1_acc_661_itm_1 <= nl_ACC1_acc_661_itm_1[13:0];
+        ACC1_mul_57_itm_1_sg2 <= ACC1_mul_57_itm[13:9];
+        ACC1_mul_57_itm_2 <= ACC1_mul_57_itm[1:0];
+        slc_acc_20_psp_1_93_itm_1 <= acc_20_psp_1_sva[11];
+        ACC1_slc_ACC1_acc_228_psp_55_itm_1 <= ACC1_acc_228_psp_sva[6];
+        ACC1_3_slc_acc_10_psp_62_itm_1 <= ACC1_acc_224_psp_sva[8];
+        ACC1_acc_652_itm_1 <= nl_ACC1_acc_652_itm_1[10:0];
+        ACC1_acc_655_itm_1 <= nl_ACC1_acc_655_itm_1[11:0];
+        main_stage_0_2 <= 1'b1;
+        regs_regs_slc_regs_regs_2_10_itm <= reg_regs_regs_0_sva_cse[79:70];
+        regs_regs_slc_regs_regs_2_11_itm <= reg_regs_regs_0_sva_cse[69:60];
+        regs_regs_slc_regs_regs_2_9_itm <= reg_regs_regs_0_sva_cse[89:80];
+        regs_regs_slc_regs_regs_2_4_itm <= reg_regs_regs_0_sva_cse[49:40];
+        regs_regs_slc_regs_regs_2_5_itm <= reg_regs_regs_0_sva_cse[39:30];
+        regs_regs_slc_regs_regs_2_3_itm <= reg_regs_regs_0_sva_cse[59:50];
+        regs_regs_slc_regs_regs_2_itm <= reg_regs_regs_0_sva_cse[29:20];
+        regs_regs_slc_regs_regs_2_1_itm <= reg_regs_regs_0_sva_cse[19:10];
+        regs_regs_slc_regs_regs_2_2_itm <= reg_regs_regs_0_sva_cse[9:0];
+        reg_regs_regs_0_sva_cse <= vin_rsc_mgc_in_wire_d;
+      end
+    end
+  end
+  assign nl_ACC1_acc_659_itm_1  = conv_s2s_12_13(conv_s2s_11_12({(ACC1_1_acc_25_psp_sva[11])
+      , 2'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11]) ,
+      1'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_224_psp_sva[0])})
+      + conv_u2s_11_12({conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[9])
+      + conv_u2u_1_2(acc_psp_1_sva[9])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[8]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[8])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[8]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[8])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[9]))
+      + conv_u2u_1_4(acc_psp_2_sva[9])) * 8'b10101) , (ACC1_acc_227_psp_sva[4]) ,
+      (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_s2s_12_13(conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_psp_2_sva[9]) , 1'b0
+      , (acc_psp_2_sva[9]) , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_2_sva[7]) , 1'b0 , (acc_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~ (ACC1_acc_338_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_338_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_210_psp_2_sva[3]) ,
+      (acc_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_220_psp_1_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_2_sva[3])
+      , (acc_psp_2_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_210_psp_2_sva[3]) ,
+      (acc_psp_2_sva[2]) , (ACC1_acc_210_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_2_sva[7])
+      , (acc_psp_2_sva[4]) , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_673_cse)))
+      + conv_u2s_7_8({(acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])
+      , 1'b0 , (acc_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_2_sva[6])
+      , 1'b0 , (acc_psp_2_sva[6]) , 1'b0 , (acc_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_673_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , ACC1_1_and_3_cse_sva}))))))))))
+      + ({(acc_psp_2_sva[11]) , 2'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11])
+      , 1'b0 , (acc_psp_2_sva[11]) , (conv_u2u_1_3(acc_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])))}))
+      + conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_20_psp_2_sva[10]) , 1'b0
+      , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10])
+      , 1'b0 , (acc_20_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_20_psp_2_sva[9]) ,
+      1'b0 , (acc_20_psp_2_sva[9]) , 1'b0 , (acc_20_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_20_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_20_psp_2_sva[7]) , 1'b0 , (acc_20_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_20_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~((ACC1_acc_359_itm[2])
+      & (~ (acc_20_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~ (ACC1_acc_358_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (ACC1_acc_358_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (ACC1_acc_217_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_20_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_217_psp_2_sva[3])
+      , (acc_20_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_223_psp_1_sva[2:1])) +
+      (readslicef_5_4_1((conv_u2s_3_5({(acc_20_psp_2_sva[3]) , (acc_20_psp_2_sva[1])
+      , 1'b1}) + conv_s2s_3_5({(ACC1_acc_217_psp_2_sva[3]) , (acc_20_psp_2_sva[2])
+      , (ACC1_acc_217_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_20_psp_2_sva[7])
+      , (acc_20_psp_2_sva[4]) , (signext_2_1(acc_20_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_699_cse)))
+      + conv_u2s_7_8({(acc_20_psp_2_sva[8]) , 1'b0 , (acc_20_psp_2_sva[8]) , 1'b0
+      , (acc_20_psp_2_sva[8]) , 1'b0 , (acc_20_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_20_psp_2_sva[11])
+      , (signext_2_1(acc_20_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_20_psp_2_sva[6])
+      , 1'b0 , (acc_20_psp_2_sva[6]) , 1'b0 , (acc_20_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_699_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[9]) , ((acc_20_psp_2_sva[11])
+      & (~ (ACC1_acc_359_itm[2])) & (ACC1_acc_359_itm[1]))})))))))))) + ({(acc_20_psp_2_sva[11])
+      , 2'b0 , (acc_20_psp_2_sva[11]) , 1'b0 , (acc_20_psp_2_sva[11]) , 1'b0 , (acc_20_psp_2_sva[11])
+      , (conv_u2u_1_3(acc_20_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])))})));
+  assign nl_ACC1_acc_658_itm_1  = conv_s2s_12_13(conv_s2s_10_12(conv_s2s_9_10(conv_u2s_7_9(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(ACC1_acc_224_psp_1_sva[6])
+      , (ACC1_acc_228_psp_sva[3]) , (signext_2_1(ACC1_acc_224_psp_sva[11]))}) + conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[5])
+      , (ACC1_acc_226_psp_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})) +
+      conv_u2u_5_6(conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[7]) , (ACC1_acc_224_psp_1_sva[3])
+      , (signext_2_1(ACC1_acc_228_psp_sva[11]))}) + conv_u2u_4_5({(acc_20_psp_1_sva[4])
+      , (ACC1_1_acc_25_psp_sva[4]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(~ (ACC1_acc_217_psp_1_sva[3])) ,
+      (~ (ACC1_acc_210_psp_1_sva[3])) , 1'b1 , (~ (ACC1_acc_367_itm[3]))}) + conv_u2u_4_5({(acc_psp_2_sva[5])
+      , (acc_20_psp_1_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})) + conv_s2u_5_6(conv_u2s_3_5(readslicef_4_3_1((conv_u2u_3_4({((acc_20_psp_1_sva[11])
+      & (~ (ACC1_acc_424_itm[2])) & (ACC1_acc_424_itm[1])) , (ACC1_acc_224_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_3_4({(acc_psp_2_sva[3]) , (ACC1_acc_224_psp_1_sva[2]) ,
+      (ACC1_1_acc_25_psp_sva[2])})))) + conv_s2s_3_5({(ACC1_acc_223_psp_sva[2:1])
+      , (ACC1_acc_224_psp_1_sva[3])})))) + conv_s2s_7_9(conv_s2s_6_7(conv_s2s_4_6(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_s2s_3_5({(ACC1_acc_220_psp_1_sva[2:1]) , (ACC1_acc_377_itm[2])}))))
+      + conv_u2s_4_6({(ACC1_acc_224_psp_1_sva[4]) , (ACC1_acc_224_psp_sva[3]) , (signext_2_1(ACC1_acc_224_psp_sva[11]))}))
+      + conv_s2s_6_7(conv_u2s_4_6({(acc_psp_2_sva[7]) , (acc_psp_2_sva[4]) , (signext_2_1(ACC1_acc_228_psp_sva[6]))})
+      + conv_s2s_3_6(conv_s2s_2_3(ACC1_acc_220_psp_sva[2:1]) + conv_s2s_2_3(ACC1_acc_222_psp_sva[2:1])))))
+      + conv_u2s_9_10({(acc_20_psp_1_sva[9]) , 1'b0 , (acc_20_psp_1_sva[9]) , 1'b0
+      , (acc_20_psp_1_sva[9]) , (ACC1_acc_228_psp_sva[4]) , 1'b0 , (signext_2_1(ACC1_acc_224_psp_sva[6]))}))
+      + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_4_10(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[8])
+      + conv_u2u_1_2(acc_psp_1_sva[8])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[7]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[7])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[7]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[7])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[8]))
+      + conv_u2u_1_4(acc_psp_2_sva[8])) * 10'b1010101))) + conv_u2s_12_14(conv_u2s_24_13(conv_u2u_4_12(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[10])
+      + conv_u2u_1_2(acc_psp_1_sva[10])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[9]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[9])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[9]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[9])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[10]))
+      + conv_u2u_1_4(acc_psp_2_sva[10])) * 12'b101010101));
+  assign nl_ACC1_acc_661_itm_1  = conv_s2s_13_14(conv_s2s_12_13({(ACC1_acc_226_psp_sva[11])
+      , 1'b0 , (ACC1_acc_226_psp_sva[11]) , 7'b0 , (ACC1_acc_226_psp_sva[11]) , (acc_psp_1_sva[2])})
+      + conv_u2s_12_13({conv_u2u_18_9(conv_u2u_3_9(conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_224_psp_sva[10])
+      + conv_u2u_1_2(ACC1_acc_228_psp_sva[10])) + conv_u2u_1_2(ACC1_acc_226_psp_sva[10]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[10])) * 9'b1010101) , (acc_psp_1_sva[4])
+      , (signext_2_1(ACC1_acc_224_psp_sva[4]))})) + conv_s2s_13_14(conv_s2s_26_13(conv_u2s_2_13((conv_u2u_1_2(ACC1_acc_227_psp_sva[11])
+      + conv_u2u_1_2(acc_psp_1_sva[11])) + conv_u2u_1_2(acc_psp_2_sva[11])) * 13'b1110010101001));
+  assign nl_ACC1_acc_652_itm_1  = conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[4])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[3])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_405_itm[2])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_3_acc_212_psp_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[5]) , (ACC1_3_acc_212_psp_sva[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_3_acc_212_psp_sva[1])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[9]) , ((ACC1_acc_226_psp_sva[11])
+      & (~ (ACC1_acc_387_itm[2])) & (ACC1_acc_387_itm[1]))})))))))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (~((ACC1_acc_387_itm[2])
+      & (~ (ACC1_acc_226_psp_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11]) , (ACC1_acc_386_itm[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11]) , (ACC1_acc_384_itm[4])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[5])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_384_itm[3])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (ACC1_acc_384_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , ((ACC1_acc_228_psp_sva[11])
+      & (~ (ACC1_acc_378_itm[2])) & (ACC1_acc_378_itm[1]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (~((ACC1_acc_378_itm[2])
+      & (~ (ACC1_acc_228_psp_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_375_itm[4])})))))))))
+      + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_375_itm[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , (ACC1_acc_375_itm[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ((ACC1_acc_224_psp_sva[11])
+      & (~ (ACC1_acc_415_itm[2])) & (ACC1_acc_415_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~((ACC1_acc_415_itm[2])
+      & (~ (ACC1_acc_224_psp_sva[11]))))}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_414_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_412_itm[4])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[5]) , (ACC1_acc_412_itm[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_412_itm[2])}))))))))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_227_psp_sva[3])
+      , (ACC1_acc_227_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(acc_psp_1_sva[3]) , (ACC1_acc_227_psp_sva[2])
+      , ((acc_psp_1_sva[11]) & (~ (ACC1_acc_396_itm[2])) & (ACC1_acc_396_itm[1]))}))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_224_psp_sva[2]) ,
+      (ACC1_acc_227_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[2])
+      , (ACC1_acc_227_psp_sva[4]) , (~((ACC1_acc_396_itm[2]) & (~ (acc_psp_1_sva[11]))))})))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_226_psp_sva[2])
+      , (acc_psp_1_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_224_psp_1_sva[2]) ,
+      (acc_psp_1_sva[3]) , (ACC1_acc_395_itm[2])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_1_acc_25_psp_sva[3])
+      , (acc_psp_1_sva[4]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[1]) , (ACC1_acc_224_psp_sva[1])
+      , (ACC1_acc_210_psp_1_sva[3])})))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[2])
+      , (ACC1_acc_224_psp_sva[2]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[3])
+      , (ACC1_acc_224_psp_sva[3]) , (ACC1_acc_210_psp_1_sva[2])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[4])
+      , (ACC1_acc_228_psp_sva[0]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[1])
+      , (ACC1_acc_226_psp_sva[0]) , (ACC1_acc_210_psp_1_sva[1])}))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[2])
+      , (ACC1_acc_226_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[3])
+      , (ACC1_acc_226_psp_sva[2]) , (ACC1_1_acc_25_psp_sva[4])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_423_itm[2])
+      , (ACC1_acc_226_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(~((ACC1_acc_424_itm[2])
+      & (~ (acc_20_psp_1_sva[11])))) , (ACC1_acc_224_psp_1_sva[0]) , (ACC1_1_acc_25_psp_sva[3])})))))))))
+      + conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_3_4({(acc_20_psp_1_sva[6]) , 1'b0 ,
+      (acc_20_psp_1_sva[6])}) + conv_u2u_3_4({(acc_psp_1_sva[7]) , (acc_20_psp_1_sva[5])
+      , (ACC1_acc_226_psp_sva[4])})) , (conv_u2u_2_3({(acc_20_psp_1_sva[6]) , (ACC1_acc_228_psp_sva[1])})
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[10])))}) + conv_u2u_7_8({(conv_u2u_3_4({(ACC1_acc_224_psp_sva[6])
+      , (acc_20_psp_1_sva[7]) , (ACC1_acc_226_psp_sva[6])}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[6])
+      , 1'b0 , (ACC1_acc_227_psp_sva[5])})) , ACC1_acc_724_cse}))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_1_2(ACC1_acc_226_psp_sva[6])
+      + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[6])) , (conv_u2u_1_2(ACC1_acc_227_psp_sva[7])
+      + conv_u2u_1_2(acc_psp_1_sva[5])) , ACC1_acc_724_cse}) + conv_u2u_7_8({(conv_u2u_1_2(ACC1_1_acc_25_psp_sva[7])
+      + conv_u2u_1_2(acc_psp_2_sva[7])) , (conv_u2u_1_2(acc_psp_1_sva[7]) + conv_u2u_1_2(ACC1_acc_224_psp_sva[4]))
+      , ACC1_acc_724_cse})) + conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_227_psp_sva[11])
+      , (signext_2_1(ACC1_acc_227_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_1_sva[11])
+      , (signext_2_1(acc_psp_1_sva[11]))}))))) + conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_sva[11])
+      , (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_228_psp_sva[11])
+      , (signext_2_1(ACC1_acc_228_psp_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(acc_20_psp_1_sva[11])
+      , 1'b0 , (signext_2_1(acc_20_psp_1_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_20_psp_1_sva[11])
+      , (signext_2_1(acc_20_psp_1_sva[11]))})))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_acc_226_psp_sva[11])
+      , 1'b0 , (signext_2_1(ACC1_acc_226_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_1_sva[11])
+      , (signext_2_1(ACC1_acc_224_psp_1_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b0 , (signext_2_1(ACC1_1_acc_25_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})))));
+  assign nl_ACC1_acc_655_itm_1  = conv_s2s_11_12(conv_u2s_10_11({(acc_20_psp_1_sva[10])
+      , 1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10])
+      , 1'b0 , (acc_20_psp_1_sva[10]) , (ACC1_acc_228_psp_sva[3])}) + conv_s2s_9_11(conv_s2s_8_9(({7'b1011011
+      , (ACC1_1_acc_25_psp_sva[1])}) + conv_u2s_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse)
+      + conv_u2u_3_4(ACC1_acc_509_cse)) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[5]))) + conv_u2u_3_4(ACC1_acc_506_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+      + conv_u2u_3_4(ACC1_acc_502_cse)))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+      + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[7]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[9]))
+      + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))))) + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+      + conv_u2u_4_5(ACC1_acc_562_ncse))))) + conv_u2s_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_502_cse)
+      + conv_u2u_3_4(ACC1_acc_506_cse)) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+      + conv_u2u_3_4(ACC1_acc_489_cse))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[6]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[8]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[10]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_u2u_4_5(ACC1_acc_553_ncse)))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_553_ncse) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_489_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[9]) , ACC1_1_and_3_cse_sva}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_338_itm[2])})))))))))
+      + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[1])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[9]) , (acc_psp_2_sva[4])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (acc_psp_2_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (acc_psp_2_sva[1])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , ((ACC1_acc_227_psp_sva[11])
+      & (~ (ACC1_acc_406_itm[2])) & (ACC1_acc_406_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[6])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[8]) , (~((ACC1_acc_406_itm[2])
+      & (~ (ACC1_acc_227_psp_sva[11]))))})))))))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[10])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , ((ACC1_1_acc_25_psp_sva[11])
+      & (~ (ACC1_acc_368_itm[2])) & (ACC1_acc_368_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (~((ACC1_acc_368_itm[2])
+      & (~ (ACC1_1_acc_25_psp_sva[11]))))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_acc_367_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_1_acc_208_psp_sva[3])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[4]) , (ACC1_1_acc_208_psp_sva[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_1_acc_208_psp_sva[1])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (~((ACC1_acc_349_itm[2])
+      & (~ (ACC1_acc_224_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[9]) , (ACC1_acc_348_itm[2])}))))))))))))
+      + conv_u2s_10_12(conv_u2u_8_10((conv_u2u_7_8({(acc_20_psp_1_sva[7]) , (ACC1_acc_227_psp_sva[7])
+      , 1'b0 , (ACC1_acc_224_psp_sva[6]) , 1'b0 , (signext_2_1(ACC1_acc_224_psp_sva[11]))})
+      + conv_u2u_6_8(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[10]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+      + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_516_cse) + conv_u2u_3_4(ACC1_acc_516_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+      + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))))))) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_412_itm[4])) , (~ (ACC1_acc_423_itm[3])) , (~ (ACC1_acc_338_itm[3]))})
+      + conv_u2u_3_4({(~ (ACC1_acc_375_itm[4])) , 1'b1 , (~ (ACC1_acc_395_itm[3]))}))
+      + conv_u2u_4_5({(readslicef_3_2_1((conv_u2u_2_3({(~ (ACC1_acc_384_itm[4]))
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_3_acc_212_psp_sva[3])) , 1'b1})))) , (({1'b1
+      , (~ (ACC1_acc_414_itm[3]))}) + ({1'b1 , (~ (ACC1_acc_377_itm[3]))}))})) +
+      conv_u2u_5_6(conv_u2u_4_5({(readslicef_3_2_1((conv_u2u_2_3({(~ (ACC1_acc_346_itm[4]))
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_208_psp_sva[3])) , 1'b1})))) , (({1'b1
+      , (~ (ACC1_acc_386_itm[3]))}) + ({1'b1 , (~ (ACC1_acc_405_itm[3]))}))}) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_210_psp_2_sva[3])) , 1'b1 , (~ (ACC1_acc_348_itm[3]))}) + conv_s2u_2_4(ACC1_acc_221_psp_sva[2:1]))))
+      + conv_s2u_6_7(conv_s2s_5_6(conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_221_psp_2_sva[2:1])
+      + conv_u2s_2_4(signext_2_1(ACC1_acc_228_psp_sva[8]))) + conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_219_psp_2_sva[2:1])
+      + conv_u2s_2_4(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_s2s_5_6(conv_s2s_4_5(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_s2s_3_5({(ACC1_acc_222_psp_1_sva[2:1]) , (acc_psp_2_sva[2])}))))
+      + conv_s2s_4_5(readslicef_5_4_1((conv_s2s_3_5({(ACC1_acc_219_psp_1_sva[2:1])
+      , 1'b1}) + conv_u2s_3_5(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , ((ACC1_acc_224_psp_1_sva[11])
+      & (~ (ACC1_acc_349_itm[2])) & (ACC1_acc_349_itm[1]))}))))))))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[6])
+      + conv_u2u_1_2(acc_psp_1_sva[6])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[5]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[5])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[5]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[5])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[6]))
+      + conv_u2u_1_4(acc_psp_2_sva[6])) * 8'b10101)) + conv_u2u_8_9({(acc_20_psp_1_sva[8])
+      , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0 , (acc_20_psp_1_sva[8])
+      , (ACC1_acc_228_psp_sva[2])})));
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [2:0] signext_3_2;
+    input [1:0] vector;
+  begin
+    signext_3_2= {{1{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_3;
+    input [2:0] vector;
+  begin
+    signext_7_3= {{4{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_4;
+    input [3:0] vector;
+  begin
+    signext_7_4= {{3{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_7_10 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_10 = {{3{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [14:0] conv_s2s_14_15 ;
+    input signed [13:0]  vector ;
+  begin
+    conv_s2s_14_15 = {vector[13], vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_13_14 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_14 = {vector[12], vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_2_14 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_14 = {{12{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_4_8 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_8 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_1_4 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_4 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_6_8 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_8 = {{2{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_9_10 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_10 = {vector[8], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_s2u_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2u_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_3_6 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_6 = {{3{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_4_10 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_10 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_24_13 ;
+    input [23:0]  vector ;
+  begin
+    conv_u2s_24_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_4_12 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_12 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_26_13 ;
+    input signed [25:0]  vector ;
+  begin
+    conv_s2s_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_9_11 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_11 = {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_8_9 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_9 = {vector[7], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_s2u_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2u_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_s2u_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2u_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v11/rtl.v.psr b/Sobel/sobel.v11/rtl.v.psr
new file mode 100644
index 0000000..9b19b07
--- /dev/null
+++ b/Sobel/sobel.v11/rtl.v.psr
@@ -0,0 +1,289 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v11/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v11/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v11/rtl.v}} -format verilog
+   setup_design -design=sobel
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'sobel': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'sobel': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'sobel'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'sobel'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to vout_rsc_z(29:0)
+   report_timing -from en -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from vin_rsc_z(89:0) -to vout_rsc_z(29:0)
+   report_timing -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock clk] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock en] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'sobel'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'sobel'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v11 mapped.v]
+          puts "-- Writing mapped netlist for 'sobel' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v11 gate.v]
+          set gate_sdf [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v11 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/Sobel/sobel.v11/rtl.v.psr_timing b/Sobel/sobel.v11/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/Sobel/sobel.v11/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/Sobel/sobel.v11/rtl.v_order.txt b/Sobel/sobel.v11/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/Sobel/sobel.v11/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/Sobel/sobel.v11/rtl_mgc_ioport.v b/Sobel/sobel.v11/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v11/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v11/rtl_mgc_ioport_v2001.v b/Sobel/sobel.v11/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v11/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v11/schedule.gnt b/Sobel/sobel.v11/schedule.gnt
new file mode 100644
index 0000000..b715e69
--- /dev/null
+++ b/Sobel/sobel.v11/schedule.gnt
@@ -0,0 +1,2358 @@
+set a(0-7005) {NAME FRAME:p:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-7004 XREFS 46715 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-7009 {}}} SUCCS {{258 0 0-7009 {}}} CYCLES {}}
+set a(0-7006) {NAME asn(regs.regs(1))#1 TYPE ASSIGN PAR 0-7004 XREFS 46716 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-7009 {}}} SUCCS {{258 0 0-7009 {}}} CYCLES {}}
+set a(0-7007) {NAME asn(regs.regs(0))#1 TYPE ASSIGN PAR 0-7004 XREFS 46717 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-7009 {}}} SUCCS {{258 0 0-7009 {}}} CYCLES {}}
+set a(0-7008) {NAME FRAME:asn(exit:FRAME) TYPE ASSIGN PAR 0-7004 XREFS 46718 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-7009 {}}} SUCCS {{259 0 0-7009 {}}} CYCLES {}}
+set a(0-7010) {NAME FRAME:asn TYPE ASSIGN PAR 0-7009 XREFS 46719 LOC {0 1.0 0 1.0 0 1.0 3 1.0} PREDS {{262 0 0-9355 {}}} SUCCS {{259 0 0-7011 {}} {256 0 0-9355 {}}} CYCLES {}}
+set a(0-7011) {NAME FRAME:select TYPE SELECT PAR 0-7009 XREFS 46720 LOC {0 1.0 0 1.0 0 1.0 3 1.0} PREDS {{259 0 0-7010 {}}} SUCCS {} CYCLES {}}
+set a(0-7012) {NAME SHIFT:if:else:else:else:asn(regs.regs(1)) TYPE ASSIGN PAR 0-7009 XREFS 46721 LOC {0 1.0 0 1.0 0 1.0 2 0.046457874999999996} PREDS {{262 0 0-9348 {}}} SUCCS {{256 0 0-9348 {}} {258 0 0-9349 {}}} CYCLES {}}
+set a(0-7013) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,90) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_read(vin:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-7009 XREFS 46722 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {} SUCCS {{259 0 0-7014 {}} {258 0 0-7016 {}} {258 0 0-7019 {}} {258 0 0-7099 {}} {258 0 0-7101 {}} {258 0 0-7104 {}} {258 0 0-7172 {}} {258 0 0-7174 {}} {258 0 0-7177 {}} {258 0 0-7248 {}} {258 0 0-7249 {}} {258 0 0-7251 {}} {258 0 0-9348 {}}} CYCLES {}}
+set a(0-7014) {NAME regs.regs:slc(regs.regs(0))#6 TYPE READSLICE PAR 0-7009 XREFS 46723 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-7013 {}}} SUCCS {{259 0 0-7015 {}}} CYCLES {}}
+set a(0-7015) {NAME {regs.operator[]:not} TYPE NOT PAR 0-7009 XREFS 46724 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-7014 {}}} SUCCS {{258 0 0-7018 {}}} CYCLES {}}
+set a(0-7016) {NAME regs.regs:slc(regs.regs(0))#7 TYPE READSLICE PAR 0-7009 XREFS 46725 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{258 0 0-7013 {}}} SUCCS {{259 0 0-7017 {}}} CYCLES {}}
+set a(0-7017) {NAME {regs.operator[]#1:not} TYPE NOT PAR 0-7009 XREFS 46726 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-7016 {}}} SUCCS {{259 0 0-7018 {}}} CYCLES {}}
+set a(0-7018) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#331 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 46727 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.09544225333641132 1 0.1749305033364113} PREDS {{258 0 0-7015 {}} {259 0 0-7017 {}}} SUCCS {{258 0 0-7022 {}}} CYCLES {}}
+set a(0-7019) {NAME regs.regs:slc(regs.regs(0))#8 TYPE READSLICE PAR 0-7009 XREFS 46728 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{258 0 0-7013 {}}} SUCCS {{259 0 0-7020 {}}} CYCLES {}}
+set a(0-7020) {NAME {regs.operator[]#2:not} TYPE NOT PAR 0-7009 XREFS 46729 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-7019 {}}} SUCCS {{259 0 0-7021 {}}} CYCLES {}}
+set a(0-7021) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#330 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 46730 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.09544225333641132 1 0.1749305033364113} PREDS {{259 0 0-7020 {}}} SUCCS {{259 0 0-7022 {}}} CYCLES {}}
+set a(0-7022) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-1:acc TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 46731 LOC {1 0.07118415 1 0.0954423 1 0.0954423 1 0.17081305637342836 1 0.25030130637342834} PREDS {{258 0 0-7018 {}} {259 0 0-7021 {}}} SUCCS {{259 0 0-7023 {}} {258 0 0-7026 {}} {258 0 0-7028 {}} {258 0 0-7033 {}} {258 0 0-7035 {}} {258 0 0-7039 {}} {258 0 0-7041 {}} {258 0 0-7043 {}} {258 0 0-7049 {}} {258 0 0-7051 {}} {258 0 0-7053 {}} {258 0 0-7057 {}} {258 0 0-7091 {}} {258 0 0-7094 {}} {258 0 0-7789 {}} {258 0 0-7797 {}} {258 0 0-7798 {}} {258 0 0-7799 {}} {258 0 0-7800 {}} {258 0 0-7801 {}} {258 0 0-7803 {}} {258 0 0-7804 {}} {258 0 0-7805 {}} {258 0 0-7806 {}} {258 0 0-7809 {}} {258 0 0-7810 {}} {258 0 0-7811 {}} {258 0 0-7814 {}} {258 0 0-7817 {}} {258 0 0-7822 {}} {258 0 0-7825 {}} {258 0 0-7833 {}} {258 0 0-7836 {}} {258 0 0-7842 {}} {258 0 0-7845 {}} {258 0 0-7856 {}} {258 0 0-7860 {}} {258 0 0-7866 {}} {258 0 0-7867 {}} {258 0 0-7871 {}} {258 0 0-7878 {}} {258 0 0-7879 {}} {258 0 0-7880 {}} {258 0 0-7883 {}} {258 0 0-7885 {}} {258 0 0-7890 {}} {258 0 0-7891 {}} {258 0 0-7892 {}} {258 0 0-7893 {}} {258 0 0-7896 {}} {258 0 0-7897 {}} {258 0 0-7901 {}} {258 0 0-7902 {}} {258 0 0-7903 {}} {258 0 0-7905 {}} {258 0 0-7907 {}} {258 0 0-7910 {}} {258 0 0-7913 {}} {258 0 0-7923 {}} {258 0 0-7924 {}} {258 0 0-7926 {}} {258 0 0-7927 {}} {258 0 0-7928 {}} {258 0 0-7929 {}} {258 0 0-7930 {}} {258 0 0-8114 {}} {258 0 0-8128 {}} {258 0 0-8155 {}} {258 0 0-8156 {}} {258 0 0-8187 {}} {258 0 0-8204 {}} {258 0 0-8230 {}} {258 0 0-8409 {}} {258 0 0-8412 {}} {258 0 0-8422 {}} {258 0 0-8425 {}} {258 0 0-8431 {}} {258 0 0-8434 {}} {258 0 0-8441 {}} {258 0 0-8444 {}} {258 0 0-8454 {}} {258 0 0-8457 {}} {258 0 0-8468 {}} {258 0 0-8471 {}} {258 0 0-8477 {}} {258 0 0-8480 {}} {258 0 0-8487 {}} {258 0 0-8490 {}} {258 0 0-8496 {}} {258 0 0-8499 {}} {258 0 0-8657 {}} {258 0 0-8716 {}} {258 0 0-8717 {}} {258 0 0-8969 {}} {258 0 0-8980 {}} {258 0 0-8989 {}} {258 0 0-9227 {}} {258 0 0-9260 {}}} CYCLES {}}
+set a(0-7023) {NAME ACC1-1:slc(acc.psp)#11 TYPE READSLICE PAR 0-7009 XREFS 46732 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.274975825} PREDS {{259 0 0-7022 {}}} SUCCS {{259 0 0-7024 {}}} CYCLES {}}
+set a(0-7024) {NAME ACC1-1:not#302 TYPE NOT PAR 0-7009 XREFS 46733 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{259 0 0-7023 {}}} SUCCS {{259 0 0-7025 {}}} CYCLES {}}
+set a(0-7025) {NAME ACC1:conc#1132 TYPE CONCATENATE PAR 0-7009 XREFS 46734 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{259 0 0-7024 {}}} SUCCS {{258 0 0-7030 {}}} CYCLES {}}
+set a(0-7026) {NAME ACC1-1:slc(acc.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 46735 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.274975825} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7027 {}}} CYCLES {}}
+set a(0-7027) {NAME ACC1-1:not#229 TYPE NOT PAR 0-7009 XREFS 46736 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{259 0 0-7026 {}}} SUCCS {{258 0 0-7029 {}}} CYCLES {}}
+set a(0-7028) {NAME ACC1-1:slc(acc.psp)#8 TYPE READSLICE PAR 0-7009 XREFS 46737 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.274975825} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7029 {}}} CYCLES {}}
+set a(0-7029) {NAME ACC1:conc#1133 TYPE CONCATENATE PAR 0-7009 XREFS 46738 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{258 0 0-7027 {}} {259 0 0-7028 {}}} SUCCS {{259 0 0-7030 {}}} CYCLES {}}
+set a(0-7030) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#334 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 46739 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.21596033508947524 1 0.29544858508947525} PREDS {{258 0 0-7025 {}} {259 0 0-7029 {}}} SUCCS {{259 0 0-7031 {}}} CYCLES {}}
+set a(0-7031) {NAME ACC1:slc#15 TYPE READSLICE PAR 0-7009 XREFS 46740 LOC {1 0.16702775 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{259 0 0-7030 {}}} SUCCS {{259 0 0-7032 {}}} CYCLES {}}
+set a(0-7032) {NAME ACC1:conc#1136 TYPE CONCATENATE PAR 0-7009 XREFS 46741 LOC {1 0.16702775 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{259 0 0-7031 {}}} SUCCS {{258 0 0-7037 {}}} CYCLES {}}
+set a(0-7033) {NAME ACC1-1:slc(acc.psp) TYPE READSLICE PAR 0-7009 XREFS 46742 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.29544862499999996} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7034 {}}} CYCLES {}}
+set a(0-7034) {NAME ACC1:conc#1127 TYPE CONCATENATE PAR 0-7009 XREFS 46743 LOC {1 0.14655495 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{259 0 0-7033 {}}} SUCCS {{258 0 0-7036 {}}} CYCLES {}}
+set a(0-7035) {NAME ACC1-1:slc(acc.psp)#10 TYPE READSLICE PAR 0-7009 XREFS 46744 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.29544862499999996} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7036 {}}} CYCLES {}}
+set a(0-7036) {NAME ACC1:conc#1137 TYPE CONCATENATE PAR 0-7009 XREFS 46745 LOC {1 0.14655495 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{258 0 0-7034 {}} {259 0 0-7035 {}}} SUCCS {{259 0 0-7037 {}}} CYCLES {}}
+set a(0-7037) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#336 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 46746 LOC {1 0.16702775 1 0.21596037499999998 1 0.21596037499999998 1 0.2591522701789505 1 0.33864052017895047} PREDS {{258 0 0-7032 {}} {259 0 0-7036 {}}} SUCCS {{259 0 0-7038 {}}} CYCLES {}}
+set a(0-7038) {NAME ACC1:slc#17 TYPE READSLICE PAR 0-7009 XREFS 46747 LOC {1 0.21021969999999998 1 0.25915232499999996 1 0.25915232499999996 1 0.338640575} PREDS {{259 0 0-7037 {}}} SUCCS {{258 0 0-7062 {}}} CYCLES {}}
+set a(0-7039) {NAME ACC1-1:slc(acc.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 46748 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7040 {}}} CYCLES {}}
+set a(0-7040) {NAME ACC1:conc#1130 TYPE CONCATENATE PAR 0-7009 XREFS 46749 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-7039 {}}} SUCCS {{258 0 0-7046 {}}} CYCLES {}}
+set a(0-7041) {NAME ACC1-1:slc(acc.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 46750 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7042 {}}} CYCLES {}}
+set a(0-7042) {NAME ACC1-1:not#230 TYPE NOT PAR 0-7009 XREFS 46751 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-7041 {}}} SUCCS {{258 0 0-7045 {}}} CYCLES {}}
+set a(0-7043) {NAME ACC1-1:slc(acc.psp)#7 TYPE READSLICE PAR 0-7009 XREFS 46752 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7044 {}}} CYCLES {}}
+set a(0-7044) {NAME ACC1-1:not#232 TYPE NOT PAR 0-7009 XREFS 46753 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-7043 {}}} SUCCS {{259 0 0-7045 {}}} CYCLES {}}
+set a(0-7045) {NAME ACC1:conc#1131 TYPE CONCATENATE PAR 0-7009 XREFS 46754 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7042 {}} {259 0 0-7044 {}}} SUCCS {{259 0 0-7046 {}}} CYCLES {}}
+set a(0-7046) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#333 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 46755 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.21159611008947524 1 0.29108436008947525} PREDS {{258 0 0-7040 {}} {259 0 0-7045 {}}} SUCCS {{259 0 0-7047 {}}} CYCLES {}}
+set a(0-7047) {NAME ACC1:slc#14 TYPE READSLICE PAR 0-7009 XREFS 46756 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-7046 {}}} SUCCS {{259 0 0-7048 {}}} CYCLES {}}
+set a(0-7048) {NAME ACC1:conc#1134 TYPE CONCATENATE PAR 0-7009 XREFS 46757 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-7047 {}}} SUCCS {{258 0 0-7060 {}}} CYCLES {}}
+set a(0-7049) {NAME ACC1-1:slc(acc.psp)#4 TYPE READSLICE PAR 0-7009 XREFS 46758 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7050 {}}} CYCLES {}}
+set a(0-7050) {NAME ACC1:conc#1128 TYPE CONCATENATE PAR 0-7009 XREFS 46759 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-7049 {}}} SUCCS {{258 0 0-7055 {}}} CYCLES {}}
+set a(0-7051) {NAME ACC1-1:slc(acc.psp)#5 TYPE READSLICE PAR 0-7009 XREFS 46760 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7052 {}}} CYCLES {}}
+set a(0-7052) {NAME ACC1-1:not#231 TYPE NOT PAR 0-7009 XREFS 46761 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-7051 {}}} SUCCS {{258 0 0-7054 {}}} CYCLES {}}
+set a(0-7053) {NAME ACC1-1:slc(acc.psp)#6 TYPE READSLICE PAR 0-7009 XREFS 46762 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7054 {}}} CYCLES {}}
+set a(0-7054) {NAME ACC1:conc#1129 TYPE CONCATENATE PAR 0-7009 XREFS 46763 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7052 {}} {259 0 0-7053 {}}} SUCCS {{259 0 0-7055 {}}} CYCLES {}}
+set a(0-7055) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#332 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 46764 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.21159611008947524 1 0.29108436008947525} PREDS {{258 0 0-7050 {}} {259 0 0-7054 {}}} SUCCS {{259 0 0-7056 {}}} CYCLES {}}
+set a(0-7056) {NAME ACC1:slc#13 TYPE READSLICE PAR 0-7009 XREFS 46765 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-7055 {}}} SUCCS {{258 0 0-7059 {}}} CYCLES {}}
+set a(0-7057) {NAME ACC1-1:slc(acc.psp)#9 TYPE READSLICE PAR 0-7009 XREFS 46766 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.29108439999999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7058 {}}} CYCLES {}}
+set a(0-7058) {NAME ACC1-1:not#233 TYPE NOT PAR 0-7009 XREFS 46767 LOC {1 0.14655495 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-7057 {}}} SUCCS {{259 0 0-7059 {}}} CYCLES {}}
+set a(0-7059) {NAME ACC1:conc#1135 TYPE CONCATENATE PAR 0-7009 XREFS 46768 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{258 0 0-7056 {}} {259 0 0-7058 {}}} SUCCS {{259 0 0-7060 {}}} CYCLES {}}
+set a(0-7060) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#335 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 46769 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.25915227707082716 1 0.33864052707082715} PREDS {{258 0 0-7048 {}} {259 0 0-7059 {}}} SUCCS {{259 0 0-7061 {}}} CYCLES {}}
+set a(0-7061) {NAME ACC1:slc#16 TYPE READSLICE PAR 0-7009 XREFS 46770 LOC {1 0.23489417499999998 1 0.25915232499999996 1 0.25915232499999996 1 0.338640575} PREDS {{259 0 0-7060 {}}} SUCCS {{259 0 0-7062 {}}} CYCLES {}}
+set a(0-7062) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1-1:acc#210 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 46771 LOC {1 0.23489417499999998 1 0.25915232499999996 1 0.25915232499999996 1 0.2921890951789505 1 0.3716773451789505} PREDS {{258 0 0-7038 {}} {259 0 0-7061 {}}} SUCCS {{259 0 0-7063 {}} {258 0 0-7065 {}} {258 0 0-7067 {}} {258 0 0-7071 {}} {258 0 0-7847 {}} {258 0 0-7859 {}} {258 0 0-7870 {}} {258 0 0-7873 {}} {258 0 0-8941 {}} {258 0 0-8950 {}} {258 0 0-8960 {}} {258 0 0-9205 {}}} CYCLES {}}
+set a(0-7063) {NAME ACC1-1:slc(ACC1:acc#210.psp) TYPE READSLICE PAR 0-7009 XREFS 46772 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{259 0 0-7062 {}}} SUCCS {{259 0 0-7064 {}}} CYCLES {}}
+set a(0-7064) {NAME ACC1:conc#1138 TYPE CONCATENATE PAR 0-7009 XREFS 46773 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{259 0 0-7063 {}}} SUCCS {{258 0 0-7069 {}}} CYCLES {}}
+set a(0-7065) {NAME ACC1-1:slc(ACC1:acc#210.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 46774 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{258 0 0-7062 {}}} SUCCS {{259 0 0-7066 {}}} CYCLES {}}
+set a(0-7066) {NAME ACC1-1:not#273 TYPE NOT PAR 0-7009 XREFS 46775 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{259 0 0-7065 {}}} SUCCS {{258 0 0-7068 {}}} CYCLES {}}
+set a(0-7067) {NAME ACC1-1:slc(ACC1:acc#210.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 46776 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{258 0 0-7062 {}}} SUCCS {{259 0 0-7068 {}}} CYCLES {}}
+set a(0-7068) {NAME ACC1:conc#1139 TYPE CONCATENATE PAR 0-7009 XREFS 46777 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{258 0 0-7066 {}} {259 0 0-7067 {}}} SUCCS {{259 0 0-7069 {}}} CYCLES {}}
+set a(0-7069) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#337 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 46778 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3329721600894753 1 0.4124604100894752} PREDS {{258 0 0-7064 {}} {259 0 0-7068 {}}} SUCCS {{259 0 0-7070 {}}} CYCLES {}}
+set a(0-7070) {NAME ACC1:slc#18 TYPE READSLICE PAR 0-7009 XREFS 46779 LOC {1 0.30871404999999996 1 0.3329722 1 0.3329722 1 0.41246045} PREDS {{259 0 0-7069 {}}} SUCCS {{258 0 0-7073 {}}} CYCLES {}}
+set a(0-7071) {NAME ACC1-1:slc(ACC1:acc#210.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 46780 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.41246045} PREDS {{258 0 0-7062 {}}} SUCCS {{259 0 0-7072 {}}} CYCLES {}}
+set a(0-7072) {NAME ACC1-1:not#305 TYPE NOT PAR 0-7009 XREFS 46781 LOC {1 0.267931 1 0.3329722 1 0.3329722 1 0.41246045} PREDS {{259 0 0-7071 {}}} SUCCS {{259 0 0-7073 {}}} CYCLES {}}
+set a(0-7073) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-1:acc#220 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 46782 LOC {1 0.30871404999999996 1 0.3329722 1 0.3329722 1 0.35344496008947524 1 0.4329332100894752} PREDS {{258 0 0-7070 {}} {259 0 0-7072 {}}} SUCCS {{259 0 0-7074 {}} {258 0 0-7077 {}} {258 0 0-7864 {}} {258 0 0-8144 {}}} CYCLES {}}
+set a(0-7074) {NAME ACC1-1:slc(ACC1:acc#220.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 46783 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-7073 {}}} SUCCS {{259 0 0-7075 {}}} CYCLES {}}
+set a(0-7075) {NAME ACC1-1:not#293 TYPE NOT PAR 0-7009 XREFS 46784 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-7074 {}}} SUCCS {{259 0 0-7076 {}}} CYCLES {}}
+set a(0-7076) {NAME ACC1:conc#1140 TYPE CONCATENATE PAR 0-7009 XREFS 46785 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-7075 {}}} SUCCS {{258 0 0-7079 {}}} CYCLES {}}
+set a(0-7077) {NAME ACC1-1:slc(ACC1:acc#220.psp) TYPE READSLICE PAR 0-7009 XREFS 46786 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{258 0 0-7073 {}}} SUCCS {{259 0 0-7078 {}}} CYCLES {}}
+set a(0-7078) {NAME ACC1:conc#1141 TYPE CONCATENATE PAR 0-7009 XREFS 46787 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-7077 {}}} SUCCS {{259 0 0-7079 {}}} CYCLES {}}
+set a(0-7079) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#338 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 46788 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.38069087707082716 1 0.4601791270708272} PREDS {{258 0 0-7076 {}} {259 0 0-7078 {}}} SUCCS {{259 0 0-7080 {}}} CYCLES {}}
+set a(0-7080) {NAME ACC1:slc#19 TYPE READSLICE PAR 0-7009 XREFS 46789 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-7079 {}}} SUCCS {{259 0 0-7081 {}} {258 0 0-7083 {}} {258 0 0-7085 {}} {258 0 0-7827 {}} {258 0 0-7838 {}} {258 0 0-8928 {}} {258 0 0-9173 {}}} CYCLES {}}
+set a(0-7081) {NAME ACC1-1:slc(acc.imod#2) TYPE READSLICE PAR 0-7009 XREFS 46790 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-7080 {}}} SUCCS {{259 0 0-7082 {}}} CYCLES {}}
+set a(0-7082) {NAME ACC1:conc#1143 TYPE CONCATENATE PAR 0-7009 XREFS 46791 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-7081 {}}} SUCCS {{258 0 0-7088 {}}} CYCLES {}}
+set a(0-7083) {NAME ACC1-1:slc(acc.imod#2)#1 TYPE READSLICE PAR 0-7009 XREFS 46792 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{258 0 0-7080 {}}} SUCCS {{259 0 0-7084 {}}} CYCLES {}}
+set a(0-7084) {NAME ACC1-1:not#25 TYPE NOT PAR 0-7009 XREFS 46793 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-7083 {}}} SUCCS {{258 0 0-7087 {}}} CYCLES {}}
+set a(0-7085) {NAME ACC1-1:slc(acc.imod#2)#2 TYPE READSLICE PAR 0-7009 XREFS 46794 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{258 0 0-7080 {}}} SUCCS {{259 0 0-7086 {}}} CYCLES {}}
+set a(0-7086) {NAME ACC1-1:not#26 TYPE NOT PAR 0-7009 XREFS 46795 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-7085 {}}} SUCCS {{259 0 0-7087 {}}} CYCLES {}}
+set a(0-7087) {NAME ACC1:conc#1144 TYPE CONCATENATE PAR 0-7009 XREFS 46796 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{258 0 0-7084 {}} {259 0 0-7086 {}}} SUCCS {{259 0 0-7088 {}}} CYCLES {}}
+set a(0-7088) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#339 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 46797 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.40793680207082716 1 0.4874250520708272} PREDS {{258 0 0-7082 {}} {259 0 0-7087 {}}} SUCCS {{259 0 0-7089 {}}} CYCLES {}}
+set a(0-7089) {NAME ACC1:slc#20 TYPE READSLICE PAR 0-7009 XREFS 46798 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7088 {}}} SUCCS {{259 0 0-7090 {}} {258 0 0-7095 {}} {258 0 0-7097 {}}} CYCLES {}}
+set a(0-7090) {NAME ACC1-1:slc(acc.imod#7) TYPE READSLICE PAR 0-7009 XREFS 46799 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7089 {}}} SUCCS {{258 0 0-7093 {}}} CYCLES {}}
+set a(0-7091) {NAME ACC1-1:slc(acc.idiv#1)#44 TYPE READSLICE PAR 0-7009 XREFS 46800 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7092 {}}} CYCLES {}}
+set a(0-7092) {NAME ACC1-1:not#59 TYPE NOT PAR 0-7009 XREFS 46801 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7091 {}}} SUCCS {{259 0 0-7093 {}}} CYCLES {}}
+set a(0-7093) {NAME ACC1-1:nand#1 TYPE NAND PAR 0-7009 XREFS 46802 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-7090 {}} {259 0 0-7092 {}}} SUCCS {{258 0 0-7819 {}} {258 0 0-8920 {}}} CYCLES {}}
+set a(0-7094) {NAME ACC1-1:slc(acc.idiv#1)#45 TYPE READSLICE PAR 0-7009 XREFS 46803 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5545639} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7098 {}}} CYCLES {}}
+set a(0-7095) {NAME ACC1-1:slc(acc.imod#7)#1 TYPE READSLICE PAR 0-7009 XREFS 46804 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{258 0 0-7089 {}}} SUCCS {{259 0 0-7096 {}}} CYCLES {}}
+set a(0-7096) {NAME ACC1-1:not#60 TYPE NOT PAR 0-7009 XREFS 46805 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{259 0 0-7095 {}}} SUCCS {{258 0 0-7098 {}}} CYCLES {}}
+set a(0-7097) {NAME ACC1-1:slc(acc.imod#7)#2 TYPE READSLICE PAR 0-7009 XREFS 46806 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{258 0 0-7089 {}}} SUCCS {{259 0 0-7098 {}}} CYCLES {}}
+set a(0-7098) {NAME ACC1-1:and#3 TYPE AND PAR 0-7009 XREFS 46807 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{258 0 0-7096 {}} {258 0 0-7094 {}} {259 0 0-7097 {}}} SUCCS {{258 0 0-7915 {}} {258 0 0-8911 {}}} CYCLES {}}
+set a(0-7099) {NAME regs.regs:slc(regs.regs(0))#3 TYPE READSLICE PAR 0-7009 XREFS 46808 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.17147225} PREDS {{258 0 0-7013 {}}} SUCCS {{259 0 0-7100 {}}} CYCLES {}}
+set a(0-7100) {NAME ACC1:not TYPE NOT PAR 0-7009 XREFS 46809 LOC {1 0.0 1 0.098043075 1 0.098043075 1 0.17147225} PREDS {{259 0 0-7099 {}}} SUCCS {{258 0 0-7103 {}}} CYCLES {}}
+set a(0-7101) {NAME regs.regs:slc(regs.regs(0))#4 TYPE READSLICE PAR 0-7009 XREFS 46810 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.17147225} PREDS {{258 0 0-7013 {}}} SUCCS {{259 0 0-7102 {}}} CYCLES {}}
+set a(0-7102) {NAME ACC1:not#307 TYPE NOT PAR 0-7009 XREFS 46811 LOC {1 0.0 1 0.098043075 1 0.098043075 1 0.17147225} PREDS {{259 0 0-7101 {}}} SUCCS {{259 0 0-7103 {}}} CYCLES {}}
+set a(0-7103) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#341 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 46812 LOC {1 0.0 1 0.098043075 1 0.098043075 1 0.16922717833641132 1 0.2426563533364113} PREDS {{258 0 0-7100 {}} {259 0 0-7102 {}}} SUCCS {{258 0 0-7107 {}}} CYCLES {}}
+set a(0-7104) {NAME regs.regs:slc(regs.regs(0))#5 TYPE READSLICE PAR 0-7009 XREFS 46813 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.17147225} PREDS {{258 0 0-7013 {}}} SUCCS {{259 0 0-7105 {}}} CYCLES {}}
+set a(0-7105) {NAME ACC1:not#308 TYPE NOT PAR 0-7009 XREFS 46814 LOC {1 0.0 1 0.098043075 1 0.098043075 1 0.17147225} PREDS {{259 0 0-7104 {}}} SUCCS {{259 0 0-7106 {}}} CYCLES {}}
+set a(0-7106) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#340 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 46815 LOC {1 0.0 1 0.098043075 1 0.098043075 1 0.16922717833641132 1 0.2426563533364113} PREDS {{259 0 0-7105 {}}} SUCCS {{259 0 0-7107 {}}} CYCLES {}}
+set a(0-7107) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-1:acc#224 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 46816 LOC {1 0.07118415 1 0.16922722499999998 1 0.16922722499999998 1 0.24459798137342836 1 0.3180271563734284} PREDS {{258 0 0-7103 {}} {259 0 0-7106 {}}} SUCCS {{259 0 0-7108 {}} {258 0 0-7111 {}} {258 0 0-7113 {}} {258 0 0-7115 {}} {258 0 0-7120 {}} {258 0 0-7126 {}} {258 0 0-7128 {}} {258 0 0-7130 {}} {258 0 0-7135 {}} {258 0 0-7137 {}} {258 0 0-7141 {}} {258 0 0-7785 {}} {258 0 0-8084 {}} {258 0 0-8096 {}} {258 0 0-8125 {}} {258 0 0-8129 {}} {258 0 0-8136 {}} {258 0 0-8149 {}} {258 0 0-8183 {}} {258 0 0-8200 {}} {258 0 0-8219 {}} {258 0 0-8238 {}} {258 0 0-8542 {}} {258 0 0-8604 {}} {258 0 0-8646 {}} {258 0 0-8705 {}} {258 0 0-8706 {}} {258 0 0-8984 {}} {258 0 0-8987 {}} {258 0 0-8994 {}} {258 0 0-8997 {}} {258 0 0-9007 {}} {258 0 0-9010 {}} {258 0 0-9022 {}} {258 0 0-9025 {}} {258 0 0-9035 {}} {258 0 0-9038 {}} {258 0 0-9048 {}} {258 0 0-9051 {}} {258 0 0-9057 {}} {258 0 0-9060 {}} {258 0 0-9068 {}} {258 0 0-9071 {}} {258 0 0-9077 {}} {258 0 0-9080 {}} {258 0 0-9093 {}} {258 0 0-9235 {}} {258 0 0-9256 {}}} CYCLES {}}
+set a(0-7108) {NAME ACC1-1:slc(acc#10.psp)#39 TYPE READSLICE PAR 0-7009 XREFS 46817 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.35881025} PREDS {{259 0 0-7107 {}}} SUCCS {{259 0 0-7109 {}}} CYCLES {}}
+set a(0-7109) {NAME ACC1-1:not#247 TYPE NOT PAR 0-7009 XREFS 46818 LOC {1 0.14655495 1 0.285381075 1 0.285381075 1 0.35881025} PREDS {{259 0 0-7108 {}}} SUCCS {{259 0 0-7110 {}}} CYCLES {}}
+set a(0-7110) {NAME ACC1:conc#1152 TYPE CONCATENATE PAR 0-7009 XREFS 46819 LOC {1 0.14655495 1 0.285381075 1 0.285381075 1 0.35881025} PREDS {{259 0 0-7109 {}}} SUCCS {{258 0 0-7123 {}}} CYCLES {}}
+set a(0-7111) {NAME ACC1-1:slc(acc#10.psp)#40 TYPE READSLICE PAR 0-7009 XREFS 46820 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-7112 {}}} CYCLES {}}
+set a(0-7112) {NAME ACC1:conc#1148 TYPE CONCATENATE PAR 0-7009 XREFS 46821 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{259 0 0-7111 {}}} SUCCS {{258 0 0-7118 {}}} CYCLES {}}
+set a(0-7113) {NAME ACC1-1:slc(acc#10.psp)#41 TYPE READSLICE PAR 0-7009 XREFS 46822 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-7114 {}}} CYCLES {}}
+set a(0-7114) {NAME ACC1-1:not#248 TYPE NOT PAR 0-7009 XREFS 46823 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{259 0 0-7113 {}}} SUCCS {{258 0 0-7117 {}}} CYCLES {}}
+set a(0-7115) {NAME ACC1-1:slc(acc#10.psp)#45 TYPE READSLICE PAR 0-7009 XREFS 46824 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-7116 {}}} CYCLES {}}
+set a(0-7116) {NAME ACC1-1:not#250 TYPE NOT PAR 0-7009 XREFS 46825 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{259 0 0-7115 {}}} SUCCS {{259 0 0-7117 {}}} CYCLES {}}
+set a(0-7117) {NAME ACC1:conc#1149 TYPE CONCATENATE PAR 0-7009 XREFS 46826 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{258 0 0-7114 {}} {259 0 0-7116 {}}} SUCCS {{259 0 0-7118 {}}} CYCLES {}}
+set a(0-7118) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#343 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 46827 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.2853810350894752 1 0.3588102100894752} PREDS {{258 0 0-7112 {}} {259 0 0-7117 {}}} SUCCS {{259 0 0-7119 {}}} CYCLES {}}
+set a(0-7119) {NAME ACC1:slc#22 TYPE READSLICE PAR 0-7009 XREFS 46828 LOC {1 0.187338 1 0.285381075 1 0.285381075 1 0.35881025} PREDS {{259 0 0-7118 {}}} SUCCS {{258 0 0-7122 {}}} CYCLES {}}
+set a(0-7120) {NAME ACC1-1:slc(acc#10.psp)#47 TYPE READSLICE PAR 0-7009 XREFS 46829 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.35881025} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-7121 {}}} CYCLES {}}
+set a(0-7121) {NAME ACC1-1:not#251 TYPE NOT PAR 0-7009 XREFS 46830 LOC {1 0.14655495 1 0.285381075 1 0.285381075 1 0.35881025} PREDS {{259 0 0-7120 {}}} SUCCS {{259 0 0-7122 {}}} CYCLES {}}
+set a(0-7122) {NAME ACC1:conc#1153 TYPE CONCATENATE PAR 0-7009 XREFS 46831 LOC {1 0.187338 1 0.285381075 1 0.285381075 1 0.35881025} PREDS {{258 0 0-7119 {}} {259 0 0-7121 {}}} SUCCS {{259 0 0-7123 {}}} CYCLES {}}
+set a(0-7123) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#345 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 46832 LOC {1 0.187338 1 0.285381075 1 0.285381075 1 0.3184178451789505 1 0.3918470201789505} PREDS {{258 0 0-7110 {}} {259 0 0-7122 {}}} SUCCS {{259 0 0-7124 {}}} CYCLES {}}
+set a(0-7124) {NAME ACC1:slc#24 TYPE READSLICE PAR 0-7009 XREFS 46833 LOC {1 0.220374825 1 0.3184179 1 0.3184179 1 0.391847075} PREDS {{259 0 0-7123 {}}} SUCCS {{259 0 0-7125 {}}} CYCLES {}}
+set a(0-7125) {NAME ACC1:conc#1154 TYPE CONCATENATE PAR 0-7009 XREFS 46834 LOC {1 0.220374825 1 0.3184179 1 0.3184179 1 0.391847075} PREDS {{259 0 0-7124 {}}} SUCCS {{258 0 0-7143 {}}} CYCLES {}}
+set a(0-7126) {NAME ACC1-1:slc(acc#10.psp)#42 TYPE READSLICE PAR 0-7009 XREFS 46835 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3238181} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-7127 {}}} CYCLES {}}
+set a(0-7127) {NAME ACC1:conc#1146 TYPE CONCATENATE PAR 0-7009 XREFS 46836 LOC {1 0.14655495 1 0.250388925 1 0.250388925 1 0.3238181} PREDS {{259 0 0-7126 {}}} SUCCS {{258 0 0-7132 {}}} CYCLES {}}
+set a(0-7128) {NAME ACC1-1:slc(acc#10.psp)#43 TYPE READSLICE PAR 0-7009 XREFS 46837 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3238181} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-7129 {}}} CYCLES {}}
+set a(0-7129) {NAME ACC1-1:not#249 TYPE NOT PAR 0-7009 XREFS 46838 LOC {1 0.14655495 1 0.250388925 1 0.250388925 1 0.3238181} PREDS {{259 0 0-7128 {}}} SUCCS {{258 0 0-7131 {}}} CYCLES {}}
+set a(0-7130) {NAME ACC1-1:slc(acc#10.psp)#44 TYPE READSLICE PAR 0-7009 XREFS 46839 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3238181} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-7131 {}}} CYCLES {}}
+set a(0-7131) {NAME ACC1:conc#1147 TYPE CONCATENATE PAR 0-7009 XREFS 46840 LOC {1 0.14655495 1 0.250388925 1 0.250388925 1 0.3238181} PREDS {{258 0 0-7129 {}} {259 0 0-7130 {}}} SUCCS {{259 0 0-7132 {}}} CYCLES {}}
+set a(0-7132) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#342 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 46841 LOC {1 0.14655495 1 0.250388925 1 0.250388925 1 0.29117193508947525 1 0.36460111008947527} PREDS {{258 0 0-7127 {}} {259 0 0-7131 {}}} SUCCS {{259 0 0-7133 {}}} CYCLES {}}
+set a(0-7133) {NAME ACC1:slc#21 TYPE READSLICE PAR 0-7009 XREFS 46842 LOC {1 0.187338 1 0.29117197499999997 1 0.29117197499999997 1 0.36460115} PREDS {{259 0 0-7132 {}}} SUCCS {{259 0 0-7134 {}}} CYCLES {}}
+set a(0-7134) {NAME ACC1:conc#1150 TYPE CONCATENATE PAR 0-7009 XREFS 46843 LOC {1 0.187338 1 0.29117197499999997 1 0.29117197499999997 1 0.36460115} PREDS {{259 0 0-7133 {}}} SUCCS {{258 0 0-7139 {}}} CYCLES {}}
+set a(0-7135) {NAME ACC1-1:slc(acc#10.psp)#49 TYPE READSLICE PAR 0-7009 XREFS 46844 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.36460115} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-7136 {}}} CYCLES {}}
+set a(0-7136) {NAME ACC1-1:not#252 TYPE NOT PAR 0-7009 XREFS 46845 LOC {1 0.14655495 1 0.29117197499999997 1 0.29117197499999997 1 0.36460115} PREDS {{259 0 0-7135 {}}} SUCCS {{258 0 0-7138 {}}} CYCLES {}}
+set a(0-7137) {NAME ACC1-1:slc(acc#10.psp)#46 TYPE READSLICE PAR 0-7009 XREFS 46846 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.36460115} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-7138 {}}} CYCLES {}}
+set a(0-7138) {NAME ACC1:conc#1151 TYPE CONCATENATE PAR 0-7009 XREFS 46847 LOC {1 0.14655495 1 0.29117197499999997 1 0.29117197499999997 1 0.36460115} PREDS {{258 0 0-7136 {}} {259 0 0-7137 {}}} SUCCS {{259 0 0-7139 {}}} CYCLES {}}
+set a(0-7139) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#344 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 46848 LOC {1 0.187338 1 0.29117197499999997 1 0.29117197499999997 1 0.3184178520708272 1 0.3918470270708272} PREDS {{258 0 0-7134 {}} {259 0 0-7138 {}}} SUCCS {{259 0 0-7140 {}}} CYCLES {}}
+set a(0-7140) {NAME ACC1:slc#23 TYPE READSLICE PAR 0-7009 XREFS 46849 LOC {1 0.21458392499999998 1 0.3184179 1 0.3184179 1 0.391847075} PREDS {{259 0 0-7139 {}}} SUCCS {{258 0 0-7142 {}}} CYCLES {}}
+set a(0-7141) {NAME ACC1-1:slc(acc#10.psp)#48 TYPE READSLICE PAR 0-7009 XREFS 46850 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.391847075} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-7142 {}}} CYCLES {}}
+set a(0-7142) {NAME ACC1:conc#1155 TYPE CONCATENATE PAR 0-7009 XREFS 46851 LOC {1 0.21458392499999998 1 0.3184179 1 0.3184179 1 0.391847075} PREDS {{258 0 0-7140 {}} {259 0 0-7141 {}}} SUCCS {{259 0 0-7143 {}}} CYCLES {}}
+set a(0-7143) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#346 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-7009 XREFS 46852 LOC {1 0.220374825 1 0.3184179 1 0.3184179 1 0.35670735949693605 1 0.43013653449693606} PREDS {{258 0 0-7125 {}} {259 0 0-7142 {}}} SUCCS {{259 0 0-7144 {}}} CYCLES {}}
+set a(0-7144) {NAME ACC1:slc#25 TYPE READSLICE PAR 0-7009 XREFS 46853 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.43013657499999997} PREDS {{259 0 0-7143 {}}} SUCCS {{259 0 0-7145 {}} {258 0 0-7147 {}} {258 0 0-7149 {}} {258 0 0-7153 {}} {258 0 0-8254 {}} {258 0 0-8263 {}} {258 0 0-8273 {}} {258 0 0-9194 {}}} CYCLES {}}
+set a(0-7145) {NAME ACC1-1:slc(ACC1:acc#214.psp) TYPE READSLICE PAR 0-7009 XREFS 46854 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{259 0 0-7144 {}}} SUCCS {{259 0 0-7146 {}}} CYCLES {}}
+set a(0-7146) {NAME ACC1:conc#1156 TYPE CONCATENATE PAR 0-7009 XREFS 46855 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{259 0 0-7145 {}}} SUCCS {{258 0 0-7151 {}}} CYCLES {}}
+set a(0-7147) {NAME ACC1-1:slc(ACC1:acc#214.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 46856 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{258 0 0-7144 {}}} SUCCS {{259 0 0-7148 {}}} CYCLES {}}
+set a(0-7148) {NAME ACC1-1:not#281 TYPE NOT PAR 0-7009 XREFS 46857 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{259 0 0-7147 {}}} SUCCS {{258 0 0-7150 {}}} CYCLES {}}
+set a(0-7149) {NAME ACC1-1:slc(ACC1:acc#214.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 46858 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{258 0 0-7144 {}}} SUCCS {{259 0 0-7150 {}}} CYCLES {}}
+set a(0-7150) {NAME ACC1:conc#1157 TYPE CONCATENATE PAR 0-7009 XREFS 46859 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{258 0 0-7148 {}} {259 0 0-7149 {}}} SUCCS {{259 0 0-7151 {}}} CYCLES {}}
+set a(0-7151) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#347 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 46860 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.3974904100894753 1 0.5338902350894752} PREDS {{258 0 0-7146 {}} {259 0 0-7150 {}}} SUCCS {{259 0 0-7152 {}}} CYCLES {}}
+set a(0-7152) {NAME ACC1:slc#26 TYPE READSLICE PAR 0-7009 XREFS 46861 LOC {1 0.29944737499999996 1 0.39749045 1 0.39749045 1 0.533890275} PREDS {{259 0 0-7151 {}}} SUCCS {{258 0 0-7155 {}}} CYCLES {}}
+set a(0-7153) {NAME ACC1-1:slc(ACC1:acc#214.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 46862 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.533890275} PREDS {{258 0 0-7144 {}}} SUCCS {{259 0 0-7154 {}}} CYCLES {}}
+set a(0-7154) {NAME ACC1-1:not#303 TYPE NOT PAR 0-7009 XREFS 46863 LOC {1 0.258664325 1 0.39749045 1 0.39749045 1 0.533890275} PREDS {{259 0 0-7153 {}}} SUCCS {{259 0 0-7155 {}}} CYCLES {}}
+set a(0-7155) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-1:acc#225 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 46864 LOC {1 0.29944737499999996 1 0.39749045 1 0.39749045 1 0.41796321008947523 1 0.5543630350894753} PREDS {{258 0 0-7152 {}} {259 0 0-7154 {}}} SUCCS {{259 0 0-7156 {}} {258 0 0-7159 {}} {258 0 0-9226 {}}} CYCLES {}}
+set a(0-7156) {NAME ACC1-1:slc(ACC1:acc#222.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 46865 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-7155 {}}} SUCCS {{259 0 0-7157 {}}} CYCLES {}}
+set a(0-7157) {NAME ACC1-1:not#297 TYPE NOT PAR 0-7009 XREFS 46866 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-7156 {}}} SUCCS {{259 0 0-7158 {}}} CYCLES {}}
+set a(0-7158) {NAME ACC1:conc#1158 TYPE CONCATENATE PAR 0-7009 XREFS 46867 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-7157 {}}} SUCCS {{258 0 0-7161 {}}} CYCLES {}}
+set a(0-7159) {NAME ACC1-1:slc(ACC1:acc#222.psp) TYPE READSLICE PAR 0-7009 XREFS 46868 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{258 0 0-7155 {}}} SUCCS {{259 0 0-7160 {}}} CYCLES {}}
+set a(0-7160) {NAME ACC1:conc#1159 TYPE CONCATENATE PAR 0-7009 XREFS 46869 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-7159 {}}} SUCCS {{259 0 0-7161 {}}} CYCLES {}}
+set a(0-7161) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#348 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 46870 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.44520912707082716 1 0.5816089520708271} PREDS {{258 0 0-7158 {}} {259 0 0-7160 {}}} SUCCS {{259 0 0-7162 {}}} CYCLES {}}
+set a(0-7162) {NAME ACC1:slc#27 TYPE READSLICE PAR 0-7009 XREFS 46871 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-7161 {}}} SUCCS {{259 0 0-7163 {}} {258 0 0-7165 {}} {258 0 0-7167 {}} {258 0 0-9104 {}} {258 0 0-9207 {}}} CYCLES {}}
+set a(0-7163) {NAME ACC1-1:slc(acc.imod#10) TYPE READSLICE PAR 0-7009 XREFS 46872 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-7162 {}}} SUCCS {{259 0 0-7164 {}}} CYCLES {}}
+set a(0-7164) {NAME ACC1:conc#1161 TYPE CONCATENATE PAR 0-7009 XREFS 46873 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-7163 {}}} SUCCS {{258 0 0-7170 {}}} CYCLES {}}
+set a(0-7165) {NAME ACC1-1:slc(acc.imod#10)#1 TYPE READSLICE PAR 0-7009 XREFS 46874 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-7162 {}}} SUCCS {{259 0 0-7166 {}}} CYCLES {}}
+set a(0-7166) {NAME ACC1-1:not#89 TYPE NOT PAR 0-7009 XREFS 46875 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-7165 {}}} SUCCS {{258 0 0-7169 {}}} CYCLES {}}
+set a(0-7167) {NAME ACC1-1:slc(acc.imod#10)#2 TYPE READSLICE PAR 0-7009 XREFS 46876 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-7162 {}}} SUCCS {{259 0 0-7168 {}}} CYCLES {}}
+set a(0-7168) {NAME ACC1-1:not#90 TYPE NOT PAR 0-7009 XREFS 46877 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-7167 {}}} SUCCS {{259 0 0-7169 {}}} CYCLES {}}
+set a(0-7169) {NAME ACC1:conc#1162 TYPE CONCATENATE PAR 0-7009 XREFS 46878 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-7166 {}} {259 0 0-7168 {}}} SUCCS {{259 0 0-7170 {}}} CYCLES {}}
+set a(0-7170) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#349 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 46879 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.47245505207082716 1 0.6088548770708271} PREDS {{258 0 0-7164 {}} {259 0 0-7169 {}}} SUCCS {{259 0 0-7171 {}}} CYCLES {}}
+set a(0-7171) {NAME ACC1:slc#28 TYPE READSLICE PAR 0-7009 XREFS 46880 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-7170 {}}} SUCCS {{258 0 0-9092 {}} {258 0 0-9236 {}} {258 0 0-9238 {}}} CYCLES {}}
+set a(0-7172) {NAME regs.regs:slc(regs.regs(0))#9 TYPE READSLICE PAR 0-7009 XREFS 46881 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{258 0 0-7013 {}}} SUCCS {{259 0 0-7173 {}}} CYCLES {}}
+set a(0-7173) {NAME {regs.operator[]#12:not} TYPE NOT PAR 0-7009 XREFS 46882 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-7172 {}}} SUCCS {{258 0 0-7176 {}}} CYCLES {}}
+set a(0-7174) {NAME regs.regs:slc(regs.regs(0))#10 TYPE READSLICE PAR 0-7009 XREFS 46883 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{258 0 0-7013 {}}} SUCCS {{259 0 0-7175 {}}} CYCLES {}}
+set a(0-7175) {NAME {regs.operator[]#13:not} TYPE NOT PAR 0-7009 XREFS 46884 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-7174 {}}} SUCCS {{259 0 0-7176 {}}} CYCLES {}}
+set a(0-7176) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#351 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 46885 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.09544225333641132 1 0.1749305033364113} PREDS {{258 0 0-7173 {}} {259 0 0-7175 {}}} SUCCS {{258 0 0-7180 {}}} CYCLES {}}
+set a(0-7177) {NAME regs.regs:slc(regs.regs(0))#11 TYPE READSLICE PAR 0-7009 XREFS 46886 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{258 0 0-7013 {}}} SUCCS {{259 0 0-7178 {}}} CYCLES {}}
+set a(0-7178) {NAME {regs.operator[]#14:not} TYPE NOT PAR 0-7009 XREFS 46887 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-7177 {}}} SUCCS {{259 0 0-7179 {}}} CYCLES {}}
+set a(0-7179) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#350 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 46888 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.09544225333641132 1 0.1749305033364113} PREDS {{259 0 0-7178 {}}} SUCCS {{259 0 0-7180 {}}} CYCLES {}}
+set a(0-7180) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-1:acc#20 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 46889 LOC {1 0.07118415 1 0.0954423 1 0.0954423 1 0.17081305637342836 1 0.25030130637342834} PREDS {{258 0 0-7176 {}} {259 0 0-7179 {}}} SUCCS {{259 0 0-7181 {}} {258 0 0-7184 {}} {258 0 0-7186 {}} {258 0 0-7191 {}} {258 0 0-7193 {}} {258 0 0-7197 {}} {258 0 0-7199 {}} {258 0 0-7201 {}} {258 0 0-7207 {}} {258 0 0-7209 {}} {258 0 0-7211 {}} {258 0 0-7215 {}} {258 0 0-7935 {}} {258 0 0-7936 {}} {258 0 0-7937 {}} {258 0 0-7938 {}} {258 0 0-7939 {}} {258 0 0-7941 {}} {258 0 0-7942 {}} {258 0 0-7943 {}} {258 0 0-7944 {}} {258 0 0-7947 {}} {258 0 0-7948 {}} {258 0 0-7949 {}} {258 0 0-7952 {}} {258 0 0-7955 {}} {258 0 0-7958 {}} {258 0 0-7964 {}} {258 0 0-7967 {}} {258 0 0-7975 {}} {258 0 0-7978 {}} {258 0 0-7984 {}} {258 0 0-7987 {}} {258 0 0-7998 {}} {258 0 0-8002 {}} {258 0 0-8008 {}} {258 0 0-8009 {}} {258 0 0-8013 {}} {258 0 0-8020 {}} {258 0 0-8021 {}} {258 0 0-8022 {}} {258 0 0-8025 {}} {258 0 0-8027 {}} {258 0 0-8032 {}} {258 0 0-8033 {}} {258 0 0-8034 {}} {258 0 0-8035 {}} {258 0 0-8038 {}} {258 0 0-8039 {}} {258 0 0-8043 {}} {258 0 0-8044 {}} {258 0 0-8045 {}} {258 0 0-8047 {}} {258 0 0-8049 {}} {258 0 0-8052 {}} {258 0 0-8055 {}} {258 0 0-8057 {}} {258 0 0-8070 {}} {258 0 0-8071 {}} {258 0 0-8073 {}} {258 0 0-8074 {}} {258 0 0-8075 {}} {258 0 0-8076 {}} {258 0 0-8077 {}}} CYCLES {}}
+set a(0-7181) {NAME ACC1-1:slc(acc#20.psp)#11 TYPE READSLICE PAR 0-7009 XREFS 46890 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.274975825} PREDS {{259 0 0-7180 {}}} SUCCS {{259 0 0-7182 {}}} CYCLES {}}
+set a(0-7182) {NAME ACC1-1:not#304 TYPE NOT PAR 0-7009 XREFS 46891 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{259 0 0-7181 {}}} SUCCS {{259 0 0-7183 {}}} CYCLES {}}
+set a(0-7183) {NAME ACC1:conc#1168 TYPE CONCATENATE PAR 0-7009 XREFS 46892 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{259 0 0-7182 {}}} SUCCS {{258 0 0-7188 {}}} CYCLES {}}
+set a(0-7184) {NAME ACC1-1:slc(acc#20.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 46893 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.274975825} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7185 {}}} CYCLES {}}
+set a(0-7185) {NAME ACC1-1:not#260 TYPE NOT PAR 0-7009 XREFS 46894 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{259 0 0-7184 {}}} SUCCS {{258 0 0-7187 {}}} CYCLES {}}
+set a(0-7186) {NAME ACC1-1:slc(acc#20.psp)#8 TYPE READSLICE PAR 0-7009 XREFS 46895 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.274975825} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7187 {}}} CYCLES {}}
+set a(0-7187) {NAME ACC1:conc#1169 TYPE CONCATENATE PAR 0-7009 XREFS 46896 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{258 0 0-7185 {}} {259 0 0-7186 {}}} SUCCS {{259 0 0-7188 {}}} CYCLES {}}
+set a(0-7188) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#354 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 46897 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.21596033508947524 1 0.29544858508947525} PREDS {{258 0 0-7183 {}} {259 0 0-7187 {}}} SUCCS {{259 0 0-7189 {}}} CYCLES {}}
+set a(0-7189) {NAME ACC1:slc#31 TYPE READSLICE PAR 0-7009 XREFS 46898 LOC {1 0.16702775 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{259 0 0-7188 {}}} SUCCS {{259 0 0-7190 {}}} CYCLES {}}
+set a(0-7190) {NAME ACC1:conc#1172 TYPE CONCATENATE PAR 0-7009 XREFS 46899 LOC {1 0.16702775 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{259 0 0-7189 {}}} SUCCS {{258 0 0-7195 {}}} CYCLES {}}
+set a(0-7191) {NAME ACC1-1:slc(acc#20.psp) TYPE READSLICE PAR 0-7009 XREFS 46900 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.29544862499999996} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7192 {}}} CYCLES {}}
+set a(0-7192) {NAME ACC1:conc#1163 TYPE CONCATENATE PAR 0-7009 XREFS 46901 LOC {1 0.14655495 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{259 0 0-7191 {}}} SUCCS {{258 0 0-7194 {}}} CYCLES {}}
+set a(0-7193) {NAME ACC1-1:slc(acc#20.psp)#10 TYPE READSLICE PAR 0-7009 XREFS 46902 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.29544862499999996} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7194 {}}} CYCLES {}}
+set a(0-7194) {NAME ACC1:conc#1173 TYPE CONCATENATE PAR 0-7009 XREFS 46903 LOC {1 0.14655495 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{258 0 0-7192 {}} {259 0 0-7193 {}}} SUCCS {{259 0 0-7195 {}}} CYCLES {}}
+set a(0-7195) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#356 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 46904 LOC {1 0.16702775 1 0.21596037499999998 1 0.21596037499999998 1 0.2591522701789505 1 0.33864052017895047} PREDS {{258 0 0-7190 {}} {259 0 0-7194 {}}} SUCCS {{259 0 0-7196 {}}} CYCLES {}}
+set a(0-7196) {NAME ACC1:slc#33 TYPE READSLICE PAR 0-7009 XREFS 46905 LOC {1 0.21021969999999998 1 0.25915232499999996 1 0.25915232499999996 1 0.338640575} PREDS {{259 0 0-7195 {}}} SUCCS {{258 0 0-7220 {}}} CYCLES {}}
+set a(0-7197) {NAME ACC1-1:slc(acc#20.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 46906 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7198 {}}} CYCLES {}}
+set a(0-7198) {NAME ACC1:conc#1166 TYPE CONCATENATE PAR 0-7009 XREFS 46907 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-7197 {}}} SUCCS {{258 0 0-7204 {}}} CYCLES {}}
+set a(0-7199) {NAME ACC1-1:slc(acc#20.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 46908 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7200 {}}} CYCLES {}}
+set a(0-7200) {NAME ACC1-1:not#261 TYPE NOT PAR 0-7009 XREFS 46909 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-7199 {}}} SUCCS {{258 0 0-7203 {}}} CYCLES {}}
+set a(0-7201) {NAME ACC1-1:slc(acc#20.psp)#7 TYPE READSLICE PAR 0-7009 XREFS 46910 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7202 {}}} CYCLES {}}
+set a(0-7202) {NAME ACC1-1:not#263 TYPE NOT PAR 0-7009 XREFS 46911 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-7201 {}}} SUCCS {{259 0 0-7203 {}}} CYCLES {}}
+set a(0-7203) {NAME ACC1:conc#1167 TYPE CONCATENATE PAR 0-7009 XREFS 46912 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7200 {}} {259 0 0-7202 {}}} SUCCS {{259 0 0-7204 {}}} CYCLES {}}
+set a(0-7204) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#353 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 46913 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.21159611008947524 1 0.29108436008947525} PREDS {{258 0 0-7198 {}} {259 0 0-7203 {}}} SUCCS {{259 0 0-7205 {}}} CYCLES {}}
+set a(0-7205) {NAME ACC1:slc#30 TYPE READSLICE PAR 0-7009 XREFS 46914 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-7204 {}}} SUCCS {{259 0 0-7206 {}}} CYCLES {}}
+set a(0-7206) {NAME ACC1:conc#1170 TYPE CONCATENATE PAR 0-7009 XREFS 46915 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-7205 {}}} SUCCS {{258 0 0-7218 {}}} CYCLES {}}
+set a(0-7207) {NAME ACC1-1:slc(acc#20.psp)#4 TYPE READSLICE PAR 0-7009 XREFS 46916 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7208 {}}} CYCLES {}}
+set a(0-7208) {NAME ACC1:conc#1164 TYPE CONCATENATE PAR 0-7009 XREFS 46917 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-7207 {}}} SUCCS {{258 0 0-7213 {}}} CYCLES {}}
+set a(0-7209) {NAME ACC1-1:slc(acc#20.psp)#5 TYPE READSLICE PAR 0-7009 XREFS 46918 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7210 {}}} CYCLES {}}
+set a(0-7210) {NAME ACC1-1:not#262 TYPE NOT PAR 0-7009 XREFS 46919 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-7209 {}}} SUCCS {{258 0 0-7212 {}}} CYCLES {}}
+set a(0-7211) {NAME ACC1-1:slc(acc#20.psp)#6 TYPE READSLICE PAR 0-7009 XREFS 46920 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7212 {}}} CYCLES {}}
+set a(0-7212) {NAME ACC1:conc#1165 TYPE CONCATENATE PAR 0-7009 XREFS 46921 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-7210 {}} {259 0 0-7211 {}}} SUCCS {{259 0 0-7213 {}}} CYCLES {}}
+set a(0-7213) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#352 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 46922 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.21159611008947524 1 0.29108436008947525} PREDS {{258 0 0-7208 {}} {259 0 0-7212 {}}} SUCCS {{259 0 0-7214 {}}} CYCLES {}}
+set a(0-7214) {NAME ACC1:slc#29 TYPE READSLICE PAR 0-7009 XREFS 46923 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-7213 {}}} SUCCS {{258 0 0-7217 {}}} CYCLES {}}
+set a(0-7215) {NAME ACC1-1:slc(acc#20.psp)#9 TYPE READSLICE PAR 0-7009 XREFS 46924 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.29108439999999997} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7216 {}}} CYCLES {}}
+set a(0-7216) {NAME ACC1-1:not#264 TYPE NOT PAR 0-7009 XREFS 46925 LOC {1 0.14655495 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-7215 {}}} SUCCS {{259 0 0-7217 {}}} CYCLES {}}
+set a(0-7217) {NAME ACC1:conc#1171 TYPE CONCATENATE PAR 0-7009 XREFS 46926 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{258 0 0-7214 {}} {259 0 0-7216 {}}} SUCCS {{259 0 0-7218 {}}} CYCLES {}}
+set a(0-7218) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#355 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 46927 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.25915227707082716 1 0.33864052707082715} PREDS {{258 0 0-7206 {}} {259 0 0-7217 {}}} SUCCS {{259 0 0-7219 {}}} CYCLES {}}
+set a(0-7219) {NAME ACC1:slc#32 TYPE READSLICE PAR 0-7009 XREFS 46928 LOC {1 0.23489417499999998 1 0.25915232499999996 1 0.25915232499999996 1 0.338640575} PREDS {{259 0 0-7218 {}}} SUCCS {{259 0 0-7220 {}}} CYCLES {}}
+set a(0-7220) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1-1:acc#217 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 46929 LOC {1 0.23489417499999998 1 0.25915232499999996 1 0.25915232499999996 1 0.2921890951789505 1 0.3716773451789505} PREDS {{258 0 0-7196 {}} {259 0 0-7219 {}}} SUCCS {{259 0 0-7221 {}} {258 0 0-7223 {}} {258 0 0-7225 {}} {258 0 0-7229 {}} {258 0 0-7989 {}} {258 0 0-8001 {}} {258 0 0-8012 {}} {258 0 0-8015 {}}} CYCLES {}}
+set a(0-7221) {NAME ACC1-1:slc(ACC1:acc#217.psp) TYPE READSLICE PAR 0-7009 XREFS 46930 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{259 0 0-7220 {}}} SUCCS {{259 0 0-7222 {}}} CYCLES {}}
+set a(0-7222) {NAME ACC1:conc#1174 TYPE CONCATENATE PAR 0-7009 XREFS 46931 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{259 0 0-7221 {}}} SUCCS {{258 0 0-7227 {}}} CYCLES {}}
+set a(0-7223) {NAME ACC1-1:slc(ACC1:acc#217.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 46932 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{258 0 0-7220 {}}} SUCCS {{259 0 0-7224 {}}} CYCLES {}}
+set a(0-7224) {NAME ACC1-1:not#287 TYPE NOT PAR 0-7009 XREFS 46933 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{259 0 0-7223 {}}} SUCCS {{258 0 0-7226 {}}} CYCLES {}}
+set a(0-7225) {NAME ACC1-1:slc(ACC1:acc#217.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 46934 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{258 0 0-7220 {}}} SUCCS {{259 0 0-7226 {}}} CYCLES {}}
+set a(0-7226) {NAME ACC1:conc#1175 TYPE CONCATENATE PAR 0-7009 XREFS 46935 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{258 0 0-7224 {}} {259 0 0-7225 {}}} SUCCS {{259 0 0-7227 {}}} CYCLES {}}
+set a(0-7227) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#357 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 46936 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3329721600894753 1 0.4124604100894752} PREDS {{258 0 0-7222 {}} {259 0 0-7226 {}}} SUCCS {{259 0 0-7228 {}}} CYCLES {}}
+set a(0-7228) {NAME ACC1:slc#34 TYPE READSLICE PAR 0-7009 XREFS 46937 LOC {1 0.30871404999999996 1 0.3329722 1 0.3329722 1 0.41246045} PREDS {{259 0 0-7227 {}}} SUCCS {{258 0 0-7231 {}}} CYCLES {}}
+set a(0-7229) {NAME ACC1-1:slc(ACC1:acc#217.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 46938 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.41246045} PREDS {{258 0 0-7220 {}}} SUCCS {{259 0 0-7230 {}}} CYCLES {}}
+set a(0-7230) {NAME ACC1-1:not#306 TYPE NOT PAR 0-7009 XREFS 46939 LOC {1 0.267931 1 0.3329722 1 0.3329722 1 0.41246045} PREDS {{259 0 0-7229 {}}} SUCCS {{259 0 0-7231 {}}} CYCLES {}}
+set a(0-7231) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-1:acc#223 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 46940 LOC {1 0.30871404999999996 1 0.3329722 1 0.3329722 1 0.35344496008947524 1 0.4329332100894752} PREDS {{258 0 0-7228 {}} {259 0 0-7230 {}}} SUCCS {{259 0 0-7232 {}} {258 0 0-7235 {}} {258 0 0-8006 {}}} CYCLES {}}
+set a(0-7232) {NAME ACC1-1:slc(ACC1:acc#223.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 46941 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-7231 {}}} SUCCS {{259 0 0-7233 {}}} CYCLES {}}
+set a(0-7233) {NAME ACC1-1:not#299 TYPE NOT PAR 0-7009 XREFS 46942 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-7232 {}}} SUCCS {{259 0 0-7234 {}}} CYCLES {}}
+set a(0-7234) {NAME ACC1:conc#1176 TYPE CONCATENATE PAR 0-7009 XREFS 46943 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-7233 {}}} SUCCS {{258 0 0-7237 {}}} CYCLES {}}
+set a(0-7235) {NAME ACC1-1:slc(ACC1:acc#223.psp) TYPE READSLICE PAR 0-7009 XREFS 46944 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{258 0 0-7231 {}}} SUCCS {{259 0 0-7236 {}}} CYCLES {}}
+set a(0-7236) {NAME ACC1:conc#1177 TYPE CONCATENATE PAR 0-7009 XREFS 46945 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-7235 {}}} SUCCS {{259 0 0-7237 {}}} CYCLES {}}
+set a(0-7237) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#358 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 46946 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.38069087707082716 1 0.4601791270708272} PREDS {{258 0 0-7234 {}} {259 0 0-7236 {}}} SUCCS {{259 0 0-7238 {}}} CYCLES {}}
+set a(0-7238) {NAME ACC1:slc#35 TYPE READSLICE PAR 0-7009 XREFS 46947 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-7237 {}}} SUCCS {{259 0 0-7239 {}} {258 0 0-7241 {}} {258 0 0-7243 {}} {258 0 0-7969 {}} {258 0 0-7980 {}}} CYCLES {}}
+set a(0-7239) {NAME ACC1-1:slc(acc.imod#18) TYPE READSLICE PAR 0-7009 XREFS 46948 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-7238 {}}} SUCCS {{259 0 0-7240 {}}} CYCLES {}}
+set a(0-7240) {NAME ACC1:conc#1179 TYPE CONCATENATE PAR 0-7009 XREFS 46949 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-7239 {}}} SUCCS {{258 0 0-7246 {}}} CYCLES {}}
+set a(0-7241) {NAME ACC1-1:slc(acc.imod#18)#1 TYPE READSLICE PAR 0-7009 XREFS 46950 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{258 0 0-7238 {}}} SUCCS {{259 0 0-7242 {}}} CYCLES {}}
+set a(0-7242) {NAME ACC1-1:not#153 TYPE NOT PAR 0-7009 XREFS 46951 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-7241 {}}} SUCCS {{258 0 0-7245 {}}} CYCLES {}}
+set a(0-7243) {NAME ACC1-1:slc(acc.imod#18)#2 TYPE READSLICE PAR 0-7009 XREFS 46952 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{258 0 0-7238 {}}} SUCCS {{259 0 0-7244 {}}} CYCLES {}}
+set a(0-7244) {NAME ACC1-1:not#154 TYPE NOT PAR 0-7009 XREFS 46953 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-7243 {}}} SUCCS {{259 0 0-7245 {}}} CYCLES {}}
+set a(0-7245) {NAME ACC1:conc#1180 TYPE CONCATENATE PAR 0-7009 XREFS 46954 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{258 0 0-7242 {}} {259 0 0-7244 {}}} SUCCS {{259 0 0-7246 {}}} CYCLES {}}
+set a(0-7246) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#359 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 46955 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.40793680207082716 1 0.4874250520708272} PREDS {{258 0 0-7240 {}} {259 0 0-7245 {}}} SUCCS {{259 0 0-7247 {}}} CYCLES {}}
+set a(0-7247) {NAME ACC1:slc#36 TYPE READSLICE PAR 0-7009 XREFS 46956 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7246 {}}} SUCCS {{258 0 0-7957 {}} {258 0 0-8058 {}} {258 0 0-8060 {}}} CYCLES {}}
+set a(0-7248) {NAME regs.regs:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-7009 XREFS 46957 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.22517622499999998} PREDS {{258 0 0-7013 {}}} SUCCS {{258 0 0-7250 {}}} CYCLES {}}
+set a(0-7249) {NAME regs.regs:slc(regs.regs(0))#2 TYPE READSLICE PAR 0-7009 XREFS 46958 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.22517622499999998} PREDS {{258 0 0-7013 {}}} SUCCS {{259 0 0-7250 {}}} CYCLES {}}
+set a(0-7250) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#360 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 46959 LOC {1 0.0 1 0.08877639999999999 1 0.08877639999999999 1 0.15996050333641132 1 0.2963603283364113} PREDS {{258 0 0-7248 {}} {259 0 0-7249 {}}} SUCCS {{258 0 0-7252 {}}} CYCLES {}}
+set a(0-7251) {NAME regs.regs:slc(regs.regs(0)) TYPE READSLICE PAR 0-7009 XREFS 46960 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.296360375} PREDS {{258 0 0-7013 {}}} SUCCS {{259 0 0-7252 {}}} CYCLES {}}
+set a(0-7252) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-1:acc#25 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 46961 LOC {1 0.07118415 1 0.15996054999999998 1 0.15996054999999998 1 0.23533130637342836 1 0.3717311313734284} PREDS {{258 0 0-7250 {}} {259 0 0-7251 {}}} SUCCS {{259 0 0-7253 {}} {258 0 0-7256 {}} {258 0 0-7258 {}} {258 0 0-7263 {}} {258 0 0-7265 {}} {258 0 0-7269 {}} {258 0 0-7271 {}} {258 0 0-7273 {}} {258 0 0-7279 {}} {258 0 0-7281 {}} {258 0 0-7283 {}} {258 0 0-7287 {}} {258 0 0-7769 {}} {258 0 0-7770 {}} {258 0 0-7771 {}} {258 0 0-7772 {}} {258 0 0-7773 {}} {258 0 0-7787 {}} {258 0 0-8089 {}} {258 0 0-8095 {}} {258 0 0-8101 {}} {258 0 0-8131 {}} {258 0 0-8185 {}} {258 0 0-8202 {}} {258 0 0-8249 {}} {258 0 0-8252 {}} {258 0 0-8258 {}} {258 0 0-8261 {}} {258 0 0-8268 {}} {258 0 0-8271 {}} {258 0 0-8277 {}} {258 0 0-8280 {}} {258 0 0-8288 {}} {258 0 0-8291 {}} {258 0 0-8297 {}} {258 0 0-8300 {}} {258 0 0-8307 {}} {258 0 0-8310 {}} {258 0 0-8549 {}} {258 0 0-8592 {}} {258 0 0-8606 {}} {258 0 0-8652 {}} {258 0 0-8711 {}} {258 0 0-8712 {}} {258 0 0-8733 {}} {258 0 0-9027 {}} {258 0 0-9041 {}} {258 0 0-9087 {}} {258 0 0-9090 {}} {258 0 0-9099 {}} {258 0 0-9102 {}} {258 0 0-9233 {}} {258 0 0-9258 {}}} CYCLES {}}
+set a(0-7253) {NAME ACC1-1:slc(acc#25.psp)#11 TYPE READSLICE PAR 0-7009 XREFS 46962 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.39640565} PREDS {{259 0 0-7252 {}}} SUCCS {{259 0 0-7254 {}}} CYCLES {}}
+set a(0-7254) {NAME ACC1:not#313 TYPE NOT PAR 0-7009 XREFS 46963 LOC {1 0.14655495 1 0.26000582499999997 1 0.26000582499999997 1 0.39640565} PREDS {{259 0 0-7253 {}}} SUCCS {{259 0 0-7255 {}}} CYCLES {}}
+set a(0-7255) {NAME ACC1:conc#1186 TYPE CONCATENATE PAR 0-7009 XREFS 46964 LOC {1 0.14655495 1 0.26000582499999997 1 0.26000582499999997 1 0.39640565} PREDS {{259 0 0-7254 {}}} SUCCS {{258 0 0-7260 {}}} CYCLES {}}
+set a(0-7256) {NAME ACC1-1:slc(acc#25.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 46965 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.39640565} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-7257 {}}} CYCLES {}}
+set a(0-7257) {NAME ACC1-1:not#220 TYPE NOT PAR 0-7009 XREFS 46966 LOC {1 0.14655495 1 0.26000582499999997 1 0.26000582499999997 1 0.39640565} PREDS {{259 0 0-7256 {}}} SUCCS {{258 0 0-7259 {}}} CYCLES {}}
+set a(0-7258) {NAME ACC1-1:slc(acc#25.psp)#8 TYPE READSLICE PAR 0-7009 XREFS 46967 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.39640565} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-7259 {}}} CYCLES {}}
+set a(0-7259) {NAME ACC1:conc#1187 TYPE CONCATENATE PAR 0-7009 XREFS 46968 LOC {1 0.14655495 1 0.26000582499999997 1 0.26000582499999997 1 0.39640565} PREDS {{258 0 0-7257 {}} {259 0 0-7258 {}}} SUCCS {{259 0 0-7260 {}}} CYCLES {}}
+set a(0-7260) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#363 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 46969 LOC {1 0.14655495 1 0.26000582499999997 1 0.26000582499999997 1 0.2804785850894752 1 0.41687841008947524} PREDS {{258 0 0-7255 {}} {259 0 0-7259 {}}} SUCCS {{259 0 0-7261 {}}} CYCLES {}}
+set a(0-7261) {NAME ACC1:slc#39 TYPE READSLICE PAR 0-7009 XREFS 46970 LOC {1 0.16702775 1 0.280478625 1 0.280478625 1 0.41687844999999996} PREDS {{259 0 0-7260 {}}} SUCCS {{259 0 0-7262 {}}} CYCLES {}}
+set a(0-7262) {NAME ACC1:conc#1190 TYPE CONCATENATE PAR 0-7009 XREFS 46971 LOC {1 0.16702775 1 0.280478625 1 0.280478625 1 0.41687844999999996} PREDS {{259 0 0-7261 {}}} SUCCS {{258 0 0-7267 {}}} CYCLES {}}
+set a(0-7263) {NAME ACC1-1:slc(acc#25.psp) TYPE READSLICE PAR 0-7009 XREFS 46972 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.41687844999999996} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-7264 {}}} CYCLES {}}
+set a(0-7264) {NAME ACC1:conc#1181 TYPE CONCATENATE PAR 0-7009 XREFS 46973 LOC {1 0.14655495 1 0.280478625 1 0.280478625 1 0.41687844999999996} PREDS {{259 0 0-7263 {}}} SUCCS {{258 0 0-7266 {}}} CYCLES {}}
+set a(0-7265) {NAME ACC1-1:slc(acc#25.psp)#10 TYPE READSLICE PAR 0-7009 XREFS 46974 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.41687844999999996} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-7266 {}}} CYCLES {}}
+set a(0-7266) {NAME ACC1:conc#1191 TYPE CONCATENATE PAR 0-7009 XREFS 46975 LOC {1 0.14655495 1 0.280478625 1 0.280478625 1 0.41687844999999996} PREDS {{258 0 0-7264 {}} {259 0 0-7265 {}}} SUCCS {{259 0 0-7267 {}}} CYCLES {}}
+set a(0-7267) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#365 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 46976 LOC {1 0.16702775 1 0.280478625 1 0.280478625 1 0.3236705201789505 1 0.46007034517895046} PREDS {{258 0 0-7262 {}} {259 0 0-7266 {}}} SUCCS {{259 0 0-7268 {}}} CYCLES {}}
+set a(0-7268) {NAME ACC1:slc#41 TYPE READSLICE PAR 0-7009 XREFS 46977 LOC {1 0.21021969999999998 1 0.32367057499999996 1 0.32367057499999996 1 0.4600704} PREDS {{259 0 0-7267 {}}} SUCCS {{258 0 0-7292 {}}} CYCLES {}}
+set a(0-7269) {NAME ACC1-1:slc(acc#25.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 46978 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-7270 {}}} CYCLES {}}
+set a(0-7270) {NAME ACC1:conc#1184 TYPE CONCATENATE PAR 0-7009 XREFS 46979 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{259 0 0-7269 {}}} SUCCS {{258 0 0-7276 {}}} CYCLES {}}
+set a(0-7271) {NAME ACC1-1:slc(acc#25.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 46980 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-7272 {}}} CYCLES {}}
+set a(0-7272) {NAME ACC1-1:not#221 TYPE NOT PAR 0-7009 XREFS 46981 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{259 0 0-7271 {}}} SUCCS {{258 0 0-7275 {}}} CYCLES {}}
+set a(0-7273) {NAME ACC1-1:slc(acc#25.psp)#7 TYPE READSLICE PAR 0-7009 XREFS 46982 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-7274 {}}} CYCLES {}}
+set a(0-7274) {NAME ACC1-1:not#223 TYPE NOT PAR 0-7009 XREFS 46983 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{259 0 0-7273 {}}} SUCCS {{259 0 0-7275 {}}} CYCLES {}}
+set a(0-7275) {NAME ACC1:conc#1185 TYPE CONCATENATE PAR 0-7009 XREFS 46984 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-7272 {}} {259 0 0-7274 {}}} SUCCS {{259 0 0-7276 {}}} CYCLES {}}
+set a(0-7276) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#362 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 46985 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.2761143600894752 1 0.41251418508947524} PREDS {{258 0 0-7270 {}} {259 0 0-7275 {}}} SUCCS {{259 0 0-7277 {}}} CYCLES {}}
+set a(0-7277) {NAME ACC1:slc#38 TYPE READSLICE PAR 0-7009 XREFS 46986 LOC {1 0.187338 1 0.2761144 1 0.2761144 1 0.41251422499999996} PREDS {{259 0 0-7276 {}}} SUCCS {{259 0 0-7278 {}}} CYCLES {}}
+set a(0-7278) {NAME ACC1:conc#1188 TYPE CONCATENATE PAR 0-7009 XREFS 46987 LOC {1 0.187338 1 0.2761144 1 0.2761144 1 0.41251422499999996} PREDS {{259 0 0-7277 {}}} SUCCS {{258 0 0-7290 {}}} CYCLES {}}
+set a(0-7279) {NAME ACC1-1:slc(acc#25.psp)#4 TYPE READSLICE PAR 0-7009 XREFS 46988 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-7280 {}}} CYCLES {}}
+set a(0-7280) {NAME ACC1:conc#1182 TYPE CONCATENATE PAR 0-7009 XREFS 46989 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{259 0 0-7279 {}}} SUCCS {{258 0 0-7285 {}}} CYCLES {}}
+set a(0-7281) {NAME ACC1-1:slc(acc#25.psp)#5 TYPE READSLICE PAR 0-7009 XREFS 46990 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-7282 {}}} CYCLES {}}
+set a(0-7282) {NAME ACC1-1:not#222 TYPE NOT PAR 0-7009 XREFS 46991 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{259 0 0-7281 {}}} SUCCS {{258 0 0-7284 {}}} CYCLES {}}
+set a(0-7283) {NAME ACC1-1:slc(acc#25.psp)#6 TYPE READSLICE PAR 0-7009 XREFS 46992 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-7284 {}}} CYCLES {}}
+set a(0-7284) {NAME ACC1:conc#1183 TYPE CONCATENATE PAR 0-7009 XREFS 46993 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-7282 {}} {259 0 0-7283 {}}} SUCCS {{259 0 0-7285 {}}} CYCLES {}}
+set a(0-7285) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#361 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 46994 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.2761143600894752 1 0.41251418508947524} PREDS {{258 0 0-7280 {}} {259 0 0-7284 {}}} SUCCS {{259 0 0-7286 {}}} CYCLES {}}
+set a(0-7286) {NAME ACC1:slc#37 TYPE READSLICE PAR 0-7009 XREFS 46995 LOC {1 0.187338 1 0.2761144 1 0.2761144 1 0.41251422499999996} PREDS {{259 0 0-7285 {}}} SUCCS {{258 0 0-7289 {}}} CYCLES {}}
+set a(0-7287) {NAME ACC1-1:slc(acc#25.psp)#9 TYPE READSLICE PAR 0-7009 XREFS 46996 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.41251422499999996} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-7288 {}}} CYCLES {}}
+set a(0-7288) {NAME ACC1-1:not#224 TYPE NOT PAR 0-7009 XREFS 46997 LOC {1 0.14655495 1 0.2761144 1 0.2761144 1 0.41251422499999996} PREDS {{259 0 0-7287 {}}} SUCCS {{259 0 0-7289 {}}} CYCLES {}}
+set a(0-7289) {NAME ACC1:conc#1189 TYPE CONCATENATE PAR 0-7009 XREFS 46998 LOC {1 0.187338 1 0.2761144 1 0.2761144 1 0.41251422499999996} PREDS {{258 0 0-7286 {}} {259 0 0-7288 {}}} SUCCS {{259 0 0-7290 {}}} CYCLES {}}
+set a(0-7290) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#364 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 46999 LOC {1 0.187338 1 0.2761144 1 0.2761144 1 0.32367052707082716 1 0.46007035207082714} PREDS {{258 0 0-7278 {}} {259 0 0-7289 {}}} SUCCS {{259 0 0-7291 {}}} CYCLES {}}
+set a(0-7291) {NAME ACC1:slc#40 TYPE READSLICE PAR 0-7009 XREFS 47000 LOC {1 0.23489417499999998 1 0.32367057499999996 1 0.32367057499999996 1 0.4600704} PREDS {{259 0 0-7290 {}}} SUCCS {{259 0 0-7292 {}}} CYCLES {}}
+set a(0-7292) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1-1:acc#208 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 47001 LOC {1 0.23489417499999998 1 0.32367057499999996 1 0.32367057499999996 1 0.3567073451789505 1 0.4931071701789505} PREDS {{258 0 0-7268 {}} {259 0 0-7291 {}}} SUCCS {{259 0 0-7293 {}} {258 0 0-7295 {}} {258 0 0-7297 {}} {258 0 0-7301 {}} {258 0 0-9062 {}} {258 0 0-9073 {}} {258 0 0-9082 {}} {258 0 0-9199 {}}} CYCLES {}}
+set a(0-7293) {NAME ACC1-1:slc(ACC1:acc#208.psp) TYPE READSLICE PAR 0-7009 XREFS 47002 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{259 0 0-7292 {}}} SUCCS {{259 0 0-7294 {}}} CYCLES {}}
+set a(0-7294) {NAME ACC1:conc#1192 TYPE CONCATENATE PAR 0-7009 XREFS 47003 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{259 0 0-7293 {}}} SUCCS {{258 0 0-7299 {}}} CYCLES {}}
+set a(0-7295) {NAME ACC1-1:slc(ACC1:acc#208.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47004 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{258 0 0-7292 {}}} SUCCS {{259 0 0-7296 {}}} CYCLES {}}
+set a(0-7296) {NAME ACC1-1:not#269 TYPE NOT PAR 0-7009 XREFS 47005 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{259 0 0-7295 {}}} SUCCS {{258 0 0-7298 {}}} CYCLES {}}
+set a(0-7297) {NAME ACC1-1:slc(ACC1:acc#208.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 47006 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{258 0 0-7292 {}}} SUCCS {{259 0 0-7298 {}}} CYCLES {}}
+set a(0-7298) {NAME ACC1:conc#1193 TYPE CONCATENATE PAR 0-7009 XREFS 47007 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{258 0 0-7296 {}} {259 0 0-7297 {}}} SUCCS {{259 0 0-7299 {}}} CYCLES {}}
+set a(0-7299) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#366 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47008 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.3974904100894753 1 0.5338902350894752} PREDS {{258 0 0-7294 {}} {259 0 0-7298 {}}} SUCCS {{259 0 0-7300 {}}} CYCLES {}}
+set a(0-7300) {NAME ACC1:slc#42 TYPE READSLICE PAR 0-7009 XREFS 47009 LOC {1 0.30871404999999996 1 0.39749045 1 0.39749045 1 0.533890275} PREDS {{259 0 0-7299 {}}} SUCCS {{258 0 0-7303 {}}} CYCLES {}}
+set a(0-7301) {NAME ACC1-1:slc(ACC1:acc#208.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 47010 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.533890275} PREDS {{258 0 0-7292 {}}} SUCCS {{259 0 0-7302 {}}} CYCLES {}}
+set a(0-7302) {NAME ACC1:not#317 TYPE NOT PAR 0-7009 XREFS 47011 LOC {1 0.267931 1 0.39749045 1 0.39749045 1 0.533890275} PREDS {{259 0 0-7301 {}}} SUCCS {{259 0 0-7303 {}}} CYCLES {}}
+set a(0-7303) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-1:acc#219 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47012 LOC {1 0.30871404999999996 1 0.39749045 1 0.39749045 1 0.41796321008947523 1 0.5543630350894753} PREDS {{258 0 0-7300 {}} {259 0 0-7302 {}}} SUCCS {{259 0 0-7304 {}} {258 0 0-7307 {}} {258 0 0-9231 {}}} CYCLES {}}
+set a(0-7304) {NAME ACC1-1:slc(ACC1:acc#219.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47013 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-7303 {}}} SUCCS {{259 0 0-7305 {}}} CYCLES {}}
+set a(0-7305) {NAME ACC1-1:not#291 TYPE NOT PAR 0-7009 XREFS 47014 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-7304 {}}} SUCCS {{259 0 0-7306 {}}} CYCLES {}}
+set a(0-7306) {NAME ACC1:conc#1194 TYPE CONCATENATE PAR 0-7009 XREFS 47015 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-7305 {}}} SUCCS {{258 0 0-7309 {}}} CYCLES {}}
+set a(0-7307) {NAME ACC1-1:slc(ACC1:acc#219.psp) TYPE READSLICE PAR 0-7009 XREFS 47016 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{258 0 0-7303 {}}} SUCCS {{259 0 0-7308 {}}} CYCLES {}}
+set a(0-7308) {NAME ACC1:conc#1195 TYPE CONCATENATE PAR 0-7009 XREFS 47017 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-7307 {}}} SUCCS {{259 0 0-7309 {}}} CYCLES {}}
+set a(0-7309) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#367 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47018 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.44520912707082716 1 0.5816089520708271} PREDS {{258 0 0-7306 {}} {259 0 0-7308 {}}} SUCCS {{259 0 0-7310 {}}} CYCLES {}}
+set a(0-7310) {NAME ACC1:slc#43 TYPE READSLICE PAR 0-7009 XREFS 47019 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-7309 {}}} SUCCS {{259 0 0-7311 {}} {258 0 0-7313 {}} {258 0 0-7315 {}} {258 0 0-8111 {}} {258 0 0-9053 {}}} CYCLES {}}
+set a(0-7311) {NAME ACC1-1:slc(acc.imod#22) TYPE READSLICE PAR 0-7009 XREFS 47020 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-7310 {}}} SUCCS {{259 0 0-7312 {}}} CYCLES {}}
+set a(0-7312) {NAME ACC1:conc#1197 TYPE CONCATENATE PAR 0-7009 XREFS 47021 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-7311 {}}} SUCCS {{258 0 0-7318 {}}} CYCLES {}}
+set a(0-7313) {NAME ACC1-1:slc(acc.imod#22)#1 TYPE READSLICE PAR 0-7009 XREFS 47022 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-7310 {}}} SUCCS {{259 0 0-7314 {}}} CYCLES {}}
+set a(0-7314) {NAME ACC1-1:not#185 TYPE NOT PAR 0-7009 XREFS 47023 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-7313 {}}} SUCCS {{258 0 0-7317 {}}} CYCLES {}}
+set a(0-7315) {NAME ACC1-1:slc(acc.imod#22)#2 TYPE READSLICE PAR 0-7009 XREFS 47024 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-7310 {}}} SUCCS {{259 0 0-7316 {}}} CYCLES {}}
+set a(0-7316) {NAME ACC1-1:not#186 TYPE NOT PAR 0-7009 XREFS 47025 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-7315 {}}} SUCCS {{259 0 0-7317 {}}} CYCLES {}}
+set a(0-7317) {NAME ACC1:conc#1198 TYPE CONCATENATE PAR 0-7009 XREFS 47026 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-7314 {}} {259 0 0-7316 {}}} SUCCS {{259 0 0-7318 {}}} CYCLES {}}
+set a(0-7318) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#368 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47027 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.47245505207082716 1 0.6088548770708271} PREDS {{258 0 0-7312 {}} {259 0 0-7317 {}}} SUCCS {{259 0 0-7319 {}}} CYCLES {}}
+set a(0-7319) {NAME ACC1:slc#44 TYPE READSLICE PAR 0-7009 XREFS 47028 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-7318 {}}} SUCCS {{258 0 0-9028 {}} {258 0 0-9030 {}} {258 0 0-9040 {}}} CYCLES {}}
+set a(0-7320) {NAME regs.regs:asn TYPE ASSIGN PAR 0-7009 XREFS 47029 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-9348 {}}} SUCCS {{259 0 0-7321 {}} {256 0 0-9348 {}}} CYCLES {}}
+set a(0-7321) {NAME regs.regs:slc(regs.regs(1))#3 TYPE READSLICE PAR 0-7009 XREFS 47030 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-7320 {}}} SUCCS {{259 0 0-7322 {}}} CYCLES {}}
+set a(0-7322) {NAME ACC1:not#309 TYPE NOT PAR 0-7009 XREFS 47031 LOC {0 1.0 1 0.05572455 1 0.05572455 1 0.05572455} PREDS {{259 0 0-7321 {}}} SUCCS {{258 0 0-7326 {}}} CYCLES {}}
+set a(0-7323) {NAME regs.regs:asn#1 TYPE ASSIGN PAR 0-7009 XREFS 47032 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-9348 {}}} SUCCS {{259 0 0-7324 {}} {256 0 0-9348 {}}} CYCLES {}}
+set a(0-7324) {NAME regs.regs:slc(regs.regs(1))#4 TYPE READSLICE PAR 0-7009 XREFS 47033 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-7323 {}}} SUCCS {{259 0 0-7325 {}}} CYCLES {}}
+set a(0-7325) {NAME ACC1:not#310 TYPE NOT PAR 0-7009 XREFS 47034 LOC {0 1.0 1 0.05572455 1 0.05572455 1 0.05572455} PREDS {{259 0 0-7324 {}}} SUCCS {{259 0 0-7326 {}}} CYCLES {}}
+set a(0-7326) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#370 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 47035 LOC {1 0.0 1 0.05572455 1 0.05572455 1 0.12690865333641133 1 0.12690865333641133} PREDS {{258 0 0-7322 {}} {259 0 0-7325 {}}} SUCCS {{258 0 0-7331 {}}} CYCLES {}}
+set a(0-7327) {NAME regs.regs:asn#2 TYPE ASSIGN PAR 0-7009 XREFS 47036 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-9348 {}}} SUCCS {{259 0 0-7328 {}} {256 0 0-9348 {}}} CYCLES {}}
+set a(0-7328) {NAME regs.regs:slc(regs.regs(1))#5 TYPE READSLICE PAR 0-7009 XREFS 47037 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-7327 {}}} SUCCS {{259 0 0-7329 {}}} CYCLES {}}
+set a(0-7329) {NAME ACC1:not#311 TYPE NOT PAR 0-7009 XREFS 47038 LOC {0 1.0 1 0.05572455 1 0.05572455 1 0.05572455} PREDS {{259 0 0-7328 {}}} SUCCS {{259 0 0-7330 {}}} CYCLES {}}
+set a(0-7330) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#369 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 47039 LOC {1 0.0 1 0.05572455 1 0.05572455 1 0.12690865333641133 1 0.12690865333641133} PREDS {{259 0 0-7329 {}}} SUCCS {{259 0 0-7331 {}}} CYCLES {}}
+set a(0-7331) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1:acc#228 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 47040 LOC {1 0.07118415 1 0.12690869999999999 1 0.12690869999999999 1 0.20227945637342837 1 0.20227945637342837} PREDS {{258 0 0-7326 {}} {259 0 0-7330 {}}} SUCCS {{259 0 0-7332 {}} {258 0 0-7335 {}} {258 0 0-7337 {}} {258 0 0-7339 {}} {258 0 0-7344 {}} {258 0 0-7350 {}} {258 0 0-7352 {}} {258 0 0-7354 {}} {258 0 0-7359 {}} {258 0 0-7361 {}} {258 0 0-7365 {}} {258 0 0-7781 {}} {258 0 0-8085 {}} {258 0 0-8091 {}} {258 0 0-8097 {}} {258 0 0-8102 {}} {258 0 0-8116 {}} {258 0 0-8157 {}} {258 0 0-8169 {}} {258 0 0-8179 {}} {258 0 0-8196 {}} {258 0 0-8215 {}} {258 0 0-8236 {}} {258 0 0-8245 {}} {258 0 0-8388 {}} {258 0 0-8403 {}} {258 0 0-8527 {}} {258 0 0-8574 {}} {258 0 0-8618 {}} {258 0 0-8633 {}} {258 0 0-8682 {}} {258 0 0-8683 {}} {258 0 0-8731 {}} {258 0 0-9121 {}} {258 0 0-9123 {}} {258 0 0-9126 {}} {258 0 0-9128 {}} {258 0 0-9132 {}} {258 0 0-9134 {}} {258 0 0-9137 {}} {258 0 0-9139 {}} {258 0 0-9144 {}} {258 0 0-9146 {}} {258 0 0-9149 {}} {258 0 0-9151 {}} {258 0 0-9215 {}} {258 0 0-9252 {}} {258 0 0-9267 {}}} CYCLES {}}
+set a(0-7332) {NAME ACC1:slc(acc#5.psp#2)#1 TYPE READSLICE PAR 0-7009 XREFS 47041 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306255} PREDS {{259 0 0-7331 {}}} SUCCS {{259 0 0-7333 {}}} CYCLES {}}
+set a(0-7333) {NAME ACC1-2:not#238 TYPE NOT PAR 0-7009 XREFS 47042 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-7332 {}}} SUCCS {{259 0 0-7334 {}}} CYCLES {}}
+set a(0-7334) {NAME ACC1:conc#1206 TYPE CONCATENATE PAR 0-7009 XREFS 47043 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-7333 {}}} SUCCS {{258 0 0-7347 {}}} CYCLES {}}
+set a(0-7335) {NAME ACC1:slc(acc#5.psp#2)#2 TYPE READSLICE PAR 0-7009 XREFS 47044 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-7336 {}}} CYCLES {}}
+set a(0-7336) {NAME ACC1:conc#1202 TYPE CONCATENATE PAR 0-7009 XREFS 47045 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-7335 {}}} SUCCS {{258 0 0-7342 {}}} CYCLES {}}
+set a(0-7337) {NAME ACC1:slc(acc#5.psp#2)#3 TYPE READSLICE PAR 0-7009 XREFS 47046 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-7338 {}}} CYCLES {}}
+set a(0-7338) {NAME ACC1-2:not#239 TYPE NOT PAR 0-7009 XREFS 47047 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-7337 {}}} SUCCS {{258 0 0-7341 {}}} CYCLES {}}
+set a(0-7339) {NAME ACC1:slc(acc#5.psp#2)#7 TYPE READSLICE PAR 0-7009 XREFS 47048 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-7340 {}}} CYCLES {}}
+set a(0-7340) {NAME ACC1-2:not#241 TYPE NOT PAR 0-7009 XREFS 47049 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-7339 {}}} SUCCS {{259 0 0-7341 {}}} CYCLES {}}
+set a(0-7341) {NAME ACC1:conc#1203 TYPE CONCATENATE PAR 0-7009 XREFS 47050 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-7338 {}} {259 0 0-7340 {}}} SUCCS {{259 0 0-7342 {}}} CYCLES {}}
+set a(0-7342) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#372 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47051 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306251008947524 1 0.24306251008947524} PREDS {{258 0 0-7336 {}} {259 0 0-7341 {}}} SUCCS {{259 0 0-7343 {}}} CYCLES {}}
+set a(0-7343) {NAME ACC1:slc#46 TYPE READSLICE PAR 0-7009 XREFS 47052 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-7342 {}}} SUCCS {{258 0 0-7346 {}}} CYCLES {}}
+set a(0-7344) {NAME ACC1:slc(acc#5.psp#2)#9 TYPE READSLICE PAR 0-7009 XREFS 47053 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306255} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-7345 {}}} CYCLES {}}
+set a(0-7345) {NAME ACC1-2:not#242 TYPE NOT PAR 0-7009 XREFS 47054 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-7344 {}}} SUCCS {{259 0 0-7346 {}}} CYCLES {}}
+set a(0-7346) {NAME ACC1:conc#1207 TYPE CONCATENATE PAR 0-7009 XREFS 47055 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{258 0 0-7343 {}} {259 0 0-7345 {}}} SUCCS {{259 0 0-7347 {}}} CYCLES {}}
+set a(0-7347) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#374 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 47056 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.2760993201789505 1 0.2760993201789505} PREDS {{258 0 0-7334 {}} {259 0 0-7346 {}}} SUCCS {{259 0 0-7348 {}}} CYCLES {}}
+set a(0-7348) {NAME ACC1:slc#48 TYPE READSLICE PAR 0-7009 XREFS 47057 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-7347 {}}} SUCCS {{259 0 0-7349 {}}} CYCLES {}}
+set a(0-7349) {NAME ACC1:conc#1208 TYPE CONCATENATE PAR 0-7009 XREFS 47058 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-7348 {}}} SUCCS {{258 0 0-7367 {}}} CYCLES {}}
+set a(0-7350) {NAME ACC1:slc(acc#5.psp#2)#4 TYPE READSLICE PAR 0-7009 XREFS 47059 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-7351 {}}} CYCLES {}}
+set a(0-7351) {NAME ACC1:conc#1200 TYPE CONCATENATE PAR 0-7009 XREFS 47060 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{259 0 0-7350 {}}} SUCCS {{258 0 0-7356 {}}} CYCLES {}}
+set a(0-7352) {NAME ACC1:slc(acc#5.psp#2)#5 TYPE READSLICE PAR 0-7009 XREFS 47061 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-7353 {}}} CYCLES {}}
+set a(0-7353) {NAME ACC1-2:not#240 TYPE NOT PAR 0-7009 XREFS 47062 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{259 0 0-7352 {}}} SUCCS {{258 0 0-7355 {}}} CYCLES {}}
+set a(0-7354) {NAME ACC1:slc(acc#5.psp#2)#6 TYPE READSLICE PAR 0-7009 XREFS 47063 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-7355 {}}} CYCLES {}}
+set a(0-7355) {NAME ACC1:conc#1201 TYPE CONCATENATE PAR 0-7009 XREFS 47064 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{258 0 0-7353 {}} {259 0 0-7354 {}}} SUCCS {{259 0 0-7356 {}}} CYCLES {}}
+set a(0-7356) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#371 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47065 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.24885341008947523 1 0.24885341008947523} PREDS {{258 0 0-7351 {}} {259 0 0-7355 {}}} SUCCS {{259 0 0-7357 {}}} CYCLES {}}
+set a(0-7357) {NAME ACC1:slc#45 TYPE READSLICE PAR 0-7009 XREFS 47066 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-7356 {}}} SUCCS {{259 0 0-7358 {}}} CYCLES {}}
+set a(0-7358) {NAME ACC1:conc#1204 TYPE CONCATENATE PAR 0-7009 XREFS 47067 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-7357 {}}} SUCCS {{258 0 0-7363 {}}} CYCLES {}}
+set a(0-7359) {NAME ACC1:slc(acc#5.psp#2)#11 TYPE READSLICE PAR 0-7009 XREFS 47068 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24885344999999998} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-7360 {}}} CYCLES {}}
+set a(0-7360) {NAME ACC1-2:not#243 TYPE NOT PAR 0-7009 XREFS 47069 LOC {1 0.14655495 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-7359 {}}} SUCCS {{258 0 0-7362 {}}} CYCLES {}}
+set a(0-7361) {NAME ACC1:slc(acc#5.psp#2)#8 TYPE READSLICE PAR 0-7009 XREFS 47070 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24885344999999998} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-7362 {}}} CYCLES {}}
+set a(0-7362) {NAME ACC1:conc#1205 TYPE CONCATENATE PAR 0-7009 XREFS 47071 LOC {1 0.14655495 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{258 0 0-7360 {}} {259 0 0-7361 {}}} SUCCS {{259 0 0-7363 {}}} CYCLES {}}
+set a(0-7363) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#373 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47072 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.2760993270708272 1 0.2760993270708272} PREDS {{258 0 0-7358 {}} {259 0 0-7362 {}}} SUCCS {{259 0 0-7364 {}}} CYCLES {}}
+set a(0-7364) {NAME ACC1:slc#47 TYPE READSLICE PAR 0-7009 XREFS 47073 LOC {1 0.21458392499999998 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-7363 {}}} SUCCS {{258 0 0-7366 {}}} CYCLES {}}
+set a(0-7365) {NAME ACC1:slc(acc#5.psp#2)#10 TYPE READSLICE PAR 0-7009 XREFS 47074 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.276099375} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-7366 {}}} CYCLES {}}
+set a(0-7366) {NAME ACC1:conc#1209 TYPE CONCATENATE PAR 0-7009 XREFS 47075 LOC {1 0.21458392499999998 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{258 0 0-7364 {}} {259 0 0-7365 {}}} SUCCS {{259 0 0-7367 {}}} CYCLES {}}
+set a(0-7367) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#375 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-7009 XREFS 47076 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.31438883449693605 1 0.31438883449693605} PREDS {{258 0 0-7349 {}} {259 0 0-7366 {}}} SUCCS {{259 0 0-7368 {}}} CYCLES {}}
+set a(0-7368) {NAME ACC1:slc#49 TYPE READSLICE PAR 0-7009 XREFS 47077 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7367 {}}} SUCCS {{259 0 0-7369 {}} {258 0 0-7371 {}} {258 0 0-7373 {}} {258 0 0-7377 {}} {258 0 0-8414 {}} {258 0 0-8427 {}} {258 0 0-8436 {}} {258 0 0-9176 {}}} CYCLES {}}
+set a(0-7369) {NAME ACC1-2:slc(ACC1:acc#212.psp) TYPE READSLICE PAR 0-7009 XREFS 47078 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7368 {}}} SUCCS {{259 0 0-7370 {}}} CYCLES {}}
+set a(0-7370) {NAME ACC1:conc#1210 TYPE CONCATENATE PAR 0-7009 XREFS 47079 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7369 {}}} SUCCS {{258 0 0-7375 {}}} CYCLES {}}
+set a(0-7371) {NAME ACC1-2:slc(ACC1:acc#212.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47080 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7368 {}}} SUCCS {{259 0 0-7372 {}}} CYCLES {}}
+set a(0-7372) {NAME ACC1-2:not#277 TYPE NOT PAR 0-7009 XREFS 47081 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7371 {}}} SUCCS {{258 0 0-7374 {}}} CYCLES {}}
+set a(0-7373) {NAME ACC1-2:slc(ACC1:acc#212.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 47082 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7368 {}}} SUCCS {{259 0 0-7374 {}}} CYCLES {}}
+set a(0-7374) {NAME ACC1:conc#1211 TYPE CONCATENATE PAR 0-7009 XREFS 47083 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7372 {}} {259 0 0-7373 {}}} SUCCS {{259 0 0-7375 {}}} CYCLES {}}
+set a(0-7375) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#376 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47084 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.3551718850894753 1 0.3551718850894753} PREDS {{258 0 0-7370 {}} {259 0 0-7374 {}}} SUCCS {{259 0 0-7376 {}}} CYCLES {}}
+set a(0-7376) {NAME ACC1:slc#50 TYPE READSLICE PAR 0-7009 XREFS 47085 LOC {1 0.29944737499999996 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-7375 {}}} SUCCS {{258 0 0-7379 {}}} CYCLES {}}
+set a(0-7377) {NAME ACC1-2:slc(ACC1:acc#212.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 47086 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.355171925} PREDS {{258 0 0-7368 {}}} SUCCS {{259 0 0-7378 {}}} CYCLES {}}
+set a(0-7378) {NAME ACC1:not#318 TYPE NOT PAR 0-7009 XREFS 47087 LOC {1 0.258664325 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-7377 {}}} SUCCS {{259 0 0-7379 {}}} CYCLES {}}
+set a(0-7379) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-2:acc#221 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47088 LOC {1 0.29944737499999996 1 0.355171925 1 0.355171925 1 0.37564468508947524 1 0.37564468508947524} PREDS {{258 0 0-7376 {}} {259 0 0-7378 {}}} SUCCS {{259 0 0-7380 {}} {258 0 0-7383 {}} {258 0 0-9214 {}}} CYCLES {}}
+set a(0-7380) {NAME ACC1-2:slc(ACC1:acc#221.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47089 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7379 {}}} SUCCS {{259 0 0-7381 {}}} CYCLES {}}
+set a(0-7381) {NAME ACC1-2:not#295 TYPE NOT PAR 0-7009 XREFS 47090 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7380 {}}} SUCCS {{259 0 0-7382 {}}} CYCLES {}}
+set a(0-7382) {NAME ACC1:conc#1212 TYPE CONCATENATE PAR 0-7009 XREFS 47091 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7381 {}}} SUCCS {{258 0 0-7385 {}}} CYCLES {}}
+set a(0-7383) {NAME ACC1-2:slc(ACC1:acc#221.psp) TYPE READSLICE PAR 0-7009 XREFS 47092 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{258 0 0-7379 {}}} SUCCS {{259 0 0-7384 {}}} CYCLES {}}
+set a(0-7384) {NAME ACC1:conc#1213 TYPE CONCATENATE PAR 0-7009 XREFS 47093 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7383 {}}} SUCCS {{259 0 0-7385 {}}} CYCLES {}}
+set a(0-7385) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#377 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47094 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.40289060207082716 1 0.40289060207082716} PREDS {{258 0 0-7382 {}} {259 0 0-7384 {}}} SUCCS {{259 0 0-7386 {}}} CYCLES {}}
+set a(0-7386) {NAME ACC1:slc#51 TYPE READSLICE PAR 0-7009 XREFS 47095 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7385 {}}} SUCCS {{259 0 0-7387 {}} {258 0 0-7389 {}} {258 0 0-7391 {}} {258 0 0-8145 {}} {258 0 0-9189 {}}} CYCLES {}}
+set a(0-7387) {NAME ACC1-2:slc(acc.imod#6) TYPE READSLICE PAR 0-7009 XREFS 47096 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7386 {}}} SUCCS {{259 0 0-7388 {}}} CYCLES {}}
+set a(0-7388) {NAME ACC1:conc#1215 TYPE CONCATENATE PAR 0-7009 XREFS 47097 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7387 {}}} SUCCS {{258 0 0-7394 {}}} CYCLES {}}
+set a(0-7389) {NAME ACC1-2:slc(acc.imod#6)#1 TYPE READSLICE PAR 0-7009 XREFS 47098 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7386 {}}} SUCCS {{259 0 0-7390 {}}} CYCLES {}}
+set a(0-7390) {NAME ACC1-2:not#57 TYPE NOT PAR 0-7009 XREFS 47099 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7389 {}}} SUCCS {{258 0 0-7393 {}}} CYCLES {}}
+set a(0-7391) {NAME ACC1-2:slc(acc.imod#6)#2 TYPE READSLICE PAR 0-7009 XREFS 47100 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7386 {}}} SUCCS {{259 0 0-7392 {}}} CYCLES {}}
+set a(0-7392) {NAME ACC1-2:not#58 TYPE NOT PAR 0-7009 XREFS 47101 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7391 {}}} SUCCS {{259 0 0-7393 {}}} CYCLES {}}
+set a(0-7393) {NAME ACC1:conc#1216 TYPE CONCATENATE PAR 0-7009 XREFS 47102 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7390 {}} {259 0 0-7392 {}}} SUCCS {{259 0 0-7394 {}}} CYCLES {}}
+set a(0-7394) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#378 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47103 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.43013652707082717 1 0.43013652707082717} PREDS {{258 0 0-7388 {}} {259 0 0-7393 {}}} SUCCS {{259 0 0-7395 {}}} CYCLES {}}
+set a(0-7395) {NAME ACC1:slc#52 TYPE READSLICE PAR 0-7009 XREFS 47104 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-7394 {}}} SUCCS {{258 0 0-8389 {}} {258 0 0-8391 {}} {258 0 0-8402 {}}} CYCLES {}}
+set a(0-7396) {NAME regs.regs:asn#3 TYPE ASSIGN PAR 0-7009 XREFS 47105 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-9348 {}}} SUCCS {{259 0 0-7397 {}} {256 0 0-9348 {}}} CYCLES {}}
+set a(0-7397) {NAME regs.regs:slc(regs.regs(1))#1 TYPE READSLICE PAR 0-7009 XREFS 47106 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-7396 {}}} SUCCS {{258 0 0-7400 {}}} CYCLES {}}
+set a(0-7398) {NAME regs.regs:asn#4 TYPE ASSIGN PAR 0-7009 XREFS 47107 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-9348 {}}} SUCCS {{259 0 0-7399 {}} {256 0 0-9348 {}}} CYCLES {}}
+set a(0-7399) {NAME regs.regs:slc(regs.regs(1))#2 TYPE READSLICE PAR 0-7009 XREFS 47108 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-7398 {}}} SUCCS {{259 0 0-7400 {}}} CYCLES {}}
+set a(0-7400) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#379 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 47109 LOC {1 0.0 1 0.05572455 1 0.05572455 1 0.12690865333641133 1 0.12690865333641133} PREDS {{258 0 0-7397 {}} {259 0 0-7399 {}}} SUCCS {{258 0 0-7403 {}}} CYCLES {}}
+set a(0-7401) {NAME regs.regs:asn#5 TYPE ASSIGN PAR 0-7009 XREFS 47110 LOC {0 1.0 0 1.0 0 1.0 1 0.12690869999999999} PREDS {{262 0 0-9348 {}}} SUCCS {{259 0 0-7402 {}} {256 0 0-9348 {}}} CYCLES {}}
+set a(0-7402) {NAME regs.regs:slc(regs.regs(1)) TYPE READSLICE PAR 0-7009 XREFS 47111 LOC {0 1.0 0 1.0 0 1.0 1 0.12690869999999999} PREDS {{259 0 0-7401 {}}} SUCCS {{259 0 0-7403 {}}} CYCLES {}}
+set a(0-7403) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1:acc#226 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 47112 LOC {1 0.07118415 1 0.12690869999999999 1 0.12690869999999999 1 0.20227945637342837 1 0.20227945637342837} PREDS {{258 0 0-7400 {}} {259 0 0-7402 {}}} SUCCS {{259 0 0-7404 {}} {258 0 0-7407 {}} {258 0 0-7409 {}} {258 0 0-7411 {}} {258 0 0-7416 {}} {258 0 0-7422 {}} {258 0 0-7424 {}} {258 0 0-7426 {}} {258 0 0-7431 {}} {258 0 0-7433 {}} {258 0 0-7437 {}} {258 0 0-7783 {}} {258 0 0-8090 {}} {258 0 0-8181 {}} {258 0 0-8198 {}} {258 0 0-8209 {}} {258 0 0-8210 {}} {258 0 0-8211 {}} {258 0 0-8217 {}} {258 0 0-8321 {}} {258 0 0-8338 {}} {258 0 0-8538 {}} {258 0 0-8578 {}} {258 0 0-8586 {}} {258 0 0-8590 {}} {258 0 0-8597 {}} {258 0 0-8622 {}} {258 0 0-8629 {}} {258 0 0-8641 {}} {258 0 0-8700 {}} {258 0 0-8701 {}} {258 0 0-8847 {}} {258 0 0-8849 {}} {258 0 0-8854 {}} {258 0 0-8856 {}} {258 0 0-8859 {}} {258 0 0-8861 {}} {258 0 0-8865 {}} {258 0 0-8867 {}} {258 0 0-8870 {}} {258 0 0-8872 {}} {258 0 0-8878 {}} {258 0 0-8880 {}} {258 0 0-8883 {}} {258 0 0-8885 {}} {258 0 0-8889 {}} {258 0 0-8891 {}} {258 0 0-8894 {}} {258 0 0-8896 {}} {258 0 0-9219 {}} {258 0 0-9254 {}}} CYCLES {}}
+set a(0-7404) {NAME ACC1:slc(acc#25.psp#2)#1 TYPE READSLICE PAR 0-7009 XREFS 47113 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306255} PREDS {{259 0 0-7403 {}}} SUCCS {{259 0 0-7405 {}}} CYCLES {}}
+set a(0-7405) {NAME ACC1-2:not#220 TYPE NOT PAR 0-7009 XREFS 47114 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-7404 {}}} SUCCS {{259 0 0-7406 {}}} CYCLES {}}
+set a(0-7406) {NAME ACC1:conc#1224 TYPE CONCATENATE PAR 0-7009 XREFS 47115 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-7405 {}}} SUCCS {{258 0 0-7419 {}}} CYCLES {}}
+set a(0-7407) {NAME ACC1:slc(acc#25.psp#2)#2 TYPE READSLICE PAR 0-7009 XREFS 47116 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-7408 {}}} CYCLES {}}
+set a(0-7408) {NAME ACC1:conc#1220 TYPE CONCATENATE PAR 0-7009 XREFS 47117 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-7407 {}}} SUCCS {{258 0 0-7414 {}}} CYCLES {}}
+set a(0-7409) {NAME ACC1:slc(acc#25.psp#2)#3 TYPE READSLICE PAR 0-7009 XREFS 47118 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-7410 {}}} CYCLES {}}
+set a(0-7410) {NAME ACC1-2:not#221 TYPE NOT PAR 0-7009 XREFS 47119 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-7409 {}}} SUCCS {{258 0 0-7413 {}}} CYCLES {}}
+set a(0-7411) {NAME ACC1:slc(acc#25.psp#2)#7 TYPE READSLICE PAR 0-7009 XREFS 47120 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-7412 {}}} CYCLES {}}
+set a(0-7412) {NAME ACC1-2:not#223 TYPE NOT PAR 0-7009 XREFS 47121 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-7411 {}}} SUCCS {{259 0 0-7413 {}}} CYCLES {}}
+set a(0-7413) {NAME ACC1:conc#1221 TYPE CONCATENATE PAR 0-7009 XREFS 47122 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-7410 {}} {259 0 0-7412 {}}} SUCCS {{259 0 0-7414 {}}} CYCLES {}}
+set a(0-7414) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#381 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47123 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306251008947524 1 0.24306251008947524} PREDS {{258 0 0-7408 {}} {259 0 0-7413 {}}} SUCCS {{259 0 0-7415 {}}} CYCLES {}}
+set a(0-7415) {NAME ACC1:slc#54 TYPE READSLICE PAR 0-7009 XREFS 47124 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-7414 {}}} SUCCS {{258 0 0-7418 {}}} CYCLES {}}
+set a(0-7416) {NAME ACC1:slc(acc#25.psp#2)#9 TYPE READSLICE PAR 0-7009 XREFS 47125 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306255} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-7417 {}}} CYCLES {}}
+set a(0-7417) {NAME ACC1-2:not#224 TYPE NOT PAR 0-7009 XREFS 47126 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-7416 {}}} SUCCS {{259 0 0-7418 {}}} CYCLES {}}
+set a(0-7418) {NAME ACC1:conc#1225 TYPE CONCATENATE PAR 0-7009 XREFS 47127 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{258 0 0-7415 {}} {259 0 0-7417 {}}} SUCCS {{259 0 0-7419 {}}} CYCLES {}}
+set a(0-7419) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#383 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 47128 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.2760993201789505 1 0.2760993201789505} PREDS {{258 0 0-7406 {}} {259 0 0-7418 {}}} SUCCS {{259 0 0-7420 {}}} CYCLES {}}
+set a(0-7420) {NAME ACC1:slc#56 TYPE READSLICE PAR 0-7009 XREFS 47129 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-7419 {}}} SUCCS {{259 0 0-7421 {}}} CYCLES {}}
+set a(0-7421) {NAME ACC1:conc#1226 TYPE CONCATENATE PAR 0-7009 XREFS 47130 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-7420 {}}} SUCCS {{258 0 0-7439 {}}} CYCLES {}}
+set a(0-7422) {NAME ACC1:slc(acc#25.psp#2)#4 TYPE READSLICE PAR 0-7009 XREFS 47131 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-7423 {}}} CYCLES {}}
+set a(0-7423) {NAME ACC1:conc#1218 TYPE CONCATENATE PAR 0-7009 XREFS 47132 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{259 0 0-7422 {}}} SUCCS {{258 0 0-7428 {}}} CYCLES {}}
+set a(0-7424) {NAME ACC1:slc(acc#25.psp#2)#5 TYPE READSLICE PAR 0-7009 XREFS 47133 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-7425 {}}} CYCLES {}}
+set a(0-7425) {NAME ACC1-2:not#222 TYPE NOT PAR 0-7009 XREFS 47134 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{259 0 0-7424 {}}} SUCCS {{258 0 0-7427 {}}} CYCLES {}}
+set a(0-7426) {NAME ACC1:slc(acc#25.psp#2)#6 TYPE READSLICE PAR 0-7009 XREFS 47135 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-7427 {}}} CYCLES {}}
+set a(0-7427) {NAME ACC1:conc#1219 TYPE CONCATENATE PAR 0-7009 XREFS 47136 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{258 0 0-7425 {}} {259 0 0-7426 {}}} SUCCS {{259 0 0-7428 {}}} CYCLES {}}
+set a(0-7428) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#380 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47137 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.24885341008947523 1 0.24885341008947523} PREDS {{258 0 0-7423 {}} {259 0 0-7427 {}}} SUCCS {{259 0 0-7429 {}}} CYCLES {}}
+set a(0-7429) {NAME ACC1:slc#53 TYPE READSLICE PAR 0-7009 XREFS 47138 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-7428 {}}} SUCCS {{259 0 0-7430 {}}} CYCLES {}}
+set a(0-7430) {NAME ACC1:conc#1222 TYPE CONCATENATE PAR 0-7009 XREFS 47139 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-7429 {}}} SUCCS {{258 0 0-7435 {}}} CYCLES {}}
+set a(0-7431) {NAME ACC1:slc(acc#25.psp#2)#11 TYPE READSLICE PAR 0-7009 XREFS 47140 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24885344999999998} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-7432 {}}} CYCLES {}}
+set a(0-7432) {NAME ACC1-2:not#225 TYPE NOT PAR 0-7009 XREFS 47141 LOC {1 0.14655495 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-7431 {}}} SUCCS {{258 0 0-7434 {}}} CYCLES {}}
+set a(0-7433) {NAME ACC1:slc(acc#25.psp#2)#8 TYPE READSLICE PAR 0-7009 XREFS 47142 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24885344999999998} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-7434 {}}} CYCLES {}}
+set a(0-7434) {NAME ACC1:conc#1223 TYPE CONCATENATE PAR 0-7009 XREFS 47143 LOC {1 0.14655495 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{258 0 0-7432 {}} {259 0 0-7433 {}}} SUCCS {{259 0 0-7435 {}}} CYCLES {}}
+set a(0-7435) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#382 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47144 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.2760993270708272 1 0.2760993270708272} PREDS {{258 0 0-7430 {}} {259 0 0-7434 {}}} SUCCS {{259 0 0-7436 {}}} CYCLES {}}
+set a(0-7436) {NAME ACC1:slc#55 TYPE READSLICE PAR 0-7009 XREFS 47145 LOC {1 0.21458392499999998 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-7435 {}}} SUCCS {{258 0 0-7438 {}}} CYCLES {}}
+set a(0-7437) {NAME ACC1:slc(acc#25.psp#2)#10 TYPE READSLICE PAR 0-7009 XREFS 47146 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.276099375} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-7438 {}}} CYCLES {}}
+set a(0-7438) {NAME ACC1:conc#1227 TYPE CONCATENATE PAR 0-7009 XREFS 47147 LOC {1 0.21458392499999998 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{258 0 0-7436 {}} {259 0 0-7437 {}}} SUCCS {{259 0 0-7439 {}}} CYCLES {}}
+set a(0-7439) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#384 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-7009 XREFS 47148 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.31438883449693605 1 0.31438883449693605} PREDS {{258 0 0-7421 {}} {259 0 0-7438 {}}} SUCCS {{259 0 0-7440 {}}} CYCLES {}}
+set a(0-7440) {NAME ACC1:slc#57 TYPE READSLICE PAR 0-7009 XREFS 47149 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7439 {}}} SUCCS {{259 0 0-7441 {}} {258 0 0-7443 {}} {258 0 0-7445 {}} {258 0 0-7449 {}} {258 0 0-8359 {}} {258 0 0-8368 {}} {258 0 0-8379 {}} {258 0 0-9182 {}}} CYCLES {}}
+set a(0-7441) {NAME ACC1-2:slc(ACC1:acc#208.psp) TYPE READSLICE PAR 0-7009 XREFS 47150 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7440 {}}} SUCCS {{259 0 0-7442 {}}} CYCLES {}}
+set a(0-7442) {NAME ACC1:conc#1228 TYPE CONCATENATE PAR 0-7009 XREFS 47151 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7441 {}}} SUCCS {{258 0 0-7447 {}}} CYCLES {}}
+set a(0-7443) {NAME ACC1-2:slc(ACC1:acc#208.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47152 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7440 {}}} SUCCS {{259 0 0-7444 {}}} CYCLES {}}
+set a(0-7444) {NAME ACC1-2:not#269 TYPE NOT PAR 0-7009 XREFS 47153 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7443 {}}} SUCCS {{258 0 0-7446 {}}} CYCLES {}}
+set a(0-7445) {NAME ACC1-2:slc(ACC1:acc#208.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 47154 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7440 {}}} SUCCS {{259 0 0-7446 {}}} CYCLES {}}
+set a(0-7446) {NAME ACC1:conc#1229 TYPE CONCATENATE PAR 0-7009 XREFS 47155 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7444 {}} {259 0 0-7445 {}}} SUCCS {{259 0 0-7447 {}}} CYCLES {}}
+set a(0-7447) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#385 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47156 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.3551718850894753 1 0.3551718850894753} PREDS {{258 0 0-7442 {}} {259 0 0-7446 {}}} SUCCS {{259 0 0-7448 {}}} CYCLES {}}
+set a(0-7448) {NAME ACC1:slc#58 TYPE READSLICE PAR 0-7009 XREFS 47157 LOC {1 0.29944737499999996 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-7447 {}}} SUCCS {{258 0 0-7451 {}}} CYCLES {}}
+set a(0-7449) {NAME ACC1-2:slc(ACC1:acc#208.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 47158 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.355171925} PREDS {{258 0 0-7440 {}}} SUCCS {{259 0 0-7450 {}}} CYCLES {}}
+set a(0-7450) {NAME ACC1:not#319 TYPE NOT PAR 0-7009 XREFS 47159 LOC {1 0.258664325 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-7449 {}}} SUCCS {{259 0 0-7451 {}}} CYCLES {}}
+set a(0-7451) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-2:acc#219 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47160 LOC {1 0.29944737499999996 1 0.355171925 1 0.355171925 1 0.37564468508947524 1 0.37564468508947524} PREDS {{258 0 0-7448 {}} {259 0 0-7450 {}}} SUCCS {{259 0 0-7452 {}} {258 0 0-7455 {}} {258 0 0-9218 {}}} CYCLES {}}
+set a(0-7452) {NAME ACC1-2:slc(ACC1:acc#219.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47161 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7451 {}}} SUCCS {{259 0 0-7453 {}}} CYCLES {}}
+set a(0-7453) {NAME ACC1-2:not#291 TYPE NOT PAR 0-7009 XREFS 47162 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7452 {}}} SUCCS {{259 0 0-7454 {}}} CYCLES {}}
+set a(0-7454) {NAME ACC1:conc#1230 TYPE CONCATENATE PAR 0-7009 XREFS 47163 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7453 {}}} SUCCS {{258 0 0-7457 {}}} CYCLES {}}
+set a(0-7455) {NAME ACC1-2:slc(ACC1:acc#219.psp) TYPE READSLICE PAR 0-7009 XREFS 47164 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{258 0 0-7451 {}}} SUCCS {{259 0 0-7456 {}}} CYCLES {}}
+set a(0-7456) {NAME ACC1:conc#1231 TYPE CONCATENATE PAR 0-7009 XREFS 47165 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7455 {}}} SUCCS {{259 0 0-7457 {}}} CYCLES {}}
+set a(0-7457) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#386 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47166 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.40289060207082716 1 0.40289060207082716} PREDS {{258 0 0-7454 {}} {259 0 0-7456 {}}} SUCCS {{259 0 0-7458 {}}} CYCLES {}}
+set a(0-7458) {NAME ACC1:slc#59 TYPE READSLICE PAR 0-7009 XREFS 47167 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7457 {}}} SUCCS {{259 0 0-7459 {}} {258 0 0-7461 {}} {258 0 0-7463 {}} {258 0 0-8349 {}} {258 0 0-9196 {}}} CYCLES {}}
+set a(0-7459) {NAME ACC1-2:slc(acc.imod#22) TYPE READSLICE PAR 0-7009 XREFS 47168 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7458 {}}} SUCCS {{259 0 0-7460 {}}} CYCLES {}}
+set a(0-7460) {NAME ACC1:conc#1233 TYPE CONCATENATE PAR 0-7009 XREFS 47169 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7459 {}}} SUCCS {{258 0 0-7466 {}}} CYCLES {}}
+set a(0-7461) {NAME ACC1-2:slc(acc.imod#22)#1 TYPE READSLICE PAR 0-7009 XREFS 47170 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7458 {}}} SUCCS {{259 0 0-7462 {}}} CYCLES {}}
+set a(0-7462) {NAME ACC1-2:not#185 TYPE NOT PAR 0-7009 XREFS 47171 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7461 {}}} SUCCS {{258 0 0-7465 {}}} CYCLES {}}
+set a(0-7463) {NAME ACC1-2:slc(acc.imod#22)#2 TYPE READSLICE PAR 0-7009 XREFS 47172 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7458 {}}} SUCCS {{259 0 0-7464 {}}} CYCLES {}}
+set a(0-7464) {NAME ACC1-2:not#186 TYPE NOT PAR 0-7009 XREFS 47173 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7463 {}}} SUCCS {{259 0 0-7465 {}}} CYCLES {}}
+set a(0-7465) {NAME ACC1:conc#1234 TYPE CONCATENATE PAR 0-7009 XREFS 47174 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7462 {}} {259 0 0-7464 {}}} SUCCS {{259 0 0-7466 {}}} CYCLES {}}
+set a(0-7466) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#387 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47175 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.43013652707082717 1 0.43013652707082717} PREDS {{258 0 0-7460 {}} {259 0 0-7465 {}}} SUCCS {{259 0 0-7467 {}}} CYCLES {}}
+set a(0-7467) {NAME ACC1:slc#60 TYPE READSLICE PAR 0-7009 XREFS 47176 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-7466 {}}} SUCCS {{258 0 0-8322 {}} {258 0 0-8324 {}} {258 0 0-8337 {}}} CYCLES {}}
+set a(0-7468) {NAME regs.regs:asn#6 TYPE ASSIGN PAR 0-7009 XREFS 47177 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{262 0 0-9349 {}}} SUCCS {{259 0 0-7469 {}} {256 0 0-9349 {}}} CYCLES {}}
+set a(0-7469) {NAME regs.regs:slc(regs.regs(2))#7 TYPE READSLICE PAR 0-7009 XREFS 47178 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{259 0 0-7468 {}}} SUCCS {{258 0 0-7472 {}}} CYCLES {}}
+set a(0-7470) {NAME regs.regs:asn#7 TYPE ASSIGN PAR 0-7009 XREFS 47179 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{262 0 0-9349 {}}} SUCCS {{259 0 0-7471 {}} {256 0 0-9349 {}}} CYCLES {}}
+set a(0-7471) {NAME regs.regs:slc(regs.regs(2))#8 TYPE READSLICE PAR 0-7009 XREFS 47180 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{259 0 0-7470 {}}} SUCCS {{259 0 0-7472 {}}} CYCLES {}}
+set a(0-7472) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#388 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 47181 LOC {1 0.0 1 0.046457874999999996 1 0.046457874999999996 1 0.11764197833641131 1 0.11764197833641131} PREDS {{258 0 0-7469 {}} {259 0 0-7471 {}}} SUCCS {{258 0 0-7475 {}}} CYCLES {}}
+set a(0-7473) {NAME regs.regs:asn#8 TYPE ASSIGN PAR 0-7009 XREFS 47182 LOC {0 1.0 0 1.0 0 1.0 1 0.117642025} PREDS {{262 0 0-9349 {}}} SUCCS {{259 0 0-7474 {}} {256 0 0-9349 {}}} CYCLES {}}
+set a(0-7474) {NAME regs.regs:slc(regs.regs(2))#6 TYPE READSLICE PAR 0-7009 XREFS 47183 LOC {0 1.0 0 1.0 0 1.0 1 0.117642025} PREDS {{259 0 0-7473 {}}} SUCCS {{259 0 0-7475 {}}} CYCLES {}}
+set a(0-7475) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-3:acc TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 47184 LOC {1 0.07118415 1 0.117642025 1 0.117642025 1 0.19301278137342837 1 0.19301278137342837} PREDS {{258 0 0-7472 {}} {259 0 0-7474 {}}} SUCCS {{259 0 0-7476 {}} {258 0 0-7479 {}} {258 0 0-7481 {}} {258 0 0-7486 {}} {258 0 0-7488 {}} {258 0 0-7492 {}} {258 0 0-7494 {}} {258 0 0-7496 {}} {258 0 0-7502 {}} {258 0 0-7504 {}} {258 0 0-7506 {}} {258 0 0-7510 {}} {258 0 0-7777 {}} {258 0 0-8175 {}} {258 0 0-8192 {}} {258 0 0-8212 {}} {258 0 0-8222 {}} {258 0 0-8228 {}} {258 0 0-8363 {}} {258 0 0-8366 {}} {258 0 0-8374 {}} {258 0 0-8512 {}} {258 0 0-8515 {}} {258 0 0-8531 {}} {258 0 0-8539 {}} {258 0 0-8543 {}} {258 0 0-8550 {}} {258 0 0-8620 {}} {258 0 0-8647 {}} {258 0 0-8653 {}} {258 0 0-8669 {}} {258 0 0-8670 {}} {258 0 0-8923 {}} {258 0 0-8926 {}} {258 0 0-8936 {}} {258 0 0-8939 {}} {258 0 0-8945 {}} {258 0 0-8948 {}} {258 0 0-8955 {}} {258 0 0-8958 {}} {258 0 0-8964 {}} {258 0 0-8967 {}} {258 0 0-8975 {}} {258 0 0-8978 {}} {258 0 0-9160 {}} {258 0 0-9162 {}} {258 0 0-9223 {}} {258 0 0-9248 {}}} CYCLES {}}
+set a(0-7476) {NAME ACC1-3:slc(acc.psp)#11 TYPE READSLICE PAR 0-7009 XREFS 47185 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.2176873} PREDS {{259 0 0-7475 {}}} SUCCS {{259 0 0-7477 {}}} CYCLES {}}
+set a(0-7477) {NAME ACC1-3:not#302 TYPE NOT PAR 0-7009 XREFS 47186 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{259 0 0-7476 {}}} SUCCS {{259 0 0-7478 {}}} CYCLES {}}
+set a(0-7478) {NAME ACC1:conc#1240 TYPE CONCATENATE PAR 0-7009 XREFS 47187 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{259 0 0-7477 {}}} SUCCS {{258 0 0-7483 {}}} CYCLES {}}
+set a(0-7479) {NAME ACC1-3:slc(acc.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47188 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.2176873} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-7480 {}}} CYCLES {}}
+set a(0-7480) {NAME ACC1-3:not#229 TYPE NOT PAR 0-7009 XREFS 47189 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{259 0 0-7479 {}}} SUCCS {{258 0 0-7482 {}}} CYCLES {}}
+set a(0-7481) {NAME ACC1-3:slc(acc.psp)#8 TYPE READSLICE PAR 0-7009 XREFS 47190 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.2176873} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-7482 {}}} CYCLES {}}
+set a(0-7482) {NAME ACC1:conc#1241 TYPE CONCATENATE PAR 0-7009 XREFS 47191 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{258 0 0-7480 {}} {259 0 0-7481 {}}} SUCCS {{259 0 0-7483 {}}} CYCLES {}}
+set a(0-7483) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#391 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47192 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.23816006008947524 1 0.23816006008947524} PREDS {{258 0 0-7478 {}} {259 0 0-7482 {}}} SUCCS {{259 0 0-7484 {}}} CYCLES {}}
+set a(0-7484) {NAME ACC1:slc#63 TYPE READSLICE PAR 0-7009 XREFS 47193 LOC {1 0.16702775 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{259 0 0-7483 {}}} SUCCS {{259 0 0-7485 {}}} CYCLES {}}
+set a(0-7485) {NAME ACC1:conc#1244 TYPE CONCATENATE PAR 0-7009 XREFS 47194 LOC {1 0.16702775 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{259 0 0-7484 {}}} SUCCS {{258 0 0-7490 {}}} CYCLES {}}
+set a(0-7486) {NAME ACC1-3:slc(acc.psp) TYPE READSLICE PAR 0-7009 XREFS 47195 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23816009999999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-7487 {}}} CYCLES {}}
+set a(0-7487) {NAME ACC1:conc#1235 TYPE CONCATENATE PAR 0-7009 XREFS 47196 LOC {1 0.14655495 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{259 0 0-7486 {}}} SUCCS {{258 0 0-7489 {}}} CYCLES {}}
+set a(0-7488) {NAME ACC1-3:slc(acc.psp)#10 TYPE READSLICE PAR 0-7009 XREFS 47197 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23816009999999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-7489 {}}} CYCLES {}}
+set a(0-7489) {NAME ACC1:conc#1245 TYPE CONCATENATE PAR 0-7009 XREFS 47198 LOC {1 0.14655495 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{258 0 0-7487 {}} {259 0 0-7488 {}}} SUCCS {{259 0 0-7490 {}}} CYCLES {}}
+set a(0-7490) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#393 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 47199 LOC {1 0.16702775 1 0.23816009999999999 1 0.23816009999999999 1 0.2813519951789505 1 0.2813519951789505} PREDS {{258 0 0-7485 {}} {259 0 0-7489 {}}} SUCCS {{259 0 0-7491 {}}} CYCLES {}}
+set a(0-7491) {NAME ACC1:slc#65 TYPE READSLICE PAR 0-7009 XREFS 47200 LOC {1 0.21021969999999998 1 0.28135204999999996 1 0.28135204999999996 1 0.28135204999999996} PREDS {{259 0 0-7490 {}}} SUCCS {{258 0 0-7515 {}}} CYCLES {}}
+set a(0-7492) {NAME ACC1-3:slc(acc.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 47201 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-7493 {}}} CYCLES {}}
+set a(0-7493) {NAME ACC1:conc#1238 TYPE CONCATENATE PAR 0-7009 XREFS 47202 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-7492 {}}} SUCCS {{258 0 0-7499 {}}} CYCLES {}}
+set a(0-7494) {NAME ACC1-3:slc(acc.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 47203 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-7495 {}}} CYCLES {}}
+set a(0-7495) {NAME ACC1-3:not#230 TYPE NOT PAR 0-7009 XREFS 47204 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-7494 {}}} SUCCS {{258 0 0-7498 {}}} CYCLES {}}
+set a(0-7496) {NAME ACC1-3:slc(acc.psp)#7 TYPE READSLICE PAR 0-7009 XREFS 47205 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-7497 {}}} CYCLES {}}
+set a(0-7497) {NAME ACC1-3:not#232 TYPE NOT PAR 0-7009 XREFS 47206 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-7496 {}}} SUCCS {{259 0 0-7498 {}}} CYCLES {}}
+set a(0-7498) {NAME ACC1:conc#1239 TYPE CONCATENATE PAR 0-7009 XREFS 47207 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7495 {}} {259 0 0-7497 {}}} SUCCS {{259 0 0-7499 {}}} CYCLES {}}
+set a(0-7499) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#390 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47208 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23379583508947524 1 0.23379583508947524} PREDS {{258 0 0-7493 {}} {259 0 0-7498 {}}} SUCCS {{259 0 0-7500 {}}} CYCLES {}}
+set a(0-7500) {NAME ACC1:slc#62 TYPE READSLICE PAR 0-7009 XREFS 47209 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-7499 {}}} SUCCS {{259 0 0-7501 {}}} CYCLES {}}
+set a(0-7501) {NAME ACC1:conc#1242 TYPE CONCATENATE PAR 0-7009 XREFS 47210 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-7500 {}}} SUCCS {{258 0 0-7513 {}}} CYCLES {}}
+set a(0-7502) {NAME ACC1-3:slc(acc.psp)#4 TYPE READSLICE PAR 0-7009 XREFS 47211 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-7503 {}}} CYCLES {}}
+set a(0-7503) {NAME ACC1:conc#1236 TYPE CONCATENATE PAR 0-7009 XREFS 47212 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-7502 {}}} SUCCS {{258 0 0-7508 {}}} CYCLES {}}
+set a(0-7504) {NAME ACC1-3:slc(acc.psp)#5 TYPE READSLICE PAR 0-7009 XREFS 47213 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-7505 {}}} CYCLES {}}
+set a(0-7505) {NAME ACC1-3:not#231 TYPE NOT PAR 0-7009 XREFS 47214 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-7504 {}}} SUCCS {{258 0 0-7507 {}}} CYCLES {}}
+set a(0-7506) {NAME ACC1-3:slc(acc.psp)#6 TYPE READSLICE PAR 0-7009 XREFS 47215 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-7507 {}}} CYCLES {}}
+set a(0-7507) {NAME ACC1:conc#1237 TYPE CONCATENATE PAR 0-7009 XREFS 47216 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7505 {}} {259 0 0-7506 {}}} SUCCS {{259 0 0-7508 {}}} CYCLES {}}
+set a(0-7508) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#389 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47217 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23379583508947524 1 0.23379583508947524} PREDS {{258 0 0-7503 {}} {259 0 0-7507 {}}} SUCCS {{259 0 0-7509 {}}} CYCLES {}}
+set a(0-7509) {NAME ACC1:slc#61 TYPE READSLICE PAR 0-7009 XREFS 47218 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-7508 {}}} SUCCS {{258 0 0-7512 {}}} CYCLES {}}
+set a(0-7510) {NAME ACC1-3:slc(acc.psp)#9 TYPE READSLICE PAR 0-7009 XREFS 47219 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.233795875} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-7511 {}}} CYCLES {}}
+set a(0-7511) {NAME ACC1-3:not#233 TYPE NOT PAR 0-7009 XREFS 47220 LOC {1 0.14655495 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-7510 {}}} SUCCS {{259 0 0-7512 {}}} CYCLES {}}
+set a(0-7512) {NAME ACC1:conc#1243 TYPE CONCATENATE PAR 0-7009 XREFS 47221 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{258 0 0-7509 {}} {259 0 0-7511 {}}} SUCCS {{259 0 0-7513 {}}} CYCLES {}}
+set a(0-7513) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#392 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47222 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.28135200207082717 1 0.28135200207082717} PREDS {{258 0 0-7501 {}} {259 0 0-7512 {}}} SUCCS {{259 0 0-7514 {}}} CYCLES {}}
+set a(0-7514) {NAME ACC1:slc#64 TYPE READSLICE PAR 0-7009 XREFS 47223 LOC {1 0.23489417499999998 1 0.28135204999999996 1 0.28135204999999996 1 0.28135204999999996} PREDS {{259 0 0-7513 {}}} SUCCS {{259 0 0-7515 {}}} CYCLES {}}
+set a(0-7515) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1-3:acc#210 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 47224 LOC {1 0.23489417499999998 1 0.28135204999999996 1 0.28135204999999996 1 0.3143888201789505 1 0.3143888201789505} PREDS {{258 0 0-7491 {}} {259 0 0-7514 {}}} SUCCS {{259 0 0-7516 {}} {258 0 0-7518 {}} {258 0 0-7520 {}} {258 0 0-7524 {}} {258 0 0-8109 {}} {258 0 0-8556 {}} {258 0 0-8569 {}} {258 0 0-8580 {}}} CYCLES {}}
+set a(0-7516) {NAME ACC1-3:slc(ACC1:acc#210.psp) TYPE READSLICE PAR 0-7009 XREFS 47225 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7515 {}}} SUCCS {{259 0 0-7517 {}}} CYCLES {}}
+set a(0-7517) {NAME ACC1:conc#1246 TYPE CONCATENATE PAR 0-7009 XREFS 47226 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7516 {}}} SUCCS {{258 0 0-7522 {}}} CYCLES {}}
+set a(0-7518) {NAME ACC1-3:slc(ACC1:acc#210.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47227 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7515 {}}} SUCCS {{259 0 0-7519 {}}} CYCLES {}}
+set a(0-7519) {NAME ACC1-3:not#273 TYPE NOT PAR 0-7009 XREFS 47228 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7518 {}}} SUCCS {{258 0 0-7521 {}}} CYCLES {}}
+set a(0-7520) {NAME ACC1-3:slc(ACC1:acc#210.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 47229 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7515 {}}} SUCCS {{259 0 0-7521 {}}} CYCLES {}}
+set a(0-7521) {NAME ACC1:conc#1247 TYPE CONCATENATE PAR 0-7009 XREFS 47230 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7519 {}} {259 0 0-7520 {}}} SUCCS {{259 0 0-7522 {}}} CYCLES {}}
+set a(0-7522) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#394 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47231 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.3551718850894753 1 0.3551718850894753} PREDS {{258 0 0-7517 {}} {259 0 0-7521 {}}} SUCCS {{259 0 0-7523 {}}} CYCLES {}}
+set a(0-7523) {NAME ACC1:slc#66 TYPE READSLICE PAR 0-7009 XREFS 47232 LOC {1 0.30871404999999996 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-7522 {}}} SUCCS {{258 0 0-7526 {}}} CYCLES {}}
+set a(0-7524) {NAME ACC1-3:slc(ACC1:acc#210.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 47233 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.355171925} PREDS {{258 0 0-7515 {}}} SUCCS {{259 0 0-7525 {}}} CYCLES {}}
+set a(0-7525) {NAME ACC1-3:not#305 TYPE NOT PAR 0-7009 XREFS 47234 LOC {1 0.267931 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-7524 {}}} SUCCS {{259 0 0-7526 {}}} CYCLES {}}
+set a(0-7526) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-3:acc#220 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47235 LOC {1 0.30871404999999996 1 0.355171925 1 0.355171925 1 0.37564468508947524 1 0.37564468508947524} PREDS {{258 0 0-7523 {}} {259 0 0-7525 {}}} SUCCS {{259 0 0-7527 {}} {258 0 0-7530 {}} {258 0 0-8160 {}}} CYCLES {}}
+set a(0-7527) {NAME ACC1-3:slc(ACC1:acc#220.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47236 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7526 {}}} SUCCS {{259 0 0-7528 {}}} CYCLES {}}
+set a(0-7528) {NAME ACC1-3:not#293 TYPE NOT PAR 0-7009 XREFS 47237 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7527 {}}} SUCCS {{259 0 0-7529 {}}} CYCLES {}}
+set a(0-7529) {NAME ACC1:conc#1248 TYPE CONCATENATE PAR 0-7009 XREFS 47238 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7528 {}}} SUCCS {{258 0 0-7532 {}}} CYCLES {}}
+set a(0-7530) {NAME ACC1-3:slc(ACC1:acc#220.psp) TYPE READSLICE PAR 0-7009 XREFS 47239 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{258 0 0-7526 {}}} SUCCS {{259 0 0-7531 {}}} CYCLES {}}
+set a(0-7531) {NAME ACC1:conc#1249 TYPE CONCATENATE PAR 0-7009 XREFS 47240 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7530 {}}} SUCCS {{259 0 0-7532 {}}} CYCLES {}}
+set a(0-7532) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#395 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47241 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.40289060207082716 1 0.40289060207082716} PREDS {{258 0 0-7529 {}} {259 0 0-7531 {}}} SUCCS {{259 0 0-7533 {}}} CYCLES {}}
+set a(0-7533) {NAME ACC1:slc#67 TYPE READSLICE PAR 0-7009 XREFS 47242 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7532 {}}} SUCCS {{259 0 0-7534 {}} {258 0 0-7536 {}} {258 0 0-7538 {}} {258 0 0-8545 {}} {258 0 0-9178 {}}} CYCLES {}}
+set a(0-7534) {NAME ACC1-3:slc(acc.imod#2) TYPE READSLICE PAR 0-7009 XREFS 47243 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7533 {}}} SUCCS {{259 0 0-7535 {}}} CYCLES {}}
+set a(0-7535) {NAME ACC1:conc#1251 TYPE CONCATENATE PAR 0-7009 XREFS 47244 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7534 {}}} SUCCS {{258 0 0-7541 {}}} CYCLES {}}
+set a(0-7536) {NAME ACC1-3:slc(acc.imod#2)#1 TYPE READSLICE PAR 0-7009 XREFS 47245 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7533 {}}} SUCCS {{259 0 0-7537 {}}} CYCLES {}}
+set a(0-7537) {NAME ACC1-3:not#25 TYPE NOT PAR 0-7009 XREFS 47246 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7536 {}}} SUCCS {{258 0 0-7540 {}}} CYCLES {}}
+set a(0-7538) {NAME ACC1-3:slc(acc.imod#2)#2 TYPE READSLICE PAR 0-7009 XREFS 47247 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7533 {}}} SUCCS {{259 0 0-7539 {}}} CYCLES {}}
+set a(0-7539) {NAME ACC1-3:not#26 TYPE NOT PAR 0-7009 XREFS 47248 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7538 {}}} SUCCS {{259 0 0-7540 {}}} CYCLES {}}
+set a(0-7540) {NAME ACC1:conc#1252 TYPE CONCATENATE PAR 0-7009 XREFS 47249 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7537 {}} {259 0 0-7539 {}}} SUCCS {{259 0 0-7541 {}}} CYCLES {}}
+set a(0-7541) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#396 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47250 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.43013652707082717 1 0.43013652707082717} PREDS {{258 0 0-7535 {}} {259 0 0-7540 {}}} SUCCS {{259 0 0-7542 {}}} CYCLES {}}
+set a(0-7542) {NAME ACC1:slc#68 TYPE READSLICE PAR 0-7009 XREFS 47251 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-7541 {}}} SUCCS {{258 0 0-8516 {}} {258 0 0-8518 {}} {258 0 0-8530 {}}} CYCLES {}}
+set a(0-7543) {NAME regs.regs:asn#9 TYPE ASSIGN PAR 0-7009 XREFS 47252 LOC {0 1.0 0 1.0 0 1.0 1 0.0737038} PREDS {{262 0 0-9349 {}}} SUCCS {{259 0 0-7544 {}} {256 0 0-9349 {}}} CYCLES {}}
+set a(0-7544) {NAME regs.regs:slc(regs.regs(2)) TYPE READSLICE PAR 0-7009 XREFS 47253 LOC {0 1.0 0 1.0 0 1.0 1 0.0737038} PREDS {{259 0 0-7543 {}}} SUCCS {{259 0 0-7545 {}}} CYCLES {}}
+set a(0-7545) {NAME {regs.operator[]:not#5} TYPE NOT PAR 0-7009 XREFS 47254 LOC {0 1.0 1 0.0737038 1 0.0737038 1 0.0737038} PREDS {{259 0 0-7544 {}}} SUCCS {{258 0 0-7549 {}}} CYCLES {}}
+set a(0-7546) {NAME regs.regs:asn#10 TYPE ASSIGN PAR 0-7009 XREFS 47255 LOC {0 1.0 0 1.0 0 1.0 1 0.0737038} PREDS {{262 0 0-9349 {}}} SUCCS {{259 0 0-7547 {}} {256 0 0-9349 {}}} CYCLES {}}
+set a(0-7547) {NAME regs.regs:slc(regs.regs(2))#1 TYPE READSLICE PAR 0-7009 XREFS 47256 LOC {0 1.0 0 1.0 0 1.0 1 0.0737038} PREDS {{259 0 0-7546 {}}} SUCCS {{259 0 0-7548 {}}} CYCLES {}}
+set a(0-7548) {NAME {regs.operator[]#1:not#5} TYPE NOT PAR 0-7009 XREFS 47257 LOC {0 1.0 1 0.0737038 1 0.0737038 1 0.0737038} PREDS {{259 0 0-7547 {}}} SUCCS {{259 0 0-7549 {}}} CYCLES {}}
+set a(0-7549) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#398 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 47258 LOC {1 0.0 1 0.0737038 1 0.0737038 1 0.14488790333641133 1 0.14488790333641133} PREDS {{258 0 0-7545 {}} {259 0 0-7548 {}}} SUCCS {{258 0 0-7554 {}}} CYCLES {}}
+set a(0-7550) {NAME regs.regs:asn#11 TYPE ASSIGN PAR 0-7009 XREFS 47259 LOC {0 1.0 0 1.0 0 1.0 1 0.0737038} PREDS {{262 0 0-9349 {}}} SUCCS {{259 0 0-7551 {}} {256 0 0-9349 {}}} CYCLES {}}
+set a(0-7551) {NAME regs.regs:slc(regs.regs(2))#2 TYPE READSLICE PAR 0-7009 XREFS 47260 LOC {0 1.0 0 1.0 0 1.0 1 0.0737038} PREDS {{259 0 0-7550 {}}} SUCCS {{259 0 0-7552 {}}} CYCLES {}}
+set a(0-7552) {NAME {regs.operator[]#2:not#5} TYPE NOT PAR 0-7009 XREFS 47261 LOC {0 1.0 1 0.0737038 1 0.0737038 1 0.0737038} PREDS {{259 0 0-7551 {}}} SUCCS {{259 0 0-7553 {}}} CYCLES {}}
+set a(0-7553) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#397 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 47262 LOC {1 0.0 1 0.0737038 1 0.0737038 1 0.14488790333641133 1 0.14488790333641133} PREDS {{259 0 0-7552 {}}} SUCCS {{259 0 0-7554 {}}} CYCLES {}}
+set a(0-7554) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1:acc#227 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 47263 LOC {1 0.07118415 1 0.14488795 1 0.14488795 1 0.22025870637342837 1 0.22025870637342837} PREDS {{258 0 0-7549 {}} {259 0 0-7553 {}}} SUCCS {{259 0 0-7555 {}} {258 0 0-7558 {}} {258 0 0-7560 {}} {258 0 0-7565 {}} {258 0 0-7567 {}} {258 0 0-7571 {}} {258 0 0-7573 {}} {258 0 0-7575 {}} {258 0 0-7581 {}} {258 0 0-7583 {}} {258 0 0-7585 {}} {258 0 0-7589 {}} {258 0 0-7776 {}} {258 0 0-7792 {}} {258 0 0-8141 {}} {258 0 0-8174 {}} {258 0 0-8191 {}} {258 0 0-8227 {}} {258 0 0-8316 {}} {258 0 0-8319 {}} {258 0 0-8332 {}} {258 0 0-8335 {}} {258 0 0-8377 {}} {258 0 0-8383 {}} {258 0 0-8386 {}} {258 0 0-8397 {}} {258 0 0-8400 {}} {258 0 0-8508 {}} {258 0 0-8509 {}} {258 0 0-8513 {}} {258 0 0-8524 {}} {258 0 0-8528 {}} {258 0 0-8634 {}} {258 0 0-8642 {}} {258 0 0-8664 {}} {258 0 0-8665 {}} {258 0 0-8735 {}} {258 0 0-8737 {}} {258 0 0-8740 {}} {258 0 0-8742 {}} {258 0 0-8746 {}} {258 0 0-8748 {}} {258 0 0-8999 {}} {258 0 0-9013 {}} {258 0 0-9116 {}} {258 0 0-9155 {}} {258 0 0-9157 {}} {258 0 0-9247 {}}} CYCLES {}}
+set a(0-7555) {NAME ACC1-3:slc(acc#5.psp)#11 TYPE READSLICE PAR 0-7009 XREFS 47264 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.24493322499999998} PREDS {{259 0 0-7554 {}}} SUCCS {{259 0 0-7556 {}}} CYCLES {}}
+set a(0-7556) {NAME ACC1:not#314 TYPE NOT PAR 0-7009 XREFS 47265 LOC {1 0.14655495 1 0.24493322499999998 1 0.24493322499999998 1 0.24493322499999998} PREDS {{259 0 0-7555 {}}} SUCCS {{259 0 0-7557 {}}} CYCLES {}}
+set a(0-7557) {NAME ACC1:conc#1258 TYPE CONCATENATE PAR 0-7009 XREFS 47266 LOC {1 0.14655495 1 0.24493322499999998 1 0.24493322499999998 1 0.24493322499999998} PREDS {{259 0 0-7556 {}}} SUCCS {{258 0 0-7562 {}}} CYCLES {}}
+set a(0-7558) {NAME ACC1-3:slc(acc#5.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47267 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.24493322499999998} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-7559 {}}} CYCLES {}}
+set a(0-7559) {NAME ACC1-3:not#238 TYPE NOT PAR 0-7009 XREFS 47268 LOC {1 0.14655495 1 0.24493322499999998 1 0.24493322499999998 1 0.24493322499999998} PREDS {{259 0 0-7558 {}}} SUCCS {{258 0 0-7561 {}}} CYCLES {}}
+set a(0-7560) {NAME ACC1-3:slc(acc#5.psp)#8 TYPE READSLICE PAR 0-7009 XREFS 47269 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.24493322499999998} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-7561 {}}} CYCLES {}}
+set a(0-7561) {NAME ACC1:conc#1259 TYPE CONCATENATE PAR 0-7009 XREFS 47270 LOC {1 0.14655495 1 0.24493322499999998 1 0.24493322499999998 1 0.24493322499999998} PREDS {{258 0 0-7559 {}} {259 0 0-7560 {}}} SUCCS {{259 0 0-7562 {}}} CYCLES {}}
+set a(0-7562) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#401 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47271 LOC {1 0.14655495 1 0.24493322499999998 1 0.24493322499999998 1 0.2654059850894752 1 0.2654059850894752} PREDS {{258 0 0-7557 {}} {259 0 0-7561 {}}} SUCCS {{259 0 0-7563 {}}} CYCLES {}}
+set a(0-7563) {NAME ACC1:slc#71 TYPE READSLICE PAR 0-7009 XREFS 47272 LOC {1 0.16702775 1 0.265406025 1 0.265406025 1 0.265406025} PREDS {{259 0 0-7562 {}}} SUCCS {{259 0 0-7564 {}}} CYCLES {}}
+set a(0-7564) {NAME ACC1:conc#1262 TYPE CONCATENATE PAR 0-7009 XREFS 47273 LOC {1 0.16702775 1 0.265406025 1 0.265406025 1 0.265406025} PREDS {{259 0 0-7563 {}}} SUCCS {{258 0 0-7569 {}}} CYCLES {}}
+set a(0-7565) {NAME ACC1-3:slc(acc#5.psp) TYPE READSLICE PAR 0-7009 XREFS 47274 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.265406025} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-7566 {}}} CYCLES {}}
+set a(0-7566) {NAME ACC1:conc#1253 TYPE CONCATENATE PAR 0-7009 XREFS 47275 LOC {1 0.14655495 1 0.265406025 1 0.265406025 1 0.265406025} PREDS {{259 0 0-7565 {}}} SUCCS {{258 0 0-7568 {}}} CYCLES {}}
+set a(0-7567) {NAME ACC1-3:slc(acc#5.psp)#10 TYPE READSLICE PAR 0-7009 XREFS 47276 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.265406025} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-7568 {}}} CYCLES {}}
+set a(0-7568) {NAME ACC1:conc#1263 TYPE CONCATENATE PAR 0-7009 XREFS 47277 LOC {1 0.14655495 1 0.265406025 1 0.265406025 1 0.265406025} PREDS {{258 0 0-7566 {}} {259 0 0-7567 {}}} SUCCS {{259 0 0-7569 {}}} CYCLES {}}
+set a(0-7569) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#403 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 47278 LOC {1 0.16702775 1 0.265406025 1 0.265406025 1 0.3085979201789505 1 0.3085979201789505} PREDS {{258 0 0-7564 {}} {259 0 0-7568 {}}} SUCCS {{259 0 0-7570 {}}} CYCLES {}}
+set a(0-7570) {NAME ACC1:slc#73 TYPE READSLICE PAR 0-7009 XREFS 47279 LOC {1 0.21021969999999998 1 0.30859797499999997 1 0.30859797499999997 1 0.30859797499999997} PREDS {{259 0 0-7569 {}}} SUCCS {{258 0 0-7594 {}}} CYCLES {}}
+set a(0-7571) {NAME ACC1-3:slc(acc#5.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 47280 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-7572 {}}} CYCLES {}}
+set a(0-7572) {NAME ACC1:conc#1256 TYPE CONCATENATE PAR 0-7009 XREFS 47281 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{259 0 0-7571 {}}} SUCCS {{258 0 0-7578 {}}} CYCLES {}}
+set a(0-7573) {NAME ACC1-3:slc(acc#5.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 47282 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-7574 {}}} CYCLES {}}
+set a(0-7574) {NAME ACC1-3:not#239 TYPE NOT PAR 0-7009 XREFS 47283 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{259 0 0-7573 {}}} SUCCS {{258 0 0-7577 {}}} CYCLES {}}
+set a(0-7575) {NAME ACC1-3:slc(acc#5.psp)#7 TYPE READSLICE PAR 0-7009 XREFS 47284 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-7576 {}}} CYCLES {}}
+set a(0-7576) {NAME ACC1-3:not#241 TYPE NOT PAR 0-7009 XREFS 47285 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{259 0 0-7575 {}}} SUCCS {{259 0 0-7577 {}}} CYCLES {}}
+set a(0-7577) {NAME ACC1:conc#1257 TYPE CONCATENATE PAR 0-7009 XREFS 47286 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-7574 {}} {259 0 0-7576 {}}} SUCCS {{259 0 0-7578 {}}} CYCLES {}}
+set a(0-7578) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#400 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47287 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.2610417600894752 1 0.2610417600894752} PREDS {{258 0 0-7572 {}} {259 0 0-7577 {}}} SUCCS {{259 0 0-7579 {}}} CYCLES {}}
+set a(0-7579) {NAME ACC1:slc#70 TYPE READSLICE PAR 0-7009 XREFS 47288 LOC {1 0.187338 1 0.2610418 1 0.2610418 1 0.2610418} PREDS {{259 0 0-7578 {}}} SUCCS {{259 0 0-7580 {}}} CYCLES {}}
+set a(0-7580) {NAME ACC1:conc#1260 TYPE CONCATENATE PAR 0-7009 XREFS 47289 LOC {1 0.187338 1 0.2610418 1 0.2610418 1 0.2610418} PREDS {{259 0 0-7579 {}}} SUCCS {{258 0 0-7592 {}}} CYCLES {}}
+set a(0-7581) {NAME ACC1-3:slc(acc#5.psp)#4 TYPE READSLICE PAR 0-7009 XREFS 47290 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-7582 {}}} CYCLES {}}
+set a(0-7582) {NAME ACC1:conc#1254 TYPE CONCATENATE PAR 0-7009 XREFS 47291 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{259 0 0-7581 {}}} SUCCS {{258 0 0-7587 {}}} CYCLES {}}
+set a(0-7583) {NAME ACC1-3:slc(acc#5.psp)#5 TYPE READSLICE PAR 0-7009 XREFS 47292 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-7584 {}}} CYCLES {}}
+set a(0-7584) {NAME ACC1-3:not#240 TYPE NOT PAR 0-7009 XREFS 47293 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{259 0 0-7583 {}}} SUCCS {{258 0 0-7586 {}}} CYCLES {}}
+set a(0-7585) {NAME ACC1-3:slc(acc#5.psp)#6 TYPE READSLICE PAR 0-7009 XREFS 47294 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-7586 {}}} CYCLES {}}
+set a(0-7586) {NAME ACC1:conc#1255 TYPE CONCATENATE PAR 0-7009 XREFS 47295 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-7584 {}} {259 0 0-7585 {}}} SUCCS {{259 0 0-7587 {}}} CYCLES {}}
+set a(0-7587) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#399 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47296 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.2610417600894752 1 0.2610417600894752} PREDS {{258 0 0-7582 {}} {259 0 0-7586 {}}} SUCCS {{259 0 0-7588 {}}} CYCLES {}}
+set a(0-7588) {NAME ACC1:slc#69 TYPE READSLICE PAR 0-7009 XREFS 47297 LOC {1 0.187338 1 0.2610418 1 0.2610418 1 0.2610418} PREDS {{259 0 0-7587 {}}} SUCCS {{258 0 0-7591 {}}} CYCLES {}}
+set a(0-7589) {NAME ACC1-3:slc(acc#5.psp)#9 TYPE READSLICE PAR 0-7009 XREFS 47298 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.2610418} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-7590 {}}} CYCLES {}}
+set a(0-7590) {NAME ACC1-3:not#242 TYPE NOT PAR 0-7009 XREFS 47299 LOC {1 0.14655495 1 0.2610418 1 0.2610418 1 0.2610418} PREDS {{259 0 0-7589 {}}} SUCCS {{259 0 0-7591 {}}} CYCLES {}}
+set a(0-7591) {NAME ACC1:conc#1261 TYPE CONCATENATE PAR 0-7009 XREFS 47300 LOC {1 0.187338 1 0.2610418 1 0.2610418 1 0.2610418} PREDS {{258 0 0-7588 {}} {259 0 0-7590 {}}} SUCCS {{259 0 0-7592 {}}} CYCLES {}}
+set a(0-7592) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#402 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47301 LOC {1 0.187338 1 0.2610418 1 0.2610418 1 0.30859792707082717 1 0.30859792707082717} PREDS {{258 0 0-7580 {}} {259 0 0-7591 {}}} SUCCS {{259 0 0-7593 {}}} CYCLES {}}
+set a(0-7593) {NAME ACC1:slc#72 TYPE READSLICE PAR 0-7009 XREFS 47302 LOC {1 0.23489417499999998 1 0.30859797499999997 1 0.30859797499999997 1 0.30859797499999997} PREDS {{259 0 0-7592 {}}} SUCCS {{259 0 0-7594 {}}} CYCLES {}}
+set a(0-7594) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1-3:acc#212 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 47303 LOC {1 0.23489417499999998 1 0.30859797499999997 1 0.30859797499999997 1 0.3416347451789505 1 0.3416347451789505} PREDS {{258 0 0-7570 {}} {259 0 0-7593 {}}} SUCCS {{259 0 0-7595 {}} {258 0 0-7597 {}} {258 0 0-7599 {}} {258 0 0-7603 {}} {258 0 0-8293 {}} {258 0 0-8302 {}} {258 0 0-8312 {}} {258 0 0-9187 {}}} CYCLES {}}
+set a(0-7595) {NAME ACC1-3:slc(ACC1:acc#212.psp) TYPE READSLICE PAR 0-7009 XREFS 47304 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.34163479999999996} PREDS {{259 0 0-7594 {}}} SUCCS {{259 0 0-7596 {}}} CYCLES {}}
+set a(0-7596) {NAME ACC1:conc#1264 TYPE CONCATENATE PAR 0-7009 XREFS 47305 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.34163479999999996} PREDS {{259 0 0-7595 {}}} SUCCS {{258 0 0-7601 {}}} CYCLES {}}
+set a(0-7597) {NAME ACC1-3:slc(ACC1:acc#212.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47306 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.34163479999999996} PREDS {{258 0 0-7594 {}}} SUCCS {{259 0 0-7598 {}}} CYCLES {}}
+set a(0-7598) {NAME ACC1-3:not#277 TYPE NOT PAR 0-7009 XREFS 47307 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.34163479999999996} PREDS {{259 0 0-7597 {}}} SUCCS {{258 0 0-7600 {}}} CYCLES {}}
+set a(0-7599) {NAME ACC1-3:slc(ACC1:acc#212.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 47308 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.34163479999999996} PREDS {{258 0 0-7594 {}}} SUCCS {{259 0 0-7600 {}}} CYCLES {}}
+set a(0-7600) {NAME ACC1:conc#1265 TYPE CONCATENATE PAR 0-7009 XREFS 47309 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.34163479999999996} PREDS {{258 0 0-7598 {}} {259 0 0-7599 {}}} SUCCS {{259 0 0-7601 {}}} CYCLES {}}
+set a(0-7601) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#404 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47310 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.3824178100894752 1 0.3824178100894752} PREDS {{258 0 0-7596 {}} {259 0 0-7600 {}}} SUCCS {{259 0 0-7602 {}}} CYCLES {}}
+set a(0-7602) {NAME ACC1:slc#74 TYPE READSLICE PAR 0-7009 XREFS 47311 LOC {1 0.30871404999999996 1 0.38241785 1 0.38241785 1 0.38241785} PREDS {{259 0 0-7601 {}}} SUCCS {{258 0 0-7605 {}}} CYCLES {}}
+set a(0-7603) {NAME ACC1-3:slc(ACC1:acc#212.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 47312 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.38241785} PREDS {{258 0 0-7594 {}}} SUCCS {{259 0 0-7604 {}}} CYCLES {}}
+set a(0-7604) {NAME ACC1:not#320 TYPE NOT PAR 0-7009 XREFS 47313 LOC {1 0.267931 1 0.38241785 1 0.38241785 1 0.38241785} PREDS {{259 0 0-7603 {}}} SUCCS {{259 0 0-7605 {}}} CYCLES {}}
+set a(0-7605) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-3:acc#221 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47314 LOC {1 0.30871404999999996 1 0.38241785 1 0.38241785 1 0.40289061008947524 1 0.40289061008947524} PREDS {{258 0 0-7602 {}} {259 0 0-7604 {}}} SUCCS {{259 0 0-7606 {}} {258 0 0-7609 {}} {258 0 0-9210 {}}} CYCLES {}}
+set a(0-7606) {NAME ACC1-3:slc(ACC1:acc#221.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47315 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7605 {}}} SUCCS {{259 0 0-7607 {}}} CYCLES {}}
+set a(0-7607) {NAME ACC1-3:not#295 TYPE NOT PAR 0-7009 XREFS 47316 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7606 {}}} SUCCS {{259 0 0-7608 {}}} CYCLES {}}
+set a(0-7608) {NAME ACC1:conc#1266 TYPE CONCATENATE PAR 0-7009 XREFS 47317 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7607 {}}} SUCCS {{258 0 0-7611 {}}} CYCLES {}}
+set a(0-7609) {NAME ACC1-3:slc(ACC1:acc#221.psp) TYPE READSLICE PAR 0-7009 XREFS 47318 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7605 {}}} SUCCS {{259 0 0-7610 {}}} CYCLES {}}
+set a(0-7610) {NAME ACC1:conc#1267 TYPE CONCATENATE PAR 0-7009 XREFS 47319 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7609 {}}} SUCCS {{259 0 0-7611 {}}} CYCLES {}}
+set a(0-7611) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#405 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47320 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.43013652707082717 1 0.43013652707082717} PREDS {{258 0 0-7608 {}} {259 0 0-7610 {}}} SUCCS {{259 0 0-7612 {}}} CYCLES {}}
+set a(0-7612) {NAME ACC1:slc#75 TYPE READSLICE PAR 0-7009 XREFS 47321 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-7611 {}}} SUCCS {{259 0 0-7613 {}} {258 0 0-7615 {}} {258 0 0-7617 {}} {258 0 0-8282 {}} {258 0 0-9201 {}}} CYCLES {}}
+set a(0-7613) {NAME ACC1-3:slc(acc.imod#6) TYPE READSLICE PAR 0-7009 XREFS 47322 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.5816089999999999} PREDS {{259 0 0-7612 {}}} SUCCS {{259 0 0-7614 {}}} CYCLES {}}
+set a(0-7614) {NAME ACC1:conc#1269 TYPE CONCATENATE PAR 0-7009 XREFS 47323 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-7613 {}}} SUCCS {{258 0 0-7620 {}}} CYCLES {}}
+set a(0-7615) {NAME ACC1-3:slc(acc.imod#6)#1 TYPE READSLICE PAR 0-7009 XREFS 47324 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.5816089999999999} PREDS {{258 0 0-7612 {}}} SUCCS {{259 0 0-7616 {}}} CYCLES {}}
+set a(0-7616) {NAME ACC1-3:not#57 TYPE NOT PAR 0-7009 XREFS 47325 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-7615 {}}} SUCCS {{258 0 0-7619 {}}} CYCLES {}}
+set a(0-7617) {NAME ACC1-3:slc(acc.imod#6)#2 TYPE READSLICE PAR 0-7009 XREFS 47326 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.5816089999999999} PREDS {{258 0 0-7612 {}}} SUCCS {{259 0 0-7618 {}}} CYCLES {}}
+set a(0-7618) {NAME ACC1-3:not#58 TYPE NOT PAR 0-7009 XREFS 47327 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-7617 {}}} SUCCS {{259 0 0-7619 {}}} CYCLES {}}
+set a(0-7619) {NAME ACC1:conc#1270 TYPE CONCATENATE PAR 0-7009 XREFS 47328 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-7616 {}} {259 0 0-7618 {}}} SUCCS {{259 0 0-7620 {}}} CYCLES {}}
+set a(0-7620) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#406 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47329 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.47245505207082716 1 0.6088548770708271} PREDS {{258 0 0-7614 {}} {259 0 0-7619 {}}} SUCCS {{259 0 0-7621 {}}} CYCLES {}}
+set a(0-7621) {NAME ACC1:slc#76 TYPE READSLICE PAR 0-7009 XREFS 47330 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-7620 {}}} SUCCS {{258 0 0-9000 {}} {258 0 0-9002 {}} {258 0 0-9012 {}}} CYCLES {}}
+set a(0-7622) {NAME regs.regs:asn#12 TYPE ASSIGN PAR 0-7009 XREFS 47331 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-9349 {}}} SUCCS {{259 0 0-7623 {}} {256 0 0-9349 {}}} CYCLES {}}
+set a(0-7623) {NAME regs.regs:slc(regs.regs(2))#4 TYPE READSLICE PAR 0-7009 XREFS 47332 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-7622 {}}} SUCCS {{258 0 0-7626 {}}} CYCLES {}}
+set a(0-7624) {NAME regs.regs:asn#13 TYPE ASSIGN PAR 0-7009 XREFS 47333 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-9349 {}}} SUCCS {{259 0 0-7625 {}} {256 0 0-9349 {}}} CYCLES {}}
+set a(0-7625) {NAME regs.regs:slc(regs.regs(2))#5 TYPE READSLICE PAR 0-7009 XREFS 47334 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-7624 {}}} SUCCS {{259 0 0-7626 {}}} CYCLES {}}
+set a(0-7626) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#407 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 47335 LOC {1 0.0 1 0.05572455 1 0.05572455 1 0.12690865333641133 1 0.12690865333641133} PREDS {{258 0 0-7623 {}} {259 0 0-7625 {}}} SUCCS {{258 0 0-7629 {}}} CYCLES {}}
+set a(0-7627) {NAME regs.regs:asn#14 TYPE ASSIGN PAR 0-7009 XREFS 47336 LOC {0 1.0 0 1.0 0 1.0 1 0.12690869999999999} PREDS {{262 0 0-9349 {}}} SUCCS {{259 0 0-7628 {}} {256 0 0-9349 {}}} CYCLES {}}
+set a(0-7628) {NAME regs.regs:slc(regs.regs(2))#3 TYPE READSLICE PAR 0-7009 XREFS 47337 LOC {0 1.0 0 1.0 0 1.0 1 0.12690869999999999} PREDS {{259 0 0-7627 {}}} SUCCS {{259 0 0-7629 {}}} CYCLES {}}
+set a(0-7629) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-3:acc#224 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 47338 LOC {1 0.07118415 1 0.12690869999999999 1 0.12690869999999999 1 0.20227945637342837 1 0.20227945637342837} PREDS {{258 0 0-7626 {}} {259 0 0-7628 {}}} SUCCS {{259 0 0-7630 {}} {258 0 0-7633 {}} {258 0 0-7635 {}} {258 0 0-7637 {}} {258 0 0-7642 {}} {258 0 0-7648 {}} {258 0 0-7650 {}} {258 0 0-7652 {}} {258 0 0-7657 {}} {258 0 0-7659 {}} {258 0 0-7663 {}} {258 0 0-7774 {}} {258 0 0-7779 {}} {258 0 0-7793 {}} {258 0 0-8086 {}} {258 0 0-8150 {}} {258 0 0-8151 {}} {258 0 0-8170 {}} {258 0 0-8177 {}} {258 0 0-8194 {}} {258 0 0-8214 {}} {258 0 0-8223 {}} {258 0 0-8235 {}} {258 0 0-8246 {}} {258 0 0-8344 {}} {258 0 0-8347 {}} {258 0 0-8354 {}} {258 0 0-8357 {}} {258 0 0-8446 {}} {258 0 0-8460 {}} {258 0 0-8523 {}} {258 0 0-8554 {}} {258 0 0-8563 {}} {258 0 0-8567 {}} {258 0 0-8623 {}} {258 0 0-8627 {}} {258 0 0-8630 {}} {258 0 0-8635 {}} {258 0 0-8643 {}} {258 0 0-8648 {}} {258 0 0-8654 {}} {258 0 0-8658 {}} {258 0 0-8659 {}} {258 0 0-8677 {}} {258 0 0-8678 {}} {258 0 0-9117 {}} {258 0 0-9118 {}} {258 0 0-9250 {}}} CYCLES {}}
+set a(0-7630) {NAME ACC1-3:slc(acc#10.psp)#39 TYPE READSLICE PAR 0-7009 XREFS 47339 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306255} PREDS {{259 0 0-7629 {}}} SUCCS {{259 0 0-7631 {}}} CYCLES {}}
+set a(0-7631) {NAME ACC1-3:not#247 TYPE NOT PAR 0-7009 XREFS 47340 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-7630 {}}} SUCCS {{259 0 0-7632 {}}} CYCLES {}}
+set a(0-7632) {NAME ACC1:conc#1278 TYPE CONCATENATE PAR 0-7009 XREFS 47341 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-7631 {}}} SUCCS {{258 0 0-7645 {}}} CYCLES {}}
+set a(0-7633) {NAME ACC1-3:slc(acc#10.psp)#40 TYPE READSLICE PAR 0-7009 XREFS 47342 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-7634 {}}} CYCLES {}}
+set a(0-7634) {NAME ACC1:conc#1274 TYPE CONCATENATE PAR 0-7009 XREFS 47343 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-7633 {}}} SUCCS {{258 0 0-7640 {}}} CYCLES {}}
+set a(0-7635) {NAME ACC1-3:slc(acc#10.psp)#41 TYPE READSLICE PAR 0-7009 XREFS 47344 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-7636 {}}} CYCLES {}}
+set a(0-7636) {NAME ACC1-3:not#248 TYPE NOT PAR 0-7009 XREFS 47345 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-7635 {}}} SUCCS {{258 0 0-7639 {}}} CYCLES {}}
+set a(0-7637) {NAME ACC1-3:slc(acc#10.psp)#45 TYPE READSLICE PAR 0-7009 XREFS 47346 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-7638 {}}} CYCLES {}}
+set a(0-7638) {NAME ACC1-3:not#250 TYPE NOT PAR 0-7009 XREFS 47347 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-7637 {}}} SUCCS {{259 0 0-7639 {}}} CYCLES {}}
+set a(0-7639) {NAME ACC1:conc#1275 TYPE CONCATENATE PAR 0-7009 XREFS 47348 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-7636 {}} {259 0 0-7638 {}}} SUCCS {{259 0 0-7640 {}}} CYCLES {}}
+set a(0-7640) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#409 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47349 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306251008947524 1 0.24306251008947524} PREDS {{258 0 0-7634 {}} {259 0 0-7639 {}}} SUCCS {{259 0 0-7641 {}}} CYCLES {}}
+set a(0-7641) {NAME ACC1:slc#78 TYPE READSLICE PAR 0-7009 XREFS 47350 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-7640 {}}} SUCCS {{258 0 0-7644 {}}} CYCLES {}}
+set a(0-7642) {NAME ACC1-3:slc(acc#10.psp)#47 TYPE READSLICE PAR 0-7009 XREFS 47351 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306255} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-7643 {}}} CYCLES {}}
+set a(0-7643) {NAME ACC1-3:not#251 TYPE NOT PAR 0-7009 XREFS 47352 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-7642 {}}} SUCCS {{259 0 0-7644 {}}} CYCLES {}}
+set a(0-7644) {NAME ACC1:conc#1279 TYPE CONCATENATE PAR 0-7009 XREFS 47353 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{258 0 0-7641 {}} {259 0 0-7643 {}}} SUCCS {{259 0 0-7645 {}}} CYCLES {}}
+set a(0-7645) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#411 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 47354 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.2760993201789505 1 0.2760993201789505} PREDS {{258 0 0-7632 {}} {259 0 0-7644 {}}} SUCCS {{259 0 0-7646 {}}} CYCLES {}}
+set a(0-7646) {NAME ACC1:slc#80 TYPE READSLICE PAR 0-7009 XREFS 47355 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-7645 {}}} SUCCS {{259 0 0-7647 {}}} CYCLES {}}
+set a(0-7647) {NAME ACC1:conc#1280 TYPE CONCATENATE PAR 0-7009 XREFS 47356 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-7646 {}}} SUCCS {{258 0 0-7665 {}}} CYCLES {}}
+set a(0-7648) {NAME ACC1-3:slc(acc#10.psp)#42 TYPE READSLICE PAR 0-7009 XREFS 47357 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-7649 {}}} CYCLES {}}
+set a(0-7649) {NAME ACC1:conc#1272 TYPE CONCATENATE PAR 0-7009 XREFS 47358 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{259 0 0-7648 {}}} SUCCS {{258 0 0-7654 {}}} CYCLES {}}
+set a(0-7650) {NAME ACC1-3:slc(acc#10.psp)#43 TYPE READSLICE PAR 0-7009 XREFS 47359 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-7651 {}}} CYCLES {}}
+set a(0-7651) {NAME ACC1-3:not#249 TYPE NOT PAR 0-7009 XREFS 47360 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{259 0 0-7650 {}}} SUCCS {{258 0 0-7653 {}}} CYCLES {}}
+set a(0-7652) {NAME ACC1-3:slc(acc#10.psp)#44 TYPE READSLICE PAR 0-7009 XREFS 47361 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-7653 {}}} CYCLES {}}
+set a(0-7653) {NAME ACC1:conc#1273 TYPE CONCATENATE PAR 0-7009 XREFS 47362 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{258 0 0-7651 {}} {259 0 0-7652 {}}} SUCCS {{259 0 0-7654 {}}} CYCLES {}}
+set a(0-7654) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#408 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47363 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.24885341008947523 1 0.24885341008947523} PREDS {{258 0 0-7649 {}} {259 0 0-7653 {}}} SUCCS {{259 0 0-7655 {}}} CYCLES {}}
+set a(0-7655) {NAME ACC1:slc#77 TYPE READSLICE PAR 0-7009 XREFS 47364 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-7654 {}}} SUCCS {{259 0 0-7656 {}}} CYCLES {}}
+set a(0-7656) {NAME ACC1:conc#1276 TYPE CONCATENATE PAR 0-7009 XREFS 47365 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-7655 {}}} SUCCS {{258 0 0-7661 {}}} CYCLES {}}
+set a(0-7657) {NAME ACC1-3:slc(acc#10.psp)#49 TYPE READSLICE PAR 0-7009 XREFS 47366 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24885344999999998} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-7658 {}}} CYCLES {}}
+set a(0-7658) {NAME ACC1-3:not#252 TYPE NOT PAR 0-7009 XREFS 47367 LOC {1 0.14655495 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-7657 {}}} SUCCS {{258 0 0-7660 {}}} CYCLES {}}
+set a(0-7659) {NAME ACC1-3:slc(acc#10.psp)#46 TYPE READSLICE PAR 0-7009 XREFS 47368 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24885344999999998} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-7660 {}}} CYCLES {}}
+set a(0-7660) {NAME ACC1:conc#1277 TYPE CONCATENATE PAR 0-7009 XREFS 47369 LOC {1 0.14655495 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{258 0 0-7658 {}} {259 0 0-7659 {}}} SUCCS {{259 0 0-7661 {}}} CYCLES {}}
+set a(0-7661) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#410 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47370 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.2760993270708272 1 0.2760993270708272} PREDS {{258 0 0-7656 {}} {259 0 0-7660 {}}} SUCCS {{259 0 0-7662 {}}} CYCLES {}}
+set a(0-7662) {NAME ACC1:slc#79 TYPE READSLICE PAR 0-7009 XREFS 47371 LOC {1 0.21458392499999998 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-7661 {}}} SUCCS {{258 0 0-7664 {}}} CYCLES {}}
+set a(0-7663) {NAME ACC1-3:slc(acc#10.psp)#48 TYPE READSLICE PAR 0-7009 XREFS 47372 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.276099375} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-7664 {}}} CYCLES {}}
+set a(0-7664) {NAME ACC1:conc#1281 TYPE CONCATENATE PAR 0-7009 XREFS 47373 LOC {1 0.21458392499999998 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{258 0 0-7662 {}} {259 0 0-7663 {}}} SUCCS {{259 0 0-7665 {}}} CYCLES {}}
+set a(0-7665) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#412 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-7009 XREFS 47374 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.31438883449693605 1 0.31438883449693605} PREDS {{258 0 0-7647 {}} {259 0 0-7664 {}}} SUCCS {{259 0 0-7666 {}}} CYCLES {}}
+set a(0-7666) {NAME ACC1:slc#81 TYPE READSLICE PAR 0-7009 XREFS 47375 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7665 {}}} SUCCS {{259 0 0-7667 {}} {258 0 0-7669 {}} {258 0 0-7671 {}} {258 0 0-7675 {}} {258 0 0-8482 {}} {258 0 0-8492 {}} {258 0 0-8501 {}} {258 0 0-9169 {}}} CYCLES {}}
+set a(0-7667) {NAME ACC1-3:slc(ACC1:acc#214.psp) TYPE READSLICE PAR 0-7009 XREFS 47376 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7666 {}}} SUCCS {{259 0 0-7668 {}}} CYCLES {}}
+set a(0-7668) {NAME ACC1:conc#1282 TYPE CONCATENATE PAR 0-7009 XREFS 47377 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7667 {}}} SUCCS {{258 0 0-7673 {}}} CYCLES {}}
+set a(0-7669) {NAME ACC1-3:slc(ACC1:acc#214.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47378 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7666 {}}} SUCCS {{259 0 0-7670 {}}} CYCLES {}}
+set a(0-7670) {NAME ACC1-3:not#281 TYPE NOT PAR 0-7009 XREFS 47379 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7669 {}}} SUCCS {{258 0 0-7672 {}}} CYCLES {}}
+set a(0-7671) {NAME ACC1-3:slc(ACC1:acc#214.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 47380 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7666 {}}} SUCCS {{259 0 0-7672 {}}} CYCLES {}}
+set a(0-7672) {NAME ACC1:conc#1283 TYPE CONCATENATE PAR 0-7009 XREFS 47381 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7670 {}} {259 0 0-7671 {}}} SUCCS {{259 0 0-7673 {}}} CYCLES {}}
+set a(0-7673) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#413 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47382 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.3551718850894753 1 0.3551718850894753} PREDS {{258 0 0-7668 {}} {259 0 0-7672 {}}} SUCCS {{259 0 0-7674 {}}} CYCLES {}}
+set a(0-7674) {NAME ACC1:slc#82 TYPE READSLICE PAR 0-7009 XREFS 47383 LOC {1 0.29944737499999996 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-7673 {}}} SUCCS {{258 0 0-7677 {}}} CYCLES {}}
+set a(0-7675) {NAME ACC1-3:slc(ACC1:acc#214.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 47384 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.355171925} PREDS {{258 0 0-7666 {}}} SUCCS {{259 0 0-7676 {}}} CYCLES {}}
+set a(0-7676) {NAME ACC1-3:not#303 TYPE NOT PAR 0-7009 XREFS 47385 LOC {1 0.258664325 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-7675 {}}} SUCCS {{259 0 0-7677 {}}} CYCLES {}}
+set a(0-7677) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-3:acc#225 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47386 LOC {1 0.29944737499999996 1 0.355171925 1 0.355171925 1 0.37564468508947524 1 0.37564468508947524} PREDS {{258 0 0-7674 {}} {259 0 0-7676 {}}} SUCCS {{259 0 0-7678 {}} {258 0 0-7681 {}} {258 0 0-8161 {}}} CYCLES {}}
+set a(0-7678) {NAME ACC1-3:slc(ACC1:acc#222.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47387 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7677 {}}} SUCCS {{259 0 0-7679 {}}} CYCLES {}}
+set a(0-7679) {NAME ACC1-3:not#297 TYPE NOT PAR 0-7009 XREFS 47388 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7678 {}}} SUCCS {{259 0 0-7680 {}}} CYCLES {}}
+set a(0-7680) {NAME ACC1:conc#1284 TYPE CONCATENATE PAR 0-7009 XREFS 47389 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7679 {}}} SUCCS {{258 0 0-7683 {}}} CYCLES {}}
+set a(0-7681) {NAME ACC1-3:slc(ACC1:acc#222.psp) TYPE READSLICE PAR 0-7009 XREFS 47390 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{258 0 0-7677 {}}} SUCCS {{259 0 0-7682 {}}} CYCLES {}}
+set a(0-7682) {NAME ACC1:conc#1285 TYPE CONCATENATE PAR 0-7009 XREFS 47391 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7681 {}}} SUCCS {{259 0 0-7683 {}}} CYCLES {}}
+set a(0-7683) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#414 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47392 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.40289060207082716 1 0.40289060207082716} PREDS {{258 0 0-7680 {}} {259 0 0-7682 {}}} SUCCS {{259 0 0-7684 {}}} CYCLES {}}
+set a(0-7684) {NAME ACC1:slc#83 TYPE READSLICE PAR 0-7009 XREFS 47393 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7683 {}}} SUCCS {{259 0 0-7685 {}} {258 0 0-7687 {}} {258 0 0-7689 {}} {258 0 0-8473 {}} {258 0 0-9184 {}}} CYCLES {}}
+set a(0-7685) {NAME ACC1-3:slc(acc.imod#10) TYPE READSLICE PAR 0-7009 XREFS 47394 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7684 {}}} SUCCS {{259 0 0-7686 {}}} CYCLES {}}
+set a(0-7686) {NAME ACC1:conc#1287 TYPE CONCATENATE PAR 0-7009 XREFS 47395 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7685 {}}} SUCCS {{258 0 0-7692 {}}} CYCLES {}}
+set a(0-7687) {NAME ACC1-3:slc(acc.imod#10)#1 TYPE READSLICE PAR 0-7009 XREFS 47396 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7684 {}}} SUCCS {{259 0 0-7688 {}}} CYCLES {}}
+set a(0-7688) {NAME ACC1-3:not#89 TYPE NOT PAR 0-7009 XREFS 47397 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7687 {}}} SUCCS {{258 0 0-7691 {}}} CYCLES {}}
+set a(0-7689) {NAME ACC1-3:slc(acc.imod#10)#2 TYPE READSLICE PAR 0-7009 XREFS 47398 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7684 {}}} SUCCS {{259 0 0-7690 {}}} CYCLES {}}
+set a(0-7690) {NAME ACC1-3:not#90 TYPE NOT PAR 0-7009 XREFS 47399 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7689 {}}} SUCCS {{259 0 0-7691 {}}} CYCLES {}}
+set a(0-7691) {NAME ACC1:conc#1288 TYPE CONCATENATE PAR 0-7009 XREFS 47400 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7688 {}} {259 0 0-7690 {}}} SUCCS {{259 0 0-7692 {}}} CYCLES {}}
+set a(0-7692) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#415 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47401 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.43013652707082717 1 0.43013652707082717} PREDS {{258 0 0-7686 {}} {259 0 0-7691 {}}} SUCCS {{259 0 0-7693 {}}} CYCLES {}}
+set a(0-7693) {NAME ACC1:slc#84 TYPE READSLICE PAR 0-7009 XREFS 47402 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-7692 {}}} SUCCS {{258 0 0-8447 {}} {258 0 0-8449 {}} {258 0 0-8459 {}}} CYCLES {}}
+set a(0-7694) {NAME regs.regs:asn#15 TYPE ASSIGN PAR 0-7009 XREFS 47403 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{262 0 0-9349 {}}} SUCCS {{259 0 0-7695 {}} {256 0 0-9349 {}}} CYCLES {}}
+set a(0-7695) {NAME regs.regs:slc(regs.regs(2))#10 TYPE READSLICE PAR 0-7009 XREFS 47404 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{259 0 0-7694 {}}} SUCCS {{258 0 0-7698 {}}} CYCLES {}}
+set a(0-7696) {NAME regs.regs:asn#16 TYPE ASSIGN PAR 0-7009 XREFS 47405 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{262 0 0-9349 {}}} SUCCS {{259 0 0-7697 {}} {256 0 0-9349 {}}} CYCLES {}}
+set a(0-7697) {NAME regs.regs:slc(regs.regs(2))#11 TYPE READSLICE PAR 0-7009 XREFS 47406 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{259 0 0-7696 {}}} SUCCS {{259 0 0-7698 {}}} CYCLES {}}
+set a(0-7698) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#416 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-7009 XREFS 47407 LOC {1 0.0 1 0.046457874999999996 1 0.046457874999999996 1 0.11764197833641131 1 0.11764197833641131} PREDS {{258 0 0-7695 {}} {259 0 0-7697 {}}} SUCCS {{258 0 0-7701 {}}} CYCLES {}}
+set a(0-7699) {NAME regs.regs:asn#17 TYPE ASSIGN PAR 0-7009 XREFS 47408 LOC {0 1.0 0 1.0 0 1.0 1 0.117642025} PREDS {{262 0 0-9349 {}}} SUCCS {{259 0 0-7700 {}} {256 0 0-9349 {}}} CYCLES {}}
+set a(0-7700) {NAME regs.regs:slc(regs.regs(2))#9 TYPE READSLICE PAR 0-7009 XREFS 47409 LOC {0 1.0 0 1.0 0 1.0 1 0.117642025} PREDS {{259 0 0-7699 {}}} SUCCS {{259 0 0-7701 {}}} CYCLES {}}
+set a(0-7701) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-3:acc#20 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 47410 LOC {1 0.07118415 1 0.117642025 1 0.117642025 1 0.19301278137342837 1 0.19301278137342837} PREDS {{258 0 0-7698 {}} {259 0 0-7700 {}}} SUCCS {{259 0 0-7702 {}} {258 0 0-7705 {}} {258 0 0-7707 {}} {258 0 0-7712 {}} {258 0 0-7714 {}} {258 0 0-7718 {}} {258 0 0-7720 {}} {258 0 0-7722 {}} {258 0 0-7728 {}} {258 0 0-7730 {}} {258 0 0-7732 {}} {258 0 0-7736 {}} {258 0 0-8100 {}} {258 0 0-8115 {}} {258 0 0-8120 {}} {258 0 0-8166 {}} {258 0 0-8167 {}} {258 0 0-8168 {}} {258 0 0-8241 {}} {258 0 0-8242 {}} {258 0 0-8243 {}} {258 0 0-8244 {}} {258 0 0-8553 {}} {258 0 0-8562 {}} {258 0 0-8566 {}} {258 0 0-8573 {}} {258 0 0-8601 {}} {258 0 0-8615 {}} {258 0 0-8616 {}} {258 0 0-8617 {}} {258 0 0-8621 {}} {258 0 0-8628 {}} {258 0 0-8688 {}} {258 0 0-8689 {}} {258 0 0-8693 {}} {258 0 0-8694 {}} {258 0 0-8726 {}} {258 0 0-8727 {}} {258 0 0-8728 {}} {258 0 0-8729 {}} {258 0 0-8730 {}} {258 0 0-8751 {}} {258 0 0-8753 {}} {258 0 0-8758 {}} {258 0 0-8760 {}} {258 0 0-8763 {}} {258 0 0-8765 {}} {258 0 0-8769 {}} {258 0 0-8771 {}} {258 0 0-8774 {}} {258 0 0-8776 {}} {258 0 0-8782 {}} {258 0 0-8784 {}} {258 0 0-8787 {}} {258 0 0-8789 {}} {258 0 0-8793 {}} {258 0 0-8795 {}} {258 0 0-8798 {}} {258 0 0-8800 {}} {258 0 0-8805 {}} {258 0 0-8807 {}} {258 0 0-8810 {}} {258 0 0-8812 {}} {258 0 0-8816 {}} {258 0 0-8818 {}} {258 0 0-8821 {}} {258 0 0-8823 {}} {258 0 0-8831 {}} {258 0 0-8833 {}} {258 0 0-8836 {}} {258 0 0-8838 {}} {258 0 0-8842 {}} {258 0 0-8844 {}} {258 0 0-8901 {}} {258 0 0-8903 {}} {258 0 0-8906 {}} {258 0 0-8909 {}} {258 0 0-8915 {}} {258 0 0-8918 {}} {258 0 0-9115 {}} {258 0 0-9263 {}} {258 0 0-9264 {}} {258 0 0-9265 {}} {258 0 0-9266 {}}} CYCLES {}}
+set a(0-7702) {NAME ACC1-3:slc(acc#20.psp)#11 TYPE READSLICE PAR 0-7009 XREFS 47411 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.2176873} PREDS {{259 0 0-7701 {}}} SUCCS {{259 0 0-7703 {}}} CYCLES {}}
+set a(0-7703) {NAME ACC1-3:not#304 TYPE NOT PAR 0-7009 XREFS 47412 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{259 0 0-7702 {}}} SUCCS {{259 0 0-7704 {}}} CYCLES {}}
+set a(0-7704) {NAME ACC1:conc#1294 TYPE CONCATENATE PAR 0-7009 XREFS 47413 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{259 0 0-7703 {}}} SUCCS {{258 0 0-7709 {}}} CYCLES {}}
+set a(0-7705) {NAME ACC1-3:slc(acc#20.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47414 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.2176873} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-7706 {}}} CYCLES {}}
+set a(0-7706) {NAME ACC1-3:not#260 TYPE NOT PAR 0-7009 XREFS 47415 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{259 0 0-7705 {}}} SUCCS {{258 0 0-7708 {}}} CYCLES {}}
+set a(0-7707) {NAME ACC1-3:slc(acc#20.psp)#8 TYPE READSLICE PAR 0-7009 XREFS 47416 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.2176873} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-7708 {}}} CYCLES {}}
+set a(0-7708) {NAME ACC1:conc#1295 TYPE CONCATENATE PAR 0-7009 XREFS 47417 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{258 0 0-7706 {}} {259 0 0-7707 {}}} SUCCS {{259 0 0-7709 {}}} CYCLES {}}
+set a(0-7709) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#419 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47418 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.23816006008947524 1 0.23816006008947524} PREDS {{258 0 0-7704 {}} {259 0 0-7708 {}}} SUCCS {{259 0 0-7710 {}}} CYCLES {}}
+set a(0-7710) {NAME ACC1:slc#87 TYPE READSLICE PAR 0-7009 XREFS 47419 LOC {1 0.16702775 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{259 0 0-7709 {}}} SUCCS {{259 0 0-7711 {}}} CYCLES {}}
+set a(0-7711) {NAME ACC1:conc#1298 TYPE CONCATENATE PAR 0-7009 XREFS 47420 LOC {1 0.16702775 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{259 0 0-7710 {}}} SUCCS {{258 0 0-7716 {}}} CYCLES {}}
+set a(0-7712) {NAME ACC1-3:slc(acc#20.psp) TYPE READSLICE PAR 0-7009 XREFS 47421 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23816009999999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-7713 {}}} CYCLES {}}
+set a(0-7713) {NAME ACC1:conc#1289 TYPE CONCATENATE PAR 0-7009 XREFS 47422 LOC {1 0.14655495 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{259 0 0-7712 {}}} SUCCS {{258 0 0-7715 {}}} CYCLES {}}
+set a(0-7714) {NAME ACC1-3:slc(acc#20.psp)#10 TYPE READSLICE PAR 0-7009 XREFS 47423 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23816009999999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-7715 {}}} CYCLES {}}
+set a(0-7715) {NAME ACC1:conc#1299 TYPE CONCATENATE PAR 0-7009 XREFS 47424 LOC {1 0.14655495 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{258 0 0-7713 {}} {259 0 0-7714 {}}} SUCCS {{259 0 0-7716 {}}} CYCLES {}}
+set a(0-7716) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#421 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 47425 LOC {1 0.16702775 1 0.23816009999999999 1 0.23816009999999999 1 0.2813519951789505 1 0.2813519951789505} PREDS {{258 0 0-7711 {}} {259 0 0-7715 {}}} SUCCS {{259 0 0-7717 {}}} CYCLES {}}
+set a(0-7717) {NAME ACC1:slc#89 TYPE READSLICE PAR 0-7009 XREFS 47426 LOC {1 0.21021969999999998 1 0.28135204999999996 1 0.28135204999999996 1 0.28135204999999996} PREDS {{259 0 0-7716 {}}} SUCCS {{258 0 0-7741 {}}} CYCLES {}}
+set a(0-7718) {NAME ACC1-3:slc(acc#20.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 47427 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-7719 {}}} CYCLES {}}
+set a(0-7719) {NAME ACC1:conc#1292 TYPE CONCATENATE PAR 0-7009 XREFS 47428 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-7718 {}}} SUCCS {{258 0 0-7725 {}}} CYCLES {}}
+set a(0-7720) {NAME ACC1-3:slc(acc#20.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 47429 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-7721 {}}} CYCLES {}}
+set a(0-7721) {NAME ACC1-3:not#261 TYPE NOT PAR 0-7009 XREFS 47430 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-7720 {}}} SUCCS {{258 0 0-7724 {}}} CYCLES {}}
+set a(0-7722) {NAME ACC1-3:slc(acc#20.psp)#7 TYPE READSLICE PAR 0-7009 XREFS 47431 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-7723 {}}} CYCLES {}}
+set a(0-7723) {NAME ACC1-3:not#263 TYPE NOT PAR 0-7009 XREFS 47432 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-7722 {}}} SUCCS {{259 0 0-7724 {}}} CYCLES {}}
+set a(0-7724) {NAME ACC1:conc#1293 TYPE CONCATENATE PAR 0-7009 XREFS 47433 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7721 {}} {259 0 0-7723 {}}} SUCCS {{259 0 0-7725 {}}} CYCLES {}}
+set a(0-7725) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#418 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47434 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23379583508947524 1 0.23379583508947524} PREDS {{258 0 0-7719 {}} {259 0 0-7724 {}}} SUCCS {{259 0 0-7726 {}}} CYCLES {}}
+set a(0-7726) {NAME ACC1:slc#86 TYPE READSLICE PAR 0-7009 XREFS 47435 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-7725 {}}} SUCCS {{259 0 0-7727 {}}} CYCLES {}}
+set a(0-7727) {NAME ACC1:conc#1296 TYPE CONCATENATE PAR 0-7009 XREFS 47436 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-7726 {}}} SUCCS {{258 0 0-7739 {}}} CYCLES {}}
+set a(0-7728) {NAME ACC1-3:slc(acc#20.psp)#4 TYPE READSLICE PAR 0-7009 XREFS 47437 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-7729 {}}} CYCLES {}}
+set a(0-7729) {NAME ACC1:conc#1290 TYPE CONCATENATE PAR 0-7009 XREFS 47438 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-7728 {}}} SUCCS {{258 0 0-7734 {}}} CYCLES {}}
+set a(0-7730) {NAME ACC1-3:slc(acc#20.psp)#5 TYPE READSLICE PAR 0-7009 XREFS 47439 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-7731 {}}} CYCLES {}}
+set a(0-7731) {NAME ACC1-3:not#262 TYPE NOT PAR 0-7009 XREFS 47440 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-7730 {}}} SUCCS {{258 0 0-7733 {}}} CYCLES {}}
+set a(0-7732) {NAME ACC1-3:slc(acc#20.psp)#6 TYPE READSLICE PAR 0-7009 XREFS 47441 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-7733 {}}} CYCLES {}}
+set a(0-7733) {NAME ACC1:conc#1291 TYPE CONCATENATE PAR 0-7009 XREFS 47442 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-7731 {}} {259 0 0-7732 {}}} SUCCS {{259 0 0-7734 {}}} CYCLES {}}
+set a(0-7734) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#417 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47443 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23379583508947524 1 0.23379583508947524} PREDS {{258 0 0-7729 {}} {259 0 0-7733 {}}} SUCCS {{259 0 0-7735 {}}} CYCLES {}}
+set a(0-7735) {NAME ACC1:slc#85 TYPE READSLICE PAR 0-7009 XREFS 47444 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-7734 {}}} SUCCS {{258 0 0-7738 {}}} CYCLES {}}
+set a(0-7736) {NAME ACC1-3:slc(acc#20.psp)#9 TYPE READSLICE PAR 0-7009 XREFS 47445 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.233795875} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-7737 {}}} CYCLES {}}
+set a(0-7737) {NAME ACC1-3:not#264 TYPE NOT PAR 0-7009 XREFS 47446 LOC {1 0.14655495 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-7736 {}}} SUCCS {{259 0 0-7738 {}}} CYCLES {}}
+set a(0-7738) {NAME ACC1:conc#1297 TYPE CONCATENATE PAR 0-7009 XREFS 47447 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{258 0 0-7735 {}} {259 0 0-7737 {}}} SUCCS {{259 0 0-7739 {}}} CYCLES {}}
+set a(0-7739) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#420 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47448 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.28135200207082717 1 0.28135200207082717} PREDS {{258 0 0-7727 {}} {259 0 0-7738 {}}} SUCCS {{259 0 0-7740 {}}} CYCLES {}}
+set a(0-7740) {NAME ACC1:slc#88 TYPE READSLICE PAR 0-7009 XREFS 47449 LOC {1 0.23489417499999998 1 0.28135204999999996 1 0.28135204999999996 1 0.28135204999999996} PREDS {{259 0 0-7739 {}}} SUCCS {{259 0 0-7741 {}}} CYCLES {}}
+set a(0-7741) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1-3:acc#217 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 47450 LOC {1 0.23489417499999998 1 0.28135204999999996 1 0.28135204999999996 1 0.3143888201789505 1 0.3143888201789505} PREDS {{258 0 0-7717 {}} {259 0 0-7740 {}}} SUCCS {{259 0 0-7742 {}} {258 0 0-7744 {}} {258 0 0-7746 {}} {258 0 0-7750 {}} {258 0 0-8107 {}} {258 0 0-8577 {}} {258 0 0-8585 {}} {258 0 0-8589 {}}} CYCLES {}}
+set a(0-7742) {NAME ACC1-3:slc(ACC1:acc#217.psp) TYPE READSLICE PAR 0-7009 XREFS 47451 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7741 {}}} SUCCS {{259 0 0-7743 {}}} CYCLES {}}
+set a(0-7743) {NAME ACC1:conc#1300 TYPE CONCATENATE PAR 0-7009 XREFS 47452 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7742 {}}} SUCCS {{258 0 0-7748 {}}} CYCLES {}}
+set a(0-7744) {NAME ACC1-3:slc(ACC1:acc#217.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47453 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7741 {}}} SUCCS {{259 0 0-7745 {}}} CYCLES {}}
+set a(0-7745) {NAME ACC1-3:not#287 TYPE NOT PAR 0-7009 XREFS 47454 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-7744 {}}} SUCCS {{258 0 0-7747 {}}} CYCLES {}}
+set a(0-7746) {NAME ACC1-3:slc(ACC1:acc#217.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 47455 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7741 {}}} SUCCS {{259 0 0-7747 {}}} CYCLES {}}
+set a(0-7747) {NAME ACC1:conc#1301 TYPE CONCATENATE PAR 0-7009 XREFS 47456 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-7745 {}} {259 0 0-7746 {}}} SUCCS {{259 0 0-7748 {}}} CYCLES {}}
+set a(0-7748) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#422 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47457 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.3551718850894753 1 0.3551718850894753} PREDS {{258 0 0-7743 {}} {259 0 0-7747 {}}} SUCCS {{259 0 0-7749 {}}} CYCLES {}}
+set a(0-7749) {NAME ACC1:slc#90 TYPE READSLICE PAR 0-7009 XREFS 47458 LOC {1 0.30871404999999996 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-7748 {}}} SUCCS {{258 0 0-7752 {}}} CYCLES {}}
+set a(0-7750) {NAME ACC1-3:slc(ACC1:acc#217.psp)#3 TYPE READSLICE PAR 0-7009 XREFS 47459 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.355171925} PREDS {{258 0 0-7741 {}}} SUCCS {{259 0 0-7751 {}}} CYCLES {}}
+set a(0-7751) {NAME ACC1-3:not#306 TYPE NOT PAR 0-7009 XREFS 47460 LOC {1 0.267931 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-7750 {}}} SUCCS {{259 0 0-7752 {}}} CYCLES {}}
+set a(0-7752) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-3:acc#223 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47461 LOC {1 0.30871404999999996 1 0.355171925 1 0.355171925 1 0.37564468508947524 1 0.37564468508947524} PREDS {{258 0 0-7749 {}} {259 0 0-7751 {}}} SUCCS {{259 0 0-7753 {}} {258 0 0-7756 {}} {258 0 0-8135 {}}} CYCLES {}}
+set a(0-7753) {NAME ACC1-3:slc(ACC1:acc#223.psp)#1 TYPE READSLICE PAR 0-7009 XREFS 47462 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7752 {}}} SUCCS {{259 0 0-7754 {}}} CYCLES {}}
+set a(0-7754) {NAME ACC1-3:not#299 TYPE NOT PAR 0-7009 XREFS 47463 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7753 {}}} SUCCS {{259 0 0-7755 {}}} CYCLES {}}
+set a(0-7755) {NAME ACC1:conc#1302 TYPE CONCATENATE PAR 0-7009 XREFS 47464 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7754 {}}} SUCCS {{258 0 0-7758 {}}} CYCLES {}}
+set a(0-7756) {NAME ACC1-3:slc(ACC1:acc#223.psp) TYPE READSLICE PAR 0-7009 XREFS 47465 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{258 0 0-7752 {}}} SUCCS {{259 0 0-7757 {}}} CYCLES {}}
+set a(0-7757) {NAME ACC1:conc#1303 TYPE CONCATENATE PAR 0-7009 XREFS 47466 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-7756 {}}} SUCCS {{259 0 0-7758 {}}} CYCLES {}}
+set a(0-7758) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#423 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47467 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.40289060207082716 1 0.40289060207082716} PREDS {{258 0 0-7755 {}} {259 0 0-7757 {}}} SUCCS {{259 0 0-7759 {}}} CYCLES {}}
+set a(0-7759) {NAME ACC1:slc#91 TYPE READSLICE PAR 0-7009 XREFS 47468 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7758 {}}} SUCCS {{259 0 0-7760 {}} {258 0 0-7762 {}} {258 0 0-7764 {}} {258 0 0-8596 {}} {258 0 0-9171 {}}} CYCLES {}}
+set a(0-7760) {NAME ACC1-3:slc(acc.imod#18) TYPE READSLICE PAR 0-7009 XREFS 47469 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7759 {}}} SUCCS {{259 0 0-7761 {}}} CYCLES {}}
+set a(0-7761) {NAME ACC1:conc#1305 TYPE CONCATENATE PAR 0-7009 XREFS 47470 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7760 {}}} SUCCS {{258 0 0-7767 {}}} CYCLES {}}
+set a(0-7762) {NAME ACC1-3:slc(acc.imod#18)#1 TYPE READSLICE PAR 0-7009 XREFS 47471 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7759 {}}} SUCCS {{259 0 0-7763 {}}} CYCLES {}}
+set a(0-7763) {NAME ACC1-3:not#153 TYPE NOT PAR 0-7009 XREFS 47472 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7762 {}}} SUCCS {{258 0 0-7766 {}}} CYCLES {}}
+set a(0-7764) {NAME ACC1-3:slc(acc.imod#18)#2 TYPE READSLICE PAR 0-7009 XREFS 47473 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7759 {}}} SUCCS {{259 0 0-7765 {}}} CYCLES {}}
+set a(0-7765) {NAME ACC1-3:not#154 TYPE NOT PAR 0-7009 XREFS 47474 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-7764 {}}} SUCCS {{259 0 0-7766 {}}} CYCLES {}}
+set a(0-7766) {NAME ACC1:conc#1306 TYPE CONCATENATE PAR 0-7009 XREFS 47475 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-7763 {}} {259 0 0-7765 {}}} SUCCS {{259 0 0-7767 {}}} CYCLES {}}
+set a(0-7767) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#424 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47476 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.43013652707082717 1 0.43013652707082717} PREDS {{258 0 0-7761 {}} {259 0 0-7766 {}}} SUCCS {{259 0 0-7768 {}}} CYCLES {}}
+set a(0-7768) {NAME ACC1:slc#92 TYPE READSLICE PAR 0-7009 XREFS 47477 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-7767 {}}} SUCCS {{258 0 0-8121 {}} {258 0 0-8123 {}} {258 0 0-8600 {}}} CYCLES {}}
+set a(0-7769) {NAME slc(ACC1-1:acc#25.psp)#5 TYPE READSLICE PAR 0-7009 XREFS 47478 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.9246291999999999} PREDS {{258 0 0-7252 {}}} SUCCS {{258 0 0-7775 {}}} CYCLES {}}
+set a(0-7770) {NAME slc(ACC1-1:acc#25.psp)#6 TYPE READSLICE PAR 0-7009 XREFS 47479 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.9246291999999999} PREDS {{258 0 0-7252 {}}} SUCCS {{258 0 0-7775 {}}} CYCLES {}}
+set a(0-7771) {NAME slc(ACC1-1:acc#25.psp)#7 TYPE READSLICE PAR 0-7009 XREFS 47480 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.9246291999999999} PREDS {{258 0 0-7252 {}}} SUCCS {{258 0 0-7775 {}}} CYCLES {}}
+set a(0-7772) {NAME slc(ACC1-1:acc#25.psp)#8 TYPE READSLICE PAR 0-7009 XREFS 47481 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.9246291999999999} PREDS {{258 0 0-7252 {}}} SUCCS {{258 0 0-7775 {}}} CYCLES {}}
+set a(0-7773) {NAME slc(ACC1-1:acc#25.psp) TYPE READSLICE PAR 0-7009 XREFS 47482 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.9246291999999999} PREDS {{258 0 0-7252 {}}} SUCCS {{258 0 0-7775 {}}} CYCLES {}}
+set a(0-7774) {NAME ACC1:slc(ACC1:acc#224.psp)#47 TYPE READSLICE PAR 0-7009 XREFS 47483 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.9246291999999999} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-7775 {}}} CYCLES {}}
+set a(0-7775) {NAME ACC1:conc#1078 TYPE CONCATENATE PAR 0-7009 XREFS 47484 LOC {1 0.14655495 1 0.84514095 1 0.84514095 1 0.9246291999999999} PREDS {{258 0 0-7773 {}} {258 0 0-7772 {}} {258 0 0-7771 {}} {258 0 0-7770 {}} {258 0 0-7769 {}} {259 0 0-7774 {}}} SUCCS {{258 0 0-7796 {}}} CYCLES {}}
+set a(0-7776) {NAME ACC1:slc(ACC1:acc#227.psp)#61 TYPE READSLICE PAR 0-7009 XREFS 47485 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.573416975} PREDS {{258 0 0-7554 {}}} SUCCS {{258 0 0-7778 {}}} CYCLES {}}
+set a(0-7777) {NAME ACC1:slc(acc.psp#1)#60 TYPE READSLICE PAR 0-7009 XREFS 47486 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.573416975} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-7778 {}}} CYCLES {}}
+set a(0-7778) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#326 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-7009 XREFS 47487 LOC {1 0.14655495 1 0.49392872499999996 1 0.49392872499999996 1 0.52553956125 1 0.60502781125} PREDS {{258 0 0-7776 {}} {259 0 0-7777 {}}} SUCCS {{258 0 0-7780 {}}} CYCLES {}}
+set a(0-7779) {NAME ACC1:slc(ACC1:acc#224.psp)#51 TYPE READSLICE PAR 0-7009 XREFS 47488 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6050278499999999} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-7780 {}}} CYCLES {}}
+set a(0-7780) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#325 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47489 LOC {1 0.178165825 1 0.5255396 1 0.5255396 1 0.5460123600894753 1 0.6255006100894752} PREDS {{258 0 0-7778 {}} {259 0 0-7779 {}}} SUCCS {{258 0 0-7782 {}}} CYCLES {}}
+set a(0-7781) {NAME ACC1:slc(ACC1:acc#228.psp)#51 TYPE READSLICE PAR 0-7009 XREFS 47490 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.62550065} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-7782 {}}} CYCLES {}}
+set a(0-7782) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#324 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47491 LOC {1 0.19863862499999999 1 0.5460124 1 0.5460124 1 0.5664851600894752 1 0.6459734100894753} PREDS {{258 0 0-7780 {}} {259 0 0-7781 {}}} SUCCS {{258 0 0-7784 {}}} CYCLES {}}
+set a(0-7783) {NAME ACC1:slc(ACC1:acc#226.psp)#42 TYPE READSLICE PAR 0-7009 XREFS 47492 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.64597345} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-7784 {}}} CYCLES {}}
+set a(0-7784) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#323 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47493 LOC {1 0.219111425 1 0.5664852 1 0.5664852 1 0.5937310770708272 1 0.6732193270708271} PREDS {{258 0 0-7782 {}} {259 0 0-7783 {}}} SUCCS {{258 0 0-7786 {}}} CYCLES {}}
+set a(0-7785) {NAME ACC1:slc(ACC1:acc#224.psp#1)#23 TYPE READSLICE PAR 0-7009 XREFS 47494 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.673219375} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-7786 {}}} CYCLES {}}
+set a(0-7786) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#322 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47495 LOC {1 0.24635735 1 0.593731125 1 0.593731125 1 0.6209770020708272 1 0.7004652520708271} PREDS {{258 0 0-7784 {}} {259 0 0-7785 {}}} SUCCS {{258 0 0-7788 {}}} CYCLES {}}
+set a(0-7787) {NAME ACC1:slc(ACC1-1:acc#25.psp)#20 TYPE READSLICE PAR 0-7009 XREFS 47496 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.7004653} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-7788 {}}} CYCLES {}}
+set a(0-7788) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#321 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47497 LOC {1 0.273603275 1 0.6209770499999999 1 0.6209770499999999 1 0.6482229270708271 1 0.7277111770708271} PREDS {{258 0 0-7786 {}} {259 0 0-7787 {}}} SUCCS {{258 0 0-7790 {}}} CYCLES {}}
+set a(0-7789) {NAME ACC1:slc(acc.psp#2)#9 TYPE READSLICE PAR 0-7009 XREFS 47498 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.727711225} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7790 {}}} CYCLES {}}
+set a(0-7790) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#320 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47499 LOC {1 0.3008492 1 0.6482229749999999 1 0.6482229749999999 1 0.6754688520708271 1 0.7549571020708271} PREDS {{258 0 0-7788 {}} {259 0 0-7789 {}}} SUCCS {{259 0 0-7791 {}}} CYCLES {}}
+set a(0-7791) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(4,0,5,0,8) AREA_SCORE 330.25 QUANTITY 2 NAME ACC1:mul#58 TYPE MUL DELAY {2.71 ns} LIBRARY_DELAY {2.71 ns} PAR 0-7009 XREFS 47500 LOC {1 0.328095125 1 0.6754688999999999 1 0.6754688999999999 1 0.8451408976245128 1 0.9246291476245129} PREDS {{259 0 0-7790 {}}} SUCCS {{258 0 0-7795 {}}} CYCLES {}}
+set a(0-7792) {NAME ACC1:slc(ACC1:acc#227.psp)#62 TYPE READSLICE PAR 0-7009 XREFS 47501 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.9246291999999999} PREDS {{258 0 0-7554 {}}} SUCCS {{258 0 0-7795 {}}} CYCLES {}}
+set a(0-7793) {NAME ACC1-3:slc(acc#10.psp)#68 TYPE READSLICE PAR 0-7009 XREFS 47502 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.9246291999999999} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-7794 {}}} CYCLES {}}
+set a(0-7794) {NAME ACC1-3:exs#51 TYPE SIGNEXTEND PAR 0-7009 XREFS 47503 LOC {1 0.14655495 1 0.84514095 1 0.84514095 1 0.9246291999999999} PREDS {{259 0 0-7793 {}}} SUCCS {{259 0 0-7795 {}}} CYCLES {}}
+set a(0-7795) {NAME ACC1:conc#1105 TYPE CONCATENATE PAR 0-7009 XREFS 47504 LOC {1 0.49776717499999995 1 0.84514095 1 0.84514095 1 0.9246291999999999} PREDS {{258 0 0-7792 {}} {258 0 0-7791 {}} {259 0 0-7794 {}}} SUCCS {{259 0 0-7796 {}}} CYCLES {}}
+set a(0-7796) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME ACC1:acc#654 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 47505 LOC {1 0.49776717499999995 1 0.84514095 1 0.84514095 1 0.9205117063734284 1 0.9999999563734283} PREDS {{258 0 0-7775 {}} {259 0 0-7795 {}}} SUCCS {{258 0 0-8083 {}}} CYCLES {}}
+set a(0-7797) {NAME ACC1-1:slc(acc.psp)#57 TYPE READSLICE PAR 0-7009 XREFS 47506 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7802 {}}} CYCLES {}}
+set a(0-7798) {NAME ACC1-1:slc(acc.psp)#58 TYPE READSLICE PAR 0-7009 XREFS 47507 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7802 {}}} CYCLES {}}
+set a(0-7799) {NAME ACC1-1:slc(acc.psp)#59 TYPE READSLICE PAR 0-7009 XREFS 47508 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7802 {}}} CYCLES {}}
+set a(0-7800) {NAME ACC1-1:slc(acc.psp)#60 TYPE READSLICE PAR 0-7009 XREFS 47509 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7802 {}}} CYCLES {}}
+set a(0-7801) {NAME ACC1-1:slc(acc.psp)#48 TYPE READSLICE PAR 0-7009 XREFS 47510 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7802 {}}} CYCLES {}}
+set a(0-7802) {NAME ACC1-1:conc#554 TYPE CONCATENATE PAR 0-7009 XREFS 47511 LOC {1 0.14655495 1 0.6519825499999999 1 0.6519825499999999 1 0.7314708} PREDS {{258 0 0-7800 {}} {258 0 0-7799 {}} {258 0 0-7798 {}} {258 0 0-7797 {}} {259 0 0-7801 {}}} SUCCS {{258 0 0-7855 {}}} CYCLES {}}
+set a(0-7803) {NAME ACC1-1:slc(acc.psp)#63 TYPE READSLICE PAR 0-7009 XREFS 47512 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7808 {}}} CYCLES {}}
+set a(0-7804) {NAME ACC1-1:slc(acc.psp)#64 TYPE READSLICE PAR 0-7009 XREFS 47513 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7808 {}}} CYCLES {}}
+set a(0-7805) {NAME ACC1-1:slc(acc.psp)#50 TYPE READSLICE PAR 0-7009 XREFS 47514 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7808 {}}} CYCLES {}}
+set a(0-7806) {NAME ACC1-1:slc(acc.psp)#65 TYPE READSLICE PAR 0-7009 XREFS 47515 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7807 {}}} CYCLES {}}
+set a(0-7807) {NAME ACC1-1:exs TYPE SIGNEXTEND PAR 0-7009 XREFS 47516 LOC {1 0.14655495 1 0.59959805 1 0.59959805 1 0.6790862999999999} PREDS {{259 0 0-7806 {}}} SUCCS {{259 0 0-7808 {}}} CYCLES {}}
+set a(0-7808) {NAME ACC1-1:conc#559 TYPE CONCATENATE PAR 0-7009 XREFS 47517 LOC {1 0.14655495 1 0.59959805 1 0.59959805 1 0.6790862999999999} PREDS {{258 0 0-7805 {}} {258 0 0-7804 {}} {258 0 0-7803 {}} {259 0 0-7807 {}}} SUCCS {{258 0 0-7854 {}}} CYCLES {}}
+set a(0-7809) {NAME ACC1-1:slc(acc.psp)#36 TYPE READSLICE PAR 0-7009 XREFS 47518 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6358845249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7813 {}}} CYCLES {}}
+set a(0-7810) {NAME ACC1-1:slc(acc.psp)#37 TYPE READSLICE PAR 0-7009 XREFS 47519 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6358845249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7813 {}}} CYCLES {}}
+set a(0-7811) {NAME ACC1-1:slc(acc.idiv)#29 TYPE READSLICE PAR 0-7009 XREFS 47520 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6358845249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7812 {}}} CYCLES {}}
+set a(0-7812) {NAME ACC1-1:exs#14 TYPE SIGNEXTEND PAR 0-7009 XREFS 47521 LOC {1 0.14655495 1 0.556396275 1 0.556396275 1 0.6358845249999999} PREDS {{259 0 0-7811 {}}} SUCCS {{259 0 0-7813 {}}} CYCLES {}}
+set a(0-7813) {NAME ACC1-1:conc#563 TYPE CONCATENATE PAR 0-7009 XREFS 47522 LOC {1 0.14655495 1 0.556396275 1 0.556396275 1 0.6358845249999999} PREDS {{258 0 0-7810 {}} {258 0 0-7809 {}} {259 0 0-7812 {}}} SUCCS {{258 0 0-7853 {}}} CYCLES {}}
+set a(0-7814) {NAME ACC1-1:slc(acc.idiv)#5 TYPE READSLICE PAR 0-7009 XREFS 47523 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7815 {}}} CYCLES {}}
+set a(0-7815) {NAME ACC1-1:exs#2 TYPE SIGNEXTEND PAR 0-7009 XREFS 47524 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7814 {}}} SUCCS {{259 0 0-7816 {}}} CYCLES {}}
+set a(0-7816) {NAME ACC1:conc#1429 TYPE CONCATENATE PAR 0-7009 XREFS 47525 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7815 {}}} SUCCS {{258 0 0-7820 {}}} CYCLES {}}
+set a(0-7817) {NAME ACC1-1:slc(acc.idiv)#7 TYPE READSLICE PAR 0-7009 XREFS 47526 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7818 {}}} CYCLES {}}
+set a(0-7818) {NAME ACC1-1:exs#3 TYPE SIGNEXTEND PAR 0-7009 XREFS 47527 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7817 {}}} SUCCS {{259 0 0-7819 {}}} CYCLES {}}
+set a(0-7819) {NAME ACC1:conc#1430 TYPE CONCATENATE PAR 0-7009 XREFS 47528 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-7093 {}} {259 0 0-7818 {}}} SUCCS {{259 0 0-7820 {}}} CYCLES {}}
+set a(0-7820) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#670 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47529 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-7816 {}} {259 0 0-7819 {}}} SUCCS {{259 0 0-7821 {}}} CYCLES {}}
+set a(0-7821) {NAME ACC1:slc#153 TYPE READSLICE PAR 0-7009 XREFS 47530 LOC {1 0.43123487499999996 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-7820 {}}} SUCCS {{258 0 0-7832 {}}} CYCLES {}}
+set a(0-7822) {NAME ACC1-1:slc(acc.idiv)#15 TYPE READSLICE PAR 0-7009 XREFS 47531 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7823 {}}} CYCLES {}}
+set a(0-7823) {NAME ACC1-1:exs#7 TYPE SIGNEXTEND PAR 0-7009 XREFS 47532 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7822 {}}} SUCCS {{259 0 0-7824 {}}} CYCLES {}}
+set a(0-7824) {NAME ACC1:conc#1427 TYPE CONCATENATE PAR 0-7009 XREFS 47533 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7823 {}}} SUCCS {{258 0 0-7830 {}}} CYCLES {}}
+set a(0-7825) {NAME ACC1-1:slc(acc.idiv)#17 TYPE READSLICE PAR 0-7009 XREFS 47534 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7826 {}}} CYCLES {}}
+set a(0-7826) {NAME ACC1-1:exs#8 TYPE SIGNEXTEND PAR 0-7009 XREFS 47535 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7825 {}}} SUCCS {{258 0 0-7829 {}}} CYCLES {}}
+set a(0-7827) {NAME ACC1-1:slc(acc.imod#2)#12 TYPE READSLICE PAR 0-7009 XREFS 47536 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.4874251} PREDS {{258 0 0-7080 {}}} SUCCS {{259 0 0-7828 {}}} CYCLES {}}
+set a(0-7828) {NAME ACC1-1:not#294 TYPE NOT PAR 0-7009 XREFS 47537 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7827 {}}} SUCCS {{259 0 0-7829 {}}} CYCLES {}}
+set a(0-7829) {NAME ACC1:conc#1428 TYPE CONCATENATE PAR 0-7009 XREFS 47538 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-7826 {}} {259 0 0-7828 {}}} SUCCS {{259 0 0-7830 {}}} CYCLES {}}
+set a(0-7830) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#669 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47539 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-7824 {}} {259 0 0-7829 {}}} SUCCS {{259 0 0-7831 {}}} CYCLES {}}
+set a(0-7831) {NAME ACC1:slc#152 TYPE READSLICE PAR 0-7009 XREFS 47540 LOC {1 0.40398894999999996 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-7830 {}}} SUCCS {{259 0 0-7832 {}}} CYCLES {}}
+set a(0-7832) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#676 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47541 LOC {1 0.43123487499999996 1 0.455493025 1 0.455493025 1 0.5030491520708271 1 0.582537402070827} PREDS {{258 0 0-7821 {}} {259 0 0-7831 {}}} SUCCS {{258 0 0-7852 {}}} CYCLES {}}
+set a(0-7833) {NAME ACC1-1:slc(acc.idiv)#13 TYPE READSLICE PAR 0-7009 XREFS 47542 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7834 {}}} CYCLES {}}
+set a(0-7834) {NAME ACC1-1:exs#6 TYPE SIGNEXTEND PAR 0-7009 XREFS 47543 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7833 {}}} SUCCS {{259 0 0-7835 {}}} CYCLES {}}
+set a(0-7835) {NAME ACC1:conc#1425 TYPE CONCATENATE PAR 0-7009 XREFS 47544 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7834 {}}} SUCCS {{258 0 0-7840 {}}} CYCLES {}}
+set a(0-7836) {NAME ACC1-1:slc(acc.idiv)#23 TYPE READSLICE PAR 0-7009 XREFS 47545 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7837 {}}} CYCLES {}}
+set a(0-7837) {NAME ACC1-1:exs#11 TYPE SIGNEXTEND PAR 0-7009 XREFS 47546 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7836 {}}} SUCCS {{258 0 0-7839 {}}} CYCLES {}}
+set a(0-7838) {NAME ACC1-1:slc(acc.imod#2)#11 TYPE READSLICE PAR 0-7009 XREFS 47547 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.4874251} PREDS {{258 0 0-7080 {}}} SUCCS {{259 0 0-7839 {}}} CYCLES {}}
+set a(0-7839) {NAME ACC1:conc#1426 TYPE CONCATENATE PAR 0-7009 XREFS 47548 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-7837 {}} {259 0 0-7838 {}}} SUCCS {{259 0 0-7840 {}}} CYCLES {}}
+set a(0-7840) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#668 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47549 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-7835 {}} {259 0 0-7839 {}}} SUCCS {{259 0 0-7841 {}}} CYCLES {}}
+set a(0-7841) {NAME ACC1:slc#151 TYPE READSLICE PAR 0-7009 XREFS 47550 LOC {1 0.40398894999999996 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-7840 {}}} SUCCS {{258 0 0-7851 {}}} CYCLES {}}
+set a(0-7842) {NAME ACC1-1:slc(acc.idiv)#19 TYPE READSLICE PAR 0-7009 XREFS 47551 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7843 {}}} CYCLES {}}
+set a(0-7843) {NAME ACC1-1:exs#9 TYPE SIGNEXTEND PAR 0-7009 XREFS 47552 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7842 {}}} SUCCS {{259 0 0-7844 {}}} CYCLES {}}
+set a(0-7844) {NAME ACC1:conc#1423 TYPE CONCATENATE PAR 0-7009 XREFS 47553 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7843 {}}} SUCCS {{258 0 0-7849 {}}} CYCLES {}}
+set a(0-7845) {NAME ACC1-1:slc(acc.idiv)#21 TYPE READSLICE PAR 0-7009 XREFS 47554 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7846 {}}} CYCLES {}}
+set a(0-7846) {NAME ACC1-1:exs#10 TYPE SIGNEXTEND PAR 0-7009 XREFS 47555 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7845 {}}} SUCCS {{258 0 0-7848 {}}} CYCLES {}}
+set a(0-7847) {NAME ACC1-1:slc(ACC1:acc#210.psp)#9 TYPE READSLICE PAR 0-7009 XREFS 47556 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.4874251} PREDS {{258 0 0-7062 {}}} SUCCS {{259 0 0-7848 {}}} CYCLES {}}
+set a(0-7848) {NAME ACC1:conc#1424 TYPE CONCATENATE PAR 0-7009 XREFS 47557 LOC {1 0.267931 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-7846 {}} {259 0 0-7847 {}}} SUCCS {{259 0 0-7849 {}}} CYCLES {}}
+set a(0-7849) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#667 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47558 LOC {1 0.267931 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-7844 {}} {259 0 0-7848 {}}} SUCCS {{259 0 0-7850 {}}} CYCLES {}}
+set a(0-7850) {NAME ACC1:slc#150 TYPE READSLICE PAR 0-7009 XREFS 47559 LOC {1 0.315487175 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-7849 {}}} SUCCS {{259 0 0-7851 {}}} CYCLES {}}
+set a(0-7851) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#675 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47560 LOC {1 0.40398894999999996 1 0.455493025 1 0.455493025 1 0.5030491520708271 1 0.582537402070827} PREDS {{258 0 0-7841 {}} {259 0 0-7850 {}}} SUCCS {{259 0 0-7852 {}}} CYCLES {}}
+set a(0-7852) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#680 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 47561 LOC {1 0.47879105 1 0.5030492 1 0.5030492 1 0.5563962201789505 1 0.6358844701789506} PREDS {{258 0 0-7832 {}} {259 0 0-7851 {}}} SUCCS {{259 0 0-7853 {}}} CYCLES {}}
+set a(0-7853) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 5 NAME ACC1:acc#683 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 47562 LOC {1 0.532138125 1 0.556396275 1 0.556396275 1 0.5995979984103024 1 0.6790862484103023} PREDS {{258 0 0-7813 {}} {259 0 0-7852 {}}} SUCCS {{259 0 0-7854 {}}} CYCLES {}}
+set a(0-7854) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#686 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-7009 XREFS 47563 LOC {1 0.5753399 1 0.59959805 1 0.59959805 1 0.6519825027684257 1 0.7314707527684257} PREDS {{258 0 0-7808 {}} {259 0 0-7853 {}}} SUCCS {{259 0 0-7855 {}}} CYCLES {}}
+set a(0-7855) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,1,11) AREA_SCORE 10.00 QUANTITY 5 NAME ACC1:acc#688 TYPE ACCU DELAY {0.91 ns} LIBRARY_DELAY {0.91 ns} PAR 0-7009 XREFS 47564 LOC {1 0.6277244 1 0.6519825499999999 1 0.6519825499999999 1 0.7087410628916543 1 0.7882293128916543} PREDS {{258 0 0-7802 {}} {259 0 0-7854 {}}} SUCCS {{258 0 0-7922 {}}} CYCLES {}}
+set a(0-7856) {NAME ACC1-1:slc(acc.psp)#29 TYPE READSLICE PAR 0-7009 XREFS 47565 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5312430499999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7857 {}}} CYCLES {}}
+set a(0-7857) {NAME ACC1:conc#1418 TYPE CONCATENATE PAR 0-7009 XREFS 47566 LOC {1 0.14655495 1 0.45175479999999996 1 0.45175479999999996 1 0.5312430499999999} PREDS {{259 0 0-7856 {}}} SUCCS {{259 0 0-7858 {}}} CYCLES {}}
+set a(0-7858) {NAME ACC1:conc#1419 TYPE CONCATENATE PAR 0-7009 XREFS 47567 LOC {1 0.14655495 1 0.45175479999999996 1 0.45175479999999996 1 0.5312430499999999} PREDS {{259 0 0-7857 {}}} SUCCS {{258 0 0-7862 {}}} CYCLES {}}
+set a(0-7859) {NAME ACC1-1:slc(ACC1:acc#210.psp)#10 TYPE READSLICE PAR 0-7009 XREFS 47568 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.5312430499999999} PREDS {{258 0 0-7062 {}}} SUCCS {{258 0 0-7861 {}}} CYCLES {}}
+set a(0-7860) {NAME ACC1-1:slc(acc.psp)#30 TYPE READSLICE PAR 0-7009 XREFS 47569 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5312430499999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7861 {}}} CYCLES {}}
+set a(0-7861) {NAME ACC1:conc#1420 TYPE CONCATENATE PAR 0-7009 XREFS 47570 LOC {1 0.267931 1 0.45175479999999996 1 0.45175479999999996 1 0.5312430499999999} PREDS {{258 0 0-7859 {}} {259 0 0-7860 {}}} SUCCS {{259 0 0-7862 {}}} CYCLES {}}
+set a(0-7862) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 4 NAME ACC1:acc#665 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-7009 XREFS 47571 LOC {1 0.267931 1 0.45175479999999996 1 0.45175479999999996 1 0.4893753770241716 1 0.5688636270241716} PREDS {{258 0 0-7858 {}} {259 0 0-7861 {}}} SUCCS {{259 0 0-7863 {}}} CYCLES {}}
+set a(0-7863) {NAME ACC1:slc#148 TYPE READSLICE PAR 0-7009 XREFS 47572 LOC {1 0.305551625 1 0.489375425 1 0.489375425 1 0.568863675} PREDS {{259 0 0-7862 {}}} SUCCS {{258 0 0-7865 {}}} CYCLES {}}
+set a(0-7864) {NAME ACC1-1:slc(ACC1:acc#220.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 47573 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.568863675} PREDS {{258 0 0-7073 {}}} SUCCS {{259 0 0-7865 {}}} CYCLES {}}
+set a(0-7865) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 4 NAME ACC1:acc#674 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-7009 XREFS 47574 LOC {1 0.32918685 1 0.489375425 1 0.489375425 1 0.5269960020241716 1 0.6064842520241717} PREDS {{258 0 0-7863 {}} {259 0 0-7864 {}}} SUCCS {{258 0 0-7877 {}}} CYCLES {}}
+set a(0-7866) {NAME ACC1-1:slc(acc.psp)#31 TYPE READSLICE PAR 0-7009 XREFS 47575 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.579238375} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7868 {}}} CYCLES {}}
+set a(0-7867) {NAME ACC1-1:slc(acc.psp)#32 TYPE READSLICE PAR 0-7009 XREFS 47576 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.579238375} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7868 {}}} CYCLES {}}
+set a(0-7868) {NAME ACC1-1:conc#556 TYPE CONCATENATE PAR 0-7009 XREFS 47577 LOC {1 0.14655495 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{258 0 0-7866 {}} {259 0 0-7867 {}}} SUCCS {{259 0 0-7869 {}}} CYCLES {}}
+set a(0-7869) {NAME ACC1:conc#1421 TYPE CONCATENATE PAR 0-7009 XREFS 47578 LOC {1 0.14655495 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{259 0 0-7868 {}}} SUCCS {{258 0 0-7875 {}}} CYCLES {}}
+set a(0-7870) {NAME ACC1-1:slc(ACC1:acc#210.psp)#11 TYPE READSLICE PAR 0-7009 XREFS 47579 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.579238375} PREDS {{258 0 0-7062 {}}} SUCCS {{258 0 0-7872 {}}} CYCLES {}}
+set a(0-7871) {NAME ACC1-1:slc(acc.psp)#33 TYPE READSLICE PAR 0-7009 XREFS 47580 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.579238375} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7872 {}}} CYCLES {}}
+set a(0-7872) {NAME ACC1-1:conc#557 TYPE CONCATENATE PAR 0-7009 XREFS 47581 LOC {1 0.267931 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{258 0 0-7870 {}} {259 0 0-7871 {}}} SUCCS {{258 0 0-7874 {}}} CYCLES {}}
+set a(0-7873) {NAME ACC1-1:slc(ACC1:acc#210.psp)#8 TYPE READSLICE PAR 0-7009 XREFS 47582 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.579238375} PREDS {{258 0 0-7062 {}}} SUCCS {{259 0 0-7874 {}}} CYCLES {}}
+set a(0-7874) {NAME ACC1:conc#1422 TYPE CONCATENATE PAR 0-7009 XREFS 47583 LOC {1 0.267931 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{258 0 0-7872 {}} {259 0 0-7873 {}}} SUCCS {{259 0 0-7875 {}}} CYCLES {}}
+set a(0-7875) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#666 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47584 LOC {1 0.267931 1 0.499750125 1 0.499750125 1 0.5269960020708272 1 0.6064842520708271} PREDS {{258 0 0-7869 {}} {259 0 0-7874 {}}} SUCCS {{259 0 0-7876 {}}} CYCLES {}}
+set a(0-7876) {NAME ACC1:slc#149 TYPE READSLICE PAR 0-7009 XREFS 47585 LOC {1 0.295176925 1 0.5269960499999999 1 0.5269960499999999 1 0.6064843} PREDS {{259 0 0-7875 {}}} SUCCS {{259 0 0-7877 {}}} CYCLES {}}
+set a(0-7877) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#679 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 47586 LOC {1 0.366807475 1 0.5269960499999999 1 0.5269960499999999 1 0.5701879451789504 1 0.6496761951789505} PREDS {{258 0 0-7865 {}} {259 0 0-7876 {}}} SUCCS {{258 0 0-7889 {}}} CYCLES {}}
+set a(0-7878) {NAME ACC1-1:slc(acc.psp)#34 TYPE READSLICE PAR 0-7009 XREFS 47587 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.616639425} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7882 {}}} CYCLES {}}
+set a(0-7879) {NAME ACC1-1:slc(acc.psp)#35 TYPE READSLICE PAR 0-7009 XREFS 47588 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.616639425} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7882 {}}} CYCLES {}}
+set a(0-7880) {NAME ACC1-1:slc(acc.idiv)#31 TYPE READSLICE PAR 0-7009 XREFS 47589 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.616639425} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7881 {}}} CYCLES {}}
+set a(0-7881) {NAME ACC1-1:exs#15 TYPE SIGNEXTEND PAR 0-7009 XREFS 47590 LOC {1 0.14655495 1 0.537151175 1 0.537151175 1 0.616639425} PREDS {{259 0 0-7880 {}}} SUCCS {{259 0 0-7882 {}}} CYCLES {}}
+set a(0-7882) {NAME ACC1-1:conc#558 TYPE CONCATENATE PAR 0-7009 XREFS 47591 LOC {1 0.14655495 1 0.537151175 1 0.537151175 1 0.616639425} PREDS {{258 0 0-7879 {}} {258 0 0-7878 {}} {259 0 0-7881 {}}} SUCCS {{258 0 0-7888 {}}} CYCLES {}}
+set a(0-7883) {NAME ACC1-1:slc(acc.idiv)#33 TYPE READSLICE PAR 0-7009 XREFS 47592 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.575856375} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7884 {}}} CYCLES {}}
+set a(0-7884) {NAME ACC1-1:exs#16 TYPE SIGNEXTEND PAR 0-7009 XREFS 47593 LOC {1 0.14655495 1 0.496368125 1 0.496368125 1 0.575856375} PREDS {{259 0 0-7883 {}}} SUCCS {{258 0 0-7887 {}}} CYCLES {}}
+set a(0-7885) {NAME ACC1-1:slc(acc.idiv)#35 TYPE READSLICE PAR 0-7009 XREFS 47594 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.575856375} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7886 {}}} CYCLES {}}
+set a(0-7886) {NAME ACC1-1:exs#17 TYPE SIGNEXTEND PAR 0-7009 XREFS 47595 LOC {1 0.14655495 1 0.496368125 1 0.496368125 1 0.575856375} PREDS {{259 0 0-7885 {}}} SUCCS {{259 0 0-7887 {}}} CYCLES {}}
+set a(0-7887) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#673 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47596 LOC {1 0.14655495 1 0.496368125 1 0.496368125 1 0.5371511350894752 1 0.6166393850894752} PREDS {{258 0 0-7884 {}} {259 0 0-7886 {}}} SUCCS {{259 0 0-7888 {}}} CYCLES {}}
+set a(0-7888) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#678 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 47597 LOC {1 0.187338 1 0.537151175 1 0.537151175 1 0.5701879451789504 1 0.6496761951789505} PREDS {{258 0 0-7882 {}} {259 0 0-7887 {}}} SUCCS {{259 0 0-7889 {}}} CYCLES {}}
+set a(0-7889) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#682 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-7009 XREFS 47598 LOC {1 0.409999425 1 0.570188 1 0.570188 1 0.6084774594969361 1 0.687965709496936} PREDS {{258 0 0-7877 {}} {259 0 0-7888 {}}} SUCCS {{258 0 0-7895 {}}} CYCLES {}}
+set a(0-7890) {NAME ACC1-1:slc(acc.psp)#54 TYPE READSLICE PAR 0-7009 XREFS 47599 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7894 {}}} CYCLES {}}
+set a(0-7891) {NAME ACC1-1:slc(acc.psp)#55 TYPE READSLICE PAR 0-7009 XREFS 47600 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7894 {}}} CYCLES {}}
+set a(0-7892) {NAME ACC1-1:slc(acc.psp)#56 TYPE READSLICE PAR 0-7009 XREFS 47601 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7894 {}}} CYCLES {}}
+set a(0-7893) {NAME ACC1-1:slc(acc.psp)#47 TYPE READSLICE PAR 0-7009 XREFS 47602 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7894 {}}} CYCLES {}}
+set a(0-7894) {NAME ACC1-1:conc#553 TYPE CONCATENATE PAR 0-7009 XREFS 47603 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{258 0 0-7892 {}} {258 0 0-7891 {}} {258 0 0-7890 {}} {259 0 0-7893 {}}} SUCCS {{259 0 0-7895 {}}} CYCLES {}}
+set a(0-7895) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 6 NAME ACC1:acc#685 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-7009 XREFS 47604 LOC {1 0.448288925 1 0.6084775 1 0.6084775 1 0.656356562932968 1 0.7358448129329679} PREDS {{258 0 0-7889 {}} {259 0 0-7894 {}}} SUCCS {{258 0 0-7921 {}}} CYCLES {}}
+set a(0-7896) {NAME ACC1-1:slc(acc.psp)#17 TYPE READSLICE PAR 0-7009 XREFS 47605 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7899 {}}} CYCLES {}}
+set a(0-7897) {NAME ACC1-1:slc(acc.idiv)#25 TYPE READSLICE PAR 0-7009 XREFS 47606 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7898 {}}} CYCLES {}}
+set a(0-7898) {NAME ACC1-1:exs#12 TYPE SIGNEXTEND PAR 0-7009 XREFS 47607 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{259 0 0-7897 {}}} SUCCS {{259 0 0-7899 {}}} CYCLES {}}
+set a(0-7899) {NAME ACC1-1:conc#482 TYPE CONCATENATE PAR 0-7009 XREFS 47608 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{258 0 0-7896 {}} {259 0 0-7898 {}}} SUCCS {{259 0 0-7900 {}}} CYCLES {}}
+set a(0-7900) {NAME ACC1-1:exs#1029 TYPE SIGNEXTEND PAR 0-7009 XREFS 47609 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{259 0 0-7899 {}}} SUCCS {{258 0 0-7920 {}}} CYCLES {}}
+set a(0-7901) {NAME ACC1-1:slc(acc.psp)#52 TYPE READSLICE PAR 0-7009 XREFS 47610 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.64967625} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7904 {}}} CYCLES {}}
+set a(0-7902) {NAME ACC1-1:slc(acc.psp)#53 TYPE READSLICE PAR 0-7009 XREFS 47611 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.64967625} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7904 {}}} CYCLES {}}
+set a(0-7903) {NAME ACC1-1:slc(acc.psp)#46 TYPE READSLICE PAR 0-7009 XREFS 47612 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.64967625} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7904 {}}} CYCLES {}}
+set a(0-7904) {NAME ACC1-1:conc TYPE CONCATENATE PAR 0-7009 XREFS 47613 LOC {1 0.14655495 1 0.570188 1 0.570188 1 0.64967625} PREDS {{258 0 0-7902 {}} {258 0 0-7901 {}} {259 0 0-7903 {}}} SUCCS {{258 0 0-7919 {}}} CYCLES {}}
+set a(0-7905) {NAME ACC1-1:slc(acc.idiv)#9 TYPE READSLICE PAR 0-7009 XREFS 47614 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5613370249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7906 {}}} CYCLES {}}
+set a(0-7906) {NAME ACC1-1:exs#4 TYPE SIGNEXTEND PAR 0-7009 XREFS 47615 LOC {1 0.14655495 1 0.48184877499999995 1 0.48184877499999995 1 0.5613370249999999} PREDS {{259 0 0-7905 {}}} SUCCS {{258 0 0-7909 {}}} CYCLES {}}
+set a(0-7907) {NAME ACC1-1:slc(acc.idiv)#11 TYPE READSLICE PAR 0-7009 XREFS 47616 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5613370249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7908 {}}} CYCLES {}}
+set a(0-7908) {NAME ACC1-1:exs#5 TYPE SIGNEXTEND PAR 0-7009 XREFS 47617 LOC {1 0.14655495 1 0.48184877499999995 1 0.48184877499999995 1 0.5613370249999999} PREDS {{259 0 0-7907 {}}} SUCCS {{259 0 0-7909 {}}} CYCLES {}}
+set a(0-7909) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#672 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47618 LOC {1 0.14655495 1 0.48184877499999995 1 0.48184877499999995 1 0.5226317850894752 1 0.6021200350894752} PREDS {{258 0 0-7906 {}} {259 0 0-7908 {}}} SUCCS {{258 0 0-7918 {}}} CYCLES {}}
+set a(0-7910) {NAME ACC1-1:slc(acc.idiv)#1 TYPE READSLICE PAR 0-7009 XREFS 47619 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5545639} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7911 {}}} CYCLES {}}
+set a(0-7911) {NAME ACC1-1:exs#951 TYPE SIGNEXTEND PAR 0-7009 XREFS 47620 LOC {1 0.14655495 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{259 0 0-7910 {}}} SUCCS {{259 0 0-7912 {}}} CYCLES {}}
+set a(0-7912) {NAME ACC1:conc#1431 TYPE CONCATENATE PAR 0-7009 XREFS 47621 LOC {1 0.14655495 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{259 0 0-7911 {}}} SUCCS {{258 0 0-7916 {}}} CYCLES {}}
+set a(0-7913) {NAME ACC1-1:slc(acc.idiv)#3 TYPE READSLICE PAR 0-7009 XREFS 47622 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5545639} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7914 {}}} CYCLES {}}
+set a(0-7914) {NAME ACC1-1:exs#1 TYPE SIGNEXTEND PAR 0-7009 XREFS 47623 LOC {1 0.14655495 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{259 0 0-7913 {}}} SUCCS {{259 0 0-7915 {}}} CYCLES {}}
+set a(0-7915) {NAME ACC1:conc#1432 TYPE CONCATENATE PAR 0-7009 XREFS 47624 LOC {1 0.3836787 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{258 0 0-7098 {}} {259 0 0-7914 {}}} SUCCS {{259 0 0-7916 {}}} CYCLES {}}
+set a(0-7916) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#671 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47625 LOC {1 0.3836787 1 0.47507564999999996 1 0.47507564999999996 1 0.5226317770708271 1 0.6021200270708271} PREDS {{258 0 0-7912 {}} {259 0 0-7915 {}}} SUCCS {{259 0 0-7917 {}}} CYCLES {}}
+set a(0-7917) {NAME ACC1:slc#154 TYPE READSLICE PAR 0-7009 XREFS 47626 LOC {1 0.43123487499999996 1 0.5226318249999999 1 0.5226318249999999 1 0.602120075} PREDS {{259 0 0-7916 {}}} SUCCS {{259 0 0-7918 {}}} CYCLES {}}
+set a(0-7918) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#677 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47627 LOC {1 0.43123487499999996 1 0.5226318249999999 1 0.5226318249999999 1 0.5701879520708271 1 0.6496762020708271} PREDS {{258 0 0-7909 {}} {259 0 0-7917 {}}} SUCCS {{259 0 0-7919 {}}} CYCLES {}}
+set a(0-7919) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#681 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-7009 XREFS 47628 LOC {1 0.47879105 1 0.570188 1 0.570188 1 0.6084774594969361 1 0.687965709496936} PREDS {{258 0 0-7904 {}} {259 0 0-7918 {}}} SUCCS {{259 0 0-7920 {}}} CYCLES {}}
+set a(0-7920) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 6 NAME ACC1:acc#684 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-7009 XREFS 47629 LOC {1 0.51708055 1 0.6084775 1 0.6084775 1 0.656356562932968 1 0.7358448129329679} PREDS {{258 0 0-7900 {}} {259 0 0-7919 {}}} SUCCS {{259 0 0-7921 {}}} CYCLES {}}
+set a(0-7921) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#687 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-7009 XREFS 47630 LOC {1 0.564959675 1 0.6563566249999999 1 0.6563566249999999 1 0.7087410777684257 1 0.7882293277684257} PREDS {{258 0 0-7895 {}} {259 0 0-7920 {}}} SUCCS {{259 0 0-7922 {}}} CYCLES {}}
+set a(0-7922) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,12) AREA_SCORE 11.00 QUANTITY 4 NAME ACC1:acc#690 TYPE ACCU DELAY {0.98 ns} LIBRARY_DELAY {0.98 ns} PAR 0-7009 XREFS 47631 LOC {1 0.684482975 1 0.708741125 1 0.708741125 1 0.7697701033364113 1 0.8492583533364113} PREDS {{258 0 0-7855 {}} {259 0 0-7921 {}}} SUCCS {{258 0 0-7934 {}}} CYCLES {}}
+set a(0-7923) {NAME ACC1-1:slc(acc.psp)#62 TYPE READSLICE PAR 0-7009 XREFS 47632 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7925 {}}} CYCLES {}}
+set a(0-7924) {NAME ACC1-1:slc(acc.psp)#49 TYPE READSLICE PAR 0-7009 XREFS 47633 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7925 {}}} CYCLES {}}
+set a(0-7925) {NAME ACC1-1:conc#555 TYPE CONCATENATE PAR 0-7009 XREFS 47634 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7679191249999999} PREDS {{258 0 0-7923 {}} {259 0 0-7924 {}}} SUCCS {{258 0 0-7933 {}}} CYCLES {}}
+set a(0-7926) {NAME ACC1-1:slc(acc.psp)#66 TYPE READSLICE PAR 0-7009 XREFS 47635 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7932 {}}} CYCLES {}}
+set a(0-7927) {NAME ACC1-1:slc(acc.psp)#67 TYPE READSLICE PAR 0-7009 XREFS 47636 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7932 {}}} CYCLES {}}
+set a(0-7928) {NAME ACC1-1:slc(acc.psp)#68 TYPE READSLICE PAR 0-7009 XREFS 47637 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7932 {}}} CYCLES {}}
+set a(0-7929) {NAME ACC1-1:slc(acc.psp)#51 TYPE READSLICE PAR 0-7009 XREFS 47638 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-7932 {}}} CYCLES {}}
+set a(0-7930) {NAME ACC1-1:slc(acc.idiv)#27 TYPE READSLICE PAR 0-7009 XREFS 47639 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-7931 {}}} CYCLES {}}
+set a(0-7931) {NAME ACC1-1:exs#13 TYPE SIGNEXTEND PAR 0-7009 XREFS 47640 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7679191249999999} PREDS {{259 0 0-7930 {}}} SUCCS {{259 0 0-7932 {}}} CYCLES {}}
+set a(0-7932) {NAME ACC1-1:conc#561 TYPE CONCATENATE PAR 0-7009 XREFS 47641 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7679191249999999} PREDS {{258 0 0-7929 {}} {258 0 0-7928 {}} {258 0 0-7927 {}} {258 0 0-7926 {}} {259 0 0-7931 {}}} SUCCS {{259 0 0-7933 {}}} CYCLES {}}
+set a(0-7933) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,11) AREA_SCORE 11.24 QUANTITY 3 NAME ACC1:acc#689 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-7009 XREFS 47642 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7697701033364113 1 0.8492583533364112} PREDS {{258 0 0-7925 {}} {259 0 0-7932 {}}} SUCCS {{259 0 0-7934 {}}} CYCLES {}}
+set a(0-7934) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-1:acc#2 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 47643 LOC {1 0.745512 1 0.7697701499999999 1 0.7697701499999999 1 0.8451409063734283 1 0.9246291563734284} PREDS {{258 0 0-7922 {}} {259 0 0-7933 {}}} SUCCS {{258 0 0-8082 {}}} CYCLES {}}
+set a(0-7935) {NAME ACC1-1:slc(acc#20.psp)#57 TYPE READSLICE PAR 0-7009 XREFS 47644 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-7940 {}}} CYCLES {}}
+set a(0-7936) {NAME ACC1-1:slc(acc#20.psp)#58 TYPE READSLICE PAR 0-7009 XREFS 47645 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-7940 {}}} CYCLES {}}
+set a(0-7937) {NAME ACC1-1:slc(acc#20.psp)#59 TYPE READSLICE PAR 0-7009 XREFS 47646 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-7940 {}}} CYCLES {}}
+set a(0-7938) {NAME ACC1-1:slc(acc#20.psp)#60 TYPE READSLICE PAR 0-7009 XREFS 47647 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-7940 {}}} CYCLES {}}
+set a(0-7939) {NAME ACC1-1:slc(acc#20.psp)#48 TYPE READSLICE PAR 0-7009 XREFS 47648 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7940 {}}} CYCLES {}}
+set a(0-7940) {NAME ACC1-1:conc#590 TYPE CONCATENATE PAR 0-7009 XREFS 47649 LOC {1 0.14655495 1 0.6519825499999999 1 0.6519825499999999 1 0.7314708} PREDS {{258 0 0-7938 {}} {258 0 0-7937 {}} {258 0 0-7936 {}} {258 0 0-7935 {}} {259 0 0-7939 {}}} SUCCS {{258 0 0-7997 {}}} CYCLES {}}
+set a(0-7941) {NAME ACC1-1:slc(acc#20.psp)#63 TYPE READSLICE PAR 0-7009 XREFS 47650 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-7946 {}}} CYCLES {}}
+set a(0-7942) {NAME ACC1-1:slc(acc#20.psp)#64 TYPE READSLICE PAR 0-7009 XREFS 47651 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-7946 {}}} CYCLES {}}
+set a(0-7943) {NAME ACC1-1:slc(acc#20.psp)#50 TYPE READSLICE PAR 0-7009 XREFS 47652 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-7946 {}}} CYCLES {}}
+set a(0-7944) {NAME ACC1-1:slc(acc#20.psp)#65 TYPE READSLICE PAR 0-7009 XREFS 47653 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7945 {}}} CYCLES {}}
+set a(0-7945) {NAME ACC1-1:exs#1039 TYPE SIGNEXTEND PAR 0-7009 XREFS 47654 LOC {1 0.14655495 1 0.59959805 1 0.59959805 1 0.6790862999999999} PREDS {{259 0 0-7944 {}}} SUCCS {{259 0 0-7946 {}}} CYCLES {}}
+set a(0-7946) {NAME ACC1-1:conc#595 TYPE CONCATENATE PAR 0-7009 XREFS 47655 LOC {1 0.14655495 1 0.59959805 1 0.59959805 1 0.6790862999999999} PREDS {{258 0 0-7943 {}} {258 0 0-7942 {}} {258 0 0-7941 {}} {259 0 0-7945 {}}} SUCCS {{258 0 0-7996 {}}} CYCLES {}}
+set a(0-7947) {NAME ACC1-1:slc(acc#20.psp)#36 TYPE READSLICE PAR 0-7009 XREFS 47656 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6358845249999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-7951 {}}} CYCLES {}}
+set a(0-7948) {NAME ACC1-1:slc(acc#20.psp)#37 TYPE READSLICE PAR 0-7009 XREFS 47657 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6358845249999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-7951 {}}} CYCLES {}}
+set a(0-7949) {NAME ACC1-1:slc(acc.idiv#4)#29 TYPE READSLICE PAR 0-7009 XREFS 47658 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6358845249999999} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7950 {}}} CYCLES {}}
+set a(0-7950) {NAME ACC1-1:exs#86 TYPE SIGNEXTEND PAR 0-7009 XREFS 47659 LOC {1 0.14655495 1 0.556396275 1 0.556396275 1 0.6358845249999999} PREDS {{259 0 0-7949 {}}} SUCCS {{259 0 0-7951 {}}} CYCLES {}}
+set a(0-7951) {NAME ACC1-1:conc#599 TYPE CONCATENATE PAR 0-7009 XREFS 47660 LOC {1 0.14655495 1 0.556396275 1 0.556396275 1 0.6358845249999999} PREDS {{258 0 0-7948 {}} {258 0 0-7947 {}} {259 0 0-7950 {}}} SUCCS {{258 0 0-7995 {}}} CYCLES {}}
+set a(0-7952) {NAME ACC1-1:slc(acc.idiv#4)#5 TYPE READSLICE PAR 0-7009 XREFS 47661 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7953 {}}} CYCLES {}}
+set a(0-7953) {NAME ACC1-1:exs#74 TYPE SIGNEXTEND PAR 0-7009 XREFS 47662 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7952 {}}} SUCCS {{259 0 0-7954 {}}} CYCLES {}}
+set a(0-7954) {NAME ACC1:conc#1444 TYPE CONCATENATE PAR 0-7009 XREFS 47663 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7953 {}}} SUCCS {{258 0 0-7962 {}}} CYCLES {}}
+set a(0-7955) {NAME ACC1-1:slc(acc.idiv#4)#7 TYPE READSLICE PAR 0-7009 XREFS 47664 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7956 {}}} CYCLES {}}
+set a(0-7956) {NAME ACC1-1:exs#75 TYPE SIGNEXTEND PAR 0-7009 XREFS 47665 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7955 {}}} SUCCS {{258 0 0-7961 {}}} CYCLES {}}
+set a(0-7957) {NAME ACC1-1:slc(acc.imod#19) TYPE READSLICE PAR 0-7009 XREFS 47666 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-7247 {}}} SUCCS {{258 0 0-7960 {}}} CYCLES {}}
+set a(0-7958) {NAME ACC1-1:slc(acc.idiv#4)#44 TYPE READSLICE PAR 0-7009 XREFS 47667 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7959 {}}} CYCLES {}}
+set a(0-7959) {NAME ACC1-1:not#155 TYPE NOT PAR 0-7009 XREFS 47668 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7958 {}}} SUCCS {{259 0 0-7960 {}}} CYCLES {}}
+set a(0-7960) {NAME ACC1-1:nand#4 TYPE NAND PAR 0-7009 XREFS 47669 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-7957 {}} {259 0 0-7959 {}}} SUCCS {{259 0 0-7961 {}}} CYCLES {}}
+set a(0-7961) {NAME ACC1:conc#1445 TYPE CONCATENATE PAR 0-7009 XREFS 47670 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-7956 {}} {259 0 0-7960 {}}} SUCCS {{259 0 0-7962 {}}} CYCLES {}}
+set a(0-7962) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#696 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47671 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-7954 {}} {259 0 0-7961 {}}} SUCCS {{259 0 0-7963 {}}} CYCLES {}}
+set a(0-7963) {NAME ACC1:slc#160 TYPE READSLICE PAR 0-7009 XREFS 47672 LOC {1 0.43123487499999996 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-7962 {}}} SUCCS {{258 0 0-7974 {}}} CYCLES {}}
+set a(0-7964) {NAME ACC1-1:slc(acc.idiv#4)#15 TYPE READSLICE PAR 0-7009 XREFS 47673 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7965 {}}} CYCLES {}}
+set a(0-7965) {NAME ACC1-1:exs#79 TYPE SIGNEXTEND PAR 0-7009 XREFS 47674 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7964 {}}} SUCCS {{259 0 0-7966 {}}} CYCLES {}}
+set a(0-7966) {NAME ACC1:conc#1442 TYPE CONCATENATE PAR 0-7009 XREFS 47675 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7965 {}}} SUCCS {{258 0 0-7972 {}}} CYCLES {}}
+set a(0-7967) {NAME ACC1-1:slc(acc.idiv#4)#17 TYPE READSLICE PAR 0-7009 XREFS 47676 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7968 {}}} CYCLES {}}
+set a(0-7968) {NAME ACC1-1:exs#80 TYPE SIGNEXTEND PAR 0-7009 XREFS 47677 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7967 {}}} SUCCS {{258 0 0-7971 {}}} CYCLES {}}
+set a(0-7969) {NAME ACC1-1:slc(acc.imod#18)#12 TYPE READSLICE PAR 0-7009 XREFS 47678 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.4874251} PREDS {{258 0 0-7238 {}}} SUCCS {{259 0 0-7970 {}}} CYCLES {}}
+set a(0-7970) {NAME ACC1-1:not#300 TYPE NOT PAR 0-7009 XREFS 47679 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7969 {}}} SUCCS {{259 0 0-7971 {}}} CYCLES {}}
+set a(0-7971) {NAME ACC1:conc#1443 TYPE CONCATENATE PAR 0-7009 XREFS 47680 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-7968 {}} {259 0 0-7970 {}}} SUCCS {{259 0 0-7972 {}}} CYCLES {}}
+set a(0-7972) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#695 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47681 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-7966 {}} {259 0 0-7971 {}}} SUCCS {{259 0 0-7973 {}}} CYCLES {}}
+set a(0-7973) {NAME ACC1:slc#159 TYPE READSLICE PAR 0-7009 XREFS 47682 LOC {1 0.40398894999999996 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-7972 {}}} SUCCS {{259 0 0-7974 {}}} CYCLES {}}
+set a(0-7974) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#702 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47683 LOC {1 0.43123487499999996 1 0.455493025 1 0.455493025 1 0.5030491520708271 1 0.582537402070827} PREDS {{258 0 0-7963 {}} {259 0 0-7973 {}}} SUCCS {{258 0 0-7994 {}}} CYCLES {}}
+set a(0-7975) {NAME ACC1-1:slc(acc.idiv#4)#13 TYPE READSLICE PAR 0-7009 XREFS 47684 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7976 {}}} CYCLES {}}
+set a(0-7976) {NAME ACC1-1:exs#78 TYPE SIGNEXTEND PAR 0-7009 XREFS 47685 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7975 {}}} SUCCS {{259 0 0-7977 {}}} CYCLES {}}
+set a(0-7977) {NAME ACC1:conc#1440 TYPE CONCATENATE PAR 0-7009 XREFS 47686 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7976 {}}} SUCCS {{258 0 0-7982 {}}} CYCLES {}}
+set a(0-7978) {NAME ACC1-1:slc(acc.idiv#4)#23 TYPE READSLICE PAR 0-7009 XREFS 47687 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7979 {}}} CYCLES {}}
+set a(0-7979) {NAME ACC1-1:exs#83 TYPE SIGNEXTEND PAR 0-7009 XREFS 47688 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7978 {}}} SUCCS {{258 0 0-7981 {}}} CYCLES {}}
+set a(0-7980) {NAME ACC1-1:slc(acc.imod#18)#11 TYPE READSLICE PAR 0-7009 XREFS 47689 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.4874251} PREDS {{258 0 0-7238 {}}} SUCCS {{259 0 0-7981 {}}} CYCLES {}}
+set a(0-7981) {NAME ACC1:conc#1441 TYPE CONCATENATE PAR 0-7009 XREFS 47690 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-7979 {}} {259 0 0-7980 {}}} SUCCS {{259 0 0-7982 {}}} CYCLES {}}
+set a(0-7982) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#694 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47691 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-7977 {}} {259 0 0-7981 {}}} SUCCS {{259 0 0-7983 {}}} CYCLES {}}
+set a(0-7983) {NAME ACC1:slc#158 TYPE READSLICE PAR 0-7009 XREFS 47692 LOC {1 0.40398894999999996 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-7982 {}}} SUCCS {{258 0 0-7993 {}}} CYCLES {}}
+set a(0-7984) {NAME ACC1-1:slc(acc.idiv#4)#19 TYPE READSLICE PAR 0-7009 XREFS 47693 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7985 {}}} CYCLES {}}
+set a(0-7985) {NAME ACC1-1:exs#81 TYPE SIGNEXTEND PAR 0-7009 XREFS 47694 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7984 {}}} SUCCS {{259 0 0-7986 {}}} CYCLES {}}
+set a(0-7986) {NAME ACC1:conc#1438 TYPE CONCATENATE PAR 0-7009 XREFS 47695 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7985 {}}} SUCCS {{258 0 0-7991 {}}} CYCLES {}}
+set a(0-7987) {NAME ACC1-1:slc(acc.idiv#4)#21 TYPE READSLICE PAR 0-7009 XREFS 47696 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7988 {}}} CYCLES {}}
+set a(0-7988) {NAME ACC1-1:exs#82 TYPE SIGNEXTEND PAR 0-7009 XREFS 47697 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-7987 {}}} SUCCS {{258 0 0-7990 {}}} CYCLES {}}
+set a(0-7989) {NAME ACC1-1:slc(ACC1:acc#217.psp)#9 TYPE READSLICE PAR 0-7009 XREFS 47698 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.4874251} PREDS {{258 0 0-7220 {}}} SUCCS {{259 0 0-7990 {}}} CYCLES {}}
+set a(0-7990) {NAME ACC1:conc#1439 TYPE CONCATENATE PAR 0-7009 XREFS 47699 LOC {1 0.267931 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-7988 {}} {259 0 0-7989 {}}} SUCCS {{259 0 0-7991 {}}} CYCLES {}}
+set a(0-7991) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#693 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47700 LOC {1 0.267931 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-7986 {}} {259 0 0-7990 {}}} SUCCS {{259 0 0-7992 {}}} CYCLES {}}
+set a(0-7992) {NAME ACC1:slc#157 TYPE READSLICE PAR 0-7009 XREFS 47701 LOC {1 0.315487175 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-7991 {}}} SUCCS {{259 0 0-7993 {}}} CYCLES {}}
+set a(0-7993) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#701 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47702 LOC {1 0.40398894999999996 1 0.455493025 1 0.455493025 1 0.5030491520708271 1 0.582537402070827} PREDS {{258 0 0-7983 {}} {259 0 0-7992 {}}} SUCCS {{259 0 0-7994 {}}} CYCLES {}}
+set a(0-7994) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#706 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 47703 LOC {1 0.47879105 1 0.5030492 1 0.5030492 1 0.5563962201789505 1 0.6358844701789506} PREDS {{258 0 0-7974 {}} {259 0 0-7993 {}}} SUCCS {{259 0 0-7995 {}}} CYCLES {}}
+set a(0-7995) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 5 NAME ACC1:acc#709 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 47704 LOC {1 0.532138125 1 0.556396275 1 0.556396275 1 0.5995979984103024 1 0.6790862484103023} PREDS {{258 0 0-7951 {}} {259 0 0-7994 {}}} SUCCS {{259 0 0-7996 {}}} CYCLES {}}
+set a(0-7996) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#712 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-7009 XREFS 47705 LOC {1 0.5753399 1 0.59959805 1 0.59959805 1 0.6519825027684257 1 0.7314707527684257} PREDS {{258 0 0-7946 {}} {259 0 0-7995 {}}} SUCCS {{259 0 0-7997 {}}} CYCLES {}}
+set a(0-7997) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,1,11) AREA_SCORE 10.00 QUANTITY 5 NAME ACC1:acc#714 TYPE ACCU DELAY {0.91 ns} LIBRARY_DELAY {0.91 ns} PAR 0-7009 XREFS 47706 LOC {1 0.6277244 1 0.6519825499999999 1 0.6519825499999999 1 0.7087410628916543 1 0.7882293128916543} PREDS {{258 0 0-7940 {}} {259 0 0-7996 {}}} SUCCS {{258 0 0-8069 {}}} CYCLES {}}
+set a(0-7998) {NAME ACC1-1:slc(acc#20.psp)#29 TYPE READSLICE PAR 0-7009 XREFS 47707 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5312430499999999} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-7999 {}}} CYCLES {}}
+set a(0-7999) {NAME ACC1:conc#1433 TYPE CONCATENATE PAR 0-7009 XREFS 47708 LOC {1 0.14655495 1 0.45175479999999996 1 0.45175479999999996 1 0.5312430499999999} PREDS {{259 0 0-7998 {}}} SUCCS {{259 0 0-8000 {}}} CYCLES {}}
+set a(0-8000) {NAME ACC1:conc#1434 TYPE CONCATENATE PAR 0-7009 XREFS 47709 LOC {1 0.14655495 1 0.45175479999999996 1 0.45175479999999996 1 0.5312430499999999} PREDS {{259 0 0-7999 {}}} SUCCS {{258 0 0-8004 {}}} CYCLES {}}
+set a(0-8001) {NAME ACC1-1:slc(ACC1:acc#217.psp)#10 TYPE READSLICE PAR 0-7009 XREFS 47710 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.5312430499999999} PREDS {{258 0 0-7220 {}}} SUCCS {{258 0 0-8003 {}}} CYCLES {}}
+set a(0-8002) {NAME ACC1-1:slc(acc#20.psp)#30 TYPE READSLICE PAR 0-7009 XREFS 47711 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5312430499999999} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8003 {}}} CYCLES {}}
+set a(0-8003) {NAME ACC1:conc#1435 TYPE CONCATENATE PAR 0-7009 XREFS 47712 LOC {1 0.267931 1 0.45175479999999996 1 0.45175479999999996 1 0.5312430499999999} PREDS {{258 0 0-8001 {}} {259 0 0-8002 {}}} SUCCS {{259 0 0-8004 {}}} CYCLES {}}
+set a(0-8004) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 4 NAME ACC1:acc#691 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-7009 XREFS 47713 LOC {1 0.267931 1 0.45175479999999996 1 0.45175479999999996 1 0.4893753770241716 1 0.5688636270241716} PREDS {{258 0 0-8000 {}} {259 0 0-8003 {}}} SUCCS {{259 0 0-8005 {}}} CYCLES {}}
+set a(0-8005) {NAME ACC1:slc#155 TYPE READSLICE PAR 0-7009 XREFS 47714 LOC {1 0.305551625 1 0.489375425 1 0.489375425 1 0.568863675} PREDS {{259 0 0-8004 {}}} SUCCS {{258 0 0-8007 {}}} CYCLES {}}
+set a(0-8006) {NAME ACC1-1:slc(ACC1:acc#223.psp)#2 TYPE READSLICE PAR 0-7009 XREFS 47715 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.568863675} PREDS {{258 0 0-7231 {}}} SUCCS {{259 0 0-8007 {}}} CYCLES {}}
+set a(0-8007) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 4 NAME ACC1:acc#700 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-7009 XREFS 47716 LOC {1 0.32918685 1 0.489375425 1 0.489375425 1 0.5269960020241716 1 0.6064842520241717} PREDS {{258 0 0-8005 {}} {259 0 0-8006 {}}} SUCCS {{258 0 0-8019 {}}} CYCLES {}}
+set a(0-8008) {NAME ACC1-1:slc(acc#20.psp)#31 TYPE READSLICE PAR 0-7009 XREFS 47717 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.579238375} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8010 {}}} CYCLES {}}
+set a(0-8009) {NAME ACC1-1:slc(acc#20.psp)#32 TYPE READSLICE PAR 0-7009 XREFS 47718 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.579238375} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8010 {}}} CYCLES {}}
+set a(0-8010) {NAME ACC1-1:conc#592 TYPE CONCATENATE PAR 0-7009 XREFS 47719 LOC {1 0.14655495 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{258 0 0-8008 {}} {259 0 0-8009 {}}} SUCCS {{259 0 0-8011 {}}} CYCLES {}}
+set a(0-8011) {NAME ACC1:conc#1436 TYPE CONCATENATE PAR 0-7009 XREFS 47720 LOC {1 0.14655495 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{259 0 0-8010 {}}} SUCCS {{258 0 0-8017 {}}} CYCLES {}}
+set a(0-8012) {NAME ACC1-1:slc(ACC1:acc#217.psp)#11 TYPE READSLICE PAR 0-7009 XREFS 47721 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.579238375} PREDS {{258 0 0-7220 {}}} SUCCS {{258 0 0-8014 {}}} CYCLES {}}
+set a(0-8013) {NAME ACC1-1:slc(acc#20.psp)#33 TYPE READSLICE PAR 0-7009 XREFS 47722 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.579238375} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8014 {}}} CYCLES {}}
+set a(0-8014) {NAME ACC1-1:conc#593 TYPE CONCATENATE PAR 0-7009 XREFS 47723 LOC {1 0.267931 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{258 0 0-8012 {}} {259 0 0-8013 {}}} SUCCS {{258 0 0-8016 {}}} CYCLES {}}
+set a(0-8015) {NAME ACC1-1:slc(ACC1:acc#217.psp)#8 TYPE READSLICE PAR 0-7009 XREFS 47724 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.579238375} PREDS {{258 0 0-7220 {}}} SUCCS {{259 0 0-8016 {}}} CYCLES {}}
+set a(0-8016) {NAME ACC1:conc#1437 TYPE CONCATENATE PAR 0-7009 XREFS 47725 LOC {1 0.267931 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{258 0 0-8014 {}} {259 0 0-8015 {}}} SUCCS {{259 0 0-8017 {}}} CYCLES {}}
+set a(0-8017) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#692 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47726 LOC {1 0.267931 1 0.499750125 1 0.499750125 1 0.5269960020708272 1 0.6064842520708271} PREDS {{258 0 0-8011 {}} {259 0 0-8016 {}}} SUCCS {{259 0 0-8018 {}}} CYCLES {}}
+set a(0-8018) {NAME ACC1:slc#156 TYPE READSLICE PAR 0-7009 XREFS 47727 LOC {1 0.295176925 1 0.5269960499999999 1 0.5269960499999999 1 0.6064843} PREDS {{259 0 0-8017 {}}} SUCCS {{259 0 0-8019 {}}} CYCLES {}}
+set a(0-8019) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#705 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 47728 LOC {1 0.366807475 1 0.5269960499999999 1 0.5269960499999999 1 0.5701879451789504 1 0.6496761951789505} PREDS {{258 0 0-8007 {}} {259 0 0-8018 {}}} SUCCS {{258 0 0-8031 {}}} CYCLES {}}
+set a(0-8020) {NAME ACC1-1:slc(acc#20.psp)#34 TYPE READSLICE PAR 0-7009 XREFS 47729 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.616639425} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8024 {}}} CYCLES {}}
+set a(0-8021) {NAME ACC1-1:slc(acc#20.psp)#35 TYPE READSLICE PAR 0-7009 XREFS 47730 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.616639425} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8024 {}}} CYCLES {}}
+set a(0-8022) {NAME ACC1-1:slc(acc.idiv#4)#31 TYPE READSLICE PAR 0-7009 XREFS 47731 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.616639425} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8023 {}}} CYCLES {}}
+set a(0-8023) {NAME ACC1-1:exs#87 TYPE SIGNEXTEND PAR 0-7009 XREFS 47732 LOC {1 0.14655495 1 0.537151175 1 0.537151175 1 0.616639425} PREDS {{259 0 0-8022 {}}} SUCCS {{259 0 0-8024 {}}} CYCLES {}}
+set a(0-8024) {NAME ACC1-1:conc#594 TYPE CONCATENATE PAR 0-7009 XREFS 47733 LOC {1 0.14655495 1 0.537151175 1 0.537151175 1 0.616639425} PREDS {{258 0 0-8021 {}} {258 0 0-8020 {}} {259 0 0-8023 {}}} SUCCS {{258 0 0-8030 {}}} CYCLES {}}
+set a(0-8025) {NAME ACC1-1:slc(acc.idiv#4)#33 TYPE READSLICE PAR 0-7009 XREFS 47734 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.575856375} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8026 {}}} CYCLES {}}
+set a(0-8026) {NAME ACC1-1:exs#88 TYPE SIGNEXTEND PAR 0-7009 XREFS 47735 LOC {1 0.14655495 1 0.496368125 1 0.496368125 1 0.575856375} PREDS {{259 0 0-8025 {}}} SUCCS {{258 0 0-8029 {}}} CYCLES {}}
+set a(0-8027) {NAME ACC1-1:slc(acc.idiv#4)#35 TYPE READSLICE PAR 0-7009 XREFS 47736 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.575856375} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8028 {}}} CYCLES {}}
+set a(0-8028) {NAME ACC1-1:exs#89 TYPE SIGNEXTEND PAR 0-7009 XREFS 47737 LOC {1 0.14655495 1 0.496368125 1 0.496368125 1 0.575856375} PREDS {{259 0 0-8027 {}}} SUCCS {{259 0 0-8029 {}}} CYCLES {}}
+set a(0-8029) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#699 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47738 LOC {1 0.14655495 1 0.496368125 1 0.496368125 1 0.5371511350894752 1 0.6166393850894752} PREDS {{258 0 0-8026 {}} {259 0 0-8028 {}}} SUCCS {{259 0 0-8030 {}}} CYCLES {}}
+set a(0-8030) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#704 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 47739 LOC {1 0.187338 1 0.537151175 1 0.537151175 1 0.5701879451789504 1 0.6496761951789505} PREDS {{258 0 0-8024 {}} {259 0 0-8029 {}}} SUCCS {{259 0 0-8031 {}}} CYCLES {}}
+set a(0-8031) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#708 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-7009 XREFS 47740 LOC {1 0.409999425 1 0.570188 1 0.570188 1 0.6084774594969361 1 0.687965709496936} PREDS {{258 0 0-8019 {}} {259 0 0-8030 {}}} SUCCS {{258 0 0-8037 {}}} CYCLES {}}
+set a(0-8032) {NAME ACC1-1:slc(acc#20.psp)#54 TYPE READSLICE PAR 0-7009 XREFS 47741 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8036 {}}} CYCLES {}}
+set a(0-8033) {NAME ACC1-1:slc(acc#20.psp)#55 TYPE READSLICE PAR 0-7009 XREFS 47742 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8036 {}}} CYCLES {}}
+set a(0-8034) {NAME ACC1-1:slc(acc#20.psp)#56 TYPE READSLICE PAR 0-7009 XREFS 47743 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8036 {}}} CYCLES {}}
+set a(0-8035) {NAME ACC1-1:slc(acc#20.psp)#47 TYPE READSLICE PAR 0-7009 XREFS 47744 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8036 {}}} CYCLES {}}
+set a(0-8036) {NAME ACC1-1:conc#589 TYPE CONCATENATE PAR 0-7009 XREFS 47745 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{258 0 0-8034 {}} {258 0 0-8033 {}} {258 0 0-8032 {}} {259 0 0-8035 {}}} SUCCS {{259 0 0-8037 {}}} CYCLES {}}
+set a(0-8037) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 6 NAME ACC1:acc#711 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-7009 XREFS 47746 LOC {1 0.448288925 1 0.6084775 1 0.6084775 1 0.656356562932968 1 0.7358448129329679} PREDS {{258 0 0-8031 {}} {259 0 0-8036 {}}} SUCCS {{258 0 0-8068 {}}} CYCLES {}}
+set a(0-8038) {NAME ACC1-1:slc(acc#20.psp)#17 TYPE READSLICE PAR 0-7009 XREFS 47747 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8041 {}}} CYCLES {}}
+set a(0-8039) {NAME ACC1-1:slc(acc.idiv#4)#25 TYPE READSLICE PAR 0-7009 XREFS 47748 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8040 {}}} CYCLES {}}
+set a(0-8040) {NAME ACC1-1:exs#84 TYPE SIGNEXTEND PAR 0-7009 XREFS 47749 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{259 0 0-8039 {}}} SUCCS {{259 0 0-8041 {}}} CYCLES {}}
+set a(0-8041) {NAME ACC1-1:conc#538 TYPE CONCATENATE PAR 0-7009 XREFS 47750 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{258 0 0-8038 {}} {259 0 0-8040 {}}} SUCCS {{259 0 0-8042 {}}} CYCLES {}}
+set a(0-8042) {NAME ACC1-1:exs#1040 TYPE SIGNEXTEND PAR 0-7009 XREFS 47751 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{259 0 0-8041 {}}} SUCCS {{258 0 0-8067 {}}} CYCLES {}}
+set a(0-8043) {NAME ACC1-1:slc(acc#20.psp)#52 TYPE READSLICE PAR 0-7009 XREFS 47752 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.64967625} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8046 {}}} CYCLES {}}
+set a(0-8044) {NAME ACC1-1:slc(acc#20.psp)#53 TYPE READSLICE PAR 0-7009 XREFS 47753 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.64967625} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8046 {}}} CYCLES {}}
+set a(0-8045) {NAME ACC1-1:slc(acc#20.psp)#46 TYPE READSLICE PAR 0-7009 XREFS 47754 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.64967625} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8046 {}}} CYCLES {}}
+set a(0-8046) {NAME ACC1-1:conc#588 TYPE CONCATENATE PAR 0-7009 XREFS 47755 LOC {1 0.14655495 1 0.570188 1 0.570188 1 0.64967625} PREDS {{258 0 0-8044 {}} {258 0 0-8043 {}} {259 0 0-8045 {}}} SUCCS {{258 0 0-8066 {}}} CYCLES {}}
+set a(0-8047) {NAME ACC1-1:slc(acc.idiv#4)#9 TYPE READSLICE PAR 0-7009 XREFS 47756 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5613370249999999} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8048 {}}} CYCLES {}}
+set a(0-8048) {NAME ACC1-1:exs#76 TYPE SIGNEXTEND PAR 0-7009 XREFS 47757 LOC {1 0.14655495 1 0.48184877499999995 1 0.48184877499999995 1 0.5613370249999999} PREDS {{259 0 0-8047 {}}} SUCCS {{258 0 0-8051 {}}} CYCLES {}}
+set a(0-8049) {NAME ACC1-1:slc(acc.idiv#4)#11 TYPE READSLICE PAR 0-7009 XREFS 47758 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5613370249999999} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8050 {}}} CYCLES {}}
+set a(0-8050) {NAME ACC1-1:exs#77 TYPE SIGNEXTEND PAR 0-7009 XREFS 47759 LOC {1 0.14655495 1 0.48184877499999995 1 0.48184877499999995 1 0.5613370249999999} PREDS {{259 0 0-8049 {}}} SUCCS {{259 0 0-8051 {}}} CYCLES {}}
+set a(0-8051) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#698 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 47760 LOC {1 0.14655495 1 0.48184877499999995 1 0.48184877499999995 1 0.5226317850894752 1 0.6021200350894752} PREDS {{258 0 0-8048 {}} {259 0 0-8050 {}}} SUCCS {{258 0 0-8065 {}}} CYCLES {}}
+set a(0-8052) {NAME ACC1-1:slc(acc.idiv#4)#1 TYPE READSLICE PAR 0-7009 XREFS 47761 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5545639} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8053 {}}} CYCLES {}}
+set a(0-8053) {NAME ACC1-1:exs#72 TYPE SIGNEXTEND PAR 0-7009 XREFS 47762 LOC {1 0.14655495 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{259 0 0-8052 {}}} SUCCS {{259 0 0-8054 {}}} CYCLES {}}
+set a(0-8054) {NAME ACC1:conc#1446 TYPE CONCATENATE PAR 0-7009 XREFS 47763 LOC {1 0.14655495 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{259 0 0-8053 {}}} SUCCS {{258 0 0-8063 {}}} CYCLES {}}
+set a(0-8055) {NAME ACC1-1:slc(acc.idiv#4)#3 TYPE READSLICE PAR 0-7009 XREFS 47764 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5545639} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8056 {}}} CYCLES {}}
+set a(0-8056) {NAME ACC1-1:exs#73 TYPE SIGNEXTEND PAR 0-7009 XREFS 47765 LOC {1 0.14655495 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{259 0 0-8055 {}}} SUCCS {{258 0 0-8062 {}}} CYCLES {}}
+set a(0-8057) {NAME ACC1-1:slc(acc.idiv#4)#45 TYPE READSLICE PAR 0-7009 XREFS 47766 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5545639} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8061 {}}} CYCLES {}}
+set a(0-8058) {NAME ACC1-1:slc(acc.imod#19)#1 TYPE READSLICE PAR 0-7009 XREFS 47767 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{258 0 0-7247 {}}} SUCCS {{259 0 0-8059 {}}} CYCLES {}}
+set a(0-8059) {NAME ACC1-1:not#156 TYPE NOT PAR 0-7009 XREFS 47768 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{259 0 0-8058 {}}} SUCCS {{258 0 0-8061 {}}} CYCLES {}}
+set a(0-8060) {NAME ACC1-1:slc(acc.imod#19)#2 TYPE READSLICE PAR 0-7009 XREFS 47769 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{258 0 0-7247 {}}} SUCCS {{259 0 0-8061 {}}} CYCLES {}}
+set a(0-8061) {NAME ACC1-1:and#9 TYPE AND PAR 0-7009 XREFS 47770 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{258 0 0-8059 {}} {258 0 0-8057 {}} {259 0 0-8060 {}}} SUCCS {{259 0 0-8062 {}}} CYCLES {}}
+set a(0-8062) {NAME ACC1:conc#1447 TYPE CONCATENATE PAR 0-7009 XREFS 47771 LOC {1 0.3836787 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{258 0 0-8056 {}} {259 0 0-8061 {}}} SUCCS {{259 0 0-8063 {}}} CYCLES {}}
+set a(0-8063) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#697 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47772 LOC {1 0.3836787 1 0.47507564999999996 1 0.47507564999999996 1 0.5226317770708271 1 0.6021200270708271} PREDS {{258 0 0-8054 {}} {259 0 0-8062 {}}} SUCCS {{259 0 0-8064 {}}} CYCLES {}}
+set a(0-8064) {NAME ACC1:slc#161 TYPE READSLICE PAR 0-7009 XREFS 47773 LOC {1 0.43123487499999996 1 0.5226318249999999 1 0.5226318249999999 1 0.602120075} PREDS {{259 0 0-8063 {}}} SUCCS {{259 0 0-8065 {}}} CYCLES {}}
+set a(0-8065) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#703 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47774 LOC {1 0.43123487499999996 1 0.5226318249999999 1 0.5226318249999999 1 0.5701879520708271 1 0.6496762020708271} PREDS {{258 0 0-8051 {}} {259 0 0-8064 {}}} SUCCS {{259 0 0-8066 {}}} CYCLES {}}
+set a(0-8066) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#707 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-7009 XREFS 47775 LOC {1 0.47879105 1 0.570188 1 0.570188 1 0.6084774594969361 1 0.687965709496936} PREDS {{258 0 0-8046 {}} {259 0 0-8065 {}}} SUCCS {{259 0 0-8067 {}}} CYCLES {}}
+set a(0-8067) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 6 NAME ACC1:acc#710 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-7009 XREFS 47776 LOC {1 0.51708055 1 0.6084775 1 0.6084775 1 0.656356562932968 1 0.7358448129329679} PREDS {{258 0 0-8042 {}} {259 0 0-8066 {}}} SUCCS {{259 0 0-8068 {}}} CYCLES {}}
+set a(0-8068) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#713 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-7009 XREFS 47777 LOC {1 0.564959675 1 0.6563566249999999 1 0.6563566249999999 1 0.7087410777684257 1 0.7882293277684257} PREDS {{258 0 0-8037 {}} {259 0 0-8067 {}}} SUCCS {{259 0 0-8069 {}}} CYCLES {}}
+set a(0-8069) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,12) AREA_SCORE 11.00 QUANTITY 4 NAME ACC1:acc#716 TYPE ACCU DELAY {0.98 ns} LIBRARY_DELAY {0.98 ns} PAR 0-7009 XREFS 47778 LOC {1 0.684482975 1 0.708741125 1 0.708741125 1 0.7697701033364113 1 0.8492583533364113} PREDS {{258 0 0-7997 {}} {259 0 0-8068 {}}} SUCCS {{258 0 0-8081 {}}} CYCLES {}}
+set a(0-8070) {NAME ACC1-1:slc(acc#20.psp)#62 TYPE READSLICE PAR 0-7009 XREFS 47779 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8072 {}}} CYCLES {}}
+set a(0-8071) {NAME ACC1-1:slc(acc#20.psp)#49 TYPE READSLICE PAR 0-7009 XREFS 47780 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8072 {}}} CYCLES {}}
+set a(0-8072) {NAME ACC1-1:conc#591 TYPE CONCATENATE PAR 0-7009 XREFS 47781 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7679191249999999} PREDS {{258 0 0-8070 {}} {259 0 0-8071 {}}} SUCCS {{258 0 0-8080 {}}} CYCLES {}}
+set a(0-8073) {NAME ACC1-1:slc(acc#20.psp)#66 TYPE READSLICE PAR 0-7009 XREFS 47782 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8079 {}}} CYCLES {}}
+set a(0-8074) {NAME ACC1-1:slc(acc#20.psp)#67 TYPE READSLICE PAR 0-7009 XREFS 47783 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8079 {}}} CYCLES {}}
+set a(0-8075) {NAME ACC1-1:slc(acc#20.psp)#68 TYPE READSLICE PAR 0-7009 XREFS 47784 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8079 {}}} CYCLES {}}
+set a(0-8076) {NAME ACC1-1:slc(acc#20.psp)#51 TYPE READSLICE PAR 0-7009 XREFS 47785 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7180 {}}} SUCCS {{258 0 0-8079 {}}} CYCLES {}}
+set a(0-8077) {NAME ACC1-1:slc(acc.idiv#4)#27 TYPE READSLICE PAR 0-7009 XREFS 47786 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-7180 {}}} SUCCS {{259 0 0-8078 {}}} CYCLES {}}
+set a(0-8078) {NAME ACC1-1:exs#85 TYPE SIGNEXTEND PAR 0-7009 XREFS 47787 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7679191249999999} PREDS {{259 0 0-8077 {}}} SUCCS {{259 0 0-8079 {}}} CYCLES {}}
+set a(0-8079) {NAME ACC1-1:conc#597 TYPE CONCATENATE PAR 0-7009 XREFS 47788 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7679191249999999} PREDS {{258 0 0-8076 {}} {258 0 0-8075 {}} {258 0 0-8074 {}} {258 0 0-8073 {}} {259 0 0-8078 {}}} SUCCS {{259 0 0-8080 {}}} CYCLES {}}
+set a(0-8080) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,11) AREA_SCORE 11.24 QUANTITY 3 NAME ACC1:acc#715 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-7009 XREFS 47789 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7697701033364113 1 0.8492583533364112} PREDS {{258 0 0-8072 {}} {259 0 0-8079 {}}} SUCCS {{259 0 0-8081 {}}} CYCLES {}}
+set a(0-8081) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-1:acc#27 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 47790 LOC {1 0.745512 1 0.7697701499999999 1 0.7697701499999999 1 0.8451409063734283 1 0.9246291563734284} PREDS {{258 0 0-8069 {}} {259 0 0-8080 {}}} SUCCS {{259 0 0-8082 {}}} CYCLES {}}
+set a(0-8082) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1:acc#653 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 47791 LOC {1 0.8208827999999999 1 0.84514095 1 0.84514095 1 0.9205117063734284 1 0.9999999563734283} PREDS {{258 0 0-7934 {}} {259 0 0-8081 {}}} SUCCS {{259 0 0-8083 {}}} CYCLES {}}
+set a(0-8083) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 4 NAME ACC1:acc#659 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-7009 XREFS 47792 LOC {1 0.8962536 1 0.92051175 1 0.92051175 1 0.9999999534997777 2 0.13630012849977768} PREDS {{258 0 0-7796 {}} {259 0 0-8082 {}}} SUCCS {{258 0 0-8208 {}}} CYCLES {}}
+set a(0-8084) {NAME ACC1:slc(ACC1:acc#224.psp#1)#26 TYPE READSLICE PAR 0-7009 XREFS 47793 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6588744249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{258 0 0-8088 {}}} CYCLES {}}
+set a(0-8085) {NAME ACC1:slc(ACC1:acc#228.psp)#53 TYPE READSLICE PAR 0-7009 XREFS 47794 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6588744249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{258 0 0-8088 {}}} CYCLES {}}
+set a(0-8086) {NAME ACC1-3:slc(acc#10.psp)#69 TYPE READSLICE PAR 0-7009 XREFS 47795 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6588744249999999} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8087 {}}} CYCLES {}}
+set a(0-8087) {NAME ACC1-3:exs#50 TYPE SIGNEXTEND PAR 0-7009 XREFS 47796 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{259 0 0-8086 {}}} SUCCS {{259 0 0-8088 {}}} CYCLES {}}
+set a(0-8088) {NAME ACC1:conc#1108 TYPE CONCATENATE PAR 0-7009 XREFS 47797 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{258 0 0-8085 {}} {258 0 0-8084 {}} {259 0 0-8087 {}}} SUCCS {{258 0 0-8094 {}}} CYCLES {}}
+set a(0-8089) {NAME ACC1:slc(ACC1-1:acc#25.psp)#21 TYPE READSLICE PAR 0-7009 XREFS 47798 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6588744249999999} PREDS {{258 0 0-7252 {}}} SUCCS {{258 0 0-8093 {}}} CYCLES {}}
+set a(0-8090) {NAME ACC1:slc(ACC1:acc#226.psp)#44 TYPE READSLICE PAR 0-7009 XREFS 47799 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6588744249999999} PREDS {{258 0 0-7403 {}}} SUCCS {{258 0 0-8093 {}}} CYCLES {}}
+set a(0-8091) {NAME ACC1:slc(acc#5.psp#2)#31 TYPE READSLICE PAR 0-7009 XREFS 47800 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6588744249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8092 {}}} CYCLES {}}
+set a(0-8092) {NAME ACC1-2:exs#34 TYPE SIGNEXTEND PAR 0-7009 XREFS 47801 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{259 0 0-8091 {}}} SUCCS {{259 0 0-8093 {}}} CYCLES {}}
+set a(0-8093) {NAME ACC1:conc#1109 TYPE CONCATENATE PAR 0-7009 XREFS 47802 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{258 0 0-8090 {}} {258 0 0-8089 {}} {259 0 0-8092 {}}} SUCCS {{259 0 0-8094 {}}} CYCLES {}}
+set a(0-8094) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#572 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 47803 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6327331951789505 1 0.7122214451789504} PREDS {{258 0 0-8088 {}} {259 0 0-8093 {}}} SUCCS {{258 0 0-8106 {}}} CYCLES {}}
+set a(0-8095) {NAME ACC1:slc(ACC1-1:acc#25.psp)#22 TYPE READSLICE PAR 0-7009 XREFS 47804 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6588744249999999} PREDS {{258 0 0-7252 {}}} SUCCS {{258 0 0-8099 {}}} CYCLES {}}
+set a(0-8096) {NAME ACC1:slc(ACC1:acc#224.psp#1)#27 TYPE READSLICE PAR 0-7009 XREFS 47805 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6588744249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{258 0 0-8099 {}}} CYCLES {}}
+set a(0-8097) {NAME ACC1:slc(acc#5.psp#2)#32 TYPE READSLICE PAR 0-7009 XREFS 47806 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6588744249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8098 {}}} CYCLES {}}
+set a(0-8098) {NAME ACC1-2:exs#35 TYPE SIGNEXTEND PAR 0-7009 XREFS 47807 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{259 0 0-8097 {}}} SUCCS {{259 0 0-8099 {}}} CYCLES {}}
+set a(0-8099) {NAME ACC1:conc#1110 TYPE CONCATENATE PAR 0-7009 XREFS 47808 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{258 0 0-8096 {}} {258 0 0-8095 {}} {259 0 0-8098 {}}} SUCCS {{258 0 0-8105 {}}} CYCLES {}}
+set a(0-8100) {NAME ACC1:slc(acc#20.psp#1)#35 TYPE READSLICE PAR 0-7009 XREFS 47809 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6588744249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8104 {}}} CYCLES {}}
+set a(0-8101) {NAME ACC1:slc(ACC1-1:acc#25.psp)#23 TYPE READSLICE PAR 0-7009 XREFS 47810 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6588744249999999} PREDS {{258 0 0-7252 {}}} SUCCS {{258 0 0-8104 {}}} CYCLES {}}
+set a(0-8102) {NAME ACC1:slc(acc#5.psp#2)#33 TYPE READSLICE PAR 0-7009 XREFS 47811 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6588744249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8103 {}}} CYCLES {}}
+set a(0-8103) {NAME ACC1-2:exs#22 TYPE SIGNEXTEND PAR 0-7009 XREFS 47812 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{259 0 0-8102 {}}} SUCCS {{259 0 0-8104 {}}} CYCLES {}}
+set a(0-8104) {NAME ACC1:conc#1111 TYPE CONCATENATE PAR 0-7009 XREFS 47813 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{258 0 0-8101 {}} {258 0 0-8100 {}} {259 0 0-8103 {}}} SUCCS {{259 0 0-8105 {}}} CYCLES {}}
+set a(0-8105) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#571 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 47814 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6327331951789505 1 0.7122214451789504} PREDS {{258 0 0-8099 {}} {259 0 0-8104 {}}} SUCCS {{259 0 0-8106 {}}} CYCLES {}}
+set a(0-8106) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#601 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-7009 XREFS 47815 LOC {1 0.19990202499999998 1 0.63273325 1 0.63273325 1 0.6913329594969361 1 0.770821209496936} PREDS {{258 0 0-8094 {}} {259 0 0-8105 {}}} SUCCS {{258 0 0-8140 {}}} CYCLES {}}
+set a(0-8107) {NAME ACC1:slc(ACC1:acc#217.psp#1)#15 TYPE READSLICE PAR 0-7009 XREFS 47816 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.679184675} PREDS {{258 0 0-7741 {}}} SUCCS {{259 0 0-8108 {}}} CYCLES {}}
+set a(0-8108) {NAME ACC1:not#383 TYPE NOT PAR 0-7009 XREFS 47817 LOC {1 0.267931 1 0.599696425 1 0.599696425 1 0.679184675} PREDS {{259 0 0-8107 {}}} SUCCS {{258 0 0-8113 {}}} CYCLES {}}
+set a(0-8109) {NAME ACC1:slc(ACC1:acc#210.psp#1)#15 TYPE READSLICE PAR 0-7009 XREFS 47818 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.679184675} PREDS {{258 0 0-7515 {}}} SUCCS {{259 0 0-8110 {}}} CYCLES {}}
+set a(0-8110) {NAME ACC1:not#384 TYPE NOT PAR 0-7009 XREFS 47819 LOC {1 0.267931 1 0.599696425 1 0.599696425 1 0.679184675} PREDS {{259 0 0-8109 {}}} SUCCS {{258 0 0-8113 {}}} CYCLES {}}
+set a(0-8111) {NAME ACC1:slc(acc.imod#42)#2 TYPE READSLICE PAR 0-7009 XREFS 47820 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.679184675} PREDS {{258 0 0-7310 {}}} SUCCS {{259 0 0-8112 {}}} CYCLES {}}
+set a(0-8112) {NAME ACC1:not#385 TYPE NOT PAR 0-7009 XREFS 47821 LOC {1 0.356432775 1 0.599696425 1 0.599696425 1 0.679184675} PREDS {{259 0 0-8111 {}}} SUCCS {{259 0 0-8113 {}}} CYCLES {}}
+set a(0-8113) {NAME ACC1:conc#1112 TYPE CONCATENATE PAR 0-7009 XREFS 47822 LOC {1 0.356432775 1 0.599696425 1 0.599696425 1 0.679184675} PREDS {{258 0 0-8110 {}} {258 0 0-8108 {}} {259 0 0-8112 {}}} SUCCS {{258 0 0-8119 {}}} CYCLES {}}
+set a(0-8114) {NAME ACC1:slc(acc.psp#2)#10 TYPE READSLICE PAR 0-7009 XREFS 47823 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.679184675} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-8118 {}}} CYCLES {}}
+set a(0-8115) {NAME ACC1:slc(acc#20.psp#1)#36 TYPE READSLICE PAR 0-7009 XREFS 47824 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.679184675} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8118 {}}} CYCLES {}}
+set a(0-8116) {NAME ACC1:slc(acc#5.psp#2)#34 TYPE READSLICE PAR 0-7009 XREFS 47825 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.679184675} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8117 {}}} CYCLES {}}
+set a(0-8117) {NAME ACC1-2:exs#23 TYPE SIGNEXTEND PAR 0-7009 XREFS 47826 LOC {1 0.14655495 1 0.599696425 1 0.599696425 1 0.679184675} PREDS {{259 0 0-8116 {}}} SUCCS {{259 0 0-8118 {}}} CYCLES {}}
+set a(0-8118) {NAME ACC1:conc#1113 TYPE CONCATENATE PAR 0-7009 XREFS 47827 LOC {1 0.14655495 1 0.599696425 1 0.599696425 1 0.679184675} PREDS {{258 0 0-8115 {}} {258 0 0-8114 {}} {259 0 0-8117 {}}} SUCCS {{259 0 0-8119 {}}} CYCLES {}}
+set a(0-8119) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#570 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 47828 LOC {1 0.356432775 1 0.599696425 1 0.599696425 1 0.6530434451789504 1 0.7325316951789504} PREDS {{258 0 0-8113 {}} {259 0 0-8118 {}}} SUCCS {{258 0 0-8139 {}}} CYCLES {}}
+set a(0-8120) {NAME ACC1-3:slc(acc.idiv#4)#45 TYPE READSLICE PAR 0-7009 XREFS 47829 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6577296499999999} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8124 {}}} CYCLES {}}
+set a(0-8121) {NAME ACC1-3:slc(acc.imod#19)#1 TYPE READSLICE PAR 0-7009 XREFS 47830 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.6577296499999999} PREDS {{258 0 0-7768 {}}} SUCCS {{259 0 0-8122 {}}} CYCLES {}}
+set a(0-8122) {NAME ACC1-3:not#156 TYPE NOT PAR 0-7009 XREFS 47831 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.6577296499999999} PREDS {{259 0 0-8121 {}}} SUCCS {{258 0 0-8124 {}}} CYCLES {}}
+set a(0-8123) {NAME ACC1-3:slc(acc.imod#19)#2 TYPE READSLICE PAR 0-7009 XREFS 47832 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.6577296499999999} PREDS {{258 0 0-7768 {}}} SUCCS {{259 0 0-8124 {}}} CYCLES {}}
+set a(0-8124) {NAME ACC1-3:and#9 TYPE AND PAR 0-7009 XREFS 47833 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.6577296499999999} PREDS {{258 0 0-8122 {}} {258 0 0-8120 {}} {259 0 0-8123 {}}} SUCCS {{258 0 0-8126 {}}} CYCLES {}}
+set a(0-8125) {NAME ACC1:slc(ACC1:acc#224.psp#1)#20 TYPE READSLICE PAR 0-7009 XREFS 47834 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6577296499999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-8126 {}}} CYCLES {}}
+set a(0-8126) {NAME ACC1:conc#1095 TYPE CONCATENATE PAR 0-7009 XREFS 47835 LOC {1 0.3836787 1 0.5782414 1 0.5782414 1 0.6577296499999999} PREDS {{258 0 0-8124 {}} {259 0 0-8125 {}}} SUCCS {{259 0 0-8127 {}}} CYCLES {}}
+set a(0-8127) {NAME ACC1:conc#1308 TYPE CONCATENATE PAR 0-7009 XREFS 47836 LOC {1 0.3836787 1 0.5782414 1 0.5782414 1 0.6577296499999999} PREDS {{259 0 0-8126 {}}} SUCCS {{258 0 0-8133 {}}} CYCLES {}}
+set a(0-8128) {NAME ACC1:slc(acc.psp#2)#8 TYPE READSLICE PAR 0-7009 XREFS 47837 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6577296499999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-8130 {}}} CYCLES {}}
+set a(0-8129) {NAME ACC1:slc(ACC1:acc#224.psp#1)#21 TYPE READSLICE PAR 0-7009 XREFS 47838 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6577296499999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-8130 {}}} CYCLES {}}
+set a(0-8130) {NAME ACC1:conc#1096 TYPE CONCATENATE PAR 0-7009 XREFS 47839 LOC {1 0.14655495 1 0.5782414 1 0.5782414 1 0.6577296499999999} PREDS {{258 0 0-8128 {}} {259 0 0-8129 {}}} SUCCS {{258 0 0-8132 {}}} CYCLES {}}
+set a(0-8131) {NAME ACC1:slc(ACC1-1:acc#25.psp)#16 TYPE READSLICE PAR 0-7009 XREFS 47840 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6577296499999999} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8132 {}}} CYCLES {}}
+set a(0-8132) {NAME ACC1:conc#1309 TYPE CONCATENATE PAR 0-7009 XREFS 47841 LOC {1 0.14655495 1 0.5782414 1 0.5782414 1 0.6577296499999999} PREDS {{258 0 0-8130 {}} {259 0 0-8131 {}}} SUCCS {{259 0 0-8133 {}}} CYCLES {}}
+set a(0-8133) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#425 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47842 LOC {1 0.3836787 1 0.5782414 1 0.5782414 1 0.6257975270708271 1 0.7052857770708271} PREDS {{258 0 0-8127 {}} {259 0 0-8132 {}}} SUCCS {{259 0 0-8134 {}}} CYCLES {}}
+set a(0-8134) {NAME ACC1:slc#93 TYPE READSLICE PAR 0-7009 XREFS 47843 LOC {1 0.43123487499999996 1 0.625797575 1 0.625797575 1 0.7052858249999999} PREDS {{259 0 0-8133 {}}} SUCCS {{258 0 0-8138 {}}} CYCLES {}}
+set a(0-8135) {NAME ACC1:slc(ACC1:acc#223.psp) TYPE READSLICE PAR 0-7009 XREFS 47844 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.7052858249999999} PREDS {{258 0 0-7752 {}}} SUCCS {{258 0 0-8137 {}}} CYCLES {}}
+set a(0-8136) {NAME ACC1:slc(ACC1:acc#224.psp#1)#22 TYPE READSLICE PAR 0-7009 XREFS 47845 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.7052858249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-8137 {}}} CYCLES {}}
+set a(0-8137) {NAME ACC1:conc#1097 TYPE CONCATENATE PAR 0-7009 XREFS 47846 LOC {1 0.32918685 1 0.625797575 1 0.625797575 1 0.7052858249999999} PREDS {{258 0 0-8135 {}} {259 0 0-8136 {}}} SUCCS {{259 0 0-8138 {}}} CYCLES {}}
+set a(0-8138) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#524 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47847 LOC {1 0.43123487499999996 1 0.625797575 1 0.625797575 1 0.6530434520708271 1 0.7325317020708271} PREDS {{258 0 0-8134 {}} {259 0 0-8137 {}}} SUCCS {{259 0 0-8139 {}}} CYCLES {}}
+set a(0-8139) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#600 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-7009 XREFS 47848 LOC {1 0.45848079999999997 1 0.6530435 1 0.6530435 1 0.6913329594969361 1 0.770821209496936} PREDS {{258 0 0-8119 {}} {259 0 0-8138 {}}} SUCCS {{259 0 0-8140 {}}} CYCLES {}}
+set a(0-8140) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#620 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-7009 XREFS 47849 LOC {1 0.4967703 1 0.691333 1 0.691333 1 0.7548449734103024 1 0.8343332234103025} PREDS {{258 0 0-8106 {}} {259 0 0-8139 {}}} SUCCS {{258 0 0-8165 {}}} CYCLES {}}
+set a(0-8141) {NAME ACC1-3:slc(acc.idiv#1)#15 TYPE READSLICE PAR 0-7009 XREFS 47850 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.720693625} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8142 {}}} CYCLES {}}
+set a(0-8142) {NAME ACC1-3:exs#25 TYPE SIGNEXTEND PAR 0-7009 XREFS 47851 LOC {1 0.14655495 1 0.641205375 1 0.641205375 1 0.720693625} PREDS {{259 0 0-8141 {}}} SUCCS {{259 0 0-8143 {}}} CYCLES {}}
+set a(0-8143) {NAME ACC1:conc#1344 TYPE CONCATENATE PAR 0-7009 XREFS 47852 LOC {1 0.14655495 1 0.641205375 1 0.641205375 1 0.720693625} PREDS {{259 0 0-8142 {}}} SUCCS {{258 0 0-8147 {}}} CYCLES {}}
+set a(0-8144) {NAME ACC1:slc(ACC1:acc#220.psp#1) TYPE READSLICE PAR 0-7009 XREFS 47853 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.720693625} PREDS {{258 0 0-7073 {}}} SUCCS {{258 0 0-8146 {}}} CYCLES {}}
+set a(0-8145) {NAME ACC1:slc(acc.imod#31) TYPE READSLICE PAR 0-7009 XREFS 47854 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.720693625} PREDS {{258 0 0-7386 {}}} SUCCS {{259 0 0-8146 {}}} CYCLES {}}
+set a(0-8146) {NAME ACC1:conc#1345 TYPE CONCATENATE PAR 0-7009 XREFS 47855 LOC {1 0.3471661 1 0.641205375 1 0.641205375 1 0.720693625} PREDS {{258 0 0-8144 {}} {259 0 0-8145 {}}} SUCCS {{259 0 0-8147 {}}} CYCLES {}}
+set a(0-8147) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#443 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47856 LOC {1 0.3471661 1 0.641205375 1 0.641205375 1 0.6684512520708271 1 0.7479395020708272} PREDS {{258 0 0-8143 {}} {259 0 0-8146 {}}} SUCCS {{259 0 0-8148 {}}} CYCLES {}}
+set a(0-8148) {NAME ACC1:slc#111 TYPE READSLICE PAR 0-7009 XREFS 47857 LOC {1 0.374412025 1 0.6684513 1 0.6684513 1 0.74793955} PREDS {{259 0 0-8147 {}}} SUCCS {{258 0 0-8154 {}}} CYCLES {}}
+set a(0-8149) {NAME ACC1:slc(ACC1:acc#224.psp#1)#25 TYPE READSLICE PAR 0-7009 XREFS 47858 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.74793955} PREDS {{258 0 0-7107 {}}} SUCCS {{258 0 0-8153 {}}} CYCLES {}}
+set a(0-8150) {NAME ACC1:slc(ACC1:acc#224.psp)#53 TYPE READSLICE PAR 0-7009 XREFS 47859 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.74793955} PREDS {{258 0 0-7629 {}}} SUCCS {{258 0 0-8153 {}}} CYCLES {}}
+set a(0-8151) {NAME ACC1-3:slc(acc#10.psp)#70 TYPE READSLICE PAR 0-7009 XREFS 47860 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.74793955} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8152 {}}} CYCLES {}}
+set a(0-8152) {NAME ACC1-3:exs#49 TYPE SIGNEXTEND PAR 0-7009 XREFS 47861 LOC {1 0.14655495 1 0.6684513 1 0.6684513 1 0.74793955} PREDS {{259 0 0-8151 {}}} SUCCS {{259 0 0-8153 {}}} CYCLES {}}
+set a(0-8153) {NAME ACC1:conc#1107 TYPE CONCATENATE PAR 0-7009 XREFS 47862 LOC {1 0.14655495 1 0.6684513 1 0.6684513 1 0.74793955} PREDS {{258 0 0-8150 {}} {258 0 0-8149 {}} {259 0 0-8152 {}}} SUCCS {{259 0 0-8154 {}}} CYCLES {}}
+set a(0-8154) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#573 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 47863 LOC {1 0.374412025 1 0.6684513 1 0.6684513 1 0.7014880701789504 1 0.7809763201789505} PREDS {{258 0 0-8148 {}} {259 0 0-8153 {}}} SUCCS {{258 0 0-8164 {}}} CYCLES {}}
+set a(0-8155) {NAME ACC1:slc(acc.psp#2)#11 TYPE READSLICE PAR 0-7009 XREFS 47864 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.74793955} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-8159 {}}} CYCLES {}}
+set a(0-8156) {NAME ACC1:slc(acc.psp#2)#12 TYPE READSLICE PAR 0-7009 XREFS 47865 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.74793955} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-8159 {}}} CYCLES {}}
+set a(0-8157) {NAME ACC1:slc(acc#5.psp#2)#35 TYPE READSLICE PAR 0-7009 XREFS 47866 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.74793955} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8158 {}}} CYCLES {}}
+set a(0-8158) {NAME ACC1-2:exs#18 TYPE SIGNEXTEND PAR 0-7009 XREFS 47867 LOC {1 0.14655495 1 0.6684513 1 0.6684513 1 0.74793955} PREDS {{259 0 0-8157 {}}} SUCCS {{259 0 0-8159 {}}} CYCLES {}}
+set a(0-8159) {NAME ACC1:conc#1114 TYPE CONCATENATE PAR 0-7009 XREFS 47868 LOC {1 0.14655495 1 0.6684513 1 0.6684513 1 0.74793955} PREDS {{258 0 0-8156 {}} {258 0 0-8155 {}} {259 0 0-8158 {}}} SUCCS {{258 0 0-8163 {}}} CYCLES {}}
+set a(0-8160) {NAME ACC1:slc(ACC1:acc#220.psp) TYPE READSLICE PAR 0-7009 XREFS 47869 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.717311625} PREDS {{258 0 0-7526 {}}} SUCCS {{258 0 0-8162 {}}} CYCLES {}}
+set a(0-8161) {NAME ACC1:slc(ACC1:acc#222.psp) TYPE READSLICE PAR 0-7009 XREFS 47870 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.717311625} PREDS {{258 0 0-7677 {}}} SUCCS {{259 0 0-8162 {}}} CYCLES {}}
+set a(0-8162) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,1,2,1,3) AREA_SCORE 3.00 QUANTITY 1 NAME ACC1:acc#519 TYPE ACCU DELAY {0.49 ns} LIBRARY_DELAY {0.49 ns} PAR 0-7009 XREFS 47871 LOC {1 0.32918685 1 0.637823375 1 0.637823375 1 0.6684512600894752 1 0.7479395100894752} PREDS {{258 0 0-8160 {}} {259 0 0-8161 {}}} SUCCS {{259 0 0-8163 {}}} CYCLES {}}
+set a(0-8163) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#569 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 47872 LOC {1 0.359814775 1 0.6684513 1 0.6684513 1 0.7014880701789504 1 0.7809763201789505} PREDS {{258 0 0-8159 {}} {259 0 0-8162 {}}} SUCCS {{259 0 0-8164 {}}} CYCLES {}}
+set a(0-8164) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,1,6,1,7) AREA_SCORE 7.00 QUANTITY 1 NAME ACC1:acc#619 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 47873 LOC {1 0.40744885 1 0.701488125 1 0.701488125 1 0.7548449734103024 1 0.8343332234103024} PREDS {{258 0 0-8154 {}} {259 0 0-8163 {}}} SUCCS {{259 0 0-8165 {}}} CYCLES {}}
+set a(0-8165) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 6 NAME ACC1:acc#635 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-7009 XREFS 47874 LOC {1 0.560282325 1 0.754845025 1 0.754845025 1 0.8027240879329679 1 0.8822123379329679} PREDS {{258 0 0-8140 {}} {259 0 0-8164 {}}} SUCCS {{258 0 0-8173 {}}} CYCLES {}}
+set a(0-8166) {NAME slc(acc#20.psp#1)#91 TYPE READSLICE PAR 0-7009 XREFS 47875 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.8822124} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8172 {}}} CYCLES {}}
+set a(0-8167) {NAME slc(acc#20.psp#1)#92 TYPE READSLICE PAR 0-7009 XREFS 47876 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.8822124} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8172 {}}} CYCLES {}}
+set a(0-8168) {NAME slc(acc#20.psp#1)#80 TYPE READSLICE PAR 0-7009 XREFS 47877 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.8822124} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8172 {}}} CYCLES {}}
+set a(0-8169) {NAME ACC1:slc(ACC1:acc#228.psp)#54 TYPE READSLICE PAR 0-7009 XREFS 47878 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.8822124} PREDS {{258 0 0-7331 {}}} SUCCS {{258 0 0-8172 {}}} CYCLES {}}
+set a(0-8170) {NAME ACC1-3:slc(acc#10.psp)#63 TYPE READSLICE PAR 0-7009 XREFS 47879 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.8822124} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8171 {}}} CYCLES {}}
+set a(0-8171) {NAME ACC1-3:exs#36 TYPE SIGNEXTEND PAR 0-7009 XREFS 47880 LOC {1 0.14655495 1 0.80272415 1 0.80272415 1 0.8822124} PREDS {{259 0 0-8170 {}}} SUCCS {{259 0 0-8172 {}}} CYCLES {}}
+set a(0-8172) {NAME ACC1:conc#1115 TYPE CONCATENATE PAR 0-7009 XREFS 47881 LOC {1 0.14655495 1 0.80272415 1 0.80272415 1 0.8822124} PREDS {{258 0 0-8169 {}} {258 0 0-8168 {}} {258 0 0-8167 {}} {258 0 0-8166 {}} {259 0 0-8171 {}}} SUCCS {{259 0 0-8173 {}}} CYCLES {}}
+set a(0-8173) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,1,11) AREA_SCORE 10.00 QUANTITY 5 NAME ACC1:acc#646 TYPE ACCU DELAY {0.91 ns} LIBRARY_DELAY {0.91 ns} PAR 0-7009 XREFS 47882 LOC {1 0.60816145 1 0.80272415 1 0.80272415 1 0.8594826628916543 1 0.9389709128916544} PREDS {{258 0 0-8165 {}} {259 0 0-8172 {}}} SUCCS {{258 0 0-8190 {}}} CYCLES {}}
+set a(0-8174) {NAME ACC1:slc(ACC1:acc#227.psp)#53 TYPE READSLICE PAR 0-7009 XREFS 47883 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.57932165} PREDS {{258 0 0-7554 {}}} SUCCS {{258 0 0-8176 {}}} CYCLES {}}
+set a(0-8175) {NAME ACC1:slc(acc.psp#1)#52 TYPE READSLICE PAR 0-7009 XREFS 47884 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.57932165} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8176 {}}} CYCLES {}}
+set a(0-8176) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#308 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-7009 XREFS 47885 LOC {1 0.14655495 1 0.4998334 1 0.4998334 1 0.53144423625 1 0.6109324862500001} PREDS {{258 0 0-8174 {}} {259 0 0-8175 {}}} SUCCS {{258 0 0-8178 {}}} CYCLES {}}
+set a(0-8177) {NAME ACC1:slc(ACC1:acc#224.psp)#43 TYPE READSLICE PAR 0-7009 XREFS 47886 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.610932525} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8178 {}}} CYCLES {}}
+set a(0-8178) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#307 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47887 LOC {1 0.178165825 1 0.531444275 1 0.531444275 1 0.5519170350894753 1 0.6314052850894752} PREDS {{258 0 0-8176 {}} {259 0 0-8177 {}}} SUCCS {{258 0 0-8180 {}}} CYCLES {}}
+set a(0-8179) {NAME ACC1:slc(ACC1:acc#228.psp)#43 TYPE READSLICE PAR 0-7009 XREFS 47888 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.631405325} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8180 {}}} CYCLES {}}
+set a(0-8180) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#306 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47889 LOC {1 0.19863862499999999 1 0.551917075 1 0.551917075 1 0.5723898350894753 1 0.6518780850894753} PREDS {{258 0 0-8178 {}} {259 0 0-8179 {}}} SUCCS {{258 0 0-8182 {}}} CYCLES {}}
+set a(0-8181) {NAME ACC1:slc(ACC1:acc#226.psp)#35 TYPE READSLICE PAR 0-7009 XREFS 47890 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.651878125} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8182 {}}} CYCLES {}}
+set a(0-8182) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#305 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47891 LOC {1 0.219111425 1 0.5723898749999999 1 0.5723898749999999 1 0.5996357520708271 1 0.6791240020708271} PREDS {{258 0 0-8180 {}} {259 0 0-8181 {}}} SUCCS {{258 0 0-8184 {}}} CYCLES {}}
+set a(0-8183) {NAME ACC1:slc(ACC1:acc#224.psp#1)#15 TYPE READSLICE PAR 0-7009 XREFS 47892 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.67912405} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-8184 {}}} CYCLES {}}
+set a(0-8184) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#304 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47893 LOC {1 0.24635735 1 0.5996357999999999 1 0.5996357999999999 1 0.6268816770708271 1 0.7063699270708271} PREDS {{258 0 0-8182 {}} {259 0 0-8183 {}}} SUCCS {{258 0 0-8186 {}}} CYCLES {}}
+set a(0-8185) {NAME ACC1:slc(ACC1-1:acc#25.psp)#13 TYPE READSLICE PAR 0-7009 XREFS 47894 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.706369975} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8186 {}}} CYCLES {}}
+set a(0-8186) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#303 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47895 LOC {1 0.273603275 1 0.626881725 1 0.626881725 1 0.6541276020708271 1 0.7336158520708271} PREDS {{258 0 0-8184 {}} {259 0 0-8185 {}}} SUCCS {{258 0 0-8188 {}}} CYCLES {}}
+set a(0-8187) {NAME ACC1:slc(acc.psp#2)#1 TYPE READSLICE PAR 0-7009 XREFS 47896 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7336159} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8188 {}}} CYCLES {}}
+set a(0-8188) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#302 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47897 LOC {1 0.3008492 1 0.65412765 1 0.65412765 1 0.6813735270708271 1 0.7608617770708271} PREDS {{258 0 0-8186 {}} {259 0 0-8187 {}}} SUCCS {{259 0 0-8189 {}}} CYCLES {}}
+set a(0-8189) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(4,0,7,0,10) AREA_SCORE 330.25 QUANTITY 2 NAME ACC1:mul#54 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-7009 XREFS 47898 LOC {1 0.328095125 1 0.681373575 1 0.681373575 1 0.8594826825545158 1 0.9389709325545158} PREDS {{259 0 0-8188 {}}} SUCCS {{259 0 0-8190 {}}} CYCLES {}}
+set a(0-8190) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,12) AREA_SCORE 11.00 QUANTITY 4 NAME ACC1:acc#651 TYPE ACCU DELAY {0.98 ns} LIBRARY_DELAY {0.98 ns} PAR 0-7009 XREFS 47899 LOC {1 0.6649200249999999 1 0.859482725 1 0.859482725 1 0.9205117033364113 1 0.9999999533364112} PREDS {{258 0 0-8173 {}} {259 0 0-8189 {}}} SUCCS {{258 0 0-8207 {}}} CYCLES {}}
+set a(0-8191) {NAME ACC1:slc(ACC1:acc#227.psp)#54 TYPE READSLICE PAR 0-7009 XREFS 47900 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6319135499999999} PREDS {{258 0 0-7554 {}}} SUCCS {{258 0 0-8193 {}}} CYCLES {}}
+set a(0-8192) {NAME ACC1:slc(acc.psp#1)#53 TYPE READSLICE PAR 0-7009 XREFS 47901 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6319135499999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8193 {}}} CYCLES {}}
+set a(0-8193) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#315 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-7009 XREFS 47902 LOC {1 0.14655495 1 0.5524253 1 0.5524253 1 0.58403613625 1 0.66352438625} PREDS {{258 0 0-8191 {}} {259 0 0-8192 {}}} SUCCS {{258 0 0-8195 {}}} CYCLES {}}
+set a(0-8194) {NAME ACC1:slc(ACC1:acc#224.psp)#44 TYPE READSLICE PAR 0-7009 XREFS 47903 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.663524425} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8195 {}}} CYCLES {}}
+set a(0-8195) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#314 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47904 LOC {1 0.178165825 1 0.5840361749999999 1 0.5840361749999999 1 0.6045089350894752 1 0.6839971850894753} PREDS {{258 0 0-8193 {}} {259 0 0-8194 {}}} SUCCS {{258 0 0-8197 {}}} CYCLES {}}
+set a(0-8196) {NAME ACC1:slc(ACC1:acc#228.psp)#44 TYPE READSLICE PAR 0-7009 XREFS 47905 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6839972249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8197 {}}} CYCLES {}}
+set a(0-8197) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#313 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47906 LOC {1 0.19863862499999999 1 0.604508975 1 0.604508975 1 0.6249817350894753 1 0.7044699850894752} PREDS {{258 0 0-8195 {}} {259 0 0-8196 {}}} SUCCS {{258 0 0-8199 {}}} CYCLES {}}
+set a(0-8198) {NAME ACC1:slc(ACC1:acc#226.psp)#36 TYPE READSLICE PAR 0-7009 XREFS 47907 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.704470025} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8199 {}}} CYCLES {}}
+set a(0-8199) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#312 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47908 LOC {1 0.219111425 1 0.624981775 1 0.624981775 1 0.6522276520708271 1 0.7317159020708272} PREDS {{258 0 0-8197 {}} {259 0 0-8198 {}}} SUCCS {{258 0 0-8201 {}}} CYCLES {}}
+set a(0-8200) {NAME ACC1:slc(ACC1:acc#224.psp#1)#16 TYPE READSLICE PAR 0-7009 XREFS 47909 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.73171595} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-8201 {}}} CYCLES {}}
+set a(0-8201) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#311 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47910 LOC {1 0.24635735 1 0.6522277 1 0.6522277 1 0.6794735770708271 1 0.7589618270708272} PREDS {{258 0 0-8199 {}} {259 0 0-8200 {}}} SUCCS {{258 0 0-8203 {}}} CYCLES {}}
+set a(0-8202) {NAME ACC1:slc(ACC1-1:acc#25.psp)#14 TYPE READSLICE PAR 0-7009 XREFS 47911 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.758961875} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8203 {}}} CYCLES {}}
+set a(0-8203) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#310 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47912 LOC {1 0.273603275 1 0.679473625 1 0.679473625 1 0.7067195020708271 1 0.7862077520708272} PREDS {{258 0 0-8201 {}} {259 0 0-8202 {}}} SUCCS {{258 0 0-8205 {}}} CYCLES {}}
+set a(0-8204) {NAME ACC1:slc(acc.psp#2)#2 TYPE READSLICE PAR 0-7009 XREFS 47913 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7862078} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8205 {}}} CYCLES {}}
+set a(0-8205) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#309 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 47914 LOC {1 0.3008492 1 0.70671955 1 0.70671955 1 0.7339654270708271 1 0.8134536770708272} PREDS {{258 0 0-8203 {}} {259 0 0-8204 {}}} SUCCS {{259 0 0-8206 {}}} CYCLES {}}
+set a(0-8206) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(4,0,9,0,12) AREA_SCORE 330.25 QUANTITY 1 NAME ACC1:mul#55 TYPE MUL DELAY {2.98 ns} LIBRARY_DELAY {2.98 ns} PAR 0-7009 XREFS 47915 LOC {1 0.328095125 1 0.733965475 1 0.733965475 1 0.9205116924845187 1 0.9999999424845187} PREDS {{259 0 0-8205 {}}} SUCCS {{259 0 0-8207 {}}} CYCLES {}}
+set a(0-8207) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,12,1,13) AREA_SCORE 13.00 QUANTITY 2 NAME ACC1:acc#658 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-7009 XREFS 47916 LOC {1 0.72594905 1 0.92051175 1 0.92051175 1 0.9999999534997777 2 0.13630012849977768} PREDS {{258 0 0-8190 {}} {259 0 0-8206 {}}} SUCCS {{259 0 0-8208 {}}} CYCLES {}}
+set a(0-8208) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,1,13,1,14) AREA_SCORE 14.00 QUANTITY 2 NAME ACC1:acc#662 TYPE ACCU DELAY {1.34 ns} LIBRARY_DELAY {1.34 ns} PAR 0-7009 XREFS 47917 LOC {2 0.0 2 0.136300175 2 0.136300175 2 0.21984771205035814 2 0.21984771205035814} PREDS {{258 0 0-8083 {}} {259 0 0-8207 {}}} SUCCS {{258 0 0-8234 {}}} CYCLES {}}
+set a(0-8209) {NAME slc(ACC1:acc#226.psp)#26 TYPE READSLICE PAR 0-7009 XREFS 47918 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.056811925} PREDS {{258 0 0-7403 {}}} SUCCS {{258 0 0-8213 {}}} CYCLES {}}
+set a(0-8210) {NAME slc(ACC1:acc#226.psp)#27 TYPE READSLICE PAR 0-7009 XREFS 47919 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.056811925} PREDS {{258 0 0-7403 {}}} SUCCS {{258 0 0-8213 {}}} CYCLES {}}
+set a(0-8211) {NAME slc(ACC1:acc#226.psp) TYPE READSLICE PAR 0-7009 XREFS 47920 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.056811925} PREDS {{258 0 0-7403 {}}} SUCCS {{258 0 0-8213 {}}} CYCLES {}}
+set a(0-8212) {NAME ACC1:slc(acc.psp#1)#57 TYPE READSLICE PAR 0-7009 XREFS 47921 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.056811925} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8213 {}}} CYCLES {}}
+set a(0-8213) {NAME ACC1:conc#1074 TYPE CONCATENATE PAR 0-7009 XREFS 47922 LOC {1 0.14655495 1 0.836964175 1 0.836964175 2 0.056811925} PREDS {{258 0 0-8211 {}} {258 0 0-8210 {}} {258 0 0-8209 {}} {259 0 0-8212 {}}} SUCCS {{258 0 0-8226 {}}} CYCLES {}}
+set a(0-8214) {NAME ACC1:slc(ACC1:acc#224.psp)#52 TYPE READSLICE PAR 0-7009 XREFS 47923 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.749334375} PREDS {{258 0 0-7629 {}}} SUCCS {{258 0 0-8216 {}}} CYCLES {}}
+set a(0-8215) {NAME ACC1:slc(ACC1:acc#228.psp)#52 TYPE READSLICE PAR 0-7009 XREFS 47924 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.749334375} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8216 {}}} CYCLES {}}
+set a(0-8216) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#329 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-7009 XREFS 47925 LOC {1 0.14655495 1 0.58629855 1 0.58629855 1 0.61790938625 1 0.7809452112499999} PREDS {{258 0 0-8214 {}} {259 0 0-8215 {}}} SUCCS {{258 0 0-8218 {}}} CYCLES {}}
+set a(0-8217) {NAME ACC1:slc(ACC1:acc#226.psp)#43 TYPE READSLICE PAR 0-7009 XREFS 47926 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7809452499999999} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8218 {}}} CYCLES {}}
+set a(0-8218) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#328 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47927 LOC {1 0.178165825 1 0.617909425 1 0.617909425 1 0.6383821850894753 1 0.8014180100894752} PREDS {{258 0 0-8216 {}} {259 0 0-8217 {}}} SUCCS {{258 0 0-8220 {}}} CYCLES {}}
+set a(0-8219) {NAME ACC1:slc(ACC1:acc#224.psp#1)#24 TYPE READSLICE PAR 0-7009 XREFS 47928 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.80141805} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-8220 {}}} CYCLES {}}
+set a(0-8220) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#327 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47929 LOC {1 0.19863862499999999 1 0.638382225 1 0.638382225 1 0.6588549850894753 1 0.8218908100894753} PREDS {{258 0 0-8218 {}} {259 0 0-8219 {}}} SUCCS {{259 0 0-8221 {}}} CYCLES {}}
+set a(0-8221) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(4,0,7,0,10) AREA_SCORE 330.25 QUANTITY 2 NAME ACC1:mul#59 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-7009 XREFS 47930 LOC {1 0.219111425 1 0.6588550249999999 1 0.6588550249999999 1 0.8369641325545157 1 0.9999999575545158} PREDS {{259 0 0-8220 {}}} SUCCS {{258 0 0-8225 {}}} CYCLES {}}
+set a(0-8222) {NAME ACC1:slc(acc.psp#1)#61 TYPE READSLICE PAR 0-7009 XREFS 47931 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.056811925} PREDS {{258 0 0-7475 {}}} SUCCS {{258 0 0-8225 {}}} CYCLES {}}
+set a(0-8223) {NAME ACC1-3:slc(acc#10.psp)#71 TYPE READSLICE PAR 0-7009 XREFS 47932 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.056811925} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8224 {}}} CYCLES {}}
+set a(0-8224) {NAME ACC1-3:exs#1034 TYPE SIGNEXTEND PAR 0-7009 XREFS 47933 LOC {1 0.14655495 1 0.836964175 1 0.836964175 2 0.056811925} PREDS {{259 0 0-8223 {}}} SUCCS {{259 0 0-8225 {}}} CYCLES {}}
+set a(0-8225) {NAME ACC1:conc#1106 TYPE CONCATENATE PAR 0-7009 XREFS 47934 LOC {1 0.39722057499999996 1 0.836964175 1 0.836964175 2 0.056811925} PREDS {{258 0 0-8222 {}} {258 0 0-8221 {}} {259 0 0-8224 {}}} SUCCS {{259 0 0-8226 {}}} CYCLES {}}
+set a(0-8226) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,12,1,13) AREA_SCORE 13.00 QUANTITY 2 NAME ACC1:acc#657 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-7009 XREFS 47935 LOC {1 0.39722057499999996 1 0.836964175 1 0.836964175 1 0.9164523784997777 2 0.13630012849977768} PREDS {{258 0 0-8213 {}} {259 0 0-8225 {}}} SUCCS {{258 0 0-8233 {}}} CYCLES {}}
+set a(0-8227) {NAME ACC1:slc(ACC1:acc#227.psp)#55 TYPE READSLICE PAR 0-7009 XREFS 47936 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.7523285249999999} PREDS {{258 0 0-7554 {}}} SUCCS {{258 0 0-8229 {}}} CYCLES {}}
+set a(0-8228) {NAME ACC1:slc(acc.psp#1)#54 TYPE READSLICE PAR 0-7009 XREFS 47937 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7523285249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8229 {}}} CYCLES {}}
+set a(0-8229) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#317 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-7009 XREFS 47938 LOC {1 0.14655495 1 0.6687809499999999 1 0.6687809499999999 1 0.70039178625 1 0.7839393612499999} PREDS {{258 0 0-8227 {}} {259 0 0-8228 {}}} SUCCS {{258 0 0-8231 {}}} CYCLES {}}
+set a(0-8230) {NAME ACC1:slc(acc.psp#2)#3 TYPE READSLICE PAR 0-7009 XREFS 47939 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7839394} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8231 {}}} CYCLES {}}
+set a(0-8231) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#316 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47940 LOC {1 0.178165825 1 0.700391825 1 0.700391825 1 0.7208645850894753 1 0.8044121600894752} PREDS {{258 0 0-8229 {}} {259 0 0-8230 {}}} SUCCS {{259 0 0-8232 {}}} CYCLES {}}
+set a(0-8232) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,11,1,13) AREA_SCORE 330.00 QUANTITY 2 NAME ACC1:mul#56 TYPE MUL DELAY {3.13 ns} LIBRARY_DELAY {3.13 ns} PAR 0-7009 XREFS 47941 LOC {1 0.19863862499999999 1 0.7208646249999999 1 0.7208646249999999 1 0.9164523687499999 1 0.9999999437499999} PREDS {{259 0 0-8231 {}}} SUCCS {{259 0 0-8233 {}}} CYCLES {}}
+set a(0-8233) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,1,13,1,14) AREA_SCORE 14.00 QUANTITY 2 NAME ACC1:acc#661 TYPE ACCU DELAY {1.34 ns} LIBRARY_DELAY {1.34 ns} PAR 0-7009 XREFS 47942 LOC {1 0.476708825 1 0.9164524249999999 1 0.9164524249999999 1 0.999999962050358 2 0.21984771205035814} PREDS {{258 0 0-8226 {}} {259 0 0-8232 {}}} SUCCS {{259 0 0-8234 {}}} CYCLES {}}
+set a(0-8234) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(14,1,14,1,15) AREA_SCORE 15.00 QUANTITY 2 NAME ACC1:acc#664 TYPE ACCU DELAY {1.40 ns} LIBRARY_DELAY {1.40 ns} PAR 0-7009 XREFS 47943 LOC {2 0.083547575 2 0.21984774999999998 2 0.21984774999999998 2 0.3074051292724431 2 0.3074051292724431} PREDS {{258 0 0-8208 {}} {259 0 0-8233 {}}} SUCCS {{258 0 0-9274 {}}} CYCLES {}}
+set a(0-8235) {NAME ACC1:slc(ACC1:acc#224.psp)#45 TYPE READSLICE PAR 0-7009 XREFS 47944 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.968389125} PREDS {{258 0 0-7629 {}}} SUCCS {{258 0 0-8237 {}}} CYCLES {}}
+set a(0-8236) {NAME ACC1:slc(ACC1:acc#228.psp)#45 TYPE READSLICE PAR 0-7009 XREFS 47945 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.968389125} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8237 {}}} CYCLES {}}
+set a(0-8237) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#319 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-7009 XREFS 47946 LOC {1 0.14655495 1 0.7496646499999999 1 0.7496646499999999 1 0.78127548625 1 0.9999999612499999} PREDS {{258 0 0-8235 {}} {259 0 0-8236 {}}} SUCCS {{258 0 0-8239 {}}} CYCLES {}}
+set a(0-8238) {NAME ACC1:slc(ACC1:acc#224.psp#1)#17 TYPE READSLICE PAR 0-7009 XREFS 47947 LOC {1 0.14655495 1 0.244598025 1 0.244598025 2 0.001123275} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-8239 {}}} CYCLES {}}
+set a(0-8239) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#318 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 47948 LOC {1 0.178165825 1 0.781275525 1 0.781275525 1 0.8017482850894753 2 0.021596035089475246} PREDS {{258 0 0-8237 {}} {259 0 0-8238 {}}} SUCCS {{259 0 0-8240 {}}} CYCLES {}}
+set a(0-8240) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,14) AREA_SCORE 330.00 QUANTITY 1 NAME ACC1:mul#57 TYPE MUL DELAY {3.17 ns} LIBRARY_DELAY {3.17 ns} PAR 0-7009 XREFS 47949 LOC {1 0.19863862499999999 1 0.8017483249999999 1 0.8017483249999999 1 0.9999999499999999 2 0.21984769999999995} PREDS {{259 0 0-8239 {}}} SUCCS {{258 0 0-9273 {}}} CYCLES {}}
+set a(0-8241) {NAME slc(acc#20.psp#1)#93 TYPE READSLICE PAR 0-7009 XREFS 47950 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.060871249999999995} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8248 {}}} CYCLES {}}
+set a(0-8242) {NAME slc(acc#20.psp#1)#94 TYPE READSLICE PAR 0-7009 XREFS 47951 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.060871249999999995} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8248 {}}} CYCLES {}}
+set a(0-8243) {NAME slc(acc#20.psp#1)#95 TYPE READSLICE PAR 0-7009 XREFS 47952 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.060871249999999995} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8248 {}}} CYCLES {}}
+set a(0-8244) {NAME slc(acc#20.psp#1)#81 TYPE READSLICE PAR 0-7009 XREFS 47953 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.060871249999999995} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8248 {}}} CYCLES {}}
+set a(0-8245) {NAME ACC1:slc(ACC1:acc#228.psp)#55 TYPE READSLICE PAR 0-7009 XREFS 47954 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.060871249999999995} PREDS {{258 0 0-7331 {}}} SUCCS {{258 0 0-8248 {}}} CYCLES {}}
+set a(0-8246) {NAME ACC1-3:slc(acc#10.psp)#62 TYPE READSLICE PAR 0-7009 XREFS 47955 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.060871249999999995} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8247 {}}} CYCLES {}}
+set a(0-8247) {NAME ACC1-3:exs#37 TYPE SIGNEXTEND PAR 0-7009 XREFS 47956 LOC {1 0.14655495 2 0.060871249999999995 2 0.060871249999999995 2 0.060871249999999995} PREDS {{259 0 0-8246 {}}} SUCCS {{259 0 0-8248 {}}} CYCLES {}}
+set a(0-8248) {NAME ACC1:conc#1117 TYPE CONCATENATE PAR 0-7009 XREFS 47957 LOC {1 0.14655495 2 0.060871249999999995 2 0.060871249999999995 2 0.060871249999999995} PREDS {{258 0 0-8245 {}} {258 0 0-8244 {}} {258 0 0-8243 {}} {258 0 0-8242 {}} {258 0 0-8241 {}} {259 0 0-8247 {}}} SUCCS {{258 0 0-8725 {}}} CYCLES {}}
+set a(0-8249) {NAME ACC1-1:slc(acc.idiv#5)#5 TYPE READSLICE PAR 0-7009 XREFS 47958 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8250 {}}} CYCLES {}}
+set a(0-8250) {NAME ACC1-1:exs#92 TYPE SIGNEXTEND PAR 0-7009 XREFS 47959 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8249 {}}} SUCCS {{259 0 0-8251 {}}} CYCLES {}}
+set a(0-8251) {NAME ACC1:conc#1374 TYPE CONCATENATE PAR 0-7009 XREFS 47960 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8250 {}}} SUCCS {{258 0 0-8256 {}}} CYCLES {}}
+set a(0-8252) {NAME ACC1-1:slc(acc.idiv#5)#7 TYPE READSLICE PAR 0-7009 XREFS 47961 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8253 {}}} CYCLES {}}
+set a(0-8253) {NAME ACC1-1:exs#93 TYPE SIGNEXTEND PAR 0-7009 XREFS 47962 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8252 {}}} SUCCS {{258 0 0-8255 {}}} CYCLES {}}
+set a(0-8254) {NAME ACC1:slc(ACC1:acc#214.psp#2)#5 TYPE READSLICE PAR 0-7009 XREFS 47963 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.43013657499999997} PREDS {{258 0 0-7144 {}}} SUCCS {{259 0 0-8255 {}}} CYCLES {}}
+set a(0-8255) {NAME ACC1:conc#1375 TYPE CONCATENATE PAR 0-7009 XREFS 47964 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8253 {}} {259 0 0-8254 {}}} SUCCS {{259 0 0-8256 {}}} CYCLES {}}
+set a(0-8256) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#458 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47965 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8251 {}} {259 0 0-8255 {}}} SUCCS {{259 0 0-8257 {}}} CYCLES {}}
+set a(0-8257) {NAME ACC1:slc#126 TYPE READSLICE PAR 0-7009 XREFS 47966 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8256 {}}} SUCCS {{258 0 0-8267 {}}} CYCLES {}}
+set a(0-8258) {NAME ACC1-1:slc(acc.idiv#5)#19 TYPE READSLICE PAR 0-7009 XREFS 47967 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8259 {}}} CYCLES {}}
+set a(0-8259) {NAME ACC1-1:exs#99 TYPE SIGNEXTEND PAR 0-7009 XREFS 47968 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8258 {}}} SUCCS {{259 0 0-8260 {}}} CYCLES {}}
+set a(0-8260) {NAME ACC1:conc#1372 TYPE CONCATENATE PAR 0-7009 XREFS 47969 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8259 {}}} SUCCS {{258 0 0-8265 {}}} CYCLES {}}
+set a(0-8261) {NAME ACC1-1:slc(acc.idiv#5)#21 TYPE READSLICE PAR 0-7009 XREFS 47970 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8262 {}}} CYCLES {}}
+set a(0-8262) {NAME ACC1-1:exs#100 TYPE SIGNEXTEND PAR 0-7009 XREFS 47971 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8261 {}}} SUCCS {{258 0 0-8264 {}}} CYCLES {}}
+set a(0-8263) {NAME ACC1:slc(ACC1:acc#214.psp#2)#4 TYPE READSLICE PAR 0-7009 XREFS 47972 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.43013657499999997} PREDS {{258 0 0-7144 {}}} SUCCS {{259 0 0-8264 {}}} CYCLES {}}
+set a(0-8264) {NAME ACC1:conc#1373 TYPE CONCATENATE PAR 0-7009 XREFS 47973 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8262 {}} {259 0 0-8263 {}}} SUCCS {{259 0 0-8265 {}}} CYCLES {}}
+set a(0-8265) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#457 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47974 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8260 {}} {259 0 0-8264 {}}} SUCCS {{259 0 0-8266 {}}} CYCLES {}}
+set a(0-8266) {NAME ACC1:slc#125 TYPE READSLICE PAR 0-7009 XREFS 47975 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8265 {}}} SUCCS {{259 0 0-8267 {}}} CYCLES {}}
+set a(0-8267) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#540 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47976 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8257 {}} {259 0 0-8266 {}}} SUCCS {{258 0 0-8287 {}}} CYCLES {}}
+set a(0-8268) {NAME ACC1-1:slc(acc.idiv#5)#13 TYPE READSLICE PAR 0-7009 XREFS 47977 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8269 {}}} CYCLES {}}
+set a(0-8269) {NAME ACC1-1:exs#96 TYPE SIGNEXTEND PAR 0-7009 XREFS 47978 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8268 {}}} SUCCS {{259 0 0-8270 {}}} CYCLES {}}
+set a(0-8270) {NAME ACC1:conc#1370 TYPE CONCATENATE PAR 0-7009 XREFS 47979 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8269 {}}} SUCCS {{258 0 0-8275 {}}} CYCLES {}}
+set a(0-8271) {NAME ACC1-1:slc(acc.idiv#5)#15 TYPE READSLICE PAR 0-7009 XREFS 47980 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8272 {}}} CYCLES {}}
+set a(0-8272) {NAME ACC1-1:exs#97 TYPE SIGNEXTEND PAR 0-7009 XREFS 47981 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8271 {}}} SUCCS {{258 0 0-8274 {}}} CYCLES {}}
+set a(0-8273) {NAME ACC1:slc(ACC1:acc#214.psp#2) TYPE READSLICE PAR 0-7009 XREFS 47982 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.43013657499999997} PREDS {{258 0 0-7144 {}}} SUCCS {{259 0 0-8274 {}}} CYCLES {}}
+set a(0-8274) {NAME ACC1:conc#1371 TYPE CONCATENATE PAR 0-7009 XREFS 47983 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8272 {}} {259 0 0-8273 {}}} SUCCS {{259 0 0-8275 {}}} CYCLES {}}
+set a(0-8275) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#456 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47984 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8270 {}} {259 0 0-8274 {}}} SUCCS {{259 0 0-8276 {}}} CYCLES {}}
+set a(0-8276) {NAME ACC1:slc#124 TYPE READSLICE PAR 0-7009 XREFS 47985 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8275 {}}} SUCCS {{258 0 0-8286 {}}} CYCLES {}}
+set a(0-8277) {NAME ACC1-1:slc(acc.idiv#5)#17 TYPE READSLICE PAR 0-7009 XREFS 47986 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8278 {}}} CYCLES {}}
+set a(0-8278) {NAME ACC1-1:exs#98 TYPE SIGNEXTEND PAR 0-7009 XREFS 47987 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8277 {}}} SUCCS {{259 0 0-8279 {}}} CYCLES {}}
+set a(0-8279) {NAME ACC1:conc#1368 TYPE CONCATENATE PAR 0-7009 XREFS 47988 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8278 {}}} SUCCS {{258 0 0-8284 {}}} CYCLES {}}
+set a(0-8280) {NAME ACC1-1:slc(acc.idiv#5)#25 TYPE READSLICE PAR 0-7009 XREFS 47989 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8281 {}}} CYCLES {}}
+set a(0-8281) {NAME ACC1-1:exs#102 TYPE SIGNEXTEND PAR 0-7009 XREFS 47990 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8280 {}}} SUCCS {{258 0 0-8283 {}}} CYCLES {}}
+set a(0-8282) {NAME ACC1:slc(acc.imod#6) TYPE READSLICE PAR 0-7009 XREFS 47991 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7612 {}}} SUCCS {{259 0 0-8283 {}}} CYCLES {}}
+set a(0-8283) {NAME ACC1:conc#1369 TYPE CONCATENATE PAR 0-7009 XREFS 47992 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8281 {}} {259 0 0-8282 {}}} SUCCS {{259 0 0-8284 {}}} CYCLES {}}
+set a(0-8284) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#455 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47993 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8279 {}} {259 0 0-8283 {}}} SUCCS {{259 0 0-8285 {}}} CYCLES {}}
+set a(0-8285) {NAME ACC1:slc#123 TYPE READSLICE PAR 0-7009 XREFS 47994 LOC {1 0.40398894999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8284 {}}} SUCCS {{259 0 0-8286 {}}} CYCLES {}}
+set a(0-8286) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#539 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 47995 LOC {1 0.40398894999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8276 {}} {259 0 0-8285 {}}} SUCCS {{259 0 0-8287 {}}} CYCLES {}}
+set a(0-8287) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#585 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 47996 LOC {1 0.451545125 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-8267 {}} {259 0 0-8286 {}}} SUCCS {{258 0 0-8331 {}}} CYCLES {}}
+set a(0-8288) {NAME ACC1-1:slc(acc#25.psp)#46 TYPE READSLICE PAR 0-7009 XREFS 47997 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8289 {}}} CYCLES {}}
+set a(0-8289) {NAME ACC1-1:exs#353 TYPE SIGNEXTEND PAR 0-7009 XREFS 47998 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8288 {}}} SUCCS {{259 0 0-8290 {}}} CYCLES {}}
+set a(0-8290) {NAME ACC1:conc#1366 TYPE CONCATENATE PAR 0-7009 XREFS 47999 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8289 {}}} SUCCS {{258 0 0-8295 {}}} CYCLES {}}
+set a(0-8291) {NAME ACC1-1:slc(acc.idiv#5)#23 TYPE READSLICE PAR 0-7009 XREFS 48000 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8292 {}}} CYCLES {}}
+set a(0-8292) {NAME ACC1-1:exs#101 TYPE SIGNEXTEND PAR 0-7009 XREFS 48001 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8291 {}}} SUCCS {{258 0 0-8294 {}}} CYCLES {}}
+set a(0-8293) {NAME ACC1:slc(ACC1-3:acc#212.psp)#14 TYPE READSLICE PAR 0-7009 XREFS 48002 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.43013657499999997} PREDS {{258 0 0-7594 {}}} SUCCS {{259 0 0-8294 {}}} CYCLES {}}
+set a(0-8294) {NAME ACC1:conc#1367 TYPE CONCATENATE PAR 0-7009 XREFS 48003 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8292 {}} {259 0 0-8293 {}}} SUCCS {{259 0 0-8295 {}}} CYCLES {}}
+set a(0-8295) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#454 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48004 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8290 {}} {259 0 0-8294 {}}} SUCCS {{259 0 0-8296 {}}} CYCLES {}}
+set a(0-8296) {NAME ACC1:slc#122 TYPE READSLICE PAR 0-7009 XREFS 48005 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8295 {}}} SUCCS {{258 0 0-8306 {}}} CYCLES {}}
+set a(0-8297) {NAME ACC1-1:slc(acc.idiv#5)#33 TYPE READSLICE PAR 0-7009 XREFS 48006 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8298 {}}} CYCLES {}}
+set a(0-8298) {NAME ACC1-1:exs#106 TYPE SIGNEXTEND PAR 0-7009 XREFS 48007 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8297 {}}} SUCCS {{259 0 0-8299 {}}} CYCLES {}}
+set a(0-8299) {NAME ACC1:conc#1364 TYPE CONCATENATE PAR 0-7009 XREFS 48008 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8298 {}}} SUCCS {{258 0 0-8304 {}}} CYCLES {}}
+set a(0-8300) {NAME ACC1-1:slc(acc#25.psp)#56 TYPE READSLICE PAR 0-7009 XREFS 48009 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8301 {}}} CYCLES {}}
+set a(0-8301) {NAME ACC1-1:exs#963 TYPE SIGNEXTEND PAR 0-7009 XREFS 48010 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8300 {}}} SUCCS {{258 0 0-8303 {}}} CYCLES {}}
+set a(0-8302) {NAME ACC1:slc(ACC1-3:acc#212.psp)#13 TYPE READSLICE PAR 0-7009 XREFS 48011 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.43013657499999997} PREDS {{258 0 0-7594 {}}} SUCCS {{259 0 0-8303 {}}} CYCLES {}}
+set a(0-8303) {NAME ACC1:conc#1365 TYPE CONCATENATE PAR 0-7009 XREFS 48012 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8301 {}} {259 0 0-8302 {}}} SUCCS {{259 0 0-8304 {}}} CYCLES {}}
+set a(0-8304) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#453 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48013 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8299 {}} {259 0 0-8303 {}}} SUCCS {{259 0 0-8305 {}}} CYCLES {}}
+set a(0-8305) {NAME ACC1:slc#121 TYPE READSLICE PAR 0-7009 XREFS 48014 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8304 {}}} SUCCS {{259 0 0-8306 {}}} CYCLES {}}
+set a(0-8306) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#538 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48015 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8296 {}} {259 0 0-8305 {}}} SUCCS {{258 0 0-8330 {}}} CYCLES {}}
+set a(0-8307) {NAME ACC1-1:slc(acc.idiv#5)#27 TYPE READSLICE PAR 0-7009 XREFS 48016 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8308 {}}} CYCLES {}}
+set a(0-8308) {NAME ACC1-1:exs#103 TYPE SIGNEXTEND PAR 0-7009 XREFS 48017 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8307 {}}} SUCCS {{259 0 0-8309 {}}} CYCLES {}}
+set a(0-8309) {NAME ACC1:conc#1362 TYPE CONCATENATE PAR 0-7009 XREFS 48018 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8308 {}}} SUCCS {{258 0 0-8314 {}}} CYCLES {}}
+set a(0-8310) {NAME ACC1-1:slc(acc.idiv#5)#29 TYPE READSLICE PAR 0-7009 XREFS 48019 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8311 {}}} CYCLES {}}
+set a(0-8311) {NAME ACC1-1:exs#104 TYPE SIGNEXTEND PAR 0-7009 XREFS 48020 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8310 {}}} SUCCS {{258 0 0-8313 {}}} CYCLES {}}
+set a(0-8312) {NAME ACC1:slc(ACC1-3:acc#212.psp) TYPE READSLICE PAR 0-7009 XREFS 48021 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.43013657499999997} PREDS {{258 0 0-7594 {}}} SUCCS {{259 0 0-8313 {}}} CYCLES {}}
+set a(0-8313) {NAME ACC1:conc#1363 TYPE CONCATENATE PAR 0-7009 XREFS 48022 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8311 {}} {259 0 0-8312 {}}} SUCCS {{259 0 0-8314 {}}} CYCLES {}}
+set a(0-8314) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#452 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48023 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8309 {}} {259 0 0-8313 {}}} SUCCS {{259 0 0-8315 {}}} CYCLES {}}
+set a(0-8315) {NAME ACC1:slc#120 TYPE READSLICE PAR 0-7009 XREFS 48024 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8314 {}}} SUCCS {{258 0 0-8329 {}}} CYCLES {}}
+set a(0-8316) {NAME ACC1-3:slc(acc.idiv#1)#17 TYPE READSLICE PAR 0-7009 XREFS 48025 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8317 {}}} CYCLES {}}
+set a(0-8317) {NAME ACC1-3:exs#26 TYPE SIGNEXTEND PAR 0-7009 XREFS 48026 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8316 {}}} SUCCS {{259 0 0-8318 {}}} CYCLES {}}
+set a(0-8318) {NAME ACC1:conc#1360 TYPE CONCATENATE PAR 0-7009 XREFS 48027 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8317 {}}} SUCCS {{258 0 0-8327 {}}} CYCLES {}}
+set a(0-8319) {NAME ACC1-3:slc(acc.idiv#1)#3 TYPE READSLICE PAR 0-7009 XREFS 48028 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8320 {}}} CYCLES {}}
+set a(0-8320) {NAME ACC1-3:exs#19 TYPE SIGNEXTEND PAR 0-7009 XREFS 48029 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8319 {}}} SUCCS {{258 0 0-8326 {}}} CYCLES {}}
+set a(0-8321) {NAME ACC1:slc(acc#25.psp#2)#26 TYPE READSLICE PAR 0-7009 XREFS 48030 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7403 {}}} SUCCS {{258 0 0-8325 {}}} CYCLES {}}
+set a(0-8322) {NAME ACC1-2:slc(acc.imod#23)#1 TYPE READSLICE PAR 0-7009 XREFS 48031 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7467 {}}} SUCCS {{259 0 0-8323 {}}} CYCLES {}}
+set a(0-8323) {NAME ACC1-2:not#188 TYPE NOT PAR 0-7009 XREFS 48032 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8322 {}}} SUCCS {{258 0 0-8325 {}}} CYCLES {}}
+set a(0-8324) {NAME ACC1-2:slc(acc.imod#23)#2 TYPE READSLICE PAR 0-7009 XREFS 48033 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7467 {}}} SUCCS {{259 0 0-8325 {}}} CYCLES {}}
+set a(0-8325) {NAME ACC1-2:and#11 TYPE AND PAR 0-7009 XREFS 48034 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8323 {}} {258 0 0-8321 {}} {259 0 0-8324 {}}} SUCCS {{259 0 0-8326 {}}} CYCLES {}}
+set a(0-8326) {NAME ACC1:conc#1361 TYPE CONCATENATE PAR 0-7009 XREFS 48035 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8320 {}} {259 0 0-8325 {}}} SUCCS {{259 0 0-8327 {}}} CYCLES {}}
+set a(0-8327) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#451 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48036 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8318 {}} {259 0 0-8326 {}}} SUCCS {{259 0 0-8328 {}}} CYCLES {}}
+set a(0-8328) {NAME ACC1:slc#119 TYPE READSLICE PAR 0-7009 XREFS 48037 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8327 {}}} SUCCS {{259 0 0-8329 {}}} CYCLES {}}
+set a(0-8329) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#537 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48038 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8315 {}} {259 0 0-8328 {}}} SUCCS {{259 0 0-8330 {}}} CYCLES {}}
+set a(0-8330) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#584 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48039 LOC {1 0.469524375 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-8306 {}} {259 0 0-8329 {}}} SUCCS {{259 0 0-8331 {}}} CYCLES {}}
+set a(0-8331) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#607 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-7009 XREFS 48040 LOC {1 0.52287145 1 0.578596 1 0.578596 1 0.637195709496936 1 0.637195709496936} PREDS {{258 0 0-8287 {}} {259 0 0-8330 {}}} SUCCS {{258 0 0-8421 {}}} CYCLES {}}
+set a(0-8332) {NAME ACC1-3:slc(acc.idiv#1)#5 TYPE READSLICE PAR 0-7009 XREFS 48041 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8333 {}}} CYCLES {}}
+set a(0-8333) {NAME ACC1-3:exs#20 TYPE SIGNEXTEND PAR 0-7009 XREFS 48042 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8332 {}}} SUCCS {{259 0 0-8334 {}}} CYCLES {}}
+set a(0-8334) {NAME ACC1:conc#1358 TYPE CONCATENATE PAR 0-7009 XREFS 48043 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8333 {}}} SUCCS {{258 0 0-8342 {}}} CYCLES {}}
+set a(0-8335) {NAME ACC1-3:slc(acc.idiv#1)#7 TYPE READSLICE PAR 0-7009 XREFS 48044 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8336 {}}} CYCLES {}}
+set a(0-8336) {NAME ACC1-3:exs#21 TYPE SIGNEXTEND PAR 0-7009 XREFS 48045 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8335 {}}} SUCCS {{258 0 0-8341 {}}} CYCLES {}}
+set a(0-8337) {NAME ACC1-2:slc(acc.imod#23) TYPE READSLICE PAR 0-7009 XREFS 48046 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7467 {}}} SUCCS {{258 0 0-8340 {}}} CYCLES {}}
+set a(0-8338) {NAME ACC1:slc(acc#25.psp#2)#25 TYPE READSLICE PAR 0-7009 XREFS 48047 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8339 {}}} CYCLES {}}
+set a(0-8339) {NAME ACC1-2:not#187 TYPE NOT PAR 0-7009 XREFS 48048 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8338 {}}} SUCCS {{259 0 0-8340 {}}} CYCLES {}}
+set a(0-8340) {NAME ACC1-2:nand#5 TYPE NAND PAR 0-7009 XREFS 48049 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8337 {}} {259 0 0-8339 {}}} SUCCS {{259 0 0-8341 {}}} CYCLES {}}
+set a(0-8341) {NAME ACC1:conc#1359 TYPE CONCATENATE PAR 0-7009 XREFS 48050 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8336 {}} {259 0 0-8340 {}}} SUCCS {{259 0 0-8342 {}}} CYCLES {}}
+set a(0-8342) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#450 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48051 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8334 {}} {259 0 0-8341 {}}} SUCCS {{259 0 0-8343 {}}} CYCLES {}}
+set a(0-8343) {NAME ACC1:slc#118 TYPE READSLICE PAR 0-7009 XREFS 48052 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8342 {}}} SUCCS {{258 0 0-8353 {}}} CYCLES {}}
+set a(0-8344) {NAME ACC1-3:slc(acc#10.psp)#67 TYPE READSLICE PAR 0-7009 XREFS 48053 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8345 {}}} CYCLES {}}
+set a(0-8345) {NAME ACC1-3:exs#52 TYPE SIGNEXTEND PAR 0-7009 XREFS 48054 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8344 {}}} SUCCS {{259 0 0-8346 {}}} CYCLES {}}
+set a(0-8346) {NAME ACC1:conc#1356 TYPE CONCATENATE PAR 0-7009 XREFS 48055 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8345 {}}} SUCCS {{258 0 0-8351 {}}} CYCLES {}}
+set a(0-8347) {NAME ACC1-3:slc(acc#10.psp)#66 TYPE READSLICE PAR 0-7009 XREFS 48056 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8348 {}}} CYCLES {}}
+set a(0-8348) {NAME ACC1-3:exs#53 TYPE SIGNEXTEND PAR 0-7009 XREFS 48057 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8347 {}}} SUCCS {{258 0 0-8350 {}}} CYCLES {}}
+set a(0-8349) {NAME ACC1:slc(acc.imod#43) TYPE READSLICE PAR 0-7009 XREFS 48058 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.43013657499999997} PREDS {{258 0 0-7458 {}}} SUCCS {{259 0 0-8350 {}}} CYCLES {}}
+set a(0-8350) {NAME ACC1:conc#1357 TYPE CONCATENATE PAR 0-7009 XREFS 48059 LOC {1 0.3471661 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8348 {}} {259 0 0-8349 {}}} SUCCS {{259 0 0-8351 {}}} CYCLES {}}
+set a(0-8351) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#449 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48060 LOC {1 0.3471661 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8346 {}} {259 0 0-8350 {}}} SUCCS {{259 0 0-8352 {}}} CYCLES {}}
+set a(0-8352) {NAME ACC1:slc#117 TYPE READSLICE PAR 0-7009 XREFS 48061 LOC {1 0.39472227499999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8351 {}}} SUCCS {{259 0 0-8353 {}}} CYCLES {}}
+set a(0-8353) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#536 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48062 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8343 {}} {259 0 0-8352 {}}} SUCCS {{258 0 0-8373 {}}} CYCLES {}}
+set a(0-8354) {NAME ACC1-3:slc(acc#10.psp)#65 TYPE READSLICE PAR 0-7009 XREFS 48063 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8355 {}}} CYCLES {}}
+set a(0-8355) {NAME ACC1-3:exs#40 TYPE SIGNEXTEND PAR 0-7009 XREFS 48064 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8354 {}}} SUCCS {{259 0 0-8356 {}}} CYCLES {}}
+set a(0-8356) {NAME ACC1:conc#1354 TYPE CONCATENATE PAR 0-7009 XREFS 48065 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8355 {}}} SUCCS {{258 0 0-8361 {}}} CYCLES {}}
+set a(0-8357) {NAME ACC1-3:slc(acc#10.psp)#64 TYPE READSLICE PAR 0-7009 XREFS 48066 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8358 {}}} CYCLES {}}
+set a(0-8358) {NAME ACC1-3:exs#41 TYPE SIGNEXTEND PAR 0-7009 XREFS 48067 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8357 {}}} SUCCS {{258 0 0-8360 {}}} CYCLES {}}
+set a(0-8359) {NAME ACC1:slc(ACC1-2:acc#208.psp)#11 TYPE READSLICE PAR 0-7009 XREFS 48068 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7440 {}}} SUCCS {{259 0 0-8360 {}}} CYCLES {}}
+set a(0-8360) {NAME ACC1:conc#1355 TYPE CONCATENATE PAR 0-7009 XREFS 48069 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8358 {}} {259 0 0-8359 {}}} SUCCS {{259 0 0-8361 {}}} CYCLES {}}
+set a(0-8361) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#448 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48070 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8356 {}} {259 0 0-8360 {}}} SUCCS {{259 0 0-8362 {}}} CYCLES {}}
+set a(0-8362) {NAME ACC1:slc#116 TYPE READSLICE PAR 0-7009 XREFS 48071 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8361 {}}} SUCCS {{258 0 0-8372 {}}} CYCLES {}}
+set a(0-8363) {NAME ACC1-3:slc(acc.psp)#65 TYPE READSLICE PAR 0-7009 XREFS 48072 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8364 {}}} CYCLES {}}
+set a(0-8364) {NAME ACC1-3:exs TYPE SIGNEXTEND PAR 0-7009 XREFS 48073 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8363 {}}} SUCCS {{259 0 0-8365 {}}} CYCLES {}}
+set a(0-8365) {NAME ACC1:conc#1352 TYPE CONCATENATE PAR 0-7009 XREFS 48074 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8364 {}}} SUCCS {{258 0 0-8370 {}}} CYCLES {}}
+set a(0-8366) {NAME ACC1-3:slc(acc.idiv)#27 TYPE READSLICE PAR 0-7009 XREFS 48075 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8367 {}}} CYCLES {}}
+set a(0-8367) {NAME ACC1-3:exs#13 TYPE SIGNEXTEND PAR 0-7009 XREFS 48076 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8366 {}}} SUCCS {{258 0 0-8369 {}}} CYCLES {}}
+set a(0-8368) {NAME ACC1:slc(ACC1-2:acc#208.psp)#10 TYPE READSLICE PAR 0-7009 XREFS 48077 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7440 {}}} SUCCS {{259 0 0-8369 {}}} CYCLES {}}
+set a(0-8369) {NAME ACC1:conc#1353 TYPE CONCATENATE PAR 0-7009 XREFS 48078 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8367 {}} {259 0 0-8368 {}}} SUCCS {{259 0 0-8370 {}}} CYCLES {}}
+set a(0-8370) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#447 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48079 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8365 {}} {259 0 0-8369 {}}} SUCCS {{259 0 0-8371 {}}} CYCLES {}}
+set a(0-8371) {NAME ACC1:slc#115 TYPE READSLICE PAR 0-7009 XREFS 48080 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8370 {}}} SUCCS {{259 0 0-8372 {}}} CYCLES {}}
+set a(0-8372) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#535 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48081 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8362 {}} {259 0 0-8371 {}}} SUCCS {{259 0 0-8373 {}}} CYCLES {}}
+set a(0-8373) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#583 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48082 LOC {1 0.469524375 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-8353 {}} {259 0 0-8372 {}}} SUCCS {{258 0 0-8420 {}}} CYCLES {}}
+set a(0-8374) {NAME ACC1-3:slc(acc.idiv)#29 TYPE READSLICE PAR 0-7009 XREFS 48083 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8375 {}}} CYCLES {}}
+set a(0-8375) {NAME ACC1-3:exs#14 TYPE SIGNEXTEND PAR 0-7009 XREFS 48084 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8374 {}}} SUCCS {{259 0 0-8376 {}}} CYCLES {}}
+set a(0-8376) {NAME ACC1:conc#1350 TYPE CONCATENATE PAR 0-7009 XREFS 48085 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8375 {}}} SUCCS {{258 0 0-8381 {}}} CYCLES {}}
+set a(0-8377) {NAME ACC1-3:slc(acc.idiv#1)#11 TYPE READSLICE PAR 0-7009 XREFS 48086 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8378 {}}} CYCLES {}}
+set a(0-8378) {NAME ACC1-3:exs#23 TYPE SIGNEXTEND PAR 0-7009 XREFS 48087 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8377 {}}} SUCCS {{258 0 0-8380 {}}} CYCLES {}}
+set a(0-8379) {NAME ACC1:slc(ACC1-2:acc#208.psp) TYPE READSLICE PAR 0-7009 XREFS 48088 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7440 {}}} SUCCS {{259 0 0-8380 {}}} CYCLES {}}
+set a(0-8380) {NAME ACC1:conc#1351 TYPE CONCATENATE PAR 0-7009 XREFS 48089 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8378 {}} {259 0 0-8379 {}}} SUCCS {{259 0 0-8381 {}}} CYCLES {}}
+set a(0-8381) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#446 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48090 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8376 {}} {259 0 0-8380 {}}} SUCCS {{259 0 0-8382 {}}} CYCLES {}}
+set a(0-8382) {NAME ACC1:slc#114 TYPE READSLICE PAR 0-7009 XREFS 48091 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8381 {}}} SUCCS {{258 0 0-8396 {}}} CYCLES {}}
+set a(0-8383) {NAME ACC1-3:slc(acc.idiv#1)#1 TYPE READSLICE PAR 0-7009 XREFS 48092 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8384 {}}} CYCLES {}}
+set a(0-8384) {NAME ACC1-3:exs#18 TYPE SIGNEXTEND PAR 0-7009 XREFS 48093 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8383 {}}} SUCCS {{259 0 0-8385 {}}} CYCLES {}}
+set a(0-8385) {NAME ACC1:conc#1348 TYPE CONCATENATE PAR 0-7009 XREFS 48094 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8384 {}}} SUCCS {{258 0 0-8394 {}}} CYCLES {}}
+set a(0-8386) {NAME ACC1-3:slc(acc.idiv#1)#33 TYPE READSLICE PAR 0-7009 XREFS 48095 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8387 {}}} CYCLES {}}
+set a(0-8387) {NAME ACC1-3:exs#34 TYPE SIGNEXTEND PAR 0-7009 XREFS 48096 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8386 {}}} SUCCS {{258 0 0-8393 {}}} CYCLES {}}
+set a(0-8388) {NAME ACC1:slc(acc#5.psp#2)#30 TYPE READSLICE PAR 0-7009 XREFS 48097 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7331 {}}} SUCCS {{258 0 0-8392 {}}} CYCLES {}}
+set a(0-8389) {NAME ACC1-2:slc(acc.imod#7)#1 TYPE READSLICE PAR 0-7009 XREFS 48098 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7395 {}}} SUCCS {{259 0 0-8390 {}}} CYCLES {}}
+set a(0-8390) {NAME ACC1-2:not#60 TYPE NOT PAR 0-7009 XREFS 48099 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8389 {}}} SUCCS {{258 0 0-8392 {}}} CYCLES {}}
+set a(0-8391) {NAME ACC1-2:slc(acc.imod#7)#2 TYPE READSLICE PAR 0-7009 XREFS 48100 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7395 {}}} SUCCS {{259 0 0-8392 {}}} CYCLES {}}
+set a(0-8392) {NAME ACC1-2:and#3 TYPE AND PAR 0-7009 XREFS 48101 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8390 {}} {258 0 0-8388 {}} {259 0 0-8391 {}}} SUCCS {{259 0 0-8393 {}}} CYCLES {}}
+set a(0-8393) {NAME ACC1:conc#1349 TYPE CONCATENATE PAR 0-7009 XREFS 48102 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8387 {}} {259 0 0-8392 {}}} SUCCS {{259 0 0-8394 {}}} CYCLES {}}
+set a(0-8394) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#445 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48103 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8385 {}} {259 0 0-8393 {}}} SUCCS {{259 0 0-8395 {}}} CYCLES {}}
+set a(0-8395) {NAME ACC1:slc#113 TYPE READSLICE PAR 0-7009 XREFS 48104 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8394 {}}} SUCCS {{259 0 0-8396 {}}} CYCLES {}}
+set a(0-8396) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#534 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48105 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8382 {}} {259 0 0-8395 {}}} SUCCS {{258 0 0-8419 {}}} CYCLES {}}
+set a(0-8397) {NAME ACC1-3:slc(acc.idiv#1)#35 TYPE READSLICE PAR 0-7009 XREFS 48106 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8398 {}}} CYCLES {}}
+set a(0-8398) {NAME ACC1-3:exs#35 TYPE SIGNEXTEND PAR 0-7009 XREFS 48107 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8397 {}}} SUCCS {{259 0 0-8399 {}}} CYCLES {}}
+set a(0-8399) {NAME ACC1:conc#1346 TYPE CONCATENATE PAR 0-7009 XREFS 48108 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8398 {}}} SUCCS {{258 0 0-8407 {}}} CYCLES {}}
+set a(0-8400) {NAME ACC1-3:slc(acc.idiv#1)#9 TYPE READSLICE PAR 0-7009 XREFS 48109 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8401 {}}} CYCLES {}}
+set a(0-8401) {NAME ACC1-3:exs#22 TYPE SIGNEXTEND PAR 0-7009 XREFS 48110 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8400 {}}} SUCCS {{258 0 0-8406 {}}} CYCLES {}}
+set a(0-8402) {NAME ACC1-2:slc(acc.imod#7) TYPE READSLICE PAR 0-7009 XREFS 48111 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7395 {}}} SUCCS {{258 0 0-8405 {}}} CYCLES {}}
+set a(0-8403) {NAME ACC1:slc(acc#5.psp#2)#29 TYPE READSLICE PAR 0-7009 XREFS 48112 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8404 {}}} CYCLES {}}
+set a(0-8404) {NAME ACC1-2:not#59 TYPE NOT PAR 0-7009 XREFS 48113 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8403 {}}} SUCCS {{259 0 0-8405 {}}} CYCLES {}}
+set a(0-8405) {NAME ACC1-2:nand#1 TYPE NAND PAR 0-7009 XREFS 48114 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8402 {}} {259 0 0-8404 {}}} SUCCS {{259 0 0-8406 {}}} CYCLES {}}
+set a(0-8406) {NAME ACC1:conc#1347 TYPE CONCATENATE PAR 0-7009 XREFS 48115 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8401 {}} {259 0 0-8405 {}}} SUCCS {{259 0 0-8407 {}}} CYCLES {}}
+set a(0-8407) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#444 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48116 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8399 {}} {259 0 0-8406 {}}} SUCCS {{259 0 0-8408 {}}} CYCLES {}}
+set a(0-8408) {NAME ACC1:slc#112 TYPE READSLICE PAR 0-7009 XREFS 48117 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8407 {}}} SUCCS {{258 0 0-8418 {}}} CYCLES {}}
+set a(0-8409) {NAME ACC1-1:slc(acc.idiv#1)#33 TYPE READSLICE PAR 0-7009 XREFS 48118 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8410 {}}} CYCLES {}}
+set a(0-8410) {NAME ACC1-1:exs#34 TYPE SIGNEXTEND PAR 0-7009 XREFS 48119 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8409 {}}} SUCCS {{259 0 0-8411 {}}} CYCLES {}}
+set a(0-8411) {NAME ACC1:conc#1342 TYPE CONCATENATE PAR 0-7009 XREFS 48120 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8410 {}}} SUCCS {{258 0 0-8416 {}}} CYCLES {}}
+set a(0-8412) {NAME ACC1-1:slc(acc.idiv#1)#35 TYPE READSLICE PAR 0-7009 XREFS 48121 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8413 {}}} CYCLES {}}
+set a(0-8413) {NAME ACC1-1:exs#35 TYPE SIGNEXTEND PAR 0-7009 XREFS 48122 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8412 {}}} SUCCS {{258 0 0-8415 {}}} CYCLES {}}
+set a(0-8414) {NAME ACC1:slc(ACC1-2:acc#212.psp)#11 TYPE READSLICE PAR 0-7009 XREFS 48123 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7368 {}}} SUCCS {{259 0 0-8415 {}}} CYCLES {}}
+set a(0-8415) {NAME ACC1:conc#1343 TYPE CONCATENATE PAR 0-7009 XREFS 48124 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8413 {}} {259 0 0-8414 {}}} SUCCS {{259 0 0-8416 {}}} CYCLES {}}
+set a(0-8416) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#442 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48125 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8411 {}} {259 0 0-8415 {}}} SUCCS {{259 0 0-8417 {}}} CYCLES {}}
+set a(0-8417) {NAME ACC1:slc#110 TYPE READSLICE PAR 0-7009 XREFS 48126 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8416 {}}} SUCCS {{259 0 0-8418 {}}} CYCLES {}}
+set a(0-8418) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#533 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48127 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8408 {}} {259 0 0-8417 {}}} SUCCS {{259 0 0-8419 {}}} CYCLES {}}
+set a(0-8419) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#582 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48128 LOC {1 0.469524375 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-8396 {}} {259 0 0-8418 {}}} SUCCS {{259 0 0-8420 {}}} CYCLES {}}
+set a(0-8420) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#606 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-7009 XREFS 48129 LOC {1 0.52287145 1 0.578596 1 0.578596 1 0.637195709496936 1 0.637195709496936} PREDS {{258 0 0-8373 {}} {259 0 0-8419 {}}} SUCCS {{259 0 0-8421 {}}} CYCLES {}}
+set a(0-8421) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#623 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-7009 XREFS 48130 LOC {1 0.5814712 1 0.63719575 1 0.63719575 1 0.7007077234103024 1 0.7007077234103024} PREDS {{258 0 0-8331 {}} {259 0 0-8420 {}}} SUCCS {{258 0 0-8614 {}}} CYCLES {}}
+set a(0-8422) {NAME ACC1-1:slc(acc.idiv#1)#9 TYPE READSLICE PAR 0-7009 XREFS 48131 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8423 {}}} CYCLES {}}
+set a(0-8423) {NAME ACC1-1:exs#22 TYPE SIGNEXTEND PAR 0-7009 XREFS 48132 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8422 {}}} SUCCS {{259 0 0-8424 {}}} CYCLES {}}
+set a(0-8424) {NAME ACC1:conc#1340 TYPE CONCATENATE PAR 0-7009 XREFS 48133 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8423 {}}} SUCCS {{258 0 0-8429 {}}} CYCLES {}}
+set a(0-8425) {NAME ACC1-1:slc(acc.idiv#1)#11 TYPE READSLICE PAR 0-7009 XREFS 48134 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8426 {}}} CYCLES {}}
+set a(0-8426) {NAME ACC1-1:exs#23 TYPE SIGNEXTEND PAR 0-7009 XREFS 48135 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8425 {}}} SUCCS {{258 0 0-8428 {}}} CYCLES {}}
+set a(0-8427) {NAME ACC1:slc(ACC1-2:acc#212.psp)#10 TYPE READSLICE PAR 0-7009 XREFS 48136 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7368 {}}} SUCCS {{259 0 0-8428 {}}} CYCLES {}}
+set a(0-8428) {NAME ACC1:conc#1341 TYPE CONCATENATE PAR 0-7009 XREFS 48137 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8426 {}} {259 0 0-8427 {}}} SUCCS {{259 0 0-8429 {}}} CYCLES {}}
+set a(0-8429) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#441 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48138 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8424 {}} {259 0 0-8428 {}}} SUCCS {{259 0 0-8430 {}}} CYCLES {}}
+set a(0-8430) {NAME ACC1:slc#109 TYPE READSLICE PAR 0-7009 XREFS 48139 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8429 {}}} SUCCS {{258 0 0-8440 {}}} CYCLES {}}
+set a(0-8431) {NAME ACC1-1:slc(acc.idiv#1)#1 TYPE READSLICE PAR 0-7009 XREFS 48140 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8432 {}}} CYCLES {}}
+set a(0-8432) {NAME ACC1-1:exs#18 TYPE SIGNEXTEND PAR 0-7009 XREFS 48141 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8431 {}}} SUCCS {{259 0 0-8433 {}}} CYCLES {}}
+set a(0-8433) {NAME ACC1:conc#1338 TYPE CONCATENATE PAR 0-7009 XREFS 48142 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8432 {}}} SUCCS {{258 0 0-8438 {}}} CYCLES {}}
+set a(0-8434) {NAME ACC1-1:slc(acc.idiv#1)#3 TYPE READSLICE PAR 0-7009 XREFS 48143 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8435 {}}} CYCLES {}}
+set a(0-8435) {NAME ACC1-1:exs#19 TYPE SIGNEXTEND PAR 0-7009 XREFS 48144 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8434 {}}} SUCCS {{258 0 0-8437 {}}} CYCLES {}}
+set a(0-8436) {NAME ACC1:slc(ACC1-2:acc#212.psp) TYPE READSLICE PAR 0-7009 XREFS 48145 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7368 {}}} SUCCS {{259 0 0-8437 {}}} CYCLES {}}
+set a(0-8437) {NAME ACC1:conc#1339 TYPE CONCATENATE PAR 0-7009 XREFS 48146 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8435 {}} {259 0 0-8436 {}}} SUCCS {{259 0 0-8438 {}}} CYCLES {}}
+set a(0-8438) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#440 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48147 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8433 {}} {259 0 0-8437 {}}} SUCCS {{259 0 0-8439 {}}} CYCLES {}}
+set a(0-8439) {NAME ACC1:slc#108 TYPE READSLICE PAR 0-7009 XREFS 48148 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8438 {}}} SUCCS {{259 0 0-8440 {}}} CYCLES {}}
+set a(0-8440) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#532 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48149 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8430 {}} {259 0 0-8439 {}}} SUCCS {{258 0 0-8467 {}}} CYCLES {}}
+set a(0-8441) {NAME ACC1-1:slc(acc.idiv#1)#5 TYPE READSLICE PAR 0-7009 XREFS 48150 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8442 {}}} CYCLES {}}
+set a(0-8442) {NAME ACC1-1:exs#20 TYPE SIGNEXTEND PAR 0-7009 XREFS 48151 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8441 {}}} SUCCS {{259 0 0-8443 {}}} CYCLES {}}
+set a(0-8443) {NAME ACC1:conc#1336 TYPE CONCATENATE PAR 0-7009 XREFS 48152 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8442 {}}} SUCCS {{258 0 0-8452 {}}} CYCLES {}}
+set a(0-8444) {NAME ACC1-1:slc(acc.idiv#1)#7 TYPE READSLICE PAR 0-7009 XREFS 48153 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8445 {}}} CYCLES {}}
+set a(0-8445) {NAME ACC1-1:exs#21 TYPE SIGNEXTEND PAR 0-7009 XREFS 48154 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8444 {}}} SUCCS {{258 0 0-8451 {}}} CYCLES {}}
+set a(0-8446) {NAME ACC1-3:slc(acc#10.psp)#51 TYPE READSLICE PAR 0-7009 XREFS 48155 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7629 {}}} SUCCS {{258 0 0-8450 {}}} CYCLES {}}
+set a(0-8447) {NAME ACC1-3:slc(acc.imod#11)#1 TYPE READSLICE PAR 0-7009 XREFS 48156 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7693 {}}} SUCCS {{259 0 0-8448 {}}} CYCLES {}}
+set a(0-8448) {NAME ACC1-3:not#92 TYPE NOT PAR 0-7009 XREFS 48157 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8447 {}}} SUCCS {{258 0 0-8450 {}}} CYCLES {}}
+set a(0-8449) {NAME ACC1-3:slc(acc.imod#11)#2 TYPE READSLICE PAR 0-7009 XREFS 48158 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7693 {}}} SUCCS {{259 0 0-8450 {}}} CYCLES {}}
+set a(0-8450) {NAME ACC1-3:and#5 TYPE AND PAR 0-7009 XREFS 48159 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8448 {}} {258 0 0-8446 {}} {259 0 0-8449 {}}} SUCCS {{259 0 0-8451 {}}} CYCLES {}}
+set a(0-8451) {NAME ACC1:conc#1337 TYPE CONCATENATE PAR 0-7009 XREFS 48160 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8445 {}} {259 0 0-8450 {}}} SUCCS {{259 0 0-8452 {}}} CYCLES {}}
+set a(0-8452) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#439 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48161 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8443 {}} {259 0 0-8451 {}}} SUCCS {{259 0 0-8453 {}}} CYCLES {}}
+set a(0-8453) {NAME ACC1:slc#107 TYPE READSLICE PAR 0-7009 XREFS 48162 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8452 {}}} SUCCS {{258 0 0-8466 {}}} CYCLES {}}
+set a(0-8454) {NAME ACC1-1:slc(acc.idiv#1)#15 TYPE READSLICE PAR 0-7009 XREFS 48163 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8455 {}}} CYCLES {}}
+set a(0-8455) {NAME ACC1-1:exs#25 TYPE SIGNEXTEND PAR 0-7009 XREFS 48164 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8454 {}}} SUCCS {{259 0 0-8456 {}}} CYCLES {}}
+set a(0-8456) {NAME ACC1:conc#1334 TYPE CONCATENATE PAR 0-7009 XREFS 48165 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8455 {}}} SUCCS {{258 0 0-8464 {}}} CYCLES {}}
+set a(0-8457) {NAME ACC1-1:slc(acc.idiv#1)#17 TYPE READSLICE PAR 0-7009 XREFS 48166 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8458 {}}} CYCLES {}}
+set a(0-8458) {NAME ACC1-1:exs#26 TYPE SIGNEXTEND PAR 0-7009 XREFS 48167 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8457 {}}} SUCCS {{258 0 0-8463 {}}} CYCLES {}}
+set a(0-8459) {NAME ACC1-3:slc(acc.imod#11) TYPE READSLICE PAR 0-7009 XREFS 48168 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7693 {}}} SUCCS {{258 0 0-8462 {}}} CYCLES {}}
+set a(0-8460) {NAME ACC1-3:slc(acc#10.psp)#50 TYPE READSLICE PAR 0-7009 XREFS 48169 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8461 {}}} CYCLES {}}
+set a(0-8461) {NAME ACC1-3:not#91 TYPE NOT PAR 0-7009 XREFS 48170 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8460 {}}} SUCCS {{259 0 0-8462 {}}} CYCLES {}}
+set a(0-8462) {NAME ACC1-3:nand#2 TYPE NAND PAR 0-7009 XREFS 48171 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8459 {}} {259 0 0-8461 {}}} SUCCS {{259 0 0-8463 {}}} CYCLES {}}
+set a(0-8463) {NAME ACC1:conc#1335 TYPE CONCATENATE PAR 0-7009 XREFS 48172 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8458 {}} {259 0 0-8462 {}}} SUCCS {{259 0 0-8464 {}}} CYCLES {}}
+set a(0-8464) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#438 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48173 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8456 {}} {259 0 0-8463 {}}} SUCCS {{259 0 0-8465 {}}} CYCLES {}}
+set a(0-8465) {NAME ACC1:slc#106 TYPE READSLICE PAR 0-7009 XREFS 48174 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8464 {}}} SUCCS {{259 0 0-8466 {}}} CYCLES {}}
+set a(0-8466) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#531 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48175 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8453 {}} {259 0 0-8465 {}}} SUCCS {{259 0 0-8467 {}}} CYCLES {}}
+set a(0-8467) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#581 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48176 LOC {1 0.469524375 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-8440 {}} {259 0 0-8466 {}}} SUCCS {{258 0 0-8507 {}}} CYCLES {}}
+set a(0-8468) {NAME ACC1-1:slc(acc.idiv#1)#13 TYPE READSLICE PAR 0-7009 XREFS 48177 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8469 {}}} CYCLES {}}
+set a(0-8469) {NAME ACC1-1:exs#24 TYPE SIGNEXTEND PAR 0-7009 XREFS 48178 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8468 {}}} SUCCS {{259 0 0-8470 {}}} CYCLES {}}
+set a(0-8470) {NAME ACC1:conc#1332 TYPE CONCATENATE PAR 0-7009 XREFS 48179 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8469 {}}} SUCCS {{258 0 0-8475 {}}} CYCLES {}}
+set a(0-8471) {NAME ACC1-1:slc(acc.idiv#1)#23 TYPE READSLICE PAR 0-7009 XREFS 48180 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8472 {}}} CYCLES {}}
+set a(0-8472) {NAME ACC1-1:exs#29 TYPE SIGNEXTEND PAR 0-7009 XREFS 48181 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8471 {}}} SUCCS {{258 0 0-8474 {}}} CYCLES {}}
+set a(0-8473) {NAME ACC1:slc(acc.imod#10) TYPE READSLICE PAR 0-7009 XREFS 48182 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.43013657499999997} PREDS {{258 0 0-7684 {}}} SUCCS {{259 0 0-8474 {}}} CYCLES {}}
+set a(0-8474) {NAME ACC1:conc#1333 TYPE CONCATENATE PAR 0-7009 XREFS 48183 LOC {1 0.3471661 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8472 {}} {259 0 0-8473 {}}} SUCCS {{259 0 0-8475 {}}} CYCLES {}}
+set a(0-8475) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#437 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48184 LOC {1 0.3471661 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8470 {}} {259 0 0-8474 {}}} SUCCS {{259 0 0-8476 {}}} CYCLES {}}
+set a(0-8476) {NAME ACC1:slc#105 TYPE READSLICE PAR 0-7009 XREFS 48185 LOC {1 0.39472227499999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8475 {}}} SUCCS {{258 0 0-8486 {}}} CYCLES {}}
+set a(0-8477) {NAME ACC1-1:slc(acc.idiv#1)#19 TYPE READSLICE PAR 0-7009 XREFS 48186 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8478 {}}} CYCLES {}}
+set a(0-8478) {NAME ACC1-1:exs#27 TYPE SIGNEXTEND PAR 0-7009 XREFS 48187 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8477 {}}} SUCCS {{259 0 0-8479 {}}} CYCLES {}}
+set a(0-8479) {NAME ACC1:conc#1330 TYPE CONCATENATE PAR 0-7009 XREFS 48188 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8478 {}}} SUCCS {{258 0 0-8484 {}}} CYCLES {}}
+set a(0-8480) {NAME ACC1-1:slc(acc.idiv#1)#21 TYPE READSLICE PAR 0-7009 XREFS 48189 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8481 {}}} CYCLES {}}
+set a(0-8481) {NAME ACC1-1:exs#28 TYPE SIGNEXTEND PAR 0-7009 XREFS 48190 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8480 {}}} SUCCS {{258 0 0-8483 {}}} CYCLES {}}
+set a(0-8482) {NAME ACC1:slc(ACC1:acc#214.psp#1)#11 TYPE READSLICE PAR 0-7009 XREFS 48191 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7666 {}}} SUCCS {{259 0 0-8483 {}}} CYCLES {}}
+set a(0-8483) {NAME ACC1:conc#1331 TYPE CONCATENATE PAR 0-7009 XREFS 48192 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8481 {}} {259 0 0-8482 {}}} SUCCS {{259 0 0-8484 {}}} CYCLES {}}
+set a(0-8484) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#436 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48193 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8479 {}} {259 0 0-8483 {}}} SUCCS {{259 0 0-8485 {}}} CYCLES {}}
+set a(0-8485) {NAME ACC1:slc#104 TYPE READSLICE PAR 0-7009 XREFS 48194 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8484 {}}} SUCCS {{259 0 0-8486 {}}} CYCLES {}}
+set a(0-8486) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#530 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48195 LOC {1 0.39472227499999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8476 {}} {259 0 0-8485 {}}} SUCCS {{258 0 0-8506 {}}} CYCLES {}}
+set a(0-8487) {NAME ACC1-1:slc(acc.idiv#1)#31 TYPE READSLICE PAR 0-7009 XREFS 48196 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8488 {}}} CYCLES {}}
+set a(0-8488) {NAME ACC1-1:exs#33 TYPE SIGNEXTEND PAR 0-7009 XREFS 48197 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8487 {}}} SUCCS {{259 0 0-8489 {}}} CYCLES {}}
+set a(0-8489) {NAME ACC1:conc#1328 TYPE CONCATENATE PAR 0-7009 XREFS 48198 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8488 {}}} SUCCS {{258 0 0-8494 {}}} CYCLES {}}
+set a(0-8490) {NAME ACC1-1:slc(acc#5.psp)#65 TYPE READSLICE PAR 0-7009 XREFS 48199 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8491 {}}} CYCLES {}}
+set a(0-8491) {NAME ACC1-1:exs#1031 TYPE SIGNEXTEND PAR 0-7009 XREFS 48200 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8490 {}}} SUCCS {{258 0 0-8493 {}}} CYCLES {}}
+set a(0-8492) {NAME ACC1:slc(ACC1:acc#214.psp#1)#10 TYPE READSLICE PAR 0-7009 XREFS 48201 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7666 {}}} SUCCS {{259 0 0-8493 {}}} CYCLES {}}
+set a(0-8493) {NAME ACC1:conc#1329 TYPE CONCATENATE PAR 0-7009 XREFS 48202 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8491 {}} {259 0 0-8492 {}}} SUCCS {{259 0 0-8494 {}}} CYCLES {}}
+set a(0-8494) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#435 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48203 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8489 {}} {259 0 0-8493 {}}} SUCCS {{259 0 0-8495 {}}} CYCLES {}}
+set a(0-8495) {NAME ACC1:slc#103 TYPE READSLICE PAR 0-7009 XREFS 48204 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8494 {}}} SUCCS {{258 0 0-8505 {}}} CYCLES {}}
+set a(0-8496) {NAME ACC1-1:slc(acc.idiv#1)#27 TYPE READSLICE PAR 0-7009 XREFS 48205 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8497 {}}} CYCLES {}}
+set a(0-8497) {NAME ACC1-1:exs#31 TYPE SIGNEXTEND PAR 0-7009 XREFS 48206 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8496 {}}} SUCCS {{259 0 0-8498 {}}} CYCLES {}}
+set a(0-8498) {NAME ACC1:conc#1326 TYPE CONCATENATE PAR 0-7009 XREFS 48207 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8497 {}}} SUCCS {{258 0 0-8503 {}}} CYCLES {}}
+set a(0-8499) {NAME ACC1-1:slc(acc.idiv#1)#29 TYPE READSLICE PAR 0-7009 XREFS 48208 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8500 {}}} CYCLES {}}
+set a(0-8500) {NAME ACC1-1:exs#32 TYPE SIGNEXTEND PAR 0-7009 XREFS 48209 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8499 {}}} SUCCS {{258 0 0-8502 {}}} CYCLES {}}
+set a(0-8501) {NAME ACC1:slc(ACC1:acc#214.psp#1) TYPE READSLICE PAR 0-7009 XREFS 48210 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7666 {}}} SUCCS {{259 0 0-8502 {}}} CYCLES {}}
+set a(0-8502) {NAME ACC1:conc#1327 TYPE CONCATENATE PAR 0-7009 XREFS 48211 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8500 {}} {259 0 0-8501 {}}} SUCCS {{259 0 0-8503 {}}} CYCLES {}}
+set a(0-8503) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#434 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48212 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8498 {}} {259 0 0-8502 {}}} SUCCS {{259 0 0-8504 {}}} CYCLES {}}
+set a(0-8504) {NAME ACC1:slc#102 TYPE READSLICE PAR 0-7009 XREFS 48213 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8503 {}}} SUCCS {{259 0 0-8505 {}}} CYCLES {}}
+set a(0-8505) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#529 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48214 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8495 {}} {259 0 0-8504 {}}} SUCCS {{259 0 0-8506 {}}} CYCLES {}}
+set a(0-8506) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#580 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48215 LOC {1 0.44227845 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-8486 {}} {259 0 0-8505 {}}} SUCCS {{259 0 0-8507 {}}} CYCLES {}}
+set a(0-8507) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#605 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-7009 XREFS 48216 LOC {1 0.52287145 1 0.578596 1 0.578596 1 0.637195709496936 1 0.637195709496936} PREDS {{258 0 0-8467 {}} {259 0 0-8506 {}}} SUCCS {{258 0 0-8613 {}}} CYCLES {}}
+set a(0-8508) {NAME ACC1:slc(ACC1:acc#227.psp)#56 TYPE READSLICE PAR 0-7009 XREFS 48217 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{258 0 0-8510 {}}} CYCLES {}}
+set a(0-8509) {NAME ACC1:slc(ACC1:acc#227.psp)#57 TYPE READSLICE PAR 0-7009 XREFS 48218 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8510 {}}} CYCLES {}}
+set a(0-8510) {NAME ACC1:conc#1324 TYPE CONCATENATE PAR 0-7009 XREFS 48219 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8508 {}} {259 0 0-8509 {}}} SUCCS {{259 0 0-8511 {}}} CYCLES {}}
+set a(0-8511) {NAME ACC1:conc TYPE CONCATENATE PAR 0-7009 XREFS 48220 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8510 {}}} SUCCS {{258 0 0-8521 {}}} CYCLES {}}
+set a(0-8512) {NAME ACC1:slc(acc.psp#1)#55 TYPE READSLICE PAR 0-7009 XREFS 48221 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7475 {}}} SUCCS {{258 0 0-8514 {}}} CYCLES {}}
+set a(0-8513) {NAME ACC1:slc(ACC1:acc#227.psp)#58 TYPE READSLICE PAR 0-7009 XREFS 48222 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8514 {}}} CYCLES {}}
+set a(0-8514) {NAME ACC1:conc#1070 TYPE CONCATENATE PAR 0-7009 XREFS 48223 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8512 {}} {259 0 0-8513 {}}} SUCCS {{258 0 0-8520 {}}} CYCLES {}}
+set a(0-8515) {NAME ACC1-3:slc(acc.idiv)#45 TYPE READSLICE PAR 0-7009 XREFS 48224 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7475 {}}} SUCCS {{258 0 0-8519 {}}} CYCLES {}}
+set a(0-8516) {NAME ACC1-3:slc(acc.imod#3)#1 TYPE READSLICE PAR 0-7009 XREFS 48225 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7542 {}}} SUCCS {{259 0 0-8517 {}}} CYCLES {}}
+set a(0-8517) {NAME ACC1-3:not#28 TYPE NOT PAR 0-7009 XREFS 48226 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8516 {}}} SUCCS {{258 0 0-8519 {}}} CYCLES {}}
+set a(0-8518) {NAME ACC1-3:slc(acc.imod#3)#2 TYPE READSLICE PAR 0-7009 XREFS 48227 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7542 {}}} SUCCS {{259 0 0-8519 {}}} CYCLES {}}
+set a(0-8519) {NAME ACC1-3:and#1 TYPE AND PAR 0-7009 XREFS 48228 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8517 {}} {258 0 0-8515 {}} {259 0 0-8518 {}}} SUCCS {{259 0 0-8520 {}}} CYCLES {}}
+set a(0-8520) {NAME ACC1:conc#1325 TYPE CONCATENATE PAR 0-7009 XREFS 48229 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8514 {}} {259 0 0-8519 {}}} SUCCS {{259 0 0-8521 {}}} CYCLES {}}
+set a(0-8521) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#433 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48230 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8511 {}} {259 0 0-8520 {}}} SUCCS {{259 0 0-8522 {}}} CYCLES {}}
+set a(0-8522) {NAME ACC1:slc#101 TYPE READSLICE PAR 0-7009 XREFS 48231 LOC {1 0.43123487499999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8521 {}}} SUCCS {{258 0 0-8537 {}}} CYCLES {}}
+set a(0-8523) {NAME ACC1:slc(ACC1:acc#224.psp)#46 TYPE READSLICE PAR 0-7009 XREFS 48232 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7629 {}}} SUCCS {{258 0 0-8525 {}}} CYCLES {}}
+set a(0-8524) {NAME ACC1:slc(ACC1:acc#227.psp)#59 TYPE READSLICE PAR 0-7009 XREFS 48233 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8525 {}}} CYCLES {}}
+set a(0-8525) {NAME ACC1:conc#1071 TYPE CONCATENATE PAR 0-7009 XREFS 48234 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8523 {}} {259 0 0-8524 {}}} SUCCS {{259 0 0-8526 {}}} CYCLES {}}
+set a(0-8526) {NAME ACC1:conc#1322 TYPE CONCATENATE PAR 0-7009 XREFS 48235 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8525 {}}} SUCCS {{258 0 0-8535 {}}} CYCLES {}}
+set a(0-8527) {NAME ACC1:slc(ACC1:acc#228.psp)#46 TYPE READSLICE PAR 0-7009 XREFS 48236 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7331 {}}} SUCCS {{258 0 0-8529 {}}} CYCLES {}}
+set a(0-8528) {NAME ACC1:slc(ACC1:acc#227.psp)#60 TYPE READSLICE PAR 0-7009 XREFS 48237 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8529 {}}} CYCLES {}}
+set a(0-8529) {NAME ACC1:conc#1072 TYPE CONCATENATE PAR 0-7009 XREFS 48238 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8527 {}} {259 0 0-8528 {}}} SUCCS {{258 0 0-8534 {}}} CYCLES {}}
+set a(0-8530) {NAME ACC1-3:slc(acc.imod#3) TYPE READSLICE PAR 0-7009 XREFS 48239 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7542 {}}} SUCCS {{258 0 0-8533 {}}} CYCLES {}}
+set a(0-8531) {NAME ACC1-3:slc(acc.idiv)#44 TYPE READSLICE PAR 0-7009 XREFS 48240 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8532 {}}} CYCLES {}}
+set a(0-8532) {NAME ACC1-3:not#27 TYPE NOT PAR 0-7009 XREFS 48241 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8531 {}}} SUCCS {{259 0 0-8533 {}}} CYCLES {}}
+set a(0-8533) {NAME ACC1-3:nand TYPE NAND PAR 0-7009 XREFS 48242 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8530 {}} {259 0 0-8532 {}}} SUCCS {{259 0 0-8534 {}}} CYCLES {}}
+set a(0-8534) {NAME ACC1:conc#1323 TYPE CONCATENATE PAR 0-7009 XREFS 48243 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8529 {}} {259 0 0-8533 {}}} SUCCS {{259 0 0-8535 {}}} CYCLES {}}
+set a(0-8535) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#432 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48244 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8526 {}} {259 0 0-8534 {}}} SUCCS {{259 0 0-8536 {}}} CYCLES {}}
+set a(0-8536) {NAME ACC1:slc#100 TYPE READSLICE PAR 0-7009 XREFS 48245 LOC {1 0.43123487499999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8535 {}}} SUCCS {{259 0 0-8537 {}}} CYCLES {}}
+set a(0-8537) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#528 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48246 LOC {1 0.43123487499999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8522 {}} {259 0 0-8536 {}}} SUCCS {{258 0 0-8561 {}}} CYCLES {}}
+set a(0-8538) {NAME ACC1:slc(ACC1:acc#226.psp)#37 TYPE READSLICE PAR 0-7009 XREFS 48247 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7403 {}}} SUCCS {{258 0 0-8540 {}}} CYCLES {}}
+set a(0-8539) {NAME ACC1:slc(acc.psp#1)#56 TYPE READSLICE PAR 0-7009 XREFS 48248 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8540 {}}} CYCLES {}}
+set a(0-8540) {NAME ACC1:conc#1073 TYPE CONCATENATE PAR 0-7009 XREFS 48249 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8538 {}} {259 0 0-8539 {}}} SUCCS {{259 0 0-8541 {}}} CYCLES {}}
+set a(0-8541) {NAME ACC1:conc#1320 TYPE CONCATENATE PAR 0-7009 XREFS 48250 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8540 {}}} SUCCS {{258 0 0-8547 {}}} CYCLES {}}
+set a(0-8542) {NAME ACC1:slc(ACC1:acc#224.psp#1)#18 TYPE READSLICE PAR 0-7009 XREFS 48251 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.43013657499999997} PREDS {{258 0 0-7107 {}}} SUCCS {{258 0 0-8544 {}}} CYCLES {}}
+set a(0-8543) {NAME ACC1:slc(acc.psp#1)#58 TYPE READSLICE PAR 0-7009 XREFS 48252 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8544 {}}} CYCLES {}}
+set a(0-8544) {NAME ACC1:conc#1076 TYPE CONCATENATE PAR 0-7009 XREFS 48253 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8542 {}} {259 0 0-8543 {}}} SUCCS {{258 0 0-8546 {}}} CYCLES {}}
+set a(0-8545) {NAME ACC1:slc(acc.imod#2) TYPE READSLICE PAR 0-7009 XREFS 48254 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.43013657499999997} PREDS {{258 0 0-7533 {}}} SUCCS {{259 0 0-8546 {}}} CYCLES {}}
+set a(0-8546) {NAME ACC1:conc#1321 TYPE CONCATENATE PAR 0-7009 XREFS 48255 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8544 {}} {259 0 0-8545 {}}} SUCCS {{259 0 0-8547 {}}} CYCLES {}}
+set a(0-8547) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#431 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48256 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8541 {}} {259 0 0-8546 {}}} SUCCS {{259 0 0-8548 {}}} CYCLES {}}
+set a(0-8548) {NAME ACC1:slc#99 TYPE READSLICE PAR 0-7009 XREFS 48257 LOC {1 0.40398894999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8547 {}}} SUCCS {{258 0 0-8560 {}}} CYCLES {}}
+set a(0-8549) {NAME ACC1:slc(ACC1-1:acc#25.psp)#19 TYPE READSLICE PAR 0-7009 XREFS 48258 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{258 0 0-8551 {}}} CYCLES {}}
+set a(0-8550) {NAME ACC1:slc(acc.psp#1)#59 TYPE READSLICE PAR 0-7009 XREFS 48259 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8551 {}}} CYCLES {}}
+set a(0-8551) {NAME ACC1:conc#1077 TYPE CONCATENATE PAR 0-7009 XREFS 48260 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8549 {}} {259 0 0-8550 {}}} SUCCS {{259 0 0-8552 {}}} CYCLES {}}
+set a(0-8552) {NAME ACC1:conc#1318 TYPE CONCATENATE PAR 0-7009 XREFS 48261 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8551 {}}} SUCCS {{258 0 0-8558 {}}} CYCLES {}}
+set a(0-8553) {NAME ACC1:slc(acc#20.psp#1) TYPE READSLICE PAR 0-7009 XREFS 48262 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8555 {}}} CYCLES {}}
+set a(0-8554) {NAME ACC1:slc(ACC1:acc#224.psp)#48 TYPE READSLICE PAR 0-7009 XREFS 48263 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8555 {}}} CYCLES {}}
+set a(0-8555) {NAME ACC1:conc#1080 TYPE CONCATENATE PAR 0-7009 XREFS 48264 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8553 {}} {259 0 0-8554 {}}} SUCCS {{258 0 0-8557 {}}} CYCLES {}}
+set a(0-8556) {NAME ACC1:slc(ACC1:acc#210.psp#1)#14 TYPE READSLICE PAR 0-7009 XREFS 48265 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7515 {}}} SUCCS {{259 0 0-8557 {}}} CYCLES {}}
+set a(0-8557) {NAME ACC1:conc#1319 TYPE CONCATENATE PAR 0-7009 XREFS 48266 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8555 {}} {259 0 0-8556 {}}} SUCCS {{259 0 0-8558 {}}} CYCLES {}}
+set a(0-8558) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#430 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48267 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8552 {}} {259 0 0-8557 {}}} SUCCS {{259 0 0-8559 {}}} CYCLES {}}
+set a(0-8559) {NAME ACC1:slc#98 TYPE READSLICE PAR 0-7009 XREFS 48268 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8558 {}}} SUCCS {{259 0 0-8560 {}}} CYCLES {}}
+set a(0-8560) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#527 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48269 LOC {1 0.40398894999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8548 {}} {259 0 0-8559 {}}} SUCCS {{259 0 0-8561 {}}} CYCLES {}}
+set a(0-8561) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#579 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48270 LOC {1 0.47879105 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-8537 {}} {259 0 0-8560 {}}} SUCCS {{258 0 0-8612 {}}} CYCLES {}}
+set a(0-8562) {NAME ACC1:slc(acc#20.psp#1)#32 TYPE READSLICE PAR 0-7009 XREFS 48271 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8564 {}}} CYCLES {}}
+set a(0-8563) {NAME ACC1:slc(ACC1:acc#224.psp)#49 TYPE READSLICE PAR 0-7009 XREFS 48272 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8564 {}}} CYCLES {}}
+set a(0-8564) {NAME ACC1:conc#1081 TYPE CONCATENATE PAR 0-7009 XREFS 48273 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8562 {}} {259 0 0-8563 {}}} SUCCS {{259 0 0-8565 {}}} CYCLES {}}
+set a(0-8565) {NAME ACC1:conc#1316 TYPE CONCATENATE PAR 0-7009 XREFS 48274 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8564 {}}} SUCCS {{258 0 0-8571 {}}} CYCLES {}}
+set a(0-8566) {NAME ACC1:slc(acc#20.psp#1)#33 TYPE READSLICE PAR 0-7009 XREFS 48275 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8568 {}}} CYCLES {}}
+set a(0-8567) {NAME ACC1:slc(ACC1:acc#224.psp)#50 TYPE READSLICE PAR 0-7009 XREFS 48276 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8568 {}}} CYCLES {}}
+set a(0-8568) {NAME ACC1:conc#1082 TYPE CONCATENATE PAR 0-7009 XREFS 48277 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8566 {}} {259 0 0-8567 {}}} SUCCS {{258 0 0-8570 {}}} CYCLES {}}
+set a(0-8569) {NAME ACC1:slc(ACC1:acc#210.psp#1)#13 TYPE READSLICE PAR 0-7009 XREFS 48278 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7515 {}}} SUCCS {{259 0 0-8570 {}}} CYCLES {}}
+set a(0-8570) {NAME ACC1:conc#1317 TYPE CONCATENATE PAR 0-7009 XREFS 48279 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8568 {}} {259 0 0-8569 {}}} SUCCS {{259 0 0-8571 {}}} CYCLES {}}
+set a(0-8571) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#429 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48280 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8565 {}} {259 0 0-8570 {}}} SUCCS {{259 0 0-8572 {}}} CYCLES {}}
+set a(0-8572) {NAME ACC1:slc#97 TYPE READSLICE PAR 0-7009 XREFS 48281 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8571 {}}} SUCCS {{258 0 0-8584 {}}} CYCLES {}}
+set a(0-8573) {NAME ACC1:slc(acc#20.psp#1)#34 TYPE READSLICE PAR 0-7009 XREFS 48282 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8575 {}}} CYCLES {}}
+set a(0-8574) {NAME ACC1:slc(ACC1:acc#228.psp)#47 TYPE READSLICE PAR 0-7009 XREFS 48283 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8575 {}}} CYCLES {}}
+set a(0-8575) {NAME ACC1:conc#1083 TYPE CONCATENATE PAR 0-7009 XREFS 48284 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8573 {}} {259 0 0-8574 {}}} SUCCS {{259 0 0-8576 {}}} CYCLES {}}
+set a(0-8576) {NAME ACC1:conc#1314 TYPE CONCATENATE PAR 0-7009 XREFS 48285 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8575 {}}} SUCCS {{258 0 0-8582 {}}} CYCLES {}}
+set a(0-8577) {NAME ACC1:slc(ACC1:acc#217.psp#1) TYPE READSLICE PAR 0-7009 XREFS 48286 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7741 {}}} SUCCS {{258 0 0-8579 {}}} CYCLES {}}
+set a(0-8578) {NAME ACC1:slc(ACC1:acc#226.psp)#38 TYPE READSLICE PAR 0-7009 XREFS 48287 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8579 {}}} CYCLES {}}
+set a(0-8579) {NAME ACC1:conc#1090 TYPE CONCATENATE PAR 0-7009 XREFS 48288 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8577 {}} {259 0 0-8578 {}}} SUCCS {{258 0 0-8581 {}}} CYCLES {}}
+set a(0-8580) {NAME ACC1:slc(ACC1:acc#210.psp#1) TYPE READSLICE PAR 0-7009 XREFS 48289 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7515 {}}} SUCCS {{259 0 0-8581 {}}} CYCLES {}}
+set a(0-8581) {NAME ACC1:conc#1315 TYPE CONCATENATE PAR 0-7009 XREFS 48290 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8579 {}} {259 0 0-8580 {}}} SUCCS {{259 0 0-8582 {}}} CYCLES {}}
+set a(0-8582) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#428 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48291 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8576 {}} {259 0 0-8581 {}}} SUCCS {{259 0 0-8583 {}}} CYCLES {}}
+set a(0-8583) {NAME ACC1:slc#96 TYPE READSLICE PAR 0-7009 XREFS 48292 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8582 {}}} SUCCS {{259 0 0-8584 {}}} CYCLES {}}
+set a(0-8584) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#526 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48293 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8572 {}} {259 0 0-8583 {}}} SUCCS {{258 0 0-8611 {}}} CYCLES {}}
+set a(0-8585) {NAME ACC1:slc(ACC1:acc#217.psp#1)#13 TYPE READSLICE PAR 0-7009 XREFS 48294 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7741 {}}} SUCCS {{258 0 0-8587 {}}} CYCLES {}}
+set a(0-8586) {NAME ACC1:slc(ACC1:acc#226.psp)#39 TYPE READSLICE PAR 0-7009 XREFS 48295 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8587 {}}} CYCLES {}}
+set a(0-8587) {NAME ACC1:conc#1091 TYPE CONCATENATE PAR 0-7009 XREFS 48296 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8585 {}} {259 0 0-8586 {}}} SUCCS {{259 0 0-8588 {}}} CYCLES {}}
+set a(0-8588) {NAME ACC1:conc#1312 TYPE CONCATENATE PAR 0-7009 XREFS 48297 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8587 {}}} SUCCS {{258 0 0-8594 {}}} CYCLES {}}
+set a(0-8589) {NAME ACC1:slc(ACC1:acc#217.psp#1)#14 TYPE READSLICE PAR 0-7009 XREFS 48298 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-7741 {}}} SUCCS {{258 0 0-8591 {}}} CYCLES {}}
+set a(0-8590) {NAME ACC1:slc(ACC1:acc#226.psp)#40 TYPE READSLICE PAR 0-7009 XREFS 48299 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8591 {}}} CYCLES {}}
+set a(0-8591) {NAME ACC1:conc#1092 TYPE CONCATENATE PAR 0-7009 XREFS 48300 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8589 {}} {259 0 0-8590 {}}} SUCCS {{258 0 0-8593 {}}} CYCLES {}}
+set a(0-8592) {NAME ACC1:slc(ACC1-1:acc#25.psp)#18 TYPE READSLICE PAR 0-7009 XREFS 48301 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8593 {}}} CYCLES {}}
+set a(0-8593) {NAME ACC1:conc#1313 TYPE CONCATENATE PAR 0-7009 XREFS 48302 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8591 {}} {259 0 0-8592 {}}} SUCCS {{259 0 0-8594 {}}} CYCLES {}}
+set a(0-8594) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#427 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48303 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8588 {}} {259 0 0-8593 {}}} SUCCS {{259 0 0-8595 {}}} CYCLES {}}
+set a(0-8595) {NAME ACC1:slc#95 TYPE READSLICE PAR 0-7009 XREFS 48304 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8594 {}}} SUCCS {{258 0 0-8610 {}}} CYCLES {}}
+set a(0-8596) {NAME ACC1:slc(acc.imod#18) TYPE READSLICE PAR 0-7009 XREFS 48305 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.43013657499999997} PREDS {{258 0 0-7759 {}}} SUCCS {{258 0 0-8598 {}}} CYCLES {}}
+set a(0-8597) {NAME ACC1:slc(ACC1:acc#226.psp)#41 TYPE READSLICE PAR 0-7009 XREFS 48306 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8598 {}}} CYCLES {}}
+set a(0-8598) {NAME ACC1:conc#1093 TYPE CONCATENATE PAR 0-7009 XREFS 48307 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8596 {}} {259 0 0-8597 {}}} SUCCS {{259 0 0-8599 {}}} CYCLES {}}
+set a(0-8599) {NAME ACC1:conc#1310 TYPE CONCATENATE PAR 0-7009 XREFS 48308 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8598 {}}} SUCCS {{258 0 0-8608 {}}} CYCLES {}}
+set a(0-8600) {NAME ACC1-3:slc(acc.imod#19) TYPE READSLICE PAR 0-7009 XREFS 48309 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-7768 {}}} SUCCS {{258 0 0-8603 {}}} CYCLES {}}
+set a(0-8601) {NAME ACC1-3:slc(acc.idiv#4)#44 TYPE READSLICE PAR 0-7009 XREFS 48310 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8602 {}}} CYCLES {}}
+set a(0-8602) {NAME ACC1-3:not#155 TYPE NOT PAR 0-7009 XREFS 48311 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-8601 {}}} SUCCS {{259 0 0-8603 {}}} CYCLES {}}
+set a(0-8603) {NAME ACC1-3:nand#4 TYPE NAND PAR 0-7009 XREFS 48312 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8600 {}} {259 0 0-8602 {}}} SUCCS {{258 0 0-8605 {}}} CYCLES {}}
+set a(0-8604) {NAME ACC1:slc(ACC1:acc#224.psp#1)#19 TYPE READSLICE PAR 0-7009 XREFS 48313 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.43013657499999997} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-8605 {}}} CYCLES {}}
+set a(0-8605) {NAME ACC1:conc#1094 TYPE CONCATENATE PAR 0-7009 XREFS 48314 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8603 {}} {259 0 0-8604 {}}} SUCCS {{258 0 0-8607 {}}} CYCLES {}}
+set a(0-8606) {NAME ACC1:slc(ACC1-1:acc#25.psp)#17 TYPE READSLICE PAR 0-7009 XREFS 48315 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8607 {}}} CYCLES {}}
+set a(0-8607) {NAME ACC1:conc#1311 TYPE CONCATENATE PAR 0-7009 XREFS 48316 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-8605 {}} {259 0 0-8606 {}}} SUCCS {{259 0 0-8608 {}}} CYCLES {}}
+set a(0-8608) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#426 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48317 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-8599 {}} {259 0 0-8607 {}}} SUCCS {{259 0 0-8609 {}}} CYCLES {}}
+set a(0-8609) {NAME ACC1:slc#94 TYPE READSLICE PAR 0-7009 XREFS 48318 LOC {1 0.43123487499999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-8608 {}}} SUCCS {{259 0 0-8610 {}}} CYCLES {}}
+set a(0-8610) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#525 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48319 LOC {1 0.43123487499999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-8595 {}} {259 0 0-8609 {}}} SUCCS {{259 0 0-8611 {}}} CYCLES {}}
+set a(0-8611) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#578 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48320 LOC {1 0.47879105 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-8584 {}} {259 0 0-8610 {}}} SUCCS {{259 0 0-8612 {}}} CYCLES {}}
+set a(0-8612) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#604 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-7009 XREFS 48321 LOC {1 0.532138125 1 0.578596 1 0.578596 1 0.637195709496936 1 0.637195709496936} PREDS {{258 0 0-8561 {}} {259 0 0-8611 {}}} SUCCS {{259 0 0-8613 {}}} CYCLES {}}
+set a(0-8613) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#622 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-7009 XREFS 48322 LOC {1 0.590737875 1 0.63719575 1 0.63719575 1 0.7007077234103024 1 0.7007077234103024} PREDS {{258 0 0-8507 {}} {259 0 0-8612 {}}} SUCCS {{259 0 0-8614 {}}} CYCLES {}}
+set a(0-8614) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#636 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-7009 XREFS 48323 LOC {1 0.6542498999999999 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-8421 {}} {259 0 0-8613 {}}} SUCCS {{258 0 0-8640 {}}} CYCLES {}}
+set a(0-8615) {NAME slc(acc#20.psp#1)#82 TYPE READSLICE PAR 0-7009 XREFS 48324 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8619 {}}} CYCLES {}}
+set a(0-8616) {NAME slc(acc#20.psp#1)#83 TYPE READSLICE PAR 0-7009 XREFS 48325 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8619 {}}} CYCLES {}}
+set a(0-8617) {NAME slc(acc#20.psp#1)#77 TYPE READSLICE PAR 0-7009 XREFS 48326 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8619 {}}} CYCLES {}}
+set a(0-8618) {NAME ACC1:slc(ACC1:acc#228.psp)#48 TYPE READSLICE PAR 0-7009 XREFS 48327 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8619 {}}} CYCLES {}}
+set a(0-8619) {NAME ACC1:conc#1084 TYPE CONCATENATE PAR 0-7009 XREFS 48328 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-8617 {}} {258 0 0-8616 {}} {258 0 0-8615 {}} {259 0 0-8618 {}}} SUCCS {{258 0 0-8626 {}}} CYCLES {}}
+set a(0-8620) {NAME ACC1:slc(acc.psp#1)#62 TYPE READSLICE PAR 0-7009 XREFS 48329 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-7475 {}}} SUCCS {{258 0 0-8625 {}}} CYCLES {}}
+set a(0-8621) {NAME ACC1:slc(acc#20.psp#1)#37 TYPE READSLICE PAR 0-7009 XREFS 48330 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8625 {}}} CYCLES {}}
+set a(0-8622) {NAME ACC1:slc(ACC1:acc#226.psp)#45 TYPE READSLICE PAR 0-7009 XREFS 48331 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7403 {}}} SUCCS {{258 0 0-8625 {}}} CYCLES {}}
+set a(0-8623) {NAME ACC1-3:slc(acc#10.psp)#61 TYPE READSLICE PAR 0-7009 XREFS 48332 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8624 {}}} CYCLES {}}
+set a(0-8624) {NAME ACC1-3:exs#38 TYPE SIGNEXTEND PAR 0-7009 XREFS 48333 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-8623 {}}} SUCCS {{259 0 0-8625 {}}} CYCLES {}}
+set a(0-8625) {NAME ACC1:conc#1119 TYPE CONCATENATE PAR 0-7009 XREFS 48334 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-8622 {}} {258 0 0-8621 {}} {258 0 0-8620 {}} {259 0 0-8624 {}}} SUCCS {{259 0 0-8626 {}}} CYCLES {}}
+set a(0-8626) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#618 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-7009 XREFS 48335 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.7007077234103024 1 0.7007077234103024} PREDS {{258 0 0-8619 {}} {259 0 0-8625 {}}} SUCCS {{258 0 0-8639 {}}} CYCLES {}}
+set a(0-8627) {NAME ACC1:slc(ACC1:acc#224.psp)#54 TYPE READSLICE PAR 0-7009 XREFS 48336 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7629 {}}} SUCCS {{258 0 0-8632 {}}} CYCLES {}}
+set a(0-8628) {NAME ACC1:slc(acc#20.psp#1)#38 TYPE READSLICE PAR 0-7009 XREFS 48337 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8632 {}}} CYCLES {}}
+set a(0-8629) {NAME ACC1:slc(ACC1:acc#226.psp)#46 TYPE READSLICE PAR 0-7009 XREFS 48338 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7403 {}}} SUCCS {{258 0 0-8632 {}}} CYCLES {}}
+set a(0-8630) {NAME ACC1-3:slc(acc#10.psp)#60 TYPE READSLICE PAR 0-7009 XREFS 48339 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8631 {}}} CYCLES {}}
+set a(0-8631) {NAME ACC1-3:exs#39 TYPE SIGNEXTEND PAR 0-7009 XREFS 48340 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-8630 {}}} SUCCS {{259 0 0-8632 {}}} CYCLES {}}
+set a(0-8632) {NAME ACC1:conc#1120 TYPE CONCATENATE PAR 0-7009 XREFS 48341 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-8629 {}} {258 0 0-8628 {}} {258 0 0-8627 {}} {259 0 0-8631 {}}} SUCCS {{258 0 0-8638 {}}} CYCLES {}}
+set a(0-8633) {NAME ACC1:slc(ACC1:acc#228.psp)#56 TYPE READSLICE PAR 0-7009 XREFS 48342 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7331 {}}} SUCCS {{258 0 0-8637 {}}} CYCLES {}}
+set a(0-8634) {NAME ACC1:slc(ACC1:acc#227.psp)#63 TYPE READSLICE PAR 0-7009 XREFS 48343 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.63719575} PREDS {{258 0 0-7554 {}}} SUCCS {{258 0 0-8637 {}}} CYCLES {}}
+set a(0-8635) {NAME ACC1-3:slc(acc#10.psp)#59 TYPE READSLICE PAR 0-7009 XREFS 48344 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8636 {}}} CYCLES {}}
+set a(0-8636) {NAME ACC1-3:exs#43 TYPE SIGNEXTEND PAR 0-7009 XREFS 48345 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-8635 {}}} SUCCS {{259 0 0-8637 {}}} CYCLES {}}
+set a(0-8637) {NAME ACC1:conc#1121 TYPE CONCATENATE PAR 0-7009 XREFS 48346 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-8634 {}} {258 0 0-8633 {}} {259 0 0-8636 {}}} SUCCS {{259 0 0-8638 {}}} CYCLES {}}
+set a(0-8638) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#617 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-7009 XREFS 48347 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.7007077234103024 1 0.7007077234103024} PREDS {{258 0 0-8632 {}} {259 0 0-8637 {}}} SUCCS {{259 0 0-8639 {}}} CYCLES {}}
+set a(0-8639) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#634 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-7009 XREFS 48348 LOC {1 0.210066975 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-8626 {}} {259 0 0-8638 {}}} SUCCS {{259 0 0-8640 {}}} CYCLES {}}
+set a(0-8640) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,9) AREA_SCORE 9.26 QUANTITY 5 NAME ACC1:acc#644 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-7009 XREFS 48349 LOC {1 0.7224392749999999 1 0.7688971499999999 1 0.7688971499999999 1 0.8415918527684256 1 0.8415918527684256} PREDS {{258 0 0-8614 {}} {259 0 0-8639 {}}} SUCCS {{258 0 0-8676 {}}} CYCLES {}}
+set a(0-8641) {NAME ACC1:slc(ACC1:acc#226.psp)#47 TYPE READSLICE PAR 0-7009 XREFS 48350 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7403 {}}} SUCCS {{258 0 0-8645 {}}} CYCLES {}}
+set a(0-8642) {NAME ACC1:slc(ACC1:acc#227.psp)#64 TYPE READSLICE PAR 0-7009 XREFS 48351 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.63719575} PREDS {{258 0 0-7554 {}}} SUCCS {{258 0 0-8645 {}}} CYCLES {}}
+set a(0-8643) {NAME ACC1-3:slc(acc#10.psp)#58 TYPE READSLICE PAR 0-7009 XREFS 48352 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8644 {}}} CYCLES {}}
+set a(0-8644) {NAME ACC1-3:exs#44 TYPE SIGNEXTEND PAR 0-7009 XREFS 48353 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-8643 {}}} SUCCS {{259 0 0-8645 {}}} CYCLES {}}
+set a(0-8645) {NAME ACC1:conc#1122 TYPE CONCATENATE PAR 0-7009 XREFS 48354 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-8642 {}} {258 0 0-8641 {}} {259 0 0-8644 {}}} SUCCS {{258 0 0-8651 {}}} CYCLES {}}
+set a(0-8646) {NAME ACC1:slc(ACC1:acc#224.psp#1)#28 TYPE READSLICE PAR 0-7009 XREFS 48355 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.63719575} PREDS {{258 0 0-7107 {}}} SUCCS {{258 0 0-8650 {}}} CYCLES {}}
+set a(0-8647) {NAME ACC1:slc(acc.psp#1)#63 TYPE READSLICE PAR 0-7009 XREFS 48356 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-7475 {}}} SUCCS {{258 0 0-8650 {}}} CYCLES {}}
+set a(0-8648) {NAME ACC1-3:slc(acc#10.psp)#57 TYPE READSLICE PAR 0-7009 XREFS 48357 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8649 {}}} CYCLES {}}
+set a(0-8649) {NAME ACC1-3:exs#42 TYPE SIGNEXTEND PAR 0-7009 XREFS 48358 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-8648 {}}} SUCCS {{259 0 0-8650 {}}} CYCLES {}}
+set a(0-8650) {NAME ACC1:conc#1123 TYPE CONCATENATE PAR 0-7009 XREFS 48359 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-8647 {}} {258 0 0-8646 {}} {259 0 0-8649 {}}} SUCCS {{259 0 0-8651 {}}} CYCLES {}}
+set a(0-8651) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#616 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-7009 XREFS 48360 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.7007077234103024 1 0.7007077234103024} PREDS {{258 0 0-8645 {}} {259 0 0-8650 {}}} SUCCS {{258 0 0-8663 {}}} CYCLES {}}
+set a(0-8652) {NAME ACC1:slc(ACC1-1:acc#25.psp)#24 TYPE READSLICE PAR 0-7009 XREFS 48361 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.63719575} PREDS {{258 0 0-7252 {}}} SUCCS {{258 0 0-8656 {}}} CYCLES {}}
+set a(0-8653) {NAME ACC1:slc(acc.psp#1)#64 TYPE READSLICE PAR 0-7009 XREFS 48362 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-7475 {}}} SUCCS {{258 0 0-8656 {}}} CYCLES {}}
+set a(0-8654) {NAME ACC1-3:slc(acc#10.psp)#56 TYPE READSLICE PAR 0-7009 XREFS 48363 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8655 {}}} CYCLES {}}
+set a(0-8655) {NAME ACC1-3:exs#47 TYPE SIGNEXTEND PAR 0-7009 XREFS 48364 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-8654 {}}} SUCCS {{259 0 0-8656 {}}} CYCLES {}}
+set a(0-8656) {NAME ACC1:conc#1124 TYPE CONCATENATE PAR 0-7009 XREFS 48365 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-8653 {}} {258 0 0-8652 {}} {259 0 0-8655 {}}} SUCCS {{258 0 0-8662 {}}} CYCLES {}}
+set a(0-8657) {NAME ACC1:slc(acc.psp#2)#13 TYPE READSLICE PAR 0-7009 XREFS 48366 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.63719575} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-8661 {}}} CYCLES {}}
+set a(0-8658) {NAME ACC1:slc(ACC1:acc#224.psp)#55 TYPE READSLICE PAR 0-7009 XREFS 48367 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7629 {}}} SUCCS {{258 0 0-8661 {}}} CYCLES {}}
+set a(0-8659) {NAME ACC1-3:slc(acc#10.psp)#55 TYPE READSLICE PAR 0-7009 XREFS 48368 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8660 {}}} CYCLES {}}
+set a(0-8660) {NAME ACC1-3:exs#45 TYPE SIGNEXTEND PAR 0-7009 XREFS 48369 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-8659 {}}} SUCCS {{259 0 0-8661 {}}} CYCLES {}}
+set a(0-8661) {NAME ACC1:conc#1125 TYPE CONCATENATE PAR 0-7009 XREFS 48370 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-8658 {}} {258 0 0-8657 {}} {259 0 0-8660 {}}} SUCCS {{259 0 0-8662 {}}} CYCLES {}}
+set a(0-8662) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#615 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-7009 XREFS 48371 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.7007077234103024 1 0.7007077234103024} PREDS {{258 0 0-8656 {}} {259 0 0-8661 {}}} SUCCS {{259 0 0-8663 {}}} CYCLES {}}
+set a(0-8663) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#633 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-7009 XREFS 48372 LOC {1 0.210066975 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-8651 {}} {259 0 0-8662 {}}} SUCCS {{258 0 0-8675 {}}} CYCLES {}}
+set a(0-8664) {NAME ACC1-3:slc(acc#5.psp)#17 TYPE READSLICE PAR 0-7009 XREFS 48373 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.7007077749999999} PREDS {{258 0 0-7554 {}}} SUCCS {{258 0 0-8667 {}}} CYCLES {}}
+set a(0-8665) {NAME ACC1-3:slc(acc.idiv#1)#25 TYPE READSLICE PAR 0-7009 XREFS 48374 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.7007077749999999} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8666 {}}} CYCLES {}}
+set a(0-8666) {NAME ACC1-3:exs#30 TYPE SIGNEXTEND PAR 0-7009 XREFS 48375 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8665 {}}} SUCCS {{259 0 0-8667 {}}} CYCLES {}}
+set a(0-8667) {NAME ACC1-3:conc#496 TYPE CONCATENATE PAR 0-7009 XREFS 48376 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-8664 {}} {259 0 0-8666 {}}} SUCCS {{259 0 0-8668 {}}} CYCLES {}}
+set a(0-8668) {NAME ACC1-3:exs#1032 TYPE SIGNEXTEND PAR 0-7009 XREFS 48377 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8667 {}}} SUCCS {{258 0 0-8674 {}}} CYCLES {}}
+set a(0-8669) {NAME ACC1-3:slc(acc.psp)#17 TYPE READSLICE PAR 0-7009 XREFS 48378 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7007077749999999} PREDS {{258 0 0-7475 {}}} SUCCS {{258 0 0-8672 {}}} CYCLES {}}
+set a(0-8670) {NAME ACC1-3:slc(acc.idiv)#25 TYPE READSLICE PAR 0-7009 XREFS 48379 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7007077749999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8671 {}}} CYCLES {}}
+set a(0-8671) {NAME ACC1-3:exs#12 TYPE SIGNEXTEND PAR 0-7009 XREFS 48380 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8670 {}}} SUCCS {{259 0 0-8672 {}}} CYCLES {}}
+set a(0-8672) {NAME ACC1-3:conc#482 TYPE CONCATENATE PAR 0-7009 XREFS 48381 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-8669 {}} {259 0 0-8671 {}}} SUCCS {{259 0 0-8673 {}}} CYCLES {}}
+set a(0-8673) {NAME ACC1-3:exs#1029 TYPE SIGNEXTEND PAR 0-7009 XREFS 48382 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8672 {}}} SUCCS {{259 0 0-8674 {}}} CYCLES {}}
+set a(0-8674) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#632 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-7009 XREFS 48383 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-8668 {}} {259 0 0-8673 {}}} SUCCS {{259 0 0-8675 {}}} CYCLES {}}
+set a(0-8675) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,9) AREA_SCORE 9.26 QUANTITY 5 NAME ACC1:acc#643 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-7009 XREFS 48384 LOC {1 0.27825635 1 0.7688971499999999 1 0.7688971499999999 1 0.8415918527684256 1 0.8415918527684256} PREDS {{258 0 0-8663 {}} {259 0 0-8674 {}}} SUCCS {{259 0 0-8676 {}}} CYCLES {}}
+set a(0-8676) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,0,10) AREA_SCORE 10.25 QUANTITY 2 NAME ACC1:acc#649 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-7009 XREFS 48385 LOC {1 0.795134025 1 0.8415919 1 0.8415919 1 0.9186606628916543 1 0.9186606628916543} PREDS {{258 0 0-8640 {}} {259 0 0-8675 {}}} SUCCS {{258 0 0-8724 {}}} CYCLES {}}
+set a(0-8677) {NAME ACC1-3:slc(acc#10.psp)#52 TYPE READSLICE PAR 0-7009 XREFS 48386 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7007077749999999} PREDS {{258 0 0-7629 {}}} SUCCS {{258 0 0-8680 {}}} CYCLES {}}
+set a(0-8678) {NAME ACC1-3:slc(acc#10.psp)#53 TYPE READSLICE PAR 0-7009 XREFS 48387 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7007077749999999} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-8679 {}}} CYCLES {}}
+set a(0-8679) {NAME ACC1-3:exs#48 TYPE SIGNEXTEND PAR 0-7009 XREFS 48388 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8678 {}}} SUCCS {{259 0 0-8680 {}}} CYCLES {}}
+set a(0-8680) {NAME ACC1-3:conc#510 TYPE CONCATENATE PAR 0-7009 XREFS 48389 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-8677 {}} {259 0 0-8679 {}}} SUCCS {{259 0 0-8681 {}}} CYCLES {}}
+set a(0-8681) {NAME ACC1-3:exs#1035 TYPE SIGNEXTEND PAR 0-7009 XREFS 48390 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8680 {}}} SUCCS {{258 0 0-8687 {}}} CYCLES {}}
+set a(0-8682) {NAME ACC1:slc(acc#5.psp#2)#63 TYPE READSLICE PAR 0-7009 XREFS 48391 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7007077749999999} PREDS {{258 0 0-7331 {}}} SUCCS {{258 0 0-8685 {}}} CYCLES {}}
+set a(0-8683) {NAME ACC1:slc(acc#5.psp#2)#64 TYPE READSLICE PAR 0-7009 XREFS 48392 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7007077749999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8684 {}}} CYCLES {}}
+set a(0-8684) {NAME ACC1-2:exs#30 TYPE SIGNEXTEND PAR 0-7009 XREFS 48393 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8683 {}}} SUCCS {{259 0 0-8685 {}}} CYCLES {}}
+set a(0-8685) {NAME ACC1-2:conc#496 TYPE CONCATENATE PAR 0-7009 XREFS 48394 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-8682 {}} {259 0 0-8684 {}}} SUCCS {{259 0 0-8686 {}}} CYCLES {}}
+set a(0-8686) {NAME ACC1-2:exs#1032 TYPE SIGNEXTEND PAR 0-7009 XREFS 48395 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8685 {}}} SUCCS {{259 0 0-8687 {}}} CYCLES {}}
+set a(0-8687) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#631 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-7009 XREFS 48396 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-8681 {}} {259 0 0-8686 {}}} SUCCS {{258 0 0-8699 {}}} CYCLES {}}
+set a(0-8688) {NAME ACC1-3:slc(acc#25.psp)#25 TYPE READSLICE PAR 0-7009 XREFS 48397 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7007077749999999} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8691 {}}} CYCLES {}}
+set a(0-8689) {NAME ACC1-3:slc(acc.idiv#5)#31 TYPE READSLICE PAR 0-7009 XREFS 48398 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7007077749999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8690 {}}} CYCLES {}}
+set a(0-8690) {NAME ACC1-3:exs#105 TYPE SIGNEXTEND PAR 0-7009 XREFS 48399 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8689 {}}} SUCCS {{259 0 0-8691 {}}} CYCLES {}}
+set a(0-8691) {NAME ACC1-3:conc#552 TYPE CONCATENATE PAR 0-7009 XREFS 48400 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-8688 {}} {259 0 0-8690 {}}} SUCCS {{259 0 0-8692 {}}} CYCLES {}}
+set a(0-8692) {NAME ACC1-3:exs#1042 TYPE SIGNEXTEND PAR 0-7009 XREFS 48401 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8691 {}}} SUCCS {{258 0 0-8698 {}}} CYCLES {}}
+set a(0-8693) {NAME ACC1-3:slc(acc#20.psp)#17 TYPE READSLICE PAR 0-7009 XREFS 48402 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7007077749999999} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8696 {}}} CYCLES {}}
+set a(0-8694) {NAME ACC1-3:slc(acc.idiv#4)#25 TYPE READSLICE PAR 0-7009 XREFS 48403 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7007077749999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8695 {}}} CYCLES {}}
+set a(0-8695) {NAME ACC1-3:exs#84 TYPE SIGNEXTEND PAR 0-7009 XREFS 48404 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8694 {}}} SUCCS {{259 0 0-8696 {}}} CYCLES {}}
+set a(0-8696) {NAME ACC1-3:conc#538 TYPE CONCATENATE PAR 0-7009 XREFS 48405 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-8693 {}} {259 0 0-8695 {}}} SUCCS {{259 0 0-8697 {}}} CYCLES {}}
+set a(0-8697) {NAME ACC1-3:exs#1040 TYPE SIGNEXTEND PAR 0-7009 XREFS 48406 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8696 {}}} SUCCS {{259 0 0-8698 {}}} CYCLES {}}
+set a(0-8698) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#630 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-7009 XREFS 48407 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-8692 {}} {259 0 0-8697 {}}} SUCCS {{259 0 0-8699 {}}} CYCLES {}}
+set a(0-8699) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,9) AREA_SCORE 9.26 QUANTITY 5 NAME ACC1:acc#642 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-7009 XREFS 48408 LOC {1 0.21474432499999999 1 0.7688971499999999 1 0.7688971499999999 1 0.8415918527684256 1 0.8415918527684256} PREDS {{258 0 0-8687 {}} {259 0 0-8698 {}}} SUCCS {{258 0 0-8723 {}}} CYCLES {}}
+set a(0-8700) {NAME ACC1:slc(acc#25.psp#2)#64 TYPE READSLICE PAR 0-7009 XREFS 48409 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7007077749999999} PREDS {{258 0 0-7403 {}}} SUCCS {{258 0 0-8703 {}}} CYCLES {}}
+set a(0-8701) {NAME ACC1:slc(acc#25.psp#2)#65 TYPE READSLICE PAR 0-7009 XREFS 48410 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7007077749999999} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8702 {}}} CYCLES {}}
+set a(0-8702) {NAME ACC1-2:exs#105 TYPE SIGNEXTEND PAR 0-7009 XREFS 48411 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8701 {}}} SUCCS {{259 0 0-8703 {}}} CYCLES {}}
+set a(0-8703) {NAME ACC1-2:conc#552 TYPE CONCATENATE PAR 0-7009 XREFS 48412 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-8700 {}} {259 0 0-8702 {}}} SUCCS {{259 0 0-8704 {}}} CYCLES {}}
+set a(0-8704) {NAME ACC1-2:exs#1042 TYPE SIGNEXTEND PAR 0-7009 XREFS 48413 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8703 {}}} SUCCS {{258 0 0-8710 {}}} CYCLES {}}
+set a(0-8705) {NAME ACC1-1:slc(acc#10.psp)#52 TYPE READSLICE PAR 0-7009 XREFS 48414 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.7007077749999999} PREDS {{258 0 0-7107 {}}} SUCCS {{258 0 0-8708 {}}} CYCLES {}}
+set a(0-8706) {NAME ACC1-1:slc(acc#10.psp)#53 TYPE READSLICE PAR 0-7009 XREFS 48415 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.7007077749999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-8707 {}}} CYCLES {}}
+set a(0-8707) {NAME ACC1-1:exs#48 TYPE SIGNEXTEND PAR 0-7009 XREFS 48416 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8706 {}}} SUCCS {{259 0 0-8708 {}}} CYCLES {}}
+set a(0-8708) {NAME ACC1-1:conc#510 TYPE CONCATENATE PAR 0-7009 XREFS 48417 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-8705 {}} {259 0 0-8707 {}}} SUCCS {{259 0 0-8709 {}}} CYCLES {}}
+set a(0-8709) {NAME ACC1-1:exs#1035 TYPE SIGNEXTEND PAR 0-7009 XREFS 48418 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8708 {}}} SUCCS {{259 0 0-8710 {}}} CYCLES {}}
+set a(0-8710) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#629 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-7009 XREFS 48419 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-8704 {}} {259 0 0-8709 {}}} SUCCS {{258 0 0-8722 {}}} CYCLES {}}
+set a(0-8711) {NAME ACC1-1:slc(acc#25.psp)#25 TYPE READSLICE PAR 0-7009 XREFS 48420 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.7007077749999999} PREDS {{258 0 0-7252 {}}} SUCCS {{258 0 0-8714 {}}} CYCLES {}}
+set a(0-8712) {NAME ACC1-1:slc(acc.idiv#5)#31 TYPE READSLICE PAR 0-7009 XREFS 48421 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.7007077749999999} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8713 {}}} CYCLES {}}
+set a(0-8713) {NAME ACC1-1:exs#105 TYPE SIGNEXTEND PAR 0-7009 XREFS 48422 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8712 {}}} SUCCS {{259 0 0-8714 {}}} CYCLES {}}
+set a(0-8714) {NAME ACC1-1:conc#552 TYPE CONCATENATE PAR 0-7009 XREFS 48423 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-8711 {}} {259 0 0-8713 {}}} SUCCS {{259 0 0-8715 {}}} CYCLES {}}
+set a(0-8715) {NAME ACC1-1:exs#1042 TYPE SIGNEXTEND PAR 0-7009 XREFS 48424 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8714 {}}} SUCCS {{258 0 0-8721 {}}} CYCLES {}}
+set a(0-8716) {NAME ACC1-1:slc(acc#5.psp)#17 TYPE READSLICE PAR 0-7009 XREFS 48425 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7007077749999999} PREDS {{258 0 0-7022 {}}} SUCCS {{258 0 0-8719 {}}} CYCLES {}}
+set a(0-8717) {NAME ACC1-1:slc(acc.idiv#1)#25 TYPE READSLICE PAR 0-7009 XREFS 48426 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7007077749999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8718 {}}} CYCLES {}}
+set a(0-8718) {NAME ACC1-1:exs#30 TYPE SIGNEXTEND PAR 0-7009 XREFS 48427 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8717 {}}} SUCCS {{259 0 0-8719 {}}} CYCLES {}}
+set a(0-8719) {NAME ACC1-1:conc#496 TYPE CONCATENATE PAR 0-7009 XREFS 48428 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-8716 {}} {259 0 0-8718 {}}} SUCCS {{259 0 0-8720 {}}} CYCLES {}}
+set a(0-8720) {NAME ACC1-1:exs#1032 TYPE SIGNEXTEND PAR 0-7009 XREFS 48429 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-8719 {}}} SUCCS {{259 0 0-8721 {}}} CYCLES {}}
+set a(0-8721) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#628 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-7009 XREFS 48430 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-8715 {}} {259 0 0-8720 {}}} SUCCS {{259 0 0-8722 {}}} CYCLES {}}
+set a(0-8722) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,9) AREA_SCORE 9.26 QUANTITY 5 NAME ACC1:acc#641 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-7009 XREFS 48431 LOC {1 0.21474432499999999 1 0.7688971499999999 1 0.7688971499999999 1 0.8415918527684256 1 0.8415918527684256} PREDS {{258 0 0-8710 {}} {259 0 0-8721 {}}} SUCCS {{259 0 0-8723 {}}} CYCLES {}}
+set a(0-8723) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,0,10) AREA_SCORE 10.25 QUANTITY 2 NAME ACC1:acc#648 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-7009 XREFS 48432 LOC {1 0.287439075 1 0.8415919 1 0.8415919 1 0.9186606628916543 1 0.9186606628916543} PREDS {{258 0 0-8699 {}} {259 0 0-8722 {}}} SUCCS {{259 0 0-8724 {}}} CYCLES {}}
+set a(0-8724) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,11) AREA_SCORE 11.24 QUANTITY 3 NAME ACC1:acc#652 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-7009 XREFS 48433 LOC {1 0.87220285 1 0.918660725 1 0.918660725 1 0.9999999533364112 1 0.9999999533364112} PREDS {{258 0 0-8676 {}} {259 0 0-8723 {}}} SUCCS {{259 0 0-8725 {}}} CYCLES {}}
+set a(0-8725) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 4 NAME ACC1:acc#656 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-7009 XREFS 48434 LOC {2 0.0 2 0.060871249999999995 2 0.060871249999999995 2 0.14035945349977766 2 0.14035945349977766} PREDS {{258 0 0-8248 {}} {259 0 0-8724 {}}} SUCCS {{258 0 0-9272 {}}} CYCLES {}}
+set a(0-8726) {NAME slc(acc#20.psp#1)#87 TYPE READSLICE PAR 0-7009 XREFS 48435 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.003959675} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8732 {}}} CYCLES {}}
+set a(0-8727) {NAME slc(acc#20.psp#1)#88 TYPE READSLICE PAR 0-7009 XREFS 48436 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.003959675} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8732 {}}} CYCLES {}}
+set a(0-8728) {NAME slc(acc#20.psp#1)#89 TYPE READSLICE PAR 0-7009 XREFS 48437 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.003959675} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8732 {}}} CYCLES {}}
+set a(0-8729) {NAME slc(acc#20.psp#1)#90 TYPE READSLICE PAR 0-7009 XREFS 48438 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.003959675} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8732 {}}} CYCLES {}}
+set a(0-8730) {NAME slc(acc#20.psp#1)#79 TYPE READSLICE PAR 0-7009 XREFS 48439 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.003959675} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-8732 {}}} CYCLES {}}
+set a(0-8731) {NAME ACC1:slc(ACC1:acc#228.psp)#50 TYPE READSLICE PAR 0-7009 XREFS 48440 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.003959675} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-8732 {}}} CYCLES {}}
+set a(0-8732) {NAME ACC1:conc#1088 TYPE CONCATENATE PAR 0-7009 XREFS 48441 LOC {1 0.14655495 1 0.863600175 1 0.863600175 2 0.003959675} PREDS {{258 0 0-8730 {}} {258 0 0-8729 {}} {258 0 0-8728 {}} {258 0 0-8727 {}} {258 0 0-8726 {}} {259 0 0-8731 {}}} SUCCS {{258 0 0-9114 {}}} CYCLES {}}
+set a(0-8733) {NAME ACC1:slc(ACC1-1:acc#25.psp)#15 TYPE READSLICE PAR 0-7009 XREFS 48442 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.895231} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-8734 {}}} CYCLES {}}
+set a(0-8734) {NAME ACC1:conc#1307 TYPE CONCATENATE PAR 0-7009 XREFS 48443 LOC {1 0.14655495 1 0.758831175 1 0.758831175 1 0.895231} PREDS {{259 0 0-8733 {}}} SUCCS {{258 0 0-8830 {}}} CYCLES {}}
+set a(0-8735) {NAME ACC1-3:slc(acc.idiv#1)#13 TYPE READSLICE PAR 0-7009 XREFS 48444 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6314329249999999} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8736 {}}} CYCLES {}}
+set a(0-8736) {NAME ACC1-3:exs#24 TYPE SIGNEXTEND PAR 0-7009 XREFS 48445 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8735 {}}} SUCCS {{258 0 0-8739 {}}} CYCLES {}}
+set a(0-8737) {NAME ACC1-3:slc(acc.idiv#1)#23 TYPE READSLICE PAR 0-7009 XREFS 48446 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6314329249999999} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8738 {}}} CYCLES {}}
+set a(0-8738) {NAME ACC1-3:exs#29 TYPE SIGNEXTEND PAR 0-7009 XREFS 48447 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8737 {}}} SUCCS {{259 0 0-8739 {}}} CYCLES {}}
+set a(0-8739) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#509 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48448 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8736 {}} {259 0 0-8738 {}}} SUCCS {{258 0 0-8745 {}}} CYCLES {}}
+set a(0-8740) {NAME ACC1-3:slc(acc.idiv#1)#19 TYPE READSLICE PAR 0-7009 XREFS 48449 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6314329249999999} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8741 {}}} CYCLES {}}
+set a(0-8741) {NAME ACC1-3:exs#27 TYPE SIGNEXTEND PAR 0-7009 XREFS 48450 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8740 {}}} SUCCS {{258 0 0-8744 {}}} CYCLES {}}
+set a(0-8742) {NAME ACC1-3:slc(acc.idiv#1)#21 TYPE READSLICE PAR 0-7009 XREFS 48451 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6314329249999999} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8743 {}}} CYCLES {}}
+set a(0-8743) {NAME ACC1-3:exs#28 TYPE SIGNEXTEND PAR 0-7009 XREFS 48452 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8742 {}}} SUCCS {{259 0 0-8744 {}}} CYCLES {}}
+set a(0-8744) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#508 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48453 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8741 {}} {259 0 0-8743 {}}} SUCCS {{259 0 0-8745 {}}} CYCLES {}}
+set a(0-8745) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#564 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48454 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-8739 {}} {259 0 0-8744 {}}} SUCCS {{258 0 0-8757 {}}} CYCLES {}}
+set a(0-8746) {NAME ACC1-3:slc(acc.idiv#1)#31 TYPE READSLICE PAR 0-7009 XREFS 48455 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6314329249999999} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8747 {}}} CYCLES {}}
+set a(0-8747) {NAME ACC1-3:exs#33 TYPE SIGNEXTEND PAR 0-7009 XREFS 48456 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8746 {}}} SUCCS {{258 0 0-8750 {}}} CYCLES {}}
+set a(0-8748) {NAME ACC1-3:slc(acc#5.psp)#65 TYPE READSLICE PAR 0-7009 XREFS 48457 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6314329249999999} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-8749 {}}} CYCLES {}}
+set a(0-8749) {NAME ACC1-3:exs#1031 TYPE SIGNEXTEND PAR 0-7009 XREFS 48458 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8748 {}}} SUCCS {{259 0 0-8750 {}}} CYCLES {}}
+set a(0-8750) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#507 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48459 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8747 {}} {259 0 0-8749 {}}} SUCCS {{258 0 0-8756 {}}} CYCLES {}}
+set a(0-8751) {NAME ACC1-3:slc(acc.idiv#5)#21 TYPE READSLICE PAR 0-7009 XREFS 48460 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8752 {}}} CYCLES {}}
+set a(0-8752) {NAME ACC1-3:exs#100 TYPE SIGNEXTEND PAR 0-7009 XREFS 48461 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8751 {}}} SUCCS {{258 0 0-8755 {}}} CYCLES {}}
+set a(0-8753) {NAME ACC1-3:slc(acc.idiv#5)#13 TYPE READSLICE PAR 0-7009 XREFS 48462 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8754 {}}} CYCLES {}}
+set a(0-8754) {NAME ACC1-3:exs#96 TYPE SIGNEXTEND PAR 0-7009 XREFS 48463 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8753 {}}} SUCCS {{259 0 0-8755 {}}} CYCLES {}}
+set a(0-8755) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#506 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48464 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8752 {}} {259 0 0-8754 {}}} SUCCS {{259 0 0-8756 {}}} CYCLES {}}
+set a(0-8756) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#563 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48465 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-8750 {}} {259 0 0-8755 {}}} SUCCS {{259 0 0-8757 {}}} CYCLES {}}
+set a(0-8757) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#597 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48466 LOC {1 0.23489417499999998 1 0.583372325 1 0.583372325 1 0.6367193451789506 1 0.7731191701789504} PREDS {{258 0 0-8745 {}} {259 0 0-8756 {}}} SUCCS {{258 0 0-8781 {}}} CYCLES {}}
+set a(0-8758) {NAME ACC1-3:slc(acc.idiv#5)#15 TYPE READSLICE PAR 0-7009 XREFS 48467 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8759 {}}} CYCLES {}}
+set a(0-8759) {NAME ACC1-3:exs#97 TYPE SIGNEXTEND PAR 0-7009 XREFS 48468 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8758 {}}} SUCCS {{258 0 0-8762 {}}} CYCLES {}}
+set a(0-8760) {NAME ACC1-3:slc(acc.idiv#5)#17 TYPE READSLICE PAR 0-7009 XREFS 48469 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8761 {}}} CYCLES {}}
+set a(0-8761) {NAME ACC1-3:exs#98 TYPE SIGNEXTEND PAR 0-7009 XREFS 48470 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8760 {}}} SUCCS {{259 0 0-8762 {}}} CYCLES {}}
+set a(0-8762) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#505 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48471 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8759 {}} {259 0 0-8761 {}}} SUCCS {{258 0 0-8768 {}}} CYCLES {}}
+set a(0-8763) {NAME ACC1-3:slc(acc.idiv#5)#25 TYPE READSLICE PAR 0-7009 XREFS 48472 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8764 {}}} CYCLES {}}
+set a(0-8764) {NAME ACC1-3:exs#102 TYPE SIGNEXTEND PAR 0-7009 XREFS 48473 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8763 {}}} SUCCS {{258 0 0-8767 {}}} CYCLES {}}
+set a(0-8765) {NAME ACC1-3:slc(acc#25.psp)#46 TYPE READSLICE PAR 0-7009 XREFS 48474 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8766 {}}} CYCLES {}}
+set a(0-8766) {NAME ACC1-3:exs#353 TYPE SIGNEXTEND PAR 0-7009 XREFS 48475 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8765 {}}} SUCCS {{259 0 0-8767 {}}} CYCLES {}}
+set a(0-8767) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#504 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48476 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8764 {}} {259 0 0-8766 {}}} SUCCS {{259 0 0-8768 {}}} CYCLES {}}
+set a(0-8768) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#562 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48477 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-8762 {}} {259 0 0-8767 {}}} SUCCS {{258 0 0-8780 {}}} CYCLES {}}
+set a(0-8769) {NAME ACC1-3:slc(acc.idiv#5)#23 TYPE READSLICE PAR 0-7009 XREFS 48478 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8770 {}}} CYCLES {}}
+set a(0-8770) {NAME ACC1-3:exs#101 TYPE SIGNEXTEND PAR 0-7009 XREFS 48479 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8769 {}}} SUCCS {{258 0 0-8773 {}}} CYCLES {}}
+set a(0-8771) {NAME ACC1-3:slc(acc.idiv#5)#33 TYPE READSLICE PAR 0-7009 XREFS 48480 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8772 {}}} CYCLES {}}
+set a(0-8772) {NAME ACC1-3:exs#106 TYPE SIGNEXTEND PAR 0-7009 XREFS 48481 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8771 {}}} SUCCS {{259 0 0-8773 {}}} CYCLES {}}
+set a(0-8773) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#503 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48482 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8770 {}} {259 0 0-8772 {}}} SUCCS {{258 0 0-8779 {}}} CYCLES {}}
+set a(0-8774) {NAME ACC1-3:slc(acc#25.psp)#56 TYPE READSLICE PAR 0-7009 XREFS 48483 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8775 {}}} CYCLES {}}
+set a(0-8775) {NAME ACC1-3:exs#963 TYPE SIGNEXTEND PAR 0-7009 XREFS 48484 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8774 {}}} SUCCS {{258 0 0-8778 {}}} CYCLES {}}
+set a(0-8776) {NAME ACC1-3:slc(acc.idiv#5)#27 TYPE READSLICE PAR 0-7009 XREFS 48485 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8777 {}}} CYCLES {}}
+set a(0-8777) {NAME ACC1-3:exs#103 TYPE SIGNEXTEND PAR 0-7009 XREFS 48486 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8776 {}}} SUCCS {{259 0 0-8778 {}}} CYCLES {}}
+set a(0-8778) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#502 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48487 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8775 {}} {259 0 0-8777 {}}} SUCCS {{259 0 0-8779 {}}} CYCLES {}}
+set a(0-8779) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#561 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48488 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-8773 {}} {259 0 0-8778 {}}} SUCCS {{259 0 0-8780 {}}} CYCLES {}}
+set a(0-8780) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#596 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48489 LOC {1 0.23489417499999998 1 0.583372325 1 0.583372325 1 0.6367193451789506 1 0.7731191701789504} PREDS {{258 0 0-8768 {}} {259 0 0-8779 {}}} SUCCS {{259 0 0-8781 {}}} CYCLES {}}
+set a(0-8781) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#613 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-7009 XREFS 48490 LOC {1 0.28824125 1 0.6367193999999999 1 0.6367193999999999 1 0.695319109496936 1 0.831718934496936} PREDS {{258 0 0-8757 {}} {259 0 0-8780 {}}} SUCCS {{258 0 0-8829 {}}} CYCLES {}}
+set a(0-8782) {NAME ACC1-3:slc(acc.idiv#5)#29 TYPE READSLICE PAR 0-7009 XREFS 48491 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8783 {}}} CYCLES {}}
+set a(0-8783) {NAME ACC1-3:exs#104 TYPE SIGNEXTEND PAR 0-7009 XREFS 48492 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8782 {}}} SUCCS {{258 0 0-8786 {}}} CYCLES {}}
+set a(0-8784) {NAME ACC1-3:slc(acc.idiv#4)#33 TYPE READSLICE PAR 0-7009 XREFS 48493 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8785 {}}} CYCLES {}}
+set a(0-8785) {NAME ACC1-3:exs#88 TYPE SIGNEXTEND PAR 0-7009 XREFS 48494 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8784 {}}} SUCCS {{259 0 0-8786 {}}} CYCLES {}}
+set a(0-8786) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#501 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48495 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8783 {}} {259 0 0-8785 {}}} SUCCS {{258 0 0-8792 {}}} CYCLES {}}
+set a(0-8787) {NAME ACC1-3:slc(acc.idiv#4)#35 TYPE READSLICE PAR 0-7009 XREFS 48496 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8788 {}}} CYCLES {}}
+set a(0-8788) {NAME ACC1-3:exs#89 TYPE SIGNEXTEND PAR 0-7009 XREFS 48497 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8787 {}}} SUCCS {{258 0 0-8791 {}}} CYCLES {}}
+set a(0-8789) {NAME ACC1-3:slc(acc.idiv#4)#9 TYPE READSLICE PAR 0-7009 XREFS 48498 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8790 {}}} CYCLES {}}
+set a(0-8790) {NAME ACC1-3:exs#76 TYPE SIGNEXTEND PAR 0-7009 XREFS 48499 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8789 {}}} SUCCS {{259 0 0-8791 {}}} CYCLES {}}
+set a(0-8791) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#500 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48500 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8788 {}} {259 0 0-8790 {}}} SUCCS {{259 0 0-8792 {}}} CYCLES {}}
+set a(0-8792) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#560 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48501 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-8786 {}} {259 0 0-8791 {}}} SUCCS {{258 0 0-8804 {}}} CYCLES {}}
+set a(0-8793) {NAME ACC1-3:slc(acc.idiv#4)#11 TYPE READSLICE PAR 0-7009 XREFS 48502 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8794 {}}} CYCLES {}}
+set a(0-8794) {NAME ACC1-3:exs#77 TYPE SIGNEXTEND PAR 0-7009 XREFS 48503 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8793 {}}} SUCCS {{258 0 0-8797 {}}} CYCLES {}}
+set a(0-8795) {NAME ACC1-3:slc(acc.idiv#4)#1 TYPE READSLICE PAR 0-7009 XREFS 48504 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8796 {}}} CYCLES {}}
+set a(0-8796) {NAME ACC1-3:exs#72 TYPE SIGNEXTEND PAR 0-7009 XREFS 48505 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8795 {}}} SUCCS {{259 0 0-8797 {}}} CYCLES {}}
+set a(0-8797) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#499 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48506 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8794 {}} {259 0 0-8796 {}}} SUCCS {{258 0 0-8803 {}}} CYCLES {}}
+set a(0-8798) {NAME ACC1-3:slc(acc.idiv#4)#3 TYPE READSLICE PAR 0-7009 XREFS 48507 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8799 {}}} CYCLES {}}
+set a(0-8799) {NAME ACC1-3:exs#73 TYPE SIGNEXTEND PAR 0-7009 XREFS 48508 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8798 {}}} SUCCS {{258 0 0-8802 {}}} CYCLES {}}
+set a(0-8800) {NAME ACC1-3:slc(acc.idiv#4)#5 TYPE READSLICE PAR 0-7009 XREFS 48509 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8801 {}}} CYCLES {}}
+set a(0-8801) {NAME ACC1-3:exs#74 TYPE SIGNEXTEND PAR 0-7009 XREFS 48510 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8800 {}}} SUCCS {{259 0 0-8802 {}}} CYCLES {}}
+set a(0-8802) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#498 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48511 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8799 {}} {259 0 0-8801 {}}} SUCCS {{259 0 0-8803 {}}} CYCLES {}}
+set a(0-8803) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#559 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48512 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-8797 {}} {259 0 0-8802 {}}} SUCCS {{259 0 0-8804 {}}} CYCLES {}}
+set a(0-8804) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#595 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48513 LOC {1 0.23489417499999998 1 0.583372325 1 0.583372325 1 0.6367193451789506 1 0.7731191701789504} PREDS {{258 0 0-8792 {}} {259 0 0-8803 {}}} SUCCS {{258 0 0-8828 {}}} CYCLES {}}
+set a(0-8805) {NAME ACC1-3:slc(acc.idiv#4)#7 TYPE READSLICE PAR 0-7009 XREFS 48514 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8806 {}}} CYCLES {}}
+set a(0-8806) {NAME ACC1-3:exs#75 TYPE SIGNEXTEND PAR 0-7009 XREFS 48515 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8805 {}}} SUCCS {{258 0 0-8809 {}}} CYCLES {}}
+set a(0-8807) {NAME ACC1-3:slc(acc.idiv#4)#15 TYPE READSLICE PAR 0-7009 XREFS 48516 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8808 {}}} CYCLES {}}
+set a(0-8808) {NAME ACC1-3:exs#79 TYPE SIGNEXTEND PAR 0-7009 XREFS 48517 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8807 {}}} SUCCS {{259 0 0-8809 {}}} CYCLES {}}
+set a(0-8809) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#497 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48518 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8806 {}} {259 0 0-8808 {}}} SUCCS {{258 0 0-8815 {}}} CYCLES {}}
+set a(0-8810) {NAME ACC1-3:slc(acc.idiv#4)#17 TYPE READSLICE PAR 0-7009 XREFS 48519 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8811 {}}} CYCLES {}}
+set a(0-8811) {NAME ACC1-3:exs#80 TYPE SIGNEXTEND PAR 0-7009 XREFS 48520 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8810 {}}} SUCCS {{258 0 0-8814 {}}} CYCLES {}}
+set a(0-8812) {NAME ACC1-3:slc(acc.idiv#4)#13 TYPE READSLICE PAR 0-7009 XREFS 48521 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8813 {}}} CYCLES {}}
+set a(0-8813) {NAME ACC1-3:exs#78 TYPE SIGNEXTEND PAR 0-7009 XREFS 48522 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8812 {}}} SUCCS {{259 0 0-8814 {}}} CYCLES {}}
+set a(0-8814) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#496 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48523 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8811 {}} {259 0 0-8813 {}}} SUCCS {{259 0 0-8815 {}}} CYCLES {}}
+set a(0-8815) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#558 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48524 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-8809 {}} {259 0 0-8814 {}}} SUCCS {{258 0 0-8827 {}}} CYCLES {}}
+set a(0-8816) {NAME ACC1-3:slc(acc.idiv#4)#23 TYPE READSLICE PAR 0-7009 XREFS 48525 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8817 {}}} CYCLES {}}
+set a(0-8817) {NAME ACC1-3:exs#83 TYPE SIGNEXTEND PAR 0-7009 XREFS 48526 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8816 {}}} SUCCS {{258 0 0-8820 {}}} CYCLES {}}
+set a(0-8818) {NAME ACC1-3:slc(acc.idiv#4)#19 TYPE READSLICE PAR 0-7009 XREFS 48527 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8819 {}}} CYCLES {}}
+set a(0-8819) {NAME ACC1-3:exs#81 TYPE SIGNEXTEND PAR 0-7009 XREFS 48528 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8818 {}}} SUCCS {{259 0 0-8820 {}}} CYCLES {}}
+set a(0-8820) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#495 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48529 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8817 {}} {259 0 0-8819 {}}} SUCCS {{258 0 0-8826 {}}} CYCLES {}}
+set a(0-8821) {NAME ACC1-3:slc(acc.idiv#4)#21 TYPE READSLICE PAR 0-7009 XREFS 48530 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8822 {}}} CYCLES {}}
+set a(0-8822) {NAME ACC1-3:exs#82 TYPE SIGNEXTEND PAR 0-7009 XREFS 48531 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8821 {}}} SUCCS {{258 0 0-8825 {}}} CYCLES {}}
+set a(0-8823) {NAME ACC1-3:slc(acc.idiv#4)#31 TYPE READSLICE PAR 0-7009 XREFS 48532 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8824 {}}} CYCLES {}}
+set a(0-8824) {NAME ACC1-3:exs#87 TYPE SIGNEXTEND PAR 0-7009 XREFS 48533 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-8823 {}}} SUCCS {{259 0 0-8825 {}}} CYCLES {}}
+set a(0-8825) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#494 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48534 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-8822 {}} {259 0 0-8824 {}}} SUCCS {{259 0 0-8826 {}}} CYCLES {}}
+set a(0-8826) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#557 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48535 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-8820 {}} {259 0 0-8825 {}}} SUCCS {{259 0 0-8827 {}}} CYCLES {}}
+set a(0-8827) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#594 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48536 LOC {1 0.23489417499999998 1 0.583372325 1 0.583372325 1 0.6367193451789506 1 0.7731191701789504} PREDS {{258 0 0-8815 {}} {259 0 0-8826 {}}} SUCCS {{259 0 0-8828 {}}} CYCLES {}}
+set a(0-8828) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#612 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-7009 XREFS 48537 LOC {1 0.28824125 1 0.6367193999999999 1 0.6367193999999999 1 0.695319109496936 1 0.831718934496936} PREDS {{258 0 0-8804 {}} {259 0 0-8827 {}}} SUCCS {{259 0 0-8829 {}}} CYCLES {}}
+set a(0-8829) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#626 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-7009 XREFS 48538 LOC {1 0.346841 1 0.69531915 1 0.69531915 1 0.7588311234103025 1 0.8952309484103024} PREDS {{258 0 0-8781 {}} {259 0 0-8828 {}}} SUCCS {{259 0 0-8830 {}}} CYCLES {}}
+set a(0-8830) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#638 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-7009 XREFS 48539 LOC {1 0.410353025 1 0.758831175 1 0.758831175 1 0.8112156277684257 1 0.9476154527684257} PREDS {{258 0 0-8734 {}} {259 0 0-8829 {}}} SUCCS {{258 0 0-9113 {}}} CYCLES {}}
+set a(0-8831) {NAME ACC1-3:slc(acc#20.psp)#65 TYPE READSLICE PAR 0-7009 XREFS 48540 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8832 {}}} CYCLES {}}
+set a(0-8832) {NAME ACC1-3:exs#1039 TYPE SIGNEXTEND PAR 0-7009 XREFS 48541 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8831 {}}} SUCCS {{258 0 0-8835 {}}} CYCLES {}}
+set a(0-8833) {NAME ACC1-3:slc(acc.idiv#4)#27 TYPE READSLICE PAR 0-7009 XREFS 48542 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8834 {}}} CYCLES {}}
+set a(0-8834) {NAME ACC1-3:exs#85 TYPE SIGNEXTEND PAR 0-7009 XREFS 48543 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8833 {}}} SUCCS {{259 0 0-8835 {}}} CYCLES {}}
+set a(0-8835) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#493 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48544 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-8832 {}} {259 0 0-8834 {}}} SUCCS {{258 0 0-8841 {}}} CYCLES {}}
+set a(0-8836) {NAME ACC1-3:slc(acc.idiv#4)#29 TYPE READSLICE PAR 0-7009 XREFS 48545 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8837 {}}} CYCLES {}}
+set a(0-8837) {NAME ACC1-3:exs#86 TYPE SIGNEXTEND PAR 0-7009 XREFS 48546 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8836 {}}} SUCCS {{258 0 0-8840 {}}} CYCLES {}}
+set a(0-8838) {NAME ACC1-3:slc(acc.idiv#5)#9 TYPE READSLICE PAR 0-7009 XREFS 48547 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8839 {}}} CYCLES {}}
+set a(0-8839) {NAME ACC1-3:exs#94 TYPE SIGNEXTEND PAR 0-7009 XREFS 48548 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8838 {}}} SUCCS {{259 0 0-8840 {}}} CYCLES {}}
+set a(0-8840) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#492 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48549 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-8837 {}} {259 0 0-8839 {}}} SUCCS {{259 0 0-8841 {}}} CYCLES {}}
+set a(0-8841) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#556 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48550 LOC {1 0.187338 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-8835 {}} {259 0 0-8840 {}}} SUCCS {{258 0 0-8853 {}}} CYCLES {}}
+set a(0-8842) {NAME ACC1-3:slc(acc.idiv#5)#11 TYPE READSLICE PAR 0-7009 XREFS 48551 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8843 {}}} CYCLES {}}
+set a(0-8843) {NAME ACC1-3:exs#95 TYPE SIGNEXTEND PAR 0-7009 XREFS 48552 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8842 {}}} SUCCS {{258 0 0-8846 {}}} CYCLES {}}
+set a(0-8844) {NAME ACC1-3:slc(acc.idiv#5)#35 TYPE READSLICE PAR 0-7009 XREFS 48553 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8845 {}}} CYCLES {}}
+set a(0-8845) {NAME ACC1-3:exs#107 TYPE SIGNEXTEND PAR 0-7009 XREFS 48554 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8844 {}}} SUCCS {{259 0 0-8846 {}}} CYCLES {}}
+set a(0-8846) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#491 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48555 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-8843 {}} {259 0 0-8845 {}}} SUCCS {{258 0 0-8852 {}}} CYCLES {}}
+set a(0-8847) {NAME ACC1:slc(acc#25.psp#2)#28 TYPE READSLICE PAR 0-7009 XREFS 48556 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8848 {}}} CYCLES {}}
+set a(0-8848) {NAME ACC1-2:exs#94 TYPE SIGNEXTEND PAR 0-7009 XREFS 48557 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8847 {}}} SUCCS {{258 0 0-8851 {}}} CYCLES {}}
+set a(0-8849) {NAME ACC1:slc(acc#25.psp#2)#29 TYPE READSLICE PAR 0-7009 XREFS 48558 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8850 {}}} CYCLES {}}
+set a(0-8850) {NAME ACC1-2:exs#95 TYPE SIGNEXTEND PAR 0-7009 XREFS 48559 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8849 {}}} SUCCS {{259 0 0-8851 {}}} CYCLES {}}
+set a(0-8851) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#489 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48560 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-8848 {}} {259 0 0-8850 {}}} SUCCS {{259 0 0-8852 {}}} CYCLES {}}
+set a(0-8852) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#555 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48561 LOC {1 0.187338 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-8846 {}} {259 0 0-8851 {}}} SUCCS {{259 0 0-8853 {}}} CYCLES {}}
+set a(0-8853) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#593 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48562 LOC {1 0.23489417499999998 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-8841 {}} {259 0 0-8852 {}}} SUCCS {{258 0 0-8877 {}}} CYCLES {}}
+set a(0-8854) {NAME ACC1:slc(acc#25.psp#2)#30 TYPE READSLICE PAR 0-7009 XREFS 48563 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8855 {}}} CYCLES {}}
+set a(0-8855) {NAME ACC1-2:exs#90 TYPE SIGNEXTEND PAR 0-7009 XREFS 48564 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8854 {}}} SUCCS {{258 0 0-8858 {}}} CYCLES {}}
+set a(0-8856) {NAME ACC1:slc(acc#25.psp#2)#31 TYPE READSLICE PAR 0-7009 XREFS 48565 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8857 {}}} CYCLES {}}
+set a(0-8857) {NAME ACC1-2:exs#91 TYPE SIGNEXTEND PAR 0-7009 XREFS 48566 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8856 {}}} SUCCS {{259 0 0-8858 {}}} CYCLES {}}
+set a(0-8858) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#488 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48567 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-8855 {}} {259 0 0-8857 {}}} SUCCS {{258 0 0-8864 {}}} CYCLES {}}
+set a(0-8859) {NAME ACC1:slc(acc#25.psp#2)#32 TYPE READSLICE PAR 0-7009 XREFS 48568 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8860 {}}} CYCLES {}}
+set a(0-8860) {NAME ACC1-2:exs#92 TYPE SIGNEXTEND PAR 0-7009 XREFS 48569 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8859 {}}} SUCCS {{258 0 0-8863 {}}} CYCLES {}}
+set a(0-8861) {NAME ACC1:slc(acc#25.psp#2)#33 TYPE READSLICE PAR 0-7009 XREFS 48570 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8862 {}}} CYCLES {}}
+set a(0-8862) {NAME ACC1-2:exs#93 TYPE SIGNEXTEND PAR 0-7009 XREFS 48571 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8861 {}}} SUCCS {{259 0 0-8863 {}}} CYCLES {}}
+set a(0-8863) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#487 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48572 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-8860 {}} {259 0 0-8862 {}}} SUCCS {{259 0 0-8864 {}}} CYCLES {}}
+set a(0-8864) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#554 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48573 LOC {1 0.187338 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-8858 {}} {259 0 0-8863 {}}} SUCCS {{258 0 0-8876 {}}} CYCLES {}}
+set a(0-8865) {NAME ACC1:slc(acc#25.psp#2)#34 TYPE READSLICE PAR 0-7009 XREFS 48574 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8866 {}}} CYCLES {}}
+set a(0-8866) {NAME ACC1-2:exs#99 TYPE SIGNEXTEND PAR 0-7009 XREFS 48575 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8865 {}}} SUCCS {{258 0 0-8869 {}}} CYCLES {}}
+set a(0-8867) {NAME ACC1:slc(acc#25.psp#2)#35 TYPE READSLICE PAR 0-7009 XREFS 48576 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8868 {}}} CYCLES {}}
+set a(0-8868) {NAME ACC1-2:exs#100 TYPE SIGNEXTEND PAR 0-7009 XREFS 48577 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8867 {}}} SUCCS {{259 0 0-8869 {}}} CYCLES {}}
+set a(0-8869) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#486 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48578 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-8866 {}} {259 0 0-8868 {}}} SUCCS {{258 0 0-8875 {}}} CYCLES {}}
+set a(0-8870) {NAME ACC1:slc(acc#25.psp#2)#36 TYPE READSLICE PAR 0-7009 XREFS 48579 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8871 {}}} CYCLES {}}
+set a(0-8871) {NAME ACC1-2:exs#96 TYPE SIGNEXTEND PAR 0-7009 XREFS 48580 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8870 {}}} SUCCS {{258 0 0-8874 {}}} CYCLES {}}
+set a(0-8872) {NAME ACC1:slc(acc#25.psp#2)#37 TYPE READSLICE PAR 0-7009 XREFS 48581 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8873 {}}} CYCLES {}}
+set a(0-8873) {NAME ACC1-2:exs#97 TYPE SIGNEXTEND PAR 0-7009 XREFS 48582 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8872 {}}} SUCCS {{259 0 0-8874 {}}} CYCLES {}}
+set a(0-8874) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#485 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48583 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-8871 {}} {259 0 0-8873 {}}} SUCCS {{259 0 0-8875 {}}} CYCLES {}}
+set a(0-8875) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#553 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48584 LOC {1 0.187338 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-8869 {}} {259 0 0-8874 {}}} SUCCS {{259 0 0-8876 {}}} CYCLES {}}
+set a(0-8876) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#592 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48585 LOC {1 0.23489417499999998 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-8864 {}} {259 0 0-8875 {}}} SUCCS {{259 0 0-8877 {}}} CYCLES {}}
+set a(0-8877) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#611 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-7009 XREFS 48586 LOC {1 0.28824125 1 0.620914525 1 0.620914525 1 0.679514234496936 1 0.815914059496936} PREDS {{258 0 0-8853 {}} {259 0 0-8876 {}}} SUCCS {{258 0 0-8935 {}}} CYCLES {}}
+set a(0-8878) {NAME ACC1:slc(acc#25.psp#2)#38 TYPE READSLICE PAR 0-7009 XREFS 48587 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8879 {}}} CYCLES {}}
+set a(0-8879) {NAME ACC1-2:exs#98 TYPE SIGNEXTEND PAR 0-7009 XREFS 48588 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8878 {}}} SUCCS {{258 0 0-8882 {}}} CYCLES {}}
+set a(0-8880) {NAME ACC1:slc(acc#25.psp#2)#39 TYPE READSLICE PAR 0-7009 XREFS 48589 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8881 {}}} CYCLES {}}
+set a(0-8881) {NAME ACC1-2:exs#102 TYPE SIGNEXTEND PAR 0-7009 XREFS 48590 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8880 {}}} SUCCS {{259 0 0-8882 {}}} CYCLES {}}
+set a(0-8882) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#484 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48591 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-8879 {}} {259 0 0-8881 {}}} SUCCS {{258 0 0-8888 {}}} CYCLES {}}
+set a(0-8883) {NAME ACC1:slc(acc#25.psp#2)#40 TYPE READSLICE PAR 0-7009 XREFS 48592 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8884 {}}} CYCLES {}}
+set a(0-8884) {NAME ACC1-2:exs#353 TYPE SIGNEXTEND PAR 0-7009 XREFS 48593 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8883 {}}} SUCCS {{258 0 0-8887 {}}} CYCLES {}}
+set a(0-8885) {NAME ACC1:slc(acc#25.psp#2)#41 TYPE READSLICE PAR 0-7009 XREFS 48594 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8886 {}}} CYCLES {}}
+set a(0-8886) {NAME ACC1-2:exs#101 TYPE SIGNEXTEND PAR 0-7009 XREFS 48595 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8885 {}}} SUCCS {{259 0 0-8887 {}}} CYCLES {}}
+set a(0-8887) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#483 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48596 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-8884 {}} {259 0 0-8886 {}}} SUCCS {{259 0 0-8888 {}}} CYCLES {}}
+set a(0-8888) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#552 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48597 LOC {1 0.187338 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-8882 {}} {259 0 0-8887 {}}} SUCCS {{258 0 0-8900 {}}} CYCLES {}}
+set a(0-8889) {NAME ACC1:slc(acc#25.psp#2)#51 TYPE READSLICE PAR 0-7009 XREFS 48598 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8890 {}}} CYCLES {}}
+set a(0-8890) {NAME ACC1-2:exs#106 TYPE SIGNEXTEND PAR 0-7009 XREFS 48599 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8889 {}}} SUCCS {{258 0 0-8893 {}}} CYCLES {}}
+set a(0-8891) {NAME ACC1:slc(acc#25.psp#2)#55 TYPE READSLICE PAR 0-7009 XREFS 48600 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8892 {}}} CYCLES {}}
+set a(0-8892) {NAME ACC1-2:exs#963 TYPE SIGNEXTEND PAR 0-7009 XREFS 48601 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8891 {}}} SUCCS {{259 0 0-8893 {}}} CYCLES {}}
+set a(0-8893) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#482 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48602 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-8890 {}} {259 0 0-8892 {}}} SUCCS {{258 0 0-8899 {}}} CYCLES {}}
+set a(0-8894) {NAME ACC1:slc(acc#25.psp#2)#60 TYPE READSLICE PAR 0-7009 XREFS 48603 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8895 {}}} CYCLES {}}
+set a(0-8895) {NAME ACC1-2:exs#103 TYPE SIGNEXTEND PAR 0-7009 XREFS 48604 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8894 {}}} SUCCS {{258 0 0-8898 {}}} CYCLES {}}
+set a(0-8896) {NAME ACC1:slc(acc#25.psp#2)#63 TYPE READSLICE PAR 0-7009 XREFS 48605 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-8897 {}}} CYCLES {}}
+set a(0-8897) {NAME ACC1-2:exs#104 TYPE SIGNEXTEND PAR 0-7009 XREFS 48606 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8896 {}}} SUCCS {{259 0 0-8898 {}}} CYCLES {}}
+set a(0-8898) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#481 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48607 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-8895 {}} {259 0 0-8897 {}}} SUCCS {{259 0 0-8899 {}}} CYCLES {}}
+set a(0-8899) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#551 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48608 LOC {1 0.187338 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-8893 {}} {259 0 0-8898 {}}} SUCCS {{259 0 0-8900 {}}} CYCLES {}}
+set a(0-8900) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#591 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48609 LOC {1 0.23489417499999998 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-8888 {}} {259 0 0-8899 {}}} SUCCS {{258 0 0-8934 {}}} CYCLES {}}
+set a(0-8901) {NAME ACC1-3:slc(acc.idiv#5)#7 TYPE READSLICE PAR 0-7009 XREFS 48610 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8902 {}}} CYCLES {}}
+set a(0-8902) {NAME ACC1-3:exs#93 TYPE SIGNEXTEND PAR 0-7009 XREFS 48611 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8901 {}}} SUCCS {{258 0 0-8905 {}}} CYCLES {}}
+set a(0-8903) {NAME slc(acc#20.psp#1) TYPE READSLICE PAR 0-7009 XREFS 48612 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8904 {}}} CYCLES {}}
+set a(0-8904) {NAME ACC1:exs#1453 TYPE SIGNEXTEND PAR 0-7009 XREFS 48613 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-8903 {}}} SUCCS {{259 0 0-8905 {}}} CYCLES {}}
+set a(0-8905) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#480 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48614 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-8902 {}} {259 0 0-8904 {}}} SUCCS {{258 0 0-8914 {}}} CYCLES {}}
+set a(0-8906) {NAME ACC1-3:slc(acc.idiv#5)#1 TYPE READSLICE PAR 0-7009 XREFS 48615 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8907 {}}} CYCLES {}}
+set a(0-8907) {NAME ACC1-3:exs#90 TYPE SIGNEXTEND PAR 0-7009 XREFS 48616 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8906 {}}} SUCCS {{259 0 0-8908 {}}} CYCLES {}}
+set a(0-8908) {NAME ACC1:conc#1416 TYPE CONCATENATE PAR 0-7009 XREFS 48617 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8907 {}}} SUCCS {{258 0 0-8912 {}}} CYCLES {}}
+set a(0-8909) {NAME ACC1-3:slc(acc.idiv#5)#3 TYPE READSLICE PAR 0-7009 XREFS 48618 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8910 {}}} CYCLES {}}
+set a(0-8910) {NAME ACC1-3:exs#91 TYPE SIGNEXTEND PAR 0-7009 XREFS 48619 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8909 {}}} SUCCS {{259 0 0-8911 {}}} CYCLES {}}
+set a(0-8911) {NAME ACC1:conc#1417 TYPE CONCATENATE PAR 0-7009 XREFS 48620 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-7098 {}} {259 0 0-8910 {}}} SUCCS {{259 0 0-8912 {}}} CYCLES {}}
+set a(0-8912) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#479 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48621 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-8908 {}} {259 0 0-8911 {}}} SUCCS {{259 0 0-8913 {}}} CYCLES {}}
+set a(0-8913) {NAME ACC1:slc#147 TYPE READSLICE PAR 0-7009 XREFS 48622 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-8912 {}}} SUCCS {{259 0 0-8914 {}}} CYCLES {}}
+set a(0-8914) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#550 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48623 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-8905 {}} {259 0 0-8913 {}}} SUCCS {{258 0 0-8933 {}}} CYCLES {}}
+set a(0-8915) {NAME ACC1-3:slc(acc.idiv#5)#5 TYPE READSLICE PAR 0-7009 XREFS 48624 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8916 {}}} CYCLES {}}
+set a(0-8916) {NAME ACC1-3:exs#92 TYPE SIGNEXTEND PAR 0-7009 XREFS 48625 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8915 {}}} SUCCS {{259 0 0-8917 {}}} CYCLES {}}
+set a(0-8917) {NAME ACC1:conc#1414 TYPE CONCATENATE PAR 0-7009 XREFS 48626 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8916 {}}} SUCCS {{258 0 0-8921 {}}} CYCLES {}}
+set a(0-8918) {NAME ACC1-3:slc(acc.idiv#5)#19 TYPE READSLICE PAR 0-7009 XREFS 48627 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7701 {}}} SUCCS {{259 0 0-8919 {}}} CYCLES {}}
+set a(0-8919) {NAME ACC1-3:exs#99 TYPE SIGNEXTEND PAR 0-7009 XREFS 48628 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8918 {}}} SUCCS {{259 0 0-8920 {}}} CYCLES {}}
+set a(0-8920) {NAME ACC1:conc#1415 TYPE CONCATENATE PAR 0-7009 XREFS 48629 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-7093 {}} {259 0 0-8919 {}}} SUCCS {{259 0 0-8921 {}}} CYCLES {}}
+set a(0-8921) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#478 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48630 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-8917 {}} {259 0 0-8920 {}}} SUCCS {{259 0 0-8922 {}}} CYCLES {}}
+set a(0-8922) {NAME ACC1:slc#146 TYPE READSLICE PAR 0-7009 XREFS 48631 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-8921 {}}} SUCCS {{258 0 0-8932 {}}} CYCLES {}}
+set a(0-8923) {NAME ACC1-3:slc(acc.idiv)#17 TYPE READSLICE PAR 0-7009 XREFS 48632 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8924 {}}} CYCLES {}}
+set a(0-8924) {NAME ACC1-3:exs#8 TYPE SIGNEXTEND PAR 0-7009 XREFS 48633 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8923 {}}} SUCCS {{259 0 0-8925 {}}} CYCLES {}}
+set a(0-8925) {NAME ACC1:conc#1412 TYPE CONCATENATE PAR 0-7009 XREFS 48634 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8924 {}}} SUCCS {{258 0 0-8930 {}}} CYCLES {}}
+set a(0-8926) {NAME ACC1-3:slc(acc.idiv)#13 TYPE READSLICE PAR 0-7009 XREFS 48635 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8927 {}}} CYCLES {}}
+set a(0-8927) {NAME ACC1-3:exs#6 TYPE SIGNEXTEND PAR 0-7009 XREFS 48636 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8926 {}}} SUCCS {{258 0 0-8929 {}}} CYCLES {}}
+set a(0-8928) {NAME ACC1:slc(acc.imod#26) TYPE READSLICE PAR 0-7009 XREFS 48637 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.6088549249999999} PREDS {{258 0 0-7080 {}}} SUCCS {{259 0 0-8929 {}}} CYCLES {}}
+set a(0-8929) {NAME ACC1:conc#1413 TYPE CONCATENATE PAR 0-7009 XREFS 48638 LOC {1 0.356432775 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-8927 {}} {259 0 0-8928 {}}} SUCCS {{259 0 0-8930 {}}} CYCLES {}}
+set a(0-8930) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#477 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48639 LOC {1 0.356432775 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-8925 {}} {259 0 0-8929 {}}} SUCCS {{259 0 0-8931 {}}} CYCLES {}}
+set a(0-8931) {NAME ACC1:slc#145 TYPE READSLICE PAR 0-7009 XREFS 48640 LOC {1 0.40398894999999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-8930 {}}} SUCCS {{259 0 0-8932 {}}} CYCLES {}}
+set a(0-8932) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#549 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48641 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-8922 {}} {259 0 0-8931 {}}} SUCCS {{259 0 0-8933 {}}} CYCLES {}}
+set a(0-8933) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#590 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48642 LOC {1 0.47879105 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-8914 {}} {259 0 0-8932 {}}} SUCCS {{259 0 0-8934 {}}} CYCLES {}}
+set a(0-8934) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#610 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-7009 XREFS 48643 LOC {1 0.532138125 1 0.620914525 1 0.620914525 1 0.679514234496936 1 0.815914059496936} PREDS {{258 0 0-8900 {}} {259 0 0-8933 {}}} SUCCS {{259 0 0-8935 {}}} CYCLES {}}
+set a(0-8935) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#625 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-7009 XREFS 48644 LOC {1 0.590737875 1 0.679514275 1 0.679514275 1 0.7430262484103024 1 0.8794260734103024} PREDS {{258 0 0-8877 {}} {259 0 0-8934 {}}} SUCCS {{258 0 0-9112 {}}} CYCLES {}}
+set a(0-8936) {NAME ACC1-3:slc(acc.idiv)#23 TYPE READSLICE PAR 0-7009 XREFS 48645 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8937 {}}} CYCLES {}}
+set a(0-8937) {NAME ACC1-3:exs#11 TYPE SIGNEXTEND PAR 0-7009 XREFS 48646 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8936 {}}} SUCCS {{259 0 0-8938 {}}} CYCLES {}}
+set a(0-8938) {NAME ACC1:conc#1410 TYPE CONCATENATE PAR 0-7009 XREFS 48647 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8937 {}}} SUCCS {{258 0 0-8943 {}}} CYCLES {}}
+set a(0-8939) {NAME ACC1-3:slc(acc.idiv)#19 TYPE READSLICE PAR 0-7009 XREFS 48648 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8940 {}}} CYCLES {}}
+set a(0-8940) {NAME ACC1-3:exs#9 TYPE SIGNEXTEND PAR 0-7009 XREFS 48649 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8939 {}}} SUCCS {{258 0 0-8942 {}}} CYCLES {}}
+set a(0-8941) {NAME ACC1:slc(ACC1:acc#210.psp#2)#2 TYPE READSLICE PAR 0-7009 XREFS 48650 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.6088549249999999} PREDS {{258 0 0-7062 {}}} SUCCS {{259 0 0-8942 {}}} CYCLES {}}
+set a(0-8942) {NAME ACC1:conc#1411 TYPE CONCATENATE PAR 0-7009 XREFS 48651 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-8940 {}} {259 0 0-8941 {}}} SUCCS {{259 0 0-8943 {}}} CYCLES {}}
+set a(0-8943) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#476 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48652 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-8938 {}} {259 0 0-8942 {}}} SUCCS {{259 0 0-8944 {}}} CYCLES {}}
+set a(0-8944) {NAME ACC1:slc#144 TYPE READSLICE PAR 0-7009 XREFS 48653 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-8943 {}}} SUCCS {{258 0 0-8954 {}}} CYCLES {}}
+set a(0-8945) {NAME ACC1-3:slc(acc.idiv)#21 TYPE READSLICE PAR 0-7009 XREFS 48654 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8946 {}}} CYCLES {}}
+set a(0-8946) {NAME ACC1-3:exs#10 TYPE SIGNEXTEND PAR 0-7009 XREFS 48655 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8945 {}}} SUCCS {{259 0 0-8947 {}}} CYCLES {}}
+set a(0-8947) {NAME ACC1:conc#1408 TYPE CONCATENATE PAR 0-7009 XREFS 48656 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8946 {}}} SUCCS {{258 0 0-8952 {}}} CYCLES {}}
+set a(0-8948) {NAME ACC1-3:slc(acc.idiv)#31 TYPE READSLICE PAR 0-7009 XREFS 48657 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8949 {}}} CYCLES {}}
+set a(0-8949) {NAME ACC1-3:exs#15 TYPE SIGNEXTEND PAR 0-7009 XREFS 48658 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8948 {}}} SUCCS {{258 0 0-8951 {}}} CYCLES {}}
+set a(0-8950) {NAME ACC1:slc(ACC1:acc#210.psp#2)#1 TYPE READSLICE PAR 0-7009 XREFS 48659 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.6088549249999999} PREDS {{258 0 0-7062 {}}} SUCCS {{259 0 0-8951 {}}} CYCLES {}}
+set a(0-8951) {NAME ACC1:conc#1409 TYPE CONCATENATE PAR 0-7009 XREFS 48660 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-8949 {}} {259 0 0-8950 {}}} SUCCS {{259 0 0-8952 {}}} CYCLES {}}
+set a(0-8952) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#475 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48661 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-8947 {}} {259 0 0-8951 {}}} SUCCS {{259 0 0-8953 {}}} CYCLES {}}
+set a(0-8953) {NAME ACC1:slc#143 TYPE READSLICE PAR 0-7009 XREFS 48662 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-8952 {}}} SUCCS {{259 0 0-8954 {}}} CYCLES {}}
+set a(0-8954) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#548 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48663 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-8944 {}} {259 0 0-8953 {}}} SUCCS {{258 0 0-8974 {}}} CYCLES {}}
+set a(0-8955) {NAME ACC1-3:slc(acc.idiv)#9 TYPE READSLICE PAR 0-7009 XREFS 48664 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8956 {}}} CYCLES {}}
+set a(0-8956) {NAME ACC1-3:exs#4 TYPE SIGNEXTEND PAR 0-7009 XREFS 48665 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8955 {}}} SUCCS {{259 0 0-8957 {}}} CYCLES {}}
+set a(0-8957) {NAME ACC1:conc#1406 TYPE CONCATENATE PAR 0-7009 XREFS 48666 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8956 {}}} SUCCS {{258 0 0-8962 {}}} CYCLES {}}
+set a(0-8958) {NAME ACC1-3:slc(acc.idiv)#11 TYPE READSLICE PAR 0-7009 XREFS 48667 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8959 {}}} CYCLES {}}
+set a(0-8959) {NAME ACC1-3:exs#5 TYPE SIGNEXTEND PAR 0-7009 XREFS 48668 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8958 {}}} SUCCS {{258 0 0-8961 {}}} CYCLES {}}
+set a(0-8960) {NAME ACC1:slc(ACC1:acc#210.psp#2) TYPE READSLICE PAR 0-7009 XREFS 48669 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.6088549249999999} PREDS {{258 0 0-7062 {}}} SUCCS {{259 0 0-8961 {}}} CYCLES {}}
+set a(0-8961) {NAME ACC1:conc#1407 TYPE CONCATENATE PAR 0-7009 XREFS 48670 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-8959 {}} {259 0 0-8960 {}}} SUCCS {{259 0 0-8962 {}}} CYCLES {}}
+set a(0-8962) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#474 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48671 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-8957 {}} {259 0 0-8961 {}}} SUCCS {{259 0 0-8963 {}}} CYCLES {}}
+set a(0-8963) {NAME ACC1:slc#142 TYPE READSLICE PAR 0-7009 XREFS 48672 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-8962 {}}} SUCCS {{258 0 0-8973 {}}} CYCLES {}}
+set a(0-8964) {NAME ACC1-3:slc(acc.idiv)#1 TYPE READSLICE PAR 0-7009 XREFS 48673 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8965 {}}} CYCLES {}}
+set a(0-8965) {NAME ACC1-3:exs#951 TYPE SIGNEXTEND PAR 0-7009 XREFS 48674 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8964 {}}} SUCCS {{259 0 0-8966 {}}} CYCLES {}}
+set a(0-8966) {NAME ACC1:conc#1404 TYPE CONCATENATE PAR 0-7009 XREFS 48675 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8965 {}}} SUCCS {{258 0 0-8971 {}}} CYCLES {}}
+set a(0-8967) {NAME ACC1-3:slc(acc.idiv)#3 TYPE READSLICE PAR 0-7009 XREFS 48676 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8968 {}}} CYCLES {}}
+set a(0-8968) {NAME ACC1-3:exs#1 TYPE SIGNEXTEND PAR 0-7009 XREFS 48677 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8967 {}}} SUCCS {{258 0 0-8970 {}}} CYCLES {}}
+set a(0-8969) {NAME ACC1:slc(acc.psp#2)#7 TYPE READSLICE PAR 0-7009 XREFS 48678 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6088549249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8970 {}}} CYCLES {}}
+set a(0-8970) {NAME ACC1:conc#1405 TYPE CONCATENATE PAR 0-7009 XREFS 48679 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-8968 {}} {259 0 0-8969 {}}} SUCCS {{259 0 0-8971 {}}} CYCLES {}}
+set a(0-8971) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#473 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48680 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-8966 {}} {259 0 0-8970 {}}} SUCCS {{259 0 0-8972 {}}} CYCLES {}}
+set a(0-8972) {NAME ACC1:slc#141 TYPE READSLICE PAR 0-7009 XREFS 48681 LOC {1 0.194111125 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-8971 {}}} SUCCS {{259 0 0-8973 {}}} CYCLES {}}
+set a(0-8973) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#547 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48682 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-8963 {}} {259 0 0-8972 {}}} SUCCS {{259 0 0-8974 {}}} CYCLES {}}
+set a(0-8974) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#589 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48683 LOC {1 0.36304335 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-8954 {}} {259 0 0-8973 {}}} SUCCS {{258 0 0-9021 {}}} CYCLES {}}
+set a(0-8975) {NAME ACC1-3:slc(acc.idiv)#5 TYPE READSLICE PAR 0-7009 XREFS 48684 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8976 {}}} CYCLES {}}
+set a(0-8976) {NAME ACC1-3:exs#2 TYPE SIGNEXTEND PAR 0-7009 XREFS 48685 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8975 {}}} SUCCS {{259 0 0-8977 {}}} CYCLES {}}
+set a(0-8977) {NAME ACC1:conc#1402 TYPE CONCATENATE PAR 0-7009 XREFS 48686 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8976 {}}} SUCCS {{258 0 0-8982 {}}} CYCLES {}}
+set a(0-8978) {NAME ACC1-3:slc(acc.idiv)#7 TYPE READSLICE PAR 0-7009 XREFS 48687 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-8979 {}}} CYCLES {}}
+set a(0-8979) {NAME ACC1-3:exs#3 TYPE SIGNEXTEND PAR 0-7009 XREFS 48688 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8978 {}}} SUCCS {{258 0 0-8981 {}}} CYCLES {}}
+set a(0-8980) {NAME ACC1:slc(acc.psp#2)#6 TYPE READSLICE PAR 0-7009 XREFS 48689 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6088549249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8981 {}}} CYCLES {}}
+set a(0-8981) {NAME ACC1:conc#1403 TYPE CONCATENATE PAR 0-7009 XREFS 48690 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-8979 {}} {259 0 0-8980 {}}} SUCCS {{259 0 0-8982 {}}} CYCLES {}}
+set a(0-8982) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#472 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48691 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-8977 {}} {259 0 0-8981 {}}} SUCCS {{259 0 0-8983 {}}} CYCLES {}}
+set a(0-8983) {NAME ACC1:slc#140 TYPE READSLICE PAR 0-7009 XREFS 48692 LOC {1 0.194111125 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-8982 {}}} SUCCS {{258 0 0-8993 {}}} CYCLES {}}
+set a(0-8984) {NAME ACC1-1:slc(acc#10.psp)#67 TYPE READSLICE PAR 0-7009 XREFS 48693 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-8985 {}}} CYCLES {}}
+set a(0-8985) {NAME ACC1-1:exs#52 TYPE SIGNEXTEND PAR 0-7009 XREFS 48694 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8984 {}}} SUCCS {{259 0 0-8986 {}}} CYCLES {}}
+set a(0-8986) {NAME ACC1:conc#1398 TYPE CONCATENATE PAR 0-7009 XREFS 48695 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8985 {}}} SUCCS {{258 0 0-8991 {}}} CYCLES {}}
+set a(0-8987) {NAME ACC1-1:slc(acc#10.psp)#66 TYPE READSLICE PAR 0-7009 XREFS 48696 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-8988 {}}} CYCLES {}}
+set a(0-8988) {NAME ACC1-1:exs#53 TYPE SIGNEXTEND PAR 0-7009 XREFS 48697 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8987 {}}} SUCCS {{258 0 0-8990 {}}} CYCLES {}}
+set a(0-8989) {NAME ACC1:slc(acc.psp#2)#4 TYPE READSLICE PAR 0-7009 XREFS 48698 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6088549249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-8990 {}}} CYCLES {}}
+set a(0-8990) {NAME ACC1:conc#1399 TYPE CONCATENATE PAR 0-7009 XREFS 48699 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-8988 {}} {259 0 0-8989 {}}} SUCCS {{259 0 0-8991 {}}} CYCLES {}}
+set a(0-8991) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#470 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48700 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-8986 {}} {259 0 0-8990 {}}} SUCCS {{259 0 0-8992 {}}} CYCLES {}}
+set a(0-8992) {NAME ACC1:slc#138 TYPE READSLICE PAR 0-7009 XREFS 48701 LOC {1 0.194111125 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-8991 {}}} SUCCS {{259 0 0-8993 {}}} CYCLES {}}
+set a(0-8993) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#546 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48702 LOC {1 0.194111125 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-8983 {}} {259 0 0-8992 {}}} SUCCS {{258 0 0-9020 {}}} CYCLES {}}
+set a(0-8994) {NAME ACC1-1:slc(acc#10.psp)#65 TYPE READSLICE PAR 0-7009 XREFS 48703 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-8995 {}}} CYCLES {}}
+set a(0-8995) {NAME ACC1-1:exs#40 TYPE SIGNEXTEND PAR 0-7009 XREFS 48704 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8994 {}}} SUCCS {{259 0 0-8996 {}}} CYCLES {}}
+set a(0-8996) {NAME ACC1:conc#1396 TYPE CONCATENATE PAR 0-7009 XREFS 48705 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8995 {}}} SUCCS {{258 0 0-9005 {}}} CYCLES {}}
+set a(0-8997) {NAME ACC1-1:slc(acc#10.psp)#64 TYPE READSLICE PAR 0-7009 XREFS 48706 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-8998 {}}} CYCLES {}}
+set a(0-8998) {NAME ACC1-1:exs#41 TYPE SIGNEXTEND PAR 0-7009 XREFS 48707 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-8997 {}}} SUCCS {{258 0 0-9004 {}}} CYCLES {}}
+set a(0-8999) {NAME ACC1-3:slc(acc.idiv#1)#45 TYPE READSLICE PAR 0-7009 XREFS 48708 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6088549249999999} PREDS {{258 0 0-7554 {}}} SUCCS {{258 0 0-9003 {}}} CYCLES {}}
+set a(0-9000) {NAME ACC1-3:slc(acc.imod#7)#1 TYPE READSLICE PAR 0-7009 XREFS 48709 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-7621 {}}} SUCCS {{259 0 0-9001 {}}} CYCLES {}}
+set a(0-9001) {NAME ACC1-3:not#60 TYPE NOT PAR 0-7009 XREFS 48710 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9000 {}}} SUCCS {{258 0 0-9003 {}}} CYCLES {}}
+set a(0-9002) {NAME ACC1-3:slc(acc.imod#7)#2 TYPE READSLICE PAR 0-7009 XREFS 48711 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-7621 {}}} SUCCS {{259 0 0-9003 {}}} CYCLES {}}
+set a(0-9003) {NAME ACC1-3:and#3 TYPE AND PAR 0-7009 XREFS 48712 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9001 {}} {258 0 0-8999 {}} {259 0 0-9002 {}}} SUCCS {{259 0 0-9004 {}}} CYCLES {}}
+set a(0-9004) {NAME ACC1:conc#1397 TYPE CONCATENATE PAR 0-7009 XREFS 48713 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-8998 {}} {259 0 0-9003 {}}} SUCCS {{259 0 0-9005 {}}} CYCLES {}}
+set a(0-9005) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#469 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48714 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-8996 {}} {259 0 0-9004 {}}} SUCCS {{259 0 0-9006 {}}} CYCLES {}}
+set a(0-9006) {NAME ACC1:slc#137 TYPE READSLICE PAR 0-7009 XREFS 48715 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-9005 {}}} SUCCS {{258 0 0-9019 {}}} CYCLES {}}
+set a(0-9007) {NAME ACC1-1:slc(acc#10.psp)#63 TYPE READSLICE PAR 0-7009 XREFS 48716 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9008 {}}} CYCLES {}}
+set a(0-9008) {NAME ACC1-1:exs#36 TYPE SIGNEXTEND PAR 0-7009 XREFS 48717 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9007 {}}} SUCCS {{259 0 0-9009 {}}} CYCLES {}}
+set a(0-9009) {NAME ACC1:conc#1394 TYPE CONCATENATE PAR 0-7009 XREFS 48718 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9008 {}}} SUCCS {{258 0 0-9017 {}}} CYCLES {}}
+set a(0-9010) {NAME ACC1-1:slc(acc#10.psp)#62 TYPE READSLICE PAR 0-7009 XREFS 48719 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9011 {}}} CYCLES {}}
+set a(0-9011) {NAME ACC1-1:exs#37 TYPE SIGNEXTEND PAR 0-7009 XREFS 48720 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9010 {}}} SUCCS {{258 0 0-9016 {}}} CYCLES {}}
+set a(0-9012) {NAME ACC1-3:slc(acc.imod#7) TYPE READSLICE PAR 0-7009 XREFS 48721 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-7621 {}}} SUCCS {{258 0 0-9015 {}}} CYCLES {}}
+set a(0-9013) {NAME ACC1-3:slc(acc.idiv#1)#44 TYPE READSLICE PAR 0-7009 XREFS 48722 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6088549249999999} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-9014 {}}} CYCLES {}}
+set a(0-9014) {NAME ACC1-3:not#59 TYPE NOT PAR 0-7009 XREFS 48723 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9013 {}}} SUCCS {{259 0 0-9015 {}}} CYCLES {}}
+set a(0-9015) {NAME ACC1-3:nand#1 TYPE NAND PAR 0-7009 XREFS 48724 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9012 {}} {259 0 0-9014 {}}} SUCCS {{259 0 0-9016 {}}} CYCLES {}}
+set a(0-9016) {NAME ACC1:conc#1395 TYPE CONCATENATE PAR 0-7009 XREFS 48725 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9011 {}} {259 0 0-9015 {}}} SUCCS {{259 0 0-9017 {}}} CYCLES {}}
+set a(0-9017) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#468 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48726 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-9009 {}} {259 0 0-9016 {}}} SUCCS {{259 0 0-9018 {}}} CYCLES {}}
+set a(0-9018) {NAME ACC1:slc#136 TYPE READSLICE PAR 0-7009 XREFS 48727 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-9017 {}}} SUCCS {{259 0 0-9019 {}}} CYCLES {}}
+set a(0-9019) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#545 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48728 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-9006 {}} {259 0 0-9018 {}}} SUCCS {{259 0 0-9020 {}}} CYCLES {}}
+set a(0-9020) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#588 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48729 LOC {1 0.47879105 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-8993 {}} {259 0 0-9019 {}}} SUCCS {{259 0 0-9021 {}}} CYCLES {}}
+set a(0-9021) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#609 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-7009 XREFS 48730 LOC {1 0.532138125 1 0.620914525 1 0.620914525 1 0.679514234496936 1 0.815914059496936} PREDS {{258 0 0-8974 {}} {259 0 0-9020 {}}} SUCCS {{258 0 0-9111 {}}} CYCLES {}}
+set a(0-9022) {NAME ACC1-1:slc(acc#10.psp)#61 TYPE READSLICE PAR 0-7009 XREFS 48731 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9023 {}}} CYCLES {}}
+set a(0-9023) {NAME ACC1-1:exs#38 TYPE SIGNEXTEND PAR 0-7009 XREFS 48732 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9022 {}}} SUCCS {{259 0 0-9024 {}}} CYCLES {}}
+set a(0-9024) {NAME ACC1:conc#1392 TYPE CONCATENATE PAR 0-7009 XREFS 48733 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9023 {}}} SUCCS {{258 0 0-9033 {}}} CYCLES {}}
+set a(0-9025) {NAME ACC1-1:slc(acc#10.psp)#60 TYPE READSLICE PAR 0-7009 XREFS 48734 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9026 {}}} CYCLES {}}
+set a(0-9026) {NAME ACC1-1:exs#39 TYPE SIGNEXTEND PAR 0-7009 XREFS 48735 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9025 {}}} SUCCS {{258 0 0-9032 {}}} CYCLES {}}
+set a(0-9027) {NAME ACC1-1:slc(acc.idiv#5)#45 TYPE READSLICE PAR 0-7009 XREFS 48736 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6088549249999999} PREDS {{258 0 0-7252 {}}} SUCCS {{258 0 0-9031 {}}} CYCLES {}}
+set a(0-9028) {NAME ACC1-1:slc(acc.imod#23)#1 TYPE READSLICE PAR 0-7009 XREFS 48737 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-7319 {}}} SUCCS {{259 0 0-9029 {}}} CYCLES {}}
+set a(0-9029) {NAME ACC1-1:not#188 TYPE NOT PAR 0-7009 XREFS 48738 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9028 {}}} SUCCS {{258 0 0-9031 {}}} CYCLES {}}
+set a(0-9030) {NAME ACC1-1:slc(acc.imod#23)#2 TYPE READSLICE PAR 0-7009 XREFS 48739 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-7319 {}}} SUCCS {{259 0 0-9031 {}}} CYCLES {}}
+set a(0-9031) {NAME ACC1-1:and#11 TYPE AND PAR 0-7009 XREFS 48740 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9029 {}} {258 0 0-9027 {}} {259 0 0-9030 {}}} SUCCS {{259 0 0-9032 {}}} CYCLES {}}
+set a(0-9032) {NAME ACC1:conc#1393 TYPE CONCATENATE PAR 0-7009 XREFS 48741 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9026 {}} {259 0 0-9031 {}}} SUCCS {{259 0 0-9033 {}}} CYCLES {}}
+set a(0-9033) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#467 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48742 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-9024 {}} {259 0 0-9032 {}}} SUCCS {{259 0 0-9034 {}}} CYCLES {}}
+set a(0-9034) {NAME ACC1:slc#135 TYPE READSLICE PAR 0-7009 XREFS 48743 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-9033 {}}} SUCCS {{258 0 0-9047 {}}} CYCLES {}}
+set a(0-9035) {NAME ACC1-1:slc(acc#10.psp)#59 TYPE READSLICE PAR 0-7009 XREFS 48744 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9036 {}}} CYCLES {}}
+set a(0-9036) {NAME ACC1-1:exs#43 TYPE SIGNEXTEND PAR 0-7009 XREFS 48745 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9035 {}}} SUCCS {{259 0 0-9037 {}}} CYCLES {}}
+set a(0-9037) {NAME ACC1:conc#1390 TYPE CONCATENATE PAR 0-7009 XREFS 48746 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9036 {}}} SUCCS {{258 0 0-9045 {}}} CYCLES {}}
+set a(0-9038) {NAME ACC1-1:slc(acc#10.psp)#58 TYPE READSLICE PAR 0-7009 XREFS 48747 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9039 {}}} CYCLES {}}
+set a(0-9039) {NAME ACC1-1:exs#44 TYPE SIGNEXTEND PAR 0-7009 XREFS 48748 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9038 {}}} SUCCS {{258 0 0-9044 {}}} CYCLES {}}
+set a(0-9040) {NAME ACC1-1:slc(acc.imod#23) TYPE READSLICE PAR 0-7009 XREFS 48749 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-7319 {}}} SUCCS {{258 0 0-9043 {}}} CYCLES {}}
+set a(0-9041) {NAME ACC1-1:slc(acc.idiv#5)#44 TYPE READSLICE PAR 0-7009 XREFS 48750 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6088549249999999} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-9042 {}}} CYCLES {}}
+set a(0-9042) {NAME ACC1-1:not#187 TYPE NOT PAR 0-7009 XREFS 48751 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9041 {}}} SUCCS {{259 0 0-9043 {}}} CYCLES {}}
+set a(0-9043) {NAME ACC1-1:nand#5 TYPE NAND PAR 0-7009 XREFS 48752 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9040 {}} {259 0 0-9042 {}}} SUCCS {{259 0 0-9044 {}}} CYCLES {}}
+set a(0-9044) {NAME ACC1:conc#1391 TYPE CONCATENATE PAR 0-7009 XREFS 48753 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9039 {}} {259 0 0-9043 {}}} SUCCS {{259 0 0-9045 {}}} CYCLES {}}
+set a(0-9045) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#466 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48754 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-9037 {}} {259 0 0-9044 {}}} SUCCS {{259 0 0-9046 {}}} CYCLES {}}
+set a(0-9046) {NAME ACC1:slc#134 TYPE READSLICE PAR 0-7009 XREFS 48755 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-9045 {}}} SUCCS {{259 0 0-9047 {}}} CYCLES {}}
+set a(0-9047) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#544 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48756 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-9034 {}} {259 0 0-9046 {}}} SUCCS {{258 0 0-9067 {}}} CYCLES {}}
+set a(0-9048) {NAME ACC1-1:slc(acc#10.psp)#57 TYPE READSLICE PAR 0-7009 XREFS 48757 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9049 {}}} CYCLES {}}
+set a(0-9049) {NAME ACC1-1:exs#42 TYPE SIGNEXTEND PAR 0-7009 XREFS 48758 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9048 {}}} SUCCS {{259 0 0-9050 {}}} CYCLES {}}
+set a(0-9050) {NAME ACC1:conc#1388 TYPE CONCATENATE PAR 0-7009 XREFS 48759 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9049 {}}} SUCCS {{258 0 0-9055 {}}} CYCLES {}}
+set a(0-9051) {NAME ACC1-1:slc(acc#10.psp)#56 TYPE READSLICE PAR 0-7009 XREFS 48760 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9052 {}}} CYCLES {}}
+set a(0-9052) {NAME ACC1-1:exs#47 TYPE SIGNEXTEND PAR 0-7009 XREFS 48761 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9051 {}}} SUCCS {{258 0 0-9054 {}}} CYCLES {}}
+set a(0-9053) {NAME ACC1:slc(acc.imod#42) TYPE READSLICE PAR 0-7009 XREFS 48762 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.6088549249999999} PREDS {{258 0 0-7310 {}}} SUCCS {{259 0 0-9054 {}}} CYCLES {}}
+set a(0-9054) {NAME ACC1:conc#1389 TYPE CONCATENATE PAR 0-7009 XREFS 48763 LOC {1 0.356432775 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9052 {}} {259 0 0-9053 {}}} SUCCS {{259 0 0-9055 {}}} CYCLES {}}
+set a(0-9055) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#465 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48764 LOC {1 0.356432775 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-9050 {}} {259 0 0-9054 {}}} SUCCS {{259 0 0-9056 {}}} CYCLES {}}
+set a(0-9056) {NAME ACC1:slc#133 TYPE READSLICE PAR 0-7009 XREFS 48765 LOC {1 0.40398894999999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-9055 {}}} SUCCS {{258 0 0-9066 {}}} CYCLES {}}
+set a(0-9057) {NAME ACC1-1:slc(acc#10.psp)#55 TYPE READSLICE PAR 0-7009 XREFS 48766 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9058 {}}} CYCLES {}}
+set a(0-9058) {NAME ACC1-1:exs#45 TYPE SIGNEXTEND PAR 0-7009 XREFS 48767 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9057 {}}} SUCCS {{259 0 0-9059 {}}} CYCLES {}}
+set a(0-9059) {NAME ACC1:conc#1386 TYPE CONCATENATE PAR 0-7009 XREFS 48768 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9058 {}}} SUCCS {{258 0 0-9064 {}}} CYCLES {}}
+set a(0-9060) {NAME ACC1-1:slc(acc#10.psp)#54 TYPE READSLICE PAR 0-7009 XREFS 48769 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9061 {}}} CYCLES {}}
+set a(0-9061) {NAME ACC1-1:exs#46 TYPE SIGNEXTEND PAR 0-7009 XREFS 48770 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9060 {}}} SUCCS {{258 0 0-9063 {}}} CYCLES {}}
+set a(0-9062) {NAME ACC1:slc(ACC1-1:acc#208.psp)#5 TYPE READSLICE PAR 0-7009 XREFS 48771 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.6088549249999999} PREDS {{258 0 0-7292 {}}} SUCCS {{259 0 0-9063 {}}} CYCLES {}}
+set a(0-9063) {NAME ACC1:conc#1387 TYPE CONCATENATE PAR 0-7009 XREFS 48772 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9061 {}} {259 0 0-9062 {}}} SUCCS {{259 0 0-9064 {}}} CYCLES {}}
+set a(0-9064) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#464 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48773 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-9059 {}} {259 0 0-9063 {}}} SUCCS {{259 0 0-9065 {}}} CYCLES {}}
+set a(0-9065) {NAME ACC1:slc#132 TYPE READSLICE PAR 0-7009 XREFS 48774 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-9064 {}}} SUCCS {{259 0 0-9066 {}}} CYCLES {}}
+set a(0-9066) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#543 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48775 LOC {1 0.40398894999999996 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-9056 {}} {259 0 0-9065 {}}} SUCCS {{259 0 0-9067 {}}} CYCLES {}}
+set a(0-9067) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#587 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48776 LOC {1 0.47879105 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-9047 {}} {259 0 0-9066 {}}} SUCCS {{258 0 0-9110 {}}} CYCLES {}}
+set a(0-9068) {NAME ACC1-1:slc(acc#10.psp)#68 TYPE READSLICE PAR 0-7009 XREFS 48777 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9069 {}}} CYCLES {}}
+set a(0-9069) {NAME ACC1-1:exs#51 TYPE SIGNEXTEND PAR 0-7009 XREFS 48778 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9068 {}}} SUCCS {{259 0 0-9070 {}}} CYCLES {}}
+set a(0-9070) {NAME ACC1:conc#1384 TYPE CONCATENATE PAR 0-7009 XREFS 48779 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9069 {}}} SUCCS {{258 0 0-9075 {}}} CYCLES {}}
+set a(0-9071) {NAME ACC1-1:slc(acc#10.psp)#71 TYPE READSLICE PAR 0-7009 XREFS 48780 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9072 {}}} CYCLES {}}
+set a(0-9072) {NAME ACC1-1:exs#1034 TYPE SIGNEXTEND PAR 0-7009 XREFS 48781 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9071 {}}} SUCCS {{258 0 0-9074 {}}} CYCLES {}}
+set a(0-9073) {NAME ACC1:slc(ACC1-1:acc#208.psp)#4 TYPE READSLICE PAR 0-7009 XREFS 48782 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.6088549249999999} PREDS {{258 0 0-7292 {}}} SUCCS {{259 0 0-9074 {}}} CYCLES {}}
+set a(0-9074) {NAME ACC1:conc#1385 TYPE CONCATENATE PAR 0-7009 XREFS 48783 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9072 {}} {259 0 0-9073 {}}} SUCCS {{259 0 0-9075 {}}} CYCLES {}}
+set a(0-9075) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#463 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48784 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-9070 {}} {259 0 0-9074 {}}} SUCCS {{259 0 0-9076 {}}} CYCLES {}}
+set a(0-9076) {NAME ACC1:slc#131 TYPE READSLICE PAR 0-7009 XREFS 48785 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-9075 {}}} SUCCS {{258 0 0-9086 {}}} CYCLES {}}
+set a(0-9077) {NAME ACC1-1:slc(acc#10.psp)#70 TYPE READSLICE PAR 0-7009 XREFS 48786 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9078 {}}} CYCLES {}}
+set a(0-9078) {NAME ACC1-1:exs#49 TYPE SIGNEXTEND PAR 0-7009 XREFS 48787 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9077 {}}} SUCCS {{259 0 0-9079 {}}} CYCLES {}}
+set a(0-9079) {NAME ACC1:conc#1382 TYPE CONCATENATE PAR 0-7009 XREFS 48788 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9078 {}}} SUCCS {{258 0 0-9084 {}}} CYCLES {}}
+set a(0-9080) {NAME ACC1-1:slc(acc#10.psp)#69 TYPE READSLICE PAR 0-7009 XREFS 48789 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9081 {}}} CYCLES {}}
+set a(0-9081) {NAME ACC1-1:exs#50 TYPE SIGNEXTEND PAR 0-7009 XREFS 48790 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9080 {}}} SUCCS {{258 0 0-9083 {}}} CYCLES {}}
+set a(0-9082) {NAME ACC1:slc(ACC1-1:acc#208.psp) TYPE READSLICE PAR 0-7009 XREFS 48791 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.6088549249999999} PREDS {{258 0 0-7292 {}}} SUCCS {{259 0 0-9083 {}}} CYCLES {}}
+set a(0-9083) {NAME ACC1:conc#1383 TYPE CONCATENATE PAR 0-7009 XREFS 48792 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9081 {}} {259 0 0-9082 {}}} SUCCS {{259 0 0-9084 {}}} CYCLES {}}
+set a(0-9084) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#462 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48793 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-9079 {}} {259 0 0-9083 {}}} SUCCS {{259 0 0-9085 {}}} CYCLES {}}
+set a(0-9085) {NAME ACC1:slc#130 TYPE READSLICE PAR 0-7009 XREFS 48794 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-9084 {}}} SUCCS {{259 0 0-9086 {}}} CYCLES {}}
+set a(0-9086) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#542 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48795 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-9076 {}} {259 0 0-9085 {}}} SUCCS {{258 0 0-9109 {}}} CYCLES {}}
+set a(0-9087) {NAME ACC1-1:slc(acc.idiv#5)#9 TYPE READSLICE PAR 0-7009 XREFS 48796 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6088549249999999} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-9088 {}}} CYCLES {}}
+set a(0-9088) {NAME ACC1-1:exs#94 TYPE SIGNEXTEND PAR 0-7009 XREFS 48797 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9087 {}}} SUCCS {{259 0 0-9089 {}}} CYCLES {}}
+set a(0-9089) {NAME ACC1:conc#1378 TYPE CONCATENATE PAR 0-7009 XREFS 48798 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9088 {}}} SUCCS {{258 0 0-9097 {}}} CYCLES {}}
+set a(0-9090) {NAME ACC1-1:slc(acc.idiv#5)#11 TYPE READSLICE PAR 0-7009 XREFS 48799 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6088549249999999} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-9091 {}}} CYCLES {}}
+set a(0-9091) {NAME ACC1-1:exs#95 TYPE SIGNEXTEND PAR 0-7009 XREFS 48800 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9090 {}}} SUCCS {{258 0 0-9096 {}}} CYCLES {}}
+set a(0-9092) {NAME ACC1-1:slc(acc.imod#11) TYPE READSLICE PAR 0-7009 XREFS 48801 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-7171 {}}} SUCCS {{258 0 0-9095 {}}} CYCLES {}}
+set a(0-9093) {NAME ACC1-1:slc(acc#10.psp)#50 TYPE READSLICE PAR 0-7009 XREFS 48802 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9094 {}}} CYCLES {}}
+set a(0-9094) {NAME ACC1-1:not#91 TYPE NOT PAR 0-7009 XREFS 48803 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9093 {}}} SUCCS {{259 0 0-9095 {}}} CYCLES {}}
+set a(0-9095) {NAME ACC1-1:nand#2 TYPE NAND PAR 0-7009 XREFS 48804 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9092 {}} {259 0 0-9094 {}}} SUCCS {{259 0 0-9096 {}}} CYCLES {}}
+set a(0-9096) {NAME ACC1:conc#1379 TYPE CONCATENATE PAR 0-7009 XREFS 48805 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9091 {}} {259 0 0-9095 {}}} SUCCS {{259 0 0-9097 {}}} CYCLES {}}
+set a(0-9097) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#460 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48806 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-9089 {}} {259 0 0-9096 {}}} SUCCS {{259 0 0-9098 {}}} CYCLES {}}
+set a(0-9098) {NAME ACC1:slc#128 TYPE READSLICE PAR 0-7009 XREFS 48807 LOC {1 0.42196819999999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-9097 {}}} SUCCS {{258 0 0-9108 {}}} CYCLES {}}
+set a(0-9099) {NAME ACC1-1:slc(acc.idiv#5)#1 TYPE READSLICE PAR 0-7009 XREFS 48808 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6088549249999999} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-9100 {}}} CYCLES {}}
+set a(0-9100) {NAME ACC1-1:exs#90 TYPE SIGNEXTEND PAR 0-7009 XREFS 48809 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9099 {}}} SUCCS {{259 0 0-9101 {}}} CYCLES {}}
+set a(0-9101) {NAME ACC1:conc#1376 TYPE CONCATENATE PAR 0-7009 XREFS 48810 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9100 {}}} SUCCS {{258 0 0-9106 {}}} CYCLES {}}
+set a(0-9102) {NAME ACC1-1:slc(acc.idiv#5)#3 TYPE READSLICE PAR 0-7009 XREFS 48811 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6088549249999999} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-9103 {}}} CYCLES {}}
+set a(0-9103) {NAME ACC1-1:exs#91 TYPE SIGNEXTEND PAR 0-7009 XREFS 48812 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9102 {}}} SUCCS {{258 0 0-9105 {}}} CYCLES {}}
+set a(0-9104) {NAME ACC1:slc(acc.imod#34) TYPE READSLICE PAR 0-7009 XREFS 48813 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.6088549249999999} PREDS {{258 0 0-7162 {}}} SUCCS {{259 0 0-9105 {}}} CYCLES {}}
+set a(0-9105) {NAME ACC1:conc#1377 TYPE CONCATENATE PAR 0-7009 XREFS 48814 LOC {1 0.3471661 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9103 {}} {259 0 0-9104 {}}} SUCCS {{259 0 0-9106 {}}} CYCLES {}}
+set a(0-9106) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#459 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48815 LOC {1 0.3471661 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-9101 {}} {259 0 0-9105 {}}} SUCCS {{259 0 0-9107 {}}} CYCLES {}}
+set a(0-9107) {NAME ACC1:slc#127 TYPE READSLICE PAR 0-7009 XREFS 48816 LOC {1 0.39472227499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-9106 {}}} SUCCS {{259 0 0-9108 {}}} CYCLES {}}
+set a(0-9108) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#541 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48817 LOC {1 0.42196819999999996 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-9098 {}} {259 0 0-9107 {}}} SUCCS {{259 0 0-9109 {}}} CYCLES {}}
+set a(0-9109) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#586 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48818 LOC {1 0.469524375 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-9086 {}} {259 0 0-9108 {}}} SUCCS {{259 0 0-9110 {}}} CYCLES {}}
+set a(0-9110) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#608 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-7009 XREFS 48819 LOC {1 0.532138125 1 0.620914525 1 0.620914525 1 0.679514234496936 1 0.815914059496936} PREDS {{258 0 0-9067 {}} {259 0 0-9109 {}}} SUCCS {{259 0 0-9111 {}}} CYCLES {}}
+set a(0-9111) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#624 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-7009 XREFS 48820 LOC {1 0.590737875 1 0.679514275 1 0.679514275 1 0.7430262484103024 1 0.8794260734103024} PREDS {{258 0 0-9021 {}} {259 0 0-9110 {}}} SUCCS {{259 0 0-9112 {}}} CYCLES {}}
+set a(0-9112) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#637 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-7009 XREFS 48821 LOC {1 0.6542498999999999 1 0.7430262999999999 1 0.7430262999999999 1 0.8112156129329678 1 0.9476154379329679} PREDS {{258 0 0-8935 {}} {259 0 0-9111 {}}} SUCCS {{259 0 0-9113 {}}} CYCLES {}}
+set a(0-9113) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#645 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-7009 XREFS 48822 LOC {1 0.7224392749999999 1 0.8112156749999999 1 0.8112156749999999 1 0.8636001277684257 1 0.9999999527684257} PREDS {{258 0 0-8830 {}} {259 0 0-9112 {}}} SUCCS {{259 0 0-9114 {}}} CYCLES {}}
+set a(0-9114) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,12) AREA_SCORE 11.00 QUANTITY 4 NAME ACC1:acc#650 TYPE ACCU DELAY {0.98 ns} LIBRARY_DELAY {0.98 ns} PAR 0-7009 XREFS 48823 LOC {1 0.774823775 1 0.863600175 1 0.863600175 1 0.9246291533364113 2 0.06498865333641131} PREDS {{258 0 0-8732 {}} {259 0 0-9113 {}}} SUCCS {{258 0 0-9271 {}}} CYCLES {}}
+set a(0-9115) {NAME ACC1:slc(acc#20.psp#1)#39 TYPE READSLICE PAR 0-7009 XREFS 48824 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.8997363749999999} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-9120 {}}} CYCLES {}}
+set a(0-9116) {NAME ACC1:slc(ACC1:acc#227.psp)#65 TYPE READSLICE PAR 0-7009 XREFS 48825 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.8997363749999999} PREDS {{258 0 0-7554 {}}} SUCCS {{258 0 0-9120 {}}} CYCLES {}}
+set a(0-9117) {NAME ACC1:slc(ACC1:acc#224.psp)#56 TYPE READSLICE PAR 0-7009 XREFS 48826 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.8997363749999999} PREDS {{258 0 0-7629 {}}} SUCCS {{258 0 0-9120 {}}} CYCLES {}}
+set a(0-9118) {NAME ACC1-3:slc(acc#10.psp)#54 TYPE READSLICE PAR 0-7009 XREFS 48827 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.8997363749999999} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-9119 {}}} CYCLES {}}
+set a(0-9119) {NAME ACC1-3:exs#46 TYPE SIGNEXTEND PAR 0-7009 XREFS 48828 LOC {1 0.14655495 1 0.7676069999999999 1 0.7676069999999999 1 0.8997363749999999} PREDS {{259 0 0-9118 {}}} SUCCS {{259 0 0-9120 {}}} CYCLES {}}
+set a(0-9120) {NAME ACC1:conc#1126 TYPE CONCATENATE PAR 0-7009 XREFS 48829 LOC {1 0.14655495 1 0.7676069999999999 1 0.7676069999999999 1 0.8997363749999999} PREDS {{258 0 0-9117 {}} {258 0 0-9116 {}} {258 0 0-9115 {}} {259 0 0-9119 {}}} SUCCS {{258 0 0-9168 {}}} CYCLES {}}
+set a(0-9121) {NAME ACC1:slc(acc#5.psp#2)#37 TYPE READSLICE PAR 0-7009 XREFS 48830 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9122 {}}} CYCLES {}}
+set a(0-9122) {NAME ACC1-2:exs#20 TYPE SIGNEXTEND PAR 0-7009 XREFS 48831 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9121 {}}} SUCCS {{258 0 0-9125 {}}} CYCLES {}}
+set a(0-9123) {NAME ACC1:slc(acc#5.psp#2)#38 TYPE READSLICE PAR 0-7009 XREFS 48832 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9124 {}}} CYCLES {}}
+set a(0-9124) {NAME ACC1-2:exs#21 TYPE SIGNEXTEND PAR 0-7009 XREFS 48833 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9123 {}}} SUCCS {{259 0 0-9125 {}}} CYCLES {}}
+set a(0-9125) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#517 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48834 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-9122 {}} {259 0 0-9124 {}}} SUCCS {{258 0 0-9131 {}}} CYCLES {}}
+set a(0-9126) {NAME ACC1:slc(acc#5.psp#2)#39 TYPE READSLICE PAR 0-7009 XREFS 48835 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9127 {}}} CYCLES {}}
+set a(0-9127) {NAME ACC1-2:exs#25 TYPE SIGNEXTEND PAR 0-7009 XREFS 48836 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9126 {}}} SUCCS {{258 0 0-9130 {}}} CYCLES {}}
+set a(0-9128) {NAME ACC1:slc(acc#5.psp#2)#40 TYPE READSLICE PAR 0-7009 XREFS 48837 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9129 {}}} CYCLES {}}
+set a(0-9129) {NAME ACC1-2:exs#26 TYPE SIGNEXTEND PAR 0-7009 XREFS 48838 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9128 {}}} SUCCS {{259 0 0-9130 {}}} CYCLES {}}
+set a(0-9130) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#516 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48839 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-9127 {}} {259 0 0-9129 {}}} SUCCS {{259 0 0-9131 {}}} CYCLES {}}
+set a(0-9131) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#568 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48840 LOC {1 0.187338 1 0.608104 1 0.608104 1 0.6556601270708271 1 0.7877895020708271} PREDS {{258 0 0-9125 {}} {259 0 0-9130 {}}} SUCCS {{258 0 0-9143 {}}} CYCLES {}}
+set a(0-9132) {NAME ACC1:slc(acc#5.psp#2)#41 TYPE READSLICE PAR 0-7009 XREFS 48841 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9133 {}}} CYCLES {}}
+set a(0-9133) {NAME ACC1-2:exs#24 TYPE SIGNEXTEND PAR 0-7009 XREFS 48842 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9132 {}}} SUCCS {{258 0 0-9136 {}}} CYCLES {}}
+set a(0-9134) {NAME ACC1:slc(acc#5.psp#2)#42 TYPE READSLICE PAR 0-7009 XREFS 48843 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9135 {}}} CYCLES {}}
+set a(0-9135) {NAME ACC1-2:exs#29 TYPE SIGNEXTEND PAR 0-7009 XREFS 48844 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9134 {}}} SUCCS {{259 0 0-9136 {}}} CYCLES {}}
+set a(0-9136) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#515 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48845 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-9133 {}} {259 0 0-9135 {}}} SUCCS {{258 0 0-9142 {}}} CYCLES {}}
+set a(0-9137) {NAME ACC1:slc(acc#5.psp#2)#43 TYPE READSLICE PAR 0-7009 XREFS 48846 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9138 {}}} CYCLES {}}
+set a(0-9138) {NAME ACC1-2:exs#27 TYPE SIGNEXTEND PAR 0-7009 XREFS 48847 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9137 {}}} SUCCS {{258 0 0-9141 {}}} CYCLES {}}
+set a(0-9139) {NAME ACC1:slc(acc#5.psp#2)#44 TYPE READSLICE PAR 0-7009 XREFS 48848 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9140 {}}} CYCLES {}}
+set a(0-9140) {NAME ACC1-2:exs#28 TYPE SIGNEXTEND PAR 0-7009 XREFS 48849 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9139 {}}} SUCCS {{259 0 0-9141 {}}} CYCLES {}}
+set a(0-9141) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#514 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48850 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-9138 {}} {259 0 0-9140 {}}} SUCCS {{259 0 0-9142 {}}} CYCLES {}}
+set a(0-9142) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#567 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48851 LOC {1 0.187338 1 0.608104 1 0.608104 1 0.6556601270708271 1 0.7877895020708271} PREDS {{258 0 0-9136 {}} {259 0 0-9141 {}}} SUCCS {{259 0 0-9143 {}}} CYCLES {}}
+set a(0-9143) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#599 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48852 LOC {1 0.23489417499999998 1 0.655660175 1 0.655660175 1 0.7090071951789505 1 0.8411365701789504} PREDS {{258 0 0-9131 {}} {259 0 0-9142 {}}} SUCCS {{258 0 0-9167 {}}} CYCLES {}}
+set a(0-9144) {NAME ACC1:slc(acc#5.psp#2)#50 TYPE READSLICE PAR 0-7009 XREFS 48853 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9145 {}}} CYCLES {}}
+set a(0-9145) {NAME ACC1-2:exs#33 TYPE SIGNEXTEND PAR 0-7009 XREFS 48854 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9144 {}}} SUCCS {{258 0 0-9148 {}}} CYCLES {}}
+set a(0-9146) {NAME ACC1:slc(acc#5.psp#2)#54 TYPE READSLICE PAR 0-7009 XREFS 48855 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9147 {}}} CYCLES {}}
+set a(0-9147) {NAME ACC1-2:exs#1031 TYPE SIGNEXTEND PAR 0-7009 XREFS 48856 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9146 {}}} SUCCS {{259 0 0-9148 {}}} CYCLES {}}
+set a(0-9148) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#513 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48857 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-9145 {}} {259 0 0-9147 {}}} SUCCS {{258 0 0-9154 {}}} CYCLES {}}
+set a(0-9149) {NAME ACC1:slc(acc#5.psp#2)#59 TYPE READSLICE PAR 0-7009 XREFS 48858 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9150 {}}} CYCLES {}}
+set a(0-9150) {NAME ACC1-2:exs#31 TYPE SIGNEXTEND PAR 0-7009 XREFS 48859 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9149 {}}} SUCCS {{258 0 0-9153 {}}} CYCLES {}}
+set a(0-9151) {NAME ACC1:slc(acc#5.psp#2)#62 TYPE READSLICE PAR 0-7009 XREFS 48860 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9152 {}}} CYCLES {}}
+set a(0-9152) {NAME ACC1-2:exs#32 TYPE SIGNEXTEND PAR 0-7009 XREFS 48861 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9151 {}}} SUCCS {{259 0 0-9153 {}}} CYCLES {}}
+set a(0-9153) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#512 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48862 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-9150 {}} {259 0 0-9152 {}}} SUCCS {{259 0 0-9154 {}}} CYCLES {}}
+set a(0-9154) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#566 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48863 LOC {1 0.187338 1 0.608104 1 0.608104 1 0.6556601270708271 1 0.7877895020708271} PREDS {{258 0 0-9148 {}} {259 0 0-9153 {}}} SUCCS {{258 0 0-9166 {}}} CYCLES {}}
+set a(0-9155) {NAME ACC1-3:slc(acc.idiv#1)#27 TYPE READSLICE PAR 0-7009 XREFS 48864 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6994503249999999} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-9156 {}}} CYCLES {}}
+set a(0-9156) {NAME ACC1-3:exs#31 TYPE SIGNEXTEND PAR 0-7009 XREFS 48865 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9155 {}}} SUCCS {{258 0 0-9159 {}}} CYCLES {}}
+set a(0-9157) {NAME ACC1-3:slc(acc.idiv#1)#29 TYPE READSLICE PAR 0-7009 XREFS 48866 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6994503249999999} PREDS {{258 0 0-7554 {}}} SUCCS {{259 0 0-9158 {}}} CYCLES {}}
+set a(0-9158) {NAME ACC1-3:exs#32 TYPE SIGNEXTEND PAR 0-7009 XREFS 48867 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9157 {}}} SUCCS {{259 0 0-9159 {}}} CYCLES {}}
+set a(0-9159) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#511 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48868 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-9156 {}} {259 0 0-9158 {}}} SUCCS {{258 0 0-9165 {}}} CYCLES {}}
+set a(0-9160) {NAME ACC1-3:slc(acc.idiv)#33 TYPE READSLICE PAR 0-7009 XREFS 48869 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6994503249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-9161 {}}} CYCLES {}}
+set a(0-9161) {NAME ACC1-3:exs#16 TYPE SIGNEXTEND PAR 0-7009 XREFS 48870 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9160 {}}} SUCCS {{258 0 0-9164 {}}} CYCLES {}}
+set a(0-9162) {NAME ACC1-3:slc(acc.idiv)#35 TYPE READSLICE PAR 0-7009 XREFS 48871 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6994503249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-9163 {}}} CYCLES {}}
+set a(0-9163) {NAME ACC1-3:exs#17 TYPE SIGNEXTEND PAR 0-7009 XREFS 48872 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-9162 {}}} SUCCS {{259 0 0-9164 {}}} CYCLES {}}
+set a(0-9164) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#510 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-7009 XREFS 48873 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-9161 {}} {259 0 0-9163 {}}} SUCCS {{259 0 0-9165 {}}} CYCLES {}}
+set a(0-9165) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#565 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48874 LOC {1 0.187338 1 0.608104 1 0.608104 1 0.6556601270708271 1 0.7877895020708271} PREDS {{258 0 0-9159 {}} {259 0 0-9164 {}}} SUCCS {{259 0 0-9166 {}}} CYCLES {}}
+set a(0-9166) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#598 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48875 LOC {1 0.23489417499999998 1 0.655660175 1 0.655660175 1 0.7090071951789505 1 0.8411365701789504} PREDS {{258 0 0-9154 {}} {259 0 0-9165 {}}} SUCCS {{259 0 0-9167 {}}} CYCLES {}}
+set a(0-9167) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#614 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-7009 XREFS 48876 LOC {1 0.28824125 1 0.70900725 1 0.70900725 1 0.767606959496936 1 0.899736334496936} PREDS {{258 0 0-9143 {}} {259 0 0-9166 {}}} SUCCS {{259 0 0-9168 {}}} CYCLES {}}
+set a(0-9168) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 6 NAME ACC1:acc#627 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-7009 XREFS 48877 LOC {1 0.346841 1 0.7676069999999999 1 0.7676069999999999 1 0.8154860629329679 1 0.9476154379329679} PREDS {{258 0 0-9120 {}} {259 0 0-9167 {}}} SUCCS {{258 0 0-9246 {}}} CYCLES {}}
+set a(0-9169) {NAME ACC1:slc(ACC1:acc#214.psp#1)#12 TYPE READSLICE PAR 0-7009 XREFS 48878 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.744910725} PREDS {{258 0 0-7666 {}}} SUCCS {{259 0 0-9170 {}}} CYCLES {}}
+set a(0-9170) {NAME ACC1:not#368 TYPE NOT PAR 0-7009 XREFS 48879 LOC {1 0.258664325 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-9169 {}}} SUCCS {{258 0 0-9175 {}}} CYCLES {}}
+set a(0-9171) {NAME ACC1:slc(acc.imod#18)#17 TYPE READSLICE PAR 0-7009 XREFS 48880 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.744910725} PREDS {{258 0 0-7759 {}}} SUCCS {{259 0 0-9172 {}}} CYCLES {}}
+set a(0-9172) {NAME ACC1:not#369 TYPE NOT PAR 0-7009 XREFS 48881 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-9171 {}}} SUCCS {{258 0 0-9175 {}}} CYCLES {}}
+set a(0-9173) {NAME ACC1:slc(acc.imod#26)#1 TYPE READSLICE PAR 0-7009 XREFS 48882 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.744910725} PREDS {{258 0 0-7080 {}}} SUCCS {{259 0 0-9174 {}}} CYCLES {}}
+set a(0-9174) {NAME ACC1:not#370 TYPE NOT PAR 0-7009 XREFS 48883 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-9173 {}}} SUCCS {{259 0 0-9175 {}}} CYCLES {}}
+set a(0-9175) {NAME ACC1:conc#1098 TYPE CONCATENATE PAR 0-7009 XREFS 48884 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{258 0 0-9172 {}} {258 0 0-9170 {}} {259 0 0-9174 {}}} SUCCS {{258 0 0-9181 {}}} CYCLES {}}
+set a(0-9176) {NAME ACC1:slc(ACC1-2:acc#212.psp)#12 TYPE READSLICE PAR 0-7009 XREFS 48885 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.744910725} PREDS {{258 0 0-7368 {}}} SUCCS {{259 0 0-9177 {}}} CYCLES {}}
+set a(0-9177) {NAME ACC1:not#371 TYPE NOT PAR 0-7009 XREFS 48886 LOC {1 0.258664325 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-9176 {}}} SUCCS {{258 0 0-9180 {}}} CYCLES {}}
+set a(0-9178) {NAME ACC1:slc(acc.imod#2)#17 TYPE READSLICE PAR 0-7009 XREFS 48887 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.744910725} PREDS {{258 0 0-7533 {}}} SUCCS {{259 0 0-9179 {}}} CYCLES {}}
+set a(0-9179) {NAME ACC1:not#372 TYPE NOT PAR 0-7009 XREFS 48888 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-9178 {}}} SUCCS {{259 0 0-9180 {}}} CYCLES {}}
+set a(0-9180) {NAME ACC1:conc#1099 TYPE CONCATENATE PAR 0-7009 XREFS 48889 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{258 0 0-9177 {}} {259 0 0-9179 {}}} SUCCS {{259 0 0-9181 {}}} CYCLES {}}
+set a(0-9181) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#523 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48890 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.6603374770708271 1 0.7924668520708271} PREDS {{258 0 0-9175 {}} {259 0 0-9180 {}}} SUCCS {{258 0 0-9193 {}}} CYCLES {}}
+set a(0-9182) {NAME ACC1:slc(ACC1-2:acc#208.psp)#12 TYPE READSLICE PAR 0-7009 XREFS 48891 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.744910725} PREDS {{258 0 0-7440 {}}} SUCCS {{259 0 0-9183 {}}} CYCLES {}}
+set a(0-9183) {NAME ACC1:not#373 TYPE NOT PAR 0-7009 XREFS 48892 LOC {1 0.258664325 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-9182 {}}} SUCCS {{258 0 0-9186 {}}} CYCLES {}}
+set a(0-9184) {NAME ACC1:slc(acc.imod#10)#16 TYPE READSLICE PAR 0-7009 XREFS 48893 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.744910725} PREDS {{258 0 0-7684 {}}} SUCCS {{259 0 0-9185 {}}} CYCLES {}}
+set a(0-9185) {NAME ACC1:not#374 TYPE NOT PAR 0-7009 XREFS 48894 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-9184 {}}} SUCCS {{259 0 0-9186 {}}} CYCLES {}}
+set a(0-9186) {NAME ACC1:conc#1100 TYPE CONCATENATE PAR 0-7009 XREFS 48895 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{258 0 0-9183 {}} {259 0 0-9185 {}}} SUCCS {{258 0 0-9192 {}}} CYCLES {}}
+set a(0-9187) {NAME ACC1:slc(ACC1-3:acc#212.psp)#15 TYPE READSLICE PAR 0-7009 XREFS 48896 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.744910725} PREDS {{258 0 0-7594 {}}} SUCCS {{259 0 0-9188 {}}} CYCLES {}}
+set a(0-9188) {NAME ACC1:not#375 TYPE NOT PAR 0-7009 XREFS 48897 LOC {1 0.267931 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-9187 {}}} SUCCS {{258 0 0-9191 {}}} CYCLES {}}
+set a(0-9189) {NAME ACC1:slc(acc.imod#31)#4 TYPE READSLICE PAR 0-7009 XREFS 48898 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.744910725} PREDS {{258 0 0-7386 {}}} SUCCS {{259 0 0-9190 {}}} CYCLES {}}
+set a(0-9190) {NAME ACC1:not#376 TYPE NOT PAR 0-7009 XREFS 48899 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-9189 {}}} SUCCS {{259 0 0-9191 {}}} CYCLES {}}
+set a(0-9191) {NAME ACC1:conc#1101 TYPE CONCATENATE PAR 0-7009 XREFS 48900 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{258 0 0-9188 {}} {259 0 0-9190 {}}} SUCCS {{259 0 0-9192 {}}} CYCLES {}}
+set a(0-9192) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#522 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48901 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.6603374770708271 1 0.7924668520708271} PREDS {{258 0 0-9186 {}} {259 0 0-9191 {}}} SUCCS {{259 0 0-9193 {}}} CYCLES {}}
+set a(0-9193) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#577 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48902 LOC {1 0.40398894999999996 1 0.660337525 1 0.660337525 1 0.7136845451789504 1 0.8458139201789505} PREDS {{258 0 0-9181 {}} {259 0 0-9192 {}}} SUCCS {{258 0 0-9213 {}}} CYCLES {}}
+set a(0-9194) {NAME ACC1:slc(ACC1:acc#214.psp#2)#6 TYPE READSLICE PAR 0-7009 XREFS 48903 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.744910725} PREDS {{258 0 0-7144 {}}} SUCCS {{259 0 0-9195 {}}} CYCLES {}}
+set a(0-9195) {NAME ACC1:not#377 TYPE NOT PAR 0-7009 XREFS 48904 LOC {1 0.258664325 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-9194 {}}} SUCCS {{258 0 0-9198 {}}} CYCLES {}}
+set a(0-9196) {NAME ACC1:slc(acc.imod#43)#4 TYPE READSLICE PAR 0-7009 XREFS 48905 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.744910725} PREDS {{258 0 0-7458 {}}} SUCCS {{259 0 0-9197 {}}} CYCLES {}}
+set a(0-9197) {NAME ACC1:not#378 TYPE NOT PAR 0-7009 XREFS 48906 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-9196 {}}} SUCCS {{259 0 0-9198 {}}} CYCLES {}}
+set a(0-9198) {NAME ACC1:conc#1102 TYPE CONCATENATE PAR 0-7009 XREFS 48907 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{258 0 0-9195 {}} {259 0 0-9197 {}}} SUCCS {{258 0 0-9204 {}}} CYCLES {}}
+set a(0-9199) {NAME ACC1:slc(ACC1-1:acc#208.psp)#6 TYPE READSLICE PAR 0-7009 XREFS 48908 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.744910725} PREDS {{258 0 0-7292 {}}} SUCCS {{259 0 0-9200 {}}} CYCLES {}}
+set a(0-9200) {NAME ACC1:not#379 TYPE NOT PAR 0-7009 XREFS 48909 LOC {1 0.267931 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-9199 {}}} SUCCS {{258 0 0-9203 {}}} CYCLES {}}
+set a(0-9201) {NAME ACC1:slc(acc.imod#6)#17 TYPE READSLICE PAR 0-7009 XREFS 48910 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.744910725} PREDS {{258 0 0-7612 {}}} SUCCS {{259 0 0-9202 {}}} CYCLES {}}
+set a(0-9202) {NAME ACC1:not#380 TYPE NOT PAR 0-7009 XREFS 48911 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-9201 {}}} SUCCS {{259 0 0-9203 {}}} CYCLES {}}
+set a(0-9203) {NAME ACC1:conc#1103 TYPE CONCATENATE PAR 0-7009 XREFS 48912 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{258 0 0-9200 {}} {259 0 0-9202 {}}} SUCCS {{259 0 0-9204 {}}} CYCLES {}}
+set a(0-9204) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#521 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48913 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.6603374770708271 1 0.7924668520708271} PREDS {{258 0 0-9198 {}} {259 0 0-9203 {}}} SUCCS {{258 0 0-9212 {}}} CYCLES {}}
+set a(0-9205) {NAME ACC1:slc(ACC1:acc#210.psp#2)#3 TYPE READSLICE PAR 0-7009 XREFS 48914 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.765220975} PREDS {{258 0 0-7062 {}}} SUCCS {{259 0 0-9206 {}}} CYCLES {}}
+set a(0-9206) {NAME ACC1:not#381 TYPE NOT PAR 0-7009 XREFS 48915 LOC {1 0.267931 1 0.6330916 1 0.6330916 1 0.765220975} PREDS {{259 0 0-9205 {}}} SUCCS {{258 0 0-9209 {}}} CYCLES {}}
+set a(0-9207) {NAME ACC1:slc(acc.imod#34)#2 TYPE READSLICE PAR 0-7009 XREFS 48916 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.765220975} PREDS {{258 0 0-7162 {}}} SUCCS {{259 0 0-9208 {}}} CYCLES {}}
+set a(0-9208) {NAME ACC1:not#382 TYPE NOT PAR 0-7009 XREFS 48917 LOC {1 0.3471661 1 0.6330916 1 0.6330916 1 0.765220975} PREDS {{259 0 0-9207 {}}} SUCCS {{259 0 0-9209 {}}} CYCLES {}}
+set a(0-9209) {NAME ACC1:conc#1104 TYPE CONCATENATE PAR 0-7009 XREFS 48918 LOC {1 0.3471661 1 0.6330916 1 0.6330916 1 0.765220975} PREDS {{258 0 0-9206 {}} {259 0 0-9208 {}}} SUCCS {{258 0 0-9211 {}}} CYCLES {}}
+set a(0-9210) {NAME ACC1:slc(ACC1:acc#221.psp) TYPE READSLICE PAR 0-7009 XREFS 48919 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.765220975} PREDS {{258 0 0-7605 {}}} SUCCS {{259 0 0-9211 {}}} CYCLES {}}
+set a(0-9211) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#520 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 48920 LOC {1 0.3471661 1 0.6330916 1 0.6330916 1 0.6603374770708271 1 0.7924668520708271} PREDS {{258 0 0-9209 {}} {259 0 0-9210 {}}} SUCCS {{259 0 0-9212 {}}} CYCLES {}}
+set a(0-9212) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#576 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48921 LOC {1 0.40398894999999996 1 0.660337525 1 0.660337525 1 0.7136845451789504 1 0.8458139201789505} PREDS {{258 0 0-9204 {}} {259 0 0-9211 {}}} SUCCS {{259 0 0-9213 {}}} CYCLES {}}
+set a(0-9213) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#603 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-7009 XREFS 48922 LOC {1 0.457336025 1 0.7136846 1 0.7136846 1 0.772284309496936 1 0.904413684496936} PREDS {{258 0 0-9193 {}} {259 0 0-9212 {}}} SUCCS {{258 0 0-9245 {}}} CYCLES {}}
+set a(0-9214) {NAME ACC1:slc(ACC1:acc#221.psp#2) TYPE READSLICE PAR 0-7009 XREFS 48923 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.79230435} PREDS {{258 0 0-7379 {}}} SUCCS {{258 0 0-9217 {}}} CYCLES {}}
+set a(0-9215) {NAME ACC1:slc(acc#5.psp#2)#36 TYPE READSLICE PAR 0-7009 XREFS 48924 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.79230435} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9216 {}}} CYCLES {}}
+set a(0-9216) {NAME ACC1-2:exs#19 TYPE SIGNEXTEND PAR 0-7009 XREFS 48925 LOC {1 0.14655495 1 0.660174975 1 0.660174975 1 0.79230435} PREDS {{259 0 0-9215 {}}} SUCCS {{259 0 0-9217 {}}} CYCLES {}}
+set a(0-9217) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#518 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 48926 LOC {1 0.319920175 1 0.660174975 1 0.660174975 1 0.6806477350894753 1 0.8127771100894753} PREDS {{258 0 0-9214 {}} {259 0 0-9216 {}}} SUCCS {{258 0 0-9222 {}}} CYCLES {}}
+set a(0-9218) {NAME ACC1:slc(ACC1:acc#219.psp#2) TYPE READSLICE PAR 0-7009 XREFS 48927 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.79230435} PREDS {{258 0 0-7451 {}}} SUCCS {{258 0 0-9221 {}}} CYCLES {}}
+set a(0-9219) {NAME ACC1:slc(acc#25.psp#2)#27 TYPE READSLICE PAR 0-7009 XREFS 48928 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.79230435} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-9220 {}}} CYCLES {}}
+set a(0-9220) {NAME ACC1-2:exs#107 TYPE SIGNEXTEND PAR 0-7009 XREFS 48929 LOC {1 0.14655495 1 0.660174975 1 0.660174975 1 0.79230435} PREDS {{259 0 0-9219 {}}} SUCCS {{259 0 0-9221 {}}} CYCLES {}}
+set a(0-9221) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#490 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 48930 LOC {1 0.319920175 1 0.660174975 1 0.660174975 1 0.6806477350894753 1 0.8127771100894753} PREDS {{258 0 0-9218 {}} {259 0 0-9220 {}}} SUCCS {{259 0 0-9222 {}}} CYCLES {}}
+set a(0-9222) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#575 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 48931 LOC {1 0.340392975 1 0.680647775 1 0.680647775 1 0.7238396701789505 1 0.8559690451789504} PREDS {{258 0 0-9217 {}} {259 0 0-9221 {}}} SUCCS {{258 0 0-9244 {}}} CYCLES {}}
+set a(0-9223) {NAME ACC1-3:slc(acc.idiv)#15 TYPE READSLICE PAR 0-7009 XREFS 48932 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7855312249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-9224 {}}} CYCLES {}}
+set a(0-9224) {NAME ACC1-3:exs#7 TYPE SIGNEXTEND PAR 0-7009 XREFS 48933 LOC {1 0.14655495 1 0.65340185 1 0.65340185 1 0.7855312249999999} PREDS {{259 0 0-9223 {}}} SUCCS {{259 0 0-9225 {}}} CYCLES {}}
+set a(0-9225) {NAME ACC1:conc#1400 TYPE CONCATENATE PAR 0-7009 XREFS 48934 LOC {1 0.14655495 1 0.65340185 1 0.65340185 1 0.7855312249999999} PREDS {{259 0 0-9224 {}}} SUCCS {{258 0 0-9229 {}}} CYCLES {}}
+set a(0-9226) {NAME ACC1:slc(ACC1:acc#222.psp#1) TYPE READSLICE PAR 0-7009 XREFS 48935 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.7855312249999999} PREDS {{258 0 0-7155 {}}} SUCCS {{258 0 0-9228 {}}} CYCLES {}}
+set a(0-9227) {NAME ACC1:slc(acc.psp#2)#5 TYPE READSLICE PAR 0-7009 XREFS 48936 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7855312249999999} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-9228 {}}} CYCLES {}}
+set a(0-9228) {NAME ACC1:conc#1401 TYPE CONCATENATE PAR 0-7009 XREFS 48937 LOC {1 0.319920175 1 0.65340185 1 0.65340185 1 0.7855312249999999} PREDS {{258 0 0-9226 {}} {259 0 0-9227 {}}} SUCCS {{259 0 0-9229 {}}} CYCLES {}}
+set a(0-9229) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#471 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 48938 LOC {1 0.319920175 1 0.65340185 1 0.65340185 1 0.6806477270708271 1 0.8127771020708271} PREDS {{258 0 0-9225 {}} {259 0 0-9228 {}}} SUCCS {{259 0 0-9230 {}}} CYCLES {}}
+set a(0-9230) {NAME ACC1:slc#139 TYPE READSLICE PAR 0-7009 XREFS 48939 LOC {1 0.3471661 1 0.680647775 1 0.680647775 1 0.81277715} PREDS {{259 0 0-9229 {}}} SUCCS {{258 0 0-9243 {}}} CYCLES {}}
+set a(0-9231) {NAME ACC1:slc(ACC1:acc#219.psp#1) TYPE READSLICE PAR 0-7009 XREFS 48940 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.7855312249999999} PREDS {{258 0 0-7303 {}}} SUCCS {{259 0 0-9232 {}}} CYCLES {}}
+set a(0-9232) {NAME ACC1:conc#1380 TYPE CONCATENATE PAR 0-7009 XREFS 48941 LOC {1 0.32918685 1 0.65340185 1 0.65340185 1 0.7855312249999999} PREDS {{259 0 0-9231 {}}} SUCCS {{258 0 0-9241 {}}} CYCLES {}}
+set a(0-9233) {NAME ACC1-1:slc(acc.idiv#5)#35 TYPE READSLICE PAR 0-7009 XREFS 48942 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.7855312249999999} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-9234 {}}} CYCLES {}}
+set a(0-9234) {NAME ACC1-1:exs#107 TYPE SIGNEXTEND PAR 0-7009 XREFS 48943 LOC {1 0.14655495 1 0.65340185 1 0.65340185 1 0.7855312249999999} PREDS {{259 0 0-9233 {}}} SUCCS {{258 0 0-9240 {}}} CYCLES {}}
+set a(0-9235) {NAME ACC1-1:slc(acc#10.psp)#51 TYPE READSLICE PAR 0-7009 XREFS 48944 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.7855312249999999} PREDS {{258 0 0-7107 {}}} SUCCS {{258 0 0-9239 {}}} CYCLES {}}
+set a(0-9236) {NAME ACC1-1:slc(acc.imod#11)#1 TYPE READSLICE PAR 0-7009 XREFS 48945 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.7855312249999999} PREDS {{258 0 0-7171 {}}} SUCCS {{259 0 0-9237 {}}} CYCLES {}}
+set a(0-9237) {NAME ACC1-1:not#92 TYPE NOT PAR 0-7009 XREFS 48946 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.7855312249999999} PREDS {{259 0 0-9236 {}}} SUCCS {{258 0 0-9239 {}}} CYCLES {}}
+set a(0-9238) {NAME ACC1-1:slc(acc.imod#11)#2 TYPE READSLICE PAR 0-7009 XREFS 48947 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.7855312249999999} PREDS {{258 0 0-7171 {}}} SUCCS {{259 0 0-9239 {}}} CYCLES {}}
+set a(0-9239) {NAME ACC1-1:and#5 TYPE AND PAR 0-7009 XREFS 48948 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.7855312249999999} PREDS {{258 0 0-9237 {}} {258 0 0-9235 {}} {259 0 0-9238 {}}} SUCCS {{259 0 0-9240 {}}} CYCLES {}}
+set a(0-9240) {NAME ACC1:conc#1381 TYPE CONCATENATE PAR 0-7009 XREFS 48949 LOC {1 0.374412025 1 0.65340185 1 0.65340185 1 0.7855312249999999} PREDS {{258 0 0-9234 {}} {259 0 0-9239 {}}} SUCCS {{259 0 0-9241 {}}} CYCLES {}}
+set a(0-9241) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#461 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 48950 LOC {1 0.374412025 1 0.65340185 1 0.65340185 1 0.6806477270708271 1 0.8127771020708271} PREDS {{258 0 0-9232 {}} {259 0 0-9240 {}}} SUCCS {{259 0 0-9242 {}}} CYCLES {}}
+set a(0-9242) {NAME ACC1:slc#129 TYPE READSLICE PAR 0-7009 XREFS 48951 LOC {1 0.40165795 1 0.680647775 1 0.680647775 1 0.81277715} PREDS {{259 0 0-9241 {}}} SUCCS {{259 0 0-9243 {}}} CYCLES {}}
+set a(0-9243) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#574 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 48952 LOC {1 0.40165795 1 0.680647775 1 0.680647775 1 0.7238396701789505 1 0.8559690451789504} PREDS {{258 0 0-9230 {}} {259 0 0-9242 {}}} SUCCS {{259 0 0-9244 {}}} CYCLES {}}
+set a(0-9244) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,1,5,1,6) AREA_SCORE 6.00 QUANTITY 1 NAME ACC1:acc#602 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-7009 XREFS 48953 LOC {1 0.44484989999999996 1 0.7238397249999999 1 0.7238397249999999 1 0.772284309496936 1 0.9044136844969359} PREDS {{258 0 0-9222 {}} {259 0 0-9243 {}}} SUCCS {{259 0 0-9245 {}}} CYCLES {}}
+set a(0-9245) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 5 NAME ACC1:acc#621 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 48954 LOC {1 0.515935775 1 0.77228435 1 0.77228435 1 0.8154860734103023 1 0.9476154484103023} PREDS {{258 0 0-9213 {}} {259 0 0-9244 {}}} SUCCS {{259 0 0-9246 {}}} CYCLES {}}
+set a(0-9246) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#640 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-7009 XREFS 48955 LOC {1 0.55913755 1 0.815486125 1 0.815486125 1 0.8678705777684257 1 0.9999999527684257} PREDS {{258 0 0-9168 {}} {259 0 0-9245 {}}} SUCCS {{258 0 0-9270 {}}} CYCLES {}}
+set a(0-9247) {NAME ACC1:slc(ACC1:acc#227.psp) TYPE READSLICE PAR 0-7009 XREFS 48956 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.5760930249999999} PREDS {{258 0 0-7554 {}}} SUCCS {{258 0 0-9249 {}}} CYCLES {}}
+set a(0-9248) {NAME ACC1:slc(acc.psp#1) TYPE READSLICE PAR 0-7009 XREFS 48957 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.5760930249999999} PREDS {{258 0 0-7475 {}}} SUCCS {{259 0 0-9249 {}}} CYCLES {}}
+set a(0-9249) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#301 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-7009 XREFS 48958 LOC {1 0.14655495 1 0.44396365 1 0.44396365 1 0.47557448625 1 0.6077038612499999} PREDS {{258 0 0-9247 {}} {259 0 0-9248 {}}} SUCCS {{258 0 0-9251 {}}} CYCLES {}}
+set a(0-9250) {NAME ACC1:slc(ACC1:acc#224.psp) TYPE READSLICE PAR 0-7009 XREFS 48959 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6077039} PREDS {{258 0 0-7629 {}}} SUCCS {{259 0 0-9251 {}}} CYCLES {}}
+set a(0-9251) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#300 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 48960 LOC {1 0.178165825 1 0.47557452499999997 1 0.47557452499999997 1 0.4960472850894752 1 0.6281766600894753} PREDS {{258 0 0-9249 {}} {259 0 0-9250 {}}} SUCCS {{258 0 0-9253 {}}} CYCLES {}}
+set a(0-9252) {NAME ACC1:slc(ACC1:acc#228.psp) TYPE READSLICE PAR 0-7009 XREFS 48961 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6281766999999999} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9253 {}}} CYCLES {}}
+set a(0-9253) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#299 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-7009 XREFS 48962 LOC {1 0.19863862499999999 1 0.496047325 1 0.496047325 1 0.5165200850894752 1 0.6486494600894752} PREDS {{258 0 0-9251 {}} {259 0 0-9252 {}}} SUCCS {{258 0 0-9255 {}}} CYCLES {}}
+set a(0-9254) {NAME ACC1:slc(ACC1:acc#226.psp) TYPE READSLICE PAR 0-7009 XREFS 48963 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6486495} PREDS {{258 0 0-7403 {}}} SUCCS {{259 0 0-9255 {}}} CYCLES {}}
+set a(0-9255) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#298 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 48964 LOC {1 0.219111425 1 0.516520125 1 0.516520125 1 0.5437660020708271 1 0.6758953770708271} PREDS {{258 0 0-9253 {}} {259 0 0-9254 {}}} SUCCS {{258 0 0-9257 {}}} CYCLES {}}
+set a(0-9256) {NAME ACC1:slc(ACC1:acc#224.psp#1) TYPE READSLICE PAR 0-7009 XREFS 48965 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.675895425} PREDS {{258 0 0-7107 {}}} SUCCS {{259 0 0-9257 {}}} CYCLES {}}
+set a(0-9257) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#297 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 48966 LOC {1 0.24635735 1 0.54376605 1 0.54376605 1 0.5710119270708272 1 0.7031413020708271} PREDS {{258 0 0-9255 {}} {259 0 0-9256 {}}} SUCCS {{258 0 0-9259 {}}} CYCLES {}}
+set a(0-9258) {NAME ACC1:slc(ACC1-1:acc#25.psp) TYPE READSLICE PAR 0-7009 XREFS 48967 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.70314135} PREDS {{258 0 0-7252 {}}} SUCCS {{259 0 0-9259 {}}} CYCLES {}}
+set a(0-9259) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#296 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 48968 LOC {1 0.273603275 1 0.571011975 1 0.571011975 1 0.5982578520708272 1 0.7303872270708271} PREDS {{258 0 0-9257 {}} {259 0 0-9258 {}}} SUCCS {{258 0 0-9261 {}}} CYCLES {}}
+set a(0-9260) {NAME ACC1:slc(acc.psp#2) TYPE READSLICE PAR 0-7009 XREFS 48969 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.730387275} PREDS {{258 0 0-7022 {}}} SUCCS {{259 0 0-9261 {}}} CYCLES {}}
+set a(0-9261) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#295 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 48970 LOC {1 0.3008492 1 0.5982579 1 0.5982579 1 0.6255037770708272 1 0.7576331520708272} PREDS {{258 0 0-9259 {}} {259 0 0-9260 {}}} SUCCS {{259 0 0-9262 {}}} CYCLES {}}
+set a(0-9262) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(4,0,5,0,8) AREA_SCORE 330.25 QUANTITY 2 NAME ACC1:mul TYPE MUL DELAY {2.71 ns} LIBRARY_DELAY {2.71 ns} PAR 0-7009 XREFS 48971 LOC {1 0.328095125 1 0.625503825 1 0.625503825 1 0.7951758226245129 1 0.9273051976245129} PREDS {{259 0 0-9261 {}}} SUCCS {{258 0 0-9269 {}}} CYCLES {}}
+set a(0-9263) {NAME slc(acc#20.psp#1)#84 TYPE READSLICE PAR 0-7009 XREFS 48972 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.92730525} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-9268 {}}} CYCLES {}}
+set a(0-9264) {NAME slc(acc#20.psp#1)#85 TYPE READSLICE PAR 0-7009 XREFS 48973 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.92730525} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-9268 {}}} CYCLES {}}
+set a(0-9265) {NAME slc(acc#20.psp#1)#86 TYPE READSLICE PAR 0-7009 XREFS 48974 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.92730525} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-9268 {}}} CYCLES {}}
+set a(0-9266) {NAME slc(acc#20.psp#1)#78 TYPE READSLICE PAR 0-7009 XREFS 48975 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.92730525} PREDS {{258 0 0-7701 {}}} SUCCS {{258 0 0-9268 {}}} CYCLES {}}
+set a(0-9267) {NAME ACC1:slc(ACC1:acc#228.psp)#49 TYPE READSLICE PAR 0-7009 XREFS 48976 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.92730525} PREDS {{258 0 0-7331 {}}} SUCCS {{259 0 0-9268 {}}} CYCLES {}}
+set a(0-9268) {NAME ACC1:conc#1086 TYPE CONCATENATE PAR 0-7009 XREFS 48977 LOC {1 0.14655495 1 0.795175875 1 0.795175875 1 0.92730525} PREDS {{258 0 0-9266 {}} {258 0 0-9265 {}} {258 0 0-9264 {}} {258 0 0-9263 {}} {259 0 0-9267 {}}} SUCCS {{259 0 0-9269 {}}} CYCLES {}}
+set a(0-9269) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,9) AREA_SCORE 9.26 QUANTITY 5 NAME ACC1:acc#639 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-7009 XREFS 48978 LOC {1 0.49776717499999995 1 0.795175875 1 0.795175875 1 0.8678705777684257 1 0.9999999527684257} PREDS {{258 0 0-9262 {}} {259 0 0-9268 {}}} SUCCS {{259 0 0-9270 {}}} CYCLES {}}
+set a(0-9270) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,1,11) AREA_SCORE 10.00 QUANTITY 5 NAME ACC1:acc#647 TYPE ACCU DELAY {0.91 ns} LIBRARY_DELAY {0.91 ns} PAR 0-7009 XREFS 48979 LOC {1 0.6115220499999999 1 0.867870625 1 0.867870625 1 0.9246291378916544 2 0.06498863789165435} PREDS {{258 0 0-9246 {}} {259 0 0-9269 {}}} SUCCS {{259 0 0-9271 {}}} CYCLES {}}
+set a(0-9271) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1:acc#655 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 48980 LOC {1 0.8358528 1 0.9246291999999999 1 0.9246291999999999 1 0.9999999563734283 2 0.14035945637342837} PREDS {{258 0 0-9114 {}} {259 0 0-9270 {}}} SUCCS {{259 0 0-9272 {}}} CYCLES {}}
+set a(0-9272) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 4 NAME ACC1:acc#660 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-7009 XREFS 48981 LOC {2 0.07948825 2 0.1403595 2 0.1403595 2 0.21984770349977767 2 0.21984770349977767} PREDS {{258 0 0-8725 {}} {259 0 0-9271 {}}} SUCCS {{259 0 0-9273 {}}} CYCLES {}}
+set a(0-9273) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(14,1,14,1,15) AREA_SCORE 15.00 QUANTITY 2 NAME ACC1:acc#663 TYPE ACCU DELAY {1.40 ns} LIBRARY_DELAY {1.40 ns} PAR 0-7009 XREFS 48982 LOC {2 0.1589765 2 0.21984774999999998 2 0.21984774999999998 2 0.3074051292724431 2 0.3074051292724431} PREDS {{258 0 0-8240 {}} {259 0 0-9272 {}}} SUCCS {{259 0 0-9274 {}}} CYCLES {}}
+set a(0-9274) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(15,0,14,1,15) AREA_SCORE 16.00 QUANTITY 1 NAME ACC1:acc TYPE ACCU DELAY {1.63 ns} LIBRARY_DELAY {1.63 ns} PAR 0-7009 XREFS 48983 LOC {2 0.246533925 2 0.307405175 2 0.307405175 2 0.40918180097764767 2 0.40918180097764767} PREDS {{258 0 0-8234 {}} {259 0 0-9273 {}}} SUCCS {{259 0 0-9275 {}}} CYCLES {}}
+set a(0-9275) {NAME ACC1:slc TYPE READSLICE PAR 0-7009 XREFS 48984 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.40918184999999996} PREDS {{259 0 0-9274 {}}} SUCCS {{259 0 0-9276 {}} {258 0 0-9277 {}} {258 0 0-9280 {}} {258 0 0-9282 {}} {258 0 0-9285 {}} {258 0 0-9288 {}} {258 0 0-9289 {}} {258 0 0-9294 {}} {258 0 0-9296 {}} {258 0 0-9298 {}} {258 0 0-9317 {}} {258 0 0-9324 {}} {258 0 0-9325 {}} {258 0 0-9327 {}}} CYCLES {}}
+set a(0-9276) {NAME intensity:slc(intensity#2.sg1)#4 TYPE READSLICE PAR 0-7009 XREFS 48985 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.40918184999999996} PREDS {{259 0 0-9275 {}}} SUCCS {{258 0 0-9279 {}}} CYCLES {}}
+set a(0-9277) {NAME intensity:slc(intensity#2.sg1)#5 TYPE READSLICE PAR 0-7009 XREFS 48986 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.40918184999999996} PREDS {{258 0 0-9275 {}}} SUCCS {{259 0 0-9278 {}}} CYCLES {}}
+set a(0-9278) {NAME FRAME:not#2 TYPE NOT PAR 0-7009 XREFS 48987 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.40918184999999996} PREDS {{259 0 0-9277 {}}} SUCCS {{259 0 0-9279 {}}} CYCLES {}}
+set a(0-9279) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME FRAME:acc#6 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 48988 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.45673797707082714 2 0.45673797707082714} PREDS {{258 0 0-9276 {}} {259 0 0-9278 {}}} SUCCS {{258 0 0-9287 {}}} CYCLES {}}
+set a(0-9280) {NAME intensity:slc(intensity#2.sg1)#6 TYPE READSLICE PAR 0-7009 XREFS 48989 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.4294921} PREDS {{258 0 0-9275 {}}} SUCCS {{259 0 0-9281 {}}} CYCLES {}}
+set a(0-9281) {NAME FRAME:not#3 TYPE NOT PAR 0-7009 XREFS 48990 LOC {2 0.34831059999999997 2 0.4294921 2 0.4294921 2 0.4294921} PREDS {{259 0 0-9280 {}}} SUCCS {{258 0 0-9284 {}}} CYCLES {}}
+set a(0-9282) {NAME intensity:slc(intensity#2.sg1)#7 TYPE READSLICE PAR 0-7009 XREFS 48991 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.4294921} PREDS {{258 0 0-9275 {}}} SUCCS {{259 0 0-9283 {}}} CYCLES {}}
+set a(0-9283) {NAME FRAME:not#9 TYPE NOT PAR 0-7009 XREFS 48992 LOC {2 0.34831059999999997 2 0.4294921 2 0.4294921 2 0.4294921} PREDS {{259 0 0-9282 {}}} SUCCS {{259 0 0-9284 {}}} CYCLES {}}
+set a(0-9284) {NAME FRAME:conc TYPE CONCATENATE PAR 0-7009 XREFS 48993 LOC {2 0.34831059999999997 2 0.4294921 2 0.4294921 2 0.4294921} PREDS {{258 0 0-9281 {}} {259 0 0-9283 {}}} SUCCS {{258 0 0-9286 {}}} CYCLES {}}
+set a(0-9285) {NAME intensity:slc(intensity#2.sg1)#1 TYPE READSLICE PAR 0-7009 XREFS 48994 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.4294921} PREDS {{258 0 0-9275 {}}} SUCCS {{259 0 0-9286 {}}} CYCLES {}}
+set a(0-9286) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME FRAME:acc#5 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 48995 LOC {2 0.34831059999999997 2 0.4294921 2 0.4294921 2 0.4567379770708272 2 0.4567379770708272} PREDS {{258 0 0-9284 {}} {259 0 0-9285 {}}} SUCCS {{259 0 0-9287 {}}} CYCLES {}}
+set a(0-9287) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME FRAME:acc#8 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-7009 XREFS 48996 LOC {2 0.395866775 2 0.456738025 2 0.456738025 2 0.5100850451789505 2 0.5100850451789505} PREDS {{258 0 0-9279 {}} {259 0 0-9286 {}}} SUCCS {{258 0 0-9292 {}}} CYCLES {}}
+set a(0-9288) {NAME intensity:slc(intensity#2.sg1)#2 TYPE READSLICE PAR 0-7009 XREFS 48997 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.462528925} PREDS {{258 0 0-9275 {}}} SUCCS {{258 0 0-9291 {}}} CYCLES {}}
+set a(0-9289) {NAME intensity:slc(intensity#2.sg1)#3 TYPE READSLICE PAR 0-7009 XREFS 48998 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.462528925} PREDS {{258 0 0-9275 {}}} SUCCS {{259 0 0-9290 {}}} CYCLES {}}
+set a(0-9290) {NAME FRAME:not#1 TYPE NOT PAR 0-7009 XREFS 48999 LOC {2 0.34831059999999997 2 0.462528925 2 0.462528925 2 0.462528925} PREDS {{259 0 0-9289 {}}} SUCCS {{259 0 0-9291 {}}} CYCLES {}}
+set a(0-9291) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME FRAME:acc#7 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-7009 XREFS 49000 LOC {2 0.34831059999999997 2 0.462528925 2 0.462528925 2 0.5100850520708271 2 0.5100850520708271} PREDS {{258 0 0-9288 {}} {259 0 0-9290 {}}} SUCCS {{259 0 0-9292 {}}} CYCLES {}}
+set a(0-9292) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME FRAME:acc#9 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-7009 XREFS 49001 LOC {2 0.44921384999999997 2 0.5100851 2 0.5100851 2 0.548374559496936 2 0.548374559496936} PREDS {{258 0 0-9287 {}} {259 0 0-9291 {}}} SUCCS {{259 0 0-9293 {}}} CYCLES {}}
+set a(0-9293) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 5 NAME acc#30 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 49002 LOC {2 0.48750335 2 0.5483745999999999 2 0.5483745999999999 2 0.5915763234103023 2 0.5915763234103023} PREDS {{259 0 0-9292 {}}} SUCCS {{258 0 0-9299 {}} {258 0 0-9301 {}} {258 0 0-9303 {}} {258 0 0-9305 {}} {258 0 0-9307 {}} {258 0 0-9315 {}}} CYCLES {}}
+set a(0-9294) {NAME intensity:slc(intensity#2.sg1)#9 TYPE READSLICE PAR 0-7009 XREFS 49003 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.632810675} PREDS {{258 0 0-9275 {}}} SUCCS {{259 0 0-9295 {}}} CYCLES {}}
+set a(0-9295) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,11,1,13) AREA_SCORE 330.00 QUANTITY 2 NAME FRAME:mul TYPE MUL DELAY {3.13 ns} LIBRARY_DELAY {3.13 ns} PAR 0-7009 XREFS 49004 LOC {2 0.34831059999999997 2 0.632810675 2 0.632810675 2 0.82839841875 2 0.82839841875} PREDS {{259 0 0-9294 {}}} SUCCS {{258 0 0-9323 {}}} CYCLES {}}
+set a(0-9296) {NAME intensity:slc(intensity#2.sg1)#11 TYPE READSLICE PAR 0-7009 XREFS 49005 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.5937580499999999} PREDS {{258 0 0-9275 {}}} SUCCS {{259 0 0-9297 {}}} CYCLES {}}
+set a(0-9297) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 1 NAME FRAME:mul#1 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-7009 XREFS 49006 LOC {2 0.34831059999999997 2 0.5937580499999999 2 0.5937580499999999 2 0.7716398421744312 2 0.7716398421744312} PREDS {{259 0 0-9296 {}}} SUCCS {{258 0 0-9322 {}}} CYCLES {}}
+set a(0-9298) {NAME intensity:slc(intensity#2.sg1) TYPE READSLICE PAR 0-7009 XREFS 49007 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.7284381249999999} PREDS {{258 0 0-9275 {}}} SUCCS {{258 0 0-9321 {}}} CYCLES {}}
+set a(0-9299) {NAME FRAME:slc(acc.imod#24)#4 TYPE READSLICE PAR 0-7009 XREFS 49008 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.690148625} PREDS {{258 0 0-9293 {}}} SUCCS {{259 0 0-9300 {}}} CYCLES {}}
+set a(0-9300) {NAME FRAME:conc#12 TYPE CONCATENATE PAR 0-7009 XREFS 49009 LOC {2 0.530705125 2 0.690148625 2 0.690148625 2 0.690148625} PREDS {{259 0 0-9299 {}}} SUCCS {{258 0 0-9320 {}}} CYCLES {}}
+set a(0-9301) {NAME FRAME:slc(acc.imod#24)#6 TYPE READSLICE PAR 0-7009 XREFS 49010 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.629865875} PREDS {{258 0 0-9293 {}}} SUCCS {{259 0 0-9302 {}}} CYCLES {}}
+set a(0-9302) {NAME FRAME:not#7 TYPE NOT PAR 0-7009 XREFS 49011 LOC {2 0.530705125 2 0.629865875 2 0.629865875 2 0.629865875} PREDS {{259 0 0-9301 {}}} SUCCS {{258 0 0-9314 {}}} CYCLES {}}
+set a(0-9303) {NAME FRAME:slc(acc.imod#24)#1 TYPE READSLICE PAR 0-7009 XREFS 49012 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{258 0 0-9293 {}}} SUCCS {{259 0 0-9304 {}}} CYCLES {}}
+set a(0-9304) {NAME FRAME:conc#14 TYPE CONCATENATE PAR 0-7009 XREFS 49013 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{259 0 0-9303 {}}} SUCCS {{258 0 0-9310 {}}} CYCLES {}}
+set a(0-9305) {NAME FRAME:slc(acc.imod#24)#2 TYPE READSLICE PAR 0-7009 XREFS 49014 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{258 0 0-9293 {}}} SUCCS {{259 0 0-9306 {}}} CYCLES {}}
+set a(0-9306) {NAME FRAME:not#5 TYPE NOT PAR 0-7009 XREFS 49015 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{259 0 0-9305 {}}} SUCCS {{258 0 0-9309 {}}} CYCLES {}}
+set a(0-9307) {NAME FRAME:slc(acc.imod#24) TYPE READSLICE PAR 0-7009 XREFS 49016 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{258 0 0-9293 {}}} SUCCS {{259 0 0-9308 {}}} CYCLES {}}
+set a(0-9308) {NAME FRAME:not#4 TYPE NOT PAR 0-7009 XREFS 49017 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{259 0 0-9307 {}}} SUCCS {{259 0 0-9309 {}}} CYCLES {}}
+set a(0-9309) {NAME FRAME:conc#15 TYPE CONCATENATE PAR 0-7009 XREFS 49018 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{258 0 0-9306 {}} {259 0 0-9308 {}}} SUCCS {{259 0 0-9310 {}}} CYCLES {}}
+set a(0-9310) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME FRAME:acc#16 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-7009 XREFS 49019 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.629865834496936 2 0.629865834496936} PREDS {{258 0 0-9304 {}} {259 0 0-9309 {}}} SUCCS {{259 0 0-9311 {}}} CYCLES {}}
+set a(0-9311) {NAME FRAME:slc#3 TYPE READSLICE PAR 0-7009 XREFS 49020 LOC {2 0.568994625 2 0.629865875 2 0.629865875 2 0.629865875} PREDS {{259 0 0-9310 {}}} SUCCS {{259 0 0-9312 {}}} CYCLES {}}
+set a(0-9312) {NAME FRAME:slc#2 TYPE READSLICE PAR 0-7009 XREFS 49021 LOC {2 0.568994625 2 0.629865875 2 0.629865875 2 0.629865875} PREDS {{259 0 0-9311 {}}} SUCCS {{259 0 0-9313 {}}} CYCLES {}}
+set a(0-9313) {NAME FRAME:not#8 TYPE NOT PAR 0-7009 XREFS 49022 LOC {2 0.568994625 2 0.629865875 2 0.629865875 2 0.629865875} PREDS {{259 0 0-9312 {}}} SUCCS {{259 0 0-9314 {}}} CYCLES {}}
+set a(0-9314) {NAME FRAME:conc#3 TYPE CONCATENATE PAR 0-7009 XREFS 49023 LOC {2 0.568994625 2 0.629865875 2 0.629865875 2 0.629865875} PREDS {{258 0 0-9302 {}} {259 0 0-9313 {}}} SUCCS {{258 0 0-9316 {}}} CYCLES {}}
+set a(0-9315) {NAME FRAME:slc(acc.imod#24)#5 TYPE READSLICE PAR 0-7009 XREFS 49024 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.629865875} PREDS {{258 0 0-9293 {}}} SUCCS {{259 0 0-9316 {}}} CYCLES {}}
+set a(0-9316) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME FRAME:acc#10 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-7009 XREFS 49025 LOC {2 0.568994625 2 0.629865875 2 0.629865875 2 0.6571117520708272 2 0.6571117520708272} PREDS {{258 0 0-9314 {}} {259 0 0-9315 {}}} SUCCS {{258 0 0-9319 {}}} CYCLES {}}
+set a(0-9317) {NAME intensity:slc(intensity#2.sg1)#10 TYPE READSLICE PAR 0-7009 XREFS 49026 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.6571118} PREDS {{258 0 0-9275 {}}} SUCCS {{259 0 0-9318 {}}} CYCLES {}}
+set a(0-9318) {NAME FRAME:not#6 TYPE NOT PAR 0-7009 XREFS 49027 LOC {2 0.34831059999999997 2 0.6571118 2 0.6571118 2 0.6571118} PREDS {{259 0 0-9317 {}}} SUCCS {{259 0 0-9319 {}}} CYCLES {}}
+set a(0-9319) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME FRAME:acc#11 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-7009 XREFS 49028 LOC {2 0.59624055 2 0.6571118 2 0.6571118 2 0.6901485701789505 2 0.6901485701789505} PREDS {{258 0 0-9316 {}} {259 0 0-9318 {}}} SUCCS {{259 0 0-9320 {}}} CYCLES {}}
+set a(0-9320) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME FRAME:acc#12 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-7009 XREFS 49029 LOC {2 0.6292773749999999 2 0.690148625 2 0.690148625 2 0.728438084496936 2 0.728438084496936} PREDS {{258 0 0-9300 {}} {259 0 0-9319 {}}} SUCCS {{259 0 0-9321 {}}} CYCLES {}}
+set a(0-9321) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 5 NAME FRAME:acc#13 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-7009 XREFS 49030 LOC {2 0.667566875 2 0.7284381249999999 2 0.7284381249999999 2 0.7716398484103023 2 0.7716398484103023} PREDS {{258 0 0-9298 {}} {259 0 0-9320 {}}} SUCCS {{259 0 0-9322 {}}} CYCLES {}}
+set a(0-9322) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,1,11) AREA_SCORE 10.00 QUANTITY 5 NAME FRAME:acc#14 TYPE ACCU DELAY {0.91 ns} LIBRARY_DELAY {0.91 ns} PAR 0-7009 XREFS 49031 LOC {2 0.71076865 2 0.7716398999999999 2 0.7716398999999999 2 0.8283984128916543 2 0.8283984128916543} PREDS {{258 0 0-9297 {}} {259 0 0-9321 {}}} SUCCS {{259 0 0-9323 {}}} CYCLES {}}
+set a(0-9323) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME FRAME:acc#15 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-7009 XREFS 49032 LOC {2 0.7675272249999999 2 0.828398475 2 0.828398475 2 0.9037692313734284 2 0.9037692313734284} PREDS {{258 0 0-9295 {}} {259 0 0-9322 {}}} SUCCS {{258 0 0-9330 {}}} CYCLES {}}
+set a(0-9324) {NAME intensity:slc(intensity#2.sg1)#12 TYPE READSLICE PAR 0-7009 XREFS 49033 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.9037692749999999} PREDS {{258 0 0-9275 {}}} SUCCS {{258 0 0-9328 {}}} CYCLES {}}
+set a(0-9325) {NAME intensity:slc(intensity#2.sg1)#13 TYPE READSLICE PAR 0-7009 XREFS 49034 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.9037692749999999} PREDS {{258 0 0-9275 {}}} SUCCS {{259 0 0-9326 {}}} CYCLES {}}
+set a(0-9326) {NAME FRAME:exs#1 TYPE SIGNEXTEND PAR 0-7009 XREFS 49035 LOC {2 0.34831059999999997 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{259 0 0-9325 {}}} SUCCS {{258 0 0-9328 {}}} CYCLES {}}
+set a(0-9327) {NAME intensity:slc(intensity#2.sg1)#8 TYPE READSLICE PAR 0-7009 XREFS 49036 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.9037692749999999} PREDS {{258 0 0-9275 {}}} SUCCS {{259 0 0-9328 {}}} CYCLES {}}
+set a(0-9328) {NAME FRAME:conc#2 TYPE CONCATENATE PAR 0-7009 XREFS 49037 LOC {2 0.34831059999999997 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{258 0 0-9326 {}} {258 0 0-9324 {}} {259 0 0-9327 {}}} SUCCS {{259 0 0-9329 {}}} CYCLES {}}
+set a(0-9329) {NAME FRAME:exs TYPE SIGNEXTEND PAR 0-7009 XREFS 49038 LOC {2 0.34831059999999997 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{259 0 0-9328 {}}} SUCCS {{259 0 0-9330 {}}} CYCLES {}}
+set a(0-9330) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 4 NAME FRAME:acc#2 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-7009 XREFS 49039 LOC {2 0.842898025 2 0.9037692749999999 2 0.9037692749999999 2 0.9832574784997776 2 0.9832574784997776} PREDS {{258 0 0-9323 {}} {259 0 0-9329 {}}} SUCCS {{259 0 0-9331 {}} {258 0 0-9332 {}} {258 0 0-9335 {}} {258 0 0-9336 {}} {258 0 0-9337 {}} {258 0 0-9340 {}}} CYCLES {}}
+set a(0-9331) {NAME intensity:slc(intensity) TYPE READSLICE PAR 0-7009 XREFS 49040 LOC {2 0.9223862749999999 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{259 0 0-9330 {}}} SUCCS {{258 0 0-9334 {}}} CYCLES {}}
+set a(0-9332) {NAME intensity:slc(intensity)#1 TYPE READSLICE PAR 0-7009 XREFS 49041 LOC {2 0.9223862749999999 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{258 0 0-9330 {}}} SUCCS {{259 0 0-9333 {}}} CYCLES {}}
+set a(0-9333) {NAME FRAME:exu TYPE PADZEROES PAR 0-7009 XREFS 49042 LOC {2 0.9223862749999999 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{259 0 0-9332 {}}} SUCCS {{259 0 0-9334 {}}} CYCLES {}}
+set a(0-9334) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(10,2) AREA_SCORE 7.30 QUANTITY 1 NAME FRAME:or TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-7009 XREFS 49043 LOC {2 0.9223862749999999 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{258 0 0-9331 {}} {259 0 0-9333 {}}} SUCCS {{258 0 0-9341 {}}} CYCLES {}}
+set a(0-9335) {NAME intensity:slc(intensity)#2 TYPE READSLICE PAR 0-7009 XREFS 49044 LOC {2 0.9223862749999999 2 0.983257525 2 0.983257525 2 1.0} PREDS {{258 0 0-9330 {}}} SUCCS {{258 0 0-9341 {}}} CYCLES {}}
+set a(0-9336) {NAME intensity:slc(intensity)#3 TYPE READSLICE PAR 0-7009 XREFS 49045 LOC {2 0.9223862749999999 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{258 0 0-9330 {}}} SUCCS {{258 0 0-9339 {}}} CYCLES {}}
+set a(0-9337) {NAME intensity:slc(intensity)#4 TYPE READSLICE PAR 0-7009 XREFS 49046 LOC {2 0.9223862749999999 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{258 0 0-9330 {}}} SUCCS {{259 0 0-9338 {}}} CYCLES {}}
+set a(0-9338) {NAME FRAME:exu#6 TYPE PADZEROES PAR 0-7009 XREFS 49047 LOC {2 0.9223862749999999 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{259 0 0-9337 {}}} SUCCS {{259 0 0-9339 {}}} CYCLES {}}
+set a(0-9339) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(6,2) AREA_SCORE 4.38 QUANTITY 1 NAME FRAME:or#3 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-7009 XREFS 49048 LOC {2 0.9223862749999999 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{258 0 0-9336 {}} {259 0 0-9338 {}}} SUCCS {{258 0 0-9341 {}}} CYCLES {}}
+set a(0-9340) {NAME intensity:slc(intensity)#5 TYPE READSLICE PAR 0-7009 XREFS 49049 LOC {2 0.9223862749999999 2 0.983257525 2 0.983257525 2 1.0} PREDS {{258 0 0-9330 {}}} SUCCS {{259 0 0-9341 {}}} CYCLES {}}
+set a(0-9341) {NAME FRAME:conc#11 TYPE CONCATENATE PAR 0-7009 XREFS 49050 LOC {2 0.93912875 2 1.0 2 1.0 2 1.0} PREDS {{258 0 0-9339 {}} {258 0 0-9335 {}} {258 0 0-9334 {}} {259 0 0-9340 {}}} SUCCS {{259 0 0-9342 {}}} CYCLES {}}
+set a(0-9342) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(2,30) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_write(vout:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-7009 XREFS 49051 LOC {2 1.0 2 1.0 2 1.0 3 0.0 2 0.9999} PREDS {{260 0 0-9342 {}} {259 0 0-9341 {}}} SUCCS {{260 0 0-9342 {}}} CYCLES {}}
+set a(0-9343) {NAME FRAME:asn#3 TYPE ASSIGN PAR 0-7009 XREFS 49052 LOC {0 1.0 1 0.81194935 1 0.81194935 3 0.81194935} PREDS {{262 0 0-9355 {}}} SUCCS {{259 0 0-9344 {}} {256 0 0-9355 {}}} CYCLES {}}
+set a(0-9344) {NAME FRAME:not#10 TYPE NOT PAR 0-7009 XREFS 49053 LOC {1 0.0 1 0.81194935 1 0.81194935 3 0.81194935} PREDS {{259 0 0-9343 {}}} SUCCS {{259 0 0-9345 {}}} CYCLES {}}
+set a(0-9345) {NAME FRAME:exs#3 TYPE SIGNEXTEND PAR 0-7009 XREFS 49054 LOC {1 0.0 1 0.81194935 1 0.81194935 3 0.81194935} PREDS {{259 0 0-9344 {}}} SUCCS {{259 0 0-9346 {}}} CYCLES {}}
+set a(0-9346) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(19,2) AREA_SCORE 13.87 QUANTITY 1 NAME FRAME:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-7009 XREFS 49055 LOC {1 0.0 1 0.81194935 1 0.81194935 1 0.828356081263854 3 0.828356081263854} PREDS {{262 0 0-9350 {}} {259 0 0-9345 {}}} SUCCS {{259 0 0-9347 {}} {256 0 0-9350 {}}} CYCLES {}}
+set a(0-9347) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(19,0,2,1,19) AREA_SCORE 20.00 QUANTITY 1 NAME FRAME:acc#4 TYPE ACCU DELAY {1.91 ns} LIBRARY_DELAY {1.91 ns} PAR 0-7009 XREFS 49056 LOC {1 0.016406775 1 0.828356125 1 0.828356125 1 0.9476154410815966 3 0.9476154410815966} PREDS {{259 0 0-9346 {}}} SUCCS {{258 0 0-9350 {}} {258 0 0-9351 {}}} CYCLES {}}
+set a(0-9348) {NAME FRAME:asn(regs.regs(0).sva) TYPE ASSIGN PAR 0-7009 XREFS 49057 LOC {1 0.0 1 0.02425815 1 0.02425815 2 0.05572455} PREDS {{260 0 0-9348 {}} {256 0 0-7012 {}} {256 0 0-7320 {}} {256 0 0-7323 {}} {256 0 0-7327 {}} {256 0 0-7396 {}} {256 0 0-7398 {}} {256 0 0-7401 {}} {258 0 0-7013 {}}} SUCCS {{262 0 0-7012 {}} {262 0 0-7320 {}} {262 0 0-7323 {}} {262 0 0-7327 {}} {262 0 0-7396 {}} {262 0 0-7398 {}} {262 0 0-7401 {}} {260 0 0-9348 {}}} CYCLES {}}
+set a(0-9349) {NAME FRAME:asn(regs.regs(1).sva) TYPE ASSIGN PAR 0-7009 XREFS 49058 LOC {0 1.0 0 1.0 0 1.0 2 0.046457874999999996} PREDS {{260 0 0-9349 {}} {256 0 0-7468 {}} {256 0 0-7470 {}} {256 0 0-7473 {}} {256 0 0-7543 {}} {256 0 0-7546 {}} {256 0 0-7550 {}} {256 0 0-7622 {}} {256 0 0-7624 {}} {256 0 0-7627 {}} {256 0 0-7694 {}} {256 0 0-7696 {}} {256 0 0-7699 {}} {258 0 0-7012 {}}} SUCCS {{262 0 0-7468 {}} {262 0 0-7470 {}} {262 0 0-7473 {}} {262 0 0-7543 {}} {262 0 0-7546 {}} {262 0 0-7550 {}} {262 0 0-7622 {}} {262 0 0-7624 {}} {262 0 0-7627 {}} {262 0 0-7694 {}} {262 0 0-7696 {}} {262 0 0-7699 {}} {260 0 0-9349 {}}} CYCLES {}}
+set a(0-9350) {NAME FRAME:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-7009 XREFS 49059 LOC {1 0.13566614999999999 1 0.9476154999999999 1 0.9476154999999999 3 1.0} PREDS {{260 0 0-9350 {}} {256 0 0-9346 {}} {258 0 0-9347 {}}} SUCCS {{262 0 0-9346 {}} {260 0 0-9350 {}}} CYCLES {}}
+set a(0-9351) {NAME FRAME:p:slc(FRAME:p)#1 TYPE READSLICE PAR 0-7009 XREFS 49060 LOC {1 0.13566614999999999 1 0.9476154999999999 1 0.9476154999999999 3 0.9476154999999999} PREDS {{258 0 0-9347 {}}} SUCCS {{259 0 0-9352 {}}} CYCLES {}}
+set a(0-9352) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME FRAME:acc TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-7009 XREFS 49061 LOC {1 0.13566614999999999 1 0.9476154999999999 1 0.9476154999999999 1 0.9999999527684257 3 0.9999999527684257} PREDS {{259 0 0-9351 {}}} SUCCS {{259 0 0-9353 {}}} CYCLES {}}
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0-8866 0-8867 0-8868 0-8869 0-8870 0-8871 0-8872 0-8873 0-8874 0-8875 0-8876 0-8877 0-8878 0-8879 0-8880 0-8881 0-8882 0-8883 0-8884 0-8885 0-8886 0-8887 0-8888 0-8889 0-8890 0-8891 0-8892 0-8893 0-8894 0-8895 0-8896 0-8897 0-8898 0-8899 0-8900 0-8901 0-8902 0-8903 0-8904 0-8905 0-8906 0-8907 0-8908 0-8909 0-8910 0-8911 0-8912 0-8913 0-8914 0-8915 0-8916 0-8917 0-8918 0-8919 0-8920 0-8921 0-8922 0-8923 0-8924 0-8925 0-8926 0-8927 0-8928 0-8929 0-8930 0-8931 0-8932 0-8933 0-8934 0-8935 0-8936 0-8937 0-8938 0-8939 0-8940 0-8941 0-8942 0-8943 0-8944 0-8945 0-8946 0-8947 0-8948 0-8949 0-8950 0-8951 0-8952 0-8953 0-8954 0-8955 0-8956 0-8957 0-8958 0-8959 0-8960 0-8961 0-8962 0-8963 0-8964 0-8965 0-8966 0-8967 0-8968 0-8969 0-8970 0-8971 0-8972 0-8973 0-8974 0-8975 0-8976 0-8977 0-8978 0-8979 0-8980 0-8981 0-8982 0-8983 0-8984 0-8985 0-8986 0-8987 0-8988 0-8989 0-8990 0-8991 0-8992 0-8993 0-8994 0-8995 0-8996 0-8997 0-8998 0-8999 0-9000 0-9001 0-9002 0-9003 0-9004 0-9005 0-9006 0-9007 0-9008 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0-9152 0-9153 0-9154 0-9155 0-9156 0-9157 0-9158 0-9159 0-9160 0-9161 0-9162 0-9163 0-9164 0-9165 0-9166 0-9167 0-9168 0-9169 0-9170 0-9171 0-9172 0-9173 0-9174 0-9175 0-9176 0-9177 0-9178 0-9179 0-9180 0-9181 0-9182 0-9183 0-9184 0-9185 0-9186 0-9187 0-9188 0-9189 0-9190 0-9191 0-9192 0-9193 0-9194 0-9195 0-9196 0-9197 0-9198 0-9199 0-9200 0-9201 0-9202 0-9203 0-9204 0-9205 0-9206 0-9207 0-9208 0-9209 0-9210 0-9211 0-9212 0-9213 0-9214 0-9215 0-9216 0-9217 0-9218 0-9219 0-9220 0-9221 0-9222 0-9223 0-9224 0-9225 0-9226 0-9227 0-9228 0-9229 0-9230 0-9231 0-9232 0-9233 0-9234 0-9235 0-9236 0-9237 0-9238 0-9239 0-9240 0-9241 0-9242 0-9243 0-9244 0-9245 0-9246 0-9247 0-9248 0-9249 0-9250 0-9251 0-9252 0-9253 0-9254 0-9255 0-9256 0-9257 0-9258 0-9259 0-9260 0-9261 0-9262 0-9263 0-9264 0-9265 0-9266 0-9267 0-9268 0-9269 0-9270 0-9271 0-9272 0-9273 0-9274 0-9275 0-9276 0-9277 0-9278 0-9279 0-9280 0-9281 0-9282 0-9283 0-9284 0-9285 0-9286 0-9287 0-9288 0-9289 0-9290 0-9291 0-9292 0-9293 0-9294 0-9295 0-9296 0-9297 0-9298 0-9299 0-9300 0-9301 0-9302 0-9303 0-9304 0-9305 0-9306 0-9307 0-9308 0-9309 0-9310 0-9311 0-9312 0-9313 0-9314 0-9315 0-9316 0-9317 0-9318 0-9319 0-9320 0-9321 0-9322 0-9323 0-9324 0-9325 0-9326 0-9327 0-9328 0-9329 0-9330 0-9331 0-9332 0-9333 0-9334 0-9335 0-9336 0-9337 0-9338 0-9339 0-9340 0-9341 0-9342 0-9343 0-9344 0-9345 0-9346 0-9347 0-9348 0-9349 0-9350 0-9351 0-9352 0-9353 0-9354 0-9355} ITERATIONS Infinite LATENCY 307201 RESET_LATENCY 0 CSTEPS 3 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 307200 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 3.0 CYCLES_IN 307202 TOTAL_CYCLES_IN 307202 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 307202 NAME main TYPE LOOP DELAY {6144060.00 ns} PAR 0-7004 XREFS 49065 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{258 0 0-7005 {}} {258 0 0-7006 {}} {258 0 0-7007 {}} {259 0 0-7008 {}}} SUCCS {{772 0 0-7005 {}} {772 0 0-7006 {}} {772 0 0-7007 {}} {772 0 0-7008 {}}} CYCLES {}}
+set a(0-7004) {CHI {0-7005 0-7006 0-7007 0-7008 0-7009} ITERATIONS Infinite LATENCY 307201 RESET_LATENCY 0 CSTEPS 0 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 307200 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 0 TOTAL_CYCLES_IN 0 TOTAL_CYCLES_UNDER 307202 TOTAL_CYCLES 307202 NAME core:rlp TYPE LOOP DELAY {6144060.00 ns} PAR {} XREFS 49066 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-7004-TOTALCYCLES) {307202}
+set a(0-7004-QMOD) {mgc_ioport.mgc_in_wire(1,90) 0-7013 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11) {0-7018 0-7021 0-7103 0-7106 0-7176 0-7179 0-7250 0-7326 0-7330 0-7400 0-7472 0-7549 0-7553 0-7626 0-7698} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12) {0-7022 0-7107 0-7180 0-7252 0-7331 0-7403 0-7475 0-7554 0-7629 0-7701 0-7934 0-8081 0-8082 0-9271} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4) {0-7030 0-7073 0-7155 0-7188 0-7231 0-7260 0-7303 0-7379 0-7451 0-7483 0-7526 0-7562 0-7605 0-7677 0-7709 0-7752 0-7780 0-7782 0-8178 0-8180 0-8195 0-8197 0-8218 0-8220 0-8231 0-8239 0-9217 0-9221 0-9251 0-9253} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5) {0-7037 0-7195 0-7267 0-7490 0-7569 0-7716 0-7877 0-8019 0-9222 0-9243} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3) {0-7046 0-7055 0-7069 0-7118 0-7132 0-7151 0-7204 0-7213 0-7227 0-7276 0-7285 0-7299 0-7342 0-7356 0-7375 0-7414 0-7428 0-7447 0-7499 0-7508 0-7522 0-7578 0-7587 0-7601 0-7640 0-7654 0-7673 0-7725 0-7734 0-7748 0-7887 0-7909 0-8029 0-8051 0-8739 0-8744 0-8750 0-8755 0-8762 0-8767 0-8773 0-8778 0-8786 0-8791 0-8797 0-8802 0-8809 0-8814 0-8820 0-8825 0-8835 0-8840 0-8846 0-8851 0-8858 0-8863 0-8869 0-8874 0-8882 0-8887 0-8893 0-8898 0-8905 0-9125 0-9130 0-9136 0-9141 0-9148 0-9153 0-9159 0-9164} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4) {0-7060 0-7218 0-7290 0-7513 0-7592 0-7739 0-7820 0-7830 0-7832 0-7840 0-7849 0-7851 0-7916 0-7918 0-7962 0-7972 0-7974 0-7982 0-7991 0-7993 0-8063 0-8065 0-8133 0-8256 0-8265 0-8267 0-8275 0-8284 0-8286 0-8295 0-8304 0-8306 0-8314 0-8327 0-8329 0-8342 0-8351 0-8353 0-8361 0-8370 0-8372 0-8381 0-8394 0-8396 0-8407 0-8416 0-8418 0-8429 0-8438 0-8440 0-8452 0-8464 0-8466 0-8475 0-8484 0-8486 0-8494 0-8503 0-8505 0-8521 0-8535 0-8537 0-8547 0-8558 0-8560 0-8571 0-8582 0-8584 0-8594 0-8608 0-8610 0-8745 0-8756 0-8768 0-8779 0-8792 0-8803 0-8815 0-8826 0-8841 0-8852 0-8864 0-8875 0-8888 0-8899 0-8912 0-8914 0-8921 0-8930 0-8932 0-8943 0-8952 0-8954 0-8962 0-8971 0-8973 0-8982 0-8991 0-8993 0-9005 0-9017 0-9019 0-9033 0-9045 0-9047 0-9055 0-9064 0-9066 0-9075 0-9084 0-9086 0-9097 0-9106 0-9108 0-9131 0-9142 0-9154 0-9165 0-9181 0-9192 0-9204 0-9279 0-9291} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6) {0-7062 0-7123 0-7220 0-7292 0-7347 0-7419 0-7515 0-7594 0-7645 0-7741 0-7888 0-8030 0-8154 0-8163 0-9319} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5) {0-7079 0-7088 0-7139 0-7161 0-7170 0-7237 0-7246 0-7309 0-7318 0-7363 0-7385 0-7394 0-7435 0-7457 0-7466 0-7532 0-7541 0-7611 0-7620 0-7661 0-7683 0-7692 0-7758 0-7767 0-7784 0-7786 0-7788 0-7790 0-7875 0-8017 0-8138 0-8147 0-8182 0-8184 0-8186 0-8188 0-8199 0-8201 0-8203 0-8205 0-9211 0-9229 0-9241 0-9255 0-9257 0-9259 0-9261 0-9286 0-9316} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7) {0-7143 0-7367 0-7439 0-7665 0-7889 0-7919 0-8031 0-8066 0-8139 0-9292 0-9310 0-9320} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2) {0-7778 0-8176 0-8193 0-8216 0-8229 0-8237 0-9249} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,5,0,8) {0-7791 0-9262} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,12) {0-7796 0-9323} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5) {0-7852 0-7994 0-8094 0-8105 0-8119 0-8287 0-8330 0-8373 0-8419 0-8467 0-8506 0-8561 0-8611 0-8757 0-8780 0-8804 0-8827 0-8853 0-8876 0-8900 0-8933 0-8974 0-9020 0-9067 0-9109 0-9143 0-9166 0-9193 0-9212 0-9287} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8) {0-7853 0-7995 0-9245 0-9293 0-9321} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10) {0-7854 0-7921 0-7996 0-8068 0-8830 0-9113 0-9246 0-9352} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,11) {0-7855 0-7997 0-8173 0-9270 0-9322} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4) {0-7862 0-7865 0-8004 0-8007} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9) {0-7895 0-7920 0-8037 0-8067 0-8165 0-9168} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,12) {0-7922 0-8069 0-8190 0-9114} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,11) {0-7933 0-8080 0-8724} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) {0-8083 0-8725 0-9272 0-9330} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6) {0-8106 0-8331 0-8420 0-8507 0-8612 0-8781 0-8828 0-8877 0-8934 0-9021 0-9110 0-9167 0-9213} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7) {0-8140 0-8421 0-8613 0-8626 0-8638 0-8651 0-8662 0-8829 0-8935 0-9111} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,1,2,1,3) 0-8162 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,1,6,1,7) 0-8164 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,7,0,10) {0-8189 0-8221} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,9,0,12) 0-8206 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,12,1,13) {0-8207 0-8226} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,1,13,1,14) {0-8208 0-8233} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,11,1,13) {0-8232 0-9295} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(14,1,14,1,15) {0-8234 0-9273} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,14) 0-8240 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8) {0-8614 0-8639 0-8663 0-8674 0-8687 0-8698 0-8710 0-8721 0-9112} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9) {0-8640 0-8675 0-8699 0-8722 0-9269} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,0,10) {0-8676 0-8723} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,1,5,1,6) 0-9244 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,14,1,15) 0-9274 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9) 0-9297 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2) 0-9334 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2) 0-9339 mgc_ioport.mgc_out_stdreg(2,30) 0-9342 mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2) 0-9346 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19) 0-9347}
+set a(0-7004-PROC_NAME) {core}
+set a(0-7004-HIER_NAME) {/sobel/core}
+set a(TOP) {0-7004}
+
diff --git a/Sobel/sobel.v11/schematic.nlv b/Sobel/sobel.v11/schematic.nlv
new file mode 100644
index 0000000..e5ec018
--- /dev/null
+++ b/Sobel/sobel.v11/schematic.nlv
@@ -0,0 +1,16656 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "sobel:core" "orig"
+load port {clk} input -attr xrf 51945 -attr oid 1 -attr vt d -attr @path {/sobel/sobel:core/clk}
+load port {en} input -attr xrf 51946 -attr oid 2 -attr vt d -attr @path {/sobel/sobel:core/en}
+load port {arst_n} input -attr xrf 51947 -attr oid 3 -attr vt d -attr @path {/sobel/sobel:core/arst_n}
+load portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} -attr xrf 51948 -attr oid 4 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} -attr xrf 51949 -attr oid 5 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load symbol "or(2,10)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,6)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(5:0)} input 6 {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(5:0)} input 6 {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,30)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(29:0)} input 30 {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(29:0)} input 30 {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(30,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(29:0)} input 30 {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(29:0)} input 30 {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(1,0,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,1,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,1,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,1,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(4,0,5,0,8)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,11,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(4,0,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,0,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,-1,7,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,2,1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,2,1,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,4,-1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,1,7,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,6,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,1,8,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,10,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(1,0,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,-1,11,-1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nand(2,1)" "INTERFACE" NAND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "and(3,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(11,1,11,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,1,12,1,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(13,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(12:0)} input 13 {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(12:0)} input 13 {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,5,1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,6,0,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,1,2,1,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,1,6,1,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,7,1,9)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,1,9,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(4,0,7,0,10)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,10,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(4,0,9,0,12)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,1,12,0,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,7,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,11,1,13)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(13,1,13,1,14)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(12:0)} input 13 {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(12:0)} input 13 {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(13:0)} output 14 {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(14,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(13:0)} input 14 {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(13:0)} input 14 {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(13:0)} output 14 {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(5,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(4:0)} input 5 {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(4:0)} input 5 {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(2,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(1:0)} input 2 {D(1)} {D(0)} \
+     portBus {DRa(1:0)} input 2 {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "reg(1,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(0:0)} input 1 {D(0)} \
+     portBus {DRa(0:0)} input 1 {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(7,0,7,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,0,8,0,9)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,9,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,10,0,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(11,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(10:0)} input 11 {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(10:0)} input 11 {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,1,8,0,9)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,9,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,2,-1,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,2,1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,1,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,4,1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,1,5,1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,6,1,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,0,9,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,10,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(12,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(11:0)} input 12 {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(11:0)} input 12 {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(10,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(9:0)} input 10 {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(9:0)} input 10 {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(90,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(89:0)} input 90 {D(89)} {D(88)} {D(87)} {D(86)} {D(85)} {D(84)} {D(83)} {D(82)} {D(81)} {D(80)} {D(79)} {D(78)} {D(77)} {D(76)} {D(75)} {D(74)} {D(73)} {D(72)} {D(71)} {D(70)} {D(69)} {D(68)} {D(67)} {D(66)} {D(65)} {D(64)} {D(63)} {D(62)} {D(61)} {D(60)} {D(59)} {D(58)} {D(57)} {D(56)} {D(55)} {D(54)} {D(53)} {D(52)} {D(51)} {D(50)} {D(49)} {D(48)} {D(47)} {D(46)} {D(45)} {D(44)} {D(43)} {D(42)} {D(41)} {D(40)} {D(39)} {D(38)} {D(37)} {D(36)} {D(35)} {D(34)} {D(33)} {D(32)} {D(31)} {D(30)} {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(89:0)} input 90 {DRa(89)} {DRa(88)} {DRa(87)} {DRa(86)} {DRa(85)} {DRa(84)} {DRa(83)} {DRa(82)} {DRa(81)} {DRa(80)} {DRa(79)} {DRa(78)} {DRa(77)} {DRa(76)} {DRa(75)} {DRa(74)} {DRa(73)} {DRa(72)} {DRa(71)} {DRa(70)} {DRa(69)} {DRa(68)} {DRa(67)} {DRa(66)} {DRa(65)} {DRa(64)} {DRa(63)} {DRa(62)} {DRa(61)} {DRa(60)} {DRa(59)} {DRa(58)} {DRa(57)} {DRa(56)} {DRa(55)} {DRa(54)} {DRa(53)} {DRa(52)} {DRa(51)} {DRa(50)} {DRa(49)} {DRa(48)} {DRa(47)} {DRa(46)} {DRa(45)} {DRa(44)} {DRa(43)} {DRa(42)} {DRa(41)} {DRa(40)} {DRa(39)} {DRa(38)} {DRa(37)} {DRa(36)} {DRa(35)} {DRa(34)} {DRa(33)} {DRa(32)} {DRa(31)} {DRa(30)} {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,6,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(3)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,-1,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,1,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,7,1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,0,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,-1,11,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(14,1,14,1,15)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(13:0)} input 14 {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(13:0)} input 14 {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(14,-1,13,1,14)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(13:0)} input 14 {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(12:0)} input 13 {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(13:0)} output 14 {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(15,-1,14,1,15)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(14:0)} input 15 {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(13:0)} input 14 {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,-1,6,-1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,10,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(10)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,2,0,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(2)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,1,1,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,12,1,14)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(13:0)} output 14 {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load net {regs.regs:slc(regs.regs(2)).itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2)).itm} 10 {regs.regs:slc(regs.regs(2)).itm(0)} {regs.regs:slc(regs.regs(2)).itm(1)} {regs.regs:slc(regs.regs(2)).itm(2)} {regs.regs:slc(regs.regs(2)).itm(3)} {regs.regs:slc(regs.regs(2)).itm(4)} {regs.regs:slc(regs.regs(2)).itm(5)} {regs.regs:slc(regs.regs(2)).itm(6)} {regs.regs:slc(regs.regs(2)).itm(7)} {regs.regs:slc(regs.regs(2)).itm(8)} {regs.regs:slc(regs.regs(2)).itm(9)} -attr xrf 51950 -attr oid 6 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#1.itm} 10 {regs.regs:slc(regs.regs(2))#1.itm(0)} {regs.regs:slc(regs.regs(2))#1.itm(1)} {regs.regs:slc(regs.regs(2))#1.itm(2)} {regs.regs:slc(regs.regs(2))#1.itm(3)} {regs.regs:slc(regs.regs(2))#1.itm(4)} {regs.regs:slc(regs.regs(2))#1.itm(5)} {regs.regs:slc(regs.regs(2))#1.itm(6)} {regs.regs:slc(regs.regs(2))#1.itm(7)} {regs.regs:slc(regs.regs(2))#1.itm(8)} {regs.regs:slc(regs.regs(2))#1.itm(9)} -attr xrf 51951 -attr oid 7 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#2.itm} 10 {regs.regs:slc(regs.regs(2))#2.itm(0)} {regs.regs:slc(regs.regs(2))#2.itm(1)} {regs.regs:slc(regs.regs(2))#2.itm(2)} {regs.regs:slc(regs.regs(2))#2.itm(3)} {regs.regs:slc(regs.regs(2))#2.itm(4)} {regs.regs:slc(regs.regs(2))#2.itm(5)} {regs.regs:slc(regs.regs(2))#2.itm(6)} {regs.regs:slc(regs.regs(2))#2.itm(7)} {regs.regs:slc(regs.regs(2))#2.itm(8)} {regs.regs:slc(regs.regs(2))#2.itm(9)} -attr xrf 51952 -attr oid 8 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#4.itm} 10 {regs.regs:slc(regs.regs(2))#4.itm(0)} {regs.regs:slc(regs.regs(2))#4.itm(1)} {regs.regs:slc(regs.regs(2))#4.itm(2)} {regs.regs:slc(regs.regs(2))#4.itm(3)} {regs.regs:slc(regs.regs(2))#4.itm(4)} {regs.regs:slc(regs.regs(2))#4.itm(5)} {regs.regs:slc(regs.regs(2))#4.itm(6)} {regs.regs:slc(regs.regs(2))#4.itm(7)} {regs.regs:slc(regs.regs(2))#4.itm(8)} {regs.regs:slc(regs.regs(2))#4.itm(9)} -attr xrf 51953 -attr oid 9 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#5.itm} 10 {regs.regs:slc(regs.regs(2))#5.itm(0)} {regs.regs:slc(regs.regs(2))#5.itm(1)} {regs.regs:slc(regs.regs(2))#5.itm(2)} {regs.regs:slc(regs.regs(2))#5.itm(3)} {regs.regs:slc(regs.regs(2))#5.itm(4)} {regs.regs:slc(regs.regs(2))#5.itm(5)} {regs.regs:slc(regs.regs(2))#5.itm(6)} {regs.regs:slc(regs.regs(2))#5.itm(7)} {regs.regs:slc(regs.regs(2))#5.itm(8)} {regs.regs:slc(regs.regs(2))#5.itm(9)} -attr xrf 51954 -attr oid 10 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#3.itm} 10 {regs.regs:slc(regs.regs(2))#3.itm(0)} {regs.regs:slc(regs.regs(2))#3.itm(1)} {regs.regs:slc(regs.regs(2))#3.itm(2)} {regs.regs:slc(regs.regs(2))#3.itm(3)} {regs.regs:slc(regs.regs(2))#3.itm(4)} {regs.regs:slc(regs.regs(2))#3.itm(5)} {regs.regs:slc(regs.regs(2))#3.itm(6)} {regs.regs:slc(regs.regs(2))#3.itm(7)} {regs.regs:slc(regs.regs(2))#3.itm(8)} {regs.regs:slc(regs.regs(2))#3.itm(9)} -attr xrf 51955 -attr oid 11 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#10.itm} 10 {regs.regs:slc(regs.regs(2))#10.itm(0)} {regs.regs:slc(regs.regs(2))#10.itm(1)} {regs.regs:slc(regs.regs(2))#10.itm(2)} {regs.regs:slc(regs.regs(2))#10.itm(3)} {regs.regs:slc(regs.regs(2))#10.itm(4)} {regs.regs:slc(regs.regs(2))#10.itm(5)} {regs.regs:slc(regs.regs(2))#10.itm(6)} {regs.regs:slc(regs.regs(2))#10.itm(7)} {regs.regs:slc(regs.regs(2))#10.itm(8)} {regs.regs:slc(regs.regs(2))#10.itm(9)} -attr xrf 51956 -attr oid 12 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#11.itm} 10 {regs.regs:slc(regs.regs(2))#11.itm(0)} {regs.regs:slc(regs.regs(2))#11.itm(1)} {regs.regs:slc(regs.regs(2))#11.itm(2)} {regs.regs:slc(regs.regs(2))#11.itm(3)} {regs.regs:slc(regs.regs(2))#11.itm(4)} {regs.regs:slc(regs.regs(2))#11.itm(5)} {regs.regs:slc(regs.regs(2))#11.itm(6)} {regs.regs:slc(regs.regs(2))#11.itm(7)} {regs.regs:slc(regs.regs(2))#11.itm(8)} {regs.regs:slc(regs.regs(2))#11.itm(9)} -attr xrf 51957 -attr oid 13 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#9.itm} 10 {regs.regs:slc(regs.regs(2))#9.itm(0)} {regs.regs:slc(regs.regs(2))#9.itm(1)} {regs.regs:slc(regs.regs(2))#9.itm(2)} {regs.regs:slc(regs.regs(2))#9.itm(3)} {regs.regs:slc(regs.regs(2))#9.itm(4)} {regs.regs:slc(regs.regs(2))#9.itm(5)} {regs.regs:slc(regs.regs(2))#9.itm(6)} {regs.regs:slc(regs.regs(2))#9.itm(7)} {regs.regs:slc(regs.regs(2))#9.itm(8)} {regs.regs:slc(regs.regs(2))#9.itm(9)} -attr xrf 51958 -attr oid 14 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {ACC1:acc#659.itm#1(0)} -attr vt d
+load net {ACC1:acc#659.itm#1(1)} -attr vt d
+load net {ACC1:acc#659.itm#1(2)} -attr vt d
+load net {ACC1:acc#659.itm#1(3)} -attr vt d
+load net {ACC1:acc#659.itm#1(4)} -attr vt d
+load net {ACC1:acc#659.itm#1(5)} -attr vt d
+load net {ACC1:acc#659.itm#1(6)} -attr vt d
+load net {ACC1:acc#659.itm#1(7)} -attr vt d
+load net {ACC1:acc#659.itm#1(8)} -attr vt d
+load net {ACC1:acc#659.itm#1(9)} -attr vt d
+load net {ACC1:acc#659.itm#1(10)} -attr vt d
+load net {ACC1:acc#659.itm#1(11)} -attr vt d
+load net {ACC1:acc#659.itm#1(12)} -attr vt d
+load netBundle {ACC1:acc#659.itm#1} 13 {ACC1:acc#659.itm#1(0)} {ACC1:acc#659.itm#1(1)} {ACC1:acc#659.itm#1(2)} {ACC1:acc#659.itm#1(3)} {ACC1:acc#659.itm#1(4)} {ACC1:acc#659.itm#1(5)} {ACC1:acc#659.itm#1(6)} {ACC1:acc#659.itm#1(7)} {ACC1:acc#659.itm#1(8)} {ACC1:acc#659.itm#1(9)} {ACC1:acc#659.itm#1(10)} {ACC1:acc#659.itm#1(11)} {ACC1:acc#659.itm#1(12)} -attr xrf 51959 -attr oid 15 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#658.itm#1(0)} -attr vt d
+load net {ACC1:acc#658.itm#1(1)} -attr vt d
+load net {ACC1:acc#658.itm#1(2)} -attr vt d
+load net {ACC1:acc#658.itm#1(3)} -attr vt d
+load net {ACC1:acc#658.itm#1(4)} -attr vt d
+load net {ACC1:acc#658.itm#1(5)} -attr vt d
+load net {ACC1:acc#658.itm#1(6)} -attr vt d
+load net {ACC1:acc#658.itm#1(7)} -attr vt d
+load net {ACC1:acc#658.itm#1(8)} -attr vt d
+load net {ACC1:acc#658.itm#1(9)} -attr vt d
+load net {ACC1:acc#658.itm#1(10)} -attr vt d
+load net {ACC1:acc#658.itm#1(11)} -attr vt d
+load net {ACC1:acc#658.itm#1(12)} -attr vt d
+load netBundle {ACC1:acc#658.itm#1} 13 {ACC1:acc#658.itm#1(0)} {ACC1:acc#658.itm#1(1)} {ACC1:acc#658.itm#1(2)} {ACC1:acc#658.itm#1(3)} {ACC1:acc#658.itm#1(4)} {ACC1:acc#658.itm#1(5)} {ACC1:acc#658.itm#1(6)} {ACC1:acc#658.itm#1(7)} {ACC1:acc#658.itm#1(8)} {ACC1:acc#658.itm#1(9)} {ACC1:acc#658.itm#1(10)} {ACC1:acc#658.itm#1(11)} {ACC1:acc#658.itm#1(12)} -attr xrf 51960 -attr oid 16 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#661.itm#1(0)} -attr vt d
+load net {ACC1:acc#661.itm#1(1)} -attr vt d
+load net {ACC1:acc#661.itm#1(2)} -attr vt d
+load net {ACC1:acc#661.itm#1(3)} -attr vt d
+load net {ACC1:acc#661.itm#1(4)} -attr vt d
+load net {ACC1:acc#661.itm#1(5)} -attr vt d
+load net {ACC1:acc#661.itm#1(6)} -attr vt d
+load net {ACC1:acc#661.itm#1(7)} -attr vt d
+load net {ACC1:acc#661.itm#1(8)} -attr vt d
+load net {ACC1:acc#661.itm#1(9)} -attr vt d
+load net {ACC1:acc#661.itm#1(10)} -attr vt d
+load net {ACC1:acc#661.itm#1(11)} -attr vt d
+load net {ACC1:acc#661.itm#1(12)} -attr vt d
+load net {ACC1:acc#661.itm#1(13)} -attr vt d
+load netBundle {ACC1:acc#661.itm#1} 14 {ACC1:acc#661.itm#1(0)} {ACC1:acc#661.itm#1(1)} {ACC1:acc#661.itm#1(2)} {ACC1:acc#661.itm#1(3)} {ACC1:acc#661.itm#1(4)} {ACC1:acc#661.itm#1(5)} {ACC1:acc#661.itm#1(6)} {ACC1:acc#661.itm#1(7)} {ACC1:acc#661.itm#1(8)} {ACC1:acc#661.itm#1(9)} {ACC1:acc#661.itm#1(10)} {ACC1:acc#661.itm#1(11)} {ACC1:acc#661.itm#1(12)} {ACC1:acc#661.itm#1(13)} -attr xrf 51961 -attr oid 17 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#652.itm#1(0)} -attr vt d
+load net {ACC1:acc#652.itm#1(1)} -attr vt d
+load net {ACC1:acc#652.itm#1(2)} -attr vt d
+load net {ACC1:acc#652.itm#1(3)} -attr vt d
+load net {ACC1:acc#652.itm#1(4)} -attr vt d
+load net {ACC1:acc#652.itm#1(5)} -attr vt d
+load net {ACC1:acc#652.itm#1(6)} -attr vt d
+load net {ACC1:acc#652.itm#1(7)} -attr vt d
+load net {ACC1:acc#652.itm#1(8)} -attr vt d
+load net {ACC1:acc#652.itm#1(9)} -attr vt d
+load net {ACC1:acc#652.itm#1(10)} -attr vt d
+load netBundle {ACC1:acc#652.itm#1} 11 {ACC1:acc#652.itm#1(0)} {ACC1:acc#652.itm#1(1)} {ACC1:acc#652.itm#1(2)} {ACC1:acc#652.itm#1(3)} {ACC1:acc#652.itm#1(4)} {ACC1:acc#652.itm#1(5)} {ACC1:acc#652.itm#1(6)} {ACC1:acc#652.itm#1(7)} {ACC1:acc#652.itm#1(8)} {ACC1:acc#652.itm#1(9)} {ACC1:acc#652.itm#1(10)} -attr xrf 51962 -attr oid 18 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#655.itm#1(0)} -attr vt d
+load net {ACC1:acc#655.itm#1(1)} -attr vt d
+load net {ACC1:acc#655.itm#1(2)} -attr vt d
+load net {ACC1:acc#655.itm#1(3)} -attr vt d
+load net {ACC1:acc#655.itm#1(4)} -attr vt d
+load net {ACC1:acc#655.itm#1(5)} -attr vt d
+load net {ACC1:acc#655.itm#1(6)} -attr vt d
+load net {ACC1:acc#655.itm#1(7)} -attr vt d
+load net {ACC1:acc#655.itm#1(8)} -attr vt d
+load net {ACC1:acc#655.itm#1(9)} -attr vt d
+load net {ACC1:acc#655.itm#1(10)} -attr vt d
+load net {ACC1:acc#655.itm#1(11)} -attr vt d
+load netBundle {ACC1:acc#655.itm#1} 12 {ACC1:acc#655.itm#1(0)} {ACC1:acc#655.itm#1(1)} {ACC1:acc#655.itm#1(2)} {ACC1:acc#655.itm#1(3)} {ACC1:acc#655.itm#1(4)} {ACC1:acc#655.itm#1(5)} {ACC1:acc#655.itm#1(6)} {ACC1:acc#655.itm#1(7)} {ACC1:acc#655.itm#1(8)} {ACC1:acc#655.itm#1(9)} {ACC1:acc#655.itm#1(10)} {ACC1:acc#655.itm#1(11)} -attr xrf 51963 -attr oid 19 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:mul#57.itm#1.sg2(0)} -attr vt d
+load net {ACC1:mul#57.itm#1.sg2(1)} -attr vt d
+load net {ACC1:mul#57.itm#1.sg2(2)} -attr vt d
+load net {ACC1:mul#57.itm#1.sg2(3)} -attr vt d
+load net {ACC1:mul#57.itm#1.sg2(4)} -attr vt d
+load netBundle {ACC1:mul#57.itm#1.sg2} 5 {ACC1:mul#57.itm#1.sg2(0)} {ACC1:mul#57.itm#1.sg2(1)} {ACC1:mul#57.itm#1.sg2(2)} {ACC1:mul#57.itm#1.sg2(3)} {ACC1:mul#57.itm#1.sg2(4)} -attr xrf 51964 -attr oid 20 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#1.sg2}
+load net {ACC1:mul#57.itm#2(0)} -attr vt d
+load net {ACC1:mul#57.itm#2(1)} -attr vt d
+load netBundle {ACC1:mul#57.itm#2} 2 {ACC1:mul#57.itm#2(0)} {ACC1:mul#57.itm#2(1)} -attr xrf 51965 -attr oid 21 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#2}
+load net {reg(regs.regs(0).sva).cse(0)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(1)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(2)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(3)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(4)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(5)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(6)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(7)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(8)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(9)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(10)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(11)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(12)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(13)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(14)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(15)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(16)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(17)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(18)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(19)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(20)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(21)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(22)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(23)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(24)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(25)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(26)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(27)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(28)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(29)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(30)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(31)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(32)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(33)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(34)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(35)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(36)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(37)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(38)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(39)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(40)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(41)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(42)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(43)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(44)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(45)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(46)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(47)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(48)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(49)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(50)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(51)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(52)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(53)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(54)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(55)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(56)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(57)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(58)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(59)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(60)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(61)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(62)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(63)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(64)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(65)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(66)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(67)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(68)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(69)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(70)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(71)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(72)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(73)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(74)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(75)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(76)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(77)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(78)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(79)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(80)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(81)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(82)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(83)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(84)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(85)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(86)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(87)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(88)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(89)} -attr vt d
+load netBundle {reg(regs.regs(0).sva).cse} 90 {reg(regs.regs(0).sva).cse(0)} {reg(regs.regs(0).sva).cse(1)} {reg(regs.regs(0).sva).cse(2)} {reg(regs.regs(0).sva).cse(3)} {reg(regs.regs(0).sva).cse(4)} {reg(regs.regs(0).sva).cse(5)} {reg(regs.regs(0).sva).cse(6)} {reg(regs.regs(0).sva).cse(7)} {reg(regs.regs(0).sva).cse(8)} {reg(regs.regs(0).sva).cse(9)} {reg(regs.regs(0).sva).cse(10)} {reg(regs.regs(0).sva).cse(11)} {reg(regs.regs(0).sva).cse(12)} {reg(regs.regs(0).sva).cse(13)} {reg(regs.regs(0).sva).cse(14)} {reg(regs.regs(0).sva).cse(15)} {reg(regs.regs(0).sva).cse(16)} {reg(regs.regs(0).sva).cse(17)} {reg(regs.regs(0).sva).cse(18)} {reg(regs.regs(0).sva).cse(19)} {reg(regs.regs(0).sva).cse(20)} {reg(regs.regs(0).sva).cse(21)} {reg(regs.regs(0).sva).cse(22)} {reg(regs.regs(0).sva).cse(23)} {reg(regs.regs(0).sva).cse(24)} {reg(regs.regs(0).sva).cse(25)} {reg(regs.regs(0).sva).cse(26)} {reg(regs.regs(0).sva).cse(27)} {reg(regs.regs(0).sva).cse(28)} {reg(regs.regs(0).sva).cse(29)} {reg(regs.regs(0).sva).cse(30)} {reg(regs.regs(0).sva).cse(31)} {reg(regs.regs(0).sva).cse(32)} {reg(regs.regs(0).sva).cse(33)} {reg(regs.regs(0).sva).cse(34)} {reg(regs.regs(0).sva).cse(35)} {reg(regs.regs(0).sva).cse(36)} {reg(regs.regs(0).sva).cse(37)} {reg(regs.regs(0).sva).cse(38)} {reg(regs.regs(0).sva).cse(39)} {reg(regs.regs(0).sva).cse(40)} {reg(regs.regs(0).sva).cse(41)} {reg(regs.regs(0).sva).cse(42)} {reg(regs.regs(0).sva).cse(43)} {reg(regs.regs(0).sva).cse(44)} {reg(regs.regs(0).sva).cse(45)} {reg(regs.regs(0).sva).cse(46)} {reg(regs.regs(0).sva).cse(47)} {reg(regs.regs(0).sva).cse(48)} {reg(regs.regs(0).sva).cse(49)} {reg(regs.regs(0).sva).cse(50)} {reg(regs.regs(0).sva).cse(51)} {reg(regs.regs(0).sva).cse(52)} {reg(regs.regs(0).sva).cse(53)} {reg(regs.regs(0).sva).cse(54)} {reg(regs.regs(0).sva).cse(55)} {reg(regs.regs(0).sva).cse(56)} {reg(regs.regs(0).sva).cse(57)} {reg(regs.regs(0).sva).cse(58)} {reg(regs.regs(0).sva).cse(59)} {reg(regs.regs(0).sva).cse(60)} {reg(regs.regs(0).sva).cse(61)} {reg(regs.regs(0).sva).cse(62)} {reg(regs.regs(0).sva).cse(63)} {reg(regs.regs(0).sva).cse(64)} {reg(regs.regs(0).sva).cse(65)} {reg(regs.regs(0).sva).cse(66)} {reg(regs.regs(0).sva).cse(67)} {reg(regs.regs(0).sva).cse(68)} {reg(regs.regs(0).sva).cse(69)} {reg(regs.regs(0).sva).cse(70)} {reg(regs.regs(0).sva).cse(71)} {reg(regs.regs(0).sva).cse(72)} {reg(regs.regs(0).sva).cse(73)} {reg(regs.regs(0).sva).cse(74)} {reg(regs.regs(0).sva).cse(75)} {reg(regs.regs(0).sva).cse(76)} {reg(regs.regs(0).sva).cse(77)} {reg(regs.regs(0).sva).cse(78)} {reg(regs.regs(0).sva).cse(79)} {reg(regs.regs(0).sva).cse(80)} {reg(regs.regs(0).sva).cse(81)} {reg(regs.regs(0).sva).cse(82)} {reg(regs.regs(0).sva).cse(83)} {reg(regs.regs(0).sva).cse(84)} {reg(regs.regs(0).sva).cse(85)} {reg(regs.regs(0).sva).cse(86)} {reg(regs.regs(0).sva).cse(87)} {reg(regs.regs(0).sva).cse(88)} {reg(regs.regs(0).sva).cse(89)} -attr xrf 51966 -attr oid 22 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {FRAME:acc#2.psp.sva(0)} -attr vt d
+load net {FRAME:acc#2.psp.sva(1)} -attr vt d
+load net {FRAME:acc#2.psp.sva(2)} -attr vt d
+load net {FRAME:acc#2.psp.sva(3)} -attr vt d
+load net {FRAME:acc#2.psp.sva(4)} -attr vt d
+load net {FRAME:acc#2.psp.sva(5)} -attr vt d
+load net {FRAME:acc#2.psp.sva(6)} -attr vt d
+load net {FRAME:acc#2.psp.sva(7)} -attr vt d
+load net {FRAME:acc#2.psp.sva(8)} -attr vt d
+load net {FRAME:acc#2.psp.sva(9)} -attr vt d
+load net {FRAME:acc#2.psp.sva(10)} -attr vt d
+load net {FRAME:acc#2.psp.sva(11)} -attr vt d
+load netBundle {FRAME:acc#2.psp.sva} 12 {FRAME:acc#2.psp.sva(0)} {FRAME:acc#2.psp.sva(1)} {FRAME:acc#2.psp.sva(2)} {FRAME:acc#2.psp.sva(3)} {FRAME:acc#2.psp.sva(4)} {FRAME:acc#2.psp.sva(5)} {FRAME:acc#2.psp.sva(6)} {FRAME:acc#2.psp.sva(7)} {FRAME:acc#2.psp.sva(8)} {FRAME:acc#2.psp.sva(9)} {FRAME:acc#2.psp.sva(10)} {FRAME:acc#2.psp.sva(11)} -attr xrf 51967 -attr oid 23 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {ACC1:slc.psp.sva(0)} -attr vt d
+load net {ACC1:slc.psp.sva(1)} -attr vt d
+load net {ACC1:slc.psp.sva(2)} -attr vt d
+load net {ACC1:slc.psp.sva(3)} -attr vt d
+load net {ACC1:slc.psp.sva(4)} -attr vt d
+load net {ACC1:slc.psp.sva(5)} -attr vt d
+load net {ACC1:slc.psp.sva(6)} -attr vt d
+load net {ACC1:slc.psp.sva(7)} -attr vt d
+load net {ACC1:slc.psp.sva(8)} -attr vt d
+load net {ACC1:slc.psp.sva(9)} -attr vt d
+load net {ACC1:slc.psp.sva(10)} -attr vt d
+load net {ACC1:slc.psp.sva(11)} -attr vt d
+load net {ACC1:slc.psp.sva(12)} -attr vt d
+load net {ACC1:slc.psp.sva(13)} -attr vt d
+load netBundle {ACC1:slc.psp.sva} 14 {ACC1:slc.psp.sva(0)} {ACC1:slc.psp.sva(1)} {ACC1:slc.psp.sva(2)} {ACC1:slc.psp.sva(3)} {ACC1:slc.psp.sva(4)} {ACC1:slc.psp.sva(5)} {ACC1:slc.psp.sva(6)} {ACC1:slc.psp.sva(7)} {ACC1:slc.psp.sva(8)} {ACC1:slc.psp.sva(9)} {ACC1:slc.psp.sva(10)} {ACC1:slc.psp.sva(11)} {ACC1:slc.psp.sva(12)} {ACC1:slc.psp.sva(13)} -attr xrf 51968 -attr oid 24 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.psp.sva}
+load net {acc.imod#24.sva(0)} -attr vt d
+load net {acc.imod#24.sva(1)} -attr vt d
+load net {acc.imod#24.sva(2)} -attr vt d
+load net {acc.imod#24.sva(3)} -attr vt d
+load net {acc.imod#24.sva(4)} -attr vt d
+load net {acc.imod#24.sva(5)} -attr vt d
+load netBundle {acc.imod#24.sva} 6 {acc.imod#24.sva(0)} {acc.imod#24.sva(1)} {acc.imod#24.sva(2)} {acc.imod#24.sva(3)} {acc.imod#24.sva(4)} {acc.imod#24.sva(5)} -attr xrf 51969 -attr oid 25 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load net {ACC1:acc#228.psp.sva(0)} -attr vt d
+load net {ACC1:acc#228.psp.sva(1)} -attr vt d
+load net {ACC1:acc#228.psp.sva(2)} -attr vt d
+load net {ACC1:acc#228.psp.sva(3)} -attr vt d
+load net {ACC1:acc#228.psp.sva(4)} -attr vt d
+load net {ACC1:acc#228.psp.sva(5)} -attr vt d
+load net {ACC1:acc#228.psp.sva(6)} -attr vt d
+load net {ACC1:acc#228.psp.sva(7)} -attr vt d
+load net {ACC1:acc#228.psp.sva(8)} -attr vt d
+load net {ACC1:acc#228.psp.sva(9)} -attr vt d
+load net {ACC1:acc#228.psp.sva(10)} -attr vt d
+load net {ACC1:acc#228.psp.sva(11)} -attr vt d
+load netBundle {ACC1:acc#228.psp.sva} 12 {ACC1:acc#228.psp.sva(0)} {ACC1:acc#228.psp.sva(1)} {ACC1:acc#228.psp.sva(2)} {ACC1:acc#228.psp.sva(3)} {ACC1:acc#228.psp.sva(4)} {ACC1:acc#228.psp.sva(5)} {ACC1:acc#228.psp.sva(6)} {ACC1:acc#228.psp.sva(7)} {ACC1:acc#228.psp.sva(8)} {ACC1:acc#228.psp.sva(9)} {ACC1:acc#228.psp.sva(10)} {ACC1:acc#228.psp.sva(11)} -attr xrf 51970 -attr oid 26 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#509.cse(0)} -attr vt d
+load net {ACC1:acc#509.cse(1)} -attr vt d
+load net {ACC1:acc#509.cse(2)} -attr vt d
+load netBundle {ACC1:acc#509.cse} 3 {ACC1:acc#509.cse(0)} {ACC1:acc#509.cse(1)} {ACC1:acc#509.cse(2)} -attr xrf 51971 -attr oid 27 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#506.cse(0)} -attr vt d
+load net {ACC1:acc#506.cse(1)} -attr vt d
+load net {ACC1:acc#506.cse(2)} -attr vt d
+load netBundle {ACC1:acc#506.cse} 3 {ACC1:acc#506.cse(0)} {ACC1:acc#506.cse(1)} {ACC1:acc#506.cse(2)} -attr xrf 51972 -attr oid 28 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#562.ncse(0)} -attr vt d
+load net {ACC1:acc#562.ncse(1)} -attr vt d
+load net {ACC1:acc#562.ncse(2)} -attr vt d
+load net {ACC1:acc#562.ncse(3)} -attr vt d
+load netBundle {ACC1:acc#562.ncse} 4 {ACC1:acc#562.ncse(0)} {ACC1:acc#562.ncse(1)} {ACC1:acc#562.ncse(2)} {ACC1:acc#562.ncse(3)} -attr xrf 51973 -attr oid 29 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#502.cse(0)} -attr vt d
+load net {ACC1:acc#502.cse(1)} -attr vt d
+load net {ACC1:acc#502.cse(2)} -attr vt d
+load netBundle {ACC1:acc#502.cse} 3 {ACC1:acc#502.cse(0)} {ACC1:acc#502.cse(1)} {ACC1:acc#502.cse(2)} -attr xrf 51974 -attr oid 30 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#489.cse(0)} -attr vt d
+load net {ACC1:acc#489.cse(1)} -attr vt d
+load net {ACC1:acc#489.cse(2)} -attr vt d
+load netBundle {ACC1:acc#489.cse} 3 {ACC1:acc#489.cse(0)} {ACC1:acc#489.cse(1)} {ACC1:acc#489.cse(2)} -attr xrf 51975 -attr oid 31 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#226.psp.sva(0)} -attr vt d
+load net {ACC1:acc#226.psp.sva(1)} -attr vt d
+load net {ACC1:acc#226.psp.sva(2)} -attr vt d
+load net {ACC1:acc#226.psp.sva(3)} -attr vt d
+load net {ACC1:acc#226.psp.sva(4)} -attr vt d
+load net {ACC1:acc#226.psp.sva(5)} -attr vt d
+load net {ACC1:acc#226.psp.sva(6)} -attr vt d
+load net {ACC1:acc#226.psp.sva(7)} -attr vt d
+load net {ACC1:acc#226.psp.sva(8)} -attr vt d
+load net {ACC1:acc#226.psp.sva(9)} -attr vt d
+load net {ACC1:acc#226.psp.sva(10)} -attr vt d
+load net {ACC1:acc#226.psp.sva(11)} -attr vt d
+load netBundle {ACC1:acc#226.psp.sva} 12 {ACC1:acc#226.psp.sva(0)} {ACC1:acc#226.psp.sva(1)} {ACC1:acc#226.psp.sva(2)} {ACC1:acc#226.psp.sva(3)} {ACC1:acc#226.psp.sva(4)} {ACC1:acc#226.psp.sva(5)} {ACC1:acc#226.psp.sva(6)} {ACC1:acc#226.psp.sva(7)} {ACC1:acc#226.psp.sva(8)} {ACC1:acc#226.psp.sva(9)} {ACC1:acc#226.psp.sva(10)} {ACC1:acc#226.psp.sva(11)} -attr xrf 51976 -attr oid 32 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#553.ncse(0)} -attr vt d
+load net {ACC1:acc#553.ncse(1)} -attr vt d
+load net {ACC1:acc#553.ncse(2)} -attr vt d
+load net {ACC1:acc#553.ncse(3)} -attr vt d
+load netBundle {ACC1:acc#553.ncse} 4 {ACC1:acc#553.ncse(0)} {ACC1:acc#553.ncse(1)} {ACC1:acc#553.ncse(2)} {ACC1:acc#553.ncse(3)} -attr xrf 51977 -attr oid 33 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#224.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(2)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(3)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(4)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(5)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(6)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(7)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(8)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(9)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(10)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(11)} -attr vt d
+load netBundle {ACC1:acc#224.psp#1.sva} 12 {ACC1:acc#224.psp#1.sva(0)} {ACC1:acc#224.psp#1.sva(1)} {ACC1:acc#224.psp#1.sva(2)} {ACC1:acc#224.psp#1.sva(3)} {ACC1:acc#224.psp#1.sva(4)} {ACC1:acc#224.psp#1.sva(5)} {ACC1:acc#224.psp#1.sva(6)} {ACC1:acc#224.psp#1.sva(7)} {ACC1:acc#224.psp#1.sva(8)} {ACC1:acc#224.psp#1.sva(9)} {ACC1:acc#224.psp#1.sva(10)} {ACC1:acc#224.psp#1.sva(11)} -attr xrf 51978 -attr oid 34 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp.sva(0)} -attr vt d
+load net {ACC1:acc#224.psp.sva(1)} -attr vt d
+load net {ACC1:acc#224.psp.sva(2)} -attr vt d
+load net {ACC1:acc#224.psp.sva(3)} -attr vt d
+load net {ACC1:acc#224.psp.sva(4)} -attr vt d
+load net {ACC1:acc#224.psp.sva(5)} -attr vt d
+load net {ACC1:acc#224.psp.sva(6)} -attr vt d
+load net {ACC1:acc#224.psp.sva(7)} -attr vt d
+load net {ACC1:acc#224.psp.sva(8)} -attr vt d
+load net {ACC1:acc#224.psp.sva(9)} -attr vt d
+load net {ACC1:acc#224.psp.sva(10)} -attr vt d
+load net {ACC1:acc#224.psp.sva(11)} -attr vt d
+load netBundle {ACC1:acc#224.psp.sva} 12 {ACC1:acc#224.psp.sva(0)} {ACC1:acc#224.psp.sva(1)} {ACC1:acc#224.psp.sva(2)} {ACC1:acc#224.psp.sva(3)} {ACC1:acc#224.psp.sva(4)} {ACC1:acc#224.psp.sva(5)} {ACC1:acc#224.psp.sva(6)} {ACC1:acc#224.psp.sva(7)} {ACC1:acc#224.psp.sva(8)} {ACC1:acc#224.psp.sva(9)} {ACC1:acc#224.psp.sva(10)} {ACC1:acc#224.psp.sva(11)} -attr xrf 51979 -attr oid 35 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#516.cse(0)} -attr vt d
+load net {ACC1:acc#516.cse(1)} -attr vt d
+load net {ACC1:acc#516.cse(2)} -attr vt d
+load netBundle {ACC1:acc#516.cse} 3 {ACC1:acc#516.cse(0)} {ACC1:acc#516.cse(1)} {ACC1:acc#516.cse(2)} -attr xrf 51980 -attr oid 36 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#221.psp.sva(0)} -attr vt d
+load net {ACC1:acc#221.psp.sva(1)} -attr vt d
+load net {ACC1:acc#221.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#221.psp.sva} 3 {ACC1:acc#221.psp.sva(0)} {ACC1:acc#221.psp.sva(1)} {ACC1:acc#221.psp.sva(2)} -attr xrf 51981 -attr oid 37 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp.sva}
+load net {ACC1:acc#221.psp#2.sva(0)} -attr vt d
+load net {ACC1:acc#221.psp#2.sva(1)} -attr vt d
+load net {ACC1:acc#221.psp#2.sva(2)} -attr vt d
+load netBundle {ACC1:acc#221.psp#2.sva} 3 {ACC1:acc#221.psp#2.sva(0)} {ACC1:acc#221.psp#2.sva(1)} {ACC1:acc#221.psp#2.sva(2)} -attr xrf 51982 -attr oid 38 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp#2.sva}
+load net {ACC1:acc#219.psp#2.sva(0)} -attr vt d
+load net {ACC1:acc#219.psp#2.sva(1)} -attr vt d
+load net {ACC1:acc#219.psp#2.sva(2)} -attr vt d
+load netBundle {ACC1:acc#219.psp#2.sva} 3 {ACC1:acc#219.psp#2.sva(0)} {ACC1:acc#219.psp#2.sva(1)} {ACC1:acc#219.psp#2.sva(2)} -attr xrf 51983 -attr oid 39 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#2.sva}
+load net {ACC1:acc#222.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#222.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#222.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#222.psp#1.sva} 3 {ACC1:acc#222.psp#1.sva(0)} {ACC1:acc#222.psp#1.sva(1)} {ACC1:acc#222.psp#1.sva(2)} -attr xrf 51984 -attr oid 40 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp#1.sva}
+load net {ACC1:acc#219.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#219.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#219.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#219.psp#1.sva} 3 {ACC1:acc#219.psp#1.sva(0)} {ACC1:acc#219.psp#1.sva(1)} {ACC1:acc#219.psp#1.sva(2)} -attr xrf 51985 -attr oid 41 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#1.sva}
+load net {ACC1:acc#724.cse(0)} -attr vt d
+load net {ACC1:acc#724.cse(1)} -attr vt d
+load net {ACC1:acc#724.cse(2)} -attr vt d
+load netBundle {ACC1:acc#724.cse} 3 {ACC1:acc#724.cse(0)} {ACC1:acc#724.cse(1)} {ACC1:acc#724.cse(2)} -attr xrf 51986 -attr oid 42 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#724.cse}
+load net {ACC1:mul#57.itm(0)} -attr vt d
+load net {ACC1:mul#57.itm(1)} -attr vt d
+load net {ACC1:mul#57.itm(2)} -attr vt d
+load net {ACC1:mul#57.itm(3)} -attr vt d
+load net {ACC1:mul#57.itm(4)} -attr vt d
+load net {ACC1:mul#57.itm(5)} -attr vt d
+load net {ACC1:mul#57.itm(6)} -attr vt d
+load net {ACC1:mul#57.itm(7)} -attr vt d
+load net {ACC1:mul#57.itm(8)} -attr vt d
+load net {ACC1:mul#57.itm(9)} -attr vt d
+load net {ACC1:mul#57.itm(10)} -attr vt d
+load net {ACC1:mul#57.itm(11)} -attr vt d
+load net {ACC1:mul#57.itm(12)} -attr vt d
+load net {ACC1:mul#57.itm(13)} -attr vt d
+load netBundle {ACC1:mul#57.itm} 14 {ACC1:mul#57.itm(0)} {ACC1:mul#57.itm(1)} {ACC1:mul#57.itm(2)} {ACC1:mul#57.itm(3)} {ACC1:mul#57.itm(4)} {ACC1:mul#57.itm(5)} {ACC1:mul#57.itm(6)} {ACC1:mul#57.itm(7)} {ACC1:mul#57.itm(8)} {ACC1:mul#57.itm(9)} {ACC1:mul#57.itm(10)} {ACC1:mul#57.itm(11)} {ACC1:mul#57.itm(12)} {ACC1:mul#57.itm(13)} -attr xrf 51987 -attr oid 43 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:acc#223.psp.sva(0)} -attr vt d
+load net {ACC1:acc#223.psp.sva(1)} -attr vt d
+load net {ACC1:acc#223.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#223.psp.sva} 3 {ACC1:acc#223.psp.sva(0)} {ACC1:acc#223.psp.sva(1)} {ACC1:acc#223.psp.sva(2)} -attr xrf 51988 -attr oid 44 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp.sva}
+load net {ACC1:acc#220.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#220.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#220.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#220.psp#1.sva} 3 {ACC1:acc#220.psp#1.sva(0)} {ACC1:acc#220.psp#1.sva(1)} {ACC1:acc#220.psp#1.sva(2)} -attr xrf 51989 -attr oid 45 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.psp#1.sva}
+load net {ACC1:acc#220.psp.sva(0)} -attr vt d
+load net {ACC1:acc#220.psp.sva(1)} -attr vt d
+load net {ACC1:acc#220.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#220.psp.sva} 3 {ACC1:acc#220.psp.sva(0)} {ACC1:acc#220.psp.sva(1)} {ACC1:acc#220.psp.sva(2)} -attr xrf 51990 -attr oid 46 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.psp.sva}
+load net {ACC1:acc#222.psp.sva(0)} -attr vt d
+load net {ACC1:acc#222.psp.sva(1)} -attr vt d
+load net {ACC1:acc#222.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#222.psp.sva} 3 {ACC1:acc#222.psp.sva(0)} {ACC1:acc#222.psp.sva(1)} {ACC1:acc#222.psp.sva(2)} -attr xrf 51991 -attr oid 47 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp.sva}
+load net {ACC1:acc#673.cse(0)} -attr vt d
+load net {ACC1:acc#673.cse(1)} -attr vt d
+load net {ACC1:acc#673.cse(2)} -attr vt d
+load netBundle {ACC1:acc#673.cse} 3 {ACC1:acc#673.cse(0)} {ACC1:acc#673.cse(1)} {ACC1:acc#673.cse(2)} -attr xrf 51992 -attr oid 48 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#223.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#223.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#223.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#223.psp#1.sva} 3 {ACC1:acc#223.psp#1.sva(0)} {ACC1:acc#223.psp#1.sva(1)} {ACC1:acc#223.psp#1.sva(2)} -attr xrf 51993 -attr oid 49 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp#1.sva}
+load net {ACC1:acc#699.cse(0)} -attr vt d
+load net {ACC1:acc#699.cse(1)} -attr vt d
+load net {ACC1:acc#699.cse(2)} -attr vt d
+load netBundle {ACC1:acc#699.cse} 3 {ACC1:acc#699.cse(0)} {ACC1:acc#699.cse(1)} {ACC1:acc#699.cse(2)} -attr xrf 51994 -attr oid 50 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {mux.itm(0)} -attr vt d
+load net {mux.itm(1)} -attr vt d
+load net {mux.itm(2)} -attr vt d
+load net {mux.itm(3)} -attr vt d
+load net {mux.itm(4)} -attr vt d
+load net {mux.itm(5)} -attr vt d
+load net {mux.itm(6)} -attr vt d
+load net {mux.itm(7)} -attr vt d
+load net {mux.itm(8)} -attr vt d
+load net {mux.itm(9)} -attr vt d
+load net {mux.itm(10)} -attr vt d
+load net {mux.itm(11)} -attr vt d
+load net {mux.itm(12)} -attr vt d
+load net {mux.itm(13)} -attr vt d
+load net {mux.itm(14)} -attr vt d
+load net {mux.itm(15)} -attr vt d
+load net {mux.itm(16)} -attr vt d
+load net {mux.itm(17)} -attr vt d
+load net {mux.itm(18)} -attr vt d
+load net {mux.itm(19)} -attr vt d
+load net {mux.itm(20)} -attr vt d
+load net {mux.itm(21)} -attr vt d
+load net {mux.itm(22)} -attr vt d
+load net {mux.itm(23)} -attr vt d
+load net {mux.itm(24)} -attr vt d
+load net {mux.itm(25)} -attr vt d
+load net {mux.itm(26)} -attr vt d
+load net {mux.itm(27)} -attr vt d
+load net {mux.itm(28)} -attr vt d
+load net {mux.itm(29)} -attr vt d
+load netBundle {mux.itm} 30 {mux.itm(0)} {mux.itm(1)} {mux.itm(2)} {mux.itm(3)} {mux.itm(4)} {mux.itm(5)} {mux.itm(6)} {mux.itm(7)} {mux.itm(8)} {mux.itm(9)} {mux.itm(10)} {mux.itm(11)} {mux.itm(12)} {mux.itm(13)} {mux.itm(14)} {mux.itm(15)} {mux.itm(16)} {mux.itm(17)} {mux.itm(18)} {mux.itm(19)} {mux.itm(20)} {mux.itm(21)} {mux.itm(22)} {mux.itm(23)} {mux.itm(24)} {mux.itm(25)} {mux.itm(26)} {mux.itm(27)} {mux.itm(28)} {mux.itm(29)} -attr xrf 51995 -attr oid 51 -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {FRAME:conc#11.itm(0)} -attr vt d
+load net {FRAME:conc#11.itm(1)} -attr vt d
+load net {FRAME:conc#11.itm(2)} -attr vt d
+load net {FRAME:conc#11.itm(3)} -attr vt d
+load net {FRAME:conc#11.itm(4)} -attr vt d
+load net {FRAME:conc#11.itm(5)} -attr vt d
+load net {FRAME:conc#11.itm(6)} -attr vt d
+load net {FRAME:conc#11.itm(7)} -attr vt d
+load net {FRAME:conc#11.itm(8)} -attr vt d
+load net {FRAME:conc#11.itm(9)} -attr vt d
+load net {FRAME:conc#11.itm(10)} -attr vt d
+load net {FRAME:conc#11.itm(11)} -attr vt d
+load net {FRAME:conc#11.itm(12)} -attr vt d
+load net {FRAME:conc#11.itm(13)} -attr vt d
+load net {FRAME:conc#11.itm(14)} -attr vt d
+load net {FRAME:conc#11.itm(15)} -attr vt d
+load net {FRAME:conc#11.itm(16)} -attr vt d
+load net {FRAME:conc#11.itm(17)} -attr vt d
+load net {FRAME:conc#11.itm(18)} -attr vt d
+load net {FRAME:conc#11.itm(19)} -attr vt d
+load net {FRAME:conc#11.itm(20)} -attr vt d
+load net {FRAME:conc#11.itm(21)} -attr vt d
+load net {FRAME:conc#11.itm(22)} -attr vt d
+load net {FRAME:conc#11.itm(23)} -attr vt d
+load net {FRAME:conc#11.itm(24)} -attr vt d
+load net {FRAME:conc#11.itm(25)} -attr vt d
+load net {FRAME:conc#11.itm(26)} -attr vt d
+load net {FRAME:conc#11.itm(27)} -attr vt d
+load net {FRAME:conc#11.itm(28)} -attr vt d
+load net {FRAME:conc#11.itm(29)} -attr vt d
+load netBundle {FRAME:conc#11.itm} 30 {FRAME:conc#11.itm(0)} {FRAME:conc#11.itm(1)} {FRAME:conc#11.itm(2)} {FRAME:conc#11.itm(3)} {FRAME:conc#11.itm(4)} {FRAME:conc#11.itm(5)} {FRAME:conc#11.itm(6)} {FRAME:conc#11.itm(7)} {FRAME:conc#11.itm(8)} {FRAME:conc#11.itm(9)} {FRAME:conc#11.itm(10)} {FRAME:conc#11.itm(11)} {FRAME:conc#11.itm(12)} {FRAME:conc#11.itm(13)} {FRAME:conc#11.itm(14)} {FRAME:conc#11.itm(15)} {FRAME:conc#11.itm(16)} {FRAME:conc#11.itm(17)} {FRAME:conc#11.itm(18)} {FRAME:conc#11.itm(19)} {FRAME:conc#11.itm(20)} {FRAME:conc#11.itm(21)} {FRAME:conc#11.itm(22)} {FRAME:conc#11.itm(23)} {FRAME:conc#11.itm(24)} {FRAME:conc#11.itm(25)} {FRAME:conc#11.itm(26)} {FRAME:conc#11.itm(27)} {FRAME:conc#11.itm(28)} {FRAME:conc#11.itm(29)} -attr xrf 51996 -attr oid 52 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(0)} -attr vt d
+load net {FRAME:or.itm(1)} -attr vt d
+load net {FRAME:or.itm(2)} -attr vt d
+load net {FRAME:or.itm(3)} -attr vt d
+load net {FRAME:or.itm(4)} -attr vt d
+load net {FRAME:or.itm(5)} -attr vt d
+load net {FRAME:or.itm(6)} -attr vt d
+load net {FRAME:or.itm(7)} -attr vt d
+load net {FRAME:or.itm(8)} -attr vt d
+load net {FRAME:or.itm(9)} -attr vt d
+load netBundle {FRAME:or.itm} 10 {FRAME:or.itm(0)} {FRAME:or.itm(1)} {FRAME:or.itm(2)} {FRAME:or.itm(3)} {FRAME:or.itm(4)} {FRAME:or.itm(5)} {FRAME:or.itm(6)} {FRAME:or.itm(7)} {FRAME:or.itm(8)} {FRAME:or.itm(9)} -attr xrf 51997 -attr oid 53 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(3)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(4)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(5)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(6)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(7)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(8)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(9)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#4.itm} 10 {slc(FRAME:acc#2.psp.sva)#4.itm(0)} {slc(FRAME:acc#2.psp.sva)#4.itm(1)} {slc(FRAME:acc#2.psp.sva)#4.itm(2)} {slc(FRAME:acc#2.psp.sva)#4.itm(3)} {slc(FRAME:acc#2.psp.sva)#4.itm(4)} {slc(FRAME:acc#2.psp.sva)#4.itm(5)} {slc(FRAME:acc#2.psp.sva)#4.itm(6)} {slc(FRAME:acc#2.psp.sva)#4.itm(7)} {slc(FRAME:acc#2.psp.sva)#4.itm(8)} {slc(FRAME:acc#2.psp.sva)#4.itm(9)} -attr xrf 51998 -attr oid 54 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {conc#878.itm(0)} -attr vt d
+load net {conc#878.itm(1)} -attr vt d
+load net {conc#878.itm(2)} -attr vt d
+load net {conc#878.itm(3)} -attr vt d
+load net {conc#878.itm(4)} -attr vt d
+load net {conc#878.itm(5)} -attr vt d
+load net {conc#878.itm(6)} -attr vt d
+load net {conc#878.itm(7)} -attr vt d
+load net {conc#878.itm(8)} -attr vt d
+load net {conc#878.itm(9)} -attr vt d
+load netBundle {conc#878.itm} 10 {conc#878.itm(0)} {conc#878.itm(1)} {conc#878.itm(2)} {conc#878.itm(3)} {conc#878.itm(4)} {conc#878.itm(5)} {conc#878.itm(6)} {conc#878.itm(7)} {conc#878.itm(8)} {conc#878.itm(9)} -attr xrf 51999 -attr oid 55 -attr vt d -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {slc(FRAME:acc#2.psp.sva)#5.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#5.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#5.itm} 2 {slc(FRAME:acc#2.psp.sva)#5.itm(0)} {slc(FRAME:acc#2.psp.sva)#5.itm(1)} -attr xrf 52000 -attr oid 56 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#5.itm}
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(3)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#2.itm} 4 {slc(FRAME:acc#2.psp.sva)#2.itm(0)} {slc(FRAME:acc#2.psp.sva)#2.itm(1)} {slc(FRAME:acc#2.psp.sva)#2.itm(2)} {slc(FRAME:acc#2.psp.sva)#2.itm(3)} -attr xrf 52001 -attr oid 57 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#2.itm}
+load net {FRAME:or#3.itm(0)} -attr vt d
+load net {FRAME:or#3.itm(1)} -attr vt d
+load net {FRAME:or#3.itm(2)} -attr vt d
+load net {FRAME:or#3.itm(3)} -attr vt d
+load net {FRAME:or#3.itm(4)} -attr vt d
+load net {FRAME:or#3.itm(5)} -attr vt d
+load netBundle {FRAME:or#3.itm} 6 {FRAME:or#3.itm(0)} {FRAME:or#3.itm(1)} {FRAME:or#3.itm(2)} {FRAME:or#3.itm(3)} {FRAME:or#3.itm(4)} {FRAME:or#3.itm(5)} -attr xrf 52002 -attr oid 58 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(3)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(4)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(5)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#3.itm} 6 {slc(FRAME:acc#2.psp.sva)#3.itm(0)} {slc(FRAME:acc#2.psp.sva)#3.itm(1)} {slc(FRAME:acc#2.psp.sva)#3.itm(2)} {slc(FRAME:acc#2.psp.sva)#3.itm(3)} {slc(FRAME:acc#2.psp.sva)#3.itm(4)} {slc(FRAME:acc#2.psp.sva)#3.itm(5)} -attr xrf 52003 -attr oid 59 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {conc#879.itm(0)} -attr vt d
+load net {conc#879.itm(1)} -attr vt d
+load net {conc#879.itm(2)} -attr vt d
+load net {conc#879.itm(3)} -attr vt d
+load net {conc#879.itm(4)} -attr vt d
+load net {conc#879.itm(5)} -attr vt d
+load netBundle {conc#879.itm} 6 {conc#879.itm(0)} {conc#879.itm(1)} {conc#879.itm(2)} {conc#879.itm(3)} {conc#879.itm(4)} {conc#879.itm(5)} -attr xrf 52004 -attr oid 60 -attr vt d -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {slc(FRAME:acc#2.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#1.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#1.itm} 2 {slc(FRAME:acc#2.psp.sva)#1.itm(0)} {slc(FRAME:acc#2.psp.sva)#1.itm(1)} -attr xrf 52005 -attr oid 61 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#1.itm}
+load net {slc(FRAME:acc#2.psp.sva).itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(3)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(4)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(5)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(6)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(7)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(8)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(9)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva).itm} 10 {slc(FRAME:acc#2.psp.sva).itm(0)} {slc(FRAME:acc#2.psp.sva).itm(1)} {slc(FRAME:acc#2.psp.sva).itm(2)} {slc(FRAME:acc#2.psp.sva).itm(3)} {slc(FRAME:acc#2.psp.sva).itm(4)} {slc(FRAME:acc#2.psp.sva).itm(5)} {slc(FRAME:acc#2.psp.sva).itm(6)} {slc(FRAME:acc#2.psp.sva).itm(7)} {slc(FRAME:acc#2.psp.sva).itm(8)} {slc(FRAME:acc#2.psp.sva).itm(9)} -attr xrf 52006 -attr oid 62 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva).itm}
+load net {ACC1:acc#659.itm(0)} -attr vt d
+load net {ACC1:acc#659.itm(1)} -attr vt d
+load net {ACC1:acc#659.itm(2)} -attr vt d
+load net {ACC1:acc#659.itm(3)} -attr vt d
+load net {ACC1:acc#659.itm(4)} -attr vt d
+load net {ACC1:acc#659.itm(5)} -attr vt d
+load net {ACC1:acc#659.itm(6)} -attr vt d
+load net {ACC1:acc#659.itm(7)} -attr vt d
+load net {ACC1:acc#659.itm(8)} -attr vt d
+load net {ACC1:acc#659.itm(9)} -attr vt d
+load net {ACC1:acc#659.itm(10)} -attr vt d
+load net {ACC1:acc#659.itm(11)} -attr vt d
+load net {ACC1:acc#659.itm(12)} -attr vt d
+load netBundle {ACC1:acc#659.itm} 13 {ACC1:acc#659.itm(0)} {ACC1:acc#659.itm(1)} {ACC1:acc#659.itm(2)} {ACC1:acc#659.itm(3)} {ACC1:acc#659.itm(4)} {ACC1:acc#659.itm(5)} {ACC1:acc#659.itm(6)} {ACC1:acc#659.itm(7)} {ACC1:acc#659.itm(8)} {ACC1:acc#659.itm(9)} {ACC1:acc#659.itm(10)} {ACC1:acc#659.itm(11)} {ACC1:acc#659.itm(12)} -attr xrf 52007 -attr oid 63 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#654.itm(0)} -attr vt d
+load net {ACC1:acc#654.itm(1)} -attr vt d
+load net {ACC1:acc#654.itm(2)} -attr vt d
+load net {ACC1:acc#654.itm(3)} -attr vt d
+load net {ACC1:acc#654.itm(4)} -attr vt d
+load net {ACC1:acc#654.itm(5)} -attr vt d
+load net {ACC1:acc#654.itm(6)} -attr vt d
+load net {ACC1:acc#654.itm(7)} -attr vt d
+load net {ACC1:acc#654.itm(8)} -attr vt d
+load net {ACC1:acc#654.itm(9)} -attr vt d
+load net {ACC1:acc#654.itm(10)} -attr vt d
+load net {ACC1:acc#654.itm(11)} -attr vt d
+load netBundle {ACC1:acc#654.itm} 12 {ACC1:acc#654.itm(0)} {ACC1:acc#654.itm(1)} {ACC1:acc#654.itm(2)} {ACC1:acc#654.itm(3)} {ACC1:acc#654.itm(4)} {ACC1:acc#654.itm(5)} {ACC1:acc#654.itm(6)} {ACC1:acc#654.itm(7)} {ACC1:acc#654.itm(8)} {ACC1:acc#654.itm(9)} {ACC1:acc#654.itm(10)} {ACC1:acc#654.itm(11)} -attr xrf 52008 -attr oid 64 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {conc#880.itm(0)} -attr vt d
+load net {conc#880.itm(1)} -attr vt d
+load net {conc#880.itm(2)} -attr vt d
+load net {conc#880.itm(3)} -attr vt d
+load net {conc#880.itm(4)} -attr vt d
+load net {conc#880.itm(5)} -attr vt d
+load net {conc#880.itm(6)} -attr vt d
+load net {conc#880.itm(7)} -attr vt d
+load net {conc#880.itm(8)} -attr vt d
+load net {conc#880.itm(9)} -attr vt d
+load net {conc#880.itm(10)} -attr vt d
+load netBundle {conc#880.itm} 11 {conc#880.itm(0)} {conc#880.itm(1)} {conc#880.itm(2)} {conc#880.itm(3)} {conc#880.itm(4)} {conc#880.itm(5)} {conc#880.itm(6)} {conc#880.itm(7)} {conc#880.itm(8)} {conc#880.itm(9)} {conc#880.itm(10)} -attr xrf 52009 -attr oid 65 -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1:conc#1105.itm(0)} -attr vt d
+load net {ACC1:conc#1105.itm(1)} -attr vt d
+load net {ACC1:conc#1105.itm(2)} -attr vt d
+load net {ACC1:conc#1105.itm(3)} -attr vt d
+load net {ACC1:conc#1105.itm(4)} -attr vt d
+load net {ACC1:conc#1105.itm(5)} -attr vt d
+load net {ACC1:conc#1105.itm(6)} -attr vt d
+load net {ACC1:conc#1105.itm(7)} -attr vt d
+load net {ACC1:conc#1105.itm(8)} -attr vt d
+load net {ACC1:conc#1105.itm(9)} -attr vt d
+load net {ACC1:conc#1105.itm(10)} -attr vt d
+load netBundle {ACC1:conc#1105.itm} 11 {ACC1:conc#1105.itm(0)} {ACC1:conc#1105.itm(1)} {ACC1:conc#1105.itm(2)} {ACC1:conc#1105.itm(3)} {ACC1:conc#1105.itm(4)} {ACC1:conc#1105.itm(5)} {ACC1:conc#1105.itm(6)} {ACC1:conc#1105.itm(7)} {ACC1:conc#1105.itm(8)} {ACC1:conc#1105.itm(9)} {ACC1:conc#1105.itm(10)} -attr xrf 52010 -attr oid 66 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(0)} -attr vt d
+load net {ACC1:mul#58.itm(1)} -attr vt d
+load net {ACC1:mul#58.itm(2)} -attr vt d
+load net {ACC1:mul#58.itm(3)} -attr vt d
+load net {ACC1:mul#58.itm(4)} -attr vt d
+load net {ACC1:mul#58.itm(5)} -attr vt d
+load net {ACC1:mul#58.itm(6)} -attr vt d
+load net {ACC1:mul#58.itm(7)} -attr vt d
+load netBundle {ACC1:mul#58.itm} 8 {ACC1:mul#58.itm(0)} {ACC1:mul#58.itm(1)} {ACC1:mul#58.itm(2)} {ACC1:mul#58.itm(3)} {ACC1:mul#58.itm(4)} {ACC1:mul#58.itm(5)} {ACC1:mul#58.itm(6)} {ACC1:mul#58.itm(7)} -attr xrf 52011 -attr oid 67 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:acc#320.itm(0)} -attr vt d
+load net {ACC1:acc#320.itm(1)} -attr vt d
+load net {ACC1:acc#320.itm(2)} -attr vt d
+load net {ACC1:acc#320.itm(3)} -attr vt d
+load netBundle {ACC1:acc#320.itm} 4 {ACC1:acc#320.itm(0)} {ACC1:acc#320.itm(1)} {ACC1:acc#320.itm(2)} {ACC1:acc#320.itm(3)} -attr xrf 52012 -attr oid 68 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#321.itm(0)} -attr vt d
+load net {ACC1:acc#321.itm(1)} -attr vt d
+load net {ACC1:acc#321.itm(2)} -attr vt d
+load netBundle {ACC1:acc#321.itm} 3 {ACC1:acc#321.itm(0)} {ACC1:acc#321.itm(1)} {ACC1:acc#321.itm(2)} -attr xrf 52013 -attr oid 69 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#322.itm(0)} -attr vt d
+load net {ACC1:acc#322.itm(1)} -attr vt d
+load net {ACC1:acc#322.itm(2)} -attr vt d
+load netBundle {ACC1:acc#322.itm} 3 {ACC1:acc#322.itm(0)} {ACC1:acc#322.itm(1)} {ACC1:acc#322.itm(2)} -attr xrf 52014 -attr oid 70 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#323.itm(0)} -attr vt d
+load net {ACC1:acc#323.itm(1)} -attr vt d
+load net {ACC1:acc#323.itm(2)} -attr vt d
+load netBundle {ACC1:acc#323.itm} 3 {ACC1:acc#323.itm(0)} {ACC1:acc#323.itm(1)} {ACC1:acc#323.itm(2)} -attr xrf 52015 -attr oid 71 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#324.itm(0)} -attr vt d
+load net {ACC1:acc#324.itm(1)} -attr vt d
+load net {ACC1:acc#324.itm(2)} -attr vt d
+load netBundle {ACC1:acc#324.itm} 3 {ACC1:acc#324.itm(0)} {ACC1:acc#324.itm(1)} {ACC1:acc#324.itm(2)} -attr xrf 52016 -attr oid 72 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#325.itm(0)} -attr vt d
+load net {ACC1:acc#325.itm(1)} -attr vt d
+load netBundle {ACC1:acc#325.itm} 2 {ACC1:acc#325.itm(0)} {ACC1:acc#325.itm(1)} -attr xrf 52017 -attr oid 73 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#326.itm(0)} -attr vt d
+load net {ACC1:acc#326.itm(1)} -attr vt d
+load netBundle {ACC1:acc#326.itm} 2 {ACC1:acc#326.itm(0)} {ACC1:acc#326.itm(1)} -attr xrf 52018 -attr oid 74 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1-3:exs#1051.itm(0)} -attr vt d
+load net {ACC1-3:exs#1051.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1051.itm} 2 {ACC1-3:exs#1051.itm(0)} {ACC1-3:exs#1051.itm(1)} -attr xrf 52019 -attr oid 75 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1051.itm}
+load net {ACC1:acc#653.itm(0)} -attr vt d
+load net {ACC1:acc#653.itm(1)} -attr vt d
+load net {ACC1:acc#653.itm(2)} -attr vt d
+load net {ACC1:acc#653.itm(3)} -attr vt d
+load net {ACC1:acc#653.itm(4)} -attr vt d
+load net {ACC1:acc#653.itm(5)} -attr vt d
+load net {ACC1:acc#653.itm(6)} -attr vt d
+load net {ACC1:acc#653.itm(7)} -attr vt d
+load net {ACC1:acc#653.itm(8)} -attr vt d
+load net {ACC1:acc#653.itm(9)} -attr vt d
+load net {ACC1:acc#653.itm(10)} -attr vt d
+load net {ACC1:acc#653.itm(11)} -attr vt d
+load netBundle {ACC1:acc#653.itm} 12 {ACC1:acc#653.itm(0)} {ACC1:acc#653.itm(1)} {ACC1:acc#653.itm(2)} {ACC1:acc#653.itm(3)} {ACC1:acc#653.itm(4)} {ACC1:acc#653.itm(5)} {ACC1:acc#653.itm(6)} {ACC1:acc#653.itm(7)} {ACC1:acc#653.itm(8)} {ACC1:acc#653.itm(9)} {ACC1:acc#653.itm(10)} {ACC1:acc#653.itm(11)} -attr xrf 52020 -attr oid 76 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1-1:acc#2.itm(0)} -attr vt d
+load net {ACC1-1:acc#2.itm(1)} -attr vt d
+load net {ACC1-1:acc#2.itm(2)} -attr vt d
+load net {ACC1-1:acc#2.itm(3)} -attr vt d
+load net {ACC1-1:acc#2.itm(4)} -attr vt d
+load net {ACC1-1:acc#2.itm(5)} -attr vt d
+load net {ACC1-1:acc#2.itm(6)} -attr vt d
+load net {ACC1-1:acc#2.itm(7)} -attr vt d
+load net {ACC1-1:acc#2.itm(8)} -attr vt d
+load net {ACC1-1:acc#2.itm(9)} -attr vt d
+load net {ACC1-1:acc#2.itm(10)} -attr vt d
+load netBundle {ACC1-1:acc#2.itm} 11 {ACC1-1:acc#2.itm(0)} {ACC1-1:acc#2.itm(1)} {ACC1-1:acc#2.itm(2)} {ACC1-1:acc#2.itm(3)} {ACC1-1:acc#2.itm(4)} {ACC1-1:acc#2.itm(5)} {ACC1-1:acc#2.itm(6)} {ACC1-1:acc#2.itm(7)} {ACC1-1:acc#2.itm(8)} {ACC1-1:acc#2.itm(9)} {ACC1-1:acc#2.itm(10)} -attr xrf 52021 -attr oid 77 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1:acc#690.itm(0)} -attr vt d
+load net {ACC1:acc#690.itm(1)} -attr vt d
+load net {ACC1:acc#690.itm(2)} -attr vt d
+load net {ACC1:acc#690.itm(3)} -attr vt d
+load net {ACC1:acc#690.itm(4)} -attr vt d
+load net {ACC1:acc#690.itm(5)} -attr vt d
+load net {ACC1:acc#690.itm(6)} -attr vt d
+load net {ACC1:acc#690.itm(7)} -attr vt d
+load net {ACC1:acc#690.itm(8)} -attr vt d
+load net {ACC1:acc#690.itm(9)} -attr vt d
+load net {ACC1:acc#690.itm(10)} -attr vt d
+load netBundle {ACC1:acc#690.itm} 11 {ACC1:acc#690.itm(0)} {ACC1:acc#690.itm(1)} {ACC1:acc#690.itm(2)} {ACC1:acc#690.itm(3)} {ACC1:acc#690.itm(4)} {ACC1:acc#690.itm(5)} {ACC1:acc#690.itm(6)} {ACC1:acc#690.itm(7)} {ACC1:acc#690.itm(8)} {ACC1:acc#690.itm(9)} {ACC1:acc#690.itm(10)} -attr xrf 52022 -attr oid 78 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#688.itm(0)} -attr vt d
+load net {ACC1:acc#688.itm(1)} -attr vt d
+load net {ACC1:acc#688.itm(2)} -attr vt d
+load net {ACC1:acc#688.itm(3)} -attr vt d
+load net {ACC1:acc#688.itm(4)} -attr vt d
+load net {ACC1:acc#688.itm(5)} -attr vt d
+load net {ACC1:acc#688.itm(6)} -attr vt d
+load net {ACC1:acc#688.itm(7)} -attr vt d
+load net {ACC1:acc#688.itm(8)} -attr vt d
+load net {ACC1:acc#688.itm(9)} -attr vt d
+load netBundle {ACC1:acc#688.itm} 10 {ACC1:acc#688.itm(0)} {ACC1:acc#688.itm(1)} {ACC1:acc#688.itm(2)} {ACC1:acc#688.itm(3)} {ACC1:acc#688.itm(4)} {ACC1:acc#688.itm(5)} {ACC1:acc#688.itm(6)} {ACC1:acc#688.itm(7)} {ACC1:acc#688.itm(8)} {ACC1:acc#688.itm(9)} -attr xrf 52023 -attr oid 79 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {conc#881.itm(0)} -attr vt d
+load net {conc#881.itm(1)} -attr vt d
+load net {conc#881.itm(2)} -attr vt d
+load net {conc#881.itm(3)} -attr vt d
+load net {conc#881.itm(4)} -attr vt d
+load net {conc#881.itm(5)} -attr vt d
+load net {conc#881.itm(6)} -attr vt d
+load net {conc#881.itm(7)} -attr vt d
+load net {conc#881.itm(8)} -attr vt d
+load netBundle {conc#881.itm} 9 {conc#881.itm(0)} {conc#881.itm(1)} {conc#881.itm(2)} {conc#881.itm(3)} {conc#881.itm(4)} {conc#881.itm(5)} {conc#881.itm(6)} {conc#881.itm(7)} {conc#881.itm(8)} -attr xrf 52024 -attr oid 80 -attr vt d -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {ACC1:acc#686.itm(0)} -attr vt d
+load net {ACC1:acc#686.itm(1)} -attr vt d
+load net {ACC1:acc#686.itm(2)} -attr vt d
+load net {ACC1:acc#686.itm(3)} -attr vt d
+load net {ACC1:acc#686.itm(4)} -attr vt d
+load net {ACC1:acc#686.itm(5)} -attr vt d
+load net {ACC1:acc#686.itm(6)} -attr vt d
+load net {ACC1:acc#686.itm(7)} -attr vt d
+load netBundle {ACC1:acc#686.itm} 8 {ACC1:acc#686.itm(0)} {ACC1:acc#686.itm(1)} {ACC1:acc#686.itm(2)} {ACC1:acc#686.itm(3)} {ACC1:acc#686.itm(4)} {ACC1:acc#686.itm(5)} {ACC1:acc#686.itm(6)} {ACC1:acc#686.itm(7)} -attr xrf 52025 -attr oid 81 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {conc#882.itm(0)} -attr vt d
+load net {conc#882.itm(1)} -attr vt d
+load net {conc#882.itm(2)} -attr vt d
+load net {conc#882.itm(3)} -attr vt d
+load net {conc#882.itm(4)} -attr vt d
+load net {conc#882.itm(5)} -attr vt d
+load net {conc#882.itm(6)} -attr vt d
+load net {conc#882.itm(7)} -attr vt d
+load netBundle {conc#882.itm} 8 {conc#882.itm(0)} {conc#882.itm(1)} {conc#882.itm(2)} {conc#882.itm(3)} {conc#882.itm(4)} {conc#882.itm(5)} {conc#882.itm(6)} {conc#882.itm(7)} -attr xrf 52026 -attr oid 82 -attr vt d -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {ACC1-1:exs#1055.itm(0)} -attr vt d
+load net {ACC1-1:exs#1055.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1055.itm} 2 {ACC1-1:exs#1055.itm(0)} {ACC1-1:exs#1055.itm(1)} -attr xrf 52027 -attr oid 83 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1055.itm}
+load net {ACC1:acc#683.itm(0)} -attr vt d
+load net {ACC1:acc#683.itm(1)} -attr vt d
+load net {ACC1:acc#683.itm(2)} -attr vt d
+load net {ACC1:acc#683.itm(3)} -attr vt d
+load net {ACC1:acc#683.itm(4)} -attr vt d
+load net {ACC1:acc#683.itm(5)} -attr vt d
+load net {ACC1:acc#683.itm(6)} -attr vt d
+load netBundle {ACC1:acc#683.itm} 7 {ACC1:acc#683.itm(0)} {ACC1:acc#683.itm(1)} {ACC1:acc#683.itm(2)} {ACC1:acc#683.itm(3)} {ACC1:acc#683.itm(4)} {ACC1:acc#683.itm(5)} {ACC1:acc#683.itm(6)} -attr xrf 52028 -attr oid 84 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {conc#883.itm(0)} -attr vt d
+load net {conc#883.itm(1)} -attr vt d
+load net {conc#883.itm(2)} -attr vt d
+load net {conc#883.itm(3)} -attr vt d
+load net {conc#883.itm(4)} -attr vt d
+load net {conc#883.itm(5)} -attr vt d
+load netBundle {conc#883.itm} 6 {conc#883.itm(0)} {conc#883.itm(1)} {conc#883.itm(2)} {conc#883.itm(3)} {conc#883.itm(4)} {conc#883.itm(5)} -attr xrf 52029 -attr oid 85 -attr vt d -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {ACC1-1:exs#1058.itm(0)} -attr vt d
+load net {ACC1-1:exs#1058.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1058.itm} 2 {ACC1-1:exs#1058.itm(0)} {ACC1-1:exs#1058.itm(1)} -attr xrf 52030 -attr oid 86 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1058.itm}
+load net {ACC1:acc#680.itm(0)} -attr vt d
+load net {ACC1:acc#680.itm(1)} -attr vt d
+load net {ACC1:acc#680.itm(2)} -attr vt d
+load net {ACC1:acc#680.itm(3)} -attr vt d
+load net {ACC1:acc#680.itm(4)} -attr vt d
+load netBundle {ACC1:acc#680.itm} 5 {ACC1:acc#680.itm(0)} {ACC1:acc#680.itm(1)} {ACC1:acc#680.itm(2)} {ACC1:acc#680.itm(3)} {ACC1:acc#680.itm(4)} -attr xrf 52031 -attr oid 87 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#676.itm(0)} -attr vt d
+load net {ACC1:acc#676.itm(1)} -attr vt d
+load net {ACC1:acc#676.itm(2)} -attr vt d
+load net {ACC1:acc#676.itm(3)} -attr vt d
+load netBundle {ACC1:acc#676.itm} 4 {ACC1:acc#676.itm(0)} {ACC1:acc#676.itm(1)} {ACC1:acc#676.itm(2)} {ACC1:acc#676.itm(3)} -attr xrf 52032 -attr oid 88 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:slc#153.itm(0)} -attr vt d
+load net {ACC1:slc#153.itm(1)} -attr vt d
+load net {ACC1:slc#153.itm(2)} -attr vt d
+load netBundle {ACC1:slc#153.itm} 3 {ACC1:slc#153.itm(0)} {ACC1:slc#153.itm(1)} {ACC1:slc#153.itm(2)} -attr xrf 52033 -attr oid 89 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#153.itm}
+load net {ACC1:acc#670.itm(0)} -attr vt d
+load net {ACC1:acc#670.itm(1)} -attr vt d
+load net {ACC1:acc#670.itm(2)} -attr vt d
+load net {ACC1:acc#670.itm(3)} -attr vt d
+load netBundle {ACC1:acc#670.itm} 4 {ACC1:acc#670.itm(0)} {ACC1:acc#670.itm(1)} {ACC1:acc#670.itm(2)} {ACC1:acc#670.itm(3)} -attr xrf 52034 -attr oid 90 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#670.itm}
+load net {exs.itm(0)} -attr vt d
+load net {exs.itm(1)} -attr vt d
+load net {exs.itm(2)} -attr vt d
+load netBundle {exs.itm} 3 {exs.itm(0)} {exs.itm(1)} {exs.itm(2)} -attr xrf 52035 -attr oid 91 -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {conc#884.itm(0)} -attr vt d
+load net {conc#884.itm(1)} -attr vt d
+load netBundle {conc#884.itm} 2 {conc#884.itm(0)} {conc#884.itm(1)} -attr xrf 52036 -attr oid 92 -attr vt d -attr @path {/sobel/sobel:core/conc#884.itm}
+load net {ACC1:exs#1474.itm(0)} -attr vt d
+load net {ACC1:exs#1474.itm(1)} -attr vt d
+load net {ACC1:exs#1474.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1474.itm} 3 {ACC1:exs#1474.itm(0)} {ACC1:exs#1474.itm(1)} {ACC1:exs#1474.itm(2)} -attr xrf 52037 -attr oid 93 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1474.itm}
+load net {ACC1:conc#1430.itm(0)} -attr vt d
+load net {ACC1:conc#1430.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1430.itm} 2 {ACC1:conc#1430.itm(0)} {ACC1:conc#1430.itm(1)} -attr xrf 52038 -attr oid 94 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1430.itm}
+load net {ACC1:slc#152.itm(0)} -attr vt d
+load net {ACC1:slc#152.itm(1)} -attr vt d
+load net {ACC1:slc#152.itm(2)} -attr vt d
+load netBundle {ACC1:slc#152.itm} 3 {ACC1:slc#152.itm(0)} {ACC1:slc#152.itm(1)} {ACC1:slc#152.itm(2)} -attr xrf 52039 -attr oid 95 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#152.itm}
+load net {ACC1:acc#669.itm(0)} -attr vt d
+load net {ACC1:acc#669.itm(1)} -attr vt d
+load net {ACC1:acc#669.itm(2)} -attr vt d
+load net {ACC1:acc#669.itm(3)} -attr vt d
+load netBundle {ACC1:acc#669.itm} 4 {ACC1:acc#669.itm(0)} {ACC1:acc#669.itm(1)} {ACC1:acc#669.itm(2)} {ACC1:acc#669.itm(3)} -attr xrf 52040 -attr oid 96 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#669.itm}
+load net {exs#46.itm(0)} -attr vt d
+load net {exs#46.itm(1)} -attr vt d
+load net {exs#46.itm(2)} -attr vt d
+load netBundle {exs#46.itm} 3 {exs#46.itm(0)} {exs#46.itm(1)} {exs#46.itm(2)} -attr xrf 52041 -attr oid 97 -attr vt d -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {conc#885.itm(0)} -attr vt d
+load net {conc#885.itm(1)} -attr vt d
+load netBundle {conc#885.itm} 2 {conc#885.itm(0)} {conc#885.itm(1)} -attr xrf 52042 -attr oid 98 -attr vt d -attr @path {/sobel/sobel:core/conc#885.itm}
+load net {ACC1:exs#1476.itm(0)} -attr vt d
+load net {ACC1:exs#1476.itm(1)} -attr vt d
+load net {ACC1:exs#1476.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1476.itm} 3 {ACC1:exs#1476.itm(0)} {ACC1:exs#1476.itm(1)} {ACC1:exs#1476.itm(2)} -attr xrf 52043 -attr oid 99 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1476.itm}
+load net {ACC1:conc#1428.itm(0)} -attr vt d
+load net {ACC1:conc#1428.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1428.itm} 2 {ACC1:conc#1428.itm(0)} {ACC1:conc#1428.itm(1)} -attr xrf 52044 -attr oid 100 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1428.itm}
+load net {ACC1:acc#675.itm(0)} -attr vt d
+load net {ACC1:acc#675.itm(1)} -attr vt d
+load net {ACC1:acc#675.itm(2)} -attr vt d
+load net {ACC1:acc#675.itm(3)} -attr vt d
+load netBundle {ACC1:acc#675.itm} 4 {ACC1:acc#675.itm(0)} {ACC1:acc#675.itm(1)} {ACC1:acc#675.itm(2)} {ACC1:acc#675.itm(3)} -attr xrf 52045 -attr oid 101 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:slc#151.itm(0)} -attr vt d
+load net {ACC1:slc#151.itm(1)} -attr vt d
+load net {ACC1:slc#151.itm(2)} -attr vt d
+load netBundle {ACC1:slc#151.itm} 3 {ACC1:slc#151.itm(0)} {ACC1:slc#151.itm(1)} {ACC1:slc#151.itm(2)} -attr xrf 52046 -attr oid 102 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#151.itm}
+load net {ACC1:acc#668.itm(0)} -attr vt d
+load net {ACC1:acc#668.itm(1)} -attr vt d
+load net {ACC1:acc#668.itm(2)} -attr vt d
+load net {ACC1:acc#668.itm(3)} -attr vt d
+load netBundle {ACC1:acc#668.itm} 4 {ACC1:acc#668.itm(0)} {ACC1:acc#668.itm(1)} {ACC1:acc#668.itm(2)} {ACC1:acc#668.itm(3)} -attr xrf 52047 -attr oid 103 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#668.itm}
+load net {exs#47.itm(0)} -attr vt d
+load net {exs#47.itm(1)} -attr vt d
+load net {exs#47.itm(2)} -attr vt d
+load netBundle {exs#47.itm} 3 {exs#47.itm(0)} {exs#47.itm(1)} {exs#47.itm(2)} -attr xrf 52048 -attr oid 104 -attr vt d -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {conc#886.itm(0)} -attr vt d
+load net {conc#886.itm(1)} -attr vt d
+load netBundle {conc#886.itm} 2 {conc#886.itm(0)} {conc#886.itm(1)} -attr xrf 52049 -attr oid 105 -attr vt d -attr @path {/sobel/sobel:core/conc#886.itm}
+load net {ACC1:exs#1478.itm(0)} -attr vt d
+load net {ACC1:exs#1478.itm(1)} -attr vt d
+load net {ACC1:exs#1478.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1478.itm} 3 {ACC1:exs#1478.itm(0)} {ACC1:exs#1478.itm(1)} {ACC1:exs#1478.itm(2)} -attr xrf 52050 -attr oid 106 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1478.itm}
+load net {ACC1:conc#1426.itm(0)} -attr vt d
+load net {ACC1:conc#1426.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1426.itm} 2 {ACC1:conc#1426.itm(0)} {ACC1:conc#1426.itm(1)} -attr xrf 52051 -attr oid 107 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1426.itm}
+load net {ACC1:slc#150.itm(0)} -attr vt d
+load net {ACC1:slc#150.itm(1)} -attr vt d
+load net {ACC1:slc#150.itm(2)} -attr vt d
+load netBundle {ACC1:slc#150.itm} 3 {ACC1:slc#150.itm(0)} {ACC1:slc#150.itm(1)} {ACC1:slc#150.itm(2)} -attr xrf 52052 -attr oid 108 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#150.itm}
+load net {ACC1:acc#667.itm(0)} -attr vt d
+load net {ACC1:acc#667.itm(1)} -attr vt d
+load net {ACC1:acc#667.itm(2)} -attr vt d
+load net {ACC1:acc#667.itm(3)} -attr vt d
+load netBundle {ACC1:acc#667.itm} 4 {ACC1:acc#667.itm(0)} {ACC1:acc#667.itm(1)} {ACC1:acc#667.itm(2)} {ACC1:acc#667.itm(3)} -attr xrf 52053 -attr oid 109 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#667.itm}
+load net {exs#48.itm(0)} -attr vt d
+load net {exs#48.itm(1)} -attr vt d
+load net {exs#48.itm(2)} -attr vt d
+load netBundle {exs#48.itm} 3 {exs#48.itm(0)} {exs#48.itm(1)} {exs#48.itm(2)} -attr xrf 52054 -attr oid 110 -attr vt d -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {conc#887.itm(0)} -attr vt d
+load net {conc#887.itm(1)} -attr vt d
+load netBundle {conc#887.itm} 2 {conc#887.itm(0)} {conc#887.itm(1)} -attr xrf 52055 -attr oid 111 -attr vt d -attr @path {/sobel/sobel:core/conc#887.itm}
+load net {ACC1:exs#1480.itm(0)} -attr vt d
+load net {ACC1:exs#1480.itm(1)} -attr vt d
+load net {ACC1:exs#1480.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1480.itm} 3 {ACC1:exs#1480.itm(0)} {ACC1:exs#1480.itm(1)} {ACC1:exs#1480.itm(2)} -attr xrf 52056 -attr oid 112 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1480.itm}
+load net {ACC1:conc#1424.itm(0)} -attr vt d
+load net {ACC1:conc#1424.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1424.itm} 2 {ACC1:conc#1424.itm(0)} {ACC1:conc#1424.itm(1)} -attr xrf 52057 -attr oid 113 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1424.itm}
+load net {ACC1:acc#687.itm(0)} -attr vt d
+load net {ACC1:acc#687.itm(1)} -attr vt d
+load net {ACC1:acc#687.itm(2)} -attr vt d
+load net {ACC1:acc#687.itm(3)} -attr vt d
+load net {ACC1:acc#687.itm(4)} -attr vt d
+load net {ACC1:acc#687.itm(5)} -attr vt d
+load net {ACC1:acc#687.itm(6)} -attr vt d
+load net {ACC1:acc#687.itm(7)} -attr vt d
+load net {ACC1:acc#687.itm(8)} -attr vt d
+load net {ACC1:acc#687.itm(9)} -attr vt d
+load netBundle {ACC1:acc#687.itm} 10 {ACC1:acc#687.itm(0)} {ACC1:acc#687.itm(1)} {ACC1:acc#687.itm(2)} {ACC1:acc#687.itm(3)} {ACC1:acc#687.itm(4)} {ACC1:acc#687.itm(5)} {ACC1:acc#687.itm(6)} {ACC1:acc#687.itm(7)} {ACC1:acc#687.itm(8)} {ACC1:acc#687.itm(9)} -attr xrf 52058 -attr oid 114 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#685.itm(0)} -attr vt d
+load net {ACC1:acc#685.itm(1)} -attr vt d
+load net {ACC1:acc#685.itm(2)} -attr vt d
+load net {ACC1:acc#685.itm(3)} -attr vt d
+load net {ACC1:acc#685.itm(4)} -attr vt d
+load net {ACC1:acc#685.itm(5)} -attr vt d
+load net {ACC1:acc#685.itm(6)} -attr vt d
+load net {ACC1:acc#685.itm(7)} -attr vt d
+load netBundle {ACC1:acc#685.itm} 8 {ACC1:acc#685.itm(0)} {ACC1:acc#685.itm(1)} {ACC1:acc#685.itm(2)} {ACC1:acc#685.itm(3)} {ACC1:acc#685.itm(4)} {ACC1:acc#685.itm(5)} {ACC1:acc#685.itm(6)} {ACC1:acc#685.itm(7)} -attr xrf 52059 -attr oid 115 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#682.itm(0)} -attr vt d
+load net {ACC1:acc#682.itm(1)} -attr vt d
+load net {ACC1:acc#682.itm(2)} -attr vt d
+load net {ACC1:acc#682.itm(3)} -attr vt d
+load net {ACC1:acc#682.itm(4)} -attr vt d
+load net {ACC1:acc#682.itm(5)} -attr vt d
+load netBundle {ACC1:acc#682.itm} 6 {ACC1:acc#682.itm(0)} {ACC1:acc#682.itm(1)} {ACC1:acc#682.itm(2)} {ACC1:acc#682.itm(3)} {ACC1:acc#682.itm(4)} {ACC1:acc#682.itm(5)} -attr xrf 52060 -attr oid 116 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#679.itm(0)} -attr vt d
+load net {ACC1:acc#679.itm(1)} -attr vt d
+load net {ACC1:acc#679.itm(2)} -attr vt d
+load net {ACC1:acc#679.itm(3)} -attr vt d
+load netBundle {ACC1:acc#679.itm} 4 {ACC1:acc#679.itm(0)} {ACC1:acc#679.itm(1)} {ACC1:acc#679.itm(2)} {ACC1:acc#679.itm(3)} -attr xrf 52061 -attr oid 117 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#674.itm(0)} -attr vt d
+load net {ACC1:acc#674.itm(1)} -attr vt d
+load net {ACC1:acc#674.itm(2)} -attr vt d
+load netBundle {ACC1:acc#674.itm} 3 {ACC1:acc#674.itm(0)} {ACC1:acc#674.itm(1)} {ACC1:acc#674.itm(2)} -attr xrf 52062 -attr oid 118 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load net {ACC1:slc#148.itm(0)} -attr vt d
+load net {ACC1:slc#148.itm(1)} -attr vt d
+load net {ACC1:slc#148.itm(2)} -attr vt d
+load netBundle {ACC1:slc#148.itm} 3 {ACC1:slc#148.itm(0)} {ACC1:slc#148.itm(1)} {ACC1:slc#148.itm(2)} -attr xrf 52063 -attr oid 119 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#148.itm}
+load net {ACC1:acc#665.itm(0)} -attr vt d
+load net {ACC1:acc#665.itm(1)} -attr vt d
+load net {ACC1:acc#665.itm(2)} -attr vt d
+load net {ACC1:acc#665.itm(3)} -attr vt d
+load netBundle {ACC1:acc#665.itm} 4 {ACC1:acc#665.itm(0)} {ACC1:acc#665.itm(1)} {ACC1:acc#665.itm(2)} {ACC1:acc#665.itm(3)} -attr xrf 52064 -attr oid 120 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#665.itm}
+load net {conc#888.itm(0)} -attr vt d
+load net {conc#888.itm(1)} -attr vt d
+load net {conc#888.itm(2)} -attr vt d
+load netBundle {conc#888.itm} 3 {conc#888.itm(0)} {conc#888.itm(1)} {conc#888.itm(2)} -attr xrf 52065 -attr oid 121 -attr vt d -attr @path {/sobel/sobel:core/conc#888.itm}
+load net {ACC1:conc#1420.itm(0)} -attr vt d
+load net {ACC1:conc#1420.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1420.itm} 2 {ACC1:conc#1420.itm(0)} {ACC1:conc#1420.itm(1)} -attr xrf 52066 -attr oid 122 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1420.itm}
+load net {slc(ACC1:acc#220.psp#1.sva)#3.itm(0)} -attr vt d
+load net {slc(ACC1:acc#220.psp#1.sva)#3.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#220.psp#1.sva)#3.itm} 2 {slc(ACC1:acc#220.psp#1.sva)#3.itm(0)} {slc(ACC1:acc#220.psp#1.sva)#3.itm(1)} -attr xrf 52067 -attr oid 123 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva)#3.itm}
+load net {ACC1:slc#149.itm(0)} -attr vt d
+load net {ACC1:slc#149.itm(1)} -attr vt d
+load net {ACC1:slc#149.itm(2)} -attr vt d
+load net {ACC1:slc#149.itm(3)} -attr vt d
+load netBundle {ACC1:slc#149.itm} 4 {ACC1:slc#149.itm(0)} {ACC1:slc#149.itm(1)} {ACC1:slc#149.itm(2)} {ACC1:slc#149.itm(3)} -attr xrf 52068 -attr oid 124 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#149.itm}
+load net {ACC1:acc#666.itm(0)} -attr vt d
+load net {ACC1:acc#666.itm(1)} -attr vt d
+load net {ACC1:acc#666.itm(2)} -attr vt d
+load net {ACC1:acc#666.itm(3)} -attr vt d
+load net {ACC1:acc#666.itm(4)} -attr vt d
+load netBundle {ACC1:acc#666.itm} 5 {ACC1:acc#666.itm(0)} {ACC1:acc#666.itm(1)} {ACC1:acc#666.itm(2)} {ACC1:acc#666.itm(3)} {ACC1:acc#666.itm(4)} -attr xrf 52069 -attr oid 125 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666.itm}
+load net {conc#889.itm(0)} -attr vt d
+load net {conc#889.itm(1)} -attr vt d
+load net {conc#889.itm(2)} -attr vt d
+load netBundle {conc#889.itm} 3 {conc#889.itm(0)} {conc#889.itm(1)} {conc#889.itm(2)} -attr xrf 52070 -attr oid 126 -attr vt d -attr @path {/sobel/sobel:core/conc#889.itm}
+load net {ACC1:conc#1422.itm(0)} -attr vt d
+load net {ACC1:conc#1422.itm(1)} -attr vt d
+load net {ACC1:conc#1422.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1422.itm} 3 {ACC1:conc#1422.itm(0)} {ACC1:conc#1422.itm(1)} {ACC1:conc#1422.itm(2)} -attr xrf 52071 -attr oid 127 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1422.itm}
+load net {ACC1:acc#678.itm(0)} -attr vt d
+load net {ACC1:acc#678.itm(1)} -attr vt d
+load net {ACC1:acc#678.itm(2)} -attr vt d
+load net {ACC1:acc#678.itm(3)} -attr vt d
+load net {ACC1:acc#678.itm(4)} -attr vt d
+load netBundle {ACC1:acc#678.itm} 5 {ACC1:acc#678.itm(0)} {ACC1:acc#678.itm(1)} {ACC1:acc#678.itm(2)} {ACC1:acc#678.itm(3)} {ACC1:acc#678.itm(4)} -attr xrf 52072 -attr oid 128 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1-1:conc#558.itm(0)} -attr vt d
+load net {ACC1-1:conc#558.itm(1)} -attr vt d
+load net {ACC1-1:conc#558.itm(2)} -attr vt d
+load net {ACC1-1:conc#558.itm(3)} -attr vt d
+load netBundle {ACC1-1:conc#558.itm} 4 {ACC1-1:conc#558.itm(0)} {ACC1-1:conc#558.itm(1)} {ACC1-1:conc#558.itm(2)} {ACC1-1:conc#558.itm(3)} -attr xrf 52073 -attr oid 129 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#558.itm}
+load net {ACC1-1:exs#1043.itm(0)} -attr vt d
+load net {ACC1-1:exs#1043.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1043.itm} 2 {ACC1-1:exs#1043.itm(0)} {ACC1-1:exs#1043.itm(1)} -attr xrf 52074 -attr oid 130 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1043.itm}
+load net {conc#890.itm(0)} -attr vt d
+load net {conc#890.itm(1)} -attr vt d
+load net {conc#890.itm(2)} -attr vt d
+load net {conc#890.itm(3)} -attr vt d
+load net {conc#890.itm(4)} -attr vt d
+load net {conc#890.itm(5)} -attr vt d
+load net {conc#890.itm(6)} -attr vt d
+load netBundle {conc#890.itm} 7 {conc#890.itm(0)} {conc#890.itm(1)} {conc#890.itm(2)} {conc#890.itm(3)} {conc#890.itm(4)} {conc#890.itm(5)} {conc#890.itm(6)} -attr xrf 52075 -attr oid 131 -attr vt d -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {ACC1:acc#684.itm(0)} -attr vt d
+load net {ACC1:acc#684.itm(1)} -attr vt d
+load net {ACC1:acc#684.itm(2)} -attr vt d
+load net {ACC1:acc#684.itm(3)} -attr vt d
+load net {ACC1:acc#684.itm(4)} -attr vt d
+load net {ACC1:acc#684.itm(5)} -attr vt d
+load net {ACC1:acc#684.itm(6)} -attr vt d
+load net {ACC1:acc#684.itm(7)} -attr vt d
+load netBundle {ACC1:acc#684.itm} 8 {ACC1:acc#684.itm(0)} {ACC1:acc#684.itm(1)} {ACC1:acc#684.itm(2)} {ACC1:acc#684.itm(3)} {ACC1:acc#684.itm(4)} {ACC1:acc#684.itm(5)} {ACC1:acc#684.itm(6)} {ACC1:acc#684.itm(7)} -attr xrf 52076 -attr oid 132 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1-1:exs#1045.itm(0)} -attr vt d
+load net {ACC1-1:exs#1045.itm(1)} -attr vt d
+load net {ACC1-1:exs#1045.itm(2)} -attr vt d
+load net {ACC1-1:exs#1045.itm(3)} -attr vt d
+load net {ACC1-1:exs#1045.itm(4)} -attr vt d
+load net {ACC1-1:exs#1045.itm(5)} -attr vt d
+load net {ACC1-1:exs#1045.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#1045.itm} 7 {ACC1-1:exs#1045.itm(0)} {ACC1-1:exs#1045.itm(1)} {ACC1-1:exs#1045.itm(2)} {ACC1-1:exs#1045.itm(3)} {ACC1-1:exs#1045.itm(4)} {ACC1-1:exs#1045.itm(5)} {ACC1-1:exs#1045.itm(6)} -attr xrf 52077 -attr oid 133 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {ACC1-1:conc#600.itm(0)} -attr vt d
+load net {ACC1-1:conc#600.itm(1)} -attr vt d
+load net {ACC1-1:conc#600.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#600.itm} 3 {ACC1-1:conc#600.itm(0)} {ACC1-1:conc#600.itm(1)} {ACC1-1:conc#600.itm(2)} -attr xrf 52078 -attr oid 134 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#600.itm}
+load net {ACC1-1:exs#1049.itm(0)} -attr vt d
+load net {ACC1-1:exs#1049.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1049.itm} 2 {ACC1-1:exs#1049.itm(0)} {ACC1-1:exs#1049.itm(1)} -attr xrf 52079 -attr oid 135 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1049.itm}
+load net {ACC1:acc#681.itm(0)} -attr vt d
+load net {ACC1:acc#681.itm(1)} -attr vt d
+load net {ACC1:acc#681.itm(2)} -attr vt d
+load net {ACC1:acc#681.itm(3)} -attr vt d
+load net {ACC1:acc#681.itm(4)} -attr vt d
+load net {ACC1:acc#681.itm(5)} -attr vt d
+load netBundle {ACC1:acc#681.itm} 6 {ACC1:acc#681.itm(0)} {ACC1:acc#681.itm(1)} {ACC1:acc#681.itm(2)} {ACC1:acc#681.itm(3)} {ACC1:acc#681.itm(4)} {ACC1:acc#681.itm(5)} -attr xrf 52080 -attr oid 136 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {conc#891.itm(0)} -attr vt d
+load net {conc#891.itm(1)} -attr vt d
+load net {conc#891.itm(2)} -attr vt d
+load net {conc#891.itm(3)} -attr vt d
+load net {conc#891.itm(4)} -attr vt d
+load netBundle {conc#891.itm} 5 {conc#891.itm(0)} {conc#891.itm(1)} {conc#891.itm(2)} {conc#891.itm(3)} {conc#891.itm(4)} -attr xrf 52081 -attr oid 137 -attr vt d -attr @path {/sobel/sobel:core/conc#891.itm}
+load net {ACC1:acc#677.itm(0)} -attr vt d
+load net {ACC1:acc#677.itm(1)} -attr vt d
+load net {ACC1:acc#677.itm(2)} -attr vt d
+load net {ACC1:acc#677.itm(3)} -attr vt d
+load netBundle {ACC1:acc#677.itm} 4 {ACC1:acc#677.itm(0)} {ACC1:acc#677.itm(1)} {ACC1:acc#677.itm(2)} {ACC1:acc#677.itm(3)} -attr xrf 52082 -attr oid 138 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:slc#154.itm(0)} -attr vt d
+load net {ACC1:slc#154.itm(1)} -attr vt d
+load net {ACC1:slc#154.itm(2)} -attr vt d
+load netBundle {ACC1:slc#154.itm} 3 {ACC1:slc#154.itm(0)} {ACC1:slc#154.itm(1)} {ACC1:slc#154.itm(2)} -attr xrf 52083 -attr oid 139 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#154.itm}
+load net {ACC1:acc#671.itm(0)} -attr vt d
+load net {ACC1:acc#671.itm(1)} -attr vt d
+load net {ACC1:acc#671.itm(2)} -attr vt d
+load net {ACC1:acc#671.itm(3)} -attr vt d
+load netBundle {ACC1:acc#671.itm} 4 {ACC1:acc#671.itm(0)} {ACC1:acc#671.itm(1)} {ACC1:acc#671.itm(2)} {ACC1:acc#671.itm(3)} -attr xrf 52084 -attr oid 140 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#671.itm}
+load net {exs#49.itm(0)} -attr vt d
+load net {exs#49.itm(1)} -attr vt d
+load net {exs#49.itm(2)} -attr vt d
+load netBundle {exs#49.itm} 3 {exs#49.itm(0)} {exs#49.itm(1)} {exs#49.itm(2)} -attr xrf 52085 -attr oid 141 -attr vt d -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {conc#892.itm(0)} -attr vt d
+load net {conc#892.itm(1)} -attr vt d
+load netBundle {conc#892.itm} 2 {conc#892.itm(0)} {conc#892.itm(1)} -attr xrf 52086 -attr oid 142 -attr vt d -attr @path {/sobel/sobel:core/conc#892.itm}
+load net {ACC1:exs#1482.itm(0)} -attr vt d
+load net {ACC1:exs#1482.itm(1)} -attr vt d
+load net {ACC1:exs#1482.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1482.itm} 3 {ACC1:exs#1482.itm(0)} {ACC1:exs#1482.itm(1)} {ACC1:exs#1482.itm(2)} -attr xrf 52087 -attr oid 143 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1482.itm}
+load net {ACC1:conc#1432.itm(0)} -attr vt d
+load net {ACC1:conc#1432.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1432.itm} 2 {ACC1:conc#1432.itm(0)} {ACC1:conc#1432.itm(1)} -attr xrf 52088 -attr oid 144 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1432.itm}
+load net {conc#893.itm(0)} -attr vt d
+load net {conc#893.itm(1)} -attr vt d
+load net {conc#893.itm(2)} -attr vt d
+load net {conc#893.itm(3)} -attr vt d
+load net {conc#893.itm(4)} -attr vt d
+load net {conc#893.itm(5)} -attr vt d
+load net {conc#893.itm(6)} -attr vt d
+load net {conc#893.itm(7)} -attr vt d
+load net {conc#893.itm(8)} -attr vt d
+load net {conc#893.itm(9)} -attr vt d
+load net {conc#893.itm(10)} -attr vt d
+load netBundle {conc#893.itm} 11 {conc#893.itm(0)} {conc#893.itm(1)} {conc#893.itm(2)} {conc#893.itm(3)} {conc#893.itm(4)} {conc#893.itm(5)} {conc#893.itm(6)} {conc#893.itm(7)} {conc#893.itm(8)} {conc#893.itm(9)} {conc#893.itm(10)} -attr xrf 52089 -attr oid 145 -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {ACC1:acc#718.itm(0)} -attr vt d
+load net {ACC1:acc#718.itm(1)} -attr vt d
+load net {ACC1:acc#718.itm(2)} -attr vt d
+load netBundle {ACC1:acc#718.itm} 3 {ACC1:acc#718.itm(0)} {ACC1:acc#718.itm(1)} {ACC1:acc#718.itm(2)} -attr xrf 52090 -attr oid 146 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#718.itm}
+load net {ACC1:exs#1640.itm(0)} -attr vt d
+load net {ACC1:exs#1640.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1640.itm} 2 {ACC1:exs#1640.itm(0)} {ACC1:exs#1640.itm(1)} -attr xrf 52091 -attr oid 147 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1640.itm}
+load net {ACC1-1:acc#27.itm(0)} -attr vt d
+load net {ACC1-1:acc#27.itm(1)} -attr vt d
+load net {ACC1-1:acc#27.itm(2)} -attr vt d
+load net {ACC1-1:acc#27.itm(3)} -attr vt d
+load net {ACC1-1:acc#27.itm(4)} -attr vt d
+load net {ACC1-1:acc#27.itm(5)} -attr vt d
+load net {ACC1-1:acc#27.itm(6)} -attr vt d
+load net {ACC1-1:acc#27.itm(7)} -attr vt d
+load net {ACC1-1:acc#27.itm(8)} -attr vt d
+load net {ACC1-1:acc#27.itm(9)} -attr vt d
+load net {ACC1-1:acc#27.itm(10)} -attr vt d
+load netBundle {ACC1-1:acc#27.itm} 11 {ACC1-1:acc#27.itm(0)} {ACC1-1:acc#27.itm(1)} {ACC1-1:acc#27.itm(2)} {ACC1-1:acc#27.itm(3)} {ACC1-1:acc#27.itm(4)} {ACC1-1:acc#27.itm(5)} {ACC1-1:acc#27.itm(6)} {ACC1-1:acc#27.itm(7)} {ACC1-1:acc#27.itm(8)} {ACC1-1:acc#27.itm(9)} {ACC1-1:acc#27.itm(10)} -attr xrf 52092 -attr oid 148 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1:acc#716.itm(0)} -attr vt d
+load net {ACC1:acc#716.itm(1)} -attr vt d
+load net {ACC1:acc#716.itm(2)} -attr vt d
+load net {ACC1:acc#716.itm(3)} -attr vt d
+load net {ACC1:acc#716.itm(4)} -attr vt d
+load net {ACC1:acc#716.itm(5)} -attr vt d
+load net {ACC1:acc#716.itm(6)} -attr vt d
+load net {ACC1:acc#716.itm(7)} -attr vt d
+load net {ACC1:acc#716.itm(8)} -attr vt d
+load net {ACC1:acc#716.itm(9)} -attr vt d
+load net {ACC1:acc#716.itm(10)} -attr vt d
+load netBundle {ACC1:acc#716.itm} 11 {ACC1:acc#716.itm(0)} {ACC1:acc#716.itm(1)} {ACC1:acc#716.itm(2)} {ACC1:acc#716.itm(3)} {ACC1:acc#716.itm(4)} {ACC1:acc#716.itm(5)} {ACC1:acc#716.itm(6)} {ACC1:acc#716.itm(7)} {ACC1:acc#716.itm(8)} {ACC1:acc#716.itm(9)} {ACC1:acc#716.itm(10)} -attr xrf 52093 -attr oid 149 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#714.itm(0)} -attr vt d
+load net {ACC1:acc#714.itm(1)} -attr vt d
+load net {ACC1:acc#714.itm(2)} -attr vt d
+load net {ACC1:acc#714.itm(3)} -attr vt d
+load net {ACC1:acc#714.itm(4)} -attr vt d
+load net {ACC1:acc#714.itm(5)} -attr vt d
+load net {ACC1:acc#714.itm(6)} -attr vt d
+load net {ACC1:acc#714.itm(7)} -attr vt d
+load net {ACC1:acc#714.itm(8)} -attr vt d
+load net {ACC1:acc#714.itm(9)} -attr vt d
+load netBundle {ACC1:acc#714.itm} 10 {ACC1:acc#714.itm(0)} {ACC1:acc#714.itm(1)} {ACC1:acc#714.itm(2)} {ACC1:acc#714.itm(3)} {ACC1:acc#714.itm(4)} {ACC1:acc#714.itm(5)} {ACC1:acc#714.itm(6)} {ACC1:acc#714.itm(7)} {ACC1:acc#714.itm(8)} {ACC1:acc#714.itm(9)} -attr xrf 52094 -attr oid 150 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {conc#894.itm(0)} -attr vt d
+load net {conc#894.itm(1)} -attr vt d
+load net {conc#894.itm(2)} -attr vt d
+load net {conc#894.itm(3)} -attr vt d
+load net {conc#894.itm(4)} -attr vt d
+load net {conc#894.itm(5)} -attr vt d
+load net {conc#894.itm(6)} -attr vt d
+load net {conc#894.itm(7)} -attr vt d
+load net {conc#894.itm(8)} -attr vt d
+load netBundle {conc#894.itm} 9 {conc#894.itm(0)} {conc#894.itm(1)} {conc#894.itm(2)} {conc#894.itm(3)} {conc#894.itm(4)} {conc#894.itm(5)} {conc#894.itm(6)} {conc#894.itm(7)} {conc#894.itm(8)} -attr xrf 52095 -attr oid 151 -attr vt d -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {ACC1:acc#712.itm(0)} -attr vt d
+load net {ACC1:acc#712.itm(1)} -attr vt d
+load net {ACC1:acc#712.itm(2)} -attr vt d
+load net {ACC1:acc#712.itm(3)} -attr vt d
+load net {ACC1:acc#712.itm(4)} -attr vt d
+load net {ACC1:acc#712.itm(5)} -attr vt d
+load net {ACC1:acc#712.itm(6)} -attr vt d
+load net {ACC1:acc#712.itm(7)} -attr vt d
+load netBundle {ACC1:acc#712.itm} 8 {ACC1:acc#712.itm(0)} {ACC1:acc#712.itm(1)} {ACC1:acc#712.itm(2)} {ACC1:acc#712.itm(3)} {ACC1:acc#712.itm(4)} {ACC1:acc#712.itm(5)} {ACC1:acc#712.itm(6)} {ACC1:acc#712.itm(7)} -attr xrf 52096 -attr oid 152 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {conc#895.itm(0)} -attr vt d
+load net {conc#895.itm(1)} -attr vt d
+load net {conc#895.itm(2)} -attr vt d
+load net {conc#895.itm(3)} -attr vt d
+load net {conc#895.itm(4)} -attr vt d
+load net {conc#895.itm(5)} -attr vt d
+load net {conc#895.itm(6)} -attr vt d
+load net {conc#895.itm(7)} -attr vt d
+load netBundle {conc#895.itm} 8 {conc#895.itm(0)} {conc#895.itm(1)} {conc#895.itm(2)} {conc#895.itm(3)} {conc#895.itm(4)} {conc#895.itm(5)} {conc#895.itm(6)} {conc#895.itm(7)} -attr xrf 52097 -attr oid 153 -attr vt d -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {ACC1-1:exs#1060.itm(0)} -attr vt d
+load net {ACC1-1:exs#1060.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1060.itm} 2 {ACC1-1:exs#1060.itm(0)} {ACC1-1:exs#1060.itm(1)} -attr xrf 52098 -attr oid 154 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1060.itm}
+load net {ACC1:acc#709.itm(0)} -attr vt d
+load net {ACC1:acc#709.itm(1)} -attr vt d
+load net {ACC1:acc#709.itm(2)} -attr vt d
+load net {ACC1:acc#709.itm(3)} -attr vt d
+load net {ACC1:acc#709.itm(4)} -attr vt d
+load net {ACC1:acc#709.itm(5)} -attr vt d
+load net {ACC1:acc#709.itm(6)} -attr vt d
+load netBundle {ACC1:acc#709.itm} 7 {ACC1:acc#709.itm(0)} {ACC1:acc#709.itm(1)} {ACC1:acc#709.itm(2)} {ACC1:acc#709.itm(3)} {ACC1:acc#709.itm(4)} {ACC1:acc#709.itm(5)} {ACC1:acc#709.itm(6)} -attr xrf 52099 -attr oid 155 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {conc#896.itm(0)} -attr vt d
+load net {conc#896.itm(1)} -attr vt d
+load net {conc#896.itm(2)} -attr vt d
+load net {conc#896.itm(3)} -attr vt d
+load net {conc#896.itm(4)} -attr vt d
+load net {conc#896.itm(5)} -attr vt d
+load netBundle {conc#896.itm} 6 {conc#896.itm(0)} {conc#896.itm(1)} {conc#896.itm(2)} {conc#896.itm(3)} {conc#896.itm(4)} {conc#896.itm(5)} -attr xrf 52100 -attr oid 156 -attr vt d -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {ACC1-1:exs#1063.itm(0)} -attr vt d
+load net {ACC1-1:exs#1063.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1063.itm} 2 {ACC1-1:exs#1063.itm(0)} {ACC1-1:exs#1063.itm(1)} -attr xrf 52101 -attr oid 157 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1063.itm}
+load net {ACC1:acc#706.itm(0)} -attr vt d
+load net {ACC1:acc#706.itm(1)} -attr vt d
+load net {ACC1:acc#706.itm(2)} -attr vt d
+load net {ACC1:acc#706.itm(3)} -attr vt d
+load net {ACC1:acc#706.itm(4)} -attr vt d
+load netBundle {ACC1:acc#706.itm} 5 {ACC1:acc#706.itm(0)} {ACC1:acc#706.itm(1)} {ACC1:acc#706.itm(2)} {ACC1:acc#706.itm(3)} {ACC1:acc#706.itm(4)} -attr xrf 52102 -attr oid 158 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#702.itm(0)} -attr vt d
+load net {ACC1:acc#702.itm(1)} -attr vt d
+load net {ACC1:acc#702.itm(2)} -attr vt d
+load net {ACC1:acc#702.itm(3)} -attr vt d
+load netBundle {ACC1:acc#702.itm} 4 {ACC1:acc#702.itm(0)} {ACC1:acc#702.itm(1)} {ACC1:acc#702.itm(2)} {ACC1:acc#702.itm(3)} -attr xrf 52103 -attr oid 159 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:slc#160.itm(0)} -attr vt d
+load net {ACC1:slc#160.itm(1)} -attr vt d
+load net {ACC1:slc#160.itm(2)} -attr vt d
+load netBundle {ACC1:slc#160.itm} 3 {ACC1:slc#160.itm(0)} {ACC1:slc#160.itm(1)} {ACC1:slc#160.itm(2)} -attr xrf 52104 -attr oid 160 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#160.itm}
+load net {ACC1:acc#696.itm(0)} -attr vt d
+load net {ACC1:acc#696.itm(1)} -attr vt d
+load net {ACC1:acc#696.itm(2)} -attr vt d
+load net {ACC1:acc#696.itm(3)} -attr vt d
+load netBundle {ACC1:acc#696.itm} 4 {ACC1:acc#696.itm(0)} {ACC1:acc#696.itm(1)} {ACC1:acc#696.itm(2)} {ACC1:acc#696.itm(3)} -attr xrf 52105 -attr oid 161 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#696.itm}
+load net {exs#50.itm(0)} -attr vt d
+load net {exs#50.itm(1)} -attr vt d
+load net {exs#50.itm(2)} -attr vt d
+load netBundle {exs#50.itm} 3 {exs#50.itm(0)} {exs#50.itm(1)} {exs#50.itm(2)} -attr xrf 52106 -attr oid 162 -attr vt d -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {conc#897.itm(0)} -attr vt d
+load net {conc#897.itm(1)} -attr vt d
+load netBundle {conc#897.itm} 2 {conc#897.itm(0)} {conc#897.itm(1)} -attr xrf 52107 -attr oid 163 -attr vt d -attr @path {/sobel/sobel:core/conc#897.itm}
+load net {ACC1:exs#1485.itm(0)} -attr vt d
+load net {ACC1:exs#1485.itm(1)} -attr vt d
+load net {ACC1:exs#1485.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1485.itm} 3 {ACC1:exs#1485.itm(0)} {ACC1:exs#1485.itm(1)} {ACC1:exs#1485.itm(2)} -attr xrf 52108 -attr oid 164 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1485.itm}
+load net {ACC1:conc#1445.itm(0)} -attr vt d
+load net {ACC1:conc#1445.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1445.itm} 2 {ACC1:conc#1445.itm(0)} {ACC1:conc#1445.itm(1)} -attr xrf 52109 -attr oid 165 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1445.itm}
+load net {ACC1:slc#159.itm(0)} -attr vt d
+load net {ACC1:slc#159.itm(1)} -attr vt d
+load net {ACC1:slc#159.itm(2)} -attr vt d
+load netBundle {ACC1:slc#159.itm} 3 {ACC1:slc#159.itm(0)} {ACC1:slc#159.itm(1)} {ACC1:slc#159.itm(2)} -attr xrf 52110 -attr oid 166 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#159.itm}
+load net {ACC1:acc#695.itm(0)} -attr vt d
+load net {ACC1:acc#695.itm(1)} -attr vt d
+load net {ACC1:acc#695.itm(2)} -attr vt d
+load net {ACC1:acc#695.itm(3)} -attr vt d
+load netBundle {ACC1:acc#695.itm} 4 {ACC1:acc#695.itm(0)} {ACC1:acc#695.itm(1)} {ACC1:acc#695.itm(2)} {ACC1:acc#695.itm(3)} -attr xrf 52111 -attr oid 167 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#695.itm}
+load net {exs#51.itm(0)} -attr vt d
+load net {exs#51.itm(1)} -attr vt d
+load net {exs#51.itm(2)} -attr vt d
+load netBundle {exs#51.itm} 3 {exs#51.itm(0)} {exs#51.itm(1)} {exs#51.itm(2)} -attr xrf 52112 -attr oid 168 -attr vt d -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {conc#898.itm(0)} -attr vt d
+load net {conc#898.itm(1)} -attr vt d
+load netBundle {conc#898.itm} 2 {conc#898.itm(0)} {conc#898.itm(1)} -attr xrf 52113 -attr oid 169 -attr vt d -attr @path {/sobel/sobel:core/conc#898.itm}
+load net {ACC1:exs#1487.itm(0)} -attr vt d
+load net {ACC1:exs#1487.itm(1)} -attr vt d
+load net {ACC1:exs#1487.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1487.itm} 3 {ACC1:exs#1487.itm(0)} {ACC1:exs#1487.itm(1)} {ACC1:exs#1487.itm(2)} -attr xrf 52114 -attr oid 170 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1487.itm}
+load net {ACC1:conc#1443.itm(0)} -attr vt d
+load net {ACC1:conc#1443.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1443.itm} 2 {ACC1:conc#1443.itm(0)} {ACC1:conc#1443.itm(1)} -attr xrf 52115 -attr oid 171 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1443.itm}
+load net {ACC1:acc#701.itm(0)} -attr vt d
+load net {ACC1:acc#701.itm(1)} -attr vt d
+load net {ACC1:acc#701.itm(2)} -attr vt d
+load net {ACC1:acc#701.itm(3)} -attr vt d
+load netBundle {ACC1:acc#701.itm} 4 {ACC1:acc#701.itm(0)} {ACC1:acc#701.itm(1)} {ACC1:acc#701.itm(2)} {ACC1:acc#701.itm(3)} -attr xrf 52116 -attr oid 172 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:slc#158.itm(0)} -attr vt d
+load net {ACC1:slc#158.itm(1)} -attr vt d
+load net {ACC1:slc#158.itm(2)} -attr vt d
+load netBundle {ACC1:slc#158.itm} 3 {ACC1:slc#158.itm(0)} {ACC1:slc#158.itm(1)} {ACC1:slc#158.itm(2)} -attr xrf 52117 -attr oid 173 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#158.itm}
+load net {ACC1:acc#694.itm(0)} -attr vt d
+load net {ACC1:acc#694.itm(1)} -attr vt d
+load net {ACC1:acc#694.itm(2)} -attr vt d
+load net {ACC1:acc#694.itm(3)} -attr vt d
+load netBundle {ACC1:acc#694.itm} 4 {ACC1:acc#694.itm(0)} {ACC1:acc#694.itm(1)} {ACC1:acc#694.itm(2)} {ACC1:acc#694.itm(3)} -attr xrf 52118 -attr oid 174 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#694.itm}
+load net {exs#52.itm(0)} -attr vt d
+load net {exs#52.itm(1)} -attr vt d
+load net {exs#52.itm(2)} -attr vt d
+load netBundle {exs#52.itm} 3 {exs#52.itm(0)} {exs#52.itm(1)} {exs#52.itm(2)} -attr xrf 52119 -attr oid 175 -attr vt d -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {conc#899.itm(0)} -attr vt d
+load net {conc#899.itm(1)} -attr vt d
+load netBundle {conc#899.itm} 2 {conc#899.itm(0)} {conc#899.itm(1)} -attr xrf 52120 -attr oid 176 -attr vt d -attr @path {/sobel/sobel:core/conc#899.itm}
+load net {ACC1:exs#1489.itm(0)} -attr vt d
+load net {ACC1:exs#1489.itm(1)} -attr vt d
+load net {ACC1:exs#1489.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1489.itm} 3 {ACC1:exs#1489.itm(0)} {ACC1:exs#1489.itm(1)} {ACC1:exs#1489.itm(2)} -attr xrf 52121 -attr oid 177 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1489.itm}
+load net {ACC1:conc#1441.itm(0)} -attr vt d
+load net {ACC1:conc#1441.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1441.itm} 2 {ACC1:conc#1441.itm(0)} {ACC1:conc#1441.itm(1)} -attr xrf 52122 -attr oid 178 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1441.itm}
+load net {ACC1:slc#157.itm(0)} -attr vt d
+load net {ACC1:slc#157.itm(1)} -attr vt d
+load net {ACC1:slc#157.itm(2)} -attr vt d
+load netBundle {ACC1:slc#157.itm} 3 {ACC1:slc#157.itm(0)} {ACC1:slc#157.itm(1)} {ACC1:slc#157.itm(2)} -attr xrf 52123 -attr oid 179 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#157.itm}
+load net {ACC1:acc#693.itm(0)} -attr vt d
+load net {ACC1:acc#693.itm(1)} -attr vt d
+load net {ACC1:acc#693.itm(2)} -attr vt d
+load net {ACC1:acc#693.itm(3)} -attr vt d
+load netBundle {ACC1:acc#693.itm} 4 {ACC1:acc#693.itm(0)} {ACC1:acc#693.itm(1)} {ACC1:acc#693.itm(2)} {ACC1:acc#693.itm(3)} -attr xrf 52124 -attr oid 180 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#693.itm}
+load net {exs#53.itm(0)} -attr vt d
+load net {exs#53.itm(1)} -attr vt d
+load net {exs#53.itm(2)} -attr vt d
+load netBundle {exs#53.itm} 3 {exs#53.itm(0)} {exs#53.itm(1)} {exs#53.itm(2)} -attr xrf 52125 -attr oid 181 -attr vt d -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {conc#900.itm(0)} -attr vt d
+load net {conc#900.itm(1)} -attr vt d
+load netBundle {conc#900.itm} 2 {conc#900.itm(0)} {conc#900.itm(1)} -attr xrf 52126 -attr oid 182 -attr vt d -attr @path {/sobel/sobel:core/conc#900.itm}
+load net {ACC1:exs#1491.itm(0)} -attr vt d
+load net {ACC1:exs#1491.itm(1)} -attr vt d
+load net {ACC1:exs#1491.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1491.itm} 3 {ACC1:exs#1491.itm(0)} {ACC1:exs#1491.itm(1)} {ACC1:exs#1491.itm(2)} -attr xrf 52127 -attr oid 183 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1491.itm}
+load net {ACC1:conc#1439.itm(0)} -attr vt d
+load net {ACC1:conc#1439.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1439.itm} 2 {ACC1:conc#1439.itm(0)} {ACC1:conc#1439.itm(1)} -attr xrf 52128 -attr oid 184 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1439.itm}
+load net {ACC1:acc#713.itm(0)} -attr vt d
+load net {ACC1:acc#713.itm(1)} -attr vt d
+load net {ACC1:acc#713.itm(2)} -attr vt d
+load net {ACC1:acc#713.itm(3)} -attr vt d
+load net {ACC1:acc#713.itm(4)} -attr vt d
+load net {ACC1:acc#713.itm(5)} -attr vt d
+load net {ACC1:acc#713.itm(6)} -attr vt d
+load net {ACC1:acc#713.itm(7)} -attr vt d
+load net {ACC1:acc#713.itm(8)} -attr vt d
+load net {ACC1:acc#713.itm(9)} -attr vt d
+load netBundle {ACC1:acc#713.itm} 10 {ACC1:acc#713.itm(0)} {ACC1:acc#713.itm(1)} {ACC1:acc#713.itm(2)} {ACC1:acc#713.itm(3)} {ACC1:acc#713.itm(4)} {ACC1:acc#713.itm(5)} {ACC1:acc#713.itm(6)} {ACC1:acc#713.itm(7)} {ACC1:acc#713.itm(8)} {ACC1:acc#713.itm(9)} -attr xrf 52129 -attr oid 185 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#711.itm(0)} -attr vt d
+load net {ACC1:acc#711.itm(1)} -attr vt d
+load net {ACC1:acc#711.itm(2)} -attr vt d
+load net {ACC1:acc#711.itm(3)} -attr vt d
+load net {ACC1:acc#711.itm(4)} -attr vt d
+load net {ACC1:acc#711.itm(5)} -attr vt d
+load net {ACC1:acc#711.itm(6)} -attr vt d
+load net {ACC1:acc#711.itm(7)} -attr vt d
+load netBundle {ACC1:acc#711.itm} 8 {ACC1:acc#711.itm(0)} {ACC1:acc#711.itm(1)} {ACC1:acc#711.itm(2)} {ACC1:acc#711.itm(3)} {ACC1:acc#711.itm(4)} {ACC1:acc#711.itm(5)} {ACC1:acc#711.itm(6)} {ACC1:acc#711.itm(7)} -attr xrf 52130 -attr oid 186 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#708.itm(0)} -attr vt d
+load net {ACC1:acc#708.itm(1)} -attr vt d
+load net {ACC1:acc#708.itm(2)} -attr vt d
+load net {ACC1:acc#708.itm(3)} -attr vt d
+load net {ACC1:acc#708.itm(4)} -attr vt d
+load net {ACC1:acc#708.itm(5)} -attr vt d
+load netBundle {ACC1:acc#708.itm} 6 {ACC1:acc#708.itm(0)} {ACC1:acc#708.itm(1)} {ACC1:acc#708.itm(2)} {ACC1:acc#708.itm(3)} {ACC1:acc#708.itm(4)} {ACC1:acc#708.itm(5)} -attr xrf 52131 -attr oid 187 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#705.itm(0)} -attr vt d
+load net {ACC1:acc#705.itm(1)} -attr vt d
+load net {ACC1:acc#705.itm(2)} -attr vt d
+load net {ACC1:acc#705.itm(3)} -attr vt d
+load netBundle {ACC1:acc#705.itm} 4 {ACC1:acc#705.itm(0)} {ACC1:acc#705.itm(1)} {ACC1:acc#705.itm(2)} {ACC1:acc#705.itm(3)} -attr xrf 52132 -attr oid 188 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#700.itm(0)} -attr vt d
+load net {ACC1:acc#700.itm(1)} -attr vt d
+load net {ACC1:acc#700.itm(2)} -attr vt d
+load netBundle {ACC1:acc#700.itm} 3 {ACC1:acc#700.itm(0)} {ACC1:acc#700.itm(1)} {ACC1:acc#700.itm(2)} -attr xrf 52133 -attr oid 189 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load net {ACC1:slc#155.itm(0)} -attr vt d
+load net {ACC1:slc#155.itm(1)} -attr vt d
+load net {ACC1:slc#155.itm(2)} -attr vt d
+load netBundle {ACC1:slc#155.itm} 3 {ACC1:slc#155.itm(0)} {ACC1:slc#155.itm(1)} {ACC1:slc#155.itm(2)} -attr xrf 52134 -attr oid 190 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#155.itm}
+load net {ACC1:acc#691.itm(0)} -attr vt d
+load net {ACC1:acc#691.itm(1)} -attr vt d
+load net {ACC1:acc#691.itm(2)} -attr vt d
+load net {ACC1:acc#691.itm(3)} -attr vt d
+load netBundle {ACC1:acc#691.itm} 4 {ACC1:acc#691.itm(0)} {ACC1:acc#691.itm(1)} {ACC1:acc#691.itm(2)} {ACC1:acc#691.itm(3)} -attr xrf 52135 -attr oid 191 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#691.itm}
+load net {conc#901.itm(0)} -attr vt d
+load net {conc#901.itm(1)} -attr vt d
+load net {conc#901.itm(2)} -attr vt d
+load netBundle {conc#901.itm} 3 {conc#901.itm(0)} {conc#901.itm(1)} {conc#901.itm(2)} -attr xrf 52136 -attr oid 192 -attr vt d -attr @path {/sobel/sobel:core/conc#901.itm}
+load net {ACC1:conc#1435.itm(0)} -attr vt d
+load net {ACC1:conc#1435.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1435.itm} 2 {ACC1:conc#1435.itm(0)} {ACC1:conc#1435.itm(1)} -attr xrf 52137 -attr oid 193 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1435.itm}
+load net {slc(ACC1:acc#223.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#223.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#223.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#223.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#223.psp#1.sva)#2.itm(1)} -attr xrf 52138 -attr oid 194 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp#1.sva)#2.itm}
+load net {ACC1:slc#156.itm(0)} -attr vt d
+load net {ACC1:slc#156.itm(1)} -attr vt d
+load net {ACC1:slc#156.itm(2)} -attr vt d
+load net {ACC1:slc#156.itm(3)} -attr vt d
+load netBundle {ACC1:slc#156.itm} 4 {ACC1:slc#156.itm(0)} {ACC1:slc#156.itm(1)} {ACC1:slc#156.itm(2)} {ACC1:slc#156.itm(3)} -attr xrf 52139 -attr oid 195 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#156.itm}
+load net {ACC1:acc#692.itm(0)} -attr vt d
+load net {ACC1:acc#692.itm(1)} -attr vt d
+load net {ACC1:acc#692.itm(2)} -attr vt d
+load net {ACC1:acc#692.itm(3)} -attr vt d
+load net {ACC1:acc#692.itm(4)} -attr vt d
+load netBundle {ACC1:acc#692.itm} 5 {ACC1:acc#692.itm(0)} {ACC1:acc#692.itm(1)} {ACC1:acc#692.itm(2)} {ACC1:acc#692.itm(3)} {ACC1:acc#692.itm(4)} -attr xrf 52140 -attr oid 196 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692.itm}
+load net {conc#902.itm(0)} -attr vt d
+load net {conc#902.itm(1)} -attr vt d
+load net {conc#902.itm(2)} -attr vt d
+load netBundle {conc#902.itm} 3 {conc#902.itm(0)} {conc#902.itm(1)} {conc#902.itm(2)} -attr xrf 52141 -attr oid 197 -attr vt d -attr @path {/sobel/sobel:core/conc#902.itm}
+load net {ACC1:conc#1437.itm(0)} -attr vt d
+load net {ACC1:conc#1437.itm(1)} -attr vt d
+load net {ACC1:conc#1437.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1437.itm} 3 {ACC1:conc#1437.itm(0)} {ACC1:conc#1437.itm(1)} {ACC1:conc#1437.itm(2)} -attr xrf 52142 -attr oid 198 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1437.itm}
+load net {ACC1:acc#704.itm(0)} -attr vt d
+load net {ACC1:acc#704.itm(1)} -attr vt d
+load net {ACC1:acc#704.itm(2)} -attr vt d
+load net {ACC1:acc#704.itm(3)} -attr vt d
+load net {ACC1:acc#704.itm(4)} -attr vt d
+load netBundle {ACC1:acc#704.itm} 5 {ACC1:acc#704.itm(0)} {ACC1:acc#704.itm(1)} {ACC1:acc#704.itm(2)} {ACC1:acc#704.itm(3)} {ACC1:acc#704.itm(4)} -attr xrf 52143 -attr oid 199 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1-1:conc#594.itm(0)} -attr vt d
+load net {ACC1-1:conc#594.itm(1)} -attr vt d
+load net {ACC1-1:conc#594.itm(2)} -attr vt d
+load net {ACC1-1:conc#594.itm(3)} -attr vt d
+load netBundle {ACC1-1:conc#594.itm} 4 {ACC1-1:conc#594.itm(0)} {ACC1-1:conc#594.itm(1)} {ACC1-1:conc#594.itm(2)} {ACC1-1:conc#594.itm(3)} -attr xrf 52144 -attr oid 200 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#594.itm}
+load net {ACC1-1:exs#1054.itm(0)} -attr vt d
+load net {ACC1-1:exs#1054.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1054.itm} 2 {ACC1-1:exs#1054.itm(0)} {ACC1-1:exs#1054.itm(1)} -attr xrf 52145 -attr oid 201 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1054.itm}
+load net {conc#903.itm(0)} -attr vt d
+load net {conc#903.itm(1)} -attr vt d
+load net {conc#903.itm(2)} -attr vt d
+load net {conc#903.itm(3)} -attr vt d
+load net {conc#903.itm(4)} -attr vt d
+load net {conc#903.itm(5)} -attr vt d
+load net {conc#903.itm(6)} -attr vt d
+load netBundle {conc#903.itm} 7 {conc#903.itm(0)} {conc#903.itm(1)} {conc#903.itm(2)} {conc#903.itm(3)} {conc#903.itm(4)} {conc#903.itm(5)} {conc#903.itm(6)} -attr xrf 52146 -attr oid 202 -attr vt d -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {ACC1:acc#710.itm(0)} -attr vt d
+load net {ACC1:acc#710.itm(1)} -attr vt d
+load net {ACC1:acc#710.itm(2)} -attr vt d
+load net {ACC1:acc#710.itm(3)} -attr vt d
+load net {ACC1:acc#710.itm(4)} -attr vt d
+load net {ACC1:acc#710.itm(5)} -attr vt d
+load net {ACC1:acc#710.itm(6)} -attr vt d
+load net {ACC1:acc#710.itm(7)} -attr vt d
+load netBundle {ACC1:acc#710.itm} 8 {ACC1:acc#710.itm(0)} {ACC1:acc#710.itm(1)} {ACC1:acc#710.itm(2)} {ACC1:acc#710.itm(3)} {ACC1:acc#710.itm(4)} {ACC1:acc#710.itm(5)} {ACC1:acc#710.itm(6)} {ACC1:acc#710.itm(7)} -attr xrf 52147 -attr oid 203 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1-1:exs#1040.itm(0)} -attr vt d
+load net {ACC1-1:exs#1040.itm(1)} -attr vt d
+load net {ACC1-1:exs#1040.itm(2)} -attr vt d
+load net {ACC1-1:exs#1040.itm(3)} -attr vt d
+load net {ACC1-1:exs#1040.itm(4)} -attr vt d
+load net {ACC1-1:exs#1040.itm(5)} -attr vt d
+load net {ACC1-1:exs#1040.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#1040.itm} 7 {ACC1-1:exs#1040.itm(0)} {ACC1-1:exs#1040.itm(1)} {ACC1-1:exs#1040.itm(2)} {ACC1-1:exs#1040.itm(3)} {ACC1-1:exs#1040.itm(4)} {ACC1-1:exs#1040.itm(5)} {ACC1-1:exs#1040.itm(6)} -attr xrf 52148 -attr oid 204 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {ACC1-1:conc#538.itm(0)} -attr vt d
+load net {ACC1-1:conc#538.itm(1)} -attr vt d
+load net {ACC1-1:conc#538.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#538.itm} 3 {ACC1-1:conc#538.itm(0)} {ACC1-1:conc#538.itm(1)} {ACC1-1:conc#538.itm(2)} -attr xrf 52149 -attr oid 205 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#538.itm}
+load net {ACC1-1:exs#1047.itm(0)} -attr vt d
+load net {ACC1-1:exs#1047.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1047.itm} 2 {ACC1-1:exs#1047.itm(0)} {ACC1-1:exs#1047.itm(1)} -attr xrf 52150 -attr oid 206 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1047.itm}
+load net {ACC1:acc#707.itm(0)} -attr vt d
+load net {ACC1:acc#707.itm(1)} -attr vt d
+load net {ACC1:acc#707.itm(2)} -attr vt d
+load net {ACC1:acc#707.itm(3)} -attr vt d
+load net {ACC1:acc#707.itm(4)} -attr vt d
+load net {ACC1:acc#707.itm(5)} -attr vt d
+load netBundle {ACC1:acc#707.itm} 6 {ACC1:acc#707.itm(0)} {ACC1:acc#707.itm(1)} {ACC1:acc#707.itm(2)} {ACC1:acc#707.itm(3)} {ACC1:acc#707.itm(4)} {ACC1:acc#707.itm(5)} -attr xrf 52151 -attr oid 207 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {conc#904.itm(0)} -attr vt d
+load net {conc#904.itm(1)} -attr vt d
+load net {conc#904.itm(2)} -attr vt d
+load net {conc#904.itm(3)} -attr vt d
+load net {conc#904.itm(4)} -attr vt d
+load netBundle {conc#904.itm} 5 {conc#904.itm(0)} {conc#904.itm(1)} {conc#904.itm(2)} {conc#904.itm(3)} {conc#904.itm(4)} -attr xrf 52152 -attr oid 208 -attr vt d -attr @path {/sobel/sobel:core/conc#904.itm}
+load net {ACC1:acc#703.itm(0)} -attr vt d
+load net {ACC1:acc#703.itm(1)} -attr vt d
+load net {ACC1:acc#703.itm(2)} -attr vt d
+load net {ACC1:acc#703.itm(3)} -attr vt d
+load netBundle {ACC1:acc#703.itm} 4 {ACC1:acc#703.itm(0)} {ACC1:acc#703.itm(1)} {ACC1:acc#703.itm(2)} {ACC1:acc#703.itm(3)} -attr xrf 52153 -attr oid 209 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:slc#161.itm(0)} -attr vt d
+load net {ACC1:slc#161.itm(1)} -attr vt d
+load net {ACC1:slc#161.itm(2)} -attr vt d
+load netBundle {ACC1:slc#161.itm} 3 {ACC1:slc#161.itm(0)} {ACC1:slc#161.itm(1)} {ACC1:slc#161.itm(2)} -attr xrf 52154 -attr oid 210 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#161.itm}
+load net {ACC1:acc#697.itm(0)} -attr vt d
+load net {ACC1:acc#697.itm(1)} -attr vt d
+load net {ACC1:acc#697.itm(2)} -attr vt d
+load net {ACC1:acc#697.itm(3)} -attr vt d
+load netBundle {ACC1:acc#697.itm} 4 {ACC1:acc#697.itm(0)} {ACC1:acc#697.itm(1)} {ACC1:acc#697.itm(2)} {ACC1:acc#697.itm(3)} -attr xrf 52155 -attr oid 211 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#697.itm}
+load net {exs#91.itm(0)} -attr vt d
+load net {exs#91.itm(1)} -attr vt d
+load net {exs#91.itm(2)} -attr vt d
+load netBundle {exs#91.itm} 3 {exs#91.itm(0)} {exs#91.itm(1)} {exs#91.itm(2)} -attr xrf 52156 -attr oid 212 -attr vt d -attr @path {/sobel/sobel:core/exs#91.itm}
+load net {conc#905.itm(0)} -attr vt d
+load net {conc#905.itm(1)} -attr vt d
+load netBundle {conc#905.itm} 2 {conc#905.itm(0)} {conc#905.itm(1)} -attr xrf 52157 -attr oid 213 -attr vt d -attr @path {/sobel/sobel:core/conc#905.itm}
+load net {ACC1:exs#1493.itm(0)} -attr vt d
+load net {ACC1:exs#1493.itm(1)} -attr vt d
+load net {ACC1:exs#1493.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1493.itm} 3 {ACC1:exs#1493.itm(0)} {ACC1:exs#1493.itm(1)} {ACC1:exs#1493.itm(2)} -attr xrf 52158 -attr oid 214 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1493.itm}
+load net {ACC1:conc#1447.itm(0)} -attr vt d
+load net {ACC1:conc#1447.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1447.itm} 2 {ACC1:conc#1447.itm(0)} {ACC1:conc#1447.itm(1)} -attr xrf 52159 -attr oid 215 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1447.itm}
+load net {conc#907.itm(0)} -attr vt d
+load net {conc#907.itm(1)} -attr vt d
+load net {conc#907.itm(2)} -attr vt d
+load net {conc#907.itm(3)} -attr vt d
+load net {conc#907.itm(4)} -attr vt d
+load net {conc#907.itm(5)} -attr vt d
+load net {conc#907.itm(6)} -attr vt d
+load net {conc#907.itm(7)} -attr vt d
+load net {conc#907.itm(8)} -attr vt d
+load net {conc#907.itm(9)} -attr vt d
+load net {conc#907.itm(10)} -attr vt d
+load netBundle {conc#907.itm} 11 {conc#907.itm(0)} {conc#907.itm(1)} {conc#907.itm(2)} {conc#907.itm(3)} {conc#907.itm(4)} {conc#907.itm(5)} {conc#907.itm(6)} {conc#907.itm(7)} {conc#907.itm(8)} {conc#907.itm(9)} {conc#907.itm(10)} -attr xrf 52160 -attr oid 216 -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {ACC1:acc#720.itm(0)} -attr vt d
+load net {ACC1:acc#720.itm(1)} -attr vt d
+load net {ACC1:acc#720.itm(2)} -attr vt d
+load netBundle {ACC1:acc#720.itm} 3 {ACC1:acc#720.itm(0)} {ACC1:acc#720.itm(1)} {ACC1:acc#720.itm(2)} -attr xrf 52161 -attr oid 217 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#720.itm}
+load net {ACC1:exs#1654.itm(0)} -attr vt d
+load net {ACC1:exs#1654.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1654.itm} 2 {ACC1:exs#1654.itm(0)} {ACC1:exs#1654.itm(1)} -attr xrf 52162 -attr oid 218 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1654.itm}
+load net {ACC1:acc#658.itm(0)} -attr vt d
+load net {ACC1:acc#658.itm(1)} -attr vt d
+load net {ACC1:acc#658.itm(2)} -attr vt d
+load net {ACC1:acc#658.itm(3)} -attr vt d
+load net {ACC1:acc#658.itm(4)} -attr vt d
+load net {ACC1:acc#658.itm(5)} -attr vt d
+load net {ACC1:acc#658.itm(6)} -attr vt d
+load net {ACC1:acc#658.itm(7)} -attr vt d
+load net {ACC1:acc#658.itm(8)} -attr vt d
+load net {ACC1:acc#658.itm(9)} -attr vt d
+load net {ACC1:acc#658.itm(10)} -attr vt d
+load net {ACC1:acc#658.itm(11)} -attr vt d
+load net {ACC1:acc#658.itm(12)} -attr vt d
+load netBundle {ACC1:acc#658.itm} 13 {ACC1:acc#658.itm(0)} {ACC1:acc#658.itm(1)} {ACC1:acc#658.itm(2)} {ACC1:acc#658.itm(3)} {ACC1:acc#658.itm(4)} {ACC1:acc#658.itm(5)} {ACC1:acc#658.itm(6)} {ACC1:acc#658.itm(7)} {ACC1:acc#658.itm(8)} {ACC1:acc#658.itm(9)} {ACC1:acc#658.itm(10)} {ACC1:acc#658.itm(11)} {ACC1:acc#658.itm(12)} -attr xrf 52163 -attr oid 219 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#651.itm(0)} -attr vt d
+load net {ACC1:acc#651.itm(1)} -attr vt d
+load net {ACC1:acc#651.itm(2)} -attr vt d
+load net {ACC1:acc#651.itm(3)} -attr vt d
+load net {ACC1:acc#651.itm(4)} -attr vt d
+load net {ACC1:acc#651.itm(5)} -attr vt d
+load net {ACC1:acc#651.itm(6)} -attr vt d
+load net {ACC1:acc#651.itm(7)} -attr vt d
+load net {ACC1:acc#651.itm(8)} -attr vt d
+load net {ACC1:acc#651.itm(9)} -attr vt d
+load net {ACC1:acc#651.itm(10)} -attr vt d
+load net {ACC1:acc#651.itm(11)} -attr vt d
+load netBundle {ACC1:acc#651.itm} 12 {ACC1:acc#651.itm(0)} {ACC1:acc#651.itm(1)} {ACC1:acc#651.itm(2)} {ACC1:acc#651.itm(3)} {ACC1:acc#651.itm(4)} {ACC1:acc#651.itm(5)} {ACC1:acc#651.itm(6)} {ACC1:acc#651.itm(7)} {ACC1:acc#651.itm(8)} {ACC1:acc#651.itm(9)} {ACC1:acc#651.itm(10)} {ACC1:acc#651.itm(11)} -attr xrf 52164 -attr oid 220 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#646.itm(0)} -attr vt d
+load net {ACC1:acc#646.itm(1)} -attr vt d
+load net {ACC1:acc#646.itm(2)} -attr vt d
+load net {ACC1:acc#646.itm(3)} -attr vt d
+load net {ACC1:acc#646.itm(4)} -attr vt d
+load net {ACC1:acc#646.itm(5)} -attr vt d
+load net {ACC1:acc#646.itm(6)} -attr vt d
+load net {ACC1:acc#646.itm(7)} -attr vt d
+load net {ACC1:acc#646.itm(8)} -attr vt d
+load net {ACC1:acc#646.itm(9)} -attr vt d
+load netBundle {ACC1:acc#646.itm} 10 {ACC1:acc#646.itm(0)} {ACC1:acc#646.itm(1)} {ACC1:acc#646.itm(2)} {ACC1:acc#646.itm(3)} {ACC1:acc#646.itm(4)} {ACC1:acc#646.itm(5)} {ACC1:acc#646.itm(6)} {ACC1:acc#646.itm(7)} {ACC1:acc#646.itm(8)} {ACC1:acc#646.itm(9)} -attr xrf 52165 -attr oid 221 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#635.itm(0)} -attr vt d
+load net {ACC1:acc#635.itm(1)} -attr vt d
+load net {ACC1:acc#635.itm(2)} -attr vt d
+load net {ACC1:acc#635.itm(3)} -attr vt d
+load net {ACC1:acc#635.itm(4)} -attr vt d
+load net {ACC1:acc#635.itm(5)} -attr vt d
+load net {ACC1:acc#635.itm(6)} -attr vt d
+load net {ACC1:acc#635.itm(7)} -attr vt d
+load net {ACC1:acc#635.itm(8)} -attr vt d
+load netBundle {ACC1:acc#635.itm} 9 {ACC1:acc#635.itm(0)} {ACC1:acc#635.itm(1)} {ACC1:acc#635.itm(2)} {ACC1:acc#635.itm(3)} {ACC1:acc#635.itm(4)} {ACC1:acc#635.itm(5)} {ACC1:acc#635.itm(6)} {ACC1:acc#635.itm(7)} {ACC1:acc#635.itm(8)} -attr xrf 52166 -attr oid 222 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#620.itm(0)} -attr vt d
+load net {ACC1:acc#620.itm(1)} -attr vt d
+load net {ACC1:acc#620.itm(2)} -attr vt d
+load net {ACC1:acc#620.itm(3)} -attr vt d
+load net {ACC1:acc#620.itm(4)} -attr vt d
+load net {ACC1:acc#620.itm(5)} -attr vt d
+load net {ACC1:acc#620.itm(6)} -attr vt d
+load netBundle {ACC1:acc#620.itm} 7 {ACC1:acc#620.itm(0)} {ACC1:acc#620.itm(1)} {ACC1:acc#620.itm(2)} {ACC1:acc#620.itm(3)} {ACC1:acc#620.itm(4)} {ACC1:acc#620.itm(5)} {ACC1:acc#620.itm(6)} -attr xrf 52167 -attr oid 223 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#601.itm(0)} -attr vt d
+load net {ACC1:acc#601.itm(1)} -attr vt d
+load net {ACC1:acc#601.itm(2)} -attr vt d
+load net {ACC1:acc#601.itm(3)} -attr vt d
+load net {ACC1:acc#601.itm(4)} -attr vt d
+load net {ACC1:acc#601.itm(5)} -attr vt d
+load netBundle {ACC1:acc#601.itm} 6 {ACC1:acc#601.itm(0)} {ACC1:acc#601.itm(1)} {ACC1:acc#601.itm(2)} {ACC1:acc#601.itm(3)} {ACC1:acc#601.itm(4)} {ACC1:acc#601.itm(5)} -attr xrf 52168 -attr oid 224 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#572.itm(0)} -attr vt d
+load net {ACC1:acc#572.itm(1)} -attr vt d
+load net {ACC1:acc#572.itm(2)} -attr vt d
+load net {ACC1:acc#572.itm(3)} -attr vt d
+load net {ACC1:acc#572.itm(4)} -attr vt d
+load netBundle {ACC1:acc#572.itm} 5 {ACC1:acc#572.itm(0)} {ACC1:acc#572.itm(1)} {ACC1:acc#572.itm(2)} {ACC1:acc#572.itm(3)} {ACC1:acc#572.itm(4)} -attr xrf 52169 -attr oid 225 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:conc#1108.itm(0)} -attr vt d
+load net {ACC1:conc#1108.itm(1)} -attr vt d
+load net {ACC1:conc#1108.itm(2)} -attr vt d
+load net {ACC1:conc#1108.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1108.itm} 4 {ACC1:conc#1108.itm(0)} {ACC1:conc#1108.itm(1)} {ACC1:conc#1108.itm(2)} {ACC1:conc#1108.itm(3)} -attr xrf 52170 -attr oid 226 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1108.itm}
+load net {ACC1-3:exs#1063.itm(0)} -attr vt d
+load net {ACC1-3:exs#1063.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1063.itm} 2 {ACC1-3:exs#1063.itm(0)} {ACC1-3:exs#1063.itm(1)} -attr xrf 52171 -attr oid 227 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1063.itm}
+load net {ACC1:conc#1109.itm(0)} -attr vt d
+load net {ACC1:conc#1109.itm(1)} -attr vt d
+load net {ACC1:conc#1109.itm(2)} -attr vt d
+load net {ACC1:conc#1109.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1109.itm} 4 {ACC1:conc#1109.itm(0)} {ACC1:conc#1109.itm(1)} {ACC1:conc#1109.itm(2)} {ACC1:conc#1109.itm(3)} -attr xrf 52172 -attr oid 228 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1109.itm}
+load net {ACC1-2:exs#1053.itm(0)} -attr vt d
+load net {ACC1-2:exs#1053.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1053.itm} 2 {ACC1-2:exs#1053.itm(0)} {ACC1-2:exs#1053.itm(1)} -attr xrf 52173 -attr oid 229 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1053.itm}
+load net {ACC1:acc#571.itm(0)} -attr vt d
+load net {ACC1:acc#571.itm(1)} -attr vt d
+load net {ACC1:acc#571.itm(2)} -attr vt d
+load net {ACC1:acc#571.itm(3)} -attr vt d
+load net {ACC1:acc#571.itm(4)} -attr vt d
+load netBundle {ACC1:acc#571.itm} 5 {ACC1:acc#571.itm(0)} {ACC1:acc#571.itm(1)} {ACC1:acc#571.itm(2)} {ACC1:acc#571.itm(3)} {ACC1:acc#571.itm(4)} -attr xrf 52174 -attr oid 230 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:conc#1110.itm(0)} -attr vt d
+load net {ACC1:conc#1110.itm(1)} -attr vt d
+load net {ACC1:conc#1110.itm(2)} -attr vt d
+load net {ACC1:conc#1110.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1110.itm} 4 {ACC1:conc#1110.itm(0)} {ACC1:conc#1110.itm(1)} {ACC1:conc#1110.itm(2)} {ACC1:conc#1110.itm(3)} -attr xrf 52175 -attr oid 231 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1110.itm}
+load net {ACC1-2:exs#1054.itm(0)} -attr vt d
+load net {ACC1-2:exs#1054.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1054.itm} 2 {ACC1-2:exs#1054.itm(0)} {ACC1-2:exs#1054.itm(1)} -attr xrf 52176 -attr oid 232 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1054.itm}
+load net {ACC1:conc#1111.itm(0)} -attr vt d
+load net {ACC1:conc#1111.itm(1)} -attr vt d
+load net {ACC1:conc#1111.itm(2)} -attr vt d
+load net {ACC1:conc#1111.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1111.itm} 4 {ACC1:conc#1111.itm(0)} {ACC1:conc#1111.itm(1)} {ACC1:conc#1111.itm(2)} {ACC1:conc#1111.itm(3)} -attr xrf 52177 -attr oid 233 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1111.itm}
+load net {ACC1-2:exs#1055.itm(0)} -attr vt d
+load net {ACC1-2:exs#1055.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1055.itm} 2 {ACC1-2:exs#1055.itm(0)} {ACC1-2:exs#1055.itm(1)} -attr xrf 52178 -attr oid 234 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1055.itm}
+load net {ACC1:acc#600.itm(0)} -attr vt d
+load net {ACC1:acc#600.itm(1)} -attr vt d
+load net {ACC1:acc#600.itm(2)} -attr vt d
+load net {ACC1:acc#600.itm(3)} -attr vt d
+load net {ACC1:acc#600.itm(4)} -attr vt d
+load net {ACC1:acc#600.itm(5)} -attr vt d
+load netBundle {ACC1:acc#600.itm} 6 {ACC1:acc#600.itm(0)} {ACC1:acc#600.itm(1)} {ACC1:acc#600.itm(2)} {ACC1:acc#600.itm(3)} {ACC1:acc#600.itm(4)} {ACC1:acc#600.itm(5)} -attr xrf 52179 -attr oid 235 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#570.itm(0)} -attr vt d
+load net {ACC1:acc#570.itm(1)} -attr vt d
+load net {ACC1:acc#570.itm(2)} -attr vt d
+load net {ACC1:acc#570.itm(3)} -attr vt d
+load net {ACC1:acc#570.itm(4)} -attr vt d
+load netBundle {ACC1:acc#570.itm} 5 {ACC1:acc#570.itm(0)} {ACC1:acc#570.itm(1)} {ACC1:acc#570.itm(2)} {ACC1:acc#570.itm(3)} {ACC1:acc#570.itm(4)} -attr xrf 52180 -attr oid 236 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {conc#908.itm(0)} -attr vt d
+load net {conc#908.itm(1)} -attr vt d
+load net {conc#908.itm(2)} -attr vt d
+load net {conc#908.itm(3)} -attr vt d
+load netBundle {conc#908.itm} 4 {conc#908.itm(0)} {conc#908.itm(1)} {conc#908.itm(2)} {conc#908.itm(3)} -attr xrf 52181 -attr oid 237 -attr vt d -attr @path {/sobel/sobel:core/conc#908.itm}
+load net {ACC1:conc#1113.itm(0)} -attr vt d
+load net {ACC1:conc#1113.itm(1)} -attr vt d
+load net {ACC1:conc#1113.itm(2)} -attr vt d
+load net {ACC1:conc#1113.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1113.itm} 4 {ACC1:conc#1113.itm(0)} {ACC1:conc#1113.itm(1)} {ACC1:conc#1113.itm(2)} {ACC1:conc#1113.itm(3)} -attr xrf 52182 -attr oid 238 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1113.itm}
+load net {ACC1-2:exs#1045.itm(0)} -attr vt d
+load net {ACC1-2:exs#1045.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1045.itm} 2 {ACC1-2:exs#1045.itm(0)} {ACC1-2:exs#1045.itm(1)} -attr xrf 52183 -attr oid 239 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1045.itm}
+load net {ACC1:acc#524.itm(0)} -attr vt d
+load net {ACC1:acc#524.itm(1)} -attr vt d
+load net {ACC1:acc#524.itm(2)} -attr vt d
+load net {ACC1:acc#524.itm(3)} -attr vt d
+load net {ACC1:acc#524.itm(4)} -attr vt d
+load netBundle {ACC1:acc#524.itm} 5 {ACC1:acc#524.itm(0)} {ACC1:acc#524.itm(1)} {ACC1:acc#524.itm(2)} {ACC1:acc#524.itm(3)} {ACC1:acc#524.itm(4)} -attr xrf 52184 -attr oid 240 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:slc#93.itm(0)} -attr vt d
+load net {ACC1:slc#93.itm(1)} -attr vt d
+load net {ACC1:slc#93.itm(2)} -attr vt d
+load netBundle {ACC1:slc#93.itm} 3 {ACC1:slc#93.itm(0)} {ACC1:slc#93.itm(1)} {ACC1:slc#93.itm(2)} -attr xrf 52185 -attr oid 241 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#425.itm(0)} -attr vt d
+load net {ACC1:acc#425.itm(1)} -attr vt d
+load net {ACC1:acc#425.itm(2)} -attr vt d
+load net {ACC1:acc#425.itm(3)} -attr vt d
+load netBundle {ACC1:acc#425.itm} 4 {ACC1:acc#425.itm(0)} {ACC1:acc#425.itm(1)} {ACC1:acc#425.itm(2)} {ACC1:acc#425.itm(3)} -attr xrf 52186 -attr oid 242 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#425.itm}
+load net {conc#909.itm(0)} -attr vt d
+load net {conc#909.itm(1)} -attr vt d
+load net {conc#909.itm(2)} -attr vt d
+load netBundle {conc#909.itm} 3 {conc#909.itm(0)} {conc#909.itm(1)} {conc#909.itm(2)} -attr xrf 52187 -attr oid 243 -attr vt d -attr @path {/sobel/sobel:core/conc#909.itm}
+load net {ACC1:conc#1309.itm(0)} -attr vt d
+load net {ACC1:conc#1309.itm(1)} -attr vt d
+load net {ACC1:conc#1309.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1309.itm} 3 {ACC1:conc#1309.itm(0)} {ACC1:conc#1309.itm(1)} {ACC1:conc#1309.itm(2)} -attr xrf 52188 -attr oid 244 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1309.itm}
+load net {ACC1:conc#1097.itm(0)} -attr vt d
+load net {ACC1:conc#1097.itm(1)} -attr vt d
+load net {ACC1:conc#1097.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1097.itm} 3 {ACC1:conc#1097.itm(0)} {ACC1:conc#1097.itm(1)} {ACC1:conc#1097.itm(2)} -attr xrf 52189 -attr oid 245 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1097.itm}
+load net {slc(ACC1:acc#223.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#223.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#223.psp.sva)#2.itm} 2 {slc(ACC1:acc#223.psp.sva)#2.itm(0)} {slc(ACC1:acc#223.psp.sva)#2.itm(1)} -attr xrf 52190 -attr oid 246 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp.sva)#2.itm}
+load net {ACC1:acc#619.itm(0)} -attr vt d
+load net {ACC1:acc#619.itm(1)} -attr vt d
+load net {ACC1:acc#619.itm(2)} -attr vt d
+load net {ACC1:acc#619.itm(3)} -attr vt d
+load net {ACC1:acc#619.itm(4)} -attr vt d
+load net {ACC1:acc#619.itm(5)} -attr vt d
+load net {ACC1:acc#619.itm(6)} -attr vt d
+load netBundle {ACC1:acc#619.itm} 7 {ACC1:acc#619.itm(0)} {ACC1:acc#619.itm(1)} {ACC1:acc#619.itm(2)} {ACC1:acc#619.itm(3)} {ACC1:acc#619.itm(4)} {ACC1:acc#619.itm(5)} {ACC1:acc#619.itm(6)} -attr xrf 52191 -attr oid 247 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#573.itm(0)} -attr vt d
+load net {ACC1:acc#573.itm(1)} -attr vt d
+load net {ACC1:acc#573.itm(2)} -attr vt d
+load net {ACC1:acc#573.itm(3)} -attr vt d
+load net {ACC1:acc#573.itm(4)} -attr vt d
+load net {ACC1:acc#573.itm(5)} -attr vt d
+load netBundle {ACC1:acc#573.itm} 6 {ACC1:acc#573.itm(0)} {ACC1:acc#573.itm(1)} {ACC1:acc#573.itm(2)} {ACC1:acc#573.itm(3)} {ACC1:acc#573.itm(4)} {ACC1:acc#573.itm(5)} -attr xrf 52192 -attr oid 248 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:slc#111.itm(0)} -attr vt d
+load net {ACC1:slc#111.itm(1)} -attr vt d
+load net {ACC1:slc#111.itm(2)} -attr vt d
+load net {ACC1:slc#111.itm(3)} -attr vt d
+load netBundle {ACC1:slc#111.itm} 4 {ACC1:slc#111.itm(0)} {ACC1:slc#111.itm(1)} {ACC1:slc#111.itm(2)} {ACC1:slc#111.itm(3)} -attr xrf 52193 -attr oid 249 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#111.itm}
+load net {ACC1:acc#443.itm(0)} -attr vt d
+load net {ACC1:acc#443.itm(1)} -attr vt d
+load net {ACC1:acc#443.itm(2)} -attr vt d
+load net {ACC1:acc#443.itm(3)} -attr vt d
+load net {ACC1:acc#443.itm(4)} -attr vt d
+load netBundle {ACC1:acc#443.itm} 5 {ACC1:acc#443.itm(0)} {ACC1:acc#443.itm(1)} {ACC1:acc#443.itm(2)} {ACC1:acc#443.itm(3)} {ACC1:acc#443.itm(4)} -attr xrf 52194 -attr oid 250 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443.itm}
+load net {exs#54.itm(0)} -attr vt d
+load net {exs#54.itm(1)} -attr vt d
+load net {exs#54.itm(2)} -attr vt d
+load netBundle {exs#54.itm} 3 {exs#54.itm(0)} {exs#54.itm(1)} {exs#54.itm(2)} -attr xrf 52195 -attr oid 251 -attr vt d -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {conc#910.itm(0)} -attr vt d
+load net {conc#910.itm(1)} -attr vt d
+load netBundle {conc#910.itm} 2 {conc#910.itm(0)} {conc#910.itm(1)} -attr xrf 52196 -attr oid 252 -attr vt d -attr @path {/sobel/sobel:core/conc#910.itm}
+load net {ACC1:conc#1345.itm(0)} -attr vt d
+load net {ACC1:conc#1345.itm(1)} -attr vt d
+load net {ACC1:conc#1345.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1345.itm} 3 {ACC1:conc#1345.itm(0)} {ACC1:conc#1345.itm(1)} {ACC1:conc#1345.itm(2)} -attr xrf 52197 -attr oid 253 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1345.itm}
+load net {slc(ACC1:acc#220.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#220.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#220.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#220.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#220.psp#1.sva)#2.itm(1)} -attr xrf 52198 -attr oid 254 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva)#2.itm}
+load net {ACC1:conc#1107.itm(0)} -attr vt d
+load net {ACC1:conc#1107.itm(1)} -attr vt d
+load net {ACC1:conc#1107.itm(2)} -attr vt d
+load net {ACC1:conc#1107.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1107.itm} 4 {ACC1:conc#1107.itm(0)} {ACC1:conc#1107.itm(1)} {ACC1:conc#1107.itm(2)} {ACC1:conc#1107.itm(3)} -attr xrf 52199 -attr oid 255 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1107.itm}
+load net {ACC1-3:exs#1064.itm(0)} -attr vt d
+load net {ACC1-3:exs#1064.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1064.itm} 2 {ACC1-3:exs#1064.itm(0)} {ACC1-3:exs#1064.itm(1)} -attr xrf 52200 -attr oid 256 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1064.itm}
+load net {ACC1:acc#569.itm(0)} -attr vt d
+load net {ACC1:acc#569.itm(1)} -attr vt d
+load net {ACC1:acc#569.itm(2)} -attr vt d
+load net {ACC1:acc#569.itm(3)} -attr vt d
+load net {ACC1:acc#569.itm(4)} -attr vt d
+load net {ACC1:acc#569.itm(5)} -attr vt d
+load netBundle {ACC1:acc#569.itm} 6 {ACC1:acc#569.itm(0)} {ACC1:acc#569.itm(1)} {ACC1:acc#569.itm(2)} {ACC1:acc#569.itm(3)} {ACC1:acc#569.itm(4)} {ACC1:acc#569.itm(5)} -attr xrf 52201 -attr oid 257 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:conc#1114.itm(0)} -attr vt d
+load net {ACC1:conc#1114.itm(1)} -attr vt d
+load net {ACC1:conc#1114.itm(2)} -attr vt d
+load net {ACC1:conc#1114.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1114.itm} 4 {ACC1:conc#1114.itm(0)} {ACC1:conc#1114.itm(1)} {ACC1:conc#1114.itm(2)} {ACC1:conc#1114.itm(3)} -attr xrf 52202 -attr oid 258 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1114.itm}
+load net {ACC1-2:exs#18.itm(0)} -attr vt d
+load net {ACC1-2:exs#18.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#18.itm} 2 {ACC1-2:exs#18.itm(0)} {ACC1-2:exs#18.itm(1)} -attr xrf 52203 -attr oid 259 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#18.itm}
+load net {ACC1:acc#519.itm(0)} -attr vt d
+load net {ACC1:acc#519.itm(1)} -attr vt d
+load net {ACC1:acc#519.itm(2)} -attr vt d
+load netBundle {ACC1:acc#519.itm} 3 {ACC1:acc#519.itm(0)} {ACC1:acc#519.itm(1)} {ACC1:acc#519.itm(2)} -attr xrf 52204 -attr oid 260 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load net {slc(ACC1:acc#220.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#220.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#220.psp.sva)#2.itm} 2 {slc(ACC1:acc#220.psp.sva)#2.itm(0)} {slc(ACC1:acc#220.psp.sva)#2.itm(1)} -attr xrf 52205 -attr oid 261 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp.sva)#2.itm}
+load net {slc(ACC1:acc#222.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#222.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#222.psp.sva)#2.itm} 2 {slc(ACC1:acc#222.psp.sva)#2.itm(0)} {slc(ACC1:acc#222.psp.sva)#2.itm(1)} -attr xrf 52206 -attr oid 262 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp.sva)#2.itm}
+load net {conc#911.itm(0)} -attr vt d
+load net {conc#911.itm(1)} -attr vt d
+load net {conc#911.itm(2)} -attr vt d
+load net {conc#911.itm(3)} -attr vt d
+load net {conc#911.itm(4)} -attr vt d
+load net {conc#911.itm(5)} -attr vt d
+load net {conc#911.itm(6)} -attr vt d
+load net {conc#911.itm(7)} -attr vt d
+load net {conc#911.itm(8)} -attr vt d
+load netBundle {conc#911.itm} 9 {conc#911.itm(0)} {conc#911.itm(1)} {conc#911.itm(2)} {conc#911.itm(3)} {conc#911.itm(4)} {conc#911.itm(5)} {conc#911.itm(6)} {conc#911.itm(7)} {conc#911.itm(8)} -attr xrf 52207 -attr oid 263 -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {ACC1-3:exs#1065.itm(0)} -attr vt d
+load net {ACC1-3:exs#1065.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1065.itm} 2 {ACC1-3:exs#1065.itm(0)} {ACC1-3:exs#1065.itm(1)} -attr xrf 52208 -attr oid 264 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1065.itm}
+load net {ACC1:mul#54.itm(0)} -attr vt d
+load net {ACC1:mul#54.itm(1)} -attr vt d
+load net {ACC1:mul#54.itm(2)} -attr vt d
+load net {ACC1:mul#54.itm(3)} -attr vt d
+load net {ACC1:mul#54.itm(4)} -attr vt d
+load net {ACC1:mul#54.itm(5)} -attr vt d
+load net {ACC1:mul#54.itm(6)} -attr vt d
+load net {ACC1:mul#54.itm(7)} -attr vt d
+load net {ACC1:mul#54.itm(8)} -attr vt d
+load net {ACC1:mul#54.itm(9)} -attr vt d
+load netBundle {ACC1:mul#54.itm} 10 {ACC1:mul#54.itm(0)} {ACC1:mul#54.itm(1)} {ACC1:mul#54.itm(2)} {ACC1:mul#54.itm(3)} {ACC1:mul#54.itm(4)} {ACC1:mul#54.itm(5)} {ACC1:mul#54.itm(6)} {ACC1:mul#54.itm(7)} {ACC1:mul#54.itm(8)} {ACC1:mul#54.itm(9)} -attr xrf 52209 -attr oid 265 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:acc#302.itm(0)} -attr vt d
+load net {ACC1:acc#302.itm(1)} -attr vt d
+load net {ACC1:acc#302.itm(2)} -attr vt d
+load net {ACC1:acc#302.itm(3)} -attr vt d
+load netBundle {ACC1:acc#302.itm} 4 {ACC1:acc#302.itm(0)} {ACC1:acc#302.itm(1)} {ACC1:acc#302.itm(2)} {ACC1:acc#302.itm(3)} -attr xrf 52210 -attr oid 266 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#303.itm(0)} -attr vt d
+load net {ACC1:acc#303.itm(1)} -attr vt d
+load net {ACC1:acc#303.itm(2)} -attr vt d
+load netBundle {ACC1:acc#303.itm} 3 {ACC1:acc#303.itm(0)} {ACC1:acc#303.itm(1)} {ACC1:acc#303.itm(2)} -attr xrf 52211 -attr oid 267 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#304.itm(0)} -attr vt d
+load net {ACC1:acc#304.itm(1)} -attr vt d
+load net {ACC1:acc#304.itm(2)} -attr vt d
+load netBundle {ACC1:acc#304.itm} 3 {ACC1:acc#304.itm(0)} {ACC1:acc#304.itm(1)} {ACC1:acc#304.itm(2)} -attr xrf 52212 -attr oid 268 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#305.itm(0)} -attr vt d
+load net {ACC1:acc#305.itm(1)} -attr vt d
+load net {ACC1:acc#305.itm(2)} -attr vt d
+load netBundle {ACC1:acc#305.itm} 3 {ACC1:acc#305.itm(0)} {ACC1:acc#305.itm(1)} {ACC1:acc#305.itm(2)} -attr xrf 52213 -attr oid 269 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#306.itm(0)} -attr vt d
+load net {ACC1:acc#306.itm(1)} -attr vt d
+load net {ACC1:acc#306.itm(2)} -attr vt d
+load netBundle {ACC1:acc#306.itm} 3 {ACC1:acc#306.itm(0)} {ACC1:acc#306.itm(1)} {ACC1:acc#306.itm(2)} -attr xrf 52214 -attr oid 270 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#307.itm(0)} -attr vt d
+load net {ACC1:acc#307.itm(1)} -attr vt d
+load netBundle {ACC1:acc#307.itm} 2 {ACC1:acc#307.itm(0)} {ACC1:acc#307.itm(1)} -attr xrf 52215 -attr oid 271 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#308.itm(0)} -attr vt d
+load net {ACC1:acc#308.itm(1)} -attr vt d
+load netBundle {ACC1:acc#308.itm} 2 {ACC1:acc#308.itm(0)} {ACC1:acc#308.itm(1)} -attr xrf 52216 -attr oid 272 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:mul#55.itm(0)} -attr vt d
+load net {ACC1:mul#55.itm(1)} -attr vt d
+load net {ACC1:mul#55.itm(2)} -attr vt d
+load net {ACC1:mul#55.itm(3)} -attr vt d
+load net {ACC1:mul#55.itm(4)} -attr vt d
+load net {ACC1:mul#55.itm(5)} -attr vt d
+load net {ACC1:mul#55.itm(6)} -attr vt d
+load net {ACC1:mul#55.itm(7)} -attr vt d
+load net {ACC1:mul#55.itm(8)} -attr vt d
+load net {ACC1:mul#55.itm(9)} -attr vt d
+load net {ACC1:mul#55.itm(10)} -attr vt d
+load net {ACC1:mul#55.itm(11)} -attr vt d
+load netBundle {ACC1:mul#55.itm} 12 {ACC1:mul#55.itm(0)} {ACC1:mul#55.itm(1)} {ACC1:mul#55.itm(2)} {ACC1:mul#55.itm(3)} {ACC1:mul#55.itm(4)} {ACC1:mul#55.itm(5)} {ACC1:mul#55.itm(6)} {ACC1:mul#55.itm(7)} {ACC1:mul#55.itm(8)} {ACC1:mul#55.itm(9)} {ACC1:mul#55.itm(10)} {ACC1:mul#55.itm(11)} -attr xrf 52217 -attr oid 273 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:acc#309.itm(0)} -attr vt d
+load net {ACC1:acc#309.itm(1)} -attr vt d
+load net {ACC1:acc#309.itm(2)} -attr vt d
+load net {ACC1:acc#309.itm(3)} -attr vt d
+load netBundle {ACC1:acc#309.itm} 4 {ACC1:acc#309.itm(0)} {ACC1:acc#309.itm(1)} {ACC1:acc#309.itm(2)} {ACC1:acc#309.itm(3)} -attr xrf 52218 -attr oid 274 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#310.itm(0)} -attr vt d
+load net {ACC1:acc#310.itm(1)} -attr vt d
+load net {ACC1:acc#310.itm(2)} -attr vt d
+load netBundle {ACC1:acc#310.itm} 3 {ACC1:acc#310.itm(0)} {ACC1:acc#310.itm(1)} {ACC1:acc#310.itm(2)} -attr xrf 52219 -attr oid 275 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#311.itm(0)} -attr vt d
+load net {ACC1:acc#311.itm(1)} -attr vt d
+load net {ACC1:acc#311.itm(2)} -attr vt d
+load netBundle {ACC1:acc#311.itm} 3 {ACC1:acc#311.itm(0)} {ACC1:acc#311.itm(1)} {ACC1:acc#311.itm(2)} -attr xrf 52220 -attr oid 276 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#312.itm(0)} -attr vt d
+load net {ACC1:acc#312.itm(1)} -attr vt d
+load net {ACC1:acc#312.itm(2)} -attr vt d
+load netBundle {ACC1:acc#312.itm} 3 {ACC1:acc#312.itm(0)} {ACC1:acc#312.itm(1)} {ACC1:acc#312.itm(2)} -attr xrf 52221 -attr oid 277 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#313.itm(0)} -attr vt d
+load net {ACC1:acc#313.itm(1)} -attr vt d
+load net {ACC1:acc#313.itm(2)} -attr vt d
+load netBundle {ACC1:acc#313.itm} 3 {ACC1:acc#313.itm(0)} {ACC1:acc#313.itm(1)} {ACC1:acc#313.itm(2)} -attr xrf 52222 -attr oid 278 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#314.itm(0)} -attr vt d
+load net {ACC1:acc#314.itm(1)} -attr vt d
+load netBundle {ACC1:acc#314.itm} 2 {ACC1:acc#314.itm(0)} {ACC1:acc#314.itm(1)} -attr xrf 52223 -attr oid 279 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#315.itm(0)} -attr vt d
+load net {ACC1:acc#315.itm(1)} -attr vt d
+load netBundle {ACC1:acc#315.itm} 2 {ACC1:acc#315.itm(0)} {ACC1:acc#315.itm(1)} -attr xrf 52224 -attr oid 280 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#661.itm(0)} -attr vt d
+load net {ACC1:acc#661.itm(1)} -attr vt d
+load net {ACC1:acc#661.itm(2)} -attr vt d
+load net {ACC1:acc#661.itm(3)} -attr vt d
+load net {ACC1:acc#661.itm(4)} -attr vt d
+load net {ACC1:acc#661.itm(5)} -attr vt d
+load net {ACC1:acc#661.itm(6)} -attr vt d
+load net {ACC1:acc#661.itm(7)} -attr vt d
+load net {ACC1:acc#661.itm(8)} -attr vt d
+load net {ACC1:acc#661.itm(9)} -attr vt d
+load net {ACC1:acc#661.itm(10)} -attr vt d
+load net {ACC1:acc#661.itm(11)} -attr vt d
+load net {ACC1:acc#661.itm(12)} -attr vt d
+load net {ACC1:acc#661.itm(13)} -attr vt d
+load netBundle {ACC1:acc#661.itm} 14 {ACC1:acc#661.itm(0)} {ACC1:acc#661.itm(1)} {ACC1:acc#661.itm(2)} {ACC1:acc#661.itm(3)} {ACC1:acc#661.itm(4)} {ACC1:acc#661.itm(5)} {ACC1:acc#661.itm(6)} {ACC1:acc#661.itm(7)} {ACC1:acc#661.itm(8)} {ACC1:acc#661.itm(9)} {ACC1:acc#661.itm(10)} {ACC1:acc#661.itm(11)} {ACC1:acc#661.itm(12)} {ACC1:acc#661.itm(13)} -attr xrf 52225 -attr oid 281 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#657.itm(0)} -attr vt d
+load net {ACC1:acc#657.itm(1)} -attr vt d
+load net {ACC1:acc#657.itm(2)} -attr vt d
+load net {ACC1:acc#657.itm(3)} -attr vt d
+load net {ACC1:acc#657.itm(4)} -attr vt d
+load net {ACC1:acc#657.itm(5)} -attr vt d
+load net {ACC1:acc#657.itm(6)} -attr vt d
+load net {ACC1:acc#657.itm(7)} -attr vt d
+load net {ACC1:acc#657.itm(8)} -attr vt d
+load net {ACC1:acc#657.itm(9)} -attr vt d
+load net {ACC1:acc#657.itm(10)} -attr vt d
+load net {ACC1:acc#657.itm(11)} -attr vt d
+load net {ACC1:acc#657.itm(12)} -attr vt d
+load netBundle {ACC1:acc#657.itm} 13 {ACC1:acc#657.itm(0)} {ACC1:acc#657.itm(1)} {ACC1:acc#657.itm(2)} {ACC1:acc#657.itm(3)} {ACC1:acc#657.itm(4)} {ACC1:acc#657.itm(5)} {ACC1:acc#657.itm(6)} {ACC1:acc#657.itm(7)} {ACC1:acc#657.itm(8)} {ACC1:acc#657.itm(9)} {ACC1:acc#657.itm(10)} {ACC1:acc#657.itm(11)} {ACC1:acc#657.itm(12)} -attr xrf 52226 -attr oid 282 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {conc#912.itm(0)} -attr vt d
+load net {conc#912.itm(1)} -attr vt d
+load net {conc#912.itm(2)} -attr vt d
+load net {conc#912.itm(3)} -attr vt d
+load net {conc#912.itm(4)} -attr vt d
+load net {conc#912.itm(5)} -attr vt d
+load net {conc#912.itm(6)} -attr vt d
+load net {conc#912.itm(7)} -attr vt d
+load net {conc#912.itm(8)} -attr vt d
+load net {conc#912.itm(9)} -attr vt d
+load net {conc#912.itm(10)} -attr vt d
+load net {conc#912.itm(11)} -attr vt d
+load netBundle {conc#912.itm} 12 {conc#912.itm(0)} {conc#912.itm(1)} {conc#912.itm(2)} {conc#912.itm(3)} {conc#912.itm(4)} {conc#912.itm(5)} {conc#912.itm(6)} {conc#912.itm(7)} {conc#912.itm(8)} {conc#912.itm(9)} {conc#912.itm(10)} {conc#912.itm(11)} -attr xrf 52227 -attr oid 283 -attr vt d -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {ACC1:conc#1106.itm(0)} -attr vt d
+load net {ACC1:conc#1106.itm(1)} -attr vt d
+load net {ACC1:conc#1106.itm(2)} -attr vt d
+load net {ACC1:conc#1106.itm(3)} -attr vt d
+load net {ACC1:conc#1106.itm(4)} -attr vt d
+load net {ACC1:conc#1106.itm(5)} -attr vt d
+load net {ACC1:conc#1106.itm(6)} -attr vt d
+load net {ACC1:conc#1106.itm(7)} -attr vt d
+load net {ACC1:conc#1106.itm(8)} -attr vt d
+load net {ACC1:conc#1106.itm(9)} -attr vt d
+load net {ACC1:conc#1106.itm(10)} -attr vt d
+load net {ACC1:conc#1106.itm(11)} -attr vt d
+load netBundle {ACC1:conc#1106.itm} 12 {ACC1:conc#1106.itm(0)} {ACC1:conc#1106.itm(1)} {ACC1:conc#1106.itm(2)} {ACC1:conc#1106.itm(3)} {ACC1:conc#1106.itm(4)} {ACC1:conc#1106.itm(5)} {ACC1:conc#1106.itm(6)} {ACC1:conc#1106.itm(7)} {ACC1:conc#1106.itm(8)} {ACC1:conc#1106.itm(9)} {ACC1:conc#1106.itm(10)} {ACC1:conc#1106.itm(11)} -attr xrf 52228 -attr oid 284 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(0)} -attr vt d
+load net {ACC1:mul#59.itm(1)} -attr vt d
+load net {ACC1:mul#59.itm(2)} -attr vt d
+load net {ACC1:mul#59.itm(3)} -attr vt d
+load net {ACC1:mul#59.itm(4)} -attr vt d
+load net {ACC1:mul#59.itm(5)} -attr vt d
+load net {ACC1:mul#59.itm(6)} -attr vt d
+load net {ACC1:mul#59.itm(7)} -attr vt d
+load net {ACC1:mul#59.itm(8)} -attr vt d
+load netBundle {ACC1:mul#59.itm} 9 {ACC1:mul#59.itm(0)} {ACC1:mul#59.itm(1)} {ACC1:mul#59.itm(2)} {ACC1:mul#59.itm(3)} {ACC1:mul#59.itm(4)} {ACC1:mul#59.itm(5)} {ACC1:mul#59.itm(6)} {ACC1:mul#59.itm(7)} {ACC1:mul#59.itm(8)} -attr xrf 52229 -attr oid 285 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:acc#327.itm(0)} -attr vt d
+load net {ACC1:acc#327.itm(1)} -attr vt d
+load net {ACC1:acc#327.itm(2)} -attr vt d
+load netBundle {ACC1:acc#327.itm} 3 {ACC1:acc#327.itm(0)} {ACC1:acc#327.itm(1)} {ACC1:acc#327.itm(2)} -attr xrf 52230 -attr oid 286 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#328.itm(0)} -attr vt d
+load net {ACC1:acc#328.itm(1)} -attr vt d
+load netBundle {ACC1:acc#328.itm} 2 {ACC1:acc#328.itm(0)} {ACC1:acc#328.itm(1)} -attr xrf 52231 -attr oid 287 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#329.itm(0)} -attr vt d
+load net {ACC1:acc#329.itm(1)} -attr vt d
+load netBundle {ACC1:acc#329.itm} 2 {ACC1:acc#329.itm(0)} {ACC1:acc#329.itm(1)} -attr xrf 52232 -attr oid 288 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1-3:exs#1034.itm(0)} -attr vt d
+load net {ACC1-3:exs#1034.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1034.itm} 2 {ACC1-3:exs#1034.itm(0)} {ACC1-3:exs#1034.itm(1)} -attr xrf 52233 -attr oid 289 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1034.itm}
+load net {ACC1:mul#56.itm(0)} -attr vt d
+load net {ACC1:mul#56.itm(1)} -attr vt d
+load net {ACC1:mul#56.itm(2)} -attr vt d
+load net {ACC1:mul#56.itm(3)} -attr vt d
+load net {ACC1:mul#56.itm(4)} -attr vt d
+load net {ACC1:mul#56.itm(5)} -attr vt d
+load net {ACC1:mul#56.itm(6)} -attr vt d
+load net {ACC1:mul#56.itm(7)} -attr vt d
+load net {ACC1:mul#56.itm(8)} -attr vt d
+load net {ACC1:mul#56.itm(9)} -attr vt d
+load net {ACC1:mul#56.itm(10)} -attr vt d
+load net {ACC1:mul#56.itm(11)} -attr vt d
+load net {ACC1:mul#56.itm(12)} -attr vt d
+load netBundle {ACC1:mul#56.itm} 13 {ACC1:mul#56.itm(0)} {ACC1:mul#56.itm(1)} {ACC1:mul#56.itm(2)} {ACC1:mul#56.itm(3)} {ACC1:mul#56.itm(4)} {ACC1:mul#56.itm(5)} {ACC1:mul#56.itm(6)} {ACC1:mul#56.itm(7)} {ACC1:mul#56.itm(8)} {ACC1:mul#56.itm(9)} {ACC1:mul#56.itm(10)} {ACC1:mul#56.itm(11)} {ACC1:mul#56.itm(12)} -attr xrf 52234 -attr oid 290 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:acc#316.itm(0)} -attr vt d
+load net {ACC1:acc#316.itm(1)} -attr vt d
+load netBundle {ACC1:acc#316.itm} 2 {ACC1:acc#316.itm(0)} {ACC1:acc#316.itm(1)} -attr xrf 52235 -attr oid 291 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#317.itm(0)} -attr vt d
+load net {ACC1:acc#317.itm(1)} -attr vt d
+load netBundle {ACC1:acc#317.itm} 2 {ACC1:acc#317.itm(0)} {ACC1:acc#317.itm(1)} -attr xrf 52236 -attr oid 292 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {slc(ACC1:mul#57.itm)#2.itm(0)} -attr vt d
+load net {slc(ACC1:mul#57.itm)#2.itm(1)} -attr vt d
+load net {slc(ACC1:mul#57.itm)#2.itm(2)} -attr vt d
+load net {slc(ACC1:mul#57.itm)#2.itm(3)} -attr vt d
+load net {slc(ACC1:mul#57.itm)#2.itm(4)} -attr vt d
+load netBundle {slc(ACC1:mul#57.itm)#2.itm} 5 {slc(ACC1:mul#57.itm)#2.itm(0)} {slc(ACC1:mul#57.itm)#2.itm(1)} {slc(ACC1:mul#57.itm)#2.itm(2)} {slc(ACC1:mul#57.itm)#2.itm(3)} {slc(ACC1:mul#57.itm)#2.itm(4)} -attr xrf 52237 -attr oid 293 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#2.itm}
+load net {slc(ACC1:mul#57.itm)#3.itm(0)} -attr vt d
+load net {slc(ACC1:mul#57.itm)#3.itm(1)} -attr vt d
+load netBundle {slc(ACC1:mul#57.itm)#3.itm} 2 {slc(ACC1:mul#57.itm)#3.itm(0)} {slc(ACC1:mul#57.itm)#3.itm(1)} -attr xrf 52238 -attr oid 294 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#3.itm}
+load net {ACC1:acc#652.itm(0)} -attr vt d
+load net {ACC1:acc#652.itm(1)} -attr vt d
+load net {ACC1:acc#652.itm(2)} -attr vt d
+load net {ACC1:acc#652.itm(3)} -attr vt d
+load net {ACC1:acc#652.itm(4)} -attr vt d
+load net {ACC1:acc#652.itm(5)} -attr vt d
+load net {ACC1:acc#652.itm(6)} -attr vt d
+load net {ACC1:acc#652.itm(7)} -attr vt d
+load net {ACC1:acc#652.itm(8)} -attr vt d
+load net {ACC1:acc#652.itm(9)} -attr vt d
+load net {ACC1:acc#652.itm(10)} -attr vt d
+load netBundle {ACC1:acc#652.itm} 11 {ACC1:acc#652.itm(0)} {ACC1:acc#652.itm(1)} {ACC1:acc#652.itm(2)} {ACC1:acc#652.itm(3)} {ACC1:acc#652.itm(4)} {ACC1:acc#652.itm(5)} {ACC1:acc#652.itm(6)} {ACC1:acc#652.itm(7)} {ACC1:acc#652.itm(8)} {ACC1:acc#652.itm(9)} {ACC1:acc#652.itm(10)} -attr xrf 52239 -attr oid 295 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#649.itm(0)} -attr vt d
+load net {ACC1:acc#649.itm(1)} -attr vt d
+load net {ACC1:acc#649.itm(2)} -attr vt d
+load net {ACC1:acc#649.itm(3)} -attr vt d
+load net {ACC1:acc#649.itm(4)} -attr vt d
+load net {ACC1:acc#649.itm(5)} -attr vt d
+load net {ACC1:acc#649.itm(6)} -attr vt d
+load net {ACC1:acc#649.itm(7)} -attr vt d
+load net {ACC1:acc#649.itm(8)} -attr vt d
+load net {ACC1:acc#649.itm(9)} -attr vt d
+load netBundle {ACC1:acc#649.itm} 10 {ACC1:acc#649.itm(0)} {ACC1:acc#649.itm(1)} {ACC1:acc#649.itm(2)} {ACC1:acc#649.itm(3)} {ACC1:acc#649.itm(4)} {ACC1:acc#649.itm(5)} {ACC1:acc#649.itm(6)} {ACC1:acc#649.itm(7)} {ACC1:acc#649.itm(8)} {ACC1:acc#649.itm(9)} -attr xrf 52240 -attr oid 296 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#644.itm(0)} -attr vt d
+load net {ACC1:acc#644.itm(1)} -attr vt d
+load net {ACC1:acc#644.itm(2)} -attr vt d
+load net {ACC1:acc#644.itm(3)} -attr vt d
+load net {ACC1:acc#644.itm(4)} -attr vt d
+load net {ACC1:acc#644.itm(5)} -attr vt d
+load net {ACC1:acc#644.itm(6)} -attr vt d
+load net {ACC1:acc#644.itm(7)} -attr vt d
+load net {ACC1:acc#644.itm(8)} -attr vt d
+load netBundle {ACC1:acc#644.itm} 9 {ACC1:acc#644.itm(0)} {ACC1:acc#644.itm(1)} {ACC1:acc#644.itm(2)} {ACC1:acc#644.itm(3)} {ACC1:acc#644.itm(4)} {ACC1:acc#644.itm(5)} {ACC1:acc#644.itm(6)} {ACC1:acc#644.itm(7)} {ACC1:acc#644.itm(8)} -attr xrf 52241 -attr oid 297 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#636.itm(0)} -attr vt d
+load net {ACC1:acc#636.itm(1)} -attr vt d
+load net {ACC1:acc#636.itm(2)} -attr vt d
+load net {ACC1:acc#636.itm(3)} -attr vt d
+load net {ACC1:acc#636.itm(4)} -attr vt d
+load net {ACC1:acc#636.itm(5)} -attr vt d
+load net {ACC1:acc#636.itm(6)} -attr vt d
+load net {ACC1:acc#636.itm(7)} -attr vt d
+load netBundle {ACC1:acc#636.itm} 8 {ACC1:acc#636.itm(0)} {ACC1:acc#636.itm(1)} {ACC1:acc#636.itm(2)} {ACC1:acc#636.itm(3)} {ACC1:acc#636.itm(4)} {ACC1:acc#636.itm(5)} {ACC1:acc#636.itm(6)} {ACC1:acc#636.itm(7)} -attr xrf 52242 -attr oid 298 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#623.itm(0)} -attr vt d
+load net {ACC1:acc#623.itm(1)} -attr vt d
+load net {ACC1:acc#623.itm(2)} -attr vt d
+load net {ACC1:acc#623.itm(3)} -attr vt d
+load net {ACC1:acc#623.itm(4)} -attr vt d
+load net {ACC1:acc#623.itm(5)} -attr vt d
+load net {ACC1:acc#623.itm(6)} -attr vt d
+load netBundle {ACC1:acc#623.itm} 7 {ACC1:acc#623.itm(0)} {ACC1:acc#623.itm(1)} {ACC1:acc#623.itm(2)} {ACC1:acc#623.itm(3)} {ACC1:acc#623.itm(4)} {ACC1:acc#623.itm(5)} {ACC1:acc#623.itm(6)} -attr xrf 52243 -attr oid 299 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#607.itm(0)} -attr vt d
+load net {ACC1:acc#607.itm(1)} -attr vt d
+load net {ACC1:acc#607.itm(2)} -attr vt d
+load net {ACC1:acc#607.itm(3)} -attr vt d
+load net {ACC1:acc#607.itm(4)} -attr vt d
+load net {ACC1:acc#607.itm(5)} -attr vt d
+load netBundle {ACC1:acc#607.itm} 6 {ACC1:acc#607.itm(0)} {ACC1:acc#607.itm(1)} {ACC1:acc#607.itm(2)} {ACC1:acc#607.itm(3)} {ACC1:acc#607.itm(4)} {ACC1:acc#607.itm(5)} -attr xrf 52244 -attr oid 300 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#585.itm(0)} -attr vt d
+load net {ACC1:acc#585.itm(1)} -attr vt d
+load net {ACC1:acc#585.itm(2)} -attr vt d
+load net {ACC1:acc#585.itm(3)} -attr vt d
+load net {ACC1:acc#585.itm(4)} -attr vt d
+load netBundle {ACC1:acc#585.itm} 5 {ACC1:acc#585.itm(0)} {ACC1:acc#585.itm(1)} {ACC1:acc#585.itm(2)} {ACC1:acc#585.itm(3)} {ACC1:acc#585.itm(4)} -attr xrf 52245 -attr oid 301 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#540.itm(0)} -attr vt d
+load net {ACC1:acc#540.itm(1)} -attr vt d
+load net {ACC1:acc#540.itm(2)} -attr vt d
+load net {ACC1:acc#540.itm(3)} -attr vt d
+load netBundle {ACC1:acc#540.itm} 4 {ACC1:acc#540.itm(0)} {ACC1:acc#540.itm(1)} {ACC1:acc#540.itm(2)} {ACC1:acc#540.itm(3)} -attr xrf 52246 -attr oid 302 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:slc#126.itm(0)} -attr vt d
+load net {ACC1:slc#126.itm(1)} -attr vt d
+load net {ACC1:slc#126.itm(2)} -attr vt d
+load netBundle {ACC1:slc#126.itm} 3 {ACC1:slc#126.itm(0)} {ACC1:slc#126.itm(1)} {ACC1:slc#126.itm(2)} -attr xrf 52247 -attr oid 303 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#126.itm}
+load net {ACC1:acc#458.itm(0)} -attr vt d
+load net {ACC1:acc#458.itm(1)} -attr vt d
+load net {ACC1:acc#458.itm(2)} -attr vt d
+load net {ACC1:acc#458.itm(3)} -attr vt d
+load netBundle {ACC1:acc#458.itm} 4 {ACC1:acc#458.itm(0)} {ACC1:acc#458.itm(1)} {ACC1:acc#458.itm(2)} {ACC1:acc#458.itm(3)} -attr xrf 52248 -attr oid 304 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#458.itm}
+load net {exs#55.itm(0)} -attr vt d
+load net {exs#55.itm(1)} -attr vt d
+load net {exs#55.itm(2)} -attr vt d
+load netBundle {exs#55.itm} 3 {exs#55.itm(0)} {exs#55.itm(1)} {exs#55.itm(2)} -attr xrf 52249 -attr oid 305 -attr vt d -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {conc#913.itm(0)} -attr vt d
+load net {conc#913.itm(1)} -attr vt d
+load netBundle {conc#913.itm} 2 {conc#913.itm(0)} {conc#913.itm(1)} -attr xrf 52250 -attr oid 306 -attr vt d -attr @path {/sobel/sobel:core/conc#913.itm}
+load net {ACC1:exs#1497.itm(0)} -attr vt d
+load net {ACC1:exs#1497.itm(1)} -attr vt d
+load net {ACC1:exs#1497.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1497.itm} 3 {ACC1:exs#1497.itm(0)} {ACC1:exs#1497.itm(1)} {ACC1:exs#1497.itm(2)} -attr xrf 52251 -attr oid 307 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1497.itm}
+load net {ACC1:conc#1375.itm(0)} -attr vt d
+load net {ACC1:conc#1375.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1375.itm} 2 {ACC1:conc#1375.itm(0)} {ACC1:conc#1375.itm(1)} -attr xrf 52252 -attr oid 308 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1375.itm}
+load net {ACC1:slc#125.itm(0)} -attr vt d
+load net {ACC1:slc#125.itm(1)} -attr vt d
+load net {ACC1:slc#125.itm(2)} -attr vt d
+load netBundle {ACC1:slc#125.itm} 3 {ACC1:slc#125.itm(0)} {ACC1:slc#125.itm(1)} {ACC1:slc#125.itm(2)} -attr xrf 52253 -attr oid 309 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#125.itm}
+load net {ACC1:acc#457.itm(0)} -attr vt d
+load net {ACC1:acc#457.itm(1)} -attr vt d
+load net {ACC1:acc#457.itm(2)} -attr vt d
+load net {ACC1:acc#457.itm(3)} -attr vt d
+load netBundle {ACC1:acc#457.itm} 4 {ACC1:acc#457.itm(0)} {ACC1:acc#457.itm(1)} {ACC1:acc#457.itm(2)} {ACC1:acc#457.itm(3)} -attr xrf 52254 -attr oid 310 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#457.itm}
+load net {exs#56.itm(0)} -attr vt d
+load net {exs#56.itm(1)} -attr vt d
+load net {exs#56.itm(2)} -attr vt d
+load netBundle {exs#56.itm} 3 {exs#56.itm(0)} {exs#56.itm(1)} {exs#56.itm(2)} -attr xrf 52255 -attr oid 311 -attr vt d -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {conc#914.itm(0)} -attr vt d
+load net {conc#914.itm(1)} -attr vt d
+load netBundle {conc#914.itm} 2 {conc#914.itm(0)} {conc#914.itm(1)} -attr xrf 52256 -attr oid 312 -attr vt d -attr @path {/sobel/sobel:core/conc#914.itm}
+load net {ACC1:exs#1499.itm(0)} -attr vt d
+load net {ACC1:exs#1499.itm(1)} -attr vt d
+load net {ACC1:exs#1499.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1499.itm} 3 {ACC1:exs#1499.itm(0)} {ACC1:exs#1499.itm(1)} {ACC1:exs#1499.itm(2)} -attr xrf 52257 -attr oid 313 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1499.itm}
+load net {ACC1:conc#1373.itm(0)} -attr vt d
+load net {ACC1:conc#1373.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1373.itm} 2 {ACC1:conc#1373.itm(0)} {ACC1:conc#1373.itm(1)} -attr xrf 52258 -attr oid 314 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1373.itm}
+load net {ACC1:acc#539.itm(0)} -attr vt d
+load net {ACC1:acc#539.itm(1)} -attr vt d
+load net {ACC1:acc#539.itm(2)} -attr vt d
+load net {ACC1:acc#539.itm(3)} -attr vt d
+load netBundle {ACC1:acc#539.itm} 4 {ACC1:acc#539.itm(0)} {ACC1:acc#539.itm(1)} {ACC1:acc#539.itm(2)} {ACC1:acc#539.itm(3)} -attr xrf 52259 -attr oid 315 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:slc#124.itm(0)} -attr vt d
+load net {ACC1:slc#124.itm(1)} -attr vt d
+load net {ACC1:slc#124.itm(2)} -attr vt d
+load netBundle {ACC1:slc#124.itm} 3 {ACC1:slc#124.itm(0)} {ACC1:slc#124.itm(1)} {ACC1:slc#124.itm(2)} -attr xrf 52260 -attr oid 316 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#124.itm}
+load net {ACC1:acc#456.itm(0)} -attr vt d
+load net {ACC1:acc#456.itm(1)} -attr vt d
+load net {ACC1:acc#456.itm(2)} -attr vt d
+load net {ACC1:acc#456.itm(3)} -attr vt d
+load netBundle {ACC1:acc#456.itm} 4 {ACC1:acc#456.itm(0)} {ACC1:acc#456.itm(1)} {ACC1:acc#456.itm(2)} {ACC1:acc#456.itm(3)} -attr xrf 52261 -attr oid 317 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#456.itm}
+load net {exs#57.itm(0)} -attr vt d
+load net {exs#57.itm(1)} -attr vt d
+load net {exs#57.itm(2)} -attr vt d
+load netBundle {exs#57.itm} 3 {exs#57.itm(0)} {exs#57.itm(1)} {exs#57.itm(2)} -attr xrf 52262 -attr oid 318 -attr vt d -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {conc#915.itm(0)} -attr vt d
+load net {conc#915.itm(1)} -attr vt d
+load netBundle {conc#915.itm} 2 {conc#915.itm(0)} {conc#915.itm(1)} -attr xrf 52263 -attr oid 319 -attr vt d -attr @path {/sobel/sobel:core/conc#915.itm}
+load net {ACC1:exs#1501.itm(0)} -attr vt d
+load net {ACC1:exs#1501.itm(1)} -attr vt d
+load net {ACC1:exs#1501.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1501.itm} 3 {ACC1:exs#1501.itm(0)} {ACC1:exs#1501.itm(1)} {ACC1:exs#1501.itm(2)} -attr xrf 52264 -attr oid 320 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1501.itm}
+load net {ACC1:conc#1371.itm(0)} -attr vt d
+load net {ACC1:conc#1371.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1371.itm} 2 {ACC1:conc#1371.itm(0)} {ACC1:conc#1371.itm(1)} -attr xrf 52265 -attr oid 321 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1371.itm}
+load net {ACC1:slc#123.itm(0)} -attr vt d
+load net {ACC1:slc#123.itm(1)} -attr vt d
+load net {ACC1:slc#123.itm(2)} -attr vt d
+load netBundle {ACC1:slc#123.itm} 3 {ACC1:slc#123.itm(0)} {ACC1:slc#123.itm(1)} {ACC1:slc#123.itm(2)} -attr xrf 52266 -attr oid 322 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#123.itm}
+load net {ACC1:acc#455.itm(0)} -attr vt d
+load net {ACC1:acc#455.itm(1)} -attr vt d
+load net {ACC1:acc#455.itm(2)} -attr vt d
+load net {ACC1:acc#455.itm(3)} -attr vt d
+load netBundle {ACC1:acc#455.itm} 4 {ACC1:acc#455.itm(0)} {ACC1:acc#455.itm(1)} {ACC1:acc#455.itm(2)} {ACC1:acc#455.itm(3)} -attr xrf 52267 -attr oid 323 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#455.itm}
+load net {exs#58.itm(0)} -attr vt d
+load net {exs#58.itm(1)} -attr vt d
+load net {exs#58.itm(2)} -attr vt d
+load netBundle {exs#58.itm} 3 {exs#58.itm(0)} {exs#58.itm(1)} {exs#58.itm(2)} -attr xrf 52268 -attr oid 324 -attr vt d -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {conc#916.itm(0)} -attr vt d
+load net {conc#916.itm(1)} -attr vt d
+load netBundle {conc#916.itm} 2 {conc#916.itm(0)} {conc#916.itm(1)} -attr xrf 52269 -attr oid 325 -attr vt d -attr @path {/sobel/sobel:core/conc#916.itm}
+load net {ACC1:exs#1503.itm(0)} -attr vt d
+load net {ACC1:exs#1503.itm(1)} -attr vt d
+load net {ACC1:exs#1503.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1503.itm} 3 {ACC1:exs#1503.itm(0)} {ACC1:exs#1503.itm(1)} {ACC1:exs#1503.itm(2)} -attr xrf 52270 -attr oid 326 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1503.itm}
+load net {ACC1:conc#1369.itm(0)} -attr vt d
+load net {ACC1:conc#1369.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1369.itm} 2 {ACC1:conc#1369.itm(0)} {ACC1:conc#1369.itm(1)} -attr xrf 52271 -attr oid 327 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1369.itm}
+load net {ACC1:acc#584.itm(0)} -attr vt d
+load net {ACC1:acc#584.itm(1)} -attr vt d
+load net {ACC1:acc#584.itm(2)} -attr vt d
+load net {ACC1:acc#584.itm(3)} -attr vt d
+load net {ACC1:acc#584.itm(4)} -attr vt d
+load netBundle {ACC1:acc#584.itm} 5 {ACC1:acc#584.itm(0)} {ACC1:acc#584.itm(1)} {ACC1:acc#584.itm(2)} {ACC1:acc#584.itm(3)} {ACC1:acc#584.itm(4)} -attr xrf 52272 -attr oid 328 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#538.itm(0)} -attr vt d
+load net {ACC1:acc#538.itm(1)} -attr vt d
+load net {ACC1:acc#538.itm(2)} -attr vt d
+load net {ACC1:acc#538.itm(3)} -attr vt d
+load netBundle {ACC1:acc#538.itm} 4 {ACC1:acc#538.itm(0)} {ACC1:acc#538.itm(1)} {ACC1:acc#538.itm(2)} {ACC1:acc#538.itm(3)} -attr xrf 52273 -attr oid 329 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:slc#122.itm(0)} -attr vt d
+load net {ACC1:slc#122.itm(1)} -attr vt d
+load net {ACC1:slc#122.itm(2)} -attr vt d
+load netBundle {ACC1:slc#122.itm} 3 {ACC1:slc#122.itm(0)} {ACC1:slc#122.itm(1)} {ACC1:slc#122.itm(2)} -attr xrf 52274 -attr oid 330 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#122.itm}
+load net {ACC1:acc#454.itm(0)} -attr vt d
+load net {ACC1:acc#454.itm(1)} -attr vt d
+load net {ACC1:acc#454.itm(2)} -attr vt d
+load net {ACC1:acc#454.itm(3)} -attr vt d
+load netBundle {ACC1:acc#454.itm} 4 {ACC1:acc#454.itm(0)} {ACC1:acc#454.itm(1)} {ACC1:acc#454.itm(2)} {ACC1:acc#454.itm(3)} -attr xrf 52275 -attr oid 331 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#454.itm}
+load net {exs#59.itm(0)} -attr vt d
+load net {exs#59.itm(1)} -attr vt d
+load net {exs#59.itm(2)} -attr vt d
+load netBundle {exs#59.itm} 3 {exs#59.itm(0)} {exs#59.itm(1)} {exs#59.itm(2)} -attr xrf 52276 -attr oid 332 -attr vt d -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {conc#917.itm(0)} -attr vt d
+load net {conc#917.itm(1)} -attr vt d
+load netBundle {conc#917.itm} 2 {conc#917.itm(0)} {conc#917.itm(1)} -attr xrf 52277 -attr oid 333 -attr vt d -attr @path {/sobel/sobel:core/conc#917.itm}
+load net {ACC1:exs#1505.itm(0)} -attr vt d
+load net {ACC1:exs#1505.itm(1)} -attr vt d
+load net {ACC1:exs#1505.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1505.itm} 3 {ACC1:exs#1505.itm(0)} {ACC1:exs#1505.itm(1)} {ACC1:exs#1505.itm(2)} -attr xrf 52278 -attr oid 334 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1505.itm}
+load net {ACC1:conc#1367.itm(0)} -attr vt d
+load net {ACC1:conc#1367.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1367.itm} 2 {ACC1:conc#1367.itm(0)} {ACC1:conc#1367.itm(1)} -attr xrf 52279 -attr oid 335 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1367.itm}
+load net {ACC1:slc#121.itm(0)} -attr vt d
+load net {ACC1:slc#121.itm(1)} -attr vt d
+load net {ACC1:slc#121.itm(2)} -attr vt d
+load netBundle {ACC1:slc#121.itm} 3 {ACC1:slc#121.itm(0)} {ACC1:slc#121.itm(1)} {ACC1:slc#121.itm(2)} -attr xrf 52280 -attr oid 336 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#121.itm}
+load net {ACC1:acc#453.itm(0)} -attr vt d
+load net {ACC1:acc#453.itm(1)} -attr vt d
+load net {ACC1:acc#453.itm(2)} -attr vt d
+load net {ACC1:acc#453.itm(3)} -attr vt d
+load netBundle {ACC1:acc#453.itm} 4 {ACC1:acc#453.itm(0)} {ACC1:acc#453.itm(1)} {ACC1:acc#453.itm(2)} {ACC1:acc#453.itm(3)} -attr xrf 52281 -attr oid 337 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#453.itm}
+load net {exs#60.itm(0)} -attr vt d
+load net {exs#60.itm(1)} -attr vt d
+load net {exs#60.itm(2)} -attr vt d
+load netBundle {exs#60.itm} 3 {exs#60.itm(0)} {exs#60.itm(1)} {exs#60.itm(2)} -attr xrf 52282 -attr oid 338 -attr vt d -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {conc#918.itm(0)} -attr vt d
+load net {conc#918.itm(1)} -attr vt d
+load netBundle {conc#918.itm} 2 {conc#918.itm(0)} {conc#918.itm(1)} -attr xrf 52283 -attr oid 339 -attr vt d -attr @path {/sobel/sobel:core/conc#918.itm}
+load net {ACC1:exs#1507.itm(0)} -attr vt d
+load net {ACC1:exs#1507.itm(1)} -attr vt d
+load net {ACC1:exs#1507.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1507.itm} 3 {ACC1:exs#1507.itm(0)} {ACC1:exs#1507.itm(1)} {ACC1:exs#1507.itm(2)} -attr xrf 52284 -attr oid 340 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1507.itm}
+load net {ACC1:conc#1365.itm(0)} -attr vt d
+load net {ACC1:conc#1365.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1365.itm} 2 {ACC1:conc#1365.itm(0)} {ACC1:conc#1365.itm(1)} -attr xrf 52285 -attr oid 341 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1365.itm}
+load net {ACC1:acc#537.itm(0)} -attr vt d
+load net {ACC1:acc#537.itm(1)} -attr vt d
+load net {ACC1:acc#537.itm(2)} -attr vt d
+load net {ACC1:acc#537.itm(3)} -attr vt d
+load netBundle {ACC1:acc#537.itm} 4 {ACC1:acc#537.itm(0)} {ACC1:acc#537.itm(1)} {ACC1:acc#537.itm(2)} {ACC1:acc#537.itm(3)} -attr xrf 52286 -attr oid 342 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:slc#120.itm(0)} -attr vt d
+load net {ACC1:slc#120.itm(1)} -attr vt d
+load net {ACC1:slc#120.itm(2)} -attr vt d
+load netBundle {ACC1:slc#120.itm} 3 {ACC1:slc#120.itm(0)} {ACC1:slc#120.itm(1)} {ACC1:slc#120.itm(2)} -attr xrf 52287 -attr oid 343 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#120.itm}
+load net {ACC1:acc#452.itm(0)} -attr vt d
+load net {ACC1:acc#452.itm(1)} -attr vt d
+load net {ACC1:acc#452.itm(2)} -attr vt d
+load net {ACC1:acc#452.itm(3)} -attr vt d
+load netBundle {ACC1:acc#452.itm} 4 {ACC1:acc#452.itm(0)} {ACC1:acc#452.itm(1)} {ACC1:acc#452.itm(2)} {ACC1:acc#452.itm(3)} -attr xrf 52288 -attr oid 344 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#452.itm}
+load net {exs#61.itm(0)} -attr vt d
+load net {exs#61.itm(1)} -attr vt d
+load net {exs#61.itm(2)} -attr vt d
+load netBundle {exs#61.itm} 3 {exs#61.itm(0)} {exs#61.itm(1)} {exs#61.itm(2)} -attr xrf 52289 -attr oid 345 -attr vt d -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {conc#919.itm(0)} -attr vt d
+load net {conc#919.itm(1)} -attr vt d
+load netBundle {conc#919.itm} 2 {conc#919.itm(0)} {conc#919.itm(1)} -attr xrf 52290 -attr oid 346 -attr vt d -attr @path {/sobel/sobel:core/conc#919.itm}
+load net {ACC1:exs#1509.itm(0)} -attr vt d
+load net {ACC1:exs#1509.itm(1)} -attr vt d
+load net {ACC1:exs#1509.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1509.itm} 3 {ACC1:exs#1509.itm(0)} {ACC1:exs#1509.itm(1)} {ACC1:exs#1509.itm(2)} -attr xrf 52291 -attr oid 347 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1509.itm}
+load net {ACC1:conc#1363.itm(0)} -attr vt d
+load net {ACC1:conc#1363.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1363.itm} 2 {ACC1:conc#1363.itm(0)} {ACC1:conc#1363.itm(1)} -attr xrf 52292 -attr oid 348 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1363.itm}
+load net {ACC1:slc#119.itm(0)} -attr vt d
+load net {ACC1:slc#119.itm(1)} -attr vt d
+load net {ACC1:slc#119.itm(2)} -attr vt d
+load netBundle {ACC1:slc#119.itm} 3 {ACC1:slc#119.itm(0)} {ACC1:slc#119.itm(1)} {ACC1:slc#119.itm(2)} -attr xrf 52293 -attr oid 349 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#119.itm}
+load net {ACC1:acc#451.itm(0)} -attr vt d
+load net {ACC1:acc#451.itm(1)} -attr vt d
+load net {ACC1:acc#451.itm(2)} -attr vt d
+load net {ACC1:acc#451.itm(3)} -attr vt d
+load netBundle {ACC1:acc#451.itm} 4 {ACC1:acc#451.itm(0)} {ACC1:acc#451.itm(1)} {ACC1:acc#451.itm(2)} {ACC1:acc#451.itm(3)} -attr xrf 52294 -attr oid 350 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#451.itm}
+load net {exs#62.itm(0)} -attr vt d
+load net {exs#62.itm(1)} -attr vt d
+load net {exs#62.itm(2)} -attr vt d
+load netBundle {exs#62.itm} 3 {exs#62.itm(0)} {exs#62.itm(1)} {exs#62.itm(2)} -attr xrf 52295 -attr oid 351 -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {conc#920.itm(0)} -attr vt d
+load net {conc#920.itm(1)} -attr vt d
+load netBundle {conc#920.itm} 2 {conc#920.itm(0)} {conc#920.itm(1)} -attr xrf 52296 -attr oid 352 -attr vt d -attr @path {/sobel/sobel:core/conc#920.itm}
+load net {ACC1:exs#1511.itm(0)} -attr vt d
+load net {ACC1:exs#1511.itm(1)} -attr vt d
+load net {ACC1:exs#1511.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1511.itm} 3 {ACC1:exs#1511.itm(0)} {ACC1:exs#1511.itm(1)} {ACC1:exs#1511.itm(2)} -attr xrf 52297 -attr oid 353 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1511.itm}
+load net {ACC1:conc#1361.itm(0)} -attr vt d
+load net {ACC1:conc#1361.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1361.itm} 2 {ACC1:conc#1361.itm(0)} {ACC1:conc#1361.itm(1)} -attr xrf 52298 -attr oid 354 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1361.itm}
+load net {ACC1:acc#606.itm(0)} -attr vt d
+load net {ACC1:acc#606.itm(1)} -attr vt d
+load net {ACC1:acc#606.itm(2)} -attr vt d
+load net {ACC1:acc#606.itm(3)} -attr vt d
+load net {ACC1:acc#606.itm(4)} -attr vt d
+load net {ACC1:acc#606.itm(5)} -attr vt d
+load netBundle {ACC1:acc#606.itm} 6 {ACC1:acc#606.itm(0)} {ACC1:acc#606.itm(1)} {ACC1:acc#606.itm(2)} {ACC1:acc#606.itm(3)} {ACC1:acc#606.itm(4)} {ACC1:acc#606.itm(5)} -attr xrf 52299 -attr oid 355 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#583.itm(0)} -attr vt d
+load net {ACC1:acc#583.itm(1)} -attr vt d
+load net {ACC1:acc#583.itm(2)} -attr vt d
+load net {ACC1:acc#583.itm(3)} -attr vt d
+load net {ACC1:acc#583.itm(4)} -attr vt d
+load netBundle {ACC1:acc#583.itm} 5 {ACC1:acc#583.itm(0)} {ACC1:acc#583.itm(1)} {ACC1:acc#583.itm(2)} {ACC1:acc#583.itm(3)} {ACC1:acc#583.itm(4)} -attr xrf 52300 -attr oid 356 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#536.itm(0)} -attr vt d
+load net {ACC1:acc#536.itm(1)} -attr vt d
+load net {ACC1:acc#536.itm(2)} -attr vt d
+load net {ACC1:acc#536.itm(3)} -attr vt d
+load netBundle {ACC1:acc#536.itm} 4 {ACC1:acc#536.itm(0)} {ACC1:acc#536.itm(1)} {ACC1:acc#536.itm(2)} {ACC1:acc#536.itm(3)} -attr xrf 52301 -attr oid 357 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:slc#118.itm(0)} -attr vt d
+load net {ACC1:slc#118.itm(1)} -attr vt d
+load net {ACC1:slc#118.itm(2)} -attr vt d
+load netBundle {ACC1:slc#118.itm} 3 {ACC1:slc#118.itm(0)} {ACC1:slc#118.itm(1)} {ACC1:slc#118.itm(2)} -attr xrf 52302 -attr oid 358 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#118.itm}
+load net {ACC1:acc#450.itm(0)} -attr vt d
+load net {ACC1:acc#450.itm(1)} -attr vt d
+load net {ACC1:acc#450.itm(2)} -attr vt d
+load net {ACC1:acc#450.itm(3)} -attr vt d
+load netBundle {ACC1:acc#450.itm} 4 {ACC1:acc#450.itm(0)} {ACC1:acc#450.itm(1)} {ACC1:acc#450.itm(2)} {ACC1:acc#450.itm(3)} -attr xrf 52303 -attr oid 359 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#450.itm}
+load net {exs#63.itm(0)} -attr vt d
+load net {exs#63.itm(1)} -attr vt d
+load net {exs#63.itm(2)} -attr vt d
+load netBundle {exs#63.itm} 3 {exs#63.itm(0)} {exs#63.itm(1)} {exs#63.itm(2)} -attr xrf 52304 -attr oid 360 -attr vt d -attr @path {/sobel/sobel:core/exs#63.itm}
+load net {conc#921.itm(0)} -attr vt d
+load net {conc#921.itm(1)} -attr vt d
+load netBundle {conc#921.itm} 2 {conc#921.itm(0)} {conc#921.itm(1)} -attr xrf 52305 -attr oid 361 -attr vt d -attr @path {/sobel/sobel:core/conc#921.itm}
+load net {ACC1:exs#1513.itm(0)} -attr vt d
+load net {ACC1:exs#1513.itm(1)} -attr vt d
+load net {ACC1:exs#1513.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1513.itm} 3 {ACC1:exs#1513.itm(0)} {ACC1:exs#1513.itm(1)} {ACC1:exs#1513.itm(2)} -attr xrf 52306 -attr oid 362 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1513.itm}
+load net {ACC1:conc#1359.itm(0)} -attr vt d
+load net {ACC1:conc#1359.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1359.itm} 2 {ACC1:conc#1359.itm(0)} {ACC1:conc#1359.itm(1)} -attr xrf 52307 -attr oid 363 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1359.itm}
+load net {ACC1:slc#117.itm(0)} -attr vt d
+load net {ACC1:slc#117.itm(1)} -attr vt d
+load net {ACC1:slc#117.itm(2)} -attr vt d
+load netBundle {ACC1:slc#117.itm} 3 {ACC1:slc#117.itm(0)} {ACC1:slc#117.itm(1)} {ACC1:slc#117.itm(2)} -attr xrf 52308 -attr oid 364 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#117.itm}
+load net {ACC1:acc#449.itm(0)} -attr vt d
+load net {ACC1:acc#449.itm(1)} -attr vt d
+load net {ACC1:acc#449.itm(2)} -attr vt d
+load net {ACC1:acc#449.itm(3)} -attr vt d
+load netBundle {ACC1:acc#449.itm} 4 {ACC1:acc#449.itm(0)} {ACC1:acc#449.itm(1)} {ACC1:acc#449.itm(2)} {ACC1:acc#449.itm(3)} -attr xrf 52309 -attr oid 365 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#449.itm}
+load net {exs#64.itm(0)} -attr vt d
+load net {exs#64.itm(1)} -attr vt d
+load net {exs#64.itm(2)} -attr vt d
+load netBundle {exs#64.itm} 3 {exs#64.itm(0)} {exs#64.itm(1)} {exs#64.itm(2)} -attr xrf 52310 -attr oid 366 -attr vt d -attr @path {/sobel/sobel:core/exs#64.itm}
+load net {conc#922.itm(0)} -attr vt d
+load net {conc#922.itm(1)} -attr vt d
+load netBundle {conc#922.itm} 2 {conc#922.itm(0)} {conc#922.itm(1)} -attr xrf 52311 -attr oid 367 -attr vt d -attr @path {/sobel/sobel:core/conc#922.itm}
+load net {ACC1:exs#1515.itm(0)} -attr vt d
+load net {ACC1:exs#1515.itm(1)} -attr vt d
+load net {ACC1:exs#1515.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1515.itm} 3 {ACC1:exs#1515.itm(0)} {ACC1:exs#1515.itm(1)} {ACC1:exs#1515.itm(2)} -attr xrf 52312 -attr oid 368 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1515.itm}
+load net {ACC1:conc#1357.itm(0)} -attr vt d
+load net {ACC1:conc#1357.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1357.itm} 2 {ACC1:conc#1357.itm(0)} {ACC1:conc#1357.itm(1)} -attr xrf 52313 -attr oid 369 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1357.itm}
+load net {ACC1:acc#535.itm(0)} -attr vt d
+load net {ACC1:acc#535.itm(1)} -attr vt d
+load net {ACC1:acc#535.itm(2)} -attr vt d
+load net {ACC1:acc#535.itm(3)} -attr vt d
+load netBundle {ACC1:acc#535.itm} 4 {ACC1:acc#535.itm(0)} {ACC1:acc#535.itm(1)} {ACC1:acc#535.itm(2)} {ACC1:acc#535.itm(3)} -attr xrf 52314 -attr oid 370 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:slc#116.itm(0)} -attr vt d
+load net {ACC1:slc#116.itm(1)} -attr vt d
+load net {ACC1:slc#116.itm(2)} -attr vt d
+load netBundle {ACC1:slc#116.itm} 3 {ACC1:slc#116.itm(0)} {ACC1:slc#116.itm(1)} {ACC1:slc#116.itm(2)} -attr xrf 52315 -attr oid 371 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#116.itm}
+load net {ACC1:acc#448.itm(0)} -attr vt d
+load net {ACC1:acc#448.itm(1)} -attr vt d
+load net {ACC1:acc#448.itm(2)} -attr vt d
+load net {ACC1:acc#448.itm(3)} -attr vt d
+load netBundle {ACC1:acc#448.itm} 4 {ACC1:acc#448.itm(0)} {ACC1:acc#448.itm(1)} {ACC1:acc#448.itm(2)} {ACC1:acc#448.itm(3)} -attr xrf 52316 -attr oid 372 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#448.itm}
+load net {exs#65.itm(0)} -attr vt d
+load net {exs#65.itm(1)} -attr vt d
+load net {exs#65.itm(2)} -attr vt d
+load netBundle {exs#65.itm} 3 {exs#65.itm(0)} {exs#65.itm(1)} {exs#65.itm(2)} -attr xrf 52317 -attr oid 373 -attr vt d -attr @path {/sobel/sobel:core/exs#65.itm}
+load net {conc#923.itm(0)} -attr vt d
+load net {conc#923.itm(1)} -attr vt d
+load netBundle {conc#923.itm} 2 {conc#923.itm(0)} {conc#923.itm(1)} -attr xrf 52318 -attr oid 374 -attr vt d -attr @path {/sobel/sobel:core/conc#923.itm}
+load net {ACC1:exs#1517.itm(0)} -attr vt d
+load net {ACC1:exs#1517.itm(1)} -attr vt d
+load net {ACC1:exs#1517.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1517.itm} 3 {ACC1:exs#1517.itm(0)} {ACC1:exs#1517.itm(1)} {ACC1:exs#1517.itm(2)} -attr xrf 52319 -attr oid 375 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1517.itm}
+load net {ACC1:conc#1355.itm(0)} -attr vt d
+load net {ACC1:conc#1355.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1355.itm} 2 {ACC1:conc#1355.itm(0)} {ACC1:conc#1355.itm(1)} -attr xrf 52320 -attr oid 376 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1355.itm}
+load net {ACC1:slc#115.itm(0)} -attr vt d
+load net {ACC1:slc#115.itm(1)} -attr vt d
+load net {ACC1:slc#115.itm(2)} -attr vt d
+load netBundle {ACC1:slc#115.itm} 3 {ACC1:slc#115.itm(0)} {ACC1:slc#115.itm(1)} {ACC1:slc#115.itm(2)} -attr xrf 52321 -attr oid 377 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#115.itm}
+load net {ACC1:acc#447.itm(0)} -attr vt d
+load net {ACC1:acc#447.itm(1)} -attr vt d
+load net {ACC1:acc#447.itm(2)} -attr vt d
+load net {ACC1:acc#447.itm(3)} -attr vt d
+load netBundle {ACC1:acc#447.itm} 4 {ACC1:acc#447.itm(0)} {ACC1:acc#447.itm(1)} {ACC1:acc#447.itm(2)} {ACC1:acc#447.itm(3)} -attr xrf 52322 -attr oid 378 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#447.itm}
+load net {exs#92.itm(0)} -attr vt d
+load net {exs#92.itm(1)} -attr vt d
+load net {exs#92.itm(2)} -attr vt d
+load netBundle {exs#92.itm} 3 {exs#92.itm(0)} {exs#92.itm(1)} {exs#92.itm(2)} -attr xrf 52323 -attr oid 379 -attr vt d -attr @path {/sobel/sobel:core/exs#92.itm}
+load net {conc#924.itm(0)} -attr vt d
+load net {conc#924.itm(1)} -attr vt d
+load netBundle {conc#924.itm} 2 {conc#924.itm(0)} {conc#924.itm(1)} -attr xrf 52324 -attr oid 380 -attr vt d -attr @path {/sobel/sobel:core/conc#924.itm}
+load net {ACC1:exs#1519.itm(0)} -attr vt d
+load net {ACC1:exs#1519.itm(1)} -attr vt d
+load net {ACC1:exs#1519.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1519.itm} 3 {ACC1:exs#1519.itm(0)} {ACC1:exs#1519.itm(1)} {ACC1:exs#1519.itm(2)} -attr xrf 52325 -attr oid 381 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1519.itm}
+load net {ACC1:conc#1353.itm(0)} -attr vt d
+load net {ACC1:conc#1353.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1353.itm} 2 {ACC1:conc#1353.itm(0)} {ACC1:conc#1353.itm(1)} -attr xrf 52326 -attr oid 382 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1353.itm}
+load net {ACC1:acc#582.itm(0)} -attr vt d
+load net {ACC1:acc#582.itm(1)} -attr vt d
+load net {ACC1:acc#582.itm(2)} -attr vt d
+load net {ACC1:acc#582.itm(3)} -attr vt d
+load net {ACC1:acc#582.itm(4)} -attr vt d
+load netBundle {ACC1:acc#582.itm} 5 {ACC1:acc#582.itm(0)} {ACC1:acc#582.itm(1)} {ACC1:acc#582.itm(2)} {ACC1:acc#582.itm(3)} {ACC1:acc#582.itm(4)} -attr xrf 52327 -attr oid 383 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#534.itm(0)} -attr vt d
+load net {ACC1:acc#534.itm(1)} -attr vt d
+load net {ACC1:acc#534.itm(2)} -attr vt d
+load net {ACC1:acc#534.itm(3)} -attr vt d
+load netBundle {ACC1:acc#534.itm} 4 {ACC1:acc#534.itm(0)} {ACC1:acc#534.itm(1)} {ACC1:acc#534.itm(2)} {ACC1:acc#534.itm(3)} -attr xrf 52328 -attr oid 384 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:slc#114.itm(0)} -attr vt d
+load net {ACC1:slc#114.itm(1)} -attr vt d
+load net {ACC1:slc#114.itm(2)} -attr vt d
+load netBundle {ACC1:slc#114.itm} 3 {ACC1:slc#114.itm(0)} {ACC1:slc#114.itm(1)} {ACC1:slc#114.itm(2)} -attr xrf 52329 -attr oid 385 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#114.itm}
+load net {ACC1:acc#446.itm(0)} -attr vt d
+load net {ACC1:acc#446.itm(1)} -attr vt d
+load net {ACC1:acc#446.itm(2)} -attr vt d
+load net {ACC1:acc#446.itm(3)} -attr vt d
+load netBundle {ACC1:acc#446.itm} 4 {ACC1:acc#446.itm(0)} {ACC1:acc#446.itm(1)} {ACC1:acc#446.itm(2)} {ACC1:acc#446.itm(3)} -attr xrf 52330 -attr oid 386 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#446.itm}
+load net {exs#66.itm(0)} -attr vt d
+load net {exs#66.itm(1)} -attr vt d
+load net {exs#66.itm(2)} -attr vt d
+load netBundle {exs#66.itm} 3 {exs#66.itm(0)} {exs#66.itm(1)} {exs#66.itm(2)} -attr xrf 52331 -attr oid 387 -attr vt d -attr @path {/sobel/sobel:core/exs#66.itm}
+load net {conc#926.itm(0)} -attr vt d
+load net {conc#926.itm(1)} -attr vt d
+load netBundle {conc#926.itm} 2 {conc#926.itm(0)} {conc#926.itm(1)} -attr xrf 52332 -attr oid 388 -attr vt d -attr @path {/sobel/sobel:core/conc#926.itm}
+load net {ACC1:exs#1521.itm(0)} -attr vt d
+load net {ACC1:exs#1521.itm(1)} -attr vt d
+load net {ACC1:exs#1521.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1521.itm} 3 {ACC1:exs#1521.itm(0)} {ACC1:exs#1521.itm(1)} {ACC1:exs#1521.itm(2)} -attr xrf 52333 -attr oid 389 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1521.itm}
+load net {ACC1:conc#1351.itm(0)} -attr vt d
+load net {ACC1:conc#1351.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1351.itm} 2 {ACC1:conc#1351.itm(0)} {ACC1:conc#1351.itm(1)} -attr xrf 52334 -attr oid 390 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1351.itm}
+load net {ACC1:slc#113.itm(0)} -attr vt d
+load net {ACC1:slc#113.itm(1)} -attr vt d
+load net {ACC1:slc#113.itm(2)} -attr vt d
+load netBundle {ACC1:slc#113.itm} 3 {ACC1:slc#113.itm(0)} {ACC1:slc#113.itm(1)} {ACC1:slc#113.itm(2)} -attr xrf 52335 -attr oid 391 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#113.itm}
+load net {ACC1:acc#445.itm(0)} -attr vt d
+load net {ACC1:acc#445.itm(1)} -attr vt d
+load net {ACC1:acc#445.itm(2)} -attr vt d
+load net {ACC1:acc#445.itm(3)} -attr vt d
+load netBundle {ACC1:acc#445.itm} 4 {ACC1:acc#445.itm(0)} {ACC1:acc#445.itm(1)} {ACC1:acc#445.itm(2)} {ACC1:acc#445.itm(3)} -attr xrf 52336 -attr oid 392 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#445.itm}
+load net {exs#93.itm(0)} -attr vt d
+load net {exs#93.itm(1)} -attr vt d
+load net {exs#93.itm(2)} -attr vt d
+load netBundle {exs#93.itm} 3 {exs#93.itm(0)} {exs#93.itm(1)} {exs#93.itm(2)} -attr xrf 52337 -attr oid 393 -attr vt d -attr @path {/sobel/sobel:core/exs#93.itm}
+load net {conc#927.itm(0)} -attr vt d
+load net {conc#927.itm(1)} -attr vt d
+load netBundle {conc#927.itm} 2 {conc#927.itm(0)} {conc#927.itm(1)} -attr xrf 52338 -attr oid 394 -attr vt d -attr @path {/sobel/sobel:core/conc#927.itm}
+load net {ACC1:exs#1523.itm(0)} -attr vt d
+load net {ACC1:exs#1523.itm(1)} -attr vt d
+load net {ACC1:exs#1523.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1523.itm} 3 {ACC1:exs#1523.itm(0)} {ACC1:exs#1523.itm(1)} {ACC1:exs#1523.itm(2)} -attr xrf 52339 -attr oid 395 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1523.itm}
+load net {ACC1:conc#1349.itm(0)} -attr vt d
+load net {ACC1:conc#1349.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1349.itm} 2 {ACC1:conc#1349.itm(0)} {ACC1:conc#1349.itm(1)} -attr xrf 52340 -attr oid 396 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1349.itm}
+load net {ACC1:acc#533.itm(0)} -attr vt d
+load net {ACC1:acc#533.itm(1)} -attr vt d
+load net {ACC1:acc#533.itm(2)} -attr vt d
+load net {ACC1:acc#533.itm(3)} -attr vt d
+load netBundle {ACC1:acc#533.itm} 4 {ACC1:acc#533.itm(0)} {ACC1:acc#533.itm(1)} {ACC1:acc#533.itm(2)} {ACC1:acc#533.itm(3)} -attr xrf 52341 -attr oid 397 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:slc#112.itm(0)} -attr vt d
+load net {ACC1:slc#112.itm(1)} -attr vt d
+load net {ACC1:slc#112.itm(2)} -attr vt d
+load netBundle {ACC1:slc#112.itm} 3 {ACC1:slc#112.itm(0)} {ACC1:slc#112.itm(1)} {ACC1:slc#112.itm(2)} -attr xrf 52342 -attr oid 398 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#112.itm}
+load net {ACC1:acc#444.itm(0)} -attr vt d
+load net {ACC1:acc#444.itm(1)} -attr vt d
+load net {ACC1:acc#444.itm(2)} -attr vt d
+load net {ACC1:acc#444.itm(3)} -attr vt d
+load netBundle {ACC1:acc#444.itm} 4 {ACC1:acc#444.itm(0)} {ACC1:acc#444.itm(1)} {ACC1:acc#444.itm(2)} {ACC1:acc#444.itm(3)} -attr xrf 52343 -attr oid 399 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#444.itm}
+load net {exs#67.itm(0)} -attr vt d
+load net {exs#67.itm(1)} -attr vt d
+load net {exs#67.itm(2)} -attr vt d
+load netBundle {exs#67.itm} 3 {exs#67.itm(0)} {exs#67.itm(1)} {exs#67.itm(2)} -attr xrf 52344 -attr oid 400 -attr vt d -attr @path {/sobel/sobel:core/exs#67.itm}
+load net {conc#929.itm(0)} -attr vt d
+load net {conc#929.itm(1)} -attr vt d
+load netBundle {conc#929.itm} 2 {conc#929.itm(0)} {conc#929.itm(1)} -attr xrf 52345 -attr oid 401 -attr vt d -attr @path {/sobel/sobel:core/conc#929.itm}
+load net {ACC1:exs#1525.itm(0)} -attr vt d
+load net {ACC1:exs#1525.itm(1)} -attr vt d
+load net {ACC1:exs#1525.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1525.itm} 3 {ACC1:exs#1525.itm(0)} {ACC1:exs#1525.itm(1)} {ACC1:exs#1525.itm(2)} -attr xrf 52346 -attr oid 402 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1525.itm}
+load net {ACC1:conc#1347.itm(0)} -attr vt d
+load net {ACC1:conc#1347.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1347.itm} 2 {ACC1:conc#1347.itm(0)} {ACC1:conc#1347.itm(1)} -attr xrf 52347 -attr oid 403 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1347.itm}
+load net {ACC1:slc#110.itm(0)} -attr vt d
+load net {ACC1:slc#110.itm(1)} -attr vt d
+load net {ACC1:slc#110.itm(2)} -attr vt d
+load netBundle {ACC1:slc#110.itm} 3 {ACC1:slc#110.itm(0)} {ACC1:slc#110.itm(1)} {ACC1:slc#110.itm(2)} -attr xrf 52348 -attr oid 404 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#110.itm}
+load net {ACC1:acc#442.itm(0)} -attr vt d
+load net {ACC1:acc#442.itm(1)} -attr vt d
+load net {ACC1:acc#442.itm(2)} -attr vt d
+load net {ACC1:acc#442.itm(3)} -attr vt d
+load netBundle {ACC1:acc#442.itm} 4 {ACC1:acc#442.itm(0)} {ACC1:acc#442.itm(1)} {ACC1:acc#442.itm(2)} {ACC1:acc#442.itm(3)} -attr xrf 52349 -attr oid 405 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#442.itm}
+load net {exs#68.itm(0)} -attr vt d
+load net {exs#68.itm(1)} -attr vt d
+load net {exs#68.itm(2)} -attr vt d
+load netBundle {exs#68.itm} 3 {exs#68.itm(0)} {exs#68.itm(1)} {exs#68.itm(2)} -attr xrf 52350 -attr oid 406 -attr vt d -attr @path {/sobel/sobel:core/exs#68.itm}
+load net {conc#930.itm(0)} -attr vt d
+load net {conc#930.itm(1)} -attr vt d
+load netBundle {conc#930.itm} 2 {conc#930.itm(0)} {conc#930.itm(1)} -attr xrf 52351 -attr oid 407 -attr vt d -attr @path {/sobel/sobel:core/conc#930.itm}
+load net {ACC1:exs#1527.itm(0)} -attr vt d
+load net {ACC1:exs#1527.itm(1)} -attr vt d
+load net {ACC1:exs#1527.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1527.itm} 3 {ACC1:exs#1527.itm(0)} {ACC1:exs#1527.itm(1)} {ACC1:exs#1527.itm(2)} -attr xrf 52352 -attr oid 408 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1527.itm}
+load net {ACC1:conc#1343.itm(0)} -attr vt d
+load net {ACC1:conc#1343.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1343.itm} 2 {ACC1:conc#1343.itm(0)} {ACC1:conc#1343.itm(1)} -attr xrf 52353 -attr oid 409 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1343.itm}
+load net {ACC1:acc#622.itm(0)} -attr vt d
+load net {ACC1:acc#622.itm(1)} -attr vt d
+load net {ACC1:acc#622.itm(2)} -attr vt d
+load net {ACC1:acc#622.itm(3)} -attr vt d
+load net {ACC1:acc#622.itm(4)} -attr vt d
+load net {ACC1:acc#622.itm(5)} -attr vt d
+load net {ACC1:acc#622.itm(6)} -attr vt d
+load netBundle {ACC1:acc#622.itm} 7 {ACC1:acc#622.itm(0)} {ACC1:acc#622.itm(1)} {ACC1:acc#622.itm(2)} {ACC1:acc#622.itm(3)} {ACC1:acc#622.itm(4)} {ACC1:acc#622.itm(5)} {ACC1:acc#622.itm(6)} -attr xrf 52354 -attr oid 410 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#605.itm(0)} -attr vt d
+load net {ACC1:acc#605.itm(1)} -attr vt d
+load net {ACC1:acc#605.itm(2)} -attr vt d
+load net {ACC1:acc#605.itm(3)} -attr vt d
+load net {ACC1:acc#605.itm(4)} -attr vt d
+load net {ACC1:acc#605.itm(5)} -attr vt d
+load netBundle {ACC1:acc#605.itm} 6 {ACC1:acc#605.itm(0)} {ACC1:acc#605.itm(1)} {ACC1:acc#605.itm(2)} {ACC1:acc#605.itm(3)} {ACC1:acc#605.itm(4)} {ACC1:acc#605.itm(5)} -attr xrf 52355 -attr oid 411 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#581.itm(0)} -attr vt d
+load net {ACC1:acc#581.itm(1)} -attr vt d
+load net {ACC1:acc#581.itm(2)} -attr vt d
+load net {ACC1:acc#581.itm(3)} -attr vt d
+load net {ACC1:acc#581.itm(4)} -attr vt d
+load netBundle {ACC1:acc#581.itm} 5 {ACC1:acc#581.itm(0)} {ACC1:acc#581.itm(1)} {ACC1:acc#581.itm(2)} {ACC1:acc#581.itm(3)} {ACC1:acc#581.itm(4)} -attr xrf 52356 -attr oid 412 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#532.itm(0)} -attr vt d
+load net {ACC1:acc#532.itm(1)} -attr vt d
+load net {ACC1:acc#532.itm(2)} -attr vt d
+load net {ACC1:acc#532.itm(3)} -attr vt d
+load netBundle {ACC1:acc#532.itm} 4 {ACC1:acc#532.itm(0)} {ACC1:acc#532.itm(1)} {ACC1:acc#532.itm(2)} {ACC1:acc#532.itm(3)} -attr xrf 52357 -attr oid 413 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:slc#109.itm(0)} -attr vt d
+load net {ACC1:slc#109.itm(1)} -attr vt d
+load net {ACC1:slc#109.itm(2)} -attr vt d
+load netBundle {ACC1:slc#109.itm} 3 {ACC1:slc#109.itm(0)} {ACC1:slc#109.itm(1)} {ACC1:slc#109.itm(2)} -attr xrf 52358 -attr oid 414 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#109.itm}
+load net {ACC1:acc#441.itm(0)} -attr vt d
+load net {ACC1:acc#441.itm(1)} -attr vt d
+load net {ACC1:acc#441.itm(2)} -attr vt d
+load net {ACC1:acc#441.itm(3)} -attr vt d
+load netBundle {ACC1:acc#441.itm} 4 {ACC1:acc#441.itm(0)} {ACC1:acc#441.itm(1)} {ACC1:acc#441.itm(2)} {ACC1:acc#441.itm(3)} -attr xrf 52359 -attr oid 415 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#441.itm}
+load net {exs#69.itm(0)} -attr vt d
+load net {exs#69.itm(1)} -attr vt d
+load net {exs#69.itm(2)} -attr vt d
+load netBundle {exs#69.itm} 3 {exs#69.itm(0)} {exs#69.itm(1)} {exs#69.itm(2)} -attr xrf 52360 -attr oid 416 -attr vt d -attr @path {/sobel/sobel:core/exs#69.itm}
+load net {conc#931.itm(0)} -attr vt d
+load net {conc#931.itm(1)} -attr vt d
+load netBundle {conc#931.itm} 2 {conc#931.itm(0)} {conc#931.itm(1)} -attr xrf 52361 -attr oid 417 -attr vt d -attr @path {/sobel/sobel:core/conc#931.itm}
+load net {ACC1:exs#1529.itm(0)} -attr vt d
+load net {ACC1:exs#1529.itm(1)} -attr vt d
+load net {ACC1:exs#1529.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1529.itm} 3 {ACC1:exs#1529.itm(0)} {ACC1:exs#1529.itm(1)} {ACC1:exs#1529.itm(2)} -attr xrf 52362 -attr oid 418 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1529.itm}
+load net {ACC1:conc#1341.itm(0)} -attr vt d
+load net {ACC1:conc#1341.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1341.itm} 2 {ACC1:conc#1341.itm(0)} {ACC1:conc#1341.itm(1)} -attr xrf 52363 -attr oid 419 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1341.itm}
+load net {ACC1:slc#108.itm(0)} -attr vt d
+load net {ACC1:slc#108.itm(1)} -attr vt d
+load net {ACC1:slc#108.itm(2)} -attr vt d
+load netBundle {ACC1:slc#108.itm} 3 {ACC1:slc#108.itm(0)} {ACC1:slc#108.itm(1)} {ACC1:slc#108.itm(2)} -attr xrf 52364 -attr oid 420 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#108.itm}
+load net {ACC1:acc#440.itm(0)} -attr vt d
+load net {ACC1:acc#440.itm(1)} -attr vt d
+load net {ACC1:acc#440.itm(2)} -attr vt d
+load net {ACC1:acc#440.itm(3)} -attr vt d
+load netBundle {ACC1:acc#440.itm} 4 {ACC1:acc#440.itm(0)} {ACC1:acc#440.itm(1)} {ACC1:acc#440.itm(2)} {ACC1:acc#440.itm(3)} -attr xrf 52365 -attr oid 421 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#440.itm}
+load net {exs#70.itm(0)} -attr vt d
+load net {exs#70.itm(1)} -attr vt d
+load net {exs#70.itm(2)} -attr vt d
+load netBundle {exs#70.itm} 3 {exs#70.itm(0)} {exs#70.itm(1)} {exs#70.itm(2)} -attr xrf 52366 -attr oid 422 -attr vt d -attr @path {/sobel/sobel:core/exs#70.itm}
+load net {conc#932.itm(0)} -attr vt d
+load net {conc#932.itm(1)} -attr vt d
+load netBundle {conc#932.itm} 2 {conc#932.itm(0)} {conc#932.itm(1)} -attr xrf 52367 -attr oid 423 -attr vt d -attr @path {/sobel/sobel:core/conc#932.itm}
+load net {ACC1:exs#1531.itm(0)} -attr vt d
+load net {ACC1:exs#1531.itm(1)} -attr vt d
+load net {ACC1:exs#1531.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1531.itm} 3 {ACC1:exs#1531.itm(0)} {ACC1:exs#1531.itm(1)} {ACC1:exs#1531.itm(2)} -attr xrf 52368 -attr oid 424 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1531.itm}
+load net {ACC1:conc#1339.itm(0)} -attr vt d
+load net {ACC1:conc#1339.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1339.itm} 2 {ACC1:conc#1339.itm(0)} {ACC1:conc#1339.itm(1)} -attr xrf 52369 -attr oid 425 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1339.itm}
+load net {ACC1:acc#531.itm(0)} -attr vt d
+load net {ACC1:acc#531.itm(1)} -attr vt d
+load net {ACC1:acc#531.itm(2)} -attr vt d
+load net {ACC1:acc#531.itm(3)} -attr vt d
+load netBundle {ACC1:acc#531.itm} 4 {ACC1:acc#531.itm(0)} {ACC1:acc#531.itm(1)} {ACC1:acc#531.itm(2)} {ACC1:acc#531.itm(3)} -attr xrf 52370 -attr oid 426 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:slc#107.itm(0)} -attr vt d
+load net {ACC1:slc#107.itm(1)} -attr vt d
+load net {ACC1:slc#107.itm(2)} -attr vt d
+load netBundle {ACC1:slc#107.itm} 3 {ACC1:slc#107.itm(0)} {ACC1:slc#107.itm(1)} {ACC1:slc#107.itm(2)} -attr xrf 52371 -attr oid 427 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#107.itm}
+load net {ACC1:acc#439.itm(0)} -attr vt d
+load net {ACC1:acc#439.itm(1)} -attr vt d
+load net {ACC1:acc#439.itm(2)} -attr vt d
+load net {ACC1:acc#439.itm(3)} -attr vt d
+load netBundle {ACC1:acc#439.itm} 4 {ACC1:acc#439.itm(0)} {ACC1:acc#439.itm(1)} {ACC1:acc#439.itm(2)} {ACC1:acc#439.itm(3)} -attr xrf 52372 -attr oid 428 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#439.itm}
+load net {exs#71.itm(0)} -attr vt d
+load net {exs#71.itm(1)} -attr vt d
+load net {exs#71.itm(2)} -attr vt d
+load netBundle {exs#71.itm} 3 {exs#71.itm(0)} {exs#71.itm(1)} {exs#71.itm(2)} -attr xrf 52373 -attr oid 429 -attr vt d -attr @path {/sobel/sobel:core/exs#71.itm}
+load net {conc#933.itm(0)} -attr vt d
+load net {conc#933.itm(1)} -attr vt d
+load netBundle {conc#933.itm} 2 {conc#933.itm(0)} {conc#933.itm(1)} -attr xrf 52374 -attr oid 430 -attr vt d -attr @path {/sobel/sobel:core/conc#933.itm}
+load net {ACC1:exs#1533.itm(0)} -attr vt d
+load net {ACC1:exs#1533.itm(1)} -attr vt d
+load net {ACC1:exs#1533.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1533.itm} 3 {ACC1:exs#1533.itm(0)} {ACC1:exs#1533.itm(1)} {ACC1:exs#1533.itm(2)} -attr xrf 52375 -attr oid 431 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1533.itm}
+load net {ACC1:conc#1337.itm(0)} -attr vt d
+load net {ACC1:conc#1337.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1337.itm} 2 {ACC1:conc#1337.itm(0)} {ACC1:conc#1337.itm(1)} -attr xrf 52376 -attr oid 432 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1337.itm}
+load net {ACC1:slc#106.itm(0)} -attr vt d
+load net {ACC1:slc#106.itm(1)} -attr vt d
+load net {ACC1:slc#106.itm(2)} -attr vt d
+load netBundle {ACC1:slc#106.itm} 3 {ACC1:slc#106.itm(0)} {ACC1:slc#106.itm(1)} {ACC1:slc#106.itm(2)} -attr xrf 52377 -attr oid 433 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#106.itm}
+load net {ACC1:acc#438.itm(0)} -attr vt d
+load net {ACC1:acc#438.itm(1)} -attr vt d
+load net {ACC1:acc#438.itm(2)} -attr vt d
+load net {ACC1:acc#438.itm(3)} -attr vt d
+load netBundle {ACC1:acc#438.itm} 4 {ACC1:acc#438.itm(0)} {ACC1:acc#438.itm(1)} {ACC1:acc#438.itm(2)} {ACC1:acc#438.itm(3)} -attr xrf 52378 -attr oid 434 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#438.itm}
+load net {exs#72.itm(0)} -attr vt d
+load net {exs#72.itm(1)} -attr vt d
+load net {exs#72.itm(2)} -attr vt d
+load netBundle {exs#72.itm} 3 {exs#72.itm(0)} {exs#72.itm(1)} {exs#72.itm(2)} -attr xrf 52379 -attr oid 435 -attr vt d -attr @path {/sobel/sobel:core/exs#72.itm}
+load net {conc#934.itm(0)} -attr vt d
+load net {conc#934.itm(1)} -attr vt d
+load netBundle {conc#934.itm} 2 {conc#934.itm(0)} {conc#934.itm(1)} -attr xrf 52380 -attr oid 436 -attr vt d -attr @path {/sobel/sobel:core/conc#934.itm}
+load net {ACC1:exs#1535.itm(0)} -attr vt d
+load net {ACC1:exs#1535.itm(1)} -attr vt d
+load net {ACC1:exs#1535.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1535.itm} 3 {ACC1:exs#1535.itm(0)} {ACC1:exs#1535.itm(1)} {ACC1:exs#1535.itm(2)} -attr xrf 52381 -attr oid 437 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1535.itm}
+load net {ACC1:conc#1335.itm(0)} -attr vt d
+load net {ACC1:conc#1335.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1335.itm} 2 {ACC1:conc#1335.itm(0)} {ACC1:conc#1335.itm(1)} -attr xrf 52382 -attr oid 438 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1335.itm}
+load net {ACC1:acc#580.itm(0)} -attr vt d
+load net {ACC1:acc#580.itm(1)} -attr vt d
+load net {ACC1:acc#580.itm(2)} -attr vt d
+load net {ACC1:acc#580.itm(3)} -attr vt d
+load net {ACC1:acc#580.itm(4)} -attr vt d
+load netBundle {ACC1:acc#580.itm} 5 {ACC1:acc#580.itm(0)} {ACC1:acc#580.itm(1)} {ACC1:acc#580.itm(2)} {ACC1:acc#580.itm(3)} {ACC1:acc#580.itm(4)} -attr xrf 52383 -attr oid 439 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#530.itm(0)} -attr vt d
+load net {ACC1:acc#530.itm(1)} -attr vt d
+load net {ACC1:acc#530.itm(2)} -attr vt d
+load net {ACC1:acc#530.itm(3)} -attr vt d
+load netBundle {ACC1:acc#530.itm} 4 {ACC1:acc#530.itm(0)} {ACC1:acc#530.itm(1)} {ACC1:acc#530.itm(2)} {ACC1:acc#530.itm(3)} -attr xrf 52384 -attr oid 440 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:slc#105.itm(0)} -attr vt d
+load net {ACC1:slc#105.itm(1)} -attr vt d
+load net {ACC1:slc#105.itm(2)} -attr vt d
+load netBundle {ACC1:slc#105.itm} 3 {ACC1:slc#105.itm(0)} {ACC1:slc#105.itm(1)} {ACC1:slc#105.itm(2)} -attr xrf 52385 -attr oid 441 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#105.itm}
+load net {ACC1:acc#437.itm(0)} -attr vt d
+load net {ACC1:acc#437.itm(1)} -attr vt d
+load net {ACC1:acc#437.itm(2)} -attr vt d
+load net {ACC1:acc#437.itm(3)} -attr vt d
+load netBundle {ACC1:acc#437.itm} 4 {ACC1:acc#437.itm(0)} {ACC1:acc#437.itm(1)} {ACC1:acc#437.itm(2)} {ACC1:acc#437.itm(3)} -attr xrf 52386 -attr oid 442 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#437.itm}
+load net {exs#73.itm(0)} -attr vt d
+load net {exs#73.itm(1)} -attr vt d
+load net {exs#73.itm(2)} -attr vt d
+load netBundle {exs#73.itm} 3 {exs#73.itm(0)} {exs#73.itm(1)} {exs#73.itm(2)} -attr xrf 52387 -attr oid 443 -attr vt d -attr @path {/sobel/sobel:core/exs#73.itm}
+load net {conc#935.itm(0)} -attr vt d
+load net {conc#935.itm(1)} -attr vt d
+load netBundle {conc#935.itm} 2 {conc#935.itm(0)} {conc#935.itm(1)} -attr xrf 52388 -attr oid 444 -attr vt d -attr @path {/sobel/sobel:core/conc#935.itm}
+load net {ACC1:exs#1537.itm(0)} -attr vt d
+load net {ACC1:exs#1537.itm(1)} -attr vt d
+load net {ACC1:exs#1537.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1537.itm} 3 {ACC1:exs#1537.itm(0)} {ACC1:exs#1537.itm(1)} {ACC1:exs#1537.itm(2)} -attr xrf 52389 -attr oid 445 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1537.itm}
+load net {ACC1:conc#1333.itm(0)} -attr vt d
+load net {ACC1:conc#1333.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1333.itm} 2 {ACC1:conc#1333.itm(0)} {ACC1:conc#1333.itm(1)} -attr xrf 52390 -attr oid 446 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1333.itm}
+load net {ACC1:slc#104.itm(0)} -attr vt d
+load net {ACC1:slc#104.itm(1)} -attr vt d
+load net {ACC1:slc#104.itm(2)} -attr vt d
+load netBundle {ACC1:slc#104.itm} 3 {ACC1:slc#104.itm(0)} {ACC1:slc#104.itm(1)} {ACC1:slc#104.itm(2)} -attr xrf 52391 -attr oid 447 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#104.itm}
+load net {ACC1:acc#436.itm(0)} -attr vt d
+load net {ACC1:acc#436.itm(1)} -attr vt d
+load net {ACC1:acc#436.itm(2)} -attr vt d
+load net {ACC1:acc#436.itm(3)} -attr vt d
+load netBundle {ACC1:acc#436.itm} 4 {ACC1:acc#436.itm(0)} {ACC1:acc#436.itm(1)} {ACC1:acc#436.itm(2)} {ACC1:acc#436.itm(3)} -attr xrf 52392 -attr oid 448 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#436.itm}
+load net {exs#74.itm(0)} -attr vt d
+load net {exs#74.itm(1)} -attr vt d
+load net {exs#74.itm(2)} -attr vt d
+load netBundle {exs#74.itm} 3 {exs#74.itm(0)} {exs#74.itm(1)} {exs#74.itm(2)} -attr xrf 52393 -attr oid 449 -attr vt d -attr @path {/sobel/sobel:core/exs#74.itm}
+load net {conc#936.itm(0)} -attr vt d
+load net {conc#936.itm(1)} -attr vt d
+load netBundle {conc#936.itm} 2 {conc#936.itm(0)} {conc#936.itm(1)} -attr xrf 52394 -attr oid 450 -attr vt d -attr @path {/sobel/sobel:core/conc#936.itm}
+load net {ACC1:exs#1539.itm(0)} -attr vt d
+load net {ACC1:exs#1539.itm(1)} -attr vt d
+load net {ACC1:exs#1539.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1539.itm} 3 {ACC1:exs#1539.itm(0)} {ACC1:exs#1539.itm(1)} {ACC1:exs#1539.itm(2)} -attr xrf 52395 -attr oid 451 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1539.itm}
+load net {ACC1:conc#1331.itm(0)} -attr vt d
+load net {ACC1:conc#1331.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1331.itm} 2 {ACC1:conc#1331.itm(0)} {ACC1:conc#1331.itm(1)} -attr xrf 52396 -attr oid 452 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1331.itm}
+load net {ACC1:acc#529.itm(0)} -attr vt d
+load net {ACC1:acc#529.itm(1)} -attr vt d
+load net {ACC1:acc#529.itm(2)} -attr vt d
+load net {ACC1:acc#529.itm(3)} -attr vt d
+load netBundle {ACC1:acc#529.itm} 4 {ACC1:acc#529.itm(0)} {ACC1:acc#529.itm(1)} {ACC1:acc#529.itm(2)} {ACC1:acc#529.itm(3)} -attr xrf 52397 -attr oid 453 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:slc#103.itm(0)} -attr vt d
+load net {ACC1:slc#103.itm(1)} -attr vt d
+load net {ACC1:slc#103.itm(2)} -attr vt d
+load netBundle {ACC1:slc#103.itm} 3 {ACC1:slc#103.itm(0)} {ACC1:slc#103.itm(1)} {ACC1:slc#103.itm(2)} -attr xrf 52398 -attr oid 454 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#103.itm}
+load net {ACC1:acc#435.itm(0)} -attr vt d
+load net {ACC1:acc#435.itm(1)} -attr vt d
+load net {ACC1:acc#435.itm(2)} -attr vt d
+load net {ACC1:acc#435.itm(3)} -attr vt d
+load netBundle {ACC1:acc#435.itm} 4 {ACC1:acc#435.itm(0)} {ACC1:acc#435.itm(1)} {ACC1:acc#435.itm(2)} {ACC1:acc#435.itm(3)} -attr xrf 52399 -attr oid 455 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#435.itm}
+load net {exs#75.itm(0)} -attr vt d
+load net {exs#75.itm(1)} -attr vt d
+load net {exs#75.itm(2)} -attr vt d
+load netBundle {exs#75.itm} 3 {exs#75.itm(0)} {exs#75.itm(1)} {exs#75.itm(2)} -attr xrf 52400 -attr oid 456 -attr vt d -attr @path {/sobel/sobel:core/exs#75.itm}
+load net {conc#937.itm(0)} -attr vt d
+load net {conc#937.itm(1)} -attr vt d
+load netBundle {conc#937.itm} 2 {conc#937.itm(0)} {conc#937.itm(1)} -attr xrf 52401 -attr oid 457 -attr vt d -attr @path {/sobel/sobel:core/conc#937.itm}
+load net {ACC1:exs#1541.itm(0)} -attr vt d
+load net {ACC1:exs#1541.itm(1)} -attr vt d
+load net {ACC1:exs#1541.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1541.itm} 3 {ACC1:exs#1541.itm(0)} {ACC1:exs#1541.itm(1)} {ACC1:exs#1541.itm(2)} -attr xrf 52402 -attr oid 458 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1541.itm}
+load net {ACC1:conc#1329.itm(0)} -attr vt d
+load net {ACC1:conc#1329.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1329.itm} 2 {ACC1:conc#1329.itm(0)} {ACC1:conc#1329.itm(1)} -attr xrf 52403 -attr oid 459 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1329.itm}
+load net {ACC1:slc#102.itm(0)} -attr vt d
+load net {ACC1:slc#102.itm(1)} -attr vt d
+load net {ACC1:slc#102.itm(2)} -attr vt d
+load netBundle {ACC1:slc#102.itm} 3 {ACC1:slc#102.itm(0)} {ACC1:slc#102.itm(1)} {ACC1:slc#102.itm(2)} -attr xrf 52404 -attr oid 460 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#102.itm}
+load net {ACC1:acc#434.itm(0)} -attr vt d
+load net {ACC1:acc#434.itm(1)} -attr vt d
+load net {ACC1:acc#434.itm(2)} -attr vt d
+load net {ACC1:acc#434.itm(3)} -attr vt d
+load netBundle {ACC1:acc#434.itm} 4 {ACC1:acc#434.itm(0)} {ACC1:acc#434.itm(1)} {ACC1:acc#434.itm(2)} {ACC1:acc#434.itm(3)} -attr xrf 52405 -attr oid 461 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#434.itm}
+load net {exs#76.itm(0)} -attr vt d
+load net {exs#76.itm(1)} -attr vt d
+load net {exs#76.itm(2)} -attr vt d
+load netBundle {exs#76.itm} 3 {exs#76.itm(0)} {exs#76.itm(1)} {exs#76.itm(2)} -attr xrf 52406 -attr oid 462 -attr vt d -attr @path {/sobel/sobel:core/exs#76.itm}
+load net {conc#938.itm(0)} -attr vt d
+load net {conc#938.itm(1)} -attr vt d
+load netBundle {conc#938.itm} 2 {conc#938.itm(0)} {conc#938.itm(1)} -attr xrf 52407 -attr oid 463 -attr vt d -attr @path {/sobel/sobel:core/conc#938.itm}
+load net {ACC1:exs#1543.itm(0)} -attr vt d
+load net {ACC1:exs#1543.itm(1)} -attr vt d
+load net {ACC1:exs#1543.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1543.itm} 3 {ACC1:exs#1543.itm(0)} {ACC1:exs#1543.itm(1)} {ACC1:exs#1543.itm(2)} -attr xrf 52408 -attr oid 464 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1543.itm}
+load net {ACC1:conc#1327.itm(0)} -attr vt d
+load net {ACC1:conc#1327.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1327.itm} 2 {ACC1:conc#1327.itm(0)} {ACC1:conc#1327.itm(1)} -attr xrf 52409 -attr oid 465 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1327.itm}
+load net {ACC1:acc#604.itm(0)} -attr vt d
+load net {ACC1:acc#604.itm(1)} -attr vt d
+load net {ACC1:acc#604.itm(2)} -attr vt d
+load net {ACC1:acc#604.itm(3)} -attr vt d
+load net {ACC1:acc#604.itm(4)} -attr vt d
+load net {ACC1:acc#604.itm(5)} -attr vt d
+load netBundle {ACC1:acc#604.itm} 6 {ACC1:acc#604.itm(0)} {ACC1:acc#604.itm(1)} {ACC1:acc#604.itm(2)} {ACC1:acc#604.itm(3)} {ACC1:acc#604.itm(4)} {ACC1:acc#604.itm(5)} -attr xrf 52410 -attr oid 466 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#579.itm(0)} -attr vt d
+load net {ACC1:acc#579.itm(1)} -attr vt d
+load net {ACC1:acc#579.itm(2)} -attr vt d
+load net {ACC1:acc#579.itm(3)} -attr vt d
+load net {ACC1:acc#579.itm(4)} -attr vt d
+load netBundle {ACC1:acc#579.itm} 5 {ACC1:acc#579.itm(0)} {ACC1:acc#579.itm(1)} {ACC1:acc#579.itm(2)} {ACC1:acc#579.itm(3)} {ACC1:acc#579.itm(4)} -attr xrf 52411 -attr oid 467 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#528.itm(0)} -attr vt d
+load net {ACC1:acc#528.itm(1)} -attr vt d
+load net {ACC1:acc#528.itm(2)} -attr vt d
+load net {ACC1:acc#528.itm(3)} -attr vt d
+load netBundle {ACC1:acc#528.itm} 4 {ACC1:acc#528.itm(0)} {ACC1:acc#528.itm(1)} {ACC1:acc#528.itm(2)} {ACC1:acc#528.itm(3)} -attr xrf 52412 -attr oid 468 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:slc#101.itm(0)} -attr vt d
+load net {ACC1:slc#101.itm(1)} -attr vt d
+load net {ACC1:slc#101.itm(2)} -attr vt d
+load netBundle {ACC1:slc#101.itm} 3 {ACC1:slc#101.itm(0)} {ACC1:slc#101.itm(1)} {ACC1:slc#101.itm(2)} -attr xrf 52413 -attr oid 469 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#101.itm}
+load net {ACC1:acc#433.itm(0)} -attr vt d
+load net {ACC1:acc#433.itm(1)} -attr vt d
+load net {ACC1:acc#433.itm(2)} -attr vt d
+load net {ACC1:acc#433.itm(3)} -attr vt d
+load netBundle {ACC1:acc#433.itm} 4 {ACC1:acc#433.itm(0)} {ACC1:acc#433.itm(1)} {ACC1:acc#433.itm(2)} {ACC1:acc#433.itm(3)} -attr xrf 52414 -attr oid 470 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#433.itm}
+load net {conc#939.itm(0)} -attr vt d
+load net {conc#939.itm(1)} -attr vt d
+load net {conc#939.itm(2)} -attr vt d
+load netBundle {conc#939.itm} 3 {conc#939.itm(0)} {conc#939.itm(1)} {conc#939.itm(2)} -attr xrf 52415 -attr oid 471 -attr vt d -attr @path {/sobel/sobel:core/conc#939.itm}
+load net {ACC1:conc#1325.itm(0)} -attr vt d
+load net {ACC1:conc#1325.itm(1)} -attr vt d
+load net {ACC1:conc#1325.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1325.itm} 3 {ACC1:conc#1325.itm(0)} {ACC1:conc#1325.itm(1)} {ACC1:conc#1325.itm(2)} -attr xrf 52416 -attr oid 472 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1325.itm}
+load net {ACC1:slc#100.itm(0)} -attr vt d
+load net {ACC1:slc#100.itm(1)} -attr vt d
+load net {ACC1:slc#100.itm(2)} -attr vt d
+load netBundle {ACC1:slc#100.itm} 3 {ACC1:slc#100.itm(0)} {ACC1:slc#100.itm(1)} {ACC1:slc#100.itm(2)} -attr xrf 52417 -attr oid 473 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#100.itm}
+load net {ACC1:acc#432.itm(0)} -attr vt d
+load net {ACC1:acc#432.itm(1)} -attr vt d
+load net {ACC1:acc#432.itm(2)} -attr vt d
+load net {ACC1:acc#432.itm(3)} -attr vt d
+load netBundle {ACC1:acc#432.itm} 4 {ACC1:acc#432.itm(0)} {ACC1:acc#432.itm(1)} {ACC1:acc#432.itm(2)} {ACC1:acc#432.itm(3)} -attr xrf 52418 -attr oid 474 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#432.itm}
+load net {conc#940.itm(0)} -attr vt d
+load net {conc#940.itm(1)} -attr vt d
+load net {conc#940.itm(2)} -attr vt d
+load netBundle {conc#940.itm} 3 {conc#940.itm(0)} {conc#940.itm(1)} {conc#940.itm(2)} -attr xrf 52419 -attr oid 475 -attr vt d -attr @path {/sobel/sobel:core/conc#940.itm}
+load net {ACC1:conc#1323.itm(0)} -attr vt d
+load net {ACC1:conc#1323.itm(1)} -attr vt d
+load net {ACC1:conc#1323.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1323.itm} 3 {ACC1:conc#1323.itm(0)} {ACC1:conc#1323.itm(1)} {ACC1:conc#1323.itm(2)} -attr xrf 52420 -attr oid 476 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1323.itm}
+load net {ACC1:acc#527.itm(0)} -attr vt d
+load net {ACC1:acc#527.itm(1)} -attr vt d
+load net {ACC1:acc#527.itm(2)} -attr vt d
+load net {ACC1:acc#527.itm(3)} -attr vt d
+load netBundle {ACC1:acc#527.itm} 4 {ACC1:acc#527.itm(0)} {ACC1:acc#527.itm(1)} {ACC1:acc#527.itm(2)} {ACC1:acc#527.itm(3)} -attr xrf 52421 -attr oid 477 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:slc#99.itm(0)} -attr vt d
+load net {ACC1:slc#99.itm(1)} -attr vt d
+load net {ACC1:slc#99.itm(2)} -attr vt d
+load netBundle {ACC1:slc#99.itm} 3 {ACC1:slc#99.itm(0)} {ACC1:slc#99.itm(1)} {ACC1:slc#99.itm(2)} -attr xrf 52422 -attr oid 478 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#431.itm(0)} -attr vt d
+load net {ACC1:acc#431.itm(1)} -attr vt d
+load net {ACC1:acc#431.itm(2)} -attr vt d
+load net {ACC1:acc#431.itm(3)} -attr vt d
+load netBundle {ACC1:acc#431.itm} 4 {ACC1:acc#431.itm(0)} {ACC1:acc#431.itm(1)} {ACC1:acc#431.itm(2)} {ACC1:acc#431.itm(3)} -attr xrf 52423 -attr oid 479 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#431.itm}
+load net {conc#941.itm(0)} -attr vt d
+load net {conc#941.itm(1)} -attr vt d
+load net {conc#941.itm(2)} -attr vt d
+load netBundle {conc#941.itm} 3 {conc#941.itm(0)} {conc#941.itm(1)} {conc#941.itm(2)} -attr xrf 52424 -attr oid 480 -attr vt d -attr @path {/sobel/sobel:core/conc#941.itm}
+load net {ACC1:conc#1321.itm(0)} -attr vt d
+load net {ACC1:conc#1321.itm(1)} -attr vt d
+load net {ACC1:conc#1321.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1321.itm} 3 {ACC1:conc#1321.itm(0)} {ACC1:conc#1321.itm(1)} {ACC1:conc#1321.itm(2)} -attr xrf 52425 -attr oid 481 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1321.itm}
+load net {ACC1:slc#98.itm(0)} -attr vt d
+load net {ACC1:slc#98.itm(1)} -attr vt d
+load net {ACC1:slc#98.itm(2)} -attr vt d
+load netBundle {ACC1:slc#98.itm} 3 {ACC1:slc#98.itm(0)} {ACC1:slc#98.itm(1)} {ACC1:slc#98.itm(2)} -attr xrf 52426 -attr oid 482 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#430.itm(0)} -attr vt d
+load net {ACC1:acc#430.itm(1)} -attr vt d
+load net {ACC1:acc#430.itm(2)} -attr vt d
+load net {ACC1:acc#430.itm(3)} -attr vt d
+load netBundle {ACC1:acc#430.itm} 4 {ACC1:acc#430.itm(0)} {ACC1:acc#430.itm(1)} {ACC1:acc#430.itm(2)} {ACC1:acc#430.itm(3)} -attr xrf 52427 -attr oid 483 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#430.itm}
+load net {conc#942.itm(0)} -attr vt d
+load net {conc#942.itm(1)} -attr vt d
+load net {conc#942.itm(2)} -attr vt d
+load netBundle {conc#942.itm} 3 {conc#942.itm(0)} {conc#942.itm(1)} {conc#942.itm(2)} -attr xrf 52428 -attr oid 484 -attr vt d -attr @path {/sobel/sobel:core/conc#942.itm}
+load net {ACC1:conc#1319.itm(0)} -attr vt d
+load net {ACC1:conc#1319.itm(1)} -attr vt d
+load net {ACC1:conc#1319.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1319.itm} 3 {ACC1:conc#1319.itm(0)} {ACC1:conc#1319.itm(1)} {ACC1:conc#1319.itm(2)} -attr xrf 52429 -attr oid 485 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1319.itm}
+load net {ACC1:acc#578.itm(0)} -attr vt d
+load net {ACC1:acc#578.itm(1)} -attr vt d
+load net {ACC1:acc#578.itm(2)} -attr vt d
+load net {ACC1:acc#578.itm(3)} -attr vt d
+load net {ACC1:acc#578.itm(4)} -attr vt d
+load netBundle {ACC1:acc#578.itm} 5 {ACC1:acc#578.itm(0)} {ACC1:acc#578.itm(1)} {ACC1:acc#578.itm(2)} {ACC1:acc#578.itm(3)} {ACC1:acc#578.itm(4)} -attr xrf 52430 -attr oid 486 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#526.itm(0)} -attr vt d
+load net {ACC1:acc#526.itm(1)} -attr vt d
+load net {ACC1:acc#526.itm(2)} -attr vt d
+load net {ACC1:acc#526.itm(3)} -attr vt d
+load netBundle {ACC1:acc#526.itm} 4 {ACC1:acc#526.itm(0)} {ACC1:acc#526.itm(1)} {ACC1:acc#526.itm(2)} {ACC1:acc#526.itm(3)} -attr xrf 52431 -attr oid 487 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:slc#97.itm(0)} -attr vt d
+load net {ACC1:slc#97.itm(1)} -attr vt d
+load net {ACC1:slc#97.itm(2)} -attr vt d
+load netBundle {ACC1:slc#97.itm} 3 {ACC1:slc#97.itm(0)} {ACC1:slc#97.itm(1)} {ACC1:slc#97.itm(2)} -attr xrf 52432 -attr oid 488 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#429.itm(0)} -attr vt d
+load net {ACC1:acc#429.itm(1)} -attr vt d
+load net {ACC1:acc#429.itm(2)} -attr vt d
+load net {ACC1:acc#429.itm(3)} -attr vt d
+load netBundle {ACC1:acc#429.itm} 4 {ACC1:acc#429.itm(0)} {ACC1:acc#429.itm(1)} {ACC1:acc#429.itm(2)} {ACC1:acc#429.itm(3)} -attr xrf 52433 -attr oid 489 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#429.itm}
+load net {conc#943.itm(0)} -attr vt d
+load net {conc#943.itm(1)} -attr vt d
+load net {conc#943.itm(2)} -attr vt d
+load netBundle {conc#943.itm} 3 {conc#943.itm(0)} {conc#943.itm(1)} {conc#943.itm(2)} -attr xrf 52434 -attr oid 490 -attr vt d -attr @path {/sobel/sobel:core/conc#943.itm}
+load net {ACC1:conc#1317.itm(0)} -attr vt d
+load net {ACC1:conc#1317.itm(1)} -attr vt d
+load net {ACC1:conc#1317.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1317.itm} 3 {ACC1:conc#1317.itm(0)} {ACC1:conc#1317.itm(1)} {ACC1:conc#1317.itm(2)} -attr xrf 52435 -attr oid 491 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1317.itm}
+load net {ACC1:slc#96.itm(0)} -attr vt d
+load net {ACC1:slc#96.itm(1)} -attr vt d
+load net {ACC1:slc#96.itm(2)} -attr vt d
+load netBundle {ACC1:slc#96.itm} 3 {ACC1:slc#96.itm(0)} {ACC1:slc#96.itm(1)} {ACC1:slc#96.itm(2)} -attr xrf 52436 -attr oid 492 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#428.itm(0)} -attr vt d
+load net {ACC1:acc#428.itm(1)} -attr vt d
+load net {ACC1:acc#428.itm(2)} -attr vt d
+load net {ACC1:acc#428.itm(3)} -attr vt d
+load netBundle {ACC1:acc#428.itm} 4 {ACC1:acc#428.itm(0)} {ACC1:acc#428.itm(1)} {ACC1:acc#428.itm(2)} {ACC1:acc#428.itm(3)} -attr xrf 52437 -attr oid 493 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#428.itm}
+load net {conc#944.itm(0)} -attr vt d
+load net {conc#944.itm(1)} -attr vt d
+load net {conc#944.itm(2)} -attr vt d
+load netBundle {conc#944.itm} 3 {conc#944.itm(0)} {conc#944.itm(1)} {conc#944.itm(2)} -attr xrf 52438 -attr oid 494 -attr vt d -attr @path {/sobel/sobel:core/conc#944.itm}
+load net {ACC1:conc#1315.itm(0)} -attr vt d
+load net {ACC1:conc#1315.itm(1)} -attr vt d
+load net {ACC1:conc#1315.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1315.itm} 3 {ACC1:conc#1315.itm(0)} {ACC1:conc#1315.itm(1)} {ACC1:conc#1315.itm(2)} -attr xrf 52439 -attr oid 495 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1315.itm}
+load net {ACC1:acc#525.itm(0)} -attr vt d
+load net {ACC1:acc#525.itm(1)} -attr vt d
+load net {ACC1:acc#525.itm(2)} -attr vt d
+load net {ACC1:acc#525.itm(3)} -attr vt d
+load netBundle {ACC1:acc#525.itm} 4 {ACC1:acc#525.itm(0)} {ACC1:acc#525.itm(1)} {ACC1:acc#525.itm(2)} {ACC1:acc#525.itm(3)} -attr xrf 52440 -attr oid 496 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:slc#95.itm(0)} -attr vt d
+load net {ACC1:slc#95.itm(1)} -attr vt d
+load net {ACC1:slc#95.itm(2)} -attr vt d
+load netBundle {ACC1:slc#95.itm} 3 {ACC1:slc#95.itm(0)} {ACC1:slc#95.itm(1)} {ACC1:slc#95.itm(2)} -attr xrf 52441 -attr oid 497 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#427.itm(0)} -attr vt d
+load net {ACC1:acc#427.itm(1)} -attr vt d
+load net {ACC1:acc#427.itm(2)} -attr vt d
+load net {ACC1:acc#427.itm(3)} -attr vt d
+load netBundle {ACC1:acc#427.itm} 4 {ACC1:acc#427.itm(0)} {ACC1:acc#427.itm(1)} {ACC1:acc#427.itm(2)} {ACC1:acc#427.itm(3)} -attr xrf 52442 -attr oid 498 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#427.itm}
+load net {conc#945.itm(0)} -attr vt d
+load net {conc#945.itm(1)} -attr vt d
+load net {conc#945.itm(2)} -attr vt d
+load netBundle {conc#945.itm} 3 {conc#945.itm(0)} {conc#945.itm(1)} {conc#945.itm(2)} -attr xrf 52443 -attr oid 499 -attr vt d -attr @path {/sobel/sobel:core/conc#945.itm}
+load net {ACC1:conc#1313.itm(0)} -attr vt d
+load net {ACC1:conc#1313.itm(1)} -attr vt d
+load net {ACC1:conc#1313.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1313.itm} 3 {ACC1:conc#1313.itm(0)} {ACC1:conc#1313.itm(1)} {ACC1:conc#1313.itm(2)} -attr xrf 52444 -attr oid 500 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1313.itm}
+load net {ACC1:slc#94.itm(0)} -attr vt d
+load net {ACC1:slc#94.itm(1)} -attr vt d
+load net {ACC1:slc#94.itm(2)} -attr vt d
+load netBundle {ACC1:slc#94.itm} 3 {ACC1:slc#94.itm(0)} {ACC1:slc#94.itm(1)} {ACC1:slc#94.itm(2)} -attr xrf 52445 -attr oid 501 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#426.itm(0)} -attr vt d
+load net {ACC1:acc#426.itm(1)} -attr vt d
+load net {ACC1:acc#426.itm(2)} -attr vt d
+load net {ACC1:acc#426.itm(3)} -attr vt d
+load netBundle {ACC1:acc#426.itm} 4 {ACC1:acc#426.itm(0)} {ACC1:acc#426.itm(1)} {ACC1:acc#426.itm(2)} {ACC1:acc#426.itm(3)} -attr xrf 52446 -attr oid 502 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#426.itm}
+load net {conc#946.itm(0)} -attr vt d
+load net {conc#946.itm(1)} -attr vt d
+load net {conc#946.itm(2)} -attr vt d
+load netBundle {conc#946.itm} 3 {conc#946.itm(0)} {conc#946.itm(1)} {conc#946.itm(2)} -attr xrf 52447 -attr oid 503 -attr vt d -attr @path {/sobel/sobel:core/conc#946.itm}
+load net {ACC1:conc#1311.itm(0)} -attr vt d
+load net {ACC1:conc#1311.itm(1)} -attr vt d
+load net {ACC1:conc#1311.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1311.itm} 3 {ACC1:conc#1311.itm(0)} {ACC1:conc#1311.itm(1)} {ACC1:conc#1311.itm(2)} -attr xrf 52448 -attr oid 504 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1311.itm}
+load net {ACC1:acc#634.itm(0)} -attr vt d
+load net {ACC1:acc#634.itm(1)} -attr vt d
+load net {ACC1:acc#634.itm(2)} -attr vt d
+load net {ACC1:acc#634.itm(3)} -attr vt d
+load net {ACC1:acc#634.itm(4)} -attr vt d
+load net {ACC1:acc#634.itm(5)} -attr vt d
+load net {ACC1:acc#634.itm(6)} -attr vt d
+load net {ACC1:acc#634.itm(7)} -attr vt d
+load netBundle {ACC1:acc#634.itm} 8 {ACC1:acc#634.itm(0)} {ACC1:acc#634.itm(1)} {ACC1:acc#634.itm(2)} {ACC1:acc#634.itm(3)} {ACC1:acc#634.itm(4)} {ACC1:acc#634.itm(5)} {ACC1:acc#634.itm(6)} {ACC1:acc#634.itm(7)} -attr xrf 52449 -attr oid 505 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:conc#1452.itm(0)} -attr vt d
+load net {ACC1:conc#1452.itm(1)} -attr vt d
+load net {ACC1:conc#1452.itm(2)} -attr vt d
+load net {ACC1:conc#1452.itm(3)} -attr vt d
+load net {ACC1:conc#1452.itm(4)} -attr vt d
+load net {ACC1:conc#1452.itm(5)} -attr vt d
+load net {ACC1:conc#1452.itm(6)} -attr vt d
+load netBundle {ACC1:conc#1452.itm} 7 {ACC1:conc#1452.itm(0)} {ACC1:conc#1452.itm(1)} {ACC1:conc#1452.itm(2)} {ACC1:conc#1452.itm(3)} {ACC1:conc#1452.itm(4)} {ACC1:conc#1452.itm(5)} {ACC1:conc#1452.itm(6)} -attr xrf 52450 -attr oid 506 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#721.itm(0)} -attr vt d
+load net {ACC1:acc#721.itm(1)} -attr vt d
+load net {ACC1:acc#721.itm(2)} -attr vt d
+load net {ACC1:acc#721.itm(3)} -attr vt d
+load netBundle {ACC1:acc#721.itm} 4 {ACC1:acc#721.itm(0)} {ACC1:acc#721.itm(1)} {ACC1:acc#721.itm(2)} {ACC1:acc#721.itm(3)} -attr xrf 52451 -attr oid 507 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#721.itm}
+load net {conc#947.itm(0)} -attr vt d
+load net {conc#947.itm(1)} -attr vt d
+load net {conc#947.itm(2)} -attr vt d
+load netBundle {conc#947.itm} 3 {conc#947.itm(0)} {conc#947.itm(1)} {conc#947.itm(2)} -attr xrf 52452 -attr oid 508 -attr vt d -attr @path {/sobel/sobel:core/conc#947.itm}
+load net {ACC1:conc#1119.itm(0)} -attr vt d
+load net {ACC1:conc#1119.itm(1)} -attr vt d
+load net {ACC1:conc#1119.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1119.itm} 3 {ACC1:conc#1119.itm(0)} {ACC1:conc#1119.itm(1)} {ACC1:conc#1119.itm(2)} -attr xrf 52453 -attr oid 509 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1119.itm}
+load net {ACC1:acc#722.itm(0)} -attr vt d
+load net {ACC1:acc#722.itm(1)} -attr vt d
+load net {ACC1:acc#722.itm(2)} -attr vt d
+load netBundle {ACC1:acc#722.itm} 3 {ACC1:acc#722.itm(0)} {ACC1:acc#722.itm(1)} {ACC1:acc#722.itm(2)} -attr xrf 52454 -attr oid 510 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#722.itm}
+load net {ACC1:conc#1453.itm(0)} -attr vt d
+load net {ACC1:conc#1453.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1453.itm} 2 {ACC1:conc#1453.itm(0)} {ACC1:conc#1453.itm(1)} -attr xrf 52455 -attr oid 511 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1453.itm}
+load net {ACC1:exs#1544.itm(0)} -attr vt d
+load net {ACC1:exs#1544.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1544.itm} 2 {ACC1:exs#1544.itm(0)} {ACC1:exs#1544.itm(1)} -attr xrf 52456 -attr oid 512 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1544.itm}
+load net {ACC1:conc#1454.itm(0)} -attr vt d
+load net {ACC1:conc#1454.itm(1)} -attr vt d
+load net {ACC1:conc#1454.itm(2)} -attr vt d
+load net {ACC1:conc#1454.itm(3)} -attr vt d
+load net {ACC1:conc#1454.itm(4)} -attr vt d
+load net {ACC1:conc#1454.itm(5)} -attr vt d
+load net {ACC1:conc#1454.itm(6)} -attr vt d
+load netBundle {ACC1:conc#1454.itm} 7 {ACC1:conc#1454.itm(0)} {ACC1:conc#1454.itm(1)} {ACC1:conc#1454.itm(2)} {ACC1:conc#1454.itm(3)} {ACC1:conc#1454.itm(4)} {ACC1:conc#1454.itm(5)} {ACC1:conc#1454.itm(6)} -attr xrf 52457 -attr oid 513 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#723.itm(0)} -attr vt d
+load net {ACC1:acc#723.itm(1)} -attr vt d
+load net {ACC1:acc#723.itm(2)} -attr vt d
+load net {ACC1:acc#723.itm(3)} -attr vt d
+load netBundle {ACC1:acc#723.itm} 4 {ACC1:acc#723.itm(0)} {ACC1:acc#723.itm(1)} {ACC1:acc#723.itm(2)} {ACC1:acc#723.itm(3)} -attr xrf 52458 -attr oid 514 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#723.itm}
+load net {ACC1:conc#1120.itm(0)} -attr vt d
+load net {ACC1:conc#1120.itm(1)} -attr vt d
+load net {ACC1:conc#1120.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1120.itm} 3 {ACC1:conc#1120.itm(0)} {ACC1:conc#1120.itm(1)} {ACC1:conc#1120.itm(2)} -attr xrf 52459 -attr oid 515 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1120.itm}
+load net {conc#948.itm(0)} -attr vt d
+load net {conc#948.itm(1)} -attr vt d
+load net {conc#948.itm(2)} -attr vt d
+load netBundle {conc#948.itm} 3 {conc#948.itm(0)} {conc#948.itm(1)} {conc#948.itm(2)} -attr xrf 52460 -attr oid 516 -attr vt d -attr @path {/sobel/sobel:core/conc#948.itm}
+load net {ACC1:acc#643.itm(0)} -attr vt d
+load net {ACC1:acc#643.itm(1)} -attr vt d
+load net {ACC1:acc#643.itm(2)} -attr vt d
+load net {ACC1:acc#643.itm(3)} -attr vt d
+load net {ACC1:acc#643.itm(4)} -attr vt d
+load net {ACC1:acc#643.itm(5)} -attr vt d
+load net {ACC1:acc#643.itm(6)} -attr vt d
+load net {ACC1:acc#643.itm(7)} -attr vt d
+load net {ACC1:acc#643.itm(8)} -attr vt d
+load netBundle {ACC1:acc#643.itm} 9 {ACC1:acc#643.itm(0)} {ACC1:acc#643.itm(1)} {ACC1:acc#643.itm(2)} {ACC1:acc#643.itm(3)} {ACC1:acc#643.itm(4)} {ACC1:acc#643.itm(5)} {ACC1:acc#643.itm(6)} {ACC1:acc#643.itm(7)} {ACC1:acc#643.itm(8)} -attr xrf 52461 -attr oid 517 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#633.itm(0)} -attr vt d
+load net {ACC1:acc#633.itm(1)} -attr vt d
+load net {ACC1:acc#633.itm(2)} -attr vt d
+load net {ACC1:acc#633.itm(3)} -attr vt d
+load net {ACC1:acc#633.itm(4)} -attr vt d
+load net {ACC1:acc#633.itm(5)} -attr vt d
+load net {ACC1:acc#633.itm(6)} -attr vt d
+load net {ACC1:acc#633.itm(7)} -attr vt d
+load netBundle {ACC1:acc#633.itm} 8 {ACC1:acc#633.itm(0)} {ACC1:acc#633.itm(1)} {ACC1:acc#633.itm(2)} {ACC1:acc#633.itm(3)} {ACC1:acc#633.itm(4)} {ACC1:acc#633.itm(5)} {ACC1:acc#633.itm(6)} {ACC1:acc#633.itm(7)} -attr xrf 52462 -attr oid 518 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:conc#1455.itm(0)} -attr vt d
+load net {ACC1:conc#1455.itm(1)} -attr vt d
+load net {ACC1:conc#1455.itm(2)} -attr vt d
+load net {ACC1:conc#1455.itm(3)} -attr vt d
+load net {ACC1:conc#1455.itm(4)} -attr vt d
+load net {ACC1:conc#1455.itm(5)} -attr vt d
+load net {ACC1:conc#1455.itm(6)} -attr vt d
+load netBundle {ACC1:conc#1455.itm} 7 {ACC1:conc#1455.itm(0)} {ACC1:conc#1455.itm(1)} {ACC1:conc#1455.itm(2)} {ACC1:conc#1455.itm(3)} {ACC1:conc#1455.itm(4)} {ACC1:conc#1455.itm(5)} {ACC1:conc#1455.itm(6)} -attr xrf 52463 -attr oid 519 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#725.itm(0)} -attr vt d
+load net {ACC1:acc#725.itm(1)} -attr vt d
+load netBundle {ACC1:acc#725.itm} 2 {ACC1:acc#725.itm(0)} {ACC1:acc#725.itm(1)} -attr xrf 52464 -attr oid 520 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#725.itm}
+load net {ACC1:acc#726.itm(0)} -attr vt d
+load net {ACC1:acc#726.itm(1)} -attr vt d
+load netBundle {ACC1:acc#726.itm} 2 {ACC1:acc#726.itm(0)} {ACC1:acc#726.itm(1)} -attr xrf 52465 -attr oid 521 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#726.itm}
+load net {ACC1:conc#1456.itm(0)} -attr vt d
+load net {ACC1:conc#1456.itm(1)} -attr vt d
+load net {ACC1:conc#1456.itm(2)} -attr vt d
+load net {ACC1:conc#1456.itm(3)} -attr vt d
+load net {ACC1:conc#1456.itm(4)} -attr vt d
+load net {ACC1:conc#1456.itm(5)} -attr vt d
+load net {ACC1:conc#1456.itm(6)} -attr vt d
+load netBundle {ACC1:conc#1456.itm} 7 {ACC1:conc#1456.itm(0)} {ACC1:conc#1456.itm(1)} {ACC1:conc#1456.itm(2)} {ACC1:conc#1456.itm(3)} {ACC1:conc#1456.itm(4)} {ACC1:conc#1456.itm(5)} {ACC1:conc#1456.itm(6)} -attr xrf 52466 -attr oid 522 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#728.itm(0)} -attr vt d
+load net {ACC1:acc#728.itm(1)} -attr vt d
+load netBundle {ACC1:acc#728.itm} 2 {ACC1:acc#728.itm(0)} {ACC1:acc#728.itm(1)} -attr xrf 52467 -attr oid 523 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#728.itm}
+load net {ACC1:acc#729.itm(0)} -attr vt d
+load net {ACC1:acc#729.itm(1)} -attr vt d
+load netBundle {ACC1:acc#729.itm} 2 {ACC1:acc#729.itm(0)} {ACC1:acc#729.itm(1)} -attr xrf 52468 -attr oid 524 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#729.itm}
+load net {ACC1:acc#632.itm(0)} -attr vt d
+load net {ACC1:acc#632.itm(1)} -attr vt d
+load net {ACC1:acc#632.itm(2)} -attr vt d
+load net {ACC1:acc#632.itm(3)} -attr vt d
+load net {ACC1:acc#632.itm(4)} -attr vt d
+load net {ACC1:acc#632.itm(5)} -attr vt d
+load net {ACC1:acc#632.itm(6)} -attr vt d
+load net {ACC1:acc#632.itm(7)} -attr vt d
+load netBundle {ACC1:acc#632.itm} 8 {ACC1:acc#632.itm(0)} {ACC1:acc#632.itm(1)} {ACC1:acc#632.itm(2)} {ACC1:acc#632.itm(3)} {ACC1:acc#632.itm(4)} {ACC1:acc#632.itm(5)} {ACC1:acc#632.itm(6)} {ACC1:acc#632.itm(7)} -attr xrf 52469 -attr oid 525 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1-3:exs#1032.itm(0)} -attr vt d
+load net {ACC1-3:exs#1032.itm(1)} -attr vt d
+load net {ACC1-3:exs#1032.itm(2)} -attr vt d
+load net {ACC1-3:exs#1032.itm(3)} -attr vt d
+load net {ACC1-3:exs#1032.itm(4)} -attr vt d
+load net {ACC1-3:exs#1032.itm(5)} -attr vt d
+load net {ACC1-3:exs#1032.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#1032.itm} 7 {ACC1-3:exs#1032.itm(0)} {ACC1-3:exs#1032.itm(1)} {ACC1-3:exs#1032.itm(2)} {ACC1-3:exs#1032.itm(3)} {ACC1-3:exs#1032.itm(4)} {ACC1-3:exs#1032.itm(5)} {ACC1-3:exs#1032.itm(6)} -attr xrf 52470 -attr oid 526 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1-3:conc#496.itm(0)} -attr vt d
+load net {ACC1-3:conc#496.itm(1)} -attr vt d
+load net {ACC1-3:conc#496.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#496.itm} 3 {ACC1-3:conc#496.itm(0)} {ACC1-3:conc#496.itm(1)} {ACC1-3:conc#496.itm(2)} -attr xrf 52471 -attr oid 527 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#496.itm}
+load net {ACC1-3:exs#30.itm(0)} -attr vt d
+load net {ACC1-3:exs#30.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#30.itm} 2 {ACC1-3:exs#30.itm(0)} {ACC1-3:exs#30.itm(1)} -attr xrf 52472 -attr oid 528 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#30.itm}
+load net {ACC1-3:exs#1029.itm(0)} -attr vt d
+load net {ACC1-3:exs#1029.itm(1)} -attr vt d
+load net {ACC1-3:exs#1029.itm(2)} -attr vt d
+load net {ACC1-3:exs#1029.itm(3)} -attr vt d
+load net {ACC1-3:exs#1029.itm(4)} -attr vt d
+load net {ACC1-3:exs#1029.itm(5)} -attr vt d
+load net {ACC1-3:exs#1029.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#1029.itm} 7 {ACC1-3:exs#1029.itm(0)} {ACC1-3:exs#1029.itm(1)} {ACC1-3:exs#1029.itm(2)} {ACC1-3:exs#1029.itm(3)} {ACC1-3:exs#1029.itm(4)} {ACC1-3:exs#1029.itm(5)} {ACC1-3:exs#1029.itm(6)} -attr xrf 52473 -attr oid 529 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {ACC1-3:conc#482.itm(0)} -attr vt d
+load net {ACC1-3:conc#482.itm(1)} -attr vt d
+load net {ACC1-3:conc#482.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#482.itm} 3 {ACC1-3:conc#482.itm(0)} {ACC1-3:conc#482.itm(1)} {ACC1-3:conc#482.itm(2)} -attr xrf 52474 -attr oid 530 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#482.itm}
+load net {ACC1-3:exs#12.itm(0)} -attr vt d
+load net {ACC1-3:exs#12.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#12.itm} 2 {ACC1-3:exs#12.itm(0)} {ACC1-3:exs#12.itm(1)} -attr xrf 52475 -attr oid 531 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#12.itm}
+load net {ACC1:acc#648.itm(0)} -attr vt d
+load net {ACC1:acc#648.itm(1)} -attr vt d
+load net {ACC1:acc#648.itm(2)} -attr vt d
+load net {ACC1:acc#648.itm(3)} -attr vt d
+load net {ACC1:acc#648.itm(4)} -attr vt d
+load net {ACC1:acc#648.itm(5)} -attr vt d
+load net {ACC1:acc#648.itm(6)} -attr vt d
+load net {ACC1:acc#648.itm(7)} -attr vt d
+load net {ACC1:acc#648.itm(8)} -attr vt d
+load net {ACC1:acc#648.itm(9)} -attr vt d
+load netBundle {ACC1:acc#648.itm} 10 {ACC1:acc#648.itm(0)} {ACC1:acc#648.itm(1)} {ACC1:acc#648.itm(2)} {ACC1:acc#648.itm(3)} {ACC1:acc#648.itm(4)} {ACC1:acc#648.itm(5)} {ACC1:acc#648.itm(6)} {ACC1:acc#648.itm(7)} {ACC1:acc#648.itm(8)} {ACC1:acc#648.itm(9)} -attr xrf 52476 -attr oid 532 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#642.itm(0)} -attr vt d
+load net {ACC1:acc#642.itm(1)} -attr vt d
+load net {ACC1:acc#642.itm(2)} -attr vt d
+load net {ACC1:acc#642.itm(3)} -attr vt d
+load net {ACC1:acc#642.itm(4)} -attr vt d
+load net {ACC1:acc#642.itm(5)} -attr vt d
+load net {ACC1:acc#642.itm(6)} -attr vt d
+load net {ACC1:acc#642.itm(7)} -attr vt d
+load net {ACC1:acc#642.itm(8)} -attr vt d
+load netBundle {ACC1:acc#642.itm} 9 {ACC1:acc#642.itm(0)} {ACC1:acc#642.itm(1)} {ACC1:acc#642.itm(2)} {ACC1:acc#642.itm(3)} {ACC1:acc#642.itm(4)} {ACC1:acc#642.itm(5)} {ACC1:acc#642.itm(6)} {ACC1:acc#642.itm(7)} {ACC1:acc#642.itm(8)} -attr xrf 52477 -attr oid 533 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#631.itm(0)} -attr vt d
+load net {ACC1:acc#631.itm(1)} -attr vt d
+load net {ACC1:acc#631.itm(2)} -attr vt d
+load net {ACC1:acc#631.itm(3)} -attr vt d
+load net {ACC1:acc#631.itm(4)} -attr vt d
+load net {ACC1:acc#631.itm(5)} -attr vt d
+load net {ACC1:acc#631.itm(6)} -attr vt d
+load net {ACC1:acc#631.itm(7)} -attr vt d
+load netBundle {ACC1:acc#631.itm} 8 {ACC1:acc#631.itm(0)} {ACC1:acc#631.itm(1)} {ACC1:acc#631.itm(2)} {ACC1:acc#631.itm(3)} {ACC1:acc#631.itm(4)} {ACC1:acc#631.itm(5)} {ACC1:acc#631.itm(6)} {ACC1:acc#631.itm(7)} -attr xrf 52478 -attr oid 534 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1-3:exs#1035.itm(0)} -attr vt d
+load net {ACC1-3:exs#1035.itm(1)} -attr vt d
+load net {ACC1-3:exs#1035.itm(2)} -attr vt d
+load net {ACC1-3:exs#1035.itm(3)} -attr vt d
+load net {ACC1-3:exs#1035.itm(4)} -attr vt d
+load net {ACC1-3:exs#1035.itm(5)} -attr vt d
+load net {ACC1-3:exs#1035.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#1035.itm} 7 {ACC1-3:exs#1035.itm(0)} {ACC1-3:exs#1035.itm(1)} {ACC1-3:exs#1035.itm(2)} {ACC1-3:exs#1035.itm(3)} {ACC1-3:exs#1035.itm(4)} {ACC1-3:exs#1035.itm(5)} {ACC1-3:exs#1035.itm(6)} -attr xrf 52479 -attr oid 535 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1-3:conc#510.itm(0)} -attr vt d
+load net {ACC1-3:conc#510.itm(1)} -attr vt d
+load net {ACC1-3:conc#510.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#510.itm} 3 {ACC1-3:conc#510.itm(0)} {ACC1-3:conc#510.itm(1)} {ACC1-3:conc#510.itm(2)} -attr xrf 52480 -attr oid 536 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#510.itm}
+load net {ACC1-3:exs#1062.itm(0)} -attr vt d
+load net {ACC1-3:exs#1062.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1062.itm} 2 {ACC1-3:exs#1062.itm(0)} {ACC1-3:exs#1062.itm(1)} -attr xrf 52481 -attr oid 537 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1062.itm}
+load net {ACC1-2:exs#1032.itm(0)} -attr vt d
+load net {ACC1-2:exs#1032.itm(1)} -attr vt d
+load net {ACC1-2:exs#1032.itm(2)} -attr vt d
+load net {ACC1-2:exs#1032.itm(3)} -attr vt d
+load net {ACC1-2:exs#1032.itm(4)} -attr vt d
+load net {ACC1-2:exs#1032.itm(5)} -attr vt d
+load net {ACC1-2:exs#1032.itm(6)} -attr vt d
+load netBundle {ACC1-2:exs#1032.itm} 7 {ACC1-2:exs#1032.itm(0)} {ACC1-2:exs#1032.itm(1)} {ACC1-2:exs#1032.itm(2)} {ACC1-2:exs#1032.itm(3)} {ACC1-2:exs#1032.itm(4)} {ACC1-2:exs#1032.itm(5)} {ACC1-2:exs#1032.itm(6)} -attr xrf 52482 -attr oid 538 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1-2:conc#496.itm(0)} -attr vt d
+load net {ACC1-2:conc#496.itm(1)} -attr vt d
+load net {ACC1-2:conc#496.itm(2)} -attr vt d
+load netBundle {ACC1-2:conc#496.itm} 3 {ACC1-2:conc#496.itm(0)} {ACC1-2:conc#496.itm(1)} {ACC1-2:conc#496.itm(2)} -attr xrf 52483 -attr oid 539 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:conc#496.itm}
+load net {ACC1-2:exs#1052.itm(0)} -attr vt d
+load net {ACC1-2:exs#1052.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1052.itm} 2 {ACC1-2:exs#1052.itm(0)} {ACC1-2:exs#1052.itm(1)} -attr xrf 52484 -attr oid 540 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1052.itm}
+load net {ACC1:acc#630.itm(0)} -attr vt d
+load net {ACC1:acc#630.itm(1)} -attr vt d
+load net {ACC1:acc#630.itm(2)} -attr vt d
+load net {ACC1:acc#630.itm(3)} -attr vt d
+load net {ACC1:acc#630.itm(4)} -attr vt d
+load net {ACC1:acc#630.itm(5)} -attr vt d
+load net {ACC1:acc#630.itm(6)} -attr vt d
+load net {ACC1:acc#630.itm(7)} -attr vt d
+load netBundle {ACC1:acc#630.itm} 8 {ACC1:acc#630.itm(0)} {ACC1:acc#630.itm(1)} {ACC1:acc#630.itm(2)} {ACC1:acc#630.itm(3)} {ACC1:acc#630.itm(4)} {ACC1:acc#630.itm(5)} {ACC1:acc#630.itm(6)} {ACC1:acc#630.itm(7)} -attr xrf 52485 -attr oid 541 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {exs#94.itm(0)} -attr vt d
+load net {exs#94.itm(1)} -attr vt d
+load net {exs#94.itm(2)} -attr vt d
+load net {exs#94.itm(3)} -attr vt d
+load net {exs#94.itm(4)} -attr vt d
+load net {exs#94.itm(5)} -attr vt d
+load net {exs#94.itm(6)} -attr vt d
+load netBundle {exs#94.itm} 7 {exs#94.itm(0)} {exs#94.itm(1)} {exs#94.itm(2)} {exs#94.itm(3)} {exs#94.itm(4)} {exs#94.itm(5)} {exs#94.itm(6)} -attr xrf 52486 -attr oid 542 -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {conc#949.itm(0)} -attr vt d
+load net {conc#949.itm(1)} -attr vt d
+load net {conc#949.itm(2)} -attr vt d
+load net {conc#949.itm(3)} -attr vt d
+load netBundle {conc#949.itm} 4 {conc#949.itm(0)} {conc#949.itm(1)} {conc#949.itm(2)} {conc#949.itm(3)} -attr xrf 52487 -attr oid 543 -attr vt d -attr @path {/sobel/sobel:core/conc#949.itm}
+load net {ACC1-3:exs#1071.itm(0)} -attr vt d
+load net {ACC1-3:exs#1071.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1071.itm} 2 {ACC1-3:exs#1071.itm(0)} {ACC1-3:exs#1071.itm(1)} -attr xrf 52488 -attr oid 544 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1071.itm}
+load net {ACC1-3:exs#1040.itm(0)} -attr vt d
+load net {ACC1-3:exs#1040.itm(1)} -attr vt d
+load net {ACC1-3:exs#1040.itm(2)} -attr vt d
+load net {ACC1-3:exs#1040.itm(3)} -attr vt d
+load net {ACC1-3:exs#1040.itm(4)} -attr vt d
+load net {ACC1-3:exs#1040.itm(5)} -attr vt d
+load net {ACC1-3:exs#1040.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#1040.itm} 7 {ACC1-3:exs#1040.itm(0)} {ACC1-3:exs#1040.itm(1)} {ACC1-3:exs#1040.itm(2)} {ACC1-3:exs#1040.itm(3)} {ACC1-3:exs#1040.itm(4)} {ACC1-3:exs#1040.itm(5)} {ACC1-3:exs#1040.itm(6)} -attr xrf 52489 -attr oid 545 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {ACC1-3:conc#538.itm(0)} -attr vt d
+load net {ACC1-3:conc#538.itm(1)} -attr vt d
+load net {ACC1-3:conc#538.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#538.itm} 3 {ACC1-3:conc#538.itm(0)} {ACC1-3:conc#538.itm(1)} {ACC1-3:conc#538.itm(2)} -attr xrf 52490 -attr oid 546 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#538.itm}
+load net {ACC1-3:exs#1045.itm(0)} -attr vt d
+load net {ACC1-3:exs#1045.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1045.itm} 2 {ACC1-3:exs#1045.itm(0)} {ACC1-3:exs#1045.itm(1)} -attr xrf 52491 -attr oid 547 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1045.itm}
+load net {ACC1:acc#641.itm(0)} -attr vt d
+load net {ACC1:acc#641.itm(1)} -attr vt d
+load net {ACC1:acc#641.itm(2)} -attr vt d
+load net {ACC1:acc#641.itm(3)} -attr vt d
+load net {ACC1:acc#641.itm(4)} -attr vt d
+load net {ACC1:acc#641.itm(5)} -attr vt d
+load net {ACC1:acc#641.itm(6)} -attr vt d
+load net {ACC1:acc#641.itm(7)} -attr vt d
+load net {ACC1:acc#641.itm(8)} -attr vt d
+load netBundle {ACC1:acc#641.itm} 9 {ACC1:acc#641.itm(0)} {ACC1:acc#641.itm(1)} {ACC1:acc#641.itm(2)} {ACC1:acc#641.itm(3)} {ACC1:acc#641.itm(4)} {ACC1:acc#641.itm(5)} {ACC1:acc#641.itm(6)} {ACC1:acc#641.itm(7)} {ACC1:acc#641.itm(8)} -attr xrf 52492 -attr oid 548 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#629.itm(0)} -attr vt d
+load net {ACC1:acc#629.itm(1)} -attr vt d
+load net {ACC1:acc#629.itm(2)} -attr vt d
+load net {ACC1:acc#629.itm(3)} -attr vt d
+load net {ACC1:acc#629.itm(4)} -attr vt d
+load net {ACC1:acc#629.itm(5)} -attr vt d
+load net {ACC1:acc#629.itm(6)} -attr vt d
+load net {ACC1:acc#629.itm(7)} -attr vt d
+load netBundle {ACC1:acc#629.itm} 8 {ACC1:acc#629.itm(0)} {ACC1:acc#629.itm(1)} {ACC1:acc#629.itm(2)} {ACC1:acc#629.itm(3)} {ACC1:acc#629.itm(4)} {ACC1:acc#629.itm(5)} {ACC1:acc#629.itm(6)} {ACC1:acc#629.itm(7)} -attr xrf 52493 -attr oid 549 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {exs#95.itm(0)} -attr vt d
+load net {exs#95.itm(1)} -attr vt d
+load net {exs#95.itm(2)} -attr vt d
+load net {exs#95.itm(3)} -attr vt d
+load net {exs#95.itm(4)} -attr vt d
+load net {exs#95.itm(5)} -attr vt d
+load net {exs#95.itm(6)} -attr vt d
+load netBundle {exs#95.itm} 7 {exs#95.itm(0)} {exs#95.itm(1)} {exs#95.itm(2)} {exs#95.itm(3)} {exs#95.itm(4)} {exs#95.itm(5)} {exs#95.itm(6)} -attr xrf 52494 -attr oid 550 -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {conc#951.itm(0)} -attr vt d
+load net {conc#951.itm(1)} -attr vt d
+load net {conc#951.itm(2)} -attr vt d
+load net {conc#951.itm(3)} -attr vt d
+load netBundle {conc#951.itm} 4 {conc#951.itm(0)} {conc#951.itm(1)} {conc#951.itm(2)} {conc#951.itm(3)} -attr xrf 52495 -attr oid 551 -attr vt d -attr @path {/sobel/sobel:core/conc#951.itm}
+load net {ACC1-2:exs#1063.itm(0)} -attr vt d
+load net {ACC1-2:exs#1063.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1063.itm} 2 {ACC1-2:exs#1063.itm(0)} {ACC1-2:exs#1063.itm(1)} -attr xrf 52496 -attr oid 552 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1063.itm}
+load net {ACC1-1:exs#1035.itm(0)} -attr vt d
+load net {ACC1-1:exs#1035.itm(1)} -attr vt d
+load net {ACC1-1:exs#1035.itm(2)} -attr vt d
+load net {ACC1-1:exs#1035.itm(3)} -attr vt d
+load net {ACC1-1:exs#1035.itm(4)} -attr vt d
+load net {ACC1-1:exs#1035.itm(5)} -attr vt d
+load net {ACC1-1:exs#1035.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#1035.itm} 7 {ACC1-1:exs#1035.itm(0)} {ACC1-1:exs#1035.itm(1)} {ACC1-1:exs#1035.itm(2)} {ACC1-1:exs#1035.itm(3)} {ACC1-1:exs#1035.itm(4)} {ACC1-1:exs#1035.itm(5)} {ACC1-1:exs#1035.itm(6)} -attr xrf 52497 -attr oid 553 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1-1:conc#510.itm(0)} -attr vt d
+load net {ACC1-1:conc#510.itm(1)} -attr vt d
+load net {ACC1-1:conc#510.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#510.itm} 3 {ACC1-1:conc#510.itm(0)} {ACC1-1:conc#510.itm(1)} {ACC1-1:conc#510.itm(2)} -attr xrf 52498 -attr oid 554 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#510.itm}
+load net {ACC1-1:exs#48.itm(0)} -attr vt d
+load net {ACC1-1:exs#48.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#48.itm} 2 {ACC1-1:exs#48.itm(0)} {ACC1-1:exs#48.itm(1)} -attr xrf 52499 -attr oid 555 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#48.itm}
+load net {ACC1:acc#628.itm(0)} -attr vt d
+load net {ACC1:acc#628.itm(1)} -attr vt d
+load net {ACC1:acc#628.itm(2)} -attr vt d
+load net {ACC1:acc#628.itm(3)} -attr vt d
+load net {ACC1:acc#628.itm(4)} -attr vt d
+load net {ACC1:acc#628.itm(5)} -attr vt d
+load net {ACC1:acc#628.itm(6)} -attr vt d
+load net {ACC1:acc#628.itm(7)} -attr vt d
+load netBundle {ACC1:acc#628.itm} 8 {ACC1:acc#628.itm(0)} {ACC1:acc#628.itm(1)} {ACC1:acc#628.itm(2)} {ACC1:acc#628.itm(3)} {ACC1:acc#628.itm(4)} {ACC1:acc#628.itm(5)} {ACC1:acc#628.itm(6)} {ACC1:acc#628.itm(7)} -attr xrf 52500 -attr oid 556 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {exs#96.itm(0)} -attr vt d
+load net {exs#96.itm(1)} -attr vt d
+load net {exs#96.itm(2)} -attr vt d
+load net {exs#96.itm(3)} -attr vt d
+load net {exs#96.itm(4)} -attr vt d
+load net {exs#96.itm(5)} -attr vt d
+load net {exs#96.itm(6)} -attr vt d
+load netBundle {exs#96.itm} 7 {exs#96.itm(0)} {exs#96.itm(1)} {exs#96.itm(2)} {exs#96.itm(3)} {exs#96.itm(4)} {exs#96.itm(5)} {exs#96.itm(6)} -attr xrf 52501 -attr oid 557 -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {conc#953.itm(0)} -attr vt d
+load net {conc#953.itm(1)} -attr vt d
+load net {conc#953.itm(2)} -attr vt d
+load net {conc#953.itm(3)} -attr vt d
+load netBundle {conc#953.itm} 4 {conc#953.itm(0)} {conc#953.itm(1)} {conc#953.itm(2)} {conc#953.itm(3)} -attr xrf 52502 -attr oid 558 -attr vt d -attr @path {/sobel/sobel:core/conc#953.itm}
+load net {ACC1-1:exs#1068.itm(0)} -attr vt d
+load net {ACC1-1:exs#1068.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1068.itm} 2 {ACC1-1:exs#1068.itm(0)} {ACC1-1:exs#1068.itm(1)} -attr xrf 52503 -attr oid 559 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1068.itm}
+load net {ACC1-1:exs#1051.itm(0)} -attr vt d
+load net {ACC1-1:exs#1051.itm(1)} -attr vt d
+load net {ACC1-1:exs#1051.itm(2)} -attr vt d
+load net {ACC1-1:exs#1051.itm(3)} -attr vt d
+load net {ACC1-1:exs#1051.itm(4)} -attr vt d
+load net {ACC1-1:exs#1051.itm(5)} -attr vt d
+load net {ACC1-1:exs#1051.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#1051.itm} 7 {ACC1-1:exs#1051.itm(0)} {ACC1-1:exs#1051.itm(1)} {ACC1-1:exs#1051.itm(2)} {ACC1-1:exs#1051.itm(3)} {ACC1-1:exs#1051.itm(4)} {ACC1-1:exs#1051.itm(5)} {ACC1-1:exs#1051.itm(6)} -attr xrf 52504 -attr oid 560 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {ACC1-1:conc#602.itm(0)} -attr vt d
+load net {ACC1-1:conc#602.itm(1)} -attr vt d
+load net {ACC1-1:conc#602.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#602.itm} 3 {ACC1-1:conc#602.itm(0)} {ACC1-1:conc#602.itm(1)} {ACC1-1:conc#602.itm(2)} -attr xrf 52505 -attr oid 561 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#602.itm}
+load net {ACC1-1:exs#1052.itm(0)} -attr vt d
+load net {ACC1-1:exs#1052.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1052.itm} 2 {ACC1-1:exs#1052.itm(0)} {ACC1-1:exs#1052.itm(1)} -attr xrf 52506 -attr oid 562 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1052.itm}
+load net {ACC1:acc#655.itm(0)} -attr vt d
+load net {ACC1:acc#655.itm(1)} -attr vt d
+load net {ACC1:acc#655.itm(2)} -attr vt d
+load net {ACC1:acc#655.itm(3)} -attr vt d
+load net {ACC1:acc#655.itm(4)} -attr vt d
+load net {ACC1:acc#655.itm(5)} -attr vt d
+load net {ACC1:acc#655.itm(6)} -attr vt d
+load net {ACC1:acc#655.itm(7)} -attr vt d
+load net {ACC1:acc#655.itm(8)} -attr vt d
+load net {ACC1:acc#655.itm(9)} -attr vt d
+load net {ACC1:acc#655.itm(10)} -attr vt d
+load net {ACC1:acc#655.itm(11)} -attr vt d
+load netBundle {ACC1:acc#655.itm} 12 {ACC1:acc#655.itm(0)} {ACC1:acc#655.itm(1)} {ACC1:acc#655.itm(2)} {ACC1:acc#655.itm(3)} {ACC1:acc#655.itm(4)} {ACC1:acc#655.itm(5)} {ACC1:acc#655.itm(6)} {ACC1:acc#655.itm(7)} {ACC1:acc#655.itm(8)} {ACC1:acc#655.itm(9)} {ACC1:acc#655.itm(10)} {ACC1:acc#655.itm(11)} -attr xrf 52507 -attr oid 563 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#650.itm(0)} -attr vt d
+load net {ACC1:acc#650.itm(1)} -attr vt d
+load net {ACC1:acc#650.itm(2)} -attr vt d
+load net {ACC1:acc#650.itm(3)} -attr vt d
+load net {ACC1:acc#650.itm(4)} -attr vt d
+load net {ACC1:acc#650.itm(5)} -attr vt d
+load net {ACC1:acc#650.itm(6)} -attr vt d
+load net {ACC1:acc#650.itm(7)} -attr vt d
+load net {ACC1:acc#650.itm(8)} -attr vt d
+load net {ACC1:acc#650.itm(9)} -attr vt d
+load net {ACC1:acc#650.itm(10)} -attr vt d
+load netBundle {ACC1:acc#650.itm} 11 {ACC1:acc#650.itm(0)} {ACC1:acc#650.itm(1)} {ACC1:acc#650.itm(2)} {ACC1:acc#650.itm(3)} {ACC1:acc#650.itm(4)} {ACC1:acc#650.itm(5)} {ACC1:acc#650.itm(6)} {ACC1:acc#650.itm(7)} {ACC1:acc#650.itm(8)} {ACC1:acc#650.itm(9)} {ACC1:acc#650.itm(10)} -attr xrf 52508 -attr oid 564 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {conc#955.itm(0)} -attr vt d
+load net {conc#955.itm(1)} -attr vt d
+load net {conc#955.itm(2)} -attr vt d
+load net {conc#955.itm(3)} -attr vt d
+load net {conc#955.itm(4)} -attr vt d
+load net {conc#955.itm(5)} -attr vt d
+load net {conc#955.itm(6)} -attr vt d
+load net {conc#955.itm(7)} -attr vt d
+load net {conc#955.itm(8)} -attr vt d
+load net {conc#955.itm(9)} -attr vt d
+load netBundle {conc#955.itm} 10 {conc#955.itm(0)} {conc#955.itm(1)} {conc#955.itm(2)} {conc#955.itm(3)} {conc#955.itm(4)} {conc#955.itm(5)} {conc#955.itm(6)} {conc#955.itm(7)} {conc#955.itm(8)} {conc#955.itm(9)} -attr xrf 52509 -attr oid 565 -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {ACC1:acc#645.itm(0)} -attr vt d
+load net {ACC1:acc#645.itm(1)} -attr vt d
+load net {ACC1:acc#645.itm(2)} -attr vt d
+load net {ACC1:acc#645.itm(3)} -attr vt d
+load net {ACC1:acc#645.itm(4)} -attr vt d
+load net {ACC1:acc#645.itm(5)} -attr vt d
+load net {ACC1:acc#645.itm(6)} -attr vt d
+load net {ACC1:acc#645.itm(7)} -attr vt d
+load net {ACC1:acc#645.itm(8)} -attr vt d
+load netBundle {ACC1:acc#645.itm} 9 {ACC1:acc#645.itm(0)} {ACC1:acc#645.itm(1)} {ACC1:acc#645.itm(2)} {ACC1:acc#645.itm(3)} {ACC1:acc#645.itm(4)} {ACC1:acc#645.itm(5)} {ACC1:acc#645.itm(6)} {ACC1:acc#645.itm(7)} {ACC1:acc#645.itm(8)} -attr xrf 52510 -attr oid 566 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#638.itm(0)} -attr vt d
+load net {ACC1:acc#638.itm(1)} -attr vt d
+load net {ACC1:acc#638.itm(2)} -attr vt d
+load net {ACC1:acc#638.itm(3)} -attr vt d
+load net {ACC1:acc#638.itm(4)} -attr vt d
+load net {ACC1:acc#638.itm(5)} -attr vt d
+load net {ACC1:acc#638.itm(6)} -attr vt d
+load net {ACC1:acc#638.itm(7)} -attr vt d
+load netBundle {ACC1:acc#638.itm} 8 {ACC1:acc#638.itm(0)} {ACC1:acc#638.itm(1)} {ACC1:acc#638.itm(2)} {ACC1:acc#638.itm(3)} {ACC1:acc#638.itm(4)} {ACC1:acc#638.itm(5)} {ACC1:acc#638.itm(6)} {ACC1:acc#638.itm(7)} -attr xrf 52511 -attr oid 567 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {conc#956.itm(0)} -attr vt d
+load net {conc#956.itm(1)} -attr vt d
+load net {conc#956.itm(2)} -attr vt d
+load net {conc#956.itm(3)} -attr vt d
+load net {conc#956.itm(4)} -attr vt d
+load net {conc#956.itm(5)} -attr vt d
+load net {conc#956.itm(6)} -attr vt d
+load net {conc#956.itm(7)} -attr vt d
+load netBundle {conc#956.itm} 8 {conc#956.itm(0)} {conc#956.itm(1)} {conc#956.itm(2)} {conc#956.itm(3)} {conc#956.itm(4)} {conc#956.itm(5)} {conc#956.itm(6)} {conc#956.itm(7)} -attr xrf 52512 -attr oid 568 -attr vt d -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {ACC1:acc#626.itm(0)} -attr vt d
+load net {ACC1:acc#626.itm(1)} -attr vt d
+load net {ACC1:acc#626.itm(2)} -attr vt d
+load net {ACC1:acc#626.itm(3)} -attr vt d
+load net {ACC1:acc#626.itm(4)} -attr vt d
+load net {ACC1:acc#626.itm(5)} -attr vt d
+load net {ACC1:acc#626.itm(6)} -attr vt d
+load netBundle {ACC1:acc#626.itm} 7 {ACC1:acc#626.itm(0)} {ACC1:acc#626.itm(1)} {ACC1:acc#626.itm(2)} {ACC1:acc#626.itm(3)} {ACC1:acc#626.itm(4)} {ACC1:acc#626.itm(5)} {ACC1:acc#626.itm(6)} -attr xrf 52513 -attr oid 569 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#613.itm(0)} -attr vt d
+load net {ACC1:acc#613.itm(1)} -attr vt d
+load net {ACC1:acc#613.itm(2)} -attr vt d
+load net {ACC1:acc#613.itm(3)} -attr vt d
+load net {ACC1:acc#613.itm(4)} -attr vt d
+load net {ACC1:acc#613.itm(5)} -attr vt d
+load netBundle {ACC1:acc#613.itm} 6 {ACC1:acc#613.itm(0)} {ACC1:acc#613.itm(1)} {ACC1:acc#613.itm(2)} {ACC1:acc#613.itm(3)} {ACC1:acc#613.itm(4)} {ACC1:acc#613.itm(5)} -attr xrf 52514 -attr oid 570 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#597.itm(0)} -attr vt d
+load net {ACC1:acc#597.itm(1)} -attr vt d
+load net {ACC1:acc#597.itm(2)} -attr vt d
+load net {ACC1:acc#597.itm(3)} -attr vt d
+load net {ACC1:acc#597.itm(4)} -attr vt d
+load netBundle {ACC1:acc#597.itm} 5 {ACC1:acc#597.itm(0)} {ACC1:acc#597.itm(1)} {ACC1:acc#597.itm(2)} {ACC1:acc#597.itm(3)} {ACC1:acc#597.itm(4)} -attr xrf 52515 -attr oid 571 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#564.itm(0)} -attr vt d
+load net {ACC1:acc#564.itm(1)} -attr vt d
+load net {ACC1:acc#564.itm(2)} -attr vt d
+load net {ACC1:acc#564.itm(3)} -attr vt d
+load netBundle {ACC1:acc#564.itm} 4 {ACC1:acc#564.itm(0)} {ACC1:acc#564.itm(1)} {ACC1:acc#564.itm(2)} {ACC1:acc#564.itm(3)} -attr xrf 52516 -attr oid 572 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#563.itm(0)} -attr vt d
+load net {ACC1:acc#563.itm(1)} -attr vt d
+load net {ACC1:acc#563.itm(2)} -attr vt d
+load net {ACC1:acc#563.itm(3)} -attr vt d
+load netBundle {ACC1:acc#563.itm} 4 {ACC1:acc#563.itm(0)} {ACC1:acc#563.itm(1)} {ACC1:acc#563.itm(2)} {ACC1:acc#563.itm(3)} -attr xrf 52517 -attr oid 573 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#507.itm(0)} -attr vt d
+load net {ACC1:acc#507.itm(1)} -attr vt d
+load net {ACC1:acc#507.itm(2)} -attr vt d
+load netBundle {ACC1:acc#507.itm} 3 {ACC1:acc#507.itm(0)} {ACC1:acc#507.itm(1)} {ACC1:acc#507.itm(2)} -attr xrf 52518 -attr oid 574 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load net {ACC1-3:exs#1058.itm(0)} -attr vt d
+load net {ACC1-3:exs#1058.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1058.itm} 2 {ACC1-3:exs#1058.itm(0)} {ACC1-3:exs#1058.itm(1)} -attr xrf 52519 -attr oid 575 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1058.itm}
+load net {ACC1-3:exs#1031.itm(0)} -attr vt d
+load net {ACC1-3:exs#1031.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1031.itm} 2 {ACC1-3:exs#1031.itm(0)} {ACC1-3:exs#1031.itm(1)} -attr xrf 52520 -attr oid 576 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1031.itm}
+load net {ACC1:acc#596.itm(0)} -attr vt d
+load net {ACC1:acc#596.itm(1)} -attr vt d
+load net {ACC1:acc#596.itm(2)} -attr vt d
+load net {ACC1:acc#596.itm(3)} -attr vt d
+load net {ACC1:acc#596.itm(4)} -attr vt d
+load netBundle {ACC1:acc#596.itm} 5 {ACC1:acc#596.itm(0)} {ACC1:acc#596.itm(1)} {ACC1:acc#596.itm(2)} {ACC1:acc#596.itm(3)} {ACC1:acc#596.itm(4)} -attr xrf 52521 -attr oid 577 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#561.itm(0)} -attr vt d
+load net {ACC1:acc#561.itm(1)} -attr vt d
+load net {ACC1:acc#561.itm(2)} -attr vt d
+load net {ACC1:acc#561.itm(3)} -attr vt d
+load netBundle {ACC1:acc#561.itm} 4 {ACC1:acc#561.itm(0)} {ACC1:acc#561.itm(1)} {ACC1:acc#561.itm(2)} {ACC1:acc#561.itm(3)} -attr xrf 52522 -attr oid 578 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#612.itm(0)} -attr vt d
+load net {ACC1:acc#612.itm(1)} -attr vt d
+load net {ACC1:acc#612.itm(2)} -attr vt d
+load net {ACC1:acc#612.itm(3)} -attr vt d
+load net {ACC1:acc#612.itm(4)} -attr vt d
+load net {ACC1:acc#612.itm(5)} -attr vt d
+load netBundle {ACC1:acc#612.itm} 6 {ACC1:acc#612.itm(0)} {ACC1:acc#612.itm(1)} {ACC1:acc#612.itm(2)} {ACC1:acc#612.itm(3)} {ACC1:acc#612.itm(4)} {ACC1:acc#612.itm(5)} -attr xrf 52523 -attr oid 579 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#595.itm(0)} -attr vt d
+load net {ACC1:acc#595.itm(1)} -attr vt d
+load net {ACC1:acc#595.itm(2)} -attr vt d
+load net {ACC1:acc#595.itm(3)} -attr vt d
+load net {ACC1:acc#595.itm(4)} -attr vt d
+load netBundle {ACC1:acc#595.itm} 5 {ACC1:acc#595.itm(0)} {ACC1:acc#595.itm(1)} {ACC1:acc#595.itm(2)} {ACC1:acc#595.itm(3)} {ACC1:acc#595.itm(4)} -attr xrf 52524 -attr oid 580 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#559.itm(0)} -attr vt d
+load net {ACC1:acc#559.itm(1)} -attr vt d
+load net {ACC1:acc#559.itm(2)} -attr vt d
+load net {ACC1:acc#559.itm(3)} -attr vt d
+load netBundle {ACC1:acc#559.itm} 4 {ACC1:acc#559.itm(0)} {ACC1:acc#559.itm(1)} {ACC1:acc#559.itm(2)} {ACC1:acc#559.itm(3)} -attr xrf 52525 -attr oid 581 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#499.itm(0)} -attr vt d
+load net {ACC1:acc#499.itm(1)} -attr vt d
+load net {ACC1:acc#499.itm(2)} -attr vt d
+load netBundle {ACC1:acc#499.itm} 3 {ACC1:acc#499.itm(0)} {ACC1:acc#499.itm(1)} {ACC1:acc#499.itm(2)} -attr xrf 52526 -attr oid 582 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load net {ACC1-3:exs#1053.itm(0)} -attr vt d
+load net {ACC1-3:exs#1053.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1053.itm} 2 {ACC1-3:exs#1053.itm(0)} {ACC1-3:exs#1053.itm(1)} -attr xrf 52527 -attr oid 583 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1053.itm}
+load net {ACC1-3:exs#72.itm(0)} -attr vt d
+load net {ACC1-3:exs#72.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#72.itm} 2 {ACC1-3:exs#72.itm(0)} {ACC1-3:exs#72.itm(1)} -attr xrf 52528 -attr oid 584 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#72.itm}
+load net {ACC1:acc#498.itm(0)} -attr vt d
+load net {ACC1:acc#498.itm(1)} -attr vt d
+load net {ACC1:acc#498.itm(2)} -attr vt d
+load netBundle {ACC1:acc#498.itm} 3 {ACC1:acc#498.itm(0)} {ACC1:acc#498.itm(1)} {ACC1:acc#498.itm(2)} -attr xrf 52529 -attr oid 585 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load net {ACC1-3:exs#73.itm(0)} -attr vt d
+load net {ACC1-3:exs#73.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#73.itm} 2 {ACC1-3:exs#73.itm(0)} {ACC1-3:exs#73.itm(1)} -attr xrf 52530 -attr oid 586 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#73.itm}
+load net {ACC1-3:exs#1054.itm(0)} -attr vt d
+load net {ACC1-3:exs#1054.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1054.itm} 2 {ACC1-3:exs#1054.itm(0)} {ACC1-3:exs#1054.itm(1)} -attr xrf 52531 -attr oid 587 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1054.itm}
+load net {ACC1:acc#594.itm(0)} -attr vt d
+load net {ACC1:acc#594.itm(1)} -attr vt d
+load net {ACC1:acc#594.itm(2)} -attr vt d
+load net {ACC1:acc#594.itm(3)} -attr vt d
+load net {ACC1:acc#594.itm(4)} -attr vt d
+load netBundle {ACC1:acc#594.itm} 5 {ACC1:acc#594.itm(0)} {ACC1:acc#594.itm(1)} {ACC1:acc#594.itm(2)} {ACC1:acc#594.itm(3)} {ACC1:acc#594.itm(4)} -attr xrf 52532 -attr oid 588 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#637.itm(0)} -attr vt d
+load net {ACC1:acc#637.itm(1)} -attr vt d
+load net {ACC1:acc#637.itm(2)} -attr vt d
+load net {ACC1:acc#637.itm(3)} -attr vt d
+load net {ACC1:acc#637.itm(4)} -attr vt d
+load net {ACC1:acc#637.itm(5)} -attr vt d
+load net {ACC1:acc#637.itm(6)} -attr vt d
+load net {ACC1:acc#637.itm(7)} -attr vt d
+load netBundle {ACC1:acc#637.itm} 8 {ACC1:acc#637.itm(0)} {ACC1:acc#637.itm(1)} {ACC1:acc#637.itm(2)} {ACC1:acc#637.itm(3)} {ACC1:acc#637.itm(4)} {ACC1:acc#637.itm(5)} {ACC1:acc#637.itm(6)} {ACC1:acc#637.itm(7)} -attr xrf 52533 -attr oid 589 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#625.itm(0)} -attr vt d
+load net {ACC1:acc#625.itm(1)} -attr vt d
+load net {ACC1:acc#625.itm(2)} -attr vt d
+load net {ACC1:acc#625.itm(3)} -attr vt d
+load net {ACC1:acc#625.itm(4)} -attr vt d
+load net {ACC1:acc#625.itm(5)} -attr vt d
+load net {ACC1:acc#625.itm(6)} -attr vt d
+load netBundle {ACC1:acc#625.itm} 7 {ACC1:acc#625.itm(0)} {ACC1:acc#625.itm(1)} {ACC1:acc#625.itm(2)} {ACC1:acc#625.itm(3)} {ACC1:acc#625.itm(4)} {ACC1:acc#625.itm(5)} {ACC1:acc#625.itm(6)} -attr xrf 52534 -attr oid 590 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#611.itm(0)} -attr vt d
+load net {ACC1:acc#611.itm(1)} -attr vt d
+load net {ACC1:acc#611.itm(2)} -attr vt d
+load net {ACC1:acc#611.itm(3)} -attr vt d
+load net {ACC1:acc#611.itm(4)} -attr vt d
+load net {ACC1:acc#611.itm(5)} -attr vt d
+load netBundle {ACC1:acc#611.itm} 6 {ACC1:acc#611.itm(0)} {ACC1:acc#611.itm(1)} {ACC1:acc#611.itm(2)} {ACC1:acc#611.itm(3)} {ACC1:acc#611.itm(4)} {ACC1:acc#611.itm(5)} -attr xrf 52535 -attr oid 591 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#593.itm(0)} -attr vt d
+load net {ACC1:acc#593.itm(1)} -attr vt d
+load net {ACC1:acc#593.itm(2)} -attr vt d
+load net {ACC1:acc#593.itm(3)} -attr vt d
+load net {ACC1:acc#593.itm(4)} -attr vt d
+load netBundle {ACC1:acc#593.itm} 5 {ACC1:acc#593.itm(0)} {ACC1:acc#593.itm(1)} {ACC1:acc#593.itm(2)} {ACC1:acc#593.itm(3)} {ACC1:acc#593.itm(4)} -attr xrf 52536 -attr oid 592 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#556.itm(0)} -attr vt d
+load net {ACC1:acc#556.itm(1)} -attr vt d
+load net {ACC1:acc#556.itm(2)} -attr vt d
+load net {ACC1:acc#556.itm(3)} -attr vt d
+load netBundle {ACC1:acc#556.itm} 4 {ACC1:acc#556.itm(0)} {ACC1:acc#556.itm(1)} {ACC1:acc#556.itm(2)} {ACC1:acc#556.itm(3)} -attr xrf 52537 -attr oid 593 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#555.itm(0)} -attr vt d
+load net {ACC1:acc#555.itm(1)} -attr vt d
+load net {ACC1:acc#555.itm(2)} -attr vt d
+load net {ACC1:acc#555.itm(3)} -attr vt d
+load netBundle {ACC1:acc#555.itm} 4 {ACC1:acc#555.itm(0)} {ACC1:acc#555.itm(1)} {ACC1:acc#555.itm(2)} {ACC1:acc#555.itm(3)} -attr xrf 52538 -attr oid 594 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#592.itm(0)} -attr vt d
+load net {ACC1:acc#592.itm(1)} -attr vt d
+load net {ACC1:acc#592.itm(2)} -attr vt d
+load net {ACC1:acc#592.itm(3)} -attr vt d
+load net {ACC1:acc#592.itm(4)} -attr vt d
+load netBundle {ACC1:acc#592.itm} 5 {ACC1:acc#592.itm(0)} {ACC1:acc#592.itm(1)} {ACC1:acc#592.itm(2)} {ACC1:acc#592.itm(3)} {ACC1:acc#592.itm(4)} -attr xrf 52539 -attr oid 595 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#554.itm(0)} -attr vt d
+load net {ACC1:acc#554.itm(1)} -attr vt d
+load net {ACC1:acc#554.itm(2)} -attr vt d
+load net {ACC1:acc#554.itm(3)} -attr vt d
+load netBundle {ACC1:acc#554.itm} 4 {ACC1:acc#554.itm(0)} {ACC1:acc#554.itm(1)} {ACC1:acc#554.itm(2)} {ACC1:acc#554.itm(3)} -attr xrf 52540 -attr oid 596 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#488.itm(0)} -attr vt d
+load net {ACC1:acc#488.itm(1)} -attr vt d
+load net {ACC1:acc#488.itm(2)} -attr vt d
+load netBundle {ACC1:acc#488.itm} 3 {ACC1:acc#488.itm(0)} {ACC1:acc#488.itm(1)} {ACC1:acc#488.itm(2)} -attr xrf 52541 -attr oid 597 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load net {ACC1-2:exs#90.itm(0)} -attr vt d
+load net {ACC1-2:exs#90.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#90.itm} 2 {ACC1-2:exs#90.itm(0)} {ACC1-2:exs#90.itm(1)} -attr xrf 52542 -attr oid 598 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#90.itm}
+load net {ACC1-2:exs#91.itm(0)} -attr vt d
+load net {ACC1-2:exs#91.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#91.itm} 2 {ACC1-2:exs#91.itm(0)} {ACC1-2:exs#91.itm(1)} -attr xrf 52543 -attr oid 599 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#91.itm}
+load net {ACC1:acc#487.itm(0)} -attr vt d
+load net {ACC1:acc#487.itm(1)} -attr vt d
+load net {ACC1:acc#487.itm(2)} -attr vt d
+load netBundle {ACC1:acc#487.itm} 3 {ACC1:acc#487.itm(0)} {ACC1:acc#487.itm(1)} {ACC1:acc#487.itm(2)} -attr xrf 52544 -attr oid 600 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load net {ACC1-2:exs#92.itm(0)} -attr vt d
+load net {ACC1-2:exs#92.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#92.itm} 2 {ACC1-2:exs#92.itm(0)} {ACC1-2:exs#92.itm(1)} -attr xrf 52545 -attr oid 601 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#92.itm}
+load net {ACC1-2:exs#1056.itm(0)} -attr vt d
+load net {ACC1-2:exs#1056.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1056.itm} 2 {ACC1-2:exs#1056.itm(0)} {ACC1-2:exs#1056.itm(1)} -attr xrf 52546 -attr oid 602 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1056.itm}
+load net {ACC1:acc#610.itm(0)} -attr vt d
+load net {ACC1:acc#610.itm(1)} -attr vt d
+load net {ACC1:acc#610.itm(2)} -attr vt d
+load net {ACC1:acc#610.itm(3)} -attr vt d
+load net {ACC1:acc#610.itm(4)} -attr vt d
+load net {ACC1:acc#610.itm(5)} -attr vt d
+load netBundle {ACC1:acc#610.itm} 6 {ACC1:acc#610.itm(0)} {ACC1:acc#610.itm(1)} {ACC1:acc#610.itm(2)} {ACC1:acc#610.itm(3)} {ACC1:acc#610.itm(4)} {ACC1:acc#610.itm(5)} -attr xrf 52547 -attr oid 603 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#591.itm(0)} -attr vt d
+load net {ACC1:acc#591.itm(1)} -attr vt d
+load net {ACC1:acc#591.itm(2)} -attr vt d
+load net {ACC1:acc#591.itm(3)} -attr vt d
+load net {ACC1:acc#591.itm(4)} -attr vt d
+load netBundle {ACC1:acc#591.itm} 5 {ACC1:acc#591.itm(0)} {ACC1:acc#591.itm(1)} {ACC1:acc#591.itm(2)} {ACC1:acc#591.itm(3)} {ACC1:acc#591.itm(4)} -attr xrf 52548 -attr oid 604 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#551.itm(0)} -attr vt d
+load net {ACC1:acc#551.itm(1)} -attr vt d
+load net {ACC1:acc#551.itm(2)} -attr vt d
+load net {ACC1:acc#551.itm(3)} -attr vt d
+load netBundle {ACC1:acc#551.itm} 4 {ACC1:acc#551.itm(0)} {ACC1:acc#551.itm(1)} {ACC1:acc#551.itm(2)} {ACC1:acc#551.itm(3)} -attr xrf 52549 -attr oid 605 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#482.itm(0)} -attr vt d
+load net {ACC1:acc#482.itm(1)} -attr vt d
+load net {ACC1:acc#482.itm(2)} -attr vt d
+load netBundle {ACC1:acc#482.itm} 3 {ACC1:acc#482.itm(0)} {ACC1:acc#482.itm(1)} {ACC1:acc#482.itm(2)} -attr xrf 52550 -attr oid 606 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load net {ACC1-2:exs#1057.itm(0)} -attr vt d
+load net {ACC1-2:exs#1057.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1057.itm} 2 {ACC1-2:exs#1057.itm(0)} {ACC1-2:exs#1057.itm(1)} -attr xrf 52551 -attr oid 607 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1057.itm}
+load net {ACC1-2:exs#963.itm(0)} -attr vt d
+load net {ACC1-2:exs#963.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#963.itm} 2 {ACC1-2:exs#963.itm(0)} {ACC1-2:exs#963.itm(1)} -attr xrf 52552 -attr oid 608 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#963.itm}
+load net {ACC1:acc#590.itm(0)} -attr vt d
+load net {ACC1:acc#590.itm(1)} -attr vt d
+load net {ACC1:acc#590.itm(2)} -attr vt d
+load net {ACC1:acc#590.itm(3)} -attr vt d
+load net {ACC1:acc#590.itm(4)} -attr vt d
+load netBundle {ACC1:acc#590.itm} 5 {ACC1:acc#590.itm(0)} {ACC1:acc#590.itm(1)} {ACC1:acc#590.itm(2)} {ACC1:acc#590.itm(3)} {ACC1:acc#590.itm(4)} -attr xrf 52553 -attr oid 609 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#550.itm(0)} -attr vt d
+load net {ACC1:acc#550.itm(1)} -attr vt d
+load net {ACC1:acc#550.itm(2)} -attr vt d
+load net {ACC1:acc#550.itm(3)} -attr vt d
+load netBundle {ACC1:acc#550.itm} 4 {ACC1:acc#550.itm(0)} {ACC1:acc#550.itm(1)} {ACC1:acc#550.itm(2)} {ACC1:acc#550.itm(3)} -attr xrf 52554 -attr oid 610 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:slc#147.itm(0)} -attr vt d
+load net {ACC1:slc#147.itm(1)} -attr vt d
+load net {ACC1:slc#147.itm(2)} -attr vt d
+load netBundle {ACC1:slc#147.itm} 3 {ACC1:slc#147.itm(0)} {ACC1:slc#147.itm(1)} {ACC1:slc#147.itm(2)} -attr xrf 52555 -attr oid 611 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#147.itm}
+load net {ACC1:acc#479.itm(0)} -attr vt d
+load net {ACC1:acc#479.itm(1)} -attr vt d
+load net {ACC1:acc#479.itm(2)} -attr vt d
+load net {ACC1:acc#479.itm(3)} -attr vt d
+load netBundle {ACC1:acc#479.itm} 4 {ACC1:acc#479.itm(0)} {ACC1:acc#479.itm(1)} {ACC1:acc#479.itm(2)} {ACC1:acc#479.itm(3)} -attr xrf 52556 -attr oid 612 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#479.itm}
+load net {exs#97.itm(0)} -attr vt d
+load net {exs#97.itm(1)} -attr vt d
+load net {exs#97.itm(2)} -attr vt d
+load netBundle {exs#97.itm} 3 {exs#97.itm(0)} {exs#97.itm(1)} {exs#97.itm(2)} -attr xrf 52557 -attr oid 613 -attr vt d -attr @path {/sobel/sobel:core/exs#97.itm}
+load net {conc#957.itm(0)} -attr vt d
+load net {conc#957.itm(1)} -attr vt d
+load netBundle {conc#957.itm} 2 {conc#957.itm(0)} {conc#957.itm(1)} -attr xrf 52558 -attr oid 614 -attr vt d -attr @path {/sobel/sobel:core/conc#957.itm}
+load net {ACC1:exs#1552.itm(0)} -attr vt d
+load net {ACC1:exs#1552.itm(1)} -attr vt d
+load net {ACC1:exs#1552.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1552.itm} 3 {ACC1:exs#1552.itm(0)} {ACC1:exs#1552.itm(1)} {ACC1:exs#1552.itm(2)} -attr xrf 52559 -attr oid 615 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1552.itm}
+load net {ACC1:conc#1417.itm(0)} -attr vt d
+load net {ACC1:conc#1417.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1417.itm} 2 {ACC1:conc#1417.itm(0)} {ACC1:conc#1417.itm(1)} -attr xrf 52560 -attr oid 616 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1417.itm}
+load net {ACC1:acc#549.itm(0)} -attr vt d
+load net {ACC1:acc#549.itm(1)} -attr vt d
+load net {ACC1:acc#549.itm(2)} -attr vt d
+load net {ACC1:acc#549.itm(3)} -attr vt d
+load netBundle {ACC1:acc#549.itm} 4 {ACC1:acc#549.itm(0)} {ACC1:acc#549.itm(1)} {ACC1:acc#549.itm(2)} {ACC1:acc#549.itm(3)} -attr xrf 52561 -attr oid 617 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:slc#146.itm(0)} -attr vt d
+load net {ACC1:slc#146.itm(1)} -attr vt d
+load net {ACC1:slc#146.itm(2)} -attr vt d
+load netBundle {ACC1:slc#146.itm} 3 {ACC1:slc#146.itm(0)} {ACC1:slc#146.itm(1)} {ACC1:slc#146.itm(2)} -attr xrf 52562 -attr oid 618 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#146.itm}
+load net {ACC1:acc#478.itm(0)} -attr vt d
+load net {ACC1:acc#478.itm(1)} -attr vt d
+load net {ACC1:acc#478.itm(2)} -attr vt d
+load net {ACC1:acc#478.itm(3)} -attr vt d
+load netBundle {ACC1:acc#478.itm} 4 {ACC1:acc#478.itm(0)} {ACC1:acc#478.itm(1)} {ACC1:acc#478.itm(2)} {ACC1:acc#478.itm(3)} -attr xrf 52563 -attr oid 619 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#478.itm}
+load net {exs#98.itm(0)} -attr vt d
+load net {exs#98.itm(1)} -attr vt d
+load net {exs#98.itm(2)} -attr vt d
+load netBundle {exs#98.itm} 3 {exs#98.itm(0)} {exs#98.itm(1)} {exs#98.itm(2)} -attr xrf 52564 -attr oid 620 -attr vt d -attr @path {/sobel/sobel:core/exs#98.itm}
+load net {conc#959.itm(0)} -attr vt d
+load net {conc#959.itm(1)} -attr vt d
+load netBundle {conc#959.itm} 2 {conc#959.itm(0)} {conc#959.itm(1)} -attr xrf 52565 -attr oid 621 -attr vt d -attr @path {/sobel/sobel:core/conc#959.itm}
+load net {ACC1:exs#1554.itm(0)} -attr vt d
+load net {ACC1:exs#1554.itm(1)} -attr vt d
+load net {ACC1:exs#1554.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1554.itm} 3 {ACC1:exs#1554.itm(0)} {ACC1:exs#1554.itm(1)} {ACC1:exs#1554.itm(2)} -attr xrf 52566 -attr oid 622 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1554.itm}
+load net {ACC1:conc#1415.itm(0)} -attr vt d
+load net {ACC1:conc#1415.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1415.itm} 2 {ACC1:conc#1415.itm(0)} {ACC1:conc#1415.itm(1)} -attr xrf 52567 -attr oid 623 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1415.itm}
+load net {ACC1:slc#145.itm(0)} -attr vt d
+load net {ACC1:slc#145.itm(1)} -attr vt d
+load net {ACC1:slc#145.itm(2)} -attr vt d
+load netBundle {ACC1:slc#145.itm} 3 {ACC1:slc#145.itm(0)} {ACC1:slc#145.itm(1)} {ACC1:slc#145.itm(2)} -attr xrf 52568 -attr oid 624 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#145.itm}
+load net {ACC1:acc#477.itm(0)} -attr vt d
+load net {ACC1:acc#477.itm(1)} -attr vt d
+load net {ACC1:acc#477.itm(2)} -attr vt d
+load net {ACC1:acc#477.itm(3)} -attr vt d
+load netBundle {ACC1:acc#477.itm} 4 {ACC1:acc#477.itm(0)} {ACC1:acc#477.itm(1)} {ACC1:acc#477.itm(2)} {ACC1:acc#477.itm(3)} -attr xrf 52569 -attr oid 625 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#477.itm}
+load net {exs#77.itm(0)} -attr vt d
+load net {exs#77.itm(1)} -attr vt d
+load net {exs#77.itm(2)} -attr vt d
+load netBundle {exs#77.itm} 3 {exs#77.itm(0)} {exs#77.itm(1)} {exs#77.itm(2)} -attr xrf 52570 -attr oid 626 -attr vt d -attr @path {/sobel/sobel:core/exs#77.itm}
+load net {conc#961.itm(0)} -attr vt d
+load net {conc#961.itm(1)} -attr vt d
+load netBundle {conc#961.itm} 2 {conc#961.itm(0)} {conc#961.itm(1)} -attr xrf 52571 -attr oid 627 -attr vt d -attr @path {/sobel/sobel:core/conc#961.itm}
+load net {ACC1:exs#1556.itm(0)} -attr vt d
+load net {ACC1:exs#1556.itm(1)} -attr vt d
+load net {ACC1:exs#1556.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1556.itm} 3 {ACC1:exs#1556.itm(0)} {ACC1:exs#1556.itm(1)} {ACC1:exs#1556.itm(2)} -attr xrf 52572 -attr oid 628 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1556.itm}
+load net {ACC1:conc#1413.itm(0)} -attr vt d
+load net {ACC1:conc#1413.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1413.itm} 2 {ACC1:conc#1413.itm(0)} {ACC1:conc#1413.itm(1)} -attr xrf 52573 -attr oid 629 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1413.itm}
+load net {ACC1:acc#624.itm(0)} -attr vt d
+load net {ACC1:acc#624.itm(1)} -attr vt d
+load net {ACC1:acc#624.itm(2)} -attr vt d
+load net {ACC1:acc#624.itm(3)} -attr vt d
+load net {ACC1:acc#624.itm(4)} -attr vt d
+load net {ACC1:acc#624.itm(5)} -attr vt d
+load net {ACC1:acc#624.itm(6)} -attr vt d
+load netBundle {ACC1:acc#624.itm} 7 {ACC1:acc#624.itm(0)} {ACC1:acc#624.itm(1)} {ACC1:acc#624.itm(2)} {ACC1:acc#624.itm(3)} {ACC1:acc#624.itm(4)} {ACC1:acc#624.itm(5)} {ACC1:acc#624.itm(6)} -attr xrf 52574 -attr oid 630 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#609.itm(0)} -attr vt d
+load net {ACC1:acc#609.itm(1)} -attr vt d
+load net {ACC1:acc#609.itm(2)} -attr vt d
+load net {ACC1:acc#609.itm(3)} -attr vt d
+load net {ACC1:acc#609.itm(4)} -attr vt d
+load net {ACC1:acc#609.itm(5)} -attr vt d
+load netBundle {ACC1:acc#609.itm} 6 {ACC1:acc#609.itm(0)} {ACC1:acc#609.itm(1)} {ACC1:acc#609.itm(2)} {ACC1:acc#609.itm(3)} {ACC1:acc#609.itm(4)} {ACC1:acc#609.itm(5)} -attr xrf 52575 -attr oid 631 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#589.itm(0)} -attr vt d
+load net {ACC1:acc#589.itm(1)} -attr vt d
+load net {ACC1:acc#589.itm(2)} -attr vt d
+load net {ACC1:acc#589.itm(3)} -attr vt d
+load net {ACC1:acc#589.itm(4)} -attr vt d
+load netBundle {ACC1:acc#589.itm} 5 {ACC1:acc#589.itm(0)} {ACC1:acc#589.itm(1)} {ACC1:acc#589.itm(2)} {ACC1:acc#589.itm(3)} {ACC1:acc#589.itm(4)} -attr xrf 52576 -attr oid 632 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#548.itm(0)} -attr vt d
+load net {ACC1:acc#548.itm(1)} -attr vt d
+load net {ACC1:acc#548.itm(2)} -attr vt d
+load net {ACC1:acc#548.itm(3)} -attr vt d
+load netBundle {ACC1:acc#548.itm} 4 {ACC1:acc#548.itm(0)} {ACC1:acc#548.itm(1)} {ACC1:acc#548.itm(2)} {ACC1:acc#548.itm(3)} -attr xrf 52577 -attr oid 633 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:slc#144.itm(0)} -attr vt d
+load net {ACC1:slc#144.itm(1)} -attr vt d
+load net {ACC1:slc#144.itm(2)} -attr vt d
+load netBundle {ACC1:slc#144.itm} 3 {ACC1:slc#144.itm(0)} {ACC1:slc#144.itm(1)} {ACC1:slc#144.itm(2)} -attr xrf 52578 -attr oid 634 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#144.itm}
+load net {ACC1:acc#476.itm(0)} -attr vt d
+load net {ACC1:acc#476.itm(1)} -attr vt d
+load net {ACC1:acc#476.itm(2)} -attr vt d
+load net {ACC1:acc#476.itm(3)} -attr vt d
+load netBundle {ACC1:acc#476.itm} 4 {ACC1:acc#476.itm(0)} {ACC1:acc#476.itm(1)} {ACC1:acc#476.itm(2)} {ACC1:acc#476.itm(3)} -attr xrf 52579 -attr oid 635 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#476.itm}
+load net {exs#78.itm(0)} -attr vt d
+load net {exs#78.itm(1)} -attr vt d
+load net {exs#78.itm(2)} -attr vt d
+load netBundle {exs#78.itm} 3 {exs#78.itm(0)} {exs#78.itm(1)} {exs#78.itm(2)} -attr xrf 52580 -attr oid 636 -attr vt d -attr @path {/sobel/sobel:core/exs#78.itm}
+load net {conc#962.itm(0)} -attr vt d
+load net {conc#962.itm(1)} -attr vt d
+load netBundle {conc#962.itm} 2 {conc#962.itm(0)} {conc#962.itm(1)} -attr xrf 52581 -attr oid 637 -attr vt d -attr @path {/sobel/sobel:core/conc#962.itm}
+load net {ACC1:exs#1558.itm(0)} -attr vt d
+load net {ACC1:exs#1558.itm(1)} -attr vt d
+load net {ACC1:exs#1558.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1558.itm} 3 {ACC1:exs#1558.itm(0)} {ACC1:exs#1558.itm(1)} {ACC1:exs#1558.itm(2)} -attr xrf 52582 -attr oid 638 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1558.itm}
+load net {ACC1:conc#1411.itm(0)} -attr vt d
+load net {ACC1:conc#1411.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1411.itm} 2 {ACC1:conc#1411.itm(0)} {ACC1:conc#1411.itm(1)} -attr xrf 52583 -attr oid 639 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1411.itm}
+load net {ACC1:slc#143.itm(0)} -attr vt d
+load net {ACC1:slc#143.itm(1)} -attr vt d
+load net {ACC1:slc#143.itm(2)} -attr vt d
+load netBundle {ACC1:slc#143.itm} 3 {ACC1:slc#143.itm(0)} {ACC1:slc#143.itm(1)} {ACC1:slc#143.itm(2)} -attr xrf 52584 -attr oid 640 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#143.itm}
+load net {ACC1:acc#475.itm(0)} -attr vt d
+load net {ACC1:acc#475.itm(1)} -attr vt d
+load net {ACC1:acc#475.itm(2)} -attr vt d
+load net {ACC1:acc#475.itm(3)} -attr vt d
+load netBundle {ACC1:acc#475.itm} 4 {ACC1:acc#475.itm(0)} {ACC1:acc#475.itm(1)} {ACC1:acc#475.itm(2)} {ACC1:acc#475.itm(3)} -attr xrf 52585 -attr oid 641 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#475.itm}
+load net {exs#79.itm(0)} -attr vt d
+load net {exs#79.itm(1)} -attr vt d
+load net {exs#79.itm(2)} -attr vt d
+load netBundle {exs#79.itm} 3 {exs#79.itm(0)} {exs#79.itm(1)} {exs#79.itm(2)} -attr xrf 52586 -attr oid 642 -attr vt d -attr @path {/sobel/sobel:core/exs#79.itm}
+load net {conc#963.itm(0)} -attr vt d
+load net {conc#963.itm(1)} -attr vt d
+load netBundle {conc#963.itm} 2 {conc#963.itm(0)} {conc#963.itm(1)} -attr xrf 52587 -attr oid 643 -attr vt d -attr @path {/sobel/sobel:core/conc#963.itm}
+load net {ACC1:exs#1560.itm(0)} -attr vt d
+load net {ACC1:exs#1560.itm(1)} -attr vt d
+load net {ACC1:exs#1560.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1560.itm} 3 {ACC1:exs#1560.itm(0)} {ACC1:exs#1560.itm(1)} {ACC1:exs#1560.itm(2)} -attr xrf 52588 -attr oid 644 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1560.itm}
+load net {ACC1:conc#1409.itm(0)} -attr vt d
+load net {ACC1:conc#1409.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1409.itm} 2 {ACC1:conc#1409.itm(0)} {ACC1:conc#1409.itm(1)} -attr xrf 52589 -attr oid 645 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1409.itm}
+load net {ACC1:acc#547.itm(0)} -attr vt d
+load net {ACC1:acc#547.itm(1)} -attr vt d
+load net {ACC1:acc#547.itm(2)} -attr vt d
+load net {ACC1:acc#547.itm(3)} -attr vt d
+load netBundle {ACC1:acc#547.itm} 4 {ACC1:acc#547.itm(0)} {ACC1:acc#547.itm(1)} {ACC1:acc#547.itm(2)} {ACC1:acc#547.itm(3)} -attr xrf 52590 -attr oid 646 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:slc#142.itm(0)} -attr vt d
+load net {ACC1:slc#142.itm(1)} -attr vt d
+load net {ACC1:slc#142.itm(2)} -attr vt d
+load netBundle {ACC1:slc#142.itm} 3 {ACC1:slc#142.itm(0)} {ACC1:slc#142.itm(1)} {ACC1:slc#142.itm(2)} -attr xrf 52591 -attr oid 647 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#142.itm}
+load net {ACC1:acc#474.itm(0)} -attr vt d
+load net {ACC1:acc#474.itm(1)} -attr vt d
+load net {ACC1:acc#474.itm(2)} -attr vt d
+load net {ACC1:acc#474.itm(3)} -attr vt d
+load netBundle {ACC1:acc#474.itm} 4 {ACC1:acc#474.itm(0)} {ACC1:acc#474.itm(1)} {ACC1:acc#474.itm(2)} {ACC1:acc#474.itm(3)} -attr xrf 52592 -attr oid 648 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#474.itm}
+load net {exs#80.itm(0)} -attr vt d
+load net {exs#80.itm(1)} -attr vt d
+load net {exs#80.itm(2)} -attr vt d
+load netBundle {exs#80.itm} 3 {exs#80.itm(0)} {exs#80.itm(1)} {exs#80.itm(2)} -attr xrf 52593 -attr oid 649 -attr vt d -attr @path {/sobel/sobel:core/exs#80.itm}
+load net {conc#964.itm(0)} -attr vt d
+load net {conc#964.itm(1)} -attr vt d
+load netBundle {conc#964.itm} 2 {conc#964.itm(0)} {conc#964.itm(1)} -attr xrf 52594 -attr oid 650 -attr vt d -attr @path {/sobel/sobel:core/conc#964.itm}
+load net {ACC1:exs#1562.itm(0)} -attr vt d
+load net {ACC1:exs#1562.itm(1)} -attr vt d
+load net {ACC1:exs#1562.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1562.itm} 3 {ACC1:exs#1562.itm(0)} {ACC1:exs#1562.itm(1)} {ACC1:exs#1562.itm(2)} -attr xrf 52595 -attr oid 651 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1562.itm}
+load net {ACC1:conc#1407.itm(0)} -attr vt d
+load net {ACC1:conc#1407.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1407.itm} 2 {ACC1:conc#1407.itm(0)} {ACC1:conc#1407.itm(1)} -attr xrf 52596 -attr oid 652 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1407.itm}
+load net {ACC1:slc#141.itm(0)} -attr vt d
+load net {ACC1:slc#141.itm(1)} -attr vt d
+load net {ACC1:slc#141.itm(2)} -attr vt d
+load netBundle {ACC1:slc#141.itm} 3 {ACC1:slc#141.itm(0)} {ACC1:slc#141.itm(1)} {ACC1:slc#141.itm(2)} -attr xrf 52597 -attr oid 653 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#141.itm}
+load net {ACC1:acc#473.itm(0)} -attr vt d
+load net {ACC1:acc#473.itm(1)} -attr vt d
+load net {ACC1:acc#473.itm(2)} -attr vt d
+load net {ACC1:acc#473.itm(3)} -attr vt d
+load netBundle {ACC1:acc#473.itm} 4 {ACC1:acc#473.itm(0)} {ACC1:acc#473.itm(1)} {ACC1:acc#473.itm(2)} {ACC1:acc#473.itm(3)} -attr xrf 52598 -attr oid 654 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#473.itm}
+load net {exs#99.itm(0)} -attr vt d
+load net {exs#99.itm(1)} -attr vt d
+load net {exs#99.itm(2)} -attr vt d
+load netBundle {exs#99.itm} 3 {exs#99.itm(0)} {exs#99.itm(1)} {exs#99.itm(2)} -attr xrf 52599 -attr oid 655 -attr vt d -attr @path {/sobel/sobel:core/exs#99.itm}
+load net {conc#965.itm(0)} -attr vt d
+load net {conc#965.itm(1)} -attr vt d
+load netBundle {conc#965.itm} 2 {conc#965.itm(0)} {conc#965.itm(1)} -attr xrf 52600 -attr oid 656 -attr vt d -attr @path {/sobel/sobel:core/conc#965.itm}
+load net {ACC1:exs#1564.itm(0)} -attr vt d
+load net {ACC1:exs#1564.itm(1)} -attr vt d
+load net {ACC1:exs#1564.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1564.itm} 3 {ACC1:exs#1564.itm(0)} {ACC1:exs#1564.itm(1)} {ACC1:exs#1564.itm(2)} -attr xrf 52601 -attr oid 657 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1564.itm}
+load net {ACC1:conc#1405.itm(0)} -attr vt d
+load net {ACC1:conc#1405.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1405.itm} 2 {ACC1:conc#1405.itm(0)} {ACC1:conc#1405.itm(1)} -attr xrf 52602 -attr oid 658 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1405.itm}
+load net {ACC1:acc#588.itm(0)} -attr vt d
+load net {ACC1:acc#588.itm(1)} -attr vt d
+load net {ACC1:acc#588.itm(2)} -attr vt d
+load net {ACC1:acc#588.itm(3)} -attr vt d
+load net {ACC1:acc#588.itm(4)} -attr vt d
+load netBundle {ACC1:acc#588.itm} 5 {ACC1:acc#588.itm(0)} {ACC1:acc#588.itm(1)} {ACC1:acc#588.itm(2)} {ACC1:acc#588.itm(3)} {ACC1:acc#588.itm(4)} -attr xrf 52603 -attr oid 659 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#546.itm(0)} -attr vt d
+load net {ACC1:acc#546.itm(1)} -attr vt d
+load net {ACC1:acc#546.itm(2)} -attr vt d
+load net {ACC1:acc#546.itm(3)} -attr vt d
+load netBundle {ACC1:acc#546.itm} 4 {ACC1:acc#546.itm(0)} {ACC1:acc#546.itm(1)} {ACC1:acc#546.itm(2)} {ACC1:acc#546.itm(3)} -attr xrf 52604 -attr oid 660 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:slc#140.itm(0)} -attr vt d
+load net {ACC1:slc#140.itm(1)} -attr vt d
+load net {ACC1:slc#140.itm(2)} -attr vt d
+load netBundle {ACC1:slc#140.itm} 3 {ACC1:slc#140.itm(0)} {ACC1:slc#140.itm(1)} {ACC1:slc#140.itm(2)} -attr xrf 52605 -attr oid 661 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#140.itm}
+load net {ACC1:acc#472.itm(0)} -attr vt d
+load net {ACC1:acc#472.itm(1)} -attr vt d
+load net {ACC1:acc#472.itm(2)} -attr vt d
+load net {ACC1:acc#472.itm(3)} -attr vt d
+load netBundle {ACC1:acc#472.itm} 4 {ACC1:acc#472.itm(0)} {ACC1:acc#472.itm(1)} {ACC1:acc#472.itm(2)} {ACC1:acc#472.itm(3)} -attr xrf 52606 -attr oid 662 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#472.itm}
+load net {exs#81.itm(0)} -attr vt d
+load net {exs#81.itm(1)} -attr vt d
+load net {exs#81.itm(2)} -attr vt d
+load netBundle {exs#81.itm} 3 {exs#81.itm(0)} {exs#81.itm(1)} {exs#81.itm(2)} -attr xrf 52607 -attr oid 663 -attr vt d -attr @path {/sobel/sobel:core/exs#81.itm}
+load net {conc#967.itm(0)} -attr vt d
+load net {conc#967.itm(1)} -attr vt d
+load netBundle {conc#967.itm} 2 {conc#967.itm(0)} {conc#967.itm(1)} -attr xrf 52608 -attr oid 664 -attr vt d -attr @path {/sobel/sobel:core/conc#967.itm}
+load net {ACC1:exs#1566.itm(0)} -attr vt d
+load net {ACC1:exs#1566.itm(1)} -attr vt d
+load net {ACC1:exs#1566.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1566.itm} 3 {ACC1:exs#1566.itm(0)} {ACC1:exs#1566.itm(1)} {ACC1:exs#1566.itm(2)} -attr xrf 52609 -attr oid 665 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1566.itm}
+load net {ACC1:conc#1403.itm(0)} -attr vt d
+load net {ACC1:conc#1403.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1403.itm} 2 {ACC1:conc#1403.itm(0)} {ACC1:conc#1403.itm(1)} -attr xrf 52610 -attr oid 666 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1403.itm}
+load net {ACC1:slc#138.itm(0)} -attr vt d
+load net {ACC1:slc#138.itm(1)} -attr vt d
+load net {ACC1:slc#138.itm(2)} -attr vt d
+load netBundle {ACC1:slc#138.itm} 3 {ACC1:slc#138.itm(0)} {ACC1:slc#138.itm(1)} {ACC1:slc#138.itm(2)} -attr xrf 52611 -attr oid 667 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#138.itm}
+load net {ACC1:acc#470.itm(0)} -attr vt d
+load net {ACC1:acc#470.itm(1)} -attr vt d
+load net {ACC1:acc#470.itm(2)} -attr vt d
+load net {ACC1:acc#470.itm(3)} -attr vt d
+load netBundle {ACC1:acc#470.itm} 4 {ACC1:acc#470.itm(0)} {ACC1:acc#470.itm(1)} {ACC1:acc#470.itm(2)} {ACC1:acc#470.itm(3)} -attr xrf 52612 -attr oid 668 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#470.itm}
+load net {exs#82.itm(0)} -attr vt d
+load net {exs#82.itm(1)} -attr vt d
+load net {exs#82.itm(2)} -attr vt d
+load netBundle {exs#82.itm} 3 {exs#82.itm(0)} {exs#82.itm(1)} {exs#82.itm(2)} -attr xrf 52613 -attr oid 669 -attr vt d -attr @path {/sobel/sobel:core/exs#82.itm}
+load net {conc#968.itm(0)} -attr vt d
+load net {conc#968.itm(1)} -attr vt d
+load netBundle {conc#968.itm} 2 {conc#968.itm(0)} {conc#968.itm(1)} -attr xrf 52614 -attr oid 670 -attr vt d -attr @path {/sobel/sobel:core/conc#968.itm}
+load net {ACC1:exs#1568.itm(0)} -attr vt d
+load net {ACC1:exs#1568.itm(1)} -attr vt d
+load net {ACC1:exs#1568.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1568.itm} 3 {ACC1:exs#1568.itm(0)} {ACC1:exs#1568.itm(1)} {ACC1:exs#1568.itm(2)} -attr xrf 52615 -attr oid 671 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1568.itm}
+load net {ACC1:conc#1399.itm(0)} -attr vt d
+load net {ACC1:conc#1399.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1399.itm} 2 {ACC1:conc#1399.itm(0)} {ACC1:conc#1399.itm(1)} -attr xrf 52616 -attr oid 672 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1399.itm}
+load net {ACC1:acc#545.itm(0)} -attr vt d
+load net {ACC1:acc#545.itm(1)} -attr vt d
+load net {ACC1:acc#545.itm(2)} -attr vt d
+load net {ACC1:acc#545.itm(3)} -attr vt d
+load netBundle {ACC1:acc#545.itm} 4 {ACC1:acc#545.itm(0)} {ACC1:acc#545.itm(1)} {ACC1:acc#545.itm(2)} {ACC1:acc#545.itm(3)} -attr xrf 52617 -attr oid 673 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:slc#137.itm(0)} -attr vt d
+load net {ACC1:slc#137.itm(1)} -attr vt d
+load net {ACC1:slc#137.itm(2)} -attr vt d
+load netBundle {ACC1:slc#137.itm} 3 {ACC1:slc#137.itm(0)} {ACC1:slc#137.itm(1)} {ACC1:slc#137.itm(2)} -attr xrf 52618 -attr oid 674 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#137.itm}
+load net {ACC1:acc#469.itm(0)} -attr vt d
+load net {ACC1:acc#469.itm(1)} -attr vt d
+load net {ACC1:acc#469.itm(2)} -attr vt d
+load net {ACC1:acc#469.itm(3)} -attr vt d
+load netBundle {ACC1:acc#469.itm} 4 {ACC1:acc#469.itm(0)} {ACC1:acc#469.itm(1)} {ACC1:acc#469.itm(2)} {ACC1:acc#469.itm(3)} -attr xrf 52619 -attr oid 675 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#469.itm}
+load net {exs#83.itm(0)} -attr vt d
+load net {exs#83.itm(1)} -attr vt d
+load net {exs#83.itm(2)} -attr vt d
+load netBundle {exs#83.itm} 3 {exs#83.itm(0)} {exs#83.itm(1)} {exs#83.itm(2)} -attr xrf 52620 -attr oid 676 -attr vt d -attr @path {/sobel/sobel:core/exs#83.itm}
+load net {conc#969.itm(0)} -attr vt d
+load net {conc#969.itm(1)} -attr vt d
+load netBundle {conc#969.itm} 2 {conc#969.itm(0)} {conc#969.itm(1)} -attr xrf 52621 -attr oid 677 -attr vt d -attr @path {/sobel/sobel:core/conc#969.itm}
+load net {ACC1:exs#1570.itm(0)} -attr vt d
+load net {ACC1:exs#1570.itm(1)} -attr vt d
+load net {ACC1:exs#1570.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1570.itm} 3 {ACC1:exs#1570.itm(0)} {ACC1:exs#1570.itm(1)} {ACC1:exs#1570.itm(2)} -attr xrf 52622 -attr oid 678 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1570.itm}
+load net {ACC1:conc#1397.itm(0)} -attr vt d
+load net {ACC1:conc#1397.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1397.itm} 2 {ACC1:conc#1397.itm(0)} {ACC1:conc#1397.itm(1)} -attr xrf 52623 -attr oid 679 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1397.itm}
+load net {ACC1:slc#136.itm(0)} -attr vt d
+load net {ACC1:slc#136.itm(1)} -attr vt d
+load net {ACC1:slc#136.itm(2)} -attr vt d
+load netBundle {ACC1:slc#136.itm} 3 {ACC1:slc#136.itm(0)} {ACC1:slc#136.itm(1)} {ACC1:slc#136.itm(2)} -attr xrf 52624 -attr oid 680 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#136.itm}
+load net {ACC1:acc#468.itm(0)} -attr vt d
+load net {ACC1:acc#468.itm(1)} -attr vt d
+load net {ACC1:acc#468.itm(2)} -attr vt d
+load net {ACC1:acc#468.itm(3)} -attr vt d
+load netBundle {ACC1:acc#468.itm} 4 {ACC1:acc#468.itm(0)} {ACC1:acc#468.itm(1)} {ACC1:acc#468.itm(2)} {ACC1:acc#468.itm(3)} -attr xrf 52625 -attr oid 681 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#468.itm}
+load net {exs#100.itm(0)} -attr vt d
+load net {exs#100.itm(1)} -attr vt d
+load net {exs#100.itm(2)} -attr vt d
+load netBundle {exs#100.itm} 3 {exs#100.itm(0)} {exs#100.itm(1)} {exs#100.itm(2)} -attr xrf 52626 -attr oid 682 -attr vt d -attr @path {/sobel/sobel:core/exs#100.itm}
+load net {conc#970.itm(0)} -attr vt d
+load net {conc#970.itm(1)} -attr vt d
+load netBundle {conc#970.itm} 2 {conc#970.itm(0)} {conc#970.itm(1)} -attr xrf 52627 -attr oid 683 -attr vt d -attr @path {/sobel/sobel:core/conc#970.itm}
+load net {ACC1:exs#1572.itm(0)} -attr vt d
+load net {ACC1:exs#1572.itm(1)} -attr vt d
+load net {ACC1:exs#1572.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1572.itm} 3 {ACC1:exs#1572.itm(0)} {ACC1:exs#1572.itm(1)} {ACC1:exs#1572.itm(2)} -attr xrf 52628 -attr oid 684 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1572.itm}
+load net {ACC1:conc#1395.itm(0)} -attr vt d
+load net {ACC1:conc#1395.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1395.itm} 2 {ACC1:conc#1395.itm(0)} {ACC1:conc#1395.itm(1)} -attr xrf 52629 -attr oid 685 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1395.itm}
+load net {ACC1:acc#608.itm(0)} -attr vt d
+load net {ACC1:acc#608.itm(1)} -attr vt d
+load net {ACC1:acc#608.itm(2)} -attr vt d
+load net {ACC1:acc#608.itm(3)} -attr vt d
+load net {ACC1:acc#608.itm(4)} -attr vt d
+load net {ACC1:acc#608.itm(5)} -attr vt d
+load netBundle {ACC1:acc#608.itm} 6 {ACC1:acc#608.itm(0)} {ACC1:acc#608.itm(1)} {ACC1:acc#608.itm(2)} {ACC1:acc#608.itm(3)} {ACC1:acc#608.itm(4)} {ACC1:acc#608.itm(5)} -attr xrf 52630 -attr oid 686 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#587.itm(0)} -attr vt d
+load net {ACC1:acc#587.itm(1)} -attr vt d
+load net {ACC1:acc#587.itm(2)} -attr vt d
+load net {ACC1:acc#587.itm(3)} -attr vt d
+load net {ACC1:acc#587.itm(4)} -attr vt d
+load netBundle {ACC1:acc#587.itm} 5 {ACC1:acc#587.itm(0)} {ACC1:acc#587.itm(1)} {ACC1:acc#587.itm(2)} {ACC1:acc#587.itm(3)} {ACC1:acc#587.itm(4)} -attr xrf 52631 -attr oid 687 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#544.itm(0)} -attr vt d
+load net {ACC1:acc#544.itm(1)} -attr vt d
+load net {ACC1:acc#544.itm(2)} -attr vt d
+load net {ACC1:acc#544.itm(3)} -attr vt d
+load netBundle {ACC1:acc#544.itm} 4 {ACC1:acc#544.itm(0)} {ACC1:acc#544.itm(1)} {ACC1:acc#544.itm(2)} {ACC1:acc#544.itm(3)} -attr xrf 52632 -attr oid 688 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:slc#135.itm(0)} -attr vt d
+load net {ACC1:slc#135.itm(1)} -attr vt d
+load net {ACC1:slc#135.itm(2)} -attr vt d
+load netBundle {ACC1:slc#135.itm} 3 {ACC1:slc#135.itm(0)} {ACC1:slc#135.itm(1)} {ACC1:slc#135.itm(2)} -attr xrf 52633 -attr oid 689 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#135.itm}
+load net {ACC1:acc#467.itm(0)} -attr vt d
+load net {ACC1:acc#467.itm(1)} -attr vt d
+load net {ACC1:acc#467.itm(2)} -attr vt d
+load net {ACC1:acc#467.itm(3)} -attr vt d
+load netBundle {ACC1:acc#467.itm} 4 {ACC1:acc#467.itm(0)} {ACC1:acc#467.itm(1)} {ACC1:acc#467.itm(2)} {ACC1:acc#467.itm(3)} -attr xrf 52634 -attr oid 690 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#467.itm}
+load net {exs#101.itm(0)} -attr vt d
+load net {exs#101.itm(1)} -attr vt d
+load net {exs#101.itm(2)} -attr vt d
+load netBundle {exs#101.itm} 3 {exs#101.itm(0)} {exs#101.itm(1)} {exs#101.itm(2)} -attr xrf 52635 -attr oid 691 -attr vt d -attr @path {/sobel/sobel:core/exs#101.itm}
+load net {conc#972.itm(0)} -attr vt d
+load net {conc#972.itm(1)} -attr vt d
+load netBundle {conc#972.itm} 2 {conc#972.itm(0)} {conc#972.itm(1)} -attr xrf 52636 -attr oid 692 -attr vt d -attr @path {/sobel/sobel:core/conc#972.itm}
+load net {ACC1:exs#1574.itm(0)} -attr vt d
+load net {ACC1:exs#1574.itm(1)} -attr vt d
+load net {ACC1:exs#1574.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1574.itm} 3 {ACC1:exs#1574.itm(0)} {ACC1:exs#1574.itm(1)} {ACC1:exs#1574.itm(2)} -attr xrf 52637 -attr oid 693 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1574.itm}
+load net {ACC1:conc#1393.itm(0)} -attr vt d
+load net {ACC1:conc#1393.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1393.itm} 2 {ACC1:conc#1393.itm(0)} {ACC1:conc#1393.itm(1)} -attr xrf 52638 -attr oid 694 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1393.itm}
+load net {ACC1:slc#134.itm(0)} -attr vt d
+load net {ACC1:slc#134.itm(1)} -attr vt d
+load net {ACC1:slc#134.itm(2)} -attr vt d
+load netBundle {ACC1:slc#134.itm} 3 {ACC1:slc#134.itm(0)} {ACC1:slc#134.itm(1)} {ACC1:slc#134.itm(2)} -attr xrf 52639 -attr oid 695 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#134.itm}
+load net {ACC1:acc#466.itm(0)} -attr vt d
+load net {ACC1:acc#466.itm(1)} -attr vt d
+load net {ACC1:acc#466.itm(2)} -attr vt d
+load net {ACC1:acc#466.itm(3)} -attr vt d
+load netBundle {ACC1:acc#466.itm} 4 {ACC1:acc#466.itm(0)} {ACC1:acc#466.itm(1)} {ACC1:acc#466.itm(2)} {ACC1:acc#466.itm(3)} -attr xrf 52640 -attr oid 696 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#466.itm}
+load net {exs#84.itm(0)} -attr vt d
+load net {exs#84.itm(1)} -attr vt d
+load net {exs#84.itm(2)} -attr vt d
+load netBundle {exs#84.itm} 3 {exs#84.itm(0)} {exs#84.itm(1)} {exs#84.itm(2)} -attr xrf 52641 -attr oid 697 -attr vt d -attr @path {/sobel/sobel:core/exs#84.itm}
+load net {conc#974.itm(0)} -attr vt d
+load net {conc#974.itm(1)} -attr vt d
+load netBundle {conc#974.itm} 2 {conc#974.itm(0)} {conc#974.itm(1)} -attr xrf 52642 -attr oid 698 -attr vt d -attr @path {/sobel/sobel:core/conc#974.itm}
+load net {ACC1:exs#1576.itm(0)} -attr vt d
+load net {ACC1:exs#1576.itm(1)} -attr vt d
+load net {ACC1:exs#1576.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1576.itm} 3 {ACC1:exs#1576.itm(0)} {ACC1:exs#1576.itm(1)} {ACC1:exs#1576.itm(2)} -attr xrf 52643 -attr oid 699 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1576.itm}
+load net {ACC1:conc#1391.itm(0)} -attr vt d
+load net {ACC1:conc#1391.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1391.itm} 2 {ACC1:conc#1391.itm(0)} {ACC1:conc#1391.itm(1)} -attr xrf 52644 -attr oid 700 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1391.itm}
+load net {ACC1:acc#543.itm(0)} -attr vt d
+load net {ACC1:acc#543.itm(1)} -attr vt d
+load net {ACC1:acc#543.itm(2)} -attr vt d
+load net {ACC1:acc#543.itm(3)} -attr vt d
+load netBundle {ACC1:acc#543.itm} 4 {ACC1:acc#543.itm(0)} {ACC1:acc#543.itm(1)} {ACC1:acc#543.itm(2)} {ACC1:acc#543.itm(3)} -attr xrf 52645 -attr oid 701 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:slc#133.itm(0)} -attr vt d
+load net {ACC1:slc#133.itm(1)} -attr vt d
+load net {ACC1:slc#133.itm(2)} -attr vt d
+load netBundle {ACC1:slc#133.itm} 3 {ACC1:slc#133.itm(0)} {ACC1:slc#133.itm(1)} {ACC1:slc#133.itm(2)} -attr xrf 52646 -attr oid 702 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#133.itm}
+load net {ACC1:acc#465.itm(0)} -attr vt d
+load net {ACC1:acc#465.itm(1)} -attr vt d
+load net {ACC1:acc#465.itm(2)} -attr vt d
+load net {ACC1:acc#465.itm(3)} -attr vt d
+load netBundle {ACC1:acc#465.itm} 4 {ACC1:acc#465.itm(0)} {ACC1:acc#465.itm(1)} {ACC1:acc#465.itm(2)} {ACC1:acc#465.itm(3)} -attr xrf 52647 -attr oid 703 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#465.itm}
+load net {exs#85.itm(0)} -attr vt d
+load net {exs#85.itm(1)} -attr vt d
+load net {exs#85.itm(2)} -attr vt d
+load netBundle {exs#85.itm} 3 {exs#85.itm(0)} {exs#85.itm(1)} {exs#85.itm(2)} -attr xrf 52648 -attr oid 704 -attr vt d -attr @path {/sobel/sobel:core/exs#85.itm}
+load net {conc#975.itm(0)} -attr vt d
+load net {conc#975.itm(1)} -attr vt d
+load netBundle {conc#975.itm} 2 {conc#975.itm(0)} {conc#975.itm(1)} -attr xrf 52649 -attr oid 705 -attr vt d -attr @path {/sobel/sobel:core/conc#975.itm}
+load net {ACC1:exs#1578.itm(0)} -attr vt d
+load net {ACC1:exs#1578.itm(1)} -attr vt d
+load net {ACC1:exs#1578.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1578.itm} 3 {ACC1:exs#1578.itm(0)} {ACC1:exs#1578.itm(1)} {ACC1:exs#1578.itm(2)} -attr xrf 52650 -attr oid 706 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1578.itm}
+load net {ACC1:conc#1389.itm(0)} -attr vt d
+load net {ACC1:conc#1389.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1389.itm} 2 {ACC1:conc#1389.itm(0)} {ACC1:conc#1389.itm(1)} -attr xrf 52651 -attr oid 707 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1389.itm}
+load net {ACC1:slc#132.itm(0)} -attr vt d
+load net {ACC1:slc#132.itm(1)} -attr vt d
+load net {ACC1:slc#132.itm(2)} -attr vt d
+load netBundle {ACC1:slc#132.itm} 3 {ACC1:slc#132.itm(0)} {ACC1:slc#132.itm(1)} {ACC1:slc#132.itm(2)} -attr xrf 52652 -attr oid 708 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#132.itm}
+load net {ACC1:acc#464.itm(0)} -attr vt d
+load net {ACC1:acc#464.itm(1)} -attr vt d
+load net {ACC1:acc#464.itm(2)} -attr vt d
+load net {ACC1:acc#464.itm(3)} -attr vt d
+load netBundle {ACC1:acc#464.itm} 4 {ACC1:acc#464.itm(0)} {ACC1:acc#464.itm(1)} {ACC1:acc#464.itm(2)} {ACC1:acc#464.itm(3)} -attr xrf 52653 -attr oid 709 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#464.itm}
+load net {exs#86.itm(0)} -attr vt d
+load net {exs#86.itm(1)} -attr vt d
+load net {exs#86.itm(2)} -attr vt d
+load netBundle {exs#86.itm} 3 {exs#86.itm(0)} {exs#86.itm(1)} {exs#86.itm(2)} -attr xrf 52654 -attr oid 710 -attr vt d -attr @path {/sobel/sobel:core/exs#86.itm}
+load net {conc#976.itm(0)} -attr vt d
+load net {conc#976.itm(1)} -attr vt d
+load netBundle {conc#976.itm} 2 {conc#976.itm(0)} {conc#976.itm(1)} -attr xrf 52655 -attr oid 711 -attr vt d -attr @path {/sobel/sobel:core/conc#976.itm}
+load net {ACC1:exs#1580.itm(0)} -attr vt d
+load net {ACC1:exs#1580.itm(1)} -attr vt d
+load net {ACC1:exs#1580.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1580.itm} 3 {ACC1:exs#1580.itm(0)} {ACC1:exs#1580.itm(1)} {ACC1:exs#1580.itm(2)} -attr xrf 52656 -attr oid 712 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1580.itm}
+load net {ACC1:conc#1387.itm(0)} -attr vt d
+load net {ACC1:conc#1387.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1387.itm} 2 {ACC1:conc#1387.itm(0)} {ACC1:conc#1387.itm(1)} -attr xrf 52657 -attr oid 713 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1387.itm}
+load net {ACC1:acc#586.itm(0)} -attr vt d
+load net {ACC1:acc#586.itm(1)} -attr vt d
+load net {ACC1:acc#586.itm(2)} -attr vt d
+load net {ACC1:acc#586.itm(3)} -attr vt d
+load net {ACC1:acc#586.itm(4)} -attr vt d
+load netBundle {ACC1:acc#586.itm} 5 {ACC1:acc#586.itm(0)} {ACC1:acc#586.itm(1)} {ACC1:acc#586.itm(2)} {ACC1:acc#586.itm(3)} {ACC1:acc#586.itm(4)} -attr xrf 52658 -attr oid 714 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#542.itm(0)} -attr vt d
+load net {ACC1:acc#542.itm(1)} -attr vt d
+load net {ACC1:acc#542.itm(2)} -attr vt d
+load net {ACC1:acc#542.itm(3)} -attr vt d
+load netBundle {ACC1:acc#542.itm} 4 {ACC1:acc#542.itm(0)} {ACC1:acc#542.itm(1)} {ACC1:acc#542.itm(2)} {ACC1:acc#542.itm(3)} -attr xrf 52659 -attr oid 715 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:slc#131.itm(0)} -attr vt d
+load net {ACC1:slc#131.itm(1)} -attr vt d
+load net {ACC1:slc#131.itm(2)} -attr vt d
+load netBundle {ACC1:slc#131.itm} 3 {ACC1:slc#131.itm(0)} {ACC1:slc#131.itm(1)} {ACC1:slc#131.itm(2)} -attr xrf 52660 -attr oid 716 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#131.itm}
+load net {ACC1:acc#463.itm(0)} -attr vt d
+load net {ACC1:acc#463.itm(1)} -attr vt d
+load net {ACC1:acc#463.itm(2)} -attr vt d
+load net {ACC1:acc#463.itm(3)} -attr vt d
+load netBundle {ACC1:acc#463.itm} 4 {ACC1:acc#463.itm(0)} {ACC1:acc#463.itm(1)} {ACC1:acc#463.itm(2)} {ACC1:acc#463.itm(3)} -attr xrf 52661 -attr oid 717 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#463.itm}
+load net {exs#87.itm(0)} -attr vt d
+load net {exs#87.itm(1)} -attr vt d
+load net {exs#87.itm(2)} -attr vt d
+load netBundle {exs#87.itm} 3 {exs#87.itm(0)} {exs#87.itm(1)} {exs#87.itm(2)} -attr xrf 52662 -attr oid 718 -attr vt d -attr @path {/sobel/sobel:core/exs#87.itm}
+load net {conc#977.itm(0)} -attr vt d
+load net {conc#977.itm(1)} -attr vt d
+load netBundle {conc#977.itm} 2 {conc#977.itm(0)} {conc#977.itm(1)} -attr xrf 52663 -attr oid 719 -attr vt d -attr @path {/sobel/sobel:core/conc#977.itm}
+load net {ACC1:exs#1582.itm(0)} -attr vt d
+load net {ACC1:exs#1582.itm(1)} -attr vt d
+load net {ACC1:exs#1582.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1582.itm} 3 {ACC1:exs#1582.itm(0)} {ACC1:exs#1582.itm(1)} {ACC1:exs#1582.itm(2)} -attr xrf 52664 -attr oid 720 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1582.itm}
+load net {ACC1:conc#1385.itm(0)} -attr vt d
+load net {ACC1:conc#1385.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1385.itm} 2 {ACC1:conc#1385.itm(0)} {ACC1:conc#1385.itm(1)} -attr xrf 52665 -attr oid 721 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1385.itm}
+load net {ACC1:slc#130.itm(0)} -attr vt d
+load net {ACC1:slc#130.itm(1)} -attr vt d
+load net {ACC1:slc#130.itm(2)} -attr vt d
+load netBundle {ACC1:slc#130.itm} 3 {ACC1:slc#130.itm(0)} {ACC1:slc#130.itm(1)} {ACC1:slc#130.itm(2)} -attr xrf 52666 -attr oid 722 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#130.itm}
+load net {ACC1:acc#462.itm(0)} -attr vt d
+load net {ACC1:acc#462.itm(1)} -attr vt d
+load net {ACC1:acc#462.itm(2)} -attr vt d
+load net {ACC1:acc#462.itm(3)} -attr vt d
+load netBundle {ACC1:acc#462.itm} 4 {ACC1:acc#462.itm(0)} {ACC1:acc#462.itm(1)} {ACC1:acc#462.itm(2)} {ACC1:acc#462.itm(3)} -attr xrf 52667 -attr oid 723 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#462.itm}
+load net {exs#88.itm(0)} -attr vt d
+load net {exs#88.itm(1)} -attr vt d
+load net {exs#88.itm(2)} -attr vt d
+load netBundle {exs#88.itm} 3 {exs#88.itm(0)} {exs#88.itm(1)} {exs#88.itm(2)} -attr xrf 52668 -attr oid 724 -attr vt d -attr @path {/sobel/sobel:core/exs#88.itm}
+load net {conc#978.itm(0)} -attr vt d
+load net {conc#978.itm(1)} -attr vt d
+load netBundle {conc#978.itm} 2 {conc#978.itm(0)} {conc#978.itm(1)} -attr xrf 52669 -attr oid 725 -attr vt d -attr @path {/sobel/sobel:core/conc#978.itm}
+load net {ACC1:exs#1584.itm(0)} -attr vt d
+load net {ACC1:exs#1584.itm(1)} -attr vt d
+load net {ACC1:exs#1584.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1584.itm} 3 {ACC1:exs#1584.itm(0)} {ACC1:exs#1584.itm(1)} {ACC1:exs#1584.itm(2)} -attr xrf 52670 -attr oid 726 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1584.itm}
+load net {ACC1:conc#1383.itm(0)} -attr vt d
+load net {ACC1:conc#1383.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1383.itm} 2 {ACC1:conc#1383.itm(0)} {ACC1:conc#1383.itm(1)} -attr xrf 52671 -attr oid 727 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1383.itm}
+load net {ACC1:acc#541.itm(0)} -attr vt d
+load net {ACC1:acc#541.itm(1)} -attr vt d
+load net {ACC1:acc#541.itm(2)} -attr vt d
+load net {ACC1:acc#541.itm(3)} -attr vt d
+load netBundle {ACC1:acc#541.itm} 4 {ACC1:acc#541.itm(0)} {ACC1:acc#541.itm(1)} {ACC1:acc#541.itm(2)} {ACC1:acc#541.itm(3)} -attr xrf 52672 -attr oid 728 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:slc#128.itm(0)} -attr vt d
+load net {ACC1:slc#128.itm(1)} -attr vt d
+load net {ACC1:slc#128.itm(2)} -attr vt d
+load netBundle {ACC1:slc#128.itm} 3 {ACC1:slc#128.itm(0)} {ACC1:slc#128.itm(1)} {ACC1:slc#128.itm(2)} -attr xrf 52673 -attr oid 729 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#128.itm}
+load net {ACC1:acc#460.itm(0)} -attr vt d
+load net {ACC1:acc#460.itm(1)} -attr vt d
+load net {ACC1:acc#460.itm(2)} -attr vt d
+load net {ACC1:acc#460.itm(3)} -attr vt d
+load netBundle {ACC1:acc#460.itm} 4 {ACC1:acc#460.itm(0)} {ACC1:acc#460.itm(1)} {ACC1:acc#460.itm(2)} {ACC1:acc#460.itm(3)} -attr xrf 52674 -attr oid 730 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#460.itm}
+load net {exs#89.itm(0)} -attr vt d
+load net {exs#89.itm(1)} -attr vt d
+load net {exs#89.itm(2)} -attr vt d
+load netBundle {exs#89.itm} 3 {exs#89.itm(0)} {exs#89.itm(1)} {exs#89.itm(2)} -attr xrf 52675 -attr oid 731 -attr vt d -attr @path {/sobel/sobel:core/exs#89.itm}
+load net {conc#979.itm(0)} -attr vt d
+load net {conc#979.itm(1)} -attr vt d
+load netBundle {conc#979.itm} 2 {conc#979.itm(0)} {conc#979.itm(1)} -attr xrf 52676 -attr oid 732 -attr vt d -attr @path {/sobel/sobel:core/conc#979.itm}
+load net {ACC1:exs#1586.itm(0)} -attr vt d
+load net {ACC1:exs#1586.itm(1)} -attr vt d
+load net {ACC1:exs#1586.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1586.itm} 3 {ACC1:exs#1586.itm(0)} {ACC1:exs#1586.itm(1)} {ACC1:exs#1586.itm(2)} -attr xrf 52677 -attr oid 733 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1586.itm}
+load net {ACC1:conc#1379.itm(0)} -attr vt d
+load net {ACC1:conc#1379.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1379.itm} 2 {ACC1:conc#1379.itm(0)} {ACC1:conc#1379.itm(1)} -attr xrf 52678 -attr oid 734 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1379.itm}
+load net {ACC1:slc#127.itm(0)} -attr vt d
+load net {ACC1:slc#127.itm(1)} -attr vt d
+load net {ACC1:slc#127.itm(2)} -attr vt d
+load netBundle {ACC1:slc#127.itm} 3 {ACC1:slc#127.itm(0)} {ACC1:slc#127.itm(1)} {ACC1:slc#127.itm(2)} -attr xrf 52679 -attr oid 735 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#127.itm}
+load net {ACC1:acc#459.itm(0)} -attr vt d
+load net {ACC1:acc#459.itm(1)} -attr vt d
+load net {ACC1:acc#459.itm(2)} -attr vt d
+load net {ACC1:acc#459.itm(3)} -attr vt d
+load netBundle {ACC1:acc#459.itm} 4 {ACC1:acc#459.itm(0)} {ACC1:acc#459.itm(1)} {ACC1:acc#459.itm(2)} {ACC1:acc#459.itm(3)} -attr xrf 52680 -attr oid 736 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#459.itm}
+load net {exs#102.itm(0)} -attr vt d
+load net {exs#102.itm(1)} -attr vt d
+load net {exs#102.itm(2)} -attr vt d
+load netBundle {exs#102.itm} 3 {exs#102.itm(0)} {exs#102.itm(1)} {exs#102.itm(2)} -attr xrf 52681 -attr oid 737 -attr vt d -attr @path {/sobel/sobel:core/exs#102.itm}
+load net {conc#980.itm(0)} -attr vt d
+load net {conc#980.itm(1)} -attr vt d
+load netBundle {conc#980.itm} 2 {conc#980.itm(0)} {conc#980.itm(1)} -attr xrf 52682 -attr oid 738 -attr vt d -attr @path {/sobel/sobel:core/conc#980.itm}
+load net {ACC1:exs#1588.itm(0)} -attr vt d
+load net {ACC1:exs#1588.itm(1)} -attr vt d
+load net {ACC1:exs#1588.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1588.itm} 3 {ACC1:exs#1588.itm(0)} {ACC1:exs#1588.itm(1)} {ACC1:exs#1588.itm(2)} -attr xrf 52683 -attr oid 739 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1588.itm}
+load net {ACC1:conc#1377.itm(0)} -attr vt d
+load net {ACC1:conc#1377.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1377.itm} 2 {ACC1:conc#1377.itm(0)} {ACC1:conc#1377.itm(1)} -attr xrf 52684 -attr oid 740 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1377.itm}
+load net {ACC1:acc#647.itm(0)} -attr vt d
+load net {ACC1:acc#647.itm(1)} -attr vt d
+load net {ACC1:acc#647.itm(2)} -attr vt d
+load net {ACC1:acc#647.itm(3)} -attr vt d
+load net {ACC1:acc#647.itm(4)} -attr vt d
+load net {ACC1:acc#647.itm(5)} -attr vt d
+load net {ACC1:acc#647.itm(6)} -attr vt d
+load net {ACC1:acc#647.itm(7)} -attr vt d
+load net {ACC1:acc#647.itm(8)} -attr vt d
+load net {ACC1:acc#647.itm(9)} -attr vt d
+load netBundle {ACC1:acc#647.itm} 10 {ACC1:acc#647.itm(0)} {ACC1:acc#647.itm(1)} {ACC1:acc#647.itm(2)} {ACC1:acc#647.itm(3)} {ACC1:acc#647.itm(4)} {ACC1:acc#647.itm(5)} {ACC1:acc#647.itm(6)} {ACC1:acc#647.itm(7)} {ACC1:acc#647.itm(8)} {ACC1:acc#647.itm(9)} -attr xrf 52685 -attr oid 741 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#640.itm(0)} -attr vt d
+load net {ACC1:acc#640.itm(1)} -attr vt d
+load net {ACC1:acc#640.itm(2)} -attr vt d
+load net {ACC1:acc#640.itm(3)} -attr vt d
+load net {ACC1:acc#640.itm(4)} -attr vt d
+load net {ACC1:acc#640.itm(5)} -attr vt d
+load net {ACC1:acc#640.itm(6)} -attr vt d
+load net {ACC1:acc#640.itm(7)} -attr vt d
+load netBundle {ACC1:acc#640.itm} 8 {ACC1:acc#640.itm(0)} {ACC1:acc#640.itm(1)} {ACC1:acc#640.itm(2)} {ACC1:acc#640.itm(3)} {ACC1:acc#640.itm(4)} {ACC1:acc#640.itm(5)} {ACC1:acc#640.itm(6)} {ACC1:acc#640.itm(7)} -attr xrf 52686 -attr oid 742 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#627.itm(0)} -attr vt d
+load net {ACC1:acc#627.itm(1)} -attr vt d
+load net {ACC1:acc#627.itm(2)} -attr vt d
+load net {ACC1:acc#627.itm(3)} -attr vt d
+load net {ACC1:acc#627.itm(4)} -attr vt d
+load net {ACC1:acc#627.itm(5)} -attr vt d
+load net {ACC1:acc#627.itm(6)} -attr vt d
+load net {ACC1:acc#627.itm(7)} -attr vt d
+load netBundle {ACC1:acc#627.itm} 8 {ACC1:acc#627.itm(0)} {ACC1:acc#627.itm(1)} {ACC1:acc#627.itm(2)} {ACC1:acc#627.itm(3)} {ACC1:acc#627.itm(4)} {ACC1:acc#627.itm(5)} {ACC1:acc#627.itm(6)} {ACC1:acc#627.itm(7)} -attr xrf 52687 -attr oid 743 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {conc#982.itm(0)} -attr vt d
+load net {conc#982.itm(1)} -attr vt d
+load net {conc#982.itm(2)} -attr vt d
+load net {conc#982.itm(3)} -attr vt d
+load net {conc#982.itm(4)} -attr vt d
+load net {conc#982.itm(5)} -attr vt d
+load net {conc#982.itm(6)} -attr vt d
+load netBundle {conc#982.itm} 7 {conc#982.itm(0)} {conc#982.itm(1)} {conc#982.itm(2)} {conc#982.itm(3)} {conc#982.itm(4)} {conc#982.itm(5)} {conc#982.itm(6)} -attr xrf 52688 -attr oid 744 -attr vt d -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {ACC1-3:exs#1072.itm(0)} -attr vt d
+load net {ACC1-3:exs#1072.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1072.itm} 2 {ACC1-3:exs#1072.itm(0)} {ACC1-3:exs#1072.itm(1)} -attr xrf 52689 -attr oid 745 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1072.itm}
+load net {ACC1:acc#614.itm(0)} -attr vt d
+load net {ACC1:acc#614.itm(1)} -attr vt d
+load net {ACC1:acc#614.itm(2)} -attr vt d
+load net {ACC1:acc#614.itm(3)} -attr vt d
+load net {ACC1:acc#614.itm(4)} -attr vt d
+load net {ACC1:acc#614.itm(5)} -attr vt d
+load netBundle {ACC1:acc#614.itm} 6 {ACC1:acc#614.itm(0)} {ACC1:acc#614.itm(1)} {ACC1:acc#614.itm(2)} {ACC1:acc#614.itm(3)} {ACC1:acc#614.itm(4)} {ACC1:acc#614.itm(5)} -attr xrf 52690 -attr oid 746 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#599.itm(0)} -attr vt d
+load net {ACC1:acc#599.itm(1)} -attr vt d
+load net {ACC1:acc#599.itm(2)} -attr vt d
+load net {ACC1:acc#599.itm(3)} -attr vt d
+load net {ACC1:acc#599.itm(4)} -attr vt d
+load netBundle {ACC1:acc#599.itm} 5 {ACC1:acc#599.itm(0)} {ACC1:acc#599.itm(1)} {ACC1:acc#599.itm(2)} {ACC1:acc#599.itm(3)} {ACC1:acc#599.itm(4)} -attr xrf 52691 -attr oid 747 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#568.itm(0)} -attr vt d
+load net {ACC1:acc#568.itm(1)} -attr vt d
+load net {ACC1:acc#568.itm(2)} -attr vt d
+load net {ACC1:acc#568.itm(3)} -attr vt d
+load netBundle {ACC1:acc#568.itm} 4 {ACC1:acc#568.itm(0)} {ACC1:acc#568.itm(1)} {ACC1:acc#568.itm(2)} {ACC1:acc#568.itm(3)} -attr xrf 52692 -attr oid 748 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#517.itm(0)} -attr vt d
+load net {ACC1:acc#517.itm(1)} -attr vt d
+load net {ACC1:acc#517.itm(2)} -attr vt d
+load netBundle {ACC1:acc#517.itm} 3 {ACC1:acc#517.itm(0)} {ACC1:acc#517.itm(1)} {ACC1:acc#517.itm(2)} -attr xrf 52693 -attr oid 749 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load net {ACC1-2:exs#20.itm(0)} -attr vt d
+load net {ACC1-2:exs#20.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#20.itm} 2 {ACC1-2:exs#20.itm(0)} {ACC1-2:exs#20.itm(1)} -attr xrf 52694 -attr oid 750 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#20.itm}
+load net {ACC1-2:exs#1049.itm(0)} -attr vt d
+load net {ACC1-2:exs#1049.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1049.itm} 2 {ACC1-2:exs#1049.itm(0)} {ACC1-2:exs#1049.itm(1)} -attr xrf 52695 -attr oid 751 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1049.itm}
+load net {ACC1:acc#567.itm(0)} -attr vt d
+load net {ACC1:acc#567.itm(1)} -attr vt d
+load net {ACC1:acc#567.itm(2)} -attr vt d
+load net {ACC1:acc#567.itm(3)} -attr vt d
+load netBundle {ACC1:acc#567.itm} 4 {ACC1:acc#567.itm(0)} {ACC1:acc#567.itm(1)} {ACC1:acc#567.itm(2)} {ACC1:acc#567.itm(3)} -attr xrf 52696 -attr oid 752 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#598.itm(0)} -attr vt d
+load net {ACC1:acc#598.itm(1)} -attr vt d
+load net {ACC1:acc#598.itm(2)} -attr vt d
+load net {ACC1:acc#598.itm(3)} -attr vt d
+load net {ACC1:acc#598.itm(4)} -attr vt d
+load netBundle {ACC1:acc#598.itm} 5 {ACC1:acc#598.itm(0)} {ACC1:acc#598.itm(1)} {ACC1:acc#598.itm(2)} {ACC1:acc#598.itm(3)} {ACC1:acc#598.itm(4)} -attr xrf 52697 -attr oid 753 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#566.itm(0)} -attr vt d
+load net {ACC1:acc#566.itm(1)} -attr vt d
+load net {ACC1:acc#566.itm(2)} -attr vt d
+load net {ACC1:acc#566.itm(3)} -attr vt d
+load netBundle {ACC1:acc#566.itm} 4 {ACC1:acc#566.itm(0)} {ACC1:acc#566.itm(1)} {ACC1:acc#566.itm(2)} {ACC1:acc#566.itm(3)} -attr xrf 52698 -attr oid 754 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#513.itm(0)} -attr vt d
+load net {ACC1:acc#513.itm(1)} -attr vt d
+load net {ACC1:acc#513.itm(2)} -attr vt d
+load netBundle {ACC1:acc#513.itm} 3 {ACC1:acc#513.itm(0)} {ACC1:acc#513.itm(1)} {ACC1:acc#513.itm(2)} -attr xrf 52699 -attr oid 755 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load net {ACC1-2:exs#1050.itm(0)} -attr vt d
+load net {ACC1-2:exs#1050.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1050.itm} 2 {ACC1-2:exs#1050.itm(0)} {ACC1-2:exs#1050.itm(1)} -attr xrf 52700 -attr oid 756 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1050.itm}
+load net {ACC1-2:exs#1031.itm(0)} -attr vt d
+load net {ACC1-2:exs#1031.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1031.itm} 2 {ACC1-2:exs#1031.itm(0)} {ACC1-2:exs#1031.itm(1)} -attr xrf 52701 -attr oid 757 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1031.itm}
+load net {ACC1:acc#565.itm(0)} -attr vt d
+load net {ACC1:acc#565.itm(1)} -attr vt d
+load net {ACC1:acc#565.itm(2)} -attr vt d
+load net {ACC1:acc#565.itm(3)} -attr vt d
+load netBundle {ACC1:acc#565.itm} 4 {ACC1:acc#565.itm(0)} {ACC1:acc#565.itm(1)} {ACC1:acc#565.itm(2)} {ACC1:acc#565.itm(3)} -attr xrf 52702 -attr oid 758 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#510.itm(0)} -attr vt d
+load net {ACC1:acc#510.itm(1)} -attr vt d
+load net {ACC1:acc#510.itm(2)} -attr vt d
+load netBundle {ACC1:acc#510.itm} 3 {ACC1:acc#510.itm(0)} {ACC1:acc#510.itm(1)} {ACC1:acc#510.itm(2)} -attr xrf 52703 -attr oid 759 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load net {ACC1-3:exs#1060.itm(0)} -attr vt d
+load net {ACC1-3:exs#1060.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1060.itm} 2 {ACC1-3:exs#1060.itm(0)} {ACC1-3:exs#1060.itm(1)} -attr xrf 52704 -attr oid 760 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1060.itm}
+load net {ACC1-3:exs#1049.itm(0)} -attr vt d
+load net {ACC1-3:exs#1049.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1049.itm} 2 {ACC1-3:exs#1049.itm(0)} {ACC1-3:exs#1049.itm(1)} -attr xrf 52705 -attr oid 761 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1049.itm}
+load net {ACC1:acc#621.itm(0)} -attr vt d
+load net {ACC1:acc#621.itm(1)} -attr vt d
+load net {ACC1:acc#621.itm(2)} -attr vt d
+load net {ACC1:acc#621.itm(3)} -attr vt d
+load net {ACC1:acc#621.itm(4)} -attr vt d
+load net {ACC1:acc#621.itm(5)} -attr vt d
+load net {ACC1:acc#621.itm(6)} -attr vt d
+load netBundle {ACC1:acc#621.itm} 7 {ACC1:acc#621.itm(0)} {ACC1:acc#621.itm(1)} {ACC1:acc#621.itm(2)} {ACC1:acc#621.itm(3)} {ACC1:acc#621.itm(4)} {ACC1:acc#621.itm(5)} {ACC1:acc#621.itm(6)} -attr xrf 52706 -attr oid 762 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#603.itm(0)} -attr vt d
+load net {ACC1:acc#603.itm(1)} -attr vt d
+load net {ACC1:acc#603.itm(2)} -attr vt d
+load net {ACC1:acc#603.itm(3)} -attr vt d
+load net {ACC1:acc#603.itm(4)} -attr vt d
+load net {ACC1:acc#603.itm(5)} -attr vt d
+load netBundle {ACC1:acc#603.itm} 6 {ACC1:acc#603.itm(0)} {ACC1:acc#603.itm(1)} {ACC1:acc#603.itm(2)} {ACC1:acc#603.itm(3)} {ACC1:acc#603.itm(4)} {ACC1:acc#603.itm(5)} -attr xrf 52707 -attr oid 763 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#577.itm(0)} -attr vt d
+load net {ACC1:acc#577.itm(1)} -attr vt d
+load net {ACC1:acc#577.itm(2)} -attr vt d
+load net {ACC1:acc#577.itm(3)} -attr vt d
+load net {ACC1:acc#577.itm(4)} -attr vt d
+load netBundle {ACC1:acc#577.itm} 5 {ACC1:acc#577.itm(0)} {ACC1:acc#577.itm(1)} {ACC1:acc#577.itm(2)} {ACC1:acc#577.itm(3)} {ACC1:acc#577.itm(4)} -attr xrf 52708 -attr oid 764 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#523.itm(0)} -attr vt d
+load net {ACC1:acc#523.itm(1)} -attr vt d
+load net {ACC1:acc#523.itm(2)} -attr vt d
+load net {ACC1:acc#523.itm(3)} -attr vt d
+load netBundle {ACC1:acc#523.itm} 4 {ACC1:acc#523.itm(0)} {ACC1:acc#523.itm(1)} {ACC1:acc#523.itm(2)} {ACC1:acc#523.itm(3)} -attr xrf 52709 -attr oid 765 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:conc#1098.itm(0)} -attr vt d
+load net {ACC1:conc#1098.itm(1)} -attr vt d
+load net {ACC1:conc#1098.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1098.itm} 3 {ACC1:conc#1098.itm(0)} {ACC1:conc#1098.itm(1)} {ACC1:conc#1098.itm(2)} -attr xrf 52710 -attr oid 766 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1098.itm}
+load net {conc#983.itm(0)} -attr vt d
+load net {conc#983.itm(1)} -attr vt d
+load net {conc#983.itm(2)} -attr vt d
+load netBundle {conc#983.itm} 3 {conc#983.itm(0)} {conc#983.itm(1)} {conc#983.itm(2)} -attr xrf 52711 -attr oid 767 -attr vt d -attr @path {/sobel/sobel:core/conc#983.itm}
+load net {ACC1:conc#1457.itm(0)} -attr vt d
+load net {ACC1:conc#1457.itm(1)} -attr vt d
+load net {ACC1:conc#1457.itm(2)} -attr vt d
+load net {ACC1:conc#1457.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1457.itm} 4 {ACC1:conc#1457.itm(0)} {ACC1:conc#1457.itm(1)} {ACC1:conc#1457.itm(2)} {ACC1:conc#1457.itm(3)} -attr xrf 52712 -attr oid 768 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1457.itm}
+load net {slc.itm(0)} -attr vt d
+load net {slc.itm(1)} -attr vt d
+load netBundle {slc.itm} 2 {slc.itm(0)} {slc.itm(1)} -attr xrf 52713 -attr oid 769 -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(0)} -attr vt d
+load net {acc.itm(1)} -attr vt d
+load net {acc.itm(2)} -attr vt d
+load netBundle {acc.itm} 3 {acc.itm(0)} {acc.itm(1)} {acc.itm(2)} -attr xrf 52714 -attr oid 770 -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {conc#984.itm(0)} -attr vt d
+load net {conc#984.itm(1)} -attr vt d
+load netBundle {conc#984.itm} 2 {conc#984.itm(0)} {conc#984.itm(1)} -attr xrf 52715 -attr oid 771 -attr vt d -attr @path {/sobel/sobel:core/conc#984.itm}
+load net {conc#985.itm(0)} -attr vt d
+load net {conc#985.itm(1)} -attr vt d
+load netBundle {conc#985.itm} 2 {conc#985.itm(0)} {conc#985.itm(1)} -attr xrf 52716 -attr oid 772 -attr vt d -attr @path {/sobel/sobel:core/conc#985.itm}
+load net {ACC1:acc#732.itm(0)} -attr vt d
+load net {ACC1:acc#732.itm(1)} -attr vt d
+load netBundle {ACC1:acc#732.itm} 2 {ACC1:acc#732.itm(0)} {ACC1:acc#732.itm(1)} -attr xrf 52717 -attr oid 773 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#732.itm}
+load net {conc#986.itm(0)} -attr vt d
+load net {conc#986.itm(1)} -attr vt d
+load netBundle {conc#986.itm} 2 {conc#986.itm(0)} {conc#986.itm(1)} -attr xrf 52718 -attr oid 774 -attr vt d -attr @path {/sobel/sobel:core/conc#986.itm}
+load net {conc#987.itm(0)} -attr vt d
+load net {conc#987.itm(1)} -attr vt d
+load netBundle {conc#987.itm} 2 {conc#987.itm(0)} {conc#987.itm(1)} -attr xrf 52719 -attr oid 775 -attr vt d -attr @path {/sobel/sobel:core/conc#987.itm}
+load net {ACC1:acc#576.itm(0)} -attr vt d
+load net {ACC1:acc#576.itm(1)} -attr vt d
+load net {ACC1:acc#576.itm(2)} -attr vt d
+load net {ACC1:acc#576.itm(3)} -attr vt d
+load net {ACC1:acc#576.itm(4)} -attr vt d
+load netBundle {ACC1:acc#576.itm} 5 {ACC1:acc#576.itm(0)} {ACC1:acc#576.itm(1)} {ACC1:acc#576.itm(2)} {ACC1:acc#576.itm(3)} {ACC1:acc#576.itm(4)} -attr xrf 52720 -attr oid 776 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:conc#1458.itm(0)} -attr vt d
+load net {ACC1:conc#1458.itm(1)} -attr vt d
+load net {ACC1:conc#1458.itm(2)} -attr vt d
+load net {ACC1:conc#1458.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1458.itm} 4 {ACC1:conc#1458.itm(0)} {ACC1:conc#1458.itm(1)} {ACC1:conc#1458.itm(2)} {ACC1:conc#1458.itm(3)} -attr xrf 52721 -attr oid 777 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1458.itm}
+load net {slc#1.itm(0)} -attr vt d
+load net {slc#1.itm(1)} -attr vt d
+load netBundle {slc#1.itm} 2 {slc#1.itm(0)} {slc#1.itm(1)} -attr xrf 52722 -attr oid 778 -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#31.itm(0)} -attr vt d
+load net {acc#31.itm(1)} -attr vt d
+load net {acc#31.itm(2)} -attr vt d
+load netBundle {acc#31.itm} 3 {acc#31.itm(0)} {acc#31.itm(1)} {acc#31.itm(2)} -attr xrf 52723 -attr oid 779 -attr vt d -attr @path {/sobel/sobel:core/acc#31.itm}
+load net {conc#988.itm(0)} -attr vt d
+load net {conc#988.itm(1)} -attr vt d
+load netBundle {conc#988.itm} 2 {conc#988.itm(0)} {conc#988.itm(1)} -attr xrf 52724 -attr oid 780 -attr vt d -attr @path {/sobel/sobel:core/conc#988.itm}
+load net {conc#989.itm(0)} -attr vt d
+load net {conc#989.itm(1)} -attr vt d
+load netBundle {conc#989.itm} 2 {conc#989.itm(0)} {conc#989.itm(1)} -attr xrf 52725 -attr oid 781 -attr vt d -attr @path {/sobel/sobel:core/conc#989.itm}
+load net {ACC1:acc#734.itm(0)} -attr vt d
+load net {ACC1:acc#734.itm(1)} -attr vt d
+load netBundle {ACC1:acc#734.itm} 2 {ACC1:acc#734.itm(0)} {ACC1:acc#734.itm(1)} -attr xrf 52726 -attr oid 782 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#734.itm}
+load net {conc#990.itm(0)} -attr vt d
+load net {conc#990.itm(1)} -attr vt d
+load netBundle {conc#990.itm} 2 {conc#990.itm(0)} {conc#990.itm(1)} -attr xrf 52727 -attr oid 783 -attr vt d -attr @path {/sobel/sobel:core/conc#990.itm}
+load net {conc#991.itm(0)} -attr vt d
+load net {conc#991.itm(1)} -attr vt d
+load netBundle {conc#991.itm} 2 {conc#991.itm(0)} {conc#991.itm(1)} -attr xrf 52728 -attr oid 784 -attr vt d -attr @path {/sobel/sobel:core/conc#991.itm}
+load net {ACC1:acc#520.itm(0)} -attr vt d
+load net {ACC1:acc#520.itm(1)} -attr vt d
+load net {ACC1:acc#520.itm(2)} -attr vt d
+load net {ACC1:acc#520.itm(3)} -attr vt d
+load netBundle {ACC1:acc#520.itm} 4 {ACC1:acc#520.itm(0)} {ACC1:acc#520.itm(1)} {ACC1:acc#520.itm(2)} {ACC1:acc#520.itm(3)} -attr xrf 52729 -attr oid 785 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {conc#992.itm(0)} -attr vt d
+load net {conc#992.itm(1)} -attr vt d
+load net {conc#992.itm(2)} -attr vt d
+load netBundle {conc#992.itm} 3 {conc#992.itm(0)} {conc#992.itm(1)} {conc#992.itm(2)} -attr xrf 52730 -attr oid 786 -attr vt d -attr @path {/sobel/sobel:core/conc#992.itm}
+load net {slc(ACC1:acc#221.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#221.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#221.psp.sva)#2.itm} 2 {slc(ACC1:acc#221.psp.sva)#2.itm(0)} {slc(ACC1:acc#221.psp.sva)#2.itm(1)} -attr xrf 52731 -attr oid 787 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp.sva)#2.itm}
+load net {ACC1:acc#602.itm(0)} -attr vt d
+load net {ACC1:acc#602.itm(1)} -attr vt d
+load net {ACC1:acc#602.itm(2)} -attr vt d
+load net {ACC1:acc#602.itm(3)} -attr vt d
+load net {ACC1:acc#602.itm(4)} -attr vt d
+load net {ACC1:acc#602.itm(5)} -attr vt d
+load netBundle {ACC1:acc#602.itm} 6 {ACC1:acc#602.itm(0)} {ACC1:acc#602.itm(1)} {ACC1:acc#602.itm(2)} {ACC1:acc#602.itm(3)} {ACC1:acc#602.itm(4)} {ACC1:acc#602.itm(5)} -attr xrf 52732 -attr oid 788 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#575.itm(0)} -attr vt d
+load net {ACC1:acc#575.itm(1)} -attr vt d
+load net {ACC1:acc#575.itm(2)} -attr vt d
+load net {ACC1:acc#575.itm(3)} -attr vt d
+load net {ACC1:acc#575.itm(4)} -attr vt d
+load netBundle {ACC1:acc#575.itm} 5 {ACC1:acc#575.itm(0)} {ACC1:acc#575.itm(1)} {ACC1:acc#575.itm(2)} {ACC1:acc#575.itm(3)} {ACC1:acc#575.itm(4)} -attr xrf 52733 -attr oid 789 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#518.itm(0)} -attr vt d
+load net {ACC1:acc#518.itm(1)} -attr vt d
+load net {ACC1:acc#518.itm(2)} -attr vt d
+load net {ACC1:acc#518.itm(3)} -attr vt d
+load netBundle {ACC1:acc#518.itm} 4 {ACC1:acc#518.itm(0)} {ACC1:acc#518.itm(1)} {ACC1:acc#518.itm(2)} {ACC1:acc#518.itm(3)} -attr xrf 52734 -attr oid 790 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {slc(ACC1:acc#221.psp#2.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#221.psp#2.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#221.psp#2.sva)#2.itm} 2 {slc(ACC1:acc#221.psp#2.sva)#2.itm(0)} {slc(ACC1:acc#221.psp#2.sva)#2.itm(1)} -attr xrf 52735 -attr oid 791 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp#2.sva)#2.itm}
+load net {ACC1-2:exs#19.itm(0)} -attr vt d
+load net {ACC1-2:exs#19.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#19.itm} 2 {ACC1-2:exs#19.itm(0)} {ACC1-2:exs#19.itm(1)} -attr xrf 52736 -attr oid 792 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#19.itm}
+load net {ACC1:acc#490.itm(0)} -attr vt d
+load net {ACC1:acc#490.itm(1)} -attr vt d
+load net {ACC1:acc#490.itm(2)} -attr vt d
+load net {ACC1:acc#490.itm(3)} -attr vt d
+load netBundle {ACC1:acc#490.itm} 4 {ACC1:acc#490.itm(0)} {ACC1:acc#490.itm(1)} {ACC1:acc#490.itm(2)} {ACC1:acc#490.itm(3)} -attr xrf 52737 -attr oid 793 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {slc(ACC1:acc#219.psp#2.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#219.psp#2.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#219.psp#2.sva)#2.itm} 2 {slc(ACC1:acc#219.psp#2.sva)#2.itm(0)} {slc(ACC1:acc#219.psp#2.sva)#2.itm(1)} -attr xrf 52738 -attr oid 794 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#2.sva)#2.itm}
+load net {ACC1-2:exs#1058.itm(0)} -attr vt d
+load net {ACC1-2:exs#1058.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1058.itm} 2 {ACC1-2:exs#1058.itm(0)} {ACC1-2:exs#1058.itm(1)} -attr xrf 52739 -attr oid 795 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1058.itm}
+load net {ACC1:acc#574.itm(0)} -attr vt d
+load net {ACC1:acc#574.itm(1)} -attr vt d
+load net {ACC1:acc#574.itm(2)} -attr vt d
+load net {ACC1:acc#574.itm(3)} -attr vt d
+load net {ACC1:acc#574.itm(4)} -attr vt d
+load netBundle {ACC1:acc#574.itm} 5 {ACC1:acc#574.itm(0)} {ACC1:acc#574.itm(1)} {ACC1:acc#574.itm(2)} {ACC1:acc#574.itm(3)} {ACC1:acc#574.itm(4)} -attr xrf 52740 -attr oid 796 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:slc#139.itm(0)} -attr vt d
+load net {ACC1:slc#139.itm(1)} -attr vt d
+load net {ACC1:slc#139.itm(2)} -attr vt d
+load net {ACC1:slc#139.itm(3)} -attr vt d
+load netBundle {ACC1:slc#139.itm} 4 {ACC1:slc#139.itm(0)} {ACC1:slc#139.itm(1)} {ACC1:slc#139.itm(2)} {ACC1:slc#139.itm(3)} -attr xrf 52741 -attr oid 797 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#139.itm}
+load net {ACC1:acc#471.itm(0)} -attr vt d
+load net {ACC1:acc#471.itm(1)} -attr vt d
+load net {ACC1:acc#471.itm(2)} -attr vt d
+load net {ACC1:acc#471.itm(3)} -attr vt d
+load net {ACC1:acc#471.itm(4)} -attr vt d
+load netBundle {ACC1:acc#471.itm} 5 {ACC1:acc#471.itm(0)} {ACC1:acc#471.itm(1)} {ACC1:acc#471.itm(2)} {ACC1:acc#471.itm(3)} {ACC1:acc#471.itm(4)} -attr xrf 52742 -attr oid 798 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471.itm}
+load net {exs#90.itm(0)} -attr vt d
+load net {exs#90.itm(1)} -attr vt d
+load net {exs#90.itm(2)} -attr vt d
+load netBundle {exs#90.itm} 3 {exs#90.itm(0)} {exs#90.itm(1)} {exs#90.itm(2)} -attr xrf 52743 -attr oid 799 -attr vt d -attr @path {/sobel/sobel:core/exs#90.itm}
+load net {conc#993.itm(0)} -attr vt d
+load net {conc#993.itm(1)} -attr vt d
+load netBundle {conc#993.itm} 2 {conc#993.itm(0)} {conc#993.itm(1)} -attr xrf 52744 -attr oid 800 -attr vt d -attr @path {/sobel/sobel:core/conc#993.itm}
+load net {ACC1:conc#1401.itm(0)} -attr vt d
+load net {ACC1:conc#1401.itm(1)} -attr vt d
+load net {ACC1:conc#1401.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1401.itm} 3 {ACC1:conc#1401.itm(0)} {ACC1:conc#1401.itm(1)} {ACC1:conc#1401.itm(2)} -attr xrf 52745 -attr oid 801 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1401.itm}
+load net {slc(ACC1:acc#222.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#222.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#222.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#222.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#222.psp#1.sva)#2.itm(1)} -attr xrf 52746 -attr oid 802 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp#1.sva)#2.itm}
+load net {ACC1:slc#129.itm(0)} -attr vt d
+load net {ACC1:slc#129.itm(1)} -attr vt d
+load net {ACC1:slc#129.itm(2)} -attr vt d
+load net {ACC1:slc#129.itm(3)} -attr vt d
+load netBundle {ACC1:slc#129.itm} 4 {ACC1:slc#129.itm(0)} {ACC1:slc#129.itm(1)} {ACC1:slc#129.itm(2)} {ACC1:slc#129.itm(3)} -attr xrf 52747 -attr oid 803 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#129.itm}
+load net {ACC1:acc#461.itm(0)} -attr vt d
+load net {ACC1:acc#461.itm(1)} -attr vt d
+load net {ACC1:acc#461.itm(2)} -attr vt d
+load net {ACC1:acc#461.itm(3)} -attr vt d
+load net {ACC1:acc#461.itm(4)} -attr vt d
+load netBundle {ACC1:acc#461.itm} 5 {ACC1:acc#461.itm(0)} {ACC1:acc#461.itm(1)} {ACC1:acc#461.itm(2)} {ACC1:acc#461.itm(3)} {ACC1:acc#461.itm(4)} -attr xrf 52748 -attr oid 804 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461.itm}
+load net {conc#994.itm(0)} -attr vt d
+load net {conc#994.itm(1)} -attr vt d
+load net {conc#994.itm(2)} -attr vt d
+load netBundle {conc#994.itm} 3 {conc#994.itm(0)} {conc#994.itm(1)} {conc#994.itm(2)} -attr xrf 52749 -attr oid 805 -attr vt d -attr @path {/sobel/sobel:core/conc#994.itm}
+load net {slc(ACC1:acc#219.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#219.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#219.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#219.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#219.psp#1.sva)#2.itm(1)} -attr xrf 52750 -attr oid 806 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#1.sva)#2.itm}
+load net {ACC1:exs#1590.itm(0)} -attr vt d
+load net {ACC1:exs#1590.itm(1)} -attr vt d
+load net {ACC1:exs#1590.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1590.itm} 3 {ACC1:exs#1590.itm(0)} {ACC1:exs#1590.itm(1)} {ACC1:exs#1590.itm(2)} -attr xrf 52751 -attr oid 807 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1590.itm}
+load net {ACC1:conc#1381.itm(0)} -attr vt d
+load net {ACC1:conc#1381.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1381.itm} 2 {ACC1:conc#1381.itm(0)} {ACC1:conc#1381.itm(1)} -attr xrf 52752 -attr oid 808 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1381.itm}
+load net {ACC1:acc#639.itm(0)} -attr vt d
+load net {ACC1:acc#639.itm(1)} -attr vt d
+load net {ACC1:acc#639.itm(2)} -attr vt d
+load net {ACC1:acc#639.itm(3)} -attr vt d
+load net {ACC1:acc#639.itm(4)} -attr vt d
+load net {ACC1:acc#639.itm(5)} -attr vt d
+load net {ACC1:acc#639.itm(6)} -attr vt d
+load net {ACC1:acc#639.itm(7)} -attr vt d
+load net {ACC1:acc#639.itm(8)} -attr vt d
+load netBundle {ACC1:acc#639.itm} 9 {ACC1:acc#639.itm(0)} {ACC1:acc#639.itm(1)} {ACC1:acc#639.itm(2)} {ACC1:acc#639.itm(3)} {ACC1:acc#639.itm(4)} {ACC1:acc#639.itm(5)} {ACC1:acc#639.itm(6)} {ACC1:acc#639.itm(7)} {ACC1:acc#639.itm(8)} -attr xrf 52753 -attr oid 809 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:mul.itm(0)} -attr vt d
+load net {ACC1:mul.itm(1)} -attr vt d
+load net {ACC1:mul.itm(2)} -attr vt d
+load net {ACC1:mul.itm(3)} -attr vt d
+load net {ACC1:mul.itm(4)} -attr vt d
+load net {ACC1:mul.itm(5)} -attr vt d
+load net {ACC1:mul.itm(6)} -attr vt d
+load net {ACC1:mul.itm(7)} -attr vt d
+load netBundle {ACC1:mul.itm} 8 {ACC1:mul.itm(0)} {ACC1:mul.itm(1)} {ACC1:mul.itm(2)} {ACC1:mul.itm(3)} {ACC1:mul.itm(4)} {ACC1:mul.itm(5)} {ACC1:mul.itm(6)} {ACC1:mul.itm(7)} -attr xrf 52754 -attr oid 810 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:acc#295.itm(0)} -attr vt d
+load net {ACC1:acc#295.itm(1)} -attr vt d
+load net {ACC1:acc#295.itm(2)} -attr vt d
+load net {ACC1:acc#295.itm(3)} -attr vt d
+load netBundle {ACC1:acc#295.itm} 4 {ACC1:acc#295.itm(0)} {ACC1:acc#295.itm(1)} {ACC1:acc#295.itm(2)} {ACC1:acc#295.itm(3)} -attr xrf 52755 -attr oid 811 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#296.itm(0)} -attr vt d
+load net {ACC1:acc#296.itm(1)} -attr vt d
+load net {ACC1:acc#296.itm(2)} -attr vt d
+load netBundle {ACC1:acc#296.itm} 3 {ACC1:acc#296.itm(0)} {ACC1:acc#296.itm(1)} {ACC1:acc#296.itm(2)} -attr xrf 52756 -attr oid 812 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#297.itm(0)} -attr vt d
+load net {ACC1:acc#297.itm(1)} -attr vt d
+load net {ACC1:acc#297.itm(2)} -attr vt d
+load netBundle {ACC1:acc#297.itm} 3 {ACC1:acc#297.itm(0)} {ACC1:acc#297.itm(1)} {ACC1:acc#297.itm(2)} -attr xrf 52757 -attr oid 813 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#298.itm(0)} -attr vt d
+load net {ACC1:acc#298.itm(1)} -attr vt d
+load net {ACC1:acc#298.itm(2)} -attr vt d
+load netBundle {ACC1:acc#298.itm} 3 {ACC1:acc#298.itm(0)} {ACC1:acc#298.itm(1)} {ACC1:acc#298.itm(2)} -attr xrf 52758 -attr oid 814 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#299.itm(0)} -attr vt d
+load net {ACC1:acc#299.itm(1)} -attr vt d
+load net {ACC1:acc#299.itm(2)} -attr vt d
+load netBundle {ACC1:acc#299.itm} 3 {ACC1:acc#299.itm(0)} {ACC1:acc#299.itm(1)} {ACC1:acc#299.itm(2)} -attr xrf 52759 -attr oid 815 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#300.itm(0)} -attr vt d
+load net {ACC1:acc#300.itm(1)} -attr vt d
+load netBundle {ACC1:acc#300.itm} 2 {ACC1:acc#300.itm(0)} {ACC1:acc#300.itm(1)} -attr xrf 52760 -attr oid 816 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#301.itm(0)} -attr vt d
+load net {ACC1:acc#301.itm(1)} -attr vt d
+load netBundle {ACC1:acc#301.itm} 2 {ACC1:acc#301.itm(0)} {ACC1:acc#301.itm(1)} -attr xrf 52761 -attr oid 817 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {conc#995.itm(0)} -attr vt d
+load net {conc#995.itm(1)} -attr vt d
+load net {conc#995.itm(2)} -attr vt d
+load net {conc#995.itm(3)} -attr vt d
+load net {conc#995.itm(4)} -attr vt d
+load net {conc#995.itm(5)} -attr vt d
+load net {conc#995.itm(6)} -attr vt d
+load net {conc#995.itm(7)} -attr vt d
+load netBundle {conc#995.itm} 8 {conc#995.itm(0)} {conc#995.itm(1)} {conc#995.itm(2)} {conc#995.itm(3)} {conc#995.itm(4)} {conc#995.itm(5)} {conc#995.itm(6)} {conc#995.itm(7)} -attr xrf 52762 -attr oid 818 -attr vt d -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {slc(regs.regs(1).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#2.itm} 10 {slc(regs.regs(1).sva)#2.itm(0)} {slc(regs.regs(1).sva)#2.itm(1)} {slc(regs.regs(1).sva)#2.itm(2)} {slc(regs.regs(1).sva)#2.itm(3)} {slc(regs.regs(1).sva)#2.itm(4)} {slc(regs.regs(1).sva)#2.itm(5)} {slc(regs.regs(1).sva)#2.itm(6)} {slc(regs.regs(1).sva)#2.itm(7)} {slc(regs.regs(1).sva)#2.itm(8)} {slc(regs.regs(1).sva)#2.itm(9)} -attr xrf 52763 -attr oid 819 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {slc(regs.regs(1).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#1.itm} 10 {slc(regs.regs(1).sva)#1.itm(0)} {slc(regs.regs(1).sva)#1.itm(1)} {slc(regs.regs(1).sva)#1.itm(2)} {slc(regs.regs(1).sva)#1.itm(3)} {slc(regs.regs(1).sva)#1.itm(4)} {slc(regs.regs(1).sva)#1.itm(5)} {slc(regs.regs(1).sva)#1.itm(6)} {slc(regs.regs(1).sva)#1.itm(7)} {slc(regs.regs(1).sva)#1.itm(8)} {slc(regs.regs(1).sva)#1.itm(9)} -attr xrf 52764 -attr oid 820 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {slc(regs.regs(1).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva).itm} 10 {slc(regs.regs(1).sva).itm(0)} {slc(regs.regs(1).sva).itm(1)} {slc(regs.regs(1).sva).itm(2)} {slc(regs.regs(1).sva).itm(3)} {slc(regs.regs(1).sva).itm(4)} {slc(regs.regs(1).sva).itm(5)} {slc(regs.regs(1).sva).itm(6)} {slc(regs.regs(1).sva).itm(7)} {slc(regs.regs(1).sva).itm(8)} {slc(regs.regs(1).sva).itm(9)} -attr xrf 52765 -attr oid 821 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {slc(regs.regs(1).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#5.itm} 10 {slc(regs.regs(1).sva)#5.itm(0)} {slc(regs.regs(1).sva)#5.itm(1)} {slc(regs.regs(1).sva)#5.itm(2)} {slc(regs.regs(1).sva)#5.itm(3)} {slc(regs.regs(1).sva)#5.itm(4)} {slc(regs.regs(1).sva)#5.itm(5)} {slc(regs.regs(1).sva)#5.itm(6)} {slc(regs.regs(1).sva)#5.itm(7)} {slc(regs.regs(1).sva)#5.itm(8)} {slc(regs.regs(1).sva)#5.itm(9)} -attr xrf 52766 -attr oid 822 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {slc(regs.regs(1).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#4.itm} 10 {slc(regs.regs(1).sva)#4.itm(0)} {slc(regs.regs(1).sva)#4.itm(1)} {slc(regs.regs(1).sva)#4.itm(2)} {slc(regs.regs(1).sva)#4.itm(3)} {slc(regs.regs(1).sva)#4.itm(4)} {slc(regs.regs(1).sva)#4.itm(5)} {slc(regs.regs(1).sva)#4.itm(6)} {slc(regs.regs(1).sva)#4.itm(7)} {slc(regs.regs(1).sva)#4.itm(8)} {slc(regs.regs(1).sva)#4.itm(9)} -attr xrf 52767 -attr oid 823 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {slc(regs.regs(1).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#3.itm} 10 {slc(regs.regs(1).sva)#3.itm(0)} {slc(regs.regs(1).sva)#3.itm(1)} {slc(regs.regs(1).sva)#3.itm(2)} {slc(regs.regs(1).sva)#3.itm(3)} {slc(regs.regs(1).sva)#3.itm(4)} {slc(regs.regs(1).sva)#3.itm(5)} {slc(regs.regs(1).sva)#3.itm(6)} {slc(regs.regs(1).sva)#3.itm(7)} {slc(regs.regs(1).sva)#3.itm(8)} {slc(regs.regs(1).sva)#3.itm(9)} -attr xrf 52768 -attr oid 824 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {slc(regs.regs(1).sva)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#8.itm} 10 {slc(regs.regs(1).sva)#8.itm(0)} {slc(regs.regs(1).sva)#8.itm(1)} {slc(regs.regs(1).sva)#8.itm(2)} {slc(regs.regs(1).sva)#8.itm(3)} {slc(regs.regs(1).sva)#8.itm(4)} {slc(regs.regs(1).sva)#8.itm(5)} {slc(regs.regs(1).sva)#8.itm(6)} {slc(regs.regs(1).sva)#8.itm(7)} {slc(regs.regs(1).sva)#8.itm(8)} {slc(regs.regs(1).sva)#8.itm(9)} -attr xrf 52769 -attr oid 825 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {slc(regs.regs(1).sva)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#7.itm} 10 {slc(regs.regs(1).sva)#7.itm(0)} {slc(regs.regs(1).sva)#7.itm(1)} {slc(regs.regs(1).sva)#7.itm(2)} {slc(regs.regs(1).sva)#7.itm(3)} {slc(regs.regs(1).sva)#7.itm(4)} {slc(regs.regs(1).sva)#7.itm(5)} {slc(regs.regs(1).sva)#7.itm(6)} {slc(regs.regs(1).sva)#7.itm(7)} {slc(regs.regs(1).sva)#7.itm(8)} {slc(regs.regs(1).sva)#7.itm(9)} -attr xrf 52770 -attr oid 826 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {slc(regs.regs(1).sva)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#6.itm} 10 {slc(regs.regs(1).sva)#6.itm(0)} {slc(regs.regs(1).sva)#6.itm(1)} {slc(regs.regs(1).sva)#6.itm(2)} {slc(regs.regs(1).sva)#6.itm(3)} {slc(regs.regs(1).sva)#6.itm(4)} {slc(regs.regs(1).sva)#6.itm(5)} {slc(regs.regs(1).sva)#6.itm(6)} {slc(regs.regs(1).sva)#6.itm(7)} {slc(regs.regs(1).sva)#6.itm(8)} {slc(regs.regs(1).sva)#6.itm(9)} -attr xrf 52771 -attr oid 827 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {FRAME:acc#15.itm(0)} -attr vt d
+load net {FRAME:acc#15.itm(1)} -attr vt d
+load net {FRAME:acc#15.itm(2)} -attr vt d
+load net {FRAME:acc#15.itm(3)} -attr vt d
+load net {FRAME:acc#15.itm(4)} -attr vt d
+load net {FRAME:acc#15.itm(5)} -attr vt d
+load net {FRAME:acc#15.itm(6)} -attr vt d
+load net {FRAME:acc#15.itm(7)} -attr vt d
+load net {FRAME:acc#15.itm(8)} -attr vt d
+load net {FRAME:acc#15.itm(9)} -attr vt d
+load net {FRAME:acc#15.itm(10)} -attr vt d
+load net {FRAME:acc#15.itm(11)} -attr vt d
+load netBundle {FRAME:acc#15.itm} 12 {FRAME:acc#15.itm(0)} {FRAME:acc#15.itm(1)} {FRAME:acc#15.itm(2)} {FRAME:acc#15.itm(3)} {FRAME:acc#15.itm(4)} {FRAME:acc#15.itm(5)} {FRAME:acc#15.itm(6)} {FRAME:acc#15.itm(7)} {FRAME:acc#15.itm(8)} {FRAME:acc#15.itm(9)} {FRAME:acc#15.itm(10)} {FRAME:acc#15.itm(11)} -attr xrf 52772 -attr oid 828 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:mul.itm(0)} -attr vt d
+load net {FRAME:mul.itm(1)} -attr vt d
+load net {FRAME:mul.itm(2)} -attr vt d
+load net {FRAME:mul.itm(3)} -attr vt d
+load net {FRAME:mul.itm(4)} -attr vt d
+load net {FRAME:mul.itm(5)} -attr vt d
+load net {FRAME:mul.itm(6)} -attr vt d
+load net {FRAME:mul.itm(7)} -attr vt d
+load net {FRAME:mul.itm(8)} -attr vt d
+load net {FRAME:mul.itm(9)} -attr vt d
+load net {FRAME:mul.itm(10)} -attr vt d
+load netBundle {FRAME:mul.itm} 11 {FRAME:mul.itm(0)} {FRAME:mul.itm(1)} {FRAME:mul.itm(2)} {FRAME:mul.itm(3)} {FRAME:mul.itm(4)} {FRAME:mul.itm(5)} {FRAME:mul.itm(6)} {FRAME:mul.itm(7)} {FRAME:mul.itm(8)} {FRAME:mul.itm(9)} {FRAME:mul.itm(10)} -attr xrf 52773 -attr oid 829 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {slc(ACC1:slc.psp.sva)#13.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#13.itm(1)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#13.itm} 2 {slc(ACC1:slc.psp.sva)#13.itm(0)} {slc(ACC1:slc.psp.sva)#13.itm(1)} -attr xrf 52774 -attr oid 830 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#13.itm}
+load net {FRAME:acc#14.itm(0)} -attr vt d
+load net {FRAME:acc#14.itm(1)} -attr vt d
+load net {FRAME:acc#14.itm(2)} -attr vt d
+load net {FRAME:acc#14.itm(3)} -attr vt d
+load net {FRAME:acc#14.itm(4)} -attr vt d
+load net {FRAME:acc#14.itm(5)} -attr vt d
+load net {FRAME:acc#14.itm(6)} -attr vt d
+load net {FRAME:acc#14.itm(7)} -attr vt d
+load net {FRAME:acc#14.itm(8)} -attr vt d
+load net {FRAME:acc#14.itm(9)} -attr vt d
+load netBundle {FRAME:acc#14.itm} 10 {FRAME:acc#14.itm(0)} {FRAME:acc#14.itm(1)} {FRAME:acc#14.itm(2)} {FRAME:acc#14.itm(3)} {FRAME:acc#14.itm(4)} {FRAME:acc#14.itm(5)} {FRAME:acc#14.itm(6)} {FRAME:acc#14.itm(7)} {FRAME:acc#14.itm(8)} {FRAME:acc#14.itm(9)} -attr xrf 52775 -attr oid 831 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:mul#1.itm(0)} -attr vt d
+load net {FRAME:mul#1.itm(1)} -attr vt d
+load net {FRAME:mul#1.itm(2)} -attr vt d
+load net {FRAME:mul#1.itm(3)} -attr vt d
+load net {FRAME:mul#1.itm(4)} -attr vt d
+load net {FRAME:mul#1.itm(5)} -attr vt d
+load net {FRAME:mul#1.itm(6)} -attr vt d
+load net {FRAME:mul#1.itm(7)} -attr vt d
+load net {FRAME:mul#1.itm(8)} -attr vt d
+load netBundle {FRAME:mul#1.itm} 9 {FRAME:mul#1.itm(0)} {FRAME:mul#1.itm(1)} {FRAME:mul#1.itm(2)} {FRAME:mul#1.itm(3)} {FRAME:mul#1.itm(4)} {FRAME:mul#1.itm(5)} {FRAME:mul#1.itm(6)} {FRAME:mul#1.itm(7)} {FRAME:mul#1.itm(8)} -attr xrf 52776 -attr oid 832 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {slc(ACC1:slc.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#1.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#1.itm} 3 {slc(ACC1:slc.psp.sva)#1.itm(0)} {slc(ACC1:slc.psp.sva)#1.itm(1)} {slc(ACC1:slc.psp.sva)#1.itm(2)} -attr xrf 52777 -attr oid 833 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#1.itm}
+load net {FRAME:acc#13.itm(0)} -attr vt d
+load net {FRAME:acc#13.itm(1)} -attr vt d
+load net {FRAME:acc#13.itm(2)} -attr vt d
+load net {FRAME:acc#13.itm(3)} -attr vt d
+load net {FRAME:acc#13.itm(4)} -attr vt d
+load net {FRAME:acc#13.itm(5)} -attr vt d
+load net {FRAME:acc#13.itm(6)} -attr vt d
+load netBundle {FRAME:acc#13.itm} 7 {FRAME:acc#13.itm(0)} {FRAME:acc#13.itm(1)} {FRAME:acc#13.itm(2)} {FRAME:acc#13.itm(3)} {FRAME:acc#13.itm(4)} {FRAME:acc#13.itm(5)} {FRAME:acc#13.itm(6)} -attr xrf 52778 -attr oid 834 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {slc(ACC1:slc.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#2.itm(2)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#2.itm(3)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#2.itm(4)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#2.itm} 6 {slc(ACC1:slc.psp.sva)#2.itm(0)} {slc(ACC1:slc.psp.sva)#2.itm(1)} {slc(ACC1:slc.psp.sva)#2.itm(2)} {slc(ACC1:slc.psp.sva)#2.itm(3)} {slc(ACC1:slc.psp.sva)#2.itm(4)} {slc(ACC1:slc.psp.sva)#2.itm(5)} -attr xrf 52779 -attr oid 835 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#2.itm}
+load net {FRAME:acc#12.itm(0)} -attr vt d
+load net {FRAME:acc#12.itm(1)} -attr vt d
+load net {FRAME:acc#12.itm(2)} -attr vt d
+load net {FRAME:acc#12.itm(3)} -attr vt d
+load net {FRAME:acc#12.itm(4)} -attr vt d
+load netBundle {FRAME:acc#12.itm} 5 {FRAME:acc#12.itm(0)} {FRAME:acc#12.itm(1)} {FRAME:acc#12.itm(2)} {FRAME:acc#12.itm(3)} {FRAME:acc#12.itm(4)} -attr xrf 52780 -attr oid 836 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {conc#996.itm(0)} -attr vt d
+load net {conc#996.itm(1)} -attr vt d
+load net {conc#996.itm(2)} -attr vt d
+load net {conc#996.itm(3)} -attr vt d
+load net {conc#996.itm(4)} -attr vt d
+load netBundle {conc#996.itm} 5 {conc#996.itm(0)} {conc#996.itm(1)} {conc#996.itm(2)} {conc#996.itm(3)} {conc#996.itm(4)} -attr xrf 52781 -attr oid 837 -attr vt d -attr @path {/sobel/sobel:core/conc#996.itm}
+load net {FRAME:acc#11.itm(0)} -attr vt d
+load net {FRAME:acc#11.itm(1)} -attr vt d
+load net {FRAME:acc#11.itm(2)} -attr vt d
+load net {FRAME:acc#11.itm(3)} -attr vt d
+load netBundle {FRAME:acc#11.itm} 4 {FRAME:acc#11.itm(0)} {FRAME:acc#11.itm(1)} {FRAME:acc#11.itm(2)} {FRAME:acc#11.itm(3)} -attr xrf 52782 -attr oid 838 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#10.itm(0)} -attr vt d
+load net {FRAME:acc#10.itm(1)} -attr vt d
+load net {FRAME:acc#10.itm(2)} -attr vt d
+load net {FRAME:acc#10.itm(3)} -attr vt d
+load netBundle {FRAME:acc#10.itm} 4 {FRAME:acc#10.itm(0)} {FRAME:acc#10.itm(1)} {FRAME:acc#10.itm(2)} {FRAME:acc#10.itm(3)} -attr xrf 52783 -attr oid 839 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {conc#997.itm(0)} -attr vt d
+load net {conc#997.itm(1)} -attr vt d
+load net {conc#997.itm(2)} -attr vt d
+load netBundle {conc#997.itm} 3 {conc#997.itm(0)} {conc#997.itm(1)} {conc#997.itm(2)} -attr xrf 52784 -attr oid 840 -attr vt d -attr @path {/sobel/sobel:core/conc#997.itm}
+load net {conc#998.itm(0)} -attr vt d
+load net {conc#998.itm(1)} -attr vt d
+load net {conc#998.itm(2)} -attr vt d
+load net {conc#998.itm(3)} -attr vt d
+load net {conc#998.itm(4)} -attr vt d
+load netBundle {conc#998.itm} 5 {conc#998.itm(0)} {conc#998.itm(1)} {conc#998.itm(2)} {conc#998.itm(3)} {conc#998.itm(4)} -attr xrf 52785 -attr oid 841 -attr vt d -attr @path {/sobel/sobel:core/conc#998.itm}
+load net {slc(acc.imod#24.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#24.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#24.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#24.sva)#1.itm} 3 {slc(acc.imod#24.sva)#1.itm(0)} {slc(acc.imod#24.sva)#1.itm(1)} {slc(acc.imod#24.sva)#1.itm(2)} -attr xrf 52786 -attr oid 842 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#1.itm}
+load net {FRAME:conc#15.itm(0)} -attr vt d
+load net {FRAME:conc#15.itm(1)} -attr vt d
+load net {FRAME:conc#15.itm(2)} -attr vt d
+load net {FRAME:conc#15.itm(3)} -attr vt d
+load netBundle {FRAME:conc#15.itm} 4 {FRAME:conc#15.itm(0)} {FRAME:conc#15.itm(1)} {FRAME:conc#15.itm(2)} {FRAME:conc#15.itm(3)} -attr xrf 52787 -attr oid 843 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(0)} -attr vt d
+load net {FRAME:not#5.itm(1)} -attr vt d
+load net {FRAME:not#5.itm(2)} -attr vt d
+load netBundle {FRAME:not#5.itm} 3 {FRAME:not#5.itm(0)} {FRAME:not#5.itm(1)} {FRAME:not#5.itm(2)} -attr xrf 52788 -attr oid 844 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {slc(acc.imod#24.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#24.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#24.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#24.sva)#2.itm} 3 {slc(acc.imod#24.sva)#2.itm(0)} {slc(acc.imod#24.sva)#2.itm(1)} {slc(acc.imod#24.sva)#2.itm(2)} -attr xrf 52789 -attr oid 845 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#2.itm}
+load net {slc(acc.imod#24.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#24.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#24.sva)#4.itm} 2 {slc(acc.imod#24.sva)#4.itm(0)} {slc(acc.imod#24.sva)#4.itm(1)} -attr xrf 52790 -attr oid 846 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#4.itm}
+load net {FRAME:not#6.itm(0)} -attr vt d
+load net {FRAME:not#6.itm(1)} -attr vt d
+load net {FRAME:not#6.itm(2)} -attr vt d
+load netBundle {FRAME:not#6.itm} 3 {FRAME:not#6.itm(0)} {FRAME:not#6.itm(1)} {FRAME:not#6.itm(2)} -attr xrf 52791 -attr oid 847 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {slc(ACC1:slc.psp.sva)#3.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#3.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#3.itm} 3 {slc(ACC1:slc.psp.sva)#3.itm(0)} {slc(ACC1:slc.psp.sva)#3.itm(1)} {slc(ACC1:slc.psp.sva)#3.itm(2)} -attr xrf 52792 -attr oid 848 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#3.itm}
+load net {exs#103.itm(0)} -attr vt d
+load net {exs#103.itm(1)} -attr vt d
+load net {exs#103.itm(2)} -attr vt d
+load net {exs#103.itm(3)} -attr vt d
+load net {exs#103.itm(4)} -attr vt d
+load net {exs#103.itm(5)} -attr vt d
+load net {exs#103.itm(6)} -attr vt d
+load net {exs#103.itm(7)} -attr vt d
+load net {exs#103.itm(8)} -attr vt d
+load net {exs#103.itm(9)} -attr vt d
+load net {exs#103.itm(10)} -attr vt d
+load netBundle {exs#103.itm} 11 {exs#103.itm(0)} {exs#103.itm(1)} {exs#103.itm(2)} {exs#103.itm(3)} {exs#103.itm(4)} {exs#103.itm(5)} {exs#103.itm(6)} {exs#103.itm(7)} {exs#103.itm(8)} {exs#103.itm(9)} {exs#103.itm(10)} -attr xrf 52793 -attr oid 849 -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {conc#999.itm(0)} -attr vt d
+load net {conc#999.itm(1)} -attr vt d
+load net {conc#999.itm(2)} -attr vt d
+load net {conc#999.itm(3)} -attr vt d
+load net {conc#999.itm(4)} -attr vt d
+load net {conc#999.itm(5)} -attr vt d
+load net {conc#999.itm(6)} -attr vt d
+load net {conc#999.itm(7)} -attr vt d
+load net {conc#999.itm(8)} -attr vt d
+load netBundle {conc#999.itm} 9 {conc#999.itm(0)} {conc#999.itm(1)} {conc#999.itm(2)} {conc#999.itm(3)} {conc#999.itm(4)} {conc#999.itm(5)} {conc#999.itm(6)} {conc#999.itm(7)} {conc#999.itm(8)} -attr xrf 52794 -attr oid 850 -attr vt d -attr @path {/sobel/sobel:core/conc#999.itm}
+load net {FRAME:exs#5.itm(0)} -attr vt d
+load net {FRAME:exs#5.itm(1)} -attr vt d
+load net {FRAME:exs#5.itm(2)} -attr vt d
+load netBundle {FRAME:exs#5.itm} 3 {FRAME:exs#5.itm(0)} {FRAME:exs#5.itm(1)} {FRAME:exs#5.itm(2)} -attr xrf 52795 -attr oid 851 -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#5.itm}
+load net {ACC1:acc.itm(0)} -attr vt d
+load net {ACC1:acc.itm(1)} -attr vt d
+load net {ACC1:acc.itm(2)} -attr vt d
+load net {ACC1:acc.itm(3)} -attr vt d
+load net {ACC1:acc.itm(4)} -attr vt d
+load net {ACC1:acc.itm(5)} -attr vt d
+load net {ACC1:acc.itm(6)} -attr vt d
+load net {ACC1:acc.itm(7)} -attr vt d
+load net {ACC1:acc.itm(8)} -attr vt d
+load net {ACC1:acc.itm(9)} -attr vt d
+load net {ACC1:acc.itm(10)} -attr vt d
+load net {ACC1:acc.itm(11)} -attr vt d
+load net {ACC1:acc.itm(12)} -attr vt d
+load net {ACC1:acc.itm(13)} -attr vt d
+load net {ACC1:acc.itm(14)} -attr vt d
+load netBundle {ACC1:acc.itm} 15 {ACC1:acc.itm(0)} {ACC1:acc.itm(1)} {ACC1:acc.itm(2)} {ACC1:acc.itm(3)} {ACC1:acc.itm(4)} {ACC1:acc.itm(5)} {ACC1:acc.itm(6)} {ACC1:acc.itm(7)} {ACC1:acc.itm(8)} {ACC1:acc.itm(9)} {ACC1:acc.itm(10)} {ACC1:acc.itm(11)} {ACC1:acc.itm(12)} {ACC1:acc.itm(13)} {ACC1:acc.itm(14)} -attr xrf 52796 -attr oid 852 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc#664.itm(0)} -attr vt d
+load net {ACC1:acc#664.itm(1)} -attr vt d
+load net {ACC1:acc#664.itm(2)} -attr vt d
+load net {ACC1:acc#664.itm(3)} -attr vt d
+load net {ACC1:acc#664.itm(4)} -attr vt d
+load net {ACC1:acc#664.itm(5)} -attr vt d
+load net {ACC1:acc#664.itm(6)} -attr vt d
+load net {ACC1:acc#664.itm(7)} -attr vt d
+load net {ACC1:acc#664.itm(8)} -attr vt d
+load net {ACC1:acc#664.itm(9)} -attr vt d
+load net {ACC1:acc#664.itm(10)} -attr vt d
+load net {ACC1:acc#664.itm(11)} -attr vt d
+load net {ACC1:acc#664.itm(12)} -attr vt d
+load net {ACC1:acc#664.itm(13)} -attr vt d
+load net {ACC1:acc#664.itm(14)} -attr vt d
+load netBundle {ACC1:acc#664.itm} 15 {ACC1:acc#664.itm(0)} {ACC1:acc#664.itm(1)} {ACC1:acc#664.itm(2)} {ACC1:acc#664.itm(3)} {ACC1:acc#664.itm(4)} {ACC1:acc#664.itm(5)} {ACC1:acc#664.itm(6)} {ACC1:acc#664.itm(7)} {ACC1:acc#664.itm(8)} {ACC1:acc#664.itm(9)} {ACC1:acc#664.itm(10)} {ACC1:acc#664.itm(11)} {ACC1:acc#664.itm(12)} {ACC1:acc#664.itm(13)} {ACC1:acc#664.itm(14)} -attr xrf 52797 -attr oid 853 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#662.itm(0)} -attr vt d
+load net {ACC1:acc#662.itm(1)} -attr vt d
+load net {ACC1:acc#662.itm(2)} -attr vt d
+load net {ACC1:acc#662.itm(3)} -attr vt d
+load net {ACC1:acc#662.itm(4)} -attr vt d
+load net {ACC1:acc#662.itm(5)} -attr vt d
+load net {ACC1:acc#662.itm(6)} -attr vt d
+load net {ACC1:acc#662.itm(7)} -attr vt d
+load net {ACC1:acc#662.itm(8)} -attr vt d
+load net {ACC1:acc#662.itm(9)} -attr vt d
+load net {ACC1:acc#662.itm(10)} -attr vt d
+load net {ACC1:acc#662.itm(11)} -attr vt d
+load net {ACC1:acc#662.itm(12)} -attr vt d
+load net {ACC1:acc#662.itm(13)} -attr vt d
+load netBundle {ACC1:acc#662.itm} 14 {ACC1:acc#662.itm(0)} {ACC1:acc#662.itm(1)} {ACC1:acc#662.itm(2)} {ACC1:acc#662.itm(3)} {ACC1:acc#662.itm(4)} {ACC1:acc#662.itm(5)} {ACC1:acc#662.itm(6)} {ACC1:acc#662.itm(7)} {ACC1:acc#662.itm(8)} {ACC1:acc#662.itm(9)} {ACC1:acc#662.itm(10)} {ACC1:acc#662.itm(11)} {ACC1:acc#662.itm(12)} {ACC1:acc#662.itm(13)} -attr xrf 52798 -attr oid 854 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#663.itm(0)} -attr vt d
+load net {ACC1:acc#663.itm(1)} -attr vt d
+load net {ACC1:acc#663.itm(2)} -attr vt d
+load net {ACC1:acc#663.itm(3)} -attr vt d
+load net {ACC1:acc#663.itm(4)} -attr vt d
+load net {ACC1:acc#663.itm(5)} -attr vt d
+load net {ACC1:acc#663.itm(6)} -attr vt d
+load net {ACC1:acc#663.itm(7)} -attr vt d
+load net {ACC1:acc#663.itm(8)} -attr vt d
+load net {ACC1:acc#663.itm(9)} -attr vt d
+load net {ACC1:acc#663.itm(10)} -attr vt d
+load net {ACC1:acc#663.itm(11)} -attr vt d
+load net {ACC1:acc#663.itm(12)} -attr vt d
+load net {ACC1:acc#663.itm(13)} -attr vt d
+load netBundle {ACC1:acc#663.itm} 14 {ACC1:acc#663.itm(0)} {ACC1:acc#663.itm(1)} {ACC1:acc#663.itm(2)} {ACC1:acc#663.itm(3)} {ACC1:acc#663.itm(4)} {ACC1:acc#663.itm(5)} {ACC1:acc#663.itm(6)} {ACC1:acc#663.itm(7)} {ACC1:acc#663.itm(8)} {ACC1:acc#663.itm(9)} {ACC1:acc#663.itm(10)} {ACC1:acc#663.itm(11)} {ACC1:acc#663.itm(12)} {ACC1:acc#663.itm(13)} -attr xrf 52799 -attr oid 855 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {conc#1001.itm(0)} -attr vt d
+load net {conc#1001.itm(1)} -attr vt d
+load net {conc#1001.itm(2)} -attr vt d
+load net {conc#1001.itm(3)} -attr vt d
+load net {conc#1001.itm(4)} -attr vt d
+load net {conc#1001.itm(5)} -attr vt d
+load net {conc#1001.itm(6)} -attr vt d
+load net {conc#1001.itm(7)} -attr vt d
+load net {conc#1001.itm(8)} -attr vt d
+load net {conc#1001.itm(9)} -attr vt d
+load net {conc#1001.itm(10)} -attr vt d
+load net {conc#1001.itm(11)} -attr vt d
+load net {conc#1001.itm(12)} -attr vt d
+load net {conc#1001.itm(13)} -attr vt d
+load netBundle {conc#1001.itm} 14 {conc#1001.itm(0)} {conc#1001.itm(1)} {conc#1001.itm(2)} {conc#1001.itm(3)} {conc#1001.itm(4)} {conc#1001.itm(5)} {conc#1001.itm(6)} {conc#1001.itm(7)} {conc#1001.itm(8)} {conc#1001.itm(9)} {conc#1001.itm(10)} {conc#1001.itm(11)} {conc#1001.itm(12)} {conc#1001.itm(13)} -attr xrf 52800 -attr oid 856 -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:acc#660.itm(0)} -attr vt d
+load net {ACC1:acc#660.itm(1)} -attr vt d
+load net {ACC1:acc#660.itm(2)} -attr vt d
+load net {ACC1:acc#660.itm(3)} -attr vt d
+load net {ACC1:acc#660.itm(4)} -attr vt d
+load net {ACC1:acc#660.itm(5)} -attr vt d
+load net {ACC1:acc#660.itm(6)} -attr vt d
+load net {ACC1:acc#660.itm(7)} -attr vt d
+load net {ACC1:acc#660.itm(8)} -attr vt d
+load net {ACC1:acc#660.itm(9)} -attr vt d
+load net {ACC1:acc#660.itm(10)} -attr vt d
+load net {ACC1:acc#660.itm(11)} -attr vt d
+load net {ACC1:acc#660.itm(12)} -attr vt d
+load netBundle {ACC1:acc#660.itm} 13 {ACC1:acc#660.itm(0)} {ACC1:acc#660.itm(1)} {ACC1:acc#660.itm(2)} {ACC1:acc#660.itm(3)} {ACC1:acc#660.itm(4)} {ACC1:acc#660.itm(5)} {ACC1:acc#660.itm(6)} {ACC1:acc#660.itm(7)} {ACC1:acc#660.itm(8)} {ACC1:acc#660.itm(9)} {ACC1:acc#660.itm(10)} {ACC1:acc#660.itm(11)} {ACC1:acc#660.itm(12)} -attr xrf 52801 -attr oid 857 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#656.itm(0)} -attr vt d
+load net {ACC1:acc#656.itm(1)} -attr vt d
+load net {ACC1:acc#656.itm(2)} -attr vt d
+load net {ACC1:acc#656.itm(3)} -attr vt d
+load net {ACC1:acc#656.itm(4)} -attr vt d
+load net {ACC1:acc#656.itm(5)} -attr vt d
+load net {ACC1:acc#656.itm(6)} -attr vt d
+load net {ACC1:acc#656.itm(7)} -attr vt d
+load net {ACC1:acc#656.itm(8)} -attr vt d
+load net {ACC1:acc#656.itm(9)} -attr vt d
+load net {ACC1:acc#656.itm(10)} -attr vt d
+load net {ACC1:acc#656.itm(11)} -attr vt d
+load netBundle {ACC1:acc#656.itm} 12 {ACC1:acc#656.itm(0)} {ACC1:acc#656.itm(1)} {ACC1:acc#656.itm(2)} {ACC1:acc#656.itm(3)} {ACC1:acc#656.itm(4)} {ACC1:acc#656.itm(5)} {ACC1:acc#656.itm(6)} {ACC1:acc#656.itm(7)} {ACC1:acc#656.itm(8)} {ACC1:acc#656.itm(9)} {ACC1:acc#656.itm(10)} {ACC1:acc#656.itm(11)} -attr xrf 52802 -attr oid 858 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {conc#1002.itm(0)} -attr vt d
+load net {conc#1002.itm(1)} -attr vt d
+load net {conc#1002.itm(2)} -attr vt d
+load net {conc#1002.itm(3)} -attr vt d
+load net {conc#1002.itm(4)} -attr vt d
+load net {conc#1002.itm(5)} -attr vt d
+load net {conc#1002.itm(6)} -attr vt d
+load net {conc#1002.itm(7)} -attr vt d
+load net {conc#1002.itm(8)} -attr vt d
+load net {conc#1002.itm(9)} -attr vt d
+load net {conc#1002.itm(10)} -attr vt d
+load net {conc#1002.itm(11)} -attr vt d
+load netBundle {conc#1002.itm} 12 {conc#1002.itm(0)} {conc#1002.itm(1)} {conc#1002.itm(2)} {conc#1002.itm(3)} {conc#1002.itm(4)} {conc#1002.itm(5)} {conc#1002.itm(6)} {conc#1002.itm(7)} {conc#1002.itm(8)} {conc#1002.itm(9)} {conc#1002.itm(10)} {conc#1002.itm(11)} -attr xrf 52803 -attr oid 859 -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {ACC1-3:exs#1074.itm(0)} -attr vt d
+load net {ACC1-3:exs#1074.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1074.itm} 2 {ACC1-3:exs#1074.itm(0)} {ACC1-3:exs#1074.itm(1)} -attr xrf 52804 -attr oid 860 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1074.itm}
+load net {FRAME:acc#9.itm(0)} -attr vt d
+load net {FRAME:acc#9.itm(1)} -attr vt d
+load net {FRAME:acc#9.itm(2)} -attr vt d
+load net {FRAME:acc#9.itm(3)} -attr vt d
+load net {FRAME:acc#9.itm(4)} -attr vt d
+load net {FRAME:acc#9.itm(5)} -attr vt d
+load netBundle {FRAME:acc#9.itm} 6 {FRAME:acc#9.itm(0)} {FRAME:acc#9.itm(1)} {FRAME:acc#9.itm(2)} {FRAME:acc#9.itm(3)} {FRAME:acc#9.itm(4)} {FRAME:acc#9.itm(5)} -attr xrf 52805 -attr oid 861 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#8.itm(0)} -attr vt d
+load net {FRAME:acc#8.itm(1)} -attr vt d
+load net {FRAME:acc#8.itm(2)} -attr vt d
+load net {FRAME:acc#8.itm(3)} -attr vt d
+load net {FRAME:acc#8.itm(4)} -attr vt d
+load netBundle {FRAME:acc#8.itm} 5 {FRAME:acc#8.itm(0)} {FRAME:acc#8.itm(1)} {FRAME:acc#8.itm(2)} {FRAME:acc#8.itm(3)} {FRAME:acc#8.itm(4)} -attr xrf 52806 -attr oid 862 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#6.itm(0)} -attr vt d
+load net {FRAME:acc#6.itm(1)} -attr vt d
+load net {FRAME:acc#6.itm(2)} -attr vt d
+load net {FRAME:acc#6.itm(3)} -attr vt d
+load netBundle {FRAME:acc#6.itm} 4 {FRAME:acc#6.itm(0)} {FRAME:acc#6.itm(1)} {FRAME:acc#6.itm(2)} {FRAME:acc#6.itm(3)} -attr xrf 52807 -attr oid 863 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {slc(ACC1:slc.psp.sva)#5.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#5.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#5.itm} 3 {slc(ACC1:slc.psp.sva)#5.itm(0)} {slc(ACC1:slc.psp.sva)#5.itm(1)} {slc(ACC1:slc.psp.sva)#5.itm(2)} -attr xrf 52808 -attr oid 864 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#5.itm}
+load net {FRAME:not#2.itm(0)} -attr vt d
+load net {FRAME:not#2.itm(1)} -attr vt d
+load net {FRAME:not#2.itm(2)} -attr vt d
+load netBundle {FRAME:not#2.itm} 3 {FRAME:not#2.itm(0)} {FRAME:not#2.itm(1)} {FRAME:not#2.itm(2)} -attr xrf 52809 -attr oid 865 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {slc(ACC1:slc.psp.sva)#6.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#6.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#6.itm} 3 {slc(ACC1:slc.psp.sva)#6.itm(0)} {slc(ACC1:slc.psp.sva)#6.itm(1)} {slc(ACC1:slc.psp.sva)#6.itm(2)} -attr xrf 52810 -attr oid 866 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#6.itm}
+load net {FRAME:acc#5.itm(0)} -attr vt d
+load net {FRAME:acc#5.itm(1)} -attr vt d
+load net {FRAME:acc#5.itm(2)} -attr vt d
+load net {FRAME:acc#5.itm(3)} -attr vt d
+load netBundle {FRAME:acc#5.itm} 4 {FRAME:acc#5.itm(0)} {FRAME:acc#5.itm(1)} {FRAME:acc#5.itm(2)} {FRAME:acc#5.itm(3)} -attr xrf 52811 -attr oid 867 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {conc#1003.itm(0)} -attr vt d
+load net {conc#1003.itm(1)} -attr vt d
+load net {conc#1003.itm(2)} -attr vt d
+load netBundle {conc#1003.itm} 3 {conc#1003.itm(0)} {conc#1003.itm(1)} {conc#1003.itm(2)} -attr xrf 52812 -attr oid 868 -attr vt d -attr @path {/sobel/sobel:core/conc#1003.itm}
+load net {slc(ACC1:slc.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva).itm} 2 {slc(ACC1:slc.psp.sva).itm(0)} {slc(ACC1:slc.psp.sva).itm(1)} -attr xrf 52813 -attr oid 869 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva).itm}
+load net {FRAME:acc#7.itm(0)} -attr vt d
+load net {FRAME:acc#7.itm(1)} -attr vt d
+load net {FRAME:acc#7.itm(2)} -attr vt d
+load net {FRAME:acc#7.itm(3)} -attr vt d
+load netBundle {FRAME:acc#7.itm} 4 {FRAME:acc#7.itm(0)} {FRAME:acc#7.itm(1)} {FRAME:acc#7.itm(2)} {FRAME:acc#7.itm(3)} -attr xrf 52814 -attr oid 870 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {slc(ACC1:slc.psp.sva)#7.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#7.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#7.itm} 3 {slc(ACC1:slc.psp.sva)#7.itm(0)} {slc(ACC1:slc.psp.sva)#7.itm(1)} {slc(ACC1:slc.psp.sva)#7.itm(2)} -attr xrf 52815 -attr oid 871 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#7.itm}
+load net {FRAME:not#1.itm(0)} -attr vt d
+load net {FRAME:not#1.itm(1)} -attr vt d
+load net {FRAME:not#1.itm(2)} -attr vt d
+load netBundle {FRAME:not#1.itm} 3 {FRAME:not#1.itm(0)} {FRAME:not#1.itm(1)} {FRAME:not#1.itm(2)} -attr xrf 52816 -attr oid 872 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {slc(ACC1:slc.psp.sva)#8.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#8.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#8.itm(2)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#8.itm} 3 {slc(ACC1:slc.psp.sva)#8.itm(0)} {slc(ACC1:slc.psp.sva)#8.itm(1)} {slc(ACC1:slc.psp.sva)#8.itm(2)} -attr xrf 52817 -attr oid 873 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#8.itm}
+load net {ACC1:acc#416.itm(0)} -attr vt d
+load net {ACC1:acc#416.itm(1)} -attr vt d
+load net {ACC1:acc#416.itm(2)} -attr vt d
+load net {ACC1:acc#416.itm(3)} -attr vt d
+load net {ACC1:acc#416.itm(4)} -attr vt d
+load net {ACC1:acc#416.itm(5)} -attr vt d
+load net {ACC1:acc#416.itm(6)} -attr vt d
+load net {ACC1:acc#416.itm(7)} -attr vt d
+load net {ACC1:acc#416.itm(8)} -attr vt d
+load net {ACC1:acc#416.itm(9)} -attr vt d
+load net {ACC1:acc#416.itm(10)} -attr vt d
+load netBundle {ACC1:acc#416.itm} 11 {ACC1:acc#416.itm(0)} {ACC1:acc#416.itm(1)} {ACC1:acc#416.itm(2)} {ACC1:acc#416.itm(3)} {ACC1:acc#416.itm(4)} {ACC1:acc#416.itm(5)} {ACC1:acc#416.itm(6)} {ACC1:acc#416.itm(7)} {ACC1:acc#416.itm(8)} {ACC1:acc#416.itm(9)} {ACC1:acc#416.itm(10)} -attr xrf 52818 -attr oid 874 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#370.itm(0)} -attr vt d
+load net {ACC1:acc#370.itm(1)} -attr vt d
+load net {ACC1:acc#370.itm(2)} -attr vt d
+load net {ACC1:acc#370.itm(3)} -attr vt d
+load net {ACC1:acc#370.itm(4)} -attr vt d
+load net {ACC1:acc#370.itm(5)} -attr vt d
+load net {ACC1:acc#370.itm(6)} -attr vt d
+load net {ACC1:acc#370.itm(7)} -attr vt d
+load net {ACC1:acc#370.itm(8)} -attr vt d
+load net {ACC1:acc#370.itm(9)} -attr vt d
+load net {ACC1:acc#370.itm(10)} -attr vt d
+load netBundle {ACC1:acc#370.itm} 11 {ACC1:acc#370.itm(0)} {ACC1:acc#370.itm(1)} {ACC1:acc#370.itm(2)} {ACC1:acc#370.itm(3)} {ACC1:acc#370.itm(4)} {ACC1:acc#370.itm(5)} {ACC1:acc#370.itm(6)} {ACC1:acc#370.itm(7)} {ACC1:acc#370.itm(8)} {ACC1:acc#370.itm(9)} {ACC1:acc#370.itm(10)} -attr xrf 52819 -attr oid 875 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:not#309.itm(0)} -attr vt d
+load net {ACC1:not#309.itm(1)} -attr vt d
+load net {ACC1:not#309.itm(2)} -attr vt d
+load net {ACC1:not#309.itm(3)} -attr vt d
+load net {ACC1:not#309.itm(4)} -attr vt d
+load net {ACC1:not#309.itm(5)} -attr vt d
+load net {ACC1:not#309.itm(6)} -attr vt d
+load net {ACC1:not#309.itm(7)} -attr vt d
+load net {ACC1:not#309.itm(8)} -attr vt d
+load net {ACC1:not#309.itm(9)} -attr vt d
+load netBundle {ACC1:not#309.itm} 10 {ACC1:not#309.itm(0)} {ACC1:not#309.itm(1)} {ACC1:not#309.itm(2)} {ACC1:not#309.itm(3)} {ACC1:not#309.itm(4)} {ACC1:not#309.itm(5)} {ACC1:not#309.itm(6)} {ACC1:not#309.itm(7)} {ACC1:not#309.itm(8)} {ACC1:not#309.itm(9)} -attr xrf 52820 -attr oid 876 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {slc(regs.regs(0).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#3.itm} 10 {slc(regs.regs(0).sva)#3.itm(0)} {slc(regs.regs(0).sva)#3.itm(1)} {slc(regs.regs(0).sva)#3.itm(2)} {slc(regs.regs(0).sva)#3.itm(3)} {slc(regs.regs(0).sva)#3.itm(4)} {slc(regs.regs(0).sva)#3.itm(5)} {slc(regs.regs(0).sva)#3.itm(6)} {slc(regs.regs(0).sva)#3.itm(7)} {slc(regs.regs(0).sva)#3.itm(8)} {slc(regs.regs(0).sva)#3.itm(9)} -attr xrf 52821 -attr oid 877 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {ACC1:not#310.itm(0)} -attr vt d
+load net {ACC1:not#310.itm(1)} -attr vt d
+load net {ACC1:not#310.itm(2)} -attr vt d
+load net {ACC1:not#310.itm(3)} -attr vt d
+load net {ACC1:not#310.itm(4)} -attr vt d
+load net {ACC1:not#310.itm(5)} -attr vt d
+load net {ACC1:not#310.itm(6)} -attr vt d
+load net {ACC1:not#310.itm(7)} -attr vt d
+load net {ACC1:not#310.itm(8)} -attr vt d
+load net {ACC1:not#310.itm(9)} -attr vt d
+load netBundle {ACC1:not#310.itm} 10 {ACC1:not#310.itm(0)} {ACC1:not#310.itm(1)} {ACC1:not#310.itm(2)} {ACC1:not#310.itm(3)} {ACC1:not#310.itm(4)} {ACC1:not#310.itm(5)} {ACC1:not#310.itm(6)} {ACC1:not#310.itm(7)} {ACC1:not#310.itm(8)} {ACC1:not#310.itm(9)} -attr xrf 52822 -attr oid 878 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {slc(regs.regs(0).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#4.itm} 10 {slc(regs.regs(0).sva)#4.itm(0)} {slc(regs.regs(0).sva)#4.itm(1)} {slc(regs.regs(0).sva)#4.itm(2)} {slc(regs.regs(0).sva)#4.itm(3)} {slc(regs.regs(0).sva)#4.itm(4)} {slc(regs.regs(0).sva)#4.itm(5)} {slc(regs.regs(0).sva)#4.itm(6)} {slc(regs.regs(0).sva)#4.itm(7)} {slc(regs.regs(0).sva)#4.itm(8)} {slc(regs.regs(0).sva)#4.itm(9)} -attr xrf 52823 -attr oid 879 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {ACC1:acc#369.itm(0)} -attr vt d
+load net {ACC1:acc#369.itm(1)} -attr vt d
+load net {ACC1:acc#369.itm(2)} -attr vt d
+load net {ACC1:acc#369.itm(3)} -attr vt d
+load net {ACC1:acc#369.itm(4)} -attr vt d
+load net {ACC1:acc#369.itm(5)} -attr vt d
+load net {ACC1:acc#369.itm(6)} -attr vt d
+load net {ACC1:acc#369.itm(7)} -attr vt d
+load net {ACC1:acc#369.itm(8)} -attr vt d
+load net {ACC1:acc#369.itm(9)} -attr vt d
+load net {ACC1:acc#369.itm(10)} -attr vt d
+load netBundle {ACC1:acc#369.itm} 11 {ACC1:acc#369.itm(0)} {ACC1:acc#369.itm(1)} {ACC1:acc#369.itm(2)} {ACC1:acc#369.itm(3)} {ACC1:acc#369.itm(4)} {ACC1:acc#369.itm(5)} {ACC1:acc#369.itm(6)} {ACC1:acc#369.itm(7)} {ACC1:acc#369.itm(8)} {ACC1:acc#369.itm(9)} {ACC1:acc#369.itm(10)} -attr xrf 52824 -attr oid 880 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:not#311.itm(0)} -attr vt d
+load net {ACC1:not#311.itm(1)} -attr vt d
+load net {ACC1:not#311.itm(2)} -attr vt d
+load net {ACC1:not#311.itm(3)} -attr vt d
+load net {ACC1:not#311.itm(4)} -attr vt d
+load net {ACC1:not#311.itm(5)} -attr vt d
+load net {ACC1:not#311.itm(6)} -attr vt d
+load net {ACC1:not#311.itm(7)} -attr vt d
+load net {ACC1:not#311.itm(8)} -attr vt d
+load net {ACC1:not#311.itm(9)} -attr vt d
+load netBundle {ACC1:not#311.itm} 10 {ACC1:not#311.itm(0)} {ACC1:not#311.itm(1)} {ACC1:not#311.itm(2)} {ACC1:not#311.itm(3)} {ACC1:not#311.itm(4)} {ACC1:not#311.itm(5)} {ACC1:not#311.itm(6)} {ACC1:not#311.itm(7)} {ACC1:not#311.itm(8)} {ACC1:not#311.itm(9)} -attr xrf 52825 -attr oid 881 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {slc(regs.regs(0).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#5.itm} 10 {slc(regs.regs(0).sva)#5.itm(0)} {slc(regs.regs(0).sva)#5.itm(1)} {slc(regs.regs(0).sva)#5.itm(2)} {slc(regs.regs(0).sva)#5.itm(3)} {slc(regs.regs(0).sva)#5.itm(4)} {slc(regs.regs(0).sva)#5.itm(5)} {slc(regs.regs(0).sva)#5.itm(6)} {slc(regs.regs(0).sva)#5.itm(7)} {slc(regs.regs(0).sva)#5.itm(8)} {slc(regs.regs(0).sva)#5.itm(9)} -attr xrf 52826 -attr oid 882 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {ACC1:acc#360.itm(0)} -attr vt d
+load net {ACC1:acc#360.itm(1)} -attr vt d
+load net {ACC1:acc#360.itm(2)} -attr vt d
+load net {ACC1:acc#360.itm(3)} -attr vt d
+load net {ACC1:acc#360.itm(4)} -attr vt d
+load net {ACC1:acc#360.itm(5)} -attr vt d
+load net {ACC1:acc#360.itm(6)} -attr vt d
+load net {ACC1:acc#360.itm(7)} -attr vt d
+load net {ACC1:acc#360.itm(8)} -attr vt d
+load net {ACC1:acc#360.itm(9)} -attr vt d
+load net {ACC1:acc#360.itm(10)} -attr vt d
+load netBundle {ACC1:acc#360.itm} 11 {ACC1:acc#360.itm(0)} {ACC1:acc#360.itm(1)} {ACC1:acc#360.itm(2)} {ACC1:acc#360.itm(3)} {ACC1:acc#360.itm(4)} {ACC1:acc#360.itm(5)} {ACC1:acc#360.itm(6)} {ACC1:acc#360.itm(7)} {ACC1:acc#360.itm(8)} {ACC1:acc#360.itm(9)} {ACC1:acc#360.itm(10)} -attr xrf 52827 -attr oid 883 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {slc(regs.regs(0).sva#1)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#1)#1.itm} 10 {slc(regs.regs(0).sva#1)#1.itm(0)} {slc(regs.regs(0).sva#1)#1.itm(1)} {slc(regs.regs(0).sva#1)#1.itm(2)} {slc(regs.regs(0).sva#1)#1.itm(3)} {slc(regs.regs(0).sva#1)#1.itm(4)} {slc(regs.regs(0).sva#1)#1.itm(5)} {slc(regs.regs(0).sva#1)#1.itm(6)} {slc(regs.regs(0).sva#1)#1.itm(7)} {slc(regs.regs(0).sva#1)#1.itm(8)} {slc(regs.regs(0).sva#1)#1.itm(9)} -attr xrf 52828 -attr oid 884 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {slc(regs.regs(0).sva#2)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#2)#1.itm} 10 {slc(regs.regs(0).sva#2)#1.itm(0)} {slc(regs.regs(0).sva#2)#1.itm(1)} {slc(regs.regs(0).sva#2)#1.itm(2)} {slc(regs.regs(0).sva#2)#1.itm(3)} {slc(regs.regs(0).sva#2)#1.itm(4)} {slc(regs.regs(0).sva#2)#1.itm(5)} {slc(regs.regs(0).sva#2)#1.itm(6)} {slc(regs.regs(0).sva#2)#1.itm(7)} {slc(regs.regs(0).sva#2)#1.itm(8)} {slc(regs.regs(0).sva#2)#1.itm(9)} -attr xrf 52829 -attr oid 885 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {slc(regs.regs(0).sva#3)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#3)#1.itm} 10 {slc(regs.regs(0).sva#3)#1.itm(0)} {slc(regs.regs(0).sva#3)#1.itm(1)} {slc(regs.regs(0).sva#3)#1.itm(2)} {slc(regs.regs(0).sva#3)#1.itm(3)} {slc(regs.regs(0).sva#3)#1.itm(4)} {slc(regs.regs(0).sva#3)#1.itm(5)} {slc(regs.regs(0).sva#3)#1.itm(6)} {slc(regs.regs(0).sva#3)#1.itm(7)} {slc(regs.regs(0).sva#3)#1.itm(8)} {slc(regs.regs(0).sva#3)#1.itm(9)} -attr xrf 52830 -attr oid 886 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {ACC1-3:exs#1059.itm(0)} -attr vt d
+load net {ACC1-3:exs#1059.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1059.itm} 2 {ACC1-3:exs#1059.itm(0)} {ACC1-3:exs#1059.itm(1)} -attr xrf 52831 -attr oid 887 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1059.itm}
+load net {ACC1-3:exs#1047.itm(0)} -attr vt d
+load net {ACC1-3:exs#1047.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1047.itm} 2 {ACC1-3:exs#1047.itm(0)} {ACC1-3:exs#1047.itm(1)} -attr xrf 52832 -attr oid 888 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1047.itm}
+load net {ACC1:acc#398.itm(0)} -attr vt d
+load net {ACC1:acc#398.itm(1)} -attr vt d
+load net {ACC1:acc#398.itm(2)} -attr vt d
+load net {ACC1:acc#398.itm(3)} -attr vt d
+load net {ACC1:acc#398.itm(4)} -attr vt d
+load net {ACC1:acc#398.itm(5)} -attr vt d
+load net {ACC1:acc#398.itm(6)} -attr vt d
+load net {ACC1:acc#398.itm(7)} -attr vt d
+load net {ACC1:acc#398.itm(8)} -attr vt d
+load net {ACC1:acc#398.itm(9)} -attr vt d
+load net {ACC1:acc#398.itm(10)} -attr vt d
+load netBundle {ACC1:acc#398.itm} 11 {ACC1:acc#398.itm(0)} {ACC1:acc#398.itm(1)} {ACC1:acc#398.itm(2)} {ACC1:acc#398.itm(3)} {ACC1:acc#398.itm(4)} {ACC1:acc#398.itm(5)} {ACC1:acc#398.itm(6)} {ACC1:acc#398.itm(7)} {ACC1:acc#398.itm(8)} {ACC1:acc#398.itm(9)} {ACC1:acc#398.itm(10)} -attr xrf 52833 -attr oid 889 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {regs.operator[]:not#5.itm(0)} -attr vt d
+load net {regs.operator[]:not#5.itm(1)} -attr vt d
+load net {regs.operator[]:not#5.itm(2)} -attr vt d
+load net {regs.operator[]:not#5.itm(3)} -attr vt d
+load net {regs.operator[]:not#5.itm(4)} -attr vt d
+load net {regs.operator[]:not#5.itm(5)} -attr vt d
+load net {regs.operator[]:not#5.itm(6)} -attr vt d
+load net {regs.operator[]:not#5.itm(7)} -attr vt d
+load net {regs.operator[]:not#5.itm(8)} -attr vt d
+load net {regs.operator[]:not#5.itm(9)} -attr vt d
+load netBundle {regs.operator[]:not#5.itm} 10 {regs.operator[]:not#5.itm(0)} {regs.operator[]:not#5.itm(1)} {regs.operator[]:not#5.itm(2)} {regs.operator[]:not#5.itm(3)} {regs.operator[]:not#5.itm(4)} {regs.operator[]:not#5.itm(5)} {regs.operator[]:not#5.itm(6)} {regs.operator[]:not#5.itm(7)} {regs.operator[]:not#5.itm(8)} {regs.operator[]:not#5.itm(9)} -attr xrf 52834 -attr oid 890 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(0)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(1)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(2)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(3)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(4)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(5)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(6)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(7)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(8)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(9)} -attr vt d
+load netBundle {regs.operator[]#1:not#5.itm} 10 {regs.operator[]#1:not#5.itm(0)} {regs.operator[]#1:not#5.itm(1)} {regs.operator[]#1:not#5.itm(2)} {regs.operator[]#1:not#5.itm(3)} {regs.operator[]#1:not#5.itm(4)} {regs.operator[]#1:not#5.itm(5)} {regs.operator[]#1:not#5.itm(6)} {regs.operator[]#1:not#5.itm(7)} {regs.operator[]#1:not#5.itm(8)} {regs.operator[]#1:not#5.itm(9)} -attr xrf 52835 -attr oid 891 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {ACC1:acc#397.itm(0)} -attr vt d
+load net {ACC1:acc#397.itm(1)} -attr vt d
+load net {ACC1:acc#397.itm(2)} -attr vt d
+load net {ACC1:acc#397.itm(3)} -attr vt d
+load net {ACC1:acc#397.itm(4)} -attr vt d
+load net {ACC1:acc#397.itm(5)} -attr vt d
+load net {ACC1:acc#397.itm(6)} -attr vt d
+load net {ACC1:acc#397.itm(7)} -attr vt d
+load net {ACC1:acc#397.itm(8)} -attr vt d
+load net {ACC1:acc#397.itm(9)} -attr vt d
+load net {ACC1:acc#397.itm(10)} -attr vt d
+load netBundle {ACC1:acc#397.itm} 11 {ACC1:acc#397.itm(0)} {ACC1:acc#397.itm(1)} {ACC1:acc#397.itm(2)} {ACC1:acc#397.itm(3)} {ACC1:acc#397.itm(4)} {ACC1:acc#397.itm(5)} {ACC1:acc#397.itm(6)} {ACC1:acc#397.itm(7)} {ACC1:acc#397.itm(8)} {ACC1:acc#397.itm(9)} {ACC1:acc#397.itm(10)} -attr xrf 52836 -attr oid 892 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {regs.operator[]#2:not#5.itm(0)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(1)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(2)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(3)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(4)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(5)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(6)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(7)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(8)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(9)} -attr vt d
+load netBundle {regs.operator[]#2:not#5.itm} 10 {regs.operator[]#2:not#5.itm(0)} {regs.operator[]#2:not#5.itm(1)} {regs.operator[]#2:not#5.itm(2)} {regs.operator[]#2:not#5.itm(3)} {regs.operator[]#2:not#5.itm(4)} {regs.operator[]#2:not#5.itm(5)} {regs.operator[]#2:not#5.itm(6)} {regs.operator[]#2:not#5.itm(7)} {regs.operator[]#2:not#5.itm(8)} {regs.operator[]#2:not#5.itm(9)} -attr xrf 52837 -attr oid 893 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {ACC1-3:exs#1056.itm(0)} -attr vt d
+load net {ACC1-3:exs#1056.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1056.itm} 2 {ACC1-3:exs#1056.itm(0)} {ACC1-3:exs#1056.itm(1)} -attr xrf 52838 -attr oid 894 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1056.itm}
+load net {ACC1-3:exs#1043.itm(0)} -attr vt d
+load net {ACC1-3:exs#1043.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1043.itm} 2 {ACC1-3:exs#1043.itm(0)} {ACC1-3:exs#1043.itm(1)} -attr xrf 52839 -attr oid 895 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1043.itm}
+load net {ACC1-3:exs#963.itm(0)} -attr vt d
+load net {ACC1-3:exs#963.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#963.itm} 2 {ACC1-3:exs#963.itm(0)} {ACC1-3:exs#963.itm(1)} -attr xrf 52840 -attr oid 896 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#963.itm}
+load net {ACC1-3:exs#1055.itm(0)} -attr vt d
+load net {ACC1-3:exs#1055.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1055.itm} 2 {ACC1-3:exs#1055.itm(0)} {ACC1-3:exs#1055.itm(1)} -attr xrf 52841 -attr oid 897 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1055.itm}
+load net {ACC1-2:exs#1059.itm(0)} -attr vt d
+load net {ACC1-2:exs#1059.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1059.itm} 2 {ACC1-2:exs#1059.itm(0)} {ACC1-2:exs#1059.itm(1)} -attr xrf 52842 -attr oid 898 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1059.itm}
+load net {ACC1-2:exs#1047.itm(0)} -attr vt d
+load net {ACC1-2:exs#1047.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1047.itm} 2 {ACC1-2:exs#1047.itm(0)} {ACC1-2:exs#1047.itm(1)} -attr xrf 52843 -attr oid 899 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1047.itm}
+load net {ACC1:acc#379.itm(0)} -attr vt d
+load net {ACC1:acc#379.itm(1)} -attr vt d
+load net {ACC1:acc#379.itm(2)} -attr vt d
+load net {ACC1:acc#379.itm(3)} -attr vt d
+load net {ACC1:acc#379.itm(4)} -attr vt d
+load net {ACC1:acc#379.itm(5)} -attr vt d
+load net {ACC1:acc#379.itm(6)} -attr vt d
+load net {ACC1:acc#379.itm(7)} -attr vt d
+load net {ACC1:acc#379.itm(8)} -attr vt d
+load net {ACC1:acc#379.itm(9)} -attr vt d
+load net {ACC1:acc#379.itm(10)} -attr vt d
+load netBundle {ACC1:acc#379.itm} 11 {ACC1:acc#379.itm(0)} {ACC1:acc#379.itm(1)} {ACC1:acc#379.itm(2)} {ACC1:acc#379.itm(3)} {ACC1:acc#379.itm(4)} {ACC1:acc#379.itm(5)} {ACC1:acc#379.itm(6)} {ACC1:acc#379.itm(7)} {ACC1:acc#379.itm(8)} {ACC1:acc#379.itm(9)} {ACC1:acc#379.itm(10)} -attr xrf 52844 -attr oid 900 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {slc(regs.regs(0).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva).itm} 10 {slc(regs.regs(0).sva).itm(0)} {slc(regs.regs(0).sva).itm(1)} {slc(regs.regs(0).sva).itm(2)} {slc(regs.regs(0).sva).itm(3)} {slc(regs.regs(0).sva).itm(4)} {slc(regs.regs(0).sva).itm(5)} {slc(regs.regs(0).sva).itm(6)} {slc(regs.regs(0).sva).itm(7)} {slc(regs.regs(0).sva).itm(8)} {slc(regs.regs(0).sva).itm(9)} -attr xrf 52845 -attr oid 901 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {slc(regs.regs(0).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#1.itm} 10 {slc(regs.regs(0).sva)#1.itm(0)} {slc(regs.regs(0).sva)#1.itm(1)} {slc(regs.regs(0).sva)#1.itm(2)} {slc(regs.regs(0).sva)#1.itm(3)} {slc(regs.regs(0).sva)#1.itm(4)} {slc(regs.regs(0).sva)#1.itm(5)} {slc(regs.regs(0).sva)#1.itm(6)} {slc(regs.regs(0).sva)#1.itm(7)} {slc(regs.regs(0).sva)#1.itm(8)} {slc(regs.regs(0).sva)#1.itm(9)} -attr xrf 52846 -attr oid 902 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {slc(regs.regs(0).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#2.itm} 10 {slc(regs.regs(0).sva)#2.itm(0)} {slc(regs.regs(0).sva)#2.itm(1)} {slc(regs.regs(0).sva)#2.itm(2)} {slc(regs.regs(0).sva)#2.itm(3)} {slc(regs.regs(0).sva)#2.itm(4)} {slc(regs.regs(0).sva)#2.itm(5)} {slc(regs.regs(0).sva)#2.itm(6)} {slc(regs.regs(0).sva)#2.itm(7)} {slc(regs.regs(0).sva)#2.itm(8)} {slc(regs.regs(0).sva)#2.itm(9)} -attr xrf 52847 -attr oid 903 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {ACC1:acc#388.itm(0)} -attr vt d
+load net {ACC1:acc#388.itm(1)} -attr vt d
+load net {ACC1:acc#388.itm(2)} -attr vt d
+load net {ACC1:acc#388.itm(3)} -attr vt d
+load net {ACC1:acc#388.itm(4)} -attr vt d
+load net {ACC1:acc#388.itm(5)} -attr vt d
+load net {ACC1:acc#388.itm(6)} -attr vt d
+load net {ACC1:acc#388.itm(7)} -attr vt d
+load net {ACC1:acc#388.itm(8)} -attr vt d
+load net {ACC1:acc#388.itm(9)} -attr vt d
+load net {ACC1:acc#388.itm(10)} -attr vt d
+load netBundle {ACC1:acc#388.itm} 11 {ACC1:acc#388.itm(0)} {ACC1:acc#388.itm(1)} {ACC1:acc#388.itm(2)} {ACC1:acc#388.itm(3)} {ACC1:acc#388.itm(4)} {ACC1:acc#388.itm(5)} {ACC1:acc#388.itm(6)} {ACC1:acc#388.itm(7)} {ACC1:acc#388.itm(8)} {ACC1:acc#388.itm(9)} {ACC1:acc#388.itm(10)} -attr xrf 52848 -attr oid 904 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#338.itm(0)} -attr vt d
+load net {ACC1:acc#338.itm(1)} -attr vt d
+load net {ACC1:acc#338.itm(2)} -attr vt d
+load net {ACC1:acc#338.itm(3)} -attr vt d
+load netBundle {ACC1:acc#338.itm} 4 {ACC1:acc#338.itm(0)} {ACC1:acc#338.itm(1)} {ACC1:acc#338.itm(2)} {ACC1:acc#338.itm(3)} -attr xrf 52849 -attr oid 905 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {conc#1004.itm(0)} -attr vt d
+load net {conc#1004.itm(1)} -attr vt d
+load net {conc#1004.itm(2)} -attr vt d
+load netBundle {conc#1004.itm} 3 {conc#1004.itm(0)} {conc#1004.itm(1)} {conc#1004.itm(2)} -attr xrf 52850 -attr oid 906 -attr vt d -attr @path {/sobel/sobel:core/conc#1004.itm}
+load net {ACC1-1:not#293.itm(0)} -attr vt d
+load net {ACC1-1:not#293.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#293.itm} 2 {ACC1-1:not#293.itm(0)} {ACC1-1:not#293.itm(1)} -attr xrf 52851 -attr oid 907 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#293.itm}
+load net {slc(ACC1:acc#220.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#220.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#220.psp#1.sva).itm} 2 {slc(ACC1:acc#220.psp#1.sva).itm(0)} {slc(ACC1:acc#220.psp#1.sva).itm(1)} -attr xrf 52852 -attr oid 908 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva).itm}
+load net {conc#1005.itm(0)} -attr vt d
+load net {conc#1005.itm(1)} -attr vt d
+load netBundle {conc#1005.itm} 2 {conc#1005.itm(0)} {conc#1005.itm(1)} -attr xrf 52853 -attr oid 909 -attr vt d -attr @path {/sobel/sobel:core/conc#1005.itm}
+load net {ACC1:slc#17.itm(0)} -attr vt d
+load net {ACC1:slc#17.itm(1)} -attr vt d
+load net {ACC1:slc#17.itm(2)} -attr vt d
+load net {ACC1:slc#17.itm(3)} -attr vt d
+load netBundle {ACC1:slc#17.itm} 4 {ACC1:slc#17.itm(0)} {ACC1:slc#17.itm(1)} {ACC1:slc#17.itm(2)} {ACC1:slc#17.itm(3)} -attr xrf 52854 -attr oid 910 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#17.itm}
+load net {ACC1:acc#336.itm(0)} -attr vt d
+load net {ACC1:acc#336.itm(1)} -attr vt d
+load net {ACC1:acc#336.itm(2)} -attr vt d
+load net {ACC1:acc#336.itm(3)} -attr vt d
+load net {ACC1:acc#336.itm(4)} -attr vt d
+load netBundle {ACC1:acc#336.itm} 5 {ACC1:acc#336.itm(0)} {ACC1:acc#336.itm(1)} {ACC1:acc#336.itm(2)} {ACC1:acc#336.itm(3)} {ACC1:acc#336.itm(4)} -attr xrf 52855 -attr oid 911 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {conc#1006.itm(0)} -attr vt d
+load net {conc#1006.itm(1)} -attr vt d
+load net {conc#1006.itm(2)} -attr vt d
+load net {conc#1006.itm(3)} -attr vt d
+load netBundle {conc#1006.itm} 4 {conc#1006.itm(0)} {conc#1006.itm(1)} {conc#1006.itm(2)} {conc#1006.itm(3)} -attr xrf 52856 -attr oid 912 -attr vt d -attr @path {/sobel/sobel:core/conc#1006.itm}
+load net {ACC1:slc#15.itm(0)} -attr vt d
+load net {ACC1:slc#15.itm(1)} -attr vt d
+load net {ACC1:slc#15.itm(2)} -attr vt d
+load netBundle {ACC1:slc#15.itm} 3 {ACC1:slc#15.itm(0)} {ACC1:slc#15.itm(1)} {ACC1:slc#15.itm(2)} -attr xrf 52857 -attr oid 913 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#15.itm}
+load net {ACC1:acc#334.itm(0)} -attr vt d
+load net {ACC1:acc#334.itm(1)} -attr vt d
+load net {ACC1:acc#334.itm(2)} -attr vt d
+load net {ACC1:acc#334.itm(3)} -attr vt d
+load netBundle {ACC1:acc#334.itm} 4 {ACC1:acc#334.itm(0)} {ACC1:acc#334.itm(1)} {ACC1:acc#334.itm(2)} {ACC1:acc#334.itm(3)} -attr xrf 52858 -attr oid 914 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {conc#1007.itm(0)} -attr vt d
+load net {conc#1007.itm(1)} -attr vt d
+load netBundle {conc#1007.itm} 2 {conc#1007.itm(0)} {conc#1007.itm(1)} -attr xrf 52859 -attr oid 915 -attr vt d -attr @path {/sobel/sobel:core/conc#1007.itm}
+load net {ACC1:conc#1133.itm(0)} -attr vt d
+load net {ACC1:conc#1133.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1133.itm} 2 {ACC1:conc#1133.itm(0)} {ACC1:conc#1133.itm(1)} -attr xrf 52860 -attr oid 916 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1133.itm}
+load net {conc#1008.itm(0)} -attr vt d
+load net {conc#1008.itm(1)} -attr vt d
+load net {conc#1008.itm(2)} -attr vt d
+load net {conc#1008.itm(3)} -attr vt d
+load netBundle {conc#1008.itm} 4 {conc#1008.itm(0)} {conc#1008.itm(1)} {conc#1008.itm(2)} {conc#1008.itm(3)} -attr xrf 52861 -attr oid 917 -attr vt d -attr @path {/sobel/sobel:core/conc#1008.itm}
+load net {ACC1:slc#16.itm(0)} -attr vt d
+load net {ACC1:slc#16.itm(1)} -attr vt d
+load net {ACC1:slc#16.itm(2)} -attr vt d
+load netBundle {ACC1:slc#16.itm} 3 {ACC1:slc#16.itm(0)} {ACC1:slc#16.itm(1)} {ACC1:slc#16.itm(2)} -attr xrf 52862 -attr oid 918 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#16.itm}
+load net {ACC1:acc#335.itm(0)} -attr vt d
+load net {ACC1:acc#335.itm(1)} -attr vt d
+load net {ACC1:acc#335.itm(2)} -attr vt d
+load net {ACC1:acc#335.itm(3)} -attr vt d
+load netBundle {ACC1:acc#335.itm} 4 {ACC1:acc#335.itm(0)} {ACC1:acc#335.itm(1)} {ACC1:acc#335.itm(2)} {ACC1:acc#335.itm(3)} -attr xrf 52863 -attr oid 919 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {conc#1009.itm(0)} -attr vt d
+load net {conc#1009.itm(1)} -attr vt d
+load net {conc#1009.itm(2)} -attr vt d
+load netBundle {conc#1009.itm} 3 {conc#1009.itm(0)} {conc#1009.itm(1)} {conc#1009.itm(2)} -attr xrf 52864 -attr oid 920 -attr vt d -attr @path {/sobel/sobel:core/conc#1009.itm}
+load net {ACC1:slc#14.itm(0)} -attr vt d
+load net {ACC1:slc#14.itm(1)} -attr vt d
+load netBundle {ACC1:slc#14.itm} 2 {ACC1:slc#14.itm(0)} {ACC1:slc#14.itm(1)} -attr xrf 52865 -attr oid 921 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#14.itm}
+load net {ACC1:acc#333.itm(0)} -attr vt d
+load net {ACC1:acc#333.itm(1)} -attr vt d
+load net {ACC1:acc#333.itm(2)} -attr vt d
+load netBundle {ACC1:acc#333.itm} 3 {ACC1:acc#333.itm(0)} {ACC1:acc#333.itm(1)} {ACC1:acc#333.itm(2)} -attr xrf 52866 -attr oid 922 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {conc#1010.itm(0)} -attr vt d
+load net {conc#1010.itm(1)} -attr vt d
+load netBundle {conc#1010.itm} 2 {conc#1010.itm(0)} {conc#1010.itm(1)} -attr xrf 52867 -attr oid 923 -attr vt d -attr @path {/sobel/sobel:core/conc#1010.itm}
+load net {ACC1:conc#1131.itm(0)} -attr vt d
+load net {ACC1:conc#1131.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1131.itm} 2 {ACC1:conc#1131.itm(0)} {ACC1:conc#1131.itm(1)} -attr xrf 52868 -attr oid 924 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1131.itm}
+load net {ACC1:conc#1135.itm(0)} -attr vt d
+load net {ACC1:conc#1135.itm(1)} -attr vt d
+load net {ACC1:conc#1135.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1135.itm} 3 {ACC1:conc#1135.itm(0)} {ACC1:conc#1135.itm(1)} {ACC1:conc#1135.itm(2)} -attr xrf 52869 -attr oid 925 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1135.itm}
+load net {ACC1:slc#13.itm(0)} -attr vt d
+load net {ACC1:slc#13.itm(1)} -attr vt d
+load netBundle {ACC1:slc#13.itm} 2 {ACC1:slc#13.itm(0)} {ACC1:slc#13.itm(1)} -attr xrf 52870 -attr oid 926 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#13.itm}
+load net {ACC1:acc#332.itm(0)} -attr vt d
+load net {ACC1:acc#332.itm(1)} -attr vt d
+load net {ACC1:acc#332.itm(2)} -attr vt d
+load netBundle {ACC1:acc#332.itm} 3 {ACC1:acc#332.itm(0)} {ACC1:acc#332.itm(1)} {ACC1:acc#332.itm(2)} -attr xrf 52871 -attr oid 927 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {conc#1011.itm(0)} -attr vt d
+load net {conc#1011.itm(1)} -attr vt d
+load netBundle {conc#1011.itm} 2 {conc#1011.itm(0)} {conc#1011.itm(1)} -attr xrf 52872 -attr oid 928 -attr vt d -attr @path {/sobel/sobel:core/conc#1011.itm}
+load net {ACC1:conc#1129.itm(0)} -attr vt d
+load net {ACC1:conc#1129.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1129.itm} 2 {ACC1:conc#1129.itm(0)} {ACC1:conc#1129.itm(1)} -attr xrf 52873 -attr oid 929 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1129.itm}
+load net {ACC1:acc#331.itm(0)} -attr vt d
+load net {ACC1:acc#331.itm(1)} -attr vt d
+load net {ACC1:acc#331.itm(2)} -attr vt d
+load net {ACC1:acc#331.itm(3)} -attr vt d
+load net {ACC1:acc#331.itm(4)} -attr vt d
+load net {ACC1:acc#331.itm(5)} -attr vt d
+load net {ACC1:acc#331.itm(6)} -attr vt d
+load net {ACC1:acc#331.itm(7)} -attr vt d
+load net {ACC1:acc#331.itm(8)} -attr vt d
+load net {ACC1:acc#331.itm(9)} -attr vt d
+load net {ACC1:acc#331.itm(10)} -attr vt d
+load netBundle {ACC1:acc#331.itm} 11 {ACC1:acc#331.itm(0)} {ACC1:acc#331.itm(1)} {ACC1:acc#331.itm(2)} {ACC1:acc#331.itm(3)} {ACC1:acc#331.itm(4)} {ACC1:acc#331.itm(5)} {ACC1:acc#331.itm(6)} {ACC1:acc#331.itm(7)} {ACC1:acc#331.itm(8)} {ACC1:acc#331.itm(9)} {ACC1:acc#331.itm(10)} -attr xrf 52874 -attr oid 930 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {regs.operator[]:not.itm(0)} -attr vt d
+load net {regs.operator[]:not.itm(1)} -attr vt d
+load net {regs.operator[]:not.itm(2)} -attr vt d
+load net {regs.operator[]:not.itm(3)} -attr vt d
+load net {regs.operator[]:not.itm(4)} -attr vt d
+load net {regs.operator[]:not.itm(5)} -attr vt d
+load net {regs.operator[]:not.itm(6)} -attr vt d
+load net {regs.operator[]:not.itm(7)} -attr vt d
+load net {regs.operator[]:not.itm(8)} -attr vt d
+load net {regs.operator[]:not.itm(9)} -attr vt d
+load netBundle {regs.operator[]:not.itm} 10 {regs.operator[]:not.itm(0)} {regs.operator[]:not.itm(1)} {regs.operator[]:not.itm(2)} {regs.operator[]:not.itm(3)} {regs.operator[]:not.itm(4)} {regs.operator[]:not.itm(5)} {regs.operator[]:not.itm(6)} {regs.operator[]:not.itm(7)} {regs.operator[]:not.itm(8)} {regs.operator[]:not.itm(9)} -attr xrf 52875 -attr oid 931 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {slc(regs.regs(0).sva#7).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#7).itm} 10 {slc(regs.regs(0).sva#7).itm(0)} {slc(regs.regs(0).sva#7).itm(1)} {slc(regs.regs(0).sva#7).itm(2)} {slc(regs.regs(0).sva#7).itm(3)} {slc(regs.regs(0).sva#7).itm(4)} {slc(regs.regs(0).sva#7).itm(5)} {slc(regs.regs(0).sva#7).itm(6)} {slc(regs.regs(0).sva#7).itm(7)} {slc(regs.regs(0).sva#7).itm(8)} {slc(regs.regs(0).sva#7).itm(9)} -attr xrf 52876 -attr oid 932 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {regs.operator[]#1:not.itm(0)} -attr vt d
+load net {regs.operator[]#1:not.itm(1)} -attr vt d
+load net {regs.operator[]#1:not.itm(2)} -attr vt d
+load net {regs.operator[]#1:not.itm(3)} -attr vt d
+load net {regs.operator[]#1:not.itm(4)} -attr vt d
+load net {regs.operator[]#1:not.itm(5)} -attr vt d
+load net {regs.operator[]#1:not.itm(6)} -attr vt d
+load net {regs.operator[]#1:not.itm(7)} -attr vt d
+load net {regs.operator[]#1:not.itm(8)} -attr vt d
+load net {regs.operator[]#1:not.itm(9)} -attr vt d
+load netBundle {regs.operator[]#1:not.itm} 10 {regs.operator[]#1:not.itm(0)} {regs.operator[]#1:not.itm(1)} {regs.operator[]#1:not.itm(2)} {regs.operator[]#1:not.itm(3)} {regs.operator[]#1:not.itm(4)} {regs.operator[]#1:not.itm(5)} {regs.operator[]#1:not.itm(6)} {regs.operator[]#1:not.itm(7)} {regs.operator[]#1:not.itm(8)} {regs.operator[]#1:not.itm(9)} -attr xrf 52877 -attr oid 933 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {slc(regs.regs(0).sva#8).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#8).itm} 10 {slc(regs.regs(0).sva#8).itm(0)} {slc(regs.regs(0).sva#8).itm(1)} {slc(regs.regs(0).sva#8).itm(2)} {slc(regs.regs(0).sva#8).itm(3)} {slc(regs.regs(0).sva#8).itm(4)} {slc(regs.regs(0).sva#8).itm(5)} {slc(regs.regs(0).sva#8).itm(6)} {slc(regs.regs(0).sva#8).itm(7)} {slc(regs.regs(0).sva#8).itm(8)} {slc(regs.regs(0).sva#8).itm(9)} -attr xrf 52878 -attr oid 934 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {ACC1:acc#330.itm(0)} -attr vt d
+load net {ACC1:acc#330.itm(1)} -attr vt d
+load net {ACC1:acc#330.itm(2)} -attr vt d
+load net {ACC1:acc#330.itm(3)} -attr vt d
+load net {ACC1:acc#330.itm(4)} -attr vt d
+load net {ACC1:acc#330.itm(5)} -attr vt d
+load net {ACC1:acc#330.itm(6)} -attr vt d
+load net {ACC1:acc#330.itm(7)} -attr vt d
+load net {ACC1:acc#330.itm(8)} -attr vt d
+load net {ACC1:acc#330.itm(9)} -attr vt d
+load net {ACC1:acc#330.itm(10)} -attr vt d
+load netBundle {ACC1:acc#330.itm} 11 {ACC1:acc#330.itm(0)} {ACC1:acc#330.itm(1)} {ACC1:acc#330.itm(2)} {ACC1:acc#330.itm(3)} {ACC1:acc#330.itm(4)} {ACC1:acc#330.itm(5)} {ACC1:acc#330.itm(6)} {ACC1:acc#330.itm(7)} {ACC1:acc#330.itm(8)} {ACC1:acc#330.itm(9)} {ACC1:acc#330.itm(10)} -attr xrf 52879 -attr oid 935 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {regs.operator[]#2:not.itm(0)} -attr vt d
+load net {regs.operator[]#2:not.itm(1)} -attr vt d
+load net {regs.operator[]#2:not.itm(2)} -attr vt d
+load net {regs.operator[]#2:not.itm(3)} -attr vt d
+load net {regs.operator[]#2:not.itm(4)} -attr vt d
+load net {regs.operator[]#2:not.itm(5)} -attr vt d
+load net {regs.operator[]#2:not.itm(6)} -attr vt d
+load net {regs.operator[]#2:not.itm(7)} -attr vt d
+load net {regs.operator[]#2:not.itm(8)} -attr vt d
+load net {regs.operator[]#2:not.itm(9)} -attr vt d
+load netBundle {regs.operator[]#2:not.itm} 10 {regs.operator[]#2:not.itm(0)} {regs.operator[]#2:not.itm(1)} {regs.operator[]#2:not.itm(2)} {regs.operator[]#2:not.itm(3)} {regs.operator[]#2:not.itm(4)} {regs.operator[]#2:not.itm(5)} {regs.operator[]#2:not.itm(6)} {regs.operator[]#2:not.itm(7)} {regs.operator[]#2:not.itm(8)} {regs.operator[]#2:not.itm(9)} -attr xrf 52880 -attr oid 936 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {slc(regs.regs(0).sva#9).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#9).itm} 10 {slc(regs.regs(0).sva#9).itm(0)} {slc(regs.regs(0).sva#9).itm(1)} {slc(regs.regs(0).sva#9).itm(2)} {slc(regs.regs(0).sva#9).itm(3)} {slc(regs.regs(0).sva#9).itm(4)} {slc(regs.regs(0).sva#9).itm(5)} {slc(regs.regs(0).sva#9).itm(6)} {slc(regs.regs(0).sva#9).itm(7)} {slc(regs.regs(0).sva#9).itm(8)} {slc(regs.regs(0).sva#9).itm(9)} -attr xrf 52881 -attr oid 937 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {ACC1:acc#341.itm(0)} -attr vt d
+load net {ACC1:acc#341.itm(1)} -attr vt d
+load net {ACC1:acc#341.itm(2)} -attr vt d
+load net {ACC1:acc#341.itm(3)} -attr vt d
+load net {ACC1:acc#341.itm(4)} -attr vt d
+load net {ACC1:acc#341.itm(5)} -attr vt d
+load net {ACC1:acc#341.itm(6)} -attr vt d
+load net {ACC1:acc#341.itm(7)} -attr vt d
+load net {ACC1:acc#341.itm(8)} -attr vt d
+load net {ACC1:acc#341.itm(9)} -attr vt d
+load net {ACC1:acc#341.itm(10)} -attr vt d
+load netBundle {ACC1:acc#341.itm} 11 {ACC1:acc#341.itm(0)} {ACC1:acc#341.itm(1)} {ACC1:acc#341.itm(2)} {ACC1:acc#341.itm(3)} {ACC1:acc#341.itm(4)} {ACC1:acc#341.itm(5)} {ACC1:acc#341.itm(6)} {ACC1:acc#341.itm(7)} {ACC1:acc#341.itm(8)} {ACC1:acc#341.itm(9)} {ACC1:acc#341.itm(10)} -attr xrf 52882 -attr oid 938 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:not.itm(0)} -attr vt d
+load net {ACC1:not.itm(1)} -attr vt d
+load net {ACC1:not.itm(2)} -attr vt d
+load net {ACC1:not.itm(3)} -attr vt d
+load net {ACC1:not.itm(4)} -attr vt d
+load net {ACC1:not.itm(5)} -attr vt d
+load net {ACC1:not.itm(6)} -attr vt d
+load net {ACC1:not.itm(7)} -attr vt d
+load net {ACC1:not.itm(8)} -attr vt d
+load net {ACC1:not.itm(9)} -attr vt d
+load netBundle {ACC1:not.itm} 10 {ACC1:not.itm(0)} {ACC1:not.itm(1)} {ACC1:not.itm(2)} {ACC1:not.itm(3)} {ACC1:not.itm(4)} {ACC1:not.itm(5)} {ACC1:not.itm(6)} {ACC1:not.itm(7)} {ACC1:not.itm(8)} {ACC1:not.itm(9)} -attr xrf 52883 -attr oid 939 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {slc(regs.regs(0).sva#4).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#4).itm} 10 {slc(regs.regs(0).sva#4).itm(0)} {slc(regs.regs(0).sva#4).itm(1)} {slc(regs.regs(0).sva#4).itm(2)} {slc(regs.regs(0).sva#4).itm(3)} {slc(regs.regs(0).sva#4).itm(4)} {slc(regs.regs(0).sva#4).itm(5)} {slc(regs.regs(0).sva#4).itm(6)} {slc(regs.regs(0).sva#4).itm(7)} {slc(regs.regs(0).sva#4).itm(8)} {slc(regs.regs(0).sva#4).itm(9)} -attr xrf 52884 -attr oid 940 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:not#307.itm(0)} -attr vt d
+load net {ACC1:not#307.itm(1)} -attr vt d
+load net {ACC1:not#307.itm(2)} -attr vt d
+load net {ACC1:not#307.itm(3)} -attr vt d
+load net {ACC1:not#307.itm(4)} -attr vt d
+load net {ACC1:not#307.itm(5)} -attr vt d
+load net {ACC1:not#307.itm(6)} -attr vt d
+load net {ACC1:not#307.itm(7)} -attr vt d
+load net {ACC1:not#307.itm(8)} -attr vt d
+load net {ACC1:not#307.itm(9)} -attr vt d
+load netBundle {ACC1:not#307.itm} 10 {ACC1:not#307.itm(0)} {ACC1:not#307.itm(1)} {ACC1:not#307.itm(2)} {ACC1:not#307.itm(3)} {ACC1:not#307.itm(4)} {ACC1:not#307.itm(5)} {ACC1:not#307.itm(6)} {ACC1:not#307.itm(7)} {ACC1:not#307.itm(8)} {ACC1:not#307.itm(9)} -attr xrf 52885 -attr oid 941 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {slc(regs.regs(0).sva#5).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#5).itm} 10 {slc(regs.regs(0).sva#5).itm(0)} {slc(regs.regs(0).sva#5).itm(1)} {slc(regs.regs(0).sva#5).itm(2)} {slc(regs.regs(0).sva#5).itm(3)} {slc(regs.regs(0).sva#5).itm(4)} {slc(regs.regs(0).sva#5).itm(5)} {slc(regs.regs(0).sva#5).itm(6)} {slc(regs.regs(0).sva#5).itm(7)} {slc(regs.regs(0).sva#5).itm(8)} {slc(regs.regs(0).sva#5).itm(9)} -attr xrf 52886 -attr oid 942 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {ACC1:acc#340.itm(0)} -attr vt d
+load net {ACC1:acc#340.itm(1)} -attr vt d
+load net {ACC1:acc#340.itm(2)} -attr vt d
+load net {ACC1:acc#340.itm(3)} -attr vt d
+load net {ACC1:acc#340.itm(4)} -attr vt d
+load net {ACC1:acc#340.itm(5)} -attr vt d
+load net {ACC1:acc#340.itm(6)} -attr vt d
+load net {ACC1:acc#340.itm(7)} -attr vt d
+load net {ACC1:acc#340.itm(8)} -attr vt d
+load net {ACC1:acc#340.itm(9)} -attr vt d
+load net {ACC1:acc#340.itm(10)} -attr vt d
+load netBundle {ACC1:acc#340.itm} 11 {ACC1:acc#340.itm(0)} {ACC1:acc#340.itm(1)} {ACC1:acc#340.itm(2)} {ACC1:acc#340.itm(3)} {ACC1:acc#340.itm(4)} {ACC1:acc#340.itm(5)} {ACC1:acc#340.itm(6)} {ACC1:acc#340.itm(7)} {ACC1:acc#340.itm(8)} {ACC1:acc#340.itm(9)} {ACC1:acc#340.itm(10)} -attr xrf 52887 -attr oid 943 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:not#308.itm(0)} -attr vt d
+load net {ACC1:not#308.itm(1)} -attr vt d
+load net {ACC1:not#308.itm(2)} -attr vt d
+load net {ACC1:not#308.itm(3)} -attr vt d
+load net {ACC1:not#308.itm(4)} -attr vt d
+load net {ACC1:not#308.itm(5)} -attr vt d
+load net {ACC1:not#308.itm(6)} -attr vt d
+load net {ACC1:not#308.itm(7)} -attr vt d
+load net {ACC1:not#308.itm(8)} -attr vt d
+load net {ACC1:not#308.itm(9)} -attr vt d
+load netBundle {ACC1:not#308.itm} 10 {ACC1:not#308.itm(0)} {ACC1:not#308.itm(1)} {ACC1:not#308.itm(2)} {ACC1:not#308.itm(3)} {ACC1:not#308.itm(4)} {ACC1:not#308.itm(5)} {ACC1:not#308.itm(6)} {ACC1:not#308.itm(7)} {ACC1:not#308.itm(8)} {ACC1:not#308.itm(9)} -attr xrf 52888 -attr oid 944 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {slc(regs.regs(0).sva#6).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#6).itm} 10 {slc(regs.regs(0).sva#6).itm(0)} {slc(regs.regs(0).sva#6).itm(1)} {slc(regs.regs(0).sva#6).itm(2)} {slc(regs.regs(0).sva#6).itm(3)} {slc(regs.regs(0).sva#6).itm(4)} {slc(regs.regs(0).sva#6).itm(5)} {slc(regs.regs(0).sva#6).itm(6)} {slc(regs.regs(0).sva#6).itm(7)} {slc(regs.regs(0).sva#6).itm(8)} {slc(regs.regs(0).sva#6).itm(9)} -attr xrf 52889 -attr oid 945 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:acc#406.itm(0)} -attr vt d
+load net {ACC1:acc#406.itm(1)} -attr vt d
+load net {ACC1:acc#406.itm(2)} -attr vt d
+load netBundle {ACC1:acc#406.itm} 3 {ACC1:acc#406.itm(0)} {ACC1:acc#406.itm(1)} {ACC1:acc#406.itm(2)} -attr xrf 52890 -attr oid 946 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#406.itm}
+load net {conc#1012.itm(0)} -attr vt d
+load net {conc#1012.itm(1)} -attr vt d
+load net {conc#1012.itm(2)} -attr vt d
+load netBundle {conc#1012.itm} 3 {conc#1012.itm(0)} {conc#1012.itm(1)} {conc#1012.itm(2)} -attr xrf 52891 -attr oid 947 -attr vt d -attr @path {/sobel/sobel:core/conc#1012.itm}
+load net {ACC1:conc#1270.itm(0)} -attr vt d
+load net {ACC1:conc#1270.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1270.itm} 2 {ACC1:conc#1270.itm(0)} {ACC1:conc#1270.itm(1)} -attr xrf 52892 -attr oid 948 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1270.itm}
+load net {ACC1:acc#368.itm(0)} -attr vt d
+load net {ACC1:acc#368.itm(1)} -attr vt d
+load net {ACC1:acc#368.itm(2)} -attr vt d
+load netBundle {ACC1:acc#368.itm} 3 {ACC1:acc#368.itm(0)} {ACC1:acc#368.itm(1)} {ACC1:acc#368.itm(2)} -attr xrf 52893 -attr oid 949 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#368.itm}
+load net {conc#1013.itm(0)} -attr vt d
+load net {conc#1013.itm(1)} -attr vt d
+load net {conc#1013.itm(2)} -attr vt d
+load netBundle {conc#1013.itm} 3 {conc#1013.itm(0)} {conc#1013.itm(1)} {conc#1013.itm(2)} -attr xrf 52894 -attr oid 950 -attr vt d -attr @path {/sobel/sobel:core/conc#1013.itm}
+load net {ACC1:conc#1198.itm(0)} -attr vt d
+load net {ACC1:conc#1198.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1198.itm} 2 {ACC1:conc#1198.itm(0)} {ACC1:conc#1198.itm(1)} -attr xrf 52895 -attr oid 951 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1198.itm}
+load net {ACC1:acc#367.itm(0)} -attr vt d
+load net {ACC1:acc#367.itm(1)} -attr vt d
+load net {ACC1:acc#367.itm(2)} -attr vt d
+load net {ACC1:acc#367.itm(3)} -attr vt d
+load netBundle {ACC1:acc#367.itm} 4 {ACC1:acc#367.itm(0)} {ACC1:acc#367.itm(1)} {ACC1:acc#367.itm(2)} {ACC1:acc#367.itm(3)} -attr xrf 52896 -attr oid 952 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#367.itm}
+load net {conc#1014.itm(0)} -attr vt d
+load net {conc#1014.itm(1)} -attr vt d
+load net {conc#1014.itm(2)} -attr vt d
+load netBundle {conc#1014.itm} 3 {conc#1014.itm(0)} {conc#1014.itm(1)} {conc#1014.itm(2)} -attr xrf 52897 -attr oid 953 -attr vt d -attr @path {/sobel/sobel:core/conc#1014.itm}
+load net {ACC1-1:not#291.itm(0)} -attr vt d
+load net {ACC1-1:not#291.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#291.itm} 2 {ACC1-1:not#291.itm(0)} {ACC1-1:not#291.itm(1)} -attr xrf 52898 -attr oid 954 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#291.itm}
+load net {slc(ACC1:acc#219.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#219.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#219.psp#1.sva).itm} 2 {slc(ACC1:acc#219.psp#1.sva).itm(0)} {slc(ACC1:acc#219.psp#1.sva).itm(1)} -attr xrf 52899 -attr oid 955 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#1.sva).itm}
+load net {conc#1015.itm(0)} -attr vt d
+load net {conc#1015.itm(1)} -attr vt d
+load netBundle {conc#1015.itm} 2 {conc#1015.itm(0)} {conc#1015.itm(1)} -attr xrf 52900 -attr oid 956 -attr vt d -attr @path {/sobel/sobel:core/conc#1015.itm}
+load net {ACC1:slc#41.itm(0)} -attr vt d
+load net {ACC1:slc#41.itm(1)} -attr vt d
+load net {ACC1:slc#41.itm(2)} -attr vt d
+load net {ACC1:slc#41.itm(3)} -attr vt d
+load netBundle {ACC1:slc#41.itm} 4 {ACC1:slc#41.itm(0)} {ACC1:slc#41.itm(1)} {ACC1:slc#41.itm(2)} {ACC1:slc#41.itm(3)} -attr xrf 52901 -attr oid 957 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#41.itm}
+load net {ACC1:acc#365.itm(0)} -attr vt d
+load net {ACC1:acc#365.itm(1)} -attr vt d
+load net {ACC1:acc#365.itm(2)} -attr vt d
+load net {ACC1:acc#365.itm(3)} -attr vt d
+load net {ACC1:acc#365.itm(4)} -attr vt d
+load netBundle {ACC1:acc#365.itm} 5 {ACC1:acc#365.itm(0)} {ACC1:acc#365.itm(1)} {ACC1:acc#365.itm(2)} {ACC1:acc#365.itm(3)} {ACC1:acc#365.itm(4)} -attr xrf 52902 -attr oid 958 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365.itm}
+load net {conc#1016.itm(0)} -attr vt d
+load net {conc#1016.itm(1)} -attr vt d
+load net {conc#1016.itm(2)} -attr vt d
+load net {conc#1016.itm(3)} -attr vt d
+load netBundle {conc#1016.itm} 4 {conc#1016.itm(0)} {conc#1016.itm(1)} {conc#1016.itm(2)} {conc#1016.itm(3)} -attr xrf 52903 -attr oid 959 -attr vt d -attr @path {/sobel/sobel:core/conc#1016.itm}
+load net {ACC1:slc#39.itm(0)} -attr vt d
+load net {ACC1:slc#39.itm(1)} -attr vt d
+load net {ACC1:slc#39.itm(2)} -attr vt d
+load netBundle {ACC1:slc#39.itm} 3 {ACC1:slc#39.itm(0)} {ACC1:slc#39.itm(1)} {ACC1:slc#39.itm(2)} -attr xrf 52904 -attr oid 960 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#39.itm}
+load net {ACC1:acc#363.itm(0)} -attr vt d
+load net {ACC1:acc#363.itm(1)} -attr vt d
+load net {ACC1:acc#363.itm(2)} -attr vt d
+load net {ACC1:acc#363.itm(3)} -attr vt d
+load netBundle {ACC1:acc#363.itm} 4 {ACC1:acc#363.itm(0)} {ACC1:acc#363.itm(1)} {ACC1:acc#363.itm(2)} {ACC1:acc#363.itm(3)} -attr xrf 52905 -attr oid 961 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#363.itm}
+load net {conc#1017.itm(0)} -attr vt d
+load net {conc#1017.itm(1)} -attr vt d
+load netBundle {conc#1017.itm} 2 {conc#1017.itm(0)} {conc#1017.itm(1)} -attr xrf 52906 -attr oid 962 -attr vt d -attr @path {/sobel/sobel:core/conc#1017.itm}
+load net {ACC1:conc#1187.itm(0)} -attr vt d
+load net {ACC1:conc#1187.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1187.itm} 2 {ACC1:conc#1187.itm(0)} {ACC1:conc#1187.itm(1)} -attr xrf 52907 -attr oid 963 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1187.itm}
+load net {conc#1018.itm(0)} -attr vt d
+load net {conc#1018.itm(1)} -attr vt d
+load net {conc#1018.itm(2)} -attr vt d
+load net {conc#1018.itm(3)} -attr vt d
+load netBundle {conc#1018.itm} 4 {conc#1018.itm(0)} {conc#1018.itm(1)} {conc#1018.itm(2)} {conc#1018.itm(3)} -attr xrf 52908 -attr oid 964 -attr vt d -attr @path {/sobel/sobel:core/conc#1018.itm}
+load net {ACC1:slc#40.itm(0)} -attr vt d
+load net {ACC1:slc#40.itm(1)} -attr vt d
+load net {ACC1:slc#40.itm(2)} -attr vt d
+load netBundle {ACC1:slc#40.itm} 3 {ACC1:slc#40.itm(0)} {ACC1:slc#40.itm(1)} {ACC1:slc#40.itm(2)} -attr xrf 52909 -attr oid 965 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1:acc#364.itm(0)} -attr vt d
+load net {ACC1:acc#364.itm(1)} -attr vt d
+load net {ACC1:acc#364.itm(2)} -attr vt d
+load net {ACC1:acc#364.itm(3)} -attr vt d
+load netBundle {ACC1:acc#364.itm} 4 {ACC1:acc#364.itm(0)} {ACC1:acc#364.itm(1)} {ACC1:acc#364.itm(2)} {ACC1:acc#364.itm(3)} -attr xrf 52910 -attr oid 966 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#364.itm}
+load net {conc#1019.itm(0)} -attr vt d
+load net {conc#1019.itm(1)} -attr vt d
+load net {conc#1019.itm(2)} -attr vt d
+load netBundle {conc#1019.itm} 3 {conc#1019.itm(0)} {conc#1019.itm(1)} {conc#1019.itm(2)} -attr xrf 52911 -attr oid 967 -attr vt d -attr @path {/sobel/sobel:core/conc#1019.itm}
+load net {ACC1:slc#38.itm(0)} -attr vt d
+load net {ACC1:slc#38.itm(1)} -attr vt d
+load netBundle {ACC1:slc#38.itm} 2 {ACC1:slc#38.itm(0)} {ACC1:slc#38.itm(1)} -attr xrf 52912 -attr oid 968 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#38.itm}
+load net {ACC1:acc#362.itm(0)} -attr vt d
+load net {ACC1:acc#362.itm(1)} -attr vt d
+load net {ACC1:acc#362.itm(2)} -attr vt d
+load netBundle {ACC1:acc#362.itm} 3 {ACC1:acc#362.itm(0)} {ACC1:acc#362.itm(1)} {ACC1:acc#362.itm(2)} -attr xrf 52913 -attr oid 969 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#362.itm}
+load net {conc#1020.itm(0)} -attr vt d
+load net {conc#1020.itm(1)} -attr vt d
+load netBundle {conc#1020.itm} 2 {conc#1020.itm(0)} {conc#1020.itm(1)} -attr xrf 52914 -attr oid 970 -attr vt d -attr @path {/sobel/sobel:core/conc#1020.itm}
+load net {ACC1:conc#1185.itm(0)} -attr vt d
+load net {ACC1:conc#1185.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1185.itm} 2 {ACC1:conc#1185.itm(0)} {ACC1:conc#1185.itm(1)} -attr xrf 52915 -attr oid 971 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1185.itm}
+load net {ACC1:conc#1189.itm(0)} -attr vt d
+load net {ACC1:conc#1189.itm(1)} -attr vt d
+load net {ACC1:conc#1189.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1189.itm} 3 {ACC1:conc#1189.itm(0)} {ACC1:conc#1189.itm(1)} {ACC1:conc#1189.itm(2)} -attr xrf 52916 -attr oid 972 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1189.itm}
+load net {ACC1:slc#37.itm(0)} -attr vt d
+load net {ACC1:slc#37.itm(1)} -attr vt d
+load netBundle {ACC1:slc#37.itm} 2 {ACC1:slc#37.itm(0)} {ACC1:slc#37.itm(1)} -attr xrf 52917 -attr oid 973 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#37.itm}
+load net {ACC1:acc#361.itm(0)} -attr vt d
+load net {ACC1:acc#361.itm(1)} -attr vt d
+load net {ACC1:acc#361.itm(2)} -attr vt d
+load netBundle {ACC1:acc#361.itm} 3 {ACC1:acc#361.itm(0)} {ACC1:acc#361.itm(1)} {ACC1:acc#361.itm(2)} -attr xrf 52918 -attr oid 974 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#361.itm}
+load net {conc#1021.itm(0)} -attr vt d
+load net {conc#1021.itm(1)} -attr vt d
+load netBundle {conc#1021.itm} 2 {conc#1021.itm(0)} {conc#1021.itm(1)} -attr xrf 52919 -attr oid 975 -attr vt d -attr @path {/sobel/sobel:core/conc#1021.itm}
+load net {ACC1:conc#1183.itm(0)} -attr vt d
+load net {ACC1:conc#1183.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1183.itm} 2 {ACC1:conc#1183.itm(0)} {ACC1:conc#1183.itm(1)} -attr xrf 52920 -attr oid 976 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1183.itm}
+load net {ACC1:acc#349.itm(0)} -attr vt d
+load net {ACC1:acc#349.itm(1)} -attr vt d
+load net {ACC1:acc#349.itm(2)} -attr vt d
+load netBundle {ACC1:acc#349.itm} 3 {ACC1:acc#349.itm(0)} {ACC1:acc#349.itm(1)} {ACC1:acc#349.itm(2)} -attr xrf 52921 -attr oid 977 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#349.itm}
+load net {conc#1022.itm(0)} -attr vt d
+load net {conc#1022.itm(1)} -attr vt d
+load net {conc#1022.itm(2)} -attr vt d
+load netBundle {conc#1022.itm} 3 {conc#1022.itm(0)} {conc#1022.itm(1)} {conc#1022.itm(2)} -attr xrf 52922 -attr oid 978 -attr vt d -attr @path {/sobel/sobel:core/conc#1022.itm}
+load net {ACC1:conc#1162.itm(0)} -attr vt d
+load net {ACC1:conc#1162.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1162.itm} 2 {ACC1:conc#1162.itm(0)} {ACC1:conc#1162.itm(1)} -attr xrf 52923 -attr oid 979 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1162.itm}
+load net {ACC1:acc#348.itm(0)} -attr vt d
+load net {ACC1:acc#348.itm(1)} -attr vt d
+load net {ACC1:acc#348.itm(2)} -attr vt d
+load net {ACC1:acc#348.itm(3)} -attr vt d
+load netBundle {ACC1:acc#348.itm} 4 {ACC1:acc#348.itm(0)} {ACC1:acc#348.itm(1)} {ACC1:acc#348.itm(2)} {ACC1:acc#348.itm(3)} -attr xrf 52924 -attr oid 980 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {conc#1023.itm(0)} -attr vt d
+load net {conc#1023.itm(1)} -attr vt d
+load net {conc#1023.itm(2)} -attr vt d
+load netBundle {conc#1023.itm} 3 {conc#1023.itm(0)} {conc#1023.itm(1)} {conc#1023.itm(2)} -attr xrf 52925 -attr oid 981 -attr vt d -attr @path {/sobel/sobel:core/conc#1023.itm}
+load net {ACC1-1:not#297.itm(0)} -attr vt d
+load net {ACC1-1:not#297.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#297.itm} 2 {ACC1-1:not#297.itm(0)} {ACC1-1:not#297.itm(1)} -attr xrf 52926 -attr oid 982 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#297.itm}
+load net {slc(ACC1:acc#222.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#222.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#222.psp#1.sva).itm} 2 {slc(ACC1:acc#222.psp#1.sva).itm(0)} {slc(ACC1:acc#222.psp#1.sva).itm(1)} -attr xrf 52927 -attr oid 983 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp#1.sva).itm}
+load net {conc#1024.itm(0)} -attr vt d
+load net {conc#1024.itm(1)} -attr vt d
+load netBundle {conc#1024.itm} 2 {conc#1024.itm(0)} {conc#1024.itm(1)} -attr xrf 52928 -attr oid 984 -attr vt d -attr @path {/sobel/sobel:core/conc#1024.itm}
+load net {ACC1:acc#407.itm(0)} -attr vt d
+load net {ACC1:acc#407.itm(1)} -attr vt d
+load net {ACC1:acc#407.itm(2)} -attr vt d
+load net {ACC1:acc#407.itm(3)} -attr vt d
+load net {ACC1:acc#407.itm(4)} -attr vt d
+load net {ACC1:acc#407.itm(5)} -attr vt d
+load net {ACC1:acc#407.itm(6)} -attr vt d
+load net {ACC1:acc#407.itm(7)} -attr vt d
+load net {ACC1:acc#407.itm(8)} -attr vt d
+load net {ACC1:acc#407.itm(9)} -attr vt d
+load net {ACC1:acc#407.itm(10)} -attr vt d
+load netBundle {ACC1:acc#407.itm} 11 {ACC1:acc#407.itm(0)} {ACC1:acc#407.itm(1)} {ACC1:acc#407.itm(2)} {ACC1:acc#407.itm(3)} {ACC1:acc#407.itm(4)} {ACC1:acc#407.itm(5)} {ACC1:acc#407.itm(6)} {ACC1:acc#407.itm(7)} {ACC1:acc#407.itm(8)} {ACC1:acc#407.itm(9)} {ACC1:acc#407.itm(10)} -attr xrf 52929 -attr oid 985 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1-2:exs#1051.itm(0)} -attr vt d
+load net {ACC1-2:exs#1051.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1051.itm} 2 {ACC1-2:exs#1051.itm(0)} {ACC1-2:exs#1051.itm(1)} -attr xrf 52930 -attr oid 986 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1051.itm}
+load net {ACC1-2:exs#1043.itm(0)} -attr vt d
+load net {ACC1-2:exs#1043.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1043.itm} 2 {ACC1-2:exs#1043.itm(0)} {ACC1-2:exs#1043.itm(1)} -attr xrf 52931 -attr oid 987 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1043.itm}
+load net {ACC1:acc#412.itm(0)} -attr vt d
+load net {ACC1:acc#412.itm(1)} -attr vt d
+load net {ACC1:acc#412.itm(2)} -attr vt d
+load net {ACC1:acc#412.itm(3)} -attr vt d
+load net {ACC1:acc#412.itm(4)} -attr vt d
+load netBundle {ACC1:acc#412.itm} 5 {ACC1:acc#412.itm(0)} {ACC1:acc#412.itm(1)} {ACC1:acc#412.itm(2)} {ACC1:acc#412.itm(3)} {ACC1:acc#412.itm(4)} -attr xrf 52932 -attr oid 988 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412.itm}
+load net {conc#1025.itm(0)} -attr vt d
+load net {conc#1025.itm(1)} -attr vt d
+load net {conc#1025.itm(2)} -attr vt d
+load net {conc#1025.itm(3)} -attr vt d
+load netBundle {conc#1025.itm} 4 {conc#1025.itm(0)} {conc#1025.itm(1)} {conc#1025.itm(2)} {conc#1025.itm(3)} -attr xrf 52933 -attr oid 989 -attr vt d -attr @path {/sobel/sobel:core/conc#1025.itm}
+load net {ACC1:slc#80.itm(0)} -attr vt d
+load net {ACC1:slc#80.itm(1)} -attr vt d
+load net {ACC1:slc#80.itm(2)} -attr vt d
+load netBundle {ACC1:slc#80.itm} 3 {ACC1:slc#80.itm(0)} {ACC1:slc#80.itm(1)} {ACC1:slc#80.itm(2)} -attr xrf 52934 -attr oid 990 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#80.itm}
+load net {ACC1:acc#411.itm(0)} -attr vt d
+load net {ACC1:acc#411.itm(1)} -attr vt d
+load net {ACC1:acc#411.itm(2)} -attr vt d
+load net {ACC1:acc#411.itm(3)} -attr vt d
+load netBundle {ACC1:acc#411.itm} 4 {ACC1:acc#411.itm(0)} {ACC1:acc#411.itm(1)} {ACC1:acc#411.itm(2)} {ACC1:acc#411.itm(3)} -attr xrf 52935 -attr oid 991 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#411.itm}
+load net {conc#1026.itm(0)} -attr vt d
+load net {conc#1026.itm(1)} -attr vt d
+load net {conc#1026.itm(2)} -attr vt d
+load net {conc#1026.itm(3)} -attr vt d
+load netBundle {conc#1026.itm} 4 {conc#1026.itm(0)} {conc#1026.itm(1)} {conc#1026.itm(2)} {conc#1026.itm(3)} -attr xrf 52936 -attr oid 992 -attr vt d -attr @path {/sobel/sobel:core/conc#1026.itm}
+load net {ACC1:conc#1279.itm(0)} -attr vt d
+load net {ACC1:conc#1279.itm(1)} -attr vt d
+load net {ACC1:conc#1279.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1279.itm} 3 {ACC1:conc#1279.itm(0)} {ACC1:conc#1279.itm(1)} {ACC1:conc#1279.itm(2)} -attr xrf 52937 -attr oid 993 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1279.itm}
+load net {ACC1:slc#78.itm(0)} -attr vt d
+load net {ACC1:slc#78.itm(1)} -attr vt d
+load netBundle {ACC1:slc#78.itm} 2 {ACC1:slc#78.itm(0)} {ACC1:slc#78.itm(1)} -attr xrf 52938 -attr oid 994 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#78.itm}
+load net {ACC1:acc#409.itm(0)} -attr vt d
+load net {ACC1:acc#409.itm(1)} -attr vt d
+load net {ACC1:acc#409.itm(2)} -attr vt d
+load netBundle {ACC1:acc#409.itm} 3 {ACC1:acc#409.itm(0)} {ACC1:acc#409.itm(1)} {ACC1:acc#409.itm(2)} -attr xrf 52939 -attr oid 995 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#409.itm}
+load net {conc#1027.itm(0)} -attr vt d
+load net {conc#1027.itm(1)} -attr vt d
+load netBundle {conc#1027.itm} 2 {conc#1027.itm(0)} {conc#1027.itm(1)} -attr xrf 52940 -attr oid 996 -attr vt d -attr @path {/sobel/sobel:core/conc#1027.itm}
+load net {ACC1:conc#1275.itm(0)} -attr vt d
+load net {ACC1:conc#1275.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1275.itm} 2 {ACC1:conc#1275.itm(0)} {ACC1:conc#1275.itm(1)} -attr xrf 52941 -attr oid 997 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1275.itm}
+load net {ACC1:conc#1281.itm(0)} -attr vt d
+load net {ACC1:conc#1281.itm(1)} -attr vt d
+load net {ACC1:conc#1281.itm(2)} -attr vt d
+load net {ACC1:conc#1281.itm(3)} -attr vt d
+load net {ACC1:conc#1281.itm(4)} -attr vt d
+load netBundle {ACC1:conc#1281.itm} 5 {ACC1:conc#1281.itm(0)} {ACC1:conc#1281.itm(1)} {ACC1:conc#1281.itm(2)} {ACC1:conc#1281.itm(3)} {ACC1:conc#1281.itm(4)} -attr xrf 52942 -attr oid 998 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1281.itm}
+load net {ACC1:slc#79.itm(0)} -attr vt d
+load net {ACC1:slc#79.itm(1)} -attr vt d
+load net {ACC1:slc#79.itm(2)} -attr vt d
+load net {ACC1:slc#79.itm(3)} -attr vt d
+load netBundle {ACC1:slc#79.itm} 4 {ACC1:slc#79.itm(0)} {ACC1:slc#79.itm(1)} {ACC1:slc#79.itm(2)} {ACC1:slc#79.itm(3)} -attr xrf 52943 -attr oid 999 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#79.itm}
+load net {ACC1:acc#410.itm(0)} -attr vt d
+load net {ACC1:acc#410.itm(1)} -attr vt d
+load net {ACC1:acc#410.itm(2)} -attr vt d
+load net {ACC1:acc#410.itm(3)} -attr vt d
+load net {ACC1:acc#410.itm(4)} -attr vt d
+load netBundle {ACC1:acc#410.itm} 5 {ACC1:acc#410.itm(0)} {ACC1:acc#410.itm(1)} {ACC1:acc#410.itm(2)} {ACC1:acc#410.itm(3)} {ACC1:acc#410.itm(4)} -attr xrf 52944 -attr oid 1000 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410.itm}
+load net {conc#1028.itm(0)} -attr vt d
+load net {conc#1028.itm(1)} -attr vt d
+load net {conc#1028.itm(2)} -attr vt d
+load netBundle {conc#1028.itm} 3 {conc#1028.itm(0)} {conc#1028.itm(1)} {conc#1028.itm(2)} -attr xrf 52945 -attr oid 1001 -attr vt d -attr @path {/sobel/sobel:core/conc#1028.itm}
+load net {ACC1:slc#77.itm(0)} -attr vt d
+load net {ACC1:slc#77.itm(1)} -attr vt d
+load netBundle {ACC1:slc#77.itm} 2 {ACC1:slc#77.itm(0)} {ACC1:slc#77.itm(1)} -attr xrf 52946 -attr oid 1002 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#77.itm}
+load net {ACC1:acc#408.itm(0)} -attr vt d
+load net {ACC1:acc#408.itm(1)} -attr vt d
+load net {ACC1:acc#408.itm(2)} -attr vt d
+load netBundle {ACC1:acc#408.itm} 3 {ACC1:acc#408.itm(0)} {ACC1:acc#408.itm(1)} {ACC1:acc#408.itm(2)} -attr xrf 52947 -attr oid 1003 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#408.itm}
+load net {conc#1029.itm(0)} -attr vt d
+load net {conc#1029.itm(1)} -attr vt d
+load netBundle {conc#1029.itm} 2 {conc#1029.itm(0)} {conc#1029.itm(1)} -attr xrf 52948 -attr oid 1004 -attr vt d -attr @path {/sobel/sobel:core/conc#1029.itm}
+load net {ACC1:conc#1273.itm(0)} -attr vt d
+load net {ACC1:conc#1273.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1273.itm} 2 {ACC1:conc#1273.itm(0)} {ACC1:conc#1273.itm(1)} -attr xrf 52949 -attr oid 1005 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1273.itm}
+load net {ACC1:conc#1277.itm(0)} -attr vt d
+load net {ACC1:conc#1277.itm(1)} -attr vt d
+load net {ACC1:conc#1277.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1277.itm} 3 {ACC1:conc#1277.itm(0)} {ACC1:conc#1277.itm(1)} {ACC1:conc#1277.itm(2)} -attr xrf 52950 -attr oid 1006 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1277.itm}
+load net {ACC1-3:not#252.itm(0)} -attr vt d
+load net {ACC1-3:not#252.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#252.itm} 2 {ACC1-3:not#252.itm(0)} {ACC1-3:not#252.itm(1)} -attr xrf 52951 -attr oid 1007 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#252.itm}
+load net {slc(ACC1:acc#224.psp.sva)#14.itm(0)} -attr vt d
+load net {slc(ACC1:acc#224.psp.sva)#14.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#224.psp.sva)#14.itm} 2 {slc(ACC1:acc#224.psp.sva)#14.itm(0)} {slc(ACC1:acc#224.psp.sva)#14.itm(1)} -attr xrf 52952 -attr oid 1008 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#14.itm}
+load net {ACC1:acc#423.itm(0)} -attr vt d
+load net {ACC1:acc#423.itm(1)} -attr vt d
+load net {ACC1:acc#423.itm(2)} -attr vt d
+load net {ACC1:acc#423.itm(3)} -attr vt d
+load netBundle {ACC1:acc#423.itm} 4 {ACC1:acc#423.itm(0)} {ACC1:acc#423.itm(1)} {ACC1:acc#423.itm(2)} {ACC1:acc#423.itm(3)} -attr xrf 52953 -attr oid 1009 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#423.itm}
+load net {conc#1030.itm(0)} -attr vt d
+load net {conc#1030.itm(1)} -attr vt d
+load net {conc#1030.itm(2)} -attr vt d
+load netBundle {conc#1030.itm} 3 {conc#1030.itm(0)} {conc#1030.itm(1)} {conc#1030.itm(2)} -attr xrf 52954 -attr oid 1010 -attr vt d -attr @path {/sobel/sobel:core/conc#1030.itm}
+load net {ACC1-3:not#299.itm(0)} -attr vt d
+load net {ACC1-3:not#299.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#299.itm} 2 {ACC1-3:not#299.itm(0)} {ACC1-3:not#299.itm(1)} -attr xrf 52955 -attr oid 1011 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#299.itm}
+load net {slc(ACC1:acc#223.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#223.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#223.psp.sva).itm} 2 {slc(ACC1:acc#223.psp.sva).itm(0)} {slc(ACC1:acc#223.psp.sva).itm(1)} -attr xrf 52956 -attr oid 1012 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp.sva).itm}
+load net {conc#1031.itm(0)} -attr vt d
+load net {conc#1031.itm(1)} -attr vt d
+load netBundle {conc#1031.itm} 2 {conc#1031.itm(0)} {conc#1031.itm(1)} -attr xrf 52957 -attr oid 1013 -attr vt d -attr @path {/sobel/sobel:core/conc#1031.itm}
+load net {ACC1:acc#375.itm(0)} -attr vt d
+load net {ACC1:acc#375.itm(1)} -attr vt d
+load net {ACC1:acc#375.itm(2)} -attr vt d
+load net {ACC1:acc#375.itm(3)} -attr vt d
+load net {ACC1:acc#375.itm(4)} -attr vt d
+load netBundle {ACC1:acc#375.itm} 5 {ACC1:acc#375.itm(0)} {ACC1:acc#375.itm(1)} {ACC1:acc#375.itm(2)} {ACC1:acc#375.itm(3)} {ACC1:acc#375.itm(4)} -attr xrf 52958 -attr oid 1014 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375.itm}
+load net {conc#1032.itm(0)} -attr vt d
+load net {conc#1032.itm(1)} -attr vt d
+load net {conc#1032.itm(2)} -attr vt d
+load net {conc#1032.itm(3)} -attr vt d
+load netBundle {conc#1032.itm} 4 {conc#1032.itm(0)} {conc#1032.itm(1)} {conc#1032.itm(2)} {conc#1032.itm(3)} -attr xrf 52959 -attr oid 1015 -attr vt d -attr @path {/sobel/sobel:core/conc#1032.itm}
+load net {ACC1:slc#48.itm(0)} -attr vt d
+load net {ACC1:slc#48.itm(1)} -attr vt d
+load net {ACC1:slc#48.itm(2)} -attr vt d
+load netBundle {ACC1:slc#48.itm} 3 {ACC1:slc#48.itm(0)} {ACC1:slc#48.itm(1)} {ACC1:slc#48.itm(2)} -attr xrf 52960 -attr oid 1016 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#48.itm}
+load net {ACC1:acc#374.itm(0)} -attr vt d
+load net {ACC1:acc#374.itm(1)} -attr vt d
+load net {ACC1:acc#374.itm(2)} -attr vt d
+load net {ACC1:acc#374.itm(3)} -attr vt d
+load netBundle {ACC1:acc#374.itm} 4 {ACC1:acc#374.itm(0)} {ACC1:acc#374.itm(1)} {ACC1:acc#374.itm(2)} {ACC1:acc#374.itm(3)} -attr xrf 52961 -attr oid 1017 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#374.itm}
+load net {conc#1033.itm(0)} -attr vt d
+load net {conc#1033.itm(1)} -attr vt d
+load net {conc#1033.itm(2)} -attr vt d
+load net {conc#1033.itm(3)} -attr vt d
+load netBundle {conc#1033.itm} 4 {conc#1033.itm(0)} {conc#1033.itm(1)} {conc#1033.itm(2)} {conc#1033.itm(3)} -attr xrf 52962 -attr oid 1018 -attr vt d -attr @path {/sobel/sobel:core/conc#1033.itm}
+load net {ACC1:conc#1207.itm(0)} -attr vt d
+load net {ACC1:conc#1207.itm(1)} -attr vt d
+load net {ACC1:conc#1207.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1207.itm} 3 {ACC1:conc#1207.itm(0)} {ACC1:conc#1207.itm(1)} {ACC1:conc#1207.itm(2)} -attr xrf 52963 -attr oid 1019 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1207.itm}
+load net {ACC1:slc#46.itm(0)} -attr vt d
+load net {ACC1:slc#46.itm(1)} -attr vt d
+load netBundle {ACC1:slc#46.itm} 2 {ACC1:slc#46.itm(0)} {ACC1:slc#46.itm(1)} -attr xrf 52964 -attr oid 1020 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#46.itm}
+load net {ACC1:acc#372.itm(0)} -attr vt d
+load net {ACC1:acc#372.itm(1)} -attr vt d
+load net {ACC1:acc#372.itm(2)} -attr vt d
+load netBundle {ACC1:acc#372.itm} 3 {ACC1:acc#372.itm(0)} {ACC1:acc#372.itm(1)} {ACC1:acc#372.itm(2)} -attr xrf 52965 -attr oid 1021 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#372.itm}
+load net {conc#1034.itm(0)} -attr vt d
+load net {conc#1034.itm(1)} -attr vt d
+load netBundle {conc#1034.itm} 2 {conc#1034.itm(0)} {conc#1034.itm(1)} -attr xrf 52966 -attr oid 1022 -attr vt d -attr @path {/sobel/sobel:core/conc#1034.itm}
+load net {ACC1:conc#1203.itm(0)} -attr vt d
+load net {ACC1:conc#1203.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1203.itm} 2 {ACC1:conc#1203.itm(0)} {ACC1:conc#1203.itm(1)} -attr xrf 52967 -attr oid 1023 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1203.itm}
+load net {ACC1:conc#1209.itm(0)} -attr vt d
+load net {ACC1:conc#1209.itm(1)} -attr vt d
+load net {ACC1:conc#1209.itm(2)} -attr vt d
+load net {ACC1:conc#1209.itm(3)} -attr vt d
+load net {ACC1:conc#1209.itm(4)} -attr vt d
+load netBundle {ACC1:conc#1209.itm} 5 {ACC1:conc#1209.itm(0)} {ACC1:conc#1209.itm(1)} {ACC1:conc#1209.itm(2)} {ACC1:conc#1209.itm(3)} {ACC1:conc#1209.itm(4)} -attr xrf 52968 -attr oid 1024 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1209.itm}
+load net {ACC1:slc#47.itm(0)} -attr vt d
+load net {ACC1:slc#47.itm(1)} -attr vt d
+load net {ACC1:slc#47.itm(2)} -attr vt d
+load net {ACC1:slc#47.itm(3)} -attr vt d
+load netBundle {ACC1:slc#47.itm} 4 {ACC1:slc#47.itm(0)} {ACC1:slc#47.itm(1)} {ACC1:slc#47.itm(2)} {ACC1:slc#47.itm(3)} -attr xrf 52969 -attr oid 1025 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#47.itm}
+load net {ACC1:acc#373.itm(0)} -attr vt d
+load net {ACC1:acc#373.itm(1)} -attr vt d
+load net {ACC1:acc#373.itm(2)} -attr vt d
+load net {ACC1:acc#373.itm(3)} -attr vt d
+load net {ACC1:acc#373.itm(4)} -attr vt d
+load netBundle {ACC1:acc#373.itm} 5 {ACC1:acc#373.itm(0)} {ACC1:acc#373.itm(1)} {ACC1:acc#373.itm(2)} {ACC1:acc#373.itm(3)} {ACC1:acc#373.itm(4)} -attr xrf 52970 -attr oid 1026 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373.itm}
+load net {conc#1035.itm(0)} -attr vt d
+load net {conc#1035.itm(1)} -attr vt d
+load net {conc#1035.itm(2)} -attr vt d
+load netBundle {conc#1035.itm} 3 {conc#1035.itm(0)} {conc#1035.itm(1)} {conc#1035.itm(2)} -attr xrf 52971 -attr oid 1027 -attr vt d -attr @path {/sobel/sobel:core/conc#1035.itm}
+load net {ACC1:slc#45.itm(0)} -attr vt d
+load net {ACC1:slc#45.itm(1)} -attr vt d
+load netBundle {ACC1:slc#45.itm} 2 {ACC1:slc#45.itm(0)} {ACC1:slc#45.itm(1)} -attr xrf 52972 -attr oid 1028 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#45.itm}
+load net {ACC1:acc#371.itm(0)} -attr vt d
+load net {ACC1:acc#371.itm(1)} -attr vt d
+load net {ACC1:acc#371.itm(2)} -attr vt d
+load netBundle {ACC1:acc#371.itm} 3 {ACC1:acc#371.itm(0)} {ACC1:acc#371.itm(1)} {ACC1:acc#371.itm(2)} -attr xrf 52973 -attr oid 1029 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#371.itm}
+load net {conc#1036.itm(0)} -attr vt d
+load net {conc#1036.itm(1)} -attr vt d
+load netBundle {conc#1036.itm} 2 {conc#1036.itm(0)} {conc#1036.itm(1)} -attr xrf 52974 -attr oid 1030 -attr vt d -attr @path {/sobel/sobel:core/conc#1036.itm}
+load net {ACC1:conc#1201.itm(0)} -attr vt d
+load net {ACC1:conc#1201.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1201.itm} 2 {ACC1:conc#1201.itm(0)} {ACC1:conc#1201.itm(1)} -attr xrf 52975 -attr oid 1031 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1201.itm}
+load net {ACC1:conc#1205.itm(0)} -attr vt d
+load net {ACC1:conc#1205.itm(1)} -attr vt d
+load net {ACC1:conc#1205.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1205.itm} 3 {ACC1:conc#1205.itm(0)} {ACC1:conc#1205.itm(1)} {ACC1:conc#1205.itm(2)} -attr xrf 52976 -attr oid 1032 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1205.itm}
+load net {ACC1-2:not#243.itm(0)} -attr vt d
+load net {ACC1-2:not#243.itm(1)} -attr vt d
+load netBundle {ACC1-2:not#243.itm} 2 {ACC1-2:not#243.itm(0)} {ACC1-2:not#243.itm(1)} -attr xrf 52977 -attr oid 1033 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#243.itm}
+load net {slc(ACC1:acc#228.psp.sva)#12.itm(0)} -attr vt d
+load net {slc(ACC1:acc#228.psp.sva)#12.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#228.psp.sva)#12.itm} 2 {slc(ACC1:acc#228.psp.sva)#12.itm(0)} {slc(ACC1:acc#228.psp.sva)#12.itm(1)} -attr xrf 52978 -attr oid 1034 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#12.itm}
+load net {ACC1:acc#395.itm(0)} -attr vt d
+load net {ACC1:acc#395.itm(1)} -attr vt d
+load net {ACC1:acc#395.itm(2)} -attr vt d
+load net {ACC1:acc#395.itm(3)} -attr vt d
+load netBundle {ACC1:acc#395.itm} 4 {ACC1:acc#395.itm(0)} {ACC1:acc#395.itm(1)} {ACC1:acc#395.itm(2)} {ACC1:acc#395.itm(3)} -attr xrf 52979 -attr oid 1035 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#395.itm}
+load net {conc#1037.itm(0)} -attr vt d
+load net {conc#1037.itm(1)} -attr vt d
+load net {conc#1037.itm(2)} -attr vt d
+load netBundle {conc#1037.itm} 3 {conc#1037.itm(0)} {conc#1037.itm(1)} {conc#1037.itm(2)} -attr xrf 52980 -attr oid 1036 -attr vt d -attr @path {/sobel/sobel:core/conc#1037.itm}
+load net {ACC1-3:not#293.itm(0)} -attr vt d
+load net {ACC1-3:not#293.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#293.itm} 2 {ACC1-3:not#293.itm(0)} {ACC1-3:not#293.itm(1)} -attr xrf 52981 -attr oid 1037 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#293.itm}
+load net {slc(ACC1:acc#220.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#220.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#220.psp.sva).itm} 2 {slc(ACC1:acc#220.psp.sva).itm(0)} {slc(ACC1:acc#220.psp.sva).itm(1)} -attr xrf 52982 -attr oid 1038 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp.sva).itm}
+load net {conc#1038.itm(0)} -attr vt d
+load net {conc#1038.itm(1)} -attr vt d
+load netBundle {conc#1038.itm} 2 {conc#1038.itm(0)} {conc#1038.itm(1)} -attr xrf 52983 -attr oid 1039 -attr vt d -attr @path {/sobel/sobel:core/conc#1038.itm}
+load net {ACC1:acc#384.itm(0)} -attr vt d
+load net {ACC1:acc#384.itm(1)} -attr vt d
+load net {ACC1:acc#384.itm(2)} -attr vt d
+load net {ACC1:acc#384.itm(3)} -attr vt d
+load net {ACC1:acc#384.itm(4)} -attr vt d
+load netBundle {ACC1:acc#384.itm} 5 {ACC1:acc#384.itm(0)} {ACC1:acc#384.itm(1)} {ACC1:acc#384.itm(2)} {ACC1:acc#384.itm(3)} {ACC1:acc#384.itm(4)} -attr xrf 52984 -attr oid 1040 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384.itm}
+load net {conc#1039.itm(0)} -attr vt d
+load net {conc#1039.itm(1)} -attr vt d
+load net {conc#1039.itm(2)} -attr vt d
+load net {conc#1039.itm(3)} -attr vt d
+load netBundle {conc#1039.itm} 4 {conc#1039.itm(0)} {conc#1039.itm(1)} {conc#1039.itm(2)} {conc#1039.itm(3)} -attr xrf 52985 -attr oid 1041 -attr vt d -attr @path {/sobel/sobel:core/conc#1039.itm}
+load net {ACC1:slc#56.itm(0)} -attr vt d
+load net {ACC1:slc#56.itm(1)} -attr vt d
+load net {ACC1:slc#56.itm(2)} -attr vt d
+load netBundle {ACC1:slc#56.itm} 3 {ACC1:slc#56.itm(0)} {ACC1:slc#56.itm(1)} {ACC1:slc#56.itm(2)} -attr xrf 52986 -attr oid 1042 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#56.itm}
+load net {ACC1:acc#383.itm(0)} -attr vt d
+load net {ACC1:acc#383.itm(1)} -attr vt d
+load net {ACC1:acc#383.itm(2)} -attr vt d
+load net {ACC1:acc#383.itm(3)} -attr vt d
+load netBundle {ACC1:acc#383.itm} 4 {ACC1:acc#383.itm(0)} {ACC1:acc#383.itm(1)} {ACC1:acc#383.itm(2)} {ACC1:acc#383.itm(3)} -attr xrf 52987 -attr oid 1043 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#383.itm}
+load net {conc#1040.itm(0)} -attr vt d
+load net {conc#1040.itm(1)} -attr vt d
+load net {conc#1040.itm(2)} -attr vt d
+load net {conc#1040.itm(3)} -attr vt d
+load netBundle {conc#1040.itm} 4 {conc#1040.itm(0)} {conc#1040.itm(1)} {conc#1040.itm(2)} {conc#1040.itm(3)} -attr xrf 52988 -attr oid 1044 -attr vt d -attr @path {/sobel/sobel:core/conc#1040.itm}
+load net {ACC1:conc#1225.itm(0)} -attr vt d
+load net {ACC1:conc#1225.itm(1)} -attr vt d
+load net {ACC1:conc#1225.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1225.itm} 3 {ACC1:conc#1225.itm(0)} {ACC1:conc#1225.itm(1)} {ACC1:conc#1225.itm(2)} -attr xrf 52989 -attr oid 1045 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1225.itm}
+load net {ACC1:slc#54.itm(0)} -attr vt d
+load net {ACC1:slc#54.itm(1)} -attr vt d
+load netBundle {ACC1:slc#54.itm} 2 {ACC1:slc#54.itm(0)} {ACC1:slc#54.itm(1)} -attr xrf 52990 -attr oid 1046 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#54.itm}
+load net {ACC1:acc#381.itm(0)} -attr vt d
+load net {ACC1:acc#381.itm(1)} -attr vt d
+load net {ACC1:acc#381.itm(2)} -attr vt d
+load netBundle {ACC1:acc#381.itm} 3 {ACC1:acc#381.itm(0)} {ACC1:acc#381.itm(1)} {ACC1:acc#381.itm(2)} -attr xrf 52991 -attr oid 1047 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#381.itm}
+load net {conc#1041.itm(0)} -attr vt d
+load net {conc#1041.itm(1)} -attr vt d
+load netBundle {conc#1041.itm} 2 {conc#1041.itm(0)} {conc#1041.itm(1)} -attr xrf 52992 -attr oid 1048 -attr vt d -attr @path {/sobel/sobel:core/conc#1041.itm}
+load net {ACC1:conc#1221.itm(0)} -attr vt d
+load net {ACC1:conc#1221.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1221.itm} 2 {ACC1:conc#1221.itm(0)} {ACC1:conc#1221.itm(1)} -attr xrf 52993 -attr oid 1049 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1221.itm}
+load net {ACC1:conc#1227.itm(0)} -attr vt d
+load net {ACC1:conc#1227.itm(1)} -attr vt d
+load net {ACC1:conc#1227.itm(2)} -attr vt d
+load net {ACC1:conc#1227.itm(3)} -attr vt d
+load net {ACC1:conc#1227.itm(4)} -attr vt d
+load netBundle {ACC1:conc#1227.itm} 5 {ACC1:conc#1227.itm(0)} {ACC1:conc#1227.itm(1)} {ACC1:conc#1227.itm(2)} {ACC1:conc#1227.itm(3)} {ACC1:conc#1227.itm(4)} -attr xrf 52994 -attr oid 1050 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1227.itm}
+load net {ACC1:slc#55.itm(0)} -attr vt d
+load net {ACC1:slc#55.itm(1)} -attr vt d
+load net {ACC1:slc#55.itm(2)} -attr vt d
+load net {ACC1:slc#55.itm(3)} -attr vt d
+load netBundle {ACC1:slc#55.itm} 4 {ACC1:slc#55.itm(0)} {ACC1:slc#55.itm(1)} {ACC1:slc#55.itm(2)} {ACC1:slc#55.itm(3)} -attr xrf 52995 -attr oid 1051 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#55.itm}
+load net {ACC1:acc#382.itm(0)} -attr vt d
+load net {ACC1:acc#382.itm(1)} -attr vt d
+load net {ACC1:acc#382.itm(2)} -attr vt d
+load net {ACC1:acc#382.itm(3)} -attr vt d
+load net {ACC1:acc#382.itm(4)} -attr vt d
+load netBundle {ACC1:acc#382.itm} 5 {ACC1:acc#382.itm(0)} {ACC1:acc#382.itm(1)} {ACC1:acc#382.itm(2)} {ACC1:acc#382.itm(3)} {ACC1:acc#382.itm(4)} -attr xrf 52996 -attr oid 1052 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382.itm}
+load net {conc#1042.itm(0)} -attr vt d
+load net {conc#1042.itm(1)} -attr vt d
+load net {conc#1042.itm(2)} -attr vt d
+load netBundle {conc#1042.itm} 3 {conc#1042.itm(0)} {conc#1042.itm(1)} {conc#1042.itm(2)} -attr xrf 52997 -attr oid 1053 -attr vt d -attr @path {/sobel/sobel:core/conc#1042.itm}
+load net {ACC1:slc#53.itm(0)} -attr vt d
+load net {ACC1:slc#53.itm(1)} -attr vt d
+load netBundle {ACC1:slc#53.itm} 2 {ACC1:slc#53.itm(0)} {ACC1:slc#53.itm(1)} -attr xrf 52998 -attr oid 1054 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#53.itm}
+load net {ACC1:acc#380.itm(0)} -attr vt d
+load net {ACC1:acc#380.itm(1)} -attr vt d
+load net {ACC1:acc#380.itm(2)} -attr vt d
+load netBundle {ACC1:acc#380.itm} 3 {ACC1:acc#380.itm(0)} {ACC1:acc#380.itm(1)} {ACC1:acc#380.itm(2)} -attr xrf 52999 -attr oid 1055 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#380.itm}
+load net {conc#1043.itm(0)} -attr vt d
+load net {conc#1043.itm(1)} -attr vt d
+load netBundle {conc#1043.itm} 2 {conc#1043.itm(0)} {conc#1043.itm(1)} -attr xrf 53000 -attr oid 1056 -attr vt d -attr @path {/sobel/sobel:core/conc#1043.itm}
+load net {ACC1:conc#1219.itm(0)} -attr vt d
+load net {ACC1:conc#1219.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1219.itm} 2 {ACC1:conc#1219.itm(0)} {ACC1:conc#1219.itm(1)} -attr xrf 53001 -attr oid 1057 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1219.itm}
+load net {ACC1:conc#1223.itm(0)} -attr vt d
+load net {ACC1:conc#1223.itm(1)} -attr vt d
+load net {ACC1:conc#1223.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1223.itm} 3 {ACC1:conc#1223.itm(0)} {ACC1:conc#1223.itm(1)} {ACC1:conc#1223.itm(2)} -attr xrf 53002 -attr oid 1058 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1223.itm}
+load net {ACC1-2:not#225.itm(0)} -attr vt d
+load net {ACC1-2:not#225.itm(1)} -attr vt d
+load netBundle {ACC1-2:not#225.itm} 2 {ACC1-2:not#225.itm(0)} {ACC1-2:not#225.itm(1)} -attr xrf 53003 -attr oid 1059 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#225.itm}
+load net {slc(ACC1:acc#226.psp.sva)#12.itm(0)} -attr vt d
+load net {slc(ACC1:acc#226.psp.sva)#12.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#226.psp.sva)#12.itm} 2 {slc(ACC1:acc#226.psp.sva)#12.itm(0)} {slc(ACC1:acc#226.psp.sva)#12.itm(1)} -attr xrf 53004 -attr oid 1060 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#12.itm}
+load net {ACC1:slc#73.itm(0)} -attr vt d
+load net {ACC1:slc#73.itm(1)} -attr vt d
+load net {ACC1:slc#73.itm(2)} -attr vt d
+load net {ACC1:slc#73.itm(3)} -attr vt d
+load netBundle {ACC1:slc#73.itm} 4 {ACC1:slc#73.itm(0)} {ACC1:slc#73.itm(1)} {ACC1:slc#73.itm(2)} {ACC1:slc#73.itm(3)} -attr xrf 53005 -attr oid 1061 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#403.itm(0)} -attr vt d
+load net {ACC1:acc#403.itm(1)} -attr vt d
+load net {ACC1:acc#403.itm(2)} -attr vt d
+load net {ACC1:acc#403.itm(3)} -attr vt d
+load net {ACC1:acc#403.itm(4)} -attr vt d
+load netBundle {ACC1:acc#403.itm} 5 {ACC1:acc#403.itm(0)} {ACC1:acc#403.itm(1)} {ACC1:acc#403.itm(2)} {ACC1:acc#403.itm(3)} {ACC1:acc#403.itm(4)} -attr xrf 53006 -attr oid 1062 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403.itm}
+load net {conc#1044.itm(0)} -attr vt d
+load net {conc#1044.itm(1)} -attr vt d
+load net {conc#1044.itm(2)} -attr vt d
+load net {conc#1044.itm(3)} -attr vt d
+load netBundle {conc#1044.itm} 4 {conc#1044.itm(0)} {conc#1044.itm(1)} {conc#1044.itm(2)} {conc#1044.itm(3)} -attr xrf 53007 -attr oid 1063 -attr vt d -attr @path {/sobel/sobel:core/conc#1044.itm}
+load net {ACC1:slc#71.itm(0)} -attr vt d
+load net {ACC1:slc#71.itm(1)} -attr vt d
+load net {ACC1:slc#71.itm(2)} -attr vt d
+load netBundle {ACC1:slc#71.itm} 3 {ACC1:slc#71.itm(0)} {ACC1:slc#71.itm(1)} {ACC1:slc#71.itm(2)} -attr xrf 53008 -attr oid 1064 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#71.itm}
+load net {ACC1:acc#401.itm(0)} -attr vt d
+load net {ACC1:acc#401.itm(1)} -attr vt d
+load net {ACC1:acc#401.itm(2)} -attr vt d
+load net {ACC1:acc#401.itm(3)} -attr vt d
+load netBundle {ACC1:acc#401.itm} 4 {ACC1:acc#401.itm(0)} {ACC1:acc#401.itm(1)} {ACC1:acc#401.itm(2)} {ACC1:acc#401.itm(3)} -attr xrf 53009 -attr oid 1065 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#401.itm}
+load net {conc#1045.itm(0)} -attr vt d
+load net {conc#1045.itm(1)} -attr vt d
+load netBundle {conc#1045.itm} 2 {conc#1045.itm(0)} {conc#1045.itm(1)} -attr xrf 53010 -attr oid 1066 -attr vt d -attr @path {/sobel/sobel:core/conc#1045.itm}
+load net {ACC1:conc#1259.itm(0)} -attr vt d
+load net {ACC1:conc#1259.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1259.itm} 2 {ACC1:conc#1259.itm(0)} {ACC1:conc#1259.itm(1)} -attr xrf 53011 -attr oid 1067 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1259.itm}
+load net {conc#1046.itm(0)} -attr vt d
+load net {conc#1046.itm(1)} -attr vt d
+load net {conc#1046.itm(2)} -attr vt d
+load net {conc#1046.itm(3)} -attr vt d
+load netBundle {conc#1046.itm} 4 {conc#1046.itm(0)} {conc#1046.itm(1)} {conc#1046.itm(2)} {conc#1046.itm(3)} -attr xrf 53012 -attr oid 1068 -attr vt d -attr @path {/sobel/sobel:core/conc#1046.itm}
+load net {ACC1:slc#72.itm(0)} -attr vt d
+load net {ACC1:slc#72.itm(1)} -attr vt d
+load net {ACC1:slc#72.itm(2)} -attr vt d
+load netBundle {ACC1:slc#72.itm} 3 {ACC1:slc#72.itm(0)} {ACC1:slc#72.itm(1)} {ACC1:slc#72.itm(2)} -attr xrf 53013 -attr oid 1069 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#402.itm(0)} -attr vt d
+load net {ACC1:acc#402.itm(1)} -attr vt d
+load net {ACC1:acc#402.itm(2)} -attr vt d
+load net {ACC1:acc#402.itm(3)} -attr vt d
+load netBundle {ACC1:acc#402.itm} 4 {ACC1:acc#402.itm(0)} {ACC1:acc#402.itm(1)} {ACC1:acc#402.itm(2)} {ACC1:acc#402.itm(3)} -attr xrf 53014 -attr oid 1070 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#402.itm}
+load net {conc#1047.itm(0)} -attr vt d
+load net {conc#1047.itm(1)} -attr vt d
+load net {conc#1047.itm(2)} -attr vt d
+load netBundle {conc#1047.itm} 3 {conc#1047.itm(0)} {conc#1047.itm(1)} {conc#1047.itm(2)} -attr xrf 53015 -attr oid 1071 -attr vt d -attr @path {/sobel/sobel:core/conc#1047.itm}
+load net {ACC1:slc#70.itm(0)} -attr vt d
+load net {ACC1:slc#70.itm(1)} -attr vt d
+load netBundle {ACC1:slc#70.itm} 2 {ACC1:slc#70.itm(0)} {ACC1:slc#70.itm(1)} -attr xrf 53016 -attr oid 1072 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#70.itm}
+load net {ACC1:acc#400.itm(0)} -attr vt d
+load net {ACC1:acc#400.itm(1)} -attr vt d
+load net {ACC1:acc#400.itm(2)} -attr vt d
+load netBundle {ACC1:acc#400.itm} 3 {ACC1:acc#400.itm(0)} {ACC1:acc#400.itm(1)} {ACC1:acc#400.itm(2)} -attr xrf 53017 -attr oid 1073 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#400.itm}
+load net {conc#1048.itm(0)} -attr vt d
+load net {conc#1048.itm(1)} -attr vt d
+load netBundle {conc#1048.itm} 2 {conc#1048.itm(0)} {conc#1048.itm(1)} -attr xrf 53018 -attr oid 1074 -attr vt d -attr @path {/sobel/sobel:core/conc#1048.itm}
+load net {ACC1:conc#1257.itm(0)} -attr vt d
+load net {ACC1:conc#1257.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1257.itm} 2 {ACC1:conc#1257.itm(0)} {ACC1:conc#1257.itm(1)} -attr xrf 53019 -attr oid 1075 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1257.itm}
+load net {ACC1:conc#1261.itm(0)} -attr vt d
+load net {ACC1:conc#1261.itm(1)} -attr vt d
+load net {ACC1:conc#1261.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1261.itm} 3 {ACC1:conc#1261.itm(0)} {ACC1:conc#1261.itm(1)} {ACC1:conc#1261.itm(2)} -attr xrf 53020 -attr oid 1076 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1261.itm}
+load net {ACC1:slc#69.itm(0)} -attr vt d
+load net {ACC1:slc#69.itm(1)} -attr vt d
+load netBundle {ACC1:slc#69.itm} 2 {ACC1:slc#69.itm(0)} {ACC1:slc#69.itm(1)} -attr xrf 53021 -attr oid 1077 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#69.itm}
+load net {ACC1:acc#399.itm(0)} -attr vt d
+load net {ACC1:acc#399.itm(1)} -attr vt d
+load net {ACC1:acc#399.itm(2)} -attr vt d
+load netBundle {ACC1:acc#399.itm} 3 {ACC1:acc#399.itm(0)} {ACC1:acc#399.itm(1)} {ACC1:acc#399.itm(2)} -attr xrf 53022 -attr oid 1078 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#399.itm}
+load net {conc#1049.itm(0)} -attr vt d
+load net {conc#1049.itm(1)} -attr vt d
+load netBundle {conc#1049.itm} 2 {conc#1049.itm(0)} {conc#1049.itm(1)} -attr xrf 53023 -attr oid 1079 -attr vt d -attr @path {/sobel/sobel:core/conc#1049.itm}
+load net {ACC1:conc#1255.itm(0)} -attr vt d
+load net {ACC1:conc#1255.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1255.itm} 2 {ACC1:conc#1255.itm(0)} {ACC1:conc#1255.itm(1)} -attr xrf 53024 -attr oid 1080 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1255.itm}
+load net {ACC1:acc#414.itm(0)} -attr vt d
+load net {ACC1:acc#414.itm(1)} -attr vt d
+load net {ACC1:acc#414.itm(2)} -attr vt d
+load net {ACC1:acc#414.itm(3)} -attr vt d
+load netBundle {ACC1:acc#414.itm} 4 {ACC1:acc#414.itm(0)} {ACC1:acc#414.itm(1)} {ACC1:acc#414.itm(2)} {ACC1:acc#414.itm(3)} -attr xrf 53025 -attr oid 1081 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#414.itm}
+load net {conc#1050.itm(0)} -attr vt d
+load net {conc#1050.itm(1)} -attr vt d
+load net {conc#1050.itm(2)} -attr vt d
+load netBundle {conc#1050.itm} 3 {conc#1050.itm(0)} {conc#1050.itm(1)} {conc#1050.itm(2)} -attr xrf 53026 -attr oid 1082 -attr vt d -attr @path {/sobel/sobel:core/conc#1050.itm}
+load net {ACC1-3:not#297.itm(0)} -attr vt d
+load net {ACC1-3:not#297.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#297.itm} 2 {ACC1-3:not#297.itm(0)} {ACC1-3:not#297.itm(1)} -attr xrf 53027 -attr oid 1083 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#297.itm}
+load net {slc(ACC1:acc#222.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#222.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#222.psp.sva).itm} 2 {slc(ACC1:acc#222.psp.sva).itm(0)} {slc(ACC1:acc#222.psp.sva).itm(1)} -attr xrf 53028 -attr oid 1084 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp.sva).itm}
+load net {conc#1051.itm(0)} -attr vt d
+load net {conc#1051.itm(1)} -attr vt d
+load netBundle {conc#1051.itm} 2 {conc#1051.itm(0)} {conc#1051.itm(1)} -attr xrf 53029 -attr oid 1085 -attr vt d -attr @path {/sobel/sobel:core/conc#1051.itm}
+load net {ACC1:acc#377.itm(0)} -attr vt d
+load net {ACC1:acc#377.itm(1)} -attr vt d
+load net {ACC1:acc#377.itm(2)} -attr vt d
+load net {ACC1:acc#377.itm(3)} -attr vt d
+load netBundle {ACC1:acc#377.itm} 4 {ACC1:acc#377.itm(0)} {ACC1:acc#377.itm(1)} {ACC1:acc#377.itm(2)} {ACC1:acc#377.itm(3)} -attr xrf 53030 -attr oid 1086 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#377.itm}
+load net {conc#1052.itm(0)} -attr vt d
+load net {conc#1052.itm(1)} -attr vt d
+load net {conc#1052.itm(2)} -attr vt d
+load netBundle {conc#1052.itm} 3 {conc#1052.itm(0)} {conc#1052.itm(1)} {conc#1052.itm(2)} -attr xrf 53031 -attr oid 1087 -attr vt d -attr @path {/sobel/sobel:core/conc#1052.itm}
+load net {ACC1-2:not#295.itm(0)} -attr vt d
+load net {ACC1-2:not#295.itm(1)} -attr vt d
+load netBundle {ACC1-2:not#295.itm} 2 {ACC1-2:not#295.itm(0)} {ACC1-2:not#295.itm(1)} -attr xrf 53032 -attr oid 1088 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#295.itm}
+load net {slc(ACC1:acc#221.psp#2.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#221.psp#2.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#221.psp#2.sva).itm} 2 {slc(ACC1:acc#221.psp#2.sva).itm(0)} {slc(ACC1:acc#221.psp#2.sva).itm(1)} -attr xrf 53033 -attr oid 1089 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp#2.sva).itm}
+load net {conc#1053.itm(0)} -attr vt d
+load net {conc#1053.itm(1)} -attr vt d
+load netBundle {conc#1053.itm} 2 {conc#1053.itm(0)} {conc#1053.itm(1)} -attr xrf 53034 -attr oid 1090 -attr vt d -attr @path {/sobel/sobel:core/conc#1053.itm}
+load net {ACC1:acc#346.itm(0)} -attr vt d
+load net {ACC1:acc#346.itm(1)} -attr vt d
+load net {ACC1:acc#346.itm(2)} -attr vt d
+load net {ACC1:acc#346.itm(3)} -attr vt d
+load net {ACC1:acc#346.itm(4)} -attr vt d
+load netBundle {ACC1:acc#346.itm} 5 {ACC1:acc#346.itm(0)} {ACC1:acc#346.itm(1)} {ACC1:acc#346.itm(2)} {ACC1:acc#346.itm(3)} {ACC1:acc#346.itm(4)} -attr xrf 53035 -attr oid 1091 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {conc#1054.itm(0)} -attr vt d
+load net {conc#1054.itm(1)} -attr vt d
+load net {conc#1054.itm(2)} -attr vt d
+load net {conc#1054.itm(3)} -attr vt d
+load netBundle {conc#1054.itm} 4 {conc#1054.itm(0)} {conc#1054.itm(1)} {conc#1054.itm(2)} {conc#1054.itm(3)} -attr xrf 53036 -attr oid 1092 -attr vt d -attr @path {/sobel/sobel:core/conc#1054.itm}
+load net {ACC1:slc#24.itm(0)} -attr vt d
+load net {ACC1:slc#24.itm(1)} -attr vt d
+load net {ACC1:slc#24.itm(2)} -attr vt d
+load netBundle {ACC1:slc#24.itm} 3 {ACC1:slc#24.itm(0)} {ACC1:slc#24.itm(1)} {ACC1:slc#24.itm(2)} -attr xrf 53037 -attr oid 1093 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#24.itm}
+load net {ACC1:acc#345.itm(0)} -attr vt d
+load net {ACC1:acc#345.itm(1)} -attr vt d
+load net {ACC1:acc#345.itm(2)} -attr vt d
+load net {ACC1:acc#345.itm(3)} -attr vt d
+load netBundle {ACC1:acc#345.itm} 4 {ACC1:acc#345.itm(0)} {ACC1:acc#345.itm(1)} {ACC1:acc#345.itm(2)} {ACC1:acc#345.itm(3)} -attr xrf 53038 -attr oid 1094 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#345.itm}
+load net {conc#1055.itm(0)} -attr vt d
+load net {conc#1055.itm(1)} -attr vt d
+load net {conc#1055.itm(2)} -attr vt d
+load net {conc#1055.itm(3)} -attr vt d
+load netBundle {conc#1055.itm} 4 {conc#1055.itm(0)} {conc#1055.itm(1)} {conc#1055.itm(2)} {conc#1055.itm(3)} -attr xrf 53039 -attr oid 1095 -attr vt d -attr @path {/sobel/sobel:core/conc#1055.itm}
+load net {ACC1:conc#1153.itm(0)} -attr vt d
+load net {ACC1:conc#1153.itm(1)} -attr vt d
+load net {ACC1:conc#1153.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1153.itm} 3 {ACC1:conc#1153.itm(0)} {ACC1:conc#1153.itm(1)} {ACC1:conc#1153.itm(2)} -attr xrf 53040 -attr oid 1096 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1153.itm}
+load net {ACC1:slc#22.itm(0)} -attr vt d
+load net {ACC1:slc#22.itm(1)} -attr vt d
+load netBundle {ACC1:slc#22.itm} 2 {ACC1:slc#22.itm(0)} {ACC1:slc#22.itm(1)} -attr xrf 53041 -attr oid 1097 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#22.itm}
+load net {ACC1:acc#343.itm(0)} -attr vt d
+load net {ACC1:acc#343.itm(1)} -attr vt d
+load net {ACC1:acc#343.itm(2)} -attr vt d
+load netBundle {ACC1:acc#343.itm} 3 {ACC1:acc#343.itm(0)} {ACC1:acc#343.itm(1)} {ACC1:acc#343.itm(2)} -attr xrf 53042 -attr oid 1098 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#343.itm}
+load net {conc#1056.itm(0)} -attr vt d
+load net {conc#1056.itm(1)} -attr vt d
+load netBundle {conc#1056.itm} 2 {conc#1056.itm(0)} {conc#1056.itm(1)} -attr xrf 53043 -attr oid 1099 -attr vt d -attr @path {/sobel/sobel:core/conc#1056.itm}
+load net {ACC1:conc#1149.itm(0)} -attr vt d
+load net {ACC1:conc#1149.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1149.itm} 2 {ACC1:conc#1149.itm(0)} {ACC1:conc#1149.itm(1)} -attr xrf 53044 -attr oid 1100 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1149.itm}
+load net {ACC1:conc#1155.itm(0)} -attr vt d
+load net {ACC1:conc#1155.itm(1)} -attr vt d
+load net {ACC1:conc#1155.itm(2)} -attr vt d
+load net {ACC1:conc#1155.itm(3)} -attr vt d
+load net {ACC1:conc#1155.itm(4)} -attr vt d
+load netBundle {ACC1:conc#1155.itm} 5 {ACC1:conc#1155.itm(0)} {ACC1:conc#1155.itm(1)} {ACC1:conc#1155.itm(2)} {ACC1:conc#1155.itm(3)} {ACC1:conc#1155.itm(4)} -attr xrf 53045 -attr oid 1101 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1155.itm}
+load net {ACC1:slc#23.itm(0)} -attr vt d
+load net {ACC1:slc#23.itm(1)} -attr vt d
+load net {ACC1:slc#23.itm(2)} -attr vt d
+load net {ACC1:slc#23.itm(3)} -attr vt d
+load netBundle {ACC1:slc#23.itm} 4 {ACC1:slc#23.itm(0)} {ACC1:slc#23.itm(1)} {ACC1:slc#23.itm(2)} {ACC1:slc#23.itm(3)} -attr xrf 53046 -attr oid 1102 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#23.itm}
+load net {ACC1:acc#344.itm(0)} -attr vt d
+load net {ACC1:acc#344.itm(1)} -attr vt d
+load net {ACC1:acc#344.itm(2)} -attr vt d
+load net {ACC1:acc#344.itm(3)} -attr vt d
+load net {ACC1:acc#344.itm(4)} -attr vt d
+load netBundle {ACC1:acc#344.itm} 5 {ACC1:acc#344.itm(0)} {ACC1:acc#344.itm(1)} {ACC1:acc#344.itm(2)} {ACC1:acc#344.itm(3)} {ACC1:acc#344.itm(4)} -attr xrf 53047 -attr oid 1103 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {conc#1057.itm(0)} -attr vt d
+load net {conc#1057.itm(1)} -attr vt d
+load net {conc#1057.itm(2)} -attr vt d
+load netBundle {conc#1057.itm} 3 {conc#1057.itm(0)} {conc#1057.itm(1)} {conc#1057.itm(2)} -attr xrf 53048 -attr oid 1104 -attr vt d -attr @path {/sobel/sobel:core/conc#1057.itm}
+load net {ACC1:slc#21.itm(0)} -attr vt d
+load net {ACC1:slc#21.itm(1)} -attr vt d
+load netBundle {ACC1:slc#21.itm} 2 {ACC1:slc#21.itm(0)} {ACC1:slc#21.itm(1)} -attr xrf 53049 -attr oid 1105 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#21.itm}
+load net {ACC1:acc#342.itm(0)} -attr vt d
+load net {ACC1:acc#342.itm(1)} -attr vt d
+load net {ACC1:acc#342.itm(2)} -attr vt d
+load netBundle {ACC1:acc#342.itm} 3 {ACC1:acc#342.itm(0)} {ACC1:acc#342.itm(1)} {ACC1:acc#342.itm(2)} -attr xrf 53050 -attr oid 1106 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {conc#1058.itm(0)} -attr vt d
+load net {conc#1058.itm(1)} -attr vt d
+load netBundle {conc#1058.itm} 2 {conc#1058.itm(0)} {conc#1058.itm(1)} -attr xrf 53051 -attr oid 1107 -attr vt d -attr @path {/sobel/sobel:core/conc#1058.itm}
+load net {ACC1:conc#1147.itm(0)} -attr vt d
+load net {ACC1:conc#1147.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1147.itm} 2 {ACC1:conc#1147.itm(0)} {ACC1:conc#1147.itm(1)} -attr xrf 53052 -attr oid 1108 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1147.itm}
+load net {ACC1:conc#1151.itm(0)} -attr vt d
+load net {ACC1:conc#1151.itm(1)} -attr vt d
+load net {ACC1:conc#1151.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1151.itm} 3 {ACC1:conc#1151.itm(0)} {ACC1:conc#1151.itm(1)} {ACC1:conc#1151.itm(2)} -attr xrf 53053 -attr oid 1109 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1151.itm}
+load net {ACC1-1:not#252.itm(0)} -attr vt d
+load net {ACC1-1:not#252.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#252.itm} 2 {ACC1-1:not#252.itm(0)} {ACC1-1:not#252.itm(1)} -attr xrf 53054 -attr oid 1110 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#252.itm}
+load net {slc(ACC1:acc#224.psp#1.sva)#12.itm(0)} -attr vt d
+load net {slc(ACC1:acc#224.psp#1.sva)#12.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#224.psp#1.sva)#12.itm} 2 {slc(ACC1:acc#224.psp#1.sva)#12.itm(0)} {slc(ACC1:acc#224.psp#1.sva)#12.itm(1)} -attr xrf 53055 -attr oid 1111 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#12.itm}
+load net {ACC1:acc#386.itm(0)} -attr vt d
+load net {ACC1:acc#386.itm(1)} -attr vt d
+load net {ACC1:acc#386.itm(2)} -attr vt d
+load net {ACC1:acc#386.itm(3)} -attr vt d
+load netBundle {ACC1:acc#386.itm} 4 {ACC1:acc#386.itm(0)} {ACC1:acc#386.itm(1)} {ACC1:acc#386.itm(2)} {ACC1:acc#386.itm(3)} -attr xrf 53056 -attr oid 1112 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#386.itm}
+load net {conc#1059.itm(0)} -attr vt d
+load net {conc#1059.itm(1)} -attr vt d
+load net {conc#1059.itm(2)} -attr vt d
+load netBundle {conc#1059.itm} 3 {conc#1059.itm(0)} {conc#1059.itm(1)} {conc#1059.itm(2)} -attr xrf 53057 -attr oid 1113 -attr vt d -attr @path {/sobel/sobel:core/conc#1059.itm}
+load net {ACC1-2:not#291.itm(0)} -attr vt d
+load net {ACC1-2:not#291.itm(1)} -attr vt d
+load netBundle {ACC1-2:not#291.itm} 2 {ACC1-2:not#291.itm(0)} {ACC1-2:not#291.itm(1)} -attr xrf 53058 -attr oid 1114 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#291.itm}
+load net {slc(ACC1:acc#219.psp#2.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#219.psp#2.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#219.psp#2.sva).itm} 2 {slc(ACC1:acc#219.psp#2.sva).itm(0)} {slc(ACC1:acc#219.psp#2.sva).itm(1)} -attr xrf 53059 -attr oid 1115 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#2.sva).itm}
+load net {conc#1060.itm(0)} -attr vt d
+load net {conc#1060.itm(1)} -attr vt d
+load netBundle {conc#1060.itm} 2 {conc#1060.itm(0)} {conc#1060.itm(1)} -attr xrf 53060 -attr oid 1116 -attr vt d -attr @path {/sobel/sobel:core/conc#1060.itm}
+load net {ACC1:acc#405.itm(0)} -attr vt d
+load net {ACC1:acc#405.itm(1)} -attr vt d
+load net {ACC1:acc#405.itm(2)} -attr vt d
+load net {ACC1:acc#405.itm(3)} -attr vt d
+load netBundle {ACC1:acc#405.itm} 4 {ACC1:acc#405.itm(0)} {ACC1:acc#405.itm(1)} {ACC1:acc#405.itm(2)} {ACC1:acc#405.itm(3)} -attr xrf 53061 -attr oid 1117 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#405.itm}
+load net {conc#1061.itm(0)} -attr vt d
+load net {conc#1061.itm(1)} -attr vt d
+load net {conc#1061.itm(2)} -attr vt d
+load netBundle {conc#1061.itm} 3 {conc#1061.itm(0)} {conc#1061.itm(1)} {conc#1061.itm(2)} -attr xrf 53062 -attr oid 1118 -attr vt d -attr @path {/sobel/sobel:core/conc#1061.itm}
+load net {ACC1-3:not#295.itm(0)} -attr vt d
+load net {ACC1-3:not#295.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#295.itm} 2 {ACC1-3:not#295.itm(0)} {ACC1-3:not#295.itm(1)} -attr xrf 53063 -attr oid 1119 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#295.itm}
+load net {slc(ACC1:acc#221.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#221.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#221.psp.sva).itm} 2 {slc(ACC1:acc#221.psp.sva).itm(0)} {slc(ACC1:acc#221.psp.sva).itm(1)} -attr xrf 53064 -attr oid 1120 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp.sva).itm}
+load net {conc#1062.itm(0)} -attr vt d
+load net {conc#1062.itm(1)} -attr vt d
+load netBundle {conc#1062.itm} 2 {conc#1062.itm(0)} {conc#1062.itm(1)} -attr xrf 53065 -attr oid 1121 -attr vt d -attr @path {/sobel/sobel:core/conc#1062.itm}
+load net {ACC1:slc#74.itm(0)} -attr vt d
+load net {ACC1:slc#74.itm(1)} -attr vt d
+load netBundle {ACC1:slc#74.itm} 2 {ACC1:slc#74.itm(0)} {ACC1:slc#74.itm(1)} -attr xrf 53066 -attr oid 1122 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:acc#404.itm(0)} -attr vt d
+load net {ACC1:acc#404.itm(1)} -attr vt d
+load net {ACC1:acc#404.itm(2)} -attr vt d
+load netBundle {ACC1:acc#404.itm} 3 {ACC1:acc#404.itm(0)} {ACC1:acc#404.itm(1)} {ACC1:acc#404.itm(2)} -attr xrf 53067 -attr oid 1123 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#404.itm}
+load net {conc#1063.itm(0)} -attr vt d
+load net {conc#1063.itm(1)} -attr vt d
+load netBundle {conc#1063.itm} 2 {conc#1063.itm(0)} {conc#1063.itm(1)} -attr xrf 53068 -attr oid 1124 -attr vt d -attr @path {/sobel/sobel:core/conc#1063.itm}
+load net {ACC1:conc#1265.itm(0)} -attr vt d
+load net {ACC1:conc#1265.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1265.itm} 2 {ACC1:conc#1265.itm(0)} {ACC1:conc#1265.itm(1)} -attr xrf 53069 -attr oid 1125 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1265.itm}
+load net {ACC1:slc#50.itm(0)} -attr vt d
+load net {ACC1:slc#50.itm(1)} -attr vt d
+load netBundle {ACC1:slc#50.itm} 2 {ACC1:slc#50.itm(0)} {ACC1:slc#50.itm(1)} -attr xrf 53070 -attr oid 1126 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#376.itm(0)} -attr vt d
+load net {ACC1:acc#376.itm(1)} -attr vt d
+load net {ACC1:acc#376.itm(2)} -attr vt d
+load netBundle {ACC1:acc#376.itm} 3 {ACC1:acc#376.itm(0)} {ACC1:acc#376.itm(1)} {ACC1:acc#376.itm(2)} -attr xrf 53071 -attr oid 1127 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#376.itm}
+load net {conc#1064.itm(0)} -attr vt d
+load net {conc#1064.itm(1)} -attr vt d
+load netBundle {conc#1064.itm} 2 {conc#1064.itm(0)} {conc#1064.itm(1)} -attr xrf 53072 -attr oid 1128 -attr vt d -attr @path {/sobel/sobel:core/conc#1064.itm}
+load net {ACC1:conc#1211.itm(0)} -attr vt d
+load net {ACC1:conc#1211.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1211.itm} 2 {ACC1:conc#1211.itm(0)} {ACC1:conc#1211.itm(1)} -attr xrf 53073 -attr oid 1129 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1211.itm}
+load net {ACC1:slc#58.itm(0)} -attr vt d
+load net {ACC1:slc#58.itm(1)} -attr vt d
+load netBundle {ACC1:slc#58.itm} 2 {ACC1:slc#58.itm(0)} {ACC1:slc#58.itm(1)} -attr xrf 53074 -attr oid 1130 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:acc#385.itm(0)} -attr vt d
+load net {ACC1:acc#385.itm(1)} -attr vt d
+load net {ACC1:acc#385.itm(2)} -attr vt d
+load netBundle {ACC1:acc#385.itm} 3 {ACC1:acc#385.itm(0)} {ACC1:acc#385.itm(1)} {ACC1:acc#385.itm(2)} -attr xrf 53075 -attr oid 1131 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#385.itm}
+load net {conc#1065.itm(0)} -attr vt d
+load net {conc#1065.itm(1)} -attr vt d
+load netBundle {conc#1065.itm} 2 {conc#1065.itm(0)} {conc#1065.itm(1)} -attr xrf 53076 -attr oid 1132 -attr vt d -attr @path {/sobel/sobel:core/conc#1065.itm}
+load net {ACC1:conc#1229.itm(0)} -attr vt d
+load net {ACC1:conc#1229.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1229.itm} 2 {ACC1:conc#1229.itm(0)} {ACC1:conc#1229.itm(1)} -attr xrf 53077 -attr oid 1133 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1229.itm}
+load net {ACC1:slc#26.itm(0)} -attr vt d
+load net {ACC1:slc#26.itm(1)} -attr vt d
+load netBundle {ACC1:slc#26.itm} 2 {ACC1:slc#26.itm(0)} {ACC1:slc#26.itm(1)} -attr xrf 53078 -attr oid 1134 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#347.itm(0)} -attr vt d
+load net {ACC1:acc#347.itm(1)} -attr vt d
+load net {ACC1:acc#347.itm(2)} -attr vt d
+load netBundle {ACC1:acc#347.itm} 3 {ACC1:acc#347.itm(0)} {ACC1:acc#347.itm(1)} {ACC1:acc#347.itm(2)} -attr xrf 53079 -attr oid 1135 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load net {conc#1066.itm(0)} -attr vt d
+load net {conc#1066.itm(1)} -attr vt d
+load netBundle {conc#1066.itm} 2 {conc#1066.itm(0)} {conc#1066.itm(1)} -attr xrf 53080 -attr oid 1136 -attr vt d -attr @path {/sobel/sobel:core/conc#1066.itm}
+load net {ACC1:conc#1157.itm(0)} -attr vt d
+load net {ACC1:conc#1157.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1157.itm} 2 {ACC1:conc#1157.itm(0)} {ACC1:conc#1157.itm(1)} -attr xrf 53081 -attr oid 1137 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1157.itm}
+load net {ACC1:slc#42.itm(0)} -attr vt d
+load net {ACC1:slc#42.itm(1)} -attr vt d
+load netBundle {ACC1:slc#42.itm} 2 {ACC1:slc#42.itm(0)} {ACC1:slc#42.itm(1)} -attr xrf 53082 -attr oid 1138 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#42.itm}
+load net {ACC1:acc#366.itm(0)} -attr vt d
+load net {ACC1:acc#366.itm(1)} -attr vt d
+load net {ACC1:acc#366.itm(2)} -attr vt d
+load netBundle {ACC1:acc#366.itm} 3 {ACC1:acc#366.itm(0)} {ACC1:acc#366.itm(1)} {ACC1:acc#366.itm(2)} -attr xrf 53083 -attr oid 1139 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#366.itm}
+load net {conc#1067.itm(0)} -attr vt d
+load net {conc#1067.itm(1)} -attr vt d
+load netBundle {conc#1067.itm} 2 {conc#1067.itm(0)} {conc#1067.itm(1)} -attr xrf 53084 -attr oid 1140 -attr vt d -attr @path {/sobel/sobel:core/conc#1067.itm}
+load net {ACC1:conc#1193.itm(0)} -attr vt d
+load net {ACC1:conc#1193.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1193.itm} 2 {ACC1:conc#1193.itm(0)} {ACC1:conc#1193.itm(1)} -attr xrf 53085 -attr oid 1141 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1193.itm}
+load net {ACC1:acc#387.itm(0)} -attr vt d
+load net {ACC1:acc#387.itm(1)} -attr vt d
+load net {ACC1:acc#387.itm(2)} -attr vt d
+load netBundle {ACC1:acc#387.itm} 3 {ACC1:acc#387.itm(0)} {ACC1:acc#387.itm(1)} {ACC1:acc#387.itm(2)} -attr xrf 53086 -attr oid 1142 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#387.itm}
+load net {conc#1068.itm(0)} -attr vt d
+load net {conc#1068.itm(1)} -attr vt d
+load net {conc#1068.itm(2)} -attr vt d
+load netBundle {conc#1068.itm} 3 {conc#1068.itm(0)} {conc#1068.itm(1)} {conc#1068.itm(2)} -attr xrf 53087 -attr oid 1143 -attr vt d -attr @path {/sobel/sobel:core/conc#1068.itm}
+load net {ACC1:conc#1234.itm(0)} -attr vt d
+load net {ACC1:conc#1234.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1234.itm} 2 {ACC1:conc#1234.itm(0)} {ACC1:conc#1234.itm(1)} -attr xrf 53088 -attr oid 1144 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1234.itm}
+load net {ACC1:acc#378.itm(0)} -attr vt d
+load net {ACC1:acc#378.itm(1)} -attr vt d
+load net {ACC1:acc#378.itm(2)} -attr vt d
+load netBundle {ACC1:acc#378.itm} 3 {ACC1:acc#378.itm(0)} {ACC1:acc#378.itm(1)} {ACC1:acc#378.itm(2)} -attr xrf 53089 -attr oid 1145 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#378.itm}
+load net {conc#1069.itm(0)} -attr vt d
+load net {conc#1069.itm(1)} -attr vt d
+load net {conc#1069.itm(2)} -attr vt d
+load netBundle {conc#1069.itm} 3 {conc#1069.itm(0)} {conc#1069.itm(1)} {conc#1069.itm(2)} -attr xrf 53090 -attr oid 1146 -attr vt d -attr @path {/sobel/sobel:core/conc#1069.itm}
+load net {ACC1:conc#1216.itm(0)} -attr vt d
+load net {ACC1:conc#1216.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1216.itm} 2 {ACC1:conc#1216.itm(0)} {ACC1:conc#1216.itm(1)} -attr xrf 53091 -attr oid 1147 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1216.itm}
+load net {ACC1:acc#415.itm(0)} -attr vt d
+load net {ACC1:acc#415.itm(1)} -attr vt d
+load net {ACC1:acc#415.itm(2)} -attr vt d
+load netBundle {ACC1:acc#415.itm} 3 {ACC1:acc#415.itm(0)} {ACC1:acc#415.itm(1)} {ACC1:acc#415.itm(2)} -attr xrf 53092 -attr oid 1148 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#415.itm}
+load net {conc#1070.itm(0)} -attr vt d
+load net {conc#1070.itm(1)} -attr vt d
+load net {conc#1070.itm(2)} -attr vt d
+load netBundle {conc#1070.itm} 3 {conc#1070.itm(0)} {conc#1070.itm(1)} {conc#1070.itm(2)} -attr xrf 53093 -attr oid 1149 -attr vt d -attr @path {/sobel/sobel:core/conc#1070.itm}
+load net {ACC1:conc#1288.itm(0)} -attr vt d
+load net {ACC1:conc#1288.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1288.itm} 2 {ACC1:conc#1288.itm(0)} {ACC1:conc#1288.itm(1)} -attr xrf 53094 -attr oid 1150 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1288.itm}
+load net {ACC1:acc#396.itm(0)} -attr vt d
+load net {ACC1:acc#396.itm(1)} -attr vt d
+load net {ACC1:acc#396.itm(2)} -attr vt d
+load netBundle {ACC1:acc#396.itm} 3 {ACC1:acc#396.itm(0)} {ACC1:acc#396.itm(1)} {ACC1:acc#396.itm(2)} -attr xrf 53095 -attr oid 1151 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#396.itm}
+load net {conc#1071.itm(0)} -attr vt d
+load net {conc#1071.itm(1)} -attr vt d
+load net {conc#1071.itm(2)} -attr vt d
+load netBundle {conc#1071.itm} 3 {conc#1071.itm(0)} {conc#1071.itm(1)} {conc#1071.itm(2)} -attr xrf 53096 -attr oid 1152 -attr vt d -attr @path {/sobel/sobel:core/conc#1071.itm}
+load net {ACC1:conc#1252.itm(0)} -attr vt d
+load net {ACC1:conc#1252.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1252.itm} 2 {ACC1:conc#1252.itm(0)} {ACC1:conc#1252.itm(1)} -attr xrf 53097 -attr oid 1153 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1252.itm}
+load net {ACC1:slc#65.itm(0)} -attr vt d
+load net {ACC1:slc#65.itm(1)} -attr vt d
+load net {ACC1:slc#65.itm(2)} -attr vt d
+load net {ACC1:slc#65.itm(3)} -attr vt d
+load netBundle {ACC1:slc#65.itm} 4 {ACC1:slc#65.itm(0)} {ACC1:slc#65.itm(1)} {ACC1:slc#65.itm(2)} {ACC1:slc#65.itm(3)} -attr xrf 53098 -attr oid 1154 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#393.itm(0)} -attr vt d
+load net {ACC1:acc#393.itm(1)} -attr vt d
+load net {ACC1:acc#393.itm(2)} -attr vt d
+load net {ACC1:acc#393.itm(3)} -attr vt d
+load net {ACC1:acc#393.itm(4)} -attr vt d
+load netBundle {ACC1:acc#393.itm} 5 {ACC1:acc#393.itm(0)} {ACC1:acc#393.itm(1)} {ACC1:acc#393.itm(2)} {ACC1:acc#393.itm(3)} {ACC1:acc#393.itm(4)} -attr xrf 53099 -attr oid 1155 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393.itm}
+load net {conc#1072.itm(0)} -attr vt d
+load net {conc#1072.itm(1)} -attr vt d
+load net {conc#1072.itm(2)} -attr vt d
+load net {conc#1072.itm(3)} -attr vt d
+load netBundle {conc#1072.itm} 4 {conc#1072.itm(0)} {conc#1072.itm(1)} {conc#1072.itm(2)} {conc#1072.itm(3)} -attr xrf 53100 -attr oid 1156 -attr vt d -attr @path {/sobel/sobel:core/conc#1072.itm}
+load net {ACC1:slc#63.itm(0)} -attr vt d
+load net {ACC1:slc#63.itm(1)} -attr vt d
+load net {ACC1:slc#63.itm(2)} -attr vt d
+load netBundle {ACC1:slc#63.itm} 3 {ACC1:slc#63.itm(0)} {ACC1:slc#63.itm(1)} {ACC1:slc#63.itm(2)} -attr xrf 53101 -attr oid 1157 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#63.itm}
+load net {ACC1:acc#391.itm(0)} -attr vt d
+load net {ACC1:acc#391.itm(1)} -attr vt d
+load net {ACC1:acc#391.itm(2)} -attr vt d
+load net {ACC1:acc#391.itm(3)} -attr vt d
+load netBundle {ACC1:acc#391.itm} 4 {ACC1:acc#391.itm(0)} {ACC1:acc#391.itm(1)} {ACC1:acc#391.itm(2)} {ACC1:acc#391.itm(3)} -attr xrf 53102 -attr oid 1158 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#391.itm}
+load net {conc#1073.itm(0)} -attr vt d
+load net {conc#1073.itm(1)} -attr vt d
+load netBundle {conc#1073.itm} 2 {conc#1073.itm(0)} {conc#1073.itm(1)} -attr xrf 53103 -attr oid 1159 -attr vt d -attr @path {/sobel/sobel:core/conc#1073.itm}
+load net {ACC1:conc#1241.itm(0)} -attr vt d
+load net {ACC1:conc#1241.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1241.itm} 2 {ACC1:conc#1241.itm(0)} {ACC1:conc#1241.itm(1)} -attr xrf 53104 -attr oid 1160 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1241.itm}
+load net {conc#1074.itm(0)} -attr vt d
+load net {conc#1074.itm(1)} -attr vt d
+load net {conc#1074.itm(2)} -attr vt d
+load net {conc#1074.itm(3)} -attr vt d
+load netBundle {conc#1074.itm} 4 {conc#1074.itm(0)} {conc#1074.itm(1)} {conc#1074.itm(2)} {conc#1074.itm(3)} -attr xrf 53105 -attr oid 1161 -attr vt d -attr @path {/sobel/sobel:core/conc#1074.itm}
+load net {ACC1:slc#64.itm(0)} -attr vt d
+load net {ACC1:slc#64.itm(1)} -attr vt d
+load net {ACC1:slc#64.itm(2)} -attr vt d
+load netBundle {ACC1:slc#64.itm} 3 {ACC1:slc#64.itm(0)} {ACC1:slc#64.itm(1)} {ACC1:slc#64.itm(2)} -attr xrf 53106 -attr oid 1162 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#392.itm(0)} -attr vt d
+load net {ACC1:acc#392.itm(1)} -attr vt d
+load net {ACC1:acc#392.itm(2)} -attr vt d
+load net {ACC1:acc#392.itm(3)} -attr vt d
+load netBundle {ACC1:acc#392.itm} 4 {ACC1:acc#392.itm(0)} {ACC1:acc#392.itm(1)} {ACC1:acc#392.itm(2)} {ACC1:acc#392.itm(3)} -attr xrf 53107 -attr oid 1163 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#392.itm}
+load net {conc#1075.itm(0)} -attr vt d
+load net {conc#1075.itm(1)} -attr vt d
+load net {conc#1075.itm(2)} -attr vt d
+load netBundle {conc#1075.itm} 3 {conc#1075.itm(0)} {conc#1075.itm(1)} {conc#1075.itm(2)} -attr xrf 53108 -attr oid 1164 -attr vt d -attr @path {/sobel/sobel:core/conc#1075.itm}
+load net {ACC1:slc#62.itm(0)} -attr vt d
+load net {ACC1:slc#62.itm(1)} -attr vt d
+load netBundle {ACC1:slc#62.itm} 2 {ACC1:slc#62.itm(0)} {ACC1:slc#62.itm(1)} -attr xrf 53109 -attr oid 1165 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#62.itm}
+load net {ACC1:acc#390.itm(0)} -attr vt d
+load net {ACC1:acc#390.itm(1)} -attr vt d
+load net {ACC1:acc#390.itm(2)} -attr vt d
+load netBundle {ACC1:acc#390.itm} 3 {ACC1:acc#390.itm(0)} {ACC1:acc#390.itm(1)} {ACC1:acc#390.itm(2)} -attr xrf 53110 -attr oid 1166 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#390.itm}
+load net {conc#1076.itm(0)} -attr vt d
+load net {conc#1076.itm(1)} -attr vt d
+load netBundle {conc#1076.itm} 2 {conc#1076.itm(0)} {conc#1076.itm(1)} -attr xrf 53111 -attr oid 1167 -attr vt d -attr @path {/sobel/sobel:core/conc#1076.itm}
+load net {ACC1:conc#1239.itm(0)} -attr vt d
+load net {ACC1:conc#1239.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1239.itm} 2 {ACC1:conc#1239.itm(0)} {ACC1:conc#1239.itm(1)} -attr xrf 53112 -attr oid 1168 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1239.itm}
+load net {ACC1:conc#1243.itm(0)} -attr vt d
+load net {ACC1:conc#1243.itm(1)} -attr vt d
+load net {ACC1:conc#1243.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1243.itm} 3 {ACC1:conc#1243.itm(0)} {ACC1:conc#1243.itm(1)} {ACC1:conc#1243.itm(2)} -attr xrf 53113 -attr oid 1169 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1243.itm}
+load net {ACC1:slc#61.itm(0)} -attr vt d
+load net {ACC1:slc#61.itm(1)} -attr vt d
+load netBundle {ACC1:slc#61.itm} 2 {ACC1:slc#61.itm(0)} {ACC1:slc#61.itm(1)} -attr xrf 53114 -attr oid 1170 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#61.itm}
+load net {ACC1:acc#389.itm(0)} -attr vt d
+load net {ACC1:acc#389.itm(1)} -attr vt d
+load net {ACC1:acc#389.itm(2)} -attr vt d
+load netBundle {ACC1:acc#389.itm} 3 {ACC1:acc#389.itm(0)} {ACC1:acc#389.itm(1)} {ACC1:acc#389.itm(2)} -attr xrf 53115 -attr oid 1171 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#389.itm}
+load net {conc#1077.itm(0)} -attr vt d
+load net {conc#1077.itm(1)} -attr vt d
+load netBundle {conc#1077.itm} 2 {conc#1077.itm(0)} {conc#1077.itm(1)} -attr xrf 53116 -attr oid 1172 -attr vt d -attr @path {/sobel/sobel:core/conc#1077.itm}
+load net {ACC1:conc#1237.itm(0)} -attr vt d
+load net {ACC1:conc#1237.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1237.itm} 2 {ACC1:conc#1237.itm(0)} {ACC1:conc#1237.itm(1)} -attr xrf 53117 -attr oid 1173 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1237.itm}
+load net {ACC1:slc#89.itm(0)} -attr vt d
+load net {ACC1:slc#89.itm(1)} -attr vt d
+load net {ACC1:slc#89.itm(2)} -attr vt d
+load net {ACC1:slc#89.itm(3)} -attr vt d
+load netBundle {ACC1:slc#89.itm} 4 {ACC1:slc#89.itm(0)} {ACC1:slc#89.itm(1)} {ACC1:slc#89.itm(2)} {ACC1:slc#89.itm(3)} -attr xrf 53118 -attr oid 1174 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#421.itm(0)} -attr vt d
+load net {ACC1:acc#421.itm(1)} -attr vt d
+load net {ACC1:acc#421.itm(2)} -attr vt d
+load net {ACC1:acc#421.itm(3)} -attr vt d
+load net {ACC1:acc#421.itm(4)} -attr vt d
+load netBundle {ACC1:acc#421.itm} 5 {ACC1:acc#421.itm(0)} {ACC1:acc#421.itm(1)} {ACC1:acc#421.itm(2)} {ACC1:acc#421.itm(3)} {ACC1:acc#421.itm(4)} -attr xrf 53119 -attr oid 1175 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421.itm}
+load net {conc#1078.itm(0)} -attr vt d
+load net {conc#1078.itm(1)} -attr vt d
+load net {conc#1078.itm(2)} -attr vt d
+load net {conc#1078.itm(3)} -attr vt d
+load netBundle {conc#1078.itm} 4 {conc#1078.itm(0)} {conc#1078.itm(1)} {conc#1078.itm(2)} {conc#1078.itm(3)} -attr xrf 53120 -attr oid 1176 -attr vt d -attr @path {/sobel/sobel:core/conc#1078.itm}
+load net {ACC1:slc#87.itm(0)} -attr vt d
+load net {ACC1:slc#87.itm(1)} -attr vt d
+load net {ACC1:slc#87.itm(2)} -attr vt d
+load netBundle {ACC1:slc#87.itm} 3 {ACC1:slc#87.itm(0)} {ACC1:slc#87.itm(1)} {ACC1:slc#87.itm(2)} -attr xrf 53121 -attr oid 1177 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#87.itm}
+load net {ACC1:acc#419.itm(0)} -attr vt d
+load net {ACC1:acc#419.itm(1)} -attr vt d
+load net {ACC1:acc#419.itm(2)} -attr vt d
+load net {ACC1:acc#419.itm(3)} -attr vt d
+load netBundle {ACC1:acc#419.itm} 4 {ACC1:acc#419.itm(0)} {ACC1:acc#419.itm(1)} {ACC1:acc#419.itm(2)} {ACC1:acc#419.itm(3)} -attr xrf 53122 -attr oid 1178 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#419.itm}
+load net {conc#1079.itm(0)} -attr vt d
+load net {conc#1079.itm(1)} -attr vt d
+load netBundle {conc#1079.itm} 2 {conc#1079.itm(0)} {conc#1079.itm(1)} -attr xrf 53123 -attr oid 1179 -attr vt d -attr @path {/sobel/sobel:core/conc#1079.itm}
+load net {ACC1:conc#1295.itm(0)} -attr vt d
+load net {ACC1:conc#1295.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1295.itm} 2 {ACC1:conc#1295.itm(0)} {ACC1:conc#1295.itm(1)} -attr xrf 53124 -attr oid 1180 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1295.itm}
+load net {conc#1080.itm(0)} -attr vt d
+load net {conc#1080.itm(1)} -attr vt d
+load net {conc#1080.itm(2)} -attr vt d
+load net {conc#1080.itm(3)} -attr vt d
+load netBundle {conc#1080.itm} 4 {conc#1080.itm(0)} {conc#1080.itm(1)} {conc#1080.itm(2)} {conc#1080.itm(3)} -attr xrf 53125 -attr oid 1181 -attr vt d -attr @path {/sobel/sobel:core/conc#1080.itm}
+load net {ACC1:slc#88.itm(0)} -attr vt d
+load net {ACC1:slc#88.itm(1)} -attr vt d
+load net {ACC1:slc#88.itm(2)} -attr vt d
+load netBundle {ACC1:slc#88.itm} 3 {ACC1:slc#88.itm(0)} {ACC1:slc#88.itm(1)} {ACC1:slc#88.itm(2)} -attr xrf 53126 -attr oid 1182 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#420.itm(0)} -attr vt d
+load net {ACC1:acc#420.itm(1)} -attr vt d
+load net {ACC1:acc#420.itm(2)} -attr vt d
+load net {ACC1:acc#420.itm(3)} -attr vt d
+load netBundle {ACC1:acc#420.itm} 4 {ACC1:acc#420.itm(0)} {ACC1:acc#420.itm(1)} {ACC1:acc#420.itm(2)} {ACC1:acc#420.itm(3)} -attr xrf 53127 -attr oid 1183 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#420.itm}
+load net {conc#1081.itm(0)} -attr vt d
+load net {conc#1081.itm(1)} -attr vt d
+load net {conc#1081.itm(2)} -attr vt d
+load netBundle {conc#1081.itm} 3 {conc#1081.itm(0)} {conc#1081.itm(1)} {conc#1081.itm(2)} -attr xrf 53128 -attr oid 1184 -attr vt d -attr @path {/sobel/sobel:core/conc#1081.itm}
+load net {ACC1:slc#86.itm(0)} -attr vt d
+load net {ACC1:slc#86.itm(1)} -attr vt d
+load netBundle {ACC1:slc#86.itm} 2 {ACC1:slc#86.itm(0)} {ACC1:slc#86.itm(1)} -attr xrf 53129 -attr oid 1185 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#86.itm}
+load net {ACC1:acc#418.itm(0)} -attr vt d
+load net {ACC1:acc#418.itm(1)} -attr vt d
+load net {ACC1:acc#418.itm(2)} -attr vt d
+load netBundle {ACC1:acc#418.itm} 3 {ACC1:acc#418.itm(0)} {ACC1:acc#418.itm(1)} {ACC1:acc#418.itm(2)} -attr xrf 53130 -attr oid 1186 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#418.itm}
+load net {conc#1082.itm(0)} -attr vt d
+load net {conc#1082.itm(1)} -attr vt d
+load netBundle {conc#1082.itm} 2 {conc#1082.itm(0)} {conc#1082.itm(1)} -attr xrf 53131 -attr oid 1187 -attr vt d -attr @path {/sobel/sobel:core/conc#1082.itm}
+load net {ACC1:conc#1293.itm(0)} -attr vt d
+load net {ACC1:conc#1293.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1293.itm} 2 {ACC1:conc#1293.itm(0)} {ACC1:conc#1293.itm(1)} -attr xrf 53132 -attr oid 1188 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1293.itm}
+load net {ACC1:conc#1297.itm(0)} -attr vt d
+load net {ACC1:conc#1297.itm(1)} -attr vt d
+load net {ACC1:conc#1297.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1297.itm} 3 {ACC1:conc#1297.itm(0)} {ACC1:conc#1297.itm(1)} {ACC1:conc#1297.itm(2)} -attr xrf 53133 -attr oid 1189 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1297.itm}
+load net {ACC1:slc#85.itm(0)} -attr vt d
+load net {ACC1:slc#85.itm(1)} -attr vt d
+load netBundle {ACC1:slc#85.itm} 2 {ACC1:slc#85.itm(0)} {ACC1:slc#85.itm(1)} -attr xrf 53134 -attr oid 1190 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#85.itm}
+load net {ACC1:acc#417.itm(0)} -attr vt d
+load net {ACC1:acc#417.itm(1)} -attr vt d
+load net {ACC1:acc#417.itm(2)} -attr vt d
+load netBundle {ACC1:acc#417.itm} 3 {ACC1:acc#417.itm(0)} {ACC1:acc#417.itm(1)} {ACC1:acc#417.itm(2)} -attr xrf 53135 -attr oid 1191 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#417.itm}
+load net {conc#1083.itm(0)} -attr vt d
+load net {conc#1083.itm(1)} -attr vt d
+load netBundle {conc#1083.itm} 2 {conc#1083.itm(0)} {conc#1083.itm(1)} -attr xrf 53136 -attr oid 1192 -attr vt d -attr @path {/sobel/sobel:core/conc#1083.itm}
+load net {ACC1:conc#1291.itm(0)} -attr vt d
+load net {ACC1:conc#1291.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1291.itm} 2 {ACC1:conc#1291.itm(0)} {ACC1:conc#1291.itm(1)} -attr xrf 53137 -attr oid 1193 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1291.itm}
+load net {ACC1:acc#424.itm(0)} -attr vt d
+load net {ACC1:acc#424.itm(1)} -attr vt d
+load net {ACC1:acc#424.itm(2)} -attr vt d
+load netBundle {ACC1:acc#424.itm} 3 {ACC1:acc#424.itm(0)} {ACC1:acc#424.itm(1)} {ACC1:acc#424.itm(2)} -attr xrf 53138 -attr oid 1194 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#424.itm}
+load net {conc#1084.itm(0)} -attr vt d
+load net {conc#1084.itm(1)} -attr vt d
+load net {conc#1084.itm(2)} -attr vt d
+load netBundle {conc#1084.itm} 3 {conc#1084.itm(0)} {conc#1084.itm(1)} {conc#1084.itm(2)} -attr xrf 53139 -attr oid 1195 -attr vt d -attr @path {/sobel/sobel:core/conc#1084.itm}
+load net {ACC1:conc#1306.itm(0)} -attr vt d
+load net {ACC1:conc#1306.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1306.itm} 2 {ACC1:conc#1306.itm(0)} {ACC1:conc#1306.itm(1)} -attr xrf 53140 -attr oid 1196 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1306.itm}
+load net {ACC1:exs#1650.itm(0)} -attr vt d
+load net {ACC1:exs#1650.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1650.itm} 2 {ACC1:exs#1650.itm(0)} {ACC1:exs#1650.itm(1)} -attr xrf 53141 -attr oid 1197 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1650.itm}
+load net {ACC1:exs#1607.itm(0)} -attr vt d
+load net {ACC1:exs#1607.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1607.itm} 2 {ACC1:exs#1607.itm(0)} {ACC1:exs#1607.itm(1)} -attr xrf 53142 -attr oid 1198 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1607.itm}
+load net {ACC1:acc#318.itm(0)} -attr vt d
+load net {ACC1:acc#318.itm(1)} -attr vt d
+load netBundle {ACC1:acc#318.itm} 2 {ACC1:acc#318.itm(0)} {ACC1:acc#318.itm(1)} -attr xrf 53143 -attr oid 1199 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#319.itm(0)} -attr vt d
+load net {ACC1:acc#319.itm(1)} -attr vt d
+load netBundle {ACC1:acc#319.itm} 2 {ACC1:acc#319.itm(0)} {ACC1:acc#319.itm(1)} -attr xrf 53144 -attr oid 1200 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:slc#90.itm(0)} -attr vt d
+load net {ACC1:slc#90.itm(1)} -attr vt d
+load netBundle {ACC1:slc#90.itm} 2 {ACC1:slc#90.itm(0)} {ACC1:slc#90.itm(1)} -attr xrf 53145 -attr oid 1201 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1:acc#422.itm(0)} -attr vt d
+load net {ACC1:acc#422.itm(1)} -attr vt d
+load net {ACC1:acc#422.itm(2)} -attr vt d
+load netBundle {ACC1:acc#422.itm} 3 {ACC1:acc#422.itm(0)} {ACC1:acc#422.itm(1)} {ACC1:acc#422.itm(2)} -attr xrf 53146 -attr oid 1202 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#422.itm}
+load net {conc#1085.itm(0)} -attr vt d
+load net {conc#1085.itm(1)} -attr vt d
+load netBundle {conc#1085.itm} 2 {conc#1085.itm(0)} {conc#1085.itm(1)} -attr xrf 53147 -attr oid 1203 -attr vt d -attr @path {/sobel/sobel:core/conc#1085.itm}
+load net {ACC1:conc#1301.itm(0)} -attr vt d
+load net {ACC1:conc#1301.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1301.itm} 2 {ACC1:conc#1301.itm(0)} {ACC1:conc#1301.itm(1)} -attr xrf 53148 -attr oid 1204 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1301.itm}
+load net {ACC1:slc#18.itm(0)} -attr vt d
+load net {ACC1:slc#18.itm(1)} -attr vt d
+load netBundle {ACC1:slc#18.itm} 2 {ACC1:slc#18.itm(0)} {ACC1:slc#18.itm(1)} -attr xrf 53149 -attr oid 1205 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#18.itm}
+load net {ACC1:acc#337.itm(0)} -attr vt d
+load net {ACC1:acc#337.itm(1)} -attr vt d
+load net {ACC1:acc#337.itm(2)} -attr vt d
+load netBundle {ACC1:acc#337.itm} 3 {ACC1:acc#337.itm(0)} {ACC1:acc#337.itm(1)} {ACC1:acc#337.itm(2)} -attr xrf 53150 -attr oid 1206 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {conc#1086.itm(0)} -attr vt d
+load net {conc#1086.itm(1)} -attr vt d
+load netBundle {conc#1086.itm} 2 {conc#1086.itm(0)} {conc#1086.itm(1)} -attr xrf 53151 -attr oid 1207 -attr vt d -attr @path {/sobel/sobel:core/conc#1086.itm}
+load net {ACC1:conc#1139.itm(0)} -attr vt d
+load net {ACC1:conc#1139.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1139.itm} 2 {ACC1:conc#1139.itm(0)} {ACC1:conc#1139.itm(1)} -attr xrf 53152 -attr oid 1208 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1139.itm}
+load net {ACC1:slc#66.itm(0)} -attr vt d
+load net {ACC1:slc#66.itm(1)} -attr vt d
+load netBundle {ACC1:slc#66.itm} 2 {ACC1:slc#66.itm(0)} {ACC1:slc#66.itm(1)} -attr xrf 53153 -attr oid 1209 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1:acc#394.itm(0)} -attr vt d
+load net {ACC1:acc#394.itm(1)} -attr vt d
+load net {ACC1:acc#394.itm(2)} -attr vt d
+load netBundle {ACC1:acc#394.itm} 3 {ACC1:acc#394.itm(0)} {ACC1:acc#394.itm(1)} {ACC1:acc#394.itm(2)} -attr xrf 53154 -attr oid 1210 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#394.itm}
+load net {conc#1087.itm(0)} -attr vt d
+load net {conc#1087.itm(1)} -attr vt d
+load netBundle {conc#1087.itm} 2 {conc#1087.itm(0)} {conc#1087.itm(1)} -attr xrf 53155 -attr oid 1211 -attr vt d -attr @path {/sobel/sobel:core/conc#1087.itm}
+load net {ACC1:conc#1247.itm(0)} -attr vt d
+load net {ACC1:conc#1247.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1247.itm} 2 {ACC1:conc#1247.itm(0)} {ACC1:conc#1247.itm(1)} -attr xrf 53156 -attr oid 1212 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1247.itm}
+load net {ACC1:slc#82.itm(0)} -attr vt d
+load net {ACC1:slc#82.itm(1)} -attr vt d
+load netBundle {ACC1:slc#82.itm} 2 {ACC1:slc#82.itm(0)} {ACC1:slc#82.itm(1)} -attr xrf 53157 -attr oid 1213 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#82.itm}
+load net {ACC1:acc#413.itm(0)} -attr vt d
+load net {ACC1:acc#413.itm(1)} -attr vt d
+load net {ACC1:acc#413.itm(2)} -attr vt d
+load netBundle {ACC1:acc#413.itm} 3 {ACC1:acc#413.itm(0)} {ACC1:acc#413.itm(1)} {ACC1:acc#413.itm(2)} -attr xrf 53158 -attr oid 1214 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#413.itm}
+load net {conc#1088.itm(0)} -attr vt d
+load net {conc#1088.itm(1)} -attr vt d
+load netBundle {conc#1088.itm} 2 {conc#1088.itm(0)} {conc#1088.itm(1)} -attr xrf 53159 -attr oid 1215 -attr vt d -attr @path {/sobel/sobel:core/conc#1088.itm}
+load net {ACC1:conc#1283.itm(0)} -attr vt d
+load net {ACC1:conc#1283.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1283.itm} 2 {ACC1:conc#1283.itm(0)} {ACC1:conc#1283.itm(1)} -attr xrf 53160 -attr oid 1216 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1283.itm}
+load net {ACC1:exs#1641.itm(0)} -attr vt d
+load net {ACC1:exs#1641.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1641.itm} 2 {ACC1:exs#1641.itm(0)} {ACC1:exs#1641.itm(1)} -attr xrf 53161 -attr oid 1217 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1641.itm}
+load net {ACC1:exs#1599.itm(0)} -attr vt d
+load net {ACC1:exs#1599.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1599.itm} 2 {ACC1:exs#1599.itm(0)} {ACC1:exs#1599.itm(1)} -attr xrf 53162 -attr oid 1218 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1599.itm}
+load net {ACC1:acc#351.itm(0)} -attr vt d
+load net {ACC1:acc#351.itm(1)} -attr vt d
+load net {ACC1:acc#351.itm(2)} -attr vt d
+load net {ACC1:acc#351.itm(3)} -attr vt d
+load net {ACC1:acc#351.itm(4)} -attr vt d
+load net {ACC1:acc#351.itm(5)} -attr vt d
+load net {ACC1:acc#351.itm(6)} -attr vt d
+load net {ACC1:acc#351.itm(7)} -attr vt d
+load net {ACC1:acc#351.itm(8)} -attr vt d
+load net {ACC1:acc#351.itm(9)} -attr vt d
+load net {ACC1:acc#351.itm(10)} -attr vt d
+load netBundle {ACC1:acc#351.itm} 11 {ACC1:acc#351.itm(0)} {ACC1:acc#351.itm(1)} {ACC1:acc#351.itm(2)} {ACC1:acc#351.itm(3)} {ACC1:acc#351.itm(4)} {ACC1:acc#351.itm(5)} {ACC1:acc#351.itm(6)} {ACC1:acc#351.itm(7)} {ACC1:acc#351.itm(8)} {ACC1:acc#351.itm(9)} {ACC1:acc#351.itm(10)} -attr xrf 53163 -attr oid 1219 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {regs.operator[]#12:not.itm(0)} -attr vt d
+load net {regs.operator[]#12:not.itm(1)} -attr vt d
+load net {regs.operator[]#12:not.itm(2)} -attr vt d
+load net {regs.operator[]#12:not.itm(3)} -attr vt d
+load net {regs.operator[]#12:not.itm(4)} -attr vt d
+load net {regs.operator[]#12:not.itm(5)} -attr vt d
+load net {regs.operator[]#12:not.itm(6)} -attr vt d
+load net {regs.operator[]#12:not.itm(7)} -attr vt d
+load net {regs.operator[]#12:not.itm(8)} -attr vt d
+load net {regs.operator[]#12:not.itm(9)} -attr vt d
+load netBundle {regs.operator[]#12:not.itm} 10 {regs.operator[]#12:not.itm(0)} {regs.operator[]#12:not.itm(1)} {regs.operator[]#12:not.itm(2)} {regs.operator[]#12:not.itm(3)} {regs.operator[]#12:not.itm(4)} {regs.operator[]#12:not.itm(5)} {regs.operator[]#12:not.itm(6)} {regs.operator[]#12:not.itm(7)} {regs.operator[]#12:not.itm(8)} {regs.operator[]#12:not.itm(9)} -attr xrf 53164 -attr oid 1220 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {slc(regs.regs(0).sva#3).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#3).itm} 10 {slc(regs.regs(0).sva#3).itm(0)} {slc(regs.regs(0).sva#3).itm(1)} {slc(regs.regs(0).sva#3).itm(2)} {slc(regs.regs(0).sva#3).itm(3)} {slc(regs.regs(0).sva#3).itm(4)} {slc(regs.regs(0).sva#3).itm(5)} {slc(regs.regs(0).sva#3).itm(6)} {slc(regs.regs(0).sva#3).itm(7)} {slc(regs.regs(0).sva#3).itm(8)} {slc(regs.regs(0).sva#3).itm(9)} -attr xrf 53165 -attr oid 1221 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {regs.operator[]#13:not.itm(0)} -attr vt d
+load net {regs.operator[]#13:not.itm(1)} -attr vt d
+load net {regs.operator[]#13:not.itm(2)} -attr vt d
+load net {regs.operator[]#13:not.itm(3)} -attr vt d
+load net {regs.operator[]#13:not.itm(4)} -attr vt d
+load net {regs.operator[]#13:not.itm(5)} -attr vt d
+load net {regs.operator[]#13:not.itm(6)} -attr vt d
+load net {regs.operator[]#13:not.itm(7)} -attr vt d
+load net {regs.operator[]#13:not.itm(8)} -attr vt d
+load net {regs.operator[]#13:not.itm(9)} -attr vt d
+load netBundle {regs.operator[]#13:not.itm} 10 {regs.operator[]#13:not.itm(0)} {regs.operator[]#13:not.itm(1)} {regs.operator[]#13:not.itm(2)} {regs.operator[]#13:not.itm(3)} {regs.operator[]#13:not.itm(4)} {regs.operator[]#13:not.itm(5)} {regs.operator[]#13:not.itm(6)} {regs.operator[]#13:not.itm(7)} {regs.operator[]#13:not.itm(8)} {regs.operator[]#13:not.itm(9)} -attr xrf 53166 -attr oid 1222 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {slc(regs.regs(0).sva#1).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#1).itm} 10 {slc(regs.regs(0).sva#1).itm(0)} {slc(regs.regs(0).sva#1).itm(1)} {slc(regs.regs(0).sva#1).itm(2)} {slc(regs.regs(0).sva#1).itm(3)} {slc(regs.regs(0).sva#1).itm(4)} {slc(regs.regs(0).sva#1).itm(5)} {slc(regs.regs(0).sva#1).itm(6)} {slc(regs.regs(0).sva#1).itm(7)} {slc(regs.regs(0).sva#1).itm(8)} {slc(regs.regs(0).sva#1).itm(9)} -attr xrf 53167 -attr oid 1223 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {ACC1:acc#350.itm(0)} -attr vt d
+load net {ACC1:acc#350.itm(1)} -attr vt d
+load net {ACC1:acc#350.itm(2)} -attr vt d
+load net {ACC1:acc#350.itm(3)} -attr vt d
+load net {ACC1:acc#350.itm(4)} -attr vt d
+load net {ACC1:acc#350.itm(5)} -attr vt d
+load net {ACC1:acc#350.itm(6)} -attr vt d
+load net {ACC1:acc#350.itm(7)} -attr vt d
+load net {ACC1:acc#350.itm(8)} -attr vt d
+load net {ACC1:acc#350.itm(9)} -attr vt d
+load net {ACC1:acc#350.itm(10)} -attr vt d
+load netBundle {ACC1:acc#350.itm} 11 {ACC1:acc#350.itm(0)} {ACC1:acc#350.itm(1)} {ACC1:acc#350.itm(2)} {ACC1:acc#350.itm(3)} {ACC1:acc#350.itm(4)} {ACC1:acc#350.itm(5)} {ACC1:acc#350.itm(6)} {ACC1:acc#350.itm(7)} {ACC1:acc#350.itm(8)} {ACC1:acc#350.itm(9)} {ACC1:acc#350.itm(10)} -attr xrf 53168 -attr oid 1224 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {regs.operator[]#14:not.itm(0)} -attr vt d
+load net {regs.operator[]#14:not.itm(1)} -attr vt d
+load net {regs.operator[]#14:not.itm(2)} -attr vt d
+load net {regs.operator[]#14:not.itm(3)} -attr vt d
+load net {regs.operator[]#14:not.itm(4)} -attr vt d
+load net {regs.operator[]#14:not.itm(5)} -attr vt d
+load net {regs.operator[]#14:not.itm(6)} -attr vt d
+load net {regs.operator[]#14:not.itm(7)} -attr vt d
+load net {regs.operator[]#14:not.itm(8)} -attr vt d
+load net {regs.operator[]#14:not.itm(9)} -attr vt d
+load netBundle {regs.operator[]#14:not.itm} 10 {regs.operator[]#14:not.itm(0)} {regs.operator[]#14:not.itm(1)} {regs.operator[]#14:not.itm(2)} {regs.operator[]#14:not.itm(3)} {regs.operator[]#14:not.itm(4)} {regs.operator[]#14:not.itm(5)} {regs.operator[]#14:not.itm(6)} {regs.operator[]#14:not.itm(7)} {regs.operator[]#14:not.itm(8)} {regs.operator[]#14:not.itm(9)} -attr xrf 53169 -attr oid 1225 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {slc(regs.regs(0).sva#2).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#2).itm} 10 {slc(regs.regs(0).sva#2).itm(0)} {slc(regs.regs(0).sva#2).itm(1)} {slc(regs.regs(0).sva#2).itm(2)} {slc(regs.regs(0).sva#2).itm(3)} {slc(regs.regs(0).sva#2).itm(4)} {slc(regs.regs(0).sva#2).itm(5)} {slc(regs.regs(0).sva#2).itm(6)} {slc(regs.regs(0).sva#2).itm(7)} {slc(regs.regs(0).sva#2).itm(8)} {slc(regs.regs(0).sva#2).itm(9)} -attr xrf 53170 -attr oid 1226 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {ACC1:acc#359.itm(0)} -attr vt d
+load net {ACC1:acc#359.itm(1)} -attr vt d
+load net {ACC1:acc#359.itm(2)} -attr vt d
+load netBundle {ACC1:acc#359.itm} 3 {ACC1:acc#359.itm(0)} {ACC1:acc#359.itm(1)} {ACC1:acc#359.itm(2)} -attr xrf 53171 -attr oid 1227 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#359.itm}
+load net {conc#1089.itm(0)} -attr vt d
+load net {conc#1089.itm(1)} -attr vt d
+load net {conc#1089.itm(2)} -attr vt d
+load netBundle {conc#1089.itm} 3 {conc#1089.itm(0)} {conc#1089.itm(1)} {conc#1089.itm(2)} -attr xrf 53172 -attr oid 1228 -attr vt d -attr @path {/sobel/sobel:core/conc#1089.itm}
+load net {ACC1:conc#1180.itm(0)} -attr vt d
+load net {ACC1:conc#1180.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1180.itm} 2 {ACC1:conc#1180.itm(0)} {ACC1:conc#1180.itm(1)} -attr xrf 53173 -attr oid 1229 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1180.itm}
+load net {ACC1:acc#358.itm(0)} -attr vt d
+load net {ACC1:acc#358.itm(1)} -attr vt d
+load net {ACC1:acc#358.itm(2)} -attr vt d
+load net {ACC1:acc#358.itm(3)} -attr vt d
+load netBundle {ACC1:acc#358.itm} 4 {ACC1:acc#358.itm(0)} {ACC1:acc#358.itm(1)} {ACC1:acc#358.itm(2)} {ACC1:acc#358.itm(3)} -attr xrf 53174 -attr oid 1230 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#358.itm}
+load net {conc#1090.itm(0)} -attr vt d
+load net {conc#1090.itm(1)} -attr vt d
+load net {conc#1090.itm(2)} -attr vt d
+load netBundle {conc#1090.itm} 3 {conc#1090.itm(0)} {conc#1090.itm(1)} {conc#1090.itm(2)} -attr xrf 53175 -attr oid 1231 -attr vt d -attr @path {/sobel/sobel:core/conc#1090.itm}
+load net {ACC1-1:not#299.itm(0)} -attr vt d
+load net {ACC1-1:not#299.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#299.itm} 2 {ACC1-1:not#299.itm(0)} {ACC1-1:not#299.itm(1)} -attr xrf 53176 -attr oid 1232 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#299.itm}
+load net {slc(ACC1:acc#223.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#223.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#223.psp#1.sva).itm} 2 {slc(ACC1:acc#223.psp#1.sva).itm(0)} {slc(ACC1:acc#223.psp#1.sva).itm(1)} -attr xrf 53177 -attr oid 1233 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp#1.sva).itm}
+load net {conc#1091.itm(0)} -attr vt d
+load net {conc#1091.itm(1)} -attr vt d
+load netBundle {conc#1091.itm} 2 {conc#1091.itm(0)} {conc#1091.itm(1)} -attr xrf 53178 -attr oid 1234 -attr vt d -attr @path {/sobel/sobel:core/conc#1091.itm}
+load net {ACC1:slc#33.itm(0)} -attr vt d
+load net {ACC1:slc#33.itm(1)} -attr vt d
+load net {ACC1:slc#33.itm(2)} -attr vt d
+load net {ACC1:slc#33.itm(3)} -attr vt d
+load netBundle {ACC1:slc#33.itm} 4 {ACC1:slc#33.itm(0)} {ACC1:slc#33.itm(1)} {ACC1:slc#33.itm(2)} {ACC1:slc#33.itm(3)} -attr xrf 53179 -attr oid 1235 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#356.itm(0)} -attr vt d
+load net {ACC1:acc#356.itm(1)} -attr vt d
+load net {ACC1:acc#356.itm(2)} -attr vt d
+load net {ACC1:acc#356.itm(3)} -attr vt d
+load net {ACC1:acc#356.itm(4)} -attr vt d
+load netBundle {ACC1:acc#356.itm} 5 {ACC1:acc#356.itm(0)} {ACC1:acc#356.itm(1)} {ACC1:acc#356.itm(2)} {ACC1:acc#356.itm(3)} {ACC1:acc#356.itm(4)} -attr xrf 53180 -attr oid 1236 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356.itm}
+load net {conc#1092.itm(0)} -attr vt d
+load net {conc#1092.itm(1)} -attr vt d
+load net {conc#1092.itm(2)} -attr vt d
+load net {conc#1092.itm(3)} -attr vt d
+load netBundle {conc#1092.itm} 4 {conc#1092.itm(0)} {conc#1092.itm(1)} {conc#1092.itm(2)} {conc#1092.itm(3)} -attr xrf 53181 -attr oid 1237 -attr vt d -attr @path {/sobel/sobel:core/conc#1092.itm}
+load net {ACC1:slc#31.itm(0)} -attr vt d
+load net {ACC1:slc#31.itm(1)} -attr vt d
+load net {ACC1:slc#31.itm(2)} -attr vt d
+load netBundle {ACC1:slc#31.itm} 3 {ACC1:slc#31.itm(0)} {ACC1:slc#31.itm(1)} {ACC1:slc#31.itm(2)} -attr xrf 53182 -attr oid 1238 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#31.itm}
+load net {ACC1:acc#354.itm(0)} -attr vt d
+load net {ACC1:acc#354.itm(1)} -attr vt d
+load net {ACC1:acc#354.itm(2)} -attr vt d
+load net {ACC1:acc#354.itm(3)} -attr vt d
+load netBundle {ACC1:acc#354.itm} 4 {ACC1:acc#354.itm(0)} {ACC1:acc#354.itm(1)} {ACC1:acc#354.itm(2)} {ACC1:acc#354.itm(3)} -attr xrf 53183 -attr oid 1239 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#354.itm}
+load net {conc#1093.itm(0)} -attr vt d
+load net {conc#1093.itm(1)} -attr vt d
+load netBundle {conc#1093.itm} 2 {conc#1093.itm(0)} {conc#1093.itm(1)} -attr xrf 53184 -attr oid 1240 -attr vt d -attr @path {/sobel/sobel:core/conc#1093.itm}
+load net {ACC1:conc#1169.itm(0)} -attr vt d
+load net {ACC1:conc#1169.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1169.itm} 2 {ACC1:conc#1169.itm(0)} {ACC1:conc#1169.itm(1)} -attr xrf 53185 -attr oid 1241 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1169.itm}
+load net {conc#1094.itm(0)} -attr vt d
+load net {conc#1094.itm(1)} -attr vt d
+load net {conc#1094.itm(2)} -attr vt d
+load net {conc#1094.itm(3)} -attr vt d
+load netBundle {conc#1094.itm} 4 {conc#1094.itm(0)} {conc#1094.itm(1)} {conc#1094.itm(2)} {conc#1094.itm(3)} -attr xrf 53186 -attr oid 1242 -attr vt d -attr @path {/sobel/sobel:core/conc#1094.itm}
+load net {ACC1:slc#32.itm(0)} -attr vt d
+load net {ACC1:slc#32.itm(1)} -attr vt d
+load net {ACC1:slc#32.itm(2)} -attr vt d
+load netBundle {ACC1:slc#32.itm} 3 {ACC1:slc#32.itm(0)} {ACC1:slc#32.itm(1)} {ACC1:slc#32.itm(2)} -attr xrf 53187 -attr oid 1243 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#32.itm}
+load net {ACC1:acc#355.itm(0)} -attr vt d
+load net {ACC1:acc#355.itm(1)} -attr vt d
+load net {ACC1:acc#355.itm(2)} -attr vt d
+load net {ACC1:acc#355.itm(3)} -attr vt d
+load netBundle {ACC1:acc#355.itm} 4 {ACC1:acc#355.itm(0)} {ACC1:acc#355.itm(1)} {ACC1:acc#355.itm(2)} {ACC1:acc#355.itm(3)} -attr xrf 53188 -attr oid 1244 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#355.itm}
+load net {conc#1095.itm(0)} -attr vt d
+load net {conc#1095.itm(1)} -attr vt d
+load net {conc#1095.itm(2)} -attr vt d
+load netBundle {conc#1095.itm} 3 {conc#1095.itm(0)} {conc#1095.itm(1)} {conc#1095.itm(2)} -attr xrf 53189 -attr oid 1245 -attr vt d -attr @path {/sobel/sobel:core/conc#1095.itm}
+load net {ACC1:slc#30.itm(0)} -attr vt d
+load net {ACC1:slc#30.itm(1)} -attr vt d
+load netBundle {ACC1:slc#30.itm} 2 {ACC1:slc#30.itm(0)} {ACC1:slc#30.itm(1)} -attr xrf 53190 -attr oid 1246 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#30.itm}
+load net {ACC1:acc#353.itm(0)} -attr vt d
+load net {ACC1:acc#353.itm(1)} -attr vt d
+load net {ACC1:acc#353.itm(2)} -attr vt d
+load netBundle {ACC1:acc#353.itm} 3 {ACC1:acc#353.itm(0)} {ACC1:acc#353.itm(1)} {ACC1:acc#353.itm(2)} -attr xrf 53191 -attr oid 1247 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#353.itm}
+load net {conc#1096.itm(0)} -attr vt d
+load net {conc#1096.itm(1)} -attr vt d
+load netBundle {conc#1096.itm} 2 {conc#1096.itm(0)} {conc#1096.itm(1)} -attr xrf 53192 -attr oid 1248 -attr vt d -attr @path {/sobel/sobel:core/conc#1096.itm}
+load net {ACC1:conc#1167.itm(0)} -attr vt d
+load net {ACC1:conc#1167.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1167.itm} 2 {ACC1:conc#1167.itm(0)} {ACC1:conc#1167.itm(1)} -attr xrf 53193 -attr oid 1249 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1167.itm}
+load net {ACC1:conc#1171.itm(0)} -attr vt d
+load net {ACC1:conc#1171.itm(1)} -attr vt d
+load net {ACC1:conc#1171.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1171.itm} 3 {ACC1:conc#1171.itm(0)} {ACC1:conc#1171.itm(1)} {ACC1:conc#1171.itm(2)} -attr xrf 53194 -attr oid 1250 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1171.itm}
+load net {ACC1:slc#29.itm(0)} -attr vt d
+load net {ACC1:slc#29.itm(1)} -attr vt d
+load netBundle {ACC1:slc#29.itm} 2 {ACC1:slc#29.itm(0)} {ACC1:slc#29.itm(1)} -attr xrf 53195 -attr oid 1251 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#29.itm}
+load net {ACC1:acc#352.itm(0)} -attr vt d
+load net {ACC1:acc#352.itm(1)} -attr vt d
+load net {ACC1:acc#352.itm(2)} -attr vt d
+load netBundle {ACC1:acc#352.itm} 3 {ACC1:acc#352.itm(0)} {ACC1:acc#352.itm(1)} {ACC1:acc#352.itm(2)} -attr xrf 53196 -attr oid 1252 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#352.itm}
+load net {conc#1097.itm(0)} -attr vt d
+load net {conc#1097.itm(1)} -attr vt d
+load netBundle {conc#1097.itm} 2 {conc#1097.itm(0)} {conc#1097.itm(1)} -attr xrf 53197 -attr oid 1253 -attr vt d -attr @path {/sobel/sobel:core/conc#1097.itm}
+load net {ACC1:conc#1165.itm(0)} -attr vt d
+load net {ACC1:conc#1165.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1165.itm} 2 {ACC1:conc#1165.itm(0)} {ACC1:conc#1165.itm(1)} -attr xrf 53198 -attr oid 1254 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1165.itm}
+load net {ACC1:slc#34.itm(0)} -attr vt d
+load net {ACC1:slc#34.itm(1)} -attr vt d
+load netBundle {ACC1:slc#34.itm} 2 {ACC1:slc#34.itm(0)} {ACC1:slc#34.itm(1)} -attr xrf 53199 -attr oid 1255 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#357.itm(0)} -attr vt d
+load net {ACC1:acc#357.itm(1)} -attr vt d
+load net {ACC1:acc#357.itm(2)} -attr vt d
+load netBundle {ACC1:acc#357.itm} 3 {ACC1:acc#357.itm(0)} {ACC1:acc#357.itm(1)} {ACC1:acc#357.itm(2)} -attr xrf 53200 -attr oid 1256 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#357.itm}
+load net {conc#1098.itm(0)} -attr vt d
+load net {conc#1098.itm(1)} -attr vt d
+load netBundle {conc#1098.itm} 2 {conc#1098.itm(0)} {conc#1098.itm(1)} -attr xrf 53201 -attr oid 1257 -attr vt d -attr @path {/sobel/sobel:core/conc#1098.itm}
+load net {ACC1:conc#1175.itm(0)} -attr vt d
+load net {ACC1:conc#1175.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1175.itm} 2 {ACC1:conc#1175.itm(0)} {ACC1:conc#1175.itm(1)} -attr xrf 53202 -attr oid 1258 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1175.itm}
+load net {ACC1:exs#1655.itm(0)} -attr vt d
+load net {ACC1:exs#1655.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1655.itm} 2 {ACC1:exs#1655.itm(0)} {ACC1:exs#1655.itm(1)} -attr xrf 53203 -attr oid 1259 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1655.itm}
+load net {ACC1:exs#1611.itm(0)} -attr vt d
+load net {ACC1:exs#1611.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1611.itm} 2 {ACC1:exs#1611.itm(0)} {ACC1:exs#1611.itm(1)} -attr xrf 53204 -attr oid 1260 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1611.itm}
+load net {ACC1:acc#339.itm(0)} -attr vt d
+load net {ACC1:acc#339.itm(1)} -attr vt d
+load net {ACC1:acc#339.itm(2)} -attr vt d
+load netBundle {ACC1:acc#339.itm} 3 {ACC1:acc#339.itm(0)} {ACC1:acc#339.itm(1)} {ACC1:acc#339.itm(2)} -attr xrf 53205 -attr oid 1261 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {conc#1099.itm(0)} -attr vt d
+load net {conc#1099.itm(1)} -attr vt d
+load net {conc#1099.itm(2)} -attr vt d
+load netBundle {conc#1099.itm} 3 {conc#1099.itm(0)} {conc#1099.itm(1)} {conc#1099.itm(2)} -attr xrf 53206 -attr oid 1262 -attr vt d -attr @path {/sobel/sobel:core/conc#1099.itm}
+load net {ACC1:conc#1144.itm(0)} -attr vt d
+load net {ACC1:conc#1144.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1144.itm} 2 {ACC1:conc#1144.itm(0)} {ACC1:conc#1144.itm(1)} -attr xrf 53207 -attr oid 1263 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1144.itm}
+load net {clk} -attr xrf 53208 -attr oid 1264
+load net {clk} -port {clk} -attr xrf 53209 -attr oid 1265
+load net {en} -attr xrf 53210 -attr oid 1266
+load net {en} -port {en} -attr xrf 53211 -attr oid 1267
+load net {arst_n} -attr xrf 53212 -attr oid 1268
+load net {arst_n} -port {arst_n} -attr xrf 53213 -attr oid 1269
+load net {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 53214 -attr oid 1270 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(0)} -port {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -port {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -port {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -port {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -port {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -port {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -port {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -port {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -port {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -port {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -port {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -port {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -port {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -port {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -port {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -port {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -port {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -port {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -port {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -port {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -port {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -port {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -port {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -port {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -port {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -port {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -port {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -port {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -port {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -port {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -port {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -port {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -port {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -port {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -port {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -port {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -port {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -port {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -port {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -port {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -port {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -port {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -port {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -port {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -port {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -port {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -port {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -port {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -port {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -port {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -port {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -port {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -port {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -port {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -port {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -port {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -port {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -port {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -port {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -port {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -port {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -port {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -port {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -port {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -port {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -port {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -port {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -port {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -port {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -port {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -port {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -port {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -port {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -port {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -port {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -port {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -port {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -port {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -port {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -port {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -port {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -port {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -port {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -port {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -port {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -port {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -port {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -port {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -port {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -port {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 53215 -attr oid 1271 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d} 30 {vout:rsc:mgc_out_stdreg.d(0)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(29)} -attr xrf 53216 -attr oid 1272 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -port {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -port {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -port {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -port {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -port {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -port {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -port {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -port {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -port {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -port {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -port {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -port {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -port {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -port {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -port {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -port {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -port {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -port {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -port {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -port {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -port {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -port {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -port {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -port {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -port {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -port {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -port {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -port {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -port {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -port {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:or" "or(2,10)" "INTERFACE" -attr xrf 53217 -attr oid 1273 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or} -attr area 7.298324 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2)"
+load net {FRAME:acc#2.psp.sva(0)} -pin  "FRAME:or" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "FRAME:or" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "FRAME:or" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "FRAME:or" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "FRAME:or" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "FRAME:or" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "FRAME:or" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "FRAME:or" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "FRAME:or" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "FRAME:or" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(10)} -pin  "FRAME:or" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {FRAME:acc#2.psp.sva(11)} -pin  "FRAME:or" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(2)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(3)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(4)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(5)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(6)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(7)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(8)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(9)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {FRAME:or.itm(0)} -pin  "FRAME:or" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(1)} -pin  "FRAME:or" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(2)} -pin  "FRAME:or" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(3)} -pin  "FRAME:or" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(4)} -pin  "FRAME:or" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(5)} -pin  "FRAME:or" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(6)} -pin  "FRAME:or" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(7)} -pin  "FRAME:or" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(8)} -pin  "FRAME:or" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(9)} -pin  "FRAME:or" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load inst "FRAME:or#3" "or(2,6)" "INTERFACE" -attr xrf 53218 -attr oid 1274 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3} -attr area 4.378994 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2)"
+load net {FRAME:acc#2.psp.sva(0)} -pin  "FRAME:or#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "FRAME:or#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "FRAME:or#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "FRAME:or#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "FRAME:or#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "FRAME:or#3" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(10)} -pin  "FRAME:or#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {FRAME:acc#2.psp.sva(11)} -pin  "FRAME:or#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(2)} -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(3)} -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(4)} -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(5)} -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {FRAME:or#3.itm(0)} -pin  "FRAME:or#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(1)} -pin  "FRAME:or#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(2)} -pin  "FRAME:or#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(3)} -pin  "FRAME:or#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(4)} -pin  "FRAME:or#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(5)} -pin  "FRAME:or#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load inst "mux" "mux(2,30)" "INTERFACE" -attr xrf 53219 -attr oid 1275 -attr vt d -attr @path {/sobel/sobel:core/mux} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {FRAME:acc#2.psp.sva(0)} -pin  "mux" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "mux" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "mux" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "mux" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "mux" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "mux" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "mux" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "mux" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "mux" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "mux" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(0)} -pin  "mux" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(1)} -pin  "mux" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(2)} -pin  "mux" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(3)} -pin  "mux" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(4)} -pin  "mux" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(5)} -pin  "mux" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "mux" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "mux" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "mux" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "mux" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(0)} -pin  "mux" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(1)} -pin  "mux" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(2)} -pin  "mux" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(3)} -pin  "mux" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(4)} -pin  "mux" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(5)} -pin  "mux" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(6)} -pin  "mux" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(7)} -pin  "mux" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(8)} -pin  "mux" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(9)} -pin  "mux" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "mux" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "mux" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "mux" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "mux" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "mux" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "mux" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "mux" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "mux" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "mux" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "mux" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "mux" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "mux" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "mux" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "mux" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "mux" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "mux" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "mux" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "mux" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "mux" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "mux" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {main.stage_0#2} -pin  "mux" {S(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {mux.itm(0)} -pin  "mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "mux" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "mux" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "mux" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "mux" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "mux" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "mux" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "mux" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "mux" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "mux" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "mux" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "mux" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "mux" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "mux" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "mux" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "mux" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "mux" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "mux" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "mux" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "mux" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "mux" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 53220 -attr oid 1276 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)}
+load net {mux.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 53221 -attr oid 1277 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "ACC1:acc#326" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 53222 -attr oid 1278 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#227.psp.sva(9)} -pin  "ACC1:acc#326" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#13.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#326" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#14.itm}
+load net {ACC1:acc#326.itm(0)} -pin  "ACC1:acc#326" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(1)} -pin  "ACC1:acc#326" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load inst "ACC1:acc#325" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 53223 -attr oid 1279 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#326.itm(0)} -pin  "ACC1:acc#325" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(1)} -pin  "ACC1:acc#325" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#224.psp.sva(8)} -pin  "ACC1:acc#325" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#8.itm}
+load net {ACC1:acc#325.itm(0)} -pin  "ACC1:acc#325" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(1)} -pin  "ACC1:acc#325" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load inst "ACC1:acc#324" "add(2,0,1,0,3)" "INTERFACE" -attr xrf 53224 -attr oid 1280 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#325.itm(0)} -pin  "ACC1:acc#324" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(1)} -pin  "ACC1:acc#324" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#228.psp.sva(8)} -pin  "ACC1:acc#324" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#25.itm}
+load net {ACC1:acc#324.itm(0)} -pin  "ACC1:acc#324" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(1)} -pin  "ACC1:acc#324" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(2)} -pin  "ACC1:acc#324" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load inst "ACC1:acc#323" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 53225 -attr oid 1281 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#324.itm(0)} -pin  "ACC1:acc#323" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(1)} -pin  "ACC1:acc#323" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(2)} -pin  "ACC1:acc#323" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#226.psp.sva(8)} -pin  "ACC1:acc#323" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#20.itm}
+load net {ACC1:acc#323.itm(0)} -pin  "ACC1:acc#323" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(1)} -pin  "ACC1:acc#323" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(2)} -pin  "ACC1:acc#323" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load inst "ACC1:acc#322" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 53226 -attr oid 1282 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#323.itm(0)} -pin  "ACC1:acc#322" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(1)} -pin  "ACC1:acc#322" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(2)} -pin  "ACC1:acc#322" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#224.psp#1.sva(8)} -pin  "ACC1:acc#322" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#37.itm}
+load net {ACC1:acc#322.itm(0)} -pin  "ACC1:acc#322" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(1)} -pin  "ACC1:acc#322" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(2)} -pin  "ACC1:acc#322" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load inst "ACC1:acc#321" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 53227 -attr oid 1283 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#322.itm(0)} -pin  "ACC1:acc#321" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(1)} -pin  "ACC1:acc#321" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(2)} -pin  "ACC1:acc#321" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1-1:acc#25.psp.sva(9)} -pin  "ACC1:acc#321" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#14.itm}
+load net {ACC1:acc#321.itm(0)} -pin  "ACC1:acc#321" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(1)} -pin  "ACC1:acc#321" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(2)} -pin  "ACC1:acc#321" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load inst "ACC1:acc#320" "add(3,0,1,0,4)" "INTERFACE" -attr xrf 53228 -attr oid 1284 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#321.itm(0)} -pin  "ACC1:acc#320" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(1)} -pin  "ACC1:acc#320" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(2)} -pin  "ACC1:acc#320" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#320" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#14.itm}
+load net {ACC1:acc#320.itm(0)} -pin  "ACC1:acc#320" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#320.itm(1)} -pin  "ACC1:acc#320" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#320.itm(2)} -pin  "ACC1:acc#320" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#320.itm(3)} -pin  "ACC1:acc#320" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load inst "ACC1:mul#58" "mul(4,0,5,0,8)" "INTERFACE" -attr xrf 53229 -attr oid 1285 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,5,0,8)"
+load net {ACC1:acc#320.itm(0)} -pin  "ACC1:mul#58" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#320.itm(1)} -pin  "ACC1:mul#58" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#320.itm(2)} -pin  "ACC1:mul#58" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#320.itm(3)} -pin  "ACC1:mul#58" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {PWR} -pin  "ACC1:mul#58" {B(0)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#58" {B(1)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#58" {B(2)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#58" {B(3)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#58" {B(4)} -attr @path {/sobel/sobel:core/C21_5}
+load net {ACC1:mul#58.itm(0)} -pin  "ACC1:mul#58" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(1)} -pin  "ACC1:mul#58" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(2)} -pin  "ACC1:mul#58" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(3)} -pin  "ACC1:mul#58" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(4)} -pin  "ACC1:mul#58" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(5)} -pin  "ACC1:mul#58" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(6)} -pin  "ACC1:mul#58" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(7)} -pin  "ACC1:mul#58" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load inst "ACC1:acc#654" "add(11,1,11,0,12)" "INTERFACE" -attr xrf 53230 -attr oid 1286 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,12)"
+load net {ACC1:acc#224.psp.sva(0)} -pin  "ACC1:acc#654" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#654" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {GND} -pin  "ACC1:acc#654" {A(2)} -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#654" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {GND} -pin  "ACC1:acc#654" {A(4)} -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#654" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {GND} -pin  "ACC1:acc#654" {A(6)} -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#654" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {GND} -pin  "ACC1:acc#654" {A(8)} -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {GND} -pin  "ACC1:acc#654" {A(9)} -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#654" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#654" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#654" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:acc#227.psp.sva(4)} -pin  "ACC1:acc#654" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(0)} -pin  "ACC1:acc#654" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(1)} -pin  "ACC1:acc#654" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(2)} -pin  "ACC1:acc#654" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(3)} -pin  "ACC1:acc#654" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(4)} -pin  "ACC1:acc#654" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(5)} -pin  "ACC1:acc#654" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(6)} -pin  "ACC1:acc#654" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(7)} -pin  "ACC1:acc#654" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:acc#654.itm(0)} -pin  "ACC1:acc#654" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(1)} -pin  "ACC1:acc#654" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(2)} -pin  "ACC1:acc#654" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(3)} -pin  "ACC1:acc#654" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(4)} -pin  "ACC1:acc#654" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(5)} -pin  "ACC1:acc#654" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(6)} -pin  "ACC1:acc#654" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(7)} -pin  "ACC1:acc#654" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(8)} -pin  "ACC1:acc#654" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(9)} -pin  "ACC1:acc#654" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(10)} -pin  "ACC1:acc#654" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(11)} -pin  "ACC1:acc#654" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load inst "ACC1:acc#670" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53231 -attr oid 1287 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#670} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#670" {A(0)} -attr @path {/sobel/sobel:core/exs.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#670" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#670" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {ACC1-1:nand#1.cse.sva} -pin  "ACC1:acc#670" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:exs#1474.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#670" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:exs#1474.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#670" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:exs#1474.itm}
+load net {ACC1:acc#670.itm(0)} -pin  "ACC1:acc#670" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#670.itm}
+load net {ACC1:acc#670.itm(1)} -pin  "ACC1:acc#670" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#670.itm}
+load net {ACC1:acc#670.itm(2)} -pin  "ACC1:acc#670" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#670.itm}
+load net {ACC1:acc#670.itm(3)} -pin  "ACC1:acc#670" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#670.itm}
+load inst "ACC1-1:not#318" "not(1)" "INTERFACE" -attr xrf 53232 -attr oid 1288 -attr @path {/sobel/sobel:core/ACC1-1:not#318} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#338.itm(3)} -pin  "ACC1-1:not#318" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#26.sva)#6.itm}
+load net {ACC1-1:not#318.itm} -pin  "ACC1-1:not#318" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#318.itm}
+load inst "ACC1:acc#669" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53233 -attr oid 1289 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#669} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#669" {A(0)} -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#669" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#669" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {ACC1-1:not#318.itm} -pin  "ACC1:acc#669" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1476.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#669" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1476.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#669" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1476.itm}
+load net {ACC1:acc#669.itm(0)} -pin  "ACC1:acc#669" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#669.itm}
+load net {ACC1:acc#669.itm(1)} -pin  "ACC1:acc#669" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#669.itm}
+load net {ACC1:acc#669.itm(2)} -pin  "ACC1:acc#669" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#669.itm}
+load net {ACC1:acc#669.itm(3)} -pin  "ACC1:acc#669" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#669.itm}
+load inst "ACC1:acc#676" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53234 -attr oid 1290 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#670.itm(1)} -pin  "ACC1:acc#676" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#153.itm}
+load net {ACC1:acc#670.itm(2)} -pin  "ACC1:acc#676" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#153.itm}
+load net {ACC1:acc#670.itm(3)} -pin  "ACC1:acc#676" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#153.itm}
+load net {ACC1:acc#669.itm(1)} -pin  "ACC1:acc#676" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#152.itm}
+load net {ACC1:acc#669.itm(2)} -pin  "ACC1:acc#676" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#152.itm}
+load net {ACC1:acc#669.itm(3)} -pin  "ACC1:acc#676" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#152.itm}
+load net {ACC1:acc#676.itm(0)} -pin  "ACC1:acc#676" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#676.itm(1)} -pin  "ACC1:acc#676" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#676.itm(2)} -pin  "ACC1:acc#676" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#676.itm(3)} -pin  "ACC1:acc#676" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load inst "ACC1:acc#668" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53235 -attr oid 1291 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#668} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#668" {A(0)} -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#668" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#668" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {ACC1:acc#338.itm(2)} -pin  "ACC1:acc#668" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1478.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#668" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1478.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#668" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1478.itm}
+load net {ACC1:acc#668.itm(0)} -pin  "ACC1:acc#668" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#668.itm}
+load net {ACC1:acc#668.itm(1)} -pin  "ACC1:acc#668" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#668.itm}
+load net {ACC1:acc#668.itm(2)} -pin  "ACC1:acc#668" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#668.itm}
+load net {ACC1:acc#668.itm(3)} -pin  "ACC1:acc#668" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#668.itm}
+load inst "ACC1:acc#667" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53236 -attr oid 1292 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#667} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#667" {A(0)} -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#667" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#667" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {ACC1:acc#210.psp#2.sva(2)} -pin  "ACC1:acc#667" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1480.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#667" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1480.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#667" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1480.itm}
+load net {ACC1:acc#667.itm(0)} -pin  "ACC1:acc#667" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#667.itm}
+load net {ACC1:acc#667.itm(1)} -pin  "ACC1:acc#667" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#667.itm}
+load net {ACC1:acc#667.itm(2)} -pin  "ACC1:acc#667" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#667.itm}
+load net {ACC1:acc#667.itm(3)} -pin  "ACC1:acc#667" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#667.itm}
+load inst "ACC1:acc#675" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53237 -attr oid 1293 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#668.itm(1)} -pin  "ACC1:acc#675" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#151.itm}
+load net {ACC1:acc#668.itm(2)} -pin  "ACC1:acc#675" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#151.itm}
+load net {ACC1:acc#668.itm(3)} -pin  "ACC1:acc#675" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#151.itm}
+load net {ACC1:acc#667.itm(1)} -pin  "ACC1:acc#675" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#150.itm}
+load net {ACC1:acc#667.itm(2)} -pin  "ACC1:acc#675" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#150.itm}
+load net {ACC1:acc#667.itm(3)} -pin  "ACC1:acc#675" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#150.itm}
+load net {ACC1:acc#675.itm(0)} -pin  "ACC1:acc#675" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#675.itm(1)} -pin  "ACC1:acc#675" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#675.itm(2)} -pin  "ACC1:acc#675" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#675.itm(3)} -pin  "ACC1:acc#675" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load inst "ACC1:acc#680" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53238 -attr oid 1294 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#676.itm(0)} -pin  "ACC1:acc#680" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#676.itm(1)} -pin  "ACC1:acc#680" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#676.itm(2)} -pin  "ACC1:acc#680" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#676.itm(3)} -pin  "ACC1:acc#680" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#675.itm(0)} -pin  "ACC1:acc#680" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#675.itm(1)} -pin  "ACC1:acc#680" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#675.itm(2)} -pin  "ACC1:acc#680" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#675.itm(3)} -pin  "ACC1:acc#680" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#680.itm(0)} -pin  "ACC1:acc#680" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(1)} -pin  "ACC1:acc#680" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(2)} -pin  "ACC1:acc#680" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(3)} -pin  "ACC1:acc#680" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(4)} -pin  "ACC1:acc#680" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load inst "ACC1:acc#683" "add(6,0,5,0,7)" "INTERFACE" -attr xrf 53239 -attr oid 1295 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#683" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#683" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {GND} -pin  "ACC1:acc#683" {A(2)} -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#683" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {GND} -pin  "ACC1:acc#683" {A(4)} -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#683" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {ACC1:acc#680.itm(0)} -pin  "ACC1:acc#683" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(1)} -pin  "ACC1:acc#683" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(2)} -pin  "ACC1:acc#683" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(3)} -pin  "ACC1:acc#683" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(4)} -pin  "ACC1:acc#683" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#683.itm(0)} -pin  "ACC1:acc#683" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(1)} -pin  "ACC1:acc#683" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(2)} -pin  "ACC1:acc#683" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(3)} -pin  "ACC1:acc#683" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(4)} -pin  "ACC1:acc#683" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(5)} -pin  "ACC1:acc#683" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(6)} -pin  "ACC1:acc#683" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load inst "ACC1:acc#686" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 53240 -attr oid 1296 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#686" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#686" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {GND} -pin  "ACC1:acc#686" {A(2)} -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#686" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {GND} -pin  "ACC1:acc#686" {A(4)} -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#686" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {GND} -pin  "ACC1:acc#686" {A(6)} -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#686" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {ACC1:acc#683.itm(0)} -pin  "ACC1:acc#686" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(1)} -pin  "ACC1:acc#686" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(2)} -pin  "ACC1:acc#686" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(3)} -pin  "ACC1:acc#686" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(4)} -pin  "ACC1:acc#686" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(5)} -pin  "ACC1:acc#686" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(6)} -pin  "ACC1:acc#686" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#686.itm(0)} -pin  "ACC1:acc#686" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(1)} -pin  "ACC1:acc#686" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(2)} -pin  "ACC1:acc#686" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(3)} -pin  "ACC1:acc#686" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(4)} -pin  "ACC1:acc#686" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(5)} -pin  "ACC1:acc#686" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(6)} -pin  "ACC1:acc#686" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(7)} -pin  "ACC1:acc#686" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load inst "ACC1:acc#688" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 53241 -attr oid 1297 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,11)"
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#688" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {GND} -pin  "ACC1:acc#688" {A(1)} -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#688" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {GND} -pin  "ACC1:acc#688" {A(3)} -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#688" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {GND} -pin  "ACC1:acc#688" {A(5)} -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#688" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {GND} -pin  "ACC1:acc#688" {A(7)} -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#688" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {ACC1:acc#686.itm(0)} -pin  "ACC1:acc#688" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(1)} -pin  "ACC1:acc#688" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(2)} -pin  "ACC1:acc#688" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(3)} -pin  "ACC1:acc#688" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(4)} -pin  "ACC1:acc#688" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(5)} -pin  "ACC1:acc#688" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(6)} -pin  "ACC1:acc#688" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(7)} -pin  "ACC1:acc#688" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#688.itm(0)} -pin  "ACC1:acc#688" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(1)} -pin  "ACC1:acc#688" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(2)} -pin  "ACC1:acc#688" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(3)} -pin  "ACC1:acc#688" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(4)} -pin  "ACC1:acc#688" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(5)} -pin  "ACC1:acc#688" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(6)} -pin  "ACC1:acc#688" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(7)} -pin  "ACC1:acc#688" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(8)} -pin  "ACC1:acc#688" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(9)} -pin  "ACC1:acc#688" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load inst "ACC1:acc#665" "add(3,1,2,1,4)" "INTERFACE" -attr xrf 53242 -attr oid 1298 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#665} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#665" {A(0)} -attr @path {/sobel/sobel:core/conc#888.itm}
+load net {acc.psp#2.sva(3)} -pin  "ACC1:acc#665" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#888.itm}
+load net {PWR} -pin  "ACC1:acc#665" {A(2)} -attr @path {/sobel/sobel:core/conc#888.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#665" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1420.itm}
+load net {ACC1:acc#210.psp#2.sva(3)} -pin  "ACC1:acc#665" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1420.itm}
+load net {ACC1:acc#665.itm(0)} -pin  "ACC1:acc#665" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#665.itm}
+load net {ACC1:acc#665.itm(1)} -pin  "ACC1:acc#665" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#665.itm}
+load net {ACC1:acc#665.itm(2)} -pin  "ACC1:acc#665" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#665.itm}
+load net {ACC1:acc#665.itm(3)} -pin  "ACC1:acc#665" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#665.itm}
+load inst "ACC1:acc#674" "add(3,-1,2,1,3)" "INTERFACE" -attr xrf 53243 -attr oid 1299 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {ACC1:acc#665.itm(1)} -pin  "ACC1:acc#674" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#148.itm}
+load net {ACC1:acc#665.itm(2)} -pin  "ACC1:acc#674" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#148.itm}
+load net {ACC1:acc#665.itm(3)} -pin  "ACC1:acc#674" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#148.itm}
+load net {ACC1:acc#220.psp#1.sva(1)} -pin  "ACC1:acc#674" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva)#3.itm}
+load net {ACC1:acc#220.psp#1.sva(2)} -pin  "ACC1:acc#674" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva)#3.itm}
+load net {ACC1:acc#674.itm(0)} -pin  "ACC1:acc#674" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load net {ACC1:acc#674.itm(1)} -pin  "ACC1:acc#674" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load net {ACC1:acc#674.itm(2)} -pin  "ACC1:acc#674" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load inst "ACC1:acc#666" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 53244 -attr oid 1300 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#666" {A(0)} -attr @path {/sobel/sobel:core/conc#889.itm}
+load net {acc.psp#2.sva(1)} -pin  "ACC1:acc#666" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#889.itm}
+load net {acc.psp#2.sva(3)} -pin  "ACC1:acc#666" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#889.itm}
+load net {ACC1:acc#210.psp#2.sva(1)} -pin  "ACC1:acc#666" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1422.itm}
+load net {acc.psp#2.sva(2)} -pin  "ACC1:acc#666" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1422.itm}
+load net {ACC1:acc#210.psp#2.sva(3)} -pin  "ACC1:acc#666" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1422.itm}
+load net {ACC1:acc#666.itm(0)} -pin  "ACC1:acc#666" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666.itm}
+load net {ACC1:acc#666.itm(1)} -pin  "ACC1:acc#666" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666.itm}
+load net {ACC1:acc#666.itm(2)} -pin  "ACC1:acc#666" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666.itm}
+load net {ACC1:acc#666.itm(3)} -pin  "ACC1:acc#666" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666.itm}
+load net {ACC1:acc#666.itm(4)} -pin  "ACC1:acc#666" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666.itm}
+load inst "ACC1:acc#679" "add(3,1,4,-1,4)" "INTERFACE" -attr xrf 53245 -attr oid 1301 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#674.itm(0)} -pin  "ACC1:acc#679" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load net {ACC1:acc#674.itm(1)} -pin  "ACC1:acc#679" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load net {ACC1:acc#674.itm(2)} -pin  "ACC1:acc#679" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load net {ACC1:acc#666.itm(1)} -pin  "ACC1:acc#679" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#149.itm}
+load net {ACC1:acc#666.itm(2)} -pin  "ACC1:acc#679" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#149.itm}
+load net {ACC1:acc#666.itm(3)} -pin  "ACC1:acc#679" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#149.itm}
+load net {ACC1:acc#666.itm(4)} -pin  "ACC1:acc#679" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#149.itm}
+load net {ACC1:acc#679.itm(0)} -pin  "ACC1:acc#679" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#679.itm(1)} -pin  "ACC1:acc#679" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#679.itm(2)} -pin  "ACC1:acc#679" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#679.itm(3)} -pin  "ACC1:acc#679" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load inst "ACC1:acc#678" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 53246 -attr oid 1302 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#678" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#558.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#678" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#558.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#678" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#558.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#678" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#558.itm}
+load net {ACC1:acc#673.cse(0)} -pin  "ACC1:acc#678" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#673.cse(1)} -pin  "ACC1:acc#678" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#673.cse(2)} -pin  "ACC1:acc#678" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#678.itm(0)} -pin  "ACC1:acc#678" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(1)} -pin  "ACC1:acc#678" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(2)} -pin  "ACC1:acc#678" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(3)} -pin  "ACC1:acc#678" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(4)} -pin  "ACC1:acc#678" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load inst "ACC1:acc#682" "add(4,1,5,0,6)" "INTERFACE" -attr xrf 53247 -attr oid 1303 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#679.itm(0)} -pin  "ACC1:acc#682" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#679.itm(1)} -pin  "ACC1:acc#682" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#679.itm(2)} -pin  "ACC1:acc#682" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#679.itm(3)} -pin  "ACC1:acc#682" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#678.itm(0)} -pin  "ACC1:acc#682" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(1)} -pin  "ACC1:acc#682" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(2)} -pin  "ACC1:acc#682" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(3)} -pin  "ACC1:acc#682" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(4)} -pin  "ACC1:acc#682" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#682.itm(0)} -pin  "ACC1:acc#682" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(1)} -pin  "ACC1:acc#682" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(2)} -pin  "ACC1:acc#682" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(3)} -pin  "ACC1:acc#682" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(4)} -pin  "ACC1:acc#682" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(5)} -pin  "ACC1:acc#682" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load inst "ACC1:acc#685" "add(6,1,7,0,8)" "INTERFACE" -attr xrf 53248 -attr oid 1304 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#682.itm(0)} -pin  "ACC1:acc#685" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(1)} -pin  "ACC1:acc#685" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(2)} -pin  "ACC1:acc#685" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(3)} -pin  "ACC1:acc#685" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(4)} -pin  "ACC1:acc#685" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(5)} -pin  "ACC1:acc#685" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#685" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {GND} -pin  "ACC1:acc#685" {B(1)} -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#685" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {GND} -pin  "ACC1:acc#685" {B(3)} -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#685" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {GND} -pin  "ACC1:acc#685" {B(5)} -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#685" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {ACC1:acc#685.itm(0)} -pin  "ACC1:acc#685" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(1)} -pin  "ACC1:acc#685" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(2)} -pin  "ACC1:acc#685" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(3)} -pin  "ACC1:acc#685" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(4)} -pin  "ACC1:acc#685" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(5)} -pin  "ACC1:acc#685" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(6)} -pin  "ACC1:acc#685" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(7)} -pin  "ACC1:acc#685" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load inst "ACC1:acc#671" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53249 -attr oid 1305 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#671} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#671" {A(0)} -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#671" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#671" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {ACC1-1:and#3.cse.sva} -pin  "ACC1:acc#671" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1482.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#671" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1482.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#671" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1482.itm}
+load net {ACC1:acc#671.itm(0)} -pin  "ACC1:acc#671" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#671.itm}
+load net {ACC1:acc#671.itm(1)} -pin  "ACC1:acc#671" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#671.itm}
+load net {ACC1:acc#671.itm(2)} -pin  "ACC1:acc#671" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#671.itm}
+load net {ACC1:acc#671.itm(3)} -pin  "ACC1:acc#671" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#671.itm}
+load inst "ACC1:acc#677" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53250 -attr oid 1306 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#673.cse(0)} -pin  "ACC1:acc#677" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#673.cse(1)} -pin  "ACC1:acc#677" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#673.cse(2)} -pin  "ACC1:acc#677" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#671.itm(1)} -pin  "ACC1:acc#677" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#154.itm}
+load net {ACC1:acc#671.itm(2)} -pin  "ACC1:acc#677" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#154.itm}
+load net {ACC1:acc#671.itm(3)} -pin  "ACC1:acc#677" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#154.itm}
+load net {ACC1:acc#677.itm(0)} -pin  "ACC1:acc#677" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#677.itm(1)} -pin  "ACC1:acc#677" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#677.itm(2)} -pin  "ACC1:acc#677" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#677.itm(3)} -pin  "ACC1:acc#677" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load inst "ACC1:acc#681" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 53251 -attr oid 1307 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#681" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#891.itm}
+load net {GND} -pin  "ACC1:acc#681" {A(1)} -attr @path {/sobel/sobel:core/conc#891.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#681" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#891.itm}
+load net {GND} -pin  "ACC1:acc#681" {A(3)} -attr @path {/sobel/sobel:core/conc#891.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#681" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#891.itm}
+load net {ACC1:acc#677.itm(0)} -pin  "ACC1:acc#681" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#677.itm(1)} -pin  "ACC1:acc#681" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#677.itm(2)} -pin  "ACC1:acc#681" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#677.itm(3)} -pin  "ACC1:acc#681" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#681.itm(0)} -pin  "ACC1:acc#681" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(1)} -pin  "ACC1:acc#681" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(2)} -pin  "ACC1:acc#681" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(3)} -pin  "ACC1:acc#681" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(4)} -pin  "ACC1:acc#681" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(5)} -pin  "ACC1:acc#681" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load inst "ACC1:acc#684" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 53252 -attr oid 1308 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {ACC1:acc#681.itm(0)} -pin  "ACC1:acc#684" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(1)} -pin  "ACC1:acc#684" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(2)} -pin  "ACC1:acc#684" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(3)} -pin  "ACC1:acc#684" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(4)} -pin  "ACC1:acc#684" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(5)} -pin  "ACC1:acc#684" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#684.itm(0)} -pin  "ACC1:acc#684" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(1)} -pin  "ACC1:acc#684" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(2)} -pin  "ACC1:acc#684" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(3)} -pin  "ACC1:acc#684" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(4)} -pin  "ACC1:acc#684" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(5)} -pin  "ACC1:acc#684" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(6)} -pin  "ACC1:acc#684" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(7)} -pin  "ACC1:acc#684" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load inst "ACC1:acc#687" "add(8,1,8,0,10)" "INTERFACE" -attr xrf 53253 -attr oid 1309 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#685.itm(0)} -pin  "ACC1:acc#687" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(1)} -pin  "ACC1:acc#687" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(2)} -pin  "ACC1:acc#687" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(3)} -pin  "ACC1:acc#687" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(4)} -pin  "ACC1:acc#687" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(5)} -pin  "ACC1:acc#687" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(6)} -pin  "ACC1:acc#687" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(7)} -pin  "ACC1:acc#687" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#684.itm(0)} -pin  "ACC1:acc#687" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(1)} -pin  "ACC1:acc#687" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(2)} -pin  "ACC1:acc#687" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(3)} -pin  "ACC1:acc#687" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(4)} -pin  "ACC1:acc#687" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(5)} -pin  "ACC1:acc#687" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(6)} -pin  "ACC1:acc#687" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(7)} -pin  "ACC1:acc#687" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#687.itm(0)} -pin  "ACC1:acc#687" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(1)} -pin  "ACC1:acc#687" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(2)} -pin  "ACC1:acc#687" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(3)} -pin  "ACC1:acc#687" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(4)} -pin  "ACC1:acc#687" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(5)} -pin  "ACC1:acc#687" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(6)} -pin  "ACC1:acc#687" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(7)} -pin  "ACC1:acc#687" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(8)} -pin  "ACC1:acc#687" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(9)} -pin  "ACC1:acc#687" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load inst "ACC1:acc#690" "add(10,0,10,1,11)" "INTERFACE" -attr xrf 53254 -attr oid 1310 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,12)"
+load net {ACC1:acc#688.itm(0)} -pin  "ACC1:acc#690" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(1)} -pin  "ACC1:acc#690" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(2)} -pin  "ACC1:acc#690" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(3)} -pin  "ACC1:acc#690" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(4)} -pin  "ACC1:acc#690" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(5)} -pin  "ACC1:acc#690" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(6)} -pin  "ACC1:acc#690" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(7)} -pin  "ACC1:acc#690" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(8)} -pin  "ACC1:acc#690" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(9)} -pin  "ACC1:acc#690" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#687.itm(0)} -pin  "ACC1:acc#690" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(1)} -pin  "ACC1:acc#690" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(2)} -pin  "ACC1:acc#690" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(3)} -pin  "ACC1:acc#690" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(4)} -pin  "ACC1:acc#690" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(5)} -pin  "ACC1:acc#690" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(6)} -pin  "ACC1:acc#690" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(7)} -pin  "ACC1:acc#690" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(8)} -pin  "ACC1:acc#690" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(9)} -pin  "ACC1:acc#690" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#690.itm(0)} -pin  "ACC1:acc#690" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(1)} -pin  "ACC1:acc#690" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(2)} -pin  "ACC1:acc#690" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(3)} -pin  "ACC1:acc#690" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(4)} -pin  "ACC1:acc#690" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(5)} -pin  "ACC1:acc#690" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(6)} -pin  "ACC1:acc#690" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(7)} -pin  "ACC1:acc#690" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(8)} -pin  "ACC1:acc#690" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(9)} -pin  "ACC1:acc#690" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(10)} -pin  "ACC1:acc#690" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load inst "ACC1:acc#718" "add(1,0,2,0,3)" "INTERFACE" -attr xrf 53255 -attr oid 1311 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#718} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,3)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#718" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#10.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#718" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1640.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#718" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1640.itm}
+load net {ACC1:acc#718.itm(0)} -pin  "ACC1:acc#718" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#718.itm}
+load net {ACC1:acc#718.itm(1)} -pin  "ACC1:acc#718" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#718.itm}
+load net {ACC1:acc#718.itm(2)} -pin  "ACC1:acc#718" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#718.itm}
+load inst "ACC1-1:acc#2" "add(11,-1,11,-1,11)" "INTERFACE" -attr xrf 53256 -attr oid 1312 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#690.itm(0)} -pin  "ACC1-1:acc#2" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(1)} -pin  "ACC1-1:acc#2" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(2)} -pin  "ACC1-1:acc#2" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(3)} -pin  "ACC1-1:acc#2" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(4)} -pin  "ACC1-1:acc#2" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(5)} -pin  "ACC1-1:acc#2" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(6)} -pin  "ACC1-1:acc#2" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(7)} -pin  "ACC1-1:acc#2" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(8)} -pin  "ACC1-1:acc#2" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(9)} -pin  "ACC1-1:acc#2" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(10)} -pin  "ACC1-1:acc#2" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#718.itm(0)} -pin  "ACC1-1:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {ACC1:acc#718.itm(1)} -pin  "ACC1-1:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {ACC1:acc#718.itm(2)} -pin  "ACC1-1:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {GND} -pin  "ACC1-1:acc#2" {B(4)} -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {GND} -pin  "ACC1-1:acc#2" {B(6)} -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {GND} -pin  "ACC1-1:acc#2" {B(8)} -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {GND} -pin  "ACC1-1:acc#2" {B(9)} -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {ACC1-1:acc#2.itm(0)} -pin  "ACC1-1:acc#2" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(1)} -pin  "ACC1-1:acc#2" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(2)} -pin  "ACC1-1:acc#2" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(3)} -pin  "ACC1-1:acc#2" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(4)} -pin  "ACC1-1:acc#2" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(5)} -pin  "ACC1-1:acc#2" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(6)} -pin  "ACC1-1:acc#2" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(7)} -pin  "ACC1-1:acc#2" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(8)} -pin  "ACC1-1:acc#2" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(9)} -pin  "ACC1-1:acc#2" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(10)} -pin  "ACC1-1:acc#2" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load inst "ACC1-1:not#320" "not(1)" "INTERFACE" -attr xrf 53257 -attr oid 1313 -attr @path {/sobel/sobel:core/ACC1-1:not#320} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:not#320" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#49.itm}
+load net {ACC1-1:not#320.itm} -pin  "ACC1-1:not#320" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#320.itm}
+load inst "ACC1-1:nand#4" "nand(2,1)" "INTERFACE" -attr xrf 53258 -attr oid 1314 -attr @path {/sobel/sobel:core/ACC1-1:nand#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#359.itm(2)} -pin  "ACC1-1:nand#4" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#40.sva)#2.itm}
+load net {ACC1-1:not#320.itm} -pin  "ACC1-1:nand#4" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#320.itm}
+load net {ACC1-1:nand#4.itm} -pin  "ACC1-1:nand#4" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:nand#4.itm}
+load inst "ACC1:acc#696" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53259 -attr oid 1315 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#696} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#696" {A(0)} -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#696" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#696" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {ACC1-1:nand#4.itm} -pin  "ACC1:acc#696" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1485.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#696" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1485.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#696" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1485.itm}
+load net {ACC1:acc#696.itm(0)} -pin  "ACC1:acc#696" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#696.itm}
+load net {ACC1:acc#696.itm(1)} -pin  "ACC1:acc#696" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#696.itm}
+load net {ACC1:acc#696.itm(2)} -pin  "ACC1:acc#696" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#696.itm}
+load net {ACC1:acc#696.itm(3)} -pin  "ACC1:acc#696" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#696.itm}
+load inst "ACC1-1:not#321" "not(1)" "INTERFACE" -attr xrf 53260 -attr oid 1316 -attr @path {/sobel/sobel:core/ACC1-1:not#321} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#358.itm(3)} -pin  "ACC1-1:not#321" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#38.sva)#4.itm}
+load net {ACC1-1:not#321.itm} -pin  "ACC1-1:not#321" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#321.itm}
+load inst "ACC1:acc#695" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53261 -attr oid 1317 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#695} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#695" {A(0)} -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#695" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#695" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {ACC1-1:not#321.itm} -pin  "ACC1:acc#695" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1487.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#695" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1487.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#695" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1487.itm}
+load net {ACC1:acc#695.itm(0)} -pin  "ACC1:acc#695" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#695.itm}
+load net {ACC1:acc#695.itm(1)} -pin  "ACC1:acc#695" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#695.itm}
+load net {ACC1:acc#695.itm(2)} -pin  "ACC1:acc#695" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#695.itm}
+load net {ACC1:acc#695.itm(3)} -pin  "ACC1:acc#695" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#695.itm}
+load inst "ACC1:acc#702" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53262 -attr oid 1318 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#696.itm(1)} -pin  "ACC1:acc#702" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#160.itm}
+load net {ACC1:acc#696.itm(2)} -pin  "ACC1:acc#702" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#160.itm}
+load net {ACC1:acc#696.itm(3)} -pin  "ACC1:acc#702" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#160.itm}
+load net {ACC1:acc#695.itm(1)} -pin  "ACC1:acc#702" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#159.itm}
+load net {ACC1:acc#695.itm(2)} -pin  "ACC1:acc#702" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#159.itm}
+load net {ACC1:acc#695.itm(3)} -pin  "ACC1:acc#702" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#159.itm}
+load net {ACC1:acc#702.itm(0)} -pin  "ACC1:acc#702" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#702.itm(1)} -pin  "ACC1:acc#702" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#702.itm(2)} -pin  "ACC1:acc#702" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#702.itm(3)} -pin  "ACC1:acc#702" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load inst "ACC1:acc#694" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53263 -attr oid 1319 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#694} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#694" {A(0)} -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#694" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#694" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {ACC1:acc#358.itm(2)} -pin  "ACC1:acc#694" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1489.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#694" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1489.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#694" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1489.itm}
+load net {ACC1:acc#694.itm(0)} -pin  "ACC1:acc#694" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#694.itm}
+load net {ACC1:acc#694.itm(1)} -pin  "ACC1:acc#694" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#694.itm}
+load net {ACC1:acc#694.itm(2)} -pin  "ACC1:acc#694" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#694.itm}
+load net {ACC1:acc#694.itm(3)} -pin  "ACC1:acc#694" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#694.itm}
+load inst "ACC1:acc#693" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53264 -attr oid 1320 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#693} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#693" {A(0)} -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#693" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#693" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {ACC1:acc#217.psp#2.sva(2)} -pin  "ACC1:acc#693" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1491.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#693" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1491.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#693" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1491.itm}
+load net {ACC1:acc#693.itm(0)} -pin  "ACC1:acc#693" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#693.itm}
+load net {ACC1:acc#693.itm(1)} -pin  "ACC1:acc#693" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#693.itm}
+load net {ACC1:acc#693.itm(2)} -pin  "ACC1:acc#693" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#693.itm}
+load net {ACC1:acc#693.itm(3)} -pin  "ACC1:acc#693" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#693.itm}
+load inst "ACC1:acc#701" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53265 -attr oid 1321 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#694.itm(1)} -pin  "ACC1:acc#701" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#158.itm}
+load net {ACC1:acc#694.itm(2)} -pin  "ACC1:acc#701" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#158.itm}
+load net {ACC1:acc#694.itm(3)} -pin  "ACC1:acc#701" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#158.itm}
+load net {ACC1:acc#693.itm(1)} -pin  "ACC1:acc#701" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#157.itm}
+load net {ACC1:acc#693.itm(2)} -pin  "ACC1:acc#701" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#157.itm}
+load net {ACC1:acc#693.itm(3)} -pin  "ACC1:acc#701" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#157.itm}
+load net {ACC1:acc#701.itm(0)} -pin  "ACC1:acc#701" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#701.itm(1)} -pin  "ACC1:acc#701" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#701.itm(2)} -pin  "ACC1:acc#701" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#701.itm(3)} -pin  "ACC1:acc#701" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load inst "ACC1:acc#706" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53266 -attr oid 1322 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#702.itm(0)} -pin  "ACC1:acc#706" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#702.itm(1)} -pin  "ACC1:acc#706" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#702.itm(2)} -pin  "ACC1:acc#706" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#702.itm(3)} -pin  "ACC1:acc#706" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#701.itm(0)} -pin  "ACC1:acc#706" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#701.itm(1)} -pin  "ACC1:acc#706" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#701.itm(2)} -pin  "ACC1:acc#706" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#701.itm(3)} -pin  "ACC1:acc#706" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#706.itm(0)} -pin  "ACC1:acc#706" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(1)} -pin  "ACC1:acc#706" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(2)} -pin  "ACC1:acc#706" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(3)} -pin  "ACC1:acc#706" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(4)} -pin  "ACC1:acc#706" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load inst "ACC1:acc#709" "add(6,0,5,0,7)" "INTERFACE" -attr xrf 53267 -attr oid 1323 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#709" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#709" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {GND} -pin  "ACC1:acc#709" {A(2)} -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {acc#20.psp#2.sva(5)} -pin  "ACC1:acc#709" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {GND} -pin  "ACC1:acc#709" {A(4)} -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {acc#20.psp#2.sva(7)} -pin  "ACC1:acc#709" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {ACC1:acc#706.itm(0)} -pin  "ACC1:acc#709" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(1)} -pin  "ACC1:acc#709" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(2)} -pin  "ACC1:acc#709" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(3)} -pin  "ACC1:acc#709" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(4)} -pin  "ACC1:acc#709" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#709.itm(0)} -pin  "ACC1:acc#709" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(1)} -pin  "ACC1:acc#709" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(2)} -pin  "ACC1:acc#709" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(3)} -pin  "ACC1:acc#709" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(4)} -pin  "ACC1:acc#709" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(5)} -pin  "ACC1:acc#709" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(6)} -pin  "ACC1:acc#709" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load inst "ACC1:acc#712" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 53268 -attr oid 1324 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {acc#20.psp#2.sva(5)} -pin  "ACC1:acc#712" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {acc#20.psp#2.sva(5)} -pin  "ACC1:acc#712" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {GND} -pin  "ACC1:acc#712" {A(2)} -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1:acc#712" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {GND} -pin  "ACC1:acc#712" {A(4)} -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1:acc#712" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {GND} -pin  "ACC1:acc#712" {A(6)} -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1:acc#712" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {ACC1:acc#709.itm(0)} -pin  "ACC1:acc#712" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(1)} -pin  "ACC1:acc#712" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(2)} -pin  "ACC1:acc#712" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(3)} -pin  "ACC1:acc#712" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(4)} -pin  "ACC1:acc#712" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(5)} -pin  "ACC1:acc#712" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(6)} -pin  "ACC1:acc#712" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#712.itm(0)} -pin  "ACC1:acc#712" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(1)} -pin  "ACC1:acc#712" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(2)} -pin  "ACC1:acc#712" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(3)} -pin  "ACC1:acc#712" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(4)} -pin  "ACC1:acc#712" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(5)} -pin  "ACC1:acc#712" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(6)} -pin  "ACC1:acc#712" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(7)} -pin  "ACC1:acc#712" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load inst "ACC1:acc#714" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 53269 -attr oid 1325 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,11)"
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1:acc#714" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {GND} -pin  "ACC1:acc#714" {A(1)} -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1:acc#714" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {GND} -pin  "ACC1:acc#714" {A(3)} -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1:acc#714" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {GND} -pin  "ACC1:acc#714" {A(5)} -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1:acc#714" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {GND} -pin  "ACC1:acc#714" {A(7)} -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1:acc#714" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {ACC1:acc#712.itm(0)} -pin  "ACC1:acc#714" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(1)} -pin  "ACC1:acc#714" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(2)} -pin  "ACC1:acc#714" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(3)} -pin  "ACC1:acc#714" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(4)} -pin  "ACC1:acc#714" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(5)} -pin  "ACC1:acc#714" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(6)} -pin  "ACC1:acc#714" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(7)} -pin  "ACC1:acc#714" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#714.itm(0)} -pin  "ACC1:acc#714" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(1)} -pin  "ACC1:acc#714" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(2)} -pin  "ACC1:acc#714" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(3)} -pin  "ACC1:acc#714" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(4)} -pin  "ACC1:acc#714" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(5)} -pin  "ACC1:acc#714" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(6)} -pin  "ACC1:acc#714" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(7)} -pin  "ACC1:acc#714" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(8)} -pin  "ACC1:acc#714" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(9)} -pin  "ACC1:acc#714" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load inst "ACC1:acc#691" "add(3,1,2,1,4)" "INTERFACE" -attr xrf 53270 -attr oid 1326 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#691} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#691" {A(0)} -attr @path {/sobel/sobel:core/conc#901.itm}
+load net {acc#20.psp#2.sva(3)} -pin  "ACC1:acc#691" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#901.itm}
+load net {PWR} -pin  "ACC1:acc#691" {A(2)} -attr @path {/sobel/sobel:core/conc#901.itm}
+load net {acc#20.psp#2.sva(4)} -pin  "ACC1:acc#691" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1435.itm}
+load net {ACC1:acc#217.psp#2.sva(3)} -pin  "ACC1:acc#691" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1435.itm}
+load net {ACC1:acc#691.itm(0)} -pin  "ACC1:acc#691" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#691.itm}
+load net {ACC1:acc#691.itm(1)} -pin  "ACC1:acc#691" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#691.itm}
+load net {ACC1:acc#691.itm(2)} -pin  "ACC1:acc#691" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#691.itm}
+load net {ACC1:acc#691.itm(3)} -pin  "ACC1:acc#691" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#691.itm}
+load inst "ACC1:acc#700" "add(3,-1,2,1,3)" "INTERFACE" -attr xrf 53271 -attr oid 1327 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {ACC1:acc#691.itm(1)} -pin  "ACC1:acc#700" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#155.itm}
+load net {ACC1:acc#691.itm(2)} -pin  "ACC1:acc#700" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#155.itm}
+load net {ACC1:acc#691.itm(3)} -pin  "ACC1:acc#700" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#155.itm}
+load net {ACC1:acc#223.psp#1.sva(1)} -pin  "ACC1:acc#700" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp#1.sva)#2.itm}
+load net {ACC1:acc#223.psp#1.sva(2)} -pin  "ACC1:acc#700" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp#1.sva)#2.itm}
+load net {ACC1:acc#700.itm(0)} -pin  "ACC1:acc#700" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load net {ACC1:acc#700.itm(1)} -pin  "ACC1:acc#700" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load net {ACC1:acc#700.itm(2)} -pin  "ACC1:acc#700" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load inst "ACC1:acc#692" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 53272 -attr oid 1328 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#692" {A(0)} -attr @path {/sobel/sobel:core/conc#902.itm}
+load net {acc#20.psp#2.sva(1)} -pin  "ACC1:acc#692" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#902.itm}
+load net {acc#20.psp#2.sva(3)} -pin  "ACC1:acc#692" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#902.itm}
+load net {ACC1:acc#217.psp#2.sva(1)} -pin  "ACC1:acc#692" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1437.itm}
+load net {acc#20.psp#2.sva(2)} -pin  "ACC1:acc#692" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1437.itm}
+load net {ACC1:acc#217.psp#2.sva(3)} -pin  "ACC1:acc#692" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1437.itm}
+load net {ACC1:acc#692.itm(0)} -pin  "ACC1:acc#692" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692.itm}
+load net {ACC1:acc#692.itm(1)} -pin  "ACC1:acc#692" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692.itm}
+load net {ACC1:acc#692.itm(2)} -pin  "ACC1:acc#692" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692.itm}
+load net {ACC1:acc#692.itm(3)} -pin  "ACC1:acc#692" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692.itm}
+load net {ACC1:acc#692.itm(4)} -pin  "ACC1:acc#692" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692.itm}
+load inst "ACC1:acc#705" "add(3,1,4,-1,4)" "INTERFACE" -attr xrf 53273 -attr oid 1329 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#700.itm(0)} -pin  "ACC1:acc#705" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load net {ACC1:acc#700.itm(1)} -pin  "ACC1:acc#705" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load net {ACC1:acc#700.itm(2)} -pin  "ACC1:acc#705" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load net {ACC1:acc#692.itm(1)} -pin  "ACC1:acc#705" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#156.itm}
+load net {ACC1:acc#692.itm(2)} -pin  "ACC1:acc#705" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#156.itm}
+load net {ACC1:acc#692.itm(3)} -pin  "ACC1:acc#705" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#156.itm}
+load net {ACC1:acc#692.itm(4)} -pin  "ACC1:acc#705" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#156.itm}
+load net {ACC1:acc#705.itm(0)} -pin  "ACC1:acc#705" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#705.itm(1)} -pin  "ACC1:acc#705" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#705.itm(2)} -pin  "ACC1:acc#705" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#705.itm(3)} -pin  "ACC1:acc#705" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load inst "ACC1:acc#704" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 53274 -attr oid 1330 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#704" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#594.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#704" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#594.itm}
+load net {acc#20.psp#2.sva(4)} -pin  "ACC1:acc#704" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#594.itm}
+load net {acc#20.psp#2.sva(7)} -pin  "ACC1:acc#704" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#594.itm}
+load net {ACC1:acc#699.cse(0)} -pin  "ACC1:acc#704" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#699.cse(1)} -pin  "ACC1:acc#704" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#699.cse(2)} -pin  "ACC1:acc#704" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#704.itm(0)} -pin  "ACC1:acc#704" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(1)} -pin  "ACC1:acc#704" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(2)} -pin  "ACC1:acc#704" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(3)} -pin  "ACC1:acc#704" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(4)} -pin  "ACC1:acc#704" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load inst "ACC1:acc#708" "add(4,1,5,0,6)" "INTERFACE" -attr xrf 53275 -attr oid 1331 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#705.itm(0)} -pin  "ACC1:acc#708" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#705.itm(1)} -pin  "ACC1:acc#708" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#705.itm(2)} -pin  "ACC1:acc#708" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#705.itm(3)} -pin  "ACC1:acc#708" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#704.itm(0)} -pin  "ACC1:acc#708" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(1)} -pin  "ACC1:acc#708" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(2)} -pin  "ACC1:acc#708" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(3)} -pin  "ACC1:acc#708" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(4)} -pin  "ACC1:acc#708" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#708.itm(0)} -pin  "ACC1:acc#708" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(1)} -pin  "ACC1:acc#708" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(2)} -pin  "ACC1:acc#708" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(3)} -pin  "ACC1:acc#708" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(4)} -pin  "ACC1:acc#708" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(5)} -pin  "ACC1:acc#708" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load inst "ACC1:acc#711" "add(6,1,7,0,8)" "INTERFACE" -attr xrf 53276 -attr oid 1332 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#708.itm(0)} -pin  "ACC1:acc#711" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(1)} -pin  "ACC1:acc#711" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(2)} -pin  "ACC1:acc#711" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(3)} -pin  "ACC1:acc#711" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(4)} -pin  "ACC1:acc#711" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(5)} -pin  "ACC1:acc#711" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {acc#20.psp#2.sva(8)} -pin  "ACC1:acc#711" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {GND} -pin  "ACC1:acc#711" {B(1)} -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {acc#20.psp#2.sva(8)} -pin  "ACC1:acc#711" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {GND} -pin  "ACC1:acc#711" {B(3)} -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {acc#20.psp#2.sva(8)} -pin  "ACC1:acc#711" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {GND} -pin  "ACC1:acc#711" {B(5)} -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {acc#20.psp#2.sva(8)} -pin  "ACC1:acc#711" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {ACC1:acc#711.itm(0)} -pin  "ACC1:acc#711" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(1)} -pin  "ACC1:acc#711" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(2)} -pin  "ACC1:acc#711" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(3)} -pin  "ACC1:acc#711" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(4)} -pin  "ACC1:acc#711" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(5)} -pin  "ACC1:acc#711" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(6)} -pin  "ACC1:acc#711" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(7)} -pin  "ACC1:acc#711" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load inst "ACC1-1:not#156" "not(1)" "INTERFACE" -attr xrf 53277 -attr oid 1333 -attr @path {/sobel/sobel:core/ACC1-1:not#156} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#359.itm(2)} -pin  "ACC1-1:not#156" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#40.sva).itm}
+load net {ACC1-1:not#156.itm} -pin  "ACC1-1:not#156" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#156.itm}
+load inst "ACC1-1:and#9" "and(3,1)" "INTERFACE" -attr xrf 53278 -attr oid 1334 -attr @path {/sobel/sobel:core/ACC1-1:and#9} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:and#9" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#37.itm}
+load net {ACC1-1:not#156.itm} -pin  "ACC1-1:and#9" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#156.itm}
+load net {ACC1:acc#359.itm(1)} -pin  "ACC1-1:and#9" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#40.sva)#1.itm}
+load net {ACC1-1:and#9.itm} -pin  "ACC1-1:and#9" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#9.itm}
+load inst "ACC1:acc#697" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53279 -attr oid 1335 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#697} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#697" {A(0)} -attr @path {/sobel/sobel:core/exs#91.itm}
+load net {acc#20.psp#2.sva(7)} -pin  "ACC1:acc#697" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#91.itm}
+load net {acc#20.psp#2.sva(7)} -pin  "ACC1:acc#697" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#91.itm}
+load net {ACC1-1:and#9.itm} -pin  "ACC1:acc#697" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1493.itm}
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1:acc#697" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1493.itm}
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1:acc#697" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1493.itm}
+load net {ACC1:acc#697.itm(0)} -pin  "ACC1:acc#697" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#697.itm}
+load net {ACC1:acc#697.itm(1)} -pin  "ACC1:acc#697" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#697.itm}
+load net {ACC1:acc#697.itm(2)} -pin  "ACC1:acc#697" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#697.itm}
+load net {ACC1:acc#697.itm(3)} -pin  "ACC1:acc#697" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#697.itm}
+load inst "ACC1:acc#703" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53280 -attr oid 1336 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#699.cse(0)} -pin  "ACC1:acc#703" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#699.cse(1)} -pin  "ACC1:acc#703" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#699.cse(2)} -pin  "ACC1:acc#703" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#697.itm(1)} -pin  "ACC1:acc#703" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#161.itm}
+load net {ACC1:acc#697.itm(2)} -pin  "ACC1:acc#703" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#161.itm}
+load net {ACC1:acc#697.itm(3)} -pin  "ACC1:acc#703" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#161.itm}
+load net {ACC1:acc#703.itm(0)} -pin  "ACC1:acc#703" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#703.itm(1)} -pin  "ACC1:acc#703" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#703.itm(2)} -pin  "ACC1:acc#703" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#703.itm(3)} -pin  "ACC1:acc#703" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load inst "ACC1:acc#707" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 53281 -attr oid 1337 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {acc#20.psp#2.sva(6)} -pin  "ACC1:acc#707" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#904.itm}
+load net {GND} -pin  "ACC1:acc#707" {A(1)} -attr @path {/sobel/sobel:core/conc#904.itm}
+load net {acc#20.psp#2.sva(6)} -pin  "ACC1:acc#707" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#904.itm}
+load net {GND} -pin  "ACC1:acc#707" {A(3)} -attr @path {/sobel/sobel:core/conc#904.itm}
+load net {acc#20.psp#2.sva(6)} -pin  "ACC1:acc#707" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#904.itm}
+load net {ACC1:acc#703.itm(0)} -pin  "ACC1:acc#707" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#703.itm(1)} -pin  "ACC1:acc#707" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#703.itm(2)} -pin  "ACC1:acc#707" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#703.itm(3)} -pin  "ACC1:acc#707" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#707.itm(0)} -pin  "ACC1:acc#707" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(1)} -pin  "ACC1:acc#707" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(2)} -pin  "ACC1:acc#707" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(3)} -pin  "ACC1:acc#707" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(4)} -pin  "ACC1:acc#707" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(5)} -pin  "ACC1:acc#707" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load inst "ACC1:acc#710" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 53282 -attr oid 1338 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {ACC1:acc#707.itm(0)} -pin  "ACC1:acc#710" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(1)} -pin  "ACC1:acc#710" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(2)} -pin  "ACC1:acc#710" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(3)} -pin  "ACC1:acc#710" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(4)} -pin  "ACC1:acc#710" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(5)} -pin  "ACC1:acc#710" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#710.itm(0)} -pin  "ACC1:acc#710" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(1)} -pin  "ACC1:acc#710" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(2)} -pin  "ACC1:acc#710" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(3)} -pin  "ACC1:acc#710" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(4)} -pin  "ACC1:acc#710" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(5)} -pin  "ACC1:acc#710" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(6)} -pin  "ACC1:acc#710" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(7)} -pin  "ACC1:acc#710" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load inst "ACC1:acc#713" "add(8,1,8,0,10)" "INTERFACE" -attr xrf 53283 -attr oid 1339 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#711.itm(0)} -pin  "ACC1:acc#713" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(1)} -pin  "ACC1:acc#713" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(2)} -pin  "ACC1:acc#713" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(3)} -pin  "ACC1:acc#713" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(4)} -pin  "ACC1:acc#713" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(5)} -pin  "ACC1:acc#713" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(6)} -pin  "ACC1:acc#713" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(7)} -pin  "ACC1:acc#713" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#710.itm(0)} -pin  "ACC1:acc#713" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(1)} -pin  "ACC1:acc#713" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(2)} -pin  "ACC1:acc#713" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(3)} -pin  "ACC1:acc#713" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(4)} -pin  "ACC1:acc#713" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(5)} -pin  "ACC1:acc#713" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(6)} -pin  "ACC1:acc#713" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(7)} -pin  "ACC1:acc#713" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#713.itm(0)} -pin  "ACC1:acc#713" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(1)} -pin  "ACC1:acc#713" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(2)} -pin  "ACC1:acc#713" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(3)} -pin  "ACC1:acc#713" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(4)} -pin  "ACC1:acc#713" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(5)} -pin  "ACC1:acc#713" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(6)} -pin  "ACC1:acc#713" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(7)} -pin  "ACC1:acc#713" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(8)} -pin  "ACC1:acc#713" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(9)} -pin  "ACC1:acc#713" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load inst "ACC1:acc#716" "add(10,0,10,1,11)" "INTERFACE" -attr xrf 53284 -attr oid 1340 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,12)"
+load net {ACC1:acc#714.itm(0)} -pin  "ACC1:acc#716" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(1)} -pin  "ACC1:acc#716" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(2)} -pin  "ACC1:acc#716" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(3)} -pin  "ACC1:acc#716" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(4)} -pin  "ACC1:acc#716" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(5)} -pin  "ACC1:acc#716" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(6)} -pin  "ACC1:acc#716" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(7)} -pin  "ACC1:acc#716" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(8)} -pin  "ACC1:acc#716" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(9)} -pin  "ACC1:acc#716" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#713.itm(0)} -pin  "ACC1:acc#716" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(1)} -pin  "ACC1:acc#716" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(2)} -pin  "ACC1:acc#716" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(3)} -pin  "ACC1:acc#716" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(4)} -pin  "ACC1:acc#716" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(5)} -pin  "ACC1:acc#716" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(6)} -pin  "ACC1:acc#716" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(7)} -pin  "ACC1:acc#716" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(8)} -pin  "ACC1:acc#716" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(9)} -pin  "ACC1:acc#716" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#716.itm(0)} -pin  "ACC1:acc#716" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(1)} -pin  "ACC1:acc#716" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(2)} -pin  "ACC1:acc#716" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(3)} -pin  "ACC1:acc#716" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(4)} -pin  "ACC1:acc#716" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(5)} -pin  "ACC1:acc#716" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(6)} -pin  "ACC1:acc#716" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(7)} -pin  "ACC1:acc#716" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(8)} -pin  "ACC1:acc#716" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(9)} -pin  "ACC1:acc#716" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(10)} -pin  "ACC1:acc#716" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load inst "ACC1:acc#720" "add(1,0,2,0,3)" "INTERFACE" -attr xrf 53285 -attr oid 1341 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#720} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,3)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#720" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#13.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#720" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1654.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#720" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1654.itm}
+load net {ACC1:acc#720.itm(0)} -pin  "ACC1:acc#720" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#720.itm}
+load net {ACC1:acc#720.itm(1)} -pin  "ACC1:acc#720" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#720.itm}
+load net {ACC1:acc#720.itm(2)} -pin  "ACC1:acc#720" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#720.itm}
+load inst "ACC1-1:acc#27" "add(11,-1,11,-1,11)" "INTERFACE" -attr xrf 53286 -attr oid 1342 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#716.itm(0)} -pin  "ACC1-1:acc#27" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(1)} -pin  "ACC1-1:acc#27" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(2)} -pin  "ACC1-1:acc#27" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(3)} -pin  "ACC1-1:acc#27" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(4)} -pin  "ACC1-1:acc#27" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(5)} -pin  "ACC1-1:acc#27" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(6)} -pin  "ACC1-1:acc#27" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(7)} -pin  "ACC1-1:acc#27" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(8)} -pin  "ACC1-1:acc#27" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(9)} -pin  "ACC1-1:acc#27" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(10)} -pin  "ACC1-1:acc#27" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#720.itm(0)} -pin  "ACC1-1:acc#27" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {ACC1:acc#720.itm(1)} -pin  "ACC1-1:acc#27" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {ACC1:acc#720.itm(2)} -pin  "ACC1-1:acc#27" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:acc#27" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {GND} -pin  "ACC1-1:acc#27" {B(4)} -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:acc#27" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {GND} -pin  "ACC1-1:acc#27" {B(6)} -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:acc#27" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {GND} -pin  "ACC1-1:acc#27" {B(8)} -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {GND} -pin  "ACC1-1:acc#27" {B(9)} -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:acc#27" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {ACC1-1:acc#27.itm(0)} -pin  "ACC1-1:acc#27" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(1)} -pin  "ACC1-1:acc#27" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(2)} -pin  "ACC1-1:acc#27" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(3)} -pin  "ACC1-1:acc#27" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(4)} -pin  "ACC1-1:acc#27" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(5)} -pin  "ACC1-1:acc#27" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(6)} -pin  "ACC1-1:acc#27" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(7)} -pin  "ACC1-1:acc#27" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(8)} -pin  "ACC1-1:acc#27" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(9)} -pin  "ACC1-1:acc#27" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(10)} -pin  "ACC1-1:acc#27" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load inst "ACC1:acc#653" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 53287 -attr oid 1343 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1-1:acc#2.itm(0)} -pin  "ACC1:acc#653" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(1)} -pin  "ACC1:acc#653" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(2)} -pin  "ACC1:acc#653" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(3)} -pin  "ACC1:acc#653" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(4)} -pin  "ACC1:acc#653" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(5)} -pin  "ACC1:acc#653" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(6)} -pin  "ACC1:acc#653" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(7)} -pin  "ACC1:acc#653" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(8)} -pin  "ACC1:acc#653" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(9)} -pin  "ACC1:acc#653" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(10)} -pin  "ACC1:acc#653" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#27.itm(0)} -pin  "ACC1:acc#653" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(1)} -pin  "ACC1:acc#653" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(2)} -pin  "ACC1:acc#653" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(3)} -pin  "ACC1:acc#653" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(4)} -pin  "ACC1:acc#653" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(5)} -pin  "ACC1:acc#653" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(6)} -pin  "ACC1:acc#653" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(7)} -pin  "ACC1:acc#653" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(8)} -pin  "ACC1:acc#653" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(9)} -pin  "ACC1:acc#653" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(10)} -pin  "ACC1:acc#653" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1:acc#653.itm(0)} -pin  "ACC1:acc#653" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(1)} -pin  "ACC1:acc#653" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(2)} -pin  "ACC1:acc#653" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(3)} -pin  "ACC1:acc#653" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(4)} -pin  "ACC1:acc#653" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(5)} -pin  "ACC1:acc#653" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(6)} -pin  "ACC1:acc#653" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(7)} -pin  "ACC1:acc#653" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(8)} -pin  "ACC1:acc#653" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(9)} -pin  "ACC1:acc#653" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(10)} -pin  "ACC1:acc#653" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(11)} -pin  "ACC1:acc#653" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load inst "ACC1:acc#659" "add(12,1,12,1,13)" "INTERFACE" -attr xrf 53288 -attr oid 1344 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1:acc#654.itm(0)} -pin  "ACC1:acc#659" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(1)} -pin  "ACC1:acc#659" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(2)} -pin  "ACC1:acc#659" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(3)} -pin  "ACC1:acc#659" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(4)} -pin  "ACC1:acc#659" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(5)} -pin  "ACC1:acc#659" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(6)} -pin  "ACC1:acc#659" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(7)} -pin  "ACC1:acc#659" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(8)} -pin  "ACC1:acc#659" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(9)} -pin  "ACC1:acc#659" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(10)} -pin  "ACC1:acc#659" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(11)} -pin  "ACC1:acc#659" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#653.itm(0)} -pin  "ACC1:acc#659" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(1)} -pin  "ACC1:acc#659" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(2)} -pin  "ACC1:acc#659" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(3)} -pin  "ACC1:acc#659" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(4)} -pin  "ACC1:acc#659" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(5)} -pin  "ACC1:acc#659" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(6)} -pin  "ACC1:acc#659" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(7)} -pin  "ACC1:acc#659" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(8)} -pin  "ACC1:acc#659" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(9)} -pin  "ACC1:acc#659" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(10)} -pin  "ACC1:acc#659" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(11)} -pin  "ACC1:acc#659" {B(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#659.itm(0)} -pin  "ACC1:acc#659" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(1)} -pin  "ACC1:acc#659" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(2)} -pin  "ACC1:acc#659" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(3)} -pin  "ACC1:acc#659" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(4)} -pin  "ACC1:acc#659" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(5)} -pin  "ACC1:acc#659" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(6)} -pin  "ACC1:acc#659" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(7)} -pin  "ACC1:acc#659" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(8)} -pin  "ACC1:acc#659" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(9)} -pin  "ACC1:acc#659" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(10)} -pin  "ACC1:acc#659" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(11)} -pin  "ACC1:acc#659" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(12)} -pin  "ACC1:acc#659" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load inst "reg(ACC1:acc#659.itm#1)" "reg(13,1,1,-1,0)" "INTERFACE" -attr xrf 53289 -attr oid 1345 -attr vt dc -attr @path {/sobel/sobel:core/reg(ACC1:acc#659.itm#1)}
+load net {ACC1:acc#659.itm(0)} -pin  "reg(ACC1:acc#659.itm#1)" {D(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(1)} -pin  "reg(ACC1:acc#659.itm#1)" {D(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(2)} -pin  "reg(ACC1:acc#659.itm#1)" {D(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(3)} -pin  "reg(ACC1:acc#659.itm#1)" {D(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(4)} -pin  "reg(ACC1:acc#659.itm#1)" {D(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(5)} -pin  "reg(ACC1:acc#659.itm#1)" {D(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(6)} -pin  "reg(ACC1:acc#659.itm#1)" {D(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(7)} -pin  "reg(ACC1:acc#659.itm#1)" {D(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(8)} -pin  "reg(ACC1:acc#659.itm#1)" {D(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(9)} -pin  "reg(ACC1:acc#659.itm#1)" {D(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(10)} -pin  "reg(ACC1:acc#659.itm#1)" {D(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(11)} -pin  "reg(ACC1:acc#659.itm#1)" {D(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(12)} -pin  "reg(ACC1:acc#659.itm#1)" {D(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_13}
+load net {clk} -pin  "reg(ACC1:acc#659.itm#1)" {clk} -attr xrf 53290 -attr oid 1346 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#659.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#659.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#659.itm#1(0)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(1)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(2)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(3)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(4)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(5)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(6)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(7)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(8)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(9)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(10)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(11)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(12)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load inst "ACC1:acc#572" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53291 -attr oid 1347 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#572" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1108.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#572" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1108.itm}
+load net {ACC1:acc#228.psp.sva(3)} -pin  "ACC1:acc#572" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1108.itm}
+load net {ACC1:acc#224.psp#1.sva(6)} -pin  "ACC1:acc#572" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1108.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#572" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1109.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#572" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1109.itm}
+load net {ACC1:acc#226.psp.sva(3)} -pin  "ACC1:acc#572" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1109.itm}
+load net {ACC1-1:acc#25.psp.sva(5)} -pin  "ACC1:acc#572" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1109.itm}
+load net {ACC1:acc#572.itm(0)} -pin  "ACC1:acc#572" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(1)} -pin  "ACC1:acc#572" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(2)} -pin  "ACC1:acc#572" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(3)} -pin  "ACC1:acc#572" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(4)} -pin  "ACC1:acc#572" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load inst "ACC1:acc#571" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53292 -attr oid 1348 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#571" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1110.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#571" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1110.itm}
+load net {ACC1:acc#224.psp#1.sva(3)} -pin  "ACC1:acc#571" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1110.itm}
+load net {ACC1-1:acc#25.psp.sva(7)} -pin  "ACC1:acc#571" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1110.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#571" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1111.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#571" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1111.itm}
+load net {ACC1-1:acc#25.psp.sva(4)} -pin  "ACC1:acc#571" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1111.itm}
+load net {acc#20.psp#1.sva(4)} -pin  "ACC1:acc#571" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1111.itm}
+load net {ACC1:acc#571.itm(0)} -pin  "ACC1:acc#571" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(1)} -pin  "ACC1:acc#571" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(2)} -pin  "ACC1:acc#571" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(3)} -pin  "ACC1:acc#571" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(4)} -pin  "ACC1:acc#571" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load inst "ACC1:acc#601" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 53293 -attr oid 1349 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#572.itm(0)} -pin  "ACC1:acc#601" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(1)} -pin  "ACC1:acc#601" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(2)} -pin  "ACC1:acc#601" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(3)} -pin  "ACC1:acc#601" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(4)} -pin  "ACC1:acc#601" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#571.itm(0)} -pin  "ACC1:acc#601" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(1)} -pin  "ACC1:acc#601" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(2)} -pin  "ACC1:acc#601" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(3)} -pin  "ACC1:acc#601" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(4)} -pin  "ACC1:acc#601" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#601.itm(0)} -pin  "ACC1:acc#601" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(1)} -pin  "ACC1:acc#601" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(2)} -pin  "ACC1:acc#601" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(3)} -pin  "ACC1:acc#601" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(4)} -pin  "ACC1:acc#601" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(5)} -pin  "ACC1:acc#601" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load inst "ACC1:not#383" "not(1)" "INTERFACE" -attr xrf 53294 -attr oid 1350 -attr @path {/sobel/sobel:core/ACC1:not#383} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#217.psp#1.sva(3)} -pin  "ACC1:not#383" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#217.psp#1.sva)#8.itm}
+load net {ACC1:not#383.itm} -pin  "ACC1:not#383" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#383.itm}
+load inst "ACC1:not#384" "not(1)" "INTERFACE" -attr xrf 53295 -attr oid 1351 -attr @path {/sobel/sobel:core/ACC1:not#384} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#210.psp#1.sva(3)} -pin  "ACC1:not#384" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#210.psp#1.sva)#8.itm}
+load net {ACC1:not#384.itm} -pin  "ACC1:not#384" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#384.itm}
+load inst "ACC1:not#388" "not(1)" "INTERFACE" -attr xrf 53296 -attr oid 1352 -attr @path {/sobel/sobel:core/ACC1:not#388} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#367.itm(3)} -pin  "ACC1:not#388" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#42.sva)#4.itm}
+load net {ACC1:not#388.itm} -pin  "ACC1:not#388" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#388.itm}
+load inst "ACC1:acc#570" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53297 -attr oid 1353 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:not#388.itm} -pin  "ACC1:acc#570" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#908.itm}
+load net {PWR} -pin  "ACC1:acc#570" {A(1)} -attr @path {/sobel/sobel:core/conc#908.itm}
+load net {ACC1:not#384.itm} -pin  "ACC1:acc#570" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#908.itm}
+load net {ACC1:not#383.itm} -pin  "ACC1:acc#570" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#908.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#570" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1113.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#570" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1113.itm}
+load net {acc#20.psp#1.sva(3)} -pin  "ACC1:acc#570" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1113.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#570" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1113.itm}
+load net {ACC1:acc#570.itm(0)} -pin  "ACC1:acc#570" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(1)} -pin  "ACC1:acc#570" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(2)} -pin  "ACC1:acc#570" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(3)} -pin  "ACC1:acc#570" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(4)} -pin  "ACC1:acc#570" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load inst "ACC1-3:not#156" "not(1)" "INTERFACE" -attr xrf 53298 -attr oid 1354 -attr @path {/sobel/sobel:core/ACC1-3:not#156} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#424.itm(2)} -pin  "ACC1-3:not#156" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#19.sva).itm}
+load net {ACC1-3:not#156.itm} -pin  "ACC1-3:not#156" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#156.itm}
+load inst "ACC1-3:and#9" "and(3,1)" "INTERFACE" -attr xrf 53299 -attr oid 1355 -attr @path {/sobel/sobel:core/ACC1-3:and#9} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1-3:and#9" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#1.itm}
+load net {ACC1-3:not#156.itm} -pin  "ACC1-3:and#9" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#156.itm}
+load net {ACC1:acc#424.itm(1)} -pin  "ACC1-3:and#9" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#19.sva)#1.itm}
+load net {ACC1-3:and#9.itm} -pin  "ACC1-3:and#9" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#9.itm}
+load inst "ACC1:acc#425" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53300 -attr oid 1356 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#425} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#425" {A(0)} -attr @path {/sobel/sobel:core/conc#909.itm}
+load net {ACC1:acc#224.psp#1.sva(1)} -pin  "ACC1:acc#425" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#909.itm}
+load net {ACC1-3:and#9.itm} -pin  "ACC1:acc#425" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#909.itm}
+load net {ACC1-1:acc#25.psp.sva(2)} -pin  "ACC1:acc#425" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1309.itm}
+load net {ACC1:acc#224.psp#1.sva(2)} -pin  "ACC1:acc#425" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1309.itm}
+load net {acc.psp#2.sva(3)} -pin  "ACC1:acc#425" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1309.itm}
+load net {ACC1:acc#425.itm(0)} -pin  "ACC1:acc#425" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#425.itm}
+load net {ACC1:acc#425.itm(1)} -pin  "ACC1:acc#425" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#425.itm}
+load net {ACC1:acc#425.itm(2)} -pin  "ACC1:acc#425" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#425.itm}
+load net {ACC1:acc#425.itm(3)} -pin  "ACC1:acc#425" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#425.itm}
+load inst "ACC1:acc#524" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 53301 -attr oid 1357 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#425.itm(1)} -pin  "ACC1:acc#524" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#425.itm(2)} -pin  "ACC1:acc#524" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#425.itm(3)} -pin  "ACC1:acc#524" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#224.psp#1.sva(3)} -pin  "ACC1:acc#524" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1097.itm}
+load net {ACC1:acc#223.psp.sva(1)} -pin  "ACC1:acc#524" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1097.itm}
+load net {ACC1:acc#223.psp.sva(2)} -pin  "ACC1:acc#524" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1097.itm}
+load net {ACC1:acc#524.itm(0)} -pin  "ACC1:acc#524" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(1)} -pin  "ACC1:acc#524" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(2)} -pin  "ACC1:acc#524" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(3)} -pin  "ACC1:acc#524" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(4)} -pin  "ACC1:acc#524" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load inst "ACC1:acc#600" "add(5,0,5,1,6)" "INTERFACE" -attr xrf 53302 -attr oid 1358 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#570.itm(0)} -pin  "ACC1:acc#600" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(1)} -pin  "ACC1:acc#600" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(2)} -pin  "ACC1:acc#600" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(3)} -pin  "ACC1:acc#600" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(4)} -pin  "ACC1:acc#600" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#524.itm(0)} -pin  "ACC1:acc#600" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(1)} -pin  "ACC1:acc#600" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(2)} -pin  "ACC1:acc#600" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(3)} -pin  "ACC1:acc#600" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(4)} -pin  "ACC1:acc#600" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#600.itm(0)} -pin  "ACC1:acc#600" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(1)} -pin  "ACC1:acc#600" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(2)} -pin  "ACC1:acc#600" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(3)} -pin  "ACC1:acc#600" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(4)} -pin  "ACC1:acc#600" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(5)} -pin  "ACC1:acc#600" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load inst "ACC1:acc#620" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 53303 -attr oid 1359 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#601.itm(0)} -pin  "ACC1:acc#620" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(1)} -pin  "ACC1:acc#620" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(2)} -pin  "ACC1:acc#620" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(3)} -pin  "ACC1:acc#620" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(4)} -pin  "ACC1:acc#620" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(5)} -pin  "ACC1:acc#620" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#600.itm(0)} -pin  "ACC1:acc#620" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(1)} -pin  "ACC1:acc#620" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(2)} -pin  "ACC1:acc#620" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(3)} -pin  "ACC1:acc#620" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(4)} -pin  "ACC1:acc#620" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(5)} -pin  "ACC1:acc#620" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#620.itm(0)} -pin  "ACC1:acc#620" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(1)} -pin  "ACC1:acc#620" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(2)} -pin  "ACC1:acc#620" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(3)} -pin  "ACC1:acc#620" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(4)} -pin  "ACC1:acc#620" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(5)} -pin  "ACC1:acc#620" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(6)} -pin  "ACC1:acc#620" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load inst "ACC1:acc#443" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 53304 -attr oid 1360 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#443" {A(0)} -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#443" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#443" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {ACC1:acc#377.itm(2)} -pin  "ACC1:acc#443" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1345.itm}
+load net {ACC1:acc#220.psp#1.sva(1)} -pin  "ACC1:acc#443" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1345.itm}
+load net {ACC1:acc#220.psp#1.sva(2)} -pin  "ACC1:acc#443" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1345.itm}
+load net {ACC1:acc#443.itm(0)} -pin  "ACC1:acc#443" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443.itm}
+load net {ACC1:acc#443.itm(1)} -pin  "ACC1:acc#443" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443.itm}
+load net {ACC1:acc#443.itm(2)} -pin  "ACC1:acc#443" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443.itm}
+load net {ACC1:acc#443.itm(3)} -pin  "ACC1:acc#443" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443.itm}
+load net {ACC1:acc#443.itm(4)} -pin  "ACC1:acc#443" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443.itm}
+load inst "ACC1:acc#573" "add(4,1,4,0,6)" "INTERFACE" -attr xrf 53305 -attr oid 1361 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#443.itm(1)} -pin  "ACC1:acc#573" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#111.itm}
+load net {ACC1:acc#443.itm(2)} -pin  "ACC1:acc#573" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#111.itm}
+load net {ACC1:acc#443.itm(3)} -pin  "ACC1:acc#573" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#111.itm}
+load net {ACC1:acc#443.itm(4)} -pin  "ACC1:acc#573" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#111.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#573" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1107.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#573" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1107.itm}
+load net {ACC1:acc#224.psp.sva(3)} -pin  "ACC1:acc#573" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1107.itm}
+load net {ACC1:acc#224.psp#1.sva(4)} -pin  "ACC1:acc#573" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1107.itm}
+load net {ACC1:acc#573.itm(0)} -pin  "ACC1:acc#573" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(1)} -pin  "ACC1:acc#573" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(2)} -pin  "ACC1:acc#573" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(3)} -pin  "ACC1:acc#573" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(4)} -pin  "ACC1:acc#573" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(5)} -pin  "ACC1:acc#573" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load inst "ACC1:acc#519" "add(2,1,2,1,3)" "INTERFACE" -attr xrf 53306 -attr oid 1362 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,1,2,1,3)"
+load net {ACC1:acc#220.psp.sva(1)} -pin  "ACC1:acc#519" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp.sva)#2.itm}
+load net {ACC1:acc#220.psp.sva(2)} -pin  "ACC1:acc#519" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp.sva)#2.itm}
+load net {ACC1:acc#222.psp.sva(1)} -pin  "ACC1:acc#519" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp.sva)#2.itm}
+load net {ACC1:acc#222.psp.sva(2)} -pin  "ACC1:acc#519" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp.sva)#2.itm}
+load net {ACC1:acc#519.itm(0)} -pin  "ACC1:acc#519" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load net {ACC1:acc#519.itm(1)} -pin  "ACC1:acc#519" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load net {ACC1:acc#519.itm(2)} -pin  "ACC1:acc#519" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load inst "ACC1:acc#569" "add(4,0,3,1,6)" "INTERFACE" -attr xrf 53307 -attr oid 1363 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#228.psp.sva(6)} -pin  "ACC1:acc#569" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1114.itm}
+load net {ACC1:acc#228.psp.sva(6)} -pin  "ACC1:acc#569" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1114.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#569" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1114.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#569" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1114.itm}
+load net {ACC1:acc#519.itm(0)} -pin  "ACC1:acc#569" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load net {ACC1:acc#519.itm(1)} -pin  "ACC1:acc#569" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load net {ACC1:acc#519.itm(2)} -pin  "ACC1:acc#569" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load net {ACC1:acc#569.itm(0)} -pin  "ACC1:acc#569" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(1)} -pin  "ACC1:acc#569" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(2)} -pin  "ACC1:acc#569" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(3)} -pin  "ACC1:acc#569" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(4)} -pin  "ACC1:acc#569" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(5)} -pin  "ACC1:acc#569" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load inst "ACC1:acc#619" "add(6,1,6,1,7)" "INTERFACE" -attr xrf 53308 -attr oid 1364 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,1,6,1,7)"
+load net {ACC1:acc#573.itm(0)} -pin  "ACC1:acc#619" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(1)} -pin  "ACC1:acc#619" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(2)} -pin  "ACC1:acc#619" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(3)} -pin  "ACC1:acc#619" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(4)} -pin  "ACC1:acc#619" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(5)} -pin  "ACC1:acc#619" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#569.itm(0)} -pin  "ACC1:acc#619" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(1)} -pin  "ACC1:acc#619" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(2)} -pin  "ACC1:acc#619" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(3)} -pin  "ACC1:acc#619" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(4)} -pin  "ACC1:acc#619" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(5)} -pin  "ACC1:acc#619" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#619.itm(0)} -pin  "ACC1:acc#619" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(1)} -pin  "ACC1:acc#619" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(2)} -pin  "ACC1:acc#619" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(3)} -pin  "ACC1:acc#619" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(4)} -pin  "ACC1:acc#619" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(5)} -pin  "ACC1:acc#619" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(6)} -pin  "ACC1:acc#619" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load inst "ACC1:acc#635" "add(7,0,7,1,9)" "INTERFACE" -attr xrf 53309 -attr oid 1365 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#620.itm(0)} -pin  "ACC1:acc#635" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(1)} -pin  "ACC1:acc#635" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(2)} -pin  "ACC1:acc#635" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(3)} -pin  "ACC1:acc#635" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(4)} -pin  "ACC1:acc#635" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(5)} -pin  "ACC1:acc#635" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(6)} -pin  "ACC1:acc#635" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#619.itm(0)} -pin  "ACC1:acc#635" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(1)} -pin  "ACC1:acc#635" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(2)} -pin  "ACC1:acc#635" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(3)} -pin  "ACC1:acc#635" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(4)} -pin  "ACC1:acc#635" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(5)} -pin  "ACC1:acc#635" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(6)} -pin  "ACC1:acc#635" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#635.itm(0)} -pin  "ACC1:acc#635" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(1)} -pin  "ACC1:acc#635" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(2)} -pin  "ACC1:acc#635" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(3)} -pin  "ACC1:acc#635" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(4)} -pin  "ACC1:acc#635" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(5)} -pin  "ACC1:acc#635" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(6)} -pin  "ACC1:acc#635" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(7)} -pin  "ACC1:acc#635" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(8)} -pin  "ACC1:acc#635" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load inst "ACC1:acc#646" "add(9,1,9,0,10)" "INTERFACE" -attr xrf 53310 -attr oid 1366 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,11)"
+load net {ACC1:acc#635.itm(0)} -pin  "ACC1:acc#646" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(1)} -pin  "ACC1:acc#646" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(2)} -pin  "ACC1:acc#646" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(3)} -pin  "ACC1:acc#646" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(4)} -pin  "ACC1:acc#646" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(5)} -pin  "ACC1:acc#646" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(6)} -pin  "ACC1:acc#646" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(7)} -pin  "ACC1:acc#646" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(8)} -pin  "ACC1:acc#646" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#224.psp.sva(6)} -pin  "ACC1:acc#646" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {ACC1:acc#224.psp.sva(6)} -pin  "ACC1:acc#646" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {GND} -pin  "ACC1:acc#646" {B(2)} -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {ACC1:acc#228.psp.sva(4)} -pin  "ACC1:acc#646" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#646" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {GND} -pin  "ACC1:acc#646" {B(5)} -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#646" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {GND} -pin  "ACC1:acc#646" {B(7)} -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#646" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {ACC1:acc#646.itm(0)} -pin  "ACC1:acc#646" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(1)} -pin  "ACC1:acc#646" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(2)} -pin  "ACC1:acc#646" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(3)} -pin  "ACC1:acc#646" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(4)} -pin  "ACC1:acc#646" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(5)} -pin  "ACC1:acc#646" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(6)} -pin  "ACC1:acc#646" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(7)} -pin  "ACC1:acc#646" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(8)} -pin  "ACC1:acc#646" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(9)} -pin  "ACC1:acc#646" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load inst "ACC1:acc#308" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 53311 -attr oid 1367 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#227.psp.sva(8)} -pin  "ACC1:acc#308" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#21.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#308" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#44.itm}
+load net {ACC1:acc#308.itm(0)} -pin  "ACC1:acc#308" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#308.itm(1)} -pin  "ACC1:acc#308" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load inst "ACC1:acc#307" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 53312 -attr oid 1368 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#308.itm(0)} -pin  "ACC1:acc#307" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#308.itm(1)} -pin  "ACC1:acc#307" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#224.psp.sva(7)} -pin  "ACC1:acc#307" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#43.itm}
+load net {ACC1:acc#307.itm(0)} -pin  "ACC1:acc#307" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#307.itm(1)} -pin  "ACC1:acc#307" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load inst "ACC1:acc#306" "add(2,0,1,0,3)" "INTERFACE" -attr xrf 53313 -attr oid 1369 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#307.itm(0)} -pin  "ACC1:acc#306" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#307.itm(1)} -pin  "ACC1:acc#306" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#228.psp.sva(7)} -pin  "ACC1:acc#306" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#18.itm}
+load net {ACC1:acc#306.itm(0)} -pin  "ACC1:acc#306" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(1)} -pin  "ACC1:acc#306" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(2)} -pin  "ACC1:acc#306" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load inst "ACC1:acc#305" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 53314 -attr oid 1370 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#306.itm(0)} -pin  "ACC1:acc#305" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(1)} -pin  "ACC1:acc#305" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(2)} -pin  "ACC1:acc#305" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#226.psp.sva(7)} -pin  "ACC1:acc#305" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#13.itm}
+load net {ACC1:acc#305.itm(0)} -pin  "ACC1:acc#305" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(1)} -pin  "ACC1:acc#305" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(2)} -pin  "ACC1:acc#305" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load inst "ACC1:acc#304" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 53315 -attr oid 1371 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#305.itm(0)} -pin  "ACC1:acc#304" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(1)} -pin  "ACC1:acc#304" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(2)} -pin  "ACC1:acc#304" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#224.psp#1.sva(7)} -pin  "ACC1:acc#304" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#17.itm}
+load net {ACC1:acc#304.itm(0)} -pin  "ACC1:acc#304" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(1)} -pin  "ACC1:acc#304" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(2)} -pin  "ACC1:acc#304" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load inst "ACC1:acc#303" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 53316 -attr oid 1372 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#304.itm(0)} -pin  "ACC1:acc#303" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(1)} -pin  "ACC1:acc#303" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(2)} -pin  "ACC1:acc#303" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1-1:acc#25.psp.sva(8)} -pin  "ACC1:acc#303" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#46.itm}
+load net {ACC1:acc#303.itm(0)} -pin  "ACC1:acc#303" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(1)} -pin  "ACC1:acc#303" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(2)} -pin  "ACC1:acc#303" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load inst "ACC1:acc#302" "add(3,0,1,0,4)" "INTERFACE" -attr xrf 53317 -attr oid 1373 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#303.itm(0)} -pin  "ACC1:acc#302" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(1)} -pin  "ACC1:acc#302" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(2)} -pin  "ACC1:acc#302" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#302" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#83.itm}
+load net {ACC1:acc#302.itm(0)} -pin  "ACC1:acc#302" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(1)} -pin  "ACC1:acc#302" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(2)} -pin  "ACC1:acc#302" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(3)} -pin  "ACC1:acc#302" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load inst "ACC1:mul#54" "mul(4,0,7,0,10)" "INTERFACE" -attr xrf 53318 -attr oid 1374 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,7,0,10)"
+load net {ACC1:acc#302.itm(0)} -pin  "ACC1:mul#54" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(1)} -pin  "ACC1:mul#54" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(2)} -pin  "ACC1:mul#54" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(3)} -pin  "ACC1:mul#54" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {PWR} -pin  "ACC1:mul#54" {B(0)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#54" {B(1)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#54" {B(2)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#54" {B(3)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#54" {B(4)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#54" {B(5)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#54" {B(6)} -attr @path {/sobel/sobel:core/C85_7}
+load net {ACC1:mul#54.itm(0)} -pin  "ACC1:mul#54" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(1)} -pin  "ACC1:mul#54" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(2)} -pin  "ACC1:mul#54" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(3)} -pin  "ACC1:mul#54" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(4)} -pin  "ACC1:mul#54" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(5)} -pin  "ACC1:mul#54" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(6)} -pin  "ACC1:mul#54" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(7)} -pin  "ACC1:mul#54" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(8)} -pin  "ACC1:mul#54" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(9)} -pin  "ACC1:mul#54" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load inst "ACC1:acc#651" "add(10,1,10,0,12)" "INTERFACE" -attr xrf 53319 -attr oid 1375 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,12)"
+load net {ACC1:acc#646.itm(0)} -pin  "ACC1:acc#651" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(1)} -pin  "ACC1:acc#651" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(2)} -pin  "ACC1:acc#651" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(3)} -pin  "ACC1:acc#651" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(4)} -pin  "ACC1:acc#651" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(5)} -pin  "ACC1:acc#651" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(6)} -pin  "ACC1:acc#651" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(7)} -pin  "ACC1:acc#651" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(8)} -pin  "ACC1:acc#651" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(9)} -pin  "ACC1:acc#651" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:mul#54.itm(0)} -pin  "ACC1:acc#651" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(1)} -pin  "ACC1:acc#651" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(2)} -pin  "ACC1:acc#651" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(3)} -pin  "ACC1:acc#651" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(4)} -pin  "ACC1:acc#651" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(5)} -pin  "ACC1:acc#651" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(6)} -pin  "ACC1:acc#651" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(7)} -pin  "ACC1:acc#651" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(8)} -pin  "ACC1:acc#651" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(9)} -pin  "ACC1:acc#651" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:acc#651.itm(0)} -pin  "ACC1:acc#651" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(1)} -pin  "ACC1:acc#651" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(2)} -pin  "ACC1:acc#651" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(3)} -pin  "ACC1:acc#651" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(4)} -pin  "ACC1:acc#651" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(5)} -pin  "ACC1:acc#651" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(6)} -pin  "ACC1:acc#651" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(7)} -pin  "ACC1:acc#651" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(8)} -pin  "ACC1:acc#651" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(9)} -pin  "ACC1:acc#651" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(10)} -pin  "ACC1:acc#651" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(11)} -pin  "ACC1:acc#651" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load inst "ACC1:acc#315" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 53320 -attr oid 1376 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#227.psp.sva(10)} -pin  "ACC1:acc#315" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#17.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#315" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#22.itm}
+load net {ACC1:acc#315.itm(0)} -pin  "ACC1:acc#315" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(1)} -pin  "ACC1:acc#315" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load inst "ACC1:acc#314" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 53321 -attr oid 1377 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#315.itm(0)} -pin  "ACC1:acc#314" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(1)} -pin  "ACC1:acc#314" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#224.psp.sva(9)} -pin  "ACC1:acc#314" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#39.itm}
+load net {ACC1:acc#314.itm(0)} -pin  "ACC1:acc#314" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(1)} -pin  "ACC1:acc#314" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load inst "ACC1:acc#313" "add(2,0,1,0,3)" "INTERFACE" -attr xrf 53322 -attr oid 1378 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#314.itm(0)} -pin  "ACC1:acc#313" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(1)} -pin  "ACC1:acc#313" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#228.psp.sva(9)} -pin  "ACC1:acc#313" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#41.itm}
+load net {ACC1:acc#313.itm(0)} -pin  "ACC1:acc#313" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(1)} -pin  "ACC1:acc#313" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(2)} -pin  "ACC1:acc#313" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load inst "ACC1:acc#312" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 53323 -attr oid 1379 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#313.itm(0)} -pin  "ACC1:acc#312" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(1)} -pin  "ACC1:acc#312" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(2)} -pin  "ACC1:acc#312" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#226.psp.sva(9)} -pin  "ACC1:acc#312" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#38.itm}
+load net {ACC1:acc#312.itm(0)} -pin  "ACC1:acc#312" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(1)} -pin  "ACC1:acc#312" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(2)} -pin  "ACC1:acc#312" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load inst "ACC1:acc#311" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 53324 -attr oid 1380 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#312.itm(0)} -pin  "ACC1:acc#311" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(1)} -pin  "ACC1:acc#311" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(2)} -pin  "ACC1:acc#311" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#224.psp#1.sva(9)} -pin  "ACC1:acc#311" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#47.itm}
+load net {ACC1:acc#311.itm(0)} -pin  "ACC1:acc#311" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(1)} -pin  "ACC1:acc#311" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(2)} -pin  "ACC1:acc#311" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load inst "ACC1:acc#310" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 53325 -attr oid 1381 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#311.itm(0)} -pin  "ACC1:acc#310" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(1)} -pin  "ACC1:acc#310" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(2)} -pin  "ACC1:acc#310" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1-1:acc#25.psp.sva(10)} -pin  "ACC1:acc#310" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#52.itm}
+load net {ACC1:acc#310.itm(0)} -pin  "ACC1:acc#310" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(1)} -pin  "ACC1:acc#310" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(2)} -pin  "ACC1:acc#310" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load inst "ACC1:acc#309" "add(3,0,1,0,4)" "INTERFACE" -attr xrf 53326 -attr oid 1382 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#310.itm(0)} -pin  "ACC1:acc#309" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(1)} -pin  "ACC1:acc#309" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(2)} -pin  "ACC1:acc#309" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#309" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#26.itm}
+load net {ACC1:acc#309.itm(0)} -pin  "ACC1:acc#309" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(1)} -pin  "ACC1:acc#309" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(2)} -pin  "ACC1:acc#309" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(3)} -pin  "ACC1:acc#309" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load inst "ACC1:mul#55" "mul(4,0,9,0,12)" "INTERFACE" -attr xrf 53327 -attr oid 1383 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,9,0,12)"
+load net {ACC1:acc#309.itm(0)} -pin  "ACC1:mul#55" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(1)} -pin  "ACC1:mul#55" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(2)} -pin  "ACC1:mul#55" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(3)} -pin  "ACC1:mul#55" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {PWR} -pin  "ACC1:mul#55" {B(0)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#55" {B(1)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#55" {B(2)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#55" {B(3)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#55" {B(4)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#55" {B(5)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#55" {B(6)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#55" {B(7)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#55" {B(8)} -attr @path {/sobel/sobel:core/C341_9}
+load net {ACC1:mul#55.itm(0)} -pin  "ACC1:mul#55" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(1)} -pin  "ACC1:mul#55" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(2)} -pin  "ACC1:mul#55" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(3)} -pin  "ACC1:mul#55" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(4)} -pin  "ACC1:mul#55" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(5)} -pin  "ACC1:mul#55" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(6)} -pin  "ACC1:mul#55" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(7)} -pin  "ACC1:mul#55" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(8)} -pin  "ACC1:mul#55" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(9)} -pin  "ACC1:mul#55" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(10)} -pin  "ACC1:mul#55" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(11)} -pin  "ACC1:mul#55" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load inst "ACC1:acc#658" "add(12,1,12,0,13)" "INTERFACE" -attr xrf 53328 -attr oid 1384 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,12,1,13)"
+load net {ACC1:acc#651.itm(0)} -pin  "ACC1:acc#658" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(1)} -pin  "ACC1:acc#658" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(2)} -pin  "ACC1:acc#658" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(3)} -pin  "ACC1:acc#658" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(4)} -pin  "ACC1:acc#658" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(5)} -pin  "ACC1:acc#658" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(6)} -pin  "ACC1:acc#658" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(7)} -pin  "ACC1:acc#658" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(8)} -pin  "ACC1:acc#658" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(9)} -pin  "ACC1:acc#658" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(10)} -pin  "ACC1:acc#658" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(11)} -pin  "ACC1:acc#658" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:mul#55.itm(0)} -pin  "ACC1:acc#658" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(1)} -pin  "ACC1:acc#658" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(2)} -pin  "ACC1:acc#658" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(3)} -pin  "ACC1:acc#658" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(4)} -pin  "ACC1:acc#658" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(5)} -pin  "ACC1:acc#658" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(6)} -pin  "ACC1:acc#658" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(7)} -pin  "ACC1:acc#658" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(8)} -pin  "ACC1:acc#658" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(9)} -pin  "ACC1:acc#658" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(10)} -pin  "ACC1:acc#658" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(11)} -pin  "ACC1:acc#658" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:acc#658.itm(0)} -pin  "ACC1:acc#658" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(1)} -pin  "ACC1:acc#658" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(2)} -pin  "ACC1:acc#658" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(3)} -pin  "ACC1:acc#658" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(4)} -pin  "ACC1:acc#658" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(5)} -pin  "ACC1:acc#658" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(6)} -pin  "ACC1:acc#658" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(7)} -pin  "ACC1:acc#658" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(8)} -pin  "ACC1:acc#658" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(9)} -pin  "ACC1:acc#658" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(10)} -pin  "ACC1:acc#658" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(11)} -pin  "ACC1:acc#658" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(12)} -pin  "ACC1:acc#658" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load inst "reg(ACC1:acc#658.itm#1)" "reg(13,1,1,-1,0)" "INTERFACE" -attr xrf 53329 -attr oid 1385 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#658.itm#1)}
+load net {ACC1:acc#658.itm(0)} -pin  "reg(ACC1:acc#658.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(1)} -pin  "reg(ACC1:acc#658.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(2)} -pin  "reg(ACC1:acc#658.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(3)} -pin  "reg(ACC1:acc#658.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(4)} -pin  "reg(ACC1:acc#658.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(5)} -pin  "reg(ACC1:acc#658.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(6)} -pin  "reg(ACC1:acc#658.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(7)} -pin  "reg(ACC1:acc#658.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(8)} -pin  "reg(ACC1:acc#658.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(9)} -pin  "reg(ACC1:acc#658.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(10)} -pin  "reg(ACC1:acc#658.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(11)} -pin  "reg(ACC1:acc#658.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(12)} -pin  "reg(ACC1:acc#658.itm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_13}
+load net {clk} -pin  "reg(ACC1:acc#658.itm#1)" {clk} -attr xrf 53330 -attr oid 1386 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#658.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#658.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#658.itm#1(0)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(1)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(2)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(3)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(4)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(5)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(6)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(7)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(8)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(9)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(10)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(11)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(12)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load inst "ACC1:acc#329" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 53331 -attr oid 1387 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#224.psp.sva(10)} -pin  "ACC1:acc#329" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#9.itm}
+load net {ACC1:acc#228.psp.sva(10)} -pin  "ACC1:acc#329" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#1.itm}
+load net {ACC1:acc#329.itm(0)} -pin  "ACC1:acc#329" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(1)} -pin  "ACC1:acc#329" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load inst "ACC1:acc#328" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 53332 -attr oid 1388 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#329.itm(0)} -pin  "ACC1:acc#328" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(1)} -pin  "ACC1:acc#328" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#226.psp.sva(10)} -pin  "ACC1:acc#328" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#2.itm}
+load net {ACC1:acc#328.itm(0)} -pin  "ACC1:acc#328" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(1)} -pin  "ACC1:acc#328" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load inst "ACC1:acc#327" "add(2,0,1,0,3)" "INTERFACE" -attr xrf 53333 -attr oid 1389 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#328.itm(0)} -pin  "ACC1:acc#327" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(1)} -pin  "ACC1:acc#327" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#224.psp#1.sva(10)} -pin  "ACC1:acc#327" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#3.itm}
+load net {ACC1:acc#327.itm(0)} -pin  "ACC1:acc#327" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(1)} -pin  "ACC1:acc#327" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(2)} -pin  "ACC1:acc#327" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load inst "ACC1:mul#59" "mul(3,0,7,0,9)" "INTERFACE" -attr xrf 53334 -attr oid 1390 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,7,0,10)"
+load net {ACC1:acc#327.itm(0)} -pin  "ACC1:mul#59" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(1)} -pin  "ACC1:mul#59" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(2)} -pin  "ACC1:mul#59" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {PWR} -pin  "ACC1:mul#59" {B(0)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#59" {B(1)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#59" {B(2)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#59" {B(3)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#59" {B(4)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#59" {B(5)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#59" {B(6)} -attr @path {/sobel/sobel:core/C85_7}
+load net {ACC1:mul#59.itm(0)} -pin  "ACC1:mul#59" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(1)} -pin  "ACC1:mul#59" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(2)} -pin  "ACC1:mul#59" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(3)} -pin  "ACC1:mul#59" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(4)} -pin  "ACC1:mul#59" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(5)} -pin  "ACC1:mul#59" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(6)} -pin  "ACC1:mul#59" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(7)} -pin  "ACC1:mul#59" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(8)} -pin  "ACC1:mul#59" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load inst "ACC1:acc#657" "add(12,1,12,0,13)" "INTERFACE" -attr xrf 53335 -attr oid 1391 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,12,1,13)"
+load net {acc.psp#1.sva(2)} -pin  "ACC1:acc#657" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#657" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(2)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(3)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(4)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(5)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(6)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(7)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(8)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#657" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(10)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#657" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {ACC1:acc#224.psp.sva(4)} -pin  "ACC1:acc#657" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:acc#224.psp.sva(4)} -pin  "ACC1:acc#657" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {acc.psp#1.sva(4)} -pin  "ACC1:acc#657" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(0)} -pin  "ACC1:acc#657" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(1)} -pin  "ACC1:acc#657" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(2)} -pin  "ACC1:acc#657" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(3)} -pin  "ACC1:acc#657" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(4)} -pin  "ACC1:acc#657" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(5)} -pin  "ACC1:acc#657" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(6)} -pin  "ACC1:acc#657" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(7)} -pin  "ACC1:acc#657" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(8)} -pin  "ACC1:acc#657" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:acc#657.itm(0)} -pin  "ACC1:acc#657" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(1)} -pin  "ACC1:acc#657" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(2)} -pin  "ACC1:acc#657" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(3)} -pin  "ACC1:acc#657" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(4)} -pin  "ACC1:acc#657" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(5)} -pin  "ACC1:acc#657" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(6)} -pin  "ACC1:acc#657" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(7)} -pin  "ACC1:acc#657" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(8)} -pin  "ACC1:acc#657" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(9)} -pin  "ACC1:acc#657" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(10)} -pin  "ACC1:acc#657" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(11)} -pin  "ACC1:acc#657" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(12)} -pin  "ACC1:acc#657" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load inst "ACC1:acc#317" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 53336 -attr oid 1392 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#317" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#10.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#317" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#11.itm}
+load net {ACC1:acc#317.itm(0)} -pin  "ACC1:acc#317" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(1)} -pin  "ACC1:acc#317" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load inst "ACC1:acc#316" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 53337 -attr oid 1393 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#317.itm(0)} -pin  "ACC1:acc#316" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(1)} -pin  "ACC1:acc#316" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#316" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#72.itm}
+load net {ACC1:acc#316.itm(0)} -pin  "ACC1:acc#316" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(1)} -pin  "ACC1:acc#316" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load inst "ACC1:mul#56" "mul(2,0,11,1,13)" "INTERFACE" -attr xrf 53338 -attr oid 1394 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,11,1,13)"
+load net {ACC1:acc#316.itm(0)} -pin  "ACC1:mul#56" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(1)} -pin  "ACC1:mul#56" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {PWR} -pin  "ACC1:mul#56" {B(0)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {GND} -pin  "ACC1:mul#56" {B(1)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {GND} -pin  "ACC1:mul#56" {B(2)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {PWR} -pin  "ACC1:mul#56" {B(3)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {GND} -pin  "ACC1:mul#56" {B(4)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {PWR} -pin  "ACC1:mul#56" {B(5)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {GND} -pin  "ACC1:mul#56" {B(6)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {PWR} -pin  "ACC1:mul#56" {B(7)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {GND} -pin  "ACC1:mul#56" {B(8)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {GND} -pin  "ACC1:mul#56" {B(9)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {PWR} -pin  "ACC1:mul#56" {B(10)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {ACC1:mul#56.itm(0)} -pin  "ACC1:mul#56" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(1)} -pin  "ACC1:mul#56" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(2)} -pin  "ACC1:mul#56" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(3)} -pin  "ACC1:mul#56" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(4)} -pin  "ACC1:mul#56" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(5)} -pin  "ACC1:mul#56" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(6)} -pin  "ACC1:mul#56" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(7)} -pin  "ACC1:mul#56" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(8)} -pin  "ACC1:mul#56" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(9)} -pin  "ACC1:mul#56" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(10)} -pin  "ACC1:mul#56" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(11)} -pin  "ACC1:mul#56" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(12)} -pin  "ACC1:mul#56" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load inst "ACC1:acc#661" "add(13,1,13,1,14)" "INTERFACE" -attr xrf 53339 -attr oid 1395 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661} -attr area 14.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,1,13,1,14)"
+load net {ACC1:acc#657.itm(0)} -pin  "ACC1:acc#661" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(1)} -pin  "ACC1:acc#661" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(2)} -pin  "ACC1:acc#661" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(3)} -pin  "ACC1:acc#661" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(4)} -pin  "ACC1:acc#661" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(5)} -pin  "ACC1:acc#661" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(6)} -pin  "ACC1:acc#661" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(7)} -pin  "ACC1:acc#661" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(8)} -pin  "ACC1:acc#661" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(9)} -pin  "ACC1:acc#661" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(10)} -pin  "ACC1:acc#661" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(11)} -pin  "ACC1:acc#661" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(12)} -pin  "ACC1:acc#661" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:mul#56.itm(0)} -pin  "ACC1:acc#661" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(1)} -pin  "ACC1:acc#661" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(2)} -pin  "ACC1:acc#661" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(3)} -pin  "ACC1:acc#661" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(4)} -pin  "ACC1:acc#661" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(5)} -pin  "ACC1:acc#661" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(6)} -pin  "ACC1:acc#661" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(7)} -pin  "ACC1:acc#661" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(8)} -pin  "ACC1:acc#661" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(9)} -pin  "ACC1:acc#661" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(10)} -pin  "ACC1:acc#661" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(11)} -pin  "ACC1:acc#661" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(12)} -pin  "ACC1:acc#661" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:acc#661.itm(0)} -pin  "ACC1:acc#661" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(1)} -pin  "ACC1:acc#661" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(2)} -pin  "ACC1:acc#661" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(3)} -pin  "ACC1:acc#661" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(4)} -pin  "ACC1:acc#661" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(5)} -pin  "ACC1:acc#661" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(6)} -pin  "ACC1:acc#661" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(7)} -pin  "ACC1:acc#661" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(8)} -pin  "ACC1:acc#661" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(9)} -pin  "ACC1:acc#661" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(10)} -pin  "ACC1:acc#661" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(11)} -pin  "ACC1:acc#661" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(12)} -pin  "ACC1:acc#661" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(13)} -pin  "ACC1:acc#661" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load inst "reg(ACC1:acc#661.itm#1)" "reg(14,1,1,-1,0)" "INTERFACE" -attr xrf 53340 -attr oid 1396 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#661.itm#1)}
+load net {ACC1:acc#661.itm(0)} -pin  "reg(ACC1:acc#661.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(1)} -pin  "reg(ACC1:acc#661.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(2)} -pin  "reg(ACC1:acc#661.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(3)} -pin  "reg(ACC1:acc#661.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(4)} -pin  "reg(ACC1:acc#661.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(5)} -pin  "reg(ACC1:acc#661.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(6)} -pin  "reg(ACC1:acc#661.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(7)} -pin  "reg(ACC1:acc#661.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(8)} -pin  "reg(ACC1:acc#661.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(9)} -pin  "reg(ACC1:acc#661.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(10)} -pin  "reg(ACC1:acc#661.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(11)} -pin  "reg(ACC1:acc#661.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(12)} -pin  "reg(ACC1:acc#661.itm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(13)} -pin  "reg(ACC1:acc#661.itm#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_14}
+load net {clk} -pin  "reg(ACC1:acc#661.itm#1)" {clk} -attr xrf 53341 -attr oid 1397 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#661.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#661.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#661.itm#1(0)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(1)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(2)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(3)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(4)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(5)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(6)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(7)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(8)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(9)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(10)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(11)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(12)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(13)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load inst "reg(ACC1:mul#57.itm#1.sg2)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 53342 -attr oid 1398 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:mul#57.itm#1.sg2)}
+load net {ACC1:mul#57.itm(9)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#2.itm}
+load net {ACC1:mul#57.itm(10)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#2.itm}
+load net {ACC1:mul#57.itm(11)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#2.itm}
+load net {ACC1:mul#57.itm(12)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#2.itm}
+load net {ACC1:mul#57.itm(13)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#2.itm}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {clk} -attr xrf 53343 -attr oid 1399 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:mul#57.itm#1.sg2(0)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#1.sg2}
+load net {ACC1:mul#57.itm#1.sg2(1)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#1.sg2}
+load net {ACC1:mul#57.itm#1.sg2(2)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#1.sg2}
+load net {ACC1:mul#57.itm#1.sg2(3)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#1.sg2}
+load net {ACC1:mul#57.itm#1.sg2(4)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#1.sg2}
+load inst "reg(ACC1:mul#57.itm#2)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 53344 -attr oid 1400 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:mul#57.itm#2)}
+load net {ACC1:mul#57.itm(0)} -pin  "reg(ACC1:mul#57.itm#2)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#3.itm}
+load net {ACC1:mul#57.itm(1)} -pin  "reg(ACC1:mul#57.itm#2)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#3.itm}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#2)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(ACC1:mul#57.itm#2)" {clk} -attr xrf 53345 -attr oid 1401 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:mul#57.itm#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:mul#57.itm#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:mul#57.itm#2(0)} -pin  "reg(ACC1:mul#57.itm#2)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#2}
+load net {ACC1:mul#57.itm#2(1)} -pin  "reg(ACC1:mul#57.itm#2)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#2}
+load inst "reg(slc(acc#20.psp#1)#93.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 53346 -attr oid 1402 -attr @path {/sobel/sobel:core/reg(slc(acc#20.psp#1)#93.itm#1)}
+load net {acc#20.psp#1.sva(11)} -pin  "reg(slc(acc#20.psp#1)#93.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#12.itm}
+load net {GND} -pin  "reg(slc(acc#20.psp#1)#93.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(slc(acc#20.psp#1)#93.itm#1)" {clk} -attr xrf 53347 -attr oid 1403 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(slc(acc#20.psp#1)#93.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(slc(acc#20.psp#1)#93.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {slc(acc#20.psp#1)#93.itm#1} -pin  "reg(slc(acc#20.psp#1)#93.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1)#93.itm#1}
+load inst "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 53348 -attr oid 1404 -attr @path {/sobel/sobel:core/reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)}
+load net {ACC1:acc#228.psp.sva(6)} -pin  "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#14.itm}
+load net {GND} -pin  "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" {clk} -attr xrf 53349 -attr oid 1405 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(ACC1:acc#228.psp)#55.itm#1} -pin  "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:slc(ACC1:acc#228.psp)#55.itm#1}
+load inst "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 53350 -attr oid 1406 -attr @path {/sobel/sobel:core/reg(ACC1-3:slc(acc#10.psp)#62.itm#1)}
+load net {ACC1:acc#224.psp.sva(8)} -pin  "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#16.itm}
+load net {GND} -pin  "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" {clk} -attr xrf 53351 -attr oid 1407 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1-3:slc(acc#10.psp)#62.itm#1} -pin  "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:slc(acc#10.psp)#62.itm#1}
+load inst "ACC1:acc#458" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53352 -attr oid 1408 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#458} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#458" {A(0)} -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#458" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#458" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {ACC1:acc#346.itm(4)} -pin  "ACC1:acc#458" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1497.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#458" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1497.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#458" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1497.itm}
+load net {ACC1:acc#458.itm(0)} -pin  "ACC1:acc#458" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#458.itm}
+load net {ACC1:acc#458.itm(1)} -pin  "ACC1:acc#458" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#458.itm}
+load net {ACC1:acc#458.itm(2)} -pin  "ACC1:acc#458" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#458.itm}
+load net {ACC1:acc#458.itm(3)} -pin  "ACC1:acc#458" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#458.itm}
+load inst "ACC1:acc#457" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53353 -attr oid 1409 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#457} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#457" {A(0)} -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#457" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#457" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {ACC1:acc#346.itm(3)} -pin  "ACC1:acc#457" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1499.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#457" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1499.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#457" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1499.itm}
+load net {ACC1:acc#457.itm(0)} -pin  "ACC1:acc#457" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#457.itm}
+load net {ACC1:acc#457.itm(1)} -pin  "ACC1:acc#457" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#457.itm}
+load net {ACC1:acc#457.itm(2)} -pin  "ACC1:acc#457" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#457.itm}
+load net {ACC1:acc#457.itm(3)} -pin  "ACC1:acc#457" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#457.itm}
+load inst "ACC1:acc#540" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53354 -attr oid 1410 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#458.itm(1)} -pin  "ACC1:acc#540" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#126.itm}
+load net {ACC1:acc#458.itm(2)} -pin  "ACC1:acc#540" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#126.itm}
+load net {ACC1:acc#458.itm(3)} -pin  "ACC1:acc#540" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#126.itm}
+load net {ACC1:acc#457.itm(1)} -pin  "ACC1:acc#540" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#125.itm}
+load net {ACC1:acc#457.itm(2)} -pin  "ACC1:acc#540" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#125.itm}
+load net {ACC1:acc#457.itm(3)} -pin  "ACC1:acc#540" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#125.itm}
+load net {ACC1:acc#540.itm(0)} -pin  "ACC1:acc#540" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#540.itm(1)} -pin  "ACC1:acc#540" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#540.itm(2)} -pin  "ACC1:acc#540" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#540.itm(3)} -pin  "ACC1:acc#540" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load inst "ACC1:acc#456" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53355 -attr oid 1411 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#456} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#456" {A(0)} -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#456" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#456" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {ACC1:acc#346.itm(2)} -pin  "ACC1:acc#456" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1501.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#456" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1501.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#456" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1501.itm}
+load net {ACC1:acc#456.itm(0)} -pin  "ACC1:acc#456" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#456.itm}
+load net {ACC1:acc#456.itm(1)} -pin  "ACC1:acc#456" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#456.itm}
+load net {ACC1:acc#456.itm(2)} -pin  "ACC1:acc#456" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#456.itm}
+load net {ACC1:acc#456.itm(3)} -pin  "ACC1:acc#456" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#456.itm}
+load inst "ACC1:acc#455" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53356 -attr oid 1412 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#455} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#455" {A(0)} -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#455" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#455" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {ACC1:acc#405.itm(2)} -pin  "ACC1:acc#455" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1503.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#455" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1503.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#455" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1503.itm}
+load net {ACC1:acc#455.itm(0)} -pin  "ACC1:acc#455" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#455.itm}
+load net {ACC1:acc#455.itm(1)} -pin  "ACC1:acc#455" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#455.itm}
+load net {ACC1:acc#455.itm(2)} -pin  "ACC1:acc#455" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#455.itm}
+load net {ACC1:acc#455.itm(3)} -pin  "ACC1:acc#455" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#455.itm}
+load inst "ACC1:acc#539" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53357 -attr oid 1413 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#456.itm(1)} -pin  "ACC1:acc#539" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#124.itm}
+load net {ACC1:acc#456.itm(2)} -pin  "ACC1:acc#539" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#124.itm}
+load net {ACC1:acc#456.itm(3)} -pin  "ACC1:acc#539" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#124.itm}
+load net {ACC1:acc#455.itm(1)} -pin  "ACC1:acc#539" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#123.itm}
+load net {ACC1:acc#455.itm(2)} -pin  "ACC1:acc#539" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#123.itm}
+load net {ACC1:acc#455.itm(3)} -pin  "ACC1:acc#539" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#123.itm}
+load net {ACC1:acc#539.itm(0)} -pin  "ACC1:acc#539" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#539.itm(1)} -pin  "ACC1:acc#539" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#539.itm(2)} -pin  "ACC1:acc#539" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#539.itm(3)} -pin  "ACC1:acc#539" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load inst "ACC1:acc#585" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53358 -attr oid 1414 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#540.itm(0)} -pin  "ACC1:acc#585" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#540.itm(1)} -pin  "ACC1:acc#585" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#540.itm(2)} -pin  "ACC1:acc#585" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#540.itm(3)} -pin  "ACC1:acc#585" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#539.itm(0)} -pin  "ACC1:acc#585" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#539.itm(1)} -pin  "ACC1:acc#585" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#539.itm(2)} -pin  "ACC1:acc#585" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#539.itm(3)} -pin  "ACC1:acc#585" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#585.itm(0)} -pin  "ACC1:acc#585" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(1)} -pin  "ACC1:acc#585" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(2)} -pin  "ACC1:acc#585" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(3)} -pin  "ACC1:acc#585" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(4)} -pin  "ACC1:acc#585" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load inst "ACC1:acc#454" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53359 -attr oid 1415 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#454} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#454" {A(0)} -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#454" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#454" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {ACC1-3:acc#212.psp.sva(3)} -pin  "ACC1:acc#454" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1505.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#454" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1505.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#454" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1505.itm}
+load net {ACC1:acc#454.itm(0)} -pin  "ACC1:acc#454" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#454.itm}
+load net {ACC1:acc#454.itm(1)} -pin  "ACC1:acc#454" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#454.itm}
+load net {ACC1:acc#454.itm(2)} -pin  "ACC1:acc#454" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#454.itm}
+load net {ACC1:acc#454.itm(3)} -pin  "ACC1:acc#454" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#454.itm}
+load inst "ACC1:acc#453" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53360 -attr oid 1416 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#453} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#453" {A(0)} -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#453" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#453" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {ACC1-3:acc#212.psp.sva(2)} -pin  "ACC1:acc#453" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1507.itm}
+load net {ACC1-1:acc#25.psp.sva(5)} -pin  "ACC1:acc#453" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1507.itm}
+load net {ACC1-1:acc#25.psp.sva(5)} -pin  "ACC1:acc#453" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1507.itm}
+load net {ACC1:acc#453.itm(0)} -pin  "ACC1:acc#453" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#453.itm}
+load net {ACC1:acc#453.itm(1)} -pin  "ACC1:acc#453" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#453.itm}
+load net {ACC1:acc#453.itm(2)} -pin  "ACC1:acc#453" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#453.itm}
+load net {ACC1:acc#453.itm(3)} -pin  "ACC1:acc#453" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#453.itm}
+load inst "ACC1:acc#538" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53361 -attr oid 1417 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#454.itm(1)} -pin  "ACC1:acc#538" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#122.itm}
+load net {ACC1:acc#454.itm(2)} -pin  "ACC1:acc#538" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#122.itm}
+load net {ACC1:acc#454.itm(3)} -pin  "ACC1:acc#538" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#122.itm}
+load net {ACC1:acc#453.itm(1)} -pin  "ACC1:acc#538" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#121.itm}
+load net {ACC1:acc#453.itm(2)} -pin  "ACC1:acc#538" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#121.itm}
+load net {ACC1:acc#453.itm(3)} -pin  "ACC1:acc#538" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#121.itm}
+load net {ACC1:acc#538.itm(0)} -pin  "ACC1:acc#538" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#538.itm(1)} -pin  "ACC1:acc#538" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#538.itm(2)} -pin  "ACC1:acc#538" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#538.itm(3)} -pin  "ACC1:acc#538" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load inst "ACC1:acc#452" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53362 -attr oid 1418 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#452} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#452" {A(0)} -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#452" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#452" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {ACC1-3:acc#212.psp.sva(1)} -pin  "ACC1:acc#452" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1509.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#452" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1509.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#452" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1509.itm}
+load net {ACC1:acc#452.itm(0)} -pin  "ACC1:acc#452" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#452.itm}
+load net {ACC1:acc#452.itm(1)} -pin  "ACC1:acc#452" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#452.itm}
+load net {ACC1:acc#452.itm(2)} -pin  "ACC1:acc#452" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#452.itm}
+load net {ACC1:acc#452.itm(3)} -pin  "ACC1:acc#452" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#452.itm}
+load inst "ACC1-2:not#188" "not(1)" "INTERFACE" -attr xrf 53363 -attr oid 1419 -attr @path {/sobel/sobel:core/ACC1-2:not#188} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#387.itm(2)} -pin  "ACC1-2:not#188" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#45.sva)#2.itm}
+load net {ACC1-2:not#188.itm} -pin  "ACC1-2:not#188" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#188.itm}
+load inst "ACC1-2:and#11" "and(3,1)" "INTERFACE" -attr xrf 53364 -attr oid 1420 -attr @path {/sobel/sobel:core/ACC1-2:and#11} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1-2:and#11" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#24.itm}
+load net {ACC1-2:not#188.itm} -pin  "ACC1-2:and#11" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#188.itm}
+load net {ACC1:acc#387.itm(1)} -pin  "ACC1-2:and#11" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#45.sva)#1.itm}
+load net {ACC1-2:and#11.itm} -pin  "ACC1-2:and#11" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:and#11.itm}
+load inst "ACC1:acc#451" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53365 -attr oid 1421 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#451} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#451" {A(0)} -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#451" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#451" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1-2:and#11.itm} -pin  "ACC1:acc#451" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1511.itm}
+load net {ACC1:acc#227.psp.sva(9)} -pin  "ACC1:acc#451" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1511.itm}
+load net {ACC1:acc#227.psp.sva(9)} -pin  "ACC1:acc#451" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1511.itm}
+load net {ACC1:acc#451.itm(0)} -pin  "ACC1:acc#451" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#451.itm}
+load net {ACC1:acc#451.itm(1)} -pin  "ACC1:acc#451" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#451.itm}
+load net {ACC1:acc#451.itm(2)} -pin  "ACC1:acc#451" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#451.itm}
+load net {ACC1:acc#451.itm(3)} -pin  "ACC1:acc#451" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#451.itm}
+load inst "ACC1:acc#537" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53366 -attr oid 1422 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#452.itm(1)} -pin  "ACC1:acc#537" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#120.itm}
+load net {ACC1:acc#452.itm(2)} -pin  "ACC1:acc#537" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#120.itm}
+load net {ACC1:acc#452.itm(3)} -pin  "ACC1:acc#537" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#120.itm}
+load net {ACC1:acc#451.itm(1)} -pin  "ACC1:acc#537" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#119.itm}
+load net {ACC1:acc#451.itm(2)} -pin  "ACC1:acc#537" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#119.itm}
+load net {ACC1:acc#451.itm(3)} -pin  "ACC1:acc#537" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#119.itm}
+load net {ACC1:acc#537.itm(0)} -pin  "ACC1:acc#537" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#537.itm(1)} -pin  "ACC1:acc#537" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#537.itm(2)} -pin  "ACC1:acc#537" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#537.itm(3)} -pin  "ACC1:acc#537" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load inst "ACC1:acc#584" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53367 -attr oid 1423 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#538.itm(0)} -pin  "ACC1:acc#584" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#538.itm(1)} -pin  "ACC1:acc#584" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#538.itm(2)} -pin  "ACC1:acc#584" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#538.itm(3)} -pin  "ACC1:acc#584" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#537.itm(0)} -pin  "ACC1:acc#584" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#537.itm(1)} -pin  "ACC1:acc#584" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#537.itm(2)} -pin  "ACC1:acc#584" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#537.itm(3)} -pin  "ACC1:acc#584" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#584.itm(0)} -pin  "ACC1:acc#584" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(1)} -pin  "ACC1:acc#584" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(2)} -pin  "ACC1:acc#584" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(3)} -pin  "ACC1:acc#584" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(4)} -pin  "ACC1:acc#584" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load inst "ACC1:acc#607" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 53368 -attr oid 1424 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#585.itm(0)} -pin  "ACC1:acc#607" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(1)} -pin  "ACC1:acc#607" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(2)} -pin  "ACC1:acc#607" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(3)} -pin  "ACC1:acc#607" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(4)} -pin  "ACC1:acc#607" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#584.itm(0)} -pin  "ACC1:acc#607" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(1)} -pin  "ACC1:acc#607" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(2)} -pin  "ACC1:acc#607" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(3)} -pin  "ACC1:acc#607" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(4)} -pin  "ACC1:acc#607" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#607.itm(0)} -pin  "ACC1:acc#607" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(1)} -pin  "ACC1:acc#607" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(2)} -pin  "ACC1:acc#607" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(3)} -pin  "ACC1:acc#607" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(4)} -pin  "ACC1:acc#607" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(5)} -pin  "ACC1:acc#607" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load inst "ACC1-2:not#187" "not(1)" "INTERFACE" -attr xrf 53369 -attr oid 1425 -attr @path {/sobel/sobel:core/ACC1-2:not#187} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1-2:not#187" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#25.itm}
+load net {ACC1-2:not#187.itm} -pin  "ACC1-2:not#187" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#187.itm}
+load inst "ACC1-2:nand#5" "nand(2,1)" "INTERFACE" -attr xrf 53370 -attr oid 1426 -attr @path {/sobel/sobel:core/ACC1-2:nand#5} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#387.itm(2)} -pin  "ACC1-2:nand#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#45.sva).itm}
+load net {ACC1-2:not#187.itm} -pin  "ACC1-2:nand#5" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#187.itm}
+load net {ACC1-2:nand#5.itm} -pin  "ACC1-2:nand#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:nand#5.itm}
+load inst "ACC1:acc#450" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53371 -attr oid 1427 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#450} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#450" {A(0)} -attr @path {/sobel/sobel:core/exs#63.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#450" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#63.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#450" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#63.itm}
+load net {ACC1-2:nand#5.itm} -pin  "ACC1:acc#450" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1513.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#450" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1513.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#450" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1513.itm}
+load net {ACC1:acc#450.itm(0)} -pin  "ACC1:acc#450" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#450.itm}
+load net {ACC1:acc#450.itm(1)} -pin  "ACC1:acc#450" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#450.itm}
+load net {ACC1:acc#450.itm(2)} -pin  "ACC1:acc#450" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#450.itm}
+load net {ACC1:acc#450.itm(3)} -pin  "ACC1:acc#450" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#450.itm}
+load inst "ACC1:acc#449" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53372 -attr oid 1428 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#449} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#449" {A(0)} -attr @path {/sobel/sobel:core/exs#64.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#449" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#64.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#449" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#64.itm}
+load net {ACC1:acc#386.itm(2)} -pin  "ACC1:acc#449" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1515.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#449" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1515.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#449" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1515.itm}
+load net {ACC1:acc#449.itm(0)} -pin  "ACC1:acc#449" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#449.itm}
+load net {ACC1:acc#449.itm(1)} -pin  "ACC1:acc#449" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#449.itm}
+load net {ACC1:acc#449.itm(2)} -pin  "ACC1:acc#449" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#449.itm}
+load net {ACC1:acc#449.itm(3)} -pin  "ACC1:acc#449" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#449.itm}
+load inst "ACC1:acc#536" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53373 -attr oid 1429 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#450.itm(1)} -pin  "ACC1:acc#536" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#118.itm}
+load net {ACC1:acc#450.itm(2)} -pin  "ACC1:acc#536" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#118.itm}
+load net {ACC1:acc#450.itm(3)} -pin  "ACC1:acc#536" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#118.itm}
+load net {ACC1:acc#449.itm(1)} -pin  "ACC1:acc#536" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#117.itm}
+load net {ACC1:acc#449.itm(2)} -pin  "ACC1:acc#536" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#117.itm}
+load net {ACC1:acc#449.itm(3)} -pin  "ACC1:acc#536" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#117.itm}
+load net {ACC1:acc#536.itm(0)} -pin  "ACC1:acc#536" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#536.itm(1)} -pin  "ACC1:acc#536" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#536.itm(2)} -pin  "ACC1:acc#536" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#536.itm(3)} -pin  "ACC1:acc#536" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load inst "ACC1:acc#448" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53374 -attr oid 1430 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#448} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#448" {A(0)} -attr @path {/sobel/sobel:core/exs#65.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#448" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#65.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#448" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#65.itm}
+load net {ACC1:acc#384.itm(4)} -pin  "ACC1:acc#448" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1517.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#448" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1517.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#448" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1517.itm}
+load net {ACC1:acc#448.itm(0)} -pin  "ACC1:acc#448" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#448.itm}
+load net {ACC1:acc#448.itm(1)} -pin  "ACC1:acc#448" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#448.itm}
+load net {ACC1:acc#448.itm(2)} -pin  "ACC1:acc#448" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#448.itm}
+load net {ACC1:acc#448.itm(3)} -pin  "ACC1:acc#448" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#448.itm}
+load inst "ACC1:acc#447" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53375 -attr oid 1431 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#447} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#447" {A(0)} -attr @path {/sobel/sobel:core/exs#92.itm}
+load net {acc.psp#1.sva(5)} -pin  "ACC1:acc#447" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#92.itm}
+load net {acc.psp#1.sva(5)} -pin  "ACC1:acc#447" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#92.itm}
+load net {ACC1:acc#384.itm(3)} -pin  "ACC1:acc#447" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1519.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#447" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1519.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#447" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1519.itm}
+load net {ACC1:acc#447.itm(0)} -pin  "ACC1:acc#447" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#447.itm}
+load net {ACC1:acc#447.itm(1)} -pin  "ACC1:acc#447" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#447.itm}
+load net {ACC1:acc#447.itm(2)} -pin  "ACC1:acc#447" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#447.itm}
+load net {ACC1:acc#447.itm(3)} -pin  "ACC1:acc#447" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#447.itm}
+load inst "ACC1:acc#535" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53376 -attr oid 1432 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#448.itm(1)} -pin  "ACC1:acc#535" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#116.itm}
+load net {ACC1:acc#448.itm(2)} -pin  "ACC1:acc#535" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#116.itm}
+load net {ACC1:acc#448.itm(3)} -pin  "ACC1:acc#535" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#116.itm}
+load net {ACC1:acc#447.itm(1)} -pin  "ACC1:acc#535" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#115.itm}
+load net {ACC1:acc#447.itm(2)} -pin  "ACC1:acc#535" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#115.itm}
+load net {ACC1:acc#447.itm(3)} -pin  "ACC1:acc#535" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#115.itm}
+load net {ACC1:acc#535.itm(0)} -pin  "ACC1:acc#535" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#535.itm(1)} -pin  "ACC1:acc#535" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#535.itm(2)} -pin  "ACC1:acc#535" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#535.itm(3)} -pin  "ACC1:acc#535" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load inst "ACC1:acc#583" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53377 -attr oid 1433 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#536.itm(0)} -pin  "ACC1:acc#583" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#536.itm(1)} -pin  "ACC1:acc#583" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#536.itm(2)} -pin  "ACC1:acc#583" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#536.itm(3)} -pin  "ACC1:acc#583" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#535.itm(0)} -pin  "ACC1:acc#583" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#535.itm(1)} -pin  "ACC1:acc#583" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#535.itm(2)} -pin  "ACC1:acc#583" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#535.itm(3)} -pin  "ACC1:acc#583" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#583.itm(0)} -pin  "ACC1:acc#583" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(1)} -pin  "ACC1:acc#583" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(2)} -pin  "ACC1:acc#583" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(3)} -pin  "ACC1:acc#583" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(4)} -pin  "ACC1:acc#583" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load inst "ACC1:acc#446" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53378 -attr oid 1434 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#446} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#446" {A(0)} -attr @path {/sobel/sobel:core/exs#66.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#446" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#66.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#446" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#66.itm}
+load net {ACC1:acc#384.itm(2)} -pin  "ACC1:acc#446" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1521.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#446" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1521.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#446" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1521.itm}
+load net {ACC1:acc#446.itm(0)} -pin  "ACC1:acc#446" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#446.itm}
+load net {ACC1:acc#446.itm(1)} -pin  "ACC1:acc#446" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#446.itm}
+load net {ACC1:acc#446.itm(2)} -pin  "ACC1:acc#446" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#446.itm}
+load net {ACC1:acc#446.itm(3)} -pin  "ACC1:acc#446" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#446.itm}
+load inst "ACC1-2:not#60" "not(1)" "INTERFACE" -attr xrf 53379 -attr oid 1435 -attr @path {/sobel/sobel:core/ACC1-2:not#60} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#378.itm(2)} -pin  "ACC1-2:not#60" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#33.sva)#2.itm}
+load net {ACC1-2:not#60.itm} -pin  "ACC1-2:not#60" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#60.itm}
+load inst "ACC1-2:and#3" "and(3,1)" "INTERFACE" -attr xrf 53380 -attr oid 1436 -attr @path {/sobel/sobel:core/ACC1-2:and#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1-2:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#29.itm}
+load net {ACC1-2:not#60.itm} -pin  "ACC1-2:and#3" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#60.itm}
+load net {ACC1:acc#378.itm(1)} -pin  "ACC1-2:and#3" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#33.sva)#1.itm}
+load net {ACC1-2:and#3.itm} -pin  "ACC1-2:and#3" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:and#3.itm}
+load inst "ACC1:acc#445" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53381 -attr oid 1437 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#445} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#445" {A(0)} -attr @path {/sobel/sobel:core/exs#93.itm}
+load net {ACC1:acc#227.psp.sva(7)} -pin  "ACC1:acc#445" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#93.itm}
+load net {ACC1:acc#227.psp.sva(7)} -pin  "ACC1:acc#445" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#93.itm}
+load net {ACC1-2:and#3.itm} -pin  "ACC1:acc#445" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1523.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#445" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1523.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#445" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1523.itm}
+load net {ACC1:acc#445.itm(0)} -pin  "ACC1:acc#445" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#445.itm}
+load net {ACC1:acc#445.itm(1)} -pin  "ACC1:acc#445" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#445.itm}
+load net {ACC1:acc#445.itm(2)} -pin  "ACC1:acc#445" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#445.itm}
+load net {ACC1:acc#445.itm(3)} -pin  "ACC1:acc#445" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#445.itm}
+load inst "ACC1:acc#534" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53382 -attr oid 1438 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#446.itm(1)} -pin  "ACC1:acc#534" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#114.itm}
+load net {ACC1:acc#446.itm(2)} -pin  "ACC1:acc#534" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#114.itm}
+load net {ACC1:acc#446.itm(3)} -pin  "ACC1:acc#534" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#114.itm}
+load net {ACC1:acc#445.itm(1)} -pin  "ACC1:acc#534" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#113.itm}
+load net {ACC1:acc#445.itm(2)} -pin  "ACC1:acc#534" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#113.itm}
+load net {ACC1:acc#445.itm(3)} -pin  "ACC1:acc#534" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#113.itm}
+load net {ACC1:acc#534.itm(0)} -pin  "ACC1:acc#534" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#534.itm(1)} -pin  "ACC1:acc#534" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#534.itm(2)} -pin  "ACC1:acc#534" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#534.itm(3)} -pin  "ACC1:acc#534" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load inst "ACC1-2:not#59" "not(1)" "INTERFACE" -attr xrf 53383 -attr oid 1439 -attr @path {/sobel/sobel:core/ACC1-2:not#59} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1-2:not#59" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#30.itm}
+load net {ACC1-2:not#59.itm} -pin  "ACC1-2:not#59" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#59.itm}
+load inst "ACC1-2:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 53384 -attr oid 1440 -attr @path {/sobel/sobel:core/ACC1-2:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#378.itm(2)} -pin  "ACC1-2:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#33.sva).itm}
+load net {ACC1-2:not#59.itm} -pin  "ACC1-2:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#59.itm}
+load net {ACC1-2:nand#1.itm} -pin  "ACC1-2:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:nand#1.itm}
+load inst "ACC1:acc#444" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53385 -attr oid 1441 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#444} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#444" {A(0)} -attr @path {/sobel/sobel:core/exs#67.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#444" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#67.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#444" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#67.itm}
+load net {ACC1-2:nand#1.itm} -pin  "ACC1:acc#444" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1525.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#444" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1525.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#444" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1525.itm}
+load net {ACC1:acc#444.itm(0)} -pin  "ACC1:acc#444" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#444.itm}
+load net {ACC1:acc#444.itm(1)} -pin  "ACC1:acc#444" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#444.itm}
+load net {ACC1:acc#444.itm(2)} -pin  "ACC1:acc#444" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#444.itm}
+load net {ACC1:acc#444.itm(3)} -pin  "ACC1:acc#444" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#444.itm}
+load inst "ACC1:acc#442" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53386 -attr oid 1442 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#442} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#442" {A(0)} -attr @path {/sobel/sobel:core/exs#68.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#442" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#68.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#442" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#68.itm}
+load net {ACC1:acc#375.itm(4)} -pin  "ACC1:acc#442" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1527.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#442" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1527.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#442" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1527.itm}
+load net {ACC1:acc#442.itm(0)} -pin  "ACC1:acc#442" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#442.itm}
+load net {ACC1:acc#442.itm(1)} -pin  "ACC1:acc#442" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#442.itm}
+load net {ACC1:acc#442.itm(2)} -pin  "ACC1:acc#442" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#442.itm}
+load net {ACC1:acc#442.itm(3)} -pin  "ACC1:acc#442" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#442.itm}
+load inst "ACC1:acc#533" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53387 -attr oid 1443 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#444.itm(1)} -pin  "ACC1:acc#533" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#112.itm}
+load net {ACC1:acc#444.itm(2)} -pin  "ACC1:acc#533" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#112.itm}
+load net {ACC1:acc#444.itm(3)} -pin  "ACC1:acc#533" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#112.itm}
+load net {ACC1:acc#442.itm(1)} -pin  "ACC1:acc#533" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#110.itm}
+load net {ACC1:acc#442.itm(2)} -pin  "ACC1:acc#533" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#110.itm}
+load net {ACC1:acc#442.itm(3)} -pin  "ACC1:acc#533" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#110.itm}
+load net {ACC1:acc#533.itm(0)} -pin  "ACC1:acc#533" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#533.itm(1)} -pin  "ACC1:acc#533" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#533.itm(2)} -pin  "ACC1:acc#533" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#533.itm(3)} -pin  "ACC1:acc#533" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load inst "ACC1:acc#582" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53388 -attr oid 1444 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#534.itm(0)} -pin  "ACC1:acc#582" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#534.itm(1)} -pin  "ACC1:acc#582" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#534.itm(2)} -pin  "ACC1:acc#582" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#534.itm(3)} -pin  "ACC1:acc#582" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#533.itm(0)} -pin  "ACC1:acc#582" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#533.itm(1)} -pin  "ACC1:acc#582" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#533.itm(2)} -pin  "ACC1:acc#582" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#533.itm(3)} -pin  "ACC1:acc#582" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#582.itm(0)} -pin  "ACC1:acc#582" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(1)} -pin  "ACC1:acc#582" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(2)} -pin  "ACC1:acc#582" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(3)} -pin  "ACC1:acc#582" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(4)} -pin  "ACC1:acc#582" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load inst "ACC1:acc#606" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 53389 -attr oid 1445 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#583.itm(0)} -pin  "ACC1:acc#606" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(1)} -pin  "ACC1:acc#606" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(2)} -pin  "ACC1:acc#606" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(3)} -pin  "ACC1:acc#606" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(4)} -pin  "ACC1:acc#606" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#582.itm(0)} -pin  "ACC1:acc#606" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(1)} -pin  "ACC1:acc#606" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(2)} -pin  "ACC1:acc#606" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(3)} -pin  "ACC1:acc#606" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(4)} -pin  "ACC1:acc#606" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#606.itm(0)} -pin  "ACC1:acc#606" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(1)} -pin  "ACC1:acc#606" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(2)} -pin  "ACC1:acc#606" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(3)} -pin  "ACC1:acc#606" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(4)} -pin  "ACC1:acc#606" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(5)} -pin  "ACC1:acc#606" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load inst "ACC1:acc#623" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 53390 -attr oid 1446 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#607.itm(0)} -pin  "ACC1:acc#623" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(1)} -pin  "ACC1:acc#623" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(2)} -pin  "ACC1:acc#623" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(3)} -pin  "ACC1:acc#623" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(4)} -pin  "ACC1:acc#623" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(5)} -pin  "ACC1:acc#623" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#606.itm(0)} -pin  "ACC1:acc#623" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(1)} -pin  "ACC1:acc#623" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(2)} -pin  "ACC1:acc#623" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(3)} -pin  "ACC1:acc#623" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(4)} -pin  "ACC1:acc#623" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(5)} -pin  "ACC1:acc#623" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#623.itm(0)} -pin  "ACC1:acc#623" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(1)} -pin  "ACC1:acc#623" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(2)} -pin  "ACC1:acc#623" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(3)} -pin  "ACC1:acc#623" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(4)} -pin  "ACC1:acc#623" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(5)} -pin  "ACC1:acc#623" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(6)} -pin  "ACC1:acc#623" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load inst "ACC1:acc#441" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53391 -attr oid 1447 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#441} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#441" {A(0)} -attr @path {/sobel/sobel:core/exs#69.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#441" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#69.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#441" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#69.itm}
+load net {ACC1:acc#375.itm(3)} -pin  "ACC1:acc#441" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1529.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#441" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1529.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#441" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1529.itm}
+load net {ACC1:acc#441.itm(0)} -pin  "ACC1:acc#441" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#441.itm}
+load net {ACC1:acc#441.itm(1)} -pin  "ACC1:acc#441" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#441.itm}
+load net {ACC1:acc#441.itm(2)} -pin  "ACC1:acc#441" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#441.itm}
+load net {ACC1:acc#441.itm(3)} -pin  "ACC1:acc#441" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#441.itm}
+load inst "ACC1:acc#440" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53392 -attr oid 1448 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#440} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#440" {A(0)} -attr @path {/sobel/sobel:core/exs#70.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#440" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#70.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#440" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#70.itm}
+load net {ACC1:acc#375.itm(2)} -pin  "ACC1:acc#440" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1531.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#440" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1531.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#440" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1531.itm}
+load net {ACC1:acc#440.itm(0)} -pin  "ACC1:acc#440" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#440.itm}
+load net {ACC1:acc#440.itm(1)} -pin  "ACC1:acc#440" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#440.itm}
+load net {ACC1:acc#440.itm(2)} -pin  "ACC1:acc#440" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#440.itm}
+load net {ACC1:acc#440.itm(3)} -pin  "ACC1:acc#440" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#440.itm}
+load inst "ACC1:acc#532" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53393 -attr oid 1449 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#441.itm(1)} -pin  "ACC1:acc#532" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#109.itm}
+load net {ACC1:acc#441.itm(2)} -pin  "ACC1:acc#532" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#109.itm}
+load net {ACC1:acc#441.itm(3)} -pin  "ACC1:acc#532" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#109.itm}
+load net {ACC1:acc#440.itm(1)} -pin  "ACC1:acc#532" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#108.itm}
+load net {ACC1:acc#440.itm(2)} -pin  "ACC1:acc#532" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#108.itm}
+load net {ACC1:acc#440.itm(3)} -pin  "ACC1:acc#532" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#108.itm}
+load net {ACC1:acc#532.itm(0)} -pin  "ACC1:acc#532" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#532.itm(1)} -pin  "ACC1:acc#532" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#532.itm(2)} -pin  "ACC1:acc#532" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#532.itm(3)} -pin  "ACC1:acc#532" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load inst "ACC1-3:not#92" "not(1)" "INTERFACE" -attr xrf 53394 -attr oid 1450 -attr @path {/sobel/sobel:core/ACC1-3:not#92} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#415.itm(2)} -pin  "ACC1-3:not#92" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#2.itm}
+load net {ACC1-3:not#92.itm} -pin  "ACC1-3:not#92" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#92.itm}
+load inst "ACC1-3:and#5" "and(3,1)" "INTERFACE" -attr xrf 53395 -attr oid 1451 -attr @path {/sobel/sobel:core/ACC1-3:and#5} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1-3:and#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#24.itm}
+load net {ACC1-3:not#92.itm} -pin  "ACC1-3:and#5" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#92.itm}
+load net {ACC1:acc#415.itm(1)} -pin  "ACC1-3:and#5" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#1.itm}
+load net {ACC1-3:and#5.itm} -pin  "ACC1-3:and#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#5.itm}
+load inst "ACC1:acc#439" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53396 -attr oid 1452 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#439} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#439" {A(0)} -attr @path {/sobel/sobel:core/exs#71.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#439" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#71.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#439" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#71.itm}
+load net {ACC1-3:and#5.itm} -pin  "ACC1:acc#439" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1533.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#439" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1533.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#439" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1533.itm}
+load net {ACC1:acc#439.itm(0)} -pin  "ACC1:acc#439" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#439.itm}
+load net {ACC1:acc#439.itm(1)} -pin  "ACC1:acc#439" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#439.itm}
+load net {ACC1:acc#439.itm(2)} -pin  "ACC1:acc#439" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#439.itm}
+load net {ACC1:acc#439.itm(3)} -pin  "ACC1:acc#439" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#439.itm}
+load inst "ACC1-3:not#91" "not(1)" "INTERFACE" -attr xrf 53397 -attr oid 1453 -attr @path {/sobel/sobel:core/ACC1-3:not#91} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1-3:not#91" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#25.itm}
+load net {ACC1-3:not#91.itm} -pin  "ACC1-3:not#91" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#91.itm}
+load inst "ACC1-3:nand#2" "nand(2,1)" "INTERFACE" -attr xrf 53398 -attr oid 1454 -attr @path {/sobel/sobel:core/ACC1-3:nand#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#415.itm(2)} -pin  "ACC1-3:nand#2" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva).itm}
+load net {ACC1-3:not#91.itm} -pin  "ACC1-3:nand#2" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#91.itm}
+load net {ACC1-3:nand#2.itm} -pin  "ACC1-3:nand#2" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand#2.itm}
+load inst "ACC1:acc#438" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53399 -attr oid 1455 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#438} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#438" {A(0)} -attr @path {/sobel/sobel:core/exs#72.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#438" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#72.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#438" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#72.itm}
+load net {ACC1-3:nand#2.itm} -pin  "ACC1:acc#438" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1535.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#438" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1535.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#438" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1535.itm}
+load net {ACC1:acc#438.itm(0)} -pin  "ACC1:acc#438" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#438.itm}
+load net {ACC1:acc#438.itm(1)} -pin  "ACC1:acc#438" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#438.itm}
+load net {ACC1:acc#438.itm(2)} -pin  "ACC1:acc#438" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#438.itm}
+load net {ACC1:acc#438.itm(3)} -pin  "ACC1:acc#438" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#438.itm}
+load inst "ACC1:acc#531" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53400 -attr oid 1456 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#439.itm(1)} -pin  "ACC1:acc#531" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#107.itm}
+load net {ACC1:acc#439.itm(2)} -pin  "ACC1:acc#531" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#107.itm}
+load net {ACC1:acc#439.itm(3)} -pin  "ACC1:acc#531" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#107.itm}
+load net {ACC1:acc#438.itm(1)} -pin  "ACC1:acc#531" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#106.itm}
+load net {ACC1:acc#438.itm(2)} -pin  "ACC1:acc#531" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#106.itm}
+load net {ACC1:acc#438.itm(3)} -pin  "ACC1:acc#531" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#106.itm}
+load net {ACC1:acc#531.itm(0)} -pin  "ACC1:acc#531" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#531.itm(1)} -pin  "ACC1:acc#531" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#531.itm(2)} -pin  "ACC1:acc#531" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#531.itm(3)} -pin  "ACC1:acc#531" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load inst "ACC1:acc#581" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53401 -attr oid 1457 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#532.itm(0)} -pin  "ACC1:acc#581" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#532.itm(1)} -pin  "ACC1:acc#581" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#532.itm(2)} -pin  "ACC1:acc#581" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#532.itm(3)} -pin  "ACC1:acc#581" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#531.itm(0)} -pin  "ACC1:acc#581" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#531.itm(1)} -pin  "ACC1:acc#581" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#531.itm(2)} -pin  "ACC1:acc#581" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#531.itm(3)} -pin  "ACC1:acc#581" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#581.itm(0)} -pin  "ACC1:acc#581" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(1)} -pin  "ACC1:acc#581" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(2)} -pin  "ACC1:acc#581" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(3)} -pin  "ACC1:acc#581" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(4)} -pin  "ACC1:acc#581" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load inst "ACC1:acc#437" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53402 -attr oid 1458 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#437} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#437" {A(0)} -attr @path {/sobel/sobel:core/exs#73.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#437" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#73.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#437" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#73.itm}
+load net {ACC1:acc#414.itm(2)} -pin  "ACC1:acc#437" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1537.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#437" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1537.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#437" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1537.itm}
+load net {ACC1:acc#437.itm(0)} -pin  "ACC1:acc#437" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#437.itm}
+load net {ACC1:acc#437.itm(1)} -pin  "ACC1:acc#437" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#437.itm}
+load net {ACC1:acc#437.itm(2)} -pin  "ACC1:acc#437" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#437.itm}
+load net {ACC1:acc#437.itm(3)} -pin  "ACC1:acc#437" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#437.itm}
+load inst "ACC1:acc#436" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53403 -attr oid 1459 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#436} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#436" {A(0)} -attr @path {/sobel/sobel:core/exs#74.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#436" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#74.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#436" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#74.itm}
+load net {ACC1:acc#412.itm(4)} -pin  "ACC1:acc#436" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1539.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#436" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1539.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#436" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1539.itm}
+load net {ACC1:acc#436.itm(0)} -pin  "ACC1:acc#436" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#436.itm}
+load net {ACC1:acc#436.itm(1)} -pin  "ACC1:acc#436" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#436.itm}
+load net {ACC1:acc#436.itm(2)} -pin  "ACC1:acc#436" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#436.itm}
+load net {ACC1:acc#436.itm(3)} -pin  "ACC1:acc#436" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#436.itm}
+load inst "ACC1:acc#530" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53404 -attr oid 1460 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#437.itm(1)} -pin  "ACC1:acc#530" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#105.itm}
+load net {ACC1:acc#437.itm(2)} -pin  "ACC1:acc#530" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#105.itm}
+load net {ACC1:acc#437.itm(3)} -pin  "ACC1:acc#530" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#105.itm}
+load net {ACC1:acc#436.itm(1)} -pin  "ACC1:acc#530" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#104.itm}
+load net {ACC1:acc#436.itm(2)} -pin  "ACC1:acc#530" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#104.itm}
+load net {ACC1:acc#436.itm(3)} -pin  "ACC1:acc#530" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#104.itm}
+load net {ACC1:acc#530.itm(0)} -pin  "ACC1:acc#530" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#530.itm(1)} -pin  "ACC1:acc#530" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#530.itm(2)} -pin  "ACC1:acc#530" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#530.itm(3)} -pin  "ACC1:acc#530" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load inst "ACC1:acc#435" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53405 -attr oid 1461 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#435} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#435" {A(0)} -attr @path {/sobel/sobel:core/exs#75.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#435" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#75.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#435" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#75.itm}
+load net {ACC1:acc#412.itm(3)} -pin  "ACC1:acc#435" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1541.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#435" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1541.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#435" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1541.itm}
+load net {ACC1:acc#435.itm(0)} -pin  "ACC1:acc#435" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#435.itm}
+load net {ACC1:acc#435.itm(1)} -pin  "ACC1:acc#435" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#435.itm}
+load net {ACC1:acc#435.itm(2)} -pin  "ACC1:acc#435" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#435.itm}
+load net {ACC1:acc#435.itm(3)} -pin  "ACC1:acc#435" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#435.itm}
+load inst "ACC1:acc#434" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53406 -attr oid 1462 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#434} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#434" {A(0)} -attr @path {/sobel/sobel:core/exs#76.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#434" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#76.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#434" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#76.itm}
+load net {ACC1:acc#412.itm(2)} -pin  "ACC1:acc#434" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1543.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#434" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1543.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#434" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1543.itm}
+load net {ACC1:acc#434.itm(0)} -pin  "ACC1:acc#434" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#434.itm}
+load net {ACC1:acc#434.itm(1)} -pin  "ACC1:acc#434" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#434.itm}
+load net {ACC1:acc#434.itm(2)} -pin  "ACC1:acc#434" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#434.itm}
+load net {ACC1:acc#434.itm(3)} -pin  "ACC1:acc#434" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#434.itm}
+load inst "ACC1:acc#529" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53407 -attr oid 1463 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#435.itm(1)} -pin  "ACC1:acc#529" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#103.itm}
+load net {ACC1:acc#435.itm(2)} -pin  "ACC1:acc#529" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#103.itm}
+load net {ACC1:acc#435.itm(3)} -pin  "ACC1:acc#529" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#103.itm}
+load net {ACC1:acc#434.itm(1)} -pin  "ACC1:acc#529" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#102.itm}
+load net {ACC1:acc#434.itm(2)} -pin  "ACC1:acc#529" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#102.itm}
+load net {ACC1:acc#434.itm(3)} -pin  "ACC1:acc#529" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#102.itm}
+load net {ACC1:acc#529.itm(0)} -pin  "ACC1:acc#529" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#529.itm(1)} -pin  "ACC1:acc#529" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#529.itm(2)} -pin  "ACC1:acc#529" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#529.itm(3)} -pin  "ACC1:acc#529" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load inst "ACC1:acc#580" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53408 -attr oid 1464 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#530.itm(0)} -pin  "ACC1:acc#580" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#530.itm(1)} -pin  "ACC1:acc#580" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#530.itm(2)} -pin  "ACC1:acc#580" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#530.itm(3)} -pin  "ACC1:acc#580" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#529.itm(0)} -pin  "ACC1:acc#580" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#529.itm(1)} -pin  "ACC1:acc#580" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#529.itm(2)} -pin  "ACC1:acc#580" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#529.itm(3)} -pin  "ACC1:acc#580" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#580.itm(0)} -pin  "ACC1:acc#580" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(1)} -pin  "ACC1:acc#580" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(2)} -pin  "ACC1:acc#580" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(3)} -pin  "ACC1:acc#580" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(4)} -pin  "ACC1:acc#580" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load inst "ACC1:acc#605" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 53409 -attr oid 1465 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#581.itm(0)} -pin  "ACC1:acc#605" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(1)} -pin  "ACC1:acc#605" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(2)} -pin  "ACC1:acc#605" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(3)} -pin  "ACC1:acc#605" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(4)} -pin  "ACC1:acc#605" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#580.itm(0)} -pin  "ACC1:acc#605" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(1)} -pin  "ACC1:acc#605" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(2)} -pin  "ACC1:acc#605" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(3)} -pin  "ACC1:acc#605" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(4)} -pin  "ACC1:acc#605" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#605.itm(0)} -pin  "ACC1:acc#605" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(1)} -pin  "ACC1:acc#605" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(2)} -pin  "ACC1:acc#605" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(3)} -pin  "ACC1:acc#605" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(4)} -pin  "ACC1:acc#605" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(5)} -pin  "ACC1:acc#605" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load inst "ACC1-3:not#28" "not(1)" "INTERFACE" -attr xrf 53410 -attr oid 1466 -attr @path {/sobel/sobel:core/ACC1-3:not#28} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#396.itm(2)} -pin  "ACC1-3:not#28" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#2.itm}
+load net {ACC1-3:not#28.itm} -pin  "ACC1-3:not#28" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#28.itm}
+load inst "ACC1-3:and#1" "and(3,1)" "INTERFACE" -attr xrf 53411 -attr oid 1467 -attr @path {/sobel/sobel:core/ACC1-3:and#1} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:and#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#31.itm}
+load net {ACC1-3:not#28.itm} -pin  "ACC1-3:and#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#28.itm}
+load net {ACC1:acc#396.itm(1)} -pin  "ACC1-3:and#1" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#1.itm}
+load net {ACC1-3:and#1.itm} -pin  "ACC1-3:and#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#1.itm}
+load inst "ACC1:acc#433" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53412 -attr oid 1468 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#433} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#433" {A(0)} -attr @path {/sobel/sobel:core/conc#939.itm}
+load net {ACC1:acc#227.psp.sva(1)} -pin  "ACC1:acc#433" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#939.itm}
+load net {ACC1:acc#227.psp.sva(3)} -pin  "ACC1:acc#433" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#939.itm}
+load net {ACC1-3:and#1.itm} -pin  "ACC1:acc#433" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1325.itm}
+load net {ACC1:acc#227.psp.sva(2)} -pin  "ACC1:acc#433" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1325.itm}
+load net {acc.psp#1.sva(3)} -pin  "ACC1:acc#433" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1325.itm}
+load net {ACC1:acc#433.itm(0)} -pin  "ACC1:acc#433" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#433.itm}
+load net {ACC1:acc#433.itm(1)} -pin  "ACC1:acc#433" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#433.itm}
+load net {ACC1:acc#433.itm(2)} -pin  "ACC1:acc#433" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#433.itm}
+load net {ACC1:acc#433.itm(3)} -pin  "ACC1:acc#433" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#433.itm}
+load inst "ACC1-3:not#315" "not(1)" "INTERFACE" -attr xrf 53413 -attr oid 1469 -attr @path {/sobel/sobel:core/ACC1-3:not#315} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:not#315" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#41.itm}
+load net {ACC1-3:not#315.itm} -pin  "ACC1-3:not#315" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#315.itm}
+load inst "ACC1-3:nand" "nand(2,1)" "INTERFACE" -attr xrf 53414 -attr oid 1470 -attr @path {/sobel/sobel:core/ACC1-3:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#396.itm(2)} -pin  "ACC1-3:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva).itm}
+load net {ACC1-3:not#315.itm} -pin  "ACC1-3:nand" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#315.itm}
+load net {ACC1-3:nand.itm} -pin  "ACC1-3:nand" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand.itm}
+load inst "ACC1:acc#432" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53415 -attr oid 1471 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#432} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#432" {A(0)} -attr @path {/sobel/sobel:core/conc#940.itm}
+load net {ACC1:acc#227.psp.sva(3)} -pin  "ACC1:acc#432" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#940.itm}
+load net {ACC1:acc#224.psp.sva(2)} -pin  "ACC1:acc#432" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#940.itm}
+load net {ACC1-3:nand.itm} -pin  "ACC1:acc#432" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1323.itm}
+load net {ACC1:acc#227.psp.sva(4)} -pin  "ACC1:acc#432" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1323.itm}
+load net {ACC1:acc#228.psp.sva(2)} -pin  "ACC1:acc#432" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1323.itm}
+load net {ACC1:acc#432.itm(0)} -pin  "ACC1:acc#432" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#432.itm}
+load net {ACC1:acc#432.itm(1)} -pin  "ACC1:acc#432" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#432.itm}
+load net {ACC1:acc#432.itm(2)} -pin  "ACC1:acc#432" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#432.itm}
+load net {ACC1:acc#432.itm(3)} -pin  "ACC1:acc#432" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#432.itm}
+load inst "ACC1:acc#528" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53416 -attr oid 1472 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#433.itm(1)} -pin  "ACC1:acc#528" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#101.itm}
+load net {ACC1:acc#433.itm(2)} -pin  "ACC1:acc#528" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#101.itm}
+load net {ACC1:acc#433.itm(3)} -pin  "ACC1:acc#528" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#101.itm}
+load net {ACC1:acc#432.itm(1)} -pin  "ACC1:acc#528" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#100.itm}
+load net {ACC1:acc#432.itm(2)} -pin  "ACC1:acc#528" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#100.itm}
+load net {ACC1:acc#432.itm(3)} -pin  "ACC1:acc#528" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#100.itm}
+load net {ACC1:acc#528.itm(0)} -pin  "ACC1:acc#528" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#528.itm(1)} -pin  "ACC1:acc#528" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#528.itm(2)} -pin  "ACC1:acc#528" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#528.itm(3)} -pin  "ACC1:acc#528" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load inst "ACC1:acc#431" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53417 -attr oid 1473 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#431} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#431" {A(0)} -attr @path {/sobel/sobel:core/conc#941.itm}
+load net {acc.psp#1.sva(1)} -pin  "ACC1:acc#431" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#941.itm}
+load net {ACC1:acc#226.psp.sva(2)} -pin  "ACC1:acc#431" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#941.itm}
+load net {ACC1:acc#395.itm(2)} -pin  "ACC1:acc#431" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1321.itm}
+load net {acc.psp#1.sva(3)} -pin  "ACC1:acc#431" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1321.itm}
+load net {ACC1:acc#224.psp#1.sva(2)} -pin  "ACC1:acc#431" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1321.itm}
+load net {ACC1:acc#431.itm(0)} -pin  "ACC1:acc#431" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#431.itm}
+load net {ACC1:acc#431.itm(1)} -pin  "ACC1:acc#431" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#431.itm}
+load net {ACC1:acc#431.itm(2)} -pin  "ACC1:acc#431" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#431.itm}
+load net {ACC1:acc#431.itm(3)} -pin  "ACC1:acc#431" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#431.itm}
+load inst "ACC1:acc#430" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53418 -attr oid 1474 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#430} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#430" {A(0)} -attr @path {/sobel/sobel:core/conc#942.itm}
+load net {acc.psp#1.sva(4)} -pin  "ACC1:acc#430" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#942.itm}
+load net {ACC1-1:acc#25.psp.sva(3)} -pin  "ACC1:acc#430" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#942.itm}
+load net {ACC1:acc#210.psp#1.sva(3)} -pin  "ACC1:acc#430" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1319.itm}
+load net {ACC1:acc#224.psp.sva(1)} -pin  "ACC1:acc#430" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1319.itm}
+load net {acc#20.psp#1.sva(1)} -pin  "ACC1:acc#430" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1319.itm}
+load net {ACC1:acc#430.itm(0)} -pin  "ACC1:acc#430" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#430.itm}
+load net {ACC1:acc#430.itm(1)} -pin  "ACC1:acc#430" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#430.itm}
+load net {ACC1:acc#430.itm(2)} -pin  "ACC1:acc#430" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#430.itm}
+load net {ACC1:acc#430.itm(3)} -pin  "ACC1:acc#430" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#430.itm}
+load inst "ACC1:acc#527" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53419 -attr oid 1475 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#431.itm(1)} -pin  "ACC1:acc#527" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#431.itm(2)} -pin  "ACC1:acc#527" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#431.itm(3)} -pin  "ACC1:acc#527" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#430.itm(1)} -pin  "ACC1:acc#527" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#430.itm(2)} -pin  "ACC1:acc#527" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#430.itm(3)} -pin  "ACC1:acc#527" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#527.itm(0)} -pin  "ACC1:acc#527" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#527.itm(1)} -pin  "ACC1:acc#527" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#527.itm(2)} -pin  "ACC1:acc#527" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#527.itm(3)} -pin  "ACC1:acc#527" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load inst "ACC1:acc#579" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53420 -attr oid 1476 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#528.itm(0)} -pin  "ACC1:acc#579" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#528.itm(1)} -pin  "ACC1:acc#579" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#528.itm(2)} -pin  "ACC1:acc#579" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#528.itm(3)} -pin  "ACC1:acc#579" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#527.itm(0)} -pin  "ACC1:acc#579" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#527.itm(1)} -pin  "ACC1:acc#579" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#527.itm(2)} -pin  "ACC1:acc#579" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#527.itm(3)} -pin  "ACC1:acc#579" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#579.itm(0)} -pin  "ACC1:acc#579" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(1)} -pin  "ACC1:acc#579" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(2)} -pin  "ACC1:acc#579" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(3)} -pin  "ACC1:acc#579" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(4)} -pin  "ACC1:acc#579" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load inst "ACC1:acc#429" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53421 -attr oid 1477 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#429} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#429" {A(0)} -attr @path {/sobel/sobel:core/conc#943.itm}
+load net {ACC1:acc#224.psp.sva(2)} -pin  "ACC1:acc#429" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#943.itm}
+load net {acc#20.psp#1.sva(2)} -pin  "ACC1:acc#429" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#943.itm}
+load net {ACC1:acc#210.psp#1.sva(2)} -pin  "ACC1:acc#429" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1317.itm}
+load net {ACC1:acc#224.psp.sva(3)} -pin  "ACC1:acc#429" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1317.itm}
+load net {acc#20.psp#1.sva(3)} -pin  "ACC1:acc#429" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1317.itm}
+load net {ACC1:acc#429.itm(0)} -pin  "ACC1:acc#429" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#429.itm}
+load net {ACC1:acc#429.itm(1)} -pin  "ACC1:acc#429" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#429.itm}
+load net {ACC1:acc#429.itm(2)} -pin  "ACC1:acc#429" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#429.itm}
+load net {ACC1:acc#429.itm(3)} -pin  "ACC1:acc#429" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#429.itm}
+load inst "ACC1:acc#428" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53422 -attr oid 1478 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#428} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#428" {A(0)} -attr @path {/sobel/sobel:core/conc#944.itm}
+load net {ACC1:acc#228.psp.sva(0)} -pin  "ACC1:acc#428" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#944.itm}
+load net {acc#20.psp#1.sva(4)} -pin  "ACC1:acc#428" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#944.itm}
+load net {ACC1:acc#210.psp#1.sva(1)} -pin  "ACC1:acc#428" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1315.itm}
+load net {ACC1:acc#226.psp.sva(0)} -pin  "ACC1:acc#428" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1315.itm}
+load net {ACC1:acc#217.psp#1.sva(1)} -pin  "ACC1:acc#428" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1315.itm}
+load net {ACC1:acc#428.itm(0)} -pin  "ACC1:acc#428" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#428.itm}
+load net {ACC1:acc#428.itm(1)} -pin  "ACC1:acc#428" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#428.itm}
+load net {ACC1:acc#428.itm(2)} -pin  "ACC1:acc#428" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#428.itm}
+load net {ACC1:acc#428.itm(3)} -pin  "ACC1:acc#428" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#428.itm}
+load inst "ACC1:acc#526" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53423 -attr oid 1479 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#429.itm(1)} -pin  "ACC1:acc#526" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#429.itm(2)} -pin  "ACC1:acc#526" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#429.itm(3)} -pin  "ACC1:acc#526" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#428.itm(1)} -pin  "ACC1:acc#526" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#428.itm(2)} -pin  "ACC1:acc#526" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#428.itm(3)} -pin  "ACC1:acc#526" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#526.itm(0)} -pin  "ACC1:acc#526" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#526.itm(1)} -pin  "ACC1:acc#526" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#526.itm(2)} -pin  "ACC1:acc#526" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#526.itm(3)} -pin  "ACC1:acc#526" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load inst "ACC1:acc#427" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53424 -attr oid 1480 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#427} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#427" {A(0)} -attr @path {/sobel/sobel:core/conc#945.itm}
+load net {ACC1:acc#226.psp.sva(1)} -pin  "ACC1:acc#427" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#945.itm}
+load net {ACC1:acc#217.psp#1.sva(2)} -pin  "ACC1:acc#427" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#945.itm}
+load net {ACC1-1:acc#25.psp.sva(4)} -pin  "ACC1:acc#427" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1313.itm}
+load net {ACC1:acc#226.psp.sva(2)} -pin  "ACC1:acc#427" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1313.itm}
+load net {ACC1:acc#217.psp#1.sva(3)} -pin  "ACC1:acc#427" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1313.itm}
+load net {ACC1:acc#427.itm(0)} -pin  "ACC1:acc#427" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#427.itm}
+load net {ACC1:acc#427.itm(1)} -pin  "ACC1:acc#427" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#427.itm}
+load net {ACC1:acc#427.itm(2)} -pin  "ACC1:acc#427" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#427.itm}
+load net {ACC1:acc#427.itm(3)} -pin  "ACC1:acc#427" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#427.itm}
+load inst "ACC1-3:not#313" "not(1)" "INTERFACE" -attr xrf 53425 -attr oid 1481 -attr @path {/sobel/sobel:core/ACC1-3:not#313} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1-3:not#313" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#33.itm}
+load net {ACC1-3:not#313.itm} -pin  "ACC1-3:not#313" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#313.itm}
+load inst "ACC1-3:nand#4" "nand(2,1)" "INTERFACE" -attr xrf 53426 -attr oid 1482 -attr @path {/sobel/sobel:core/ACC1-3:nand#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#424.itm(2)} -pin  "ACC1-3:nand#4" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#19.sva)#2.itm}
+load net {ACC1-3:not#313.itm} -pin  "ACC1-3:nand#4" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#313.itm}
+load net {ACC1-3:nand#4.itm} -pin  "ACC1-3:nand#4" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand#4.itm}
+load inst "ACC1:acc#426" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53427 -attr oid 1483 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#426} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#426" {A(0)} -attr @path {/sobel/sobel:core/conc#946.itm}
+load net {ACC1:acc#226.psp.sva(3)} -pin  "ACC1:acc#426" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#946.itm}
+load net {ACC1:acc#423.itm(2)} -pin  "ACC1:acc#426" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#946.itm}
+load net {ACC1-1:acc#25.psp.sva(3)} -pin  "ACC1:acc#426" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1311.itm}
+load net {ACC1:acc#224.psp#1.sva(0)} -pin  "ACC1:acc#426" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1311.itm}
+load net {ACC1-3:nand#4.itm} -pin  "ACC1:acc#426" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1311.itm}
+load net {ACC1:acc#426.itm(0)} -pin  "ACC1:acc#426" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#426.itm}
+load net {ACC1:acc#426.itm(1)} -pin  "ACC1:acc#426" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#426.itm}
+load net {ACC1:acc#426.itm(2)} -pin  "ACC1:acc#426" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#426.itm}
+load net {ACC1:acc#426.itm(3)} -pin  "ACC1:acc#426" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#426.itm}
+load inst "ACC1:acc#525" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53428 -attr oid 1484 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#427.itm(1)} -pin  "ACC1:acc#525" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#427.itm(2)} -pin  "ACC1:acc#525" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#427.itm(3)} -pin  "ACC1:acc#525" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#426.itm(1)} -pin  "ACC1:acc#525" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#426.itm(2)} -pin  "ACC1:acc#525" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#426.itm(3)} -pin  "ACC1:acc#525" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#525.itm(0)} -pin  "ACC1:acc#525" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#525.itm(1)} -pin  "ACC1:acc#525" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#525.itm(2)} -pin  "ACC1:acc#525" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#525.itm(3)} -pin  "ACC1:acc#525" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load inst "ACC1:acc#578" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53429 -attr oid 1485 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#526.itm(0)} -pin  "ACC1:acc#578" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#526.itm(1)} -pin  "ACC1:acc#578" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#526.itm(2)} -pin  "ACC1:acc#578" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#526.itm(3)} -pin  "ACC1:acc#578" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#525.itm(0)} -pin  "ACC1:acc#578" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#525.itm(1)} -pin  "ACC1:acc#578" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#525.itm(2)} -pin  "ACC1:acc#578" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#525.itm(3)} -pin  "ACC1:acc#578" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#578.itm(0)} -pin  "ACC1:acc#578" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(1)} -pin  "ACC1:acc#578" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(2)} -pin  "ACC1:acc#578" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(3)} -pin  "ACC1:acc#578" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(4)} -pin  "ACC1:acc#578" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load inst "ACC1:acc#604" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 53430 -attr oid 1486 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#579.itm(0)} -pin  "ACC1:acc#604" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(1)} -pin  "ACC1:acc#604" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(2)} -pin  "ACC1:acc#604" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(3)} -pin  "ACC1:acc#604" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(4)} -pin  "ACC1:acc#604" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#578.itm(0)} -pin  "ACC1:acc#604" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(1)} -pin  "ACC1:acc#604" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(2)} -pin  "ACC1:acc#604" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(3)} -pin  "ACC1:acc#604" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(4)} -pin  "ACC1:acc#604" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#604.itm(0)} -pin  "ACC1:acc#604" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(1)} -pin  "ACC1:acc#604" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(2)} -pin  "ACC1:acc#604" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(3)} -pin  "ACC1:acc#604" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(4)} -pin  "ACC1:acc#604" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(5)} -pin  "ACC1:acc#604" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load inst "ACC1:acc#622" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 53431 -attr oid 1487 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#605.itm(0)} -pin  "ACC1:acc#622" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(1)} -pin  "ACC1:acc#622" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(2)} -pin  "ACC1:acc#622" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(3)} -pin  "ACC1:acc#622" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(4)} -pin  "ACC1:acc#622" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(5)} -pin  "ACC1:acc#622" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#604.itm(0)} -pin  "ACC1:acc#622" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(1)} -pin  "ACC1:acc#622" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(2)} -pin  "ACC1:acc#622" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(3)} -pin  "ACC1:acc#622" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(4)} -pin  "ACC1:acc#622" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(5)} -pin  "ACC1:acc#622" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#622.itm(0)} -pin  "ACC1:acc#622" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(1)} -pin  "ACC1:acc#622" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(2)} -pin  "ACC1:acc#622" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(3)} -pin  "ACC1:acc#622" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(4)} -pin  "ACC1:acc#622" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(5)} -pin  "ACC1:acc#622" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(6)} -pin  "ACC1:acc#622" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load inst "ACC1:acc#636" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 53432 -attr oid 1488 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#623.itm(0)} -pin  "ACC1:acc#636" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(1)} -pin  "ACC1:acc#636" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(2)} -pin  "ACC1:acc#636" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(3)} -pin  "ACC1:acc#636" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(4)} -pin  "ACC1:acc#636" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(5)} -pin  "ACC1:acc#636" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(6)} -pin  "ACC1:acc#636" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#622.itm(0)} -pin  "ACC1:acc#636" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(1)} -pin  "ACC1:acc#636" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(2)} -pin  "ACC1:acc#636" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(3)} -pin  "ACC1:acc#636" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(4)} -pin  "ACC1:acc#636" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(5)} -pin  "ACC1:acc#636" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(6)} -pin  "ACC1:acc#636" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#636.itm(0)} -pin  "ACC1:acc#636" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(1)} -pin  "ACC1:acc#636" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(2)} -pin  "ACC1:acc#636" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(3)} -pin  "ACC1:acc#636" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(4)} -pin  "ACC1:acc#636" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(5)} -pin  "ACC1:acc#636" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(6)} -pin  "ACC1:acc#636" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(7)} -pin  "ACC1:acc#636" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load inst "ACC1:acc#721" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53433 -attr oid 1489 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#721} -attr area 4.303074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {acc#20.psp#1.sva(6)} -pin  "ACC1:acc#721" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#947.itm}
+load net {GND} -pin  "ACC1:acc#721" {A(1)} -attr @path {/sobel/sobel:core/conc#947.itm}
+load net {acc#20.psp#1.sva(6)} -pin  "ACC1:acc#721" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#947.itm}
+load net {ACC1:acc#226.psp.sva(4)} -pin  "ACC1:acc#721" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1119.itm}
+load net {acc#20.psp#1.sva(5)} -pin  "ACC1:acc#721" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1119.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#721" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1119.itm}
+load net {ACC1:acc#721.itm(0)} -pin  "ACC1:acc#721" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#721.itm}
+load net {ACC1:acc#721.itm(1)} -pin  "ACC1:acc#721" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#721.itm}
+load net {ACC1:acc#721.itm(2)} -pin  "ACC1:acc#721" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#721.itm}
+load net {ACC1:acc#721.itm(3)} -pin  "ACC1:acc#721" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#721.itm}
+load inst "ACC1:acc#722" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53434 -attr oid 1490 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#722} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#228.psp.sva(1)} -pin  "ACC1:acc#722" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1453.itm}
+load net {acc#20.psp#1.sva(6)} -pin  "ACC1:acc#722" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1453.itm}
+load net {ACC1:acc#224.psp.sva(10)} -pin  "ACC1:acc#722" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1544.itm}
+load net {ACC1:acc#224.psp.sva(10)} -pin  "ACC1:acc#722" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1544.itm}
+load net {ACC1:acc#722.itm(0)} -pin  "ACC1:acc#722" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#722.itm}
+load net {ACC1:acc#722.itm(1)} -pin  "ACC1:acc#722" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#722.itm}
+load net {ACC1:acc#722.itm(2)} -pin  "ACC1:acc#722" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#722.itm}
+load inst "ACC1:acc#723" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53435 -attr oid 1491 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#723} -attr area 4.303074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#226.psp.sva(6)} -pin  "ACC1:acc#723" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1120.itm}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1:acc#723" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1120.itm}
+load net {ACC1:acc#224.psp.sva(6)} -pin  "ACC1:acc#723" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1120.itm}
+load net {ACC1:acc#227.psp.sva(5)} -pin  "ACC1:acc#723" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#948.itm}
+load net {GND} -pin  "ACC1:acc#723" {B(1)} -attr @path {/sobel/sobel:core/conc#948.itm}
+load net {ACC1:acc#228.psp.sva(6)} -pin  "ACC1:acc#723" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#948.itm}
+load net {ACC1:acc#723.itm(0)} -pin  "ACC1:acc#723" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#723.itm}
+load net {ACC1:acc#723.itm(1)} -pin  "ACC1:acc#723" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#723.itm}
+load net {ACC1:acc#723.itm(2)} -pin  "ACC1:acc#723" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#723.itm}
+load net {ACC1:acc#723.itm(3)} -pin  "ACC1:acc#723" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#723.itm}
+load inst "ACC1:acc#634" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 53436 -attr oid 1492 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#722.itm(0)} -pin  "ACC1:acc#634" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#722.itm(1)} -pin  "ACC1:acc#634" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#722.itm(2)} -pin  "ACC1:acc#634" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#721.itm(0)} -pin  "ACC1:acc#634" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#721.itm(1)} -pin  "ACC1:acc#634" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#721.itm(2)} -pin  "ACC1:acc#634" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#721.itm(3)} -pin  "ACC1:acc#634" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#724.cse(0)} -pin  "ACC1:acc#634" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#724.cse(1)} -pin  "ACC1:acc#634" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#724.cse(2)} -pin  "ACC1:acc#634" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#723.itm(0)} -pin  "ACC1:acc#634" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#723.itm(1)} -pin  "ACC1:acc#634" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#723.itm(2)} -pin  "ACC1:acc#634" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#723.itm(3)} -pin  "ACC1:acc#634" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#634.itm(0)} -pin  "ACC1:acc#634" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(1)} -pin  "ACC1:acc#634" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(2)} -pin  "ACC1:acc#634" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(3)} -pin  "ACC1:acc#634" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(4)} -pin  "ACC1:acc#634" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(5)} -pin  "ACC1:acc#634" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(6)} -pin  "ACC1:acc#634" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(7)} -pin  "ACC1:acc#634" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load inst "ACC1:acc#644" "add(8,0,8,0,9)" "INTERFACE" -attr xrf 53437 -attr oid 1493 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9)"
+load net {ACC1:acc#636.itm(0)} -pin  "ACC1:acc#644" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(1)} -pin  "ACC1:acc#644" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(2)} -pin  "ACC1:acc#644" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(3)} -pin  "ACC1:acc#644" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(4)} -pin  "ACC1:acc#644" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(5)} -pin  "ACC1:acc#644" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(6)} -pin  "ACC1:acc#644" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(7)} -pin  "ACC1:acc#644" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#634.itm(0)} -pin  "ACC1:acc#644" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(1)} -pin  "ACC1:acc#644" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(2)} -pin  "ACC1:acc#644" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(3)} -pin  "ACC1:acc#644" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(4)} -pin  "ACC1:acc#644" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(5)} -pin  "ACC1:acc#644" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(6)} -pin  "ACC1:acc#644" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(7)} -pin  "ACC1:acc#644" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#644.itm(0)} -pin  "ACC1:acc#644" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(1)} -pin  "ACC1:acc#644" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(2)} -pin  "ACC1:acc#644" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(3)} -pin  "ACC1:acc#644" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(4)} -pin  "ACC1:acc#644" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(5)} -pin  "ACC1:acc#644" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(6)} -pin  "ACC1:acc#644" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(7)} -pin  "ACC1:acc#644" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(8)} -pin  "ACC1:acc#644" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load inst "ACC1:acc#725" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 53438 -attr oid 1494 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#725} -attr area 2.320458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#226.psp.sva(6)} -pin  "ACC1:acc#725" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#36.itm}
+load net {ACC1:acc#224.psp#1.sva(6)} -pin  "ACC1:acc#725" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#42.itm}
+load net {ACC1:acc#725.itm(0)} -pin  "ACC1:acc#725" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#725.itm}
+load net {ACC1:acc#725.itm(1)} -pin  "ACC1:acc#725" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#725.itm}
+load inst "ACC1:acc#726" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 53439 -attr oid 1495 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#726} -attr area 2.320458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#227.psp.sva(7)} -pin  "ACC1:acc#726" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#2.itm}
+load net {acc.psp#1.sva(5)} -pin  "ACC1:acc#726" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#9.itm}
+load net {ACC1:acc#726.itm(0)} -pin  "ACC1:acc#726" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#726.itm}
+load net {ACC1:acc#726.itm(1)} -pin  "ACC1:acc#726" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#726.itm}
+load inst "ACC1:acc#728" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 53440 -attr oid 1496 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#728} -attr area 2.320458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1-1:acc#25.psp.sva(7)} -pin  "ACC1:acc#728" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#19.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#728" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#81.itm}
+load net {ACC1:acc#728.itm(0)} -pin  "ACC1:acc#728" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#728.itm}
+load net {ACC1:acc#728.itm(1)} -pin  "ACC1:acc#728" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#728.itm}
+load inst "ACC1:acc#729" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 53441 -attr oid 1497 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#729} -attr area 2.320458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#729" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#8.itm}
+load net {ACC1:acc#224.psp.sva(4)} -pin  "ACC1:acc#729" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#41.itm}
+load net {ACC1:acc#729.itm(0)} -pin  "ACC1:acc#729" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#729.itm}
+load net {ACC1:acc#729.itm(1)} -pin  "ACC1:acc#729" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#729.itm}
+load inst "ACC1:acc#633" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 53442 -attr oid 1498 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#724.cse(0)} -pin  "ACC1:acc#633" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#724.cse(1)} -pin  "ACC1:acc#633" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#724.cse(2)} -pin  "ACC1:acc#633" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#726.itm(0)} -pin  "ACC1:acc#633" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#726.itm(1)} -pin  "ACC1:acc#633" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#725.itm(0)} -pin  "ACC1:acc#633" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#725.itm(1)} -pin  "ACC1:acc#633" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#724.cse(0)} -pin  "ACC1:acc#633" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#724.cse(1)} -pin  "ACC1:acc#633" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#724.cse(2)} -pin  "ACC1:acc#633" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#729.itm(0)} -pin  "ACC1:acc#633" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#729.itm(1)} -pin  "ACC1:acc#633" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#728.itm(0)} -pin  "ACC1:acc#633" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#728.itm(1)} -pin  "ACC1:acc#633" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#633.itm(0)} -pin  "ACC1:acc#633" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(1)} -pin  "ACC1:acc#633" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(2)} -pin  "ACC1:acc#633" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(3)} -pin  "ACC1:acc#633" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(4)} -pin  "ACC1:acc#633" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(5)} -pin  "ACC1:acc#633" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(6)} -pin  "ACC1:acc#633" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(7)} -pin  "ACC1:acc#633" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load inst "ACC1:acc#632" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 53443 -attr oid 1499 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {ACC1:acc#632.itm(0)} -pin  "ACC1:acc#632" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(1)} -pin  "ACC1:acc#632" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(2)} -pin  "ACC1:acc#632" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(3)} -pin  "ACC1:acc#632" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(4)} -pin  "ACC1:acc#632" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(5)} -pin  "ACC1:acc#632" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(6)} -pin  "ACC1:acc#632" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(7)} -pin  "ACC1:acc#632" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load inst "ACC1:acc#643" "add(8,0,8,0,9)" "INTERFACE" -attr xrf 53444 -attr oid 1500 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9)"
+load net {ACC1:acc#633.itm(0)} -pin  "ACC1:acc#643" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(1)} -pin  "ACC1:acc#643" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(2)} -pin  "ACC1:acc#643" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(3)} -pin  "ACC1:acc#643" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(4)} -pin  "ACC1:acc#643" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(5)} -pin  "ACC1:acc#643" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(6)} -pin  "ACC1:acc#643" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(7)} -pin  "ACC1:acc#643" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#632.itm(0)} -pin  "ACC1:acc#643" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(1)} -pin  "ACC1:acc#643" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(2)} -pin  "ACC1:acc#643" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(3)} -pin  "ACC1:acc#643" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(4)} -pin  "ACC1:acc#643" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(5)} -pin  "ACC1:acc#643" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(6)} -pin  "ACC1:acc#643" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(7)} -pin  "ACC1:acc#643" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#643.itm(0)} -pin  "ACC1:acc#643" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(1)} -pin  "ACC1:acc#643" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(2)} -pin  "ACC1:acc#643" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(3)} -pin  "ACC1:acc#643" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(4)} -pin  "ACC1:acc#643" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(5)} -pin  "ACC1:acc#643" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(6)} -pin  "ACC1:acc#643" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(7)} -pin  "ACC1:acc#643" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(8)} -pin  "ACC1:acc#643" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load inst "ACC1:acc#649" "add(9,0,9,0,10)" "INTERFACE" -attr xrf 53445 -attr oid 1501 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649} -attr area 10.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,0,10)"
+load net {ACC1:acc#644.itm(0)} -pin  "ACC1:acc#649" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(1)} -pin  "ACC1:acc#649" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(2)} -pin  "ACC1:acc#649" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(3)} -pin  "ACC1:acc#649" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(4)} -pin  "ACC1:acc#649" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(5)} -pin  "ACC1:acc#649" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(6)} -pin  "ACC1:acc#649" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(7)} -pin  "ACC1:acc#649" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(8)} -pin  "ACC1:acc#649" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#643.itm(0)} -pin  "ACC1:acc#649" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(1)} -pin  "ACC1:acc#649" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(2)} -pin  "ACC1:acc#649" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(3)} -pin  "ACC1:acc#649" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(4)} -pin  "ACC1:acc#649" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(5)} -pin  "ACC1:acc#649" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(6)} -pin  "ACC1:acc#649" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(7)} -pin  "ACC1:acc#649" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(8)} -pin  "ACC1:acc#649" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#649.itm(0)} -pin  "ACC1:acc#649" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(1)} -pin  "ACC1:acc#649" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(2)} -pin  "ACC1:acc#649" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(3)} -pin  "ACC1:acc#649" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(4)} -pin  "ACC1:acc#649" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(5)} -pin  "ACC1:acc#649" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(6)} -pin  "ACC1:acc#649" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(7)} -pin  "ACC1:acc#649" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(8)} -pin  "ACC1:acc#649" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(9)} -pin  "ACC1:acc#649" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load inst "ACC1:acc#631" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 53446 -attr oid 1502 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#631.itm(0)} -pin  "ACC1:acc#631" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(1)} -pin  "ACC1:acc#631" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(2)} -pin  "ACC1:acc#631" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(3)} -pin  "ACC1:acc#631" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(4)} -pin  "ACC1:acc#631" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(5)} -pin  "ACC1:acc#631" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(6)} -pin  "ACC1:acc#631" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(7)} -pin  "ACC1:acc#631" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load inst "ACC1:acc#630" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 53447 -attr oid 1503 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {GND} -pin  "ACC1:acc#630" {A(2)} -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {ACC1:acc#630.itm(0)} -pin  "ACC1:acc#630" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(1)} -pin  "ACC1:acc#630" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(2)} -pin  "ACC1:acc#630" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(3)} -pin  "ACC1:acc#630" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(4)} -pin  "ACC1:acc#630" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(5)} -pin  "ACC1:acc#630" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(6)} -pin  "ACC1:acc#630" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(7)} -pin  "ACC1:acc#630" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load inst "ACC1:acc#642" "add(8,0,8,0,9)" "INTERFACE" -attr xrf 53448 -attr oid 1504 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9)"
+load net {ACC1:acc#631.itm(0)} -pin  "ACC1:acc#642" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(1)} -pin  "ACC1:acc#642" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(2)} -pin  "ACC1:acc#642" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(3)} -pin  "ACC1:acc#642" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(4)} -pin  "ACC1:acc#642" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(5)} -pin  "ACC1:acc#642" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(6)} -pin  "ACC1:acc#642" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(7)} -pin  "ACC1:acc#642" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#630.itm(0)} -pin  "ACC1:acc#642" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(1)} -pin  "ACC1:acc#642" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(2)} -pin  "ACC1:acc#642" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(3)} -pin  "ACC1:acc#642" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(4)} -pin  "ACC1:acc#642" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(5)} -pin  "ACC1:acc#642" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(6)} -pin  "ACC1:acc#642" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(7)} -pin  "ACC1:acc#642" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#642.itm(0)} -pin  "ACC1:acc#642" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(1)} -pin  "ACC1:acc#642" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(2)} -pin  "ACC1:acc#642" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(3)} -pin  "ACC1:acc#642" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(4)} -pin  "ACC1:acc#642" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(5)} -pin  "ACC1:acc#642" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(6)} -pin  "ACC1:acc#642" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(7)} -pin  "ACC1:acc#642" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(8)} -pin  "ACC1:acc#642" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load inst "ACC1:acc#629" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 53449 -attr oid 1505 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#629" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#629" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {GND} -pin  "ACC1:acc#629" {A(2)} -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#629" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#629" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#629" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#629" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#629.itm(0)} -pin  "ACC1:acc#629" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(1)} -pin  "ACC1:acc#629" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(2)} -pin  "ACC1:acc#629" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(3)} -pin  "ACC1:acc#629" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(4)} -pin  "ACC1:acc#629" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(5)} -pin  "ACC1:acc#629" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(6)} -pin  "ACC1:acc#629" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(7)} -pin  "ACC1:acc#629" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load inst "ACC1:acc#628" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 53450 -attr oid 1506 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#628" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#628" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {GND} -pin  "ACC1:acc#628" {A(2)} -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#628" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#628" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#628" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#628" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {ACC1:acc#628.itm(0)} -pin  "ACC1:acc#628" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(1)} -pin  "ACC1:acc#628" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(2)} -pin  "ACC1:acc#628" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(3)} -pin  "ACC1:acc#628" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(4)} -pin  "ACC1:acc#628" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(5)} -pin  "ACC1:acc#628" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(6)} -pin  "ACC1:acc#628" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(7)} -pin  "ACC1:acc#628" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load inst "ACC1:acc#641" "add(8,0,8,0,9)" "INTERFACE" -attr xrf 53451 -attr oid 1507 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9)"
+load net {ACC1:acc#629.itm(0)} -pin  "ACC1:acc#641" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(1)} -pin  "ACC1:acc#641" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(2)} -pin  "ACC1:acc#641" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(3)} -pin  "ACC1:acc#641" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(4)} -pin  "ACC1:acc#641" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(5)} -pin  "ACC1:acc#641" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(6)} -pin  "ACC1:acc#641" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(7)} -pin  "ACC1:acc#641" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#628.itm(0)} -pin  "ACC1:acc#641" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(1)} -pin  "ACC1:acc#641" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(2)} -pin  "ACC1:acc#641" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(3)} -pin  "ACC1:acc#641" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(4)} -pin  "ACC1:acc#641" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(5)} -pin  "ACC1:acc#641" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(6)} -pin  "ACC1:acc#641" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(7)} -pin  "ACC1:acc#641" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#641.itm(0)} -pin  "ACC1:acc#641" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(1)} -pin  "ACC1:acc#641" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(2)} -pin  "ACC1:acc#641" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(3)} -pin  "ACC1:acc#641" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(4)} -pin  "ACC1:acc#641" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(5)} -pin  "ACC1:acc#641" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(6)} -pin  "ACC1:acc#641" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(7)} -pin  "ACC1:acc#641" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(8)} -pin  "ACC1:acc#641" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load inst "ACC1:acc#648" "add(9,0,9,0,10)" "INTERFACE" -attr xrf 53452 -attr oid 1508 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648} -attr area 10.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,0,10)"
+load net {ACC1:acc#642.itm(0)} -pin  "ACC1:acc#648" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(1)} -pin  "ACC1:acc#648" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(2)} -pin  "ACC1:acc#648" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(3)} -pin  "ACC1:acc#648" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(4)} -pin  "ACC1:acc#648" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(5)} -pin  "ACC1:acc#648" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(6)} -pin  "ACC1:acc#648" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(7)} -pin  "ACC1:acc#648" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(8)} -pin  "ACC1:acc#648" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#641.itm(0)} -pin  "ACC1:acc#648" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(1)} -pin  "ACC1:acc#648" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(2)} -pin  "ACC1:acc#648" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(3)} -pin  "ACC1:acc#648" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(4)} -pin  "ACC1:acc#648" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(5)} -pin  "ACC1:acc#648" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(6)} -pin  "ACC1:acc#648" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(7)} -pin  "ACC1:acc#648" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(8)} -pin  "ACC1:acc#648" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#648.itm(0)} -pin  "ACC1:acc#648" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(1)} -pin  "ACC1:acc#648" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(2)} -pin  "ACC1:acc#648" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(3)} -pin  "ACC1:acc#648" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(4)} -pin  "ACC1:acc#648" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(5)} -pin  "ACC1:acc#648" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(6)} -pin  "ACC1:acc#648" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(7)} -pin  "ACC1:acc#648" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(8)} -pin  "ACC1:acc#648" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(9)} -pin  "ACC1:acc#648" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load inst "ACC1:acc#652" "add(10,0,10,0,11)" "INTERFACE" -attr xrf 53453 -attr oid 1509 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652} -attr area 11.241230 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,11)"
+load net {ACC1:acc#649.itm(0)} -pin  "ACC1:acc#652" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(1)} -pin  "ACC1:acc#652" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(2)} -pin  "ACC1:acc#652" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(3)} -pin  "ACC1:acc#652" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(4)} -pin  "ACC1:acc#652" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(5)} -pin  "ACC1:acc#652" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(6)} -pin  "ACC1:acc#652" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(7)} -pin  "ACC1:acc#652" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(8)} -pin  "ACC1:acc#652" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(9)} -pin  "ACC1:acc#652" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#648.itm(0)} -pin  "ACC1:acc#652" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(1)} -pin  "ACC1:acc#652" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(2)} -pin  "ACC1:acc#652" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(3)} -pin  "ACC1:acc#652" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(4)} -pin  "ACC1:acc#652" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(5)} -pin  "ACC1:acc#652" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(6)} -pin  "ACC1:acc#652" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(7)} -pin  "ACC1:acc#652" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(8)} -pin  "ACC1:acc#652" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(9)} -pin  "ACC1:acc#652" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#652.itm(0)} -pin  "ACC1:acc#652" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(1)} -pin  "ACC1:acc#652" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(2)} -pin  "ACC1:acc#652" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(3)} -pin  "ACC1:acc#652" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(4)} -pin  "ACC1:acc#652" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(5)} -pin  "ACC1:acc#652" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(6)} -pin  "ACC1:acc#652" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(7)} -pin  "ACC1:acc#652" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(8)} -pin  "ACC1:acc#652" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(9)} -pin  "ACC1:acc#652" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(10)} -pin  "ACC1:acc#652" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load inst "reg(ACC1:acc#652.itm#1)" "reg(11,1,1,-1,0)" "INTERFACE" -attr xrf 53454 -attr oid 1510 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#652.itm#1)}
+load net {ACC1:acc#652.itm(0)} -pin  "reg(ACC1:acc#652.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(1)} -pin  "reg(ACC1:acc#652.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(2)} -pin  "reg(ACC1:acc#652.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(3)} -pin  "reg(ACC1:acc#652.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(4)} -pin  "reg(ACC1:acc#652.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(5)} -pin  "reg(ACC1:acc#652.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(6)} -pin  "reg(ACC1:acc#652.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(7)} -pin  "reg(ACC1:acc#652.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(8)} -pin  "reg(ACC1:acc#652.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(9)} -pin  "reg(ACC1:acc#652.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(10)} -pin  "reg(ACC1:acc#652.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_11}
+load net {clk} -pin  "reg(ACC1:acc#652.itm#1)" {clk} -attr xrf 53455 -attr oid 1511 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#652.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#652.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#652.itm#1(0)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(1)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(2)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(3)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(4)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(5)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(6)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(7)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(8)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(9)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(10)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load inst "ACC1:acc#564" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53456 -attr oid 1512 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#509.cse(0)} -pin  "ACC1:acc#564" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(1)} -pin  "ACC1:acc#564" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(2)} -pin  "ACC1:acc#564" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(0)} -pin  "ACC1:acc#564" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(1)} -pin  "ACC1:acc#564" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(2)} -pin  "ACC1:acc#564" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#564.itm(0)} -pin  "ACC1:acc#564" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#564.itm(1)} -pin  "ACC1:acc#564" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#564.itm(2)} -pin  "ACC1:acc#564" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#564.itm(3)} -pin  "ACC1:acc#564" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load inst "ACC1:acc#507" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53457 -attr oid 1513 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#507" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1058.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#507" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1058.itm}
+load net {ACC1:acc#227.psp.sva(5)} -pin  "ACC1:acc#507" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1031.itm}
+load net {ACC1:acc#227.psp.sva(5)} -pin  "ACC1:acc#507" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1031.itm}
+load net {ACC1:acc#507.itm(0)} -pin  "ACC1:acc#507" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load net {ACC1:acc#507.itm(1)} -pin  "ACC1:acc#507" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load net {ACC1:acc#507.itm(2)} -pin  "ACC1:acc#507" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load inst "ACC1:acc#563" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53458 -attr oid 1514 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#507.itm(0)} -pin  "ACC1:acc#563" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load net {ACC1:acc#507.itm(1)} -pin  "ACC1:acc#563" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load net {ACC1:acc#507.itm(2)} -pin  "ACC1:acc#563" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#563" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#563" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#563" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#563.itm(0)} -pin  "ACC1:acc#563" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#563.itm(1)} -pin  "ACC1:acc#563" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#563.itm(2)} -pin  "ACC1:acc#563" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#563.itm(3)} -pin  "ACC1:acc#563" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load inst "ACC1:acc#597" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53459 -attr oid 1515 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#564.itm(0)} -pin  "ACC1:acc#597" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#564.itm(1)} -pin  "ACC1:acc#597" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#564.itm(2)} -pin  "ACC1:acc#597" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#564.itm(3)} -pin  "ACC1:acc#597" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#563.itm(0)} -pin  "ACC1:acc#597" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#563.itm(1)} -pin  "ACC1:acc#597" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#563.itm(2)} -pin  "ACC1:acc#597" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#563.itm(3)} -pin  "ACC1:acc#597" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#597.itm(0)} -pin  "ACC1:acc#597" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(1)} -pin  "ACC1:acc#597" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(2)} -pin  "ACC1:acc#597" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(3)} -pin  "ACC1:acc#597" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(4)} -pin  "ACC1:acc#597" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load inst "ACC1:acc#561" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53460 -attr oid 1516 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#561" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#561" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#561" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#502.cse(0)} -pin  "ACC1:acc#561" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#502.cse(1)} -pin  "ACC1:acc#561" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#502.cse(2)} -pin  "ACC1:acc#561" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#561.itm(0)} -pin  "ACC1:acc#561" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#561.itm(1)} -pin  "ACC1:acc#561" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#561.itm(2)} -pin  "ACC1:acc#561" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#561.itm(3)} -pin  "ACC1:acc#561" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load inst "ACC1:acc#596" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53461 -attr oid 1517 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#562.ncse(0)} -pin  "ACC1:acc#596" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(1)} -pin  "ACC1:acc#596" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(2)} -pin  "ACC1:acc#596" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(3)} -pin  "ACC1:acc#596" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#561.itm(0)} -pin  "ACC1:acc#596" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#561.itm(1)} -pin  "ACC1:acc#596" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#561.itm(2)} -pin  "ACC1:acc#596" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#561.itm(3)} -pin  "ACC1:acc#596" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#596.itm(0)} -pin  "ACC1:acc#596" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(1)} -pin  "ACC1:acc#596" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(2)} -pin  "ACC1:acc#596" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(3)} -pin  "ACC1:acc#596" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(4)} -pin  "ACC1:acc#596" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load inst "ACC1:acc#613" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 53462 -attr oid 1518 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#597.itm(0)} -pin  "ACC1:acc#613" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(1)} -pin  "ACC1:acc#613" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(2)} -pin  "ACC1:acc#613" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(3)} -pin  "ACC1:acc#613" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(4)} -pin  "ACC1:acc#613" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#596.itm(0)} -pin  "ACC1:acc#613" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(1)} -pin  "ACC1:acc#613" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(2)} -pin  "ACC1:acc#613" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(3)} -pin  "ACC1:acc#613" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(4)} -pin  "ACC1:acc#613" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#613.itm(0)} -pin  "ACC1:acc#613" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(1)} -pin  "ACC1:acc#613" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(2)} -pin  "ACC1:acc#613" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(3)} -pin  "ACC1:acc#613" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(4)} -pin  "ACC1:acc#613" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(5)} -pin  "ACC1:acc#613" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load inst "ACC1:acc#499" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53463 -attr oid 1519 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#499" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1053.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#499" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1053.itm}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1:acc#499" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#72.itm}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1:acc#499" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#72.itm}
+load net {ACC1:acc#499.itm(0)} -pin  "ACC1:acc#499" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load net {ACC1:acc#499.itm(1)} -pin  "ACC1:acc#499" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load net {ACC1:acc#499.itm(2)} -pin  "ACC1:acc#499" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load inst "ACC1:acc#498" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53464 -attr oid 1520 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#498" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#73.itm}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#498" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#73.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#498" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1054.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#498" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1054.itm}
+load net {ACC1:acc#498.itm(0)} -pin  "ACC1:acc#498" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load net {ACC1:acc#498.itm(1)} -pin  "ACC1:acc#498" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load net {ACC1:acc#498.itm(2)} -pin  "ACC1:acc#498" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load inst "ACC1:acc#559" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53465 -attr oid 1521 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#499.itm(0)} -pin  "ACC1:acc#559" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load net {ACC1:acc#499.itm(1)} -pin  "ACC1:acc#559" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load net {ACC1:acc#499.itm(2)} -pin  "ACC1:acc#559" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load net {ACC1:acc#498.itm(0)} -pin  "ACC1:acc#559" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load net {ACC1:acc#498.itm(1)} -pin  "ACC1:acc#559" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load net {ACC1:acc#498.itm(2)} -pin  "ACC1:acc#559" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load net {ACC1:acc#559.itm(0)} -pin  "ACC1:acc#559" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#559.itm(1)} -pin  "ACC1:acc#559" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#559.itm(2)} -pin  "ACC1:acc#559" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#559.itm(3)} -pin  "ACC1:acc#559" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load inst "ACC1:acc#595" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53466 -attr oid 1522 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#562.ncse(0)} -pin  "ACC1:acc#595" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(1)} -pin  "ACC1:acc#595" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(2)} -pin  "ACC1:acc#595" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(3)} -pin  "ACC1:acc#595" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#559.itm(0)} -pin  "ACC1:acc#595" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#559.itm(1)} -pin  "ACC1:acc#595" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#559.itm(2)} -pin  "ACC1:acc#595" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#559.itm(3)} -pin  "ACC1:acc#595" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#595.itm(0)} -pin  "ACC1:acc#595" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(1)} -pin  "ACC1:acc#595" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(2)} -pin  "ACC1:acc#595" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(3)} -pin  "ACC1:acc#595" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(4)} -pin  "ACC1:acc#595" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load inst "ACC1:acc#594" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53467 -attr oid 1523 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#562.ncse(0)} -pin  "ACC1:acc#594" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(1)} -pin  "ACC1:acc#594" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(2)} -pin  "ACC1:acc#594" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(3)} -pin  "ACC1:acc#594" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(0)} -pin  "ACC1:acc#594" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(1)} -pin  "ACC1:acc#594" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(2)} -pin  "ACC1:acc#594" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(3)} -pin  "ACC1:acc#594" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#594.itm(0)} -pin  "ACC1:acc#594" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(1)} -pin  "ACC1:acc#594" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(2)} -pin  "ACC1:acc#594" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(3)} -pin  "ACC1:acc#594" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(4)} -pin  "ACC1:acc#594" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load inst "ACC1:acc#612" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 53468 -attr oid 1524 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#595.itm(0)} -pin  "ACC1:acc#612" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(1)} -pin  "ACC1:acc#612" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(2)} -pin  "ACC1:acc#612" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(3)} -pin  "ACC1:acc#612" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(4)} -pin  "ACC1:acc#612" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#594.itm(0)} -pin  "ACC1:acc#612" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(1)} -pin  "ACC1:acc#612" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(2)} -pin  "ACC1:acc#612" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(3)} -pin  "ACC1:acc#612" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(4)} -pin  "ACC1:acc#612" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#612.itm(0)} -pin  "ACC1:acc#612" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(1)} -pin  "ACC1:acc#612" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(2)} -pin  "ACC1:acc#612" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(3)} -pin  "ACC1:acc#612" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(4)} -pin  "ACC1:acc#612" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(5)} -pin  "ACC1:acc#612" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load inst "ACC1:acc#626" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 53469 -attr oid 1525 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#613.itm(0)} -pin  "ACC1:acc#626" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(1)} -pin  "ACC1:acc#626" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(2)} -pin  "ACC1:acc#626" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(3)} -pin  "ACC1:acc#626" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(4)} -pin  "ACC1:acc#626" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(5)} -pin  "ACC1:acc#626" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#612.itm(0)} -pin  "ACC1:acc#626" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(1)} -pin  "ACC1:acc#626" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(2)} -pin  "ACC1:acc#626" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(3)} -pin  "ACC1:acc#626" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(4)} -pin  "ACC1:acc#626" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(5)} -pin  "ACC1:acc#626" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#626.itm(0)} -pin  "ACC1:acc#626" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(1)} -pin  "ACC1:acc#626" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(2)} -pin  "ACC1:acc#626" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(3)} -pin  "ACC1:acc#626" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(4)} -pin  "ACC1:acc#626" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(5)} -pin  "ACC1:acc#626" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(6)} -pin  "ACC1:acc#626" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load inst "ACC1:acc#638" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 53470 -attr oid 1526 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1-1:acc#25.psp.sva(1)} -pin  "ACC1:acc#638" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {PWR} -pin  "ACC1:acc#638" {A(1)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {PWR} -pin  "ACC1:acc#638" {A(2)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {GND} -pin  "ACC1:acc#638" {A(3)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {PWR} -pin  "ACC1:acc#638" {A(4)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {PWR} -pin  "ACC1:acc#638" {A(5)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {GND} -pin  "ACC1:acc#638" {A(6)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {PWR} -pin  "ACC1:acc#638" {A(7)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {ACC1:acc#626.itm(0)} -pin  "ACC1:acc#638" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(1)} -pin  "ACC1:acc#638" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(2)} -pin  "ACC1:acc#638" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(3)} -pin  "ACC1:acc#638" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(4)} -pin  "ACC1:acc#638" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(5)} -pin  "ACC1:acc#638" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(6)} -pin  "ACC1:acc#638" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#638.itm(0)} -pin  "ACC1:acc#638" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(1)} -pin  "ACC1:acc#638" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(2)} -pin  "ACC1:acc#638" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(3)} -pin  "ACC1:acc#638" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(4)} -pin  "ACC1:acc#638" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(5)} -pin  "ACC1:acc#638" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(6)} -pin  "ACC1:acc#638" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(7)} -pin  "ACC1:acc#638" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load inst "ACC1:acc#556" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53471 -attr oid 1527 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#502.cse(0)} -pin  "ACC1:acc#556" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#502.cse(1)} -pin  "ACC1:acc#556" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#502.cse(2)} -pin  "ACC1:acc#556" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#556" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#556" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#556" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#556.itm(0)} -pin  "ACC1:acc#556" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#556.itm(1)} -pin  "ACC1:acc#556" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#556.itm(2)} -pin  "ACC1:acc#556" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#556.itm(3)} -pin  "ACC1:acc#556" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load inst "ACC1:acc#555" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53472 -attr oid 1528 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#555" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#555" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#555" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#489.cse(0)} -pin  "ACC1:acc#555" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(1)} -pin  "ACC1:acc#555" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(2)} -pin  "ACC1:acc#555" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#555.itm(0)} -pin  "ACC1:acc#555" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#555.itm(1)} -pin  "ACC1:acc#555" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#555.itm(2)} -pin  "ACC1:acc#555" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#555.itm(3)} -pin  "ACC1:acc#555" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load inst "ACC1:acc#593" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53473 -attr oid 1529 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#556.itm(0)} -pin  "ACC1:acc#593" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#556.itm(1)} -pin  "ACC1:acc#593" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#556.itm(2)} -pin  "ACC1:acc#593" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#556.itm(3)} -pin  "ACC1:acc#593" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#555.itm(0)} -pin  "ACC1:acc#593" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#555.itm(1)} -pin  "ACC1:acc#593" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#555.itm(2)} -pin  "ACC1:acc#593" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#555.itm(3)} -pin  "ACC1:acc#593" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#593.itm(0)} -pin  "ACC1:acc#593" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(1)} -pin  "ACC1:acc#593" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(2)} -pin  "ACC1:acc#593" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(3)} -pin  "ACC1:acc#593" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(4)} -pin  "ACC1:acc#593" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load inst "ACC1:acc#488" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53474 -attr oid 1530 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#226.psp.sva(6)} -pin  "ACC1:acc#488" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#90.itm}
+load net {ACC1:acc#226.psp.sva(6)} -pin  "ACC1:acc#488" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#90.itm}
+load net {ACC1:acc#226.psp.sva(8)} -pin  "ACC1:acc#488" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#91.itm}
+load net {ACC1:acc#226.psp.sva(8)} -pin  "ACC1:acc#488" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#91.itm}
+load net {ACC1:acc#488.itm(0)} -pin  "ACC1:acc#488" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load net {ACC1:acc#488.itm(1)} -pin  "ACC1:acc#488" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load net {ACC1:acc#488.itm(2)} -pin  "ACC1:acc#488" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load inst "ACC1:acc#487" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53475 -attr oid 1531 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#226.psp.sva(10)} -pin  "ACC1:acc#487" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#92.itm}
+load net {ACC1:acc#226.psp.sva(10)} -pin  "ACC1:acc#487" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#92.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#487" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1056.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#487" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1056.itm}
+load net {ACC1:acc#487.itm(0)} -pin  "ACC1:acc#487" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load net {ACC1:acc#487.itm(1)} -pin  "ACC1:acc#487" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load net {ACC1:acc#487.itm(2)} -pin  "ACC1:acc#487" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load inst "ACC1:acc#554" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53476 -attr oid 1532 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#488.itm(0)} -pin  "ACC1:acc#554" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load net {ACC1:acc#488.itm(1)} -pin  "ACC1:acc#554" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load net {ACC1:acc#488.itm(2)} -pin  "ACC1:acc#554" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load net {ACC1:acc#487.itm(0)} -pin  "ACC1:acc#554" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load net {ACC1:acc#487.itm(1)} -pin  "ACC1:acc#554" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load net {ACC1:acc#487.itm(2)} -pin  "ACC1:acc#554" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load net {ACC1:acc#554.itm(0)} -pin  "ACC1:acc#554" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#554.itm(1)} -pin  "ACC1:acc#554" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#554.itm(2)} -pin  "ACC1:acc#554" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#554.itm(3)} -pin  "ACC1:acc#554" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load inst "ACC1:acc#592" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53477 -attr oid 1533 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#554.itm(0)} -pin  "ACC1:acc#592" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#554.itm(1)} -pin  "ACC1:acc#592" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#554.itm(2)} -pin  "ACC1:acc#592" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#554.itm(3)} -pin  "ACC1:acc#592" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#553.ncse(0)} -pin  "ACC1:acc#592" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(1)} -pin  "ACC1:acc#592" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(2)} -pin  "ACC1:acc#592" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(3)} -pin  "ACC1:acc#592" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#592.itm(0)} -pin  "ACC1:acc#592" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(1)} -pin  "ACC1:acc#592" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(2)} -pin  "ACC1:acc#592" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(3)} -pin  "ACC1:acc#592" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(4)} -pin  "ACC1:acc#592" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load inst "ACC1:acc#611" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 53478 -attr oid 1534 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#593.itm(0)} -pin  "ACC1:acc#611" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(1)} -pin  "ACC1:acc#611" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(2)} -pin  "ACC1:acc#611" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(3)} -pin  "ACC1:acc#611" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(4)} -pin  "ACC1:acc#611" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#592.itm(0)} -pin  "ACC1:acc#611" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(1)} -pin  "ACC1:acc#611" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(2)} -pin  "ACC1:acc#611" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(3)} -pin  "ACC1:acc#611" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(4)} -pin  "ACC1:acc#611" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#611.itm(0)} -pin  "ACC1:acc#611" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(1)} -pin  "ACC1:acc#611" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(2)} -pin  "ACC1:acc#611" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(3)} -pin  "ACC1:acc#611" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(4)} -pin  "ACC1:acc#611" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(5)} -pin  "ACC1:acc#611" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load inst "ACC1:acc#482" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53479 -attr oid 1535 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#482" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1057.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#482" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1057.itm}
+load net {ACC1:acc#226.psp.sva(4)} -pin  "ACC1:acc#482" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#963.itm}
+load net {ACC1:acc#226.psp.sva(4)} -pin  "ACC1:acc#482" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#963.itm}
+load net {ACC1:acc#482.itm(0)} -pin  "ACC1:acc#482" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load net {ACC1:acc#482.itm(1)} -pin  "ACC1:acc#482" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load net {ACC1:acc#482.itm(2)} -pin  "ACC1:acc#482" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load inst "ACC1:acc#551" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53480 -attr oid 1536 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#482.itm(0)} -pin  "ACC1:acc#551" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load net {ACC1:acc#482.itm(1)} -pin  "ACC1:acc#551" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load net {ACC1:acc#482.itm(2)} -pin  "ACC1:acc#551" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load net {ACC1:acc#489.cse(0)} -pin  "ACC1:acc#551" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(1)} -pin  "ACC1:acc#551" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(2)} -pin  "ACC1:acc#551" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#551.itm(0)} -pin  "ACC1:acc#551" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#551.itm(1)} -pin  "ACC1:acc#551" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#551.itm(2)} -pin  "ACC1:acc#551" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#551.itm(3)} -pin  "ACC1:acc#551" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load inst "ACC1:acc#591" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53481 -attr oid 1537 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#553.ncse(0)} -pin  "ACC1:acc#591" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(1)} -pin  "ACC1:acc#591" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(2)} -pin  "ACC1:acc#591" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(3)} -pin  "ACC1:acc#591" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#551.itm(0)} -pin  "ACC1:acc#591" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#551.itm(1)} -pin  "ACC1:acc#591" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#551.itm(2)} -pin  "ACC1:acc#591" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#551.itm(3)} -pin  "ACC1:acc#591" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#591.itm(0)} -pin  "ACC1:acc#591" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(1)} -pin  "ACC1:acc#591" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(2)} -pin  "ACC1:acc#591" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(3)} -pin  "ACC1:acc#591" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(4)} -pin  "ACC1:acc#591" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load inst "ACC1:acc#479" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53482 -attr oid 1538 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#479} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#479" {A(0)} -attr @path {/sobel/sobel:core/exs#97.itm}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1:acc#479" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#97.itm}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1:acc#479" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#97.itm}
+load net {ACC1-1:and#3.cse.sva} -pin  "ACC1:acc#479" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1552.itm}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#479" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1552.itm}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#479" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1552.itm}
+load net {ACC1:acc#479.itm(0)} -pin  "ACC1:acc#479" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#479.itm}
+load net {ACC1:acc#479.itm(1)} -pin  "ACC1:acc#479" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#479.itm}
+load net {ACC1:acc#479.itm(2)} -pin  "ACC1:acc#479" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#479.itm}
+load net {ACC1:acc#479.itm(3)} -pin  "ACC1:acc#479" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#479.itm}
+load inst "ACC1:acc#550" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53483 -attr oid 1539 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#550" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#550" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#550" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#479.itm(1)} -pin  "ACC1:acc#550" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#147.itm}
+load net {ACC1:acc#479.itm(2)} -pin  "ACC1:acc#550" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#147.itm}
+load net {ACC1:acc#479.itm(3)} -pin  "ACC1:acc#550" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#147.itm}
+load net {ACC1:acc#550.itm(0)} -pin  "ACC1:acc#550" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#550.itm(1)} -pin  "ACC1:acc#550" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#550.itm(2)} -pin  "ACC1:acc#550" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#550.itm(3)} -pin  "ACC1:acc#550" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load inst "ACC1:acc#478" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53484 -attr oid 1540 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#478} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#478" {A(0)} -attr @path {/sobel/sobel:core/exs#98.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#478" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#98.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#478" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#98.itm}
+load net {ACC1-1:nand#1.cse.sva} -pin  "ACC1:acc#478" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1554.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#478" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1554.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#478" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1554.itm}
+load net {ACC1:acc#478.itm(0)} -pin  "ACC1:acc#478" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#478.itm}
+load net {ACC1:acc#478.itm(1)} -pin  "ACC1:acc#478" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#478.itm}
+load net {ACC1:acc#478.itm(2)} -pin  "ACC1:acc#478" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#478.itm}
+load net {ACC1:acc#478.itm(3)} -pin  "ACC1:acc#478" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#478.itm}
+load inst "ACC1:acc#477" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53485 -attr oid 1541 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#477} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#477" {A(0)} -attr @path {/sobel/sobel:core/exs#77.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#477" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#77.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#477" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#77.itm}
+load net {ACC1:acc#338.itm(2)} -pin  "ACC1:acc#477" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1556.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#477" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1556.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#477" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1556.itm}
+load net {ACC1:acc#477.itm(0)} -pin  "ACC1:acc#477" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#477.itm}
+load net {ACC1:acc#477.itm(1)} -pin  "ACC1:acc#477" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#477.itm}
+load net {ACC1:acc#477.itm(2)} -pin  "ACC1:acc#477" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#477.itm}
+load net {ACC1:acc#477.itm(3)} -pin  "ACC1:acc#477" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#477.itm}
+load inst "ACC1:acc#549" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53486 -attr oid 1542 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#478.itm(1)} -pin  "ACC1:acc#549" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#146.itm}
+load net {ACC1:acc#478.itm(2)} -pin  "ACC1:acc#549" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#146.itm}
+load net {ACC1:acc#478.itm(3)} -pin  "ACC1:acc#549" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#146.itm}
+load net {ACC1:acc#477.itm(1)} -pin  "ACC1:acc#549" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#145.itm}
+load net {ACC1:acc#477.itm(2)} -pin  "ACC1:acc#549" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#145.itm}
+load net {ACC1:acc#477.itm(3)} -pin  "ACC1:acc#549" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#145.itm}
+load net {ACC1:acc#549.itm(0)} -pin  "ACC1:acc#549" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#549.itm(1)} -pin  "ACC1:acc#549" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#549.itm(2)} -pin  "ACC1:acc#549" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#549.itm(3)} -pin  "ACC1:acc#549" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load inst "ACC1:acc#590" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53487 -attr oid 1543 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#550.itm(0)} -pin  "ACC1:acc#590" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#550.itm(1)} -pin  "ACC1:acc#590" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#550.itm(2)} -pin  "ACC1:acc#590" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#550.itm(3)} -pin  "ACC1:acc#590" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#549.itm(0)} -pin  "ACC1:acc#590" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#549.itm(1)} -pin  "ACC1:acc#590" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#549.itm(2)} -pin  "ACC1:acc#590" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#549.itm(3)} -pin  "ACC1:acc#590" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#590.itm(0)} -pin  "ACC1:acc#590" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(1)} -pin  "ACC1:acc#590" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(2)} -pin  "ACC1:acc#590" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(3)} -pin  "ACC1:acc#590" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(4)} -pin  "ACC1:acc#590" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load inst "ACC1:acc#610" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 53488 -attr oid 1544 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#591.itm(0)} -pin  "ACC1:acc#610" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(1)} -pin  "ACC1:acc#610" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(2)} -pin  "ACC1:acc#610" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(3)} -pin  "ACC1:acc#610" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(4)} -pin  "ACC1:acc#610" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#590.itm(0)} -pin  "ACC1:acc#610" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(1)} -pin  "ACC1:acc#610" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(2)} -pin  "ACC1:acc#610" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(3)} -pin  "ACC1:acc#610" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(4)} -pin  "ACC1:acc#610" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#610.itm(0)} -pin  "ACC1:acc#610" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(1)} -pin  "ACC1:acc#610" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(2)} -pin  "ACC1:acc#610" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(3)} -pin  "ACC1:acc#610" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(4)} -pin  "ACC1:acc#610" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(5)} -pin  "ACC1:acc#610" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load inst "ACC1:acc#625" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 53489 -attr oid 1545 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#611.itm(0)} -pin  "ACC1:acc#625" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(1)} -pin  "ACC1:acc#625" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(2)} -pin  "ACC1:acc#625" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(3)} -pin  "ACC1:acc#625" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(4)} -pin  "ACC1:acc#625" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(5)} -pin  "ACC1:acc#625" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#610.itm(0)} -pin  "ACC1:acc#625" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(1)} -pin  "ACC1:acc#625" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(2)} -pin  "ACC1:acc#625" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(3)} -pin  "ACC1:acc#625" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(4)} -pin  "ACC1:acc#625" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(5)} -pin  "ACC1:acc#625" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#625.itm(0)} -pin  "ACC1:acc#625" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(1)} -pin  "ACC1:acc#625" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(2)} -pin  "ACC1:acc#625" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(3)} -pin  "ACC1:acc#625" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(4)} -pin  "ACC1:acc#625" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(5)} -pin  "ACC1:acc#625" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(6)} -pin  "ACC1:acc#625" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load inst "ACC1:acc#476" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53490 -attr oid 1546 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#476} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#476" {A(0)} -attr @path {/sobel/sobel:core/exs#78.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#476" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#78.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#476" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#78.itm}
+load net {ACC1:acc#210.psp#2.sva(3)} -pin  "ACC1:acc#476" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1558.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#476" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1558.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#476" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1558.itm}
+load net {ACC1:acc#476.itm(0)} -pin  "ACC1:acc#476" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#476.itm}
+load net {ACC1:acc#476.itm(1)} -pin  "ACC1:acc#476" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#476.itm}
+load net {ACC1:acc#476.itm(2)} -pin  "ACC1:acc#476" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#476.itm}
+load net {ACC1:acc#476.itm(3)} -pin  "ACC1:acc#476" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#476.itm}
+load inst "ACC1:acc#475" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53491 -attr oid 1547 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#475} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#475" {A(0)} -attr @path {/sobel/sobel:core/exs#79.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#475" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#79.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#475" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#79.itm}
+load net {ACC1:acc#210.psp#2.sva(2)} -pin  "ACC1:acc#475" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1560.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#475" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1560.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#475" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1560.itm}
+load net {ACC1:acc#475.itm(0)} -pin  "ACC1:acc#475" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#475.itm}
+load net {ACC1:acc#475.itm(1)} -pin  "ACC1:acc#475" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#475.itm}
+load net {ACC1:acc#475.itm(2)} -pin  "ACC1:acc#475" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#475.itm}
+load net {ACC1:acc#475.itm(3)} -pin  "ACC1:acc#475" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#475.itm}
+load inst "ACC1:acc#548" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53492 -attr oid 1548 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#476.itm(1)} -pin  "ACC1:acc#548" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#144.itm}
+load net {ACC1:acc#476.itm(2)} -pin  "ACC1:acc#548" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#144.itm}
+load net {ACC1:acc#476.itm(3)} -pin  "ACC1:acc#548" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#144.itm}
+load net {ACC1:acc#475.itm(1)} -pin  "ACC1:acc#548" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#143.itm}
+load net {ACC1:acc#475.itm(2)} -pin  "ACC1:acc#548" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#143.itm}
+load net {ACC1:acc#475.itm(3)} -pin  "ACC1:acc#548" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#143.itm}
+load net {ACC1:acc#548.itm(0)} -pin  "ACC1:acc#548" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#548.itm(1)} -pin  "ACC1:acc#548" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#548.itm(2)} -pin  "ACC1:acc#548" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#548.itm(3)} -pin  "ACC1:acc#548" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load inst "ACC1:acc#474" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53493 -attr oid 1549 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#474} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#474" {A(0)} -attr @path {/sobel/sobel:core/exs#80.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#474" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#80.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#474" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#80.itm}
+load net {ACC1:acc#210.psp#2.sva(1)} -pin  "ACC1:acc#474" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1562.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#474" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1562.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#474" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1562.itm}
+load net {ACC1:acc#474.itm(0)} -pin  "ACC1:acc#474" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#474.itm}
+load net {ACC1:acc#474.itm(1)} -pin  "ACC1:acc#474" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#474.itm}
+load net {ACC1:acc#474.itm(2)} -pin  "ACC1:acc#474" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#474.itm}
+load net {ACC1:acc#474.itm(3)} -pin  "ACC1:acc#474" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#474.itm}
+load inst "ACC1:acc#473" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53494 -attr oid 1550 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#473} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#473" {A(0)} -attr @path {/sobel/sobel:core/exs#99.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#473" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#99.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#473" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#99.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#473" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1564.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#473" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1564.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#473" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1564.itm}
+load net {ACC1:acc#473.itm(0)} -pin  "ACC1:acc#473" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#473.itm}
+load net {ACC1:acc#473.itm(1)} -pin  "ACC1:acc#473" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#473.itm}
+load net {ACC1:acc#473.itm(2)} -pin  "ACC1:acc#473" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#473.itm}
+load net {ACC1:acc#473.itm(3)} -pin  "ACC1:acc#473" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#473.itm}
+load inst "ACC1:acc#547" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53495 -attr oid 1551 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#474.itm(1)} -pin  "ACC1:acc#547" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#142.itm}
+load net {ACC1:acc#474.itm(2)} -pin  "ACC1:acc#547" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#142.itm}
+load net {ACC1:acc#474.itm(3)} -pin  "ACC1:acc#547" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#142.itm}
+load net {ACC1:acc#473.itm(1)} -pin  "ACC1:acc#547" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#141.itm}
+load net {ACC1:acc#473.itm(2)} -pin  "ACC1:acc#547" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#141.itm}
+load net {ACC1:acc#473.itm(3)} -pin  "ACC1:acc#547" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#141.itm}
+load net {ACC1:acc#547.itm(0)} -pin  "ACC1:acc#547" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#547.itm(1)} -pin  "ACC1:acc#547" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#547.itm(2)} -pin  "ACC1:acc#547" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#547.itm(3)} -pin  "ACC1:acc#547" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load inst "ACC1:acc#589" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53496 -attr oid 1552 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#548.itm(0)} -pin  "ACC1:acc#589" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#548.itm(1)} -pin  "ACC1:acc#589" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#548.itm(2)} -pin  "ACC1:acc#589" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#548.itm(3)} -pin  "ACC1:acc#589" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#547.itm(0)} -pin  "ACC1:acc#589" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#547.itm(1)} -pin  "ACC1:acc#589" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#547.itm(2)} -pin  "ACC1:acc#589" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#547.itm(3)} -pin  "ACC1:acc#589" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#589.itm(0)} -pin  "ACC1:acc#589" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(1)} -pin  "ACC1:acc#589" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(2)} -pin  "ACC1:acc#589" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(3)} -pin  "ACC1:acc#589" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(4)} -pin  "ACC1:acc#589" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load inst "ACC1:acc#472" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53497 -attr oid 1553 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#472} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#472" {A(0)} -attr @path {/sobel/sobel:core/exs#81.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#472" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#81.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#472" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#81.itm}
+load net {acc.psp#2.sva(3)} -pin  "ACC1:acc#472" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1566.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#472" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1566.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#472" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1566.itm}
+load net {ACC1:acc#472.itm(0)} -pin  "ACC1:acc#472" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#472.itm}
+load net {ACC1:acc#472.itm(1)} -pin  "ACC1:acc#472" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#472.itm}
+load net {ACC1:acc#472.itm(2)} -pin  "ACC1:acc#472" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#472.itm}
+load net {ACC1:acc#472.itm(3)} -pin  "ACC1:acc#472" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#472.itm}
+load inst "ACC1:acc#470" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53498 -attr oid 1554 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#470} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#470" {A(0)} -attr @path {/sobel/sobel:core/exs#82.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#470" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#82.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#470" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#82.itm}
+load net {acc.psp#2.sva(1)} -pin  "ACC1:acc#470" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1568.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#470" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1568.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#470" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1568.itm}
+load net {ACC1:acc#470.itm(0)} -pin  "ACC1:acc#470" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#470.itm}
+load net {ACC1:acc#470.itm(1)} -pin  "ACC1:acc#470" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#470.itm}
+load net {ACC1:acc#470.itm(2)} -pin  "ACC1:acc#470" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#470.itm}
+load net {ACC1:acc#470.itm(3)} -pin  "ACC1:acc#470" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#470.itm}
+load inst "ACC1:acc#546" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53499 -attr oid 1555 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#472.itm(1)} -pin  "ACC1:acc#546" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#140.itm}
+load net {ACC1:acc#472.itm(2)} -pin  "ACC1:acc#546" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#140.itm}
+load net {ACC1:acc#472.itm(3)} -pin  "ACC1:acc#546" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#140.itm}
+load net {ACC1:acc#470.itm(1)} -pin  "ACC1:acc#546" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#138.itm}
+load net {ACC1:acc#470.itm(2)} -pin  "ACC1:acc#546" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#138.itm}
+load net {ACC1:acc#470.itm(3)} -pin  "ACC1:acc#546" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#138.itm}
+load net {ACC1:acc#546.itm(0)} -pin  "ACC1:acc#546" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#546.itm(1)} -pin  "ACC1:acc#546" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#546.itm(2)} -pin  "ACC1:acc#546" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#546.itm(3)} -pin  "ACC1:acc#546" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load inst "ACC1-3:not#60" "not(1)" "INTERFACE" -attr xrf 53500 -attr oid 1556 -attr @path {/sobel/sobel:core/ACC1-3:not#60} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#406.itm(2)} -pin  "ACC1-3:not#60" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#2.itm}
+load net {ACC1-3:not#60.itm} -pin  "ACC1-3:not#60" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#60.itm}
+load inst "ACC1-3:and#3" "and(3,1)" "INTERFACE" -attr xrf 53501 -attr oid 1557 -attr @path {/sobel/sobel:core/ACC1-3:and#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1-3:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#23.itm}
+load net {ACC1-3:not#60.itm} -pin  "ACC1-3:and#3" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#60.itm}
+load net {ACC1:acc#406.itm(1)} -pin  "ACC1-3:and#3" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#1.itm}
+load net {ACC1-3:and#3.itm} -pin  "ACC1-3:and#3" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#3.itm}
+load inst "ACC1:acc#469" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53502 -attr oid 1558 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#469} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#469" {A(0)} -attr @path {/sobel/sobel:core/exs#83.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#469" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#83.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#469" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#83.itm}
+load net {ACC1-3:and#3.itm} -pin  "ACC1:acc#469" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1570.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#469" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1570.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#469" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1570.itm}
+load net {ACC1:acc#469.itm(0)} -pin  "ACC1:acc#469" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#469.itm}
+load net {ACC1:acc#469.itm(1)} -pin  "ACC1:acc#469" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#469.itm}
+load net {ACC1:acc#469.itm(2)} -pin  "ACC1:acc#469" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#469.itm}
+load net {ACC1:acc#469.itm(3)} -pin  "ACC1:acc#469" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#469.itm}
+load inst "ACC1-3:not#314" "not(1)" "INTERFACE" -attr xrf 53503 -attr oid 1559 -attr @path {/sobel/sobel:core/ACC1-3:not#314} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1-3:not#314" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#36.itm}
+load net {ACC1-3:not#314.itm} -pin  "ACC1-3:not#314" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#314.itm}
+load inst "ACC1-3:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 53504 -attr oid 1560 -attr @path {/sobel/sobel:core/ACC1-3:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#406.itm(2)} -pin  "ACC1-3:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva).itm}
+load net {ACC1-3:not#314.itm} -pin  "ACC1-3:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#314.itm}
+load net {ACC1-3:nand#1.itm} -pin  "ACC1-3:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand#1.itm}
+load inst "ACC1:acc#468" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53505 -attr oid 1561 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#468} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#468" {A(0)} -attr @path {/sobel/sobel:core/exs#100.itm}
+load net {ACC1:acc#224.psp#1.sva(6)} -pin  "ACC1:acc#468" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#100.itm}
+load net {ACC1:acc#224.psp#1.sva(6)} -pin  "ACC1:acc#468" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#100.itm}
+load net {ACC1-3:nand#1.itm} -pin  "ACC1:acc#468" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1572.itm}
+load net {ACC1:acc#224.psp#1.sva(8)} -pin  "ACC1:acc#468" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1572.itm}
+load net {ACC1:acc#224.psp#1.sva(8)} -pin  "ACC1:acc#468" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1572.itm}
+load net {ACC1:acc#468.itm(0)} -pin  "ACC1:acc#468" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#468.itm}
+load net {ACC1:acc#468.itm(1)} -pin  "ACC1:acc#468" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#468.itm}
+load net {ACC1:acc#468.itm(2)} -pin  "ACC1:acc#468" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#468.itm}
+load net {ACC1:acc#468.itm(3)} -pin  "ACC1:acc#468" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#468.itm}
+load inst "ACC1:acc#545" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53506 -attr oid 1562 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#469.itm(1)} -pin  "ACC1:acc#545" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#137.itm}
+load net {ACC1:acc#469.itm(2)} -pin  "ACC1:acc#545" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#137.itm}
+load net {ACC1:acc#469.itm(3)} -pin  "ACC1:acc#545" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#137.itm}
+load net {ACC1:acc#468.itm(1)} -pin  "ACC1:acc#545" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#136.itm}
+load net {ACC1:acc#468.itm(2)} -pin  "ACC1:acc#545" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#136.itm}
+load net {ACC1:acc#468.itm(3)} -pin  "ACC1:acc#545" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#136.itm}
+load net {ACC1:acc#545.itm(0)} -pin  "ACC1:acc#545" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#545.itm(1)} -pin  "ACC1:acc#545" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#545.itm(2)} -pin  "ACC1:acc#545" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#545.itm(3)} -pin  "ACC1:acc#545" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load inst "ACC1:acc#588" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53507 -attr oid 1563 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#546.itm(0)} -pin  "ACC1:acc#588" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#546.itm(1)} -pin  "ACC1:acc#588" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#546.itm(2)} -pin  "ACC1:acc#588" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#546.itm(3)} -pin  "ACC1:acc#588" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#545.itm(0)} -pin  "ACC1:acc#588" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#545.itm(1)} -pin  "ACC1:acc#588" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#545.itm(2)} -pin  "ACC1:acc#588" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#545.itm(3)} -pin  "ACC1:acc#588" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#588.itm(0)} -pin  "ACC1:acc#588" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(1)} -pin  "ACC1:acc#588" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(2)} -pin  "ACC1:acc#588" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(3)} -pin  "ACC1:acc#588" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(4)} -pin  "ACC1:acc#588" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load inst "ACC1:acc#609" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 53508 -attr oid 1564 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#589.itm(0)} -pin  "ACC1:acc#609" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(1)} -pin  "ACC1:acc#609" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(2)} -pin  "ACC1:acc#609" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(3)} -pin  "ACC1:acc#609" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(4)} -pin  "ACC1:acc#609" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#588.itm(0)} -pin  "ACC1:acc#609" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(1)} -pin  "ACC1:acc#609" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(2)} -pin  "ACC1:acc#609" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(3)} -pin  "ACC1:acc#609" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(4)} -pin  "ACC1:acc#609" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#609.itm(0)} -pin  "ACC1:acc#609" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(1)} -pin  "ACC1:acc#609" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(2)} -pin  "ACC1:acc#609" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(3)} -pin  "ACC1:acc#609" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(4)} -pin  "ACC1:acc#609" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(5)} -pin  "ACC1:acc#609" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load inst "ACC1-1:not#188" "not(1)" "INTERFACE" -attr xrf 53509 -attr oid 1565 -attr @path {/sobel/sobel:core/ACC1-1:not#188} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#368.itm(2)} -pin  "ACC1-1:not#188" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#44.sva)#2.itm}
+load net {ACC1-1:not#188.itm} -pin  "ACC1-1:not#188" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#188.itm}
+load inst "ACC1-1:and#11" "and(3,1)" "INTERFACE" -attr xrf 53510 -attr oid 1566 -attr @path {/sobel/sobel:core/ACC1-1:and#11} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1-1:and#11" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#22.itm}
+load net {ACC1-1:not#188.itm} -pin  "ACC1-1:and#11" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#188.itm}
+load net {ACC1:acc#368.itm(1)} -pin  "ACC1-1:and#11" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#44.sva)#1.itm}
+load net {ACC1-1:and#11.itm} -pin  "ACC1-1:and#11" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#11.itm}
+load inst "ACC1:acc#467" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53511 -attr oid 1567 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#467} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#467" {A(0)} -attr @path {/sobel/sobel:core/exs#101.itm}
+load net {ACC1:acc#224.psp#1.sva(10)} -pin  "ACC1:acc#467" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#101.itm}
+load net {ACC1:acc#224.psp#1.sva(10)} -pin  "ACC1:acc#467" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#101.itm}
+load net {ACC1-1:and#11.itm} -pin  "ACC1:acc#467" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1574.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#467" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1574.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#467" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1574.itm}
+load net {ACC1:acc#467.itm(0)} -pin  "ACC1:acc#467" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#467.itm}
+load net {ACC1:acc#467.itm(1)} -pin  "ACC1:acc#467" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#467.itm}
+load net {ACC1:acc#467.itm(2)} -pin  "ACC1:acc#467" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#467.itm}
+load net {ACC1:acc#467.itm(3)} -pin  "ACC1:acc#467" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#467.itm}
+load inst "ACC1-1:not#317" "not(1)" "INTERFACE" -attr xrf 53512 -attr oid 1568 -attr @path {/sobel/sobel:core/ACC1-1:not#317} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1-1:not#317" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#41.itm}
+load net {ACC1-1:not#317.itm} -pin  "ACC1-1:not#317" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#317.itm}
+load inst "ACC1-1:nand#5" "nand(2,1)" "INTERFACE" -attr xrf 53513 -attr oid 1569 -attr @path {/sobel/sobel:core/ACC1-1:nand#5} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#368.itm(2)} -pin  "ACC1-1:nand#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#44.sva).itm}
+load net {ACC1-1:not#317.itm} -pin  "ACC1-1:nand#5" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#317.itm}
+load net {ACC1-1:nand#5.itm} -pin  "ACC1-1:nand#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:nand#5.itm}
+load inst "ACC1:acc#466" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53514 -attr oid 1570 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#466} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#466" {A(0)} -attr @path {/sobel/sobel:core/exs#84.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#466" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#84.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#466" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#84.itm}
+load net {ACC1-1:nand#5.itm} -pin  "ACC1:acc#466" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1576.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#466" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1576.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#466" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1576.itm}
+load net {ACC1:acc#466.itm(0)} -pin  "ACC1:acc#466" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#466.itm}
+load net {ACC1:acc#466.itm(1)} -pin  "ACC1:acc#466" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#466.itm}
+load net {ACC1:acc#466.itm(2)} -pin  "ACC1:acc#466" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#466.itm}
+load net {ACC1:acc#466.itm(3)} -pin  "ACC1:acc#466" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#466.itm}
+load inst "ACC1:acc#544" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53515 -attr oid 1571 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#467.itm(1)} -pin  "ACC1:acc#544" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#135.itm}
+load net {ACC1:acc#467.itm(2)} -pin  "ACC1:acc#544" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#135.itm}
+load net {ACC1:acc#467.itm(3)} -pin  "ACC1:acc#544" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#135.itm}
+load net {ACC1:acc#466.itm(1)} -pin  "ACC1:acc#544" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#134.itm}
+load net {ACC1:acc#466.itm(2)} -pin  "ACC1:acc#544" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#134.itm}
+load net {ACC1:acc#466.itm(3)} -pin  "ACC1:acc#544" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#134.itm}
+load net {ACC1:acc#544.itm(0)} -pin  "ACC1:acc#544" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#544.itm(1)} -pin  "ACC1:acc#544" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#544.itm(2)} -pin  "ACC1:acc#544" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#544.itm(3)} -pin  "ACC1:acc#544" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load inst "ACC1:acc#465" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53516 -attr oid 1572 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#465} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#465" {A(0)} -attr @path {/sobel/sobel:core/exs#85.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#465" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#85.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#465" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#85.itm}
+load net {ACC1:acc#367.itm(2)} -pin  "ACC1:acc#465" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1578.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#465" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1578.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#465" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1578.itm}
+load net {ACC1:acc#465.itm(0)} -pin  "ACC1:acc#465" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#465.itm}
+load net {ACC1:acc#465.itm(1)} -pin  "ACC1:acc#465" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#465.itm}
+load net {ACC1:acc#465.itm(2)} -pin  "ACC1:acc#465" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#465.itm}
+load net {ACC1:acc#465.itm(3)} -pin  "ACC1:acc#465" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#465.itm}
+load inst "ACC1:acc#464" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53517 -attr oid 1573 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#464} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#464" {A(0)} -attr @path {/sobel/sobel:core/exs#86.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#464" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#86.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#464" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#86.itm}
+load net {ACC1-1:acc#208.psp.sva(3)} -pin  "ACC1:acc#464" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1580.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#464" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1580.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#464" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1580.itm}
+load net {ACC1:acc#464.itm(0)} -pin  "ACC1:acc#464" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#464.itm}
+load net {ACC1:acc#464.itm(1)} -pin  "ACC1:acc#464" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#464.itm}
+load net {ACC1:acc#464.itm(2)} -pin  "ACC1:acc#464" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#464.itm}
+load net {ACC1:acc#464.itm(3)} -pin  "ACC1:acc#464" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#464.itm}
+load inst "ACC1:acc#543" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53518 -attr oid 1574 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#465.itm(1)} -pin  "ACC1:acc#543" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#133.itm}
+load net {ACC1:acc#465.itm(2)} -pin  "ACC1:acc#543" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#133.itm}
+load net {ACC1:acc#465.itm(3)} -pin  "ACC1:acc#543" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#133.itm}
+load net {ACC1:acc#464.itm(1)} -pin  "ACC1:acc#543" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#132.itm}
+load net {ACC1:acc#464.itm(2)} -pin  "ACC1:acc#543" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#132.itm}
+load net {ACC1:acc#464.itm(3)} -pin  "ACC1:acc#543" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#132.itm}
+load net {ACC1:acc#543.itm(0)} -pin  "ACC1:acc#543" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#543.itm(1)} -pin  "ACC1:acc#543" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#543.itm(2)} -pin  "ACC1:acc#543" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#543.itm(3)} -pin  "ACC1:acc#543" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load inst "ACC1:acc#587" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53519 -attr oid 1575 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#544.itm(0)} -pin  "ACC1:acc#587" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#544.itm(1)} -pin  "ACC1:acc#587" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#544.itm(2)} -pin  "ACC1:acc#587" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#544.itm(3)} -pin  "ACC1:acc#587" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#543.itm(0)} -pin  "ACC1:acc#587" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#543.itm(1)} -pin  "ACC1:acc#587" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#543.itm(2)} -pin  "ACC1:acc#587" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#543.itm(3)} -pin  "ACC1:acc#587" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#587.itm(0)} -pin  "ACC1:acc#587" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(1)} -pin  "ACC1:acc#587" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(2)} -pin  "ACC1:acc#587" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(3)} -pin  "ACC1:acc#587" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(4)} -pin  "ACC1:acc#587" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load inst "ACC1:acc#463" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53520 -attr oid 1576 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#463} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#463" {A(0)} -attr @path {/sobel/sobel:core/exs#87.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#463" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#87.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#463" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#87.itm}
+load net {ACC1-1:acc#208.psp.sva(2)} -pin  "ACC1:acc#463" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1582.itm}
+load net {ACC1:acc#224.psp#1.sva(4)} -pin  "ACC1:acc#463" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1582.itm}
+load net {ACC1:acc#224.psp#1.sva(4)} -pin  "ACC1:acc#463" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1582.itm}
+load net {ACC1:acc#463.itm(0)} -pin  "ACC1:acc#463" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#463.itm}
+load net {ACC1:acc#463.itm(1)} -pin  "ACC1:acc#463" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#463.itm}
+load net {ACC1:acc#463.itm(2)} -pin  "ACC1:acc#463" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#463.itm}
+load net {ACC1:acc#463.itm(3)} -pin  "ACC1:acc#463" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#463.itm}
+load inst "ACC1:acc#462" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53521 -attr oid 1577 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#462} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#462" {A(0)} -attr @path {/sobel/sobel:core/exs#88.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#462" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#88.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#462" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#88.itm}
+load net {ACC1-1:acc#208.psp.sva(1)} -pin  "ACC1:acc#462" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1584.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#462" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1584.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#462" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1584.itm}
+load net {ACC1:acc#462.itm(0)} -pin  "ACC1:acc#462" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#462.itm}
+load net {ACC1:acc#462.itm(1)} -pin  "ACC1:acc#462" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#462.itm}
+load net {ACC1:acc#462.itm(2)} -pin  "ACC1:acc#462" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#462.itm}
+load net {ACC1:acc#462.itm(3)} -pin  "ACC1:acc#462" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#462.itm}
+load inst "ACC1:acc#542" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53522 -attr oid 1578 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#463.itm(1)} -pin  "ACC1:acc#542" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#131.itm}
+load net {ACC1:acc#463.itm(2)} -pin  "ACC1:acc#542" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#131.itm}
+load net {ACC1:acc#463.itm(3)} -pin  "ACC1:acc#542" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#131.itm}
+load net {ACC1:acc#462.itm(1)} -pin  "ACC1:acc#542" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#130.itm}
+load net {ACC1:acc#462.itm(2)} -pin  "ACC1:acc#542" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#130.itm}
+load net {ACC1:acc#462.itm(3)} -pin  "ACC1:acc#542" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#130.itm}
+load net {ACC1:acc#542.itm(0)} -pin  "ACC1:acc#542" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#542.itm(1)} -pin  "ACC1:acc#542" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#542.itm(2)} -pin  "ACC1:acc#542" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#542.itm(3)} -pin  "ACC1:acc#542" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load inst "ACC1-1:not#91" "not(1)" "INTERFACE" -attr xrf 53523 -attr oid 1579 -attr @path {/sobel/sobel:core/ACC1-1:not#91} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1-1:not#91" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#26.itm}
+load net {ACC1-1:not#91.itm} -pin  "ACC1-1:not#91" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#91.itm}
+load inst "ACC1-1:nand#2" "nand(2,1)" "INTERFACE" -attr xrf 53524 -attr oid 1580 -attr @path {/sobel/sobel:core/ACC1-1:nand#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#349.itm(2)} -pin  "ACC1-1:nand#2" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#36.sva)#2.itm}
+load net {ACC1-1:not#91.itm} -pin  "ACC1-1:nand#2" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#91.itm}
+load net {ACC1-1:nand#2.itm} -pin  "ACC1-1:nand#2" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:nand#2.itm}
+load inst "ACC1:acc#460" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53525 -attr oid 1581 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#460} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#460" {A(0)} -attr @path {/sobel/sobel:core/exs#89.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#460" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#89.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#460" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#89.itm}
+load net {ACC1-1:nand#2.itm} -pin  "ACC1:acc#460" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1586.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#460" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1586.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#460" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1586.itm}
+load net {ACC1:acc#460.itm(0)} -pin  "ACC1:acc#460" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#460.itm}
+load net {ACC1:acc#460.itm(1)} -pin  "ACC1:acc#460" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#460.itm}
+load net {ACC1:acc#460.itm(2)} -pin  "ACC1:acc#460" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#460.itm}
+load net {ACC1:acc#460.itm(3)} -pin  "ACC1:acc#460" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#460.itm}
+load inst "ACC1:acc#459" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53526 -attr oid 1582 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#459} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#459" {A(0)} -attr @path {/sobel/sobel:core/exs#102.itm}
+load net {ACC1-1:acc#25.psp.sva(7)} -pin  "ACC1:acc#459" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#102.itm}
+load net {ACC1-1:acc#25.psp.sva(7)} -pin  "ACC1:acc#459" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#102.itm}
+load net {ACC1:acc#348.itm(2)} -pin  "ACC1:acc#459" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1588.itm}
+load net {ACC1-1:acc#25.psp.sva(9)} -pin  "ACC1:acc#459" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1588.itm}
+load net {ACC1-1:acc#25.psp.sva(9)} -pin  "ACC1:acc#459" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1588.itm}
+load net {ACC1:acc#459.itm(0)} -pin  "ACC1:acc#459" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#459.itm}
+load net {ACC1:acc#459.itm(1)} -pin  "ACC1:acc#459" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#459.itm}
+load net {ACC1:acc#459.itm(2)} -pin  "ACC1:acc#459" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#459.itm}
+load net {ACC1:acc#459.itm(3)} -pin  "ACC1:acc#459" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#459.itm}
+load inst "ACC1:acc#541" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53527 -attr oid 1583 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#460.itm(1)} -pin  "ACC1:acc#541" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#128.itm}
+load net {ACC1:acc#460.itm(2)} -pin  "ACC1:acc#541" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#128.itm}
+load net {ACC1:acc#460.itm(3)} -pin  "ACC1:acc#541" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#128.itm}
+load net {ACC1:acc#459.itm(1)} -pin  "ACC1:acc#541" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#127.itm}
+load net {ACC1:acc#459.itm(2)} -pin  "ACC1:acc#541" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#127.itm}
+load net {ACC1:acc#459.itm(3)} -pin  "ACC1:acc#541" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#127.itm}
+load net {ACC1:acc#541.itm(0)} -pin  "ACC1:acc#541" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#541.itm(1)} -pin  "ACC1:acc#541" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#541.itm(2)} -pin  "ACC1:acc#541" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#541.itm(3)} -pin  "ACC1:acc#541" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load inst "ACC1:acc#586" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53528 -attr oid 1584 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#542.itm(0)} -pin  "ACC1:acc#586" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#542.itm(1)} -pin  "ACC1:acc#586" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#542.itm(2)} -pin  "ACC1:acc#586" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#542.itm(3)} -pin  "ACC1:acc#586" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#541.itm(0)} -pin  "ACC1:acc#586" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#541.itm(1)} -pin  "ACC1:acc#586" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#541.itm(2)} -pin  "ACC1:acc#586" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#541.itm(3)} -pin  "ACC1:acc#586" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#586.itm(0)} -pin  "ACC1:acc#586" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(1)} -pin  "ACC1:acc#586" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(2)} -pin  "ACC1:acc#586" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(3)} -pin  "ACC1:acc#586" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(4)} -pin  "ACC1:acc#586" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load inst "ACC1:acc#608" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 53529 -attr oid 1585 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#587.itm(0)} -pin  "ACC1:acc#608" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(1)} -pin  "ACC1:acc#608" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(2)} -pin  "ACC1:acc#608" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(3)} -pin  "ACC1:acc#608" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(4)} -pin  "ACC1:acc#608" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#586.itm(0)} -pin  "ACC1:acc#608" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(1)} -pin  "ACC1:acc#608" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(2)} -pin  "ACC1:acc#608" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(3)} -pin  "ACC1:acc#608" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(4)} -pin  "ACC1:acc#608" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#608.itm(0)} -pin  "ACC1:acc#608" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(1)} -pin  "ACC1:acc#608" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(2)} -pin  "ACC1:acc#608" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(3)} -pin  "ACC1:acc#608" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(4)} -pin  "ACC1:acc#608" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(5)} -pin  "ACC1:acc#608" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load inst "ACC1:acc#624" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 53530 -attr oid 1586 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#609.itm(0)} -pin  "ACC1:acc#624" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(1)} -pin  "ACC1:acc#624" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(2)} -pin  "ACC1:acc#624" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(3)} -pin  "ACC1:acc#624" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(4)} -pin  "ACC1:acc#624" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(5)} -pin  "ACC1:acc#624" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#608.itm(0)} -pin  "ACC1:acc#624" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(1)} -pin  "ACC1:acc#624" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(2)} -pin  "ACC1:acc#624" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(3)} -pin  "ACC1:acc#624" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(4)} -pin  "ACC1:acc#624" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(5)} -pin  "ACC1:acc#624" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#624.itm(0)} -pin  "ACC1:acc#624" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(1)} -pin  "ACC1:acc#624" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(2)} -pin  "ACC1:acc#624" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(3)} -pin  "ACC1:acc#624" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(4)} -pin  "ACC1:acc#624" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(5)} -pin  "ACC1:acc#624" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(6)} -pin  "ACC1:acc#624" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load inst "ACC1:acc#637" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 53531 -attr oid 1587 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#625.itm(0)} -pin  "ACC1:acc#637" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(1)} -pin  "ACC1:acc#637" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(2)} -pin  "ACC1:acc#637" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(3)} -pin  "ACC1:acc#637" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(4)} -pin  "ACC1:acc#637" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(5)} -pin  "ACC1:acc#637" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(6)} -pin  "ACC1:acc#637" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#624.itm(0)} -pin  "ACC1:acc#637" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(1)} -pin  "ACC1:acc#637" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(2)} -pin  "ACC1:acc#637" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(3)} -pin  "ACC1:acc#637" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(4)} -pin  "ACC1:acc#637" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(5)} -pin  "ACC1:acc#637" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(6)} -pin  "ACC1:acc#637" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#637.itm(0)} -pin  "ACC1:acc#637" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(1)} -pin  "ACC1:acc#637" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(2)} -pin  "ACC1:acc#637" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(3)} -pin  "ACC1:acc#637" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(4)} -pin  "ACC1:acc#637" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(5)} -pin  "ACC1:acc#637" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(6)} -pin  "ACC1:acc#637" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(7)} -pin  "ACC1:acc#637" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load inst "ACC1:acc#645" "add(8,1,8,0,9)" "INTERFACE" -attr xrf 53532 -attr oid 1588 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#638.itm(0)} -pin  "ACC1:acc#645" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(1)} -pin  "ACC1:acc#645" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(2)} -pin  "ACC1:acc#645" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(3)} -pin  "ACC1:acc#645" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(4)} -pin  "ACC1:acc#645" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(5)} -pin  "ACC1:acc#645" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(6)} -pin  "ACC1:acc#645" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(7)} -pin  "ACC1:acc#645" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#637.itm(0)} -pin  "ACC1:acc#645" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(1)} -pin  "ACC1:acc#645" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(2)} -pin  "ACC1:acc#645" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(3)} -pin  "ACC1:acc#645" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(4)} -pin  "ACC1:acc#645" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(5)} -pin  "ACC1:acc#645" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(6)} -pin  "ACC1:acc#645" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(7)} -pin  "ACC1:acc#645" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#645.itm(0)} -pin  "ACC1:acc#645" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(1)} -pin  "ACC1:acc#645" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(2)} -pin  "ACC1:acc#645" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(3)} -pin  "ACC1:acc#645" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(4)} -pin  "ACC1:acc#645" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(5)} -pin  "ACC1:acc#645" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(6)} -pin  "ACC1:acc#645" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(7)} -pin  "ACC1:acc#645" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(8)} -pin  "ACC1:acc#645" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load inst "ACC1:acc#650" "add(10,0,9,1,11)" "INTERFACE" -attr xrf 53533 -attr oid 1589 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,12)"
+load net {ACC1:acc#228.psp.sva(3)} -pin  "ACC1:acc#650" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1:acc#650" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {GND} -pin  "ACC1:acc#650" {A(2)} -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1:acc#650" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {GND} -pin  "ACC1:acc#650" {A(4)} -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1:acc#650" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {GND} -pin  "ACC1:acc#650" {A(6)} -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1:acc#650" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {GND} -pin  "ACC1:acc#650" {A(8)} -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1:acc#650" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {ACC1:acc#645.itm(0)} -pin  "ACC1:acc#650" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(1)} -pin  "ACC1:acc#650" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(2)} -pin  "ACC1:acc#650" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(3)} -pin  "ACC1:acc#650" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(4)} -pin  "ACC1:acc#650" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(5)} -pin  "ACC1:acc#650" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(6)} -pin  "ACC1:acc#650" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(7)} -pin  "ACC1:acc#650" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(8)} -pin  "ACC1:acc#650" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#650.itm(0)} -pin  "ACC1:acc#650" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(1)} -pin  "ACC1:acc#650" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(2)} -pin  "ACC1:acc#650" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(3)} -pin  "ACC1:acc#650" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(4)} -pin  "ACC1:acc#650" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(5)} -pin  "ACC1:acc#650" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(6)} -pin  "ACC1:acc#650" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(7)} -pin  "ACC1:acc#650" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(8)} -pin  "ACC1:acc#650" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(9)} -pin  "ACC1:acc#650" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(10)} -pin  "ACC1:acc#650" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load inst "ACC1:acc#517" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53534 -attr oid 1590 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#228.psp.sva(10)} -pin  "ACC1:acc#517" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#20.itm}
+load net {ACC1:acc#228.psp.sva(10)} -pin  "ACC1:acc#517" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#20.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#517" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1049.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#517" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1049.itm}
+load net {ACC1:acc#517.itm(0)} -pin  "ACC1:acc#517" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load net {ACC1:acc#517.itm(1)} -pin  "ACC1:acc#517" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load net {ACC1:acc#517.itm(2)} -pin  "ACC1:acc#517" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load inst "ACC1:acc#568" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53535 -attr oid 1591 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#517.itm(0)} -pin  "ACC1:acc#568" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load net {ACC1:acc#517.itm(1)} -pin  "ACC1:acc#568" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load net {ACC1:acc#517.itm(2)} -pin  "ACC1:acc#568" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load net {ACC1:acc#516.cse(0)} -pin  "ACC1:acc#568" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(1)} -pin  "ACC1:acc#568" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(2)} -pin  "ACC1:acc#568" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#568.itm(0)} -pin  "ACC1:acc#568" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#568.itm(1)} -pin  "ACC1:acc#568" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#568.itm(2)} -pin  "ACC1:acc#568" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#568.itm(3)} -pin  "ACC1:acc#568" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load inst "ACC1:acc#567" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53536 -attr oid 1592 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#516.cse(0)} -pin  "ACC1:acc#567" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(1)} -pin  "ACC1:acc#567" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(2)} -pin  "ACC1:acc#567" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(0)} -pin  "ACC1:acc#567" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(1)} -pin  "ACC1:acc#567" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(2)} -pin  "ACC1:acc#567" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#567.itm(0)} -pin  "ACC1:acc#567" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#567.itm(1)} -pin  "ACC1:acc#567" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#567.itm(2)} -pin  "ACC1:acc#567" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#567.itm(3)} -pin  "ACC1:acc#567" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load inst "ACC1:acc#599" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53537 -attr oid 1593 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#568.itm(0)} -pin  "ACC1:acc#599" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#568.itm(1)} -pin  "ACC1:acc#599" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#568.itm(2)} -pin  "ACC1:acc#599" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#568.itm(3)} -pin  "ACC1:acc#599" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#567.itm(0)} -pin  "ACC1:acc#599" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#567.itm(1)} -pin  "ACC1:acc#599" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#567.itm(2)} -pin  "ACC1:acc#599" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#567.itm(3)} -pin  "ACC1:acc#599" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#599.itm(0)} -pin  "ACC1:acc#599" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(1)} -pin  "ACC1:acc#599" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(2)} -pin  "ACC1:acc#599" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(3)} -pin  "ACC1:acc#599" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(4)} -pin  "ACC1:acc#599" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load inst "ACC1:acc#513" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53538 -attr oid 1594 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#513" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1050.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#513" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1050.itm}
+load net {ACC1:acc#228.psp.sva(4)} -pin  "ACC1:acc#513" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1031.itm}
+load net {ACC1:acc#228.psp.sva(4)} -pin  "ACC1:acc#513" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1031.itm}
+load net {ACC1:acc#513.itm(0)} -pin  "ACC1:acc#513" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load net {ACC1:acc#513.itm(1)} -pin  "ACC1:acc#513" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load net {ACC1:acc#513.itm(2)} -pin  "ACC1:acc#513" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load inst "ACC1:acc#566" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53539 -attr oid 1595 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#513.itm(0)} -pin  "ACC1:acc#566" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load net {ACC1:acc#513.itm(1)} -pin  "ACC1:acc#566" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load net {ACC1:acc#513.itm(2)} -pin  "ACC1:acc#566" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load net {ACC1:acc#516.cse(0)} -pin  "ACC1:acc#566" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(1)} -pin  "ACC1:acc#566" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(2)} -pin  "ACC1:acc#566" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#566.itm(0)} -pin  "ACC1:acc#566" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#566.itm(1)} -pin  "ACC1:acc#566" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#566.itm(2)} -pin  "ACC1:acc#566" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#566.itm(3)} -pin  "ACC1:acc#566" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load inst "ACC1:acc#510" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53540 -attr oid 1596 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#510" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1060.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#510" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1060.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#510" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1049.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#510" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1049.itm}
+load net {ACC1:acc#510.itm(0)} -pin  "ACC1:acc#510" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load net {ACC1:acc#510.itm(1)} -pin  "ACC1:acc#510" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load net {ACC1:acc#510.itm(2)} -pin  "ACC1:acc#510" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load inst "ACC1:acc#565" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53541 -attr oid 1597 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#509.cse(0)} -pin  "ACC1:acc#565" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(1)} -pin  "ACC1:acc#565" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(2)} -pin  "ACC1:acc#565" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#510.itm(0)} -pin  "ACC1:acc#565" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load net {ACC1:acc#510.itm(1)} -pin  "ACC1:acc#565" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load net {ACC1:acc#510.itm(2)} -pin  "ACC1:acc#565" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load net {ACC1:acc#565.itm(0)} -pin  "ACC1:acc#565" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#565.itm(1)} -pin  "ACC1:acc#565" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#565.itm(2)} -pin  "ACC1:acc#565" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#565.itm(3)} -pin  "ACC1:acc#565" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load inst "ACC1:acc#598" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53542 -attr oid 1598 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#566.itm(0)} -pin  "ACC1:acc#598" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#566.itm(1)} -pin  "ACC1:acc#598" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#566.itm(2)} -pin  "ACC1:acc#598" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#566.itm(3)} -pin  "ACC1:acc#598" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#565.itm(0)} -pin  "ACC1:acc#598" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#565.itm(1)} -pin  "ACC1:acc#598" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#565.itm(2)} -pin  "ACC1:acc#598" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#565.itm(3)} -pin  "ACC1:acc#598" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#598.itm(0)} -pin  "ACC1:acc#598" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(1)} -pin  "ACC1:acc#598" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(2)} -pin  "ACC1:acc#598" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(3)} -pin  "ACC1:acc#598" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(4)} -pin  "ACC1:acc#598" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load inst "ACC1:acc#614" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 53543 -attr oid 1599 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#599.itm(0)} -pin  "ACC1:acc#614" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(1)} -pin  "ACC1:acc#614" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(2)} -pin  "ACC1:acc#614" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(3)} -pin  "ACC1:acc#614" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(4)} -pin  "ACC1:acc#614" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#598.itm(0)} -pin  "ACC1:acc#614" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(1)} -pin  "ACC1:acc#614" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(2)} -pin  "ACC1:acc#614" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(3)} -pin  "ACC1:acc#614" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(4)} -pin  "ACC1:acc#614" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#614.itm(0)} -pin  "ACC1:acc#614" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(1)} -pin  "ACC1:acc#614" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(2)} -pin  "ACC1:acc#614" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(3)} -pin  "ACC1:acc#614" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(4)} -pin  "ACC1:acc#614" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(5)} -pin  "ACC1:acc#614" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load inst "ACC1:acc#627" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 53544 -attr oid 1600 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#627" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#627" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {GND} -pin  "ACC1:acc#627" {A(2)} -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {ACC1:acc#224.psp.sva(6)} -pin  "ACC1:acc#627" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {GND} -pin  "ACC1:acc#627" {A(4)} -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {ACC1:acc#227.psp.sva(7)} -pin  "ACC1:acc#627" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1:acc#627" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {ACC1:acc#614.itm(0)} -pin  "ACC1:acc#627" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(1)} -pin  "ACC1:acc#627" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(2)} -pin  "ACC1:acc#627" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(3)} -pin  "ACC1:acc#627" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(4)} -pin  "ACC1:acc#627" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(5)} -pin  "ACC1:acc#627" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#627.itm(0)} -pin  "ACC1:acc#627" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(1)} -pin  "ACC1:acc#627" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(2)} -pin  "ACC1:acc#627" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(3)} -pin  "ACC1:acc#627" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(4)} -pin  "ACC1:acc#627" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(5)} -pin  "ACC1:acc#627" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(6)} -pin  "ACC1:acc#627" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(7)} -pin  "ACC1:acc#627" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load inst "ACC1:not#368" "not(1)" "INTERFACE" -attr xrf 53545 -attr oid 1601 -attr @path {/sobel/sobel:core/ACC1:not#368} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#412.itm(4)} -pin  "ACC1:not#368" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#214.psp#1.sva)#6.itm}
+load net {ACC1:not#368.itm} -pin  "ACC1:not#368" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#368.itm}
+load inst "ACC1:not#369" "not(1)" "INTERFACE" -attr xrf 53546 -attr oid 1602 -attr @path {/sobel/sobel:core/ACC1:not#369} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#423.itm(3)} -pin  "ACC1:not#369" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva).itm}
+load net {ACC1:not#369.itm} -pin  "ACC1:not#369" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#369.itm}
+load inst "ACC1:not#370" "not(1)" "INTERFACE" -attr xrf 53547 -attr oid 1603 -attr @path {/sobel/sobel:core/ACC1:not#370} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#338.itm(3)} -pin  "ACC1:not#370" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#26.sva)#1.itm}
+load net {ACC1:not#370.itm} -pin  "ACC1:not#370" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#370.itm}
+load inst "ACC1:not#371" "not(1)" "INTERFACE" -attr xrf 53548 -attr oid 1604 -attr @path {/sobel/sobel:core/ACC1:not#371} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#375.itm(4)} -pin  "ACC1:not#371" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-2:acc#212.psp.sva)#8.itm}
+load net {ACC1:not#371.itm} -pin  "ACC1:not#371" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#371.itm}
+load inst "ACC1:not#390" "not(1)" "INTERFACE" -attr xrf 53549 -attr oid 1605 -attr @path {/sobel/sobel:core/ACC1:not#390} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#395.itm(3)} -pin  "ACC1:not#390" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#4.itm}
+load net {ACC1:not#390.itm} -pin  "ACC1:not#390" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#390.itm}
+load inst "ACC1:acc#523" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53550 -attr oid 1606 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:not#370.itm} -pin  "ACC1:acc#523" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1098.itm}
+load net {ACC1:not#369.itm} -pin  "ACC1:acc#523" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1098.itm}
+load net {ACC1:not#368.itm} -pin  "ACC1:acc#523" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1098.itm}
+load net {ACC1:not#390.itm} -pin  "ACC1:acc#523" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#983.itm}
+load net {PWR} -pin  "ACC1:acc#523" {B(1)} -attr @path {/sobel/sobel:core/conc#983.itm}
+load net {ACC1:not#371.itm} -pin  "ACC1:acc#523" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#983.itm}
+load net {ACC1:acc#523.itm(0)} -pin  "ACC1:acc#523" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#523.itm(1)} -pin  "ACC1:acc#523" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#523.itm(2)} -pin  "ACC1:acc#523" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#523.itm(3)} -pin  "ACC1:acc#523" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load inst "ACC1:not#373" "not(1)" "INTERFACE" -attr xrf 53551 -attr oid 1607 -attr @path {/sobel/sobel:core/ACC1:not#373} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#384.itm(4)} -pin  "ACC1:not#373" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-2:acc#208.psp.sva)#6.itm}
+load net {ACC1:not#373.itm} -pin  "ACC1:not#373" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#373.itm}
+load inst "ACC1:not#375" "not(1)" "INTERFACE" -attr xrf 53552 -attr oid 1608 -attr @path {/sobel/sobel:core/ACC1:not#375} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-3:acc#212.psp.sva(3)} -pin  "ACC1:not#375" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-3:acc#212.psp.sva)#6.itm}
+load net {ACC1:not#375.itm} -pin  "ACC1:not#375" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#375.itm}
+load inst "acc" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53553 -attr oid 1609 -attr vt d -attr @path {/sobel/sobel:core/acc} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "acc" {A(0)} -attr @path {/sobel/sobel:core/conc#984.itm}
+load net {ACC1:not#373.itm} -pin  "acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#984.itm}
+load net {PWR} -pin  "acc" {B(0)} -attr @path {/sobel/sobel:core/conc#985.itm}
+load net {ACC1:not#375.itm} -pin  "acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#985.itm}
+load net {acc.itm(0)} -pin  "acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(1)} -pin  "acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(2)} -pin  "acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load inst "ACC1:not#374" "not(1)" "INTERFACE" -attr xrf 53554 -attr oid 1610 -attr @path {/sobel/sobel:core/ACC1:not#374} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#414.itm(3)} -pin  "ACC1:not#374" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#10.sva)#4.itm}
+load net {ACC1:not#374.itm} -pin  "ACC1:not#374" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#374.itm}
+load inst "ACC1:not#376" "not(1)" "INTERFACE" -attr xrf 53555 -attr oid 1611 -attr @path {/sobel/sobel:core/ACC1:not#376} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#377.itm(3)} -pin  "ACC1:not#376" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#31.sva)#4.itm}
+load net {ACC1:not#376.itm} -pin  "ACC1:not#376" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#376.itm}
+load inst "ACC1:acc#732" "add(2,-1,2,-1,2)" "INTERFACE" -attr xrf 53556 -attr oid 1612 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#732} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2)"
+load net {ACC1:not#374.itm} -pin  "ACC1:acc#732" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#986.itm}
+load net {PWR} -pin  "ACC1:acc#732" {A(1)} -attr @path {/sobel/sobel:core/conc#986.itm}
+load net {ACC1:not#376.itm} -pin  "ACC1:acc#732" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#987.itm}
+load net {PWR} -pin  "ACC1:acc#732" {B(1)} -attr @path {/sobel/sobel:core/conc#987.itm}
+load net {ACC1:acc#732.itm(0)} -pin  "ACC1:acc#732" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#732.itm}
+load net {ACC1:acc#732.itm(1)} -pin  "ACC1:acc#732" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#732.itm}
+load inst "ACC1:acc#577" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53557 -attr oid 1613 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#523.itm(0)} -pin  "ACC1:acc#577" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#523.itm(1)} -pin  "ACC1:acc#577" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#523.itm(2)} -pin  "ACC1:acc#577" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#523.itm(3)} -pin  "ACC1:acc#577" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#732.itm(0)} -pin  "ACC1:acc#577" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1457.itm}
+load net {ACC1:acc#732.itm(1)} -pin  "ACC1:acc#577" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1457.itm}
+load net {acc.itm(1)} -pin  "ACC1:acc#577" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1457.itm}
+load net {acc.itm(2)} -pin  "ACC1:acc#577" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1457.itm}
+load net {ACC1:acc#577.itm(0)} -pin  "ACC1:acc#577" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(1)} -pin  "ACC1:acc#577" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(2)} -pin  "ACC1:acc#577" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(3)} -pin  "ACC1:acc#577" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(4)} -pin  "ACC1:acc#577" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load inst "ACC1:not#377" "not(1)" "INTERFACE" -attr xrf 53558 -attr oid 1614 -attr @path {/sobel/sobel:core/ACC1:not#377} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#346.itm(4)} -pin  "ACC1:not#377" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#214.psp#2.sva)#6.itm}
+load net {ACC1:not#377.itm} -pin  "ACC1:not#377" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#377.itm}
+load inst "ACC1:not#379" "not(1)" "INTERFACE" -attr xrf 53559 -attr oid 1615 -attr @path {/sobel/sobel:core/ACC1:not#379} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#208.psp.sva(3)} -pin  "ACC1:not#379" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#208.psp.sva).itm}
+load net {ACC1:not#379.itm} -pin  "ACC1:not#379" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#379.itm}
+load inst "acc#31" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53560 -attr oid 1616 -attr vt d -attr @path {/sobel/sobel:core/acc#31} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "acc#31" {A(0)} -attr @path {/sobel/sobel:core/conc#988.itm}
+load net {ACC1:not#377.itm} -pin  "acc#31" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#988.itm}
+load net {PWR} -pin  "acc#31" {B(0)} -attr @path {/sobel/sobel:core/conc#989.itm}
+load net {ACC1:not#379.itm} -pin  "acc#31" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#989.itm}
+load net {acc#31.itm(0)} -pin  "acc#31" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#31.itm}
+load net {acc#31.itm(1)} -pin  "acc#31" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#31.itm}
+load net {acc#31.itm(2)} -pin  "acc#31" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#31.itm}
+load inst "ACC1:not#378" "not(1)" "INTERFACE" -attr xrf 53561 -attr oid 1617 -attr @path {/sobel/sobel:core/ACC1:not#378} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#386.itm(3)} -pin  "ACC1:not#378" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#43.sva)#4.itm}
+load net {ACC1:not#378.itm} -pin  "ACC1:not#378" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#378.itm}
+load inst "ACC1:not#380" "not(1)" "INTERFACE" -attr xrf 53562 -attr oid 1618 -attr @path {/sobel/sobel:core/ACC1:not#380} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#405.itm(3)} -pin  "ACC1:not#380" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#4.itm}
+load net {ACC1:not#380.itm} -pin  "ACC1:not#380" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#380.itm}
+load inst "ACC1:acc#734" "add(2,-1,2,-1,2)" "INTERFACE" -attr xrf 53563 -attr oid 1619 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#734} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2)"
+load net {ACC1:not#378.itm} -pin  "ACC1:acc#734" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#990.itm}
+load net {PWR} -pin  "ACC1:acc#734" {A(1)} -attr @path {/sobel/sobel:core/conc#990.itm}
+load net {ACC1:not#380.itm} -pin  "ACC1:acc#734" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#991.itm}
+load net {PWR} -pin  "ACC1:acc#734" {B(1)} -attr @path {/sobel/sobel:core/conc#991.itm}
+load net {ACC1:acc#734.itm(0)} -pin  "ACC1:acc#734" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#734.itm}
+load net {ACC1:acc#734.itm(1)} -pin  "ACC1:acc#734" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#734.itm}
+load inst "ACC1:not#381" "not(1)" "INTERFACE" -attr xrf 53564 -attr oid 1620 -attr @path {/sobel/sobel:core/ACC1:not#381} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#210.psp#2.sva(3)} -pin  "ACC1:not#381" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#210.psp#2.sva)#12.itm}
+load net {ACC1:not#381.itm} -pin  "ACC1:not#381" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#381.itm}
+load inst "ACC1:not#392" "not(1)" "INTERFACE" -attr xrf 53565 -attr oid 1621 -attr @path {/sobel/sobel:core/ACC1:not#392} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#348.itm(3)} -pin  "ACC1:not#392" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#34.sva)#4.itm}
+load net {ACC1:not#392.itm} -pin  "ACC1:not#392" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#392.itm}
+load inst "ACC1:acc#520" "add(3,0,2,1,4)" "INTERFACE" -attr xrf 53566 -attr oid 1622 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:not#392.itm} -pin  "ACC1:acc#520" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#992.itm}
+load net {PWR} -pin  "ACC1:acc#520" {A(1)} -attr @path {/sobel/sobel:core/conc#992.itm}
+load net {ACC1:not#381.itm} -pin  "ACC1:acc#520" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#992.itm}
+load net {ACC1:acc#221.psp.sva(1)} -pin  "ACC1:acc#520" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp.sva)#2.itm}
+load net {ACC1:acc#221.psp.sva(2)} -pin  "ACC1:acc#520" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp.sva)#2.itm}
+load net {ACC1:acc#520.itm(0)} -pin  "ACC1:acc#520" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#520.itm(1)} -pin  "ACC1:acc#520" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#520.itm(2)} -pin  "ACC1:acc#520" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#520.itm(3)} -pin  "ACC1:acc#520" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load inst "ACC1:acc#576" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53567 -attr oid 1623 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#734.itm(0)} -pin  "ACC1:acc#576" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1458.itm}
+load net {ACC1:acc#734.itm(1)} -pin  "ACC1:acc#576" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1458.itm}
+load net {acc#31.itm(1)} -pin  "ACC1:acc#576" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1458.itm}
+load net {acc#31.itm(2)} -pin  "ACC1:acc#576" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1458.itm}
+load net {ACC1:acc#520.itm(0)} -pin  "ACC1:acc#576" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#520.itm(1)} -pin  "ACC1:acc#576" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#520.itm(2)} -pin  "ACC1:acc#576" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#520.itm(3)} -pin  "ACC1:acc#576" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#576.itm(0)} -pin  "ACC1:acc#576" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(1)} -pin  "ACC1:acc#576" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(2)} -pin  "ACC1:acc#576" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(3)} -pin  "ACC1:acc#576" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(4)} -pin  "ACC1:acc#576" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load inst "ACC1:acc#603" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 53568 -attr oid 1624 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#577.itm(0)} -pin  "ACC1:acc#603" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(1)} -pin  "ACC1:acc#603" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(2)} -pin  "ACC1:acc#603" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(3)} -pin  "ACC1:acc#603" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(4)} -pin  "ACC1:acc#603" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#576.itm(0)} -pin  "ACC1:acc#603" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(1)} -pin  "ACC1:acc#603" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(2)} -pin  "ACC1:acc#603" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(3)} -pin  "ACC1:acc#603" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(4)} -pin  "ACC1:acc#603" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#603.itm(0)} -pin  "ACC1:acc#603" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(1)} -pin  "ACC1:acc#603" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(2)} -pin  "ACC1:acc#603" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(3)} -pin  "ACC1:acc#603" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(4)} -pin  "ACC1:acc#603" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(5)} -pin  "ACC1:acc#603" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load inst "ACC1:acc#518" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 53569 -attr oid 1625 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#221.psp#2.sva(1)} -pin  "ACC1:acc#518" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp#2.sva)#2.itm}
+load net {ACC1:acc#221.psp#2.sva(2)} -pin  "ACC1:acc#518" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp#2.sva)#2.itm}
+load net {ACC1:acc#228.psp.sva(8)} -pin  "ACC1:acc#518" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#19.itm}
+load net {ACC1:acc#228.psp.sva(8)} -pin  "ACC1:acc#518" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#19.itm}
+load net {ACC1:acc#518.itm(0)} -pin  "ACC1:acc#518" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#518.itm(1)} -pin  "ACC1:acc#518" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#518.itm(2)} -pin  "ACC1:acc#518" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#518.itm(3)} -pin  "ACC1:acc#518" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load inst "ACC1:acc#490" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 53570 -attr oid 1626 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#219.psp#2.sva(1)} -pin  "ACC1:acc#490" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#2.sva)#2.itm}
+load net {ACC1:acc#219.psp#2.sva(2)} -pin  "ACC1:acc#490" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#2.sva)#2.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#490" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1058.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#490" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1058.itm}
+load net {ACC1:acc#490.itm(0)} -pin  "ACC1:acc#490" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#490.itm(1)} -pin  "ACC1:acc#490" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#490.itm(2)} -pin  "ACC1:acc#490" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#490.itm(3)} -pin  "ACC1:acc#490" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load inst "ACC1:acc#575" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 53571 -attr oid 1627 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#518.itm(0)} -pin  "ACC1:acc#575" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#518.itm(1)} -pin  "ACC1:acc#575" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#518.itm(2)} -pin  "ACC1:acc#575" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#518.itm(3)} -pin  "ACC1:acc#575" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#490.itm(0)} -pin  "ACC1:acc#575" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#490.itm(1)} -pin  "ACC1:acc#575" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#490.itm(2)} -pin  "ACC1:acc#575" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#490.itm(3)} -pin  "ACC1:acc#575" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#575.itm(0)} -pin  "ACC1:acc#575" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(1)} -pin  "ACC1:acc#575" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(2)} -pin  "ACC1:acc#575" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(3)} -pin  "ACC1:acc#575" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(4)} -pin  "ACC1:acc#575" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load inst "ACC1:acc#471" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 53572 -attr oid 1628 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#471" {A(0)} -attr @path {/sobel/sobel:core/exs#90.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#471" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#90.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#471" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#90.itm}
+load net {acc.psp#2.sva(2)} -pin  "ACC1:acc#471" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1401.itm}
+load net {ACC1:acc#222.psp#1.sva(1)} -pin  "ACC1:acc#471" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1401.itm}
+load net {ACC1:acc#222.psp#1.sva(2)} -pin  "ACC1:acc#471" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1401.itm}
+load net {ACC1:acc#471.itm(0)} -pin  "ACC1:acc#471" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471.itm}
+load net {ACC1:acc#471.itm(1)} -pin  "ACC1:acc#471" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471.itm}
+load net {ACC1:acc#471.itm(2)} -pin  "ACC1:acc#471" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471.itm}
+load net {ACC1:acc#471.itm(3)} -pin  "ACC1:acc#471" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471.itm}
+load net {ACC1:acc#471.itm(4)} -pin  "ACC1:acc#471" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471.itm}
+load inst "ACC1-1:not#92" "not(1)" "INTERFACE" -attr xrf 53573 -attr oid 1629 -attr @path {/sobel/sobel:core/ACC1-1:not#92} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#349.itm(2)} -pin  "ACC1-1:not#92" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#36.sva).itm}
+load net {ACC1-1:not#92.itm} -pin  "ACC1-1:not#92" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#92.itm}
+load inst "ACC1-1:and#5" "and(3,1)" "INTERFACE" -attr xrf 53574 -attr oid 1630 -attr @path {/sobel/sobel:core/ACC1-1:and#5} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1-1:and#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#27.itm}
+load net {ACC1-1:not#92.itm} -pin  "ACC1-1:and#5" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#92.itm}
+load net {ACC1:acc#349.itm(1)} -pin  "ACC1-1:and#5" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#36.sva)#1.itm}
+load net {ACC1-1:and#5.itm} -pin  "ACC1-1:and#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#5.itm}
+load inst "ACC1:acc#461" "add(3,1,3,0,5)" "INTERFACE" -attr xrf 53575 -attr oid 1631 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#461" {A(0)} -attr @path {/sobel/sobel:core/conc#994.itm}
+load net {ACC1:acc#219.psp#1.sva(1)} -pin  "ACC1:acc#461" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#994.itm}
+load net {ACC1:acc#219.psp#1.sva(2)} -pin  "ACC1:acc#461" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#994.itm}
+load net {ACC1-1:and#5.itm} -pin  "ACC1:acc#461" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1590.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#461" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1590.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#461" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1590.itm}
+load net {ACC1:acc#461.itm(0)} -pin  "ACC1:acc#461" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461.itm}
+load net {ACC1:acc#461.itm(1)} -pin  "ACC1:acc#461" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461.itm}
+load net {ACC1:acc#461.itm(2)} -pin  "ACC1:acc#461" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461.itm}
+load net {ACC1:acc#461.itm(3)} -pin  "ACC1:acc#461" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461.itm}
+load net {ACC1:acc#461.itm(4)} -pin  "ACC1:acc#461" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461.itm}
+load inst "ACC1:acc#574" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 53576 -attr oid 1632 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#471.itm(1)} -pin  "ACC1:acc#574" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#139.itm}
+load net {ACC1:acc#471.itm(2)} -pin  "ACC1:acc#574" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#139.itm}
+load net {ACC1:acc#471.itm(3)} -pin  "ACC1:acc#574" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#139.itm}
+load net {ACC1:acc#471.itm(4)} -pin  "ACC1:acc#574" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#139.itm}
+load net {ACC1:acc#461.itm(1)} -pin  "ACC1:acc#574" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#129.itm}
+load net {ACC1:acc#461.itm(2)} -pin  "ACC1:acc#574" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#129.itm}
+load net {ACC1:acc#461.itm(3)} -pin  "ACC1:acc#574" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#129.itm}
+load net {ACC1:acc#461.itm(4)} -pin  "ACC1:acc#574" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#129.itm}
+load net {ACC1:acc#574.itm(0)} -pin  "ACC1:acc#574" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(1)} -pin  "ACC1:acc#574" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(2)} -pin  "ACC1:acc#574" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(3)} -pin  "ACC1:acc#574" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(4)} -pin  "ACC1:acc#574" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load inst "ACC1:acc#602" "add(5,1,5,1,6)" "INTERFACE" -attr xrf 53577 -attr oid 1633 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,1,5,1,6)"
+load net {ACC1:acc#575.itm(0)} -pin  "ACC1:acc#602" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(1)} -pin  "ACC1:acc#602" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(2)} -pin  "ACC1:acc#602" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(3)} -pin  "ACC1:acc#602" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(4)} -pin  "ACC1:acc#602" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#574.itm(0)} -pin  "ACC1:acc#602" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(1)} -pin  "ACC1:acc#602" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(2)} -pin  "ACC1:acc#602" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(3)} -pin  "ACC1:acc#602" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(4)} -pin  "ACC1:acc#602" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#602.itm(0)} -pin  "ACC1:acc#602" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(1)} -pin  "ACC1:acc#602" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(2)} -pin  "ACC1:acc#602" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(3)} -pin  "ACC1:acc#602" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(4)} -pin  "ACC1:acc#602" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(5)} -pin  "ACC1:acc#602" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load inst "ACC1:acc#621" "add(6,0,6,1,7)" "INTERFACE" -attr xrf 53578 -attr oid 1634 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {ACC1:acc#603.itm(0)} -pin  "ACC1:acc#621" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(1)} -pin  "ACC1:acc#621" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(2)} -pin  "ACC1:acc#621" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(3)} -pin  "ACC1:acc#621" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(4)} -pin  "ACC1:acc#621" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(5)} -pin  "ACC1:acc#621" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#602.itm(0)} -pin  "ACC1:acc#621" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(1)} -pin  "ACC1:acc#621" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(2)} -pin  "ACC1:acc#621" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(3)} -pin  "ACC1:acc#621" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(4)} -pin  "ACC1:acc#621" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(5)} -pin  "ACC1:acc#621" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#621.itm(0)} -pin  "ACC1:acc#621" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(1)} -pin  "ACC1:acc#621" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(2)} -pin  "ACC1:acc#621" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(3)} -pin  "ACC1:acc#621" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(4)} -pin  "ACC1:acc#621" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(5)} -pin  "ACC1:acc#621" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(6)} -pin  "ACC1:acc#621" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load inst "ACC1:acc#640" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 53579 -attr oid 1635 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#627.itm(0)} -pin  "ACC1:acc#640" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(1)} -pin  "ACC1:acc#640" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(2)} -pin  "ACC1:acc#640" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(3)} -pin  "ACC1:acc#640" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(4)} -pin  "ACC1:acc#640" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(5)} -pin  "ACC1:acc#640" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(6)} -pin  "ACC1:acc#640" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(7)} -pin  "ACC1:acc#640" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#621.itm(0)} -pin  "ACC1:acc#640" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(1)} -pin  "ACC1:acc#640" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(2)} -pin  "ACC1:acc#640" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(3)} -pin  "ACC1:acc#640" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(4)} -pin  "ACC1:acc#640" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(5)} -pin  "ACC1:acc#640" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(6)} -pin  "ACC1:acc#640" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#640.itm(0)} -pin  "ACC1:acc#640" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(1)} -pin  "ACC1:acc#640" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(2)} -pin  "ACC1:acc#640" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(3)} -pin  "ACC1:acc#640" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(4)} -pin  "ACC1:acc#640" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(5)} -pin  "ACC1:acc#640" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(6)} -pin  "ACC1:acc#640" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(7)} -pin  "ACC1:acc#640" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load inst "ACC1:acc#301" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 53580 -attr oid 1636 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#227.psp.sva(6)} -pin  "ACC1:acc#301" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#38.itm}
+load net {acc.psp#1.sva(6)} -pin  "ACC1:acc#301" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#46.itm}
+load net {ACC1:acc#301.itm(0)} -pin  "ACC1:acc#301" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {ACC1:acc#301.itm(1)} -pin  "ACC1:acc#301" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load inst "ACC1:acc#300" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 53581 -attr oid 1637 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#301.itm(0)} -pin  "ACC1:acc#300" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {ACC1:acc#301.itm(1)} -pin  "ACC1:acc#300" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {ACC1:acc#224.psp.sva(5)} -pin  "ACC1:acc#300" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#19.itm}
+load net {ACC1:acc#300.itm(0)} -pin  "ACC1:acc#300" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#300.itm(1)} -pin  "ACC1:acc#300" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load inst "ACC1:acc#299" "add(2,0,1,0,3)" "INTERFACE" -attr xrf 53582 -attr oid 1638 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#300.itm(0)} -pin  "ACC1:acc#299" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#300.itm(1)} -pin  "ACC1:acc#299" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#228.psp.sva(5)} -pin  "ACC1:acc#299" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#22.itm}
+load net {ACC1:acc#299.itm(0)} -pin  "ACC1:acc#299" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(1)} -pin  "ACC1:acc#299" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(2)} -pin  "ACC1:acc#299" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load inst "ACC1:acc#298" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 53583 -attr oid 1639 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#299.itm(0)} -pin  "ACC1:acc#298" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(1)} -pin  "ACC1:acc#298" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(2)} -pin  "ACC1:acc#298" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#226.psp.sva(5)} -pin  "ACC1:acc#298" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#17.itm}
+load net {ACC1:acc#298.itm(0)} -pin  "ACC1:acc#298" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(1)} -pin  "ACC1:acc#298" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(2)} -pin  "ACC1:acc#298" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load inst "ACC1:acc#297" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 53584 -attr oid 1640 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#298.itm(0)} -pin  "ACC1:acc#297" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(1)} -pin  "ACC1:acc#297" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(2)} -pin  "ACC1:acc#297" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#224.psp#1.sva(5)} -pin  "ACC1:acc#297" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#38.itm}
+load net {ACC1:acc#297.itm(0)} -pin  "ACC1:acc#297" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(1)} -pin  "ACC1:acc#297" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(2)} -pin  "ACC1:acc#297" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load inst "ACC1:acc#296" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 53585 -attr oid 1641 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#297.itm(0)} -pin  "ACC1:acc#296" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(1)} -pin  "ACC1:acc#296" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(2)} -pin  "ACC1:acc#296" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1-1:acc#25.psp.sva(6)} -pin  "ACC1:acc#296" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#50.itm}
+load net {ACC1:acc#296.itm(0)} -pin  "ACC1:acc#296" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(1)} -pin  "ACC1:acc#296" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(2)} -pin  "ACC1:acc#296" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load inst "ACC1:acc#295" "add(3,0,1,0,4)" "INTERFACE" -attr xrf 53586 -attr oid 1642 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#296.itm(0)} -pin  "ACC1:acc#295" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(1)} -pin  "ACC1:acc#295" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(2)} -pin  "ACC1:acc#295" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#295" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#73.itm}
+load net {ACC1:acc#295.itm(0)} -pin  "ACC1:acc#295" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(1)} -pin  "ACC1:acc#295" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(2)} -pin  "ACC1:acc#295" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(3)} -pin  "ACC1:acc#295" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load inst "ACC1:mul" "mul(4,0,5,0,8)" "INTERFACE" -attr xrf 53587 -attr oid 1643 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,5,0,8)"
+load net {ACC1:acc#295.itm(0)} -pin  "ACC1:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(1)} -pin  "ACC1:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(2)} -pin  "ACC1:mul" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(3)} -pin  "ACC1:mul" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {PWR} -pin  "ACC1:mul" {B(0)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul" {B(1)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul" {B(2)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul" {B(3)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul" {B(4)} -attr @path {/sobel/sobel:core/C21_5}
+load net {ACC1:mul.itm(0)} -pin  "ACC1:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(1)} -pin  "ACC1:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(2)} -pin  "ACC1:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(3)} -pin  "ACC1:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(4)} -pin  "ACC1:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(5)} -pin  "ACC1:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(6)} -pin  "ACC1:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(7)} -pin  "ACC1:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load inst "ACC1:acc#639" "add(8,0,8,0,9)" "INTERFACE" -attr xrf 53588 -attr oid 1644 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9)"
+load net {ACC1:mul.itm(0)} -pin  "ACC1:acc#639" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(1)} -pin  "ACC1:acc#639" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(2)} -pin  "ACC1:acc#639" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(3)} -pin  "ACC1:acc#639" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(4)} -pin  "ACC1:acc#639" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(5)} -pin  "ACC1:acc#639" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(6)} -pin  "ACC1:acc#639" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(7)} -pin  "ACC1:acc#639" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:acc#228.psp.sva(2)} -pin  "ACC1:acc#639" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {acc#20.psp#1.sva(8)} -pin  "ACC1:acc#639" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {GND} -pin  "ACC1:acc#639" {B(2)} -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {acc#20.psp#1.sva(8)} -pin  "ACC1:acc#639" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {GND} -pin  "ACC1:acc#639" {B(4)} -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {acc#20.psp#1.sva(8)} -pin  "ACC1:acc#639" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {GND} -pin  "ACC1:acc#639" {B(6)} -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {acc#20.psp#1.sva(8)} -pin  "ACC1:acc#639" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {ACC1:acc#639.itm(0)} -pin  "ACC1:acc#639" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(1)} -pin  "ACC1:acc#639" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(2)} -pin  "ACC1:acc#639" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(3)} -pin  "ACC1:acc#639" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(4)} -pin  "ACC1:acc#639" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(5)} -pin  "ACC1:acc#639" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(6)} -pin  "ACC1:acc#639" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(7)} -pin  "ACC1:acc#639" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(8)} -pin  "ACC1:acc#639" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load inst "ACC1:acc#647" "add(8,0,9,0,10)" "INTERFACE" -attr xrf 53589 -attr oid 1645 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,11)"
+load net {ACC1:acc#640.itm(0)} -pin  "ACC1:acc#647" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(1)} -pin  "ACC1:acc#647" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(2)} -pin  "ACC1:acc#647" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(3)} -pin  "ACC1:acc#647" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(4)} -pin  "ACC1:acc#647" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(5)} -pin  "ACC1:acc#647" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(6)} -pin  "ACC1:acc#647" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(7)} -pin  "ACC1:acc#647" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#639.itm(0)} -pin  "ACC1:acc#647" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(1)} -pin  "ACC1:acc#647" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(2)} -pin  "ACC1:acc#647" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(3)} -pin  "ACC1:acc#647" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(4)} -pin  "ACC1:acc#647" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(5)} -pin  "ACC1:acc#647" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(6)} -pin  "ACC1:acc#647" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(7)} -pin  "ACC1:acc#647" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(8)} -pin  "ACC1:acc#647" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#647.itm(0)} -pin  "ACC1:acc#647" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(1)} -pin  "ACC1:acc#647" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(2)} -pin  "ACC1:acc#647" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(3)} -pin  "ACC1:acc#647" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(4)} -pin  "ACC1:acc#647" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(5)} -pin  "ACC1:acc#647" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(6)} -pin  "ACC1:acc#647" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(7)} -pin  "ACC1:acc#647" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(8)} -pin  "ACC1:acc#647" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(9)} -pin  "ACC1:acc#647" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load inst "ACC1:acc#655" "add(11,1,10,0,12)" "INTERFACE" -attr xrf 53590 -attr oid 1646 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#650.itm(0)} -pin  "ACC1:acc#655" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(1)} -pin  "ACC1:acc#655" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(2)} -pin  "ACC1:acc#655" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(3)} -pin  "ACC1:acc#655" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(4)} -pin  "ACC1:acc#655" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(5)} -pin  "ACC1:acc#655" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(6)} -pin  "ACC1:acc#655" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(7)} -pin  "ACC1:acc#655" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(8)} -pin  "ACC1:acc#655" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(9)} -pin  "ACC1:acc#655" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(10)} -pin  "ACC1:acc#655" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#647.itm(0)} -pin  "ACC1:acc#655" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(1)} -pin  "ACC1:acc#655" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(2)} -pin  "ACC1:acc#655" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(3)} -pin  "ACC1:acc#655" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(4)} -pin  "ACC1:acc#655" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(5)} -pin  "ACC1:acc#655" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(6)} -pin  "ACC1:acc#655" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(7)} -pin  "ACC1:acc#655" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(8)} -pin  "ACC1:acc#655" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(9)} -pin  "ACC1:acc#655" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#655.itm(0)} -pin  "ACC1:acc#655" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(1)} -pin  "ACC1:acc#655" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(2)} -pin  "ACC1:acc#655" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(3)} -pin  "ACC1:acc#655" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(4)} -pin  "ACC1:acc#655" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(5)} -pin  "ACC1:acc#655" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(6)} -pin  "ACC1:acc#655" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(7)} -pin  "ACC1:acc#655" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(8)} -pin  "ACC1:acc#655" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(9)} -pin  "ACC1:acc#655" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(10)} -pin  "ACC1:acc#655" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(11)} -pin  "ACC1:acc#655" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load inst "reg(ACC1:acc#655.itm#1)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 53591 -attr oid 1647 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#655.itm#1)}
+load net {ACC1:acc#655.itm(0)} -pin  "reg(ACC1:acc#655.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(1)} -pin  "reg(ACC1:acc#655.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(2)} -pin  "reg(ACC1:acc#655.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(3)} -pin  "reg(ACC1:acc#655.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(4)} -pin  "reg(ACC1:acc#655.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(5)} -pin  "reg(ACC1:acc#655.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(6)} -pin  "reg(ACC1:acc#655.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(7)} -pin  "reg(ACC1:acc#655.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(8)} -pin  "reg(ACC1:acc#655.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(9)} -pin  "reg(ACC1:acc#655.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(10)} -pin  "reg(ACC1:acc#655.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(11)} -pin  "reg(ACC1:acc#655.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(ACC1:acc#655.itm#1)" {clk} -attr xrf 53592 -attr oid 1648 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#655.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#655.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#655.itm#1(0)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(1)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(2)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(3)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(4)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(5)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(6)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(7)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(8)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(9)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(10)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(11)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load inst "reg(main.stage_0#2)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 53593 -attr oid 1649 -attr @path {/sobel/sobel:core/reg(main.stage_0#2)}
+load net {PWR} -pin  "reg(main.stage_0#2)" {D(0)} -attr @path {/sobel/sobel:core/C0_10#10_Not}
+load net {GND} -pin  "reg(main.stage_0#2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#10}
+load net {clk} -pin  "reg(main.stage_0#2)" {clk} -attr xrf 53594 -attr oid 1650 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(main.stage_0#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(main.stage_0#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {main.stage_0#2} -pin  "reg(main.stage_0#2)" {Z(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load inst "reg(regs.regs:slc(regs.regs(2))#10.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 53595 -attr oid 1651 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#10.itm)}
+load net {reg(regs.regs(0).sva).cse(70)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(71)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(72)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(73)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(74)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(75)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(76)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(77)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(78)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(79)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {clk} -attr xrf 53596 -attr oid 1652 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#10.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#11.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 53597 -attr oid 1653 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#11.itm)}
+load net {reg(regs.regs(0).sva).cse(60)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(61)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(62)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(63)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(64)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(65)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(66)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(67)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(68)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(69)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {clk} -attr xrf 53598 -attr oid 1654 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#11.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#9.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 53599 -attr oid 1655 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#9.itm)}
+load net {reg(regs.regs(0).sva).cse(80)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(81)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(82)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(83)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(84)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(85)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(86)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(87)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(88)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(89)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {clk} -attr xrf 53600 -attr oid 1656 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#9.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#4.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 53601 -attr oid 1657 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#4.itm)}
+load net {reg(regs.regs(0).sva).cse(40)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(41)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(42)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(43)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(44)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(45)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(46)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(47)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(48)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(49)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {clk} -attr xrf 53602 -attr oid 1658 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#4.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#5.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 53603 -attr oid 1659 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#5.itm)}
+load net {reg(regs.regs(0).sva).cse(30)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(31)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(32)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(33)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(34)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(35)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(36)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(37)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(38)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(39)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {clk} -attr xrf 53604 -attr oid 1660 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#5.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#3.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 53605 -attr oid 1661 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#3.itm)}
+load net {reg(regs.regs(0).sva).cse(50)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(51)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(52)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(53)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(54)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(55)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(56)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(57)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(58)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(59)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {clk} -attr xrf 53606 -attr oid 1662 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#3.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load inst "reg(regs.regs:slc(regs.regs(2)).itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 53607 -attr oid 1663 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2)).itm)}
+load net {reg(regs.regs(0).sva).cse(20)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(21)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(22)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(23)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(24)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(25)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(26)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(27)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(28)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(29)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {clk} -attr xrf 53608 -attr oid 1664 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2)).itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#1.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 53609 -attr oid 1665 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#1.itm)}
+load net {reg(regs.regs(0).sva).cse(10)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(11)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(12)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(13)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(14)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(15)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(16)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(17)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(18)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(19)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {clk} -attr xrf 53610 -attr oid 1666 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#1.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#2.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 53611 -attr oid 1667 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#2.itm)}
+load net {reg(regs.regs(0).sva).cse(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {clk} -attr xrf 53612 -attr oid 1668 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#2.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load inst "reg(regs.regs(0).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 53613 -attr oid 1669 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva)}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "reg(regs.regs(0).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "reg(regs.regs(0).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "reg(regs.regs(0).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "reg(regs.regs(0).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "reg(regs.regs(0).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "reg(regs.regs(0).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "reg(regs.regs(0).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "reg(regs.regs(0).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "reg(regs.regs(0).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "reg(regs.regs(0).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "reg(regs.regs(0).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "reg(regs.regs(0).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "reg(regs.regs(0).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "reg(regs.regs(0).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "reg(regs.regs(0).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "reg(regs.regs(0).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "reg(regs.regs(0).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "reg(regs.regs(0).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "reg(regs.regs(0).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "reg(regs.regs(0).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "reg(regs.regs(0).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "reg(regs.regs(0).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "reg(regs.regs(0).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "reg(regs.regs(0).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "reg(regs.regs(0).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "reg(regs.regs(0).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "reg(regs.regs(0).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "reg(regs.regs(0).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "reg(regs.regs(0).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "reg(regs.regs(0).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "reg(regs.regs(0).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "reg(regs.regs(0).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "reg(regs.regs(0).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "reg(regs.regs(0).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "reg(regs.regs(0).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "reg(regs.regs(0).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "reg(regs.regs(0).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "reg(regs.regs(0).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "reg(regs.regs(0).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "reg(regs.regs(0).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "reg(regs.regs(0).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "reg(regs.regs(0).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "reg(regs.regs(0).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "reg(regs.regs(0).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "reg(regs.regs(0).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "reg(regs.regs(0).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "reg(regs.regs(0).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "reg(regs.regs(0).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "reg(regs.regs(0).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "reg(regs.regs(0).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "reg(regs.regs(0).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "reg(regs.regs(0).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "reg(regs.regs(0).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "reg(regs.regs(0).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "reg(regs.regs(0).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "reg(regs.regs(0).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "reg(regs.regs(0).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "reg(regs.regs(0).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "reg(regs.regs(0).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "reg(regs.regs(0).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "reg(regs.regs(0).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "reg(regs.regs(0).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "reg(regs.regs(0).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "reg(regs.regs(0).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "reg(regs.regs(0).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "reg(regs.regs(0).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "reg(regs.regs(0).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "reg(regs.regs(0).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "reg(regs.regs(0).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "reg(regs.regs(0).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "reg(regs.regs(0).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "reg(regs.regs(0).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "reg(regs.regs(0).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "reg(regs.regs(0).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "reg(regs.regs(0).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "reg(regs.regs(0).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "reg(regs.regs(0).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "reg(regs.regs(0).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "reg(regs.regs(0).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "reg(regs.regs(0).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "reg(regs.regs(0).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "reg(regs.regs(0).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "reg(regs.regs(0).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "reg(regs.regs(0).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "reg(regs.regs(0).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "reg(regs.regs(0).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "reg(regs.regs(0).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "reg(regs.regs(0).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "reg(regs.regs(0).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "reg(regs.regs(0).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {clk} -pin  "reg(regs.regs(0).sva)" {clk} -attr xrf 53614 -attr oid 1670 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(0).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(0).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {reg(regs.regs(0).sva).cse(0)} -pin  "reg(regs.regs(0).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(1)} -pin  "reg(regs.regs(0).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(2)} -pin  "reg(regs.regs(0).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(3)} -pin  "reg(regs.regs(0).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(4)} -pin  "reg(regs.regs(0).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(5)} -pin  "reg(regs.regs(0).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(6)} -pin  "reg(regs.regs(0).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(7)} -pin  "reg(regs.regs(0).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(8)} -pin  "reg(regs.regs(0).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(9)} -pin  "reg(regs.regs(0).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(10)} -pin  "reg(regs.regs(0).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(11)} -pin  "reg(regs.regs(0).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(12)} -pin  "reg(regs.regs(0).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(13)} -pin  "reg(regs.regs(0).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(14)} -pin  "reg(regs.regs(0).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(15)} -pin  "reg(regs.regs(0).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(16)} -pin  "reg(regs.regs(0).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(17)} -pin  "reg(regs.regs(0).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(18)} -pin  "reg(regs.regs(0).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(19)} -pin  "reg(regs.regs(0).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(20)} -pin  "reg(regs.regs(0).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(21)} -pin  "reg(regs.regs(0).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(22)} -pin  "reg(regs.regs(0).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(23)} -pin  "reg(regs.regs(0).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(24)} -pin  "reg(regs.regs(0).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(25)} -pin  "reg(regs.regs(0).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(26)} -pin  "reg(regs.regs(0).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(27)} -pin  "reg(regs.regs(0).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(28)} -pin  "reg(regs.regs(0).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(29)} -pin  "reg(regs.regs(0).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(30)} -pin  "reg(regs.regs(0).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(31)} -pin  "reg(regs.regs(0).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(32)} -pin  "reg(regs.regs(0).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(33)} -pin  "reg(regs.regs(0).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(34)} -pin  "reg(regs.regs(0).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(35)} -pin  "reg(regs.regs(0).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(36)} -pin  "reg(regs.regs(0).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(37)} -pin  "reg(regs.regs(0).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(38)} -pin  "reg(regs.regs(0).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(39)} -pin  "reg(regs.regs(0).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(40)} -pin  "reg(regs.regs(0).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(41)} -pin  "reg(regs.regs(0).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(42)} -pin  "reg(regs.regs(0).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(43)} -pin  "reg(regs.regs(0).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(44)} -pin  "reg(regs.regs(0).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(45)} -pin  "reg(regs.regs(0).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(46)} -pin  "reg(regs.regs(0).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(47)} -pin  "reg(regs.regs(0).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(48)} -pin  "reg(regs.regs(0).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(49)} -pin  "reg(regs.regs(0).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(50)} -pin  "reg(regs.regs(0).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(51)} -pin  "reg(regs.regs(0).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(52)} -pin  "reg(regs.regs(0).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(53)} -pin  "reg(regs.regs(0).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(54)} -pin  "reg(regs.regs(0).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(55)} -pin  "reg(regs.regs(0).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(56)} -pin  "reg(regs.regs(0).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(57)} -pin  "reg(regs.regs(0).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(58)} -pin  "reg(regs.regs(0).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(59)} -pin  "reg(regs.regs(0).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(60)} -pin  "reg(regs.regs(0).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(61)} -pin  "reg(regs.regs(0).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(62)} -pin  "reg(regs.regs(0).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(63)} -pin  "reg(regs.regs(0).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(64)} -pin  "reg(regs.regs(0).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(65)} -pin  "reg(regs.regs(0).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(66)} -pin  "reg(regs.regs(0).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(67)} -pin  "reg(regs.regs(0).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(68)} -pin  "reg(regs.regs(0).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(69)} -pin  "reg(regs.regs(0).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(70)} -pin  "reg(regs.regs(0).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(71)} -pin  "reg(regs.regs(0).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(72)} -pin  "reg(regs.regs(0).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(73)} -pin  "reg(regs.regs(0).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(74)} -pin  "reg(regs.regs(0).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(75)} -pin  "reg(regs.regs(0).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(76)} -pin  "reg(regs.regs(0).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(77)} -pin  "reg(regs.regs(0).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(78)} -pin  "reg(regs.regs(0).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(79)} -pin  "reg(regs.regs(0).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(80)} -pin  "reg(regs.regs(0).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(81)} -pin  "reg(regs.regs(0).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(82)} -pin  "reg(regs.regs(0).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(83)} -pin  "reg(regs.regs(0).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(84)} -pin  "reg(regs.regs(0).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(85)} -pin  "reg(regs.regs(0).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(86)} -pin  "reg(regs.regs(0).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(87)} -pin  "reg(regs.regs(0).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(88)} -pin  "reg(regs.regs(0).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(89)} -pin  "reg(regs.regs(0).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load inst "FRAME:mul" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 53615 -attr oid 1671 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,11,1,13)"
+load net {ACC1:acc.itm(13)} -pin  "FRAME:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#13.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#13.itm}
+load net {PWR} -pin  "FRAME:mul" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul.itm(0)} -pin  "FRAME:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(1)} -pin  "FRAME:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(2)} -pin  "FRAME:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(3)} -pin  "FRAME:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(4)} -pin  "FRAME:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(5)} -pin  "FRAME:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(6)} -pin  "FRAME:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(7)} -pin  "FRAME:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(8)} -pin  "FRAME:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(9)} -pin  "FRAME:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(10)} -pin  "FRAME:mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load inst "FRAME:mul#1" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 53616 -attr oid 1672 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc.itm(10)} -pin  "FRAME:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#1.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#1.itm}
+load net {ACC1:acc.itm(12)} -pin  "FRAME:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#1.itm}
+load net {PWR} -pin  "FRAME:mul#1" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#1.itm(0)} -pin  "FRAME:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "FRAME:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "FRAME:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "FRAME:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "FRAME:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "FRAME:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "FRAME:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "FRAME:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "FRAME:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load inst "FRAME:not#7" "not(1)" "INTERFACE" -attr xrf 53617 -attr oid 1673 -attr @path {/sobel/sobel:core/FRAME:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#24.sva(5)} -pin  "FRAME:not#7" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#6.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load inst "FRAME:not#5" "not(3)" "INTERFACE" -attr xrf 53618 -attr oid 1674 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#24.sva(3)} -pin  "FRAME:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#2.itm}
+load net {acc.imod#24.sva(4)} -pin  "FRAME:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#2.itm}
+load net {acc.imod#24.sva(5)} -pin  "FRAME:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#2.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load inst "FRAME:not#4" "not(1)" "INTERFACE" -attr xrf 53619 -attr oid 1675 -attr @path {/sobel/sobel:core/FRAME:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#24.sva(5)} -pin  "FRAME:not#4" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#3.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:not#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#4.itm}
+load inst "FRAME:acc#16" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 53620 -attr oid 1676 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "FRAME:acc#16" {A(0)} -attr @path {/sobel/sobel:core/conc#998.itm}
+load net {acc.imod#24.sva(0)} -pin  "FRAME:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#998.itm}
+load net {acc.imod#24.sva(1)} -pin  "FRAME:acc#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#998.itm}
+load net {acc.imod#24.sva(2)} -pin  "FRAME:acc#16" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#998.itm}
+load net {PWR} -pin  "FRAME:acc#16" {A(4)} -attr @path {/sobel/sobel:core/conc#998.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:acc#16" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:acc#16" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:acc#16" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:acc#16" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:acc#16.itm(0)} -pin  "FRAME:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "FRAME:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "FRAME:acc#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "FRAME:acc#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:acc#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load inst "FRAME:not#14" "not(1)" "INTERFACE" -attr xrf 53621 -attr oid 1677 -attr @path {/sobel/sobel:core/FRAME:not#14} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:not#14" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#3.itm}
+load net {FRAME:not#14.itm} -pin  "FRAME:not#14" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load inst "FRAME:acc#10" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 53622 -attr oid 1678 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {FRAME:not#14.itm} -pin  "FRAME:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#997.itm}
+load net {PWR} -pin  "FRAME:acc#10" {A(1)} -attr @path {/sobel/sobel:core/conc#997.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#997.itm}
+load net {acc.imod#24.sva(3)} -pin  "FRAME:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#4.itm}
+load net {acc.imod#24.sva(4)} -pin  "FRAME:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#4.itm}
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load inst "FRAME:not#6" "not(3)" "INTERFACE" -attr xrf 53623 -attr oid 1679 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(7)} -pin  "FRAME:not#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#3.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:not#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#3.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:not#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#3.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:not#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:not#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:not#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load inst "FRAME:acc#11" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 53624 -attr oid 1680 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#11" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#11" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#11" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#11" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:acc#11" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:acc#11" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:acc#11" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#11" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#11" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#11" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#11" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load inst "FRAME:acc#12" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 53625 -attr oid 1681 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {acc.imod#24.sva(5)} -pin  "FRAME:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#996.itm}
+load net {PWR} -pin  "FRAME:acc#12" {A(1)} -attr @path {/sobel/sobel:core/conc#996.itm}
+load net {GND} -pin  "FRAME:acc#12" {A(2)} -attr @path {/sobel/sobel:core/conc#996.itm}
+load net {GND} -pin  "FRAME:acc#12" {A(3)} -attr @path {/sobel/sobel:core/conc#996.itm}
+load net {PWR} -pin  "FRAME:acc#12" {A(4)} -attr @path {/sobel/sobel:core/conc#996.itm}
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#12" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#12" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(4)} -pin  "FRAME:acc#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load inst "FRAME:acc#13" "add(6,0,5,1,7)" "INTERFACE" -attr xrf 53626 -attr oid 1682 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {ACC1:acc.itm(4)} -pin  "FRAME:acc#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#2.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:acc#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#2.itm}
+load net {ACC1:acc.itm(6)} -pin  "FRAME:acc#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#2.itm}
+load net {ACC1:acc.itm(7)} -pin  "FRAME:acc#13" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#2.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:acc#13" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#2.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:acc#13" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#2.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#13" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#13" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#13" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#13" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(4)} -pin  "FRAME:acc#13" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(4)} -pin  "FRAME:acc#13" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(5)} -pin  "FRAME:acc#13" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(6)} -pin  "FRAME:acc#13" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load inst "FRAME:acc#14" "add(9,0,7,1,10)" "INTERFACE" -attr xrf 53627 -attr oid 1683 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,11)"
+load net {FRAME:mul#1.itm(0)} -pin  "FRAME:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "FRAME:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "FRAME:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "FRAME:acc#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "FRAME:acc#14" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "FRAME:acc#14" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "FRAME:acc#14" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "FRAME:acc#14" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "FRAME:acc#14" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#14" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(4)} -pin  "FRAME:acc#14" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(5)} -pin  "FRAME:acc#14" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(6)} -pin  "FRAME:acc#14" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
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+load net {FRAME:acc#14.itm(4)} -pin  "FRAME:acc#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(5)} -pin  "FRAME:acc#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(6)} -pin  "FRAME:acc#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(7)} -pin  "FRAME:acc#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(8)} -pin  "FRAME:acc#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(9)} -pin  "FRAME:acc#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load inst "FRAME:acc#15" "add(11,0,10,1,12)" "INTERFACE" -attr xrf 53628 -attr oid 1684 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,12)"
+load net {FRAME:mul.itm(0)} -pin  "FRAME:acc#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(1)} -pin  "FRAME:acc#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(2)} -pin  "FRAME:acc#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(3)} -pin  "FRAME:acc#15" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(4)} -pin  "FRAME:acc#15" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(5)} -pin  "FRAME:acc#15" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
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+load net {FRAME:acc#14.itm(8)} -pin  "FRAME:acc#15" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
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+load net {FRAME:acc#15.itm(11)} -pin  "FRAME:acc#15" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load inst "FRAME:acc#2" "add(12,-1,11,0,12)" "INTERFACE" -attr xrf 53629 -attr oid 1685 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
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+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(5)} -pin  "FRAME:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(6)} -pin  "FRAME:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(7)} -pin  "FRAME:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(8)} -pin  "FRAME:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
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+load net {FRAME:acc#15.itm(11)} -pin  "FRAME:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(1)} -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(5)} -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(6)} -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(7)} -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {FRAME:acc#2.psp.sva(0)} -pin  "FRAME:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "FRAME:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "FRAME:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "FRAME:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "FRAME:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "FRAME:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "FRAME:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "FRAME:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "FRAME:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "FRAME:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(10)} -pin  "FRAME:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(11)} -pin  "FRAME:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load inst "ACC1:acc#662" "add(13,1,13,1,14)" "INTERFACE" -attr xrf 53630 -attr oid 1686 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662} -attr area 14.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,1,13,1,14)"
+load net {ACC1:acc#659.itm#1(0)} -pin  "ACC1:acc#662" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(1)} -pin  "ACC1:acc#662" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(2)} -pin  "ACC1:acc#662" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(3)} -pin  "ACC1:acc#662" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(4)} -pin  "ACC1:acc#662" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(5)} -pin  "ACC1:acc#662" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(6)} -pin  "ACC1:acc#662" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(7)} -pin  "ACC1:acc#662" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(8)} -pin  "ACC1:acc#662" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(9)} -pin  "ACC1:acc#662" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(10)} -pin  "ACC1:acc#662" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(11)} -pin  "ACC1:acc#662" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(12)} -pin  "ACC1:acc#662" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#658.itm#1(0)} -pin  "ACC1:acc#662" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(1)} -pin  "ACC1:acc#662" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(2)} -pin  "ACC1:acc#662" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(3)} -pin  "ACC1:acc#662" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(4)} -pin  "ACC1:acc#662" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(5)} -pin  "ACC1:acc#662" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(6)} -pin  "ACC1:acc#662" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(7)} -pin  "ACC1:acc#662" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(8)} -pin  "ACC1:acc#662" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(9)} -pin  "ACC1:acc#662" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(10)} -pin  "ACC1:acc#662" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(11)} -pin  "ACC1:acc#662" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(12)} -pin  "ACC1:acc#662" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#662.itm(0)} -pin  "ACC1:acc#662" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(1)} -pin  "ACC1:acc#662" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(2)} -pin  "ACC1:acc#662" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(3)} -pin  "ACC1:acc#662" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(4)} -pin  "ACC1:acc#662" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(5)} -pin  "ACC1:acc#662" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(6)} -pin  "ACC1:acc#662" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(7)} -pin  "ACC1:acc#662" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(8)} -pin  "ACC1:acc#662" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(9)} -pin  "ACC1:acc#662" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(10)} -pin  "ACC1:acc#662" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(11)} -pin  "ACC1:acc#662" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(12)} -pin  "ACC1:acc#662" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(13)} -pin  "ACC1:acc#662" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load inst "ACC1:acc#664" "add(14,1,14,1,15)" "INTERFACE" -attr xrf 53631 -attr oid 1687 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664} -attr area 15.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(14,1,14,1,15)"
+load net {ACC1:acc#662.itm(0)} -pin  "ACC1:acc#664" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(1)} -pin  "ACC1:acc#664" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(2)} -pin  "ACC1:acc#664" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(3)} -pin  "ACC1:acc#664" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(4)} -pin  "ACC1:acc#664" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(5)} -pin  "ACC1:acc#664" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(6)} -pin  "ACC1:acc#664" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(7)} -pin  "ACC1:acc#664" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(8)} -pin  "ACC1:acc#664" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(9)} -pin  "ACC1:acc#664" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(10)} -pin  "ACC1:acc#664" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(11)} -pin  "ACC1:acc#664" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(12)} -pin  "ACC1:acc#664" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(13)} -pin  "ACC1:acc#664" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#661.itm#1(0)} -pin  "ACC1:acc#664" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(1)} -pin  "ACC1:acc#664" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(2)} -pin  "ACC1:acc#664" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(3)} -pin  "ACC1:acc#664" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(4)} -pin  "ACC1:acc#664" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(5)} -pin  "ACC1:acc#664" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(6)} -pin  "ACC1:acc#664" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(7)} -pin  "ACC1:acc#664" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(8)} -pin  "ACC1:acc#664" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(9)} -pin  "ACC1:acc#664" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(10)} -pin  "ACC1:acc#664" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(11)} -pin  "ACC1:acc#664" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(12)} -pin  "ACC1:acc#664" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(13)} -pin  "ACC1:acc#664" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#664.itm(0)} -pin  "ACC1:acc#664" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(1)} -pin  "ACC1:acc#664" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(2)} -pin  "ACC1:acc#664" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(3)} -pin  "ACC1:acc#664" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(4)} -pin  "ACC1:acc#664" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(5)} -pin  "ACC1:acc#664" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(6)} -pin  "ACC1:acc#664" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(7)} -pin  "ACC1:acc#664" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(8)} -pin  "ACC1:acc#664" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(9)} -pin  "ACC1:acc#664" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(10)} -pin  "ACC1:acc#664" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(11)} -pin  "ACC1:acc#664" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(12)} -pin  "ACC1:acc#664" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(13)} -pin  "ACC1:acc#664" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(14)} -pin  "ACC1:acc#664" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load inst "ACC1:acc#656" "add(12,-1,11,0,12)" "INTERFACE" -attr xrf 53632 -attr oid 1688 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1-3:slc(acc#10.psp)#62.itm#1} -pin  "ACC1:acc#656" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {ACC1-3:slc(acc#10.psp)#62.itm#1} -pin  "ACC1:acc#656" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {GND} -pin  "ACC1:acc#656" {A(2)} -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {ACC1:slc(ACC1:acc#228.psp)#55.itm#1} -pin  "ACC1:acc#656" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {slc(acc#20.psp#1)#93.itm#1} -pin  "ACC1:acc#656" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {GND} -pin  "ACC1:acc#656" {A(5)} -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {slc(acc#20.psp#1)#93.itm#1} -pin  "ACC1:acc#656" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {GND} -pin  "ACC1:acc#656" {A(7)} -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {slc(acc#20.psp#1)#93.itm#1} -pin  "ACC1:acc#656" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {GND} -pin  "ACC1:acc#656" {A(9)} -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {GND} -pin  "ACC1:acc#656" {A(10)} -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {slc(acc#20.psp#1)#93.itm#1} -pin  "ACC1:acc#656" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {ACC1:acc#652.itm#1(0)} -pin  "ACC1:acc#656" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(1)} -pin  "ACC1:acc#656" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(2)} -pin  "ACC1:acc#656" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(3)} -pin  "ACC1:acc#656" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(4)} -pin  "ACC1:acc#656" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(5)} -pin  "ACC1:acc#656" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(6)} -pin  "ACC1:acc#656" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(7)} -pin  "ACC1:acc#656" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(8)} -pin  "ACC1:acc#656" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(9)} -pin  "ACC1:acc#656" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(10)} -pin  "ACC1:acc#656" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#656.itm(0)} -pin  "ACC1:acc#656" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(1)} -pin  "ACC1:acc#656" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(2)} -pin  "ACC1:acc#656" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(3)} -pin  "ACC1:acc#656" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(4)} -pin  "ACC1:acc#656" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(5)} -pin  "ACC1:acc#656" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(6)} -pin  "ACC1:acc#656" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(7)} -pin  "ACC1:acc#656" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(8)} -pin  "ACC1:acc#656" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(9)} -pin  "ACC1:acc#656" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(10)} -pin  "ACC1:acc#656" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(11)} -pin  "ACC1:acc#656" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load inst "ACC1:acc#660" "add(12,1,12,1,13)" "INTERFACE" -attr xrf 53633 -attr oid 1689 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1:acc#656.itm(0)} -pin  "ACC1:acc#660" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(1)} -pin  "ACC1:acc#660" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(2)} -pin  "ACC1:acc#660" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(3)} -pin  "ACC1:acc#660" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(4)} -pin  "ACC1:acc#660" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(5)} -pin  "ACC1:acc#660" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(6)} -pin  "ACC1:acc#660" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(7)} -pin  "ACC1:acc#660" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(8)} -pin  "ACC1:acc#660" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(9)} -pin  "ACC1:acc#660" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(10)} -pin  "ACC1:acc#660" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(11)} -pin  "ACC1:acc#660" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#655.itm#1(0)} -pin  "ACC1:acc#660" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(1)} -pin  "ACC1:acc#660" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(2)} -pin  "ACC1:acc#660" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(3)} -pin  "ACC1:acc#660" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(4)} -pin  "ACC1:acc#660" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(5)} -pin  "ACC1:acc#660" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(6)} -pin  "ACC1:acc#660" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(7)} -pin  "ACC1:acc#660" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(8)} -pin  "ACC1:acc#660" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(9)} -pin  "ACC1:acc#660" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(10)} -pin  "ACC1:acc#660" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(11)} -pin  "ACC1:acc#660" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#660.itm(0)} -pin  "ACC1:acc#660" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(1)} -pin  "ACC1:acc#660" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(2)} -pin  "ACC1:acc#660" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(3)} -pin  "ACC1:acc#660" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(4)} -pin  "ACC1:acc#660" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(5)} -pin  "ACC1:acc#660" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(6)} -pin  "ACC1:acc#660" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(7)} -pin  "ACC1:acc#660" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(8)} -pin  "ACC1:acc#660" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(9)} -pin  "ACC1:acc#660" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(10)} -pin  "ACC1:acc#660" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(11)} -pin  "ACC1:acc#660" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(12)} -pin  "ACC1:acc#660" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load inst "ACC1:acc#663" "add(14,-1,13,1,14)" "INTERFACE" -attr xrf 53634 -attr oid 1690 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663} -attr area 15.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(14,1,14,1,15)"
+load net {ACC1:mul#57.itm#2(0)} -pin  "ACC1:acc#663" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:mul#57.itm#2(1)} -pin  "ACC1:acc#663" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(2)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(3)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(4)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(5)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(6)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(7)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(8)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:mul#57.itm#1.sg2(0)} -pin  "ACC1:acc#663" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:mul#57.itm#1.sg2(1)} -pin  "ACC1:acc#663" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:mul#57.itm#1.sg2(2)} -pin  "ACC1:acc#663" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:mul#57.itm#1.sg2(3)} -pin  "ACC1:acc#663" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:mul#57.itm#1.sg2(4)} -pin  "ACC1:acc#663" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:acc#660.itm(0)} -pin  "ACC1:acc#663" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(1)} -pin  "ACC1:acc#663" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(2)} -pin  "ACC1:acc#663" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(3)} -pin  "ACC1:acc#663" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(4)} -pin  "ACC1:acc#663" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(5)} -pin  "ACC1:acc#663" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(6)} -pin  "ACC1:acc#663" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(7)} -pin  "ACC1:acc#663" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(8)} -pin  "ACC1:acc#663" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(9)} -pin  "ACC1:acc#663" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(10)} -pin  "ACC1:acc#663" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(11)} -pin  "ACC1:acc#663" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(12)} -pin  "ACC1:acc#663" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#663.itm(0)} -pin  "ACC1:acc#663" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(1)} -pin  "ACC1:acc#663" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(2)} -pin  "ACC1:acc#663" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(3)} -pin  "ACC1:acc#663" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(4)} -pin  "ACC1:acc#663" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(5)} -pin  "ACC1:acc#663" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(6)} -pin  "ACC1:acc#663" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(7)} -pin  "ACC1:acc#663" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(8)} -pin  "ACC1:acc#663" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(9)} -pin  "ACC1:acc#663" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(10)} -pin  "ACC1:acc#663" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(11)} -pin  "ACC1:acc#663" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(12)} -pin  "ACC1:acc#663" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(13)} -pin  "ACC1:acc#663" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load inst "ACC1:acc" "add(15,-1,14,1,15)" "INTERFACE" -attr xrf 53635 -attr oid 1691 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc} -attr area 16.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,14,1,15)"
+load net {ACC1:acc#664.itm(0)} -pin  "ACC1:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(1)} -pin  "ACC1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(2)} -pin  "ACC1:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(3)} -pin  "ACC1:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(4)} -pin  "ACC1:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(5)} -pin  "ACC1:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(6)} -pin  "ACC1:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(7)} -pin  "ACC1:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(8)} -pin  "ACC1:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(9)} -pin  "ACC1:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(10)} -pin  "ACC1:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(11)} -pin  "ACC1:acc" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(12)} -pin  "ACC1:acc" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(13)} -pin  "ACC1:acc" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(14)} -pin  "ACC1:acc" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#663.itm(0)} -pin  "ACC1:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(1)} -pin  "ACC1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(2)} -pin  "ACC1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(3)} -pin  "ACC1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(4)} -pin  "ACC1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(5)} -pin  "ACC1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(6)} -pin  "ACC1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(7)} -pin  "ACC1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(8)} -pin  "ACC1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(9)} -pin  "ACC1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(10)} -pin  "ACC1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(11)} -pin  "ACC1:acc" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(12)} -pin  "ACC1:acc" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(13)} -pin  "ACC1:acc" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc.itm(0)} -pin  "ACC1:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(1)} -pin  "ACC1:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(2)} -pin  "ACC1:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(3)} -pin  "ACC1:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(4)} -pin  "ACC1:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(5)} -pin  "ACC1:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(6)} -pin  "ACC1:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(7)} -pin  "ACC1:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(8)} -pin  "ACC1:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(9)} -pin  "ACC1:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(10)} -pin  "ACC1:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(11)} -pin  "ACC1:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(12)} -pin  "ACC1:acc" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(13)} -pin  "ACC1:acc" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(14)} -pin  "ACC1:acc" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load inst "FRAME:not#2" "not(3)" "INTERFACE" -attr xrf 53636 -attr oid 1692 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(10)} -pin  "FRAME:not#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#6.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:not#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#6.itm}
+load net {ACC1:acc.itm(12)} -pin  "FRAME:not#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#6.itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:not#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:not#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:not#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load inst "FRAME:acc#6" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53637 -attr oid 1693 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc.itm(7)} -pin  "FRAME:acc#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#5.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:acc#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#5.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:acc#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#5.itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:acc#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:acc#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:acc#6" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:acc#6.itm(0)} -pin  "FRAME:acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(1)} -pin  "FRAME:acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(2)} -pin  "FRAME:acc#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(3)} -pin  "FRAME:acc#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load inst "FRAME:not#12" "not(1)" "INTERFACE" -attr xrf 53638 -attr oid 1694 -attr @path {/sobel/sobel:core/FRAME:not#12} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc.itm(14)} -pin  "FRAME:not#12" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#29.itm}
+load net {FRAME:not#12.itm} -pin  "FRAME:not#12" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#12.itm}
+load inst "FRAME:not#16" "not(1)" "INTERFACE" -attr xrf 53639 -attr oid 1695 -attr @path {/sobel/sobel:core/FRAME:not#16} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc.itm(14)} -pin  "FRAME:not#16" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#11.itm}
+load net {FRAME:not#16.itm} -pin  "FRAME:not#16" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load inst "FRAME:acc#5" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 53640 -attr oid 1696 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {FRAME:not#16.itm} -pin  "FRAME:acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1003.itm}
+load net {PWR} -pin  "FRAME:acc#5" {A(1)} -attr @path {/sobel/sobel:core/conc#1003.itm}
+load net {FRAME:not#12.itm} -pin  "FRAME:acc#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1003.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#5" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva).itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#5" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva).itm}
+load net {FRAME:acc#5.itm(0)} -pin  "FRAME:acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(1)} -pin  "FRAME:acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(2)} -pin  "FRAME:acc#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(3)} -pin  "FRAME:acc#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load inst "FRAME:acc#8" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 53641 -attr oid 1697 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#6.itm(0)} -pin  "FRAME:acc#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(1)} -pin  "FRAME:acc#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(2)} -pin  "FRAME:acc#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(3)} -pin  "FRAME:acc#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#5.itm(0)} -pin  "FRAME:acc#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(1)} -pin  "FRAME:acc#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(2)} -pin  "FRAME:acc#8" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(3)} -pin  "FRAME:acc#8" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(4)} -pin  "FRAME:acc#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load inst "FRAME:not#1" "not(3)" "INTERFACE" -attr xrf 53642 -attr oid 1698 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(4)} -pin  "FRAME:not#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#8.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:not#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#8.itm}
+load net {ACC1:acc.itm(6)} -pin  "FRAME:not#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#8.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:not#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:not#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:not#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load inst "FRAME:acc#7" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53643 -attr oid 1699 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc.itm(1)} -pin  "FRAME:acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#7.itm}
+load net {ACC1:acc.itm(2)} -pin  "FRAME:acc#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#7.itm}
+load net {ACC1:acc.itm(3)} -pin  "FRAME:acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#7.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:acc#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:acc#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:acc#7" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load inst "FRAME:acc#9" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 53644 -attr oid 1700 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#9" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(4)} -pin  "FRAME:acc#9" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#9" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#9" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#9" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#9" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(4)} -pin  "FRAME:acc#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(5)} -pin  "FRAME:acc#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load inst "acc#30" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 53645 -attr oid 1701 -attr vt d -attr @path {/sobel/sobel:core/acc#30} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {FRAME:acc#9.itm(0)} -pin  "acc#30" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "acc#30" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "acc#30" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "acc#30" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(4)} -pin  "acc#30" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(5)} -pin  "acc#30" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {PWR} -pin  "acc#30" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#30" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#30" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#30" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#30" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#30" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#24.sva(0)} -pin  "acc#30" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load net {acc.imod#24.sva(1)} -pin  "acc#30" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load net {acc.imod#24.sva(2)} -pin  "acc#30" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load net {acc.imod#24.sva(3)} -pin  "acc#30" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load net {acc.imod#24.sva(4)} -pin  "acc#30" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load net {acc.imod#24.sva(5)} -pin  "acc#30" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load inst "ACC1:acc#416" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 53646 -attr oid 1702 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.regs:slc(regs.regs(2))#10.itm(0)} -pin  "ACC1:acc#416" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(1)} -pin  "ACC1:acc#416" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(2)} -pin  "ACC1:acc#416" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(3)} -pin  "ACC1:acc#416" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(4)} -pin  "ACC1:acc#416" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(5)} -pin  "ACC1:acc#416" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(6)} -pin  "ACC1:acc#416" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(7)} -pin  "ACC1:acc#416" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(8)} -pin  "ACC1:acc#416" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(9)} -pin  "ACC1:acc#416" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(0)} -pin  "ACC1:acc#416" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(1)} -pin  "ACC1:acc#416" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(2)} -pin  "ACC1:acc#416" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(3)} -pin  "ACC1:acc#416" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(4)} -pin  "ACC1:acc#416" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(5)} -pin  "ACC1:acc#416" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(6)} -pin  "ACC1:acc#416" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(7)} -pin  "ACC1:acc#416" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(8)} -pin  "ACC1:acc#416" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(9)} -pin  "ACC1:acc#416" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {ACC1:acc#416.itm(0)} -pin  "ACC1:acc#416" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(1)} -pin  "ACC1:acc#416" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(2)} -pin  "ACC1:acc#416" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(3)} -pin  "ACC1:acc#416" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(4)} -pin  "ACC1:acc#416" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(5)} -pin  "ACC1:acc#416" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(6)} -pin  "ACC1:acc#416" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(7)} -pin  "ACC1:acc#416" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(8)} -pin  "ACC1:acc#416" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(9)} -pin  "ACC1:acc#416" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(10)} -pin  "ACC1:acc#416" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load inst "ACC1-3:acc#20" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 53647 -attr oid 1703 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#20} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#416.itm(0)} -pin  "ACC1-3:acc#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(1)} -pin  "ACC1-3:acc#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(2)} -pin  "ACC1-3:acc#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(3)} -pin  "ACC1-3:acc#20" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(4)} -pin  "ACC1-3:acc#20" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(5)} -pin  "ACC1-3:acc#20" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(6)} -pin  "ACC1-3:acc#20" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(7)} -pin  "ACC1-3:acc#20" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(8)} -pin  "ACC1-3:acc#20" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(9)} -pin  "ACC1-3:acc#20" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(10)} -pin  "ACC1-3:acc#20" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(0)} -pin  "ACC1-3:acc#20" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(1)} -pin  "ACC1-3:acc#20" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(2)} -pin  "ACC1-3:acc#20" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(3)} -pin  "ACC1-3:acc#20" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(4)} -pin  "ACC1-3:acc#20" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(5)} -pin  "ACC1-3:acc#20" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(6)} -pin  "ACC1-3:acc#20" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(7)} -pin  "ACC1-3:acc#20" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(8)} -pin  "ACC1-3:acc#20" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(9)} -pin  "ACC1-3:acc#20" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {acc#20.psp#1.sva(0)} -pin  "ACC1-3:acc#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(1)} -pin  "ACC1-3:acc#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(2)} -pin  "ACC1-3:acc#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(3)} -pin  "ACC1-3:acc#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(4)} -pin  "ACC1-3:acc#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(5)} -pin  "ACC1-3:acc#20" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(6)} -pin  "ACC1-3:acc#20" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1-3:acc#20" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(8)} -pin  "ACC1-3:acc#20" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1-3:acc#20" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1-3:acc#20" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1-3:acc#20" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load inst "ACC1:not#309" "not(10)" "INTERFACE" -attr xrf 53648 -attr oid 1704 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {reg(regs.regs(0).sva).cse(0)} -pin  "ACC1:not#309" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(1)} -pin  "ACC1:not#309" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(2)} -pin  "ACC1:not#309" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(3)} -pin  "ACC1:not#309" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(4)} -pin  "ACC1:not#309" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(5)} -pin  "ACC1:not#309" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(6)} -pin  "ACC1:not#309" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(7)} -pin  "ACC1:not#309" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(8)} -pin  "ACC1:not#309" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(9)} -pin  "ACC1:not#309" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {ACC1:not#309.itm(0)} -pin  "ACC1:not#309" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(1)} -pin  "ACC1:not#309" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(2)} -pin  "ACC1:not#309" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(3)} -pin  "ACC1:not#309" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(4)} -pin  "ACC1:not#309" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(5)} -pin  "ACC1:not#309" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(6)} -pin  "ACC1:not#309" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(7)} -pin  "ACC1:not#309" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(8)} -pin  "ACC1:not#309" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(9)} -pin  "ACC1:not#309" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load inst "ACC1:not#310" "not(10)" "INTERFACE" -attr xrf 53649 -attr oid 1705 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {reg(regs.regs(0).sva).cse(10)} -pin  "ACC1:not#310" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(11)} -pin  "ACC1:not#310" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(12)} -pin  "ACC1:not#310" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(13)} -pin  "ACC1:not#310" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(14)} -pin  "ACC1:not#310" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(15)} -pin  "ACC1:not#310" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(16)} -pin  "ACC1:not#310" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(17)} -pin  "ACC1:not#310" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(18)} -pin  "ACC1:not#310" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(19)} -pin  "ACC1:not#310" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {ACC1:not#310.itm(0)} -pin  "ACC1:not#310" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(1)} -pin  "ACC1:not#310" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(2)} -pin  "ACC1:not#310" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(3)} -pin  "ACC1:not#310" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(4)} -pin  "ACC1:not#310" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(5)} -pin  "ACC1:not#310" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(6)} -pin  "ACC1:not#310" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(7)} -pin  "ACC1:not#310" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(8)} -pin  "ACC1:not#310" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(9)} -pin  "ACC1:not#310" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load inst "ACC1:acc#370" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 53650 -attr oid 1706 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#309.itm(0)} -pin  "ACC1:acc#370" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(1)} -pin  "ACC1:acc#370" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(2)} -pin  "ACC1:acc#370" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(3)} -pin  "ACC1:acc#370" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(4)} -pin  "ACC1:acc#370" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(5)} -pin  "ACC1:acc#370" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(6)} -pin  "ACC1:acc#370" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(7)} -pin  "ACC1:acc#370" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(8)} -pin  "ACC1:acc#370" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(9)} -pin  "ACC1:acc#370" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#310.itm(0)} -pin  "ACC1:acc#370" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(1)} -pin  "ACC1:acc#370" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(2)} -pin  "ACC1:acc#370" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(3)} -pin  "ACC1:acc#370" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(4)} -pin  "ACC1:acc#370" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(5)} -pin  "ACC1:acc#370" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(6)} -pin  "ACC1:acc#370" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(7)} -pin  "ACC1:acc#370" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(8)} -pin  "ACC1:acc#370" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(9)} -pin  "ACC1:acc#370" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:acc#370.itm(0)} -pin  "ACC1:acc#370" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(1)} -pin  "ACC1:acc#370" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(2)} -pin  "ACC1:acc#370" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(3)} -pin  "ACC1:acc#370" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(4)} -pin  "ACC1:acc#370" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(5)} -pin  "ACC1:acc#370" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(6)} -pin  "ACC1:acc#370" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(7)} -pin  "ACC1:acc#370" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(8)} -pin  "ACC1:acc#370" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(9)} -pin  "ACC1:acc#370" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(10)} -pin  "ACC1:acc#370" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load inst "ACC1:not#311" "not(10)" "INTERFACE" -attr xrf 53651 -attr oid 1707 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {reg(regs.regs(0).sva).cse(20)} -pin  "ACC1:not#311" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(21)} -pin  "ACC1:not#311" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(22)} -pin  "ACC1:not#311" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(23)} -pin  "ACC1:not#311" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(24)} -pin  "ACC1:not#311" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(25)} -pin  "ACC1:not#311" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(26)} -pin  "ACC1:not#311" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(27)} -pin  "ACC1:not#311" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(28)} -pin  "ACC1:not#311" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(29)} -pin  "ACC1:not#311" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {ACC1:not#311.itm(0)} -pin  "ACC1:not#311" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(1)} -pin  "ACC1:not#311" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(2)} -pin  "ACC1:not#311" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(3)} -pin  "ACC1:not#311" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(4)} -pin  "ACC1:not#311" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(5)} -pin  "ACC1:not#311" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(6)} -pin  "ACC1:not#311" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(7)} -pin  "ACC1:not#311" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(8)} -pin  "ACC1:not#311" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(9)} -pin  "ACC1:not#311" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load inst "ACC1:acc#369" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 53652 -attr oid 1708 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#311.itm(0)} -pin  "ACC1:acc#369" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(1)} -pin  "ACC1:acc#369" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(2)} -pin  "ACC1:acc#369" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(3)} -pin  "ACC1:acc#369" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(4)} -pin  "ACC1:acc#369" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(5)} -pin  "ACC1:acc#369" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(6)} -pin  "ACC1:acc#369" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(7)} -pin  "ACC1:acc#369" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(8)} -pin  "ACC1:acc#369" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(9)} -pin  "ACC1:acc#369" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {PWR} -pin  "ACC1:acc#369" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#369" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#369.itm(0)} -pin  "ACC1:acc#369" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(1)} -pin  "ACC1:acc#369" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(2)} -pin  "ACC1:acc#369" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(3)} -pin  "ACC1:acc#369" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(4)} -pin  "ACC1:acc#369" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(5)} -pin  "ACC1:acc#369" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(6)} -pin  "ACC1:acc#369" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(7)} -pin  "ACC1:acc#369" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(8)} -pin  "ACC1:acc#369" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(9)} -pin  "ACC1:acc#369" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(10)} -pin  "ACC1:acc#369" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load inst "ACC1:acc#228" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 53653 -attr oid 1709 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#370.itm(0)} -pin  "ACC1:acc#228" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(1)} -pin  "ACC1:acc#228" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(2)} -pin  "ACC1:acc#228" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(3)} -pin  "ACC1:acc#228" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(4)} -pin  "ACC1:acc#228" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(5)} -pin  "ACC1:acc#228" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(6)} -pin  "ACC1:acc#228" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(7)} -pin  "ACC1:acc#228" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(8)} -pin  "ACC1:acc#228" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(9)} -pin  "ACC1:acc#228" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(10)} -pin  "ACC1:acc#228" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#369.itm(0)} -pin  "ACC1:acc#228" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(1)} -pin  "ACC1:acc#228" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(2)} -pin  "ACC1:acc#228" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(3)} -pin  "ACC1:acc#228" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(4)} -pin  "ACC1:acc#228" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(5)} -pin  "ACC1:acc#228" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(6)} -pin  "ACC1:acc#228" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(7)} -pin  "ACC1:acc#228" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(8)} -pin  "ACC1:acc#228" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(9)} -pin  "ACC1:acc#228" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(10)} -pin  "ACC1:acc#228" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#228.psp.sva(0)} -pin  "ACC1:acc#228" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(1)} -pin  "ACC1:acc#228" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(2)} -pin  "ACC1:acc#228" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(3)} -pin  "ACC1:acc#228" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(4)} -pin  "ACC1:acc#228" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(5)} -pin  "ACC1:acc#228" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(6)} -pin  "ACC1:acc#228" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(7)} -pin  "ACC1:acc#228" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(8)} -pin  "ACC1:acc#228" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(9)} -pin  "ACC1:acc#228" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(10)} -pin  "ACC1:acc#228" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#228" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load inst "ACC1:acc#360" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 53654 -attr oid 1710 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "ACC1:acc#360" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "ACC1:acc#360" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "ACC1:acc#360" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "ACC1:acc#360" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "ACC1:acc#360" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "ACC1:acc#360" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "ACC1:acc#360" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "ACC1:acc#360" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "ACC1:acc#360" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:acc#360" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "ACC1:acc#360" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "ACC1:acc#360" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "ACC1:acc#360" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "ACC1:acc#360" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "ACC1:acc#360" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "ACC1:acc#360" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "ACC1:acc#360" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "ACC1:acc#360" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "ACC1:acc#360" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:acc#360" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {ACC1:acc#360.itm(0)} -pin  "ACC1:acc#360" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(1)} -pin  "ACC1:acc#360" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(2)} -pin  "ACC1:acc#360" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(3)} -pin  "ACC1:acc#360" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(4)} -pin  "ACC1:acc#360" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(5)} -pin  "ACC1:acc#360" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(6)} -pin  "ACC1:acc#360" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(7)} -pin  "ACC1:acc#360" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(8)} -pin  "ACC1:acc#360" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(9)} -pin  "ACC1:acc#360" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(10)} -pin  "ACC1:acc#360" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load inst "ACC1-1:acc#25" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 53655 -attr oid 1711 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#360.itm(0)} -pin  "ACC1-1:acc#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(1)} -pin  "ACC1-1:acc#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(2)} -pin  "ACC1-1:acc#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(3)} -pin  "ACC1-1:acc#25" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(4)} -pin  "ACC1-1:acc#25" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(5)} -pin  "ACC1-1:acc#25" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(6)} -pin  "ACC1-1:acc#25" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(7)} -pin  "ACC1-1:acc#25" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(8)} -pin  "ACC1-1:acc#25" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(9)} -pin  "ACC1-1:acc#25" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(10)} -pin  "ACC1-1:acc#25" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "ACC1-1:acc#25" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "ACC1-1:acc#25" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "ACC1-1:acc#25" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "ACC1-1:acc#25" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "ACC1-1:acc#25" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "ACC1-1:acc#25" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "ACC1-1:acc#25" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "ACC1-1:acc#25" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "ACC1-1:acc#25" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1-1:acc#25" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {ACC1-1:acc#25.psp.sva(0)} -pin  "ACC1-1:acc#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(1)} -pin  "ACC1-1:acc#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(2)} -pin  "ACC1-1:acc#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(3)} -pin  "ACC1-1:acc#25" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(4)} -pin  "ACC1-1:acc#25" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(5)} -pin  "ACC1-1:acc#25" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(6)} -pin  "ACC1-1:acc#25" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(7)} -pin  "ACC1-1:acc#25" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(8)} -pin  "ACC1-1:acc#25" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(9)} -pin  "ACC1-1:acc#25" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(10)} -pin  "ACC1-1:acc#25" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1-1:acc#25" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load inst "ACC1:acc#509" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53656 -attr oid 1712 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#509" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1059.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#509" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1059.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#509" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1047.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#509" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1047.itm}
+load net {ACC1:acc#509.cse(0)} -pin  "ACC1:acc#509" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(1)} -pin  "ACC1:acc#509" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(2)} -pin  "ACC1:acc#509" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load inst "regs.operator[]:not#5" "not(10)" "INTERFACE" -attr xrf 53657 -attr oid 1713 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs:slc(regs.regs(2)).itm(0)} -pin  "regs.operator[]:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(1)} -pin  "regs.operator[]:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(2)} -pin  "regs.operator[]:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(3)} -pin  "regs.operator[]:not#5" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(4)} -pin  "regs.operator[]:not#5" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(5)} -pin  "regs.operator[]:not#5" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(6)} -pin  "regs.operator[]:not#5" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(7)} -pin  "regs.operator[]:not#5" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(8)} -pin  "regs.operator[]:not#5" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(9)} -pin  "regs.operator[]:not#5" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.operator[]:not#5.itm(0)} -pin  "regs.operator[]:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(1)} -pin  "regs.operator[]:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(2)} -pin  "regs.operator[]:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(3)} -pin  "regs.operator[]:not#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(4)} -pin  "regs.operator[]:not#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(5)} -pin  "regs.operator[]:not#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(6)} -pin  "regs.operator[]:not#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(7)} -pin  "regs.operator[]:not#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(8)} -pin  "regs.operator[]:not#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(9)} -pin  "regs.operator[]:not#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load inst "regs.operator[]#1:not#5" "not(10)" "INTERFACE" -attr xrf 53658 -attr oid 1714 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs:slc(regs.regs(2))#1.itm(0)} -pin  "regs.operator[]#1:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(1)} -pin  "regs.operator[]#1:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(2)} -pin  "regs.operator[]#1:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(3)} -pin  "regs.operator[]#1:not#5" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(4)} -pin  "regs.operator[]#1:not#5" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(5)} -pin  "regs.operator[]#1:not#5" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(6)} -pin  "regs.operator[]#1:not#5" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(7)} -pin  "regs.operator[]#1:not#5" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(8)} -pin  "regs.operator[]#1:not#5" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(9)} -pin  "regs.operator[]#1:not#5" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.operator[]#1:not#5.itm(0)} -pin  "regs.operator[]#1:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(1)} -pin  "regs.operator[]#1:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(2)} -pin  "regs.operator[]#1:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(3)} -pin  "regs.operator[]#1:not#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(4)} -pin  "regs.operator[]#1:not#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(5)} -pin  "regs.operator[]#1:not#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(6)} -pin  "regs.operator[]#1:not#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(7)} -pin  "regs.operator[]#1:not#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(8)} -pin  "regs.operator[]#1:not#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(9)} -pin  "regs.operator[]#1:not#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load inst "ACC1:acc#398" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 53659 -attr oid 1715 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.operator[]:not#5.itm(0)} -pin  "ACC1:acc#398" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(1)} -pin  "ACC1:acc#398" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(2)} -pin  "ACC1:acc#398" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(3)} -pin  "ACC1:acc#398" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(4)} -pin  "ACC1:acc#398" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(5)} -pin  "ACC1:acc#398" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(6)} -pin  "ACC1:acc#398" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(7)} -pin  "ACC1:acc#398" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(8)} -pin  "ACC1:acc#398" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(9)} -pin  "ACC1:acc#398" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(0)} -pin  "ACC1:acc#398" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(1)} -pin  "ACC1:acc#398" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(2)} -pin  "ACC1:acc#398" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(3)} -pin  "ACC1:acc#398" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(4)} -pin  "ACC1:acc#398" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(5)} -pin  "ACC1:acc#398" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(6)} -pin  "ACC1:acc#398" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(7)} -pin  "ACC1:acc#398" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(8)} -pin  "ACC1:acc#398" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(9)} -pin  "ACC1:acc#398" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {ACC1:acc#398.itm(0)} -pin  "ACC1:acc#398" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(1)} -pin  "ACC1:acc#398" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(2)} -pin  "ACC1:acc#398" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(3)} -pin  "ACC1:acc#398" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(4)} -pin  "ACC1:acc#398" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(5)} -pin  "ACC1:acc#398" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(6)} -pin  "ACC1:acc#398" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(7)} -pin  "ACC1:acc#398" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(8)} -pin  "ACC1:acc#398" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(9)} -pin  "ACC1:acc#398" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(10)} -pin  "ACC1:acc#398" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load inst "regs.operator[]#2:not#5" "not(10)" "INTERFACE" -attr xrf 53660 -attr oid 1716 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs:slc(regs.regs(2))#2.itm(0)} -pin  "regs.operator[]#2:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(1)} -pin  "regs.operator[]#2:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(2)} -pin  "regs.operator[]#2:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(3)} -pin  "regs.operator[]#2:not#5" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(4)} -pin  "regs.operator[]#2:not#5" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(5)} -pin  "regs.operator[]#2:not#5" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(6)} -pin  "regs.operator[]#2:not#5" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(7)} -pin  "regs.operator[]#2:not#5" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(8)} -pin  "regs.operator[]#2:not#5" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(9)} -pin  "regs.operator[]#2:not#5" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.operator[]#2:not#5.itm(0)} -pin  "regs.operator[]#2:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(1)} -pin  "regs.operator[]#2:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(2)} -pin  "regs.operator[]#2:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(3)} -pin  "regs.operator[]#2:not#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(4)} -pin  "regs.operator[]#2:not#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(5)} -pin  "regs.operator[]#2:not#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(6)} -pin  "regs.operator[]#2:not#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(7)} -pin  "regs.operator[]#2:not#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(8)} -pin  "regs.operator[]#2:not#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(9)} -pin  "regs.operator[]#2:not#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load inst "ACC1:acc#397" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 53661 -attr oid 1717 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.operator[]#2:not#5.itm(0)} -pin  "ACC1:acc#397" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(1)} -pin  "ACC1:acc#397" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(2)} -pin  "ACC1:acc#397" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(3)} -pin  "ACC1:acc#397" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(4)} -pin  "ACC1:acc#397" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(5)} -pin  "ACC1:acc#397" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(6)} -pin  "ACC1:acc#397" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(7)} -pin  "ACC1:acc#397" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(8)} -pin  "ACC1:acc#397" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(9)} -pin  "ACC1:acc#397" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {PWR} -pin  "ACC1:acc#397" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#397" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#397.itm(0)} -pin  "ACC1:acc#397" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(1)} -pin  "ACC1:acc#397" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(2)} -pin  "ACC1:acc#397" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(3)} -pin  "ACC1:acc#397" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(4)} -pin  "ACC1:acc#397" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(5)} -pin  "ACC1:acc#397" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(6)} -pin  "ACC1:acc#397" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(7)} -pin  "ACC1:acc#397" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(8)} -pin  "ACC1:acc#397" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(9)} -pin  "ACC1:acc#397" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(10)} -pin  "ACC1:acc#397" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load inst "ACC1:acc#227" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 53662 -attr oid 1718 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#398.itm(0)} -pin  "ACC1:acc#227" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(1)} -pin  "ACC1:acc#227" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(2)} -pin  "ACC1:acc#227" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(3)} -pin  "ACC1:acc#227" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(4)} -pin  "ACC1:acc#227" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(5)} -pin  "ACC1:acc#227" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(6)} -pin  "ACC1:acc#227" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(7)} -pin  "ACC1:acc#227" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(8)} -pin  "ACC1:acc#227" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(9)} -pin  "ACC1:acc#227" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(10)} -pin  "ACC1:acc#227" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#397.itm(0)} -pin  "ACC1:acc#227" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(1)} -pin  "ACC1:acc#227" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(2)} -pin  "ACC1:acc#227" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(3)} -pin  "ACC1:acc#227" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(4)} -pin  "ACC1:acc#227" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(5)} -pin  "ACC1:acc#227" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(6)} -pin  "ACC1:acc#227" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(7)} -pin  "ACC1:acc#227" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(8)} -pin  "ACC1:acc#227" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(9)} -pin  "ACC1:acc#227" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(10)} -pin  "ACC1:acc#227" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#227.psp.sva(0)} -pin  "ACC1:acc#227" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(1)} -pin  "ACC1:acc#227" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(2)} -pin  "ACC1:acc#227" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(3)} -pin  "ACC1:acc#227" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(4)} -pin  "ACC1:acc#227" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(5)} -pin  "ACC1:acc#227" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(6)} -pin  "ACC1:acc#227" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(7)} -pin  "ACC1:acc#227" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(8)} -pin  "ACC1:acc#227" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(9)} -pin  "ACC1:acc#227" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(10)} -pin  "ACC1:acc#227" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#227" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load inst "ACC1:acc#506" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53663 -attr oid 1719 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#506" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1056.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#506" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1056.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#506" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1043.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#506" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1043.itm}
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#506" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#506" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#506" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load inst "ACC1:acc#562" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53664 -attr oid 1720 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#562" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#562" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#562" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#562" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#562" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#562" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#562.ncse(0)} -pin  "ACC1:acc#562" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(1)} -pin  "ACC1:acc#562" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(2)} -pin  "ACC1:acc#562" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(3)} -pin  "ACC1:acc#562" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load inst "ACC1:acc#502" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53665 -attr oid 1721 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#20.psp#1.sva(5)} -pin  "ACC1:acc#502" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#963.itm}
+load net {acc#20.psp#1.sva(5)} -pin  "ACC1:acc#502" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#963.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#502" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1055.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#502" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1055.itm}
+load net {ACC1:acc#502.cse(0)} -pin  "ACC1:acc#502" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#502.cse(1)} -pin  "ACC1:acc#502" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#502.cse(2)} -pin  "ACC1:acc#502" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load inst "ACC1:acc#489" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53666 -attr oid 1722 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#489" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1059.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#489" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1059.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#489" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1047.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#489" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1047.itm}
+load net {ACC1:acc#489.cse(0)} -pin  "ACC1:acc#489" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(1)} -pin  "ACC1:acc#489" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(2)} -pin  "ACC1:acc#489" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load inst "ACC1:acc#379" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 53667 -attr oid 1723 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {reg(regs.regs(0).sva).cse(70)} -pin  "ACC1:acc#379" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(71)} -pin  "ACC1:acc#379" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(72)} -pin  "ACC1:acc#379" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(73)} -pin  "ACC1:acc#379" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(74)} -pin  "ACC1:acc#379" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(75)} -pin  "ACC1:acc#379" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(76)} -pin  "ACC1:acc#379" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(77)} -pin  "ACC1:acc#379" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(78)} -pin  "ACC1:acc#379" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(79)} -pin  "ACC1:acc#379" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(60)} -pin  "ACC1:acc#379" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(61)} -pin  "ACC1:acc#379" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(62)} -pin  "ACC1:acc#379" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(63)} -pin  "ACC1:acc#379" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(64)} -pin  "ACC1:acc#379" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(65)} -pin  "ACC1:acc#379" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(66)} -pin  "ACC1:acc#379" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(67)} -pin  "ACC1:acc#379" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(68)} -pin  "ACC1:acc#379" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(69)} -pin  "ACC1:acc#379" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {ACC1:acc#379.itm(0)} -pin  "ACC1:acc#379" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(1)} -pin  "ACC1:acc#379" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(2)} -pin  "ACC1:acc#379" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(3)} -pin  "ACC1:acc#379" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(4)} -pin  "ACC1:acc#379" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(5)} -pin  "ACC1:acc#379" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(6)} -pin  "ACC1:acc#379" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(7)} -pin  "ACC1:acc#379" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(8)} -pin  "ACC1:acc#379" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(9)} -pin  "ACC1:acc#379" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(10)} -pin  "ACC1:acc#379" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load inst "ACC1:acc#226" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 53668 -attr oid 1724 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#379.itm(0)} -pin  "ACC1:acc#226" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(1)} -pin  "ACC1:acc#226" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(2)} -pin  "ACC1:acc#226" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(3)} -pin  "ACC1:acc#226" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(4)} -pin  "ACC1:acc#226" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(5)} -pin  "ACC1:acc#226" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(6)} -pin  "ACC1:acc#226" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(7)} -pin  "ACC1:acc#226" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(8)} -pin  "ACC1:acc#226" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(9)} -pin  "ACC1:acc#226" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(10)} -pin  "ACC1:acc#226" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {reg(regs.regs(0).sva).cse(80)} -pin  "ACC1:acc#226" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(81)} -pin  "ACC1:acc#226" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(82)} -pin  "ACC1:acc#226" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(83)} -pin  "ACC1:acc#226" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(84)} -pin  "ACC1:acc#226" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(85)} -pin  "ACC1:acc#226" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(86)} -pin  "ACC1:acc#226" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(87)} -pin  "ACC1:acc#226" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(88)} -pin  "ACC1:acc#226" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(89)} -pin  "ACC1:acc#226" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {ACC1:acc#226.psp.sva(0)} -pin  "ACC1:acc#226" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(1)} -pin  "ACC1:acc#226" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(2)} -pin  "ACC1:acc#226" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(3)} -pin  "ACC1:acc#226" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(4)} -pin  "ACC1:acc#226" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(5)} -pin  "ACC1:acc#226" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(6)} -pin  "ACC1:acc#226" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(7)} -pin  "ACC1:acc#226" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(8)} -pin  "ACC1:acc#226" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(9)} -pin  "ACC1:acc#226" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(10)} -pin  "ACC1:acc#226" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#226" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load inst "ACC1:acc#553" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53669 -attr oid 1725 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#489.cse(0)} -pin  "ACC1:acc#553" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(1)} -pin  "ACC1:acc#553" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(2)} -pin  "ACC1:acc#553" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(0)} -pin  "ACC1:acc#553" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(1)} -pin  "ACC1:acc#553" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(2)} -pin  "ACC1:acc#553" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#553.ncse(0)} -pin  "ACC1:acc#553" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(1)} -pin  "ACC1:acc#553" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(2)} -pin  "ACC1:acc#553" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(3)} -pin  "ACC1:acc#553" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load inst "ACC1-1:not#60" "not(1)" "INTERFACE" -attr xrf 53670 -attr oid 1726 -attr @path {/sobel/sobel:core/ACC1-1:not#60} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#339.itm(2)} -pin  "ACC1-1:not#60" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#32.sva)#2.itm}
+load net {ACC1-1:not#60.itm} -pin  "ACC1-1:not#60" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#60.itm}
+load inst "ACC1-1:and#3" "and(3,1)" "INTERFACE" -attr xrf 53671 -attr oid 1727 -attr @path {/sobel/sobel:core/ACC1-1:and#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#50.itm}
+load net {ACC1-1:not#60.itm} -pin  "ACC1-1:and#3" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#60.itm}
+load net {ACC1:acc#339.itm(1)} -pin  "ACC1-1:and#3" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#32.sva)#1.itm}
+load net {ACC1-1:and#3.cse.sva} -pin  "ACC1-1:and#3" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#3.cse.sva}
+load inst "ACC1-1:not#319" "not(1)" "INTERFACE" -attr xrf 53672 -attr oid 1728 -attr @path {/sobel/sobel:core/ACC1-1:not#319} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:not#319" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#71.itm}
+load net {ACC1-1:not#319.itm} -pin  "ACC1-1:not#319" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#319.itm}
+load inst "ACC1-1:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 53673 -attr oid 1729 -attr vt c -attr @path {/sobel/sobel:core/ACC1-1:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#339.itm(2)} -pin  "ACC1-1:nand#1" {A0(0)} -attr vt c -attr @path {/sobel/sobel:core/slc(acc.imod#32.sva).itm}
+load net {ACC1-1:not#319.itm} -pin  "ACC1-1:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#319.itm}
+load net {ACC1-1:nand#1.cse.sva} -pin  "ACC1-1:nand#1" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/ACC1-1:nand#1.cse.sva}
+load inst "ACC1:acc#388" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 53674 -attr oid 1730 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.regs:slc(regs.regs(2))#1.itm(0)} -pin  "ACC1:acc#388" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(1)} -pin  "ACC1:acc#388" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(2)} -pin  "ACC1:acc#388" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(3)} -pin  "ACC1:acc#388" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(4)} -pin  "ACC1:acc#388" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(5)} -pin  "ACC1:acc#388" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(6)} -pin  "ACC1:acc#388" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(7)} -pin  "ACC1:acc#388" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(8)} -pin  "ACC1:acc#388" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(9)} -pin  "ACC1:acc#388" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(0)} -pin  "ACC1:acc#388" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(1)} -pin  "ACC1:acc#388" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(2)} -pin  "ACC1:acc#388" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(3)} -pin  "ACC1:acc#388" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(4)} -pin  "ACC1:acc#388" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(5)} -pin  "ACC1:acc#388" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(6)} -pin  "ACC1:acc#388" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(7)} -pin  "ACC1:acc#388" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(8)} -pin  "ACC1:acc#388" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(9)} -pin  "ACC1:acc#388" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {ACC1:acc#388.itm(0)} -pin  "ACC1:acc#388" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(1)} -pin  "ACC1:acc#388" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(2)} -pin  "ACC1:acc#388" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(3)} -pin  "ACC1:acc#388" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(4)} -pin  "ACC1:acc#388" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(5)} -pin  "ACC1:acc#388" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(6)} -pin  "ACC1:acc#388" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(7)} -pin  "ACC1:acc#388" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(8)} -pin  "ACC1:acc#388" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(9)} -pin  "ACC1:acc#388" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(10)} -pin  "ACC1:acc#388" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load inst "ACC1-3:acc" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 53675 -attr oid 1731 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#388.itm(0)} -pin  "ACC1-3:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(1)} -pin  "ACC1-3:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(2)} -pin  "ACC1-3:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(3)} -pin  "ACC1-3:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(4)} -pin  "ACC1-3:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(5)} -pin  "ACC1-3:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(6)} -pin  "ACC1-3:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(7)} -pin  "ACC1-3:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(8)} -pin  "ACC1-3:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(9)} -pin  "ACC1-3:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(10)} -pin  "ACC1-3:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {regs.regs:slc(regs.regs(2)).itm(0)} -pin  "ACC1-3:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(1)} -pin  "ACC1-3:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(2)} -pin  "ACC1-3:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(3)} -pin  "ACC1-3:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(4)} -pin  "ACC1-3:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(5)} -pin  "ACC1-3:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(6)} -pin  "ACC1-3:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(7)} -pin  "ACC1-3:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(8)} -pin  "ACC1-3:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(9)} -pin  "ACC1-3:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {acc.psp#1.sva(0)} -pin  "ACC1-3:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(1)} -pin  "ACC1-3:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(2)} -pin  "ACC1-3:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(3)} -pin  "ACC1-3:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(4)} -pin  "ACC1-3:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(5)} -pin  "ACC1-3:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(6)} -pin  "ACC1-3:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(7)} -pin  "ACC1-3:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(8)} -pin  "ACC1-3:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(9)} -pin  "ACC1-3:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(10)} -pin  "ACC1-3:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load inst "ACC1-1:not#293" "not(2)" "INTERFACE" -attr xrf 53676 -attr oid 1732 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:not#293} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#220.psp#1.sva(1)} -pin  "ACC1-1:not#293" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva).itm}
+load net {ACC1:acc#220.psp#1.sva(2)} -pin  "ACC1-1:not#293" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva).itm}
+load net {ACC1-1:not#293.itm(0)} -pin  "ACC1-1:not#293" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:not#293.itm}
+load net {ACC1-1:not#293.itm(1)} -pin  "ACC1-1:not#293" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:not#293.itm}
+load inst "ACC1:acc#338" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 53677 -attr oid 1733 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#338} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#338" {A(0)} -attr @path {/sobel/sobel:core/conc#1004.itm}
+load net {ACC1-1:not#293.itm(0)} -pin  "ACC1:acc#338" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1004.itm}
+load net {ACC1-1:not#293.itm(1)} -pin  "ACC1:acc#338" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1004.itm}
+load net {PWR} -pin  "ACC1:acc#338" {B(0)} -attr @path {/sobel/sobel:core/conc#1005.itm}
+load net {ACC1:acc#220.psp#1.sva(0)} -pin  "ACC1:acc#338" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1005.itm}
+load net {ACC1:acc#338.itm(0)} -pin  "ACC1:acc#338" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(1)} -pin  "ACC1:acc#338" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(2)} -pin  "ACC1:acc#338" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(3)} -pin  "ACC1:acc#338" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load inst "ACC1-1:not#311" "not(1)" "INTERFACE" -attr xrf 53678 -attr oid 1734 -attr @path {/sobel/sobel:core/ACC1-1:not#311} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:not#311" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#51.itm}
+load net {ACC1-1:not#311.itm} -pin  "ACC1-1:not#311" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#311.itm}
+load inst "ACC1-1:not#229" "not(1)" "INTERFACE" -attr xrf 53679 -attr oid 1735 -attr @path {/sobel/sobel:core/ACC1-1:not#229} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(1)} -pin  "ACC1-1:not#229" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#17.itm}
+load net {ACC1-1:not#229.itm} -pin  "ACC1-1:not#229" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#229.itm}
+load inst "ACC1:acc#334" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 53680 -attr oid 1736 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#334" {A(0)} -attr @path {/sobel/sobel:core/conc#1007.itm}
+load net {ACC1-1:not#311.itm} -pin  "ACC1:acc#334" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1007.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#334" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1133.itm}
+load net {ACC1-1:not#229.itm} -pin  "ACC1:acc#334" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1133.itm}
+load net {ACC1:acc#334.itm(0)} -pin  "ACC1:acc#334" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(1)} -pin  "ACC1:acc#334" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(2)} -pin  "ACC1:acc#334" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(3)} -pin  "ACC1:acc#334" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load inst "ACC1:acc#336" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 53681 -attr oid 1737 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#336" {A(0)} -attr @path {/sobel/sobel:core/conc#1006.itm}
+load net {ACC1:acc#334.itm(1)} -pin  "ACC1:acc#336" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1006.itm}
+load net {ACC1:acc#334.itm(2)} -pin  "ACC1:acc#336" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1006.itm}
+load net {ACC1:acc#334.itm(3)} -pin  "ACC1:acc#336" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1006.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#336" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1008.itm}
+load net {acc.psp#2.sva(0)} -pin  "ACC1:acc#336" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1008.itm}
+load net {GND} -pin  "ACC1:acc#336" {B(2)} -attr @path {/sobel/sobel:core/conc#1008.itm}
+load net {PWR} -pin  "ACC1:acc#336" {B(3)} -attr @path {/sobel/sobel:core/conc#1008.itm}
+load net {ACC1:acc#336.itm(0)} -pin  "ACC1:acc#336" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(1)} -pin  "ACC1:acc#336" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(2)} -pin  "ACC1:acc#336" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(3)} -pin  "ACC1:acc#336" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(4)} -pin  "ACC1:acc#336" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load inst "ACC1-1:not#230" "not(1)" "INTERFACE" -attr xrf 53682 -attr oid 1738 -attr @path {/sobel/sobel:core/ACC1-1:not#230} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(3)} -pin  "ACC1-1:not#230" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#16.itm}
+load net {ACC1-1:not#230.itm} -pin  "ACC1-1:not#230" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#230.itm}
+load inst "ACC1-1:not#232" "not(1)" "INTERFACE" -attr xrf 53683 -attr oid 1739 -attr @path {/sobel/sobel:core/ACC1-1:not#232} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(7)} -pin  "ACC1-1:not#232" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#6.itm}
+load net {ACC1-1:not#232.itm} -pin  "ACC1-1:not#232" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#232.itm}
+load inst "ACC1:acc#333" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53684 -attr oid 1740 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#333} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#333" {A(0)} -attr @path {/sobel/sobel:core/conc#1010.itm}
+load net {acc.psp#2.sva(2)} -pin  "ACC1:acc#333" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1010.itm}
+load net {ACC1-1:not#232.itm} -pin  "ACC1:acc#333" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1131.itm}
+load net {ACC1-1:not#230.itm} -pin  "ACC1:acc#333" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1131.itm}
+load net {ACC1:acc#333.itm(0)} -pin  "ACC1:acc#333" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(1)} -pin  "ACC1:acc#333" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(2)} -pin  "ACC1:acc#333" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load inst "ACC1-1:not#231" "not(1)" "INTERFACE" -attr xrf 53685 -attr oid 1741 -attr @path {/sobel/sobel:core/ACC1-1:not#231} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(5)} -pin  "ACC1-1:not#231" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#8.itm}
+load net {ACC1-1:not#231.itm} -pin  "ACC1-1:not#231" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#231.itm}
+load inst "ACC1:acc#332" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53686 -attr oid 1742 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#332" {A(0)} -attr @path {/sobel/sobel:core/conc#1011.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#332" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1011.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#332" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1129.itm}
+load net {ACC1-1:not#231.itm} -pin  "ACC1:acc#332" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1129.itm}
+load net {ACC1:acc#332.itm(0)} -pin  "ACC1:acc#332" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(1)} -pin  "ACC1:acc#332" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(2)} -pin  "ACC1:acc#332" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load inst "ACC1-1:not#233" "not(1)" "INTERFACE" -attr xrf 53687 -attr oid 1743 -attr @path {/sobel/sobel:core/ACC1-1:not#233} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(9)} -pin  "ACC1-1:not#233" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#93.itm}
+load net {ACC1-1:not#233.itm} -pin  "ACC1-1:not#233" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#233.itm}
+load inst "ACC1:acc#335" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53688 -attr oid 1744 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#335} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#335" {A(0)} -attr @path {/sobel/sobel:core/conc#1009.itm}
+load net {ACC1:acc#333.itm(1)} -pin  "ACC1:acc#335" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1009.itm}
+load net {ACC1:acc#333.itm(2)} -pin  "ACC1:acc#335" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1009.itm}
+load net {ACC1-1:not#233.itm} -pin  "ACC1:acc#335" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1135.itm}
+load net {ACC1:acc#332.itm(1)} -pin  "ACC1:acc#335" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1135.itm}
+load net {ACC1:acc#332.itm(2)} -pin  "ACC1:acc#335" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1135.itm}
+load net {ACC1:acc#335.itm(0)} -pin  "ACC1:acc#335" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(1)} -pin  "ACC1:acc#335" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(2)} -pin  "ACC1:acc#335" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(3)} -pin  "ACC1:acc#335" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load inst "ACC1-1:acc#210" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 53689 -attr oid 1745 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#210} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#336.itm(1)} -pin  "ACC1-1:acc#210" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#17.itm}
+load net {ACC1:acc#336.itm(2)} -pin  "ACC1-1:acc#210" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#17.itm}
+load net {ACC1:acc#336.itm(3)} -pin  "ACC1-1:acc#210" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#17.itm}
+load net {ACC1:acc#336.itm(4)} -pin  "ACC1-1:acc#210" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#17.itm}
+load net {ACC1:acc#335.itm(1)} -pin  "ACC1-1:acc#210" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#16.itm}
+load net {ACC1:acc#335.itm(2)} -pin  "ACC1-1:acc#210" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#16.itm}
+load net {ACC1:acc#335.itm(3)} -pin  "ACC1-1:acc#210" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#16.itm}
+load net {ACC1:acc#210.psp#2.sva(0)} -pin  "ACC1-1:acc#210" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#2.sva}
+load net {ACC1:acc#210.psp#2.sva(1)} -pin  "ACC1-1:acc#210" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#2.sva}
+load net {ACC1:acc#210.psp#2.sva(2)} -pin  "ACC1-1:acc#210" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#2.sva}
+load net {ACC1:acc#210.psp#2.sva(3)} -pin  "ACC1-1:acc#210" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#2.sva}
+load inst "regs.operator[]:not" "not(10)" "INTERFACE" -attr xrf 53690 -attr oid 1746 -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "regs.operator[]:not" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "regs.operator[]:not" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "regs.operator[]:not" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "regs.operator[]:not" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "regs.operator[]:not" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "regs.operator[]:not" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "regs.operator[]:not" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "regs.operator[]:not" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "regs.operator[]:not" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "regs.operator[]:not" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {regs.operator[]:not.itm(0)} -pin  "regs.operator[]:not" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(1)} -pin  "regs.operator[]:not" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(2)} -pin  "regs.operator[]:not" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(3)} -pin  "regs.operator[]:not" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(4)} -pin  "regs.operator[]:not" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(5)} -pin  "regs.operator[]:not" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(6)} -pin  "regs.operator[]:not" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(7)} -pin  "regs.operator[]:not" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(8)} -pin  "regs.operator[]:not" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(9)} -pin  "regs.operator[]:not" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load inst "regs.operator[]#1:not" "not(10)" "INTERFACE" -attr xrf 53691 -attr oid 1747 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "regs.operator[]#1:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "regs.operator[]#1:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "regs.operator[]#1:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "regs.operator[]#1:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "regs.operator[]#1:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "regs.operator[]#1:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "regs.operator[]#1:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "regs.operator[]#1:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "regs.operator[]#1:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "regs.operator[]#1:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {regs.operator[]#1:not.itm(0)} -pin  "regs.operator[]#1:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(1)} -pin  "regs.operator[]#1:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(2)} -pin  "regs.operator[]#1:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(3)} -pin  "regs.operator[]#1:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(4)} -pin  "regs.operator[]#1:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(5)} -pin  "regs.operator[]#1:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(6)} -pin  "regs.operator[]#1:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(7)} -pin  "regs.operator[]#1:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(8)} -pin  "regs.operator[]#1:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(9)} -pin  "regs.operator[]#1:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load inst "ACC1:acc#331" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 53692 -attr oid 1748 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.operator[]:not.itm(0)} -pin  "ACC1:acc#331" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(1)} -pin  "ACC1:acc#331" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(2)} -pin  "ACC1:acc#331" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(3)} -pin  "ACC1:acc#331" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(4)} -pin  "ACC1:acc#331" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(5)} -pin  "ACC1:acc#331" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(6)} -pin  "ACC1:acc#331" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(7)} -pin  "ACC1:acc#331" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(8)} -pin  "ACC1:acc#331" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(9)} -pin  "ACC1:acc#331" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]#1:not.itm(0)} -pin  "ACC1:acc#331" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(1)} -pin  "ACC1:acc#331" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(2)} -pin  "ACC1:acc#331" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(3)} -pin  "ACC1:acc#331" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(4)} -pin  "ACC1:acc#331" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(5)} -pin  "ACC1:acc#331" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(6)} -pin  "ACC1:acc#331" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(7)} -pin  "ACC1:acc#331" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(8)} -pin  "ACC1:acc#331" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(9)} -pin  "ACC1:acc#331" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {ACC1:acc#331.itm(0)} -pin  "ACC1:acc#331" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(1)} -pin  "ACC1:acc#331" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(2)} -pin  "ACC1:acc#331" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(3)} -pin  "ACC1:acc#331" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(4)} -pin  "ACC1:acc#331" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(5)} -pin  "ACC1:acc#331" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(6)} -pin  "ACC1:acc#331" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(7)} -pin  "ACC1:acc#331" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(8)} -pin  "ACC1:acc#331" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(9)} -pin  "ACC1:acc#331" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(10)} -pin  "ACC1:acc#331" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load inst "regs.operator[]#2:not" "not(10)" "INTERFACE" -attr xrf 53693 -attr oid 1749 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "regs.operator[]#2:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "regs.operator[]#2:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "regs.operator[]#2:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "regs.operator[]#2:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "regs.operator[]#2:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "regs.operator[]#2:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "regs.operator[]#2:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "regs.operator[]#2:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "regs.operator[]#2:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "regs.operator[]#2:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {regs.operator[]#2:not.itm(0)} -pin  "regs.operator[]#2:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(1)} -pin  "regs.operator[]#2:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(2)} -pin  "regs.operator[]#2:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(3)} -pin  "regs.operator[]#2:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(4)} -pin  "regs.operator[]#2:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(5)} -pin  "regs.operator[]#2:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(6)} -pin  "regs.operator[]#2:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(7)} -pin  "regs.operator[]#2:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(8)} -pin  "regs.operator[]#2:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(9)} -pin  "regs.operator[]#2:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load inst "ACC1:acc#330" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 53694 -attr oid 1750 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.operator[]#2:not.itm(0)} -pin  "ACC1:acc#330" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(1)} -pin  "ACC1:acc#330" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(2)} -pin  "ACC1:acc#330" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(3)} -pin  "ACC1:acc#330" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(4)} -pin  "ACC1:acc#330" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(5)} -pin  "ACC1:acc#330" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(6)} -pin  "ACC1:acc#330" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(7)} -pin  "ACC1:acc#330" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(8)} -pin  "ACC1:acc#330" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(9)} -pin  "ACC1:acc#330" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {PWR} -pin  "ACC1:acc#330" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#330" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#330.itm(0)} -pin  "ACC1:acc#330" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(1)} -pin  "ACC1:acc#330" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(2)} -pin  "ACC1:acc#330" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(3)} -pin  "ACC1:acc#330" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(4)} -pin  "ACC1:acc#330" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(5)} -pin  "ACC1:acc#330" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(6)} -pin  "ACC1:acc#330" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(7)} -pin  "ACC1:acc#330" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(8)} -pin  "ACC1:acc#330" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(9)} -pin  "ACC1:acc#330" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(10)} -pin  "ACC1:acc#330" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load inst "ACC1-1:acc" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 53695 -attr oid 1751 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#331.itm(0)} -pin  "ACC1-1:acc" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(1)} -pin  "ACC1-1:acc" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(2)} -pin  "ACC1-1:acc" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(3)} -pin  "ACC1-1:acc" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(4)} -pin  "ACC1-1:acc" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(5)} -pin  "ACC1-1:acc" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(6)} -pin  "ACC1-1:acc" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(7)} -pin  "ACC1-1:acc" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(8)} -pin  "ACC1-1:acc" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(9)} -pin  "ACC1-1:acc" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(10)} -pin  "ACC1-1:acc" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#330.itm(0)} -pin  "ACC1-1:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(1)} -pin  "ACC1-1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(2)} -pin  "ACC1-1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(3)} -pin  "ACC1-1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(4)} -pin  "ACC1-1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(5)} -pin  "ACC1-1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(6)} -pin  "ACC1-1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(7)} -pin  "ACC1-1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(8)} -pin  "ACC1-1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(9)} -pin  "ACC1-1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(10)} -pin  "ACC1-1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {acc.psp#2.sva(0)} -pin  "ACC1-1:acc" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(1)} -pin  "ACC1-1:acc" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(2)} -pin  "ACC1-1:acc" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(3)} -pin  "ACC1-1:acc" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(4)} -pin  "ACC1-1:acc" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(5)} -pin  "ACC1-1:acc" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(6)} -pin  "ACC1-1:acc" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(7)} -pin  "ACC1-1:acc" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(8)} -pin  "ACC1-1:acc" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(9)} -pin  "ACC1-1:acc" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(10)} -pin  "ACC1-1:acc" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load inst "ACC1:not" "not(10)" "INTERFACE" -attr xrf 53696 -attr oid 1752 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "ACC1:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "ACC1:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "ACC1:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "ACC1:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "ACC1:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "ACC1:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "ACC1:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "ACC1:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "ACC1:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "ACC1:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load inst "ACC1:not#307" "not(10)" "INTERFACE" -attr xrf 53697 -attr oid 1753 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "ACC1:not#307" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "ACC1:not#307" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "ACC1:not#307" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "ACC1:not#307" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "ACC1:not#307" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "ACC1:not#307" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "ACC1:not#307" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "ACC1:not#307" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "ACC1:not#307" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "ACC1:not#307" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {ACC1:not#307.itm(0)} -pin  "ACC1:not#307" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(1)} -pin  "ACC1:not#307" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(2)} -pin  "ACC1:not#307" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(3)} -pin  "ACC1:not#307" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(4)} -pin  "ACC1:not#307" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(5)} -pin  "ACC1:not#307" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(6)} -pin  "ACC1:not#307" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(7)} -pin  "ACC1:not#307" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(8)} -pin  "ACC1:not#307" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(9)} -pin  "ACC1:not#307" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load inst "ACC1:acc#341" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 53698 -attr oid 1754 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not.itm(0)} -pin  "ACC1:acc#341" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:acc#341" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:acc#341" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:acc#341" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:acc#341" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:acc#341" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:acc#341" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:acc#341" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:acc#341" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:acc#341" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not#307.itm(0)} -pin  "ACC1:acc#341" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(1)} -pin  "ACC1:acc#341" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(2)} -pin  "ACC1:acc#341" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(3)} -pin  "ACC1:acc#341" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(4)} -pin  "ACC1:acc#341" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(5)} -pin  "ACC1:acc#341" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(6)} -pin  "ACC1:acc#341" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(7)} -pin  "ACC1:acc#341" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(8)} -pin  "ACC1:acc#341" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(9)} -pin  "ACC1:acc#341" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:acc#341.itm(0)} -pin  "ACC1:acc#341" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(1)} -pin  "ACC1:acc#341" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(2)} -pin  "ACC1:acc#341" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(3)} -pin  "ACC1:acc#341" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(4)} -pin  "ACC1:acc#341" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(5)} -pin  "ACC1:acc#341" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(6)} -pin  "ACC1:acc#341" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(7)} -pin  "ACC1:acc#341" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(8)} -pin  "ACC1:acc#341" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(9)} -pin  "ACC1:acc#341" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(10)} -pin  "ACC1:acc#341" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load inst "ACC1:not#308" "not(10)" "INTERFACE" -attr xrf 53699 -attr oid 1755 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "ACC1:not#308" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "ACC1:not#308" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "ACC1:not#308" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "ACC1:not#308" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "ACC1:not#308" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "ACC1:not#308" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "ACC1:not#308" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "ACC1:not#308" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "ACC1:not#308" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "ACC1:not#308" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:not#308.itm(0)} -pin  "ACC1:not#308" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(1)} -pin  "ACC1:not#308" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(2)} -pin  "ACC1:not#308" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(3)} -pin  "ACC1:not#308" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(4)} -pin  "ACC1:not#308" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(5)} -pin  "ACC1:not#308" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(6)} -pin  "ACC1:not#308" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(7)} -pin  "ACC1:not#308" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(8)} -pin  "ACC1:not#308" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(9)} -pin  "ACC1:not#308" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load inst "ACC1:acc#340" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 53700 -attr oid 1756 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#308.itm(0)} -pin  "ACC1:acc#340" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(1)} -pin  "ACC1:acc#340" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(2)} -pin  "ACC1:acc#340" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(3)} -pin  "ACC1:acc#340" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(4)} -pin  "ACC1:acc#340" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(5)} -pin  "ACC1:acc#340" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(6)} -pin  "ACC1:acc#340" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(7)} -pin  "ACC1:acc#340" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(8)} -pin  "ACC1:acc#340" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(9)} -pin  "ACC1:acc#340" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {PWR} -pin  "ACC1:acc#340" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#340" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#340.itm(0)} -pin  "ACC1:acc#340" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(1)} -pin  "ACC1:acc#340" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(2)} -pin  "ACC1:acc#340" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(3)} -pin  "ACC1:acc#340" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(4)} -pin  "ACC1:acc#340" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(5)} -pin  "ACC1:acc#340" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(6)} -pin  "ACC1:acc#340" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(7)} -pin  "ACC1:acc#340" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(8)} -pin  "ACC1:acc#340" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(9)} -pin  "ACC1:acc#340" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(10)} -pin  "ACC1:acc#340" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load inst "ACC1-1:acc#224" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 53701 -attr oid 1757 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#224} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#341.itm(0)} -pin  "ACC1-1:acc#224" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(1)} -pin  "ACC1-1:acc#224" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(2)} -pin  "ACC1-1:acc#224" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(3)} -pin  "ACC1-1:acc#224" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(4)} -pin  "ACC1-1:acc#224" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(5)} -pin  "ACC1-1:acc#224" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(6)} -pin  "ACC1-1:acc#224" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(7)} -pin  "ACC1-1:acc#224" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(8)} -pin  "ACC1-1:acc#224" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(9)} -pin  "ACC1-1:acc#224" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(10)} -pin  "ACC1-1:acc#224" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#340.itm(0)} -pin  "ACC1-1:acc#224" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(1)} -pin  "ACC1-1:acc#224" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(2)} -pin  "ACC1-1:acc#224" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(3)} -pin  "ACC1-1:acc#224" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(4)} -pin  "ACC1-1:acc#224" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(5)} -pin  "ACC1-1:acc#224" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(6)} -pin  "ACC1-1:acc#224" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(7)} -pin  "ACC1-1:acc#224" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(8)} -pin  "ACC1-1:acc#224" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(9)} -pin  "ACC1-1:acc#224" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(10)} -pin  "ACC1-1:acc#224" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#224.psp#1.sva(0)} -pin  "ACC1-1:acc#224" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(1)} -pin  "ACC1-1:acc#224" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(2)} -pin  "ACC1-1:acc#224" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(3)} -pin  "ACC1-1:acc#224" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(4)} -pin  "ACC1-1:acc#224" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(5)} -pin  "ACC1-1:acc#224" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(6)} -pin  "ACC1-1:acc#224" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(7)} -pin  "ACC1-1:acc#224" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(8)} -pin  "ACC1-1:acc#224" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(9)} -pin  "ACC1-1:acc#224" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(10)} -pin  "ACC1-1:acc#224" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1-1:acc#224" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load inst "ACC1-3:not#57" "not(1)" "INTERFACE" -attr xrf 53702 -attr oid 1758 -attr @path {/sobel/sobel:core/ACC1-3:not#57} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#405.itm(2)} -pin  "ACC1-3:not#57" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#3.itm}
+load net {ACC1-3:not#57.itm} -pin  "ACC1-3:not#57" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#57.itm}
+load inst "ACC1-3:not#58" "not(1)" "INTERFACE" -attr xrf 53703 -attr oid 1759 -attr @path {/sobel/sobel:core/ACC1-3:not#58} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#405.itm(3)} -pin  "ACC1-3:not#58" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva).itm}
+load net {ACC1-3:not#58.itm} -pin  "ACC1-3:not#58" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#58.itm}
+load inst "ACC1:acc#406" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 53704 -attr oid 1760 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#406} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#406" {A(0)} -attr @path {/sobel/sobel:core/conc#1012.itm}
+load net {ACC1:acc#405.itm(1)} -pin  "ACC1:acc#406" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1012.itm}
+load net {PWR} -pin  "ACC1:acc#406" {A(2)} -attr @path {/sobel/sobel:core/conc#1012.itm}
+load net {ACC1-3:not#58.itm} -pin  "ACC1:acc#406" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1270.itm}
+load net {ACC1-3:not#57.itm} -pin  "ACC1:acc#406" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1270.itm}
+load net {ACC1:acc#406.itm(0)} -pin  "ACC1:acc#406" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#406.itm}
+load net {ACC1:acc#406.itm(1)} -pin  "ACC1:acc#406" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#406.itm}
+load net {ACC1:acc#406.itm(2)} -pin  "ACC1:acc#406" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#406.itm}
+load inst "ACC1-1:not#185" "not(1)" "INTERFACE" -attr xrf 53705 -attr oid 1761 -attr @path {/sobel/sobel:core/ACC1-1:not#185} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#367.itm(2)} -pin  "ACC1-1:not#185" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#42.sva)#3.itm}
+load net {ACC1-1:not#185.itm} -pin  "ACC1-1:not#185" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#185.itm}
+load inst "ACC1-1:not#186" "not(1)" "INTERFACE" -attr xrf 53706 -attr oid 1762 -attr @path {/sobel/sobel:core/ACC1-1:not#186} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#367.itm(3)} -pin  "ACC1-1:not#186" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#42.sva)#1.itm}
+load net {ACC1-1:not#186.itm} -pin  "ACC1-1:not#186" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#186.itm}
+load inst "ACC1:acc#368" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 53707 -attr oid 1763 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#368} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#368" {A(0)} -attr @path {/sobel/sobel:core/conc#1013.itm}
+load net {ACC1:acc#367.itm(1)} -pin  "ACC1:acc#368" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1013.itm}
+load net {PWR} -pin  "ACC1:acc#368" {A(2)} -attr @path {/sobel/sobel:core/conc#1013.itm}
+load net {ACC1-1:not#186.itm} -pin  "ACC1:acc#368" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1198.itm}
+load net {ACC1-1:not#185.itm} -pin  "ACC1:acc#368" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1198.itm}
+load net {ACC1:acc#368.itm(0)} -pin  "ACC1:acc#368" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#368.itm}
+load net {ACC1:acc#368.itm(1)} -pin  "ACC1:acc#368" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#368.itm}
+load net {ACC1:acc#368.itm(2)} -pin  "ACC1:acc#368" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#368.itm}
+load inst "ACC1-1:not#291" "not(2)" "INTERFACE" -attr xrf 53708 -attr oid 1764 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#291} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#219.psp#1.sva(1)} -pin  "ACC1-1:not#291" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#1.sva).itm}
+load net {ACC1:acc#219.psp#1.sva(2)} -pin  "ACC1-1:not#291" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#1.sva).itm}
+load net {ACC1-1:not#291.itm(0)} -pin  "ACC1-1:not#291" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#291.itm}
+load net {ACC1-1:not#291.itm(1)} -pin  "ACC1-1:not#291" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#291.itm}
+load inst "ACC1:acc#367" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 53709 -attr oid 1765 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#367} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#367" {A(0)} -attr @path {/sobel/sobel:core/conc#1014.itm}
+load net {ACC1-1:not#291.itm(0)} -pin  "ACC1:acc#367" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1014.itm}
+load net {ACC1-1:not#291.itm(1)} -pin  "ACC1:acc#367" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1014.itm}
+load net {PWR} -pin  "ACC1:acc#367" {B(0)} -attr @path {/sobel/sobel:core/conc#1015.itm}
+load net {ACC1:acc#219.psp#1.sva(0)} -pin  "ACC1:acc#367" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1015.itm}
+load net {ACC1:acc#367.itm(0)} -pin  "ACC1:acc#367" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#367.itm}
+load net {ACC1:acc#367.itm(1)} -pin  "ACC1:acc#367" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#367.itm}
+load net {ACC1:acc#367.itm(2)} -pin  "ACC1:acc#367" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#367.itm}
+load net {ACC1:acc#367.itm(3)} -pin  "ACC1:acc#367" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#367.itm}
+load inst "ACC1-1:not#307" "not(1)" "INTERFACE" -attr xrf 53710 -attr oid 1766 -attr @path {/sobel/sobel:core/ACC1-1:not#307} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1-1:not#307" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#23.itm}
+load net {ACC1-1:not#307.itm} -pin  "ACC1-1:not#307" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#307.itm}
+load inst "ACC1-1:not#220" "not(1)" "INTERFACE" -attr xrf 53711 -attr oid 1767 -attr @path {/sobel/sobel:core/ACC1-1:not#220} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(1)} -pin  "ACC1-1:not#220" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#15.itm}
+load net {ACC1-1:not#220.itm} -pin  "ACC1-1:not#220" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#220.itm}
+load inst "ACC1:acc#363" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 53712 -attr oid 1768 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#363} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#363" {A(0)} -attr @path {/sobel/sobel:core/conc#1017.itm}
+load net {ACC1-1:not#307.itm} -pin  "ACC1:acc#363" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1017.itm}
+load net {ACC1-1:acc#25.psp.sva(8)} -pin  "ACC1:acc#363" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1187.itm}
+load net {ACC1-1:not#220.itm} -pin  "ACC1:acc#363" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1187.itm}
+load net {ACC1:acc#363.itm(0)} -pin  "ACC1:acc#363" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#363.itm}
+load net {ACC1:acc#363.itm(1)} -pin  "ACC1:acc#363" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#363.itm}
+load net {ACC1:acc#363.itm(2)} -pin  "ACC1:acc#363" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#363.itm}
+load net {ACC1:acc#363.itm(3)} -pin  "ACC1:acc#363" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#363.itm}
+load inst "ACC1:acc#365" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 53713 -attr oid 1769 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#365" {A(0)} -attr @path {/sobel/sobel:core/conc#1016.itm}
+load net {ACC1:acc#363.itm(1)} -pin  "ACC1:acc#365" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1016.itm}
+load net {ACC1:acc#363.itm(2)} -pin  "ACC1:acc#365" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1016.itm}
+load net {ACC1:acc#363.itm(3)} -pin  "ACC1:acc#365" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1016.itm}
+load net {ACC1-1:acc#25.psp.sva(10)} -pin  "ACC1:acc#365" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1018.itm}
+load net {ACC1-1:acc#25.psp.sva(0)} -pin  "ACC1:acc#365" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1018.itm}
+load net {GND} -pin  "ACC1:acc#365" {B(2)} -attr @path {/sobel/sobel:core/conc#1018.itm}
+load net {PWR} -pin  "ACC1:acc#365" {B(3)} -attr @path {/sobel/sobel:core/conc#1018.itm}
+load net {ACC1:acc#365.itm(0)} -pin  "ACC1:acc#365" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365.itm}
+load net {ACC1:acc#365.itm(1)} -pin  "ACC1:acc#365" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365.itm}
+load net {ACC1:acc#365.itm(2)} -pin  "ACC1:acc#365" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365.itm}
+load net {ACC1:acc#365.itm(3)} -pin  "ACC1:acc#365" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365.itm}
+load net {ACC1:acc#365.itm(4)} -pin  "ACC1:acc#365" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365.itm}
+load inst "ACC1-1:not#221" "not(1)" "INTERFACE" -attr xrf 53714 -attr oid 1770 -attr @path {/sobel/sobel:core/ACC1-1:not#221} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(3)} -pin  "ACC1-1:not#221" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#17.itm}
+load net {ACC1-1:not#221.itm} -pin  "ACC1-1:not#221" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#221.itm}
+load inst "ACC1-1:not#223" "not(1)" "INTERFACE" -attr xrf 53715 -attr oid 1771 -attr @path {/sobel/sobel:core/ACC1-1:not#223} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(7)} -pin  "ACC1-1:not#223" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#2.itm}
+load net {ACC1-1:not#223.itm} -pin  "ACC1-1:not#223" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#223.itm}
+load inst "ACC1:acc#362" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53716 -attr oid 1772 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#362} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#362" {A(0)} -attr @path {/sobel/sobel:core/conc#1020.itm}
+load net {ACC1-1:acc#25.psp.sva(2)} -pin  "ACC1:acc#362" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1020.itm}
+load net {ACC1-1:not#223.itm} -pin  "ACC1:acc#362" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1185.itm}
+load net {ACC1-1:not#221.itm} -pin  "ACC1:acc#362" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1185.itm}
+load net {ACC1:acc#362.itm(0)} -pin  "ACC1:acc#362" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#362.itm}
+load net {ACC1:acc#362.itm(1)} -pin  "ACC1:acc#362" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#362.itm}
+load net {ACC1:acc#362.itm(2)} -pin  "ACC1:acc#362" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#362.itm}
+load inst "ACC1-1:not#222" "not(1)" "INTERFACE" -attr xrf 53717 -attr oid 1773 -attr @path {/sobel/sobel:core/ACC1-1:not#222} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(5)} -pin  "ACC1-1:not#222" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#5.itm}
+load net {ACC1-1:not#222.itm} -pin  "ACC1-1:not#222" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#222.itm}
+load inst "ACC1:acc#361" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53718 -attr oid 1774 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#361} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#361" {A(0)} -attr @path {/sobel/sobel:core/conc#1021.itm}
+load net {ACC1-1:acc#25.psp.sva(4)} -pin  "ACC1:acc#361" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1021.itm}
+load net {ACC1-1:acc#25.psp.sva(6)} -pin  "ACC1:acc#361" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1183.itm}
+load net {ACC1-1:not#222.itm} -pin  "ACC1:acc#361" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1183.itm}
+load net {ACC1:acc#361.itm(0)} -pin  "ACC1:acc#361" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#361.itm}
+load net {ACC1:acc#361.itm(1)} -pin  "ACC1:acc#361" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#361.itm}
+load net {ACC1:acc#361.itm(2)} -pin  "ACC1:acc#361" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#361.itm}
+load inst "ACC1-1:not#224" "not(1)" "INTERFACE" -attr xrf 53719 -attr oid 1775 -attr @path {/sobel/sobel:core/ACC1-1:not#224} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(9)} -pin  "ACC1-1:not#224" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#3.itm}
+load net {ACC1-1:not#224.itm} -pin  "ACC1-1:not#224" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#224.itm}
+load inst "ACC1:acc#364" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53720 -attr oid 1776 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#364} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#364" {A(0)} -attr @path {/sobel/sobel:core/conc#1019.itm}
+load net {ACC1:acc#362.itm(1)} -pin  "ACC1:acc#364" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1019.itm}
+load net {ACC1:acc#362.itm(2)} -pin  "ACC1:acc#364" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1019.itm}
+load net {ACC1-1:not#224.itm} -pin  "ACC1:acc#364" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1189.itm}
+load net {ACC1:acc#361.itm(1)} -pin  "ACC1:acc#364" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1189.itm}
+load net {ACC1:acc#361.itm(2)} -pin  "ACC1:acc#364" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1189.itm}
+load net {ACC1:acc#364.itm(0)} -pin  "ACC1:acc#364" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#364.itm}
+load net {ACC1:acc#364.itm(1)} -pin  "ACC1:acc#364" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#364.itm}
+load net {ACC1:acc#364.itm(2)} -pin  "ACC1:acc#364" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#364.itm}
+load net {ACC1:acc#364.itm(3)} -pin  "ACC1:acc#364" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#364.itm}
+load inst "ACC1-1:acc#208" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 53721 -attr oid 1777 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#208} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#365.itm(1)} -pin  "ACC1-1:acc#208" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#41.itm}
+load net {ACC1:acc#365.itm(2)} -pin  "ACC1-1:acc#208" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#41.itm}
+load net {ACC1:acc#365.itm(3)} -pin  "ACC1-1:acc#208" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#41.itm}
+load net {ACC1:acc#365.itm(4)} -pin  "ACC1-1:acc#208" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#41.itm}
+load net {ACC1:acc#364.itm(1)} -pin  "ACC1-1:acc#208" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1:acc#364.itm(2)} -pin  "ACC1-1:acc#208" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1:acc#364.itm(3)} -pin  "ACC1-1:acc#208" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1-1:acc#208.psp.sva(0)} -pin  "ACC1-1:acc#208" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#208.psp.sva}
+load net {ACC1-1:acc#208.psp.sva(1)} -pin  "ACC1-1:acc#208" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#208.psp.sva}
+load net {ACC1-1:acc#208.psp.sva(2)} -pin  "ACC1-1:acc#208" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#208.psp.sva}
+load net {ACC1-1:acc#208.psp.sva(3)} -pin  "ACC1-1:acc#208" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#208.psp.sva}
+load inst "ACC1-1:not#89" "not(1)" "INTERFACE" -attr xrf 53722 -attr oid 1778 -attr @path {/sobel/sobel:core/ACC1-1:not#89} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#348.itm(2)} -pin  "ACC1-1:not#89" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#34.sva)#3.itm}
+load net {ACC1-1:not#89.itm} -pin  "ACC1-1:not#89" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#89.itm}
+load inst "ACC1-1:not#90" "not(1)" "INTERFACE" -attr xrf 53723 -attr oid 1779 -attr @path {/sobel/sobel:core/ACC1-1:not#90} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#348.itm(3)} -pin  "ACC1-1:not#90" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#34.sva)#1.itm}
+load net {ACC1-1:not#90.itm} -pin  "ACC1-1:not#90" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#90.itm}
+load inst "ACC1:acc#349" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 53724 -attr oid 1780 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#349} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#349" {A(0)} -attr @path {/sobel/sobel:core/conc#1022.itm}
+load net {ACC1:acc#348.itm(1)} -pin  "ACC1:acc#349" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1022.itm}
+load net {PWR} -pin  "ACC1:acc#349" {A(2)} -attr @path {/sobel/sobel:core/conc#1022.itm}
+load net {ACC1-1:not#90.itm} -pin  "ACC1:acc#349" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1162.itm}
+load net {ACC1-1:not#89.itm} -pin  "ACC1:acc#349" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1162.itm}
+load net {ACC1:acc#349.itm(0)} -pin  "ACC1:acc#349" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#349.itm}
+load net {ACC1:acc#349.itm(1)} -pin  "ACC1:acc#349" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#349.itm}
+load net {ACC1:acc#349.itm(2)} -pin  "ACC1:acc#349" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#349.itm}
+load inst "ACC1-1:not#297" "not(2)" "INTERFACE" -attr xrf 53725 -attr oid 1781 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#297} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#222.psp#1.sva(1)} -pin  "ACC1-1:not#297" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp#1.sva).itm}
+load net {ACC1:acc#222.psp#1.sva(2)} -pin  "ACC1-1:not#297" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp#1.sva).itm}
+load net {ACC1-1:not#297.itm(0)} -pin  "ACC1-1:not#297" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#297.itm}
+load net {ACC1-1:not#297.itm(1)} -pin  "ACC1-1:not#297" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#297.itm}
+load inst "ACC1:acc#348" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 53726 -attr oid 1782 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#348" {A(0)} -attr @path {/sobel/sobel:core/conc#1023.itm}
+load net {ACC1-1:not#297.itm(0)} -pin  "ACC1:acc#348" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1023.itm}
+load net {ACC1-1:not#297.itm(1)} -pin  "ACC1:acc#348" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1023.itm}
+load net {PWR} -pin  "ACC1:acc#348" {B(0)} -attr @path {/sobel/sobel:core/conc#1024.itm}
+load net {ACC1:acc#222.psp#1.sva(0)} -pin  "ACC1:acc#348" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1024.itm}
+load net {ACC1:acc#348.itm(0)} -pin  "ACC1:acc#348" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {ACC1:acc#348.itm(1)} -pin  "ACC1:acc#348" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {ACC1:acc#348.itm(2)} -pin  "ACC1:acc#348" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {ACC1:acc#348.itm(3)} -pin  "ACC1:acc#348" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load inst "ACC1:acc#407" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 53727 -attr oid 1783 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.regs:slc(regs.regs(2))#4.itm(0)} -pin  "ACC1:acc#407" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(1)} -pin  "ACC1:acc#407" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(2)} -pin  "ACC1:acc#407" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(3)} -pin  "ACC1:acc#407" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(4)} -pin  "ACC1:acc#407" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(5)} -pin  "ACC1:acc#407" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(6)} -pin  "ACC1:acc#407" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(7)} -pin  "ACC1:acc#407" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(8)} -pin  "ACC1:acc#407" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(9)} -pin  "ACC1:acc#407" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(0)} -pin  "ACC1:acc#407" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(1)} -pin  "ACC1:acc#407" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(2)} -pin  "ACC1:acc#407" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(3)} -pin  "ACC1:acc#407" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(4)} -pin  "ACC1:acc#407" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(5)} -pin  "ACC1:acc#407" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(6)} -pin  "ACC1:acc#407" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(7)} -pin  "ACC1:acc#407" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(8)} -pin  "ACC1:acc#407" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(9)} -pin  "ACC1:acc#407" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {ACC1:acc#407.itm(0)} -pin  "ACC1:acc#407" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(1)} -pin  "ACC1:acc#407" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(2)} -pin  "ACC1:acc#407" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(3)} -pin  "ACC1:acc#407" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(4)} -pin  "ACC1:acc#407" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(5)} -pin  "ACC1:acc#407" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(6)} -pin  "ACC1:acc#407" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(7)} -pin  "ACC1:acc#407" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(8)} -pin  "ACC1:acc#407" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(9)} -pin  "ACC1:acc#407" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(10)} -pin  "ACC1:acc#407" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load inst "ACC1-3:acc#224" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 53728 -attr oid 1784 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#224} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#407.itm(0)} -pin  "ACC1-3:acc#224" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(1)} -pin  "ACC1-3:acc#224" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(2)} -pin  "ACC1-3:acc#224" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(3)} -pin  "ACC1-3:acc#224" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(4)} -pin  "ACC1-3:acc#224" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(5)} -pin  "ACC1-3:acc#224" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(6)} -pin  "ACC1-3:acc#224" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(7)} -pin  "ACC1-3:acc#224" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(8)} -pin  "ACC1-3:acc#224" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(9)} -pin  "ACC1-3:acc#224" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(10)} -pin  "ACC1-3:acc#224" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(0)} -pin  "ACC1-3:acc#224" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(1)} -pin  "ACC1-3:acc#224" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(2)} -pin  "ACC1-3:acc#224" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(3)} -pin  "ACC1-3:acc#224" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(4)} -pin  "ACC1-3:acc#224" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(5)} -pin  "ACC1-3:acc#224" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(6)} -pin  "ACC1-3:acc#224" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(7)} -pin  "ACC1-3:acc#224" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(8)} -pin  "ACC1-3:acc#224" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(9)} -pin  "ACC1-3:acc#224" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {ACC1:acc#224.psp.sva(0)} -pin  "ACC1-3:acc#224" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(1)} -pin  "ACC1-3:acc#224" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(2)} -pin  "ACC1-3:acc#224" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(3)} -pin  "ACC1-3:acc#224" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(4)} -pin  "ACC1-3:acc#224" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(5)} -pin  "ACC1-3:acc#224" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(6)} -pin  "ACC1-3:acc#224" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(7)} -pin  "ACC1-3:acc#224" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(8)} -pin  "ACC1-3:acc#224" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(9)} -pin  "ACC1-3:acc#224" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(10)} -pin  "ACC1-3:acc#224" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1-3:acc#224" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load inst "ACC1:acc#516" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53729 -attr oid 1785 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#516" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1051.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#516" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1051.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#516" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1043.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#516" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1043.itm}
+load net {ACC1:acc#516.cse(0)} -pin  "ACC1:acc#516" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(1)} -pin  "ACC1:acc#516" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(2)} -pin  "ACC1:acc#516" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load inst "ACC1-3:not#247" "not(1)" "INTERFACE" -attr xrf 53730 -attr oid 1786 -attr @path {/sobel/sobel:core/ACC1-3:not#247} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp.sva(0)} -pin  "ACC1-3:not#247" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#12.itm}
+load net {ACC1-3:not#247.itm} -pin  "ACC1-3:not#247" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#247.itm}
+load inst "ACC1-3:not#248" "not(1)" "INTERFACE" -attr xrf 53731 -attr oid 1787 -attr @path {/sobel/sobel:core/ACC1-3:not#248} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp.sva(2)} -pin  "ACC1-3:not#248" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#3.itm}
+load net {ACC1-3:not#248.itm} -pin  "ACC1-3:not#248" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#248.itm}
+load inst "ACC1-3:not#250" "not(1)" "INTERFACE" -attr xrf 53732 -attr oid 1788 -attr @path {/sobel/sobel:core/ACC1-3:not#250} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp.sva(6)} -pin  "ACC1-3:not#250" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva).itm}
+load net {ACC1-3:not#250.itm} -pin  "ACC1-3:not#250" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#250.itm}
+load inst "ACC1:acc#409" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53733 -attr oid 1789 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#409} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#409" {A(0)} -attr @path {/sobel/sobel:core/conc#1027.itm}
+load net {ACC1:acc#224.psp.sva(1)} -pin  "ACC1:acc#409" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1027.itm}
+load net {ACC1-3:not#250.itm} -pin  "ACC1:acc#409" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1275.itm}
+load net {ACC1-3:not#248.itm} -pin  "ACC1:acc#409" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1275.itm}
+load net {ACC1:acc#409.itm(0)} -pin  "ACC1:acc#409" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#409.itm}
+load net {ACC1:acc#409.itm(1)} -pin  "ACC1:acc#409" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#409.itm}
+load net {ACC1:acc#409.itm(2)} -pin  "ACC1:acc#409" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#409.itm}
+load inst "ACC1-3:not#251" "not(1)" "INTERFACE" -attr xrf 53734 -attr oid 1790 -attr @path {/sobel/sobel:core/ACC1-3:not#251} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp.sva(8)} -pin  "ACC1-3:not#251" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#15.itm}
+load net {ACC1-3:not#251.itm} -pin  "ACC1-3:not#251" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#251.itm}
+load inst "ACC1:acc#411" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 53735 -attr oid 1791 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#411} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#411" {A(0)} -attr @path {/sobel/sobel:core/conc#1026.itm}
+load net {ACC1-3:not#247.itm} -pin  "ACC1:acc#411" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1026.itm}
+load net {GND} -pin  "ACC1:acc#411" {A(2)} -attr @path {/sobel/sobel:core/conc#1026.itm}
+load net {PWR} -pin  "ACC1:acc#411" {A(3)} -attr @path {/sobel/sobel:core/conc#1026.itm}
+load net {ACC1-3:not#251.itm} -pin  "ACC1:acc#411" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1279.itm}
+load net {ACC1:acc#409.itm(1)} -pin  "ACC1:acc#411" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1279.itm}
+load net {ACC1:acc#409.itm(2)} -pin  "ACC1:acc#411" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1279.itm}
+load net {ACC1:acc#411.itm(0)} -pin  "ACC1:acc#411" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#411.itm}
+load net {ACC1:acc#411.itm(1)} -pin  "ACC1:acc#411" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#411.itm}
+load net {ACC1:acc#411.itm(2)} -pin  "ACC1:acc#411" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#411.itm}
+load net {ACC1:acc#411.itm(3)} -pin  "ACC1:acc#411" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#411.itm}
+load inst "ACC1-3:not#249" "not(1)" "INTERFACE" -attr xrf 53736 -attr oid 1792 -attr @path {/sobel/sobel:core/ACC1-3:not#249} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp.sva(4)} -pin  "ACC1-3:not#249" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#7.itm}
+load net {ACC1-3:not#249.itm} -pin  "ACC1-3:not#249" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#249.itm}
+load inst "ACC1:acc#408" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53737 -attr oid 1793 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#408} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#408" {A(0)} -attr @path {/sobel/sobel:core/conc#1029.itm}
+load net {ACC1:acc#224.psp.sva(3)} -pin  "ACC1:acc#408" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1029.itm}
+load net {ACC1:acc#224.psp.sva(5)} -pin  "ACC1:acc#408" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1273.itm}
+load net {ACC1-3:not#249.itm} -pin  "ACC1:acc#408" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1273.itm}
+load net {ACC1:acc#408.itm(0)} -pin  "ACC1:acc#408" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#408.itm}
+load net {ACC1:acc#408.itm(1)} -pin  "ACC1:acc#408" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#408.itm}
+load net {ACC1:acc#408.itm(2)} -pin  "ACC1:acc#408" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#408.itm}
+load inst "ACC1-3:not#252" "not(2)" "INTERFACE" -attr xrf 53738 -attr oid 1794 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#252} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#224.psp.sva(10)} -pin  "ACC1-3:not#252" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#14.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1-3:not#252" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#14.itm}
+load net {ACC1-3:not#252.itm(0)} -pin  "ACC1-3:not#252" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#252.itm}
+load net {ACC1-3:not#252.itm(1)} -pin  "ACC1-3:not#252" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#252.itm}
+load inst "ACC1:acc#410" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 53739 -attr oid 1795 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#410" {A(0)} -attr @path {/sobel/sobel:core/conc#1028.itm}
+load net {ACC1:acc#408.itm(1)} -pin  "ACC1:acc#410" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1028.itm}
+load net {ACC1:acc#408.itm(2)} -pin  "ACC1:acc#410" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1028.itm}
+load net {ACC1:acc#224.psp.sva(7)} -pin  "ACC1:acc#410" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1277.itm}
+load net {ACC1-3:not#252.itm(0)} -pin  "ACC1:acc#410" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1277.itm}
+load net {ACC1-3:not#252.itm(1)} -pin  "ACC1:acc#410" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1277.itm}
+load net {ACC1:acc#410.itm(0)} -pin  "ACC1:acc#410" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410.itm}
+load net {ACC1:acc#410.itm(1)} -pin  "ACC1:acc#410" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410.itm}
+load net {ACC1:acc#410.itm(2)} -pin  "ACC1:acc#410" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410.itm}
+load net {ACC1:acc#410.itm(3)} -pin  "ACC1:acc#410" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410.itm}
+load net {ACC1:acc#410.itm(4)} -pin  "ACC1:acc#410" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410.itm}
+load inst "ACC1:acc#412" "add(4,1,5,-1,5)" "INTERFACE" -attr xrf 53740 -attr oid 1796 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "ACC1:acc#412" {A(0)} -attr @path {/sobel/sobel:core/conc#1025.itm}
+load net {ACC1:acc#411.itm(1)} -pin  "ACC1:acc#412" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1025.itm}
+load net {ACC1:acc#411.itm(2)} -pin  "ACC1:acc#412" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1025.itm}
+load net {ACC1:acc#411.itm(3)} -pin  "ACC1:acc#412" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1025.itm}
+load net {ACC1:acc#224.psp.sva(9)} -pin  "ACC1:acc#412" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1281.itm}
+load net {ACC1:acc#410.itm(1)} -pin  "ACC1:acc#412" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1281.itm}
+load net {ACC1:acc#410.itm(2)} -pin  "ACC1:acc#412" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1281.itm}
+load net {ACC1:acc#410.itm(3)} -pin  "ACC1:acc#412" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1281.itm}
+load net {ACC1:acc#410.itm(4)} -pin  "ACC1:acc#412" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1281.itm}
+load net {ACC1:acc#412.itm(0)} -pin  "ACC1:acc#412" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412.itm}
+load net {ACC1:acc#412.itm(1)} -pin  "ACC1:acc#412" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412.itm}
+load net {ACC1:acc#412.itm(2)} -pin  "ACC1:acc#412" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412.itm}
+load net {ACC1:acc#412.itm(3)} -pin  "ACC1:acc#412" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412.itm}
+load net {ACC1:acc#412.itm(4)} -pin  "ACC1:acc#412" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412.itm}
+load inst "ACC1-3:not#299" "not(2)" "INTERFACE" -attr xrf 53741 -attr oid 1797 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#299} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#223.psp.sva(1)} -pin  "ACC1-3:not#299" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp.sva).itm}
+load net {ACC1:acc#223.psp.sva(2)} -pin  "ACC1-3:not#299" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp.sva).itm}
+load net {ACC1-3:not#299.itm(0)} -pin  "ACC1-3:not#299" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#299.itm}
+load net {ACC1-3:not#299.itm(1)} -pin  "ACC1-3:not#299" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#299.itm}
+load inst "ACC1:acc#423" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 53742 -attr oid 1798 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#423} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#423" {A(0)} -attr @path {/sobel/sobel:core/conc#1030.itm}
+load net {ACC1-3:not#299.itm(0)} -pin  "ACC1:acc#423" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1030.itm}
+load net {ACC1-3:not#299.itm(1)} -pin  "ACC1:acc#423" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1030.itm}
+load net {PWR} -pin  "ACC1:acc#423" {B(0)} -attr @path {/sobel/sobel:core/conc#1031.itm}
+load net {ACC1:acc#223.psp.sva(0)} -pin  "ACC1:acc#423" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1031.itm}
+load net {ACC1:acc#423.itm(0)} -pin  "ACC1:acc#423" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#423.itm}
+load net {ACC1:acc#423.itm(1)} -pin  "ACC1:acc#423" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#423.itm}
+load net {ACC1:acc#423.itm(2)} -pin  "ACC1:acc#423" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#423.itm}
+load net {ACC1:acc#423.itm(3)} -pin  "ACC1:acc#423" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#423.itm}
+load inst "ACC1-2:not#238" "not(1)" "INTERFACE" -attr xrf 53743 -attr oid 1799 -attr @path {/sobel/sobel:core/ACC1-2:not#238} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#228.psp.sva(0)} -pin  "ACC1-2:not#238" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#7.itm}
+load net {ACC1-2:not#238.itm} -pin  "ACC1-2:not#238" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#238.itm}
+load inst "ACC1-2:not#239" "not(1)" "INTERFACE" -attr xrf 53744 -attr oid 1800 -attr @path {/sobel/sobel:core/ACC1-2:not#239} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#228.psp.sva(2)} -pin  "ACC1-2:not#239" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#6.itm}
+load net {ACC1-2:not#239.itm} -pin  "ACC1-2:not#239" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#239.itm}
+load inst "ACC1-2:not#241" "not(1)" "INTERFACE" -attr xrf 53745 -attr oid 1801 -attr @path {/sobel/sobel:core/ACC1-2:not#241} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#228.psp.sva(6)} -pin  "ACC1-2:not#241" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#13.itm}
+load net {ACC1-2:not#241.itm} -pin  "ACC1-2:not#241" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#241.itm}
+load inst "ACC1:acc#372" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53746 -attr oid 1802 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#372} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#372" {A(0)} -attr @path {/sobel/sobel:core/conc#1034.itm}
+load net {ACC1:acc#228.psp.sva(1)} -pin  "ACC1:acc#372" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1034.itm}
+load net {ACC1-2:not#241.itm} -pin  "ACC1:acc#372" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1203.itm}
+load net {ACC1-2:not#239.itm} -pin  "ACC1:acc#372" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1203.itm}
+load net {ACC1:acc#372.itm(0)} -pin  "ACC1:acc#372" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#372.itm}
+load net {ACC1:acc#372.itm(1)} -pin  "ACC1:acc#372" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#372.itm}
+load net {ACC1:acc#372.itm(2)} -pin  "ACC1:acc#372" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#372.itm}
+load inst "ACC1-2:not#242" "not(1)" "INTERFACE" -attr xrf 53747 -attr oid 1803 -attr @path {/sobel/sobel:core/ACC1-2:not#242} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#228.psp.sva(8)} -pin  "ACC1-2:not#242" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#4.itm}
+load net {ACC1-2:not#242.itm} -pin  "ACC1-2:not#242" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#242.itm}
+load inst "ACC1:acc#374" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 53748 -attr oid 1804 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#374} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#374" {A(0)} -attr @path {/sobel/sobel:core/conc#1033.itm}
+load net {ACC1-2:not#238.itm} -pin  "ACC1:acc#374" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1033.itm}
+load net {GND} -pin  "ACC1:acc#374" {A(2)} -attr @path {/sobel/sobel:core/conc#1033.itm}
+load net {PWR} -pin  "ACC1:acc#374" {A(3)} -attr @path {/sobel/sobel:core/conc#1033.itm}
+load net {ACC1-2:not#242.itm} -pin  "ACC1:acc#374" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1207.itm}
+load net {ACC1:acc#372.itm(1)} -pin  "ACC1:acc#374" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1207.itm}
+load net {ACC1:acc#372.itm(2)} -pin  "ACC1:acc#374" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1207.itm}
+load net {ACC1:acc#374.itm(0)} -pin  "ACC1:acc#374" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#374.itm}
+load net {ACC1:acc#374.itm(1)} -pin  "ACC1:acc#374" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#374.itm}
+load net {ACC1:acc#374.itm(2)} -pin  "ACC1:acc#374" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#374.itm}
+load net {ACC1:acc#374.itm(3)} -pin  "ACC1:acc#374" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#374.itm}
+load inst "ACC1-2:not#240" "not(1)" "INTERFACE" -attr xrf 53749 -attr oid 1805 -attr @path {/sobel/sobel:core/ACC1-2:not#240} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#228.psp.sva(4)} -pin  "ACC1-2:not#240" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#3.itm}
+load net {ACC1-2:not#240.itm} -pin  "ACC1-2:not#240" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#240.itm}
+load inst "ACC1:acc#371" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53750 -attr oid 1806 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#371} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#371" {A(0)} -attr @path {/sobel/sobel:core/conc#1036.itm}
+load net {ACC1:acc#228.psp.sva(3)} -pin  "ACC1:acc#371" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1036.itm}
+load net {ACC1:acc#228.psp.sva(5)} -pin  "ACC1:acc#371" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1201.itm}
+load net {ACC1-2:not#240.itm} -pin  "ACC1:acc#371" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1201.itm}
+load net {ACC1:acc#371.itm(0)} -pin  "ACC1:acc#371" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#371.itm}
+load net {ACC1:acc#371.itm(1)} -pin  "ACC1:acc#371" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#371.itm}
+load net {ACC1:acc#371.itm(2)} -pin  "ACC1:acc#371" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#371.itm}
+load inst "ACC1-2:not#243" "not(2)" "INTERFACE" -attr xrf 53751 -attr oid 1807 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#243} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#228.psp.sva(10)} -pin  "ACC1-2:not#243" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#12.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1-2:not#243" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#12.itm}
+load net {ACC1-2:not#243.itm(0)} -pin  "ACC1-2:not#243" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#243.itm}
+load net {ACC1-2:not#243.itm(1)} -pin  "ACC1-2:not#243" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#243.itm}
+load inst "ACC1:acc#373" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 53752 -attr oid 1808 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#373" {A(0)} -attr @path {/sobel/sobel:core/conc#1035.itm}
+load net {ACC1:acc#371.itm(1)} -pin  "ACC1:acc#373" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1035.itm}
+load net {ACC1:acc#371.itm(2)} -pin  "ACC1:acc#373" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1035.itm}
+load net {ACC1:acc#228.psp.sva(7)} -pin  "ACC1:acc#373" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1205.itm}
+load net {ACC1-2:not#243.itm(0)} -pin  "ACC1:acc#373" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1205.itm}
+load net {ACC1-2:not#243.itm(1)} -pin  "ACC1:acc#373" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1205.itm}
+load net {ACC1:acc#373.itm(0)} -pin  "ACC1:acc#373" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373.itm}
+load net {ACC1:acc#373.itm(1)} -pin  "ACC1:acc#373" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373.itm}
+load net {ACC1:acc#373.itm(2)} -pin  "ACC1:acc#373" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373.itm}
+load net {ACC1:acc#373.itm(3)} -pin  "ACC1:acc#373" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373.itm}
+load net {ACC1:acc#373.itm(4)} -pin  "ACC1:acc#373" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373.itm}
+load inst "ACC1:acc#375" "add(4,1,5,-1,5)" "INTERFACE" -attr xrf 53753 -attr oid 1809 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "ACC1:acc#375" {A(0)} -attr @path {/sobel/sobel:core/conc#1032.itm}
+load net {ACC1:acc#374.itm(1)} -pin  "ACC1:acc#375" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1032.itm}
+load net {ACC1:acc#374.itm(2)} -pin  "ACC1:acc#375" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1032.itm}
+load net {ACC1:acc#374.itm(3)} -pin  "ACC1:acc#375" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1032.itm}
+load net {ACC1:acc#228.psp.sva(9)} -pin  "ACC1:acc#375" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1209.itm}
+load net {ACC1:acc#373.itm(1)} -pin  "ACC1:acc#375" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1209.itm}
+load net {ACC1:acc#373.itm(2)} -pin  "ACC1:acc#375" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1209.itm}
+load net {ACC1:acc#373.itm(3)} -pin  "ACC1:acc#375" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1209.itm}
+load net {ACC1:acc#373.itm(4)} -pin  "ACC1:acc#375" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1209.itm}
+load net {ACC1:acc#375.itm(0)} -pin  "ACC1:acc#375" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375.itm}
+load net {ACC1:acc#375.itm(1)} -pin  "ACC1:acc#375" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375.itm}
+load net {ACC1:acc#375.itm(2)} -pin  "ACC1:acc#375" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375.itm}
+load net {ACC1:acc#375.itm(3)} -pin  "ACC1:acc#375" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375.itm}
+load net {ACC1:acc#375.itm(4)} -pin  "ACC1:acc#375" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375.itm}
+load inst "ACC1-3:not#293" "not(2)" "INTERFACE" -attr xrf 53754 -attr oid 1810 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#293} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#220.psp.sva(1)} -pin  "ACC1-3:not#293" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp.sva).itm}
+load net {ACC1:acc#220.psp.sva(2)} -pin  "ACC1-3:not#293" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp.sva).itm}
+load net {ACC1-3:not#293.itm(0)} -pin  "ACC1-3:not#293" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#293.itm}
+load net {ACC1-3:not#293.itm(1)} -pin  "ACC1-3:not#293" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#293.itm}
+load inst "ACC1:acc#395" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 53755 -attr oid 1811 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#395} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#395" {A(0)} -attr @path {/sobel/sobel:core/conc#1037.itm}
+load net {ACC1-3:not#293.itm(0)} -pin  "ACC1:acc#395" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1037.itm}
+load net {ACC1-3:not#293.itm(1)} -pin  "ACC1:acc#395" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1037.itm}
+load net {PWR} -pin  "ACC1:acc#395" {B(0)} -attr @path {/sobel/sobel:core/conc#1038.itm}
+load net {ACC1:acc#220.psp.sva(0)} -pin  "ACC1:acc#395" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1038.itm}
+load net {ACC1:acc#395.itm(0)} -pin  "ACC1:acc#395" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#395.itm}
+load net {ACC1:acc#395.itm(1)} -pin  "ACC1:acc#395" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#395.itm}
+load net {ACC1:acc#395.itm(2)} -pin  "ACC1:acc#395" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#395.itm}
+load net {ACC1:acc#395.itm(3)} -pin  "ACC1:acc#395" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#395.itm}
+load inst "ACC1-2:not#220" "not(1)" "INTERFACE" -attr xrf 53756 -attr oid 1812 -attr @path {/sobel/sobel:core/ACC1-2:not#220} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#226.psp.sva(0)} -pin  "ACC1-2:not#220" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#7.itm}
+load net {ACC1-2:not#220.itm} -pin  "ACC1-2:not#220" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#220.itm}
+load inst "ACC1-2:not#221" "not(1)" "INTERFACE" -attr xrf 53757 -attr oid 1813 -attr @path {/sobel/sobel:core/ACC1-2:not#221} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#226.psp.sva(2)} -pin  "ACC1-2:not#221" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#6.itm}
+load net {ACC1-2:not#221.itm} -pin  "ACC1-2:not#221" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#221.itm}
+load inst "ACC1-2:not#223" "not(1)" "INTERFACE" -attr xrf 53758 -attr oid 1814 -attr @path {/sobel/sobel:core/ACC1-2:not#223} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#226.psp.sva(6)} -pin  "ACC1-2:not#223" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva).itm}
+load net {ACC1-2:not#223.itm} -pin  "ACC1-2:not#223" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#223.itm}
+load inst "ACC1:acc#381" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53759 -attr oid 1815 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#381} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#381" {A(0)} -attr @path {/sobel/sobel:core/conc#1041.itm}
+load net {ACC1:acc#226.psp.sva(1)} -pin  "ACC1:acc#381" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1041.itm}
+load net {ACC1-2:not#223.itm} -pin  "ACC1:acc#381" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1221.itm}
+load net {ACC1-2:not#221.itm} -pin  "ACC1:acc#381" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1221.itm}
+load net {ACC1:acc#381.itm(0)} -pin  "ACC1:acc#381" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#381.itm}
+load net {ACC1:acc#381.itm(1)} -pin  "ACC1:acc#381" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#381.itm}
+load net {ACC1:acc#381.itm(2)} -pin  "ACC1:acc#381" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#381.itm}
+load inst "ACC1-2:not#224" "not(1)" "INTERFACE" -attr xrf 53760 -attr oid 1816 -attr @path {/sobel/sobel:core/ACC1-2:not#224} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#226.psp.sva(8)} -pin  "ACC1-2:not#224" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#1.itm}
+load net {ACC1-2:not#224.itm} -pin  "ACC1-2:not#224" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#224.itm}
+load inst "ACC1:acc#383" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 53761 -attr oid 1817 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#383} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#383" {A(0)} -attr @path {/sobel/sobel:core/conc#1040.itm}
+load net {ACC1-2:not#220.itm} -pin  "ACC1:acc#383" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1040.itm}
+load net {GND} -pin  "ACC1:acc#383" {A(2)} -attr @path {/sobel/sobel:core/conc#1040.itm}
+load net {PWR} -pin  "ACC1:acc#383" {A(3)} -attr @path {/sobel/sobel:core/conc#1040.itm}
+load net {ACC1-2:not#224.itm} -pin  "ACC1:acc#383" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1225.itm}
+load net {ACC1:acc#381.itm(1)} -pin  "ACC1:acc#383" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1225.itm}
+load net {ACC1:acc#381.itm(2)} -pin  "ACC1:acc#383" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1225.itm}
+load net {ACC1:acc#383.itm(0)} -pin  "ACC1:acc#383" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#383.itm}
+load net {ACC1:acc#383.itm(1)} -pin  "ACC1:acc#383" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#383.itm}
+load net {ACC1:acc#383.itm(2)} -pin  "ACC1:acc#383" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#383.itm}
+load net {ACC1:acc#383.itm(3)} -pin  "ACC1:acc#383" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#383.itm}
+load inst "ACC1-2:not#222" "not(1)" "INTERFACE" -attr xrf 53762 -attr oid 1818 -attr @path {/sobel/sobel:core/ACC1-2:not#222} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#226.psp.sva(4)} -pin  "ACC1-2:not#222" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#4.itm}
+load net {ACC1-2:not#222.itm} -pin  "ACC1-2:not#222" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#222.itm}
+load inst "ACC1:acc#380" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53763 -attr oid 1819 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#380} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#380" {A(0)} -attr @path {/sobel/sobel:core/conc#1043.itm}
+load net {ACC1:acc#226.psp.sva(3)} -pin  "ACC1:acc#380" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1043.itm}
+load net {ACC1:acc#226.psp.sva(5)} -pin  "ACC1:acc#380" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1219.itm}
+load net {ACC1-2:not#222.itm} -pin  "ACC1:acc#380" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1219.itm}
+load net {ACC1:acc#380.itm(0)} -pin  "ACC1:acc#380" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#380.itm}
+load net {ACC1:acc#380.itm(1)} -pin  "ACC1:acc#380" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#380.itm}
+load net {ACC1:acc#380.itm(2)} -pin  "ACC1:acc#380" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#380.itm}
+load inst "ACC1-2:not#225" "not(2)" "INTERFACE" -attr xrf 53764 -attr oid 1820 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#225} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#226.psp.sva(10)} -pin  "ACC1-2:not#225" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#12.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1-2:not#225" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#12.itm}
+load net {ACC1-2:not#225.itm(0)} -pin  "ACC1-2:not#225" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#225.itm}
+load net {ACC1-2:not#225.itm(1)} -pin  "ACC1-2:not#225" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#225.itm}
+load inst "ACC1:acc#382" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 53765 -attr oid 1821 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#382" {A(0)} -attr @path {/sobel/sobel:core/conc#1042.itm}
+load net {ACC1:acc#380.itm(1)} -pin  "ACC1:acc#382" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1042.itm}
+load net {ACC1:acc#380.itm(2)} -pin  "ACC1:acc#382" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1042.itm}
+load net {ACC1:acc#226.psp.sva(7)} -pin  "ACC1:acc#382" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1223.itm}
+load net {ACC1-2:not#225.itm(0)} -pin  "ACC1:acc#382" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1223.itm}
+load net {ACC1-2:not#225.itm(1)} -pin  "ACC1:acc#382" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1223.itm}
+load net {ACC1:acc#382.itm(0)} -pin  "ACC1:acc#382" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382.itm}
+load net {ACC1:acc#382.itm(1)} -pin  "ACC1:acc#382" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382.itm}
+load net {ACC1:acc#382.itm(2)} -pin  "ACC1:acc#382" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382.itm}
+load net {ACC1:acc#382.itm(3)} -pin  "ACC1:acc#382" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382.itm}
+load net {ACC1:acc#382.itm(4)} -pin  "ACC1:acc#382" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382.itm}
+load inst "ACC1:acc#384" "add(4,1,5,-1,5)" "INTERFACE" -attr xrf 53766 -attr oid 1822 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "ACC1:acc#384" {A(0)} -attr @path {/sobel/sobel:core/conc#1039.itm}
+load net {ACC1:acc#383.itm(1)} -pin  "ACC1:acc#384" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1039.itm}
+load net {ACC1:acc#383.itm(2)} -pin  "ACC1:acc#384" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1039.itm}
+load net {ACC1:acc#383.itm(3)} -pin  "ACC1:acc#384" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1039.itm}
+load net {ACC1:acc#226.psp.sva(9)} -pin  "ACC1:acc#384" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1227.itm}
+load net {ACC1:acc#382.itm(1)} -pin  "ACC1:acc#384" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1227.itm}
+load net {ACC1:acc#382.itm(2)} -pin  "ACC1:acc#384" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1227.itm}
+load net {ACC1:acc#382.itm(3)} -pin  "ACC1:acc#384" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1227.itm}
+load net {ACC1:acc#382.itm(4)} -pin  "ACC1:acc#384" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1227.itm}
+load net {ACC1:acc#384.itm(0)} -pin  "ACC1:acc#384" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384.itm}
+load net {ACC1:acc#384.itm(1)} -pin  "ACC1:acc#384" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384.itm}
+load net {ACC1:acc#384.itm(2)} -pin  "ACC1:acc#384" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384.itm}
+load net {ACC1:acc#384.itm(3)} -pin  "ACC1:acc#384" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384.itm}
+load net {ACC1:acc#384.itm(4)} -pin  "ACC1:acc#384" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384.itm}
+load inst "ACC1-3:not#309" "not(1)" "INTERFACE" -attr xrf 53767 -attr oid 1823 -attr @path {/sobel/sobel:core/ACC1-3:not#309} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1-3:not#309" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#24.itm}
+load net {ACC1-3:not#309.itm} -pin  "ACC1-3:not#309" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#309.itm}
+load inst "ACC1-3:not#238" "not(1)" "INTERFACE" -attr xrf 53768 -attr oid 1824 -attr @path {/sobel/sobel:core/ACC1-3:not#238} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(1)} -pin  "ACC1-3:not#238" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#14.itm}
+load net {ACC1-3:not#238.itm} -pin  "ACC1-3:not#238" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#238.itm}
+load inst "ACC1:acc#401" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 53769 -attr oid 1825 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#401} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#401" {A(0)} -attr @path {/sobel/sobel:core/conc#1045.itm}
+load net {ACC1-3:not#309.itm} -pin  "ACC1:acc#401" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1045.itm}
+load net {ACC1:acc#227.psp.sva(8)} -pin  "ACC1:acc#401" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1259.itm}
+load net {ACC1-3:not#238.itm} -pin  "ACC1:acc#401" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1259.itm}
+load net {ACC1:acc#401.itm(0)} -pin  "ACC1:acc#401" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#401.itm}
+load net {ACC1:acc#401.itm(1)} -pin  "ACC1:acc#401" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#401.itm}
+load net {ACC1:acc#401.itm(2)} -pin  "ACC1:acc#401" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#401.itm}
+load net {ACC1:acc#401.itm(3)} -pin  "ACC1:acc#401" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#401.itm}
+load inst "ACC1:acc#403" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 53770 -attr oid 1826 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#403" {A(0)} -attr @path {/sobel/sobel:core/conc#1044.itm}
+load net {ACC1:acc#401.itm(1)} -pin  "ACC1:acc#403" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1044.itm}
+load net {ACC1:acc#401.itm(2)} -pin  "ACC1:acc#403" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1044.itm}
+load net {ACC1:acc#401.itm(3)} -pin  "ACC1:acc#403" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1044.itm}
+load net {ACC1:acc#227.psp.sva(10)} -pin  "ACC1:acc#403" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1046.itm}
+load net {ACC1:acc#227.psp.sva(0)} -pin  "ACC1:acc#403" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1046.itm}
+load net {GND} -pin  "ACC1:acc#403" {B(2)} -attr @path {/sobel/sobel:core/conc#1046.itm}
+load net {PWR} -pin  "ACC1:acc#403" {B(3)} -attr @path {/sobel/sobel:core/conc#1046.itm}
+load net {ACC1:acc#403.itm(0)} -pin  "ACC1:acc#403" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403.itm}
+load net {ACC1:acc#403.itm(1)} -pin  "ACC1:acc#403" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403.itm}
+load net {ACC1:acc#403.itm(2)} -pin  "ACC1:acc#403" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403.itm}
+load net {ACC1:acc#403.itm(3)} -pin  "ACC1:acc#403" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403.itm}
+load net {ACC1:acc#403.itm(4)} -pin  "ACC1:acc#403" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403.itm}
+load inst "ACC1-3:not#239" "not(1)" "INTERFACE" -attr xrf 53771 -attr oid 1827 -attr @path {/sobel/sobel:core/ACC1-3:not#239} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(3)} -pin  "ACC1-3:not#239" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#16.itm}
+load net {ACC1-3:not#239.itm} -pin  "ACC1-3:not#239" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#239.itm}
+load inst "ACC1-3:not#241" "not(1)" "INTERFACE" -attr xrf 53772 -attr oid 1828 -attr @path {/sobel/sobel:core/ACC1-3:not#241} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(7)} -pin  "ACC1-3:not#241" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#5.itm}
+load net {ACC1-3:not#241.itm} -pin  "ACC1-3:not#241" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#241.itm}
+load inst "ACC1:acc#400" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53773 -attr oid 1829 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#400} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#400" {A(0)} -attr @path {/sobel/sobel:core/conc#1048.itm}
+load net {ACC1:acc#227.psp.sva(2)} -pin  "ACC1:acc#400" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1048.itm}
+load net {ACC1-3:not#241.itm} -pin  "ACC1:acc#400" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1257.itm}
+load net {ACC1-3:not#239.itm} -pin  "ACC1:acc#400" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1257.itm}
+load net {ACC1:acc#400.itm(0)} -pin  "ACC1:acc#400" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#400.itm}
+load net {ACC1:acc#400.itm(1)} -pin  "ACC1:acc#400" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#400.itm}
+load net {ACC1:acc#400.itm(2)} -pin  "ACC1:acc#400" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#400.itm}
+load inst "ACC1-3:not#240" "not(1)" "INTERFACE" -attr xrf 53774 -attr oid 1830 -attr @path {/sobel/sobel:core/ACC1-3:not#240} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(5)} -pin  "ACC1-3:not#240" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#1.itm}
+load net {ACC1-3:not#240.itm} -pin  "ACC1-3:not#240" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#240.itm}
+load inst "ACC1:acc#399" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53775 -attr oid 1831 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#399} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#399" {A(0)} -attr @path {/sobel/sobel:core/conc#1049.itm}
+load net {ACC1:acc#227.psp.sva(4)} -pin  "ACC1:acc#399" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1049.itm}
+load net {ACC1:acc#227.psp.sva(6)} -pin  "ACC1:acc#399" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1255.itm}
+load net {ACC1-3:not#240.itm} -pin  "ACC1:acc#399" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1255.itm}
+load net {ACC1:acc#399.itm(0)} -pin  "ACC1:acc#399" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#399.itm}
+load net {ACC1:acc#399.itm(1)} -pin  "ACC1:acc#399" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#399.itm}
+load net {ACC1:acc#399.itm(2)} -pin  "ACC1:acc#399" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#399.itm}
+load inst "ACC1-3:not#242" "not(1)" "INTERFACE" -attr xrf 53776 -attr oid 1832 -attr @path {/sobel/sobel:core/ACC1-3:not#242} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(9)} -pin  "ACC1-3:not#242" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#4.itm}
+load net {ACC1-3:not#242.itm} -pin  "ACC1-3:not#242" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#242.itm}
+load inst "ACC1:acc#402" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53777 -attr oid 1833 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#402} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#402" {A(0)} -attr @path {/sobel/sobel:core/conc#1047.itm}
+load net {ACC1:acc#400.itm(1)} -pin  "ACC1:acc#402" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1047.itm}
+load net {ACC1:acc#400.itm(2)} -pin  "ACC1:acc#402" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1047.itm}
+load net {ACC1-3:not#242.itm} -pin  "ACC1:acc#402" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1261.itm}
+load net {ACC1:acc#399.itm(1)} -pin  "ACC1:acc#402" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1261.itm}
+load net {ACC1:acc#399.itm(2)} -pin  "ACC1:acc#402" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1261.itm}
+load net {ACC1:acc#402.itm(0)} -pin  "ACC1:acc#402" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#402.itm}
+load net {ACC1:acc#402.itm(1)} -pin  "ACC1:acc#402" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#402.itm}
+load net {ACC1:acc#402.itm(2)} -pin  "ACC1:acc#402" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#402.itm}
+load net {ACC1:acc#402.itm(3)} -pin  "ACC1:acc#402" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#402.itm}
+load inst "ACC1-3:acc#212" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 53778 -attr oid 1834 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#212} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#403.itm(1)} -pin  "ACC1-3:acc#212" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#403.itm(2)} -pin  "ACC1-3:acc#212" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#403.itm(3)} -pin  "ACC1-3:acc#212" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#403.itm(4)} -pin  "ACC1-3:acc#212" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#402.itm(1)} -pin  "ACC1-3:acc#212" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#402.itm(2)} -pin  "ACC1-3:acc#212" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#402.itm(3)} -pin  "ACC1-3:acc#212" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1-3:acc#212.psp.sva(0)} -pin  "ACC1-3:acc#212" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#212.psp.sva}
+load net {ACC1-3:acc#212.psp.sva(1)} -pin  "ACC1-3:acc#212" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#212.psp.sva}
+load net {ACC1-3:acc#212.psp.sva(2)} -pin  "ACC1-3:acc#212" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#212.psp.sva}
+load net {ACC1-3:acc#212.psp.sva(3)} -pin  "ACC1-3:acc#212" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#212.psp.sva}
+load inst "ACC1-3:not#297" "not(2)" "INTERFACE" -attr xrf 53779 -attr oid 1835 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#297} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#222.psp.sva(1)} -pin  "ACC1-3:not#297" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp.sva).itm}
+load net {ACC1:acc#222.psp.sva(2)} -pin  "ACC1-3:not#297" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp.sva).itm}
+load net {ACC1-3:not#297.itm(0)} -pin  "ACC1-3:not#297" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#297.itm}
+load net {ACC1-3:not#297.itm(1)} -pin  "ACC1-3:not#297" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#297.itm}
+load inst "ACC1:acc#414" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 53780 -attr oid 1836 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#414} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#414" {A(0)} -attr @path {/sobel/sobel:core/conc#1050.itm}
+load net {ACC1-3:not#297.itm(0)} -pin  "ACC1:acc#414" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1050.itm}
+load net {ACC1-3:not#297.itm(1)} -pin  "ACC1:acc#414" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1050.itm}
+load net {PWR} -pin  "ACC1:acc#414" {B(0)} -attr @path {/sobel/sobel:core/conc#1051.itm}
+load net {ACC1:acc#222.psp.sva(0)} -pin  "ACC1:acc#414" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1051.itm}
+load net {ACC1:acc#414.itm(0)} -pin  "ACC1:acc#414" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#414.itm}
+load net {ACC1:acc#414.itm(1)} -pin  "ACC1:acc#414" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#414.itm}
+load net {ACC1:acc#414.itm(2)} -pin  "ACC1:acc#414" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#414.itm}
+load net {ACC1:acc#414.itm(3)} -pin  "ACC1:acc#414" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#414.itm}
+load inst "ACC1-2:not#295" "not(2)" "INTERFACE" -attr xrf 53781 -attr oid 1837 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#295} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#221.psp#2.sva(1)} -pin  "ACC1-2:not#295" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp#2.sva).itm}
+load net {ACC1:acc#221.psp#2.sva(2)} -pin  "ACC1-2:not#295" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp#2.sva).itm}
+load net {ACC1-2:not#295.itm(0)} -pin  "ACC1-2:not#295" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#295.itm}
+load net {ACC1-2:not#295.itm(1)} -pin  "ACC1-2:not#295" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#295.itm}
+load inst "ACC1:acc#377" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 53782 -attr oid 1838 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#377} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#377" {A(0)} -attr @path {/sobel/sobel:core/conc#1052.itm}
+load net {ACC1-2:not#295.itm(0)} -pin  "ACC1:acc#377" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1052.itm}
+load net {ACC1-2:not#295.itm(1)} -pin  "ACC1:acc#377" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1052.itm}
+load net {PWR} -pin  "ACC1:acc#377" {B(0)} -attr @path {/sobel/sobel:core/conc#1053.itm}
+load net {ACC1:acc#221.psp#2.sva(0)} -pin  "ACC1:acc#377" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1053.itm}
+load net {ACC1:acc#377.itm(0)} -pin  "ACC1:acc#377" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#377.itm}
+load net {ACC1:acc#377.itm(1)} -pin  "ACC1:acc#377" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#377.itm}
+load net {ACC1:acc#377.itm(2)} -pin  "ACC1:acc#377" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#377.itm}
+load net {ACC1:acc#377.itm(3)} -pin  "ACC1:acc#377" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#377.itm}
+load inst "ACC1-1:not#247" "not(1)" "INTERFACE" -attr xrf 53783 -attr oid 1839 -attr @path {/sobel/sobel:core/ACC1-1:not#247} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp#1.sva(0)} -pin  "ACC1-1:not#247" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#7.itm}
+load net {ACC1-1:not#247.itm} -pin  "ACC1-1:not#247" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#247.itm}
+load inst "ACC1-1:not#248" "not(1)" "INTERFACE" -attr xrf 53784 -attr oid 1840 -attr @path {/sobel/sobel:core/ACC1-1:not#248} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp#1.sva(2)} -pin  "ACC1-1:not#248" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#6.itm}
+load net {ACC1-1:not#248.itm} -pin  "ACC1-1:not#248" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#248.itm}
+load inst "ACC1-1:not#250" "not(1)" "INTERFACE" -attr xrf 53785 -attr oid 1841 -attr @path {/sobel/sobel:core/ACC1-1:not#250} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp#1.sva(6)} -pin  "ACC1-1:not#250" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#1.itm}
+load net {ACC1-1:not#250.itm} -pin  "ACC1-1:not#250" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#250.itm}
+load inst "ACC1:acc#343" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53786 -attr oid 1842 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#343} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#343" {A(0)} -attr @path {/sobel/sobel:core/conc#1056.itm}
+load net {ACC1:acc#224.psp#1.sva(1)} -pin  "ACC1:acc#343" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1056.itm}
+load net {ACC1-1:not#250.itm} -pin  "ACC1:acc#343" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1149.itm}
+load net {ACC1-1:not#248.itm} -pin  "ACC1:acc#343" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1149.itm}
+load net {ACC1:acc#343.itm(0)} -pin  "ACC1:acc#343" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#343.itm}
+load net {ACC1:acc#343.itm(1)} -pin  "ACC1:acc#343" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#343.itm}
+load net {ACC1:acc#343.itm(2)} -pin  "ACC1:acc#343" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#343.itm}
+load inst "ACC1-1:not#251" "not(1)" "INTERFACE" -attr xrf 53787 -attr oid 1843 -attr @path {/sobel/sobel:core/ACC1-1:not#251} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp#1.sva(8)} -pin  "ACC1-1:not#251" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#2.itm}
+load net {ACC1-1:not#251.itm} -pin  "ACC1-1:not#251" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#251.itm}
+load inst "ACC1:acc#345" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 53788 -attr oid 1844 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#345} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#345" {A(0)} -attr @path {/sobel/sobel:core/conc#1055.itm}
+load net {ACC1-1:not#247.itm} -pin  "ACC1:acc#345" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1055.itm}
+load net {GND} -pin  "ACC1:acc#345" {A(2)} -attr @path {/sobel/sobel:core/conc#1055.itm}
+load net {PWR} -pin  "ACC1:acc#345" {A(3)} -attr @path {/sobel/sobel:core/conc#1055.itm}
+load net {ACC1-1:not#251.itm} -pin  "ACC1:acc#345" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1153.itm}
+load net {ACC1:acc#343.itm(1)} -pin  "ACC1:acc#345" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1153.itm}
+load net {ACC1:acc#343.itm(2)} -pin  "ACC1:acc#345" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1153.itm}
+load net {ACC1:acc#345.itm(0)} -pin  "ACC1:acc#345" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#345.itm}
+load net {ACC1:acc#345.itm(1)} -pin  "ACC1:acc#345" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#345.itm}
+load net {ACC1:acc#345.itm(2)} -pin  "ACC1:acc#345" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#345.itm}
+load net {ACC1:acc#345.itm(3)} -pin  "ACC1:acc#345" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#345.itm}
+load inst "ACC1-1:not#249" "not(1)" "INTERFACE" -attr xrf 53789 -attr oid 1845 -attr @path {/sobel/sobel:core/ACC1-1:not#249} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp#1.sva(4)} -pin  "ACC1-1:not#249" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#4.itm}
+load net {ACC1-1:not#249.itm} -pin  "ACC1-1:not#249" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#249.itm}
+load inst "ACC1:acc#342" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53790 -attr oid 1846 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#342" {A(0)} -attr @path {/sobel/sobel:core/conc#1058.itm}
+load net {ACC1:acc#224.psp#1.sva(3)} -pin  "ACC1:acc#342" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1058.itm}
+load net {ACC1:acc#224.psp#1.sva(5)} -pin  "ACC1:acc#342" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1147.itm}
+load net {ACC1-1:not#249.itm} -pin  "ACC1:acc#342" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1147.itm}
+load net {ACC1:acc#342.itm(0)} -pin  "ACC1:acc#342" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(1)} -pin  "ACC1:acc#342" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(2)} -pin  "ACC1:acc#342" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load inst "ACC1-1:not#252" "not(2)" "INTERFACE" -attr xrf 53791 -attr oid 1847 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#252} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#224.psp#1.sva(10)} -pin  "ACC1-1:not#252" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#12.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1-1:not#252" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#12.itm}
+load net {ACC1-1:not#252.itm(0)} -pin  "ACC1-1:not#252" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#252.itm}
+load net {ACC1-1:not#252.itm(1)} -pin  "ACC1-1:not#252" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#252.itm}
+load inst "ACC1:acc#344" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 53792 -attr oid 1848 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#344" {A(0)} -attr @path {/sobel/sobel:core/conc#1057.itm}
+load net {ACC1:acc#342.itm(1)} -pin  "ACC1:acc#344" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1057.itm}
+load net {ACC1:acc#342.itm(2)} -pin  "ACC1:acc#344" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1057.itm}
+load net {ACC1:acc#224.psp#1.sva(7)} -pin  "ACC1:acc#344" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1151.itm}
+load net {ACC1-1:not#252.itm(0)} -pin  "ACC1:acc#344" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1151.itm}
+load net {ACC1-1:not#252.itm(1)} -pin  "ACC1:acc#344" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1151.itm}
+load net {ACC1:acc#344.itm(0)} -pin  "ACC1:acc#344" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:acc#344.itm(1)} -pin  "ACC1:acc#344" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:acc#344.itm(2)} -pin  "ACC1:acc#344" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:acc#344.itm(3)} -pin  "ACC1:acc#344" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:acc#344.itm(4)} -pin  "ACC1:acc#344" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load inst "ACC1:acc#346" "add(4,1,5,-1,5)" "INTERFACE" -attr xrf 53793 -attr oid 1849 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "ACC1:acc#346" {A(0)} -attr @path {/sobel/sobel:core/conc#1054.itm}
+load net {ACC1:acc#345.itm(1)} -pin  "ACC1:acc#346" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1054.itm}
+load net {ACC1:acc#345.itm(2)} -pin  "ACC1:acc#346" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1054.itm}
+load net {ACC1:acc#345.itm(3)} -pin  "ACC1:acc#346" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1054.itm}
+load net {ACC1:acc#224.psp#1.sva(9)} -pin  "ACC1:acc#346" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1155.itm}
+load net {ACC1:acc#344.itm(1)} -pin  "ACC1:acc#346" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1155.itm}
+load net {ACC1:acc#344.itm(2)} -pin  "ACC1:acc#346" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1155.itm}
+load net {ACC1:acc#344.itm(3)} -pin  "ACC1:acc#346" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1155.itm}
+load net {ACC1:acc#344.itm(4)} -pin  "ACC1:acc#346" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1155.itm}
+load net {ACC1:acc#346.itm(0)} -pin  "ACC1:acc#346" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:acc#346.itm(1)} -pin  "ACC1:acc#346" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:acc#346.itm(2)} -pin  "ACC1:acc#346" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:acc#346.itm(3)} -pin  "ACC1:acc#346" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:acc#346.itm(4)} -pin  "ACC1:acc#346" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load inst "ACC1-2:not#291" "not(2)" "INTERFACE" -attr xrf 53794 -attr oid 1850 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#291} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#219.psp#2.sva(1)} -pin  "ACC1-2:not#291" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#2.sva).itm}
+load net {ACC1:acc#219.psp#2.sva(2)} -pin  "ACC1-2:not#291" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#2.sva).itm}
+load net {ACC1-2:not#291.itm(0)} -pin  "ACC1-2:not#291" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#291.itm}
+load net {ACC1-2:not#291.itm(1)} -pin  "ACC1-2:not#291" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#291.itm}
+load inst "ACC1:acc#386" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 53795 -attr oid 1851 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#386} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#386" {A(0)} -attr @path {/sobel/sobel:core/conc#1059.itm}
+load net {ACC1-2:not#291.itm(0)} -pin  "ACC1:acc#386" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1059.itm}
+load net {ACC1-2:not#291.itm(1)} -pin  "ACC1:acc#386" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1059.itm}
+load net {PWR} -pin  "ACC1:acc#386" {B(0)} -attr @path {/sobel/sobel:core/conc#1060.itm}
+load net {ACC1:acc#219.psp#2.sva(0)} -pin  "ACC1:acc#386" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1060.itm}
+load net {ACC1:acc#386.itm(0)} -pin  "ACC1:acc#386" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#386.itm}
+load net {ACC1:acc#386.itm(1)} -pin  "ACC1:acc#386" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#386.itm}
+load net {ACC1:acc#386.itm(2)} -pin  "ACC1:acc#386" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#386.itm}
+load net {ACC1:acc#386.itm(3)} -pin  "ACC1:acc#386" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#386.itm}
+load inst "ACC1-3:not#295" "not(2)" "INTERFACE" -attr xrf 53796 -attr oid 1852 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#295} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#221.psp.sva(1)} -pin  "ACC1-3:not#295" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp.sva).itm}
+load net {ACC1:acc#221.psp.sva(2)} -pin  "ACC1-3:not#295" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp.sva).itm}
+load net {ACC1-3:not#295.itm(0)} -pin  "ACC1-3:not#295" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#295.itm}
+load net {ACC1-3:not#295.itm(1)} -pin  "ACC1-3:not#295" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#295.itm}
+load inst "ACC1:acc#405" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 53797 -attr oid 1853 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#405} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#405" {A(0)} -attr @path {/sobel/sobel:core/conc#1061.itm}
+load net {ACC1-3:not#295.itm(0)} -pin  "ACC1:acc#405" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1061.itm}
+load net {ACC1-3:not#295.itm(1)} -pin  "ACC1:acc#405" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1061.itm}
+load net {PWR} -pin  "ACC1:acc#405" {B(0)} -attr @path {/sobel/sobel:core/conc#1062.itm}
+load net {ACC1:acc#221.psp.sva(0)} -pin  "ACC1:acc#405" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1062.itm}
+load net {ACC1:acc#405.itm(0)} -pin  "ACC1:acc#405" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#405.itm}
+load net {ACC1:acc#405.itm(1)} -pin  "ACC1:acc#405" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#405.itm}
+load net {ACC1:acc#405.itm(2)} -pin  "ACC1:acc#405" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#405.itm}
+load net {ACC1:acc#405.itm(3)} -pin  "ACC1:acc#405" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#405.itm}
+load inst "ACC1-3:not#277" "not(1)" "INTERFACE" -attr xrf 53798 -attr oid 1854 -attr @path {/sobel/sobel:core/ACC1-3:not#277} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-3:acc#212.psp.sva(1)} -pin  "ACC1-3:not#277" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-3:acc#212.psp.sva)#4.itm}
+load net {ACC1-3:not#277.itm} -pin  "ACC1-3:not#277" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#277.itm}
+load inst "ACC1:acc#404" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53799 -attr oid 1855 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#404} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#404" {A(0)} -attr @path {/sobel/sobel:core/conc#1063.itm}
+load net {ACC1-3:acc#212.psp.sva(0)} -pin  "ACC1:acc#404" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1063.itm}
+load net {ACC1-3:acc#212.psp.sva(2)} -pin  "ACC1:acc#404" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1265.itm}
+load net {ACC1-3:not#277.itm} -pin  "ACC1:acc#404" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1265.itm}
+load net {ACC1:acc#404.itm(0)} -pin  "ACC1:acc#404" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#404.itm}
+load net {ACC1:acc#404.itm(1)} -pin  "ACC1:acc#404" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#404.itm}
+load net {ACC1:acc#404.itm(2)} -pin  "ACC1:acc#404" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#404.itm}
+load inst "ACC1:not#320" "not(1)" "INTERFACE" -attr xrf 53800 -attr oid 1856 -attr @path {/sobel/sobel:core/ACC1:not#320} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-3:acc#212.psp.sva(3)} -pin  "ACC1:not#320" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-3:acc#212.psp.sva)#5.itm}
+load net {ACC1:not#320.itm} -pin  "ACC1:not#320" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#320.itm}
+load inst "ACC1-3:acc#221" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 53801 -attr oid 1857 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#221} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#404.itm(1)} -pin  "ACC1-3:acc#221" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:acc#404.itm(2)} -pin  "ACC1-3:acc#221" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:not#320.itm} -pin  "ACC1-3:acc#221" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#320.itm}
+load net {ACC1:acc#221.psp.sva(0)} -pin  "ACC1-3:acc#221" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp.sva}
+load net {ACC1:acc#221.psp.sva(1)} -pin  "ACC1-3:acc#221" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp.sva}
+load net {ACC1:acc#221.psp.sva(2)} -pin  "ACC1-3:acc#221" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp.sva}
+load inst "ACC1-2:not#277" "not(1)" "INTERFACE" -attr xrf 53802 -attr oid 1858 -attr @path {/sobel/sobel:core/ACC1-2:not#277} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#375.itm(2)} -pin  "ACC1-2:not#277" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-2:acc#212.psp.sva)#4.itm}
+load net {ACC1-2:not#277.itm} -pin  "ACC1-2:not#277" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#277.itm}
+load inst "ACC1:acc#376" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53803 -attr oid 1859 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#376} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#376" {A(0)} -attr @path {/sobel/sobel:core/conc#1064.itm}
+load net {ACC1:acc#375.itm(1)} -pin  "ACC1:acc#376" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1064.itm}
+load net {ACC1:acc#375.itm(3)} -pin  "ACC1:acc#376" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1211.itm}
+load net {ACC1-2:not#277.itm} -pin  "ACC1:acc#376" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1211.itm}
+load net {ACC1:acc#376.itm(0)} -pin  "ACC1:acc#376" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#376.itm}
+load net {ACC1:acc#376.itm(1)} -pin  "ACC1:acc#376" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#376.itm}
+load net {ACC1:acc#376.itm(2)} -pin  "ACC1:acc#376" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#376.itm}
+load inst "ACC1:not#318" "not(1)" "INTERFACE" -attr xrf 53804 -attr oid 1860 -attr @path {/sobel/sobel:core/ACC1:not#318} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#375.itm(4)} -pin  "ACC1:not#318" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-2:acc#212.psp.sva)#5.itm}
+load net {ACC1:not#318.itm} -pin  "ACC1:not#318" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#318.itm}
+load inst "ACC1-2:acc#221" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 53805 -attr oid 1861 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:acc#221} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#376.itm(1)} -pin  "ACC1-2:acc#221" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#376.itm(2)} -pin  "ACC1-2:acc#221" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:not#318.itm} -pin  "ACC1-2:acc#221" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#318.itm}
+load net {ACC1:acc#221.psp#2.sva(0)} -pin  "ACC1-2:acc#221" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp#2.sva}
+load net {ACC1:acc#221.psp#2.sva(1)} -pin  "ACC1-2:acc#221" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp#2.sva}
+load net {ACC1:acc#221.psp#2.sva(2)} -pin  "ACC1-2:acc#221" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp#2.sva}
+load inst "ACC1-2:not#269" "not(1)" "INTERFACE" -attr xrf 53806 -attr oid 1862 -attr @path {/sobel/sobel:core/ACC1-2:not#269} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#384.itm(2)} -pin  "ACC1-2:not#269" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-2:acc#208.psp.sva)#4.itm}
+load net {ACC1-2:not#269.itm} -pin  "ACC1-2:not#269" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#269.itm}
+load inst "ACC1:acc#385" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53807 -attr oid 1863 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#385} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#385" {A(0)} -attr @path {/sobel/sobel:core/conc#1065.itm}
+load net {ACC1:acc#384.itm(1)} -pin  "ACC1:acc#385" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1065.itm}
+load net {ACC1:acc#384.itm(3)} -pin  "ACC1:acc#385" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1229.itm}
+load net {ACC1-2:not#269.itm} -pin  "ACC1:acc#385" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1229.itm}
+load net {ACC1:acc#385.itm(0)} -pin  "ACC1:acc#385" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#385.itm}
+load net {ACC1:acc#385.itm(1)} -pin  "ACC1:acc#385" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#385.itm}
+load net {ACC1:acc#385.itm(2)} -pin  "ACC1:acc#385" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#385.itm}
+load inst "ACC1:not#319" "not(1)" "INTERFACE" -attr xrf 53808 -attr oid 1864 -attr @path {/sobel/sobel:core/ACC1:not#319} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#384.itm(4)} -pin  "ACC1:not#319" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-2:acc#208.psp.sva)#5.itm}
+load net {ACC1:not#319.itm} -pin  "ACC1:not#319" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#319.itm}
+load inst "ACC1-2:acc#219" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 53809 -attr oid 1865 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:acc#219} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#385.itm(1)} -pin  "ACC1-2:acc#219" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:acc#385.itm(2)} -pin  "ACC1-2:acc#219" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:not#319.itm} -pin  "ACC1-2:acc#219" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#319.itm}
+load net {ACC1:acc#219.psp#2.sva(0)} -pin  "ACC1-2:acc#219" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#2.sva}
+load net {ACC1:acc#219.psp#2.sva(1)} -pin  "ACC1-2:acc#219" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#2.sva}
+load net {ACC1:acc#219.psp#2.sva(2)} -pin  "ACC1-2:acc#219" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#2.sva}
+load inst "ACC1-1:not#281" "not(1)" "INTERFACE" -attr xrf 53810 -attr oid 1866 -attr @path {/sobel/sobel:core/ACC1-1:not#281} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#346.itm(2)} -pin  "ACC1-1:not#281" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#214.psp#2.sva)#4.itm}
+load net {ACC1-1:not#281.itm} -pin  "ACC1-1:not#281" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#281.itm}
+load inst "ACC1:acc#347" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53811 -attr oid 1867 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#347" {A(0)} -attr @path {/sobel/sobel:core/conc#1066.itm}
+load net {ACC1:acc#346.itm(1)} -pin  "ACC1:acc#347" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1066.itm}
+load net {ACC1:acc#346.itm(3)} -pin  "ACC1:acc#347" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1157.itm}
+load net {ACC1-1:not#281.itm} -pin  "ACC1:acc#347" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1157.itm}
+load net {ACC1:acc#347.itm(0)} -pin  "ACC1:acc#347" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load net {ACC1:acc#347.itm(1)} -pin  "ACC1:acc#347" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load net {ACC1:acc#347.itm(2)} -pin  "ACC1:acc#347" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load inst "ACC1-1:not#303" "not(1)" "INTERFACE" -attr xrf 53812 -attr oid 1868 -attr @path {/sobel/sobel:core/ACC1-1:not#303} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#346.itm(4)} -pin  "ACC1-1:not#303" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#214.psp#2.sva)#5.itm}
+load net {ACC1-1:not#303.itm} -pin  "ACC1-1:not#303" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#303.itm}
+load inst "ACC1-1:acc#225" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 53813 -attr oid 1869 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#225} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#347.itm(1)} -pin  "ACC1-1:acc#225" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#347.itm(2)} -pin  "ACC1-1:acc#225" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1-1:not#303.itm} -pin  "ACC1-1:acc#225" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#303.itm}
+load net {ACC1:acc#222.psp#1.sva(0)} -pin  "ACC1-1:acc#225" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp#1.sva}
+load net {ACC1:acc#222.psp#1.sva(1)} -pin  "ACC1-1:acc#225" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp#1.sva}
+load net {ACC1:acc#222.psp#1.sva(2)} -pin  "ACC1-1:acc#225" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp#1.sva}
+load inst "ACC1-1:not#269" "not(1)" "INTERFACE" -attr xrf 53814 -attr oid 1870 -attr @path {/sobel/sobel:core/ACC1-1:not#269} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#208.psp.sva(1)} -pin  "ACC1-1:not#269" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#208.psp.sva)#4.itm}
+load net {ACC1-1:not#269.itm} -pin  "ACC1-1:not#269" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#269.itm}
+load inst "ACC1:acc#366" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53815 -attr oid 1871 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#366} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#366" {A(0)} -attr @path {/sobel/sobel:core/conc#1067.itm}
+load net {ACC1-1:acc#208.psp.sva(0)} -pin  "ACC1:acc#366" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1067.itm}
+load net {ACC1-1:acc#208.psp.sva(2)} -pin  "ACC1:acc#366" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1193.itm}
+load net {ACC1-1:not#269.itm} -pin  "ACC1:acc#366" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1193.itm}
+load net {ACC1:acc#366.itm(0)} -pin  "ACC1:acc#366" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#366.itm}
+load net {ACC1:acc#366.itm(1)} -pin  "ACC1:acc#366" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#366.itm}
+load net {ACC1:acc#366.itm(2)} -pin  "ACC1:acc#366" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#366.itm}
+load inst "ACC1:not#317" "not(1)" "INTERFACE" -attr xrf 53816 -attr oid 1872 -attr @path {/sobel/sobel:core/ACC1:not#317} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#208.psp.sva(3)} -pin  "ACC1:not#317" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#208.psp.sva)#5.itm}
+load net {ACC1:not#317.itm} -pin  "ACC1:not#317" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#317.itm}
+load inst "ACC1-1:acc#219" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 53817 -attr oid 1873 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#219} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#366.itm(1)} -pin  "ACC1-1:acc#219" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#42.itm}
+load net {ACC1:acc#366.itm(2)} -pin  "ACC1-1:acc#219" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#42.itm}
+load net {ACC1:not#317.itm} -pin  "ACC1-1:acc#219" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#317.itm}
+load net {ACC1:acc#219.psp#1.sva(0)} -pin  "ACC1-1:acc#219" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#1.sva}
+load net {ACC1:acc#219.psp#1.sva(1)} -pin  "ACC1-1:acc#219" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#1.sva}
+load net {ACC1:acc#219.psp#1.sva(2)} -pin  "ACC1-1:acc#219" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#1.sva}
+load inst "ACC1-2:not#185" "not(1)" "INTERFACE" -attr xrf 53818 -attr oid 1874 -attr @path {/sobel/sobel:core/ACC1-2:not#185} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#386.itm(2)} -pin  "ACC1-2:not#185" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#43.sva)#3.itm}
+load net {ACC1-2:not#185.itm} -pin  "ACC1-2:not#185" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#185.itm}
+load inst "ACC1-2:not#186" "not(1)" "INTERFACE" -attr xrf 53819 -attr oid 1875 -attr @path {/sobel/sobel:core/ACC1-2:not#186} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#386.itm(3)} -pin  "ACC1-2:not#186" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#43.sva).itm}
+load net {ACC1-2:not#186.itm} -pin  "ACC1-2:not#186" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#186.itm}
+load inst "ACC1:acc#387" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 53820 -attr oid 1876 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#387} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#387" {A(0)} -attr @path {/sobel/sobel:core/conc#1068.itm}
+load net {ACC1:acc#386.itm(1)} -pin  "ACC1:acc#387" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1068.itm}
+load net {PWR} -pin  "ACC1:acc#387" {A(2)} -attr @path {/sobel/sobel:core/conc#1068.itm}
+load net {ACC1-2:not#186.itm} -pin  "ACC1:acc#387" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1234.itm}
+load net {ACC1-2:not#185.itm} -pin  "ACC1:acc#387" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1234.itm}
+load net {ACC1:acc#387.itm(0)} -pin  "ACC1:acc#387" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#387.itm}
+load net {ACC1:acc#387.itm(1)} -pin  "ACC1:acc#387" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#387.itm}
+load net {ACC1:acc#387.itm(2)} -pin  "ACC1:acc#387" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#387.itm}
+load inst "ACC1-2:not#57" "not(1)" "INTERFACE" -attr xrf 53821 -attr oid 1877 -attr @path {/sobel/sobel:core/ACC1-2:not#57} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#377.itm(2)} -pin  "ACC1-2:not#57" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#31.sva)#3.itm}
+load net {ACC1-2:not#57.itm} -pin  "ACC1-2:not#57" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#57.itm}
+load inst "ACC1-2:not#58" "not(1)" "INTERFACE" -attr xrf 53822 -attr oid 1878 -attr @path {/sobel/sobel:core/ACC1-2:not#58} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#377.itm(3)} -pin  "ACC1-2:not#58" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#31.sva).itm}
+load net {ACC1-2:not#58.itm} -pin  "ACC1-2:not#58" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#58.itm}
+load inst "ACC1:acc#378" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 53823 -attr oid 1879 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#378} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#378" {A(0)} -attr @path {/sobel/sobel:core/conc#1069.itm}
+load net {ACC1:acc#377.itm(1)} -pin  "ACC1:acc#378" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1069.itm}
+load net {PWR} -pin  "ACC1:acc#378" {A(2)} -attr @path {/sobel/sobel:core/conc#1069.itm}
+load net {ACC1-2:not#58.itm} -pin  "ACC1:acc#378" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1216.itm}
+load net {ACC1-2:not#57.itm} -pin  "ACC1:acc#378" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1216.itm}
+load net {ACC1:acc#378.itm(0)} -pin  "ACC1:acc#378" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#378.itm}
+load net {ACC1:acc#378.itm(1)} -pin  "ACC1:acc#378" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#378.itm}
+load net {ACC1:acc#378.itm(2)} -pin  "ACC1:acc#378" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#378.itm}
+load inst "ACC1-3:not#89" "not(1)" "INTERFACE" -attr xrf 53824 -attr oid 1880 -attr @path {/sobel/sobel:core/ACC1-3:not#89} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#414.itm(2)} -pin  "ACC1-3:not#89" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#10.sva)#3.itm}
+load net {ACC1-3:not#89.itm} -pin  "ACC1-3:not#89" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#89.itm}
+load inst "ACC1-3:not#90" "not(1)" "INTERFACE" -attr xrf 53825 -attr oid 1881 -attr @path {/sobel/sobel:core/ACC1-3:not#90} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#414.itm(3)} -pin  "ACC1-3:not#90" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#10.sva).itm}
+load net {ACC1-3:not#90.itm} -pin  "ACC1-3:not#90" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#90.itm}
+load inst "ACC1:acc#415" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 53826 -attr oid 1882 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#415} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#415" {A(0)} -attr @path {/sobel/sobel:core/conc#1070.itm}
+load net {ACC1:acc#414.itm(1)} -pin  "ACC1:acc#415" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1070.itm}
+load net {PWR} -pin  "ACC1:acc#415" {A(2)} -attr @path {/sobel/sobel:core/conc#1070.itm}
+load net {ACC1-3:not#90.itm} -pin  "ACC1:acc#415" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1288.itm}
+load net {ACC1-3:not#89.itm} -pin  "ACC1:acc#415" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1288.itm}
+load net {ACC1:acc#415.itm(0)} -pin  "ACC1:acc#415" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#415.itm}
+load net {ACC1:acc#415.itm(1)} -pin  "ACC1:acc#415" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#415.itm}
+load net {ACC1:acc#415.itm(2)} -pin  "ACC1:acc#415" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#415.itm}
+load inst "ACC1-3:not#25" "not(1)" "INTERFACE" -attr xrf 53827 -attr oid 1883 -attr @path {/sobel/sobel:core/ACC1-3:not#25} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#395.itm(2)} -pin  "ACC1-3:not#25" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#3.itm}
+load net {ACC1-3:not#25.itm} -pin  "ACC1-3:not#25" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#25.itm}
+load inst "ACC1-3:not#26" "not(1)" "INTERFACE" -attr xrf 53828 -attr oid 1884 -attr @path {/sobel/sobel:core/ACC1-3:not#26} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#395.itm(3)} -pin  "ACC1-3:not#26" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva).itm}
+load net {ACC1-3:not#26.itm} -pin  "ACC1-3:not#26" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#26.itm}
+load inst "ACC1:acc#396" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 53829 -attr oid 1885 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#396} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#396" {A(0)} -attr @path {/sobel/sobel:core/conc#1071.itm}
+load net {ACC1:acc#395.itm(1)} -pin  "ACC1:acc#396" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1071.itm}
+load net {PWR} -pin  "ACC1:acc#396" {A(2)} -attr @path {/sobel/sobel:core/conc#1071.itm}
+load net {ACC1-3:not#26.itm} -pin  "ACC1:acc#396" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1252.itm}
+load net {ACC1-3:not#25.itm} -pin  "ACC1:acc#396" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1252.itm}
+load net {ACC1:acc#396.itm(0)} -pin  "ACC1:acc#396" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#396.itm}
+load net {ACC1:acc#396.itm(1)} -pin  "ACC1:acc#396" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#396.itm}
+load net {ACC1:acc#396.itm(2)} -pin  "ACC1:acc#396" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#396.itm}
+load inst "ACC1-3:not#311" "not(1)" "INTERFACE" -attr xrf 53830 -attr oid 1886 -attr @path {/sobel/sobel:core/ACC1-3:not#311} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:not#311" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#32.itm}
+load net {ACC1-3:not#311.itm} -pin  "ACC1-3:not#311" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#311.itm}
+load inst "ACC1-3:not#229" "not(1)" "INTERFACE" -attr xrf 53831 -attr oid 1887 -attr @path {/sobel/sobel:core/ACC1-3:not#229} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(1)} -pin  "ACC1-3:not#229" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#15.itm}
+load net {ACC1-3:not#229.itm} -pin  "ACC1-3:not#229" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#229.itm}
+load inst "ACC1:acc#391" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 53832 -attr oid 1888 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#391} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#391" {A(0)} -attr @path {/sobel/sobel:core/conc#1073.itm}
+load net {ACC1-3:not#311.itm} -pin  "ACC1:acc#391" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1073.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#391" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1241.itm}
+load net {ACC1-3:not#229.itm} -pin  "ACC1:acc#391" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1241.itm}
+load net {ACC1:acc#391.itm(0)} -pin  "ACC1:acc#391" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#391.itm}
+load net {ACC1:acc#391.itm(1)} -pin  "ACC1:acc#391" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#391.itm}
+load net {ACC1:acc#391.itm(2)} -pin  "ACC1:acc#391" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#391.itm}
+load net {ACC1:acc#391.itm(3)} -pin  "ACC1:acc#391" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#391.itm}
+load inst "ACC1:acc#393" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 53833 -attr oid 1889 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#393" {A(0)} -attr @path {/sobel/sobel:core/conc#1072.itm}
+load net {ACC1:acc#391.itm(1)} -pin  "ACC1:acc#393" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1072.itm}
+load net {ACC1:acc#391.itm(2)} -pin  "ACC1:acc#393" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1072.itm}
+load net {ACC1:acc#391.itm(3)} -pin  "ACC1:acc#393" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1072.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#393" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1074.itm}
+load net {acc.psp#1.sva(0)} -pin  "ACC1:acc#393" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1074.itm}
+load net {GND} -pin  "ACC1:acc#393" {B(2)} -attr @path {/sobel/sobel:core/conc#1074.itm}
+load net {PWR} -pin  "ACC1:acc#393" {B(3)} -attr @path {/sobel/sobel:core/conc#1074.itm}
+load net {ACC1:acc#393.itm(0)} -pin  "ACC1:acc#393" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393.itm}
+load net {ACC1:acc#393.itm(1)} -pin  "ACC1:acc#393" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393.itm}
+load net {ACC1:acc#393.itm(2)} -pin  "ACC1:acc#393" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393.itm}
+load net {ACC1:acc#393.itm(3)} -pin  "ACC1:acc#393" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393.itm}
+load net {ACC1:acc#393.itm(4)} -pin  "ACC1:acc#393" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393.itm}
+load inst "ACC1-3:not#230" "not(1)" "INTERFACE" -attr xrf 53834 -attr oid 1890 -attr @path {/sobel/sobel:core/ACC1-3:not#230} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(3)} -pin  "ACC1-3:not#230" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#17.itm}
+load net {ACC1-3:not#230.itm} -pin  "ACC1-3:not#230" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#230.itm}
+load inst "ACC1-3:not#232" "not(1)" "INTERFACE" -attr xrf 53835 -attr oid 1891 -attr @path {/sobel/sobel:core/ACC1-3:not#232} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(7)} -pin  "ACC1-3:not#232" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#1.itm}
+load net {ACC1-3:not#232.itm} -pin  "ACC1-3:not#232" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#232.itm}
+load inst "ACC1:acc#390" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53836 -attr oid 1892 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#390} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#390" {A(0)} -attr @path {/sobel/sobel:core/conc#1076.itm}
+load net {acc.psp#1.sva(2)} -pin  "ACC1:acc#390" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1076.itm}
+load net {ACC1-3:not#232.itm} -pin  "ACC1:acc#390" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1239.itm}
+load net {ACC1-3:not#230.itm} -pin  "ACC1:acc#390" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1239.itm}
+load net {ACC1:acc#390.itm(0)} -pin  "ACC1:acc#390" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#390.itm}
+load net {ACC1:acc#390.itm(1)} -pin  "ACC1:acc#390" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#390.itm}
+load net {ACC1:acc#390.itm(2)} -pin  "ACC1:acc#390" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#390.itm}
+load inst "ACC1-3:not#231" "not(1)" "INTERFACE" -attr xrf 53837 -attr oid 1893 -attr @path {/sobel/sobel:core/ACC1-3:not#231} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(5)} -pin  "ACC1-3:not#231" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#4.itm}
+load net {ACC1-3:not#231.itm} -pin  "ACC1-3:not#231" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#231.itm}
+load inst "ACC1:acc#389" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53838 -attr oid 1894 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#389} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#389" {A(0)} -attr @path {/sobel/sobel:core/conc#1077.itm}
+load net {acc.psp#1.sva(4)} -pin  "ACC1:acc#389" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1077.itm}
+load net {acc.psp#1.sva(6)} -pin  "ACC1:acc#389" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1237.itm}
+load net {ACC1-3:not#231.itm} -pin  "ACC1:acc#389" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1237.itm}
+load net {ACC1:acc#389.itm(0)} -pin  "ACC1:acc#389" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#389.itm}
+load net {ACC1:acc#389.itm(1)} -pin  "ACC1:acc#389" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#389.itm}
+load net {ACC1:acc#389.itm(2)} -pin  "ACC1:acc#389" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#389.itm}
+load inst "ACC1-3:not#233" "not(1)" "INTERFACE" -attr xrf 53839 -attr oid 1895 -attr @path {/sobel/sobel:core/ACC1-3:not#233} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(9)} -pin  "ACC1-3:not#233" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#2.itm}
+load net {ACC1-3:not#233.itm} -pin  "ACC1-3:not#233" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#233.itm}
+load inst "ACC1:acc#392" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53840 -attr oid 1896 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#392} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#392" {A(0)} -attr @path {/sobel/sobel:core/conc#1075.itm}
+load net {ACC1:acc#390.itm(1)} -pin  "ACC1:acc#392" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1075.itm}
+load net {ACC1:acc#390.itm(2)} -pin  "ACC1:acc#392" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1075.itm}
+load net {ACC1-3:not#233.itm} -pin  "ACC1:acc#392" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1243.itm}
+load net {ACC1:acc#389.itm(1)} -pin  "ACC1:acc#392" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1243.itm}
+load net {ACC1:acc#389.itm(2)} -pin  "ACC1:acc#392" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1243.itm}
+load net {ACC1:acc#392.itm(0)} -pin  "ACC1:acc#392" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#392.itm}
+load net {ACC1:acc#392.itm(1)} -pin  "ACC1:acc#392" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#392.itm}
+load net {ACC1:acc#392.itm(2)} -pin  "ACC1:acc#392" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#392.itm}
+load net {ACC1:acc#392.itm(3)} -pin  "ACC1:acc#392" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#392.itm}
+load inst "ACC1-3:acc#210" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 53841 -attr oid 1897 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#210} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#393.itm(1)} -pin  "ACC1-3:acc#210" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#393.itm(2)} -pin  "ACC1-3:acc#210" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#393.itm(3)} -pin  "ACC1-3:acc#210" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#393.itm(4)} -pin  "ACC1-3:acc#210" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#392.itm(1)} -pin  "ACC1-3:acc#210" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#392.itm(2)} -pin  "ACC1-3:acc#210" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#392.itm(3)} -pin  "ACC1-3:acc#210" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#210.psp#1.sva(0)} -pin  "ACC1-3:acc#210" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#1.sva}
+load net {ACC1:acc#210.psp#1.sva(1)} -pin  "ACC1-3:acc#210" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#1.sva}
+load net {ACC1:acc#210.psp#1.sva(2)} -pin  "ACC1-3:acc#210" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#1.sva}
+load net {ACC1:acc#210.psp#1.sva(3)} -pin  "ACC1-3:acc#210" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#1.sva}
+load inst "ACC1-3:not#307" "not(1)" "INTERFACE" -attr xrf 53842 -attr oid 1898 -attr @path {/sobel/sobel:core/ACC1-3:not#307} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1-3:not#307" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#24.itm}
+load net {ACC1-3:not#307.itm} -pin  "ACC1-3:not#307" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#307.itm}
+load inst "ACC1-3:not#260" "not(1)" "INTERFACE" -attr xrf 53843 -attr oid 1899 -attr @path {/sobel/sobel:core/ACC1-3:not#260} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(1)} -pin  "ACC1-3:not#260" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#15.itm}
+load net {ACC1-3:not#260.itm} -pin  "ACC1-3:not#260" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#260.itm}
+load inst "ACC1:acc#419" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 53844 -attr oid 1900 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#419} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#419" {A(0)} -attr @path {/sobel/sobel:core/conc#1079.itm}
+load net {ACC1-3:not#307.itm} -pin  "ACC1:acc#419" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1079.itm}
+load net {acc#20.psp#1.sva(8)} -pin  "ACC1:acc#419" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1295.itm}
+load net {ACC1-3:not#260.itm} -pin  "ACC1:acc#419" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1295.itm}
+load net {ACC1:acc#419.itm(0)} -pin  "ACC1:acc#419" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#419.itm}
+load net {ACC1:acc#419.itm(1)} -pin  "ACC1:acc#419" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#419.itm}
+load net {ACC1:acc#419.itm(2)} -pin  "ACC1:acc#419" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#419.itm}
+load net {ACC1:acc#419.itm(3)} -pin  "ACC1:acc#419" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#419.itm}
+load inst "ACC1:acc#421" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 53845 -attr oid 1901 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#421" {A(0)} -attr @path {/sobel/sobel:core/conc#1078.itm}
+load net {ACC1:acc#419.itm(1)} -pin  "ACC1:acc#421" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1078.itm}
+load net {ACC1:acc#419.itm(2)} -pin  "ACC1:acc#421" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1078.itm}
+load net {ACC1:acc#419.itm(3)} -pin  "ACC1:acc#421" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1078.itm}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1:acc#421" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1080.itm}
+load net {acc#20.psp#1.sva(0)} -pin  "ACC1:acc#421" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1080.itm}
+load net {GND} -pin  "ACC1:acc#421" {B(2)} -attr @path {/sobel/sobel:core/conc#1080.itm}
+load net {PWR} -pin  "ACC1:acc#421" {B(3)} -attr @path {/sobel/sobel:core/conc#1080.itm}
+load net {ACC1:acc#421.itm(0)} -pin  "ACC1:acc#421" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421.itm}
+load net {ACC1:acc#421.itm(1)} -pin  "ACC1:acc#421" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421.itm}
+load net {ACC1:acc#421.itm(2)} -pin  "ACC1:acc#421" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421.itm}
+load net {ACC1:acc#421.itm(3)} -pin  "ACC1:acc#421" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421.itm}
+load net {ACC1:acc#421.itm(4)} -pin  "ACC1:acc#421" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421.itm}
+load inst "ACC1-3:not#261" "not(1)" "INTERFACE" -attr xrf 53846 -attr oid 1902 -attr @path {/sobel/sobel:core/ACC1-3:not#261} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(3)} -pin  "ACC1-3:not#261" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#17.itm}
+load net {ACC1-3:not#261.itm} -pin  "ACC1-3:not#261" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#261.itm}
+load inst "ACC1-3:not#263" "not(1)" "INTERFACE" -attr xrf 53847 -attr oid 1903 -attr @path {/sobel/sobel:core/ACC1-3:not#263} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1-3:not#263" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#2.itm}
+load net {ACC1-3:not#263.itm} -pin  "ACC1-3:not#263" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#263.itm}
+load inst "ACC1:acc#418" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53848 -attr oid 1904 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#418} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#418" {A(0)} -attr @path {/sobel/sobel:core/conc#1082.itm}
+load net {acc#20.psp#1.sva(2)} -pin  "ACC1:acc#418" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1082.itm}
+load net {ACC1-3:not#263.itm} -pin  "ACC1:acc#418" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1293.itm}
+load net {ACC1-3:not#261.itm} -pin  "ACC1:acc#418" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1293.itm}
+load net {ACC1:acc#418.itm(0)} -pin  "ACC1:acc#418" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#418.itm}
+load net {ACC1:acc#418.itm(1)} -pin  "ACC1:acc#418" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#418.itm}
+load net {ACC1:acc#418.itm(2)} -pin  "ACC1:acc#418" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#418.itm}
+load inst "ACC1-3:not#262" "not(1)" "INTERFACE" -attr xrf 53849 -attr oid 1905 -attr @path {/sobel/sobel:core/ACC1-3:not#262} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(5)} -pin  "ACC1-3:not#262" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#14.itm}
+load net {ACC1-3:not#262.itm} -pin  "ACC1-3:not#262" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#262.itm}
+load inst "ACC1:acc#417" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53850 -attr oid 1906 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#417} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#417" {A(0)} -attr @path {/sobel/sobel:core/conc#1083.itm}
+load net {acc#20.psp#1.sva(4)} -pin  "ACC1:acc#417" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1083.itm}
+load net {acc#20.psp#1.sva(6)} -pin  "ACC1:acc#417" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1291.itm}
+load net {ACC1-3:not#262.itm} -pin  "ACC1:acc#417" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1291.itm}
+load net {ACC1:acc#417.itm(0)} -pin  "ACC1:acc#417" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#417.itm}
+load net {ACC1:acc#417.itm(1)} -pin  "ACC1:acc#417" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#417.itm}
+load net {ACC1:acc#417.itm(2)} -pin  "ACC1:acc#417" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#417.itm}
+load inst "ACC1-3:not#264" "not(1)" "INTERFACE" -attr xrf 53851 -attr oid 1907 -attr @path {/sobel/sobel:core/ACC1-3:not#264} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1-3:not#264" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#3.itm}
+load net {ACC1-3:not#264.itm} -pin  "ACC1-3:not#264" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#264.itm}
+load inst "ACC1:acc#420" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53852 -attr oid 1908 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#420} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#420" {A(0)} -attr @path {/sobel/sobel:core/conc#1081.itm}
+load net {ACC1:acc#418.itm(1)} -pin  "ACC1:acc#420" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1081.itm}
+load net {ACC1:acc#418.itm(2)} -pin  "ACC1:acc#420" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1081.itm}
+load net {ACC1-3:not#264.itm} -pin  "ACC1:acc#420" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1297.itm}
+load net {ACC1:acc#417.itm(1)} -pin  "ACC1:acc#420" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1297.itm}
+load net {ACC1:acc#417.itm(2)} -pin  "ACC1:acc#420" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1297.itm}
+load net {ACC1:acc#420.itm(0)} -pin  "ACC1:acc#420" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#420.itm}
+load net {ACC1:acc#420.itm(1)} -pin  "ACC1:acc#420" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#420.itm}
+load net {ACC1:acc#420.itm(2)} -pin  "ACC1:acc#420" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#420.itm}
+load net {ACC1:acc#420.itm(3)} -pin  "ACC1:acc#420" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#420.itm}
+load inst "ACC1-3:acc#217" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 53853 -attr oid 1909 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#217} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#421.itm(1)} -pin  "ACC1-3:acc#217" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#421.itm(2)} -pin  "ACC1-3:acc#217" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#421.itm(3)} -pin  "ACC1-3:acc#217" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#421.itm(4)} -pin  "ACC1-3:acc#217" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#420.itm(1)} -pin  "ACC1-3:acc#217" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#420.itm(2)} -pin  "ACC1-3:acc#217" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#420.itm(3)} -pin  "ACC1-3:acc#217" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#217.psp#1.sva(0)} -pin  "ACC1-3:acc#217" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#1.sva}
+load net {ACC1:acc#217.psp#1.sva(1)} -pin  "ACC1-3:acc#217" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#1.sva}
+load net {ACC1:acc#217.psp#1.sva(2)} -pin  "ACC1-3:acc#217" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#1.sva}
+load net {ACC1:acc#217.psp#1.sva(3)} -pin  "ACC1-3:acc#217" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#1.sva}
+load inst "ACC1-3:not#153" "not(1)" "INTERFACE" -attr xrf 53854 -attr oid 1910 -attr @path {/sobel/sobel:core/ACC1-3:not#153} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#423.itm(2)} -pin  "ACC1-3:not#153" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva)#3.itm}
+load net {ACC1-3:not#153.itm} -pin  "ACC1-3:not#153" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#153.itm}
+load inst "ACC1-3:not#154" "not(1)" "INTERFACE" -attr xrf 53855 -attr oid 1911 -attr @path {/sobel/sobel:core/ACC1-3:not#154} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#423.itm(3)} -pin  "ACC1-3:not#154" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva)#4.itm}
+load net {ACC1-3:not#154.itm} -pin  "ACC1-3:not#154" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#154.itm}
+load inst "ACC1:acc#424" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 53856 -attr oid 1912 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#424} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#424" {A(0)} -attr @path {/sobel/sobel:core/conc#1084.itm}
+load net {ACC1:acc#423.itm(1)} -pin  "ACC1:acc#424" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1084.itm}
+load net {PWR} -pin  "ACC1:acc#424" {A(2)} -attr @path {/sobel/sobel:core/conc#1084.itm}
+load net {ACC1-3:not#154.itm} -pin  "ACC1:acc#424" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1306.itm}
+load net {ACC1-3:not#153.itm} -pin  "ACC1:acc#424" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1306.itm}
+load net {ACC1:acc#424.itm(0)} -pin  "ACC1:acc#424" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#424.itm}
+load net {ACC1:acc#424.itm(1)} -pin  "ACC1:acc#424" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#424.itm}
+load net {ACC1:acc#424.itm(2)} -pin  "ACC1:acc#424" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#424.itm}
+load inst "ACC1:acc#724" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53857 -attr oid 1913 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#724} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#724" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1650.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#724" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1650.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#724" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1607.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#724" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1607.itm}
+load net {ACC1:acc#724.cse(0)} -pin  "ACC1:acc#724" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#724.cse}
+load net {ACC1:acc#724.cse(1)} -pin  "ACC1:acc#724" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#724.cse}
+load net {ACC1:acc#724.cse(2)} -pin  "ACC1:acc#724" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#724.cse}
+load inst "ACC1:acc#319" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 53858 -attr oid 1914 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#319" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#1.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#319" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#2.itm}
+load net {ACC1:acc#319.itm(0)} -pin  "ACC1:acc#319" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(1)} -pin  "ACC1:acc#319" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load inst "ACC1:acc#318" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 53859 -attr oid 1915 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#319.itm(0)} -pin  "ACC1:acc#318" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(1)} -pin  "ACC1:acc#318" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#318" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva).itm}
+load net {ACC1:acc#318.itm(0)} -pin  "ACC1:acc#318" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(1)} -pin  "ACC1:acc#318" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load inst "ACC1:mul#57" "mul(2,0,12,1,14)" "INTERFACE" -attr xrf 53860 -attr oid 1916 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,14)"
+load net {ACC1:acc#318.itm(0)} -pin  "ACC1:mul#57" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(1)} -pin  "ACC1:mul#57" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {PWR} -pin  "ACC1:mul#57" {B(0)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(1)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(2)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(3)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(4)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(5)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(6)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(7)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(8)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {PWR} -pin  "ACC1:mul#57" {B(9)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(10)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {PWR} -pin  "ACC1:mul#57" {B(11)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {ACC1:mul#57.itm(0)} -pin  "ACC1:mul#57" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(1)} -pin  "ACC1:mul#57" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(2)} -pin  "ACC1:mul#57" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(3)} -pin  "ACC1:mul#57" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(4)} -pin  "ACC1:mul#57" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(5)} -pin  "ACC1:mul#57" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(6)} -pin  "ACC1:mul#57" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(7)} -pin  "ACC1:mul#57" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(8)} -pin  "ACC1:mul#57" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(9)} -pin  "ACC1:mul#57" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(10)} -pin  "ACC1:mul#57" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(11)} -pin  "ACC1:mul#57" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(12)} -pin  "ACC1:mul#57" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(13)} -pin  "ACC1:mul#57" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load inst "ACC1-3:not#287" "not(1)" "INTERFACE" -attr xrf 53861 -attr oid 1917 -attr @path {/sobel/sobel:core/ACC1-3:not#287} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#217.psp#1.sva(1)} -pin  "ACC1-3:not#287" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#217.psp#1.sva)#4.itm}
+load net {ACC1-3:not#287.itm} -pin  "ACC1-3:not#287" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#287.itm}
+load inst "ACC1:acc#422" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53862 -attr oid 1918 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#422} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#422" {A(0)} -attr @path {/sobel/sobel:core/conc#1085.itm}
+load net {ACC1:acc#217.psp#1.sva(0)} -pin  "ACC1:acc#422" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1085.itm}
+load net {ACC1:acc#217.psp#1.sva(2)} -pin  "ACC1:acc#422" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1301.itm}
+load net {ACC1-3:not#287.itm} -pin  "ACC1:acc#422" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1301.itm}
+load net {ACC1:acc#422.itm(0)} -pin  "ACC1:acc#422" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#422.itm}
+load net {ACC1:acc#422.itm(1)} -pin  "ACC1:acc#422" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#422.itm}
+load net {ACC1:acc#422.itm(2)} -pin  "ACC1:acc#422" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#422.itm}
+load inst "ACC1-3:not#306" "not(1)" "INTERFACE" -attr xrf 53863 -attr oid 1919 -attr @path {/sobel/sobel:core/ACC1-3:not#306} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#217.psp#1.sva(3)} -pin  "ACC1-3:not#306" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#217.psp#1.sva)#5.itm}
+load net {ACC1-3:not#306.itm} -pin  "ACC1-3:not#306" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#306.itm}
+load inst "ACC1-3:acc#223" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 53864 -attr oid 1920 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#223} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#422.itm(1)} -pin  "ACC1-3:acc#223" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1:acc#422.itm(2)} -pin  "ACC1-3:acc#223" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1-3:not#306.itm} -pin  "ACC1-3:acc#223" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#306.itm}
+load net {ACC1:acc#223.psp.sva(0)} -pin  "ACC1-3:acc#223" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp.sva}
+load net {ACC1:acc#223.psp.sva(1)} -pin  "ACC1-3:acc#223" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp.sva}
+load net {ACC1:acc#223.psp.sva(2)} -pin  "ACC1-3:acc#223" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp.sva}
+load inst "ACC1-1:not#273" "not(1)" "INTERFACE" -attr xrf 53865 -attr oid 1921 -attr @path {/sobel/sobel:core/ACC1-1:not#273} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#210.psp#2.sva(1)} -pin  "ACC1-1:not#273" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#210.psp#2.sva)#5.itm}
+load net {ACC1-1:not#273.itm} -pin  "ACC1-1:not#273" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#273.itm}
+load inst "ACC1:acc#337" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53866 -attr oid 1922 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#337} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#337" {A(0)} -attr @path {/sobel/sobel:core/conc#1086.itm}
+load net {ACC1:acc#210.psp#2.sva(0)} -pin  "ACC1:acc#337" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1086.itm}
+load net {ACC1:acc#210.psp#2.sva(2)} -pin  "ACC1:acc#337" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1139.itm}
+load net {ACC1-1:not#273.itm} -pin  "ACC1:acc#337" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1139.itm}
+load net {ACC1:acc#337.itm(0)} -pin  "ACC1:acc#337" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(1)} -pin  "ACC1:acc#337" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(2)} -pin  "ACC1:acc#337" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load inst "ACC1-1:not#305" "not(1)" "INTERFACE" -attr xrf 53867 -attr oid 1923 -attr @path {/sobel/sobel:core/ACC1-1:not#305} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#210.psp#2.sva(3)} -pin  "ACC1-1:not#305" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#210.psp#2.sva)#3.itm}
+load net {ACC1-1:not#305.itm} -pin  "ACC1-1:not#305" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#305.itm}
+load inst "ACC1-1:acc#220" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 53868 -attr oid 1924 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#220} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#337.itm(1)} -pin  "ACC1-1:acc#220" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#18.itm}
+load net {ACC1:acc#337.itm(2)} -pin  "ACC1-1:acc#220" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#18.itm}
+load net {ACC1-1:not#305.itm} -pin  "ACC1-1:acc#220" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#305.itm}
+load net {ACC1:acc#220.psp#1.sva(0)} -pin  "ACC1-1:acc#220" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#220.psp#1.sva}
+load net {ACC1:acc#220.psp#1.sva(1)} -pin  "ACC1-1:acc#220" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#220.psp#1.sva}
+load net {ACC1:acc#220.psp#1.sva(2)} -pin  "ACC1-1:acc#220" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#220.psp#1.sva}
+load inst "ACC1-3:not#273" "not(1)" "INTERFACE" -attr xrf 53869 -attr oid 1925 -attr @path {/sobel/sobel:core/ACC1-3:not#273} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#210.psp#1.sva(1)} -pin  "ACC1-3:not#273" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#210.psp#1.sva)#4.itm}
+load net {ACC1-3:not#273.itm} -pin  "ACC1-3:not#273" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#273.itm}
+load inst "ACC1:acc#394" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53870 -attr oid 1926 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#394} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#394" {A(0)} -attr @path {/sobel/sobel:core/conc#1087.itm}
+load net {ACC1:acc#210.psp#1.sva(0)} -pin  "ACC1:acc#394" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1087.itm}
+load net {ACC1:acc#210.psp#1.sva(2)} -pin  "ACC1:acc#394" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1247.itm}
+load net {ACC1-3:not#273.itm} -pin  "ACC1:acc#394" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1247.itm}
+load net {ACC1:acc#394.itm(0)} -pin  "ACC1:acc#394" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#394.itm}
+load net {ACC1:acc#394.itm(1)} -pin  "ACC1:acc#394" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#394.itm}
+load net {ACC1:acc#394.itm(2)} -pin  "ACC1:acc#394" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#394.itm}
+load inst "ACC1-3:not#305" "not(1)" "INTERFACE" -attr xrf 53871 -attr oid 1927 -attr @path {/sobel/sobel:core/ACC1-3:not#305} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#210.psp#1.sva(3)} -pin  "ACC1-3:not#305" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#210.psp#1.sva)#5.itm}
+load net {ACC1-3:not#305.itm} -pin  "ACC1-3:not#305" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#305.itm}
+load inst "ACC1-3:acc#220" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 53872 -attr oid 1928 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#220} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#394.itm(1)} -pin  "ACC1-3:acc#220" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1:acc#394.itm(2)} -pin  "ACC1-3:acc#220" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1-3:not#305.itm} -pin  "ACC1-3:acc#220" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#305.itm}
+load net {ACC1:acc#220.psp.sva(0)} -pin  "ACC1-3:acc#220" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.psp.sva}
+load net {ACC1:acc#220.psp.sva(1)} -pin  "ACC1-3:acc#220" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.psp.sva}
+load net {ACC1:acc#220.psp.sva(2)} -pin  "ACC1-3:acc#220" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.psp.sva}
+load inst "ACC1-3:not#281" "not(1)" "INTERFACE" -attr xrf 53873 -attr oid 1929 -attr @path {/sobel/sobel:core/ACC1-3:not#281} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#412.itm(2)} -pin  "ACC1-3:not#281" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#214.psp#1.sva)#4.itm}
+load net {ACC1-3:not#281.itm} -pin  "ACC1-3:not#281" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#281.itm}
+load inst "ACC1:acc#413" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53874 -attr oid 1930 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#413} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#413" {A(0)} -attr @path {/sobel/sobel:core/conc#1088.itm}
+load net {ACC1:acc#412.itm(1)} -pin  "ACC1:acc#413" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1088.itm}
+load net {ACC1:acc#412.itm(3)} -pin  "ACC1:acc#413" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1283.itm}
+load net {ACC1-3:not#281.itm} -pin  "ACC1:acc#413" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1283.itm}
+load net {ACC1:acc#413.itm(0)} -pin  "ACC1:acc#413" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#413.itm}
+load net {ACC1:acc#413.itm(1)} -pin  "ACC1:acc#413" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#413.itm}
+load net {ACC1:acc#413.itm(2)} -pin  "ACC1:acc#413" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#413.itm}
+load inst "ACC1-3:not#303" "not(1)" "INTERFACE" -attr xrf 53875 -attr oid 1931 -attr @path {/sobel/sobel:core/ACC1-3:not#303} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#412.itm(4)} -pin  "ACC1-3:not#303" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#214.psp#1.sva)#5.itm}
+load net {ACC1-3:not#303.itm} -pin  "ACC1-3:not#303" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#303.itm}
+load inst "ACC1-3:acc#225" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 53876 -attr oid 1932 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#225} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#413.itm(1)} -pin  "ACC1-3:acc#225" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#82.itm}
+load net {ACC1:acc#413.itm(2)} -pin  "ACC1-3:acc#225" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#82.itm}
+load net {ACC1-3:not#303.itm} -pin  "ACC1-3:acc#225" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#303.itm}
+load net {ACC1:acc#222.psp.sva(0)} -pin  "ACC1-3:acc#225" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp.sva}
+load net {ACC1:acc#222.psp.sva(1)} -pin  "ACC1-3:acc#225" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp.sva}
+load net {ACC1:acc#222.psp.sva(2)} -pin  "ACC1-3:acc#225" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp.sva}
+load inst "ACC1:acc#673" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53877 -attr oid 1933 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#673" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1641.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#673" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1641.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#673" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1599.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#673" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1599.itm}
+load net {ACC1:acc#673.cse(0)} -pin  "ACC1:acc#673" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#673.cse(1)} -pin  "ACC1:acc#673" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#673.cse(2)} -pin  "ACC1:acc#673" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load inst "regs.operator[]#12:not" "not(10)" "INTERFACE" -attr xrf 53878 -attr oid 1934 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "regs.operator[]#12:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "regs.operator[]#12:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "regs.operator[]#12:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "regs.operator[]#12:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "regs.operator[]#12:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "regs.operator[]#12:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "regs.operator[]#12:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "regs.operator[]#12:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "regs.operator[]#12:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "regs.operator[]#12:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {regs.operator[]#12:not.itm(0)} -pin  "regs.operator[]#12:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(1)} -pin  "regs.operator[]#12:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(2)} -pin  "regs.operator[]#12:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(3)} -pin  "regs.operator[]#12:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(4)} -pin  "regs.operator[]#12:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(5)} -pin  "regs.operator[]#12:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(6)} -pin  "regs.operator[]#12:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(7)} -pin  "regs.operator[]#12:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(8)} -pin  "regs.operator[]#12:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(9)} -pin  "regs.operator[]#12:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load inst "regs.operator[]#13:not" "not(10)" "INTERFACE" -attr xrf 53879 -attr oid 1935 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "regs.operator[]#13:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "regs.operator[]#13:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "regs.operator[]#13:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "regs.operator[]#13:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "regs.operator[]#13:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "regs.operator[]#13:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "regs.operator[]#13:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "regs.operator[]#13:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "regs.operator[]#13:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "regs.operator[]#13:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {regs.operator[]#13:not.itm(0)} -pin  "regs.operator[]#13:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(1)} -pin  "regs.operator[]#13:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(2)} -pin  "regs.operator[]#13:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(3)} -pin  "regs.operator[]#13:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(4)} -pin  "regs.operator[]#13:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(5)} -pin  "regs.operator[]#13:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(6)} -pin  "regs.operator[]#13:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(7)} -pin  "regs.operator[]#13:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(8)} -pin  "regs.operator[]#13:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(9)} -pin  "regs.operator[]#13:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load inst "ACC1:acc#351" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 53880 -attr oid 1936 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.operator[]#12:not.itm(0)} -pin  "ACC1:acc#351" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(1)} -pin  "ACC1:acc#351" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(2)} -pin  "ACC1:acc#351" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(3)} -pin  "ACC1:acc#351" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(4)} -pin  "ACC1:acc#351" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(5)} -pin  "ACC1:acc#351" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(6)} -pin  "ACC1:acc#351" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(7)} -pin  "ACC1:acc#351" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(8)} -pin  "ACC1:acc#351" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(9)} -pin  "ACC1:acc#351" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#13:not.itm(0)} -pin  "ACC1:acc#351" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(1)} -pin  "ACC1:acc#351" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(2)} -pin  "ACC1:acc#351" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(3)} -pin  "ACC1:acc#351" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(4)} -pin  "ACC1:acc#351" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(5)} -pin  "ACC1:acc#351" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(6)} -pin  "ACC1:acc#351" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(7)} -pin  "ACC1:acc#351" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(8)} -pin  "ACC1:acc#351" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(9)} -pin  "ACC1:acc#351" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {ACC1:acc#351.itm(0)} -pin  "ACC1:acc#351" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(1)} -pin  "ACC1:acc#351" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(2)} -pin  "ACC1:acc#351" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(3)} -pin  "ACC1:acc#351" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(4)} -pin  "ACC1:acc#351" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(5)} -pin  "ACC1:acc#351" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(6)} -pin  "ACC1:acc#351" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(7)} -pin  "ACC1:acc#351" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(8)} -pin  "ACC1:acc#351" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(9)} -pin  "ACC1:acc#351" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(10)} -pin  "ACC1:acc#351" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load inst "regs.operator[]#14:not" "not(10)" "INTERFACE" -attr xrf 53881 -attr oid 1937 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "regs.operator[]#14:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "regs.operator[]#14:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "regs.operator[]#14:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "regs.operator[]#14:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "regs.operator[]#14:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "regs.operator[]#14:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "regs.operator[]#14:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "regs.operator[]#14:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "regs.operator[]#14:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "regs.operator[]#14:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {regs.operator[]#14:not.itm(0)} -pin  "regs.operator[]#14:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(1)} -pin  "regs.operator[]#14:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(2)} -pin  "regs.operator[]#14:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(3)} -pin  "regs.operator[]#14:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(4)} -pin  "regs.operator[]#14:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(5)} -pin  "regs.operator[]#14:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(6)} -pin  "regs.operator[]#14:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(7)} -pin  "regs.operator[]#14:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(8)} -pin  "regs.operator[]#14:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(9)} -pin  "regs.operator[]#14:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load inst "ACC1:acc#350" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 53882 -attr oid 1938 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.operator[]#14:not.itm(0)} -pin  "ACC1:acc#350" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(1)} -pin  "ACC1:acc#350" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(2)} -pin  "ACC1:acc#350" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(3)} -pin  "ACC1:acc#350" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(4)} -pin  "ACC1:acc#350" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(5)} -pin  "ACC1:acc#350" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(6)} -pin  "ACC1:acc#350" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(7)} -pin  "ACC1:acc#350" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(8)} -pin  "ACC1:acc#350" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(9)} -pin  "ACC1:acc#350" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {PWR} -pin  "ACC1:acc#350" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#350" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#350.itm(0)} -pin  "ACC1:acc#350" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(1)} -pin  "ACC1:acc#350" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(2)} -pin  "ACC1:acc#350" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(3)} -pin  "ACC1:acc#350" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(4)} -pin  "ACC1:acc#350" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(5)} -pin  "ACC1:acc#350" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(6)} -pin  "ACC1:acc#350" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(7)} -pin  "ACC1:acc#350" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(8)} -pin  "ACC1:acc#350" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(9)} -pin  "ACC1:acc#350" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(10)} -pin  "ACC1:acc#350" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load inst "ACC1-1:acc#20" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 53883 -attr oid 1939 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#20} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#351.itm(0)} -pin  "ACC1-1:acc#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(1)} -pin  "ACC1-1:acc#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(2)} -pin  "ACC1-1:acc#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(3)} -pin  "ACC1-1:acc#20" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(4)} -pin  "ACC1-1:acc#20" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(5)} -pin  "ACC1-1:acc#20" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(6)} -pin  "ACC1-1:acc#20" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(7)} -pin  "ACC1-1:acc#20" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(8)} -pin  "ACC1-1:acc#20" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(9)} -pin  "ACC1-1:acc#20" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(10)} -pin  "ACC1-1:acc#20" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#350.itm(0)} -pin  "ACC1-1:acc#20" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(1)} -pin  "ACC1-1:acc#20" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(2)} -pin  "ACC1-1:acc#20" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(3)} -pin  "ACC1-1:acc#20" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(4)} -pin  "ACC1-1:acc#20" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(5)} -pin  "ACC1-1:acc#20" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(6)} -pin  "ACC1-1:acc#20" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(7)} -pin  "ACC1-1:acc#20" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(8)} -pin  "ACC1-1:acc#20" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(9)} -pin  "ACC1-1:acc#20" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(10)} -pin  "ACC1-1:acc#20" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {acc#20.psp#2.sva(0)} -pin  "ACC1-1:acc#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(1)} -pin  "ACC1-1:acc#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(2)} -pin  "ACC1-1:acc#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(3)} -pin  "ACC1-1:acc#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(4)} -pin  "ACC1-1:acc#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(5)} -pin  "ACC1-1:acc#20" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(6)} -pin  "ACC1-1:acc#20" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(7)} -pin  "ACC1-1:acc#20" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(8)} -pin  "ACC1-1:acc#20" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1-1:acc#20" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1-1:acc#20" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:acc#20" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load inst "ACC1-1:not#153" "not(1)" "INTERFACE" -attr xrf 53884 -attr oid 1940 -attr @path {/sobel/sobel:core/ACC1-1:not#153} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#358.itm(2)} -pin  "ACC1-1:not#153" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#38.sva)#3.itm}
+load net {ACC1-1:not#153.itm} -pin  "ACC1-1:not#153" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#153.itm}
+load inst "ACC1-1:not#315" "not(1)" "INTERFACE" -attr xrf 53885 -attr oid 1941 -attr @path {/sobel/sobel:core/ACC1-1:not#315} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#358.itm(3)} -pin  "ACC1-1:not#315" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#38.sva).itm}
+load net {ACC1-1:not#315.itm} -pin  "ACC1-1:not#315" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#315.itm}
+load inst "ACC1:acc#359" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 53886 -attr oid 1942 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#359} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#359" {A(0)} -attr @path {/sobel/sobel:core/conc#1089.itm}
+load net {ACC1:acc#358.itm(1)} -pin  "ACC1:acc#359" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1089.itm}
+load net {PWR} -pin  "ACC1:acc#359" {A(2)} -attr @path {/sobel/sobel:core/conc#1089.itm}
+load net {ACC1-1:not#315.itm} -pin  "ACC1:acc#359" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1180.itm}
+load net {ACC1-1:not#153.itm} -pin  "ACC1:acc#359" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1180.itm}
+load net {ACC1:acc#359.itm(0)} -pin  "ACC1:acc#359" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#359.itm}
+load net {ACC1:acc#359.itm(1)} -pin  "ACC1:acc#359" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#359.itm}
+load net {ACC1:acc#359.itm(2)} -pin  "ACC1:acc#359" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#359.itm}
+load inst "ACC1-1:not#299" "not(2)" "INTERFACE" -attr xrf 53887 -attr oid 1943 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#299} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#223.psp#1.sva(1)} -pin  "ACC1-1:not#299" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp#1.sva).itm}
+load net {ACC1:acc#223.psp#1.sva(2)} -pin  "ACC1-1:not#299" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp#1.sva).itm}
+load net {ACC1-1:not#299.itm(0)} -pin  "ACC1-1:not#299" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#299.itm}
+load net {ACC1-1:not#299.itm(1)} -pin  "ACC1-1:not#299" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#299.itm}
+load inst "ACC1:acc#358" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 53888 -attr oid 1944 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#358} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#358" {A(0)} -attr @path {/sobel/sobel:core/conc#1090.itm}
+load net {ACC1-1:not#299.itm(0)} -pin  "ACC1:acc#358" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1090.itm}
+load net {ACC1-1:not#299.itm(1)} -pin  "ACC1:acc#358" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1090.itm}
+load net {PWR} -pin  "ACC1:acc#358" {B(0)} -attr @path {/sobel/sobel:core/conc#1091.itm}
+load net {ACC1:acc#223.psp#1.sva(0)} -pin  "ACC1:acc#358" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1091.itm}
+load net {ACC1:acc#358.itm(0)} -pin  "ACC1:acc#358" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#358.itm}
+load net {ACC1:acc#358.itm(1)} -pin  "ACC1:acc#358" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#358.itm}
+load net {ACC1:acc#358.itm(2)} -pin  "ACC1:acc#358" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#358.itm}
+load net {ACC1:acc#358.itm(3)} -pin  "ACC1:acc#358" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#358.itm}
+load inst "ACC1-1:not#313" "not(1)" "INTERFACE" -attr xrf 53889 -attr oid 1945 -attr @path {/sobel/sobel:core/ACC1-1:not#313} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:not#313" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#32.itm}
+load net {ACC1-1:not#313.itm} -pin  "ACC1-1:not#313" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#313.itm}
+load inst "ACC1-1:not#260" "not(1)" "INTERFACE" -attr xrf 53890 -attr oid 1946 -attr @path {/sobel/sobel:core/ACC1-1:not#260} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(1)} -pin  "ACC1-1:not#260" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#8.itm}
+load net {ACC1-1:not#260.itm} -pin  "ACC1-1:not#260" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#260.itm}
+load inst "ACC1:acc#354" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 53891 -attr oid 1947 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#354} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#354" {A(0)} -attr @path {/sobel/sobel:core/conc#1093.itm}
+load net {ACC1-1:not#313.itm} -pin  "ACC1:acc#354" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1093.itm}
+load net {acc#20.psp#2.sva(8)} -pin  "ACC1:acc#354" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1169.itm}
+load net {ACC1-1:not#260.itm} -pin  "ACC1:acc#354" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1169.itm}
+load net {ACC1:acc#354.itm(0)} -pin  "ACC1:acc#354" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#354.itm}
+load net {ACC1:acc#354.itm(1)} -pin  "ACC1:acc#354" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#354.itm}
+load net {ACC1:acc#354.itm(2)} -pin  "ACC1:acc#354" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#354.itm}
+load net {ACC1:acc#354.itm(3)} -pin  "ACC1:acc#354" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#354.itm}
+load inst "ACC1:acc#356" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 53892 -attr oid 1948 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#356" {A(0)} -attr @path {/sobel/sobel:core/conc#1092.itm}
+load net {ACC1:acc#354.itm(1)} -pin  "ACC1:acc#356" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1092.itm}
+load net {ACC1:acc#354.itm(2)} -pin  "ACC1:acc#356" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1092.itm}
+load net {ACC1:acc#354.itm(3)} -pin  "ACC1:acc#356" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1092.itm}
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1:acc#356" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1094.itm}
+load net {acc#20.psp#2.sva(0)} -pin  "ACC1:acc#356" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1094.itm}
+load net {GND} -pin  "ACC1:acc#356" {B(2)} -attr @path {/sobel/sobel:core/conc#1094.itm}
+load net {PWR} -pin  "ACC1:acc#356" {B(3)} -attr @path {/sobel/sobel:core/conc#1094.itm}
+load net {ACC1:acc#356.itm(0)} -pin  "ACC1:acc#356" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356.itm}
+load net {ACC1:acc#356.itm(1)} -pin  "ACC1:acc#356" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356.itm}
+load net {ACC1:acc#356.itm(2)} -pin  "ACC1:acc#356" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356.itm}
+load net {ACC1:acc#356.itm(3)} -pin  "ACC1:acc#356" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356.itm}
+load net {ACC1:acc#356.itm(4)} -pin  "ACC1:acc#356" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356.itm}
+load inst "ACC1-1:not#261" "not(1)" "INTERFACE" -attr xrf 53893 -attr oid 1949 -attr @path {/sobel/sobel:core/ACC1-1:not#261} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(3)} -pin  "ACC1-1:not#261" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#7.itm}
+load net {ACC1-1:not#261.itm} -pin  "ACC1-1:not#261" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#261.itm}
+load inst "ACC1-1:not#263" "not(1)" "INTERFACE" -attr xrf 53894 -attr oid 1950 -attr @path {/sobel/sobel:core/ACC1-1:not#263} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(7)} -pin  "ACC1-1:not#263" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#3.itm}
+load net {ACC1-1:not#263.itm} -pin  "ACC1-1:not#263" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#263.itm}
+load inst "ACC1:acc#353" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53895 -attr oid 1951 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#353} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#353" {A(0)} -attr @path {/sobel/sobel:core/conc#1096.itm}
+load net {acc#20.psp#2.sva(2)} -pin  "ACC1:acc#353" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1096.itm}
+load net {ACC1-1:not#263.itm} -pin  "ACC1:acc#353" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1167.itm}
+load net {ACC1-1:not#261.itm} -pin  "ACC1:acc#353" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1167.itm}
+load net {ACC1:acc#353.itm(0)} -pin  "ACC1:acc#353" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#353.itm}
+load net {ACC1:acc#353.itm(1)} -pin  "ACC1:acc#353" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#353.itm}
+load net {ACC1:acc#353.itm(2)} -pin  "ACC1:acc#353" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#353.itm}
+load inst "ACC1-1:not#262" "not(1)" "INTERFACE" -attr xrf 53896 -attr oid 1952 -attr @path {/sobel/sobel:core/ACC1-1:not#262} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(5)} -pin  "ACC1-1:not#262" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#2.itm}
+load net {ACC1-1:not#262.itm} -pin  "ACC1-1:not#262" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#262.itm}
+load inst "ACC1:acc#352" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53897 -attr oid 1953 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#352} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#352" {A(0)} -attr @path {/sobel/sobel:core/conc#1097.itm}
+load net {acc#20.psp#2.sva(4)} -pin  "ACC1:acc#352" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1097.itm}
+load net {acc#20.psp#2.sva(6)} -pin  "ACC1:acc#352" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1165.itm}
+load net {ACC1-1:not#262.itm} -pin  "ACC1:acc#352" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1165.itm}
+load net {ACC1:acc#352.itm(0)} -pin  "ACC1:acc#352" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#352.itm}
+load net {ACC1:acc#352.itm(1)} -pin  "ACC1:acc#352" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#352.itm}
+load net {ACC1:acc#352.itm(2)} -pin  "ACC1:acc#352" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#352.itm}
+load inst "ACC1-1:not#264" "not(1)" "INTERFACE" -attr xrf 53898 -attr oid 1954 -attr @path {/sobel/sobel:core/ACC1-1:not#264} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1-1:not#264" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#59.itm}
+load net {ACC1-1:not#264.itm} -pin  "ACC1-1:not#264" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#264.itm}
+load inst "ACC1:acc#355" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 53899 -attr oid 1955 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#355} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#355" {A(0)} -attr @path {/sobel/sobel:core/conc#1095.itm}
+load net {ACC1:acc#353.itm(1)} -pin  "ACC1:acc#355" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1095.itm}
+load net {ACC1:acc#353.itm(2)} -pin  "ACC1:acc#355" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1095.itm}
+load net {ACC1-1:not#264.itm} -pin  "ACC1:acc#355" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1171.itm}
+load net {ACC1:acc#352.itm(1)} -pin  "ACC1:acc#355" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1171.itm}
+load net {ACC1:acc#352.itm(2)} -pin  "ACC1:acc#355" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1171.itm}
+load net {ACC1:acc#355.itm(0)} -pin  "ACC1:acc#355" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#355.itm}
+load net {ACC1:acc#355.itm(1)} -pin  "ACC1:acc#355" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#355.itm}
+load net {ACC1:acc#355.itm(2)} -pin  "ACC1:acc#355" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#355.itm}
+load net {ACC1:acc#355.itm(3)} -pin  "ACC1:acc#355" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#355.itm}
+load inst "ACC1-1:acc#217" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 53900 -attr oid 1956 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#217} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#356.itm(1)} -pin  "ACC1-1:acc#217" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#356.itm(2)} -pin  "ACC1-1:acc#217" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#356.itm(3)} -pin  "ACC1-1:acc#217" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#356.itm(4)} -pin  "ACC1-1:acc#217" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#355.itm(1)} -pin  "ACC1-1:acc#217" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#32.itm}
+load net {ACC1:acc#355.itm(2)} -pin  "ACC1-1:acc#217" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#32.itm}
+load net {ACC1:acc#355.itm(3)} -pin  "ACC1-1:acc#217" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#32.itm}
+load net {ACC1:acc#217.psp#2.sva(0)} -pin  "ACC1-1:acc#217" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#2.sva}
+load net {ACC1:acc#217.psp#2.sva(1)} -pin  "ACC1-1:acc#217" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#2.sva}
+load net {ACC1:acc#217.psp#2.sva(2)} -pin  "ACC1-1:acc#217" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#2.sva}
+load net {ACC1:acc#217.psp#2.sva(3)} -pin  "ACC1-1:acc#217" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#2.sva}
+load inst "ACC1-1:not#287" "not(1)" "INTERFACE" -attr xrf 53901 -attr oid 1957 -attr @path {/sobel/sobel:core/ACC1-1:not#287} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#217.psp#2.sva(1)} -pin  "ACC1-1:not#287" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#217.psp#2.sva)#4.itm}
+load net {ACC1-1:not#287.itm} -pin  "ACC1-1:not#287" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#287.itm}
+load inst "ACC1:acc#357" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53902 -attr oid 1958 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#357} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#357" {A(0)} -attr @path {/sobel/sobel:core/conc#1098.itm}
+load net {ACC1:acc#217.psp#2.sva(0)} -pin  "ACC1:acc#357" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1098.itm}
+load net {ACC1:acc#217.psp#2.sva(2)} -pin  "ACC1:acc#357" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1175.itm}
+load net {ACC1-1:not#287.itm} -pin  "ACC1:acc#357" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1175.itm}
+load net {ACC1:acc#357.itm(0)} -pin  "ACC1:acc#357" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#357.itm}
+load net {ACC1:acc#357.itm(1)} -pin  "ACC1:acc#357" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#357.itm}
+load net {ACC1:acc#357.itm(2)} -pin  "ACC1:acc#357" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#357.itm}
+load inst "ACC1-1:not#306" "not(1)" "INTERFACE" -attr xrf 53903 -attr oid 1959 -attr @path {/sobel/sobel:core/ACC1-1:not#306} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#217.psp#2.sva(3)} -pin  "ACC1-1:not#306" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#217.psp#2.sva)#1.itm}
+load net {ACC1-1:not#306.itm} -pin  "ACC1-1:not#306" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#306.itm}
+load inst "ACC1-1:acc#223" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 53904 -attr oid 1960 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#223} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#357.itm(1)} -pin  "ACC1-1:acc#223" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#357.itm(2)} -pin  "ACC1-1:acc#223" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1-1:not#306.itm} -pin  "ACC1-1:acc#223" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#306.itm}
+load net {ACC1:acc#223.psp#1.sva(0)} -pin  "ACC1-1:acc#223" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp#1.sva}
+load net {ACC1:acc#223.psp#1.sva(1)} -pin  "ACC1-1:acc#223" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp#1.sva}
+load net {ACC1:acc#223.psp#1.sva(2)} -pin  "ACC1-1:acc#223" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp#1.sva}
+load inst "ACC1:acc#699" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 53905 -attr oid 1961 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#699" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1655.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#699" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1655.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#699" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1611.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#699" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1611.itm}
+load net {ACC1:acc#699.cse(0)} -pin  "ACC1:acc#699" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#699.cse(1)} -pin  "ACC1:acc#699" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#699.cse(2)} -pin  "ACC1:acc#699" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load inst "ACC1-1:not#25" "not(1)" "INTERFACE" -attr xrf 53906 -attr oid 1962 -attr @path {/sobel/sobel:core/ACC1-1:not#25} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#338.itm(2)} -pin  "ACC1-1:not#25" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#26.sva)#4.itm}
+load net {ACC1-1:not#25.itm} -pin  "ACC1-1:not#25" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#25.itm}
+load inst "ACC1-1:not#309" "not(1)" "INTERFACE" -attr xrf 53907 -attr oid 1963 -attr @path {/sobel/sobel:core/ACC1-1:not#309} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#338.itm(3)} -pin  "ACC1-1:not#309" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#26.sva)#2.itm}
+load net {ACC1-1:not#309.itm} -pin  "ACC1-1:not#309" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#309.itm}
+load inst "ACC1:acc#339" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 53908 -attr oid 1964 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#339} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#339" {A(0)} -attr @path {/sobel/sobel:core/conc#1099.itm}
+load net {ACC1:acc#338.itm(1)} -pin  "ACC1:acc#339" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1099.itm}
+load net {PWR} -pin  "ACC1:acc#339" {A(2)} -attr @path {/sobel/sobel:core/conc#1099.itm}
+load net {ACC1-1:not#309.itm} -pin  "ACC1:acc#339" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1144.itm}
+load net {ACC1-1:not#25.itm} -pin  "ACC1:acc#339" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1144.itm}
+load net {ACC1:acc#339.itm(0)} -pin  "ACC1:acc#339" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(1)} -pin  "ACC1:acc#339" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(2)} -pin  "ACC1:acc#339" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+### END MODULE 
+
+module new "sobel" "orig"
+load portBus {vin:rsc.z(89:0)} input 90 {vin:rsc.z(89)} {vin:rsc.z(88)} {vin:rsc.z(87)} {vin:rsc.z(86)} {vin:rsc.z(85)} {vin:rsc.z(84)} {vin:rsc.z(83)} {vin:rsc.z(82)} {vin:rsc.z(81)} {vin:rsc.z(80)} {vin:rsc.z(79)} {vin:rsc.z(78)} {vin:rsc.z(77)} {vin:rsc.z(76)} {vin:rsc.z(75)} {vin:rsc.z(74)} {vin:rsc.z(73)} {vin:rsc.z(72)} {vin:rsc.z(71)} {vin:rsc.z(70)} {vin:rsc.z(69)} {vin:rsc.z(68)} {vin:rsc.z(67)} {vin:rsc.z(66)} {vin:rsc.z(65)} {vin:rsc.z(64)} {vin:rsc.z(63)} {vin:rsc.z(62)} {vin:rsc.z(61)} {vin:rsc.z(60)} {vin:rsc.z(59)} {vin:rsc.z(58)} {vin:rsc.z(57)} {vin:rsc.z(56)} {vin:rsc.z(55)} {vin:rsc.z(54)} {vin:rsc.z(53)} {vin:rsc.z(52)} {vin:rsc.z(51)} {vin:rsc.z(50)} {vin:rsc.z(49)} {vin:rsc.z(48)} {vin:rsc.z(47)} {vin:rsc.z(46)} {vin:rsc.z(45)} {vin:rsc.z(44)} {vin:rsc.z(43)} {vin:rsc.z(42)} {vin:rsc.z(41)} {vin:rsc.z(40)} {vin:rsc.z(39)} {vin:rsc.z(38)} {vin:rsc.z(37)} {vin:rsc.z(36)} {vin:rsc.z(35)} {vin:rsc.z(34)} {vin:rsc.z(33)} {vin:rsc.z(32)} {vin:rsc.z(31)} {vin:rsc.z(30)} {vin:rsc.z(29)} {vin:rsc.z(28)} {vin:rsc.z(27)} {vin:rsc.z(26)} {vin:rsc.z(25)} {vin:rsc.z(24)} {vin:rsc.z(23)} {vin:rsc.z(22)} {vin:rsc.z(21)} {vin:rsc.z(20)} {vin:rsc.z(19)} {vin:rsc.z(18)} {vin:rsc.z(17)} {vin:rsc.z(16)} {vin:rsc.z(15)} {vin:rsc.z(14)} {vin:rsc.z(13)} {vin:rsc.z(12)} {vin:rsc.z(11)} {vin:rsc.z(10)} {vin:rsc.z(9)} {vin:rsc.z(8)} {vin:rsc.z(7)} {vin:rsc.z(6)} {vin:rsc.z(5)} {vin:rsc.z(4)} {vin:rsc.z(3)} {vin:rsc.z(2)} {vin:rsc.z(1)} {vin:rsc.z(0)} -attr xrf 53909 -attr oid 1965 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load portBus {vout:rsc.z(29:0)} output 30 {vout:rsc.z(29)} {vout:rsc.z(28)} {vout:rsc.z(27)} {vout:rsc.z(26)} {vout:rsc.z(25)} {vout:rsc.z(24)} {vout:rsc.z(23)} {vout:rsc.z(22)} {vout:rsc.z(21)} {vout:rsc.z(20)} {vout:rsc.z(19)} {vout:rsc.z(18)} {vout:rsc.z(17)} {vout:rsc.z(16)} {vout:rsc.z(15)} {vout:rsc.z(14)} {vout:rsc.z(13)} {vout:rsc.z(12)} {vout:rsc.z(11)} {vout:rsc.z(10)} {vout:rsc.z(9)} {vout:rsc.z(8)} {vout:rsc.z(7)} {vout:rsc.z(6)} {vout:rsc.z(5)} {vout:rsc.z(4)} {vout:rsc.z(3)} {vout:rsc.z(2)} {vout:rsc.z(1)} {vout:rsc.z(0)} -attr xrf 53910 -attr oid 1966 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load port {clk} input -attr xrf 53911 -attr oid 1967 -attr vt d -attr @path {/sobel/clk}
+load port {en} input -attr xrf 53912 -attr oid 1968 -attr vt d -attr @path {/sobel/en}
+load port {arst_n} input -attr xrf 53913 -attr oid 1969 -attr vt d -attr @path {/sobel/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(89:0)} output 90 {d(89)} {d(88)} {d(87)} {d(86)} {d(85)} {d(84)} {d(83)} {d(82)} {d(81)} {d(80)} {d(79)} {d(78)} {d(77)} {d(76)} {d(75)} {d(74)} {d(73)} {d(72)} {d(71)} {d(70)} {d(69)} {d(68)} {d(67)} {d(66)} {d(65)} {d(64)} {d(63)} {d(62)} {d(61)} {d(60)} {d(59)} {d(58)} {d(57)} {d(56)} {d(55)} {d(54)} {d(53)} {d(52)} {d(51)} {d(50)} {d(49)} {d(48)} {d(47)} {d(46)} {d(45)} {d(44)} {d(43)} {d(42)} {d(41)} {d(40)} {d(39)} {d(38)} {d(37)} {d(36)} {d(35)} {d(34)} {d(33)} {d(32)} {d(31)} {d(30)} {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(89:0)} input 90 {z(89)} {z(88)} {z(87)} {z(86)} {z(85)} {z(84)} {z(83)} {z(82)} {z(81)} {z(80)} {z(79)} {z(78)} {z(77)} {z(76)} {z(75)} {z(74)} {z(73)} {z(72)} {z(71)} {z(70)} {z(69)} {z(68)} {z(67)} {z(66)} {z(65)} {z(64)} {z(63)} {z(62)} {z(61)} {z(60)} {z(59)} {z(58)} {z(57)} {z(56)} {z(55)} {z(54)} {z(53)} {z(52)} {z(51)} {z(50)} {z(49)} {z(48)} {z(47)} {z(46)} {z(45)} {z(44)} {z(43)} {z(42)} {z(41)} {z(40)} {z(39)} {z(38)} {z(37)} {z(36)} {z(35)} {z(34)} {z(33)} {z(32)} {z(31)} {z(30)} {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(29:0)} input 30 {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(29:0)} output 30 {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "sobel:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} \
+     portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} \
+
+load net {vin:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d#1} 90 {vin:rsc:mgc_in_wire.d#1(0)} {vin:rsc:mgc_in_wire.d#1(1)} {vin:rsc:mgc_in_wire.d#1(2)} {vin:rsc:mgc_in_wire.d#1(3)} {vin:rsc:mgc_in_wire.d#1(4)} {vin:rsc:mgc_in_wire.d#1(5)} {vin:rsc:mgc_in_wire.d#1(6)} {vin:rsc:mgc_in_wire.d#1(7)} {vin:rsc:mgc_in_wire.d#1(8)} {vin:rsc:mgc_in_wire.d#1(9)} {vin:rsc:mgc_in_wire.d#1(10)} {vin:rsc:mgc_in_wire.d#1(11)} {vin:rsc:mgc_in_wire.d#1(12)} {vin:rsc:mgc_in_wire.d#1(13)} {vin:rsc:mgc_in_wire.d#1(14)} {vin:rsc:mgc_in_wire.d#1(15)} {vin:rsc:mgc_in_wire.d#1(16)} {vin:rsc:mgc_in_wire.d#1(17)} {vin:rsc:mgc_in_wire.d#1(18)} {vin:rsc:mgc_in_wire.d#1(19)} {vin:rsc:mgc_in_wire.d#1(20)} {vin:rsc:mgc_in_wire.d#1(21)} {vin:rsc:mgc_in_wire.d#1(22)} {vin:rsc:mgc_in_wire.d#1(23)} {vin:rsc:mgc_in_wire.d#1(24)} {vin:rsc:mgc_in_wire.d#1(25)} {vin:rsc:mgc_in_wire.d#1(26)} {vin:rsc:mgc_in_wire.d#1(27)} {vin:rsc:mgc_in_wire.d#1(28)} {vin:rsc:mgc_in_wire.d#1(29)} {vin:rsc:mgc_in_wire.d#1(30)} {vin:rsc:mgc_in_wire.d#1(31)} {vin:rsc:mgc_in_wire.d#1(32)} {vin:rsc:mgc_in_wire.d#1(33)} {vin:rsc:mgc_in_wire.d#1(34)} {vin:rsc:mgc_in_wire.d#1(35)} {vin:rsc:mgc_in_wire.d#1(36)} {vin:rsc:mgc_in_wire.d#1(37)} {vin:rsc:mgc_in_wire.d#1(38)} {vin:rsc:mgc_in_wire.d#1(39)} {vin:rsc:mgc_in_wire.d#1(40)} {vin:rsc:mgc_in_wire.d#1(41)} {vin:rsc:mgc_in_wire.d#1(42)} {vin:rsc:mgc_in_wire.d#1(43)} {vin:rsc:mgc_in_wire.d#1(44)} {vin:rsc:mgc_in_wire.d#1(45)} {vin:rsc:mgc_in_wire.d#1(46)} {vin:rsc:mgc_in_wire.d#1(47)} {vin:rsc:mgc_in_wire.d#1(48)} {vin:rsc:mgc_in_wire.d#1(49)} {vin:rsc:mgc_in_wire.d#1(50)} {vin:rsc:mgc_in_wire.d#1(51)} {vin:rsc:mgc_in_wire.d#1(52)} {vin:rsc:mgc_in_wire.d#1(53)} {vin:rsc:mgc_in_wire.d#1(54)} {vin:rsc:mgc_in_wire.d#1(55)} {vin:rsc:mgc_in_wire.d#1(56)} {vin:rsc:mgc_in_wire.d#1(57)} {vin:rsc:mgc_in_wire.d#1(58)} {vin:rsc:mgc_in_wire.d#1(59)} {vin:rsc:mgc_in_wire.d#1(60)} {vin:rsc:mgc_in_wire.d#1(61)} {vin:rsc:mgc_in_wire.d#1(62)} {vin:rsc:mgc_in_wire.d#1(63)} {vin:rsc:mgc_in_wire.d#1(64)} {vin:rsc:mgc_in_wire.d#1(65)} {vin:rsc:mgc_in_wire.d#1(66)} {vin:rsc:mgc_in_wire.d#1(67)} {vin:rsc:mgc_in_wire.d#1(68)} {vin:rsc:mgc_in_wire.d#1(69)} {vin:rsc:mgc_in_wire.d#1(70)} {vin:rsc:mgc_in_wire.d#1(71)} {vin:rsc:mgc_in_wire.d#1(72)} {vin:rsc:mgc_in_wire.d#1(73)} {vin:rsc:mgc_in_wire.d#1(74)} {vin:rsc:mgc_in_wire.d#1(75)} {vin:rsc:mgc_in_wire.d#1(76)} {vin:rsc:mgc_in_wire.d#1(77)} {vin:rsc:mgc_in_wire.d#1(78)} {vin:rsc:mgc_in_wire.d#1(79)} {vin:rsc:mgc_in_wire.d#1(80)} {vin:rsc:mgc_in_wire.d#1(81)} {vin:rsc:mgc_in_wire.d#1(82)} {vin:rsc:mgc_in_wire.d#1(83)} {vin:rsc:mgc_in_wire.d#1(84)} {vin:rsc:mgc_in_wire.d#1(85)} {vin:rsc:mgc_in_wire.d#1(86)} {vin:rsc:mgc_in_wire.d#1(87)} {vin:rsc:mgc_in_wire.d#1(88)} {vin:rsc:mgc_in_wire.d#1(89)} -attr xrf 53914 -attr oid 1970 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d#1} 30 {vout:rsc:mgc_out_stdreg.d#1(0)} {vout:rsc:mgc_out_stdreg.d#1(1)} {vout:rsc:mgc_out_stdreg.d#1(2)} {vout:rsc:mgc_out_stdreg.d#1(3)} {vout:rsc:mgc_out_stdreg.d#1(4)} {vout:rsc:mgc_out_stdreg.d#1(5)} {vout:rsc:mgc_out_stdreg.d#1(6)} {vout:rsc:mgc_out_stdreg.d#1(7)} {vout:rsc:mgc_out_stdreg.d#1(8)} {vout:rsc:mgc_out_stdreg.d#1(9)} {vout:rsc:mgc_out_stdreg.d#1(10)} {vout:rsc:mgc_out_stdreg.d#1(11)} {vout:rsc:mgc_out_stdreg.d#1(12)} {vout:rsc:mgc_out_stdreg.d#1(13)} {vout:rsc:mgc_out_stdreg.d#1(14)} {vout:rsc:mgc_out_stdreg.d#1(15)} {vout:rsc:mgc_out_stdreg.d#1(16)} {vout:rsc:mgc_out_stdreg.d#1(17)} {vout:rsc:mgc_out_stdreg.d#1(18)} {vout:rsc:mgc_out_stdreg.d#1(19)} {vout:rsc:mgc_out_stdreg.d#1(20)} {vout:rsc:mgc_out_stdreg.d#1(21)} {vout:rsc:mgc_out_stdreg.d#1(22)} {vout:rsc:mgc_out_stdreg.d#1(23)} {vout:rsc:mgc_out_stdreg.d#1(24)} {vout:rsc:mgc_out_stdreg.d#1(25)} {vout:rsc:mgc_out_stdreg.d#1(26)} {vout:rsc:mgc_out_stdreg.d#1(27)} {vout:rsc:mgc_out_stdreg.d#1(28)} {vout:rsc:mgc_out_stdreg.d#1(29)} -attr xrf 53915 -attr oid 1971 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -attr vt d
+load net {vin:rsc.z(13)} -attr vt d
+load net {vin:rsc.z(14)} -attr vt d
+load net {vin:rsc.z(15)} -attr vt d
+load net {vin:rsc.z(16)} -attr vt d
+load net {vin:rsc.z(17)} -attr vt d
+load net {vin:rsc.z(18)} -attr vt d
+load net {vin:rsc.z(19)} -attr vt d
+load net {vin:rsc.z(20)} -attr vt d
+load net {vin:rsc.z(21)} -attr vt d
+load net {vin:rsc.z(22)} -attr vt d
+load net {vin:rsc.z(23)} -attr vt d
+load net {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -attr vt d
+load net {vin:rsc.z(28)} -attr vt d
+load net {vin:rsc.z(29)} -attr vt d
+load net {vin:rsc.z(30)} -attr vt d
+load net {vin:rsc.z(31)} -attr vt d
+load net {vin:rsc.z(32)} -attr vt d
+load net {vin:rsc.z(33)} -attr vt d
+load net {vin:rsc.z(34)} -attr vt d
+load net {vin:rsc.z(35)} -attr vt d
+load net {vin:rsc.z(36)} -attr vt d
+load net {vin:rsc.z(37)} -attr vt d
+load net {vin:rsc.z(38)} -attr vt d
+load net {vin:rsc.z(39)} -attr vt d
+load net {vin:rsc.z(40)} -attr vt d
+load net {vin:rsc.z(41)} -attr vt d
+load net {vin:rsc.z(42)} -attr vt d
+load net {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -attr vt d
+load net {vin:rsc.z(45)} -attr vt d
+load net {vin:rsc.z(46)} -attr vt d
+load net {vin:rsc.z(47)} -attr vt d
+load net {vin:rsc.z(48)} -attr vt d
+load net {vin:rsc.z(49)} -attr vt d
+load net {vin:rsc.z(50)} -attr vt d
+load net {vin:rsc.z(51)} -attr vt d
+load net {vin:rsc.z(52)} -attr vt d
+load net {vin:rsc.z(53)} -attr vt d
+load net {vin:rsc.z(54)} -attr vt d
+load net {vin:rsc.z(55)} -attr vt d
+load net {vin:rsc.z(56)} -attr vt d
+load net {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -attr vt d
+load net {vin:rsc.z(63)} -attr vt d
+load net {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -attr vt d
+load net {vin:rsc.z(68)} -attr vt d
+load net {vin:rsc.z(69)} -attr vt d
+load net {vin:rsc.z(70)} -attr vt d
+load net {vin:rsc.z(71)} -attr vt d
+load net {vin:rsc.z(72)} -attr vt d
+load net {vin:rsc.z(73)} -attr vt d
+load net {vin:rsc.z(74)} -attr vt d
+load net {vin:rsc.z(75)} -attr vt d
+load net {vin:rsc.z(76)} -attr vt d
+load net {vin:rsc.z(77)} -attr vt d
+load net {vin:rsc.z(78)} -attr vt d
+load net {vin:rsc.z(79)} -attr vt d
+load net {vin:rsc.z(80)} -attr vt d
+load net {vin:rsc.z(81)} -attr vt d
+load net {vin:rsc.z(82)} -attr vt d
+load net {vin:rsc.z(83)} -attr vt d
+load net {vin:rsc.z(84)} -attr vt d
+load net {vin:rsc.z(85)} -attr vt d
+load net {vin:rsc.z(86)} -attr vt d
+load net {vin:rsc.z(87)} -attr vt d
+load net {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 53916 -attr oid 1972 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(0)} -port {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -port {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -port {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -port {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -port {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -port {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -port {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -port {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -port {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -port {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -port {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -port {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -port {vin:rsc.z(12)} -attr vt d
+load net {vin:rsc.z(13)} -port {vin:rsc.z(13)} -attr vt d
+load net {vin:rsc.z(14)} -port {vin:rsc.z(14)} -attr vt d
+load net {vin:rsc.z(15)} -port {vin:rsc.z(15)} -attr vt d
+load net {vin:rsc.z(16)} -port {vin:rsc.z(16)} -attr vt d
+load net {vin:rsc.z(17)} -port {vin:rsc.z(17)} -attr vt d
+load net {vin:rsc.z(18)} -port {vin:rsc.z(18)} -attr vt d
+load net {vin:rsc.z(19)} -port {vin:rsc.z(19)} -attr vt d
+load net {vin:rsc.z(20)} -port {vin:rsc.z(20)} -attr vt d
+load net {vin:rsc.z(21)} -port {vin:rsc.z(21)} -attr vt d
+load net {vin:rsc.z(22)} -port {vin:rsc.z(22)} -attr vt d
+load net {vin:rsc.z(23)} -port {vin:rsc.z(23)} -attr vt d
+load net {vin:rsc.z(24)} -port {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -port {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -port {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -port {vin:rsc.z(27)} -attr vt d
+load net {vin:rsc.z(28)} -port {vin:rsc.z(28)} -attr vt d
+load net {vin:rsc.z(29)} -port {vin:rsc.z(29)} -attr vt d
+load net {vin:rsc.z(30)} -port {vin:rsc.z(30)} -attr vt d
+load net {vin:rsc.z(31)} -port {vin:rsc.z(31)} -attr vt d
+load net {vin:rsc.z(32)} -port {vin:rsc.z(32)} -attr vt d
+load net {vin:rsc.z(33)} -port {vin:rsc.z(33)} -attr vt d
+load net {vin:rsc.z(34)} -port {vin:rsc.z(34)} -attr vt d
+load net {vin:rsc.z(35)} -port {vin:rsc.z(35)} -attr vt d
+load net {vin:rsc.z(36)} -port {vin:rsc.z(36)} -attr vt d
+load net {vin:rsc.z(37)} -port {vin:rsc.z(37)} -attr vt d
+load net {vin:rsc.z(38)} -port {vin:rsc.z(38)} -attr vt d
+load net {vin:rsc.z(39)} -port {vin:rsc.z(39)} -attr vt d
+load net {vin:rsc.z(40)} -port {vin:rsc.z(40)} -attr vt d
+load net {vin:rsc.z(41)} -port {vin:rsc.z(41)} -attr vt d
+load net {vin:rsc.z(42)} -port {vin:rsc.z(42)} -attr vt d
+load net {vin:rsc.z(43)} -port {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -port {vin:rsc.z(44)} -attr vt d
+load net {vin:rsc.z(45)} -port {vin:rsc.z(45)} -attr vt d
+load net {vin:rsc.z(46)} -port {vin:rsc.z(46)} -attr vt d
+load net {vin:rsc.z(47)} -port {vin:rsc.z(47)} -attr vt d
+load net {vin:rsc.z(48)} -port {vin:rsc.z(48)} -attr vt d
+load net {vin:rsc.z(49)} -port {vin:rsc.z(49)} -attr vt d
+load net {vin:rsc.z(50)} -port {vin:rsc.z(50)} -attr vt d
+load net {vin:rsc.z(51)} -port {vin:rsc.z(51)} -attr vt d
+load net {vin:rsc.z(52)} -port {vin:rsc.z(52)} -attr vt d
+load net {vin:rsc.z(53)} -port {vin:rsc.z(53)} -attr vt d
+load net {vin:rsc.z(54)} -port {vin:rsc.z(54)} -attr vt d
+load net {vin:rsc.z(55)} -port {vin:rsc.z(55)} -attr vt d
+load net {vin:rsc.z(56)} -port {vin:rsc.z(56)} -attr vt d
+load net {vin:rsc.z(57)} -port {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -port {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -port {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -port {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -port {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -port {vin:rsc.z(62)} -attr vt d
+load net {vin:rsc.z(63)} -port {vin:rsc.z(63)} -attr vt d
+load net {vin:rsc.z(64)} -port {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -port {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -port {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -port {vin:rsc.z(67)} -attr vt d
+load net {vin:rsc.z(68)} -port {vin:rsc.z(68)} -attr vt d
+load net {vin:rsc.z(69)} -port {vin:rsc.z(69)} -attr vt d
+load net {vin:rsc.z(70)} -port {vin:rsc.z(70)} -attr vt d
+load net {vin:rsc.z(71)} -port {vin:rsc.z(71)} -attr vt d
+load net {vin:rsc.z(72)} -port {vin:rsc.z(72)} -attr vt d
+load net {vin:rsc.z(73)} -port {vin:rsc.z(73)} -attr vt d
+load net {vin:rsc.z(74)} -port {vin:rsc.z(74)} -attr vt d
+load net {vin:rsc.z(75)} -port {vin:rsc.z(75)} -attr vt d
+load net {vin:rsc.z(76)} -port {vin:rsc.z(76)} -attr vt d
+load net {vin:rsc.z(77)} -port {vin:rsc.z(77)} -attr vt d
+load net {vin:rsc.z(78)} -port {vin:rsc.z(78)} -attr vt d
+load net {vin:rsc.z(79)} -port {vin:rsc.z(79)} -attr vt d
+load net {vin:rsc.z(80)} -port {vin:rsc.z(80)} -attr vt d
+load net {vin:rsc.z(81)} -port {vin:rsc.z(81)} -attr vt d
+load net {vin:rsc.z(82)} -port {vin:rsc.z(82)} -attr vt d
+load net {vin:rsc.z(83)} -port {vin:rsc.z(83)} -attr vt d
+load net {vin:rsc.z(84)} -port {vin:rsc.z(84)} -attr vt d
+load net {vin:rsc.z(85)} -port {vin:rsc.z(85)} -attr vt d
+load net {vin:rsc.z(86)} -port {vin:rsc.z(86)} -attr vt d
+load net {vin:rsc.z(87)} -port {vin:rsc.z(87)} -attr vt d
+load net {vin:rsc.z(88)} -port {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -port {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 53917 -attr oid 1973 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vout:rsc.z(0)} -attr vt d
+load net {vout:rsc.z(1)} -attr vt d
+load net {vout:rsc.z(2)} -attr vt d
+load net {vout:rsc.z(3)} -attr vt d
+load net {vout:rsc.z(4)} -attr vt d
+load net {vout:rsc.z(5)} -attr vt d
+load net {vout:rsc.z(6)} -attr vt d
+load net {vout:rsc.z(7)} -attr vt d
+load net {vout:rsc.z(8)} -attr vt d
+load net {vout:rsc.z(9)} -attr vt d
+load net {vout:rsc.z(10)} -attr vt d
+load net {vout:rsc.z(11)} -attr vt d
+load net {vout:rsc.z(12)} -attr vt d
+load net {vout:rsc.z(13)} -attr vt d
+load net {vout:rsc.z(14)} -attr vt d
+load net {vout:rsc.z(15)} -attr vt d
+load net {vout:rsc.z(16)} -attr vt d
+load net {vout:rsc.z(17)} -attr vt d
+load net {vout:rsc.z(18)} -attr vt d
+load net {vout:rsc.z(19)} -attr vt d
+load net {vout:rsc.z(20)} -attr vt d
+load net {vout:rsc.z(21)} -attr vt d
+load net {vout:rsc.z(22)} -attr vt d
+load net {vout:rsc.z(23)} -attr vt d
+load net {vout:rsc.z(24)} -attr vt d
+load net {vout:rsc.z(25)} -attr vt d
+load net {vout:rsc.z(26)} -attr vt d
+load net {vout:rsc.z(27)} -attr vt d
+load net {vout:rsc.z(28)} -attr vt d
+load net {vout:rsc.z(29)} -attr vt d
+load netBundle {vout:rsc.z} 30 {vout:rsc.z(0)} {vout:rsc.z(1)} {vout:rsc.z(2)} {vout:rsc.z(3)} {vout:rsc.z(4)} {vout:rsc.z(5)} {vout:rsc.z(6)} {vout:rsc.z(7)} {vout:rsc.z(8)} {vout:rsc.z(9)} {vout:rsc.z(10)} {vout:rsc.z(11)} {vout:rsc.z(12)} {vout:rsc.z(13)} {vout:rsc.z(14)} {vout:rsc.z(15)} {vout:rsc.z(16)} {vout:rsc.z(17)} {vout:rsc.z(18)} {vout:rsc.z(19)} {vout:rsc.z(20)} {vout:rsc.z(21)} {vout:rsc.z(22)} {vout:rsc.z(23)} {vout:rsc.z(24)} {vout:rsc.z(25)} {vout:rsc.z(26)} {vout:rsc.z(27)} {vout:rsc.z(28)} {vout:rsc.z(29)} -attr xrf 53918 -attr oid 1974 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(0)} -port {vout:rsc.z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -port {vout:rsc.z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -port {vout:rsc.z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -port {vout:rsc.z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -port {vout:rsc.z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -port {vout:rsc.z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -port {vout:rsc.z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -port {vout:rsc.z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -port {vout:rsc.z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -port {vout:rsc.z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -port {vout:rsc.z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -port {vout:rsc.z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -port {vout:rsc.z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -port {vout:rsc.z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -port {vout:rsc.z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -port {vout:rsc.z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -port {vout:rsc.z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -port {vout:rsc.z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -port {vout:rsc.z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -port {vout:rsc.z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -port {vout:rsc.z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -port {vout:rsc.z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -port {vout:rsc.z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -port {vout:rsc.z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -port {vout:rsc.z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -port {vout:rsc.z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -port {vout:rsc.z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -port {vout:rsc.z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -port {vout:rsc.z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -port {vout:rsc.z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {clk} -attr xrf 53919 -attr oid 1975
+load net {clk} -port {clk} -attr xrf 53920 -attr oid 1976
+load net {en} -attr xrf 53921 -attr oid 1977
+load net {en} -port {en} -attr xrf 53922 -attr oid 1978
+load net {arst_n} -attr xrf 53923 -attr oid 1979
+load net {arst_n} -port {arst_n} -attr xrf 53924 -attr oid 1980
+load inst "sobel:core:inst" "sobel:core" "orig" -attr xrf 53925 -attr oid 1981 -attr vt dc -attr @path {/sobel/sobel:core:inst} -attr area 5445.659661 -attr delay 15.672745 -attr hier "/sobel/sobel:core" -pg 1 -lvl 3
+load net {clk} -pin  "sobel:core:inst" {clk#1} -attr xrf 53926 -attr oid 1982 -attr @path {/sobel/clk}
+load net {en} -pin  "sobel:core:inst" {en#1} -attr xrf 53927 -attr oid 1983 -attr @path {/sobel/en}
+load net {arst_n} -pin  "sobel:core:inst" {arst_n#1} -attr xrf 53928 -attr oid 1984 -attr @path {/sobel/arst_n}
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(8)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(9)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(10)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(11)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(12)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(13)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(14)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(15)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(16)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(17)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(18)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(19)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(20)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(21)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(22)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(23)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(24)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(25)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(26)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(27)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(28)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(29)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(30)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(31)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(32)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(33)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(34)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(35)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(36)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(37)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(38)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(39)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(40)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(41)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(42)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(43)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(44)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(45)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(46)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(47)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(48)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(49)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(50)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(51)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(52)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(53)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(54)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(55)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(56)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(57)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(58)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(59)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(60)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(61)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(62)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(63)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(64)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(65)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(66)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(67)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(68)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(69)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(70)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(71)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(72)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(73)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(74)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(75)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(76)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(77)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(78)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(79)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(80)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(81)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(82)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(83)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(84)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(85)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(86)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(87)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(88)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(89)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(8)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(9)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(10)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(11)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(12)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(13)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(14)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(15)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(16)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(17)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(18)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(19)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(20)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(21)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(22)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(23)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(24)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(25)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(26)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(27)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(28)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(29)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load inst "vin:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" -attr xrf 53929 -attr oid 1985 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,90)" -pg 1 -lvl 1
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "vin:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "vin:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "vin:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "vin:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "vin:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "vin:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "vin:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "vin:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "vin:rsc:mgc_in_wire" {d(8)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "vin:rsc:mgc_in_wire" {d(9)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "vin:rsc:mgc_in_wire" {d(10)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "vin:rsc:mgc_in_wire" {d(11)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "vin:rsc:mgc_in_wire" {d(12)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "vin:rsc:mgc_in_wire" {d(13)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "vin:rsc:mgc_in_wire" {d(14)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "vin:rsc:mgc_in_wire" {d(15)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "vin:rsc:mgc_in_wire" {d(16)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "vin:rsc:mgc_in_wire" {d(17)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "vin:rsc:mgc_in_wire" {d(18)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "vin:rsc:mgc_in_wire" {d(19)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "vin:rsc:mgc_in_wire" {d(20)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "vin:rsc:mgc_in_wire" {d(21)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "vin:rsc:mgc_in_wire" {d(22)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "vin:rsc:mgc_in_wire" {d(23)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "vin:rsc:mgc_in_wire" {d(24)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "vin:rsc:mgc_in_wire" {d(25)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "vin:rsc:mgc_in_wire" {d(26)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "vin:rsc:mgc_in_wire" {d(27)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "vin:rsc:mgc_in_wire" {d(28)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "vin:rsc:mgc_in_wire" {d(29)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "vin:rsc:mgc_in_wire" {d(30)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "vin:rsc:mgc_in_wire" {d(31)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "vin:rsc:mgc_in_wire" {d(32)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "vin:rsc:mgc_in_wire" {d(33)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "vin:rsc:mgc_in_wire" {d(34)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "vin:rsc:mgc_in_wire" {d(35)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "vin:rsc:mgc_in_wire" {d(36)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "vin:rsc:mgc_in_wire" {d(37)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "vin:rsc:mgc_in_wire" {d(38)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "vin:rsc:mgc_in_wire" {d(39)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "vin:rsc:mgc_in_wire" {d(40)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "vin:rsc:mgc_in_wire" {d(41)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "vin:rsc:mgc_in_wire" {d(42)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "vin:rsc:mgc_in_wire" {d(43)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "vin:rsc:mgc_in_wire" {d(44)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "vin:rsc:mgc_in_wire" {d(45)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "vin:rsc:mgc_in_wire" {d(46)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "vin:rsc:mgc_in_wire" {d(47)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "vin:rsc:mgc_in_wire" {d(48)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "vin:rsc:mgc_in_wire" {d(49)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "vin:rsc:mgc_in_wire" {d(50)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "vin:rsc:mgc_in_wire" {d(51)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "vin:rsc:mgc_in_wire" {d(52)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "vin:rsc:mgc_in_wire" {d(53)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "vin:rsc:mgc_in_wire" {d(54)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "vin:rsc:mgc_in_wire" {d(55)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "vin:rsc:mgc_in_wire" {d(56)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "vin:rsc:mgc_in_wire" {d(57)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "vin:rsc:mgc_in_wire" {d(58)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "vin:rsc:mgc_in_wire" {d(59)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "vin:rsc:mgc_in_wire" {d(60)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "vin:rsc:mgc_in_wire" {d(61)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "vin:rsc:mgc_in_wire" {d(62)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "vin:rsc:mgc_in_wire" {d(63)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "vin:rsc:mgc_in_wire" {d(64)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "vin:rsc:mgc_in_wire" {d(65)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "vin:rsc:mgc_in_wire" {d(66)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "vin:rsc:mgc_in_wire" {d(67)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "vin:rsc:mgc_in_wire" {d(68)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "vin:rsc:mgc_in_wire" {d(69)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "vin:rsc:mgc_in_wire" {d(70)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "vin:rsc:mgc_in_wire" {d(71)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "vin:rsc:mgc_in_wire" {d(72)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "vin:rsc:mgc_in_wire" {d(73)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "vin:rsc:mgc_in_wire" {d(74)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "vin:rsc:mgc_in_wire" {d(75)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "vin:rsc:mgc_in_wire" {d(76)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "vin:rsc:mgc_in_wire" {d(77)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "vin:rsc:mgc_in_wire" {d(78)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "vin:rsc:mgc_in_wire" {d(79)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "vin:rsc:mgc_in_wire" {d(80)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "vin:rsc:mgc_in_wire" {d(81)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "vin:rsc:mgc_in_wire" {d(82)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "vin:rsc:mgc_in_wire" {d(83)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "vin:rsc:mgc_in_wire" {d(84)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "vin:rsc:mgc_in_wire" {d(85)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "vin:rsc:mgc_in_wire" {d(86)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "vin:rsc:mgc_in_wire" {d(87)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "vin:rsc:mgc_in_wire" {d(88)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "vin:rsc:mgc_in_wire" {d(89)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc.z(0)} -pin  "vin:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(1)} -pin  "vin:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(2)} -pin  "vin:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(3)} -pin  "vin:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(4)} -pin  "vin:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(5)} -pin  "vin:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(6)} -pin  "vin:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(7)} -pin  "vin:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(8)} -pin  "vin:rsc:mgc_in_wire" {z(8)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(9)} -pin  "vin:rsc:mgc_in_wire" {z(9)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(10)} -pin  "vin:rsc:mgc_in_wire" {z(10)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(11)} -pin  "vin:rsc:mgc_in_wire" {z(11)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(12)} -pin  "vin:rsc:mgc_in_wire" {z(12)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(13)} -pin  "vin:rsc:mgc_in_wire" {z(13)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(14)} -pin  "vin:rsc:mgc_in_wire" {z(14)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(15)} -pin  "vin:rsc:mgc_in_wire" {z(15)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(16)} -pin  "vin:rsc:mgc_in_wire" {z(16)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(17)} -pin  "vin:rsc:mgc_in_wire" {z(17)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(18)} -pin  "vin:rsc:mgc_in_wire" {z(18)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(19)} -pin  "vin:rsc:mgc_in_wire" {z(19)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(20)} -pin  "vin:rsc:mgc_in_wire" {z(20)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(21)} -pin  "vin:rsc:mgc_in_wire" {z(21)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(22)} -pin  "vin:rsc:mgc_in_wire" {z(22)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(23)} -pin  "vin:rsc:mgc_in_wire" {z(23)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(24)} -pin  "vin:rsc:mgc_in_wire" {z(24)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(25)} -pin  "vin:rsc:mgc_in_wire" {z(25)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(26)} -pin  "vin:rsc:mgc_in_wire" {z(26)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(27)} -pin  "vin:rsc:mgc_in_wire" {z(27)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(28)} -pin  "vin:rsc:mgc_in_wire" {z(28)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(29)} -pin  "vin:rsc:mgc_in_wire" {z(29)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(30)} -pin  "vin:rsc:mgc_in_wire" {z(30)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(31)} -pin  "vin:rsc:mgc_in_wire" {z(31)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(32)} -pin  "vin:rsc:mgc_in_wire" {z(32)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(33)} -pin  "vin:rsc:mgc_in_wire" {z(33)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(34)} -pin  "vin:rsc:mgc_in_wire" {z(34)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(35)} -pin  "vin:rsc:mgc_in_wire" {z(35)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(36)} -pin  "vin:rsc:mgc_in_wire" {z(36)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(37)} -pin  "vin:rsc:mgc_in_wire" {z(37)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(38)} -pin  "vin:rsc:mgc_in_wire" {z(38)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(39)} -pin  "vin:rsc:mgc_in_wire" {z(39)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(40)} -pin  "vin:rsc:mgc_in_wire" {z(40)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(41)} -pin  "vin:rsc:mgc_in_wire" {z(41)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(42)} -pin  "vin:rsc:mgc_in_wire" {z(42)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(43)} -pin  "vin:rsc:mgc_in_wire" {z(43)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(44)} -pin  "vin:rsc:mgc_in_wire" {z(44)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(45)} -pin  "vin:rsc:mgc_in_wire" {z(45)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(46)} -pin  "vin:rsc:mgc_in_wire" {z(46)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(47)} -pin  "vin:rsc:mgc_in_wire" {z(47)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(48)} -pin  "vin:rsc:mgc_in_wire" {z(48)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(49)} -pin  "vin:rsc:mgc_in_wire" {z(49)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(50)} -pin  "vin:rsc:mgc_in_wire" {z(50)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(51)} -pin  "vin:rsc:mgc_in_wire" {z(51)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(52)} -pin  "vin:rsc:mgc_in_wire" {z(52)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(53)} -pin  "vin:rsc:mgc_in_wire" {z(53)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(54)} -pin  "vin:rsc:mgc_in_wire" {z(54)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(55)} -pin  "vin:rsc:mgc_in_wire" {z(55)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(56)} -pin  "vin:rsc:mgc_in_wire" {z(56)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(57)} -pin  "vin:rsc:mgc_in_wire" {z(57)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(58)} -pin  "vin:rsc:mgc_in_wire" {z(58)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(59)} -pin  "vin:rsc:mgc_in_wire" {z(59)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(60)} -pin  "vin:rsc:mgc_in_wire" {z(60)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(61)} -pin  "vin:rsc:mgc_in_wire" {z(61)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(62)} -pin  "vin:rsc:mgc_in_wire" {z(62)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(63)} -pin  "vin:rsc:mgc_in_wire" {z(63)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(64)} -pin  "vin:rsc:mgc_in_wire" {z(64)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(65)} -pin  "vin:rsc:mgc_in_wire" {z(65)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(66)} -pin  "vin:rsc:mgc_in_wire" {z(66)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(67)} -pin  "vin:rsc:mgc_in_wire" {z(67)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(68)} -pin  "vin:rsc:mgc_in_wire" {z(68)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(69)} -pin  "vin:rsc:mgc_in_wire" {z(69)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(70)} -pin  "vin:rsc:mgc_in_wire" {z(70)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(71)} -pin  "vin:rsc:mgc_in_wire" {z(71)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(72)} -pin  "vin:rsc:mgc_in_wire" {z(72)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(73)} -pin  "vin:rsc:mgc_in_wire" {z(73)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(74)} -pin  "vin:rsc:mgc_in_wire" {z(74)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(75)} -pin  "vin:rsc:mgc_in_wire" {z(75)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(76)} -pin  "vin:rsc:mgc_in_wire" {z(76)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(77)} -pin  "vin:rsc:mgc_in_wire" {z(77)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(78)} -pin  "vin:rsc:mgc_in_wire" {z(78)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(79)} -pin  "vin:rsc:mgc_in_wire" {z(79)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(80)} -pin  "vin:rsc:mgc_in_wire" {z(80)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(81)} -pin  "vin:rsc:mgc_in_wire" {z(81)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(82)} -pin  "vin:rsc:mgc_in_wire" {z(82)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(83)} -pin  "vin:rsc:mgc_in_wire" {z(83)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(84)} -pin  "vin:rsc:mgc_in_wire" {z(84)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(85)} -pin  "vin:rsc:mgc_in_wire" {z(85)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(86)} -pin  "vin:rsc:mgc_in_wire" {z(86)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(87)} -pin  "vin:rsc:mgc_in_wire" {z(87)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(88)} -pin  "vin:rsc:mgc_in_wire" {z(88)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(89)} -pin  "vin:rsc:mgc_in_wire" {z(89)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load inst "vout:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" -attr xrf 53930 -attr oid 1986 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(2,30)" -pg 1 -lvl 1002
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "vout:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "vout:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "vout:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "vout:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "vout:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "vout:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "vout:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "vout:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "vout:rsc:mgc_out_stdreg" {d(8)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "vout:rsc:mgc_out_stdreg" {d(9)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "vout:rsc:mgc_out_stdreg" {d(10)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "vout:rsc:mgc_out_stdreg" {d(11)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "vout:rsc:mgc_out_stdreg" {d(12)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "vout:rsc:mgc_out_stdreg" {d(13)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "vout:rsc:mgc_out_stdreg" {d(14)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "vout:rsc:mgc_out_stdreg" {d(15)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "vout:rsc:mgc_out_stdreg" {d(16)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "vout:rsc:mgc_out_stdreg" {d(17)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "vout:rsc:mgc_out_stdreg" {d(18)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "vout:rsc:mgc_out_stdreg" {d(19)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "vout:rsc:mgc_out_stdreg" {d(20)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "vout:rsc:mgc_out_stdreg" {d(21)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "vout:rsc:mgc_out_stdreg" {d(22)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "vout:rsc:mgc_out_stdreg" {d(23)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "vout:rsc:mgc_out_stdreg" {d(24)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "vout:rsc:mgc_out_stdreg" {d(25)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "vout:rsc:mgc_out_stdreg" {d(26)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "vout:rsc:mgc_out_stdreg" {d(27)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "vout:rsc:mgc_out_stdreg" {d(28)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "vout:rsc:mgc_out_stdreg" {d(29)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc.z(0)} -pin  "vout:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -pin  "vout:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -pin  "vout:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -pin  "vout:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -pin  "vout:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -pin  "vout:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -pin  "vout:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -pin  "vout:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -pin  "vout:rsc:mgc_out_stdreg" {z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -pin  "vout:rsc:mgc_out_stdreg" {z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -pin  "vout:rsc:mgc_out_stdreg" {z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -pin  "vout:rsc:mgc_out_stdreg" {z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -pin  "vout:rsc:mgc_out_stdreg" {z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -pin  "vout:rsc:mgc_out_stdreg" {z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -pin  "vout:rsc:mgc_out_stdreg" {z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -pin  "vout:rsc:mgc_out_stdreg" {z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -pin  "vout:rsc:mgc_out_stdreg" {z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -pin  "vout:rsc:mgc_out_stdreg" {z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -pin  "vout:rsc:mgc_out_stdreg" {z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -pin  "vout:rsc:mgc_out_stdreg" {z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -pin  "vout:rsc:mgc_out_stdreg" {z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -pin  "vout:rsc:mgc_out_stdreg" {z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -pin  "vout:rsc:mgc_out_stdreg" {z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -pin  "vout:rsc:mgc_out_stdreg" {z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -pin  "vout:rsc:mgc_out_stdreg" {z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -pin  "vout:rsc:mgc_out_stdreg" {z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -pin  "vout:rsc:mgc_out_stdreg" {z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -pin  "vout:rsc:mgc_out_stdreg" {z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -pin  "vout:rsc:mgc_out_stdreg" {z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -pin  "vout:rsc:mgc_out_stdreg" {z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+### END MODULE 
+
diff --git a/Sobel/sobel.v12/concat_rtl.v b/Sobel/sobel.v12/concat_rtl.v
new file mode 100644
index 0000000..014da96
--- /dev/null
+++ b/Sobel/sobel.v12/concat_rtl.v
@@ -0,0 +1,2857 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 16:19:43 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] regs_regs_slc_regs_regs_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_1_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_4_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_5_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_3_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_10_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_11_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_9_itm;
+  reg [12:0] ACC1_acc_659_itm_1;
+  wire [14:0] nl_ACC1_acc_659_itm_1;
+  reg [12:0] ACC1_acc_658_itm_1;
+  wire [13:0] nl_ACC1_acc_658_itm_1;
+  reg [13:0] ACC1_acc_661_itm_1;
+  wire [14:0] nl_ACC1_acc_661_itm_1;
+  reg slc_acc_20_psp_1_93_itm_1;
+  reg ACC1_slc_ACC1_acc_228_psp_55_itm_1;
+  reg ACC1_3_slc_acc_10_psp_62_itm_1;
+  reg [10:0] ACC1_acc_652_itm_1;
+  wire [11:0] nl_ACC1_acc_652_itm_1;
+  reg [11:0] ACC1_acc_655_itm_1;
+  wire [12:0] nl_ACC1_acc_655_itm_1;
+  reg main_stage_0_2;
+  reg [4:0] ACC1_mul_57_itm_1_sg2;
+  reg [1:0] ACC1_mul_57_itm_2;
+  reg [89:0] reg_regs_regs_0_sva_cse;
+  wire [11:0] FRAME_acc_2_psp_sva;
+  wire [13:0] nl_FRAME_acc_2_psp_sva;
+  wire [5:0] acc_imod_24_sva;
+  wire [7:0] nl_acc_imod_24_sva;
+  wire [11:0] acc_20_psp_1_sva;
+  wire [12:0] nl_acc_20_psp_1_sva;
+  wire [11:0] ACC1_acc_228_psp_sva;
+  wire [12:0] nl_ACC1_acc_228_psp_sva;
+  wire [11:0] ACC1_1_acc_25_psp_sva;
+  wire [12:0] nl_ACC1_1_acc_25_psp_sva;
+  wire [2:0] ACC1_acc_509_cse;
+  wire [3:0] nl_ACC1_acc_509_cse;
+  wire [11:0] ACC1_acc_227_psp_sva;
+  wire [12:0] nl_ACC1_acc_227_psp_sva;
+  wire [2:0] ACC1_acc_506_cse;
+  wire [3:0] nl_ACC1_acc_506_cse;
+  wire [3:0] ACC1_acc_562_ncse;
+  wire [4:0] nl_ACC1_acc_562_ncse;
+  wire [2:0] ACC1_acc_502_cse;
+  wire [3:0] nl_ACC1_acc_502_cse;
+  wire [2:0] ACC1_acc_489_cse;
+  wire [3:0] nl_ACC1_acc_489_cse;
+  wire [11:0] ACC1_acc_226_psp_sva;
+  wire [12:0] nl_ACC1_acc_226_psp_sva;
+  wire [3:0] ACC1_acc_553_ncse;
+  wire [4:0] nl_ACC1_acc_553_ncse;
+  wire ACC1_1_and_3_cse_sva;
+  wire ACC1_1_nand_1_cse_sva;
+  wire [11:0] acc_psp_1_sva;
+  wire [12:0] nl_acc_psp_1_sva;
+  wire [3:0] ACC1_acc_210_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_210_psp_2_sva;
+  wire [11:0] acc_psp_2_sva;
+  wire [12:0] nl_acc_psp_2_sva;
+  wire [11:0] ACC1_acc_224_psp_1_sva;
+  wire [12:0] nl_ACC1_acc_224_psp_1_sva;
+  wire [3:0] ACC1_1_acc_208_psp_sva;
+  wire [4:0] nl_ACC1_1_acc_208_psp_sva;
+  wire [11:0] ACC1_acc_224_psp_sva;
+  wire [12:0] nl_ACC1_acc_224_psp_sva;
+  wire [2:0] ACC1_acc_516_cse;
+  wire [3:0] nl_ACC1_acc_516_cse;
+  wire [3:0] ACC1_3_acc_212_psp_sva;
+  wire [4:0] nl_ACC1_3_acc_212_psp_sva;
+  wire [2:0] ACC1_acc_221_psp_sva;
+  wire [3:0] nl_ACC1_acc_221_psp_sva;
+  wire [2:0] ACC1_acc_221_psp_2_sva;
+  wire [3:0] nl_ACC1_acc_221_psp_2_sva;
+  wire [2:0] ACC1_acc_219_psp_2_sva;
+  wire [3:0] nl_ACC1_acc_219_psp_2_sva;
+  wire [2:0] ACC1_acc_222_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_222_psp_1_sva;
+  wire [2:0] ACC1_acc_219_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_219_psp_1_sva;
+  wire [3:0] ACC1_acc_210_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_210_psp_1_sva;
+  wire [3:0] ACC1_acc_217_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_217_psp_1_sva;
+  wire [2:0] ACC1_acc_724_cse;
+  wire [3:0] nl_ACC1_acc_724_cse;
+  wire [13:0] ACC1_mul_57_itm;
+  wire [27:0] nl_ACC1_mul_57_itm;
+  wire [2:0] ACC1_acc_223_psp_sva;
+  wire [3:0] nl_ACC1_acc_223_psp_sva;
+  wire [2:0] ACC1_acc_220_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_220_psp_1_sva;
+  wire [2:0] ACC1_acc_220_psp_sva;
+  wire [3:0] nl_ACC1_acc_220_psp_sva;
+  wire [2:0] ACC1_acc_222_psp_sva;
+  wire [3:0] nl_ACC1_acc_222_psp_sva;
+  wire [2:0] ACC1_acc_673_cse;
+  wire [3:0] nl_ACC1_acc_673_cse;
+  wire [11:0] acc_20_psp_2_sva;
+  wire [12:0] nl_acc_20_psp_2_sva;
+  wire [3:0] ACC1_acc_217_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_217_psp_2_sva;
+  wire [2:0] ACC1_acc_223_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_223_psp_1_sva;
+  wire [2:0] ACC1_acc_699_cse;
+  wire [3:0] nl_ACC1_acc_699_cse;
+  wire [14:0] ACC1_acc_itm;
+  wire [16:0] nl_ACC1_acc_itm;
+  wire [3:0] ACC1_acc_338_itm;
+  wire [4:0] nl_ACC1_acc_338_itm;
+  wire [2:0] ACC1_acc_406_itm;
+  wire [3:0] nl_ACC1_acc_406_itm;
+  wire [2:0] ACC1_acc_368_itm;
+  wire [3:0] nl_ACC1_acc_368_itm;
+  wire [3:0] ACC1_acc_367_itm;
+  wire [4:0] nl_ACC1_acc_367_itm;
+  wire [2:0] ACC1_acc_349_itm;
+  wire [3:0] nl_ACC1_acc_349_itm;
+  wire [3:0] ACC1_acc_348_itm;
+  wire [4:0] nl_ACC1_acc_348_itm;
+  wire [4:0] ACC1_acc_412_itm;
+  wire [5:0] nl_ACC1_acc_412_itm;
+  wire [3:0] ACC1_acc_423_itm;
+  wire [4:0] nl_ACC1_acc_423_itm;
+  wire [4:0] ACC1_acc_375_itm;
+  wire [5:0] nl_ACC1_acc_375_itm;
+  wire [3:0] ACC1_acc_395_itm;
+  wire [4:0] nl_ACC1_acc_395_itm;
+  wire [4:0] ACC1_acc_384_itm;
+  wire [5:0] nl_ACC1_acc_384_itm;
+  wire [3:0] ACC1_acc_414_itm;
+  wire [4:0] nl_ACC1_acc_414_itm;
+  wire [3:0] ACC1_acc_377_itm;
+  wire [4:0] nl_ACC1_acc_377_itm;
+  wire [4:0] ACC1_acc_346_itm;
+  wire [5:0] nl_ACC1_acc_346_itm;
+  wire [3:0] ACC1_acc_386_itm;
+  wire [4:0] nl_ACC1_acc_386_itm;
+  wire [3:0] ACC1_acc_405_itm;
+  wire [4:0] nl_ACC1_acc_405_itm;
+  wire [2:0] ACC1_acc_387_itm;
+  wire [3:0] nl_ACC1_acc_387_itm;
+  wire [2:0] ACC1_acc_378_itm;
+  wire [3:0] nl_ACC1_acc_378_itm;
+  wire [2:0] ACC1_acc_415_itm;
+  wire [3:0] nl_ACC1_acc_415_itm;
+  wire [2:0] ACC1_acc_396_itm;
+  wire [3:0] nl_ACC1_acc_396_itm;
+  wire [2:0] ACC1_acc_424_itm;
+  wire [3:0] nl_ACC1_acc_424_itm;
+  wire [2:0] ACC1_acc_359_itm;
+  wire [3:0] nl_ACC1_acc_359_itm;
+  wire [3:0] ACC1_acc_358_itm;
+  wire [4:0] nl_ACC1_acc_358_itm;
+  wire [2:0] ACC1_acc_339_itm;
+  wire [3:0] nl_ACC1_acc_339_itm;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_2_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(ACC1_acc_itm[14:13])
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_itm[12:10])
+      * 9'b111001)) + conv_s2s_7_10(conv_u2s_6_7(ACC1_acc_itm[9:4]) + conv_s2s_5_7(({4'b1001
+      , (acc_imod_24_sva[5])}) + conv_u2s_4_5((conv_u2u_3_4({(~ (acc_imod_24_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_24_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_24_sva[5:3])) , (~ (acc_imod_24_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_24_sva[4:3]))
+      + conv_u2u_3_4(~ (ACC1_acc_itm[9:7]))))))) + conv_u2u_11_12(signext_11_9({(ACC1_acc_itm[14])
+      , 3'b0 , (signext_3_1(ACC1_acc_itm[14])) , 1'b0 , (ACC1_acc_itm[14])}));
+  assign FRAME_acc_2_psp_sva = nl_FRAME_acc_2_psp_sva[11:0];
+  assign nl_ACC1_acc_itm = (conv_s2s_14_15(conv_s2s_13_14(ACC1_acc_659_itm_1) + conv_s2s_13_14(ACC1_acc_658_itm_1))
+      + conv_s2s_14_15(ACC1_acc_661_itm_1)) + conv_s2s_14_15(({ACC1_mul_57_itm_1_sg2
+      , 7'b0 , ACC1_mul_57_itm_2}) + conv_s2s_13_14(conv_s2s_12_13(({slc_acc_20_psp_1_93_itm_1
+      , 2'b0 , slc_acc_20_psp_1_93_itm_1 , 1'b0 , slc_acc_20_psp_1_93_itm_1 , 1'b0
+      , slc_acc_20_psp_1_93_itm_1 , ACC1_slc_ACC1_acc_228_psp_55_itm_1 , 1'b0 , ({{1{ACC1_3_slc_acc_10_psp_62_itm_1}},
+      ACC1_3_slc_acc_10_psp_62_itm_1})}) + conv_u2s_11_12(ACC1_acc_652_itm_1)) +
+      conv_s2s_12_13(ACC1_acc_655_itm_1)));
+  assign ACC1_acc_itm = nl_ACC1_acc_itm[14:0];
+  assign nl_acc_imod_24_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~ (ACC1_acc_itm[14]))
+      , 1'b1 , (~ (ACC1_acc_itm[14]))}) + conv_u2u_2_4(ACC1_acc_itm[14:13]))) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_itm[3:1])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[6:4])))) + 6'b101011;
+  assign acc_imod_24_sva = nl_acc_imod_24_sva[5:0];
+  assign nl_acc_20_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_10_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_11_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_9_itm);
+  assign acc_20_psp_1_sva = nl_acc_20_psp_1_sva[11:0];
+  assign nl_ACC1_acc_228_psp_sva = conv_s2u_11_12(conv_s2s_10_11(~ (reg_regs_regs_0_sva_cse[9:0]))
+      + conv_s2s_10_11(~ (reg_regs_regs_0_sva_cse[19:10]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (reg_regs_regs_0_sva_cse[29:20])) + 11'b11);
+  assign ACC1_acc_228_psp_sva = nl_ACC1_acc_228_psp_sva[11:0];
+  assign nl_ACC1_1_acc_25_psp_sva = conv_s2s_11_12(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[79:70])
+      + conv_s2s_10_11(vin_rsc_mgc_in_wire_d[69:60])) + conv_s2s_10_12(vin_rsc_mgc_in_wire_d[89:80]);
+  assign ACC1_1_acc_25_psp_sva = nl_ACC1_1_acc_25_psp_sva[11:0];
+  assign nl_ACC1_acc_509_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]));
+  assign ACC1_acc_509_cse = nl_ACC1_acc_509_cse[2:0];
+  assign nl_ACC1_acc_227_psp_sva = conv_s2s_11_12(conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_itm)
+      + conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_1_itm)) + conv_s2s_11_12(conv_s2s_10_11(~
+      regs_regs_slc_regs_regs_2_2_itm) + 11'b11);
+  assign ACC1_acc_227_psp_sva = nl_ACC1_acc_227_psp_sva[11:0];
+  assign nl_ACC1_acc_506_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+  assign ACC1_acc_506_cse = nl_ACC1_acc_506_cse[2:0];
+  assign nl_ACC1_acc_562_ncse = conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(ACC1_acc_506_cse);
+  assign ACC1_acc_562_ncse = nl_ACC1_acc_562_ncse[3:0];
+  assign nl_ACC1_acc_502_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[5])) + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+  assign ACC1_acc_502_cse = nl_ACC1_acc_502_cse[2:0];
+  assign nl_ACC1_acc_489_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]));
+  assign ACC1_acc_489_cse = nl_ACC1_acc_489_cse[2:0];
+  assign nl_ACC1_acc_226_psp_sva = conv_s2u_11_12(conv_s2s_10_11(reg_regs_regs_0_sva_cse[79:70])
+      + conv_s2s_10_11(reg_regs_regs_0_sva_cse[69:60])) + conv_s2u_10_12(reg_regs_regs_0_sva_cse[89:80]);
+  assign ACC1_acc_226_psp_sva = nl_ACC1_acc_226_psp_sva[11:0];
+  assign nl_ACC1_acc_553_ncse = conv_u2u_3_4(ACC1_acc_489_cse) + conv_u2u_3_4(ACC1_acc_489_cse);
+  assign ACC1_acc_553_ncse = nl_ACC1_acc_553_ncse[3:0];
+  assign ACC1_1_and_3_cse_sva = (acc_psp_2_sva[11]) & (~ (ACC1_acc_339_itm[2])) &
+      (ACC1_acc_339_itm[1]);
+  assign ACC1_1_nand_1_cse_sva = ~((ACC1_acc_339_itm[2]) & (~ (acc_psp_2_sva[11])));
+  assign nl_acc_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_1_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_2_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_itm);
+  assign acc_psp_1_sva = nl_acc_psp_1_sva[11:0];
+  assign nl_ACC1_acc_338_itm = conv_s2s_3_4({(~ (ACC1_acc_220_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_220_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_338_itm = nl_ACC1_acc_338_itm[3:0];
+  assign nl_ACC1_acc_210_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_2_sva[1])) , (acc_psp_2_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_2_sva[0]) , (acc_psp_2_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[3])) , (~ (acc_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[5])) , (acc_psp_2_sva[6])})))) ,
+      (~ (acc_psp_2_sva[9]))}))));
+  assign ACC1_acc_210_psp_2_sva = nl_ACC1_acc_210_psp_2_sva[3:0];
+  assign nl_acc_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[29:20]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[19:10]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[9:0])) + 11'b11);
+  assign acc_psp_2_sva = nl_acc_psp_2_sva[11:0];
+  assign nl_ACC1_acc_224_psp_1_sva = conv_s2u_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[39:30]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[49:40]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[59:50])) + 11'b11);
+  assign ACC1_acc_224_psp_1_sva = nl_ACC1_acc_224_psp_1_sva[11:0];
+  assign nl_ACC1_acc_406_itm = ({1'b1 , (ACC1_acc_405_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_405_itm[2])) , (~ (ACC1_acc_405_itm[3]))});
+  assign ACC1_acc_406_itm = nl_ACC1_acc_406_itm[2:0];
+  assign nl_ACC1_acc_368_itm = ({1'b1 , (ACC1_acc_367_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_367_itm[2])) , (~ (ACC1_acc_367_itm[3]))});
+  assign ACC1_acc_368_itm = nl_ACC1_acc_368_itm[2:0];
+  assign nl_ACC1_acc_367_itm = conv_s2s_3_4({(~ (ACC1_acc_219_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_367_itm = nl_ACC1_acc_367_itm[3:0];
+  assign nl_ACC1_1_acc_208_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (ACC1_1_acc_25_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_1_acc_25_psp_sva[1]))
+      , (ACC1_1_acc_25_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (ACC1_1_acc_25_psp_sva[0])
+      , (ACC1_1_acc_25_psp_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[3])) , (~ (ACC1_1_acc_25_psp_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[5])) , (ACC1_1_acc_25_psp_sva[6])}))))
+      , (~ (ACC1_1_acc_25_psp_sva[9]))}))));
+  assign ACC1_1_acc_208_psp_sva = nl_ACC1_1_acc_208_psp_sva[3:0];
+  assign nl_ACC1_acc_349_itm = ({1'b1 , (ACC1_acc_348_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_348_itm[2])) , (~ (ACC1_acc_348_itm[3]))});
+  assign ACC1_acc_349_itm = nl_ACC1_acc_349_itm[2:0];
+  assign nl_ACC1_acc_348_itm = conv_s2s_3_4({(~ (ACC1_acc_222_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_222_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_348_itm = nl_ACC1_acc_348_itm[3:0];
+  assign nl_ACC1_acc_224_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_4_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_5_itm)) + conv_s2u_10_12(regs_regs_slc_regs_regs_2_3_itm);
+  assign ACC1_acc_224_psp_sva = nl_ACC1_acc_224_psp_sva[11:0];
+  assign nl_ACC1_acc_516_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]));
+  assign ACC1_acc_516_cse = nl_ACC1_acc_516_cse[2:0];
+  assign nl_ACC1_acc_412_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_224_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[2])) , (~ (ACC1_acc_224_psp_sva[6]))}))))
+      , (~ (ACC1_acc_224_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[4])) , (ACC1_acc_224_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_sva[11:10])) , (ACC1_acc_224_psp_sva[7])}))))
+      , (ACC1_acc_224_psp_sva[9])});
+  assign ACC1_acc_412_itm = nl_ACC1_acc_412_itm[4:0];
+  assign nl_ACC1_acc_423_itm = conv_s2s_3_4({(~ (ACC1_acc_223_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_223_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_423_itm = nl_ACC1_acc_423_itm[3:0];
+  assign nl_ACC1_acc_375_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_228_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[2])) , (~ (ACC1_acc_228_psp_sva[6]))}))))
+      , (~ (ACC1_acc_228_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[4])) , (ACC1_acc_228_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_228_psp_sva[11:10])) , (ACC1_acc_228_psp_sva[7])}))))
+      , (ACC1_acc_228_psp_sva[9])});
+  assign ACC1_acc_375_itm = nl_ACC1_acc_375_itm[4:0];
+  assign nl_ACC1_acc_395_itm = conv_s2s_3_4({(~ (ACC1_acc_220_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_220_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_395_itm = nl_ACC1_acc_395_itm[3:0];
+  assign nl_ACC1_acc_384_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_226_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[2])) , (~ (ACC1_acc_226_psp_sva[6]))}))))
+      , (~ (ACC1_acc_226_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[4])) , (ACC1_acc_226_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_226_psp_sva[11:10])) , (ACC1_acc_226_psp_sva[7])}))))
+      , (ACC1_acc_226_psp_sva[9])});
+  assign ACC1_acc_384_itm = nl_ACC1_acc_384_itm[4:0];
+  assign nl_ACC1_3_acc_212_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (ACC1_acc_227_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_acc_227_psp_sva[1]))
+      , (ACC1_acc_227_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (ACC1_acc_227_psp_sva[0])
+      , (ACC1_acc_227_psp_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[3])) , (~ (ACC1_acc_227_psp_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[5])) , (ACC1_acc_227_psp_sva[6])}))))
+      , (~ (ACC1_acc_227_psp_sva[9]))}))));
+  assign ACC1_3_acc_212_psp_sva = nl_ACC1_3_acc_212_psp_sva[3:0];
+  assign nl_ACC1_acc_414_itm = conv_s2s_3_4({(~ (ACC1_acc_222_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_222_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_414_itm = nl_ACC1_acc_414_itm[3:0];
+  assign nl_ACC1_acc_377_itm = conv_s2s_3_4({(~ (ACC1_acc_221_psp_2_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_221_psp_2_sva[0]) , 1'b1});
+  assign ACC1_acc_377_itm = nl_ACC1_acc_377_itm[3:0];
+  assign nl_ACC1_acc_346_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_224_psp_1_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[2])) , (~ (ACC1_acc_224_psp_1_sva[6]))}))))
+      , (~ (ACC1_acc_224_psp_1_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[4])) , (ACC1_acc_224_psp_1_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_1_sva[11:10])) , (ACC1_acc_224_psp_1_sva[7])}))))
+      , (ACC1_acc_224_psp_1_sva[9])});
+  assign ACC1_acc_346_itm = nl_ACC1_acc_346_itm[4:0];
+  assign nl_ACC1_acc_386_itm = conv_s2s_3_4({(~ (ACC1_acc_219_psp_2_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_2_sva[0]) , 1'b1});
+  assign ACC1_acc_386_itm = nl_ACC1_acc_386_itm[3:0];
+  assign nl_ACC1_acc_405_itm = conv_s2s_3_4({(~ (ACC1_acc_221_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_221_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_405_itm = nl_ACC1_acc_405_itm[3:0];
+  assign nl_ACC1_acc_221_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_3_acc_212_psp_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_3_acc_212_psp_sva[1])) , (ACC1_3_acc_212_psp_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_3_acc_212_psp_sva[3]));
+  assign ACC1_acc_221_psp_sva = nl_ACC1_acc_221_psp_sva[2:0];
+  assign nl_ACC1_acc_221_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_375_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_375_itm[2])) , (ACC1_acc_375_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_375_itm[4]));
+  assign ACC1_acc_221_psp_2_sva = nl_ACC1_acc_221_psp_2_sva[2:0];
+  assign nl_ACC1_acc_219_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_384_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_384_itm[2])) , (ACC1_acc_384_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_384_itm[4]));
+  assign ACC1_acc_219_psp_2_sva = nl_ACC1_acc_219_psp_2_sva[2:0];
+  assign nl_ACC1_acc_222_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_346_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_346_itm[2])) , (ACC1_acc_346_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_346_itm[4]));
+  assign ACC1_acc_222_psp_1_sva = nl_ACC1_acc_222_psp_1_sva[2:0];
+  assign nl_ACC1_acc_219_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_208_psp_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_208_psp_sva[1])) , (ACC1_1_acc_208_psp_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_1_acc_208_psp_sva[3]));
+  assign ACC1_acc_219_psp_1_sva = nl_ACC1_acc_219_psp_1_sva[2:0];
+  assign nl_ACC1_acc_387_itm = ({1'b1 , (ACC1_acc_386_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_386_itm[2])) , (~ (ACC1_acc_386_itm[3]))});
+  assign ACC1_acc_387_itm = nl_ACC1_acc_387_itm[2:0];
+  assign nl_ACC1_acc_378_itm = ({1'b1 , (ACC1_acc_377_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_377_itm[2])) , (~ (ACC1_acc_377_itm[3]))});
+  assign ACC1_acc_378_itm = nl_ACC1_acc_378_itm[2:0];
+  assign nl_ACC1_acc_415_itm = ({1'b1 , (ACC1_acc_414_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_414_itm[2])) , (~ (ACC1_acc_414_itm[3]))});
+  assign ACC1_acc_415_itm = nl_ACC1_acc_415_itm[2:0];
+  assign nl_ACC1_acc_396_itm = ({1'b1 , (ACC1_acc_395_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_395_itm[2])) , (~ (ACC1_acc_395_itm[3]))});
+  assign ACC1_acc_396_itm = nl_ACC1_acc_396_itm[2:0];
+  assign nl_ACC1_acc_210_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_1_sva[1])) , (acc_psp_1_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_1_sva[0]) , (acc_psp_1_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[3])) , (~ (acc_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[5])) , (acc_psp_1_sva[6])})))) ,
+      (~ (acc_psp_1_sva[9]))}))));
+  assign ACC1_acc_210_psp_1_sva = nl_ACC1_acc_210_psp_1_sva[3:0];
+  assign nl_ACC1_acc_217_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_20_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_1_sva[1]))
+      , (acc_20_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_1_sva[0])
+      , (acc_20_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[3])) , (~ (acc_20_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[5])) , (acc_20_psp_1_sva[6])}))))
+      , (~ (acc_20_psp_1_sva[9]))}))));
+  assign ACC1_acc_217_psp_1_sva = nl_ACC1_acc_217_psp_1_sva[3:0];
+  assign nl_ACC1_acc_424_itm = ({1'b1 , (ACC1_acc_423_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_423_itm[2])) , (~ (ACC1_acc_423_itm[3]))});
+  assign ACC1_acc_424_itm = nl_ACC1_acc_424_itm[2:0];
+  assign nl_ACC1_acc_724_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]));
+  assign ACC1_acc_724_cse = nl_ACC1_acc_724_cse[2:0];
+  assign nl_ACC1_mul_57_itm = conv_u2s_2_14((conv_u2u_1_2(ACC1_acc_224_psp_sva[11])
+      + conv_u2u_1_2(ACC1_acc_228_psp_sva[11])) + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[11]))
+      * 14'b11101000000001;
+  assign ACC1_mul_57_itm = nl_ACC1_mul_57_itm[13:0];
+  assign nl_ACC1_acc_223_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_1_sva[1])) , (ACC1_acc_217_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_217_psp_1_sva[3]));
+  assign ACC1_acc_223_psp_sva = nl_ACC1_acc_223_psp_sva[2:0];
+  assign nl_ACC1_acc_220_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_2_sva[1])) , (ACC1_acc_210_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_210_psp_2_sva[3]));
+  assign ACC1_acc_220_psp_1_sva = nl_ACC1_acc_220_psp_1_sva[2:0];
+  assign nl_ACC1_acc_220_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_1_sva[1])) , (ACC1_acc_210_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_210_psp_1_sva[3]));
+  assign ACC1_acc_220_psp_sva = nl_ACC1_acc_220_psp_sva[2:0];
+  assign nl_ACC1_acc_222_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_412_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_412_itm[2])) , (ACC1_acc_412_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_412_itm[4]));
+  assign ACC1_acc_222_psp_sva = nl_ACC1_acc_222_psp_sva[2:0];
+  assign nl_ACC1_acc_673_cse = conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11]));
+  assign ACC1_acc_673_cse = nl_ACC1_acc_673_cse[2:0];
+  assign nl_acc_20_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[89:80]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[79:70]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[69:60])) + 11'b11);
+  assign acc_20_psp_2_sva = nl_acc_20_psp_2_sva[11:0];
+  assign nl_ACC1_acc_359_itm = ({1'b1 , (ACC1_acc_358_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_358_itm[2])) , (~ (ACC1_acc_358_itm[3]))});
+  assign ACC1_acc_359_itm = nl_ACC1_acc_359_itm[2:0];
+  assign nl_ACC1_acc_358_itm = conv_s2s_3_4({(~ (ACC1_acc_223_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_223_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_358_itm = nl_ACC1_acc_358_itm[3:0];
+  assign nl_ACC1_acc_217_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_20_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_2_sva[1]))
+      , (acc_20_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_2_sva[0])
+      , (acc_20_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[3])) , (~ (acc_20_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[5])) , (acc_20_psp_2_sva[6])}))))
+      , (~ (acc_20_psp_2_sva[9]))}))));
+  assign ACC1_acc_217_psp_2_sva = nl_ACC1_acc_217_psp_2_sva[3:0];
+  assign nl_ACC1_acc_223_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_2_sva[1])) , (ACC1_acc_217_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_217_psp_2_sva[3]));
+  assign ACC1_acc_223_psp_1_sva = nl_ACC1_acc_223_psp_1_sva[2:0];
+  assign nl_ACC1_acc_699_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11]));
+  assign ACC1_acc_699_cse = nl_ACC1_acc_699_cse[2:0];
+  assign nl_ACC1_acc_339_itm = ({1'b1 , (ACC1_acc_338_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_338_itm[2])) , (~ (ACC1_acc_338_itm[3]))});
+  assign ACC1_acc_339_itm = nl_ACC1_acc_339_itm[2:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      ACC1_acc_659_itm_1 <= 13'b0;
+      ACC1_acc_658_itm_1 <= 13'b0;
+      ACC1_acc_661_itm_1 <= 14'b0;
+      ACC1_mul_57_itm_1_sg2 <= 5'b0;
+      ACC1_mul_57_itm_2 <= 2'b0;
+      slc_acc_20_psp_1_93_itm_1 <= 1'b0;
+      ACC1_slc_ACC1_acc_228_psp_55_itm_1 <= 1'b0;
+      ACC1_3_slc_acc_10_psp_62_itm_1 <= 1'b0;
+      ACC1_acc_652_itm_1 <= 11'b0;
+      ACC1_acc_655_itm_1 <= 12'b0;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_slc_regs_regs_2_10_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_11_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_9_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_4_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_5_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_3_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_1_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_2_itm <= 10'b0;
+      reg_regs_regs_0_sva_cse <= 90'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({vout_rsc_mgc_out_stdreg_d , ({((FRAME_acc_2_psp_sva[9:0])
+            | ({8'b0 , (FRAME_acc_2_psp_sva[11:10])})) , (FRAME_acc_2_psp_sva[9:6])
+            , ((FRAME_acc_2_psp_sva[5:0]) | ({4'b0 , (FRAME_acc_2_psp_sva[11:10])}))
+            , (FRAME_acc_2_psp_sva[9:0])})}, main_stage_0_2);
+        ACC1_acc_659_itm_1 <= nl_ACC1_acc_659_itm_1[12:0];
+        ACC1_acc_658_itm_1 <= nl_ACC1_acc_658_itm_1[12:0];
+        ACC1_acc_661_itm_1 <= nl_ACC1_acc_661_itm_1[13:0];
+        ACC1_mul_57_itm_1_sg2 <= ACC1_mul_57_itm[13:9];
+        ACC1_mul_57_itm_2 <= ACC1_mul_57_itm[1:0];
+        slc_acc_20_psp_1_93_itm_1 <= acc_20_psp_1_sva[11];
+        ACC1_slc_ACC1_acc_228_psp_55_itm_1 <= ACC1_acc_228_psp_sva[6];
+        ACC1_3_slc_acc_10_psp_62_itm_1 <= ACC1_acc_224_psp_sva[8];
+        ACC1_acc_652_itm_1 <= nl_ACC1_acc_652_itm_1[10:0];
+        ACC1_acc_655_itm_1 <= nl_ACC1_acc_655_itm_1[11:0];
+        main_stage_0_2 <= 1'b1;
+        regs_regs_slc_regs_regs_2_10_itm <= reg_regs_regs_0_sva_cse[79:70];
+        regs_regs_slc_regs_regs_2_11_itm <= reg_regs_regs_0_sva_cse[69:60];
+        regs_regs_slc_regs_regs_2_9_itm <= reg_regs_regs_0_sva_cse[89:80];
+        regs_regs_slc_regs_regs_2_4_itm <= reg_regs_regs_0_sva_cse[49:40];
+        regs_regs_slc_regs_regs_2_5_itm <= reg_regs_regs_0_sva_cse[39:30];
+        regs_regs_slc_regs_regs_2_3_itm <= reg_regs_regs_0_sva_cse[59:50];
+        regs_regs_slc_regs_regs_2_itm <= reg_regs_regs_0_sva_cse[29:20];
+        regs_regs_slc_regs_regs_2_1_itm <= reg_regs_regs_0_sva_cse[19:10];
+        regs_regs_slc_regs_regs_2_2_itm <= reg_regs_regs_0_sva_cse[9:0];
+        reg_regs_regs_0_sva_cse <= vin_rsc_mgc_in_wire_d;
+      end
+    end
+  end
+  assign nl_ACC1_acc_659_itm_1  = conv_s2s_12_13(conv_s2s_11_12({(ACC1_1_acc_25_psp_sva[11])
+      , 2'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11]) ,
+      1'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_224_psp_sva[0])})
+      + conv_u2s_11_12({conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[9])
+      + conv_u2u_1_2(acc_psp_1_sva[9])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[8]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[8])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[8]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[8])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[9]))
+      + conv_u2u_1_4(acc_psp_2_sva[9])) * 8'b10101) , (ACC1_acc_227_psp_sva[4]) ,
+      (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_s2s_12_13(conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_psp_2_sva[9]) , 1'b0
+      , (acc_psp_2_sva[9]) , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_2_sva[7]) , 1'b0 , (acc_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~ (ACC1_acc_338_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_338_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_210_psp_2_sva[3]) ,
+      (acc_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_220_psp_1_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_2_sva[3])
+      , (acc_psp_2_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_210_psp_2_sva[3]) ,
+      (acc_psp_2_sva[2]) , (ACC1_acc_210_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_2_sva[7])
+      , (acc_psp_2_sva[4]) , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_673_cse)))
+      + conv_u2s_7_8({(acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])
+      , 1'b0 , (acc_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_2_sva[6])
+      , 1'b0 , (acc_psp_2_sva[6]) , 1'b0 , (acc_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_673_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , ACC1_1_and_3_cse_sva}))))))))))
+      + ({(acc_psp_2_sva[11]) , 2'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11])
+      , 1'b0 , (acc_psp_2_sva[11]) , (conv_u2u_1_3(acc_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])))}))
+      + conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_20_psp_2_sva[10]) , 1'b0
+      , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10])
+      , 1'b0 , (acc_20_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_20_psp_2_sva[9]) ,
+      1'b0 , (acc_20_psp_2_sva[9]) , 1'b0 , (acc_20_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_20_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_20_psp_2_sva[7]) , 1'b0 , (acc_20_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_20_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~((ACC1_acc_359_itm[2])
+      & (~ (acc_20_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~ (ACC1_acc_358_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (ACC1_acc_358_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (ACC1_acc_217_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_20_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_217_psp_2_sva[3])
+      , (acc_20_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_223_psp_1_sva[2:1])) +
+      (readslicef_5_4_1((conv_u2s_3_5({(acc_20_psp_2_sva[3]) , (acc_20_psp_2_sva[1])
+      , 1'b1}) + conv_s2s_3_5({(ACC1_acc_217_psp_2_sva[3]) , (acc_20_psp_2_sva[2])
+      , (ACC1_acc_217_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_20_psp_2_sva[7])
+      , (acc_20_psp_2_sva[4]) , (signext_2_1(acc_20_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_699_cse)))
+      + conv_u2s_7_8({(acc_20_psp_2_sva[8]) , 1'b0 , (acc_20_psp_2_sva[8]) , 1'b0
+      , (acc_20_psp_2_sva[8]) , 1'b0 , (acc_20_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_20_psp_2_sva[11])
+      , (signext_2_1(acc_20_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_20_psp_2_sva[6])
+      , 1'b0 , (acc_20_psp_2_sva[6]) , 1'b0 , (acc_20_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_699_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[9]) , ((acc_20_psp_2_sva[11])
+      & (~ (ACC1_acc_359_itm[2])) & (ACC1_acc_359_itm[1]))})))))))))) + ({(acc_20_psp_2_sva[11])
+      , 2'b0 , (acc_20_psp_2_sva[11]) , 1'b0 , (acc_20_psp_2_sva[11]) , 1'b0 , (acc_20_psp_2_sva[11])
+      , (conv_u2u_1_3(acc_20_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])))})));
+  assign nl_ACC1_acc_658_itm_1  = conv_s2s_12_13(conv_s2s_10_12(conv_s2s_9_10(conv_u2s_7_9(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(ACC1_acc_224_psp_1_sva[6])
+      , (ACC1_acc_228_psp_sva[3]) , (signext_2_1(ACC1_acc_224_psp_sva[11]))}) + conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[5])
+      , (ACC1_acc_226_psp_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})) +
+      conv_u2u_5_6(conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[7]) , (ACC1_acc_224_psp_1_sva[3])
+      , (signext_2_1(ACC1_acc_228_psp_sva[11]))}) + conv_u2u_4_5({(acc_20_psp_1_sva[4])
+      , (ACC1_1_acc_25_psp_sva[4]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(~ (ACC1_acc_217_psp_1_sva[3])) ,
+      (~ (ACC1_acc_210_psp_1_sva[3])) , 1'b1 , (~ (ACC1_acc_367_itm[3]))}) + conv_u2u_4_5({(acc_psp_2_sva[5])
+      , (acc_20_psp_1_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})) + conv_s2u_5_6(conv_u2s_3_5(readslicef_4_3_1((conv_u2u_3_4({((acc_20_psp_1_sva[11])
+      & (~ (ACC1_acc_424_itm[2])) & (ACC1_acc_424_itm[1])) , (ACC1_acc_224_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_3_4({(acc_psp_2_sva[3]) , (ACC1_acc_224_psp_1_sva[2]) ,
+      (ACC1_1_acc_25_psp_sva[2])})))) + conv_s2s_3_5({(ACC1_acc_223_psp_sva[2:1])
+      , (ACC1_acc_224_psp_1_sva[3])})))) + conv_s2s_7_9(conv_s2s_6_7(conv_s2s_4_6(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_s2s_3_5({(ACC1_acc_220_psp_1_sva[2:1]) , (ACC1_acc_377_itm[2])}))))
+      + conv_u2s_4_6({(ACC1_acc_224_psp_1_sva[4]) , (ACC1_acc_224_psp_sva[3]) , (signext_2_1(ACC1_acc_224_psp_sva[11]))}))
+      + conv_s2s_6_7(conv_u2s_4_6({(acc_psp_2_sva[7]) , (acc_psp_2_sva[4]) , (signext_2_1(ACC1_acc_228_psp_sva[6]))})
+      + conv_s2s_3_6(conv_s2s_2_3(ACC1_acc_220_psp_sva[2:1]) + conv_s2s_2_3(ACC1_acc_222_psp_sva[2:1])))))
+      + conv_u2s_9_10({(acc_20_psp_1_sva[9]) , 1'b0 , (acc_20_psp_1_sva[9]) , 1'b0
+      , (acc_20_psp_1_sva[9]) , (ACC1_acc_228_psp_sva[4]) , 1'b0 , (signext_2_1(ACC1_acc_224_psp_sva[6]))}))
+      + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_4_10(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[8])
+      + conv_u2u_1_2(acc_psp_1_sva[8])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[7]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[7])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[7]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[7])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[8]))
+      + conv_u2u_1_4(acc_psp_2_sva[8])) * 10'b1010101))) + conv_u2s_12_14(conv_u2s_24_13(conv_u2u_4_12(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[10])
+      + conv_u2u_1_2(acc_psp_1_sva[10])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[9]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[9])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[9]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[9])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[10]))
+      + conv_u2u_1_4(acc_psp_2_sva[10])) * 12'b101010101));
+  assign nl_ACC1_acc_661_itm_1  = conv_s2s_13_14(conv_s2s_12_13({(ACC1_acc_226_psp_sva[11])
+      , 1'b0 , (ACC1_acc_226_psp_sva[11]) , 7'b0 , (ACC1_acc_226_psp_sva[11]) , (acc_psp_1_sva[2])})
+      + conv_u2s_12_13({conv_u2u_18_9(conv_u2u_3_9(conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_224_psp_sva[10])
+      + conv_u2u_1_2(ACC1_acc_228_psp_sva[10])) + conv_u2u_1_2(ACC1_acc_226_psp_sva[10]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[10])) * 9'b1010101) , (acc_psp_1_sva[4])
+      , (signext_2_1(ACC1_acc_224_psp_sva[4]))})) + conv_s2s_13_14(conv_s2s_26_13(conv_u2s_2_13((conv_u2u_1_2(ACC1_acc_227_psp_sva[11])
+      + conv_u2u_1_2(acc_psp_1_sva[11])) + conv_u2u_1_2(acc_psp_2_sva[11])) * 13'b1110010101001));
+  assign nl_ACC1_acc_652_itm_1  = conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[4])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[3])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_405_itm[2])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_3_acc_212_psp_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[5]) , (ACC1_3_acc_212_psp_sva[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_3_acc_212_psp_sva[1])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[9]) , ((ACC1_acc_226_psp_sva[11])
+      & (~ (ACC1_acc_387_itm[2])) & (ACC1_acc_387_itm[1]))})))))))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (~((ACC1_acc_387_itm[2])
+      & (~ (ACC1_acc_226_psp_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11]) , (ACC1_acc_386_itm[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11]) , (ACC1_acc_384_itm[4])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[5])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_384_itm[3])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (ACC1_acc_384_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , ((ACC1_acc_228_psp_sva[11])
+      & (~ (ACC1_acc_378_itm[2])) & (ACC1_acc_378_itm[1]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (~((ACC1_acc_378_itm[2])
+      & (~ (ACC1_acc_228_psp_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_375_itm[4])})))))))))
+      + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_375_itm[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , (ACC1_acc_375_itm[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ((ACC1_acc_224_psp_sva[11])
+      & (~ (ACC1_acc_415_itm[2])) & (ACC1_acc_415_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~((ACC1_acc_415_itm[2])
+      & (~ (ACC1_acc_224_psp_sva[11]))))}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_414_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_412_itm[4])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[5]) , (ACC1_acc_412_itm[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_412_itm[2])}))))))))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_227_psp_sva[3])
+      , (ACC1_acc_227_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(acc_psp_1_sva[3]) , (ACC1_acc_227_psp_sva[2])
+      , ((acc_psp_1_sva[11]) & (~ (ACC1_acc_396_itm[2])) & (ACC1_acc_396_itm[1]))}))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_224_psp_sva[2]) ,
+      (ACC1_acc_227_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[2])
+      , (ACC1_acc_227_psp_sva[4]) , (~((ACC1_acc_396_itm[2]) & (~ (acc_psp_1_sva[11]))))})))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_226_psp_sva[2])
+      , (acc_psp_1_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_224_psp_1_sva[2]) ,
+      (acc_psp_1_sva[3]) , (ACC1_acc_395_itm[2])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_1_acc_25_psp_sva[3])
+      , (acc_psp_1_sva[4]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[1]) , (ACC1_acc_224_psp_sva[1])
+      , (ACC1_acc_210_psp_1_sva[3])})))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[2])
+      , (ACC1_acc_224_psp_sva[2]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[3])
+      , (ACC1_acc_224_psp_sva[3]) , (ACC1_acc_210_psp_1_sva[2])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[4])
+      , (ACC1_acc_228_psp_sva[0]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[1])
+      , (ACC1_acc_226_psp_sva[0]) , (ACC1_acc_210_psp_1_sva[1])}))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[2])
+      , (ACC1_acc_226_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[3])
+      , (ACC1_acc_226_psp_sva[2]) , (ACC1_1_acc_25_psp_sva[4])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_423_itm[2])
+      , (ACC1_acc_226_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(~((ACC1_acc_424_itm[2])
+      & (~ (acc_20_psp_1_sva[11])))) , (ACC1_acc_224_psp_1_sva[0]) , (ACC1_1_acc_25_psp_sva[3])})))))))))
+      + conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_3_4({(acc_20_psp_1_sva[6]) , 1'b0 ,
+      (acc_20_psp_1_sva[6])}) + conv_u2u_3_4({(acc_psp_1_sva[7]) , (acc_20_psp_1_sva[5])
+      , (ACC1_acc_226_psp_sva[4])})) , (conv_u2u_2_3({(acc_20_psp_1_sva[6]) , (ACC1_acc_228_psp_sva[1])})
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[10])))}) + conv_u2u_7_8({(conv_u2u_3_4({(ACC1_acc_224_psp_sva[6])
+      , (acc_20_psp_1_sva[7]) , (ACC1_acc_226_psp_sva[6])}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[6])
+      , 1'b0 , (ACC1_acc_227_psp_sva[5])})) , ACC1_acc_724_cse}))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_1_2(ACC1_acc_226_psp_sva[6])
+      + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[6])) , (conv_u2u_1_2(ACC1_acc_227_psp_sva[7])
+      + conv_u2u_1_2(acc_psp_1_sva[5])) , ACC1_acc_724_cse}) + conv_u2u_7_8({(conv_u2u_1_2(ACC1_1_acc_25_psp_sva[7])
+      + conv_u2u_1_2(acc_psp_2_sva[7])) , (conv_u2u_1_2(acc_psp_1_sva[7]) + conv_u2u_1_2(ACC1_acc_224_psp_sva[4]))
+      , ACC1_acc_724_cse})) + conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_227_psp_sva[11])
+      , (signext_2_1(ACC1_acc_227_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_1_sva[11])
+      , (signext_2_1(acc_psp_1_sva[11]))}))))) + conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_sva[11])
+      , (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_228_psp_sva[11])
+      , (signext_2_1(ACC1_acc_228_psp_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(acc_20_psp_1_sva[11])
+      , 1'b0 , (signext_2_1(acc_20_psp_1_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_20_psp_1_sva[11])
+      , (signext_2_1(acc_20_psp_1_sva[11]))})))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_acc_226_psp_sva[11])
+      , 1'b0 , (signext_2_1(ACC1_acc_226_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_1_sva[11])
+      , (signext_2_1(ACC1_acc_224_psp_1_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b0 , (signext_2_1(ACC1_1_acc_25_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})))));
+  assign nl_ACC1_acc_655_itm_1  = conv_s2s_11_12(conv_u2s_10_11({(acc_20_psp_1_sva[10])
+      , 1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10])
+      , 1'b0 , (acc_20_psp_1_sva[10]) , (ACC1_acc_228_psp_sva[3])}) + conv_s2s_9_11(conv_s2s_8_9(({7'b1011011
+      , (ACC1_1_acc_25_psp_sva[1])}) + conv_u2s_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse)
+      + conv_u2u_3_4(ACC1_acc_509_cse)) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[5]))) + conv_u2u_3_4(ACC1_acc_506_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+      + conv_u2u_3_4(ACC1_acc_502_cse)))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+      + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[7]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[9]))
+      + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))))) + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+      + conv_u2u_4_5(ACC1_acc_562_ncse))))) + conv_u2s_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_502_cse)
+      + conv_u2u_3_4(ACC1_acc_506_cse)) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+      + conv_u2u_3_4(ACC1_acc_489_cse))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[6]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[8]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[10]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_u2u_4_5(ACC1_acc_553_ncse)))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_553_ncse) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_489_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[9]) , ACC1_1_and_3_cse_sva}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_338_itm[2])})))))))))
+      + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[1])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[9]) , (acc_psp_2_sva[4])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (acc_psp_2_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (acc_psp_2_sva[1])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , ((ACC1_acc_227_psp_sva[11])
+      & (~ (ACC1_acc_406_itm[2])) & (ACC1_acc_406_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[6])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[8]) , (~((ACC1_acc_406_itm[2])
+      & (~ (ACC1_acc_227_psp_sva[11]))))})))))))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[10])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , ((ACC1_1_acc_25_psp_sva[11])
+      & (~ (ACC1_acc_368_itm[2])) & (ACC1_acc_368_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (~((ACC1_acc_368_itm[2])
+      & (~ (ACC1_1_acc_25_psp_sva[11]))))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_acc_367_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_1_acc_208_psp_sva[3])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[4]) , (ACC1_1_acc_208_psp_sva[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_1_acc_208_psp_sva[1])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (~((ACC1_acc_349_itm[2])
+      & (~ (ACC1_acc_224_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[9]) , (ACC1_acc_348_itm[2])}))))))))))))
+      + conv_u2s_10_12(conv_u2u_8_10((conv_u2u_7_8({(acc_20_psp_1_sva[7]) , (ACC1_acc_227_psp_sva[7])
+      , 1'b0 , (ACC1_acc_224_psp_sva[6]) , 1'b0 , (signext_2_1(ACC1_acc_224_psp_sva[11]))})
+      + conv_u2u_6_8(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[10]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+      + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_516_cse) + conv_u2u_3_4(ACC1_acc_516_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+      + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))))))) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_412_itm[4])) , (~ (ACC1_acc_423_itm[3])) , (~ (ACC1_acc_338_itm[3]))})
+      + conv_u2u_3_4({(~ (ACC1_acc_375_itm[4])) , 1'b1 , (~ (ACC1_acc_395_itm[3]))}))
+      + conv_u2u_4_5({(readslicef_3_2_1((conv_u2u_2_3({(~ (ACC1_acc_384_itm[4]))
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_3_acc_212_psp_sva[3])) , 1'b1})))) , (({1'b1
+      , (~ (ACC1_acc_414_itm[3]))}) + ({1'b1 , (~ (ACC1_acc_377_itm[3]))}))})) +
+      conv_u2u_5_6(conv_u2u_4_5({(readslicef_3_2_1((conv_u2u_2_3({(~ (ACC1_acc_346_itm[4]))
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_208_psp_sva[3])) , 1'b1})))) , (({1'b1
+      , (~ (ACC1_acc_386_itm[3]))}) + ({1'b1 , (~ (ACC1_acc_405_itm[3]))}))}) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_210_psp_2_sva[3])) , 1'b1 , (~ (ACC1_acc_348_itm[3]))}) + conv_s2u_2_4(ACC1_acc_221_psp_sva[2:1]))))
+      + conv_s2u_6_7(conv_s2s_5_6(conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_221_psp_2_sva[2:1])
+      + conv_u2s_2_4(signext_2_1(ACC1_acc_228_psp_sva[8]))) + conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_219_psp_2_sva[2:1])
+      + conv_u2s_2_4(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_s2s_5_6(conv_s2s_4_5(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_s2s_3_5({(ACC1_acc_222_psp_1_sva[2:1]) , (acc_psp_2_sva[2])}))))
+      + conv_s2s_4_5(readslicef_5_4_1((conv_s2s_3_5({(ACC1_acc_219_psp_1_sva[2:1])
+      , 1'b1}) + conv_u2s_3_5(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , ((ACC1_acc_224_psp_1_sva[11])
+      & (~ (ACC1_acc_349_itm[2])) & (ACC1_acc_349_itm[1]))}))))))))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[6])
+      + conv_u2u_1_2(acc_psp_1_sva[6])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[5]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[5])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[5]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[5])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[6]))
+      + conv_u2u_1_4(acc_psp_2_sva[6])) * 8'b10101)) + conv_u2u_8_9({(acc_20_psp_1_sva[8])
+      , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0 , (acc_20_psp_1_sva[8])
+      , (ACC1_acc_228_psp_sva[2])})));
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [2:0] signext_3_2;
+    input [1:0] vector;
+  begin
+    signext_3_2= {{1{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_3;
+    input [2:0] vector;
+  begin
+    signext_7_3= {{4{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_4;
+    input [3:0] vector;
+  begin
+    signext_7_4= {{3{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_7_10 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_10 = {{3{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [14:0] conv_s2s_14_15 ;
+    input signed [13:0]  vector ;
+  begin
+    conv_s2s_14_15 = {vector[13], vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_13_14 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_14 = {vector[12], vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_2_14 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_14 = {{12{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_4_8 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_8 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_1_4 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_4 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_6_8 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_8 = {{2{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_9_10 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_10 = {vector[8], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_s2u_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2u_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_3_6 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_6 = {{3{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_4_10 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_10 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_24_13 ;
+    input [23:0]  vector ;
+  begin
+    conv_u2s_24_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_4_12 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_12 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_26_13 ;
+    input signed [25:0]  vector ;
+  begin
+    conv_s2s_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_9_11 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_11 = {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_8_9 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_9 = {vector[7], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_s2u_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2u_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_s2u_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2u_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v12/cycle.rpt b/Sobel/sobel.v12/cycle.rpt
new file mode 100644
index 0000000..782a7df
--- /dev/null
+++ b/Sobel/sobel.v12/cycle.rpt
@@ -0,0 +1,85 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 16:18:45 +0000 2016                      
+
+Solution Settings: sobel.v12
+  Current state: schedule
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       677  307201     307200            0  1          
+    Design Total:                     677  307201     307200            0  0          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /sobel/core              
+    
+  I/O Data Ranges
+    Port       Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ---------- ---- -------- --------- --------- ------- -------- --------
+    vin:rsc.z  IN   Unsigned        90                                     
+    clk        IN   Unsigned         1                                     
+    en         IN   Unsigned         1                                     
+    arst_n     IN   Unsigned         1                                     
+    vout:rsc.z OUT  Unsigned        30                                     
+    
+  Memory Resources
+    Resource Name: /sobel/vin:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 90
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable   Indices Phys Memory Address     
+      ---------- ------- -----------------------
+      /sobel/vin    0:89 00000000-00000000 (0-0) 
+      
+    Resource Name: /sobel/vout:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 30
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable    Indices Phys Memory Address     
+      ----------- ------- -----------------------
+      /sobel/vout    0:29 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process     Loop             Iterations C-Steps Total Cycles  Duration  Unroll Init Comments 
+    ----------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
+    /sobel/core core:rlp           Infinite       0       307202   6.14 ms                       
+    /sobel/core   main             Infinite       3       307202   6.14 ms            1          
+    
+  Loop Execution Profile
+    Process     Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------- ---------------- ------------ -------------------------- ----------------- --------
+    /sobel/core core:rlp                   0                        0.00           307200           
+    /sobel/core   main                307202                      100.00           307200           
+    
+  End of Report
diff --git a/Sobel/sobel.v12/cycle.v b/Sobel/sobel.v12/cycle.v
new file mode 100644
index 0000000..4a97651
--- /dev/null
+++ b/Sobel/sobel.v12/cycle.v
@@ -0,0 +1,1598 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 16:18:46 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg [89:0] regs_regs_1_sva;
+    reg [89:0] regs_regs_0_sva;
+    reg [89:0] regs_regs_0_sva_1;
+    reg [11:0] acc_psp_2_sva;
+    reg [3:0] ACC1_acc_210_psp_2_sva;
+    reg [2:0] ACC1_acc_220_psp_1_sva;
+    reg [2:0] acc_imod_26_sva;
+    reg [1:0] acc_imod_32_sva;
+    reg ACC1_1_nand_1_cse_sva;
+    reg ACC1_1_and_3_cse_sva;
+    reg [11:0] ACC1_acc_224_psp_1_sva;
+    reg [3:0] ACC1_acc_214_psp_2_sva;
+    reg [2:0] ACC1_acc_222_psp_1_sva;
+    reg [2:0] acc_imod_34_sva;
+    reg [1:0] acc_imod_36_sva;
+    reg [11:0] acc_20_psp_2_sva;
+    reg [3:0] ACC1_acc_217_psp_2_sva;
+    reg [2:0] ACC1_acc_223_psp_1_sva;
+    reg [2:0] acc_imod_38_sva;
+    reg [1:0] acc_imod_40_sva;
+    reg [11:0] ACC1_1_acc_25_psp_sva;
+    reg [3:0] ACC1_1_acc_208_psp_sva;
+    reg [2:0] ACC1_acc_219_psp_1_sva;
+    reg [2:0] acc_imod_42_sva;
+    reg [1:0] acc_imod_44_sva;
+    reg [11:0] ACC1_acc_228_psp_sva;
+    reg [3:0] ACC1_2_acc_212_psp_sva;
+    reg [2:0] ACC1_acc_221_psp_2_sva;
+    reg [2:0] acc_imod_31_sva;
+    reg [1:0] acc_imod_33_sva;
+    reg [11:0] ACC1_acc_226_psp_sva;
+    reg [3:0] ACC1_2_acc_208_psp_sva;
+    reg [2:0] ACC1_acc_219_psp_2_sva;
+    reg [2:0] acc_imod_43_sva;
+    reg [1:0] acc_imod_45_sva;
+    reg [11:0] acc_psp_1_sva;
+    reg [3:0] ACC1_acc_210_psp_1_sva;
+    reg [2:0] ACC1_acc_220_psp_sva;
+    reg [2:0] acc_imod_2_sva;
+    reg [1:0] acc_imod_3_sva;
+    reg [11:0] ACC1_acc_227_psp_sva;
+    reg [3:0] ACC1_3_acc_212_psp_sva;
+    reg [2:0] ACC1_acc_221_psp_sva;
+    reg [2:0] acc_imod_6_sva;
+    reg [1:0] acc_imod_7_sva;
+    reg [11:0] ACC1_acc_224_psp_sva;
+    reg [3:0] ACC1_acc_214_psp_1_sva;
+    reg [2:0] ACC1_acc_222_psp_sva;
+    reg [2:0] acc_imod_10_sva;
+    reg [1:0] acc_imod_11_sva;
+    reg [11:0] acc_20_psp_1_sva;
+    reg [3:0] ACC1_acc_217_psp_1_sva;
+    reg [2:0] ACC1_acc_223_psp_sva;
+    reg [2:0] acc_imod_18_sva;
+    reg [1:0] acc_imod_19_sva;
+    reg [13:0] ACC1_slc_psp_sva;
+    reg [5:0] acc_imod_24_sva;
+    reg [11:0] FRAME_acc_2_psp_sva;
+    reg [9:0] regs_regs_slc_regs_regs_2_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_1_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_2_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_4_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_5_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_3_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_10_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_11_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_9_itm;
+    reg [12:0] ACC1_acc_659_itm_1;
+    reg [12:0] ACC1_acc_658_itm_1;
+    reg [13:0] ACC1_acc_661_itm_1;
+    reg [13:0] ACC1_mul_57_itm;
+    reg slc_acc_20_psp_1_93_itm_1;
+    reg slc_acc_20_psp_1_94_itm_1;
+    reg slc_acc_20_psp_1_95_itm_1;
+    reg slc_acc_20_psp_1_81_itm_1;
+    reg ACC1_slc_ACC1_acc_228_psp_55_itm_1;
+    reg ACC1_3_slc_acc_10_psp_62_itm_1;
+    reg [10:0] ACC1_acc_652_itm_1;
+    reg [11:0] ACC1_acc_655_itm_1;
+    reg main_stage_0_2;
+    reg [2:0] ACC1_acc_673_cse;
+    reg [2:0] ACC1_acc_699_cse;
+    reg [2:0] ACC1_acc_724_cse;
+    reg [2:0] ACC1_acc_509_cse;
+    reg [2:0] ACC1_acc_506_cse;
+    reg [2:0] ACC1_acc_502_cse;
+    reg [2:0] ACC1_acc_489_cse;
+    reg [2:0] ACC1_acc_516_cse;
+    reg [3:0] ACC1_acc_562_ncse;
+    reg [3:0] ACC1_acc_553_ncse;
+    reg [4:0] ACC1_mul_57_itm_1_sg2;
+    reg [1:0] ACC1_mul_57_itm_2;
+
+    begin : core_rlpExit
+      forever begin : core_rlp
+        // C-Step 0 of Loop 'core_rlp'
+        regs_regs_1_sva = 90'b0;
+        regs_regs_0_sva = 90'b0;
+        main_stage_0_2 = 1'b0;
+        begin : mainExit
+          forever begin : main
+            // C-Step 0 of Loop 'main'
+            regs_regs_slc_regs_regs_2_itm = regs_regs_1_sva[29:20];
+            regs_regs_slc_regs_regs_2_1_itm = regs_regs_1_sva[19:10];
+            regs_regs_slc_regs_regs_2_2_itm = regs_regs_1_sva[9:0];
+            regs_regs_slc_regs_regs_2_4_itm = regs_regs_1_sva[49:40];
+            regs_regs_slc_regs_regs_2_5_itm = regs_regs_1_sva[39:30];
+            regs_regs_slc_regs_regs_2_3_itm = regs_regs_1_sva[59:50];
+            regs_regs_slc_regs_regs_2_10_itm = regs_regs_1_sva[79:70];
+            regs_regs_slc_regs_regs_2_11_itm = regs_regs_1_sva[69:60];
+            regs_regs_slc_regs_regs_2_9_itm = regs_regs_1_sva[89:80];
+            regs_regs_1_sva = regs_regs_0_sva;
+            begin : waitLoop0Exit
+              forever begin : waitLoop0
+                @(posedge clk or negedge ( arst_n ));
+                if ( ~ arst_n )
+                  disable core_rlpExit;
+                if ( en )
+                  disable waitLoop0Exit;
+              end
+            end
+            // C-Step 1 of Loop 'main'
+            if ( main_stage_0_2 ) begin
+              ACC1_slc_psp_sva = readslicef_15_14_1(((conv_s2s_14_15(conv_s2s_13_14(ACC1_acc_659_itm_1)
+                  + conv_s2s_13_14(ACC1_acc_658_itm_1)) + conv_s2s_14_15(ACC1_acc_661_itm_1))
+                  + conv_s2s_14_15(({ACC1_mul_57_itm_1_sg2 , 7'b0 , ACC1_mul_57_itm_2})
+                  + conv_s2s_13_14(conv_s2s_12_13(({slc_acc_20_psp_1_93_itm_1 , 2'b0
+                  , slc_acc_20_psp_1_94_itm_1 , 1'b0 , slc_acc_20_psp_1_95_itm_1
+                  , 1'b0 , slc_acc_20_psp_1_81_itm_1 , ACC1_slc_ACC1_acc_228_psp_55_itm_1
+                  , 1'b0 , ({{1{ACC1_3_slc_acc_10_psp_62_itm_1}}, ACC1_3_slc_acc_10_psp_62_itm_1})})
+                  + conv_u2s_11_12(ACC1_acc_652_itm_1)) + conv_s2s_12_13(ACC1_acc_655_itm_1)))));
+              acc_imod_24_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_slc_psp_sva[8:6])
+                  + conv_u2u_3_4(~ (ACC1_slc_psp_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                  (ACC1_slc_psp_sva[13])) , 1'b1 , (~ (ACC1_slc_psp_sva[13]))}) +
+                  conv_u2u_2_4(ACC1_slc_psp_sva[13:12]))) + conv_u2u_4_6(conv_u2u_3_4(ACC1_slc_psp_sva[2:0])
+                  + conv_u2u_3_4(~ (ACC1_slc_psp_sva[5:3])))) + 6'b101011;
+              FRAME_acc_2_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(ACC1_slc_psp_sva[13:12])
+                  * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_slc_psp_sva[11:9])
+                  * 9'b111001)) + conv_s2s_7_10(conv_u2s_6_7(ACC1_slc_psp_sva[8:3])
+                  + conv_s2s_5_7(({4'b1001 , (acc_imod_24_sva[5])}) + conv_u2s_4_5((conv_u2u_3_4({(~
+                  (acc_imod_24_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_24_sva[2:0])
+                  , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_24_sva[5:3])) , (~ (acc_imod_24_sva[5]))})))))})
+                  + conv_u2u_2_4(acc_imod_24_sva[4:3])) + conv_u2u_3_4(~ (ACC1_slc_psp_sva[8:6])))))))
+                  + conv_u2u_11_12(signext_11_9({(ACC1_slc_psp_sva[13]) , 3'b0 ,
+                  (signext_3_1(ACC1_slc_psp_sva[13])) , 1'b0 , (ACC1_slc_psp_sva[13])}));
+              vout_rsc_mgc_out_stdreg_d <= {((FRAME_acc_2_psp_sva[9:0]) | ({8'b0,
+                  FRAME_acc_2_psp_sva[11:10]})) , (FRAME_acc_2_psp_sva[9:6]) , ((FRAME_acc_2_psp_sva[5:0])
+                  | ({4'b0, FRAME_acc_2_psp_sva[11:10]})) , (FRAME_acc_2_psp_sva[9:0])};
+            end
+            regs_regs_0_sva_1 = vin_rsc_mgc_in_wire_d;
+            acc_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (regs_regs_0_sva_1[29:20]))
+                + conv_s2s_10_11(~ (regs_regs_0_sva_1[19:10]))) + conv_s2s_11_12(conv_s2s_10_11(~
+                (regs_regs_0_sva_1[9:0])) + 11'b11);
+            ACC1_acc_210_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                (acc_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_2_sva[1]))
+                , (acc_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_2_sva[0])
+                , (acc_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[3])) , (~ (acc_psp_2_sva[7]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[5])) , (acc_psp_2_sva[6])}))))
+                , (~ (acc_psp_2_sva[9]))}))));
+            ACC1_acc_220_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_2_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_2_sva[1])) , (ACC1_acc_210_psp_2_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_acc_210_psp_2_sva[3]));
+            acc_imod_26_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_220_psp_1_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_220_psp_1_sva[0]) , 1'b1})));
+            acc_imod_32_sva = readslicef_3_2_1((({1'b1 , (acc_imod_26_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_26_sva[1])) , (~ (acc_imod_26_sva[2]))})));
+            ACC1_1_nand_1_cse_sva = ~((acc_imod_32_sva[1]) & (~ (acc_psp_2_sva[11])));
+            ACC1_1_and_3_cse_sva = (acc_psp_2_sva[11]) & (~ (acc_imod_32_sva[1]))
+                & (acc_imod_32_sva[0]);
+            ACC1_acc_224_psp_1_sva = conv_s2u_11_12(conv_s2s_10_11(~ (regs_regs_0_sva_1[39:30]))
+                + conv_s2s_10_11(~ (regs_regs_0_sva_1[49:40]))) + conv_s2u_11_12(conv_s2s_10_11(~
+                (regs_regs_0_sva_1[59:50])) + 11'b11);
+            ACC1_acc_214_psp_2_sva = readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((({2'b10
+                , (~ (ACC1_acc_224_psp_1_sva[0])) , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[1])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[2])) , (~ (ACC1_acc_224_psp_1_sva[6]))}))))
+                , (~ (ACC1_acc_224_psp_1_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[3])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[4])) , (ACC1_acc_224_psp_1_sva[5])}))))
+                , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_1_sva[11:10])) , (ACC1_acc_224_psp_1_sva[7])}))))
+                , (ACC1_acc_224_psp_1_sva[9])})));
+            ACC1_acc_222_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_214_psp_2_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_214_psp_2_sva[1])) , (ACC1_acc_214_psp_2_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_acc_214_psp_2_sva[3]));
+            acc_imod_34_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_222_psp_1_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_222_psp_1_sva[0]) , 1'b1})));
+            acc_imod_36_sva = readslicef_3_2_1((({1'b1 , (acc_imod_34_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_34_sva[1])) , (~ (acc_imod_34_sva[2]))})));
+            acc_20_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (regs_regs_0_sva_1[89:80]))
+                + conv_s2s_10_11(~ (regs_regs_0_sva_1[79:70]))) + conv_s2s_11_12(conv_s2s_10_11(~
+                (regs_regs_0_sva_1[69:60])) + 11'b11);
+            ACC1_acc_217_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                (acc_20_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_2_sva[1]))
+                , (acc_20_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_2_sva[0])
+                , (acc_20_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[3])) , (~ (acc_20_psp_2_sva[7]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[5])) , (acc_20_psp_2_sva[6])}))))
+                , (~ (acc_20_psp_2_sva[9]))}))));
+            ACC1_acc_223_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_2_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_2_sva[1])) , (ACC1_acc_217_psp_2_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_acc_217_psp_2_sva[3]));
+            acc_imod_38_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_223_psp_1_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_223_psp_1_sva[0]) , 1'b1})));
+            acc_imod_40_sva = readslicef_3_2_1((({1'b1 , (acc_imod_38_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_38_sva[1])) , (~ (acc_imod_38_sva[2]))})));
+            ACC1_1_acc_25_psp_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_0_sva_1[79:70])
+                + conv_s2s_10_11(regs_regs_0_sva_1[69:60])) + conv_s2s_10_12(regs_regs_0_sva_1[89:80]);
+            ACC1_1_acc_208_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                (ACC1_1_acc_25_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_1_acc_25_psp_sva[1]))
+                , (ACC1_1_acc_25_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10
+                , (ACC1_1_acc_25_psp_sva[0]) , (ACC1_1_acc_25_psp_sva[10])})))) +
+                conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[3])) , (~ (ACC1_1_acc_25_psp_sva[7]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[5])) , (ACC1_1_acc_25_psp_sva[6])}))))
+                , (~ (ACC1_1_acc_25_psp_sva[9]))}))));
+            ACC1_acc_219_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_208_psp_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_208_psp_sva[1])) , (ACC1_1_acc_208_psp_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_1_acc_208_psp_sva[3]));
+            acc_imod_42_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_219_psp_1_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_1_sva[0]) , 1'b1})));
+            acc_imod_44_sva = readslicef_3_2_1((({1'b1 , (acc_imod_42_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_42_sva[1])) , (~ (acc_imod_42_sva[2]))})));
+            ACC1_acc_228_psp_sva = conv_s2u_11_12(conv_s2s_10_11(~ (regs_regs_0_sva[9:0]))
+                + conv_s2s_10_11(~ (regs_regs_0_sva[19:10]))) + conv_s2u_11_12(conv_s2s_10_11(~
+                (regs_regs_0_sva[29:20])) + 11'b11);
+            ACC1_2_acc_212_psp_sva = readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((({2'b10
+                , (~ (ACC1_acc_228_psp_sva[0])) , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[1])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[2])) , (~ (ACC1_acc_228_psp_sva[6]))}))))
+                , (~ (ACC1_acc_228_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[3])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[4])) , (ACC1_acc_228_psp_sva[5])}))))
+                , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_228_psp_sva[11:10])) , (ACC1_acc_228_psp_sva[7])}))))
+                , (ACC1_acc_228_psp_sva[9])})));
+            ACC1_acc_221_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_2_acc_212_psp_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_2_acc_212_psp_sva[1])) , (ACC1_2_acc_212_psp_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_2_acc_212_psp_sva[3]));
+            acc_imod_31_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_221_psp_2_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_221_psp_2_sva[0]) , 1'b1})));
+            acc_imod_33_sva = readslicef_3_2_1((({1'b1 , (acc_imod_31_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_31_sva[1])) , (~ (acc_imod_31_sva[2]))})));
+            ACC1_acc_226_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_0_sva[79:70])
+                + conv_s2s_10_11(regs_regs_0_sva[69:60])) + conv_s2u_10_12(regs_regs_0_sva[89:80]);
+            ACC1_2_acc_208_psp_sva = readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((({2'b10
+                , (~ (ACC1_acc_226_psp_sva[0])) , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[1])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[2])) , (~ (ACC1_acc_226_psp_sva[6]))}))))
+                , (~ (ACC1_acc_226_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[3])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[4])) , (ACC1_acc_226_psp_sva[5])}))))
+                , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_226_psp_sva[11:10])) , (ACC1_acc_226_psp_sva[7])}))))
+                , (ACC1_acc_226_psp_sva[9])})));
+            ACC1_acc_219_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_2_acc_208_psp_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_2_acc_208_psp_sva[1])) , (ACC1_2_acc_208_psp_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_2_acc_208_psp_sva[3]));
+            acc_imod_43_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_219_psp_2_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_2_sva[0]) , 1'b1})));
+            acc_imod_45_sva = readslicef_3_2_1((({1'b1 , (acc_imod_43_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_43_sva[1])) , (~ (acc_imod_43_sva[2]))})));
+            acc_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_1_itm)
+                + conv_s2s_10_11(regs_regs_slc_regs_regs_2_2_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_itm);
+            ACC1_acc_210_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                (acc_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_1_sva[1]))
+                , (acc_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_1_sva[0])
+                , (acc_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[3])) , (~ (acc_psp_1_sva[7]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[5])) , (acc_psp_1_sva[6])}))))
+                , (~ (acc_psp_1_sva[9]))}))));
+            ACC1_acc_220_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_1_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_1_sva[1])) , (ACC1_acc_210_psp_1_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_acc_210_psp_1_sva[3]));
+            acc_imod_2_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_220_psp_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_220_psp_sva[0]) , 1'b1})));
+            acc_imod_3_sva = readslicef_3_2_1((({1'b1 , (acc_imod_2_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_2_sva[1])) , (~ (acc_imod_2_sva[2]))})));
+            ACC1_acc_227_psp_sva = conv_s2s_11_12(conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_itm)
+                + conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_1_itm)) + conv_s2s_11_12(conv_s2s_10_11(~
+                regs_regs_slc_regs_regs_2_2_itm) + 11'b11);
+            ACC1_3_acc_212_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                (ACC1_acc_227_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_acc_227_psp_sva[1]))
+                , (ACC1_acc_227_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 ,
+                (ACC1_acc_227_psp_sva[0]) , (ACC1_acc_227_psp_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[3])) , (~ (ACC1_acc_227_psp_sva[7]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[5])) , (ACC1_acc_227_psp_sva[6])}))))
+                , (~ (ACC1_acc_227_psp_sva[9]))}))));
+            ACC1_acc_221_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_3_acc_212_psp_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_3_acc_212_psp_sva[1])) , (ACC1_3_acc_212_psp_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_3_acc_212_psp_sva[3]));
+            acc_imod_6_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_221_psp_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_221_psp_sva[0]) , 1'b1})));
+            acc_imod_7_sva = readslicef_3_2_1((({1'b1 , (acc_imod_6_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_6_sva[1])) , (~ (acc_imod_6_sva[2]))})));
+            ACC1_acc_224_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_4_itm)
+                + conv_s2s_10_11(regs_regs_slc_regs_regs_2_5_itm)) + conv_s2u_10_12(regs_regs_slc_regs_regs_2_3_itm);
+            ACC1_acc_214_psp_1_sva = readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((({2'b10
+                , (~ (ACC1_acc_224_psp_sva[0])) , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[1])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[2])) , (~ (ACC1_acc_224_psp_sva[6]))}))))
+                , (~ (ACC1_acc_224_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[3])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[4])) , (ACC1_acc_224_psp_sva[5])}))))
+                , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_sva[11:10])) , (ACC1_acc_224_psp_sva[7])}))))
+                , (ACC1_acc_224_psp_sva[9])})));
+            ACC1_acc_222_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_214_psp_1_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_214_psp_1_sva[1])) , (ACC1_acc_214_psp_1_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_acc_214_psp_1_sva[3]));
+            acc_imod_10_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_222_psp_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_222_psp_sva[0]) , 1'b1})));
+            acc_imod_11_sva = readslicef_3_2_1((({1'b1 , (acc_imod_10_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_10_sva[1])) , (~ (acc_imod_10_sva[2]))})));
+            acc_20_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_10_itm)
+                + conv_s2s_10_11(regs_regs_slc_regs_regs_2_11_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_9_itm);
+            ACC1_acc_217_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                (acc_20_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_1_sva[1]))
+                , (acc_20_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_1_sva[0])
+                , (acc_20_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[3])) , (~ (acc_20_psp_1_sva[7]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[5])) , (acc_20_psp_1_sva[6])}))))
+                , (~ (acc_20_psp_1_sva[9]))}))));
+            ACC1_acc_223_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_1_sva[0])
+                , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_1_sva[1])) , (ACC1_acc_217_psp_1_sva[2])}))))
+                + conv_s2s_1_3(~ (ACC1_acc_217_psp_1_sva[3]));
+            acc_imod_18_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_223_psp_sva[2:1]))
+                , 1'b1}) + conv_u2s_2_4({(ACC1_acc_223_psp_sva[0]) , 1'b1})));
+            acc_imod_19_sva = readslicef_3_2_1((({1'b1 , (acc_imod_18_sva[0]) , 1'b1})
+                + conv_u2s_2_3({(~ (acc_imod_18_sva[1])) , (~ (acc_imod_18_sva[2]))})));
+            ACC1_acc_673_cse = conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11]));
+            ACC1_acc_699_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])) +
+                conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11]));
+            ACC1_mul_57_itm = conv_s2u_28_14(conv_u2s_2_14((conv_u2u_1_2(ACC1_acc_224_psp_sva[11])
+                + conv_u2u_1_2(ACC1_acc_228_psp_sva[11])) + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[11]))
+                * 14'b11101000000001);
+            ACC1_acc_724_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]));
+            ACC1_acc_509_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]));
+            ACC1_acc_506_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11])) +
+                conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+            ACC1_acc_502_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[5])) + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+            ACC1_acc_489_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]));
+            ACC1_acc_516_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]));
+            ACC1_acc_562_ncse = conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(ACC1_acc_506_cse);
+            ACC1_acc_553_ncse = conv_u2u_3_4(ACC1_acc_489_cse) + conv_u2u_3_4(ACC1_acc_489_cse);
+            regs_regs_0_sva = regs_regs_0_sva_1;
+            ACC1_acc_659_itm_1 = conv_s2s_12_13(conv_s2s_11_12({(ACC1_1_acc_25_psp_sva[11])
+                , 2'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11])
+                , 1'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11])
+                , (ACC1_acc_224_psp_sva[0])}) + conv_u2s_11_12({conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[9])
+                + conv_u2u_1_2(acc_psp_1_sva[9])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[8]))
+                + conv_u2u_1_3(ACC1_acc_228_psp_sva[8])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[8]))
+                + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[8])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[9]))
+                + conv_u2u_1_4(acc_psp_2_sva[9])) * 8'b10101) , (ACC1_acc_227_psp_sva[4])
+                , (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_s2s_12_13(conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_psp_2_sva[10])
+                , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10]) , 1'b0
+                , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_psp_2_sva[9])
+                , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 ,
+                (signext_2_1(acc_psp_2_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_2_sva[7])
+                , 1'b0 , (acc_psp_2_sva[5]) , 1'b0 , (signext_2_1(acc_psp_2_sva[11]))})
+                + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~ (acc_imod_26_sva[2]))}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (acc_imod_26_sva[1])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))))))
+                + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+                , (acc_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_210_psp_2_sva[3])
+                , (acc_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_220_psp_1_sva[2:1]))
+                + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_2_sva[3]) , (acc_psp_2_sva[1])
+                , 1'b1}) + conv_s2s_3_5({(ACC1_acc_210_psp_2_sva[3]) , (acc_psp_2_sva[2])
+                , (ACC1_acc_210_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_2_sva[7])
+                , (acc_psp_2_sva[4]) , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_673_cse)))
+                + conv_u2s_7_8({(acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8]) ,
+                1'b0 , (acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+                , (signext_2_1(acc_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_2_sva[6])
+                , 1'b0 , (acc_psp_2_sva[6]) , 1'b0 , (acc_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_673_cse)
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , ACC1_1_and_3_cse_sva}))))))))))
+                + ({(acc_psp_2_sva[11]) , 2'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11])
+                , 1'b0 , (acc_psp_2_sva[11]) , (conv_u2u_1_3(acc_psp_2_sva[11]) +
+                conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])))})) + conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_20_psp_2_sva[10])
+                , 1'b0 , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10]) ,
+                1'b0 , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10])}) +
+                conv_u2u_8_10(({(acc_20_psp_2_sva[9]) , 1'b0 , (acc_20_psp_2_sva[9])
+                , 1'b0 , (acc_20_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_20_psp_2_sva[5]))})
+                + conv_u2u_7_8(conv_u2u_6_7({(acc_20_psp_2_sva[7]) , 1'b0 , (acc_20_psp_2_sva[5])
+                , 1'b0 , (signext_2_1(acc_20_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~((acc_imod_40_sva[1])
+                & (~ (acc_20_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~
+                (acc_imod_38_sva[2]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (acc_imod_38_sva[1])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (ACC1_acc_217_psp_2_sva[2])}))))))))))
+                + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+                , (acc_20_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_217_psp_2_sva[3])
+                , (acc_20_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_223_psp_1_sva[2:1]))
+                + (readslicef_5_4_1((conv_u2s_3_5({(acc_20_psp_2_sva[3]) , (acc_20_psp_2_sva[1])
+                , 1'b1}) + conv_s2s_3_5({(ACC1_acc_217_psp_2_sva[3]) , (acc_20_psp_2_sva[2])
+                , (ACC1_acc_217_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_20_psp_2_sva[7])
+                , (acc_20_psp_2_sva[4]) , (signext_2_1(acc_20_psp_2_sva[11]))}) +
+                conv_u2u_3_5(ACC1_acc_699_cse))) + conv_u2s_7_8({(acc_20_psp_2_sva[8])
+                , 1'b0 , (acc_20_psp_2_sva[8]) , 1'b0 , (acc_20_psp_2_sva[8]) , 1'b0
+                , (acc_20_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_20_psp_2_sva[11])
+                , (signext_2_1(acc_20_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_20_psp_2_sva[6])
+                , 1'b0 , (acc_20_psp_2_sva[6]) , 1'b0 , (acc_20_psp_2_sva[6])}) +
+                conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_699_cse) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[9]) , ((acc_20_psp_2_sva[11])
+                & (~ (acc_imod_40_sva[1])) & (acc_imod_40_sva[0]))})))))))))) + ({(acc_20_psp_2_sva[11])
+                , 2'b0 , (acc_20_psp_2_sva[11]) , 1'b0 , (acc_20_psp_2_sva[11]) ,
+                1'b0 , (acc_20_psp_2_sva[11]) , (conv_u2u_1_3(acc_20_psp_2_sva[11])
+                + conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])))})));
+            ACC1_acc_658_itm_1 = conv_s2s_12_13(conv_s2s_10_12(conv_s2s_9_10(conv_u2s_7_9(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(ACC1_acc_224_psp_1_sva[6])
+                , (ACC1_acc_228_psp_sva[3]) , (signext_2_1(ACC1_acc_224_psp_sva[11]))})
+                + conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[5]) , (ACC1_acc_226_psp_sva[3])
+                , (signext_2_1(ACC1_acc_228_psp_sva[11]))})) + conv_u2u_5_6(conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[7])
+                , (ACC1_acc_224_psp_1_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})
+                + conv_u2u_4_5({(acc_20_psp_1_sva[4]) , (ACC1_1_acc_25_psp_sva[4])
+                , (signext_2_1(ACC1_acc_228_psp_sva[11]))}))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(~
+                (ACC1_acc_217_psp_1_sva[3])) , (~ (ACC1_acc_210_psp_1_sva[3])) ,
+                1'b1 , (~ (acc_imod_42_sva[2]))}) + conv_u2u_4_5({(acc_psp_2_sva[5])
+                , (acc_20_psp_1_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))}))
+                + conv_s2u_5_6(conv_u2s_3_5(readslicef_4_3_1((conv_u2u_3_4({((acc_20_psp_1_sva[11])
+                & (~ (acc_imod_19_sva[1])) & (acc_imod_19_sva[0])) , (ACC1_acc_224_psp_1_sva[1])
+                , 1'b1}) + conv_u2u_3_4({(acc_psp_2_sva[3]) , (ACC1_acc_224_psp_1_sva[2])
+                , (ACC1_1_acc_25_psp_sva[2])})))) + conv_s2s_3_5({(ACC1_acc_223_psp_sva[2:1])
+                , (ACC1_acc_224_psp_1_sva[3])})))) + conv_s2s_7_9(conv_s2s_6_7(conv_s2s_4_6(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , 1'b1})) + conv_s2s_3_5({(ACC1_acc_220_psp_1_sva[2:1]) , (acc_imod_31_sva[1])}))))
+                + conv_u2s_4_6({(ACC1_acc_224_psp_1_sva[4]) , (ACC1_acc_224_psp_sva[3])
+                , (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_s2s_6_7(conv_u2s_4_6({(acc_psp_2_sva[7])
+                , (acc_psp_2_sva[4]) , (signext_2_1(ACC1_acc_228_psp_sva[6]))}) +
+                conv_s2s_3_6(conv_s2s_2_3(ACC1_acc_220_psp_sva[2:1]) + conv_s2s_2_3(ACC1_acc_222_psp_sva[2:1])))))
+                + conv_u2s_9_10({(acc_20_psp_1_sva[9]) , 1'b0 , (acc_20_psp_1_sva[9])
+                , 1'b0 , (acc_20_psp_1_sva[9]) , (ACC1_acc_228_psp_sva[4]) , 1'b0
+                , (signext_2_1(ACC1_acc_224_psp_sva[6]))})) + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_4_10(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[8])
+                + conv_u2u_1_2(acc_psp_1_sva[8])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[7]))
+                + conv_u2u_1_3(ACC1_acc_228_psp_sva[7])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[7]))
+                + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[7])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[8]))
+                + conv_u2u_1_4(acc_psp_2_sva[8])) * 10'b1010101))) + conv_u2s_12_14(conv_u2s_24_13(conv_u2u_4_12(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[10])
+                + conv_u2u_1_2(acc_psp_1_sva[10])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[9]))
+                + conv_u2u_1_3(ACC1_acc_228_psp_sva[9])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[9]))
+                + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[9])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[10]))
+                + conv_u2u_1_4(acc_psp_2_sva[10])) * 12'b101010101));
+            ACC1_acc_661_itm_1 = conv_s2s_13_14(conv_s2s_12_13({(ACC1_acc_226_psp_sva[11])
+                , 1'b0 , (ACC1_acc_226_psp_sva[11]) , 7'b0 , (ACC1_acc_226_psp_sva[11])
+                , (acc_psp_1_sva[2])}) + conv_u2s_12_13({conv_u2u_18_9(conv_u2u_3_9(conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_224_psp_sva[10])
+                + conv_u2u_1_2(ACC1_acc_228_psp_sva[10])) + conv_u2u_1_2(ACC1_acc_226_psp_sva[10]))
+                + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[10])) * 9'b1010101) , (acc_psp_1_sva[4])
+                , (signext_2_1(ACC1_acc_224_psp_sva[4]))})) + conv_s2s_13_14(conv_s2s_26_13(conv_u2s_2_13((conv_u2u_1_2(ACC1_acc_227_psp_sva[11])
+                + conv_u2u_1_2(acc_psp_1_sva[11])) + conv_u2u_1_2(acc_psp_2_sva[11]))
+                * 13'b1110010101001));
+            ACC1_mul_57_itm_2 = ACC1_mul_57_itm[1:0];
+            ACC1_mul_57_itm_1_sg2 = ACC1_mul_57_itm[13:9];
+            slc_acc_20_psp_1_93_itm_1 = acc_20_psp_1_sva[11];
+            slc_acc_20_psp_1_94_itm_1 = acc_20_psp_1_sva[11];
+            slc_acc_20_psp_1_95_itm_1 = acc_20_psp_1_sva[11];
+            slc_acc_20_psp_1_81_itm_1 = acc_20_psp_1_sva[11];
+            ACC1_slc_ACC1_acc_228_psp_55_itm_1 = ACC1_acc_228_psp_sva[6];
+            ACC1_3_slc_acc_10_psp_62_itm_1 = ACC1_acc_224_psp_sva[8];
+            ACC1_acc_652_itm_1 = conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (ACC1_acc_214_psp_2_sva[3])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (ACC1_acc_214_psp_2_sva[2])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (ACC1_acc_214_psp_2_sva[1])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (acc_imod_6_sva[1])}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (ACC1_3_acc_212_psp_sva[3])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[5])
+                , (ACC1_3_acc_212_psp_sva[2])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (ACC1_3_acc_212_psp_sva[1])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[9]) ,
+                ((ACC1_acc_226_psp_sva[11]) & (~ (acc_imod_45_sva[1])) & (acc_imod_45_sva[0]))}))))))))
+                + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , (~((acc_imod_45_sva[1]) & (~ (ACC1_acc_226_psp_sva[11]))))})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+                , (acc_imod_43_sva[1])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+                , (ACC1_2_acc_208_psp_sva[3])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[5])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_2_acc_208_psp_sva[2])})))))))
+                + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , (ACC1_2_acc_208_psp_sva[1])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , ((ACC1_acc_228_psp_sva[11]) & (~ (acc_imod_33_sva[1])) & (acc_imod_33_sva[0]))}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+                , (~((acc_imod_33_sva[1]) & (~ (ACC1_acc_228_psp_sva[11]))))})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_2_acc_212_psp_sva[3])})))))))))
+                + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_2_acc_212_psp_sva[2])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , (ACC1_2_acc_212_psp_sva[1])}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ((ACC1_acc_224_psp_sva[11])
+                & (~ (acc_imod_11_sva[1])) & (acc_imod_11_sva[0]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~((acc_imod_11_sva[1])
+                & (~ (ACC1_acc_224_psp_sva[11]))))}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (acc_imod_10_sva[1])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_214_psp_1_sva[3])}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[5]) , (ACC1_acc_214_psp_1_sva[2])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_214_psp_1_sva[1])}))))))))
+                + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_227_psp_sva[3])
+                , (ACC1_acc_227_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(acc_psp_1_sva[3])
+                , (ACC1_acc_227_psp_sva[2]) , ((acc_psp_1_sva[11]) & (~ (acc_imod_3_sva[1]))
+                & (acc_imod_3_sva[0]))})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_224_psp_sva[2])
+                , (ACC1_acc_227_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[2])
+                , (ACC1_acc_227_psp_sva[4]) , (~((acc_imod_3_sva[1]) & (~ (acc_psp_1_sva[11]))))})))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_226_psp_sva[2])
+                , (acc_psp_1_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_224_psp_1_sva[2])
+                , (acc_psp_1_sva[3]) , (acc_imod_2_sva[1])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_1_acc_25_psp_sva[3])
+                , (acc_psp_1_sva[4]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[1])
+                , (ACC1_acc_224_psp_sva[1]) , (ACC1_acc_210_psp_1_sva[3])}))))))
+                + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[2])
+                , (ACC1_acc_224_psp_sva[2]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[3])
+                , (ACC1_acc_224_psp_sva[3]) , (ACC1_acc_210_psp_1_sva[2])})))) +
+                conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[4])
+                , (ACC1_acc_228_psp_sva[0]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[1])
+                , (ACC1_acc_226_psp_sva[0]) , (ACC1_acc_210_psp_1_sva[1])}))))) +
+                conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[2])
+                , (ACC1_acc_226_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[3])
+                , (ACC1_acc_226_psp_sva[2]) , (ACC1_1_acc_25_psp_sva[4])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_imod_18_sva[1])
+                , (ACC1_acc_226_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(~((acc_imod_19_sva[1])
+                & (~ (acc_20_psp_1_sva[11])))) , (ACC1_acc_224_psp_1_sva[0]) , (ACC1_1_acc_25_psp_sva[3])})))))))))
+                + conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_3_4({(acc_20_psp_1_sva[6])
+                , 1'b0 , (acc_20_psp_1_sva[6])}) + conv_u2u_3_4({(acc_psp_1_sva[7])
+                , (acc_20_psp_1_sva[5]) , (ACC1_acc_226_psp_sva[4])})) , (conv_u2u_2_3({(acc_20_psp_1_sva[6])
+                , (ACC1_acc_228_psp_sva[1])}) + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[10])))})
+                + conv_u2u_7_8({(conv_u2u_3_4({(ACC1_acc_224_psp_sva[6]) , (acc_20_psp_1_sva[7])
+                , (ACC1_acc_226_psp_sva[6])}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[6])
+                , 1'b0 , (ACC1_acc_227_psp_sva[5])})) , ACC1_acc_724_cse}))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_1_2(ACC1_acc_226_psp_sva[6])
+                + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[6])) , (conv_u2u_1_2(ACC1_acc_227_psp_sva[7])
+                + conv_u2u_1_2(acc_psp_1_sva[5])) , ACC1_acc_724_cse}) + conv_u2u_7_8({(conv_u2u_1_2(ACC1_1_acc_25_psp_sva[7])
+                + conv_u2u_1_2(acc_psp_2_sva[7])) , (conv_u2u_1_2(acc_psp_1_sva[7])
+                + conv_u2u_1_2(ACC1_acc_224_psp_sva[4])) , ACC1_acc_724_cse})) +
+                conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_227_psp_sva[11])
+                , (signext_2_1(ACC1_acc_227_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_1_sva[11])
+                , (signext_2_1(acc_psp_1_sva[11]))}))))) + conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_sva[11])
+                , (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_228_psp_sva[11])
+                , (signext_2_1(ACC1_acc_228_psp_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(acc_20_psp_1_sva[11])
+                , 1'b0 , (signext_2_1(acc_20_psp_1_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_20_psp_1_sva[11])
+                , (signext_2_1(acc_20_psp_1_sva[11]))})))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_acc_226_psp_sva[11])
+                , 1'b0 , (signext_2_1(ACC1_acc_226_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_1_sva[11])
+                , (signext_2_1(ACC1_acc_224_psp_1_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b0 , (signext_2_1(ACC1_1_acc_25_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+                , (signext_2_1(acc_psp_2_sva[11]))})))));
+            ACC1_acc_655_itm_1 = conv_s2s_11_12(conv_u2s_10_11({(acc_20_psp_1_sva[10])
+                , 1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10]) ,
+                1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10]) , (ACC1_acc_228_psp_sva[3])})
+                + conv_s2s_9_11(conv_s2s_8_9(({7'b1011011 , (ACC1_1_acc_25_psp_sva[1])})
+                + conv_u2s_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse)
+                + conv_u2u_3_4(ACC1_acc_509_cse)) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[5]))) + conv_u2u_3_4(ACC1_acc_506_cse)))
+                + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+                + conv_u2u_3_4(ACC1_acc_502_cse)))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+                + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))
+                + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[7]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[9]))
+                + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))))) + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+                + conv_u2u_4_5(ACC1_acc_562_ncse))))) + conv_u2s_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_502_cse)
+                + conv_u2u_3_4(ACC1_acc_506_cse)) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+                + conv_u2u_3_4(ACC1_acc_489_cse))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[6]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[8]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[10]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_u2u_4_5(ACC1_acc_553_ncse)))
+                + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_553_ncse) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_489_cse)))
+                + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[9]) , ACC1_1_and_3_cse_sva}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (acc_imod_26_sva[1])})))))))))
+                + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[3])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[1])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[9]) , (acc_psp_2_sva[4])})))))))
+                + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (acc_psp_2_sva[3])})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , (acc_psp_2_sva[1])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , ((ACC1_acc_227_psp_sva[11]) & (~ (acc_imod_7_sva[1])) & (acc_imod_7_sva[0]))})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[6])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[8])
+                , (~((acc_imod_7_sva[1]) & (~ (ACC1_acc_227_psp_sva[11]))))}))))))))
+                + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[10])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , ((ACC1_1_acc_25_psp_sva[11]) & (~ (acc_imod_44_sva[1])) & (acc_imod_44_sva[0]))})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , (~((acc_imod_44_sva[1]) & (~ (ACC1_1_acc_25_psp_sva[11]))))}))))))
+                + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , (acc_imod_42_sva[1])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , (ACC1_1_acc_208_psp_sva[3])}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[4])
+                , (ACC1_1_acc_208_psp_sva[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+                , (ACC1_1_acc_208_psp_sva[1])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , (~((acc_imod_36_sva[1]) & (~ (ACC1_acc_224_psp_1_sva[11]))))})))))
+                + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[7])
+                , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[9])
+                , (acc_imod_34_sva[1])})))))))))))) + conv_u2s_10_12(conv_u2u_8_10((conv_u2u_7_8({(acc_20_psp_1_sva[7])
+                , (ACC1_acc_227_psp_sva[7]) , 1'b0 , (ACC1_acc_224_psp_sva[6]) ,
+                1'b0 , (signext_2_1(ACC1_acc_224_psp_sva[11]))}) + conv_u2u_6_8(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[10]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+                + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_516_cse) + conv_u2u_3_4(ACC1_acc_516_cse)))
+                + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+                + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+                + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))
+                + conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))))))) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4({(~
+                (ACC1_acc_214_psp_1_sva[3])) , (~ (acc_imod_18_sva[2])) , (~ (acc_imod_26_sva[2]))})
+                + conv_u2u_3_4({(~ (ACC1_2_acc_212_psp_sva[3])) , 1'b1 , (~ (acc_imod_2_sva[2]))}))
+                + conv_u2u_4_5({(conv_u2u_1_2(~ (ACC1_2_acc_208_psp_sva[3])) + conv_u2u_1_2(~
+                (ACC1_3_acc_212_psp_sva[3])) + 2'b1) , (({1'b1 , (~ (acc_imod_10_sva[2]))})
+                + ({1'b1 , (~ (acc_imod_31_sva[2]))}))})) + conv_u2u_5_6(conv_u2u_4_5({(conv_u2u_1_2(~
+                (ACC1_acc_214_psp_2_sva[3])) + conv_u2u_1_2(~ (ACC1_1_acc_208_psp_sva[3]))
+                + 2'b1) , (({1'b1 , (~ (acc_imod_43_sva[2]))}) + ({1'b1 , (~ (acc_imod_6_sva[2]))}))})
+                + conv_u2u_4_5(conv_u2u_3_4({(~ (ACC1_acc_210_psp_2_sva[3])) , 1'b1
+                , (~ (acc_imod_34_sva[2]))}) + conv_s2u_2_4(ACC1_acc_221_psp_sva[2:1]))))
+                + conv_s2u_6_7(conv_s2s_5_6(conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_221_psp_2_sva[2:1])
+                + conv_u2s_2_4(signext_2_1(ACC1_acc_228_psp_sva[8]))) + conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_219_psp_2_sva[2:1])
+                + conv_u2s_2_4(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_s2s_5_6(conv_s2s_4_5(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(acc_psp_1_sva[11])
+                , 1'b1})) + conv_s2s_3_5({(ACC1_acc_222_psp_1_sva[2:1]) , (acc_psp_2_sva[2])}))))
+                + conv_s2s_4_5(readslicef_5_4_1((conv_s2s_3_5({(ACC1_acc_219_psp_1_sva[2:1])
+                , 1'b1}) + conv_u2s_3_5(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+                , ((ACC1_acc_224_psp_1_sva[11]) & (~ (acc_imod_36_sva[1])) & (acc_imod_36_sva[0]))})))))))))
+                + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[6])
+                + conv_u2u_1_2(acc_psp_1_sva[6])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[5]))
+                + conv_u2u_1_3(ACC1_acc_228_psp_sva[5])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[5]))
+                + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[5])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[6]))
+                + conv_u2u_1_4(acc_psp_2_sva[6])) * 8'b10101)) + conv_u2u_8_9({(acc_20_psp_1_sva[8])
+                , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0
+                , (acc_20_psp_1_sva[8]) , (ACC1_acc_228_psp_sva[2])})));
+            main_stage_0_2 = 1'b1;
+          end
+        end
+      end
+    end
+    ACC1_mul_57_itm_2 = 2'b0;
+    ACC1_mul_57_itm_1_sg2 = 5'b0;
+    ACC1_acc_553_ncse = 4'b0;
+    ACC1_acc_562_ncse = 4'b0;
+    ACC1_acc_516_cse = 3'b0;
+    ACC1_acc_489_cse = 3'b0;
+    ACC1_acc_502_cse = 3'b0;
+    ACC1_acc_506_cse = 3'b0;
+    ACC1_acc_509_cse = 3'b0;
+    ACC1_acc_724_cse = 3'b0;
+    ACC1_acc_699_cse = 3'b0;
+    ACC1_acc_673_cse = 3'b0;
+    main_stage_0_2 = 1'b0;
+    ACC1_acc_655_itm_1 = 12'b0;
+    ACC1_acc_652_itm_1 = 11'b0;
+    ACC1_3_slc_acc_10_psp_62_itm_1 = 1'b0;
+    ACC1_slc_ACC1_acc_228_psp_55_itm_1 = 1'b0;
+    slc_acc_20_psp_1_81_itm_1 = 1'b0;
+    slc_acc_20_psp_1_95_itm_1 = 1'b0;
+    slc_acc_20_psp_1_94_itm_1 = 1'b0;
+    slc_acc_20_psp_1_93_itm_1 = 1'b0;
+    ACC1_mul_57_itm = 14'b0;
+    ACC1_acc_661_itm_1 = 14'b0;
+    ACC1_acc_658_itm_1 = 13'b0;
+    ACC1_acc_659_itm_1 = 13'b0;
+    regs_regs_slc_regs_regs_2_9_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_11_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_10_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_3_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_5_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_4_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_2_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_1_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_itm = 10'b0;
+    FRAME_acc_2_psp_sva = 12'b0;
+    acc_imod_24_sva = 6'b0;
+    ACC1_slc_psp_sva = 14'b0;
+    acc_imod_19_sva = 2'b0;
+    acc_imod_18_sva = 3'b0;
+    ACC1_acc_223_psp_sva = 3'b0;
+    ACC1_acc_217_psp_1_sva = 4'b0;
+    acc_20_psp_1_sva = 12'b0;
+    acc_imod_11_sva = 2'b0;
+    acc_imod_10_sva = 3'b0;
+    ACC1_acc_222_psp_sva = 3'b0;
+    ACC1_acc_214_psp_1_sva = 4'b0;
+    ACC1_acc_224_psp_sva = 12'b0;
+    acc_imod_7_sva = 2'b0;
+    acc_imod_6_sva = 3'b0;
+    ACC1_acc_221_psp_sva = 3'b0;
+    ACC1_3_acc_212_psp_sva = 4'b0;
+    ACC1_acc_227_psp_sva = 12'b0;
+    acc_imod_3_sva = 2'b0;
+    acc_imod_2_sva = 3'b0;
+    ACC1_acc_220_psp_sva = 3'b0;
+    ACC1_acc_210_psp_1_sva = 4'b0;
+    acc_psp_1_sva = 12'b0;
+    acc_imod_45_sva = 2'b0;
+    acc_imod_43_sva = 3'b0;
+    ACC1_acc_219_psp_2_sva = 3'b0;
+    ACC1_2_acc_208_psp_sva = 4'b0;
+    ACC1_acc_226_psp_sva = 12'b0;
+    acc_imod_33_sva = 2'b0;
+    acc_imod_31_sva = 3'b0;
+    ACC1_acc_221_psp_2_sva = 3'b0;
+    ACC1_2_acc_212_psp_sva = 4'b0;
+    ACC1_acc_228_psp_sva = 12'b0;
+    acc_imod_44_sva = 2'b0;
+    acc_imod_42_sva = 3'b0;
+    ACC1_acc_219_psp_1_sva = 3'b0;
+    ACC1_1_acc_208_psp_sva = 4'b0;
+    ACC1_1_acc_25_psp_sva = 12'b0;
+    acc_imod_40_sva = 2'b0;
+    acc_imod_38_sva = 3'b0;
+    ACC1_acc_223_psp_1_sva = 3'b0;
+    ACC1_acc_217_psp_2_sva = 4'b0;
+    acc_20_psp_2_sva = 12'b0;
+    acc_imod_36_sva = 2'b0;
+    acc_imod_34_sva = 3'b0;
+    ACC1_acc_222_psp_1_sva = 3'b0;
+    ACC1_acc_214_psp_2_sva = 4'b0;
+    ACC1_acc_224_psp_1_sva = 12'b0;
+    ACC1_1_and_3_cse_sva = 1'b0;
+    ACC1_1_nand_1_cse_sva = 1'b0;
+    acc_imod_32_sva = 2'b0;
+    acc_imod_26_sva = 3'b0;
+    ACC1_acc_220_psp_1_sva = 3'b0;
+    ACC1_acc_210_psp_2_sva = 4'b0;
+    acc_psp_2_sva = 12'b0;
+    regs_regs_0_sva_1 = 90'b0;
+    regs_regs_0_sva = 90'b0;
+    regs_regs_1_sva = 90'b0;
+    vout_rsc_mgc_out_stdreg_d <= 30'b0;
+  end
+
+
+  function [13:0] readslicef_15_14_1;
+    input [14:0] vector;
+    reg [14:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_15_14_1 = tmp[13:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_2;
+    input [1:0] vector;
+  begin
+    signext_3_2= {{1{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_3;
+    input [2:0] vector;
+  begin
+    signext_7_3= {{4{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_4;
+    input [3:0] vector;
+  begin
+    signext_7_4= {{3{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [14:0] conv_s2s_14_15 ;
+    input signed [13:0]  vector ;
+  begin
+    conv_s2s_14_15 = {vector[13], vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_13_14 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_14 = {vector[12], vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_7_10 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_10 = {{3{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_s2u_28_14 ;
+    input signed [27:0]  vector ;
+  begin
+    conv_s2u_28_14 = vector[13:0];
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_2_14 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_14 = {{12{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_4_8 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_8 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_1_4 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_4 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_6_8 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_8 = {{2{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_9_10 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_10 = {vector[8], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_s2u_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2u_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_3_6 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_6 = {{3{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_4_10 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_10 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_24_13 ;
+    input [23:0]  vector ;
+  begin
+    conv_u2s_24_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_4_12 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_12 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_26_13 ;
+    input signed [25:0]  vector ;
+  begin
+    conv_s2s_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_9_11 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_11 = {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_8_9 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_9 = {vector[7], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_s2u_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2u_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_s2u_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2u_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v12/cycle_mgc_ioport.v b/Sobel/sobel.v12/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v12/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v12/cycle_mgc_ioport_v2001.v b/Sobel/sobel.v12/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v12/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v12/cycle_set.tcl b/Sobel/sobel.v12/cycle_set.tcl
new file mode 100644
index 0000000..1afb9a0
--- /dev/null
+++ b/Sobel/sobel.v12/cycle_set.tcl
@@ -0,0 +1,489 @@
+
+# Loop constraints
+directive set /sobel/core/core:rlp CSTEPS_FROM {{. == 0}}
+directive set /sobel/core/core:rlp/main CSTEPS_FROM {{. == 3} {.. == 0}}
+
+# IO operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:io_read(vin:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:io_write(vout:rsc.d) CSTEPS_FROM {{.. == 2}}
+
+# Real operation constraints
+directive set /sobel/core/core:rlp/main/ACC1:acc#331 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#330 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#334 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#336 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#333 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#332 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#335 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#210 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#337 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#220 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#338 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#339 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#341 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#340 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#224 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#343 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#345 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#342 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#344 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#346 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#347 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#225 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#348 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#349 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#351 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#350 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#20 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#354 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#356 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#353 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#352 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#355 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#217 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#357 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#223 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#358 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#359 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#360 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#363 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#365 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#362 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#361 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#364 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#208 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#366 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#219 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#367 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#368 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#370 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#369 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#228 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#372 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#374 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#371 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#373 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#375 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#376 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-2:acc#221 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#377 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#378 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#379 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#226 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#381 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#383 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#380 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#382 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#384 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#385 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-2:acc#219 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#386 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#387 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#388 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#391 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#393 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#390 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#389 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#392 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#210 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#394 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#220 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#395 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#396 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#398 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#397 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#227 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#401 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#403 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#400 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#399 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#402 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#212 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#404 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#221 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#405 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#406 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#407 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#224 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#409 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#411 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#408 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#410 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#412 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#413 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#225 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#414 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#415 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#416 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#20 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#419 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#421 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#418 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#417 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#420 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#217 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#422 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#223 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#423 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#424 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#326 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#325 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#324 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#323 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#322 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#321 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#320 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#58 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#654 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#670 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#669 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#676 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#668 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#667 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#675 CSTEPS_FROM {{.. == 1}}
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+directive set /sobel/core/core:rlp/main/ACC1:acc#551 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#591 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#480 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#479 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#550 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#478 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#477 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#549 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#590 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#610 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#625 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#476 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#475 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#548 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#474 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#473 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#547 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#589 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#472 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#470 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#546 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#469 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#468 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#545 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#588 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#609 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#467 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#466 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#544 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#465 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#464 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#543 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#587 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#463 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#462 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#542 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#460 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#459 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#541 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#586 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#608 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#624 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#637 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#645 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#650 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#517 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#516 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#568 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#515 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#514 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#567 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#599 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#513 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#512 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#566 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#511 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#510 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#565 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#598 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#614 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#627 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#523 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#522 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#577 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#521 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#520 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#576 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#603 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#518 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#490 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#575 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#471 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#461 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#574 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#602 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#621 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#640 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#301 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#300 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#299 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#298 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#297 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#296 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#295 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#639 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#647 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#655 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#660 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#663 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#6 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#5 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#8 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#7 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#9 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/acc#30 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#1 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#16 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#10 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#11 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#12 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#13 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#14 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#15 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#2 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc CSTEPS_FROM {{.. == 1}}
diff --git a/Sobel/sobel.v12/directives.tcl b/Sobel/sobel.v12/directives.tcl
new file mode 100644
index 0000000..504c4bb
--- /dev/null
+++ b/Sobel/sobel.v12/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
+go extract
diff --git a/Sobel/sobel.v12/messages.txt b/Sobel/sobel.v12/messages.txt
new file mode 100644
index 0000000..76e600a
--- /dev/null
+++ b/Sobel/sobel.v12/messages.txt
@@ -0,0 +1,245 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v3' at state 'new' (PRJ-2)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v3' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v3': elapsed time 3.14 seconds, memory usage 379144kB, peak memory usage 498484kB (SOL-9)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.cpp(121): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+
+# Messages from "go compile"
+
+Starting transformation 'compile' on solution 'solution.v3' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'sobel' specified by directive (CIN-52)
+Synthesizing routine 'sobel' (CIN-13)
+Inlining routine 'sobel' (CIN-14)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Optimizing block '/sobel' ... (CIN-4)
+Inout port 'vin' is only used as an input. (OPT-10)
+Inout port 'vout' is only used as an output. (OPT-11)
+Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+Detected constant initialization of array 'inte', optimizing loop 'RESET' (LOOP-12)
+Design 'sobel' was read (SOL-1)
+Optimizing partition '/sobel': (Total ops = 1693, Real ops = 337, Vars = 368) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1693, Real ops = 337, Vars = 366) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1658, Real ops = 327, Vars = 372) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1658, Real ops = 327, Vars = 374) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1658, Real ops = 327, Vars = 374) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1658, Real ops = 327, Vars = 372) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1602, Real ops = 326, Vars = 359) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1577, Real ops = 326, Vars = 358) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1577, Real ops = 326, Vars = 358) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1577, Real ops = 326, Vars = 360) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1577, Real ops = 326, Vars = 360) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1556, Real ops = 324, Vars = 402) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 57) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1177, Real ops = 184, Vars = 60) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 848, Real ops = 155, Vars = 50) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 846, Real ops = 155, Vars = 50) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 846, Real ops = 155, Vars = 52) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 842, Real ops = 155, Vars = 54) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 840, Real ops = 155, Vars = 50) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 840, Real ops = 155, Vars = 52) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 840, Real ops = 155, Vars = 50) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 840, Real ops = 155, Vars = 52) (SOL-10)
+Completed transformation 'compile' on solution 'sobel.v12': elapsed time 9.08 seconds, memory usage 376880kB, peak memory usage 498484kB (SOL-9)
+Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'sobel.v12' (SOL-8)
+Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+Loop '/sobel/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/sobel/core': (Total ops = 2387, Real ops = 428, Vars = 50) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1805, Real ops = 303, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1797, Real ops = 303, Vars = 73) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1797, Real ops = 303, Vars = 73) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1701, Real ops = 260, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1548, Real ops = 285, Vars = 61) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1519, Real ops = 295, Vars = 59) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1519, Real ops = 295, Vars = 64) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 60) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1516, Real ops = 295, Vars = 68) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1516, Real ops = 295, Vars = 63) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1489, Real ops = 300, Vars = 59) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1489, Real ops = 300, Vars = 64) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1489, Real ops = 300, Vars = 59) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1489, Real ops = 300, Vars = 64) (SOL-10)
+Design 'sobel' contains '676' real operations. (SOL-11)
+Optimizing partition '/sobel/core': (Total ops = 1492, Real ops = 300, Vars = 60) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1926, Real ops = 304, Vars = 311) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1496, Real ops = 302, Vars = 63) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1495, Real ops = 302, Vars = 62) (SOL-10)
+Completed transformation 'architect' on solution 'sobel.v12': elapsed time 23.82 seconds, memory usage 377284kB, peak memory usage 498484kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'sobel.v12' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 307201, Area (Datapath, Register, Total) = 5750.29, 0.00, 5750.29 (CRAAS-11)
+Optimized LOOP 'main': Latency = 307201, Area (Datapath, Register, Total) = 5558.68, 0.00, 5558.68 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 307201, Area (Datapath, Register, Total) = 5558.68, 0.00, 5558.68 (CRAAS-12)
+Completed transformation 'allocate' on solution 'sobel.v12': elapsed time 16.72 seconds, memory usage 382608kB, peak memory usage 498484kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'sobel.v12' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 2382, Real ops = 677, Vars = 121) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2372, Real ops = 676, Vars = 113) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 2367, Real ops = 676, Vars = 108) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 2174, Real ops = 648, Vars = 96) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 2158, Real ops = 648, Vars = 91) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2172, Real ops = 648, Vars = 103) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2163, Real ops = 648, Vars = 96) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 2155, Real ops = 648, Vars = 93) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 2155, Real ops = 648, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2169, Real ops = 648, Vars = 104) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2160, Real ops = 648, Vars = 97) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 2155, Real ops = 648, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2169, Real ops = 648, Vars = 104) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2160, Real ops = 648, Vars = 97) (SOL-10)
+Completed transformation 'schedule' on solution 'sobel.v12': elapsed time 8.02 seconds, memory usage 389548kB, peak memory usage 498484kB (SOL-9)
+Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'sobel.v12' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 2428, Real ops = 663, Vars = 1568) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2419, Real ops = 663, Vars = 1561) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 3946, Real ops = 670, Vars = 100) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 3937, Real ops = 670, Vars = 93) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+Completed transformation 'dpfsm' on solution 'sobel.v12': elapsed time 4.18 seconds, memory usage 391324kB, peak memory usage 498484kB (SOL-9)
+
+# Messages from "go extract"
+
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'sobel.v12' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2151, Real ops = 668, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2142, Real ops = 668, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2151, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2142, Real ops = 668, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2151, Real ops = 668, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2142, Real ops = 668, Vars = 92) (SOL-10)
+Completed transformation 'extract' on solution 'sobel.v12': elapsed time 18.09 seconds, memory usage 395324kB, peak memory usage 498484kB (SOL-9)
diff --git a/Sobel/sobel.v12/reg_sharing.tcl b/Sobel/sobel.v12/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v12/reg_sharing.tcl
diff --git a/Sobel/sobel.v12/res_sharing.tcl b/Sobel/sobel.v12/res_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v12/res_sharing.tcl
diff --git a/Sobel/sobel.v12/rtl.rpt b/Sobel/sobel.v12/rtl.rpt
new file mode 100644
index 0000000..4a9ca8e
--- /dev/null
+++ b/Sobel/sobel.v12/rtl.rpt
@@ -0,0 +1,1144 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 16:19:42 +0000 2016                      
+
+Solution Settings: sobel.v12
+  Current state: extract
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       677  307201     307200            0  1          
+    Design Total:                     677  307201     307200            0  0          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(1,0,1,0,2)                           2.319                       0.000      2.319 0.506          7          11 
+    mgc_add(10,0,10,0,11)                       11.241                       0.000     11.241 1.301          3           1 
+    mgc_add(10,0,10,1,12)                       11.000                       0.000     11.000 0.976          4           4 
+    mgc_add(10,1,10,1,11)                       11.000                       0.000     11.000 1.139         15          15 
+    mgc_add(11,0,11,1,12)                       12.000                       0.000     12.000 1.206          2           2 
+    mgc_add(11,1,11,1,12)                       12.000                       0.000     12.000 1.206         14          14 
+    mgc_add(12,0,12,1,13)                       13.000                       0.000     13.000 1.272          2           2 
+    mgc_add(12,1,12,1,13)                       13.000                       0.000     13.000 1.272          4           4 
+    mgc_add(13,1,13,1,14)                       14.000                       0.000     14.000 1.337          2           2 
+    mgc_add(14,1,14,1,15)                       15.000                       0.000     15.000 1.401          2           2 
+    mgc_add(15,0,14,1,15)                       16.000                       0.000     16.000 1.628          1           1 
+    mgc_add(19,0,2,1,19)                        20.000                       0.000     20.000 1.908          1           0 
+    mgc_add(2,0,1,0,3)                           3.315                       0.000      3.315 0.658          0           2 
+    mgc_add(2,0,2,0,2)                           3.311                       0.000      3.311 0.653          0           2 
+    mgc_add(2,0,2,0,3)                           3.311                       0.000      3.311 0.653         71          50 
+    mgc_add(2,0,2,1,4)                           3.000                       0.000      3.000 0.328         30          30 
+    mgc_add(2,1,2,1,3)                           3.000                       0.000      3.000 0.490          1           1 
+    mgc_add(3,0,3,0,4)                           4.302                       0.000      4.302 0.761        123         119 
+    mgc_add(3,0,3,1,5)                           4.000                       0.000      4.000 0.436         49          49 
+    mgc_add(3,1,2,1,4)                           4.000                       0.000      4.000 0.602          4           4 
+    mgc_add(4,0,4,0,5)                           5.293                       0.000      5.293 0.854         30          30 
+    mgc_add(4,0,4,1,6)                           5.000                       0.000      5.000 0.529         15          15 
+    mgc_add(4,1,4,1,5)                           5.000                       0.000      5.000 0.691         10          10 
+    mgc_add(5,0,5,0,6)                           6.285                       0.000      6.285 0.938         13          13 
+    mgc_add(5,0,5,1,7)                           6.000                       0.000      6.000 0.613         12          12 
+    mgc_add(5,1,5,1,6)                           6.000                       0.000      6.000 0.775          1           1 
+    mgc_add(6,0,6,0,7)                           7.276                       0.000      7.276 1.016         10           6 
+    mgc_add(6,0,6,1,8)                           7.000                       0.000      7.000 0.691          5           5 
+    mgc_add(6,1,6,1,7)                           7.000                       0.000      7.000 0.854          1           1 
+    mgc_add(7,0,7,0,8)                           8.267                       0.000      8.267 1.091          9           9 
+    mgc_add(7,0,7,1,9)                           8.000                       0.000      8.000 0.766          6           6 
+    mgc_add(8,0,8,0,9)                           9.259                       0.000      9.259 1.163          5           5 
+    mgc_add(8,0,8,1,10)                          9.000                       0.000      9.000 0.838          8           7 
+    mgc_add(9,0,9,0,10)                         10.250                       0.000     10.250 1.233          2           2 
+    mgc_add(9,0,9,1,11)                         10.000                       0.000     10.000 0.908          5           5 
+    mgc_and(1,3)                                 1.054                       0.000      1.054 0.416          0          10 
+    mgc_and(19,2)                               13.867                       0.000     13.867 0.263          1           0 
+    mgc_mul(2,0,11,1,13)                       330.000                       2.000     10.000 3.129          2           2 
+    mgc_mul(2,0,12,1,14)                       330.000                       2.000     10.000 3.172          1           1 
+    mgc_mul(3,0,6,0,9)                         330.250                       2.000     10.250 2.846          1           1 
+    mgc_mul(4,0,5,0,8)                         330.250                       2.000     10.250 2.715          2           2 
+    mgc_mul(4,0,7,0,10)                        330.250                       2.000     10.250 2.850          2           2 
+    mgc_mul(4,0,9,0,12)                        330.250                       2.000     10.250 2.985          1           1 
+    mgc_mux(30,1,2)                             27.583                       0.000     27.583 0.369          0           1 
+    mgc_nand(1,2)                                0.730                       0.000      0.730 0.268          0          10 
+    mgc_not(1)                                   0.000                       0.000      0.000 0.000          0         141 
+    mgc_not(10)                                  0.000                       0.000      0.000 0.000          0          15 
+    mgc_not(2)                                   0.000                       0.000      0.000 0.000          0          14 
+    mgc_not(3)                                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_or(10,2)                                 7.298                       0.000      7.298 0.268          1           1 
+    mgc_or(6,2)                                  4.379                       0.000      4.379 0.268          1           1 
+    mgc_reg_pos(1,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_reg_pos(10,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           9 
+    mgc_reg_pos(11,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(12,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(13,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(14,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(2,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(30,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(5,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(90,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,90)                            0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(2,30)                         0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):            5445.451                      18.000   2565.000                              
+    
+  Area Scores
+                      Post-Scheduling   Post-DP & FSM Post-Assignment 
+    ----------------- --------------- --------------- ---------------
+    Total Area Score:   5558.7          5445.5          5445.5        
+    Total Reg:             0.0             0.0             0.0        
+                                                                      
+    DataPath:           5558.7 (100%)   5445.5 (100%)   5445.5 (100%) 
+      MUX:                 0.0            27.6   (1%)     27.6   (1%) 
+      FUNC:             5533.1 (100%)   5388.3  (99%)   5388.3  (99%) 
+      LOGIC:              25.5   (0%)     29.5   (1%)     29.5   (1%) 
+      BUFFER:              0.0             0.0             0.0        
+      MEM:                 0.0             0.0             0.0        
+      ROM:                 0.0             0.0             0.0        
+      REG:                 0.0             0.0             0.0        
+                                                                      
+    
+    FSM:                   0.0             0.0             0.0        
+      FSM-REG:             0.0             0.0             0.0        
+      FSM-COMB:            0.0             0.0             0.0        
+                                                                      
+    
+  Register-to-Variable Mappings
+    Register                            Size(bits) Gated Register CG Opt Done Variables                                             
+    ----------------------------------- ---------- -------------- ----------- -----------------------------------------------------
+    reg(regs.regs(0).sva).cse                   90         Y                  reg(regs.regs(0).sva).cse                             
+    vout:rsc:mgc_out_stdreg.d                   30         Y                  vout:rsc:mgc_out_stdreg.d                             
+    ACC1:acc#661.itm#1                          14         Y                  ACC1:acc#661.itm#1                                    
+    ACC1:acc#658.itm#1                          13         Y                  ACC1:acc#658.itm#1                                    
+    ACC1:acc#659.itm#1                          13         Y                  ACC1:acc#659.itm#1                                    
+    ACC1:acc#655.itm#1                          12         Y                  ACC1:acc#655.itm#1                                    
+    ACC1:acc#652.itm#1                          11         Y                  ACC1:acc#652.itm#1                                    
+    regs.regs:slc(regs.regs(2))#1.itm           10         Y                  regs.regs:slc(regs.regs(2))#1.itm                     
+    regs.regs:slc(regs.regs(2))#10.itm          10         Y                  regs.regs:slc(regs.regs(2))#10.itm                    
+    regs.regs:slc(regs.regs(2))#11.itm          10         Y                  regs.regs:slc(regs.regs(2))#11.itm                    
+    regs.regs:slc(regs.regs(2))#2.itm           10         Y                  regs.regs:slc(regs.regs(2))#2.itm                     
+    regs.regs:slc(regs.regs(2))#3.itm           10         Y                  regs.regs:slc(regs.regs(2))#3.itm                     
+    regs.regs:slc(regs.regs(2))#4.itm           10         Y                  regs.regs:slc(regs.regs(2))#4.itm                     
+    regs.regs:slc(regs.regs(2))#5.itm           10         Y                  regs.regs:slc(regs.regs(2))#5.itm                     
+    regs.regs:slc(regs.regs(2))#9.itm           10         Y                  regs.regs:slc(regs.regs(2))#9.itm                     
+    regs.regs:slc(regs.regs(2)).itm             10         Y                  regs.regs:slc(regs.regs(2)).itm                       
+    ACC1:mul#57.itm#1.sg2                        5         Y                  ACC1:mul#57.itm#1.sg2                                 
+    ACC1:mul#57.itm#2                            2         Y                  ACC1:mul#57.itm#2                                     
+    ACC1-3:slc(acc#10.psp)#62.itm#1              1         Y                  ACC1-3:slc(acc#10.psp)#62.itm#1                       
+    ACC1:slc(ACC1:acc#228.psp)#55.itm#1          1         Y                  ACC1:slc(ACC1:acc#228.psp)#55.itm#1                   
+    main.stage_0#2                               1         Y                  main.stage_0#2                                        
+    slc(acc#20.psp#1)#93.itm#1                   1         Y                  slc(acc#20.psp#1)#93.itm#1                            
+                                                                                                                                    
+    Total:                                     284            284           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  15.879753
+      Slack:      4.120247000000001
+      
+      Path                                           Startpoint                       Endpoint                           Delay   Slack   
+      ---------------------------------------------- -------------------------------- ---------------------------------- ------- -------
+      1                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]:not               mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]:not.itm                                                                               0.0000  0.0000  
+        sobel:core/ACC1:acc#331                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#331.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc                        mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                         0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3                                                                                  0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3.itm                                                                              0.0000  2.3449  
+        sobel:core/conc#1010                                                                                             0.0000  2.3449  
+        sobel:core/conc#1010.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#333                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#333.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#14                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#14.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1009                                                                                             0.0000  2.9974  
+        sobel:core/conc#1009.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#335                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#335.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#16                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#16.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#210                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#210.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4.itm                                                                     0.0000  4.2869  
+        sobel:core/conc#1086                                                                                             0.0000  4.2869  
+        sobel:core/conc#1086.itm                                                                                         0.0000  4.2869  
+        sobel:core/ACC1:acc#337                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#337.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#18                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#18.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#220                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#220.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)                                                                           0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva).itm                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#293                    mgc_not_2                                                           0.0000  5.2670  
+        sobel:core/ACC1-1:not#293.itm                                                                                    0.0000  5.2670  
+        sobel:core/conc#1004                                                                                             0.0000  5.2670  
+        sobel:core/conc#1004.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#338                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#338.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#19                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#26.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/conc#1099                                                                                             0.0000  5.7029  
+        sobel:core/conc#1099.itm                                                                                         0.0000  5.7029  
+        sobel:core/ACC1:acc#339                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#339.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#20                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#32.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva)                                                                                  0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva).itm                                                                              0.0000  6.1389  
+        sobel:core/ACC1-1:nand#1                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#1.cse.sva                                                                                 0.0000  6.4067  
+        sobel:core/ACC1:conc#1430                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1430.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1474                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1474.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#670                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#670.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#153                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#153.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#676                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#676.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#680                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#680.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#683                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#683.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#686                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#686.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#688                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#688.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#690                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#690.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#2                      mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#2.itm                                                                                      0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      2                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not            mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not.itm                                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#351                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#351.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc#20                     mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc#20.psp#2.sva                                                                                      0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17                                                                              0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17.itm                                                                          0.0000  2.3449  
+        sobel:core/conc#1096                                                                                             0.0000  2.3449  
+        sobel:core/conc#1096.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#353                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#353.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#30                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#30.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1095                                                                                             0.0000  2.9974  
+        sobel:core/conc#1095.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#355                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#355.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#32                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#32.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#217                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#217.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)#3                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)#3.itm                                                                     0.0000  4.2869  
+        sobel:core/conc#1098                                                                                             0.0000  4.2869  
+        sobel:core/conc#1098.itm                                                                                         0.0000  4.2869  
+        sobel:core/ACC1:acc#357                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#357.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#34                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#34.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#223                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#223.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva)                                                                           0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva).itm                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#299                    mgc_not_2                                                           0.0000  5.2670  
+        sobel:core/ACC1-1:not#299.itm                                                                                    0.0000  5.2670  
+        sobel:core/conc#1090                                                                                             0.0000  5.2670  
+        sobel:core/conc#1090.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#358                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#358.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#35                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#38.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#2                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#2.itm                                                                            0.0000  5.7029  
+        sobel:core/conc#1089                                                                                             0.0000  5.7029  
+        sobel:core/conc#1089.itm                                                                                         0.0000  5.7029  
+        sobel:core/ACC1:acc#359                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#359.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#36                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#40.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2                                                                                0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2.itm                                                                            0.0000  6.1389  
+        sobel:core/ACC1-1:nand#4                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#4.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#1445                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1445.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1485                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1485.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#696                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#696.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#160                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#160.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#702                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#702.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#706                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#706.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#709                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#709.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#712                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#712.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#714                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#714.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#716                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#716.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#27                     mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#27.itm                                                                                     0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      3                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]:not               mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]:not.itm                                                                               0.0000  0.0000  
+        sobel:core/ACC1:acc#331                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#331.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc                        mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                         0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3                                                                                  0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3.itm                                                                              0.0000  2.3449  
+        sobel:core/conc#1010                                                                                             0.0000  2.3449  
+        sobel:core/conc#1010.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#333                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#333.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#14                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#14.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1009                                                                                             0.0000  2.9974  
+        sobel:core/conc#1009.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#335                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#335.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#16                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#16.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#210                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#210.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4.itm                                                                     0.0000  4.2869  
+        sobel:core/conc#1086                                                                                             0.0000  4.2869  
+        sobel:core/conc#1086.itm                                                                                         0.0000  4.2869  
+        sobel:core/ACC1:acc#337                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#337.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#18                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#18.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#220                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#220.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1.itm                                                                     0.0000  5.2670  
+        sobel:core/conc#1005                                                                                             0.0000  5.2670  
+        sobel:core/conc#1005.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#338                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#338.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#19                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#26.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/conc#1099                                                                                             0.0000  5.7029  
+        sobel:core/conc#1099.itm                                                                                         0.0000  5.7029  
+        sobel:core/ACC1:acc#339                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#339.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#20                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#32.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva)                                                                                  0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva).itm                                                                              0.0000  6.1389  
+        sobel:core/ACC1-1:nand#1                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#1.cse.sva                                                                                 0.0000  6.4067  
+        sobel:core/ACC1:conc#1430                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1430.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1474                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1474.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#670                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#670.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#153                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#153.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#676                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#676.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#680                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#680.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#683                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#683.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#686                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#686.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#688                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#688.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#690                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#690.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#2                      mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#2.itm                                                                                      0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      4                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#8)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#8).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#1:not             mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]#1:not.itm                                                                             0.0000  0.0000  
+        sobel:core/ACC1:acc#331                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#331.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc                        mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                         0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3                                                                                  0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3.itm                                                                              0.0000  2.3449  
+        sobel:core/conc#1010                                                                                             0.0000  2.3449  
+        sobel:core/conc#1010.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#333                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#333.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#14                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#14.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1009                                                                                             0.0000  2.9974  
+        sobel:core/conc#1009.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#335                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#335.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#16                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#16.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#210                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#210.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4.itm                                                                     0.0000  4.2869  
+        sobel:core/conc#1086                                                                                             0.0000  4.2869  
+        sobel:core/conc#1086.itm                                                                                         0.0000  4.2869  
+        sobel:core/ACC1:acc#337                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#337.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#18                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#18.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#220                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#220.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1.itm                                                                     0.0000  5.2670  
+        sobel:core/conc#1005                                                                                             0.0000  5.2670  
+        sobel:core/conc#1005.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#338                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#338.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#19                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#26.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/conc#1099                                                                                             0.0000  5.7029  
+        sobel:core/conc#1099.itm                                                                                         0.0000  5.7029  
+        sobel:core/ACC1:acc#339                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#339.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#20                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#32.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva)                                                                                  0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva).itm                                                                              0.0000  6.1389  
+        sobel:core/ACC1-1:nand#1                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#1.cse.sva                                                                                 0.0000  6.4067  
+        sobel:core/ACC1:conc#1430                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1430.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1474                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1474.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#670                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#670.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#153                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#153.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#676                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#676.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#680                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#680.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#683                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#683.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#686                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#686.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#688                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#688.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#690                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#690.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#2                      mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#2.itm                                                                                      0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      5                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not            mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not.itm                                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#351                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#351.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc#20                     mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc#20.psp#2.sva                                                                                      0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17                                                                              0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17.itm                                                                          0.0000  2.3449  
+        sobel:core/conc#1096                                                                                             0.0000  2.3449  
+        sobel:core/conc#1096.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#353                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#353.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#30                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#30.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1095                                                                                             0.0000  2.9974  
+        sobel:core/conc#1095.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#355                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#355.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#32                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#32.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#217                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#217.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)#3                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)#3.itm                                                                     0.0000  4.2869  
+        sobel:core/conc#1098                                                                                             0.0000  4.2869  
+        sobel:core/conc#1098.itm                                                                                         0.0000  4.2869  
+        sobel:core/ACC1:acc#357                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#357.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#34                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#34.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#223                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#223.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva)                                                                           0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva).itm                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#299                    mgc_not_2                                                           0.0000  5.2670  
+        sobel:core/ACC1-1:not#299.itm                                                                                    0.0000  5.2670  
+        sobel:core/conc#1090                                                                                             0.0000  5.2670  
+        sobel:core/conc#1090.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#358                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#358.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#35                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#38.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/ACC1-1:not#153                    mgc_not_1                                                           0.0000  5.7029  
+        sobel:core/ACC1-1:not#153.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:conc#1180                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:conc#1180.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:acc#359                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#359.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#36                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#40.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2                                                                                0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2.itm                                                                            0.0000  6.1389  
+        sobel:core/ACC1-1:nand#4                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#4.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#1445                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1445.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1485                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1485.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#696                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#696.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#160                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#160.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#702                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#702.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#706                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#706.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#709                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#709.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#712                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#712.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#714                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#714.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#716                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#716.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#27                     mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#27.itm                                                                                     0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      6                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not            mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not.itm                                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#351                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#351.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc#20                     mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc#20.psp#2.sva                                                                                      0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17                                                                              0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17.itm                                                                          0.0000  2.3449  
+        sobel:core/conc#1096                                                                                             0.0000  2.3449  
+        sobel:core/conc#1096.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#353                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#353.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#30                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#30.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1095                                                                                             0.0000  2.9974  
+        sobel:core/conc#1095.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#355                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#355.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#32                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#32.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#217                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#217.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)#4                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)#4.itm                                                                     0.0000  4.2869  
+        sobel:core/ACC1-1:not#287                    mgc_not_1                                                           0.0000  4.2869  
+        sobel:core/ACC1-1:not#287.itm                                                                                    0.0000  4.2869  
+        sobel:core/ACC1:conc#1175                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:conc#1175.itm                                                                                    0.0000  4.2869  
+        sobel:core/ACC1:acc#357                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#357.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#34                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#34.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#223                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#223.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva)                                                                           0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva).itm                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#299                    mgc_not_2                                                           0.0000  5.2670  
+        sobel:core/ACC1-1:not#299.itm                                                                                    0.0000  5.2670  
+        sobel:core/conc#1090                                                                                             0.0000  5.2670  
+        sobel:core/conc#1090.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#358                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#358.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#35                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#38.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/ACC1-1:not#153                    mgc_not_1                                                           0.0000  5.7029  
+        sobel:core/ACC1-1:not#153.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:conc#1180                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:conc#1180.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:acc#359                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#359.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#36                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#40.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2                                                                                0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2.itm                                                                            0.0000  6.1389  
+        sobel:core/ACC1-1:nand#4                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#4.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#1445                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1445.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1485                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1485.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#696                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#696.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#160                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#160.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#702                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#702.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#706                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#706.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#709                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#709.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#712                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#712.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#714                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#714.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#716                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#716.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#27                     mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#27.itm                                                                                     0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      7                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]:not               mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]:not.itm                                                                               0.0000  0.0000  
+        sobel:core/ACC1:acc#331                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#331.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc                        mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                         0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3                                                                                  0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3.itm                                                                              0.0000  2.3449  
+        sobel:core/conc#1010                                                                                             0.0000  2.3449  
+        sobel:core/conc#1010.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#333                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#333.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#14                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#14.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1009                                                                                             0.0000  2.9974  
+        sobel:core/conc#1009.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#335                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#335.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#16                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#16.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#210                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#210.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#5                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#5.itm                                                                     0.0000  4.2869  
+        sobel:core/ACC1-1:not#273                    mgc_not_1                                                           0.0000  4.2869  
+        sobel:core/ACC1-1:not#273.itm                                                                                    0.0000  4.2869  
+        sobel:core/ACC1:conc#1139                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:conc#1139.itm                                                                                    0.0000  4.2869  
+        sobel:core/ACC1:acc#337                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#337.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#18                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#18.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#220                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#220.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1.itm                                                                     0.0000  5.2670  
+        sobel:core/conc#1005                                                                                             0.0000  5.2670  
+        sobel:core/conc#1005.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#338                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#338.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#19                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#26.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/conc#1099                                                                                             0.0000  5.7029  
+        sobel:core/conc#1099.itm                                                                                         0.0000  5.7029  
+        sobel:core/ACC1:acc#339                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#339.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#20                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#32.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva)                                                                                  0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva).itm                                                                              0.0000  6.1389  
+        sobel:core/ACC1-1:nand#1                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#1.cse.sva                                                                                 0.0000  6.4067  
+        sobel:core/ACC1:conc#1430                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1430.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1474                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1474.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#670                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#670.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#153                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#153.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#676                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#676.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#680                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#680.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#683                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#683.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#686                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#686.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#688                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#688.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#690                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#690.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#2                      mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#2.itm                                                                                      0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      8                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not            mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]#12:not.itm                                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#351                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#351.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc#20                     mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc#20.psp#2.sva                                                                                      0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17                                                                              0.0000  2.3449  
+        sobel:core/slc(acc#20.psp#2.sva)#17.itm                                                                          0.0000  2.3449  
+        sobel:core/conc#1096                                                                                             0.0000  2.3449  
+        sobel:core/conc#1096.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#353                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#353.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#30                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#30.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1095                                                                                             0.0000  2.9974  
+        sobel:core/conc#1095.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#355                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#355.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#32                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#32.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#217                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#217.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva)                                                                           0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#217.psp#2.sva).itm                                                                       0.0000  4.2869  
+        sobel:core/ACC1:conc#1175                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:conc#1175.itm                                                                                    0.0000  4.2869  
+        sobel:core/ACC1:acc#357                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#357.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#34                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#34.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#223                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#223.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva)                                                                           0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#223.psp#1.sva).itm                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#299                    mgc_not_2                                                           0.0000  5.2670  
+        sobel:core/ACC1-1:not#299.itm                                                                                    0.0000  5.2670  
+        sobel:core/conc#1090                                                                                             0.0000  5.2670  
+        sobel:core/conc#1090.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#358                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#358.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#35                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#38.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#38.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/ACC1-1:not#153                    mgc_not_1                                                           0.0000  5.7029  
+        sobel:core/ACC1-1:not#153.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:conc#1180                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:conc#1180.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:acc#359                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#359.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#36                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#40.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2                                                                                0.0000  6.1389  
+        sobel:core/slc(acc.imod#40.sva)#2.itm                                                                            0.0000  6.1389  
+        sobel:core/ACC1-1:nand#4                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#4.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#1445                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1445.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1485                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1485.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#696                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#696.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#160                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#160.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#702                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#702.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#706                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#706.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#709                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#709.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#712                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#712.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#714                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#714.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#716                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#716.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#27                     mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#27.itm                                                                                     0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      9                                              sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]:not               mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]:not.itm                                                                               0.0000  0.0000  
+        sobel:core/ACC1:acc#331                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#331.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc                        mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                         0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3                                                                                  0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3.itm                                                                              0.0000  2.3449  
+        sobel:core/conc#1010                                                                                             0.0000  2.3449  
+        sobel:core/conc#1010.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#333                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#333.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#14                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#14.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1009                                                                                             0.0000  2.9974  
+        sobel:core/conc#1009.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#335                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#335.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#16                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#16.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#210                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#210.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#1                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#1.itm                                                                     0.0000  4.2869  
+        sobel:core/ACC1:conc#1139                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:conc#1139.itm                                                                                    0.0000  4.2869  
+        sobel:core/ACC1:acc#337                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#337.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#18                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#18.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#220                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#220.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)#1.itm                                                                     0.0000  5.2670  
+        sobel:core/conc#1005                                                                                             0.0000  5.2670  
+        sobel:core/conc#1005.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#338                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#338.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#19                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#26.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#3.itm                                                                            0.0000  5.7029  
+        sobel:core/conc#1099                                                                                             0.0000  5.7029  
+        sobel:core/conc#1099.itm                                                                                         0.0000  5.7029  
+        sobel:core/ACC1:acc#339                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#339.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#20                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#32.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva)                                                                                  0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva).itm                                                                              0.0000  6.1389  
+        sobel:core/ACC1-1:nand#1                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#1.cse.sva                                                                                 0.0000  6.4067  
+        sobel:core/ACC1:conc#1430                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1430.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1474                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1474.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#670                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#670.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#153                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#153.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#676                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#676.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#680                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#680.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#683                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#683.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#686                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#686.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#688                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#688.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#690                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#690.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#2                      mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#2.itm                                                                                      0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      10                                             sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(ACC1:acc#659.itm#1) 15.8798 4.1202  
+                                                                                                                                         
+        Instance                                     Component                                                           Delta   Delay   
+        --------                                     ---------                                                           -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]:not               mgc_not_10                                                          0.0000  0.0000  
+        sobel:core/regs.operator[]:not.itm                                                                               0.0000  0.0000  
+        sobel:core/ACC1:acc#331                      mgc_add_10_1_10_1_11                                                1.1389  1.1389  
+        sobel:core/ACC1:acc#331.itm                                                                                      0.0000  1.1389  
+        sobel:core/ACC1-1:acc                        mgc_add_11_1_11_1_12                                                1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                         0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3                                                                                  0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#3.itm                                                                              0.0000  2.3449  
+        sobel:core/conc#1010                                                                                             0.0000  2.3449  
+        sobel:core/conc#1010.itm                                                                                         0.0000  2.3449  
+        sobel:core/ACC1:acc#333                      mgc_add_2_0_2_0_3                                                   0.6525  2.9974  
+        sobel:core/ACC1:acc#333.itm                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:slc#14                                                                                           0.0000  2.9974  
+        sobel:core/ACC1:slc#14.itm                                                                                       0.0000  2.9974  
+        sobel:core/conc#1009                                                                                             0.0000  2.9974  
+        sobel:core/conc#1009.itm                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:acc#335                      mgc_add_3_0_3_0_4                                                   0.7609  3.7583  
+        sobel:core/ACC1:acc#335.itm                                                                                      0.0000  3.7583  
+        sobel:core/ACC1:slc#16                                                                                           0.0000  3.7583  
+        sobel:core/ACC1:slc#16.itm                                                                                       0.0000  3.7583  
+        sobel:core/ACC1-1:acc#210                    mgc_add_4_0_4_1_6                                                   0.5286  4.2869  
+        sobel:core/ACC1:acc#210.psp#2.sva                                                                                0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4                                                                         0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#210.psp#2.sva)#4.itm                                                                     0.0000  4.2869  
+        sobel:core/conc#1086                                                                                             0.0000  4.2869  
+        sobel:core/conc#1086.itm                                                                                         0.0000  4.2869  
+        sobel:core/ACC1:acc#337                      mgc_add_2_0_2_0_3                                                   0.6525  4.9394  
+        sobel:core/ACC1:acc#337.itm                                                                                      0.0000  4.9394  
+        sobel:core/ACC1:slc#18                                                                                           0.0000  4.9394  
+        sobel:core/ACC1:slc#18.itm                                                                                       0.0000  4.9394  
+        sobel:core/ACC1-1:acc#220                    mgc_add_2_0_2_1_4                                                   0.3276  5.2670  
+        sobel:core/ACC1:acc#220.psp#1.sva                                                                                0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva)                                                                           0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#220.psp#1.sva).itm                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#293                    mgc_not_2                                                           0.0000  5.2670  
+        sobel:core/ACC1-1:not#293.itm                                                                                    0.0000  5.2670  
+        sobel:core/conc#1004                                                                                             0.0000  5.2670  
+        sobel:core/conc#1004.itm                                                                                         0.0000  5.2670  
+        sobel:core/ACC1:acc#338                      mgc_add_3_0_3_1_5                                                   0.4359  5.7029  
+        sobel:core/ACC1:acc#338.itm                                                                                      0.0000  5.7029  
+        sobel:core/ACC1:slc#19                                                                                           0.0000  5.7029  
+        sobel:core/acc.imod#26.sva                                                                                       0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#4                                                                                0.0000  5.7029  
+        sobel:core/slc(acc.imod#26.sva)#4.itm                                                                            0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                     mgc_not_1                                                           0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                     0.0000  5.7029  
+        sobel:core/ACC1:conc#1144                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:conc#1144.itm                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:acc#339                      mgc_add_3_0_3_1_5                                                   0.4359  6.1389  
+        sobel:core/ACC1:acc#339.itm                                                                                      0.0000  6.1389  
+        sobel:core/ACC1:slc#20                                                                                           0.0000  6.1389  
+        sobel:core/acc.imod#32.sva                                                                                       0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva)                                                                                  0.0000  6.1389  
+        sobel:core/slc(acc.imod#32.sva).itm                                                                              0.0000  6.1389  
+        sobel:core/ACC1-1:nand#1                     mgc_nand_1_2                                                        0.2679  6.4067  
+        sobel:core/ACC1-1:nand#1.cse.sva                                                                                 0.0000  6.4067  
+        sobel:core/ACC1:conc#1430                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:conc#1430.itm                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:exs#1474                                                                                         0.0000  6.4067  
+        sobel:core/ACC1:exs#1474.itm                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:acc#670                      mgc_add_3_0_3_0_4                                                   0.7609  7.1676  
+        sobel:core/ACC1:acc#670.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:slc#153                                                                                          0.0000  7.1676  
+        sobel:core/ACC1:slc#153.itm                                                                                      0.0000  7.1676  
+        sobel:core/ACC1:acc#676                      mgc_add_3_0_3_0_4                                                   0.7609  7.9285  
+        sobel:core/ACC1:acc#676.itm                                                                                      0.0000  7.9285  
+        sobel:core/ACC1:acc#680                      mgc_add_4_0_4_0_5                                                   0.8536  8.7821  
+        sobel:core/ACC1:acc#680.itm                                                                                      0.0000  8.7821  
+        sobel:core/ACC1:acc#683                      mgc_add_6_0_6_1_8                                                   0.6912  9.4733  
+        sobel:core/ACC1:acc#683.itm                                                                                      0.0000  9.4733  
+        sobel:core/ACC1:acc#686                      mgc_add_8_0_8_1_10                                                  0.8382  10.3115 
+        sobel:core/ACC1:acc#686.itm                                                                                      0.0000  10.3115 
+        sobel:core/ACC1:acc#688                      mgc_add_9_0_9_1_11                                                  0.9081  11.2196 
+        sobel:core/ACC1:acc#688.itm                                                                                      0.0000  11.2196 
+        sobel:core/ACC1:acc#690                      mgc_add_10_0_10_1_12                                                0.9765  12.1961 
+        sobel:core/ACC1:acc#690.itm                                                                                      0.0000  12.1961 
+        sobel:core/ACC1-1:acc#2                      mgc_add_11_1_11_1_12                                                1.2059  13.4020 
+        sobel:core/ACC1-1:acc#2.itm                                                                                      0.0000  13.4020 
+        sobel:core/ACC1:acc#653                      mgc_add_11_1_11_1_12                                                1.2059  14.6079 
+        sobel:core/ACC1:acc#653.itm                                                                                      0.0000  14.6079 
+        sobel:core/ACC1:acc#659                      mgc_add_12_1_12_1_13                                                1.2718  15.8798 
+        sobel:core/ACC1:acc#659.itm                                                                                      0.0000  15.8798 
+        sobel:core/reg(ACC1:acc#659.itm#1)           mgc_reg_pos_13_1_0_0_0_1_1                                          0.0000  15.8798 
+                                                                                                                                         
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                            Port                               Slack (Delay) Messages 
+      --------------------------------------------------- -------------------------------- ------- ------- --------
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)           mux.itm                           4.6050 15.3950          
+      sobel:core/reg(ACC1:acc#659.itm#1)                  ACC1:acc#659.itm                  4.1202 15.8798          
+      sobel:core/reg(ACC1:acc#658.itm#1)                  ACC1:acc#658.itm                  6.6969 13.3031          
+      sobel:core/reg(ACC1:acc#661.itm#1)                  ACC1:acc#661.itm                 11.0359  8.9641          
+      sobel:core/reg(ACC1:mul#57.itm#1.sg2)               slc(ACC1:mul#57.itm)#2.itm       13.6498  6.3502          
+      sobel:core/reg(ACC1:mul#57.itm#2)                   slc(ACC1:mul#57.itm)#3.itm       13.6498  6.3502          
+      sobel:core/reg(slc(acc#20.psp#1)#93.itm#1)          slc(acc#20.psp#1.sva)#12.itm     17.6551  2.3449          
+      sobel:core/reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1) slc(ACC1:acc#228.psp.sva)#14.itm 17.6551  2.3449          
+      sobel:core/reg(ACC1-3:slc(acc#10.psp)#62.itm#1)     slc(ACC1:acc#224.psp.sva)#16.itm 17.6551  2.3449          
+      sobel:core/reg(ACC1:acc#652.itm#1)                  ACC1:acc#652.itm                  4.3273 15.6727          
+      sobel:core/reg(ACC1:acc#655.itm#1)                  ACC1:acc#655.itm                  5.0044 14.9956          
+      sobel:core/reg(main.stage_0#2)                      C0_10#10_Not                     20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#10.itm)  slc(regs.regs(1).sva)#2.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#11.itm)  slc(regs.regs(1).sva)#1.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#9.itm)   slc(regs.regs(1).sva).itm        20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#4.itm)   slc(regs.regs(1).sva)#5.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#5.itm)   slc(regs.regs(1).sva)#4.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#3.itm)   slc(regs.regs(1).sva)#3.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2)).itm)     slc(regs.regs(1).sva)#8.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#1.itm)   slc(regs.regs(1).sva)#7.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#2.itm)   slc(regs.regs(1).sva)#6.itm      20.0000  0.0000          
+      sobel:core/reg(regs.regs(0).sva)                    vin:rsc:mgc_in_wire.d             4.1202 15.8798          
+      sobel                                               vout:rsc.z                       20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                   15     3 
+    -                   14     2 
+    -                   13     6 
+    -                   12    20 
+    -                   11    21 
+    -                   10     9 
+    -                    9    11 
+    -                    8    14 
+    -                    7    19 
+    -                    6    29 
+    -                    5    89 
+    -                    4   153 
+    -                    3    53 
+    -                    2    13 
+    and                          
+    -                    3    10 
+    mul                          
+    -                   14     1 
+    -                   13     2 
+    -                   12     1 
+    -                   10     2 
+    -                    9     1 
+    -                    8     2 
+    mux                          
+    -                    1     1 
+    nand                         
+    -                    2    10 
+    not                          
+    -                   10    15 
+    -                    3     4 
+    -                    2    14 
+    -                    1   141 
+    or                           
+    -                    2     2 
+    read_port                    
+    -                   90     1 
+    reg                          
+    -                   90     1 
+    -                   30     1 
+    -                   14     1 
+    -                   13     2 
+    -                   12     1 
+    -                   11     1 
+    -                   10     9 
+    -                    5     1 
+    -                    2     1 
+    -                    1     4 
+    write_port                   
+    -                   30     1 
+    
+  End of Report
diff --git a/Sobel/sobel.v12/rtl.v b/Sobel/sobel.v12/rtl.v
new file mode 100644
index 0000000..261a927
--- /dev/null
+++ b/Sobel/sobel.v12/rtl.v
@@ -0,0 +1,1609 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 16:19:43 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] regs_regs_slc_regs_regs_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_1_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_4_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_5_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_3_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_10_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_11_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_9_itm;
+  reg [12:0] ACC1_acc_659_itm_1;
+  wire [14:0] nl_ACC1_acc_659_itm_1;
+  reg [12:0] ACC1_acc_658_itm_1;
+  wire [13:0] nl_ACC1_acc_658_itm_1;
+  reg [13:0] ACC1_acc_661_itm_1;
+  wire [14:0] nl_ACC1_acc_661_itm_1;
+  reg slc_acc_20_psp_1_93_itm_1;
+  reg ACC1_slc_ACC1_acc_228_psp_55_itm_1;
+  reg ACC1_3_slc_acc_10_psp_62_itm_1;
+  reg [10:0] ACC1_acc_652_itm_1;
+  wire [11:0] nl_ACC1_acc_652_itm_1;
+  reg [11:0] ACC1_acc_655_itm_1;
+  wire [12:0] nl_ACC1_acc_655_itm_1;
+  reg main_stage_0_2;
+  reg [4:0] ACC1_mul_57_itm_1_sg2;
+  reg [1:0] ACC1_mul_57_itm_2;
+  reg [89:0] reg_regs_regs_0_sva_cse;
+  wire [11:0] FRAME_acc_2_psp_sva;
+  wire [13:0] nl_FRAME_acc_2_psp_sva;
+  wire [5:0] acc_imod_24_sva;
+  wire [7:0] nl_acc_imod_24_sva;
+  wire [11:0] acc_20_psp_1_sva;
+  wire [12:0] nl_acc_20_psp_1_sva;
+  wire [11:0] ACC1_acc_228_psp_sva;
+  wire [12:0] nl_ACC1_acc_228_psp_sva;
+  wire [11:0] ACC1_1_acc_25_psp_sva;
+  wire [12:0] nl_ACC1_1_acc_25_psp_sva;
+  wire [2:0] ACC1_acc_509_cse;
+  wire [3:0] nl_ACC1_acc_509_cse;
+  wire [11:0] ACC1_acc_227_psp_sva;
+  wire [12:0] nl_ACC1_acc_227_psp_sva;
+  wire [2:0] ACC1_acc_506_cse;
+  wire [3:0] nl_ACC1_acc_506_cse;
+  wire [3:0] ACC1_acc_562_ncse;
+  wire [4:0] nl_ACC1_acc_562_ncse;
+  wire [2:0] ACC1_acc_502_cse;
+  wire [3:0] nl_ACC1_acc_502_cse;
+  wire [2:0] ACC1_acc_489_cse;
+  wire [3:0] nl_ACC1_acc_489_cse;
+  wire [11:0] ACC1_acc_226_psp_sva;
+  wire [12:0] nl_ACC1_acc_226_psp_sva;
+  wire [3:0] ACC1_acc_553_ncse;
+  wire [4:0] nl_ACC1_acc_553_ncse;
+  wire ACC1_1_and_3_cse_sva;
+  wire ACC1_1_nand_1_cse_sva;
+  wire [11:0] acc_psp_1_sva;
+  wire [12:0] nl_acc_psp_1_sva;
+  wire [3:0] ACC1_acc_210_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_210_psp_2_sva;
+  wire [11:0] acc_psp_2_sva;
+  wire [12:0] nl_acc_psp_2_sva;
+  wire [11:0] ACC1_acc_224_psp_1_sva;
+  wire [12:0] nl_ACC1_acc_224_psp_1_sva;
+  wire [3:0] ACC1_1_acc_208_psp_sva;
+  wire [4:0] nl_ACC1_1_acc_208_psp_sva;
+  wire [11:0] ACC1_acc_224_psp_sva;
+  wire [12:0] nl_ACC1_acc_224_psp_sva;
+  wire [2:0] ACC1_acc_516_cse;
+  wire [3:0] nl_ACC1_acc_516_cse;
+  wire [3:0] ACC1_3_acc_212_psp_sva;
+  wire [4:0] nl_ACC1_3_acc_212_psp_sva;
+  wire [2:0] ACC1_acc_221_psp_sva;
+  wire [3:0] nl_ACC1_acc_221_psp_sva;
+  wire [2:0] ACC1_acc_221_psp_2_sva;
+  wire [3:0] nl_ACC1_acc_221_psp_2_sva;
+  wire [2:0] ACC1_acc_219_psp_2_sva;
+  wire [3:0] nl_ACC1_acc_219_psp_2_sva;
+  wire [2:0] ACC1_acc_222_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_222_psp_1_sva;
+  wire [2:0] ACC1_acc_219_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_219_psp_1_sva;
+  wire [3:0] ACC1_acc_210_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_210_psp_1_sva;
+  wire [3:0] ACC1_acc_217_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_217_psp_1_sva;
+  wire [2:0] ACC1_acc_724_cse;
+  wire [3:0] nl_ACC1_acc_724_cse;
+  wire [13:0] ACC1_mul_57_itm;
+  wire [27:0] nl_ACC1_mul_57_itm;
+  wire [2:0] ACC1_acc_223_psp_sva;
+  wire [3:0] nl_ACC1_acc_223_psp_sva;
+  wire [2:0] ACC1_acc_220_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_220_psp_1_sva;
+  wire [2:0] ACC1_acc_220_psp_sva;
+  wire [3:0] nl_ACC1_acc_220_psp_sva;
+  wire [2:0] ACC1_acc_222_psp_sva;
+  wire [3:0] nl_ACC1_acc_222_psp_sva;
+  wire [2:0] ACC1_acc_673_cse;
+  wire [3:0] nl_ACC1_acc_673_cse;
+  wire [11:0] acc_20_psp_2_sva;
+  wire [12:0] nl_acc_20_psp_2_sva;
+  wire [3:0] ACC1_acc_217_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_217_psp_2_sva;
+  wire [2:0] ACC1_acc_223_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_223_psp_1_sva;
+  wire [2:0] ACC1_acc_699_cse;
+  wire [3:0] nl_ACC1_acc_699_cse;
+  wire [14:0] ACC1_acc_itm;
+  wire [16:0] nl_ACC1_acc_itm;
+  wire [3:0] ACC1_acc_338_itm;
+  wire [4:0] nl_ACC1_acc_338_itm;
+  wire [2:0] ACC1_acc_406_itm;
+  wire [3:0] nl_ACC1_acc_406_itm;
+  wire [2:0] ACC1_acc_368_itm;
+  wire [3:0] nl_ACC1_acc_368_itm;
+  wire [3:0] ACC1_acc_367_itm;
+  wire [4:0] nl_ACC1_acc_367_itm;
+  wire [2:0] ACC1_acc_349_itm;
+  wire [3:0] nl_ACC1_acc_349_itm;
+  wire [3:0] ACC1_acc_348_itm;
+  wire [4:0] nl_ACC1_acc_348_itm;
+  wire [4:0] ACC1_acc_412_itm;
+  wire [5:0] nl_ACC1_acc_412_itm;
+  wire [3:0] ACC1_acc_423_itm;
+  wire [4:0] nl_ACC1_acc_423_itm;
+  wire [4:0] ACC1_acc_375_itm;
+  wire [5:0] nl_ACC1_acc_375_itm;
+  wire [3:0] ACC1_acc_395_itm;
+  wire [4:0] nl_ACC1_acc_395_itm;
+  wire [4:0] ACC1_acc_384_itm;
+  wire [5:0] nl_ACC1_acc_384_itm;
+  wire [3:0] ACC1_acc_414_itm;
+  wire [4:0] nl_ACC1_acc_414_itm;
+  wire [3:0] ACC1_acc_377_itm;
+  wire [4:0] nl_ACC1_acc_377_itm;
+  wire [4:0] ACC1_acc_346_itm;
+  wire [5:0] nl_ACC1_acc_346_itm;
+  wire [3:0] ACC1_acc_386_itm;
+  wire [4:0] nl_ACC1_acc_386_itm;
+  wire [3:0] ACC1_acc_405_itm;
+  wire [4:0] nl_ACC1_acc_405_itm;
+  wire [2:0] ACC1_acc_387_itm;
+  wire [3:0] nl_ACC1_acc_387_itm;
+  wire [2:0] ACC1_acc_378_itm;
+  wire [3:0] nl_ACC1_acc_378_itm;
+  wire [2:0] ACC1_acc_415_itm;
+  wire [3:0] nl_ACC1_acc_415_itm;
+  wire [2:0] ACC1_acc_396_itm;
+  wire [3:0] nl_ACC1_acc_396_itm;
+  wire [2:0] ACC1_acc_424_itm;
+  wire [3:0] nl_ACC1_acc_424_itm;
+  wire [2:0] ACC1_acc_359_itm;
+  wire [3:0] nl_ACC1_acc_359_itm;
+  wire [3:0] ACC1_acc_358_itm;
+  wire [4:0] nl_ACC1_acc_358_itm;
+  wire [2:0] ACC1_acc_339_itm;
+  wire [3:0] nl_ACC1_acc_339_itm;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_2_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(ACC1_acc_itm[14:13])
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_itm[12:10])
+      * 9'b111001)) + conv_s2s_7_10(conv_u2s_6_7(ACC1_acc_itm[9:4]) + conv_s2s_5_7(({4'b1001
+      , (acc_imod_24_sva[5])}) + conv_u2s_4_5((conv_u2u_3_4({(~ (acc_imod_24_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_24_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_24_sva[5:3])) , (~ (acc_imod_24_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_24_sva[4:3]))
+      + conv_u2u_3_4(~ (ACC1_acc_itm[9:7]))))))) + conv_u2u_11_12(signext_11_9({(ACC1_acc_itm[14])
+      , 3'b0 , (signext_3_1(ACC1_acc_itm[14])) , 1'b0 , (ACC1_acc_itm[14])}));
+  assign FRAME_acc_2_psp_sva = nl_FRAME_acc_2_psp_sva[11:0];
+  assign nl_ACC1_acc_itm = (conv_s2s_14_15(conv_s2s_13_14(ACC1_acc_659_itm_1) + conv_s2s_13_14(ACC1_acc_658_itm_1))
+      + conv_s2s_14_15(ACC1_acc_661_itm_1)) + conv_s2s_14_15(({ACC1_mul_57_itm_1_sg2
+      , 7'b0 , ACC1_mul_57_itm_2}) + conv_s2s_13_14(conv_s2s_12_13(({slc_acc_20_psp_1_93_itm_1
+      , 2'b0 , slc_acc_20_psp_1_93_itm_1 , 1'b0 , slc_acc_20_psp_1_93_itm_1 , 1'b0
+      , slc_acc_20_psp_1_93_itm_1 , ACC1_slc_ACC1_acc_228_psp_55_itm_1 , 1'b0 , ({{1{ACC1_3_slc_acc_10_psp_62_itm_1}},
+      ACC1_3_slc_acc_10_psp_62_itm_1})}) + conv_u2s_11_12(ACC1_acc_652_itm_1)) +
+      conv_s2s_12_13(ACC1_acc_655_itm_1)));
+  assign ACC1_acc_itm = nl_ACC1_acc_itm[14:0];
+  assign nl_acc_imod_24_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~ (ACC1_acc_itm[14]))
+      , 1'b1 , (~ (ACC1_acc_itm[14]))}) + conv_u2u_2_4(ACC1_acc_itm[14:13]))) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_itm[3:1])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[6:4])))) + 6'b101011;
+  assign acc_imod_24_sva = nl_acc_imod_24_sva[5:0];
+  assign nl_acc_20_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_10_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_11_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_9_itm);
+  assign acc_20_psp_1_sva = nl_acc_20_psp_1_sva[11:0];
+  assign nl_ACC1_acc_228_psp_sva = conv_s2u_11_12(conv_s2s_10_11(~ (reg_regs_regs_0_sva_cse[9:0]))
+      + conv_s2s_10_11(~ (reg_regs_regs_0_sva_cse[19:10]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (reg_regs_regs_0_sva_cse[29:20])) + 11'b11);
+  assign ACC1_acc_228_psp_sva = nl_ACC1_acc_228_psp_sva[11:0];
+  assign nl_ACC1_1_acc_25_psp_sva = conv_s2s_11_12(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[79:70])
+      + conv_s2s_10_11(vin_rsc_mgc_in_wire_d[69:60])) + conv_s2s_10_12(vin_rsc_mgc_in_wire_d[89:80]);
+  assign ACC1_1_acc_25_psp_sva = nl_ACC1_1_acc_25_psp_sva[11:0];
+  assign nl_ACC1_acc_509_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]));
+  assign ACC1_acc_509_cse = nl_ACC1_acc_509_cse[2:0];
+  assign nl_ACC1_acc_227_psp_sva = conv_s2s_11_12(conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_itm)
+      + conv_s2s_10_11(~ regs_regs_slc_regs_regs_2_1_itm)) + conv_s2s_11_12(conv_s2s_10_11(~
+      regs_regs_slc_regs_regs_2_2_itm) + 11'b11);
+  assign ACC1_acc_227_psp_sva = nl_ACC1_acc_227_psp_sva[11:0];
+  assign nl_ACC1_acc_506_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+  assign ACC1_acc_506_cse = nl_ACC1_acc_506_cse[2:0];
+  assign nl_ACC1_acc_562_ncse = conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(ACC1_acc_506_cse);
+  assign ACC1_acc_562_ncse = nl_ACC1_acc_562_ncse[3:0];
+  assign nl_ACC1_acc_502_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[5])) + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]));
+  assign ACC1_acc_502_cse = nl_ACC1_acc_502_cse[2:0];
+  assign nl_ACC1_acc_489_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]));
+  assign ACC1_acc_489_cse = nl_ACC1_acc_489_cse[2:0];
+  assign nl_ACC1_acc_226_psp_sva = conv_s2u_11_12(conv_s2s_10_11(reg_regs_regs_0_sva_cse[79:70])
+      + conv_s2s_10_11(reg_regs_regs_0_sva_cse[69:60])) + conv_s2u_10_12(reg_regs_regs_0_sva_cse[89:80]);
+  assign ACC1_acc_226_psp_sva = nl_ACC1_acc_226_psp_sva[11:0];
+  assign nl_ACC1_acc_553_ncse = conv_u2u_3_4(ACC1_acc_489_cse) + conv_u2u_3_4(ACC1_acc_489_cse);
+  assign ACC1_acc_553_ncse = nl_ACC1_acc_553_ncse[3:0];
+  assign ACC1_1_and_3_cse_sva = (acc_psp_2_sva[11]) & (~ (ACC1_acc_339_itm[2])) &
+      (ACC1_acc_339_itm[1]);
+  assign ACC1_1_nand_1_cse_sva = ~((ACC1_acc_339_itm[2]) & (~ (acc_psp_2_sva[11])));
+  assign nl_acc_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_1_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_2_itm)) + conv_s2s_10_12(regs_regs_slc_regs_regs_2_itm);
+  assign acc_psp_1_sva = nl_acc_psp_1_sva[11:0];
+  assign nl_ACC1_acc_338_itm = conv_s2s_3_4({(~ (ACC1_acc_220_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_220_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_338_itm = nl_ACC1_acc_338_itm[3:0];
+  assign nl_ACC1_acc_210_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_2_sva[1])) , (acc_psp_2_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_2_sva[0]) , (acc_psp_2_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[3])) , (~ (acc_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[5])) , (acc_psp_2_sva[6])})))) ,
+      (~ (acc_psp_2_sva[9]))}))));
+  assign ACC1_acc_210_psp_2_sva = nl_ACC1_acc_210_psp_2_sva[3:0];
+  assign nl_acc_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[29:20]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[19:10]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[9:0])) + 11'b11);
+  assign acc_psp_2_sva = nl_acc_psp_2_sva[11:0];
+  assign nl_ACC1_acc_224_psp_1_sva = conv_s2u_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[39:30]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[49:40]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[59:50])) + 11'b11);
+  assign ACC1_acc_224_psp_1_sva = nl_ACC1_acc_224_psp_1_sva[11:0];
+  assign nl_ACC1_acc_406_itm = ({1'b1 , (ACC1_acc_405_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_405_itm[2])) , (~ (ACC1_acc_405_itm[3]))});
+  assign ACC1_acc_406_itm = nl_ACC1_acc_406_itm[2:0];
+  assign nl_ACC1_acc_368_itm = ({1'b1 , (ACC1_acc_367_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_367_itm[2])) , (~ (ACC1_acc_367_itm[3]))});
+  assign ACC1_acc_368_itm = nl_ACC1_acc_368_itm[2:0];
+  assign nl_ACC1_acc_367_itm = conv_s2s_3_4({(~ (ACC1_acc_219_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_367_itm = nl_ACC1_acc_367_itm[3:0];
+  assign nl_ACC1_1_acc_208_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (ACC1_1_acc_25_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_1_acc_25_psp_sva[1]))
+      , (ACC1_1_acc_25_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (ACC1_1_acc_25_psp_sva[0])
+      , (ACC1_1_acc_25_psp_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[3])) , (~ (ACC1_1_acc_25_psp_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_25_psp_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_25_psp_sva[5])) , (ACC1_1_acc_25_psp_sva[6])}))))
+      , (~ (ACC1_1_acc_25_psp_sva[9]))}))));
+  assign ACC1_1_acc_208_psp_sva = nl_ACC1_1_acc_208_psp_sva[3:0];
+  assign nl_ACC1_acc_349_itm = ({1'b1 , (ACC1_acc_348_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_348_itm[2])) , (~ (ACC1_acc_348_itm[3]))});
+  assign ACC1_acc_349_itm = nl_ACC1_acc_349_itm[2:0];
+  assign nl_ACC1_acc_348_itm = conv_s2s_3_4({(~ (ACC1_acc_222_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_222_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_348_itm = nl_ACC1_acc_348_itm[3:0];
+  assign nl_ACC1_acc_224_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_slc_regs_regs_2_4_itm)
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_5_itm)) + conv_s2u_10_12(regs_regs_slc_regs_regs_2_3_itm);
+  assign ACC1_acc_224_psp_sva = nl_ACC1_acc_224_psp_sva[11:0];
+  assign nl_ACC1_acc_516_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]));
+  assign ACC1_acc_516_cse = nl_ACC1_acc_516_cse[2:0];
+  assign nl_ACC1_acc_412_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_224_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[2])) , (~ (ACC1_acc_224_psp_sva[6]))}))))
+      , (~ (ACC1_acc_224_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_sva[4])) , (ACC1_acc_224_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_sva[11:10])) , (ACC1_acc_224_psp_sva[7])}))))
+      , (ACC1_acc_224_psp_sva[9])});
+  assign ACC1_acc_412_itm = nl_ACC1_acc_412_itm[4:0];
+  assign nl_ACC1_acc_423_itm = conv_s2s_3_4({(~ (ACC1_acc_223_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_223_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_423_itm = nl_ACC1_acc_423_itm[3:0];
+  assign nl_ACC1_acc_375_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_228_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[2])) , (~ (ACC1_acc_228_psp_sva[6]))}))))
+      , (~ (ACC1_acc_228_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_228_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_228_psp_sva[4])) , (ACC1_acc_228_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_228_psp_sva[11:10])) , (ACC1_acc_228_psp_sva[7])}))))
+      , (ACC1_acc_228_psp_sva[9])});
+  assign ACC1_acc_375_itm = nl_ACC1_acc_375_itm[4:0];
+  assign nl_ACC1_acc_395_itm = conv_s2s_3_4({(~ (ACC1_acc_220_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_220_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_395_itm = nl_ACC1_acc_395_itm[3:0];
+  assign nl_ACC1_acc_384_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_226_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[2])) , (~ (ACC1_acc_226_psp_sva[6]))}))))
+      , (~ (ACC1_acc_226_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_226_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_226_psp_sva[4])) , (ACC1_acc_226_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_226_psp_sva[11:10])) , (ACC1_acc_226_psp_sva[7])}))))
+      , (ACC1_acc_226_psp_sva[9])});
+  assign ACC1_acc_384_itm = nl_ACC1_acc_384_itm[4:0];
+  assign nl_ACC1_3_acc_212_psp_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (ACC1_acc_227_psp_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (ACC1_acc_227_psp_sva[1]))
+      , (ACC1_acc_227_psp_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (ACC1_acc_227_psp_sva[0])
+      , (ACC1_acc_227_psp_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[3])) , (~ (ACC1_acc_227_psp_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_227_psp_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_227_psp_sva[5])) , (ACC1_acc_227_psp_sva[6])}))))
+      , (~ (ACC1_acc_227_psp_sva[9]))}))));
+  assign ACC1_3_acc_212_psp_sva = nl_ACC1_3_acc_212_psp_sva[3:0];
+  assign nl_ACC1_acc_414_itm = conv_s2s_3_4({(~ (ACC1_acc_222_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_222_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_414_itm = nl_ACC1_acc_414_itm[3:0];
+  assign nl_ACC1_acc_377_itm = conv_s2s_3_4({(~ (ACC1_acc_221_psp_2_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_221_psp_2_sva[0]) , 1'b1});
+  assign ACC1_acc_377_itm = nl_ACC1_acc_377_itm[3:0];
+  assign nl_ACC1_acc_346_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_224_psp_1_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[2])) , (~ (ACC1_acc_224_psp_1_sva[6]))}))))
+      , (~ (ACC1_acc_224_psp_1_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_224_psp_1_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_224_psp_1_sva[4])) , (ACC1_acc_224_psp_1_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_224_psp_1_sva[11:10])) , (ACC1_acc_224_psp_1_sva[7])}))))
+      , (ACC1_acc_224_psp_1_sva[9])});
+  assign ACC1_acc_346_itm = nl_ACC1_acc_346_itm[4:0];
+  assign nl_ACC1_acc_386_itm = conv_s2s_3_4({(~ (ACC1_acc_219_psp_2_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_219_psp_2_sva[0]) , 1'b1});
+  assign ACC1_acc_386_itm = nl_ACC1_acc_386_itm[3:0];
+  assign nl_ACC1_acc_405_itm = conv_s2s_3_4({(~ (ACC1_acc_221_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_221_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_405_itm = nl_ACC1_acc_405_itm[3:0];
+  assign nl_ACC1_acc_221_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_3_acc_212_psp_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_3_acc_212_psp_sva[1])) , (ACC1_3_acc_212_psp_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_3_acc_212_psp_sva[3]));
+  assign ACC1_acc_221_psp_sva = nl_ACC1_acc_221_psp_sva[2:0];
+  assign nl_ACC1_acc_221_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_375_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_375_itm[2])) , (ACC1_acc_375_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_375_itm[4]));
+  assign ACC1_acc_221_psp_2_sva = nl_ACC1_acc_221_psp_2_sva[2:0];
+  assign nl_ACC1_acc_219_psp_2_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_384_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_384_itm[2])) , (ACC1_acc_384_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_384_itm[4]));
+  assign ACC1_acc_219_psp_2_sva = nl_ACC1_acc_219_psp_2_sva[2:0];
+  assign nl_ACC1_acc_222_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_346_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_346_itm[2])) , (ACC1_acc_346_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_346_itm[4]));
+  assign ACC1_acc_222_psp_1_sva = nl_ACC1_acc_222_psp_1_sva[2:0];
+  assign nl_ACC1_acc_219_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_1_acc_208_psp_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_208_psp_sva[1])) , (ACC1_1_acc_208_psp_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_1_acc_208_psp_sva[3]));
+  assign ACC1_acc_219_psp_1_sva = nl_ACC1_acc_219_psp_1_sva[2:0];
+  assign nl_ACC1_acc_387_itm = ({1'b1 , (ACC1_acc_386_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_386_itm[2])) , (~ (ACC1_acc_386_itm[3]))});
+  assign ACC1_acc_387_itm = nl_ACC1_acc_387_itm[2:0];
+  assign nl_ACC1_acc_378_itm = ({1'b1 , (ACC1_acc_377_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_377_itm[2])) , (~ (ACC1_acc_377_itm[3]))});
+  assign ACC1_acc_378_itm = nl_ACC1_acc_378_itm[2:0];
+  assign nl_ACC1_acc_415_itm = ({1'b1 , (ACC1_acc_414_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_414_itm[2])) , (~ (ACC1_acc_414_itm[3]))});
+  assign ACC1_acc_415_itm = nl_ACC1_acc_415_itm[2:0];
+  assign nl_ACC1_acc_396_itm = ({1'b1 , (ACC1_acc_395_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_395_itm[2])) , (~ (ACC1_acc_395_itm[3]))});
+  assign ACC1_acc_396_itm = nl_ACC1_acc_396_itm[2:0];
+  assign nl_ACC1_acc_210_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_1_sva[1])) , (acc_psp_1_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_1_sva[0]) , (acc_psp_1_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[3])) , (~ (acc_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[5])) , (acc_psp_1_sva[6])})))) ,
+      (~ (acc_psp_1_sva[9]))}))));
+  assign ACC1_acc_210_psp_1_sva = nl_ACC1_acc_210_psp_1_sva[3:0];
+  assign nl_ACC1_acc_217_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_20_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_1_sva[1]))
+      , (acc_20_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_1_sva[0])
+      , (acc_20_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[3])) , (~ (acc_20_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_1_sva[5])) , (acc_20_psp_1_sva[6])}))))
+      , (~ (acc_20_psp_1_sva[9]))}))));
+  assign ACC1_acc_217_psp_1_sva = nl_ACC1_acc_217_psp_1_sva[3:0];
+  assign nl_ACC1_acc_424_itm = ({1'b1 , (ACC1_acc_423_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_423_itm[2])) , (~ (ACC1_acc_423_itm[3]))});
+  assign ACC1_acc_424_itm = nl_ACC1_acc_424_itm[2:0];
+  assign nl_ACC1_acc_724_cse = conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[11]));
+  assign ACC1_acc_724_cse = nl_ACC1_acc_724_cse[2:0];
+  assign nl_ACC1_mul_57_itm = conv_u2s_2_14((conv_u2u_1_2(ACC1_acc_224_psp_sva[11])
+      + conv_u2u_1_2(ACC1_acc_228_psp_sva[11])) + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[11]))
+      * 14'b11101000000001;
+  assign ACC1_mul_57_itm = nl_ACC1_mul_57_itm[13:0];
+  assign nl_ACC1_acc_223_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_1_sva[1])) , (ACC1_acc_217_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_217_psp_1_sva[3]));
+  assign ACC1_acc_223_psp_sva = nl_ACC1_acc_223_psp_sva[2:0];
+  assign nl_ACC1_acc_220_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_2_sva[1])) , (ACC1_acc_210_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_210_psp_2_sva[3]));
+  assign ACC1_acc_220_psp_1_sva = nl_ACC1_acc_220_psp_1_sva[2:0];
+  assign nl_ACC1_acc_220_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_210_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_210_psp_1_sva[1])) , (ACC1_acc_210_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_210_psp_1_sva[3]));
+  assign ACC1_acc_220_psp_sva = nl_ACC1_acc_220_psp_sva[2:0];
+  assign nl_ACC1_acc_222_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_412_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_412_itm[2])) , (ACC1_acc_412_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_412_itm[4]));
+  assign ACC1_acc_222_psp_sva = nl_ACC1_acc_222_psp_sva[2:0];
+  assign nl_ACC1_acc_673_cse = conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11]));
+  assign ACC1_acc_673_cse = nl_ACC1_acc_673_cse[2:0];
+  assign nl_acc_20_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[89:80]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[79:70]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[69:60])) + 11'b11);
+  assign acc_20_psp_2_sva = nl_acc_20_psp_2_sva[11:0];
+  assign nl_ACC1_acc_359_itm = ({1'b1 , (ACC1_acc_358_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_358_itm[2])) , (~ (ACC1_acc_358_itm[3]))});
+  assign ACC1_acc_359_itm = nl_ACC1_acc_359_itm[2:0];
+  assign nl_ACC1_acc_358_itm = conv_s2s_3_4({(~ (ACC1_acc_223_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_223_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_358_itm = nl_ACC1_acc_358_itm[3:0];
+  assign nl_ACC1_acc_217_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_20_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_20_psp_2_sva[1]))
+      , (acc_20_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_20_psp_2_sva[0])
+      , (acc_20_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[3])) , (~ (acc_20_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_20_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_20_psp_2_sva[5])) , (acc_20_psp_2_sva[6])}))))
+      , (~ (acc_20_psp_2_sva[9]))}))));
+  assign ACC1_acc_217_psp_2_sva = nl_ACC1_acc_217_psp_2_sva[3:0];
+  assign nl_ACC1_acc_223_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_217_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_217_psp_2_sva[1])) , (ACC1_acc_217_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_217_psp_2_sva[3]));
+  assign ACC1_acc_223_psp_1_sva = nl_ACC1_acc_223_psp_1_sva[2:0];
+  assign nl_ACC1_acc_699_cse = conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11]));
+  assign ACC1_acc_699_cse = nl_ACC1_acc_699_cse[2:0];
+  assign nl_ACC1_acc_339_itm = ({1'b1 , (ACC1_acc_338_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_338_itm[2])) , (~ (ACC1_acc_338_itm[3]))});
+  assign ACC1_acc_339_itm = nl_ACC1_acc_339_itm[2:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      ACC1_acc_659_itm_1 <= 13'b0;
+      ACC1_acc_658_itm_1 <= 13'b0;
+      ACC1_acc_661_itm_1 <= 14'b0;
+      ACC1_mul_57_itm_1_sg2 <= 5'b0;
+      ACC1_mul_57_itm_2 <= 2'b0;
+      slc_acc_20_psp_1_93_itm_1 <= 1'b0;
+      ACC1_slc_ACC1_acc_228_psp_55_itm_1 <= 1'b0;
+      ACC1_3_slc_acc_10_psp_62_itm_1 <= 1'b0;
+      ACC1_acc_652_itm_1 <= 11'b0;
+      ACC1_acc_655_itm_1 <= 12'b0;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_slc_regs_regs_2_10_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_11_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_9_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_4_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_5_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_3_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_1_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_2_itm <= 10'b0;
+      reg_regs_regs_0_sva_cse <= 90'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({vout_rsc_mgc_out_stdreg_d , ({((FRAME_acc_2_psp_sva[9:0])
+            | ({8'b0 , (FRAME_acc_2_psp_sva[11:10])})) , (FRAME_acc_2_psp_sva[9:6])
+            , ((FRAME_acc_2_psp_sva[5:0]) | ({4'b0 , (FRAME_acc_2_psp_sva[11:10])}))
+            , (FRAME_acc_2_psp_sva[9:0])})}, main_stage_0_2);
+        ACC1_acc_659_itm_1 <= nl_ACC1_acc_659_itm_1[12:0];
+        ACC1_acc_658_itm_1 <= nl_ACC1_acc_658_itm_1[12:0];
+        ACC1_acc_661_itm_1 <= nl_ACC1_acc_661_itm_1[13:0];
+        ACC1_mul_57_itm_1_sg2 <= ACC1_mul_57_itm[13:9];
+        ACC1_mul_57_itm_2 <= ACC1_mul_57_itm[1:0];
+        slc_acc_20_psp_1_93_itm_1 <= acc_20_psp_1_sva[11];
+        ACC1_slc_ACC1_acc_228_psp_55_itm_1 <= ACC1_acc_228_psp_sva[6];
+        ACC1_3_slc_acc_10_psp_62_itm_1 <= ACC1_acc_224_psp_sva[8];
+        ACC1_acc_652_itm_1 <= nl_ACC1_acc_652_itm_1[10:0];
+        ACC1_acc_655_itm_1 <= nl_ACC1_acc_655_itm_1[11:0];
+        main_stage_0_2 <= 1'b1;
+        regs_regs_slc_regs_regs_2_10_itm <= reg_regs_regs_0_sva_cse[79:70];
+        regs_regs_slc_regs_regs_2_11_itm <= reg_regs_regs_0_sva_cse[69:60];
+        regs_regs_slc_regs_regs_2_9_itm <= reg_regs_regs_0_sva_cse[89:80];
+        regs_regs_slc_regs_regs_2_4_itm <= reg_regs_regs_0_sva_cse[49:40];
+        regs_regs_slc_regs_regs_2_5_itm <= reg_regs_regs_0_sva_cse[39:30];
+        regs_regs_slc_regs_regs_2_3_itm <= reg_regs_regs_0_sva_cse[59:50];
+        regs_regs_slc_regs_regs_2_itm <= reg_regs_regs_0_sva_cse[29:20];
+        regs_regs_slc_regs_regs_2_1_itm <= reg_regs_regs_0_sva_cse[19:10];
+        regs_regs_slc_regs_regs_2_2_itm <= reg_regs_regs_0_sva_cse[9:0];
+        reg_regs_regs_0_sva_cse <= vin_rsc_mgc_in_wire_d;
+      end
+    end
+  end
+  assign nl_ACC1_acc_659_itm_1  = conv_s2s_12_13(conv_s2s_11_12({(ACC1_1_acc_25_psp_sva[11])
+      , 2'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11]) ,
+      1'b0 , (ACC1_1_acc_25_psp_sva[11]) , 1'b0 , (ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_224_psp_sva[0])})
+      + conv_u2s_11_12({conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[9])
+      + conv_u2u_1_2(acc_psp_1_sva[9])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[8]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[8])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[8]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[8])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[9]))
+      + conv_u2u_1_4(acc_psp_2_sva[9])) * 8'b10101) , (ACC1_acc_227_psp_sva[4]) ,
+      (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_s2s_12_13(conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_psp_2_sva[9]) , 1'b0
+      , (acc_psp_2_sva[9]) , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_2_sva[7]) , 1'b0 , (acc_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~ (ACC1_acc_338_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_338_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_210_psp_2_sva[3]) ,
+      (acc_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_220_psp_1_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_2_sva[3])
+      , (acc_psp_2_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_210_psp_2_sva[3]) ,
+      (acc_psp_2_sva[2]) , (ACC1_acc_210_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_2_sva[7])
+      , (acc_psp_2_sva[4]) , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_673_cse)))
+      + conv_u2s_7_8({(acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])
+      , 1'b0 , (acc_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_2_sva[6])
+      , 1'b0 , (acc_psp_2_sva[6]) , 1'b0 , (acc_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_673_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , ACC1_1_and_3_cse_sva}))))))))))
+      + ({(acc_psp_2_sva[11]) , 2'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11])
+      , 1'b0 , (acc_psp_2_sva[11]) , (conv_u2u_1_3(acc_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])))}))
+      + conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_20_psp_2_sva[10]) , 1'b0
+      , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10]) , 1'b0 , (acc_20_psp_2_sva[10])
+      , 1'b0 , (acc_20_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_20_psp_2_sva[9]) ,
+      1'b0 , (acc_20_psp_2_sva[9]) , 1'b0 , (acc_20_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_20_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_20_psp_2_sva[7]) , 1'b0 , (acc_20_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_20_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~((ACC1_acc_359_itm[2])
+      & (~ (acc_20_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (~ (ACC1_acc_358_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (ACC1_acc_358_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[11]) , (ACC1_acc_217_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_20_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_217_psp_2_sva[3])
+      , (acc_20_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_223_psp_1_sva[2:1])) +
+      (readslicef_5_4_1((conv_u2s_3_5({(acc_20_psp_2_sva[3]) , (acc_20_psp_2_sva[1])
+      , 1'b1}) + conv_s2s_3_5({(ACC1_acc_217_psp_2_sva[3]) , (acc_20_psp_2_sva[2])
+      , (ACC1_acc_217_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_20_psp_2_sva[7])
+      , (acc_20_psp_2_sva[4]) , (signext_2_1(acc_20_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_699_cse)))
+      + conv_u2s_7_8({(acc_20_psp_2_sva[8]) , 1'b0 , (acc_20_psp_2_sva[8]) , 1'b0
+      , (acc_20_psp_2_sva[8]) , 1'b0 , (acc_20_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_20_psp_2_sva[11])
+      , (signext_2_1(acc_20_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_20_psp_2_sva[6])
+      , 1'b0 , (acc_20_psp_2_sva[6]) , 1'b0 , (acc_20_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_699_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_2_sva[9]) , ((acc_20_psp_2_sva[11])
+      & (~ (ACC1_acc_359_itm[2])) & (ACC1_acc_359_itm[1]))})))))))))) + ({(acc_20_psp_2_sva[11])
+      , 2'b0 , (acc_20_psp_2_sva[11]) , 1'b0 , (acc_20_psp_2_sva[11]) , 1'b0 , (acc_20_psp_2_sva[11])
+      , (conv_u2u_1_3(acc_20_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_20_psp_2_sva[11])))})));
+  assign nl_ACC1_acc_658_itm_1  = conv_s2s_12_13(conv_s2s_10_12(conv_s2s_9_10(conv_u2s_7_9(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(ACC1_acc_224_psp_1_sva[6])
+      , (ACC1_acc_228_psp_sva[3]) , (signext_2_1(ACC1_acc_224_psp_sva[11]))}) + conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[5])
+      , (ACC1_acc_226_psp_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})) +
+      conv_u2u_5_6(conv_u2u_4_5({(ACC1_1_acc_25_psp_sva[7]) , (ACC1_acc_224_psp_1_sva[3])
+      , (signext_2_1(ACC1_acc_228_psp_sva[11]))}) + conv_u2u_4_5({(acc_20_psp_1_sva[4])
+      , (ACC1_1_acc_25_psp_sva[4]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5({(~ (ACC1_acc_217_psp_1_sva[3])) ,
+      (~ (ACC1_acc_210_psp_1_sva[3])) , 1'b1 , (~ (ACC1_acc_367_itm[3]))}) + conv_u2u_4_5({(acc_psp_2_sva[5])
+      , (acc_20_psp_1_sva[3]) , (signext_2_1(ACC1_acc_228_psp_sva[11]))})) + conv_s2u_5_6(conv_u2s_3_5(readslicef_4_3_1((conv_u2u_3_4({((acc_20_psp_1_sva[11])
+      & (~ (ACC1_acc_424_itm[2])) & (ACC1_acc_424_itm[1])) , (ACC1_acc_224_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_3_4({(acc_psp_2_sva[3]) , (ACC1_acc_224_psp_1_sva[2]) ,
+      (ACC1_1_acc_25_psp_sva[2])})))) + conv_s2s_3_5({(ACC1_acc_223_psp_sva[2:1])
+      , (ACC1_acc_224_psp_1_sva[3])})))) + conv_s2s_7_9(conv_s2s_6_7(conv_s2s_4_6(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_s2s_3_5({(ACC1_acc_220_psp_1_sva[2:1]) , (ACC1_acc_377_itm[2])}))))
+      + conv_u2s_4_6({(ACC1_acc_224_psp_1_sva[4]) , (ACC1_acc_224_psp_sva[3]) , (signext_2_1(ACC1_acc_224_psp_sva[11]))}))
+      + conv_s2s_6_7(conv_u2s_4_6({(acc_psp_2_sva[7]) , (acc_psp_2_sva[4]) , (signext_2_1(ACC1_acc_228_psp_sva[6]))})
+      + conv_s2s_3_6(conv_s2s_2_3(ACC1_acc_220_psp_sva[2:1]) + conv_s2s_2_3(ACC1_acc_222_psp_sva[2:1])))))
+      + conv_u2s_9_10({(acc_20_psp_1_sva[9]) , 1'b0 , (acc_20_psp_1_sva[9]) , 1'b0
+      , (acc_20_psp_1_sva[9]) , (ACC1_acc_228_psp_sva[4]) , 1'b0 , (signext_2_1(ACC1_acc_224_psp_sva[6]))}))
+      + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_4_10(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[8])
+      + conv_u2u_1_2(acc_psp_1_sva[8])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[7]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[7])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[7]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[7])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[8]))
+      + conv_u2u_1_4(acc_psp_2_sva[8])) * 10'b1010101))) + conv_u2s_12_14(conv_u2s_24_13(conv_u2u_4_12(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[10])
+      + conv_u2u_1_2(acc_psp_1_sva[10])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[9]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[9])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[9]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[9])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[10]))
+      + conv_u2u_1_4(acc_psp_2_sva[10])) * 12'b101010101));
+  assign nl_ACC1_acc_661_itm_1  = conv_s2s_13_14(conv_s2s_12_13({(ACC1_acc_226_psp_sva[11])
+      , 1'b0 , (ACC1_acc_226_psp_sva[11]) , 7'b0 , (ACC1_acc_226_psp_sva[11]) , (acc_psp_1_sva[2])})
+      + conv_u2s_12_13({conv_u2u_18_9(conv_u2u_3_9(conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_224_psp_sva[10])
+      + conv_u2u_1_2(ACC1_acc_228_psp_sva[10])) + conv_u2u_1_2(ACC1_acc_226_psp_sva[10]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[10])) * 9'b1010101) , (acc_psp_1_sva[4])
+      , (signext_2_1(ACC1_acc_224_psp_sva[4]))})) + conv_s2s_13_14(conv_s2s_26_13(conv_u2s_2_13((conv_u2u_1_2(ACC1_acc_227_psp_sva[11])
+      + conv_u2u_1_2(acc_psp_1_sva[11])) + conv_u2u_1_2(acc_psp_2_sva[11])) * 13'b1110010101001));
+  assign nl_ACC1_acc_652_itm_1  = conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[4])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[3])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_346_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_acc_405_itm[2])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_3_acc_212_psp_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[5]) , (ACC1_3_acc_212_psp_sva[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (ACC1_3_acc_212_psp_sva[1])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[9]) , ((ACC1_acc_226_psp_sva[11])
+      & (~ (ACC1_acc_387_itm[2])) & (ACC1_acc_387_itm[1]))})))))))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (~((ACC1_acc_387_itm[2])
+      & (~ (ACC1_acc_226_psp_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11]) , (ACC1_acc_386_itm[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_sva[11]) , (ACC1_acc_384_itm[4])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[5])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_384_itm[3])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (ACC1_acc_384_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , ((ACC1_acc_228_psp_sva[11])
+      & (~ (ACC1_acc_378_itm[2])) & (ACC1_acc_378_itm[1]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_227_psp_sva[11]) , (~((ACC1_acc_378_itm[2])
+      & (~ (ACC1_acc_228_psp_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_375_itm[4])})))))))))
+      + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_375_itm[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , (ACC1_acc_375_itm[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , ((ACC1_acc_224_psp_sva[11])
+      & (~ (ACC1_acc_415_itm[2])) & (ACC1_acc_415_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~((ACC1_acc_415_itm[2])
+      & (~ (ACC1_acc_224_psp_sva[11]))))}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_414_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_412_itm[4])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[5]) , (ACC1_acc_412_itm[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_412_itm[2])}))))))))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_227_psp_sva[3])
+      , (ACC1_acc_227_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(acc_psp_1_sva[3]) , (ACC1_acc_227_psp_sva[2])
+      , ((acc_psp_1_sva[11]) & (~ (ACC1_acc_396_itm[2])) & (ACC1_acc_396_itm[1]))}))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_224_psp_sva[2]) ,
+      (ACC1_acc_227_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[2])
+      , (ACC1_acc_227_psp_sva[4]) , (~((ACC1_acc_396_itm[2]) & (~ (acc_psp_1_sva[11]))))})))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_226_psp_sva[2])
+      , (acc_psp_1_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_224_psp_1_sva[2]) ,
+      (acc_psp_1_sva[3]) , (ACC1_acc_395_itm[2])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_1_acc_25_psp_sva[3])
+      , (acc_psp_1_sva[4]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[1]) , (ACC1_acc_224_psp_sva[1])
+      , (ACC1_acc_210_psp_1_sva[3])})))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[2])
+      , (ACC1_acc_224_psp_sva[2]) , 1'b1}) + conv_u2u_3_4({(acc_20_psp_1_sva[3])
+      , (ACC1_acc_224_psp_sva[3]) , (ACC1_acc_210_psp_1_sva[2])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(acc_20_psp_1_sva[4])
+      , (ACC1_acc_228_psp_sva[0]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[1])
+      , (ACC1_acc_226_psp_sva[0]) , (ACC1_acc_210_psp_1_sva[1])}))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[2])
+      , (ACC1_acc_226_psp_sva[1]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_217_psp_1_sva[3])
+      , (ACC1_acc_226_psp_sva[2]) , (ACC1_1_acc_25_psp_sva[4])})))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_423_itm[2])
+      , (ACC1_acc_226_psp_sva[3]) , 1'b1}) + conv_u2u_3_4({(~((ACC1_acc_424_itm[2])
+      & (~ (acc_20_psp_1_sva[11])))) , (ACC1_acc_224_psp_1_sva[0]) , (ACC1_1_acc_25_psp_sva[3])})))))))))
+      + conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_3_4({(acc_20_psp_1_sva[6]) , 1'b0 ,
+      (acc_20_psp_1_sva[6])}) + conv_u2u_3_4({(acc_psp_1_sva[7]) , (acc_20_psp_1_sva[5])
+      , (ACC1_acc_226_psp_sva[4])})) , (conv_u2u_2_3({(acc_20_psp_1_sva[6]) , (ACC1_acc_228_psp_sva[1])})
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_224_psp_sva[10])))}) + conv_u2u_7_8({(conv_u2u_3_4({(ACC1_acc_224_psp_sva[6])
+      , (acc_20_psp_1_sva[7]) , (ACC1_acc_226_psp_sva[6])}) + conv_u2u_3_4({(ACC1_acc_228_psp_sva[6])
+      , 1'b0 , (ACC1_acc_227_psp_sva[5])})) , ACC1_acc_724_cse}))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8({(conv_u2u_1_2(ACC1_acc_226_psp_sva[6])
+      + conv_u2u_1_2(ACC1_acc_224_psp_1_sva[6])) , (conv_u2u_1_2(ACC1_acc_227_psp_sva[7])
+      + conv_u2u_1_2(acc_psp_1_sva[5])) , ACC1_acc_724_cse}) + conv_u2u_7_8({(conv_u2u_1_2(ACC1_1_acc_25_psp_sva[7])
+      + conv_u2u_1_2(acc_psp_2_sva[7])) , (conv_u2u_1_2(acc_psp_1_sva[7]) + conv_u2u_1_2(ACC1_acc_224_psp_sva[4]))
+      , ACC1_acc_724_cse})) + conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_227_psp_sva[11])
+      , (signext_2_1(ACC1_acc_227_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_1_sva[11])
+      , (signext_2_1(acc_psp_1_sva[11]))}))))) + conv_u2u_10_11(conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_sva[11])
+      , (signext_2_1(ACC1_acc_224_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_228_psp_sva[11])
+      , (signext_2_1(ACC1_acc_228_psp_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(acc_20_psp_1_sva[11])
+      , 1'b0 , (signext_2_1(acc_20_psp_1_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_20_psp_1_sva[11])
+      , (signext_2_1(acc_20_psp_1_sva[11]))})))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_acc_226_psp_sva[11])
+      , 1'b0 , (signext_2_1(ACC1_acc_226_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(ACC1_acc_224_psp_1_sva[11])
+      , (signext_2_1(ACC1_acc_224_psp_1_sva[11]))}))) + conv_u2u_8_9(conv_u2u_7_8(signext_7_4({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b0 , (signext_2_1(ACC1_1_acc_25_psp_sva[11]))})) + conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})))));
+  assign nl_ACC1_acc_655_itm_1  = conv_s2s_11_12(conv_u2s_10_11({(acc_20_psp_1_sva[10])
+      , 1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10]) , 1'b0 , (acc_20_psp_1_sva[10])
+      , 1'b0 , (acc_20_psp_1_sva[10]) , (ACC1_acc_228_psp_sva[3])}) + conv_s2s_9_11(conv_s2s_8_9(({7'b1011011
+      , (ACC1_1_acc_25_psp_sva[1])}) + conv_u2s_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse)
+      + conv_u2u_3_4(ACC1_acc_509_cse)) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_227_psp_sva[5]))) + conv_u2u_3_4(ACC1_acc_506_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+      + conv_u2u_3_4(ACC1_acc_502_cse)))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+      + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[7]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[9]))
+      + conv_u2u_2_3(signext_2_1(acc_20_psp_1_sva[11]))))) + conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_562_ncse)
+      + conv_u2u_4_5(ACC1_acc_562_ncse))))) + conv_u2s_8_9(conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_502_cse)
+      + conv_u2u_3_4(ACC1_acc_506_cse)) + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse)
+      + conv_u2u_3_4(ACC1_acc_489_cse))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[6]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[8]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[10]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_u2u_4_5(ACC1_acc_553_ncse)))
+      + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(ACC1_acc_553_ncse) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_226_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_489_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_506_cse) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[9]) , ACC1_1_and_3_cse_sva}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_20_psp_1_sva[11]) , ACC1_1_nand_1_cse_sva})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_338_itm[2])})))))))))
+      + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[2])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_210_psp_2_sva[1])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[9]) , (acc_psp_2_sva[4])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (acc_psp_2_sva[3])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (acc_psp_2_sva[1])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , ((ACC1_acc_227_psp_sva[11])
+      & (~ (ACC1_acc_406_itm[2])) & (ACC1_acc_406_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[6])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[8]) , (~((ACC1_acc_406_itm[2])
+      & (~ (ACC1_acc_227_psp_sva[11]))))})))))))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[10])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , ((ACC1_1_acc_25_psp_sva[11])
+      & (~ (ACC1_acc_368_itm[2])) & (ACC1_acc_368_itm[1]))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (~((ACC1_acc_368_itm[2])
+      & (~ (ACC1_1_acc_25_psp_sva[11]))))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_acc_367_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_1_acc_208_psp_sva[3])})))))))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[4]) , (ACC1_1_acc_208_psp_sva[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_224_psp_1_sva[11]) , (ACC1_1_acc_208_psp_sva[1])}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , (~((ACC1_acc_349_itm[2])
+      & (~ (ACC1_acc_224_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_1_acc_25_psp_sva[9]) , (ACC1_acc_348_itm[2])}))))))))))))
+      + conv_u2s_10_12(conv_u2u_8_10((conv_u2u_7_8({(acc_20_psp_1_sva[7]) , (ACC1_acc_227_psp_sva[7])
+      , 1'b0 , (ACC1_acc_224_psp_sva[6]) , 1'b0 , (signext_2_1(ACC1_acc_224_psp_sva[11]))})
+      + conv_u2u_6_8(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[10]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+      + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_516_cse) + conv_u2u_3_4(ACC1_acc_516_cse)))
+      + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[11]))
+      + conv_u2u_2_3(signext_2_1(ACC1_acc_228_psp_sva[4]))) + conv_u2u_3_4(ACC1_acc_516_cse))
+      + conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_509_cse) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]))))))) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_412_itm[4])) , (~ (ACC1_acc_423_itm[3])) , (~ (ACC1_acc_338_itm[3]))})
+      + conv_u2u_3_4({(~ (ACC1_acc_375_itm[4])) , 1'b1 , (~ (ACC1_acc_395_itm[3]))}))
+      + conv_u2u_4_5({(readslicef_3_2_1((conv_u2u_2_3({(~ (ACC1_acc_384_itm[4]))
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_3_acc_212_psp_sva[3])) , 1'b1})))) , (({1'b1
+      , (~ (ACC1_acc_414_itm[3]))}) + ({1'b1 , (~ (ACC1_acc_377_itm[3]))}))})) +
+      conv_u2u_5_6(conv_u2u_4_5({(readslicef_3_2_1((conv_u2u_2_3({(~ (ACC1_acc_346_itm[4]))
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_1_acc_208_psp_sva[3])) , 1'b1})))) , (({1'b1
+      , (~ (ACC1_acc_386_itm[3]))}) + ({1'b1 , (~ (ACC1_acc_405_itm[3]))}))}) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_210_psp_2_sva[3])) , 1'b1 , (~ (ACC1_acc_348_itm[3]))}) + conv_s2u_2_4(ACC1_acc_221_psp_sva[2:1]))))
+      + conv_s2u_6_7(conv_s2s_5_6(conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_221_psp_2_sva[2:1])
+      + conv_u2s_2_4(signext_2_1(ACC1_acc_228_psp_sva[8]))) + conv_s2s_4_5(conv_s2s_2_4(ACC1_acc_219_psp_2_sva[2:1])
+      + conv_u2s_2_4(signext_2_1(ACC1_acc_226_psp_sva[11])))) + conv_s2s_5_6(conv_s2s_4_5(readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_s2s_3_5({(ACC1_acc_222_psp_1_sva[2:1]) , (acc_psp_2_sva[2])}))))
+      + conv_s2s_4_5(readslicef_5_4_1((conv_s2s_3_5({(ACC1_acc_219_psp_1_sva[2:1])
+      , 1'b1}) + conv_u2s_3_5(signext_3_2({(ACC1_1_acc_25_psp_sva[11]) , ((ACC1_acc_224_psp_1_sva[11])
+      & (~ (ACC1_acc_349_itm[2])) & (ACC1_acc_349_itm[1]))}))))))))) + conv_u2u_9_10(conv_u2u_8_9(conv_u2u_16_8(conv_u2u_4_8(conv_u2u_3_4((((conv_u2u_2_3((conv_u2u_1_2(ACC1_acc_227_psp_sva[6])
+      + conv_u2u_1_2(acc_psp_1_sva[6])) + conv_u2u_1_2(ACC1_acc_224_psp_sva[5]))
+      + conv_u2u_1_3(ACC1_acc_228_psp_sva[5])) + conv_u2u_1_3(ACC1_acc_226_psp_sva[5]))
+      + conv_u2u_1_3(ACC1_acc_224_psp_1_sva[5])) + conv_u2u_1_3(ACC1_1_acc_25_psp_sva[6]))
+      + conv_u2u_1_4(acc_psp_2_sva[6])) * 8'b10101)) + conv_u2u_8_9({(acc_20_psp_1_sva[8])
+      , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0 , (acc_20_psp_1_sva[8]) , 1'b0 , (acc_20_psp_1_sva[8])
+      , (ACC1_acc_228_psp_sva[2])})));
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [2:0] signext_3_2;
+    input [1:0] vector;
+  begin
+    signext_3_2= {{1{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_3;
+    input [2:0] vector;
+  begin
+    signext_7_3= {{4{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_4;
+    input [3:0] vector;
+  begin
+    signext_7_4= {{3{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_7_10 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_10 = {{3{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [14:0] conv_s2s_14_15 ;
+    input signed [13:0]  vector ;
+  begin
+    conv_s2s_14_15 = {vector[13], vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_13_14 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_14 = {vector[12], vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_2_14 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_14 = {{12{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_4_8 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_8 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_1_4 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_4 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_6_8 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_8 = {{2{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_9_10 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_10 = {vector[8], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_s2u_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2u_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_3_6 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_6 = {{3{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_4_10 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_10 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_24_13 ;
+    input [23:0]  vector ;
+  begin
+    conv_u2s_24_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_4_12 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_12 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_26_13 ;
+    input signed [25:0]  vector ;
+  begin
+    conv_s2s_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_9_11 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_11 = {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_8_9 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_9 = {vector[7], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_s2u_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2u_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_s2u_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2u_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v12/rtl.v.psr b/Sobel/sobel.v12/rtl.v.psr
new file mode 100644
index 0000000..62d1040
--- /dev/null
+++ b/Sobel/sobel.v12/rtl.v.psr
@@ -0,0 +1,289 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/rtl.v}} -format verilog
+   setup_design -design=sobel
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'sobel': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'sobel': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'sobel'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'sobel'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to vout_rsc_z(29:0)
+   report_timing -from en -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from vin_rsc_z(89:0) -to vout_rsc_z(29:0)
+   report_timing -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock clk] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock en] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'sobel'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'sobel'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v12 mapped.v]
+          puts "-- Writing mapped netlist for 'sobel' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v12 gate.v]
+          set gate_sdf [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v12 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/Sobel/sobel.v12/rtl.v.psr_timing b/Sobel/sobel.v12/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/Sobel/sobel.v12/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/Sobel/sobel.v12/rtl.v_order.txt b/Sobel/sobel.v12/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/Sobel/sobel.v12/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/Sobel/sobel.v12/rtl_mgc_ioport.v b/Sobel/sobel.v12/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v12/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v12/rtl_mgc_ioport_v2001.v b/Sobel/sobel.v12/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v12/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v12/schedule.gnt b/Sobel/sobel.v12/schedule.gnt
new file mode 100644
index 0000000..b9f90e6
--- /dev/null
+++ b/Sobel/sobel.v12/schedule.gnt
@@ -0,0 +1,2358 @@
+set a(0-9369) {NAME FRAME:p:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-9368 XREFS 57581 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-9373 {}}} SUCCS {{258 0 0-9373 {}}} CYCLES {}}
+set a(0-9370) {NAME asn(regs.regs(1))#1 TYPE ASSIGN PAR 0-9368 XREFS 57582 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-9373 {}}} SUCCS {{258 0 0-9373 {}}} CYCLES {}}
+set a(0-9371) {NAME asn(regs.regs(0))#1 TYPE ASSIGN PAR 0-9368 XREFS 57583 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-9373 {}}} SUCCS {{258 0 0-9373 {}}} CYCLES {}}
+set a(0-9372) {NAME FRAME:asn(exit:FRAME) TYPE ASSIGN PAR 0-9368 XREFS 57584 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-9373 {}}} SUCCS {{259 0 0-9373 {}}} CYCLES {}}
+set a(0-9374) {NAME FRAME:asn TYPE ASSIGN PAR 0-9373 XREFS 57585 LOC {0 1.0 0 1.0 0 1.0 3 1.0} PREDS {{262 0 0-11719 {}}} SUCCS {{259 0 0-9375 {}} {256 0 0-11719 {}}} CYCLES {}}
+set a(0-9375) {NAME FRAME:select TYPE SELECT PAR 0-9373 XREFS 57586 LOC {0 1.0 0 1.0 0 1.0 3 1.0} PREDS {{259 0 0-9374 {}}} SUCCS {} CYCLES {}}
+set a(0-9376) {NAME SHIFT:if:else:else:else:asn(regs.regs(1)) TYPE ASSIGN PAR 0-9373 XREFS 57587 LOC {0 1.0 0 1.0 0 1.0 2 0.046457874999999996} PREDS {{262 0 0-11712 {}}} SUCCS {{256 0 0-11712 {}} {258 0 0-11713 {}}} CYCLES {}}
+set a(0-9377) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,90) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_read(vin:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-9373 XREFS 57588 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {} SUCCS {{259 0 0-9378 {}} {258 0 0-9380 {}} {258 0 0-9383 {}} {258 0 0-9463 {}} {258 0 0-9465 {}} {258 0 0-9468 {}} {258 0 0-9536 {}} {258 0 0-9538 {}} {258 0 0-9541 {}} {258 0 0-9612 {}} {258 0 0-9613 {}} {258 0 0-9615 {}} {258 0 0-11712 {}}} CYCLES {}}
+set a(0-9378) {NAME regs.regs:slc(regs.regs(0))#6 TYPE READSLICE PAR 0-9373 XREFS 57589 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-9377 {}}} SUCCS {{259 0 0-9379 {}}} CYCLES {}}
+set a(0-9379) {NAME {regs.operator[]:not} TYPE NOT PAR 0-9373 XREFS 57590 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-9378 {}}} SUCCS {{258 0 0-9382 {}}} CYCLES {}}
+set a(0-9380) {NAME regs.regs:slc(regs.regs(0))#7 TYPE READSLICE PAR 0-9373 XREFS 57591 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{258 0 0-9377 {}}} SUCCS {{259 0 0-9381 {}}} CYCLES {}}
+set a(0-9381) {NAME {regs.operator[]#1:not} TYPE NOT PAR 0-9373 XREFS 57592 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-9380 {}}} SUCCS {{259 0 0-9382 {}}} CYCLES {}}
+set a(0-9382) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#331 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 57593 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.09544225333641132 1 0.1749305033364113} PREDS {{258 0 0-9379 {}} {259 0 0-9381 {}}} SUCCS {{258 0 0-9386 {}}} CYCLES {}}
+set a(0-9383) {NAME regs.regs:slc(regs.regs(0))#8 TYPE READSLICE PAR 0-9373 XREFS 57594 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{258 0 0-9377 {}}} SUCCS {{259 0 0-9384 {}}} CYCLES {}}
+set a(0-9384) {NAME {regs.operator[]#2:not} TYPE NOT PAR 0-9373 XREFS 57595 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-9383 {}}} SUCCS {{259 0 0-9385 {}}} CYCLES {}}
+set a(0-9385) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#330 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 57596 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.09544225333641132 1 0.1749305033364113} PREDS {{259 0 0-9384 {}}} SUCCS {{259 0 0-9386 {}}} CYCLES {}}
+set a(0-9386) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-1:acc TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 57597 LOC {1 0.07118415 1 0.0954423 1 0.0954423 1 0.17081305637342836 1 0.25030130637342834} PREDS {{258 0 0-9382 {}} {259 0 0-9385 {}}} SUCCS {{259 0 0-9387 {}} {258 0 0-9390 {}} {258 0 0-9392 {}} {258 0 0-9397 {}} {258 0 0-9399 {}} {258 0 0-9403 {}} {258 0 0-9405 {}} {258 0 0-9407 {}} {258 0 0-9413 {}} {258 0 0-9415 {}} {258 0 0-9417 {}} {258 0 0-9421 {}} {258 0 0-9455 {}} {258 0 0-9458 {}} {258 0 0-10153 {}} {258 0 0-10161 {}} {258 0 0-10162 {}} {258 0 0-10163 {}} {258 0 0-10164 {}} {258 0 0-10165 {}} {258 0 0-10167 {}} {258 0 0-10168 {}} {258 0 0-10169 {}} {258 0 0-10170 {}} {258 0 0-10173 {}} {258 0 0-10174 {}} {258 0 0-10175 {}} {258 0 0-10178 {}} {258 0 0-10181 {}} {258 0 0-10186 {}} {258 0 0-10189 {}} {258 0 0-10197 {}} {258 0 0-10200 {}} {258 0 0-10206 {}} {258 0 0-10209 {}} {258 0 0-10220 {}} {258 0 0-10224 {}} {258 0 0-10230 {}} {258 0 0-10231 {}} {258 0 0-10235 {}} {258 0 0-10242 {}} {258 0 0-10243 {}} {258 0 0-10244 {}} {258 0 0-10247 {}} {258 0 0-10249 {}} {258 0 0-10254 {}} {258 0 0-10255 {}} {258 0 0-10256 {}} {258 0 0-10257 {}} {258 0 0-10260 {}} {258 0 0-10261 {}} {258 0 0-10265 {}} {258 0 0-10266 {}} {258 0 0-10267 {}} {258 0 0-10269 {}} {258 0 0-10271 {}} {258 0 0-10274 {}} {258 0 0-10277 {}} {258 0 0-10287 {}} {258 0 0-10288 {}} {258 0 0-10290 {}} {258 0 0-10291 {}} {258 0 0-10292 {}} {258 0 0-10293 {}} {258 0 0-10294 {}} {258 0 0-10478 {}} {258 0 0-10492 {}} {258 0 0-10519 {}} {258 0 0-10520 {}} {258 0 0-10551 {}} {258 0 0-10568 {}} {258 0 0-10594 {}} {258 0 0-10773 {}} {258 0 0-10776 {}} {258 0 0-10786 {}} {258 0 0-10789 {}} {258 0 0-10795 {}} {258 0 0-10798 {}} {258 0 0-10805 {}} {258 0 0-10808 {}} {258 0 0-10818 {}} {258 0 0-10821 {}} {258 0 0-10832 {}} {258 0 0-10835 {}} {258 0 0-10841 {}} {258 0 0-10844 {}} {258 0 0-10851 {}} {258 0 0-10854 {}} {258 0 0-10860 {}} {258 0 0-10863 {}} {258 0 0-11021 {}} {258 0 0-11080 {}} {258 0 0-11081 {}} {258 0 0-11333 {}} {258 0 0-11344 {}} {258 0 0-11353 {}} {258 0 0-11591 {}} {258 0 0-11624 {}}} CYCLES {}}
+set a(0-9387) {NAME ACC1-1:slc(acc.psp)#11 TYPE READSLICE PAR 0-9373 XREFS 57598 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.274975825} PREDS {{259 0 0-9386 {}}} SUCCS {{259 0 0-9388 {}}} CYCLES {}}
+set a(0-9388) {NAME ACC1-1:not#302 TYPE NOT PAR 0-9373 XREFS 57599 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{259 0 0-9387 {}}} SUCCS {{259 0 0-9389 {}}} CYCLES {}}
+set a(0-9389) {NAME ACC1:conc#1132 TYPE CONCATENATE PAR 0-9373 XREFS 57600 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{259 0 0-9388 {}}} SUCCS {{258 0 0-9394 {}}} CYCLES {}}
+set a(0-9390) {NAME ACC1-1:slc(acc.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 57601 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.274975825} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-9391 {}}} CYCLES {}}
+set a(0-9391) {NAME ACC1-1:not#229 TYPE NOT PAR 0-9373 XREFS 57602 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{259 0 0-9390 {}}} SUCCS {{258 0 0-9393 {}}} CYCLES {}}
+set a(0-9392) {NAME ACC1-1:slc(acc.psp)#8 TYPE READSLICE PAR 0-9373 XREFS 57603 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.274975825} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-9393 {}}} CYCLES {}}
+set a(0-9393) {NAME ACC1:conc#1133 TYPE CONCATENATE PAR 0-9373 XREFS 57604 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{258 0 0-9391 {}} {259 0 0-9392 {}}} SUCCS {{259 0 0-9394 {}}} CYCLES {}}
+set a(0-9394) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#334 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 57605 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.21596033508947524 1 0.29544858508947525} PREDS {{258 0 0-9389 {}} {259 0 0-9393 {}}} SUCCS {{259 0 0-9395 {}}} CYCLES {}}
+set a(0-9395) {NAME ACC1:slc#15 TYPE READSLICE PAR 0-9373 XREFS 57606 LOC {1 0.16702775 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{259 0 0-9394 {}}} SUCCS {{259 0 0-9396 {}}} CYCLES {}}
+set a(0-9396) {NAME ACC1:conc#1136 TYPE CONCATENATE PAR 0-9373 XREFS 57607 LOC {1 0.16702775 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{259 0 0-9395 {}}} SUCCS {{258 0 0-9401 {}}} CYCLES {}}
+set a(0-9397) {NAME ACC1-1:slc(acc.psp) TYPE READSLICE PAR 0-9373 XREFS 57608 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.29544862499999996} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-9398 {}}} CYCLES {}}
+set a(0-9398) {NAME ACC1:conc#1127 TYPE CONCATENATE PAR 0-9373 XREFS 57609 LOC {1 0.14655495 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{259 0 0-9397 {}}} SUCCS {{258 0 0-9400 {}}} CYCLES {}}
+set a(0-9399) {NAME ACC1-1:slc(acc.psp)#10 TYPE READSLICE PAR 0-9373 XREFS 57610 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.29544862499999996} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-9400 {}}} CYCLES {}}
+set a(0-9400) {NAME ACC1:conc#1137 TYPE CONCATENATE PAR 0-9373 XREFS 57611 LOC {1 0.14655495 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{258 0 0-9398 {}} {259 0 0-9399 {}}} SUCCS {{259 0 0-9401 {}}} CYCLES {}}
+set a(0-9401) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#336 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 57612 LOC {1 0.16702775 1 0.21596037499999998 1 0.21596037499999998 1 0.2591522701789505 1 0.33864052017895047} PREDS {{258 0 0-9396 {}} {259 0 0-9400 {}}} SUCCS {{259 0 0-9402 {}}} CYCLES {}}
+set a(0-9402) {NAME ACC1:slc#17 TYPE READSLICE PAR 0-9373 XREFS 57613 LOC {1 0.21021969999999998 1 0.25915232499999996 1 0.25915232499999996 1 0.338640575} PREDS {{259 0 0-9401 {}}} SUCCS {{258 0 0-9426 {}}} CYCLES {}}
+set a(0-9403) {NAME ACC1-1:slc(acc.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 57614 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-9404 {}}} CYCLES {}}
+set a(0-9404) {NAME ACC1:conc#1130 TYPE CONCATENATE PAR 0-9373 XREFS 57615 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-9403 {}}} SUCCS {{258 0 0-9410 {}}} CYCLES {}}
+set a(0-9405) {NAME ACC1-1:slc(acc.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 57616 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-9406 {}}} CYCLES {}}
+set a(0-9406) {NAME ACC1-1:not#230 TYPE NOT PAR 0-9373 XREFS 57617 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-9405 {}}} SUCCS {{258 0 0-9409 {}}} CYCLES {}}
+set a(0-9407) {NAME ACC1-1:slc(acc.psp)#7 TYPE READSLICE PAR 0-9373 XREFS 57618 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-9408 {}}} CYCLES {}}
+set a(0-9408) {NAME ACC1-1:not#232 TYPE NOT PAR 0-9373 XREFS 57619 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-9407 {}}} SUCCS {{259 0 0-9409 {}}} CYCLES {}}
+set a(0-9409) {NAME ACC1:conc#1131 TYPE CONCATENATE PAR 0-9373 XREFS 57620 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9406 {}} {259 0 0-9408 {}}} SUCCS {{259 0 0-9410 {}}} CYCLES {}}
+set a(0-9410) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#333 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57621 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.21159611008947524 1 0.29108436008947525} PREDS {{258 0 0-9404 {}} {259 0 0-9409 {}}} SUCCS {{259 0 0-9411 {}}} CYCLES {}}
+set a(0-9411) {NAME ACC1:slc#14 TYPE READSLICE PAR 0-9373 XREFS 57622 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-9410 {}}} SUCCS {{259 0 0-9412 {}}} CYCLES {}}
+set a(0-9412) {NAME ACC1:conc#1134 TYPE CONCATENATE PAR 0-9373 XREFS 57623 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-9411 {}}} SUCCS {{258 0 0-9424 {}}} CYCLES {}}
+set a(0-9413) {NAME ACC1-1:slc(acc.psp)#4 TYPE READSLICE PAR 0-9373 XREFS 57624 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-9414 {}}} CYCLES {}}
+set a(0-9414) {NAME ACC1:conc#1128 TYPE CONCATENATE PAR 0-9373 XREFS 57625 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-9413 {}}} SUCCS {{258 0 0-9419 {}}} CYCLES {}}
+set a(0-9415) {NAME ACC1-1:slc(acc.psp)#5 TYPE READSLICE PAR 0-9373 XREFS 57626 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-9416 {}}} CYCLES {}}
+set a(0-9416) {NAME ACC1-1:not#231 TYPE NOT PAR 0-9373 XREFS 57627 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-9415 {}}} SUCCS {{258 0 0-9418 {}}} CYCLES {}}
+set a(0-9417) {NAME ACC1-1:slc(acc.psp)#6 TYPE READSLICE PAR 0-9373 XREFS 57628 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-9418 {}}} CYCLES {}}
+set a(0-9418) {NAME ACC1:conc#1129 TYPE CONCATENATE PAR 0-9373 XREFS 57629 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9416 {}} {259 0 0-9417 {}}} SUCCS {{259 0 0-9419 {}}} CYCLES {}}
+set a(0-9419) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#332 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57630 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.21159611008947524 1 0.29108436008947525} PREDS {{258 0 0-9414 {}} {259 0 0-9418 {}}} SUCCS {{259 0 0-9420 {}}} CYCLES {}}
+set a(0-9420) {NAME ACC1:slc#13 TYPE READSLICE PAR 0-9373 XREFS 57631 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-9419 {}}} SUCCS {{258 0 0-9423 {}}} CYCLES {}}
+set a(0-9421) {NAME ACC1-1:slc(acc.psp)#9 TYPE READSLICE PAR 0-9373 XREFS 57632 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.29108439999999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-9422 {}}} CYCLES {}}
+set a(0-9422) {NAME ACC1-1:not#233 TYPE NOT PAR 0-9373 XREFS 57633 LOC {1 0.14655495 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-9421 {}}} SUCCS {{259 0 0-9423 {}}} CYCLES {}}
+set a(0-9423) {NAME ACC1:conc#1135 TYPE CONCATENATE PAR 0-9373 XREFS 57634 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{258 0 0-9420 {}} {259 0 0-9422 {}}} SUCCS {{259 0 0-9424 {}}} CYCLES {}}
+set a(0-9424) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#335 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 57635 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.25915227707082716 1 0.33864052707082715} PREDS {{258 0 0-9412 {}} {259 0 0-9423 {}}} SUCCS {{259 0 0-9425 {}}} CYCLES {}}
+set a(0-9425) {NAME ACC1:slc#16 TYPE READSLICE PAR 0-9373 XREFS 57636 LOC {1 0.23489417499999998 1 0.25915232499999996 1 0.25915232499999996 1 0.338640575} PREDS {{259 0 0-9424 {}}} SUCCS {{259 0 0-9426 {}}} CYCLES {}}
+set a(0-9426) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1-1:acc#210 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 57637 LOC {1 0.23489417499999998 1 0.25915232499999996 1 0.25915232499999996 1 0.2921890951789505 1 0.3716773451789505} PREDS {{258 0 0-9402 {}} {259 0 0-9425 {}}} SUCCS {{259 0 0-9427 {}} {258 0 0-9429 {}} {258 0 0-9431 {}} {258 0 0-9435 {}} {258 0 0-10211 {}} {258 0 0-10223 {}} {258 0 0-10234 {}} {258 0 0-10237 {}} {258 0 0-11305 {}} {258 0 0-11314 {}} {258 0 0-11324 {}} {258 0 0-11569 {}}} CYCLES {}}
+set a(0-9427) {NAME ACC1-1:slc(ACC1:acc#210.psp) TYPE READSLICE PAR 0-9373 XREFS 57638 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{259 0 0-9426 {}}} SUCCS {{259 0 0-9428 {}}} CYCLES {}}
+set a(0-9428) {NAME ACC1:conc#1138 TYPE CONCATENATE PAR 0-9373 XREFS 57639 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{259 0 0-9427 {}}} SUCCS {{258 0 0-9433 {}}} CYCLES {}}
+set a(0-9429) {NAME ACC1-1:slc(ACC1:acc#210.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 57640 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{258 0 0-9426 {}}} SUCCS {{259 0 0-9430 {}}} CYCLES {}}
+set a(0-9430) {NAME ACC1-1:not#273 TYPE NOT PAR 0-9373 XREFS 57641 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{259 0 0-9429 {}}} SUCCS {{258 0 0-9432 {}}} CYCLES {}}
+set a(0-9431) {NAME ACC1-1:slc(ACC1:acc#210.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 57642 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{258 0 0-9426 {}}} SUCCS {{259 0 0-9432 {}}} CYCLES {}}
+set a(0-9432) {NAME ACC1:conc#1139 TYPE CONCATENATE PAR 0-9373 XREFS 57643 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{258 0 0-9430 {}} {259 0 0-9431 {}}} SUCCS {{259 0 0-9433 {}}} CYCLES {}}
+set a(0-9433) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#337 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57644 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3329721600894753 1 0.4124604100894752} PREDS {{258 0 0-9428 {}} {259 0 0-9432 {}}} SUCCS {{259 0 0-9434 {}}} CYCLES {}}
+set a(0-9434) {NAME ACC1:slc#18 TYPE READSLICE PAR 0-9373 XREFS 57645 LOC {1 0.30871404999999996 1 0.3329722 1 0.3329722 1 0.41246045} PREDS {{259 0 0-9433 {}}} SUCCS {{258 0 0-9437 {}}} CYCLES {}}
+set a(0-9435) {NAME ACC1-1:slc(ACC1:acc#210.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 57646 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.41246045} PREDS {{258 0 0-9426 {}}} SUCCS {{259 0 0-9436 {}}} CYCLES {}}
+set a(0-9436) {NAME ACC1-1:not#305 TYPE NOT PAR 0-9373 XREFS 57647 LOC {1 0.267931 1 0.3329722 1 0.3329722 1 0.41246045} PREDS {{259 0 0-9435 {}}} SUCCS {{259 0 0-9437 {}}} CYCLES {}}
+set a(0-9437) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-1:acc#220 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 57648 LOC {1 0.30871404999999996 1 0.3329722 1 0.3329722 1 0.35344496008947524 1 0.4329332100894752} PREDS {{258 0 0-9434 {}} {259 0 0-9436 {}}} SUCCS {{259 0 0-9438 {}} {258 0 0-9441 {}} {258 0 0-10228 {}} {258 0 0-10508 {}}} CYCLES {}}
+set a(0-9438) {NAME ACC1-1:slc(ACC1:acc#220.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 57649 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-9437 {}}} SUCCS {{259 0 0-9439 {}}} CYCLES {}}
+set a(0-9439) {NAME ACC1-1:not#293 TYPE NOT PAR 0-9373 XREFS 57650 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-9438 {}}} SUCCS {{259 0 0-9440 {}}} CYCLES {}}
+set a(0-9440) {NAME ACC1:conc#1140 TYPE CONCATENATE PAR 0-9373 XREFS 57651 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-9439 {}}} SUCCS {{258 0 0-9443 {}}} CYCLES {}}
+set a(0-9441) {NAME ACC1-1:slc(ACC1:acc#220.psp) TYPE READSLICE PAR 0-9373 XREFS 57652 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{258 0 0-9437 {}}} SUCCS {{259 0 0-9442 {}}} CYCLES {}}
+set a(0-9442) {NAME ACC1:conc#1141 TYPE CONCATENATE PAR 0-9373 XREFS 57653 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-9441 {}}} SUCCS {{259 0 0-9443 {}}} CYCLES {}}
+set a(0-9443) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#338 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 57654 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.38069087707082716 1 0.4601791270708272} PREDS {{258 0 0-9440 {}} {259 0 0-9442 {}}} SUCCS {{259 0 0-9444 {}}} CYCLES {}}
+set a(0-9444) {NAME ACC1:slc#19 TYPE READSLICE PAR 0-9373 XREFS 57655 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-9443 {}}} SUCCS {{259 0 0-9445 {}} {258 0 0-9447 {}} {258 0 0-9449 {}} {258 0 0-10191 {}} {258 0 0-10202 {}} {258 0 0-11292 {}} {258 0 0-11537 {}}} CYCLES {}}
+set a(0-9445) {NAME ACC1-1:slc(acc.imod#2) TYPE READSLICE PAR 0-9373 XREFS 57656 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-9444 {}}} SUCCS {{259 0 0-9446 {}}} CYCLES {}}
+set a(0-9446) {NAME ACC1:conc#1143 TYPE CONCATENATE PAR 0-9373 XREFS 57657 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-9445 {}}} SUCCS {{258 0 0-9452 {}}} CYCLES {}}
+set a(0-9447) {NAME ACC1-1:slc(acc.imod#2)#1 TYPE READSLICE PAR 0-9373 XREFS 57658 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{258 0 0-9444 {}}} SUCCS {{259 0 0-9448 {}}} CYCLES {}}
+set a(0-9448) {NAME ACC1-1:not#25 TYPE NOT PAR 0-9373 XREFS 57659 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-9447 {}}} SUCCS {{258 0 0-9451 {}}} CYCLES {}}
+set a(0-9449) {NAME ACC1-1:slc(acc.imod#2)#2 TYPE READSLICE PAR 0-9373 XREFS 57660 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{258 0 0-9444 {}}} SUCCS {{259 0 0-9450 {}}} CYCLES {}}
+set a(0-9450) {NAME ACC1-1:not#26 TYPE NOT PAR 0-9373 XREFS 57661 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-9449 {}}} SUCCS {{259 0 0-9451 {}}} CYCLES {}}
+set a(0-9451) {NAME ACC1:conc#1144 TYPE CONCATENATE PAR 0-9373 XREFS 57662 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{258 0 0-9448 {}} {259 0 0-9450 {}}} SUCCS {{259 0 0-9452 {}}} CYCLES {}}
+set a(0-9452) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#339 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 57663 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.40793680207082716 1 0.4874250520708272} PREDS {{258 0 0-9446 {}} {259 0 0-9451 {}}} SUCCS {{259 0 0-9453 {}}} CYCLES {}}
+set a(0-9453) {NAME ACC1:slc#20 TYPE READSLICE PAR 0-9373 XREFS 57664 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-9452 {}}} SUCCS {{259 0 0-9454 {}} {258 0 0-9459 {}} {258 0 0-9461 {}}} CYCLES {}}
+set a(0-9454) {NAME ACC1-1:slc(acc.imod#7) TYPE READSLICE PAR 0-9373 XREFS 57665 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-9453 {}}} SUCCS {{258 0 0-9457 {}}} CYCLES {}}
+set a(0-9455) {NAME ACC1-1:slc(acc.idiv#1)#44 TYPE READSLICE PAR 0-9373 XREFS 57666 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-9456 {}}} CYCLES {}}
+set a(0-9456) {NAME ACC1-1:not#59 TYPE NOT PAR 0-9373 XREFS 57667 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-9455 {}}} SUCCS {{259 0 0-9457 {}}} CYCLES {}}
+set a(0-9457) {NAME ACC1-1:nand#1 TYPE NAND PAR 0-9373 XREFS 57668 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-9454 {}} {259 0 0-9456 {}}} SUCCS {{258 0 0-10183 {}} {258 0 0-11284 {}}} CYCLES {}}
+set a(0-9458) {NAME ACC1-1:slc(acc.idiv#1)#45 TYPE READSLICE PAR 0-9373 XREFS 57669 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5545639} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-9462 {}}} CYCLES {}}
+set a(0-9459) {NAME ACC1-1:slc(acc.imod#7)#1 TYPE READSLICE PAR 0-9373 XREFS 57670 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{258 0 0-9453 {}}} SUCCS {{259 0 0-9460 {}}} CYCLES {}}
+set a(0-9460) {NAME ACC1-1:not#60 TYPE NOT PAR 0-9373 XREFS 57671 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{259 0 0-9459 {}}} SUCCS {{258 0 0-9462 {}}} CYCLES {}}
+set a(0-9461) {NAME ACC1-1:slc(acc.imod#7)#2 TYPE READSLICE PAR 0-9373 XREFS 57672 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{258 0 0-9453 {}}} SUCCS {{259 0 0-9462 {}}} CYCLES {}}
+set a(0-9462) {NAME ACC1-1:and#3 TYPE AND PAR 0-9373 XREFS 57673 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{258 0 0-9460 {}} {258 0 0-9458 {}} {259 0 0-9461 {}}} SUCCS {{258 0 0-10279 {}} {258 0 0-11275 {}}} CYCLES {}}
+set a(0-9463) {NAME regs.regs:slc(regs.regs(0))#3 TYPE READSLICE PAR 0-9373 XREFS 57674 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.17147225} PREDS {{258 0 0-9377 {}}} SUCCS {{259 0 0-9464 {}}} CYCLES {}}
+set a(0-9464) {NAME ACC1:not TYPE NOT PAR 0-9373 XREFS 57675 LOC {1 0.0 1 0.098043075 1 0.098043075 1 0.17147225} PREDS {{259 0 0-9463 {}}} SUCCS {{258 0 0-9467 {}}} CYCLES {}}
+set a(0-9465) {NAME regs.regs:slc(regs.regs(0))#4 TYPE READSLICE PAR 0-9373 XREFS 57676 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.17147225} PREDS {{258 0 0-9377 {}}} SUCCS {{259 0 0-9466 {}}} CYCLES {}}
+set a(0-9466) {NAME ACC1:not#307 TYPE NOT PAR 0-9373 XREFS 57677 LOC {1 0.0 1 0.098043075 1 0.098043075 1 0.17147225} PREDS {{259 0 0-9465 {}}} SUCCS {{259 0 0-9467 {}}} CYCLES {}}
+set a(0-9467) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#341 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 57678 LOC {1 0.0 1 0.098043075 1 0.098043075 1 0.16922717833641132 1 0.2426563533364113} PREDS {{258 0 0-9464 {}} {259 0 0-9466 {}}} SUCCS {{258 0 0-9471 {}}} CYCLES {}}
+set a(0-9468) {NAME regs.regs:slc(regs.regs(0))#5 TYPE READSLICE PAR 0-9373 XREFS 57679 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.17147225} PREDS {{258 0 0-9377 {}}} SUCCS {{259 0 0-9469 {}}} CYCLES {}}
+set a(0-9469) {NAME ACC1:not#308 TYPE NOT PAR 0-9373 XREFS 57680 LOC {1 0.0 1 0.098043075 1 0.098043075 1 0.17147225} PREDS {{259 0 0-9468 {}}} SUCCS {{259 0 0-9470 {}}} CYCLES {}}
+set a(0-9470) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#340 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 57681 LOC {1 0.0 1 0.098043075 1 0.098043075 1 0.16922717833641132 1 0.2426563533364113} PREDS {{259 0 0-9469 {}}} SUCCS {{259 0 0-9471 {}}} CYCLES {}}
+set a(0-9471) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-1:acc#224 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 57682 LOC {1 0.07118415 1 0.16922722499999998 1 0.16922722499999998 1 0.24459798137342836 1 0.3180271563734284} PREDS {{258 0 0-9467 {}} {259 0 0-9470 {}}} SUCCS {{259 0 0-9472 {}} {258 0 0-9475 {}} {258 0 0-9477 {}} {258 0 0-9479 {}} {258 0 0-9484 {}} {258 0 0-9490 {}} {258 0 0-9492 {}} {258 0 0-9494 {}} {258 0 0-9499 {}} {258 0 0-9501 {}} {258 0 0-9505 {}} {258 0 0-10149 {}} {258 0 0-10448 {}} {258 0 0-10460 {}} {258 0 0-10489 {}} {258 0 0-10493 {}} {258 0 0-10500 {}} {258 0 0-10513 {}} {258 0 0-10547 {}} {258 0 0-10564 {}} {258 0 0-10583 {}} {258 0 0-10602 {}} {258 0 0-10906 {}} {258 0 0-10968 {}} {258 0 0-11010 {}} {258 0 0-11069 {}} {258 0 0-11070 {}} {258 0 0-11348 {}} {258 0 0-11351 {}} {258 0 0-11358 {}} {258 0 0-11361 {}} {258 0 0-11371 {}} {258 0 0-11374 {}} {258 0 0-11386 {}} {258 0 0-11389 {}} {258 0 0-11399 {}} {258 0 0-11402 {}} {258 0 0-11412 {}} {258 0 0-11415 {}} {258 0 0-11421 {}} {258 0 0-11424 {}} {258 0 0-11432 {}} {258 0 0-11435 {}} {258 0 0-11441 {}} {258 0 0-11444 {}} {258 0 0-11457 {}} {258 0 0-11599 {}} {258 0 0-11620 {}}} CYCLES {}}
+set a(0-9472) {NAME ACC1-1:slc(acc#10.psp)#39 TYPE READSLICE PAR 0-9373 XREFS 57683 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.35881025} PREDS {{259 0 0-9471 {}}} SUCCS {{259 0 0-9473 {}}} CYCLES {}}
+set a(0-9473) {NAME ACC1-1:not#247 TYPE NOT PAR 0-9373 XREFS 57684 LOC {1 0.14655495 1 0.285381075 1 0.285381075 1 0.35881025} PREDS {{259 0 0-9472 {}}} SUCCS {{259 0 0-9474 {}}} CYCLES {}}
+set a(0-9474) {NAME ACC1:conc#1152 TYPE CONCATENATE PAR 0-9373 XREFS 57685 LOC {1 0.14655495 1 0.285381075 1 0.285381075 1 0.35881025} PREDS {{259 0 0-9473 {}}} SUCCS {{258 0 0-9487 {}}} CYCLES {}}
+set a(0-9475) {NAME ACC1-1:slc(acc#10.psp)#40 TYPE READSLICE PAR 0-9373 XREFS 57686 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-9476 {}}} CYCLES {}}
+set a(0-9476) {NAME ACC1:conc#1148 TYPE CONCATENATE PAR 0-9373 XREFS 57687 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{259 0 0-9475 {}}} SUCCS {{258 0 0-9482 {}}} CYCLES {}}
+set a(0-9477) {NAME ACC1-1:slc(acc#10.psp)#41 TYPE READSLICE PAR 0-9373 XREFS 57688 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-9478 {}}} CYCLES {}}
+set a(0-9478) {NAME ACC1-1:not#248 TYPE NOT PAR 0-9373 XREFS 57689 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{259 0 0-9477 {}}} SUCCS {{258 0 0-9481 {}}} CYCLES {}}
+set a(0-9479) {NAME ACC1-1:slc(acc#10.psp)#45 TYPE READSLICE PAR 0-9373 XREFS 57690 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-9480 {}}} CYCLES {}}
+set a(0-9480) {NAME ACC1-1:not#250 TYPE NOT PAR 0-9373 XREFS 57691 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{259 0 0-9479 {}}} SUCCS {{259 0 0-9481 {}}} CYCLES {}}
+set a(0-9481) {NAME ACC1:conc#1149 TYPE CONCATENATE PAR 0-9373 XREFS 57692 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3180272} PREDS {{258 0 0-9478 {}} {259 0 0-9480 {}}} SUCCS {{259 0 0-9482 {}}} CYCLES {}}
+set a(0-9482) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#343 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57693 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.2853810350894752 1 0.3588102100894752} PREDS {{258 0 0-9476 {}} {259 0 0-9481 {}}} SUCCS {{259 0 0-9483 {}}} CYCLES {}}
+set a(0-9483) {NAME ACC1:slc#22 TYPE READSLICE PAR 0-9373 XREFS 57694 LOC {1 0.187338 1 0.285381075 1 0.285381075 1 0.35881025} PREDS {{259 0 0-9482 {}}} SUCCS {{258 0 0-9486 {}}} CYCLES {}}
+set a(0-9484) {NAME ACC1-1:slc(acc#10.psp)#47 TYPE READSLICE PAR 0-9373 XREFS 57695 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.35881025} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-9485 {}}} CYCLES {}}
+set a(0-9485) {NAME ACC1-1:not#251 TYPE NOT PAR 0-9373 XREFS 57696 LOC {1 0.14655495 1 0.285381075 1 0.285381075 1 0.35881025} PREDS {{259 0 0-9484 {}}} SUCCS {{259 0 0-9486 {}}} CYCLES {}}
+set a(0-9486) {NAME ACC1:conc#1153 TYPE CONCATENATE PAR 0-9373 XREFS 57697 LOC {1 0.187338 1 0.285381075 1 0.285381075 1 0.35881025} PREDS {{258 0 0-9483 {}} {259 0 0-9485 {}}} SUCCS {{259 0 0-9487 {}}} CYCLES {}}
+set a(0-9487) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#345 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 57698 LOC {1 0.187338 1 0.285381075 1 0.285381075 1 0.3184178451789505 1 0.3918470201789505} PREDS {{258 0 0-9474 {}} {259 0 0-9486 {}}} SUCCS {{259 0 0-9488 {}}} CYCLES {}}
+set a(0-9488) {NAME ACC1:slc#24 TYPE READSLICE PAR 0-9373 XREFS 57699 LOC {1 0.220374825 1 0.3184179 1 0.3184179 1 0.391847075} PREDS {{259 0 0-9487 {}}} SUCCS {{259 0 0-9489 {}}} CYCLES {}}
+set a(0-9489) {NAME ACC1:conc#1154 TYPE CONCATENATE PAR 0-9373 XREFS 57700 LOC {1 0.220374825 1 0.3184179 1 0.3184179 1 0.391847075} PREDS {{259 0 0-9488 {}}} SUCCS {{258 0 0-9507 {}}} CYCLES {}}
+set a(0-9490) {NAME ACC1-1:slc(acc#10.psp)#42 TYPE READSLICE PAR 0-9373 XREFS 57701 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3238181} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-9491 {}}} CYCLES {}}
+set a(0-9491) {NAME ACC1:conc#1146 TYPE CONCATENATE PAR 0-9373 XREFS 57702 LOC {1 0.14655495 1 0.250388925 1 0.250388925 1 0.3238181} PREDS {{259 0 0-9490 {}}} SUCCS {{258 0 0-9496 {}}} CYCLES {}}
+set a(0-9492) {NAME ACC1-1:slc(acc#10.psp)#43 TYPE READSLICE PAR 0-9373 XREFS 57703 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3238181} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-9493 {}}} CYCLES {}}
+set a(0-9493) {NAME ACC1-1:not#249 TYPE NOT PAR 0-9373 XREFS 57704 LOC {1 0.14655495 1 0.250388925 1 0.250388925 1 0.3238181} PREDS {{259 0 0-9492 {}}} SUCCS {{258 0 0-9495 {}}} CYCLES {}}
+set a(0-9494) {NAME ACC1-1:slc(acc#10.psp)#44 TYPE READSLICE PAR 0-9373 XREFS 57705 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.3238181} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-9495 {}}} CYCLES {}}
+set a(0-9495) {NAME ACC1:conc#1147 TYPE CONCATENATE PAR 0-9373 XREFS 57706 LOC {1 0.14655495 1 0.250388925 1 0.250388925 1 0.3238181} PREDS {{258 0 0-9493 {}} {259 0 0-9494 {}}} SUCCS {{259 0 0-9496 {}}} CYCLES {}}
+set a(0-9496) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#342 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57707 LOC {1 0.14655495 1 0.250388925 1 0.250388925 1 0.29117193508947525 1 0.36460111008947527} PREDS {{258 0 0-9491 {}} {259 0 0-9495 {}}} SUCCS {{259 0 0-9497 {}}} CYCLES {}}
+set a(0-9497) {NAME ACC1:slc#21 TYPE READSLICE PAR 0-9373 XREFS 57708 LOC {1 0.187338 1 0.29117197499999997 1 0.29117197499999997 1 0.36460115} PREDS {{259 0 0-9496 {}}} SUCCS {{259 0 0-9498 {}}} CYCLES {}}
+set a(0-9498) {NAME ACC1:conc#1150 TYPE CONCATENATE PAR 0-9373 XREFS 57709 LOC {1 0.187338 1 0.29117197499999997 1 0.29117197499999997 1 0.36460115} PREDS {{259 0 0-9497 {}}} SUCCS {{258 0 0-9503 {}}} CYCLES {}}
+set a(0-9499) {NAME ACC1-1:slc(acc#10.psp)#49 TYPE READSLICE PAR 0-9373 XREFS 57710 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.36460115} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-9500 {}}} CYCLES {}}
+set a(0-9500) {NAME ACC1-1:not#252 TYPE NOT PAR 0-9373 XREFS 57711 LOC {1 0.14655495 1 0.29117197499999997 1 0.29117197499999997 1 0.36460115} PREDS {{259 0 0-9499 {}}} SUCCS {{258 0 0-9502 {}}} CYCLES {}}
+set a(0-9501) {NAME ACC1-1:slc(acc#10.psp)#46 TYPE READSLICE PAR 0-9373 XREFS 57712 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.36460115} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-9502 {}}} CYCLES {}}
+set a(0-9502) {NAME ACC1:conc#1151 TYPE CONCATENATE PAR 0-9373 XREFS 57713 LOC {1 0.14655495 1 0.29117197499999997 1 0.29117197499999997 1 0.36460115} PREDS {{258 0 0-9500 {}} {259 0 0-9501 {}}} SUCCS {{259 0 0-9503 {}}} CYCLES {}}
+set a(0-9503) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#344 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 57714 LOC {1 0.187338 1 0.29117197499999997 1 0.29117197499999997 1 0.3184178520708272 1 0.3918470270708272} PREDS {{258 0 0-9498 {}} {259 0 0-9502 {}}} SUCCS {{259 0 0-9504 {}}} CYCLES {}}
+set a(0-9504) {NAME ACC1:slc#23 TYPE READSLICE PAR 0-9373 XREFS 57715 LOC {1 0.21458392499999998 1 0.3184179 1 0.3184179 1 0.391847075} PREDS {{259 0 0-9503 {}}} SUCCS {{258 0 0-9506 {}}} CYCLES {}}
+set a(0-9505) {NAME ACC1-1:slc(acc#10.psp)#48 TYPE READSLICE PAR 0-9373 XREFS 57716 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.391847075} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-9506 {}}} CYCLES {}}
+set a(0-9506) {NAME ACC1:conc#1155 TYPE CONCATENATE PAR 0-9373 XREFS 57717 LOC {1 0.21458392499999998 1 0.3184179 1 0.3184179 1 0.391847075} PREDS {{258 0 0-9504 {}} {259 0 0-9505 {}}} SUCCS {{259 0 0-9507 {}}} CYCLES {}}
+set a(0-9507) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#346 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-9373 XREFS 57718 LOC {1 0.220374825 1 0.3184179 1 0.3184179 1 0.35670735949693605 1 0.43013653449693606} PREDS {{258 0 0-9489 {}} {259 0 0-9506 {}}} SUCCS {{259 0 0-9508 {}}} CYCLES {}}
+set a(0-9508) {NAME ACC1:slc#25 TYPE READSLICE PAR 0-9373 XREFS 57719 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.43013657499999997} PREDS {{259 0 0-9507 {}}} SUCCS {{259 0 0-9509 {}} {258 0 0-9511 {}} {258 0 0-9513 {}} {258 0 0-9517 {}} {258 0 0-10618 {}} {258 0 0-10627 {}} {258 0 0-10637 {}} {258 0 0-11558 {}}} CYCLES {}}
+set a(0-9509) {NAME ACC1-1:slc(ACC1:acc#214.psp) TYPE READSLICE PAR 0-9373 XREFS 57720 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{259 0 0-9508 {}}} SUCCS {{259 0 0-9510 {}}} CYCLES {}}
+set a(0-9510) {NAME ACC1:conc#1156 TYPE CONCATENATE PAR 0-9373 XREFS 57721 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{259 0 0-9509 {}}} SUCCS {{258 0 0-9515 {}}} CYCLES {}}
+set a(0-9511) {NAME ACC1-1:slc(ACC1:acc#214.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 57722 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{258 0 0-9508 {}}} SUCCS {{259 0 0-9512 {}}} CYCLES {}}
+set a(0-9512) {NAME ACC1-1:not#281 TYPE NOT PAR 0-9373 XREFS 57723 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{259 0 0-9511 {}}} SUCCS {{258 0 0-9514 {}}} CYCLES {}}
+set a(0-9513) {NAME ACC1-1:slc(ACC1:acc#214.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 57724 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{258 0 0-9508 {}}} SUCCS {{259 0 0-9514 {}}} CYCLES {}}
+set a(0-9514) {NAME ACC1:conc#1157 TYPE CONCATENATE PAR 0-9373 XREFS 57725 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{258 0 0-9512 {}} {259 0 0-9513 {}}} SUCCS {{259 0 0-9515 {}}} CYCLES {}}
+set a(0-9515) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#347 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57726 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.3974904100894753 1 0.5338902350894752} PREDS {{258 0 0-9510 {}} {259 0 0-9514 {}}} SUCCS {{259 0 0-9516 {}}} CYCLES {}}
+set a(0-9516) {NAME ACC1:slc#26 TYPE READSLICE PAR 0-9373 XREFS 57727 LOC {1 0.29944737499999996 1 0.39749045 1 0.39749045 1 0.533890275} PREDS {{259 0 0-9515 {}}} SUCCS {{258 0 0-9519 {}}} CYCLES {}}
+set a(0-9517) {NAME ACC1-1:slc(ACC1:acc#214.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 57728 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.533890275} PREDS {{258 0 0-9508 {}}} SUCCS {{259 0 0-9518 {}}} CYCLES {}}
+set a(0-9518) {NAME ACC1-1:not#303 TYPE NOT PAR 0-9373 XREFS 57729 LOC {1 0.258664325 1 0.39749045 1 0.39749045 1 0.533890275} PREDS {{259 0 0-9517 {}}} SUCCS {{259 0 0-9519 {}}} CYCLES {}}
+set a(0-9519) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-1:acc#225 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 57730 LOC {1 0.29944737499999996 1 0.39749045 1 0.39749045 1 0.41796321008947523 1 0.5543630350894753} PREDS {{258 0 0-9516 {}} {259 0 0-9518 {}}} SUCCS {{259 0 0-9520 {}} {258 0 0-9523 {}} {258 0 0-11590 {}}} CYCLES {}}
+set a(0-9520) {NAME ACC1-1:slc(ACC1:acc#222.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 57731 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-9519 {}}} SUCCS {{259 0 0-9521 {}}} CYCLES {}}
+set a(0-9521) {NAME ACC1-1:not#297 TYPE NOT PAR 0-9373 XREFS 57732 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-9520 {}}} SUCCS {{259 0 0-9522 {}}} CYCLES {}}
+set a(0-9522) {NAME ACC1:conc#1158 TYPE CONCATENATE PAR 0-9373 XREFS 57733 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-9521 {}}} SUCCS {{258 0 0-9525 {}}} CYCLES {}}
+set a(0-9523) {NAME ACC1-1:slc(ACC1:acc#222.psp) TYPE READSLICE PAR 0-9373 XREFS 57734 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{258 0 0-9519 {}}} SUCCS {{259 0 0-9524 {}}} CYCLES {}}
+set a(0-9524) {NAME ACC1:conc#1159 TYPE CONCATENATE PAR 0-9373 XREFS 57735 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-9523 {}}} SUCCS {{259 0 0-9525 {}}} CYCLES {}}
+set a(0-9525) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#348 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 57736 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.44520912707082716 1 0.5816089520708271} PREDS {{258 0 0-9522 {}} {259 0 0-9524 {}}} SUCCS {{259 0 0-9526 {}}} CYCLES {}}
+set a(0-9526) {NAME ACC1:slc#27 TYPE READSLICE PAR 0-9373 XREFS 57737 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-9525 {}}} SUCCS {{259 0 0-9527 {}} {258 0 0-9529 {}} {258 0 0-9531 {}} {258 0 0-11468 {}} {258 0 0-11571 {}}} CYCLES {}}
+set a(0-9527) {NAME ACC1-1:slc(acc.imod#10) TYPE READSLICE PAR 0-9373 XREFS 57738 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-9526 {}}} SUCCS {{259 0 0-9528 {}}} CYCLES {}}
+set a(0-9528) {NAME ACC1:conc#1161 TYPE CONCATENATE PAR 0-9373 XREFS 57739 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-9527 {}}} SUCCS {{258 0 0-9534 {}}} CYCLES {}}
+set a(0-9529) {NAME ACC1-1:slc(acc.imod#10)#1 TYPE READSLICE PAR 0-9373 XREFS 57740 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-9526 {}}} SUCCS {{259 0 0-9530 {}}} CYCLES {}}
+set a(0-9530) {NAME ACC1-1:not#89 TYPE NOT PAR 0-9373 XREFS 57741 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-9529 {}}} SUCCS {{258 0 0-9533 {}}} CYCLES {}}
+set a(0-9531) {NAME ACC1-1:slc(acc.imod#10)#2 TYPE READSLICE PAR 0-9373 XREFS 57742 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-9526 {}}} SUCCS {{259 0 0-9532 {}}} CYCLES {}}
+set a(0-9532) {NAME ACC1-1:not#90 TYPE NOT PAR 0-9373 XREFS 57743 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-9531 {}}} SUCCS {{259 0 0-9533 {}}} CYCLES {}}
+set a(0-9533) {NAME ACC1:conc#1162 TYPE CONCATENATE PAR 0-9373 XREFS 57744 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-9530 {}} {259 0 0-9532 {}}} SUCCS {{259 0 0-9534 {}}} CYCLES {}}
+set a(0-9534) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#349 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 57745 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.47245505207082716 1 0.6088548770708271} PREDS {{258 0 0-9528 {}} {259 0 0-9533 {}}} SUCCS {{259 0 0-9535 {}}} CYCLES {}}
+set a(0-9535) {NAME ACC1:slc#28 TYPE READSLICE PAR 0-9373 XREFS 57746 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9534 {}}} SUCCS {{258 0 0-11456 {}} {258 0 0-11600 {}} {258 0 0-11602 {}}} CYCLES {}}
+set a(0-9536) {NAME regs.regs:slc(regs.regs(0))#9 TYPE READSLICE PAR 0-9373 XREFS 57747 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{258 0 0-9377 {}}} SUCCS {{259 0 0-9537 {}}} CYCLES {}}
+set a(0-9537) {NAME {regs.operator[]#12:not} TYPE NOT PAR 0-9373 XREFS 57748 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-9536 {}}} SUCCS {{258 0 0-9540 {}}} CYCLES {}}
+set a(0-9538) {NAME regs.regs:slc(regs.regs(0))#10 TYPE READSLICE PAR 0-9373 XREFS 57749 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{258 0 0-9377 {}}} SUCCS {{259 0 0-9539 {}}} CYCLES {}}
+set a(0-9539) {NAME {regs.operator[]#13:not} TYPE NOT PAR 0-9373 XREFS 57750 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-9538 {}}} SUCCS {{259 0 0-9540 {}}} CYCLES {}}
+set a(0-9540) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#351 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 57751 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.09544225333641132 1 0.1749305033364113} PREDS {{258 0 0-9537 {}} {259 0 0-9539 {}}} SUCCS {{258 0 0-9544 {}}} CYCLES {}}
+set a(0-9541) {NAME regs.regs:slc(regs.regs(0))#11 TYPE READSLICE PAR 0-9373 XREFS 57752 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{258 0 0-9377 {}}} SUCCS {{259 0 0-9542 {}}} CYCLES {}}
+set a(0-9542) {NAME {regs.operator[]#14:not} TYPE NOT PAR 0-9373 XREFS 57753 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.10374639999999999} PREDS {{259 0 0-9541 {}}} SUCCS {{259 0 0-9543 {}}} CYCLES {}}
+set a(0-9543) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#350 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 57754 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.09544225333641132 1 0.1749305033364113} PREDS {{259 0 0-9542 {}}} SUCCS {{259 0 0-9544 {}}} CYCLES {}}
+set a(0-9544) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-1:acc#20 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 57755 LOC {1 0.07118415 1 0.0954423 1 0.0954423 1 0.17081305637342836 1 0.25030130637342834} PREDS {{258 0 0-9540 {}} {259 0 0-9543 {}}} SUCCS {{259 0 0-9545 {}} {258 0 0-9548 {}} {258 0 0-9550 {}} {258 0 0-9555 {}} {258 0 0-9557 {}} {258 0 0-9561 {}} {258 0 0-9563 {}} {258 0 0-9565 {}} {258 0 0-9571 {}} {258 0 0-9573 {}} {258 0 0-9575 {}} {258 0 0-9579 {}} {258 0 0-10299 {}} {258 0 0-10300 {}} {258 0 0-10301 {}} {258 0 0-10302 {}} {258 0 0-10303 {}} {258 0 0-10305 {}} {258 0 0-10306 {}} {258 0 0-10307 {}} {258 0 0-10308 {}} {258 0 0-10311 {}} {258 0 0-10312 {}} {258 0 0-10313 {}} {258 0 0-10316 {}} {258 0 0-10319 {}} {258 0 0-10322 {}} {258 0 0-10328 {}} {258 0 0-10331 {}} {258 0 0-10339 {}} {258 0 0-10342 {}} {258 0 0-10348 {}} {258 0 0-10351 {}} {258 0 0-10362 {}} {258 0 0-10366 {}} {258 0 0-10372 {}} {258 0 0-10373 {}} {258 0 0-10377 {}} {258 0 0-10384 {}} {258 0 0-10385 {}} {258 0 0-10386 {}} {258 0 0-10389 {}} {258 0 0-10391 {}} {258 0 0-10396 {}} {258 0 0-10397 {}} {258 0 0-10398 {}} {258 0 0-10399 {}} {258 0 0-10402 {}} {258 0 0-10403 {}} {258 0 0-10407 {}} {258 0 0-10408 {}} {258 0 0-10409 {}} {258 0 0-10411 {}} {258 0 0-10413 {}} {258 0 0-10416 {}} {258 0 0-10419 {}} {258 0 0-10421 {}} {258 0 0-10434 {}} {258 0 0-10435 {}} {258 0 0-10437 {}} {258 0 0-10438 {}} {258 0 0-10439 {}} {258 0 0-10440 {}} {258 0 0-10441 {}}} CYCLES {}}
+set a(0-9545) {NAME ACC1-1:slc(acc#20.psp)#11 TYPE READSLICE PAR 0-9373 XREFS 57756 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.274975825} PREDS {{259 0 0-9544 {}}} SUCCS {{259 0 0-9546 {}}} CYCLES {}}
+set a(0-9546) {NAME ACC1-1:not#304 TYPE NOT PAR 0-9373 XREFS 57757 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{259 0 0-9545 {}}} SUCCS {{259 0 0-9547 {}}} CYCLES {}}
+set a(0-9547) {NAME ACC1:conc#1168 TYPE CONCATENATE PAR 0-9373 XREFS 57758 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{259 0 0-9546 {}}} SUCCS {{258 0 0-9552 {}}} CYCLES {}}
+set a(0-9548) {NAME ACC1-1:slc(acc#20.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 57759 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.274975825} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-9549 {}}} CYCLES {}}
+set a(0-9549) {NAME ACC1-1:not#260 TYPE NOT PAR 0-9373 XREFS 57760 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{259 0 0-9548 {}}} SUCCS {{258 0 0-9551 {}}} CYCLES {}}
+set a(0-9550) {NAME ACC1-1:slc(acc#20.psp)#8 TYPE READSLICE PAR 0-9373 XREFS 57761 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.274975825} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-9551 {}}} CYCLES {}}
+set a(0-9551) {NAME ACC1:conc#1169 TYPE CONCATENATE PAR 0-9373 XREFS 57762 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.274975825} PREDS {{258 0 0-9549 {}} {259 0 0-9550 {}}} SUCCS {{259 0 0-9552 {}}} CYCLES {}}
+set a(0-9552) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#354 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 57763 LOC {1 0.14655495 1 0.195487575 1 0.195487575 1 0.21596033508947524 1 0.29544858508947525} PREDS {{258 0 0-9547 {}} {259 0 0-9551 {}}} SUCCS {{259 0 0-9553 {}}} CYCLES {}}
+set a(0-9553) {NAME ACC1:slc#31 TYPE READSLICE PAR 0-9373 XREFS 57764 LOC {1 0.16702775 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{259 0 0-9552 {}}} SUCCS {{259 0 0-9554 {}}} CYCLES {}}
+set a(0-9554) {NAME ACC1:conc#1172 TYPE CONCATENATE PAR 0-9373 XREFS 57765 LOC {1 0.16702775 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{259 0 0-9553 {}}} SUCCS {{258 0 0-9559 {}}} CYCLES {}}
+set a(0-9555) {NAME ACC1-1:slc(acc#20.psp) TYPE READSLICE PAR 0-9373 XREFS 57766 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.29544862499999996} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-9556 {}}} CYCLES {}}
+set a(0-9556) {NAME ACC1:conc#1163 TYPE CONCATENATE PAR 0-9373 XREFS 57767 LOC {1 0.14655495 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{259 0 0-9555 {}}} SUCCS {{258 0 0-9558 {}}} CYCLES {}}
+set a(0-9557) {NAME ACC1-1:slc(acc#20.psp)#10 TYPE READSLICE PAR 0-9373 XREFS 57768 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.29544862499999996} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-9558 {}}} CYCLES {}}
+set a(0-9558) {NAME ACC1:conc#1173 TYPE CONCATENATE PAR 0-9373 XREFS 57769 LOC {1 0.14655495 1 0.21596037499999998 1 0.21596037499999998 1 0.29544862499999996} PREDS {{258 0 0-9556 {}} {259 0 0-9557 {}}} SUCCS {{259 0 0-9559 {}}} CYCLES {}}
+set a(0-9559) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#356 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 57770 LOC {1 0.16702775 1 0.21596037499999998 1 0.21596037499999998 1 0.2591522701789505 1 0.33864052017895047} PREDS {{258 0 0-9554 {}} {259 0 0-9558 {}}} SUCCS {{259 0 0-9560 {}}} CYCLES {}}
+set a(0-9560) {NAME ACC1:slc#33 TYPE READSLICE PAR 0-9373 XREFS 57771 LOC {1 0.21021969999999998 1 0.25915232499999996 1 0.25915232499999996 1 0.338640575} PREDS {{259 0 0-9559 {}}} SUCCS {{258 0 0-9584 {}}} CYCLES {}}
+set a(0-9561) {NAME ACC1-1:slc(acc#20.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 57772 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-9562 {}}} CYCLES {}}
+set a(0-9562) {NAME ACC1:conc#1166 TYPE CONCATENATE PAR 0-9373 XREFS 57773 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-9561 {}}} SUCCS {{258 0 0-9568 {}}} CYCLES {}}
+set a(0-9563) {NAME ACC1-1:slc(acc#20.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 57774 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-9564 {}}} CYCLES {}}
+set a(0-9564) {NAME ACC1-1:not#261 TYPE NOT PAR 0-9373 XREFS 57775 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-9563 {}}} SUCCS {{258 0 0-9567 {}}} CYCLES {}}
+set a(0-9565) {NAME ACC1-1:slc(acc#20.psp)#7 TYPE READSLICE PAR 0-9373 XREFS 57776 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-9566 {}}} CYCLES {}}
+set a(0-9566) {NAME ACC1-1:not#263 TYPE NOT PAR 0-9373 XREFS 57777 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-9565 {}}} SUCCS {{259 0 0-9567 {}}} CYCLES {}}
+set a(0-9567) {NAME ACC1:conc#1167 TYPE CONCATENATE PAR 0-9373 XREFS 57778 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9564 {}} {259 0 0-9566 {}}} SUCCS {{259 0 0-9568 {}}} CYCLES {}}
+set a(0-9568) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#353 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57779 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.21159611008947524 1 0.29108436008947525} PREDS {{258 0 0-9562 {}} {259 0 0-9567 {}}} SUCCS {{259 0 0-9569 {}}} CYCLES {}}
+set a(0-9569) {NAME ACC1:slc#30 TYPE READSLICE PAR 0-9373 XREFS 57780 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-9568 {}}} SUCCS {{259 0 0-9570 {}}} CYCLES {}}
+set a(0-9570) {NAME ACC1:conc#1170 TYPE CONCATENATE PAR 0-9373 XREFS 57781 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-9569 {}}} SUCCS {{258 0 0-9582 {}}} CYCLES {}}
+set a(0-9571) {NAME ACC1-1:slc(acc#20.psp)#4 TYPE READSLICE PAR 0-9373 XREFS 57782 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-9572 {}}} CYCLES {}}
+set a(0-9572) {NAME ACC1:conc#1164 TYPE CONCATENATE PAR 0-9373 XREFS 57783 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-9571 {}}} SUCCS {{258 0 0-9577 {}}} CYCLES {}}
+set a(0-9573) {NAME ACC1-1:slc(acc#20.psp)#5 TYPE READSLICE PAR 0-9373 XREFS 57784 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-9574 {}}} CYCLES {}}
+set a(0-9574) {NAME ACC1-1:not#262 TYPE NOT PAR 0-9373 XREFS 57785 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{259 0 0-9573 {}}} SUCCS {{258 0 0-9576 {}}} CYCLES {}}
+set a(0-9575) {NAME ACC1-1:slc(acc#20.psp)#6 TYPE READSLICE PAR 0-9373 XREFS 57786 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-9576 {}}} CYCLES {}}
+set a(0-9576) {NAME ACC1:conc#1165 TYPE CONCATENATE PAR 0-9373 XREFS 57787 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.25030135} PREDS {{258 0 0-9574 {}} {259 0 0-9575 {}}} SUCCS {{259 0 0-9577 {}}} CYCLES {}}
+set a(0-9577) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#352 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57788 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.21159611008947524 1 0.29108436008947525} PREDS {{258 0 0-9572 {}} {259 0 0-9576 {}}} SUCCS {{259 0 0-9578 {}}} CYCLES {}}
+set a(0-9578) {NAME ACC1:slc#29 TYPE READSLICE PAR 0-9373 XREFS 57789 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-9577 {}}} SUCCS {{258 0 0-9581 {}}} CYCLES {}}
+set a(0-9579) {NAME ACC1-1:slc(acc#20.psp)#9 TYPE READSLICE PAR 0-9373 XREFS 57790 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.29108439999999997} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-9580 {}}} CYCLES {}}
+set a(0-9580) {NAME ACC1-1:not#264 TYPE NOT PAR 0-9373 XREFS 57791 LOC {1 0.14655495 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{259 0 0-9579 {}}} SUCCS {{259 0 0-9581 {}}} CYCLES {}}
+set a(0-9581) {NAME ACC1:conc#1171 TYPE CONCATENATE PAR 0-9373 XREFS 57792 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.29108439999999997} PREDS {{258 0 0-9578 {}} {259 0 0-9580 {}}} SUCCS {{259 0 0-9582 {}}} CYCLES {}}
+set a(0-9582) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#355 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 57793 LOC {1 0.187338 1 0.21159614999999998 1 0.21159614999999998 1 0.25915227707082716 1 0.33864052707082715} PREDS {{258 0 0-9570 {}} {259 0 0-9581 {}}} SUCCS {{259 0 0-9583 {}}} CYCLES {}}
+set a(0-9583) {NAME ACC1:slc#32 TYPE READSLICE PAR 0-9373 XREFS 57794 LOC {1 0.23489417499999998 1 0.25915232499999996 1 0.25915232499999996 1 0.338640575} PREDS {{259 0 0-9582 {}}} SUCCS {{259 0 0-9584 {}}} CYCLES {}}
+set a(0-9584) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1-1:acc#217 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 57795 LOC {1 0.23489417499999998 1 0.25915232499999996 1 0.25915232499999996 1 0.2921890951789505 1 0.3716773451789505} PREDS {{258 0 0-9560 {}} {259 0 0-9583 {}}} SUCCS {{259 0 0-9585 {}} {258 0 0-9587 {}} {258 0 0-9589 {}} {258 0 0-9593 {}} {258 0 0-10353 {}} {258 0 0-10365 {}} {258 0 0-10376 {}} {258 0 0-10379 {}}} CYCLES {}}
+set a(0-9585) {NAME ACC1-1:slc(ACC1:acc#217.psp) TYPE READSLICE PAR 0-9373 XREFS 57796 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{259 0 0-9584 {}}} SUCCS {{259 0 0-9586 {}}} CYCLES {}}
+set a(0-9586) {NAME ACC1:conc#1174 TYPE CONCATENATE PAR 0-9373 XREFS 57797 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{259 0 0-9585 {}}} SUCCS {{258 0 0-9591 {}}} CYCLES {}}
+set a(0-9587) {NAME ACC1-1:slc(ACC1:acc#217.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 57798 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{258 0 0-9584 {}}} SUCCS {{259 0 0-9588 {}}} CYCLES {}}
+set a(0-9588) {NAME ACC1-1:not#287 TYPE NOT PAR 0-9373 XREFS 57799 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{259 0 0-9587 {}}} SUCCS {{258 0 0-9590 {}}} CYCLES {}}
+set a(0-9589) {NAME ACC1-1:slc(ACC1:acc#217.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 57800 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{258 0 0-9584 {}}} SUCCS {{259 0 0-9590 {}}} CYCLES {}}
+set a(0-9590) {NAME ACC1:conc#1175 TYPE CONCATENATE PAR 0-9373 XREFS 57801 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3716774} PREDS {{258 0 0-9588 {}} {259 0 0-9589 {}}} SUCCS {{259 0 0-9591 {}}} CYCLES {}}
+set a(0-9591) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#357 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57802 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.3329721600894753 1 0.4124604100894752} PREDS {{258 0 0-9586 {}} {259 0 0-9590 {}}} SUCCS {{259 0 0-9592 {}}} CYCLES {}}
+set a(0-9592) {NAME ACC1:slc#34 TYPE READSLICE PAR 0-9373 XREFS 57803 LOC {1 0.30871404999999996 1 0.3329722 1 0.3329722 1 0.41246045} PREDS {{259 0 0-9591 {}}} SUCCS {{258 0 0-9595 {}}} CYCLES {}}
+set a(0-9593) {NAME ACC1-1:slc(ACC1:acc#217.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 57804 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.41246045} PREDS {{258 0 0-9584 {}}} SUCCS {{259 0 0-9594 {}}} CYCLES {}}
+set a(0-9594) {NAME ACC1-1:not#306 TYPE NOT PAR 0-9373 XREFS 57805 LOC {1 0.267931 1 0.3329722 1 0.3329722 1 0.41246045} PREDS {{259 0 0-9593 {}}} SUCCS {{259 0 0-9595 {}}} CYCLES {}}
+set a(0-9595) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-1:acc#223 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 57806 LOC {1 0.30871404999999996 1 0.3329722 1 0.3329722 1 0.35344496008947524 1 0.4329332100894752} PREDS {{258 0 0-9592 {}} {259 0 0-9594 {}}} SUCCS {{259 0 0-9596 {}} {258 0 0-9599 {}} {258 0 0-10370 {}}} CYCLES {}}
+set a(0-9596) {NAME ACC1-1:slc(ACC1:acc#223.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 57807 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-9595 {}}} SUCCS {{259 0 0-9597 {}}} CYCLES {}}
+set a(0-9597) {NAME ACC1-1:not#299 TYPE NOT PAR 0-9373 XREFS 57808 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-9596 {}}} SUCCS {{259 0 0-9598 {}}} CYCLES {}}
+set a(0-9598) {NAME ACC1:conc#1176 TYPE CONCATENATE PAR 0-9373 XREFS 57809 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-9597 {}}} SUCCS {{258 0 0-9601 {}}} CYCLES {}}
+set a(0-9599) {NAME ACC1-1:slc(ACC1:acc#223.psp) TYPE READSLICE PAR 0-9373 XREFS 57810 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{258 0 0-9595 {}}} SUCCS {{259 0 0-9600 {}}} CYCLES {}}
+set a(0-9600) {NAME ACC1:conc#1177 TYPE CONCATENATE PAR 0-9373 XREFS 57811 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.43293325} PREDS {{259 0 0-9599 {}}} SUCCS {{259 0 0-9601 {}}} CYCLES {}}
+set a(0-9601) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#358 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 57812 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.38069087707082716 1 0.4601791270708272} PREDS {{258 0 0-9598 {}} {259 0 0-9600 {}}} SUCCS {{259 0 0-9602 {}}} CYCLES {}}
+set a(0-9602) {NAME ACC1:slc#35 TYPE READSLICE PAR 0-9373 XREFS 57813 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-9601 {}}} SUCCS {{259 0 0-9603 {}} {258 0 0-9605 {}} {258 0 0-9607 {}} {258 0 0-10333 {}} {258 0 0-10344 {}}} CYCLES {}}
+set a(0-9603) {NAME ACC1-1:slc(acc.imod#18) TYPE READSLICE PAR 0-9373 XREFS 57814 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-9602 {}}} SUCCS {{259 0 0-9604 {}}} CYCLES {}}
+set a(0-9604) {NAME ACC1:conc#1179 TYPE CONCATENATE PAR 0-9373 XREFS 57815 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-9603 {}}} SUCCS {{258 0 0-9610 {}}} CYCLES {}}
+set a(0-9605) {NAME ACC1-1:slc(acc.imod#18)#1 TYPE READSLICE PAR 0-9373 XREFS 57816 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{258 0 0-9602 {}}} SUCCS {{259 0 0-9606 {}}} CYCLES {}}
+set a(0-9606) {NAME ACC1-1:not#153 TYPE NOT PAR 0-9373 XREFS 57817 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-9605 {}}} SUCCS {{258 0 0-9609 {}}} CYCLES {}}
+set a(0-9607) {NAME ACC1-1:slc(acc.imod#18)#2 TYPE READSLICE PAR 0-9373 XREFS 57818 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{258 0 0-9602 {}}} SUCCS {{259 0 0-9608 {}}} CYCLES {}}
+set a(0-9608) {NAME ACC1-1:not#154 TYPE NOT PAR 0-9373 XREFS 57819 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{259 0 0-9607 {}}} SUCCS {{259 0 0-9609 {}}} CYCLES {}}
+set a(0-9609) {NAME ACC1:conc#1180 TYPE CONCATENATE PAR 0-9373 XREFS 57820 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.460179175} PREDS {{258 0 0-9606 {}} {259 0 0-9608 {}}} SUCCS {{259 0 0-9610 {}}} CYCLES {}}
+set a(0-9610) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#359 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 57821 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.40793680207082716 1 0.4874250520708272} PREDS {{258 0 0-9604 {}} {259 0 0-9609 {}}} SUCCS {{259 0 0-9611 {}}} CYCLES {}}
+set a(0-9611) {NAME ACC1:slc#36 TYPE READSLICE PAR 0-9373 XREFS 57822 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-9610 {}}} SUCCS {{258 0 0-10321 {}} {258 0 0-10422 {}} {258 0 0-10424 {}}} CYCLES {}}
+set a(0-9612) {NAME regs.regs:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-9373 XREFS 57823 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.22517622499999998} PREDS {{258 0 0-9377 {}}} SUCCS {{258 0 0-9614 {}}} CYCLES {}}
+set a(0-9613) {NAME regs.regs:slc(regs.regs(0))#2 TYPE READSLICE PAR 0-9373 XREFS 57824 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.22517622499999998} PREDS {{258 0 0-9377 {}}} SUCCS {{259 0 0-9614 {}}} CYCLES {}}
+set a(0-9614) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#360 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 57825 LOC {1 0.0 1 0.08877639999999999 1 0.08877639999999999 1 0.15996050333641132 1 0.2963603283364113} PREDS {{258 0 0-9612 {}} {259 0 0-9613 {}}} SUCCS {{258 0 0-9616 {}}} CYCLES {}}
+set a(0-9615) {NAME regs.regs:slc(regs.regs(0)) TYPE READSLICE PAR 0-9373 XREFS 57826 LOC {1 0.0 1 0.02425815 1 0.02425815 1 0.296360375} PREDS {{258 0 0-9377 {}}} SUCCS {{259 0 0-9616 {}}} CYCLES {}}
+set a(0-9616) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-1:acc#25 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 57827 LOC {1 0.07118415 1 0.15996054999999998 1 0.15996054999999998 1 0.23533130637342836 1 0.3717311313734284} PREDS {{258 0 0-9614 {}} {259 0 0-9615 {}}} SUCCS {{259 0 0-9617 {}} {258 0 0-9620 {}} {258 0 0-9622 {}} {258 0 0-9627 {}} {258 0 0-9629 {}} {258 0 0-9633 {}} {258 0 0-9635 {}} {258 0 0-9637 {}} {258 0 0-9643 {}} {258 0 0-9645 {}} {258 0 0-9647 {}} {258 0 0-9651 {}} {258 0 0-10133 {}} {258 0 0-10134 {}} {258 0 0-10135 {}} {258 0 0-10136 {}} {258 0 0-10137 {}} {258 0 0-10151 {}} {258 0 0-10453 {}} {258 0 0-10459 {}} {258 0 0-10465 {}} {258 0 0-10495 {}} {258 0 0-10549 {}} {258 0 0-10566 {}} {258 0 0-10613 {}} {258 0 0-10616 {}} {258 0 0-10622 {}} {258 0 0-10625 {}} {258 0 0-10632 {}} {258 0 0-10635 {}} {258 0 0-10641 {}} {258 0 0-10644 {}} {258 0 0-10652 {}} {258 0 0-10655 {}} {258 0 0-10661 {}} {258 0 0-10664 {}} {258 0 0-10671 {}} {258 0 0-10674 {}} {258 0 0-10913 {}} {258 0 0-10956 {}} {258 0 0-10970 {}} {258 0 0-11016 {}} {258 0 0-11075 {}} {258 0 0-11076 {}} {258 0 0-11097 {}} {258 0 0-11391 {}} {258 0 0-11405 {}} {258 0 0-11451 {}} {258 0 0-11454 {}} {258 0 0-11463 {}} {258 0 0-11466 {}} {258 0 0-11597 {}} {258 0 0-11622 {}}} CYCLES {}}
+set a(0-9617) {NAME ACC1-1:slc(acc#25.psp)#11 TYPE READSLICE PAR 0-9373 XREFS 57828 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.39640565} PREDS {{259 0 0-9616 {}}} SUCCS {{259 0 0-9618 {}}} CYCLES {}}
+set a(0-9618) {NAME ACC1:not#313 TYPE NOT PAR 0-9373 XREFS 57829 LOC {1 0.14655495 1 0.26000582499999997 1 0.26000582499999997 1 0.39640565} PREDS {{259 0 0-9617 {}}} SUCCS {{259 0 0-9619 {}}} CYCLES {}}
+set a(0-9619) {NAME ACC1:conc#1186 TYPE CONCATENATE PAR 0-9373 XREFS 57830 LOC {1 0.14655495 1 0.26000582499999997 1 0.26000582499999997 1 0.39640565} PREDS {{259 0 0-9618 {}}} SUCCS {{258 0 0-9624 {}}} CYCLES {}}
+set a(0-9620) {NAME ACC1-1:slc(acc#25.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 57831 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.39640565} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-9621 {}}} CYCLES {}}
+set a(0-9621) {NAME ACC1-1:not#220 TYPE NOT PAR 0-9373 XREFS 57832 LOC {1 0.14655495 1 0.26000582499999997 1 0.26000582499999997 1 0.39640565} PREDS {{259 0 0-9620 {}}} SUCCS {{258 0 0-9623 {}}} CYCLES {}}
+set a(0-9622) {NAME ACC1-1:slc(acc#25.psp)#8 TYPE READSLICE PAR 0-9373 XREFS 57833 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.39640565} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-9623 {}}} CYCLES {}}
+set a(0-9623) {NAME ACC1:conc#1187 TYPE CONCATENATE PAR 0-9373 XREFS 57834 LOC {1 0.14655495 1 0.26000582499999997 1 0.26000582499999997 1 0.39640565} PREDS {{258 0 0-9621 {}} {259 0 0-9622 {}}} SUCCS {{259 0 0-9624 {}}} CYCLES {}}
+set a(0-9624) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#363 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 57835 LOC {1 0.14655495 1 0.26000582499999997 1 0.26000582499999997 1 0.2804785850894752 1 0.41687841008947524} PREDS {{258 0 0-9619 {}} {259 0 0-9623 {}}} SUCCS {{259 0 0-9625 {}}} CYCLES {}}
+set a(0-9625) {NAME ACC1:slc#39 TYPE READSLICE PAR 0-9373 XREFS 57836 LOC {1 0.16702775 1 0.280478625 1 0.280478625 1 0.41687844999999996} PREDS {{259 0 0-9624 {}}} SUCCS {{259 0 0-9626 {}}} CYCLES {}}
+set a(0-9626) {NAME ACC1:conc#1190 TYPE CONCATENATE PAR 0-9373 XREFS 57837 LOC {1 0.16702775 1 0.280478625 1 0.280478625 1 0.41687844999999996} PREDS {{259 0 0-9625 {}}} SUCCS {{258 0 0-9631 {}}} CYCLES {}}
+set a(0-9627) {NAME ACC1-1:slc(acc#25.psp) TYPE READSLICE PAR 0-9373 XREFS 57838 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.41687844999999996} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-9628 {}}} CYCLES {}}
+set a(0-9628) {NAME ACC1:conc#1181 TYPE CONCATENATE PAR 0-9373 XREFS 57839 LOC {1 0.14655495 1 0.280478625 1 0.280478625 1 0.41687844999999996} PREDS {{259 0 0-9627 {}}} SUCCS {{258 0 0-9630 {}}} CYCLES {}}
+set a(0-9629) {NAME ACC1-1:slc(acc#25.psp)#10 TYPE READSLICE PAR 0-9373 XREFS 57840 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.41687844999999996} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-9630 {}}} CYCLES {}}
+set a(0-9630) {NAME ACC1:conc#1191 TYPE CONCATENATE PAR 0-9373 XREFS 57841 LOC {1 0.14655495 1 0.280478625 1 0.280478625 1 0.41687844999999996} PREDS {{258 0 0-9628 {}} {259 0 0-9629 {}}} SUCCS {{259 0 0-9631 {}}} CYCLES {}}
+set a(0-9631) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#365 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 57842 LOC {1 0.16702775 1 0.280478625 1 0.280478625 1 0.3236705201789505 1 0.46007034517895046} PREDS {{258 0 0-9626 {}} {259 0 0-9630 {}}} SUCCS {{259 0 0-9632 {}}} CYCLES {}}
+set a(0-9632) {NAME ACC1:slc#41 TYPE READSLICE PAR 0-9373 XREFS 57843 LOC {1 0.21021969999999998 1 0.32367057499999996 1 0.32367057499999996 1 0.4600704} PREDS {{259 0 0-9631 {}}} SUCCS {{258 0 0-9656 {}}} CYCLES {}}
+set a(0-9633) {NAME ACC1-1:slc(acc#25.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 57844 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-9634 {}}} CYCLES {}}
+set a(0-9634) {NAME ACC1:conc#1184 TYPE CONCATENATE PAR 0-9373 XREFS 57845 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{259 0 0-9633 {}}} SUCCS {{258 0 0-9640 {}}} CYCLES {}}
+set a(0-9635) {NAME ACC1-1:slc(acc#25.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 57846 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-9636 {}}} CYCLES {}}
+set a(0-9636) {NAME ACC1-1:not#221 TYPE NOT PAR 0-9373 XREFS 57847 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{259 0 0-9635 {}}} SUCCS {{258 0 0-9639 {}}} CYCLES {}}
+set a(0-9637) {NAME ACC1-1:slc(acc#25.psp)#7 TYPE READSLICE PAR 0-9373 XREFS 57848 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-9638 {}}} CYCLES {}}
+set a(0-9638) {NAME ACC1-1:not#223 TYPE NOT PAR 0-9373 XREFS 57849 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{259 0 0-9637 {}}} SUCCS {{259 0 0-9639 {}}} CYCLES {}}
+set a(0-9639) {NAME ACC1:conc#1185 TYPE CONCATENATE PAR 0-9373 XREFS 57850 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-9636 {}} {259 0 0-9638 {}}} SUCCS {{259 0 0-9640 {}}} CYCLES {}}
+set a(0-9640) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#362 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57851 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.2761143600894752 1 0.41251418508947524} PREDS {{258 0 0-9634 {}} {259 0 0-9639 {}}} SUCCS {{259 0 0-9641 {}}} CYCLES {}}
+set a(0-9641) {NAME ACC1:slc#38 TYPE READSLICE PAR 0-9373 XREFS 57852 LOC {1 0.187338 1 0.2761144 1 0.2761144 1 0.41251422499999996} PREDS {{259 0 0-9640 {}}} SUCCS {{259 0 0-9642 {}}} CYCLES {}}
+set a(0-9642) {NAME ACC1:conc#1188 TYPE CONCATENATE PAR 0-9373 XREFS 57853 LOC {1 0.187338 1 0.2761144 1 0.2761144 1 0.41251422499999996} PREDS {{259 0 0-9641 {}}} SUCCS {{258 0 0-9654 {}}} CYCLES {}}
+set a(0-9643) {NAME ACC1-1:slc(acc#25.psp)#4 TYPE READSLICE PAR 0-9373 XREFS 57854 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-9644 {}}} CYCLES {}}
+set a(0-9644) {NAME ACC1:conc#1182 TYPE CONCATENATE PAR 0-9373 XREFS 57855 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{259 0 0-9643 {}}} SUCCS {{258 0 0-9649 {}}} CYCLES {}}
+set a(0-9645) {NAME ACC1-1:slc(acc#25.psp)#5 TYPE READSLICE PAR 0-9373 XREFS 57856 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-9646 {}}} CYCLES {}}
+set a(0-9646) {NAME ACC1-1:not#222 TYPE NOT PAR 0-9373 XREFS 57857 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{259 0 0-9645 {}}} SUCCS {{258 0 0-9648 {}}} CYCLES {}}
+set a(0-9647) {NAME ACC1-1:slc(acc#25.psp)#6 TYPE READSLICE PAR 0-9373 XREFS 57858 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-9648 {}}} CYCLES {}}
+set a(0-9648) {NAME ACC1:conc#1183 TYPE CONCATENATE PAR 0-9373 XREFS 57859 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.37173117499999997} PREDS {{258 0 0-9646 {}} {259 0 0-9647 {}}} SUCCS {{259 0 0-9649 {}}} CYCLES {}}
+set a(0-9649) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#361 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57860 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.2761143600894752 1 0.41251418508947524} PREDS {{258 0 0-9644 {}} {259 0 0-9648 {}}} SUCCS {{259 0 0-9650 {}}} CYCLES {}}
+set a(0-9650) {NAME ACC1:slc#37 TYPE READSLICE PAR 0-9373 XREFS 57861 LOC {1 0.187338 1 0.2761144 1 0.2761144 1 0.41251422499999996} PREDS {{259 0 0-9649 {}}} SUCCS {{258 0 0-9653 {}}} CYCLES {}}
+set a(0-9651) {NAME ACC1-1:slc(acc#25.psp)#9 TYPE READSLICE PAR 0-9373 XREFS 57862 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.41251422499999996} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-9652 {}}} CYCLES {}}
+set a(0-9652) {NAME ACC1-1:not#224 TYPE NOT PAR 0-9373 XREFS 57863 LOC {1 0.14655495 1 0.2761144 1 0.2761144 1 0.41251422499999996} PREDS {{259 0 0-9651 {}}} SUCCS {{259 0 0-9653 {}}} CYCLES {}}
+set a(0-9653) {NAME ACC1:conc#1189 TYPE CONCATENATE PAR 0-9373 XREFS 57864 LOC {1 0.187338 1 0.2761144 1 0.2761144 1 0.41251422499999996} PREDS {{258 0 0-9650 {}} {259 0 0-9652 {}}} SUCCS {{259 0 0-9654 {}}} CYCLES {}}
+set a(0-9654) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#364 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 57865 LOC {1 0.187338 1 0.2761144 1 0.2761144 1 0.32367052707082716 1 0.46007035207082714} PREDS {{258 0 0-9642 {}} {259 0 0-9653 {}}} SUCCS {{259 0 0-9655 {}}} CYCLES {}}
+set a(0-9655) {NAME ACC1:slc#40 TYPE READSLICE PAR 0-9373 XREFS 57866 LOC {1 0.23489417499999998 1 0.32367057499999996 1 0.32367057499999996 1 0.4600704} PREDS {{259 0 0-9654 {}}} SUCCS {{259 0 0-9656 {}}} CYCLES {}}
+set a(0-9656) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1-1:acc#208 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 57867 LOC {1 0.23489417499999998 1 0.32367057499999996 1 0.32367057499999996 1 0.3567073451789505 1 0.4931071701789505} PREDS {{258 0 0-9632 {}} {259 0 0-9655 {}}} SUCCS {{259 0 0-9657 {}} {258 0 0-9659 {}} {258 0 0-9661 {}} {258 0 0-9665 {}} {258 0 0-11426 {}} {258 0 0-11437 {}} {258 0 0-11446 {}} {258 0 0-11563 {}}} CYCLES {}}
+set a(0-9657) {NAME ACC1-1:slc(ACC1:acc#208.psp) TYPE READSLICE PAR 0-9373 XREFS 57868 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{259 0 0-9656 {}}} SUCCS {{259 0 0-9658 {}}} CYCLES {}}
+set a(0-9658) {NAME ACC1:conc#1192 TYPE CONCATENATE PAR 0-9373 XREFS 57869 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{259 0 0-9657 {}}} SUCCS {{258 0 0-9663 {}}} CYCLES {}}
+set a(0-9659) {NAME ACC1-1:slc(ACC1:acc#208.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 57870 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{258 0 0-9656 {}}} SUCCS {{259 0 0-9660 {}}} CYCLES {}}
+set a(0-9660) {NAME ACC1-1:not#269 TYPE NOT PAR 0-9373 XREFS 57871 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{259 0 0-9659 {}}} SUCCS {{258 0 0-9662 {}}} CYCLES {}}
+set a(0-9661) {NAME ACC1-1:slc(ACC1:acc#208.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 57872 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{258 0 0-9656 {}}} SUCCS {{259 0 0-9662 {}}} CYCLES {}}
+set a(0-9662) {NAME ACC1:conc#1193 TYPE CONCATENATE PAR 0-9373 XREFS 57873 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.493107225} PREDS {{258 0 0-9660 {}} {259 0 0-9661 {}}} SUCCS {{259 0 0-9663 {}}} CYCLES {}}
+set a(0-9663) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#366 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57874 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.3974904100894753 1 0.5338902350894752} PREDS {{258 0 0-9658 {}} {259 0 0-9662 {}}} SUCCS {{259 0 0-9664 {}}} CYCLES {}}
+set a(0-9664) {NAME ACC1:slc#42 TYPE READSLICE PAR 0-9373 XREFS 57875 LOC {1 0.30871404999999996 1 0.39749045 1 0.39749045 1 0.533890275} PREDS {{259 0 0-9663 {}}} SUCCS {{258 0 0-9667 {}}} CYCLES {}}
+set a(0-9665) {NAME ACC1-1:slc(ACC1:acc#208.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 57876 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.533890275} PREDS {{258 0 0-9656 {}}} SUCCS {{259 0 0-9666 {}}} CYCLES {}}
+set a(0-9666) {NAME ACC1:not#317 TYPE NOT PAR 0-9373 XREFS 57877 LOC {1 0.267931 1 0.39749045 1 0.39749045 1 0.533890275} PREDS {{259 0 0-9665 {}}} SUCCS {{259 0 0-9667 {}}} CYCLES {}}
+set a(0-9667) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-1:acc#219 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 57878 LOC {1 0.30871404999999996 1 0.39749045 1 0.39749045 1 0.41796321008947523 1 0.5543630350894753} PREDS {{258 0 0-9664 {}} {259 0 0-9666 {}}} SUCCS {{259 0 0-9668 {}} {258 0 0-9671 {}} {258 0 0-11595 {}}} CYCLES {}}
+set a(0-9668) {NAME ACC1-1:slc(ACC1:acc#219.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 57879 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-9667 {}}} SUCCS {{259 0 0-9669 {}}} CYCLES {}}
+set a(0-9669) {NAME ACC1-1:not#291 TYPE NOT PAR 0-9373 XREFS 57880 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-9668 {}}} SUCCS {{259 0 0-9670 {}}} CYCLES {}}
+set a(0-9670) {NAME ACC1:conc#1194 TYPE CONCATENATE PAR 0-9373 XREFS 57881 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-9669 {}}} SUCCS {{258 0 0-9673 {}}} CYCLES {}}
+set a(0-9671) {NAME ACC1-1:slc(ACC1:acc#219.psp) TYPE READSLICE PAR 0-9373 XREFS 57882 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{258 0 0-9667 {}}} SUCCS {{259 0 0-9672 {}}} CYCLES {}}
+set a(0-9672) {NAME ACC1:conc#1195 TYPE CONCATENATE PAR 0-9373 XREFS 57883 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.5543630749999999} PREDS {{259 0 0-9671 {}}} SUCCS {{259 0 0-9673 {}}} CYCLES {}}
+set a(0-9673) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#367 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 57884 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.44520912707082716 1 0.5816089520708271} PREDS {{258 0 0-9670 {}} {259 0 0-9672 {}}} SUCCS {{259 0 0-9674 {}}} CYCLES {}}
+set a(0-9674) {NAME ACC1:slc#43 TYPE READSLICE PAR 0-9373 XREFS 57885 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-9673 {}}} SUCCS {{259 0 0-9675 {}} {258 0 0-9677 {}} {258 0 0-9679 {}} {258 0 0-10475 {}} {258 0 0-11417 {}}} CYCLES {}}
+set a(0-9675) {NAME ACC1-1:slc(acc.imod#22) TYPE READSLICE PAR 0-9373 XREFS 57886 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-9674 {}}} SUCCS {{259 0 0-9676 {}}} CYCLES {}}
+set a(0-9676) {NAME ACC1:conc#1197 TYPE CONCATENATE PAR 0-9373 XREFS 57887 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-9675 {}}} SUCCS {{258 0 0-9682 {}}} CYCLES {}}
+set a(0-9677) {NAME ACC1-1:slc(acc.imod#22)#1 TYPE READSLICE PAR 0-9373 XREFS 57888 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-9674 {}}} SUCCS {{259 0 0-9678 {}}} CYCLES {}}
+set a(0-9678) {NAME ACC1-1:not#185 TYPE NOT PAR 0-9373 XREFS 57889 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-9677 {}}} SUCCS {{258 0 0-9681 {}}} CYCLES {}}
+set a(0-9679) {NAME ACC1-1:slc(acc.imod#22)#2 TYPE READSLICE PAR 0-9373 XREFS 57890 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-9674 {}}} SUCCS {{259 0 0-9680 {}}} CYCLES {}}
+set a(0-9680) {NAME ACC1-1:not#186 TYPE NOT PAR 0-9373 XREFS 57891 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-9679 {}}} SUCCS {{259 0 0-9681 {}}} CYCLES {}}
+set a(0-9681) {NAME ACC1:conc#1198 TYPE CONCATENATE PAR 0-9373 XREFS 57892 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-9678 {}} {259 0 0-9680 {}}} SUCCS {{259 0 0-9682 {}}} CYCLES {}}
+set a(0-9682) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#368 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 57893 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.47245505207082716 1 0.6088548770708271} PREDS {{258 0 0-9676 {}} {259 0 0-9681 {}}} SUCCS {{259 0 0-9683 {}}} CYCLES {}}
+set a(0-9683) {NAME ACC1:slc#44 TYPE READSLICE PAR 0-9373 XREFS 57894 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9682 {}}} SUCCS {{258 0 0-11392 {}} {258 0 0-11394 {}} {258 0 0-11404 {}}} CYCLES {}}
+set a(0-9684) {NAME regs.regs:asn TYPE ASSIGN PAR 0-9373 XREFS 57895 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-11712 {}}} SUCCS {{259 0 0-9685 {}} {256 0 0-11712 {}}} CYCLES {}}
+set a(0-9685) {NAME regs.regs:slc(regs.regs(1))#3 TYPE READSLICE PAR 0-9373 XREFS 57896 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-9684 {}}} SUCCS {{259 0 0-9686 {}}} CYCLES {}}
+set a(0-9686) {NAME ACC1:not#309 TYPE NOT PAR 0-9373 XREFS 57897 LOC {0 1.0 1 0.05572455 1 0.05572455 1 0.05572455} PREDS {{259 0 0-9685 {}}} SUCCS {{258 0 0-9690 {}}} CYCLES {}}
+set a(0-9687) {NAME regs.regs:asn#1 TYPE ASSIGN PAR 0-9373 XREFS 57898 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-11712 {}}} SUCCS {{259 0 0-9688 {}} {256 0 0-11712 {}}} CYCLES {}}
+set a(0-9688) {NAME regs.regs:slc(regs.regs(1))#4 TYPE READSLICE PAR 0-9373 XREFS 57899 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-9687 {}}} SUCCS {{259 0 0-9689 {}}} CYCLES {}}
+set a(0-9689) {NAME ACC1:not#310 TYPE NOT PAR 0-9373 XREFS 57900 LOC {0 1.0 1 0.05572455 1 0.05572455 1 0.05572455} PREDS {{259 0 0-9688 {}}} SUCCS {{259 0 0-9690 {}}} CYCLES {}}
+set a(0-9690) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#370 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 57901 LOC {1 0.0 1 0.05572455 1 0.05572455 1 0.12690865333641133 1 0.12690865333641133} PREDS {{258 0 0-9686 {}} {259 0 0-9689 {}}} SUCCS {{258 0 0-9695 {}}} CYCLES {}}
+set a(0-9691) {NAME regs.regs:asn#2 TYPE ASSIGN PAR 0-9373 XREFS 57902 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-11712 {}}} SUCCS {{259 0 0-9692 {}} {256 0 0-11712 {}}} CYCLES {}}
+set a(0-9692) {NAME regs.regs:slc(regs.regs(1))#5 TYPE READSLICE PAR 0-9373 XREFS 57903 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-9691 {}}} SUCCS {{259 0 0-9693 {}}} CYCLES {}}
+set a(0-9693) {NAME ACC1:not#311 TYPE NOT PAR 0-9373 XREFS 57904 LOC {0 1.0 1 0.05572455 1 0.05572455 1 0.05572455} PREDS {{259 0 0-9692 {}}} SUCCS {{259 0 0-9694 {}}} CYCLES {}}
+set a(0-9694) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#369 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 57905 LOC {1 0.0 1 0.05572455 1 0.05572455 1 0.12690865333641133 1 0.12690865333641133} PREDS {{259 0 0-9693 {}}} SUCCS {{259 0 0-9695 {}}} CYCLES {}}
+set a(0-9695) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1:acc#228 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 57906 LOC {1 0.07118415 1 0.12690869999999999 1 0.12690869999999999 1 0.20227945637342837 1 0.20227945637342837} PREDS {{258 0 0-9690 {}} {259 0 0-9694 {}}} SUCCS {{259 0 0-9696 {}} {258 0 0-9699 {}} {258 0 0-9701 {}} {258 0 0-9703 {}} {258 0 0-9708 {}} {258 0 0-9714 {}} {258 0 0-9716 {}} {258 0 0-9718 {}} {258 0 0-9723 {}} {258 0 0-9725 {}} {258 0 0-9729 {}} {258 0 0-10145 {}} {258 0 0-10449 {}} {258 0 0-10455 {}} {258 0 0-10461 {}} {258 0 0-10466 {}} {258 0 0-10480 {}} {258 0 0-10521 {}} {258 0 0-10533 {}} {258 0 0-10543 {}} {258 0 0-10560 {}} {258 0 0-10579 {}} {258 0 0-10600 {}} {258 0 0-10609 {}} {258 0 0-10752 {}} {258 0 0-10767 {}} {258 0 0-10891 {}} {258 0 0-10938 {}} {258 0 0-10982 {}} {258 0 0-10997 {}} {258 0 0-11046 {}} {258 0 0-11047 {}} {258 0 0-11095 {}} {258 0 0-11485 {}} {258 0 0-11487 {}} {258 0 0-11490 {}} {258 0 0-11492 {}} {258 0 0-11496 {}} {258 0 0-11498 {}} {258 0 0-11501 {}} {258 0 0-11503 {}} {258 0 0-11508 {}} {258 0 0-11510 {}} {258 0 0-11513 {}} {258 0 0-11515 {}} {258 0 0-11579 {}} {258 0 0-11616 {}} {258 0 0-11631 {}}} CYCLES {}}
+set a(0-9696) {NAME ACC1:slc(acc#5.psp#2)#1 TYPE READSLICE PAR 0-9373 XREFS 57907 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306255} PREDS {{259 0 0-9695 {}}} SUCCS {{259 0 0-9697 {}}} CYCLES {}}
+set a(0-9697) {NAME ACC1-2:not#238 TYPE NOT PAR 0-9373 XREFS 57908 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-9696 {}}} SUCCS {{259 0 0-9698 {}}} CYCLES {}}
+set a(0-9698) {NAME ACC1:conc#1206 TYPE CONCATENATE PAR 0-9373 XREFS 57909 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-9697 {}}} SUCCS {{258 0 0-9711 {}}} CYCLES {}}
+set a(0-9699) {NAME ACC1:slc(acc#5.psp#2)#2 TYPE READSLICE PAR 0-9373 XREFS 57910 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-9700 {}}} CYCLES {}}
+set a(0-9700) {NAME ACC1:conc#1202 TYPE CONCATENATE PAR 0-9373 XREFS 57911 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-9699 {}}} SUCCS {{258 0 0-9706 {}}} CYCLES {}}
+set a(0-9701) {NAME ACC1:slc(acc#5.psp#2)#3 TYPE READSLICE PAR 0-9373 XREFS 57912 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-9702 {}}} CYCLES {}}
+set a(0-9702) {NAME ACC1-2:not#239 TYPE NOT PAR 0-9373 XREFS 57913 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-9701 {}}} SUCCS {{258 0 0-9705 {}}} CYCLES {}}
+set a(0-9703) {NAME ACC1:slc(acc#5.psp#2)#7 TYPE READSLICE PAR 0-9373 XREFS 57914 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-9704 {}}} CYCLES {}}
+set a(0-9704) {NAME ACC1-2:not#241 TYPE NOT PAR 0-9373 XREFS 57915 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-9703 {}}} SUCCS {{259 0 0-9705 {}}} CYCLES {}}
+set a(0-9705) {NAME ACC1:conc#1203 TYPE CONCATENATE PAR 0-9373 XREFS 57916 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-9702 {}} {259 0 0-9704 {}}} SUCCS {{259 0 0-9706 {}}} CYCLES {}}
+set a(0-9706) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#372 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57917 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306251008947524 1 0.24306251008947524} PREDS {{258 0 0-9700 {}} {259 0 0-9705 {}}} SUCCS {{259 0 0-9707 {}}} CYCLES {}}
+set a(0-9707) {NAME ACC1:slc#46 TYPE READSLICE PAR 0-9373 XREFS 57918 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-9706 {}}} SUCCS {{258 0 0-9710 {}}} CYCLES {}}
+set a(0-9708) {NAME ACC1:slc(acc#5.psp#2)#9 TYPE READSLICE PAR 0-9373 XREFS 57919 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306255} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-9709 {}}} CYCLES {}}
+set a(0-9709) {NAME ACC1-2:not#242 TYPE NOT PAR 0-9373 XREFS 57920 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-9708 {}}} SUCCS {{259 0 0-9710 {}}} CYCLES {}}
+set a(0-9710) {NAME ACC1:conc#1207 TYPE CONCATENATE PAR 0-9373 XREFS 57921 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{258 0 0-9707 {}} {259 0 0-9709 {}}} SUCCS {{259 0 0-9711 {}}} CYCLES {}}
+set a(0-9711) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#374 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 57922 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.2760993201789505 1 0.2760993201789505} PREDS {{258 0 0-9698 {}} {259 0 0-9710 {}}} SUCCS {{259 0 0-9712 {}}} CYCLES {}}
+set a(0-9712) {NAME ACC1:slc#48 TYPE READSLICE PAR 0-9373 XREFS 57923 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-9711 {}}} SUCCS {{259 0 0-9713 {}}} CYCLES {}}
+set a(0-9713) {NAME ACC1:conc#1208 TYPE CONCATENATE PAR 0-9373 XREFS 57924 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-9712 {}}} SUCCS {{258 0 0-9731 {}}} CYCLES {}}
+set a(0-9714) {NAME ACC1:slc(acc#5.psp#2)#4 TYPE READSLICE PAR 0-9373 XREFS 57925 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-9715 {}}} CYCLES {}}
+set a(0-9715) {NAME ACC1:conc#1200 TYPE CONCATENATE PAR 0-9373 XREFS 57926 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{259 0 0-9714 {}}} SUCCS {{258 0 0-9720 {}}} CYCLES {}}
+set a(0-9716) {NAME ACC1:slc(acc#5.psp#2)#5 TYPE READSLICE PAR 0-9373 XREFS 57927 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-9717 {}}} CYCLES {}}
+set a(0-9717) {NAME ACC1-2:not#240 TYPE NOT PAR 0-9373 XREFS 57928 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{259 0 0-9716 {}}} SUCCS {{258 0 0-9719 {}}} CYCLES {}}
+set a(0-9718) {NAME ACC1:slc(acc#5.psp#2)#6 TYPE READSLICE PAR 0-9373 XREFS 57929 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-9719 {}}} CYCLES {}}
+set a(0-9719) {NAME ACC1:conc#1201 TYPE CONCATENATE PAR 0-9373 XREFS 57930 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{258 0 0-9717 {}} {259 0 0-9718 {}}} SUCCS {{259 0 0-9720 {}}} CYCLES {}}
+set a(0-9720) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#371 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57931 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.24885341008947523 1 0.24885341008947523} PREDS {{258 0 0-9715 {}} {259 0 0-9719 {}}} SUCCS {{259 0 0-9721 {}}} CYCLES {}}
+set a(0-9721) {NAME ACC1:slc#45 TYPE READSLICE PAR 0-9373 XREFS 57932 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-9720 {}}} SUCCS {{259 0 0-9722 {}}} CYCLES {}}
+set a(0-9722) {NAME ACC1:conc#1204 TYPE CONCATENATE PAR 0-9373 XREFS 57933 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-9721 {}}} SUCCS {{258 0 0-9727 {}}} CYCLES {}}
+set a(0-9723) {NAME ACC1:slc(acc#5.psp#2)#11 TYPE READSLICE PAR 0-9373 XREFS 57934 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24885344999999998} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-9724 {}}} CYCLES {}}
+set a(0-9724) {NAME ACC1-2:not#243 TYPE NOT PAR 0-9373 XREFS 57935 LOC {1 0.14655495 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-9723 {}}} SUCCS {{258 0 0-9726 {}}} CYCLES {}}
+set a(0-9725) {NAME ACC1:slc(acc#5.psp#2)#8 TYPE READSLICE PAR 0-9373 XREFS 57936 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24885344999999998} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-9726 {}}} CYCLES {}}
+set a(0-9726) {NAME ACC1:conc#1205 TYPE CONCATENATE PAR 0-9373 XREFS 57937 LOC {1 0.14655495 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{258 0 0-9724 {}} {259 0 0-9725 {}}} SUCCS {{259 0 0-9727 {}}} CYCLES {}}
+set a(0-9727) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#373 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 57938 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.2760993270708272 1 0.2760993270708272} PREDS {{258 0 0-9722 {}} {259 0 0-9726 {}}} SUCCS {{259 0 0-9728 {}}} CYCLES {}}
+set a(0-9728) {NAME ACC1:slc#47 TYPE READSLICE PAR 0-9373 XREFS 57939 LOC {1 0.21458392499999998 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-9727 {}}} SUCCS {{258 0 0-9730 {}}} CYCLES {}}
+set a(0-9729) {NAME ACC1:slc(acc#5.psp#2)#10 TYPE READSLICE PAR 0-9373 XREFS 57940 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.276099375} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-9730 {}}} CYCLES {}}
+set a(0-9730) {NAME ACC1:conc#1209 TYPE CONCATENATE PAR 0-9373 XREFS 57941 LOC {1 0.21458392499999998 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{258 0 0-9728 {}} {259 0 0-9729 {}}} SUCCS {{259 0 0-9731 {}}} CYCLES {}}
+set a(0-9731) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#375 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-9373 XREFS 57942 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.31438883449693605 1 0.31438883449693605} PREDS {{258 0 0-9713 {}} {259 0 0-9730 {}}} SUCCS {{259 0 0-9732 {}}} CYCLES {}}
+set a(0-9732) {NAME ACC1:slc#49 TYPE READSLICE PAR 0-9373 XREFS 57943 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-9731 {}}} SUCCS {{259 0 0-9733 {}} {258 0 0-9735 {}} {258 0 0-9737 {}} {258 0 0-9741 {}} {258 0 0-10778 {}} {258 0 0-10791 {}} {258 0 0-10800 {}} {258 0 0-11540 {}}} CYCLES {}}
+set a(0-9733) {NAME ACC1-2:slc(ACC1:acc#212.psp) TYPE READSLICE PAR 0-9373 XREFS 57944 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-9732 {}}} SUCCS {{259 0 0-9734 {}}} CYCLES {}}
+set a(0-9734) {NAME ACC1:conc#1210 TYPE CONCATENATE PAR 0-9373 XREFS 57945 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-9733 {}}} SUCCS {{258 0 0-9739 {}}} CYCLES {}}
+set a(0-9735) {NAME ACC1-2:slc(ACC1:acc#212.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 57946 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-9732 {}}} SUCCS {{259 0 0-9736 {}}} CYCLES {}}
+set a(0-9736) {NAME ACC1-2:not#277 TYPE NOT PAR 0-9373 XREFS 57947 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-9735 {}}} SUCCS {{258 0 0-9738 {}}} CYCLES {}}
+set a(0-9737) {NAME ACC1-2:slc(ACC1:acc#212.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 57948 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-9732 {}}} SUCCS {{259 0 0-9738 {}}} CYCLES {}}
+set a(0-9738) {NAME ACC1:conc#1211 TYPE CONCATENATE PAR 0-9373 XREFS 57949 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-9736 {}} {259 0 0-9737 {}}} SUCCS {{259 0 0-9739 {}}} CYCLES {}}
+set a(0-9739) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#376 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57950 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.3551718850894753 1 0.3551718850894753} PREDS {{258 0 0-9734 {}} {259 0 0-9738 {}}} SUCCS {{259 0 0-9740 {}}} CYCLES {}}
+set a(0-9740) {NAME ACC1:slc#50 TYPE READSLICE PAR 0-9373 XREFS 57951 LOC {1 0.29944737499999996 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-9739 {}}} SUCCS {{258 0 0-9743 {}}} CYCLES {}}
+set a(0-9741) {NAME ACC1-2:slc(ACC1:acc#212.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 57952 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.355171925} PREDS {{258 0 0-9732 {}}} SUCCS {{259 0 0-9742 {}}} CYCLES {}}
+set a(0-9742) {NAME ACC1:not#318 TYPE NOT PAR 0-9373 XREFS 57953 LOC {1 0.258664325 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-9741 {}}} SUCCS {{259 0 0-9743 {}}} CYCLES {}}
+set a(0-9743) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-2:acc#221 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 57954 LOC {1 0.29944737499999996 1 0.355171925 1 0.355171925 1 0.37564468508947524 1 0.37564468508947524} PREDS {{258 0 0-9740 {}} {259 0 0-9742 {}}} SUCCS {{259 0 0-9744 {}} {258 0 0-9747 {}} {258 0 0-11578 {}}} CYCLES {}}
+set a(0-9744) {NAME ACC1-2:slc(ACC1:acc#221.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 57955 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-9743 {}}} SUCCS {{259 0 0-9745 {}}} CYCLES {}}
+set a(0-9745) {NAME ACC1-2:not#295 TYPE NOT PAR 0-9373 XREFS 57956 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-9744 {}}} SUCCS {{259 0 0-9746 {}}} CYCLES {}}
+set a(0-9746) {NAME ACC1:conc#1212 TYPE CONCATENATE PAR 0-9373 XREFS 57957 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-9745 {}}} SUCCS {{258 0 0-9749 {}}} CYCLES {}}
+set a(0-9747) {NAME ACC1-2:slc(ACC1:acc#221.psp) TYPE READSLICE PAR 0-9373 XREFS 57958 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{258 0 0-9743 {}}} SUCCS {{259 0 0-9748 {}}} CYCLES {}}
+set a(0-9748) {NAME ACC1:conc#1213 TYPE CONCATENATE PAR 0-9373 XREFS 57959 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-9747 {}}} SUCCS {{259 0 0-9749 {}}} CYCLES {}}
+set a(0-9749) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#377 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 57960 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.40289060207082716 1 0.40289060207082716} PREDS {{258 0 0-9746 {}} {259 0 0-9748 {}}} SUCCS {{259 0 0-9750 {}}} CYCLES {}}
+set a(0-9750) {NAME ACC1:slc#51 TYPE READSLICE PAR 0-9373 XREFS 57961 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9749 {}}} SUCCS {{259 0 0-9751 {}} {258 0 0-9753 {}} {258 0 0-9755 {}} {258 0 0-10509 {}} {258 0 0-11553 {}}} CYCLES {}}
+set a(0-9751) {NAME ACC1-2:slc(acc.imod#6) TYPE READSLICE PAR 0-9373 XREFS 57962 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9750 {}}} SUCCS {{259 0 0-9752 {}}} CYCLES {}}
+set a(0-9752) {NAME ACC1:conc#1215 TYPE CONCATENATE PAR 0-9373 XREFS 57963 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9751 {}}} SUCCS {{258 0 0-9758 {}}} CYCLES {}}
+set a(0-9753) {NAME ACC1-2:slc(acc.imod#6)#1 TYPE READSLICE PAR 0-9373 XREFS 57964 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-9750 {}}} SUCCS {{259 0 0-9754 {}}} CYCLES {}}
+set a(0-9754) {NAME ACC1-2:not#57 TYPE NOT PAR 0-9373 XREFS 57965 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9753 {}}} SUCCS {{258 0 0-9757 {}}} CYCLES {}}
+set a(0-9755) {NAME ACC1-2:slc(acc.imod#6)#2 TYPE READSLICE PAR 0-9373 XREFS 57966 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-9750 {}}} SUCCS {{259 0 0-9756 {}}} CYCLES {}}
+set a(0-9756) {NAME ACC1-2:not#58 TYPE NOT PAR 0-9373 XREFS 57967 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9755 {}}} SUCCS {{259 0 0-9757 {}}} CYCLES {}}
+set a(0-9757) {NAME ACC1:conc#1216 TYPE CONCATENATE PAR 0-9373 XREFS 57968 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-9754 {}} {259 0 0-9756 {}}} SUCCS {{259 0 0-9758 {}}} CYCLES {}}
+set a(0-9758) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#378 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 57969 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.43013652707082717 1 0.43013652707082717} PREDS {{258 0 0-9752 {}} {259 0 0-9757 {}}} SUCCS {{259 0 0-9759 {}}} CYCLES {}}
+set a(0-9759) {NAME ACC1:slc#52 TYPE READSLICE PAR 0-9373 XREFS 57970 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-9758 {}}} SUCCS {{258 0 0-10753 {}} {258 0 0-10755 {}} {258 0 0-10766 {}}} CYCLES {}}
+set a(0-9760) {NAME regs.regs:asn#3 TYPE ASSIGN PAR 0-9373 XREFS 57971 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-11712 {}}} SUCCS {{259 0 0-9761 {}} {256 0 0-11712 {}}} CYCLES {}}
+set a(0-9761) {NAME regs.regs:slc(regs.regs(1))#1 TYPE READSLICE PAR 0-9373 XREFS 57972 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-9760 {}}} SUCCS {{258 0 0-9764 {}}} CYCLES {}}
+set a(0-9762) {NAME regs.regs:asn#4 TYPE ASSIGN PAR 0-9373 XREFS 57973 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-11712 {}}} SUCCS {{259 0 0-9763 {}} {256 0 0-11712 {}}} CYCLES {}}
+set a(0-9763) {NAME regs.regs:slc(regs.regs(1))#2 TYPE READSLICE PAR 0-9373 XREFS 57974 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-9762 {}}} SUCCS {{259 0 0-9764 {}}} CYCLES {}}
+set a(0-9764) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#379 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 57975 LOC {1 0.0 1 0.05572455 1 0.05572455 1 0.12690865333641133 1 0.12690865333641133} PREDS {{258 0 0-9761 {}} {259 0 0-9763 {}}} SUCCS {{258 0 0-9767 {}}} CYCLES {}}
+set a(0-9765) {NAME regs.regs:asn#5 TYPE ASSIGN PAR 0-9373 XREFS 57976 LOC {0 1.0 0 1.0 0 1.0 1 0.12690869999999999} PREDS {{262 0 0-11712 {}}} SUCCS {{259 0 0-9766 {}} {256 0 0-11712 {}}} CYCLES {}}
+set a(0-9766) {NAME regs.regs:slc(regs.regs(1)) TYPE READSLICE PAR 0-9373 XREFS 57977 LOC {0 1.0 0 1.0 0 1.0 1 0.12690869999999999} PREDS {{259 0 0-9765 {}}} SUCCS {{259 0 0-9767 {}}} CYCLES {}}
+set a(0-9767) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1:acc#226 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 57978 LOC {1 0.07118415 1 0.12690869999999999 1 0.12690869999999999 1 0.20227945637342837 1 0.20227945637342837} PREDS {{258 0 0-9764 {}} {259 0 0-9766 {}}} SUCCS {{259 0 0-9768 {}} {258 0 0-9771 {}} {258 0 0-9773 {}} {258 0 0-9775 {}} {258 0 0-9780 {}} {258 0 0-9786 {}} {258 0 0-9788 {}} {258 0 0-9790 {}} {258 0 0-9795 {}} {258 0 0-9797 {}} {258 0 0-9801 {}} {258 0 0-10147 {}} {258 0 0-10454 {}} {258 0 0-10545 {}} {258 0 0-10562 {}} {258 0 0-10573 {}} {258 0 0-10574 {}} {258 0 0-10575 {}} {258 0 0-10581 {}} {258 0 0-10685 {}} {258 0 0-10702 {}} {258 0 0-10902 {}} {258 0 0-10942 {}} {258 0 0-10950 {}} {258 0 0-10954 {}} {258 0 0-10961 {}} {258 0 0-10986 {}} {258 0 0-10993 {}} {258 0 0-11005 {}} {258 0 0-11064 {}} {258 0 0-11065 {}} {258 0 0-11211 {}} {258 0 0-11213 {}} {258 0 0-11218 {}} {258 0 0-11220 {}} {258 0 0-11223 {}} {258 0 0-11225 {}} {258 0 0-11229 {}} {258 0 0-11231 {}} {258 0 0-11234 {}} {258 0 0-11236 {}} {258 0 0-11242 {}} {258 0 0-11244 {}} {258 0 0-11247 {}} {258 0 0-11249 {}} {258 0 0-11253 {}} {258 0 0-11255 {}} {258 0 0-11258 {}} {258 0 0-11260 {}} {258 0 0-11583 {}} {258 0 0-11618 {}}} CYCLES {}}
+set a(0-9768) {NAME ACC1:slc(acc#25.psp#2)#1 TYPE READSLICE PAR 0-9373 XREFS 57979 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306255} PREDS {{259 0 0-9767 {}}} SUCCS {{259 0 0-9769 {}}} CYCLES {}}
+set a(0-9769) {NAME ACC1-2:not#220 TYPE NOT PAR 0-9373 XREFS 57980 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-9768 {}}} SUCCS {{259 0 0-9770 {}}} CYCLES {}}
+set a(0-9770) {NAME ACC1:conc#1224 TYPE CONCATENATE PAR 0-9373 XREFS 57981 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-9769 {}}} SUCCS {{258 0 0-9783 {}}} CYCLES {}}
+set a(0-9771) {NAME ACC1:slc(acc#25.psp#2)#2 TYPE READSLICE PAR 0-9373 XREFS 57982 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-9772 {}}} CYCLES {}}
+set a(0-9772) {NAME ACC1:conc#1220 TYPE CONCATENATE PAR 0-9373 XREFS 57983 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-9771 {}}} SUCCS {{258 0 0-9778 {}}} CYCLES {}}
+set a(0-9773) {NAME ACC1:slc(acc#25.psp#2)#3 TYPE READSLICE PAR 0-9373 XREFS 57984 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-9774 {}}} CYCLES {}}
+set a(0-9774) {NAME ACC1-2:not#221 TYPE NOT PAR 0-9373 XREFS 57985 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-9773 {}}} SUCCS {{258 0 0-9777 {}}} CYCLES {}}
+set a(0-9775) {NAME ACC1:slc(acc#25.psp#2)#7 TYPE READSLICE PAR 0-9373 XREFS 57986 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-9776 {}}} CYCLES {}}
+set a(0-9776) {NAME ACC1-2:not#223 TYPE NOT PAR 0-9373 XREFS 57987 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-9775 {}}} SUCCS {{259 0 0-9777 {}}} CYCLES {}}
+set a(0-9777) {NAME ACC1:conc#1221 TYPE CONCATENATE PAR 0-9373 XREFS 57988 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-9774 {}} {259 0 0-9776 {}}} SUCCS {{259 0 0-9778 {}}} CYCLES {}}
+set a(0-9778) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#381 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 57989 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306251008947524 1 0.24306251008947524} PREDS {{258 0 0-9772 {}} {259 0 0-9777 {}}} SUCCS {{259 0 0-9779 {}}} CYCLES {}}
+set a(0-9779) {NAME ACC1:slc#54 TYPE READSLICE PAR 0-9373 XREFS 57990 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-9778 {}}} SUCCS {{258 0 0-9782 {}}} CYCLES {}}
+set a(0-9780) {NAME ACC1:slc(acc#25.psp#2)#9 TYPE READSLICE PAR 0-9373 XREFS 57991 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306255} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-9781 {}}} CYCLES {}}
+set a(0-9781) {NAME ACC1-2:not#224 TYPE NOT PAR 0-9373 XREFS 57992 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-9780 {}}} SUCCS {{259 0 0-9782 {}}} CYCLES {}}
+set a(0-9782) {NAME ACC1:conc#1225 TYPE CONCATENATE PAR 0-9373 XREFS 57993 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{258 0 0-9779 {}} {259 0 0-9781 {}}} SUCCS {{259 0 0-9783 {}}} CYCLES {}}
+set a(0-9783) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#383 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 57994 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.2760993201789505 1 0.2760993201789505} PREDS {{258 0 0-9770 {}} {259 0 0-9782 {}}} SUCCS {{259 0 0-9784 {}}} CYCLES {}}
+set a(0-9784) {NAME ACC1:slc#56 TYPE READSLICE PAR 0-9373 XREFS 57995 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-9783 {}}} SUCCS {{259 0 0-9785 {}}} CYCLES {}}
+set a(0-9785) {NAME ACC1:conc#1226 TYPE CONCATENATE PAR 0-9373 XREFS 57996 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-9784 {}}} SUCCS {{258 0 0-9803 {}}} CYCLES {}}
+set a(0-9786) {NAME ACC1:slc(acc#25.psp#2)#4 TYPE READSLICE PAR 0-9373 XREFS 57997 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-9787 {}}} CYCLES {}}
+set a(0-9787) {NAME ACC1:conc#1218 TYPE CONCATENATE PAR 0-9373 XREFS 57998 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{259 0 0-9786 {}}} SUCCS {{258 0 0-9792 {}}} CYCLES {}}
+set a(0-9788) {NAME ACC1:slc(acc#25.psp#2)#5 TYPE READSLICE PAR 0-9373 XREFS 57999 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-9789 {}}} CYCLES {}}
+set a(0-9789) {NAME ACC1-2:not#222 TYPE NOT PAR 0-9373 XREFS 58000 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{259 0 0-9788 {}}} SUCCS {{258 0 0-9791 {}}} CYCLES {}}
+set a(0-9790) {NAME ACC1:slc(acc#25.psp#2)#6 TYPE READSLICE PAR 0-9373 XREFS 58001 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-9791 {}}} CYCLES {}}
+set a(0-9791) {NAME ACC1:conc#1219 TYPE CONCATENATE PAR 0-9373 XREFS 58002 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{258 0 0-9789 {}} {259 0 0-9790 {}}} SUCCS {{259 0 0-9792 {}}} CYCLES {}}
+set a(0-9792) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#380 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58003 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.24885341008947523 1 0.24885341008947523} PREDS {{258 0 0-9787 {}} {259 0 0-9791 {}}} SUCCS {{259 0 0-9793 {}}} CYCLES {}}
+set a(0-9793) {NAME ACC1:slc#53 TYPE READSLICE PAR 0-9373 XREFS 58004 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-9792 {}}} SUCCS {{259 0 0-9794 {}}} CYCLES {}}
+set a(0-9794) {NAME ACC1:conc#1222 TYPE CONCATENATE PAR 0-9373 XREFS 58005 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-9793 {}}} SUCCS {{258 0 0-9799 {}}} CYCLES {}}
+set a(0-9795) {NAME ACC1:slc(acc#25.psp#2)#11 TYPE READSLICE PAR 0-9373 XREFS 58006 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24885344999999998} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-9796 {}}} CYCLES {}}
+set a(0-9796) {NAME ACC1-2:not#225 TYPE NOT PAR 0-9373 XREFS 58007 LOC {1 0.14655495 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-9795 {}}} SUCCS {{258 0 0-9798 {}}} CYCLES {}}
+set a(0-9797) {NAME ACC1:slc(acc#25.psp#2)#8 TYPE READSLICE PAR 0-9373 XREFS 58008 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24885344999999998} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-9798 {}}} CYCLES {}}
+set a(0-9798) {NAME ACC1:conc#1223 TYPE CONCATENATE PAR 0-9373 XREFS 58009 LOC {1 0.14655495 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{258 0 0-9796 {}} {259 0 0-9797 {}}} SUCCS {{259 0 0-9799 {}}} CYCLES {}}
+set a(0-9799) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#382 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58010 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.2760993270708272 1 0.2760993270708272} PREDS {{258 0 0-9794 {}} {259 0 0-9798 {}}} SUCCS {{259 0 0-9800 {}}} CYCLES {}}
+set a(0-9800) {NAME ACC1:slc#55 TYPE READSLICE PAR 0-9373 XREFS 58011 LOC {1 0.21458392499999998 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-9799 {}}} SUCCS {{258 0 0-9802 {}}} CYCLES {}}
+set a(0-9801) {NAME ACC1:slc(acc#25.psp#2)#10 TYPE READSLICE PAR 0-9373 XREFS 58012 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.276099375} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-9802 {}}} CYCLES {}}
+set a(0-9802) {NAME ACC1:conc#1227 TYPE CONCATENATE PAR 0-9373 XREFS 58013 LOC {1 0.21458392499999998 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{258 0 0-9800 {}} {259 0 0-9801 {}}} SUCCS {{259 0 0-9803 {}}} CYCLES {}}
+set a(0-9803) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#384 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-9373 XREFS 58014 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.31438883449693605 1 0.31438883449693605} PREDS {{258 0 0-9785 {}} {259 0 0-9802 {}}} SUCCS {{259 0 0-9804 {}}} CYCLES {}}
+set a(0-9804) {NAME ACC1:slc#57 TYPE READSLICE PAR 0-9373 XREFS 58015 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-9803 {}}} SUCCS {{259 0 0-9805 {}} {258 0 0-9807 {}} {258 0 0-9809 {}} {258 0 0-9813 {}} {258 0 0-10723 {}} {258 0 0-10732 {}} {258 0 0-10743 {}} {258 0 0-11546 {}}} CYCLES {}}
+set a(0-9805) {NAME ACC1-2:slc(ACC1:acc#208.psp) TYPE READSLICE PAR 0-9373 XREFS 58016 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-9804 {}}} SUCCS {{259 0 0-9806 {}}} CYCLES {}}
+set a(0-9806) {NAME ACC1:conc#1228 TYPE CONCATENATE PAR 0-9373 XREFS 58017 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-9805 {}}} SUCCS {{258 0 0-9811 {}}} CYCLES {}}
+set a(0-9807) {NAME ACC1-2:slc(ACC1:acc#208.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 58018 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-9804 {}}} SUCCS {{259 0 0-9808 {}}} CYCLES {}}
+set a(0-9808) {NAME ACC1-2:not#269 TYPE NOT PAR 0-9373 XREFS 58019 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-9807 {}}} SUCCS {{258 0 0-9810 {}}} CYCLES {}}
+set a(0-9809) {NAME ACC1-2:slc(ACC1:acc#208.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 58020 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-9804 {}}} SUCCS {{259 0 0-9810 {}}} CYCLES {}}
+set a(0-9810) {NAME ACC1:conc#1229 TYPE CONCATENATE PAR 0-9373 XREFS 58021 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-9808 {}} {259 0 0-9809 {}}} SUCCS {{259 0 0-9811 {}}} CYCLES {}}
+set a(0-9811) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#385 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58022 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.3551718850894753 1 0.3551718850894753} PREDS {{258 0 0-9806 {}} {259 0 0-9810 {}}} SUCCS {{259 0 0-9812 {}}} CYCLES {}}
+set a(0-9812) {NAME ACC1:slc#58 TYPE READSLICE PAR 0-9373 XREFS 58023 LOC {1 0.29944737499999996 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-9811 {}}} SUCCS {{258 0 0-9815 {}}} CYCLES {}}
+set a(0-9813) {NAME ACC1-2:slc(ACC1:acc#208.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 58024 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.355171925} PREDS {{258 0 0-9804 {}}} SUCCS {{259 0 0-9814 {}}} CYCLES {}}
+set a(0-9814) {NAME ACC1:not#319 TYPE NOT PAR 0-9373 XREFS 58025 LOC {1 0.258664325 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-9813 {}}} SUCCS {{259 0 0-9815 {}}} CYCLES {}}
+set a(0-9815) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-2:acc#219 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58026 LOC {1 0.29944737499999996 1 0.355171925 1 0.355171925 1 0.37564468508947524 1 0.37564468508947524} PREDS {{258 0 0-9812 {}} {259 0 0-9814 {}}} SUCCS {{259 0 0-9816 {}} {258 0 0-9819 {}} {258 0 0-11582 {}}} CYCLES {}}
+set a(0-9816) {NAME ACC1-2:slc(ACC1:acc#219.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 58027 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-9815 {}}} SUCCS {{259 0 0-9817 {}}} CYCLES {}}
+set a(0-9817) {NAME ACC1-2:not#291 TYPE NOT PAR 0-9373 XREFS 58028 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-9816 {}}} SUCCS {{259 0 0-9818 {}}} CYCLES {}}
+set a(0-9818) {NAME ACC1:conc#1230 TYPE CONCATENATE PAR 0-9373 XREFS 58029 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-9817 {}}} SUCCS {{258 0 0-9821 {}}} CYCLES {}}
+set a(0-9819) {NAME ACC1-2:slc(ACC1:acc#219.psp) TYPE READSLICE PAR 0-9373 XREFS 58030 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{258 0 0-9815 {}}} SUCCS {{259 0 0-9820 {}}} CYCLES {}}
+set a(0-9820) {NAME ACC1:conc#1231 TYPE CONCATENATE PAR 0-9373 XREFS 58031 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-9819 {}}} SUCCS {{259 0 0-9821 {}}} CYCLES {}}
+set a(0-9821) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#386 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58032 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.40289060207082716 1 0.40289060207082716} PREDS {{258 0 0-9818 {}} {259 0 0-9820 {}}} SUCCS {{259 0 0-9822 {}}} CYCLES {}}
+set a(0-9822) {NAME ACC1:slc#59 TYPE READSLICE PAR 0-9373 XREFS 58033 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9821 {}}} SUCCS {{259 0 0-9823 {}} {258 0 0-9825 {}} {258 0 0-9827 {}} {258 0 0-10713 {}} {258 0 0-11560 {}}} CYCLES {}}
+set a(0-9823) {NAME ACC1-2:slc(acc.imod#22) TYPE READSLICE PAR 0-9373 XREFS 58034 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9822 {}}} SUCCS {{259 0 0-9824 {}}} CYCLES {}}
+set a(0-9824) {NAME ACC1:conc#1233 TYPE CONCATENATE PAR 0-9373 XREFS 58035 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9823 {}}} SUCCS {{258 0 0-9830 {}}} CYCLES {}}
+set a(0-9825) {NAME ACC1-2:slc(acc.imod#22)#1 TYPE READSLICE PAR 0-9373 XREFS 58036 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-9822 {}}} SUCCS {{259 0 0-9826 {}}} CYCLES {}}
+set a(0-9826) {NAME ACC1-2:not#185 TYPE NOT PAR 0-9373 XREFS 58037 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9825 {}}} SUCCS {{258 0 0-9829 {}}} CYCLES {}}
+set a(0-9827) {NAME ACC1-2:slc(acc.imod#22)#2 TYPE READSLICE PAR 0-9373 XREFS 58038 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-9822 {}}} SUCCS {{259 0 0-9828 {}}} CYCLES {}}
+set a(0-9828) {NAME ACC1-2:not#186 TYPE NOT PAR 0-9373 XREFS 58039 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9827 {}}} SUCCS {{259 0 0-9829 {}}} CYCLES {}}
+set a(0-9829) {NAME ACC1:conc#1234 TYPE CONCATENATE PAR 0-9373 XREFS 58040 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-9826 {}} {259 0 0-9828 {}}} SUCCS {{259 0 0-9830 {}}} CYCLES {}}
+set a(0-9830) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#387 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58041 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.43013652707082717 1 0.43013652707082717} PREDS {{258 0 0-9824 {}} {259 0 0-9829 {}}} SUCCS {{259 0 0-9831 {}}} CYCLES {}}
+set a(0-9831) {NAME ACC1:slc#60 TYPE READSLICE PAR 0-9373 XREFS 58042 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-9830 {}}} SUCCS {{258 0 0-10686 {}} {258 0 0-10688 {}} {258 0 0-10701 {}}} CYCLES {}}
+set a(0-9832) {NAME regs.regs:asn#6 TYPE ASSIGN PAR 0-9373 XREFS 58043 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{262 0 0-11713 {}}} SUCCS {{259 0 0-9833 {}} {256 0 0-11713 {}}} CYCLES {}}
+set a(0-9833) {NAME regs.regs:slc(regs.regs(2))#7 TYPE READSLICE PAR 0-9373 XREFS 58044 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{259 0 0-9832 {}}} SUCCS {{258 0 0-9836 {}}} CYCLES {}}
+set a(0-9834) {NAME regs.regs:asn#7 TYPE ASSIGN PAR 0-9373 XREFS 58045 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{262 0 0-11713 {}}} SUCCS {{259 0 0-9835 {}} {256 0 0-11713 {}}} CYCLES {}}
+set a(0-9835) {NAME regs.regs:slc(regs.regs(2))#8 TYPE READSLICE PAR 0-9373 XREFS 58046 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{259 0 0-9834 {}}} SUCCS {{259 0 0-9836 {}}} CYCLES {}}
+set a(0-9836) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#388 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 58047 LOC {1 0.0 1 0.046457874999999996 1 0.046457874999999996 1 0.11764197833641131 1 0.11764197833641131} PREDS {{258 0 0-9833 {}} {259 0 0-9835 {}}} SUCCS {{258 0 0-9839 {}}} CYCLES {}}
+set a(0-9837) {NAME regs.regs:asn#8 TYPE ASSIGN PAR 0-9373 XREFS 58048 LOC {0 1.0 0 1.0 0 1.0 1 0.117642025} PREDS {{262 0 0-11713 {}}} SUCCS {{259 0 0-9838 {}} {256 0 0-11713 {}}} CYCLES {}}
+set a(0-9838) {NAME regs.regs:slc(regs.regs(2))#6 TYPE READSLICE PAR 0-9373 XREFS 58049 LOC {0 1.0 0 1.0 0 1.0 1 0.117642025} PREDS {{259 0 0-9837 {}}} SUCCS {{259 0 0-9839 {}}} CYCLES {}}
+set a(0-9839) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-3:acc TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 58050 LOC {1 0.07118415 1 0.117642025 1 0.117642025 1 0.19301278137342837 1 0.19301278137342837} PREDS {{258 0 0-9836 {}} {259 0 0-9838 {}}} SUCCS {{259 0 0-9840 {}} {258 0 0-9843 {}} {258 0 0-9845 {}} {258 0 0-9850 {}} {258 0 0-9852 {}} {258 0 0-9856 {}} {258 0 0-9858 {}} {258 0 0-9860 {}} {258 0 0-9866 {}} {258 0 0-9868 {}} {258 0 0-9870 {}} {258 0 0-9874 {}} {258 0 0-10141 {}} {258 0 0-10539 {}} {258 0 0-10556 {}} {258 0 0-10576 {}} {258 0 0-10586 {}} {258 0 0-10592 {}} {258 0 0-10727 {}} {258 0 0-10730 {}} {258 0 0-10738 {}} {258 0 0-10876 {}} {258 0 0-10879 {}} {258 0 0-10895 {}} {258 0 0-10903 {}} {258 0 0-10907 {}} {258 0 0-10914 {}} {258 0 0-10984 {}} {258 0 0-11011 {}} {258 0 0-11017 {}} {258 0 0-11033 {}} {258 0 0-11034 {}} {258 0 0-11287 {}} {258 0 0-11290 {}} {258 0 0-11300 {}} {258 0 0-11303 {}} {258 0 0-11309 {}} {258 0 0-11312 {}} {258 0 0-11319 {}} {258 0 0-11322 {}} {258 0 0-11328 {}} {258 0 0-11331 {}} {258 0 0-11339 {}} {258 0 0-11342 {}} {258 0 0-11524 {}} {258 0 0-11526 {}} {258 0 0-11587 {}} {258 0 0-11612 {}}} CYCLES {}}
+set a(0-9840) {NAME ACC1-3:slc(acc.psp)#11 TYPE READSLICE PAR 0-9373 XREFS 58051 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.2176873} PREDS {{259 0 0-9839 {}}} SUCCS {{259 0 0-9841 {}}} CYCLES {}}
+set a(0-9841) {NAME ACC1-3:not#302 TYPE NOT PAR 0-9373 XREFS 58052 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{259 0 0-9840 {}}} SUCCS {{259 0 0-9842 {}}} CYCLES {}}
+set a(0-9842) {NAME ACC1:conc#1240 TYPE CONCATENATE PAR 0-9373 XREFS 58053 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{259 0 0-9841 {}}} SUCCS {{258 0 0-9847 {}}} CYCLES {}}
+set a(0-9843) {NAME ACC1-3:slc(acc.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 58054 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.2176873} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-9844 {}}} CYCLES {}}
+set a(0-9844) {NAME ACC1-3:not#229 TYPE NOT PAR 0-9373 XREFS 58055 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{259 0 0-9843 {}}} SUCCS {{258 0 0-9846 {}}} CYCLES {}}
+set a(0-9845) {NAME ACC1-3:slc(acc.psp)#8 TYPE READSLICE PAR 0-9373 XREFS 58056 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.2176873} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-9846 {}}} CYCLES {}}
+set a(0-9846) {NAME ACC1:conc#1241 TYPE CONCATENATE PAR 0-9373 XREFS 58057 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{258 0 0-9844 {}} {259 0 0-9845 {}}} SUCCS {{259 0 0-9847 {}}} CYCLES {}}
+set a(0-9847) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#391 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58058 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.23816006008947524 1 0.23816006008947524} PREDS {{258 0 0-9842 {}} {259 0 0-9846 {}}} SUCCS {{259 0 0-9848 {}}} CYCLES {}}
+set a(0-9848) {NAME ACC1:slc#63 TYPE READSLICE PAR 0-9373 XREFS 58059 LOC {1 0.16702775 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{259 0 0-9847 {}}} SUCCS {{259 0 0-9849 {}}} CYCLES {}}
+set a(0-9849) {NAME ACC1:conc#1244 TYPE CONCATENATE PAR 0-9373 XREFS 58060 LOC {1 0.16702775 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{259 0 0-9848 {}}} SUCCS {{258 0 0-9854 {}}} CYCLES {}}
+set a(0-9850) {NAME ACC1-3:slc(acc.psp) TYPE READSLICE PAR 0-9373 XREFS 58061 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23816009999999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-9851 {}}} CYCLES {}}
+set a(0-9851) {NAME ACC1:conc#1235 TYPE CONCATENATE PAR 0-9373 XREFS 58062 LOC {1 0.14655495 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{259 0 0-9850 {}}} SUCCS {{258 0 0-9853 {}}} CYCLES {}}
+set a(0-9852) {NAME ACC1-3:slc(acc.psp)#10 TYPE READSLICE PAR 0-9373 XREFS 58063 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23816009999999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-9853 {}}} CYCLES {}}
+set a(0-9853) {NAME ACC1:conc#1245 TYPE CONCATENATE PAR 0-9373 XREFS 58064 LOC {1 0.14655495 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{258 0 0-9851 {}} {259 0 0-9852 {}}} SUCCS {{259 0 0-9854 {}}} CYCLES {}}
+set a(0-9854) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#393 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 58065 LOC {1 0.16702775 1 0.23816009999999999 1 0.23816009999999999 1 0.2813519951789505 1 0.2813519951789505} PREDS {{258 0 0-9849 {}} {259 0 0-9853 {}}} SUCCS {{259 0 0-9855 {}}} CYCLES {}}
+set a(0-9855) {NAME ACC1:slc#65 TYPE READSLICE PAR 0-9373 XREFS 58066 LOC {1 0.21021969999999998 1 0.28135204999999996 1 0.28135204999999996 1 0.28135204999999996} PREDS {{259 0 0-9854 {}}} SUCCS {{258 0 0-9879 {}}} CYCLES {}}
+set a(0-9856) {NAME ACC1-3:slc(acc.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 58067 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-9857 {}}} CYCLES {}}
+set a(0-9857) {NAME ACC1:conc#1238 TYPE CONCATENATE PAR 0-9373 XREFS 58068 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-9856 {}}} SUCCS {{258 0 0-9863 {}}} CYCLES {}}
+set a(0-9858) {NAME ACC1-3:slc(acc.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 58069 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-9859 {}}} CYCLES {}}
+set a(0-9859) {NAME ACC1-3:not#230 TYPE NOT PAR 0-9373 XREFS 58070 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-9858 {}}} SUCCS {{258 0 0-9862 {}}} CYCLES {}}
+set a(0-9860) {NAME ACC1-3:slc(acc.psp)#7 TYPE READSLICE PAR 0-9373 XREFS 58071 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-9861 {}}} CYCLES {}}
+set a(0-9861) {NAME ACC1-3:not#232 TYPE NOT PAR 0-9373 XREFS 58072 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-9860 {}}} SUCCS {{259 0 0-9862 {}}} CYCLES {}}
+set a(0-9862) {NAME ACC1:conc#1239 TYPE CONCATENATE PAR 0-9373 XREFS 58073 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-9859 {}} {259 0 0-9861 {}}} SUCCS {{259 0 0-9863 {}}} CYCLES {}}
+set a(0-9863) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#390 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58074 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23379583508947524 1 0.23379583508947524} PREDS {{258 0 0-9857 {}} {259 0 0-9862 {}}} SUCCS {{259 0 0-9864 {}}} CYCLES {}}
+set a(0-9864) {NAME ACC1:slc#62 TYPE READSLICE PAR 0-9373 XREFS 58075 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-9863 {}}} SUCCS {{259 0 0-9865 {}}} CYCLES {}}
+set a(0-9865) {NAME ACC1:conc#1242 TYPE CONCATENATE PAR 0-9373 XREFS 58076 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-9864 {}}} SUCCS {{258 0 0-9877 {}}} CYCLES {}}
+set a(0-9866) {NAME ACC1-3:slc(acc.psp)#4 TYPE READSLICE PAR 0-9373 XREFS 58077 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-9867 {}}} CYCLES {}}
+set a(0-9867) {NAME ACC1:conc#1236 TYPE CONCATENATE PAR 0-9373 XREFS 58078 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-9866 {}}} SUCCS {{258 0 0-9872 {}}} CYCLES {}}
+set a(0-9868) {NAME ACC1-3:slc(acc.psp)#5 TYPE READSLICE PAR 0-9373 XREFS 58079 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-9869 {}}} CYCLES {}}
+set a(0-9869) {NAME ACC1-3:not#231 TYPE NOT PAR 0-9373 XREFS 58080 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-9868 {}}} SUCCS {{258 0 0-9871 {}}} CYCLES {}}
+set a(0-9870) {NAME ACC1-3:slc(acc.psp)#6 TYPE READSLICE PAR 0-9373 XREFS 58081 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-9871 {}}} CYCLES {}}
+set a(0-9871) {NAME ACC1:conc#1237 TYPE CONCATENATE PAR 0-9373 XREFS 58082 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-9869 {}} {259 0 0-9870 {}}} SUCCS {{259 0 0-9872 {}}} CYCLES {}}
+set a(0-9872) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#389 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58083 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23379583508947524 1 0.23379583508947524} PREDS {{258 0 0-9867 {}} {259 0 0-9871 {}}} SUCCS {{259 0 0-9873 {}}} CYCLES {}}
+set a(0-9873) {NAME ACC1:slc#61 TYPE READSLICE PAR 0-9373 XREFS 58084 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-9872 {}}} SUCCS {{258 0 0-9876 {}}} CYCLES {}}
+set a(0-9874) {NAME ACC1-3:slc(acc.psp)#9 TYPE READSLICE PAR 0-9373 XREFS 58085 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.233795875} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-9875 {}}} CYCLES {}}
+set a(0-9875) {NAME ACC1-3:not#233 TYPE NOT PAR 0-9373 XREFS 58086 LOC {1 0.14655495 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-9874 {}}} SUCCS {{259 0 0-9876 {}}} CYCLES {}}
+set a(0-9876) {NAME ACC1:conc#1243 TYPE CONCATENATE PAR 0-9373 XREFS 58087 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{258 0 0-9873 {}} {259 0 0-9875 {}}} SUCCS {{259 0 0-9877 {}}} CYCLES {}}
+set a(0-9877) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#392 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58088 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.28135200207082717 1 0.28135200207082717} PREDS {{258 0 0-9865 {}} {259 0 0-9876 {}}} SUCCS {{259 0 0-9878 {}}} CYCLES {}}
+set a(0-9878) {NAME ACC1:slc#64 TYPE READSLICE PAR 0-9373 XREFS 58089 LOC {1 0.23489417499999998 1 0.28135204999999996 1 0.28135204999999996 1 0.28135204999999996} PREDS {{259 0 0-9877 {}}} SUCCS {{259 0 0-9879 {}}} CYCLES {}}
+set a(0-9879) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1-3:acc#210 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 58090 LOC {1 0.23489417499999998 1 0.28135204999999996 1 0.28135204999999996 1 0.3143888201789505 1 0.3143888201789505} PREDS {{258 0 0-9855 {}} {259 0 0-9878 {}}} SUCCS {{259 0 0-9880 {}} {258 0 0-9882 {}} {258 0 0-9884 {}} {258 0 0-9888 {}} {258 0 0-10473 {}} {258 0 0-10920 {}} {258 0 0-10933 {}} {258 0 0-10944 {}}} CYCLES {}}
+set a(0-9880) {NAME ACC1-3:slc(ACC1:acc#210.psp) TYPE READSLICE PAR 0-9373 XREFS 58091 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-9879 {}}} SUCCS {{259 0 0-9881 {}}} CYCLES {}}
+set a(0-9881) {NAME ACC1:conc#1246 TYPE CONCATENATE PAR 0-9373 XREFS 58092 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-9880 {}}} SUCCS {{258 0 0-9886 {}}} CYCLES {}}
+set a(0-9882) {NAME ACC1-3:slc(ACC1:acc#210.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 58093 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-9879 {}}} SUCCS {{259 0 0-9883 {}}} CYCLES {}}
+set a(0-9883) {NAME ACC1-3:not#273 TYPE NOT PAR 0-9373 XREFS 58094 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-9882 {}}} SUCCS {{258 0 0-9885 {}}} CYCLES {}}
+set a(0-9884) {NAME ACC1-3:slc(ACC1:acc#210.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 58095 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-9879 {}}} SUCCS {{259 0 0-9885 {}}} CYCLES {}}
+set a(0-9885) {NAME ACC1:conc#1247 TYPE CONCATENATE PAR 0-9373 XREFS 58096 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-9883 {}} {259 0 0-9884 {}}} SUCCS {{259 0 0-9886 {}}} CYCLES {}}
+set a(0-9886) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#394 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58097 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.3551718850894753 1 0.3551718850894753} PREDS {{258 0 0-9881 {}} {259 0 0-9885 {}}} SUCCS {{259 0 0-9887 {}}} CYCLES {}}
+set a(0-9887) {NAME ACC1:slc#66 TYPE READSLICE PAR 0-9373 XREFS 58098 LOC {1 0.30871404999999996 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-9886 {}}} SUCCS {{258 0 0-9890 {}}} CYCLES {}}
+set a(0-9888) {NAME ACC1-3:slc(ACC1:acc#210.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 58099 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.355171925} PREDS {{258 0 0-9879 {}}} SUCCS {{259 0 0-9889 {}}} CYCLES {}}
+set a(0-9889) {NAME ACC1-3:not#305 TYPE NOT PAR 0-9373 XREFS 58100 LOC {1 0.267931 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-9888 {}}} SUCCS {{259 0 0-9890 {}}} CYCLES {}}
+set a(0-9890) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-3:acc#220 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58101 LOC {1 0.30871404999999996 1 0.355171925 1 0.355171925 1 0.37564468508947524 1 0.37564468508947524} PREDS {{258 0 0-9887 {}} {259 0 0-9889 {}}} SUCCS {{259 0 0-9891 {}} {258 0 0-9894 {}} {258 0 0-10524 {}}} CYCLES {}}
+set a(0-9891) {NAME ACC1-3:slc(ACC1:acc#220.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 58102 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-9890 {}}} SUCCS {{259 0 0-9892 {}}} CYCLES {}}
+set a(0-9892) {NAME ACC1-3:not#293 TYPE NOT PAR 0-9373 XREFS 58103 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-9891 {}}} SUCCS {{259 0 0-9893 {}}} CYCLES {}}
+set a(0-9893) {NAME ACC1:conc#1248 TYPE CONCATENATE PAR 0-9373 XREFS 58104 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-9892 {}}} SUCCS {{258 0 0-9896 {}}} CYCLES {}}
+set a(0-9894) {NAME ACC1-3:slc(ACC1:acc#220.psp) TYPE READSLICE PAR 0-9373 XREFS 58105 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{258 0 0-9890 {}}} SUCCS {{259 0 0-9895 {}}} CYCLES {}}
+set a(0-9895) {NAME ACC1:conc#1249 TYPE CONCATENATE PAR 0-9373 XREFS 58106 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-9894 {}}} SUCCS {{259 0 0-9896 {}}} CYCLES {}}
+set a(0-9896) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#395 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58107 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.40289060207082716 1 0.40289060207082716} PREDS {{258 0 0-9893 {}} {259 0 0-9895 {}}} SUCCS {{259 0 0-9897 {}}} CYCLES {}}
+set a(0-9897) {NAME ACC1:slc#67 TYPE READSLICE PAR 0-9373 XREFS 58108 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9896 {}}} SUCCS {{259 0 0-9898 {}} {258 0 0-9900 {}} {258 0 0-9902 {}} {258 0 0-10909 {}} {258 0 0-11542 {}}} CYCLES {}}
+set a(0-9898) {NAME ACC1-3:slc(acc.imod#2) TYPE READSLICE PAR 0-9373 XREFS 58109 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9897 {}}} SUCCS {{259 0 0-9899 {}}} CYCLES {}}
+set a(0-9899) {NAME ACC1:conc#1251 TYPE CONCATENATE PAR 0-9373 XREFS 58110 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9898 {}}} SUCCS {{258 0 0-9905 {}}} CYCLES {}}
+set a(0-9900) {NAME ACC1-3:slc(acc.imod#2)#1 TYPE READSLICE PAR 0-9373 XREFS 58111 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-9897 {}}} SUCCS {{259 0 0-9901 {}}} CYCLES {}}
+set a(0-9901) {NAME ACC1-3:not#25 TYPE NOT PAR 0-9373 XREFS 58112 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9900 {}}} SUCCS {{258 0 0-9904 {}}} CYCLES {}}
+set a(0-9902) {NAME ACC1-3:slc(acc.imod#2)#2 TYPE READSLICE PAR 0-9373 XREFS 58113 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-9897 {}}} SUCCS {{259 0 0-9903 {}}} CYCLES {}}
+set a(0-9903) {NAME ACC1-3:not#26 TYPE NOT PAR 0-9373 XREFS 58114 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9902 {}}} SUCCS {{259 0 0-9904 {}}} CYCLES {}}
+set a(0-9904) {NAME ACC1:conc#1252 TYPE CONCATENATE PAR 0-9373 XREFS 58115 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-9901 {}} {259 0 0-9903 {}}} SUCCS {{259 0 0-9905 {}}} CYCLES {}}
+set a(0-9905) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#396 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58116 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.43013652707082717 1 0.43013652707082717} PREDS {{258 0 0-9899 {}} {259 0 0-9904 {}}} SUCCS {{259 0 0-9906 {}}} CYCLES {}}
+set a(0-9906) {NAME ACC1:slc#68 TYPE READSLICE PAR 0-9373 XREFS 58117 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-9905 {}}} SUCCS {{258 0 0-10880 {}} {258 0 0-10882 {}} {258 0 0-10894 {}}} CYCLES {}}
+set a(0-9907) {NAME regs.regs:asn#9 TYPE ASSIGN PAR 0-9373 XREFS 58118 LOC {0 1.0 0 1.0 0 1.0 1 0.0737038} PREDS {{262 0 0-11713 {}}} SUCCS {{259 0 0-9908 {}} {256 0 0-11713 {}}} CYCLES {}}
+set a(0-9908) {NAME regs.regs:slc(regs.regs(2)) TYPE READSLICE PAR 0-9373 XREFS 58119 LOC {0 1.0 0 1.0 0 1.0 1 0.0737038} PREDS {{259 0 0-9907 {}}} SUCCS {{259 0 0-9909 {}}} CYCLES {}}
+set a(0-9909) {NAME {regs.operator[]:not#5} TYPE NOT PAR 0-9373 XREFS 58120 LOC {0 1.0 1 0.0737038 1 0.0737038 1 0.0737038} PREDS {{259 0 0-9908 {}}} SUCCS {{258 0 0-9913 {}}} CYCLES {}}
+set a(0-9910) {NAME regs.regs:asn#10 TYPE ASSIGN PAR 0-9373 XREFS 58121 LOC {0 1.0 0 1.0 0 1.0 1 0.0737038} PREDS {{262 0 0-11713 {}}} SUCCS {{259 0 0-9911 {}} {256 0 0-11713 {}}} CYCLES {}}
+set a(0-9911) {NAME regs.regs:slc(regs.regs(2))#1 TYPE READSLICE PAR 0-9373 XREFS 58122 LOC {0 1.0 0 1.0 0 1.0 1 0.0737038} PREDS {{259 0 0-9910 {}}} SUCCS {{259 0 0-9912 {}}} CYCLES {}}
+set a(0-9912) {NAME {regs.operator[]#1:not#5} TYPE NOT PAR 0-9373 XREFS 58123 LOC {0 1.0 1 0.0737038 1 0.0737038 1 0.0737038} PREDS {{259 0 0-9911 {}}} SUCCS {{259 0 0-9913 {}}} CYCLES {}}
+set a(0-9913) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#398 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 58124 LOC {1 0.0 1 0.0737038 1 0.0737038 1 0.14488790333641133 1 0.14488790333641133} PREDS {{258 0 0-9909 {}} {259 0 0-9912 {}}} SUCCS {{258 0 0-9918 {}}} CYCLES {}}
+set a(0-9914) {NAME regs.regs:asn#11 TYPE ASSIGN PAR 0-9373 XREFS 58125 LOC {0 1.0 0 1.0 0 1.0 1 0.0737038} PREDS {{262 0 0-11713 {}}} SUCCS {{259 0 0-9915 {}} {256 0 0-11713 {}}} CYCLES {}}
+set a(0-9915) {NAME regs.regs:slc(regs.regs(2))#2 TYPE READSLICE PAR 0-9373 XREFS 58126 LOC {0 1.0 0 1.0 0 1.0 1 0.0737038} PREDS {{259 0 0-9914 {}}} SUCCS {{259 0 0-9916 {}}} CYCLES {}}
+set a(0-9916) {NAME {regs.operator[]#2:not#5} TYPE NOT PAR 0-9373 XREFS 58127 LOC {0 1.0 1 0.0737038 1 0.0737038 1 0.0737038} PREDS {{259 0 0-9915 {}}} SUCCS {{259 0 0-9917 {}}} CYCLES {}}
+set a(0-9917) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#397 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 58128 LOC {1 0.0 1 0.0737038 1 0.0737038 1 0.14488790333641133 1 0.14488790333641133} PREDS {{259 0 0-9916 {}}} SUCCS {{259 0 0-9918 {}}} CYCLES {}}
+set a(0-9918) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1:acc#227 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 58129 LOC {1 0.07118415 1 0.14488795 1 0.14488795 1 0.22025870637342837 1 0.22025870637342837} PREDS {{258 0 0-9913 {}} {259 0 0-9917 {}}} SUCCS {{259 0 0-9919 {}} {258 0 0-9922 {}} {258 0 0-9924 {}} {258 0 0-9929 {}} {258 0 0-9931 {}} {258 0 0-9935 {}} {258 0 0-9937 {}} {258 0 0-9939 {}} {258 0 0-9945 {}} {258 0 0-9947 {}} {258 0 0-9949 {}} {258 0 0-9953 {}} {258 0 0-10140 {}} {258 0 0-10156 {}} {258 0 0-10505 {}} {258 0 0-10538 {}} {258 0 0-10555 {}} {258 0 0-10591 {}} {258 0 0-10680 {}} {258 0 0-10683 {}} {258 0 0-10696 {}} {258 0 0-10699 {}} {258 0 0-10741 {}} {258 0 0-10747 {}} {258 0 0-10750 {}} {258 0 0-10761 {}} {258 0 0-10764 {}} {258 0 0-10872 {}} {258 0 0-10873 {}} {258 0 0-10877 {}} {258 0 0-10888 {}} {258 0 0-10892 {}} {258 0 0-10998 {}} {258 0 0-11006 {}} {258 0 0-11028 {}} {258 0 0-11029 {}} {258 0 0-11099 {}} {258 0 0-11101 {}} {258 0 0-11104 {}} {258 0 0-11106 {}} {258 0 0-11110 {}} {258 0 0-11112 {}} {258 0 0-11363 {}} {258 0 0-11377 {}} {258 0 0-11480 {}} {258 0 0-11519 {}} {258 0 0-11521 {}} {258 0 0-11611 {}}} CYCLES {}}
+set a(0-9919) {NAME ACC1-3:slc(acc#5.psp)#11 TYPE READSLICE PAR 0-9373 XREFS 58130 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.24493322499999998} PREDS {{259 0 0-9918 {}}} SUCCS {{259 0 0-9920 {}}} CYCLES {}}
+set a(0-9920) {NAME ACC1:not#314 TYPE NOT PAR 0-9373 XREFS 58131 LOC {1 0.14655495 1 0.24493322499999998 1 0.24493322499999998 1 0.24493322499999998} PREDS {{259 0 0-9919 {}}} SUCCS {{259 0 0-9921 {}}} CYCLES {}}
+set a(0-9921) {NAME ACC1:conc#1258 TYPE CONCATENATE PAR 0-9373 XREFS 58132 LOC {1 0.14655495 1 0.24493322499999998 1 0.24493322499999998 1 0.24493322499999998} PREDS {{259 0 0-9920 {}}} SUCCS {{258 0 0-9926 {}}} CYCLES {}}
+set a(0-9922) {NAME ACC1-3:slc(acc#5.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 58133 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.24493322499999998} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-9923 {}}} CYCLES {}}
+set a(0-9923) {NAME ACC1-3:not#238 TYPE NOT PAR 0-9373 XREFS 58134 LOC {1 0.14655495 1 0.24493322499999998 1 0.24493322499999998 1 0.24493322499999998} PREDS {{259 0 0-9922 {}}} SUCCS {{258 0 0-9925 {}}} CYCLES {}}
+set a(0-9924) {NAME ACC1-3:slc(acc#5.psp)#8 TYPE READSLICE PAR 0-9373 XREFS 58135 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.24493322499999998} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-9925 {}}} CYCLES {}}
+set a(0-9925) {NAME ACC1:conc#1259 TYPE CONCATENATE PAR 0-9373 XREFS 58136 LOC {1 0.14655495 1 0.24493322499999998 1 0.24493322499999998 1 0.24493322499999998} PREDS {{258 0 0-9923 {}} {259 0 0-9924 {}}} SUCCS {{259 0 0-9926 {}}} CYCLES {}}
+set a(0-9926) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#401 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58137 LOC {1 0.14655495 1 0.24493322499999998 1 0.24493322499999998 1 0.2654059850894752 1 0.2654059850894752} PREDS {{258 0 0-9921 {}} {259 0 0-9925 {}}} SUCCS {{259 0 0-9927 {}}} CYCLES {}}
+set a(0-9927) {NAME ACC1:slc#71 TYPE READSLICE PAR 0-9373 XREFS 58138 LOC {1 0.16702775 1 0.265406025 1 0.265406025 1 0.265406025} PREDS {{259 0 0-9926 {}}} SUCCS {{259 0 0-9928 {}}} CYCLES {}}
+set a(0-9928) {NAME ACC1:conc#1262 TYPE CONCATENATE PAR 0-9373 XREFS 58139 LOC {1 0.16702775 1 0.265406025 1 0.265406025 1 0.265406025} PREDS {{259 0 0-9927 {}}} SUCCS {{258 0 0-9933 {}}} CYCLES {}}
+set a(0-9929) {NAME ACC1-3:slc(acc#5.psp) TYPE READSLICE PAR 0-9373 XREFS 58140 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.265406025} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-9930 {}}} CYCLES {}}
+set a(0-9930) {NAME ACC1:conc#1253 TYPE CONCATENATE PAR 0-9373 XREFS 58141 LOC {1 0.14655495 1 0.265406025 1 0.265406025 1 0.265406025} PREDS {{259 0 0-9929 {}}} SUCCS {{258 0 0-9932 {}}} CYCLES {}}
+set a(0-9931) {NAME ACC1-3:slc(acc#5.psp)#10 TYPE READSLICE PAR 0-9373 XREFS 58142 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.265406025} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-9932 {}}} CYCLES {}}
+set a(0-9932) {NAME ACC1:conc#1263 TYPE CONCATENATE PAR 0-9373 XREFS 58143 LOC {1 0.14655495 1 0.265406025 1 0.265406025 1 0.265406025} PREDS {{258 0 0-9930 {}} {259 0 0-9931 {}}} SUCCS {{259 0 0-9933 {}}} CYCLES {}}
+set a(0-9933) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#403 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 58144 LOC {1 0.16702775 1 0.265406025 1 0.265406025 1 0.3085979201789505 1 0.3085979201789505} PREDS {{258 0 0-9928 {}} {259 0 0-9932 {}}} SUCCS {{259 0 0-9934 {}}} CYCLES {}}
+set a(0-9934) {NAME ACC1:slc#73 TYPE READSLICE PAR 0-9373 XREFS 58145 LOC {1 0.21021969999999998 1 0.30859797499999997 1 0.30859797499999997 1 0.30859797499999997} PREDS {{259 0 0-9933 {}}} SUCCS {{258 0 0-9958 {}}} CYCLES {}}
+set a(0-9935) {NAME ACC1-3:slc(acc#5.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 58146 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-9936 {}}} CYCLES {}}
+set a(0-9936) {NAME ACC1:conc#1256 TYPE CONCATENATE PAR 0-9373 XREFS 58147 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{259 0 0-9935 {}}} SUCCS {{258 0 0-9942 {}}} CYCLES {}}
+set a(0-9937) {NAME ACC1-3:slc(acc#5.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 58148 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-9938 {}}} CYCLES {}}
+set a(0-9938) {NAME ACC1-3:not#239 TYPE NOT PAR 0-9373 XREFS 58149 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{259 0 0-9937 {}}} SUCCS {{258 0 0-9941 {}}} CYCLES {}}
+set a(0-9939) {NAME ACC1-3:slc(acc#5.psp)#7 TYPE READSLICE PAR 0-9373 XREFS 58150 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-9940 {}}} CYCLES {}}
+set a(0-9940) {NAME ACC1-3:not#241 TYPE NOT PAR 0-9373 XREFS 58151 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{259 0 0-9939 {}}} SUCCS {{259 0 0-9941 {}}} CYCLES {}}
+set a(0-9941) {NAME ACC1:conc#1257 TYPE CONCATENATE PAR 0-9373 XREFS 58152 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-9938 {}} {259 0 0-9940 {}}} SUCCS {{259 0 0-9942 {}}} CYCLES {}}
+set a(0-9942) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#400 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58153 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.2610417600894752 1 0.2610417600894752} PREDS {{258 0 0-9936 {}} {259 0 0-9941 {}}} SUCCS {{259 0 0-9943 {}}} CYCLES {}}
+set a(0-9943) {NAME ACC1:slc#70 TYPE READSLICE PAR 0-9373 XREFS 58154 LOC {1 0.187338 1 0.2610418 1 0.2610418 1 0.2610418} PREDS {{259 0 0-9942 {}}} SUCCS {{259 0 0-9944 {}}} CYCLES {}}
+set a(0-9944) {NAME ACC1:conc#1260 TYPE CONCATENATE PAR 0-9373 XREFS 58155 LOC {1 0.187338 1 0.2610418 1 0.2610418 1 0.2610418} PREDS {{259 0 0-9943 {}}} SUCCS {{258 0 0-9956 {}}} CYCLES {}}
+set a(0-9945) {NAME ACC1-3:slc(acc#5.psp)#4 TYPE READSLICE PAR 0-9373 XREFS 58156 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-9946 {}}} CYCLES {}}
+set a(0-9946) {NAME ACC1:conc#1254 TYPE CONCATENATE PAR 0-9373 XREFS 58157 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{259 0 0-9945 {}}} SUCCS {{258 0 0-9951 {}}} CYCLES {}}
+set a(0-9947) {NAME ACC1-3:slc(acc#5.psp)#5 TYPE READSLICE PAR 0-9373 XREFS 58158 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-9948 {}}} CYCLES {}}
+set a(0-9948) {NAME ACC1-3:not#240 TYPE NOT PAR 0-9373 XREFS 58159 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{259 0 0-9947 {}}} SUCCS {{258 0 0-9950 {}}} CYCLES {}}
+set a(0-9949) {NAME ACC1-3:slc(acc#5.psp)#6 TYPE READSLICE PAR 0-9373 XREFS 58160 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-9950 {}}} CYCLES {}}
+set a(0-9950) {NAME ACC1:conc#1255 TYPE CONCATENATE PAR 0-9373 XREFS 58161 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.22025875} PREDS {{258 0 0-9948 {}} {259 0 0-9949 {}}} SUCCS {{259 0 0-9951 {}}} CYCLES {}}
+set a(0-9951) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#399 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58162 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.2610417600894752 1 0.2610417600894752} PREDS {{258 0 0-9946 {}} {259 0 0-9950 {}}} SUCCS {{259 0 0-9952 {}}} CYCLES {}}
+set a(0-9952) {NAME ACC1:slc#69 TYPE READSLICE PAR 0-9373 XREFS 58163 LOC {1 0.187338 1 0.2610418 1 0.2610418 1 0.2610418} PREDS {{259 0 0-9951 {}}} SUCCS {{258 0 0-9955 {}}} CYCLES {}}
+set a(0-9953) {NAME ACC1-3:slc(acc#5.psp)#9 TYPE READSLICE PAR 0-9373 XREFS 58164 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.2610418} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-9954 {}}} CYCLES {}}
+set a(0-9954) {NAME ACC1-3:not#242 TYPE NOT PAR 0-9373 XREFS 58165 LOC {1 0.14655495 1 0.2610418 1 0.2610418 1 0.2610418} PREDS {{259 0 0-9953 {}}} SUCCS {{259 0 0-9955 {}}} CYCLES {}}
+set a(0-9955) {NAME ACC1:conc#1261 TYPE CONCATENATE PAR 0-9373 XREFS 58166 LOC {1 0.187338 1 0.2610418 1 0.2610418 1 0.2610418} PREDS {{258 0 0-9952 {}} {259 0 0-9954 {}}} SUCCS {{259 0 0-9956 {}}} CYCLES {}}
+set a(0-9956) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#402 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58167 LOC {1 0.187338 1 0.2610418 1 0.2610418 1 0.30859792707082717 1 0.30859792707082717} PREDS {{258 0 0-9944 {}} {259 0 0-9955 {}}} SUCCS {{259 0 0-9957 {}}} CYCLES {}}
+set a(0-9957) {NAME ACC1:slc#72 TYPE READSLICE PAR 0-9373 XREFS 58168 LOC {1 0.23489417499999998 1 0.30859797499999997 1 0.30859797499999997 1 0.30859797499999997} PREDS {{259 0 0-9956 {}}} SUCCS {{259 0 0-9958 {}}} CYCLES {}}
+set a(0-9958) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1-3:acc#212 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 58169 LOC {1 0.23489417499999998 1 0.30859797499999997 1 0.30859797499999997 1 0.3416347451789505 1 0.3416347451789505} PREDS {{258 0 0-9934 {}} {259 0 0-9957 {}}} SUCCS {{259 0 0-9959 {}} {258 0 0-9961 {}} {258 0 0-9963 {}} {258 0 0-9967 {}} {258 0 0-10657 {}} {258 0 0-10666 {}} {258 0 0-10676 {}} {258 0 0-11551 {}}} CYCLES {}}
+set a(0-9959) {NAME ACC1-3:slc(ACC1:acc#212.psp) TYPE READSLICE PAR 0-9373 XREFS 58170 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.34163479999999996} PREDS {{259 0 0-9958 {}}} SUCCS {{259 0 0-9960 {}}} CYCLES {}}
+set a(0-9960) {NAME ACC1:conc#1264 TYPE CONCATENATE PAR 0-9373 XREFS 58171 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.34163479999999996} PREDS {{259 0 0-9959 {}}} SUCCS {{258 0 0-9965 {}}} CYCLES {}}
+set a(0-9961) {NAME ACC1-3:slc(ACC1:acc#212.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 58172 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.34163479999999996} PREDS {{258 0 0-9958 {}}} SUCCS {{259 0 0-9962 {}}} CYCLES {}}
+set a(0-9962) {NAME ACC1-3:not#277 TYPE NOT PAR 0-9373 XREFS 58173 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.34163479999999996} PREDS {{259 0 0-9961 {}}} SUCCS {{258 0 0-9964 {}}} CYCLES {}}
+set a(0-9963) {NAME ACC1-3:slc(ACC1:acc#212.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 58174 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.34163479999999996} PREDS {{258 0 0-9958 {}}} SUCCS {{259 0 0-9964 {}}} CYCLES {}}
+set a(0-9964) {NAME ACC1:conc#1265 TYPE CONCATENATE PAR 0-9373 XREFS 58175 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.34163479999999996} PREDS {{258 0 0-9962 {}} {259 0 0-9963 {}}} SUCCS {{259 0 0-9965 {}}} CYCLES {}}
+set a(0-9965) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#404 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58176 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.3824178100894752 1 0.3824178100894752} PREDS {{258 0 0-9960 {}} {259 0 0-9964 {}}} SUCCS {{259 0 0-9966 {}}} CYCLES {}}
+set a(0-9966) {NAME ACC1:slc#74 TYPE READSLICE PAR 0-9373 XREFS 58177 LOC {1 0.30871404999999996 1 0.38241785 1 0.38241785 1 0.38241785} PREDS {{259 0 0-9965 {}}} SUCCS {{258 0 0-9969 {}}} CYCLES {}}
+set a(0-9967) {NAME ACC1-3:slc(ACC1:acc#212.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 58178 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.38241785} PREDS {{258 0 0-9958 {}}} SUCCS {{259 0 0-9968 {}}} CYCLES {}}
+set a(0-9968) {NAME ACC1:not#320 TYPE NOT PAR 0-9373 XREFS 58179 LOC {1 0.267931 1 0.38241785 1 0.38241785 1 0.38241785} PREDS {{259 0 0-9967 {}}} SUCCS {{259 0 0-9969 {}}} CYCLES {}}
+set a(0-9969) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-3:acc#221 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58180 LOC {1 0.30871404999999996 1 0.38241785 1 0.38241785 1 0.40289061008947524 1 0.40289061008947524} PREDS {{258 0 0-9966 {}} {259 0 0-9968 {}}} SUCCS {{259 0 0-9970 {}} {258 0 0-9973 {}} {258 0 0-11574 {}}} CYCLES {}}
+set a(0-9970) {NAME ACC1-3:slc(ACC1:acc#221.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 58181 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9969 {}}} SUCCS {{259 0 0-9971 {}}} CYCLES {}}
+set a(0-9971) {NAME ACC1-3:not#295 TYPE NOT PAR 0-9373 XREFS 58182 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9970 {}}} SUCCS {{259 0 0-9972 {}}} CYCLES {}}
+set a(0-9972) {NAME ACC1:conc#1266 TYPE CONCATENATE PAR 0-9373 XREFS 58183 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9971 {}}} SUCCS {{258 0 0-9975 {}}} CYCLES {}}
+set a(0-9973) {NAME ACC1-3:slc(ACC1:acc#221.psp) TYPE READSLICE PAR 0-9373 XREFS 58184 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-9969 {}}} SUCCS {{259 0 0-9974 {}}} CYCLES {}}
+set a(0-9974) {NAME ACC1:conc#1267 TYPE CONCATENATE PAR 0-9373 XREFS 58185 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-9973 {}}} SUCCS {{259 0 0-9975 {}}} CYCLES {}}
+set a(0-9975) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#405 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58186 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.43013652707082717 1 0.43013652707082717} PREDS {{258 0 0-9972 {}} {259 0 0-9974 {}}} SUCCS {{259 0 0-9976 {}}} CYCLES {}}
+set a(0-9976) {NAME ACC1:slc#75 TYPE READSLICE PAR 0-9373 XREFS 58187 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-9975 {}}} SUCCS {{259 0 0-9977 {}} {258 0 0-9979 {}} {258 0 0-9981 {}} {258 0 0-10646 {}} {258 0 0-11565 {}}} CYCLES {}}
+set a(0-9977) {NAME ACC1-3:slc(acc.imod#6) TYPE READSLICE PAR 0-9373 XREFS 58188 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.5816089999999999} PREDS {{259 0 0-9976 {}}} SUCCS {{259 0 0-9978 {}}} CYCLES {}}
+set a(0-9978) {NAME ACC1:conc#1269 TYPE CONCATENATE PAR 0-9373 XREFS 58189 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-9977 {}}} SUCCS {{258 0 0-9984 {}}} CYCLES {}}
+set a(0-9979) {NAME ACC1-3:slc(acc.imod#6)#1 TYPE READSLICE PAR 0-9373 XREFS 58190 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.5816089999999999} PREDS {{258 0 0-9976 {}}} SUCCS {{259 0 0-9980 {}}} CYCLES {}}
+set a(0-9980) {NAME ACC1-3:not#57 TYPE NOT PAR 0-9373 XREFS 58191 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-9979 {}}} SUCCS {{258 0 0-9983 {}}} CYCLES {}}
+set a(0-9981) {NAME ACC1-3:slc(acc.imod#6)#2 TYPE READSLICE PAR 0-9373 XREFS 58192 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.5816089999999999} PREDS {{258 0 0-9976 {}}} SUCCS {{259 0 0-9982 {}}} CYCLES {}}
+set a(0-9982) {NAME ACC1-3:not#58 TYPE NOT PAR 0-9373 XREFS 58193 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{259 0 0-9981 {}}} SUCCS {{259 0 0-9983 {}}} CYCLES {}}
+set a(0-9983) {NAME ACC1:conc#1270 TYPE CONCATENATE PAR 0-9373 XREFS 58194 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.5816089999999999} PREDS {{258 0 0-9980 {}} {259 0 0-9982 {}}} SUCCS {{259 0 0-9984 {}}} CYCLES {}}
+set a(0-9984) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#406 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58195 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.47245505207082716 1 0.6088548770708271} PREDS {{258 0 0-9978 {}} {259 0 0-9983 {}}} SUCCS {{259 0 0-9985 {}}} CYCLES {}}
+set a(0-9985) {NAME ACC1:slc#76 TYPE READSLICE PAR 0-9373 XREFS 58196 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-9984 {}}} SUCCS {{258 0 0-11364 {}} {258 0 0-11366 {}} {258 0 0-11376 {}}} CYCLES {}}
+set a(0-9986) {NAME regs.regs:asn#12 TYPE ASSIGN PAR 0-9373 XREFS 58197 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-11713 {}}} SUCCS {{259 0 0-9987 {}} {256 0 0-11713 {}}} CYCLES {}}
+set a(0-9987) {NAME regs.regs:slc(regs.regs(2))#4 TYPE READSLICE PAR 0-9373 XREFS 58198 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-9986 {}}} SUCCS {{258 0 0-9990 {}}} CYCLES {}}
+set a(0-9988) {NAME regs.regs:asn#13 TYPE ASSIGN PAR 0-9373 XREFS 58199 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{262 0 0-11713 {}}} SUCCS {{259 0 0-9989 {}} {256 0 0-11713 {}}} CYCLES {}}
+set a(0-9989) {NAME regs.regs:slc(regs.regs(2))#5 TYPE READSLICE PAR 0-9373 XREFS 58200 LOC {0 1.0 0 1.0 0 1.0 1 0.05572455} PREDS {{259 0 0-9988 {}}} SUCCS {{259 0 0-9990 {}}} CYCLES {}}
+set a(0-9990) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#407 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 58201 LOC {1 0.0 1 0.05572455 1 0.05572455 1 0.12690865333641133 1 0.12690865333641133} PREDS {{258 0 0-9987 {}} {259 0 0-9989 {}}} SUCCS {{258 0 0-9993 {}}} CYCLES {}}
+set a(0-9991) {NAME regs.regs:asn#14 TYPE ASSIGN PAR 0-9373 XREFS 58202 LOC {0 1.0 0 1.0 0 1.0 1 0.12690869999999999} PREDS {{262 0 0-11713 {}}} SUCCS {{259 0 0-9992 {}} {256 0 0-11713 {}}} CYCLES {}}
+set a(0-9992) {NAME regs.regs:slc(regs.regs(2))#3 TYPE READSLICE PAR 0-9373 XREFS 58203 LOC {0 1.0 0 1.0 0 1.0 1 0.12690869999999999} PREDS {{259 0 0-9991 {}}} SUCCS {{259 0 0-9993 {}}} CYCLES {}}
+set a(0-9993) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-3:acc#224 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 58204 LOC {1 0.07118415 1 0.12690869999999999 1 0.12690869999999999 1 0.20227945637342837 1 0.20227945637342837} PREDS {{258 0 0-9990 {}} {259 0 0-9992 {}}} SUCCS {{259 0 0-9994 {}} {258 0 0-9997 {}} {258 0 0-9999 {}} {258 0 0-10001 {}} {258 0 0-10006 {}} {258 0 0-10012 {}} {258 0 0-10014 {}} {258 0 0-10016 {}} {258 0 0-10021 {}} {258 0 0-10023 {}} {258 0 0-10027 {}} {258 0 0-10138 {}} {258 0 0-10143 {}} {258 0 0-10157 {}} {258 0 0-10450 {}} {258 0 0-10514 {}} {258 0 0-10515 {}} {258 0 0-10534 {}} {258 0 0-10541 {}} {258 0 0-10558 {}} {258 0 0-10578 {}} {258 0 0-10587 {}} {258 0 0-10599 {}} {258 0 0-10610 {}} {258 0 0-10708 {}} {258 0 0-10711 {}} {258 0 0-10718 {}} {258 0 0-10721 {}} {258 0 0-10810 {}} {258 0 0-10824 {}} {258 0 0-10887 {}} {258 0 0-10918 {}} {258 0 0-10927 {}} {258 0 0-10931 {}} {258 0 0-10987 {}} {258 0 0-10991 {}} {258 0 0-10994 {}} {258 0 0-10999 {}} {258 0 0-11007 {}} {258 0 0-11012 {}} {258 0 0-11018 {}} {258 0 0-11022 {}} {258 0 0-11023 {}} {258 0 0-11041 {}} {258 0 0-11042 {}} {258 0 0-11481 {}} {258 0 0-11482 {}} {258 0 0-11614 {}}} CYCLES {}}
+set a(0-9994) {NAME ACC1-3:slc(acc#10.psp)#39 TYPE READSLICE PAR 0-9373 XREFS 58205 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306255} PREDS {{259 0 0-9993 {}}} SUCCS {{259 0 0-9995 {}}} CYCLES {}}
+set a(0-9995) {NAME ACC1-3:not#247 TYPE NOT PAR 0-9373 XREFS 58206 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-9994 {}}} SUCCS {{259 0 0-9996 {}}} CYCLES {}}
+set a(0-9996) {NAME ACC1:conc#1278 TYPE CONCATENATE PAR 0-9373 XREFS 58207 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-9995 {}}} SUCCS {{258 0 0-10009 {}}} CYCLES {}}
+set a(0-9997) {NAME ACC1-3:slc(acc#10.psp)#40 TYPE READSLICE PAR 0-9373 XREFS 58208 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-9998 {}}} CYCLES {}}
+set a(0-9998) {NAME ACC1:conc#1274 TYPE CONCATENATE PAR 0-9373 XREFS 58209 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-9997 {}}} SUCCS {{258 0 0-10004 {}}} CYCLES {}}
+set a(0-9999) {NAME ACC1-3:slc(acc#10.psp)#41 TYPE READSLICE PAR 0-9373 XREFS 58210 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10000 {}}} CYCLES {}}
+set a(0-10000) {NAME ACC1-3:not#248 TYPE NOT PAR 0-9373 XREFS 58211 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-9999 {}}} SUCCS {{258 0 0-10003 {}}} CYCLES {}}
+set a(0-10001) {NAME ACC1-3:slc(acc#10.psp)#45 TYPE READSLICE PAR 0-9373 XREFS 58212 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10002 {}}} CYCLES {}}
+set a(0-10002) {NAME ACC1-3:not#250 TYPE NOT PAR 0-9373 XREFS 58213 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{259 0 0-10001 {}}} SUCCS {{259 0 0-10003 {}}} CYCLES {}}
+set a(0-10003) {NAME ACC1:conc#1275 TYPE CONCATENATE PAR 0-9373 XREFS 58214 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2022795} PREDS {{258 0 0-10000 {}} {259 0 0-10002 {}}} SUCCS {{259 0 0-10004 {}}} CYCLES {}}
+set a(0-10004) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#409 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58215 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306251008947524 1 0.24306251008947524} PREDS {{258 0 0-9998 {}} {259 0 0-10003 {}}} SUCCS {{259 0 0-10005 {}}} CYCLES {}}
+set a(0-10005) {NAME ACC1:slc#78 TYPE READSLICE PAR 0-9373 XREFS 58216 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-10004 {}}} SUCCS {{258 0 0-10008 {}}} CYCLES {}}
+set a(0-10006) {NAME ACC1-3:slc(acc#10.psp)#47 TYPE READSLICE PAR 0-9373 XREFS 58217 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24306255} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10007 {}}} CYCLES {}}
+set a(0-10007) {NAME ACC1-3:not#251 TYPE NOT PAR 0-9373 XREFS 58218 LOC {1 0.14655495 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{259 0 0-10006 {}}} SUCCS {{259 0 0-10008 {}}} CYCLES {}}
+set a(0-10008) {NAME ACC1:conc#1279 TYPE CONCATENATE PAR 0-9373 XREFS 58219 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.24306255} PREDS {{258 0 0-10005 {}} {259 0 0-10007 {}}} SUCCS {{259 0 0-10009 {}}} CYCLES {}}
+set a(0-10009) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#411 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 58220 LOC {1 0.187338 1 0.24306255 1 0.24306255 1 0.2760993201789505 1 0.2760993201789505} PREDS {{258 0 0-9996 {}} {259 0 0-10008 {}}} SUCCS {{259 0 0-10010 {}}} CYCLES {}}
+set a(0-10010) {NAME ACC1:slc#80 TYPE READSLICE PAR 0-9373 XREFS 58221 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-10009 {}}} SUCCS {{259 0 0-10011 {}}} CYCLES {}}
+set a(0-10011) {NAME ACC1:conc#1280 TYPE CONCATENATE PAR 0-9373 XREFS 58222 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-10010 {}}} SUCCS {{258 0 0-10029 {}}} CYCLES {}}
+set a(0-10012) {NAME ACC1-3:slc(acc#10.psp)#42 TYPE READSLICE PAR 0-9373 XREFS 58223 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10013 {}}} CYCLES {}}
+set a(0-10013) {NAME ACC1:conc#1272 TYPE CONCATENATE PAR 0-9373 XREFS 58224 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{259 0 0-10012 {}}} SUCCS {{258 0 0-10018 {}}} CYCLES {}}
+set a(0-10014) {NAME ACC1-3:slc(acc#10.psp)#43 TYPE READSLICE PAR 0-9373 XREFS 58225 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10015 {}}} CYCLES {}}
+set a(0-10015) {NAME ACC1-3:not#249 TYPE NOT PAR 0-9373 XREFS 58226 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{259 0 0-10014 {}}} SUCCS {{258 0 0-10017 {}}} CYCLES {}}
+set a(0-10016) {NAME ACC1-3:slc(acc#10.psp)#44 TYPE READSLICE PAR 0-9373 XREFS 58227 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.2080704} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10017 {}}} CYCLES {}}
+set a(0-10017) {NAME ACC1:conc#1273 TYPE CONCATENATE PAR 0-9373 XREFS 58228 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.2080704} PREDS {{258 0 0-10015 {}} {259 0 0-10016 {}}} SUCCS {{259 0 0-10018 {}}} CYCLES {}}
+set a(0-10018) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#408 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58229 LOC {1 0.14655495 1 0.2080704 1 0.2080704 1 0.24885341008947523 1 0.24885341008947523} PREDS {{258 0 0-10013 {}} {259 0 0-10017 {}}} SUCCS {{259 0 0-10019 {}}} CYCLES {}}
+set a(0-10019) {NAME ACC1:slc#77 TYPE READSLICE PAR 0-9373 XREFS 58230 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-10018 {}}} SUCCS {{259 0 0-10020 {}}} CYCLES {}}
+set a(0-10020) {NAME ACC1:conc#1276 TYPE CONCATENATE PAR 0-9373 XREFS 58231 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-10019 {}}} SUCCS {{258 0 0-10025 {}}} CYCLES {}}
+set a(0-10021) {NAME ACC1-3:slc(acc#10.psp)#49 TYPE READSLICE PAR 0-9373 XREFS 58232 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24885344999999998} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10022 {}}} CYCLES {}}
+set a(0-10022) {NAME ACC1-3:not#252 TYPE NOT PAR 0-9373 XREFS 58233 LOC {1 0.14655495 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{259 0 0-10021 {}}} SUCCS {{258 0 0-10024 {}}} CYCLES {}}
+set a(0-10023) {NAME ACC1-3:slc(acc#10.psp)#46 TYPE READSLICE PAR 0-9373 XREFS 58234 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.24885344999999998} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10024 {}}} CYCLES {}}
+set a(0-10024) {NAME ACC1:conc#1277 TYPE CONCATENATE PAR 0-9373 XREFS 58235 LOC {1 0.14655495 1 0.24885344999999998 1 0.24885344999999998 1 0.24885344999999998} PREDS {{258 0 0-10022 {}} {259 0 0-10023 {}}} SUCCS {{259 0 0-10025 {}}} CYCLES {}}
+set a(0-10025) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#410 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58236 LOC {1 0.187338 1 0.24885344999999998 1 0.24885344999999998 1 0.2760993270708272 1 0.2760993270708272} PREDS {{258 0 0-10020 {}} {259 0 0-10024 {}}} SUCCS {{259 0 0-10026 {}}} CYCLES {}}
+set a(0-10026) {NAME ACC1:slc#79 TYPE READSLICE PAR 0-9373 XREFS 58237 LOC {1 0.21458392499999998 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{259 0 0-10025 {}}} SUCCS {{258 0 0-10028 {}}} CYCLES {}}
+set a(0-10027) {NAME ACC1-3:slc(acc#10.psp)#48 TYPE READSLICE PAR 0-9373 XREFS 58238 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.276099375} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10028 {}}} CYCLES {}}
+set a(0-10028) {NAME ACC1:conc#1281 TYPE CONCATENATE PAR 0-9373 XREFS 58239 LOC {1 0.21458392499999998 1 0.276099375 1 0.276099375 1 0.276099375} PREDS {{258 0 0-10026 {}} {259 0 0-10027 {}}} SUCCS {{259 0 0-10029 {}}} CYCLES {}}
+set a(0-10029) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#412 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-9373 XREFS 58240 LOC {1 0.220374825 1 0.276099375 1 0.276099375 1 0.31438883449693605 1 0.31438883449693605} PREDS {{258 0 0-10011 {}} {259 0 0-10028 {}}} SUCCS {{259 0 0-10030 {}}} CYCLES {}}
+set a(0-10030) {NAME ACC1:slc#81 TYPE READSLICE PAR 0-9373 XREFS 58241 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-10029 {}}} SUCCS {{259 0 0-10031 {}} {258 0 0-10033 {}} {258 0 0-10035 {}} {258 0 0-10039 {}} {258 0 0-10846 {}} {258 0 0-10856 {}} {258 0 0-10865 {}} {258 0 0-11533 {}}} CYCLES {}}
+set a(0-10031) {NAME ACC1-3:slc(ACC1:acc#214.psp) TYPE READSLICE PAR 0-9373 XREFS 58242 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-10030 {}}} SUCCS {{259 0 0-10032 {}}} CYCLES {}}
+set a(0-10032) {NAME ACC1:conc#1282 TYPE CONCATENATE PAR 0-9373 XREFS 58243 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-10031 {}}} SUCCS {{258 0 0-10037 {}}} CYCLES {}}
+set a(0-10033) {NAME ACC1-3:slc(ACC1:acc#214.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 58244 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-10030 {}}} SUCCS {{259 0 0-10034 {}}} CYCLES {}}
+set a(0-10034) {NAME ACC1-3:not#281 TYPE NOT PAR 0-9373 XREFS 58245 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-10033 {}}} SUCCS {{258 0 0-10036 {}}} CYCLES {}}
+set a(0-10035) {NAME ACC1-3:slc(ACC1:acc#214.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 58246 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-10030 {}}} SUCCS {{259 0 0-10036 {}}} CYCLES {}}
+set a(0-10036) {NAME ACC1:conc#1283 TYPE CONCATENATE PAR 0-9373 XREFS 58247 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-10034 {}} {259 0 0-10035 {}}} SUCCS {{259 0 0-10037 {}}} CYCLES {}}
+set a(0-10037) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#413 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58248 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.3551718850894753 1 0.3551718850894753} PREDS {{258 0 0-10032 {}} {259 0 0-10036 {}}} SUCCS {{259 0 0-10038 {}}} CYCLES {}}
+set a(0-10038) {NAME ACC1:slc#82 TYPE READSLICE PAR 0-9373 XREFS 58249 LOC {1 0.29944737499999996 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-10037 {}}} SUCCS {{258 0 0-10041 {}}} CYCLES {}}
+set a(0-10039) {NAME ACC1-3:slc(ACC1:acc#214.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 58250 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.355171925} PREDS {{258 0 0-10030 {}}} SUCCS {{259 0 0-10040 {}}} CYCLES {}}
+set a(0-10040) {NAME ACC1-3:not#303 TYPE NOT PAR 0-9373 XREFS 58251 LOC {1 0.258664325 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-10039 {}}} SUCCS {{259 0 0-10041 {}}} CYCLES {}}
+set a(0-10041) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-3:acc#225 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58252 LOC {1 0.29944737499999996 1 0.355171925 1 0.355171925 1 0.37564468508947524 1 0.37564468508947524} PREDS {{258 0 0-10038 {}} {259 0 0-10040 {}}} SUCCS {{259 0 0-10042 {}} {258 0 0-10045 {}} {258 0 0-10525 {}}} CYCLES {}}
+set a(0-10042) {NAME ACC1-3:slc(ACC1:acc#222.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 58253 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-10041 {}}} SUCCS {{259 0 0-10043 {}}} CYCLES {}}
+set a(0-10043) {NAME ACC1-3:not#297 TYPE NOT PAR 0-9373 XREFS 58254 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-10042 {}}} SUCCS {{259 0 0-10044 {}}} CYCLES {}}
+set a(0-10044) {NAME ACC1:conc#1284 TYPE CONCATENATE PAR 0-9373 XREFS 58255 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-10043 {}}} SUCCS {{258 0 0-10047 {}}} CYCLES {}}
+set a(0-10045) {NAME ACC1-3:slc(ACC1:acc#222.psp) TYPE READSLICE PAR 0-9373 XREFS 58256 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{258 0 0-10041 {}}} SUCCS {{259 0 0-10046 {}}} CYCLES {}}
+set a(0-10046) {NAME ACC1:conc#1285 TYPE CONCATENATE PAR 0-9373 XREFS 58257 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-10045 {}}} SUCCS {{259 0 0-10047 {}}} CYCLES {}}
+set a(0-10047) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#414 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58258 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.40289060207082716 1 0.40289060207082716} PREDS {{258 0 0-10044 {}} {259 0 0-10046 {}}} SUCCS {{259 0 0-10048 {}}} CYCLES {}}
+set a(0-10048) {NAME ACC1:slc#83 TYPE READSLICE PAR 0-9373 XREFS 58259 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-10047 {}}} SUCCS {{259 0 0-10049 {}} {258 0 0-10051 {}} {258 0 0-10053 {}} {258 0 0-10837 {}} {258 0 0-11548 {}}} CYCLES {}}
+set a(0-10049) {NAME ACC1-3:slc(acc.imod#10) TYPE READSLICE PAR 0-9373 XREFS 58260 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-10048 {}}} SUCCS {{259 0 0-10050 {}}} CYCLES {}}
+set a(0-10050) {NAME ACC1:conc#1287 TYPE CONCATENATE PAR 0-9373 XREFS 58261 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-10049 {}}} SUCCS {{258 0 0-10056 {}}} CYCLES {}}
+set a(0-10051) {NAME ACC1-3:slc(acc.imod#10)#1 TYPE READSLICE PAR 0-9373 XREFS 58262 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-10048 {}}} SUCCS {{259 0 0-10052 {}}} CYCLES {}}
+set a(0-10052) {NAME ACC1-3:not#89 TYPE NOT PAR 0-9373 XREFS 58263 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-10051 {}}} SUCCS {{258 0 0-10055 {}}} CYCLES {}}
+set a(0-10053) {NAME ACC1-3:slc(acc.imod#10)#2 TYPE READSLICE PAR 0-9373 XREFS 58264 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-10048 {}}} SUCCS {{259 0 0-10054 {}}} CYCLES {}}
+set a(0-10054) {NAME ACC1-3:not#90 TYPE NOT PAR 0-9373 XREFS 58265 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-10053 {}}} SUCCS {{259 0 0-10055 {}}} CYCLES {}}
+set a(0-10055) {NAME ACC1:conc#1288 TYPE CONCATENATE PAR 0-9373 XREFS 58266 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-10052 {}} {259 0 0-10054 {}}} SUCCS {{259 0 0-10056 {}}} CYCLES {}}
+set a(0-10056) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#415 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58267 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.43013652707082717 1 0.43013652707082717} PREDS {{258 0 0-10050 {}} {259 0 0-10055 {}}} SUCCS {{259 0 0-10057 {}}} CYCLES {}}
+set a(0-10057) {NAME ACC1:slc#84 TYPE READSLICE PAR 0-9373 XREFS 58268 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10056 {}}} SUCCS {{258 0 0-10811 {}} {258 0 0-10813 {}} {258 0 0-10823 {}}} CYCLES {}}
+set a(0-10058) {NAME regs.regs:asn#15 TYPE ASSIGN PAR 0-9373 XREFS 58269 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{262 0 0-11713 {}}} SUCCS {{259 0 0-10059 {}} {256 0 0-11713 {}}} CYCLES {}}
+set a(0-10059) {NAME regs.regs:slc(regs.regs(2))#10 TYPE READSLICE PAR 0-9373 XREFS 58270 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{259 0 0-10058 {}}} SUCCS {{258 0 0-10062 {}}} CYCLES {}}
+set a(0-10060) {NAME regs.regs:asn#16 TYPE ASSIGN PAR 0-9373 XREFS 58271 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{262 0 0-11713 {}}} SUCCS {{259 0 0-10061 {}} {256 0 0-11713 {}}} CYCLES {}}
+set a(0-10061) {NAME regs.regs:slc(regs.regs(2))#11 TYPE READSLICE PAR 0-9373 XREFS 58272 LOC {0 1.0 0 1.0 0 1.0 1 0.046457874999999996} PREDS {{259 0 0-10060 {}}} SUCCS {{259 0 0-10062 {}}} CYCLES {}}
+set a(0-10062) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 15 NAME ACC1:acc#416 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-9373 XREFS 58273 LOC {1 0.0 1 0.046457874999999996 1 0.046457874999999996 1 0.11764197833641131 1 0.11764197833641131} PREDS {{258 0 0-10059 {}} {259 0 0-10061 {}}} SUCCS {{258 0 0-10065 {}}} CYCLES {}}
+set a(0-10063) {NAME regs.regs:asn#17 TYPE ASSIGN PAR 0-9373 XREFS 58274 LOC {0 1.0 0 1.0 0 1.0 1 0.117642025} PREDS {{262 0 0-11713 {}}} SUCCS {{259 0 0-10064 {}} {256 0 0-11713 {}}} CYCLES {}}
+set a(0-10064) {NAME regs.regs:slc(regs.regs(2))#9 TYPE READSLICE PAR 0-9373 XREFS 58275 LOC {0 1.0 0 1.0 0 1.0 1 0.117642025} PREDS {{259 0 0-10063 {}}} SUCCS {{259 0 0-10065 {}}} CYCLES {}}
+set a(0-10065) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-3:acc#20 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 58276 LOC {1 0.07118415 1 0.117642025 1 0.117642025 1 0.19301278137342837 1 0.19301278137342837} PREDS {{258 0 0-10062 {}} {259 0 0-10064 {}}} SUCCS {{259 0 0-10066 {}} {258 0 0-10069 {}} {258 0 0-10071 {}} {258 0 0-10076 {}} {258 0 0-10078 {}} {258 0 0-10082 {}} {258 0 0-10084 {}} {258 0 0-10086 {}} {258 0 0-10092 {}} {258 0 0-10094 {}} {258 0 0-10096 {}} {258 0 0-10100 {}} {258 0 0-10464 {}} {258 0 0-10479 {}} {258 0 0-10484 {}} {258 0 0-10530 {}} {258 0 0-10531 {}} {258 0 0-10532 {}} {258 0 0-10605 {}} {258 0 0-10606 {}} {258 0 0-10607 {}} {258 0 0-10608 {}} {258 0 0-10917 {}} {258 0 0-10926 {}} {258 0 0-10930 {}} {258 0 0-10937 {}} {258 0 0-10965 {}} {258 0 0-10979 {}} {258 0 0-10980 {}} {258 0 0-10981 {}} {258 0 0-10985 {}} {258 0 0-10992 {}} {258 0 0-11052 {}} {258 0 0-11053 {}} {258 0 0-11057 {}} {258 0 0-11058 {}} {258 0 0-11090 {}} {258 0 0-11091 {}} {258 0 0-11092 {}} {258 0 0-11093 {}} {258 0 0-11094 {}} {258 0 0-11115 {}} {258 0 0-11117 {}} {258 0 0-11122 {}} {258 0 0-11124 {}} {258 0 0-11127 {}} {258 0 0-11129 {}} {258 0 0-11133 {}} {258 0 0-11135 {}} {258 0 0-11138 {}} {258 0 0-11140 {}} {258 0 0-11146 {}} {258 0 0-11148 {}} {258 0 0-11151 {}} {258 0 0-11153 {}} {258 0 0-11157 {}} {258 0 0-11159 {}} {258 0 0-11162 {}} {258 0 0-11164 {}} {258 0 0-11169 {}} {258 0 0-11171 {}} {258 0 0-11174 {}} {258 0 0-11176 {}} {258 0 0-11180 {}} {258 0 0-11182 {}} {258 0 0-11185 {}} {258 0 0-11187 {}} {258 0 0-11195 {}} {258 0 0-11197 {}} {258 0 0-11200 {}} {258 0 0-11202 {}} {258 0 0-11206 {}} {258 0 0-11208 {}} {258 0 0-11265 {}} {258 0 0-11267 {}} {258 0 0-11270 {}} {258 0 0-11273 {}} {258 0 0-11279 {}} {258 0 0-11282 {}} {258 0 0-11479 {}} {258 0 0-11627 {}} {258 0 0-11628 {}} {258 0 0-11629 {}} {258 0 0-11630 {}}} CYCLES {}}
+set a(0-10066) {NAME ACC1-3:slc(acc#20.psp)#11 TYPE READSLICE PAR 0-9373 XREFS 58277 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.2176873} PREDS {{259 0 0-10065 {}}} SUCCS {{259 0 0-10067 {}}} CYCLES {}}
+set a(0-10067) {NAME ACC1-3:not#304 TYPE NOT PAR 0-9373 XREFS 58278 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{259 0 0-10066 {}}} SUCCS {{259 0 0-10068 {}}} CYCLES {}}
+set a(0-10068) {NAME ACC1:conc#1294 TYPE CONCATENATE PAR 0-9373 XREFS 58279 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{259 0 0-10067 {}}} SUCCS {{258 0 0-10073 {}}} CYCLES {}}
+set a(0-10069) {NAME ACC1-3:slc(acc#20.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 58280 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.2176873} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-10070 {}}} CYCLES {}}
+set a(0-10070) {NAME ACC1-3:not#260 TYPE NOT PAR 0-9373 XREFS 58281 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{259 0 0-10069 {}}} SUCCS {{258 0 0-10072 {}}} CYCLES {}}
+set a(0-10071) {NAME ACC1-3:slc(acc#20.psp)#8 TYPE READSLICE PAR 0-9373 XREFS 58282 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.2176873} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-10072 {}}} CYCLES {}}
+set a(0-10072) {NAME ACC1:conc#1295 TYPE CONCATENATE PAR 0-9373 XREFS 58283 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.2176873} PREDS {{258 0 0-10070 {}} {259 0 0-10071 {}}} SUCCS {{259 0 0-10073 {}}} CYCLES {}}
+set a(0-10073) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#419 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58284 LOC {1 0.14655495 1 0.2176873 1 0.2176873 1 0.23816006008947524 1 0.23816006008947524} PREDS {{258 0 0-10068 {}} {259 0 0-10072 {}}} SUCCS {{259 0 0-10074 {}}} CYCLES {}}
+set a(0-10074) {NAME ACC1:slc#87 TYPE READSLICE PAR 0-9373 XREFS 58285 LOC {1 0.16702775 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{259 0 0-10073 {}}} SUCCS {{259 0 0-10075 {}}} CYCLES {}}
+set a(0-10075) {NAME ACC1:conc#1298 TYPE CONCATENATE PAR 0-9373 XREFS 58286 LOC {1 0.16702775 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{259 0 0-10074 {}}} SUCCS {{258 0 0-10080 {}}} CYCLES {}}
+set a(0-10076) {NAME ACC1-3:slc(acc#20.psp) TYPE READSLICE PAR 0-9373 XREFS 58287 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23816009999999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-10077 {}}} CYCLES {}}
+set a(0-10077) {NAME ACC1:conc#1289 TYPE CONCATENATE PAR 0-9373 XREFS 58288 LOC {1 0.14655495 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{259 0 0-10076 {}}} SUCCS {{258 0 0-10079 {}}} CYCLES {}}
+set a(0-10078) {NAME ACC1-3:slc(acc#20.psp)#10 TYPE READSLICE PAR 0-9373 XREFS 58289 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23816009999999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-10079 {}}} CYCLES {}}
+set a(0-10079) {NAME ACC1:conc#1299 TYPE CONCATENATE PAR 0-9373 XREFS 58290 LOC {1 0.14655495 1 0.23816009999999999 1 0.23816009999999999 1 0.23816009999999999} PREDS {{258 0 0-10077 {}} {259 0 0-10078 {}}} SUCCS {{259 0 0-10080 {}}} CYCLES {}}
+set a(0-10080) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#421 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 58291 LOC {1 0.16702775 1 0.23816009999999999 1 0.23816009999999999 1 0.2813519951789505 1 0.2813519951789505} PREDS {{258 0 0-10075 {}} {259 0 0-10079 {}}} SUCCS {{259 0 0-10081 {}}} CYCLES {}}
+set a(0-10081) {NAME ACC1:slc#89 TYPE READSLICE PAR 0-9373 XREFS 58292 LOC {1 0.21021969999999998 1 0.28135204999999996 1 0.28135204999999996 1 0.28135204999999996} PREDS {{259 0 0-10080 {}}} SUCCS {{258 0 0-10105 {}}} CYCLES {}}
+set a(0-10082) {NAME ACC1-3:slc(acc#20.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 58293 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-10083 {}}} CYCLES {}}
+set a(0-10083) {NAME ACC1:conc#1292 TYPE CONCATENATE PAR 0-9373 XREFS 58294 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-10082 {}}} SUCCS {{258 0 0-10089 {}}} CYCLES {}}
+set a(0-10084) {NAME ACC1-3:slc(acc#20.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 58295 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-10085 {}}} CYCLES {}}
+set a(0-10085) {NAME ACC1-3:not#261 TYPE NOT PAR 0-9373 XREFS 58296 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-10084 {}}} SUCCS {{258 0 0-10088 {}}} CYCLES {}}
+set a(0-10086) {NAME ACC1-3:slc(acc#20.psp)#7 TYPE READSLICE PAR 0-9373 XREFS 58297 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-10087 {}}} CYCLES {}}
+set a(0-10087) {NAME ACC1-3:not#263 TYPE NOT PAR 0-9373 XREFS 58298 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-10086 {}}} SUCCS {{259 0 0-10088 {}}} CYCLES {}}
+set a(0-10088) {NAME ACC1:conc#1293 TYPE CONCATENATE PAR 0-9373 XREFS 58299 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-10085 {}} {259 0 0-10087 {}}} SUCCS {{259 0 0-10089 {}}} CYCLES {}}
+set a(0-10089) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#418 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58300 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23379583508947524 1 0.23379583508947524} PREDS {{258 0 0-10083 {}} {259 0 0-10088 {}}} SUCCS {{259 0 0-10090 {}}} CYCLES {}}
+set a(0-10090) {NAME ACC1:slc#86 TYPE READSLICE PAR 0-9373 XREFS 58301 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-10089 {}}} SUCCS {{259 0 0-10091 {}}} CYCLES {}}
+set a(0-10091) {NAME ACC1:conc#1296 TYPE CONCATENATE PAR 0-9373 XREFS 58302 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-10090 {}}} SUCCS {{258 0 0-10103 {}}} CYCLES {}}
+set a(0-10092) {NAME ACC1-3:slc(acc#20.psp)#4 TYPE READSLICE PAR 0-9373 XREFS 58303 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-10093 {}}} CYCLES {}}
+set a(0-10093) {NAME ACC1:conc#1290 TYPE CONCATENATE PAR 0-9373 XREFS 58304 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-10092 {}}} SUCCS {{258 0 0-10098 {}}} CYCLES {}}
+set a(0-10094) {NAME ACC1-3:slc(acc#20.psp)#5 TYPE READSLICE PAR 0-9373 XREFS 58305 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-10095 {}}} CYCLES {}}
+set a(0-10095) {NAME ACC1-3:not#262 TYPE NOT PAR 0-9373 XREFS 58306 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{259 0 0-10094 {}}} SUCCS {{258 0 0-10097 {}}} CYCLES {}}
+set a(0-10096) {NAME ACC1-3:slc(acc#20.psp)#6 TYPE READSLICE PAR 0-9373 XREFS 58307 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-10097 {}}} CYCLES {}}
+set a(0-10097) {NAME ACC1:conc#1291 TYPE CONCATENATE PAR 0-9373 XREFS 58308 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.193012825} PREDS {{258 0 0-10095 {}} {259 0 0-10096 {}}} SUCCS {{259 0 0-10098 {}}} CYCLES {}}
+set a(0-10098) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#417 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58309 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.23379583508947524 1 0.23379583508947524} PREDS {{258 0 0-10093 {}} {259 0 0-10097 {}}} SUCCS {{259 0 0-10099 {}}} CYCLES {}}
+set a(0-10099) {NAME ACC1:slc#85 TYPE READSLICE PAR 0-9373 XREFS 58310 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-10098 {}}} SUCCS {{258 0 0-10102 {}}} CYCLES {}}
+set a(0-10100) {NAME ACC1-3:slc(acc#20.psp)#9 TYPE READSLICE PAR 0-9373 XREFS 58311 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.233795875} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-10101 {}}} CYCLES {}}
+set a(0-10101) {NAME ACC1-3:not#264 TYPE NOT PAR 0-9373 XREFS 58312 LOC {1 0.14655495 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{259 0 0-10100 {}}} SUCCS {{259 0 0-10102 {}}} CYCLES {}}
+set a(0-10102) {NAME ACC1:conc#1297 TYPE CONCATENATE PAR 0-9373 XREFS 58313 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.233795875} PREDS {{258 0 0-10099 {}} {259 0 0-10101 {}}} SUCCS {{259 0 0-10103 {}}} CYCLES {}}
+set a(0-10103) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#420 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58314 LOC {1 0.187338 1 0.233795875 1 0.233795875 1 0.28135200207082717 1 0.28135200207082717} PREDS {{258 0 0-10091 {}} {259 0 0-10102 {}}} SUCCS {{259 0 0-10104 {}}} CYCLES {}}
+set a(0-10104) {NAME ACC1:slc#88 TYPE READSLICE PAR 0-9373 XREFS 58315 LOC {1 0.23489417499999998 1 0.28135204999999996 1 0.28135204999999996 1 0.28135204999999996} PREDS {{259 0 0-10103 {}}} SUCCS {{259 0 0-10105 {}}} CYCLES {}}
+set a(0-10105) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1-3:acc#217 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 58316 LOC {1 0.23489417499999998 1 0.28135204999999996 1 0.28135204999999996 1 0.3143888201789505 1 0.3143888201789505} PREDS {{258 0 0-10081 {}} {259 0 0-10104 {}}} SUCCS {{259 0 0-10106 {}} {258 0 0-10108 {}} {258 0 0-10110 {}} {258 0 0-10114 {}} {258 0 0-10471 {}} {258 0 0-10941 {}} {258 0 0-10949 {}} {258 0 0-10953 {}}} CYCLES {}}
+set a(0-10106) {NAME ACC1-3:slc(ACC1:acc#217.psp) TYPE READSLICE PAR 0-9373 XREFS 58317 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-10105 {}}} SUCCS {{259 0 0-10107 {}}} CYCLES {}}
+set a(0-10107) {NAME ACC1:conc#1300 TYPE CONCATENATE PAR 0-9373 XREFS 58318 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-10106 {}}} SUCCS {{258 0 0-10112 {}}} CYCLES {}}
+set a(0-10108) {NAME ACC1-3:slc(ACC1:acc#217.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 58319 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-10105 {}}} SUCCS {{259 0 0-10109 {}}} CYCLES {}}
+set a(0-10109) {NAME ACC1-3:not#287 TYPE NOT PAR 0-9373 XREFS 58320 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{259 0 0-10108 {}}} SUCCS {{258 0 0-10111 {}}} CYCLES {}}
+set a(0-10110) {NAME ACC1-3:slc(ACC1:acc#217.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 58321 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-10105 {}}} SUCCS {{259 0 0-10111 {}}} CYCLES {}}
+set a(0-10111) {NAME ACC1:conc#1301 TYPE CONCATENATE PAR 0-9373 XREFS 58322 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.314388875} PREDS {{258 0 0-10109 {}} {259 0 0-10110 {}}} SUCCS {{259 0 0-10112 {}}} CYCLES {}}
+set a(0-10112) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#422 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58323 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.3551718850894753 1 0.3551718850894753} PREDS {{258 0 0-10107 {}} {259 0 0-10111 {}}} SUCCS {{259 0 0-10113 {}}} CYCLES {}}
+set a(0-10113) {NAME ACC1:slc#90 TYPE READSLICE PAR 0-9373 XREFS 58324 LOC {1 0.30871404999999996 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-10112 {}}} SUCCS {{258 0 0-10116 {}}} CYCLES {}}
+set a(0-10114) {NAME ACC1-3:slc(ACC1:acc#217.psp)#3 TYPE READSLICE PAR 0-9373 XREFS 58325 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.355171925} PREDS {{258 0 0-10105 {}}} SUCCS {{259 0 0-10115 {}}} CYCLES {}}
+set a(0-10115) {NAME ACC1-3:not#306 TYPE NOT PAR 0-9373 XREFS 58326 LOC {1 0.267931 1 0.355171925 1 0.355171925 1 0.355171925} PREDS {{259 0 0-10114 {}}} SUCCS {{259 0 0-10116 {}}} CYCLES {}}
+set a(0-10116) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1-3:acc#223 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58327 LOC {1 0.30871404999999996 1 0.355171925 1 0.355171925 1 0.37564468508947524 1 0.37564468508947524} PREDS {{258 0 0-10113 {}} {259 0 0-10115 {}}} SUCCS {{259 0 0-10117 {}} {258 0 0-10120 {}} {258 0 0-10499 {}}} CYCLES {}}
+set a(0-10117) {NAME ACC1-3:slc(ACC1:acc#223.psp)#1 TYPE READSLICE PAR 0-9373 XREFS 58328 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-10116 {}}} SUCCS {{259 0 0-10118 {}}} CYCLES {}}
+set a(0-10118) {NAME ACC1-3:not#299 TYPE NOT PAR 0-9373 XREFS 58329 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-10117 {}}} SUCCS {{259 0 0-10119 {}}} CYCLES {}}
+set a(0-10119) {NAME ACC1:conc#1302 TYPE CONCATENATE PAR 0-9373 XREFS 58330 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-10118 {}}} SUCCS {{258 0 0-10122 {}}} CYCLES {}}
+set a(0-10120) {NAME ACC1-3:slc(ACC1:acc#223.psp) TYPE READSLICE PAR 0-9373 XREFS 58331 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{258 0 0-10116 {}}} SUCCS {{259 0 0-10121 {}}} CYCLES {}}
+set a(0-10121) {NAME ACC1:conc#1303 TYPE CONCATENATE PAR 0-9373 XREFS 58332 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.37564472499999996} PREDS {{259 0 0-10120 {}}} SUCCS {{259 0 0-10122 {}}} CYCLES {}}
+set a(0-10122) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#423 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58333 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.40289060207082716 1 0.40289060207082716} PREDS {{258 0 0-10119 {}} {259 0 0-10121 {}}} SUCCS {{259 0 0-10123 {}}} CYCLES {}}
+set a(0-10123) {NAME ACC1:slc#91 TYPE READSLICE PAR 0-9373 XREFS 58334 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-10122 {}}} SUCCS {{259 0 0-10124 {}} {258 0 0-10126 {}} {258 0 0-10128 {}} {258 0 0-10960 {}} {258 0 0-11535 {}}} CYCLES {}}
+set a(0-10124) {NAME ACC1-3:slc(acc.imod#18) TYPE READSLICE PAR 0-9373 XREFS 58335 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-10123 {}}} SUCCS {{259 0 0-10125 {}}} CYCLES {}}
+set a(0-10125) {NAME ACC1:conc#1305 TYPE CONCATENATE PAR 0-9373 XREFS 58336 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-10124 {}}} SUCCS {{258 0 0-10131 {}}} CYCLES {}}
+set a(0-10126) {NAME ACC1-3:slc(acc.imod#18)#1 TYPE READSLICE PAR 0-9373 XREFS 58337 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-10123 {}}} SUCCS {{259 0 0-10127 {}}} CYCLES {}}
+set a(0-10127) {NAME ACC1-3:not#153 TYPE NOT PAR 0-9373 XREFS 58338 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-10126 {}}} SUCCS {{258 0 0-10130 {}}} CYCLES {}}
+set a(0-10128) {NAME ACC1-3:slc(acc.imod#18)#2 TYPE READSLICE PAR 0-9373 XREFS 58339 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-10123 {}}} SUCCS {{259 0 0-10129 {}}} CYCLES {}}
+set a(0-10129) {NAME ACC1-3:not#154 TYPE NOT PAR 0-9373 XREFS 58340 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{259 0 0-10128 {}}} SUCCS {{259 0 0-10130 {}}} CYCLES {}}
+set a(0-10130) {NAME ACC1:conc#1306 TYPE CONCATENATE PAR 0-9373 XREFS 58341 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.40289064999999996} PREDS {{258 0 0-10127 {}} {259 0 0-10129 {}}} SUCCS {{259 0 0-10131 {}}} CYCLES {}}
+set a(0-10131) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#424 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58342 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.43013652707082717 1 0.43013652707082717} PREDS {{258 0 0-10125 {}} {259 0 0-10130 {}}} SUCCS {{259 0 0-10132 {}}} CYCLES {}}
+set a(0-10132) {NAME ACC1:slc#92 TYPE READSLICE PAR 0-9373 XREFS 58343 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10131 {}}} SUCCS {{258 0 0-10485 {}} {258 0 0-10487 {}} {258 0 0-10964 {}}} CYCLES {}}
+set a(0-10133) {NAME slc(ACC1-1:acc#25.psp)#5 TYPE READSLICE PAR 0-9373 XREFS 58344 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.9246291999999999} PREDS {{258 0 0-9616 {}}} SUCCS {{258 0 0-10139 {}}} CYCLES {}}
+set a(0-10134) {NAME slc(ACC1-1:acc#25.psp)#6 TYPE READSLICE PAR 0-9373 XREFS 58345 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.9246291999999999} PREDS {{258 0 0-9616 {}}} SUCCS {{258 0 0-10139 {}}} CYCLES {}}
+set a(0-10135) {NAME slc(ACC1-1:acc#25.psp)#7 TYPE READSLICE PAR 0-9373 XREFS 58346 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.9246291999999999} PREDS {{258 0 0-9616 {}}} SUCCS {{258 0 0-10139 {}}} CYCLES {}}
+set a(0-10136) {NAME slc(ACC1-1:acc#25.psp)#8 TYPE READSLICE PAR 0-9373 XREFS 58347 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.9246291999999999} PREDS {{258 0 0-9616 {}}} SUCCS {{258 0 0-10139 {}}} CYCLES {}}
+set a(0-10137) {NAME slc(ACC1-1:acc#25.psp) TYPE READSLICE PAR 0-9373 XREFS 58348 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.9246291999999999} PREDS {{258 0 0-9616 {}}} SUCCS {{258 0 0-10139 {}}} CYCLES {}}
+set a(0-10138) {NAME ACC1:slc(ACC1:acc#224.psp)#47 TYPE READSLICE PAR 0-9373 XREFS 58349 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.9246291999999999} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10139 {}}} CYCLES {}}
+set a(0-10139) {NAME ACC1:conc#1078 TYPE CONCATENATE PAR 0-9373 XREFS 58350 LOC {1 0.14655495 1 0.84514095 1 0.84514095 1 0.9246291999999999} PREDS {{258 0 0-10137 {}} {258 0 0-10136 {}} {258 0 0-10135 {}} {258 0 0-10134 {}} {258 0 0-10133 {}} {259 0 0-10138 {}}} SUCCS {{258 0 0-10160 {}}} CYCLES {}}
+set a(0-10140) {NAME ACC1:slc(ACC1:acc#227.psp)#61 TYPE READSLICE PAR 0-9373 XREFS 58351 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.573416975} PREDS {{258 0 0-9918 {}}} SUCCS {{258 0 0-10142 {}}} CYCLES {}}
+set a(0-10141) {NAME ACC1:slc(acc.psp#1)#60 TYPE READSLICE PAR 0-9373 XREFS 58352 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.573416975} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-10142 {}}} CYCLES {}}
+set a(0-10142) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#326 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-9373 XREFS 58353 LOC {1 0.14655495 1 0.49392872499999996 1 0.49392872499999996 1 0.52553956125 1 0.60502781125} PREDS {{258 0 0-10140 {}} {259 0 0-10141 {}}} SUCCS {{258 0 0-10144 {}}} CYCLES {}}
+set a(0-10143) {NAME ACC1:slc(ACC1:acc#224.psp)#51 TYPE READSLICE PAR 0-9373 XREFS 58354 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6050278499999999} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10144 {}}} CYCLES {}}
+set a(0-10144) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#325 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58355 LOC {1 0.178165825 1 0.5255396 1 0.5255396 1 0.5460123600894753 1 0.6255006100894752} PREDS {{258 0 0-10142 {}} {259 0 0-10143 {}}} SUCCS {{258 0 0-10146 {}}} CYCLES {}}
+set a(0-10145) {NAME ACC1:slc(ACC1:acc#228.psp)#51 TYPE READSLICE PAR 0-9373 XREFS 58356 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.62550065} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-10146 {}}} CYCLES {}}
+set a(0-10146) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#324 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58357 LOC {1 0.19863862499999999 1 0.5460124 1 0.5460124 1 0.5664851600894752 1 0.6459734100894753} PREDS {{258 0 0-10144 {}} {259 0 0-10145 {}}} SUCCS {{258 0 0-10148 {}}} CYCLES {}}
+set a(0-10147) {NAME ACC1:slc(ACC1:acc#226.psp)#42 TYPE READSLICE PAR 0-9373 XREFS 58358 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.64597345} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-10148 {}}} CYCLES {}}
+set a(0-10148) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#323 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58359 LOC {1 0.219111425 1 0.5664852 1 0.5664852 1 0.5937310770708272 1 0.6732193270708271} PREDS {{258 0 0-10146 {}} {259 0 0-10147 {}}} SUCCS {{258 0 0-10150 {}}} CYCLES {}}
+set a(0-10149) {NAME ACC1:slc(ACC1:acc#224.psp#1)#23 TYPE READSLICE PAR 0-9373 XREFS 58360 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.673219375} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-10150 {}}} CYCLES {}}
+set a(0-10150) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#322 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58361 LOC {1 0.24635735 1 0.593731125 1 0.593731125 1 0.6209770020708272 1 0.7004652520708271} PREDS {{258 0 0-10148 {}} {259 0 0-10149 {}}} SUCCS {{258 0 0-10152 {}}} CYCLES {}}
+set a(0-10151) {NAME ACC1:slc(ACC1-1:acc#25.psp)#20 TYPE READSLICE PAR 0-9373 XREFS 58362 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.7004653} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10152 {}}} CYCLES {}}
+set a(0-10152) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#321 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58363 LOC {1 0.273603275 1 0.6209770499999999 1 0.6209770499999999 1 0.6482229270708271 1 0.7277111770708271} PREDS {{258 0 0-10150 {}} {259 0 0-10151 {}}} SUCCS {{258 0 0-10154 {}}} CYCLES {}}
+set a(0-10153) {NAME ACC1:slc(acc.psp#2)#9 TYPE READSLICE PAR 0-9373 XREFS 58364 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.727711225} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10154 {}}} CYCLES {}}
+set a(0-10154) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#320 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58365 LOC {1 0.3008492 1 0.6482229749999999 1 0.6482229749999999 1 0.6754688520708271 1 0.7549571020708271} PREDS {{258 0 0-10152 {}} {259 0 0-10153 {}}} SUCCS {{259 0 0-10155 {}}} CYCLES {}}
+set a(0-10155) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(4,0,5,0,8) AREA_SCORE 330.25 QUANTITY 2 NAME ACC1:mul#58 TYPE MUL DELAY {2.71 ns} LIBRARY_DELAY {2.71 ns} PAR 0-9373 XREFS 58366 LOC {1 0.328095125 1 0.6754688999999999 1 0.6754688999999999 1 0.8451408976245128 1 0.9246291476245129} PREDS {{259 0 0-10154 {}}} SUCCS {{258 0 0-10159 {}}} CYCLES {}}
+set a(0-10156) {NAME ACC1:slc(ACC1:acc#227.psp)#62 TYPE READSLICE PAR 0-9373 XREFS 58367 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.9246291999999999} PREDS {{258 0 0-9918 {}}} SUCCS {{258 0 0-10159 {}}} CYCLES {}}
+set a(0-10157) {NAME ACC1-3:slc(acc#10.psp)#68 TYPE READSLICE PAR 0-9373 XREFS 58368 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.9246291999999999} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10158 {}}} CYCLES {}}
+set a(0-10158) {NAME ACC1-3:exs#51 TYPE SIGNEXTEND PAR 0-9373 XREFS 58369 LOC {1 0.14655495 1 0.84514095 1 0.84514095 1 0.9246291999999999} PREDS {{259 0 0-10157 {}}} SUCCS {{259 0 0-10159 {}}} CYCLES {}}
+set a(0-10159) {NAME ACC1:conc#1105 TYPE CONCATENATE PAR 0-9373 XREFS 58370 LOC {1 0.49776717499999995 1 0.84514095 1 0.84514095 1 0.9246291999999999} PREDS {{258 0 0-10156 {}} {258 0 0-10155 {}} {259 0 0-10158 {}}} SUCCS {{259 0 0-10160 {}}} CYCLES {}}
+set a(0-10160) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME ACC1:acc#654 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 58371 LOC {1 0.49776717499999995 1 0.84514095 1 0.84514095 1 0.9205117063734284 1 0.9999999563734283} PREDS {{258 0 0-10139 {}} {259 0 0-10159 {}}} SUCCS {{258 0 0-10447 {}}} CYCLES {}}
+set a(0-10161) {NAME ACC1-1:slc(acc.psp)#57 TYPE READSLICE PAR 0-9373 XREFS 58372 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10166 {}}} CYCLES {}}
+set a(0-10162) {NAME ACC1-1:slc(acc.psp)#58 TYPE READSLICE PAR 0-9373 XREFS 58373 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10166 {}}} CYCLES {}}
+set a(0-10163) {NAME ACC1-1:slc(acc.psp)#59 TYPE READSLICE PAR 0-9373 XREFS 58374 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10166 {}}} CYCLES {}}
+set a(0-10164) {NAME ACC1-1:slc(acc.psp)#60 TYPE READSLICE PAR 0-9373 XREFS 58375 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10166 {}}} CYCLES {}}
+set a(0-10165) {NAME ACC1-1:slc(acc.psp)#48 TYPE READSLICE PAR 0-9373 XREFS 58376 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10166 {}}} CYCLES {}}
+set a(0-10166) {NAME ACC1-1:conc#554 TYPE CONCATENATE PAR 0-9373 XREFS 58377 LOC {1 0.14655495 1 0.6519825499999999 1 0.6519825499999999 1 0.7314708} PREDS {{258 0 0-10164 {}} {258 0 0-10163 {}} {258 0 0-10162 {}} {258 0 0-10161 {}} {259 0 0-10165 {}}} SUCCS {{258 0 0-10219 {}}} CYCLES {}}
+set a(0-10167) {NAME ACC1-1:slc(acc.psp)#63 TYPE READSLICE PAR 0-9373 XREFS 58378 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10172 {}}} CYCLES {}}
+set a(0-10168) {NAME ACC1-1:slc(acc.psp)#64 TYPE READSLICE PAR 0-9373 XREFS 58379 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10172 {}}} CYCLES {}}
+set a(0-10169) {NAME ACC1-1:slc(acc.psp)#50 TYPE READSLICE PAR 0-9373 XREFS 58380 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10172 {}}} CYCLES {}}
+set a(0-10170) {NAME ACC1-1:slc(acc.psp)#65 TYPE READSLICE PAR 0-9373 XREFS 58381 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10171 {}}} CYCLES {}}
+set a(0-10171) {NAME ACC1-1:exs TYPE SIGNEXTEND PAR 0-9373 XREFS 58382 LOC {1 0.14655495 1 0.59959805 1 0.59959805 1 0.6790862999999999} PREDS {{259 0 0-10170 {}}} SUCCS {{259 0 0-10172 {}}} CYCLES {}}
+set a(0-10172) {NAME ACC1-1:conc#559 TYPE CONCATENATE PAR 0-9373 XREFS 58383 LOC {1 0.14655495 1 0.59959805 1 0.59959805 1 0.6790862999999999} PREDS {{258 0 0-10169 {}} {258 0 0-10168 {}} {258 0 0-10167 {}} {259 0 0-10171 {}}} SUCCS {{258 0 0-10218 {}}} CYCLES {}}
+set a(0-10173) {NAME ACC1-1:slc(acc.psp)#36 TYPE READSLICE PAR 0-9373 XREFS 58384 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6358845249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10177 {}}} CYCLES {}}
+set a(0-10174) {NAME ACC1-1:slc(acc.psp)#37 TYPE READSLICE PAR 0-9373 XREFS 58385 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6358845249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10177 {}}} CYCLES {}}
+set a(0-10175) {NAME ACC1-1:slc(acc.idiv)#29 TYPE READSLICE PAR 0-9373 XREFS 58386 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6358845249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10176 {}}} CYCLES {}}
+set a(0-10176) {NAME ACC1-1:exs#14 TYPE SIGNEXTEND PAR 0-9373 XREFS 58387 LOC {1 0.14655495 1 0.556396275 1 0.556396275 1 0.6358845249999999} PREDS {{259 0 0-10175 {}}} SUCCS {{259 0 0-10177 {}}} CYCLES {}}
+set a(0-10177) {NAME ACC1-1:conc#563 TYPE CONCATENATE PAR 0-9373 XREFS 58388 LOC {1 0.14655495 1 0.556396275 1 0.556396275 1 0.6358845249999999} PREDS {{258 0 0-10174 {}} {258 0 0-10173 {}} {259 0 0-10176 {}}} SUCCS {{258 0 0-10217 {}}} CYCLES {}}
+set a(0-10178) {NAME ACC1-1:slc(acc.idiv)#5 TYPE READSLICE PAR 0-9373 XREFS 58389 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10179 {}}} CYCLES {}}
+set a(0-10179) {NAME ACC1-1:exs#2 TYPE SIGNEXTEND PAR 0-9373 XREFS 58390 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10178 {}}} SUCCS {{259 0 0-10180 {}}} CYCLES {}}
+set a(0-10180) {NAME ACC1:conc#1429 TYPE CONCATENATE PAR 0-9373 XREFS 58391 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10179 {}}} SUCCS {{258 0 0-10184 {}}} CYCLES {}}
+set a(0-10181) {NAME ACC1-1:slc(acc.idiv)#7 TYPE READSLICE PAR 0-9373 XREFS 58392 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10182 {}}} CYCLES {}}
+set a(0-10182) {NAME ACC1-1:exs#3 TYPE SIGNEXTEND PAR 0-9373 XREFS 58393 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10181 {}}} SUCCS {{259 0 0-10183 {}}} CYCLES {}}
+set a(0-10183) {NAME ACC1:conc#1430 TYPE CONCATENATE PAR 0-9373 XREFS 58394 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-9457 {}} {259 0 0-10182 {}}} SUCCS {{259 0 0-10184 {}}} CYCLES {}}
+set a(0-10184) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#670 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58395 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-10180 {}} {259 0 0-10183 {}}} SUCCS {{259 0 0-10185 {}}} CYCLES {}}
+set a(0-10185) {NAME ACC1:slc#153 TYPE READSLICE PAR 0-9373 XREFS 58396 LOC {1 0.43123487499999996 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-10184 {}}} SUCCS {{258 0 0-10196 {}}} CYCLES {}}
+set a(0-10186) {NAME ACC1-1:slc(acc.idiv)#15 TYPE READSLICE PAR 0-9373 XREFS 58397 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10187 {}}} CYCLES {}}
+set a(0-10187) {NAME ACC1-1:exs#7 TYPE SIGNEXTEND PAR 0-9373 XREFS 58398 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10186 {}}} SUCCS {{259 0 0-10188 {}}} CYCLES {}}
+set a(0-10188) {NAME ACC1:conc#1427 TYPE CONCATENATE PAR 0-9373 XREFS 58399 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10187 {}}} SUCCS {{258 0 0-10194 {}}} CYCLES {}}
+set a(0-10189) {NAME ACC1-1:slc(acc.idiv)#17 TYPE READSLICE PAR 0-9373 XREFS 58400 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10190 {}}} CYCLES {}}
+set a(0-10190) {NAME ACC1-1:exs#8 TYPE SIGNEXTEND PAR 0-9373 XREFS 58401 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10189 {}}} SUCCS {{258 0 0-10193 {}}} CYCLES {}}
+set a(0-10191) {NAME ACC1-1:slc(acc.imod#2)#12 TYPE READSLICE PAR 0-9373 XREFS 58402 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.4874251} PREDS {{258 0 0-9444 {}}} SUCCS {{259 0 0-10192 {}}} CYCLES {}}
+set a(0-10192) {NAME ACC1-1:not#294 TYPE NOT PAR 0-9373 XREFS 58403 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10191 {}}} SUCCS {{259 0 0-10193 {}}} CYCLES {}}
+set a(0-10193) {NAME ACC1:conc#1428 TYPE CONCATENATE PAR 0-9373 XREFS 58404 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-10190 {}} {259 0 0-10192 {}}} SUCCS {{259 0 0-10194 {}}} CYCLES {}}
+set a(0-10194) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#669 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58405 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-10188 {}} {259 0 0-10193 {}}} SUCCS {{259 0 0-10195 {}}} CYCLES {}}
+set a(0-10195) {NAME ACC1:slc#152 TYPE READSLICE PAR 0-9373 XREFS 58406 LOC {1 0.40398894999999996 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-10194 {}}} SUCCS {{259 0 0-10196 {}}} CYCLES {}}
+set a(0-10196) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#676 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58407 LOC {1 0.43123487499999996 1 0.455493025 1 0.455493025 1 0.5030491520708271 1 0.582537402070827} PREDS {{258 0 0-10185 {}} {259 0 0-10195 {}}} SUCCS {{258 0 0-10216 {}}} CYCLES {}}
+set a(0-10197) {NAME ACC1-1:slc(acc.idiv)#13 TYPE READSLICE PAR 0-9373 XREFS 58408 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10198 {}}} CYCLES {}}
+set a(0-10198) {NAME ACC1-1:exs#6 TYPE SIGNEXTEND PAR 0-9373 XREFS 58409 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10197 {}}} SUCCS {{259 0 0-10199 {}}} CYCLES {}}
+set a(0-10199) {NAME ACC1:conc#1425 TYPE CONCATENATE PAR 0-9373 XREFS 58410 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10198 {}}} SUCCS {{258 0 0-10204 {}}} CYCLES {}}
+set a(0-10200) {NAME ACC1-1:slc(acc.idiv)#23 TYPE READSLICE PAR 0-9373 XREFS 58411 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10201 {}}} CYCLES {}}
+set a(0-10201) {NAME ACC1-1:exs#11 TYPE SIGNEXTEND PAR 0-9373 XREFS 58412 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10200 {}}} SUCCS {{258 0 0-10203 {}}} CYCLES {}}
+set a(0-10202) {NAME ACC1-1:slc(acc.imod#2)#11 TYPE READSLICE PAR 0-9373 XREFS 58413 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.4874251} PREDS {{258 0 0-9444 {}}} SUCCS {{259 0 0-10203 {}}} CYCLES {}}
+set a(0-10203) {NAME ACC1:conc#1426 TYPE CONCATENATE PAR 0-9373 XREFS 58414 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-10201 {}} {259 0 0-10202 {}}} SUCCS {{259 0 0-10204 {}}} CYCLES {}}
+set a(0-10204) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#668 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58415 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-10199 {}} {259 0 0-10203 {}}} SUCCS {{259 0 0-10205 {}}} CYCLES {}}
+set a(0-10205) {NAME ACC1:slc#151 TYPE READSLICE PAR 0-9373 XREFS 58416 LOC {1 0.40398894999999996 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-10204 {}}} SUCCS {{258 0 0-10215 {}}} CYCLES {}}
+set a(0-10206) {NAME ACC1-1:slc(acc.idiv)#19 TYPE READSLICE PAR 0-9373 XREFS 58417 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10207 {}}} CYCLES {}}
+set a(0-10207) {NAME ACC1-1:exs#9 TYPE SIGNEXTEND PAR 0-9373 XREFS 58418 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10206 {}}} SUCCS {{259 0 0-10208 {}}} CYCLES {}}
+set a(0-10208) {NAME ACC1:conc#1423 TYPE CONCATENATE PAR 0-9373 XREFS 58419 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10207 {}}} SUCCS {{258 0 0-10213 {}}} CYCLES {}}
+set a(0-10209) {NAME ACC1-1:slc(acc.idiv)#21 TYPE READSLICE PAR 0-9373 XREFS 58420 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10210 {}}} CYCLES {}}
+set a(0-10210) {NAME ACC1-1:exs#10 TYPE SIGNEXTEND PAR 0-9373 XREFS 58421 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10209 {}}} SUCCS {{258 0 0-10212 {}}} CYCLES {}}
+set a(0-10211) {NAME ACC1-1:slc(ACC1:acc#210.psp)#9 TYPE READSLICE PAR 0-9373 XREFS 58422 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.4874251} PREDS {{258 0 0-9426 {}}} SUCCS {{259 0 0-10212 {}}} CYCLES {}}
+set a(0-10212) {NAME ACC1:conc#1424 TYPE CONCATENATE PAR 0-9373 XREFS 58423 LOC {1 0.267931 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-10210 {}} {259 0 0-10211 {}}} SUCCS {{259 0 0-10213 {}}} CYCLES {}}
+set a(0-10213) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#667 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58424 LOC {1 0.267931 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-10208 {}} {259 0 0-10212 {}}} SUCCS {{259 0 0-10214 {}}} CYCLES {}}
+set a(0-10214) {NAME ACC1:slc#150 TYPE READSLICE PAR 0-9373 XREFS 58425 LOC {1 0.315487175 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-10213 {}}} SUCCS {{259 0 0-10215 {}}} CYCLES {}}
+set a(0-10215) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#675 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58426 LOC {1 0.40398894999999996 1 0.455493025 1 0.455493025 1 0.5030491520708271 1 0.582537402070827} PREDS {{258 0 0-10205 {}} {259 0 0-10214 {}}} SUCCS {{259 0 0-10216 {}}} CYCLES {}}
+set a(0-10216) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#680 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 58427 LOC {1 0.47879105 1 0.5030492 1 0.5030492 1 0.5563962201789505 1 0.6358844701789506} PREDS {{258 0 0-10196 {}} {259 0 0-10215 {}}} SUCCS {{259 0 0-10217 {}}} CYCLES {}}
+set a(0-10217) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 5 NAME ACC1:acc#683 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 58428 LOC {1 0.532138125 1 0.556396275 1 0.556396275 1 0.5995979984103024 1 0.6790862484103023} PREDS {{258 0 0-10177 {}} {259 0 0-10216 {}}} SUCCS {{259 0 0-10218 {}}} CYCLES {}}
+set a(0-10218) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#686 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-9373 XREFS 58429 LOC {1 0.5753399 1 0.59959805 1 0.59959805 1 0.6519825027684257 1 0.7314707527684257} PREDS {{258 0 0-10172 {}} {259 0 0-10217 {}}} SUCCS {{259 0 0-10219 {}}} CYCLES {}}
+set a(0-10219) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,1,11) AREA_SCORE 10.00 QUANTITY 5 NAME ACC1:acc#688 TYPE ACCU DELAY {0.91 ns} LIBRARY_DELAY {0.91 ns} PAR 0-9373 XREFS 58430 LOC {1 0.6277244 1 0.6519825499999999 1 0.6519825499999999 1 0.7087410628916543 1 0.7882293128916543} PREDS {{258 0 0-10166 {}} {259 0 0-10218 {}}} SUCCS {{258 0 0-10286 {}}} CYCLES {}}
+set a(0-10220) {NAME ACC1-1:slc(acc.psp)#29 TYPE READSLICE PAR 0-9373 XREFS 58431 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5312430499999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10221 {}}} CYCLES {}}
+set a(0-10221) {NAME ACC1:conc#1418 TYPE CONCATENATE PAR 0-9373 XREFS 58432 LOC {1 0.14655495 1 0.45175479999999996 1 0.45175479999999996 1 0.5312430499999999} PREDS {{259 0 0-10220 {}}} SUCCS {{259 0 0-10222 {}}} CYCLES {}}
+set a(0-10222) {NAME ACC1:conc#1419 TYPE CONCATENATE PAR 0-9373 XREFS 58433 LOC {1 0.14655495 1 0.45175479999999996 1 0.45175479999999996 1 0.5312430499999999} PREDS {{259 0 0-10221 {}}} SUCCS {{258 0 0-10226 {}}} CYCLES {}}
+set a(0-10223) {NAME ACC1-1:slc(ACC1:acc#210.psp)#10 TYPE READSLICE PAR 0-9373 XREFS 58434 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.5312430499999999} PREDS {{258 0 0-9426 {}}} SUCCS {{258 0 0-10225 {}}} CYCLES {}}
+set a(0-10224) {NAME ACC1-1:slc(acc.psp)#30 TYPE READSLICE PAR 0-9373 XREFS 58435 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5312430499999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10225 {}}} CYCLES {}}
+set a(0-10225) {NAME ACC1:conc#1420 TYPE CONCATENATE PAR 0-9373 XREFS 58436 LOC {1 0.267931 1 0.45175479999999996 1 0.45175479999999996 1 0.5312430499999999} PREDS {{258 0 0-10223 {}} {259 0 0-10224 {}}} SUCCS {{259 0 0-10226 {}}} CYCLES {}}
+set a(0-10226) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 4 NAME ACC1:acc#665 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-9373 XREFS 58437 LOC {1 0.267931 1 0.45175479999999996 1 0.45175479999999996 1 0.4893753770241716 1 0.5688636270241716} PREDS {{258 0 0-10222 {}} {259 0 0-10225 {}}} SUCCS {{259 0 0-10227 {}}} CYCLES {}}
+set a(0-10227) {NAME ACC1:slc#148 TYPE READSLICE PAR 0-9373 XREFS 58438 LOC {1 0.305551625 1 0.489375425 1 0.489375425 1 0.568863675} PREDS {{259 0 0-10226 {}}} SUCCS {{258 0 0-10229 {}}} CYCLES {}}
+set a(0-10228) {NAME ACC1-1:slc(ACC1:acc#220.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 58439 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.568863675} PREDS {{258 0 0-9437 {}}} SUCCS {{259 0 0-10229 {}}} CYCLES {}}
+set a(0-10229) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 4 NAME ACC1:acc#674 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-9373 XREFS 58440 LOC {1 0.32918685 1 0.489375425 1 0.489375425 1 0.5269960020241716 1 0.6064842520241717} PREDS {{258 0 0-10227 {}} {259 0 0-10228 {}}} SUCCS {{258 0 0-10241 {}}} CYCLES {}}
+set a(0-10230) {NAME ACC1-1:slc(acc.psp)#31 TYPE READSLICE PAR 0-9373 XREFS 58441 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.579238375} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10232 {}}} CYCLES {}}
+set a(0-10231) {NAME ACC1-1:slc(acc.psp)#32 TYPE READSLICE PAR 0-9373 XREFS 58442 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.579238375} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10232 {}}} CYCLES {}}
+set a(0-10232) {NAME ACC1-1:conc#556 TYPE CONCATENATE PAR 0-9373 XREFS 58443 LOC {1 0.14655495 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{258 0 0-10230 {}} {259 0 0-10231 {}}} SUCCS {{259 0 0-10233 {}}} CYCLES {}}
+set a(0-10233) {NAME ACC1:conc#1421 TYPE CONCATENATE PAR 0-9373 XREFS 58444 LOC {1 0.14655495 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{259 0 0-10232 {}}} SUCCS {{258 0 0-10239 {}}} CYCLES {}}
+set a(0-10234) {NAME ACC1-1:slc(ACC1:acc#210.psp)#11 TYPE READSLICE PAR 0-9373 XREFS 58445 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.579238375} PREDS {{258 0 0-9426 {}}} SUCCS {{258 0 0-10236 {}}} CYCLES {}}
+set a(0-10235) {NAME ACC1-1:slc(acc.psp)#33 TYPE READSLICE PAR 0-9373 XREFS 58446 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.579238375} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10236 {}}} CYCLES {}}
+set a(0-10236) {NAME ACC1-1:conc#557 TYPE CONCATENATE PAR 0-9373 XREFS 58447 LOC {1 0.267931 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{258 0 0-10234 {}} {259 0 0-10235 {}}} SUCCS {{258 0 0-10238 {}}} CYCLES {}}
+set a(0-10237) {NAME ACC1-1:slc(ACC1:acc#210.psp)#8 TYPE READSLICE PAR 0-9373 XREFS 58448 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.579238375} PREDS {{258 0 0-9426 {}}} SUCCS {{259 0 0-10238 {}}} CYCLES {}}
+set a(0-10238) {NAME ACC1:conc#1422 TYPE CONCATENATE PAR 0-9373 XREFS 58449 LOC {1 0.267931 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{258 0 0-10236 {}} {259 0 0-10237 {}}} SUCCS {{259 0 0-10239 {}}} CYCLES {}}
+set a(0-10239) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#666 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58450 LOC {1 0.267931 1 0.499750125 1 0.499750125 1 0.5269960020708272 1 0.6064842520708271} PREDS {{258 0 0-10233 {}} {259 0 0-10238 {}}} SUCCS {{259 0 0-10240 {}}} CYCLES {}}
+set a(0-10240) {NAME ACC1:slc#149 TYPE READSLICE PAR 0-9373 XREFS 58451 LOC {1 0.295176925 1 0.5269960499999999 1 0.5269960499999999 1 0.6064843} PREDS {{259 0 0-10239 {}}} SUCCS {{259 0 0-10241 {}}} CYCLES {}}
+set a(0-10241) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#679 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 58452 LOC {1 0.366807475 1 0.5269960499999999 1 0.5269960499999999 1 0.5701879451789504 1 0.6496761951789505} PREDS {{258 0 0-10229 {}} {259 0 0-10240 {}}} SUCCS {{258 0 0-10253 {}}} CYCLES {}}
+set a(0-10242) {NAME ACC1-1:slc(acc.psp)#34 TYPE READSLICE PAR 0-9373 XREFS 58453 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.616639425} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10246 {}}} CYCLES {}}
+set a(0-10243) {NAME ACC1-1:slc(acc.psp)#35 TYPE READSLICE PAR 0-9373 XREFS 58454 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.616639425} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10246 {}}} CYCLES {}}
+set a(0-10244) {NAME ACC1-1:slc(acc.idiv)#31 TYPE READSLICE PAR 0-9373 XREFS 58455 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.616639425} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10245 {}}} CYCLES {}}
+set a(0-10245) {NAME ACC1-1:exs#15 TYPE SIGNEXTEND PAR 0-9373 XREFS 58456 LOC {1 0.14655495 1 0.537151175 1 0.537151175 1 0.616639425} PREDS {{259 0 0-10244 {}}} SUCCS {{259 0 0-10246 {}}} CYCLES {}}
+set a(0-10246) {NAME ACC1-1:conc#558 TYPE CONCATENATE PAR 0-9373 XREFS 58457 LOC {1 0.14655495 1 0.537151175 1 0.537151175 1 0.616639425} PREDS {{258 0 0-10243 {}} {258 0 0-10242 {}} {259 0 0-10245 {}}} SUCCS {{258 0 0-10252 {}}} CYCLES {}}
+set a(0-10247) {NAME ACC1-1:slc(acc.idiv)#33 TYPE READSLICE PAR 0-9373 XREFS 58458 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.575856375} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10248 {}}} CYCLES {}}
+set a(0-10248) {NAME ACC1-1:exs#16 TYPE SIGNEXTEND PAR 0-9373 XREFS 58459 LOC {1 0.14655495 1 0.496368125 1 0.496368125 1 0.575856375} PREDS {{259 0 0-10247 {}}} SUCCS {{258 0 0-10251 {}}} CYCLES {}}
+set a(0-10249) {NAME ACC1-1:slc(acc.idiv)#35 TYPE READSLICE PAR 0-9373 XREFS 58460 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.575856375} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10250 {}}} CYCLES {}}
+set a(0-10250) {NAME ACC1-1:exs#17 TYPE SIGNEXTEND PAR 0-9373 XREFS 58461 LOC {1 0.14655495 1 0.496368125 1 0.496368125 1 0.575856375} PREDS {{259 0 0-10249 {}}} SUCCS {{259 0 0-10251 {}}} CYCLES {}}
+set a(0-10251) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#673 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58462 LOC {1 0.14655495 1 0.496368125 1 0.496368125 1 0.5371511350894752 1 0.6166393850894752} PREDS {{258 0 0-10248 {}} {259 0 0-10250 {}}} SUCCS {{259 0 0-10252 {}}} CYCLES {}}
+set a(0-10252) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#678 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 58463 LOC {1 0.187338 1 0.537151175 1 0.537151175 1 0.5701879451789504 1 0.6496761951789505} PREDS {{258 0 0-10246 {}} {259 0 0-10251 {}}} SUCCS {{259 0 0-10253 {}}} CYCLES {}}
+set a(0-10253) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#682 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-9373 XREFS 58464 LOC {1 0.409999425 1 0.570188 1 0.570188 1 0.6084774594969361 1 0.687965709496936} PREDS {{258 0 0-10241 {}} {259 0 0-10252 {}}} SUCCS {{258 0 0-10259 {}}} CYCLES {}}
+set a(0-10254) {NAME ACC1-1:slc(acc.psp)#54 TYPE READSLICE PAR 0-9373 XREFS 58465 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10258 {}}} CYCLES {}}
+set a(0-10255) {NAME ACC1-1:slc(acc.psp)#55 TYPE READSLICE PAR 0-9373 XREFS 58466 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10258 {}}} CYCLES {}}
+set a(0-10256) {NAME ACC1-1:slc(acc.psp)#56 TYPE READSLICE PAR 0-9373 XREFS 58467 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10258 {}}} CYCLES {}}
+set a(0-10257) {NAME ACC1-1:slc(acc.psp)#47 TYPE READSLICE PAR 0-9373 XREFS 58468 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10258 {}}} CYCLES {}}
+set a(0-10258) {NAME ACC1-1:conc#553 TYPE CONCATENATE PAR 0-9373 XREFS 58469 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{258 0 0-10256 {}} {258 0 0-10255 {}} {258 0 0-10254 {}} {259 0 0-10257 {}}} SUCCS {{259 0 0-10259 {}}} CYCLES {}}
+set a(0-10259) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 6 NAME ACC1:acc#685 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-9373 XREFS 58470 LOC {1 0.448288925 1 0.6084775 1 0.6084775 1 0.656356562932968 1 0.7358448129329679} PREDS {{258 0 0-10253 {}} {259 0 0-10258 {}}} SUCCS {{258 0 0-10285 {}}} CYCLES {}}
+set a(0-10260) {NAME ACC1-1:slc(acc.psp)#17 TYPE READSLICE PAR 0-9373 XREFS 58471 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10263 {}}} CYCLES {}}
+set a(0-10261) {NAME ACC1-1:slc(acc.idiv)#25 TYPE READSLICE PAR 0-9373 XREFS 58472 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10262 {}}} CYCLES {}}
+set a(0-10262) {NAME ACC1-1:exs#12 TYPE SIGNEXTEND PAR 0-9373 XREFS 58473 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{259 0 0-10261 {}}} SUCCS {{259 0 0-10263 {}}} CYCLES {}}
+set a(0-10263) {NAME ACC1-1:conc#482 TYPE CONCATENATE PAR 0-9373 XREFS 58474 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{258 0 0-10260 {}} {259 0 0-10262 {}}} SUCCS {{259 0 0-10264 {}}} CYCLES {}}
+set a(0-10264) {NAME ACC1-1:exs#1029 TYPE SIGNEXTEND PAR 0-9373 XREFS 58475 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{259 0 0-10263 {}}} SUCCS {{258 0 0-10284 {}}} CYCLES {}}
+set a(0-10265) {NAME ACC1-1:slc(acc.psp)#52 TYPE READSLICE PAR 0-9373 XREFS 58476 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.64967625} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10268 {}}} CYCLES {}}
+set a(0-10266) {NAME ACC1-1:slc(acc.psp)#53 TYPE READSLICE PAR 0-9373 XREFS 58477 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.64967625} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10268 {}}} CYCLES {}}
+set a(0-10267) {NAME ACC1-1:slc(acc.psp)#46 TYPE READSLICE PAR 0-9373 XREFS 58478 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.64967625} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10268 {}}} CYCLES {}}
+set a(0-10268) {NAME ACC1-1:conc TYPE CONCATENATE PAR 0-9373 XREFS 58479 LOC {1 0.14655495 1 0.570188 1 0.570188 1 0.64967625} PREDS {{258 0 0-10266 {}} {258 0 0-10265 {}} {259 0 0-10267 {}}} SUCCS {{258 0 0-10283 {}}} CYCLES {}}
+set a(0-10269) {NAME ACC1-1:slc(acc.idiv)#9 TYPE READSLICE PAR 0-9373 XREFS 58480 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5613370249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10270 {}}} CYCLES {}}
+set a(0-10270) {NAME ACC1-1:exs#4 TYPE SIGNEXTEND PAR 0-9373 XREFS 58481 LOC {1 0.14655495 1 0.48184877499999995 1 0.48184877499999995 1 0.5613370249999999} PREDS {{259 0 0-10269 {}}} SUCCS {{258 0 0-10273 {}}} CYCLES {}}
+set a(0-10271) {NAME ACC1-1:slc(acc.idiv)#11 TYPE READSLICE PAR 0-9373 XREFS 58482 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5613370249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10272 {}}} CYCLES {}}
+set a(0-10272) {NAME ACC1-1:exs#5 TYPE SIGNEXTEND PAR 0-9373 XREFS 58483 LOC {1 0.14655495 1 0.48184877499999995 1 0.48184877499999995 1 0.5613370249999999} PREDS {{259 0 0-10271 {}}} SUCCS {{259 0 0-10273 {}}} CYCLES {}}
+set a(0-10273) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#672 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58484 LOC {1 0.14655495 1 0.48184877499999995 1 0.48184877499999995 1 0.5226317850894752 1 0.6021200350894752} PREDS {{258 0 0-10270 {}} {259 0 0-10272 {}}} SUCCS {{258 0 0-10282 {}}} CYCLES {}}
+set a(0-10274) {NAME ACC1-1:slc(acc.idiv)#1 TYPE READSLICE PAR 0-9373 XREFS 58485 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5545639} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10275 {}}} CYCLES {}}
+set a(0-10275) {NAME ACC1-1:exs#951 TYPE SIGNEXTEND PAR 0-9373 XREFS 58486 LOC {1 0.14655495 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{259 0 0-10274 {}}} SUCCS {{259 0 0-10276 {}}} CYCLES {}}
+set a(0-10276) {NAME ACC1:conc#1431 TYPE CONCATENATE PAR 0-9373 XREFS 58487 LOC {1 0.14655495 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{259 0 0-10275 {}}} SUCCS {{258 0 0-10280 {}}} CYCLES {}}
+set a(0-10277) {NAME ACC1-1:slc(acc.idiv)#3 TYPE READSLICE PAR 0-9373 XREFS 58488 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5545639} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10278 {}}} CYCLES {}}
+set a(0-10278) {NAME ACC1-1:exs#1 TYPE SIGNEXTEND PAR 0-9373 XREFS 58489 LOC {1 0.14655495 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{259 0 0-10277 {}}} SUCCS {{259 0 0-10279 {}}} CYCLES {}}
+set a(0-10279) {NAME ACC1:conc#1432 TYPE CONCATENATE PAR 0-9373 XREFS 58490 LOC {1 0.3836787 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{258 0 0-9462 {}} {259 0 0-10278 {}}} SUCCS {{259 0 0-10280 {}}} CYCLES {}}
+set a(0-10280) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#671 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58491 LOC {1 0.3836787 1 0.47507564999999996 1 0.47507564999999996 1 0.5226317770708271 1 0.6021200270708271} PREDS {{258 0 0-10276 {}} {259 0 0-10279 {}}} SUCCS {{259 0 0-10281 {}}} CYCLES {}}
+set a(0-10281) {NAME ACC1:slc#154 TYPE READSLICE PAR 0-9373 XREFS 58492 LOC {1 0.43123487499999996 1 0.5226318249999999 1 0.5226318249999999 1 0.602120075} PREDS {{259 0 0-10280 {}}} SUCCS {{259 0 0-10282 {}}} CYCLES {}}
+set a(0-10282) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#677 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58493 LOC {1 0.43123487499999996 1 0.5226318249999999 1 0.5226318249999999 1 0.5701879520708271 1 0.6496762020708271} PREDS {{258 0 0-10273 {}} {259 0 0-10281 {}}} SUCCS {{259 0 0-10283 {}}} CYCLES {}}
+set a(0-10283) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#681 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-9373 XREFS 58494 LOC {1 0.47879105 1 0.570188 1 0.570188 1 0.6084774594969361 1 0.687965709496936} PREDS {{258 0 0-10268 {}} {259 0 0-10282 {}}} SUCCS {{259 0 0-10284 {}}} CYCLES {}}
+set a(0-10284) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 6 NAME ACC1:acc#684 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-9373 XREFS 58495 LOC {1 0.51708055 1 0.6084775 1 0.6084775 1 0.656356562932968 1 0.7358448129329679} PREDS {{258 0 0-10264 {}} {259 0 0-10283 {}}} SUCCS {{259 0 0-10285 {}}} CYCLES {}}
+set a(0-10285) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#687 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-9373 XREFS 58496 LOC {1 0.564959675 1 0.6563566249999999 1 0.6563566249999999 1 0.7087410777684257 1 0.7882293277684257} PREDS {{258 0 0-10259 {}} {259 0 0-10284 {}}} SUCCS {{259 0 0-10286 {}}} CYCLES {}}
+set a(0-10286) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,12) AREA_SCORE 11.00 QUANTITY 4 NAME ACC1:acc#690 TYPE ACCU DELAY {0.98 ns} LIBRARY_DELAY {0.98 ns} PAR 0-9373 XREFS 58497 LOC {1 0.684482975 1 0.708741125 1 0.708741125 1 0.7697701033364113 1 0.8492583533364113} PREDS {{258 0 0-10219 {}} {259 0 0-10285 {}}} SUCCS {{258 0 0-10298 {}}} CYCLES {}}
+set a(0-10287) {NAME ACC1-1:slc(acc.psp)#62 TYPE READSLICE PAR 0-9373 XREFS 58498 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10289 {}}} CYCLES {}}
+set a(0-10288) {NAME ACC1-1:slc(acc.psp)#49 TYPE READSLICE PAR 0-9373 XREFS 58499 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10289 {}}} CYCLES {}}
+set a(0-10289) {NAME ACC1-1:conc#555 TYPE CONCATENATE PAR 0-9373 XREFS 58500 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7679191249999999} PREDS {{258 0 0-10287 {}} {259 0 0-10288 {}}} SUCCS {{258 0 0-10297 {}}} CYCLES {}}
+set a(0-10290) {NAME ACC1-1:slc(acc.psp)#66 TYPE READSLICE PAR 0-9373 XREFS 58501 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10296 {}}} CYCLES {}}
+set a(0-10291) {NAME ACC1-1:slc(acc.psp)#67 TYPE READSLICE PAR 0-9373 XREFS 58502 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10296 {}}} CYCLES {}}
+set a(0-10292) {NAME ACC1-1:slc(acc.psp)#68 TYPE READSLICE PAR 0-9373 XREFS 58503 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10296 {}}} CYCLES {}}
+set a(0-10293) {NAME ACC1-1:slc(acc.psp)#51 TYPE READSLICE PAR 0-9373 XREFS 58504 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10296 {}}} CYCLES {}}
+set a(0-10294) {NAME ACC1-1:slc(acc.idiv)#27 TYPE READSLICE PAR 0-9373 XREFS 58505 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10295 {}}} CYCLES {}}
+set a(0-10295) {NAME ACC1-1:exs#13 TYPE SIGNEXTEND PAR 0-9373 XREFS 58506 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7679191249999999} PREDS {{259 0 0-10294 {}}} SUCCS {{259 0 0-10296 {}}} CYCLES {}}
+set a(0-10296) {NAME ACC1-1:conc#561 TYPE CONCATENATE PAR 0-9373 XREFS 58507 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7679191249999999} PREDS {{258 0 0-10293 {}} {258 0 0-10292 {}} {258 0 0-10291 {}} {258 0 0-10290 {}} {259 0 0-10295 {}}} SUCCS {{259 0 0-10297 {}}} CYCLES {}}
+set a(0-10297) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,11) AREA_SCORE 11.24 QUANTITY 3 NAME ACC1:acc#689 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-9373 XREFS 58508 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7697701033364113 1 0.8492583533364112} PREDS {{258 0 0-10289 {}} {259 0 0-10296 {}}} SUCCS {{259 0 0-10298 {}}} CYCLES {}}
+set a(0-10298) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-1:acc#2 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 58509 LOC {1 0.745512 1 0.7697701499999999 1 0.7697701499999999 1 0.8451409063734283 1 0.9246291563734284} PREDS {{258 0 0-10286 {}} {259 0 0-10297 {}}} SUCCS {{258 0 0-10446 {}}} CYCLES {}}
+set a(0-10299) {NAME ACC1-1:slc(acc#20.psp)#57 TYPE READSLICE PAR 0-9373 XREFS 58510 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10304 {}}} CYCLES {}}
+set a(0-10300) {NAME ACC1-1:slc(acc#20.psp)#58 TYPE READSLICE PAR 0-9373 XREFS 58511 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10304 {}}} CYCLES {}}
+set a(0-10301) {NAME ACC1-1:slc(acc#20.psp)#59 TYPE READSLICE PAR 0-9373 XREFS 58512 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10304 {}}} CYCLES {}}
+set a(0-10302) {NAME ACC1-1:slc(acc#20.psp)#60 TYPE READSLICE PAR 0-9373 XREFS 58513 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10304 {}}} CYCLES {}}
+set a(0-10303) {NAME ACC1-1:slc(acc#20.psp)#48 TYPE READSLICE PAR 0-9373 XREFS 58514 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7314708} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10304 {}}} CYCLES {}}
+set a(0-10304) {NAME ACC1-1:conc#590 TYPE CONCATENATE PAR 0-9373 XREFS 58515 LOC {1 0.14655495 1 0.6519825499999999 1 0.6519825499999999 1 0.7314708} PREDS {{258 0 0-10302 {}} {258 0 0-10301 {}} {258 0 0-10300 {}} {258 0 0-10299 {}} {259 0 0-10303 {}}} SUCCS {{258 0 0-10361 {}}} CYCLES {}}
+set a(0-10305) {NAME ACC1-1:slc(acc#20.psp)#63 TYPE READSLICE PAR 0-9373 XREFS 58516 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10310 {}}} CYCLES {}}
+set a(0-10306) {NAME ACC1-1:slc(acc#20.psp)#64 TYPE READSLICE PAR 0-9373 XREFS 58517 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10310 {}}} CYCLES {}}
+set a(0-10307) {NAME ACC1-1:slc(acc#20.psp)#50 TYPE READSLICE PAR 0-9373 XREFS 58518 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10310 {}}} CYCLES {}}
+set a(0-10308) {NAME ACC1-1:slc(acc#20.psp)#65 TYPE READSLICE PAR 0-9373 XREFS 58519 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6790862999999999} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10309 {}}} CYCLES {}}
+set a(0-10309) {NAME ACC1-1:exs#1039 TYPE SIGNEXTEND PAR 0-9373 XREFS 58520 LOC {1 0.14655495 1 0.59959805 1 0.59959805 1 0.6790862999999999} PREDS {{259 0 0-10308 {}}} SUCCS {{259 0 0-10310 {}}} CYCLES {}}
+set a(0-10310) {NAME ACC1-1:conc#595 TYPE CONCATENATE PAR 0-9373 XREFS 58521 LOC {1 0.14655495 1 0.59959805 1 0.59959805 1 0.6790862999999999} PREDS {{258 0 0-10307 {}} {258 0 0-10306 {}} {258 0 0-10305 {}} {259 0 0-10309 {}}} SUCCS {{258 0 0-10360 {}}} CYCLES {}}
+set a(0-10311) {NAME ACC1-1:slc(acc#20.psp)#36 TYPE READSLICE PAR 0-9373 XREFS 58522 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6358845249999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10315 {}}} CYCLES {}}
+set a(0-10312) {NAME ACC1-1:slc(acc#20.psp)#37 TYPE READSLICE PAR 0-9373 XREFS 58523 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6358845249999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10315 {}}} CYCLES {}}
+set a(0-10313) {NAME ACC1-1:slc(acc.idiv#4)#29 TYPE READSLICE PAR 0-9373 XREFS 58524 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6358845249999999} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10314 {}}} CYCLES {}}
+set a(0-10314) {NAME ACC1-1:exs#86 TYPE SIGNEXTEND PAR 0-9373 XREFS 58525 LOC {1 0.14655495 1 0.556396275 1 0.556396275 1 0.6358845249999999} PREDS {{259 0 0-10313 {}}} SUCCS {{259 0 0-10315 {}}} CYCLES {}}
+set a(0-10315) {NAME ACC1-1:conc#599 TYPE CONCATENATE PAR 0-9373 XREFS 58526 LOC {1 0.14655495 1 0.556396275 1 0.556396275 1 0.6358845249999999} PREDS {{258 0 0-10312 {}} {258 0 0-10311 {}} {259 0 0-10314 {}}} SUCCS {{258 0 0-10359 {}}} CYCLES {}}
+set a(0-10316) {NAME ACC1-1:slc(acc.idiv#4)#5 TYPE READSLICE PAR 0-9373 XREFS 58527 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10317 {}}} CYCLES {}}
+set a(0-10317) {NAME ACC1-1:exs#74 TYPE SIGNEXTEND PAR 0-9373 XREFS 58528 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10316 {}}} SUCCS {{259 0 0-10318 {}}} CYCLES {}}
+set a(0-10318) {NAME ACC1:conc#1444 TYPE CONCATENATE PAR 0-9373 XREFS 58529 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10317 {}}} SUCCS {{258 0 0-10326 {}}} CYCLES {}}
+set a(0-10319) {NAME ACC1-1:slc(acc.idiv#4)#7 TYPE READSLICE PAR 0-9373 XREFS 58530 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10320 {}}} CYCLES {}}
+set a(0-10320) {NAME ACC1-1:exs#75 TYPE SIGNEXTEND PAR 0-9373 XREFS 58531 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10319 {}}} SUCCS {{258 0 0-10325 {}}} CYCLES {}}
+set a(0-10321) {NAME ACC1-1:slc(acc.imod#19) TYPE READSLICE PAR 0-9373 XREFS 58532 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-9611 {}}} SUCCS {{258 0 0-10324 {}}} CYCLES {}}
+set a(0-10322) {NAME ACC1-1:slc(acc.idiv#4)#44 TYPE READSLICE PAR 0-9373 XREFS 58533 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10323 {}}} CYCLES {}}
+set a(0-10323) {NAME ACC1-1:not#155 TYPE NOT PAR 0-9373 XREFS 58534 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10322 {}}} SUCCS {{259 0 0-10324 {}}} CYCLES {}}
+set a(0-10324) {NAME ACC1-1:nand#4 TYPE NAND PAR 0-9373 XREFS 58535 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-10321 {}} {259 0 0-10323 {}}} SUCCS {{259 0 0-10325 {}}} CYCLES {}}
+set a(0-10325) {NAME ACC1:conc#1445 TYPE CONCATENATE PAR 0-9373 XREFS 58536 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-10320 {}} {259 0 0-10324 {}}} SUCCS {{259 0 0-10326 {}}} CYCLES {}}
+set a(0-10326) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#696 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58537 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-10318 {}} {259 0 0-10325 {}}} SUCCS {{259 0 0-10327 {}}} CYCLES {}}
+set a(0-10327) {NAME ACC1:slc#160 TYPE READSLICE PAR 0-9373 XREFS 58538 LOC {1 0.43123487499999996 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-10326 {}}} SUCCS {{258 0 0-10338 {}}} CYCLES {}}
+set a(0-10328) {NAME ACC1-1:slc(acc.idiv#4)#15 TYPE READSLICE PAR 0-9373 XREFS 58539 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10329 {}}} CYCLES {}}
+set a(0-10329) {NAME ACC1-1:exs#79 TYPE SIGNEXTEND PAR 0-9373 XREFS 58540 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10328 {}}} SUCCS {{259 0 0-10330 {}}} CYCLES {}}
+set a(0-10330) {NAME ACC1:conc#1442 TYPE CONCATENATE PAR 0-9373 XREFS 58541 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10329 {}}} SUCCS {{258 0 0-10336 {}}} CYCLES {}}
+set a(0-10331) {NAME ACC1-1:slc(acc.idiv#4)#17 TYPE READSLICE PAR 0-9373 XREFS 58542 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10332 {}}} CYCLES {}}
+set a(0-10332) {NAME ACC1-1:exs#80 TYPE SIGNEXTEND PAR 0-9373 XREFS 58543 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10331 {}}} SUCCS {{258 0 0-10335 {}}} CYCLES {}}
+set a(0-10333) {NAME ACC1-1:slc(acc.imod#18)#12 TYPE READSLICE PAR 0-9373 XREFS 58544 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.4874251} PREDS {{258 0 0-9602 {}}} SUCCS {{259 0 0-10334 {}}} CYCLES {}}
+set a(0-10334) {NAME ACC1-1:not#300 TYPE NOT PAR 0-9373 XREFS 58545 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10333 {}}} SUCCS {{259 0 0-10335 {}}} CYCLES {}}
+set a(0-10335) {NAME ACC1:conc#1443 TYPE CONCATENATE PAR 0-9373 XREFS 58546 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-10332 {}} {259 0 0-10334 {}}} SUCCS {{259 0 0-10336 {}}} CYCLES {}}
+set a(0-10336) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#695 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58547 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-10330 {}} {259 0 0-10335 {}}} SUCCS {{259 0 0-10337 {}}} CYCLES {}}
+set a(0-10337) {NAME ACC1:slc#159 TYPE READSLICE PAR 0-9373 XREFS 58548 LOC {1 0.40398894999999996 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-10336 {}}} SUCCS {{259 0 0-10338 {}}} CYCLES {}}
+set a(0-10338) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#702 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58549 LOC {1 0.43123487499999996 1 0.455493025 1 0.455493025 1 0.5030491520708271 1 0.582537402070827} PREDS {{258 0 0-10327 {}} {259 0 0-10337 {}}} SUCCS {{258 0 0-10358 {}}} CYCLES {}}
+set a(0-10339) {NAME ACC1-1:slc(acc.idiv#4)#13 TYPE READSLICE PAR 0-9373 XREFS 58550 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10340 {}}} CYCLES {}}
+set a(0-10340) {NAME ACC1-1:exs#78 TYPE SIGNEXTEND PAR 0-9373 XREFS 58551 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10339 {}}} SUCCS {{259 0 0-10341 {}}} CYCLES {}}
+set a(0-10341) {NAME ACC1:conc#1440 TYPE CONCATENATE PAR 0-9373 XREFS 58552 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10340 {}}} SUCCS {{258 0 0-10346 {}}} CYCLES {}}
+set a(0-10342) {NAME ACC1-1:slc(acc.idiv#4)#23 TYPE READSLICE PAR 0-9373 XREFS 58553 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10343 {}}} CYCLES {}}
+set a(0-10343) {NAME ACC1-1:exs#83 TYPE SIGNEXTEND PAR 0-9373 XREFS 58554 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10342 {}}} SUCCS {{258 0 0-10345 {}}} CYCLES {}}
+set a(0-10344) {NAME ACC1-1:slc(acc.imod#18)#11 TYPE READSLICE PAR 0-9373 XREFS 58555 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.4874251} PREDS {{258 0 0-9602 {}}} SUCCS {{259 0 0-10345 {}}} CYCLES {}}
+set a(0-10345) {NAME ACC1:conc#1441 TYPE CONCATENATE PAR 0-9373 XREFS 58556 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-10343 {}} {259 0 0-10344 {}}} SUCCS {{259 0 0-10346 {}}} CYCLES {}}
+set a(0-10346) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#694 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58557 LOC {1 0.356432775 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-10341 {}} {259 0 0-10345 {}}} SUCCS {{259 0 0-10347 {}}} CYCLES {}}
+set a(0-10347) {NAME ACC1:slc#158 TYPE READSLICE PAR 0-9373 XREFS 58558 LOC {1 0.40398894999999996 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-10346 {}}} SUCCS {{258 0 0-10357 {}}} CYCLES {}}
+set a(0-10348) {NAME ACC1-1:slc(acc.idiv#4)#19 TYPE READSLICE PAR 0-9373 XREFS 58559 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10349 {}}} CYCLES {}}
+set a(0-10349) {NAME ACC1-1:exs#81 TYPE SIGNEXTEND PAR 0-9373 XREFS 58560 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10348 {}}} SUCCS {{259 0 0-10350 {}}} CYCLES {}}
+set a(0-10350) {NAME ACC1:conc#1438 TYPE CONCATENATE PAR 0-9373 XREFS 58561 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10349 {}}} SUCCS {{258 0 0-10355 {}}} CYCLES {}}
+set a(0-10351) {NAME ACC1-1:slc(acc.idiv#4)#21 TYPE READSLICE PAR 0-9373 XREFS 58562 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.4874251} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10352 {}}} CYCLES {}}
+set a(0-10352) {NAME ACC1-1:exs#82 TYPE SIGNEXTEND PAR 0-9373 XREFS 58563 LOC {1 0.14655495 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{259 0 0-10351 {}}} SUCCS {{258 0 0-10354 {}}} CYCLES {}}
+set a(0-10353) {NAME ACC1-1:slc(ACC1:acc#217.psp)#9 TYPE READSLICE PAR 0-9373 XREFS 58564 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.4874251} PREDS {{258 0 0-9584 {}}} SUCCS {{259 0 0-10354 {}}} CYCLES {}}
+set a(0-10354) {NAME ACC1:conc#1439 TYPE CONCATENATE PAR 0-9373 XREFS 58565 LOC {1 0.267931 1 0.40793684999999996 1 0.40793684999999996 1 0.4874251} PREDS {{258 0 0-10352 {}} {259 0 0-10353 {}}} SUCCS {{259 0 0-10355 {}}} CYCLES {}}
+set a(0-10355) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#693 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58566 LOC {1 0.267931 1 0.40793684999999996 1 0.40793684999999996 1 0.45549297707082714 1 0.5349812270708272} PREDS {{258 0 0-10350 {}} {259 0 0-10354 {}}} SUCCS {{259 0 0-10356 {}}} CYCLES {}}
+set a(0-10356) {NAME ACC1:slc#157 TYPE READSLICE PAR 0-9373 XREFS 58567 LOC {1 0.315487175 1 0.455493025 1 0.455493025 1 0.5349812749999999} PREDS {{259 0 0-10355 {}}} SUCCS {{259 0 0-10357 {}}} CYCLES {}}
+set a(0-10357) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#701 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58568 LOC {1 0.40398894999999996 1 0.455493025 1 0.455493025 1 0.5030491520708271 1 0.582537402070827} PREDS {{258 0 0-10347 {}} {259 0 0-10356 {}}} SUCCS {{259 0 0-10358 {}}} CYCLES {}}
+set a(0-10358) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#706 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 58569 LOC {1 0.47879105 1 0.5030492 1 0.5030492 1 0.5563962201789505 1 0.6358844701789506} PREDS {{258 0 0-10338 {}} {259 0 0-10357 {}}} SUCCS {{259 0 0-10359 {}}} CYCLES {}}
+set a(0-10359) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 5 NAME ACC1:acc#709 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 58570 LOC {1 0.532138125 1 0.556396275 1 0.556396275 1 0.5995979984103024 1 0.6790862484103023} PREDS {{258 0 0-10315 {}} {259 0 0-10358 {}}} SUCCS {{259 0 0-10360 {}}} CYCLES {}}
+set a(0-10360) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#712 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-9373 XREFS 58571 LOC {1 0.5753399 1 0.59959805 1 0.59959805 1 0.6519825027684257 1 0.7314707527684257} PREDS {{258 0 0-10310 {}} {259 0 0-10359 {}}} SUCCS {{259 0 0-10361 {}}} CYCLES {}}
+set a(0-10361) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,1,11) AREA_SCORE 10.00 QUANTITY 5 NAME ACC1:acc#714 TYPE ACCU DELAY {0.91 ns} LIBRARY_DELAY {0.91 ns} PAR 0-9373 XREFS 58572 LOC {1 0.6277244 1 0.6519825499999999 1 0.6519825499999999 1 0.7087410628916543 1 0.7882293128916543} PREDS {{258 0 0-10304 {}} {259 0 0-10360 {}}} SUCCS {{258 0 0-10433 {}}} CYCLES {}}
+set a(0-10362) {NAME ACC1-1:slc(acc#20.psp)#29 TYPE READSLICE PAR 0-9373 XREFS 58573 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5312430499999999} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10363 {}}} CYCLES {}}
+set a(0-10363) {NAME ACC1:conc#1433 TYPE CONCATENATE PAR 0-9373 XREFS 58574 LOC {1 0.14655495 1 0.45175479999999996 1 0.45175479999999996 1 0.5312430499999999} PREDS {{259 0 0-10362 {}}} SUCCS {{259 0 0-10364 {}}} CYCLES {}}
+set a(0-10364) {NAME ACC1:conc#1434 TYPE CONCATENATE PAR 0-9373 XREFS 58575 LOC {1 0.14655495 1 0.45175479999999996 1 0.45175479999999996 1 0.5312430499999999} PREDS {{259 0 0-10363 {}}} SUCCS {{258 0 0-10368 {}}} CYCLES {}}
+set a(0-10365) {NAME ACC1-1:slc(ACC1:acc#217.psp)#10 TYPE READSLICE PAR 0-9373 XREFS 58576 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.5312430499999999} PREDS {{258 0 0-9584 {}}} SUCCS {{258 0 0-10367 {}}} CYCLES {}}
+set a(0-10366) {NAME ACC1-1:slc(acc#20.psp)#30 TYPE READSLICE PAR 0-9373 XREFS 58577 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5312430499999999} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10367 {}}} CYCLES {}}
+set a(0-10367) {NAME ACC1:conc#1435 TYPE CONCATENATE PAR 0-9373 XREFS 58578 LOC {1 0.267931 1 0.45175479999999996 1 0.45175479999999996 1 0.5312430499999999} PREDS {{258 0 0-10365 {}} {259 0 0-10366 {}}} SUCCS {{259 0 0-10368 {}}} CYCLES {}}
+set a(0-10368) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 4 NAME ACC1:acc#691 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-9373 XREFS 58579 LOC {1 0.267931 1 0.45175479999999996 1 0.45175479999999996 1 0.4893753770241716 1 0.5688636270241716} PREDS {{258 0 0-10364 {}} {259 0 0-10367 {}}} SUCCS {{259 0 0-10369 {}}} CYCLES {}}
+set a(0-10369) {NAME ACC1:slc#155 TYPE READSLICE PAR 0-9373 XREFS 58580 LOC {1 0.305551625 1 0.489375425 1 0.489375425 1 0.568863675} PREDS {{259 0 0-10368 {}}} SUCCS {{258 0 0-10371 {}}} CYCLES {}}
+set a(0-10370) {NAME ACC1-1:slc(ACC1:acc#223.psp)#2 TYPE READSLICE PAR 0-9373 XREFS 58581 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.568863675} PREDS {{258 0 0-9595 {}}} SUCCS {{259 0 0-10371 {}}} CYCLES {}}
+set a(0-10371) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 4 NAME ACC1:acc#700 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-9373 XREFS 58582 LOC {1 0.32918685 1 0.489375425 1 0.489375425 1 0.5269960020241716 1 0.6064842520241717} PREDS {{258 0 0-10369 {}} {259 0 0-10370 {}}} SUCCS {{258 0 0-10383 {}}} CYCLES {}}
+set a(0-10372) {NAME ACC1-1:slc(acc#20.psp)#31 TYPE READSLICE PAR 0-9373 XREFS 58583 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.579238375} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10374 {}}} CYCLES {}}
+set a(0-10373) {NAME ACC1-1:slc(acc#20.psp)#32 TYPE READSLICE PAR 0-9373 XREFS 58584 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.579238375} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10374 {}}} CYCLES {}}
+set a(0-10374) {NAME ACC1-1:conc#592 TYPE CONCATENATE PAR 0-9373 XREFS 58585 LOC {1 0.14655495 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{258 0 0-10372 {}} {259 0 0-10373 {}}} SUCCS {{259 0 0-10375 {}}} CYCLES {}}
+set a(0-10375) {NAME ACC1:conc#1436 TYPE CONCATENATE PAR 0-9373 XREFS 58586 LOC {1 0.14655495 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{259 0 0-10374 {}}} SUCCS {{258 0 0-10381 {}}} CYCLES {}}
+set a(0-10376) {NAME ACC1-1:slc(ACC1:acc#217.psp)#11 TYPE READSLICE PAR 0-9373 XREFS 58587 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.579238375} PREDS {{258 0 0-9584 {}}} SUCCS {{258 0 0-10378 {}}} CYCLES {}}
+set a(0-10377) {NAME ACC1-1:slc(acc#20.psp)#33 TYPE READSLICE PAR 0-9373 XREFS 58588 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.579238375} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10378 {}}} CYCLES {}}
+set a(0-10378) {NAME ACC1-1:conc#593 TYPE CONCATENATE PAR 0-9373 XREFS 58589 LOC {1 0.267931 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{258 0 0-10376 {}} {259 0 0-10377 {}}} SUCCS {{258 0 0-10380 {}}} CYCLES {}}
+set a(0-10379) {NAME ACC1-1:slc(ACC1:acc#217.psp)#8 TYPE READSLICE PAR 0-9373 XREFS 58590 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.579238375} PREDS {{258 0 0-9584 {}}} SUCCS {{259 0 0-10380 {}}} CYCLES {}}
+set a(0-10380) {NAME ACC1:conc#1437 TYPE CONCATENATE PAR 0-9373 XREFS 58591 LOC {1 0.267931 1 0.499750125 1 0.499750125 1 0.579238375} PREDS {{258 0 0-10378 {}} {259 0 0-10379 {}}} SUCCS {{259 0 0-10381 {}}} CYCLES {}}
+set a(0-10381) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#692 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58592 LOC {1 0.267931 1 0.499750125 1 0.499750125 1 0.5269960020708272 1 0.6064842520708271} PREDS {{258 0 0-10375 {}} {259 0 0-10380 {}}} SUCCS {{259 0 0-10382 {}}} CYCLES {}}
+set a(0-10382) {NAME ACC1:slc#156 TYPE READSLICE PAR 0-9373 XREFS 58593 LOC {1 0.295176925 1 0.5269960499999999 1 0.5269960499999999 1 0.6064843} PREDS {{259 0 0-10381 {}}} SUCCS {{259 0 0-10383 {}}} CYCLES {}}
+set a(0-10383) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#705 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 58594 LOC {1 0.366807475 1 0.5269960499999999 1 0.5269960499999999 1 0.5701879451789504 1 0.6496761951789505} PREDS {{258 0 0-10371 {}} {259 0 0-10382 {}}} SUCCS {{258 0 0-10395 {}}} CYCLES {}}
+set a(0-10384) {NAME ACC1-1:slc(acc#20.psp)#34 TYPE READSLICE PAR 0-9373 XREFS 58595 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.616639425} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10388 {}}} CYCLES {}}
+set a(0-10385) {NAME ACC1-1:slc(acc#20.psp)#35 TYPE READSLICE PAR 0-9373 XREFS 58596 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.616639425} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10388 {}}} CYCLES {}}
+set a(0-10386) {NAME ACC1-1:slc(acc.idiv#4)#31 TYPE READSLICE PAR 0-9373 XREFS 58597 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.616639425} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10387 {}}} CYCLES {}}
+set a(0-10387) {NAME ACC1-1:exs#87 TYPE SIGNEXTEND PAR 0-9373 XREFS 58598 LOC {1 0.14655495 1 0.537151175 1 0.537151175 1 0.616639425} PREDS {{259 0 0-10386 {}}} SUCCS {{259 0 0-10388 {}}} CYCLES {}}
+set a(0-10388) {NAME ACC1-1:conc#594 TYPE CONCATENATE PAR 0-9373 XREFS 58599 LOC {1 0.14655495 1 0.537151175 1 0.537151175 1 0.616639425} PREDS {{258 0 0-10385 {}} {258 0 0-10384 {}} {259 0 0-10387 {}}} SUCCS {{258 0 0-10394 {}}} CYCLES {}}
+set a(0-10389) {NAME ACC1-1:slc(acc.idiv#4)#33 TYPE READSLICE PAR 0-9373 XREFS 58600 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.575856375} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10390 {}}} CYCLES {}}
+set a(0-10390) {NAME ACC1-1:exs#88 TYPE SIGNEXTEND PAR 0-9373 XREFS 58601 LOC {1 0.14655495 1 0.496368125 1 0.496368125 1 0.575856375} PREDS {{259 0 0-10389 {}}} SUCCS {{258 0 0-10393 {}}} CYCLES {}}
+set a(0-10391) {NAME ACC1-1:slc(acc.idiv#4)#35 TYPE READSLICE PAR 0-9373 XREFS 58602 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.575856375} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10392 {}}} CYCLES {}}
+set a(0-10392) {NAME ACC1-1:exs#89 TYPE SIGNEXTEND PAR 0-9373 XREFS 58603 LOC {1 0.14655495 1 0.496368125 1 0.496368125 1 0.575856375} PREDS {{259 0 0-10391 {}}} SUCCS {{259 0 0-10393 {}}} CYCLES {}}
+set a(0-10393) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#699 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58604 LOC {1 0.14655495 1 0.496368125 1 0.496368125 1 0.5371511350894752 1 0.6166393850894752} PREDS {{258 0 0-10390 {}} {259 0 0-10392 {}}} SUCCS {{259 0 0-10394 {}}} CYCLES {}}
+set a(0-10394) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#704 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 58605 LOC {1 0.187338 1 0.537151175 1 0.537151175 1 0.5701879451789504 1 0.6496761951789505} PREDS {{258 0 0-10388 {}} {259 0 0-10393 {}}} SUCCS {{259 0 0-10395 {}}} CYCLES {}}
+set a(0-10395) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#708 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-9373 XREFS 58606 LOC {1 0.409999425 1 0.570188 1 0.570188 1 0.6084774594969361 1 0.687965709496936} PREDS {{258 0 0-10383 {}} {259 0 0-10394 {}}} SUCCS {{258 0 0-10401 {}}} CYCLES {}}
+set a(0-10396) {NAME ACC1-1:slc(acc#20.psp)#54 TYPE READSLICE PAR 0-9373 XREFS 58607 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10400 {}}} CYCLES {}}
+set a(0-10397) {NAME ACC1-1:slc(acc#20.psp)#55 TYPE READSLICE PAR 0-9373 XREFS 58608 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10400 {}}} CYCLES {}}
+set a(0-10398) {NAME ACC1-1:slc(acc#20.psp)#56 TYPE READSLICE PAR 0-9373 XREFS 58609 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10400 {}}} CYCLES {}}
+set a(0-10399) {NAME ACC1-1:slc(acc#20.psp)#47 TYPE READSLICE PAR 0-9373 XREFS 58610 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10400 {}}} CYCLES {}}
+set a(0-10400) {NAME ACC1-1:conc#589 TYPE CONCATENATE PAR 0-9373 XREFS 58611 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{258 0 0-10398 {}} {258 0 0-10397 {}} {258 0 0-10396 {}} {259 0 0-10399 {}}} SUCCS {{259 0 0-10401 {}}} CYCLES {}}
+set a(0-10401) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 6 NAME ACC1:acc#711 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-9373 XREFS 58612 LOC {1 0.448288925 1 0.6084775 1 0.6084775 1 0.656356562932968 1 0.7358448129329679} PREDS {{258 0 0-10395 {}} {259 0 0-10400 {}}} SUCCS {{258 0 0-10432 {}}} CYCLES {}}
+set a(0-10402) {NAME ACC1-1:slc(acc#20.psp)#17 TYPE READSLICE PAR 0-9373 XREFS 58613 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10405 {}}} CYCLES {}}
+set a(0-10403) {NAME ACC1-1:slc(acc.idiv#4)#25 TYPE READSLICE PAR 0-9373 XREFS 58614 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6879657499999999} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10404 {}}} CYCLES {}}
+set a(0-10404) {NAME ACC1-1:exs#84 TYPE SIGNEXTEND PAR 0-9373 XREFS 58615 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{259 0 0-10403 {}}} SUCCS {{259 0 0-10405 {}}} CYCLES {}}
+set a(0-10405) {NAME ACC1-1:conc#538 TYPE CONCATENATE PAR 0-9373 XREFS 58616 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{258 0 0-10402 {}} {259 0 0-10404 {}}} SUCCS {{259 0 0-10406 {}}} CYCLES {}}
+set a(0-10406) {NAME ACC1-1:exs#1040 TYPE SIGNEXTEND PAR 0-9373 XREFS 58617 LOC {1 0.14655495 1 0.6084775 1 0.6084775 1 0.6879657499999999} PREDS {{259 0 0-10405 {}}} SUCCS {{258 0 0-10431 {}}} CYCLES {}}
+set a(0-10407) {NAME ACC1-1:slc(acc#20.psp)#52 TYPE READSLICE PAR 0-9373 XREFS 58618 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.64967625} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10410 {}}} CYCLES {}}
+set a(0-10408) {NAME ACC1-1:slc(acc#20.psp)#53 TYPE READSLICE PAR 0-9373 XREFS 58619 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.64967625} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10410 {}}} CYCLES {}}
+set a(0-10409) {NAME ACC1-1:slc(acc#20.psp)#46 TYPE READSLICE PAR 0-9373 XREFS 58620 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.64967625} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10410 {}}} CYCLES {}}
+set a(0-10410) {NAME ACC1-1:conc#588 TYPE CONCATENATE PAR 0-9373 XREFS 58621 LOC {1 0.14655495 1 0.570188 1 0.570188 1 0.64967625} PREDS {{258 0 0-10408 {}} {258 0 0-10407 {}} {259 0 0-10409 {}}} SUCCS {{258 0 0-10430 {}}} CYCLES {}}
+set a(0-10411) {NAME ACC1-1:slc(acc.idiv#4)#9 TYPE READSLICE PAR 0-9373 XREFS 58622 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5613370249999999} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10412 {}}} CYCLES {}}
+set a(0-10412) {NAME ACC1-1:exs#76 TYPE SIGNEXTEND PAR 0-9373 XREFS 58623 LOC {1 0.14655495 1 0.48184877499999995 1 0.48184877499999995 1 0.5613370249999999} PREDS {{259 0 0-10411 {}}} SUCCS {{258 0 0-10415 {}}} CYCLES {}}
+set a(0-10413) {NAME ACC1-1:slc(acc.idiv#4)#11 TYPE READSLICE PAR 0-9373 XREFS 58624 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5613370249999999} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10414 {}}} CYCLES {}}
+set a(0-10414) {NAME ACC1-1:exs#77 TYPE SIGNEXTEND PAR 0-9373 XREFS 58625 LOC {1 0.14655495 1 0.48184877499999995 1 0.48184877499999995 1 0.5613370249999999} PREDS {{259 0 0-10413 {}}} SUCCS {{259 0 0-10415 {}}} CYCLES {}}
+set a(0-10415) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#698 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 58626 LOC {1 0.14655495 1 0.48184877499999995 1 0.48184877499999995 1 0.5226317850894752 1 0.6021200350894752} PREDS {{258 0 0-10412 {}} {259 0 0-10414 {}}} SUCCS {{258 0 0-10429 {}}} CYCLES {}}
+set a(0-10416) {NAME ACC1-1:slc(acc.idiv#4)#1 TYPE READSLICE PAR 0-9373 XREFS 58627 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5545639} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10417 {}}} CYCLES {}}
+set a(0-10417) {NAME ACC1-1:exs#72 TYPE SIGNEXTEND PAR 0-9373 XREFS 58628 LOC {1 0.14655495 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{259 0 0-10416 {}}} SUCCS {{259 0 0-10418 {}}} CYCLES {}}
+set a(0-10418) {NAME ACC1:conc#1446 TYPE CONCATENATE PAR 0-9373 XREFS 58629 LOC {1 0.14655495 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{259 0 0-10417 {}}} SUCCS {{258 0 0-10427 {}}} CYCLES {}}
+set a(0-10419) {NAME ACC1-1:slc(acc.idiv#4)#3 TYPE READSLICE PAR 0-9373 XREFS 58630 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5545639} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10420 {}}} CYCLES {}}
+set a(0-10420) {NAME ACC1-1:exs#73 TYPE SIGNEXTEND PAR 0-9373 XREFS 58631 LOC {1 0.14655495 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{259 0 0-10419 {}}} SUCCS {{258 0 0-10426 {}}} CYCLES {}}
+set a(0-10421) {NAME ACC1-1:slc(acc.idiv#4)#45 TYPE READSLICE PAR 0-9373 XREFS 58632 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.5545639} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10425 {}}} CYCLES {}}
+set a(0-10422) {NAME ACC1-1:slc(acc.imod#19)#1 TYPE READSLICE PAR 0-9373 XREFS 58633 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{258 0 0-9611 {}}} SUCCS {{259 0 0-10423 {}}} CYCLES {}}
+set a(0-10423) {NAME ACC1-1:not#156 TYPE NOT PAR 0-9373 XREFS 58634 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{259 0 0-10422 {}}} SUCCS {{258 0 0-10425 {}}} CYCLES {}}
+set a(0-10424) {NAME ACC1-1:slc(acc.imod#19)#2 TYPE READSLICE PAR 0-9373 XREFS 58635 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{258 0 0-9611 {}}} SUCCS {{259 0 0-10425 {}}} CYCLES {}}
+set a(0-10425) {NAME ACC1-1:and#9 TYPE AND PAR 0-9373 XREFS 58636 LOC {1 0.3836787 1 0.40793684999999996 1 0.40793684999999996 1 0.5545639} PREDS {{258 0 0-10423 {}} {258 0 0-10421 {}} {259 0 0-10424 {}}} SUCCS {{259 0 0-10426 {}}} CYCLES {}}
+set a(0-10426) {NAME ACC1:conc#1447 TYPE CONCATENATE PAR 0-9373 XREFS 58637 LOC {1 0.3836787 1 0.47507564999999996 1 0.47507564999999996 1 0.5545639} PREDS {{258 0 0-10420 {}} {259 0 0-10425 {}}} SUCCS {{259 0 0-10427 {}}} CYCLES {}}
+set a(0-10427) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#697 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58638 LOC {1 0.3836787 1 0.47507564999999996 1 0.47507564999999996 1 0.5226317770708271 1 0.6021200270708271} PREDS {{258 0 0-10418 {}} {259 0 0-10426 {}}} SUCCS {{259 0 0-10428 {}}} CYCLES {}}
+set a(0-10428) {NAME ACC1:slc#161 TYPE READSLICE PAR 0-9373 XREFS 58639 LOC {1 0.43123487499999996 1 0.5226318249999999 1 0.5226318249999999 1 0.602120075} PREDS {{259 0 0-10427 {}}} SUCCS {{259 0 0-10429 {}}} CYCLES {}}
+set a(0-10429) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#703 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58640 LOC {1 0.43123487499999996 1 0.5226318249999999 1 0.5226318249999999 1 0.5701879520708271 1 0.6496762020708271} PREDS {{258 0 0-10415 {}} {259 0 0-10428 {}}} SUCCS {{259 0 0-10430 {}}} CYCLES {}}
+set a(0-10430) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#707 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-9373 XREFS 58641 LOC {1 0.47879105 1 0.570188 1 0.570188 1 0.6084774594969361 1 0.687965709496936} PREDS {{258 0 0-10410 {}} {259 0 0-10429 {}}} SUCCS {{259 0 0-10431 {}}} CYCLES {}}
+set a(0-10431) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 6 NAME ACC1:acc#710 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-9373 XREFS 58642 LOC {1 0.51708055 1 0.6084775 1 0.6084775 1 0.656356562932968 1 0.7358448129329679} PREDS {{258 0 0-10406 {}} {259 0 0-10430 {}}} SUCCS {{259 0 0-10432 {}}} CYCLES {}}
+set a(0-10432) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#713 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-9373 XREFS 58643 LOC {1 0.564959675 1 0.6563566249999999 1 0.6563566249999999 1 0.7087410777684257 1 0.7882293277684257} PREDS {{258 0 0-10401 {}} {259 0 0-10431 {}}} SUCCS {{259 0 0-10433 {}}} CYCLES {}}
+set a(0-10433) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,12) AREA_SCORE 11.00 QUANTITY 4 NAME ACC1:acc#716 TYPE ACCU DELAY {0.98 ns} LIBRARY_DELAY {0.98 ns} PAR 0-9373 XREFS 58644 LOC {1 0.684482975 1 0.708741125 1 0.708741125 1 0.7697701033364113 1 0.8492583533364113} PREDS {{258 0 0-10361 {}} {259 0 0-10432 {}}} SUCCS {{258 0 0-10445 {}}} CYCLES {}}
+set a(0-10434) {NAME ACC1-1:slc(acc#20.psp)#62 TYPE READSLICE PAR 0-9373 XREFS 58645 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10436 {}}} CYCLES {}}
+set a(0-10435) {NAME ACC1-1:slc(acc#20.psp)#49 TYPE READSLICE PAR 0-9373 XREFS 58646 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10436 {}}} CYCLES {}}
+set a(0-10436) {NAME ACC1-1:conc#591 TYPE CONCATENATE PAR 0-9373 XREFS 58647 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7679191249999999} PREDS {{258 0 0-10434 {}} {259 0 0-10435 {}}} SUCCS {{258 0 0-10444 {}}} CYCLES {}}
+set a(0-10437) {NAME ACC1-1:slc(acc#20.psp)#66 TYPE READSLICE PAR 0-9373 XREFS 58648 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10443 {}}} CYCLES {}}
+set a(0-10438) {NAME ACC1-1:slc(acc#20.psp)#67 TYPE READSLICE PAR 0-9373 XREFS 58649 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10443 {}}} CYCLES {}}
+set a(0-10439) {NAME ACC1-1:slc(acc#20.psp)#68 TYPE READSLICE PAR 0-9373 XREFS 58650 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10443 {}}} CYCLES {}}
+set a(0-10440) {NAME ACC1-1:slc(acc#20.psp)#51 TYPE READSLICE PAR 0-9373 XREFS 58651 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9544 {}}} SUCCS {{258 0 0-10443 {}}} CYCLES {}}
+set a(0-10441) {NAME ACC1-1:slc(acc.idiv#4)#27 TYPE READSLICE PAR 0-9373 XREFS 58652 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7679191249999999} PREDS {{258 0 0-9544 {}}} SUCCS {{259 0 0-10442 {}}} CYCLES {}}
+set a(0-10442) {NAME ACC1-1:exs#85 TYPE SIGNEXTEND PAR 0-9373 XREFS 58653 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7679191249999999} PREDS {{259 0 0-10441 {}}} SUCCS {{259 0 0-10443 {}}} CYCLES {}}
+set a(0-10443) {NAME ACC1-1:conc#597 TYPE CONCATENATE PAR 0-9373 XREFS 58654 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7679191249999999} PREDS {{258 0 0-10440 {}} {258 0 0-10439 {}} {258 0 0-10438 {}} {258 0 0-10437 {}} {259 0 0-10442 {}}} SUCCS {{259 0 0-10444 {}}} CYCLES {}}
+set a(0-10444) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,11) AREA_SCORE 11.24 QUANTITY 3 NAME ACC1:acc#715 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-9373 XREFS 58655 LOC {1 0.14655495 1 0.688430875 1 0.688430875 1 0.7697701033364113 1 0.8492583533364112} PREDS {{258 0 0-10436 {}} {259 0 0-10443 {}}} SUCCS {{259 0 0-10445 {}}} CYCLES {}}
+set a(0-10445) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1-1:acc#27 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 58656 LOC {1 0.745512 1 0.7697701499999999 1 0.7697701499999999 1 0.8451409063734283 1 0.9246291563734284} PREDS {{258 0 0-10433 {}} {259 0 0-10444 {}}} SUCCS {{259 0 0-10446 {}}} CYCLES {}}
+set a(0-10446) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1:acc#653 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 58657 LOC {1 0.8208827999999999 1 0.84514095 1 0.84514095 1 0.9205117063734284 1 0.9999999563734283} PREDS {{258 0 0-10298 {}} {259 0 0-10445 {}}} SUCCS {{259 0 0-10447 {}}} CYCLES {}}
+set a(0-10447) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 4 NAME ACC1:acc#659 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-9373 XREFS 58658 LOC {1 0.8962536 1 0.92051175 1 0.92051175 1 0.9999999534997777 2 0.13630012849977768} PREDS {{258 0 0-10160 {}} {259 0 0-10446 {}}} SUCCS {{258 0 0-10572 {}}} CYCLES {}}
+set a(0-10448) {NAME ACC1:slc(ACC1:acc#224.psp#1)#26 TYPE READSLICE PAR 0-9373 XREFS 58659 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6588744249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{258 0 0-10452 {}}} CYCLES {}}
+set a(0-10449) {NAME ACC1:slc(ACC1:acc#228.psp)#53 TYPE READSLICE PAR 0-9373 XREFS 58660 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6588744249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{258 0 0-10452 {}}} CYCLES {}}
+set a(0-10450) {NAME ACC1-3:slc(acc#10.psp)#69 TYPE READSLICE PAR 0-9373 XREFS 58661 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6588744249999999} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10451 {}}} CYCLES {}}
+set a(0-10451) {NAME ACC1-3:exs#50 TYPE SIGNEXTEND PAR 0-9373 XREFS 58662 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{259 0 0-10450 {}}} SUCCS {{259 0 0-10452 {}}} CYCLES {}}
+set a(0-10452) {NAME ACC1:conc#1108 TYPE CONCATENATE PAR 0-9373 XREFS 58663 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{258 0 0-10449 {}} {258 0 0-10448 {}} {259 0 0-10451 {}}} SUCCS {{258 0 0-10458 {}}} CYCLES {}}
+set a(0-10453) {NAME ACC1:slc(ACC1-1:acc#25.psp)#21 TYPE READSLICE PAR 0-9373 XREFS 58664 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6588744249999999} PREDS {{258 0 0-9616 {}}} SUCCS {{258 0 0-10457 {}}} CYCLES {}}
+set a(0-10454) {NAME ACC1:slc(ACC1:acc#226.psp)#44 TYPE READSLICE PAR 0-9373 XREFS 58665 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6588744249999999} PREDS {{258 0 0-9767 {}}} SUCCS {{258 0 0-10457 {}}} CYCLES {}}
+set a(0-10455) {NAME ACC1:slc(acc#5.psp#2)#31 TYPE READSLICE PAR 0-9373 XREFS 58666 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6588744249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-10456 {}}} CYCLES {}}
+set a(0-10456) {NAME ACC1-2:exs#34 TYPE SIGNEXTEND PAR 0-9373 XREFS 58667 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{259 0 0-10455 {}}} SUCCS {{259 0 0-10457 {}}} CYCLES {}}
+set a(0-10457) {NAME ACC1:conc#1109 TYPE CONCATENATE PAR 0-9373 XREFS 58668 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{258 0 0-10454 {}} {258 0 0-10453 {}} {259 0 0-10456 {}}} SUCCS {{259 0 0-10458 {}}} CYCLES {}}
+set a(0-10458) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#572 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 58669 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6327331951789505 1 0.7122214451789504} PREDS {{258 0 0-10452 {}} {259 0 0-10457 {}}} SUCCS {{258 0 0-10470 {}}} CYCLES {}}
+set a(0-10459) {NAME ACC1:slc(ACC1-1:acc#25.psp)#22 TYPE READSLICE PAR 0-9373 XREFS 58670 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6588744249999999} PREDS {{258 0 0-9616 {}}} SUCCS {{258 0 0-10463 {}}} CYCLES {}}
+set a(0-10460) {NAME ACC1:slc(ACC1:acc#224.psp#1)#27 TYPE READSLICE PAR 0-9373 XREFS 58671 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6588744249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{258 0 0-10463 {}}} CYCLES {}}
+set a(0-10461) {NAME ACC1:slc(acc#5.psp#2)#32 TYPE READSLICE PAR 0-9373 XREFS 58672 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6588744249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-10462 {}}} CYCLES {}}
+set a(0-10462) {NAME ACC1-2:exs#35 TYPE SIGNEXTEND PAR 0-9373 XREFS 58673 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{259 0 0-10461 {}}} SUCCS {{259 0 0-10463 {}}} CYCLES {}}
+set a(0-10463) {NAME ACC1:conc#1110 TYPE CONCATENATE PAR 0-9373 XREFS 58674 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{258 0 0-10460 {}} {258 0 0-10459 {}} {259 0 0-10462 {}}} SUCCS {{258 0 0-10469 {}}} CYCLES {}}
+set a(0-10464) {NAME ACC1:slc(acc#20.psp#1)#35 TYPE READSLICE PAR 0-9373 XREFS 58675 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6588744249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10468 {}}} CYCLES {}}
+set a(0-10465) {NAME ACC1:slc(ACC1-1:acc#25.psp)#23 TYPE READSLICE PAR 0-9373 XREFS 58676 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6588744249999999} PREDS {{258 0 0-9616 {}}} SUCCS {{258 0 0-10468 {}}} CYCLES {}}
+set a(0-10466) {NAME ACC1:slc(acc#5.psp#2)#33 TYPE READSLICE PAR 0-9373 XREFS 58677 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6588744249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-10467 {}}} CYCLES {}}
+set a(0-10467) {NAME ACC1-2:exs#22 TYPE SIGNEXTEND PAR 0-9373 XREFS 58678 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{259 0 0-10466 {}}} SUCCS {{259 0 0-10468 {}}} CYCLES {}}
+set a(0-10468) {NAME ACC1:conc#1111 TYPE CONCATENATE PAR 0-9373 XREFS 58679 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6588744249999999} PREDS {{258 0 0-10465 {}} {258 0 0-10464 {}} {259 0 0-10467 {}}} SUCCS {{259 0 0-10469 {}}} CYCLES {}}
+set a(0-10469) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#571 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 58680 LOC {1 0.14655495 1 0.579386175 1 0.579386175 1 0.6327331951789505 1 0.7122214451789504} PREDS {{258 0 0-10463 {}} {259 0 0-10468 {}}} SUCCS {{259 0 0-10470 {}}} CYCLES {}}
+set a(0-10470) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#601 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-9373 XREFS 58681 LOC {1 0.19990202499999998 1 0.63273325 1 0.63273325 1 0.6913329594969361 1 0.770821209496936} PREDS {{258 0 0-10458 {}} {259 0 0-10469 {}}} SUCCS {{258 0 0-10504 {}}} CYCLES {}}
+set a(0-10471) {NAME ACC1:slc(ACC1:acc#217.psp#1)#15 TYPE READSLICE PAR 0-9373 XREFS 58682 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.679184675} PREDS {{258 0 0-10105 {}}} SUCCS {{259 0 0-10472 {}}} CYCLES {}}
+set a(0-10472) {NAME ACC1:not#383 TYPE NOT PAR 0-9373 XREFS 58683 LOC {1 0.267931 1 0.599696425 1 0.599696425 1 0.679184675} PREDS {{259 0 0-10471 {}}} SUCCS {{258 0 0-10477 {}}} CYCLES {}}
+set a(0-10473) {NAME ACC1:slc(ACC1:acc#210.psp#1)#15 TYPE READSLICE PAR 0-9373 XREFS 58684 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.679184675} PREDS {{258 0 0-9879 {}}} SUCCS {{259 0 0-10474 {}}} CYCLES {}}
+set a(0-10474) {NAME ACC1:not#384 TYPE NOT PAR 0-9373 XREFS 58685 LOC {1 0.267931 1 0.599696425 1 0.599696425 1 0.679184675} PREDS {{259 0 0-10473 {}}} SUCCS {{258 0 0-10477 {}}} CYCLES {}}
+set a(0-10475) {NAME ACC1:slc(acc.imod#42)#2 TYPE READSLICE PAR 0-9373 XREFS 58686 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.679184675} PREDS {{258 0 0-9674 {}}} SUCCS {{259 0 0-10476 {}}} CYCLES {}}
+set a(0-10476) {NAME ACC1:not#385 TYPE NOT PAR 0-9373 XREFS 58687 LOC {1 0.356432775 1 0.599696425 1 0.599696425 1 0.679184675} PREDS {{259 0 0-10475 {}}} SUCCS {{259 0 0-10477 {}}} CYCLES {}}
+set a(0-10477) {NAME ACC1:conc#1112 TYPE CONCATENATE PAR 0-9373 XREFS 58688 LOC {1 0.356432775 1 0.599696425 1 0.599696425 1 0.679184675} PREDS {{258 0 0-10474 {}} {258 0 0-10472 {}} {259 0 0-10476 {}}} SUCCS {{258 0 0-10483 {}}} CYCLES {}}
+set a(0-10478) {NAME ACC1:slc(acc.psp#2)#10 TYPE READSLICE PAR 0-9373 XREFS 58689 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.679184675} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10482 {}}} CYCLES {}}
+set a(0-10479) {NAME ACC1:slc(acc#20.psp#1)#36 TYPE READSLICE PAR 0-9373 XREFS 58690 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.679184675} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10482 {}}} CYCLES {}}
+set a(0-10480) {NAME ACC1:slc(acc#5.psp#2)#34 TYPE READSLICE PAR 0-9373 XREFS 58691 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.679184675} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-10481 {}}} CYCLES {}}
+set a(0-10481) {NAME ACC1-2:exs#23 TYPE SIGNEXTEND PAR 0-9373 XREFS 58692 LOC {1 0.14655495 1 0.599696425 1 0.599696425 1 0.679184675} PREDS {{259 0 0-10480 {}}} SUCCS {{259 0 0-10482 {}}} CYCLES {}}
+set a(0-10482) {NAME ACC1:conc#1113 TYPE CONCATENATE PAR 0-9373 XREFS 58693 LOC {1 0.14655495 1 0.599696425 1 0.599696425 1 0.679184675} PREDS {{258 0 0-10479 {}} {258 0 0-10478 {}} {259 0 0-10481 {}}} SUCCS {{259 0 0-10483 {}}} CYCLES {}}
+set a(0-10483) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#570 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 58694 LOC {1 0.356432775 1 0.599696425 1 0.599696425 1 0.6530434451789504 1 0.7325316951789504} PREDS {{258 0 0-10477 {}} {259 0 0-10482 {}}} SUCCS {{258 0 0-10503 {}}} CYCLES {}}
+set a(0-10484) {NAME ACC1-3:slc(acc.idiv#4)#45 TYPE READSLICE PAR 0-9373 XREFS 58695 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6577296499999999} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10488 {}}} CYCLES {}}
+set a(0-10485) {NAME ACC1-3:slc(acc.imod#19)#1 TYPE READSLICE PAR 0-9373 XREFS 58696 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.6577296499999999} PREDS {{258 0 0-10132 {}}} SUCCS {{259 0 0-10486 {}}} CYCLES {}}
+set a(0-10486) {NAME ACC1-3:not#156 TYPE NOT PAR 0-9373 XREFS 58697 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.6577296499999999} PREDS {{259 0 0-10485 {}}} SUCCS {{258 0 0-10488 {}}} CYCLES {}}
+set a(0-10487) {NAME ACC1-3:slc(acc.imod#19)#2 TYPE READSLICE PAR 0-9373 XREFS 58698 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.6577296499999999} PREDS {{258 0 0-10132 {}}} SUCCS {{259 0 0-10488 {}}} CYCLES {}}
+set a(0-10488) {NAME ACC1-3:and#9 TYPE AND PAR 0-9373 XREFS 58699 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.6577296499999999} PREDS {{258 0 0-10486 {}} {258 0 0-10484 {}} {259 0 0-10487 {}}} SUCCS {{258 0 0-10490 {}}} CYCLES {}}
+set a(0-10489) {NAME ACC1:slc(ACC1:acc#224.psp#1)#20 TYPE READSLICE PAR 0-9373 XREFS 58700 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6577296499999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-10490 {}}} CYCLES {}}
+set a(0-10490) {NAME ACC1:conc#1095 TYPE CONCATENATE PAR 0-9373 XREFS 58701 LOC {1 0.3836787 1 0.5782414 1 0.5782414 1 0.6577296499999999} PREDS {{258 0 0-10488 {}} {259 0 0-10489 {}}} SUCCS {{259 0 0-10491 {}}} CYCLES {}}
+set a(0-10491) {NAME ACC1:conc#1308 TYPE CONCATENATE PAR 0-9373 XREFS 58702 LOC {1 0.3836787 1 0.5782414 1 0.5782414 1 0.6577296499999999} PREDS {{259 0 0-10490 {}}} SUCCS {{258 0 0-10497 {}}} CYCLES {}}
+set a(0-10492) {NAME ACC1:slc(acc.psp#2)#8 TYPE READSLICE PAR 0-9373 XREFS 58703 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6577296499999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10494 {}}} CYCLES {}}
+set a(0-10493) {NAME ACC1:slc(ACC1:acc#224.psp#1)#21 TYPE READSLICE PAR 0-9373 XREFS 58704 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6577296499999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-10494 {}}} CYCLES {}}
+set a(0-10494) {NAME ACC1:conc#1096 TYPE CONCATENATE PAR 0-9373 XREFS 58705 LOC {1 0.14655495 1 0.5782414 1 0.5782414 1 0.6577296499999999} PREDS {{258 0 0-10492 {}} {259 0 0-10493 {}}} SUCCS {{258 0 0-10496 {}}} CYCLES {}}
+set a(0-10495) {NAME ACC1:slc(ACC1-1:acc#25.psp)#16 TYPE READSLICE PAR 0-9373 XREFS 58706 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6577296499999999} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10496 {}}} CYCLES {}}
+set a(0-10496) {NAME ACC1:conc#1309 TYPE CONCATENATE PAR 0-9373 XREFS 58707 LOC {1 0.14655495 1 0.5782414 1 0.5782414 1 0.6577296499999999} PREDS {{258 0 0-10494 {}} {259 0 0-10495 {}}} SUCCS {{259 0 0-10497 {}}} CYCLES {}}
+set a(0-10497) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#425 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58708 LOC {1 0.3836787 1 0.5782414 1 0.5782414 1 0.6257975270708271 1 0.7052857770708271} PREDS {{258 0 0-10491 {}} {259 0 0-10496 {}}} SUCCS {{259 0 0-10498 {}}} CYCLES {}}
+set a(0-10498) {NAME ACC1:slc#93 TYPE READSLICE PAR 0-9373 XREFS 58709 LOC {1 0.43123487499999996 1 0.625797575 1 0.625797575 1 0.7052858249999999} PREDS {{259 0 0-10497 {}}} SUCCS {{258 0 0-10502 {}}} CYCLES {}}
+set a(0-10499) {NAME ACC1:slc(ACC1:acc#223.psp) TYPE READSLICE PAR 0-9373 XREFS 58710 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.7052858249999999} PREDS {{258 0 0-10116 {}}} SUCCS {{258 0 0-10501 {}}} CYCLES {}}
+set a(0-10500) {NAME ACC1:slc(ACC1:acc#224.psp#1)#22 TYPE READSLICE PAR 0-9373 XREFS 58711 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.7052858249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-10501 {}}} CYCLES {}}
+set a(0-10501) {NAME ACC1:conc#1097 TYPE CONCATENATE PAR 0-9373 XREFS 58712 LOC {1 0.32918685 1 0.625797575 1 0.625797575 1 0.7052858249999999} PREDS {{258 0 0-10499 {}} {259 0 0-10500 {}}} SUCCS {{259 0 0-10502 {}}} CYCLES {}}
+set a(0-10502) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#524 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58713 LOC {1 0.43123487499999996 1 0.625797575 1 0.625797575 1 0.6530434520708271 1 0.7325317020708271} PREDS {{258 0 0-10498 {}} {259 0 0-10501 {}}} SUCCS {{259 0 0-10503 {}}} CYCLES {}}
+set a(0-10503) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME ACC1:acc#600 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-9373 XREFS 58714 LOC {1 0.45848079999999997 1 0.6530435 1 0.6530435 1 0.6913329594969361 1 0.770821209496936} PREDS {{258 0 0-10483 {}} {259 0 0-10502 {}}} SUCCS {{259 0 0-10504 {}}} CYCLES {}}
+set a(0-10504) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#620 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-9373 XREFS 58715 LOC {1 0.4967703 1 0.691333 1 0.691333 1 0.7548449734103024 1 0.8343332234103025} PREDS {{258 0 0-10470 {}} {259 0 0-10503 {}}} SUCCS {{258 0 0-10529 {}}} CYCLES {}}
+set a(0-10505) {NAME ACC1-3:slc(acc.idiv#1)#15 TYPE READSLICE PAR 0-9373 XREFS 58716 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.720693625} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10506 {}}} CYCLES {}}
+set a(0-10506) {NAME ACC1-3:exs#25 TYPE SIGNEXTEND PAR 0-9373 XREFS 58717 LOC {1 0.14655495 1 0.641205375 1 0.641205375 1 0.720693625} PREDS {{259 0 0-10505 {}}} SUCCS {{259 0 0-10507 {}}} CYCLES {}}
+set a(0-10507) {NAME ACC1:conc#1344 TYPE CONCATENATE PAR 0-9373 XREFS 58718 LOC {1 0.14655495 1 0.641205375 1 0.641205375 1 0.720693625} PREDS {{259 0 0-10506 {}}} SUCCS {{258 0 0-10511 {}}} CYCLES {}}
+set a(0-10508) {NAME ACC1:slc(ACC1:acc#220.psp#1) TYPE READSLICE PAR 0-9373 XREFS 58719 LOC {1 0.32918685 1 0.353445 1 0.353445 1 0.720693625} PREDS {{258 0 0-9437 {}}} SUCCS {{258 0 0-10510 {}}} CYCLES {}}
+set a(0-10509) {NAME ACC1:slc(acc.imod#31) TYPE READSLICE PAR 0-9373 XREFS 58720 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.720693625} PREDS {{258 0 0-9750 {}}} SUCCS {{259 0 0-10510 {}}} CYCLES {}}
+set a(0-10510) {NAME ACC1:conc#1345 TYPE CONCATENATE PAR 0-9373 XREFS 58721 LOC {1 0.3471661 1 0.641205375 1 0.641205375 1 0.720693625} PREDS {{258 0 0-10508 {}} {259 0 0-10509 {}}} SUCCS {{259 0 0-10511 {}}} CYCLES {}}
+set a(0-10511) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#443 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58722 LOC {1 0.3471661 1 0.641205375 1 0.641205375 1 0.6684512520708271 1 0.7479395020708272} PREDS {{258 0 0-10507 {}} {259 0 0-10510 {}}} SUCCS {{259 0 0-10512 {}}} CYCLES {}}
+set a(0-10512) {NAME ACC1:slc#111 TYPE READSLICE PAR 0-9373 XREFS 58723 LOC {1 0.374412025 1 0.6684513 1 0.6684513 1 0.74793955} PREDS {{259 0 0-10511 {}}} SUCCS {{258 0 0-10518 {}}} CYCLES {}}
+set a(0-10513) {NAME ACC1:slc(ACC1:acc#224.psp#1)#25 TYPE READSLICE PAR 0-9373 XREFS 58724 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.74793955} PREDS {{258 0 0-9471 {}}} SUCCS {{258 0 0-10517 {}}} CYCLES {}}
+set a(0-10514) {NAME ACC1:slc(ACC1:acc#224.psp)#53 TYPE READSLICE PAR 0-9373 XREFS 58725 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.74793955} PREDS {{258 0 0-9993 {}}} SUCCS {{258 0 0-10517 {}}} CYCLES {}}
+set a(0-10515) {NAME ACC1-3:slc(acc#10.psp)#70 TYPE READSLICE PAR 0-9373 XREFS 58726 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.74793955} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10516 {}}} CYCLES {}}
+set a(0-10516) {NAME ACC1-3:exs#49 TYPE SIGNEXTEND PAR 0-9373 XREFS 58727 LOC {1 0.14655495 1 0.6684513 1 0.6684513 1 0.74793955} PREDS {{259 0 0-10515 {}}} SUCCS {{259 0 0-10517 {}}} CYCLES {}}
+set a(0-10517) {NAME ACC1:conc#1107 TYPE CONCATENATE PAR 0-9373 XREFS 58728 LOC {1 0.14655495 1 0.6684513 1 0.6684513 1 0.74793955} PREDS {{258 0 0-10514 {}} {258 0 0-10513 {}} {259 0 0-10516 {}}} SUCCS {{259 0 0-10518 {}}} CYCLES {}}
+set a(0-10518) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#573 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 58729 LOC {1 0.374412025 1 0.6684513 1 0.6684513 1 0.7014880701789504 1 0.7809763201789505} PREDS {{258 0 0-10512 {}} {259 0 0-10517 {}}} SUCCS {{258 0 0-10528 {}}} CYCLES {}}
+set a(0-10519) {NAME ACC1:slc(acc.psp#2)#11 TYPE READSLICE PAR 0-9373 XREFS 58730 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.74793955} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10523 {}}} CYCLES {}}
+set a(0-10520) {NAME ACC1:slc(acc.psp#2)#12 TYPE READSLICE PAR 0-9373 XREFS 58731 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.74793955} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-10523 {}}} CYCLES {}}
+set a(0-10521) {NAME ACC1:slc(acc#5.psp#2)#35 TYPE READSLICE PAR 0-9373 XREFS 58732 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.74793955} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-10522 {}}} CYCLES {}}
+set a(0-10522) {NAME ACC1-2:exs#18 TYPE SIGNEXTEND PAR 0-9373 XREFS 58733 LOC {1 0.14655495 1 0.6684513 1 0.6684513 1 0.74793955} PREDS {{259 0 0-10521 {}}} SUCCS {{259 0 0-10523 {}}} CYCLES {}}
+set a(0-10523) {NAME ACC1:conc#1114 TYPE CONCATENATE PAR 0-9373 XREFS 58734 LOC {1 0.14655495 1 0.6684513 1 0.6684513 1 0.74793955} PREDS {{258 0 0-10520 {}} {258 0 0-10519 {}} {259 0 0-10522 {}}} SUCCS {{258 0 0-10527 {}}} CYCLES {}}
+set a(0-10524) {NAME ACC1:slc(ACC1:acc#220.psp) TYPE READSLICE PAR 0-9373 XREFS 58735 LOC {1 0.32918685 1 0.37564472499999996 1 0.37564472499999996 1 0.717311625} PREDS {{258 0 0-9890 {}}} SUCCS {{258 0 0-10526 {}}} CYCLES {}}
+set a(0-10525) {NAME ACC1:slc(ACC1:acc#222.psp) TYPE READSLICE PAR 0-9373 XREFS 58736 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.717311625} PREDS {{258 0 0-10041 {}}} SUCCS {{259 0 0-10526 {}}} CYCLES {}}
+set a(0-10526) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,1,2,1,3) AREA_SCORE 3.00 QUANTITY 1 NAME ACC1:acc#519 TYPE ACCU DELAY {0.49 ns} LIBRARY_DELAY {0.49 ns} PAR 0-9373 XREFS 58737 LOC {1 0.32918685 1 0.637823375 1 0.637823375 1 0.6684512600894752 1 0.7479395100894752} PREDS {{258 0 0-10524 {}} {259 0 0-10525 {}}} SUCCS {{259 0 0-10527 {}}} CYCLES {}}
+set a(0-10527) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME ACC1:acc#569 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 58738 LOC {1 0.359814775 1 0.6684513 1 0.6684513 1 0.7014880701789504 1 0.7809763201789505} PREDS {{258 0 0-10523 {}} {259 0 0-10526 {}}} SUCCS {{259 0 0-10528 {}}} CYCLES {}}
+set a(0-10528) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,1,6,1,7) AREA_SCORE 7.00 QUANTITY 1 NAME ACC1:acc#619 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 58739 LOC {1 0.40744885 1 0.701488125 1 0.701488125 1 0.7548449734103024 1 0.8343332234103024} PREDS {{258 0 0-10518 {}} {259 0 0-10527 {}}} SUCCS {{259 0 0-10529 {}}} CYCLES {}}
+set a(0-10529) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 6 NAME ACC1:acc#635 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-9373 XREFS 58740 LOC {1 0.560282325 1 0.754845025 1 0.754845025 1 0.8027240879329679 1 0.8822123379329679} PREDS {{258 0 0-10504 {}} {259 0 0-10528 {}}} SUCCS {{258 0 0-10537 {}}} CYCLES {}}
+set a(0-10530) {NAME slc(acc#20.psp#1)#91 TYPE READSLICE PAR 0-9373 XREFS 58741 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.8822124} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10536 {}}} CYCLES {}}
+set a(0-10531) {NAME slc(acc#20.psp#1)#92 TYPE READSLICE PAR 0-9373 XREFS 58742 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.8822124} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10536 {}}} CYCLES {}}
+set a(0-10532) {NAME slc(acc#20.psp#1)#80 TYPE READSLICE PAR 0-9373 XREFS 58743 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.8822124} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10536 {}}} CYCLES {}}
+set a(0-10533) {NAME ACC1:slc(ACC1:acc#228.psp)#54 TYPE READSLICE PAR 0-9373 XREFS 58744 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.8822124} PREDS {{258 0 0-9695 {}}} SUCCS {{258 0 0-10536 {}}} CYCLES {}}
+set a(0-10534) {NAME ACC1-3:slc(acc#10.psp)#63 TYPE READSLICE PAR 0-9373 XREFS 58745 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.8822124} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10535 {}}} CYCLES {}}
+set a(0-10535) {NAME ACC1-3:exs#36 TYPE SIGNEXTEND PAR 0-9373 XREFS 58746 LOC {1 0.14655495 1 0.80272415 1 0.80272415 1 0.8822124} PREDS {{259 0 0-10534 {}}} SUCCS {{259 0 0-10536 {}}} CYCLES {}}
+set a(0-10536) {NAME ACC1:conc#1115 TYPE CONCATENATE PAR 0-9373 XREFS 58747 LOC {1 0.14655495 1 0.80272415 1 0.80272415 1 0.8822124} PREDS {{258 0 0-10533 {}} {258 0 0-10532 {}} {258 0 0-10531 {}} {258 0 0-10530 {}} {259 0 0-10535 {}}} SUCCS {{259 0 0-10537 {}}} CYCLES {}}
+set a(0-10537) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,1,11) AREA_SCORE 10.00 QUANTITY 5 NAME ACC1:acc#646 TYPE ACCU DELAY {0.91 ns} LIBRARY_DELAY {0.91 ns} PAR 0-9373 XREFS 58748 LOC {1 0.60816145 1 0.80272415 1 0.80272415 1 0.8594826628916543 1 0.9389709128916544} PREDS {{258 0 0-10529 {}} {259 0 0-10536 {}}} SUCCS {{258 0 0-10554 {}}} CYCLES {}}
+set a(0-10538) {NAME ACC1:slc(ACC1:acc#227.psp)#53 TYPE READSLICE PAR 0-9373 XREFS 58749 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.57932165} PREDS {{258 0 0-9918 {}}} SUCCS {{258 0 0-10540 {}}} CYCLES {}}
+set a(0-10539) {NAME ACC1:slc(acc.psp#1)#52 TYPE READSLICE PAR 0-9373 XREFS 58750 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.57932165} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-10540 {}}} CYCLES {}}
+set a(0-10540) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#308 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-9373 XREFS 58751 LOC {1 0.14655495 1 0.4998334 1 0.4998334 1 0.53144423625 1 0.6109324862500001} PREDS {{258 0 0-10538 {}} {259 0 0-10539 {}}} SUCCS {{258 0 0-10542 {}}} CYCLES {}}
+set a(0-10541) {NAME ACC1:slc(ACC1:acc#224.psp)#43 TYPE READSLICE PAR 0-9373 XREFS 58752 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.610932525} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10542 {}}} CYCLES {}}
+set a(0-10542) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#307 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58753 LOC {1 0.178165825 1 0.531444275 1 0.531444275 1 0.5519170350894753 1 0.6314052850894752} PREDS {{258 0 0-10540 {}} {259 0 0-10541 {}}} SUCCS {{258 0 0-10544 {}}} CYCLES {}}
+set a(0-10543) {NAME ACC1:slc(ACC1:acc#228.psp)#43 TYPE READSLICE PAR 0-9373 XREFS 58754 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.631405325} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-10544 {}}} CYCLES {}}
+set a(0-10544) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#306 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58755 LOC {1 0.19863862499999999 1 0.551917075 1 0.551917075 1 0.5723898350894753 1 0.6518780850894753} PREDS {{258 0 0-10542 {}} {259 0 0-10543 {}}} SUCCS {{258 0 0-10546 {}}} CYCLES {}}
+set a(0-10545) {NAME ACC1:slc(ACC1:acc#226.psp)#35 TYPE READSLICE PAR 0-9373 XREFS 58756 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.651878125} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-10546 {}}} CYCLES {}}
+set a(0-10546) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#305 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58757 LOC {1 0.219111425 1 0.5723898749999999 1 0.5723898749999999 1 0.5996357520708271 1 0.6791240020708271} PREDS {{258 0 0-10544 {}} {259 0 0-10545 {}}} SUCCS {{258 0 0-10548 {}}} CYCLES {}}
+set a(0-10547) {NAME ACC1:slc(ACC1:acc#224.psp#1)#15 TYPE READSLICE PAR 0-9373 XREFS 58758 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.67912405} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-10548 {}}} CYCLES {}}
+set a(0-10548) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#304 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58759 LOC {1 0.24635735 1 0.5996357999999999 1 0.5996357999999999 1 0.6268816770708271 1 0.7063699270708271} PREDS {{258 0 0-10546 {}} {259 0 0-10547 {}}} SUCCS {{258 0 0-10550 {}}} CYCLES {}}
+set a(0-10549) {NAME ACC1:slc(ACC1-1:acc#25.psp)#13 TYPE READSLICE PAR 0-9373 XREFS 58760 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.706369975} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10550 {}}} CYCLES {}}
+set a(0-10550) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#303 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58761 LOC {1 0.273603275 1 0.626881725 1 0.626881725 1 0.6541276020708271 1 0.7336158520708271} PREDS {{258 0 0-10548 {}} {259 0 0-10549 {}}} SUCCS {{258 0 0-10552 {}}} CYCLES {}}
+set a(0-10551) {NAME ACC1:slc(acc.psp#2)#1 TYPE READSLICE PAR 0-9373 XREFS 58762 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7336159} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10552 {}}} CYCLES {}}
+set a(0-10552) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#302 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58763 LOC {1 0.3008492 1 0.65412765 1 0.65412765 1 0.6813735270708271 1 0.7608617770708271} PREDS {{258 0 0-10550 {}} {259 0 0-10551 {}}} SUCCS {{259 0 0-10553 {}}} CYCLES {}}
+set a(0-10553) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(4,0,7,0,10) AREA_SCORE 330.25 QUANTITY 2 NAME ACC1:mul#54 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-9373 XREFS 58764 LOC {1 0.328095125 1 0.681373575 1 0.681373575 1 0.8594826825545158 1 0.9389709325545158} PREDS {{259 0 0-10552 {}}} SUCCS {{259 0 0-10554 {}}} CYCLES {}}
+set a(0-10554) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,12) AREA_SCORE 11.00 QUANTITY 4 NAME ACC1:acc#651 TYPE ACCU DELAY {0.98 ns} LIBRARY_DELAY {0.98 ns} PAR 0-9373 XREFS 58765 LOC {1 0.6649200249999999 1 0.859482725 1 0.859482725 1 0.9205117033364113 1 0.9999999533364112} PREDS {{258 0 0-10537 {}} {259 0 0-10553 {}}} SUCCS {{258 0 0-10571 {}}} CYCLES {}}
+set a(0-10555) {NAME ACC1:slc(ACC1:acc#227.psp)#54 TYPE READSLICE PAR 0-9373 XREFS 58766 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6319135499999999} PREDS {{258 0 0-9918 {}}} SUCCS {{258 0 0-10557 {}}} CYCLES {}}
+set a(0-10556) {NAME ACC1:slc(acc.psp#1)#53 TYPE READSLICE PAR 0-9373 XREFS 58767 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6319135499999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-10557 {}}} CYCLES {}}
+set a(0-10557) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#315 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-9373 XREFS 58768 LOC {1 0.14655495 1 0.5524253 1 0.5524253 1 0.58403613625 1 0.66352438625} PREDS {{258 0 0-10555 {}} {259 0 0-10556 {}}} SUCCS {{258 0 0-10559 {}}} CYCLES {}}
+set a(0-10558) {NAME ACC1:slc(ACC1:acc#224.psp)#44 TYPE READSLICE PAR 0-9373 XREFS 58769 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.663524425} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10559 {}}} CYCLES {}}
+set a(0-10559) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#314 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58770 LOC {1 0.178165825 1 0.5840361749999999 1 0.5840361749999999 1 0.6045089350894752 1 0.6839971850894753} PREDS {{258 0 0-10557 {}} {259 0 0-10558 {}}} SUCCS {{258 0 0-10561 {}}} CYCLES {}}
+set a(0-10560) {NAME ACC1:slc(ACC1:acc#228.psp)#44 TYPE READSLICE PAR 0-9373 XREFS 58771 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6839972249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-10561 {}}} CYCLES {}}
+set a(0-10561) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#313 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58772 LOC {1 0.19863862499999999 1 0.604508975 1 0.604508975 1 0.6249817350894753 1 0.7044699850894752} PREDS {{258 0 0-10559 {}} {259 0 0-10560 {}}} SUCCS {{258 0 0-10563 {}}} CYCLES {}}
+set a(0-10562) {NAME ACC1:slc(ACC1:acc#226.psp)#36 TYPE READSLICE PAR 0-9373 XREFS 58773 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.704470025} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-10563 {}}} CYCLES {}}
+set a(0-10563) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#312 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58774 LOC {1 0.219111425 1 0.624981775 1 0.624981775 1 0.6522276520708271 1 0.7317159020708272} PREDS {{258 0 0-10561 {}} {259 0 0-10562 {}}} SUCCS {{258 0 0-10565 {}}} CYCLES {}}
+set a(0-10564) {NAME ACC1:slc(ACC1:acc#224.psp#1)#16 TYPE READSLICE PAR 0-9373 XREFS 58775 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.73171595} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-10565 {}}} CYCLES {}}
+set a(0-10565) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#311 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58776 LOC {1 0.24635735 1 0.6522277 1 0.6522277 1 0.6794735770708271 1 0.7589618270708272} PREDS {{258 0 0-10563 {}} {259 0 0-10564 {}}} SUCCS {{258 0 0-10567 {}}} CYCLES {}}
+set a(0-10566) {NAME ACC1:slc(ACC1-1:acc#25.psp)#14 TYPE READSLICE PAR 0-9373 XREFS 58777 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.758961875} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10567 {}}} CYCLES {}}
+set a(0-10567) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#310 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58778 LOC {1 0.273603275 1 0.679473625 1 0.679473625 1 0.7067195020708271 1 0.7862077520708272} PREDS {{258 0 0-10565 {}} {259 0 0-10566 {}}} SUCCS {{258 0 0-10569 {}}} CYCLES {}}
+set a(0-10568) {NAME ACC1:slc(acc.psp#2)#2 TYPE READSLICE PAR 0-9373 XREFS 58779 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7862078} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10569 {}}} CYCLES {}}
+set a(0-10569) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#309 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 58780 LOC {1 0.3008492 1 0.70671955 1 0.70671955 1 0.7339654270708271 1 0.8134536770708272} PREDS {{258 0 0-10567 {}} {259 0 0-10568 {}}} SUCCS {{259 0 0-10570 {}}} CYCLES {}}
+set a(0-10570) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(4,0,9,0,12) AREA_SCORE 330.25 QUANTITY 1 NAME ACC1:mul#55 TYPE MUL DELAY {2.98 ns} LIBRARY_DELAY {2.98 ns} PAR 0-9373 XREFS 58781 LOC {1 0.328095125 1 0.733965475 1 0.733965475 1 0.9205116924845187 1 0.9999999424845187} PREDS {{259 0 0-10569 {}}} SUCCS {{259 0 0-10571 {}}} CYCLES {}}
+set a(0-10571) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,12,1,13) AREA_SCORE 13.00 QUANTITY 2 NAME ACC1:acc#658 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-9373 XREFS 58782 LOC {1 0.72594905 1 0.92051175 1 0.92051175 1 0.9999999534997777 2 0.13630012849977768} PREDS {{258 0 0-10554 {}} {259 0 0-10570 {}}} SUCCS {{259 0 0-10572 {}}} CYCLES {}}
+set a(0-10572) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,1,13,1,14) AREA_SCORE 14.00 QUANTITY 2 NAME ACC1:acc#662 TYPE ACCU DELAY {1.34 ns} LIBRARY_DELAY {1.34 ns} PAR 0-9373 XREFS 58783 LOC {2 0.0 2 0.136300175 2 0.136300175 2 0.21984771205035814 2 0.21984771205035814} PREDS {{258 0 0-10447 {}} {259 0 0-10571 {}}} SUCCS {{258 0 0-10598 {}}} CYCLES {}}
+set a(0-10573) {NAME slc(ACC1:acc#226.psp)#26 TYPE READSLICE PAR 0-9373 XREFS 58784 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.056811925} PREDS {{258 0 0-9767 {}}} SUCCS {{258 0 0-10577 {}}} CYCLES {}}
+set a(0-10574) {NAME slc(ACC1:acc#226.psp)#27 TYPE READSLICE PAR 0-9373 XREFS 58785 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.056811925} PREDS {{258 0 0-9767 {}}} SUCCS {{258 0 0-10577 {}}} CYCLES {}}
+set a(0-10575) {NAME slc(ACC1:acc#226.psp) TYPE READSLICE PAR 0-9373 XREFS 58786 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.056811925} PREDS {{258 0 0-9767 {}}} SUCCS {{258 0 0-10577 {}}} CYCLES {}}
+set a(0-10576) {NAME ACC1:slc(acc.psp#1)#57 TYPE READSLICE PAR 0-9373 XREFS 58787 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.056811925} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-10577 {}}} CYCLES {}}
+set a(0-10577) {NAME ACC1:conc#1074 TYPE CONCATENATE PAR 0-9373 XREFS 58788 LOC {1 0.14655495 1 0.836964175 1 0.836964175 2 0.056811925} PREDS {{258 0 0-10575 {}} {258 0 0-10574 {}} {258 0 0-10573 {}} {259 0 0-10576 {}}} SUCCS {{258 0 0-10590 {}}} CYCLES {}}
+set a(0-10578) {NAME ACC1:slc(ACC1:acc#224.psp)#52 TYPE READSLICE PAR 0-9373 XREFS 58789 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.749334375} PREDS {{258 0 0-9993 {}}} SUCCS {{258 0 0-10580 {}}} CYCLES {}}
+set a(0-10579) {NAME ACC1:slc(ACC1:acc#228.psp)#52 TYPE READSLICE PAR 0-9373 XREFS 58790 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.749334375} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-10580 {}}} CYCLES {}}
+set a(0-10580) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#329 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-9373 XREFS 58791 LOC {1 0.14655495 1 0.58629855 1 0.58629855 1 0.61790938625 1 0.7809452112499999} PREDS {{258 0 0-10578 {}} {259 0 0-10579 {}}} SUCCS {{258 0 0-10582 {}}} CYCLES {}}
+set a(0-10581) {NAME ACC1:slc(ACC1:acc#226.psp)#43 TYPE READSLICE PAR 0-9373 XREFS 58792 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7809452499999999} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-10582 {}}} CYCLES {}}
+set a(0-10582) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#328 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58793 LOC {1 0.178165825 1 0.617909425 1 0.617909425 1 0.6383821850894753 1 0.8014180100894752} PREDS {{258 0 0-10580 {}} {259 0 0-10581 {}}} SUCCS {{258 0 0-10584 {}}} CYCLES {}}
+set a(0-10583) {NAME ACC1:slc(ACC1:acc#224.psp#1)#24 TYPE READSLICE PAR 0-9373 XREFS 58794 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.80141805} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-10584 {}}} CYCLES {}}
+set a(0-10584) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#327 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58795 LOC {1 0.19863862499999999 1 0.638382225 1 0.638382225 1 0.6588549850894753 1 0.8218908100894753} PREDS {{258 0 0-10582 {}} {259 0 0-10583 {}}} SUCCS {{259 0 0-10585 {}}} CYCLES {}}
+set a(0-10585) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(4,0,7,0,10) AREA_SCORE 330.25 QUANTITY 2 NAME ACC1:mul#59 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-9373 XREFS 58796 LOC {1 0.219111425 1 0.6588550249999999 1 0.6588550249999999 1 0.8369641325545157 1 0.9999999575545158} PREDS {{259 0 0-10584 {}}} SUCCS {{258 0 0-10589 {}}} CYCLES {}}
+set a(0-10586) {NAME ACC1:slc(acc.psp#1)#61 TYPE READSLICE PAR 0-9373 XREFS 58797 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.056811925} PREDS {{258 0 0-9839 {}}} SUCCS {{258 0 0-10589 {}}} CYCLES {}}
+set a(0-10587) {NAME ACC1-3:slc(acc#10.psp)#71 TYPE READSLICE PAR 0-9373 XREFS 58798 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.056811925} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10588 {}}} CYCLES {}}
+set a(0-10588) {NAME ACC1-3:exs#1034 TYPE SIGNEXTEND PAR 0-9373 XREFS 58799 LOC {1 0.14655495 1 0.836964175 1 0.836964175 2 0.056811925} PREDS {{259 0 0-10587 {}}} SUCCS {{259 0 0-10589 {}}} CYCLES {}}
+set a(0-10589) {NAME ACC1:conc#1106 TYPE CONCATENATE PAR 0-9373 XREFS 58800 LOC {1 0.39722057499999996 1 0.836964175 1 0.836964175 2 0.056811925} PREDS {{258 0 0-10586 {}} {258 0 0-10585 {}} {259 0 0-10588 {}}} SUCCS {{259 0 0-10590 {}}} CYCLES {}}
+set a(0-10590) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,12,1,13) AREA_SCORE 13.00 QUANTITY 2 NAME ACC1:acc#657 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-9373 XREFS 58801 LOC {1 0.39722057499999996 1 0.836964175 1 0.836964175 1 0.9164523784997777 2 0.13630012849977768} PREDS {{258 0 0-10577 {}} {259 0 0-10589 {}}} SUCCS {{258 0 0-10597 {}}} CYCLES {}}
+set a(0-10591) {NAME ACC1:slc(ACC1:acc#227.psp)#55 TYPE READSLICE PAR 0-9373 XREFS 58802 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.7523285249999999} PREDS {{258 0 0-9918 {}}} SUCCS {{258 0 0-10593 {}}} CYCLES {}}
+set a(0-10592) {NAME ACC1:slc(acc.psp#1)#54 TYPE READSLICE PAR 0-9373 XREFS 58803 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7523285249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-10593 {}}} CYCLES {}}
+set a(0-10593) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#317 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-9373 XREFS 58804 LOC {1 0.14655495 1 0.6687809499999999 1 0.6687809499999999 1 0.70039178625 1 0.7839393612499999} PREDS {{258 0 0-10591 {}} {259 0 0-10592 {}}} SUCCS {{258 0 0-10595 {}}} CYCLES {}}
+set a(0-10594) {NAME ACC1:slc(acc.psp#2)#3 TYPE READSLICE PAR 0-9373 XREFS 58805 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7839394} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10595 {}}} CYCLES {}}
+set a(0-10595) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#316 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58806 LOC {1 0.178165825 1 0.700391825 1 0.700391825 1 0.7208645850894753 1 0.8044121600894752} PREDS {{258 0 0-10593 {}} {259 0 0-10594 {}}} SUCCS {{259 0 0-10596 {}}} CYCLES {}}
+set a(0-10596) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,11,1,13) AREA_SCORE 330.00 QUANTITY 2 NAME ACC1:mul#56 TYPE MUL DELAY {3.13 ns} LIBRARY_DELAY {3.13 ns} PAR 0-9373 XREFS 58807 LOC {1 0.19863862499999999 1 0.7208646249999999 1 0.7208646249999999 1 0.9164523687499999 1 0.9999999437499999} PREDS {{259 0 0-10595 {}}} SUCCS {{259 0 0-10597 {}}} CYCLES {}}
+set a(0-10597) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,1,13,1,14) AREA_SCORE 14.00 QUANTITY 2 NAME ACC1:acc#661 TYPE ACCU DELAY {1.34 ns} LIBRARY_DELAY {1.34 ns} PAR 0-9373 XREFS 58808 LOC {1 0.476708825 1 0.9164524249999999 1 0.9164524249999999 1 0.999999962050358 2 0.21984771205035814} PREDS {{258 0 0-10590 {}} {259 0 0-10596 {}}} SUCCS {{259 0 0-10598 {}}} CYCLES {}}
+set a(0-10598) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(14,1,14,1,15) AREA_SCORE 15.00 QUANTITY 2 NAME ACC1:acc#664 TYPE ACCU DELAY {1.40 ns} LIBRARY_DELAY {1.40 ns} PAR 0-9373 XREFS 58809 LOC {2 0.083547575 2 0.21984774999999998 2 0.21984774999999998 2 0.3074051292724431 2 0.3074051292724431} PREDS {{258 0 0-10572 {}} {259 0 0-10597 {}}} SUCCS {{258 0 0-11638 {}}} CYCLES {}}
+set a(0-10599) {NAME ACC1:slc(ACC1:acc#224.psp)#45 TYPE READSLICE PAR 0-9373 XREFS 58810 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.968389125} PREDS {{258 0 0-9993 {}}} SUCCS {{258 0 0-10601 {}}} CYCLES {}}
+set a(0-10600) {NAME ACC1:slc(ACC1:acc#228.psp)#45 TYPE READSLICE PAR 0-9373 XREFS 58811 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.968389125} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-10601 {}}} CYCLES {}}
+set a(0-10601) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#319 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-9373 XREFS 58812 LOC {1 0.14655495 1 0.7496646499999999 1 0.7496646499999999 1 0.78127548625 1 0.9999999612499999} PREDS {{258 0 0-10599 {}} {259 0 0-10600 {}}} SUCCS {{258 0 0-10603 {}}} CYCLES {}}
+set a(0-10602) {NAME ACC1:slc(ACC1:acc#224.psp#1)#17 TYPE READSLICE PAR 0-9373 XREFS 58813 LOC {1 0.14655495 1 0.244598025 1 0.244598025 2 0.001123275} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-10603 {}}} CYCLES {}}
+set a(0-10603) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#318 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 58814 LOC {1 0.178165825 1 0.781275525 1 0.781275525 1 0.8017482850894753 2 0.021596035089475246} PREDS {{258 0 0-10601 {}} {259 0 0-10602 {}}} SUCCS {{259 0 0-10604 {}}} CYCLES {}}
+set a(0-10604) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,14) AREA_SCORE 330.00 QUANTITY 1 NAME ACC1:mul#57 TYPE MUL DELAY {3.17 ns} LIBRARY_DELAY {3.17 ns} PAR 0-9373 XREFS 58815 LOC {1 0.19863862499999999 1 0.8017483249999999 1 0.8017483249999999 1 0.9999999499999999 2 0.21984769999999995} PREDS {{259 0 0-10603 {}}} SUCCS {{258 0 0-11637 {}}} CYCLES {}}
+set a(0-10605) {NAME slc(acc#20.psp#1)#93 TYPE READSLICE PAR 0-9373 XREFS 58816 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.060871249999999995} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10612 {}}} CYCLES {}}
+set a(0-10606) {NAME slc(acc#20.psp#1)#94 TYPE READSLICE PAR 0-9373 XREFS 58817 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.060871249999999995} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10612 {}}} CYCLES {}}
+set a(0-10607) {NAME slc(acc#20.psp#1)#95 TYPE READSLICE PAR 0-9373 XREFS 58818 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.060871249999999995} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10612 {}}} CYCLES {}}
+set a(0-10608) {NAME slc(acc#20.psp#1)#81 TYPE READSLICE PAR 0-9373 XREFS 58819 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.060871249999999995} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10612 {}}} CYCLES {}}
+set a(0-10609) {NAME ACC1:slc(ACC1:acc#228.psp)#55 TYPE READSLICE PAR 0-9373 XREFS 58820 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.060871249999999995} PREDS {{258 0 0-9695 {}}} SUCCS {{258 0 0-10612 {}}} CYCLES {}}
+set a(0-10610) {NAME ACC1-3:slc(acc#10.psp)#62 TYPE READSLICE PAR 0-9373 XREFS 58821 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.060871249999999995} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10611 {}}} CYCLES {}}
+set a(0-10611) {NAME ACC1-3:exs#37 TYPE SIGNEXTEND PAR 0-9373 XREFS 58822 LOC {1 0.14655495 2 0.060871249999999995 2 0.060871249999999995 2 0.060871249999999995} PREDS {{259 0 0-10610 {}}} SUCCS {{259 0 0-10612 {}}} CYCLES {}}
+set a(0-10612) {NAME ACC1:conc#1117 TYPE CONCATENATE PAR 0-9373 XREFS 58823 LOC {1 0.14655495 2 0.060871249999999995 2 0.060871249999999995 2 0.060871249999999995} PREDS {{258 0 0-10609 {}} {258 0 0-10608 {}} {258 0 0-10607 {}} {258 0 0-10606 {}} {258 0 0-10605 {}} {259 0 0-10611 {}}} SUCCS {{258 0 0-11089 {}}} CYCLES {}}
+set a(0-10613) {NAME ACC1-1:slc(acc.idiv#5)#5 TYPE READSLICE PAR 0-9373 XREFS 58824 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10614 {}}} CYCLES {}}
+set a(0-10614) {NAME ACC1-1:exs#92 TYPE SIGNEXTEND PAR 0-9373 XREFS 58825 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10613 {}}} SUCCS {{259 0 0-10615 {}}} CYCLES {}}
+set a(0-10615) {NAME ACC1:conc#1374 TYPE CONCATENATE PAR 0-9373 XREFS 58826 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10614 {}}} SUCCS {{258 0 0-10620 {}}} CYCLES {}}
+set a(0-10616) {NAME ACC1-1:slc(acc.idiv#5)#7 TYPE READSLICE PAR 0-9373 XREFS 58827 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10617 {}}} CYCLES {}}
+set a(0-10617) {NAME ACC1-1:exs#93 TYPE SIGNEXTEND PAR 0-9373 XREFS 58828 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10616 {}}} SUCCS {{258 0 0-10619 {}}} CYCLES {}}
+set a(0-10618) {NAME ACC1:slc(ACC1:acc#214.psp#2)#5 TYPE READSLICE PAR 0-9373 XREFS 58829 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.43013657499999997} PREDS {{258 0 0-9508 {}}} SUCCS {{259 0 0-10619 {}}} CYCLES {}}
+set a(0-10619) {NAME ACC1:conc#1375 TYPE CONCATENATE PAR 0-9373 XREFS 58830 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10617 {}} {259 0 0-10618 {}}} SUCCS {{259 0 0-10620 {}}} CYCLES {}}
+set a(0-10620) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#458 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58831 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10615 {}} {259 0 0-10619 {}}} SUCCS {{259 0 0-10621 {}}} CYCLES {}}
+set a(0-10621) {NAME ACC1:slc#126 TYPE READSLICE PAR 0-9373 XREFS 58832 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10620 {}}} SUCCS {{258 0 0-10631 {}}} CYCLES {}}
+set a(0-10622) {NAME ACC1-1:slc(acc.idiv#5)#19 TYPE READSLICE PAR 0-9373 XREFS 58833 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10623 {}}} CYCLES {}}
+set a(0-10623) {NAME ACC1-1:exs#99 TYPE SIGNEXTEND PAR 0-9373 XREFS 58834 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10622 {}}} SUCCS {{259 0 0-10624 {}}} CYCLES {}}
+set a(0-10624) {NAME ACC1:conc#1372 TYPE CONCATENATE PAR 0-9373 XREFS 58835 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10623 {}}} SUCCS {{258 0 0-10629 {}}} CYCLES {}}
+set a(0-10625) {NAME ACC1-1:slc(acc.idiv#5)#21 TYPE READSLICE PAR 0-9373 XREFS 58836 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10626 {}}} CYCLES {}}
+set a(0-10626) {NAME ACC1-1:exs#100 TYPE SIGNEXTEND PAR 0-9373 XREFS 58837 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10625 {}}} SUCCS {{258 0 0-10628 {}}} CYCLES {}}
+set a(0-10627) {NAME ACC1:slc(ACC1:acc#214.psp#2)#4 TYPE READSLICE PAR 0-9373 XREFS 58838 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.43013657499999997} PREDS {{258 0 0-9508 {}}} SUCCS {{259 0 0-10628 {}}} CYCLES {}}
+set a(0-10628) {NAME ACC1:conc#1373 TYPE CONCATENATE PAR 0-9373 XREFS 58839 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10626 {}} {259 0 0-10627 {}}} SUCCS {{259 0 0-10629 {}}} CYCLES {}}
+set a(0-10629) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#457 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58840 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10624 {}} {259 0 0-10628 {}}} SUCCS {{259 0 0-10630 {}}} CYCLES {}}
+set a(0-10630) {NAME ACC1:slc#125 TYPE READSLICE PAR 0-9373 XREFS 58841 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10629 {}}} SUCCS {{259 0 0-10631 {}}} CYCLES {}}
+set a(0-10631) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#540 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58842 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10621 {}} {259 0 0-10630 {}}} SUCCS {{258 0 0-10651 {}}} CYCLES {}}
+set a(0-10632) {NAME ACC1-1:slc(acc.idiv#5)#13 TYPE READSLICE PAR 0-9373 XREFS 58843 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10633 {}}} CYCLES {}}
+set a(0-10633) {NAME ACC1-1:exs#96 TYPE SIGNEXTEND PAR 0-9373 XREFS 58844 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10632 {}}} SUCCS {{259 0 0-10634 {}}} CYCLES {}}
+set a(0-10634) {NAME ACC1:conc#1370 TYPE CONCATENATE PAR 0-9373 XREFS 58845 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10633 {}}} SUCCS {{258 0 0-10639 {}}} CYCLES {}}
+set a(0-10635) {NAME ACC1-1:slc(acc.idiv#5)#15 TYPE READSLICE PAR 0-9373 XREFS 58846 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10636 {}}} CYCLES {}}
+set a(0-10636) {NAME ACC1-1:exs#97 TYPE SIGNEXTEND PAR 0-9373 XREFS 58847 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10635 {}}} SUCCS {{258 0 0-10638 {}}} CYCLES {}}
+set a(0-10637) {NAME ACC1:slc(ACC1:acc#214.psp#2) TYPE READSLICE PAR 0-9373 XREFS 58848 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.43013657499999997} PREDS {{258 0 0-9508 {}}} SUCCS {{259 0 0-10638 {}}} CYCLES {}}
+set a(0-10638) {NAME ACC1:conc#1371 TYPE CONCATENATE PAR 0-9373 XREFS 58849 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10636 {}} {259 0 0-10637 {}}} SUCCS {{259 0 0-10639 {}}} CYCLES {}}
+set a(0-10639) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#456 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58850 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10634 {}} {259 0 0-10638 {}}} SUCCS {{259 0 0-10640 {}}} CYCLES {}}
+set a(0-10640) {NAME ACC1:slc#124 TYPE READSLICE PAR 0-9373 XREFS 58851 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10639 {}}} SUCCS {{258 0 0-10650 {}}} CYCLES {}}
+set a(0-10641) {NAME ACC1-1:slc(acc.idiv#5)#17 TYPE READSLICE PAR 0-9373 XREFS 58852 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10642 {}}} CYCLES {}}
+set a(0-10642) {NAME ACC1-1:exs#98 TYPE SIGNEXTEND PAR 0-9373 XREFS 58853 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10641 {}}} SUCCS {{259 0 0-10643 {}}} CYCLES {}}
+set a(0-10643) {NAME ACC1:conc#1368 TYPE CONCATENATE PAR 0-9373 XREFS 58854 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10642 {}}} SUCCS {{258 0 0-10648 {}}} CYCLES {}}
+set a(0-10644) {NAME ACC1-1:slc(acc.idiv#5)#25 TYPE READSLICE PAR 0-9373 XREFS 58855 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10645 {}}} CYCLES {}}
+set a(0-10645) {NAME ACC1-1:exs#102 TYPE SIGNEXTEND PAR 0-9373 XREFS 58856 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10644 {}}} SUCCS {{258 0 0-10647 {}}} CYCLES {}}
+set a(0-10646) {NAME ACC1:slc(acc.imod#6) TYPE READSLICE PAR 0-9373 XREFS 58857 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-9976 {}}} SUCCS {{259 0 0-10647 {}}} CYCLES {}}
+set a(0-10647) {NAME ACC1:conc#1369 TYPE CONCATENATE PAR 0-9373 XREFS 58858 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10645 {}} {259 0 0-10646 {}}} SUCCS {{259 0 0-10648 {}}} CYCLES {}}
+set a(0-10648) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#455 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58859 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10643 {}} {259 0 0-10647 {}}} SUCCS {{259 0 0-10649 {}}} CYCLES {}}
+set a(0-10649) {NAME ACC1:slc#123 TYPE READSLICE PAR 0-9373 XREFS 58860 LOC {1 0.40398894999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10648 {}}} SUCCS {{259 0 0-10650 {}}} CYCLES {}}
+set a(0-10650) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#539 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58861 LOC {1 0.40398894999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10640 {}} {259 0 0-10649 {}}} SUCCS {{259 0 0-10651 {}}} CYCLES {}}
+set a(0-10651) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#585 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 58862 LOC {1 0.451545125 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-10631 {}} {259 0 0-10650 {}}} SUCCS {{258 0 0-10695 {}}} CYCLES {}}
+set a(0-10652) {NAME ACC1-1:slc(acc#25.psp)#46 TYPE READSLICE PAR 0-9373 XREFS 58863 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10653 {}}} CYCLES {}}
+set a(0-10653) {NAME ACC1-1:exs#353 TYPE SIGNEXTEND PAR 0-9373 XREFS 58864 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10652 {}}} SUCCS {{259 0 0-10654 {}}} CYCLES {}}
+set a(0-10654) {NAME ACC1:conc#1366 TYPE CONCATENATE PAR 0-9373 XREFS 58865 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10653 {}}} SUCCS {{258 0 0-10659 {}}} CYCLES {}}
+set a(0-10655) {NAME ACC1-1:slc(acc.idiv#5)#23 TYPE READSLICE PAR 0-9373 XREFS 58866 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10656 {}}} CYCLES {}}
+set a(0-10656) {NAME ACC1-1:exs#101 TYPE SIGNEXTEND PAR 0-9373 XREFS 58867 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10655 {}}} SUCCS {{258 0 0-10658 {}}} CYCLES {}}
+set a(0-10657) {NAME ACC1:slc(ACC1-3:acc#212.psp)#14 TYPE READSLICE PAR 0-9373 XREFS 58868 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.43013657499999997} PREDS {{258 0 0-9958 {}}} SUCCS {{259 0 0-10658 {}}} CYCLES {}}
+set a(0-10658) {NAME ACC1:conc#1367 TYPE CONCATENATE PAR 0-9373 XREFS 58869 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10656 {}} {259 0 0-10657 {}}} SUCCS {{259 0 0-10659 {}}} CYCLES {}}
+set a(0-10659) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#454 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58870 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10654 {}} {259 0 0-10658 {}}} SUCCS {{259 0 0-10660 {}}} CYCLES {}}
+set a(0-10660) {NAME ACC1:slc#122 TYPE READSLICE PAR 0-9373 XREFS 58871 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10659 {}}} SUCCS {{258 0 0-10670 {}}} CYCLES {}}
+set a(0-10661) {NAME ACC1-1:slc(acc.idiv#5)#33 TYPE READSLICE PAR 0-9373 XREFS 58872 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10662 {}}} CYCLES {}}
+set a(0-10662) {NAME ACC1-1:exs#106 TYPE SIGNEXTEND PAR 0-9373 XREFS 58873 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10661 {}}} SUCCS {{259 0 0-10663 {}}} CYCLES {}}
+set a(0-10663) {NAME ACC1:conc#1364 TYPE CONCATENATE PAR 0-9373 XREFS 58874 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10662 {}}} SUCCS {{258 0 0-10668 {}}} CYCLES {}}
+set a(0-10664) {NAME ACC1-1:slc(acc#25.psp)#56 TYPE READSLICE PAR 0-9373 XREFS 58875 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10665 {}}} CYCLES {}}
+set a(0-10665) {NAME ACC1-1:exs#963 TYPE SIGNEXTEND PAR 0-9373 XREFS 58876 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10664 {}}} SUCCS {{258 0 0-10667 {}}} CYCLES {}}
+set a(0-10666) {NAME ACC1:slc(ACC1-3:acc#212.psp)#13 TYPE READSLICE PAR 0-9373 XREFS 58877 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.43013657499999997} PREDS {{258 0 0-9958 {}}} SUCCS {{259 0 0-10667 {}}} CYCLES {}}
+set a(0-10667) {NAME ACC1:conc#1365 TYPE CONCATENATE PAR 0-9373 XREFS 58878 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10665 {}} {259 0 0-10666 {}}} SUCCS {{259 0 0-10668 {}}} CYCLES {}}
+set a(0-10668) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#453 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58879 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10663 {}} {259 0 0-10667 {}}} SUCCS {{259 0 0-10669 {}}} CYCLES {}}
+set a(0-10669) {NAME ACC1:slc#121 TYPE READSLICE PAR 0-9373 XREFS 58880 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10668 {}}} SUCCS {{259 0 0-10670 {}}} CYCLES {}}
+set a(0-10670) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#538 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58881 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10660 {}} {259 0 0-10669 {}}} SUCCS {{258 0 0-10694 {}}} CYCLES {}}
+set a(0-10671) {NAME ACC1-1:slc(acc.idiv#5)#27 TYPE READSLICE PAR 0-9373 XREFS 58882 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10672 {}}} CYCLES {}}
+set a(0-10672) {NAME ACC1-1:exs#103 TYPE SIGNEXTEND PAR 0-9373 XREFS 58883 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10671 {}}} SUCCS {{259 0 0-10673 {}}} CYCLES {}}
+set a(0-10673) {NAME ACC1:conc#1362 TYPE CONCATENATE PAR 0-9373 XREFS 58884 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10672 {}}} SUCCS {{258 0 0-10678 {}}} CYCLES {}}
+set a(0-10674) {NAME ACC1-1:slc(acc.idiv#5)#29 TYPE READSLICE PAR 0-9373 XREFS 58885 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10675 {}}} CYCLES {}}
+set a(0-10675) {NAME ACC1-1:exs#104 TYPE SIGNEXTEND PAR 0-9373 XREFS 58886 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10674 {}}} SUCCS {{258 0 0-10677 {}}} CYCLES {}}
+set a(0-10676) {NAME ACC1:slc(ACC1-3:acc#212.psp) TYPE READSLICE PAR 0-9373 XREFS 58887 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.43013657499999997} PREDS {{258 0 0-9958 {}}} SUCCS {{259 0 0-10677 {}}} CYCLES {}}
+set a(0-10677) {NAME ACC1:conc#1363 TYPE CONCATENATE PAR 0-9373 XREFS 58888 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10675 {}} {259 0 0-10676 {}}} SUCCS {{259 0 0-10678 {}}} CYCLES {}}
+set a(0-10678) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#452 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58889 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10673 {}} {259 0 0-10677 {}}} SUCCS {{259 0 0-10679 {}}} CYCLES {}}
+set a(0-10679) {NAME ACC1:slc#120 TYPE READSLICE PAR 0-9373 XREFS 58890 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10678 {}}} SUCCS {{258 0 0-10693 {}}} CYCLES {}}
+set a(0-10680) {NAME ACC1-3:slc(acc.idiv#1)#17 TYPE READSLICE PAR 0-9373 XREFS 58891 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10681 {}}} CYCLES {}}
+set a(0-10681) {NAME ACC1-3:exs#26 TYPE SIGNEXTEND PAR 0-9373 XREFS 58892 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10680 {}}} SUCCS {{259 0 0-10682 {}}} CYCLES {}}
+set a(0-10682) {NAME ACC1:conc#1360 TYPE CONCATENATE PAR 0-9373 XREFS 58893 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10681 {}}} SUCCS {{258 0 0-10691 {}}} CYCLES {}}
+set a(0-10683) {NAME ACC1-3:slc(acc.idiv#1)#3 TYPE READSLICE PAR 0-9373 XREFS 58894 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10684 {}}} CYCLES {}}
+set a(0-10684) {NAME ACC1-3:exs#19 TYPE SIGNEXTEND PAR 0-9373 XREFS 58895 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10683 {}}} SUCCS {{258 0 0-10690 {}}} CYCLES {}}
+set a(0-10685) {NAME ACC1:slc(acc#25.psp#2)#26 TYPE READSLICE PAR 0-9373 XREFS 58896 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9767 {}}} SUCCS {{258 0 0-10689 {}}} CYCLES {}}
+set a(0-10686) {NAME ACC1-2:slc(acc.imod#23)#1 TYPE READSLICE PAR 0-9373 XREFS 58897 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-9831 {}}} SUCCS {{259 0 0-10687 {}}} CYCLES {}}
+set a(0-10687) {NAME ACC1-2:not#188 TYPE NOT PAR 0-9373 XREFS 58898 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10686 {}}} SUCCS {{258 0 0-10689 {}}} CYCLES {}}
+set a(0-10688) {NAME ACC1-2:slc(acc.imod#23)#2 TYPE READSLICE PAR 0-9373 XREFS 58899 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-9831 {}}} SUCCS {{259 0 0-10689 {}}} CYCLES {}}
+set a(0-10689) {NAME ACC1-2:and#11 TYPE AND PAR 0-9373 XREFS 58900 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10687 {}} {258 0 0-10685 {}} {259 0 0-10688 {}}} SUCCS {{259 0 0-10690 {}}} CYCLES {}}
+set a(0-10690) {NAME ACC1:conc#1361 TYPE CONCATENATE PAR 0-9373 XREFS 58901 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10684 {}} {259 0 0-10689 {}}} SUCCS {{259 0 0-10691 {}}} CYCLES {}}
+set a(0-10691) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#451 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58902 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10682 {}} {259 0 0-10690 {}}} SUCCS {{259 0 0-10692 {}}} CYCLES {}}
+set a(0-10692) {NAME ACC1:slc#119 TYPE READSLICE PAR 0-9373 XREFS 58903 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10691 {}}} SUCCS {{259 0 0-10693 {}}} CYCLES {}}
+set a(0-10693) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#537 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58904 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10679 {}} {259 0 0-10692 {}}} SUCCS {{259 0 0-10694 {}}} CYCLES {}}
+set a(0-10694) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#584 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 58905 LOC {1 0.469524375 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-10670 {}} {259 0 0-10693 {}}} SUCCS {{259 0 0-10695 {}}} CYCLES {}}
+set a(0-10695) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#607 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-9373 XREFS 58906 LOC {1 0.52287145 1 0.578596 1 0.578596 1 0.637195709496936 1 0.637195709496936} PREDS {{258 0 0-10651 {}} {259 0 0-10694 {}}} SUCCS {{258 0 0-10785 {}}} CYCLES {}}
+set a(0-10696) {NAME ACC1-3:slc(acc.idiv#1)#5 TYPE READSLICE PAR 0-9373 XREFS 58907 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10697 {}}} CYCLES {}}
+set a(0-10697) {NAME ACC1-3:exs#20 TYPE SIGNEXTEND PAR 0-9373 XREFS 58908 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10696 {}}} SUCCS {{259 0 0-10698 {}}} CYCLES {}}
+set a(0-10698) {NAME ACC1:conc#1358 TYPE CONCATENATE PAR 0-9373 XREFS 58909 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10697 {}}} SUCCS {{258 0 0-10706 {}}} CYCLES {}}
+set a(0-10699) {NAME ACC1-3:slc(acc.idiv#1)#7 TYPE READSLICE PAR 0-9373 XREFS 58910 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10700 {}}} CYCLES {}}
+set a(0-10700) {NAME ACC1-3:exs#21 TYPE SIGNEXTEND PAR 0-9373 XREFS 58911 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10699 {}}} SUCCS {{258 0 0-10705 {}}} CYCLES {}}
+set a(0-10701) {NAME ACC1-2:slc(acc.imod#23) TYPE READSLICE PAR 0-9373 XREFS 58912 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-9831 {}}} SUCCS {{258 0 0-10704 {}}} CYCLES {}}
+set a(0-10702) {NAME ACC1:slc(acc#25.psp#2)#25 TYPE READSLICE PAR 0-9373 XREFS 58913 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-10703 {}}} CYCLES {}}
+set a(0-10703) {NAME ACC1-2:not#187 TYPE NOT PAR 0-9373 XREFS 58914 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10702 {}}} SUCCS {{259 0 0-10704 {}}} CYCLES {}}
+set a(0-10704) {NAME ACC1-2:nand#5 TYPE NAND PAR 0-9373 XREFS 58915 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10701 {}} {259 0 0-10703 {}}} SUCCS {{259 0 0-10705 {}}} CYCLES {}}
+set a(0-10705) {NAME ACC1:conc#1359 TYPE CONCATENATE PAR 0-9373 XREFS 58916 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10700 {}} {259 0 0-10704 {}}} SUCCS {{259 0 0-10706 {}}} CYCLES {}}
+set a(0-10706) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#450 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58917 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10698 {}} {259 0 0-10705 {}}} SUCCS {{259 0 0-10707 {}}} CYCLES {}}
+set a(0-10707) {NAME ACC1:slc#118 TYPE READSLICE PAR 0-9373 XREFS 58918 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10706 {}}} SUCCS {{258 0 0-10717 {}}} CYCLES {}}
+set a(0-10708) {NAME ACC1-3:slc(acc#10.psp)#67 TYPE READSLICE PAR 0-9373 XREFS 58919 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10709 {}}} CYCLES {}}
+set a(0-10709) {NAME ACC1-3:exs#52 TYPE SIGNEXTEND PAR 0-9373 XREFS 58920 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10708 {}}} SUCCS {{259 0 0-10710 {}}} CYCLES {}}
+set a(0-10710) {NAME ACC1:conc#1356 TYPE CONCATENATE PAR 0-9373 XREFS 58921 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10709 {}}} SUCCS {{258 0 0-10715 {}}} CYCLES {}}
+set a(0-10711) {NAME ACC1-3:slc(acc#10.psp)#66 TYPE READSLICE PAR 0-9373 XREFS 58922 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10712 {}}} CYCLES {}}
+set a(0-10712) {NAME ACC1-3:exs#53 TYPE SIGNEXTEND PAR 0-9373 XREFS 58923 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10711 {}}} SUCCS {{258 0 0-10714 {}}} CYCLES {}}
+set a(0-10713) {NAME ACC1:slc(acc.imod#43) TYPE READSLICE PAR 0-9373 XREFS 58924 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.43013657499999997} PREDS {{258 0 0-9822 {}}} SUCCS {{259 0 0-10714 {}}} CYCLES {}}
+set a(0-10714) {NAME ACC1:conc#1357 TYPE CONCATENATE PAR 0-9373 XREFS 58925 LOC {1 0.3471661 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10712 {}} {259 0 0-10713 {}}} SUCCS {{259 0 0-10715 {}}} CYCLES {}}
+set a(0-10715) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#449 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58926 LOC {1 0.3471661 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10710 {}} {259 0 0-10714 {}}} SUCCS {{259 0 0-10716 {}}} CYCLES {}}
+set a(0-10716) {NAME ACC1:slc#117 TYPE READSLICE PAR 0-9373 XREFS 58927 LOC {1 0.39472227499999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10715 {}}} SUCCS {{259 0 0-10717 {}}} CYCLES {}}
+set a(0-10717) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#536 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58928 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10707 {}} {259 0 0-10716 {}}} SUCCS {{258 0 0-10737 {}}} CYCLES {}}
+set a(0-10718) {NAME ACC1-3:slc(acc#10.psp)#65 TYPE READSLICE PAR 0-9373 XREFS 58929 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10719 {}}} CYCLES {}}
+set a(0-10719) {NAME ACC1-3:exs#40 TYPE SIGNEXTEND PAR 0-9373 XREFS 58930 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10718 {}}} SUCCS {{259 0 0-10720 {}}} CYCLES {}}
+set a(0-10720) {NAME ACC1:conc#1354 TYPE CONCATENATE PAR 0-9373 XREFS 58931 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10719 {}}} SUCCS {{258 0 0-10725 {}}} CYCLES {}}
+set a(0-10721) {NAME ACC1-3:slc(acc#10.psp)#64 TYPE READSLICE PAR 0-9373 XREFS 58932 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10722 {}}} CYCLES {}}
+set a(0-10722) {NAME ACC1-3:exs#41 TYPE SIGNEXTEND PAR 0-9373 XREFS 58933 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10721 {}}} SUCCS {{258 0 0-10724 {}}} CYCLES {}}
+set a(0-10723) {NAME ACC1:slc(ACC1-2:acc#208.psp)#11 TYPE READSLICE PAR 0-9373 XREFS 58934 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-9804 {}}} SUCCS {{259 0 0-10724 {}}} CYCLES {}}
+set a(0-10724) {NAME ACC1:conc#1355 TYPE CONCATENATE PAR 0-9373 XREFS 58935 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10722 {}} {259 0 0-10723 {}}} SUCCS {{259 0 0-10725 {}}} CYCLES {}}
+set a(0-10725) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#448 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58936 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10720 {}} {259 0 0-10724 {}}} SUCCS {{259 0 0-10726 {}}} CYCLES {}}
+set a(0-10726) {NAME ACC1:slc#116 TYPE READSLICE PAR 0-9373 XREFS 58937 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10725 {}}} SUCCS {{258 0 0-10736 {}}} CYCLES {}}
+set a(0-10727) {NAME ACC1-3:slc(acc.psp)#65 TYPE READSLICE PAR 0-9373 XREFS 58938 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-10728 {}}} CYCLES {}}
+set a(0-10728) {NAME ACC1-3:exs TYPE SIGNEXTEND PAR 0-9373 XREFS 58939 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10727 {}}} SUCCS {{259 0 0-10729 {}}} CYCLES {}}
+set a(0-10729) {NAME ACC1:conc#1352 TYPE CONCATENATE PAR 0-9373 XREFS 58940 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10728 {}}} SUCCS {{258 0 0-10734 {}}} CYCLES {}}
+set a(0-10730) {NAME ACC1-3:slc(acc.idiv)#27 TYPE READSLICE PAR 0-9373 XREFS 58941 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-10731 {}}} CYCLES {}}
+set a(0-10731) {NAME ACC1-3:exs#13 TYPE SIGNEXTEND PAR 0-9373 XREFS 58942 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10730 {}}} SUCCS {{258 0 0-10733 {}}} CYCLES {}}
+set a(0-10732) {NAME ACC1:slc(ACC1-2:acc#208.psp)#10 TYPE READSLICE PAR 0-9373 XREFS 58943 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-9804 {}}} SUCCS {{259 0 0-10733 {}}} CYCLES {}}
+set a(0-10733) {NAME ACC1:conc#1353 TYPE CONCATENATE PAR 0-9373 XREFS 58944 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10731 {}} {259 0 0-10732 {}}} SUCCS {{259 0 0-10734 {}}} CYCLES {}}
+set a(0-10734) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#447 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58945 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10729 {}} {259 0 0-10733 {}}} SUCCS {{259 0 0-10735 {}}} CYCLES {}}
+set a(0-10735) {NAME ACC1:slc#115 TYPE READSLICE PAR 0-9373 XREFS 58946 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10734 {}}} SUCCS {{259 0 0-10736 {}}} CYCLES {}}
+set a(0-10736) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#535 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58947 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10726 {}} {259 0 0-10735 {}}} SUCCS {{259 0 0-10737 {}}} CYCLES {}}
+set a(0-10737) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#583 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 58948 LOC {1 0.469524375 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-10717 {}} {259 0 0-10736 {}}} SUCCS {{258 0 0-10784 {}}} CYCLES {}}
+set a(0-10738) {NAME ACC1-3:slc(acc.idiv)#29 TYPE READSLICE PAR 0-9373 XREFS 58949 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-10739 {}}} CYCLES {}}
+set a(0-10739) {NAME ACC1-3:exs#14 TYPE SIGNEXTEND PAR 0-9373 XREFS 58950 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10738 {}}} SUCCS {{259 0 0-10740 {}}} CYCLES {}}
+set a(0-10740) {NAME ACC1:conc#1350 TYPE CONCATENATE PAR 0-9373 XREFS 58951 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10739 {}}} SUCCS {{258 0 0-10745 {}}} CYCLES {}}
+set a(0-10741) {NAME ACC1-3:slc(acc.idiv#1)#11 TYPE READSLICE PAR 0-9373 XREFS 58952 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10742 {}}} CYCLES {}}
+set a(0-10742) {NAME ACC1-3:exs#23 TYPE SIGNEXTEND PAR 0-9373 XREFS 58953 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10741 {}}} SUCCS {{258 0 0-10744 {}}} CYCLES {}}
+set a(0-10743) {NAME ACC1:slc(ACC1-2:acc#208.psp) TYPE READSLICE PAR 0-9373 XREFS 58954 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-9804 {}}} SUCCS {{259 0 0-10744 {}}} CYCLES {}}
+set a(0-10744) {NAME ACC1:conc#1351 TYPE CONCATENATE PAR 0-9373 XREFS 58955 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10742 {}} {259 0 0-10743 {}}} SUCCS {{259 0 0-10745 {}}} CYCLES {}}
+set a(0-10745) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#446 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58956 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10740 {}} {259 0 0-10744 {}}} SUCCS {{259 0 0-10746 {}}} CYCLES {}}
+set a(0-10746) {NAME ACC1:slc#114 TYPE READSLICE PAR 0-9373 XREFS 58957 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10745 {}}} SUCCS {{258 0 0-10760 {}}} CYCLES {}}
+set a(0-10747) {NAME ACC1-3:slc(acc.idiv#1)#1 TYPE READSLICE PAR 0-9373 XREFS 58958 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10748 {}}} CYCLES {}}
+set a(0-10748) {NAME ACC1-3:exs#18 TYPE SIGNEXTEND PAR 0-9373 XREFS 58959 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10747 {}}} SUCCS {{259 0 0-10749 {}}} CYCLES {}}
+set a(0-10749) {NAME ACC1:conc#1348 TYPE CONCATENATE PAR 0-9373 XREFS 58960 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10748 {}}} SUCCS {{258 0 0-10758 {}}} CYCLES {}}
+set a(0-10750) {NAME ACC1-3:slc(acc.idiv#1)#33 TYPE READSLICE PAR 0-9373 XREFS 58961 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10751 {}}} CYCLES {}}
+set a(0-10751) {NAME ACC1-3:exs#34 TYPE SIGNEXTEND PAR 0-9373 XREFS 58962 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10750 {}}} SUCCS {{258 0 0-10757 {}}} CYCLES {}}
+set a(0-10752) {NAME ACC1:slc(acc#5.psp#2)#30 TYPE READSLICE PAR 0-9373 XREFS 58963 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9695 {}}} SUCCS {{258 0 0-10756 {}}} CYCLES {}}
+set a(0-10753) {NAME ACC1-2:slc(acc.imod#7)#1 TYPE READSLICE PAR 0-9373 XREFS 58964 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-9759 {}}} SUCCS {{259 0 0-10754 {}}} CYCLES {}}
+set a(0-10754) {NAME ACC1-2:not#60 TYPE NOT PAR 0-9373 XREFS 58965 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10753 {}}} SUCCS {{258 0 0-10756 {}}} CYCLES {}}
+set a(0-10755) {NAME ACC1-2:slc(acc.imod#7)#2 TYPE READSLICE PAR 0-9373 XREFS 58966 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-9759 {}}} SUCCS {{259 0 0-10756 {}}} CYCLES {}}
+set a(0-10756) {NAME ACC1-2:and#3 TYPE AND PAR 0-9373 XREFS 58967 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10754 {}} {258 0 0-10752 {}} {259 0 0-10755 {}}} SUCCS {{259 0 0-10757 {}}} CYCLES {}}
+set a(0-10757) {NAME ACC1:conc#1349 TYPE CONCATENATE PAR 0-9373 XREFS 58968 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10751 {}} {259 0 0-10756 {}}} SUCCS {{259 0 0-10758 {}}} CYCLES {}}
+set a(0-10758) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#445 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58969 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10749 {}} {259 0 0-10757 {}}} SUCCS {{259 0 0-10759 {}}} CYCLES {}}
+set a(0-10759) {NAME ACC1:slc#113 TYPE READSLICE PAR 0-9373 XREFS 58970 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10758 {}}} SUCCS {{259 0 0-10760 {}}} CYCLES {}}
+set a(0-10760) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#534 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58971 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10746 {}} {259 0 0-10759 {}}} SUCCS {{258 0 0-10783 {}}} CYCLES {}}
+set a(0-10761) {NAME ACC1-3:slc(acc.idiv#1)#35 TYPE READSLICE PAR 0-9373 XREFS 58972 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10762 {}}} CYCLES {}}
+set a(0-10762) {NAME ACC1-3:exs#35 TYPE SIGNEXTEND PAR 0-9373 XREFS 58973 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10761 {}}} SUCCS {{259 0 0-10763 {}}} CYCLES {}}
+set a(0-10763) {NAME ACC1:conc#1346 TYPE CONCATENATE PAR 0-9373 XREFS 58974 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10762 {}}} SUCCS {{258 0 0-10771 {}}} CYCLES {}}
+set a(0-10764) {NAME ACC1-3:slc(acc.idiv#1)#9 TYPE READSLICE PAR 0-9373 XREFS 58975 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10765 {}}} CYCLES {}}
+set a(0-10765) {NAME ACC1-3:exs#22 TYPE SIGNEXTEND PAR 0-9373 XREFS 58976 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10764 {}}} SUCCS {{258 0 0-10770 {}}} CYCLES {}}
+set a(0-10766) {NAME ACC1-2:slc(acc.imod#7) TYPE READSLICE PAR 0-9373 XREFS 58977 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-9759 {}}} SUCCS {{258 0 0-10769 {}}} CYCLES {}}
+set a(0-10767) {NAME ACC1:slc(acc#5.psp#2)#29 TYPE READSLICE PAR 0-9373 XREFS 58978 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-10768 {}}} CYCLES {}}
+set a(0-10768) {NAME ACC1-2:not#59 TYPE NOT PAR 0-9373 XREFS 58979 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10767 {}}} SUCCS {{259 0 0-10769 {}}} CYCLES {}}
+set a(0-10769) {NAME ACC1-2:nand#1 TYPE NAND PAR 0-9373 XREFS 58980 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10766 {}} {259 0 0-10768 {}}} SUCCS {{259 0 0-10770 {}}} CYCLES {}}
+set a(0-10770) {NAME ACC1:conc#1347 TYPE CONCATENATE PAR 0-9373 XREFS 58981 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10765 {}} {259 0 0-10769 {}}} SUCCS {{259 0 0-10771 {}}} CYCLES {}}
+set a(0-10771) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#444 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58982 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10763 {}} {259 0 0-10770 {}}} SUCCS {{259 0 0-10772 {}}} CYCLES {}}
+set a(0-10772) {NAME ACC1:slc#112 TYPE READSLICE PAR 0-9373 XREFS 58983 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10771 {}}} SUCCS {{258 0 0-10782 {}}} CYCLES {}}
+set a(0-10773) {NAME ACC1-1:slc(acc.idiv#1)#33 TYPE READSLICE PAR 0-9373 XREFS 58984 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10774 {}}} CYCLES {}}
+set a(0-10774) {NAME ACC1-1:exs#34 TYPE SIGNEXTEND PAR 0-9373 XREFS 58985 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10773 {}}} SUCCS {{259 0 0-10775 {}}} CYCLES {}}
+set a(0-10775) {NAME ACC1:conc#1342 TYPE CONCATENATE PAR 0-9373 XREFS 58986 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10774 {}}} SUCCS {{258 0 0-10780 {}}} CYCLES {}}
+set a(0-10776) {NAME ACC1-1:slc(acc.idiv#1)#35 TYPE READSLICE PAR 0-9373 XREFS 58987 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10777 {}}} CYCLES {}}
+set a(0-10777) {NAME ACC1-1:exs#35 TYPE SIGNEXTEND PAR 0-9373 XREFS 58988 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10776 {}}} SUCCS {{258 0 0-10779 {}}} CYCLES {}}
+set a(0-10778) {NAME ACC1:slc(ACC1-2:acc#212.psp)#11 TYPE READSLICE PAR 0-9373 XREFS 58989 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-9732 {}}} SUCCS {{259 0 0-10779 {}}} CYCLES {}}
+set a(0-10779) {NAME ACC1:conc#1343 TYPE CONCATENATE PAR 0-9373 XREFS 58990 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10777 {}} {259 0 0-10778 {}}} SUCCS {{259 0 0-10780 {}}} CYCLES {}}
+set a(0-10780) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#442 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58991 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10775 {}} {259 0 0-10779 {}}} SUCCS {{259 0 0-10781 {}}} CYCLES {}}
+set a(0-10781) {NAME ACC1:slc#110 TYPE READSLICE PAR 0-9373 XREFS 58992 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10780 {}}} SUCCS {{259 0 0-10782 {}}} CYCLES {}}
+set a(0-10782) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#533 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 58993 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10772 {}} {259 0 0-10781 {}}} SUCCS {{259 0 0-10783 {}}} CYCLES {}}
+set a(0-10783) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#582 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 58994 LOC {1 0.469524375 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-10760 {}} {259 0 0-10782 {}}} SUCCS {{259 0 0-10784 {}}} CYCLES {}}
+set a(0-10784) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#606 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-9373 XREFS 58995 LOC {1 0.52287145 1 0.578596 1 0.578596 1 0.637195709496936 1 0.637195709496936} PREDS {{258 0 0-10737 {}} {259 0 0-10783 {}}} SUCCS {{259 0 0-10785 {}}} CYCLES {}}
+set a(0-10785) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#623 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-9373 XREFS 58996 LOC {1 0.5814712 1 0.63719575 1 0.63719575 1 0.7007077234103024 1 0.7007077234103024} PREDS {{258 0 0-10695 {}} {259 0 0-10784 {}}} SUCCS {{258 0 0-10978 {}}} CYCLES {}}
+set a(0-10786) {NAME ACC1-1:slc(acc.idiv#1)#9 TYPE READSLICE PAR 0-9373 XREFS 58997 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10787 {}}} CYCLES {}}
+set a(0-10787) {NAME ACC1-1:exs#22 TYPE SIGNEXTEND PAR 0-9373 XREFS 58998 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10786 {}}} SUCCS {{259 0 0-10788 {}}} CYCLES {}}
+set a(0-10788) {NAME ACC1:conc#1340 TYPE CONCATENATE PAR 0-9373 XREFS 58999 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10787 {}}} SUCCS {{258 0 0-10793 {}}} CYCLES {}}
+set a(0-10789) {NAME ACC1-1:slc(acc.idiv#1)#11 TYPE READSLICE PAR 0-9373 XREFS 59000 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10790 {}}} CYCLES {}}
+set a(0-10790) {NAME ACC1-1:exs#23 TYPE SIGNEXTEND PAR 0-9373 XREFS 59001 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10789 {}}} SUCCS {{258 0 0-10792 {}}} CYCLES {}}
+set a(0-10791) {NAME ACC1:slc(ACC1-2:acc#212.psp)#10 TYPE READSLICE PAR 0-9373 XREFS 59002 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-9732 {}}} SUCCS {{259 0 0-10792 {}}} CYCLES {}}
+set a(0-10792) {NAME ACC1:conc#1341 TYPE CONCATENATE PAR 0-9373 XREFS 59003 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10790 {}} {259 0 0-10791 {}}} SUCCS {{259 0 0-10793 {}}} CYCLES {}}
+set a(0-10793) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#441 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59004 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10788 {}} {259 0 0-10792 {}}} SUCCS {{259 0 0-10794 {}}} CYCLES {}}
+set a(0-10794) {NAME ACC1:slc#109 TYPE READSLICE PAR 0-9373 XREFS 59005 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10793 {}}} SUCCS {{258 0 0-10804 {}}} CYCLES {}}
+set a(0-10795) {NAME ACC1-1:slc(acc.idiv#1)#1 TYPE READSLICE PAR 0-9373 XREFS 59006 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10796 {}}} CYCLES {}}
+set a(0-10796) {NAME ACC1-1:exs#18 TYPE SIGNEXTEND PAR 0-9373 XREFS 59007 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10795 {}}} SUCCS {{259 0 0-10797 {}}} CYCLES {}}
+set a(0-10797) {NAME ACC1:conc#1338 TYPE CONCATENATE PAR 0-9373 XREFS 59008 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10796 {}}} SUCCS {{258 0 0-10802 {}}} CYCLES {}}
+set a(0-10798) {NAME ACC1-1:slc(acc.idiv#1)#3 TYPE READSLICE PAR 0-9373 XREFS 59009 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10799 {}}} CYCLES {}}
+set a(0-10799) {NAME ACC1-1:exs#19 TYPE SIGNEXTEND PAR 0-9373 XREFS 59010 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10798 {}}} SUCCS {{258 0 0-10801 {}}} CYCLES {}}
+set a(0-10800) {NAME ACC1:slc(ACC1-2:acc#212.psp) TYPE READSLICE PAR 0-9373 XREFS 59011 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-9732 {}}} SUCCS {{259 0 0-10801 {}}} CYCLES {}}
+set a(0-10801) {NAME ACC1:conc#1339 TYPE CONCATENATE PAR 0-9373 XREFS 59012 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10799 {}} {259 0 0-10800 {}}} SUCCS {{259 0 0-10802 {}}} CYCLES {}}
+set a(0-10802) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#440 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59013 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10797 {}} {259 0 0-10801 {}}} SUCCS {{259 0 0-10803 {}}} CYCLES {}}
+set a(0-10803) {NAME ACC1:slc#108 TYPE READSLICE PAR 0-9373 XREFS 59014 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10802 {}}} SUCCS {{259 0 0-10804 {}}} CYCLES {}}
+set a(0-10804) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#532 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59015 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10794 {}} {259 0 0-10803 {}}} SUCCS {{258 0 0-10831 {}}} CYCLES {}}
+set a(0-10805) {NAME ACC1-1:slc(acc.idiv#1)#5 TYPE READSLICE PAR 0-9373 XREFS 59016 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10806 {}}} CYCLES {}}
+set a(0-10806) {NAME ACC1-1:exs#20 TYPE SIGNEXTEND PAR 0-9373 XREFS 59017 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10805 {}}} SUCCS {{259 0 0-10807 {}}} CYCLES {}}
+set a(0-10807) {NAME ACC1:conc#1336 TYPE CONCATENATE PAR 0-9373 XREFS 59018 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10806 {}}} SUCCS {{258 0 0-10816 {}}} CYCLES {}}
+set a(0-10808) {NAME ACC1-1:slc(acc.idiv#1)#7 TYPE READSLICE PAR 0-9373 XREFS 59019 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10809 {}}} CYCLES {}}
+set a(0-10809) {NAME ACC1-1:exs#21 TYPE SIGNEXTEND PAR 0-9373 XREFS 59020 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10808 {}}} SUCCS {{258 0 0-10815 {}}} CYCLES {}}
+set a(0-10810) {NAME ACC1-3:slc(acc#10.psp)#51 TYPE READSLICE PAR 0-9373 XREFS 59021 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9993 {}}} SUCCS {{258 0 0-10814 {}}} CYCLES {}}
+set a(0-10811) {NAME ACC1-3:slc(acc.imod#11)#1 TYPE READSLICE PAR 0-9373 XREFS 59022 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10057 {}}} SUCCS {{259 0 0-10812 {}}} CYCLES {}}
+set a(0-10812) {NAME ACC1-3:not#92 TYPE NOT PAR 0-9373 XREFS 59023 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10811 {}}} SUCCS {{258 0 0-10814 {}}} CYCLES {}}
+set a(0-10813) {NAME ACC1-3:slc(acc.imod#11)#2 TYPE READSLICE PAR 0-9373 XREFS 59024 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10057 {}}} SUCCS {{259 0 0-10814 {}}} CYCLES {}}
+set a(0-10814) {NAME ACC1-3:and#5 TYPE AND PAR 0-9373 XREFS 59025 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10812 {}} {258 0 0-10810 {}} {259 0 0-10813 {}}} SUCCS {{259 0 0-10815 {}}} CYCLES {}}
+set a(0-10815) {NAME ACC1:conc#1337 TYPE CONCATENATE PAR 0-9373 XREFS 59026 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10809 {}} {259 0 0-10814 {}}} SUCCS {{259 0 0-10816 {}}} CYCLES {}}
+set a(0-10816) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#439 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59027 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10807 {}} {259 0 0-10815 {}}} SUCCS {{259 0 0-10817 {}}} CYCLES {}}
+set a(0-10817) {NAME ACC1:slc#107 TYPE READSLICE PAR 0-9373 XREFS 59028 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10816 {}}} SUCCS {{258 0 0-10830 {}}} CYCLES {}}
+set a(0-10818) {NAME ACC1-1:slc(acc.idiv#1)#15 TYPE READSLICE PAR 0-9373 XREFS 59029 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10819 {}}} CYCLES {}}
+set a(0-10819) {NAME ACC1-1:exs#25 TYPE SIGNEXTEND PAR 0-9373 XREFS 59030 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10818 {}}} SUCCS {{259 0 0-10820 {}}} CYCLES {}}
+set a(0-10820) {NAME ACC1:conc#1334 TYPE CONCATENATE PAR 0-9373 XREFS 59031 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10819 {}}} SUCCS {{258 0 0-10828 {}}} CYCLES {}}
+set a(0-10821) {NAME ACC1-1:slc(acc.idiv#1)#17 TYPE READSLICE PAR 0-9373 XREFS 59032 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10822 {}}} CYCLES {}}
+set a(0-10822) {NAME ACC1-1:exs#26 TYPE SIGNEXTEND PAR 0-9373 XREFS 59033 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10821 {}}} SUCCS {{258 0 0-10827 {}}} CYCLES {}}
+set a(0-10823) {NAME ACC1-3:slc(acc.imod#11) TYPE READSLICE PAR 0-9373 XREFS 59034 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10057 {}}} SUCCS {{258 0 0-10826 {}}} CYCLES {}}
+set a(0-10824) {NAME ACC1-3:slc(acc#10.psp)#50 TYPE READSLICE PAR 0-9373 XREFS 59035 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10825 {}}} CYCLES {}}
+set a(0-10825) {NAME ACC1-3:not#91 TYPE NOT PAR 0-9373 XREFS 59036 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10824 {}}} SUCCS {{259 0 0-10826 {}}} CYCLES {}}
+set a(0-10826) {NAME ACC1-3:nand#2 TYPE NAND PAR 0-9373 XREFS 59037 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10823 {}} {259 0 0-10825 {}}} SUCCS {{259 0 0-10827 {}}} CYCLES {}}
+set a(0-10827) {NAME ACC1:conc#1335 TYPE CONCATENATE PAR 0-9373 XREFS 59038 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10822 {}} {259 0 0-10826 {}}} SUCCS {{259 0 0-10828 {}}} CYCLES {}}
+set a(0-10828) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#438 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59039 LOC {1 0.374412025 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10820 {}} {259 0 0-10827 {}}} SUCCS {{259 0 0-10829 {}}} CYCLES {}}
+set a(0-10829) {NAME ACC1:slc#106 TYPE READSLICE PAR 0-9373 XREFS 59040 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10828 {}}} SUCCS {{259 0 0-10830 {}}} CYCLES {}}
+set a(0-10830) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#531 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59041 LOC {1 0.42196819999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10817 {}} {259 0 0-10829 {}}} SUCCS {{259 0 0-10831 {}}} CYCLES {}}
+set a(0-10831) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#581 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59042 LOC {1 0.469524375 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-10804 {}} {259 0 0-10830 {}}} SUCCS {{258 0 0-10871 {}}} CYCLES {}}
+set a(0-10832) {NAME ACC1-1:slc(acc.idiv#1)#13 TYPE READSLICE PAR 0-9373 XREFS 59043 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10833 {}}} CYCLES {}}
+set a(0-10833) {NAME ACC1-1:exs#24 TYPE SIGNEXTEND PAR 0-9373 XREFS 59044 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10832 {}}} SUCCS {{259 0 0-10834 {}}} CYCLES {}}
+set a(0-10834) {NAME ACC1:conc#1332 TYPE CONCATENATE PAR 0-9373 XREFS 59045 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10833 {}}} SUCCS {{258 0 0-10839 {}}} CYCLES {}}
+set a(0-10835) {NAME ACC1-1:slc(acc.idiv#1)#23 TYPE READSLICE PAR 0-9373 XREFS 59046 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10836 {}}} CYCLES {}}
+set a(0-10836) {NAME ACC1-1:exs#29 TYPE SIGNEXTEND PAR 0-9373 XREFS 59047 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10835 {}}} SUCCS {{258 0 0-10838 {}}} CYCLES {}}
+set a(0-10837) {NAME ACC1:slc(acc.imod#10) TYPE READSLICE PAR 0-9373 XREFS 59048 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.43013657499999997} PREDS {{258 0 0-10048 {}}} SUCCS {{259 0 0-10838 {}}} CYCLES {}}
+set a(0-10838) {NAME ACC1:conc#1333 TYPE CONCATENATE PAR 0-9373 XREFS 59049 LOC {1 0.3471661 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10836 {}} {259 0 0-10837 {}}} SUCCS {{259 0 0-10839 {}}} CYCLES {}}
+set a(0-10839) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#437 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59050 LOC {1 0.3471661 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10834 {}} {259 0 0-10838 {}}} SUCCS {{259 0 0-10840 {}}} CYCLES {}}
+set a(0-10840) {NAME ACC1:slc#105 TYPE READSLICE PAR 0-9373 XREFS 59051 LOC {1 0.39472227499999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10839 {}}} SUCCS {{258 0 0-10850 {}}} CYCLES {}}
+set a(0-10841) {NAME ACC1-1:slc(acc.idiv#1)#19 TYPE READSLICE PAR 0-9373 XREFS 59052 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10842 {}}} CYCLES {}}
+set a(0-10842) {NAME ACC1-1:exs#27 TYPE SIGNEXTEND PAR 0-9373 XREFS 59053 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10841 {}}} SUCCS {{259 0 0-10843 {}}} CYCLES {}}
+set a(0-10843) {NAME ACC1:conc#1330 TYPE CONCATENATE PAR 0-9373 XREFS 59054 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10842 {}}} SUCCS {{258 0 0-10848 {}}} CYCLES {}}
+set a(0-10844) {NAME ACC1-1:slc(acc.idiv#1)#21 TYPE READSLICE PAR 0-9373 XREFS 59055 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10845 {}}} CYCLES {}}
+set a(0-10845) {NAME ACC1-1:exs#28 TYPE SIGNEXTEND PAR 0-9373 XREFS 59056 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10844 {}}} SUCCS {{258 0 0-10847 {}}} CYCLES {}}
+set a(0-10846) {NAME ACC1:slc(ACC1:acc#214.psp#1)#11 TYPE READSLICE PAR 0-9373 XREFS 59057 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-10030 {}}} SUCCS {{259 0 0-10847 {}}} CYCLES {}}
+set a(0-10847) {NAME ACC1:conc#1331 TYPE CONCATENATE PAR 0-9373 XREFS 59058 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10845 {}} {259 0 0-10846 {}}} SUCCS {{259 0 0-10848 {}}} CYCLES {}}
+set a(0-10848) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#436 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59059 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10843 {}} {259 0 0-10847 {}}} SUCCS {{259 0 0-10849 {}}} CYCLES {}}
+set a(0-10849) {NAME ACC1:slc#104 TYPE READSLICE PAR 0-9373 XREFS 59060 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10848 {}}} SUCCS {{259 0 0-10850 {}}} CYCLES {}}
+set a(0-10850) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#530 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59061 LOC {1 0.39472227499999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10840 {}} {259 0 0-10849 {}}} SUCCS {{258 0 0-10870 {}}} CYCLES {}}
+set a(0-10851) {NAME ACC1-1:slc(acc.idiv#1)#31 TYPE READSLICE PAR 0-9373 XREFS 59062 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10852 {}}} CYCLES {}}
+set a(0-10852) {NAME ACC1-1:exs#33 TYPE SIGNEXTEND PAR 0-9373 XREFS 59063 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10851 {}}} SUCCS {{259 0 0-10853 {}}} CYCLES {}}
+set a(0-10853) {NAME ACC1:conc#1328 TYPE CONCATENATE PAR 0-9373 XREFS 59064 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10852 {}}} SUCCS {{258 0 0-10858 {}}} CYCLES {}}
+set a(0-10854) {NAME ACC1-1:slc(acc#5.psp)#65 TYPE READSLICE PAR 0-9373 XREFS 59065 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10855 {}}} CYCLES {}}
+set a(0-10855) {NAME ACC1-1:exs#1031 TYPE SIGNEXTEND PAR 0-9373 XREFS 59066 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10854 {}}} SUCCS {{258 0 0-10857 {}}} CYCLES {}}
+set a(0-10856) {NAME ACC1:slc(ACC1:acc#214.psp#1)#10 TYPE READSLICE PAR 0-9373 XREFS 59067 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-10030 {}}} SUCCS {{259 0 0-10857 {}}} CYCLES {}}
+set a(0-10857) {NAME ACC1:conc#1329 TYPE CONCATENATE PAR 0-9373 XREFS 59068 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10855 {}} {259 0 0-10856 {}}} SUCCS {{259 0 0-10858 {}}} CYCLES {}}
+set a(0-10858) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#435 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59069 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10853 {}} {259 0 0-10857 {}}} SUCCS {{259 0 0-10859 {}}} CYCLES {}}
+set a(0-10859) {NAME ACC1:slc#103 TYPE READSLICE PAR 0-9373 XREFS 59070 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10858 {}}} SUCCS {{258 0 0-10869 {}}} CYCLES {}}
+set a(0-10860) {NAME ACC1-1:slc(acc.idiv#1)#27 TYPE READSLICE PAR 0-9373 XREFS 59071 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10861 {}}} CYCLES {}}
+set a(0-10861) {NAME ACC1-1:exs#31 TYPE SIGNEXTEND PAR 0-9373 XREFS 59072 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10860 {}}} SUCCS {{259 0 0-10862 {}}} CYCLES {}}
+set a(0-10862) {NAME ACC1:conc#1326 TYPE CONCATENATE PAR 0-9373 XREFS 59073 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10861 {}}} SUCCS {{258 0 0-10867 {}}} CYCLES {}}
+set a(0-10863) {NAME ACC1-1:slc(acc.idiv#1)#29 TYPE READSLICE PAR 0-9373 XREFS 59074 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.43013657499999997} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-10864 {}}} CYCLES {}}
+set a(0-10864) {NAME ACC1-1:exs#32 TYPE SIGNEXTEND PAR 0-9373 XREFS 59075 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10863 {}}} SUCCS {{258 0 0-10866 {}}} CYCLES {}}
+set a(0-10865) {NAME ACC1:slc(ACC1:acc#214.psp#1) TYPE READSLICE PAR 0-9373 XREFS 59076 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-10030 {}}} SUCCS {{259 0 0-10866 {}}} CYCLES {}}
+set a(0-10866) {NAME ACC1:conc#1327 TYPE CONCATENATE PAR 0-9373 XREFS 59077 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10864 {}} {259 0 0-10865 {}}} SUCCS {{259 0 0-10867 {}}} CYCLES {}}
+set a(0-10867) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#434 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59078 LOC {1 0.258664325 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10862 {}} {259 0 0-10866 {}}} SUCCS {{259 0 0-10868 {}}} CYCLES {}}
+set a(0-10868) {NAME ACC1:slc#102 TYPE READSLICE PAR 0-9373 XREFS 59079 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10867 {}}} SUCCS {{259 0 0-10869 {}}} CYCLES {}}
+set a(0-10869) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#529 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59080 LOC {1 0.3062205 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10859 {}} {259 0 0-10868 {}}} SUCCS {{259 0 0-10870 {}}} CYCLES {}}
+set a(0-10870) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#580 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59081 LOC {1 0.44227845 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-10850 {}} {259 0 0-10869 {}}} SUCCS {{259 0 0-10871 {}}} CYCLES {}}
+set a(0-10871) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#605 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-9373 XREFS 59082 LOC {1 0.52287145 1 0.578596 1 0.578596 1 0.637195709496936 1 0.637195709496936} PREDS {{258 0 0-10831 {}} {259 0 0-10870 {}}} SUCCS {{258 0 0-10977 {}}} CYCLES {}}
+set a(0-10872) {NAME ACC1:slc(ACC1:acc#227.psp)#56 TYPE READSLICE PAR 0-9373 XREFS 59083 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{258 0 0-10874 {}}} CYCLES {}}
+set a(0-10873) {NAME ACC1:slc(ACC1:acc#227.psp)#57 TYPE READSLICE PAR 0-9373 XREFS 59084 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10874 {}}} CYCLES {}}
+set a(0-10874) {NAME ACC1:conc#1324 TYPE CONCATENATE PAR 0-9373 XREFS 59085 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10872 {}} {259 0 0-10873 {}}} SUCCS {{259 0 0-10875 {}}} CYCLES {}}
+set a(0-10875) {NAME ACC1:conc TYPE CONCATENATE PAR 0-9373 XREFS 59086 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10874 {}}} SUCCS {{258 0 0-10885 {}}} CYCLES {}}
+set a(0-10876) {NAME ACC1:slc(acc.psp#1)#55 TYPE READSLICE PAR 0-9373 XREFS 59087 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-9839 {}}} SUCCS {{258 0 0-10878 {}}} CYCLES {}}
+set a(0-10877) {NAME ACC1:slc(ACC1:acc#227.psp)#58 TYPE READSLICE PAR 0-9373 XREFS 59088 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10878 {}}} CYCLES {}}
+set a(0-10878) {NAME ACC1:conc#1070 TYPE CONCATENATE PAR 0-9373 XREFS 59089 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10876 {}} {259 0 0-10877 {}}} SUCCS {{258 0 0-10884 {}}} CYCLES {}}
+set a(0-10879) {NAME ACC1-3:slc(acc.idiv)#45 TYPE READSLICE PAR 0-9373 XREFS 59090 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-9839 {}}} SUCCS {{258 0 0-10883 {}}} CYCLES {}}
+set a(0-10880) {NAME ACC1-3:slc(acc.imod#3)#1 TYPE READSLICE PAR 0-9373 XREFS 59091 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-9906 {}}} SUCCS {{259 0 0-10881 {}}} CYCLES {}}
+set a(0-10881) {NAME ACC1-3:not#28 TYPE NOT PAR 0-9373 XREFS 59092 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10880 {}}} SUCCS {{258 0 0-10883 {}}} CYCLES {}}
+set a(0-10882) {NAME ACC1-3:slc(acc.imod#3)#2 TYPE READSLICE PAR 0-9373 XREFS 59093 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-9906 {}}} SUCCS {{259 0 0-10883 {}}} CYCLES {}}
+set a(0-10883) {NAME ACC1-3:and#1 TYPE AND PAR 0-9373 XREFS 59094 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10881 {}} {258 0 0-10879 {}} {259 0 0-10882 {}}} SUCCS {{259 0 0-10884 {}}} CYCLES {}}
+set a(0-10884) {NAME ACC1:conc#1325 TYPE CONCATENATE PAR 0-9373 XREFS 59095 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10878 {}} {259 0 0-10883 {}}} SUCCS {{259 0 0-10885 {}}} CYCLES {}}
+set a(0-10885) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#433 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59096 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10875 {}} {259 0 0-10884 {}}} SUCCS {{259 0 0-10886 {}}} CYCLES {}}
+set a(0-10886) {NAME ACC1:slc#101 TYPE READSLICE PAR 0-9373 XREFS 59097 LOC {1 0.43123487499999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10885 {}}} SUCCS {{258 0 0-10901 {}}} CYCLES {}}
+set a(0-10887) {NAME ACC1:slc(ACC1:acc#224.psp)#46 TYPE READSLICE PAR 0-9373 XREFS 59098 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9993 {}}} SUCCS {{258 0 0-10889 {}}} CYCLES {}}
+set a(0-10888) {NAME ACC1:slc(ACC1:acc#227.psp)#59 TYPE READSLICE PAR 0-9373 XREFS 59099 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10889 {}}} CYCLES {}}
+set a(0-10889) {NAME ACC1:conc#1071 TYPE CONCATENATE PAR 0-9373 XREFS 59100 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10887 {}} {259 0 0-10888 {}}} SUCCS {{259 0 0-10890 {}}} CYCLES {}}
+set a(0-10890) {NAME ACC1:conc#1322 TYPE CONCATENATE PAR 0-9373 XREFS 59101 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10889 {}}} SUCCS {{258 0 0-10899 {}}} CYCLES {}}
+set a(0-10891) {NAME ACC1:slc(ACC1:acc#228.psp)#46 TYPE READSLICE PAR 0-9373 XREFS 59102 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9695 {}}} SUCCS {{258 0 0-10893 {}}} CYCLES {}}
+set a(0-10892) {NAME ACC1:slc(ACC1:acc#227.psp)#60 TYPE READSLICE PAR 0-9373 XREFS 59103 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.43013657499999997} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-10893 {}}} CYCLES {}}
+set a(0-10893) {NAME ACC1:conc#1072 TYPE CONCATENATE PAR 0-9373 XREFS 59104 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10891 {}} {259 0 0-10892 {}}} SUCCS {{258 0 0-10898 {}}} CYCLES {}}
+set a(0-10894) {NAME ACC1-3:slc(acc.imod#3) TYPE READSLICE PAR 0-9373 XREFS 59105 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-9906 {}}} SUCCS {{258 0 0-10897 {}}} CYCLES {}}
+set a(0-10895) {NAME ACC1-3:slc(acc.idiv)#44 TYPE READSLICE PAR 0-9373 XREFS 59106 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-10896 {}}} CYCLES {}}
+set a(0-10896) {NAME ACC1-3:not#27 TYPE NOT PAR 0-9373 XREFS 59107 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10895 {}}} SUCCS {{259 0 0-10897 {}}} CYCLES {}}
+set a(0-10897) {NAME ACC1-3:nand TYPE NAND PAR 0-9373 XREFS 59108 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10894 {}} {259 0 0-10896 {}}} SUCCS {{259 0 0-10898 {}}} CYCLES {}}
+set a(0-10898) {NAME ACC1:conc#1323 TYPE CONCATENATE PAR 0-9373 XREFS 59109 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10893 {}} {259 0 0-10897 {}}} SUCCS {{259 0 0-10899 {}}} CYCLES {}}
+set a(0-10899) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#432 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59110 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10890 {}} {259 0 0-10898 {}}} SUCCS {{259 0 0-10900 {}}} CYCLES {}}
+set a(0-10900) {NAME ACC1:slc#100 TYPE READSLICE PAR 0-9373 XREFS 59111 LOC {1 0.43123487499999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10899 {}}} SUCCS {{259 0 0-10901 {}}} CYCLES {}}
+set a(0-10901) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#528 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59112 LOC {1 0.43123487499999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10886 {}} {259 0 0-10900 {}}} SUCCS {{258 0 0-10925 {}}} CYCLES {}}
+set a(0-10902) {NAME ACC1:slc(ACC1:acc#226.psp)#37 TYPE READSLICE PAR 0-9373 XREFS 59113 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9767 {}}} SUCCS {{258 0 0-10904 {}}} CYCLES {}}
+set a(0-10903) {NAME ACC1:slc(acc.psp#1)#56 TYPE READSLICE PAR 0-9373 XREFS 59114 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-10904 {}}} CYCLES {}}
+set a(0-10904) {NAME ACC1:conc#1073 TYPE CONCATENATE PAR 0-9373 XREFS 59115 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10902 {}} {259 0 0-10903 {}}} SUCCS {{259 0 0-10905 {}}} CYCLES {}}
+set a(0-10905) {NAME ACC1:conc#1320 TYPE CONCATENATE PAR 0-9373 XREFS 59116 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10904 {}}} SUCCS {{258 0 0-10911 {}}} CYCLES {}}
+set a(0-10906) {NAME ACC1:slc(ACC1:acc#224.psp#1)#18 TYPE READSLICE PAR 0-9373 XREFS 59117 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.43013657499999997} PREDS {{258 0 0-9471 {}}} SUCCS {{258 0 0-10908 {}}} CYCLES {}}
+set a(0-10907) {NAME ACC1:slc(acc.psp#1)#58 TYPE READSLICE PAR 0-9373 XREFS 59118 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-10908 {}}} CYCLES {}}
+set a(0-10908) {NAME ACC1:conc#1076 TYPE CONCATENATE PAR 0-9373 XREFS 59119 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10906 {}} {259 0 0-10907 {}}} SUCCS {{258 0 0-10910 {}}} CYCLES {}}
+set a(0-10909) {NAME ACC1:slc(acc.imod#2) TYPE READSLICE PAR 0-9373 XREFS 59120 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.43013657499999997} PREDS {{258 0 0-9897 {}}} SUCCS {{259 0 0-10910 {}}} CYCLES {}}
+set a(0-10910) {NAME ACC1:conc#1321 TYPE CONCATENATE PAR 0-9373 XREFS 59121 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10908 {}} {259 0 0-10909 {}}} SUCCS {{259 0 0-10911 {}}} CYCLES {}}
+set a(0-10911) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#431 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59122 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10905 {}} {259 0 0-10910 {}}} SUCCS {{259 0 0-10912 {}}} CYCLES {}}
+set a(0-10912) {NAME ACC1:slc#99 TYPE READSLICE PAR 0-9373 XREFS 59123 LOC {1 0.40398894999999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10911 {}}} SUCCS {{258 0 0-10924 {}}} CYCLES {}}
+set a(0-10913) {NAME ACC1:slc(ACC1-1:acc#25.psp)#19 TYPE READSLICE PAR 0-9373 XREFS 59124 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{258 0 0-10915 {}}} CYCLES {}}
+set a(0-10914) {NAME ACC1:slc(acc.psp#1)#59 TYPE READSLICE PAR 0-9373 XREFS 59125 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-10915 {}}} CYCLES {}}
+set a(0-10915) {NAME ACC1:conc#1077 TYPE CONCATENATE PAR 0-9373 XREFS 59126 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10913 {}} {259 0 0-10914 {}}} SUCCS {{259 0 0-10916 {}}} CYCLES {}}
+set a(0-10916) {NAME ACC1:conc#1318 TYPE CONCATENATE PAR 0-9373 XREFS 59127 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10915 {}}} SUCCS {{258 0 0-10922 {}}} CYCLES {}}
+set a(0-10917) {NAME ACC1:slc(acc#20.psp#1) TYPE READSLICE PAR 0-9373 XREFS 59128 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10919 {}}} CYCLES {}}
+set a(0-10918) {NAME ACC1:slc(ACC1:acc#224.psp)#48 TYPE READSLICE PAR 0-9373 XREFS 59129 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10919 {}}} CYCLES {}}
+set a(0-10919) {NAME ACC1:conc#1080 TYPE CONCATENATE PAR 0-9373 XREFS 59130 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10917 {}} {259 0 0-10918 {}}} SUCCS {{258 0 0-10921 {}}} CYCLES {}}
+set a(0-10920) {NAME ACC1:slc(ACC1:acc#210.psp#1)#14 TYPE READSLICE PAR 0-9373 XREFS 59131 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-9879 {}}} SUCCS {{259 0 0-10921 {}}} CYCLES {}}
+set a(0-10921) {NAME ACC1:conc#1319 TYPE CONCATENATE PAR 0-9373 XREFS 59132 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10919 {}} {259 0 0-10920 {}}} SUCCS {{259 0 0-10922 {}}} CYCLES {}}
+set a(0-10922) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#430 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59133 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10916 {}} {259 0 0-10921 {}}} SUCCS {{259 0 0-10923 {}}} CYCLES {}}
+set a(0-10923) {NAME ACC1:slc#98 TYPE READSLICE PAR 0-9373 XREFS 59134 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10922 {}}} SUCCS {{259 0 0-10924 {}}} CYCLES {}}
+set a(0-10924) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#527 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59135 LOC {1 0.40398894999999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10912 {}} {259 0 0-10923 {}}} SUCCS {{259 0 0-10925 {}}} CYCLES {}}
+set a(0-10925) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#579 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59136 LOC {1 0.47879105 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-10901 {}} {259 0 0-10924 {}}} SUCCS {{258 0 0-10976 {}}} CYCLES {}}
+set a(0-10926) {NAME ACC1:slc(acc#20.psp#1)#32 TYPE READSLICE PAR 0-9373 XREFS 59137 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10928 {}}} CYCLES {}}
+set a(0-10927) {NAME ACC1:slc(ACC1:acc#224.psp)#49 TYPE READSLICE PAR 0-9373 XREFS 59138 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10928 {}}} CYCLES {}}
+set a(0-10928) {NAME ACC1:conc#1081 TYPE CONCATENATE PAR 0-9373 XREFS 59139 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10926 {}} {259 0 0-10927 {}}} SUCCS {{259 0 0-10929 {}}} CYCLES {}}
+set a(0-10929) {NAME ACC1:conc#1316 TYPE CONCATENATE PAR 0-9373 XREFS 59140 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10928 {}}} SUCCS {{258 0 0-10935 {}}} CYCLES {}}
+set a(0-10930) {NAME ACC1:slc(acc#20.psp#1)#33 TYPE READSLICE PAR 0-9373 XREFS 59141 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10932 {}}} CYCLES {}}
+set a(0-10931) {NAME ACC1:slc(ACC1:acc#224.psp)#50 TYPE READSLICE PAR 0-9373 XREFS 59142 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10932 {}}} CYCLES {}}
+set a(0-10932) {NAME ACC1:conc#1082 TYPE CONCATENATE PAR 0-9373 XREFS 59143 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10930 {}} {259 0 0-10931 {}}} SUCCS {{258 0 0-10934 {}}} CYCLES {}}
+set a(0-10933) {NAME ACC1:slc(ACC1:acc#210.psp#1)#13 TYPE READSLICE PAR 0-9373 XREFS 59144 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-9879 {}}} SUCCS {{259 0 0-10934 {}}} CYCLES {}}
+set a(0-10934) {NAME ACC1:conc#1317 TYPE CONCATENATE PAR 0-9373 XREFS 59145 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10932 {}} {259 0 0-10933 {}}} SUCCS {{259 0 0-10935 {}}} CYCLES {}}
+set a(0-10935) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#429 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59146 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10929 {}} {259 0 0-10934 {}}} SUCCS {{259 0 0-10936 {}}} CYCLES {}}
+set a(0-10936) {NAME ACC1:slc#97 TYPE READSLICE PAR 0-9373 XREFS 59147 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10935 {}}} SUCCS {{258 0 0-10948 {}}} CYCLES {}}
+set a(0-10937) {NAME ACC1:slc(acc#20.psp#1)#34 TYPE READSLICE PAR 0-9373 XREFS 59148 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10939 {}}} CYCLES {}}
+set a(0-10938) {NAME ACC1:slc(ACC1:acc#228.psp)#47 TYPE READSLICE PAR 0-9373 XREFS 59149 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-10939 {}}} CYCLES {}}
+set a(0-10939) {NAME ACC1:conc#1083 TYPE CONCATENATE PAR 0-9373 XREFS 59150 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10937 {}} {259 0 0-10938 {}}} SUCCS {{259 0 0-10940 {}}} CYCLES {}}
+set a(0-10940) {NAME ACC1:conc#1314 TYPE CONCATENATE PAR 0-9373 XREFS 59151 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10939 {}}} SUCCS {{258 0 0-10946 {}}} CYCLES {}}
+set a(0-10941) {NAME ACC1:slc(ACC1:acc#217.psp#1) TYPE READSLICE PAR 0-9373 XREFS 59152 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-10105 {}}} SUCCS {{258 0 0-10943 {}}} CYCLES {}}
+set a(0-10942) {NAME ACC1:slc(ACC1:acc#226.psp)#38 TYPE READSLICE PAR 0-9373 XREFS 59153 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-10943 {}}} CYCLES {}}
+set a(0-10943) {NAME ACC1:conc#1090 TYPE CONCATENATE PAR 0-9373 XREFS 59154 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10941 {}} {259 0 0-10942 {}}} SUCCS {{258 0 0-10945 {}}} CYCLES {}}
+set a(0-10944) {NAME ACC1:slc(ACC1:acc#210.psp#1) TYPE READSLICE PAR 0-9373 XREFS 59155 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-9879 {}}} SUCCS {{259 0 0-10945 {}}} CYCLES {}}
+set a(0-10945) {NAME ACC1:conc#1315 TYPE CONCATENATE PAR 0-9373 XREFS 59156 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10943 {}} {259 0 0-10944 {}}} SUCCS {{259 0 0-10946 {}}} CYCLES {}}
+set a(0-10946) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#428 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59157 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10940 {}} {259 0 0-10945 {}}} SUCCS {{259 0 0-10947 {}}} CYCLES {}}
+set a(0-10947) {NAME ACC1:slc#96 TYPE READSLICE PAR 0-9373 XREFS 59158 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10946 {}}} SUCCS {{259 0 0-10948 {}}} CYCLES {}}
+set a(0-10948) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#526 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59159 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10936 {}} {259 0 0-10947 {}}} SUCCS {{258 0 0-10975 {}}} CYCLES {}}
+set a(0-10949) {NAME ACC1:slc(ACC1:acc#217.psp#1)#13 TYPE READSLICE PAR 0-9373 XREFS 59160 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-10105 {}}} SUCCS {{258 0 0-10951 {}}} CYCLES {}}
+set a(0-10950) {NAME ACC1:slc(ACC1:acc#226.psp)#39 TYPE READSLICE PAR 0-9373 XREFS 59161 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-10951 {}}} CYCLES {}}
+set a(0-10951) {NAME ACC1:conc#1091 TYPE CONCATENATE PAR 0-9373 XREFS 59162 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10949 {}} {259 0 0-10950 {}}} SUCCS {{259 0 0-10952 {}}} CYCLES {}}
+set a(0-10952) {NAME ACC1:conc#1312 TYPE CONCATENATE PAR 0-9373 XREFS 59163 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10951 {}}} SUCCS {{258 0 0-10958 {}}} CYCLES {}}
+set a(0-10953) {NAME ACC1:slc(ACC1:acc#217.psp#1)#14 TYPE READSLICE PAR 0-9373 XREFS 59164 LOC {1 0.267931 1 0.314388875 1 0.314388875 1 0.43013657499999997} PREDS {{258 0 0-10105 {}}} SUCCS {{258 0 0-10955 {}}} CYCLES {}}
+set a(0-10954) {NAME ACC1:slc(ACC1:acc#226.psp)#40 TYPE READSLICE PAR 0-9373 XREFS 59165 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-10955 {}}} CYCLES {}}
+set a(0-10955) {NAME ACC1:conc#1092 TYPE CONCATENATE PAR 0-9373 XREFS 59166 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10953 {}} {259 0 0-10954 {}}} SUCCS {{258 0 0-10957 {}}} CYCLES {}}
+set a(0-10956) {NAME ACC1:slc(ACC1-1:acc#25.psp)#18 TYPE READSLICE PAR 0-9373 XREFS 59167 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10957 {}}} CYCLES {}}
+set a(0-10957) {NAME ACC1:conc#1313 TYPE CONCATENATE PAR 0-9373 XREFS 59168 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10955 {}} {259 0 0-10956 {}}} SUCCS {{259 0 0-10958 {}}} CYCLES {}}
+set a(0-10958) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#427 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59169 LOC {1 0.267931 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10952 {}} {259 0 0-10957 {}}} SUCCS {{259 0 0-10959 {}}} CYCLES {}}
+set a(0-10959) {NAME ACC1:slc#95 TYPE READSLICE PAR 0-9373 XREFS 59170 LOC {1 0.315487175 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10958 {}}} SUCCS {{258 0 0-10974 {}}} CYCLES {}}
+set a(0-10960) {NAME ACC1:slc(acc.imod#18) TYPE READSLICE PAR 0-9373 XREFS 59171 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.43013657499999997} PREDS {{258 0 0-10123 {}}} SUCCS {{258 0 0-10962 {}}} CYCLES {}}
+set a(0-10961) {NAME ACC1:slc(ACC1:acc#226.psp)#41 TYPE READSLICE PAR 0-9373 XREFS 59172 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.43013657499999997} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-10962 {}}} CYCLES {}}
+set a(0-10962) {NAME ACC1:conc#1093 TYPE CONCATENATE PAR 0-9373 XREFS 59173 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10960 {}} {259 0 0-10961 {}}} SUCCS {{259 0 0-10963 {}}} CYCLES {}}
+set a(0-10963) {NAME ACC1:conc#1310 TYPE CONCATENATE PAR 0-9373 XREFS 59174 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10962 {}}} SUCCS {{258 0 0-10972 {}}} CYCLES {}}
+set a(0-10964) {NAME ACC1-3:slc(acc.imod#19) TYPE READSLICE PAR 0-9373 XREFS 59175 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10132 {}}} SUCCS {{258 0 0-10967 {}}} CYCLES {}}
+set a(0-10965) {NAME ACC1-3:slc(acc.idiv#4)#44 TYPE READSLICE PAR 0-9373 XREFS 59176 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.43013657499999997} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-10966 {}}} CYCLES {}}
+set a(0-10966) {NAME ACC1-3:not#155 TYPE NOT PAR 0-9373 XREFS 59177 LOC {1 0.14655495 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{259 0 0-10965 {}}} SUCCS {{259 0 0-10967 {}}} CYCLES {}}
+set a(0-10967) {NAME ACC1-3:nand#4 TYPE NAND PAR 0-9373 XREFS 59178 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10964 {}} {259 0 0-10966 {}}} SUCCS {{258 0 0-10969 {}}} CYCLES {}}
+set a(0-10968) {NAME ACC1:slc(ACC1:acc#224.psp#1)#19 TYPE READSLICE PAR 0-9373 XREFS 59179 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.43013657499999997} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-10969 {}}} CYCLES {}}
+set a(0-10969) {NAME ACC1:conc#1094 TYPE CONCATENATE PAR 0-9373 XREFS 59180 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10967 {}} {259 0 0-10968 {}}} SUCCS {{258 0 0-10971 {}}} CYCLES {}}
+set a(0-10970) {NAME ACC1:slc(ACC1-1:acc#25.psp)#17 TYPE READSLICE PAR 0-9373 XREFS 59181 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.43013657499999997} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-10971 {}}} CYCLES {}}
+set a(0-10971) {NAME ACC1:conc#1311 TYPE CONCATENATE PAR 0-9373 XREFS 59182 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.43013657499999997} PREDS {{258 0 0-10969 {}} {259 0 0-10970 {}}} SUCCS {{259 0 0-10972 {}}} CYCLES {}}
+set a(0-10972) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#426 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59183 LOC {1 0.3836787 1 0.43013657499999997 1 0.43013657499999997 1 0.47769270207082715 1 0.47769270207082715} PREDS {{258 0 0-10963 {}} {259 0 0-10971 {}}} SUCCS {{259 0 0-10973 {}}} CYCLES {}}
+set a(0-10973) {NAME ACC1:slc#94 TYPE READSLICE PAR 0-9373 XREFS 59184 LOC {1 0.43123487499999996 1 0.47769275 1 0.47769275 1 0.47769275} PREDS {{259 0 0-10972 {}}} SUCCS {{259 0 0-10974 {}}} CYCLES {}}
+set a(0-10974) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#525 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59185 LOC {1 0.43123487499999996 1 0.47769275 1 0.47769275 1 0.5252488770708271 1 0.5252488770708271} PREDS {{258 0 0-10959 {}} {259 0 0-10973 {}}} SUCCS {{259 0 0-10975 {}}} CYCLES {}}
+set a(0-10975) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#578 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59186 LOC {1 0.47879105 1 0.525248925 1 0.525248925 1 0.5785959451789504 1 0.5785959451789504} PREDS {{258 0 0-10948 {}} {259 0 0-10974 {}}} SUCCS {{259 0 0-10976 {}}} CYCLES {}}
+set a(0-10976) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#604 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-9373 XREFS 59187 LOC {1 0.532138125 1 0.578596 1 0.578596 1 0.637195709496936 1 0.637195709496936} PREDS {{258 0 0-10925 {}} {259 0 0-10975 {}}} SUCCS {{259 0 0-10977 {}}} CYCLES {}}
+set a(0-10977) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#622 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-9373 XREFS 59188 LOC {1 0.590737875 1 0.63719575 1 0.63719575 1 0.7007077234103024 1 0.7007077234103024} PREDS {{258 0 0-10871 {}} {259 0 0-10976 {}}} SUCCS {{259 0 0-10978 {}}} CYCLES {}}
+set a(0-10978) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#636 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-9373 XREFS 59189 LOC {1 0.6542498999999999 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-10785 {}} {259 0 0-10977 {}}} SUCCS {{258 0 0-11004 {}}} CYCLES {}}
+set a(0-10979) {NAME slc(acc#20.psp#1)#82 TYPE READSLICE PAR 0-9373 XREFS 59190 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10983 {}}} CYCLES {}}
+set a(0-10980) {NAME slc(acc#20.psp#1)#83 TYPE READSLICE PAR 0-9373 XREFS 59191 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10983 {}}} CYCLES {}}
+set a(0-10981) {NAME slc(acc#20.psp#1)#77 TYPE READSLICE PAR 0-9373 XREFS 59192 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10983 {}}} CYCLES {}}
+set a(0-10982) {NAME ACC1:slc(ACC1:acc#228.psp)#48 TYPE READSLICE PAR 0-9373 XREFS 59193 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-10983 {}}} CYCLES {}}
+set a(0-10983) {NAME ACC1:conc#1084 TYPE CONCATENATE PAR 0-9373 XREFS 59194 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-10981 {}} {258 0 0-10980 {}} {258 0 0-10979 {}} {259 0 0-10982 {}}} SUCCS {{258 0 0-10990 {}}} CYCLES {}}
+set a(0-10984) {NAME ACC1:slc(acc.psp#1)#62 TYPE READSLICE PAR 0-9373 XREFS 59195 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-9839 {}}} SUCCS {{258 0 0-10989 {}}} CYCLES {}}
+set a(0-10985) {NAME ACC1:slc(acc#20.psp#1)#37 TYPE READSLICE PAR 0-9373 XREFS 59196 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10989 {}}} CYCLES {}}
+set a(0-10986) {NAME ACC1:slc(ACC1:acc#226.psp)#45 TYPE READSLICE PAR 0-9373 XREFS 59197 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9767 {}}} SUCCS {{258 0 0-10989 {}}} CYCLES {}}
+set a(0-10987) {NAME ACC1-3:slc(acc#10.psp)#61 TYPE READSLICE PAR 0-9373 XREFS 59198 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10988 {}}} CYCLES {}}
+set a(0-10988) {NAME ACC1-3:exs#38 TYPE SIGNEXTEND PAR 0-9373 XREFS 59199 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-10987 {}}} SUCCS {{259 0 0-10989 {}}} CYCLES {}}
+set a(0-10989) {NAME ACC1:conc#1119 TYPE CONCATENATE PAR 0-9373 XREFS 59200 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-10986 {}} {258 0 0-10985 {}} {258 0 0-10984 {}} {259 0 0-10988 {}}} SUCCS {{259 0 0-10990 {}}} CYCLES {}}
+set a(0-10990) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#618 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-9373 XREFS 59201 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.7007077234103024 1 0.7007077234103024} PREDS {{258 0 0-10983 {}} {259 0 0-10989 {}}} SUCCS {{258 0 0-11003 {}}} CYCLES {}}
+set a(0-10991) {NAME ACC1:slc(ACC1:acc#224.psp)#54 TYPE READSLICE PAR 0-9373 XREFS 59202 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9993 {}}} SUCCS {{258 0 0-10996 {}}} CYCLES {}}
+set a(0-10992) {NAME ACC1:slc(acc#20.psp#1)#38 TYPE READSLICE PAR 0-9373 XREFS 59203 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-10996 {}}} CYCLES {}}
+set a(0-10993) {NAME ACC1:slc(ACC1:acc#226.psp)#46 TYPE READSLICE PAR 0-9373 XREFS 59204 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9767 {}}} SUCCS {{258 0 0-10996 {}}} CYCLES {}}
+set a(0-10994) {NAME ACC1-3:slc(acc#10.psp)#60 TYPE READSLICE PAR 0-9373 XREFS 59205 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-10995 {}}} CYCLES {}}
+set a(0-10995) {NAME ACC1-3:exs#39 TYPE SIGNEXTEND PAR 0-9373 XREFS 59206 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-10994 {}}} SUCCS {{259 0 0-10996 {}}} CYCLES {}}
+set a(0-10996) {NAME ACC1:conc#1120 TYPE CONCATENATE PAR 0-9373 XREFS 59207 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-10993 {}} {258 0 0-10992 {}} {258 0 0-10991 {}} {259 0 0-10995 {}}} SUCCS {{258 0 0-11002 {}}} CYCLES {}}
+set a(0-10997) {NAME ACC1:slc(ACC1:acc#228.psp)#56 TYPE READSLICE PAR 0-9373 XREFS 59208 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9695 {}}} SUCCS {{258 0 0-11001 {}}} CYCLES {}}
+set a(0-10998) {NAME ACC1:slc(ACC1:acc#227.psp)#63 TYPE READSLICE PAR 0-9373 XREFS 59209 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.63719575} PREDS {{258 0 0-9918 {}}} SUCCS {{258 0 0-11001 {}}} CYCLES {}}
+set a(0-10999) {NAME ACC1-3:slc(acc#10.psp)#59 TYPE READSLICE PAR 0-9373 XREFS 59210 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-11000 {}}} CYCLES {}}
+set a(0-11000) {NAME ACC1-3:exs#43 TYPE SIGNEXTEND PAR 0-9373 XREFS 59211 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-10999 {}}} SUCCS {{259 0 0-11001 {}}} CYCLES {}}
+set a(0-11001) {NAME ACC1:conc#1121 TYPE CONCATENATE PAR 0-9373 XREFS 59212 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-10998 {}} {258 0 0-10997 {}} {259 0 0-11000 {}}} SUCCS {{259 0 0-11002 {}}} CYCLES {}}
+set a(0-11002) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#617 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-9373 XREFS 59213 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.7007077234103024 1 0.7007077234103024} PREDS {{258 0 0-10996 {}} {259 0 0-11001 {}}} SUCCS {{259 0 0-11003 {}}} CYCLES {}}
+set a(0-11003) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#634 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-9373 XREFS 59214 LOC {1 0.210066975 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-10990 {}} {259 0 0-11002 {}}} SUCCS {{259 0 0-11004 {}}} CYCLES {}}
+set a(0-11004) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,9) AREA_SCORE 9.26 QUANTITY 5 NAME ACC1:acc#644 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-9373 XREFS 59215 LOC {1 0.7224392749999999 1 0.7688971499999999 1 0.7688971499999999 1 0.8415918527684256 1 0.8415918527684256} PREDS {{258 0 0-10978 {}} {259 0 0-11003 {}}} SUCCS {{258 0 0-11040 {}}} CYCLES {}}
+set a(0-11005) {NAME ACC1:slc(ACC1:acc#226.psp)#47 TYPE READSLICE PAR 0-9373 XREFS 59216 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9767 {}}} SUCCS {{258 0 0-11009 {}}} CYCLES {}}
+set a(0-11006) {NAME ACC1:slc(ACC1:acc#227.psp)#64 TYPE READSLICE PAR 0-9373 XREFS 59217 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.63719575} PREDS {{258 0 0-9918 {}}} SUCCS {{258 0 0-11009 {}}} CYCLES {}}
+set a(0-11007) {NAME ACC1-3:slc(acc#10.psp)#58 TYPE READSLICE PAR 0-9373 XREFS 59218 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-11008 {}}} CYCLES {}}
+set a(0-11008) {NAME ACC1-3:exs#44 TYPE SIGNEXTEND PAR 0-9373 XREFS 59219 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-11007 {}}} SUCCS {{259 0 0-11009 {}}} CYCLES {}}
+set a(0-11009) {NAME ACC1:conc#1122 TYPE CONCATENATE PAR 0-9373 XREFS 59220 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-11006 {}} {258 0 0-11005 {}} {259 0 0-11008 {}}} SUCCS {{258 0 0-11015 {}}} CYCLES {}}
+set a(0-11010) {NAME ACC1:slc(ACC1:acc#224.psp#1)#28 TYPE READSLICE PAR 0-9373 XREFS 59221 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.63719575} PREDS {{258 0 0-9471 {}}} SUCCS {{258 0 0-11014 {}}} CYCLES {}}
+set a(0-11011) {NAME ACC1:slc(acc.psp#1)#63 TYPE READSLICE PAR 0-9373 XREFS 59222 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-9839 {}}} SUCCS {{258 0 0-11014 {}}} CYCLES {}}
+set a(0-11012) {NAME ACC1-3:slc(acc#10.psp)#57 TYPE READSLICE PAR 0-9373 XREFS 59223 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-11013 {}}} CYCLES {}}
+set a(0-11013) {NAME ACC1-3:exs#42 TYPE SIGNEXTEND PAR 0-9373 XREFS 59224 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-11012 {}}} SUCCS {{259 0 0-11014 {}}} CYCLES {}}
+set a(0-11014) {NAME ACC1:conc#1123 TYPE CONCATENATE PAR 0-9373 XREFS 59225 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-11011 {}} {258 0 0-11010 {}} {259 0 0-11013 {}}} SUCCS {{259 0 0-11015 {}}} CYCLES {}}
+set a(0-11015) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#616 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-9373 XREFS 59226 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.7007077234103024 1 0.7007077234103024} PREDS {{258 0 0-11009 {}} {259 0 0-11014 {}}} SUCCS {{258 0 0-11027 {}}} CYCLES {}}
+set a(0-11016) {NAME ACC1:slc(ACC1-1:acc#25.psp)#24 TYPE READSLICE PAR 0-9373 XREFS 59227 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.63719575} PREDS {{258 0 0-9616 {}}} SUCCS {{258 0 0-11020 {}}} CYCLES {}}
+set a(0-11017) {NAME ACC1:slc(acc.psp#1)#64 TYPE READSLICE PAR 0-9373 XREFS 59228 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.63719575} PREDS {{258 0 0-9839 {}}} SUCCS {{258 0 0-11020 {}}} CYCLES {}}
+set a(0-11018) {NAME ACC1-3:slc(acc#10.psp)#56 TYPE READSLICE PAR 0-9373 XREFS 59229 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-11019 {}}} CYCLES {}}
+set a(0-11019) {NAME ACC1-3:exs#47 TYPE SIGNEXTEND PAR 0-9373 XREFS 59230 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-11018 {}}} SUCCS {{259 0 0-11020 {}}} CYCLES {}}
+set a(0-11020) {NAME ACC1:conc#1124 TYPE CONCATENATE PAR 0-9373 XREFS 59231 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-11017 {}} {258 0 0-11016 {}} {259 0 0-11019 {}}} SUCCS {{258 0 0-11026 {}}} CYCLES {}}
+set a(0-11021) {NAME ACC1:slc(acc.psp#2)#13 TYPE READSLICE PAR 0-9373 XREFS 59232 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.63719575} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-11025 {}}} CYCLES {}}
+set a(0-11022) {NAME ACC1:slc(ACC1:acc#224.psp)#55 TYPE READSLICE PAR 0-9373 XREFS 59233 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9993 {}}} SUCCS {{258 0 0-11025 {}}} CYCLES {}}
+set a(0-11023) {NAME ACC1-3:slc(acc#10.psp)#55 TYPE READSLICE PAR 0-9373 XREFS 59234 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.63719575} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-11024 {}}} CYCLES {}}
+set a(0-11024) {NAME ACC1-3:exs#45 TYPE SIGNEXTEND PAR 0-9373 XREFS 59235 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{259 0 0-11023 {}}} SUCCS {{259 0 0-11025 {}}} CYCLES {}}
+set a(0-11025) {NAME ACC1:conc#1125 TYPE CONCATENATE PAR 0-9373 XREFS 59236 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.63719575} PREDS {{258 0 0-11022 {}} {258 0 0-11021 {}} {259 0 0-11024 {}}} SUCCS {{259 0 0-11026 {}}} CYCLES {}}
+set a(0-11026) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#615 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-9373 XREFS 59237 LOC {1 0.14655495 1 0.63719575 1 0.63719575 1 0.7007077234103024 1 0.7007077234103024} PREDS {{258 0 0-11020 {}} {259 0 0-11025 {}}} SUCCS {{259 0 0-11027 {}}} CYCLES {}}
+set a(0-11027) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#633 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-9373 XREFS 59238 LOC {1 0.210066975 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-11015 {}} {259 0 0-11026 {}}} SUCCS {{258 0 0-11039 {}}} CYCLES {}}
+set a(0-11028) {NAME ACC1-3:slc(acc#5.psp)#17 TYPE READSLICE PAR 0-9373 XREFS 59239 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.7007077749999999} PREDS {{258 0 0-9918 {}}} SUCCS {{258 0 0-11031 {}}} CYCLES {}}
+set a(0-11029) {NAME ACC1-3:slc(acc.idiv#1)#25 TYPE READSLICE PAR 0-9373 XREFS 59240 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.7007077749999999} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-11030 {}}} CYCLES {}}
+set a(0-11030) {NAME ACC1-3:exs#30 TYPE SIGNEXTEND PAR 0-9373 XREFS 59241 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11029 {}}} SUCCS {{259 0 0-11031 {}}} CYCLES {}}
+set a(0-11031) {NAME ACC1-3:conc#496 TYPE CONCATENATE PAR 0-9373 XREFS 59242 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-11028 {}} {259 0 0-11030 {}}} SUCCS {{259 0 0-11032 {}}} CYCLES {}}
+set a(0-11032) {NAME ACC1-3:exs#1032 TYPE SIGNEXTEND PAR 0-9373 XREFS 59243 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11031 {}}} SUCCS {{258 0 0-11038 {}}} CYCLES {}}
+set a(0-11033) {NAME ACC1-3:slc(acc.psp)#17 TYPE READSLICE PAR 0-9373 XREFS 59244 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7007077749999999} PREDS {{258 0 0-9839 {}}} SUCCS {{258 0 0-11036 {}}} CYCLES {}}
+set a(0-11034) {NAME ACC1-3:slc(acc.idiv)#25 TYPE READSLICE PAR 0-9373 XREFS 59245 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7007077749999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11035 {}}} CYCLES {}}
+set a(0-11035) {NAME ACC1-3:exs#12 TYPE SIGNEXTEND PAR 0-9373 XREFS 59246 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11034 {}}} SUCCS {{259 0 0-11036 {}}} CYCLES {}}
+set a(0-11036) {NAME ACC1-3:conc#482 TYPE CONCATENATE PAR 0-9373 XREFS 59247 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-11033 {}} {259 0 0-11035 {}}} SUCCS {{259 0 0-11037 {}}} CYCLES {}}
+set a(0-11037) {NAME ACC1-3:exs#1029 TYPE SIGNEXTEND PAR 0-9373 XREFS 59248 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11036 {}}} SUCCS {{259 0 0-11038 {}}} CYCLES {}}
+set a(0-11038) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#632 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-9373 XREFS 59249 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-11032 {}} {259 0 0-11037 {}}} SUCCS {{259 0 0-11039 {}}} CYCLES {}}
+set a(0-11039) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,9) AREA_SCORE 9.26 QUANTITY 5 NAME ACC1:acc#643 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-9373 XREFS 59250 LOC {1 0.27825635 1 0.7688971499999999 1 0.7688971499999999 1 0.8415918527684256 1 0.8415918527684256} PREDS {{258 0 0-11027 {}} {259 0 0-11038 {}}} SUCCS {{259 0 0-11040 {}}} CYCLES {}}
+set a(0-11040) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,0,10) AREA_SCORE 10.25 QUANTITY 2 NAME ACC1:acc#649 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-9373 XREFS 59251 LOC {1 0.795134025 1 0.8415919 1 0.8415919 1 0.9186606628916543 1 0.9186606628916543} PREDS {{258 0 0-11004 {}} {259 0 0-11039 {}}} SUCCS {{258 0 0-11088 {}}} CYCLES {}}
+set a(0-11041) {NAME ACC1-3:slc(acc#10.psp)#52 TYPE READSLICE PAR 0-9373 XREFS 59252 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7007077749999999} PREDS {{258 0 0-9993 {}}} SUCCS {{258 0 0-11044 {}}} CYCLES {}}
+set a(0-11042) {NAME ACC1-3:slc(acc#10.psp)#53 TYPE READSLICE PAR 0-9373 XREFS 59253 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7007077749999999} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-11043 {}}} CYCLES {}}
+set a(0-11043) {NAME ACC1-3:exs#48 TYPE SIGNEXTEND PAR 0-9373 XREFS 59254 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11042 {}}} SUCCS {{259 0 0-11044 {}}} CYCLES {}}
+set a(0-11044) {NAME ACC1-3:conc#510 TYPE CONCATENATE PAR 0-9373 XREFS 59255 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-11041 {}} {259 0 0-11043 {}}} SUCCS {{259 0 0-11045 {}}} CYCLES {}}
+set a(0-11045) {NAME ACC1-3:exs#1035 TYPE SIGNEXTEND PAR 0-9373 XREFS 59256 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11044 {}}} SUCCS {{258 0 0-11051 {}}} CYCLES {}}
+set a(0-11046) {NAME ACC1:slc(acc#5.psp#2)#63 TYPE READSLICE PAR 0-9373 XREFS 59257 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7007077749999999} PREDS {{258 0 0-9695 {}}} SUCCS {{258 0 0-11049 {}}} CYCLES {}}
+set a(0-11047) {NAME ACC1:slc(acc#5.psp#2)#64 TYPE READSLICE PAR 0-9373 XREFS 59258 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7007077749999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11048 {}}} CYCLES {}}
+set a(0-11048) {NAME ACC1-2:exs#30 TYPE SIGNEXTEND PAR 0-9373 XREFS 59259 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11047 {}}} SUCCS {{259 0 0-11049 {}}} CYCLES {}}
+set a(0-11049) {NAME ACC1-2:conc#496 TYPE CONCATENATE PAR 0-9373 XREFS 59260 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-11046 {}} {259 0 0-11048 {}}} SUCCS {{259 0 0-11050 {}}} CYCLES {}}
+set a(0-11050) {NAME ACC1-2:exs#1032 TYPE SIGNEXTEND PAR 0-9373 XREFS 59261 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11049 {}}} SUCCS {{259 0 0-11051 {}}} CYCLES {}}
+set a(0-11051) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#631 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-9373 XREFS 59262 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-11045 {}} {259 0 0-11050 {}}} SUCCS {{258 0 0-11063 {}}} CYCLES {}}
+set a(0-11052) {NAME ACC1-3:slc(acc#25.psp)#25 TYPE READSLICE PAR 0-9373 XREFS 59263 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7007077749999999} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-11055 {}}} CYCLES {}}
+set a(0-11053) {NAME ACC1-3:slc(acc.idiv#5)#31 TYPE READSLICE PAR 0-9373 XREFS 59264 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7007077749999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11054 {}}} CYCLES {}}
+set a(0-11054) {NAME ACC1-3:exs#105 TYPE SIGNEXTEND PAR 0-9373 XREFS 59265 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11053 {}}} SUCCS {{259 0 0-11055 {}}} CYCLES {}}
+set a(0-11055) {NAME ACC1-3:conc#552 TYPE CONCATENATE PAR 0-9373 XREFS 59266 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-11052 {}} {259 0 0-11054 {}}} SUCCS {{259 0 0-11056 {}}} CYCLES {}}
+set a(0-11056) {NAME ACC1-3:exs#1042 TYPE SIGNEXTEND PAR 0-9373 XREFS 59267 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11055 {}}} SUCCS {{258 0 0-11062 {}}} CYCLES {}}
+set a(0-11057) {NAME ACC1-3:slc(acc#20.psp)#17 TYPE READSLICE PAR 0-9373 XREFS 59268 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7007077749999999} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-11060 {}}} CYCLES {}}
+set a(0-11058) {NAME ACC1-3:slc(acc.idiv#4)#25 TYPE READSLICE PAR 0-9373 XREFS 59269 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7007077749999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11059 {}}} CYCLES {}}
+set a(0-11059) {NAME ACC1-3:exs#84 TYPE SIGNEXTEND PAR 0-9373 XREFS 59270 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11058 {}}} SUCCS {{259 0 0-11060 {}}} CYCLES {}}
+set a(0-11060) {NAME ACC1-3:conc#538 TYPE CONCATENATE PAR 0-9373 XREFS 59271 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-11057 {}} {259 0 0-11059 {}}} SUCCS {{259 0 0-11061 {}}} CYCLES {}}
+set a(0-11061) {NAME ACC1-3:exs#1040 TYPE SIGNEXTEND PAR 0-9373 XREFS 59272 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11060 {}}} SUCCS {{259 0 0-11062 {}}} CYCLES {}}
+set a(0-11062) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#630 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-9373 XREFS 59273 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-11056 {}} {259 0 0-11061 {}}} SUCCS {{259 0 0-11063 {}}} CYCLES {}}
+set a(0-11063) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,9) AREA_SCORE 9.26 QUANTITY 5 NAME ACC1:acc#642 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-9373 XREFS 59274 LOC {1 0.21474432499999999 1 0.7688971499999999 1 0.7688971499999999 1 0.8415918527684256 1 0.8415918527684256} PREDS {{258 0 0-11051 {}} {259 0 0-11062 {}}} SUCCS {{258 0 0-11087 {}}} CYCLES {}}
+set a(0-11064) {NAME ACC1:slc(acc#25.psp#2)#64 TYPE READSLICE PAR 0-9373 XREFS 59275 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7007077749999999} PREDS {{258 0 0-9767 {}}} SUCCS {{258 0 0-11067 {}}} CYCLES {}}
+set a(0-11065) {NAME ACC1:slc(acc#25.psp#2)#65 TYPE READSLICE PAR 0-9373 XREFS 59276 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.7007077749999999} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11066 {}}} CYCLES {}}
+set a(0-11066) {NAME ACC1-2:exs#105 TYPE SIGNEXTEND PAR 0-9373 XREFS 59277 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11065 {}}} SUCCS {{259 0 0-11067 {}}} CYCLES {}}
+set a(0-11067) {NAME ACC1-2:conc#552 TYPE CONCATENATE PAR 0-9373 XREFS 59278 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-11064 {}} {259 0 0-11066 {}}} SUCCS {{259 0 0-11068 {}}} CYCLES {}}
+set a(0-11068) {NAME ACC1-2:exs#1042 TYPE SIGNEXTEND PAR 0-9373 XREFS 59279 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11067 {}}} SUCCS {{258 0 0-11074 {}}} CYCLES {}}
+set a(0-11069) {NAME ACC1-1:slc(acc#10.psp)#52 TYPE READSLICE PAR 0-9373 XREFS 59280 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.7007077749999999} PREDS {{258 0 0-9471 {}}} SUCCS {{258 0 0-11072 {}}} CYCLES {}}
+set a(0-11070) {NAME ACC1-1:slc(acc#10.psp)#53 TYPE READSLICE PAR 0-9373 XREFS 59281 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.7007077749999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11071 {}}} CYCLES {}}
+set a(0-11071) {NAME ACC1-1:exs#48 TYPE SIGNEXTEND PAR 0-9373 XREFS 59282 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11070 {}}} SUCCS {{259 0 0-11072 {}}} CYCLES {}}
+set a(0-11072) {NAME ACC1-1:conc#510 TYPE CONCATENATE PAR 0-9373 XREFS 59283 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-11069 {}} {259 0 0-11071 {}}} SUCCS {{259 0 0-11073 {}}} CYCLES {}}
+set a(0-11073) {NAME ACC1-1:exs#1035 TYPE SIGNEXTEND PAR 0-9373 XREFS 59284 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11072 {}}} SUCCS {{259 0 0-11074 {}}} CYCLES {}}
+set a(0-11074) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#629 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-9373 XREFS 59285 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-11068 {}} {259 0 0-11073 {}}} SUCCS {{258 0 0-11086 {}}} CYCLES {}}
+set a(0-11075) {NAME ACC1-1:slc(acc#25.psp)#25 TYPE READSLICE PAR 0-9373 XREFS 59286 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.7007077749999999} PREDS {{258 0 0-9616 {}}} SUCCS {{258 0 0-11078 {}}} CYCLES {}}
+set a(0-11076) {NAME ACC1-1:slc(acc.idiv#5)#31 TYPE READSLICE PAR 0-9373 XREFS 59287 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.7007077749999999} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-11077 {}}} CYCLES {}}
+set a(0-11077) {NAME ACC1-1:exs#105 TYPE SIGNEXTEND PAR 0-9373 XREFS 59288 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11076 {}}} SUCCS {{259 0 0-11078 {}}} CYCLES {}}
+set a(0-11078) {NAME ACC1-1:conc#552 TYPE CONCATENATE PAR 0-9373 XREFS 59289 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-11075 {}} {259 0 0-11077 {}}} SUCCS {{259 0 0-11079 {}}} CYCLES {}}
+set a(0-11079) {NAME ACC1-1:exs#1042 TYPE SIGNEXTEND PAR 0-9373 XREFS 59290 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11078 {}}} SUCCS {{258 0 0-11085 {}}} CYCLES {}}
+set a(0-11080) {NAME ACC1-1:slc(acc#5.psp)#17 TYPE READSLICE PAR 0-9373 XREFS 59291 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7007077749999999} PREDS {{258 0 0-9386 {}}} SUCCS {{258 0 0-11083 {}}} CYCLES {}}
+set a(0-11081) {NAME ACC1-1:slc(acc.idiv#1)#25 TYPE READSLICE PAR 0-9373 XREFS 59292 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7007077749999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-11082 {}}} CYCLES {}}
+set a(0-11082) {NAME ACC1-1:exs#30 TYPE SIGNEXTEND PAR 0-9373 XREFS 59293 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11081 {}}} SUCCS {{259 0 0-11083 {}}} CYCLES {}}
+set a(0-11083) {NAME ACC1-1:conc#496 TYPE CONCATENATE PAR 0-9373 XREFS 59294 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{258 0 0-11080 {}} {259 0 0-11082 {}}} SUCCS {{259 0 0-11084 {}}} CYCLES {}}
+set a(0-11084) {NAME ACC1-1:exs#1032 TYPE SIGNEXTEND PAR 0-9373 XREFS 59295 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7007077749999999} PREDS {{259 0 0-11083 {}}} SUCCS {{259 0 0-11085 {}}} CYCLES {}}
+set a(0-11085) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#628 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-9373 XREFS 59296 LOC {1 0.14655495 1 0.7007077749999999 1 0.7007077749999999 1 0.7688970879329678 1 0.7688970879329678} PREDS {{258 0 0-11079 {}} {259 0 0-11084 {}}} SUCCS {{259 0 0-11086 {}}} CYCLES {}}
+set a(0-11086) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,9) AREA_SCORE 9.26 QUANTITY 5 NAME ACC1:acc#641 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-9373 XREFS 59297 LOC {1 0.21474432499999999 1 0.7688971499999999 1 0.7688971499999999 1 0.8415918527684256 1 0.8415918527684256} PREDS {{258 0 0-11074 {}} {259 0 0-11085 {}}} SUCCS {{259 0 0-11087 {}}} CYCLES {}}
+set a(0-11087) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,0,10) AREA_SCORE 10.25 QUANTITY 2 NAME ACC1:acc#648 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-9373 XREFS 59298 LOC {1 0.287439075 1 0.8415919 1 0.8415919 1 0.9186606628916543 1 0.9186606628916543} PREDS {{258 0 0-11063 {}} {259 0 0-11086 {}}} SUCCS {{259 0 0-11088 {}}} CYCLES {}}
+set a(0-11088) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,11) AREA_SCORE 11.24 QUANTITY 3 NAME ACC1:acc#652 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-9373 XREFS 59299 LOC {1 0.87220285 1 0.918660725 1 0.918660725 1 0.9999999533364112 1 0.9999999533364112} PREDS {{258 0 0-11040 {}} {259 0 0-11087 {}}} SUCCS {{259 0 0-11089 {}}} CYCLES {}}
+set a(0-11089) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 4 NAME ACC1:acc#656 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-9373 XREFS 59300 LOC {2 0.0 2 0.060871249999999995 2 0.060871249999999995 2 0.14035945349977766 2 0.14035945349977766} PREDS {{258 0 0-10612 {}} {259 0 0-11088 {}}} SUCCS {{258 0 0-11636 {}}} CYCLES {}}
+set a(0-11090) {NAME slc(acc#20.psp#1)#87 TYPE READSLICE PAR 0-9373 XREFS 59301 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.003959675} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-11096 {}}} CYCLES {}}
+set a(0-11091) {NAME slc(acc#20.psp#1)#88 TYPE READSLICE PAR 0-9373 XREFS 59302 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.003959675} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-11096 {}}} CYCLES {}}
+set a(0-11092) {NAME slc(acc#20.psp#1)#89 TYPE READSLICE PAR 0-9373 XREFS 59303 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.003959675} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-11096 {}}} CYCLES {}}
+set a(0-11093) {NAME slc(acc#20.psp#1)#90 TYPE READSLICE PAR 0-9373 XREFS 59304 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.003959675} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-11096 {}}} CYCLES {}}
+set a(0-11094) {NAME slc(acc#20.psp#1)#79 TYPE READSLICE PAR 0-9373 XREFS 59305 LOC {1 0.14655495 1 0.193012825 1 0.193012825 2 0.003959675} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-11096 {}}} CYCLES {}}
+set a(0-11095) {NAME ACC1:slc(ACC1:acc#228.psp)#50 TYPE READSLICE PAR 0-9373 XREFS 59306 LOC {1 0.14655495 1 0.2022795 1 0.2022795 2 0.003959675} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11096 {}}} CYCLES {}}
+set a(0-11096) {NAME ACC1:conc#1088 TYPE CONCATENATE PAR 0-9373 XREFS 59307 LOC {1 0.14655495 1 0.863600175 1 0.863600175 2 0.003959675} PREDS {{258 0 0-11094 {}} {258 0 0-11093 {}} {258 0 0-11092 {}} {258 0 0-11091 {}} {258 0 0-11090 {}} {259 0 0-11095 {}}} SUCCS {{258 0 0-11478 {}}} CYCLES {}}
+set a(0-11097) {NAME ACC1:slc(ACC1-1:acc#25.psp)#15 TYPE READSLICE PAR 0-9373 XREFS 59308 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.895231} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-11098 {}}} CYCLES {}}
+set a(0-11098) {NAME ACC1:conc#1307 TYPE CONCATENATE PAR 0-9373 XREFS 59309 LOC {1 0.14655495 1 0.758831175 1 0.758831175 1 0.895231} PREDS {{259 0 0-11097 {}}} SUCCS {{258 0 0-11194 {}}} CYCLES {}}
+set a(0-11099) {NAME ACC1-3:slc(acc.idiv#1)#13 TYPE READSLICE PAR 0-9373 XREFS 59310 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6314329249999999} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-11100 {}}} CYCLES {}}
+set a(0-11100) {NAME ACC1-3:exs#24 TYPE SIGNEXTEND PAR 0-9373 XREFS 59311 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11099 {}}} SUCCS {{258 0 0-11103 {}}} CYCLES {}}
+set a(0-11101) {NAME ACC1-3:slc(acc.idiv#1)#23 TYPE READSLICE PAR 0-9373 XREFS 59312 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6314329249999999} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-11102 {}}} CYCLES {}}
+set a(0-11102) {NAME ACC1-3:exs#29 TYPE SIGNEXTEND PAR 0-9373 XREFS 59313 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11101 {}}} SUCCS {{259 0 0-11103 {}}} CYCLES {}}
+set a(0-11103) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#509 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59314 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11100 {}} {259 0 0-11102 {}}} SUCCS {{258 0 0-11109 {}}} CYCLES {}}
+set a(0-11104) {NAME ACC1-3:slc(acc.idiv#1)#19 TYPE READSLICE PAR 0-9373 XREFS 59315 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6314329249999999} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-11105 {}}} CYCLES {}}
+set a(0-11105) {NAME ACC1-3:exs#27 TYPE SIGNEXTEND PAR 0-9373 XREFS 59316 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11104 {}}} SUCCS {{258 0 0-11108 {}}} CYCLES {}}
+set a(0-11106) {NAME ACC1-3:slc(acc.idiv#1)#21 TYPE READSLICE PAR 0-9373 XREFS 59317 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6314329249999999} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-11107 {}}} CYCLES {}}
+set a(0-11107) {NAME ACC1-3:exs#28 TYPE SIGNEXTEND PAR 0-9373 XREFS 59318 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11106 {}}} SUCCS {{259 0 0-11108 {}}} CYCLES {}}
+set a(0-11108) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#508 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59319 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11105 {}} {259 0 0-11107 {}}} SUCCS {{259 0 0-11109 {}}} CYCLES {}}
+set a(0-11109) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#564 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59320 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-11103 {}} {259 0 0-11108 {}}} SUCCS {{258 0 0-11121 {}}} CYCLES {}}
+set a(0-11110) {NAME ACC1-3:slc(acc.idiv#1)#31 TYPE READSLICE PAR 0-9373 XREFS 59321 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6314329249999999} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-11111 {}}} CYCLES {}}
+set a(0-11111) {NAME ACC1-3:exs#33 TYPE SIGNEXTEND PAR 0-9373 XREFS 59322 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11110 {}}} SUCCS {{258 0 0-11114 {}}} CYCLES {}}
+set a(0-11112) {NAME ACC1-3:slc(acc#5.psp)#65 TYPE READSLICE PAR 0-9373 XREFS 59323 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6314329249999999} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-11113 {}}} CYCLES {}}
+set a(0-11113) {NAME ACC1-3:exs#1031 TYPE SIGNEXTEND PAR 0-9373 XREFS 59324 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11112 {}}} SUCCS {{259 0 0-11114 {}}} CYCLES {}}
+set a(0-11114) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#507 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59325 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11111 {}} {259 0 0-11113 {}}} SUCCS {{258 0 0-11120 {}}} CYCLES {}}
+set a(0-11115) {NAME ACC1-3:slc(acc.idiv#5)#21 TYPE READSLICE PAR 0-9373 XREFS 59326 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11116 {}}} CYCLES {}}
+set a(0-11116) {NAME ACC1-3:exs#100 TYPE SIGNEXTEND PAR 0-9373 XREFS 59327 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11115 {}}} SUCCS {{258 0 0-11119 {}}} CYCLES {}}
+set a(0-11117) {NAME ACC1-3:slc(acc.idiv#5)#13 TYPE READSLICE PAR 0-9373 XREFS 59328 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11118 {}}} CYCLES {}}
+set a(0-11118) {NAME ACC1-3:exs#96 TYPE SIGNEXTEND PAR 0-9373 XREFS 59329 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11117 {}}} SUCCS {{259 0 0-11119 {}}} CYCLES {}}
+set a(0-11119) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#506 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59330 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11116 {}} {259 0 0-11118 {}}} SUCCS {{259 0 0-11120 {}}} CYCLES {}}
+set a(0-11120) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#563 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59331 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-11114 {}} {259 0 0-11119 {}}} SUCCS {{259 0 0-11121 {}}} CYCLES {}}
+set a(0-11121) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#597 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59332 LOC {1 0.23489417499999998 1 0.583372325 1 0.583372325 1 0.6367193451789506 1 0.7731191701789504} PREDS {{258 0 0-11109 {}} {259 0 0-11120 {}}} SUCCS {{258 0 0-11145 {}}} CYCLES {}}
+set a(0-11122) {NAME ACC1-3:slc(acc.idiv#5)#15 TYPE READSLICE PAR 0-9373 XREFS 59333 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11123 {}}} CYCLES {}}
+set a(0-11123) {NAME ACC1-3:exs#97 TYPE SIGNEXTEND PAR 0-9373 XREFS 59334 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11122 {}}} SUCCS {{258 0 0-11126 {}}} CYCLES {}}
+set a(0-11124) {NAME ACC1-3:slc(acc.idiv#5)#17 TYPE READSLICE PAR 0-9373 XREFS 59335 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11125 {}}} CYCLES {}}
+set a(0-11125) {NAME ACC1-3:exs#98 TYPE SIGNEXTEND PAR 0-9373 XREFS 59336 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11124 {}}} SUCCS {{259 0 0-11126 {}}} CYCLES {}}
+set a(0-11126) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#505 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59337 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11123 {}} {259 0 0-11125 {}}} SUCCS {{258 0 0-11132 {}}} CYCLES {}}
+set a(0-11127) {NAME ACC1-3:slc(acc.idiv#5)#25 TYPE READSLICE PAR 0-9373 XREFS 59338 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11128 {}}} CYCLES {}}
+set a(0-11128) {NAME ACC1-3:exs#102 TYPE SIGNEXTEND PAR 0-9373 XREFS 59339 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11127 {}}} SUCCS {{258 0 0-11131 {}}} CYCLES {}}
+set a(0-11129) {NAME ACC1-3:slc(acc#25.psp)#46 TYPE READSLICE PAR 0-9373 XREFS 59340 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11130 {}}} CYCLES {}}
+set a(0-11130) {NAME ACC1-3:exs#353 TYPE SIGNEXTEND PAR 0-9373 XREFS 59341 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11129 {}}} SUCCS {{259 0 0-11131 {}}} CYCLES {}}
+set a(0-11131) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#504 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59342 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11128 {}} {259 0 0-11130 {}}} SUCCS {{259 0 0-11132 {}}} CYCLES {}}
+set a(0-11132) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#562 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59343 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-11126 {}} {259 0 0-11131 {}}} SUCCS {{258 0 0-11144 {}}} CYCLES {}}
+set a(0-11133) {NAME ACC1-3:slc(acc.idiv#5)#23 TYPE READSLICE PAR 0-9373 XREFS 59344 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11134 {}}} CYCLES {}}
+set a(0-11134) {NAME ACC1-3:exs#101 TYPE SIGNEXTEND PAR 0-9373 XREFS 59345 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11133 {}}} SUCCS {{258 0 0-11137 {}}} CYCLES {}}
+set a(0-11135) {NAME ACC1-3:slc(acc.idiv#5)#33 TYPE READSLICE PAR 0-9373 XREFS 59346 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11136 {}}} CYCLES {}}
+set a(0-11136) {NAME ACC1-3:exs#106 TYPE SIGNEXTEND PAR 0-9373 XREFS 59347 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11135 {}}} SUCCS {{259 0 0-11137 {}}} CYCLES {}}
+set a(0-11137) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#503 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59348 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11134 {}} {259 0 0-11136 {}}} SUCCS {{258 0 0-11143 {}}} CYCLES {}}
+set a(0-11138) {NAME ACC1-3:slc(acc#25.psp)#56 TYPE READSLICE PAR 0-9373 XREFS 59349 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11139 {}}} CYCLES {}}
+set a(0-11139) {NAME ACC1-3:exs#963 TYPE SIGNEXTEND PAR 0-9373 XREFS 59350 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11138 {}}} SUCCS {{258 0 0-11142 {}}} CYCLES {}}
+set a(0-11140) {NAME ACC1-3:slc(acc.idiv#5)#27 TYPE READSLICE PAR 0-9373 XREFS 59351 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11141 {}}} CYCLES {}}
+set a(0-11141) {NAME ACC1-3:exs#103 TYPE SIGNEXTEND PAR 0-9373 XREFS 59352 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11140 {}}} SUCCS {{259 0 0-11142 {}}} CYCLES {}}
+set a(0-11142) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#502 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59353 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11139 {}} {259 0 0-11141 {}}} SUCCS {{259 0 0-11143 {}}} CYCLES {}}
+set a(0-11143) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#561 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59354 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-11137 {}} {259 0 0-11142 {}}} SUCCS {{259 0 0-11144 {}}} CYCLES {}}
+set a(0-11144) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#596 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59355 LOC {1 0.23489417499999998 1 0.583372325 1 0.583372325 1 0.6367193451789506 1 0.7731191701789504} PREDS {{258 0 0-11132 {}} {259 0 0-11143 {}}} SUCCS {{259 0 0-11145 {}}} CYCLES {}}
+set a(0-11145) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#613 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-9373 XREFS 59356 LOC {1 0.28824125 1 0.6367193999999999 1 0.6367193999999999 1 0.695319109496936 1 0.831718934496936} PREDS {{258 0 0-11121 {}} {259 0 0-11144 {}}} SUCCS {{258 0 0-11193 {}}} CYCLES {}}
+set a(0-11146) {NAME ACC1-3:slc(acc.idiv#5)#29 TYPE READSLICE PAR 0-9373 XREFS 59357 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11147 {}}} CYCLES {}}
+set a(0-11147) {NAME ACC1-3:exs#104 TYPE SIGNEXTEND PAR 0-9373 XREFS 59358 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11146 {}}} SUCCS {{258 0 0-11150 {}}} CYCLES {}}
+set a(0-11148) {NAME ACC1-3:slc(acc.idiv#4)#33 TYPE READSLICE PAR 0-9373 XREFS 59359 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11149 {}}} CYCLES {}}
+set a(0-11149) {NAME ACC1-3:exs#88 TYPE SIGNEXTEND PAR 0-9373 XREFS 59360 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11148 {}}} SUCCS {{259 0 0-11150 {}}} CYCLES {}}
+set a(0-11150) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#501 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59361 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11147 {}} {259 0 0-11149 {}}} SUCCS {{258 0 0-11156 {}}} CYCLES {}}
+set a(0-11151) {NAME ACC1-3:slc(acc.idiv#4)#35 TYPE READSLICE PAR 0-9373 XREFS 59362 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11152 {}}} CYCLES {}}
+set a(0-11152) {NAME ACC1-3:exs#89 TYPE SIGNEXTEND PAR 0-9373 XREFS 59363 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11151 {}}} SUCCS {{258 0 0-11155 {}}} CYCLES {}}
+set a(0-11153) {NAME ACC1-3:slc(acc.idiv#4)#9 TYPE READSLICE PAR 0-9373 XREFS 59364 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11154 {}}} CYCLES {}}
+set a(0-11154) {NAME ACC1-3:exs#76 TYPE SIGNEXTEND PAR 0-9373 XREFS 59365 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11153 {}}} SUCCS {{259 0 0-11155 {}}} CYCLES {}}
+set a(0-11155) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#500 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59366 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11152 {}} {259 0 0-11154 {}}} SUCCS {{259 0 0-11156 {}}} CYCLES {}}
+set a(0-11156) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#560 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59367 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-11150 {}} {259 0 0-11155 {}}} SUCCS {{258 0 0-11168 {}}} CYCLES {}}
+set a(0-11157) {NAME ACC1-3:slc(acc.idiv#4)#11 TYPE READSLICE PAR 0-9373 XREFS 59368 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11158 {}}} CYCLES {}}
+set a(0-11158) {NAME ACC1-3:exs#77 TYPE SIGNEXTEND PAR 0-9373 XREFS 59369 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11157 {}}} SUCCS {{258 0 0-11161 {}}} CYCLES {}}
+set a(0-11159) {NAME ACC1-3:slc(acc.idiv#4)#1 TYPE READSLICE PAR 0-9373 XREFS 59370 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11160 {}}} CYCLES {}}
+set a(0-11160) {NAME ACC1-3:exs#72 TYPE SIGNEXTEND PAR 0-9373 XREFS 59371 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11159 {}}} SUCCS {{259 0 0-11161 {}}} CYCLES {}}
+set a(0-11161) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#499 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59372 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11158 {}} {259 0 0-11160 {}}} SUCCS {{258 0 0-11167 {}}} CYCLES {}}
+set a(0-11162) {NAME ACC1-3:slc(acc.idiv#4)#3 TYPE READSLICE PAR 0-9373 XREFS 59373 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11163 {}}} CYCLES {}}
+set a(0-11163) {NAME ACC1-3:exs#73 TYPE SIGNEXTEND PAR 0-9373 XREFS 59374 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11162 {}}} SUCCS {{258 0 0-11166 {}}} CYCLES {}}
+set a(0-11164) {NAME ACC1-3:slc(acc.idiv#4)#5 TYPE READSLICE PAR 0-9373 XREFS 59375 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11165 {}}} CYCLES {}}
+set a(0-11165) {NAME ACC1-3:exs#74 TYPE SIGNEXTEND PAR 0-9373 XREFS 59376 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11164 {}}} SUCCS {{259 0 0-11166 {}}} CYCLES {}}
+set a(0-11166) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#498 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59377 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11163 {}} {259 0 0-11165 {}}} SUCCS {{259 0 0-11167 {}}} CYCLES {}}
+set a(0-11167) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#559 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59378 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-11161 {}} {259 0 0-11166 {}}} SUCCS {{259 0 0-11168 {}}} CYCLES {}}
+set a(0-11168) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#595 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59379 LOC {1 0.23489417499999998 1 0.583372325 1 0.583372325 1 0.6367193451789506 1 0.7731191701789504} PREDS {{258 0 0-11156 {}} {259 0 0-11167 {}}} SUCCS {{258 0 0-11192 {}}} CYCLES {}}
+set a(0-11169) {NAME ACC1-3:slc(acc.idiv#4)#7 TYPE READSLICE PAR 0-9373 XREFS 59380 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11170 {}}} CYCLES {}}
+set a(0-11170) {NAME ACC1-3:exs#75 TYPE SIGNEXTEND PAR 0-9373 XREFS 59381 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11169 {}}} SUCCS {{258 0 0-11173 {}}} CYCLES {}}
+set a(0-11171) {NAME ACC1-3:slc(acc.idiv#4)#15 TYPE READSLICE PAR 0-9373 XREFS 59382 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11172 {}}} CYCLES {}}
+set a(0-11172) {NAME ACC1-3:exs#79 TYPE SIGNEXTEND PAR 0-9373 XREFS 59383 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11171 {}}} SUCCS {{259 0 0-11173 {}}} CYCLES {}}
+set a(0-11173) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#497 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59384 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11170 {}} {259 0 0-11172 {}}} SUCCS {{258 0 0-11179 {}}} CYCLES {}}
+set a(0-11174) {NAME ACC1-3:slc(acc.idiv#4)#17 TYPE READSLICE PAR 0-9373 XREFS 59385 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11175 {}}} CYCLES {}}
+set a(0-11175) {NAME ACC1-3:exs#80 TYPE SIGNEXTEND PAR 0-9373 XREFS 59386 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11174 {}}} SUCCS {{258 0 0-11178 {}}} CYCLES {}}
+set a(0-11176) {NAME ACC1-3:slc(acc.idiv#4)#13 TYPE READSLICE PAR 0-9373 XREFS 59387 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11177 {}}} CYCLES {}}
+set a(0-11177) {NAME ACC1-3:exs#78 TYPE SIGNEXTEND PAR 0-9373 XREFS 59388 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11176 {}}} SUCCS {{259 0 0-11178 {}}} CYCLES {}}
+set a(0-11178) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#496 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59389 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11175 {}} {259 0 0-11177 {}}} SUCCS {{259 0 0-11179 {}}} CYCLES {}}
+set a(0-11179) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#558 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59390 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-11173 {}} {259 0 0-11178 {}}} SUCCS {{258 0 0-11191 {}}} CYCLES {}}
+set a(0-11180) {NAME ACC1-3:slc(acc.idiv#4)#23 TYPE READSLICE PAR 0-9373 XREFS 59391 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11181 {}}} CYCLES {}}
+set a(0-11181) {NAME ACC1-3:exs#83 TYPE SIGNEXTEND PAR 0-9373 XREFS 59392 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11180 {}}} SUCCS {{258 0 0-11184 {}}} CYCLES {}}
+set a(0-11182) {NAME ACC1-3:slc(acc.idiv#4)#19 TYPE READSLICE PAR 0-9373 XREFS 59393 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11183 {}}} CYCLES {}}
+set a(0-11183) {NAME ACC1-3:exs#81 TYPE SIGNEXTEND PAR 0-9373 XREFS 59394 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11182 {}}} SUCCS {{259 0 0-11184 {}}} CYCLES {}}
+set a(0-11184) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#495 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59395 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11181 {}} {259 0 0-11183 {}}} SUCCS {{258 0 0-11190 {}}} CYCLES {}}
+set a(0-11185) {NAME ACC1-3:slc(acc.idiv#4)#21 TYPE READSLICE PAR 0-9373 XREFS 59396 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11186 {}}} CYCLES {}}
+set a(0-11186) {NAME ACC1-3:exs#82 TYPE SIGNEXTEND PAR 0-9373 XREFS 59397 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11185 {}}} SUCCS {{258 0 0-11189 {}}} CYCLES {}}
+set a(0-11187) {NAME ACC1-3:slc(acc.idiv#4)#31 TYPE READSLICE PAR 0-9373 XREFS 59398 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6314329249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11188 {}}} CYCLES {}}
+set a(0-11188) {NAME ACC1-3:exs#87 TYPE SIGNEXTEND PAR 0-9373 XREFS 59399 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.6314329249999999} PREDS {{259 0 0-11187 {}}} SUCCS {{259 0 0-11189 {}}} CYCLES {}}
+set a(0-11189) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#494 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59400 LOC {1 0.14655495 1 0.4950331 1 0.4950331 1 0.5358161100894753 1 0.6722159350894752} PREDS {{258 0 0-11186 {}} {259 0 0-11188 {}}} SUCCS {{259 0 0-11190 {}}} CYCLES {}}
+set a(0-11190) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#557 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59401 LOC {1 0.187338 1 0.5358161499999999 1 0.5358161499999999 1 0.5833722770708271 1 0.7197721020708271} PREDS {{258 0 0-11184 {}} {259 0 0-11189 {}}} SUCCS {{259 0 0-11191 {}}} CYCLES {}}
+set a(0-11191) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#594 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59402 LOC {1 0.23489417499999998 1 0.583372325 1 0.583372325 1 0.6367193451789506 1 0.7731191701789504} PREDS {{258 0 0-11179 {}} {259 0 0-11190 {}}} SUCCS {{259 0 0-11192 {}}} CYCLES {}}
+set a(0-11192) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#612 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-9373 XREFS 59403 LOC {1 0.28824125 1 0.6367193999999999 1 0.6367193999999999 1 0.695319109496936 1 0.831718934496936} PREDS {{258 0 0-11168 {}} {259 0 0-11191 {}}} SUCCS {{259 0 0-11193 {}}} CYCLES {}}
+set a(0-11193) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#626 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-9373 XREFS 59404 LOC {1 0.346841 1 0.69531915 1 0.69531915 1 0.7588311234103025 1 0.8952309484103024} PREDS {{258 0 0-11145 {}} {259 0 0-11192 {}}} SUCCS {{259 0 0-11194 {}}} CYCLES {}}
+set a(0-11194) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#638 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-9373 XREFS 59405 LOC {1 0.410353025 1 0.758831175 1 0.758831175 1 0.8112156277684257 1 0.9476154527684257} PREDS {{258 0 0-11098 {}} {259 0 0-11193 {}}} SUCCS {{258 0 0-11477 {}}} CYCLES {}}
+set a(0-11195) {NAME ACC1-3:slc(acc#20.psp)#65 TYPE READSLICE PAR 0-9373 XREFS 59406 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11196 {}}} CYCLES {}}
+set a(0-11196) {NAME ACC1-3:exs#1039 TYPE SIGNEXTEND PAR 0-9373 XREFS 59407 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11195 {}}} SUCCS {{258 0 0-11199 {}}} CYCLES {}}
+set a(0-11197) {NAME ACC1-3:slc(acc.idiv#4)#27 TYPE READSLICE PAR 0-9373 XREFS 59408 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11198 {}}} CYCLES {}}
+set a(0-11198) {NAME ACC1-3:exs#85 TYPE SIGNEXTEND PAR 0-9373 XREFS 59409 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11197 {}}} SUCCS {{259 0 0-11199 {}}} CYCLES {}}
+set a(0-11199) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#493 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59410 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-11196 {}} {259 0 0-11198 {}}} SUCCS {{258 0 0-11205 {}}} CYCLES {}}
+set a(0-11200) {NAME ACC1-3:slc(acc.idiv#4)#29 TYPE READSLICE PAR 0-9373 XREFS 59411 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11201 {}}} CYCLES {}}
+set a(0-11201) {NAME ACC1-3:exs#86 TYPE SIGNEXTEND PAR 0-9373 XREFS 59412 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11200 {}}} SUCCS {{258 0 0-11204 {}}} CYCLES {}}
+set a(0-11202) {NAME ACC1-3:slc(acc.idiv#5)#9 TYPE READSLICE PAR 0-9373 XREFS 59413 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11203 {}}} CYCLES {}}
+set a(0-11203) {NAME ACC1-3:exs#94 TYPE SIGNEXTEND PAR 0-9373 XREFS 59414 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11202 {}}} SUCCS {{259 0 0-11204 {}}} CYCLES {}}
+set a(0-11204) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#492 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59415 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-11201 {}} {259 0 0-11203 {}}} SUCCS {{259 0 0-11205 {}}} CYCLES {}}
+set a(0-11205) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#556 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59416 LOC {1 0.187338 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11199 {}} {259 0 0-11204 {}}} SUCCS {{258 0 0-11217 {}}} CYCLES {}}
+set a(0-11206) {NAME ACC1-3:slc(acc.idiv#5)#11 TYPE READSLICE PAR 0-9373 XREFS 59417 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11207 {}}} CYCLES {}}
+set a(0-11207) {NAME ACC1-3:exs#95 TYPE SIGNEXTEND PAR 0-9373 XREFS 59418 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11206 {}}} SUCCS {{258 0 0-11210 {}}} CYCLES {}}
+set a(0-11208) {NAME ACC1-3:slc(acc.idiv#5)#35 TYPE READSLICE PAR 0-9373 XREFS 59419 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11209 {}}} CYCLES {}}
+set a(0-11209) {NAME ACC1-3:exs#107 TYPE SIGNEXTEND PAR 0-9373 XREFS 59420 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11208 {}}} SUCCS {{259 0 0-11210 {}}} CYCLES {}}
+set a(0-11210) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#491 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59421 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-11207 {}} {259 0 0-11209 {}}} SUCCS {{258 0 0-11216 {}}} CYCLES {}}
+set a(0-11211) {NAME ACC1:slc(acc#25.psp#2)#28 TYPE READSLICE PAR 0-9373 XREFS 59422 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11212 {}}} CYCLES {}}
+set a(0-11212) {NAME ACC1-2:exs#94 TYPE SIGNEXTEND PAR 0-9373 XREFS 59423 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11211 {}}} SUCCS {{258 0 0-11215 {}}} CYCLES {}}
+set a(0-11213) {NAME ACC1:slc(acc#25.psp#2)#29 TYPE READSLICE PAR 0-9373 XREFS 59424 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11214 {}}} CYCLES {}}
+set a(0-11214) {NAME ACC1-2:exs#95 TYPE SIGNEXTEND PAR 0-9373 XREFS 59425 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11213 {}}} SUCCS {{259 0 0-11215 {}}} CYCLES {}}
+set a(0-11215) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#489 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59426 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-11212 {}} {259 0 0-11214 {}}} SUCCS {{259 0 0-11216 {}}} CYCLES {}}
+set a(0-11216) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#555 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59427 LOC {1 0.187338 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11210 {}} {259 0 0-11215 {}}} SUCCS {{259 0 0-11217 {}}} CYCLES {}}
+set a(0-11217) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#593 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59428 LOC {1 0.23489417499999998 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-11205 {}} {259 0 0-11216 {}}} SUCCS {{258 0 0-11241 {}}} CYCLES {}}
+set a(0-11218) {NAME ACC1:slc(acc#25.psp#2)#30 TYPE READSLICE PAR 0-9373 XREFS 59429 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11219 {}}} CYCLES {}}
+set a(0-11219) {NAME ACC1-2:exs#90 TYPE SIGNEXTEND PAR 0-9373 XREFS 59430 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11218 {}}} SUCCS {{258 0 0-11222 {}}} CYCLES {}}
+set a(0-11220) {NAME ACC1:slc(acc#25.psp#2)#31 TYPE READSLICE PAR 0-9373 XREFS 59431 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11221 {}}} CYCLES {}}
+set a(0-11221) {NAME ACC1-2:exs#91 TYPE SIGNEXTEND PAR 0-9373 XREFS 59432 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11220 {}}} SUCCS {{259 0 0-11222 {}}} CYCLES {}}
+set a(0-11222) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#488 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59433 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-11219 {}} {259 0 0-11221 {}}} SUCCS {{258 0 0-11228 {}}} CYCLES {}}
+set a(0-11223) {NAME ACC1:slc(acc#25.psp#2)#32 TYPE READSLICE PAR 0-9373 XREFS 59434 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11224 {}}} CYCLES {}}
+set a(0-11224) {NAME ACC1-2:exs#92 TYPE SIGNEXTEND PAR 0-9373 XREFS 59435 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11223 {}}} SUCCS {{258 0 0-11227 {}}} CYCLES {}}
+set a(0-11225) {NAME ACC1:slc(acc#25.psp#2)#33 TYPE READSLICE PAR 0-9373 XREFS 59436 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11226 {}}} CYCLES {}}
+set a(0-11226) {NAME ACC1-2:exs#93 TYPE SIGNEXTEND PAR 0-9373 XREFS 59437 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11225 {}}} SUCCS {{259 0 0-11227 {}}} CYCLES {}}
+set a(0-11227) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#487 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59438 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-11224 {}} {259 0 0-11226 {}}} SUCCS {{259 0 0-11228 {}}} CYCLES {}}
+set a(0-11228) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#554 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59439 LOC {1 0.187338 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11222 {}} {259 0 0-11227 {}}} SUCCS {{258 0 0-11240 {}}} CYCLES {}}
+set a(0-11229) {NAME ACC1:slc(acc#25.psp#2)#34 TYPE READSLICE PAR 0-9373 XREFS 59440 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11230 {}}} CYCLES {}}
+set a(0-11230) {NAME ACC1-2:exs#99 TYPE SIGNEXTEND PAR 0-9373 XREFS 59441 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11229 {}}} SUCCS {{258 0 0-11233 {}}} CYCLES {}}
+set a(0-11231) {NAME ACC1:slc(acc#25.psp#2)#35 TYPE READSLICE PAR 0-9373 XREFS 59442 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11232 {}}} CYCLES {}}
+set a(0-11232) {NAME ACC1-2:exs#100 TYPE SIGNEXTEND PAR 0-9373 XREFS 59443 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11231 {}}} SUCCS {{259 0 0-11233 {}}} CYCLES {}}
+set a(0-11233) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#486 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59444 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-11230 {}} {259 0 0-11232 {}}} SUCCS {{258 0 0-11239 {}}} CYCLES {}}
+set a(0-11234) {NAME ACC1:slc(acc#25.psp#2)#36 TYPE READSLICE PAR 0-9373 XREFS 59445 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11235 {}}} CYCLES {}}
+set a(0-11235) {NAME ACC1-2:exs#96 TYPE SIGNEXTEND PAR 0-9373 XREFS 59446 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11234 {}}} SUCCS {{258 0 0-11238 {}}} CYCLES {}}
+set a(0-11236) {NAME ACC1:slc(acc#25.psp#2)#37 TYPE READSLICE PAR 0-9373 XREFS 59447 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11237 {}}} CYCLES {}}
+set a(0-11237) {NAME ACC1-2:exs#97 TYPE SIGNEXTEND PAR 0-9373 XREFS 59448 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11236 {}}} SUCCS {{259 0 0-11238 {}}} CYCLES {}}
+set a(0-11238) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#485 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59449 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-11235 {}} {259 0 0-11237 {}}} SUCCS {{259 0 0-11239 {}}} CYCLES {}}
+set a(0-11239) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#553 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59450 LOC {1 0.187338 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11233 {}} {259 0 0-11238 {}}} SUCCS {{259 0 0-11240 {}}} CYCLES {}}
+set a(0-11240) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#592 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59451 LOC {1 0.23489417499999998 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-11228 {}} {259 0 0-11239 {}}} SUCCS {{259 0 0-11241 {}}} CYCLES {}}
+set a(0-11241) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#611 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-9373 XREFS 59452 LOC {1 0.28824125 1 0.620914525 1 0.620914525 1 0.679514234496936 1 0.815914059496936} PREDS {{258 0 0-11217 {}} {259 0 0-11240 {}}} SUCCS {{258 0 0-11299 {}}} CYCLES {}}
+set a(0-11242) {NAME ACC1:slc(acc#25.psp#2)#38 TYPE READSLICE PAR 0-9373 XREFS 59453 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11243 {}}} CYCLES {}}
+set a(0-11243) {NAME ACC1-2:exs#98 TYPE SIGNEXTEND PAR 0-9373 XREFS 59454 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11242 {}}} SUCCS {{258 0 0-11246 {}}} CYCLES {}}
+set a(0-11244) {NAME ACC1:slc(acc#25.psp#2)#39 TYPE READSLICE PAR 0-9373 XREFS 59455 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11245 {}}} CYCLES {}}
+set a(0-11245) {NAME ACC1-2:exs#102 TYPE SIGNEXTEND PAR 0-9373 XREFS 59456 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11244 {}}} SUCCS {{259 0 0-11246 {}}} CYCLES {}}
+set a(0-11246) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#484 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59457 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-11243 {}} {259 0 0-11245 {}}} SUCCS {{258 0 0-11252 {}}} CYCLES {}}
+set a(0-11247) {NAME ACC1:slc(acc#25.psp#2)#40 TYPE READSLICE PAR 0-9373 XREFS 59458 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11248 {}}} CYCLES {}}
+set a(0-11248) {NAME ACC1-2:exs#353 TYPE SIGNEXTEND PAR 0-9373 XREFS 59459 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11247 {}}} SUCCS {{258 0 0-11251 {}}} CYCLES {}}
+set a(0-11249) {NAME ACC1:slc(acc#25.psp#2)#41 TYPE READSLICE PAR 0-9373 XREFS 59460 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11250 {}}} CYCLES {}}
+set a(0-11250) {NAME ACC1-2:exs#101 TYPE SIGNEXTEND PAR 0-9373 XREFS 59461 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11249 {}}} SUCCS {{259 0 0-11251 {}}} CYCLES {}}
+set a(0-11251) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#483 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59462 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-11248 {}} {259 0 0-11250 {}}} SUCCS {{259 0 0-11252 {}}} CYCLES {}}
+set a(0-11252) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#552 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59463 LOC {1 0.187338 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11246 {}} {259 0 0-11251 {}}} SUCCS {{258 0 0-11264 {}}} CYCLES {}}
+set a(0-11253) {NAME ACC1:slc(acc#25.psp#2)#51 TYPE READSLICE PAR 0-9373 XREFS 59464 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11254 {}}} CYCLES {}}
+set a(0-11254) {NAME ACC1-2:exs#106 TYPE SIGNEXTEND PAR 0-9373 XREFS 59465 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11253 {}}} SUCCS {{258 0 0-11257 {}}} CYCLES {}}
+set a(0-11255) {NAME ACC1:slc(acc#25.psp#2)#55 TYPE READSLICE PAR 0-9373 XREFS 59466 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11256 {}}} CYCLES {}}
+set a(0-11256) {NAME ACC1-2:exs#963 TYPE SIGNEXTEND PAR 0-9373 XREFS 59467 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11255 {}}} SUCCS {{259 0 0-11257 {}}} CYCLES {}}
+set a(0-11257) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#482 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59468 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-11254 {}} {259 0 0-11256 {}}} SUCCS {{258 0 0-11263 {}}} CYCLES {}}
+set a(0-11258) {NAME ACC1:slc(acc#25.psp#2)#60 TYPE READSLICE PAR 0-9373 XREFS 59469 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11259 {}}} CYCLES {}}
+set a(0-11259) {NAME ACC1-2:exs#103 TYPE SIGNEXTEND PAR 0-9373 XREFS 59470 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11258 {}}} SUCCS {{258 0 0-11262 {}}} CYCLES {}}
+set a(0-11260) {NAME ACC1:slc(acc#25.psp#2)#63 TYPE READSLICE PAR 0-9373 XREFS 59471 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.61562805} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11261 {}}} CYCLES {}}
+set a(0-11261) {NAME ACC1-2:exs#104 TYPE SIGNEXTEND PAR 0-9373 XREFS 59472 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11260 {}}} SUCCS {{259 0 0-11262 {}}} CYCLES {}}
+set a(0-11262) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#481 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59473 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-11259 {}} {259 0 0-11261 {}}} SUCCS {{259 0 0-11263 {}}} CYCLES {}}
+set a(0-11263) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#551 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59474 LOC {1 0.187338 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11257 {}} {259 0 0-11262 {}}} SUCCS {{259 0 0-11264 {}}} CYCLES {}}
+set a(0-11264) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#591 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59475 LOC {1 0.23489417499999998 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-11252 {}} {259 0 0-11263 {}}} SUCCS {{258 0 0-11298 {}}} CYCLES {}}
+set a(0-11265) {NAME ACC1-3:slc(acc.idiv#5)#7 TYPE READSLICE PAR 0-9373 XREFS 59476 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11266 {}}} CYCLES {}}
+set a(0-11266) {NAME ACC1-3:exs#93 TYPE SIGNEXTEND PAR 0-9373 XREFS 59477 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11265 {}}} SUCCS {{258 0 0-11269 {}}} CYCLES {}}
+set a(0-11267) {NAME slc(acc#20.psp#1) TYPE READSLICE PAR 0-9373 XREFS 59478 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.61562805} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11268 {}}} CYCLES {}}
+set a(0-11268) {NAME ACC1:exs#1453 TYPE SIGNEXTEND PAR 0-9373 XREFS 59479 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.61562805} PREDS {{259 0 0-11267 {}}} SUCCS {{259 0 0-11269 {}}} CYCLES {}}
+set a(0-11269) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#480 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59480 LOC {1 0.14655495 1 0.47922822499999995 1 0.47922822499999995 1 0.5200112350894752 1 0.6564110600894753} PREDS {{258 0 0-11266 {}} {259 0 0-11268 {}}} SUCCS {{258 0 0-11278 {}}} CYCLES {}}
+set a(0-11270) {NAME ACC1-3:slc(acc.idiv#5)#1 TYPE READSLICE PAR 0-9373 XREFS 59481 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11271 {}}} CYCLES {}}
+set a(0-11271) {NAME ACC1-3:exs#90 TYPE SIGNEXTEND PAR 0-9373 XREFS 59482 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11270 {}}} SUCCS {{259 0 0-11272 {}}} CYCLES {}}
+set a(0-11272) {NAME ACC1:conc#1416 TYPE CONCATENATE PAR 0-9373 XREFS 59483 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11271 {}}} SUCCS {{258 0 0-11276 {}}} CYCLES {}}
+set a(0-11273) {NAME ACC1-3:slc(acc.idiv#5)#3 TYPE READSLICE PAR 0-9373 XREFS 59484 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11274 {}}} CYCLES {}}
+set a(0-11274) {NAME ACC1-3:exs#91 TYPE SIGNEXTEND PAR 0-9373 XREFS 59485 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11273 {}}} SUCCS {{259 0 0-11275 {}}} CYCLES {}}
+set a(0-11275) {NAME ACC1:conc#1417 TYPE CONCATENATE PAR 0-9373 XREFS 59486 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9462 {}} {259 0 0-11274 {}}} SUCCS {{259 0 0-11276 {}}} CYCLES {}}
+set a(0-11276) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#479 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59487 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11272 {}} {259 0 0-11275 {}}} SUCCS {{259 0 0-11277 {}}} CYCLES {}}
+set a(0-11277) {NAME ACC1:slc#147 TYPE READSLICE PAR 0-9373 XREFS 59488 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11276 {}}} SUCCS {{259 0 0-11278 {}}} CYCLES {}}
+set a(0-11278) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#550 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59489 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11269 {}} {259 0 0-11277 {}}} SUCCS {{258 0 0-11297 {}}} CYCLES {}}
+set a(0-11279) {NAME ACC1-3:slc(acc.idiv#5)#5 TYPE READSLICE PAR 0-9373 XREFS 59490 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11280 {}}} CYCLES {}}
+set a(0-11280) {NAME ACC1-3:exs#92 TYPE SIGNEXTEND PAR 0-9373 XREFS 59491 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11279 {}}} SUCCS {{259 0 0-11281 {}}} CYCLES {}}
+set a(0-11281) {NAME ACC1:conc#1414 TYPE CONCATENATE PAR 0-9373 XREFS 59492 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11280 {}}} SUCCS {{258 0 0-11285 {}}} CYCLES {}}
+set a(0-11282) {NAME ACC1-3:slc(acc.idiv#5)#19 TYPE READSLICE PAR 0-9373 XREFS 59493 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-10065 {}}} SUCCS {{259 0 0-11283 {}}} CYCLES {}}
+set a(0-11283) {NAME ACC1-3:exs#99 TYPE SIGNEXTEND PAR 0-9373 XREFS 59494 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11282 {}}} SUCCS {{259 0 0-11284 {}}} CYCLES {}}
+set a(0-11284) {NAME ACC1:conc#1415 TYPE CONCATENATE PAR 0-9373 XREFS 59495 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9457 {}} {259 0 0-11283 {}}} SUCCS {{259 0 0-11285 {}}} CYCLES {}}
+set a(0-11285) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#478 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59496 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11281 {}} {259 0 0-11284 {}}} SUCCS {{259 0 0-11286 {}}} CYCLES {}}
+set a(0-11286) {NAME ACC1:slc#146 TYPE READSLICE PAR 0-9373 XREFS 59497 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11285 {}}} SUCCS {{258 0 0-11296 {}}} CYCLES {}}
+set a(0-11287) {NAME ACC1-3:slc(acc.idiv)#17 TYPE READSLICE PAR 0-9373 XREFS 59498 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11288 {}}} CYCLES {}}
+set a(0-11288) {NAME ACC1-3:exs#8 TYPE SIGNEXTEND PAR 0-9373 XREFS 59499 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11287 {}}} SUCCS {{259 0 0-11289 {}}} CYCLES {}}
+set a(0-11289) {NAME ACC1:conc#1412 TYPE CONCATENATE PAR 0-9373 XREFS 59500 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11288 {}}} SUCCS {{258 0 0-11294 {}}} CYCLES {}}
+set a(0-11290) {NAME ACC1-3:slc(acc.idiv)#13 TYPE READSLICE PAR 0-9373 XREFS 59501 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11291 {}}} CYCLES {}}
+set a(0-11291) {NAME ACC1-3:exs#6 TYPE SIGNEXTEND PAR 0-9373 XREFS 59502 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11290 {}}} SUCCS {{258 0 0-11293 {}}} CYCLES {}}
+set a(0-11292) {NAME ACC1:slc(acc.imod#26) TYPE READSLICE PAR 0-9373 XREFS 59503 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.6088549249999999} PREDS {{258 0 0-9444 {}}} SUCCS {{259 0 0-11293 {}}} CYCLES {}}
+set a(0-11293) {NAME ACC1:conc#1413 TYPE CONCATENATE PAR 0-9373 XREFS 59504 LOC {1 0.356432775 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11291 {}} {259 0 0-11292 {}}} SUCCS {{259 0 0-11294 {}}} CYCLES {}}
+set a(0-11294) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#477 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59505 LOC {1 0.356432775 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11289 {}} {259 0 0-11293 {}}} SUCCS {{259 0 0-11295 {}}} CYCLES {}}
+set a(0-11295) {NAME ACC1:slc#145 TYPE READSLICE PAR 0-9373 XREFS 59506 LOC {1 0.40398894999999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11294 {}}} SUCCS {{259 0 0-11296 {}}} CYCLES {}}
+set a(0-11296) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#549 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59507 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11286 {}} {259 0 0-11295 {}}} SUCCS {{259 0 0-11297 {}}} CYCLES {}}
+set a(0-11297) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#590 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59508 LOC {1 0.47879105 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-11278 {}} {259 0 0-11296 {}}} SUCCS {{259 0 0-11298 {}}} CYCLES {}}
+set a(0-11298) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#610 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-9373 XREFS 59509 LOC {1 0.532138125 1 0.620914525 1 0.620914525 1 0.679514234496936 1 0.815914059496936} PREDS {{258 0 0-11264 {}} {259 0 0-11297 {}}} SUCCS {{259 0 0-11299 {}}} CYCLES {}}
+set a(0-11299) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#625 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-9373 XREFS 59510 LOC {1 0.590737875 1 0.679514275 1 0.679514275 1 0.7430262484103024 1 0.8794260734103024} PREDS {{258 0 0-11241 {}} {259 0 0-11298 {}}} SUCCS {{258 0 0-11476 {}}} CYCLES {}}
+set a(0-11300) {NAME ACC1-3:slc(acc.idiv)#23 TYPE READSLICE PAR 0-9373 XREFS 59511 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11301 {}}} CYCLES {}}
+set a(0-11301) {NAME ACC1-3:exs#11 TYPE SIGNEXTEND PAR 0-9373 XREFS 59512 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11300 {}}} SUCCS {{259 0 0-11302 {}}} CYCLES {}}
+set a(0-11302) {NAME ACC1:conc#1410 TYPE CONCATENATE PAR 0-9373 XREFS 59513 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11301 {}}} SUCCS {{258 0 0-11307 {}}} CYCLES {}}
+set a(0-11303) {NAME ACC1-3:slc(acc.idiv)#19 TYPE READSLICE PAR 0-9373 XREFS 59514 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11304 {}}} CYCLES {}}
+set a(0-11304) {NAME ACC1-3:exs#9 TYPE SIGNEXTEND PAR 0-9373 XREFS 59515 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11303 {}}} SUCCS {{258 0 0-11306 {}}} CYCLES {}}
+set a(0-11305) {NAME ACC1:slc(ACC1:acc#210.psp#2)#2 TYPE READSLICE PAR 0-9373 XREFS 59516 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.6088549249999999} PREDS {{258 0 0-9426 {}}} SUCCS {{259 0 0-11306 {}}} CYCLES {}}
+set a(0-11306) {NAME ACC1:conc#1411 TYPE CONCATENATE PAR 0-9373 XREFS 59517 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11304 {}} {259 0 0-11305 {}}} SUCCS {{259 0 0-11307 {}}} CYCLES {}}
+set a(0-11307) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#476 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59518 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11302 {}} {259 0 0-11306 {}}} SUCCS {{259 0 0-11308 {}}} CYCLES {}}
+set a(0-11308) {NAME ACC1:slc#144 TYPE READSLICE PAR 0-9373 XREFS 59519 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11307 {}}} SUCCS {{258 0 0-11318 {}}} CYCLES {}}
+set a(0-11309) {NAME ACC1-3:slc(acc.idiv)#21 TYPE READSLICE PAR 0-9373 XREFS 59520 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11310 {}}} CYCLES {}}
+set a(0-11310) {NAME ACC1-3:exs#10 TYPE SIGNEXTEND PAR 0-9373 XREFS 59521 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11309 {}}} SUCCS {{259 0 0-11311 {}}} CYCLES {}}
+set a(0-11311) {NAME ACC1:conc#1408 TYPE CONCATENATE PAR 0-9373 XREFS 59522 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11310 {}}} SUCCS {{258 0 0-11316 {}}} CYCLES {}}
+set a(0-11312) {NAME ACC1-3:slc(acc.idiv)#31 TYPE READSLICE PAR 0-9373 XREFS 59523 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11313 {}}} CYCLES {}}
+set a(0-11313) {NAME ACC1-3:exs#15 TYPE SIGNEXTEND PAR 0-9373 XREFS 59524 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11312 {}}} SUCCS {{258 0 0-11315 {}}} CYCLES {}}
+set a(0-11314) {NAME ACC1:slc(ACC1:acc#210.psp#2)#1 TYPE READSLICE PAR 0-9373 XREFS 59525 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.6088549249999999} PREDS {{258 0 0-9426 {}}} SUCCS {{259 0 0-11315 {}}} CYCLES {}}
+set a(0-11315) {NAME ACC1:conc#1409 TYPE CONCATENATE PAR 0-9373 XREFS 59526 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11313 {}} {259 0 0-11314 {}}} SUCCS {{259 0 0-11316 {}}} CYCLES {}}
+set a(0-11316) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#475 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59527 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11311 {}} {259 0 0-11315 {}}} SUCCS {{259 0 0-11317 {}}} CYCLES {}}
+set a(0-11317) {NAME ACC1:slc#143 TYPE READSLICE PAR 0-9373 XREFS 59528 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11316 {}}} SUCCS {{259 0 0-11318 {}}} CYCLES {}}
+set a(0-11318) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#548 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59529 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11308 {}} {259 0 0-11317 {}}} SUCCS {{258 0 0-11338 {}}} CYCLES {}}
+set a(0-11319) {NAME ACC1-3:slc(acc.idiv)#9 TYPE READSLICE PAR 0-9373 XREFS 59530 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11320 {}}} CYCLES {}}
+set a(0-11320) {NAME ACC1-3:exs#4 TYPE SIGNEXTEND PAR 0-9373 XREFS 59531 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11319 {}}} SUCCS {{259 0 0-11321 {}}} CYCLES {}}
+set a(0-11321) {NAME ACC1:conc#1406 TYPE CONCATENATE PAR 0-9373 XREFS 59532 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11320 {}}} SUCCS {{258 0 0-11326 {}}} CYCLES {}}
+set a(0-11322) {NAME ACC1-3:slc(acc.idiv)#11 TYPE READSLICE PAR 0-9373 XREFS 59533 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11323 {}}} CYCLES {}}
+set a(0-11323) {NAME ACC1-3:exs#5 TYPE SIGNEXTEND PAR 0-9373 XREFS 59534 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11322 {}}} SUCCS {{258 0 0-11325 {}}} CYCLES {}}
+set a(0-11324) {NAME ACC1:slc(ACC1:acc#210.psp#2) TYPE READSLICE PAR 0-9373 XREFS 59535 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.6088549249999999} PREDS {{258 0 0-9426 {}}} SUCCS {{259 0 0-11325 {}}} CYCLES {}}
+set a(0-11325) {NAME ACC1:conc#1407 TYPE CONCATENATE PAR 0-9373 XREFS 59536 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11323 {}} {259 0 0-11324 {}}} SUCCS {{259 0 0-11326 {}}} CYCLES {}}
+set a(0-11326) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#474 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59537 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11321 {}} {259 0 0-11325 {}}} SUCCS {{259 0 0-11327 {}}} CYCLES {}}
+set a(0-11327) {NAME ACC1:slc#142 TYPE READSLICE PAR 0-9373 XREFS 59538 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11326 {}}} SUCCS {{258 0 0-11337 {}}} CYCLES {}}
+set a(0-11328) {NAME ACC1-3:slc(acc.idiv)#1 TYPE READSLICE PAR 0-9373 XREFS 59539 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11329 {}}} CYCLES {}}
+set a(0-11329) {NAME ACC1-3:exs#951 TYPE SIGNEXTEND PAR 0-9373 XREFS 59540 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11328 {}}} SUCCS {{259 0 0-11330 {}}} CYCLES {}}
+set a(0-11330) {NAME ACC1:conc#1404 TYPE CONCATENATE PAR 0-9373 XREFS 59541 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11329 {}}} SUCCS {{258 0 0-11335 {}}} CYCLES {}}
+set a(0-11331) {NAME ACC1-3:slc(acc.idiv)#3 TYPE READSLICE PAR 0-9373 XREFS 59542 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11332 {}}} CYCLES {}}
+set a(0-11332) {NAME ACC1-3:exs#1 TYPE SIGNEXTEND PAR 0-9373 XREFS 59543 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11331 {}}} SUCCS {{258 0 0-11334 {}}} CYCLES {}}
+set a(0-11333) {NAME ACC1:slc(acc.psp#2)#7 TYPE READSLICE PAR 0-9373 XREFS 59544 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6088549249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-11334 {}}} CYCLES {}}
+set a(0-11334) {NAME ACC1:conc#1405 TYPE CONCATENATE PAR 0-9373 XREFS 59545 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11332 {}} {259 0 0-11333 {}}} SUCCS {{259 0 0-11335 {}}} CYCLES {}}
+set a(0-11335) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#473 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59546 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11330 {}} {259 0 0-11334 {}}} SUCCS {{259 0 0-11336 {}}} CYCLES {}}
+set a(0-11336) {NAME ACC1:slc#141 TYPE READSLICE PAR 0-9373 XREFS 59547 LOC {1 0.194111125 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11335 {}}} SUCCS {{259 0 0-11337 {}}} CYCLES {}}
+set a(0-11337) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#547 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59548 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11327 {}} {259 0 0-11336 {}}} SUCCS {{259 0 0-11338 {}}} CYCLES {}}
+set a(0-11338) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#589 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59549 LOC {1 0.36304335 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-11318 {}} {259 0 0-11337 {}}} SUCCS {{258 0 0-11385 {}}} CYCLES {}}
+set a(0-11339) {NAME ACC1-3:slc(acc.idiv)#5 TYPE READSLICE PAR 0-9373 XREFS 59550 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11340 {}}} CYCLES {}}
+set a(0-11340) {NAME ACC1-3:exs#2 TYPE SIGNEXTEND PAR 0-9373 XREFS 59551 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11339 {}}} SUCCS {{259 0 0-11341 {}}} CYCLES {}}
+set a(0-11341) {NAME ACC1:conc#1402 TYPE CONCATENATE PAR 0-9373 XREFS 59552 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11340 {}}} SUCCS {{258 0 0-11346 {}}} CYCLES {}}
+set a(0-11342) {NAME ACC1-3:slc(acc.idiv)#7 TYPE READSLICE PAR 0-9373 XREFS 59553 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6088549249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11343 {}}} CYCLES {}}
+set a(0-11343) {NAME ACC1-3:exs#3 TYPE SIGNEXTEND PAR 0-9373 XREFS 59554 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11342 {}}} SUCCS {{258 0 0-11345 {}}} CYCLES {}}
+set a(0-11344) {NAME ACC1:slc(acc.psp#2)#6 TYPE READSLICE PAR 0-9373 XREFS 59555 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6088549249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-11345 {}}} CYCLES {}}
+set a(0-11345) {NAME ACC1:conc#1403 TYPE CONCATENATE PAR 0-9373 XREFS 59556 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11343 {}} {259 0 0-11344 {}}} SUCCS {{259 0 0-11346 {}}} CYCLES {}}
+set a(0-11346) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#472 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59557 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11341 {}} {259 0 0-11345 {}}} SUCCS {{259 0 0-11347 {}}} CYCLES {}}
+set a(0-11347) {NAME ACC1:slc#140 TYPE READSLICE PAR 0-9373 XREFS 59558 LOC {1 0.194111125 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11346 {}}} SUCCS {{258 0 0-11357 {}}} CYCLES {}}
+set a(0-11348) {NAME ACC1-1:slc(acc#10.psp)#67 TYPE READSLICE PAR 0-9373 XREFS 59559 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11349 {}}} CYCLES {}}
+set a(0-11349) {NAME ACC1-1:exs#52 TYPE SIGNEXTEND PAR 0-9373 XREFS 59560 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11348 {}}} SUCCS {{259 0 0-11350 {}}} CYCLES {}}
+set a(0-11350) {NAME ACC1:conc#1398 TYPE CONCATENATE PAR 0-9373 XREFS 59561 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11349 {}}} SUCCS {{258 0 0-11355 {}}} CYCLES {}}
+set a(0-11351) {NAME ACC1-1:slc(acc#10.psp)#66 TYPE READSLICE PAR 0-9373 XREFS 59562 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11352 {}}} CYCLES {}}
+set a(0-11352) {NAME ACC1-1:exs#53 TYPE SIGNEXTEND PAR 0-9373 XREFS 59563 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11351 {}}} SUCCS {{258 0 0-11354 {}}} CYCLES {}}
+set a(0-11353) {NAME ACC1:slc(acc.psp#2)#4 TYPE READSLICE PAR 0-9373 XREFS 59564 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.6088549249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-11354 {}}} CYCLES {}}
+set a(0-11354) {NAME ACC1:conc#1399 TYPE CONCATENATE PAR 0-9373 XREFS 59565 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11352 {}} {259 0 0-11353 {}}} SUCCS {{259 0 0-11355 {}}} CYCLES {}}
+set a(0-11355) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#470 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59566 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11350 {}} {259 0 0-11354 {}}} SUCCS {{259 0 0-11356 {}}} CYCLES {}}
+set a(0-11356) {NAME ACC1:slc#138 TYPE READSLICE PAR 0-9373 XREFS 59567 LOC {1 0.194111125 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11355 {}}} SUCCS {{259 0 0-11357 {}}} CYCLES {}}
+set a(0-11357) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#546 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59568 LOC {1 0.194111125 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11347 {}} {259 0 0-11356 {}}} SUCCS {{258 0 0-11384 {}}} CYCLES {}}
+set a(0-11358) {NAME ACC1-1:slc(acc#10.psp)#65 TYPE READSLICE PAR 0-9373 XREFS 59569 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11359 {}}} CYCLES {}}
+set a(0-11359) {NAME ACC1-1:exs#40 TYPE SIGNEXTEND PAR 0-9373 XREFS 59570 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11358 {}}} SUCCS {{259 0 0-11360 {}}} CYCLES {}}
+set a(0-11360) {NAME ACC1:conc#1396 TYPE CONCATENATE PAR 0-9373 XREFS 59571 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11359 {}}} SUCCS {{258 0 0-11369 {}}} CYCLES {}}
+set a(0-11361) {NAME ACC1-1:slc(acc#10.psp)#64 TYPE READSLICE PAR 0-9373 XREFS 59572 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11362 {}}} CYCLES {}}
+set a(0-11362) {NAME ACC1-1:exs#41 TYPE SIGNEXTEND PAR 0-9373 XREFS 59573 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11361 {}}} SUCCS {{258 0 0-11368 {}}} CYCLES {}}
+set a(0-11363) {NAME ACC1-3:slc(acc.idiv#1)#45 TYPE READSLICE PAR 0-9373 XREFS 59574 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6088549249999999} PREDS {{258 0 0-9918 {}}} SUCCS {{258 0 0-11367 {}}} CYCLES {}}
+set a(0-11364) {NAME ACC1-3:slc(acc.imod#7)#1 TYPE READSLICE PAR 0-9373 XREFS 59575 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9985 {}}} SUCCS {{259 0 0-11365 {}}} CYCLES {}}
+set a(0-11365) {NAME ACC1-3:not#60 TYPE NOT PAR 0-9373 XREFS 59576 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11364 {}}} SUCCS {{258 0 0-11367 {}}} CYCLES {}}
+set a(0-11366) {NAME ACC1-3:slc(acc.imod#7)#2 TYPE READSLICE PAR 0-9373 XREFS 59577 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9985 {}}} SUCCS {{259 0 0-11367 {}}} CYCLES {}}
+set a(0-11367) {NAME ACC1-3:and#3 TYPE AND PAR 0-9373 XREFS 59578 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11365 {}} {258 0 0-11363 {}} {259 0 0-11366 {}}} SUCCS {{259 0 0-11368 {}}} CYCLES {}}
+set a(0-11368) {NAME ACC1:conc#1397 TYPE CONCATENATE PAR 0-9373 XREFS 59579 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11362 {}} {259 0 0-11367 {}}} SUCCS {{259 0 0-11369 {}}} CYCLES {}}
+set a(0-11369) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#469 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59580 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11360 {}} {259 0 0-11368 {}}} SUCCS {{259 0 0-11370 {}}} CYCLES {}}
+set a(0-11370) {NAME ACC1:slc#137 TYPE READSLICE PAR 0-9373 XREFS 59581 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11369 {}}} SUCCS {{258 0 0-11383 {}}} CYCLES {}}
+set a(0-11371) {NAME ACC1-1:slc(acc#10.psp)#63 TYPE READSLICE PAR 0-9373 XREFS 59582 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11372 {}}} CYCLES {}}
+set a(0-11372) {NAME ACC1-1:exs#36 TYPE SIGNEXTEND PAR 0-9373 XREFS 59583 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11371 {}}} SUCCS {{259 0 0-11373 {}}} CYCLES {}}
+set a(0-11373) {NAME ACC1:conc#1394 TYPE CONCATENATE PAR 0-9373 XREFS 59584 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11372 {}}} SUCCS {{258 0 0-11381 {}}} CYCLES {}}
+set a(0-11374) {NAME ACC1-1:slc(acc#10.psp)#62 TYPE READSLICE PAR 0-9373 XREFS 59585 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11375 {}}} CYCLES {}}
+set a(0-11375) {NAME ACC1-1:exs#37 TYPE SIGNEXTEND PAR 0-9373 XREFS 59586 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11374 {}}} SUCCS {{258 0 0-11380 {}}} CYCLES {}}
+set a(0-11376) {NAME ACC1-3:slc(acc.imod#7) TYPE READSLICE PAR 0-9373 XREFS 59587 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9985 {}}} SUCCS {{258 0 0-11379 {}}} CYCLES {}}
+set a(0-11377) {NAME ACC1-3:slc(acc.idiv#1)#44 TYPE READSLICE PAR 0-9373 XREFS 59588 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6088549249999999} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-11378 {}}} CYCLES {}}
+set a(0-11378) {NAME ACC1-3:not#59 TYPE NOT PAR 0-9373 XREFS 59589 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11377 {}}} SUCCS {{259 0 0-11379 {}}} CYCLES {}}
+set a(0-11379) {NAME ACC1-3:nand#1 TYPE NAND PAR 0-9373 XREFS 59590 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11376 {}} {259 0 0-11378 {}}} SUCCS {{259 0 0-11380 {}}} CYCLES {}}
+set a(0-11380) {NAME ACC1:conc#1395 TYPE CONCATENATE PAR 0-9373 XREFS 59591 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11375 {}} {259 0 0-11379 {}}} SUCCS {{259 0 0-11381 {}}} CYCLES {}}
+set a(0-11381) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#468 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59592 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11373 {}} {259 0 0-11380 {}}} SUCCS {{259 0 0-11382 {}}} CYCLES {}}
+set a(0-11382) {NAME ACC1:slc#136 TYPE READSLICE PAR 0-9373 XREFS 59593 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11381 {}}} SUCCS {{259 0 0-11383 {}}} CYCLES {}}
+set a(0-11383) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#545 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59594 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11370 {}} {259 0 0-11382 {}}} SUCCS {{259 0 0-11384 {}}} CYCLES {}}
+set a(0-11384) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#588 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59595 LOC {1 0.47879105 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-11357 {}} {259 0 0-11383 {}}} SUCCS {{259 0 0-11385 {}}} CYCLES {}}
+set a(0-11385) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#609 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-9373 XREFS 59596 LOC {1 0.532138125 1 0.620914525 1 0.620914525 1 0.679514234496936 1 0.815914059496936} PREDS {{258 0 0-11338 {}} {259 0 0-11384 {}}} SUCCS {{258 0 0-11475 {}}} CYCLES {}}
+set a(0-11386) {NAME ACC1-1:slc(acc#10.psp)#61 TYPE READSLICE PAR 0-9373 XREFS 59597 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11387 {}}} CYCLES {}}
+set a(0-11387) {NAME ACC1-1:exs#38 TYPE SIGNEXTEND PAR 0-9373 XREFS 59598 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11386 {}}} SUCCS {{259 0 0-11388 {}}} CYCLES {}}
+set a(0-11388) {NAME ACC1:conc#1392 TYPE CONCATENATE PAR 0-9373 XREFS 59599 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11387 {}}} SUCCS {{258 0 0-11397 {}}} CYCLES {}}
+set a(0-11389) {NAME ACC1-1:slc(acc#10.psp)#60 TYPE READSLICE PAR 0-9373 XREFS 59600 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11390 {}}} CYCLES {}}
+set a(0-11390) {NAME ACC1-1:exs#39 TYPE SIGNEXTEND PAR 0-9373 XREFS 59601 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11389 {}}} SUCCS {{258 0 0-11396 {}}} CYCLES {}}
+set a(0-11391) {NAME ACC1-1:slc(acc.idiv#5)#45 TYPE READSLICE PAR 0-9373 XREFS 59602 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6088549249999999} PREDS {{258 0 0-9616 {}}} SUCCS {{258 0 0-11395 {}}} CYCLES {}}
+set a(0-11392) {NAME ACC1-1:slc(acc.imod#23)#1 TYPE READSLICE PAR 0-9373 XREFS 59603 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9683 {}}} SUCCS {{259 0 0-11393 {}}} CYCLES {}}
+set a(0-11393) {NAME ACC1-1:not#188 TYPE NOT PAR 0-9373 XREFS 59604 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11392 {}}} SUCCS {{258 0 0-11395 {}}} CYCLES {}}
+set a(0-11394) {NAME ACC1-1:slc(acc.imod#23)#2 TYPE READSLICE PAR 0-9373 XREFS 59605 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9683 {}}} SUCCS {{259 0 0-11395 {}}} CYCLES {}}
+set a(0-11395) {NAME ACC1-1:and#11 TYPE AND PAR 0-9373 XREFS 59606 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11393 {}} {258 0 0-11391 {}} {259 0 0-11394 {}}} SUCCS {{259 0 0-11396 {}}} CYCLES {}}
+set a(0-11396) {NAME ACC1:conc#1393 TYPE CONCATENATE PAR 0-9373 XREFS 59607 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11390 {}} {259 0 0-11395 {}}} SUCCS {{259 0 0-11397 {}}} CYCLES {}}
+set a(0-11397) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#467 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59608 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11388 {}} {259 0 0-11396 {}}} SUCCS {{259 0 0-11398 {}}} CYCLES {}}
+set a(0-11398) {NAME ACC1:slc#135 TYPE READSLICE PAR 0-9373 XREFS 59609 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11397 {}}} SUCCS {{258 0 0-11411 {}}} CYCLES {}}
+set a(0-11399) {NAME ACC1-1:slc(acc#10.psp)#59 TYPE READSLICE PAR 0-9373 XREFS 59610 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11400 {}}} CYCLES {}}
+set a(0-11400) {NAME ACC1-1:exs#43 TYPE SIGNEXTEND PAR 0-9373 XREFS 59611 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11399 {}}} SUCCS {{259 0 0-11401 {}}} CYCLES {}}
+set a(0-11401) {NAME ACC1:conc#1390 TYPE CONCATENATE PAR 0-9373 XREFS 59612 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11400 {}}} SUCCS {{258 0 0-11409 {}}} CYCLES {}}
+set a(0-11402) {NAME ACC1-1:slc(acc#10.psp)#58 TYPE READSLICE PAR 0-9373 XREFS 59613 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11403 {}}} CYCLES {}}
+set a(0-11403) {NAME ACC1-1:exs#44 TYPE SIGNEXTEND PAR 0-9373 XREFS 59614 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11402 {}}} SUCCS {{258 0 0-11408 {}}} CYCLES {}}
+set a(0-11404) {NAME ACC1-1:slc(acc.imod#23) TYPE READSLICE PAR 0-9373 XREFS 59615 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9683 {}}} SUCCS {{258 0 0-11407 {}}} CYCLES {}}
+set a(0-11405) {NAME ACC1-1:slc(acc.idiv#5)#44 TYPE READSLICE PAR 0-9373 XREFS 59616 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6088549249999999} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-11406 {}}} CYCLES {}}
+set a(0-11406) {NAME ACC1-1:not#187 TYPE NOT PAR 0-9373 XREFS 59617 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11405 {}}} SUCCS {{259 0 0-11407 {}}} CYCLES {}}
+set a(0-11407) {NAME ACC1-1:nand#5 TYPE NAND PAR 0-9373 XREFS 59618 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11404 {}} {259 0 0-11406 {}}} SUCCS {{259 0 0-11408 {}}} CYCLES {}}
+set a(0-11408) {NAME ACC1:conc#1391 TYPE CONCATENATE PAR 0-9373 XREFS 59619 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11403 {}} {259 0 0-11407 {}}} SUCCS {{259 0 0-11409 {}}} CYCLES {}}
+set a(0-11409) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#466 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59620 LOC {1 0.3836787 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11401 {}} {259 0 0-11408 {}}} SUCCS {{259 0 0-11410 {}}} CYCLES {}}
+set a(0-11410) {NAME ACC1:slc#134 TYPE READSLICE PAR 0-9373 XREFS 59621 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11409 {}}} SUCCS {{259 0 0-11411 {}}} CYCLES {}}
+set a(0-11411) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#544 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59622 LOC {1 0.43123487499999996 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11398 {}} {259 0 0-11410 {}}} SUCCS {{258 0 0-11431 {}}} CYCLES {}}
+set a(0-11412) {NAME ACC1-1:slc(acc#10.psp)#57 TYPE READSLICE PAR 0-9373 XREFS 59623 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11413 {}}} CYCLES {}}
+set a(0-11413) {NAME ACC1-1:exs#42 TYPE SIGNEXTEND PAR 0-9373 XREFS 59624 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11412 {}}} SUCCS {{259 0 0-11414 {}}} CYCLES {}}
+set a(0-11414) {NAME ACC1:conc#1388 TYPE CONCATENATE PAR 0-9373 XREFS 59625 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11413 {}}} SUCCS {{258 0 0-11419 {}}} CYCLES {}}
+set a(0-11415) {NAME ACC1-1:slc(acc#10.psp)#56 TYPE READSLICE PAR 0-9373 XREFS 59626 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11416 {}}} CYCLES {}}
+set a(0-11416) {NAME ACC1-1:exs#47 TYPE SIGNEXTEND PAR 0-9373 XREFS 59627 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11415 {}}} SUCCS {{258 0 0-11418 {}}} CYCLES {}}
+set a(0-11417) {NAME ACC1:slc(acc.imod#42) TYPE READSLICE PAR 0-9373 XREFS 59628 LOC {1 0.356432775 1 0.44520917499999996 1 0.44520917499999996 1 0.6088549249999999} PREDS {{258 0 0-9674 {}}} SUCCS {{259 0 0-11418 {}}} CYCLES {}}
+set a(0-11418) {NAME ACC1:conc#1389 TYPE CONCATENATE PAR 0-9373 XREFS 59629 LOC {1 0.356432775 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11416 {}} {259 0 0-11417 {}}} SUCCS {{259 0 0-11419 {}}} CYCLES {}}
+set a(0-11419) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#465 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59630 LOC {1 0.356432775 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11414 {}} {259 0 0-11418 {}}} SUCCS {{259 0 0-11420 {}}} CYCLES {}}
+set a(0-11420) {NAME ACC1:slc#133 TYPE READSLICE PAR 0-9373 XREFS 59631 LOC {1 0.40398894999999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11419 {}}} SUCCS {{258 0 0-11430 {}}} CYCLES {}}
+set a(0-11421) {NAME ACC1-1:slc(acc#10.psp)#55 TYPE READSLICE PAR 0-9373 XREFS 59632 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11422 {}}} CYCLES {}}
+set a(0-11422) {NAME ACC1-1:exs#45 TYPE SIGNEXTEND PAR 0-9373 XREFS 59633 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11421 {}}} SUCCS {{259 0 0-11423 {}}} CYCLES {}}
+set a(0-11423) {NAME ACC1:conc#1386 TYPE CONCATENATE PAR 0-9373 XREFS 59634 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11422 {}}} SUCCS {{258 0 0-11428 {}}} CYCLES {}}
+set a(0-11424) {NAME ACC1-1:slc(acc#10.psp)#54 TYPE READSLICE PAR 0-9373 XREFS 59635 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11425 {}}} CYCLES {}}
+set a(0-11425) {NAME ACC1-1:exs#46 TYPE SIGNEXTEND PAR 0-9373 XREFS 59636 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11424 {}}} SUCCS {{258 0 0-11427 {}}} CYCLES {}}
+set a(0-11426) {NAME ACC1:slc(ACC1-1:acc#208.psp)#5 TYPE READSLICE PAR 0-9373 XREFS 59637 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.6088549249999999} PREDS {{258 0 0-9656 {}}} SUCCS {{259 0 0-11427 {}}} CYCLES {}}
+set a(0-11427) {NAME ACC1:conc#1387 TYPE CONCATENATE PAR 0-9373 XREFS 59638 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11425 {}} {259 0 0-11426 {}}} SUCCS {{259 0 0-11428 {}}} CYCLES {}}
+set a(0-11428) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#464 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59639 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11423 {}} {259 0 0-11427 {}}} SUCCS {{259 0 0-11429 {}}} CYCLES {}}
+set a(0-11429) {NAME ACC1:slc#132 TYPE READSLICE PAR 0-9373 XREFS 59640 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11428 {}}} SUCCS {{259 0 0-11430 {}}} CYCLES {}}
+set a(0-11430) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#543 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59641 LOC {1 0.40398894999999996 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11420 {}} {259 0 0-11429 {}}} SUCCS {{259 0 0-11431 {}}} CYCLES {}}
+set a(0-11431) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#587 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59642 LOC {1 0.47879105 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-11411 {}} {259 0 0-11430 {}}} SUCCS {{258 0 0-11474 {}}} CYCLES {}}
+set a(0-11432) {NAME ACC1-1:slc(acc#10.psp)#68 TYPE READSLICE PAR 0-9373 XREFS 59643 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11433 {}}} CYCLES {}}
+set a(0-11433) {NAME ACC1-1:exs#51 TYPE SIGNEXTEND PAR 0-9373 XREFS 59644 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11432 {}}} SUCCS {{259 0 0-11434 {}}} CYCLES {}}
+set a(0-11434) {NAME ACC1:conc#1384 TYPE CONCATENATE PAR 0-9373 XREFS 59645 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11433 {}}} SUCCS {{258 0 0-11439 {}}} CYCLES {}}
+set a(0-11435) {NAME ACC1-1:slc(acc#10.psp)#71 TYPE READSLICE PAR 0-9373 XREFS 59646 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11436 {}}} CYCLES {}}
+set a(0-11436) {NAME ACC1-1:exs#1034 TYPE SIGNEXTEND PAR 0-9373 XREFS 59647 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11435 {}}} SUCCS {{258 0 0-11438 {}}} CYCLES {}}
+set a(0-11437) {NAME ACC1:slc(ACC1-1:acc#208.psp)#4 TYPE READSLICE PAR 0-9373 XREFS 59648 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.6088549249999999} PREDS {{258 0 0-9656 {}}} SUCCS {{259 0 0-11438 {}}} CYCLES {}}
+set a(0-11438) {NAME ACC1:conc#1385 TYPE CONCATENATE PAR 0-9373 XREFS 59649 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11436 {}} {259 0 0-11437 {}}} SUCCS {{259 0 0-11439 {}}} CYCLES {}}
+set a(0-11439) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#463 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59650 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11434 {}} {259 0 0-11438 {}}} SUCCS {{259 0 0-11440 {}}} CYCLES {}}
+set a(0-11440) {NAME ACC1:slc#131 TYPE READSLICE PAR 0-9373 XREFS 59651 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11439 {}}} SUCCS {{258 0 0-11450 {}}} CYCLES {}}
+set a(0-11441) {NAME ACC1-1:slc(acc#10.psp)#70 TYPE READSLICE PAR 0-9373 XREFS 59652 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11442 {}}} CYCLES {}}
+set a(0-11442) {NAME ACC1-1:exs#49 TYPE SIGNEXTEND PAR 0-9373 XREFS 59653 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11441 {}}} SUCCS {{259 0 0-11443 {}}} CYCLES {}}
+set a(0-11443) {NAME ACC1:conc#1382 TYPE CONCATENATE PAR 0-9373 XREFS 59654 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11442 {}}} SUCCS {{258 0 0-11448 {}}} CYCLES {}}
+set a(0-11444) {NAME ACC1-1:slc(acc#10.psp)#69 TYPE READSLICE PAR 0-9373 XREFS 59655 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11445 {}}} CYCLES {}}
+set a(0-11445) {NAME ACC1-1:exs#50 TYPE SIGNEXTEND PAR 0-9373 XREFS 59656 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11444 {}}} SUCCS {{258 0 0-11447 {}}} CYCLES {}}
+set a(0-11446) {NAME ACC1:slc(ACC1-1:acc#208.psp) TYPE READSLICE PAR 0-9373 XREFS 59657 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.6088549249999999} PREDS {{258 0 0-9656 {}}} SUCCS {{259 0 0-11447 {}}} CYCLES {}}
+set a(0-11447) {NAME ACC1:conc#1383 TYPE CONCATENATE PAR 0-9373 XREFS 59658 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11445 {}} {259 0 0-11446 {}}} SUCCS {{259 0 0-11448 {}}} CYCLES {}}
+set a(0-11448) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#462 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59659 LOC {1 0.267931 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11443 {}} {259 0 0-11447 {}}} SUCCS {{259 0 0-11449 {}}} CYCLES {}}
+set a(0-11449) {NAME ACC1:slc#130 TYPE READSLICE PAR 0-9373 XREFS 59660 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11448 {}}} SUCCS {{259 0 0-11450 {}}} CYCLES {}}
+set a(0-11450) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#542 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59661 LOC {1 0.315487175 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11440 {}} {259 0 0-11449 {}}} SUCCS {{258 0 0-11473 {}}} CYCLES {}}
+set a(0-11451) {NAME ACC1-1:slc(acc.idiv#5)#9 TYPE READSLICE PAR 0-9373 XREFS 59662 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6088549249999999} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-11452 {}}} CYCLES {}}
+set a(0-11452) {NAME ACC1-1:exs#94 TYPE SIGNEXTEND PAR 0-9373 XREFS 59663 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11451 {}}} SUCCS {{259 0 0-11453 {}}} CYCLES {}}
+set a(0-11453) {NAME ACC1:conc#1378 TYPE CONCATENATE PAR 0-9373 XREFS 59664 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11452 {}}} SUCCS {{258 0 0-11461 {}}} CYCLES {}}
+set a(0-11454) {NAME ACC1-1:slc(acc.idiv#5)#11 TYPE READSLICE PAR 0-9373 XREFS 59665 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6088549249999999} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-11455 {}}} CYCLES {}}
+set a(0-11455) {NAME ACC1-1:exs#95 TYPE SIGNEXTEND PAR 0-9373 XREFS 59666 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11454 {}}} SUCCS {{258 0 0-11460 {}}} CYCLES {}}
+set a(0-11456) {NAME ACC1-1:slc(acc.imod#11) TYPE READSLICE PAR 0-9373 XREFS 59667 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-9535 {}}} SUCCS {{258 0 0-11459 {}}} CYCLES {}}
+set a(0-11457) {NAME ACC1-1:slc(acc#10.psp)#50 TYPE READSLICE PAR 0-9373 XREFS 59668 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.6088549249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11458 {}}} CYCLES {}}
+set a(0-11458) {NAME ACC1-1:not#91 TYPE NOT PAR 0-9373 XREFS 59669 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11457 {}}} SUCCS {{259 0 0-11459 {}}} CYCLES {}}
+set a(0-11459) {NAME ACC1-1:nand#2 TYPE NAND PAR 0-9373 XREFS 59670 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11456 {}} {259 0 0-11458 {}}} SUCCS {{259 0 0-11460 {}}} CYCLES {}}
+set a(0-11460) {NAME ACC1:conc#1379 TYPE CONCATENATE PAR 0-9373 XREFS 59671 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11455 {}} {259 0 0-11459 {}}} SUCCS {{259 0 0-11461 {}}} CYCLES {}}
+set a(0-11461) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#460 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59672 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11453 {}} {259 0 0-11460 {}}} SUCCS {{259 0 0-11462 {}}} CYCLES {}}
+set a(0-11462) {NAME ACC1:slc#128 TYPE READSLICE PAR 0-9373 XREFS 59673 LOC {1 0.42196819999999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11461 {}}} SUCCS {{258 0 0-11472 {}}} CYCLES {}}
+set a(0-11463) {NAME ACC1-1:slc(acc.idiv#5)#1 TYPE READSLICE PAR 0-9373 XREFS 59674 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6088549249999999} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-11464 {}}} CYCLES {}}
+set a(0-11464) {NAME ACC1-1:exs#90 TYPE SIGNEXTEND PAR 0-9373 XREFS 59675 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11463 {}}} SUCCS {{259 0 0-11465 {}}} CYCLES {}}
+set a(0-11465) {NAME ACC1:conc#1376 TYPE CONCATENATE PAR 0-9373 XREFS 59676 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11464 {}}} SUCCS {{258 0 0-11470 {}}} CYCLES {}}
+set a(0-11466) {NAME ACC1-1:slc(acc.idiv#5)#3 TYPE READSLICE PAR 0-9373 XREFS 59677 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.6088549249999999} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-11467 {}}} CYCLES {}}
+set a(0-11467) {NAME ACC1-1:exs#91 TYPE SIGNEXTEND PAR 0-9373 XREFS 59678 LOC {1 0.14655495 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{259 0 0-11466 {}}} SUCCS {{258 0 0-11469 {}}} CYCLES {}}
+set a(0-11468) {NAME ACC1:slc(acc.imod#34) TYPE READSLICE PAR 0-9373 XREFS 59679 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.6088549249999999} PREDS {{258 0 0-9526 {}}} SUCCS {{259 0 0-11469 {}}} CYCLES {}}
+set a(0-11469) {NAME ACC1:conc#1377 TYPE CONCATENATE PAR 0-9373 XREFS 59680 LOC {1 0.3471661 1 0.47245509999999996 1 0.47245509999999996 1 0.6088549249999999} PREDS {{258 0 0-11467 {}} {259 0 0-11468 {}}} SUCCS {{259 0 0-11470 {}}} CYCLES {}}
+set a(0-11470) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#459 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59681 LOC {1 0.3471661 1 0.47245509999999996 1 0.47245509999999996 1 0.5200112270708271 1 0.6564110520708271} PREDS {{258 0 0-11465 {}} {259 0 0-11469 {}}} SUCCS {{259 0 0-11471 {}}} CYCLES {}}
+set a(0-11471) {NAME ACC1:slc#127 TYPE READSLICE PAR 0-9373 XREFS 59682 LOC {1 0.39472227499999996 1 0.520011275 1 0.520011275 1 0.6564111} PREDS {{259 0 0-11470 {}}} SUCCS {{259 0 0-11472 {}}} CYCLES {}}
+set a(0-11472) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#541 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59683 LOC {1 0.42196819999999996 1 0.520011275 1 0.520011275 1 0.5675674020708271 1 0.7039672270708272} PREDS {{258 0 0-11462 {}} {259 0 0-11471 {}}} SUCCS {{259 0 0-11473 {}}} CYCLES {}}
+set a(0-11473) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#586 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59684 LOC {1 0.469524375 1 0.56756745 1 0.56756745 1 0.6209144701789504 1 0.7573142951789504} PREDS {{258 0 0-11450 {}} {259 0 0-11472 {}}} SUCCS {{259 0 0-11474 {}}} CYCLES {}}
+set a(0-11474) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#608 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-9373 XREFS 59685 LOC {1 0.532138125 1 0.620914525 1 0.620914525 1 0.679514234496936 1 0.815914059496936} PREDS {{258 0 0-11431 {}} {259 0 0-11473 {}}} SUCCS {{259 0 0-11475 {}}} CYCLES {}}
+set a(0-11475) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 10 NAME ACC1:acc#624 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-9373 XREFS 59686 LOC {1 0.590737875 1 0.679514275 1 0.679514275 1 0.7430262484103024 1 0.8794260734103024} PREDS {{258 0 0-11385 {}} {259 0 0-11474 {}}} SUCCS {{259 0 0-11476 {}}} CYCLES {}}
+set a(0-11476) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 9 NAME ACC1:acc#637 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-9373 XREFS 59687 LOC {1 0.6542498999999999 1 0.7430262999999999 1 0.7430262999999999 1 0.8112156129329678 1 0.9476154379329679} PREDS {{258 0 0-11299 {}} {259 0 0-11475 {}}} SUCCS {{259 0 0-11477 {}}} CYCLES {}}
+set a(0-11477) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#645 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-9373 XREFS 59688 LOC {1 0.7224392749999999 1 0.8112156749999999 1 0.8112156749999999 1 0.8636001277684257 1 0.9999999527684257} PREDS {{258 0 0-11194 {}} {259 0 0-11476 {}}} SUCCS {{259 0 0-11478 {}}} CYCLES {}}
+set a(0-11478) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,12) AREA_SCORE 11.00 QUANTITY 4 NAME ACC1:acc#650 TYPE ACCU DELAY {0.98 ns} LIBRARY_DELAY {0.98 ns} PAR 0-9373 XREFS 59689 LOC {1 0.774823775 1 0.863600175 1 0.863600175 1 0.9246291533364113 2 0.06498865333641131} PREDS {{258 0 0-11096 {}} {259 0 0-11477 {}}} SUCCS {{258 0 0-11635 {}}} CYCLES {}}
+set a(0-11479) {NAME ACC1:slc(acc#20.psp#1)#39 TYPE READSLICE PAR 0-9373 XREFS 59690 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.8997363749999999} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-11484 {}}} CYCLES {}}
+set a(0-11480) {NAME ACC1:slc(ACC1:acc#227.psp)#65 TYPE READSLICE PAR 0-9373 XREFS 59691 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.8997363749999999} PREDS {{258 0 0-9918 {}}} SUCCS {{258 0 0-11484 {}}} CYCLES {}}
+set a(0-11481) {NAME ACC1:slc(ACC1:acc#224.psp)#56 TYPE READSLICE PAR 0-9373 XREFS 59692 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.8997363749999999} PREDS {{258 0 0-9993 {}}} SUCCS {{258 0 0-11484 {}}} CYCLES {}}
+set a(0-11482) {NAME ACC1-3:slc(acc#10.psp)#54 TYPE READSLICE PAR 0-9373 XREFS 59693 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.8997363749999999} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-11483 {}}} CYCLES {}}
+set a(0-11483) {NAME ACC1-3:exs#46 TYPE SIGNEXTEND PAR 0-9373 XREFS 59694 LOC {1 0.14655495 1 0.7676069999999999 1 0.7676069999999999 1 0.8997363749999999} PREDS {{259 0 0-11482 {}}} SUCCS {{259 0 0-11484 {}}} CYCLES {}}
+set a(0-11484) {NAME ACC1:conc#1126 TYPE CONCATENATE PAR 0-9373 XREFS 59695 LOC {1 0.14655495 1 0.7676069999999999 1 0.7676069999999999 1 0.8997363749999999} PREDS {{258 0 0-11481 {}} {258 0 0-11480 {}} {258 0 0-11479 {}} {259 0 0-11483 {}}} SUCCS {{258 0 0-11532 {}}} CYCLES {}}
+set a(0-11485) {NAME ACC1:slc(acc#5.psp#2)#37 TYPE READSLICE PAR 0-9373 XREFS 59696 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11486 {}}} CYCLES {}}
+set a(0-11486) {NAME ACC1-2:exs#20 TYPE SIGNEXTEND PAR 0-9373 XREFS 59697 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11485 {}}} SUCCS {{258 0 0-11489 {}}} CYCLES {}}
+set a(0-11487) {NAME ACC1:slc(acc#5.psp#2)#38 TYPE READSLICE PAR 0-9373 XREFS 59698 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11488 {}}} CYCLES {}}
+set a(0-11488) {NAME ACC1-2:exs#21 TYPE SIGNEXTEND PAR 0-9373 XREFS 59699 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11487 {}}} SUCCS {{259 0 0-11489 {}}} CYCLES {}}
+set a(0-11489) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#517 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59700 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-11486 {}} {259 0 0-11488 {}}} SUCCS {{258 0 0-11495 {}}} CYCLES {}}
+set a(0-11490) {NAME ACC1:slc(acc#5.psp#2)#39 TYPE READSLICE PAR 0-9373 XREFS 59701 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11491 {}}} CYCLES {}}
+set a(0-11491) {NAME ACC1-2:exs#25 TYPE SIGNEXTEND PAR 0-9373 XREFS 59702 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11490 {}}} SUCCS {{258 0 0-11494 {}}} CYCLES {}}
+set a(0-11492) {NAME ACC1:slc(acc#5.psp#2)#40 TYPE READSLICE PAR 0-9373 XREFS 59703 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11493 {}}} CYCLES {}}
+set a(0-11493) {NAME ACC1-2:exs#26 TYPE SIGNEXTEND PAR 0-9373 XREFS 59704 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11492 {}}} SUCCS {{259 0 0-11494 {}}} CYCLES {}}
+set a(0-11494) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#516 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59705 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-11491 {}} {259 0 0-11493 {}}} SUCCS {{259 0 0-11495 {}}} CYCLES {}}
+set a(0-11495) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#568 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59706 LOC {1 0.187338 1 0.608104 1 0.608104 1 0.6556601270708271 1 0.7877895020708271} PREDS {{258 0 0-11489 {}} {259 0 0-11494 {}}} SUCCS {{258 0 0-11507 {}}} CYCLES {}}
+set a(0-11496) {NAME ACC1:slc(acc#5.psp#2)#41 TYPE READSLICE PAR 0-9373 XREFS 59707 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11497 {}}} CYCLES {}}
+set a(0-11497) {NAME ACC1-2:exs#24 TYPE SIGNEXTEND PAR 0-9373 XREFS 59708 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11496 {}}} SUCCS {{258 0 0-11500 {}}} CYCLES {}}
+set a(0-11498) {NAME ACC1:slc(acc#5.psp#2)#42 TYPE READSLICE PAR 0-9373 XREFS 59709 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11499 {}}} CYCLES {}}
+set a(0-11499) {NAME ACC1-2:exs#29 TYPE SIGNEXTEND PAR 0-9373 XREFS 59710 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11498 {}}} SUCCS {{259 0 0-11500 {}}} CYCLES {}}
+set a(0-11500) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#515 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59711 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-11497 {}} {259 0 0-11499 {}}} SUCCS {{258 0 0-11506 {}}} CYCLES {}}
+set a(0-11501) {NAME ACC1:slc(acc#5.psp#2)#43 TYPE READSLICE PAR 0-9373 XREFS 59712 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11502 {}}} CYCLES {}}
+set a(0-11502) {NAME ACC1-2:exs#27 TYPE SIGNEXTEND PAR 0-9373 XREFS 59713 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11501 {}}} SUCCS {{258 0 0-11505 {}}} CYCLES {}}
+set a(0-11503) {NAME ACC1:slc(acc#5.psp#2)#44 TYPE READSLICE PAR 0-9373 XREFS 59714 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11504 {}}} CYCLES {}}
+set a(0-11504) {NAME ACC1-2:exs#28 TYPE SIGNEXTEND PAR 0-9373 XREFS 59715 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11503 {}}} SUCCS {{259 0 0-11505 {}}} CYCLES {}}
+set a(0-11505) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#514 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59716 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-11502 {}} {259 0 0-11504 {}}} SUCCS {{259 0 0-11506 {}}} CYCLES {}}
+set a(0-11506) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#567 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59717 LOC {1 0.187338 1 0.608104 1 0.608104 1 0.6556601270708271 1 0.7877895020708271} PREDS {{258 0 0-11500 {}} {259 0 0-11505 {}}} SUCCS {{259 0 0-11507 {}}} CYCLES {}}
+set a(0-11507) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#599 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59718 LOC {1 0.23489417499999998 1 0.655660175 1 0.655660175 1 0.7090071951789505 1 0.8411365701789504} PREDS {{258 0 0-11495 {}} {259 0 0-11506 {}}} SUCCS {{258 0 0-11531 {}}} CYCLES {}}
+set a(0-11508) {NAME ACC1:slc(acc#5.psp#2)#50 TYPE READSLICE PAR 0-9373 XREFS 59719 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11509 {}}} CYCLES {}}
+set a(0-11509) {NAME ACC1-2:exs#33 TYPE SIGNEXTEND PAR 0-9373 XREFS 59720 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11508 {}}} SUCCS {{258 0 0-11512 {}}} CYCLES {}}
+set a(0-11510) {NAME ACC1:slc(acc#5.psp#2)#54 TYPE READSLICE PAR 0-9373 XREFS 59721 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11511 {}}} CYCLES {}}
+set a(0-11511) {NAME ACC1-2:exs#1031 TYPE SIGNEXTEND PAR 0-9373 XREFS 59722 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11510 {}}} SUCCS {{259 0 0-11512 {}}} CYCLES {}}
+set a(0-11512) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#513 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59723 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-11509 {}} {259 0 0-11511 {}}} SUCCS {{258 0 0-11518 {}}} CYCLES {}}
+set a(0-11513) {NAME ACC1:slc(acc#5.psp#2)#59 TYPE READSLICE PAR 0-9373 XREFS 59724 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11514 {}}} CYCLES {}}
+set a(0-11514) {NAME ACC1-2:exs#31 TYPE SIGNEXTEND PAR 0-9373 XREFS 59725 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11513 {}}} SUCCS {{258 0 0-11517 {}}} CYCLES {}}
+set a(0-11515) {NAME ACC1:slc(acc#5.psp#2)#62 TYPE READSLICE PAR 0-9373 XREFS 59726 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6994503249999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11516 {}}} CYCLES {}}
+set a(0-11516) {NAME ACC1-2:exs#32 TYPE SIGNEXTEND PAR 0-9373 XREFS 59727 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11515 {}}} SUCCS {{259 0 0-11517 {}}} CYCLES {}}
+set a(0-11517) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#512 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59728 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-11514 {}} {259 0 0-11516 {}}} SUCCS {{259 0 0-11518 {}}} CYCLES {}}
+set a(0-11518) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#566 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59729 LOC {1 0.187338 1 0.608104 1 0.608104 1 0.6556601270708271 1 0.7877895020708271} PREDS {{258 0 0-11512 {}} {259 0 0-11517 {}}} SUCCS {{258 0 0-11530 {}}} CYCLES {}}
+set a(0-11519) {NAME ACC1-3:slc(acc.idiv#1)#27 TYPE READSLICE PAR 0-9373 XREFS 59730 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6994503249999999} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-11520 {}}} CYCLES {}}
+set a(0-11520) {NAME ACC1-3:exs#31 TYPE SIGNEXTEND PAR 0-9373 XREFS 59731 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11519 {}}} SUCCS {{258 0 0-11523 {}}} CYCLES {}}
+set a(0-11521) {NAME ACC1-3:slc(acc.idiv#1)#29 TYPE READSLICE PAR 0-9373 XREFS 59732 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.6994503249999999} PREDS {{258 0 0-9918 {}}} SUCCS {{259 0 0-11522 {}}} CYCLES {}}
+set a(0-11522) {NAME ACC1-3:exs#32 TYPE SIGNEXTEND PAR 0-9373 XREFS 59733 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11521 {}}} SUCCS {{259 0 0-11523 {}}} CYCLES {}}
+set a(0-11523) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#511 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59734 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-11520 {}} {259 0 0-11522 {}}} SUCCS {{258 0 0-11529 {}}} CYCLES {}}
+set a(0-11524) {NAME ACC1-3:slc(acc.idiv)#33 TYPE READSLICE PAR 0-9373 XREFS 59735 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6994503249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11525 {}}} CYCLES {}}
+set a(0-11525) {NAME ACC1-3:exs#16 TYPE SIGNEXTEND PAR 0-9373 XREFS 59736 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11524 {}}} SUCCS {{258 0 0-11528 {}}} CYCLES {}}
+set a(0-11526) {NAME ACC1-3:slc(acc.idiv)#35 TYPE READSLICE PAR 0-9373 XREFS 59737 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.6994503249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11527 {}}} CYCLES {}}
+set a(0-11527) {NAME ACC1-3:exs#17 TYPE SIGNEXTEND PAR 0-9373 XREFS 59738 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6994503249999999} PREDS {{259 0 0-11526 {}}} SUCCS {{259 0 0-11528 {}}} CYCLES {}}
+set a(0-11528) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 71 NAME ACC1:acc#510 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-9373 XREFS 59739 LOC {1 0.14655495 1 0.5673209499999999 1 0.5673209499999999 1 0.6081039600894752 1 0.7402333350894752} PREDS {{258 0 0-11525 {}} {259 0 0-11527 {}}} SUCCS {{259 0 0-11529 {}}} CYCLES {}}
+set a(0-11529) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#565 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59740 LOC {1 0.187338 1 0.608104 1 0.608104 1 0.6556601270708271 1 0.7877895020708271} PREDS {{258 0 0-11523 {}} {259 0 0-11528 {}}} SUCCS {{259 0 0-11530 {}}} CYCLES {}}
+set a(0-11530) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#598 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59741 LOC {1 0.23489417499999998 1 0.655660175 1 0.655660175 1 0.7090071951789505 1 0.8411365701789504} PREDS {{258 0 0-11518 {}} {259 0 0-11529 {}}} SUCCS {{259 0 0-11531 {}}} CYCLES {}}
+set a(0-11531) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#614 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-9373 XREFS 59742 LOC {1 0.28824125 1 0.70900725 1 0.70900725 1 0.767606959496936 1 0.899736334496936} PREDS {{258 0 0-11507 {}} {259 0 0-11530 {}}} SUCCS {{259 0 0-11532 {}}} CYCLES {}}
+set a(0-11532) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 6 NAME ACC1:acc#627 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-9373 XREFS 59743 LOC {1 0.346841 1 0.7676069999999999 1 0.7676069999999999 1 0.8154860629329679 1 0.9476154379329679} PREDS {{258 0 0-11484 {}} {259 0 0-11531 {}}} SUCCS {{258 0 0-11610 {}}} CYCLES {}}
+set a(0-11533) {NAME ACC1:slc(ACC1:acc#214.psp#1)#12 TYPE READSLICE PAR 0-9373 XREFS 59744 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.744910725} PREDS {{258 0 0-10030 {}}} SUCCS {{259 0 0-11534 {}}} CYCLES {}}
+set a(0-11534) {NAME ACC1:not#368 TYPE NOT PAR 0-9373 XREFS 59745 LOC {1 0.258664325 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-11533 {}}} SUCCS {{258 0 0-11539 {}}} CYCLES {}}
+set a(0-11535) {NAME ACC1:slc(acc.imod#18)#17 TYPE READSLICE PAR 0-9373 XREFS 59746 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.744910725} PREDS {{258 0 0-10123 {}}} SUCCS {{259 0 0-11536 {}}} CYCLES {}}
+set a(0-11536) {NAME ACC1:not#369 TYPE NOT PAR 0-9373 XREFS 59747 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-11535 {}}} SUCCS {{258 0 0-11539 {}}} CYCLES {}}
+set a(0-11537) {NAME ACC1:slc(acc.imod#26)#1 TYPE READSLICE PAR 0-9373 XREFS 59748 LOC {1 0.356432775 1 0.38069092499999996 1 0.38069092499999996 1 0.744910725} PREDS {{258 0 0-9444 {}}} SUCCS {{259 0 0-11538 {}}} CYCLES {}}
+set a(0-11538) {NAME ACC1:not#370 TYPE NOT PAR 0-9373 XREFS 59749 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-11537 {}}} SUCCS {{259 0 0-11539 {}}} CYCLES {}}
+set a(0-11539) {NAME ACC1:conc#1098 TYPE CONCATENATE PAR 0-9373 XREFS 59750 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{258 0 0-11536 {}} {258 0 0-11534 {}} {259 0 0-11538 {}}} SUCCS {{258 0 0-11545 {}}} CYCLES {}}
+set a(0-11540) {NAME ACC1:slc(ACC1-2:acc#212.psp)#12 TYPE READSLICE PAR 0-9373 XREFS 59751 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.744910725} PREDS {{258 0 0-9732 {}}} SUCCS {{259 0 0-11541 {}}} CYCLES {}}
+set a(0-11541) {NAME ACC1:not#371 TYPE NOT PAR 0-9373 XREFS 59752 LOC {1 0.258664325 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-11540 {}}} SUCCS {{258 0 0-11544 {}}} CYCLES {}}
+set a(0-11542) {NAME ACC1:slc(acc.imod#2)#17 TYPE READSLICE PAR 0-9373 XREFS 59753 LOC {1 0.356432775 1 0.40289064999999996 1 0.40289064999999996 1 0.744910725} PREDS {{258 0 0-9897 {}}} SUCCS {{259 0 0-11543 {}}} CYCLES {}}
+set a(0-11543) {NAME ACC1:not#372 TYPE NOT PAR 0-9373 XREFS 59754 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-11542 {}}} SUCCS {{259 0 0-11544 {}}} CYCLES {}}
+set a(0-11544) {NAME ACC1:conc#1099 TYPE CONCATENATE PAR 0-9373 XREFS 59755 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{258 0 0-11541 {}} {259 0 0-11543 {}}} SUCCS {{259 0 0-11545 {}}} CYCLES {}}
+set a(0-11545) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#523 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59756 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.6603374770708271 1 0.7924668520708271} PREDS {{258 0 0-11539 {}} {259 0 0-11544 {}}} SUCCS {{258 0 0-11557 {}}} CYCLES {}}
+set a(0-11546) {NAME ACC1:slc(ACC1-2:acc#208.psp)#12 TYPE READSLICE PAR 0-9373 XREFS 59757 LOC {1 0.258664325 1 0.314388875 1 0.314388875 1 0.744910725} PREDS {{258 0 0-9804 {}}} SUCCS {{259 0 0-11547 {}}} CYCLES {}}
+set a(0-11547) {NAME ACC1:not#373 TYPE NOT PAR 0-9373 XREFS 59758 LOC {1 0.258664325 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-11546 {}}} SUCCS {{258 0 0-11550 {}}} CYCLES {}}
+set a(0-11548) {NAME ACC1:slc(acc.imod#10)#16 TYPE READSLICE PAR 0-9373 XREFS 59759 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.744910725} PREDS {{258 0 0-10048 {}}} SUCCS {{259 0 0-11549 {}}} CYCLES {}}
+set a(0-11549) {NAME ACC1:not#374 TYPE NOT PAR 0-9373 XREFS 59760 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-11548 {}}} SUCCS {{259 0 0-11550 {}}} CYCLES {}}
+set a(0-11550) {NAME ACC1:conc#1100 TYPE CONCATENATE PAR 0-9373 XREFS 59761 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{258 0 0-11547 {}} {259 0 0-11549 {}}} SUCCS {{258 0 0-11556 {}}} CYCLES {}}
+set a(0-11551) {NAME ACC1:slc(ACC1-3:acc#212.psp)#15 TYPE READSLICE PAR 0-9373 XREFS 59762 LOC {1 0.267931 1 0.34163479999999996 1 0.34163479999999996 1 0.744910725} PREDS {{258 0 0-9958 {}}} SUCCS {{259 0 0-11552 {}}} CYCLES {}}
+set a(0-11552) {NAME ACC1:not#375 TYPE NOT PAR 0-9373 XREFS 59763 LOC {1 0.267931 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-11551 {}}} SUCCS {{258 0 0-11555 {}}} CYCLES {}}
+set a(0-11553) {NAME ACC1:slc(acc.imod#31)#4 TYPE READSLICE PAR 0-9373 XREFS 59764 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.744910725} PREDS {{258 0 0-9750 {}}} SUCCS {{259 0 0-11554 {}}} CYCLES {}}
+set a(0-11554) {NAME ACC1:not#376 TYPE NOT PAR 0-9373 XREFS 59765 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-11553 {}}} SUCCS {{259 0 0-11555 {}}} CYCLES {}}
+set a(0-11555) {NAME ACC1:conc#1101 TYPE CONCATENATE PAR 0-9373 XREFS 59766 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{258 0 0-11552 {}} {259 0 0-11554 {}}} SUCCS {{259 0 0-11556 {}}} CYCLES {}}
+set a(0-11556) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#522 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59767 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.6603374770708271 1 0.7924668520708271} PREDS {{258 0 0-11550 {}} {259 0 0-11555 {}}} SUCCS {{259 0 0-11557 {}}} CYCLES {}}
+set a(0-11557) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#577 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59768 LOC {1 0.40398894999999996 1 0.660337525 1 0.660337525 1 0.7136845451789504 1 0.8458139201789505} PREDS {{258 0 0-11545 {}} {259 0 0-11556 {}}} SUCCS {{258 0 0-11577 {}}} CYCLES {}}
+set a(0-11558) {NAME ACC1:slc(ACC1:acc#214.psp#2)#6 TYPE READSLICE PAR 0-9373 XREFS 59769 LOC {1 0.258664325 1 0.3567074 1 0.3567074 1 0.744910725} PREDS {{258 0 0-9508 {}}} SUCCS {{259 0 0-11559 {}}} CYCLES {}}
+set a(0-11559) {NAME ACC1:not#377 TYPE NOT PAR 0-9373 XREFS 59770 LOC {1 0.258664325 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-11558 {}}} SUCCS {{258 0 0-11562 {}}} CYCLES {}}
+set a(0-11560) {NAME ACC1:slc(acc.imod#43)#4 TYPE READSLICE PAR 0-9373 XREFS 59771 LOC {1 0.3471661 1 0.40289064999999996 1 0.40289064999999996 1 0.744910725} PREDS {{258 0 0-9822 {}}} SUCCS {{259 0 0-11561 {}}} CYCLES {}}
+set a(0-11561) {NAME ACC1:not#378 TYPE NOT PAR 0-9373 XREFS 59772 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-11560 {}}} SUCCS {{259 0 0-11562 {}}} CYCLES {}}
+set a(0-11562) {NAME ACC1:conc#1102 TYPE CONCATENATE PAR 0-9373 XREFS 59773 LOC {1 0.3471661 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{258 0 0-11559 {}} {259 0 0-11561 {}}} SUCCS {{258 0 0-11568 {}}} CYCLES {}}
+set a(0-11563) {NAME ACC1:slc(ACC1-1:acc#208.psp)#6 TYPE READSLICE PAR 0-9373 XREFS 59774 LOC {1 0.267931 1 0.3567074 1 0.3567074 1 0.744910725} PREDS {{258 0 0-9656 {}}} SUCCS {{259 0 0-11564 {}}} CYCLES {}}
+set a(0-11564) {NAME ACC1:not#379 TYPE NOT PAR 0-9373 XREFS 59775 LOC {1 0.267931 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-11563 {}}} SUCCS {{258 0 0-11567 {}}} CYCLES {}}
+set a(0-11565) {NAME ACC1:slc(acc.imod#6)#17 TYPE READSLICE PAR 0-9373 XREFS 59776 LOC {1 0.356432775 1 0.43013657499999997 1 0.43013657499999997 1 0.744910725} PREDS {{258 0 0-9976 {}}} SUCCS {{259 0 0-11566 {}}} CYCLES {}}
+set a(0-11566) {NAME ACC1:not#380 TYPE NOT PAR 0-9373 XREFS 59777 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{259 0 0-11565 {}}} SUCCS {{259 0 0-11567 {}}} CYCLES {}}
+set a(0-11567) {NAME ACC1:conc#1103 TYPE CONCATENATE PAR 0-9373 XREFS 59778 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.744910725} PREDS {{258 0 0-11564 {}} {259 0 0-11566 {}}} SUCCS {{259 0 0-11568 {}}} CYCLES {}}
+set a(0-11568) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME ACC1:acc#521 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59779 LOC {1 0.356432775 1 0.61278135 1 0.61278135 1 0.6603374770708271 1 0.7924668520708271} PREDS {{258 0 0-11562 {}} {259 0 0-11567 {}}} SUCCS {{258 0 0-11576 {}}} CYCLES {}}
+set a(0-11569) {NAME ACC1:slc(ACC1:acc#210.psp#2)#3 TYPE READSLICE PAR 0-9373 XREFS 59780 LOC {1 0.267931 1 0.29218915 1 0.29218915 1 0.765220975} PREDS {{258 0 0-9426 {}}} SUCCS {{259 0 0-11570 {}}} CYCLES {}}
+set a(0-11570) {NAME ACC1:not#381 TYPE NOT PAR 0-9373 XREFS 59781 LOC {1 0.267931 1 0.6330916 1 0.6330916 1 0.765220975} PREDS {{259 0 0-11569 {}}} SUCCS {{258 0 0-11573 {}}} CYCLES {}}
+set a(0-11571) {NAME ACC1:slc(acc.imod#34)#2 TYPE READSLICE PAR 0-9373 XREFS 59782 LOC {1 0.3471661 1 0.44520917499999996 1 0.44520917499999996 1 0.765220975} PREDS {{258 0 0-9526 {}}} SUCCS {{259 0 0-11572 {}}} CYCLES {}}
+set a(0-11572) {NAME ACC1:not#382 TYPE NOT PAR 0-9373 XREFS 59783 LOC {1 0.3471661 1 0.6330916 1 0.6330916 1 0.765220975} PREDS {{259 0 0-11571 {}}} SUCCS {{259 0 0-11573 {}}} CYCLES {}}
+set a(0-11573) {NAME ACC1:conc#1104 TYPE CONCATENATE PAR 0-9373 XREFS 59784 LOC {1 0.3471661 1 0.6330916 1 0.6330916 1 0.765220975} PREDS {{258 0 0-11570 {}} {259 0 0-11572 {}}} SUCCS {{258 0 0-11575 {}}} CYCLES {}}
+set a(0-11574) {NAME ACC1:slc(ACC1:acc#221.psp) TYPE READSLICE PAR 0-9373 XREFS 59785 LOC {1 0.32918685 1 0.40289064999999996 1 0.40289064999999996 1 0.765220975} PREDS {{258 0 0-9969 {}}} SUCCS {{259 0 0-11575 {}}} CYCLES {}}
+set a(0-11575) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#520 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 59786 LOC {1 0.3471661 1 0.6330916 1 0.6330916 1 0.6603374770708271 1 0.7924668520708271} PREDS {{258 0 0-11573 {}} {259 0 0-11574 {}}} SUCCS {{259 0 0-11576 {}}} CYCLES {}}
+set a(0-11576) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME ACC1:acc#576 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59787 LOC {1 0.40398894999999996 1 0.660337525 1 0.660337525 1 0.7136845451789504 1 0.8458139201789505} PREDS {{258 0 0-11568 {}} {259 0 0-11575 {}}} SUCCS {{259 0 0-11577 {}}} CYCLES {}}
+set a(0-11577) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 13 NAME ACC1:acc#603 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-9373 XREFS 59788 LOC {1 0.457336025 1 0.7136846 1 0.7136846 1 0.772284309496936 1 0.904413684496936} PREDS {{258 0 0-11557 {}} {259 0 0-11576 {}}} SUCCS {{258 0 0-11609 {}}} CYCLES {}}
+set a(0-11578) {NAME ACC1:slc(ACC1:acc#221.psp#2) TYPE READSLICE PAR 0-9373 XREFS 59789 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.79230435} PREDS {{258 0 0-9743 {}}} SUCCS {{258 0 0-11581 {}}} CYCLES {}}
+set a(0-11579) {NAME ACC1:slc(acc#5.psp#2)#36 TYPE READSLICE PAR 0-9373 XREFS 59790 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.79230435} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11580 {}}} CYCLES {}}
+set a(0-11580) {NAME ACC1-2:exs#19 TYPE SIGNEXTEND PAR 0-9373 XREFS 59791 LOC {1 0.14655495 1 0.660174975 1 0.660174975 1 0.79230435} PREDS {{259 0 0-11579 {}}} SUCCS {{259 0 0-11581 {}}} CYCLES {}}
+set a(0-11581) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#518 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 59792 LOC {1 0.319920175 1 0.660174975 1 0.660174975 1 0.6806477350894753 1 0.8127771100894753} PREDS {{258 0 0-11578 {}} {259 0 0-11580 {}}} SUCCS {{258 0 0-11586 {}}} CYCLES {}}
+set a(0-11582) {NAME ACC1:slc(ACC1:acc#219.psp#2) TYPE READSLICE PAR 0-9373 XREFS 59793 LOC {1 0.319920175 1 0.37564472499999996 1 0.37564472499999996 1 0.79230435} PREDS {{258 0 0-9815 {}}} SUCCS {{258 0 0-11585 {}}} CYCLES {}}
+set a(0-11583) {NAME ACC1:slc(acc#25.psp#2)#27 TYPE READSLICE PAR 0-9373 XREFS 59794 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.79230435} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11584 {}}} CYCLES {}}
+set a(0-11584) {NAME ACC1-2:exs#107 TYPE SIGNEXTEND PAR 0-9373 XREFS 59795 LOC {1 0.14655495 1 0.660174975 1 0.660174975 1 0.79230435} PREDS {{259 0 0-11583 {}}} SUCCS {{259 0 0-11585 {}}} CYCLES {}}
+set a(0-11585) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#490 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 59796 LOC {1 0.319920175 1 0.660174975 1 0.660174975 1 0.6806477350894753 1 0.8127771100894753} PREDS {{258 0 0-11582 {}} {259 0 0-11584 {}}} SUCCS {{259 0 0-11586 {}}} CYCLES {}}
+set a(0-11586) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#575 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 59797 LOC {1 0.340392975 1 0.680647775 1 0.680647775 1 0.7238396701789505 1 0.8559690451789504} PREDS {{258 0 0-11581 {}} {259 0 0-11585 {}}} SUCCS {{258 0 0-11608 {}}} CYCLES {}}
+set a(0-11587) {NAME ACC1-3:slc(acc.idiv)#15 TYPE READSLICE PAR 0-9373 XREFS 59798 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.7855312249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11588 {}}} CYCLES {}}
+set a(0-11588) {NAME ACC1-3:exs#7 TYPE SIGNEXTEND PAR 0-9373 XREFS 59799 LOC {1 0.14655495 1 0.65340185 1 0.65340185 1 0.7855312249999999} PREDS {{259 0 0-11587 {}}} SUCCS {{259 0 0-11589 {}}} CYCLES {}}
+set a(0-11589) {NAME ACC1:conc#1400 TYPE CONCATENATE PAR 0-9373 XREFS 59800 LOC {1 0.14655495 1 0.65340185 1 0.65340185 1 0.7855312249999999} PREDS {{259 0 0-11588 {}}} SUCCS {{258 0 0-11593 {}}} CYCLES {}}
+set a(0-11590) {NAME ACC1:slc(ACC1:acc#222.psp#1) TYPE READSLICE PAR 0-9373 XREFS 59801 LOC {1 0.319920175 1 0.41796325 1 0.41796325 1 0.7855312249999999} PREDS {{258 0 0-9519 {}}} SUCCS {{258 0 0-11592 {}}} CYCLES {}}
+set a(0-11591) {NAME ACC1:slc(acc.psp#2)#5 TYPE READSLICE PAR 0-9373 XREFS 59802 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.7855312249999999} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-11592 {}}} CYCLES {}}
+set a(0-11592) {NAME ACC1:conc#1401 TYPE CONCATENATE PAR 0-9373 XREFS 59803 LOC {1 0.319920175 1 0.65340185 1 0.65340185 1 0.7855312249999999} PREDS {{258 0 0-11590 {}} {259 0 0-11591 {}}} SUCCS {{259 0 0-11593 {}}} CYCLES {}}
+set a(0-11593) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#471 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 59804 LOC {1 0.319920175 1 0.65340185 1 0.65340185 1 0.6806477270708271 1 0.8127771020708271} PREDS {{258 0 0-11589 {}} {259 0 0-11592 {}}} SUCCS {{259 0 0-11594 {}}} CYCLES {}}
+set a(0-11594) {NAME ACC1:slc#139 TYPE READSLICE PAR 0-9373 XREFS 59805 LOC {1 0.3471661 1 0.680647775 1 0.680647775 1 0.81277715} PREDS {{259 0 0-11593 {}}} SUCCS {{258 0 0-11607 {}}} CYCLES {}}
+set a(0-11595) {NAME ACC1:slc(ACC1:acc#219.psp#1) TYPE READSLICE PAR 0-9373 XREFS 59806 LOC {1 0.32918685 1 0.41796325 1 0.41796325 1 0.7855312249999999} PREDS {{258 0 0-9667 {}}} SUCCS {{259 0 0-11596 {}}} CYCLES {}}
+set a(0-11596) {NAME ACC1:conc#1380 TYPE CONCATENATE PAR 0-9373 XREFS 59807 LOC {1 0.32918685 1 0.65340185 1 0.65340185 1 0.7855312249999999} PREDS {{259 0 0-11595 {}}} SUCCS {{258 0 0-11605 {}}} CYCLES {}}
+set a(0-11597) {NAME ACC1-1:slc(acc.idiv#5)#35 TYPE READSLICE PAR 0-9373 XREFS 59808 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.7855312249999999} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-11598 {}}} CYCLES {}}
+set a(0-11598) {NAME ACC1-1:exs#107 TYPE SIGNEXTEND PAR 0-9373 XREFS 59809 LOC {1 0.14655495 1 0.65340185 1 0.65340185 1 0.7855312249999999} PREDS {{259 0 0-11597 {}}} SUCCS {{258 0 0-11604 {}}} CYCLES {}}
+set a(0-11599) {NAME ACC1-1:slc(acc#10.psp)#51 TYPE READSLICE PAR 0-9373 XREFS 59810 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.7855312249999999} PREDS {{258 0 0-9471 {}}} SUCCS {{258 0 0-11603 {}}} CYCLES {}}
+set a(0-11600) {NAME ACC1-1:slc(acc.imod#11)#1 TYPE READSLICE PAR 0-9373 XREFS 59811 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.7855312249999999} PREDS {{258 0 0-9535 {}}} SUCCS {{259 0 0-11601 {}}} CYCLES {}}
+set a(0-11601) {NAME ACC1-1:not#92 TYPE NOT PAR 0-9373 XREFS 59812 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.7855312249999999} PREDS {{259 0 0-11600 {}}} SUCCS {{258 0 0-11603 {}}} CYCLES {}}
+set a(0-11602) {NAME ACC1-1:slc(acc.imod#11)#2 TYPE READSLICE PAR 0-9373 XREFS 59813 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.7855312249999999} PREDS {{258 0 0-9535 {}}} SUCCS {{259 0 0-11603 {}}} CYCLES {}}
+set a(0-11603) {NAME ACC1-1:and#5 TYPE AND PAR 0-9373 XREFS 59814 LOC {1 0.374412025 1 0.47245509999999996 1 0.47245509999999996 1 0.7855312249999999} PREDS {{258 0 0-11601 {}} {258 0 0-11599 {}} {259 0 0-11602 {}}} SUCCS {{259 0 0-11604 {}}} CYCLES {}}
+set a(0-11604) {NAME ACC1:conc#1381 TYPE CONCATENATE PAR 0-9373 XREFS 59815 LOC {1 0.374412025 1 0.65340185 1 0.65340185 1 0.7855312249999999} PREDS {{258 0 0-11598 {}} {259 0 0-11603 {}}} SUCCS {{259 0 0-11605 {}}} CYCLES {}}
+set a(0-11605) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#461 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 59816 LOC {1 0.374412025 1 0.65340185 1 0.65340185 1 0.6806477270708271 1 0.8127771020708271} PREDS {{258 0 0-11596 {}} {259 0 0-11604 {}}} SUCCS {{259 0 0-11606 {}}} CYCLES {}}
+set a(0-11606) {NAME ACC1:slc#129 TYPE READSLICE PAR 0-9373 XREFS 59817 LOC {1 0.40165795 1 0.680647775 1 0.680647775 1 0.81277715} PREDS {{259 0 0-11605 {}}} SUCCS {{259 0 0-11607 {}}} CYCLES {}}
+set a(0-11607) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 10 NAME ACC1:acc#574 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 59818 LOC {1 0.40165795 1 0.680647775 1 0.680647775 1 0.7238396701789505 1 0.8559690451789504} PREDS {{258 0 0-11594 {}} {259 0 0-11606 {}}} SUCCS {{259 0 0-11608 {}}} CYCLES {}}
+set a(0-11608) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,1,5,1,6) AREA_SCORE 6.00 QUANTITY 1 NAME ACC1:acc#602 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-9373 XREFS 59819 LOC {1 0.44484989999999996 1 0.7238397249999999 1 0.7238397249999999 1 0.772284309496936 1 0.9044136844969359} PREDS {{258 0 0-11586 {}} {259 0 0-11607 {}}} SUCCS {{259 0 0-11609 {}}} CYCLES {}}
+set a(0-11609) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 5 NAME ACC1:acc#621 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 59820 LOC {1 0.515935775 1 0.77228435 1 0.77228435 1 0.8154860734103023 1 0.9476154484103023} PREDS {{258 0 0-11577 {}} {259 0 0-11608 {}}} SUCCS {{259 0 0-11610 {}}} CYCLES {}}
+set a(0-11610) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME ACC1:acc#640 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-9373 XREFS 59821 LOC {1 0.55913755 1 0.815486125 1 0.815486125 1 0.8678705777684257 1 0.9999999527684257} PREDS {{258 0 0-11532 {}} {259 0 0-11609 {}}} SUCCS {{258 0 0-11634 {}}} CYCLES {}}
+set a(0-11611) {NAME ACC1:slc(ACC1:acc#227.psp) TYPE READSLICE PAR 0-9373 XREFS 59822 LOC {1 0.14655495 1 0.22025875 1 0.22025875 1 0.5760930249999999} PREDS {{258 0 0-9918 {}}} SUCCS {{258 0 0-11613 {}}} CYCLES {}}
+set a(0-11612) {NAME ACC1:slc(acc.psp#1) TYPE READSLICE PAR 0-9373 XREFS 59823 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.5760930249999999} PREDS {{258 0 0-9839 {}}} SUCCS {{259 0 0-11613 {}}} CYCLES {}}
+set a(0-11613) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 7 NAME ACC1:acc#301 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-9373 XREFS 59824 LOC {1 0.14655495 1 0.44396365 1 0.44396365 1 0.47557448625 1 0.6077038612499999} PREDS {{258 0 0-11611 {}} {259 0 0-11612 {}}} SUCCS {{258 0 0-11615 {}}} CYCLES {}}
+set a(0-11614) {NAME ACC1:slc(ACC1:acc#224.psp) TYPE READSLICE PAR 0-9373 XREFS 59825 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6077039} PREDS {{258 0 0-9993 {}}} SUCCS {{259 0 0-11615 {}}} CYCLES {}}
+set a(0-11615) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#300 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 59826 LOC {1 0.178165825 1 0.47557452499999997 1 0.47557452499999997 1 0.4960472850894752 1 0.6281766600894753} PREDS {{258 0 0-11613 {}} {259 0 0-11614 {}}} SUCCS {{258 0 0-11617 {}}} CYCLES {}}
+set a(0-11616) {NAME ACC1:slc(ACC1:acc#228.psp) TYPE READSLICE PAR 0-9373 XREFS 59827 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6281766999999999} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11617 {}}} CYCLES {}}
+set a(0-11617) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 30 NAME ACC1:acc#299 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-9373 XREFS 59828 LOC {1 0.19863862499999999 1 0.496047325 1 0.496047325 1 0.5165200850894752 1 0.6486494600894752} PREDS {{258 0 0-11615 {}} {259 0 0-11616 {}}} SUCCS {{258 0 0-11619 {}}} CYCLES {}}
+set a(0-11618) {NAME ACC1:slc(ACC1:acc#226.psp) TYPE READSLICE PAR 0-9373 XREFS 59829 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.6486495} PREDS {{258 0 0-9767 {}}} SUCCS {{259 0 0-11619 {}}} CYCLES {}}
+set a(0-11619) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#298 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 59830 LOC {1 0.219111425 1 0.516520125 1 0.516520125 1 0.5437660020708271 1 0.6758953770708271} PREDS {{258 0 0-11617 {}} {259 0 0-11618 {}}} SUCCS {{258 0 0-11621 {}}} CYCLES {}}
+set a(0-11620) {NAME ACC1:slc(ACC1:acc#224.psp#1) TYPE READSLICE PAR 0-9373 XREFS 59831 LOC {1 0.14655495 1 0.244598025 1 0.244598025 1 0.675895425} PREDS {{258 0 0-9471 {}}} SUCCS {{259 0 0-11621 {}}} CYCLES {}}
+set a(0-11621) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#297 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 59832 LOC {1 0.24635735 1 0.54376605 1 0.54376605 1 0.5710119270708272 1 0.7031413020708271} PREDS {{258 0 0-11619 {}} {259 0 0-11620 {}}} SUCCS {{258 0 0-11623 {}}} CYCLES {}}
+set a(0-11622) {NAME ACC1:slc(ACC1-1:acc#25.psp) TYPE READSLICE PAR 0-9373 XREFS 59833 LOC {1 0.14655495 1 0.23533135 1 0.23533135 1 0.70314135} PREDS {{258 0 0-9616 {}}} SUCCS {{259 0 0-11623 {}}} CYCLES {}}
+set a(0-11623) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#296 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 59834 LOC {1 0.273603275 1 0.571011975 1 0.571011975 1 0.5982578520708272 1 0.7303872270708271} PREDS {{258 0 0-11621 {}} {259 0 0-11622 {}}} SUCCS {{258 0 0-11625 {}}} CYCLES {}}
+set a(0-11624) {NAME ACC1:slc(acc.psp#2) TYPE READSLICE PAR 0-9373 XREFS 59835 LOC {1 0.14655495 1 0.1708131 1 0.1708131 1 0.730387275} PREDS {{258 0 0-9386 {}}} SUCCS {{259 0 0-11625 {}}} CYCLES {}}
+set a(0-11625) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME ACC1:acc#295 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 59836 LOC {1 0.3008492 1 0.5982579 1 0.5982579 1 0.6255037770708272 1 0.7576331520708272} PREDS {{258 0 0-11623 {}} {259 0 0-11624 {}}} SUCCS {{259 0 0-11626 {}}} CYCLES {}}
+set a(0-11626) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(4,0,5,0,8) AREA_SCORE 330.25 QUANTITY 2 NAME ACC1:mul TYPE MUL DELAY {2.71 ns} LIBRARY_DELAY {2.71 ns} PAR 0-9373 XREFS 59837 LOC {1 0.328095125 1 0.625503825 1 0.625503825 1 0.7951758226245129 1 0.9273051976245129} PREDS {{259 0 0-11625 {}}} SUCCS {{258 0 0-11633 {}}} CYCLES {}}
+set a(0-11627) {NAME slc(acc#20.psp#1)#84 TYPE READSLICE PAR 0-9373 XREFS 59838 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.92730525} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-11632 {}}} CYCLES {}}
+set a(0-11628) {NAME slc(acc#20.psp#1)#85 TYPE READSLICE PAR 0-9373 XREFS 59839 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.92730525} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-11632 {}}} CYCLES {}}
+set a(0-11629) {NAME slc(acc#20.psp#1)#86 TYPE READSLICE PAR 0-9373 XREFS 59840 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.92730525} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-11632 {}}} CYCLES {}}
+set a(0-11630) {NAME slc(acc#20.psp#1)#78 TYPE READSLICE PAR 0-9373 XREFS 59841 LOC {1 0.14655495 1 0.193012825 1 0.193012825 1 0.92730525} PREDS {{258 0 0-10065 {}}} SUCCS {{258 0 0-11632 {}}} CYCLES {}}
+set a(0-11631) {NAME ACC1:slc(ACC1:acc#228.psp)#49 TYPE READSLICE PAR 0-9373 XREFS 59842 LOC {1 0.14655495 1 0.2022795 1 0.2022795 1 0.92730525} PREDS {{258 0 0-9695 {}}} SUCCS {{259 0 0-11632 {}}} CYCLES {}}
+set a(0-11632) {NAME ACC1:conc#1086 TYPE CONCATENATE PAR 0-9373 XREFS 59843 LOC {1 0.14655495 1 0.795175875 1 0.795175875 1 0.92730525} PREDS {{258 0 0-11630 {}} {258 0 0-11629 {}} {258 0 0-11628 {}} {258 0 0-11627 {}} {259 0 0-11631 {}}} SUCCS {{259 0 0-11633 {}}} CYCLES {}}
+set a(0-11633) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,9) AREA_SCORE 9.26 QUANTITY 5 NAME ACC1:acc#639 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-9373 XREFS 59844 LOC {1 0.49776717499999995 1 0.795175875 1 0.795175875 1 0.8678705777684257 1 0.9999999527684257} PREDS {{258 0 0-11626 {}} {259 0 0-11632 {}}} SUCCS {{259 0 0-11634 {}}} CYCLES {}}
+set a(0-11634) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,1,11) AREA_SCORE 10.00 QUANTITY 5 NAME ACC1:acc#647 TYPE ACCU DELAY {0.91 ns} LIBRARY_DELAY {0.91 ns} PAR 0-9373 XREFS 59845 LOC {1 0.6115220499999999 1 0.867870625 1 0.867870625 1 0.9246291378916544 2 0.06498863789165435} PREDS {{258 0 0-11610 {}} {259 0 0-11633 {}}} SUCCS {{259 0 0-11635 {}}} CYCLES {}}
+set a(0-11635) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 14 NAME ACC1:acc#655 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 59846 LOC {1 0.8358528 1 0.9246291999999999 1 0.9246291999999999 1 0.9999999563734283 2 0.14035945637342837} PREDS {{258 0 0-11478 {}} {259 0 0-11634 {}}} SUCCS {{259 0 0-11636 {}}} CYCLES {}}
+set a(0-11636) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 4 NAME ACC1:acc#660 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-9373 XREFS 59847 LOC {2 0.07948825 2 0.1403595 2 0.1403595 2 0.21984770349977767 2 0.21984770349977767} PREDS {{258 0 0-11089 {}} {259 0 0-11635 {}}} SUCCS {{259 0 0-11637 {}}} CYCLES {}}
+set a(0-11637) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(14,1,14,1,15) AREA_SCORE 15.00 QUANTITY 2 NAME ACC1:acc#663 TYPE ACCU DELAY {1.40 ns} LIBRARY_DELAY {1.40 ns} PAR 0-9373 XREFS 59848 LOC {2 0.1589765 2 0.21984774999999998 2 0.21984774999999998 2 0.3074051292724431 2 0.3074051292724431} PREDS {{258 0 0-10604 {}} {259 0 0-11636 {}}} SUCCS {{259 0 0-11638 {}}} CYCLES {}}
+set a(0-11638) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(15,0,14,1,15) AREA_SCORE 16.00 QUANTITY 1 NAME ACC1:acc TYPE ACCU DELAY {1.63 ns} LIBRARY_DELAY {1.63 ns} PAR 0-9373 XREFS 59849 LOC {2 0.246533925 2 0.307405175 2 0.307405175 2 0.40918180097764767 2 0.40918180097764767} PREDS {{258 0 0-10598 {}} {259 0 0-11637 {}}} SUCCS {{259 0 0-11639 {}}} CYCLES {}}
+set a(0-11639) {NAME ACC1:slc TYPE READSLICE PAR 0-9373 XREFS 59850 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.40918184999999996} PREDS {{259 0 0-11638 {}}} SUCCS {{259 0 0-11640 {}} {258 0 0-11641 {}} {258 0 0-11644 {}} {258 0 0-11646 {}} {258 0 0-11649 {}} {258 0 0-11652 {}} {258 0 0-11653 {}} {258 0 0-11658 {}} {258 0 0-11660 {}} {258 0 0-11662 {}} {258 0 0-11681 {}} {258 0 0-11688 {}} {258 0 0-11689 {}} {258 0 0-11691 {}}} CYCLES {}}
+set a(0-11640) {NAME intensity:slc(intensity#2.sg1)#4 TYPE READSLICE PAR 0-9373 XREFS 59851 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.40918184999999996} PREDS {{259 0 0-11639 {}}} SUCCS {{258 0 0-11643 {}}} CYCLES {}}
+set a(0-11641) {NAME intensity:slc(intensity#2.sg1)#5 TYPE READSLICE PAR 0-9373 XREFS 59852 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.40918184999999996} PREDS {{258 0 0-11639 {}}} SUCCS {{259 0 0-11642 {}}} CYCLES {}}
+set a(0-11642) {NAME FRAME:not#2 TYPE NOT PAR 0-9373 XREFS 59853 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.40918184999999996} PREDS {{259 0 0-11641 {}}} SUCCS {{259 0 0-11643 {}}} CYCLES {}}
+set a(0-11643) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME FRAME:acc#6 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59854 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.45673797707082714 2 0.45673797707082714} PREDS {{258 0 0-11640 {}} {259 0 0-11642 {}}} SUCCS {{258 0 0-11651 {}}} CYCLES {}}
+set a(0-11644) {NAME intensity:slc(intensity#2.sg1)#6 TYPE READSLICE PAR 0-9373 XREFS 59855 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.4294921} PREDS {{258 0 0-11639 {}}} SUCCS {{259 0 0-11645 {}}} CYCLES {}}
+set a(0-11645) {NAME FRAME:not#3 TYPE NOT PAR 0-9373 XREFS 59856 LOC {2 0.34831059999999997 2 0.4294921 2 0.4294921 2 0.4294921} PREDS {{259 0 0-11644 {}}} SUCCS {{258 0 0-11648 {}}} CYCLES {}}
+set a(0-11646) {NAME intensity:slc(intensity#2.sg1)#7 TYPE READSLICE PAR 0-9373 XREFS 59857 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.4294921} PREDS {{258 0 0-11639 {}}} SUCCS {{259 0 0-11647 {}}} CYCLES {}}
+set a(0-11647) {NAME FRAME:not#9 TYPE NOT PAR 0-9373 XREFS 59858 LOC {2 0.34831059999999997 2 0.4294921 2 0.4294921 2 0.4294921} PREDS {{259 0 0-11646 {}}} SUCCS {{259 0 0-11648 {}}} CYCLES {}}
+set a(0-11648) {NAME FRAME:conc TYPE CONCATENATE PAR 0-9373 XREFS 59859 LOC {2 0.34831059999999997 2 0.4294921 2 0.4294921 2 0.4294921} PREDS {{258 0 0-11645 {}} {259 0 0-11647 {}}} SUCCS {{258 0 0-11650 {}}} CYCLES {}}
+set a(0-11649) {NAME intensity:slc(intensity#2.sg1)#1 TYPE READSLICE PAR 0-9373 XREFS 59860 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.4294921} PREDS {{258 0 0-11639 {}}} SUCCS {{259 0 0-11650 {}}} CYCLES {}}
+set a(0-11650) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME FRAME:acc#5 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 59861 LOC {2 0.34831059999999997 2 0.4294921 2 0.4294921 2 0.4567379770708272 2 0.4567379770708272} PREDS {{258 0 0-11648 {}} {259 0 0-11649 {}}} SUCCS {{259 0 0-11651 {}}} CYCLES {}}
+set a(0-11651) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 30 NAME FRAME:acc#8 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-9373 XREFS 59862 LOC {2 0.395866775 2 0.456738025 2 0.456738025 2 0.5100850451789505 2 0.5100850451789505} PREDS {{258 0 0-11643 {}} {259 0 0-11650 {}}} SUCCS {{258 0 0-11656 {}}} CYCLES {}}
+set a(0-11652) {NAME intensity:slc(intensity#2.sg1)#2 TYPE READSLICE PAR 0-9373 XREFS 59863 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.462528925} PREDS {{258 0 0-11639 {}}} SUCCS {{258 0 0-11655 {}}} CYCLES {}}
+set a(0-11653) {NAME intensity:slc(intensity#2.sg1)#3 TYPE READSLICE PAR 0-9373 XREFS 59864 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.462528925} PREDS {{258 0 0-11639 {}}} SUCCS {{259 0 0-11654 {}}} CYCLES {}}
+set a(0-11654) {NAME FRAME:not#1 TYPE NOT PAR 0-9373 XREFS 59865 LOC {2 0.34831059999999997 2 0.462528925 2 0.462528925 2 0.462528925} PREDS {{259 0 0-11653 {}}} SUCCS {{259 0 0-11655 {}}} CYCLES {}}
+set a(0-11655) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 123 NAME FRAME:acc#7 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-9373 XREFS 59866 LOC {2 0.34831059999999997 2 0.462528925 2 0.462528925 2 0.5100850520708271 2 0.5100850520708271} PREDS {{258 0 0-11652 {}} {259 0 0-11654 {}}} SUCCS {{259 0 0-11656 {}}} CYCLES {}}
+set a(0-11656) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME FRAME:acc#9 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-9373 XREFS 59867 LOC {2 0.44921384999999997 2 0.5100851 2 0.5100851 2 0.548374559496936 2 0.548374559496936} PREDS {{258 0 0-11651 {}} {259 0 0-11655 {}}} SUCCS {{259 0 0-11657 {}}} CYCLES {}}
+set a(0-11657) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 5 NAME acc#30 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 59868 LOC {2 0.48750335 2 0.5483745999999999 2 0.5483745999999999 2 0.5915763234103023 2 0.5915763234103023} PREDS {{259 0 0-11656 {}}} SUCCS {{258 0 0-11663 {}} {258 0 0-11665 {}} {258 0 0-11667 {}} {258 0 0-11669 {}} {258 0 0-11671 {}} {258 0 0-11679 {}}} CYCLES {}}
+set a(0-11658) {NAME intensity:slc(intensity#2.sg1)#9 TYPE READSLICE PAR 0-9373 XREFS 59869 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.632810675} PREDS {{258 0 0-11639 {}}} SUCCS {{259 0 0-11659 {}}} CYCLES {}}
+set a(0-11659) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,11,1,13) AREA_SCORE 330.00 QUANTITY 2 NAME FRAME:mul TYPE MUL DELAY {3.13 ns} LIBRARY_DELAY {3.13 ns} PAR 0-9373 XREFS 59870 LOC {2 0.34831059999999997 2 0.632810675 2 0.632810675 2 0.82839841875 2 0.82839841875} PREDS {{259 0 0-11658 {}}} SUCCS {{258 0 0-11687 {}}} CYCLES {}}
+set a(0-11660) {NAME intensity:slc(intensity#2.sg1)#11 TYPE READSLICE PAR 0-9373 XREFS 59871 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.5937580499999999} PREDS {{258 0 0-11639 {}}} SUCCS {{259 0 0-11661 {}}} CYCLES {}}
+set a(0-11661) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 1 NAME FRAME:mul#1 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-9373 XREFS 59872 LOC {2 0.34831059999999997 2 0.5937580499999999 2 0.5937580499999999 2 0.7716398421744312 2 0.7716398421744312} PREDS {{259 0 0-11660 {}}} SUCCS {{258 0 0-11686 {}}} CYCLES {}}
+set a(0-11662) {NAME intensity:slc(intensity#2.sg1) TYPE READSLICE PAR 0-9373 XREFS 59873 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.7284381249999999} PREDS {{258 0 0-11639 {}}} SUCCS {{258 0 0-11685 {}}} CYCLES {}}
+set a(0-11663) {NAME FRAME:slc(acc.imod#24)#4 TYPE READSLICE PAR 0-9373 XREFS 59874 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.690148625} PREDS {{258 0 0-11657 {}}} SUCCS {{259 0 0-11664 {}}} CYCLES {}}
+set a(0-11664) {NAME FRAME:conc#12 TYPE CONCATENATE PAR 0-9373 XREFS 59875 LOC {2 0.530705125 2 0.690148625 2 0.690148625 2 0.690148625} PREDS {{259 0 0-11663 {}}} SUCCS {{258 0 0-11684 {}}} CYCLES {}}
+set a(0-11665) {NAME FRAME:slc(acc.imod#24)#6 TYPE READSLICE PAR 0-9373 XREFS 59876 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.629865875} PREDS {{258 0 0-11657 {}}} SUCCS {{259 0 0-11666 {}}} CYCLES {}}
+set a(0-11666) {NAME FRAME:not#7 TYPE NOT PAR 0-9373 XREFS 59877 LOC {2 0.530705125 2 0.629865875 2 0.629865875 2 0.629865875} PREDS {{259 0 0-11665 {}}} SUCCS {{258 0 0-11678 {}}} CYCLES {}}
+set a(0-11667) {NAME FRAME:slc(acc.imod#24)#1 TYPE READSLICE PAR 0-9373 XREFS 59878 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{258 0 0-11657 {}}} SUCCS {{259 0 0-11668 {}}} CYCLES {}}
+set a(0-11668) {NAME FRAME:conc#14 TYPE CONCATENATE PAR 0-9373 XREFS 59879 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{259 0 0-11667 {}}} SUCCS {{258 0 0-11674 {}}} CYCLES {}}
+set a(0-11669) {NAME FRAME:slc(acc.imod#24)#2 TYPE READSLICE PAR 0-9373 XREFS 59880 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{258 0 0-11657 {}}} SUCCS {{259 0 0-11670 {}}} CYCLES {}}
+set a(0-11670) {NAME FRAME:not#5 TYPE NOT PAR 0-9373 XREFS 59881 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{259 0 0-11669 {}}} SUCCS {{258 0 0-11673 {}}} CYCLES {}}
+set a(0-11671) {NAME FRAME:slc(acc.imod#24) TYPE READSLICE PAR 0-9373 XREFS 59882 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{258 0 0-11657 {}}} SUCCS {{259 0 0-11672 {}}} CYCLES {}}
+set a(0-11672) {NAME FRAME:not#4 TYPE NOT PAR 0-9373 XREFS 59883 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{259 0 0-11671 {}}} SUCCS {{259 0 0-11673 {}}} CYCLES {}}
+set a(0-11673) {NAME FRAME:conc#15 TYPE CONCATENATE PAR 0-9373 XREFS 59884 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.5915763749999999} PREDS {{258 0 0-11670 {}} {259 0 0-11672 {}}} SUCCS {{259 0 0-11674 {}}} CYCLES {}}
+set a(0-11674) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME FRAME:acc#16 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-9373 XREFS 59885 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.629865834496936 2 0.629865834496936} PREDS {{258 0 0-11668 {}} {259 0 0-11673 {}}} SUCCS {{259 0 0-11675 {}}} CYCLES {}}
+set a(0-11675) {NAME FRAME:slc#3 TYPE READSLICE PAR 0-9373 XREFS 59886 LOC {2 0.568994625 2 0.629865875 2 0.629865875 2 0.629865875} PREDS {{259 0 0-11674 {}}} SUCCS {{259 0 0-11676 {}}} CYCLES {}}
+set a(0-11676) {NAME FRAME:slc#2 TYPE READSLICE PAR 0-9373 XREFS 59887 LOC {2 0.568994625 2 0.629865875 2 0.629865875 2 0.629865875} PREDS {{259 0 0-11675 {}}} SUCCS {{259 0 0-11677 {}}} CYCLES {}}
+set a(0-11677) {NAME FRAME:not#8 TYPE NOT PAR 0-9373 XREFS 59888 LOC {2 0.568994625 2 0.629865875 2 0.629865875 2 0.629865875} PREDS {{259 0 0-11676 {}}} SUCCS {{259 0 0-11678 {}}} CYCLES {}}
+set a(0-11678) {NAME FRAME:conc#3 TYPE CONCATENATE PAR 0-9373 XREFS 59889 LOC {2 0.568994625 2 0.629865875 2 0.629865875 2 0.629865875} PREDS {{258 0 0-11666 {}} {259 0 0-11677 {}}} SUCCS {{258 0 0-11680 {}}} CYCLES {}}
+set a(0-11679) {NAME FRAME:slc(acc.imod#24)#5 TYPE READSLICE PAR 0-9373 XREFS 59890 LOC {2 0.530705125 2 0.5915763749999999 2 0.5915763749999999 2 0.629865875} PREDS {{258 0 0-11657 {}}} SUCCS {{259 0 0-11680 {}}} CYCLES {}}
+set a(0-11680) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 49 NAME FRAME:acc#10 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-9373 XREFS 59891 LOC {2 0.568994625 2 0.629865875 2 0.629865875 2 0.6571117520708272 2 0.6571117520708272} PREDS {{258 0 0-11678 {}} {259 0 0-11679 {}}} SUCCS {{258 0 0-11683 {}}} CYCLES {}}
+set a(0-11681) {NAME intensity:slc(intensity#2.sg1)#10 TYPE READSLICE PAR 0-9373 XREFS 59892 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.6571118} PREDS {{258 0 0-11639 {}}} SUCCS {{259 0 0-11682 {}}} CYCLES {}}
+set a(0-11682) {NAME FRAME:not#6 TYPE NOT PAR 0-9373 XREFS 59893 LOC {2 0.34831059999999997 2 0.6571118 2 0.6571118 2 0.6571118} PREDS {{259 0 0-11681 {}}} SUCCS {{259 0 0-11683 {}}} CYCLES {}}
+set a(0-11683) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 15 NAME FRAME:acc#11 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-9373 XREFS 59894 LOC {2 0.59624055 2 0.6571118 2 0.6571118 2 0.6901485701789505 2 0.6901485701789505} PREDS {{258 0 0-11680 {}} {259 0 0-11682 {}}} SUCCS {{259 0 0-11684 {}}} CYCLES {}}
+set a(0-11684) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 12 NAME FRAME:acc#12 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-9373 XREFS 59895 LOC {2 0.6292773749999999 2 0.690148625 2 0.690148625 2 0.728438084496936 2 0.728438084496936} PREDS {{258 0 0-11664 {}} {259 0 0-11683 {}}} SUCCS {{259 0 0-11685 {}}} CYCLES {}}
+set a(0-11685) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 5 NAME FRAME:acc#13 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-9373 XREFS 59896 LOC {2 0.667566875 2 0.7284381249999999 2 0.7284381249999999 2 0.7716398484103023 2 0.7716398484103023} PREDS {{258 0 0-11662 {}} {259 0 0-11684 {}}} SUCCS {{259 0 0-11686 {}}} CYCLES {}}
+set a(0-11686) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,1,11) AREA_SCORE 10.00 QUANTITY 5 NAME FRAME:acc#14 TYPE ACCU DELAY {0.91 ns} LIBRARY_DELAY {0.91 ns} PAR 0-9373 XREFS 59897 LOC {2 0.71076865 2 0.7716398999999999 2 0.7716398999999999 2 0.8283984128916543 2 0.8283984128916543} PREDS {{258 0 0-11661 {}} {259 0 0-11685 {}}} SUCCS {{259 0 0-11687 {}}} CYCLES {}}
+set a(0-11687) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME FRAME:acc#15 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-9373 XREFS 59898 LOC {2 0.7675272249999999 2 0.828398475 2 0.828398475 2 0.9037692313734284 2 0.9037692313734284} PREDS {{258 0 0-11659 {}} {259 0 0-11686 {}}} SUCCS {{258 0 0-11694 {}}} CYCLES {}}
+set a(0-11688) {NAME intensity:slc(intensity#2.sg1)#12 TYPE READSLICE PAR 0-9373 XREFS 59899 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.9037692749999999} PREDS {{258 0 0-11639 {}}} SUCCS {{258 0 0-11692 {}}} CYCLES {}}
+set a(0-11689) {NAME intensity:slc(intensity#2.sg1)#13 TYPE READSLICE PAR 0-9373 XREFS 59900 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.9037692749999999} PREDS {{258 0 0-11639 {}}} SUCCS {{259 0 0-11690 {}}} CYCLES {}}
+set a(0-11690) {NAME FRAME:exs#1 TYPE SIGNEXTEND PAR 0-9373 XREFS 59901 LOC {2 0.34831059999999997 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{259 0 0-11689 {}}} SUCCS {{258 0 0-11692 {}}} CYCLES {}}
+set a(0-11691) {NAME intensity:slc(intensity#2.sg1)#8 TYPE READSLICE PAR 0-9373 XREFS 59902 LOC {2 0.34831059999999997 2 0.40918184999999996 2 0.40918184999999996 2 0.9037692749999999} PREDS {{258 0 0-11639 {}}} SUCCS {{259 0 0-11692 {}}} CYCLES {}}
+set a(0-11692) {NAME FRAME:conc#2 TYPE CONCATENATE PAR 0-9373 XREFS 59903 LOC {2 0.34831059999999997 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{258 0 0-11690 {}} {258 0 0-11688 {}} {259 0 0-11691 {}}} SUCCS {{259 0 0-11693 {}}} CYCLES {}}
+set a(0-11693) {NAME FRAME:exs TYPE SIGNEXTEND PAR 0-9373 XREFS 59904 LOC {2 0.34831059999999997 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{259 0 0-11692 {}}} SUCCS {{259 0 0-11694 {}}} CYCLES {}}
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+set a(0-11703) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(6,2) AREA_SCORE 4.38 QUANTITY 1 NAME FRAME:or#3 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-9373 XREFS 59914 LOC {2 0.9223862749999999 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{258 0 0-11700 {}} {259 0 0-11702 {}}} SUCCS {{258 0 0-11705 {}}} CYCLES {}}
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+set a(0-11711) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(19,0,2,1,19) AREA_SCORE 20.00 QUANTITY 1 NAME FRAME:acc#4 TYPE ACCU DELAY {1.91 ns} LIBRARY_DELAY {1.91 ns} PAR 0-9373 XREFS 59922 LOC {1 0.016406775 1 0.828356125 1 0.828356125 1 0.9476154410815966 3 0.9476154410815966} PREDS {{259 0 0-11710 {}}} SUCCS {{258 0 0-11714 {}} {258 0 0-11715 {}}} CYCLES {}}
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+set a(0-11716) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 8 NAME FRAME:acc TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-9373 XREFS 59927 LOC {1 0.13566614999999999 1 0.9476154999999999 1 0.9476154999999999 1 0.9999999527684257 3 0.9999999527684257} PREDS {{259 0 0-11715 {}}} SUCCS {{259 0 0-11717 {}}} CYCLES {}}
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+set a(0-11718) {NAME FRAME:not TYPE NOT PAR 0-9373 XREFS 59929 LOC {1 0.18805064999999999 1 1.0 1 1.0 3 1.0} PREDS {{259 0 0-11717 {}}} SUCCS {{259 0 0-11719 {}}} CYCLES {}}
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0-11575 0-11576 0-11577 0-11578 0-11579 0-11580 0-11581 0-11582 0-11583 0-11584 0-11585 0-11586 0-11587 0-11588 0-11589 0-11590 0-11591 0-11592 0-11593 0-11594 0-11595 0-11596 0-11597 0-11598 0-11599 0-11600 0-11601 0-11602 0-11603 0-11604 0-11605 0-11606 0-11607 0-11608 0-11609 0-11610 0-11611 0-11612 0-11613 0-11614 0-11615 0-11616 0-11617 0-11618 0-11619 0-11620 0-11621 0-11622 0-11623 0-11624 0-11625 0-11626 0-11627 0-11628 0-11629 0-11630 0-11631 0-11632 0-11633 0-11634 0-11635 0-11636 0-11637 0-11638 0-11639 0-11640 0-11641 0-11642 0-11643 0-11644 0-11645 0-11646 0-11647 0-11648 0-11649 0-11650 0-11651 0-11652 0-11653 0-11654 0-11655 0-11656 0-11657 0-11658 0-11659 0-11660 0-11661 0-11662 0-11663 0-11664 0-11665 0-11666 0-11667 0-11668 0-11669 0-11670 0-11671 0-11672 0-11673 0-11674 0-11675 0-11676 0-11677 0-11678 0-11679 0-11680 0-11681 0-11682 0-11683 0-11684 0-11685 0-11686 0-11687 0-11688 0-11689 0-11690 0-11691 0-11692 0-11693 0-11694 0-11695 0-11696 0-11697 0-11698 0-11699 0-11700 0-11701 0-11702 0-11703 0-11704 0-11705 0-11706 0-11707 0-11708 0-11709 0-11710 0-11711 0-11712 0-11713 0-11714 0-11715 0-11716 0-11717 0-11718 0-11719} ITERATIONS Infinite LATENCY 307201 RESET_LATENCY 0 CSTEPS 3 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 307200 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 3.0 CYCLES_IN 307202 TOTAL_CYCLES_IN 307202 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 307202 NAME main TYPE LOOP DELAY {6144060.00 ns} PAR 0-9368 XREFS 59931 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{258 0 0-9369 {}} {258 0 0-9370 {}} {258 0 0-9371 {}} {259 0 0-9372 {}}} SUCCS {{772 0 0-9369 {}} {772 0 0-9370 {}} {772 0 0-9371 {}} {772 0 0-9372 {}}} CYCLES {}}
+set a(0-9368) {CHI {0-9369 0-9370 0-9371 0-9372 0-9373} ITERATIONS Infinite LATENCY 307201 RESET_LATENCY 0 CSTEPS 0 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 307200 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 0 TOTAL_CYCLES_IN 0 TOTAL_CYCLES_UNDER 307202 TOTAL_CYCLES 307202 NAME core:rlp TYPE LOOP DELAY {6144060.00 ns} PAR {} XREFS 59932 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-9368-TOTALCYCLES) {307202}
+set a(0-9368-QMOD) {mgc_ioport.mgc_in_wire(1,90) 0-9377 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11) {0-9382 0-9385 0-9467 0-9470 0-9540 0-9543 0-9614 0-9690 0-9694 0-9764 0-9836 0-9913 0-9917 0-9990 0-10062} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12) {0-9386 0-9471 0-9544 0-9616 0-9695 0-9767 0-9839 0-9918 0-9993 0-10065 0-10298 0-10445 0-10446 0-11635} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4) {0-9394 0-9437 0-9519 0-9552 0-9595 0-9624 0-9667 0-9743 0-9815 0-9847 0-9890 0-9926 0-9969 0-10041 0-10073 0-10116 0-10144 0-10146 0-10542 0-10544 0-10559 0-10561 0-10582 0-10584 0-10595 0-10603 0-11581 0-11585 0-11615 0-11617} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5) {0-9401 0-9559 0-9631 0-9854 0-9933 0-10080 0-10241 0-10383 0-11586 0-11607} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3) {0-9410 0-9419 0-9433 0-9482 0-9496 0-9515 0-9568 0-9577 0-9591 0-9640 0-9649 0-9663 0-9706 0-9720 0-9739 0-9778 0-9792 0-9811 0-9863 0-9872 0-9886 0-9942 0-9951 0-9965 0-10004 0-10018 0-10037 0-10089 0-10098 0-10112 0-10251 0-10273 0-10393 0-10415 0-11103 0-11108 0-11114 0-11119 0-11126 0-11131 0-11137 0-11142 0-11150 0-11155 0-11161 0-11166 0-11173 0-11178 0-11184 0-11189 0-11199 0-11204 0-11210 0-11215 0-11222 0-11227 0-11233 0-11238 0-11246 0-11251 0-11257 0-11262 0-11269 0-11489 0-11494 0-11500 0-11505 0-11512 0-11517 0-11523 0-11528} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4) {0-9424 0-9582 0-9654 0-9877 0-9956 0-10103 0-10184 0-10194 0-10196 0-10204 0-10213 0-10215 0-10280 0-10282 0-10326 0-10336 0-10338 0-10346 0-10355 0-10357 0-10427 0-10429 0-10497 0-10620 0-10629 0-10631 0-10639 0-10648 0-10650 0-10659 0-10668 0-10670 0-10678 0-10691 0-10693 0-10706 0-10715 0-10717 0-10725 0-10734 0-10736 0-10745 0-10758 0-10760 0-10771 0-10780 0-10782 0-10793 0-10802 0-10804 0-10816 0-10828 0-10830 0-10839 0-10848 0-10850 0-10858 0-10867 0-10869 0-10885 0-10899 0-10901 0-10911 0-10922 0-10924 0-10935 0-10946 0-10948 0-10958 0-10972 0-10974 0-11109 0-11120 0-11132 0-11143 0-11156 0-11167 0-11179 0-11190 0-11205 0-11216 0-11228 0-11239 0-11252 0-11263 0-11276 0-11278 0-11285 0-11294 0-11296 0-11307 0-11316 0-11318 0-11326 0-11335 0-11337 0-11346 0-11355 0-11357 0-11369 0-11381 0-11383 0-11397 0-11409 0-11411 0-11419 0-11428 0-11430 0-11439 0-11448 0-11450 0-11461 0-11470 0-11472 0-11495 0-11506 0-11518 0-11529 0-11545 0-11556 0-11568 0-11643 0-11655} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6) {0-9426 0-9487 0-9584 0-9656 0-9711 0-9783 0-9879 0-9958 0-10009 0-10105 0-10252 0-10394 0-10518 0-10527 0-11683} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5) {0-9443 0-9452 0-9503 0-9525 0-9534 0-9601 0-9610 0-9673 0-9682 0-9727 0-9749 0-9758 0-9799 0-9821 0-9830 0-9896 0-9905 0-9975 0-9984 0-10025 0-10047 0-10056 0-10122 0-10131 0-10148 0-10150 0-10152 0-10154 0-10239 0-10381 0-10502 0-10511 0-10546 0-10548 0-10550 0-10552 0-10563 0-10565 0-10567 0-10569 0-11575 0-11593 0-11605 0-11619 0-11621 0-11623 0-11625 0-11650 0-11680} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7) {0-9507 0-9731 0-9803 0-10029 0-10253 0-10283 0-10395 0-10430 0-10503 0-11656 0-11674 0-11684} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2) {0-10142 0-10540 0-10557 0-10580 0-10593 0-10601 0-11613} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,5,0,8) {0-10155 0-11626} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,12) {0-10160 0-11687} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5) {0-10216 0-10358 0-10458 0-10469 0-10483 0-10651 0-10694 0-10737 0-10783 0-10831 0-10870 0-10925 0-10975 0-11121 0-11144 0-11168 0-11191 0-11217 0-11240 0-11264 0-11297 0-11338 0-11384 0-11431 0-11473 0-11507 0-11530 0-11557 0-11576 0-11651} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8) {0-10217 0-10359 0-11609 0-11657 0-11685} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10) {0-10218 0-10285 0-10360 0-10432 0-11194 0-11477 0-11610 0-11716} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,11) {0-10219 0-10361 0-10537 0-11634 0-11686} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4) {0-10226 0-10229 0-10368 0-10371} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9) {0-10259 0-10284 0-10401 0-10431 0-10529 0-11532} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,12) {0-10286 0-10433 0-10554 0-11478} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,11) {0-10297 0-10444 0-11088} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) {0-10447 0-11089 0-11636 0-11694} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6) {0-10470 0-10695 0-10784 0-10871 0-10976 0-11145 0-11192 0-11241 0-11298 0-11385 0-11474 0-11531 0-11577} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7) {0-10504 0-10785 0-10977 0-10990 0-11002 0-11015 0-11026 0-11193 0-11299 0-11475} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,1,2,1,3) 0-10526 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,1,6,1,7) 0-10528 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,7,0,10) {0-10553 0-10585} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,9,0,12) 0-10570 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,12,1,13) {0-10571 0-10590} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,1,13,1,14) {0-10572 0-10597} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,11,1,13) {0-10596 0-11659} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(14,1,14,1,15) {0-10598 0-11637} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,14) 0-10604 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8) {0-10978 0-11003 0-11027 0-11038 0-11051 0-11062 0-11074 0-11085 0-11476} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9) {0-11004 0-11039 0-11063 0-11086 0-11633} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,0,10) {0-11040 0-11087} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,1,5,1,6) 0-11608 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,14,1,15) 0-11638 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9) 0-11661 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2) 0-11698 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2) 0-11703 mgc_ioport.mgc_out_stdreg(2,30) 0-11706 mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2) 0-11710 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19) 0-11711}
+set a(0-9368-PROC_NAME) {core}
+set a(0-9368-HIER_NAME) {/sobel/core}
+set a(TOP) {0-9368}
+
diff --git a/Sobel/sobel.v12/schematic.nlv b/Sobel/sobel.v12/schematic.nlv
new file mode 100644
index 0000000..a2fd872
--- /dev/null
+++ b/Sobel/sobel.v12/schematic.nlv
@@ -0,0 +1,16656 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "sobel:core" "orig"
+load port {clk} input -attr xrf 62811 -attr oid 1 -attr vt d -attr @path {/sobel/sobel:core/clk}
+load port {en} input -attr xrf 62812 -attr oid 2 -attr vt d -attr @path {/sobel/sobel:core/en}
+load port {arst_n} input -attr xrf 62813 -attr oid 3 -attr vt d -attr @path {/sobel/sobel:core/arst_n}
+load portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} -attr xrf 62814 -attr oid 4 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} -attr xrf 62815 -attr oid 5 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load symbol "or(2,10)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,6)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(5:0)} input 6 {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(5:0)} input 6 {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,30)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(29:0)} input 30 {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(29:0)} input 30 {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(30,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(29:0)} input 30 {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(29:0)} input 30 {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(1,0,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,1,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,1,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,1,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(4,0,5,0,8)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,11,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(4,0,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,0,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,-1,7,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,2,1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,2,1,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,4,-1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,1,7,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,6,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,1,8,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,10,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(1,0,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,-1,11,-1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nand(2,1)" "INTERFACE" NAND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "and(3,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(11,1,11,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,1,12,1,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(13,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(12:0)} input 13 {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(12:0)} input 13 {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,5,1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,6,0,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,1,2,1,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,1,6,1,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,7,1,9)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,1,9,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(4,0,7,0,10)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,10,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(4,0,9,0,12)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,1,12,0,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,7,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,11,1,13)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(13,1,13,1,14)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(12:0)} input 13 {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(12:0)} input 13 {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(13:0)} output 14 {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(14,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(13:0)} input 14 {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(13:0)} input 14 {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(13:0)} output 14 {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(5,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(4:0)} input 5 {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(4:0)} input 5 {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(2,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(1:0)} input 2 {D(1)} {D(0)} \
+     portBus {DRa(1:0)} input 2 {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "reg(1,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(0:0)} input 1 {D(0)} \
+     portBus {DRa(0:0)} input 1 {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(7,0,7,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,0,8,0,9)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,9,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,10,0,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(11,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(10:0)} input 11 {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(10:0)} input 11 {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,1,8,0,9)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,9,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,2,-1,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,2,1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,1,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,4,1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,1,5,1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,6,1,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,0,9,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,10,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(12,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(11:0)} input 12 {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(11:0)} input 12 {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(10,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(9:0)} input 10 {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(9:0)} input 10 {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(90,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(89:0)} input 90 {D(89)} {D(88)} {D(87)} {D(86)} {D(85)} {D(84)} {D(83)} {D(82)} {D(81)} {D(80)} {D(79)} {D(78)} {D(77)} {D(76)} {D(75)} {D(74)} {D(73)} {D(72)} {D(71)} {D(70)} {D(69)} {D(68)} {D(67)} {D(66)} {D(65)} {D(64)} {D(63)} {D(62)} {D(61)} {D(60)} {D(59)} {D(58)} {D(57)} {D(56)} {D(55)} {D(54)} {D(53)} {D(52)} {D(51)} {D(50)} {D(49)} {D(48)} {D(47)} {D(46)} {D(45)} {D(44)} {D(43)} {D(42)} {D(41)} {D(40)} {D(39)} {D(38)} {D(37)} {D(36)} {D(35)} {D(34)} {D(33)} {D(32)} {D(31)} {D(30)} {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(89:0)} input 90 {DRa(89)} {DRa(88)} {DRa(87)} {DRa(86)} {DRa(85)} {DRa(84)} {DRa(83)} {DRa(82)} {DRa(81)} {DRa(80)} {DRa(79)} {DRa(78)} {DRa(77)} {DRa(76)} {DRa(75)} {DRa(74)} {DRa(73)} {DRa(72)} {DRa(71)} {DRa(70)} {DRa(69)} {DRa(68)} {DRa(67)} {DRa(66)} {DRa(65)} {DRa(64)} {DRa(63)} {DRa(62)} {DRa(61)} {DRa(60)} {DRa(59)} {DRa(58)} {DRa(57)} {DRa(56)} {DRa(55)} {DRa(54)} {DRa(53)} {DRa(52)} {DRa(51)} {DRa(50)} {DRa(49)} {DRa(48)} {DRa(47)} {DRa(46)} {DRa(45)} {DRa(44)} {DRa(43)} {DRa(42)} {DRa(41)} {DRa(40)} {DRa(39)} {DRa(38)} {DRa(37)} {DRa(36)} {DRa(35)} {DRa(34)} {DRa(33)} {DRa(32)} {DRa(31)} {DRa(30)} {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,6,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(3)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,-1,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,1,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,7,1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,0,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,-1,11,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(14,1,14,1,15)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(13:0)} input 14 {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(13:0)} input 14 {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(14,-1,13,1,14)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(13:0)} input 14 {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(12:0)} input 13 {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(13:0)} output 14 {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(15,-1,14,1,15)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(14:0)} input 15 {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(13:0)} input 14 {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,-1,6,-1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,10,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(10)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,2,0,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(2)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,1,1,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,12,1,14)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(13:0)} output 14 {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load net {regs.regs:slc(regs.regs(2)).itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2)).itm} 10 {regs.regs:slc(regs.regs(2)).itm(0)} {regs.regs:slc(regs.regs(2)).itm(1)} {regs.regs:slc(regs.regs(2)).itm(2)} {regs.regs:slc(regs.regs(2)).itm(3)} {regs.regs:slc(regs.regs(2)).itm(4)} {regs.regs:slc(regs.regs(2)).itm(5)} {regs.regs:slc(regs.regs(2)).itm(6)} {regs.regs:slc(regs.regs(2)).itm(7)} {regs.regs:slc(regs.regs(2)).itm(8)} {regs.regs:slc(regs.regs(2)).itm(9)} -attr xrf 62816 -attr oid 6 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#1.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#1.itm} 10 {regs.regs:slc(regs.regs(2))#1.itm(0)} {regs.regs:slc(regs.regs(2))#1.itm(1)} {regs.regs:slc(regs.regs(2))#1.itm(2)} {regs.regs:slc(regs.regs(2))#1.itm(3)} {regs.regs:slc(regs.regs(2))#1.itm(4)} {regs.regs:slc(regs.regs(2))#1.itm(5)} {regs.regs:slc(regs.regs(2))#1.itm(6)} {regs.regs:slc(regs.regs(2))#1.itm(7)} {regs.regs:slc(regs.regs(2))#1.itm(8)} {regs.regs:slc(regs.regs(2))#1.itm(9)} -attr xrf 62817 -attr oid 7 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#2.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#2.itm} 10 {regs.regs:slc(regs.regs(2))#2.itm(0)} {regs.regs:slc(regs.regs(2))#2.itm(1)} {regs.regs:slc(regs.regs(2))#2.itm(2)} {regs.regs:slc(regs.regs(2))#2.itm(3)} {regs.regs:slc(regs.regs(2))#2.itm(4)} {regs.regs:slc(regs.regs(2))#2.itm(5)} {regs.regs:slc(regs.regs(2))#2.itm(6)} {regs.regs:slc(regs.regs(2))#2.itm(7)} {regs.regs:slc(regs.regs(2))#2.itm(8)} {regs.regs:slc(regs.regs(2))#2.itm(9)} -attr xrf 62818 -attr oid 8 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#4.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#4.itm} 10 {regs.regs:slc(regs.regs(2))#4.itm(0)} {regs.regs:slc(regs.regs(2))#4.itm(1)} {regs.regs:slc(regs.regs(2))#4.itm(2)} {regs.regs:slc(regs.regs(2))#4.itm(3)} {regs.regs:slc(regs.regs(2))#4.itm(4)} {regs.regs:slc(regs.regs(2))#4.itm(5)} {regs.regs:slc(regs.regs(2))#4.itm(6)} {regs.regs:slc(regs.regs(2))#4.itm(7)} {regs.regs:slc(regs.regs(2))#4.itm(8)} {regs.regs:slc(regs.regs(2))#4.itm(9)} -attr xrf 62819 -attr oid 9 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#5.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#5.itm} 10 {regs.regs:slc(regs.regs(2))#5.itm(0)} {regs.regs:slc(regs.regs(2))#5.itm(1)} {regs.regs:slc(regs.regs(2))#5.itm(2)} {regs.regs:slc(regs.regs(2))#5.itm(3)} {regs.regs:slc(regs.regs(2))#5.itm(4)} {regs.regs:slc(regs.regs(2))#5.itm(5)} {regs.regs:slc(regs.regs(2))#5.itm(6)} {regs.regs:slc(regs.regs(2))#5.itm(7)} {regs.regs:slc(regs.regs(2))#5.itm(8)} {regs.regs:slc(regs.regs(2))#5.itm(9)} -attr xrf 62820 -attr oid 10 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#3.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#3.itm} 10 {regs.regs:slc(regs.regs(2))#3.itm(0)} {regs.regs:slc(regs.regs(2))#3.itm(1)} {regs.regs:slc(regs.regs(2))#3.itm(2)} {regs.regs:slc(regs.regs(2))#3.itm(3)} {regs.regs:slc(regs.regs(2))#3.itm(4)} {regs.regs:slc(regs.regs(2))#3.itm(5)} {regs.regs:slc(regs.regs(2))#3.itm(6)} {regs.regs:slc(regs.regs(2))#3.itm(7)} {regs.regs:slc(regs.regs(2))#3.itm(8)} {regs.regs:slc(regs.regs(2))#3.itm(9)} -attr xrf 62821 -attr oid 11 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#10.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#10.itm} 10 {regs.regs:slc(regs.regs(2))#10.itm(0)} {regs.regs:slc(regs.regs(2))#10.itm(1)} {regs.regs:slc(regs.regs(2))#10.itm(2)} {regs.regs:slc(regs.regs(2))#10.itm(3)} {regs.regs:slc(regs.regs(2))#10.itm(4)} {regs.regs:slc(regs.regs(2))#10.itm(5)} {regs.regs:slc(regs.regs(2))#10.itm(6)} {regs.regs:slc(regs.regs(2))#10.itm(7)} {regs.regs:slc(regs.regs(2))#10.itm(8)} {regs.regs:slc(regs.regs(2))#10.itm(9)} -attr xrf 62822 -attr oid 12 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#11.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#11.itm} 10 {regs.regs:slc(regs.regs(2))#11.itm(0)} {regs.regs:slc(regs.regs(2))#11.itm(1)} {regs.regs:slc(regs.regs(2))#11.itm(2)} {regs.regs:slc(regs.regs(2))#11.itm(3)} {regs.regs:slc(regs.regs(2))#11.itm(4)} {regs.regs:slc(regs.regs(2))#11.itm(5)} {regs.regs:slc(regs.regs(2))#11.itm(6)} {regs.regs:slc(regs.regs(2))#11.itm(7)} {regs.regs:slc(regs.regs(2))#11.itm(8)} {regs.regs:slc(regs.regs(2))#11.itm(9)} -attr xrf 62823 -attr oid 13 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#9.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#9.itm} 10 {regs.regs:slc(regs.regs(2))#9.itm(0)} {regs.regs:slc(regs.regs(2))#9.itm(1)} {regs.regs:slc(regs.regs(2))#9.itm(2)} {regs.regs:slc(regs.regs(2))#9.itm(3)} {regs.regs:slc(regs.regs(2))#9.itm(4)} {regs.regs:slc(regs.regs(2))#9.itm(5)} {regs.regs:slc(regs.regs(2))#9.itm(6)} {regs.regs:slc(regs.regs(2))#9.itm(7)} {regs.regs:slc(regs.regs(2))#9.itm(8)} {regs.regs:slc(regs.regs(2))#9.itm(9)} -attr xrf 62824 -attr oid 14 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {ACC1:acc#659.itm#1(0)} -attr vt d
+load net {ACC1:acc#659.itm#1(1)} -attr vt d
+load net {ACC1:acc#659.itm#1(2)} -attr vt d
+load net {ACC1:acc#659.itm#1(3)} -attr vt d
+load net {ACC1:acc#659.itm#1(4)} -attr vt d
+load net {ACC1:acc#659.itm#1(5)} -attr vt d
+load net {ACC1:acc#659.itm#1(6)} -attr vt d
+load net {ACC1:acc#659.itm#1(7)} -attr vt d
+load net {ACC1:acc#659.itm#1(8)} -attr vt d
+load net {ACC1:acc#659.itm#1(9)} -attr vt d
+load net {ACC1:acc#659.itm#1(10)} -attr vt d
+load net {ACC1:acc#659.itm#1(11)} -attr vt d
+load net {ACC1:acc#659.itm#1(12)} -attr vt d
+load netBundle {ACC1:acc#659.itm#1} 13 {ACC1:acc#659.itm#1(0)} {ACC1:acc#659.itm#1(1)} {ACC1:acc#659.itm#1(2)} {ACC1:acc#659.itm#1(3)} {ACC1:acc#659.itm#1(4)} {ACC1:acc#659.itm#1(5)} {ACC1:acc#659.itm#1(6)} {ACC1:acc#659.itm#1(7)} {ACC1:acc#659.itm#1(8)} {ACC1:acc#659.itm#1(9)} {ACC1:acc#659.itm#1(10)} {ACC1:acc#659.itm#1(11)} {ACC1:acc#659.itm#1(12)} -attr xrf 62825 -attr oid 15 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#658.itm#1(0)} -attr vt d
+load net {ACC1:acc#658.itm#1(1)} -attr vt d
+load net {ACC1:acc#658.itm#1(2)} -attr vt d
+load net {ACC1:acc#658.itm#1(3)} -attr vt d
+load net {ACC1:acc#658.itm#1(4)} -attr vt d
+load net {ACC1:acc#658.itm#1(5)} -attr vt d
+load net {ACC1:acc#658.itm#1(6)} -attr vt d
+load net {ACC1:acc#658.itm#1(7)} -attr vt d
+load net {ACC1:acc#658.itm#1(8)} -attr vt d
+load net {ACC1:acc#658.itm#1(9)} -attr vt d
+load net {ACC1:acc#658.itm#1(10)} -attr vt d
+load net {ACC1:acc#658.itm#1(11)} -attr vt d
+load net {ACC1:acc#658.itm#1(12)} -attr vt d
+load netBundle {ACC1:acc#658.itm#1} 13 {ACC1:acc#658.itm#1(0)} {ACC1:acc#658.itm#1(1)} {ACC1:acc#658.itm#1(2)} {ACC1:acc#658.itm#1(3)} {ACC1:acc#658.itm#1(4)} {ACC1:acc#658.itm#1(5)} {ACC1:acc#658.itm#1(6)} {ACC1:acc#658.itm#1(7)} {ACC1:acc#658.itm#1(8)} {ACC1:acc#658.itm#1(9)} {ACC1:acc#658.itm#1(10)} {ACC1:acc#658.itm#1(11)} {ACC1:acc#658.itm#1(12)} -attr xrf 62826 -attr oid 16 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#661.itm#1(0)} -attr vt d
+load net {ACC1:acc#661.itm#1(1)} -attr vt d
+load net {ACC1:acc#661.itm#1(2)} -attr vt d
+load net {ACC1:acc#661.itm#1(3)} -attr vt d
+load net {ACC1:acc#661.itm#1(4)} -attr vt d
+load net {ACC1:acc#661.itm#1(5)} -attr vt d
+load net {ACC1:acc#661.itm#1(6)} -attr vt d
+load net {ACC1:acc#661.itm#1(7)} -attr vt d
+load net {ACC1:acc#661.itm#1(8)} -attr vt d
+load net {ACC1:acc#661.itm#1(9)} -attr vt d
+load net {ACC1:acc#661.itm#1(10)} -attr vt d
+load net {ACC1:acc#661.itm#1(11)} -attr vt d
+load net {ACC1:acc#661.itm#1(12)} -attr vt d
+load net {ACC1:acc#661.itm#1(13)} -attr vt d
+load netBundle {ACC1:acc#661.itm#1} 14 {ACC1:acc#661.itm#1(0)} {ACC1:acc#661.itm#1(1)} {ACC1:acc#661.itm#1(2)} {ACC1:acc#661.itm#1(3)} {ACC1:acc#661.itm#1(4)} {ACC1:acc#661.itm#1(5)} {ACC1:acc#661.itm#1(6)} {ACC1:acc#661.itm#1(7)} {ACC1:acc#661.itm#1(8)} {ACC1:acc#661.itm#1(9)} {ACC1:acc#661.itm#1(10)} {ACC1:acc#661.itm#1(11)} {ACC1:acc#661.itm#1(12)} {ACC1:acc#661.itm#1(13)} -attr xrf 62827 -attr oid 17 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#652.itm#1(0)} -attr vt d
+load net {ACC1:acc#652.itm#1(1)} -attr vt d
+load net {ACC1:acc#652.itm#1(2)} -attr vt d
+load net {ACC1:acc#652.itm#1(3)} -attr vt d
+load net {ACC1:acc#652.itm#1(4)} -attr vt d
+load net {ACC1:acc#652.itm#1(5)} -attr vt d
+load net {ACC1:acc#652.itm#1(6)} -attr vt d
+load net {ACC1:acc#652.itm#1(7)} -attr vt d
+load net {ACC1:acc#652.itm#1(8)} -attr vt d
+load net {ACC1:acc#652.itm#1(9)} -attr vt d
+load net {ACC1:acc#652.itm#1(10)} -attr vt d
+load netBundle {ACC1:acc#652.itm#1} 11 {ACC1:acc#652.itm#1(0)} {ACC1:acc#652.itm#1(1)} {ACC1:acc#652.itm#1(2)} {ACC1:acc#652.itm#1(3)} {ACC1:acc#652.itm#1(4)} {ACC1:acc#652.itm#1(5)} {ACC1:acc#652.itm#1(6)} {ACC1:acc#652.itm#1(7)} {ACC1:acc#652.itm#1(8)} {ACC1:acc#652.itm#1(9)} {ACC1:acc#652.itm#1(10)} -attr xrf 62828 -attr oid 18 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#655.itm#1(0)} -attr vt d
+load net {ACC1:acc#655.itm#1(1)} -attr vt d
+load net {ACC1:acc#655.itm#1(2)} -attr vt d
+load net {ACC1:acc#655.itm#1(3)} -attr vt d
+load net {ACC1:acc#655.itm#1(4)} -attr vt d
+load net {ACC1:acc#655.itm#1(5)} -attr vt d
+load net {ACC1:acc#655.itm#1(6)} -attr vt d
+load net {ACC1:acc#655.itm#1(7)} -attr vt d
+load net {ACC1:acc#655.itm#1(8)} -attr vt d
+load net {ACC1:acc#655.itm#1(9)} -attr vt d
+load net {ACC1:acc#655.itm#1(10)} -attr vt d
+load net {ACC1:acc#655.itm#1(11)} -attr vt d
+load netBundle {ACC1:acc#655.itm#1} 12 {ACC1:acc#655.itm#1(0)} {ACC1:acc#655.itm#1(1)} {ACC1:acc#655.itm#1(2)} {ACC1:acc#655.itm#1(3)} {ACC1:acc#655.itm#1(4)} {ACC1:acc#655.itm#1(5)} {ACC1:acc#655.itm#1(6)} {ACC1:acc#655.itm#1(7)} {ACC1:acc#655.itm#1(8)} {ACC1:acc#655.itm#1(9)} {ACC1:acc#655.itm#1(10)} {ACC1:acc#655.itm#1(11)} -attr xrf 62829 -attr oid 19 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:mul#57.itm#1.sg2(0)} -attr vt d
+load net {ACC1:mul#57.itm#1.sg2(1)} -attr vt d
+load net {ACC1:mul#57.itm#1.sg2(2)} -attr vt d
+load net {ACC1:mul#57.itm#1.sg2(3)} -attr vt d
+load net {ACC1:mul#57.itm#1.sg2(4)} -attr vt d
+load netBundle {ACC1:mul#57.itm#1.sg2} 5 {ACC1:mul#57.itm#1.sg2(0)} {ACC1:mul#57.itm#1.sg2(1)} {ACC1:mul#57.itm#1.sg2(2)} {ACC1:mul#57.itm#1.sg2(3)} {ACC1:mul#57.itm#1.sg2(4)} -attr xrf 62830 -attr oid 20 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#1.sg2}
+load net {ACC1:mul#57.itm#2(0)} -attr vt d
+load net {ACC1:mul#57.itm#2(1)} -attr vt d
+load netBundle {ACC1:mul#57.itm#2} 2 {ACC1:mul#57.itm#2(0)} {ACC1:mul#57.itm#2(1)} -attr xrf 62831 -attr oid 21 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#2}
+load net {reg(regs.regs(0).sva).cse(0)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(1)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(2)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(3)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(4)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(5)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(6)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(7)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(8)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(9)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(10)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(11)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(12)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(13)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(14)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(15)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(16)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(17)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(18)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(19)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(20)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(21)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(22)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(23)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(24)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(25)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(26)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(27)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(28)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(29)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(30)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(31)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(32)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(33)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(34)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(35)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(36)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(37)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(38)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(39)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(40)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(41)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(42)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(43)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(44)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(45)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(46)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(47)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(48)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(49)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(50)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(51)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(52)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(53)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(54)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(55)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(56)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(57)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(58)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(59)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(60)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(61)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(62)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(63)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(64)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(65)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(66)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(67)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(68)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(69)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(70)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(71)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(72)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(73)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(74)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(75)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(76)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(77)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(78)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(79)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(80)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(81)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(82)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(83)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(84)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(85)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(86)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(87)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(88)} -attr vt d
+load net {reg(regs.regs(0).sva).cse(89)} -attr vt d
+load netBundle {reg(regs.regs(0).sva).cse} 90 {reg(regs.regs(0).sva).cse(0)} {reg(regs.regs(0).sva).cse(1)} {reg(regs.regs(0).sva).cse(2)} {reg(regs.regs(0).sva).cse(3)} {reg(regs.regs(0).sva).cse(4)} {reg(regs.regs(0).sva).cse(5)} {reg(regs.regs(0).sva).cse(6)} {reg(regs.regs(0).sva).cse(7)} {reg(regs.regs(0).sva).cse(8)} {reg(regs.regs(0).sva).cse(9)} {reg(regs.regs(0).sva).cse(10)} {reg(regs.regs(0).sva).cse(11)} {reg(regs.regs(0).sva).cse(12)} {reg(regs.regs(0).sva).cse(13)} {reg(regs.regs(0).sva).cse(14)} {reg(regs.regs(0).sva).cse(15)} {reg(regs.regs(0).sva).cse(16)} {reg(regs.regs(0).sva).cse(17)} {reg(regs.regs(0).sva).cse(18)} {reg(regs.regs(0).sva).cse(19)} {reg(regs.regs(0).sva).cse(20)} {reg(regs.regs(0).sva).cse(21)} {reg(regs.regs(0).sva).cse(22)} {reg(regs.regs(0).sva).cse(23)} {reg(regs.regs(0).sva).cse(24)} {reg(regs.regs(0).sva).cse(25)} {reg(regs.regs(0).sva).cse(26)} {reg(regs.regs(0).sva).cse(27)} {reg(regs.regs(0).sva).cse(28)} {reg(regs.regs(0).sva).cse(29)} {reg(regs.regs(0).sva).cse(30)} {reg(regs.regs(0).sva).cse(31)} {reg(regs.regs(0).sva).cse(32)} {reg(regs.regs(0).sva).cse(33)} {reg(regs.regs(0).sva).cse(34)} {reg(regs.regs(0).sva).cse(35)} {reg(regs.regs(0).sva).cse(36)} {reg(regs.regs(0).sva).cse(37)} {reg(regs.regs(0).sva).cse(38)} {reg(regs.regs(0).sva).cse(39)} {reg(regs.regs(0).sva).cse(40)} {reg(regs.regs(0).sva).cse(41)} {reg(regs.regs(0).sva).cse(42)} {reg(regs.regs(0).sva).cse(43)} {reg(regs.regs(0).sva).cse(44)} {reg(regs.regs(0).sva).cse(45)} {reg(regs.regs(0).sva).cse(46)} {reg(regs.regs(0).sva).cse(47)} {reg(regs.regs(0).sva).cse(48)} {reg(regs.regs(0).sva).cse(49)} {reg(regs.regs(0).sva).cse(50)} {reg(regs.regs(0).sva).cse(51)} {reg(regs.regs(0).sva).cse(52)} {reg(regs.regs(0).sva).cse(53)} {reg(regs.regs(0).sva).cse(54)} {reg(regs.regs(0).sva).cse(55)} {reg(regs.regs(0).sva).cse(56)} {reg(regs.regs(0).sva).cse(57)} {reg(regs.regs(0).sva).cse(58)} {reg(regs.regs(0).sva).cse(59)} {reg(regs.regs(0).sva).cse(60)} {reg(regs.regs(0).sva).cse(61)} {reg(regs.regs(0).sva).cse(62)} {reg(regs.regs(0).sva).cse(63)} {reg(regs.regs(0).sva).cse(64)} {reg(regs.regs(0).sva).cse(65)} {reg(regs.regs(0).sva).cse(66)} {reg(regs.regs(0).sva).cse(67)} {reg(regs.regs(0).sva).cse(68)} {reg(regs.regs(0).sva).cse(69)} {reg(regs.regs(0).sva).cse(70)} {reg(regs.regs(0).sva).cse(71)} {reg(regs.regs(0).sva).cse(72)} {reg(regs.regs(0).sva).cse(73)} {reg(regs.regs(0).sva).cse(74)} {reg(regs.regs(0).sva).cse(75)} {reg(regs.regs(0).sva).cse(76)} {reg(regs.regs(0).sva).cse(77)} {reg(regs.regs(0).sva).cse(78)} {reg(regs.regs(0).sva).cse(79)} {reg(regs.regs(0).sva).cse(80)} {reg(regs.regs(0).sva).cse(81)} {reg(regs.regs(0).sva).cse(82)} {reg(regs.regs(0).sva).cse(83)} {reg(regs.regs(0).sva).cse(84)} {reg(regs.regs(0).sva).cse(85)} {reg(regs.regs(0).sva).cse(86)} {reg(regs.regs(0).sva).cse(87)} {reg(regs.regs(0).sva).cse(88)} {reg(regs.regs(0).sva).cse(89)} -attr xrf 62832 -attr oid 22 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {FRAME:acc#2.psp.sva(0)} -attr vt d
+load net {FRAME:acc#2.psp.sva(1)} -attr vt d
+load net {FRAME:acc#2.psp.sva(2)} -attr vt d
+load net {FRAME:acc#2.psp.sva(3)} -attr vt d
+load net {FRAME:acc#2.psp.sva(4)} -attr vt d
+load net {FRAME:acc#2.psp.sva(5)} -attr vt d
+load net {FRAME:acc#2.psp.sva(6)} -attr vt d
+load net {FRAME:acc#2.psp.sva(7)} -attr vt d
+load net {FRAME:acc#2.psp.sva(8)} -attr vt d
+load net {FRAME:acc#2.psp.sva(9)} -attr vt d
+load net {FRAME:acc#2.psp.sva(10)} -attr vt d
+load net {FRAME:acc#2.psp.sva(11)} -attr vt d
+load netBundle {FRAME:acc#2.psp.sva} 12 {FRAME:acc#2.psp.sva(0)} {FRAME:acc#2.psp.sva(1)} {FRAME:acc#2.psp.sva(2)} {FRAME:acc#2.psp.sva(3)} {FRAME:acc#2.psp.sva(4)} {FRAME:acc#2.psp.sva(5)} {FRAME:acc#2.psp.sva(6)} {FRAME:acc#2.psp.sva(7)} {FRAME:acc#2.psp.sva(8)} {FRAME:acc#2.psp.sva(9)} {FRAME:acc#2.psp.sva(10)} {FRAME:acc#2.psp.sva(11)} -attr xrf 62833 -attr oid 23 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {ACC1:slc.psp.sva(0)} -attr vt d
+load net {ACC1:slc.psp.sva(1)} -attr vt d
+load net {ACC1:slc.psp.sva(2)} -attr vt d
+load net {ACC1:slc.psp.sva(3)} -attr vt d
+load net {ACC1:slc.psp.sva(4)} -attr vt d
+load net {ACC1:slc.psp.sva(5)} -attr vt d
+load net {ACC1:slc.psp.sva(6)} -attr vt d
+load net {ACC1:slc.psp.sva(7)} -attr vt d
+load net {ACC1:slc.psp.sva(8)} -attr vt d
+load net {ACC1:slc.psp.sva(9)} -attr vt d
+load net {ACC1:slc.psp.sva(10)} -attr vt d
+load net {ACC1:slc.psp.sva(11)} -attr vt d
+load net {ACC1:slc.psp.sva(12)} -attr vt d
+load net {ACC1:slc.psp.sva(13)} -attr vt d
+load netBundle {ACC1:slc.psp.sva} 14 {ACC1:slc.psp.sva(0)} {ACC1:slc.psp.sva(1)} {ACC1:slc.psp.sva(2)} {ACC1:slc.psp.sva(3)} {ACC1:slc.psp.sva(4)} {ACC1:slc.psp.sva(5)} {ACC1:slc.psp.sva(6)} {ACC1:slc.psp.sva(7)} {ACC1:slc.psp.sva(8)} {ACC1:slc.psp.sva(9)} {ACC1:slc.psp.sva(10)} {ACC1:slc.psp.sva(11)} {ACC1:slc.psp.sva(12)} {ACC1:slc.psp.sva(13)} -attr xrf 62834 -attr oid 24 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.psp.sva}
+load net {acc.imod#24.sva(0)} -attr vt d
+load net {acc.imod#24.sva(1)} -attr vt d
+load net {acc.imod#24.sva(2)} -attr vt d
+load net {acc.imod#24.sva(3)} -attr vt d
+load net {acc.imod#24.sva(4)} -attr vt d
+load net {acc.imod#24.sva(5)} -attr vt d
+load netBundle {acc.imod#24.sva} 6 {acc.imod#24.sva(0)} {acc.imod#24.sva(1)} {acc.imod#24.sva(2)} {acc.imod#24.sva(3)} {acc.imod#24.sva(4)} {acc.imod#24.sva(5)} -attr xrf 62835 -attr oid 25 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load net {ACC1:acc#228.psp.sva(0)} -attr vt d
+load net {ACC1:acc#228.psp.sva(1)} -attr vt d
+load net {ACC1:acc#228.psp.sva(2)} -attr vt d
+load net {ACC1:acc#228.psp.sva(3)} -attr vt d
+load net {ACC1:acc#228.psp.sva(4)} -attr vt d
+load net {ACC1:acc#228.psp.sva(5)} -attr vt d
+load net {ACC1:acc#228.psp.sva(6)} -attr vt d
+load net {ACC1:acc#228.psp.sva(7)} -attr vt d
+load net {ACC1:acc#228.psp.sva(8)} -attr vt d
+load net {ACC1:acc#228.psp.sva(9)} -attr vt d
+load net {ACC1:acc#228.psp.sva(10)} -attr vt d
+load net {ACC1:acc#228.psp.sva(11)} -attr vt d
+load netBundle {ACC1:acc#228.psp.sva} 12 {ACC1:acc#228.psp.sva(0)} {ACC1:acc#228.psp.sva(1)} {ACC1:acc#228.psp.sva(2)} {ACC1:acc#228.psp.sva(3)} {ACC1:acc#228.psp.sva(4)} {ACC1:acc#228.psp.sva(5)} {ACC1:acc#228.psp.sva(6)} {ACC1:acc#228.psp.sva(7)} {ACC1:acc#228.psp.sva(8)} {ACC1:acc#228.psp.sva(9)} {ACC1:acc#228.psp.sva(10)} {ACC1:acc#228.psp.sva(11)} -attr xrf 62836 -attr oid 26 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#509.cse(0)} -attr vt d
+load net {ACC1:acc#509.cse(1)} -attr vt d
+load net {ACC1:acc#509.cse(2)} -attr vt d
+load netBundle {ACC1:acc#509.cse} 3 {ACC1:acc#509.cse(0)} {ACC1:acc#509.cse(1)} {ACC1:acc#509.cse(2)} -attr xrf 62837 -attr oid 27 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#506.cse(0)} -attr vt d
+load net {ACC1:acc#506.cse(1)} -attr vt d
+load net {ACC1:acc#506.cse(2)} -attr vt d
+load netBundle {ACC1:acc#506.cse} 3 {ACC1:acc#506.cse(0)} {ACC1:acc#506.cse(1)} {ACC1:acc#506.cse(2)} -attr xrf 62838 -attr oid 28 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#562.ncse(0)} -attr vt d
+load net {ACC1:acc#562.ncse(1)} -attr vt d
+load net {ACC1:acc#562.ncse(2)} -attr vt d
+load net {ACC1:acc#562.ncse(3)} -attr vt d
+load netBundle {ACC1:acc#562.ncse} 4 {ACC1:acc#562.ncse(0)} {ACC1:acc#562.ncse(1)} {ACC1:acc#562.ncse(2)} {ACC1:acc#562.ncse(3)} -attr xrf 62839 -attr oid 29 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#502.cse(0)} -attr vt d
+load net {ACC1:acc#502.cse(1)} -attr vt d
+load net {ACC1:acc#502.cse(2)} -attr vt d
+load netBundle {ACC1:acc#502.cse} 3 {ACC1:acc#502.cse(0)} {ACC1:acc#502.cse(1)} {ACC1:acc#502.cse(2)} -attr xrf 62840 -attr oid 30 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#489.cse(0)} -attr vt d
+load net {ACC1:acc#489.cse(1)} -attr vt d
+load net {ACC1:acc#489.cse(2)} -attr vt d
+load netBundle {ACC1:acc#489.cse} 3 {ACC1:acc#489.cse(0)} {ACC1:acc#489.cse(1)} {ACC1:acc#489.cse(2)} -attr xrf 62841 -attr oid 31 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#226.psp.sva(0)} -attr vt d
+load net {ACC1:acc#226.psp.sva(1)} -attr vt d
+load net {ACC1:acc#226.psp.sva(2)} -attr vt d
+load net {ACC1:acc#226.psp.sva(3)} -attr vt d
+load net {ACC1:acc#226.psp.sva(4)} -attr vt d
+load net {ACC1:acc#226.psp.sva(5)} -attr vt d
+load net {ACC1:acc#226.psp.sva(6)} -attr vt d
+load net {ACC1:acc#226.psp.sva(7)} -attr vt d
+load net {ACC1:acc#226.psp.sva(8)} -attr vt d
+load net {ACC1:acc#226.psp.sva(9)} -attr vt d
+load net {ACC1:acc#226.psp.sva(10)} -attr vt d
+load net {ACC1:acc#226.psp.sva(11)} -attr vt d
+load netBundle {ACC1:acc#226.psp.sva} 12 {ACC1:acc#226.psp.sva(0)} {ACC1:acc#226.psp.sva(1)} {ACC1:acc#226.psp.sva(2)} {ACC1:acc#226.psp.sva(3)} {ACC1:acc#226.psp.sva(4)} {ACC1:acc#226.psp.sva(5)} {ACC1:acc#226.psp.sva(6)} {ACC1:acc#226.psp.sva(7)} {ACC1:acc#226.psp.sva(8)} {ACC1:acc#226.psp.sva(9)} {ACC1:acc#226.psp.sva(10)} {ACC1:acc#226.psp.sva(11)} -attr xrf 62842 -attr oid 32 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#553.ncse(0)} -attr vt d
+load net {ACC1:acc#553.ncse(1)} -attr vt d
+load net {ACC1:acc#553.ncse(2)} -attr vt d
+load net {ACC1:acc#553.ncse(3)} -attr vt d
+load netBundle {ACC1:acc#553.ncse} 4 {ACC1:acc#553.ncse(0)} {ACC1:acc#553.ncse(1)} {ACC1:acc#553.ncse(2)} {ACC1:acc#553.ncse(3)} -attr xrf 62843 -attr oid 33 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#224.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(2)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(3)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(4)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(5)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(6)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(7)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(8)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(9)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(10)} -attr vt d
+load net {ACC1:acc#224.psp#1.sva(11)} -attr vt d
+load netBundle {ACC1:acc#224.psp#1.sva} 12 {ACC1:acc#224.psp#1.sva(0)} {ACC1:acc#224.psp#1.sva(1)} {ACC1:acc#224.psp#1.sva(2)} {ACC1:acc#224.psp#1.sva(3)} {ACC1:acc#224.psp#1.sva(4)} {ACC1:acc#224.psp#1.sva(5)} {ACC1:acc#224.psp#1.sva(6)} {ACC1:acc#224.psp#1.sva(7)} {ACC1:acc#224.psp#1.sva(8)} {ACC1:acc#224.psp#1.sva(9)} {ACC1:acc#224.psp#1.sva(10)} {ACC1:acc#224.psp#1.sva(11)} -attr xrf 62844 -attr oid 34 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp.sva(0)} -attr vt d
+load net {ACC1:acc#224.psp.sva(1)} -attr vt d
+load net {ACC1:acc#224.psp.sva(2)} -attr vt d
+load net {ACC1:acc#224.psp.sva(3)} -attr vt d
+load net {ACC1:acc#224.psp.sva(4)} -attr vt d
+load net {ACC1:acc#224.psp.sva(5)} -attr vt d
+load net {ACC1:acc#224.psp.sva(6)} -attr vt d
+load net {ACC1:acc#224.psp.sva(7)} -attr vt d
+load net {ACC1:acc#224.psp.sva(8)} -attr vt d
+load net {ACC1:acc#224.psp.sva(9)} -attr vt d
+load net {ACC1:acc#224.psp.sva(10)} -attr vt d
+load net {ACC1:acc#224.psp.sva(11)} -attr vt d
+load netBundle {ACC1:acc#224.psp.sva} 12 {ACC1:acc#224.psp.sva(0)} {ACC1:acc#224.psp.sva(1)} {ACC1:acc#224.psp.sva(2)} {ACC1:acc#224.psp.sva(3)} {ACC1:acc#224.psp.sva(4)} {ACC1:acc#224.psp.sva(5)} {ACC1:acc#224.psp.sva(6)} {ACC1:acc#224.psp.sva(7)} {ACC1:acc#224.psp.sva(8)} {ACC1:acc#224.psp.sva(9)} {ACC1:acc#224.psp.sva(10)} {ACC1:acc#224.psp.sva(11)} -attr xrf 62845 -attr oid 35 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#516.cse(0)} -attr vt d
+load net {ACC1:acc#516.cse(1)} -attr vt d
+load net {ACC1:acc#516.cse(2)} -attr vt d
+load netBundle {ACC1:acc#516.cse} 3 {ACC1:acc#516.cse(0)} {ACC1:acc#516.cse(1)} {ACC1:acc#516.cse(2)} -attr xrf 62846 -attr oid 36 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#221.psp.sva(0)} -attr vt d
+load net {ACC1:acc#221.psp.sva(1)} -attr vt d
+load net {ACC1:acc#221.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#221.psp.sva} 3 {ACC1:acc#221.psp.sva(0)} {ACC1:acc#221.psp.sva(1)} {ACC1:acc#221.psp.sva(2)} -attr xrf 62847 -attr oid 37 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp.sva}
+load net {ACC1:acc#221.psp#2.sva(0)} -attr vt d
+load net {ACC1:acc#221.psp#2.sva(1)} -attr vt d
+load net {ACC1:acc#221.psp#2.sva(2)} -attr vt d
+load netBundle {ACC1:acc#221.psp#2.sva} 3 {ACC1:acc#221.psp#2.sva(0)} {ACC1:acc#221.psp#2.sva(1)} {ACC1:acc#221.psp#2.sva(2)} -attr xrf 62848 -attr oid 38 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp#2.sva}
+load net {ACC1:acc#219.psp#2.sva(0)} -attr vt d
+load net {ACC1:acc#219.psp#2.sva(1)} -attr vt d
+load net {ACC1:acc#219.psp#2.sva(2)} -attr vt d
+load netBundle {ACC1:acc#219.psp#2.sva} 3 {ACC1:acc#219.psp#2.sva(0)} {ACC1:acc#219.psp#2.sva(1)} {ACC1:acc#219.psp#2.sva(2)} -attr xrf 62849 -attr oid 39 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#2.sva}
+load net {ACC1:acc#222.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#222.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#222.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#222.psp#1.sva} 3 {ACC1:acc#222.psp#1.sva(0)} {ACC1:acc#222.psp#1.sva(1)} {ACC1:acc#222.psp#1.sva(2)} -attr xrf 62850 -attr oid 40 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp#1.sva}
+load net {ACC1:acc#219.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#219.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#219.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#219.psp#1.sva} 3 {ACC1:acc#219.psp#1.sva(0)} {ACC1:acc#219.psp#1.sva(1)} {ACC1:acc#219.psp#1.sva(2)} -attr xrf 62851 -attr oid 41 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#1.sva}
+load net {ACC1:acc#724.cse(0)} -attr vt d
+load net {ACC1:acc#724.cse(1)} -attr vt d
+load net {ACC1:acc#724.cse(2)} -attr vt d
+load netBundle {ACC1:acc#724.cse} 3 {ACC1:acc#724.cse(0)} {ACC1:acc#724.cse(1)} {ACC1:acc#724.cse(2)} -attr xrf 62852 -attr oid 42 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#724.cse}
+load net {ACC1:mul#57.itm(0)} -attr vt d
+load net {ACC1:mul#57.itm(1)} -attr vt d
+load net {ACC1:mul#57.itm(2)} -attr vt d
+load net {ACC1:mul#57.itm(3)} -attr vt d
+load net {ACC1:mul#57.itm(4)} -attr vt d
+load net {ACC1:mul#57.itm(5)} -attr vt d
+load net {ACC1:mul#57.itm(6)} -attr vt d
+load net {ACC1:mul#57.itm(7)} -attr vt d
+load net {ACC1:mul#57.itm(8)} -attr vt d
+load net {ACC1:mul#57.itm(9)} -attr vt d
+load net {ACC1:mul#57.itm(10)} -attr vt d
+load net {ACC1:mul#57.itm(11)} -attr vt d
+load net {ACC1:mul#57.itm(12)} -attr vt d
+load net {ACC1:mul#57.itm(13)} -attr vt d
+load netBundle {ACC1:mul#57.itm} 14 {ACC1:mul#57.itm(0)} {ACC1:mul#57.itm(1)} {ACC1:mul#57.itm(2)} {ACC1:mul#57.itm(3)} {ACC1:mul#57.itm(4)} {ACC1:mul#57.itm(5)} {ACC1:mul#57.itm(6)} {ACC1:mul#57.itm(7)} {ACC1:mul#57.itm(8)} {ACC1:mul#57.itm(9)} {ACC1:mul#57.itm(10)} {ACC1:mul#57.itm(11)} {ACC1:mul#57.itm(12)} {ACC1:mul#57.itm(13)} -attr xrf 62853 -attr oid 43 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:acc#223.psp.sva(0)} -attr vt d
+load net {ACC1:acc#223.psp.sva(1)} -attr vt d
+load net {ACC1:acc#223.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#223.psp.sva} 3 {ACC1:acc#223.psp.sva(0)} {ACC1:acc#223.psp.sva(1)} {ACC1:acc#223.psp.sva(2)} -attr xrf 62854 -attr oid 44 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp.sva}
+load net {ACC1:acc#220.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#220.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#220.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#220.psp#1.sva} 3 {ACC1:acc#220.psp#1.sva(0)} {ACC1:acc#220.psp#1.sva(1)} {ACC1:acc#220.psp#1.sva(2)} -attr xrf 62855 -attr oid 45 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.psp#1.sva}
+load net {ACC1:acc#220.psp.sva(0)} -attr vt d
+load net {ACC1:acc#220.psp.sva(1)} -attr vt d
+load net {ACC1:acc#220.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#220.psp.sva} 3 {ACC1:acc#220.psp.sva(0)} {ACC1:acc#220.psp.sva(1)} {ACC1:acc#220.psp.sva(2)} -attr xrf 62856 -attr oid 46 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.psp.sva}
+load net {ACC1:acc#222.psp.sva(0)} -attr vt d
+load net {ACC1:acc#222.psp.sva(1)} -attr vt d
+load net {ACC1:acc#222.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#222.psp.sva} 3 {ACC1:acc#222.psp.sva(0)} {ACC1:acc#222.psp.sva(1)} {ACC1:acc#222.psp.sva(2)} -attr xrf 62857 -attr oid 47 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp.sva}
+load net {ACC1:acc#673.cse(0)} -attr vt d
+load net {ACC1:acc#673.cse(1)} -attr vt d
+load net {ACC1:acc#673.cse(2)} -attr vt d
+load netBundle {ACC1:acc#673.cse} 3 {ACC1:acc#673.cse(0)} {ACC1:acc#673.cse(1)} {ACC1:acc#673.cse(2)} -attr xrf 62858 -attr oid 48 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#223.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#223.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#223.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#223.psp#1.sva} 3 {ACC1:acc#223.psp#1.sva(0)} {ACC1:acc#223.psp#1.sva(1)} {ACC1:acc#223.psp#1.sva(2)} -attr xrf 62859 -attr oid 49 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp#1.sva}
+load net {ACC1:acc#699.cse(0)} -attr vt d
+load net {ACC1:acc#699.cse(1)} -attr vt d
+load net {ACC1:acc#699.cse(2)} -attr vt d
+load netBundle {ACC1:acc#699.cse} 3 {ACC1:acc#699.cse(0)} {ACC1:acc#699.cse(1)} {ACC1:acc#699.cse(2)} -attr xrf 62860 -attr oid 50 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {mux.itm(0)} -attr vt d
+load net {mux.itm(1)} -attr vt d
+load net {mux.itm(2)} -attr vt d
+load net {mux.itm(3)} -attr vt d
+load net {mux.itm(4)} -attr vt d
+load net {mux.itm(5)} -attr vt d
+load net {mux.itm(6)} -attr vt d
+load net {mux.itm(7)} -attr vt d
+load net {mux.itm(8)} -attr vt d
+load net {mux.itm(9)} -attr vt d
+load net {mux.itm(10)} -attr vt d
+load net {mux.itm(11)} -attr vt d
+load net {mux.itm(12)} -attr vt d
+load net {mux.itm(13)} -attr vt d
+load net {mux.itm(14)} -attr vt d
+load net {mux.itm(15)} -attr vt d
+load net {mux.itm(16)} -attr vt d
+load net {mux.itm(17)} -attr vt d
+load net {mux.itm(18)} -attr vt d
+load net {mux.itm(19)} -attr vt d
+load net {mux.itm(20)} -attr vt d
+load net {mux.itm(21)} -attr vt d
+load net {mux.itm(22)} -attr vt d
+load net {mux.itm(23)} -attr vt d
+load net {mux.itm(24)} -attr vt d
+load net {mux.itm(25)} -attr vt d
+load net {mux.itm(26)} -attr vt d
+load net {mux.itm(27)} -attr vt d
+load net {mux.itm(28)} -attr vt d
+load net {mux.itm(29)} -attr vt d
+load netBundle {mux.itm} 30 {mux.itm(0)} {mux.itm(1)} {mux.itm(2)} {mux.itm(3)} {mux.itm(4)} {mux.itm(5)} {mux.itm(6)} {mux.itm(7)} {mux.itm(8)} {mux.itm(9)} {mux.itm(10)} {mux.itm(11)} {mux.itm(12)} {mux.itm(13)} {mux.itm(14)} {mux.itm(15)} {mux.itm(16)} {mux.itm(17)} {mux.itm(18)} {mux.itm(19)} {mux.itm(20)} {mux.itm(21)} {mux.itm(22)} {mux.itm(23)} {mux.itm(24)} {mux.itm(25)} {mux.itm(26)} {mux.itm(27)} {mux.itm(28)} {mux.itm(29)} -attr xrf 62861 -attr oid 51 -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {FRAME:conc#11.itm(0)} -attr vt d
+load net {FRAME:conc#11.itm(1)} -attr vt d
+load net {FRAME:conc#11.itm(2)} -attr vt d
+load net {FRAME:conc#11.itm(3)} -attr vt d
+load net {FRAME:conc#11.itm(4)} -attr vt d
+load net {FRAME:conc#11.itm(5)} -attr vt d
+load net {FRAME:conc#11.itm(6)} -attr vt d
+load net {FRAME:conc#11.itm(7)} -attr vt d
+load net {FRAME:conc#11.itm(8)} -attr vt d
+load net {FRAME:conc#11.itm(9)} -attr vt d
+load net {FRAME:conc#11.itm(10)} -attr vt d
+load net {FRAME:conc#11.itm(11)} -attr vt d
+load net {FRAME:conc#11.itm(12)} -attr vt d
+load net {FRAME:conc#11.itm(13)} -attr vt d
+load net {FRAME:conc#11.itm(14)} -attr vt d
+load net {FRAME:conc#11.itm(15)} -attr vt d
+load net {FRAME:conc#11.itm(16)} -attr vt d
+load net {FRAME:conc#11.itm(17)} -attr vt d
+load net {FRAME:conc#11.itm(18)} -attr vt d
+load net {FRAME:conc#11.itm(19)} -attr vt d
+load net {FRAME:conc#11.itm(20)} -attr vt d
+load net {FRAME:conc#11.itm(21)} -attr vt d
+load net {FRAME:conc#11.itm(22)} -attr vt d
+load net {FRAME:conc#11.itm(23)} -attr vt d
+load net {FRAME:conc#11.itm(24)} -attr vt d
+load net {FRAME:conc#11.itm(25)} -attr vt d
+load net {FRAME:conc#11.itm(26)} -attr vt d
+load net {FRAME:conc#11.itm(27)} -attr vt d
+load net {FRAME:conc#11.itm(28)} -attr vt d
+load net {FRAME:conc#11.itm(29)} -attr vt d
+load netBundle {FRAME:conc#11.itm} 30 {FRAME:conc#11.itm(0)} {FRAME:conc#11.itm(1)} {FRAME:conc#11.itm(2)} {FRAME:conc#11.itm(3)} {FRAME:conc#11.itm(4)} {FRAME:conc#11.itm(5)} {FRAME:conc#11.itm(6)} {FRAME:conc#11.itm(7)} {FRAME:conc#11.itm(8)} {FRAME:conc#11.itm(9)} {FRAME:conc#11.itm(10)} {FRAME:conc#11.itm(11)} {FRAME:conc#11.itm(12)} {FRAME:conc#11.itm(13)} {FRAME:conc#11.itm(14)} {FRAME:conc#11.itm(15)} {FRAME:conc#11.itm(16)} {FRAME:conc#11.itm(17)} {FRAME:conc#11.itm(18)} {FRAME:conc#11.itm(19)} {FRAME:conc#11.itm(20)} {FRAME:conc#11.itm(21)} {FRAME:conc#11.itm(22)} {FRAME:conc#11.itm(23)} {FRAME:conc#11.itm(24)} {FRAME:conc#11.itm(25)} {FRAME:conc#11.itm(26)} {FRAME:conc#11.itm(27)} {FRAME:conc#11.itm(28)} {FRAME:conc#11.itm(29)} -attr xrf 62862 -attr oid 52 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(0)} -attr vt d
+load net {FRAME:or.itm(1)} -attr vt d
+load net {FRAME:or.itm(2)} -attr vt d
+load net {FRAME:or.itm(3)} -attr vt d
+load net {FRAME:or.itm(4)} -attr vt d
+load net {FRAME:or.itm(5)} -attr vt d
+load net {FRAME:or.itm(6)} -attr vt d
+load net {FRAME:or.itm(7)} -attr vt d
+load net {FRAME:or.itm(8)} -attr vt d
+load net {FRAME:or.itm(9)} -attr vt d
+load netBundle {FRAME:or.itm} 10 {FRAME:or.itm(0)} {FRAME:or.itm(1)} {FRAME:or.itm(2)} {FRAME:or.itm(3)} {FRAME:or.itm(4)} {FRAME:or.itm(5)} {FRAME:or.itm(6)} {FRAME:or.itm(7)} {FRAME:or.itm(8)} {FRAME:or.itm(9)} -attr xrf 62863 -attr oid 53 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(3)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(4)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(5)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(6)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(7)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(8)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(9)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#4.itm} 10 {slc(FRAME:acc#2.psp.sva)#4.itm(0)} {slc(FRAME:acc#2.psp.sva)#4.itm(1)} {slc(FRAME:acc#2.psp.sva)#4.itm(2)} {slc(FRAME:acc#2.psp.sva)#4.itm(3)} {slc(FRAME:acc#2.psp.sva)#4.itm(4)} {slc(FRAME:acc#2.psp.sva)#4.itm(5)} {slc(FRAME:acc#2.psp.sva)#4.itm(6)} {slc(FRAME:acc#2.psp.sva)#4.itm(7)} {slc(FRAME:acc#2.psp.sva)#4.itm(8)} {slc(FRAME:acc#2.psp.sva)#4.itm(9)} -attr xrf 62864 -attr oid 54 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {conc#878.itm(0)} -attr vt d
+load net {conc#878.itm(1)} -attr vt d
+load net {conc#878.itm(2)} -attr vt d
+load net {conc#878.itm(3)} -attr vt d
+load net {conc#878.itm(4)} -attr vt d
+load net {conc#878.itm(5)} -attr vt d
+load net {conc#878.itm(6)} -attr vt d
+load net {conc#878.itm(7)} -attr vt d
+load net {conc#878.itm(8)} -attr vt d
+load net {conc#878.itm(9)} -attr vt d
+load netBundle {conc#878.itm} 10 {conc#878.itm(0)} {conc#878.itm(1)} {conc#878.itm(2)} {conc#878.itm(3)} {conc#878.itm(4)} {conc#878.itm(5)} {conc#878.itm(6)} {conc#878.itm(7)} {conc#878.itm(8)} {conc#878.itm(9)} -attr xrf 62865 -attr oid 55 -attr vt d -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {slc(FRAME:acc#2.psp.sva)#5.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#5.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#5.itm} 2 {slc(FRAME:acc#2.psp.sva)#5.itm(0)} {slc(FRAME:acc#2.psp.sva)#5.itm(1)} -attr xrf 62866 -attr oid 56 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#5.itm}
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(3)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#2.itm} 4 {slc(FRAME:acc#2.psp.sva)#2.itm(0)} {slc(FRAME:acc#2.psp.sva)#2.itm(1)} {slc(FRAME:acc#2.psp.sva)#2.itm(2)} {slc(FRAME:acc#2.psp.sva)#2.itm(3)} -attr xrf 62867 -attr oid 57 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#2.itm}
+load net {FRAME:or#3.itm(0)} -attr vt d
+load net {FRAME:or#3.itm(1)} -attr vt d
+load net {FRAME:or#3.itm(2)} -attr vt d
+load net {FRAME:or#3.itm(3)} -attr vt d
+load net {FRAME:or#3.itm(4)} -attr vt d
+load net {FRAME:or#3.itm(5)} -attr vt d
+load netBundle {FRAME:or#3.itm} 6 {FRAME:or#3.itm(0)} {FRAME:or#3.itm(1)} {FRAME:or#3.itm(2)} {FRAME:or#3.itm(3)} {FRAME:or#3.itm(4)} {FRAME:or#3.itm(5)} -attr xrf 62868 -attr oid 58 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(3)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(4)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(5)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#3.itm} 6 {slc(FRAME:acc#2.psp.sva)#3.itm(0)} {slc(FRAME:acc#2.psp.sva)#3.itm(1)} {slc(FRAME:acc#2.psp.sva)#3.itm(2)} {slc(FRAME:acc#2.psp.sva)#3.itm(3)} {slc(FRAME:acc#2.psp.sva)#3.itm(4)} {slc(FRAME:acc#2.psp.sva)#3.itm(5)} -attr xrf 62869 -attr oid 59 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {conc#879.itm(0)} -attr vt d
+load net {conc#879.itm(1)} -attr vt d
+load net {conc#879.itm(2)} -attr vt d
+load net {conc#879.itm(3)} -attr vt d
+load net {conc#879.itm(4)} -attr vt d
+load net {conc#879.itm(5)} -attr vt d
+load netBundle {conc#879.itm} 6 {conc#879.itm(0)} {conc#879.itm(1)} {conc#879.itm(2)} {conc#879.itm(3)} {conc#879.itm(4)} {conc#879.itm(5)} -attr xrf 62870 -attr oid 60 -attr vt d -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {slc(FRAME:acc#2.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#1.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#1.itm} 2 {slc(FRAME:acc#2.psp.sva)#1.itm(0)} {slc(FRAME:acc#2.psp.sva)#1.itm(1)} -attr xrf 62871 -attr oid 61 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#1.itm}
+load net {slc(FRAME:acc#2.psp.sva).itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(3)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(4)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(5)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(6)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(7)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(8)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(9)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva).itm} 10 {slc(FRAME:acc#2.psp.sva).itm(0)} {slc(FRAME:acc#2.psp.sva).itm(1)} {slc(FRAME:acc#2.psp.sva).itm(2)} {slc(FRAME:acc#2.psp.sva).itm(3)} {slc(FRAME:acc#2.psp.sva).itm(4)} {slc(FRAME:acc#2.psp.sva).itm(5)} {slc(FRAME:acc#2.psp.sva).itm(6)} {slc(FRAME:acc#2.psp.sva).itm(7)} {slc(FRAME:acc#2.psp.sva).itm(8)} {slc(FRAME:acc#2.psp.sva).itm(9)} -attr xrf 62872 -attr oid 62 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva).itm}
+load net {ACC1:acc#659.itm(0)} -attr vt d
+load net {ACC1:acc#659.itm(1)} -attr vt d
+load net {ACC1:acc#659.itm(2)} -attr vt d
+load net {ACC1:acc#659.itm(3)} -attr vt d
+load net {ACC1:acc#659.itm(4)} -attr vt d
+load net {ACC1:acc#659.itm(5)} -attr vt d
+load net {ACC1:acc#659.itm(6)} -attr vt d
+load net {ACC1:acc#659.itm(7)} -attr vt d
+load net {ACC1:acc#659.itm(8)} -attr vt d
+load net {ACC1:acc#659.itm(9)} -attr vt d
+load net {ACC1:acc#659.itm(10)} -attr vt d
+load net {ACC1:acc#659.itm(11)} -attr vt d
+load net {ACC1:acc#659.itm(12)} -attr vt d
+load netBundle {ACC1:acc#659.itm} 13 {ACC1:acc#659.itm(0)} {ACC1:acc#659.itm(1)} {ACC1:acc#659.itm(2)} {ACC1:acc#659.itm(3)} {ACC1:acc#659.itm(4)} {ACC1:acc#659.itm(5)} {ACC1:acc#659.itm(6)} {ACC1:acc#659.itm(7)} {ACC1:acc#659.itm(8)} {ACC1:acc#659.itm(9)} {ACC1:acc#659.itm(10)} {ACC1:acc#659.itm(11)} {ACC1:acc#659.itm(12)} -attr xrf 62873 -attr oid 63 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#654.itm(0)} -attr vt d
+load net {ACC1:acc#654.itm(1)} -attr vt d
+load net {ACC1:acc#654.itm(2)} -attr vt d
+load net {ACC1:acc#654.itm(3)} -attr vt d
+load net {ACC1:acc#654.itm(4)} -attr vt d
+load net {ACC1:acc#654.itm(5)} -attr vt d
+load net {ACC1:acc#654.itm(6)} -attr vt d
+load net {ACC1:acc#654.itm(7)} -attr vt d
+load net {ACC1:acc#654.itm(8)} -attr vt d
+load net {ACC1:acc#654.itm(9)} -attr vt d
+load net {ACC1:acc#654.itm(10)} -attr vt d
+load net {ACC1:acc#654.itm(11)} -attr vt d
+load netBundle {ACC1:acc#654.itm} 12 {ACC1:acc#654.itm(0)} {ACC1:acc#654.itm(1)} {ACC1:acc#654.itm(2)} {ACC1:acc#654.itm(3)} {ACC1:acc#654.itm(4)} {ACC1:acc#654.itm(5)} {ACC1:acc#654.itm(6)} {ACC1:acc#654.itm(7)} {ACC1:acc#654.itm(8)} {ACC1:acc#654.itm(9)} {ACC1:acc#654.itm(10)} {ACC1:acc#654.itm(11)} -attr xrf 62874 -attr oid 64 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {conc#880.itm(0)} -attr vt d
+load net {conc#880.itm(1)} -attr vt d
+load net {conc#880.itm(2)} -attr vt d
+load net {conc#880.itm(3)} -attr vt d
+load net {conc#880.itm(4)} -attr vt d
+load net {conc#880.itm(5)} -attr vt d
+load net {conc#880.itm(6)} -attr vt d
+load net {conc#880.itm(7)} -attr vt d
+load net {conc#880.itm(8)} -attr vt d
+load net {conc#880.itm(9)} -attr vt d
+load net {conc#880.itm(10)} -attr vt d
+load netBundle {conc#880.itm} 11 {conc#880.itm(0)} {conc#880.itm(1)} {conc#880.itm(2)} {conc#880.itm(3)} {conc#880.itm(4)} {conc#880.itm(5)} {conc#880.itm(6)} {conc#880.itm(7)} {conc#880.itm(8)} {conc#880.itm(9)} {conc#880.itm(10)} -attr xrf 62875 -attr oid 65 -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1:conc#1105.itm(0)} -attr vt d
+load net {ACC1:conc#1105.itm(1)} -attr vt d
+load net {ACC1:conc#1105.itm(2)} -attr vt d
+load net {ACC1:conc#1105.itm(3)} -attr vt d
+load net {ACC1:conc#1105.itm(4)} -attr vt d
+load net {ACC1:conc#1105.itm(5)} -attr vt d
+load net {ACC1:conc#1105.itm(6)} -attr vt d
+load net {ACC1:conc#1105.itm(7)} -attr vt d
+load net {ACC1:conc#1105.itm(8)} -attr vt d
+load net {ACC1:conc#1105.itm(9)} -attr vt d
+load net {ACC1:conc#1105.itm(10)} -attr vt d
+load netBundle {ACC1:conc#1105.itm} 11 {ACC1:conc#1105.itm(0)} {ACC1:conc#1105.itm(1)} {ACC1:conc#1105.itm(2)} {ACC1:conc#1105.itm(3)} {ACC1:conc#1105.itm(4)} {ACC1:conc#1105.itm(5)} {ACC1:conc#1105.itm(6)} {ACC1:conc#1105.itm(7)} {ACC1:conc#1105.itm(8)} {ACC1:conc#1105.itm(9)} {ACC1:conc#1105.itm(10)} -attr xrf 62876 -attr oid 66 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(0)} -attr vt d
+load net {ACC1:mul#58.itm(1)} -attr vt d
+load net {ACC1:mul#58.itm(2)} -attr vt d
+load net {ACC1:mul#58.itm(3)} -attr vt d
+load net {ACC1:mul#58.itm(4)} -attr vt d
+load net {ACC1:mul#58.itm(5)} -attr vt d
+load net {ACC1:mul#58.itm(6)} -attr vt d
+load net {ACC1:mul#58.itm(7)} -attr vt d
+load netBundle {ACC1:mul#58.itm} 8 {ACC1:mul#58.itm(0)} {ACC1:mul#58.itm(1)} {ACC1:mul#58.itm(2)} {ACC1:mul#58.itm(3)} {ACC1:mul#58.itm(4)} {ACC1:mul#58.itm(5)} {ACC1:mul#58.itm(6)} {ACC1:mul#58.itm(7)} -attr xrf 62877 -attr oid 67 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:acc#320.itm(0)} -attr vt d
+load net {ACC1:acc#320.itm(1)} -attr vt d
+load net {ACC1:acc#320.itm(2)} -attr vt d
+load net {ACC1:acc#320.itm(3)} -attr vt d
+load netBundle {ACC1:acc#320.itm} 4 {ACC1:acc#320.itm(0)} {ACC1:acc#320.itm(1)} {ACC1:acc#320.itm(2)} {ACC1:acc#320.itm(3)} -attr xrf 62878 -attr oid 68 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#321.itm(0)} -attr vt d
+load net {ACC1:acc#321.itm(1)} -attr vt d
+load net {ACC1:acc#321.itm(2)} -attr vt d
+load netBundle {ACC1:acc#321.itm} 3 {ACC1:acc#321.itm(0)} {ACC1:acc#321.itm(1)} {ACC1:acc#321.itm(2)} -attr xrf 62879 -attr oid 69 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#322.itm(0)} -attr vt d
+load net {ACC1:acc#322.itm(1)} -attr vt d
+load net {ACC1:acc#322.itm(2)} -attr vt d
+load netBundle {ACC1:acc#322.itm} 3 {ACC1:acc#322.itm(0)} {ACC1:acc#322.itm(1)} {ACC1:acc#322.itm(2)} -attr xrf 62880 -attr oid 70 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#323.itm(0)} -attr vt d
+load net {ACC1:acc#323.itm(1)} -attr vt d
+load net {ACC1:acc#323.itm(2)} -attr vt d
+load netBundle {ACC1:acc#323.itm} 3 {ACC1:acc#323.itm(0)} {ACC1:acc#323.itm(1)} {ACC1:acc#323.itm(2)} -attr xrf 62881 -attr oid 71 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#324.itm(0)} -attr vt d
+load net {ACC1:acc#324.itm(1)} -attr vt d
+load net {ACC1:acc#324.itm(2)} -attr vt d
+load netBundle {ACC1:acc#324.itm} 3 {ACC1:acc#324.itm(0)} {ACC1:acc#324.itm(1)} {ACC1:acc#324.itm(2)} -attr xrf 62882 -attr oid 72 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#325.itm(0)} -attr vt d
+load net {ACC1:acc#325.itm(1)} -attr vt d
+load netBundle {ACC1:acc#325.itm} 2 {ACC1:acc#325.itm(0)} {ACC1:acc#325.itm(1)} -attr xrf 62883 -attr oid 73 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#326.itm(0)} -attr vt d
+load net {ACC1:acc#326.itm(1)} -attr vt d
+load netBundle {ACC1:acc#326.itm} 2 {ACC1:acc#326.itm(0)} {ACC1:acc#326.itm(1)} -attr xrf 62884 -attr oid 74 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1-3:exs#1051.itm(0)} -attr vt d
+load net {ACC1-3:exs#1051.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1051.itm} 2 {ACC1-3:exs#1051.itm(0)} {ACC1-3:exs#1051.itm(1)} -attr xrf 62885 -attr oid 75 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1051.itm}
+load net {ACC1:acc#653.itm(0)} -attr vt d
+load net {ACC1:acc#653.itm(1)} -attr vt d
+load net {ACC1:acc#653.itm(2)} -attr vt d
+load net {ACC1:acc#653.itm(3)} -attr vt d
+load net {ACC1:acc#653.itm(4)} -attr vt d
+load net {ACC1:acc#653.itm(5)} -attr vt d
+load net {ACC1:acc#653.itm(6)} -attr vt d
+load net {ACC1:acc#653.itm(7)} -attr vt d
+load net {ACC1:acc#653.itm(8)} -attr vt d
+load net {ACC1:acc#653.itm(9)} -attr vt d
+load net {ACC1:acc#653.itm(10)} -attr vt d
+load net {ACC1:acc#653.itm(11)} -attr vt d
+load netBundle {ACC1:acc#653.itm} 12 {ACC1:acc#653.itm(0)} {ACC1:acc#653.itm(1)} {ACC1:acc#653.itm(2)} {ACC1:acc#653.itm(3)} {ACC1:acc#653.itm(4)} {ACC1:acc#653.itm(5)} {ACC1:acc#653.itm(6)} {ACC1:acc#653.itm(7)} {ACC1:acc#653.itm(8)} {ACC1:acc#653.itm(9)} {ACC1:acc#653.itm(10)} {ACC1:acc#653.itm(11)} -attr xrf 62886 -attr oid 76 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1-1:acc#2.itm(0)} -attr vt d
+load net {ACC1-1:acc#2.itm(1)} -attr vt d
+load net {ACC1-1:acc#2.itm(2)} -attr vt d
+load net {ACC1-1:acc#2.itm(3)} -attr vt d
+load net {ACC1-1:acc#2.itm(4)} -attr vt d
+load net {ACC1-1:acc#2.itm(5)} -attr vt d
+load net {ACC1-1:acc#2.itm(6)} -attr vt d
+load net {ACC1-1:acc#2.itm(7)} -attr vt d
+load net {ACC1-1:acc#2.itm(8)} -attr vt d
+load net {ACC1-1:acc#2.itm(9)} -attr vt d
+load net {ACC1-1:acc#2.itm(10)} -attr vt d
+load netBundle {ACC1-1:acc#2.itm} 11 {ACC1-1:acc#2.itm(0)} {ACC1-1:acc#2.itm(1)} {ACC1-1:acc#2.itm(2)} {ACC1-1:acc#2.itm(3)} {ACC1-1:acc#2.itm(4)} {ACC1-1:acc#2.itm(5)} {ACC1-1:acc#2.itm(6)} {ACC1-1:acc#2.itm(7)} {ACC1-1:acc#2.itm(8)} {ACC1-1:acc#2.itm(9)} {ACC1-1:acc#2.itm(10)} -attr xrf 62887 -attr oid 77 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1:acc#690.itm(0)} -attr vt d
+load net {ACC1:acc#690.itm(1)} -attr vt d
+load net {ACC1:acc#690.itm(2)} -attr vt d
+load net {ACC1:acc#690.itm(3)} -attr vt d
+load net {ACC1:acc#690.itm(4)} -attr vt d
+load net {ACC1:acc#690.itm(5)} -attr vt d
+load net {ACC1:acc#690.itm(6)} -attr vt d
+load net {ACC1:acc#690.itm(7)} -attr vt d
+load net {ACC1:acc#690.itm(8)} -attr vt d
+load net {ACC1:acc#690.itm(9)} -attr vt d
+load net {ACC1:acc#690.itm(10)} -attr vt d
+load netBundle {ACC1:acc#690.itm} 11 {ACC1:acc#690.itm(0)} {ACC1:acc#690.itm(1)} {ACC1:acc#690.itm(2)} {ACC1:acc#690.itm(3)} {ACC1:acc#690.itm(4)} {ACC1:acc#690.itm(5)} {ACC1:acc#690.itm(6)} {ACC1:acc#690.itm(7)} {ACC1:acc#690.itm(8)} {ACC1:acc#690.itm(9)} {ACC1:acc#690.itm(10)} -attr xrf 62888 -attr oid 78 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#688.itm(0)} -attr vt d
+load net {ACC1:acc#688.itm(1)} -attr vt d
+load net {ACC1:acc#688.itm(2)} -attr vt d
+load net {ACC1:acc#688.itm(3)} -attr vt d
+load net {ACC1:acc#688.itm(4)} -attr vt d
+load net {ACC1:acc#688.itm(5)} -attr vt d
+load net {ACC1:acc#688.itm(6)} -attr vt d
+load net {ACC1:acc#688.itm(7)} -attr vt d
+load net {ACC1:acc#688.itm(8)} -attr vt d
+load net {ACC1:acc#688.itm(9)} -attr vt d
+load netBundle {ACC1:acc#688.itm} 10 {ACC1:acc#688.itm(0)} {ACC1:acc#688.itm(1)} {ACC1:acc#688.itm(2)} {ACC1:acc#688.itm(3)} {ACC1:acc#688.itm(4)} {ACC1:acc#688.itm(5)} {ACC1:acc#688.itm(6)} {ACC1:acc#688.itm(7)} {ACC1:acc#688.itm(8)} {ACC1:acc#688.itm(9)} -attr xrf 62889 -attr oid 79 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {conc#881.itm(0)} -attr vt d
+load net {conc#881.itm(1)} -attr vt d
+load net {conc#881.itm(2)} -attr vt d
+load net {conc#881.itm(3)} -attr vt d
+load net {conc#881.itm(4)} -attr vt d
+load net {conc#881.itm(5)} -attr vt d
+load net {conc#881.itm(6)} -attr vt d
+load net {conc#881.itm(7)} -attr vt d
+load net {conc#881.itm(8)} -attr vt d
+load netBundle {conc#881.itm} 9 {conc#881.itm(0)} {conc#881.itm(1)} {conc#881.itm(2)} {conc#881.itm(3)} {conc#881.itm(4)} {conc#881.itm(5)} {conc#881.itm(6)} {conc#881.itm(7)} {conc#881.itm(8)} -attr xrf 62890 -attr oid 80 -attr vt d -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {ACC1:acc#686.itm(0)} -attr vt d
+load net {ACC1:acc#686.itm(1)} -attr vt d
+load net {ACC1:acc#686.itm(2)} -attr vt d
+load net {ACC1:acc#686.itm(3)} -attr vt d
+load net {ACC1:acc#686.itm(4)} -attr vt d
+load net {ACC1:acc#686.itm(5)} -attr vt d
+load net {ACC1:acc#686.itm(6)} -attr vt d
+load net {ACC1:acc#686.itm(7)} -attr vt d
+load netBundle {ACC1:acc#686.itm} 8 {ACC1:acc#686.itm(0)} {ACC1:acc#686.itm(1)} {ACC1:acc#686.itm(2)} {ACC1:acc#686.itm(3)} {ACC1:acc#686.itm(4)} {ACC1:acc#686.itm(5)} {ACC1:acc#686.itm(6)} {ACC1:acc#686.itm(7)} -attr xrf 62891 -attr oid 81 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {conc#882.itm(0)} -attr vt d
+load net {conc#882.itm(1)} -attr vt d
+load net {conc#882.itm(2)} -attr vt d
+load net {conc#882.itm(3)} -attr vt d
+load net {conc#882.itm(4)} -attr vt d
+load net {conc#882.itm(5)} -attr vt d
+load net {conc#882.itm(6)} -attr vt d
+load net {conc#882.itm(7)} -attr vt d
+load netBundle {conc#882.itm} 8 {conc#882.itm(0)} {conc#882.itm(1)} {conc#882.itm(2)} {conc#882.itm(3)} {conc#882.itm(4)} {conc#882.itm(5)} {conc#882.itm(6)} {conc#882.itm(7)} -attr xrf 62892 -attr oid 82 -attr vt d -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {ACC1-1:exs#1055.itm(0)} -attr vt d
+load net {ACC1-1:exs#1055.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1055.itm} 2 {ACC1-1:exs#1055.itm(0)} {ACC1-1:exs#1055.itm(1)} -attr xrf 62893 -attr oid 83 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1055.itm}
+load net {ACC1:acc#683.itm(0)} -attr vt d
+load net {ACC1:acc#683.itm(1)} -attr vt d
+load net {ACC1:acc#683.itm(2)} -attr vt d
+load net {ACC1:acc#683.itm(3)} -attr vt d
+load net {ACC1:acc#683.itm(4)} -attr vt d
+load net {ACC1:acc#683.itm(5)} -attr vt d
+load net {ACC1:acc#683.itm(6)} -attr vt d
+load netBundle {ACC1:acc#683.itm} 7 {ACC1:acc#683.itm(0)} {ACC1:acc#683.itm(1)} {ACC1:acc#683.itm(2)} {ACC1:acc#683.itm(3)} {ACC1:acc#683.itm(4)} {ACC1:acc#683.itm(5)} {ACC1:acc#683.itm(6)} -attr xrf 62894 -attr oid 84 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {conc#883.itm(0)} -attr vt d
+load net {conc#883.itm(1)} -attr vt d
+load net {conc#883.itm(2)} -attr vt d
+load net {conc#883.itm(3)} -attr vt d
+load net {conc#883.itm(4)} -attr vt d
+load net {conc#883.itm(5)} -attr vt d
+load netBundle {conc#883.itm} 6 {conc#883.itm(0)} {conc#883.itm(1)} {conc#883.itm(2)} {conc#883.itm(3)} {conc#883.itm(4)} {conc#883.itm(5)} -attr xrf 62895 -attr oid 85 -attr vt d -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {ACC1-1:exs#1058.itm(0)} -attr vt d
+load net {ACC1-1:exs#1058.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1058.itm} 2 {ACC1-1:exs#1058.itm(0)} {ACC1-1:exs#1058.itm(1)} -attr xrf 62896 -attr oid 86 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1058.itm}
+load net {ACC1:acc#680.itm(0)} -attr vt d
+load net {ACC1:acc#680.itm(1)} -attr vt d
+load net {ACC1:acc#680.itm(2)} -attr vt d
+load net {ACC1:acc#680.itm(3)} -attr vt d
+load net {ACC1:acc#680.itm(4)} -attr vt d
+load netBundle {ACC1:acc#680.itm} 5 {ACC1:acc#680.itm(0)} {ACC1:acc#680.itm(1)} {ACC1:acc#680.itm(2)} {ACC1:acc#680.itm(3)} {ACC1:acc#680.itm(4)} -attr xrf 62897 -attr oid 87 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#676.itm(0)} -attr vt d
+load net {ACC1:acc#676.itm(1)} -attr vt d
+load net {ACC1:acc#676.itm(2)} -attr vt d
+load net {ACC1:acc#676.itm(3)} -attr vt d
+load netBundle {ACC1:acc#676.itm} 4 {ACC1:acc#676.itm(0)} {ACC1:acc#676.itm(1)} {ACC1:acc#676.itm(2)} {ACC1:acc#676.itm(3)} -attr xrf 62898 -attr oid 88 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:slc#153.itm(0)} -attr vt d
+load net {ACC1:slc#153.itm(1)} -attr vt d
+load net {ACC1:slc#153.itm(2)} -attr vt d
+load netBundle {ACC1:slc#153.itm} 3 {ACC1:slc#153.itm(0)} {ACC1:slc#153.itm(1)} {ACC1:slc#153.itm(2)} -attr xrf 62899 -attr oid 89 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#153.itm}
+load net {ACC1:acc#670.itm(0)} -attr vt d
+load net {ACC1:acc#670.itm(1)} -attr vt d
+load net {ACC1:acc#670.itm(2)} -attr vt d
+load net {ACC1:acc#670.itm(3)} -attr vt d
+load netBundle {ACC1:acc#670.itm} 4 {ACC1:acc#670.itm(0)} {ACC1:acc#670.itm(1)} {ACC1:acc#670.itm(2)} {ACC1:acc#670.itm(3)} -attr xrf 62900 -attr oid 90 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#670.itm}
+load net {exs.itm(0)} -attr vt d
+load net {exs.itm(1)} -attr vt d
+load net {exs.itm(2)} -attr vt d
+load netBundle {exs.itm} 3 {exs.itm(0)} {exs.itm(1)} {exs.itm(2)} -attr xrf 62901 -attr oid 91 -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {conc#884.itm(0)} -attr vt d
+load net {conc#884.itm(1)} -attr vt d
+load netBundle {conc#884.itm} 2 {conc#884.itm(0)} {conc#884.itm(1)} -attr xrf 62902 -attr oid 92 -attr vt d -attr @path {/sobel/sobel:core/conc#884.itm}
+load net {ACC1:exs#1474.itm(0)} -attr vt d
+load net {ACC1:exs#1474.itm(1)} -attr vt d
+load net {ACC1:exs#1474.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1474.itm} 3 {ACC1:exs#1474.itm(0)} {ACC1:exs#1474.itm(1)} {ACC1:exs#1474.itm(2)} -attr xrf 62903 -attr oid 93 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1474.itm}
+load net {ACC1:conc#1430.itm(0)} -attr vt d
+load net {ACC1:conc#1430.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1430.itm} 2 {ACC1:conc#1430.itm(0)} {ACC1:conc#1430.itm(1)} -attr xrf 62904 -attr oid 94 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1430.itm}
+load net {ACC1:slc#152.itm(0)} -attr vt d
+load net {ACC1:slc#152.itm(1)} -attr vt d
+load net {ACC1:slc#152.itm(2)} -attr vt d
+load netBundle {ACC1:slc#152.itm} 3 {ACC1:slc#152.itm(0)} {ACC1:slc#152.itm(1)} {ACC1:slc#152.itm(2)} -attr xrf 62905 -attr oid 95 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#152.itm}
+load net {ACC1:acc#669.itm(0)} -attr vt d
+load net {ACC1:acc#669.itm(1)} -attr vt d
+load net {ACC1:acc#669.itm(2)} -attr vt d
+load net {ACC1:acc#669.itm(3)} -attr vt d
+load netBundle {ACC1:acc#669.itm} 4 {ACC1:acc#669.itm(0)} {ACC1:acc#669.itm(1)} {ACC1:acc#669.itm(2)} {ACC1:acc#669.itm(3)} -attr xrf 62906 -attr oid 96 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#669.itm}
+load net {exs#46.itm(0)} -attr vt d
+load net {exs#46.itm(1)} -attr vt d
+load net {exs#46.itm(2)} -attr vt d
+load netBundle {exs#46.itm} 3 {exs#46.itm(0)} {exs#46.itm(1)} {exs#46.itm(2)} -attr xrf 62907 -attr oid 97 -attr vt d -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {conc#885.itm(0)} -attr vt d
+load net {conc#885.itm(1)} -attr vt d
+load netBundle {conc#885.itm} 2 {conc#885.itm(0)} {conc#885.itm(1)} -attr xrf 62908 -attr oid 98 -attr vt d -attr @path {/sobel/sobel:core/conc#885.itm}
+load net {ACC1:exs#1476.itm(0)} -attr vt d
+load net {ACC1:exs#1476.itm(1)} -attr vt d
+load net {ACC1:exs#1476.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1476.itm} 3 {ACC1:exs#1476.itm(0)} {ACC1:exs#1476.itm(1)} {ACC1:exs#1476.itm(2)} -attr xrf 62909 -attr oid 99 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1476.itm}
+load net {ACC1:conc#1428.itm(0)} -attr vt d
+load net {ACC1:conc#1428.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1428.itm} 2 {ACC1:conc#1428.itm(0)} {ACC1:conc#1428.itm(1)} -attr xrf 62910 -attr oid 100 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1428.itm}
+load net {ACC1:acc#675.itm(0)} -attr vt d
+load net {ACC1:acc#675.itm(1)} -attr vt d
+load net {ACC1:acc#675.itm(2)} -attr vt d
+load net {ACC1:acc#675.itm(3)} -attr vt d
+load netBundle {ACC1:acc#675.itm} 4 {ACC1:acc#675.itm(0)} {ACC1:acc#675.itm(1)} {ACC1:acc#675.itm(2)} {ACC1:acc#675.itm(3)} -attr xrf 62911 -attr oid 101 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:slc#151.itm(0)} -attr vt d
+load net {ACC1:slc#151.itm(1)} -attr vt d
+load net {ACC1:slc#151.itm(2)} -attr vt d
+load netBundle {ACC1:slc#151.itm} 3 {ACC1:slc#151.itm(0)} {ACC1:slc#151.itm(1)} {ACC1:slc#151.itm(2)} -attr xrf 62912 -attr oid 102 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#151.itm}
+load net {ACC1:acc#668.itm(0)} -attr vt d
+load net {ACC1:acc#668.itm(1)} -attr vt d
+load net {ACC1:acc#668.itm(2)} -attr vt d
+load net {ACC1:acc#668.itm(3)} -attr vt d
+load netBundle {ACC1:acc#668.itm} 4 {ACC1:acc#668.itm(0)} {ACC1:acc#668.itm(1)} {ACC1:acc#668.itm(2)} {ACC1:acc#668.itm(3)} -attr xrf 62913 -attr oid 103 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#668.itm}
+load net {exs#47.itm(0)} -attr vt d
+load net {exs#47.itm(1)} -attr vt d
+load net {exs#47.itm(2)} -attr vt d
+load netBundle {exs#47.itm} 3 {exs#47.itm(0)} {exs#47.itm(1)} {exs#47.itm(2)} -attr xrf 62914 -attr oid 104 -attr vt d -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {conc#886.itm(0)} -attr vt d
+load net {conc#886.itm(1)} -attr vt d
+load netBundle {conc#886.itm} 2 {conc#886.itm(0)} {conc#886.itm(1)} -attr xrf 62915 -attr oid 105 -attr vt d -attr @path {/sobel/sobel:core/conc#886.itm}
+load net {ACC1:exs#1478.itm(0)} -attr vt d
+load net {ACC1:exs#1478.itm(1)} -attr vt d
+load net {ACC1:exs#1478.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1478.itm} 3 {ACC1:exs#1478.itm(0)} {ACC1:exs#1478.itm(1)} {ACC1:exs#1478.itm(2)} -attr xrf 62916 -attr oid 106 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1478.itm}
+load net {ACC1:conc#1426.itm(0)} -attr vt d
+load net {ACC1:conc#1426.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1426.itm} 2 {ACC1:conc#1426.itm(0)} {ACC1:conc#1426.itm(1)} -attr xrf 62917 -attr oid 107 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1426.itm}
+load net {ACC1:slc#150.itm(0)} -attr vt d
+load net {ACC1:slc#150.itm(1)} -attr vt d
+load net {ACC1:slc#150.itm(2)} -attr vt d
+load netBundle {ACC1:slc#150.itm} 3 {ACC1:slc#150.itm(0)} {ACC1:slc#150.itm(1)} {ACC1:slc#150.itm(2)} -attr xrf 62918 -attr oid 108 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#150.itm}
+load net {ACC1:acc#667.itm(0)} -attr vt d
+load net {ACC1:acc#667.itm(1)} -attr vt d
+load net {ACC1:acc#667.itm(2)} -attr vt d
+load net {ACC1:acc#667.itm(3)} -attr vt d
+load netBundle {ACC1:acc#667.itm} 4 {ACC1:acc#667.itm(0)} {ACC1:acc#667.itm(1)} {ACC1:acc#667.itm(2)} {ACC1:acc#667.itm(3)} -attr xrf 62919 -attr oid 109 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#667.itm}
+load net {exs#48.itm(0)} -attr vt d
+load net {exs#48.itm(1)} -attr vt d
+load net {exs#48.itm(2)} -attr vt d
+load netBundle {exs#48.itm} 3 {exs#48.itm(0)} {exs#48.itm(1)} {exs#48.itm(2)} -attr xrf 62920 -attr oid 110 -attr vt d -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {conc#887.itm(0)} -attr vt d
+load net {conc#887.itm(1)} -attr vt d
+load netBundle {conc#887.itm} 2 {conc#887.itm(0)} {conc#887.itm(1)} -attr xrf 62921 -attr oid 111 -attr vt d -attr @path {/sobel/sobel:core/conc#887.itm}
+load net {ACC1:exs#1480.itm(0)} -attr vt d
+load net {ACC1:exs#1480.itm(1)} -attr vt d
+load net {ACC1:exs#1480.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1480.itm} 3 {ACC1:exs#1480.itm(0)} {ACC1:exs#1480.itm(1)} {ACC1:exs#1480.itm(2)} -attr xrf 62922 -attr oid 112 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1480.itm}
+load net {ACC1:conc#1424.itm(0)} -attr vt d
+load net {ACC1:conc#1424.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1424.itm} 2 {ACC1:conc#1424.itm(0)} {ACC1:conc#1424.itm(1)} -attr xrf 62923 -attr oid 113 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1424.itm}
+load net {ACC1:acc#687.itm(0)} -attr vt d
+load net {ACC1:acc#687.itm(1)} -attr vt d
+load net {ACC1:acc#687.itm(2)} -attr vt d
+load net {ACC1:acc#687.itm(3)} -attr vt d
+load net {ACC1:acc#687.itm(4)} -attr vt d
+load net {ACC1:acc#687.itm(5)} -attr vt d
+load net {ACC1:acc#687.itm(6)} -attr vt d
+load net {ACC1:acc#687.itm(7)} -attr vt d
+load net {ACC1:acc#687.itm(8)} -attr vt d
+load net {ACC1:acc#687.itm(9)} -attr vt d
+load netBundle {ACC1:acc#687.itm} 10 {ACC1:acc#687.itm(0)} {ACC1:acc#687.itm(1)} {ACC1:acc#687.itm(2)} {ACC1:acc#687.itm(3)} {ACC1:acc#687.itm(4)} {ACC1:acc#687.itm(5)} {ACC1:acc#687.itm(6)} {ACC1:acc#687.itm(7)} {ACC1:acc#687.itm(8)} {ACC1:acc#687.itm(9)} -attr xrf 62924 -attr oid 114 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#685.itm(0)} -attr vt d
+load net {ACC1:acc#685.itm(1)} -attr vt d
+load net {ACC1:acc#685.itm(2)} -attr vt d
+load net {ACC1:acc#685.itm(3)} -attr vt d
+load net {ACC1:acc#685.itm(4)} -attr vt d
+load net {ACC1:acc#685.itm(5)} -attr vt d
+load net {ACC1:acc#685.itm(6)} -attr vt d
+load net {ACC1:acc#685.itm(7)} -attr vt d
+load netBundle {ACC1:acc#685.itm} 8 {ACC1:acc#685.itm(0)} {ACC1:acc#685.itm(1)} {ACC1:acc#685.itm(2)} {ACC1:acc#685.itm(3)} {ACC1:acc#685.itm(4)} {ACC1:acc#685.itm(5)} {ACC1:acc#685.itm(6)} {ACC1:acc#685.itm(7)} -attr xrf 62925 -attr oid 115 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#682.itm(0)} -attr vt d
+load net {ACC1:acc#682.itm(1)} -attr vt d
+load net {ACC1:acc#682.itm(2)} -attr vt d
+load net {ACC1:acc#682.itm(3)} -attr vt d
+load net {ACC1:acc#682.itm(4)} -attr vt d
+load net {ACC1:acc#682.itm(5)} -attr vt d
+load netBundle {ACC1:acc#682.itm} 6 {ACC1:acc#682.itm(0)} {ACC1:acc#682.itm(1)} {ACC1:acc#682.itm(2)} {ACC1:acc#682.itm(3)} {ACC1:acc#682.itm(4)} {ACC1:acc#682.itm(5)} -attr xrf 62926 -attr oid 116 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#679.itm(0)} -attr vt d
+load net {ACC1:acc#679.itm(1)} -attr vt d
+load net {ACC1:acc#679.itm(2)} -attr vt d
+load net {ACC1:acc#679.itm(3)} -attr vt d
+load netBundle {ACC1:acc#679.itm} 4 {ACC1:acc#679.itm(0)} {ACC1:acc#679.itm(1)} {ACC1:acc#679.itm(2)} {ACC1:acc#679.itm(3)} -attr xrf 62927 -attr oid 117 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#674.itm(0)} -attr vt d
+load net {ACC1:acc#674.itm(1)} -attr vt d
+load net {ACC1:acc#674.itm(2)} -attr vt d
+load netBundle {ACC1:acc#674.itm} 3 {ACC1:acc#674.itm(0)} {ACC1:acc#674.itm(1)} {ACC1:acc#674.itm(2)} -attr xrf 62928 -attr oid 118 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load net {ACC1:slc#148.itm(0)} -attr vt d
+load net {ACC1:slc#148.itm(1)} -attr vt d
+load net {ACC1:slc#148.itm(2)} -attr vt d
+load netBundle {ACC1:slc#148.itm} 3 {ACC1:slc#148.itm(0)} {ACC1:slc#148.itm(1)} {ACC1:slc#148.itm(2)} -attr xrf 62929 -attr oid 119 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#148.itm}
+load net {ACC1:acc#665.itm(0)} -attr vt d
+load net {ACC1:acc#665.itm(1)} -attr vt d
+load net {ACC1:acc#665.itm(2)} -attr vt d
+load net {ACC1:acc#665.itm(3)} -attr vt d
+load netBundle {ACC1:acc#665.itm} 4 {ACC1:acc#665.itm(0)} {ACC1:acc#665.itm(1)} {ACC1:acc#665.itm(2)} {ACC1:acc#665.itm(3)} -attr xrf 62930 -attr oid 120 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#665.itm}
+load net {conc#888.itm(0)} -attr vt d
+load net {conc#888.itm(1)} -attr vt d
+load net {conc#888.itm(2)} -attr vt d
+load netBundle {conc#888.itm} 3 {conc#888.itm(0)} {conc#888.itm(1)} {conc#888.itm(2)} -attr xrf 62931 -attr oid 121 -attr vt d -attr @path {/sobel/sobel:core/conc#888.itm}
+load net {ACC1:conc#1420.itm(0)} -attr vt d
+load net {ACC1:conc#1420.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1420.itm} 2 {ACC1:conc#1420.itm(0)} {ACC1:conc#1420.itm(1)} -attr xrf 62932 -attr oid 122 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1420.itm}
+load net {slc(ACC1:acc#220.psp#1.sva)#3.itm(0)} -attr vt d
+load net {slc(ACC1:acc#220.psp#1.sva)#3.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#220.psp#1.sva)#3.itm} 2 {slc(ACC1:acc#220.psp#1.sva)#3.itm(0)} {slc(ACC1:acc#220.psp#1.sva)#3.itm(1)} -attr xrf 62933 -attr oid 123 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva)#3.itm}
+load net {ACC1:slc#149.itm(0)} -attr vt d
+load net {ACC1:slc#149.itm(1)} -attr vt d
+load net {ACC1:slc#149.itm(2)} -attr vt d
+load net {ACC1:slc#149.itm(3)} -attr vt d
+load netBundle {ACC1:slc#149.itm} 4 {ACC1:slc#149.itm(0)} {ACC1:slc#149.itm(1)} {ACC1:slc#149.itm(2)} {ACC1:slc#149.itm(3)} -attr xrf 62934 -attr oid 124 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#149.itm}
+load net {ACC1:acc#666.itm(0)} -attr vt d
+load net {ACC1:acc#666.itm(1)} -attr vt d
+load net {ACC1:acc#666.itm(2)} -attr vt d
+load net {ACC1:acc#666.itm(3)} -attr vt d
+load net {ACC1:acc#666.itm(4)} -attr vt d
+load netBundle {ACC1:acc#666.itm} 5 {ACC1:acc#666.itm(0)} {ACC1:acc#666.itm(1)} {ACC1:acc#666.itm(2)} {ACC1:acc#666.itm(3)} {ACC1:acc#666.itm(4)} -attr xrf 62935 -attr oid 125 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666.itm}
+load net {conc#889.itm(0)} -attr vt d
+load net {conc#889.itm(1)} -attr vt d
+load net {conc#889.itm(2)} -attr vt d
+load netBundle {conc#889.itm} 3 {conc#889.itm(0)} {conc#889.itm(1)} {conc#889.itm(2)} -attr xrf 62936 -attr oid 126 -attr vt d -attr @path {/sobel/sobel:core/conc#889.itm}
+load net {ACC1:conc#1422.itm(0)} -attr vt d
+load net {ACC1:conc#1422.itm(1)} -attr vt d
+load net {ACC1:conc#1422.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1422.itm} 3 {ACC1:conc#1422.itm(0)} {ACC1:conc#1422.itm(1)} {ACC1:conc#1422.itm(2)} -attr xrf 62937 -attr oid 127 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1422.itm}
+load net {ACC1:acc#678.itm(0)} -attr vt d
+load net {ACC1:acc#678.itm(1)} -attr vt d
+load net {ACC1:acc#678.itm(2)} -attr vt d
+load net {ACC1:acc#678.itm(3)} -attr vt d
+load net {ACC1:acc#678.itm(4)} -attr vt d
+load netBundle {ACC1:acc#678.itm} 5 {ACC1:acc#678.itm(0)} {ACC1:acc#678.itm(1)} {ACC1:acc#678.itm(2)} {ACC1:acc#678.itm(3)} {ACC1:acc#678.itm(4)} -attr xrf 62938 -attr oid 128 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1-1:conc#558.itm(0)} -attr vt d
+load net {ACC1-1:conc#558.itm(1)} -attr vt d
+load net {ACC1-1:conc#558.itm(2)} -attr vt d
+load net {ACC1-1:conc#558.itm(3)} -attr vt d
+load netBundle {ACC1-1:conc#558.itm} 4 {ACC1-1:conc#558.itm(0)} {ACC1-1:conc#558.itm(1)} {ACC1-1:conc#558.itm(2)} {ACC1-1:conc#558.itm(3)} -attr xrf 62939 -attr oid 129 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#558.itm}
+load net {ACC1-1:exs#1043.itm(0)} -attr vt d
+load net {ACC1-1:exs#1043.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1043.itm} 2 {ACC1-1:exs#1043.itm(0)} {ACC1-1:exs#1043.itm(1)} -attr xrf 62940 -attr oid 130 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1043.itm}
+load net {conc#890.itm(0)} -attr vt d
+load net {conc#890.itm(1)} -attr vt d
+load net {conc#890.itm(2)} -attr vt d
+load net {conc#890.itm(3)} -attr vt d
+load net {conc#890.itm(4)} -attr vt d
+load net {conc#890.itm(5)} -attr vt d
+load net {conc#890.itm(6)} -attr vt d
+load netBundle {conc#890.itm} 7 {conc#890.itm(0)} {conc#890.itm(1)} {conc#890.itm(2)} {conc#890.itm(3)} {conc#890.itm(4)} {conc#890.itm(5)} {conc#890.itm(6)} -attr xrf 62941 -attr oid 131 -attr vt d -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {ACC1:acc#684.itm(0)} -attr vt d
+load net {ACC1:acc#684.itm(1)} -attr vt d
+load net {ACC1:acc#684.itm(2)} -attr vt d
+load net {ACC1:acc#684.itm(3)} -attr vt d
+load net {ACC1:acc#684.itm(4)} -attr vt d
+load net {ACC1:acc#684.itm(5)} -attr vt d
+load net {ACC1:acc#684.itm(6)} -attr vt d
+load net {ACC1:acc#684.itm(7)} -attr vt d
+load netBundle {ACC1:acc#684.itm} 8 {ACC1:acc#684.itm(0)} {ACC1:acc#684.itm(1)} {ACC1:acc#684.itm(2)} {ACC1:acc#684.itm(3)} {ACC1:acc#684.itm(4)} {ACC1:acc#684.itm(5)} {ACC1:acc#684.itm(6)} {ACC1:acc#684.itm(7)} -attr xrf 62942 -attr oid 132 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1-1:exs#1045.itm(0)} -attr vt d
+load net {ACC1-1:exs#1045.itm(1)} -attr vt d
+load net {ACC1-1:exs#1045.itm(2)} -attr vt d
+load net {ACC1-1:exs#1045.itm(3)} -attr vt d
+load net {ACC1-1:exs#1045.itm(4)} -attr vt d
+load net {ACC1-1:exs#1045.itm(5)} -attr vt d
+load net {ACC1-1:exs#1045.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#1045.itm} 7 {ACC1-1:exs#1045.itm(0)} {ACC1-1:exs#1045.itm(1)} {ACC1-1:exs#1045.itm(2)} {ACC1-1:exs#1045.itm(3)} {ACC1-1:exs#1045.itm(4)} {ACC1-1:exs#1045.itm(5)} {ACC1-1:exs#1045.itm(6)} -attr xrf 62943 -attr oid 133 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {ACC1-1:conc#600.itm(0)} -attr vt d
+load net {ACC1-1:conc#600.itm(1)} -attr vt d
+load net {ACC1-1:conc#600.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#600.itm} 3 {ACC1-1:conc#600.itm(0)} {ACC1-1:conc#600.itm(1)} {ACC1-1:conc#600.itm(2)} -attr xrf 62944 -attr oid 134 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#600.itm}
+load net {ACC1-1:exs#1049.itm(0)} -attr vt d
+load net {ACC1-1:exs#1049.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1049.itm} 2 {ACC1-1:exs#1049.itm(0)} {ACC1-1:exs#1049.itm(1)} -attr xrf 62945 -attr oid 135 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1049.itm}
+load net {ACC1:acc#681.itm(0)} -attr vt d
+load net {ACC1:acc#681.itm(1)} -attr vt d
+load net {ACC1:acc#681.itm(2)} -attr vt d
+load net {ACC1:acc#681.itm(3)} -attr vt d
+load net {ACC1:acc#681.itm(4)} -attr vt d
+load net {ACC1:acc#681.itm(5)} -attr vt d
+load netBundle {ACC1:acc#681.itm} 6 {ACC1:acc#681.itm(0)} {ACC1:acc#681.itm(1)} {ACC1:acc#681.itm(2)} {ACC1:acc#681.itm(3)} {ACC1:acc#681.itm(4)} {ACC1:acc#681.itm(5)} -attr xrf 62946 -attr oid 136 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {conc#891.itm(0)} -attr vt d
+load net {conc#891.itm(1)} -attr vt d
+load net {conc#891.itm(2)} -attr vt d
+load net {conc#891.itm(3)} -attr vt d
+load net {conc#891.itm(4)} -attr vt d
+load netBundle {conc#891.itm} 5 {conc#891.itm(0)} {conc#891.itm(1)} {conc#891.itm(2)} {conc#891.itm(3)} {conc#891.itm(4)} -attr xrf 62947 -attr oid 137 -attr vt d -attr @path {/sobel/sobel:core/conc#891.itm}
+load net {ACC1:acc#677.itm(0)} -attr vt d
+load net {ACC1:acc#677.itm(1)} -attr vt d
+load net {ACC1:acc#677.itm(2)} -attr vt d
+load net {ACC1:acc#677.itm(3)} -attr vt d
+load netBundle {ACC1:acc#677.itm} 4 {ACC1:acc#677.itm(0)} {ACC1:acc#677.itm(1)} {ACC1:acc#677.itm(2)} {ACC1:acc#677.itm(3)} -attr xrf 62948 -attr oid 138 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:slc#154.itm(0)} -attr vt d
+load net {ACC1:slc#154.itm(1)} -attr vt d
+load net {ACC1:slc#154.itm(2)} -attr vt d
+load netBundle {ACC1:slc#154.itm} 3 {ACC1:slc#154.itm(0)} {ACC1:slc#154.itm(1)} {ACC1:slc#154.itm(2)} -attr xrf 62949 -attr oid 139 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#154.itm}
+load net {ACC1:acc#671.itm(0)} -attr vt d
+load net {ACC1:acc#671.itm(1)} -attr vt d
+load net {ACC1:acc#671.itm(2)} -attr vt d
+load net {ACC1:acc#671.itm(3)} -attr vt d
+load netBundle {ACC1:acc#671.itm} 4 {ACC1:acc#671.itm(0)} {ACC1:acc#671.itm(1)} {ACC1:acc#671.itm(2)} {ACC1:acc#671.itm(3)} -attr xrf 62950 -attr oid 140 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#671.itm}
+load net {exs#49.itm(0)} -attr vt d
+load net {exs#49.itm(1)} -attr vt d
+load net {exs#49.itm(2)} -attr vt d
+load netBundle {exs#49.itm} 3 {exs#49.itm(0)} {exs#49.itm(1)} {exs#49.itm(2)} -attr xrf 62951 -attr oid 141 -attr vt d -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {conc#892.itm(0)} -attr vt d
+load net {conc#892.itm(1)} -attr vt d
+load netBundle {conc#892.itm} 2 {conc#892.itm(0)} {conc#892.itm(1)} -attr xrf 62952 -attr oid 142 -attr vt d -attr @path {/sobel/sobel:core/conc#892.itm}
+load net {ACC1:exs#1482.itm(0)} -attr vt d
+load net {ACC1:exs#1482.itm(1)} -attr vt d
+load net {ACC1:exs#1482.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1482.itm} 3 {ACC1:exs#1482.itm(0)} {ACC1:exs#1482.itm(1)} {ACC1:exs#1482.itm(2)} -attr xrf 62953 -attr oid 143 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1482.itm}
+load net {ACC1:conc#1432.itm(0)} -attr vt d
+load net {ACC1:conc#1432.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1432.itm} 2 {ACC1:conc#1432.itm(0)} {ACC1:conc#1432.itm(1)} -attr xrf 62954 -attr oid 144 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1432.itm}
+load net {conc#893.itm(0)} -attr vt d
+load net {conc#893.itm(1)} -attr vt d
+load net {conc#893.itm(2)} -attr vt d
+load net {conc#893.itm(3)} -attr vt d
+load net {conc#893.itm(4)} -attr vt d
+load net {conc#893.itm(5)} -attr vt d
+load net {conc#893.itm(6)} -attr vt d
+load net {conc#893.itm(7)} -attr vt d
+load net {conc#893.itm(8)} -attr vt d
+load net {conc#893.itm(9)} -attr vt d
+load net {conc#893.itm(10)} -attr vt d
+load netBundle {conc#893.itm} 11 {conc#893.itm(0)} {conc#893.itm(1)} {conc#893.itm(2)} {conc#893.itm(3)} {conc#893.itm(4)} {conc#893.itm(5)} {conc#893.itm(6)} {conc#893.itm(7)} {conc#893.itm(8)} {conc#893.itm(9)} {conc#893.itm(10)} -attr xrf 62955 -attr oid 145 -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {ACC1:acc#718.itm(0)} -attr vt d
+load net {ACC1:acc#718.itm(1)} -attr vt d
+load net {ACC1:acc#718.itm(2)} -attr vt d
+load netBundle {ACC1:acc#718.itm} 3 {ACC1:acc#718.itm(0)} {ACC1:acc#718.itm(1)} {ACC1:acc#718.itm(2)} -attr xrf 62956 -attr oid 146 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#718.itm}
+load net {ACC1:exs#1640.itm(0)} -attr vt d
+load net {ACC1:exs#1640.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1640.itm} 2 {ACC1:exs#1640.itm(0)} {ACC1:exs#1640.itm(1)} -attr xrf 62957 -attr oid 147 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1640.itm}
+load net {ACC1-1:acc#27.itm(0)} -attr vt d
+load net {ACC1-1:acc#27.itm(1)} -attr vt d
+load net {ACC1-1:acc#27.itm(2)} -attr vt d
+load net {ACC1-1:acc#27.itm(3)} -attr vt d
+load net {ACC1-1:acc#27.itm(4)} -attr vt d
+load net {ACC1-1:acc#27.itm(5)} -attr vt d
+load net {ACC1-1:acc#27.itm(6)} -attr vt d
+load net {ACC1-1:acc#27.itm(7)} -attr vt d
+load net {ACC1-1:acc#27.itm(8)} -attr vt d
+load net {ACC1-1:acc#27.itm(9)} -attr vt d
+load net {ACC1-1:acc#27.itm(10)} -attr vt d
+load netBundle {ACC1-1:acc#27.itm} 11 {ACC1-1:acc#27.itm(0)} {ACC1-1:acc#27.itm(1)} {ACC1-1:acc#27.itm(2)} {ACC1-1:acc#27.itm(3)} {ACC1-1:acc#27.itm(4)} {ACC1-1:acc#27.itm(5)} {ACC1-1:acc#27.itm(6)} {ACC1-1:acc#27.itm(7)} {ACC1-1:acc#27.itm(8)} {ACC1-1:acc#27.itm(9)} {ACC1-1:acc#27.itm(10)} -attr xrf 62958 -attr oid 148 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1:acc#716.itm(0)} -attr vt d
+load net {ACC1:acc#716.itm(1)} -attr vt d
+load net {ACC1:acc#716.itm(2)} -attr vt d
+load net {ACC1:acc#716.itm(3)} -attr vt d
+load net {ACC1:acc#716.itm(4)} -attr vt d
+load net {ACC1:acc#716.itm(5)} -attr vt d
+load net {ACC1:acc#716.itm(6)} -attr vt d
+load net {ACC1:acc#716.itm(7)} -attr vt d
+load net {ACC1:acc#716.itm(8)} -attr vt d
+load net {ACC1:acc#716.itm(9)} -attr vt d
+load net {ACC1:acc#716.itm(10)} -attr vt d
+load netBundle {ACC1:acc#716.itm} 11 {ACC1:acc#716.itm(0)} {ACC1:acc#716.itm(1)} {ACC1:acc#716.itm(2)} {ACC1:acc#716.itm(3)} {ACC1:acc#716.itm(4)} {ACC1:acc#716.itm(5)} {ACC1:acc#716.itm(6)} {ACC1:acc#716.itm(7)} {ACC1:acc#716.itm(8)} {ACC1:acc#716.itm(9)} {ACC1:acc#716.itm(10)} -attr xrf 62959 -attr oid 149 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#714.itm(0)} -attr vt d
+load net {ACC1:acc#714.itm(1)} -attr vt d
+load net {ACC1:acc#714.itm(2)} -attr vt d
+load net {ACC1:acc#714.itm(3)} -attr vt d
+load net {ACC1:acc#714.itm(4)} -attr vt d
+load net {ACC1:acc#714.itm(5)} -attr vt d
+load net {ACC1:acc#714.itm(6)} -attr vt d
+load net {ACC1:acc#714.itm(7)} -attr vt d
+load net {ACC1:acc#714.itm(8)} -attr vt d
+load net {ACC1:acc#714.itm(9)} -attr vt d
+load netBundle {ACC1:acc#714.itm} 10 {ACC1:acc#714.itm(0)} {ACC1:acc#714.itm(1)} {ACC1:acc#714.itm(2)} {ACC1:acc#714.itm(3)} {ACC1:acc#714.itm(4)} {ACC1:acc#714.itm(5)} {ACC1:acc#714.itm(6)} {ACC1:acc#714.itm(7)} {ACC1:acc#714.itm(8)} {ACC1:acc#714.itm(9)} -attr xrf 62960 -attr oid 150 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {conc#894.itm(0)} -attr vt d
+load net {conc#894.itm(1)} -attr vt d
+load net {conc#894.itm(2)} -attr vt d
+load net {conc#894.itm(3)} -attr vt d
+load net {conc#894.itm(4)} -attr vt d
+load net {conc#894.itm(5)} -attr vt d
+load net {conc#894.itm(6)} -attr vt d
+load net {conc#894.itm(7)} -attr vt d
+load net {conc#894.itm(8)} -attr vt d
+load netBundle {conc#894.itm} 9 {conc#894.itm(0)} {conc#894.itm(1)} {conc#894.itm(2)} {conc#894.itm(3)} {conc#894.itm(4)} {conc#894.itm(5)} {conc#894.itm(6)} {conc#894.itm(7)} {conc#894.itm(8)} -attr xrf 62961 -attr oid 151 -attr vt d -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {ACC1:acc#712.itm(0)} -attr vt d
+load net {ACC1:acc#712.itm(1)} -attr vt d
+load net {ACC1:acc#712.itm(2)} -attr vt d
+load net {ACC1:acc#712.itm(3)} -attr vt d
+load net {ACC1:acc#712.itm(4)} -attr vt d
+load net {ACC1:acc#712.itm(5)} -attr vt d
+load net {ACC1:acc#712.itm(6)} -attr vt d
+load net {ACC1:acc#712.itm(7)} -attr vt d
+load netBundle {ACC1:acc#712.itm} 8 {ACC1:acc#712.itm(0)} {ACC1:acc#712.itm(1)} {ACC1:acc#712.itm(2)} {ACC1:acc#712.itm(3)} {ACC1:acc#712.itm(4)} {ACC1:acc#712.itm(5)} {ACC1:acc#712.itm(6)} {ACC1:acc#712.itm(7)} -attr xrf 62962 -attr oid 152 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {conc#895.itm(0)} -attr vt d
+load net {conc#895.itm(1)} -attr vt d
+load net {conc#895.itm(2)} -attr vt d
+load net {conc#895.itm(3)} -attr vt d
+load net {conc#895.itm(4)} -attr vt d
+load net {conc#895.itm(5)} -attr vt d
+load net {conc#895.itm(6)} -attr vt d
+load net {conc#895.itm(7)} -attr vt d
+load netBundle {conc#895.itm} 8 {conc#895.itm(0)} {conc#895.itm(1)} {conc#895.itm(2)} {conc#895.itm(3)} {conc#895.itm(4)} {conc#895.itm(5)} {conc#895.itm(6)} {conc#895.itm(7)} -attr xrf 62963 -attr oid 153 -attr vt d -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {ACC1-1:exs#1060.itm(0)} -attr vt d
+load net {ACC1-1:exs#1060.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1060.itm} 2 {ACC1-1:exs#1060.itm(0)} {ACC1-1:exs#1060.itm(1)} -attr xrf 62964 -attr oid 154 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1060.itm}
+load net {ACC1:acc#709.itm(0)} -attr vt d
+load net {ACC1:acc#709.itm(1)} -attr vt d
+load net {ACC1:acc#709.itm(2)} -attr vt d
+load net {ACC1:acc#709.itm(3)} -attr vt d
+load net {ACC1:acc#709.itm(4)} -attr vt d
+load net {ACC1:acc#709.itm(5)} -attr vt d
+load net {ACC1:acc#709.itm(6)} -attr vt d
+load netBundle {ACC1:acc#709.itm} 7 {ACC1:acc#709.itm(0)} {ACC1:acc#709.itm(1)} {ACC1:acc#709.itm(2)} {ACC1:acc#709.itm(3)} {ACC1:acc#709.itm(4)} {ACC1:acc#709.itm(5)} {ACC1:acc#709.itm(6)} -attr xrf 62965 -attr oid 155 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {conc#896.itm(0)} -attr vt d
+load net {conc#896.itm(1)} -attr vt d
+load net {conc#896.itm(2)} -attr vt d
+load net {conc#896.itm(3)} -attr vt d
+load net {conc#896.itm(4)} -attr vt d
+load net {conc#896.itm(5)} -attr vt d
+load netBundle {conc#896.itm} 6 {conc#896.itm(0)} {conc#896.itm(1)} {conc#896.itm(2)} {conc#896.itm(3)} {conc#896.itm(4)} {conc#896.itm(5)} -attr xrf 62966 -attr oid 156 -attr vt d -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {ACC1-1:exs#1063.itm(0)} -attr vt d
+load net {ACC1-1:exs#1063.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1063.itm} 2 {ACC1-1:exs#1063.itm(0)} {ACC1-1:exs#1063.itm(1)} -attr xrf 62967 -attr oid 157 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1063.itm}
+load net {ACC1:acc#706.itm(0)} -attr vt d
+load net {ACC1:acc#706.itm(1)} -attr vt d
+load net {ACC1:acc#706.itm(2)} -attr vt d
+load net {ACC1:acc#706.itm(3)} -attr vt d
+load net {ACC1:acc#706.itm(4)} -attr vt d
+load netBundle {ACC1:acc#706.itm} 5 {ACC1:acc#706.itm(0)} {ACC1:acc#706.itm(1)} {ACC1:acc#706.itm(2)} {ACC1:acc#706.itm(3)} {ACC1:acc#706.itm(4)} -attr xrf 62968 -attr oid 158 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#702.itm(0)} -attr vt d
+load net {ACC1:acc#702.itm(1)} -attr vt d
+load net {ACC1:acc#702.itm(2)} -attr vt d
+load net {ACC1:acc#702.itm(3)} -attr vt d
+load netBundle {ACC1:acc#702.itm} 4 {ACC1:acc#702.itm(0)} {ACC1:acc#702.itm(1)} {ACC1:acc#702.itm(2)} {ACC1:acc#702.itm(3)} -attr xrf 62969 -attr oid 159 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:slc#160.itm(0)} -attr vt d
+load net {ACC1:slc#160.itm(1)} -attr vt d
+load net {ACC1:slc#160.itm(2)} -attr vt d
+load netBundle {ACC1:slc#160.itm} 3 {ACC1:slc#160.itm(0)} {ACC1:slc#160.itm(1)} {ACC1:slc#160.itm(2)} -attr xrf 62970 -attr oid 160 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#160.itm}
+load net {ACC1:acc#696.itm(0)} -attr vt d
+load net {ACC1:acc#696.itm(1)} -attr vt d
+load net {ACC1:acc#696.itm(2)} -attr vt d
+load net {ACC1:acc#696.itm(3)} -attr vt d
+load netBundle {ACC1:acc#696.itm} 4 {ACC1:acc#696.itm(0)} {ACC1:acc#696.itm(1)} {ACC1:acc#696.itm(2)} {ACC1:acc#696.itm(3)} -attr xrf 62971 -attr oid 161 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#696.itm}
+load net {exs#50.itm(0)} -attr vt d
+load net {exs#50.itm(1)} -attr vt d
+load net {exs#50.itm(2)} -attr vt d
+load netBundle {exs#50.itm} 3 {exs#50.itm(0)} {exs#50.itm(1)} {exs#50.itm(2)} -attr xrf 62972 -attr oid 162 -attr vt d -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {conc#897.itm(0)} -attr vt d
+load net {conc#897.itm(1)} -attr vt d
+load netBundle {conc#897.itm} 2 {conc#897.itm(0)} {conc#897.itm(1)} -attr xrf 62973 -attr oid 163 -attr vt d -attr @path {/sobel/sobel:core/conc#897.itm}
+load net {ACC1:exs#1485.itm(0)} -attr vt d
+load net {ACC1:exs#1485.itm(1)} -attr vt d
+load net {ACC1:exs#1485.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1485.itm} 3 {ACC1:exs#1485.itm(0)} {ACC1:exs#1485.itm(1)} {ACC1:exs#1485.itm(2)} -attr xrf 62974 -attr oid 164 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1485.itm}
+load net {ACC1:conc#1445.itm(0)} -attr vt d
+load net {ACC1:conc#1445.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1445.itm} 2 {ACC1:conc#1445.itm(0)} {ACC1:conc#1445.itm(1)} -attr xrf 62975 -attr oid 165 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1445.itm}
+load net {ACC1:slc#159.itm(0)} -attr vt d
+load net {ACC1:slc#159.itm(1)} -attr vt d
+load net {ACC1:slc#159.itm(2)} -attr vt d
+load netBundle {ACC1:slc#159.itm} 3 {ACC1:slc#159.itm(0)} {ACC1:slc#159.itm(1)} {ACC1:slc#159.itm(2)} -attr xrf 62976 -attr oid 166 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#159.itm}
+load net {ACC1:acc#695.itm(0)} -attr vt d
+load net {ACC1:acc#695.itm(1)} -attr vt d
+load net {ACC1:acc#695.itm(2)} -attr vt d
+load net {ACC1:acc#695.itm(3)} -attr vt d
+load netBundle {ACC1:acc#695.itm} 4 {ACC1:acc#695.itm(0)} {ACC1:acc#695.itm(1)} {ACC1:acc#695.itm(2)} {ACC1:acc#695.itm(3)} -attr xrf 62977 -attr oid 167 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#695.itm}
+load net {exs#51.itm(0)} -attr vt d
+load net {exs#51.itm(1)} -attr vt d
+load net {exs#51.itm(2)} -attr vt d
+load netBundle {exs#51.itm} 3 {exs#51.itm(0)} {exs#51.itm(1)} {exs#51.itm(2)} -attr xrf 62978 -attr oid 168 -attr vt d -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {conc#898.itm(0)} -attr vt d
+load net {conc#898.itm(1)} -attr vt d
+load netBundle {conc#898.itm} 2 {conc#898.itm(0)} {conc#898.itm(1)} -attr xrf 62979 -attr oid 169 -attr vt d -attr @path {/sobel/sobel:core/conc#898.itm}
+load net {ACC1:exs#1487.itm(0)} -attr vt d
+load net {ACC1:exs#1487.itm(1)} -attr vt d
+load net {ACC1:exs#1487.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1487.itm} 3 {ACC1:exs#1487.itm(0)} {ACC1:exs#1487.itm(1)} {ACC1:exs#1487.itm(2)} -attr xrf 62980 -attr oid 170 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1487.itm}
+load net {ACC1:conc#1443.itm(0)} -attr vt d
+load net {ACC1:conc#1443.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1443.itm} 2 {ACC1:conc#1443.itm(0)} {ACC1:conc#1443.itm(1)} -attr xrf 62981 -attr oid 171 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1443.itm}
+load net {ACC1:acc#701.itm(0)} -attr vt d
+load net {ACC1:acc#701.itm(1)} -attr vt d
+load net {ACC1:acc#701.itm(2)} -attr vt d
+load net {ACC1:acc#701.itm(3)} -attr vt d
+load netBundle {ACC1:acc#701.itm} 4 {ACC1:acc#701.itm(0)} {ACC1:acc#701.itm(1)} {ACC1:acc#701.itm(2)} {ACC1:acc#701.itm(3)} -attr xrf 62982 -attr oid 172 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:slc#158.itm(0)} -attr vt d
+load net {ACC1:slc#158.itm(1)} -attr vt d
+load net {ACC1:slc#158.itm(2)} -attr vt d
+load netBundle {ACC1:slc#158.itm} 3 {ACC1:slc#158.itm(0)} {ACC1:slc#158.itm(1)} {ACC1:slc#158.itm(2)} -attr xrf 62983 -attr oid 173 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#158.itm}
+load net {ACC1:acc#694.itm(0)} -attr vt d
+load net {ACC1:acc#694.itm(1)} -attr vt d
+load net {ACC1:acc#694.itm(2)} -attr vt d
+load net {ACC1:acc#694.itm(3)} -attr vt d
+load netBundle {ACC1:acc#694.itm} 4 {ACC1:acc#694.itm(0)} {ACC1:acc#694.itm(1)} {ACC1:acc#694.itm(2)} {ACC1:acc#694.itm(3)} -attr xrf 62984 -attr oid 174 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#694.itm}
+load net {exs#52.itm(0)} -attr vt d
+load net {exs#52.itm(1)} -attr vt d
+load net {exs#52.itm(2)} -attr vt d
+load netBundle {exs#52.itm} 3 {exs#52.itm(0)} {exs#52.itm(1)} {exs#52.itm(2)} -attr xrf 62985 -attr oid 175 -attr vt d -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {conc#899.itm(0)} -attr vt d
+load net {conc#899.itm(1)} -attr vt d
+load netBundle {conc#899.itm} 2 {conc#899.itm(0)} {conc#899.itm(1)} -attr xrf 62986 -attr oid 176 -attr vt d -attr @path {/sobel/sobel:core/conc#899.itm}
+load net {ACC1:exs#1489.itm(0)} -attr vt d
+load net {ACC1:exs#1489.itm(1)} -attr vt d
+load net {ACC1:exs#1489.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1489.itm} 3 {ACC1:exs#1489.itm(0)} {ACC1:exs#1489.itm(1)} {ACC1:exs#1489.itm(2)} -attr xrf 62987 -attr oid 177 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1489.itm}
+load net {ACC1:conc#1441.itm(0)} -attr vt d
+load net {ACC1:conc#1441.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1441.itm} 2 {ACC1:conc#1441.itm(0)} {ACC1:conc#1441.itm(1)} -attr xrf 62988 -attr oid 178 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1441.itm}
+load net {ACC1:slc#157.itm(0)} -attr vt d
+load net {ACC1:slc#157.itm(1)} -attr vt d
+load net {ACC1:slc#157.itm(2)} -attr vt d
+load netBundle {ACC1:slc#157.itm} 3 {ACC1:slc#157.itm(0)} {ACC1:slc#157.itm(1)} {ACC1:slc#157.itm(2)} -attr xrf 62989 -attr oid 179 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#157.itm}
+load net {ACC1:acc#693.itm(0)} -attr vt d
+load net {ACC1:acc#693.itm(1)} -attr vt d
+load net {ACC1:acc#693.itm(2)} -attr vt d
+load net {ACC1:acc#693.itm(3)} -attr vt d
+load netBundle {ACC1:acc#693.itm} 4 {ACC1:acc#693.itm(0)} {ACC1:acc#693.itm(1)} {ACC1:acc#693.itm(2)} {ACC1:acc#693.itm(3)} -attr xrf 62990 -attr oid 180 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#693.itm}
+load net {exs#53.itm(0)} -attr vt d
+load net {exs#53.itm(1)} -attr vt d
+load net {exs#53.itm(2)} -attr vt d
+load netBundle {exs#53.itm} 3 {exs#53.itm(0)} {exs#53.itm(1)} {exs#53.itm(2)} -attr xrf 62991 -attr oid 181 -attr vt d -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {conc#900.itm(0)} -attr vt d
+load net {conc#900.itm(1)} -attr vt d
+load netBundle {conc#900.itm} 2 {conc#900.itm(0)} {conc#900.itm(1)} -attr xrf 62992 -attr oid 182 -attr vt d -attr @path {/sobel/sobel:core/conc#900.itm}
+load net {ACC1:exs#1491.itm(0)} -attr vt d
+load net {ACC1:exs#1491.itm(1)} -attr vt d
+load net {ACC1:exs#1491.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1491.itm} 3 {ACC1:exs#1491.itm(0)} {ACC1:exs#1491.itm(1)} {ACC1:exs#1491.itm(2)} -attr xrf 62993 -attr oid 183 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1491.itm}
+load net {ACC1:conc#1439.itm(0)} -attr vt d
+load net {ACC1:conc#1439.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1439.itm} 2 {ACC1:conc#1439.itm(0)} {ACC1:conc#1439.itm(1)} -attr xrf 62994 -attr oid 184 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1439.itm}
+load net {ACC1:acc#713.itm(0)} -attr vt d
+load net {ACC1:acc#713.itm(1)} -attr vt d
+load net {ACC1:acc#713.itm(2)} -attr vt d
+load net {ACC1:acc#713.itm(3)} -attr vt d
+load net {ACC1:acc#713.itm(4)} -attr vt d
+load net {ACC1:acc#713.itm(5)} -attr vt d
+load net {ACC1:acc#713.itm(6)} -attr vt d
+load net {ACC1:acc#713.itm(7)} -attr vt d
+load net {ACC1:acc#713.itm(8)} -attr vt d
+load net {ACC1:acc#713.itm(9)} -attr vt d
+load netBundle {ACC1:acc#713.itm} 10 {ACC1:acc#713.itm(0)} {ACC1:acc#713.itm(1)} {ACC1:acc#713.itm(2)} {ACC1:acc#713.itm(3)} {ACC1:acc#713.itm(4)} {ACC1:acc#713.itm(5)} {ACC1:acc#713.itm(6)} {ACC1:acc#713.itm(7)} {ACC1:acc#713.itm(8)} {ACC1:acc#713.itm(9)} -attr xrf 62995 -attr oid 185 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#711.itm(0)} -attr vt d
+load net {ACC1:acc#711.itm(1)} -attr vt d
+load net {ACC1:acc#711.itm(2)} -attr vt d
+load net {ACC1:acc#711.itm(3)} -attr vt d
+load net {ACC1:acc#711.itm(4)} -attr vt d
+load net {ACC1:acc#711.itm(5)} -attr vt d
+load net {ACC1:acc#711.itm(6)} -attr vt d
+load net {ACC1:acc#711.itm(7)} -attr vt d
+load netBundle {ACC1:acc#711.itm} 8 {ACC1:acc#711.itm(0)} {ACC1:acc#711.itm(1)} {ACC1:acc#711.itm(2)} {ACC1:acc#711.itm(3)} {ACC1:acc#711.itm(4)} {ACC1:acc#711.itm(5)} {ACC1:acc#711.itm(6)} {ACC1:acc#711.itm(7)} -attr xrf 62996 -attr oid 186 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#708.itm(0)} -attr vt d
+load net {ACC1:acc#708.itm(1)} -attr vt d
+load net {ACC1:acc#708.itm(2)} -attr vt d
+load net {ACC1:acc#708.itm(3)} -attr vt d
+load net {ACC1:acc#708.itm(4)} -attr vt d
+load net {ACC1:acc#708.itm(5)} -attr vt d
+load netBundle {ACC1:acc#708.itm} 6 {ACC1:acc#708.itm(0)} {ACC1:acc#708.itm(1)} {ACC1:acc#708.itm(2)} {ACC1:acc#708.itm(3)} {ACC1:acc#708.itm(4)} {ACC1:acc#708.itm(5)} -attr xrf 62997 -attr oid 187 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#705.itm(0)} -attr vt d
+load net {ACC1:acc#705.itm(1)} -attr vt d
+load net {ACC1:acc#705.itm(2)} -attr vt d
+load net {ACC1:acc#705.itm(3)} -attr vt d
+load netBundle {ACC1:acc#705.itm} 4 {ACC1:acc#705.itm(0)} {ACC1:acc#705.itm(1)} {ACC1:acc#705.itm(2)} {ACC1:acc#705.itm(3)} -attr xrf 62998 -attr oid 188 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#700.itm(0)} -attr vt d
+load net {ACC1:acc#700.itm(1)} -attr vt d
+load net {ACC1:acc#700.itm(2)} -attr vt d
+load netBundle {ACC1:acc#700.itm} 3 {ACC1:acc#700.itm(0)} {ACC1:acc#700.itm(1)} {ACC1:acc#700.itm(2)} -attr xrf 62999 -attr oid 189 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load net {ACC1:slc#155.itm(0)} -attr vt d
+load net {ACC1:slc#155.itm(1)} -attr vt d
+load net {ACC1:slc#155.itm(2)} -attr vt d
+load netBundle {ACC1:slc#155.itm} 3 {ACC1:slc#155.itm(0)} {ACC1:slc#155.itm(1)} {ACC1:slc#155.itm(2)} -attr xrf 63000 -attr oid 190 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#155.itm}
+load net {ACC1:acc#691.itm(0)} -attr vt d
+load net {ACC1:acc#691.itm(1)} -attr vt d
+load net {ACC1:acc#691.itm(2)} -attr vt d
+load net {ACC1:acc#691.itm(3)} -attr vt d
+load netBundle {ACC1:acc#691.itm} 4 {ACC1:acc#691.itm(0)} {ACC1:acc#691.itm(1)} {ACC1:acc#691.itm(2)} {ACC1:acc#691.itm(3)} -attr xrf 63001 -attr oid 191 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#691.itm}
+load net {conc#901.itm(0)} -attr vt d
+load net {conc#901.itm(1)} -attr vt d
+load net {conc#901.itm(2)} -attr vt d
+load netBundle {conc#901.itm} 3 {conc#901.itm(0)} {conc#901.itm(1)} {conc#901.itm(2)} -attr xrf 63002 -attr oid 192 -attr vt d -attr @path {/sobel/sobel:core/conc#901.itm}
+load net {ACC1:conc#1435.itm(0)} -attr vt d
+load net {ACC1:conc#1435.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1435.itm} 2 {ACC1:conc#1435.itm(0)} {ACC1:conc#1435.itm(1)} -attr xrf 63003 -attr oid 193 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1435.itm}
+load net {slc(ACC1:acc#223.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#223.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#223.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#223.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#223.psp#1.sva)#2.itm(1)} -attr xrf 63004 -attr oid 194 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp#1.sva)#2.itm}
+load net {ACC1:slc#156.itm(0)} -attr vt d
+load net {ACC1:slc#156.itm(1)} -attr vt d
+load net {ACC1:slc#156.itm(2)} -attr vt d
+load net {ACC1:slc#156.itm(3)} -attr vt d
+load netBundle {ACC1:slc#156.itm} 4 {ACC1:slc#156.itm(0)} {ACC1:slc#156.itm(1)} {ACC1:slc#156.itm(2)} {ACC1:slc#156.itm(3)} -attr xrf 63005 -attr oid 195 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#156.itm}
+load net {ACC1:acc#692.itm(0)} -attr vt d
+load net {ACC1:acc#692.itm(1)} -attr vt d
+load net {ACC1:acc#692.itm(2)} -attr vt d
+load net {ACC1:acc#692.itm(3)} -attr vt d
+load net {ACC1:acc#692.itm(4)} -attr vt d
+load netBundle {ACC1:acc#692.itm} 5 {ACC1:acc#692.itm(0)} {ACC1:acc#692.itm(1)} {ACC1:acc#692.itm(2)} {ACC1:acc#692.itm(3)} {ACC1:acc#692.itm(4)} -attr xrf 63006 -attr oid 196 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692.itm}
+load net {conc#902.itm(0)} -attr vt d
+load net {conc#902.itm(1)} -attr vt d
+load net {conc#902.itm(2)} -attr vt d
+load netBundle {conc#902.itm} 3 {conc#902.itm(0)} {conc#902.itm(1)} {conc#902.itm(2)} -attr xrf 63007 -attr oid 197 -attr vt d -attr @path {/sobel/sobel:core/conc#902.itm}
+load net {ACC1:conc#1437.itm(0)} -attr vt d
+load net {ACC1:conc#1437.itm(1)} -attr vt d
+load net {ACC1:conc#1437.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1437.itm} 3 {ACC1:conc#1437.itm(0)} {ACC1:conc#1437.itm(1)} {ACC1:conc#1437.itm(2)} -attr xrf 63008 -attr oid 198 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1437.itm}
+load net {ACC1:acc#704.itm(0)} -attr vt d
+load net {ACC1:acc#704.itm(1)} -attr vt d
+load net {ACC1:acc#704.itm(2)} -attr vt d
+load net {ACC1:acc#704.itm(3)} -attr vt d
+load net {ACC1:acc#704.itm(4)} -attr vt d
+load netBundle {ACC1:acc#704.itm} 5 {ACC1:acc#704.itm(0)} {ACC1:acc#704.itm(1)} {ACC1:acc#704.itm(2)} {ACC1:acc#704.itm(3)} {ACC1:acc#704.itm(4)} -attr xrf 63009 -attr oid 199 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1-1:conc#594.itm(0)} -attr vt d
+load net {ACC1-1:conc#594.itm(1)} -attr vt d
+load net {ACC1-1:conc#594.itm(2)} -attr vt d
+load net {ACC1-1:conc#594.itm(3)} -attr vt d
+load netBundle {ACC1-1:conc#594.itm} 4 {ACC1-1:conc#594.itm(0)} {ACC1-1:conc#594.itm(1)} {ACC1-1:conc#594.itm(2)} {ACC1-1:conc#594.itm(3)} -attr xrf 63010 -attr oid 200 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#594.itm}
+load net {ACC1-1:exs#1054.itm(0)} -attr vt d
+load net {ACC1-1:exs#1054.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1054.itm} 2 {ACC1-1:exs#1054.itm(0)} {ACC1-1:exs#1054.itm(1)} -attr xrf 63011 -attr oid 201 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1054.itm}
+load net {conc#903.itm(0)} -attr vt d
+load net {conc#903.itm(1)} -attr vt d
+load net {conc#903.itm(2)} -attr vt d
+load net {conc#903.itm(3)} -attr vt d
+load net {conc#903.itm(4)} -attr vt d
+load net {conc#903.itm(5)} -attr vt d
+load net {conc#903.itm(6)} -attr vt d
+load netBundle {conc#903.itm} 7 {conc#903.itm(0)} {conc#903.itm(1)} {conc#903.itm(2)} {conc#903.itm(3)} {conc#903.itm(4)} {conc#903.itm(5)} {conc#903.itm(6)} -attr xrf 63012 -attr oid 202 -attr vt d -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {ACC1:acc#710.itm(0)} -attr vt d
+load net {ACC1:acc#710.itm(1)} -attr vt d
+load net {ACC1:acc#710.itm(2)} -attr vt d
+load net {ACC1:acc#710.itm(3)} -attr vt d
+load net {ACC1:acc#710.itm(4)} -attr vt d
+load net {ACC1:acc#710.itm(5)} -attr vt d
+load net {ACC1:acc#710.itm(6)} -attr vt d
+load net {ACC1:acc#710.itm(7)} -attr vt d
+load netBundle {ACC1:acc#710.itm} 8 {ACC1:acc#710.itm(0)} {ACC1:acc#710.itm(1)} {ACC1:acc#710.itm(2)} {ACC1:acc#710.itm(3)} {ACC1:acc#710.itm(4)} {ACC1:acc#710.itm(5)} {ACC1:acc#710.itm(6)} {ACC1:acc#710.itm(7)} -attr xrf 63013 -attr oid 203 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1-1:exs#1040.itm(0)} -attr vt d
+load net {ACC1-1:exs#1040.itm(1)} -attr vt d
+load net {ACC1-1:exs#1040.itm(2)} -attr vt d
+load net {ACC1-1:exs#1040.itm(3)} -attr vt d
+load net {ACC1-1:exs#1040.itm(4)} -attr vt d
+load net {ACC1-1:exs#1040.itm(5)} -attr vt d
+load net {ACC1-1:exs#1040.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#1040.itm} 7 {ACC1-1:exs#1040.itm(0)} {ACC1-1:exs#1040.itm(1)} {ACC1-1:exs#1040.itm(2)} {ACC1-1:exs#1040.itm(3)} {ACC1-1:exs#1040.itm(4)} {ACC1-1:exs#1040.itm(5)} {ACC1-1:exs#1040.itm(6)} -attr xrf 63014 -attr oid 204 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {ACC1-1:conc#538.itm(0)} -attr vt d
+load net {ACC1-1:conc#538.itm(1)} -attr vt d
+load net {ACC1-1:conc#538.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#538.itm} 3 {ACC1-1:conc#538.itm(0)} {ACC1-1:conc#538.itm(1)} {ACC1-1:conc#538.itm(2)} -attr xrf 63015 -attr oid 205 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#538.itm}
+load net {ACC1-1:exs#1047.itm(0)} -attr vt d
+load net {ACC1-1:exs#1047.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1047.itm} 2 {ACC1-1:exs#1047.itm(0)} {ACC1-1:exs#1047.itm(1)} -attr xrf 63016 -attr oid 206 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1047.itm}
+load net {ACC1:acc#707.itm(0)} -attr vt d
+load net {ACC1:acc#707.itm(1)} -attr vt d
+load net {ACC1:acc#707.itm(2)} -attr vt d
+load net {ACC1:acc#707.itm(3)} -attr vt d
+load net {ACC1:acc#707.itm(4)} -attr vt d
+load net {ACC1:acc#707.itm(5)} -attr vt d
+load netBundle {ACC1:acc#707.itm} 6 {ACC1:acc#707.itm(0)} {ACC1:acc#707.itm(1)} {ACC1:acc#707.itm(2)} {ACC1:acc#707.itm(3)} {ACC1:acc#707.itm(4)} {ACC1:acc#707.itm(5)} -attr xrf 63017 -attr oid 207 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {conc#904.itm(0)} -attr vt d
+load net {conc#904.itm(1)} -attr vt d
+load net {conc#904.itm(2)} -attr vt d
+load net {conc#904.itm(3)} -attr vt d
+load net {conc#904.itm(4)} -attr vt d
+load netBundle {conc#904.itm} 5 {conc#904.itm(0)} {conc#904.itm(1)} {conc#904.itm(2)} {conc#904.itm(3)} {conc#904.itm(4)} -attr xrf 63018 -attr oid 208 -attr vt d -attr @path {/sobel/sobel:core/conc#904.itm}
+load net {ACC1:acc#703.itm(0)} -attr vt d
+load net {ACC1:acc#703.itm(1)} -attr vt d
+load net {ACC1:acc#703.itm(2)} -attr vt d
+load net {ACC1:acc#703.itm(3)} -attr vt d
+load netBundle {ACC1:acc#703.itm} 4 {ACC1:acc#703.itm(0)} {ACC1:acc#703.itm(1)} {ACC1:acc#703.itm(2)} {ACC1:acc#703.itm(3)} -attr xrf 63019 -attr oid 209 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:slc#161.itm(0)} -attr vt d
+load net {ACC1:slc#161.itm(1)} -attr vt d
+load net {ACC1:slc#161.itm(2)} -attr vt d
+load netBundle {ACC1:slc#161.itm} 3 {ACC1:slc#161.itm(0)} {ACC1:slc#161.itm(1)} {ACC1:slc#161.itm(2)} -attr xrf 63020 -attr oid 210 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#161.itm}
+load net {ACC1:acc#697.itm(0)} -attr vt d
+load net {ACC1:acc#697.itm(1)} -attr vt d
+load net {ACC1:acc#697.itm(2)} -attr vt d
+load net {ACC1:acc#697.itm(3)} -attr vt d
+load netBundle {ACC1:acc#697.itm} 4 {ACC1:acc#697.itm(0)} {ACC1:acc#697.itm(1)} {ACC1:acc#697.itm(2)} {ACC1:acc#697.itm(3)} -attr xrf 63021 -attr oid 211 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#697.itm}
+load net {exs#91.itm(0)} -attr vt d
+load net {exs#91.itm(1)} -attr vt d
+load net {exs#91.itm(2)} -attr vt d
+load netBundle {exs#91.itm} 3 {exs#91.itm(0)} {exs#91.itm(1)} {exs#91.itm(2)} -attr xrf 63022 -attr oid 212 -attr vt d -attr @path {/sobel/sobel:core/exs#91.itm}
+load net {conc#905.itm(0)} -attr vt d
+load net {conc#905.itm(1)} -attr vt d
+load netBundle {conc#905.itm} 2 {conc#905.itm(0)} {conc#905.itm(1)} -attr xrf 63023 -attr oid 213 -attr vt d -attr @path {/sobel/sobel:core/conc#905.itm}
+load net {ACC1:exs#1493.itm(0)} -attr vt d
+load net {ACC1:exs#1493.itm(1)} -attr vt d
+load net {ACC1:exs#1493.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1493.itm} 3 {ACC1:exs#1493.itm(0)} {ACC1:exs#1493.itm(1)} {ACC1:exs#1493.itm(2)} -attr xrf 63024 -attr oid 214 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1493.itm}
+load net {ACC1:conc#1447.itm(0)} -attr vt d
+load net {ACC1:conc#1447.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1447.itm} 2 {ACC1:conc#1447.itm(0)} {ACC1:conc#1447.itm(1)} -attr xrf 63025 -attr oid 215 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1447.itm}
+load net {conc#907.itm(0)} -attr vt d
+load net {conc#907.itm(1)} -attr vt d
+load net {conc#907.itm(2)} -attr vt d
+load net {conc#907.itm(3)} -attr vt d
+load net {conc#907.itm(4)} -attr vt d
+load net {conc#907.itm(5)} -attr vt d
+load net {conc#907.itm(6)} -attr vt d
+load net {conc#907.itm(7)} -attr vt d
+load net {conc#907.itm(8)} -attr vt d
+load net {conc#907.itm(9)} -attr vt d
+load net {conc#907.itm(10)} -attr vt d
+load netBundle {conc#907.itm} 11 {conc#907.itm(0)} {conc#907.itm(1)} {conc#907.itm(2)} {conc#907.itm(3)} {conc#907.itm(4)} {conc#907.itm(5)} {conc#907.itm(6)} {conc#907.itm(7)} {conc#907.itm(8)} {conc#907.itm(9)} {conc#907.itm(10)} -attr xrf 63026 -attr oid 216 -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {ACC1:acc#720.itm(0)} -attr vt d
+load net {ACC1:acc#720.itm(1)} -attr vt d
+load net {ACC1:acc#720.itm(2)} -attr vt d
+load netBundle {ACC1:acc#720.itm} 3 {ACC1:acc#720.itm(0)} {ACC1:acc#720.itm(1)} {ACC1:acc#720.itm(2)} -attr xrf 63027 -attr oid 217 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#720.itm}
+load net {ACC1:exs#1654.itm(0)} -attr vt d
+load net {ACC1:exs#1654.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1654.itm} 2 {ACC1:exs#1654.itm(0)} {ACC1:exs#1654.itm(1)} -attr xrf 63028 -attr oid 218 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1654.itm}
+load net {ACC1:acc#658.itm(0)} -attr vt d
+load net {ACC1:acc#658.itm(1)} -attr vt d
+load net {ACC1:acc#658.itm(2)} -attr vt d
+load net {ACC1:acc#658.itm(3)} -attr vt d
+load net {ACC1:acc#658.itm(4)} -attr vt d
+load net {ACC1:acc#658.itm(5)} -attr vt d
+load net {ACC1:acc#658.itm(6)} -attr vt d
+load net {ACC1:acc#658.itm(7)} -attr vt d
+load net {ACC1:acc#658.itm(8)} -attr vt d
+load net {ACC1:acc#658.itm(9)} -attr vt d
+load net {ACC1:acc#658.itm(10)} -attr vt d
+load net {ACC1:acc#658.itm(11)} -attr vt d
+load net {ACC1:acc#658.itm(12)} -attr vt d
+load netBundle {ACC1:acc#658.itm} 13 {ACC1:acc#658.itm(0)} {ACC1:acc#658.itm(1)} {ACC1:acc#658.itm(2)} {ACC1:acc#658.itm(3)} {ACC1:acc#658.itm(4)} {ACC1:acc#658.itm(5)} {ACC1:acc#658.itm(6)} {ACC1:acc#658.itm(7)} {ACC1:acc#658.itm(8)} {ACC1:acc#658.itm(9)} {ACC1:acc#658.itm(10)} {ACC1:acc#658.itm(11)} {ACC1:acc#658.itm(12)} -attr xrf 63029 -attr oid 219 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#651.itm(0)} -attr vt d
+load net {ACC1:acc#651.itm(1)} -attr vt d
+load net {ACC1:acc#651.itm(2)} -attr vt d
+load net {ACC1:acc#651.itm(3)} -attr vt d
+load net {ACC1:acc#651.itm(4)} -attr vt d
+load net {ACC1:acc#651.itm(5)} -attr vt d
+load net {ACC1:acc#651.itm(6)} -attr vt d
+load net {ACC1:acc#651.itm(7)} -attr vt d
+load net {ACC1:acc#651.itm(8)} -attr vt d
+load net {ACC1:acc#651.itm(9)} -attr vt d
+load net {ACC1:acc#651.itm(10)} -attr vt d
+load net {ACC1:acc#651.itm(11)} -attr vt d
+load netBundle {ACC1:acc#651.itm} 12 {ACC1:acc#651.itm(0)} {ACC1:acc#651.itm(1)} {ACC1:acc#651.itm(2)} {ACC1:acc#651.itm(3)} {ACC1:acc#651.itm(4)} {ACC1:acc#651.itm(5)} {ACC1:acc#651.itm(6)} {ACC1:acc#651.itm(7)} {ACC1:acc#651.itm(8)} {ACC1:acc#651.itm(9)} {ACC1:acc#651.itm(10)} {ACC1:acc#651.itm(11)} -attr xrf 63030 -attr oid 220 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#646.itm(0)} -attr vt d
+load net {ACC1:acc#646.itm(1)} -attr vt d
+load net {ACC1:acc#646.itm(2)} -attr vt d
+load net {ACC1:acc#646.itm(3)} -attr vt d
+load net {ACC1:acc#646.itm(4)} -attr vt d
+load net {ACC1:acc#646.itm(5)} -attr vt d
+load net {ACC1:acc#646.itm(6)} -attr vt d
+load net {ACC1:acc#646.itm(7)} -attr vt d
+load net {ACC1:acc#646.itm(8)} -attr vt d
+load net {ACC1:acc#646.itm(9)} -attr vt d
+load netBundle {ACC1:acc#646.itm} 10 {ACC1:acc#646.itm(0)} {ACC1:acc#646.itm(1)} {ACC1:acc#646.itm(2)} {ACC1:acc#646.itm(3)} {ACC1:acc#646.itm(4)} {ACC1:acc#646.itm(5)} {ACC1:acc#646.itm(6)} {ACC1:acc#646.itm(7)} {ACC1:acc#646.itm(8)} {ACC1:acc#646.itm(9)} -attr xrf 63031 -attr oid 221 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#635.itm(0)} -attr vt d
+load net {ACC1:acc#635.itm(1)} -attr vt d
+load net {ACC1:acc#635.itm(2)} -attr vt d
+load net {ACC1:acc#635.itm(3)} -attr vt d
+load net {ACC1:acc#635.itm(4)} -attr vt d
+load net {ACC1:acc#635.itm(5)} -attr vt d
+load net {ACC1:acc#635.itm(6)} -attr vt d
+load net {ACC1:acc#635.itm(7)} -attr vt d
+load net {ACC1:acc#635.itm(8)} -attr vt d
+load netBundle {ACC1:acc#635.itm} 9 {ACC1:acc#635.itm(0)} {ACC1:acc#635.itm(1)} {ACC1:acc#635.itm(2)} {ACC1:acc#635.itm(3)} {ACC1:acc#635.itm(4)} {ACC1:acc#635.itm(5)} {ACC1:acc#635.itm(6)} {ACC1:acc#635.itm(7)} {ACC1:acc#635.itm(8)} -attr xrf 63032 -attr oid 222 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#620.itm(0)} -attr vt d
+load net {ACC1:acc#620.itm(1)} -attr vt d
+load net {ACC1:acc#620.itm(2)} -attr vt d
+load net {ACC1:acc#620.itm(3)} -attr vt d
+load net {ACC1:acc#620.itm(4)} -attr vt d
+load net {ACC1:acc#620.itm(5)} -attr vt d
+load net {ACC1:acc#620.itm(6)} -attr vt d
+load netBundle {ACC1:acc#620.itm} 7 {ACC1:acc#620.itm(0)} {ACC1:acc#620.itm(1)} {ACC1:acc#620.itm(2)} {ACC1:acc#620.itm(3)} {ACC1:acc#620.itm(4)} {ACC1:acc#620.itm(5)} {ACC1:acc#620.itm(6)} -attr xrf 63033 -attr oid 223 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#601.itm(0)} -attr vt d
+load net {ACC1:acc#601.itm(1)} -attr vt d
+load net {ACC1:acc#601.itm(2)} -attr vt d
+load net {ACC1:acc#601.itm(3)} -attr vt d
+load net {ACC1:acc#601.itm(4)} -attr vt d
+load net {ACC1:acc#601.itm(5)} -attr vt d
+load netBundle {ACC1:acc#601.itm} 6 {ACC1:acc#601.itm(0)} {ACC1:acc#601.itm(1)} {ACC1:acc#601.itm(2)} {ACC1:acc#601.itm(3)} {ACC1:acc#601.itm(4)} {ACC1:acc#601.itm(5)} -attr xrf 63034 -attr oid 224 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#572.itm(0)} -attr vt d
+load net {ACC1:acc#572.itm(1)} -attr vt d
+load net {ACC1:acc#572.itm(2)} -attr vt d
+load net {ACC1:acc#572.itm(3)} -attr vt d
+load net {ACC1:acc#572.itm(4)} -attr vt d
+load netBundle {ACC1:acc#572.itm} 5 {ACC1:acc#572.itm(0)} {ACC1:acc#572.itm(1)} {ACC1:acc#572.itm(2)} {ACC1:acc#572.itm(3)} {ACC1:acc#572.itm(4)} -attr xrf 63035 -attr oid 225 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:conc#1108.itm(0)} -attr vt d
+load net {ACC1:conc#1108.itm(1)} -attr vt d
+load net {ACC1:conc#1108.itm(2)} -attr vt d
+load net {ACC1:conc#1108.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1108.itm} 4 {ACC1:conc#1108.itm(0)} {ACC1:conc#1108.itm(1)} {ACC1:conc#1108.itm(2)} {ACC1:conc#1108.itm(3)} -attr xrf 63036 -attr oid 226 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1108.itm}
+load net {ACC1-3:exs#1063.itm(0)} -attr vt d
+load net {ACC1-3:exs#1063.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1063.itm} 2 {ACC1-3:exs#1063.itm(0)} {ACC1-3:exs#1063.itm(1)} -attr xrf 63037 -attr oid 227 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1063.itm}
+load net {ACC1:conc#1109.itm(0)} -attr vt d
+load net {ACC1:conc#1109.itm(1)} -attr vt d
+load net {ACC1:conc#1109.itm(2)} -attr vt d
+load net {ACC1:conc#1109.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1109.itm} 4 {ACC1:conc#1109.itm(0)} {ACC1:conc#1109.itm(1)} {ACC1:conc#1109.itm(2)} {ACC1:conc#1109.itm(3)} -attr xrf 63038 -attr oid 228 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1109.itm}
+load net {ACC1-2:exs#1053.itm(0)} -attr vt d
+load net {ACC1-2:exs#1053.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1053.itm} 2 {ACC1-2:exs#1053.itm(0)} {ACC1-2:exs#1053.itm(1)} -attr xrf 63039 -attr oid 229 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1053.itm}
+load net {ACC1:acc#571.itm(0)} -attr vt d
+load net {ACC1:acc#571.itm(1)} -attr vt d
+load net {ACC1:acc#571.itm(2)} -attr vt d
+load net {ACC1:acc#571.itm(3)} -attr vt d
+load net {ACC1:acc#571.itm(4)} -attr vt d
+load netBundle {ACC1:acc#571.itm} 5 {ACC1:acc#571.itm(0)} {ACC1:acc#571.itm(1)} {ACC1:acc#571.itm(2)} {ACC1:acc#571.itm(3)} {ACC1:acc#571.itm(4)} -attr xrf 63040 -attr oid 230 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:conc#1110.itm(0)} -attr vt d
+load net {ACC1:conc#1110.itm(1)} -attr vt d
+load net {ACC1:conc#1110.itm(2)} -attr vt d
+load net {ACC1:conc#1110.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1110.itm} 4 {ACC1:conc#1110.itm(0)} {ACC1:conc#1110.itm(1)} {ACC1:conc#1110.itm(2)} {ACC1:conc#1110.itm(3)} -attr xrf 63041 -attr oid 231 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1110.itm}
+load net {ACC1-2:exs#1054.itm(0)} -attr vt d
+load net {ACC1-2:exs#1054.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1054.itm} 2 {ACC1-2:exs#1054.itm(0)} {ACC1-2:exs#1054.itm(1)} -attr xrf 63042 -attr oid 232 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1054.itm}
+load net {ACC1:conc#1111.itm(0)} -attr vt d
+load net {ACC1:conc#1111.itm(1)} -attr vt d
+load net {ACC1:conc#1111.itm(2)} -attr vt d
+load net {ACC1:conc#1111.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1111.itm} 4 {ACC1:conc#1111.itm(0)} {ACC1:conc#1111.itm(1)} {ACC1:conc#1111.itm(2)} {ACC1:conc#1111.itm(3)} -attr xrf 63043 -attr oid 233 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1111.itm}
+load net {ACC1-2:exs#1055.itm(0)} -attr vt d
+load net {ACC1-2:exs#1055.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1055.itm} 2 {ACC1-2:exs#1055.itm(0)} {ACC1-2:exs#1055.itm(1)} -attr xrf 63044 -attr oid 234 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1055.itm}
+load net {ACC1:acc#600.itm(0)} -attr vt d
+load net {ACC1:acc#600.itm(1)} -attr vt d
+load net {ACC1:acc#600.itm(2)} -attr vt d
+load net {ACC1:acc#600.itm(3)} -attr vt d
+load net {ACC1:acc#600.itm(4)} -attr vt d
+load net {ACC1:acc#600.itm(5)} -attr vt d
+load netBundle {ACC1:acc#600.itm} 6 {ACC1:acc#600.itm(0)} {ACC1:acc#600.itm(1)} {ACC1:acc#600.itm(2)} {ACC1:acc#600.itm(3)} {ACC1:acc#600.itm(4)} {ACC1:acc#600.itm(5)} -attr xrf 63045 -attr oid 235 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#570.itm(0)} -attr vt d
+load net {ACC1:acc#570.itm(1)} -attr vt d
+load net {ACC1:acc#570.itm(2)} -attr vt d
+load net {ACC1:acc#570.itm(3)} -attr vt d
+load net {ACC1:acc#570.itm(4)} -attr vt d
+load netBundle {ACC1:acc#570.itm} 5 {ACC1:acc#570.itm(0)} {ACC1:acc#570.itm(1)} {ACC1:acc#570.itm(2)} {ACC1:acc#570.itm(3)} {ACC1:acc#570.itm(4)} -attr xrf 63046 -attr oid 236 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {conc#908.itm(0)} -attr vt d
+load net {conc#908.itm(1)} -attr vt d
+load net {conc#908.itm(2)} -attr vt d
+load net {conc#908.itm(3)} -attr vt d
+load netBundle {conc#908.itm} 4 {conc#908.itm(0)} {conc#908.itm(1)} {conc#908.itm(2)} {conc#908.itm(3)} -attr xrf 63047 -attr oid 237 -attr vt d -attr @path {/sobel/sobel:core/conc#908.itm}
+load net {ACC1:conc#1113.itm(0)} -attr vt d
+load net {ACC1:conc#1113.itm(1)} -attr vt d
+load net {ACC1:conc#1113.itm(2)} -attr vt d
+load net {ACC1:conc#1113.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1113.itm} 4 {ACC1:conc#1113.itm(0)} {ACC1:conc#1113.itm(1)} {ACC1:conc#1113.itm(2)} {ACC1:conc#1113.itm(3)} -attr xrf 63048 -attr oid 238 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1113.itm}
+load net {ACC1-2:exs#1045.itm(0)} -attr vt d
+load net {ACC1-2:exs#1045.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1045.itm} 2 {ACC1-2:exs#1045.itm(0)} {ACC1-2:exs#1045.itm(1)} -attr xrf 63049 -attr oid 239 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1045.itm}
+load net {ACC1:acc#524.itm(0)} -attr vt d
+load net {ACC1:acc#524.itm(1)} -attr vt d
+load net {ACC1:acc#524.itm(2)} -attr vt d
+load net {ACC1:acc#524.itm(3)} -attr vt d
+load net {ACC1:acc#524.itm(4)} -attr vt d
+load netBundle {ACC1:acc#524.itm} 5 {ACC1:acc#524.itm(0)} {ACC1:acc#524.itm(1)} {ACC1:acc#524.itm(2)} {ACC1:acc#524.itm(3)} {ACC1:acc#524.itm(4)} -attr xrf 63050 -attr oid 240 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:slc#93.itm(0)} -attr vt d
+load net {ACC1:slc#93.itm(1)} -attr vt d
+load net {ACC1:slc#93.itm(2)} -attr vt d
+load netBundle {ACC1:slc#93.itm} 3 {ACC1:slc#93.itm(0)} {ACC1:slc#93.itm(1)} {ACC1:slc#93.itm(2)} -attr xrf 63051 -attr oid 241 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#425.itm(0)} -attr vt d
+load net {ACC1:acc#425.itm(1)} -attr vt d
+load net {ACC1:acc#425.itm(2)} -attr vt d
+load net {ACC1:acc#425.itm(3)} -attr vt d
+load netBundle {ACC1:acc#425.itm} 4 {ACC1:acc#425.itm(0)} {ACC1:acc#425.itm(1)} {ACC1:acc#425.itm(2)} {ACC1:acc#425.itm(3)} -attr xrf 63052 -attr oid 242 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#425.itm}
+load net {conc#909.itm(0)} -attr vt d
+load net {conc#909.itm(1)} -attr vt d
+load net {conc#909.itm(2)} -attr vt d
+load netBundle {conc#909.itm} 3 {conc#909.itm(0)} {conc#909.itm(1)} {conc#909.itm(2)} -attr xrf 63053 -attr oid 243 -attr vt d -attr @path {/sobel/sobel:core/conc#909.itm}
+load net {ACC1:conc#1309.itm(0)} -attr vt d
+load net {ACC1:conc#1309.itm(1)} -attr vt d
+load net {ACC1:conc#1309.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1309.itm} 3 {ACC1:conc#1309.itm(0)} {ACC1:conc#1309.itm(1)} {ACC1:conc#1309.itm(2)} -attr xrf 63054 -attr oid 244 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1309.itm}
+load net {ACC1:conc#1097.itm(0)} -attr vt d
+load net {ACC1:conc#1097.itm(1)} -attr vt d
+load net {ACC1:conc#1097.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1097.itm} 3 {ACC1:conc#1097.itm(0)} {ACC1:conc#1097.itm(1)} {ACC1:conc#1097.itm(2)} -attr xrf 63055 -attr oid 245 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1097.itm}
+load net {slc(ACC1:acc#223.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#223.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#223.psp.sva)#2.itm} 2 {slc(ACC1:acc#223.psp.sva)#2.itm(0)} {slc(ACC1:acc#223.psp.sva)#2.itm(1)} -attr xrf 63056 -attr oid 246 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp.sva)#2.itm}
+load net {ACC1:acc#619.itm(0)} -attr vt d
+load net {ACC1:acc#619.itm(1)} -attr vt d
+load net {ACC1:acc#619.itm(2)} -attr vt d
+load net {ACC1:acc#619.itm(3)} -attr vt d
+load net {ACC1:acc#619.itm(4)} -attr vt d
+load net {ACC1:acc#619.itm(5)} -attr vt d
+load net {ACC1:acc#619.itm(6)} -attr vt d
+load netBundle {ACC1:acc#619.itm} 7 {ACC1:acc#619.itm(0)} {ACC1:acc#619.itm(1)} {ACC1:acc#619.itm(2)} {ACC1:acc#619.itm(3)} {ACC1:acc#619.itm(4)} {ACC1:acc#619.itm(5)} {ACC1:acc#619.itm(6)} -attr xrf 63057 -attr oid 247 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#573.itm(0)} -attr vt d
+load net {ACC1:acc#573.itm(1)} -attr vt d
+load net {ACC1:acc#573.itm(2)} -attr vt d
+load net {ACC1:acc#573.itm(3)} -attr vt d
+load net {ACC1:acc#573.itm(4)} -attr vt d
+load net {ACC1:acc#573.itm(5)} -attr vt d
+load netBundle {ACC1:acc#573.itm} 6 {ACC1:acc#573.itm(0)} {ACC1:acc#573.itm(1)} {ACC1:acc#573.itm(2)} {ACC1:acc#573.itm(3)} {ACC1:acc#573.itm(4)} {ACC1:acc#573.itm(5)} -attr xrf 63058 -attr oid 248 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:slc#111.itm(0)} -attr vt d
+load net {ACC1:slc#111.itm(1)} -attr vt d
+load net {ACC1:slc#111.itm(2)} -attr vt d
+load net {ACC1:slc#111.itm(3)} -attr vt d
+load netBundle {ACC1:slc#111.itm} 4 {ACC1:slc#111.itm(0)} {ACC1:slc#111.itm(1)} {ACC1:slc#111.itm(2)} {ACC1:slc#111.itm(3)} -attr xrf 63059 -attr oid 249 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#111.itm}
+load net {ACC1:acc#443.itm(0)} -attr vt d
+load net {ACC1:acc#443.itm(1)} -attr vt d
+load net {ACC1:acc#443.itm(2)} -attr vt d
+load net {ACC1:acc#443.itm(3)} -attr vt d
+load net {ACC1:acc#443.itm(4)} -attr vt d
+load netBundle {ACC1:acc#443.itm} 5 {ACC1:acc#443.itm(0)} {ACC1:acc#443.itm(1)} {ACC1:acc#443.itm(2)} {ACC1:acc#443.itm(3)} {ACC1:acc#443.itm(4)} -attr xrf 63060 -attr oid 250 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443.itm}
+load net {exs#54.itm(0)} -attr vt d
+load net {exs#54.itm(1)} -attr vt d
+load net {exs#54.itm(2)} -attr vt d
+load netBundle {exs#54.itm} 3 {exs#54.itm(0)} {exs#54.itm(1)} {exs#54.itm(2)} -attr xrf 63061 -attr oid 251 -attr vt d -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {conc#910.itm(0)} -attr vt d
+load net {conc#910.itm(1)} -attr vt d
+load netBundle {conc#910.itm} 2 {conc#910.itm(0)} {conc#910.itm(1)} -attr xrf 63062 -attr oid 252 -attr vt d -attr @path {/sobel/sobel:core/conc#910.itm}
+load net {ACC1:conc#1345.itm(0)} -attr vt d
+load net {ACC1:conc#1345.itm(1)} -attr vt d
+load net {ACC1:conc#1345.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1345.itm} 3 {ACC1:conc#1345.itm(0)} {ACC1:conc#1345.itm(1)} {ACC1:conc#1345.itm(2)} -attr xrf 63063 -attr oid 253 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1345.itm}
+load net {slc(ACC1:acc#220.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#220.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#220.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#220.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#220.psp#1.sva)#2.itm(1)} -attr xrf 63064 -attr oid 254 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva)#2.itm}
+load net {ACC1:conc#1107.itm(0)} -attr vt d
+load net {ACC1:conc#1107.itm(1)} -attr vt d
+load net {ACC1:conc#1107.itm(2)} -attr vt d
+load net {ACC1:conc#1107.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1107.itm} 4 {ACC1:conc#1107.itm(0)} {ACC1:conc#1107.itm(1)} {ACC1:conc#1107.itm(2)} {ACC1:conc#1107.itm(3)} -attr xrf 63065 -attr oid 255 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1107.itm}
+load net {ACC1-3:exs#1064.itm(0)} -attr vt d
+load net {ACC1-3:exs#1064.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1064.itm} 2 {ACC1-3:exs#1064.itm(0)} {ACC1-3:exs#1064.itm(1)} -attr xrf 63066 -attr oid 256 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1064.itm}
+load net {ACC1:acc#569.itm(0)} -attr vt d
+load net {ACC1:acc#569.itm(1)} -attr vt d
+load net {ACC1:acc#569.itm(2)} -attr vt d
+load net {ACC1:acc#569.itm(3)} -attr vt d
+load net {ACC1:acc#569.itm(4)} -attr vt d
+load net {ACC1:acc#569.itm(5)} -attr vt d
+load netBundle {ACC1:acc#569.itm} 6 {ACC1:acc#569.itm(0)} {ACC1:acc#569.itm(1)} {ACC1:acc#569.itm(2)} {ACC1:acc#569.itm(3)} {ACC1:acc#569.itm(4)} {ACC1:acc#569.itm(5)} -attr xrf 63067 -attr oid 257 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:conc#1114.itm(0)} -attr vt d
+load net {ACC1:conc#1114.itm(1)} -attr vt d
+load net {ACC1:conc#1114.itm(2)} -attr vt d
+load net {ACC1:conc#1114.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1114.itm} 4 {ACC1:conc#1114.itm(0)} {ACC1:conc#1114.itm(1)} {ACC1:conc#1114.itm(2)} {ACC1:conc#1114.itm(3)} -attr xrf 63068 -attr oid 258 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1114.itm}
+load net {ACC1-2:exs#18.itm(0)} -attr vt d
+load net {ACC1-2:exs#18.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#18.itm} 2 {ACC1-2:exs#18.itm(0)} {ACC1-2:exs#18.itm(1)} -attr xrf 63069 -attr oid 259 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#18.itm}
+load net {ACC1:acc#519.itm(0)} -attr vt d
+load net {ACC1:acc#519.itm(1)} -attr vt d
+load net {ACC1:acc#519.itm(2)} -attr vt d
+load netBundle {ACC1:acc#519.itm} 3 {ACC1:acc#519.itm(0)} {ACC1:acc#519.itm(1)} {ACC1:acc#519.itm(2)} -attr xrf 63070 -attr oid 260 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load net {slc(ACC1:acc#220.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#220.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#220.psp.sva)#2.itm} 2 {slc(ACC1:acc#220.psp.sva)#2.itm(0)} {slc(ACC1:acc#220.psp.sva)#2.itm(1)} -attr xrf 63071 -attr oid 261 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp.sva)#2.itm}
+load net {slc(ACC1:acc#222.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#222.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#222.psp.sva)#2.itm} 2 {slc(ACC1:acc#222.psp.sva)#2.itm(0)} {slc(ACC1:acc#222.psp.sva)#2.itm(1)} -attr xrf 63072 -attr oid 262 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp.sva)#2.itm}
+load net {conc#911.itm(0)} -attr vt d
+load net {conc#911.itm(1)} -attr vt d
+load net {conc#911.itm(2)} -attr vt d
+load net {conc#911.itm(3)} -attr vt d
+load net {conc#911.itm(4)} -attr vt d
+load net {conc#911.itm(5)} -attr vt d
+load net {conc#911.itm(6)} -attr vt d
+load net {conc#911.itm(7)} -attr vt d
+load net {conc#911.itm(8)} -attr vt d
+load netBundle {conc#911.itm} 9 {conc#911.itm(0)} {conc#911.itm(1)} {conc#911.itm(2)} {conc#911.itm(3)} {conc#911.itm(4)} {conc#911.itm(5)} {conc#911.itm(6)} {conc#911.itm(7)} {conc#911.itm(8)} -attr xrf 63073 -attr oid 263 -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {ACC1-3:exs#1065.itm(0)} -attr vt d
+load net {ACC1-3:exs#1065.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1065.itm} 2 {ACC1-3:exs#1065.itm(0)} {ACC1-3:exs#1065.itm(1)} -attr xrf 63074 -attr oid 264 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1065.itm}
+load net {ACC1:mul#54.itm(0)} -attr vt d
+load net {ACC1:mul#54.itm(1)} -attr vt d
+load net {ACC1:mul#54.itm(2)} -attr vt d
+load net {ACC1:mul#54.itm(3)} -attr vt d
+load net {ACC1:mul#54.itm(4)} -attr vt d
+load net {ACC1:mul#54.itm(5)} -attr vt d
+load net {ACC1:mul#54.itm(6)} -attr vt d
+load net {ACC1:mul#54.itm(7)} -attr vt d
+load net {ACC1:mul#54.itm(8)} -attr vt d
+load net {ACC1:mul#54.itm(9)} -attr vt d
+load netBundle {ACC1:mul#54.itm} 10 {ACC1:mul#54.itm(0)} {ACC1:mul#54.itm(1)} {ACC1:mul#54.itm(2)} {ACC1:mul#54.itm(3)} {ACC1:mul#54.itm(4)} {ACC1:mul#54.itm(5)} {ACC1:mul#54.itm(6)} {ACC1:mul#54.itm(7)} {ACC1:mul#54.itm(8)} {ACC1:mul#54.itm(9)} -attr xrf 63075 -attr oid 265 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:acc#302.itm(0)} -attr vt d
+load net {ACC1:acc#302.itm(1)} -attr vt d
+load net {ACC1:acc#302.itm(2)} -attr vt d
+load net {ACC1:acc#302.itm(3)} -attr vt d
+load netBundle {ACC1:acc#302.itm} 4 {ACC1:acc#302.itm(0)} {ACC1:acc#302.itm(1)} {ACC1:acc#302.itm(2)} {ACC1:acc#302.itm(3)} -attr xrf 63076 -attr oid 266 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#303.itm(0)} -attr vt d
+load net {ACC1:acc#303.itm(1)} -attr vt d
+load net {ACC1:acc#303.itm(2)} -attr vt d
+load netBundle {ACC1:acc#303.itm} 3 {ACC1:acc#303.itm(0)} {ACC1:acc#303.itm(1)} {ACC1:acc#303.itm(2)} -attr xrf 63077 -attr oid 267 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#304.itm(0)} -attr vt d
+load net {ACC1:acc#304.itm(1)} -attr vt d
+load net {ACC1:acc#304.itm(2)} -attr vt d
+load netBundle {ACC1:acc#304.itm} 3 {ACC1:acc#304.itm(0)} {ACC1:acc#304.itm(1)} {ACC1:acc#304.itm(2)} -attr xrf 63078 -attr oid 268 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#305.itm(0)} -attr vt d
+load net {ACC1:acc#305.itm(1)} -attr vt d
+load net {ACC1:acc#305.itm(2)} -attr vt d
+load netBundle {ACC1:acc#305.itm} 3 {ACC1:acc#305.itm(0)} {ACC1:acc#305.itm(1)} {ACC1:acc#305.itm(2)} -attr xrf 63079 -attr oid 269 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#306.itm(0)} -attr vt d
+load net {ACC1:acc#306.itm(1)} -attr vt d
+load net {ACC1:acc#306.itm(2)} -attr vt d
+load netBundle {ACC1:acc#306.itm} 3 {ACC1:acc#306.itm(0)} {ACC1:acc#306.itm(1)} {ACC1:acc#306.itm(2)} -attr xrf 63080 -attr oid 270 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#307.itm(0)} -attr vt d
+load net {ACC1:acc#307.itm(1)} -attr vt d
+load netBundle {ACC1:acc#307.itm} 2 {ACC1:acc#307.itm(0)} {ACC1:acc#307.itm(1)} -attr xrf 63081 -attr oid 271 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#308.itm(0)} -attr vt d
+load net {ACC1:acc#308.itm(1)} -attr vt d
+load netBundle {ACC1:acc#308.itm} 2 {ACC1:acc#308.itm(0)} {ACC1:acc#308.itm(1)} -attr xrf 63082 -attr oid 272 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:mul#55.itm(0)} -attr vt d
+load net {ACC1:mul#55.itm(1)} -attr vt d
+load net {ACC1:mul#55.itm(2)} -attr vt d
+load net {ACC1:mul#55.itm(3)} -attr vt d
+load net {ACC1:mul#55.itm(4)} -attr vt d
+load net {ACC1:mul#55.itm(5)} -attr vt d
+load net {ACC1:mul#55.itm(6)} -attr vt d
+load net {ACC1:mul#55.itm(7)} -attr vt d
+load net {ACC1:mul#55.itm(8)} -attr vt d
+load net {ACC1:mul#55.itm(9)} -attr vt d
+load net {ACC1:mul#55.itm(10)} -attr vt d
+load net {ACC1:mul#55.itm(11)} -attr vt d
+load netBundle {ACC1:mul#55.itm} 12 {ACC1:mul#55.itm(0)} {ACC1:mul#55.itm(1)} {ACC1:mul#55.itm(2)} {ACC1:mul#55.itm(3)} {ACC1:mul#55.itm(4)} {ACC1:mul#55.itm(5)} {ACC1:mul#55.itm(6)} {ACC1:mul#55.itm(7)} {ACC1:mul#55.itm(8)} {ACC1:mul#55.itm(9)} {ACC1:mul#55.itm(10)} {ACC1:mul#55.itm(11)} -attr xrf 63083 -attr oid 273 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:acc#309.itm(0)} -attr vt d
+load net {ACC1:acc#309.itm(1)} -attr vt d
+load net {ACC1:acc#309.itm(2)} -attr vt d
+load net {ACC1:acc#309.itm(3)} -attr vt d
+load netBundle {ACC1:acc#309.itm} 4 {ACC1:acc#309.itm(0)} {ACC1:acc#309.itm(1)} {ACC1:acc#309.itm(2)} {ACC1:acc#309.itm(3)} -attr xrf 63084 -attr oid 274 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#310.itm(0)} -attr vt d
+load net {ACC1:acc#310.itm(1)} -attr vt d
+load net {ACC1:acc#310.itm(2)} -attr vt d
+load netBundle {ACC1:acc#310.itm} 3 {ACC1:acc#310.itm(0)} {ACC1:acc#310.itm(1)} {ACC1:acc#310.itm(2)} -attr xrf 63085 -attr oid 275 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#311.itm(0)} -attr vt d
+load net {ACC1:acc#311.itm(1)} -attr vt d
+load net {ACC1:acc#311.itm(2)} -attr vt d
+load netBundle {ACC1:acc#311.itm} 3 {ACC1:acc#311.itm(0)} {ACC1:acc#311.itm(1)} {ACC1:acc#311.itm(2)} -attr xrf 63086 -attr oid 276 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#312.itm(0)} -attr vt d
+load net {ACC1:acc#312.itm(1)} -attr vt d
+load net {ACC1:acc#312.itm(2)} -attr vt d
+load netBundle {ACC1:acc#312.itm} 3 {ACC1:acc#312.itm(0)} {ACC1:acc#312.itm(1)} {ACC1:acc#312.itm(2)} -attr xrf 63087 -attr oid 277 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#313.itm(0)} -attr vt d
+load net {ACC1:acc#313.itm(1)} -attr vt d
+load net {ACC1:acc#313.itm(2)} -attr vt d
+load netBundle {ACC1:acc#313.itm} 3 {ACC1:acc#313.itm(0)} {ACC1:acc#313.itm(1)} {ACC1:acc#313.itm(2)} -attr xrf 63088 -attr oid 278 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#314.itm(0)} -attr vt d
+load net {ACC1:acc#314.itm(1)} -attr vt d
+load netBundle {ACC1:acc#314.itm} 2 {ACC1:acc#314.itm(0)} {ACC1:acc#314.itm(1)} -attr xrf 63089 -attr oid 279 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#315.itm(0)} -attr vt d
+load net {ACC1:acc#315.itm(1)} -attr vt d
+load netBundle {ACC1:acc#315.itm} 2 {ACC1:acc#315.itm(0)} {ACC1:acc#315.itm(1)} -attr xrf 63090 -attr oid 280 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#661.itm(0)} -attr vt d
+load net {ACC1:acc#661.itm(1)} -attr vt d
+load net {ACC1:acc#661.itm(2)} -attr vt d
+load net {ACC1:acc#661.itm(3)} -attr vt d
+load net {ACC1:acc#661.itm(4)} -attr vt d
+load net {ACC1:acc#661.itm(5)} -attr vt d
+load net {ACC1:acc#661.itm(6)} -attr vt d
+load net {ACC1:acc#661.itm(7)} -attr vt d
+load net {ACC1:acc#661.itm(8)} -attr vt d
+load net {ACC1:acc#661.itm(9)} -attr vt d
+load net {ACC1:acc#661.itm(10)} -attr vt d
+load net {ACC1:acc#661.itm(11)} -attr vt d
+load net {ACC1:acc#661.itm(12)} -attr vt d
+load net {ACC1:acc#661.itm(13)} -attr vt d
+load netBundle {ACC1:acc#661.itm} 14 {ACC1:acc#661.itm(0)} {ACC1:acc#661.itm(1)} {ACC1:acc#661.itm(2)} {ACC1:acc#661.itm(3)} {ACC1:acc#661.itm(4)} {ACC1:acc#661.itm(5)} {ACC1:acc#661.itm(6)} {ACC1:acc#661.itm(7)} {ACC1:acc#661.itm(8)} {ACC1:acc#661.itm(9)} {ACC1:acc#661.itm(10)} {ACC1:acc#661.itm(11)} {ACC1:acc#661.itm(12)} {ACC1:acc#661.itm(13)} -attr xrf 63091 -attr oid 281 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#657.itm(0)} -attr vt d
+load net {ACC1:acc#657.itm(1)} -attr vt d
+load net {ACC1:acc#657.itm(2)} -attr vt d
+load net {ACC1:acc#657.itm(3)} -attr vt d
+load net {ACC1:acc#657.itm(4)} -attr vt d
+load net {ACC1:acc#657.itm(5)} -attr vt d
+load net {ACC1:acc#657.itm(6)} -attr vt d
+load net {ACC1:acc#657.itm(7)} -attr vt d
+load net {ACC1:acc#657.itm(8)} -attr vt d
+load net {ACC1:acc#657.itm(9)} -attr vt d
+load net {ACC1:acc#657.itm(10)} -attr vt d
+load net {ACC1:acc#657.itm(11)} -attr vt d
+load net {ACC1:acc#657.itm(12)} -attr vt d
+load netBundle {ACC1:acc#657.itm} 13 {ACC1:acc#657.itm(0)} {ACC1:acc#657.itm(1)} {ACC1:acc#657.itm(2)} {ACC1:acc#657.itm(3)} {ACC1:acc#657.itm(4)} {ACC1:acc#657.itm(5)} {ACC1:acc#657.itm(6)} {ACC1:acc#657.itm(7)} {ACC1:acc#657.itm(8)} {ACC1:acc#657.itm(9)} {ACC1:acc#657.itm(10)} {ACC1:acc#657.itm(11)} {ACC1:acc#657.itm(12)} -attr xrf 63092 -attr oid 282 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {conc#912.itm(0)} -attr vt d
+load net {conc#912.itm(1)} -attr vt d
+load net {conc#912.itm(2)} -attr vt d
+load net {conc#912.itm(3)} -attr vt d
+load net {conc#912.itm(4)} -attr vt d
+load net {conc#912.itm(5)} -attr vt d
+load net {conc#912.itm(6)} -attr vt d
+load net {conc#912.itm(7)} -attr vt d
+load net {conc#912.itm(8)} -attr vt d
+load net {conc#912.itm(9)} -attr vt d
+load net {conc#912.itm(10)} -attr vt d
+load net {conc#912.itm(11)} -attr vt d
+load netBundle {conc#912.itm} 12 {conc#912.itm(0)} {conc#912.itm(1)} {conc#912.itm(2)} {conc#912.itm(3)} {conc#912.itm(4)} {conc#912.itm(5)} {conc#912.itm(6)} {conc#912.itm(7)} {conc#912.itm(8)} {conc#912.itm(9)} {conc#912.itm(10)} {conc#912.itm(11)} -attr xrf 63093 -attr oid 283 -attr vt d -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {ACC1:conc#1106.itm(0)} -attr vt d
+load net {ACC1:conc#1106.itm(1)} -attr vt d
+load net {ACC1:conc#1106.itm(2)} -attr vt d
+load net {ACC1:conc#1106.itm(3)} -attr vt d
+load net {ACC1:conc#1106.itm(4)} -attr vt d
+load net {ACC1:conc#1106.itm(5)} -attr vt d
+load net {ACC1:conc#1106.itm(6)} -attr vt d
+load net {ACC1:conc#1106.itm(7)} -attr vt d
+load net {ACC1:conc#1106.itm(8)} -attr vt d
+load net {ACC1:conc#1106.itm(9)} -attr vt d
+load net {ACC1:conc#1106.itm(10)} -attr vt d
+load net {ACC1:conc#1106.itm(11)} -attr vt d
+load netBundle {ACC1:conc#1106.itm} 12 {ACC1:conc#1106.itm(0)} {ACC1:conc#1106.itm(1)} {ACC1:conc#1106.itm(2)} {ACC1:conc#1106.itm(3)} {ACC1:conc#1106.itm(4)} {ACC1:conc#1106.itm(5)} {ACC1:conc#1106.itm(6)} {ACC1:conc#1106.itm(7)} {ACC1:conc#1106.itm(8)} {ACC1:conc#1106.itm(9)} {ACC1:conc#1106.itm(10)} {ACC1:conc#1106.itm(11)} -attr xrf 63094 -attr oid 284 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(0)} -attr vt d
+load net {ACC1:mul#59.itm(1)} -attr vt d
+load net {ACC1:mul#59.itm(2)} -attr vt d
+load net {ACC1:mul#59.itm(3)} -attr vt d
+load net {ACC1:mul#59.itm(4)} -attr vt d
+load net {ACC1:mul#59.itm(5)} -attr vt d
+load net {ACC1:mul#59.itm(6)} -attr vt d
+load net {ACC1:mul#59.itm(7)} -attr vt d
+load net {ACC1:mul#59.itm(8)} -attr vt d
+load netBundle {ACC1:mul#59.itm} 9 {ACC1:mul#59.itm(0)} {ACC1:mul#59.itm(1)} {ACC1:mul#59.itm(2)} {ACC1:mul#59.itm(3)} {ACC1:mul#59.itm(4)} {ACC1:mul#59.itm(5)} {ACC1:mul#59.itm(6)} {ACC1:mul#59.itm(7)} {ACC1:mul#59.itm(8)} -attr xrf 63095 -attr oid 285 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:acc#327.itm(0)} -attr vt d
+load net {ACC1:acc#327.itm(1)} -attr vt d
+load net {ACC1:acc#327.itm(2)} -attr vt d
+load netBundle {ACC1:acc#327.itm} 3 {ACC1:acc#327.itm(0)} {ACC1:acc#327.itm(1)} {ACC1:acc#327.itm(2)} -attr xrf 63096 -attr oid 286 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#328.itm(0)} -attr vt d
+load net {ACC1:acc#328.itm(1)} -attr vt d
+load netBundle {ACC1:acc#328.itm} 2 {ACC1:acc#328.itm(0)} {ACC1:acc#328.itm(1)} -attr xrf 63097 -attr oid 287 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#329.itm(0)} -attr vt d
+load net {ACC1:acc#329.itm(1)} -attr vt d
+load netBundle {ACC1:acc#329.itm} 2 {ACC1:acc#329.itm(0)} {ACC1:acc#329.itm(1)} -attr xrf 63098 -attr oid 288 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1-3:exs#1034.itm(0)} -attr vt d
+load net {ACC1-3:exs#1034.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1034.itm} 2 {ACC1-3:exs#1034.itm(0)} {ACC1-3:exs#1034.itm(1)} -attr xrf 63099 -attr oid 289 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1034.itm}
+load net {ACC1:mul#56.itm(0)} -attr vt d
+load net {ACC1:mul#56.itm(1)} -attr vt d
+load net {ACC1:mul#56.itm(2)} -attr vt d
+load net {ACC1:mul#56.itm(3)} -attr vt d
+load net {ACC1:mul#56.itm(4)} -attr vt d
+load net {ACC1:mul#56.itm(5)} -attr vt d
+load net {ACC1:mul#56.itm(6)} -attr vt d
+load net {ACC1:mul#56.itm(7)} -attr vt d
+load net {ACC1:mul#56.itm(8)} -attr vt d
+load net {ACC1:mul#56.itm(9)} -attr vt d
+load net {ACC1:mul#56.itm(10)} -attr vt d
+load net {ACC1:mul#56.itm(11)} -attr vt d
+load net {ACC1:mul#56.itm(12)} -attr vt d
+load netBundle {ACC1:mul#56.itm} 13 {ACC1:mul#56.itm(0)} {ACC1:mul#56.itm(1)} {ACC1:mul#56.itm(2)} {ACC1:mul#56.itm(3)} {ACC1:mul#56.itm(4)} {ACC1:mul#56.itm(5)} {ACC1:mul#56.itm(6)} {ACC1:mul#56.itm(7)} {ACC1:mul#56.itm(8)} {ACC1:mul#56.itm(9)} {ACC1:mul#56.itm(10)} {ACC1:mul#56.itm(11)} {ACC1:mul#56.itm(12)} -attr xrf 63100 -attr oid 290 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:acc#316.itm(0)} -attr vt d
+load net {ACC1:acc#316.itm(1)} -attr vt d
+load netBundle {ACC1:acc#316.itm} 2 {ACC1:acc#316.itm(0)} {ACC1:acc#316.itm(1)} -attr xrf 63101 -attr oid 291 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#317.itm(0)} -attr vt d
+load net {ACC1:acc#317.itm(1)} -attr vt d
+load netBundle {ACC1:acc#317.itm} 2 {ACC1:acc#317.itm(0)} {ACC1:acc#317.itm(1)} -attr xrf 63102 -attr oid 292 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {slc(ACC1:mul#57.itm)#2.itm(0)} -attr vt d
+load net {slc(ACC1:mul#57.itm)#2.itm(1)} -attr vt d
+load net {slc(ACC1:mul#57.itm)#2.itm(2)} -attr vt d
+load net {slc(ACC1:mul#57.itm)#2.itm(3)} -attr vt d
+load net {slc(ACC1:mul#57.itm)#2.itm(4)} -attr vt d
+load netBundle {slc(ACC1:mul#57.itm)#2.itm} 5 {slc(ACC1:mul#57.itm)#2.itm(0)} {slc(ACC1:mul#57.itm)#2.itm(1)} {slc(ACC1:mul#57.itm)#2.itm(2)} {slc(ACC1:mul#57.itm)#2.itm(3)} {slc(ACC1:mul#57.itm)#2.itm(4)} -attr xrf 63103 -attr oid 293 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#2.itm}
+load net {slc(ACC1:mul#57.itm)#3.itm(0)} -attr vt d
+load net {slc(ACC1:mul#57.itm)#3.itm(1)} -attr vt d
+load netBundle {slc(ACC1:mul#57.itm)#3.itm} 2 {slc(ACC1:mul#57.itm)#3.itm(0)} {slc(ACC1:mul#57.itm)#3.itm(1)} -attr xrf 63104 -attr oid 294 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#3.itm}
+load net {ACC1:acc#652.itm(0)} -attr vt d
+load net {ACC1:acc#652.itm(1)} -attr vt d
+load net {ACC1:acc#652.itm(2)} -attr vt d
+load net {ACC1:acc#652.itm(3)} -attr vt d
+load net {ACC1:acc#652.itm(4)} -attr vt d
+load net {ACC1:acc#652.itm(5)} -attr vt d
+load net {ACC1:acc#652.itm(6)} -attr vt d
+load net {ACC1:acc#652.itm(7)} -attr vt d
+load net {ACC1:acc#652.itm(8)} -attr vt d
+load net {ACC1:acc#652.itm(9)} -attr vt d
+load net {ACC1:acc#652.itm(10)} -attr vt d
+load netBundle {ACC1:acc#652.itm} 11 {ACC1:acc#652.itm(0)} {ACC1:acc#652.itm(1)} {ACC1:acc#652.itm(2)} {ACC1:acc#652.itm(3)} {ACC1:acc#652.itm(4)} {ACC1:acc#652.itm(5)} {ACC1:acc#652.itm(6)} {ACC1:acc#652.itm(7)} {ACC1:acc#652.itm(8)} {ACC1:acc#652.itm(9)} {ACC1:acc#652.itm(10)} -attr xrf 63105 -attr oid 295 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#649.itm(0)} -attr vt d
+load net {ACC1:acc#649.itm(1)} -attr vt d
+load net {ACC1:acc#649.itm(2)} -attr vt d
+load net {ACC1:acc#649.itm(3)} -attr vt d
+load net {ACC1:acc#649.itm(4)} -attr vt d
+load net {ACC1:acc#649.itm(5)} -attr vt d
+load net {ACC1:acc#649.itm(6)} -attr vt d
+load net {ACC1:acc#649.itm(7)} -attr vt d
+load net {ACC1:acc#649.itm(8)} -attr vt d
+load net {ACC1:acc#649.itm(9)} -attr vt d
+load netBundle {ACC1:acc#649.itm} 10 {ACC1:acc#649.itm(0)} {ACC1:acc#649.itm(1)} {ACC1:acc#649.itm(2)} {ACC1:acc#649.itm(3)} {ACC1:acc#649.itm(4)} {ACC1:acc#649.itm(5)} {ACC1:acc#649.itm(6)} {ACC1:acc#649.itm(7)} {ACC1:acc#649.itm(8)} {ACC1:acc#649.itm(9)} -attr xrf 63106 -attr oid 296 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#644.itm(0)} -attr vt d
+load net {ACC1:acc#644.itm(1)} -attr vt d
+load net {ACC1:acc#644.itm(2)} -attr vt d
+load net {ACC1:acc#644.itm(3)} -attr vt d
+load net {ACC1:acc#644.itm(4)} -attr vt d
+load net {ACC1:acc#644.itm(5)} -attr vt d
+load net {ACC1:acc#644.itm(6)} -attr vt d
+load net {ACC1:acc#644.itm(7)} -attr vt d
+load net {ACC1:acc#644.itm(8)} -attr vt d
+load netBundle {ACC1:acc#644.itm} 9 {ACC1:acc#644.itm(0)} {ACC1:acc#644.itm(1)} {ACC1:acc#644.itm(2)} {ACC1:acc#644.itm(3)} {ACC1:acc#644.itm(4)} {ACC1:acc#644.itm(5)} {ACC1:acc#644.itm(6)} {ACC1:acc#644.itm(7)} {ACC1:acc#644.itm(8)} -attr xrf 63107 -attr oid 297 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#636.itm(0)} -attr vt d
+load net {ACC1:acc#636.itm(1)} -attr vt d
+load net {ACC1:acc#636.itm(2)} -attr vt d
+load net {ACC1:acc#636.itm(3)} -attr vt d
+load net {ACC1:acc#636.itm(4)} -attr vt d
+load net {ACC1:acc#636.itm(5)} -attr vt d
+load net {ACC1:acc#636.itm(6)} -attr vt d
+load net {ACC1:acc#636.itm(7)} -attr vt d
+load netBundle {ACC1:acc#636.itm} 8 {ACC1:acc#636.itm(0)} {ACC1:acc#636.itm(1)} {ACC1:acc#636.itm(2)} {ACC1:acc#636.itm(3)} {ACC1:acc#636.itm(4)} {ACC1:acc#636.itm(5)} {ACC1:acc#636.itm(6)} {ACC1:acc#636.itm(7)} -attr xrf 63108 -attr oid 298 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#623.itm(0)} -attr vt d
+load net {ACC1:acc#623.itm(1)} -attr vt d
+load net {ACC1:acc#623.itm(2)} -attr vt d
+load net {ACC1:acc#623.itm(3)} -attr vt d
+load net {ACC1:acc#623.itm(4)} -attr vt d
+load net {ACC1:acc#623.itm(5)} -attr vt d
+load net {ACC1:acc#623.itm(6)} -attr vt d
+load netBundle {ACC1:acc#623.itm} 7 {ACC1:acc#623.itm(0)} {ACC1:acc#623.itm(1)} {ACC1:acc#623.itm(2)} {ACC1:acc#623.itm(3)} {ACC1:acc#623.itm(4)} {ACC1:acc#623.itm(5)} {ACC1:acc#623.itm(6)} -attr xrf 63109 -attr oid 299 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#607.itm(0)} -attr vt d
+load net {ACC1:acc#607.itm(1)} -attr vt d
+load net {ACC1:acc#607.itm(2)} -attr vt d
+load net {ACC1:acc#607.itm(3)} -attr vt d
+load net {ACC1:acc#607.itm(4)} -attr vt d
+load net {ACC1:acc#607.itm(5)} -attr vt d
+load netBundle {ACC1:acc#607.itm} 6 {ACC1:acc#607.itm(0)} {ACC1:acc#607.itm(1)} {ACC1:acc#607.itm(2)} {ACC1:acc#607.itm(3)} {ACC1:acc#607.itm(4)} {ACC1:acc#607.itm(5)} -attr xrf 63110 -attr oid 300 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#585.itm(0)} -attr vt d
+load net {ACC1:acc#585.itm(1)} -attr vt d
+load net {ACC1:acc#585.itm(2)} -attr vt d
+load net {ACC1:acc#585.itm(3)} -attr vt d
+load net {ACC1:acc#585.itm(4)} -attr vt d
+load netBundle {ACC1:acc#585.itm} 5 {ACC1:acc#585.itm(0)} {ACC1:acc#585.itm(1)} {ACC1:acc#585.itm(2)} {ACC1:acc#585.itm(3)} {ACC1:acc#585.itm(4)} -attr xrf 63111 -attr oid 301 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#540.itm(0)} -attr vt d
+load net {ACC1:acc#540.itm(1)} -attr vt d
+load net {ACC1:acc#540.itm(2)} -attr vt d
+load net {ACC1:acc#540.itm(3)} -attr vt d
+load netBundle {ACC1:acc#540.itm} 4 {ACC1:acc#540.itm(0)} {ACC1:acc#540.itm(1)} {ACC1:acc#540.itm(2)} {ACC1:acc#540.itm(3)} -attr xrf 63112 -attr oid 302 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:slc#126.itm(0)} -attr vt d
+load net {ACC1:slc#126.itm(1)} -attr vt d
+load net {ACC1:slc#126.itm(2)} -attr vt d
+load netBundle {ACC1:slc#126.itm} 3 {ACC1:slc#126.itm(0)} {ACC1:slc#126.itm(1)} {ACC1:slc#126.itm(2)} -attr xrf 63113 -attr oid 303 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#126.itm}
+load net {ACC1:acc#458.itm(0)} -attr vt d
+load net {ACC1:acc#458.itm(1)} -attr vt d
+load net {ACC1:acc#458.itm(2)} -attr vt d
+load net {ACC1:acc#458.itm(3)} -attr vt d
+load netBundle {ACC1:acc#458.itm} 4 {ACC1:acc#458.itm(0)} {ACC1:acc#458.itm(1)} {ACC1:acc#458.itm(2)} {ACC1:acc#458.itm(3)} -attr xrf 63114 -attr oid 304 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#458.itm}
+load net {exs#55.itm(0)} -attr vt d
+load net {exs#55.itm(1)} -attr vt d
+load net {exs#55.itm(2)} -attr vt d
+load netBundle {exs#55.itm} 3 {exs#55.itm(0)} {exs#55.itm(1)} {exs#55.itm(2)} -attr xrf 63115 -attr oid 305 -attr vt d -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {conc#913.itm(0)} -attr vt d
+load net {conc#913.itm(1)} -attr vt d
+load netBundle {conc#913.itm} 2 {conc#913.itm(0)} {conc#913.itm(1)} -attr xrf 63116 -attr oid 306 -attr vt d -attr @path {/sobel/sobel:core/conc#913.itm}
+load net {ACC1:exs#1497.itm(0)} -attr vt d
+load net {ACC1:exs#1497.itm(1)} -attr vt d
+load net {ACC1:exs#1497.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1497.itm} 3 {ACC1:exs#1497.itm(0)} {ACC1:exs#1497.itm(1)} {ACC1:exs#1497.itm(2)} -attr xrf 63117 -attr oid 307 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1497.itm}
+load net {ACC1:conc#1375.itm(0)} -attr vt d
+load net {ACC1:conc#1375.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1375.itm} 2 {ACC1:conc#1375.itm(0)} {ACC1:conc#1375.itm(1)} -attr xrf 63118 -attr oid 308 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1375.itm}
+load net {ACC1:slc#125.itm(0)} -attr vt d
+load net {ACC1:slc#125.itm(1)} -attr vt d
+load net {ACC1:slc#125.itm(2)} -attr vt d
+load netBundle {ACC1:slc#125.itm} 3 {ACC1:slc#125.itm(0)} {ACC1:slc#125.itm(1)} {ACC1:slc#125.itm(2)} -attr xrf 63119 -attr oid 309 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#125.itm}
+load net {ACC1:acc#457.itm(0)} -attr vt d
+load net {ACC1:acc#457.itm(1)} -attr vt d
+load net {ACC1:acc#457.itm(2)} -attr vt d
+load net {ACC1:acc#457.itm(3)} -attr vt d
+load netBundle {ACC1:acc#457.itm} 4 {ACC1:acc#457.itm(0)} {ACC1:acc#457.itm(1)} {ACC1:acc#457.itm(2)} {ACC1:acc#457.itm(3)} -attr xrf 63120 -attr oid 310 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#457.itm}
+load net {exs#56.itm(0)} -attr vt d
+load net {exs#56.itm(1)} -attr vt d
+load net {exs#56.itm(2)} -attr vt d
+load netBundle {exs#56.itm} 3 {exs#56.itm(0)} {exs#56.itm(1)} {exs#56.itm(2)} -attr xrf 63121 -attr oid 311 -attr vt d -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {conc#914.itm(0)} -attr vt d
+load net {conc#914.itm(1)} -attr vt d
+load netBundle {conc#914.itm} 2 {conc#914.itm(0)} {conc#914.itm(1)} -attr xrf 63122 -attr oid 312 -attr vt d -attr @path {/sobel/sobel:core/conc#914.itm}
+load net {ACC1:exs#1499.itm(0)} -attr vt d
+load net {ACC1:exs#1499.itm(1)} -attr vt d
+load net {ACC1:exs#1499.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1499.itm} 3 {ACC1:exs#1499.itm(0)} {ACC1:exs#1499.itm(1)} {ACC1:exs#1499.itm(2)} -attr xrf 63123 -attr oid 313 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1499.itm}
+load net {ACC1:conc#1373.itm(0)} -attr vt d
+load net {ACC1:conc#1373.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1373.itm} 2 {ACC1:conc#1373.itm(0)} {ACC1:conc#1373.itm(1)} -attr xrf 63124 -attr oid 314 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1373.itm}
+load net {ACC1:acc#539.itm(0)} -attr vt d
+load net {ACC1:acc#539.itm(1)} -attr vt d
+load net {ACC1:acc#539.itm(2)} -attr vt d
+load net {ACC1:acc#539.itm(3)} -attr vt d
+load netBundle {ACC1:acc#539.itm} 4 {ACC1:acc#539.itm(0)} {ACC1:acc#539.itm(1)} {ACC1:acc#539.itm(2)} {ACC1:acc#539.itm(3)} -attr xrf 63125 -attr oid 315 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:slc#124.itm(0)} -attr vt d
+load net {ACC1:slc#124.itm(1)} -attr vt d
+load net {ACC1:slc#124.itm(2)} -attr vt d
+load netBundle {ACC1:slc#124.itm} 3 {ACC1:slc#124.itm(0)} {ACC1:slc#124.itm(1)} {ACC1:slc#124.itm(2)} -attr xrf 63126 -attr oid 316 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#124.itm}
+load net {ACC1:acc#456.itm(0)} -attr vt d
+load net {ACC1:acc#456.itm(1)} -attr vt d
+load net {ACC1:acc#456.itm(2)} -attr vt d
+load net {ACC1:acc#456.itm(3)} -attr vt d
+load netBundle {ACC1:acc#456.itm} 4 {ACC1:acc#456.itm(0)} {ACC1:acc#456.itm(1)} {ACC1:acc#456.itm(2)} {ACC1:acc#456.itm(3)} -attr xrf 63127 -attr oid 317 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#456.itm}
+load net {exs#57.itm(0)} -attr vt d
+load net {exs#57.itm(1)} -attr vt d
+load net {exs#57.itm(2)} -attr vt d
+load netBundle {exs#57.itm} 3 {exs#57.itm(0)} {exs#57.itm(1)} {exs#57.itm(2)} -attr xrf 63128 -attr oid 318 -attr vt d -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {conc#915.itm(0)} -attr vt d
+load net {conc#915.itm(1)} -attr vt d
+load netBundle {conc#915.itm} 2 {conc#915.itm(0)} {conc#915.itm(1)} -attr xrf 63129 -attr oid 319 -attr vt d -attr @path {/sobel/sobel:core/conc#915.itm}
+load net {ACC1:exs#1501.itm(0)} -attr vt d
+load net {ACC1:exs#1501.itm(1)} -attr vt d
+load net {ACC1:exs#1501.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1501.itm} 3 {ACC1:exs#1501.itm(0)} {ACC1:exs#1501.itm(1)} {ACC1:exs#1501.itm(2)} -attr xrf 63130 -attr oid 320 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1501.itm}
+load net {ACC1:conc#1371.itm(0)} -attr vt d
+load net {ACC1:conc#1371.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1371.itm} 2 {ACC1:conc#1371.itm(0)} {ACC1:conc#1371.itm(1)} -attr xrf 63131 -attr oid 321 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1371.itm}
+load net {ACC1:slc#123.itm(0)} -attr vt d
+load net {ACC1:slc#123.itm(1)} -attr vt d
+load net {ACC1:slc#123.itm(2)} -attr vt d
+load netBundle {ACC1:slc#123.itm} 3 {ACC1:slc#123.itm(0)} {ACC1:slc#123.itm(1)} {ACC1:slc#123.itm(2)} -attr xrf 63132 -attr oid 322 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#123.itm}
+load net {ACC1:acc#455.itm(0)} -attr vt d
+load net {ACC1:acc#455.itm(1)} -attr vt d
+load net {ACC1:acc#455.itm(2)} -attr vt d
+load net {ACC1:acc#455.itm(3)} -attr vt d
+load netBundle {ACC1:acc#455.itm} 4 {ACC1:acc#455.itm(0)} {ACC1:acc#455.itm(1)} {ACC1:acc#455.itm(2)} {ACC1:acc#455.itm(3)} -attr xrf 63133 -attr oid 323 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#455.itm}
+load net {exs#58.itm(0)} -attr vt d
+load net {exs#58.itm(1)} -attr vt d
+load net {exs#58.itm(2)} -attr vt d
+load netBundle {exs#58.itm} 3 {exs#58.itm(0)} {exs#58.itm(1)} {exs#58.itm(2)} -attr xrf 63134 -attr oid 324 -attr vt d -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {conc#916.itm(0)} -attr vt d
+load net {conc#916.itm(1)} -attr vt d
+load netBundle {conc#916.itm} 2 {conc#916.itm(0)} {conc#916.itm(1)} -attr xrf 63135 -attr oid 325 -attr vt d -attr @path {/sobel/sobel:core/conc#916.itm}
+load net {ACC1:exs#1503.itm(0)} -attr vt d
+load net {ACC1:exs#1503.itm(1)} -attr vt d
+load net {ACC1:exs#1503.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1503.itm} 3 {ACC1:exs#1503.itm(0)} {ACC1:exs#1503.itm(1)} {ACC1:exs#1503.itm(2)} -attr xrf 63136 -attr oid 326 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1503.itm}
+load net {ACC1:conc#1369.itm(0)} -attr vt d
+load net {ACC1:conc#1369.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1369.itm} 2 {ACC1:conc#1369.itm(0)} {ACC1:conc#1369.itm(1)} -attr xrf 63137 -attr oid 327 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1369.itm}
+load net {ACC1:acc#584.itm(0)} -attr vt d
+load net {ACC1:acc#584.itm(1)} -attr vt d
+load net {ACC1:acc#584.itm(2)} -attr vt d
+load net {ACC1:acc#584.itm(3)} -attr vt d
+load net {ACC1:acc#584.itm(4)} -attr vt d
+load netBundle {ACC1:acc#584.itm} 5 {ACC1:acc#584.itm(0)} {ACC1:acc#584.itm(1)} {ACC1:acc#584.itm(2)} {ACC1:acc#584.itm(3)} {ACC1:acc#584.itm(4)} -attr xrf 63138 -attr oid 328 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#538.itm(0)} -attr vt d
+load net {ACC1:acc#538.itm(1)} -attr vt d
+load net {ACC1:acc#538.itm(2)} -attr vt d
+load net {ACC1:acc#538.itm(3)} -attr vt d
+load netBundle {ACC1:acc#538.itm} 4 {ACC1:acc#538.itm(0)} {ACC1:acc#538.itm(1)} {ACC1:acc#538.itm(2)} {ACC1:acc#538.itm(3)} -attr xrf 63139 -attr oid 329 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:slc#122.itm(0)} -attr vt d
+load net {ACC1:slc#122.itm(1)} -attr vt d
+load net {ACC1:slc#122.itm(2)} -attr vt d
+load netBundle {ACC1:slc#122.itm} 3 {ACC1:slc#122.itm(0)} {ACC1:slc#122.itm(1)} {ACC1:slc#122.itm(2)} -attr xrf 63140 -attr oid 330 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#122.itm}
+load net {ACC1:acc#454.itm(0)} -attr vt d
+load net {ACC1:acc#454.itm(1)} -attr vt d
+load net {ACC1:acc#454.itm(2)} -attr vt d
+load net {ACC1:acc#454.itm(3)} -attr vt d
+load netBundle {ACC1:acc#454.itm} 4 {ACC1:acc#454.itm(0)} {ACC1:acc#454.itm(1)} {ACC1:acc#454.itm(2)} {ACC1:acc#454.itm(3)} -attr xrf 63141 -attr oid 331 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#454.itm}
+load net {exs#59.itm(0)} -attr vt d
+load net {exs#59.itm(1)} -attr vt d
+load net {exs#59.itm(2)} -attr vt d
+load netBundle {exs#59.itm} 3 {exs#59.itm(0)} {exs#59.itm(1)} {exs#59.itm(2)} -attr xrf 63142 -attr oid 332 -attr vt d -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {conc#917.itm(0)} -attr vt d
+load net {conc#917.itm(1)} -attr vt d
+load netBundle {conc#917.itm} 2 {conc#917.itm(0)} {conc#917.itm(1)} -attr xrf 63143 -attr oid 333 -attr vt d -attr @path {/sobel/sobel:core/conc#917.itm}
+load net {ACC1:exs#1505.itm(0)} -attr vt d
+load net {ACC1:exs#1505.itm(1)} -attr vt d
+load net {ACC1:exs#1505.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1505.itm} 3 {ACC1:exs#1505.itm(0)} {ACC1:exs#1505.itm(1)} {ACC1:exs#1505.itm(2)} -attr xrf 63144 -attr oid 334 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1505.itm}
+load net {ACC1:conc#1367.itm(0)} -attr vt d
+load net {ACC1:conc#1367.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1367.itm} 2 {ACC1:conc#1367.itm(0)} {ACC1:conc#1367.itm(1)} -attr xrf 63145 -attr oid 335 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1367.itm}
+load net {ACC1:slc#121.itm(0)} -attr vt d
+load net {ACC1:slc#121.itm(1)} -attr vt d
+load net {ACC1:slc#121.itm(2)} -attr vt d
+load netBundle {ACC1:slc#121.itm} 3 {ACC1:slc#121.itm(0)} {ACC1:slc#121.itm(1)} {ACC1:slc#121.itm(2)} -attr xrf 63146 -attr oid 336 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#121.itm}
+load net {ACC1:acc#453.itm(0)} -attr vt d
+load net {ACC1:acc#453.itm(1)} -attr vt d
+load net {ACC1:acc#453.itm(2)} -attr vt d
+load net {ACC1:acc#453.itm(3)} -attr vt d
+load netBundle {ACC1:acc#453.itm} 4 {ACC1:acc#453.itm(0)} {ACC1:acc#453.itm(1)} {ACC1:acc#453.itm(2)} {ACC1:acc#453.itm(3)} -attr xrf 63147 -attr oid 337 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#453.itm}
+load net {exs#60.itm(0)} -attr vt d
+load net {exs#60.itm(1)} -attr vt d
+load net {exs#60.itm(2)} -attr vt d
+load netBundle {exs#60.itm} 3 {exs#60.itm(0)} {exs#60.itm(1)} {exs#60.itm(2)} -attr xrf 63148 -attr oid 338 -attr vt d -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {conc#918.itm(0)} -attr vt d
+load net {conc#918.itm(1)} -attr vt d
+load netBundle {conc#918.itm} 2 {conc#918.itm(0)} {conc#918.itm(1)} -attr xrf 63149 -attr oid 339 -attr vt d -attr @path {/sobel/sobel:core/conc#918.itm}
+load net {ACC1:exs#1507.itm(0)} -attr vt d
+load net {ACC1:exs#1507.itm(1)} -attr vt d
+load net {ACC1:exs#1507.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1507.itm} 3 {ACC1:exs#1507.itm(0)} {ACC1:exs#1507.itm(1)} {ACC1:exs#1507.itm(2)} -attr xrf 63150 -attr oid 340 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1507.itm}
+load net {ACC1:conc#1365.itm(0)} -attr vt d
+load net {ACC1:conc#1365.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1365.itm} 2 {ACC1:conc#1365.itm(0)} {ACC1:conc#1365.itm(1)} -attr xrf 63151 -attr oid 341 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1365.itm}
+load net {ACC1:acc#537.itm(0)} -attr vt d
+load net {ACC1:acc#537.itm(1)} -attr vt d
+load net {ACC1:acc#537.itm(2)} -attr vt d
+load net {ACC1:acc#537.itm(3)} -attr vt d
+load netBundle {ACC1:acc#537.itm} 4 {ACC1:acc#537.itm(0)} {ACC1:acc#537.itm(1)} {ACC1:acc#537.itm(2)} {ACC1:acc#537.itm(3)} -attr xrf 63152 -attr oid 342 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:slc#120.itm(0)} -attr vt d
+load net {ACC1:slc#120.itm(1)} -attr vt d
+load net {ACC1:slc#120.itm(2)} -attr vt d
+load netBundle {ACC1:slc#120.itm} 3 {ACC1:slc#120.itm(0)} {ACC1:slc#120.itm(1)} {ACC1:slc#120.itm(2)} -attr xrf 63153 -attr oid 343 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#120.itm}
+load net {ACC1:acc#452.itm(0)} -attr vt d
+load net {ACC1:acc#452.itm(1)} -attr vt d
+load net {ACC1:acc#452.itm(2)} -attr vt d
+load net {ACC1:acc#452.itm(3)} -attr vt d
+load netBundle {ACC1:acc#452.itm} 4 {ACC1:acc#452.itm(0)} {ACC1:acc#452.itm(1)} {ACC1:acc#452.itm(2)} {ACC1:acc#452.itm(3)} -attr xrf 63154 -attr oid 344 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#452.itm}
+load net {exs#61.itm(0)} -attr vt d
+load net {exs#61.itm(1)} -attr vt d
+load net {exs#61.itm(2)} -attr vt d
+load netBundle {exs#61.itm} 3 {exs#61.itm(0)} {exs#61.itm(1)} {exs#61.itm(2)} -attr xrf 63155 -attr oid 345 -attr vt d -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {conc#919.itm(0)} -attr vt d
+load net {conc#919.itm(1)} -attr vt d
+load netBundle {conc#919.itm} 2 {conc#919.itm(0)} {conc#919.itm(1)} -attr xrf 63156 -attr oid 346 -attr vt d -attr @path {/sobel/sobel:core/conc#919.itm}
+load net {ACC1:exs#1509.itm(0)} -attr vt d
+load net {ACC1:exs#1509.itm(1)} -attr vt d
+load net {ACC1:exs#1509.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1509.itm} 3 {ACC1:exs#1509.itm(0)} {ACC1:exs#1509.itm(1)} {ACC1:exs#1509.itm(2)} -attr xrf 63157 -attr oid 347 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1509.itm}
+load net {ACC1:conc#1363.itm(0)} -attr vt d
+load net {ACC1:conc#1363.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1363.itm} 2 {ACC1:conc#1363.itm(0)} {ACC1:conc#1363.itm(1)} -attr xrf 63158 -attr oid 348 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1363.itm}
+load net {ACC1:slc#119.itm(0)} -attr vt d
+load net {ACC1:slc#119.itm(1)} -attr vt d
+load net {ACC1:slc#119.itm(2)} -attr vt d
+load netBundle {ACC1:slc#119.itm} 3 {ACC1:slc#119.itm(0)} {ACC1:slc#119.itm(1)} {ACC1:slc#119.itm(2)} -attr xrf 63159 -attr oid 349 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#119.itm}
+load net {ACC1:acc#451.itm(0)} -attr vt d
+load net {ACC1:acc#451.itm(1)} -attr vt d
+load net {ACC1:acc#451.itm(2)} -attr vt d
+load net {ACC1:acc#451.itm(3)} -attr vt d
+load netBundle {ACC1:acc#451.itm} 4 {ACC1:acc#451.itm(0)} {ACC1:acc#451.itm(1)} {ACC1:acc#451.itm(2)} {ACC1:acc#451.itm(3)} -attr xrf 63160 -attr oid 350 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#451.itm}
+load net {exs#62.itm(0)} -attr vt d
+load net {exs#62.itm(1)} -attr vt d
+load net {exs#62.itm(2)} -attr vt d
+load netBundle {exs#62.itm} 3 {exs#62.itm(0)} {exs#62.itm(1)} {exs#62.itm(2)} -attr xrf 63161 -attr oid 351 -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {conc#920.itm(0)} -attr vt d
+load net {conc#920.itm(1)} -attr vt d
+load netBundle {conc#920.itm} 2 {conc#920.itm(0)} {conc#920.itm(1)} -attr xrf 63162 -attr oid 352 -attr vt d -attr @path {/sobel/sobel:core/conc#920.itm}
+load net {ACC1:exs#1511.itm(0)} -attr vt d
+load net {ACC1:exs#1511.itm(1)} -attr vt d
+load net {ACC1:exs#1511.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1511.itm} 3 {ACC1:exs#1511.itm(0)} {ACC1:exs#1511.itm(1)} {ACC1:exs#1511.itm(2)} -attr xrf 63163 -attr oid 353 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1511.itm}
+load net {ACC1:conc#1361.itm(0)} -attr vt d
+load net {ACC1:conc#1361.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1361.itm} 2 {ACC1:conc#1361.itm(0)} {ACC1:conc#1361.itm(1)} -attr xrf 63164 -attr oid 354 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1361.itm}
+load net {ACC1:acc#606.itm(0)} -attr vt d
+load net {ACC1:acc#606.itm(1)} -attr vt d
+load net {ACC1:acc#606.itm(2)} -attr vt d
+load net {ACC1:acc#606.itm(3)} -attr vt d
+load net {ACC1:acc#606.itm(4)} -attr vt d
+load net {ACC1:acc#606.itm(5)} -attr vt d
+load netBundle {ACC1:acc#606.itm} 6 {ACC1:acc#606.itm(0)} {ACC1:acc#606.itm(1)} {ACC1:acc#606.itm(2)} {ACC1:acc#606.itm(3)} {ACC1:acc#606.itm(4)} {ACC1:acc#606.itm(5)} -attr xrf 63165 -attr oid 355 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#583.itm(0)} -attr vt d
+load net {ACC1:acc#583.itm(1)} -attr vt d
+load net {ACC1:acc#583.itm(2)} -attr vt d
+load net {ACC1:acc#583.itm(3)} -attr vt d
+load net {ACC1:acc#583.itm(4)} -attr vt d
+load netBundle {ACC1:acc#583.itm} 5 {ACC1:acc#583.itm(0)} {ACC1:acc#583.itm(1)} {ACC1:acc#583.itm(2)} {ACC1:acc#583.itm(3)} {ACC1:acc#583.itm(4)} -attr xrf 63166 -attr oid 356 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#536.itm(0)} -attr vt d
+load net {ACC1:acc#536.itm(1)} -attr vt d
+load net {ACC1:acc#536.itm(2)} -attr vt d
+load net {ACC1:acc#536.itm(3)} -attr vt d
+load netBundle {ACC1:acc#536.itm} 4 {ACC1:acc#536.itm(0)} {ACC1:acc#536.itm(1)} {ACC1:acc#536.itm(2)} {ACC1:acc#536.itm(3)} -attr xrf 63167 -attr oid 357 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:slc#118.itm(0)} -attr vt d
+load net {ACC1:slc#118.itm(1)} -attr vt d
+load net {ACC1:slc#118.itm(2)} -attr vt d
+load netBundle {ACC1:slc#118.itm} 3 {ACC1:slc#118.itm(0)} {ACC1:slc#118.itm(1)} {ACC1:slc#118.itm(2)} -attr xrf 63168 -attr oid 358 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#118.itm}
+load net {ACC1:acc#450.itm(0)} -attr vt d
+load net {ACC1:acc#450.itm(1)} -attr vt d
+load net {ACC1:acc#450.itm(2)} -attr vt d
+load net {ACC1:acc#450.itm(3)} -attr vt d
+load netBundle {ACC1:acc#450.itm} 4 {ACC1:acc#450.itm(0)} {ACC1:acc#450.itm(1)} {ACC1:acc#450.itm(2)} {ACC1:acc#450.itm(3)} -attr xrf 63169 -attr oid 359 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#450.itm}
+load net {exs#63.itm(0)} -attr vt d
+load net {exs#63.itm(1)} -attr vt d
+load net {exs#63.itm(2)} -attr vt d
+load netBundle {exs#63.itm} 3 {exs#63.itm(0)} {exs#63.itm(1)} {exs#63.itm(2)} -attr xrf 63170 -attr oid 360 -attr vt d -attr @path {/sobel/sobel:core/exs#63.itm}
+load net {conc#921.itm(0)} -attr vt d
+load net {conc#921.itm(1)} -attr vt d
+load netBundle {conc#921.itm} 2 {conc#921.itm(0)} {conc#921.itm(1)} -attr xrf 63171 -attr oid 361 -attr vt d -attr @path {/sobel/sobel:core/conc#921.itm}
+load net {ACC1:exs#1513.itm(0)} -attr vt d
+load net {ACC1:exs#1513.itm(1)} -attr vt d
+load net {ACC1:exs#1513.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1513.itm} 3 {ACC1:exs#1513.itm(0)} {ACC1:exs#1513.itm(1)} {ACC1:exs#1513.itm(2)} -attr xrf 63172 -attr oid 362 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1513.itm}
+load net {ACC1:conc#1359.itm(0)} -attr vt d
+load net {ACC1:conc#1359.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1359.itm} 2 {ACC1:conc#1359.itm(0)} {ACC1:conc#1359.itm(1)} -attr xrf 63173 -attr oid 363 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1359.itm}
+load net {ACC1:slc#117.itm(0)} -attr vt d
+load net {ACC1:slc#117.itm(1)} -attr vt d
+load net {ACC1:slc#117.itm(2)} -attr vt d
+load netBundle {ACC1:slc#117.itm} 3 {ACC1:slc#117.itm(0)} {ACC1:slc#117.itm(1)} {ACC1:slc#117.itm(2)} -attr xrf 63174 -attr oid 364 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#117.itm}
+load net {ACC1:acc#449.itm(0)} -attr vt d
+load net {ACC1:acc#449.itm(1)} -attr vt d
+load net {ACC1:acc#449.itm(2)} -attr vt d
+load net {ACC1:acc#449.itm(3)} -attr vt d
+load netBundle {ACC1:acc#449.itm} 4 {ACC1:acc#449.itm(0)} {ACC1:acc#449.itm(1)} {ACC1:acc#449.itm(2)} {ACC1:acc#449.itm(3)} -attr xrf 63175 -attr oid 365 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#449.itm}
+load net {exs#64.itm(0)} -attr vt d
+load net {exs#64.itm(1)} -attr vt d
+load net {exs#64.itm(2)} -attr vt d
+load netBundle {exs#64.itm} 3 {exs#64.itm(0)} {exs#64.itm(1)} {exs#64.itm(2)} -attr xrf 63176 -attr oid 366 -attr vt d -attr @path {/sobel/sobel:core/exs#64.itm}
+load net {conc#922.itm(0)} -attr vt d
+load net {conc#922.itm(1)} -attr vt d
+load netBundle {conc#922.itm} 2 {conc#922.itm(0)} {conc#922.itm(1)} -attr xrf 63177 -attr oid 367 -attr vt d -attr @path {/sobel/sobel:core/conc#922.itm}
+load net {ACC1:exs#1515.itm(0)} -attr vt d
+load net {ACC1:exs#1515.itm(1)} -attr vt d
+load net {ACC1:exs#1515.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1515.itm} 3 {ACC1:exs#1515.itm(0)} {ACC1:exs#1515.itm(1)} {ACC1:exs#1515.itm(2)} -attr xrf 63178 -attr oid 368 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1515.itm}
+load net {ACC1:conc#1357.itm(0)} -attr vt d
+load net {ACC1:conc#1357.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1357.itm} 2 {ACC1:conc#1357.itm(0)} {ACC1:conc#1357.itm(1)} -attr xrf 63179 -attr oid 369 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1357.itm}
+load net {ACC1:acc#535.itm(0)} -attr vt d
+load net {ACC1:acc#535.itm(1)} -attr vt d
+load net {ACC1:acc#535.itm(2)} -attr vt d
+load net {ACC1:acc#535.itm(3)} -attr vt d
+load netBundle {ACC1:acc#535.itm} 4 {ACC1:acc#535.itm(0)} {ACC1:acc#535.itm(1)} {ACC1:acc#535.itm(2)} {ACC1:acc#535.itm(3)} -attr xrf 63180 -attr oid 370 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:slc#116.itm(0)} -attr vt d
+load net {ACC1:slc#116.itm(1)} -attr vt d
+load net {ACC1:slc#116.itm(2)} -attr vt d
+load netBundle {ACC1:slc#116.itm} 3 {ACC1:slc#116.itm(0)} {ACC1:slc#116.itm(1)} {ACC1:slc#116.itm(2)} -attr xrf 63181 -attr oid 371 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#116.itm}
+load net {ACC1:acc#448.itm(0)} -attr vt d
+load net {ACC1:acc#448.itm(1)} -attr vt d
+load net {ACC1:acc#448.itm(2)} -attr vt d
+load net {ACC1:acc#448.itm(3)} -attr vt d
+load netBundle {ACC1:acc#448.itm} 4 {ACC1:acc#448.itm(0)} {ACC1:acc#448.itm(1)} {ACC1:acc#448.itm(2)} {ACC1:acc#448.itm(3)} -attr xrf 63182 -attr oid 372 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#448.itm}
+load net {exs#65.itm(0)} -attr vt d
+load net {exs#65.itm(1)} -attr vt d
+load net {exs#65.itm(2)} -attr vt d
+load netBundle {exs#65.itm} 3 {exs#65.itm(0)} {exs#65.itm(1)} {exs#65.itm(2)} -attr xrf 63183 -attr oid 373 -attr vt d -attr @path {/sobel/sobel:core/exs#65.itm}
+load net {conc#923.itm(0)} -attr vt d
+load net {conc#923.itm(1)} -attr vt d
+load netBundle {conc#923.itm} 2 {conc#923.itm(0)} {conc#923.itm(1)} -attr xrf 63184 -attr oid 374 -attr vt d -attr @path {/sobel/sobel:core/conc#923.itm}
+load net {ACC1:exs#1517.itm(0)} -attr vt d
+load net {ACC1:exs#1517.itm(1)} -attr vt d
+load net {ACC1:exs#1517.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1517.itm} 3 {ACC1:exs#1517.itm(0)} {ACC1:exs#1517.itm(1)} {ACC1:exs#1517.itm(2)} -attr xrf 63185 -attr oid 375 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1517.itm}
+load net {ACC1:conc#1355.itm(0)} -attr vt d
+load net {ACC1:conc#1355.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1355.itm} 2 {ACC1:conc#1355.itm(0)} {ACC1:conc#1355.itm(1)} -attr xrf 63186 -attr oid 376 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1355.itm}
+load net {ACC1:slc#115.itm(0)} -attr vt d
+load net {ACC1:slc#115.itm(1)} -attr vt d
+load net {ACC1:slc#115.itm(2)} -attr vt d
+load netBundle {ACC1:slc#115.itm} 3 {ACC1:slc#115.itm(0)} {ACC1:slc#115.itm(1)} {ACC1:slc#115.itm(2)} -attr xrf 63187 -attr oid 377 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#115.itm}
+load net {ACC1:acc#447.itm(0)} -attr vt d
+load net {ACC1:acc#447.itm(1)} -attr vt d
+load net {ACC1:acc#447.itm(2)} -attr vt d
+load net {ACC1:acc#447.itm(3)} -attr vt d
+load netBundle {ACC1:acc#447.itm} 4 {ACC1:acc#447.itm(0)} {ACC1:acc#447.itm(1)} {ACC1:acc#447.itm(2)} {ACC1:acc#447.itm(3)} -attr xrf 63188 -attr oid 378 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#447.itm}
+load net {exs#92.itm(0)} -attr vt d
+load net {exs#92.itm(1)} -attr vt d
+load net {exs#92.itm(2)} -attr vt d
+load netBundle {exs#92.itm} 3 {exs#92.itm(0)} {exs#92.itm(1)} {exs#92.itm(2)} -attr xrf 63189 -attr oid 379 -attr vt d -attr @path {/sobel/sobel:core/exs#92.itm}
+load net {conc#924.itm(0)} -attr vt d
+load net {conc#924.itm(1)} -attr vt d
+load netBundle {conc#924.itm} 2 {conc#924.itm(0)} {conc#924.itm(1)} -attr xrf 63190 -attr oid 380 -attr vt d -attr @path {/sobel/sobel:core/conc#924.itm}
+load net {ACC1:exs#1519.itm(0)} -attr vt d
+load net {ACC1:exs#1519.itm(1)} -attr vt d
+load net {ACC1:exs#1519.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1519.itm} 3 {ACC1:exs#1519.itm(0)} {ACC1:exs#1519.itm(1)} {ACC1:exs#1519.itm(2)} -attr xrf 63191 -attr oid 381 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1519.itm}
+load net {ACC1:conc#1353.itm(0)} -attr vt d
+load net {ACC1:conc#1353.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1353.itm} 2 {ACC1:conc#1353.itm(0)} {ACC1:conc#1353.itm(1)} -attr xrf 63192 -attr oid 382 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1353.itm}
+load net {ACC1:acc#582.itm(0)} -attr vt d
+load net {ACC1:acc#582.itm(1)} -attr vt d
+load net {ACC1:acc#582.itm(2)} -attr vt d
+load net {ACC1:acc#582.itm(3)} -attr vt d
+load net {ACC1:acc#582.itm(4)} -attr vt d
+load netBundle {ACC1:acc#582.itm} 5 {ACC1:acc#582.itm(0)} {ACC1:acc#582.itm(1)} {ACC1:acc#582.itm(2)} {ACC1:acc#582.itm(3)} {ACC1:acc#582.itm(4)} -attr xrf 63193 -attr oid 383 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#534.itm(0)} -attr vt d
+load net {ACC1:acc#534.itm(1)} -attr vt d
+load net {ACC1:acc#534.itm(2)} -attr vt d
+load net {ACC1:acc#534.itm(3)} -attr vt d
+load netBundle {ACC1:acc#534.itm} 4 {ACC1:acc#534.itm(0)} {ACC1:acc#534.itm(1)} {ACC1:acc#534.itm(2)} {ACC1:acc#534.itm(3)} -attr xrf 63194 -attr oid 384 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:slc#114.itm(0)} -attr vt d
+load net {ACC1:slc#114.itm(1)} -attr vt d
+load net {ACC1:slc#114.itm(2)} -attr vt d
+load netBundle {ACC1:slc#114.itm} 3 {ACC1:slc#114.itm(0)} {ACC1:slc#114.itm(1)} {ACC1:slc#114.itm(2)} -attr xrf 63195 -attr oid 385 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#114.itm}
+load net {ACC1:acc#446.itm(0)} -attr vt d
+load net {ACC1:acc#446.itm(1)} -attr vt d
+load net {ACC1:acc#446.itm(2)} -attr vt d
+load net {ACC1:acc#446.itm(3)} -attr vt d
+load netBundle {ACC1:acc#446.itm} 4 {ACC1:acc#446.itm(0)} {ACC1:acc#446.itm(1)} {ACC1:acc#446.itm(2)} {ACC1:acc#446.itm(3)} -attr xrf 63196 -attr oid 386 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#446.itm}
+load net {exs#66.itm(0)} -attr vt d
+load net {exs#66.itm(1)} -attr vt d
+load net {exs#66.itm(2)} -attr vt d
+load netBundle {exs#66.itm} 3 {exs#66.itm(0)} {exs#66.itm(1)} {exs#66.itm(2)} -attr xrf 63197 -attr oid 387 -attr vt d -attr @path {/sobel/sobel:core/exs#66.itm}
+load net {conc#926.itm(0)} -attr vt d
+load net {conc#926.itm(1)} -attr vt d
+load netBundle {conc#926.itm} 2 {conc#926.itm(0)} {conc#926.itm(1)} -attr xrf 63198 -attr oid 388 -attr vt d -attr @path {/sobel/sobel:core/conc#926.itm}
+load net {ACC1:exs#1521.itm(0)} -attr vt d
+load net {ACC1:exs#1521.itm(1)} -attr vt d
+load net {ACC1:exs#1521.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1521.itm} 3 {ACC1:exs#1521.itm(0)} {ACC1:exs#1521.itm(1)} {ACC1:exs#1521.itm(2)} -attr xrf 63199 -attr oid 389 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1521.itm}
+load net {ACC1:conc#1351.itm(0)} -attr vt d
+load net {ACC1:conc#1351.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1351.itm} 2 {ACC1:conc#1351.itm(0)} {ACC1:conc#1351.itm(1)} -attr xrf 63200 -attr oid 390 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1351.itm}
+load net {ACC1:slc#113.itm(0)} -attr vt d
+load net {ACC1:slc#113.itm(1)} -attr vt d
+load net {ACC1:slc#113.itm(2)} -attr vt d
+load netBundle {ACC1:slc#113.itm} 3 {ACC1:slc#113.itm(0)} {ACC1:slc#113.itm(1)} {ACC1:slc#113.itm(2)} -attr xrf 63201 -attr oid 391 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#113.itm}
+load net {ACC1:acc#445.itm(0)} -attr vt d
+load net {ACC1:acc#445.itm(1)} -attr vt d
+load net {ACC1:acc#445.itm(2)} -attr vt d
+load net {ACC1:acc#445.itm(3)} -attr vt d
+load netBundle {ACC1:acc#445.itm} 4 {ACC1:acc#445.itm(0)} {ACC1:acc#445.itm(1)} {ACC1:acc#445.itm(2)} {ACC1:acc#445.itm(3)} -attr xrf 63202 -attr oid 392 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#445.itm}
+load net {exs#93.itm(0)} -attr vt d
+load net {exs#93.itm(1)} -attr vt d
+load net {exs#93.itm(2)} -attr vt d
+load netBundle {exs#93.itm} 3 {exs#93.itm(0)} {exs#93.itm(1)} {exs#93.itm(2)} -attr xrf 63203 -attr oid 393 -attr vt d -attr @path {/sobel/sobel:core/exs#93.itm}
+load net {conc#927.itm(0)} -attr vt d
+load net {conc#927.itm(1)} -attr vt d
+load netBundle {conc#927.itm} 2 {conc#927.itm(0)} {conc#927.itm(1)} -attr xrf 63204 -attr oid 394 -attr vt d -attr @path {/sobel/sobel:core/conc#927.itm}
+load net {ACC1:exs#1523.itm(0)} -attr vt d
+load net {ACC1:exs#1523.itm(1)} -attr vt d
+load net {ACC1:exs#1523.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1523.itm} 3 {ACC1:exs#1523.itm(0)} {ACC1:exs#1523.itm(1)} {ACC1:exs#1523.itm(2)} -attr xrf 63205 -attr oid 395 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1523.itm}
+load net {ACC1:conc#1349.itm(0)} -attr vt d
+load net {ACC1:conc#1349.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1349.itm} 2 {ACC1:conc#1349.itm(0)} {ACC1:conc#1349.itm(1)} -attr xrf 63206 -attr oid 396 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1349.itm}
+load net {ACC1:acc#533.itm(0)} -attr vt d
+load net {ACC1:acc#533.itm(1)} -attr vt d
+load net {ACC1:acc#533.itm(2)} -attr vt d
+load net {ACC1:acc#533.itm(3)} -attr vt d
+load netBundle {ACC1:acc#533.itm} 4 {ACC1:acc#533.itm(0)} {ACC1:acc#533.itm(1)} {ACC1:acc#533.itm(2)} {ACC1:acc#533.itm(3)} -attr xrf 63207 -attr oid 397 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:slc#112.itm(0)} -attr vt d
+load net {ACC1:slc#112.itm(1)} -attr vt d
+load net {ACC1:slc#112.itm(2)} -attr vt d
+load netBundle {ACC1:slc#112.itm} 3 {ACC1:slc#112.itm(0)} {ACC1:slc#112.itm(1)} {ACC1:slc#112.itm(2)} -attr xrf 63208 -attr oid 398 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#112.itm}
+load net {ACC1:acc#444.itm(0)} -attr vt d
+load net {ACC1:acc#444.itm(1)} -attr vt d
+load net {ACC1:acc#444.itm(2)} -attr vt d
+load net {ACC1:acc#444.itm(3)} -attr vt d
+load netBundle {ACC1:acc#444.itm} 4 {ACC1:acc#444.itm(0)} {ACC1:acc#444.itm(1)} {ACC1:acc#444.itm(2)} {ACC1:acc#444.itm(3)} -attr xrf 63209 -attr oid 399 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#444.itm}
+load net {exs#67.itm(0)} -attr vt d
+load net {exs#67.itm(1)} -attr vt d
+load net {exs#67.itm(2)} -attr vt d
+load netBundle {exs#67.itm} 3 {exs#67.itm(0)} {exs#67.itm(1)} {exs#67.itm(2)} -attr xrf 63210 -attr oid 400 -attr vt d -attr @path {/sobel/sobel:core/exs#67.itm}
+load net {conc#929.itm(0)} -attr vt d
+load net {conc#929.itm(1)} -attr vt d
+load netBundle {conc#929.itm} 2 {conc#929.itm(0)} {conc#929.itm(1)} -attr xrf 63211 -attr oid 401 -attr vt d -attr @path {/sobel/sobel:core/conc#929.itm}
+load net {ACC1:exs#1525.itm(0)} -attr vt d
+load net {ACC1:exs#1525.itm(1)} -attr vt d
+load net {ACC1:exs#1525.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1525.itm} 3 {ACC1:exs#1525.itm(0)} {ACC1:exs#1525.itm(1)} {ACC1:exs#1525.itm(2)} -attr xrf 63212 -attr oid 402 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1525.itm}
+load net {ACC1:conc#1347.itm(0)} -attr vt d
+load net {ACC1:conc#1347.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1347.itm} 2 {ACC1:conc#1347.itm(0)} {ACC1:conc#1347.itm(1)} -attr xrf 63213 -attr oid 403 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1347.itm}
+load net {ACC1:slc#110.itm(0)} -attr vt d
+load net {ACC1:slc#110.itm(1)} -attr vt d
+load net {ACC1:slc#110.itm(2)} -attr vt d
+load netBundle {ACC1:slc#110.itm} 3 {ACC1:slc#110.itm(0)} {ACC1:slc#110.itm(1)} {ACC1:slc#110.itm(2)} -attr xrf 63214 -attr oid 404 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#110.itm}
+load net {ACC1:acc#442.itm(0)} -attr vt d
+load net {ACC1:acc#442.itm(1)} -attr vt d
+load net {ACC1:acc#442.itm(2)} -attr vt d
+load net {ACC1:acc#442.itm(3)} -attr vt d
+load netBundle {ACC1:acc#442.itm} 4 {ACC1:acc#442.itm(0)} {ACC1:acc#442.itm(1)} {ACC1:acc#442.itm(2)} {ACC1:acc#442.itm(3)} -attr xrf 63215 -attr oid 405 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#442.itm}
+load net {exs#68.itm(0)} -attr vt d
+load net {exs#68.itm(1)} -attr vt d
+load net {exs#68.itm(2)} -attr vt d
+load netBundle {exs#68.itm} 3 {exs#68.itm(0)} {exs#68.itm(1)} {exs#68.itm(2)} -attr xrf 63216 -attr oid 406 -attr vt d -attr @path {/sobel/sobel:core/exs#68.itm}
+load net {conc#930.itm(0)} -attr vt d
+load net {conc#930.itm(1)} -attr vt d
+load netBundle {conc#930.itm} 2 {conc#930.itm(0)} {conc#930.itm(1)} -attr xrf 63217 -attr oid 407 -attr vt d -attr @path {/sobel/sobel:core/conc#930.itm}
+load net {ACC1:exs#1527.itm(0)} -attr vt d
+load net {ACC1:exs#1527.itm(1)} -attr vt d
+load net {ACC1:exs#1527.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1527.itm} 3 {ACC1:exs#1527.itm(0)} {ACC1:exs#1527.itm(1)} {ACC1:exs#1527.itm(2)} -attr xrf 63218 -attr oid 408 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1527.itm}
+load net {ACC1:conc#1343.itm(0)} -attr vt d
+load net {ACC1:conc#1343.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1343.itm} 2 {ACC1:conc#1343.itm(0)} {ACC1:conc#1343.itm(1)} -attr xrf 63219 -attr oid 409 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1343.itm}
+load net {ACC1:acc#622.itm(0)} -attr vt d
+load net {ACC1:acc#622.itm(1)} -attr vt d
+load net {ACC1:acc#622.itm(2)} -attr vt d
+load net {ACC1:acc#622.itm(3)} -attr vt d
+load net {ACC1:acc#622.itm(4)} -attr vt d
+load net {ACC1:acc#622.itm(5)} -attr vt d
+load net {ACC1:acc#622.itm(6)} -attr vt d
+load netBundle {ACC1:acc#622.itm} 7 {ACC1:acc#622.itm(0)} {ACC1:acc#622.itm(1)} {ACC1:acc#622.itm(2)} {ACC1:acc#622.itm(3)} {ACC1:acc#622.itm(4)} {ACC1:acc#622.itm(5)} {ACC1:acc#622.itm(6)} -attr xrf 63220 -attr oid 410 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#605.itm(0)} -attr vt d
+load net {ACC1:acc#605.itm(1)} -attr vt d
+load net {ACC1:acc#605.itm(2)} -attr vt d
+load net {ACC1:acc#605.itm(3)} -attr vt d
+load net {ACC1:acc#605.itm(4)} -attr vt d
+load net {ACC1:acc#605.itm(5)} -attr vt d
+load netBundle {ACC1:acc#605.itm} 6 {ACC1:acc#605.itm(0)} {ACC1:acc#605.itm(1)} {ACC1:acc#605.itm(2)} {ACC1:acc#605.itm(3)} {ACC1:acc#605.itm(4)} {ACC1:acc#605.itm(5)} -attr xrf 63221 -attr oid 411 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#581.itm(0)} -attr vt d
+load net {ACC1:acc#581.itm(1)} -attr vt d
+load net {ACC1:acc#581.itm(2)} -attr vt d
+load net {ACC1:acc#581.itm(3)} -attr vt d
+load net {ACC1:acc#581.itm(4)} -attr vt d
+load netBundle {ACC1:acc#581.itm} 5 {ACC1:acc#581.itm(0)} {ACC1:acc#581.itm(1)} {ACC1:acc#581.itm(2)} {ACC1:acc#581.itm(3)} {ACC1:acc#581.itm(4)} -attr xrf 63222 -attr oid 412 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#532.itm(0)} -attr vt d
+load net {ACC1:acc#532.itm(1)} -attr vt d
+load net {ACC1:acc#532.itm(2)} -attr vt d
+load net {ACC1:acc#532.itm(3)} -attr vt d
+load netBundle {ACC1:acc#532.itm} 4 {ACC1:acc#532.itm(0)} {ACC1:acc#532.itm(1)} {ACC1:acc#532.itm(2)} {ACC1:acc#532.itm(3)} -attr xrf 63223 -attr oid 413 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:slc#109.itm(0)} -attr vt d
+load net {ACC1:slc#109.itm(1)} -attr vt d
+load net {ACC1:slc#109.itm(2)} -attr vt d
+load netBundle {ACC1:slc#109.itm} 3 {ACC1:slc#109.itm(0)} {ACC1:slc#109.itm(1)} {ACC1:slc#109.itm(2)} -attr xrf 63224 -attr oid 414 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#109.itm}
+load net {ACC1:acc#441.itm(0)} -attr vt d
+load net {ACC1:acc#441.itm(1)} -attr vt d
+load net {ACC1:acc#441.itm(2)} -attr vt d
+load net {ACC1:acc#441.itm(3)} -attr vt d
+load netBundle {ACC1:acc#441.itm} 4 {ACC1:acc#441.itm(0)} {ACC1:acc#441.itm(1)} {ACC1:acc#441.itm(2)} {ACC1:acc#441.itm(3)} -attr xrf 63225 -attr oid 415 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#441.itm}
+load net {exs#69.itm(0)} -attr vt d
+load net {exs#69.itm(1)} -attr vt d
+load net {exs#69.itm(2)} -attr vt d
+load netBundle {exs#69.itm} 3 {exs#69.itm(0)} {exs#69.itm(1)} {exs#69.itm(2)} -attr xrf 63226 -attr oid 416 -attr vt d -attr @path {/sobel/sobel:core/exs#69.itm}
+load net {conc#931.itm(0)} -attr vt d
+load net {conc#931.itm(1)} -attr vt d
+load netBundle {conc#931.itm} 2 {conc#931.itm(0)} {conc#931.itm(1)} -attr xrf 63227 -attr oid 417 -attr vt d -attr @path {/sobel/sobel:core/conc#931.itm}
+load net {ACC1:exs#1529.itm(0)} -attr vt d
+load net {ACC1:exs#1529.itm(1)} -attr vt d
+load net {ACC1:exs#1529.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1529.itm} 3 {ACC1:exs#1529.itm(0)} {ACC1:exs#1529.itm(1)} {ACC1:exs#1529.itm(2)} -attr xrf 63228 -attr oid 418 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1529.itm}
+load net {ACC1:conc#1341.itm(0)} -attr vt d
+load net {ACC1:conc#1341.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1341.itm} 2 {ACC1:conc#1341.itm(0)} {ACC1:conc#1341.itm(1)} -attr xrf 63229 -attr oid 419 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1341.itm}
+load net {ACC1:slc#108.itm(0)} -attr vt d
+load net {ACC1:slc#108.itm(1)} -attr vt d
+load net {ACC1:slc#108.itm(2)} -attr vt d
+load netBundle {ACC1:slc#108.itm} 3 {ACC1:slc#108.itm(0)} {ACC1:slc#108.itm(1)} {ACC1:slc#108.itm(2)} -attr xrf 63230 -attr oid 420 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#108.itm}
+load net {ACC1:acc#440.itm(0)} -attr vt d
+load net {ACC1:acc#440.itm(1)} -attr vt d
+load net {ACC1:acc#440.itm(2)} -attr vt d
+load net {ACC1:acc#440.itm(3)} -attr vt d
+load netBundle {ACC1:acc#440.itm} 4 {ACC1:acc#440.itm(0)} {ACC1:acc#440.itm(1)} {ACC1:acc#440.itm(2)} {ACC1:acc#440.itm(3)} -attr xrf 63231 -attr oid 421 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#440.itm}
+load net {exs#70.itm(0)} -attr vt d
+load net {exs#70.itm(1)} -attr vt d
+load net {exs#70.itm(2)} -attr vt d
+load netBundle {exs#70.itm} 3 {exs#70.itm(0)} {exs#70.itm(1)} {exs#70.itm(2)} -attr xrf 63232 -attr oid 422 -attr vt d -attr @path {/sobel/sobel:core/exs#70.itm}
+load net {conc#932.itm(0)} -attr vt d
+load net {conc#932.itm(1)} -attr vt d
+load netBundle {conc#932.itm} 2 {conc#932.itm(0)} {conc#932.itm(1)} -attr xrf 63233 -attr oid 423 -attr vt d -attr @path {/sobel/sobel:core/conc#932.itm}
+load net {ACC1:exs#1531.itm(0)} -attr vt d
+load net {ACC1:exs#1531.itm(1)} -attr vt d
+load net {ACC1:exs#1531.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1531.itm} 3 {ACC1:exs#1531.itm(0)} {ACC1:exs#1531.itm(1)} {ACC1:exs#1531.itm(2)} -attr xrf 63234 -attr oid 424 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1531.itm}
+load net {ACC1:conc#1339.itm(0)} -attr vt d
+load net {ACC1:conc#1339.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1339.itm} 2 {ACC1:conc#1339.itm(0)} {ACC1:conc#1339.itm(1)} -attr xrf 63235 -attr oid 425 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1339.itm}
+load net {ACC1:acc#531.itm(0)} -attr vt d
+load net {ACC1:acc#531.itm(1)} -attr vt d
+load net {ACC1:acc#531.itm(2)} -attr vt d
+load net {ACC1:acc#531.itm(3)} -attr vt d
+load netBundle {ACC1:acc#531.itm} 4 {ACC1:acc#531.itm(0)} {ACC1:acc#531.itm(1)} {ACC1:acc#531.itm(2)} {ACC1:acc#531.itm(3)} -attr xrf 63236 -attr oid 426 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:slc#107.itm(0)} -attr vt d
+load net {ACC1:slc#107.itm(1)} -attr vt d
+load net {ACC1:slc#107.itm(2)} -attr vt d
+load netBundle {ACC1:slc#107.itm} 3 {ACC1:slc#107.itm(0)} {ACC1:slc#107.itm(1)} {ACC1:slc#107.itm(2)} -attr xrf 63237 -attr oid 427 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#107.itm}
+load net {ACC1:acc#439.itm(0)} -attr vt d
+load net {ACC1:acc#439.itm(1)} -attr vt d
+load net {ACC1:acc#439.itm(2)} -attr vt d
+load net {ACC1:acc#439.itm(3)} -attr vt d
+load netBundle {ACC1:acc#439.itm} 4 {ACC1:acc#439.itm(0)} {ACC1:acc#439.itm(1)} {ACC1:acc#439.itm(2)} {ACC1:acc#439.itm(3)} -attr xrf 63238 -attr oid 428 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#439.itm}
+load net {exs#71.itm(0)} -attr vt d
+load net {exs#71.itm(1)} -attr vt d
+load net {exs#71.itm(2)} -attr vt d
+load netBundle {exs#71.itm} 3 {exs#71.itm(0)} {exs#71.itm(1)} {exs#71.itm(2)} -attr xrf 63239 -attr oid 429 -attr vt d -attr @path {/sobel/sobel:core/exs#71.itm}
+load net {conc#933.itm(0)} -attr vt d
+load net {conc#933.itm(1)} -attr vt d
+load netBundle {conc#933.itm} 2 {conc#933.itm(0)} {conc#933.itm(1)} -attr xrf 63240 -attr oid 430 -attr vt d -attr @path {/sobel/sobel:core/conc#933.itm}
+load net {ACC1:exs#1533.itm(0)} -attr vt d
+load net {ACC1:exs#1533.itm(1)} -attr vt d
+load net {ACC1:exs#1533.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1533.itm} 3 {ACC1:exs#1533.itm(0)} {ACC1:exs#1533.itm(1)} {ACC1:exs#1533.itm(2)} -attr xrf 63241 -attr oid 431 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1533.itm}
+load net {ACC1:conc#1337.itm(0)} -attr vt d
+load net {ACC1:conc#1337.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1337.itm} 2 {ACC1:conc#1337.itm(0)} {ACC1:conc#1337.itm(1)} -attr xrf 63242 -attr oid 432 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1337.itm}
+load net {ACC1:slc#106.itm(0)} -attr vt d
+load net {ACC1:slc#106.itm(1)} -attr vt d
+load net {ACC1:slc#106.itm(2)} -attr vt d
+load netBundle {ACC1:slc#106.itm} 3 {ACC1:slc#106.itm(0)} {ACC1:slc#106.itm(1)} {ACC1:slc#106.itm(2)} -attr xrf 63243 -attr oid 433 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#106.itm}
+load net {ACC1:acc#438.itm(0)} -attr vt d
+load net {ACC1:acc#438.itm(1)} -attr vt d
+load net {ACC1:acc#438.itm(2)} -attr vt d
+load net {ACC1:acc#438.itm(3)} -attr vt d
+load netBundle {ACC1:acc#438.itm} 4 {ACC1:acc#438.itm(0)} {ACC1:acc#438.itm(1)} {ACC1:acc#438.itm(2)} {ACC1:acc#438.itm(3)} -attr xrf 63244 -attr oid 434 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#438.itm}
+load net {exs#72.itm(0)} -attr vt d
+load net {exs#72.itm(1)} -attr vt d
+load net {exs#72.itm(2)} -attr vt d
+load netBundle {exs#72.itm} 3 {exs#72.itm(0)} {exs#72.itm(1)} {exs#72.itm(2)} -attr xrf 63245 -attr oid 435 -attr vt d -attr @path {/sobel/sobel:core/exs#72.itm}
+load net {conc#934.itm(0)} -attr vt d
+load net {conc#934.itm(1)} -attr vt d
+load netBundle {conc#934.itm} 2 {conc#934.itm(0)} {conc#934.itm(1)} -attr xrf 63246 -attr oid 436 -attr vt d -attr @path {/sobel/sobel:core/conc#934.itm}
+load net {ACC1:exs#1535.itm(0)} -attr vt d
+load net {ACC1:exs#1535.itm(1)} -attr vt d
+load net {ACC1:exs#1535.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1535.itm} 3 {ACC1:exs#1535.itm(0)} {ACC1:exs#1535.itm(1)} {ACC1:exs#1535.itm(2)} -attr xrf 63247 -attr oid 437 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1535.itm}
+load net {ACC1:conc#1335.itm(0)} -attr vt d
+load net {ACC1:conc#1335.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1335.itm} 2 {ACC1:conc#1335.itm(0)} {ACC1:conc#1335.itm(1)} -attr xrf 63248 -attr oid 438 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1335.itm}
+load net {ACC1:acc#580.itm(0)} -attr vt d
+load net {ACC1:acc#580.itm(1)} -attr vt d
+load net {ACC1:acc#580.itm(2)} -attr vt d
+load net {ACC1:acc#580.itm(3)} -attr vt d
+load net {ACC1:acc#580.itm(4)} -attr vt d
+load netBundle {ACC1:acc#580.itm} 5 {ACC1:acc#580.itm(0)} {ACC1:acc#580.itm(1)} {ACC1:acc#580.itm(2)} {ACC1:acc#580.itm(3)} {ACC1:acc#580.itm(4)} -attr xrf 63249 -attr oid 439 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#530.itm(0)} -attr vt d
+load net {ACC1:acc#530.itm(1)} -attr vt d
+load net {ACC1:acc#530.itm(2)} -attr vt d
+load net {ACC1:acc#530.itm(3)} -attr vt d
+load netBundle {ACC1:acc#530.itm} 4 {ACC1:acc#530.itm(0)} {ACC1:acc#530.itm(1)} {ACC1:acc#530.itm(2)} {ACC1:acc#530.itm(3)} -attr xrf 63250 -attr oid 440 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:slc#105.itm(0)} -attr vt d
+load net {ACC1:slc#105.itm(1)} -attr vt d
+load net {ACC1:slc#105.itm(2)} -attr vt d
+load netBundle {ACC1:slc#105.itm} 3 {ACC1:slc#105.itm(0)} {ACC1:slc#105.itm(1)} {ACC1:slc#105.itm(2)} -attr xrf 63251 -attr oid 441 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#105.itm}
+load net {ACC1:acc#437.itm(0)} -attr vt d
+load net {ACC1:acc#437.itm(1)} -attr vt d
+load net {ACC1:acc#437.itm(2)} -attr vt d
+load net {ACC1:acc#437.itm(3)} -attr vt d
+load netBundle {ACC1:acc#437.itm} 4 {ACC1:acc#437.itm(0)} {ACC1:acc#437.itm(1)} {ACC1:acc#437.itm(2)} {ACC1:acc#437.itm(3)} -attr xrf 63252 -attr oid 442 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#437.itm}
+load net {exs#73.itm(0)} -attr vt d
+load net {exs#73.itm(1)} -attr vt d
+load net {exs#73.itm(2)} -attr vt d
+load netBundle {exs#73.itm} 3 {exs#73.itm(0)} {exs#73.itm(1)} {exs#73.itm(2)} -attr xrf 63253 -attr oid 443 -attr vt d -attr @path {/sobel/sobel:core/exs#73.itm}
+load net {conc#935.itm(0)} -attr vt d
+load net {conc#935.itm(1)} -attr vt d
+load netBundle {conc#935.itm} 2 {conc#935.itm(0)} {conc#935.itm(1)} -attr xrf 63254 -attr oid 444 -attr vt d -attr @path {/sobel/sobel:core/conc#935.itm}
+load net {ACC1:exs#1537.itm(0)} -attr vt d
+load net {ACC1:exs#1537.itm(1)} -attr vt d
+load net {ACC1:exs#1537.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1537.itm} 3 {ACC1:exs#1537.itm(0)} {ACC1:exs#1537.itm(1)} {ACC1:exs#1537.itm(2)} -attr xrf 63255 -attr oid 445 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1537.itm}
+load net {ACC1:conc#1333.itm(0)} -attr vt d
+load net {ACC1:conc#1333.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1333.itm} 2 {ACC1:conc#1333.itm(0)} {ACC1:conc#1333.itm(1)} -attr xrf 63256 -attr oid 446 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1333.itm}
+load net {ACC1:slc#104.itm(0)} -attr vt d
+load net {ACC1:slc#104.itm(1)} -attr vt d
+load net {ACC1:slc#104.itm(2)} -attr vt d
+load netBundle {ACC1:slc#104.itm} 3 {ACC1:slc#104.itm(0)} {ACC1:slc#104.itm(1)} {ACC1:slc#104.itm(2)} -attr xrf 63257 -attr oid 447 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#104.itm}
+load net {ACC1:acc#436.itm(0)} -attr vt d
+load net {ACC1:acc#436.itm(1)} -attr vt d
+load net {ACC1:acc#436.itm(2)} -attr vt d
+load net {ACC1:acc#436.itm(3)} -attr vt d
+load netBundle {ACC1:acc#436.itm} 4 {ACC1:acc#436.itm(0)} {ACC1:acc#436.itm(1)} {ACC1:acc#436.itm(2)} {ACC1:acc#436.itm(3)} -attr xrf 63258 -attr oid 448 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#436.itm}
+load net {exs#74.itm(0)} -attr vt d
+load net {exs#74.itm(1)} -attr vt d
+load net {exs#74.itm(2)} -attr vt d
+load netBundle {exs#74.itm} 3 {exs#74.itm(0)} {exs#74.itm(1)} {exs#74.itm(2)} -attr xrf 63259 -attr oid 449 -attr vt d -attr @path {/sobel/sobel:core/exs#74.itm}
+load net {conc#936.itm(0)} -attr vt d
+load net {conc#936.itm(1)} -attr vt d
+load netBundle {conc#936.itm} 2 {conc#936.itm(0)} {conc#936.itm(1)} -attr xrf 63260 -attr oid 450 -attr vt d -attr @path {/sobel/sobel:core/conc#936.itm}
+load net {ACC1:exs#1539.itm(0)} -attr vt d
+load net {ACC1:exs#1539.itm(1)} -attr vt d
+load net {ACC1:exs#1539.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1539.itm} 3 {ACC1:exs#1539.itm(0)} {ACC1:exs#1539.itm(1)} {ACC1:exs#1539.itm(2)} -attr xrf 63261 -attr oid 451 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1539.itm}
+load net {ACC1:conc#1331.itm(0)} -attr vt d
+load net {ACC1:conc#1331.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1331.itm} 2 {ACC1:conc#1331.itm(0)} {ACC1:conc#1331.itm(1)} -attr xrf 63262 -attr oid 452 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1331.itm}
+load net {ACC1:acc#529.itm(0)} -attr vt d
+load net {ACC1:acc#529.itm(1)} -attr vt d
+load net {ACC1:acc#529.itm(2)} -attr vt d
+load net {ACC1:acc#529.itm(3)} -attr vt d
+load netBundle {ACC1:acc#529.itm} 4 {ACC1:acc#529.itm(0)} {ACC1:acc#529.itm(1)} {ACC1:acc#529.itm(2)} {ACC1:acc#529.itm(3)} -attr xrf 63263 -attr oid 453 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:slc#103.itm(0)} -attr vt d
+load net {ACC1:slc#103.itm(1)} -attr vt d
+load net {ACC1:slc#103.itm(2)} -attr vt d
+load netBundle {ACC1:slc#103.itm} 3 {ACC1:slc#103.itm(0)} {ACC1:slc#103.itm(1)} {ACC1:slc#103.itm(2)} -attr xrf 63264 -attr oid 454 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#103.itm}
+load net {ACC1:acc#435.itm(0)} -attr vt d
+load net {ACC1:acc#435.itm(1)} -attr vt d
+load net {ACC1:acc#435.itm(2)} -attr vt d
+load net {ACC1:acc#435.itm(3)} -attr vt d
+load netBundle {ACC1:acc#435.itm} 4 {ACC1:acc#435.itm(0)} {ACC1:acc#435.itm(1)} {ACC1:acc#435.itm(2)} {ACC1:acc#435.itm(3)} -attr xrf 63265 -attr oid 455 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#435.itm}
+load net {exs#75.itm(0)} -attr vt d
+load net {exs#75.itm(1)} -attr vt d
+load net {exs#75.itm(2)} -attr vt d
+load netBundle {exs#75.itm} 3 {exs#75.itm(0)} {exs#75.itm(1)} {exs#75.itm(2)} -attr xrf 63266 -attr oid 456 -attr vt d -attr @path {/sobel/sobel:core/exs#75.itm}
+load net {conc#937.itm(0)} -attr vt d
+load net {conc#937.itm(1)} -attr vt d
+load netBundle {conc#937.itm} 2 {conc#937.itm(0)} {conc#937.itm(1)} -attr xrf 63267 -attr oid 457 -attr vt d -attr @path {/sobel/sobel:core/conc#937.itm}
+load net {ACC1:exs#1541.itm(0)} -attr vt d
+load net {ACC1:exs#1541.itm(1)} -attr vt d
+load net {ACC1:exs#1541.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1541.itm} 3 {ACC1:exs#1541.itm(0)} {ACC1:exs#1541.itm(1)} {ACC1:exs#1541.itm(2)} -attr xrf 63268 -attr oid 458 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1541.itm}
+load net {ACC1:conc#1329.itm(0)} -attr vt d
+load net {ACC1:conc#1329.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1329.itm} 2 {ACC1:conc#1329.itm(0)} {ACC1:conc#1329.itm(1)} -attr xrf 63269 -attr oid 459 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1329.itm}
+load net {ACC1:slc#102.itm(0)} -attr vt d
+load net {ACC1:slc#102.itm(1)} -attr vt d
+load net {ACC1:slc#102.itm(2)} -attr vt d
+load netBundle {ACC1:slc#102.itm} 3 {ACC1:slc#102.itm(0)} {ACC1:slc#102.itm(1)} {ACC1:slc#102.itm(2)} -attr xrf 63270 -attr oid 460 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#102.itm}
+load net {ACC1:acc#434.itm(0)} -attr vt d
+load net {ACC1:acc#434.itm(1)} -attr vt d
+load net {ACC1:acc#434.itm(2)} -attr vt d
+load net {ACC1:acc#434.itm(3)} -attr vt d
+load netBundle {ACC1:acc#434.itm} 4 {ACC1:acc#434.itm(0)} {ACC1:acc#434.itm(1)} {ACC1:acc#434.itm(2)} {ACC1:acc#434.itm(3)} -attr xrf 63271 -attr oid 461 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#434.itm}
+load net {exs#76.itm(0)} -attr vt d
+load net {exs#76.itm(1)} -attr vt d
+load net {exs#76.itm(2)} -attr vt d
+load netBundle {exs#76.itm} 3 {exs#76.itm(0)} {exs#76.itm(1)} {exs#76.itm(2)} -attr xrf 63272 -attr oid 462 -attr vt d -attr @path {/sobel/sobel:core/exs#76.itm}
+load net {conc#938.itm(0)} -attr vt d
+load net {conc#938.itm(1)} -attr vt d
+load netBundle {conc#938.itm} 2 {conc#938.itm(0)} {conc#938.itm(1)} -attr xrf 63273 -attr oid 463 -attr vt d -attr @path {/sobel/sobel:core/conc#938.itm}
+load net {ACC1:exs#1543.itm(0)} -attr vt d
+load net {ACC1:exs#1543.itm(1)} -attr vt d
+load net {ACC1:exs#1543.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1543.itm} 3 {ACC1:exs#1543.itm(0)} {ACC1:exs#1543.itm(1)} {ACC1:exs#1543.itm(2)} -attr xrf 63274 -attr oid 464 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1543.itm}
+load net {ACC1:conc#1327.itm(0)} -attr vt d
+load net {ACC1:conc#1327.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1327.itm} 2 {ACC1:conc#1327.itm(0)} {ACC1:conc#1327.itm(1)} -attr xrf 63275 -attr oid 465 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1327.itm}
+load net {ACC1:acc#604.itm(0)} -attr vt d
+load net {ACC1:acc#604.itm(1)} -attr vt d
+load net {ACC1:acc#604.itm(2)} -attr vt d
+load net {ACC1:acc#604.itm(3)} -attr vt d
+load net {ACC1:acc#604.itm(4)} -attr vt d
+load net {ACC1:acc#604.itm(5)} -attr vt d
+load netBundle {ACC1:acc#604.itm} 6 {ACC1:acc#604.itm(0)} {ACC1:acc#604.itm(1)} {ACC1:acc#604.itm(2)} {ACC1:acc#604.itm(3)} {ACC1:acc#604.itm(4)} {ACC1:acc#604.itm(5)} -attr xrf 63276 -attr oid 466 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#579.itm(0)} -attr vt d
+load net {ACC1:acc#579.itm(1)} -attr vt d
+load net {ACC1:acc#579.itm(2)} -attr vt d
+load net {ACC1:acc#579.itm(3)} -attr vt d
+load net {ACC1:acc#579.itm(4)} -attr vt d
+load netBundle {ACC1:acc#579.itm} 5 {ACC1:acc#579.itm(0)} {ACC1:acc#579.itm(1)} {ACC1:acc#579.itm(2)} {ACC1:acc#579.itm(3)} {ACC1:acc#579.itm(4)} -attr xrf 63277 -attr oid 467 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#528.itm(0)} -attr vt d
+load net {ACC1:acc#528.itm(1)} -attr vt d
+load net {ACC1:acc#528.itm(2)} -attr vt d
+load net {ACC1:acc#528.itm(3)} -attr vt d
+load netBundle {ACC1:acc#528.itm} 4 {ACC1:acc#528.itm(0)} {ACC1:acc#528.itm(1)} {ACC1:acc#528.itm(2)} {ACC1:acc#528.itm(3)} -attr xrf 63278 -attr oid 468 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:slc#101.itm(0)} -attr vt d
+load net {ACC1:slc#101.itm(1)} -attr vt d
+load net {ACC1:slc#101.itm(2)} -attr vt d
+load netBundle {ACC1:slc#101.itm} 3 {ACC1:slc#101.itm(0)} {ACC1:slc#101.itm(1)} {ACC1:slc#101.itm(2)} -attr xrf 63279 -attr oid 469 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#101.itm}
+load net {ACC1:acc#433.itm(0)} -attr vt d
+load net {ACC1:acc#433.itm(1)} -attr vt d
+load net {ACC1:acc#433.itm(2)} -attr vt d
+load net {ACC1:acc#433.itm(3)} -attr vt d
+load netBundle {ACC1:acc#433.itm} 4 {ACC1:acc#433.itm(0)} {ACC1:acc#433.itm(1)} {ACC1:acc#433.itm(2)} {ACC1:acc#433.itm(3)} -attr xrf 63280 -attr oid 470 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#433.itm}
+load net {conc#939.itm(0)} -attr vt d
+load net {conc#939.itm(1)} -attr vt d
+load net {conc#939.itm(2)} -attr vt d
+load netBundle {conc#939.itm} 3 {conc#939.itm(0)} {conc#939.itm(1)} {conc#939.itm(2)} -attr xrf 63281 -attr oid 471 -attr vt d -attr @path {/sobel/sobel:core/conc#939.itm}
+load net {ACC1:conc#1325.itm(0)} -attr vt d
+load net {ACC1:conc#1325.itm(1)} -attr vt d
+load net {ACC1:conc#1325.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1325.itm} 3 {ACC1:conc#1325.itm(0)} {ACC1:conc#1325.itm(1)} {ACC1:conc#1325.itm(2)} -attr xrf 63282 -attr oid 472 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1325.itm}
+load net {ACC1:slc#100.itm(0)} -attr vt d
+load net {ACC1:slc#100.itm(1)} -attr vt d
+load net {ACC1:slc#100.itm(2)} -attr vt d
+load netBundle {ACC1:slc#100.itm} 3 {ACC1:slc#100.itm(0)} {ACC1:slc#100.itm(1)} {ACC1:slc#100.itm(2)} -attr xrf 63283 -attr oid 473 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#100.itm}
+load net {ACC1:acc#432.itm(0)} -attr vt d
+load net {ACC1:acc#432.itm(1)} -attr vt d
+load net {ACC1:acc#432.itm(2)} -attr vt d
+load net {ACC1:acc#432.itm(3)} -attr vt d
+load netBundle {ACC1:acc#432.itm} 4 {ACC1:acc#432.itm(0)} {ACC1:acc#432.itm(1)} {ACC1:acc#432.itm(2)} {ACC1:acc#432.itm(3)} -attr xrf 63284 -attr oid 474 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#432.itm}
+load net {conc#940.itm(0)} -attr vt d
+load net {conc#940.itm(1)} -attr vt d
+load net {conc#940.itm(2)} -attr vt d
+load netBundle {conc#940.itm} 3 {conc#940.itm(0)} {conc#940.itm(1)} {conc#940.itm(2)} -attr xrf 63285 -attr oid 475 -attr vt d -attr @path {/sobel/sobel:core/conc#940.itm}
+load net {ACC1:conc#1323.itm(0)} -attr vt d
+load net {ACC1:conc#1323.itm(1)} -attr vt d
+load net {ACC1:conc#1323.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1323.itm} 3 {ACC1:conc#1323.itm(0)} {ACC1:conc#1323.itm(1)} {ACC1:conc#1323.itm(2)} -attr xrf 63286 -attr oid 476 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1323.itm}
+load net {ACC1:acc#527.itm(0)} -attr vt d
+load net {ACC1:acc#527.itm(1)} -attr vt d
+load net {ACC1:acc#527.itm(2)} -attr vt d
+load net {ACC1:acc#527.itm(3)} -attr vt d
+load netBundle {ACC1:acc#527.itm} 4 {ACC1:acc#527.itm(0)} {ACC1:acc#527.itm(1)} {ACC1:acc#527.itm(2)} {ACC1:acc#527.itm(3)} -attr xrf 63287 -attr oid 477 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:slc#99.itm(0)} -attr vt d
+load net {ACC1:slc#99.itm(1)} -attr vt d
+load net {ACC1:slc#99.itm(2)} -attr vt d
+load netBundle {ACC1:slc#99.itm} 3 {ACC1:slc#99.itm(0)} {ACC1:slc#99.itm(1)} {ACC1:slc#99.itm(2)} -attr xrf 63288 -attr oid 478 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#431.itm(0)} -attr vt d
+load net {ACC1:acc#431.itm(1)} -attr vt d
+load net {ACC1:acc#431.itm(2)} -attr vt d
+load net {ACC1:acc#431.itm(3)} -attr vt d
+load netBundle {ACC1:acc#431.itm} 4 {ACC1:acc#431.itm(0)} {ACC1:acc#431.itm(1)} {ACC1:acc#431.itm(2)} {ACC1:acc#431.itm(3)} -attr xrf 63289 -attr oid 479 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#431.itm}
+load net {conc#941.itm(0)} -attr vt d
+load net {conc#941.itm(1)} -attr vt d
+load net {conc#941.itm(2)} -attr vt d
+load netBundle {conc#941.itm} 3 {conc#941.itm(0)} {conc#941.itm(1)} {conc#941.itm(2)} -attr xrf 63290 -attr oid 480 -attr vt d -attr @path {/sobel/sobel:core/conc#941.itm}
+load net {ACC1:conc#1321.itm(0)} -attr vt d
+load net {ACC1:conc#1321.itm(1)} -attr vt d
+load net {ACC1:conc#1321.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1321.itm} 3 {ACC1:conc#1321.itm(0)} {ACC1:conc#1321.itm(1)} {ACC1:conc#1321.itm(2)} -attr xrf 63291 -attr oid 481 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1321.itm}
+load net {ACC1:slc#98.itm(0)} -attr vt d
+load net {ACC1:slc#98.itm(1)} -attr vt d
+load net {ACC1:slc#98.itm(2)} -attr vt d
+load netBundle {ACC1:slc#98.itm} 3 {ACC1:slc#98.itm(0)} {ACC1:slc#98.itm(1)} {ACC1:slc#98.itm(2)} -attr xrf 63292 -attr oid 482 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#430.itm(0)} -attr vt d
+load net {ACC1:acc#430.itm(1)} -attr vt d
+load net {ACC1:acc#430.itm(2)} -attr vt d
+load net {ACC1:acc#430.itm(3)} -attr vt d
+load netBundle {ACC1:acc#430.itm} 4 {ACC1:acc#430.itm(0)} {ACC1:acc#430.itm(1)} {ACC1:acc#430.itm(2)} {ACC1:acc#430.itm(3)} -attr xrf 63293 -attr oid 483 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#430.itm}
+load net {conc#942.itm(0)} -attr vt d
+load net {conc#942.itm(1)} -attr vt d
+load net {conc#942.itm(2)} -attr vt d
+load netBundle {conc#942.itm} 3 {conc#942.itm(0)} {conc#942.itm(1)} {conc#942.itm(2)} -attr xrf 63294 -attr oid 484 -attr vt d -attr @path {/sobel/sobel:core/conc#942.itm}
+load net {ACC1:conc#1319.itm(0)} -attr vt d
+load net {ACC1:conc#1319.itm(1)} -attr vt d
+load net {ACC1:conc#1319.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1319.itm} 3 {ACC1:conc#1319.itm(0)} {ACC1:conc#1319.itm(1)} {ACC1:conc#1319.itm(2)} -attr xrf 63295 -attr oid 485 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1319.itm}
+load net {ACC1:acc#578.itm(0)} -attr vt d
+load net {ACC1:acc#578.itm(1)} -attr vt d
+load net {ACC1:acc#578.itm(2)} -attr vt d
+load net {ACC1:acc#578.itm(3)} -attr vt d
+load net {ACC1:acc#578.itm(4)} -attr vt d
+load netBundle {ACC1:acc#578.itm} 5 {ACC1:acc#578.itm(0)} {ACC1:acc#578.itm(1)} {ACC1:acc#578.itm(2)} {ACC1:acc#578.itm(3)} {ACC1:acc#578.itm(4)} -attr xrf 63296 -attr oid 486 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#526.itm(0)} -attr vt d
+load net {ACC1:acc#526.itm(1)} -attr vt d
+load net {ACC1:acc#526.itm(2)} -attr vt d
+load net {ACC1:acc#526.itm(3)} -attr vt d
+load netBundle {ACC1:acc#526.itm} 4 {ACC1:acc#526.itm(0)} {ACC1:acc#526.itm(1)} {ACC1:acc#526.itm(2)} {ACC1:acc#526.itm(3)} -attr xrf 63297 -attr oid 487 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:slc#97.itm(0)} -attr vt d
+load net {ACC1:slc#97.itm(1)} -attr vt d
+load net {ACC1:slc#97.itm(2)} -attr vt d
+load netBundle {ACC1:slc#97.itm} 3 {ACC1:slc#97.itm(0)} {ACC1:slc#97.itm(1)} {ACC1:slc#97.itm(2)} -attr xrf 63298 -attr oid 488 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#429.itm(0)} -attr vt d
+load net {ACC1:acc#429.itm(1)} -attr vt d
+load net {ACC1:acc#429.itm(2)} -attr vt d
+load net {ACC1:acc#429.itm(3)} -attr vt d
+load netBundle {ACC1:acc#429.itm} 4 {ACC1:acc#429.itm(0)} {ACC1:acc#429.itm(1)} {ACC1:acc#429.itm(2)} {ACC1:acc#429.itm(3)} -attr xrf 63299 -attr oid 489 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#429.itm}
+load net {conc#943.itm(0)} -attr vt d
+load net {conc#943.itm(1)} -attr vt d
+load net {conc#943.itm(2)} -attr vt d
+load netBundle {conc#943.itm} 3 {conc#943.itm(0)} {conc#943.itm(1)} {conc#943.itm(2)} -attr xrf 63300 -attr oid 490 -attr vt d -attr @path {/sobel/sobel:core/conc#943.itm}
+load net {ACC1:conc#1317.itm(0)} -attr vt d
+load net {ACC1:conc#1317.itm(1)} -attr vt d
+load net {ACC1:conc#1317.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1317.itm} 3 {ACC1:conc#1317.itm(0)} {ACC1:conc#1317.itm(1)} {ACC1:conc#1317.itm(2)} -attr xrf 63301 -attr oid 491 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1317.itm}
+load net {ACC1:slc#96.itm(0)} -attr vt d
+load net {ACC1:slc#96.itm(1)} -attr vt d
+load net {ACC1:slc#96.itm(2)} -attr vt d
+load netBundle {ACC1:slc#96.itm} 3 {ACC1:slc#96.itm(0)} {ACC1:slc#96.itm(1)} {ACC1:slc#96.itm(2)} -attr xrf 63302 -attr oid 492 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#428.itm(0)} -attr vt d
+load net {ACC1:acc#428.itm(1)} -attr vt d
+load net {ACC1:acc#428.itm(2)} -attr vt d
+load net {ACC1:acc#428.itm(3)} -attr vt d
+load netBundle {ACC1:acc#428.itm} 4 {ACC1:acc#428.itm(0)} {ACC1:acc#428.itm(1)} {ACC1:acc#428.itm(2)} {ACC1:acc#428.itm(3)} -attr xrf 63303 -attr oid 493 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#428.itm}
+load net {conc#944.itm(0)} -attr vt d
+load net {conc#944.itm(1)} -attr vt d
+load net {conc#944.itm(2)} -attr vt d
+load netBundle {conc#944.itm} 3 {conc#944.itm(0)} {conc#944.itm(1)} {conc#944.itm(2)} -attr xrf 63304 -attr oid 494 -attr vt d -attr @path {/sobel/sobel:core/conc#944.itm}
+load net {ACC1:conc#1315.itm(0)} -attr vt d
+load net {ACC1:conc#1315.itm(1)} -attr vt d
+load net {ACC1:conc#1315.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1315.itm} 3 {ACC1:conc#1315.itm(0)} {ACC1:conc#1315.itm(1)} {ACC1:conc#1315.itm(2)} -attr xrf 63305 -attr oid 495 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1315.itm}
+load net {ACC1:acc#525.itm(0)} -attr vt d
+load net {ACC1:acc#525.itm(1)} -attr vt d
+load net {ACC1:acc#525.itm(2)} -attr vt d
+load net {ACC1:acc#525.itm(3)} -attr vt d
+load netBundle {ACC1:acc#525.itm} 4 {ACC1:acc#525.itm(0)} {ACC1:acc#525.itm(1)} {ACC1:acc#525.itm(2)} {ACC1:acc#525.itm(3)} -attr xrf 63306 -attr oid 496 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:slc#95.itm(0)} -attr vt d
+load net {ACC1:slc#95.itm(1)} -attr vt d
+load net {ACC1:slc#95.itm(2)} -attr vt d
+load netBundle {ACC1:slc#95.itm} 3 {ACC1:slc#95.itm(0)} {ACC1:slc#95.itm(1)} {ACC1:slc#95.itm(2)} -attr xrf 63307 -attr oid 497 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#427.itm(0)} -attr vt d
+load net {ACC1:acc#427.itm(1)} -attr vt d
+load net {ACC1:acc#427.itm(2)} -attr vt d
+load net {ACC1:acc#427.itm(3)} -attr vt d
+load netBundle {ACC1:acc#427.itm} 4 {ACC1:acc#427.itm(0)} {ACC1:acc#427.itm(1)} {ACC1:acc#427.itm(2)} {ACC1:acc#427.itm(3)} -attr xrf 63308 -attr oid 498 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#427.itm}
+load net {conc#945.itm(0)} -attr vt d
+load net {conc#945.itm(1)} -attr vt d
+load net {conc#945.itm(2)} -attr vt d
+load netBundle {conc#945.itm} 3 {conc#945.itm(0)} {conc#945.itm(1)} {conc#945.itm(2)} -attr xrf 63309 -attr oid 499 -attr vt d -attr @path {/sobel/sobel:core/conc#945.itm}
+load net {ACC1:conc#1313.itm(0)} -attr vt d
+load net {ACC1:conc#1313.itm(1)} -attr vt d
+load net {ACC1:conc#1313.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1313.itm} 3 {ACC1:conc#1313.itm(0)} {ACC1:conc#1313.itm(1)} {ACC1:conc#1313.itm(2)} -attr xrf 63310 -attr oid 500 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1313.itm}
+load net {ACC1:slc#94.itm(0)} -attr vt d
+load net {ACC1:slc#94.itm(1)} -attr vt d
+load net {ACC1:slc#94.itm(2)} -attr vt d
+load netBundle {ACC1:slc#94.itm} 3 {ACC1:slc#94.itm(0)} {ACC1:slc#94.itm(1)} {ACC1:slc#94.itm(2)} -attr xrf 63311 -attr oid 501 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#426.itm(0)} -attr vt d
+load net {ACC1:acc#426.itm(1)} -attr vt d
+load net {ACC1:acc#426.itm(2)} -attr vt d
+load net {ACC1:acc#426.itm(3)} -attr vt d
+load netBundle {ACC1:acc#426.itm} 4 {ACC1:acc#426.itm(0)} {ACC1:acc#426.itm(1)} {ACC1:acc#426.itm(2)} {ACC1:acc#426.itm(3)} -attr xrf 63312 -attr oid 502 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#426.itm}
+load net {conc#946.itm(0)} -attr vt d
+load net {conc#946.itm(1)} -attr vt d
+load net {conc#946.itm(2)} -attr vt d
+load netBundle {conc#946.itm} 3 {conc#946.itm(0)} {conc#946.itm(1)} {conc#946.itm(2)} -attr xrf 63313 -attr oid 503 -attr vt d -attr @path {/sobel/sobel:core/conc#946.itm}
+load net {ACC1:conc#1311.itm(0)} -attr vt d
+load net {ACC1:conc#1311.itm(1)} -attr vt d
+load net {ACC1:conc#1311.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1311.itm} 3 {ACC1:conc#1311.itm(0)} {ACC1:conc#1311.itm(1)} {ACC1:conc#1311.itm(2)} -attr xrf 63314 -attr oid 504 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1311.itm}
+load net {ACC1:acc#634.itm(0)} -attr vt d
+load net {ACC1:acc#634.itm(1)} -attr vt d
+load net {ACC1:acc#634.itm(2)} -attr vt d
+load net {ACC1:acc#634.itm(3)} -attr vt d
+load net {ACC1:acc#634.itm(4)} -attr vt d
+load net {ACC1:acc#634.itm(5)} -attr vt d
+load net {ACC1:acc#634.itm(6)} -attr vt d
+load net {ACC1:acc#634.itm(7)} -attr vt d
+load netBundle {ACC1:acc#634.itm} 8 {ACC1:acc#634.itm(0)} {ACC1:acc#634.itm(1)} {ACC1:acc#634.itm(2)} {ACC1:acc#634.itm(3)} {ACC1:acc#634.itm(4)} {ACC1:acc#634.itm(5)} {ACC1:acc#634.itm(6)} {ACC1:acc#634.itm(7)} -attr xrf 63315 -attr oid 505 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:conc#1452.itm(0)} -attr vt d
+load net {ACC1:conc#1452.itm(1)} -attr vt d
+load net {ACC1:conc#1452.itm(2)} -attr vt d
+load net {ACC1:conc#1452.itm(3)} -attr vt d
+load net {ACC1:conc#1452.itm(4)} -attr vt d
+load net {ACC1:conc#1452.itm(5)} -attr vt d
+load net {ACC1:conc#1452.itm(6)} -attr vt d
+load netBundle {ACC1:conc#1452.itm} 7 {ACC1:conc#1452.itm(0)} {ACC1:conc#1452.itm(1)} {ACC1:conc#1452.itm(2)} {ACC1:conc#1452.itm(3)} {ACC1:conc#1452.itm(4)} {ACC1:conc#1452.itm(5)} {ACC1:conc#1452.itm(6)} -attr xrf 63316 -attr oid 506 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#721.itm(0)} -attr vt d
+load net {ACC1:acc#721.itm(1)} -attr vt d
+load net {ACC1:acc#721.itm(2)} -attr vt d
+load net {ACC1:acc#721.itm(3)} -attr vt d
+load netBundle {ACC1:acc#721.itm} 4 {ACC1:acc#721.itm(0)} {ACC1:acc#721.itm(1)} {ACC1:acc#721.itm(2)} {ACC1:acc#721.itm(3)} -attr xrf 63317 -attr oid 507 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#721.itm}
+load net {conc#947.itm(0)} -attr vt d
+load net {conc#947.itm(1)} -attr vt d
+load net {conc#947.itm(2)} -attr vt d
+load netBundle {conc#947.itm} 3 {conc#947.itm(0)} {conc#947.itm(1)} {conc#947.itm(2)} -attr xrf 63318 -attr oid 508 -attr vt d -attr @path {/sobel/sobel:core/conc#947.itm}
+load net {ACC1:conc#1119.itm(0)} -attr vt d
+load net {ACC1:conc#1119.itm(1)} -attr vt d
+load net {ACC1:conc#1119.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1119.itm} 3 {ACC1:conc#1119.itm(0)} {ACC1:conc#1119.itm(1)} {ACC1:conc#1119.itm(2)} -attr xrf 63319 -attr oid 509 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1119.itm}
+load net {ACC1:acc#722.itm(0)} -attr vt d
+load net {ACC1:acc#722.itm(1)} -attr vt d
+load net {ACC1:acc#722.itm(2)} -attr vt d
+load netBundle {ACC1:acc#722.itm} 3 {ACC1:acc#722.itm(0)} {ACC1:acc#722.itm(1)} {ACC1:acc#722.itm(2)} -attr xrf 63320 -attr oid 510 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#722.itm}
+load net {ACC1:conc#1453.itm(0)} -attr vt d
+load net {ACC1:conc#1453.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1453.itm} 2 {ACC1:conc#1453.itm(0)} {ACC1:conc#1453.itm(1)} -attr xrf 63321 -attr oid 511 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1453.itm}
+load net {ACC1:exs#1544.itm(0)} -attr vt d
+load net {ACC1:exs#1544.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1544.itm} 2 {ACC1:exs#1544.itm(0)} {ACC1:exs#1544.itm(1)} -attr xrf 63322 -attr oid 512 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1544.itm}
+load net {ACC1:conc#1454.itm(0)} -attr vt d
+load net {ACC1:conc#1454.itm(1)} -attr vt d
+load net {ACC1:conc#1454.itm(2)} -attr vt d
+load net {ACC1:conc#1454.itm(3)} -attr vt d
+load net {ACC1:conc#1454.itm(4)} -attr vt d
+load net {ACC1:conc#1454.itm(5)} -attr vt d
+load net {ACC1:conc#1454.itm(6)} -attr vt d
+load netBundle {ACC1:conc#1454.itm} 7 {ACC1:conc#1454.itm(0)} {ACC1:conc#1454.itm(1)} {ACC1:conc#1454.itm(2)} {ACC1:conc#1454.itm(3)} {ACC1:conc#1454.itm(4)} {ACC1:conc#1454.itm(5)} {ACC1:conc#1454.itm(6)} -attr xrf 63323 -attr oid 513 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#723.itm(0)} -attr vt d
+load net {ACC1:acc#723.itm(1)} -attr vt d
+load net {ACC1:acc#723.itm(2)} -attr vt d
+load net {ACC1:acc#723.itm(3)} -attr vt d
+load netBundle {ACC1:acc#723.itm} 4 {ACC1:acc#723.itm(0)} {ACC1:acc#723.itm(1)} {ACC1:acc#723.itm(2)} {ACC1:acc#723.itm(3)} -attr xrf 63324 -attr oid 514 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#723.itm}
+load net {ACC1:conc#1120.itm(0)} -attr vt d
+load net {ACC1:conc#1120.itm(1)} -attr vt d
+load net {ACC1:conc#1120.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1120.itm} 3 {ACC1:conc#1120.itm(0)} {ACC1:conc#1120.itm(1)} {ACC1:conc#1120.itm(2)} -attr xrf 63325 -attr oid 515 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1120.itm}
+load net {conc#948.itm(0)} -attr vt d
+load net {conc#948.itm(1)} -attr vt d
+load net {conc#948.itm(2)} -attr vt d
+load netBundle {conc#948.itm} 3 {conc#948.itm(0)} {conc#948.itm(1)} {conc#948.itm(2)} -attr xrf 63326 -attr oid 516 -attr vt d -attr @path {/sobel/sobel:core/conc#948.itm}
+load net {ACC1:acc#643.itm(0)} -attr vt d
+load net {ACC1:acc#643.itm(1)} -attr vt d
+load net {ACC1:acc#643.itm(2)} -attr vt d
+load net {ACC1:acc#643.itm(3)} -attr vt d
+load net {ACC1:acc#643.itm(4)} -attr vt d
+load net {ACC1:acc#643.itm(5)} -attr vt d
+load net {ACC1:acc#643.itm(6)} -attr vt d
+load net {ACC1:acc#643.itm(7)} -attr vt d
+load net {ACC1:acc#643.itm(8)} -attr vt d
+load netBundle {ACC1:acc#643.itm} 9 {ACC1:acc#643.itm(0)} {ACC1:acc#643.itm(1)} {ACC1:acc#643.itm(2)} {ACC1:acc#643.itm(3)} {ACC1:acc#643.itm(4)} {ACC1:acc#643.itm(5)} {ACC1:acc#643.itm(6)} {ACC1:acc#643.itm(7)} {ACC1:acc#643.itm(8)} -attr xrf 63327 -attr oid 517 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#633.itm(0)} -attr vt d
+load net {ACC1:acc#633.itm(1)} -attr vt d
+load net {ACC1:acc#633.itm(2)} -attr vt d
+load net {ACC1:acc#633.itm(3)} -attr vt d
+load net {ACC1:acc#633.itm(4)} -attr vt d
+load net {ACC1:acc#633.itm(5)} -attr vt d
+load net {ACC1:acc#633.itm(6)} -attr vt d
+load net {ACC1:acc#633.itm(7)} -attr vt d
+load netBundle {ACC1:acc#633.itm} 8 {ACC1:acc#633.itm(0)} {ACC1:acc#633.itm(1)} {ACC1:acc#633.itm(2)} {ACC1:acc#633.itm(3)} {ACC1:acc#633.itm(4)} {ACC1:acc#633.itm(5)} {ACC1:acc#633.itm(6)} {ACC1:acc#633.itm(7)} -attr xrf 63328 -attr oid 518 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:conc#1455.itm(0)} -attr vt d
+load net {ACC1:conc#1455.itm(1)} -attr vt d
+load net {ACC1:conc#1455.itm(2)} -attr vt d
+load net {ACC1:conc#1455.itm(3)} -attr vt d
+load net {ACC1:conc#1455.itm(4)} -attr vt d
+load net {ACC1:conc#1455.itm(5)} -attr vt d
+load net {ACC1:conc#1455.itm(6)} -attr vt d
+load netBundle {ACC1:conc#1455.itm} 7 {ACC1:conc#1455.itm(0)} {ACC1:conc#1455.itm(1)} {ACC1:conc#1455.itm(2)} {ACC1:conc#1455.itm(3)} {ACC1:conc#1455.itm(4)} {ACC1:conc#1455.itm(5)} {ACC1:conc#1455.itm(6)} -attr xrf 63329 -attr oid 519 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#725.itm(0)} -attr vt d
+load net {ACC1:acc#725.itm(1)} -attr vt d
+load netBundle {ACC1:acc#725.itm} 2 {ACC1:acc#725.itm(0)} {ACC1:acc#725.itm(1)} -attr xrf 63330 -attr oid 520 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#725.itm}
+load net {ACC1:acc#726.itm(0)} -attr vt d
+load net {ACC1:acc#726.itm(1)} -attr vt d
+load netBundle {ACC1:acc#726.itm} 2 {ACC1:acc#726.itm(0)} {ACC1:acc#726.itm(1)} -attr xrf 63331 -attr oid 521 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#726.itm}
+load net {ACC1:conc#1456.itm(0)} -attr vt d
+load net {ACC1:conc#1456.itm(1)} -attr vt d
+load net {ACC1:conc#1456.itm(2)} -attr vt d
+load net {ACC1:conc#1456.itm(3)} -attr vt d
+load net {ACC1:conc#1456.itm(4)} -attr vt d
+load net {ACC1:conc#1456.itm(5)} -attr vt d
+load net {ACC1:conc#1456.itm(6)} -attr vt d
+load netBundle {ACC1:conc#1456.itm} 7 {ACC1:conc#1456.itm(0)} {ACC1:conc#1456.itm(1)} {ACC1:conc#1456.itm(2)} {ACC1:conc#1456.itm(3)} {ACC1:conc#1456.itm(4)} {ACC1:conc#1456.itm(5)} {ACC1:conc#1456.itm(6)} -attr xrf 63332 -attr oid 522 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#728.itm(0)} -attr vt d
+load net {ACC1:acc#728.itm(1)} -attr vt d
+load netBundle {ACC1:acc#728.itm} 2 {ACC1:acc#728.itm(0)} {ACC1:acc#728.itm(1)} -attr xrf 63333 -attr oid 523 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#728.itm}
+load net {ACC1:acc#729.itm(0)} -attr vt d
+load net {ACC1:acc#729.itm(1)} -attr vt d
+load netBundle {ACC1:acc#729.itm} 2 {ACC1:acc#729.itm(0)} {ACC1:acc#729.itm(1)} -attr xrf 63334 -attr oid 524 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#729.itm}
+load net {ACC1:acc#632.itm(0)} -attr vt d
+load net {ACC1:acc#632.itm(1)} -attr vt d
+load net {ACC1:acc#632.itm(2)} -attr vt d
+load net {ACC1:acc#632.itm(3)} -attr vt d
+load net {ACC1:acc#632.itm(4)} -attr vt d
+load net {ACC1:acc#632.itm(5)} -attr vt d
+load net {ACC1:acc#632.itm(6)} -attr vt d
+load net {ACC1:acc#632.itm(7)} -attr vt d
+load netBundle {ACC1:acc#632.itm} 8 {ACC1:acc#632.itm(0)} {ACC1:acc#632.itm(1)} {ACC1:acc#632.itm(2)} {ACC1:acc#632.itm(3)} {ACC1:acc#632.itm(4)} {ACC1:acc#632.itm(5)} {ACC1:acc#632.itm(6)} {ACC1:acc#632.itm(7)} -attr xrf 63335 -attr oid 525 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1-3:exs#1032.itm(0)} -attr vt d
+load net {ACC1-3:exs#1032.itm(1)} -attr vt d
+load net {ACC1-3:exs#1032.itm(2)} -attr vt d
+load net {ACC1-3:exs#1032.itm(3)} -attr vt d
+load net {ACC1-3:exs#1032.itm(4)} -attr vt d
+load net {ACC1-3:exs#1032.itm(5)} -attr vt d
+load net {ACC1-3:exs#1032.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#1032.itm} 7 {ACC1-3:exs#1032.itm(0)} {ACC1-3:exs#1032.itm(1)} {ACC1-3:exs#1032.itm(2)} {ACC1-3:exs#1032.itm(3)} {ACC1-3:exs#1032.itm(4)} {ACC1-3:exs#1032.itm(5)} {ACC1-3:exs#1032.itm(6)} -attr xrf 63336 -attr oid 526 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1-3:conc#496.itm(0)} -attr vt d
+load net {ACC1-3:conc#496.itm(1)} -attr vt d
+load net {ACC1-3:conc#496.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#496.itm} 3 {ACC1-3:conc#496.itm(0)} {ACC1-3:conc#496.itm(1)} {ACC1-3:conc#496.itm(2)} -attr xrf 63337 -attr oid 527 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#496.itm}
+load net {ACC1-3:exs#30.itm(0)} -attr vt d
+load net {ACC1-3:exs#30.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#30.itm} 2 {ACC1-3:exs#30.itm(0)} {ACC1-3:exs#30.itm(1)} -attr xrf 63338 -attr oid 528 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#30.itm}
+load net {ACC1-3:exs#1029.itm(0)} -attr vt d
+load net {ACC1-3:exs#1029.itm(1)} -attr vt d
+load net {ACC1-3:exs#1029.itm(2)} -attr vt d
+load net {ACC1-3:exs#1029.itm(3)} -attr vt d
+load net {ACC1-3:exs#1029.itm(4)} -attr vt d
+load net {ACC1-3:exs#1029.itm(5)} -attr vt d
+load net {ACC1-3:exs#1029.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#1029.itm} 7 {ACC1-3:exs#1029.itm(0)} {ACC1-3:exs#1029.itm(1)} {ACC1-3:exs#1029.itm(2)} {ACC1-3:exs#1029.itm(3)} {ACC1-3:exs#1029.itm(4)} {ACC1-3:exs#1029.itm(5)} {ACC1-3:exs#1029.itm(6)} -attr xrf 63339 -attr oid 529 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {ACC1-3:conc#482.itm(0)} -attr vt d
+load net {ACC1-3:conc#482.itm(1)} -attr vt d
+load net {ACC1-3:conc#482.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#482.itm} 3 {ACC1-3:conc#482.itm(0)} {ACC1-3:conc#482.itm(1)} {ACC1-3:conc#482.itm(2)} -attr xrf 63340 -attr oid 530 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#482.itm}
+load net {ACC1-3:exs#12.itm(0)} -attr vt d
+load net {ACC1-3:exs#12.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#12.itm} 2 {ACC1-3:exs#12.itm(0)} {ACC1-3:exs#12.itm(1)} -attr xrf 63341 -attr oid 531 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#12.itm}
+load net {ACC1:acc#648.itm(0)} -attr vt d
+load net {ACC1:acc#648.itm(1)} -attr vt d
+load net {ACC1:acc#648.itm(2)} -attr vt d
+load net {ACC1:acc#648.itm(3)} -attr vt d
+load net {ACC1:acc#648.itm(4)} -attr vt d
+load net {ACC1:acc#648.itm(5)} -attr vt d
+load net {ACC1:acc#648.itm(6)} -attr vt d
+load net {ACC1:acc#648.itm(7)} -attr vt d
+load net {ACC1:acc#648.itm(8)} -attr vt d
+load net {ACC1:acc#648.itm(9)} -attr vt d
+load netBundle {ACC1:acc#648.itm} 10 {ACC1:acc#648.itm(0)} {ACC1:acc#648.itm(1)} {ACC1:acc#648.itm(2)} {ACC1:acc#648.itm(3)} {ACC1:acc#648.itm(4)} {ACC1:acc#648.itm(5)} {ACC1:acc#648.itm(6)} {ACC1:acc#648.itm(7)} {ACC1:acc#648.itm(8)} {ACC1:acc#648.itm(9)} -attr xrf 63342 -attr oid 532 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#642.itm(0)} -attr vt d
+load net {ACC1:acc#642.itm(1)} -attr vt d
+load net {ACC1:acc#642.itm(2)} -attr vt d
+load net {ACC1:acc#642.itm(3)} -attr vt d
+load net {ACC1:acc#642.itm(4)} -attr vt d
+load net {ACC1:acc#642.itm(5)} -attr vt d
+load net {ACC1:acc#642.itm(6)} -attr vt d
+load net {ACC1:acc#642.itm(7)} -attr vt d
+load net {ACC1:acc#642.itm(8)} -attr vt d
+load netBundle {ACC1:acc#642.itm} 9 {ACC1:acc#642.itm(0)} {ACC1:acc#642.itm(1)} {ACC1:acc#642.itm(2)} {ACC1:acc#642.itm(3)} {ACC1:acc#642.itm(4)} {ACC1:acc#642.itm(5)} {ACC1:acc#642.itm(6)} {ACC1:acc#642.itm(7)} {ACC1:acc#642.itm(8)} -attr xrf 63343 -attr oid 533 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#631.itm(0)} -attr vt d
+load net {ACC1:acc#631.itm(1)} -attr vt d
+load net {ACC1:acc#631.itm(2)} -attr vt d
+load net {ACC1:acc#631.itm(3)} -attr vt d
+load net {ACC1:acc#631.itm(4)} -attr vt d
+load net {ACC1:acc#631.itm(5)} -attr vt d
+load net {ACC1:acc#631.itm(6)} -attr vt d
+load net {ACC1:acc#631.itm(7)} -attr vt d
+load netBundle {ACC1:acc#631.itm} 8 {ACC1:acc#631.itm(0)} {ACC1:acc#631.itm(1)} {ACC1:acc#631.itm(2)} {ACC1:acc#631.itm(3)} {ACC1:acc#631.itm(4)} {ACC1:acc#631.itm(5)} {ACC1:acc#631.itm(6)} {ACC1:acc#631.itm(7)} -attr xrf 63344 -attr oid 534 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1-3:exs#1035.itm(0)} -attr vt d
+load net {ACC1-3:exs#1035.itm(1)} -attr vt d
+load net {ACC1-3:exs#1035.itm(2)} -attr vt d
+load net {ACC1-3:exs#1035.itm(3)} -attr vt d
+load net {ACC1-3:exs#1035.itm(4)} -attr vt d
+load net {ACC1-3:exs#1035.itm(5)} -attr vt d
+load net {ACC1-3:exs#1035.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#1035.itm} 7 {ACC1-3:exs#1035.itm(0)} {ACC1-3:exs#1035.itm(1)} {ACC1-3:exs#1035.itm(2)} {ACC1-3:exs#1035.itm(3)} {ACC1-3:exs#1035.itm(4)} {ACC1-3:exs#1035.itm(5)} {ACC1-3:exs#1035.itm(6)} -attr xrf 63345 -attr oid 535 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1-3:conc#510.itm(0)} -attr vt d
+load net {ACC1-3:conc#510.itm(1)} -attr vt d
+load net {ACC1-3:conc#510.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#510.itm} 3 {ACC1-3:conc#510.itm(0)} {ACC1-3:conc#510.itm(1)} {ACC1-3:conc#510.itm(2)} -attr xrf 63346 -attr oid 536 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#510.itm}
+load net {ACC1-3:exs#1062.itm(0)} -attr vt d
+load net {ACC1-3:exs#1062.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1062.itm} 2 {ACC1-3:exs#1062.itm(0)} {ACC1-3:exs#1062.itm(1)} -attr xrf 63347 -attr oid 537 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1062.itm}
+load net {ACC1-2:exs#1032.itm(0)} -attr vt d
+load net {ACC1-2:exs#1032.itm(1)} -attr vt d
+load net {ACC1-2:exs#1032.itm(2)} -attr vt d
+load net {ACC1-2:exs#1032.itm(3)} -attr vt d
+load net {ACC1-2:exs#1032.itm(4)} -attr vt d
+load net {ACC1-2:exs#1032.itm(5)} -attr vt d
+load net {ACC1-2:exs#1032.itm(6)} -attr vt d
+load netBundle {ACC1-2:exs#1032.itm} 7 {ACC1-2:exs#1032.itm(0)} {ACC1-2:exs#1032.itm(1)} {ACC1-2:exs#1032.itm(2)} {ACC1-2:exs#1032.itm(3)} {ACC1-2:exs#1032.itm(4)} {ACC1-2:exs#1032.itm(5)} {ACC1-2:exs#1032.itm(6)} -attr xrf 63348 -attr oid 538 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1-2:conc#496.itm(0)} -attr vt d
+load net {ACC1-2:conc#496.itm(1)} -attr vt d
+load net {ACC1-2:conc#496.itm(2)} -attr vt d
+load netBundle {ACC1-2:conc#496.itm} 3 {ACC1-2:conc#496.itm(0)} {ACC1-2:conc#496.itm(1)} {ACC1-2:conc#496.itm(2)} -attr xrf 63349 -attr oid 539 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:conc#496.itm}
+load net {ACC1-2:exs#1052.itm(0)} -attr vt d
+load net {ACC1-2:exs#1052.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1052.itm} 2 {ACC1-2:exs#1052.itm(0)} {ACC1-2:exs#1052.itm(1)} -attr xrf 63350 -attr oid 540 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1052.itm}
+load net {ACC1:acc#630.itm(0)} -attr vt d
+load net {ACC1:acc#630.itm(1)} -attr vt d
+load net {ACC1:acc#630.itm(2)} -attr vt d
+load net {ACC1:acc#630.itm(3)} -attr vt d
+load net {ACC1:acc#630.itm(4)} -attr vt d
+load net {ACC1:acc#630.itm(5)} -attr vt d
+load net {ACC1:acc#630.itm(6)} -attr vt d
+load net {ACC1:acc#630.itm(7)} -attr vt d
+load netBundle {ACC1:acc#630.itm} 8 {ACC1:acc#630.itm(0)} {ACC1:acc#630.itm(1)} {ACC1:acc#630.itm(2)} {ACC1:acc#630.itm(3)} {ACC1:acc#630.itm(4)} {ACC1:acc#630.itm(5)} {ACC1:acc#630.itm(6)} {ACC1:acc#630.itm(7)} -attr xrf 63351 -attr oid 541 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {exs#94.itm(0)} -attr vt d
+load net {exs#94.itm(1)} -attr vt d
+load net {exs#94.itm(2)} -attr vt d
+load net {exs#94.itm(3)} -attr vt d
+load net {exs#94.itm(4)} -attr vt d
+load net {exs#94.itm(5)} -attr vt d
+load net {exs#94.itm(6)} -attr vt d
+load netBundle {exs#94.itm} 7 {exs#94.itm(0)} {exs#94.itm(1)} {exs#94.itm(2)} {exs#94.itm(3)} {exs#94.itm(4)} {exs#94.itm(5)} {exs#94.itm(6)} -attr xrf 63352 -attr oid 542 -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {conc#949.itm(0)} -attr vt d
+load net {conc#949.itm(1)} -attr vt d
+load net {conc#949.itm(2)} -attr vt d
+load net {conc#949.itm(3)} -attr vt d
+load netBundle {conc#949.itm} 4 {conc#949.itm(0)} {conc#949.itm(1)} {conc#949.itm(2)} {conc#949.itm(3)} -attr xrf 63353 -attr oid 543 -attr vt d -attr @path {/sobel/sobel:core/conc#949.itm}
+load net {ACC1-3:exs#1071.itm(0)} -attr vt d
+load net {ACC1-3:exs#1071.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1071.itm} 2 {ACC1-3:exs#1071.itm(0)} {ACC1-3:exs#1071.itm(1)} -attr xrf 63354 -attr oid 544 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1071.itm}
+load net {ACC1-3:exs#1040.itm(0)} -attr vt d
+load net {ACC1-3:exs#1040.itm(1)} -attr vt d
+load net {ACC1-3:exs#1040.itm(2)} -attr vt d
+load net {ACC1-3:exs#1040.itm(3)} -attr vt d
+load net {ACC1-3:exs#1040.itm(4)} -attr vt d
+load net {ACC1-3:exs#1040.itm(5)} -attr vt d
+load net {ACC1-3:exs#1040.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#1040.itm} 7 {ACC1-3:exs#1040.itm(0)} {ACC1-3:exs#1040.itm(1)} {ACC1-3:exs#1040.itm(2)} {ACC1-3:exs#1040.itm(3)} {ACC1-3:exs#1040.itm(4)} {ACC1-3:exs#1040.itm(5)} {ACC1-3:exs#1040.itm(6)} -attr xrf 63355 -attr oid 545 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {ACC1-3:conc#538.itm(0)} -attr vt d
+load net {ACC1-3:conc#538.itm(1)} -attr vt d
+load net {ACC1-3:conc#538.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#538.itm} 3 {ACC1-3:conc#538.itm(0)} {ACC1-3:conc#538.itm(1)} {ACC1-3:conc#538.itm(2)} -attr xrf 63356 -attr oid 546 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#538.itm}
+load net {ACC1-3:exs#1045.itm(0)} -attr vt d
+load net {ACC1-3:exs#1045.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1045.itm} 2 {ACC1-3:exs#1045.itm(0)} {ACC1-3:exs#1045.itm(1)} -attr xrf 63357 -attr oid 547 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1045.itm}
+load net {ACC1:acc#641.itm(0)} -attr vt d
+load net {ACC1:acc#641.itm(1)} -attr vt d
+load net {ACC1:acc#641.itm(2)} -attr vt d
+load net {ACC1:acc#641.itm(3)} -attr vt d
+load net {ACC1:acc#641.itm(4)} -attr vt d
+load net {ACC1:acc#641.itm(5)} -attr vt d
+load net {ACC1:acc#641.itm(6)} -attr vt d
+load net {ACC1:acc#641.itm(7)} -attr vt d
+load net {ACC1:acc#641.itm(8)} -attr vt d
+load netBundle {ACC1:acc#641.itm} 9 {ACC1:acc#641.itm(0)} {ACC1:acc#641.itm(1)} {ACC1:acc#641.itm(2)} {ACC1:acc#641.itm(3)} {ACC1:acc#641.itm(4)} {ACC1:acc#641.itm(5)} {ACC1:acc#641.itm(6)} {ACC1:acc#641.itm(7)} {ACC1:acc#641.itm(8)} -attr xrf 63358 -attr oid 548 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#629.itm(0)} -attr vt d
+load net {ACC1:acc#629.itm(1)} -attr vt d
+load net {ACC1:acc#629.itm(2)} -attr vt d
+load net {ACC1:acc#629.itm(3)} -attr vt d
+load net {ACC1:acc#629.itm(4)} -attr vt d
+load net {ACC1:acc#629.itm(5)} -attr vt d
+load net {ACC1:acc#629.itm(6)} -attr vt d
+load net {ACC1:acc#629.itm(7)} -attr vt d
+load netBundle {ACC1:acc#629.itm} 8 {ACC1:acc#629.itm(0)} {ACC1:acc#629.itm(1)} {ACC1:acc#629.itm(2)} {ACC1:acc#629.itm(3)} {ACC1:acc#629.itm(4)} {ACC1:acc#629.itm(5)} {ACC1:acc#629.itm(6)} {ACC1:acc#629.itm(7)} -attr xrf 63359 -attr oid 549 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {exs#95.itm(0)} -attr vt d
+load net {exs#95.itm(1)} -attr vt d
+load net {exs#95.itm(2)} -attr vt d
+load net {exs#95.itm(3)} -attr vt d
+load net {exs#95.itm(4)} -attr vt d
+load net {exs#95.itm(5)} -attr vt d
+load net {exs#95.itm(6)} -attr vt d
+load netBundle {exs#95.itm} 7 {exs#95.itm(0)} {exs#95.itm(1)} {exs#95.itm(2)} {exs#95.itm(3)} {exs#95.itm(4)} {exs#95.itm(5)} {exs#95.itm(6)} -attr xrf 63360 -attr oid 550 -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {conc#951.itm(0)} -attr vt d
+load net {conc#951.itm(1)} -attr vt d
+load net {conc#951.itm(2)} -attr vt d
+load net {conc#951.itm(3)} -attr vt d
+load netBundle {conc#951.itm} 4 {conc#951.itm(0)} {conc#951.itm(1)} {conc#951.itm(2)} {conc#951.itm(3)} -attr xrf 63361 -attr oid 551 -attr vt d -attr @path {/sobel/sobel:core/conc#951.itm}
+load net {ACC1-2:exs#1063.itm(0)} -attr vt d
+load net {ACC1-2:exs#1063.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1063.itm} 2 {ACC1-2:exs#1063.itm(0)} {ACC1-2:exs#1063.itm(1)} -attr xrf 63362 -attr oid 552 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1063.itm}
+load net {ACC1-1:exs#1035.itm(0)} -attr vt d
+load net {ACC1-1:exs#1035.itm(1)} -attr vt d
+load net {ACC1-1:exs#1035.itm(2)} -attr vt d
+load net {ACC1-1:exs#1035.itm(3)} -attr vt d
+load net {ACC1-1:exs#1035.itm(4)} -attr vt d
+load net {ACC1-1:exs#1035.itm(5)} -attr vt d
+load net {ACC1-1:exs#1035.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#1035.itm} 7 {ACC1-1:exs#1035.itm(0)} {ACC1-1:exs#1035.itm(1)} {ACC1-1:exs#1035.itm(2)} {ACC1-1:exs#1035.itm(3)} {ACC1-1:exs#1035.itm(4)} {ACC1-1:exs#1035.itm(5)} {ACC1-1:exs#1035.itm(6)} -attr xrf 63363 -attr oid 553 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1-1:conc#510.itm(0)} -attr vt d
+load net {ACC1-1:conc#510.itm(1)} -attr vt d
+load net {ACC1-1:conc#510.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#510.itm} 3 {ACC1-1:conc#510.itm(0)} {ACC1-1:conc#510.itm(1)} {ACC1-1:conc#510.itm(2)} -attr xrf 63364 -attr oid 554 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#510.itm}
+load net {ACC1-1:exs#48.itm(0)} -attr vt d
+load net {ACC1-1:exs#48.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#48.itm} 2 {ACC1-1:exs#48.itm(0)} {ACC1-1:exs#48.itm(1)} -attr xrf 63365 -attr oid 555 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#48.itm}
+load net {ACC1:acc#628.itm(0)} -attr vt d
+load net {ACC1:acc#628.itm(1)} -attr vt d
+load net {ACC1:acc#628.itm(2)} -attr vt d
+load net {ACC1:acc#628.itm(3)} -attr vt d
+load net {ACC1:acc#628.itm(4)} -attr vt d
+load net {ACC1:acc#628.itm(5)} -attr vt d
+load net {ACC1:acc#628.itm(6)} -attr vt d
+load net {ACC1:acc#628.itm(7)} -attr vt d
+load netBundle {ACC1:acc#628.itm} 8 {ACC1:acc#628.itm(0)} {ACC1:acc#628.itm(1)} {ACC1:acc#628.itm(2)} {ACC1:acc#628.itm(3)} {ACC1:acc#628.itm(4)} {ACC1:acc#628.itm(5)} {ACC1:acc#628.itm(6)} {ACC1:acc#628.itm(7)} -attr xrf 63366 -attr oid 556 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {exs#96.itm(0)} -attr vt d
+load net {exs#96.itm(1)} -attr vt d
+load net {exs#96.itm(2)} -attr vt d
+load net {exs#96.itm(3)} -attr vt d
+load net {exs#96.itm(4)} -attr vt d
+load net {exs#96.itm(5)} -attr vt d
+load net {exs#96.itm(6)} -attr vt d
+load netBundle {exs#96.itm} 7 {exs#96.itm(0)} {exs#96.itm(1)} {exs#96.itm(2)} {exs#96.itm(3)} {exs#96.itm(4)} {exs#96.itm(5)} {exs#96.itm(6)} -attr xrf 63367 -attr oid 557 -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {conc#953.itm(0)} -attr vt d
+load net {conc#953.itm(1)} -attr vt d
+load net {conc#953.itm(2)} -attr vt d
+load net {conc#953.itm(3)} -attr vt d
+load netBundle {conc#953.itm} 4 {conc#953.itm(0)} {conc#953.itm(1)} {conc#953.itm(2)} {conc#953.itm(3)} -attr xrf 63368 -attr oid 558 -attr vt d -attr @path {/sobel/sobel:core/conc#953.itm}
+load net {ACC1-1:exs#1068.itm(0)} -attr vt d
+load net {ACC1-1:exs#1068.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1068.itm} 2 {ACC1-1:exs#1068.itm(0)} {ACC1-1:exs#1068.itm(1)} -attr xrf 63369 -attr oid 559 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1068.itm}
+load net {ACC1-1:exs#1051.itm(0)} -attr vt d
+load net {ACC1-1:exs#1051.itm(1)} -attr vt d
+load net {ACC1-1:exs#1051.itm(2)} -attr vt d
+load net {ACC1-1:exs#1051.itm(3)} -attr vt d
+load net {ACC1-1:exs#1051.itm(4)} -attr vt d
+load net {ACC1-1:exs#1051.itm(5)} -attr vt d
+load net {ACC1-1:exs#1051.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#1051.itm} 7 {ACC1-1:exs#1051.itm(0)} {ACC1-1:exs#1051.itm(1)} {ACC1-1:exs#1051.itm(2)} {ACC1-1:exs#1051.itm(3)} {ACC1-1:exs#1051.itm(4)} {ACC1-1:exs#1051.itm(5)} {ACC1-1:exs#1051.itm(6)} -attr xrf 63370 -attr oid 560 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {ACC1-1:conc#602.itm(0)} -attr vt d
+load net {ACC1-1:conc#602.itm(1)} -attr vt d
+load net {ACC1-1:conc#602.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#602.itm} 3 {ACC1-1:conc#602.itm(0)} {ACC1-1:conc#602.itm(1)} {ACC1-1:conc#602.itm(2)} -attr xrf 63371 -attr oid 561 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#602.itm}
+load net {ACC1-1:exs#1052.itm(0)} -attr vt d
+load net {ACC1-1:exs#1052.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1052.itm} 2 {ACC1-1:exs#1052.itm(0)} {ACC1-1:exs#1052.itm(1)} -attr xrf 63372 -attr oid 562 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1052.itm}
+load net {ACC1:acc#655.itm(0)} -attr vt d
+load net {ACC1:acc#655.itm(1)} -attr vt d
+load net {ACC1:acc#655.itm(2)} -attr vt d
+load net {ACC1:acc#655.itm(3)} -attr vt d
+load net {ACC1:acc#655.itm(4)} -attr vt d
+load net {ACC1:acc#655.itm(5)} -attr vt d
+load net {ACC1:acc#655.itm(6)} -attr vt d
+load net {ACC1:acc#655.itm(7)} -attr vt d
+load net {ACC1:acc#655.itm(8)} -attr vt d
+load net {ACC1:acc#655.itm(9)} -attr vt d
+load net {ACC1:acc#655.itm(10)} -attr vt d
+load net {ACC1:acc#655.itm(11)} -attr vt d
+load netBundle {ACC1:acc#655.itm} 12 {ACC1:acc#655.itm(0)} {ACC1:acc#655.itm(1)} {ACC1:acc#655.itm(2)} {ACC1:acc#655.itm(3)} {ACC1:acc#655.itm(4)} {ACC1:acc#655.itm(5)} {ACC1:acc#655.itm(6)} {ACC1:acc#655.itm(7)} {ACC1:acc#655.itm(8)} {ACC1:acc#655.itm(9)} {ACC1:acc#655.itm(10)} {ACC1:acc#655.itm(11)} -attr xrf 63373 -attr oid 563 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#650.itm(0)} -attr vt d
+load net {ACC1:acc#650.itm(1)} -attr vt d
+load net {ACC1:acc#650.itm(2)} -attr vt d
+load net {ACC1:acc#650.itm(3)} -attr vt d
+load net {ACC1:acc#650.itm(4)} -attr vt d
+load net {ACC1:acc#650.itm(5)} -attr vt d
+load net {ACC1:acc#650.itm(6)} -attr vt d
+load net {ACC1:acc#650.itm(7)} -attr vt d
+load net {ACC1:acc#650.itm(8)} -attr vt d
+load net {ACC1:acc#650.itm(9)} -attr vt d
+load net {ACC1:acc#650.itm(10)} -attr vt d
+load netBundle {ACC1:acc#650.itm} 11 {ACC1:acc#650.itm(0)} {ACC1:acc#650.itm(1)} {ACC1:acc#650.itm(2)} {ACC1:acc#650.itm(3)} {ACC1:acc#650.itm(4)} {ACC1:acc#650.itm(5)} {ACC1:acc#650.itm(6)} {ACC1:acc#650.itm(7)} {ACC1:acc#650.itm(8)} {ACC1:acc#650.itm(9)} {ACC1:acc#650.itm(10)} -attr xrf 63374 -attr oid 564 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {conc#955.itm(0)} -attr vt d
+load net {conc#955.itm(1)} -attr vt d
+load net {conc#955.itm(2)} -attr vt d
+load net {conc#955.itm(3)} -attr vt d
+load net {conc#955.itm(4)} -attr vt d
+load net {conc#955.itm(5)} -attr vt d
+load net {conc#955.itm(6)} -attr vt d
+load net {conc#955.itm(7)} -attr vt d
+load net {conc#955.itm(8)} -attr vt d
+load net {conc#955.itm(9)} -attr vt d
+load netBundle {conc#955.itm} 10 {conc#955.itm(0)} {conc#955.itm(1)} {conc#955.itm(2)} {conc#955.itm(3)} {conc#955.itm(4)} {conc#955.itm(5)} {conc#955.itm(6)} {conc#955.itm(7)} {conc#955.itm(8)} {conc#955.itm(9)} -attr xrf 63375 -attr oid 565 -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {ACC1:acc#645.itm(0)} -attr vt d
+load net {ACC1:acc#645.itm(1)} -attr vt d
+load net {ACC1:acc#645.itm(2)} -attr vt d
+load net {ACC1:acc#645.itm(3)} -attr vt d
+load net {ACC1:acc#645.itm(4)} -attr vt d
+load net {ACC1:acc#645.itm(5)} -attr vt d
+load net {ACC1:acc#645.itm(6)} -attr vt d
+load net {ACC1:acc#645.itm(7)} -attr vt d
+load net {ACC1:acc#645.itm(8)} -attr vt d
+load netBundle {ACC1:acc#645.itm} 9 {ACC1:acc#645.itm(0)} {ACC1:acc#645.itm(1)} {ACC1:acc#645.itm(2)} {ACC1:acc#645.itm(3)} {ACC1:acc#645.itm(4)} {ACC1:acc#645.itm(5)} {ACC1:acc#645.itm(6)} {ACC1:acc#645.itm(7)} {ACC1:acc#645.itm(8)} -attr xrf 63376 -attr oid 566 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#638.itm(0)} -attr vt d
+load net {ACC1:acc#638.itm(1)} -attr vt d
+load net {ACC1:acc#638.itm(2)} -attr vt d
+load net {ACC1:acc#638.itm(3)} -attr vt d
+load net {ACC1:acc#638.itm(4)} -attr vt d
+load net {ACC1:acc#638.itm(5)} -attr vt d
+load net {ACC1:acc#638.itm(6)} -attr vt d
+load net {ACC1:acc#638.itm(7)} -attr vt d
+load netBundle {ACC1:acc#638.itm} 8 {ACC1:acc#638.itm(0)} {ACC1:acc#638.itm(1)} {ACC1:acc#638.itm(2)} {ACC1:acc#638.itm(3)} {ACC1:acc#638.itm(4)} {ACC1:acc#638.itm(5)} {ACC1:acc#638.itm(6)} {ACC1:acc#638.itm(7)} -attr xrf 63377 -attr oid 567 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {conc#956.itm(0)} -attr vt d
+load net {conc#956.itm(1)} -attr vt d
+load net {conc#956.itm(2)} -attr vt d
+load net {conc#956.itm(3)} -attr vt d
+load net {conc#956.itm(4)} -attr vt d
+load net {conc#956.itm(5)} -attr vt d
+load net {conc#956.itm(6)} -attr vt d
+load net {conc#956.itm(7)} -attr vt d
+load netBundle {conc#956.itm} 8 {conc#956.itm(0)} {conc#956.itm(1)} {conc#956.itm(2)} {conc#956.itm(3)} {conc#956.itm(4)} {conc#956.itm(5)} {conc#956.itm(6)} {conc#956.itm(7)} -attr xrf 63378 -attr oid 568 -attr vt d -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {ACC1:acc#626.itm(0)} -attr vt d
+load net {ACC1:acc#626.itm(1)} -attr vt d
+load net {ACC1:acc#626.itm(2)} -attr vt d
+load net {ACC1:acc#626.itm(3)} -attr vt d
+load net {ACC1:acc#626.itm(4)} -attr vt d
+load net {ACC1:acc#626.itm(5)} -attr vt d
+load net {ACC1:acc#626.itm(6)} -attr vt d
+load netBundle {ACC1:acc#626.itm} 7 {ACC1:acc#626.itm(0)} {ACC1:acc#626.itm(1)} {ACC1:acc#626.itm(2)} {ACC1:acc#626.itm(3)} {ACC1:acc#626.itm(4)} {ACC1:acc#626.itm(5)} {ACC1:acc#626.itm(6)} -attr xrf 63379 -attr oid 569 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#613.itm(0)} -attr vt d
+load net {ACC1:acc#613.itm(1)} -attr vt d
+load net {ACC1:acc#613.itm(2)} -attr vt d
+load net {ACC1:acc#613.itm(3)} -attr vt d
+load net {ACC1:acc#613.itm(4)} -attr vt d
+load net {ACC1:acc#613.itm(5)} -attr vt d
+load netBundle {ACC1:acc#613.itm} 6 {ACC1:acc#613.itm(0)} {ACC1:acc#613.itm(1)} {ACC1:acc#613.itm(2)} {ACC1:acc#613.itm(3)} {ACC1:acc#613.itm(4)} {ACC1:acc#613.itm(5)} -attr xrf 63380 -attr oid 570 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#597.itm(0)} -attr vt d
+load net {ACC1:acc#597.itm(1)} -attr vt d
+load net {ACC1:acc#597.itm(2)} -attr vt d
+load net {ACC1:acc#597.itm(3)} -attr vt d
+load net {ACC1:acc#597.itm(4)} -attr vt d
+load netBundle {ACC1:acc#597.itm} 5 {ACC1:acc#597.itm(0)} {ACC1:acc#597.itm(1)} {ACC1:acc#597.itm(2)} {ACC1:acc#597.itm(3)} {ACC1:acc#597.itm(4)} -attr xrf 63381 -attr oid 571 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#564.itm(0)} -attr vt d
+load net {ACC1:acc#564.itm(1)} -attr vt d
+load net {ACC1:acc#564.itm(2)} -attr vt d
+load net {ACC1:acc#564.itm(3)} -attr vt d
+load netBundle {ACC1:acc#564.itm} 4 {ACC1:acc#564.itm(0)} {ACC1:acc#564.itm(1)} {ACC1:acc#564.itm(2)} {ACC1:acc#564.itm(3)} -attr xrf 63382 -attr oid 572 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#563.itm(0)} -attr vt d
+load net {ACC1:acc#563.itm(1)} -attr vt d
+load net {ACC1:acc#563.itm(2)} -attr vt d
+load net {ACC1:acc#563.itm(3)} -attr vt d
+load netBundle {ACC1:acc#563.itm} 4 {ACC1:acc#563.itm(0)} {ACC1:acc#563.itm(1)} {ACC1:acc#563.itm(2)} {ACC1:acc#563.itm(3)} -attr xrf 63383 -attr oid 573 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#507.itm(0)} -attr vt d
+load net {ACC1:acc#507.itm(1)} -attr vt d
+load net {ACC1:acc#507.itm(2)} -attr vt d
+load netBundle {ACC1:acc#507.itm} 3 {ACC1:acc#507.itm(0)} {ACC1:acc#507.itm(1)} {ACC1:acc#507.itm(2)} -attr xrf 63384 -attr oid 574 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load net {ACC1-3:exs#1058.itm(0)} -attr vt d
+load net {ACC1-3:exs#1058.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1058.itm} 2 {ACC1-3:exs#1058.itm(0)} {ACC1-3:exs#1058.itm(1)} -attr xrf 63385 -attr oid 575 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1058.itm}
+load net {ACC1-3:exs#1031.itm(0)} -attr vt d
+load net {ACC1-3:exs#1031.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1031.itm} 2 {ACC1-3:exs#1031.itm(0)} {ACC1-3:exs#1031.itm(1)} -attr xrf 63386 -attr oid 576 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1031.itm}
+load net {ACC1:acc#596.itm(0)} -attr vt d
+load net {ACC1:acc#596.itm(1)} -attr vt d
+load net {ACC1:acc#596.itm(2)} -attr vt d
+load net {ACC1:acc#596.itm(3)} -attr vt d
+load net {ACC1:acc#596.itm(4)} -attr vt d
+load netBundle {ACC1:acc#596.itm} 5 {ACC1:acc#596.itm(0)} {ACC1:acc#596.itm(1)} {ACC1:acc#596.itm(2)} {ACC1:acc#596.itm(3)} {ACC1:acc#596.itm(4)} -attr xrf 63387 -attr oid 577 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#561.itm(0)} -attr vt d
+load net {ACC1:acc#561.itm(1)} -attr vt d
+load net {ACC1:acc#561.itm(2)} -attr vt d
+load net {ACC1:acc#561.itm(3)} -attr vt d
+load netBundle {ACC1:acc#561.itm} 4 {ACC1:acc#561.itm(0)} {ACC1:acc#561.itm(1)} {ACC1:acc#561.itm(2)} {ACC1:acc#561.itm(3)} -attr xrf 63388 -attr oid 578 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#612.itm(0)} -attr vt d
+load net {ACC1:acc#612.itm(1)} -attr vt d
+load net {ACC1:acc#612.itm(2)} -attr vt d
+load net {ACC1:acc#612.itm(3)} -attr vt d
+load net {ACC1:acc#612.itm(4)} -attr vt d
+load net {ACC1:acc#612.itm(5)} -attr vt d
+load netBundle {ACC1:acc#612.itm} 6 {ACC1:acc#612.itm(0)} {ACC1:acc#612.itm(1)} {ACC1:acc#612.itm(2)} {ACC1:acc#612.itm(3)} {ACC1:acc#612.itm(4)} {ACC1:acc#612.itm(5)} -attr xrf 63389 -attr oid 579 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#595.itm(0)} -attr vt d
+load net {ACC1:acc#595.itm(1)} -attr vt d
+load net {ACC1:acc#595.itm(2)} -attr vt d
+load net {ACC1:acc#595.itm(3)} -attr vt d
+load net {ACC1:acc#595.itm(4)} -attr vt d
+load netBundle {ACC1:acc#595.itm} 5 {ACC1:acc#595.itm(0)} {ACC1:acc#595.itm(1)} {ACC1:acc#595.itm(2)} {ACC1:acc#595.itm(3)} {ACC1:acc#595.itm(4)} -attr xrf 63390 -attr oid 580 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#559.itm(0)} -attr vt d
+load net {ACC1:acc#559.itm(1)} -attr vt d
+load net {ACC1:acc#559.itm(2)} -attr vt d
+load net {ACC1:acc#559.itm(3)} -attr vt d
+load netBundle {ACC1:acc#559.itm} 4 {ACC1:acc#559.itm(0)} {ACC1:acc#559.itm(1)} {ACC1:acc#559.itm(2)} {ACC1:acc#559.itm(3)} -attr xrf 63391 -attr oid 581 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#499.itm(0)} -attr vt d
+load net {ACC1:acc#499.itm(1)} -attr vt d
+load net {ACC1:acc#499.itm(2)} -attr vt d
+load netBundle {ACC1:acc#499.itm} 3 {ACC1:acc#499.itm(0)} {ACC1:acc#499.itm(1)} {ACC1:acc#499.itm(2)} -attr xrf 63392 -attr oid 582 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load net {ACC1-3:exs#1053.itm(0)} -attr vt d
+load net {ACC1-3:exs#1053.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1053.itm} 2 {ACC1-3:exs#1053.itm(0)} {ACC1-3:exs#1053.itm(1)} -attr xrf 63393 -attr oid 583 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1053.itm}
+load net {ACC1-3:exs#72.itm(0)} -attr vt d
+load net {ACC1-3:exs#72.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#72.itm} 2 {ACC1-3:exs#72.itm(0)} {ACC1-3:exs#72.itm(1)} -attr xrf 63394 -attr oid 584 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#72.itm}
+load net {ACC1:acc#498.itm(0)} -attr vt d
+load net {ACC1:acc#498.itm(1)} -attr vt d
+load net {ACC1:acc#498.itm(2)} -attr vt d
+load netBundle {ACC1:acc#498.itm} 3 {ACC1:acc#498.itm(0)} {ACC1:acc#498.itm(1)} {ACC1:acc#498.itm(2)} -attr xrf 63395 -attr oid 585 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load net {ACC1-3:exs#73.itm(0)} -attr vt d
+load net {ACC1-3:exs#73.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#73.itm} 2 {ACC1-3:exs#73.itm(0)} {ACC1-3:exs#73.itm(1)} -attr xrf 63396 -attr oid 586 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#73.itm}
+load net {ACC1-3:exs#1054.itm(0)} -attr vt d
+load net {ACC1-3:exs#1054.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1054.itm} 2 {ACC1-3:exs#1054.itm(0)} {ACC1-3:exs#1054.itm(1)} -attr xrf 63397 -attr oid 587 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1054.itm}
+load net {ACC1:acc#594.itm(0)} -attr vt d
+load net {ACC1:acc#594.itm(1)} -attr vt d
+load net {ACC1:acc#594.itm(2)} -attr vt d
+load net {ACC1:acc#594.itm(3)} -attr vt d
+load net {ACC1:acc#594.itm(4)} -attr vt d
+load netBundle {ACC1:acc#594.itm} 5 {ACC1:acc#594.itm(0)} {ACC1:acc#594.itm(1)} {ACC1:acc#594.itm(2)} {ACC1:acc#594.itm(3)} {ACC1:acc#594.itm(4)} -attr xrf 63398 -attr oid 588 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#637.itm(0)} -attr vt d
+load net {ACC1:acc#637.itm(1)} -attr vt d
+load net {ACC1:acc#637.itm(2)} -attr vt d
+load net {ACC1:acc#637.itm(3)} -attr vt d
+load net {ACC1:acc#637.itm(4)} -attr vt d
+load net {ACC1:acc#637.itm(5)} -attr vt d
+load net {ACC1:acc#637.itm(6)} -attr vt d
+load net {ACC1:acc#637.itm(7)} -attr vt d
+load netBundle {ACC1:acc#637.itm} 8 {ACC1:acc#637.itm(0)} {ACC1:acc#637.itm(1)} {ACC1:acc#637.itm(2)} {ACC1:acc#637.itm(3)} {ACC1:acc#637.itm(4)} {ACC1:acc#637.itm(5)} {ACC1:acc#637.itm(6)} {ACC1:acc#637.itm(7)} -attr xrf 63399 -attr oid 589 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#625.itm(0)} -attr vt d
+load net {ACC1:acc#625.itm(1)} -attr vt d
+load net {ACC1:acc#625.itm(2)} -attr vt d
+load net {ACC1:acc#625.itm(3)} -attr vt d
+load net {ACC1:acc#625.itm(4)} -attr vt d
+load net {ACC1:acc#625.itm(5)} -attr vt d
+load net {ACC1:acc#625.itm(6)} -attr vt d
+load netBundle {ACC1:acc#625.itm} 7 {ACC1:acc#625.itm(0)} {ACC1:acc#625.itm(1)} {ACC1:acc#625.itm(2)} {ACC1:acc#625.itm(3)} {ACC1:acc#625.itm(4)} {ACC1:acc#625.itm(5)} {ACC1:acc#625.itm(6)} -attr xrf 63400 -attr oid 590 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#611.itm(0)} -attr vt d
+load net {ACC1:acc#611.itm(1)} -attr vt d
+load net {ACC1:acc#611.itm(2)} -attr vt d
+load net {ACC1:acc#611.itm(3)} -attr vt d
+load net {ACC1:acc#611.itm(4)} -attr vt d
+load net {ACC1:acc#611.itm(5)} -attr vt d
+load netBundle {ACC1:acc#611.itm} 6 {ACC1:acc#611.itm(0)} {ACC1:acc#611.itm(1)} {ACC1:acc#611.itm(2)} {ACC1:acc#611.itm(3)} {ACC1:acc#611.itm(4)} {ACC1:acc#611.itm(5)} -attr xrf 63401 -attr oid 591 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#593.itm(0)} -attr vt d
+load net {ACC1:acc#593.itm(1)} -attr vt d
+load net {ACC1:acc#593.itm(2)} -attr vt d
+load net {ACC1:acc#593.itm(3)} -attr vt d
+load net {ACC1:acc#593.itm(4)} -attr vt d
+load netBundle {ACC1:acc#593.itm} 5 {ACC1:acc#593.itm(0)} {ACC1:acc#593.itm(1)} {ACC1:acc#593.itm(2)} {ACC1:acc#593.itm(3)} {ACC1:acc#593.itm(4)} -attr xrf 63402 -attr oid 592 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#556.itm(0)} -attr vt d
+load net {ACC1:acc#556.itm(1)} -attr vt d
+load net {ACC1:acc#556.itm(2)} -attr vt d
+load net {ACC1:acc#556.itm(3)} -attr vt d
+load netBundle {ACC1:acc#556.itm} 4 {ACC1:acc#556.itm(0)} {ACC1:acc#556.itm(1)} {ACC1:acc#556.itm(2)} {ACC1:acc#556.itm(3)} -attr xrf 63403 -attr oid 593 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#555.itm(0)} -attr vt d
+load net {ACC1:acc#555.itm(1)} -attr vt d
+load net {ACC1:acc#555.itm(2)} -attr vt d
+load net {ACC1:acc#555.itm(3)} -attr vt d
+load netBundle {ACC1:acc#555.itm} 4 {ACC1:acc#555.itm(0)} {ACC1:acc#555.itm(1)} {ACC1:acc#555.itm(2)} {ACC1:acc#555.itm(3)} -attr xrf 63404 -attr oid 594 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#592.itm(0)} -attr vt d
+load net {ACC1:acc#592.itm(1)} -attr vt d
+load net {ACC1:acc#592.itm(2)} -attr vt d
+load net {ACC1:acc#592.itm(3)} -attr vt d
+load net {ACC1:acc#592.itm(4)} -attr vt d
+load netBundle {ACC1:acc#592.itm} 5 {ACC1:acc#592.itm(0)} {ACC1:acc#592.itm(1)} {ACC1:acc#592.itm(2)} {ACC1:acc#592.itm(3)} {ACC1:acc#592.itm(4)} -attr xrf 63405 -attr oid 595 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#554.itm(0)} -attr vt d
+load net {ACC1:acc#554.itm(1)} -attr vt d
+load net {ACC1:acc#554.itm(2)} -attr vt d
+load net {ACC1:acc#554.itm(3)} -attr vt d
+load netBundle {ACC1:acc#554.itm} 4 {ACC1:acc#554.itm(0)} {ACC1:acc#554.itm(1)} {ACC1:acc#554.itm(2)} {ACC1:acc#554.itm(3)} -attr xrf 63406 -attr oid 596 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#488.itm(0)} -attr vt d
+load net {ACC1:acc#488.itm(1)} -attr vt d
+load net {ACC1:acc#488.itm(2)} -attr vt d
+load netBundle {ACC1:acc#488.itm} 3 {ACC1:acc#488.itm(0)} {ACC1:acc#488.itm(1)} {ACC1:acc#488.itm(2)} -attr xrf 63407 -attr oid 597 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load net {ACC1-2:exs#90.itm(0)} -attr vt d
+load net {ACC1-2:exs#90.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#90.itm} 2 {ACC1-2:exs#90.itm(0)} {ACC1-2:exs#90.itm(1)} -attr xrf 63408 -attr oid 598 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#90.itm}
+load net {ACC1-2:exs#91.itm(0)} -attr vt d
+load net {ACC1-2:exs#91.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#91.itm} 2 {ACC1-2:exs#91.itm(0)} {ACC1-2:exs#91.itm(1)} -attr xrf 63409 -attr oid 599 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#91.itm}
+load net {ACC1:acc#487.itm(0)} -attr vt d
+load net {ACC1:acc#487.itm(1)} -attr vt d
+load net {ACC1:acc#487.itm(2)} -attr vt d
+load netBundle {ACC1:acc#487.itm} 3 {ACC1:acc#487.itm(0)} {ACC1:acc#487.itm(1)} {ACC1:acc#487.itm(2)} -attr xrf 63410 -attr oid 600 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load net {ACC1-2:exs#92.itm(0)} -attr vt d
+load net {ACC1-2:exs#92.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#92.itm} 2 {ACC1-2:exs#92.itm(0)} {ACC1-2:exs#92.itm(1)} -attr xrf 63411 -attr oid 601 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#92.itm}
+load net {ACC1-2:exs#1056.itm(0)} -attr vt d
+load net {ACC1-2:exs#1056.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1056.itm} 2 {ACC1-2:exs#1056.itm(0)} {ACC1-2:exs#1056.itm(1)} -attr xrf 63412 -attr oid 602 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1056.itm}
+load net {ACC1:acc#610.itm(0)} -attr vt d
+load net {ACC1:acc#610.itm(1)} -attr vt d
+load net {ACC1:acc#610.itm(2)} -attr vt d
+load net {ACC1:acc#610.itm(3)} -attr vt d
+load net {ACC1:acc#610.itm(4)} -attr vt d
+load net {ACC1:acc#610.itm(5)} -attr vt d
+load netBundle {ACC1:acc#610.itm} 6 {ACC1:acc#610.itm(0)} {ACC1:acc#610.itm(1)} {ACC1:acc#610.itm(2)} {ACC1:acc#610.itm(3)} {ACC1:acc#610.itm(4)} {ACC1:acc#610.itm(5)} -attr xrf 63413 -attr oid 603 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#591.itm(0)} -attr vt d
+load net {ACC1:acc#591.itm(1)} -attr vt d
+load net {ACC1:acc#591.itm(2)} -attr vt d
+load net {ACC1:acc#591.itm(3)} -attr vt d
+load net {ACC1:acc#591.itm(4)} -attr vt d
+load netBundle {ACC1:acc#591.itm} 5 {ACC1:acc#591.itm(0)} {ACC1:acc#591.itm(1)} {ACC1:acc#591.itm(2)} {ACC1:acc#591.itm(3)} {ACC1:acc#591.itm(4)} -attr xrf 63414 -attr oid 604 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#551.itm(0)} -attr vt d
+load net {ACC1:acc#551.itm(1)} -attr vt d
+load net {ACC1:acc#551.itm(2)} -attr vt d
+load net {ACC1:acc#551.itm(3)} -attr vt d
+load netBundle {ACC1:acc#551.itm} 4 {ACC1:acc#551.itm(0)} {ACC1:acc#551.itm(1)} {ACC1:acc#551.itm(2)} {ACC1:acc#551.itm(3)} -attr xrf 63415 -attr oid 605 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#482.itm(0)} -attr vt d
+load net {ACC1:acc#482.itm(1)} -attr vt d
+load net {ACC1:acc#482.itm(2)} -attr vt d
+load netBundle {ACC1:acc#482.itm} 3 {ACC1:acc#482.itm(0)} {ACC1:acc#482.itm(1)} {ACC1:acc#482.itm(2)} -attr xrf 63416 -attr oid 606 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load net {ACC1-2:exs#1057.itm(0)} -attr vt d
+load net {ACC1-2:exs#1057.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1057.itm} 2 {ACC1-2:exs#1057.itm(0)} {ACC1-2:exs#1057.itm(1)} -attr xrf 63417 -attr oid 607 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1057.itm}
+load net {ACC1-2:exs#963.itm(0)} -attr vt d
+load net {ACC1-2:exs#963.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#963.itm} 2 {ACC1-2:exs#963.itm(0)} {ACC1-2:exs#963.itm(1)} -attr xrf 63418 -attr oid 608 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#963.itm}
+load net {ACC1:acc#590.itm(0)} -attr vt d
+load net {ACC1:acc#590.itm(1)} -attr vt d
+load net {ACC1:acc#590.itm(2)} -attr vt d
+load net {ACC1:acc#590.itm(3)} -attr vt d
+load net {ACC1:acc#590.itm(4)} -attr vt d
+load netBundle {ACC1:acc#590.itm} 5 {ACC1:acc#590.itm(0)} {ACC1:acc#590.itm(1)} {ACC1:acc#590.itm(2)} {ACC1:acc#590.itm(3)} {ACC1:acc#590.itm(4)} -attr xrf 63419 -attr oid 609 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#550.itm(0)} -attr vt d
+load net {ACC1:acc#550.itm(1)} -attr vt d
+load net {ACC1:acc#550.itm(2)} -attr vt d
+load net {ACC1:acc#550.itm(3)} -attr vt d
+load netBundle {ACC1:acc#550.itm} 4 {ACC1:acc#550.itm(0)} {ACC1:acc#550.itm(1)} {ACC1:acc#550.itm(2)} {ACC1:acc#550.itm(3)} -attr xrf 63420 -attr oid 610 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:slc#147.itm(0)} -attr vt d
+load net {ACC1:slc#147.itm(1)} -attr vt d
+load net {ACC1:slc#147.itm(2)} -attr vt d
+load netBundle {ACC1:slc#147.itm} 3 {ACC1:slc#147.itm(0)} {ACC1:slc#147.itm(1)} {ACC1:slc#147.itm(2)} -attr xrf 63421 -attr oid 611 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#147.itm}
+load net {ACC1:acc#479.itm(0)} -attr vt d
+load net {ACC1:acc#479.itm(1)} -attr vt d
+load net {ACC1:acc#479.itm(2)} -attr vt d
+load net {ACC1:acc#479.itm(3)} -attr vt d
+load netBundle {ACC1:acc#479.itm} 4 {ACC1:acc#479.itm(0)} {ACC1:acc#479.itm(1)} {ACC1:acc#479.itm(2)} {ACC1:acc#479.itm(3)} -attr xrf 63422 -attr oid 612 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#479.itm}
+load net {exs#97.itm(0)} -attr vt d
+load net {exs#97.itm(1)} -attr vt d
+load net {exs#97.itm(2)} -attr vt d
+load netBundle {exs#97.itm} 3 {exs#97.itm(0)} {exs#97.itm(1)} {exs#97.itm(2)} -attr xrf 63423 -attr oid 613 -attr vt d -attr @path {/sobel/sobel:core/exs#97.itm}
+load net {conc#957.itm(0)} -attr vt d
+load net {conc#957.itm(1)} -attr vt d
+load netBundle {conc#957.itm} 2 {conc#957.itm(0)} {conc#957.itm(1)} -attr xrf 63424 -attr oid 614 -attr vt d -attr @path {/sobel/sobel:core/conc#957.itm}
+load net {ACC1:exs#1552.itm(0)} -attr vt d
+load net {ACC1:exs#1552.itm(1)} -attr vt d
+load net {ACC1:exs#1552.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1552.itm} 3 {ACC1:exs#1552.itm(0)} {ACC1:exs#1552.itm(1)} {ACC1:exs#1552.itm(2)} -attr xrf 63425 -attr oid 615 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1552.itm}
+load net {ACC1:conc#1417.itm(0)} -attr vt d
+load net {ACC1:conc#1417.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1417.itm} 2 {ACC1:conc#1417.itm(0)} {ACC1:conc#1417.itm(1)} -attr xrf 63426 -attr oid 616 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1417.itm}
+load net {ACC1:acc#549.itm(0)} -attr vt d
+load net {ACC1:acc#549.itm(1)} -attr vt d
+load net {ACC1:acc#549.itm(2)} -attr vt d
+load net {ACC1:acc#549.itm(3)} -attr vt d
+load netBundle {ACC1:acc#549.itm} 4 {ACC1:acc#549.itm(0)} {ACC1:acc#549.itm(1)} {ACC1:acc#549.itm(2)} {ACC1:acc#549.itm(3)} -attr xrf 63427 -attr oid 617 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:slc#146.itm(0)} -attr vt d
+load net {ACC1:slc#146.itm(1)} -attr vt d
+load net {ACC1:slc#146.itm(2)} -attr vt d
+load netBundle {ACC1:slc#146.itm} 3 {ACC1:slc#146.itm(0)} {ACC1:slc#146.itm(1)} {ACC1:slc#146.itm(2)} -attr xrf 63428 -attr oid 618 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#146.itm}
+load net {ACC1:acc#478.itm(0)} -attr vt d
+load net {ACC1:acc#478.itm(1)} -attr vt d
+load net {ACC1:acc#478.itm(2)} -attr vt d
+load net {ACC1:acc#478.itm(3)} -attr vt d
+load netBundle {ACC1:acc#478.itm} 4 {ACC1:acc#478.itm(0)} {ACC1:acc#478.itm(1)} {ACC1:acc#478.itm(2)} {ACC1:acc#478.itm(3)} -attr xrf 63429 -attr oid 619 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#478.itm}
+load net {exs#98.itm(0)} -attr vt d
+load net {exs#98.itm(1)} -attr vt d
+load net {exs#98.itm(2)} -attr vt d
+load netBundle {exs#98.itm} 3 {exs#98.itm(0)} {exs#98.itm(1)} {exs#98.itm(2)} -attr xrf 63430 -attr oid 620 -attr vt d -attr @path {/sobel/sobel:core/exs#98.itm}
+load net {conc#959.itm(0)} -attr vt d
+load net {conc#959.itm(1)} -attr vt d
+load netBundle {conc#959.itm} 2 {conc#959.itm(0)} {conc#959.itm(1)} -attr xrf 63431 -attr oid 621 -attr vt d -attr @path {/sobel/sobel:core/conc#959.itm}
+load net {ACC1:exs#1554.itm(0)} -attr vt d
+load net {ACC1:exs#1554.itm(1)} -attr vt d
+load net {ACC1:exs#1554.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1554.itm} 3 {ACC1:exs#1554.itm(0)} {ACC1:exs#1554.itm(1)} {ACC1:exs#1554.itm(2)} -attr xrf 63432 -attr oid 622 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1554.itm}
+load net {ACC1:conc#1415.itm(0)} -attr vt d
+load net {ACC1:conc#1415.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1415.itm} 2 {ACC1:conc#1415.itm(0)} {ACC1:conc#1415.itm(1)} -attr xrf 63433 -attr oid 623 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1415.itm}
+load net {ACC1:slc#145.itm(0)} -attr vt d
+load net {ACC1:slc#145.itm(1)} -attr vt d
+load net {ACC1:slc#145.itm(2)} -attr vt d
+load netBundle {ACC1:slc#145.itm} 3 {ACC1:slc#145.itm(0)} {ACC1:slc#145.itm(1)} {ACC1:slc#145.itm(2)} -attr xrf 63434 -attr oid 624 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#145.itm}
+load net {ACC1:acc#477.itm(0)} -attr vt d
+load net {ACC1:acc#477.itm(1)} -attr vt d
+load net {ACC1:acc#477.itm(2)} -attr vt d
+load net {ACC1:acc#477.itm(3)} -attr vt d
+load netBundle {ACC1:acc#477.itm} 4 {ACC1:acc#477.itm(0)} {ACC1:acc#477.itm(1)} {ACC1:acc#477.itm(2)} {ACC1:acc#477.itm(3)} -attr xrf 63435 -attr oid 625 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#477.itm}
+load net {exs#77.itm(0)} -attr vt d
+load net {exs#77.itm(1)} -attr vt d
+load net {exs#77.itm(2)} -attr vt d
+load netBundle {exs#77.itm} 3 {exs#77.itm(0)} {exs#77.itm(1)} {exs#77.itm(2)} -attr xrf 63436 -attr oid 626 -attr vt d -attr @path {/sobel/sobel:core/exs#77.itm}
+load net {conc#961.itm(0)} -attr vt d
+load net {conc#961.itm(1)} -attr vt d
+load netBundle {conc#961.itm} 2 {conc#961.itm(0)} {conc#961.itm(1)} -attr xrf 63437 -attr oid 627 -attr vt d -attr @path {/sobel/sobel:core/conc#961.itm}
+load net {ACC1:exs#1556.itm(0)} -attr vt d
+load net {ACC1:exs#1556.itm(1)} -attr vt d
+load net {ACC1:exs#1556.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1556.itm} 3 {ACC1:exs#1556.itm(0)} {ACC1:exs#1556.itm(1)} {ACC1:exs#1556.itm(2)} -attr xrf 63438 -attr oid 628 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1556.itm}
+load net {ACC1:conc#1413.itm(0)} -attr vt d
+load net {ACC1:conc#1413.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1413.itm} 2 {ACC1:conc#1413.itm(0)} {ACC1:conc#1413.itm(1)} -attr xrf 63439 -attr oid 629 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1413.itm}
+load net {ACC1:acc#624.itm(0)} -attr vt d
+load net {ACC1:acc#624.itm(1)} -attr vt d
+load net {ACC1:acc#624.itm(2)} -attr vt d
+load net {ACC1:acc#624.itm(3)} -attr vt d
+load net {ACC1:acc#624.itm(4)} -attr vt d
+load net {ACC1:acc#624.itm(5)} -attr vt d
+load net {ACC1:acc#624.itm(6)} -attr vt d
+load netBundle {ACC1:acc#624.itm} 7 {ACC1:acc#624.itm(0)} {ACC1:acc#624.itm(1)} {ACC1:acc#624.itm(2)} {ACC1:acc#624.itm(3)} {ACC1:acc#624.itm(4)} {ACC1:acc#624.itm(5)} {ACC1:acc#624.itm(6)} -attr xrf 63440 -attr oid 630 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#609.itm(0)} -attr vt d
+load net {ACC1:acc#609.itm(1)} -attr vt d
+load net {ACC1:acc#609.itm(2)} -attr vt d
+load net {ACC1:acc#609.itm(3)} -attr vt d
+load net {ACC1:acc#609.itm(4)} -attr vt d
+load net {ACC1:acc#609.itm(5)} -attr vt d
+load netBundle {ACC1:acc#609.itm} 6 {ACC1:acc#609.itm(0)} {ACC1:acc#609.itm(1)} {ACC1:acc#609.itm(2)} {ACC1:acc#609.itm(3)} {ACC1:acc#609.itm(4)} {ACC1:acc#609.itm(5)} -attr xrf 63441 -attr oid 631 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#589.itm(0)} -attr vt d
+load net {ACC1:acc#589.itm(1)} -attr vt d
+load net {ACC1:acc#589.itm(2)} -attr vt d
+load net {ACC1:acc#589.itm(3)} -attr vt d
+load net {ACC1:acc#589.itm(4)} -attr vt d
+load netBundle {ACC1:acc#589.itm} 5 {ACC1:acc#589.itm(0)} {ACC1:acc#589.itm(1)} {ACC1:acc#589.itm(2)} {ACC1:acc#589.itm(3)} {ACC1:acc#589.itm(4)} -attr xrf 63442 -attr oid 632 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#548.itm(0)} -attr vt d
+load net {ACC1:acc#548.itm(1)} -attr vt d
+load net {ACC1:acc#548.itm(2)} -attr vt d
+load net {ACC1:acc#548.itm(3)} -attr vt d
+load netBundle {ACC1:acc#548.itm} 4 {ACC1:acc#548.itm(0)} {ACC1:acc#548.itm(1)} {ACC1:acc#548.itm(2)} {ACC1:acc#548.itm(3)} -attr xrf 63443 -attr oid 633 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:slc#144.itm(0)} -attr vt d
+load net {ACC1:slc#144.itm(1)} -attr vt d
+load net {ACC1:slc#144.itm(2)} -attr vt d
+load netBundle {ACC1:slc#144.itm} 3 {ACC1:slc#144.itm(0)} {ACC1:slc#144.itm(1)} {ACC1:slc#144.itm(2)} -attr xrf 63444 -attr oid 634 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#144.itm}
+load net {ACC1:acc#476.itm(0)} -attr vt d
+load net {ACC1:acc#476.itm(1)} -attr vt d
+load net {ACC1:acc#476.itm(2)} -attr vt d
+load net {ACC1:acc#476.itm(3)} -attr vt d
+load netBundle {ACC1:acc#476.itm} 4 {ACC1:acc#476.itm(0)} {ACC1:acc#476.itm(1)} {ACC1:acc#476.itm(2)} {ACC1:acc#476.itm(3)} -attr xrf 63445 -attr oid 635 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#476.itm}
+load net {exs#78.itm(0)} -attr vt d
+load net {exs#78.itm(1)} -attr vt d
+load net {exs#78.itm(2)} -attr vt d
+load netBundle {exs#78.itm} 3 {exs#78.itm(0)} {exs#78.itm(1)} {exs#78.itm(2)} -attr xrf 63446 -attr oid 636 -attr vt d -attr @path {/sobel/sobel:core/exs#78.itm}
+load net {conc#962.itm(0)} -attr vt d
+load net {conc#962.itm(1)} -attr vt d
+load netBundle {conc#962.itm} 2 {conc#962.itm(0)} {conc#962.itm(1)} -attr xrf 63447 -attr oid 637 -attr vt d -attr @path {/sobel/sobel:core/conc#962.itm}
+load net {ACC1:exs#1558.itm(0)} -attr vt d
+load net {ACC1:exs#1558.itm(1)} -attr vt d
+load net {ACC1:exs#1558.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1558.itm} 3 {ACC1:exs#1558.itm(0)} {ACC1:exs#1558.itm(1)} {ACC1:exs#1558.itm(2)} -attr xrf 63448 -attr oid 638 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1558.itm}
+load net {ACC1:conc#1411.itm(0)} -attr vt d
+load net {ACC1:conc#1411.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1411.itm} 2 {ACC1:conc#1411.itm(0)} {ACC1:conc#1411.itm(1)} -attr xrf 63449 -attr oid 639 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1411.itm}
+load net {ACC1:slc#143.itm(0)} -attr vt d
+load net {ACC1:slc#143.itm(1)} -attr vt d
+load net {ACC1:slc#143.itm(2)} -attr vt d
+load netBundle {ACC1:slc#143.itm} 3 {ACC1:slc#143.itm(0)} {ACC1:slc#143.itm(1)} {ACC1:slc#143.itm(2)} -attr xrf 63450 -attr oid 640 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#143.itm}
+load net {ACC1:acc#475.itm(0)} -attr vt d
+load net {ACC1:acc#475.itm(1)} -attr vt d
+load net {ACC1:acc#475.itm(2)} -attr vt d
+load net {ACC1:acc#475.itm(3)} -attr vt d
+load netBundle {ACC1:acc#475.itm} 4 {ACC1:acc#475.itm(0)} {ACC1:acc#475.itm(1)} {ACC1:acc#475.itm(2)} {ACC1:acc#475.itm(3)} -attr xrf 63451 -attr oid 641 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#475.itm}
+load net {exs#79.itm(0)} -attr vt d
+load net {exs#79.itm(1)} -attr vt d
+load net {exs#79.itm(2)} -attr vt d
+load netBundle {exs#79.itm} 3 {exs#79.itm(0)} {exs#79.itm(1)} {exs#79.itm(2)} -attr xrf 63452 -attr oid 642 -attr vt d -attr @path {/sobel/sobel:core/exs#79.itm}
+load net {conc#963.itm(0)} -attr vt d
+load net {conc#963.itm(1)} -attr vt d
+load netBundle {conc#963.itm} 2 {conc#963.itm(0)} {conc#963.itm(1)} -attr xrf 63453 -attr oid 643 -attr vt d -attr @path {/sobel/sobel:core/conc#963.itm}
+load net {ACC1:exs#1560.itm(0)} -attr vt d
+load net {ACC1:exs#1560.itm(1)} -attr vt d
+load net {ACC1:exs#1560.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1560.itm} 3 {ACC1:exs#1560.itm(0)} {ACC1:exs#1560.itm(1)} {ACC1:exs#1560.itm(2)} -attr xrf 63454 -attr oid 644 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1560.itm}
+load net {ACC1:conc#1409.itm(0)} -attr vt d
+load net {ACC1:conc#1409.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1409.itm} 2 {ACC1:conc#1409.itm(0)} {ACC1:conc#1409.itm(1)} -attr xrf 63455 -attr oid 645 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1409.itm}
+load net {ACC1:acc#547.itm(0)} -attr vt d
+load net {ACC1:acc#547.itm(1)} -attr vt d
+load net {ACC1:acc#547.itm(2)} -attr vt d
+load net {ACC1:acc#547.itm(3)} -attr vt d
+load netBundle {ACC1:acc#547.itm} 4 {ACC1:acc#547.itm(0)} {ACC1:acc#547.itm(1)} {ACC1:acc#547.itm(2)} {ACC1:acc#547.itm(3)} -attr xrf 63456 -attr oid 646 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:slc#142.itm(0)} -attr vt d
+load net {ACC1:slc#142.itm(1)} -attr vt d
+load net {ACC1:slc#142.itm(2)} -attr vt d
+load netBundle {ACC1:slc#142.itm} 3 {ACC1:slc#142.itm(0)} {ACC1:slc#142.itm(1)} {ACC1:slc#142.itm(2)} -attr xrf 63457 -attr oid 647 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#142.itm}
+load net {ACC1:acc#474.itm(0)} -attr vt d
+load net {ACC1:acc#474.itm(1)} -attr vt d
+load net {ACC1:acc#474.itm(2)} -attr vt d
+load net {ACC1:acc#474.itm(3)} -attr vt d
+load netBundle {ACC1:acc#474.itm} 4 {ACC1:acc#474.itm(0)} {ACC1:acc#474.itm(1)} {ACC1:acc#474.itm(2)} {ACC1:acc#474.itm(3)} -attr xrf 63458 -attr oid 648 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#474.itm}
+load net {exs#80.itm(0)} -attr vt d
+load net {exs#80.itm(1)} -attr vt d
+load net {exs#80.itm(2)} -attr vt d
+load netBundle {exs#80.itm} 3 {exs#80.itm(0)} {exs#80.itm(1)} {exs#80.itm(2)} -attr xrf 63459 -attr oid 649 -attr vt d -attr @path {/sobel/sobel:core/exs#80.itm}
+load net {conc#964.itm(0)} -attr vt d
+load net {conc#964.itm(1)} -attr vt d
+load netBundle {conc#964.itm} 2 {conc#964.itm(0)} {conc#964.itm(1)} -attr xrf 63460 -attr oid 650 -attr vt d -attr @path {/sobel/sobel:core/conc#964.itm}
+load net {ACC1:exs#1562.itm(0)} -attr vt d
+load net {ACC1:exs#1562.itm(1)} -attr vt d
+load net {ACC1:exs#1562.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1562.itm} 3 {ACC1:exs#1562.itm(0)} {ACC1:exs#1562.itm(1)} {ACC1:exs#1562.itm(2)} -attr xrf 63461 -attr oid 651 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1562.itm}
+load net {ACC1:conc#1407.itm(0)} -attr vt d
+load net {ACC1:conc#1407.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1407.itm} 2 {ACC1:conc#1407.itm(0)} {ACC1:conc#1407.itm(1)} -attr xrf 63462 -attr oid 652 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1407.itm}
+load net {ACC1:slc#141.itm(0)} -attr vt d
+load net {ACC1:slc#141.itm(1)} -attr vt d
+load net {ACC1:slc#141.itm(2)} -attr vt d
+load netBundle {ACC1:slc#141.itm} 3 {ACC1:slc#141.itm(0)} {ACC1:slc#141.itm(1)} {ACC1:slc#141.itm(2)} -attr xrf 63463 -attr oid 653 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#141.itm}
+load net {ACC1:acc#473.itm(0)} -attr vt d
+load net {ACC1:acc#473.itm(1)} -attr vt d
+load net {ACC1:acc#473.itm(2)} -attr vt d
+load net {ACC1:acc#473.itm(3)} -attr vt d
+load netBundle {ACC1:acc#473.itm} 4 {ACC1:acc#473.itm(0)} {ACC1:acc#473.itm(1)} {ACC1:acc#473.itm(2)} {ACC1:acc#473.itm(3)} -attr xrf 63464 -attr oid 654 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#473.itm}
+load net {exs#99.itm(0)} -attr vt d
+load net {exs#99.itm(1)} -attr vt d
+load net {exs#99.itm(2)} -attr vt d
+load netBundle {exs#99.itm} 3 {exs#99.itm(0)} {exs#99.itm(1)} {exs#99.itm(2)} -attr xrf 63465 -attr oid 655 -attr vt d -attr @path {/sobel/sobel:core/exs#99.itm}
+load net {conc#965.itm(0)} -attr vt d
+load net {conc#965.itm(1)} -attr vt d
+load netBundle {conc#965.itm} 2 {conc#965.itm(0)} {conc#965.itm(1)} -attr xrf 63466 -attr oid 656 -attr vt d -attr @path {/sobel/sobel:core/conc#965.itm}
+load net {ACC1:exs#1564.itm(0)} -attr vt d
+load net {ACC1:exs#1564.itm(1)} -attr vt d
+load net {ACC1:exs#1564.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1564.itm} 3 {ACC1:exs#1564.itm(0)} {ACC1:exs#1564.itm(1)} {ACC1:exs#1564.itm(2)} -attr xrf 63467 -attr oid 657 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1564.itm}
+load net {ACC1:conc#1405.itm(0)} -attr vt d
+load net {ACC1:conc#1405.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1405.itm} 2 {ACC1:conc#1405.itm(0)} {ACC1:conc#1405.itm(1)} -attr xrf 63468 -attr oid 658 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1405.itm}
+load net {ACC1:acc#588.itm(0)} -attr vt d
+load net {ACC1:acc#588.itm(1)} -attr vt d
+load net {ACC1:acc#588.itm(2)} -attr vt d
+load net {ACC1:acc#588.itm(3)} -attr vt d
+load net {ACC1:acc#588.itm(4)} -attr vt d
+load netBundle {ACC1:acc#588.itm} 5 {ACC1:acc#588.itm(0)} {ACC1:acc#588.itm(1)} {ACC1:acc#588.itm(2)} {ACC1:acc#588.itm(3)} {ACC1:acc#588.itm(4)} -attr xrf 63469 -attr oid 659 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#546.itm(0)} -attr vt d
+load net {ACC1:acc#546.itm(1)} -attr vt d
+load net {ACC1:acc#546.itm(2)} -attr vt d
+load net {ACC1:acc#546.itm(3)} -attr vt d
+load netBundle {ACC1:acc#546.itm} 4 {ACC1:acc#546.itm(0)} {ACC1:acc#546.itm(1)} {ACC1:acc#546.itm(2)} {ACC1:acc#546.itm(3)} -attr xrf 63470 -attr oid 660 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:slc#140.itm(0)} -attr vt d
+load net {ACC1:slc#140.itm(1)} -attr vt d
+load net {ACC1:slc#140.itm(2)} -attr vt d
+load netBundle {ACC1:slc#140.itm} 3 {ACC1:slc#140.itm(0)} {ACC1:slc#140.itm(1)} {ACC1:slc#140.itm(2)} -attr xrf 63471 -attr oid 661 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#140.itm}
+load net {ACC1:acc#472.itm(0)} -attr vt d
+load net {ACC1:acc#472.itm(1)} -attr vt d
+load net {ACC1:acc#472.itm(2)} -attr vt d
+load net {ACC1:acc#472.itm(3)} -attr vt d
+load netBundle {ACC1:acc#472.itm} 4 {ACC1:acc#472.itm(0)} {ACC1:acc#472.itm(1)} {ACC1:acc#472.itm(2)} {ACC1:acc#472.itm(3)} -attr xrf 63472 -attr oid 662 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#472.itm}
+load net {exs#81.itm(0)} -attr vt d
+load net {exs#81.itm(1)} -attr vt d
+load net {exs#81.itm(2)} -attr vt d
+load netBundle {exs#81.itm} 3 {exs#81.itm(0)} {exs#81.itm(1)} {exs#81.itm(2)} -attr xrf 63473 -attr oid 663 -attr vt d -attr @path {/sobel/sobel:core/exs#81.itm}
+load net {conc#967.itm(0)} -attr vt d
+load net {conc#967.itm(1)} -attr vt d
+load netBundle {conc#967.itm} 2 {conc#967.itm(0)} {conc#967.itm(1)} -attr xrf 63474 -attr oid 664 -attr vt d -attr @path {/sobel/sobel:core/conc#967.itm}
+load net {ACC1:exs#1566.itm(0)} -attr vt d
+load net {ACC1:exs#1566.itm(1)} -attr vt d
+load net {ACC1:exs#1566.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1566.itm} 3 {ACC1:exs#1566.itm(0)} {ACC1:exs#1566.itm(1)} {ACC1:exs#1566.itm(2)} -attr xrf 63475 -attr oid 665 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1566.itm}
+load net {ACC1:conc#1403.itm(0)} -attr vt d
+load net {ACC1:conc#1403.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1403.itm} 2 {ACC1:conc#1403.itm(0)} {ACC1:conc#1403.itm(1)} -attr xrf 63476 -attr oid 666 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1403.itm}
+load net {ACC1:slc#138.itm(0)} -attr vt d
+load net {ACC1:slc#138.itm(1)} -attr vt d
+load net {ACC1:slc#138.itm(2)} -attr vt d
+load netBundle {ACC1:slc#138.itm} 3 {ACC1:slc#138.itm(0)} {ACC1:slc#138.itm(1)} {ACC1:slc#138.itm(2)} -attr xrf 63477 -attr oid 667 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#138.itm}
+load net {ACC1:acc#470.itm(0)} -attr vt d
+load net {ACC1:acc#470.itm(1)} -attr vt d
+load net {ACC1:acc#470.itm(2)} -attr vt d
+load net {ACC1:acc#470.itm(3)} -attr vt d
+load netBundle {ACC1:acc#470.itm} 4 {ACC1:acc#470.itm(0)} {ACC1:acc#470.itm(1)} {ACC1:acc#470.itm(2)} {ACC1:acc#470.itm(3)} -attr xrf 63478 -attr oid 668 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#470.itm}
+load net {exs#82.itm(0)} -attr vt d
+load net {exs#82.itm(1)} -attr vt d
+load net {exs#82.itm(2)} -attr vt d
+load netBundle {exs#82.itm} 3 {exs#82.itm(0)} {exs#82.itm(1)} {exs#82.itm(2)} -attr xrf 63479 -attr oid 669 -attr vt d -attr @path {/sobel/sobel:core/exs#82.itm}
+load net {conc#968.itm(0)} -attr vt d
+load net {conc#968.itm(1)} -attr vt d
+load netBundle {conc#968.itm} 2 {conc#968.itm(0)} {conc#968.itm(1)} -attr xrf 63480 -attr oid 670 -attr vt d -attr @path {/sobel/sobel:core/conc#968.itm}
+load net {ACC1:exs#1568.itm(0)} -attr vt d
+load net {ACC1:exs#1568.itm(1)} -attr vt d
+load net {ACC1:exs#1568.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1568.itm} 3 {ACC1:exs#1568.itm(0)} {ACC1:exs#1568.itm(1)} {ACC1:exs#1568.itm(2)} -attr xrf 63481 -attr oid 671 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1568.itm}
+load net {ACC1:conc#1399.itm(0)} -attr vt d
+load net {ACC1:conc#1399.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1399.itm} 2 {ACC1:conc#1399.itm(0)} {ACC1:conc#1399.itm(1)} -attr xrf 63482 -attr oid 672 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1399.itm}
+load net {ACC1:acc#545.itm(0)} -attr vt d
+load net {ACC1:acc#545.itm(1)} -attr vt d
+load net {ACC1:acc#545.itm(2)} -attr vt d
+load net {ACC1:acc#545.itm(3)} -attr vt d
+load netBundle {ACC1:acc#545.itm} 4 {ACC1:acc#545.itm(0)} {ACC1:acc#545.itm(1)} {ACC1:acc#545.itm(2)} {ACC1:acc#545.itm(3)} -attr xrf 63483 -attr oid 673 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:slc#137.itm(0)} -attr vt d
+load net {ACC1:slc#137.itm(1)} -attr vt d
+load net {ACC1:slc#137.itm(2)} -attr vt d
+load netBundle {ACC1:slc#137.itm} 3 {ACC1:slc#137.itm(0)} {ACC1:slc#137.itm(1)} {ACC1:slc#137.itm(2)} -attr xrf 63484 -attr oid 674 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#137.itm}
+load net {ACC1:acc#469.itm(0)} -attr vt d
+load net {ACC1:acc#469.itm(1)} -attr vt d
+load net {ACC1:acc#469.itm(2)} -attr vt d
+load net {ACC1:acc#469.itm(3)} -attr vt d
+load netBundle {ACC1:acc#469.itm} 4 {ACC1:acc#469.itm(0)} {ACC1:acc#469.itm(1)} {ACC1:acc#469.itm(2)} {ACC1:acc#469.itm(3)} -attr xrf 63485 -attr oid 675 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#469.itm}
+load net {exs#83.itm(0)} -attr vt d
+load net {exs#83.itm(1)} -attr vt d
+load net {exs#83.itm(2)} -attr vt d
+load netBundle {exs#83.itm} 3 {exs#83.itm(0)} {exs#83.itm(1)} {exs#83.itm(2)} -attr xrf 63486 -attr oid 676 -attr vt d -attr @path {/sobel/sobel:core/exs#83.itm}
+load net {conc#969.itm(0)} -attr vt d
+load net {conc#969.itm(1)} -attr vt d
+load netBundle {conc#969.itm} 2 {conc#969.itm(0)} {conc#969.itm(1)} -attr xrf 63487 -attr oid 677 -attr vt d -attr @path {/sobel/sobel:core/conc#969.itm}
+load net {ACC1:exs#1570.itm(0)} -attr vt d
+load net {ACC1:exs#1570.itm(1)} -attr vt d
+load net {ACC1:exs#1570.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1570.itm} 3 {ACC1:exs#1570.itm(0)} {ACC1:exs#1570.itm(1)} {ACC1:exs#1570.itm(2)} -attr xrf 63488 -attr oid 678 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1570.itm}
+load net {ACC1:conc#1397.itm(0)} -attr vt d
+load net {ACC1:conc#1397.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1397.itm} 2 {ACC1:conc#1397.itm(0)} {ACC1:conc#1397.itm(1)} -attr xrf 63489 -attr oid 679 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1397.itm}
+load net {ACC1:slc#136.itm(0)} -attr vt d
+load net {ACC1:slc#136.itm(1)} -attr vt d
+load net {ACC1:slc#136.itm(2)} -attr vt d
+load netBundle {ACC1:slc#136.itm} 3 {ACC1:slc#136.itm(0)} {ACC1:slc#136.itm(1)} {ACC1:slc#136.itm(2)} -attr xrf 63490 -attr oid 680 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#136.itm}
+load net {ACC1:acc#468.itm(0)} -attr vt d
+load net {ACC1:acc#468.itm(1)} -attr vt d
+load net {ACC1:acc#468.itm(2)} -attr vt d
+load net {ACC1:acc#468.itm(3)} -attr vt d
+load netBundle {ACC1:acc#468.itm} 4 {ACC1:acc#468.itm(0)} {ACC1:acc#468.itm(1)} {ACC1:acc#468.itm(2)} {ACC1:acc#468.itm(3)} -attr xrf 63491 -attr oid 681 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#468.itm}
+load net {exs#100.itm(0)} -attr vt d
+load net {exs#100.itm(1)} -attr vt d
+load net {exs#100.itm(2)} -attr vt d
+load netBundle {exs#100.itm} 3 {exs#100.itm(0)} {exs#100.itm(1)} {exs#100.itm(2)} -attr xrf 63492 -attr oid 682 -attr vt d -attr @path {/sobel/sobel:core/exs#100.itm}
+load net {conc#970.itm(0)} -attr vt d
+load net {conc#970.itm(1)} -attr vt d
+load netBundle {conc#970.itm} 2 {conc#970.itm(0)} {conc#970.itm(1)} -attr xrf 63493 -attr oid 683 -attr vt d -attr @path {/sobel/sobel:core/conc#970.itm}
+load net {ACC1:exs#1572.itm(0)} -attr vt d
+load net {ACC1:exs#1572.itm(1)} -attr vt d
+load net {ACC1:exs#1572.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1572.itm} 3 {ACC1:exs#1572.itm(0)} {ACC1:exs#1572.itm(1)} {ACC1:exs#1572.itm(2)} -attr xrf 63494 -attr oid 684 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1572.itm}
+load net {ACC1:conc#1395.itm(0)} -attr vt d
+load net {ACC1:conc#1395.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1395.itm} 2 {ACC1:conc#1395.itm(0)} {ACC1:conc#1395.itm(1)} -attr xrf 63495 -attr oid 685 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1395.itm}
+load net {ACC1:acc#608.itm(0)} -attr vt d
+load net {ACC1:acc#608.itm(1)} -attr vt d
+load net {ACC1:acc#608.itm(2)} -attr vt d
+load net {ACC1:acc#608.itm(3)} -attr vt d
+load net {ACC1:acc#608.itm(4)} -attr vt d
+load net {ACC1:acc#608.itm(5)} -attr vt d
+load netBundle {ACC1:acc#608.itm} 6 {ACC1:acc#608.itm(0)} {ACC1:acc#608.itm(1)} {ACC1:acc#608.itm(2)} {ACC1:acc#608.itm(3)} {ACC1:acc#608.itm(4)} {ACC1:acc#608.itm(5)} -attr xrf 63496 -attr oid 686 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#587.itm(0)} -attr vt d
+load net {ACC1:acc#587.itm(1)} -attr vt d
+load net {ACC1:acc#587.itm(2)} -attr vt d
+load net {ACC1:acc#587.itm(3)} -attr vt d
+load net {ACC1:acc#587.itm(4)} -attr vt d
+load netBundle {ACC1:acc#587.itm} 5 {ACC1:acc#587.itm(0)} {ACC1:acc#587.itm(1)} {ACC1:acc#587.itm(2)} {ACC1:acc#587.itm(3)} {ACC1:acc#587.itm(4)} -attr xrf 63497 -attr oid 687 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#544.itm(0)} -attr vt d
+load net {ACC1:acc#544.itm(1)} -attr vt d
+load net {ACC1:acc#544.itm(2)} -attr vt d
+load net {ACC1:acc#544.itm(3)} -attr vt d
+load netBundle {ACC1:acc#544.itm} 4 {ACC1:acc#544.itm(0)} {ACC1:acc#544.itm(1)} {ACC1:acc#544.itm(2)} {ACC1:acc#544.itm(3)} -attr xrf 63498 -attr oid 688 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:slc#135.itm(0)} -attr vt d
+load net {ACC1:slc#135.itm(1)} -attr vt d
+load net {ACC1:slc#135.itm(2)} -attr vt d
+load netBundle {ACC1:slc#135.itm} 3 {ACC1:slc#135.itm(0)} {ACC1:slc#135.itm(1)} {ACC1:slc#135.itm(2)} -attr xrf 63499 -attr oid 689 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#135.itm}
+load net {ACC1:acc#467.itm(0)} -attr vt d
+load net {ACC1:acc#467.itm(1)} -attr vt d
+load net {ACC1:acc#467.itm(2)} -attr vt d
+load net {ACC1:acc#467.itm(3)} -attr vt d
+load netBundle {ACC1:acc#467.itm} 4 {ACC1:acc#467.itm(0)} {ACC1:acc#467.itm(1)} {ACC1:acc#467.itm(2)} {ACC1:acc#467.itm(3)} -attr xrf 63500 -attr oid 690 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#467.itm}
+load net {exs#101.itm(0)} -attr vt d
+load net {exs#101.itm(1)} -attr vt d
+load net {exs#101.itm(2)} -attr vt d
+load netBundle {exs#101.itm} 3 {exs#101.itm(0)} {exs#101.itm(1)} {exs#101.itm(2)} -attr xrf 63501 -attr oid 691 -attr vt d -attr @path {/sobel/sobel:core/exs#101.itm}
+load net {conc#972.itm(0)} -attr vt d
+load net {conc#972.itm(1)} -attr vt d
+load netBundle {conc#972.itm} 2 {conc#972.itm(0)} {conc#972.itm(1)} -attr xrf 63502 -attr oid 692 -attr vt d -attr @path {/sobel/sobel:core/conc#972.itm}
+load net {ACC1:exs#1574.itm(0)} -attr vt d
+load net {ACC1:exs#1574.itm(1)} -attr vt d
+load net {ACC1:exs#1574.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1574.itm} 3 {ACC1:exs#1574.itm(0)} {ACC1:exs#1574.itm(1)} {ACC1:exs#1574.itm(2)} -attr xrf 63503 -attr oid 693 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1574.itm}
+load net {ACC1:conc#1393.itm(0)} -attr vt d
+load net {ACC1:conc#1393.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1393.itm} 2 {ACC1:conc#1393.itm(0)} {ACC1:conc#1393.itm(1)} -attr xrf 63504 -attr oid 694 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1393.itm}
+load net {ACC1:slc#134.itm(0)} -attr vt d
+load net {ACC1:slc#134.itm(1)} -attr vt d
+load net {ACC1:slc#134.itm(2)} -attr vt d
+load netBundle {ACC1:slc#134.itm} 3 {ACC1:slc#134.itm(0)} {ACC1:slc#134.itm(1)} {ACC1:slc#134.itm(2)} -attr xrf 63505 -attr oid 695 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#134.itm}
+load net {ACC1:acc#466.itm(0)} -attr vt d
+load net {ACC1:acc#466.itm(1)} -attr vt d
+load net {ACC1:acc#466.itm(2)} -attr vt d
+load net {ACC1:acc#466.itm(3)} -attr vt d
+load netBundle {ACC1:acc#466.itm} 4 {ACC1:acc#466.itm(0)} {ACC1:acc#466.itm(1)} {ACC1:acc#466.itm(2)} {ACC1:acc#466.itm(3)} -attr xrf 63506 -attr oid 696 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#466.itm}
+load net {exs#84.itm(0)} -attr vt d
+load net {exs#84.itm(1)} -attr vt d
+load net {exs#84.itm(2)} -attr vt d
+load netBundle {exs#84.itm} 3 {exs#84.itm(0)} {exs#84.itm(1)} {exs#84.itm(2)} -attr xrf 63507 -attr oid 697 -attr vt d -attr @path {/sobel/sobel:core/exs#84.itm}
+load net {conc#974.itm(0)} -attr vt d
+load net {conc#974.itm(1)} -attr vt d
+load netBundle {conc#974.itm} 2 {conc#974.itm(0)} {conc#974.itm(1)} -attr xrf 63508 -attr oid 698 -attr vt d -attr @path {/sobel/sobel:core/conc#974.itm}
+load net {ACC1:exs#1576.itm(0)} -attr vt d
+load net {ACC1:exs#1576.itm(1)} -attr vt d
+load net {ACC1:exs#1576.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1576.itm} 3 {ACC1:exs#1576.itm(0)} {ACC1:exs#1576.itm(1)} {ACC1:exs#1576.itm(2)} -attr xrf 63509 -attr oid 699 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1576.itm}
+load net {ACC1:conc#1391.itm(0)} -attr vt d
+load net {ACC1:conc#1391.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1391.itm} 2 {ACC1:conc#1391.itm(0)} {ACC1:conc#1391.itm(1)} -attr xrf 63510 -attr oid 700 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1391.itm}
+load net {ACC1:acc#543.itm(0)} -attr vt d
+load net {ACC1:acc#543.itm(1)} -attr vt d
+load net {ACC1:acc#543.itm(2)} -attr vt d
+load net {ACC1:acc#543.itm(3)} -attr vt d
+load netBundle {ACC1:acc#543.itm} 4 {ACC1:acc#543.itm(0)} {ACC1:acc#543.itm(1)} {ACC1:acc#543.itm(2)} {ACC1:acc#543.itm(3)} -attr xrf 63511 -attr oid 701 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:slc#133.itm(0)} -attr vt d
+load net {ACC1:slc#133.itm(1)} -attr vt d
+load net {ACC1:slc#133.itm(2)} -attr vt d
+load netBundle {ACC1:slc#133.itm} 3 {ACC1:slc#133.itm(0)} {ACC1:slc#133.itm(1)} {ACC1:slc#133.itm(2)} -attr xrf 63512 -attr oid 702 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#133.itm}
+load net {ACC1:acc#465.itm(0)} -attr vt d
+load net {ACC1:acc#465.itm(1)} -attr vt d
+load net {ACC1:acc#465.itm(2)} -attr vt d
+load net {ACC1:acc#465.itm(3)} -attr vt d
+load netBundle {ACC1:acc#465.itm} 4 {ACC1:acc#465.itm(0)} {ACC1:acc#465.itm(1)} {ACC1:acc#465.itm(2)} {ACC1:acc#465.itm(3)} -attr xrf 63513 -attr oid 703 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#465.itm}
+load net {exs#85.itm(0)} -attr vt d
+load net {exs#85.itm(1)} -attr vt d
+load net {exs#85.itm(2)} -attr vt d
+load netBundle {exs#85.itm} 3 {exs#85.itm(0)} {exs#85.itm(1)} {exs#85.itm(2)} -attr xrf 63514 -attr oid 704 -attr vt d -attr @path {/sobel/sobel:core/exs#85.itm}
+load net {conc#975.itm(0)} -attr vt d
+load net {conc#975.itm(1)} -attr vt d
+load netBundle {conc#975.itm} 2 {conc#975.itm(0)} {conc#975.itm(1)} -attr xrf 63515 -attr oid 705 -attr vt d -attr @path {/sobel/sobel:core/conc#975.itm}
+load net {ACC1:exs#1578.itm(0)} -attr vt d
+load net {ACC1:exs#1578.itm(1)} -attr vt d
+load net {ACC1:exs#1578.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1578.itm} 3 {ACC1:exs#1578.itm(0)} {ACC1:exs#1578.itm(1)} {ACC1:exs#1578.itm(2)} -attr xrf 63516 -attr oid 706 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1578.itm}
+load net {ACC1:conc#1389.itm(0)} -attr vt d
+load net {ACC1:conc#1389.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1389.itm} 2 {ACC1:conc#1389.itm(0)} {ACC1:conc#1389.itm(1)} -attr xrf 63517 -attr oid 707 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1389.itm}
+load net {ACC1:slc#132.itm(0)} -attr vt d
+load net {ACC1:slc#132.itm(1)} -attr vt d
+load net {ACC1:slc#132.itm(2)} -attr vt d
+load netBundle {ACC1:slc#132.itm} 3 {ACC1:slc#132.itm(0)} {ACC1:slc#132.itm(1)} {ACC1:slc#132.itm(2)} -attr xrf 63518 -attr oid 708 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#132.itm}
+load net {ACC1:acc#464.itm(0)} -attr vt d
+load net {ACC1:acc#464.itm(1)} -attr vt d
+load net {ACC1:acc#464.itm(2)} -attr vt d
+load net {ACC1:acc#464.itm(3)} -attr vt d
+load netBundle {ACC1:acc#464.itm} 4 {ACC1:acc#464.itm(0)} {ACC1:acc#464.itm(1)} {ACC1:acc#464.itm(2)} {ACC1:acc#464.itm(3)} -attr xrf 63519 -attr oid 709 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#464.itm}
+load net {exs#86.itm(0)} -attr vt d
+load net {exs#86.itm(1)} -attr vt d
+load net {exs#86.itm(2)} -attr vt d
+load netBundle {exs#86.itm} 3 {exs#86.itm(0)} {exs#86.itm(1)} {exs#86.itm(2)} -attr xrf 63520 -attr oid 710 -attr vt d -attr @path {/sobel/sobel:core/exs#86.itm}
+load net {conc#976.itm(0)} -attr vt d
+load net {conc#976.itm(1)} -attr vt d
+load netBundle {conc#976.itm} 2 {conc#976.itm(0)} {conc#976.itm(1)} -attr xrf 63521 -attr oid 711 -attr vt d -attr @path {/sobel/sobel:core/conc#976.itm}
+load net {ACC1:exs#1580.itm(0)} -attr vt d
+load net {ACC1:exs#1580.itm(1)} -attr vt d
+load net {ACC1:exs#1580.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1580.itm} 3 {ACC1:exs#1580.itm(0)} {ACC1:exs#1580.itm(1)} {ACC1:exs#1580.itm(2)} -attr xrf 63522 -attr oid 712 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1580.itm}
+load net {ACC1:conc#1387.itm(0)} -attr vt d
+load net {ACC1:conc#1387.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1387.itm} 2 {ACC1:conc#1387.itm(0)} {ACC1:conc#1387.itm(1)} -attr xrf 63523 -attr oid 713 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1387.itm}
+load net {ACC1:acc#586.itm(0)} -attr vt d
+load net {ACC1:acc#586.itm(1)} -attr vt d
+load net {ACC1:acc#586.itm(2)} -attr vt d
+load net {ACC1:acc#586.itm(3)} -attr vt d
+load net {ACC1:acc#586.itm(4)} -attr vt d
+load netBundle {ACC1:acc#586.itm} 5 {ACC1:acc#586.itm(0)} {ACC1:acc#586.itm(1)} {ACC1:acc#586.itm(2)} {ACC1:acc#586.itm(3)} {ACC1:acc#586.itm(4)} -attr xrf 63524 -attr oid 714 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#542.itm(0)} -attr vt d
+load net {ACC1:acc#542.itm(1)} -attr vt d
+load net {ACC1:acc#542.itm(2)} -attr vt d
+load net {ACC1:acc#542.itm(3)} -attr vt d
+load netBundle {ACC1:acc#542.itm} 4 {ACC1:acc#542.itm(0)} {ACC1:acc#542.itm(1)} {ACC1:acc#542.itm(2)} {ACC1:acc#542.itm(3)} -attr xrf 63525 -attr oid 715 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:slc#131.itm(0)} -attr vt d
+load net {ACC1:slc#131.itm(1)} -attr vt d
+load net {ACC1:slc#131.itm(2)} -attr vt d
+load netBundle {ACC1:slc#131.itm} 3 {ACC1:slc#131.itm(0)} {ACC1:slc#131.itm(1)} {ACC1:slc#131.itm(2)} -attr xrf 63526 -attr oid 716 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#131.itm}
+load net {ACC1:acc#463.itm(0)} -attr vt d
+load net {ACC1:acc#463.itm(1)} -attr vt d
+load net {ACC1:acc#463.itm(2)} -attr vt d
+load net {ACC1:acc#463.itm(3)} -attr vt d
+load netBundle {ACC1:acc#463.itm} 4 {ACC1:acc#463.itm(0)} {ACC1:acc#463.itm(1)} {ACC1:acc#463.itm(2)} {ACC1:acc#463.itm(3)} -attr xrf 63527 -attr oid 717 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#463.itm}
+load net {exs#87.itm(0)} -attr vt d
+load net {exs#87.itm(1)} -attr vt d
+load net {exs#87.itm(2)} -attr vt d
+load netBundle {exs#87.itm} 3 {exs#87.itm(0)} {exs#87.itm(1)} {exs#87.itm(2)} -attr xrf 63528 -attr oid 718 -attr vt d -attr @path {/sobel/sobel:core/exs#87.itm}
+load net {conc#977.itm(0)} -attr vt d
+load net {conc#977.itm(1)} -attr vt d
+load netBundle {conc#977.itm} 2 {conc#977.itm(0)} {conc#977.itm(1)} -attr xrf 63529 -attr oid 719 -attr vt d -attr @path {/sobel/sobel:core/conc#977.itm}
+load net {ACC1:exs#1582.itm(0)} -attr vt d
+load net {ACC1:exs#1582.itm(1)} -attr vt d
+load net {ACC1:exs#1582.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1582.itm} 3 {ACC1:exs#1582.itm(0)} {ACC1:exs#1582.itm(1)} {ACC1:exs#1582.itm(2)} -attr xrf 63530 -attr oid 720 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1582.itm}
+load net {ACC1:conc#1385.itm(0)} -attr vt d
+load net {ACC1:conc#1385.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1385.itm} 2 {ACC1:conc#1385.itm(0)} {ACC1:conc#1385.itm(1)} -attr xrf 63531 -attr oid 721 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1385.itm}
+load net {ACC1:slc#130.itm(0)} -attr vt d
+load net {ACC1:slc#130.itm(1)} -attr vt d
+load net {ACC1:slc#130.itm(2)} -attr vt d
+load netBundle {ACC1:slc#130.itm} 3 {ACC1:slc#130.itm(0)} {ACC1:slc#130.itm(1)} {ACC1:slc#130.itm(2)} -attr xrf 63532 -attr oid 722 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#130.itm}
+load net {ACC1:acc#462.itm(0)} -attr vt d
+load net {ACC1:acc#462.itm(1)} -attr vt d
+load net {ACC1:acc#462.itm(2)} -attr vt d
+load net {ACC1:acc#462.itm(3)} -attr vt d
+load netBundle {ACC1:acc#462.itm} 4 {ACC1:acc#462.itm(0)} {ACC1:acc#462.itm(1)} {ACC1:acc#462.itm(2)} {ACC1:acc#462.itm(3)} -attr xrf 63533 -attr oid 723 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#462.itm}
+load net {exs#88.itm(0)} -attr vt d
+load net {exs#88.itm(1)} -attr vt d
+load net {exs#88.itm(2)} -attr vt d
+load netBundle {exs#88.itm} 3 {exs#88.itm(0)} {exs#88.itm(1)} {exs#88.itm(2)} -attr xrf 63534 -attr oid 724 -attr vt d -attr @path {/sobel/sobel:core/exs#88.itm}
+load net {conc#978.itm(0)} -attr vt d
+load net {conc#978.itm(1)} -attr vt d
+load netBundle {conc#978.itm} 2 {conc#978.itm(0)} {conc#978.itm(1)} -attr xrf 63535 -attr oid 725 -attr vt d -attr @path {/sobel/sobel:core/conc#978.itm}
+load net {ACC1:exs#1584.itm(0)} -attr vt d
+load net {ACC1:exs#1584.itm(1)} -attr vt d
+load net {ACC1:exs#1584.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1584.itm} 3 {ACC1:exs#1584.itm(0)} {ACC1:exs#1584.itm(1)} {ACC1:exs#1584.itm(2)} -attr xrf 63536 -attr oid 726 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1584.itm}
+load net {ACC1:conc#1383.itm(0)} -attr vt d
+load net {ACC1:conc#1383.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1383.itm} 2 {ACC1:conc#1383.itm(0)} {ACC1:conc#1383.itm(1)} -attr xrf 63537 -attr oid 727 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1383.itm}
+load net {ACC1:acc#541.itm(0)} -attr vt d
+load net {ACC1:acc#541.itm(1)} -attr vt d
+load net {ACC1:acc#541.itm(2)} -attr vt d
+load net {ACC1:acc#541.itm(3)} -attr vt d
+load netBundle {ACC1:acc#541.itm} 4 {ACC1:acc#541.itm(0)} {ACC1:acc#541.itm(1)} {ACC1:acc#541.itm(2)} {ACC1:acc#541.itm(3)} -attr xrf 63538 -attr oid 728 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:slc#128.itm(0)} -attr vt d
+load net {ACC1:slc#128.itm(1)} -attr vt d
+load net {ACC1:slc#128.itm(2)} -attr vt d
+load netBundle {ACC1:slc#128.itm} 3 {ACC1:slc#128.itm(0)} {ACC1:slc#128.itm(1)} {ACC1:slc#128.itm(2)} -attr xrf 63539 -attr oid 729 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#128.itm}
+load net {ACC1:acc#460.itm(0)} -attr vt d
+load net {ACC1:acc#460.itm(1)} -attr vt d
+load net {ACC1:acc#460.itm(2)} -attr vt d
+load net {ACC1:acc#460.itm(3)} -attr vt d
+load netBundle {ACC1:acc#460.itm} 4 {ACC1:acc#460.itm(0)} {ACC1:acc#460.itm(1)} {ACC1:acc#460.itm(2)} {ACC1:acc#460.itm(3)} -attr xrf 63540 -attr oid 730 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#460.itm}
+load net {exs#89.itm(0)} -attr vt d
+load net {exs#89.itm(1)} -attr vt d
+load net {exs#89.itm(2)} -attr vt d
+load netBundle {exs#89.itm} 3 {exs#89.itm(0)} {exs#89.itm(1)} {exs#89.itm(2)} -attr xrf 63541 -attr oid 731 -attr vt d -attr @path {/sobel/sobel:core/exs#89.itm}
+load net {conc#979.itm(0)} -attr vt d
+load net {conc#979.itm(1)} -attr vt d
+load netBundle {conc#979.itm} 2 {conc#979.itm(0)} {conc#979.itm(1)} -attr xrf 63542 -attr oid 732 -attr vt d -attr @path {/sobel/sobel:core/conc#979.itm}
+load net {ACC1:exs#1586.itm(0)} -attr vt d
+load net {ACC1:exs#1586.itm(1)} -attr vt d
+load net {ACC1:exs#1586.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1586.itm} 3 {ACC1:exs#1586.itm(0)} {ACC1:exs#1586.itm(1)} {ACC1:exs#1586.itm(2)} -attr xrf 63543 -attr oid 733 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1586.itm}
+load net {ACC1:conc#1379.itm(0)} -attr vt d
+load net {ACC1:conc#1379.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1379.itm} 2 {ACC1:conc#1379.itm(0)} {ACC1:conc#1379.itm(1)} -attr xrf 63544 -attr oid 734 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1379.itm}
+load net {ACC1:slc#127.itm(0)} -attr vt d
+load net {ACC1:slc#127.itm(1)} -attr vt d
+load net {ACC1:slc#127.itm(2)} -attr vt d
+load netBundle {ACC1:slc#127.itm} 3 {ACC1:slc#127.itm(0)} {ACC1:slc#127.itm(1)} {ACC1:slc#127.itm(2)} -attr xrf 63545 -attr oid 735 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#127.itm}
+load net {ACC1:acc#459.itm(0)} -attr vt d
+load net {ACC1:acc#459.itm(1)} -attr vt d
+load net {ACC1:acc#459.itm(2)} -attr vt d
+load net {ACC1:acc#459.itm(3)} -attr vt d
+load netBundle {ACC1:acc#459.itm} 4 {ACC1:acc#459.itm(0)} {ACC1:acc#459.itm(1)} {ACC1:acc#459.itm(2)} {ACC1:acc#459.itm(3)} -attr xrf 63546 -attr oid 736 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#459.itm}
+load net {exs#102.itm(0)} -attr vt d
+load net {exs#102.itm(1)} -attr vt d
+load net {exs#102.itm(2)} -attr vt d
+load netBundle {exs#102.itm} 3 {exs#102.itm(0)} {exs#102.itm(1)} {exs#102.itm(2)} -attr xrf 63547 -attr oid 737 -attr vt d -attr @path {/sobel/sobel:core/exs#102.itm}
+load net {conc#980.itm(0)} -attr vt d
+load net {conc#980.itm(1)} -attr vt d
+load netBundle {conc#980.itm} 2 {conc#980.itm(0)} {conc#980.itm(1)} -attr xrf 63548 -attr oid 738 -attr vt d -attr @path {/sobel/sobel:core/conc#980.itm}
+load net {ACC1:exs#1588.itm(0)} -attr vt d
+load net {ACC1:exs#1588.itm(1)} -attr vt d
+load net {ACC1:exs#1588.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1588.itm} 3 {ACC1:exs#1588.itm(0)} {ACC1:exs#1588.itm(1)} {ACC1:exs#1588.itm(2)} -attr xrf 63549 -attr oid 739 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1588.itm}
+load net {ACC1:conc#1377.itm(0)} -attr vt d
+load net {ACC1:conc#1377.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1377.itm} 2 {ACC1:conc#1377.itm(0)} {ACC1:conc#1377.itm(1)} -attr xrf 63550 -attr oid 740 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1377.itm}
+load net {ACC1:acc#647.itm(0)} -attr vt d
+load net {ACC1:acc#647.itm(1)} -attr vt d
+load net {ACC1:acc#647.itm(2)} -attr vt d
+load net {ACC1:acc#647.itm(3)} -attr vt d
+load net {ACC1:acc#647.itm(4)} -attr vt d
+load net {ACC1:acc#647.itm(5)} -attr vt d
+load net {ACC1:acc#647.itm(6)} -attr vt d
+load net {ACC1:acc#647.itm(7)} -attr vt d
+load net {ACC1:acc#647.itm(8)} -attr vt d
+load net {ACC1:acc#647.itm(9)} -attr vt d
+load netBundle {ACC1:acc#647.itm} 10 {ACC1:acc#647.itm(0)} {ACC1:acc#647.itm(1)} {ACC1:acc#647.itm(2)} {ACC1:acc#647.itm(3)} {ACC1:acc#647.itm(4)} {ACC1:acc#647.itm(5)} {ACC1:acc#647.itm(6)} {ACC1:acc#647.itm(7)} {ACC1:acc#647.itm(8)} {ACC1:acc#647.itm(9)} -attr xrf 63551 -attr oid 741 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#640.itm(0)} -attr vt d
+load net {ACC1:acc#640.itm(1)} -attr vt d
+load net {ACC1:acc#640.itm(2)} -attr vt d
+load net {ACC1:acc#640.itm(3)} -attr vt d
+load net {ACC1:acc#640.itm(4)} -attr vt d
+load net {ACC1:acc#640.itm(5)} -attr vt d
+load net {ACC1:acc#640.itm(6)} -attr vt d
+load net {ACC1:acc#640.itm(7)} -attr vt d
+load netBundle {ACC1:acc#640.itm} 8 {ACC1:acc#640.itm(0)} {ACC1:acc#640.itm(1)} {ACC1:acc#640.itm(2)} {ACC1:acc#640.itm(3)} {ACC1:acc#640.itm(4)} {ACC1:acc#640.itm(5)} {ACC1:acc#640.itm(6)} {ACC1:acc#640.itm(7)} -attr xrf 63552 -attr oid 742 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#627.itm(0)} -attr vt d
+load net {ACC1:acc#627.itm(1)} -attr vt d
+load net {ACC1:acc#627.itm(2)} -attr vt d
+load net {ACC1:acc#627.itm(3)} -attr vt d
+load net {ACC1:acc#627.itm(4)} -attr vt d
+load net {ACC1:acc#627.itm(5)} -attr vt d
+load net {ACC1:acc#627.itm(6)} -attr vt d
+load net {ACC1:acc#627.itm(7)} -attr vt d
+load netBundle {ACC1:acc#627.itm} 8 {ACC1:acc#627.itm(0)} {ACC1:acc#627.itm(1)} {ACC1:acc#627.itm(2)} {ACC1:acc#627.itm(3)} {ACC1:acc#627.itm(4)} {ACC1:acc#627.itm(5)} {ACC1:acc#627.itm(6)} {ACC1:acc#627.itm(7)} -attr xrf 63553 -attr oid 743 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {conc#982.itm(0)} -attr vt d
+load net {conc#982.itm(1)} -attr vt d
+load net {conc#982.itm(2)} -attr vt d
+load net {conc#982.itm(3)} -attr vt d
+load net {conc#982.itm(4)} -attr vt d
+load net {conc#982.itm(5)} -attr vt d
+load net {conc#982.itm(6)} -attr vt d
+load netBundle {conc#982.itm} 7 {conc#982.itm(0)} {conc#982.itm(1)} {conc#982.itm(2)} {conc#982.itm(3)} {conc#982.itm(4)} {conc#982.itm(5)} {conc#982.itm(6)} -attr xrf 63554 -attr oid 744 -attr vt d -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {ACC1-3:exs#1072.itm(0)} -attr vt d
+load net {ACC1-3:exs#1072.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1072.itm} 2 {ACC1-3:exs#1072.itm(0)} {ACC1-3:exs#1072.itm(1)} -attr xrf 63555 -attr oid 745 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1072.itm}
+load net {ACC1:acc#614.itm(0)} -attr vt d
+load net {ACC1:acc#614.itm(1)} -attr vt d
+load net {ACC1:acc#614.itm(2)} -attr vt d
+load net {ACC1:acc#614.itm(3)} -attr vt d
+load net {ACC1:acc#614.itm(4)} -attr vt d
+load net {ACC1:acc#614.itm(5)} -attr vt d
+load netBundle {ACC1:acc#614.itm} 6 {ACC1:acc#614.itm(0)} {ACC1:acc#614.itm(1)} {ACC1:acc#614.itm(2)} {ACC1:acc#614.itm(3)} {ACC1:acc#614.itm(4)} {ACC1:acc#614.itm(5)} -attr xrf 63556 -attr oid 746 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#599.itm(0)} -attr vt d
+load net {ACC1:acc#599.itm(1)} -attr vt d
+load net {ACC1:acc#599.itm(2)} -attr vt d
+load net {ACC1:acc#599.itm(3)} -attr vt d
+load net {ACC1:acc#599.itm(4)} -attr vt d
+load netBundle {ACC1:acc#599.itm} 5 {ACC1:acc#599.itm(0)} {ACC1:acc#599.itm(1)} {ACC1:acc#599.itm(2)} {ACC1:acc#599.itm(3)} {ACC1:acc#599.itm(4)} -attr xrf 63557 -attr oid 747 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#568.itm(0)} -attr vt d
+load net {ACC1:acc#568.itm(1)} -attr vt d
+load net {ACC1:acc#568.itm(2)} -attr vt d
+load net {ACC1:acc#568.itm(3)} -attr vt d
+load netBundle {ACC1:acc#568.itm} 4 {ACC1:acc#568.itm(0)} {ACC1:acc#568.itm(1)} {ACC1:acc#568.itm(2)} {ACC1:acc#568.itm(3)} -attr xrf 63558 -attr oid 748 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#517.itm(0)} -attr vt d
+load net {ACC1:acc#517.itm(1)} -attr vt d
+load net {ACC1:acc#517.itm(2)} -attr vt d
+load netBundle {ACC1:acc#517.itm} 3 {ACC1:acc#517.itm(0)} {ACC1:acc#517.itm(1)} {ACC1:acc#517.itm(2)} -attr xrf 63559 -attr oid 749 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load net {ACC1-2:exs#20.itm(0)} -attr vt d
+load net {ACC1-2:exs#20.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#20.itm} 2 {ACC1-2:exs#20.itm(0)} {ACC1-2:exs#20.itm(1)} -attr xrf 63560 -attr oid 750 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#20.itm}
+load net {ACC1-2:exs#1049.itm(0)} -attr vt d
+load net {ACC1-2:exs#1049.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1049.itm} 2 {ACC1-2:exs#1049.itm(0)} {ACC1-2:exs#1049.itm(1)} -attr xrf 63561 -attr oid 751 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1049.itm}
+load net {ACC1:acc#567.itm(0)} -attr vt d
+load net {ACC1:acc#567.itm(1)} -attr vt d
+load net {ACC1:acc#567.itm(2)} -attr vt d
+load net {ACC1:acc#567.itm(3)} -attr vt d
+load netBundle {ACC1:acc#567.itm} 4 {ACC1:acc#567.itm(0)} {ACC1:acc#567.itm(1)} {ACC1:acc#567.itm(2)} {ACC1:acc#567.itm(3)} -attr xrf 63562 -attr oid 752 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#598.itm(0)} -attr vt d
+load net {ACC1:acc#598.itm(1)} -attr vt d
+load net {ACC1:acc#598.itm(2)} -attr vt d
+load net {ACC1:acc#598.itm(3)} -attr vt d
+load net {ACC1:acc#598.itm(4)} -attr vt d
+load netBundle {ACC1:acc#598.itm} 5 {ACC1:acc#598.itm(0)} {ACC1:acc#598.itm(1)} {ACC1:acc#598.itm(2)} {ACC1:acc#598.itm(3)} {ACC1:acc#598.itm(4)} -attr xrf 63563 -attr oid 753 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#566.itm(0)} -attr vt d
+load net {ACC1:acc#566.itm(1)} -attr vt d
+load net {ACC1:acc#566.itm(2)} -attr vt d
+load net {ACC1:acc#566.itm(3)} -attr vt d
+load netBundle {ACC1:acc#566.itm} 4 {ACC1:acc#566.itm(0)} {ACC1:acc#566.itm(1)} {ACC1:acc#566.itm(2)} {ACC1:acc#566.itm(3)} -attr xrf 63564 -attr oid 754 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#513.itm(0)} -attr vt d
+load net {ACC1:acc#513.itm(1)} -attr vt d
+load net {ACC1:acc#513.itm(2)} -attr vt d
+load netBundle {ACC1:acc#513.itm} 3 {ACC1:acc#513.itm(0)} {ACC1:acc#513.itm(1)} {ACC1:acc#513.itm(2)} -attr xrf 63565 -attr oid 755 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load net {ACC1-2:exs#1050.itm(0)} -attr vt d
+load net {ACC1-2:exs#1050.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1050.itm} 2 {ACC1-2:exs#1050.itm(0)} {ACC1-2:exs#1050.itm(1)} -attr xrf 63566 -attr oid 756 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1050.itm}
+load net {ACC1-2:exs#1031.itm(0)} -attr vt d
+load net {ACC1-2:exs#1031.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1031.itm} 2 {ACC1-2:exs#1031.itm(0)} {ACC1-2:exs#1031.itm(1)} -attr xrf 63567 -attr oid 757 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1031.itm}
+load net {ACC1:acc#565.itm(0)} -attr vt d
+load net {ACC1:acc#565.itm(1)} -attr vt d
+load net {ACC1:acc#565.itm(2)} -attr vt d
+load net {ACC1:acc#565.itm(3)} -attr vt d
+load netBundle {ACC1:acc#565.itm} 4 {ACC1:acc#565.itm(0)} {ACC1:acc#565.itm(1)} {ACC1:acc#565.itm(2)} {ACC1:acc#565.itm(3)} -attr xrf 63568 -attr oid 758 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#510.itm(0)} -attr vt d
+load net {ACC1:acc#510.itm(1)} -attr vt d
+load net {ACC1:acc#510.itm(2)} -attr vt d
+load netBundle {ACC1:acc#510.itm} 3 {ACC1:acc#510.itm(0)} {ACC1:acc#510.itm(1)} {ACC1:acc#510.itm(2)} -attr xrf 63569 -attr oid 759 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load net {ACC1-3:exs#1060.itm(0)} -attr vt d
+load net {ACC1-3:exs#1060.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1060.itm} 2 {ACC1-3:exs#1060.itm(0)} {ACC1-3:exs#1060.itm(1)} -attr xrf 63570 -attr oid 760 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1060.itm}
+load net {ACC1-3:exs#1049.itm(0)} -attr vt d
+load net {ACC1-3:exs#1049.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1049.itm} 2 {ACC1-3:exs#1049.itm(0)} {ACC1-3:exs#1049.itm(1)} -attr xrf 63571 -attr oid 761 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1049.itm}
+load net {ACC1:acc#621.itm(0)} -attr vt d
+load net {ACC1:acc#621.itm(1)} -attr vt d
+load net {ACC1:acc#621.itm(2)} -attr vt d
+load net {ACC1:acc#621.itm(3)} -attr vt d
+load net {ACC1:acc#621.itm(4)} -attr vt d
+load net {ACC1:acc#621.itm(5)} -attr vt d
+load net {ACC1:acc#621.itm(6)} -attr vt d
+load netBundle {ACC1:acc#621.itm} 7 {ACC1:acc#621.itm(0)} {ACC1:acc#621.itm(1)} {ACC1:acc#621.itm(2)} {ACC1:acc#621.itm(3)} {ACC1:acc#621.itm(4)} {ACC1:acc#621.itm(5)} {ACC1:acc#621.itm(6)} -attr xrf 63572 -attr oid 762 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#603.itm(0)} -attr vt d
+load net {ACC1:acc#603.itm(1)} -attr vt d
+load net {ACC1:acc#603.itm(2)} -attr vt d
+load net {ACC1:acc#603.itm(3)} -attr vt d
+load net {ACC1:acc#603.itm(4)} -attr vt d
+load net {ACC1:acc#603.itm(5)} -attr vt d
+load netBundle {ACC1:acc#603.itm} 6 {ACC1:acc#603.itm(0)} {ACC1:acc#603.itm(1)} {ACC1:acc#603.itm(2)} {ACC1:acc#603.itm(3)} {ACC1:acc#603.itm(4)} {ACC1:acc#603.itm(5)} -attr xrf 63573 -attr oid 763 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#577.itm(0)} -attr vt d
+load net {ACC1:acc#577.itm(1)} -attr vt d
+load net {ACC1:acc#577.itm(2)} -attr vt d
+load net {ACC1:acc#577.itm(3)} -attr vt d
+load net {ACC1:acc#577.itm(4)} -attr vt d
+load netBundle {ACC1:acc#577.itm} 5 {ACC1:acc#577.itm(0)} {ACC1:acc#577.itm(1)} {ACC1:acc#577.itm(2)} {ACC1:acc#577.itm(3)} {ACC1:acc#577.itm(4)} -attr xrf 63574 -attr oid 764 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#523.itm(0)} -attr vt d
+load net {ACC1:acc#523.itm(1)} -attr vt d
+load net {ACC1:acc#523.itm(2)} -attr vt d
+load net {ACC1:acc#523.itm(3)} -attr vt d
+load netBundle {ACC1:acc#523.itm} 4 {ACC1:acc#523.itm(0)} {ACC1:acc#523.itm(1)} {ACC1:acc#523.itm(2)} {ACC1:acc#523.itm(3)} -attr xrf 63575 -attr oid 765 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:conc#1098.itm(0)} -attr vt d
+load net {ACC1:conc#1098.itm(1)} -attr vt d
+load net {ACC1:conc#1098.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1098.itm} 3 {ACC1:conc#1098.itm(0)} {ACC1:conc#1098.itm(1)} {ACC1:conc#1098.itm(2)} -attr xrf 63576 -attr oid 766 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1098.itm}
+load net {conc#983.itm(0)} -attr vt d
+load net {conc#983.itm(1)} -attr vt d
+load net {conc#983.itm(2)} -attr vt d
+load netBundle {conc#983.itm} 3 {conc#983.itm(0)} {conc#983.itm(1)} {conc#983.itm(2)} -attr xrf 63577 -attr oid 767 -attr vt d -attr @path {/sobel/sobel:core/conc#983.itm}
+load net {ACC1:conc#1457.itm(0)} -attr vt d
+load net {ACC1:conc#1457.itm(1)} -attr vt d
+load net {ACC1:conc#1457.itm(2)} -attr vt d
+load net {ACC1:conc#1457.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1457.itm} 4 {ACC1:conc#1457.itm(0)} {ACC1:conc#1457.itm(1)} {ACC1:conc#1457.itm(2)} {ACC1:conc#1457.itm(3)} -attr xrf 63578 -attr oid 768 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1457.itm}
+load net {slc.itm(0)} -attr vt d
+load net {slc.itm(1)} -attr vt d
+load netBundle {slc.itm} 2 {slc.itm(0)} {slc.itm(1)} -attr xrf 63579 -attr oid 769 -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(0)} -attr vt d
+load net {acc.itm(1)} -attr vt d
+load net {acc.itm(2)} -attr vt d
+load netBundle {acc.itm} 3 {acc.itm(0)} {acc.itm(1)} {acc.itm(2)} -attr xrf 63580 -attr oid 770 -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {conc#984.itm(0)} -attr vt d
+load net {conc#984.itm(1)} -attr vt d
+load netBundle {conc#984.itm} 2 {conc#984.itm(0)} {conc#984.itm(1)} -attr xrf 63581 -attr oid 771 -attr vt d -attr @path {/sobel/sobel:core/conc#984.itm}
+load net {conc#985.itm(0)} -attr vt d
+load net {conc#985.itm(1)} -attr vt d
+load netBundle {conc#985.itm} 2 {conc#985.itm(0)} {conc#985.itm(1)} -attr xrf 63582 -attr oid 772 -attr vt d -attr @path {/sobel/sobel:core/conc#985.itm}
+load net {ACC1:acc#732.itm(0)} -attr vt d
+load net {ACC1:acc#732.itm(1)} -attr vt d
+load netBundle {ACC1:acc#732.itm} 2 {ACC1:acc#732.itm(0)} {ACC1:acc#732.itm(1)} -attr xrf 63583 -attr oid 773 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#732.itm}
+load net {conc#986.itm(0)} -attr vt d
+load net {conc#986.itm(1)} -attr vt d
+load netBundle {conc#986.itm} 2 {conc#986.itm(0)} {conc#986.itm(1)} -attr xrf 63584 -attr oid 774 -attr vt d -attr @path {/sobel/sobel:core/conc#986.itm}
+load net {conc#987.itm(0)} -attr vt d
+load net {conc#987.itm(1)} -attr vt d
+load netBundle {conc#987.itm} 2 {conc#987.itm(0)} {conc#987.itm(1)} -attr xrf 63585 -attr oid 775 -attr vt d -attr @path {/sobel/sobel:core/conc#987.itm}
+load net {ACC1:acc#576.itm(0)} -attr vt d
+load net {ACC1:acc#576.itm(1)} -attr vt d
+load net {ACC1:acc#576.itm(2)} -attr vt d
+load net {ACC1:acc#576.itm(3)} -attr vt d
+load net {ACC1:acc#576.itm(4)} -attr vt d
+load netBundle {ACC1:acc#576.itm} 5 {ACC1:acc#576.itm(0)} {ACC1:acc#576.itm(1)} {ACC1:acc#576.itm(2)} {ACC1:acc#576.itm(3)} {ACC1:acc#576.itm(4)} -attr xrf 63586 -attr oid 776 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:conc#1458.itm(0)} -attr vt d
+load net {ACC1:conc#1458.itm(1)} -attr vt d
+load net {ACC1:conc#1458.itm(2)} -attr vt d
+load net {ACC1:conc#1458.itm(3)} -attr vt d
+load netBundle {ACC1:conc#1458.itm} 4 {ACC1:conc#1458.itm(0)} {ACC1:conc#1458.itm(1)} {ACC1:conc#1458.itm(2)} {ACC1:conc#1458.itm(3)} -attr xrf 63587 -attr oid 777 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1458.itm}
+load net {slc#1.itm(0)} -attr vt d
+load net {slc#1.itm(1)} -attr vt d
+load netBundle {slc#1.itm} 2 {slc#1.itm(0)} {slc#1.itm(1)} -attr xrf 63588 -attr oid 778 -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#31.itm(0)} -attr vt d
+load net {acc#31.itm(1)} -attr vt d
+load net {acc#31.itm(2)} -attr vt d
+load netBundle {acc#31.itm} 3 {acc#31.itm(0)} {acc#31.itm(1)} {acc#31.itm(2)} -attr xrf 63589 -attr oid 779 -attr vt d -attr @path {/sobel/sobel:core/acc#31.itm}
+load net {conc#988.itm(0)} -attr vt d
+load net {conc#988.itm(1)} -attr vt d
+load netBundle {conc#988.itm} 2 {conc#988.itm(0)} {conc#988.itm(1)} -attr xrf 63590 -attr oid 780 -attr vt d -attr @path {/sobel/sobel:core/conc#988.itm}
+load net {conc#989.itm(0)} -attr vt d
+load net {conc#989.itm(1)} -attr vt d
+load netBundle {conc#989.itm} 2 {conc#989.itm(0)} {conc#989.itm(1)} -attr xrf 63591 -attr oid 781 -attr vt d -attr @path {/sobel/sobel:core/conc#989.itm}
+load net {ACC1:acc#734.itm(0)} -attr vt d
+load net {ACC1:acc#734.itm(1)} -attr vt d
+load netBundle {ACC1:acc#734.itm} 2 {ACC1:acc#734.itm(0)} {ACC1:acc#734.itm(1)} -attr xrf 63592 -attr oid 782 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#734.itm}
+load net {conc#990.itm(0)} -attr vt d
+load net {conc#990.itm(1)} -attr vt d
+load netBundle {conc#990.itm} 2 {conc#990.itm(0)} {conc#990.itm(1)} -attr xrf 63593 -attr oid 783 -attr vt d -attr @path {/sobel/sobel:core/conc#990.itm}
+load net {conc#991.itm(0)} -attr vt d
+load net {conc#991.itm(1)} -attr vt d
+load netBundle {conc#991.itm} 2 {conc#991.itm(0)} {conc#991.itm(1)} -attr xrf 63594 -attr oid 784 -attr vt d -attr @path {/sobel/sobel:core/conc#991.itm}
+load net {ACC1:acc#520.itm(0)} -attr vt d
+load net {ACC1:acc#520.itm(1)} -attr vt d
+load net {ACC1:acc#520.itm(2)} -attr vt d
+load net {ACC1:acc#520.itm(3)} -attr vt d
+load netBundle {ACC1:acc#520.itm} 4 {ACC1:acc#520.itm(0)} {ACC1:acc#520.itm(1)} {ACC1:acc#520.itm(2)} {ACC1:acc#520.itm(3)} -attr xrf 63595 -attr oid 785 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {conc#992.itm(0)} -attr vt d
+load net {conc#992.itm(1)} -attr vt d
+load net {conc#992.itm(2)} -attr vt d
+load netBundle {conc#992.itm} 3 {conc#992.itm(0)} {conc#992.itm(1)} {conc#992.itm(2)} -attr xrf 63596 -attr oid 786 -attr vt d -attr @path {/sobel/sobel:core/conc#992.itm}
+load net {slc(ACC1:acc#221.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#221.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#221.psp.sva)#2.itm} 2 {slc(ACC1:acc#221.psp.sva)#2.itm(0)} {slc(ACC1:acc#221.psp.sva)#2.itm(1)} -attr xrf 63597 -attr oid 787 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp.sva)#2.itm}
+load net {ACC1:acc#602.itm(0)} -attr vt d
+load net {ACC1:acc#602.itm(1)} -attr vt d
+load net {ACC1:acc#602.itm(2)} -attr vt d
+load net {ACC1:acc#602.itm(3)} -attr vt d
+load net {ACC1:acc#602.itm(4)} -attr vt d
+load net {ACC1:acc#602.itm(5)} -attr vt d
+load netBundle {ACC1:acc#602.itm} 6 {ACC1:acc#602.itm(0)} {ACC1:acc#602.itm(1)} {ACC1:acc#602.itm(2)} {ACC1:acc#602.itm(3)} {ACC1:acc#602.itm(4)} {ACC1:acc#602.itm(5)} -attr xrf 63598 -attr oid 788 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#575.itm(0)} -attr vt d
+load net {ACC1:acc#575.itm(1)} -attr vt d
+load net {ACC1:acc#575.itm(2)} -attr vt d
+load net {ACC1:acc#575.itm(3)} -attr vt d
+load net {ACC1:acc#575.itm(4)} -attr vt d
+load netBundle {ACC1:acc#575.itm} 5 {ACC1:acc#575.itm(0)} {ACC1:acc#575.itm(1)} {ACC1:acc#575.itm(2)} {ACC1:acc#575.itm(3)} {ACC1:acc#575.itm(4)} -attr xrf 63599 -attr oid 789 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#518.itm(0)} -attr vt d
+load net {ACC1:acc#518.itm(1)} -attr vt d
+load net {ACC1:acc#518.itm(2)} -attr vt d
+load net {ACC1:acc#518.itm(3)} -attr vt d
+load netBundle {ACC1:acc#518.itm} 4 {ACC1:acc#518.itm(0)} {ACC1:acc#518.itm(1)} {ACC1:acc#518.itm(2)} {ACC1:acc#518.itm(3)} -attr xrf 63600 -attr oid 790 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {slc(ACC1:acc#221.psp#2.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#221.psp#2.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#221.psp#2.sva)#2.itm} 2 {slc(ACC1:acc#221.psp#2.sva)#2.itm(0)} {slc(ACC1:acc#221.psp#2.sva)#2.itm(1)} -attr xrf 63601 -attr oid 791 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp#2.sva)#2.itm}
+load net {ACC1-2:exs#19.itm(0)} -attr vt d
+load net {ACC1-2:exs#19.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#19.itm} 2 {ACC1-2:exs#19.itm(0)} {ACC1-2:exs#19.itm(1)} -attr xrf 63602 -attr oid 792 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#19.itm}
+load net {ACC1:acc#490.itm(0)} -attr vt d
+load net {ACC1:acc#490.itm(1)} -attr vt d
+load net {ACC1:acc#490.itm(2)} -attr vt d
+load net {ACC1:acc#490.itm(3)} -attr vt d
+load netBundle {ACC1:acc#490.itm} 4 {ACC1:acc#490.itm(0)} {ACC1:acc#490.itm(1)} {ACC1:acc#490.itm(2)} {ACC1:acc#490.itm(3)} -attr xrf 63603 -attr oid 793 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {slc(ACC1:acc#219.psp#2.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#219.psp#2.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#219.psp#2.sva)#2.itm} 2 {slc(ACC1:acc#219.psp#2.sva)#2.itm(0)} {slc(ACC1:acc#219.psp#2.sva)#2.itm(1)} -attr xrf 63604 -attr oid 794 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#2.sva)#2.itm}
+load net {ACC1-2:exs#1058.itm(0)} -attr vt d
+load net {ACC1-2:exs#1058.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1058.itm} 2 {ACC1-2:exs#1058.itm(0)} {ACC1-2:exs#1058.itm(1)} -attr xrf 63605 -attr oid 795 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1058.itm}
+load net {ACC1:acc#574.itm(0)} -attr vt d
+load net {ACC1:acc#574.itm(1)} -attr vt d
+load net {ACC1:acc#574.itm(2)} -attr vt d
+load net {ACC1:acc#574.itm(3)} -attr vt d
+load net {ACC1:acc#574.itm(4)} -attr vt d
+load netBundle {ACC1:acc#574.itm} 5 {ACC1:acc#574.itm(0)} {ACC1:acc#574.itm(1)} {ACC1:acc#574.itm(2)} {ACC1:acc#574.itm(3)} {ACC1:acc#574.itm(4)} -attr xrf 63606 -attr oid 796 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:slc#139.itm(0)} -attr vt d
+load net {ACC1:slc#139.itm(1)} -attr vt d
+load net {ACC1:slc#139.itm(2)} -attr vt d
+load net {ACC1:slc#139.itm(3)} -attr vt d
+load netBundle {ACC1:slc#139.itm} 4 {ACC1:slc#139.itm(0)} {ACC1:slc#139.itm(1)} {ACC1:slc#139.itm(2)} {ACC1:slc#139.itm(3)} -attr xrf 63607 -attr oid 797 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#139.itm}
+load net {ACC1:acc#471.itm(0)} -attr vt d
+load net {ACC1:acc#471.itm(1)} -attr vt d
+load net {ACC1:acc#471.itm(2)} -attr vt d
+load net {ACC1:acc#471.itm(3)} -attr vt d
+load net {ACC1:acc#471.itm(4)} -attr vt d
+load netBundle {ACC1:acc#471.itm} 5 {ACC1:acc#471.itm(0)} {ACC1:acc#471.itm(1)} {ACC1:acc#471.itm(2)} {ACC1:acc#471.itm(3)} {ACC1:acc#471.itm(4)} -attr xrf 63608 -attr oid 798 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471.itm}
+load net {exs#90.itm(0)} -attr vt d
+load net {exs#90.itm(1)} -attr vt d
+load net {exs#90.itm(2)} -attr vt d
+load netBundle {exs#90.itm} 3 {exs#90.itm(0)} {exs#90.itm(1)} {exs#90.itm(2)} -attr xrf 63609 -attr oid 799 -attr vt d -attr @path {/sobel/sobel:core/exs#90.itm}
+load net {conc#993.itm(0)} -attr vt d
+load net {conc#993.itm(1)} -attr vt d
+load netBundle {conc#993.itm} 2 {conc#993.itm(0)} {conc#993.itm(1)} -attr xrf 63610 -attr oid 800 -attr vt d -attr @path {/sobel/sobel:core/conc#993.itm}
+load net {ACC1:conc#1401.itm(0)} -attr vt d
+load net {ACC1:conc#1401.itm(1)} -attr vt d
+load net {ACC1:conc#1401.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1401.itm} 3 {ACC1:conc#1401.itm(0)} {ACC1:conc#1401.itm(1)} {ACC1:conc#1401.itm(2)} -attr xrf 63611 -attr oid 801 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1401.itm}
+load net {slc(ACC1:acc#222.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#222.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#222.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#222.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#222.psp#1.sva)#2.itm(1)} -attr xrf 63612 -attr oid 802 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp#1.sva)#2.itm}
+load net {ACC1:slc#129.itm(0)} -attr vt d
+load net {ACC1:slc#129.itm(1)} -attr vt d
+load net {ACC1:slc#129.itm(2)} -attr vt d
+load net {ACC1:slc#129.itm(3)} -attr vt d
+load netBundle {ACC1:slc#129.itm} 4 {ACC1:slc#129.itm(0)} {ACC1:slc#129.itm(1)} {ACC1:slc#129.itm(2)} {ACC1:slc#129.itm(3)} -attr xrf 63613 -attr oid 803 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#129.itm}
+load net {ACC1:acc#461.itm(0)} -attr vt d
+load net {ACC1:acc#461.itm(1)} -attr vt d
+load net {ACC1:acc#461.itm(2)} -attr vt d
+load net {ACC1:acc#461.itm(3)} -attr vt d
+load net {ACC1:acc#461.itm(4)} -attr vt d
+load netBundle {ACC1:acc#461.itm} 5 {ACC1:acc#461.itm(0)} {ACC1:acc#461.itm(1)} {ACC1:acc#461.itm(2)} {ACC1:acc#461.itm(3)} {ACC1:acc#461.itm(4)} -attr xrf 63614 -attr oid 804 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461.itm}
+load net {conc#994.itm(0)} -attr vt d
+load net {conc#994.itm(1)} -attr vt d
+load net {conc#994.itm(2)} -attr vt d
+load netBundle {conc#994.itm} 3 {conc#994.itm(0)} {conc#994.itm(1)} {conc#994.itm(2)} -attr xrf 63615 -attr oid 805 -attr vt d -attr @path {/sobel/sobel:core/conc#994.itm}
+load net {slc(ACC1:acc#219.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#219.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#219.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#219.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#219.psp#1.sva)#2.itm(1)} -attr xrf 63616 -attr oid 806 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#1.sva)#2.itm}
+load net {ACC1:exs#1590.itm(0)} -attr vt d
+load net {ACC1:exs#1590.itm(1)} -attr vt d
+load net {ACC1:exs#1590.itm(2)} -attr vt d
+load netBundle {ACC1:exs#1590.itm} 3 {ACC1:exs#1590.itm(0)} {ACC1:exs#1590.itm(1)} {ACC1:exs#1590.itm(2)} -attr xrf 63617 -attr oid 807 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1590.itm}
+load net {ACC1:conc#1381.itm(0)} -attr vt d
+load net {ACC1:conc#1381.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1381.itm} 2 {ACC1:conc#1381.itm(0)} {ACC1:conc#1381.itm(1)} -attr xrf 63618 -attr oid 808 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1381.itm}
+load net {ACC1:acc#639.itm(0)} -attr vt d
+load net {ACC1:acc#639.itm(1)} -attr vt d
+load net {ACC1:acc#639.itm(2)} -attr vt d
+load net {ACC1:acc#639.itm(3)} -attr vt d
+load net {ACC1:acc#639.itm(4)} -attr vt d
+load net {ACC1:acc#639.itm(5)} -attr vt d
+load net {ACC1:acc#639.itm(6)} -attr vt d
+load net {ACC1:acc#639.itm(7)} -attr vt d
+load net {ACC1:acc#639.itm(8)} -attr vt d
+load netBundle {ACC1:acc#639.itm} 9 {ACC1:acc#639.itm(0)} {ACC1:acc#639.itm(1)} {ACC1:acc#639.itm(2)} {ACC1:acc#639.itm(3)} {ACC1:acc#639.itm(4)} {ACC1:acc#639.itm(5)} {ACC1:acc#639.itm(6)} {ACC1:acc#639.itm(7)} {ACC1:acc#639.itm(8)} -attr xrf 63619 -attr oid 809 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:mul.itm(0)} -attr vt d
+load net {ACC1:mul.itm(1)} -attr vt d
+load net {ACC1:mul.itm(2)} -attr vt d
+load net {ACC1:mul.itm(3)} -attr vt d
+load net {ACC1:mul.itm(4)} -attr vt d
+load net {ACC1:mul.itm(5)} -attr vt d
+load net {ACC1:mul.itm(6)} -attr vt d
+load net {ACC1:mul.itm(7)} -attr vt d
+load netBundle {ACC1:mul.itm} 8 {ACC1:mul.itm(0)} {ACC1:mul.itm(1)} {ACC1:mul.itm(2)} {ACC1:mul.itm(3)} {ACC1:mul.itm(4)} {ACC1:mul.itm(5)} {ACC1:mul.itm(6)} {ACC1:mul.itm(7)} -attr xrf 63620 -attr oid 810 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:acc#295.itm(0)} -attr vt d
+load net {ACC1:acc#295.itm(1)} -attr vt d
+load net {ACC1:acc#295.itm(2)} -attr vt d
+load net {ACC1:acc#295.itm(3)} -attr vt d
+load netBundle {ACC1:acc#295.itm} 4 {ACC1:acc#295.itm(0)} {ACC1:acc#295.itm(1)} {ACC1:acc#295.itm(2)} {ACC1:acc#295.itm(3)} -attr xrf 63621 -attr oid 811 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#296.itm(0)} -attr vt d
+load net {ACC1:acc#296.itm(1)} -attr vt d
+load net {ACC1:acc#296.itm(2)} -attr vt d
+load netBundle {ACC1:acc#296.itm} 3 {ACC1:acc#296.itm(0)} {ACC1:acc#296.itm(1)} {ACC1:acc#296.itm(2)} -attr xrf 63622 -attr oid 812 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#297.itm(0)} -attr vt d
+load net {ACC1:acc#297.itm(1)} -attr vt d
+load net {ACC1:acc#297.itm(2)} -attr vt d
+load netBundle {ACC1:acc#297.itm} 3 {ACC1:acc#297.itm(0)} {ACC1:acc#297.itm(1)} {ACC1:acc#297.itm(2)} -attr xrf 63623 -attr oid 813 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#298.itm(0)} -attr vt d
+load net {ACC1:acc#298.itm(1)} -attr vt d
+load net {ACC1:acc#298.itm(2)} -attr vt d
+load netBundle {ACC1:acc#298.itm} 3 {ACC1:acc#298.itm(0)} {ACC1:acc#298.itm(1)} {ACC1:acc#298.itm(2)} -attr xrf 63624 -attr oid 814 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#299.itm(0)} -attr vt d
+load net {ACC1:acc#299.itm(1)} -attr vt d
+load net {ACC1:acc#299.itm(2)} -attr vt d
+load netBundle {ACC1:acc#299.itm} 3 {ACC1:acc#299.itm(0)} {ACC1:acc#299.itm(1)} {ACC1:acc#299.itm(2)} -attr xrf 63625 -attr oid 815 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#300.itm(0)} -attr vt d
+load net {ACC1:acc#300.itm(1)} -attr vt d
+load netBundle {ACC1:acc#300.itm} 2 {ACC1:acc#300.itm(0)} {ACC1:acc#300.itm(1)} -attr xrf 63626 -attr oid 816 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#301.itm(0)} -attr vt d
+load net {ACC1:acc#301.itm(1)} -attr vt d
+load netBundle {ACC1:acc#301.itm} 2 {ACC1:acc#301.itm(0)} {ACC1:acc#301.itm(1)} -attr xrf 63627 -attr oid 817 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {conc#995.itm(0)} -attr vt d
+load net {conc#995.itm(1)} -attr vt d
+load net {conc#995.itm(2)} -attr vt d
+load net {conc#995.itm(3)} -attr vt d
+load net {conc#995.itm(4)} -attr vt d
+load net {conc#995.itm(5)} -attr vt d
+load net {conc#995.itm(6)} -attr vt d
+load net {conc#995.itm(7)} -attr vt d
+load netBundle {conc#995.itm} 8 {conc#995.itm(0)} {conc#995.itm(1)} {conc#995.itm(2)} {conc#995.itm(3)} {conc#995.itm(4)} {conc#995.itm(5)} {conc#995.itm(6)} {conc#995.itm(7)} -attr xrf 63628 -attr oid 818 -attr vt d -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {slc(regs.regs(1).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#2.itm} 10 {slc(regs.regs(1).sva)#2.itm(0)} {slc(regs.regs(1).sva)#2.itm(1)} {slc(regs.regs(1).sva)#2.itm(2)} {slc(regs.regs(1).sva)#2.itm(3)} {slc(regs.regs(1).sva)#2.itm(4)} {slc(regs.regs(1).sva)#2.itm(5)} {slc(regs.regs(1).sva)#2.itm(6)} {slc(regs.regs(1).sva)#2.itm(7)} {slc(regs.regs(1).sva)#2.itm(8)} {slc(regs.regs(1).sva)#2.itm(9)} -attr xrf 63629 -attr oid 819 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {slc(regs.regs(1).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#1.itm} 10 {slc(regs.regs(1).sva)#1.itm(0)} {slc(regs.regs(1).sva)#1.itm(1)} {slc(regs.regs(1).sva)#1.itm(2)} {slc(regs.regs(1).sva)#1.itm(3)} {slc(regs.regs(1).sva)#1.itm(4)} {slc(regs.regs(1).sva)#1.itm(5)} {slc(regs.regs(1).sva)#1.itm(6)} {slc(regs.regs(1).sva)#1.itm(7)} {slc(regs.regs(1).sva)#1.itm(8)} {slc(regs.regs(1).sva)#1.itm(9)} -attr xrf 63630 -attr oid 820 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {slc(regs.regs(1).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva).itm} 10 {slc(regs.regs(1).sva).itm(0)} {slc(regs.regs(1).sva).itm(1)} {slc(regs.regs(1).sva).itm(2)} {slc(regs.regs(1).sva).itm(3)} {slc(regs.regs(1).sva).itm(4)} {slc(regs.regs(1).sva).itm(5)} {slc(regs.regs(1).sva).itm(6)} {slc(regs.regs(1).sva).itm(7)} {slc(regs.regs(1).sva).itm(8)} {slc(regs.regs(1).sva).itm(9)} -attr xrf 63631 -attr oid 821 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {slc(regs.regs(1).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#5.itm} 10 {slc(regs.regs(1).sva)#5.itm(0)} {slc(regs.regs(1).sva)#5.itm(1)} {slc(regs.regs(1).sva)#5.itm(2)} {slc(regs.regs(1).sva)#5.itm(3)} {slc(regs.regs(1).sva)#5.itm(4)} {slc(regs.regs(1).sva)#5.itm(5)} {slc(regs.regs(1).sva)#5.itm(6)} {slc(regs.regs(1).sva)#5.itm(7)} {slc(regs.regs(1).sva)#5.itm(8)} {slc(regs.regs(1).sva)#5.itm(9)} -attr xrf 63632 -attr oid 822 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {slc(regs.regs(1).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#4.itm} 10 {slc(regs.regs(1).sva)#4.itm(0)} {slc(regs.regs(1).sva)#4.itm(1)} {slc(regs.regs(1).sva)#4.itm(2)} {slc(regs.regs(1).sva)#4.itm(3)} {slc(regs.regs(1).sva)#4.itm(4)} {slc(regs.regs(1).sva)#4.itm(5)} {slc(regs.regs(1).sva)#4.itm(6)} {slc(regs.regs(1).sva)#4.itm(7)} {slc(regs.regs(1).sva)#4.itm(8)} {slc(regs.regs(1).sva)#4.itm(9)} -attr xrf 63633 -attr oid 823 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {slc(regs.regs(1).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#3.itm} 10 {slc(regs.regs(1).sva)#3.itm(0)} {slc(regs.regs(1).sva)#3.itm(1)} {slc(regs.regs(1).sva)#3.itm(2)} {slc(regs.regs(1).sva)#3.itm(3)} {slc(regs.regs(1).sva)#3.itm(4)} {slc(regs.regs(1).sva)#3.itm(5)} {slc(regs.regs(1).sva)#3.itm(6)} {slc(regs.regs(1).sva)#3.itm(7)} {slc(regs.regs(1).sva)#3.itm(8)} {slc(regs.regs(1).sva)#3.itm(9)} -attr xrf 63634 -attr oid 824 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {slc(regs.regs(1).sva)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#8.itm} 10 {slc(regs.regs(1).sva)#8.itm(0)} {slc(regs.regs(1).sva)#8.itm(1)} {slc(regs.regs(1).sva)#8.itm(2)} {slc(regs.regs(1).sva)#8.itm(3)} {slc(regs.regs(1).sva)#8.itm(4)} {slc(regs.regs(1).sva)#8.itm(5)} {slc(regs.regs(1).sva)#8.itm(6)} {slc(regs.regs(1).sva)#8.itm(7)} {slc(regs.regs(1).sva)#8.itm(8)} {slc(regs.regs(1).sva)#8.itm(9)} -attr xrf 63635 -attr oid 825 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {slc(regs.regs(1).sva)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#7.itm} 10 {slc(regs.regs(1).sva)#7.itm(0)} {slc(regs.regs(1).sva)#7.itm(1)} {slc(regs.regs(1).sva)#7.itm(2)} {slc(regs.regs(1).sva)#7.itm(3)} {slc(regs.regs(1).sva)#7.itm(4)} {slc(regs.regs(1).sva)#7.itm(5)} {slc(regs.regs(1).sva)#7.itm(6)} {slc(regs.regs(1).sva)#7.itm(7)} {slc(regs.regs(1).sva)#7.itm(8)} {slc(regs.regs(1).sva)#7.itm(9)} -attr xrf 63636 -attr oid 826 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {slc(regs.regs(1).sva)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#6.itm} 10 {slc(regs.regs(1).sva)#6.itm(0)} {slc(regs.regs(1).sva)#6.itm(1)} {slc(regs.regs(1).sva)#6.itm(2)} {slc(regs.regs(1).sva)#6.itm(3)} {slc(regs.regs(1).sva)#6.itm(4)} {slc(regs.regs(1).sva)#6.itm(5)} {slc(regs.regs(1).sva)#6.itm(6)} {slc(regs.regs(1).sva)#6.itm(7)} {slc(regs.regs(1).sva)#6.itm(8)} {slc(regs.regs(1).sva)#6.itm(9)} -attr xrf 63637 -attr oid 827 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {FRAME:acc#15.itm(0)} -attr vt d
+load net {FRAME:acc#15.itm(1)} -attr vt d
+load net {FRAME:acc#15.itm(2)} -attr vt d
+load net {FRAME:acc#15.itm(3)} -attr vt d
+load net {FRAME:acc#15.itm(4)} -attr vt d
+load net {FRAME:acc#15.itm(5)} -attr vt d
+load net {FRAME:acc#15.itm(6)} -attr vt d
+load net {FRAME:acc#15.itm(7)} -attr vt d
+load net {FRAME:acc#15.itm(8)} -attr vt d
+load net {FRAME:acc#15.itm(9)} -attr vt d
+load net {FRAME:acc#15.itm(10)} -attr vt d
+load net {FRAME:acc#15.itm(11)} -attr vt d
+load netBundle {FRAME:acc#15.itm} 12 {FRAME:acc#15.itm(0)} {FRAME:acc#15.itm(1)} {FRAME:acc#15.itm(2)} {FRAME:acc#15.itm(3)} {FRAME:acc#15.itm(4)} {FRAME:acc#15.itm(5)} {FRAME:acc#15.itm(6)} {FRAME:acc#15.itm(7)} {FRAME:acc#15.itm(8)} {FRAME:acc#15.itm(9)} {FRAME:acc#15.itm(10)} {FRAME:acc#15.itm(11)} -attr xrf 63638 -attr oid 828 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:mul.itm(0)} -attr vt d
+load net {FRAME:mul.itm(1)} -attr vt d
+load net {FRAME:mul.itm(2)} -attr vt d
+load net {FRAME:mul.itm(3)} -attr vt d
+load net {FRAME:mul.itm(4)} -attr vt d
+load net {FRAME:mul.itm(5)} -attr vt d
+load net {FRAME:mul.itm(6)} -attr vt d
+load net {FRAME:mul.itm(7)} -attr vt d
+load net {FRAME:mul.itm(8)} -attr vt d
+load net {FRAME:mul.itm(9)} -attr vt d
+load net {FRAME:mul.itm(10)} -attr vt d
+load netBundle {FRAME:mul.itm} 11 {FRAME:mul.itm(0)} {FRAME:mul.itm(1)} {FRAME:mul.itm(2)} {FRAME:mul.itm(3)} {FRAME:mul.itm(4)} {FRAME:mul.itm(5)} {FRAME:mul.itm(6)} {FRAME:mul.itm(7)} {FRAME:mul.itm(8)} {FRAME:mul.itm(9)} {FRAME:mul.itm(10)} -attr xrf 63639 -attr oid 829 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {slc(ACC1:slc.psp.sva)#13.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#13.itm(1)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#13.itm} 2 {slc(ACC1:slc.psp.sva)#13.itm(0)} {slc(ACC1:slc.psp.sva)#13.itm(1)} -attr xrf 63640 -attr oid 830 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#13.itm}
+load net {FRAME:acc#14.itm(0)} -attr vt d
+load net {FRAME:acc#14.itm(1)} -attr vt d
+load net {FRAME:acc#14.itm(2)} -attr vt d
+load net {FRAME:acc#14.itm(3)} -attr vt d
+load net {FRAME:acc#14.itm(4)} -attr vt d
+load net {FRAME:acc#14.itm(5)} -attr vt d
+load net {FRAME:acc#14.itm(6)} -attr vt d
+load net {FRAME:acc#14.itm(7)} -attr vt d
+load net {FRAME:acc#14.itm(8)} -attr vt d
+load net {FRAME:acc#14.itm(9)} -attr vt d
+load netBundle {FRAME:acc#14.itm} 10 {FRAME:acc#14.itm(0)} {FRAME:acc#14.itm(1)} {FRAME:acc#14.itm(2)} {FRAME:acc#14.itm(3)} {FRAME:acc#14.itm(4)} {FRAME:acc#14.itm(5)} {FRAME:acc#14.itm(6)} {FRAME:acc#14.itm(7)} {FRAME:acc#14.itm(8)} {FRAME:acc#14.itm(9)} -attr xrf 63641 -attr oid 831 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:mul#1.itm(0)} -attr vt d
+load net {FRAME:mul#1.itm(1)} -attr vt d
+load net {FRAME:mul#1.itm(2)} -attr vt d
+load net {FRAME:mul#1.itm(3)} -attr vt d
+load net {FRAME:mul#1.itm(4)} -attr vt d
+load net {FRAME:mul#1.itm(5)} -attr vt d
+load net {FRAME:mul#1.itm(6)} -attr vt d
+load net {FRAME:mul#1.itm(7)} -attr vt d
+load net {FRAME:mul#1.itm(8)} -attr vt d
+load netBundle {FRAME:mul#1.itm} 9 {FRAME:mul#1.itm(0)} {FRAME:mul#1.itm(1)} {FRAME:mul#1.itm(2)} {FRAME:mul#1.itm(3)} {FRAME:mul#1.itm(4)} {FRAME:mul#1.itm(5)} {FRAME:mul#1.itm(6)} {FRAME:mul#1.itm(7)} {FRAME:mul#1.itm(8)} -attr xrf 63642 -attr oid 832 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {slc(ACC1:slc.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#1.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#1.itm} 3 {slc(ACC1:slc.psp.sva)#1.itm(0)} {slc(ACC1:slc.psp.sva)#1.itm(1)} {slc(ACC1:slc.psp.sva)#1.itm(2)} -attr xrf 63643 -attr oid 833 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#1.itm}
+load net {FRAME:acc#13.itm(0)} -attr vt d
+load net {FRAME:acc#13.itm(1)} -attr vt d
+load net {FRAME:acc#13.itm(2)} -attr vt d
+load net {FRAME:acc#13.itm(3)} -attr vt d
+load net {FRAME:acc#13.itm(4)} -attr vt d
+load net {FRAME:acc#13.itm(5)} -attr vt d
+load net {FRAME:acc#13.itm(6)} -attr vt d
+load netBundle {FRAME:acc#13.itm} 7 {FRAME:acc#13.itm(0)} {FRAME:acc#13.itm(1)} {FRAME:acc#13.itm(2)} {FRAME:acc#13.itm(3)} {FRAME:acc#13.itm(4)} {FRAME:acc#13.itm(5)} {FRAME:acc#13.itm(6)} -attr xrf 63644 -attr oid 834 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {slc(ACC1:slc.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#2.itm(2)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#2.itm(3)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#2.itm(4)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#2.itm} 6 {slc(ACC1:slc.psp.sva)#2.itm(0)} {slc(ACC1:slc.psp.sva)#2.itm(1)} {slc(ACC1:slc.psp.sva)#2.itm(2)} {slc(ACC1:slc.psp.sva)#2.itm(3)} {slc(ACC1:slc.psp.sva)#2.itm(4)} {slc(ACC1:slc.psp.sva)#2.itm(5)} -attr xrf 63645 -attr oid 835 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#2.itm}
+load net {FRAME:acc#12.itm(0)} -attr vt d
+load net {FRAME:acc#12.itm(1)} -attr vt d
+load net {FRAME:acc#12.itm(2)} -attr vt d
+load net {FRAME:acc#12.itm(3)} -attr vt d
+load net {FRAME:acc#12.itm(4)} -attr vt d
+load netBundle {FRAME:acc#12.itm} 5 {FRAME:acc#12.itm(0)} {FRAME:acc#12.itm(1)} {FRAME:acc#12.itm(2)} {FRAME:acc#12.itm(3)} {FRAME:acc#12.itm(4)} -attr xrf 63646 -attr oid 836 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {conc#996.itm(0)} -attr vt d
+load net {conc#996.itm(1)} -attr vt d
+load net {conc#996.itm(2)} -attr vt d
+load net {conc#996.itm(3)} -attr vt d
+load net {conc#996.itm(4)} -attr vt d
+load netBundle {conc#996.itm} 5 {conc#996.itm(0)} {conc#996.itm(1)} {conc#996.itm(2)} {conc#996.itm(3)} {conc#996.itm(4)} -attr xrf 63647 -attr oid 837 -attr vt d -attr @path {/sobel/sobel:core/conc#996.itm}
+load net {FRAME:acc#11.itm(0)} -attr vt d
+load net {FRAME:acc#11.itm(1)} -attr vt d
+load net {FRAME:acc#11.itm(2)} -attr vt d
+load net {FRAME:acc#11.itm(3)} -attr vt d
+load netBundle {FRAME:acc#11.itm} 4 {FRAME:acc#11.itm(0)} {FRAME:acc#11.itm(1)} {FRAME:acc#11.itm(2)} {FRAME:acc#11.itm(3)} -attr xrf 63648 -attr oid 838 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#10.itm(0)} -attr vt d
+load net {FRAME:acc#10.itm(1)} -attr vt d
+load net {FRAME:acc#10.itm(2)} -attr vt d
+load net {FRAME:acc#10.itm(3)} -attr vt d
+load netBundle {FRAME:acc#10.itm} 4 {FRAME:acc#10.itm(0)} {FRAME:acc#10.itm(1)} {FRAME:acc#10.itm(2)} {FRAME:acc#10.itm(3)} -attr xrf 63649 -attr oid 839 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {conc#997.itm(0)} -attr vt d
+load net {conc#997.itm(1)} -attr vt d
+load net {conc#997.itm(2)} -attr vt d
+load netBundle {conc#997.itm} 3 {conc#997.itm(0)} {conc#997.itm(1)} {conc#997.itm(2)} -attr xrf 63650 -attr oid 840 -attr vt d -attr @path {/sobel/sobel:core/conc#997.itm}
+load net {conc#998.itm(0)} -attr vt d
+load net {conc#998.itm(1)} -attr vt d
+load net {conc#998.itm(2)} -attr vt d
+load net {conc#998.itm(3)} -attr vt d
+load net {conc#998.itm(4)} -attr vt d
+load netBundle {conc#998.itm} 5 {conc#998.itm(0)} {conc#998.itm(1)} {conc#998.itm(2)} {conc#998.itm(3)} {conc#998.itm(4)} -attr xrf 63651 -attr oid 841 -attr vt d -attr @path {/sobel/sobel:core/conc#998.itm}
+load net {slc(acc.imod#24.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#24.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#24.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#24.sva)#1.itm} 3 {slc(acc.imod#24.sva)#1.itm(0)} {slc(acc.imod#24.sva)#1.itm(1)} {slc(acc.imod#24.sva)#1.itm(2)} -attr xrf 63652 -attr oid 842 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#1.itm}
+load net {FRAME:conc#15.itm(0)} -attr vt d
+load net {FRAME:conc#15.itm(1)} -attr vt d
+load net {FRAME:conc#15.itm(2)} -attr vt d
+load net {FRAME:conc#15.itm(3)} -attr vt d
+load netBundle {FRAME:conc#15.itm} 4 {FRAME:conc#15.itm(0)} {FRAME:conc#15.itm(1)} {FRAME:conc#15.itm(2)} {FRAME:conc#15.itm(3)} -attr xrf 63653 -attr oid 843 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(0)} -attr vt d
+load net {FRAME:not#5.itm(1)} -attr vt d
+load net {FRAME:not#5.itm(2)} -attr vt d
+load netBundle {FRAME:not#5.itm} 3 {FRAME:not#5.itm(0)} {FRAME:not#5.itm(1)} {FRAME:not#5.itm(2)} -attr xrf 63654 -attr oid 844 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {slc(acc.imod#24.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#24.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#24.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#24.sva)#2.itm} 3 {slc(acc.imod#24.sva)#2.itm(0)} {slc(acc.imod#24.sva)#2.itm(1)} {slc(acc.imod#24.sva)#2.itm(2)} -attr xrf 63655 -attr oid 845 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#2.itm}
+load net {slc(acc.imod#24.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#24.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#24.sva)#4.itm} 2 {slc(acc.imod#24.sva)#4.itm(0)} {slc(acc.imod#24.sva)#4.itm(1)} -attr xrf 63656 -attr oid 846 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#4.itm}
+load net {FRAME:not#6.itm(0)} -attr vt d
+load net {FRAME:not#6.itm(1)} -attr vt d
+load net {FRAME:not#6.itm(2)} -attr vt d
+load netBundle {FRAME:not#6.itm} 3 {FRAME:not#6.itm(0)} {FRAME:not#6.itm(1)} {FRAME:not#6.itm(2)} -attr xrf 63657 -attr oid 847 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {slc(ACC1:slc.psp.sva)#3.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#3.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#3.itm} 3 {slc(ACC1:slc.psp.sva)#3.itm(0)} {slc(ACC1:slc.psp.sva)#3.itm(1)} {slc(ACC1:slc.psp.sva)#3.itm(2)} -attr xrf 63658 -attr oid 848 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#3.itm}
+load net {exs#103.itm(0)} -attr vt d
+load net {exs#103.itm(1)} -attr vt d
+load net {exs#103.itm(2)} -attr vt d
+load net {exs#103.itm(3)} -attr vt d
+load net {exs#103.itm(4)} -attr vt d
+load net {exs#103.itm(5)} -attr vt d
+load net {exs#103.itm(6)} -attr vt d
+load net {exs#103.itm(7)} -attr vt d
+load net {exs#103.itm(8)} -attr vt d
+load net {exs#103.itm(9)} -attr vt d
+load net {exs#103.itm(10)} -attr vt d
+load netBundle {exs#103.itm} 11 {exs#103.itm(0)} {exs#103.itm(1)} {exs#103.itm(2)} {exs#103.itm(3)} {exs#103.itm(4)} {exs#103.itm(5)} {exs#103.itm(6)} {exs#103.itm(7)} {exs#103.itm(8)} {exs#103.itm(9)} {exs#103.itm(10)} -attr xrf 63659 -attr oid 849 -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {conc#999.itm(0)} -attr vt d
+load net {conc#999.itm(1)} -attr vt d
+load net {conc#999.itm(2)} -attr vt d
+load net {conc#999.itm(3)} -attr vt d
+load net {conc#999.itm(4)} -attr vt d
+load net {conc#999.itm(5)} -attr vt d
+load net {conc#999.itm(6)} -attr vt d
+load net {conc#999.itm(7)} -attr vt d
+load net {conc#999.itm(8)} -attr vt d
+load netBundle {conc#999.itm} 9 {conc#999.itm(0)} {conc#999.itm(1)} {conc#999.itm(2)} {conc#999.itm(3)} {conc#999.itm(4)} {conc#999.itm(5)} {conc#999.itm(6)} {conc#999.itm(7)} {conc#999.itm(8)} -attr xrf 63660 -attr oid 850 -attr vt d -attr @path {/sobel/sobel:core/conc#999.itm}
+load net {FRAME:exs#5.itm(0)} -attr vt d
+load net {FRAME:exs#5.itm(1)} -attr vt d
+load net {FRAME:exs#5.itm(2)} -attr vt d
+load netBundle {FRAME:exs#5.itm} 3 {FRAME:exs#5.itm(0)} {FRAME:exs#5.itm(1)} {FRAME:exs#5.itm(2)} -attr xrf 63661 -attr oid 851 -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#5.itm}
+load net {ACC1:acc.itm(0)} -attr vt d
+load net {ACC1:acc.itm(1)} -attr vt d
+load net {ACC1:acc.itm(2)} -attr vt d
+load net {ACC1:acc.itm(3)} -attr vt d
+load net {ACC1:acc.itm(4)} -attr vt d
+load net {ACC1:acc.itm(5)} -attr vt d
+load net {ACC1:acc.itm(6)} -attr vt d
+load net {ACC1:acc.itm(7)} -attr vt d
+load net {ACC1:acc.itm(8)} -attr vt d
+load net {ACC1:acc.itm(9)} -attr vt d
+load net {ACC1:acc.itm(10)} -attr vt d
+load net {ACC1:acc.itm(11)} -attr vt d
+load net {ACC1:acc.itm(12)} -attr vt d
+load net {ACC1:acc.itm(13)} -attr vt d
+load net {ACC1:acc.itm(14)} -attr vt d
+load netBundle {ACC1:acc.itm} 15 {ACC1:acc.itm(0)} {ACC1:acc.itm(1)} {ACC1:acc.itm(2)} {ACC1:acc.itm(3)} {ACC1:acc.itm(4)} {ACC1:acc.itm(5)} {ACC1:acc.itm(6)} {ACC1:acc.itm(7)} {ACC1:acc.itm(8)} {ACC1:acc.itm(9)} {ACC1:acc.itm(10)} {ACC1:acc.itm(11)} {ACC1:acc.itm(12)} {ACC1:acc.itm(13)} {ACC1:acc.itm(14)} -attr xrf 63662 -attr oid 852 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc#664.itm(0)} -attr vt d
+load net {ACC1:acc#664.itm(1)} -attr vt d
+load net {ACC1:acc#664.itm(2)} -attr vt d
+load net {ACC1:acc#664.itm(3)} -attr vt d
+load net {ACC1:acc#664.itm(4)} -attr vt d
+load net {ACC1:acc#664.itm(5)} -attr vt d
+load net {ACC1:acc#664.itm(6)} -attr vt d
+load net {ACC1:acc#664.itm(7)} -attr vt d
+load net {ACC1:acc#664.itm(8)} -attr vt d
+load net {ACC1:acc#664.itm(9)} -attr vt d
+load net {ACC1:acc#664.itm(10)} -attr vt d
+load net {ACC1:acc#664.itm(11)} -attr vt d
+load net {ACC1:acc#664.itm(12)} -attr vt d
+load net {ACC1:acc#664.itm(13)} -attr vt d
+load net {ACC1:acc#664.itm(14)} -attr vt d
+load netBundle {ACC1:acc#664.itm} 15 {ACC1:acc#664.itm(0)} {ACC1:acc#664.itm(1)} {ACC1:acc#664.itm(2)} {ACC1:acc#664.itm(3)} {ACC1:acc#664.itm(4)} {ACC1:acc#664.itm(5)} {ACC1:acc#664.itm(6)} {ACC1:acc#664.itm(7)} {ACC1:acc#664.itm(8)} {ACC1:acc#664.itm(9)} {ACC1:acc#664.itm(10)} {ACC1:acc#664.itm(11)} {ACC1:acc#664.itm(12)} {ACC1:acc#664.itm(13)} {ACC1:acc#664.itm(14)} -attr xrf 63663 -attr oid 853 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#662.itm(0)} -attr vt d
+load net {ACC1:acc#662.itm(1)} -attr vt d
+load net {ACC1:acc#662.itm(2)} -attr vt d
+load net {ACC1:acc#662.itm(3)} -attr vt d
+load net {ACC1:acc#662.itm(4)} -attr vt d
+load net {ACC1:acc#662.itm(5)} -attr vt d
+load net {ACC1:acc#662.itm(6)} -attr vt d
+load net {ACC1:acc#662.itm(7)} -attr vt d
+load net {ACC1:acc#662.itm(8)} -attr vt d
+load net {ACC1:acc#662.itm(9)} -attr vt d
+load net {ACC1:acc#662.itm(10)} -attr vt d
+load net {ACC1:acc#662.itm(11)} -attr vt d
+load net {ACC1:acc#662.itm(12)} -attr vt d
+load net {ACC1:acc#662.itm(13)} -attr vt d
+load netBundle {ACC1:acc#662.itm} 14 {ACC1:acc#662.itm(0)} {ACC1:acc#662.itm(1)} {ACC1:acc#662.itm(2)} {ACC1:acc#662.itm(3)} {ACC1:acc#662.itm(4)} {ACC1:acc#662.itm(5)} {ACC1:acc#662.itm(6)} {ACC1:acc#662.itm(7)} {ACC1:acc#662.itm(8)} {ACC1:acc#662.itm(9)} {ACC1:acc#662.itm(10)} {ACC1:acc#662.itm(11)} {ACC1:acc#662.itm(12)} {ACC1:acc#662.itm(13)} -attr xrf 63664 -attr oid 854 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#663.itm(0)} -attr vt d
+load net {ACC1:acc#663.itm(1)} -attr vt d
+load net {ACC1:acc#663.itm(2)} -attr vt d
+load net {ACC1:acc#663.itm(3)} -attr vt d
+load net {ACC1:acc#663.itm(4)} -attr vt d
+load net {ACC1:acc#663.itm(5)} -attr vt d
+load net {ACC1:acc#663.itm(6)} -attr vt d
+load net {ACC1:acc#663.itm(7)} -attr vt d
+load net {ACC1:acc#663.itm(8)} -attr vt d
+load net {ACC1:acc#663.itm(9)} -attr vt d
+load net {ACC1:acc#663.itm(10)} -attr vt d
+load net {ACC1:acc#663.itm(11)} -attr vt d
+load net {ACC1:acc#663.itm(12)} -attr vt d
+load net {ACC1:acc#663.itm(13)} -attr vt d
+load netBundle {ACC1:acc#663.itm} 14 {ACC1:acc#663.itm(0)} {ACC1:acc#663.itm(1)} {ACC1:acc#663.itm(2)} {ACC1:acc#663.itm(3)} {ACC1:acc#663.itm(4)} {ACC1:acc#663.itm(5)} {ACC1:acc#663.itm(6)} {ACC1:acc#663.itm(7)} {ACC1:acc#663.itm(8)} {ACC1:acc#663.itm(9)} {ACC1:acc#663.itm(10)} {ACC1:acc#663.itm(11)} {ACC1:acc#663.itm(12)} {ACC1:acc#663.itm(13)} -attr xrf 63665 -attr oid 855 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {conc#1001.itm(0)} -attr vt d
+load net {conc#1001.itm(1)} -attr vt d
+load net {conc#1001.itm(2)} -attr vt d
+load net {conc#1001.itm(3)} -attr vt d
+load net {conc#1001.itm(4)} -attr vt d
+load net {conc#1001.itm(5)} -attr vt d
+load net {conc#1001.itm(6)} -attr vt d
+load net {conc#1001.itm(7)} -attr vt d
+load net {conc#1001.itm(8)} -attr vt d
+load net {conc#1001.itm(9)} -attr vt d
+load net {conc#1001.itm(10)} -attr vt d
+load net {conc#1001.itm(11)} -attr vt d
+load net {conc#1001.itm(12)} -attr vt d
+load net {conc#1001.itm(13)} -attr vt d
+load netBundle {conc#1001.itm} 14 {conc#1001.itm(0)} {conc#1001.itm(1)} {conc#1001.itm(2)} {conc#1001.itm(3)} {conc#1001.itm(4)} {conc#1001.itm(5)} {conc#1001.itm(6)} {conc#1001.itm(7)} {conc#1001.itm(8)} {conc#1001.itm(9)} {conc#1001.itm(10)} {conc#1001.itm(11)} {conc#1001.itm(12)} {conc#1001.itm(13)} -attr xrf 63666 -attr oid 856 -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:acc#660.itm(0)} -attr vt d
+load net {ACC1:acc#660.itm(1)} -attr vt d
+load net {ACC1:acc#660.itm(2)} -attr vt d
+load net {ACC1:acc#660.itm(3)} -attr vt d
+load net {ACC1:acc#660.itm(4)} -attr vt d
+load net {ACC1:acc#660.itm(5)} -attr vt d
+load net {ACC1:acc#660.itm(6)} -attr vt d
+load net {ACC1:acc#660.itm(7)} -attr vt d
+load net {ACC1:acc#660.itm(8)} -attr vt d
+load net {ACC1:acc#660.itm(9)} -attr vt d
+load net {ACC1:acc#660.itm(10)} -attr vt d
+load net {ACC1:acc#660.itm(11)} -attr vt d
+load net {ACC1:acc#660.itm(12)} -attr vt d
+load netBundle {ACC1:acc#660.itm} 13 {ACC1:acc#660.itm(0)} {ACC1:acc#660.itm(1)} {ACC1:acc#660.itm(2)} {ACC1:acc#660.itm(3)} {ACC1:acc#660.itm(4)} {ACC1:acc#660.itm(5)} {ACC1:acc#660.itm(6)} {ACC1:acc#660.itm(7)} {ACC1:acc#660.itm(8)} {ACC1:acc#660.itm(9)} {ACC1:acc#660.itm(10)} {ACC1:acc#660.itm(11)} {ACC1:acc#660.itm(12)} -attr xrf 63667 -attr oid 857 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#656.itm(0)} -attr vt d
+load net {ACC1:acc#656.itm(1)} -attr vt d
+load net {ACC1:acc#656.itm(2)} -attr vt d
+load net {ACC1:acc#656.itm(3)} -attr vt d
+load net {ACC1:acc#656.itm(4)} -attr vt d
+load net {ACC1:acc#656.itm(5)} -attr vt d
+load net {ACC1:acc#656.itm(6)} -attr vt d
+load net {ACC1:acc#656.itm(7)} -attr vt d
+load net {ACC1:acc#656.itm(8)} -attr vt d
+load net {ACC1:acc#656.itm(9)} -attr vt d
+load net {ACC1:acc#656.itm(10)} -attr vt d
+load net {ACC1:acc#656.itm(11)} -attr vt d
+load netBundle {ACC1:acc#656.itm} 12 {ACC1:acc#656.itm(0)} {ACC1:acc#656.itm(1)} {ACC1:acc#656.itm(2)} {ACC1:acc#656.itm(3)} {ACC1:acc#656.itm(4)} {ACC1:acc#656.itm(5)} {ACC1:acc#656.itm(6)} {ACC1:acc#656.itm(7)} {ACC1:acc#656.itm(8)} {ACC1:acc#656.itm(9)} {ACC1:acc#656.itm(10)} {ACC1:acc#656.itm(11)} -attr xrf 63668 -attr oid 858 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {conc#1002.itm(0)} -attr vt d
+load net {conc#1002.itm(1)} -attr vt d
+load net {conc#1002.itm(2)} -attr vt d
+load net {conc#1002.itm(3)} -attr vt d
+load net {conc#1002.itm(4)} -attr vt d
+load net {conc#1002.itm(5)} -attr vt d
+load net {conc#1002.itm(6)} -attr vt d
+load net {conc#1002.itm(7)} -attr vt d
+load net {conc#1002.itm(8)} -attr vt d
+load net {conc#1002.itm(9)} -attr vt d
+load net {conc#1002.itm(10)} -attr vt d
+load net {conc#1002.itm(11)} -attr vt d
+load netBundle {conc#1002.itm} 12 {conc#1002.itm(0)} {conc#1002.itm(1)} {conc#1002.itm(2)} {conc#1002.itm(3)} {conc#1002.itm(4)} {conc#1002.itm(5)} {conc#1002.itm(6)} {conc#1002.itm(7)} {conc#1002.itm(8)} {conc#1002.itm(9)} {conc#1002.itm(10)} {conc#1002.itm(11)} -attr xrf 63669 -attr oid 859 -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {ACC1-3:exs#1074.itm(0)} -attr vt d
+load net {ACC1-3:exs#1074.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1074.itm} 2 {ACC1-3:exs#1074.itm(0)} {ACC1-3:exs#1074.itm(1)} -attr xrf 63670 -attr oid 860 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1074.itm}
+load net {FRAME:acc#9.itm(0)} -attr vt d
+load net {FRAME:acc#9.itm(1)} -attr vt d
+load net {FRAME:acc#9.itm(2)} -attr vt d
+load net {FRAME:acc#9.itm(3)} -attr vt d
+load net {FRAME:acc#9.itm(4)} -attr vt d
+load net {FRAME:acc#9.itm(5)} -attr vt d
+load netBundle {FRAME:acc#9.itm} 6 {FRAME:acc#9.itm(0)} {FRAME:acc#9.itm(1)} {FRAME:acc#9.itm(2)} {FRAME:acc#9.itm(3)} {FRAME:acc#9.itm(4)} {FRAME:acc#9.itm(5)} -attr xrf 63671 -attr oid 861 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#8.itm(0)} -attr vt d
+load net {FRAME:acc#8.itm(1)} -attr vt d
+load net {FRAME:acc#8.itm(2)} -attr vt d
+load net {FRAME:acc#8.itm(3)} -attr vt d
+load net {FRAME:acc#8.itm(4)} -attr vt d
+load netBundle {FRAME:acc#8.itm} 5 {FRAME:acc#8.itm(0)} {FRAME:acc#8.itm(1)} {FRAME:acc#8.itm(2)} {FRAME:acc#8.itm(3)} {FRAME:acc#8.itm(4)} -attr xrf 63672 -attr oid 862 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#6.itm(0)} -attr vt d
+load net {FRAME:acc#6.itm(1)} -attr vt d
+load net {FRAME:acc#6.itm(2)} -attr vt d
+load net {FRAME:acc#6.itm(3)} -attr vt d
+load netBundle {FRAME:acc#6.itm} 4 {FRAME:acc#6.itm(0)} {FRAME:acc#6.itm(1)} {FRAME:acc#6.itm(2)} {FRAME:acc#6.itm(3)} -attr xrf 63673 -attr oid 863 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {slc(ACC1:slc.psp.sva)#5.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#5.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#5.itm} 3 {slc(ACC1:slc.psp.sva)#5.itm(0)} {slc(ACC1:slc.psp.sva)#5.itm(1)} {slc(ACC1:slc.psp.sva)#5.itm(2)} -attr xrf 63674 -attr oid 864 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#5.itm}
+load net {FRAME:not#2.itm(0)} -attr vt d
+load net {FRAME:not#2.itm(1)} -attr vt d
+load net {FRAME:not#2.itm(2)} -attr vt d
+load netBundle {FRAME:not#2.itm} 3 {FRAME:not#2.itm(0)} {FRAME:not#2.itm(1)} {FRAME:not#2.itm(2)} -attr xrf 63675 -attr oid 865 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {slc(ACC1:slc.psp.sva)#6.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#6.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#6.itm} 3 {slc(ACC1:slc.psp.sva)#6.itm(0)} {slc(ACC1:slc.psp.sva)#6.itm(1)} {slc(ACC1:slc.psp.sva)#6.itm(2)} -attr xrf 63676 -attr oid 866 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#6.itm}
+load net {FRAME:acc#5.itm(0)} -attr vt d
+load net {FRAME:acc#5.itm(1)} -attr vt d
+load net {FRAME:acc#5.itm(2)} -attr vt d
+load net {FRAME:acc#5.itm(3)} -attr vt d
+load netBundle {FRAME:acc#5.itm} 4 {FRAME:acc#5.itm(0)} {FRAME:acc#5.itm(1)} {FRAME:acc#5.itm(2)} {FRAME:acc#5.itm(3)} -attr xrf 63677 -attr oid 867 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {conc#1003.itm(0)} -attr vt d
+load net {conc#1003.itm(1)} -attr vt d
+load net {conc#1003.itm(2)} -attr vt d
+load netBundle {conc#1003.itm} 3 {conc#1003.itm(0)} {conc#1003.itm(1)} {conc#1003.itm(2)} -attr xrf 63678 -attr oid 868 -attr vt d -attr @path {/sobel/sobel:core/conc#1003.itm}
+load net {slc(ACC1:slc.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva).itm} 2 {slc(ACC1:slc.psp.sva).itm(0)} {slc(ACC1:slc.psp.sva).itm(1)} -attr xrf 63679 -attr oid 869 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva).itm}
+load net {FRAME:acc#7.itm(0)} -attr vt d
+load net {FRAME:acc#7.itm(1)} -attr vt d
+load net {FRAME:acc#7.itm(2)} -attr vt d
+load net {FRAME:acc#7.itm(3)} -attr vt d
+load netBundle {FRAME:acc#7.itm} 4 {FRAME:acc#7.itm(0)} {FRAME:acc#7.itm(1)} {FRAME:acc#7.itm(2)} {FRAME:acc#7.itm(3)} -attr xrf 63680 -attr oid 870 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {slc(ACC1:slc.psp.sva)#7.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#7.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#7.itm} 3 {slc(ACC1:slc.psp.sva)#7.itm(0)} {slc(ACC1:slc.psp.sva)#7.itm(1)} {slc(ACC1:slc.psp.sva)#7.itm(2)} -attr xrf 63681 -attr oid 871 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#7.itm}
+load net {FRAME:not#1.itm(0)} -attr vt d
+load net {FRAME:not#1.itm(1)} -attr vt d
+load net {FRAME:not#1.itm(2)} -attr vt d
+load netBundle {FRAME:not#1.itm} 3 {FRAME:not#1.itm(0)} {FRAME:not#1.itm(1)} {FRAME:not#1.itm(2)} -attr xrf 63682 -attr oid 872 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {slc(ACC1:slc.psp.sva)#8.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#8.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#8.itm(2)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#8.itm} 3 {slc(ACC1:slc.psp.sva)#8.itm(0)} {slc(ACC1:slc.psp.sva)#8.itm(1)} {slc(ACC1:slc.psp.sva)#8.itm(2)} -attr xrf 63683 -attr oid 873 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#8.itm}
+load net {ACC1:acc#416.itm(0)} -attr vt d
+load net {ACC1:acc#416.itm(1)} -attr vt d
+load net {ACC1:acc#416.itm(2)} -attr vt d
+load net {ACC1:acc#416.itm(3)} -attr vt d
+load net {ACC1:acc#416.itm(4)} -attr vt d
+load net {ACC1:acc#416.itm(5)} -attr vt d
+load net {ACC1:acc#416.itm(6)} -attr vt d
+load net {ACC1:acc#416.itm(7)} -attr vt d
+load net {ACC1:acc#416.itm(8)} -attr vt d
+load net {ACC1:acc#416.itm(9)} -attr vt d
+load net {ACC1:acc#416.itm(10)} -attr vt d
+load netBundle {ACC1:acc#416.itm} 11 {ACC1:acc#416.itm(0)} {ACC1:acc#416.itm(1)} {ACC1:acc#416.itm(2)} {ACC1:acc#416.itm(3)} {ACC1:acc#416.itm(4)} {ACC1:acc#416.itm(5)} {ACC1:acc#416.itm(6)} {ACC1:acc#416.itm(7)} {ACC1:acc#416.itm(8)} {ACC1:acc#416.itm(9)} {ACC1:acc#416.itm(10)} -attr xrf 63684 -attr oid 874 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#370.itm(0)} -attr vt d
+load net {ACC1:acc#370.itm(1)} -attr vt d
+load net {ACC1:acc#370.itm(2)} -attr vt d
+load net {ACC1:acc#370.itm(3)} -attr vt d
+load net {ACC1:acc#370.itm(4)} -attr vt d
+load net {ACC1:acc#370.itm(5)} -attr vt d
+load net {ACC1:acc#370.itm(6)} -attr vt d
+load net {ACC1:acc#370.itm(7)} -attr vt d
+load net {ACC1:acc#370.itm(8)} -attr vt d
+load net {ACC1:acc#370.itm(9)} -attr vt d
+load net {ACC1:acc#370.itm(10)} -attr vt d
+load netBundle {ACC1:acc#370.itm} 11 {ACC1:acc#370.itm(0)} {ACC1:acc#370.itm(1)} {ACC1:acc#370.itm(2)} {ACC1:acc#370.itm(3)} {ACC1:acc#370.itm(4)} {ACC1:acc#370.itm(5)} {ACC1:acc#370.itm(6)} {ACC1:acc#370.itm(7)} {ACC1:acc#370.itm(8)} {ACC1:acc#370.itm(9)} {ACC1:acc#370.itm(10)} -attr xrf 63685 -attr oid 875 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:not#309.itm(0)} -attr vt d
+load net {ACC1:not#309.itm(1)} -attr vt d
+load net {ACC1:not#309.itm(2)} -attr vt d
+load net {ACC1:not#309.itm(3)} -attr vt d
+load net {ACC1:not#309.itm(4)} -attr vt d
+load net {ACC1:not#309.itm(5)} -attr vt d
+load net {ACC1:not#309.itm(6)} -attr vt d
+load net {ACC1:not#309.itm(7)} -attr vt d
+load net {ACC1:not#309.itm(8)} -attr vt d
+load net {ACC1:not#309.itm(9)} -attr vt d
+load netBundle {ACC1:not#309.itm} 10 {ACC1:not#309.itm(0)} {ACC1:not#309.itm(1)} {ACC1:not#309.itm(2)} {ACC1:not#309.itm(3)} {ACC1:not#309.itm(4)} {ACC1:not#309.itm(5)} {ACC1:not#309.itm(6)} {ACC1:not#309.itm(7)} {ACC1:not#309.itm(8)} {ACC1:not#309.itm(9)} -attr xrf 63686 -attr oid 876 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {slc(regs.regs(0).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#3.itm} 10 {slc(regs.regs(0).sva)#3.itm(0)} {slc(regs.regs(0).sva)#3.itm(1)} {slc(regs.regs(0).sva)#3.itm(2)} {slc(regs.regs(0).sva)#3.itm(3)} {slc(regs.regs(0).sva)#3.itm(4)} {slc(regs.regs(0).sva)#3.itm(5)} {slc(regs.regs(0).sva)#3.itm(6)} {slc(regs.regs(0).sva)#3.itm(7)} {slc(regs.regs(0).sva)#3.itm(8)} {slc(regs.regs(0).sva)#3.itm(9)} -attr xrf 63687 -attr oid 877 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {ACC1:not#310.itm(0)} -attr vt d
+load net {ACC1:not#310.itm(1)} -attr vt d
+load net {ACC1:not#310.itm(2)} -attr vt d
+load net {ACC1:not#310.itm(3)} -attr vt d
+load net {ACC1:not#310.itm(4)} -attr vt d
+load net {ACC1:not#310.itm(5)} -attr vt d
+load net {ACC1:not#310.itm(6)} -attr vt d
+load net {ACC1:not#310.itm(7)} -attr vt d
+load net {ACC1:not#310.itm(8)} -attr vt d
+load net {ACC1:not#310.itm(9)} -attr vt d
+load netBundle {ACC1:not#310.itm} 10 {ACC1:not#310.itm(0)} {ACC1:not#310.itm(1)} {ACC1:not#310.itm(2)} {ACC1:not#310.itm(3)} {ACC1:not#310.itm(4)} {ACC1:not#310.itm(5)} {ACC1:not#310.itm(6)} {ACC1:not#310.itm(7)} {ACC1:not#310.itm(8)} {ACC1:not#310.itm(9)} -attr xrf 63688 -attr oid 878 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {slc(regs.regs(0).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#4.itm} 10 {slc(regs.regs(0).sva)#4.itm(0)} {slc(regs.regs(0).sva)#4.itm(1)} {slc(regs.regs(0).sva)#4.itm(2)} {slc(regs.regs(0).sva)#4.itm(3)} {slc(regs.regs(0).sva)#4.itm(4)} {slc(regs.regs(0).sva)#4.itm(5)} {slc(regs.regs(0).sva)#4.itm(6)} {slc(regs.regs(0).sva)#4.itm(7)} {slc(regs.regs(0).sva)#4.itm(8)} {slc(regs.regs(0).sva)#4.itm(9)} -attr xrf 63689 -attr oid 879 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {ACC1:acc#369.itm(0)} -attr vt d
+load net {ACC1:acc#369.itm(1)} -attr vt d
+load net {ACC1:acc#369.itm(2)} -attr vt d
+load net {ACC1:acc#369.itm(3)} -attr vt d
+load net {ACC1:acc#369.itm(4)} -attr vt d
+load net {ACC1:acc#369.itm(5)} -attr vt d
+load net {ACC1:acc#369.itm(6)} -attr vt d
+load net {ACC1:acc#369.itm(7)} -attr vt d
+load net {ACC1:acc#369.itm(8)} -attr vt d
+load net {ACC1:acc#369.itm(9)} -attr vt d
+load net {ACC1:acc#369.itm(10)} -attr vt d
+load netBundle {ACC1:acc#369.itm} 11 {ACC1:acc#369.itm(0)} {ACC1:acc#369.itm(1)} {ACC1:acc#369.itm(2)} {ACC1:acc#369.itm(3)} {ACC1:acc#369.itm(4)} {ACC1:acc#369.itm(5)} {ACC1:acc#369.itm(6)} {ACC1:acc#369.itm(7)} {ACC1:acc#369.itm(8)} {ACC1:acc#369.itm(9)} {ACC1:acc#369.itm(10)} -attr xrf 63690 -attr oid 880 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:not#311.itm(0)} -attr vt d
+load net {ACC1:not#311.itm(1)} -attr vt d
+load net {ACC1:not#311.itm(2)} -attr vt d
+load net {ACC1:not#311.itm(3)} -attr vt d
+load net {ACC1:not#311.itm(4)} -attr vt d
+load net {ACC1:not#311.itm(5)} -attr vt d
+load net {ACC1:not#311.itm(6)} -attr vt d
+load net {ACC1:not#311.itm(7)} -attr vt d
+load net {ACC1:not#311.itm(8)} -attr vt d
+load net {ACC1:not#311.itm(9)} -attr vt d
+load netBundle {ACC1:not#311.itm} 10 {ACC1:not#311.itm(0)} {ACC1:not#311.itm(1)} {ACC1:not#311.itm(2)} {ACC1:not#311.itm(3)} {ACC1:not#311.itm(4)} {ACC1:not#311.itm(5)} {ACC1:not#311.itm(6)} {ACC1:not#311.itm(7)} {ACC1:not#311.itm(8)} {ACC1:not#311.itm(9)} -attr xrf 63691 -attr oid 881 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {slc(regs.regs(0).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#5.itm} 10 {slc(regs.regs(0).sva)#5.itm(0)} {slc(regs.regs(0).sva)#5.itm(1)} {slc(regs.regs(0).sva)#5.itm(2)} {slc(regs.regs(0).sva)#5.itm(3)} {slc(regs.regs(0).sva)#5.itm(4)} {slc(regs.regs(0).sva)#5.itm(5)} {slc(regs.regs(0).sva)#5.itm(6)} {slc(regs.regs(0).sva)#5.itm(7)} {slc(regs.regs(0).sva)#5.itm(8)} {slc(regs.regs(0).sva)#5.itm(9)} -attr xrf 63692 -attr oid 882 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {ACC1:acc#360.itm(0)} -attr vt d
+load net {ACC1:acc#360.itm(1)} -attr vt d
+load net {ACC1:acc#360.itm(2)} -attr vt d
+load net {ACC1:acc#360.itm(3)} -attr vt d
+load net {ACC1:acc#360.itm(4)} -attr vt d
+load net {ACC1:acc#360.itm(5)} -attr vt d
+load net {ACC1:acc#360.itm(6)} -attr vt d
+load net {ACC1:acc#360.itm(7)} -attr vt d
+load net {ACC1:acc#360.itm(8)} -attr vt d
+load net {ACC1:acc#360.itm(9)} -attr vt d
+load net {ACC1:acc#360.itm(10)} -attr vt d
+load netBundle {ACC1:acc#360.itm} 11 {ACC1:acc#360.itm(0)} {ACC1:acc#360.itm(1)} {ACC1:acc#360.itm(2)} {ACC1:acc#360.itm(3)} {ACC1:acc#360.itm(4)} {ACC1:acc#360.itm(5)} {ACC1:acc#360.itm(6)} {ACC1:acc#360.itm(7)} {ACC1:acc#360.itm(8)} {ACC1:acc#360.itm(9)} {ACC1:acc#360.itm(10)} -attr xrf 63693 -attr oid 883 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {slc(regs.regs(0).sva#1)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#1)#1.itm} 10 {slc(regs.regs(0).sva#1)#1.itm(0)} {slc(regs.regs(0).sva#1)#1.itm(1)} {slc(regs.regs(0).sva#1)#1.itm(2)} {slc(regs.regs(0).sva#1)#1.itm(3)} {slc(regs.regs(0).sva#1)#1.itm(4)} {slc(regs.regs(0).sva#1)#1.itm(5)} {slc(regs.regs(0).sva#1)#1.itm(6)} {slc(regs.regs(0).sva#1)#1.itm(7)} {slc(regs.regs(0).sva#1)#1.itm(8)} {slc(regs.regs(0).sva#1)#1.itm(9)} -attr xrf 63694 -attr oid 884 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {slc(regs.regs(0).sva#2)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#2)#1.itm} 10 {slc(regs.regs(0).sva#2)#1.itm(0)} {slc(regs.regs(0).sva#2)#1.itm(1)} {slc(regs.regs(0).sva#2)#1.itm(2)} {slc(regs.regs(0).sva#2)#1.itm(3)} {slc(regs.regs(0).sva#2)#1.itm(4)} {slc(regs.regs(0).sva#2)#1.itm(5)} {slc(regs.regs(0).sva#2)#1.itm(6)} {slc(regs.regs(0).sva#2)#1.itm(7)} {slc(regs.regs(0).sva#2)#1.itm(8)} {slc(regs.regs(0).sva#2)#1.itm(9)} -attr xrf 63695 -attr oid 885 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {slc(regs.regs(0).sva#3)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#3)#1.itm} 10 {slc(regs.regs(0).sva#3)#1.itm(0)} {slc(regs.regs(0).sva#3)#1.itm(1)} {slc(regs.regs(0).sva#3)#1.itm(2)} {slc(regs.regs(0).sva#3)#1.itm(3)} {slc(regs.regs(0).sva#3)#1.itm(4)} {slc(regs.regs(0).sva#3)#1.itm(5)} {slc(regs.regs(0).sva#3)#1.itm(6)} {slc(regs.regs(0).sva#3)#1.itm(7)} {slc(regs.regs(0).sva#3)#1.itm(8)} {slc(regs.regs(0).sva#3)#1.itm(9)} -attr xrf 63696 -attr oid 886 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {ACC1-3:exs#1059.itm(0)} -attr vt d
+load net {ACC1-3:exs#1059.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1059.itm} 2 {ACC1-3:exs#1059.itm(0)} {ACC1-3:exs#1059.itm(1)} -attr xrf 63697 -attr oid 887 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1059.itm}
+load net {ACC1-3:exs#1047.itm(0)} -attr vt d
+load net {ACC1-3:exs#1047.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1047.itm} 2 {ACC1-3:exs#1047.itm(0)} {ACC1-3:exs#1047.itm(1)} -attr xrf 63698 -attr oid 888 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1047.itm}
+load net {ACC1:acc#398.itm(0)} -attr vt d
+load net {ACC1:acc#398.itm(1)} -attr vt d
+load net {ACC1:acc#398.itm(2)} -attr vt d
+load net {ACC1:acc#398.itm(3)} -attr vt d
+load net {ACC1:acc#398.itm(4)} -attr vt d
+load net {ACC1:acc#398.itm(5)} -attr vt d
+load net {ACC1:acc#398.itm(6)} -attr vt d
+load net {ACC1:acc#398.itm(7)} -attr vt d
+load net {ACC1:acc#398.itm(8)} -attr vt d
+load net {ACC1:acc#398.itm(9)} -attr vt d
+load net {ACC1:acc#398.itm(10)} -attr vt d
+load netBundle {ACC1:acc#398.itm} 11 {ACC1:acc#398.itm(0)} {ACC1:acc#398.itm(1)} {ACC1:acc#398.itm(2)} {ACC1:acc#398.itm(3)} {ACC1:acc#398.itm(4)} {ACC1:acc#398.itm(5)} {ACC1:acc#398.itm(6)} {ACC1:acc#398.itm(7)} {ACC1:acc#398.itm(8)} {ACC1:acc#398.itm(9)} {ACC1:acc#398.itm(10)} -attr xrf 63699 -attr oid 889 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {regs.operator[]:not#5.itm(0)} -attr vt d
+load net {regs.operator[]:not#5.itm(1)} -attr vt d
+load net {regs.operator[]:not#5.itm(2)} -attr vt d
+load net {regs.operator[]:not#5.itm(3)} -attr vt d
+load net {regs.operator[]:not#5.itm(4)} -attr vt d
+load net {regs.operator[]:not#5.itm(5)} -attr vt d
+load net {regs.operator[]:not#5.itm(6)} -attr vt d
+load net {regs.operator[]:not#5.itm(7)} -attr vt d
+load net {regs.operator[]:not#5.itm(8)} -attr vt d
+load net {regs.operator[]:not#5.itm(9)} -attr vt d
+load netBundle {regs.operator[]:not#5.itm} 10 {regs.operator[]:not#5.itm(0)} {regs.operator[]:not#5.itm(1)} {regs.operator[]:not#5.itm(2)} {regs.operator[]:not#5.itm(3)} {regs.operator[]:not#5.itm(4)} {regs.operator[]:not#5.itm(5)} {regs.operator[]:not#5.itm(6)} {regs.operator[]:not#5.itm(7)} {regs.operator[]:not#5.itm(8)} {regs.operator[]:not#5.itm(9)} -attr xrf 63700 -attr oid 890 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(0)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(1)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(2)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(3)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(4)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(5)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(6)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(7)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(8)} -attr vt d
+load net {regs.operator[]#1:not#5.itm(9)} -attr vt d
+load netBundle {regs.operator[]#1:not#5.itm} 10 {regs.operator[]#1:not#5.itm(0)} {regs.operator[]#1:not#5.itm(1)} {regs.operator[]#1:not#5.itm(2)} {regs.operator[]#1:not#5.itm(3)} {regs.operator[]#1:not#5.itm(4)} {regs.operator[]#1:not#5.itm(5)} {regs.operator[]#1:not#5.itm(6)} {regs.operator[]#1:not#5.itm(7)} {regs.operator[]#1:not#5.itm(8)} {regs.operator[]#1:not#5.itm(9)} -attr xrf 63701 -attr oid 891 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {ACC1:acc#397.itm(0)} -attr vt d
+load net {ACC1:acc#397.itm(1)} -attr vt d
+load net {ACC1:acc#397.itm(2)} -attr vt d
+load net {ACC1:acc#397.itm(3)} -attr vt d
+load net {ACC1:acc#397.itm(4)} -attr vt d
+load net {ACC1:acc#397.itm(5)} -attr vt d
+load net {ACC1:acc#397.itm(6)} -attr vt d
+load net {ACC1:acc#397.itm(7)} -attr vt d
+load net {ACC1:acc#397.itm(8)} -attr vt d
+load net {ACC1:acc#397.itm(9)} -attr vt d
+load net {ACC1:acc#397.itm(10)} -attr vt d
+load netBundle {ACC1:acc#397.itm} 11 {ACC1:acc#397.itm(0)} {ACC1:acc#397.itm(1)} {ACC1:acc#397.itm(2)} {ACC1:acc#397.itm(3)} {ACC1:acc#397.itm(4)} {ACC1:acc#397.itm(5)} {ACC1:acc#397.itm(6)} {ACC1:acc#397.itm(7)} {ACC1:acc#397.itm(8)} {ACC1:acc#397.itm(9)} {ACC1:acc#397.itm(10)} -attr xrf 63702 -attr oid 892 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {regs.operator[]#2:not#5.itm(0)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(1)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(2)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(3)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(4)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(5)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(6)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(7)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(8)} -attr vt d
+load net {regs.operator[]#2:not#5.itm(9)} -attr vt d
+load netBundle {regs.operator[]#2:not#5.itm} 10 {regs.operator[]#2:not#5.itm(0)} {regs.operator[]#2:not#5.itm(1)} {regs.operator[]#2:not#5.itm(2)} {regs.operator[]#2:not#5.itm(3)} {regs.operator[]#2:not#5.itm(4)} {regs.operator[]#2:not#5.itm(5)} {regs.operator[]#2:not#5.itm(6)} {regs.operator[]#2:not#5.itm(7)} {regs.operator[]#2:not#5.itm(8)} {regs.operator[]#2:not#5.itm(9)} -attr xrf 63703 -attr oid 893 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {ACC1-3:exs#1056.itm(0)} -attr vt d
+load net {ACC1-3:exs#1056.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1056.itm} 2 {ACC1-3:exs#1056.itm(0)} {ACC1-3:exs#1056.itm(1)} -attr xrf 63704 -attr oid 894 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1056.itm}
+load net {ACC1-3:exs#1043.itm(0)} -attr vt d
+load net {ACC1-3:exs#1043.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1043.itm} 2 {ACC1-3:exs#1043.itm(0)} {ACC1-3:exs#1043.itm(1)} -attr xrf 63705 -attr oid 895 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1043.itm}
+load net {ACC1-3:exs#963.itm(0)} -attr vt d
+load net {ACC1-3:exs#963.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#963.itm} 2 {ACC1-3:exs#963.itm(0)} {ACC1-3:exs#963.itm(1)} -attr xrf 63706 -attr oid 896 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#963.itm}
+load net {ACC1-3:exs#1055.itm(0)} -attr vt d
+load net {ACC1-3:exs#1055.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1055.itm} 2 {ACC1-3:exs#1055.itm(0)} {ACC1-3:exs#1055.itm(1)} -attr xrf 63707 -attr oid 897 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1055.itm}
+load net {ACC1-2:exs#1059.itm(0)} -attr vt d
+load net {ACC1-2:exs#1059.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1059.itm} 2 {ACC1-2:exs#1059.itm(0)} {ACC1-2:exs#1059.itm(1)} -attr xrf 63708 -attr oid 898 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1059.itm}
+load net {ACC1-2:exs#1047.itm(0)} -attr vt d
+load net {ACC1-2:exs#1047.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1047.itm} 2 {ACC1-2:exs#1047.itm(0)} {ACC1-2:exs#1047.itm(1)} -attr xrf 63709 -attr oid 899 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1047.itm}
+load net {ACC1:acc#379.itm(0)} -attr vt d
+load net {ACC1:acc#379.itm(1)} -attr vt d
+load net {ACC1:acc#379.itm(2)} -attr vt d
+load net {ACC1:acc#379.itm(3)} -attr vt d
+load net {ACC1:acc#379.itm(4)} -attr vt d
+load net {ACC1:acc#379.itm(5)} -attr vt d
+load net {ACC1:acc#379.itm(6)} -attr vt d
+load net {ACC1:acc#379.itm(7)} -attr vt d
+load net {ACC1:acc#379.itm(8)} -attr vt d
+load net {ACC1:acc#379.itm(9)} -attr vt d
+load net {ACC1:acc#379.itm(10)} -attr vt d
+load netBundle {ACC1:acc#379.itm} 11 {ACC1:acc#379.itm(0)} {ACC1:acc#379.itm(1)} {ACC1:acc#379.itm(2)} {ACC1:acc#379.itm(3)} {ACC1:acc#379.itm(4)} {ACC1:acc#379.itm(5)} {ACC1:acc#379.itm(6)} {ACC1:acc#379.itm(7)} {ACC1:acc#379.itm(8)} {ACC1:acc#379.itm(9)} {ACC1:acc#379.itm(10)} -attr xrf 63710 -attr oid 900 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {slc(regs.regs(0).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva).itm} 10 {slc(regs.regs(0).sva).itm(0)} {slc(regs.regs(0).sva).itm(1)} {slc(regs.regs(0).sva).itm(2)} {slc(regs.regs(0).sva).itm(3)} {slc(regs.regs(0).sva).itm(4)} {slc(regs.regs(0).sva).itm(5)} {slc(regs.regs(0).sva).itm(6)} {slc(regs.regs(0).sva).itm(7)} {slc(regs.regs(0).sva).itm(8)} {slc(regs.regs(0).sva).itm(9)} -attr xrf 63711 -attr oid 901 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {slc(regs.regs(0).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#1.itm} 10 {slc(regs.regs(0).sva)#1.itm(0)} {slc(regs.regs(0).sva)#1.itm(1)} {slc(regs.regs(0).sva)#1.itm(2)} {slc(regs.regs(0).sva)#1.itm(3)} {slc(regs.regs(0).sva)#1.itm(4)} {slc(regs.regs(0).sva)#1.itm(5)} {slc(regs.regs(0).sva)#1.itm(6)} {slc(regs.regs(0).sva)#1.itm(7)} {slc(regs.regs(0).sva)#1.itm(8)} {slc(regs.regs(0).sva)#1.itm(9)} -attr xrf 63712 -attr oid 902 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {slc(regs.regs(0).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#2.itm} 10 {slc(regs.regs(0).sva)#2.itm(0)} {slc(regs.regs(0).sva)#2.itm(1)} {slc(regs.regs(0).sva)#2.itm(2)} {slc(regs.regs(0).sva)#2.itm(3)} {slc(regs.regs(0).sva)#2.itm(4)} {slc(regs.regs(0).sva)#2.itm(5)} {slc(regs.regs(0).sva)#2.itm(6)} {slc(regs.regs(0).sva)#2.itm(7)} {slc(regs.regs(0).sva)#2.itm(8)} {slc(regs.regs(0).sva)#2.itm(9)} -attr xrf 63713 -attr oid 903 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {ACC1:acc#388.itm(0)} -attr vt d
+load net {ACC1:acc#388.itm(1)} -attr vt d
+load net {ACC1:acc#388.itm(2)} -attr vt d
+load net {ACC1:acc#388.itm(3)} -attr vt d
+load net {ACC1:acc#388.itm(4)} -attr vt d
+load net {ACC1:acc#388.itm(5)} -attr vt d
+load net {ACC1:acc#388.itm(6)} -attr vt d
+load net {ACC1:acc#388.itm(7)} -attr vt d
+load net {ACC1:acc#388.itm(8)} -attr vt d
+load net {ACC1:acc#388.itm(9)} -attr vt d
+load net {ACC1:acc#388.itm(10)} -attr vt d
+load netBundle {ACC1:acc#388.itm} 11 {ACC1:acc#388.itm(0)} {ACC1:acc#388.itm(1)} {ACC1:acc#388.itm(2)} {ACC1:acc#388.itm(3)} {ACC1:acc#388.itm(4)} {ACC1:acc#388.itm(5)} {ACC1:acc#388.itm(6)} {ACC1:acc#388.itm(7)} {ACC1:acc#388.itm(8)} {ACC1:acc#388.itm(9)} {ACC1:acc#388.itm(10)} -attr xrf 63714 -attr oid 904 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#338.itm(0)} -attr vt d
+load net {ACC1:acc#338.itm(1)} -attr vt d
+load net {ACC1:acc#338.itm(2)} -attr vt d
+load net {ACC1:acc#338.itm(3)} -attr vt d
+load netBundle {ACC1:acc#338.itm} 4 {ACC1:acc#338.itm(0)} {ACC1:acc#338.itm(1)} {ACC1:acc#338.itm(2)} {ACC1:acc#338.itm(3)} -attr xrf 63715 -attr oid 905 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {conc#1004.itm(0)} -attr vt d
+load net {conc#1004.itm(1)} -attr vt d
+load net {conc#1004.itm(2)} -attr vt d
+load netBundle {conc#1004.itm} 3 {conc#1004.itm(0)} {conc#1004.itm(1)} {conc#1004.itm(2)} -attr xrf 63716 -attr oid 906 -attr vt d -attr @path {/sobel/sobel:core/conc#1004.itm}
+load net {ACC1-1:not#293.itm(0)} -attr vt d
+load net {ACC1-1:not#293.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#293.itm} 2 {ACC1-1:not#293.itm(0)} {ACC1-1:not#293.itm(1)} -attr xrf 63717 -attr oid 907 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#293.itm}
+load net {slc(ACC1:acc#220.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#220.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#220.psp#1.sva).itm} 2 {slc(ACC1:acc#220.psp#1.sva).itm(0)} {slc(ACC1:acc#220.psp#1.sva).itm(1)} -attr xrf 63718 -attr oid 908 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva).itm}
+load net {conc#1005.itm(0)} -attr vt d
+load net {conc#1005.itm(1)} -attr vt d
+load netBundle {conc#1005.itm} 2 {conc#1005.itm(0)} {conc#1005.itm(1)} -attr xrf 63719 -attr oid 909 -attr vt d -attr @path {/sobel/sobel:core/conc#1005.itm}
+load net {ACC1:slc#17.itm(0)} -attr vt d
+load net {ACC1:slc#17.itm(1)} -attr vt d
+load net {ACC1:slc#17.itm(2)} -attr vt d
+load net {ACC1:slc#17.itm(3)} -attr vt d
+load netBundle {ACC1:slc#17.itm} 4 {ACC1:slc#17.itm(0)} {ACC1:slc#17.itm(1)} {ACC1:slc#17.itm(2)} {ACC1:slc#17.itm(3)} -attr xrf 63720 -attr oid 910 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#17.itm}
+load net {ACC1:acc#336.itm(0)} -attr vt d
+load net {ACC1:acc#336.itm(1)} -attr vt d
+load net {ACC1:acc#336.itm(2)} -attr vt d
+load net {ACC1:acc#336.itm(3)} -attr vt d
+load net {ACC1:acc#336.itm(4)} -attr vt d
+load netBundle {ACC1:acc#336.itm} 5 {ACC1:acc#336.itm(0)} {ACC1:acc#336.itm(1)} {ACC1:acc#336.itm(2)} {ACC1:acc#336.itm(3)} {ACC1:acc#336.itm(4)} -attr xrf 63721 -attr oid 911 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {conc#1006.itm(0)} -attr vt d
+load net {conc#1006.itm(1)} -attr vt d
+load net {conc#1006.itm(2)} -attr vt d
+load net {conc#1006.itm(3)} -attr vt d
+load netBundle {conc#1006.itm} 4 {conc#1006.itm(0)} {conc#1006.itm(1)} {conc#1006.itm(2)} {conc#1006.itm(3)} -attr xrf 63722 -attr oid 912 -attr vt d -attr @path {/sobel/sobel:core/conc#1006.itm}
+load net {ACC1:slc#15.itm(0)} -attr vt d
+load net {ACC1:slc#15.itm(1)} -attr vt d
+load net {ACC1:slc#15.itm(2)} -attr vt d
+load netBundle {ACC1:slc#15.itm} 3 {ACC1:slc#15.itm(0)} {ACC1:slc#15.itm(1)} {ACC1:slc#15.itm(2)} -attr xrf 63723 -attr oid 913 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#15.itm}
+load net {ACC1:acc#334.itm(0)} -attr vt d
+load net {ACC1:acc#334.itm(1)} -attr vt d
+load net {ACC1:acc#334.itm(2)} -attr vt d
+load net {ACC1:acc#334.itm(3)} -attr vt d
+load netBundle {ACC1:acc#334.itm} 4 {ACC1:acc#334.itm(0)} {ACC1:acc#334.itm(1)} {ACC1:acc#334.itm(2)} {ACC1:acc#334.itm(3)} -attr xrf 63724 -attr oid 914 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {conc#1007.itm(0)} -attr vt d
+load net {conc#1007.itm(1)} -attr vt d
+load netBundle {conc#1007.itm} 2 {conc#1007.itm(0)} {conc#1007.itm(1)} -attr xrf 63725 -attr oid 915 -attr vt d -attr @path {/sobel/sobel:core/conc#1007.itm}
+load net {ACC1:conc#1133.itm(0)} -attr vt d
+load net {ACC1:conc#1133.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1133.itm} 2 {ACC1:conc#1133.itm(0)} {ACC1:conc#1133.itm(1)} -attr xrf 63726 -attr oid 916 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1133.itm}
+load net {conc#1008.itm(0)} -attr vt d
+load net {conc#1008.itm(1)} -attr vt d
+load net {conc#1008.itm(2)} -attr vt d
+load net {conc#1008.itm(3)} -attr vt d
+load netBundle {conc#1008.itm} 4 {conc#1008.itm(0)} {conc#1008.itm(1)} {conc#1008.itm(2)} {conc#1008.itm(3)} -attr xrf 63727 -attr oid 917 -attr vt d -attr @path {/sobel/sobel:core/conc#1008.itm}
+load net {ACC1:slc#16.itm(0)} -attr vt d
+load net {ACC1:slc#16.itm(1)} -attr vt d
+load net {ACC1:slc#16.itm(2)} -attr vt d
+load netBundle {ACC1:slc#16.itm} 3 {ACC1:slc#16.itm(0)} {ACC1:slc#16.itm(1)} {ACC1:slc#16.itm(2)} -attr xrf 63728 -attr oid 918 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#16.itm}
+load net {ACC1:acc#335.itm(0)} -attr vt d
+load net {ACC1:acc#335.itm(1)} -attr vt d
+load net {ACC1:acc#335.itm(2)} -attr vt d
+load net {ACC1:acc#335.itm(3)} -attr vt d
+load netBundle {ACC1:acc#335.itm} 4 {ACC1:acc#335.itm(0)} {ACC1:acc#335.itm(1)} {ACC1:acc#335.itm(2)} {ACC1:acc#335.itm(3)} -attr xrf 63729 -attr oid 919 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {conc#1009.itm(0)} -attr vt d
+load net {conc#1009.itm(1)} -attr vt d
+load net {conc#1009.itm(2)} -attr vt d
+load netBundle {conc#1009.itm} 3 {conc#1009.itm(0)} {conc#1009.itm(1)} {conc#1009.itm(2)} -attr xrf 63730 -attr oid 920 -attr vt d -attr @path {/sobel/sobel:core/conc#1009.itm}
+load net {ACC1:slc#14.itm(0)} -attr vt d
+load net {ACC1:slc#14.itm(1)} -attr vt d
+load netBundle {ACC1:slc#14.itm} 2 {ACC1:slc#14.itm(0)} {ACC1:slc#14.itm(1)} -attr xrf 63731 -attr oid 921 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#14.itm}
+load net {ACC1:acc#333.itm(0)} -attr vt d
+load net {ACC1:acc#333.itm(1)} -attr vt d
+load net {ACC1:acc#333.itm(2)} -attr vt d
+load netBundle {ACC1:acc#333.itm} 3 {ACC1:acc#333.itm(0)} {ACC1:acc#333.itm(1)} {ACC1:acc#333.itm(2)} -attr xrf 63732 -attr oid 922 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {conc#1010.itm(0)} -attr vt d
+load net {conc#1010.itm(1)} -attr vt d
+load netBundle {conc#1010.itm} 2 {conc#1010.itm(0)} {conc#1010.itm(1)} -attr xrf 63733 -attr oid 923 -attr vt d -attr @path {/sobel/sobel:core/conc#1010.itm}
+load net {ACC1:conc#1131.itm(0)} -attr vt d
+load net {ACC1:conc#1131.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1131.itm} 2 {ACC1:conc#1131.itm(0)} {ACC1:conc#1131.itm(1)} -attr xrf 63734 -attr oid 924 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1131.itm}
+load net {ACC1:conc#1135.itm(0)} -attr vt d
+load net {ACC1:conc#1135.itm(1)} -attr vt d
+load net {ACC1:conc#1135.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1135.itm} 3 {ACC1:conc#1135.itm(0)} {ACC1:conc#1135.itm(1)} {ACC1:conc#1135.itm(2)} -attr xrf 63735 -attr oid 925 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1135.itm}
+load net {ACC1:slc#13.itm(0)} -attr vt d
+load net {ACC1:slc#13.itm(1)} -attr vt d
+load netBundle {ACC1:slc#13.itm} 2 {ACC1:slc#13.itm(0)} {ACC1:slc#13.itm(1)} -attr xrf 63736 -attr oid 926 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#13.itm}
+load net {ACC1:acc#332.itm(0)} -attr vt d
+load net {ACC1:acc#332.itm(1)} -attr vt d
+load net {ACC1:acc#332.itm(2)} -attr vt d
+load netBundle {ACC1:acc#332.itm} 3 {ACC1:acc#332.itm(0)} {ACC1:acc#332.itm(1)} {ACC1:acc#332.itm(2)} -attr xrf 63737 -attr oid 927 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {conc#1011.itm(0)} -attr vt d
+load net {conc#1011.itm(1)} -attr vt d
+load netBundle {conc#1011.itm} 2 {conc#1011.itm(0)} {conc#1011.itm(1)} -attr xrf 63738 -attr oid 928 -attr vt d -attr @path {/sobel/sobel:core/conc#1011.itm}
+load net {ACC1:conc#1129.itm(0)} -attr vt d
+load net {ACC1:conc#1129.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1129.itm} 2 {ACC1:conc#1129.itm(0)} {ACC1:conc#1129.itm(1)} -attr xrf 63739 -attr oid 929 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1129.itm}
+load net {ACC1:acc#331.itm(0)} -attr vt d
+load net {ACC1:acc#331.itm(1)} -attr vt d
+load net {ACC1:acc#331.itm(2)} -attr vt d
+load net {ACC1:acc#331.itm(3)} -attr vt d
+load net {ACC1:acc#331.itm(4)} -attr vt d
+load net {ACC1:acc#331.itm(5)} -attr vt d
+load net {ACC1:acc#331.itm(6)} -attr vt d
+load net {ACC1:acc#331.itm(7)} -attr vt d
+load net {ACC1:acc#331.itm(8)} -attr vt d
+load net {ACC1:acc#331.itm(9)} -attr vt d
+load net {ACC1:acc#331.itm(10)} -attr vt d
+load netBundle {ACC1:acc#331.itm} 11 {ACC1:acc#331.itm(0)} {ACC1:acc#331.itm(1)} {ACC1:acc#331.itm(2)} {ACC1:acc#331.itm(3)} {ACC1:acc#331.itm(4)} {ACC1:acc#331.itm(5)} {ACC1:acc#331.itm(6)} {ACC1:acc#331.itm(7)} {ACC1:acc#331.itm(8)} {ACC1:acc#331.itm(9)} {ACC1:acc#331.itm(10)} -attr xrf 63740 -attr oid 930 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {regs.operator[]:not.itm(0)} -attr vt d
+load net {regs.operator[]:not.itm(1)} -attr vt d
+load net {regs.operator[]:not.itm(2)} -attr vt d
+load net {regs.operator[]:not.itm(3)} -attr vt d
+load net {regs.operator[]:not.itm(4)} -attr vt d
+load net {regs.operator[]:not.itm(5)} -attr vt d
+load net {regs.operator[]:not.itm(6)} -attr vt d
+load net {regs.operator[]:not.itm(7)} -attr vt d
+load net {regs.operator[]:not.itm(8)} -attr vt d
+load net {regs.operator[]:not.itm(9)} -attr vt d
+load netBundle {regs.operator[]:not.itm} 10 {regs.operator[]:not.itm(0)} {regs.operator[]:not.itm(1)} {regs.operator[]:not.itm(2)} {regs.operator[]:not.itm(3)} {regs.operator[]:not.itm(4)} {regs.operator[]:not.itm(5)} {regs.operator[]:not.itm(6)} {regs.operator[]:not.itm(7)} {regs.operator[]:not.itm(8)} {regs.operator[]:not.itm(9)} -attr xrf 63741 -attr oid 931 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {slc(regs.regs(0).sva#7).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#7).itm} 10 {slc(regs.regs(0).sva#7).itm(0)} {slc(regs.regs(0).sva#7).itm(1)} {slc(regs.regs(0).sva#7).itm(2)} {slc(regs.regs(0).sva#7).itm(3)} {slc(regs.regs(0).sva#7).itm(4)} {slc(regs.regs(0).sva#7).itm(5)} {slc(regs.regs(0).sva#7).itm(6)} {slc(regs.regs(0).sva#7).itm(7)} {slc(regs.regs(0).sva#7).itm(8)} {slc(regs.regs(0).sva#7).itm(9)} -attr xrf 63742 -attr oid 932 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {regs.operator[]#1:not.itm(0)} -attr vt d
+load net {regs.operator[]#1:not.itm(1)} -attr vt d
+load net {regs.operator[]#1:not.itm(2)} -attr vt d
+load net {regs.operator[]#1:not.itm(3)} -attr vt d
+load net {regs.operator[]#1:not.itm(4)} -attr vt d
+load net {regs.operator[]#1:not.itm(5)} -attr vt d
+load net {regs.operator[]#1:not.itm(6)} -attr vt d
+load net {regs.operator[]#1:not.itm(7)} -attr vt d
+load net {regs.operator[]#1:not.itm(8)} -attr vt d
+load net {regs.operator[]#1:not.itm(9)} -attr vt d
+load netBundle {regs.operator[]#1:not.itm} 10 {regs.operator[]#1:not.itm(0)} {regs.operator[]#1:not.itm(1)} {regs.operator[]#1:not.itm(2)} {regs.operator[]#1:not.itm(3)} {regs.operator[]#1:not.itm(4)} {regs.operator[]#1:not.itm(5)} {regs.operator[]#1:not.itm(6)} {regs.operator[]#1:not.itm(7)} {regs.operator[]#1:not.itm(8)} {regs.operator[]#1:not.itm(9)} -attr xrf 63743 -attr oid 933 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {slc(regs.regs(0).sva#8).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#8).itm} 10 {slc(regs.regs(0).sva#8).itm(0)} {slc(regs.regs(0).sva#8).itm(1)} {slc(regs.regs(0).sva#8).itm(2)} {slc(regs.regs(0).sva#8).itm(3)} {slc(regs.regs(0).sva#8).itm(4)} {slc(regs.regs(0).sva#8).itm(5)} {slc(regs.regs(0).sva#8).itm(6)} {slc(regs.regs(0).sva#8).itm(7)} {slc(regs.regs(0).sva#8).itm(8)} {slc(regs.regs(0).sva#8).itm(9)} -attr xrf 63744 -attr oid 934 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {ACC1:acc#330.itm(0)} -attr vt d
+load net {ACC1:acc#330.itm(1)} -attr vt d
+load net {ACC1:acc#330.itm(2)} -attr vt d
+load net {ACC1:acc#330.itm(3)} -attr vt d
+load net {ACC1:acc#330.itm(4)} -attr vt d
+load net {ACC1:acc#330.itm(5)} -attr vt d
+load net {ACC1:acc#330.itm(6)} -attr vt d
+load net {ACC1:acc#330.itm(7)} -attr vt d
+load net {ACC1:acc#330.itm(8)} -attr vt d
+load net {ACC1:acc#330.itm(9)} -attr vt d
+load net {ACC1:acc#330.itm(10)} -attr vt d
+load netBundle {ACC1:acc#330.itm} 11 {ACC1:acc#330.itm(0)} {ACC1:acc#330.itm(1)} {ACC1:acc#330.itm(2)} {ACC1:acc#330.itm(3)} {ACC1:acc#330.itm(4)} {ACC1:acc#330.itm(5)} {ACC1:acc#330.itm(6)} {ACC1:acc#330.itm(7)} {ACC1:acc#330.itm(8)} {ACC1:acc#330.itm(9)} {ACC1:acc#330.itm(10)} -attr xrf 63745 -attr oid 935 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {regs.operator[]#2:not.itm(0)} -attr vt d
+load net {regs.operator[]#2:not.itm(1)} -attr vt d
+load net {regs.operator[]#2:not.itm(2)} -attr vt d
+load net {regs.operator[]#2:not.itm(3)} -attr vt d
+load net {regs.operator[]#2:not.itm(4)} -attr vt d
+load net {regs.operator[]#2:not.itm(5)} -attr vt d
+load net {regs.operator[]#2:not.itm(6)} -attr vt d
+load net {regs.operator[]#2:not.itm(7)} -attr vt d
+load net {regs.operator[]#2:not.itm(8)} -attr vt d
+load net {regs.operator[]#2:not.itm(9)} -attr vt d
+load netBundle {regs.operator[]#2:not.itm} 10 {regs.operator[]#2:not.itm(0)} {regs.operator[]#2:not.itm(1)} {regs.operator[]#2:not.itm(2)} {regs.operator[]#2:not.itm(3)} {regs.operator[]#2:not.itm(4)} {regs.operator[]#2:not.itm(5)} {regs.operator[]#2:not.itm(6)} {regs.operator[]#2:not.itm(7)} {regs.operator[]#2:not.itm(8)} {regs.operator[]#2:not.itm(9)} -attr xrf 63746 -attr oid 936 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {slc(regs.regs(0).sva#9).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#9).itm} 10 {slc(regs.regs(0).sva#9).itm(0)} {slc(regs.regs(0).sva#9).itm(1)} {slc(regs.regs(0).sva#9).itm(2)} {slc(regs.regs(0).sva#9).itm(3)} {slc(regs.regs(0).sva#9).itm(4)} {slc(regs.regs(0).sva#9).itm(5)} {slc(regs.regs(0).sva#9).itm(6)} {slc(regs.regs(0).sva#9).itm(7)} {slc(regs.regs(0).sva#9).itm(8)} {slc(regs.regs(0).sva#9).itm(9)} -attr xrf 63747 -attr oid 937 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {ACC1:acc#341.itm(0)} -attr vt d
+load net {ACC1:acc#341.itm(1)} -attr vt d
+load net {ACC1:acc#341.itm(2)} -attr vt d
+load net {ACC1:acc#341.itm(3)} -attr vt d
+load net {ACC1:acc#341.itm(4)} -attr vt d
+load net {ACC1:acc#341.itm(5)} -attr vt d
+load net {ACC1:acc#341.itm(6)} -attr vt d
+load net {ACC1:acc#341.itm(7)} -attr vt d
+load net {ACC1:acc#341.itm(8)} -attr vt d
+load net {ACC1:acc#341.itm(9)} -attr vt d
+load net {ACC1:acc#341.itm(10)} -attr vt d
+load netBundle {ACC1:acc#341.itm} 11 {ACC1:acc#341.itm(0)} {ACC1:acc#341.itm(1)} {ACC1:acc#341.itm(2)} {ACC1:acc#341.itm(3)} {ACC1:acc#341.itm(4)} {ACC1:acc#341.itm(5)} {ACC1:acc#341.itm(6)} {ACC1:acc#341.itm(7)} {ACC1:acc#341.itm(8)} {ACC1:acc#341.itm(9)} {ACC1:acc#341.itm(10)} -attr xrf 63748 -attr oid 938 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:not.itm(0)} -attr vt d
+load net {ACC1:not.itm(1)} -attr vt d
+load net {ACC1:not.itm(2)} -attr vt d
+load net {ACC1:not.itm(3)} -attr vt d
+load net {ACC1:not.itm(4)} -attr vt d
+load net {ACC1:not.itm(5)} -attr vt d
+load net {ACC1:not.itm(6)} -attr vt d
+load net {ACC1:not.itm(7)} -attr vt d
+load net {ACC1:not.itm(8)} -attr vt d
+load net {ACC1:not.itm(9)} -attr vt d
+load netBundle {ACC1:not.itm} 10 {ACC1:not.itm(0)} {ACC1:not.itm(1)} {ACC1:not.itm(2)} {ACC1:not.itm(3)} {ACC1:not.itm(4)} {ACC1:not.itm(5)} {ACC1:not.itm(6)} {ACC1:not.itm(7)} {ACC1:not.itm(8)} {ACC1:not.itm(9)} -attr xrf 63749 -attr oid 939 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {slc(regs.regs(0).sva#4).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#4).itm} 10 {slc(regs.regs(0).sva#4).itm(0)} {slc(regs.regs(0).sva#4).itm(1)} {slc(regs.regs(0).sva#4).itm(2)} {slc(regs.regs(0).sva#4).itm(3)} {slc(regs.regs(0).sva#4).itm(4)} {slc(regs.regs(0).sva#4).itm(5)} {slc(regs.regs(0).sva#4).itm(6)} {slc(regs.regs(0).sva#4).itm(7)} {slc(regs.regs(0).sva#4).itm(8)} {slc(regs.regs(0).sva#4).itm(9)} -attr xrf 63750 -attr oid 940 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:not#307.itm(0)} -attr vt d
+load net {ACC1:not#307.itm(1)} -attr vt d
+load net {ACC1:not#307.itm(2)} -attr vt d
+load net {ACC1:not#307.itm(3)} -attr vt d
+load net {ACC1:not#307.itm(4)} -attr vt d
+load net {ACC1:not#307.itm(5)} -attr vt d
+load net {ACC1:not#307.itm(6)} -attr vt d
+load net {ACC1:not#307.itm(7)} -attr vt d
+load net {ACC1:not#307.itm(8)} -attr vt d
+load net {ACC1:not#307.itm(9)} -attr vt d
+load netBundle {ACC1:not#307.itm} 10 {ACC1:not#307.itm(0)} {ACC1:not#307.itm(1)} {ACC1:not#307.itm(2)} {ACC1:not#307.itm(3)} {ACC1:not#307.itm(4)} {ACC1:not#307.itm(5)} {ACC1:not#307.itm(6)} {ACC1:not#307.itm(7)} {ACC1:not#307.itm(8)} {ACC1:not#307.itm(9)} -attr xrf 63751 -attr oid 941 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {slc(regs.regs(0).sva#5).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#5).itm} 10 {slc(regs.regs(0).sva#5).itm(0)} {slc(regs.regs(0).sva#5).itm(1)} {slc(regs.regs(0).sva#5).itm(2)} {slc(regs.regs(0).sva#5).itm(3)} {slc(regs.regs(0).sva#5).itm(4)} {slc(regs.regs(0).sva#5).itm(5)} {slc(regs.regs(0).sva#5).itm(6)} {slc(regs.regs(0).sva#5).itm(7)} {slc(regs.regs(0).sva#5).itm(8)} {slc(regs.regs(0).sva#5).itm(9)} -attr xrf 63752 -attr oid 942 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {ACC1:acc#340.itm(0)} -attr vt d
+load net {ACC1:acc#340.itm(1)} -attr vt d
+load net {ACC1:acc#340.itm(2)} -attr vt d
+load net {ACC1:acc#340.itm(3)} -attr vt d
+load net {ACC1:acc#340.itm(4)} -attr vt d
+load net {ACC1:acc#340.itm(5)} -attr vt d
+load net {ACC1:acc#340.itm(6)} -attr vt d
+load net {ACC1:acc#340.itm(7)} -attr vt d
+load net {ACC1:acc#340.itm(8)} -attr vt d
+load net {ACC1:acc#340.itm(9)} -attr vt d
+load net {ACC1:acc#340.itm(10)} -attr vt d
+load netBundle {ACC1:acc#340.itm} 11 {ACC1:acc#340.itm(0)} {ACC1:acc#340.itm(1)} {ACC1:acc#340.itm(2)} {ACC1:acc#340.itm(3)} {ACC1:acc#340.itm(4)} {ACC1:acc#340.itm(5)} {ACC1:acc#340.itm(6)} {ACC1:acc#340.itm(7)} {ACC1:acc#340.itm(8)} {ACC1:acc#340.itm(9)} {ACC1:acc#340.itm(10)} -attr xrf 63753 -attr oid 943 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:not#308.itm(0)} -attr vt d
+load net {ACC1:not#308.itm(1)} -attr vt d
+load net {ACC1:not#308.itm(2)} -attr vt d
+load net {ACC1:not#308.itm(3)} -attr vt d
+load net {ACC1:not#308.itm(4)} -attr vt d
+load net {ACC1:not#308.itm(5)} -attr vt d
+load net {ACC1:not#308.itm(6)} -attr vt d
+load net {ACC1:not#308.itm(7)} -attr vt d
+load net {ACC1:not#308.itm(8)} -attr vt d
+load net {ACC1:not#308.itm(9)} -attr vt d
+load netBundle {ACC1:not#308.itm} 10 {ACC1:not#308.itm(0)} {ACC1:not#308.itm(1)} {ACC1:not#308.itm(2)} {ACC1:not#308.itm(3)} {ACC1:not#308.itm(4)} {ACC1:not#308.itm(5)} {ACC1:not#308.itm(6)} {ACC1:not#308.itm(7)} {ACC1:not#308.itm(8)} {ACC1:not#308.itm(9)} -attr xrf 63754 -attr oid 944 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {slc(regs.regs(0).sva#6).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#6).itm} 10 {slc(regs.regs(0).sva#6).itm(0)} {slc(regs.regs(0).sva#6).itm(1)} {slc(regs.regs(0).sva#6).itm(2)} {slc(regs.regs(0).sva#6).itm(3)} {slc(regs.regs(0).sva#6).itm(4)} {slc(regs.regs(0).sva#6).itm(5)} {slc(regs.regs(0).sva#6).itm(6)} {slc(regs.regs(0).sva#6).itm(7)} {slc(regs.regs(0).sva#6).itm(8)} {slc(regs.regs(0).sva#6).itm(9)} -attr xrf 63755 -attr oid 945 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:acc#406.itm(0)} -attr vt d
+load net {ACC1:acc#406.itm(1)} -attr vt d
+load net {ACC1:acc#406.itm(2)} -attr vt d
+load netBundle {ACC1:acc#406.itm} 3 {ACC1:acc#406.itm(0)} {ACC1:acc#406.itm(1)} {ACC1:acc#406.itm(2)} -attr xrf 63756 -attr oid 946 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#406.itm}
+load net {conc#1012.itm(0)} -attr vt d
+load net {conc#1012.itm(1)} -attr vt d
+load net {conc#1012.itm(2)} -attr vt d
+load netBundle {conc#1012.itm} 3 {conc#1012.itm(0)} {conc#1012.itm(1)} {conc#1012.itm(2)} -attr xrf 63757 -attr oid 947 -attr vt d -attr @path {/sobel/sobel:core/conc#1012.itm}
+load net {ACC1:conc#1270.itm(0)} -attr vt d
+load net {ACC1:conc#1270.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1270.itm} 2 {ACC1:conc#1270.itm(0)} {ACC1:conc#1270.itm(1)} -attr xrf 63758 -attr oid 948 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1270.itm}
+load net {ACC1:acc#368.itm(0)} -attr vt d
+load net {ACC1:acc#368.itm(1)} -attr vt d
+load net {ACC1:acc#368.itm(2)} -attr vt d
+load netBundle {ACC1:acc#368.itm} 3 {ACC1:acc#368.itm(0)} {ACC1:acc#368.itm(1)} {ACC1:acc#368.itm(2)} -attr xrf 63759 -attr oid 949 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#368.itm}
+load net {conc#1013.itm(0)} -attr vt d
+load net {conc#1013.itm(1)} -attr vt d
+load net {conc#1013.itm(2)} -attr vt d
+load netBundle {conc#1013.itm} 3 {conc#1013.itm(0)} {conc#1013.itm(1)} {conc#1013.itm(2)} -attr xrf 63760 -attr oid 950 -attr vt d -attr @path {/sobel/sobel:core/conc#1013.itm}
+load net {ACC1:conc#1198.itm(0)} -attr vt d
+load net {ACC1:conc#1198.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1198.itm} 2 {ACC1:conc#1198.itm(0)} {ACC1:conc#1198.itm(1)} -attr xrf 63761 -attr oid 951 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1198.itm}
+load net {ACC1:acc#367.itm(0)} -attr vt d
+load net {ACC1:acc#367.itm(1)} -attr vt d
+load net {ACC1:acc#367.itm(2)} -attr vt d
+load net {ACC1:acc#367.itm(3)} -attr vt d
+load netBundle {ACC1:acc#367.itm} 4 {ACC1:acc#367.itm(0)} {ACC1:acc#367.itm(1)} {ACC1:acc#367.itm(2)} {ACC1:acc#367.itm(3)} -attr xrf 63762 -attr oid 952 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#367.itm}
+load net {conc#1014.itm(0)} -attr vt d
+load net {conc#1014.itm(1)} -attr vt d
+load net {conc#1014.itm(2)} -attr vt d
+load netBundle {conc#1014.itm} 3 {conc#1014.itm(0)} {conc#1014.itm(1)} {conc#1014.itm(2)} -attr xrf 63763 -attr oid 953 -attr vt d -attr @path {/sobel/sobel:core/conc#1014.itm}
+load net {ACC1-1:not#291.itm(0)} -attr vt d
+load net {ACC1-1:not#291.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#291.itm} 2 {ACC1-1:not#291.itm(0)} {ACC1-1:not#291.itm(1)} -attr xrf 63764 -attr oid 954 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#291.itm}
+load net {slc(ACC1:acc#219.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#219.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#219.psp#1.sva).itm} 2 {slc(ACC1:acc#219.psp#1.sva).itm(0)} {slc(ACC1:acc#219.psp#1.sva).itm(1)} -attr xrf 63765 -attr oid 955 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#1.sva).itm}
+load net {conc#1015.itm(0)} -attr vt d
+load net {conc#1015.itm(1)} -attr vt d
+load netBundle {conc#1015.itm} 2 {conc#1015.itm(0)} {conc#1015.itm(1)} -attr xrf 63766 -attr oid 956 -attr vt d -attr @path {/sobel/sobel:core/conc#1015.itm}
+load net {ACC1:slc#41.itm(0)} -attr vt d
+load net {ACC1:slc#41.itm(1)} -attr vt d
+load net {ACC1:slc#41.itm(2)} -attr vt d
+load net {ACC1:slc#41.itm(3)} -attr vt d
+load netBundle {ACC1:slc#41.itm} 4 {ACC1:slc#41.itm(0)} {ACC1:slc#41.itm(1)} {ACC1:slc#41.itm(2)} {ACC1:slc#41.itm(3)} -attr xrf 63767 -attr oid 957 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#41.itm}
+load net {ACC1:acc#365.itm(0)} -attr vt d
+load net {ACC1:acc#365.itm(1)} -attr vt d
+load net {ACC1:acc#365.itm(2)} -attr vt d
+load net {ACC1:acc#365.itm(3)} -attr vt d
+load net {ACC1:acc#365.itm(4)} -attr vt d
+load netBundle {ACC1:acc#365.itm} 5 {ACC1:acc#365.itm(0)} {ACC1:acc#365.itm(1)} {ACC1:acc#365.itm(2)} {ACC1:acc#365.itm(3)} {ACC1:acc#365.itm(4)} -attr xrf 63768 -attr oid 958 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365.itm}
+load net {conc#1016.itm(0)} -attr vt d
+load net {conc#1016.itm(1)} -attr vt d
+load net {conc#1016.itm(2)} -attr vt d
+load net {conc#1016.itm(3)} -attr vt d
+load netBundle {conc#1016.itm} 4 {conc#1016.itm(0)} {conc#1016.itm(1)} {conc#1016.itm(2)} {conc#1016.itm(3)} -attr xrf 63769 -attr oid 959 -attr vt d -attr @path {/sobel/sobel:core/conc#1016.itm}
+load net {ACC1:slc#39.itm(0)} -attr vt d
+load net {ACC1:slc#39.itm(1)} -attr vt d
+load net {ACC1:slc#39.itm(2)} -attr vt d
+load netBundle {ACC1:slc#39.itm} 3 {ACC1:slc#39.itm(0)} {ACC1:slc#39.itm(1)} {ACC1:slc#39.itm(2)} -attr xrf 63770 -attr oid 960 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#39.itm}
+load net {ACC1:acc#363.itm(0)} -attr vt d
+load net {ACC1:acc#363.itm(1)} -attr vt d
+load net {ACC1:acc#363.itm(2)} -attr vt d
+load net {ACC1:acc#363.itm(3)} -attr vt d
+load netBundle {ACC1:acc#363.itm} 4 {ACC1:acc#363.itm(0)} {ACC1:acc#363.itm(1)} {ACC1:acc#363.itm(2)} {ACC1:acc#363.itm(3)} -attr xrf 63771 -attr oid 961 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#363.itm}
+load net {conc#1017.itm(0)} -attr vt d
+load net {conc#1017.itm(1)} -attr vt d
+load netBundle {conc#1017.itm} 2 {conc#1017.itm(0)} {conc#1017.itm(1)} -attr xrf 63772 -attr oid 962 -attr vt d -attr @path {/sobel/sobel:core/conc#1017.itm}
+load net {ACC1:conc#1187.itm(0)} -attr vt d
+load net {ACC1:conc#1187.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1187.itm} 2 {ACC1:conc#1187.itm(0)} {ACC1:conc#1187.itm(1)} -attr xrf 63773 -attr oid 963 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1187.itm}
+load net {conc#1018.itm(0)} -attr vt d
+load net {conc#1018.itm(1)} -attr vt d
+load net {conc#1018.itm(2)} -attr vt d
+load net {conc#1018.itm(3)} -attr vt d
+load netBundle {conc#1018.itm} 4 {conc#1018.itm(0)} {conc#1018.itm(1)} {conc#1018.itm(2)} {conc#1018.itm(3)} -attr xrf 63774 -attr oid 964 -attr vt d -attr @path {/sobel/sobel:core/conc#1018.itm}
+load net {ACC1:slc#40.itm(0)} -attr vt d
+load net {ACC1:slc#40.itm(1)} -attr vt d
+load net {ACC1:slc#40.itm(2)} -attr vt d
+load netBundle {ACC1:slc#40.itm} 3 {ACC1:slc#40.itm(0)} {ACC1:slc#40.itm(1)} {ACC1:slc#40.itm(2)} -attr xrf 63775 -attr oid 965 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1:acc#364.itm(0)} -attr vt d
+load net {ACC1:acc#364.itm(1)} -attr vt d
+load net {ACC1:acc#364.itm(2)} -attr vt d
+load net {ACC1:acc#364.itm(3)} -attr vt d
+load netBundle {ACC1:acc#364.itm} 4 {ACC1:acc#364.itm(0)} {ACC1:acc#364.itm(1)} {ACC1:acc#364.itm(2)} {ACC1:acc#364.itm(3)} -attr xrf 63776 -attr oid 966 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#364.itm}
+load net {conc#1019.itm(0)} -attr vt d
+load net {conc#1019.itm(1)} -attr vt d
+load net {conc#1019.itm(2)} -attr vt d
+load netBundle {conc#1019.itm} 3 {conc#1019.itm(0)} {conc#1019.itm(1)} {conc#1019.itm(2)} -attr xrf 63777 -attr oid 967 -attr vt d -attr @path {/sobel/sobel:core/conc#1019.itm}
+load net {ACC1:slc#38.itm(0)} -attr vt d
+load net {ACC1:slc#38.itm(1)} -attr vt d
+load netBundle {ACC1:slc#38.itm} 2 {ACC1:slc#38.itm(0)} {ACC1:slc#38.itm(1)} -attr xrf 63778 -attr oid 968 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#38.itm}
+load net {ACC1:acc#362.itm(0)} -attr vt d
+load net {ACC1:acc#362.itm(1)} -attr vt d
+load net {ACC1:acc#362.itm(2)} -attr vt d
+load netBundle {ACC1:acc#362.itm} 3 {ACC1:acc#362.itm(0)} {ACC1:acc#362.itm(1)} {ACC1:acc#362.itm(2)} -attr xrf 63779 -attr oid 969 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#362.itm}
+load net {conc#1020.itm(0)} -attr vt d
+load net {conc#1020.itm(1)} -attr vt d
+load netBundle {conc#1020.itm} 2 {conc#1020.itm(0)} {conc#1020.itm(1)} -attr xrf 63780 -attr oid 970 -attr vt d -attr @path {/sobel/sobel:core/conc#1020.itm}
+load net {ACC1:conc#1185.itm(0)} -attr vt d
+load net {ACC1:conc#1185.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1185.itm} 2 {ACC1:conc#1185.itm(0)} {ACC1:conc#1185.itm(1)} -attr xrf 63781 -attr oid 971 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1185.itm}
+load net {ACC1:conc#1189.itm(0)} -attr vt d
+load net {ACC1:conc#1189.itm(1)} -attr vt d
+load net {ACC1:conc#1189.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1189.itm} 3 {ACC1:conc#1189.itm(0)} {ACC1:conc#1189.itm(1)} {ACC1:conc#1189.itm(2)} -attr xrf 63782 -attr oid 972 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1189.itm}
+load net {ACC1:slc#37.itm(0)} -attr vt d
+load net {ACC1:slc#37.itm(1)} -attr vt d
+load netBundle {ACC1:slc#37.itm} 2 {ACC1:slc#37.itm(0)} {ACC1:slc#37.itm(1)} -attr xrf 63783 -attr oid 973 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#37.itm}
+load net {ACC1:acc#361.itm(0)} -attr vt d
+load net {ACC1:acc#361.itm(1)} -attr vt d
+load net {ACC1:acc#361.itm(2)} -attr vt d
+load netBundle {ACC1:acc#361.itm} 3 {ACC1:acc#361.itm(0)} {ACC1:acc#361.itm(1)} {ACC1:acc#361.itm(2)} -attr xrf 63784 -attr oid 974 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#361.itm}
+load net {conc#1021.itm(0)} -attr vt d
+load net {conc#1021.itm(1)} -attr vt d
+load netBundle {conc#1021.itm} 2 {conc#1021.itm(0)} {conc#1021.itm(1)} -attr xrf 63785 -attr oid 975 -attr vt d -attr @path {/sobel/sobel:core/conc#1021.itm}
+load net {ACC1:conc#1183.itm(0)} -attr vt d
+load net {ACC1:conc#1183.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1183.itm} 2 {ACC1:conc#1183.itm(0)} {ACC1:conc#1183.itm(1)} -attr xrf 63786 -attr oid 976 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1183.itm}
+load net {ACC1:acc#349.itm(0)} -attr vt d
+load net {ACC1:acc#349.itm(1)} -attr vt d
+load net {ACC1:acc#349.itm(2)} -attr vt d
+load netBundle {ACC1:acc#349.itm} 3 {ACC1:acc#349.itm(0)} {ACC1:acc#349.itm(1)} {ACC1:acc#349.itm(2)} -attr xrf 63787 -attr oid 977 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#349.itm}
+load net {conc#1022.itm(0)} -attr vt d
+load net {conc#1022.itm(1)} -attr vt d
+load net {conc#1022.itm(2)} -attr vt d
+load netBundle {conc#1022.itm} 3 {conc#1022.itm(0)} {conc#1022.itm(1)} {conc#1022.itm(2)} -attr xrf 63788 -attr oid 978 -attr vt d -attr @path {/sobel/sobel:core/conc#1022.itm}
+load net {ACC1:conc#1162.itm(0)} -attr vt d
+load net {ACC1:conc#1162.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1162.itm} 2 {ACC1:conc#1162.itm(0)} {ACC1:conc#1162.itm(1)} -attr xrf 63789 -attr oid 979 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1162.itm}
+load net {ACC1:acc#348.itm(0)} -attr vt d
+load net {ACC1:acc#348.itm(1)} -attr vt d
+load net {ACC1:acc#348.itm(2)} -attr vt d
+load net {ACC1:acc#348.itm(3)} -attr vt d
+load netBundle {ACC1:acc#348.itm} 4 {ACC1:acc#348.itm(0)} {ACC1:acc#348.itm(1)} {ACC1:acc#348.itm(2)} {ACC1:acc#348.itm(3)} -attr xrf 63790 -attr oid 980 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {conc#1023.itm(0)} -attr vt d
+load net {conc#1023.itm(1)} -attr vt d
+load net {conc#1023.itm(2)} -attr vt d
+load netBundle {conc#1023.itm} 3 {conc#1023.itm(0)} {conc#1023.itm(1)} {conc#1023.itm(2)} -attr xrf 63791 -attr oid 981 -attr vt d -attr @path {/sobel/sobel:core/conc#1023.itm}
+load net {ACC1-1:not#297.itm(0)} -attr vt d
+load net {ACC1-1:not#297.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#297.itm} 2 {ACC1-1:not#297.itm(0)} {ACC1-1:not#297.itm(1)} -attr xrf 63792 -attr oid 982 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#297.itm}
+load net {slc(ACC1:acc#222.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#222.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#222.psp#1.sva).itm} 2 {slc(ACC1:acc#222.psp#1.sva).itm(0)} {slc(ACC1:acc#222.psp#1.sva).itm(1)} -attr xrf 63793 -attr oid 983 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp#1.sva).itm}
+load net {conc#1024.itm(0)} -attr vt d
+load net {conc#1024.itm(1)} -attr vt d
+load netBundle {conc#1024.itm} 2 {conc#1024.itm(0)} {conc#1024.itm(1)} -attr xrf 63794 -attr oid 984 -attr vt d -attr @path {/sobel/sobel:core/conc#1024.itm}
+load net {ACC1:acc#407.itm(0)} -attr vt d
+load net {ACC1:acc#407.itm(1)} -attr vt d
+load net {ACC1:acc#407.itm(2)} -attr vt d
+load net {ACC1:acc#407.itm(3)} -attr vt d
+load net {ACC1:acc#407.itm(4)} -attr vt d
+load net {ACC1:acc#407.itm(5)} -attr vt d
+load net {ACC1:acc#407.itm(6)} -attr vt d
+load net {ACC1:acc#407.itm(7)} -attr vt d
+load net {ACC1:acc#407.itm(8)} -attr vt d
+load net {ACC1:acc#407.itm(9)} -attr vt d
+load net {ACC1:acc#407.itm(10)} -attr vt d
+load netBundle {ACC1:acc#407.itm} 11 {ACC1:acc#407.itm(0)} {ACC1:acc#407.itm(1)} {ACC1:acc#407.itm(2)} {ACC1:acc#407.itm(3)} {ACC1:acc#407.itm(4)} {ACC1:acc#407.itm(5)} {ACC1:acc#407.itm(6)} {ACC1:acc#407.itm(7)} {ACC1:acc#407.itm(8)} {ACC1:acc#407.itm(9)} {ACC1:acc#407.itm(10)} -attr xrf 63795 -attr oid 985 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1-2:exs#1051.itm(0)} -attr vt d
+load net {ACC1-2:exs#1051.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1051.itm} 2 {ACC1-2:exs#1051.itm(0)} {ACC1-2:exs#1051.itm(1)} -attr xrf 63796 -attr oid 986 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1051.itm}
+load net {ACC1-2:exs#1043.itm(0)} -attr vt d
+load net {ACC1-2:exs#1043.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#1043.itm} 2 {ACC1-2:exs#1043.itm(0)} {ACC1-2:exs#1043.itm(1)} -attr xrf 63797 -attr oid 987 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1043.itm}
+load net {ACC1:acc#412.itm(0)} -attr vt d
+load net {ACC1:acc#412.itm(1)} -attr vt d
+load net {ACC1:acc#412.itm(2)} -attr vt d
+load net {ACC1:acc#412.itm(3)} -attr vt d
+load net {ACC1:acc#412.itm(4)} -attr vt d
+load netBundle {ACC1:acc#412.itm} 5 {ACC1:acc#412.itm(0)} {ACC1:acc#412.itm(1)} {ACC1:acc#412.itm(2)} {ACC1:acc#412.itm(3)} {ACC1:acc#412.itm(4)} -attr xrf 63798 -attr oid 988 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412.itm}
+load net {conc#1025.itm(0)} -attr vt d
+load net {conc#1025.itm(1)} -attr vt d
+load net {conc#1025.itm(2)} -attr vt d
+load net {conc#1025.itm(3)} -attr vt d
+load netBundle {conc#1025.itm} 4 {conc#1025.itm(0)} {conc#1025.itm(1)} {conc#1025.itm(2)} {conc#1025.itm(3)} -attr xrf 63799 -attr oid 989 -attr vt d -attr @path {/sobel/sobel:core/conc#1025.itm}
+load net {ACC1:slc#80.itm(0)} -attr vt d
+load net {ACC1:slc#80.itm(1)} -attr vt d
+load net {ACC1:slc#80.itm(2)} -attr vt d
+load netBundle {ACC1:slc#80.itm} 3 {ACC1:slc#80.itm(0)} {ACC1:slc#80.itm(1)} {ACC1:slc#80.itm(2)} -attr xrf 63800 -attr oid 990 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#80.itm}
+load net {ACC1:acc#411.itm(0)} -attr vt d
+load net {ACC1:acc#411.itm(1)} -attr vt d
+load net {ACC1:acc#411.itm(2)} -attr vt d
+load net {ACC1:acc#411.itm(3)} -attr vt d
+load netBundle {ACC1:acc#411.itm} 4 {ACC1:acc#411.itm(0)} {ACC1:acc#411.itm(1)} {ACC1:acc#411.itm(2)} {ACC1:acc#411.itm(3)} -attr xrf 63801 -attr oid 991 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#411.itm}
+load net {conc#1026.itm(0)} -attr vt d
+load net {conc#1026.itm(1)} -attr vt d
+load net {conc#1026.itm(2)} -attr vt d
+load net {conc#1026.itm(3)} -attr vt d
+load netBundle {conc#1026.itm} 4 {conc#1026.itm(0)} {conc#1026.itm(1)} {conc#1026.itm(2)} {conc#1026.itm(3)} -attr xrf 63802 -attr oid 992 -attr vt d -attr @path {/sobel/sobel:core/conc#1026.itm}
+load net {ACC1:conc#1279.itm(0)} -attr vt d
+load net {ACC1:conc#1279.itm(1)} -attr vt d
+load net {ACC1:conc#1279.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1279.itm} 3 {ACC1:conc#1279.itm(0)} {ACC1:conc#1279.itm(1)} {ACC1:conc#1279.itm(2)} -attr xrf 63803 -attr oid 993 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1279.itm}
+load net {ACC1:slc#78.itm(0)} -attr vt d
+load net {ACC1:slc#78.itm(1)} -attr vt d
+load netBundle {ACC1:slc#78.itm} 2 {ACC1:slc#78.itm(0)} {ACC1:slc#78.itm(1)} -attr xrf 63804 -attr oid 994 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#78.itm}
+load net {ACC1:acc#409.itm(0)} -attr vt d
+load net {ACC1:acc#409.itm(1)} -attr vt d
+load net {ACC1:acc#409.itm(2)} -attr vt d
+load netBundle {ACC1:acc#409.itm} 3 {ACC1:acc#409.itm(0)} {ACC1:acc#409.itm(1)} {ACC1:acc#409.itm(2)} -attr xrf 63805 -attr oid 995 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#409.itm}
+load net {conc#1027.itm(0)} -attr vt d
+load net {conc#1027.itm(1)} -attr vt d
+load netBundle {conc#1027.itm} 2 {conc#1027.itm(0)} {conc#1027.itm(1)} -attr xrf 63806 -attr oid 996 -attr vt d -attr @path {/sobel/sobel:core/conc#1027.itm}
+load net {ACC1:conc#1275.itm(0)} -attr vt d
+load net {ACC1:conc#1275.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1275.itm} 2 {ACC1:conc#1275.itm(0)} {ACC1:conc#1275.itm(1)} -attr xrf 63807 -attr oid 997 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1275.itm}
+load net {ACC1:conc#1281.itm(0)} -attr vt d
+load net {ACC1:conc#1281.itm(1)} -attr vt d
+load net {ACC1:conc#1281.itm(2)} -attr vt d
+load net {ACC1:conc#1281.itm(3)} -attr vt d
+load net {ACC1:conc#1281.itm(4)} -attr vt d
+load netBundle {ACC1:conc#1281.itm} 5 {ACC1:conc#1281.itm(0)} {ACC1:conc#1281.itm(1)} {ACC1:conc#1281.itm(2)} {ACC1:conc#1281.itm(3)} {ACC1:conc#1281.itm(4)} -attr xrf 63808 -attr oid 998 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1281.itm}
+load net {ACC1:slc#79.itm(0)} -attr vt d
+load net {ACC1:slc#79.itm(1)} -attr vt d
+load net {ACC1:slc#79.itm(2)} -attr vt d
+load net {ACC1:slc#79.itm(3)} -attr vt d
+load netBundle {ACC1:slc#79.itm} 4 {ACC1:slc#79.itm(0)} {ACC1:slc#79.itm(1)} {ACC1:slc#79.itm(2)} {ACC1:slc#79.itm(3)} -attr xrf 63809 -attr oid 999 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#79.itm}
+load net {ACC1:acc#410.itm(0)} -attr vt d
+load net {ACC1:acc#410.itm(1)} -attr vt d
+load net {ACC1:acc#410.itm(2)} -attr vt d
+load net {ACC1:acc#410.itm(3)} -attr vt d
+load net {ACC1:acc#410.itm(4)} -attr vt d
+load netBundle {ACC1:acc#410.itm} 5 {ACC1:acc#410.itm(0)} {ACC1:acc#410.itm(1)} {ACC1:acc#410.itm(2)} {ACC1:acc#410.itm(3)} {ACC1:acc#410.itm(4)} -attr xrf 63810 -attr oid 1000 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410.itm}
+load net {conc#1028.itm(0)} -attr vt d
+load net {conc#1028.itm(1)} -attr vt d
+load net {conc#1028.itm(2)} -attr vt d
+load netBundle {conc#1028.itm} 3 {conc#1028.itm(0)} {conc#1028.itm(1)} {conc#1028.itm(2)} -attr xrf 63811 -attr oid 1001 -attr vt d -attr @path {/sobel/sobel:core/conc#1028.itm}
+load net {ACC1:slc#77.itm(0)} -attr vt d
+load net {ACC1:slc#77.itm(1)} -attr vt d
+load netBundle {ACC1:slc#77.itm} 2 {ACC1:slc#77.itm(0)} {ACC1:slc#77.itm(1)} -attr xrf 63812 -attr oid 1002 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#77.itm}
+load net {ACC1:acc#408.itm(0)} -attr vt d
+load net {ACC1:acc#408.itm(1)} -attr vt d
+load net {ACC1:acc#408.itm(2)} -attr vt d
+load netBundle {ACC1:acc#408.itm} 3 {ACC1:acc#408.itm(0)} {ACC1:acc#408.itm(1)} {ACC1:acc#408.itm(2)} -attr xrf 63813 -attr oid 1003 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#408.itm}
+load net {conc#1029.itm(0)} -attr vt d
+load net {conc#1029.itm(1)} -attr vt d
+load netBundle {conc#1029.itm} 2 {conc#1029.itm(0)} {conc#1029.itm(1)} -attr xrf 63814 -attr oid 1004 -attr vt d -attr @path {/sobel/sobel:core/conc#1029.itm}
+load net {ACC1:conc#1273.itm(0)} -attr vt d
+load net {ACC1:conc#1273.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1273.itm} 2 {ACC1:conc#1273.itm(0)} {ACC1:conc#1273.itm(1)} -attr xrf 63815 -attr oid 1005 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1273.itm}
+load net {ACC1:conc#1277.itm(0)} -attr vt d
+load net {ACC1:conc#1277.itm(1)} -attr vt d
+load net {ACC1:conc#1277.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1277.itm} 3 {ACC1:conc#1277.itm(0)} {ACC1:conc#1277.itm(1)} {ACC1:conc#1277.itm(2)} -attr xrf 63816 -attr oid 1006 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1277.itm}
+load net {ACC1-3:not#252.itm(0)} -attr vt d
+load net {ACC1-3:not#252.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#252.itm} 2 {ACC1-3:not#252.itm(0)} {ACC1-3:not#252.itm(1)} -attr xrf 63817 -attr oid 1007 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#252.itm}
+load net {slc(ACC1:acc#224.psp.sva)#14.itm(0)} -attr vt d
+load net {slc(ACC1:acc#224.psp.sva)#14.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#224.psp.sva)#14.itm} 2 {slc(ACC1:acc#224.psp.sva)#14.itm(0)} {slc(ACC1:acc#224.psp.sva)#14.itm(1)} -attr xrf 63818 -attr oid 1008 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#14.itm}
+load net {ACC1:acc#423.itm(0)} -attr vt d
+load net {ACC1:acc#423.itm(1)} -attr vt d
+load net {ACC1:acc#423.itm(2)} -attr vt d
+load net {ACC1:acc#423.itm(3)} -attr vt d
+load netBundle {ACC1:acc#423.itm} 4 {ACC1:acc#423.itm(0)} {ACC1:acc#423.itm(1)} {ACC1:acc#423.itm(2)} {ACC1:acc#423.itm(3)} -attr xrf 63819 -attr oid 1009 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#423.itm}
+load net {conc#1030.itm(0)} -attr vt d
+load net {conc#1030.itm(1)} -attr vt d
+load net {conc#1030.itm(2)} -attr vt d
+load netBundle {conc#1030.itm} 3 {conc#1030.itm(0)} {conc#1030.itm(1)} {conc#1030.itm(2)} -attr xrf 63820 -attr oid 1010 -attr vt d -attr @path {/sobel/sobel:core/conc#1030.itm}
+load net {ACC1-3:not#299.itm(0)} -attr vt d
+load net {ACC1-3:not#299.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#299.itm} 2 {ACC1-3:not#299.itm(0)} {ACC1-3:not#299.itm(1)} -attr xrf 63821 -attr oid 1011 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#299.itm}
+load net {slc(ACC1:acc#223.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#223.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#223.psp.sva).itm} 2 {slc(ACC1:acc#223.psp.sva).itm(0)} {slc(ACC1:acc#223.psp.sva).itm(1)} -attr xrf 63822 -attr oid 1012 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp.sva).itm}
+load net {conc#1031.itm(0)} -attr vt d
+load net {conc#1031.itm(1)} -attr vt d
+load netBundle {conc#1031.itm} 2 {conc#1031.itm(0)} {conc#1031.itm(1)} -attr xrf 63823 -attr oid 1013 -attr vt d -attr @path {/sobel/sobel:core/conc#1031.itm}
+load net {ACC1:acc#375.itm(0)} -attr vt d
+load net {ACC1:acc#375.itm(1)} -attr vt d
+load net {ACC1:acc#375.itm(2)} -attr vt d
+load net {ACC1:acc#375.itm(3)} -attr vt d
+load net {ACC1:acc#375.itm(4)} -attr vt d
+load netBundle {ACC1:acc#375.itm} 5 {ACC1:acc#375.itm(0)} {ACC1:acc#375.itm(1)} {ACC1:acc#375.itm(2)} {ACC1:acc#375.itm(3)} {ACC1:acc#375.itm(4)} -attr xrf 63824 -attr oid 1014 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375.itm}
+load net {conc#1032.itm(0)} -attr vt d
+load net {conc#1032.itm(1)} -attr vt d
+load net {conc#1032.itm(2)} -attr vt d
+load net {conc#1032.itm(3)} -attr vt d
+load netBundle {conc#1032.itm} 4 {conc#1032.itm(0)} {conc#1032.itm(1)} {conc#1032.itm(2)} {conc#1032.itm(3)} -attr xrf 63825 -attr oid 1015 -attr vt d -attr @path {/sobel/sobel:core/conc#1032.itm}
+load net {ACC1:slc#48.itm(0)} -attr vt d
+load net {ACC1:slc#48.itm(1)} -attr vt d
+load net {ACC1:slc#48.itm(2)} -attr vt d
+load netBundle {ACC1:slc#48.itm} 3 {ACC1:slc#48.itm(0)} {ACC1:slc#48.itm(1)} {ACC1:slc#48.itm(2)} -attr xrf 63826 -attr oid 1016 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#48.itm}
+load net {ACC1:acc#374.itm(0)} -attr vt d
+load net {ACC1:acc#374.itm(1)} -attr vt d
+load net {ACC1:acc#374.itm(2)} -attr vt d
+load net {ACC1:acc#374.itm(3)} -attr vt d
+load netBundle {ACC1:acc#374.itm} 4 {ACC1:acc#374.itm(0)} {ACC1:acc#374.itm(1)} {ACC1:acc#374.itm(2)} {ACC1:acc#374.itm(3)} -attr xrf 63827 -attr oid 1017 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#374.itm}
+load net {conc#1033.itm(0)} -attr vt d
+load net {conc#1033.itm(1)} -attr vt d
+load net {conc#1033.itm(2)} -attr vt d
+load net {conc#1033.itm(3)} -attr vt d
+load netBundle {conc#1033.itm} 4 {conc#1033.itm(0)} {conc#1033.itm(1)} {conc#1033.itm(2)} {conc#1033.itm(3)} -attr xrf 63828 -attr oid 1018 -attr vt d -attr @path {/sobel/sobel:core/conc#1033.itm}
+load net {ACC1:conc#1207.itm(0)} -attr vt d
+load net {ACC1:conc#1207.itm(1)} -attr vt d
+load net {ACC1:conc#1207.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1207.itm} 3 {ACC1:conc#1207.itm(0)} {ACC1:conc#1207.itm(1)} {ACC1:conc#1207.itm(2)} -attr xrf 63829 -attr oid 1019 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1207.itm}
+load net {ACC1:slc#46.itm(0)} -attr vt d
+load net {ACC1:slc#46.itm(1)} -attr vt d
+load netBundle {ACC1:slc#46.itm} 2 {ACC1:slc#46.itm(0)} {ACC1:slc#46.itm(1)} -attr xrf 63830 -attr oid 1020 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#46.itm}
+load net {ACC1:acc#372.itm(0)} -attr vt d
+load net {ACC1:acc#372.itm(1)} -attr vt d
+load net {ACC1:acc#372.itm(2)} -attr vt d
+load netBundle {ACC1:acc#372.itm} 3 {ACC1:acc#372.itm(0)} {ACC1:acc#372.itm(1)} {ACC1:acc#372.itm(2)} -attr xrf 63831 -attr oid 1021 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#372.itm}
+load net {conc#1034.itm(0)} -attr vt d
+load net {conc#1034.itm(1)} -attr vt d
+load netBundle {conc#1034.itm} 2 {conc#1034.itm(0)} {conc#1034.itm(1)} -attr xrf 63832 -attr oid 1022 -attr vt d -attr @path {/sobel/sobel:core/conc#1034.itm}
+load net {ACC1:conc#1203.itm(0)} -attr vt d
+load net {ACC1:conc#1203.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1203.itm} 2 {ACC1:conc#1203.itm(0)} {ACC1:conc#1203.itm(1)} -attr xrf 63833 -attr oid 1023 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1203.itm}
+load net {ACC1:conc#1209.itm(0)} -attr vt d
+load net {ACC1:conc#1209.itm(1)} -attr vt d
+load net {ACC1:conc#1209.itm(2)} -attr vt d
+load net {ACC1:conc#1209.itm(3)} -attr vt d
+load net {ACC1:conc#1209.itm(4)} -attr vt d
+load netBundle {ACC1:conc#1209.itm} 5 {ACC1:conc#1209.itm(0)} {ACC1:conc#1209.itm(1)} {ACC1:conc#1209.itm(2)} {ACC1:conc#1209.itm(3)} {ACC1:conc#1209.itm(4)} -attr xrf 63834 -attr oid 1024 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1209.itm}
+load net {ACC1:slc#47.itm(0)} -attr vt d
+load net {ACC1:slc#47.itm(1)} -attr vt d
+load net {ACC1:slc#47.itm(2)} -attr vt d
+load net {ACC1:slc#47.itm(3)} -attr vt d
+load netBundle {ACC1:slc#47.itm} 4 {ACC1:slc#47.itm(0)} {ACC1:slc#47.itm(1)} {ACC1:slc#47.itm(2)} {ACC1:slc#47.itm(3)} -attr xrf 63835 -attr oid 1025 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#47.itm}
+load net {ACC1:acc#373.itm(0)} -attr vt d
+load net {ACC1:acc#373.itm(1)} -attr vt d
+load net {ACC1:acc#373.itm(2)} -attr vt d
+load net {ACC1:acc#373.itm(3)} -attr vt d
+load net {ACC1:acc#373.itm(4)} -attr vt d
+load netBundle {ACC1:acc#373.itm} 5 {ACC1:acc#373.itm(0)} {ACC1:acc#373.itm(1)} {ACC1:acc#373.itm(2)} {ACC1:acc#373.itm(3)} {ACC1:acc#373.itm(4)} -attr xrf 63836 -attr oid 1026 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373.itm}
+load net {conc#1035.itm(0)} -attr vt d
+load net {conc#1035.itm(1)} -attr vt d
+load net {conc#1035.itm(2)} -attr vt d
+load netBundle {conc#1035.itm} 3 {conc#1035.itm(0)} {conc#1035.itm(1)} {conc#1035.itm(2)} -attr xrf 63837 -attr oid 1027 -attr vt d -attr @path {/sobel/sobel:core/conc#1035.itm}
+load net {ACC1:slc#45.itm(0)} -attr vt d
+load net {ACC1:slc#45.itm(1)} -attr vt d
+load netBundle {ACC1:slc#45.itm} 2 {ACC1:slc#45.itm(0)} {ACC1:slc#45.itm(1)} -attr xrf 63838 -attr oid 1028 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#45.itm}
+load net {ACC1:acc#371.itm(0)} -attr vt d
+load net {ACC1:acc#371.itm(1)} -attr vt d
+load net {ACC1:acc#371.itm(2)} -attr vt d
+load netBundle {ACC1:acc#371.itm} 3 {ACC1:acc#371.itm(0)} {ACC1:acc#371.itm(1)} {ACC1:acc#371.itm(2)} -attr xrf 63839 -attr oid 1029 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#371.itm}
+load net {conc#1036.itm(0)} -attr vt d
+load net {conc#1036.itm(1)} -attr vt d
+load netBundle {conc#1036.itm} 2 {conc#1036.itm(0)} {conc#1036.itm(1)} -attr xrf 63840 -attr oid 1030 -attr vt d -attr @path {/sobel/sobel:core/conc#1036.itm}
+load net {ACC1:conc#1201.itm(0)} -attr vt d
+load net {ACC1:conc#1201.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1201.itm} 2 {ACC1:conc#1201.itm(0)} {ACC1:conc#1201.itm(1)} -attr xrf 63841 -attr oid 1031 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1201.itm}
+load net {ACC1:conc#1205.itm(0)} -attr vt d
+load net {ACC1:conc#1205.itm(1)} -attr vt d
+load net {ACC1:conc#1205.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1205.itm} 3 {ACC1:conc#1205.itm(0)} {ACC1:conc#1205.itm(1)} {ACC1:conc#1205.itm(2)} -attr xrf 63842 -attr oid 1032 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1205.itm}
+load net {ACC1-2:not#243.itm(0)} -attr vt d
+load net {ACC1-2:not#243.itm(1)} -attr vt d
+load netBundle {ACC1-2:not#243.itm} 2 {ACC1-2:not#243.itm(0)} {ACC1-2:not#243.itm(1)} -attr xrf 63843 -attr oid 1033 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#243.itm}
+load net {slc(ACC1:acc#228.psp.sva)#12.itm(0)} -attr vt d
+load net {slc(ACC1:acc#228.psp.sva)#12.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#228.psp.sva)#12.itm} 2 {slc(ACC1:acc#228.psp.sva)#12.itm(0)} {slc(ACC1:acc#228.psp.sva)#12.itm(1)} -attr xrf 63844 -attr oid 1034 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#12.itm}
+load net {ACC1:acc#395.itm(0)} -attr vt d
+load net {ACC1:acc#395.itm(1)} -attr vt d
+load net {ACC1:acc#395.itm(2)} -attr vt d
+load net {ACC1:acc#395.itm(3)} -attr vt d
+load netBundle {ACC1:acc#395.itm} 4 {ACC1:acc#395.itm(0)} {ACC1:acc#395.itm(1)} {ACC1:acc#395.itm(2)} {ACC1:acc#395.itm(3)} -attr xrf 63845 -attr oid 1035 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#395.itm}
+load net {conc#1037.itm(0)} -attr vt d
+load net {conc#1037.itm(1)} -attr vt d
+load net {conc#1037.itm(2)} -attr vt d
+load netBundle {conc#1037.itm} 3 {conc#1037.itm(0)} {conc#1037.itm(1)} {conc#1037.itm(2)} -attr xrf 63846 -attr oid 1036 -attr vt d -attr @path {/sobel/sobel:core/conc#1037.itm}
+load net {ACC1-3:not#293.itm(0)} -attr vt d
+load net {ACC1-3:not#293.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#293.itm} 2 {ACC1-3:not#293.itm(0)} {ACC1-3:not#293.itm(1)} -attr xrf 63847 -attr oid 1037 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#293.itm}
+load net {slc(ACC1:acc#220.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#220.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#220.psp.sva).itm} 2 {slc(ACC1:acc#220.psp.sva).itm(0)} {slc(ACC1:acc#220.psp.sva).itm(1)} -attr xrf 63848 -attr oid 1038 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp.sva).itm}
+load net {conc#1038.itm(0)} -attr vt d
+load net {conc#1038.itm(1)} -attr vt d
+load netBundle {conc#1038.itm} 2 {conc#1038.itm(0)} {conc#1038.itm(1)} -attr xrf 63849 -attr oid 1039 -attr vt d -attr @path {/sobel/sobel:core/conc#1038.itm}
+load net {ACC1:acc#384.itm(0)} -attr vt d
+load net {ACC1:acc#384.itm(1)} -attr vt d
+load net {ACC1:acc#384.itm(2)} -attr vt d
+load net {ACC1:acc#384.itm(3)} -attr vt d
+load net {ACC1:acc#384.itm(4)} -attr vt d
+load netBundle {ACC1:acc#384.itm} 5 {ACC1:acc#384.itm(0)} {ACC1:acc#384.itm(1)} {ACC1:acc#384.itm(2)} {ACC1:acc#384.itm(3)} {ACC1:acc#384.itm(4)} -attr xrf 63850 -attr oid 1040 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384.itm}
+load net {conc#1039.itm(0)} -attr vt d
+load net {conc#1039.itm(1)} -attr vt d
+load net {conc#1039.itm(2)} -attr vt d
+load net {conc#1039.itm(3)} -attr vt d
+load netBundle {conc#1039.itm} 4 {conc#1039.itm(0)} {conc#1039.itm(1)} {conc#1039.itm(2)} {conc#1039.itm(3)} -attr xrf 63851 -attr oid 1041 -attr vt d -attr @path {/sobel/sobel:core/conc#1039.itm}
+load net {ACC1:slc#56.itm(0)} -attr vt d
+load net {ACC1:slc#56.itm(1)} -attr vt d
+load net {ACC1:slc#56.itm(2)} -attr vt d
+load netBundle {ACC1:slc#56.itm} 3 {ACC1:slc#56.itm(0)} {ACC1:slc#56.itm(1)} {ACC1:slc#56.itm(2)} -attr xrf 63852 -attr oid 1042 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#56.itm}
+load net {ACC1:acc#383.itm(0)} -attr vt d
+load net {ACC1:acc#383.itm(1)} -attr vt d
+load net {ACC1:acc#383.itm(2)} -attr vt d
+load net {ACC1:acc#383.itm(3)} -attr vt d
+load netBundle {ACC1:acc#383.itm} 4 {ACC1:acc#383.itm(0)} {ACC1:acc#383.itm(1)} {ACC1:acc#383.itm(2)} {ACC1:acc#383.itm(3)} -attr xrf 63853 -attr oid 1043 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#383.itm}
+load net {conc#1040.itm(0)} -attr vt d
+load net {conc#1040.itm(1)} -attr vt d
+load net {conc#1040.itm(2)} -attr vt d
+load net {conc#1040.itm(3)} -attr vt d
+load netBundle {conc#1040.itm} 4 {conc#1040.itm(0)} {conc#1040.itm(1)} {conc#1040.itm(2)} {conc#1040.itm(3)} -attr xrf 63854 -attr oid 1044 -attr vt d -attr @path {/sobel/sobel:core/conc#1040.itm}
+load net {ACC1:conc#1225.itm(0)} -attr vt d
+load net {ACC1:conc#1225.itm(1)} -attr vt d
+load net {ACC1:conc#1225.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1225.itm} 3 {ACC1:conc#1225.itm(0)} {ACC1:conc#1225.itm(1)} {ACC1:conc#1225.itm(2)} -attr xrf 63855 -attr oid 1045 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1225.itm}
+load net {ACC1:slc#54.itm(0)} -attr vt d
+load net {ACC1:slc#54.itm(1)} -attr vt d
+load netBundle {ACC1:slc#54.itm} 2 {ACC1:slc#54.itm(0)} {ACC1:slc#54.itm(1)} -attr xrf 63856 -attr oid 1046 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#54.itm}
+load net {ACC1:acc#381.itm(0)} -attr vt d
+load net {ACC1:acc#381.itm(1)} -attr vt d
+load net {ACC1:acc#381.itm(2)} -attr vt d
+load netBundle {ACC1:acc#381.itm} 3 {ACC1:acc#381.itm(0)} {ACC1:acc#381.itm(1)} {ACC1:acc#381.itm(2)} -attr xrf 63857 -attr oid 1047 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#381.itm}
+load net {conc#1041.itm(0)} -attr vt d
+load net {conc#1041.itm(1)} -attr vt d
+load netBundle {conc#1041.itm} 2 {conc#1041.itm(0)} {conc#1041.itm(1)} -attr xrf 63858 -attr oid 1048 -attr vt d -attr @path {/sobel/sobel:core/conc#1041.itm}
+load net {ACC1:conc#1221.itm(0)} -attr vt d
+load net {ACC1:conc#1221.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1221.itm} 2 {ACC1:conc#1221.itm(0)} {ACC1:conc#1221.itm(1)} -attr xrf 63859 -attr oid 1049 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1221.itm}
+load net {ACC1:conc#1227.itm(0)} -attr vt d
+load net {ACC1:conc#1227.itm(1)} -attr vt d
+load net {ACC1:conc#1227.itm(2)} -attr vt d
+load net {ACC1:conc#1227.itm(3)} -attr vt d
+load net {ACC1:conc#1227.itm(4)} -attr vt d
+load netBundle {ACC1:conc#1227.itm} 5 {ACC1:conc#1227.itm(0)} {ACC1:conc#1227.itm(1)} {ACC1:conc#1227.itm(2)} {ACC1:conc#1227.itm(3)} {ACC1:conc#1227.itm(4)} -attr xrf 63860 -attr oid 1050 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1227.itm}
+load net {ACC1:slc#55.itm(0)} -attr vt d
+load net {ACC1:slc#55.itm(1)} -attr vt d
+load net {ACC1:slc#55.itm(2)} -attr vt d
+load net {ACC1:slc#55.itm(3)} -attr vt d
+load netBundle {ACC1:slc#55.itm} 4 {ACC1:slc#55.itm(0)} {ACC1:slc#55.itm(1)} {ACC1:slc#55.itm(2)} {ACC1:slc#55.itm(3)} -attr xrf 63861 -attr oid 1051 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#55.itm}
+load net {ACC1:acc#382.itm(0)} -attr vt d
+load net {ACC1:acc#382.itm(1)} -attr vt d
+load net {ACC1:acc#382.itm(2)} -attr vt d
+load net {ACC1:acc#382.itm(3)} -attr vt d
+load net {ACC1:acc#382.itm(4)} -attr vt d
+load netBundle {ACC1:acc#382.itm} 5 {ACC1:acc#382.itm(0)} {ACC1:acc#382.itm(1)} {ACC1:acc#382.itm(2)} {ACC1:acc#382.itm(3)} {ACC1:acc#382.itm(4)} -attr xrf 63862 -attr oid 1052 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382.itm}
+load net {conc#1042.itm(0)} -attr vt d
+load net {conc#1042.itm(1)} -attr vt d
+load net {conc#1042.itm(2)} -attr vt d
+load netBundle {conc#1042.itm} 3 {conc#1042.itm(0)} {conc#1042.itm(1)} {conc#1042.itm(2)} -attr xrf 63863 -attr oid 1053 -attr vt d -attr @path {/sobel/sobel:core/conc#1042.itm}
+load net {ACC1:slc#53.itm(0)} -attr vt d
+load net {ACC1:slc#53.itm(1)} -attr vt d
+load netBundle {ACC1:slc#53.itm} 2 {ACC1:slc#53.itm(0)} {ACC1:slc#53.itm(1)} -attr xrf 63864 -attr oid 1054 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#53.itm}
+load net {ACC1:acc#380.itm(0)} -attr vt d
+load net {ACC1:acc#380.itm(1)} -attr vt d
+load net {ACC1:acc#380.itm(2)} -attr vt d
+load netBundle {ACC1:acc#380.itm} 3 {ACC1:acc#380.itm(0)} {ACC1:acc#380.itm(1)} {ACC1:acc#380.itm(2)} -attr xrf 63865 -attr oid 1055 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#380.itm}
+load net {conc#1043.itm(0)} -attr vt d
+load net {conc#1043.itm(1)} -attr vt d
+load netBundle {conc#1043.itm} 2 {conc#1043.itm(0)} {conc#1043.itm(1)} -attr xrf 63866 -attr oid 1056 -attr vt d -attr @path {/sobel/sobel:core/conc#1043.itm}
+load net {ACC1:conc#1219.itm(0)} -attr vt d
+load net {ACC1:conc#1219.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1219.itm} 2 {ACC1:conc#1219.itm(0)} {ACC1:conc#1219.itm(1)} -attr xrf 63867 -attr oid 1057 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1219.itm}
+load net {ACC1:conc#1223.itm(0)} -attr vt d
+load net {ACC1:conc#1223.itm(1)} -attr vt d
+load net {ACC1:conc#1223.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1223.itm} 3 {ACC1:conc#1223.itm(0)} {ACC1:conc#1223.itm(1)} {ACC1:conc#1223.itm(2)} -attr xrf 63868 -attr oid 1058 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1223.itm}
+load net {ACC1-2:not#225.itm(0)} -attr vt d
+load net {ACC1-2:not#225.itm(1)} -attr vt d
+load netBundle {ACC1-2:not#225.itm} 2 {ACC1-2:not#225.itm(0)} {ACC1-2:not#225.itm(1)} -attr xrf 63869 -attr oid 1059 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#225.itm}
+load net {slc(ACC1:acc#226.psp.sva)#12.itm(0)} -attr vt d
+load net {slc(ACC1:acc#226.psp.sva)#12.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#226.psp.sva)#12.itm} 2 {slc(ACC1:acc#226.psp.sva)#12.itm(0)} {slc(ACC1:acc#226.psp.sva)#12.itm(1)} -attr xrf 63870 -attr oid 1060 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#12.itm}
+load net {ACC1:slc#73.itm(0)} -attr vt d
+load net {ACC1:slc#73.itm(1)} -attr vt d
+load net {ACC1:slc#73.itm(2)} -attr vt d
+load net {ACC1:slc#73.itm(3)} -attr vt d
+load netBundle {ACC1:slc#73.itm} 4 {ACC1:slc#73.itm(0)} {ACC1:slc#73.itm(1)} {ACC1:slc#73.itm(2)} {ACC1:slc#73.itm(3)} -attr xrf 63871 -attr oid 1061 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#403.itm(0)} -attr vt d
+load net {ACC1:acc#403.itm(1)} -attr vt d
+load net {ACC1:acc#403.itm(2)} -attr vt d
+load net {ACC1:acc#403.itm(3)} -attr vt d
+load net {ACC1:acc#403.itm(4)} -attr vt d
+load netBundle {ACC1:acc#403.itm} 5 {ACC1:acc#403.itm(0)} {ACC1:acc#403.itm(1)} {ACC1:acc#403.itm(2)} {ACC1:acc#403.itm(3)} {ACC1:acc#403.itm(4)} -attr xrf 63872 -attr oid 1062 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403.itm}
+load net {conc#1044.itm(0)} -attr vt d
+load net {conc#1044.itm(1)} -attr vt d
+load net {conc#1044.itm(2)} -attr vt d
+load net {conc#1044.itm(3)} -attr vt d
+load netBundle {conc#1044.itm} 4 {conc#1044.itm(0)} {conc#1044.itm(1)} {conc#1044.itm(2)} {conc#1044.itm(3)} -attr xrf 63873 -attr oid 1063 -attr vt d -attr @path {/sobel/sobel:core/conc#1044.itm}
+load net {ACC1:slc#71.itm(0)} -attr vt d
+load net {ACC1:slc#71.itm(1)} -attr vt d
+load net {ACC1:slc#71.itm(2)} -attr vt d
+load netBundle {ACC1:slc#71.itm} 3 {ACC1:slc#71.itm(0)} {ACC1:slc#71.itm(1)} {ACC1:slc#71.itm(2)} -attr xrf 63874 -attr oid 1064 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#71.itm}
+load net {ACC1:acc#401.itm(0)} -attr vt d
+load net {ACC1:acc#401.itm(1)} -attr vt d
+load net {ACC1:acc#401.itm(2)} -attr vt d
+load net {ACC1:acc#401.itm(3)} -attr vt d
+load netBundle {ACC1:acc#401.itm} 4 {ACC1:acc#401.itm(0)} {ACC1:acc#401.itm(1)} {ACC1:acc#401.itm(2)} {ACC1:acc#401.itm(3)} -attr xrf 63875 -attr oid 1065 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#401.itm}
+load net {conc#1045.itm(0)} -attr vt d
+load net {conc#1045.itm(1)} -attr vt d
+load netBundle {conc#1045.itm} 2 {conc#1045.itm(0)} {conc#1045.itm(1)} -attr xrf 63876 -attr oid 1066 -attr vt d -attr @path {/sobel/sobel:core/conc#1045.itm}
+load net {ACC1:conc#1259.itm(0)} -attr vt d
+load net {ACC1:conc#1259.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1259.itm} 2 {ACC1:conc#1259.itm(0)} {ACC1:conc#1259.itm(1)} -attr xrf 63877 -attr oid 1067 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1259.itm}
+load net {conc#1046.itm(0)} -attr vt d
+load net {conc#1046.itm(1)} -attr vt d
+load net {conc#1046.itm(2)} -attr vt d
+load net {conc#1046.itm(3)} -attr vt d
+load netBundle {conc#1046.itm} 4 {conc#1046.itm(0)} {conc#1046.itm(1)} {conc#1046.itm(2)} {conc#1046.itm(3)} -attr xrf 63878 -attr oid 1068 -attr vt d -attr @path {/sobel/sobel:core/conc#1046.itm}
+load net {ACC1:slc#72.itm(0)} -attr vt d
+load net {ACC1:slc#72.itm(1)} -attr vt d
+load net {ACC1:slc#72.itm(2)} -attr vt d
+load netBundle {ACC1:slc#72.itm} 3 {ACC1:slc#72.itm(0)} {ACC1:slc#72.itm(1)} {ACC1:slc#72.itm(2)} -attr xrf 63879 -attr oid 1069 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#402.itm(0)} -attr vt d
+load net {ACC1:acc#402.itm(1)} -attr vt d
+load net {ACC1:acc#402.itm(2)} -attr vt d
+load net {ACC1:acc#402.itm(3)} -attr vt d
+load netBundle {ACC1:acc#402.itm} 4 {ACC1:acc#402.itm(0)} {ACC1:acc#402.itm(1)} {ACC1:acc#402.itm(2)} {ACC1:acc#402.itm(3)} -attr xrf 63880 -attr oid 1070 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#402.itm}
+load net {conc#1047.itm(0)} -attr vt d
+load net {conc#1047.itm(1)} -attr vt d
+load net {conc#1047.itm(2)} -attr vt d
+load netBundle {conc#1047.itm} 3 {conc#1047.itm(0)} {conc#1047.itm(1)} {conc#1047.itm(2)} -attr xrf 63881 -attr oid 1071 -attr vt d -attr @path {/sobel/sobel:core/conc#1047.itm}
+load net {ACC1:slc#70.itm(0)} -attr vt d
+load net {ACC1:slc#70.itm(1)} -attr vt d
+load netBundle {ACC1:slc#70.itm} 2 {ACC1:slc#70.itm(0)} {ACC1:slc#70.itm(1)} -attr xrf 63882 -attr oid 1072 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#70.itm}
+load net {ACC1:acc#400.itm(0)} -attr vt d
+load net {ACC1:acc#400.itm(1)} -attr vt d
+load net {ACC1:acc#400.itm(2)} -attr vt d
+load netBundle {ACC1:acc#400.itm} 3 {ACC1:acc#400.itm(0)} {ACC1:acc#400.itm(1)} {ACC1:acc#400.itm(2)} -attr xrf 63883 -attr oid 1073 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#400.itm}
+load net {conc#1048.itm(0)} -attr vt d
+load net {conc#1048.itm(1)} -attr vt d
+load netBundle {conc#1048.itm} 2 {conc#1048.itm(0)} {conc#1048.itm(1)} -attr xrf 63884 -attr oid 1074 -attr vt d -attr @path {/sobel/sobel:core/conc#1048.itm}
+load net {ACC1:conc#1257.itm(0)} -attr vt d
+load net {ACC1:conc#1257.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1257.itm} 2 {ACC1:conc#1257.itm(0)} {ACC1:conc#1257.itm(1)} -attr xrf 63885 -attr oid 1075 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1257.itm}
+load net {ACC1:conc#1261.itm(0)} -attr vt d
+load net {ACC1:conc#1261.itm(1)} -attr vt d
+load net {ACC1:conc#1261.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1261.itm} 3 {ACC1:conc#1261.itm(0)} {ACC1:conc#1261.itm(1)} {ACC1:conc#1261.itm(2)} -attr xrf 63886 -attr oid 1076 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1261.itm}
+load net {ACC1:slc#69.itm(0)} -attr vt d
+load net {ACC1:slc#69.itm(1)} -attr vt d
+load netBundle {ACC1:slc#69.itm} 2 {ACC1:slc#69.itm(0)} {ACC1:slc#69.itm(1)} -attr xrf 63887 -attr oid 1077 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#69.itm}
+load net {ACC1:acc#399.itm(0)} -attr vt d
+load net {ACC1:acc#399.itm(1)} -attr vt d
+load net {ACC1:acc#399.itm(2)} -attr vt d
+load netBundle {ACC1:acc#399.itm} 3 {ACC1:acc#399.itm(0)} {ACC1:acc#399.itm(1)} {ACC1:acc#399.itm(2)} -attr xrf 63888 -attr oid 1078 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#399.itm}
+load net {conc#1049.itm(0)} -attr vt d
+load net {conc#1049.itm(1)} -attr vt d
+load netBundle {conc#1049.itm} 2 {conc#1049.itm(0)} {conc#1049.itm(1)} -attr xrf 63889 -attr oid 1079 -attr vt d -attr @path {/sobel/sobel:core/conc#1049.itm}
+load net {ACC1:conc#1255.itm(0)} -attr vt d
+load net {ACC1:conc#1255.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1255.itm} 2 {ACC1:conc#1255.itm(0)} {ACC1:conc#1255.itm(1)} -attr xrf 63890 -attr oid 1080 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1255.itm}
+load net {ACC1:acc#414.itm(0)} -attr vt d
+load net {ACC1:acc#414.itm(1)} -attr vt d
+load net {ACC1:acc#414.itm(2)} -attr vt d
+load net {ACC1:acc#414.itm(3)} -attr vt d
+load netBundle {ACC1:acc#414.itm} 4 {ACC1:acc#414.itm(0)} {ACC1:acc#414.itm(1)} {ACC1:acc#414.itm(2)} {ACC1:acc#414.itm(3)} -attr xrf 63891 -attr oid 1081 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#414.itm}
+load net {conc#1050.itm(0)} -attr vt d
+load net {conc#1050.itm(1)} -attr vt d
+load net {conc#1050.itm(2)} -attr vt d
+load netBundle {conc#1050.itm} 3 {conc#1050.itm(0)} {conc#1050.itm(1)} {conc#1050.itm(2)} -attr xrf 63892 -attr oid 1082 -attr vt d -attr @path {/sobel/sobel:core/conc#1050.itm}
+load net {ACC1-3:not#297.itm(0)} -attr vt d
+load net {ACC1-3:not#297.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#297.itm} 2 {ACC1-3:not#297.itm(0)} {ACC1-3:not#297.itm(1)} -attr xrf 63893 -attr oid 1083 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#297.itm}
+load net {slc(ACC1:acc#222.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#222.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#222.psp.sva).itm} 2 {slc(ACC1:acc#222.psp.sva).itm(0)} {slc(ACC1:acc#222.psp.sva).itm(1)} -attr xrf 63894 -attr oid 1084 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp.sva).itm}
+load net {conc#1051.itm(0)} -attr vt d
+load net {conc#1051.itm(1)} -attr vt d
+load netBundle {conc#1051.itm} 2 {conc#1051.itm(0)} {conc#1051.itm(1)} -attr xrf 63895 -attr oid 1085 -attr vt d -attr @path {/sobel/sobel:core/conc#1051.itm}
+load net {ACC1:acc#377.itm(0)} -attr vt d
+load net {ACC1:acc#377.itm(1)} -attr vt d
+load net {ACC1:acc#377.itm(2)} -attr vt d
+load net {ACC1:acc#377.itm(3)} -attr vt d
+load netBundle {ACC1:acc#377.itm} 4 {ACC1:acc#377.itm(0)} {ACC1:acc#377.itm(1)} {ACC1:acc#377.itm(2)} {ACC1:acc#377.itm(3)} -attr xrf 63896 -attr oid 1086 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#377.itm}
+load net {conc#1052.itm(0)} -attr vt d
+load net {conc#1052.itm(1)} -attr vt d
+load net {conc#1052.itm(2)} -attr vt d
+load netBundle {conc#1052.itm} 3 {conc#1052.itm(0)} {conc#1052.itm(1)} {conc#1052.itm(2)} -attr xrf 63897 -attr oid 1087 -attr vt d -attr @path {/sobel/sobel:core/conc#1052.itm}
+load net {ACC1-2:not#295.itm(0)} -attr vt d
+load net {ACC1-2:not#295.itm(1)} -attr vt d
+load netBundle {ACC1-2:not#295.itm} 2 {ACC1-2:not#295.itm(0)} {ACC1-2:not#295.itm(1)} -attr xrf 63898 -attr oid 1088 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#295.itm}
+load net {slc(ACC1:acc#221.psp#2.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#221.psp#2.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#221.psp#2.sva).itm} 2 {slc(ACC1:acc#221.psp#2.sva).itm(0)} {slc(ACC1:acc#221.psp#2.sva).itm(1)} -attr xrf 63899 -attr oid 1089 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp#2.sva).itm}
+load net {conc#1053.itm(0)} -attr vt d
+load net {conc#1053.itm(1)} -attr vt d
+load netBundle {conc#1053.itm} 2 {conc#1053.itm(0)} {conc#1053.itm(1)} -attr xrf 63900 -attr oid 1090 -attr vt d -attr @path {/sobel/sobel:core/conc#1053.itm}
+load net {ACC1:acc#346.itm(0)} -attr vt d
+load net {ACC1:acc#346.itm(1)} -attr vt d
+load net {ACC1:acc#346.itm(2)} -attr vt d
+load net {ACC1:acc#346.itm(3)} -attr vt d
+load net {ACC1:acc#346.itm(4)} -attr vt d
+load netBundle {ACC1:acc#346.itm} 5 {ACC1:acc#346.itm(0)} {ACC1:acc#346.itm(1)} {ACC1:acc#346.itm(2)} {ACC1:acc#346.itm(3)} {ACC1:acc#346.itm(4)} -attr xrf 63901 -attr oid 1091 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {conc#1054.itm(0)} -attr vt d
+load net {conc#1054.itm(1)} -attr vt d
+load net {conc#1054.itm(2)} -attr vt d
+load net {conc#1054.itm(3)} -attr vt d
+load netBundle {conc#1054.itm} 4 {conc#1054.itm(0)} {conc#1054.itm(1)} {conc#1054.itm(2)} {conc#1054.itm(3)} -attr xrf 63902 -attr oid 1092 -attr vt d -attr @path {/sobel/sobel:core/conc#1054.itm}
+load net {ACC1:slc#24.itm(0)} -attr vt d
+load net {ACC1:slc#24.itm(1)} -attr vt d
+load net {ACC1:slc#24.itm(2)} -attr vt d
+load netBundle {ACC1:slc#24.itm} 3 {ACC1:slc#24.itm(0)} {ACC1:slc#24.itm(1)} {ACC1:slc#24.itm(2)} -attr xrf 63903 -attr oid 1093 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#24.itm}
+load net {ACC1:acc#345.itm(0)} -attr vt d
+load net {ACC1:acc#345.itm(1)} -attr vt d
+load net {ACC1:acc#345.itm(2)} -attr vt d
+load net {ACC1:acc#345.itm(3)} -attr vt d
+load netBundle {ACC1:acc#345.itm} 4 {ACC1:acc#345.itm(0)} {ACC1:acc#345.itm(1)} {ACC1:acc#345.itm(2)} {ACC1:acc#345.itm(3)} -attr xrf 63904 -attr oid 1094 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#345.itm}
+load net {conc#1055.itm(0)} -attr vt d
+load net {conc#1055.itm(1)} -attr vt d
+load net {conc#1055.itm(2)} -attr vt d
+load net {conc#1055.itm(3)} -attr vt d
+load netBundle {conc#1055.itm} 4 {conc#1055.itm(0)} {conc#1055.itm(1)} {conc#1055.itm(2)} {conc#1055.itm(3)} -attr xrf 63905 -attr oid 1095 -attr vt d -attr @path {/sobel/sobel:core/conc#1055.itm}
+load net {ACC1:conc#1153.itm(0)} -attr vt d
+load net {ACC1:conc#1153.itm(1)} -attr vt d
+load net {ACC1:conc#1153.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1153.itm} 3 {ACC1:conc#1153.itm(0)} {ACC1:conc#1153.itm(1)} {ACC1:conc#1153.itm(2)} -attr xrf 63906 -attr oid 1096 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1153.itm}
+load net {ACC1:slc#22.itm(0)} -attr vt d
+load net {ACC1:slc#22.itm(1)} -attr vt d
+load netBundle {ACC1:slc#22.itm} 2 {ACC1:slc#22.itm(0)} {ACC1:slc#22.itm(1)} -attr xrf 63907 -attr oid 1097 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#22.itm}
+load net {ACC1:acc#343.itm(0)} -attr vt d
+load net {ACC1:acc#343.itm(1)} -attr vt d
+load net {ACC1:acc#343.itm(2)} -attr vt d
+load netBundle {ACC1:acc#343.itm} 3 {ACC1:acc#343.itm(0)} {ACC1:acc#343.itm(1)} {ACC1:acc#343.itm(2)} -attr xrf 63908 -attr oid 1098 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#343.itm}
+load net {conc#1056.itm(0)} -attr vt d
+load net {conc#1056.itm(1)} -attr vt d
+load netBundle {conc#1056.itm} 2 {conc#1056.itm(0)} {conc#1056.itm(1)} -attr xrf 63909 -attr oid 1099 -attr vt d -attr @path {/sobel/sobel:core/conc#1056.itm}
+load net {ACC1:conc#1149.itm(0)} -attr vt d
+load net {ACC1:conc#1149.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1149.itm} 2 {ACC1:conc#1149.itm(0)} {ACC1:conc#1149.itm(1)} -attr xrf 63910 -attr oid 1100 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1149.itm}
+load net {ACC1:conc#1155.itm(0)} -attr vt d
+load net {ACC1:conc#1155.itm(1)} -attr vt d
+load net {ACC1:conc#1155.itm(2)} -attr vt d
+load net {ACC1:conc#1155.itm(3)} -attr vt d
+load net {ACC1:conc#1155.itm(4)} -attr vt d
+load netBundle {ACC1:conc#1155.itm} 5 {ACC1:conc#1155.itm(0)} {ACC1:conc#1155.itm(1)} {ACC1:conc#1155.itm(2)} {ACC1:conc#1155.itm(3)} {ACC1:conc#1155.itm(4)} -attr xrf 63911 -attr oid 1101 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1155.itm}
+load net {ACC1:slc#23.itm(0)} -attr vt d
+load net {ACC1:slc#23.itm(1)} -attr vt d
+load net {ACC1:slc#23.itm(2)} -attr vt d
+load net {ACC1:slc#23.itm(3)} -attr vt d
+load netBundle {ACC1:slc#23.itm} 4 {ACC1:slc#23.itm(0)} {ACC1:slc#23.itm(1)} {ACC1:slc#23.itm(2)} {ACC1:slc#23.itm(3)} -attr xrf 63912 -attr oid 1102 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#23.itm}
+load net {ACC1:acc#344.itm(0)} -attr vt d
+load net {ACC1:acc#344.itm(1)} -attr vt d
+load net {ACC1:acc#344.itm(2)} -attr vt d
+load net {ACC1:acc#344.itm(3)} -attr vt d
+load net {ACC1:acc#344.itm(4)} -attr vt d
+load netBundle {ACC1:acc#344.itm} 5 {ACC1:acc#344.itm(0)} {ACC1:acc#344.itm(1)} {ACC1:acc#344.itm(2)} {ACC1:acc#344.itm(3)} {ACC1:acc#344.itm(4)} -attr xrf 63913 -attr oid 1103 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {conc#1057.itm(0)} -attr vt d
+load net {conc#1057.itm(1)} -attr vt d
+load net {conc#1057.itm(2)} -attr vt d
+load netBundle {conc#1057.itm} 3 {conc#1057.itm(0)} {conc#1057.itm(1)} {conc#1057.itm(2)} -attr xrf 63914 -attr oid 1104 -attr vt d -attr @path {/sobel/sobel:core/conc#1057.itm}
+load net {ACC1:slc#21.itm(0)} -attr vt d
+load net {ACC1:slc#21.itm(1)} -attr vt d
+load netBundle {ACC1:slc#21.itm} 2 {ACC1:slc#21.itm(0)} {ACC1:slc#21.itm(1)} -attr xrf 63915 -attr oid 1105 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#21.itm}
+load net {ACC1:acc#342.itm(0)} -attr vt d
+load net {ACC1:acc#342.itm(1)} -attr vt d
+load net {ACC1:acc#342.itm(2)} -attr vt d
+load netBundle {ACC1:acc#342.itm} 3 {ACC1:acc#342.itm(0)} {ACC1:acc#342.itm(1)} {ACC1:acc#342.itm(2)} -attr xrf 63916 -attr oid 1106 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {conc#1058.itm(0)} -attr vt d
+load net {conc#1058.itm(1)} -attr vt d
+load netBundle {conc#1058.itm} 2 {conc#1058.itm(0)} {conc#1058.itm(1)} -attr xrf 63917 -attr oid 1107 -attr vt d -attr @path {/sobel/sobel:core/conc#1058.itm}
+load net {ACC1:conc#1147.itm(0)} -attr vt d
+load net {ACC1:conc#1147.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1147.itm} 2 {ACC1:conc#1147.itm(0)} {ACC1:conc#1147.itm(1)} -attr xrf 63918 -attr oid 1108 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1147.itm}
+load net {ACC1:conc#1151.itm(0)} -attr vt d
+load net {ACC1:conc#1151.itm(1)} -attr vt d
+load net {ACC1:conc#1151.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1151.itm} 3 {ACC1:conc#1151.itm(0)} {ACC1:conc#1151.itm(1)} {ACC1:conc#1151.itm(2)} -attr xrf 63919 -attr oid 1109 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1151.itm}
+load net {ACC1-1:not#252.itm(0)} -attr vt d
+load net {ACC1-1:not#252.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#252.itm} 2 {ACC1-1:not#252.itm(0)} {ACC1-1:not#252.itm(1)} -attr xrf 63920 -attr oid 1110 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#252.itm}
+load net {slc(ACC1:acc#224.psp#1.sva)#12.itm(0)} -attr vt d
+load net {slc(ACC1:acc#224.psp#1.sva)#12.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#224.psp#1.sva)#12.itm} 2 {slc(ACC1:acc#224.psp#1.sva)#12.itm(0)} {slc(ACC1:acc#224.psp#1.sva)#12.itm(1)} -attr xrf 63921 -attr oid 1111 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#12.itm}
+load net {ACC1:acc#386.itm(0)} -attr vt d
+load net {ACC1:acc#386.itm(1)} -attr vt d
+load net {ACC1:acc#386.itm(2)} -attr vt d
+load net {ACC1:acc#386.itm(3)} -attr vt d
+load netBundle {ACC1:acc#386.itm} 4 {ACC1:acc#386.itm(0)} {ACC1:acc#386.itm(1)} {ACC1:acc#386.itm(2)} {ACC1:acc#386.itm(3)} -attr xrf 63922 -attr oid 1112 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#386.itm}
+load net {conc#1059.itm(0)} -attr vt d
+load net {conc#1059.itm(1)} -attr vt d
+load net {conc#1059.itm(2)} -attr vt d
+load netBundle {conc#1059.itm} 3 {conc#1059.itm(0)} {conc#1059.itm(1)} {conc#1059.itm(2)} -attr xrf 63923 -attr oid 1113 -attr vt d -attr @path {/sobel/sobel:core/conc#1059.itm}
+load net {ACC1-2:not#291.itm(0)} -attr vt d
+load net {ACC1-2:not#291.itm(1)} -attr vt d
+load netBundle {ACC1-2:not#291.itm} 2 {ACC1-2:not#291.itm(0)} {ACC1-2:not#291.itm(1)} -attr xrf 63924 -attr oid 1114 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#291.itm}
+load net {slc(ACC1:acc#219.psp#2.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#219.psp#2.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#219.psp#2.sva).itm} 2 {slc(ACC1:acc#219.psp#2.sva).itm(0)} {slc(ACC1:acc#219.psp#2.sva).itm(1)} -attr xrf 63925 -attr oid 1115 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#2.sva).itm}
+load net {conc#1060.itm(0)} -attr vt d
+load net {conc#1060.itm(1)} -attr vt d
+load netBundle {conc#1060.itm} 2 {conc#1060.itm(0)} {conc#1060.itm(1)} -attr xrf 63926 -attr oid 1116 -attr vt d -attr @path {/sobel/sobel:core/conc#1060.itm}
+load net {ACC1:acc#405.itm(0)} -attr vt d
+load net {ACC1:acc#405.itm(1)} -attr vt d
+load net {ACC1:acc#405.itm(2)} -attr vt d
+load net {ACC1:acc#405.itm(3)} -attr vt d
+load netBundle {ACC1:acc#405.itm} 4 {ACC1:acc#405.itm(0)} {ACC1:acc#405.itm(1)} {ACC1:acc#405.itm(2)} {ACC1:acc#405.itm(3)} -attr xrf 63927 -attr oid 1117 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#405.itm}
+load net {conc#1061.itm(0)} -attr vt d
+load net {conc#1061.itm(1)} -attr vt d
+load net {conc#1061.itm(2)} -attr vt d
+load netBundle {conc#1061.itm} 3 {conc#1061.itm(0)} {conc#1061.itm(1)} {conc#1061.itm(2)} -attr xrf 63928 -attr oid 1118 -attr vt d -attr @path {/sobel/sobel:core/conc#1061.itm}
+load net {ACC1-3:not#295.itm(0)} -attr vt d
+load net {ACC1-3:not#295.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#295.itm} 2 {ACC1-3:not#295.itm(0)} {ACC1-3:not#295.itm(1)} -attr xrf 63929 -attr oid 1119 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#295.itm}
+load net {slc(ACC1:acc#221.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#221.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#221.psp.sva).itm} 2 {slc(ACC1:acc#221.psp.sva).itm(0)} {slc(ACC1:acc#221.psp.sva).itm(1)} -attr xrf 63930 -attr oid 1120 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp.sva).itm}
+load net {conc#1062.itm(0)} -attr vt d
+load net {conc#1062.itm(1)} -attr vt d
+load netBundle {conc#1062.itm} 2 {conc#1062.itm(0)} {conc#1062.itm(1)} -attr xrf 63931 -attr oid 1121 -attr vt d -attr @path {/sobel/sobel:core/conc#1062.itm}
+load net {ACC1:slc#74.itm(0)} -attr vt d
+load net {ACC1:slc#74.itm(1)} -attr vt d
+load netBundle {ACC1:slc#74.itm} 2 {ACC1:slc#74.itm(0)} {ACC1:slc#74.itm(1)} -attr xrf 63932 -attr oid 1122 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:acc#404.itm(0)} -attr vt d
+load net {ACC1:acc#404.itm(1)} -attr vt d
+load net {ACC1:acc#404.itm(2)} -attr vt d
+load netBundle {ACC1:acc#404.itm} 3 {ACC1:acc#404.itm(0)} {ACC1:acc#404.itm(1)} {ACC1:acc#404.itm(2)} -attr xrf 63933 -attr oid 1123 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#404.itm}
+load net {conc#1063.itm(0)} -attr vt d
+load net {conc#1063.itm(1)} -attr vt d
+load netBundle {conc#1063.itm} 2 {conc#1063.itm(0)} {conc#1063.itm(1)} -attr xrf 63934 -attr oid 1124 -attr vt d -attr @path {/sobel/sobel:core/conc#1063.itm}
+load net {ACC1:conc#1265.itm(0)} -attr vt d
+load net {ACC1:conc#1265.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1265.itm} 2 {ACC1:conc#1265.itm(0)} {ACC1:conc#1265.itm(1)} -attr xrf 63935 -attr oid 1125 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1265.itm}
+load net {ACC1:slc#50.itm(0)} -attr vt d
+load net {ACC1:slc#50.itm(1)} -attr vt d
+load netBundle {ACC1:slc#50.itm} 2 {ACC1:slc#50.itm(0)} {ACC1:slc#50.itm(1)} -attr xrf 63936 -attr oid 1126 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#376.itm(0)} -attr vt d
+load net {ACC1:acc#376.itm(1)} -attr vt d
+load net {ACC1:acc#376.itm(2)} -attr vt d
+load netBundle {ACC1:acc#376.itm} 3 {ACC1:acc#376.itm(0)} {ACC1:acc#376.itm(1)} {ACC1:acc#376.itm(2)} -attr xrf 63937 -attr oid 1127 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#376.itm}
+load net {conc#1064.itm(0)} -attr vt d
+load net {conc#1064.itm(1)} -attr vt d
+load netBundle {conc#1064.itm} 2 {conc#1064.itm(0)} {conc#1064.itm(1)} -attr xrf 63938 -attr oid 1128 -attr vt d -attr @path {/sobel/sobel:core/conc#1064.itm}
+load net {ACC1:conc#1211.itm(0)} -attr vt d
+load net {ACC1:conc#1211.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1211.itm} 2 {ACC1:conc#1211.itm(0)} {ACC1:conc#1211.itm(1)} -attr xrf 63939 -attr oid 1129 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1211.itm}
+load net {ACC1:slc#58.itm(0)} -attr vt d
+load net {ACC1:slc#58.itm(1)} -attr vt d
+load netBundle {ACC1:slc#58.itm} 2 {ACC1:slc#58.itm(0)} {ACC1:slc#58.itm(1)} -attr xrf 63940 -attr oid 1130 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:acc#385.itm(0)} -attr vt d
+load net {ACC1:acc#385.itm(1)} -attr vt d
+load net {ACC1:acc#385.itm(2)} -attr vt d
+load netBundle {ACC1:acc#385.itm} 3 {ACC1:acc#385.itm(0)} {ACC1:acc#385.itm(1)} {ACC1:acc#385.itm(2)} -attr xrf 63941 -attr oid 1131 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#385.itm}
+load net {conc#1065.itm(0)} -attr vt d
+load net {conc#1065.itm(1)} -attr vt d
+load netBundle {conc#1065.itm} 2 {conc#1065.itm(0)} {conc#1065.itm(1)} -attr xrf 63942 -attr oid 1132 -attr vt d -attr @path {/sobel/sobel:core/conc#1065.itm}
+load net {ACC1:conc#1229.itm(0)} -attr vt d
+load net {ACC1:conc#1229.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1229.itm} 2 {ACC1:conc#1229.itm(0)} {ACC1:conc#1229.itm(1)} -attr xrf 63943 -attr oid 1133 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1229.itm}
+load net {ACC1:slc#26.itm(0)} -attr vt d
+load net {ACC1:slc#26.itm(1)} -attr vt d
+load netBundle {ACC1:slc#26.itm} 2 {ACC1:slc#26.itm(0)} {ACC1:slc#26.itm(1)} -attr xrf 63944 -attr oid 1134 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#347.itm(0)} -attr vt d
+load net {ACC1:acc#347.itm(1)} -attr vt d
+load net {ACC1:acc#347.itm(2)} -attr vt d
+load netBundle {ACC1:acc#347.itm} 3 {ACC1:acc#347.itm(0)} {ACC1:acc#347.itm(1)} {ACC1:acc#347.itm(2)} -attr xrf 63945 -attr oid 1135 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load net {conc#1066.itm(0)} -attr vt d
+load net {conc#1066.itm(1)} -attr vt d
+load netBundle {conc#1066.itm} 2 {conc#1066.itm(0)} {conc#1066.itm(1)} -attr xrf 63946 -attr oid 1136 -attr vt d -attr @path {/sobel/sobel:core/conc#1066.itm}
+load net {ACC1:conc#1157.itm(0)} -attr vt d
+load net {ACC1:conc#1157.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1157.itm} 2 {ACC1:conc#1157.itm(0)} {ACC1:conc#1157.itm(1)} -attr xrf 63947 -attr oid 1137 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1157.itm}
+load net {ACC1:slc#42.itm(0)} -attr vt d
+load net {ACC1:slc#42.itm(1)} -attr vt d
+load netBundle {ACC1:slc#42.itm} 2 {ACC1:slc#42.itm(0)} {ACC1:slc#42.itm(1)} -attr xrf 63948 -attr oid 1138 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#42.itm}
+load net {ACC1:acc#366.itm(0)} -attr vt d
+load net {ACC1:acc#366.itm(1)} -attr vt d
+load net {ACC1:acc#366.itm(2)} -attr vt d
+load netBundle {ACC1:acc#366.itm} 3 {ACC1:acc#366.itm(0)} {ACC1:acc#366.itm(1)} {ACC1:acc#366.itm(2)} -attr xrf 63949 -attr oid 1139 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#366.itm}
+load net {conc#1067.itm(0)} -attr vt d
+load net {conc#1067.itm(1)} -attr vt d
+load netBundle {conc#1067.itm} 2 {conc#1067.itm(0)} {conc#1067.itm(1)} -attr xrf 63950 -attr oid 1140 -attr vt d -attr @path {/sobel/sobel:core/conc#1067.itm}
+load net {ACC1:conc#1193.itm(0)} -attr vt d
+load net {ACC1:conc#1193.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1193.itm} 2 {ACC1:conc#1193.itm(0)} {ACC1:conc#1193.itm(1)} -attr xrf 63951 -attr oid 1141 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1193.itm}
+load net {ACC1:acc#387.itm(0)} -attr vt d
+load net {ACC1:acc#387.itm(1)} -attr vt d
+load net {ACC1:acc#387.itm(2)} -attr vt d
+load netBundle {ACC1:acc#387.itm} 3 {ACC1:acc#387.itm(0)} {ACC1:acc#387.itm(1)} {ACC1:acc#387.itm(2)} -attr xrf 63952 -attr oid 1142 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#387.itm}
+load net {conc#1068.itm(0)} -attr vt d
+load net {conc#1068.itm(1)} -attr vt d
+load net {conc#1068.itm(2)} -attr vt d
+load netBundle {conc#1068.itm} 3 {conc#1068.itm(0)} {conc#1068.itm(1)} {conc#1068.itm(2)} -attr xrf 63953 -attr oid 1143 -attr vt d -attr @path {/sobel/sobel:core/conc#1068.itm}
+load net {ACC1:conc#1234.itm(0)} -attr vt d
+load net {ACC1:conc#1234.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1234.itm} 2 {ACC1:conc#1234.itm(0)} {ACC1:conc#1234.itm(1)} -attr xrf 63954 -attr oid 1144 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1234.itm}
+load net {ACC1:acc#378.itm(0)} -attr vt d
+load net {ACC1:acc#378.itm(1)} -attr vt d
+load net {ACC1:acc#378.itm(2)} -attr vt d
+load netBundle {ACC1:acc#378.itm} 3 {ACC1:acc#378.itm(0)} {ACC1:acc#378.itm(1)} {ACC1:acc#378.itm(2)} -attr xrf 63955 -attr oid 1145 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#378.itm}
+load net {conc#1069.itm(0)} -attr vt d
+load net {conc#1069.itm(1)} -attr vt d
+load net {conc#1069.itm(2)} -attr vt d
+load netBundle {conc#1069.itm} 3 {conc#1069.itm(0)} {conc#1069.itm(1)} {conc#1069.itm(2)} -attr xrf 63956 -attr oid 1146 -attr vt d -attr @path {/sobel/sobel:core/conc#1069.itm}
+load net {ACC1:conc#1216.itm(0)} -attr vt d
+load net {ACC1:conc#1216.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1216.itm} 2 {ACC1:conc#1216.itm(0)} {ACC1:conc#1216.itm(1)} -attr xrf 63957 -attr oid 1147 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1216.itm}
+load net {ACC1:acc#415.itm(0)} -attr vt d
+load net {ACC1:acc#415.itm(1)} -attr vt d
+load net {ACC1:acc#415.itm(2)} -attr vt d
+load netBundle {ACC1:acc#415.itm} 3 {ACC1:acc#415.itm(0)} {ACC1:acc#415.itm(1)} {ACC1:acc#415.itm(2)} -attr xrf 63958 -attr oid 1148 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#415.itm}
+load net {conc#1070.itm(0)} -attr vt d
+load net {conc#1070.itm(1)} -attr vt d
+load net {conc#1070.itm(2)} -attr vt d
+load netBundle {conc#1070.itm} 3 {conc#1070.itm(0)} {conc#1070.itm(1)} {conc#1070.itm(2)} -attr xrf 63959 -attr oid 1149 -attr vt d -attr @path {/sobel/sobel:core/conc#1070.itm}
+load net {ACC1:conc#1288.itm(0)} -attr vt d
+load net {ACC1:conc#1288.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1288.itm} 2 {ACC1:conc#1288.itm(0)} {ACC1:conc#1288.itm(1)} -attr xrf 63960 -attr oid 1150 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1288.itm}
+load net {ACC1:acc#396.itm(0)} -attr vt d
+load net {ACC1:acc#396.itm(1)} -attr vt d
+load net {ACC1:acc#396.itm(2)} -attr vt d
+load netBundle {ACC1:acc#396.itm} 3 {ACC1:acc#396.itm(0)} {ACC1:acc#396.itm(1)} {ACC1:acc#396.itm(2)} -attr xrf 63961 -attr oid 1151 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#396.itm}
+load net {conc#1071.itm(0)} -attr vt d
+load net {conc#1071.itm(1)} -attr vt d
+load net {conc#1071.itm(2)} -attr vt d
+load netBundle {conc#1071.itm} 3 {conc#1071.itm(0)} {conc#1071.itm(1)} {conc#1071.itm(2)} -attr xrf 63962 -attr oid 1152 -attr vt d -attr @path {/sobel/sobel:core/conc#1071.itm}
+load net {ACC1:conc#1252.itm(0)} -attr vt d
+load net {ACC1:conc#1252.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1252.itm} 2 {ACC1:conc#1252.itm(0)} {ACC1:conc#1252.itm(1)} -attr xrf 63963 -attr oid 1153 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1252.itm}
+load net {ACC1:slc#65.itm(0)} -attr vt d
+load net {ACC1:slc#65.itm(1)} -attr vt d
+load net {ACC1:slc#65.itm(2)} -attr vt d
+load net {ACC1:slc#65.itm(3)} -attr vt d
+load netBundle {ACC1:slc#65.itm} 4 {ACC1:slc#65.itm(0)} {ACC1:slc#65.itm(1)} {ACC1:slc#65.itm(2)} {ACC1:slc#65.itm(3)} -attr xrf 63964 -attr oid 1154 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#393.itm(0)} -attr vt d
+load net {ACC1:acc#393.itm(1)} -attr vt d
+load net {ACC1:acc#393.itm(2)} -attr vt d
+load net {ACC1:acc#393.itm(3)} -attr vt d
+load net {ACC1:acc#393.itm(4)} -attr vt d
+load netBundle {ACC1:acc#393.itm} 5 {ACC1:acc#393.itm(0)} {ACC1:acc#393.itm(1)} {ACC1:acc#393.itm(2)} {ACC1:acc#393.itm(3)} {ACC1:acc#393.itm(4)} -attr xrf 63965 -attr oid 1155 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393.itm}
+load net {conc#1072.itm(0)} -attr vt d
+load net {conc#1072.itm(1)} -attr vt d
+load net {conc#1072.itm(2)} -attr vt d
+load net {conc#1072.itm(3)} -attr vt d
+load netBundle {conc#1072.itm} 4 {conc#1072.itm(0)} {conc#1072.itm(1)} {conc#1072.itm(2)} {conc#1072.itm(3)} -attr xrf 63966 -attr oid 1156 -attr vt d -attr @path {/sobel/sobel:core/conc#1072.itm}
+load net {ACC1:slc#63.itm(0)} -attr vt d
+load net {ACC1:slc#63.itm(1)} -attr vt d
+load net {ACC1:slc#63.itm(2)} -attr vt d
+load netBundle {ACC1:slc#63.itm} 3 {ACC1:slc#63.itm(0)} {ACC1:slc#63.itm(1)} {ACC1:slc#63.itm(2)} -attr xrf 63967 -attr oid 1157 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#63.itm}
+load net {ACC1:acc#391.itm(0)} -attr vt d
+load net {ACC1:acc#391.itm(1)} -attr vt d
+load net {ACC1:acc#391.itm(2)} -attr vt d
+load net {ACC1:acc#391.itm(3)} -attr vt d
+load netBundle {ACC1:acc#391.itm} 4 {ACC1:acc#391.itm(0)} {ACC1:acc#391.itm(1)} {ACC1:acc#391.itm(2)} {ACC1:acc#391.itm(3)} -attr xrf 63968 -attr oid 1158 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#391.itm}
+load net {conc#1073.itm(0)} -attr vt d
+load net {conc#1073.itm(1)} -attr vt d
+load netBundle {conc#1073.itm} 2 {conc#1073.itm(0)} {conc#1073.itm(1)} -attr xrf 63969 -attr oid 1159 -attr vt d -attr @path {/sobel/sobel:core/conc#1073.itm}
+load net {ACC1:conc#1241.itm(0)} -attr vt d
+load net {ACC1:conc#1241.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1241.itm} 2 {ACC1:conc#1241.itm(0)} {ACC1:conc#1241.itm(1)} -attr xrf 63970 -attr oid 1160 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1241.itm}
+load net {conc#1074.itm(0)} -attr vt d
+load net {conc#1074.itm(1)} -attr vt d
+load net {conc#1074.itm(2)} -attr vt d
+load net {conc#1074.itm(3)} -attr vt d
+load netBundle {conc#1074.itm} 4 {conc#1074.itm(0)} {conc#1074.itm(1)} {conc#1074.itm(2)} {conc#1074.itm(3)} -attr xrf 63971 -attr oid 1161 -attr vt d -attr @path {/sobel/sobel:core/conc#1074.itm}
+load net {ACC1:slc#64.itm(0)} -attr vt d
+load net {ACC1:slc#64.itm(1)} -attr vt d
+load net {ACC1:slc#64.itm(2)} -attr vt d
+load netBundle {ACC1:slc#64.itm} 3 {ACC1:slc#64.itm(0)} {ACC1:slc#64.itm(1)} {ACC1:slc#64.itm(2)} -attr xrf 63972 -attr oid 1162 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#392.itm(0)} -attr vt d
+load net {ACC1:acc#392.itm(1)} -attr vt d
+load net {ACC1:acc#392.itm(2)} -attr vt d
+load net {ACC1:acc#392.itm(3)} -attr vt d
+load netBundle {ACC1:acc#392.itm} 4 {ACC1:acc#392.itm(0)} {ACC1:acc#392.itm(1)} {ACC1:acc#392.itm(2)} {ACC1:acc#392.itm(3)} -attr xrf 63973 -attr oid 1163 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#392.itm}
+load net {conc#1075.itm(0)} -attr vt d
+load net {conc#1075.itm(1)} -attr vt d
+load net {conc#1075.itm(2)} -attr vt d
+load netBundle {conc#1075.itm} 3 {conc#1075.itm(0)} {conc#1075.itm(1)} {conc#1075.itm(2)} -attr xrf 63974 -attr oid 1164 -attr vt d -attr @path {/sobel/sobel:core/conc#1075.itm}
+load net {ACC1:slc#62.itm(0)} -attr vt d
+load net {ACC1:slc#62.itm(1)} -attr vt d
+load netBundle {ACC1:slc#62.itm} 2 {ACC1:slc#62.itm(0)} {ACC1:slc#62.itm(1)} -attr xrf 63975 -attr oid 1165 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#62.itm}
+load net {ACC1:acc#390.itm(0)} -attr vt d
+load net {ACC1:acc#390.itm(1)} -attr vt d
+load net {ACC1:acc#390.itm(2)} -attr vt d
+load netBundle {ACC1:acc#390.itm} 3 {ACC1:acc#390.itm(0)} {ACC1:acc#390.itm(1)} {ACC1:acc#390.itm(2)} -attr xrf 63976 -attr oid 1166 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#390.itm}
+load net {conc#1076.itm(0)} -attr vt d
+load net {conc#1076.itm(1)} -attr vt d
+load netBundle {conc#1076.itm} 2 {conc#1076.itm(0)} {conc#1076.itm(1)} -attr xrf 63977 -attr oid 1167 -attr vt d -attr @path {/sobel/sobel:core/conc#1076.itm}
+load net {ACC1:conc#1239.itm(0)} -attr vt d
+load net {ACC1:conc#1239.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1239.itm} 2 {ACC1:conc#1239.itm(0)} {ACC1:conc#1239.itm(1)} -attr xrf 63978 -attr oid 1168 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1239.itm}
+load net {ACC1:conc#1243.itm(0)} -attr vt d
+load net {ACC1:conc#1243.itm(1)} -attr vt d
+load net {ACC1:conc#1243.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1243.itm} 3 {ACC1:conc#1243.itm(0)} {ACC1:conc#1243.itm(1)} {ACC1:conc#1243.itm(2)} -attr xrf 63979 -attr oid 1169 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1243.itm}
+load net {ACC1:slc#61.itm(0)} -attr vt d
+load net {ACC1:slc#61.itm(1)} -attr vt d
+load netBundle {ACC1:slc#61.itm} 2 {ACC1:slc#61.itm(0)} {ACC1:slc#61.itm(1)} -attr xrf 63980 -attr oid 1170 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#61.itm}
+load net {ACC1:acc#389.itm(0)} -attr vt d
+load net {ACC1:acc#389.itm(1)} -attr vt d
+load net {ACC1:acc#389.itm(2)} -attr vt d
+load netBundle {ACC1:acc#389.itm} 3 {ACC1:acc#389.itm(0)} {ACC1:acc#389.itm(1)} {ACC1:acc#389.itm(2)} -attr xrf 63981 -attr oid 1171 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#389.itm}
+load net {conc#1077.itm(0)} -attr vt d
+load net {conc#1077.itm(1)} -attr vt d
+load netBundle {conc#1077.itm} 2 {conc#1077.itm(0)} {conc#1077.itm(1)} -attr xrf 63982 -attr oid 1172 -attr vt d -attr @path {/sobel/sobel:core/conc#1077.itm}
+load net {ACC1:conc#1237.itm(0)} -attr vt d
+load net {ACC1:conc#1237.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1237.itm} 2 {ACC1:conc#1237.itm(0)} {ACC1:conc#1237.itm(1)} -attr xrf 63983 -attr oid 1173 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1237.itm}
+load net {ACC1:slc#89.itm(0)} -attr vt d
+load net {ACC1:slc#89.itm(1)} -attr vt d
+load net {ACC1:slc#89.itm(2)} -attr vt d
+load net {ACC1:slc#89.itm(3)} -attr vt d
+load netBundle {ACC1:slc#89.itm} 4 {ACC1:slc#89.itm(0)} {ACC1:slc#89.itm(1)} {ACC1:slc#89.itm(2)} {ACC1:slc#89.itm(3)} -attr xrf 63984 -attr oid 1174 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#421.itm(0)} -attr vt d
+load net {ACC1:acc#421.itm(1)} -attr vt d
+load net {ACC1:acc#421.itm(2)} -attr vt d
+load net {ACC1:acc#421.itm(3)} -attr vt d
+load net {ACC1:acc#421.itm(4)} -attr vt d
+load netBundle {ACC1:acc#421.itm} 5 {ACC1:acc#421.itm(0)} {ACC1:acc#421.itm(1)} {ACC1:acc#421.itm(2)} {ACC1:acc#421.itm(3)} {ACC1:acc#421.itm(4)} -attr xrf 63985 -attr oid 1175 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421.itm}
+load net {conc#1078.itm(0)} -attr vt d
+load net {conc#1078.itm(1)} -attr vt d
+load net {conc#1078.itm(2)} -attr vt d
+load net {conc#1078.itm(3)} -attr vt d
+load netBundle {conc#1078.itm} 4 {conc#1078.itm(0)} {conc#1078.itm(1)} {conc#1078.itm(2)} {conc#1078.itm(3)} -attr xrf 63986 -attr oid 1176 -attr vt d -attr @path {/sobel/sobel:core/conc#1078.itm}
+load net {ACC1:slc#87.itm(0)} -attr vt d
+load net {ACC1:slc#87.itm(1)} -attr vt d
+load net {ACC1:slc#87.itm(2)} -attr vt d
+load netBundle {ACC1:slc#87.itm} 3 {ACC1:slc#87.itm(0)} {ACC1:slc#87.itm(1)} {ACC1:slc#87.itm(2)} -attr xrf 63987 -attr oid 1177 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#87.itm}
+load net {ACC1:acc#419.itm(0)} -attr vt d
+load net {ACC1:acc#419.itm(1)} -attr vt d
+load net {ACC1:acc#419.itm(2)} -attr vt d
+load net {ACC1:acc#419.itm(3)} -attr vt d
+load netBundle {ACC1:acc#419.itm} 4 {ACC1:acc#419.itm(0)} {ACC1:acc#419.itm(1)} {ACC1:acc#419.itm(2)} {ACC1:acc#419.itm(3)} -attr xrf 63988 -attr oid 1178 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#419.itm}
+load net {conc#1079.itm(0)} -attr vt d
+load net {conc#1079.itm(1)} -attr vt d
+load netBundle {conc#1079.itm} 2 {conc#1079.itm(0)} {conc#1079.itm(1)} -attr xrf 63989 -attr oid 1179 -attr vt d -attr @path {/sobel/sobel:core/conc#1079.itm}
+load net {ACC1:conc#1295.itm(0)} -attr vt d
+load net {ACC1:conc#1295.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1295.itm} 2 {ACC1:conc#1295.itm(0)} {ACC1:conc#1295.itm(1)} -attr xrf 63990 -attr oid 1180 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1295.itm}
+load net {conc#1080.itm(0)} -attr vt d
+load net {conc#1080.itm(1)} -attr vt d
+load net {conc#1080.itm(2)} -attr vt d
+load net {conc#1080.itm(3)} -attr vt d
+load netBundle {conc#1080.itm} 4 {conc#1080.itm(0)} {conc#1080.itm(1)} {conc#1080.itm(2)} {conc#1080.itm(3)} -attr xrf 63991 -attr oid 1181 -attr vt d -attr @path {/sobel/sobel:core/conc#1080.itm}
+load net {ACC1:slc#88.itm(0)} -attr vt d
+load net {ACC1:slc#88.itm(1)} -attr vt d
+load net {ACC1:slc#88.itm(2)} -attr vt d
+load netBundle {ACC1:slc#88.itm} 3 {ACC1:slc#88.itm(0)} {ACC1:slc#88.itm(1)} {ACC1:slc#88.itm(2)} -attr xrf 63992 -attr oid 1182 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#420.itm(0)} -attr vt d
+load net {ACC1:acc#420.itm(1)} -attr vt d
+load net {ACC1:acc#420.itm(2)} -attr vt d
+load net {ACC1:acc#420.itm(3)} -attr vt d
+load netBundle {ACC1:acc#420.itm} 4 {ACC1:acc#420.itm(0)} {ACC1:acc#420.itm(1)} {ACC1:acc#420.itm(2)} {ACC1:acc#420.itm(3)} -attr xrf 63993 -attr oid 1183 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#420.itm}
+load net {conc#1081.itm(0)} -attr vt d
+load net {conc#1081.itm(1)} -attr vt d
+load net {conc#1081.itm(2)} -attr vt d
+load netBundle {conc#1081.itm} 3 {conc#1081.itm(0)} {conc#1081.itm(1)} {conc#1081.itm(2)} -attr xrf 63994 -attr oid 1184 -attr vt d -attr @path {/sobel/sobel:core/conc#1081.itm}
+load net {ACC1:slc#86.itm(0)} -attr vt d
+load net {ACC1:slc#86.itm(1)} -attr vt d
+load netBundle {ACC1:slc#86.itm} 2 {ACC1:slc#86.itm(0)} {ACC1:slc#86.itm(1)} -attr xrf 63995 -attr oid 1185 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#86.itm}
+load net {ACC1:acc#418.itm(0)} -attr vt d
+load net {ACC1:acc#418.itm(1)} -attr vt d
+load net {ACC1:acc#418.itm(2)} -attr vt d
+load netBundle {ACC1:acc#418.itm} 3 {ACC1:acc#418.itm(0)} {ACC1:acc#418.itm(1)} {ACC1:acc#418.itm(2)} -attr xrf 63996 -attr oid 1186 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#418.itm}
+load net {conc#1082.itm(0)} -attr vt d
+load net {conc#1082.itm(1)} -attr vt d
+load netBundle {conc#1082.itm} 2 {conc#1082.itm(0)} {conc#1082.itm(1)} -attr xrf 63997 -attr oid 1187 -attr vt d -attr @path {/sobel/sobel:core/conc#1082.itm}
+load net {ACC1:conc#1293.itm(0)} -attr vt d
+load net {ACC1:conc#1293.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1293.itm} 2 {ACC1:conc#1293.itm(0)} {ACC1:conc#1293.itm(1)} -attr xrf 63998 -attr oid 1188 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1293.itm}
+load net {ACC1:conc#1297.itm(0)} -attr vt d
+load net {ACC1:conc#1297.itm(1)} -attr vt d
+load net {ACC1:conc#1297.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1297.itm} 3 {ACC1:conc#1297.itm(0)} {ACC1:conc#1297.itm(1)} {ACC1:conc#1297.itm(2)} -attr xrf 63999 -attr oid 1189 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1297.itm}
+load net {ACC1:slc#85.itm(0)} -attr vt d
+load net {ACC1:slc#85.itm(1)} -attr vt d
+load netBundle {ACC1:slc#85.itm} 2 {ACC1:slc#85.itm(0)} {ACC1:slc#85.itm(1)} -attr xrf 64000 -attr oid 1190 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#85.itm}
+load net {ACC1:acc#417.itm(0)} -attr vt d
+load net {ACC1:acc#417.itm(1)} -attr vt d
+load net {ACC1:acc#417.itm(2)} -attr vt d
+load netBundle {ACC1:acc#417.itm} 3 {ACC1:acc#417.itm(0)} {ACC1:acc#417.itm(1)} {ACC1:acc#417.itm(2)} -attr xrf 64001 -attr oid 1191 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#417.itm}
+load net {conc#1083.itm(0)} -attr vt d
+load net {conc#1083.itm(1)} -attr vt d
+load netBundle {conc#1083.itm} 2 {conc#1083.itm(0)} {conc#1083.itm(1)} -attr xrf 64002 -attr oid 1192 -attr vt d -attr @path {/sobel/sobel:core/conc#1083.itm}
+load net {ACC1:conc#1291.itm(0)} -attr vt d
+load net {ACC1:conc#1291.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1291.itm} 2 {ACC1:conc#1291.itm(0)} {ACC1:conc#1291.itm(1)} -attr xrf 64003 -attr oid 1193 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1291.itm}
+load net {ACC1:acc#424.itm(0)} -attr vt d
+load net {ACC1:acc#424.itm(1)} -attr vt d
+load net {ACC1:acc#424.itm(2)} -attr vt d
+load netBundle {ACC1:acc#424.itm} 3 {ACC1:acc#424.itm(0)} {ACC1:acc#424.itm(1)} {ACC1:acc#424.itm(2)} -attr xrf 64004 -attr oid 1194 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#424.itm}
+load net {conc#1084.itm(0)} -attr vt d
+load net {conc#1084.itm(1)} -attr vt d
+load net {conc#1084.itm(2)} -attr vt d
+load netBundle {conc#1084.itm} 3 {conc#1084.itm(0)} {conc#1084.itm(1)} {conc#1084.itm(2)} -attr xrf 64005 -attr oid 1195 -attr vt d -attr @path {/sobel/sobel:core/conc#1084.itm}
+load net {ACC1:conc#1306.itm(0)} -attr vt d
+load net {ACC1:conc#1306.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1306.itm} 2 {ACC1:conc#1306.itm(0)} {ACC1:conc#1306.itm(1)} -attr xrf 64006 -attr oid 1196 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1306.itm}
+load net {ACC1:exs#1650.itm(0)} -attr vt d
+load net {ACC1:exs#1650.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1650.itm} 2 {ACC1:exs#1650.itm(0)} {ACC1:exs#1650.itm(1)} -attr xrf 64007 -attr oid 1197 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1650.itm}
+load net {ACC1:exs#1607.itm(0)} -attr vt d
+load net {ACC1:exs#1607.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1607.itm} 2 {ACC1:exs#1607.itm(0)} {ACC1:exs#1607.itm(1)} -attr xrf 64008 -attr oid 1198 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1607.itm}
+load net {ACC1:acc#318.itm(0)} -attr vt d
+load net {ACC1:acc#318.itm(1)} -attr vt d
+load netBundle {ACC1:acc#318.itm} 2 {ACC1:acc#318.itm(0)} {ACC1:acc#318.itm(1)} -attr xrf 64009 -attr oid 1199 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#319.itm(0)} -attr vt d
+load net {ACC1:acc#319.itm(1)} -attr vt d
+load netBundle {ACC1:acc#319.itm} 2 {ACC1:acc#319.itm(0)} {ACC1:acc#319.itm(1)} -attr xrf 64010 -attr oid 1200 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:slc#90.itm(0)} -attr vt d
+load net {ACC1:slc#90.itm(1)} -attr vt d
+load netBundle {ACC1:slc#90.itm} 2 {ACC1:slc#90.itm(0)} {ACC1:slc#90.itm(1)} -attr xrf 64011 -attr oid 1201 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1:acc#422.itm(0)} -attr vt d
+load net {ACC1:acc#422.itm(1)} -attr vt d
+load net {ACC1:acc#422.itm(2)} -attr vt d
+load netBundle {ACC1:acc#422.itm} 3 {ACC1:acc#422.itm(0)} {ACC1:acc#422.itm(1)} {ACC1:acc#422.itm(2)} -attr xrf 64012 -attr oid 1202 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#422.itm}
+load net {conc#1085.itm(0)} -attr vt d
+load net {conc#1085.itm(1)} -attr vt d
+load netBundle {conc#1085.itm} 2 {conc#1085.itm(0)} {conc#1085.itm(1)} -attr xrf 64013 -attr oid 1203 -attr vt d -attr @path {/sobel/sobel:core/conc#1085.itm}
+load net {ACC1:conc#1301.itm(0)} -attr vt d
+load net {ACC1:conc#1301.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1301.itm} 2 {ACC1:conc#1301.itm(0)} {ACC1:conc#1301.itm(1)} -attr xrf 64014 -attr oid 1204 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1301.itm}
+load net {ACC1:slc#18.itm(0)} -attr vt d
+load net {ACC1:slc#18.itm(1)} -attr vt d
+load netBundle {ACC1:slc#18.itm} 2 {ACC1:slc#18.itm(0)} {ACC1:slc#18.itm(1)} -attr xrf 64015 -attr oid 1205 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#18.itm}
+load net {ACC1:acc#337.itm(0)} -attr vt d
+load net {ACC1:acc#337.itm(1)} -attr vt d
+load net {ACC1:acc#337.itm(2)} -attr vt d
+load netBundle {ACC1:acc#337.itm} 3 {ACC1:acc#337.itm(0)} {ACC1:acc#337.itm(1)} {ACC1:acc#337.itm(2)} -attr xrf 64016 -attr oid 1206 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {conc#1086.itm(0)} -attr vt d
+load net {conc#1086.itm(1)} -attr vt d
+load netBundle {conc#1086.itm} 2 {conc#1086.itm(0)} {conc#1086.itm(1)} -attr xrf 64017 -attr oid 1207 -attr vt d -attr @path {/sobel/sobel:core/conc#1086.itm}
+load net {ACC1:conc#1139.itm(0)} -attr vt d
+load net {ACC1:conc#1139.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1139.itm} 2 {ACC1:conc#1139.itm(0)} {ACC1:conc#1139.itm(1)} -attr xrf 64018 -attr oid 1208 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1139.itm}
+load net {ACC1:slc#66.itm(0)} -attr vt d
+load net {ACC1:slc#66.itm(1)} -attr vt d
+load netBundle {ACC1:slc#66.itm} 2 {ACC1:slc#66.itm(0)} {ACC1:slc#66.itm(1)} -attr xrf 64019 -attr oid 1209 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1:acc#394.itm(0)} -attr vt d
+load net {ACC1:acc#394.itm(1)} -attr vt d
+load net {ACC1:acc#394.itm(2)} -attr vt d
+load netBundle {ACC1:acc#394.itm} 3 {ACC1:acc#394.itm(0)} {ACC1:acc#394.itm(1)} {ACC1:acc#394.itm(2)} -attr xrf 64020 -attr oid 1210 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#394.itm}
+load net {conc#1087.itm(0)} -attr vt d
+load net {conc#1087.itm(1)} -attr vt d
+load netBundle {conc#1087.itm} 2 {conc#1087.itm(0)} {conc#1087.itm(1)} -attr xrf 64021 -attr oid 1211 -attr vt d -attr @path {/sobel/sobel:core/conc#1087.itm}
+load net {ACC1:conc#1247.itm(0)} -attr vt d
+load net {ACC1:conc#1247.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1247.itm} 2 {ACC1:conc#1247.itm(0)} {ACC1:conc#1247.itm(1)} -attr xrf 64022 -attr oid 1212 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1247.itm}
+load net {ACC1:slc#82.itm(0)} -attr vt d
+load net {ACC1:slc#82.itm(1)} -attr vt d
+load netBundle {ACC1:slc#82.itm} 2 {ACC1:slc#82.itm(0)} {ACC1:slc#82.itm(1)} -attr xrf 64023 -attr oid 1213 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#82.itm}
+load net {ACC1:acc#413.itm(0)} -attr vt d
+load net {ACC1:acc#413.itm(1)} -attr vt d
+load net {ACC1:acc#413.itm(2)} -attr vt d
+load netBundle {ACC1:acc#413.itm} 3 {ACC1:acc#413.itm(0)} {ACC1:acc#413.itm(1)} {ACC1:acc#413.itm(2)} -attr xrf 64024 -attr oid 1214 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#413.itm}
+load net {conc#1088.itm(0)} -attr vt d
+load net {conc#1088.itm(1)} -attr vt d
+load netBundle {conc#1088.itm} 2 {conc#1088.itm(0)} {conc#1088.itm(1)} -attr xrf 64025 -attr oid 1215 -attr vt d -attr @path {/sobel/sobel:core/conc#1088.itm}
+load net {ACC1:conc#1283.itm(0)} -attr vt d
+load net {ACC1:conc#1283.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1283.itm} 2 {ACC1:conc#1283.itm(0)} {ACC1:conc#1283.itm(1)} -attr xrf 64026 -attr oid 1216 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1283.itm}
+load net {ACC1:exs#1641.itm(0)} -attr vt d
+load net {ACC1:exs#1641.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1641.itm} 2 {ACC1:exs#1641.itm(0)} {ACC1:exs#1641.itm(1)} -attr xrf 64027 -attr oid 1217 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1641.itm}
+load net {ACC1:exs#1599.itm(0)} -attr vt d
+load net {ACC1:exs#1599.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1599.itm} 2 {ACC1:exs#1599.itm(0)} {ACC1:exs#1599.itm(1)} -attr xrf 64028 -attr oid 1218 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1599.itm}
+load net {ACC1:acc#351.itm(0)} -attr vt d
+load net {ACC1:acc#351.itm(1)} -attr vt d
+load net {ACC1:acc#351.itm(2)} -attr vt d
+load net {ACC1:acc#351.itm(3)} -attr vt d
+load net {ACC1:acc#351.itm(4)} -attr vt d
+load net {ACC1:acc#351.itm(5)} -attr vt d
+load net {ACC1:acc#351.itm(6)} -attr vt d
+load net {ACC1:acc#351.itm(7)} -attr vt d
+load net {ACC1:acc#351.itm(8)} -attr vt d
+load net {ACC1:acc#351.itm(9)} -attr vt d
+load net {ACC1:acc#351.itm(10)} -attr vt d
+load netBundle {ACC1:acc#351.itm} 11 {ACC1:acc#351.itm(0)} {ACC1:acc#351.itm(1)} {ACC1:acc#351.itm(2)} {ACC1:acc#351.itm(3)} {ACC1:acc#351.itm(4)} {ACC1:acc#351.itm(5)} {ACC1:acc#351.itm(6)} {ACC1:acc#351.itm(7)} {ACC1:acc#351.itm(8)} {ACC1:acc#351.itm(9)} {ACC1:acc#351.itm(10)} -attr xrf 64029 -attr oid 1219 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {regs.operator[]#12:not.itm(0)} -attr vt d
+load net {regs.operator[]#12:not.itm(1)} -attr vt d
+load net {regs.operator[]#12:not.itm(2)} -attr vt d
+load net {regs.operator[]#12:not.itm(3)} -attr vt d
+load net {regs.operator[]#12:not.itm(4)} -attr vt d
+load net {regs.operator[]#12:not.itm(5)} -attr vt d
+load net {regs.operator[]#12:not.itm(6)} -attr vt d
+load net {regs.operator[]#12:not.itm(7)} -attr vt d
+load net {regs.operator[]#12:not.itm(8)} -attr vt d
+load net {regs.operator[]#12:not.itm(9)} -attr vt d
+load netBundle {regs.operator[]#12:not.itm} 10 {regs.operator[]#12:not.itm(0)} {regs.operator[]#12:not.itm(1)} {regs.operator[]#12:not.itm(2)} {regs.operator[]#12:not.itm(3)} {regs.operator[]#12:not.itm(4)} {regs.operator[]#12:not.itm(5)} {regs.operator[]#12:not.itm(6)} {regs.operator[]#12:not.itm(7)} {regs.operator[]#12:not.itm(8)} {regs.operator[]#12:not.itm(9)} -attr xrf 64030 -attr oid 1220 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {slc(regs.regs(0).sva#3).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#3).itm} 10 {slc(regs.regs(0).sva#3).itm(0)} {slc(regs.regs(0).sva#3).itm(1)} {slc(regs.regs(0).sva#3).itm(2)} {slc(regs.regs(0).sva#3).itm(3)} {slc(regs.regs(0).sva#3).itm(4)} {slc(regs.regs(0).sva#3).itm(5)} {slc(regs.regs(0).sva#3).itm(6)} {slc(regs.regs(0).sva#3).itm(7)} {slc(regs.regs(0).sva#3).itm(8)} {slc(regs.regs(0).sva#3).itm(9)} -attr xrf 64031 -attr oid 1221 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {regs.operator[]#13:not.itm(0)} -attr vt d
+load net {regs.operator[]#13:not.itm(1)} -attr vt d
+load net {regs.operator[]#13:not.itm(2)} -attr vt d
+load net {regs.operator[]#13:not.itm(3)} -attr vt d
+load net {regs.operator[]#13:not.itm(4)} -attr vt d
+load net {regs.operator[]#13:not.itm(5)} -attr vt d
+load net {regs.operator[]#13:not.itm(6)} -attr vt d
+load net {regs.operator[]#13:not.itm(7)} -attr vt d
+load net {regs.operator[]#13:not.itm(8)} -attr vt d
+load net {regs.operator[]#13:not.itm(9)} -attr vt d
+load netBundle {regs.operator[]#13:not.itm} 10 {regs.operator[]#13:not.itm(0)} {regs.operator[]#13:not.itm(1)} {regs.operator[]#13:not.itm(2)} {regs.operator[]#13:not.itm(3)} {regs.operator[]#13:not.itm(4)} {regs.operator[]#13:not.itm(5)} {regs.operator[]#13:not.itm(6)} {regs.operator[]#13:not.itm(7)} {regs.operator[]#13:not.itm(8)} {regs.operator[]#13:not.itm(9)} -attr xrf 64032 -attr oid 1222 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {slc(regs.regs(0).sva#1).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#1).itm} 10 {slc(regs.regs(0).sva#1).itm(0)} {slc(regs.regs(0).sva#1).itm(1)} {slc(regs.regs(0).sva#1).itm(2)} {slc(regs.regs(0).sva#1).itm(3)} {slc(regs.regs(0).sva#1).itm(4)} {slc(regs.regs(0).sva#1).itm(5)} {slc(regs.regs(0).sva#1).itm(6)} {slc(regs.regs(0).sva#1).itm(7)} {slc(regs.regs(0).sva#1).itm(8)} {slc(regs.regs(0).sva#1).itm(9)} -attr xrf 64033 -attr oid 1223 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {ACC1:acc#350.itm(0)} -attr vt d
+load net {ACC1:acc#350.itm(1)} -attr vt d
+load net {ACC1:acc#350.itm(2)} -attr vt d
+load net {ACC1:acc#350.itm(3)} -attr vt d
+load net {ACC1:acc#350.itm(4)} -attr vt d
+load net {ACC1:acc#350.itm(5)} -attr vt d
+load net {ACC1:acc#350.itm(6)} -attr vt d
+load net {ACC1:acc#350.itm(7)} -attr vt d
+load net {ACC1:acc#350.itm(8)} -attr vt d
+load net {ACC1:acc#350.itm(9)} -attr vt d
+load net {ACC1:acc#350.itm(10)} -attr vt d
+load netBundle {ACC1:acc#350.itm} 11 {ACC1:acc#350.itm(0)} {ACC1:acc#350.itm(1)} {ACC1:acc#350.itm(2)} {ACC1:acc#350.itm(3)} {ACC1:acc#350.itm(4)} {ACC1:acc#350.itm(5)} {ACC1:acc#350.itm(6)} {ACC1:acc#350.itm(7)} {ACC1:acc#350.itm(8)} {ACC1:acc#350.itm(9)} {ACC1:acc#350.itm(10)} -attr xrf 64034 -attr oid 1224 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {regs.operator[]#14:not.itm(0)} -attr vt d
+load net {regs.operator[]#14:not.itm(1)} -attr vt d
+load net {regs.operator[]#14:not.itm(2)} -attr vt d
+load net {regs.operator[]#14:not.itm(3)} -attr vt d
+load net {regs.operator[]#14:not.itm(4)} -attr vt d
+load net {regs.operator[]#14:not.itm(5)} -attr vt d
+load net {regs.operator[]#14:not.itm(6)} -attr vt d
+load net {regs.operator[]#14:not.itm(7)} -attr vt d
+load net {regs.operator[]#14:not.itm(8)} -attr vt d
+load net {regs.operator[]#14:not.itm(9)} -attr vt d
+load netBundle {regs.operator[]#14:not.itm} 10 {regs.operator[]#14:not.itm(0)} {regs.operator[]#14:not.itm(1)} {regs.operator[]#14:not.itm(2)} {regs.operator[]#14:not.itm(3)} {regs.operator[]#14:not.itm(4)} {regs.operator[]#14:not.itm(5)} {regs.operator[]#14:not.itm(6)} {regs.operator[]#14:not.itm(7)} {regs.operator[]#14:not.itm(8)} {regs.operator[]#14:not.itm(9)} -attr xrf 64035 -attr oid 1225 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {slc(regs.regs(0).sva#2).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#2).itm} 10 {slc(regs.regs(0).sva#2).itm(0)} {slc(regs.regs(0).sva#2).itm(1)} {slc(regs.regs(0).sva#2).itm(2)} {slc(regs.regs(0).sva#2).itm(3)} {slc(regs.regs(0).sva#2).itm(4)} {slc(regs.regs(0).sva#2).itm(5)} {slc(regs.regs(0).sva#2).itm(6)} {slc(regs.regs(0).sva#2).itm(7)} {slc(regs.regs(0).sva#2).itm(8)} {slc(regs.regs(0).sva#2).itm(9)} -attr xrf 64036 -attr oid 1226 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {ACC1:acc#359.itm(0)} -attr vt d
+load net {ACC1:acc#359.itm(1)} -attr vt d
+load net {ACC1:acc#359.itm(2)} -attr vt d
+load netBundle {ACC1:acc#359.itm} 3 {ACC1:acc#359.itm(0)} {ACC1:acc#359.itm(1)} {ACC1:acc#359.itm(2)} -attr xrf 64037 -attr oid 1227 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#359.itm}
+load net {conc#1089.itm(0)} -attr vt d
+load net {conc#1089.itm(1)} -attr vt d
+load net {conc#1089.itm(2)} -attr vt d
+load netBundle {conc#1089.itm} 3 {conc#1089.itm(0)} {conc#1089.itm(1)} {conc#1089.itm(2)} -attr xrf 64038 -attr oid 1228 -attr vt d -attr @path {/sobel/sobel:core/conc#1089.itm}
+load net {ACC1:conc#1180.itm(0)} -attr vt d
+load net {ACC1:conc#1180.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1180.itm} 2 {ACC1:conc#1180.itm(0)} {ACC1:conc#1180.itm(1)} -attr xrf 64039 -attr oid 1229 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1180.itm}
+load net {ACC1:acc#358.itm(0)} -attr vt d
+load net {ACC1:acc#358.itm(1)} -attr vt d
+load net {ACC1:acc#358.itm(2)} -attr vt d
+load net {ACC1:acc#358.itm(3)} -attr vt d
+load netBundle {ACC1:acc#358.itm} 4 {ACC1:acc#358.itm(0)} {ACC1:acc#358.itm(1)} {ACC1:acc#358.itm(2)} {ACC1:acc#358.itm(3)} -attr xrf 64040 -attr oid 1230 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#358.itm}
+load net {conc#1090.itm(0)} -attr vt d
+load net {conc#1090.itm(1)} -attr vt d
+load net {conc#1090.itm(2)} -attr vt d
+load netBundle {conc#1090.itm} 3 {conc#1090.itm(0)} {conc#1090.itm(1)} {conc#1090.itm(2)} -attr xrf 64041 -attr oid 1231 -attr vt d -attr @path {/sobel/sobel:core/conc#1090.itm}
+load net {ACC1-1:not#299.itm(0)} -attr vt d
+load net {ACC1-1:not#299.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#299.itm} 2 {ACC1-1:not#299.itm(0)} {ACC1-1:not#299.itm(1)} -attr xrf 64042 -attr oid 1232 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#299.itm}
+load net {slc(ACC1:acc#223.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#223.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#223.psp#1.sva).itm} 2 {slc(ACC1:acc#223.psp#1.sva).itm(0)} {slc(ACC1:acc#223.psp#1.sva).itm(1)} -attr xrf 64043 -attr oid 1233 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp#1.sva).itm}
+load net {conc#1091.itm(0)} -attr vt d
+load net {conc#1091.itm(1)} -attr vt d
+load netBundle {conc#1091.itm} 2 {conc#1091.itm(0)} {conc#1091.itm(1)} -attr xrf 64044 -attr oid 1234 -attr vt d -attr @path {/sobel/sobel:core/conc#1091.itm}
+load net {ACC1:slc#33.itm(0)} -attr vt d
+load net {ACC1:slc#33.itm(1)} -attr vt d
+load net {ACC1:slc#33.itm(2)} -attr vt d
+load net {ACC1:slc#33.itm(3)} -attr vt d
+load netBundle {ACC1:slc#33.itm} 4 {ACC1:slc#33.itm(0)} {ACC1:slc#33.itm(1)} {ACC1:slc#33.itm(2)} {ACC1:slc#33.itm(3)} -attr xrf 64045 -attr oid 1235 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#356.itm(0)} -attr vt d
+load net {ACC1:acc#356.itm(1)} -attr vt d
+load net {ACC1:acc#356.itm(2)} -attr vt d
+load net {ACC1:acc#356.itm(3)} -attr vt d
+load net {ACC1:acc#356.itm(4)} -attr vt d
+load netBundle {ACC1:acc#356.itm} 5 {ACC1:acc#356.itm(0)} {ACC1:acc#356.itm(1)} {ACC1:acc#356.itm(2)} {ACC1:acc#356.itm(3)} {ACC1:acc#356.itm(4)} -attr xrf 64046 -attr oid 1236 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356.itm}
+load net {conc#1092.itm(0)} -attr vt d
+load net {conc#1092.itm(1)} -attr vt d
+load net {conc#1092.itm(2)} -attr vt d
+load net {conc#1092.itm(3)} -attr vt d
+load netBundle {conc#1092.itm} 4 {conc#1092.itm(0)} {conc#1092.itm(1)} {conc#1092.itm(2)} {conc#1092.itm(3)} -attr xrf 64047 -attr oid 1237 -attr vt d -attr @path {/sobel/sobel:core/conc#1092.itm}
+load net {ACC1:slc#31.itm(0)} -attr vt d
+load net {ACC1:slc#31.itm(1)} -attr vt d
+load net {ACC1:slc#31.itm(2)} -attr vt d
+load netBundle {ACC1:slc#31.itm} 3 {ACC1:slc#31.itm(0)} {ACC1:slc#31.itm(1)} {ACC1:slc#31.itm(2)} -attr xrf 64048 -attr oid 1238 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#31.itm}
+load net {ACC1:acc#354.itm(0)} -attr vt d
+load net {ACC1:acc#354.itm(1)} -attr vt d
+load net {ACC1:acc#354.itm(2)} -attr vt d
+load net {ACC1:acc#354.itm(3)} -attr vt d
+load netBundle {ACC1:acc#354.itm} 4 {ACC1:acc#354.itm(0)} {ACC1:acc#354.itm(1)} {ACC1:acc#354.itm(2)} {ACC1:acc#354.itm(3)} -attr xrf 64049 -attr oid 1239 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#354.itm}
+load net {conc#1093.itm(0)} -attr vt d
+load net {conc#1093.itm(1)} -attr vt d
+load netBundle {conc#1093.itm} 2 {conc#1093.itm(0)} {conc#1093.itm(1)} -attr xrf 64050 -attr oid 1240 -attr vt d -attr @path {/sobel/sobel:core/conc#1093.itm}
+load net {ACC1:conc#1169.itm(0)} -attr vt d
+load net {ACC1:conc#1169.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1169.itm} 2 {ACC1:conc#1169.itm(0)} {ACC1:conc#1169.itm(1)} -attr xrf 64051 -attr oid 1241 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1169.itm}
+load net {conc#1094.itm(0)} -attr vt d
+load net {conc#1094.itm(1)} -attr vt d
+load net {conc#1094.itm(2)} -attr vt d
+load net {conc#1094.itm(3)} -attr vt d
+load netBundle {conc#1094.itm} 4 {conc#1094.itm(0)} {conc#1094.itm(1)} {conc#1094.itm(2)} {conc#1094.itm(3)} -attr xrf 64052 -attr oid 1242 -attr vt d -attr @path {/sobel/sobel:core/conc#1094.itm}
+load net {ACC1:slc#32.itm(0)} -attr vt d
+load net {ACC1:slc#32.itm(1)} -attr vt d
+load net {ACC1:slc#32.itm(2)} -attr vt d
+load netBundle {ACC1:slc#32.itm} 3 {ACC1:slc#32.itm(0)} {ACC1:slc#32.itm(1)} {ACC1:slc#32.itm(2)} -attr xrf 64053 -attr oid 1243 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#32.itm}
+load net {ACC1:acc#355.itm(0)} -attr vt d
+load net {ACC1:acc#355.itm(1)} -attr vt d
+load net {ACC1:acc#355.itm(2)} -attr vt d
+load net {ACC1:acc#355.itm(3)} -attr vt d
+load netBundle {ACC1:acc#355.itm} 4 {ACC1:acc#355.itm(0)} {ACC1:acc#355.itm(1)} {ACC1:acc#355.itm(2)} {ACC1:acc#355.itm(3)} -attr xrf 64054 -attr oid 1244 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#355.itm}
+load net {conc#1095.itm(0)} -attr vt d
+load net {conc#1095.itm(1)} -attr vt d
+load net {conc#1095.itm(2)} -attr vt d
+load netBundle {conc#1095.itm} 3 {conc#1095.itm(0)} {conc#1095.itm(1)} {conc#1095.itm(2)} -attr xrf 64055 -attr oid 1245 -attr vt d -attr @path {/sobel/sobel:core/conc#1095.itm}
+load net {ACC1:slc#30.itm(0)} -attr vt d
+load net {ACC1:slc#30.itm(1)} -attr vt d
+load netBundle {ACC1:slc#30.itm} 2 {ACC1:slc#30.itm(0)} {ACC1:slc#30.itm(1)} -attr xrf 64056 -attr oid 1246 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#30.itm}
+load net {ACC1:acc#353.itm(0)} -attr vt d
+load net {ACC1:acc#353.itm(1)} -attr vt d
+load net {ACC1:acc#353.itm(2)} -attr vt d
+load netBundle {ACC1:acc#353.itm} 3 {ACC1:acc#353.itm(0)} {ACC1:acc#353.itm(1)} {ACC1:acc#353.itm(2)} -attr xrf 64057 -attr oid 1247 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#353.itm}
+load net {conc#1096.itm(0)} -attr vt d
+load net {conc#1096.itm(1)} -attr vt d
+load netBundle {conc#1096.itm} 2 {conc#1096.itm(0)} {conc#1096.itm(1)} -attr xrf 64058 -attr oid 1248 -attr vt d -attr @path {/sobel/sobel:core/conc#1096.itm}
+load net {ACC1:conc#1167.itm(0)} -attr vt d
+load net {ACC1:conc#1167.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1167.itm} 2 {ACC1:conc#1167.itm(0)} {ACC1:conc#1167.itm(1)} -attr xrf 64059 -attr oid 1249 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1167.itm}
+load net {ACC1:conc#1171.itm(0)} -attr vt d
+load net {ACC1:conc#1171.itm(1)} -attr vt d
+load net {ACC1:conc#1171.itm(2)} -attr vt d
+load netBundle {ACC1:conc#1171.itm} 3 {ACC1:conc#1171.itm(0)} {ACC1:conc#1171.itm(1)} {ACC1:conc#1171.itm(2)} -attr xrf 64060 -attr oid 1250 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1171.itm}
+load net {ACC1:slc#29.itm(0)} -attr vt d
+load net {ACC1:slc#29.itm(1)} -attr vt d
+load netBundle {ACC1:slc#29.itm} 2 {ACC1:slc#29.itm(0)} {ACC1:slc#29.itm(1)} -attr xrf 64061 -attr oid 1251 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#29.itm}
+load net {ACC1:acc#352.itm(0)} -attr vt d
+load net {ACC1:acc#352.itm(1)} -attr vt d
+load net {ACC1:acc#352.itm(2)} -attr vt d
+load netBundle {ACC1:acc#352.itm} 3 {ACC1:acc#352.itm(0)} {ACC1:acc#352.itm(1)} {ACC1:acc#352.itm(2)} -attr xrf 64062 -attr oid 1252 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#352.itm}
+load net {conc#1097.itm(0)} -attr vt d
+load net {conc#1097.itm(1)} -attr vt d
+load netBundle {conc#1097.itm} 2 {conc#1097.itm(0)} {conc#1097.itm(1)} -attr xrf 64063 -attr oid 1253 -attr vt d -attr @path {/sobel/sobel:core/conc#1097.itm}
+load net {ACC1:conc#1165.itm(0)} -attr vt d
+load net {ACC1:conc#1165.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1165.itm} 2 {ACC1:conc#1165.itm(0)} {ACC1:conc#1165.itm(1)} -attr xrf 64064 -attr oid 1254 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1165.itm}
+load net {ACC1:slc#34.itm(0)} -attr vt d
+load net {ACC1:slc#34.itm(1)} -attr vt d
+load netBundle {ACC1:slc#34.itm} 2 {ACC1:slc#34.itm(0)} {ACC1:slc#34.itm(1)} -attr xrf 64065 -attr oid 1255 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#357.itm(0)} -attr vt d
+load net {ACC1:acc#357.itm(1)} -attr vt d
+load net {ACC1:acc#357.itm(2)} -attr vt d
+load netBundle {ACC1:acc#357.itm} 3 {ACC1:acc#357.itm(0)} {ACC1:acc#357.itm(1)} {ACC1:acc#357.itm(2)} -attr xrf 64066 -attr oid 1256 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#357.itm}
+load net {conc#1098.itm(0)} -attr vt d
+load net {conc#1098.itm(1)} -attr vt d
+load netBundle {conc#1098.itm} 2 {conc#1098.itm(0)} {conc#1098.itm(1)} -attr xrf 64067 -attr oid 1257 -attr vt d -attr @path {/sobel/sobel:core/conc#1098.itm}
+load net {ACC1:conc#1175.itm(0)} -attr vt d
+load net {ACC1:conc#1175.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1175.itm} 2 {ACC1:conc#1175.itm(0)} {ACC1:conc#1175.itm(1)} -attr xrf 64068 -attr oid 1258 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1175.itm}
+load net {ACC1:exs#1655.itm(0)} -attr vt d
+load net {ACC1:exs#1655.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1655.itm} 2 {ACC1:exs#1655.itm(0)} {ACC1:exs#1655.itm(1)} -attr xrf 64069 -attr oid 1259 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1655.itm}
+load net {ACC1:exs#1611.itm(0)} -attr vt d
+load net {ACC1:exs#1611.itm(1)} -attr vt d
+load netBundle {ACC1:exs#1611.itm} 2 {ACC1:exs#1611.itm(0)} {ACC1:exs#1611.itm(1)} -attr xrf 64070 -attr oid 1260 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1611.itm}
+load net {ACC1:acc#339.itm(0)} -attr vt d
+load net {ACC1:acc#339.itm(1)} -attr vt d
+load net {ACC1:acc#339.itm(2)} -attr vt d
+load netBundle {ACC1:acc#339.itm} 3 {ACC1:acc#339.itm(0)} {ACC1:acc#339.itm(1)} {ACC1:acc#339.itm(2)} -attr xrf 64071 -attr oid 1261 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {conc#1099.itm(0)} -attr vt d
+load net {conc#1099.itm(1)} -attr vt d
+load net {conc#1099.itm(2)} -attr vt d
+load netBundle {conc#1099.itm} 3 {conc#1099.itm(0)} {conc#1099.itm(1)} {conc#1099.itm(2)} -attr xrf 64072 -attr oid 1262 -attr vt d -attr @path {/sobel/sobel:core/conc#1099.itm}
+load net {ACC1:conc#1144.itm(0)} -attr vt d
+load net {ACC1:conc#1144.itm(1)} -attr vt d
+load netBundle {ACC1:conc#1144.itm} 2 {ACC1:conc#1144.itm(0)} {ACC1:conc#1144.itm(1)} -attr xrf 64073 -attr oid 1263 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1144.itm}
+load net {clk} -attr xrf 64074 -attr oid 1264
+load net {clk} -port {clk} -attr xrf 64075 -attr oid 1265
+load net {en} -attr xrf 64076 -attr oid 1266
+load net {en} -port {en} -attr xrf 64077 -attr oid 1267
+load net {arst_n} -attr xrf 64078 -attr oid 1268
+load net {arst_n} -port {arst_n} -attr xrf 64079 -attr oid 1269
+load net {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 64080 -attr oid 1270 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(0)} -port {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -port {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -port {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -port {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -port {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -port {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -port {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -port {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -port {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -port {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -port {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -port {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -port {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -port {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -port {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -port {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -port {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -port {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -port {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -port {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -port {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -port {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -port {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -port {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -port {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -port {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -port {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -port {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -port {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -port {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -port {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -port {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -port {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -port {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -port {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -port {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -port {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -port {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -port {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -port {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -port {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -port {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -port {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -port {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -port {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -port {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -port {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -port {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -port {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -port {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -port {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -port {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -port {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -port {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -port {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -port {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -port {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -port {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -port {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -port {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -port {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -port {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -port {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -port {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -port {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -port {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -port {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -port {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -port {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -port {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -port {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -port {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -port {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -port {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -port {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -port {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -port {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -port {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -port {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -port {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -port {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -port {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -port {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -port {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -port {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -port {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -port {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -port {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -port {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -port {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 64081 -attr oid 1271 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d} 30 {vout:rsc:mgc_out_stdreg.d(0)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(29)} -attr xrf 64082 -attr oid 1272 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -port {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -port {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -port {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -port {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -port {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -port {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -port {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -port {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -port {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -port {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -port {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -port {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -port {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -port {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -port {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -port {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -port {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -port {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -port {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -port {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -port {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -port {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -port {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -port {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -port {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -port {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -port {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -port {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -port {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -port {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:or" "or(2,10)" "INTERFACE" -attr xrf 64083 -attr oid 1273 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or} -attr area 7.298324 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2)"
+load net {FRAME:acc#2.psp.sva(0)} -pin  "FRAME:or" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "FRAME:or" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "FRAME:or" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "FRAME:or" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "FRAME:or" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "FRAME:or" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "FRAME:or" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "FRAME:or" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "FRAME:or" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "FRAME:or" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(10)} -pin  "FRAME:or" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {FRAME:acc#2.psp.sva(11)} -pin  "FRAME:or" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(2)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(3)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(4)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(5)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(6)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(7)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(8)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {GND} -pin  "FRAME:or" {A1(9)} -attr @path {/sobel/sobel:core/conc#878.itm}
+load net {FRAME:or.itm(0)} -pin  "FRAME:or" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(1)} -pin  "FRAME:or" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(2)} -pin  "FRAME:or" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(3)} -pin  "FRAME:or" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(4)} -pin  "FRAME:or" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(5)} -pin  "FRAME:or" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(6)} -pin  "FRAME:or" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(7)} -pin  "FRAME:or" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(8)} -pin  "FRAME:or" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(9)} -pin  "FRAME:or" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load inst "FRAME:or#3" "or(2,6)" "INTERFACE" -attr xrf 64084 -attr oid 1274 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3} -attr area 4.378994 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2)"
+load net {FRAME:acc#2.psp.sva(0)} -pin  "FRAME:or#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "FRAME:or#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "FRAME:or#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "FRAME:or#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "FRAME:or#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "FRAME:or#3" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(10)} -pin  "FRAME:or#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {FRAME:acc#2.psp.sva(11)} -pin  "FRAME:or#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(2)} -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(3)} -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(4)} -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(5)} -attr @path {/sobel/sobel:core/conc#879.itm}
+load net {FRAME:or#3.itm(0)} -pin  "FRAME:or#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(1)} -pin  "FRAME:or#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(2)} -pin  "FRAME:or#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(3)} -pin  "FRAME:or#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(4)} -pin  "FRAME:or#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(5)} -pin  "FRAME:or#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load inst "mux" "mux(2,30)" "INTERFACE" -attr xrf 64085 -attr oid 1275 -attr vt d -attr @path {/sobel/sobel:core/mux} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {FRAME:acc#2.psp.sva(0)} -pin  "mux" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "mux" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "mux" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "mux" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "mux" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "mux" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "mux" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "mux" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "mux" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "mux" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(0)} -pin  "mux" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(1)} -pin  "mux" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(2)} -pin  "mux" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(3)} -pin  "mux" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(4)} -pin  "mux" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(5)} -pin  "mux" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "mux" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "mux" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "mux" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "mux" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(0)} -pin  "mux" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(1)} -pin  "mux" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(2)} -pin  "mux" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(3)} -pin  "mux" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(4)} -pin  "mux" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(5)} -pin  "mux" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(6)} -pin  "mux" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(7)} -pin  "mux" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(8)} -pin  "mux" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(9)} -pin  "mux" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "mux" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "mux" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "mux" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "mux" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "mux" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "mux" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "mux" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "mux" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "mux" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "mux" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "mux" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "mux" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "mux" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "mux" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "mux" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "mux" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "mux" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "mux" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "mux" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "mux" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {main.stage_0#2} -pin  "mux" {S(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {mux.itm(0)} -pin  "mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "mux" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "mux" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "mux" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "mux" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "mux" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "mux" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "mux" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "mux" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "mux" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "mux" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "mux" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "mux" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "mux" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "mux" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "mux" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "mux" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "mux" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "mux" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "mux" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "mux" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 64086 -attr oid 1276 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)}
+load net {mux.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 64087 -attr oid 1277 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "ACC1:acc#326" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 64088 -attr oid 1278 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#227.psp.sva(9)} -pin  "ACC1:acc#326" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#13.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#326" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#14.itm}
+load net {ACC1:acc#326.itm(0)} -pin  "ACC1:acc#326" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(1)} -pin  "ACC1:acc#326" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load inst "ACC1:acc#325" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 64089 -attr oid 1279 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#326.itm(0)} -pin  "ACC1:acc#325" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(1)} -pin  "ACC1:acc#325" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#224.psp.sva(8)} -pin  "ACC1:acc#325" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#8.itm}
+load net {ACC1:acc#325.itm(0)} -pin  "ACC1:acc#325" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(1)} -pin  "ACC1:acc#325" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load inst "ACC1:acc#324" "add(2,0,1,0,3)" "INTERFACE" -attr xrf 64090 -attr oid 1280 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#325.itm(0)} -pin  "ACC1:acc#324" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(1)} -pin  "ACC1:acc#324" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#228.psp.sva(8)} -pin  "ACC1:acc#324" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#25.itm}
+load net {ACC1:acc#324.itm(0)} -pin  "ACC1:acc#324" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(1)} -pin  "ACC1:acc#324" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(2)} -pin  "ACC1:acc#324" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load inst "ACC1:acc#323" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 64091 -attr oid 1281 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#324.itm(0)} -pin  "ACC1:acc#323" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(1)} -pin  "ACC1:acc#323" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(2)} -pin  "ACC1:acc#323" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#226.psp.sva(8)} -pin  "ACC1:acc#323" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#20.itm}
+load net {ACC1:acc#323.itm(0)} -pin  "ACC1:acc#323" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(1)} -pin  "ACC1:acc#323" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(2)} -pin  "ACC1:acc#323" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load inst "ACC1:acc#322" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 64092 -attr oid 1282 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#323.itm(0)} -pin  "ACC1:acc#322" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(1)} -pin  "ACC1:acc#322" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(2)} -pin  "ACC1:acc#322" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#224.psp#1.sva(8)} -pin  "ACC1:acc#322" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#37.itm}
+load net {ACC1:acc#322.itm(0)} -pin  "ACC1:acc#322" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(1)} -pin  "ACC1:acc#322" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(2)} -pin  "ACC1:acc#322" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load inst "ACC1:acc#321" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 64093 -attr oid 1283 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#322.itm(0)} -pin  "ACC1:acc#321" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(1)} -pin  "ACC1:acc#321" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(2)} -pin  "ACC1:acc#321" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1-1:acc#25.psp.sva(9)} -pin  "ACC1:acc#321" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#14.itm}
+load net {ACC1:acc#321.itm(0)} -pin  "ACC1:acc#321" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(1)} -pin  "ACC1:acc#321" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(2)} -pin  "ACC1:acc#321" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load inst "ACC1:acc#320" "add(3,0,1,0,4)" "INTERFACE" -attr xrf 64094 -attr oid 1284 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#321.itm(0)} -pin  "ACC1:acc#320" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(1)} -pin  "ACC1:acc#320" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(2)} -pin  "ACC1:acc#320" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#320" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#14.itm}
+load net {ACC1:acc#320.itm(0)} -pin  "ACC1:acc#320" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#320.itm(1)} -pin  "ACC1:acc#320" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#320.itm(2)} -pin  "ACC1:acc#320" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#320.itm(3)} -pin  "ACC1:acc#320" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load inst "ACC1:mul#58" "mul(4,0,5,0,8)" "INTERFACE" -attr xrf 64095 -attr oid 1285 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,5,0,8)"
+load net {ACC1:acc#320.itm(0)} -pin  "ACC1:mul#58" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#320.itm(1)} -pin  "ACC1:mul#58" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#320.itm(2)} -pin  "ACC1:mul#58" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {ACC1:acc#320.itm(3)} -pin  "ACC1:mul#58" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#320.itm}
+load net {PWR} -pin  "ACC1:mul#58" {B(0)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#58" {B(1)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#58" {B(2)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#58" {B(3)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#58" {B(4)} -attr @path {/sobel/sobel:core/C21_5}
+load net {ACC1:mul#58.itm(0)} -pin  "ACC1:mul#58" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(1)} -pin  "ACC1:mul#58" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(2)} -pin  "ACC1:mul#58" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(3)} -pin  "ACC1:mul#58" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(4)} -pin  "ACC1:mul#58" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(5)} -pin  "ACC1:mul#58" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(6)} -pin  "ACC1:mul#58" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load net {ACC1:mul#58.itm(7)} -pin  "ACC1:mul#58" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#58.itm}
+load inst "ACC1:acc#654" "add(11,1,11,0,12)" "INTERFACE" -attr xrf 64096 -attr oid 1286 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,12)"
+load net {ACC1:acc#224.psp.sva(0)} -pin  "ACC1:acc#654" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#654" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {GND} -pin  "ACC1:acc#654" {A(2)} -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#654" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {GND} -pin  "ACC1:acc#654" {A(4)} -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#654" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {GND} -pin  "ACC1:acc#654" {A(6)} -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#654" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {GND} -pin  "ACC1:acc#654" {A(8)} -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {GND} -pin  "ACC1:acc#654" {A(9)} -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#654" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#880.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#654" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#654" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:acc#227.psp.sva(4)} -pin  "ACC1:acc#654" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(0)} -pin  "ACC1:acc#654" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(1)} -pin  "ACC1:acc#654" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(2)} -pin  "ACC1:acc#654" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(3)} -pin  "ACC1:acc#654" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(4)} -pin  "ACC1:acc#654" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(5)} -pin  "ACC1:acc#654" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(6)} -pin  "ACC1:acc#654" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:mul#58.itm(7)} -pin  "ACC1:acc#654" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1105.itm}
+load net {ACC1:acc#654.itm(0)} -pin  "ACC1:acc#654" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(1)} -pin  "ACC1:acc#654" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(2)} -pin  "ACC1:acc#654" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(3)} -pin  "ACC1:acc#654" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(4)} -pin  "ACC1:acc#654" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(5)} -pin  "ACC1:acc#654" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(6)} -pin  "ACC1:acc#654" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(7)} -pin  "ACC1:acc#654" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(8)} -pin  "ACC1:acc#654" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(9)} -pin  "ACC1:acc#654" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(10)} -pin  "ACC1:acc#654" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(11)} -pin  "ACC1:acc#654" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load inst "ACC1:acc#670" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64097 -attr oid 1287 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#670} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#670" {A(0)} -attr @path {/sobel/sobel:core/exs.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#670" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#670" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {ACC1-1:nand#1.cse.sva} -pin  "ACC1:acc#670" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:exs#1474.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#670" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:exs#1474.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#670" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:exs#1474.itm}
+load net {ACC1:acc#670.itm(0)} -pin  "ACC1:acc#670" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#670.itm}
+load net {ACC1:acc#670.itm(1)} -pin  "ACC1:acc#670" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#670.itm}
+load net {ACC1:acc#670.itm(2)} -pin  "ACC1:acc#670" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#670.itm}
+load net {ACC1:acc#670.itm(3)} -pin  "ACC1:acc#670" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#670.itm}
+load inst "ACC1-1:not#318" "not(1)" "INTERFACE" -attr xrf 64098 -attr oid 1288 -attr @path {/sobel/sobel:core/ACC1-1:not#318} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#338.itm(3)} -pin  "ACC1-1:not#318" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#26.sva)#6.itm}
+load net {ACC1-1:not#318.itm} -pin  "ACC1-1:not#318" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#318.itm}
+load inst "ACC1:acc#669" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64099 -attr oid 1289 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#669} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#669" {A(0)} -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#669" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#669" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {ACC1-1:not#318.itm} -pin  "ACC1:acc#669" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1476.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#669" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1476.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#669" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1476.itm}
+load net {ACC1:acc#669.itm(0)} -pin  "ACC1:acc#669" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#669.itm}
+load net {ACC1:acc#669.itm(1)} -pin  "ACC1:acc#669" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#669.itm}
+load net {ACC1:acc#669.itm(2)} -pin  "ACC1:acc#669" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#669.itm}
+load net {ACC1:acc#669.itm(3)} -pin  "ACC1:acc#669" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#669.itm}
+load inst "ACC1:acc#676" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64100 -attr oid 1290 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#670.itm(1)} -pin  "ACC1:acc#676" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#153.itm}
+load net {ACC1:acc#670.itm(2)} -pin  "ACC1:acc#676" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#153.itm}
+load net {ACC1:acc#670.itm(3)} -pin  "ACC1:acc#676" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#153.itm}
+load net {ACC1:acc#669.itm(1)} -pin  "ACC1:acc#676" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#152.itm}
+load net {ACC1:acc#669.itm(2)} -pin  "ACC1:acc#676" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#152.itm}
+load net {ACC1:acc#669.itm(3)} -pin  "ACC1:acc#676" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#152.itm}
+load net {ACC1:acc#676.itm(0)} -pin  "ACC1:acc#676" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#676.itm(1)} -pin  "ACC1:acc#676" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#676.itm(2)} -pin  "ACC1:acc#676" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#676.itm(3)} -pin  "ACC1:acc#676" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load inst "ACC1:acc#668" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64101 -attr oid 1291 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#668} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#668" {A(0)} -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#668" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#668" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {ACC1:acc#338.itm(2)} -pin  "ACC1:acc#668" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1478.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#668" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1478.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#668" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1478.itm}
+load net {ACC1:acc#668.itm(0)} -pin  "ACC1:acc#668" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#668.itm}
+load net {ACC1:acc#668.itm(1)} -pin  "ACC1:acc#668" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#668.itm}
+load net {ACC1:acc#668.itm(2)} -pin  "ACC1:acc#668" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#668.itm}
+load net {ACC1:acc#668.itm(3)} -pin  "ACC1:acc#668" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#668.itm}
+load inst "ACC1:acc#667" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64102 -attr oid 1292 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#667} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#667" {A(0)} -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#667" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#667" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {ACC1:acc#210.psp#2.sva(2)} -pin  "ACC1:acc#667" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1480.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#667" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1480.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#667" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1480.itm}
+load net {ACC1:acc#667.itm(0)} -pin  "ACC1:acc#667" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#667.itm}
+load net {ACC1:acc#667.itm(1)} -pin  "ACC1:acc#667" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#667.itm}
+load net {ACC1:acc#667.itm(2)} -pin  "ACC1:acc#667" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#667.itm}
+load net {ACC1:acc#667.itm(3)} -pin  "ACC1:acc#667" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#667.itm}
+load inst "ACC1:acc#675" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64103 -attr oid 1293 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#668.itm(1)} -pin  "ACC1:acc#675" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#151.itm}
+load net {ACC1:acc#668.itm(2)} -pin  "ACC1:acc#675" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#151.itm}
+load net {ACC1:acc#668.itm(3)} -pin  "ACC1:acc#675" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#151.itm}
+load net {ACC1:acc#667.itm(1)} -pin  "ACC1:acc#675" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#150.itm}
+load net {ACC1:acc#667.itm(2)} -pin  "ACC1:acc#675" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#150.itm}
+load net {ACC1:acc#667.itm(3)} -pin  "ACC1:acc#675" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#150.itm}
+load net {ACC1:acc#675.itm(0)} -pin  "ACC1:acc#675" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#675.itm(1)} -pin  "ACC1:acc#675" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#675.itm(2)} -pin  "ACC1:acc#675" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#675.itm(3)} -pin  "ACC1:acc#675" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load inst "ACC1:acc#680" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64104 -attr oid 1294 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#676.itm(0)} -pin  "ACC1:acc#680" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#676.itm(1)} -pin  "ACC1:acc#680" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#676.itm(2)} -pin  "ACC1:acc#680" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#676.itm(3)} -pin  "ACC1:acc#680" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#676.itm}
+load net {ACC1:acc#675.itm(0)} -pin  "ACC1:acc#680" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#675.itm(1)} -pin  "ACC1:acc#680" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#675.itm(2)} -pin  "ACC1:acc#680" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#675.itm(3)} -pin  "ACC1:acc#680" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#675.itm}
+load net {ACC1:acc#680.itm(0)} -pin  "ACC1:acc#680" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(1)} -pin  "ACC1:acc#680" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(2)} -pin  "ACC1:acc#680" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(3)} -pin  "ACC1:acc#680" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(4)} -pin  "ACC1:acc#680" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load inst "ACC1:acc#683" "add(6,0,5,0,7)" "INTERFACE" -attr xrf 64105 -attr oid 1295 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#683" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#683" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {GND} -pin  "ACC1:acc#683" {A(2)} -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#683" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {GND} -pin  "ACC1:acc#683" {A(4)} -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#683" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#883.itm}
+load net {ACC1:acc#680.itm(0)} -pin  "ACC1:acc#683" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(1)} -pin  "ACC1:acc#683" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(2)} -pin  "ACC1:acc#683" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(3)} -pin  "ACC1:acc#683" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#680.itm(4)} -pin  "ACC1:acc#683" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#680.itm}
+load net {ACC1:acc#683.itm(0)} -pin  "ACC1:acc#683" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(1)} -pin  "ACC1:acc#683" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(2)} -pin  "ACC1:acc#683" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(3)} -pin  "ACC1:acc#683" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(4)} -pin  "ACC1:acc#683" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(5)} -pin  "ACC1:acc#683" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(6)} -pin  "ACC1:acc#683" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load inst "ACC1:acc#686" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 64106 -attr oid 1296 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#686" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#686" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {GND} -pin  "ACC1:acc#686" {A(2)} -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#686" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {GND} -pin  "ACC1:acc#686" {A(4)} -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#686" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {GND} -pin  "ACC1:acc#686" {A(6)} -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#686" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#882.itm}
+load net {ACC1:acc#683.itm(0)} -pin  "ACC1:acc#686" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(1)} -pin  "ACC1:acc#686" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(2)} -pin  "ACC1:acc#686" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(3)} -pin  "ACC1:acc#686" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(4)} -pin  "ACC1:acc#686" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(5)} -pin  "ACC1:acc#686" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#683.itm(6)} -pin  "ACC1:acc#686" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#683.itm}
+load net {ACC1:acc#686.itm(0)} -pin  "ACC1:acc#686" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(1)} -pin  "ACC1:acc#686" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(2)} -pin  "ACC1:acc#686" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(3)} -pin  "ACC1:acc#686" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(4)} -pin  "ACC1:acc#686" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(5)} -pin  "ACC1:acc#686" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(6)} -pin  "ACC1:acc#686" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(7)} -pin  "ACC1:acc#686" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load inst "ACC1:acc#688" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 64107 -attr oid 1297 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,11)"
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#688" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {GND} -pin  "ACC1:acc#688" {A(1)} -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#688" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {GND} -pin  "ACC1:acc#688" {A(3)} -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#688" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {GND} -pin  "ACC1:acc#688" {A(5)} -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#688" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {GND} -pin  "ACC1:acc#688" {A(7)} -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#688" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#881.itm}
+load net {ACC1:acc#686.itm(0)} -pin  "ACC1:acc#688" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(1)} -pin  "ACC1:acc#688" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(2)} -pin  "ACC1:acc#688" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(3)} -pin  "ACC1:acc#688" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(4)} -pin  "ACC1:acc#688" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(5)} -pin  "ACC1:acc#688" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(6)} -pin  "ACC1:acc#688" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#686.itm(7)} -pin  "ACC1:acc#688" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#686.itm}
+load net {ACC1:acc#688.itm(0)} -pin  "ACC1:acc#688" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(1)} -pin  "ACC1:acc#688" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(2)} -pin  "ACC1:acc#688" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(3)} -pin  "ACC1:acc#688" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(4)} -pin  "ACC1:acc#688" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(5)} -pin  "ACC1:acc#688" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(6)} -pin  "ACC1:acc#688" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(7)} -pin  "ACC1:acc#688" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(8)} -pin  "ACC1:acc#688" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(9)} -pin  "ACC1:acc#688" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load inst "ACC1:acc#665" "add(3,1,2,1,4)" "INTERFACE" -attr xrf 64108 -attr oid 1298 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#665} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#665" {A(0)} -attr @path {/sobel/sobel:core/conc#888.itm}
+load net {acc.psp#2.sva(3)} -pin  "ACC1:acc#665" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#888.itm}
+load net {PWR} -pin  "ACC1:acc#665" {A(2)} -attr @path {/sobel/sobel:core/conc#888.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#665" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1420.itm}
+load net {ACC1:acc#210.psp#2.sva(3)} -pin  "ACC1:acc#665" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1420.itm}
+load net {ACC1:acc#665.itm(0)} -pin  "ACC1:acc#665" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#665.itm}
+load net {ACC1:acc#665.itm(1)} -pin  "ACC1:acc#665" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#665.itm}
+load net {ACC1:acc#665.itm(2)} -pin  "ACC1:acc#665" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#665.itm}
+load net {ACC1:acc#665.itm(3)} -pin  "ACC1:acc#665" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#665.itm}
+load inst "ACC1:acc#674" "add(3,-1,2,1,3)" "INTERFACE" -attr xrf 64109 -attr oid 1299 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {ACC1:acc#665.itm(1)} -pin  "ACC1:acc#674" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#148.itm}
+load net {ACC1:acc#665.itm(2)} -pin  "ACC1:acc#674" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#148.itm}
+load net {ACC1:acc#665.itm(3)} -pin  "ACC1:acc#674" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#148.itm}
+load net {ACC1:acc#220.psp#1.sva(1)} -pin  "ACC1:acc#674" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva)#3.itm}
+load net {ACC1:acc#220.psp#1.sva(2)} -pin  "ACC1:acc#674" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva)#3.itm}
+load net {ACC1:acc#674.itm(0)} -pin  "ACC1:acc#674" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load net {ACC1:acc#674.itm(1)} -pin  "ACC1:acc#674" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load net {ACC1:acc#674.itm(2)} -pin  "ACC1:acc#674" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load inst "ACC1:acc#666" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 64110 -attr oid 1300 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#666" {A(0)} -attr @path {/sobel/sobel:core/conc#889.itm}
+load net {acc.psp#2.sva(1)} -pin  "ACC1:acc#666" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#889.itm}
+load net {acc.psp#2.sva(3)} -pin  "ACC1:acc#666" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#889.itm}
+load net {ACC1:acc#210.psp#2.sva(1)} -pin  "ACC1:acc#666" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1422.itm}
+load net {acc.psp#2.sva(2)} -pin  "ACC1:acc#666" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1422.itm}
+load net {ACC1:acc#210.psp#2.sva(3)} -pin  "ACC1:acc#666" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1422.itm}
+load net {ACC1:acc#666.itm(0)} -pin  "ACC1:acc#666" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666.itm}
+load net {ACC1:acc#666.itm(1)} -pin  "ACC1:acc#666" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666.itm}
+load net {ACC1:acc#666.itm(2)} -pin  "ACC1:acc#666" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666.itm}
+load net {ACC1:acc#666.itm(3)} -pin  "ACC1:acc#666" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666.itm}
+load net {ACC1:acc#666.itm(4)} -pin  "ACC1:acc#666" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#666.itm}
+load inst "ACC1:acc#679" "add(3,1,4,-1,4)" "INTERFACE" -attr xrf 64111 -attr oid 1301 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#674.itm(0)} -pin  "ACC1:acc#679" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load net {ACC1:acc#674.itm(1)} -pin  "ACC1:acc#679" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load net {ACC1:acc#674.itm(2)} -pin  "ACC1:acc#679" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#674.itm}
+load net {ACC1:acc#666.itm(1)} -pin  "ACC1:acc#679" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#149.itm}
+load net {ACC1:acc#666.itm(2)} -pin  "ACC1:acc#679" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#149.itm}
+load net {ACC1:acc#666.itm(3)} -pin  "ACC1:acc#679" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#149.itm}
+load net {ACC1:acc#666.itm(4)} -pin  "ACC1:acc#679" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#149.itm}
+load net {ACC1:acc#679.itm(0)} -pin  "ACC1:acc#679" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#679.itm(1)} -pin  "ACC1:acc#679" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#679.itm(2)} -pin  "ACC1:acc#679" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#679.itm(3)} -pin  "ACC1:acc#679" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load inst "ACC1:acc#678" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 64112 -attr oid 1302 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#678" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#558.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#678" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#558.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#678" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#558.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#678" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#558.itm}
+load net {ACC1:acc#673.cse(0)} -pin  "ACC1:acc#678" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#673.cse(1)} -pin  "ACC1:acc#678" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#673.cse(2)} -pin  "ACC1:acc#678" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#678.itm(0)} -pin  "ACC1:acc#678" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(1)} -pin  "ACC1:acc#678" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(2)} -pin  "ACC1:acc#678" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(3)} -pin  "ACC1:acc#678" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(4)} -pin  "ACC1:acc#678" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load inst "ACC1:acc#682" "add(4,1,5,0,6)" "INTERFACE" -attr xrf 64113 -attr oid 1303 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#679.itm(0)} -pin  "ACC1:acc#682" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#679.itm(1)} -pin  "ACC1:acc#682" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#679.itm(2)} -pin  "ACC1:acc#682" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#679.itm(3)} -pin  "ACC1:acc#682" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#679.itm}
+load net {ACC1:acc#678.itm(0)} -pin  "ACC1:acc#682" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(1)} -pin  "ACC1:acc#682" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(2)} -pin  "ACC1:acc#682" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(3)} -pin  "ACC1:acc#682" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#678.itm(4)} -pin  "ACC1:acc#682" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#678.itm}
+load net {ACC1:acc#682.itm(0)} -pin  "ACC1:acc#682" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(1)} -pin  "ACC1:acc#682" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(2)} -pin  "ACC1:acc#682" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(3)} -pin  "ACC1:acc#682" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(4)} -pin  "ACC1:acc#682" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(5)} -pin  "ACC1:acc#682" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load inst "ACC1:acc#685" "add(6,1,7,0,8)" "INTERFACE" -attr xrf 64114 -attr oid 1304 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#682.itm(0)} -pin  "ACC1:acc#685" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(1)} -pin  "ACC1:acc#685" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(2)} -pin  "ACC1:acc#685" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(3)} -pin  "ACC1:acc#685" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(4)} -pin  "ACC1:acc#685" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {ACC1:acc#682.itm(5)} -pin  "ACC1:acc#685" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#682.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#685" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {GND} -pin  "ACC1:acc#685" {B(1)} -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#685" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {GND} -pin  "ACC1:acc#685" {B(3)} -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#685" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {GND} -pin  "ACC1:acc#685" {B(5)} -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#685" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#890.itm}
+load net {ACC1:acc#685.itm(0)} -pin  "ACC1:acc#685" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(1)} -pin  "ACC1:acc#685" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(2)} -pin  "ACC1:acc#685" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(3)} -pin  "ACC1:acc#685" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(4)} -pin  "ACC1:acc#685" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(5)} -pin  "ACC1:acc#685" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(6)} -pin  "ACC1:acc#685" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(7)} -pin  "ACC1:acc#685" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load inst "ACC1:acc#671" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64115 -attr oid 1305 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#671} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#671" {A(0)} -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#671" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#671" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {ACC1-1:and#3.cse.sva} -pin  "ACC1:acc#671" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1482.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#671" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1482.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#671" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1482.itm}
+load net {ACC1:acc#671.itm(0)} -pin  "ACC1:acc#671" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#671.itm}
+load net {ACC1:acc#671.itm(1)} -pin  "ACC1:acc#671" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#671.itm}
+load net {ACC1:acc#671.itm(2)} -pin  "ACC1:acc#671" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#671.itm}
+load net {ACC1:acc#671.itm(3)} -pin  "ACC1:acc#671" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#671.itm}
+load inst "ACC1:acc#677" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64116 -attr oid 1306 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#673.cse(0)} -pin  "ACC1:acc#677" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#673.cse(1)} -pin  "ACC1:acc#677" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#673.cse(2)} -pin  "ACC1:acc#677" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#671.itm(1)} -pin  "ACC1:acc#677" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#154.itm}
+load net {ACC1:acc#671.itm(2)} -pin  "ACC1:acc#677" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#154.itm}
+load net {ACC1:acc#671.itm(3)} -pin  "ACC1:acc#677" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#154.itm}
+load net {ACC1:acc#677.itm(0)} -pin  "ACC1:acc#677" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#677.itm(1)} -pin  "ACC1:acc#677" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#677.itm(2)} -pin  "ACC1:acc#677" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#677.itm(3)} -pin  "ACC1:acc#677" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load inst "ACC1:acc#681" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 64117 -attr oid 1307 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#681" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#891.itm}
+load net {GND} -pin  "ACC1:acc#681" {A(1)} -attr @path {/sobel/sobel:core/conc#891.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#681" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#891.itm}
+load net {GND} -pin  "ACC1:acc#681" {A(3)} -attr @path {/sobel/sobel:core/conc#891.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#681" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#891.itm}
+load net {ACC1:acc#677.itm(0)} -pin  "ACC1:acc#681" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#677.itm(1)} -pin  "ACC1:acc#681" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#677.itm(2)} -pin  "ACC1:acc#681" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#677.itm(3)} -pin  "ACC1:acc#681" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#677.itm}
+load net {ACC1:acc#681.itm(0)} -pin  "ACC1:acc#681" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(1)} -pin  "ACC1:acc#681" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(2)} -pin  "ACC1:acc#681" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(3)} -pin  "ACC1:acc#681" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(4)} -pin  "ACC1:acc#681" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(5)} -pin  "ACC1:acc#681" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load inst "ACC1:acc#684" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 64118 -attr oid 1308 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#684" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1045.itm}
+load net {ACC1:acc#681.itm(0)} -pin  "ACC1:acc#684" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(1)} -pin  "ACC1:acc#684" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(2)} -pin  "ACC1:acc#684" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(3)} -pin  "ACC1:acc#684" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(4)} -pin  "ACC1:acc#684" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#681.itm(5)} -pin  "ACC1:acc#684" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#681.itm}
+load net {ACC1:acc#684.itm(0)} -pin  "ACC1:acc#684" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(1)} -pin  "ACC1:acc#684" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(2)} -pin  "ACC1:acc#684" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(3)} -pin  "ACC1:acc#684" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(4)} -pin  "ACC1:acc#684" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(5)} -pin  "ACC1:acc#684" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(6)} -pin  "ACC1:acc#684" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(7)} -pin  "ACC1:acc#684" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load inst "ACC1:acc#687" "add(8,1,8,0,10)" "INTERFACE" -attr xrf 64119 -attr oid 1309 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#685.itm(0)} -pin  "ACC1:acc#687" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(1)} -pin  "ACC1:acc#687" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(2)} -pin  "ACC1:acc#687" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(3)} -pin  "ACC1:acc#687" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(4)} -pin  "ACC1:acc#687" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(5)} -pin  "ACC1:acc#687" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(6)} -pin  "ACC1:acc#687" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#685.itm(7)} -pin  "ACC1:acc#687" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#685.itm}
+load net {ACC1:acc#684.itm(0)} -pin  "ACC1:acc#687" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(1)} -pin  "ACC1:acc#687" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(2)} -pin  "ACC1:acc#687" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(3)} -pin  "ACC1:acc#687" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(4)} -pin  "ACC1:acc#687" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(5)} -pin  "ACC1:acc#687" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(6)} -pin  "ACC1:acc#687" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#684.itm(7)} -pin  "ACC1:acc#687" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#684.itm}
+load net {ACC1:acc#687.itm(0)} -pin  "ACC1:acc#687" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(1)} -pin  "ACC1:acc#687" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(2)} -pin  "ACC1:acc#687" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(3)} -pin  "ACC1:acc#687" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(4)} -pin  "ACC1:acc#687" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(5)} -pin  "ACC1:acc#687" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(6)} -pin  "ACC1:acc#687" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(7)} -pin  "ACC1:acc#687" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(8)} -pin  "ACC1:acc#687" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(9)} -pin  "ACC1:acc#687" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load inst "ACC1:acc#690" "add(10,0,10,1,11)" "INTERFACE" -attr xrf 64120 -attr oid 1310 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,12)"
+load net {ACC1:acc#688.itm(0)} -pin  "ACC1:acc#690" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(1)} -pin  "ACC1:acc#690" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(2)} -pin  "ACC1:acc#690" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(3)} -pin  "ACC1:acc#690" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(4)} -pin  "ACC1:acc#690" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(5)} -pin  "ACC1:acc#690" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(6)} -pin  "ACC1:acc#690" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(7)} -pin  "ACC1:acc#690" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(8)} -pin  "ACC1:acc#690" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#688.itm(9)} -pin  "ACC1:acc#690" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#688.itm}
+load net {ACC1:acc#687.itm(0)} -pin  "ACC1:acc#690" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(1)} -pin  "ACC1:acc#690" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(2)} -pin  "ACC1:acc#690" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(3)} -pin  "ACC1:acc#690" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(4)} -pin  "ACC1:acc#690" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(5)} -pin  "ACC1:acc#690" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(6)} -pin  "ACC1:acc#690" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(7)} -pin  "ACC1:acc#690" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(8)} -pin  "ACC1:acc#690" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#687.itm(9)} -pin  "ACC1:acc#690" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#687.itm}
+load net {ACC1:acc#690.itm(0)} -pin  "ACC1:acc#690" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(1)} -pin  "ACC1:acc#690" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(2)} -pin  "ACC1:acc#690" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(3)} -pin  "ACC1:acc#690" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(4)} -pin  "ACC1:acc#690" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(5)} -pin  "ACC1:acc#690" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(6)} -pin  "ACC1:acc#690" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(7)} -pin  "ACC1:acc#690" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(8)} -pin  "ACC1:acc#690" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(9)} -pin  "ACC1:acc#690" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(10)} -pin  "ACC1:acc#690" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load inst "ACC1:acc#718" "add(1,0,2,0,3)" "INTERFACE" -attr xrf 64121 -attr oid 1311 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#718} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,3)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#718" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#10.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#718" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1640.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#718" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1640.itm}
+load net {ACC1:acc#718.itm(0)} -pin  "ACC1:acc#718" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#718.itm}
+load net {ACC1:acc#718.itm(1)} -pin  "ACC1:acc#718" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#718.itm}
+load net {ACC1:acc#718.itm(2)} -pin  "ACC1:acc#718" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#718.itm}
+load inst "ACC1-1:acc#2" "add(11,-1,11,-1,11)" "INTERFACE" -attr xrf 64122 -attr oid 1312 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#690.itm(0)} -pin  "ACC1-1:acc#2" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(1)} -pin  "ACC1-1:acc#2" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(2)} -pin  "ACC1-1:acc#2" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(3)} -pin  "ACC1-1:acc#2" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(4)} -pin  "ACC1-1:acc#2" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(5)} -pin  "ACC1-1:acc#2" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(6)} -pin  "ACC1-1:acc#2" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(7)} -pin  "ACC1-1:acc#2" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(8)} -pin  "ACC1-1:acc#2" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(9)} -pin  "ACC1-1:acc#2" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#690.itm(10)} -pin  "ACC1-1:acc#2" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#690.itm}
+load net {ACC1:acc#718.itm(0)} -pin  "ACC1-1:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {ACC1:acc#718.itm(1)} -pin  "ACC1-1:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {ACC1:acc#718.itm(2)} -pin  "ACC1-1:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {GND} -pin  "ACC1-1:acc#2" {B(4)} -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {GND} -pin  "ACC1-1:acc#2" {B(6)} -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {GND} -pin  "ACC1-1:acc#2" {B(8)} -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {GND} -pin  "ACC1-1:acc#2" {B(9)} -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#893.itm}
+load net {ACC1-1:acc#2.itm(0)} -pin  "ACC1-1:acc#2" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(1)} -pin  "ACC1-1:acc#2" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(2)} -pin  "ACC1-1:acc#2" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(3)} -pin  "ACC1-1:acc#2" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(4)} -pin  "ACC1-1:acc#2" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(5)} -pin  "ACC1-1:acc#2" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(6)} -pin  "ACC1-1:acc#2" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(7)} -pin  "ACC1-1:acc#2" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(8)} -pin  "ACC1-1:acc#2" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(9)} -pin  "ACC1-1:acc#2" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(10)} -pin  "ACC1-1:acc#2" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load inst "ACC1-1:not#320" "not(1)" "INTERFACE" -attr xrf 64123 -attr oid 1313 -attr @path {/sobel/sobel:core/ACC1-1:not#320} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:not#320" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#49.itm}
+load net {ACC1-1:not#320.itm} -pin  "ACC1-1:not#320" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#320.itm}
+load inst "ACC1-1:nand#4" "nand(2,1)" "INTERFACE" -attr xrf 64124 -attr oid 1314 -attr @path {/sobel/sobel:core/ACC1-1:nand#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#359.itm(2)} -pin  "ACC1-1:nand#4" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#40.sva)#2.itm}
+load net {ACC1-1:not#320.itm} -pin  "ACC1-1:nand#4" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#320.itm}
+load net {ACC1-1:nand#4.itm} -pin  "ACC1-1:nand#4" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:nand#4.itm}
+load inst "ACC1:acc#696" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64125 -attr oid 1315 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#696} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#696" {A(0)} -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#696" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#696" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {ACC1-1:nand#4.itm} -pin  "ACC1:acc#696" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1485.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#696" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1485.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#696" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1485.itm}
+load net {ACC1:acc#696.itm(0)} -pin  "ACC1:acc#696" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#696.itm}
+load net {ACC1:acc#696.itm(1)} -pin  "ACC1:acc#696" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#696.itm}
+load net {ACC1:acc#696.itm(2)} -pin  "ACC1:acc#696" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#696.itm}
+load net {ACC1:acc#696.itm(3)} -pin  "ACC1:acc#696" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#696.itm}
+load inst "ACC1-1:not#321" "not(1)" "INTERFACE" -attr xrf 64126 -attr oid 1316 -attr @path {/sobel/sobel:core/ACC1-1:not#321} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#358.itm(3)} -pin  "ACC1-1:not#321" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#38.sva)#4.itm}
+load net {ACC1-1:not#321.itm} -pin  "ACC1-1:not#321" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#321.itm}
+load inst "ACC1:acc#695" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64127 -attr oid 1317 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#695} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#695" {A(0)} -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#695" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#695" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {ACC1-1:not#321.itm} -pin  "ACC1:acc#695" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1487.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#695" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1487.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#695" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1487.itm}
+load net {ACC1:acc#695.itm(0)} -pin  "ACC1:acc#695" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#695.itm}
+load net {ACC1:acc#695.itm(1)} -pin  "ACC1:acc#695" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#695.itm}
+load net {ACC1:acc#695.itm(2)} -pin  "ACC1:acc#695" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#695.itm}
+load net {ACC1:acc#695.itm(3)} -pin  "ACC1:acc#695" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#695.itm}
+load inst "ACC1:acc#702" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64128 -attr oid 1318 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#696.itm(1)} -pin  "ACC1:acc#702" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#160.itm}
+load net {ACC1:acc#696.itm(2)} -pin  "ACC1:acc#702" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#160.itm}
+load net {ACC1:acc#696.itm(3)} -pin  "ACC1:acc#702" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#160.itm}
+load net {ACC1:acc#695.itm(1)} -pin  "ACC1:acc#702" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#159.itm}
+load net {ACC1:acc#695.itm(2)} -pin  "ACC1:acc#702" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#159.itm}
+load net {ACC1:acc#695.itm(3)} -pin  "ACC1:acc#702" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#159.itm}
+load net {ACC1:acc#702.itm(0)} -pin  "ACC1:acc#702" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#702.itm(1)} -pin  "ACC1:acc#702" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#702.itm(2)} -pin  "ACC1:acc#702" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#702.itm(3)} -pin  "ACC1:acc#702" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load inst "ACC1:acc#694" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64129 -attr oid 1319 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#694} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#694" {A(0)} -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#694" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#694" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {ACC1:acc#358.itm(2)} -pin  "ACC1:acc#694" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1489.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#694" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1489.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#694" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1489.itm}
+load net {ACC1:acc#694.itm(0)} -pin  "ACC1:acc#694" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#694.itm}
+load net {ACC1:acc#694.itm(1)} -pin  "ACC1:acc#694" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#694.itm}
+load net {ACC1:acc#694.itm(2)} -pin  "ACC1:acc#694" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#694.itm}
+load net {ACC1:acc#694.itm(3)} -pin  "ACC1:acc#694" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#694.itm}
+load inst "ACC1:acc#693" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64130 -attr oid 1320 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#693} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#693" {A(0)} -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#693" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#693" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {ACC1:acc#217.psp#2.sva(2)} -pin  "ACC1:acc#693" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1491.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#693" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1491.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#693" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1491.itm}
+load net {ACC1:acc#693.itm(0)} -pin  "ACC1:acc#693" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#693.itm}
+load net {ACC1:acc#693.itm(1)} -pin  "ACC1:acc#693" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#693.itm}
+load net {ACC1:acc#693.itm(2)} -pin  "ACC1:acc#693" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#693.itm}
+load net {ACC1:acc#693.itm(3)} -pin  "ACC1:acc#693" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#693.itm}
+load inst "ACC1:acc#701" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64131 -attr oid 1321 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#694.itm(1)} -pin  "ACC1:acc#701" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#158.itm}
+load net {ACC1:acc#694.itm(2)} -pin  "ACC1:acc#701" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#158.itm}
+load net {ACC1:acc#694.itm(3)} -pin  "ACC1:acc#701" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#158.itm}
+load net {ACC1:acc#693.itm(1)} -pin  "ACC1:acc#701" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#157.itm}
+load net {ACC1:acc#693.itm(2)} -pin  "ACC1:acc#701" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#157.itm}
+load net {ACC1:acc#693.itm(3)} -pin  "ACC1:acc#701" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#157.itm}
+load net {ACC1:acc#701.itm(0)} -pin  "ACC1:acc#701" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#701.itm(1)} -pin  "ACC1:acc#701" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#701.itm(2)} -pin  "ACC1:acc#701" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#701.itm(3)} -pin  "ACC1:acc#701" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load inst "ACC1:acc#706" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64132 -attr oid 1322 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#702.itm(0)} -pin  "ACC1:acc#706" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#702.itm(1)} -pin  "ACC1:acc#706" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#702.itm(2)} -pin  "ACC1:acc#706" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#702.itm(3)} -pin  "ACC1:acc#706" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#702.itm}
+load net {ACC1:acc#701.itm(0)} -pin  "ACC1:acc#706" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#701.itm(1)} -pin  "ACC1:acc#706" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#701.itm(2)} -pin  "ACC1:acc#706" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#701.itm(3)} -pin  "ACC1:acc#706" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#701.itm}
+load net {ACC1:acc#706.itm(0)} -pin  "ACC1:acc#706" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(1)} -pin  "ACC1:acc#706" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(2)} -pin  "ACC1:acc#706" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(3)} -pin  "ACC1:acc#706" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(4)} -pin  "ACC1:acc#706" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load inst "ACC1:acc#709" "add(6,0,5,0,7)" "INTERFACE" -attr xrf 64133 -attr oid 1323 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#709" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#709" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {GND} -pin  "ACC1:acc#709" {A(2)} -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {acc#20.psp#2.sva(5)} -pin  "ACC1:acc#709" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {GND} -pin  "ACC1:acc#709" {A(4)} -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {acc#20.psp#2.sva(7)} -pin  "ACC1:acc#709" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#896.itm}
+load net {ACC1:acc#706.itm(0)} -pin  "ACC1:acc#709" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(1)} -pin  "ACC1:acc#709" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(2)} -pin  "ACC1:acc#709" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(3)} -pin  "ACC1:acc#709" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#706.itm(4)} -pin  "ACC1:acc#709" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#706.itm}
+load net {ACC1:acc#709.itm(0)} -pin  "ACC1:acc#709" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(1)} -pin  "ACC1:acc#709" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(2)} -pin  "ACC1:acc#709" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(3)} -pin  "ACC1:acc#709" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(4)} -pin  "ACC1:acc#709" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(5)} -pin  "ACC1:acc#709" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(6)} -pin  "ACC1:acc#709" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load inst "ACC1:acc#712" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 64134 -attr oid 1324 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {acc#20.psp#2.sva(5)} -pin  "ACC1:acc#712" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {acc#20.psp#2.sva(5)} -pin  "ACC1:acc#712" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {GND} -pin  "ACC1:acc#712" {A(2)} -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1:acc#712" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {GND} -pin  "ACC1:acc#712" {A(4)} -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1:acc#712" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {GND} -pin  "ACC1:acc#712" {A(6)} -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1:acc#712" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#895.itm}
+load net {ACC1:acc#709.itm(0)} -pin  "ACC1:acc#712" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(1)} -pin  "ACC1:acc#712" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(2)} -pin  "ACC1:acc#712" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(3)} -pin  "ACC1:acc#712" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(4)} -pin  "ACC1:acc#712" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(5)} -pin  "ACC1:acc#712" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#709.itm(6)} -pin  "ACC1:acc#712" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#709.itm}
+load net {ACC1:acc#712.itm(0)} -pin  "ACC1:acc#712" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(1)} -pin  "ACC1:acc#712" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(2)} -pin  "ACC1:acc#712" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(3)} -pin  "ACC1:acc#712" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(4)} -pin  "ACC1:acc#712" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(5)} -pin  "ACC1:acc#712" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(6)} -pin  "ACC1:acc#712" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(7)} -pin  "ACC1:acc#712" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load inst "ACC1:acc#714" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 64135 -attr oid 1325 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,11)"
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1:acc#714" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {GND} -pin  "ACC1:acc#714" {A(1)} -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1:acc#714" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {GND} -pin  "ACC1:acc#714" {A(3)} -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1:acc#714" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {GND} -pin  "ACC1:acc#714" {A(5)} -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1:acc#714" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {GND} -pin  "ACC1:acc#714" {A(7)} -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1:acc#714" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#894.itm}
+load net {ACC1:acc#712.itm(0)} -pin  "ACC1:acc#714" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(1)} -pin  "ACC1:acc#714" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(2)} -pin  "ACC1:acc#714" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(3)} -pin  "ACC1:acc#714" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(4)} -pin  "ACC1:acc#714" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(5)} -pin  "ACC1:acc#714" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(6)} -pin  "ACC1:acc#714" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#712.itm(7)} -pin  "ACC1:acc#714" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#712.itm}
+load net {ACC1:acc#714.itm(0)} -pin  "ACC1:acc#714" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(1)} -pin  "ACC1:acc#714" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(2)} -pin  "ACC1:acc#714" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(3)} -pin  "ACC1:acc#714" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(4)} -pin  "ACC1:acc#714" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(5)} -pin  "ACC1:acc#714" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(6)} -pin  "ACC1:acc#714" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(7)} -pin  "ACC1:acc#714" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(8)} -pin  "ACC1:acc#714" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(9)} -pin  "ACC1:acc#714" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load inst "ACC1:acc#691" "add(3,1,2,1,4)" "INTERFACE" -attr xrf 64136 -attr oid 1326 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#691} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#691" {A(0)} -attr @path {/sobel/sobel:core/conc#901.itm}
+load net {acc#20.psp#2.sva(3)} -pin  "ACC1:acc#691" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#901.itm}
+load net {PWR} -pin  "ACC1:acc#691" {A(2)} -attr @path {/sobel/sobel:core/conc#901.itm}
+load net {acc#20.psp#2.sva(4)} -pin  "ACC1:acc#691" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1435.itm}
+load net {ACC1:acc#217.psp#2.sva(3)} -pin  "ACC1:acc#691" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1435.itm}
+load net {ACC1:acc#691.itm(0)} -pin  "ACC1:acc#691" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#691.itm}
+load net {ACC1:acc#691.itm(1)} -pin  "ACC1:acc#691" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#691.itm}
+load net {ACC1:acc#691.itm(2)} -pin  "ACC1:acc#691" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#691.itm}
+load net {ACC1:acc#691.itm(3)} -pin  "ACC1:acc#691" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#691.itm}
+load inst "ACC1:acc#700" "add(3,-1,2,1,3)" "INTERFACE" -attr xrf 64137 -attr oid 1327 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {ACC1:acc#691.itm(1)} -pin  "ACC1:acc#700" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#155.itm}
+load net {ACC1:acc#691.itm(2)} -pin  "ACC1:acc#700" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#155.itm}
+load net {ACC1:acc#691.itm(3)} -pin  "ACC1:acc#700" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#155.itm}
+load net {ACC1:acc#223.psp#1.sva(1)} -pin  "ACC1:acc#700" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp#1.sva)#2.itm}
+load net {ACC1:acc#223.psp#1.sva(2)} -pin  "ACC1:acc#700" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp#1.sva)#2.itm}
+load net {ACC1:acc#700.itm(0)} -pin  "ACC1:acc#700" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load net {ACC1:acc#700.itm(1)} -pin  "ACC1:acc#700" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load net {ACC1:acc#700.itm(2)} -pin  "ACC1:acc#700" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load inst "ACC1:acc#692" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 64138 -attr oid 1328 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#692" {A(0)} -attr @path {/sobel/sobel:core/conc#902.itm}
+load net {acc#20.psp#2.sva(1)} -pin  "ACC1:acc#692" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#902.itm}
+load net {acc#20.psp#2.sva(3)} -pin  "ACC1:acc#692" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#902.itm}
+load net {ACC1:acc#217.psp#2.sva(1)} -pin  "ACC1:acc#692" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1437.itm}
+load net {acc#20.psp#2.sva(2)} -pin  "ACC1:acc#692" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1437.itm}
+load net {ACC1:acc#217.psp#2.sva(3)} -pin  "ACC1:acc#692" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1437.itm}
+load net {ACC1:acc#692.itm(0)} -pin  "ACC1:acc#692" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692.itm}
+load net {ACC1:acc#692.itm(1)} -pin  "ACC1:acc#692" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692.itm}
+load net {ACC1:acc#692.itm(2)} -pin  "ACC1:acc#692" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692.itm}
+load net {ACC1:acc#692.itm(3)} -pin  "ACC1:acc#692" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692.itm}
+load net {ACC1:acc#692.itm(4)} -pin  "ACC1:acc#692" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#692.itm}
+load inst "ACC1:acc#705" "add(3,1,4,-1,4)" "INTERFACE" -attr xrf 64139 -attr oid 1329 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#700.itm(0)} -pin  "ACC1:acc#705" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load net {ACC1:acc#700.itm(1)} -pin  "ACC1:acc#705" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load net {ACC1:acc#700.itm(2)} -pin  "ACC1:acc#705" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#700.itm}
+load net {ACC1:acc#692.itm(1)} -pin  "ACC1:acc#705" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#156.itm}
+load net {ACC1:acc#692.itm(2)} -pin  "ACC1:acc#705" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#156.itm}
+load net {ACC1:acc#692.itm(3)} -pin  "ACC1:acc#705" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#156.itm}
+load net {ACC1:acc#692.itm(4)} -pin  "ACC1:acc#705" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#156.itm}
+load net {ACC1:acc#705.itm(0)} -pin  "ACC1:acc#705" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#705.itm(1)} -pin  "ACC1:acc#705" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#705.itm(2)} -pin  "ACC1:acc#705" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#705.itm(3)} -pin  "ACC1:acc#705" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load inst "ACC1:acc#704" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 64140 -attr oid 1330 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#704" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#594.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#704" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#594.itm}
+load net {acc#20.psp#2.sva(4)} -pin  "ACC1:acc#704" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#594.itm}
+load net {acc#20.psp#2.sva(7)} -pin  "ACC1:acc#704" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#594.itm}
+load net {ACC1:acc#699.cse(0)} -pin  "ACC1:acc#704" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#699.cse(1)} -pin  "ACC1:acc#704" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#699.cse(2)} -pin  "ACC1:acc#704" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#704.itm(0)} -pin  "ACC1:acc#704" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(1)} -pin  "ACC1:acc#704" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(2)} -pin  "ACC1:acc#704" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(3)} -pin  "ACC1:acc#704" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(4)} -pin  "ACC1:acc#704" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load inst "ACC1:acc#708" "add(4,1,5,0,6)" "INTERFACE" -attr xrf 64141 -attr oid 1331 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#705.itm(0)} -pin  "ACC1:acc#708" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#705.itm(1)} -pin  "ACC1:acc#708" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#705.itm(2)} -pin  "ACC1:acc#708" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#705.itm(3)} -pin  "ACC1:acc#708" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#705.itm}
+load net {ACC1:acc#704.itm(0)} -pin  "ACC1:acc#708" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(1)} -pin  "ACC1:acc#708" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(2)} -pin  "ACC1:acc#708" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(3)} -pin  "ACC1:acc#708" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#704.itm(4)} -pin  "ACC1:acc#708" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#704.itm}
+load net {ACC1:acc#708.itm(0)} -pin  "ACC1:acc#708" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(1)} -pin  "ACC1:acc#708" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(2)} -pin  "ACC1:acc#708" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(3)} -pin  "ACC1:acc#708" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(4)} -pin  "ACC1:acc#708" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(5)} -pin  "ACC1:acc#708" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load inst "ACC1:acc#711" "add(6,1,7,0,8)" "INTERFACE" -attr xrf 64142 -attr oid 1332 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#708.itm(0)} -pin  "ACC1:acc#711" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(1)} -pin  "ACC1:acc#711" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(2)} -pin  "ACC1:acc#711" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(3)} -pin  "ACC1:acc#711" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(4)} -pin  "ACC1:acc#711" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {ACC1:acc#708.itm(5)} -pin  "ACC1:acc#711" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#708.itm}
+load net {acc#20.psp#2.sva(8)} -pin  "ACC1:acc#711" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {GND} -pin  "ACC1:acc#711" {B(1)} -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {acc#20.psp#2.sva(8)} -pin  "ACC1:acc#711" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {GND} -pin  "ACC1:acc#711" {B(3)} -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {acc#20.psp#2.sva(8)} -pin  "ACC1:acc#711" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {GND} -pin  "ACC1:acc#711" {B(5)} -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {acc#20.psp#2.sva(8)} -pin  "ACC1:acc#711" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#903.itm}
+load net {ACC1:acc#711.itm(0)} -pin  "ACC1:acc#711" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(1)} -pin  "ACC1:acc#711" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(2)} -pin  "ACC1:acc#711" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(3)} -pin  "ACC1:acc#711" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(4)} -pin  "ACC1:acc#711" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(5)} -pin  "ACC1:acc#711" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(6)} -pin  "ACC1:acc#711" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(7)} -pin  "ACC1:acc#711" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load inst "ACC1-1:not#156" "not(1)" "INTERFACE" -attr xrf 64143 -attr oid 1333 -attr @path {/sobel/sobel:core/ACC1-1:not#156} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#359.itm(2)} -pin  "ACC1-1:not#156" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#40.sva).itm}
+load net {ACC1-1:not#156.itm} -pin  "ACC1-1:not#156" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#156.itm}
+load inst "ACC1-1:and#9" "and(3,1)" "INTERFACE" -attr xrf 64144 -attr oid 1334 -attr @path {/sobel/sobel:core/ACC1-1:and#9} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:and#9" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#37.itm}
+load net {ACC1-1:not#156.itm} -pin  "ACC1-1:and#9" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#156.itm}
+load net {ACC1:acc#359.itm(1)} -pin  "ACC1-1:and#9" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#40.sva)#1.itm}
+load net {ACC1-1:and#9.itm} -pin  "ACC1-1:and#9" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#9.itm}
+load inst "ACC1:acc#697" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64145 -attr oid 1335 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#697} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#697" {A(0)} -attr @path {/sobel/sobel:core/exs#91.itm}
+load net {acc#20.psp#2.sva(7)} -pin  "ACC1:acc#697" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#91.itm}
+load net {acc#20.psp#2.sva(7)} -pin  "ACC1:acc#697" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#91.itm}
+load net {ACC1-1:and#9.itm} -pin  "ACC1:acc#697" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1493.itm}
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1:acc#697" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1493.itm}
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1:acc#697" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1493.itm}
+load net {ACC1:acc#697.itm(0)} -pin  "ACC1:acc#697" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#697.itm}
+load net {ACC1:acc#697.itm(1)} -pin  "ACC1:acc#697" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#697.itm}
+load net {ACC1:acc#697.itm(2)} -pin  "ACC1:acc#697" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#697.itm}
+load net {ACC1:acc#697.itm(3)} -pin  "ACC1:acc#697" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#697.itm}
+load inst "ACC1:acc#703" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64146 -attr oid 1336 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#699.cse(0)} -pin  "ACC1:acc#703" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#699.cse(1)} -pin  "ACC1:acc#703" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#699.cse(2)} -pin  "ACC1:acc#703" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#697.itm(1)} -pin  "ACC1:acc#703" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#161.itm}
+load net {ACC1:acc#697.itm(2)} -pin  "ACC1:acc#703" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#161.itm}
+load net {ACC1:acc#697.itm(3)} -pin  "ACC1:acc#703" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#161.itm}
+load net {ACC1:acc#703.itm(0)} -pin  "ACC1:acc#703" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#703.itm(1)} -pin  "ACC1:acc#703" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#703.itm(2)} -pin  "ACC1:acc#703" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#703.itm(3)} -pin  "ACC1:acc#703" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load inst "ACC1:acc#707" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 64147 -attr oid 1337 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {acc#20.psp#2.sva(6)} -pin  "ACC1:acc#707" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#904.itm}
+load net {GND} -pin  "ACC1:acc#707" {A(1)} -attr @path {/sobel/sobel:core/conc#904.itm}
+load net {acc#20.psp#2.sva(6)} -pin  "ACC1:acc#707" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#904.itm}
+load net {GND} -pin  "ACC1:acc#707" {A(3)} -attr @path {/sobel/sobel:core/conc#904.itm}
+load net {acc#20.psp#2.sva(6)} -pin  "ACC1:acc#707" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#904.itm}
+load net {ACC1:acc#703.itm(0)} -pin  "ACC1:acc#707" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#703.itm(1)} -pin  "ACC1:acc#707" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#703.itm(2)} -pin  "ACC1:acc#707" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#703.itm(3)} -pin  "ACC1:acc#707" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#703.itm}
+load net {ACC1:acc#707.itm(0)} -pin  "ACC1:acc#707" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(1)} -pin  "ACC1:acc#707" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(2)} -pin  "ACC1:acc#707" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(3)} -pin  "ACC1:acc#707" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(4)} -pin  "ACC1:acc#707" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(5)} -pin  "ACC1:acc#707" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load inst "ACC1:acc#710" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 64148 -attr oid 1338 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#710" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1040.itm}
+load net {ACC1:acc#707.itm(0)} -pin  "ACC1:acc#710" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(1)} -pin  "ACC1:acc#710" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(2)} -pin  "ACC1:acc#710" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(3)} -pin  "ACC1:acc#710" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(4)} -pin  "ACC1:acc#710" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#707.itm(5)} -pin  "ACC1:acc#710" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#707.itm}
+load net {ACC1:acc#710.itm(0)} -pin  "ACC1:acc#710" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(1)} -pin  "ACC1:acc#710" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(2)} -pin  "ACC1:acc#710" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(3)} -pin  "ACC1:acc#710" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(4)} -pin  "ACC1:acc#710" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(5)} -pin  "ACC1:acc#710" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(6)} -pin  "ACC1:acc#710" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(7)} -pin  "ACC1:acc#710" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load inst "ACC1:acc#713" "add(8,1,8,0,10)" "INTERFACE" -attr xrf 64149 -attr oid 1339 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#711.itm(0)} -pin  "ACC1:acc#713" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(1)} -pin  "ACC1:acc#713" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(2)} -pin  "ACC1:acc#713" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(3)} -pin  "ACC1:acc#713" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(4)} -pin  "ACC1:acc#713" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(5)} -pin  "ACC1:acc#713" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(6)} -pin  "ACC1:acc#713" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#711.itm(7)} -pin  "ACC1:acc#713" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#711.itm}
+load net {ACC1:acc#710.itm(0)} -pin  "ACC1:acc#713" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(1)} -pin  "ACC1:acc#713" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(2)} -pin  "ACC1:acc#713" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(3)} -pin  "ACC1:acc#713" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(4)} -pin  "ACC1:acc#713" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(5)} -pin  "ACC1:acc#713" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(6)} -pin  "ACC1:acc#713" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#710.itm(7)} -pin  "ACC1:acc#713" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#710.itm}
+load net {ACC1:acc#713.itm(0)} -pin  "ACC1:acc#713" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(1)} -pin  "ACC1:acc#713" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(2)} -pin  "ACC1:acc#713" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(3)} -pin  "ACC1:acc#713" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(4)} -pin  "ACC1:acc#713" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(5)} -pin  "ACC1:acc#713" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(6)} -pin  "ACC1:acc#713" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(7)} -pin  "ACC1:acc#713" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(8)} -pin  "ACC1:acc#713" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(9)} -pin  "ACC1:acc#713" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load inst "ACC1:acc#716" "add(10,0,10,1,11)" "INTERFACE" -attr xrf 64150 -attr oid 1340 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,12)"
+load net {ACC1:acc#714.itm(0)} -pin  "ACC1:acc#716" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(1)} -pin  "ACC1:acc#716" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(2)} -pin  "ACC1:acc#716" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(3)} -pin  "ACC1:acc#716" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(4)} -pin  "ACC1:acc#716" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(5)} -pin  "ACC1:acc#716" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(6)} -pin  "ACC1:acc#716" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(7)} -pin  "ACC1:acc#716" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(8)} -pin  "ACC1:acc#716" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#714.itm(9)} -pin  "ACC1:acc#716" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#714.itm}
+load net {ACC1:acc#713.itm(0)} -pin  "ACC1:acc#716" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(1)} -pin  "ACC1:acc#716" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(2)} -pin  "ACC1:acc#716" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(3)} -pin  "ACC1:acc#716" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(4)} -pin  "ACC1:acc#716" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(5)} -pin  "ACC1:acc#716" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(6)} -pin  "ACC1:acc#716" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(7)} -pin  "ACC1:acc#716" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(8)} -pin  "ACC1:acc#716" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#713.itm(9)} -pin  "ACC1:acc#716" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#713.itm}
+load net {ACC1:acc#716.itm(0)} -pin  "ACC1:acc#716" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(1)} -pin  "ACC1:acc#716" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(2)} -pin  "ACC1:acc#716" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(3)} -pin  "ACC1:acc#716" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(4)} -pin  "ACC1:acc#716" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(5)} -pin  "ACC1:acc#716" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(6)} -pin  "ACC1:acc#716" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(7)} -pin  "ACC1:acc#716" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(8)} -pin  "ACC1:acc#716" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(9)} -pin  "ACC1:acc#716" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(10)} -pin  "ACC1:acc#716" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load inst "ACC1:acc#720" "add(1,0,2,0,3)" "INTERFACE" -attr xrf 64151 -attr oid 1341 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#720} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,3)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#720" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#13.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#720" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1654.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#720" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1654.itm}
+load net {ACC1:acc#720.itm(0)} -pin  "ACC1:acc#720" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#720.itm}
+load net {ACC1:acc#720.itm(1)} -pin  "ACC1:acc#720" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#720.itm}
+load net {ACC1:acc#720.itm(2)} -pin  "ACC1:acc#720" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#720.itm}
+load inst "ACC1-1:acc#27" "add(11,-1,11,-1,11)" "INTERFACE" -attr xrf 64152 -attr oid 1342 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#716.itm(0)} -pin  "ACC1-1:acc#27" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(1)} -pin  "ACC1-1:acc#27" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(2)} -pin  "ACC1-1:acc#27" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(3)} -pin  "ACC1-1:acc#27" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(4)} -pin  "ACC1-1:acc#27" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(5)} -pin  "ACC1-1:acc#27" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(6)} -pin  "ACC1-1:acc#27" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(7)} -pin  "ACC1-1:acc#27" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(8)} -pin  "ACC1-1:acc#27" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(9)} -pin  "ACC1-1:acc#27" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#716.itm(10)} -pin  "ACC1-1:acc#27" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#716.itm}
+load net {ACC1:acc#720.itm(0)} -pin  "ACC1-1:acc#27" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {ACC1:acc#720.itm(1)} -pin  "ACC1-1:acc#27" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {ACC1:acc#720.itm(2)} -pin  "ACC1-1:acc#27" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:acc#27" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {GND} -pin  "ACC1-1:acc#27" {B(4)} -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:acc#27" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {GND} -pin  "ACC1-1:acc#27" {B(6)} -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:acc#27" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {GND} -pin  "ACC1-1:acc#27" {B(8)} -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {GND} -pin  "ACC1-1:acc#27" {B(9)} -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:acc#27" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#907.itm}
+load net {ACC1-1:acc#27.itm(0)} -pin  "ACC1-1:acc#27" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(1)} -pin  "ACC1-1:acc#27" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(2)} -pin  "ACC1-1:acc#27" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(3)} -pin  "ACC1-1:acc#27" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(4)} -pin  "ACC1-1:acc#27" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(5)} -pin  "ACC1-1:acc#27" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(6)} -pin  "ACC1-1:acc#27" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(7)} -pin  "ACC1-1:acc#27" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(8)} -pin  "ACC1-1:acc#27" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(9)} -pin  "ACC1-1:acc#27" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(10)} -pin  "ACC1-1:acc#27" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load inst "ACC1:acc#653" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 64153 -attr oid 1343 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1-1:acc#2.itm(0)} -pin  "ACC1:acc#653" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(1)} -pin  "ACC1:acc#653" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(2)} -pin  "ACC1:acc#653" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(3)} -pin  "ACC1:acc#653" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(4)} -pin  "ACC1:acc#653" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(5)} -pin  "ACC1:acc#653" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(6)} -pin  "ACC1:acc#653" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(7)} -pin  "ACC1:acc#653" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(8)} -pin  "ACC1:acc#653" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(9)} -pin  "ACC1:acc#653" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#2.itm(10)} -pin  "ACC1:acc#653" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#2.itm}
+load net {ACC1-1:acc#27.itm(0)} -pin  "ACC1:acc#653" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(1)} -pin  "ACC1:acc#653" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(2)} -pin  "ACC1:acc#653" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(3)} -pin  "ACC1:acc#653" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(4)} -pin  "ACC1:acc#653" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(5)} -pin  "ACC1:acc#653" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(6)} -pin  "ACC1:acc#653" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(7)} -pin  "ACC1:acc#653" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(8)} -pin  "ACC1:acc#653" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(9)} -pin  "ACC1:acc#653" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1-1:acc#27.itm(10)} -pin  "ACC1:acc#653" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#27.itm}
+load net {ACC1:acc#653.itm(0)} -pin  "ACC1:acc#653" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(1)} -pin  "ACC1:acc#653" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(2)} -pin  "ACC1:acc#653" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(3)} -pin  "ACC1:acc#653" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(4)} -pin  "ACC1:acc#653" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(5)} -pin  "ACC1:acc#653" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(6)} -pin  "ACC1:acc#653" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(7)} -pin  "ACC1:acc#653" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(8)} -pin  "ACC1:acc#653" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(9)} -pin  "ACC1:acc#653" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(10)} -pin  "ACC1:acc#653" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(11)} -pin  "ACC1:acc#653" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load inst "ACC1:acc#659" "add(12,1,12,1,13)" "INTERFACE" -attr xrf 64154 -attr oid 1344 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1:acc#654.itm(0)} -pin  "ACC1:acc#659" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(1)} -pin  "ACC1:acc#659" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(2)} -pin  "ACC1:acc#659" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(3)} -pin  "ACC1:acc#659" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(4)} -pin  "ACC1:acc#659" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(5)} -pin  "ACC1:acc#659" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(6)} -pin  "ACC1:acc#659" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(7)} -pin  "ACC1:acc#659" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(8)} -pin  "ACC1:acc#659" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(9)} -pin  "ACC1:acc#659" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(10)} -pin  "ACC1:acc#659" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#654.itm(11)} -pin  "ACC1:acc#659" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#654.itm}
+load net {ACC1:acc#653.itm(0)} -pin  "ACC1:acc#659" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(1)} -pin  "ACC1:acc#659" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(2)} -pin  "ACC1:acc#659" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(3)} -pin  "ACC1:acc#659" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(4)} -pin  "ACC1:acc#659" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(5)} -pin  "ACC1:acc#659" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(6)} -pin  "ACC1:acc#659" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(7)} -pin  "ACC1:acc#659" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(8)} -pin  "ACC1:acc#659" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(9)} -pin  "ACC1:acc#659" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(10)} -pin  "ACC1:acc#659" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#653.itm(11)} -pin  "ACC1:acc#659" {B(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#653.itm}
+load net {ACC1:acc#659.itm(0)} -pin  "ACC1:acc#659" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(1)} -pin  "ACC1:acc#659" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(2)} -pin  "ACC1:acc#659" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(3)} -pin  "ACC1:acc#659" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(4)} -pin  "ACC1:acc#659" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(5)} -pin  "ACC1:acc#659" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(6)} -pin  "ACC1:acc#659" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(7)} -pin  "ACC1:acc#659" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(8)} -pin  "ACC1:acc#659" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(9)} -pin  "ACC1:acc#659" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(10)} -pin  "ACC1:acc#659" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(11)} -pin  "ACC1:acc#659" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(12)} -pin  "ACC1:acc#659" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load inst "reg(ACC1:acc#659.itm#1)" "reg(13,1,1,-1,0)" "INTERFACE" -attr xrf 64155 -attr oid 1345 -attr vt dc -attr @path {/sobel/sobel:core/reg(ACC1:acc#659.itm#1)}
+load net {ACC1:acc#659.itm(0)} -pin  "reg(ACC1:acc#659.itm#1)" {D(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(1)} -pin  "reg(ACC1:acc#659.itm#1)" {D(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(2)} -pin  "reg(ACC1:acc#659.itm#1)" {D(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(3)} -pin  "reg(ACC1:acc#659.itm#1)" {D(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(4)} -pin  "reg(ACC1:acc#659.itm#1)" {D(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(5)} -pin  "reg(ACC1:acc#659.itm#1)" {D(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(6)} -pin  "reg(ACC1:acc#659.itm#1)" {D(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(7)} -pin  "reg(ACC1:acc#659.itm#1)" {D(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(8)} -pin  "reg(ACC1:acc#659.itm#1)" {D(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(9)} -pin  "reg(ACC1:acc#659.itm#1)" {D(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(10)} -pin  "reg(ACC1:acc#659.itm#1)" {D(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(11)} -pin  "reg(ACC1:acc#659.itm#1)" {D(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {ACC1:acc#659.itm(12)} -pin  "reg(ACC1:acc#659.itm#1)" {D(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#659.itm}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#659.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_13}
+load net {clk} -pin  "reg(ACC1:acc#659.itm#1)" {clk} -attr xrf 64156 -attr oid 1346 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#659.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#659.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#659.itm#1(0)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(1)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(2)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(3)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(4)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(5)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(6)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(7)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(8)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(9)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(10)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(11)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(12)} -pin  "reg(ACC1:acc#659.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load inst "ACC1:acc#572" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64157 -attr oid 1347 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#572" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1108.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#572" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1108.itm}
+load net {ACC1:acc#228.psp.sva(3)} -pin  "ACC1:acc#572" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1108.itm}
+load net {ACC1:acc#224.psp#1.sva(6)} -pin  "ACC1:acc#572" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1108.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#572" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1109.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#572" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1109.itm}
+load net {ACC1:acc#226.psp.sva(3)} -pin  "ACC1:acc#572" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1109.itm}
+load net {ACC1-1:acc#25.psp.sva(5)} -pin  "ACC1:acc#572" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1109.itm}
+load net {ACC1:acc#572.itm(0)} -pin  "ACC1:acc#572" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(1)} -pin  "ACC1:acc#572" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(2)} -pin  "ACC1:acc#572" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(3)} -pin  "ACC1:acc#572" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(4)} -pin  "ACC1:acc#572" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load inst "ACC1:acc#571" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64158 -attr oid 1348 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#571" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1110.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#571" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1110.itm}
+load net {ACC1:acc#224.psp#1.sva(3)} -pin  "ACC1:acc#571" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1110.itm}
+load net {ACC1-1:acc#25.psp.sva(7)} -pin  "ACC1:acc#571" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1110.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#571" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1111.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#571" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1111.itm}
+load net {ACC1-1:acc#25.psp.sva(4)} -pin  "ACC1:acc#571" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1111.itm}
+load net {acc#20.psp#1.sva(4)} -pin  "ACC1:acc#571" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1111.itm}
+load net {ACC1:acc#571.itm(0)} -pin  "ACC1:acc#571" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(1)} -pin  "ACC1:acc#571" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(2)} -pin  "ACC1:acc#571" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(3)} -pin  "ACC1:acc#571" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(4)} -pin  "ACC1:acc#571" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load inst "ACC1:acc#601" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 64159 -attr oid 1349 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#572.itm(0)} -pin  "ACC1:acc#601" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(1)} -pin  "ACC1:acc#601" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(2)} -pin  "ACC1:acc#601" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(3)} -pin  "ACC1:acc#601" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#572.itm(4)} -pin  "ACC1:acc#601" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#572.itm}
+load net {ACC1:acc#571.itm(0)} -pin  "ACC1:acc#601" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(1)} -pin  "ACC1:acc#601" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(2)} -pin  "ACC1:acc#601" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(3)} -pin  "ACC1:acc#601" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#571.itm(4)} -pin  "ACC1:acc#601" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#571.itm}
+load net {ACC1:acc#601.itm(0)} -pin  "ACC1:acc#601" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(1)} -pin  "ACC1:acc#601" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(2)} -pin  "ACC1:acc#601" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(3)} -pin  "ACC1:acc#601" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(4)} -pin  "ACC1:acc#601" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(5)} -pin  "ACC1:acc#601" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load inst "ACC1:not#383" "not(1)" "INTERFACE" -attr xrf 64160 -attr oid 1350 -attr @path {/sobel/sobel:core/ACC1:not#383} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#217.psp#1.sva(3)} -pin  "ACC1:not#383" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#217.psp#1.sva)#8.itm}
+load net {ACC1:not#383.itm} -pin  "ACC1:not#383" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#383.itm}
+load inst "ACC1:not#384" "not(1)" "INTERFACE" -attr xrf 64161 -attr oid 1351 -attr @path {/sobel/sobel:core/ACC1:not#384} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#210.psp#1.sva(3)} -pin  "ACC1:not#384" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#210.psp#1.sva)#8.itm}
+load net {ACC1:not#384.itm} -pin  "ACC1:not#384" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#384.itm}
+load inst "ACC1:not#388" "not(1)" "INTERFACE" -attr xrf 64162 -attr oid 1352 -attr @path {/sobel/sobel:core/ACC1:not#388} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#367.itm(3)} -pin  "ACC1:not#388" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#42.sva)#4.itm}
+load net {ACC1:not#388.itm} -pin  "ACC1:not#388" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#388.itm}
+load inst "ACC1:acc#570" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64163 -attr oid 1353 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:not#388.itm} -pin  "ACC1:acc#570" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#908.itm}
+load net {PWR} -pin  "ACC1:acc#570" {A(1)} -attr @path {/sobel/sobel:core/conc#908.itm}
+load net {ACC1:not#384.itm} -pin  "ACC1:acc#570" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#908.itm}
+load net {ACC1:not#383.itm} -pin  "ACC1:acc#570" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#908.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#570" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1113.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#570" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1113.itm}
+load net {acc#20.psp#1.sva(3)} -pin  "ACC1:acc#570" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1113.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#570" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1113.itm}
+load net {ACC1:acc#570.itm(0)} -pin  "ACC1:acc#570" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(1)} -pin  "ACC1:acc#570" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(2)} -pin  "ACC1:acc#570" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(3)} -pin  "ACC1:acc#570" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(4)} -pin  "ACC1:acc#570" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load inst "ACC1-3:not#156" "not(1)" "INTERFACE" -attr xrf 64164 -attr oid 1354 -attr @path {/sobel/sobel:core/ACC1-3:not#156} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#424.itm(2)} -pin  "ACC1-3:not#156" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#19.sva).itm}
+load net {ACC1-3:not#156.itm} -pin  "ACC1-3:not#156" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#156.itm}
+load inst "ACC1-3:and#9" "and(3,1)" "INTERFACE" -attr xrf 64165 -attr oid 1355 -attr @path {/sobel/sobel:core/ACC1-3:and#9} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1-3:and#9" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#1.itm}
+load net {ACC1-3:not#156.itm} -pin  "ACC1-3:and#9" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#156.itm}
+load net {ACC1:acc#424.itm(1)} -pin  "ACC1-3:and#9" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#19.sva)#1.itm}
+load net {ACC1-3:and#9.itm} -pin  "ACC1-3:and#9" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#9.itm}
+load inst "ACC1:acc#425" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64166 -attr oid 1356 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#425} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#425" {A(0)} -attr @path {/sobel/sobel:core/conc#909.itm}
+load net {ACC1:acc#224.psp#1.sva(1)} -pin  "ACC1:acc#425" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#909.itm}
+load net {ACC1-3:and#9.itm} -pin  "ACC1:acc#425" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#909.itm}
+load net {ACC1-1:acc#25.psp.sva(2)} -pin  "ACC1:acc#425" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1309.itm}
+load net {ACC1:acc#224.psp#1.sva(2)} -pin  "ACC1:acc#425" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1309.itm}
+load net {acc.psp#2.sva(3)} -pin  "ACC1:acc#425" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1309.itm}
+load net {ACC1:acc#425.itm(0)} -pin  "ACC1:acc#425" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#425.itm}
+load net {ACC1:acc#425.itm(1)} -pin  "ACC1:acc#425" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#425.itm}
+load net {ACC1:acc#425.itm(2)} -pin  "ACC1:acc#425" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#425.itm}
+load net {ACC1:acc#425.itm(3)} -pin  "ACC1:acc#425" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#425.itm}
+load inst "ACC1:acc#524" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 64167 -attr oid 1357 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#425.itm(1)} -pin  "ACC1:acc#524" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#425.itm(2)} -pin  "ACC1:acc#524" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#425.itm(3)} -pin  "ACC1:acc#524" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#224.psp#1.sva(3)} -pin  "ACC1:acc#524" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1097.itm}
+load net {ACC1:acc#223.psp.sva(1)} -pin  "ACC1:acc#524" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1097.itm}
+load net {ACC1:acc#223.psp.sva(2)} -pin  "ACC1:acc#524" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1097.itm}
+load net {ACC1:acc#524.itm(0)} -pin  "ACC1:acc#524" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(1)} -pin  "ACC1:acc#524" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(2)} -pin  "ACC1:acc#524" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(3)} -pin  "ACC1:acc#524" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(4)} -pin  "ACC1:acc#524" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load inst "ACC1:acc#600" "add(5,0,5,1,6)" "INTERFACE" -attr xrf 64168 -attr oid 1358 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#570.itm(0)} -pin  "ACC1:acc#600" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(1)} -pin  "ACC1:acc#600" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(2)} -pin  "ACC1:acc#600" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(3)} -pin  "ACC1:acc#600" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#570.itm(4)} -pin  "ACC1:acc#600" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#570.itm}
+load net {ACC1:acc#524.itm(0)} -pin  "ACC1:acc#600" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(1)} -pin  "ACC1:acc#600" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(2)} -pin  "ACC1:acc#600" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(3)} -pin  "ACC1:acc#600" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#524.itm(4)} -pin  "ACC1:acc#600" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#524.itm}
+load net {ACC1:acc#600.itm(0)} -pin  "ACC1:acc#600" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(1)} -pin  "ACC1:acc#600" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(2)} -pin  "ACC1:acc#600" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(3)} -pin  "ACC1:acc#600" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(4)} -pin  "ACC1:acc#600" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(5)} -pin  "ACC1:acc#600" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load inst "ACC1:acc#620" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 64169 -attr oid 1359 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#601.itm(0)} -pin  "ACC1:acc#620" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(1)} -pin  "ACC1:acc#620" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(2)} -pin  "ACC1:acc#620" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(3)} -pin  "ACC1:acc#620" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(4)} -pin  "ACC1:acc#620" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#601.itm(5)} -pin  "ACC1:acc#620" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#601.itm}
+load net {ACC1:acc#600.itm(0)} -pin  "ACC1:acc#620" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(1)} -pin  "ACC1:acc#620" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(2)} -pin  "ACC1:acc#620" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(3)} -pin  "ACC1:acc#620" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(4)} -pin  "ACC1:acc#620" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#600.itm(5)} -pin  "ACC1:acc#620" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#600.itm}
+load net {ACC1:acc#620.itm(0)} -pin  "ACC1:acc#620" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(1)} -pin  "ACC1:acc#620" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(2)} -pin  "ACC1:acc#620" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(3)} -pin  "ACC1:acc#620" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(4)} -pin  "ACC1:acc#620" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(5)} -pin  "ACC1:acc#620" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(6)} -pin  "ACC1:acc#620" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load inst "ACC1:acc#443" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 64170 -attr oid 1360 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#443" {A(0)} -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#443" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#443" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {ACC1:acc#377.itm(2)} -pin  "ACC1:acc#443" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1345.itm}
+load net {ACC1:acc#220.psp#1.sva(1)} -pin  "ACC1:acc#443" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1345.itm}
+load net {ACC1:acc#220.psp#1.sva(2)} -pin  "ACC1:acc#443" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1345.itm}
+load net {ACC1:acc#443.itm(0)} -pin  "ACC1:acc#443" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443.itm}
+load net {ACC1:acc#443.itm(1)} -pin  "ACC1:acc#443" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443.itm}
+load net {ACC1:acc#443.itm(2)} -pin  "ACC1:acc#443" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443.itm}
+load net {ACC1:acc#443.itm(3)} -pin  "ACC1:acc#443" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443.itm}
+load net {ACC1:acc#443.itm(4)} -pin  "ACC1:acc#443" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#443.itm}
+load inst "ACC1:acc#573" "add(4,1,4,0,6)" "INTERFACE" -attr xrf 64171 -attr oid 1361 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#443.itm(1)} -pin  "ACC1:acc#573" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#111.itm}
+load net {ACC1:acc#443.itm(2)} -pin  "ACC1:acc#573" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#111.itm}
+load net {ACC1:acc#443.itm(3)} -pin  "ACC1:acc#573" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#111.itm}
+load net {ACC1:acc#443.itm(4)} -pin  "ACC1:acc#573" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#111.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#573" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1107.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#573" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1107.itm}
+load net {ACC1:acc#224.psp.sva(3)} -pin  "ACC1:acc#573" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1107.itm}
+load net {ACC1:acc#224.psp#1.sva(4)} -pin  "ACC1:acc#573" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1107.itm}
+load net {ACC1:acc#573.itm(0)} -pin  "ACC1:acc#573" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(1)} -pin  "ACC1:acc#573" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(2)} -pin  "ACC1:acc#573" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(3)} -pin  "ACC1:acc#573" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(4)} -pin  "ACC1:acc#573" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(5)} -pin  "ACC1:acc#573" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load inst "ACC1:acc#519" "add(2,1,2,1,3)" "INTERFACE" -attr xrf 64172 -attr oid 1362 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,1,2,1,3)"
+load net {ACC1:acc#220.psp.sva(1)} -pin  "ACC1:acc#519" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp.sva)#2.itm}
+load net {ACC1:acc#220.psp.sva(2)} -pin  "ACC1:acc#519" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp.sva)#2.itm}
+load net {ACC1:acc#222.psp.sva(1)} -pin  "ACC1:acc#519" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp.sva)#2.itm}
+load net {ACC1:acc#222.psp.sva(2)} -pin  "ACC1:acc#519" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp.sva)#2.itm}
+load net {ACC1:acc#519.itm(0)} -pin  "ACC1:acc#519" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load net {ACC1:acc#519.itm(1)} -pin  "ACC1:acc#519" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load net {ACC1:acc#519.itm(2)} -pin  "ACC1:acc#519" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load inst "ACC1:acc#569" "add(4,0,3,1,6)" "INTERFACE" -attr xrf 64173 -attr oid 1363 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#228.psp.sva(6)} -pin  "ACC1:acc#569" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1114.itm}
+load net {ACC1:acc#228.psp.sva(6)} -pin  "ACC1:acc#569" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1114.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#569" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1114.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#569" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1114.itm}
+load net {ACC1:acc#519.itm(0)} -pin  "ACC1:acc#569" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load net {ACC1:acc#519.itm(1)} -pin  "ACC1:acc#569" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load net {ACC1:acc#519.itm(2)} -pin  "ACC1:acc#569" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#519.itm}
+load net {ACC1:acc#569.itm(0)} -pin  "ACC1:acc#569" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(1)} -pin  "ACC1:acc#569" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(2)} -pin  "ACC1:acc#569" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(3)} -pin  "ACC1:acc#569" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(4)} -pin  "ACC1:acc#569" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(5)} -pin  "ACC1:acc#569" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load inst "ACC1:acc#619" "add(6,1,6,1,7)" "INTERFACE" -attr xrf 64174 -attr oid 1364 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,1,6,1,7)"
+load net {ACC1:acc#573.itm(0)} -pin  "ACC1:acc#619" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(1)} -pin  "ACC1:acc#619" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(2)} -pin  "ACC1:acc#619" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(3)} -pin  "ACC1:acc#619" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(4)} -pin  "ACC1:acc#619" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#573.itm(5)} -pin  "ACC1:acc#619" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#573.itm}
+load net {ACC1:acc#569.itm(0)} -pin  "ACC1:acc#619" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(1)} -pin  "ACC1:acc#619" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(2)} -pin  "ACC1:acc#619" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(3)} -pin  "ACC1:acc#619" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(4)} -pin  "ACC1:acc#619" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#569.itm(5)} -pin  "ACC1:acc#619" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#569.itm}
+load net {ACC1:acc#619.itm(0)} -pin  "ACC1:acc#619" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(1)} -pin  "ACC1:acc#619" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(2)} -pin  "ACC1:acc#619" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(3)} -pin  "ACC1:acc#619" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(4)} -pin  "ACC1:acc#619" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(5)} -pin  "ACC1:acc#619" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(6)} -pin  "ACC1:acc#619" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load inst "ACC1:acc#635" "add(7,0,7,1,9)" "INTERFACE" -attr xrf 64175 -attr oid 1365 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#620.itm(0)} -pin  "ACC1:acc#635" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(1)} -pin  "ACC1:acc#635" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(2)} -pin  "ACC1:acc#635" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(3)} -pin  "ACC1:acc#635" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(4)} -pin  "ACC1:acc#635" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(5)} -pin  "ACC1:acc#635" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#620.itm(6)} -pin  "ACC1:acc#635" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#620.itm}
+load net {ACC1:acc#619.itm(0)} -pin  "ACC1:acc#635" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(1)} -pin  "ACC1:acc#635" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(2)} -pin  "ACC1:acc#635" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(3)} -pin  "ACC1:acc#635" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(4)} -pin  "ACC1:acc#635" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(5)} -pin  "ACC1:acc#635" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#619.itm(6)} -pin  "ACC1:acc#635" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#619.itm}
+load net {ACC1:acc#635.itm(0)} -pin  "ACC1:acc#635" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(1)} -pin  "ACC1:acc#635" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(2)} -pin  "ACC1:acc#635" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(3)} -pin  "ACC1:acc#635" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(4)} -pin  "ACC1:acc#635" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(5)} -pin  "ACC1:acc#635" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(6)} -pin  "ACC1:acc#635" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(7)} -pin  "ACC1:acc#635" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(8)} -pin  "ACC1:acc#635" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load inst "ACC1:acc#646" "add(9,1,9,0,10)" "INTERFACE" -attr xrf 64176 -attr oid 1366 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,11)"
+load net {ACC1:acc#635.itm(0)} -pin  "ACC1:acc#646" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(1)} -pin  "ACC1:acc#646" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(2)} -pin  "ACC1:acc#646" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(3)} -pin  "ACC1:acc#646" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(4)} -pin  "ACC1:acc#646" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(5)} -pin  "ACC1:acc#646" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(6)} -pin  "ACC1:acc#646" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(7)} -pin  "ACC1:acc#646" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#635.itm(8)} -pin  "ACC1:acc#646" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#635.itm}
+load net {ACC1:acc#224.psp.sva(6)} -pin  "ACC1:acc#646" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {ACC1:acc#224.psp.sva(6)} -pin  "ACC1:acc#646" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {GND} -pin  "ACC1:acc#646" {B(2)} -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {ACC1:acc#228.psp.sva(4)} -pin  "ACC1:acc#646" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#646" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {GND} -pin  "ACC1:acc#646" {B(5)} -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#646" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {GND} -pin  "ACC1:acc#646" {B(7)} -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#646" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#911.itm}
+load net {ACC1:acc#646.itm(0)} -pin  "ACC1:acc#646" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(1)} -pin  "ACC1:acc#646" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(2)} -pin  "ACC1:acc#646" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(3)} -pin  "ACC1:acc#646" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(4)} -pin  "ACC1:acc#646" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(5)} -pin  "ACC1:acc#646" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(6)} -pin  "ACC1:acc#646" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(7)} -pin  "ACC1:acc#646" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(8)} -pin  "ACC1:acc#646" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(9)} -pin  "ACC1:acc#646" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load inst "ACC1:acc#308" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 64177 -attr oid 1367 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#227.psp.sva(8)} -pin  "ACC1:acc#308" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#21.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#308" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#44.itm}
+load net {ACC1:acc#308.itm(0)} -pin  "ACC1:acc#308" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#308.itm(1)} -pin  "ACC1:acc#308" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load inst "ACC1:acc#307" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 64178 -attr oid 1368 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#308.itm(0)} -pin  "ACC1:acc#307" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#308.itm(1)} -pin  "ACC1:acc#307" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#224.psp.sva(7)} -pin  "ACC1:acc#307" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#43.itm}
+load net {ACC1:acc#307.itm(0)} -pin  "ACC1:acc#307" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#307.itm(1)} -pin  "ACC1:acc#307" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load inst "ACC1:acc#306" "add(2,0,1,0,3)" "INTERFACE" -attr xrf 64179 -attr oid 1369 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#307.itm(0)} -pin  "ACC1:acc#306" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#307.itm(1)} -pin  "ACC1:acc#306" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#228.psp.sva(7)} -pin  "ACC1:acc#306" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#18.itm}
+load net {ACC1:acc#306.itm(0)} -pin  "ACC1:acc#306" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(1)} -pin  "ACC1:acc#306" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(2)} -pin  "ACC1:acc#306" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load inst "ACC1:acc#305" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 64180 -attr oid 1370 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#306.itm(0)} -pin  "ACC1:acc#305" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(1)} -pin  "ACC1:acc#305" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(2)} -pin  "ACC1:acc#305" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#226.psp.sva(7)} -pin  "ACC1:acc#305" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#13.itm}
+load net {ACC1:acc#305.itm(0)} -pin  "ACC1:acc#305" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(1)} -pin  "ACC1:acc#305" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(2)} -pin  "ACC1:acc#305" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load inst "ACC1:acc#304" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 64181 -attr oid 1371 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#305.itm(0)} -pin  "ACC1:acc#304" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(1)} -pin  "ACC1:acc#304" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(2)} -pin  "ACC1:acc#304" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#224.psp#1.sva(7)} -pin  "ACC1:acc#304" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#17.itm}
+load net {ACC1:acc#304.itm(0)} -pin  "ACC1:acc#304" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(1)} -pin  "ACC1:acc#304" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(2)} -pin  "ACC1:acc#304" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load inst "ACC1:acc#303" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 64182 -attr oid 1372 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#304.itm(0)} -pin  "ACC1:acc#303" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(1)} -pin  "ACC1:acc#303" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(2)} -pin  "ACC1:acc#303" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1-1:acc#25.psp.sva(8)} -pin  "ACC1:acc#303" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#46.itm}
+load net {ACC1:acc#303.itm(0)} -pin  "ACC1:acc#303" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(1)} -pin  "ACC1:acc#303" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(2)} -pin  "ACC1:acc#303" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load inst "ACC1:acc#302" "add(3,0,1,0,4)" "INTERFACE" -attr xrf 64183 -attr oid 1373 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#303.itm(0)} -pin  "ACC1:acc#302" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(1)} -pin  "ACC1:acc#302" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(2)} -pin  "ACC1:acc#302" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#302" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#83.itm}
+load net {ACC1:acc#302.itm(0)} -pin  "ACC1:acc#302" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(1)} -pin  "ACC1:acc#302" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(2)} -pin  "ACC1:acc#302" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(3)} -pin  "ACC1:acc#302" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load inst "ACC1:mul#54" "mul(4,0,7,0,10)" "INTERFACE" -attr xrf 64184 -attr oid 1374 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,7,0,10)"
+load net {ACC1:acc#302.itm(0)} -pin  "ACC1:mul#54" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(1)} -pin  "ACC1:mul#54" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(2)} -pin  "ACC1:mul#54" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(3)} -pin  "ACC1:mul#54" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {PWR} -pin  "ACC1:mul#54" {B(0)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#54" {B(1)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#54" {B(2)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#54" {B(3)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#54" {B(4)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#54" {B(5)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#54" {B(6)} -attr @path {/sobel/sobel:core/C85_7}
+load net {ACC1:mul#54.itm(0)} -pin  "ACC1:mul#54" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(1)} -pin  "ACC1:mul#54" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(2)} -pin  "ACC1:mul#54" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(3)} -pin  "ACC1:mul#54" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(4)} -pin  "ACC1:mul#54" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(5)} -pin  "ACC1:mul#54" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(6)} -pin  "ACC1:mul#54" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(7)} -pin  "ACC1:mul#54" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(8)} -pin  "ACC1:mul#54" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(9)} -pin  "ACC1:mul#54" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load inst "ACC1:acc#651" "add(10,1,10,0,12)" "INTERFACE" -attr xrf 64185 -attr oid 1375 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,12)"
+load net {ACC1:acc#646.itm(0)} -pin  "ACC1:acc#651" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(1)} -pin  "ACC1:acc#651" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(2)} -pin  "ACC1:acc#651" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(3)} -pin  "ACC1:acc#651" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(4)} -pin  "ACC1:acc#651" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(5)} -pin  "ACC1:acc#651" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(6)} -pin  "ACC1:acc#651" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(7)} -pin  "ACC1:acc#651" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(8)} -pin  "ACC1:acc#651" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:acc#646.itm(9)} -pin  "ACC1:acc#651" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#646.itm}
+load net {ACC1:mul#54.itm(0)} -pin  "ACC1:acc#651" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(1)} -pin  "ACC1:acc#651" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(2)} -pin  "ACC1:acc#651" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(3)} -pin  "ACC1:acc#651" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(4)} -pin  "ACC1:acc#651" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(5)} -pin  "ACC1:acc#651" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(6)} -pin  "ACC1:acc#651" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(7)} -pin  "ACC1:acc#651" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(8)} -pin  "ACC1:acc#651" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:mul#54.itm(9)} -pin  "ACC1:acc#651" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#54.itm}
+load net {ACC1:acc#651.itm(0)} -pin  "ACC1:acc#651" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(1)} -pin  "ACC1:acc#651" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(2)} -pin  "ACC1:acc#651" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(3)} -pin  "ACC1:acc#651" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(4)} -pin  "ACC1:acc#651" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(5)} -pin  "ACC1:acc#651" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(6)} -pin  "ACC1:acc#651" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(7)} -pin  "ACC1:acc#651" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(8)} -pin  "ACC1:acc#651" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(9)} -pin  "ACC1:acc#651" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(10)} -pin  "ACC1:acc#651" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(11)} -pin  "ACC1:acc#651" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load inst "ACC1:acc#315" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 64186 -attr oid 1376 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#227.psp.sva(10)} -pin  "ACC1:acc#315" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#17.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#315" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#22.itm}
+load net {ACC1:acc#315.itm(0)} -pin  "ACC1:acc#315" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(1)} -pin  "ACC1:acc#315" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load inst "ACC1:acc#314" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 64187 -attr oid 1377 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#315.itm(0)} -pin  "ACC1:acc#314" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(1)} -pin  "ACC1:acc#314" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#224.psp.sva(9)} -pin  "ACC1:acc#314" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#39.itm}
+load net {ACC1:acc#314.itm(0)} -pin  "ACC1:acc#314" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(1)} -pin  "ACC1:acc#314" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load inst "ACC1:acc#313" "add(2,0,1,0,3)" "INTERFACE" -attr xrf 64188 -attr oid 1378 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#314.itm(0)} -pin  "ACC1:acc#313" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(1)} -pin  "ACC1:acc#313" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#228.psp.sva(9)} -pin  "ACC1:acc#313" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#41.itm}
+load net {ACC1:acc#313.itm(0)} -pin  "ACC1:acc#313" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(1)} -pin  "ACC1:acc#313" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(2)} -pin  "ACC1:acc#313" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load inst "ACC1:acc#312" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 64189 -attr oid 1379 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#313.itm(0)} -pin  "ACC1:acc#312" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(1)} -pin  "ACC1:acc#312" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(2)} -pin  "ACC1:acc#312" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#226.psp.sva(9)} -pin  "ACC1:acc#312" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#38.itm}
+load net {ACC1:acc#312.itm(0)} -pin  "ACC1:acc#312" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(1)} -pin  "ACC1:acc#312" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(2)} -pin  "ACC1:acc#312" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load inst "ACC1:acc#311" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 64190 -attr oid 1380 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#312.itm(0)} -pin  "ACC1:acc#311" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(1)} -pin  "ACC1:acc#311" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(2)} -pin  "ACC1:acc#311" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#224.psp#1.sva(9)} -pin  "ACC1:acc#311" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#47.itm}
+load net {ACC1:acc#311.itm(0)} -pin  "ACC1:acc#311" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(1)} -pin  "ACC1:acc#311" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(2)} -pin  "ACC1:acc#311" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load inst "ACC1:acc#310" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 64191 -attr oid 1381 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#311.itm(0)} -pin  "ACC1:acc#310" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(1)} -pin  "ACC1:acc#310" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(2)} -pin  "ACC1:acc#310" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1-1:acc#25.psp.sva(10)} -pin  "ACC1:acc#310" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#52.itm}
+load net {ACC1:acc#310.itm(0)} -pin  "ACC1:acc#310" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(1)} -pin  "ACC1:acc#310" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(2)} -pin  "ACC1:acc#310" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load inst "ACC1:acc#309" "add(3,0,1,0,4)" "INTERFACE" -attr xrf 64192 -attr oid 1382 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#310.itm(0)} -pin  "ACC1:acc#309" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(1)} -pin  "ACC1:acc#309" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(2)} -pin  "ACC1:acc#309" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#309" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#26.itm}
+load net {ACC1:acc#309.itm(0)} -pin  "ACC1:acc#309" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(1)} -pin  "ACC1:acc#309" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(2)} -pin  "ACC1:acc#309" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(3)} -pin  "ACC1:acc#309" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load inst "ACC1:mul#55" "mul(4,0,9,0,12)" "INTERFACE" -attr xrf 64193 -attr oid 1383 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,9,0,12)"
+load net {ACC1:acc#309.itm(0)} -pin  "ACC1:mul#55" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(1)} -pin  "ACC1:mul#55" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(2)} -pin  "ACC1:mul#55" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(3)} -pin  "ACC1:mul#55" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {PWR} -pin  "ACC1:mul#55" {B(0)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#55" {B(1)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#55" {B(2)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#55" {B(3)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#55" {B(4)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#55" {B(5)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#55" {B(6)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#55" {B(7)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#55" {B(8)} -attr @path {/sobel/sobel:core/C341_9}
+load net {ACC1:mul#55.itm(0)} -pin  "ACC1:mul#55" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(1)} -pin  "ACC1:mul#55" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(2)} -pin  "ACC1:mul#55" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(3)} -pin  "ACC1:mul#55" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(4)} -pin  "ACC1:mul#55" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(5)} -pin  "ACC1:mul#55" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(6)} -pin  "ACC1:mul#55" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(7)} -pin  "ACC1:mul#55" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(8)} -pin  "ACC1:mul#55" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(9)} -pin  "ACC1:mul#55" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(10)} -pin  "ACC1:mul#55" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(11)} -pin  "ACC1:mul#55" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load inst "ACC1:acc#658" "add(12,1,12,0,13)" "INTERFACE" -attr xrf 64194 -attr oid 1384 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,12,1,13)"
+load net {ACC1:acc#651.itm(0)} -pin  "ACC1:acc#658" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(1)} -pin  "ACC1:acc#658" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(2)} -pin  "ACC1:acc#658" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(3)} -pin  "ACC1:acc#658" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(4)} -pin  "ACC1:acc#658" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(5)} -pin  "ACC1:acc#658" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(6)} -pin  "ACC1:acc#658" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(7)} -pin  "ACC1:acc#658" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(8)} -pin  "ACC1:acc#658" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(9)} -pin  "ACC1:acc#658" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(10)} -pin  "ACC1:acc#658" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:acc#651.itm(11)} -pin  "ACC1:acc#658" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#651.itm}
+load net {ACC1:mul#55.itm(0)} -pin  "ACC1:acc#658" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(1)} -pin  "ACC1:acc#658" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(2)} -pin  "ACC1:acc#658" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(3)} -pin  "ACC1:acc#658" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(4)} -pin  "ACC1:acc#658" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(5)} -pin  "ACC1:acc#658" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(6)} -pin  "ACC1:acc#658" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(7)} -pin  "ACC1:acc#658" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(8)} -pin  "ACC1:acc#658" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(9)} -pin  "ACC1:acc#658" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(10)} -pin  "ACC1:acc#658" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:mul#55.itm(11)} -pin  "ACC1:acc#658" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#55.itm}
+load net {ACC1:acc#658.itm(0)} -pin  "ACC1:acc#658" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(1)} -pin  "ACC1:acc#658" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(2)} -pin  "ACC1:acc#658" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(3)} -pin  "ACC1:acc#658" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(4)} -pin  "ACC1:acc#658" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(5)} -pin  "ACC1:acc#658" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(6)} -pin  "ACC1:acc#658" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(7)} -pin  "ACC1:acc#658" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(8)} -pin  "ACC1:acc#658" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(9)} -pin  "ACC1:acc#658" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(10)} -pin  "ACC1:acc#658" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(11)} -pin  "ACC1:acc#658" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(12)} -pin  "ACC1:acc#658" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load inst "reg(ACC1:acc#658.itm#1)" "reg(13,1,1,-1,0)" "INTERFACE" -attr xrf 64195 -attr oid 1385 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#658.itm#1)}
+load net {ACC1:acc#658.itm(0)} -pin  "reg(ACC1:acc#658.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(1)} -pin  "reg(ACC1:acc#658.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(2)} -pin  "reg(ACC1:acc#658.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(3)} -pin  "reg(ACC1:acc#658.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(4)} -pin  "reg(ACC1:acc#658.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(5)} -pin  "reg(ACC1:acc#658.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(6)} -pin  "reg(ACC1:acc#658.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(7)} -pin  "reg(ACC1:acc#658.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(8)} -pin  "reg(ACC1:acc#658.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(9)} -pin  "reg(ACC1:acc#658.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(10)} -pin  "reg(ACC1:acc#658.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(11)} -pin  "reg(ACC1:acc#658.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {ACC1:acc#658.itm(12)} -pin  "reg(ACC1:acc#658.itm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#658.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_13}
+load net {clk} -pin  "reg(ACC1:acc#658.itm#1)" {clk} -attr xrf 64196 -attr oid 1386 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#658.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#658.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#658.itm#1(0)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(1)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(2)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(3)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(4)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(5)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(6)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(7)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(8)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(9)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(10)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(11)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(12)} -pin  "reg(ACC1:acc#658.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load inst "ACC1:acc#329" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 64197 -attr oid 1387 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#224.psp.sva(10)} -pin  "ACC1:acc#329" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#9.itm}
+load net {ACC1:acc#228.psp.sva(10)} -pin  "ACC1:acc#329" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#1.itm}
+load net {ACC1:acc#329.itm(0)} -pin  "ACC1:acc#329" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(1)} -pin  "ACC1:acc#329" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load inst "ACC1:acc#328" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 64198 -attr oid 1388 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#329.itm(0)} -pin  "ACC1:acc#328" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(1)} -pin  "ACC1:acc#328" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#226.psp.sva(10)} -pin  "ACC1:acc#328" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#2.itm}
+load net {ACC1:acc#328.itm(0)} -pin  "ACC1:acc#328" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(1)} -pin  "ACC1:acc#328" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load inst "ACC1:acc#327" "add(2,0,1,0,3)" "INTERFACE" -attr xrf 64199 -attr oid 1389 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#328.itm(0)} -pin  "ACC1:acc#327" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(1)} -pin  "ACC1:acc#327" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#224.psp#1.sva(10)} -pin  "ACC1:acc#327" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#3.itm}
+load net {ACC1:acc#327.itm(0)} -pin  "ACC1:acc#327" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(1)} -pin  "ACC1:acc#327" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(2)} -pin  "ACC1:acc#327" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load inst "ACC1:mul#59" "mul(3,0,7,0,9)" "INTERFACE" -attr xrf 64200 -attr oid 1390 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,7,0,10)"
+load net {ACC1:acc#327.itm(0)} -pin  "ACC1:mul#59" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(1)} -pin  "ACC1:mul#59" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(2)} -pin  "ACC1:mul#59" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {PWR} -pin  "ACC1:mul#59" {B(0)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#59" {B(1)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#59" {B(2)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#59" {B(3)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#59" {B(4)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#59" {B(5)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#59" {B(6)} -attr @path {/sobel/sobel:core/C85_7}
+load net {ACC1:mul#59.itm(0)} -pin  "ACC1:mul#59" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(1)} -pin  "ACC1:mul#59" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(2)} -pin  "ACC1:mul#59" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(3)} -pin  "ACC1:mul#59" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(4)} -pin  "ACC1:mul#59" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(5)} -pin  "ACC1:mul#59" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(6)} -pin  "ACC1:mul#59" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(7)} -pin  "ACC1:mul#59" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load net {ACC1:mul#59.itm(8)} -pin  "ACC1:mul#59" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#59.itm}
+load inst "ACC1:acc#657" "add(12,1,12,0,13)" "INTERFACE" -attr xrf 64201 -attr oid 1391 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,12,1,13)"
+load net {acc.psp#1.sva(2)} -pin  "ACC1:acc#657" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#657" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(2)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(3)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(4)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(5)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(6)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(7)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(8)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#657" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {GND} -pin  "ACC1:acc#657" {A(10)} -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#657" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#912.itm}
+load net {ACC1:acc#224.psp.sva(4)} -pin  "ACC1:acc#657" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:acc#224.psp.sva(4)} -pin  "ACC1:acc#657" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {acc.psp#1.sva(4)} -pin  "ACC1:acc#657" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(0)} -pin  "ACC1:acc#657" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(1)} -pin  "ACC1:acc#657" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(2)} -pin  "ACC1:acc#657" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(3)} -pin  "ACC1:acc#657" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(4)} -pin  "ACC1:acc#657" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(5)} -pin  "ACC1:acc#657" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(6)} -pin  "ACC1:acc#657" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(7)} -pin  "ACC1:acc#657" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:mul#59.itm(8)} -pin  "ACC1:acc#657" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1106.itm}
+load net {ACC1:acc#657.itm(0)} -pin  "ACC1:acc#657" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(1)} -pin  "ACC1:acc#657" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(2)} -pin  "ACC1:acc#657" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(3)} -pin  "ACC1:acc#657" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(4)} -pin  "ACC1:acc#657" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(5)} -pin  "ACC1:acc#657" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(6)} -pin  "ACC1:acc#657" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(7)} -pin  "ACC1:acc#657" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(8)} -pin  "ACC1:acc#657" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(9)} -pin  "ACC1:acc#657" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(10)} -pin  "ACC1:acc#657" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(11)} -pin  "ACC1:acc#657" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(12)} -pin  "ACC1:acc#657" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load inst "ACC1:acc#317" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 64202 -attr oid 1392 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#317" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#10.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#317" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#11.itm}
+load net {ACC1:acc#317.itm(0)} -pin  "ACC1:acc#317" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(1)} -pin  "ACC1:acc#317" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load inst "ACC1:acc#316" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 64203 -attr oid 1393 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#317.itm(0)} -pin  "ACC1:acc#316" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(1)} -pin  "ACC1:acc#316" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#316" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#72.itm}
+load net {ACC1:acc#316.itm(0)} -pin  "ACC1:acc#316" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(1)} -pin  "ACC1:acc#316" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load inst "ACC1:mul#56" "mul(2,0,11,1,13)" "INTERFACE" -attr xrf 64204 -attr oid 1394 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,11,1,13)"
+load net {ACC1:acc#316.itm(0)} -pin  "ACC1:mul#56" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(1)} -pin  "ACC1:mul#56" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {PWR} -pin  "ACC1:mul#56" {B(0)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {GND} -pin  "ACC1:mul#56" {B(1)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {GND} -pin  "ACC1:mul#56" {B(2)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {PWR} -pin  "ACC1:mul#56" {B(3)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {GND} -pin  "ACC1:mul#56" {B(4)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {PWR} -pin  "ACC1:mul#56" {B(5)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {GND} -pin  "ACC1:mul#56" {B(6)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {PWR} -pin  "ACC1:mul#56" {B(7)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {GND} -pin  "ACC1:mul#56" {B(8)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {GND} -pin  "ACC1:mul#56" {B(9)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {PWR} -pin  "ACC1:mul#56" {B(10)} -attr @path {/sobel/sobel:core/Cn855_11}
+load net {ACC1:mul#56.itm(0)} -pin  "ACC1:mul#56" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(1)} -pin  "ACC1:mul#56" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(2)} -pin  "ACC1:mul#56" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(3)} -pin  "ACC1:mul#56" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(4)} -pin  "ACC1:mul#56" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(5)} -pin  "ACC1:mul#56" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(6)} -pin  "ACC1:mul#56" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(7)} -pin  "ACC1:mul#56" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(8)} -pin  "ACC1:mul#56" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(9)} -pin  "ACC1:mul#56" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(10)} -pin  "ACC1:mul#56" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(11)} -pin  "ACC1:mul#56" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(12)} -pin  "ACC1:mul#56" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load inst "ACC1:acc#661" "add(13,1,13,1,14)" "INTERFACE" -attr xrf 64205 -attr oid 1395 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661} -attr area 14.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,1,13,1,14)"
+load net {ACC1:acc#657.itm(0)} -pin  "ACC1:acc#661" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(1)} -pin  "ACC1:acc#661" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(2)} -pin  "ACC1:acc#661" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(3)} -pin  "ACC1:acc#661" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(4)} -pin  "ACC1:acc#661" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(5)} -pin  "ACC1:acc#661" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(6)} -pin  "ACC1:acc#661" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(7)} -pin  "ACC1:acc#661" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(8)} -pin  "ACC1:acc#661" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(9)} -pin  "ACC1:acc#661" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(10)} -pin  "ACC1:acc#661" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(11)} -pin  "ACC1:acc#661" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:acc#657.itm(12)} -pin  "ACC1:acc#661" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#657.itm}
+load net {ACC1:mul#56.itm(0)} -pin  "ACC1:acc#661" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(1)} -pin  "ACC1:acc#661" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(2)} -pin  "ACC1:acc#661" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(3)} -pin  "ACC1:acc#661" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(4)} -pin  "ACC1:acc#661" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(5)} -pin  "ACC1:acc#661" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(6)} -pin  "ACC1:acc#661" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(7)} -pin  "ACC1:acc#661" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(8)} -pin  "ACC1:acc#661" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(9)} -pin  "ACC1:acc#661" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(10)} -pin  "ACC1:acc#661" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(11)} -pin  "ACC1:acc#661" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:mul#56.itm(12)} -pin  "ACC1:acc#661" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#56.itm}
+load net {ACC1:acc#661.itm(0)} -pin  "ACC1:acc#661" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(1)} -pin  "ACC1:acc#661" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(2)} -pin  "ACC1:acc#661" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(3)} -pin  "ACC1:acc#661" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(4)} -pin  "ACC1:acc#661" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(5)} -pin  "ACC1:acc#661" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(6)} -pin  "ACC1:acc#661" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(7)} -pin  "ACC1:acc#661" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(8)} -pin  "ACC1:acc#661" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(9)} -pin  "ACC1:acc#661" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(10)} -pin  "ACC1:acc#661" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(11)} -pin  "ACC1:acc#661" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(12)} -pin  "ACC1:acc#661" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(13)} -pin  "ACC1:acc#661" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load inst "reg(ACC1:acc#661.itm#1)" "reg(14,1,1,-1,0)" "INTERFACE" -attr xrf 64206 -attr oid 1396 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#661.itm#1)}
+load net {ACC1:acc#661.itm(0)} -pin  "reg(ACC1:acc#661.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(1)} -pin  "reg(ACC1:acc#661.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(2)} -pin  "reg(ACC1:acc#661.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(3)} -pin  "reg(ACC1:acc#661.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(4)} -pin  "reg(ACC1:acc#661.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(5)} -pin  "reg(ACC1:acc#661.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(6)} -pin  "reg(ACC1:acc#661.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(7)} -pin  "reg(ACC1:acc#661.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(8)} -pin  "reg(ACC1:acc#661.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(9)} -pin  "reg(ACC1:acc#661.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(10)} -pin  "reg(ACC1:acc#661.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(11)} -pin  "reg(ACC1:acc#661.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(12)} -pin  "reg(ACC1:acc#661.itm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {ACC1:acc#661.itm(13)} -pin  "reg(ACC1:acc#661.itm#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:acc#661.itm#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_14}
+load net {clk} -pin  "reg(ACC1:acc#661.itm#1)" {clk} -attr xrf 64207 -attr oid 1397 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#661.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#661.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#661.itm#1(0)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(1)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(2)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(3)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(4)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(5)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(6)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(7)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(8)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(9)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(10)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(11)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(12)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(13)} -pin  "reg(ACC1:acc#661.itm#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load inst "reg(ACC1:mul#57.itm#1.sg2)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 64208 -attr oid 1398 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:mul#57.itm#1.sg2)}
+load net {ACC1:mul#57.itm(9)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#2.itm}
+load net {ACC1:mul#57.itm(10)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#2.itm}
+load net {ACC1:mul#57.itm(11)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#2.itm}
+load net {ACC1:mul#57.itm(12)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#2.itm}
+load net {ACC1:mul#57.itm(13)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#2.itm}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {clk} -attr xrf 64209 -attr oid 1399 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:mul#57.itm#1.sg2(0)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#1.sg2}
+load net {ACC1:mul#57.itm#1.sg2(1)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#1.sg2}
+load net {ACC1:mul#57.itm#1.sg2(2)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#1.sg2}
+load net {ACC1:mul#57.itm#1.sg2(3)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#1.sg2}
+load net {ACC1:mul#57.itm#1.sg2(4)} -pin  "reg(ACC1:mul#57.itm#1.sg2)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#1.sg2}
+load inst "reg(ACC1:mul#57.itm#2)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 64210 -attr oid 1400 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:mul#57.itm#2)}
+load net {ACC1:mul#57.itm(0)} -pin  "reg(ACC1:mul#57.itm#2)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#3.itm}
+load net {ACC1:mul#57.itm(1)} -pin  "reg(ACC1:mul#57.itm#2)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:mul#57.itm)#3.itm}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(ACC1:mul#57.itm#2)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(ACC1:mul#57.itm#2)" {clk} -attr xrf 64211 -attr oid 1401 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:mul#57.itm#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:mul#57.itm#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:mul#57.itm#2(0)} -pin  "reg(ACC1:mul#57.itm#2)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#2}
+load net {ACC1:mul#57.itm#2(1)} -pin  "reg(ACC1:mul#57.itm#2)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm#2}
+load inst "reg(slc(acc#20.psp#1)#93.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 64212 -attr oid 1402 -attr @path {/sobel/sobel:core/reg(slc(acc#20.psp#1)#93.itm#1)}
+load net {acc#20.psp#1.sva(11)} -pin  "reg(slc(acc#20.psp#1)#93.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#12.itm}
+load net {GND} -pin  "reg(slc(acc#20.psp#1)#93.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(slc(acc#20.psp#1)#93.itm#1)" {clk} -attr xrf 64213 -attr oid 1403 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(slc(acc#20.psp#1)#93.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(slc(acc#20.psp#1)#93.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {slc(acc#20.psp#1)#93.itm#1} -pin  "reg(slc(acc#20.psp#1)#93.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1)#93.itm#1}
+load inst "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 64214 -attr oid 1404 -attr @path {/sobel/sobel:core/reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)}
+load net {ACC1:acc#228.psp.sva(6)} -pin  "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#14.itm}
+load net {GND} -pin  "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" {clk} -attr xrf 64215 -attr oid 1405 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(ACC1:acc#228.psp)#55.itm#1} -pin  "reg(ACC1:slc(ACC1:acc#228.psp)#55.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:slc(ACC1:acc#228.psp)#55.itm#1}
+load inst "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 64216 -attr oid 1406 -attr @path {/sobel/sobel:core/reg(ACC1-3:slc(acc#10.psp)#62.itm#1)}
+load net {ACC1:acc#224.psp.sva(8)} -pin  "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#16.itm}
+load net {GND} -pin  "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" {clk} -attr xrf 64217 -attr oid 1407 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1-3:slc(acc#10.psp)#62.itm#1} -pin  "reg(ACC1-3:slc(acc#10.psp)#62.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:slc(acc#10.psp)#62.itm#1}
+load inst "ACC1:acc#458" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64218 -attr oid 1408 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#458} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#458" {A(0)} -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#458" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#458" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {ACC1:acc#346.itm(4)} -pin  "ACC1:acc#458" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1497.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#458" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1497.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#458" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1497.itm}
+load net {ACC1:acc#458.itm(0)} -pin  "ACC1:acc#458" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#458.itm}
+load net {ACC1:acc#458.itm(1)} -pin  "ACC1:acc#458" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#458.itm}
+load net {ACC1:acc#458.itm(2)} -pin  "ACC1:acc#458" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#458.itm}
+load net {ACC1:acc#458.itm(3)} -pin  "ACC1:acc#458" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#458.itm}
+load inst "ACC1:acc#457" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64219 -attr oid 1409 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#457} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#457" {A(0)} -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#457" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#457" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {ACC1:acc#346.itm(3)} -pin  "ACC1:acc#457" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1499.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#457" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1499.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#457" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1499.itm}
+load net {ACC1:acc#457.itm(0)} -pin  "ACC1:acc#457" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#457.itm}
+load net {ACC1:acc#457.itm(1)} -pin  "ACC1:acc#457" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#457.itm}
+load net {ACC1:acc#457.itm(2)} -pin  "ACC1:acc#457" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#457.itm}
+load net {ACC1:acc#457.itm(3)} -pin  "ACC1:acc#457" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#457.itm}
+load inst "ACC1:acc#540" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64220 -attr oid 1410 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#458.itm(1)} -pin  "ACC1:acc#540" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#126.itm}
+load net {ACC1:acc#458.itm(2)} -pin  "ACC1:acc#540" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#126.itm}
+load net {ACC1:acc#458.itm(3)} -pin  "ACC1:acc#540" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#126.itm}
+load net {ACC1:acc#457.itm(1)} -pin  "ACC1:acc#540" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#125.itm}
+load net {ACC1:acc#457.itm(2)} -pin  "ACC1:acc#540" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#125.itm}
+load net {ACC1:acc#457.itm(3)} -pin  "ACC1:acc#540" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#125.itm}
+load net {ACC1:acc#540.itm(0)} -pin  "ACC1:acc#540" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#540.itm(1)} -pin  "ACC1:acc#540" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#540.itm(2)} -pin  "ACC1:acc#540" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#540.itm(3)} -pin  "ACC1:acc#540" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load inst "ACC1:acc#456" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64221 -attr oid 1411 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#456} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#456" {A(0)} -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#456" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#456" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {ACC1:acc#346.itm(2)} -pin  "ACC1:acc#456" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1501.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#456" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1501.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#456" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1501.itm}
+load net {ACC1:acc#456.itm(0)} -pin  "ACC1:acc#456" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#456.itm}
+load net {ACC1:acc#456.itm(1)} -pin  "ACC1:acc#456" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#456.itm}
+load net {ACC1:acc#456.itm(2)} -pin  "ACC1:acc#456" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#456.itm}
+load net {ACC1:acc#456.itm(3)} -pin  "ACC1:acc#456" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#456.itm}
+load inst "ACC1:acc#455" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64222 -attr oid 1412 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#455} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#455" {A(0)} -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#455" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#455" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {ACC1:acc#405.itm(2)} -pin  "ACC1:acc#455" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1503.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#455" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1503.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#455" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1503.itm}
+load net {ACC1:acc#455.itm(0)} -pin  "ACC1:acc#455" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#455.itm}
+load net {ACC1:acc#455.itm(1)} -pin  "ACC1:acc#455" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#455.itm}
+load net {ACC1:acc#455.itm(2)} -pin  "ACC1:acc#455" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#455.itm}
+load net {ACC1:acc#455.itm(3)} -pin  "ACC1:acc#455" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#455.itm}
+load inst "ACC1:acc#539" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64223 -attr oid 1413 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#456.itm(1)} -pin  "ACC1:acc#539" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#124.itm}
+load net {ACC1:acc#456.itm(2)} -pin  "ACC1:acc#539" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#124.itm}
+load net {ACC1:acc#456.itm(3)} -pin  "ACC1:acc#539" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#124.itm}
+load net {ACC1:acc#455.itm(1)} -pin  "ACC1:acc#539" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#123.itm}
+load net {ACC1:acc#455.itm(2)} -pin  "ACC1:acc#539" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#123.itm}
+load net {ACC1:acc#455.itm(3)} -pin  "ACC1:acc#539" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#123.itm}
+load net {ACC1:acc#539.itm(0)} -pin  "ACC1:acc#539" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#539.itm(1)} -pin  "ACC1:acc#539" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#539.itm(2)} -pin  "ACC1:acc#539" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#539.itm(3)} -pin  "ACC1:acc#539" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load inst "ACC1:acc#585" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64224 -attr oid 1414 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#540.itm(0)} -pin  "ACC1:acc#585" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#540.itm(1)} -pin  "ACC1:acc#585" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#540.itm(2)} -pin  "ACC1:acc#585" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#540.itm(3)} -pin  "ACC1:acc#585" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#540.itm}
+load net {ACC1:acc#539.itm(0)} -pin  "ACC1:acc#585" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#539.itm(1)} -pin  "ACC1:acc#585" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#539.itm(2)} -pin  "ACC1:acc#585" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#539.itm(3)} -pin  "ACC1:acc#585" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#539.itm}
+load net {ACC1:acc#585.itm(0)} -pin  "ACC1:acc#585" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(1)} -pin  "ACC1:acc#585" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(2)} -pin  "ACC1:acc#585" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(3)} -pin  "ACC1:acc#585" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(4)} -pin  "ACC1:acc#585" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load inst "ACC1:acc#454" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64225 -attr oid 1415 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#454} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#454" {A(0)} -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#454" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#454" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {ACC1-3:acc#212.psp.sva(3)} -pin  "ACC1:acc#454" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1505.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#454" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1505.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#454" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1505.itm}
+load net {ACC1:acc#454.itm(0)} -pin  "ACC1:acc#454" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#454.itm}
+load net {ACC1:acc#454.itm(1)} -pin  "ACC1:acc#454" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#454.itm}
+load net {ACC1:acc#454.itm(2)} -pin  "ACC1:acc#454" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#454.itm}
+load net {ACC1:acc#454.itm(3)} -pin  "ACC1:acc#454" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#454.itm}
+load inst "ACC1:acc#453" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64226 -attr oid 1416 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#453} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#453" {A(0)} -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#453" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#453" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {ACC1-3:acc#212.psp.sva(2)} -pin  "ACC1:acc#453" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1507.itm}
+load net {ACC1-1:acc#25.psp.sva(5)} -pin  "ACC1:acc#453" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1507.itm}
+load net {ACC1-1:acc#25.psp.sva(5)} -pin  "ACC1:acc#453" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1507.itm}
+load net {ACC1:acc#453.itm(0)} -pin  "ACC1:acc#453" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#453.itm}
+load net {ACC1:acc#453.itm(1)} -pin  "ACC1:acc#453" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#453.itm}
+load net {ACC1:acc#453.itm(2)} -pin  "ACC1:acc#453" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#453.itm}
+load net {ACC1:acc#453.itm(3)} -pin  "ACC1:acc#453" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#453.itm}
+load inst "ACC1:acc#538" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64227 -attr oid 1417 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#454.itm(1)} -pin  "ACC1:acc#538" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#122.itm}
+load net {ACC1:acc#454.itm(2)} -pin  "ACC1:acc#538" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#122.itm}
+load net {ACC1:acc#454.itm(3)} -pin  "ACC1:acc#538" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#122.itm}
+load net {ACC1:acc#453.itm(1)} -pin  "ACC1:acc#538" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#121.itm}
+load net {ACC1:acc#453.itm(2)} -pin  "ACC1:acc#538" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#121.itm}
+load net {ACC1:acc#453.itm(3)} -pin  "ACC1:acc#538" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#121.itm}
+load net {ACC1:acc#538.itm(0)} -pin  "ACC1:acc#538" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#538.itm(1)} -pin  "ACC1:acc#538" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#538.itm(2)} -pin  "ACC1:acc#538" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#538.itm(3)} -pin  "ACC1:acc#538" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load inst "ACC1:acc#452" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64228 -attr oid 1418 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#452} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#452" {A(0)} -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#452" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#452" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {ACC1-3:acc#212.psp.sva(1)} -pin  "ACC1:acc#452" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1509.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#452" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1509.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#452" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1509.itm}
+load net {ACC1:acc#452.itm(0)} -pin  "ACC1:acc#452" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#452.itm}
+load net {ACC1:acc#452.itm(1)} -pin  "ACC1:acc#452" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#452.itm}
+load net {ACC1:acc#452.itm(2)} -pin  "ACC1:acc#452" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#452.itm}
+load net {ACC1:acc#452.itm(3)} -pin  "ACC1:acc#452" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#452.itm}
+load inst "ACC1-2:not#188" "not(1)" "INTERFACE" -attr xrf 64229 -attr oid 1419 -attr @path {/sobel/sobel:core/ACC1-2:not#188} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#387.itm(2)} -pin  "ACC1-2:not#188" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#45.sva)#2.itm}
+load net {ACC1-2:not#188.itm} -pin  "ACC1-2:not#188" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#188.itm}
+load inst "ACC1-2:and#11" "and(3,1)" "INTERFACE" -attr xrf 64230 -attr oid 1420 -attr @path {/sobel/sobel:core/ACC1-2:and#11} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1-2:and#11" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#24.itm}
+load net {ACC1-2:not#188.itm} -pin  "ACC1-2:and#11" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#188.itm}
+load net {ACC1:acc#387.itm(1)} -pin  "ACC1-2:and#11" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#45.sva)#1.itm}
+load net {ACC1-2:and#11.itm} -pin  "ACC1-2:and#11" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:and#11.itm}
+load inst "ACC1:acc#451" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64231 -attr oid 1421 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#451} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#451" {A(0)} -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#451" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#451" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1-2:and#11.itm} -pin  "ACC1:acc#451" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1511.itm}
+load net {ACC1:acc#227.psp.sva(9)} -pin  "ACC1:acc#451" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1511.itm}
+load net {ACC1:acc#227.psp.sva(9)} -pin  "ACC1:acc#451" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1511.itm}
+load net {ACC1:acc#451.itm(0)} -pin  "ACC1:acc#451" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#451.itm}
+load net {ACC1:acc#451.itm(1)} -pin  "ACC1:acc#451" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#451.itm}
+load net {ACC1:acc#451.itm(2)} -pin  "ACC1:acc#451" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#451.itm}
+load net {ACC1:acc#451.itm(3)} -pin  "ACC1:acc#451" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#451.itm}
+load inst "ACC1:acc#537" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64232 -attr oid 1422 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#452.itm(1)} -pin  "ACC1:acc#537" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#120.itm}
+load net {ACC1:acc#452.itm(2)} -pin  "ACC1:acc#537" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#120.itm}
+load net {ACC1:acc#452.itm(3)} -pin  "ACC1:acc#537" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#120.itm}
+load net {ACC1:acc#451.itm(1)} -pin  "ACC1:acc#537" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#119.itm}
+load net {ACC1:acc#451.itm(2)} -pin  "ACC1:acc#537" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#119.itm}
+load net {ACC1:acc#451.itm(3)} -pin  "ACC1:acc#537" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#119.itm}
+load net {ACC1:acc#537.itm(0)} -pin  "ACC1:acc#537" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#537.itm(1)} -pin  "ACC1:acc#537" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#537.itm(2)} -pin  "ACC1:acc#537" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#537.itm(3)} -pin  "ACC1:acc#537" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load inst "ACC1:acc#584" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64233 -attr oid 1423 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#538.itm(0)} -pin  "ACC1:acc#584" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#538.itm(1)} -pin  "ACC1:acc#584" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#538.itm(2)} -pin  "ACC1:acc#584" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#538.itm(3)} -pin  "ACC1:acc#584" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#538.itm}
+load net {ACC1:acc#537.itm(0)} -pin  "ACC1:acc#584" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#537.itm(1)} -pin  "ACC1:acc#584" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#537.itm(2)} -pin  "ACC1:acc#584" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#537.itm(3)} -pin  "ACC1:acc#584" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#537.itm}
+load net {ACC1:acc#584.itm(0)} -pin  "ACC1:acc#584" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(1)} -pin  "ACC1:acc#584" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(2)} -pin  "ACC1:acc#584" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(3)} -pin  "ACC1:acc#584" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(4)} -pin  "ACC1:acc#584" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load inst "ACC1:acc#607" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 64234 -attr oid 1424 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#585.itm(0)} -pin  "ACC1:acc#607" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(1)} -pin  "ACC1:acc#607" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(2)} -pin  "ACC1:acc#607" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(3)} -pin  "ACC1:acc#607" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#585.itm(4)} -pin  "ACC1:acc#607" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#585.itm}
+load net {ACC1:acc#584.itm(0)} -pin  "ACC1:acc#607" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(1)} -pin  "ACC1:acc#607" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(2)} -pin  "ACC1:acc#607" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(3)} -pin  "ACC1:acc#607" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#584.itm(4)} -pin  "ACC1:acc#607" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#584.itm}
+load net {ACC1:acc#607.itm(0)} -pin  "ACC1:acc#607" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(1)} -pin  "ACC1:acc#607" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(2)} -pin  "ACC1:acc#607" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(3)} -pin  "ACC1:acc#607" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(4)} -pin  "ACC1:acc#607" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(5)} -pin  "ACC1:acc#607" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load inst "ACC1-2:not#187" "not(1)" "INTERFACE" -attr xrf 64235 -attr oid 1425 -attr @path {/sobel/sobel:core/ACC1-2:not#187} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1-2:not#187" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#25.itm}
+load net {ACC1-2:not#187.itm} -pin  "ACC1-2:not#187" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#187.itm}
+load inst "ACC1-2:nand#5" "nand(2,1)" "INTERFACE" -attr xrf 64236 -attr oid 1426 -attr @path {/sobel/sobel:core/ACC1-2:nand#5} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#387.itm(2)} -pin  "ACC1-2:nand#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#45.sva).itm}
+load net {ACC1-2:not#187.itm} -pin  "ACC1-2:nand#5" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#187.itm}
+load net {ACC1-2:nand#5.itm} -pin  "ACC1-2:nand#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:nand#5.itm}
+load inst "ACC1:acc#450" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64237 -attr oid 1427 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#450} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#450" {A(0)} -attr @path {/sobel/sobel:core/exs#63.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#450" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#63.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#450" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#63.itm}
+load net {ACC1-2:nand#5.itm} -pin  "ACC1:acc#450" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1513.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#450" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1513.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#450" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1513.itm}
+load net {ACC1:acc#450.itm(0)} -pin  "ACC1:acc#450" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#450.itm}
+load net {ACC1:acc#450.itm(1)} -pin  "ACC1:acc#450" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#450.itm}
+load net {ACC1:acc#450.itm(2)} -pin  "ACC1:acc#450" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#450.itm}
+load net {ACC1:acc#450.itm(3)} -pin  "ACC1:acc#450" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#450.itm}
+load inst "ACC1:acc#449" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64238 -attr oid 1428 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#449} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#449" {A(0)} -attr @path {/sobel/sobel:core/exs#64.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#449" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#64.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#449" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#64.itm}
+load net {ACC1:acc#386.itm(2)} -pin  "ACC1:acc#449" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1515.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#449" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1515.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#449" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1515.itm}
+load net {ACC1:acc#449.itm(0)} -pin  "ACC1:acc#449" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#449.itm}
+load net {ACC1:acc#449.itm(1)} -pin  "ACC1:acc#449" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#449.itm}
+load net {ACC1:acc#449.itm(2)} -pin  "ACC1:acc#449" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#449.itm}
+load net {ACC1:acc#449.itm(3)} -pin  "ACC1:acc#449" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#449.itm}
+load inst "ACC1:acc#536" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64239 -attr oid 1429 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#450.itm(1)} -pin  "ACC1:acc#536" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#118.itm}
+load net {ACC1:acc#450.itm(2)} -pin  "ACC1:acc#536" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#118.itm}
+load net {ACC1:acc#450.itm(3)} -pin  "ACC1:acc#536" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#118.itm}
+load net {ACC1:acc#449.itm(1)} -pin  "ACC1:acc#536" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#117.itm}
+load net {ACC1:acc#449.itm(2)} -pin  "ACC1:acc#536" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#117.itm}
+load net {ACC1:acc#449.itm(3)} -pin  "ACC1:acc#536" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#117.itm}
+load net {ACC1:acc#536.itm(0)} -pin  "ACC1:acc#536" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#536.itm(1)} -pin  "ACC1:acc#536" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#536.itm(2)} -pin  "ACC1:acc#536" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#536.itm(3)} -pin  "ACC1:acc#536" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load inst "ACC1:acc#448" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64240 -attr oid 1430 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#448} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#448" {A(0)} -attr @path {/sobel/sobel:core/exs#65.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#448" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#65.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#448" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#65.itm}
+load net {ACC1:acc#384.itm(4)} -pin  "ACC1:acc#448" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1517.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#448" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1517.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#448" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1517.itm}
+load net {ACC1:acc#448.itm(0)} -pin  "ACC1:acc#448" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#448.itm}
+load net {ACC1:acc#448.itm(1)} -pin  "ACC1:acc#448" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#448.itm}
+load net {ACC1:acc#448.itm(2)} -pin  "ACC1:acc#448" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#448.itm}
+load net {ACC1:acc#448.itm(3)} -pin  "ACC1:acc#448" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#448.itm}
+load inst "ACC1:acc#447" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64241 -attr oid 1431 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#447} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#447" {A(0)} -attr @path {/sobel/sobel:core/exs#92.itm}
+load net {acc.psp#1.sva(5)} -pin  "ACC1:acc#447" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#92.itm}
+load net {acc.psp#1.sva(5)} -pin  "ACC1:acc#447" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#92.itm}
+load net {ACC1:acc#384.itm(3)} -pin  "ACC1:acc#447" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1519.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#447" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1519.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#447" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1519.itm}
+load net {ACC1:acc#447.itm(0)} -pin  "ACC1:acc#447" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#447.itm}
+load net {ACC1:acc#447.itm(1)} -pin  "ACC1:acc#447" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#447.itm}
+load net {ACC1:acc#447.itm(2)} -pin  "ACC1:acc#447" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#447.itm}
+load net {ACC1:acc#447.itm(3)} -pin  "ACC1:acc#447" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#447.itm}
+load inst "ACC1:acc#535" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64242 -attr oid 1432 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#448.itm(1)} -pin  "ACC1:acc#535" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#116.itm}
+load net {ACC1:acc#448.itm(2)} -pin  "ACC1:acc#535" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#116.itm}
+load net {ACC1:acc#448.itm(3)} -pin  "ACC1:acc#535" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#116.itm}
+load net {ACC1:acc#447.itm(1)} -pin  "ACC1:acc#535" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#115.itm}
+load net {ACC1:acc#447.itm(2)} -pin  "ACC1:acc#535" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#115.itm}
+load net {ACC1:acc#447.itm(3)} -pin  "ACC1:acc#535" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#115.itm}
+load net {ACC1:acc#535.itm(0)} -pin  "ACC1:acc#535" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#535.itm(1)} -pin  "ACC1:acc#535" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#535.itm(2)} -pin  "ACC1:acc#535" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#535.itm(3)} -pin  "ACC1:acc#535" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load inst "ACC1:acc#583" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64243 -attr oid 1433 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#536.itm(0)} -pin  "ACC1:acc#583" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#536.itm(1)} -pin  "ACC1:acc#583" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#536.itm(2)} -pin  "ACC1:acc#583" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#536.itm(3)} -pin  "ACC1:acc#583" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#536.itm}
+load net {ACC1:acc#535.itm(0)} -pin  "ACC1:acc#583" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#535.itm(1)} -pin  "ACC1:acc#583" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#535.itm(2)} -pin  "ACC1:acc#583" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#535.itm(3)} -pin  "ACC1:acc#583" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#535.itm}
+load net {ACC1:acc#583.itm(0)} -pin  "ACC1:acc#583" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(1)} -pin  "ACC1:acc#583" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(2)} -pin  "ACC1:acc#583" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(3)} -pin  "ACC1:acc#583" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(4)} -pin  "ACC1:acc#583" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load inst "ACC1:acc#446" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64244 -attr oid 1434 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#446} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#446" {A(0)} -attr @path {/sobel/sobel:core/exs#66.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#446" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#66.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#446" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#66.itm}
+load net {ACC1:acc#384.itm(2)} -pin  "ACC1:acc#446" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1521.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#446" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1521.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#446" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1521.itm}
+load net {ACC1:acc#446.itm(0)} -pin  "ACC1:acc#446" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#446.itm}
+load net {ACC1:acc#446.itm(1)} -pin  "ACC1:acc#446" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#446.itm}
+load net {ACC1:acc#446.itm(2)} -pin  "ACC1:acc#446" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#446.itm}
+load net {ACC1:acc#446.itm(3)} -pin  "ACC1:acc#446" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#446.itm}
+load inst "ACC1-2:not#60" "not(1)" "INTERFACE" -attr xrf 64245 -attr oid 1435 -attr @path {/sobel/sobel:core/ACC1-2:not#60} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#378.itm(2)} -pin  "ACC1-2:not#60" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#33.sva)#2.itm}
+load net {ACC1-2:not#60.itm} -pin  "ACC1-2:not#60" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#60.itm}
+load inst "ACC1-2:and#3" "and(3,1)" "INTERFACE" -attr xrf 64246 -attr oid 1436 -attr @path {/sobel/sobel:core/ACC1-2:and#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1-2:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#29.itm}
+load net {ACC1-2:not#60.itm} -pin  "ACC1-2:and#3" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#60.itm}
+load net {ACC1:acc#378.itm(1)} -pin  "ACC1-2:and#3" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#33.sva)#1.itm}
+load net {ACC1-2:and#3.itm} -pin  "ACC1-2:and#3" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:and#3.itm}
+load inst "ACC1:acc#445" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64247 -attr oid 1437 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#445} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#445" {A(0)} -attr @path {/sobel/sobel:core/exs#93.itm}
+load net {ACC1:acc#227.psp.sva(7)} -pin  "ACC1:acc#445" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#93.itm}
+load net {ACC1:acc#227.psp.sva(7)} -pin  "ACC1:acc#445" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#93.itm}
+load net {ACC1-2:and#3.itm} -pin  "ACC1:acc#445" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1523.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#445" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1523.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#445" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1523.itm}
+load net {ACC1:acc#445.itm(0)} -pin  "ACC1:acc#445" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#445.itm}
+load net {ACC1:acc#445.itm(1)} -pin  "ACC1:acc#445" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#445.itm}
+load net {ACC1:acc#445.itm(2)} -pin  "ACC1:acc#445" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#445.itm}
+load net {ACC1:acc#445.itm(3)} -pin  "ACC1:acc#445" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#445.itm}
+load inst "ACC1:acc#534" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64248 -attr oid 1438 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#446.itm(1)} -pin  "ACC1:acc#534" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#114.itm}
+load net {ACC1:acc#446.itm(2)} -pin  "ACC1:acc#534" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#114.itm}
+load net {ACC1:acc#446.itm(3)} -pin  "ACC1:acc#534" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#114.itm}
+load net {ACC1:acc#445.itm(1)} -pin  "ACC1:acc#534" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#113.itm}
+load net {ACC1:acc#445.itm(2)} -pin  "ACC1:acc#534" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#113.itm}
+load net {ACC1:acc#445.itm(3)} -pin  "ACC1:acc#534" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#113.itm}
+load net {ACC1:acc#534.itm(0)} -pin  "ACC1:acc#534" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#534.itm(1)} -pin  "ACC1:acc#534" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#534.itm(2)} -pin  "ACC1:acc#534" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#534.itm(3)} -pin  "ACC1:acc#534" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load inst "ACC1-2:not#59" "not(1)" "INTERFACE" -attr xrf 64249 -attr oid 1439 -attr @path {/sobel/sobel:core/ACC1-2:not#59} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1-2:not#59" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#30.itm}
+load net {ACC1-2:not#59.itm} -pin  "ACC1-2:not#59" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#59.itm}
+load inst "ACC1-2:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 64250 -attr oid 1440 -attr @path {/sobel/sobel:core/ACC1-2:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#378.itm(2)} -pin  "ACC1-2:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#33.sva).itm}
+load net {ACC1-2:not#59.itm} -pin  "ACC1-2:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#59.itm}
+load net {ACC1-2:nand#1.itm} -pin  "ACC1-2:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:nand#1.itm}
+load inst "ACC1:acc#444" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64251 -attr oid 1441 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#444} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#444" {A(0)} -attr @path {/sobel/sobel:core/exs#67.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#444" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#67.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#444" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#67.itm}
+load net {ACC1-2:nand#1.itm} -pin  "ACC1:acc#444" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1525.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#444" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1525.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#444" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1525.itm}
+load net {ACC1:acc#444.itm(0)} -pin  "ACC1:acc#444" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#444.itm}
+load net {ACC1:acc#444.itm(1)} -pin  "ACC1:acc#444" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#444.itm}
+load net {ACC1:acc#444.itm(2)} -pin  "ACC1:acc#444" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#444.itm}
+load net {ACC1:acc#444.itm(3)} -pin  "ACC1:acc#444" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#444.itm}
+load inst "ACC1:acc#442" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64252 -attr oid 1442 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#442} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#442" {A(0)} -attr @path {/sobel/sobel:core/exs#68.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#442" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#68.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#442" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#68.itm}
+load net {ACC1:acc#375.itm(4)} -pin  "ACC1:acc#442" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1527.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#442" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1527.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#442" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1527.itm}
+load net {ACC1:acc#442.itm(0)} -pin  "ACC1:acc#442" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#442.itm}
+load net {ACC1:acc#442.itm(1)} -pin  "ACC1:acc#442" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#442.itm}
+load net {ACC1:acc#442.itm(2)} -pin  "ACC1:acc#442" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#442.itm}
+load net {ACC1:acc#442.itm(3)} -pin  "ACC1:acc#442" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#442.itm}
+load inst "ACC1:acc#533" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64253 -attr oid 1443 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#444.itm(1)} -pin  "ACC1:acc#533" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#112.itm}
+load net {ACC1:acc#444.itm(2)} -pin  "ACC1:acc#533" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#112.itm}
+load net {ACC1:acc#444.itm(3)} -pin  "ACC1:acc#533" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#112.itm}
+load net {ACC1:acc#442.itm(1)} -pin  "ACC1:acc#533" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#110.itm}
+load net {ACC1:acc#442.itm(2)} -pin  "ACC1:acc#533" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#110.itm}
+load net {ACC1:acc#442.itm(3)} -pin  "ACC1:acc#533" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#110.itm}
+load net {ACC1:acc#533.itm(0)} -pin  "ACC1:acc#533" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#533.itm(1)} -pin  "ACC1:acc#533" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#533.itm(2)} -pin  "ACC1:acc#533" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#533.itm(3)} -pin  "ACC1:acc#533" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load inst "ACC1:acc#582" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64254 -attr oid 1444 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#534.itm(0)} -pin  "ACC1:acc#582" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#534.itm(1)} -pin  "ACC1:acc#582" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#534.itm(2)} -pin  "ACC1:acc#582" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#534.itm(3)} -pin  "ACC1:acc#582" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#534.itm}
+load net {ACC1:acc#533.itm(0)} -pin  "ACC1:acc#582" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#533.itm(1)} -pin  "ACC1:acc#582" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#533.itm(2)} -pin  "ACC1:acc#582" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#533.itm(3)} -pin  "ACC1:acc#582" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#533.itm}
+load net {ACC1:acc#582.itm(0)} -pin  "ACC1:acc#582" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(1)} -pin  "ACC1:acc#582" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(2)} -pin  "ACC1:acc#582" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(3)} -pin  "ACC1:acc#582" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(4)} -pin  "ACC1:acc#582" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load inst "ACC1:acc#606" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 64255 -attr oid 1445 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#583.itm(0)} -pin  "ACC1:acc#606" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(1)} -pin  "ACC1:acc#606" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(2)} -pin  "ACC1:acc#606" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(3)} -pin  "ACC1:acc#606" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#583.itm(4)} -pin  "ACC1:acc#606" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#583.itm}
+load net {ACC1:acc#582.itm(0)} -pin  "ACC1:acc#606" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(1)} -pin  "ACC1:acc#606" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(2)} -pin  "ACC1:acc#606" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(3)} -pin  "ACC1:acc#606" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#582.itm(4)} -pin  "ACC1:acc#606" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#582.itm}
+load net {ACC1:acc#606.itm(0)} -pin  "ACC1:acc#606" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(1)} -pin  "ACC1:acc#606" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(2)} -pin  "ACC1:acc#606" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(3)} -pin  "ACC1:acc#606" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(4)} -pin  "ACC1:acc#606" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(5)} -pin  "ACC1:acc#606" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load inst "ACC1:acc#623" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 64256 -attr oid 1446 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#607.itm(0)} -pin  "ACC1:acc#623" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(1)} -pin  "ACC1:acc#623" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(2)} -pin  "ACC1:acc#623" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(3)} -pin  "ACC1:acc#623" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(4)} -pin  "ACC1:acc#623" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#607.itm(5)} -pin  "ACC1:acc#623" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#607.itm}
+load net {ACC1:acc#606.itm(0)} -pin  "ACC1:acc#623" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(1)} -pin  "ACC1:acc#623" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(2)} -pin  "ACC1:acc#623" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(3)} -pin  "ACC1:acc#623" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(4)} -pin  "ACC1:acc#623" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#606.itm(5)} -pin  "ACC1:acc#623" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#606.itm}
+load net {ACC1:acc#623.itm(0)} -pin  "ACC1:acc#623" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(1)} -pin  "ACC1:acc#623" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(2)} -pin  "ACC1:acc#623" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(3)} -pin  "ACC1:acc#623" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(4)} -pin  "ACC1:acc#623" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(5)} -pin  "ACC1:acc#623" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(6)} -pin  "ACC1:acc#623" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load inst "ACC1:acc#441" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64257 -attr oid 1447 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#441} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#441" {A(0)} -attr @path {/sobel/sobel:core/exs#69.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#441" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#69.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#441" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#69.itm}
+load net {ACC1:acc#375.itm(3)} -pin  "ACC1:acc#441" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1529.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#441" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1529.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#441" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1529.itm}
+load net {ACC1:acc#441.itm(0)} -pin  "ACC1:acc#441" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#441.itm}
+load net {ACC1:acc#441.itm(1)} -pin  "ACC1:acc#441" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#441.itm}
+load net {ACC1:acc#441.itm(2)} -pin  "ACC1:acc#441" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#441.itm}
+load net {ACC1:acc#441.itm(3)} -pin  "ACC1:acc#441" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#441.itm}
+load inst "ACC1:acc#440" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64258 -attr oid 1448 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#440} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#440" {A(0)} -attr @path {/sobel/sobel:core/exs#70.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#440" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#70.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#440" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#70.itm}
+load net {ACC1:acc#375.itm(2)} -pin  "ACC1:acc#440" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1531.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#440" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1531.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#440" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1531.itm}
+load net {ACC1:acc#440.itm(0)} -pin  "ACC1:acc#440" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#440.itm}
+load net {ACC1:acc#440.itm(1)} -pin  "ACC1:acc#440" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#440.itm}
+load net {ACC1:acc#440.itm(2)} -pin  "ACC1:acc#440" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#440.itm}
+load net {ACC1:acc#440.itm(3)} -pin  "ACC1:acc#440" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#440.itm}
+load inst "ACC1:acc#532" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64259 -attr oid 1449 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#441.itm(1)} -pin  "ACC1:acc#532" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#109.itm}
+load net {ACC1:acc#441.itm(2)} -pin  "ACC1:acc#532" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#109.itm}
+load net {ACC1:acc#441.itm(3)} -pin  "ACC1:acc#532" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#109.itm}
+load net {ACC1:acc#440.itm(1)} -pin  "ACC1:acc#532" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#108.itm}
+load net {ACC1:acc#440.itm(2)} -pin  "ACC1:acc#532" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#108.itm}
+load net {ACC1:acc#440.itm(3)} -pin  "ACC1:acc#532" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#108.itm}
+load net {ACC1:acc#532.itm(0)} -pin  "ACC1:acc#532" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#532.itm(1)} -pin  "ACC1:acc#532" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#532.itm(2)} -pin  "ACC1:acc#532" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#532.itm(3)} -pin  "ACC1:acc#532" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load inst "ACC1-3:not#92" "not(1)" "INTERFACE" -attr xrf 64260 -attr oid 1450 -attr @path {/sobel/sobel:core/ACC1-3:not#92} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#415.itm(2)} -pin  "ACC1-3:not#92" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#2.itm}
+load net {ACC1-3:not#92.itm} -pin  "ACC1-3:not#92" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#92.itm}
+load inst "ACC1-3:and#5" "and(3,1)" "INTERFACE" -attr xrf 64261 -attr oid 1451 -attr @path {/sobel/sobel:core/ACC1-3:and#5} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1-3:and#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#24.itm}
+load net {ACC1-3:not#92.itm} -pin  "ACC1-3:and#5" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#92.itm}
+load net {ACC1:acc#415.itm(1)} -pin  "ACC1-3:and#5" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#1.itm}
+load net {ACC1-3:and#5.itm} -pin  "ACC1-3:and#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#5.itm}
+load inst "ACC1:acc#439" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64262 -attr oid 1452 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#439} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#439" {A(0)} -attr @path {/sobel/sobel:core/exs#71.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#439" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#71.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#439" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#71.itm}
+load net {ACC1-3:and#5.itm} -pin  "ACC1:acc#439" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1533.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#439" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1533.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#439" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1533.itm}
+load net {ACC1:acc#439.itm(0)} -pin  "ACC1:acc#439" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#439.itm}
+load net {ACC1:acc#439.itm(1)} -pin  "ACC1:acc#439" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#439.itm}
+load net {ACC1:acc#439.itm(2)} -pin  "ACC1:acc#439" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#439.itm}
+load net {ACC1:acc#439.itm(3)} -pin  "ACC1:acc#439" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#439.itm}
+load inst "ACC1-3:not#91" "not(1)" "INTERFACE" -attr xrf 64263 -attr oid 1453 -attr @path {/sobel/sobel:core/ACC1-3:not#91} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1-3:not#91" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#25.itm}
+load net {ACC1-3:not#91.itm} -pin  "ACC1-3:not#91" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#91.itm}
+load inst "ACC1-3:nand#2" "nand(2,1)" "INTERFACE" -attr xrf 64264 -attr oid 1454 -attr @path {/sobel/sobel:core/ACC1-3:nand#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#415.itm(2)} -pin  "ACC1-3:nand#2" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva).itm}
+load net {ACC1-3:not#91.itm} -pin  "ACC1-3:nand#2" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#91.itm}
+load net {ACC1-3:nand#2.itm} -pin  "ACC1-3:nand#2" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand#2.itm}
+load inst "ACC1:acc#438" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64265 -attr oid 1455 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#438} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#438" {A(0)} -attr @path {/sobel/sobel:core/exs#72.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#438" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#72.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#438" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#72.itm}
+load net {ACC1-3:nand#2.itm} -pin  "ACC1:acc#438" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1535.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#438" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1535.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#438" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1535.itm}
+load net {ACC1:acc#438.itm(0)} -pin  "ACC1:acc#438" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#438.itm}
+load net {ACC1:acc#438.itm(1)} -pin  "ACC1:acc#438" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#438.itm}
+load net {ACC1:acc#438.itm(2)} -pin  "ACC1:acc#438" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#438.itm}
+load net {ACC1:acc#438.itm(3)} -pin  "ACC1:acc#438" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#438.itm}
+load inst "ACC1:acc#531" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64266 -attr oid 1456 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#439.itm(1)} -pin  "ACC1:acc#531" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#107.itm}
+load net {ACC1:acc#439.itm(2)} -pin  "ACC1:acc#531" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#107.itm}
+load net {ACC1:acc#439.itm(3)} -pin  "ACC1:acc#531" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#107.itm}
+load net {ACC1:acc#438.itm(1)} -pin  "ACC1:acc#531" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#106.itm}
+load net {ACC1:acc#438.itm(2)} -pin  "ACC1:acc#531" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#106.itm}
+load net {ACC1:acc#438.itm(3)} -pin  "ACC1:acc#531" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#106.itm}
+load net {ACC1:acc#531.itm(0)} -pin  "ACC1:acc#531" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#531.itm(1)} -pin  "ACC1:acc#531" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#531.itm(2)} -pin  "ACC1:acc#531" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#531.itm(3)} -pin  "ACC1:acc#531" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load inst "ACC1:acc#581" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64267 -attr oid 1457 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#532.itm(0)} -pin  "ACC1:acc#581" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#532.itm(1)} -pin  "ACC1:acc#581" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#532.itm(2)} -pin  "ACC1:acc#581" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#532.itm(3)} -pin  "ACC1:acc#581" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#532.itm}
+load net {ACC1:acc#531.itm(0)} -pin  "ACC1:acc#581" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#531.itm(1)} -pin  "ACC1:acc#581" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#531.itm(2)} -pin  "ACC1:acc#581" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#531.itm(3)} -pin  "ACC1:acc#581" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#531.itm}
+load net {ACC1:acc#581.itm(0)} -pin  "ACC1:acc#581" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(1)} -pin  "ACC1:acc#581" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(2)} -pin  "ACC1:acc#581" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(3)} -pin  "ACC1:acc#581" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(4)} -pin  "ACC1:acc#581" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load inst "ACC1:acc#437" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64268 -attr oid 1458 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#437} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#437" {A(0)} -attr @path {/sobel/sobel:core/exs#73.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#437" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#73.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#437" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#73.itm}
+load net {ACC1:acc#414.itm(2)} -pin  "ACC1:acc#437" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1537.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#437" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1537.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#437" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1537.itm}
+load net {ACC1:acc#437.itm(0)} -pin  "ACC1:acc#437" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#437.itm}
+load net {ACC1:acc#437.itm(1)} -pin  "ACC1:acc#437" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#437.itm}
+load net {ACC1:acc#437.itm(2)} -pin  "ACC1:acc#437" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#437.itm}
+load net {ACC1:acc#437.itm(3)} -pin  "ACC1:acc#437" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#437.itm}
+load inst "ACC1:acc#436" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64269 -attr oid 1459 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#436} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#436" {A(0)} -attr @path {/sobel/sobel:core/exs#74.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#436" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#74.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#436" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#74.itm}
+load net {ACC1:acc#412.itm(4)} -pin  "ACC1:acc#436" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1539.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#436" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1539.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#436" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1539.itm}
+load net {ACC1:acc#436.itm(0)} -pin  "ACC1:acc#436" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#436.itm}
+load net {ACC1:acc#436.itm(1)} -pin  "ACC1:acc#436" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#436.itm}
+load net {ACC1:acc#436.itm(2)} -pin  "ACC1:acc#436" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#436.itm}
+load net {ACC1:acc#436.itm(3)} -pin  "ACC1:acc#436" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#436.itm}
+load inst "ACC1:acc#530" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64270 -attr oid 1460 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#437.itm(1)} -pin  "ACC1:acc#530" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#105.itm}
+load net {ACC1:acc#437.itm(2)} -pin  "ACC1:acc#530" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#105.itm}
+load net {ACC1:acc#437.itm(3)} -pin  "ACC1:acc#530" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#105.itm}
+load net {ACC1:acc#436.itm(1)} -pin  "ACC1:acc#530" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#104.itm}
+load net {ACC1:acc#436.itm(2)} -pin  "ACC1:acc#530" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#104.itm}
+load net {ACC1:acc#436.itm(3)} -pin  "ACC1:acc#530" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#104.itm}
+load net {ACC1:acc#530.itm(0)} -pin  "ACC1:acc#530" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#530.itm(1)} -pin  "ACC1:acc#530" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#530.itm(2)} -pin  "ACC1:acc#530" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#530.itm(3)} -pin  "ACC1:acc#530" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load inst "ACC1:acc#435" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64271 -attr oid 1461 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#435} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#435" {A(0)} -attr @path {/sobel/sobel:core/exs#75.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#435" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#75.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#435" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#75.itm}
+load net {ACC1:acc#412.itm(3)} -pin  "ACC1:acc#435" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1541.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#435" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1541.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#435" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1541.itm}
+load net {ACC1:acc#435.itm(0)} -pin  "ACC1:acc#435" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#435.itm}
+load net {ACC1:acc#435.itm(1)} -pin  "ACC1:acc#435" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#435.itm}
+load net {ACC1:acc#435.itm(2)} -pin  "ACC1:acc#435" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#435.itm}
+load net {ACC1:acc#435.itm(3)} -pin  "ACC1:acc#435" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#435.itm}
+load inst "ACC1:acc#434" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64272 -attr oid 1462 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#434} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#434" {A(0)} -attr @path {/sobel/sobel:core/exs#76.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#434" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#76.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#434" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#76.itm}
+load net {ACC1:acc#412.itm(2)} -pin  "ACC1:acc#434" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1543.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#434" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1543.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#434" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1543.itm}
+load net {ACC1:acc#434.itm(0)} -pin  "ACC1:acc#434" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#434.itm}
+load net {ACC1:acc#434.itm(1)} -pin  "ACC1:acc#434" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#434.itm}
+load net {ACC1:acc#434.itm(2)} -pin  "ACC1:acc#434" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#434.itm}
+load net {ACC1:acc#434.itm(3)} -pin  "ACC1:acc#434" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#434.itm}
+load inst "ACC1:acc#529" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64273 -attr oid 1463 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#435.itm(1)} -pin  "ACC1:acc#529" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#103.itm}
+load net {ACC1:acc#435.itm(2)} -pin  "ACC1:acc#529" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#103.itm}
+load net {ACC1:acc#435.itm(3)} -pin  "ACC1:acc#529" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#103.itm}
+load net {ACC1:acc#434.itm(1)} -pin  "ACC1:acc#529" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#102.itm}
+load net {ACC1:acc#434.itm(2)} -pin  "ACC1:acc#529" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#102.itm}
+load net {ACC1:acc#434.itm(3)} -pin  "ACC1:acc#529" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#102.itm}
+load net {ACC1:acc#529.itm(0)} -pin  "ACC1:acc#529" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#529.itm(1)} -pin  "ACC1:acc#529" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#529.itm(2)} -pin  "ACC1:acc#529" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#529.itm(3)} -pin  "ACC1:acc#529" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load inst "ACC1:acc#580" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64274 -attr oid 1464 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#530.itm(0)} -pin  "ACC1:acc#580" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#530.itm(1)} -pin  "ACC1:acc#580" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#530.itm(2)} -pin  "ACC1:acc#580" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#530.itm(3)} -pin  "ACC1:acc#580" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#530.itm}
+load net {ACC1:acc#529.itm(0)} -pin  "ACC1:acc#580" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#529.itm(1)} -pin  "ACC1:acc#580" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#529.itm(2)} -pin  "ACC1:acc#580" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#529.itm(3)} -pin  "ACC1:acc#580" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#529.itm}
+load net {ACC1:acc#580.itm(0)} -pin  "ACC1:acc#580" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(1)} -pin  "ACC1:acc#580" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(2)} -pin  "ACC1:acc#580" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(3)} -pin  "ACC1:acc#580" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(4)} -pin  "ACC1:acc#580" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load inst "ACC1:acc#605" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 64275 -attr oid 1465 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#581.itm(0)} -pin  "ACC1:acc#605" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(1)} -pin  "ACC1:acc#605" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(2)} -pin  "ACC1:acc#605" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(3)} -pin  "ACC1:acc#605" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#581.itm(4)} -pin  "ACC1:acc#605" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#581.itm}
+load net {ACC1:acc#580.itm(0)} -pin  "ACC1:acc#605" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(1)} -pin  "ACC1:acc#605" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(2)} -pin  "ACC1:acc#605" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(3)} -pin  "ACC1:acc#605" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#580.itm(4)} -pin  "ACC1:acc#605" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#580.itm}
+load net {ACC1:acc#605.itm(0)} -pin  "ACC1:acc#605" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(1)} -pin  "ACC1:acc#605" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(2)} -pin  "ACC1:acc#605" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(3)} -pin  "ACC1:acc#605" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(4)} -pin  "ACC1:acc#605" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(5)} -pin  "ACC1:acc#605" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load inst "ACC1-3:not#28" "not(1)" "INTERFACE" -attr xrf 64276 -attr oid 1466 -attr @path {/sobel/sobel:core/ACC1-3:not#28} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#396.itm(2)} -pin  "ACC1-3:not#28" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#2.itm}
+load net {ACC1-3:not#28.itm} -pin  "ACC1-3:not#28" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#28.itm}
+load inst "ACC1-3:and#1" "and(3,1)" "INTERFACE" -attr xrf 64277 -attr oid 1467 -attr @path {/sobel/sobel:core/ACC1-3:and#1} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:and#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#31.itm}
+load net {ACC1-3:not#28.itm} -pin  "ACC1-3:and#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#28.itm}
+load net {ACC1:acc#396.itm(1)} -pin  "ACC1-3:and#1" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#1.itm}
+load net {ACC1-3:and#1.itm} -pin  "ACC1-3:and#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#1.itm}
+load inst "ACC1:acc#433" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64278 -attr oid 1468 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#433} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#433" {A(0)} -attr @path {/sobel/sobel:core/conc#939.itm}
+load net {ACC1:acc#227.psp.sva(1)} -pin  "ACC1:acc#433" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#939.itm}
+load net {ACC1:acc#227.psp.sva(3)} -pin  "ACC1:acc#433" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#939.itm}
+load net {ACC1-3:and#1.itm} -pin  "ACC1:acc#433" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1325.itm}
+load net {ACC1:acc#227.psp.sva(2)} -pin  "ACC1:acc#433" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1325.itm}
+load net {acc.psp#1.sva(3)} -pin  "ACC1:acc#433" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1325.itm}
+load net {ACC1:acc#433.itm(0)} -pin  "ACC1:acc#433" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#433.itm}
+load net {ACC1:acc#433.itm(1)} -pin  "ACC1:acc#433" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#433.itm}
+load net {ACC1:acc#433.itm(2)} -pin  "ACC1:acc#433" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#433.itm}
+load net {ACC1:acc#433.itm(3)} -pin  "ACC1:acc#433" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#433.itm}
+load inst "ACC1-3:not#315" "not(1)" "INTERFACE" -attr xrf 64279 -attr oid 1469 -attr @path {/sobel/sobel:core/ACC1-3:not#315} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:not#315" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#41.itm}
+load net {ACC1-3:not#315.itm} -pin  "ACC1-3:not#315" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#315.itm}
+load inst "ACC1-3:nand" "nand(2,1)" "INTERFACE" -attr xrf 64280 -attr oid 1470 -attr @path {/sobel/sobel:core/ACC1-3:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#396.itm(2)} -pin  "ACC1-3:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva).itm}
+load net {ACC1-3:not#315.itm} -pin  "ACC1-3:nand" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#315.itm}
+load net {ACC1-3:nand.itm} -pin  "ACC1-3:nand" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand.itm}
+load inst "ACC1:acc#432" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64281 -attr oid 1471 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#432} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#432" {A(0)} -attr @path {/sobel/sobel:core/conc#940.itm}
+load net {ACC1:acc#227.psp.sva(3)} -pin  "ACC1:acc#432" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#940.itm}
+load net {ACC1:acc#224.psp.sva(2)} -pin  "ACC1:acc#432" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#940.itm}
+load net {ACC1-3:nand.itm} -pin  "ACC1:acc#432" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1323.itm}
+load net {ACC1:acc#227.psp.sva(4)} -pin  "ACC1:acc#432" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1323.itm}
+load net {ACC1:acc#228.psp.sva(2)} -pin  "ACC1:acc#432" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1323.itm}
+load net {ACC1:acc#432.itm(0)} -pin  "ACC1:acc#432" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#432.itm}
+load net {ACC1:acc#432.itm(1)} -pin  "ACC1:acc#432" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#432.itm}
+load net {ACC1:acc#432.itm(2)} -pin  "ACC1:acc#432" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#432.itm}
+load net {ACC1:acc#432.itm(3)} -pin  "ACC1:acc#432" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#432.itm}
+load inst "ACC1:acc#528" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64282 -attr oid 1472 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#433.itm(1)} -pin  "ACC1:acc#528" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#101.itm}
+load net {ACC1:acc#433.itm(2)} -pin  "ACC1:acc#528" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#101.itm}
+load net {ACC1:acc#433.itm(3)} -pin  "ACC1:acc#528" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#101.itm}
+load net {ACC1:acc#432.itm(1)} -pin  "ACC1:acc#528" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#100.itm}
+load net {ACC1:acc#432.itm(2)} -pin  "ACC1:acc#528" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#100.itm}
+load net {ACC1:acc#432.itm(3)} -pin  "ACC1:acc#528" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#100.itm}
+load net {ACC1:acc#528.itm(0)} -pin  "ACC1:acc#528" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#528.itm(1)} -pin  "ACC1:acc#528" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#528.itm(2)} -pin  "ACC1:acc#528" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#528.itm(3)} -pin  "ACC1:acc#528" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load inst "ACC1:acc#431" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64283 -attr oid 1473 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#431} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#431" {A(0)} -attr @path {/sobel/sobel:core/conc#941.itm}
+load net {acc.psp#1.sva(1)} -pin  "ACC1:acc#431" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#941.itm}
+load net {ACC1:acc#226.psp.sva(2)} -pin  "ACC1:acc#431" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#941.itm}
+load net {ACC1:acc#395.itm(2)} -pin  "ACC1:acc#431" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1321.itm}
+load net {acc.psp#1.sva(3)} -pin  "ACC1:acc#431" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1321.itm}
+load net {ACC1:acc#224.psp#1.sva(2)} -pin  "ACC1:acc#431" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1321.itm}
+load net {ACC1:acc#431.itm(0)} -pin  "ACC1:acc#431" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#431.itm}
+load net {ACC1:acc#431.itm(1)} -pin  "ACC1:acc#431" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#431.itm}
+load net {ACC1:acc#431.itm(2)} -pin  "ACC1:acc#431" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#431.itm}
+load net {ACC1:acc#431.itm(3)} -pin  "ACC1:acc#431" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#431.itm}
+load inst "ACC1:acc#430" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64284 -attr oid 1474 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#430} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#430" {A(0)} -attr @path {/sobel/sobel:core/conc#942.itm}
+load net {acc.psp#1.sva(4)} -pin  "ACC1:acc#430" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#942.itm}
+load net {ACC1-1:acc#25.psp.sva(3)} -pin  "ACC1:acc#430" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#942.itm}
+load net {ACC1:acc#210.psp#1.sva(3)} -pin  "ACC1:acc#430" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1319.itm}
+load net {ACC1:acc#224.psp.sva(1)} -pin  "ACC1:acc#430" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1319.itm}
+load net {acc#20.psp#1.sva(1)} -pin  "ACC1:acc#430" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1319.itm}
+load net {ACC1:acc#430.itm(0)} -pin  "ACC1:acc#430" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#430.itm}
+load net {ACC1:acc#430.itm(1)} -pin  "ACC1:acc#430" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#430.itm}
+load net {ACC1:acc#430.itm(2)} -pin  "ACC1:acc#430" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#430.itm}
+load net {ACC1:acc#430.itm(3)} -pin  "ACC1:acc#430" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#430.itm}
+load inst "ACC1:acc#527" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64285 -attr oid 1475 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#431.itm(1)} -pin  "ACC1:acc#527" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#431.itm(2)} -pin  "ACC1:acc#527" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#431.itm(3)} -pin  "ACC1:acc#527" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#430.itm(1)} -pin  "ACC1:acc#527" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#430.itm(2)} -pin  "ACC1:acc#527" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#430.itm(3)} -pin  "ACC1:acc#527" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#527.itm(0)} -pin  "ACC1:acc#527" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#527.itm(1)} -pin  "ACC1:acc#527" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#527.itm(2)} -pin  "ACC1:acc#527" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#527.itm(3)} -pin  "ACC1:acc#527" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load inst "ACC1:acc#579" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64286 -attr oid 1476 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#528.itm(0)} -pin  "ACC1:acc#579" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#528.itm(1)} -pin  "ACC1:acc#579" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#528.itm(2)} -pin  "ACC1:acc#579" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#528.itm(3)} -pin  "ACC1:acc#579" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#528.itm}
+load net {ACC1:acc#527.itm(0)} -pin  "ACC1:acc#579" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#527.itm(1)} -pin  "ACC1:acc#579" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#527.itm(2)} -pin  "ACC1:acc#579" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#527.itm(3)} -pin  "ACC1:acc#579" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#527.itm}
+load net {ACC1:acc#579.itm(0)} -pin  "ACC1:acc#579" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(1)} -pin  "ACC1:acc#579" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(2)} -pin  "ACC1:acc#579" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(3)} -pin  "ACC1:acc#579" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(4)} -pin  "ACC1:acc#579" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load inst "ACC1:acc#429" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64287 -attr oid 1477 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#429} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#429" {A(0)} -attr @path {/sobel/sobel:core/conc#943.itm}
+load net {ACC1:acc#224.psp.sva(2)} -pin  "ACC1:acc#429" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#943.itm}
+load net {acc#20.psp#1.sva(2)} -pin  "ACC1:acc#429" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#943.itm}
+load net {ACC1:acc#210.psp#1.sva(2)} -pin  "ACC1:acc#429" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1317.itm}
+load net {ACC1:acc#224.psp.sva(3)} -pin  "ACC1:acc#429" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1317.itm}
+load net {acc#20.psp#1.sva(3)} -pin  "ACC1:acc#429" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1317.itm}
+load net {ACC1:acc#429.itm(0)} -pin  "ACC1:acc#429" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#429.itm}
+load net {ACC1:acc#429.itm(1)} -pin  "ACC1:acc#429" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#429.itm}
+load net {ACC1:acc#429.itm(2)} -pin  "ACC1:acc#429" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#429.itm}
+load net {ACC1:acc#429.itm(3)} -pin  "ACC1:acc#429" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#429.itm}
+load inst "ACC1:acc#428" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64288 -attr oid 1478 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#428} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#428" {A(0)} -attr @path {/sobel/sobel:core/conc#944.itm}
+load net {ACC1:acc#228.psp.sva(0)} -pin  "ACC1:acc#428" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#944.itm}
+load net {acc#20.psp#1.sva(4)} -pin  "ACC1:acc#428" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#944.itm}
+load net {ACC1:acc#210.psp#1.sva(1)} -pin  "ACC1:acc#428" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1315.itm}
+load net {ACC1:acc#226.psp.sva(0)} -pin  "ACC1:acc#428" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1315.itm}
+load net {ACC1:acc#217.psp#1.sva(1)} -pin  "ACC1:acc#428" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1315.itm}
+load net {ACC1:acc#428.itm(0)} -pin  "ACC1:acc#428" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#428.itm}
+load net {ACC1:acc#428.itm(1)} -pin  "ACC1:acc#428" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#428.itm}
+load net {ACC1:acc#428.itm(2)} -pin  "ACC1:acc#428" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#428.itm}
+load net {ACC1:acc#428.itm(3)} -pin  "ACC1:acc#428" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#428.itm}
+load inst "ACC1:acc#526" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64289 -attr oid 1479 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#429.itm(1)} -pin  "ACC1:acc#526" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#429.itm(2)} -pin  "ACC1:acc#526" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#429.itm(3)} -pin  "ACC1:acc#526" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#428.itm(1)} -pin  "ACC1:acc#526" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#428.itm(2)} -pin  "ACC1:acc#526" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#428.itm(3)} -pin  "ACC1:acc#526" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#526.itm(0)} -pin  "ACC1:acc#526" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#526.itm(1)} -pin  "ACC1:acc#526" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#526.itm(2)} -pin  "ACC1:acc#526" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#526.itm(3)} -pin  "ACC1:acc#526" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load inst "ACC1:acc#427" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64290 -attr oid 1480 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#427} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#427" {A(0)} -attr @path {/sobel/sobel:core/conc#945.itm}
+load net {ACC1:acc#226.psp.sva(1)} -pin  "ACC1:acc#427" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#945.itm}
+load net {ACC1:acc#217.psp#1.sva(2)} -pin  "ACC1:acc#427" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#945.itm}
+load net {ACC1-1:acc#25.psp.sva(4)} -pin  "ACC1:acc#427" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1313.itm}
+load net {ACC1:acc#226.psp.sva(2)} -pin  "ACC1:acc#427" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1313.itm}
+load net {ACC1:acc#217.psp#1.sva(3)} -pin  "ACC1:acc#427" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1313.itm}
+load net {ACC1:acc#427.itm(0)} -pin  "ACC1:acc#427" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#427.itm}
+load net {ACC1:acc#427.itm(1)} -pin  "ACC1:acc#427" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#427.itm}
+load net {ACC1:acc#427.itm(2)} -pin  "ACC1:acc#427" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#427.itm}
+load net {ACC1:acc#427.itm(3)} -pin  "ACC1:acc#427" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#427.itm}
+load inst "ACC1-3:not#313" "not(1)" "INTERFACE" -attr xrf 64291 -attr oid 1481 -attr @path {/sobel/sobel:core/ACC1-3:not#313} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1-3:not#313" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#33.itm}
+load net {ACC1-3:not#313.itm} -pin  "ACC1-3:not#313" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#313.itm}
+load inst "ACC1-3:nand#4" "nand(2,1)" "INTERFACE" -attr xrf 64292 -attr oid 1482 -attr @path {/sobel/sobel:core/ACC1-3:nand#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#424.itm(2)} -pin  "ACC1-3:nand#4" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#19.sva)#2.itm}
+load net {ACC1-3:not#313.itm} -pin  "ACC1-3:nand#4" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#313.itm}
+load net {ACC1-3:nand#4.itm} -pin  "ACC1-3:nand#4" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand#4.itm}
+load inst "ACC1:acc#426" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64293 -attr oid 1483 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#426} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#426" {A(0)} -attr @path {/sobel/sobel:core/conc#946.itm}
+load net {ACC1:acc#226.psp.sva(3)} -pin  "ACC1:acc#426" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#946.itm}
+load net {ACC1:acc#423.itm(2)} -pin  "ACC1:acc#426" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#946.itm}
+load net {ACC1-1:acc#25.psp.sva(3)} -pin  "ACC1:acc#426" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1311.itm}
+load net {ACC1:acc#224.psp#1.sva(0)} -pin  "ACC1:acc#426" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1311.itm}
+load net {ACC1-3:nand#4.itm} -pin  "ACC1:acc#426" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1311.itm}
+load net {ACC1:acc#426.itm(0)} -pin  "ACC1:acc#426" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#426.itm}
+load net {ACC1:acc#426.itm(1)} -pin  "ACC1:acc#426" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#426.itm}
+load net {ACC1:acc#426.itm(2)} -pin  "ACC1:acc#426" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#426.itm}
+load net {ACC1:acc#426.itm(3)} -pin  "ACC1:acc#426" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#426.itm}
+load inst "ACC1:acc#525" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64294 -attr oid 1484 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#427.itm(1)} -pin  "ACC1:acc#525" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#427.itm(2)} -pin  "ACC1:acc#525" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#427.itm(3)} -pin  "ACC1:acc#525" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#426.itm(1)} -pin  "ACC1:acc#525" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#426.itm(2)} -pin  "ACC1:acc#525" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#426.itm(3)} -pin  "ACC1:acc#525" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#525.itm(0)} -pin  "ACC1:acc#525" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#525.itm(1)} -pin  "ACC1:acc#525" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#525.itm(2)} -pin  "ACC1:acc#525" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#525.itm(3)} -pin  "ACC1:acc#525" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load inst "ACC1:acc#578" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64295 -attr oid 1485 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#526.itm(0)} -pin  "ACC1:acc#578" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#526.itm(1)} -pin  "ACC1:acc#578" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#526.itm(2)} -pin  "ACC1:acc#578" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#526.itm(3)} -pin  "ACC1:acc#578" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#526.itm}
+load net {ACC1:acc#525.itm(0)} -pin  "ACC1:acc#578" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#525.itm(1)} -pin  "ACC1:acc#578" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#525.itm(2)} -pin  "ACC1:acc#578" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#525.itm(3)} -pin  "ACC1:acc#578" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#525.itm}
+load net {ACC1:acc#578.itm(0)} -pin  "ACC1:acc#578" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(1)} -pin  "ACC1:acc#578" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(2)} -pin  "ACC1:acc#578" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(3)} -pin  "ACC1:acc#578" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(4)} -pin  "ACC1:acc#578" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load inst "ACC1:acc#604" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 64296 -attr oid 1486 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#579.itm(0)} -pin  "ACC1:acc#604" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(1)} -pin  "ACC1:acc#604" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(2)} -pin  "ACC1:acc#604" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(3)} -pin  "ACC1:acc#604" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#579.itm(4)} -pin  "ACC1:acc#604" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#579.itm}
+load net {ACC1:acc#578.itm(0)} -pin  "ACC1:acc#604" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(1)} -pin  "ACC1:acc#604" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(2)} -pin  "ACC1:acc#604" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(3)} -pin  "ACC1:acc#604" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#578.itm(4)} -pin  "ACC1:acc#604" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#578.itm}
+load net {ACC1:acc#604.itm(0)} -pin  "ACC1:acc#604" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(1)} -pin  "ACC1:acc#604" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(2)} -pin  "ACC1:acc#604" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(3)} -pin  "ACC1:acc#604" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(4)} -pin  "ACC1:acc#604" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(5)} -pin  "ACC1:acc#604" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load inst "ACC1:acc#622" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 64297 -attr oid 1487 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#605.itm(0)} -pin  "ACC1:acc#622" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(1)} -pin  "ACC1:acc#622" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(2)} -pin  "ACC1:acc#622" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(3)} -pin  "ACC1:acc#622" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(4)} -pin  "ACC1:acc#622" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#605.itm(5)} -pin  "ACC1:acc#622" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#605.itm}
+load net {ACC1:acc#604.itm(0)} -pin  "ACC1:acc#622" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(1)} -pin  "ACC1:acc#622" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(2)} -pin  "ACC1:acc#622" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(3)} -pin  "ACC1:acc#622" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(4)} -pin  "ACC1:acc#622" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#604.itm(5)} -pin  "ACC1:acc#622" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#604.itm}
+load net {ACC1:acc#622.itm(0)} -pin  "ACC1:acc#622" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(1)} -pin  "ACC1:acc#622" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(2)} -pin  "ACC1:acc#622" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(3)} -pin  "ACC1:acc#622" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(4)} -pin  "ACC1:acc#622" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(5)} -pin  "ACC1:acc#622" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(6)} -pin  "ACC1:acc#622" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load inst "ACC1:acc#636" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 64298 -attr oid 1488 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#623.itm(0)} -pin  "ACC1:acc#636" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(1)} -pin  "ACC1:acc#636" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(2)} -pin  "ACC1:acc#636" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(3)} -pin  "ACC1:acc#636" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(4)} -pin  "ACC1:acc#636" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(5)} -pin  "ACC1:acc#636" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#623.itm(6)} -pin  "ACC1:acc#636" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#623.itm}
+load net {ACC1:acc#622.itm(0)} -pin  "ACC1:acc#636" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(1)} -pin  "ACC1:acc#636" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(2)} -pin  "ACC1:acc#636" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(3)} -pin  "ACC1:acc#636" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(4)} -pin  "ACC1:acc#636" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(5)} -pin  "ACC1:acc#636" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#622.itm(6)} -pin  "ACC1:acc#636" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#622.itm}
+load net {ACC1:acc#636.itm(0)} -pin  "ACC1:acc#636" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(1)} -pin  "ACC1:acc#636" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(2)} -pin  "ACC1:acc#636" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(3)} -pin  "ACC1:acc#636" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(4)} -pin  "ACC1:acc#636" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(5)} -pin  "ACC1:acc#636" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(6)} -pin  "ACC1:acc#636" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(7)} -pin  "ACC1:acc#636" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load inst "ACC1:acc#721" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64299 -attr oid 1489 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#721} -attr area 4.303074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {acc#20.psp#1.sva(6)} -pin  "ACC1:acc#721" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#947.itm}
+load net {GND} -pin  "ACC1:acc#721" {A(1)} -attr @path {/sobel/sobel:core/conc#947.itm}
+load net {acc#20.psp#1.sva(6)} -pin  "ACC1:acc#721" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#947.itm}
+load net {ACC1:acc#226.psp.sva(4)} -pin  "ACC1:acc#721" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1119.itm}
+load net {acc#20.psp#1.sva(5)} -pin  "ACC1:acc#721" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1119.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#721" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1119.itm}
+load net {ACC1:acc#721.itm(0)} -pin  "ACC1:acc#721" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#721.itm}
+load net {ACC1:acc#721.itm(1)} -pin  "ACC1:acc#721" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#721.itm}
+load net {ACC1:acc#721.itm(2)} -pin  "ACC1:acc#721" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#721.itm}
+load net {ACC1:acc#721.itm(3)} -pin  "ACC1:acc#721" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#721.itm}
+load inst "ACC1:acc#722" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64300 -attr oid 1490 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#722} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#228.psp.sva(1)} -pin  "ACC1:acc#722" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1453.itm}
+load net {acc#20.psp#1.sva(6)} -pin  "ACC1:acc#722" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1453.itm}
+load net {ACC1:acc#224.psp.sva(10)} -pin  "ACC1:acc#722" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1544.itm}
+load net {ACC1:acc#224.psp.sva(10)} -pin  "ACC1:acc#722" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1544.itm}
+load net {ACC1:acc#722.itm(0)} -pin  "ACC1:acc#722" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#722.itm}
+load net {ACC1:acc#722.itm(1)} -pin  "ACC1:acc#722" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#722.itm}
+load net {ACC1:acc#722.itm(2)} -pin  "ACC1:acc#722" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#722.itm}
+load inst "ACC1:acc#723" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64301 -attr oid 1491 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#723} -attr area 4.303074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#226.psp.sva(6)} -pin  "ACC1:acc#723" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1120.itm}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1:acc#723" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1120.itm}
+load net {ACC1:acc#224.psp.sva(6)} -pin  "ACC1:acc#723" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1120.itm}
+load net {ACC1:acc#227.psp.sva(5)} -pin  "ACC1:acc#723" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#948.itm}
+load net {GND} -pin  "ACC1:acc#723" {B(1)} -attr @path {/sobel/sobel:core/conc#948.itm}
+load net {ACC1:acc#228.psp.sva(6)} -pin  "ACC1:acc#723" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#948.itm}
+load net {ACC1:acc#723.itm(0)} -pin  "ACC1:acc#723" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#723.itm}
+load net {ACC1:acc#723.itm(1)} -pin  "ACC1:acc#723" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#723.itm}
+load net {ACC1:acc#723.itm(2)} -pin  "ACC1:acc#723" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#723.itm}
+load net {ACC1:acc#723.itm(3)} -pin  "ACC1:acc#723" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#723.itm}
+load inst "ACC1:acc#634" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 64302 -attr oid 1492 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#722.itm(0)} -pin  "ACC1:acc#634" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#722.itm(1)} -pin  "ACC1:acc#634" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#722.itm(2)} -pin  "ACC1:acc#634" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#721.itm(0)} -pin  "ACC1:acc#634" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#721.itm(1)} -pin  "ACC1:acc#634" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#721.itm(2)} -pin  "ACC1:acc#634" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#721.itm(3)} -pin  "ACC1:acc#634" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1452.itm}
+load net {ACC1:acc#724.cse(0)} -pin  "ACC1:acc#634" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#724.cse(1)} -pin  "ACC1:acc#634" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#724.cse(2)} -pin  "ACC1:acc#634" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#723.itm(0)} -pin  "ACC1:acc#634" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#723.itm(1)} -pin  "ACC1:acc#634" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#723.itm(2)} -pin  "ACC1:acc#634" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#723.itm(3)} -pin  "ACC1:acc#634" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1454.itm}
+load net {ACC1:acc#634.itm(0)} -pin  "ACC1:acc#634" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(1)} -pin  "ACC1:acc#634" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(2)} -pin  "ACC1:acc#634" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(3)} -pin  "ACC1:acc#634" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(4)} -pin  "ACC1:acc#634" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(5)} -pin  "ACC1:acc#634" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(6)} -pin  "ACC1:acc#634" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(7)} -pin  "ACC1:acc#634" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load inst "ACC1:acc#644" "add(8,0,8,0,9)" "INTERFACE" -attr xrf 64303 -attr oid 1493 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9)"
+load net {ACC1:acc#636.itm(0)} -pin  "ACC1:acc#644" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(1)} -pin  "ACC1:acc#644" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(2)} -pin  "ACC1:acc#644" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(3)} -pin  "ACC1:acc#644" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(4)} -pin  "ACC1:acc#644" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(5)} -pin  "ACC1:acc#644" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(6)} -pin  "ACC1:acc#644" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#636.itm(7)} -pin  "ACC1:acc#644" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#636.itm}
+load net {ACC1:acc#634.itm(0)} -pin  "ACC1:acc#644" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(1)} -pin  "ACC1:acc#644" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(2)} -pin  "ACC1:acc#644" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(3)} -pin  "ACC1:acc#644" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(4)} -pin  "ACC1:acc#644" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(5)} -pin  "ACC1:acc#644" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(6)} -pin  "ACC1:acc#644" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#634.itm(7)} -pin  "ACC1:acc#644" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#634.itm}
+load net {ACC1:acc#644.itm(0)} -pin  "ACC1:acc#644" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(1)} -pin  "ACC1:acc#644" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(2)} -pin  "ACC1:acc#644" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(3)} -pin  "ACC1:acc#644" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(4)} -pin  "ACC1:acc#644" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(5)} -pin  "ACC1:acc#644" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(6)} -pin  "ACC1:acc#644" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(7)} -pin  "ACC1:acc#644" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(8)} -pin  "ACC1:acc#644" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load inst "ACC1:acc#725" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 64304 -attr oid 1494 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#725} -attr area 2.320458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#226.psp.sva(6)} -pin  "ACC1:acc#725" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#36.itm}
+load net {ACC1:acc#224.psp#1.sva(6)} -pin  "ACC1:acc#725" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#42.itm}
+load net {ACC1:acc#725.itm(0)} -pin  "ACC1:acc#725" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#725.itm}
+load net {ACC1:acc#725.itm(1)} -pin  "ACC1:acc#725" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#725.itm}
+load inst "ACC1:acc#726" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 64305 -attr oid 1495 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#726} -attr area 2.320458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#227.psp.sva(7)} -pin  "ACC1:acc#726" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#2.itm}
+load net {acc.psp#1.sva(5)} -pin  "ACC1:acc#726" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#9.itm}
+load net {ACC1:acc#726.itm(0)} -pin  "ACC1:acc#726" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#726.itm}
+load net {ACC1:acc#726.itm(1)} -pin  "ACC1:acc#726" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#726.itm}
+load inst "ACC1:acc#728" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 64306 -attr oid 1496 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#728} -attr area 2.320458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1-1:acc#25.psp.sva(7)} -pin  "ACC1:acc#728" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#19.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#728" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#81.itm}
+load net {ACC1:acc#728.itm(0)} -pin  "ACC1:acc#728" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#728.itm}
+load net {ACC1:acc#728.itm(1)} -pin  "ACC1:acc#728" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#728.itm}
+load inst "ACC1:acc#729" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 64307 -attr oid 1497 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#729} -attr area 2.320458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#729" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#8.itm}
+load net {ACC1:acc#224.psp.sva(4)} -pin  "ACC1:acc#729" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#41.itm}
+load net {ACC1:acc#729.itm(0)} -pin  "ACC1:acc#729" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#729.itm}
+load net {ACC1:acc#729.itm(1)} -pin  "ACC1:acc#729" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#729.itm}
+load inst "ACC1:acc#633" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 64308 -attr oid 1498 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#724.cse(0)} -pin  "ACC1:acc#633" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#724.cse(1)} -pin  "ACC1:acc#633" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#724.cse(2)} -pin  "ACC1:acc#633" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#726.itm(0)} -pin  "ACC1:acc#633" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#726.itm(1)} -pin  "ACC1:acc#633" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#725.itm(0)} -pin  "ACC1:acc#633" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#725.itm(1)} -pin  "ACC1:acc#633" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1455.itm}
+load net {ACC1:acc#724.cse(0)} -pin  "ACC1:acc#633" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#724.cse(1)} -pin  "ACC1:acc#633" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#724.cse(2)} -pin  "ACC1:acc#633" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#729.itm(0)} -pin  "ACC1:acc#633" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#729.itm(1)} -pin  "ACC1:acc#633" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#728.itm(0)} -pin  "ACC1:acc#633" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#728.itm(1)} -pin  "ACC1:acc#633" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1456.itm}
+load net {ACC1:acc#633.itm(0)} -pin  "ACC1:acc#633" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(1)} -pin  "ACC1:acc#633" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(2)} -pin  "ACC1:acc#633" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(3)} -pin  "ACC1:acc#633" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(4)} -pin  "ACC1:acc#633" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(5)} -pin  "ACC1:acc#633" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(6)} -pin  "ACC1:acc#633" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(7)} -pin  "ACC1:acc#633" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load inst "ACC1:acc#632" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 64309 -attr oid 1499 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#632" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1032.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#632" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1029.itm}
+load net {ACC1:acc#632.itm(0)} -pin  "ACC1:acc#632" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(1)} -pin  "ACC1:acc#632" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(2)} -pin  "ACC1:acc#632" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(3)} -pin  "ACC1:acc#632" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(4)} -pin  "ACC1:acc#632" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(5)} -pin  "ACC1:acc#632" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(6)} -pin  "ACC1:acc#632" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(7)} -pin  "ACC1:acc#632" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load inst "ACC1:acc#643" "add(8,0,8,0,9)" "INTERFACE" -attr xrf 64310 -attr oid 1500 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9)"
+load net {ACC1:acc#633.itm(0)} -pin  "ACC1:acc#643" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(1)} -pin  "ACC1:acc#643" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(2)} -pin  "ACC1:acc#643" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(3)} -pin  "ACC1:acc#643" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(4)} -pin  "ACC1:acc#643" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(5)} -pin  "ACC1:acc#643" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(6)} -pin  "ACC1:acc#643" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#633.itm(7)} -pin  "ACC1:acc#643" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#633.itm}
+load net {ACC1:acc#632.itm(0)} -pin  "ACC1:acc#643" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(1)} -pin  "ACC1:acc#643" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(2)} -pin  "ACC1:acc#643" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(3)} -pin  "ACC1:acc#643" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(4)} -pin  "ACC1:acc#643" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(5)} -pin  "ACC1:acc#643" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(6)} -pin  "ACC1:acc#643" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#632.itm(7)} -pin  "ACC1:acc#643" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#632.itm}
+load net {ACC1:acc#643.itm(0)} -pin  "ACC1:acc#643" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(1)} -pin  "ACC1:acc#643" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(2)} -pin  "ACC1:acc#643" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(3)} -pin  "ACC1:acc#643" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(4)} -pin  "ACC1:acc#643" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(5)} -pin  "ACC1:acc#643" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(6)} -pin  "ACC1:acc#643" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(7)} -pin  "ACC1:acc#643" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(8)} -pin  "ACC1:acc#643" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load inst "ACC1:acc#649" "add(9,0,9,0,10)" "INTERFACE" -attr xrf 64311 -attr oid 1501 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649} -attr area 10.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,0,10)"
+load net {ACC1:acc#644.itm(0)} -pin  "ACC1:acc#649" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(1)} -pin  "ACC1:acc#649" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(2)} -pin  "ACC1:acc#649" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(3)} -pin  "ACC1:acc#649" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(4)} -pin  "ACC1:acc#649" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(5)} -pin  "ACC1:acc#649" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(6)} -pin  "ACC1:acc#649" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(7)} -pin  "ACC1:acc#649" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#644.itm(8)} -pin  "ACC1:acc#649" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#644.itm}
+load net {ACC1:acc#643.itm(0)} -pin  "ACC1:acc#649" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(1)} -pin  "ACC1:acc#649" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(2)} -pin  "ACC1:acc#649" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(3)} -pin  "ACC1:acc#649" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(4)} -pin  "ACC1:acc#649" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(5)} -pin  "ACC1:acc#649" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(6)} -pin  "ACC1:acc#649" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(7)} -pin  "ACC1:acc#649" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#643.itm(8)} -pin  "ACC1:acc#649" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#643.itm}
+load net {ACC1:acc#649.itm(0)} -pin  "ACC1:acc#649" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(1)} -pin  "ACC1:acc#649" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(2)} -pin  "ACC1:acc#649" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(3)} -pin  "ACC1:acc#649" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(4)} -pin  "ACC1:acc#649" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(5)} -pin  "ACC1:acc#649" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(6)} -pin  "ACC1:acc#649" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(7)} -pin  "ACC1:acc#649" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(8)} -pin  "ACC1:acc#649" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(9)} -pin  "ACC1:acc#649" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load inst "ACC1:acc#631" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 64312 -attr oid 1502 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#631" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1035.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#631" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1032.itm}
+load net {ACC1:acc#631.itm(0)} -pin  "ACC1:acc#631" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(1)} -pin  "ACC1:acc#631" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(2)} -pin  "ACC1:acc#631" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(3)} -pin  "ACC1:acc#631" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(4)} -pin  "ACC1:acc#631" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(5)} -pin  "ACC1:acc#631" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(6)} -pin  "ACC1:acc#631" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(7)} -pin  "ACC1:acc#631" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load inst "ACC1:acc#630" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 64313 -attr oid 1503 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {GND} -pin  "ACC1:acc#630" {A(2)} -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/exs#94.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#630" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1040.itm}
+load net {ACC1:acc#630.itm(0)} -pin  "ACC1:acc#630" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(1)} -pin  "ACC1:acc#630" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(2)} -pin  "ACC1:acc#630" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(3)} -pin  "ACC1:acc#630" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(4)} -pin  "ACC1:acc#630" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(5)} -pin  "ACC1:acc#630" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(6)} -pin  "ACC1:acc#630" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(7)} -pin  "ACC1:acc#630" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load inst "ACC1:acc#642" "add(8,0,8,0,9)" "INTERFACE" -attr xrf 64314 -attr oid 1504 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9)"
+load net {ACC1:acc#631.itm(0)} -pin  "ACC1:acc#642" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(1)} -pin  "ACC1:acc#642" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(2)} -pin  "ACC1:acc#642" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(3)} -pin  "ACC1:acc#642" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(4)} -pin  "ACC1:acc#642" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(5)} -pin  "ACC1:acc#642" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(6)} -pin  "ACC1:acc#642" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#631.itm(7)} -pin  "ACC1:acc#642" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#631.itm}
+load net {ACC1:acc#630.itm(0)} -pin  "ACC1:acc#642" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(1)} -pin  "ACC1:acc#642" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(2)} -pin  "ACC1:acc#642" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(3)} -pin  "ACC1:acc#642" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(4)} -pin  "ACC1:acc#642" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(5)} -pin  "ACC1:acc#642" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(6)} -pin  "ACC1:acc#642" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#630.itm(7)} -pin  "ACC1:acc#642" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#630.itm}
+load net {ACC1:acc#642.itm(0)} -pin  "ACC1:acc#642" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(1)} -pin  "ACC1:acc#642" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(2)} -pin  "ACC1:acc#642" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(3)} -pin  "ACC1:acc#642" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(4)} -pin  "ACC1:acc#642" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(5)} -pin  "ACC1:acc#642" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(6)} -pin  "ACC1:acc#642" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(7)} -pin  "ACC1:acc#642" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(8)} -pin  "ACC1:acc#642" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load inst "ACC1:acc#629" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 64315 -attr oid 1505 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#629" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#629" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {GND} -pin  "ACC1:acc#629" {A(2)} -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#629" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#629" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#629" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#629" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/exs#95.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#629" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1035.itm}
+load net {ACC1:acc#629.itm(0)} -pin  "ACC1:acc#629" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(1)} -pin  "ACC1:acc#629" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(2)} -pin  "ACC1:acc#629" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(3)} -pin  "ACC1:acc#629" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(4)} -pin  "ACC1:acc#629" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(5)} -pin  "ACC1:acc#629" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(6)} -pin  "ACC1:acc#629" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(7)} -pin  "ACC1:acc#629" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load inst "ACC1:acc#628" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 64316 -attr oid 1506 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#628" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#628" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {GND} -pin  "ACC1:acc#628" {A(2)} -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#628" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#628" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#628" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#628" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/exs#96.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#628" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1051.itm}
+load net {ACC1:acc#628.itm(0)} -pin  "ACC1:acc#628" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(1)} -pin  "ACC1:acc#628" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(2)} -pin  "ACC1:acc#628" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(3)} -pin  "ACC1:acc#628" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(4)} -pin  "ACC1:acc#628" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(5)} -pin  "ACC1:acc#628" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(6)} -pin  "ACC1:acc#628" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(7)} -pin  "ACC1:acc#628" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load inst "ACC1:acc#641" "add(8,0,8,0,9)" "INTERFACE" -attr xrf 64317 -attr oid 1507 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9)"
+load net {ACC1:acc#629.itm(0)} -pin  "ACC1:acc#641" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(1)} -pin  "ACC1:acc#641" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(2)} -pin  "ACC1:acc#641" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(3)} -pin  "ACC1:acc#641" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(4)} -pin  "ACC1:acc#641" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(5)} -pin  "ACC1:acc#641" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(6)} -pin  "ACC1:acc#641" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#629.itm(7)} -pin  "ACC1:acc#641" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#629.itm}
+load net {ACC1:acc#628.itm(0)} -pin  "ACC1:acc#641" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(1)} -pin  "ACC1:acc#641" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(2)} -pin  "ACC1:acc#641" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(3)} -pin  "ACC1:acc#641" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(4)} -pin  "ACC1:acc#641" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(5)} -pin  "ACC1:acc#641" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(6)} -pin  "ACC1:acc#641" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#628.itm(7)} -pin  "ACC1:acc#641" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#628.itm}
+load net {ACC1:acc#641.itm(0)} -pin  "ACC1:acc#641" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(1)} -pin  "ACC1:acc#641" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(2)} -pin  "ACC1:acc#641" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(3)} -pin  "ACC1:acc#641" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(4)} -pin  "ACC1:acc#641" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(5)} -pin  "ACC1:acc#641" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(6)} -pin  "ACC1:acc#641" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(7)} -pin  "ACC1:acc#641" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(8)} -pin  "ACC1:acc#641" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load inst "ACC1:acc#648" "add(9,0,9,0,10)" "INTERFACE" -attr xrf 64318 -attr oid 1508 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648} -attr area 10.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,0,10)"
+load net {ACC1:acc#642.itm(0)} -pin  "ACC1:acc#648" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(1)} -pin  "ACC1:acc#648" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(2)} -pin  "ACC1:acc#648" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(3)} -pin  "ACC1:acc#648" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(4)} -pin  "ACC1:acc#648" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(5)} -pin  "ACC1:acc#648" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(6)} -pin  "ACC1:acc#648" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(7)} -pin  "ACC1:acc#648" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#642.itm(8)} -pin  "ACC1:acc#648" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#642.itm}
+load net {ACC1:acc#641.itm(0)} -pin  "ACC1:acc#648" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(1)} -pin  "ACC1:acc#648" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(2)} -pin  "ACC1:acc#648" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(3)} -pin  "ACC1:acc#648" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(4)} -pin  "ACC1:acc#648" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(5)} -pin  "ACC1:acc#648" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(6)} -pin  "ACC1:acc#648" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(7)} -pin  "ACC1:acc#648" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#641.itm(8)} -pin  "ACC1:acc#648" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#641.itm}
+load net {ACC1:acc#648.itm(0)} -pin  "ACC1:acc#648" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(1)} -pin  "ACC1:acc#648" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(2)} -pin  "ACC1:acc#648" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(3)} -pin  "ACC1:acc#648" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(4)} -pin  "ACC1:acc#648" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(5)} -pin  "ACC1:acc#648" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(6)} -pin  "ACC1:acc#648" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(7)} -pin  "ACC1:acc#648" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(8)} -pin  "ACC1:acc#648" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(9)} -pin  "ACC1:acc#648" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load inst "ACC1:acc#652" "add(10,0,10,0,11)" "INTERFACE" -attr xrf 64319 -attr oid 1509 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652} -attr area 11.241230 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,11)"
+load net {ACC1:acc#649.itm(0)} -pin  "ACC1:acc#652" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(1)} -pin  "ACC1:acc#652" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(2)} -pin  "ACC1:acc#652" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(3)} -pin  "ACC1:acc#652" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(4)} -pin  "ACC1:acc#652" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(5)} -pin  "ACC1:acc#652" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(6)} -pin  "ACC1:acc#652" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(7)} -pin  "ACC1:acc#652" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(8)} -pin  "ACC1:acc#652" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#649.itm(9)} -pin  "ACC1:acc#652" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#649.itm}
+load net {ACC1:acc#648.itm(0)} -pin  "ACC1:acc#652" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(1)} -pin  "ACC1:acc#652" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(2)} -pin  "ACC1:acc#652" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(3)} -pin  "ACC1:acc#652" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(4)} -pin  "ACC1:acc#652" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(5)} -pin  "ACC1:acc#652" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(6)} -pin  "ACC1:acc#652" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(7)} -pin  "ACC1:acc#652" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(8)} -pin  "ACC1:acc#652" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#648.itm(9)} -pin  "ACC1:acc#652" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#648.itm}
+load net {ACC1:acc#652.itm(0)} -pin  "ACC1:acc#652" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(1)} -pin  "ACC1:acc#652" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(2)} -pin  "ACC1:acc#652" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(3)} -pin  "ACC1:acc#652" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(4)} -pin  "ACC1:acc#652" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(5)} -pin  "ACC1:acc#652" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(6)} -pin  "ACC1:acc#652" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(7)} -pin  "ACC1:acc#652" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(8)} -pin  "ACC1:acc#652" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(9)} -pin  "ACC1:acc#652" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(10)} -pin  "ACC1:acc#652" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load inst "reg(ACC1:acc#652.itm#1)" "reg(11,1,1,-1,0)" "INTERFACE" -attr xrf 64320 -attr oid 1510 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#652.itm#1)}
+load net {ACC1:acc#652.itm(0)} -pin  "reg(ACC1:acc#652.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(1)} -pin  "reg(ACC1:acc#652.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(2)} -pin  "reg(ACC1:acc#652.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(3)} -pin  "reg(ACC1:acc#652.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(4)} -pin  "reg(ACC1:acc#652.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(5)} -pin  "reg(ACC1:acc#652.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(6)} -pin  "reg(ACC1:acc#652.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(7)} -pin  "reg(ACC1:acc#652.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(8)} -pin  "reg(ACC1:acc#652.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(9)} -pin  "reg(ACC1:acc#652.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {ACC1:acc#652.itm(10)} -pin  "reg(ACC1:acc#652.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(ACC1:acc#652.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_11}
+load net {clk} -pin  "reg(ACC1:acc#652.itm#1)" {clk} -attr xrf 64321 -attr oid 1511 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#652.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#652.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#652.itm#1(0)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(1)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(2)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(3)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(4)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(5)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(6)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(7)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(8)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(9)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(10)} -pin  "reg(ACC1:acc#652.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load inst "ACC1:acc#564" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64322 -attr oid 1512 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#509.cse(0)} -pin  "ACC1:acc#564" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(1)} -pin  "ACC1:acc#564" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(2)} -pin  "ACC1:acc#564" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(0)} -pin  "ACC1:acc#564" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(1)} -pin  "ACC1:acc#564" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(2)} -pin  "ACC1:acc#564" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#564.itm(0)} -pin  "ACC1:acc#564" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#564.itm(1)} -pin  "ACC1:acc#564" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#564.itm(2)} -pin  "ACC1:acc#564" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#564.itm(3)} -pin  "ACC1:acc#564" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load inst "ACC1:acc#507" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64323 -attr oid 1513 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#507" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1058.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#507" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1058.itm}
+load net {ACC1:acc#227.psp.sva(5)} -pin  "ACC1:acc#507" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1031.itm}
+load net {ACC1:acc#227.psp.sva(5)} -pin  "ACC1:acc#507" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1031.itm}
+load net {ACC1:acc#507.itm(0)} -pin  "ACC1:acc#507" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load net {ACC1:acc#507.itm(1)} -pin  "ACC1:acc#507" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load net {ACC1:acc#507.itm(2)} -pin  "ACC1:acc#507" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load inst "ACC1:acc#563" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64324 -attr oid 1514 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#507.itm(0)} -pin  "ACC1:acc#563" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load net {ACC1:acc#507.itm(1)} -pin  "ACC1:acc#563" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load net {ACC1:acc#507.itm(2)} -pin  "ACC1:acc#563" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#507.itm}
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#563" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#563" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#563" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#563.itm(0)} -pin  "ACC1:acc#563" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#563.itm(1)} -pin  "ACC1:acc#563" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#563.itm(2)} -pin  "ACC1:acc#563" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#563.itm(3)} -pin  "ACC1:acc#563" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load inst "ACC1:acc#597" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64325 -attr oid 1515 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#564.itm(0)} -pin  "ACC1:acc#597" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#564.itm(1)} -pin  "ACC1:acc#597" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#564.itm(2)} -pin  "ACC1:acc#597" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#564.itm(3)} -pin  "ACC1:acc#597" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#564.itm}
+load net {ACC1:acc#563.itm(0)} -pin  "ACC1:acc#597" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#563.itm(1)} -pin  "ACC1:acc#597" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#563.itm(2)} -pin  "ACC1:acc#597" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#563.itm(3)} -pin  "ACC1:acc#597" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#563.itm}
+load net {ACC1:acc#597.itm(0)} -pin  "ACC1:acc#597" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(1)} -pin  "ACC1:acc#597" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(2)} -pin  "ACC1:acc#597" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(3)} -pin  "ACC1:acc#597" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(4)} -pin  "ACC1:acc#597" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load inst "ACC1:acc#561" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64326 -attr oid 1516 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#561" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#561" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#561" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#502.cse(0)} -pin  "ACC1:acc#561" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#502.cse(1)} -pin  "ACC1:acc#561" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#502.cse(2)} -pin  "ACC1:acc#561" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#561.itm(0)} -pin  "ACC1:acc#561" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#561.itm(1)} -pin  "ACC1:acc#561" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#561.itm(2)} -pin  "ACC1:acc#561" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#561.itm(3)} -pin  "ACC1:acc#561" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load inst "ACC1:acc#596" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64327 -attr oid 1517 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#562.ncse(0)} -pin  "ACC1:acc#596" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(1)} -pin  "ACC1:acc#596" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(2)} -pin  "ACC1:acc#596" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(3)} -pin  "ACC1:acc#596" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#561.itm(0)} -pin  "ACC1:acc#596" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#561.itm(1)} -pin  "ACC1:acc#596" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#561.itm(2)} -pin  "ACC1:acc#596" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#561.itm(3)} -pin  "ACC1:acc#596" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#561.itm}
+load net {ACC1:acc#596.itm(0)} -pin  "ACC1:acc#596" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(1)} -pin  "ACC1:acc#596" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(2)} -pin  "ACC1:acc#596" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(3)} -pin  "ACC1:acc#596" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(4)} -pin  "ACC1:acc#596" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load inst "ACC1:acc#613" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 64328 -attr oid 1518 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#597.itm(0)} -pin  "ACC1:acc#613" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(1)} -pin  "ACC1:acc#613" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(2)} -pin  "ACC1:acc#613" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(3)} -pin  "ACC1:acc#613" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#597.itm(4)} -pin  "ACC1:acc#613" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#597.itm}
+load net {ACC1:acc#596.itm(0)} -pin  "ACC1:acc#613" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(1)} -pin  "ACC1:acc#613" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(2)} -pin  "ACC1:acc#613" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(3)} -pin  "ACC1:acc#613" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#596.itm(4)} -pin  "ACC1:acc#613" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#596.itm}
+load net {ACC1:acc#613.itm(0)} -pin  "ACC1:acc#613" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(1)} -pin  "ACC1:acc#613" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(2)} -pin  "ACC1:acc#613" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(3)} -pin  "ACC1:acc#613" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(4)} -pin  "ACC1:acc#613" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(5)} -pin  "ACC1:acc#613" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load inst "ACC1:acc#499" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64329 -attr oid 1519 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#499" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1053.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#499" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1053.itm}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1:acc#499" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#72.itm}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1:acc#499" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#72.itm}
+load net {ACC1:acc#499.itm(0)} -pin  "ACC1:acc#499" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load net {ACC1:acc#499.itm(1)} -pin  "ACC1:acc#499" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load net {ACC1:acc#499.itm(2)} -pin  "ACC1:acc#499" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load inst "ACC1:acc#498" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64330 -attr oid 1520 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#498" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#73.itm}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#498" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#73.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#498" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1054.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#498" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1054.itm}
+load net {ACC1:acc#498.itm(0)} -pin  "ACC1:acc#498" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load net {ACC1:acc#498.itm(1)} -pin  "ACC1:acc#498" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load net {ACC1:acc#498.itm(2)} -pin  "ACC1:acc#498" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load inst "ACC1:acc#559" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64331 -attr oid 1521 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#499.itm(0)} -pin  "ACC1:acc#559" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load net {ACC1:acc#499.itm(1)} -pin  "ACC1:acc#559" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load net {ACC1:acc#499.itm(2)} -pin  "ACC1:acc#559" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#499.itm}
+load net {ACC1:acc#498.itm(0)} -pin  "ACC1:acc#559" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load net {ACC1:acc#498.itm(1)} -pin  "ACC1:acc#559" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load net {ACC1:acc#498.itm(2)} -pin  "ACC1:acc#559" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#498.itm}
+load net {ACC1:acc#559.itm(0)} -pin  "ACC1:acc#559" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#559.itm(1)} -pin  "ACC1:acc#559" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#559.itm(2)} -pin  "ACC1:acc#559" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#559.itm(3)} -pin  "ACC1:acc#559" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load inst "ACC1:acc#595" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64332 -attr oid 1522 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#562.ncse(0)} -pin  "ACC1:acc#595" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(1)} -pin  "ACC1:acc#595" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(2)} -pin  "ACC1:acc#595" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(3)} -pin  "ACC1:acc#595" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#559.itm(0)} -pin  "ACC1:acc#595" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#559.itm(1)} -pin  "ACC1:acc#595" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#559.itm(2)} -pin  "ACC1:acc#595" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#559.itm(3)} -pin  "ACC1:acc#595" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#559.itm}
+load net {ACC1:acc#595.itm(0)} -pin  "ACC1:acc#595" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(1)} -pin  "ACC1:acc#595" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(2)} -pin  "ACC1:acc#595" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(3)} -pin  "ACC1:acc#595" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(4)} -pin  "ACC1:acc#595" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load inst "ACC1:acc#594" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64333 -attr oid 1523 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#562.ncse(0)} -pin  "ACC1:acc#594" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(1)} -pin  "ACC1:acc#594" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(2)} -pin  "ACC1:acc#594" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(3)} -pin  "ACC1:acc#594" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(0)} -pin  "ACC1:acc#594" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(1)} -pin  "ACC1:acc#594" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(2)} -pin  "ACC1:acc#594" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(3)} -pin  "ACC1:acc#594" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#594.itm(0)} -pin  "ACC1:acc#594" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(1)} -pin  "ACC1:acc#594" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(2)} -pin  "ACC1:acc#594" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(3)} -pin  "ACC1:acc#594" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(4)} -pin  "ACC1:acc#594" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load inst "ACC1:acc#612" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 64334 -attr oid 1524 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#595.itm(0)} -pin  "ACC1:acc#612" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(1)} -pin  "ACC1:acc#612" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(2)} -pin  "ACC1:acc#612" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(3)} -pin  "ACC1:acc#612" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#595.itm(4)} -pin  "ACC1:acc#612" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#595.itm}
+load net {ACC1:acc#594.itm(0)} -pin  "ACC1:acc#612" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(1)} -pin  "ACC1:acc#612" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(2)} -pin  "ACC1:acc#612" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(3)} -pin  "ACC1:acc#612" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#594.itm(4)} -pin  "ACC1:acc#612" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#594.itm}
+load net {ACC1:acc#612.itm(0)} -pin  "ACC1:acc#612" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(1)} -pin  "ACC1:acc#612" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(2)} -pin  "ACC1:acc#612" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(3)} -pin  "ACC1:acc#612" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(4)} -pin  "ACC1:acc#612" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(5)} -pin  "ACC1:acc#612" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load inst "ACC1:acc#626" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 64335 -attr oid 1525 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#613.itm(0)} -pin  "ACC1:acc#626" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(1)} -pin  "ACC1:acc#626" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(2)} -pin  "ACC1:acc#626" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(3)} -pin  "ACC1:acc#626" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(4)} -pin  "ACC1:acc#626" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#613.itm(5)} -pin  "ACC1:acc#626" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#613.itm}
+load net {ACC1:acc#612.itm(0)} -pin  "ACC1:acc#626" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(1)} -pin  "ACC1:acc#626" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(2)} -pin  "ACC1:acc#626" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(3)} -pin  "ACC1:acc#626" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(4)} -pin  "ACC1:acc#626" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#612.itm(5)} -pin  "ACC1:acc#626" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#612.itm}
+load net {ACC1:acc#626.itm(0)} -pin  "ACC1:acc#626" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(1)} -pin  "ACC1:acc#626" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(2)} -pin  "ACC1:acc#626" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(3)} -pin  "ACC1:acc#626" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(4)} -pin  "ACC1:acc#626" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(5)} -pin  "ACC1:acc#626" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(6)} -pin  "ACC1:acc#626" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load inst "ACC1:acc#638" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 64336 -attr oid 1526 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1-1:acc#25.psp.sva(1)} -pin  "ACC1:acc#638" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {PWR} -pin  "ACC1:acc#638" {A(1)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {PWR} -pin  "ACC1:acc#638" {A(2)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {GND} -pin  "ACC1:acc#638" {A(3)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {PWR} -pin  "ACC1:acc#638" {A(4)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {PWR} -pin  "ACC1:acc#638" {A(5)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {GND} -pin  "ACC1:acc#638" {A(6)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {PWR} -pin  "ACC1:acc#638" {A(7)} -attr @path {/sobel/sobel:core/conc#956.itm}
+load net {ACC1:acc#626.itm(0)} -pin  "ACC1:acc#638" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(1)} -pin  "ACC1:acc#638" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(2)} -pin  "ACC1:acc#638" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(3)} -pin  "ACC1:acc#638" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(4)} -pin  "ACC1:acc#638" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(5)} -pin  "ACC1:acc#638" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#626.itm(6)} -pin  "ACC1:acc#638" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#626.itm}
+load net {ACC1:acc#638.itm(0)} -pin  "ACC1:acc#638" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(1)} -pin  "ACC1:acc#638" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(2)} -pin  "ACC1:acc#638" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(3)} -pin  "ACC1:acc#638" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(4)} -pin  "ACC1:acc#638" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(5)} -pin  "ACC1:acc#638" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(6)} -pin  "ACC1:acc#638" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(7)} -pin  "ACC1:acc#638" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load inst "ACC1:acc#556" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64337 -attr oid 1527 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#502.cse(0)} -pin  "ACC1:acc#556" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#502.cse(1)} -pin  "ACC1:acc#556" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#502.cse(2)} -pin  "ACC1:acc#556" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#556" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#556" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#556" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#556.itm(0)} -pin  "ACC1:acc#556" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#556.itm(1)} -pin  "ACC1:acc#556" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#556.itm(2)} -pin  "ACC1:acc#556" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#556.itm(3)} -pin  "ACC1:acc#556" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load inst "ACC1:acc#555" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64338 -attr oid 1528 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#555" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#555" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#555" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#489.cse(0)} -pin  "ACC1:acc#555" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(1)} -pin  "ACC1:acc#555" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(2)} -pin  "ACC1:acc#555" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#555.itm(0)} -pin  "ACC1:acc#555" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#555.itm(1)} -pin  "ACC1:acc#555" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#555.itm(2)} -pin  "ACC1:acc#555" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#555.itm(3)} -pin  "ACC1:acc#555" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load inst "ACC1:acc#593" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64339 -attr oid 1529 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#556.itm(0)} -pin  "ACC1:acc#593" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#556.itm(1)} -pin  "ACC1:acc#593" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#556.itm(2)} -pin  "ACC1:acc#593" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#556.itm(3)} -pin  "ACC1:acc#593" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#556.itm}
+load net {ACC1:acc#555.itm(0)} -pin  "ACC1:acc#593" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#555.itm(1)} -pin  "ACC1:acc#593" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#555.itm(2)} -pin  "ACC1:acc#593" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#555.itm(3)} -pin  "ACC1:acc#593" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#555.itm}
+load net {ACC1:acc#593.itm(0)} -pin  "ACC1:acc#593" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(1)} -pin  "ACC1:acc#593" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(2)} -pin  "ACC1:acc#593" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(3)} -pin  "ACC1:acc#593" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(4)} -pin  "ACC1:acc#593" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load inst "ACC1:acc#488" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64340 -attr oid 1530 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#226.psp.sva(6)} -pin  "ACC1:acc#488" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#90.itm}
+load net {ACC1:acc#226.psp.sva(6)} -pin  "ACC1:acc#488" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#90.itm}
+load net {ACC1:acc#226.psp.sva(8)} -pin  "ACC1:acc#488" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#91.itm}
+load net {ACC1:acc#226.psp.sva(8)} -pin  "ACC1:acc#488" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#91.itm}
+load net {ACC1:acc#488.itm(0)} -pin  "ACC1:acc#488" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load net {ACC1:acc#488.itm(1)} -pin  "ACC1:acc#488" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load net {ACC1:acc#488.itm(2)} -pin  "ACC1:acc#488" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load inst "ACC1:acc#487" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64341 -attr oid 1531 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#226.psp.sva(10)} -pin  "ACC1:acc#487" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#92.itm}
+load net {ACC1:acc#226.psp.sva(10)} -pin  "ACC1:acc#487" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#92.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#487" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1056.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#487" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1056.itm}
+load net {ACC1:acc#487.itm(0)} -pin  "ACC1:acc#487" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load net {ACC1:acc#487.itm(1)} -pin  "ACC1:acc#487" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load net {ACC1:acc#487.itm(2)} -pin  "ACC1:acc#487" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load inst "ACC1:acc#554" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64342 -attr oid 1532 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#488.itm(0)} -pin  "ACC1:acc#554" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load net {ACC1:acc#488.itm(1)} -pin  "ACC1:acc#554" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load net {ACC1:acc#488.itm(2)} -pin  "ACC1:acc#554" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#488.itm}
+load net {ACC1:acc#487.itm(0)} -pin  "ACC1:acc#554" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load net {ACC1:acc#487.itm(1)} -pin  "ACC1:acc#554" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load net {ACC1:acc#487.itm(2)} -pin  "ACC1:acc#554" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#487.itm}
+load net {ACC1:acc#554.itm(0)} -pin  "ACC1:acc#554" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#554.itm(1)} -pin  "ACC1:acc#554" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#554.itm(2)} -pin  "ACC1:acc#554" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#554.itm(3)} -pin  "ACC1:acc#554" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load inst "ACC1:acc#592" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64343 -attr oid 1533 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#554.itm(0)} -pin  "ACC1:acc#592" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#554.itm(1)} -pin  "ACC1:acc#592" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#554.itm(2)} -pin  "ACC1:acc#592" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#554.itm(3)} -pin  "ACC1:acc#592" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#554.itm}
+load net {ACC1:acc#553.ncse(0)} -pin  "ACC1:acc#592" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(1)} -pin  "ACC1:acc#592" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(2)} -pin  "ACC1:acc#592" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(3)} -pin  "ACC1:acc#592" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#592.itm(0)} -pin  "ACC1:acc#592" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(1)} -pin  "ACC1:acc#592" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(2)} -pin  "ACC1:acc#592" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(3)} -pin  "ACC1:acc#592" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(4)} -pin  "ACC1:acc#592" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load inst "ACC1:acc#611" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 64344 -attr oid 1534 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#593.itm(0)} -pin  "ACC1:acc#611" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(1)} -pin  "ACC1:acc#611" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(2)} -pin  "ACC1:acc#611" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(3)} -pin  "ACC1:acc#611" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#593.itm(4)} -pin  "ACC1:acc#611" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#593.itm}
+load net {ACC1:acc#592.itm(0)} -pin  "ACC1:acc#611" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(1)} -pin  "ACC1:acc#611" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(2)} -pin  "ACC1:acc#611" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(3)} -pin  "ACC1:acc#611" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#592.itm(4)} -pin  "ACC1:acc#611" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#592.itm}
+load net {ACC1:acc#611.itm(0)} -pin  "ACC1:acc#611" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(1)} -pin  "ACC1:acc#611" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(2)} -pin  "ACC1:acc#611" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(3)} -pin  "ACC1:acc#611" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(4)} -pin  "ACC1:acc#611" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(5)} -pin  "ACC1:acc#611" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load inst "ACC1:acc#482" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64345 -attr oid 1535 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#482" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1057.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#482" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1057.itm}
+load net {ACC1:acc#226.psp.sva(4)} -pin  "ACC1:acc#482" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#963.itm}
+load net {ACC1:acc#226.psp.sva(4)} -pin  "ACC1:acc#482" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#963.itm}
+load net {ACC1:acc#482.itm(0)} -pin  "ACC1:acc#482" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load net {ACC1:acc#482.itm(1)} -pin  "ACC1:acc#482" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load net {ACC1:acc#482.itm(2)} -pin  "ACC1:acc#482" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load inst "ACC1:acc#551" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64346 -attr oid 1536 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#482.itm(0)} -pin  "ACC1:acc#551" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load net {ACC1:acc#482.itm(1)} -pin  "ACC1:acc#551" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load net {ACC1:acc#482.itm(2)} -pin  "ACC1:acc#551" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#482.itm}
+load net {ACC1:acc#489.cse(0)} -pin  "ACC1:acc#551" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(1)} -pin  "ACC1:acc#551" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(2)} -pin  "ACC1:acc#551" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#551.itm(0)} -pin  "ACC1:acc#551" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#551.itm(1)} -pin  "ACC1:acc#551" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#551.itm(2)} -pin  "ACC1:acc#551" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#551.itm(3)} -pin  "ACC1:acc#551" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load inst "ACC1:acc#591" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64347 -attr oid 1537 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#553.ncse(0)} -pin  "ACC1:acc#591" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(1)} -pin  "ACC1:acc#591" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(2)} -pin  "ACC1:acc#591" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(3)} -pin  "ACC1:acc#591" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#551.itm(0)} -pin  "ACC1:acc#591" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#551.itm(1)} -pin  "ACC1:acc#591" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#551.itm(2)} -pin  "ACC1:acc#591" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#551.itm(3)} -pin  "ACC1:acc#591" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#551.itm}
+load net {ACC1:acc#591.itm(0)} -pin  "ACC1:acc#591" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(1)} -pin  "ACC1:acc#591" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(2)} -pin  "ACC1:acc#591" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(3)} -pin  "ACC1:acc#591" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(4)} -pin  "ACC1:acc#591" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load inst "ACC1:acc#479" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64348 -attr oid 1538 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#479} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#479" {A(0)} -attr @path {/sobel/sobel:core/exs#97.itm}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1:acc#479" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#97.itm}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1:acc#479" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#97.itm}
+load net {ACC1-1:and#3.cse.sva} -pin  "ACC1:acc#479" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1552.itm}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#479" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1552.itm}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1:acc#479" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1552.itm}
+load net {ACC1:acc#479.itm(0)} -pin  "ACC1:acc#479" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#479.itm}
+load net {ACC1:acc#479.itm(1)} -pin  "ACC1:acc#479" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#479.itm}
+load net {ACC1:acc#479.itm(2)} -pin  "ACC1:acc#479" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#479.itm}
+load net {ACC1:acc#479.itm(3)} -pin  "ACC1:acc#479" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#479.itm}
+load inst "ACC1:acc#550" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64349 -attr oid 1539 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#550" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#550" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#550" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#479.itm(1)} -pin  "ACC1:acc#550" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#147.itm}
+load net {ACC1:acc#479.itm(2)} -pin  "ACC1:acc#550" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#147.itm}
+load net {ACC1:acc#479.itm(3)} -pin  "ACC1:acc#550" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#147.itm}
+load net {ACC1:acc#550.itm(0)} -pin  "ACC1:acc#550" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#550.itm(1)} -pin  "ACC1:acc#550" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#550.itm(2)} -pin  "ACC1:acc#550" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#550.itm(3)} -pin  "ACC1:acc#550" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load inst "ACC1:acc#478" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64350 -attr oid 1540 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#478} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#478" {A(0)} -attr @path {/sobel/sobel:core/exs#98.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#478" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#98.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#478" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#98.itm}
+load net {ACC1-1:nand#1.cse.sva} -pin  "ACC1:acc#478" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1554.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#478" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1554.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#478" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1554.itm}
+load net {ACC1:acc#478.itm(0)} -pin  "ACC1:acc#478" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#478.itm}
+load net {ACC1:acc#478.itm(1)} -pin  "ACC1:acc#478" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#478.itm}
+load net {ACC1:acc#478.itm(2)} -pin  "ACC1:acc#478" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#478.itm}
+load net {ACC1:acc#478.itm(3)} -pin  "ACC1:acc#478" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#478.itm}
+load inst "ACC1:acc#477" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64351 -attr oid 1541 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#477} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#477" {A(0)} -attr @path {/sobel/sobel:core/exs#77.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#477" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#77.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#477" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#77.itm}
+load net {ACC1:acc#338.itm(2)} -pin  "ACC1:acc#477" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1556.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#477" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1556.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#477" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1556.itm}
+load net {ACC1:acc#477.itm(0)} -pin  "ACC1:acc#477" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#477.itm}
+load net {ACC1:acc#477.itm(1)} -pin  "ACC1:acc#477" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#477.itm}
+load net {ACC1:acc#477.itm(2)} -pin  "ACC1:acc#477" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#477.itm}
+load net {ACC1:acc#477.itm(3)} -pin  "ACC1:acc#477" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#477.itm}
+load inst "ACC1:acc#549" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64352 -attr oid 1542 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#478.itm(1)} -pin  "ACC1:acc#549" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#146.itm}
+load net {ACC1:acc#478.itm(2)} -pin  "ACC1:acc#549" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#146.itm}
+load net {ACC1:acc#478.itm(3)} -pin  "ACC1:acc#549" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#146.itm}
+load net {ACC1:acc#477.itm(1)} -pin  "ACC1:acc#549" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#145.itm}
+load net {ACC1:acc#477.itm(2)} -pin  "ACC1:acc#549" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#145.itm}
+load net {ACC1:acc#477.itm(3)} -pin  "ACC1:acc#549" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#145.itm}
+load net {ACC1:acc#549.itm(0)} -pin  "ACC1:acc#549" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#549.itm(1)} -pin  "ACC1:acc#549" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#549.itm(2)} -pin  "ACC1:acc#549" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#549.itm(3)} -pin  "ACC1:acc#549" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load inst "ACC1:acc#590" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64353 -attr oid 1543 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#550.itm(0)} -pin  "ACC1:acc#590" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#550.itm(1)} -pin  "ACC1:acc#590" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#550.itm(2)} -pin  "ACC1:acc#590" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#550.itm(3)} -pin  "ACC1:acc#590" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#550.itm}
+load net {ACC1:acc#549.itm(0)} -pin  "ACC1:acc#590" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#549.itm(1)} -pin  "ACC1:acc#590" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#549.itm(2)} -pin  "ACC1:acc#590" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#549.itm(3)} -pin  "ACC1:acc#590" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#549.itm}
+load net {ACC1:acc#590.itm(0)} -pin  "ACC1:acc#590" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(1)} -pin  "ACC1:acc#590" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(2)} -pin  "ACC1:acc#590" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(3)} -pin  "ACC1:acc#590" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(4)} -pin  "ACC1:acc#590" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load inst "ACC1:acc#610" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 64354 -attr oid 1544 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#591.itm(0)} -pin  "ACC1:acc#610" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(1)} -pin  "ACC1:acc#610" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(2)} -pin  "ACC1:acc#610" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(3)} -pin  "ACC1:acc#610" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#591.itm(4)} -pin  "ACC1:acc#610" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#591.itm}
+load net {ACC1:acc#590.itm(0)} -pin  "ACC1:acc#610" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(1)} -pin  "ACC1:acc#610" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(2)} -pin  "ACC1:acc#610" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(3)} -pin  "ACC1:acc#610" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#590.itm(4)} -pin  "ACC1:acc#610" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#590.itm}
+load net {ACC1:acc#610.itm(0)} -pin  "ACC1:acc#610" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(1)} -pin  "ACC1:acc#610" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(2)} -pin  "ACC1:acc#610" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(3)} -pin  "ACC1:acc#610" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(4)} -pin  "ACC1:acc#610" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(5)} -pin  "ACC1:acc#610" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load inst "ACC1:acc#625" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 64355 -attr oid 1545 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#611.itm(0)} -pin  "ACC1:acc#625" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(1)} -pin  "ACC1:acc#625" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(2)} -pin  "ACC1:acc#625" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(3)} -pin  "ACC1:acc#625" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(4)} -pin  "ACC1:acc#625" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#611.itm(5)} -pin  "ACC1:acc#625" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#611.itm}
+load net {ACC1:acc#610.itm(0)} -pin  "ACC1:acc#625" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(1)} -pin  "ACC1:acc#625" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(2)} -pin  "ACC1:acc#625" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(3)} -pin  "ACC1:acc#625" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(4)} -pin  "ACC1:acc#625" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#610.itm(5)} -pin  "ACC1:acc#625" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#610.itm}
+load net {ACC1:acc#625.itm(0)} -pin  "ACC1:acc#625" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(1)} -pin  "ACC1:acc#625" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(2)} -pin  "ACC1:acc#625" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(3)} -pin  "ACC1:acc#625" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(4)} -pin  "ACC1:acc#625" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(5)} -pin  "ACC1:acc#625" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(6)} -pin  "ACC1:acc#625" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load inst "ACC1:acc#476" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64356 -attr oid 1546 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#476} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#476" {A(0)} -attr @path {/sobel/sobel:core/exs#78.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#476" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#78.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#476" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#78.itm}
+load net {ACC1:acc#210.psp#2.sva(3)} -pin  "ACC1:acc#476" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1558.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#476" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1558.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#476" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1558.itm}
+load net {ACC1:acc#476.itm(0)} -pin  "ACC1:acc#476" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#476.itm}
+load net {ACC1:acc#476.itm(1)} -pin  "ACC1:acc#476" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#476.itm}
+load net {ACC1:acc#476.itm(2)} -pin  "ACC1:acc#476" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#476.itm}
+load net {ACC1:acc#476.itm(3)} -pin  "ACC1:acc#476" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#476.itm}
+load inst "ACC1:acc#475" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64357 -attr oid 1547 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#475} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#475" {A(0)} -attr @path {/sobel/sobel:core/exs#79.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#475" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#79.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#475" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#79.itm}
+load net {ACC1:acc#210.psp#2.sva(2)} -pin  "ACC1:acc#475" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1560.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#475" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1560.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#475" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1560.itm}
+load net {ACC1:acc#475.itm(0)} -pin  "ACC1:acc#475" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#475.itm}
+load net {ACC1:acc#475.itm(1)} -pin  "ACC1:acc#475" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#475.itm}
+load net {ACC1:acc#475.itm(2)} -pin  "ACC1:acc#475" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#475.itm}
+load net {ACC1:acc#475.itm(3)} -pin  "ACC1:acc#475" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#475.itm}
+load inst "ACC1:acc#548" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64358 -attr oid 1548 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#476.itm(1)} -pin  "ACC1:acc#548" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#144.itm}
+load net {ACC1:acc#476.itm(2)} -pin  "ACC1:acc#548" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#144.itm}
+load net {ACC1:acc#476.itm(3)} -pin  "ACC1:acc#548" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#144.itm}
+load net {ACC1:acc#475.itm(1)} -pin  "ACC1:acc#548" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#143.itm}
+load net {ACC1:acc#475.itm(2)} -pin  "ACC1:acc#548" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#143.itm}
+load net {ACC1:acc#475.itm(3)} -pin  "ACC1:acc#548" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#143.itm}
+load net {ACC1:acc#548.itm(0)} -pin  "ACC1:acc#548" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#548.itm(1)} -pin  "ACC1:acc#548" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#548.itm(2)} -pin  "ACC1:acc#548" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#548.itm(3)} -pin  "ACC1:acc#548" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load inst "ACC1:acc#474" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64359 -attr oid 1549 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#474} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#474" {A(0)} -attr @path {/sobel/sobel:core/exs#80.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#474" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#80.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#474" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#80.itm}
+load net {ACC1:acc#210.psp#2.sva(1)} -pin  "ACC1:acc#474" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1562.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#474" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1562.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#474" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1562.itm}
+load net {ACC1:acc#474.itm(0)} -pin  "ACC1:acc#474" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#474.itm}
+load net {ACC1:acc#474.itm(1)} -pin  "ACC1:acc#474" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#474.itm}
+load net {ACC1:acc#474.itm(2)} -pin  "ACC1:acc#474" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#474.itm}
+load net {ACC1:acc#474.itm(3)} -pin  "ACC1:acc#474" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#474.itm}
+load inst "ACC1:acc#473" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64360 -attr oid 1550 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#473} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#473" {A(0)} -attr @path {/sobel/sobel:core/exs#99.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#473" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#99.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#473" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#99.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#473" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1564.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#473" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1564.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#473" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1564.itm}
+load net {ACC1:acc#473.itm(0)} -pin  "ACC1:acc#473" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#473.itm}
+load net {ACC1:acc#473.itm(1)} -pin  "ACC1:acc#473" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#473.itm}
+load net {ACC1:acc#473.itm(2)} -pin  "ACC1:acc#473" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#473.itm}
+load net {ACC1:acc#473.itm(3)} -pin  "ACC1:acc#473" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#473.itm}
+load inst "ACC1:acc#547" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64361 -attr oid 1551 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#474.itm(1)} -pin  "ACC1:acc#547" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#142.itm}
+load net {ACC1:acc#474.itm(2)} -pin  "ACC1:acc#547" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#142.itm}
+load net {ACC1:acc#474.itm(3)} -pin  "ACC1:acc#547" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#142.itm}
+load net {ACC1:acc#473.itm(1)} -pin  "ACC1:acc#547" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#141.itm}
+load net {ACC1:acc#473.itm(2)} -pin  "ACC1:acc#547" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#141.itm}
+load net {ACC1:acc#473.itm(3)} -pin  "ACC1:acc#547" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#141.itm}
+load net {ACC1:acc#547.itm(0)} -pin  "ACC1:acc#547" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#547.itm(1)} -pin  "ACC1:acc#547" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#547.itm(2)} -pin  "ACC1:acc#547" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#547.itm(3)} -pin  "ACC1:acc#547" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load inst "ACC1:acc#589" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64362 -attr oid 1552 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#548.itm(0)} -pin  "ACC1:acc#589" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#548.itm(1)} -pin  "ACC1:acc#589" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#548.itm(2)} -pin  "ACC1:acc#589" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#548.itm(3)} -pin  "ACC1:acc#589" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#548.itm}
+load net {ACC1:acc#547.itm(0)} -pin  "ACC1:acc#589" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#547.itm(1)} -pin  "ACC1:acc#589" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#547.itm(2)} -pin  "ACC1:acc#589" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#547.itm(3)} -pin  "ACC1:acc#589" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#547.itm}
+load net {ACC1:acc#589.itm(0)} -pin  "ACC1:acc#589" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(1)} -pin  "ACC1:acc#589" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(2)} -pin  "ACC1:acc#589" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(3)} -pin  "ACC1:acc#589" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(4)} -pin  "ACC1:acc#589" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load inst "ACC1:acc#472" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64363 -attr oid 1553 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#472} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#472" {A(0)} -attr @path {/sobel/sobel:core/exs#81.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#472" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#81.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#472" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#81.itm}
+load net {acc.psp#2.sva(3)} -pin  "ACC1:acc#472" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1566.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#472" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1566.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#472" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1566.itm}
+load net {ACC1:acc#472.itm(0)} -pin  "ACC1:acc#472" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#472.itm}
+load net {ACC1:acc#472.itm(1)} -pin  "ACC1:acc#472" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#472.itm}
+load net {ACC1:acc#472.itm(2)} -pin  "ACC1:acc#472" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#472.itm}
+load net {ACC1:acc#472.itm(3)} -pin  "ACC1:acc#472" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#472.itm}
+load inst "ACC1:acc#470" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64364 -attr oid 1554 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#470} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#470" {A(0)} -attr @path {/sobel/sobel:core/exs#82.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#470" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#82.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#470" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#82.itm}
+load net {acc.psp#2.sva(1)} -pin  "ACC1:acc#470" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1568.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#470" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1568.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#470" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1568.itm}
+load net {ACC1:acc#470.itm(0)} -pin  "ACC1:acc#470" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#470.itm}
+load net {ACC1:acc#470.itm(1)} -pin  "ACC1:acc#470" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#470.itm}
+load net {ACC1:acc#470.itm(2)} -pin  "ACC1:acc#470" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#470.itm}
+load net {ACC1:acc#470.itm(3)} -pin  "ACC1:acc#470" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#470.itm}
+load inst "ACC1:acc#546" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64365 -attr oid 1555 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#472.itm(1)} -pin  "ACC1:acc#546" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#140.itm}
+load net {ACC1:acc#472.itm(2)} -pin  "ACC1:acc#546" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#140.itm}
+load net {ACC1:acc#472.itm(3)} -pin  "ACC1:acc#546" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#140.itm}
+load net {ACC1:acc#470.itm(1)} -pin  "ACC1:acc#546" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#138.itm}
+load net {ACC1:acc#470.itm(2)} -pin  "ACC1:acc#546" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#138.itm}
+load net {ACC1:acc#470.itm(3)} -pin  "ACC1:acc#546" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#138.itm}
+load net {ACC1:acc#546.itm(0)} -pin  "ACC1:acc#546" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#546.itm(1)} -pin  "ACC1:acc#546" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#546.itm(2)} -pin  "ACC1:acc#546" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#546.itm(3)} -pin  "ACC1:acc#546" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load inst "ACC1-3:not#60" "not(1)" "INTERFACE" -attr xrf 64366 -attr oid 1556 -attr @path {/sobel/sobel:core/ACC1-3:not#60} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#406.itm(2)} -pin  "ACC1-3:not#60" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#2.itm}
+load net {ACC1-3:not#60.itm} -pin  "ACC1-3:not#60" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#60.itm}
+load inst "ACC1-3:and#3" "and(3,1)" "INTERFACE" -attr xrf 64367 -attr oid 1557 -attr @path {/sobel/sobel:core/ACC1-3:and#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1-3:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#23.itm}
+load net {ACC1-3:not#60.itm} -pin  "ACC1-3:and#3" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#60.itm}
+load net {ACC1:acc#406.itm(1)} -pin  "ACC1-3:and#3" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#1.itm}
+load net {ACC1-3:and#3.itm} -pin  "ACC1-3:and#3" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#3.itm}
+load inst "ACC1:acc#469" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64368 -attr oid 1558 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#469} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#469" {A(0)} -attr @path {/sobel/sobel:core/exs#83.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#469" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#83.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#469" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#83.itm}
+load net {ACC1-3:and#3.itm} -pin  "ACC1:acc#469" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1570.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#469" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1570.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#469" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1570.itm}
+load net {ACC1:acc#469.itm(0)} -pin  "ACC1:acc#469" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#469.itm}
+load net {ACC1:acc#469.itm(1)} -pin  "ACC1:acc#469" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#469.itm}
+load net {ACC1:acc#469.itm(2)} -pin  "ACC1:acc#469" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#469.itm}
+load net {ACC1:acc#469.itm(3)} -pin  "ACC1:acc#469" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#469.itm}
+load inst "ACC1-3:not#314" "not(1)" "INTERFACE" -attr xrf 64369 -attr oid 1559 -attr @path {/sobel/sobel:core/ACC1-3:not#314} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1-3:not#314" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#36.itm}
+load net {ACC1-3:not#314.itm} -pin  "ACC1-3:not#314" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#314.itm}
+load inst "ACC1-3:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 64370 -attr oid 1560 -attr @path {/sobel/sobel:core/ACC1-3:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#406.itm(2)} -pin  "ACC1-3:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva).itm}
+load net {ACC1-3:not#314.itm} -pin  "ACC1-3:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#314.itm}
+load net {ACC1-3:nand#1.itm} -pin  "ACC1-3:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand#1.itm}
+load inst "ACC1:acc#468" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64371 -attr oid 1561 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#468} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#468" {A(0)} -attr @path {/sobel/sobel:core/exs#100.itm}
+load net {ACC1:acc#224.psp#1.sva(6)} -pin  "ACC1:acc#468" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#100.itm}
+load net {ACC1:acc#224.psp#1.sva(6)} -pin  "ACC1:acc#468" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#100.itm}
+load net {ACC1-3:nand#1.itm} -pin  "ACC1:acc#468" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1572.itm}
+load net {ACC1:acc#224.psp#1.sva(8)} -pin  "ACC1:acc#468" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1572.itm}
+load net {ACC1:acc#224.psp#1.sva(8)} -pin  "ACC1:acc#468" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1572.itm}
+load net {ACC1:acc#468.itm(0)} -pin  "ACC1:acc#468" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#468.itm}
+load net {ACC1:acc#468.itm(1)} -pin  "ACC1:acc#468" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#468.itm}
+load net {ACC1:acc#468.itm(2)} -pin  "ACC1:acc#468" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#468.itm}
+load net {ACC1:acc#468.itm(3)} -pin  "ACC1:acc#468" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#468.itm}
+load inst "ACC1:acc#545" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64372 -attr oid 1562 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#469.itm(1)} -pin  "ACC1:acc#545" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#137.itm}
+load net {ACC1:acc#469.itm(2)} -pin  "ACC1:acc#545" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#137.itm}
+load net {ACC1:acc#469.itm(3)} -pin  "ACC1:acc#545" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#137.itm}
+load net {ACC1:acc#468.itm(1)} -pin  "ACC1:acc#545" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#136.itm}
+load net {ACC1:acc#468.itm(2)} -pin  "ACC1:acc#545" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#136.itm}
+load net {ACC1:acc#468.itm(3)} -pin  "ACC1:acc#545" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#136.itm}
+load net {ACC1:acc#545.itm(0)} -pin  "ACC1:acc#545" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#545.itm(1)} -pin  "ACC1:acc#545" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#545.itm(2)} -pin  "ACC1:acc#545" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#545.itm(3)} -pin  "ACC1:acc#545" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load inst "ACC1:acc#588" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64373 -attr oid 1563 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#546.itm(0)} -pin  "ACC1:acc#588" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#546.itm(1)} -pin  "ACC1:acc#588" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#546.itm(2)} -pin  "ACC1:acc#588" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#546.itm(3)} -pin  "ACC1:acc#588" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#546.itm}
+load net {ACC1:acc#545.itm(0)} -pin  "ACC1:acc#588" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#545.itm(1)} -pin  "ACC1:acc#588" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#545.itm(2)} -pin  "ACC1:acc#588" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#545.itm(3)} -pin  "ACC1:acc#588" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#545.itm}
+load net {ACC1:acc#588.itm(0)} -pin  "ACC1:acc#588" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(1)} -pin  "ACC1:acc#588" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(2)} -pin  "ACC1:acc#588" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(3)} -pin  "ACC1:acc#588" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(4)} -pin  "ACC1:acc#588" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load inst "ACC1:acc#609" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 64374 -attr oid 1564 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#589.itm(0)} -pin  "ACC1:acc#609" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(1)} -pin  "ACC1:acc#609" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(2)} -pin  "ACC1:acc#609" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(3)} -pin  "ACC1:acc#609" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#589.itm(4)} -pin  "ACC1:acc#609" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#589.itm}
+load net {ACC1:acc#588.itm(0)} -pin  "ACC1:acc#609" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(1)} -pin  "ACC1:acc#609" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(2)} -pin  "ACC1:acc#609" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(3)} -pin  "ACC1:acc#609" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#588.itm(4)} -pin  "ACC1:acc#609" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#588.itm}
+load net {ACC1:acc#609.itm(0)} -pin  "ACC1:acc#609" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(1)} -pin  "ACC1:acc#609" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(2)} -pin  "ACC1:acc#609" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(3)} -pin  "ACC1:acc#609" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(4)} -pin  "ACC1:acc#609" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(5)} -pin  "ACC1:acc#609" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load inst "ACC1-1:not#188" "not(1)" "INTERFACE" -attr xrf 64375 -attr oid 1565 -attr @path {/sobel/sobel:core/ACC1-1:not#188} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#368.itm(2)} -pin  "ACC1-1:not#188" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#44.sva)#2.itm}
+load net {ACC1-1:not#188.itm} -pin  "ACC1-1:not#188" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#188.itm}
+load inst "ACC1-1:and#11" "and(3,1)" "INTERFACE" -attr xrf 64376 -attr oid 1566 -attr @path {/sobel/sobel:core/ACC1-1:and#11} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1-1:and#11" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#22.itm}
+load net {ACC1-1:not#188.itm} -pin  "ACC1-1:and#11" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#188.itm}
+load net {ACC1:acc#368.itm(1)} -pin  "ACC1-1:and#11" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#44.sva)#1.itm}
+load net {ACC1-1:and#11.itm} -pin  "ACC1-1:and#11" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#11.itm}
+load inst "ACC1:acc#467" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64377 -attr oid 1567 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#467} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#467" {A(0)} -attr @path {/sobel/sobel:core/exs#101.itm}
+load net {ACC1:acc#224.psp#1.sva(10)} -pin  "ACC1:acc#467" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#101.itm}
+load net {ACC1:acc#224.psp#1.sva(10)} -pin  "ACC1:acc#467" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#101.itm}
+load net {ACC1-1:and#11.itm} -pin  "ACC1:acc#467" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1574.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#467" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1574.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#467" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1574.itm}
+load net {ACC1:acc#467.itm(0)} -pin  "ACC1:acc#467" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#467.itm}
+load net {ACC1:acc#467.itm(1)} -pin  "ACC1:acc#467" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#467.itm}
+load net {ACC1:acc#467.itm(2)} -pin  "ACC1:acc#467" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#467.itm}
+load net {ACC1:acc#467.itm(3)} -pin  "ACC1:acc#467" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#467.itm}
+load inst "ACC1-1:not#317" "not(1)" "INTERFACE" -attr xrf 64378 -attr oid 1568 -attr @path {/sobel/sobel:core/ACC1-1:not#317} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1-1:not#317" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#41.itm}
+load net {ACC1-1:not#317.itm} -pin  "ACC1-1:not#317" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#317.itm}
+load inst "ACC1-1:nand#5" "nand(2,1)" "INTERFACE" -attr xrf 64379 -attr oid 1569 -attr @path {/sobel/sobel:core/ACC1-1:nand#5} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#368.itm(2)} -pin  "ACC1-1:nand#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#44.sva).itm}
+load net {ACC1-1:not#317.itm} -pin  "ACC1-1:nand#5" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#317.itm}
+load net {ACC1-1:nand#5.itm} -pin  "ACC1-1:nand#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:nand#5.itm}
+load inst "ACC1:acc#466" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64380 -attr oid 1570 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#466} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#466" {A(0)} -attr @path {/sobel/sobel:core/exs#84.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#466" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#84.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#466" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#84.itm}
+load net {ACC1-1:nand#5.itm} -pin  "ACC1:acc#466" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1576.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#466" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1576.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#466" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1576.itm}
+load net {ACC1:acc#466.itm(0)} -pin  "ACC1:acc#466" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#466.itm}
+load net {ACC1:acc#466.itm(1)} -pin  "ACC1:acc#466" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#466.itm}
+load net {ACC1:acc#466.itm(2)} -pin  "ACC1:acc#466" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#466.itm}
+load net {ACC1:acc#466.itm(3)} -pin  "ACC1:acc#466" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#466.itm}
+load inst "ACC1:acc#544" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64381 -attr oid 1571 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#467.itm(1)} -pin  "ACC1:acc#544" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#135.itm}
+load net {ACC1:acc#467.itm(2)} -pin  "ACC1:acc#544" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#135.itm}
+load net {ACC1:acc#467.itm(3)} -pin  "ACC1:acc#544" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#135.itm}
+load net {ACC1:acc#466.itm(1)} -pin  "ACC1:acc#544" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#134.itm}
+load net {ACC1:acc#466.itm(2)} -pin  "ACC1:acc#544" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#134.itm}
+load net {ACC1:acc#466.itm(3)} -pin  "ACC1:acc#544" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#134.itm}
+load net {ACC1:acc#544.itm(0)} -pin  "ACC1:acc#544" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#544.itm(1)} -pin  "ACC1:acc#544" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#544.itm(2)} -pin  "ACC1:acc#544" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#544.itm(3)} -pin  "ACC1:acc#544" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load inst "ACC1:acc#465" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64382 -attr oid 1572 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#465} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#465" {A(0)} -attr @path {/sobel/sobel:core/exs#85.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#465" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#85.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#465" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#85.itm}
+load net {ACC1:acc#367.itm(2)} -pin  "ACC1:acc#465" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1578.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#465" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1578.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#465" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1578.itm}
+load net {ACC1:acc#465.itm(0)} -pin  "ACC1:acc#465" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#465.itm}
+load net {ACC1:acc#465.itm(1)} -pin  "ACC1:acc#465" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#465.itm}
+load net {ACC1:acc#465.itm(2)} -pin  "ACC1:acc#465" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#465.itm}
+load net {ACC1:acc#465.itm(3)} -pin  "ACC1:acc#465" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#465.itm}
+load inst "ACC1:acc#464" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64383 -attr oid 1573 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#464} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#464" {A(0)} -attr @path {/sobel/sobel:core/exs#86.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#464" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#86.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#464" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#86.itm}
+load net {ACC1-1:acc#208.psp.sva(3)} -pin  "ACC1:acc#464" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1580.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#464" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1580.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#464" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1580.itm}
+load net {ACC1:acc#464.itm(0)} -pin  "ACC1:acc#464" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#464.itm}
+load net {ACC1:acc#464.itm(1)} -pin  "ACC1:acc#464" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#464.itm}
+load net {ACC1:acc#464.itm(2)} -pin  "ACC1:acc#464" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#464.itm}
+load net {ACC1:acc#464.itm(3)} -pin  "ACC1:acc#464" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#464.itm}
+load inst "ACC1:acc#543" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64384 -attr oid 1574 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#465.itm(1)} -pin  "ACC1:acc#543" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#133.itm}
+load net {ACC1:acc#465.itm(2)} -pin  "ACC1:acc#543" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#133.itm}
+load net {ACC1:acc#465.itm(3)} -pin  "ACC1:acc#543" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#133.itm}
+load net {ACC1:acc#464.itm(1)} -pin  "ACC1:acc#543" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#132.itm}
+load net {ACC1:acc#464.itm(2)} -pin  "ACC1:acc#543" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#132.itm}
+load net {ACC1:acc#464.itm(3)} -pin  "ACC1:acc#543" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#132.itm}
+load net {ACC1:acc#543.itm(0)} -pin  "ACC1:acc#543" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#543.itm(1)} -pin  "ACC1:acc#543" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#543.itm(2)} -pin  "ACC1:acc#543" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#543.itm(3)} -pin  "ACC1:acc#543" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load inst "ACC1:acc#587" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64385 -attr oid 1575 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#544.itm(0)} -pin  "ACC1:acc#587" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#544.itm(1)} -pin  "ACC1:acc#587" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#544.itm(2)} -pin  "ACC1:acc#587" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#544.itm(3)} -pin  "ACC1:acc#587" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#544.itm}
+load net {ACC1:acc#543.itm(0)} -pin  "ACC1:acc#587" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#543.itm(1)} -pin  "ACC1:acc#587" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#543.itm(2)} -pin  "ACC1:acc#587" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#543.itm(3)} -pin  "ACC1:acc#587" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#543.itm}
+load net {ACC1:acc#587.itm(0)} -pin  "ACC1:acc#587" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(1)} -pin  "ACC1:acc#587" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(2)} -pin  "ACC1:acc#587" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(3)} -pin  "ACC1:acc#587" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(4)} -pin  "ACC1:acc#587" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load inst "ACC1:acc#463" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64386 -attr oid 1576 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#463} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#463" {A(0)} -attr @path {/sobel/sobel:core/exs#87.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#463" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#87.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#463" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#87.itm}
+load net {ACC1-1:acc#208.psp.sva(2)} -pin  "ACC1:acc#463" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1582.itm}
+load net {ACC1:acc#224.psp#1.sva(4)} -pin  "ACC1:acc#463" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1582.itm}
+load net {ACC1:acc#224.psp#1.sva(4)} -pin  "ACC1:acc#463" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1582.itm}
+load net {ACC1:acc#463.itm(0)} -pin  "ACC1:acc#463" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#463.itm}
+load net {ACC1:acc#463.itm(1)} -pin  "ACC1:acc#463" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#463.itm}
+load net {ACC1:acc#463.itm(2)} -pin  "ACC1:acc#463" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#463.itm}
+load net {ACC1:acc#463.itm(3)} -pin  "ACC1:acc#463" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#463.itm}
+load inst "ACC1:acc#462" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64387 -attr oid 1577 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#462} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#462" {A(0)} -attr @path {/sobel/sobel:core/exs#88.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#462" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#88.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#462" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#88.itm}
+load net {ACC1-1:acc#208.psp.sva(1)} -pin  "ACC1:acc#462" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1584.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#462" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1584.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#462" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1584.itm}
+load net {ACC1:acc#462.itm(0)} -pin  "ACC1:acc#462" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#462.itm}
+load net {ACC1:acc#462.itm(1)} -pin  "ACC1:acc#462" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#462.itm}
+load net {ACC1:acc#462.itm(2)} -pin  "ACC1:acc#462" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#462.itm}
+load net {ACC1:acc#462.itm(3)} -pin  "ACC1:acc#462" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#462.itm}
+load inst "ACC1:acc#542" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64388 -attr oid 1578 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#463.itm(1)} -pin  "ACC1:acc#542" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#131.itm}
+load net {ACC1:acc#463.itm(2)} -pin  "ACC1:acc#542" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#131.itm}
+load net {ACC1:acc#463.itm(3)} -pin  "ACC1:acc#542" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#131.itm}
+load net {ACC1:acc#462.itm(1)} -pin  "ACC1:acc#542" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#130.itm}
+load net {ACC1:acc#462.itm(2)} -pin  "ACC1:acc#542" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#130.itm}
+load net {ACC1:acc#462.itm(3)} -pin  "ACC1:acc#542" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#130.itm}
+load net {ACC1:acc#542.itm(0)} -pin  "ACC1:acc#542" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#542.itm(1)} -pin  "ACC1:acc#542" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#542.itm(2)} -pin  "ACC1:acc#542" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#542.itm(3)} -pin  "ACC1:acc#542" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load inst "ACC1-1:not#91" "not(1)" "INTERFACE" -attr xrf 64389 -attr oid 1579 -attr @path {/sobel/sobel:core/ACC1-1:not#91} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1-1:not#91" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#26.itm}
+load net {ACC1-1:not#91.itm} -pin  "ACC1-1:not#91" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#91.itm}
+load inst "ACC1-1:nand#2" "nand(2,1)" "INTERFACE" -attr xrf 64390 -attr oid 1580 -attr @path {/sobel/sobel:core/ACC1-1:nand#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#349.itm(2)} -pin  "ACC1-1:nand#2" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#36.sva)#2.itm}
+load net {ACC1-1:not#91.itm} -pin  "ACC1-1:nand#2" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#91.itm}
+load net {ACC1-1:nand#2.itm} -pin  "ACC1-1:nand#2" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:nand#2.itm}
+load inst "ACC1:acc#460" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64391 -attr oid 1581 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#460} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#460" {A(0)} -attr @path {/sobel/sobel:core/exs#89.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#460" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#89.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#460" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#89.itm}
+load net {ACC1-1:nand#2.itm} -pin  "ACC1:acc#460" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1586.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#460" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1586.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#460" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1586.itm}
+load net {ACC1:acc#460.itm(0)} -pin  "ACC1:acc#460" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#460.itm}
+load net {ACC1:acc#460.itm(1)} -pin  "ACC1:acc#460" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#460.itm}
+load net {ACC1:acc#460.itm(2)} -pin  "ACC1:acc#460" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#460.itm}
+load net {ACC1:acc#460.itm(3)} -pin  "ACC1:acc#460" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#460.itm}
+load inst "ACC1:acc#459" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64392 -attr oid 1582 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#459} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#459" {A(0)} -attr @path {/sobel/sobel:core/exs#102.itm}
+load net {ACC1-1:acc#25.psp.sva(7)} -pin  "ACC1:acc#459" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#102.itm}
+load net {ACC1-1:acc#25.psp.sva(7)} -pin  "ACC1:acc#459" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#102.itm}
+load net {ACC1:acc#348.itm(2)} -pin  "ACC1:acc#459" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1588.itm}
+load net {ACC1-1:acc#25.psp.sva(9)} -pin  "ACC1:acc#459" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1588.itm}
+load net {ACC1-1:acc#25.psp.sva(9)} -pin  "ACC1:acc#459" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1588.itm}
+load net {ACC1:acc#459.itm(0)} -pin  "ACC1:acc#459" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#459.itm}
+load net {ACC1:acc#459.itm(1)} -pin  "ACC1:acc#459" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#459.itm}
+load net {ACC1:acc#459.itm(2)} -pin  "ACC1:acc#459" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#459.itm}
+load net {ACC1:acc#459.itm(3)} -pin  "ACC1:acc#459" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#459.itm}
+load inst "ACC1:acc#541" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64393 -attr oid 1583 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#460.itm(1)} -pin  "ACC1:acc#541" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#128.itm}
+load net {ACC1:acc#460.itm(2)} -pin  "ACC1:acc#541" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#128.itm}
+load net {ACC1:acc#460.itm(3)} -pin  "ACC1:acc#541" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#128.itm}
+load net {ACC1:acc#459.itm(1)} -pin  "ACC1:acc#541" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#127.itm}
+load net {ACC1:acc#459.itm(2)} -pin  "ACC1:acc#541" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#127.itm}
+load net {ACC1:acc#459.itm(3)} -pin  "ACC1:acc#541" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#127.itm}
+load net {ACC1:acc#541.itm(0)} -pin  "ACC1:acc#541" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#541.itm(1)} -pin  "ACC1:acc#541" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#541.itm(2)} -pin  "ACC1:acc#541" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#541.itm(3)} -pin  "ACC1:acc#541" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load inst "ACC1:acc#586" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64394 -attr oid 1584 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#542.itm(0)} -pin  "ACC1:acc#586" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#542.itm(1)} -pin  "ACC1:acc#586" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#542.itm(2)} -pin  "ACC1:acc#586" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#542.itm(3)} -pin  "ACC1:acc#586" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#542.itm}
+load net {ACC1:acc#541.itm(0)} -pin  "ACC1:acc#586" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#541.itm(1)} -pin  "ACC1:acc#586" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#541.itm(2)} -pin  "ACC1:acc#586" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#541.itm(3)} -pin  "ACC1:acc#586" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#541.itm}
+load net {ACC1:acc#586.itm(0)} -pin  "ACC1:acc#586" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(1)} -pin  "ACC1:acc#586" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(2)} -pin  "ACC1:acc#586" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(3)} -pin  "ACC1:acc#586" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(4)} -pin  "ACC1:acc#586" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load inst "ACC1:acc#608" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 64395 -attr oid 1585 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#587.itm(0)} -pin  "ACC1:acc#608" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(1)} -pin  "ACC1:acc#608" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(2)} -pin  "ACC1:acc#608" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(3)} -pin  "ACC1:acc#608" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#587.itm(4)} -pin  "ACC1:acc#608" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#587.itm}
+load net {ACC1:acc#586.itm(0)} -pin  "ACC1:acc#608" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(1)} -pin  "ACC1:acc#608" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(2)} -pin  "ACC1:acc#608" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(3)} -pin  "ACC1:acc#608" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#586.itm(4)} -pin  "ACC1:acc#608" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#586.itm}
+load net {ACC1:acc#608.itm(0)} -pin  "ACC1:acc#608" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(1)} -pin  "ACC1:acc#608" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(2)} -pin  "ACC1:acc#608" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(3)} -pin  "ACC1:acc#608" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(4)} -pin  "ACC1:acc#608" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(5)} -pin  "ACC1:acc#608" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load inst "ACC1:acc#624" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 64396 -attr oid 1586 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#609.itm(0)} -pin  "ACC1:acc#624" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(1)} -pin  "ACC1:acc#624" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(2)} -pin  "ACC1:acc#624" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(3)} -pin  "ACC1:acc#624" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(4)} -pin  "ACC1:acc#624" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#609.itm(5)} -pin  "ACC1:acc#624" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#609.itm}
+load net {ACC1:acc#608.itm(0)} -pin  "ACC1:acc#624" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(1)} -pin  "ACC1:acc#624" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(2)} -pin  "ACC1:acc#624" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(3)} -pin  "ACC1:acc#624" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(4)} -pin  "ACC1:acc#624" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#608.itm(5)} -pin  "ACC1:acc#624" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#608.itm}
+load net {ACC1:acc#624.itm(0)} -pin  "ACC1:acc#624" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(1)} -pin  "ACC1:acc#624" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(2)} -pin  "ACC1:acc#624" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(3)} -pin  "ACC1:acc#624" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(4)} -pin  "ACC1:acc#624" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(5)} -pin  "ACC1:acc#624" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(6)} -pin  "ACC1:acc#624" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load inst "ACC1:acc#637" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 64397 -attr oid 1587 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#625.itm(0)} -pin  "ACC1:acc#637" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(1)} -pin  "ACC1:acc#637" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(2)} -pin  "ACC1:acc#637" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(3)} -pin  "ACC1:acc#637" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(4)} -pin  "ACC1:acc#637" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(5)} -pin  "ACC1:acc#637" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#625.itm(6)} -pin  "ACC1:acc#637" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#625.itm}
+load net {ACC1:acc#624.itm(0)} -pin  "ACC1:acc#637" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(1)} -pin  "ACC1:acc#637" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(2)} -pin  "ACC1:acc#637" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(3)} -pin  "ACC1:acc#637" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(4)} -pin  "ACC1:acc#637" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(5)} -pin  "ACC1:acc#637" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#624.itm(6)} -pin  "ACC1:acc#637" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#624.itm}
+load net {ACC1:acc#637.itm(0)} -pin  "ACC1:acc#637" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(1)} -pin  "ACC1:acc#637" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(2)} -pin  "ACC1:acc#637" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(3)} -pin  "ACC1:acc#637" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(4)} -pin  "ACC1:acc#637" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(5)} -pin  "ACC1:acc#637" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(6)} -pin  "ACC1:acc#637" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(7)} -pin  "ACC1:acc#637" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load inst "ACC1:acc#645" "add(8,1,8,0,9)" "INTERFACE" -attr xrf 64398 -attr oid 1588 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#638.itm(0)} -pin  "ACC1:acc#645" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(1)} -pin  "ACC1:acc#645" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(2)} -pin  "ACC1:acc#645" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(3)} -pin  "ACC1:acc#645" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(4)} -pin  "ACC1:acc#645" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(5)} -pin  "ACC1:acc#645" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(6)} -pin  "ACC1:acc#645" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#638.itm(7)} -pin  "ACC1:acc#645" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#638.itm}
+load net {ACC1:acc#637.itm(0)} -pin  "ACC1:acc#645" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(1)} -pin  "ACC1:acc#645" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(2)} -pin  "ACC1:acc#645" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(3)} -pin  "ACC1:acc#645" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(4)} -pin  "ACC1:acc#645" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(5)} -pin  "ACC1:acc#645" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(6)} -pin  "ACC1:acc#645" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#637.itm(7)} -pin  "ACC1:acc#645" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#637.itm}
+load net {ACC1:acc#645.itm(0)} -pin  "ACC1:acc#645" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(1)} -pin  "ACC1:acc#645" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(2)} -pin  "ACC1:acc#645" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(3)} -pin  "ACC1:acc#645" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(4)} -pin  "ACC1:acc#645" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(5)} -pin  "ACC1:acc#645" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(6)} -pin  "ACC1:acc#645" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(7)} -pin  "ACC1:acc#645" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(8)} -pin  "ACC1:acc#645" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load inst "ACC1:acc#650" "add(10,0,9,1,11)" "INTERFACE" -attr xrf 64399 -attr oid 1589 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,12)"
+load net {ACC1:acc#228.psp.sva(3)} -pin  "ACC1:acc#650" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1:acc#650" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {GND} -pin  "ACC1:acc#650" {A(2)} -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1:acc#650" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {GND} -pin  "ACC1:acc#650" {A(4)} -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1:acc#650" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {GND} -pin  "ACC1:acc#650" {A(6)} -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1:acc#650" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {GND} -pin  "ACC1:acc#650" {A(8)} -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1:acc#650" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#955.itm}
+load net {ACC1:acc#645.itm(0)} -pin  "ACC1:acc#650" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(1)} -pin  "ACC1:acc#650" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(2)} -pin  "ACC1:acc#650" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(3)} -pin  "ACC1:acc#650" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(4)} -pin  "ACC1:acc#650" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(5)} -pin  "ACC1:acc#650" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(6)} -pin  "ACC1:acc#650" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(7)} -pin  "ACC1:acc#650" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#645.itm(8)} -pin  "ACC1:acc#650" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#645.itm}
+load net {ACC1:acc#650.itm(0)} -pin  "ACC1:acc#650" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(1)} -pin  "ACC1:acc#650" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(2)} -pin  "ACC1:acc#650" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(3)} -pin  "ACC1:acc#650" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(4)} -pin  "ACC1:acc#650" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(5)} -pin  "ACC1:acc#650" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(6)} -pin  "ACC1:acc#650" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(7)} -pin  "ACC1:acc#650" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(8)} -pin  "ACC1:acc#650" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(9)} -pin  "ACC1:acc#650" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(10)} -pin  "ACC1:acc#650" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load inst "ACC1:acc#517" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64400 -attr oid 1590 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#228.psp.sva(10)} -pin  "ACC1:acc#517" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#20.itm}
+load net {ACC1:acc#228.psp.sva(10)} -pin  "ACC1:acc#517" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#20.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#517" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1049.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#517" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1049.itm}
+load net {ACC1:acc#517.itm(0)} -pin  "ACC1:acc#517" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load net {ACC1:acc#517.itm(1)} -pin  "ACC1:acc#517" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load net {ACC1:acc#517.itm(2)} -pin  "ACC1:acc#517" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load inst "ACC1:acc#568" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64401 -attr oid 1591 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#517.itm(0)} -pin  "ACC1:acc#568" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load net {ACC1:acc#517.itm(1)} -pin  "ACC1:acc#568" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load net {ACC1:acc#517.itm(2)} -pin  "ACC1:acc#568" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#517.itm}
+load net {ACC1:acc#516.cse(0)} -pin  "ACC1:acc#568" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(1)} -pin  "ACC1:acc#568" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(2)} -pin  "ACC1:acc#568" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#568.itm(0)} -pin  "ACC1:acc#568" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#568.itm(1)} -pin  "ACC1:acc#568" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#568.itm(2)} -pin  "ACC1:acc#568" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#568.itm(3)} -pin  "ACC1:acc#568" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load inst "ACC1:acc#567" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64402 -attr oid 1592 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#516.cse(0)} -pin  "ACC1:acc#567" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(1)} -pin  "ACC1:acc#567" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(2)} -pin  "ACC1:acc#567" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(0)} -pin  "ACC1:acc#567" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(1)} -pin  "ACC1:acc#567" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(2)} -pin  "ACC1:acc#567" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#567.itm(0)} -pin  "ACC1:acc#567" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#567.itm(1)} -pin  "ACC1:acc#567" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#567.itm(2)} -pin  "ACC1:acc#567" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#567.itm(3)} -pin  "ACC1:acc#567" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load inst "ACC1:acc#599" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64403 -attr oid 1593 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#568.itm(0)} -pin  "ACC1:acc#599" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#568.itm(1)} -pin  "ACC1:acc#599" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#568.itm(2)} -pin  "ACC1:acc#599" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#568.itm(3)} -pin  "ACC1:acc#599" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#568.itm}
+load net {ACC1:acc#567.itm(0)} -pin  "ACC1:acc#599" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#567.itm(1)} -pin  "ACC1:acc#599" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#567.itm(2)} -pin  "ACC1:acc#599" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#567.itm(3)} -pin  "ACC1:acc#599" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#567.itm}
+load net {ACC1:acc#599.itm(0)} -pin  "ACC1:acc#599" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(1)} -pin  "ACC1:acc#599" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(2)} -pin  "ACC1:acc#599" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(3)} -pin  "ACC1:acc#599" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(4)} -pin  "ACC1:acc#599" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load inst "ACC1:acc#513" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64404 -attr oid 1594 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#513" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1050.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#513" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1050.itm}
+load net {ACC1:acc#228.psp.sva(4)} -pin  "ACC1:acc#513" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1031.itm}
+load net {ACC1:acc#228.psp.sva(4)} -pin  "ACC1:acc#513" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1031.itm}
+load net {ACC1:acc#513.itm(0)} -pin  "ACC1:acc#513" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load net {ACC1:acc#513.itm(1)} -pin  "ACC1:acc#513" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load net {ACC1:acc#513.itm(2)} -pin  "ACC1:acc#513" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load inst "ACC1:acc#566" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64405 -attr oid 1595 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#513.itm(0)} -pin  "ACC1:acc#566" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load net {ACC1:acc#513.itm(1)} -pin  "ACC1:acc#566" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load net {ACC1:acc#513.itm(2)} -pin  "ACC1:acc#566" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#513.itm}
+load net {ACC1:acc#516.cse(0)} -pin  "ACC1:acc#566" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(1)} -pin  "ACC1:acc#566" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(2)} -pin  "ACC1:acc#566" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#566.itm(0)} -pin  "ACC1:acc#566" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#566.itm(1)} -pin  "ACC1:acc#566" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#566.itm(2)} -pin  "ACC1:acc#566" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#566.itm(3)} -pin  "ACC1:acc#566" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load inst "ACC1:acc#510" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64406 -attr oid 1596 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#510" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1060.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#510" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1060.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#510" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1049.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#510" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1049.itm}
+load net {ACC1:acc#510.itm(0)} -pin  "ACC1:acc#510" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load net {ACC1:acc#510.itm(1)} -pin  "ACC1:acc#510" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load net {ACC1:acc#510.itm(2)} -pin  "ACC1:acc#510" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load inst "ACC1:acc#565" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64407 -attr oid 1597 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#509.cse(0)} -pin  "ACC1:acc#565" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(1)} -pin  "ACC1:acc#565" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(2)} -pin  "ACC1:acc#565" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#510.itm(0)} -pin  "ACC1:acc#565" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load net {ACC1:acc#510.itm(1)} -pin  "ACC1:acc#565" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load net {ACC1:acc#510.itm(2)} -pin  "ACC1:acc#565" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#510.itm}
+load net {ACC1:acc#565.itm(0)} -pin  "ACC1:acc#565" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#565.itm(1)} -pin  "ACC1:acc#565" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#565.itm(2)} -pin  "ACC1:acc#565" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#565.itm(3)} -pin  "ACC1:acc#565" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load inst "ACC1:acc#598" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64408 -attr oid 1598 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#566.itm(0)} -pin  "ACC1:acc#598" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#566.itm(1)} -pin  "ACC1:acc#598" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#566.itm(2)} -pin  "ACC1:acc#598" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#566.itm(3)} -pin  "ACC1:acc#598" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#566.itm}
+load net {ACC1:acc#565.itm(0)} -pin  "ACC1:acc#598" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#565.itm(1)} -pin  "ACC1:acc#598" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#565.itm(2)} -pin  "ACC1:acc#598" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#565.itm(3)} -pin  "ACC1:acc#598" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#565.itm}
+load net {ACC1:acc#598.itm(0)} -pin  "ACC1:acc#598" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(1)} -pin  "ACC1:acc#598" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(2)} -pin  "ACC1:acc#598" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(3)} -pin  "ACC1:acc#598" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(4)} -pin  "ACC1:acc#598" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load inst "ACC1:acc#614" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 64409 -attr oid 1599 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#599.itm(0)} -pin  "ACC1:acc#614" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(1)} -pin  "ACC1:acc#614" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(2)} -pin  "ACC1:acc#614" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(3)} -pin  "ACC1:acc#614" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#599.itm(4)} -pin  "ACC1:acc#614" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#599.itm}
+load net {ACC1:acc#598.itm(0)} -pin  "ACC1:acc#614" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(1)} -pin  "ACC1:acc#614" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(2)} -pin  "ACC1:acc#614" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(3)} -pin  "ACC1:acc#614" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#598.itm(4)} -pin  "ACC1:acc#614" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#598.itm}
+load net {ACC1:acc#614.itm(0)} -pin  "ACC1:acc#614" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(1)} -pin  "ACC1:acc#614" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(2)} -pin  "ACC1:acc#614" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(3)} -pin  "ACC1:acc#614" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(4)} -pin  "ACC1:acc#614" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(5)} -pin  "ACC1:acc#614" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load inst "ACC1:acc#627" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 64410 -attr oid 1600 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#627" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#627" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {GND} -pin  "ACC1:acc#627" {A(2)} -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {ACC1:acc#224.psp.sva(6)} -pin  "ACC1:acc#627" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {GND} -pin  "ACC1:acc#627" {A(4)} -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {ACC1:acc#227.psp.sva(7)} -pin  "ACC1:acc#627" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1:acc#627" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#982.itm}
+load net {ACC1:acc#614.itm(0)} -pin  "ACC1:acc#627" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(1)} -pin  "ACC1:acc#627" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(2)} -pin  "ACC1:acc#627" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(3)} -pin  "ACC1:acc#627" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(4)} -pin  "ACC1:acc#627" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#614.itm(5)} -pin  "ACC1:acc#627" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#614.itm}
+load net {ACC1:acc#627.itm(0)} -pin  "ACC1:acc#627" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(1)} -pin  "ACC1:acc#627" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(2)} -pin  "ACC1:acc#627" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(3)} -pin  "ACC1:acc#627" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(4)} -pin  "ACC1:acc#627" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(5)} -pin  "ACC1:acc#627" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(6)} -pin  "ACC1:acc#627" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(7)} -pin  "ACC1:acc#627" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load inst "ACC1:not#368" "not(1)" "INTERFACE" -attr xrf 64411 -attr oid 1601 -attr @path {/sobel/sobel:core/ACC1:not#368} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#412.itm(4)} -pin  "ACC1:not#368" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#214.psp#1.sva)#6.itm}
+load net {ACC1:not#368.itm} -pin  "ACC1:not#368" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#368.itm}
+load inst "ACC1:not#369" "not(1)" "INTERFACE" -attr xrf 64412 -attr oid 1602 -attr @path {/sobel/sobel:core/ACC1:not#369} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#423.itm(3)} -pin  "ACC1:not#369" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva).itm}
+load net {ACC1:not#369.itm} -pin  "ACC1:not#369" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#369.itm}
+load inst "ACC1:not#370" "not(1)" "INTERFACE" -attr xrf 64413 -attr oid 1603 -attr @path {/sobel/sobel:core/ACC1:not#370} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#338.itm(3)} -pin  "ACC1:not#370" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#26.sva)#1.itm}
+load net {ACC1:not#370.itm} -pin  "ACC1:not#370" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#370.itm}
+load inst "ACC1:not#371" "not(1)" "INTERFACE" -attr xrf 64414 -attr oid 1604 -attr @path {/sobel/sobel:core/ACC1:not#371} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#375.itm(4)} -pin  "ACC1:not#371" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-2:acc#212.psp.sva)#8.itm}
+load net {ACC1:not#371.itm} -pin  "ACC1:not#371" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#371.itm}
+load inst "ACC1:not#390" "not(1)" "INTERFACE" -attr xrf 64415 -attr oid 1605 -attr @path {/sobel/sobel:core/ACC1:not#390} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#395.itm(3)} -pin  "ACC1:not#390" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#4.itm}
+load net {ACC1:not#390.itm} -pin  "ACC1:not#390" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#390.itm}
+load inst "ACC1:acc#523" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64416 -attr oid 1606 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:not#370.itm} -pin  "ACC1:acc#523" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1098.itm}
+load net {ACC1:not#369.itm} -pin  "ACC1:acc#523" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1098.itm}
+load net {ACC1:not#368.itm} -pin  "ACC1:acc#523" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1098.itm}
+load net {ACC1:not#390.itm} -pin  "ACC1:acc#523" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#983.itm}
+load net {PWR} -pin  "ACC1:acc#523" {B(1)} -attr @path {/sobel/sobel:core/conc#983.itm}
+load net {ACC1:not#371.itm} -pin  "ACC1:acc#523" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#983.itm}
+load net {ACC1:acc#523.itm(0)} -pin  "ACC1:acc#523" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#523.itm(1)} -pin  "ACC1:acc#523" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#523.itm(2)} -pin  "ACC1:acc#523" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#523.itm(3)} -pin  "ACC1:acc#523" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load inst "ACC1:not#373" "not(1)" "INTERFACE" -attr xrf 64417 -attr oid 1607 -attr @path {/sobel/sobel:core/ACC1:not#373} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#384.itm(4)} -pin  "ACC1:not#373" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-2:acc#208.psp.sva)#6.itm}
+load net {ACC1:not#373.itm} -pin  "ACC1:not#373" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#373.itm}
+load inst "ACC1:not#375" "not(1)" "INTERFACE" -attr xrf 64418 -attr oid 1608 -attr @path {/sobel/sobel:core/ACC1:not#375} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-3:acc#212.psp.sva(3)} -pin  "ACC1:not#375" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-3:acc#212.psp.sva)#6.itm}
+load net {ACC1:not#375.itm} -pin  "ACC1:not#375" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#375.itm}
+load inst "acc" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64419 -attr oid 1609 -attr vt d -attr @path {/sobel/sobel:core/acc} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "acc" {A(0)} -attr @path {/sobel/sobel:core/conc#984.itm}
+load net {ACC1:not#373.itm} -pin  "acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#984.itm}
+load net {PWR} -pin  "acc" {B(0)} -attr @path {/sobel/sobel:core/conc#985.itm}
+load net {ACC1:not#375.itm} -pin  "acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#985.itm}
+load net {acc.itm(0)} -pin  "acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(1)} -pin  "acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(2)} -pin  "acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load inst "ACC1:not#374" "not(1)" "INTERFACE" -attr xrf 64420 -attr oid 1610 -attr @path {/sobel/sobel:core/ACC1:not#374} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#414.itm(3)} -pin  "ACC1:not#374" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#10.sva)#4.itm}
+load net {ACC1:not#374.itm} -pin  "ACC1:not#374" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#374.itm}
+load inst "ACC1:not#376" "not(1)" "INTERFACE" -attr xrf 64421 -attr oid 1611 -attr @path {/sobel/sobel:core/ACC1:not#376} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#377.itm(3)} -pin  "ACC1:not#376" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#31.sva)#4.itm}
+load net {ACC1:not#376.itm} -pin  "ACC1:not#376" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#376.itm}
+load inst "ACC1:acc#732" "add(2,-1,2,-1,2)" "INTERFACE" -attr xrf 64422 -attr oid 1612 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#732} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2)"
+load net {ACC1:not#374.itm} -pin  "ACC1:acc#732" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#986.itm}
+load net {PWR} -pin  "ACC1:acc#732" {A(1)} -attr @path {/sobel/sobel:core/conc#986.itm}
+load net {ACC1:not#376.itm} -pin  "ACC1:acc#732" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#987.itm}
+load net {PWR} -pin  "ACC1:acc#732" {B(1)} -attr @path {/sobel/sobel:core/conc#987.itm}
+load net {ACC1:acc#732.itm(0)} -pin  "ACC1:acc#732" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#732.itm}
+load net {ACC1:acc#732.itm(1)} -pin  "ACC1:acc#732" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#732.itm}
+load inst "ACC1:acc#577" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64423 -attr oid 1613 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#523.itm(0)} -pin  "ACC1:acc#577" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#523.itm(1)} -pin  "ACC1:acc#577" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#523.itm(2)} -pin  "ACC1:acc#577" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#523.itm(3)} -pin  "ACC1:acc#577" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#523.itm}
+load net {ACC1:acc#732.itm(0)} -pin  "ACC1:acc#577" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1457.itm}
+load net {ACC1:acc#732.itm(1)} -pin  "ACC1:acc#577" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1457.itm}
+load net {acc.itm(1)} -pin  "ACC1:acc#577" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1457.itm}
+load net {acc.itm(2)} -pin  "ACC1:acc#577" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1457.itm}
+load net {ACC1:acc#577.itm(0)} -pin  "ACC1:acc#577" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(1)} -pin  "ACC1:acc#577" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(2)} -pin  "ACC1:acc#577" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(3)} -pin  "ACC1:acc#577" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(4)} -pin  "ACC1:acc#577" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load inst "ACC1:not#377" "not(1)" "INTERFACE" -attr xrf 64424 -attr oid 1614 -attr @path {/sobel/sobel:core/ACC1:not#377} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#346.itm(4)} -pin  "ACC1:not#377" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#214.psp#2.sva)#6.itm}
+load net {ACC1:not#377.itm} -pin  "ACC1:not#377" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#377.itm}
+load inst "ACC1:not#379" "not(1)" "INTERFACE" -attr xrf 64425 -attr oid 1615 -attr @path {/sobel/sobel:core/ACC1:not#379} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#208.psp.sva(3)} -pin  "ACC1:not#379" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#208.psp.sva).itm}
+load net {ACC1:not#379.itm} -pin  "ACC1:not#379" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#379.itm}
+load inst "acc#31" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64426 -attr oid 1616 -attr vt d -attr @path {/sobel/sobel:core/acc#31} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "acc#31" {A(0)} -attr @path {/sobel/sobel:core/conc#988.itm}
+load net {ACC1:not#377.itm} -pin  "acc#31" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#988.itm}
+load net {PWR} -pin  "acc#31" {B(0)} -attr @path {/sobel/sobel:core/conc#989.itm}
+load net {ACC1:not#379.itm} -pin  "acc#31" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#989.itm}
+load net {acc#31.itm(0)} -pin  "acc#31" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#31.itm}
+load net {acc#31.itm(1)} -pin  "acc#31" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#31.itm}
+load net {acc#31.itm(2)} -pin  "acc#31" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#31.itm}
+load inst "ACC1:not#378" "not(1)" "INTERFACE" -attr xrf 64427 -attr oid 1617 -attr @path {/sobel/sobel:core/ACC1:not#378} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#386.itm(3)} -pin  "ACC1:not#378" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#43.sva)#4.itm}
+load net {ACC1:not#378.itm} -pin  "ACC1:not#378" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#378.itm}
+load inst "ACC1:not#380" "not(1)" "INTERFACE" -attr xrf 64428 -attr oid 1618 -attr @path {/sobel/sobel:core/ACC1:not#380} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#405.itm(3)} -pin  "ACC1:not#380" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#4.itm}
+load net {ACC1:not#380.itm} -pin  "ACC1:not#380" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#380.itm}
+load inst "ACC1:acc#734" "add(2,-1,2,-1,2)" "INTERFACE" -attr xrf 64429 -attr oid 1619 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#734} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2)"
+load net {ACC1:not#378.itm} -pin  "ACC1:acc#734" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#990.itm}
+load net {PWR} -pin  "ACC1:acc#734" {A(1)} -attr @path {/sobel/sobel:core/conc#990.itm}
+load net {ACC1:not#380.itm} -pin  "ACC1:acc#734" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#991.itm}
+load net {PWR} -pin  "ACC1:acc#734" {B(1)} -attr @path {/sobel/sobel:core/conc#991.itm}
+load net {ACC1:acc#734.itm(0)} -pin  "ACC1:acc#734" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#734.itm}
+load net {ACC1:acc#734.itm(1)} -pin  "ACC1:acc#734" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#734.itm}
+load inst "ACC1:not#381" "not(1)" "INTERFACE" -attr xrf 64430 -attr oid 1620 -attr @path {/sobel/sobel:core/ACC1:not#381} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#210.psp#2.sva(3)} -pin  "ACC1:not#381" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#210.psp#2.sva)#12.itm}
+load net {ACC1:not#381.itm} -pin  "ACC1:not#381" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#381.itm}
+load inst "ACC1:not#392" "not(1)" "INTERFACE" -attr xrf 64431 -attr oid 1621 -attr @path {/sobel/sobel:core/ACC1:not#392} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#348.itm(3)} -pin  "ACC1:not#392" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#34.sva)#4.itm}
+load net {ACC1:not#392.itm} -pin  "ACC1:not#392" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#392.itm}
+load inst "ACC1:acc#520" "add(3,0,2,1,4)" "INTERFACE" -attr xrf 64432 -attr oid 1622 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:not#392.itm} -pin  "ACC1:acc#520" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#992.itm}
+load net {PWR} -pin  "ACC1:acc#520" {A(1)} -attr @path {/sobel/sobel:core/conc#992.itm}
+load net {ACC1:not#381.itm} -pin  "ACC1:acc#520" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#992.itm}
+load net {ACC1:acc#221.psp.sva(1)} -pin  "ACC1:acc#520" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp.sva)#2.itm}
+load net {ACC1:acc#221.psp.sva(2)} -pin  "ACC1:acc#520" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp.sva)#2.itm}
+load net {ACC1:acc#520.itm(0)} -pin  "ACC1:acc#520" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#520.itm(1)} -pin  "ACC1:acc#520" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#520.itm(2)} -pin  "ACC1:acc#520" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#520.itm(3)} -pin  "ACC1:acc#520" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load inst "ACC1:acc#576" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64433 -attr oid 1623 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#734.itm(0)} -pin  "ACC1:acc#576" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1458.itm}
+load net {ACC1:acc#734.itm(1)} -pin  "ACC1:acc#576" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1458.itm}
+load net {acc#31.itm(1)} -pin  "ACC1:acc#576" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1458.itm}
+load net {acc#31.itm(2)} -pin  "ACC1:acc#576" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1458.itm}
+load net {ACC1:acc#520.itm(0)} -pin  "ACC1:acc#576" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#520.itm(1)} -pin  "ACC1:acc#576" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#520.itm(2)} -pin  "ACC1:acc#576" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#520.itm(3)} -pin  "ACC1:acc#576" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#520.itm}
+load net {ACC1:acc#576.itm(0)} -pin  "ACC1:acc#576" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(1)} -pin  "ACC1:acc#576" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(2)} -pin  "ACC1:acc#576" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(3)} -pin  "ACC1:acc#576" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(4)} -pin  "ACC1:acc#576" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load inst "ACC1:acc#603" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 64434 -attr oid 1624 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#577.itm(0)} -pin  "ACC1:acc#603" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(1)} -pin  "ACC1:acc#603" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(2)} -pin  "ACC1:acc#603" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(3)} -pin  "ACC1:acc#603" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#577.itm(4)} -pin  "ACC1:acc#603" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#577.itm}
+load net {ACC1:acc#576.itm(0)} -pin  "ACC1:acc#603" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(1)} -pin  "ACC1:acc#603" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(2)} -pin  "ACC1:acc#603" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(3)} -pin  "ACC1:acc#603" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#576.itm(4)} -pin  "ACC1:acc#603" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#576.itm}
+load net {ACC1:acc#603.itm(0)} -pin  "ACC1:acc#603" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(1)} -pin  "ACC1:acc#603" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(2)} -pin  "ACC1:acc#603" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(3)} -pin  "ACC1:acc#603" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(4)} -pin  "ACC1:acc#603" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(5)} -pin  "ACC1:acc#603" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load inst "ACC1:acc#518" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 64435 -attr oid 1625 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#221.psp#2.sva(1)} -pin  "ACC1:acc#518" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp#2.sva)#2.itm}
+load net {ACC1:acc#221.psp#2.sva(2)} -pin  "ACC1:acc#518" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp#2.sva)#2.itm}
+load net {ACC1:acc#228.psp.sva(8)} -pin  "ACC1:acc#518" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#19.itm}
+load net {ACC1:acc#228.psp.sva(8)} -pin  "ACC1:acc#518" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#19.itm}
+load net {ACC1:acc#518.itm(0)} -pin  "ACC1:acc#518" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#518.itm(1)} -pin  "ACC1:acc#518" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#518.itm(2)} -pin  "ACC1:acc#518" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#518.itm(3)} -pin  "ACC1:acc#518" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load inst "ACC1:acc#490" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 64436 -attr oid 1626 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#219.psp#2.sva(1)} -pin  "ACC1:acc#490" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#2.sva)#2.itm}
+load net {ACC1:acc#219.psp#2.sva(2)} -pin  "ACC1:acc#490" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#2.sva)#2.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#490" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1058.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#490" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1058.itm}
+load net {ACC1:acc#490.itm(0)} -pin  "ACC1:acc#490" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#490.itm(1)} -pin  "ACC1:acc#490" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#490.itm(2)} -pin  "ACC1:acc#490" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#490.itm(3)} -pin  "ACC1:acc#490" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load inst "ACC1:acc#575" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 64437 -attr oid 1627 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#518.itm(0)} -pin  "ACC1:acc#575" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#518.itm(1)} -pin  "ACC1:acc#575" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#518.itm(2)} -pin  "ACC1:acc#575" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#518.itm(3)} -pin  "ACC1:acc#575" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#518.itm}
+load net {ACC1:acc#490.itm(0)} -pin  "ACC1:acc#575" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#490.itm(1)} -pin  "ACC1:acc#575" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#490.itm(2)} -pin  "ACC1:acc#575" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#490.itm(3)} -pin  "ACC1:acc#575" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#490.itm}
+load net {ACC1:acc#575.itm(0)} -pin  "ACC1:acc#575" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(1)} -pin  "ACC1:acc#575" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(2)} -pin  "ACC1:acc#575" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(3)} -pin  "ACC1:acc#575" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(4)} -pin  "ACC1:acc#575" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load inst "ACC1:acc#471" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 64438 -attr oid 1628 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#471" {A(0)} -attr @path {/sobel/sobel:core/exs#90.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#471" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#90.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#471" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#90.itm}
+load net {acc.psp#2.sva(2)} -pin  "ACC1:acc#471" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1401.itm}
+load net {ACC1:acc#222.psp#1.sva(1)} -pin  "ACC1:acc#471" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1401.itm}
+load net {ACC1:acc#222.psp#1.sva(2)} -pin  "ACC1:acc#471" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1401.itm}
+load net {ACC1:acc#471.itm(0)} -pin  "ACC1:acc#471" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471.itm}
+load net {ACC1:acc#471.itm(1)} -pin  "ACC1:acc#471" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471.itm}
+load net {ACC1:acc#471.itm(2)} -pin  "ACC1:acc#471" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471.itm}
+load net {ACC1:acc#471.itm(3)} -pin  "ACC1:acc#471" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471.itm}
+load net {ACC1:acc#471.itm(4)} -pin  "ACC1:acc#471" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#471.itm}
+load inst "ACC1-1:not#92" "not(1)" "INTERFACE" -attr xrf 64439 -attr oid 1629 -attr @path {/sobel/sobel:core/ACC1-1:not#92} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#349.itm(2)} -pin  "ACC1-1:not#92" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#36.sva).itm}
+load net {ACC1-1:not#92.itm} -pin  "ACC1-1:not#92" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#92.itm}
+load inst "ACC1-1:and#5" "and(3,1)" "INTERFACE" -attr xrf 64440 -attr oid 1630 -attr @path {/sobel/sobel:core/ACC1-1:and#5} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1-1:and#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#27.itm}
+load net {ACC1-1:not#92.itm} -pin  "ACC1-1:and#5" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#92.itm}
+load net {ACC1:acc#349.itm(1)} -pin  "ACC1-1:and#5" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#36.sva)#1.itm}
+load net {ACC1-1:and#5.itm} -pin  "ACC1-1:and#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#5.itm}
+load inst "ACC1:acc#461" "add(3,1,3,0,5)" "INTERFACE" -attr xrf 64441 -attr oid 1631 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#461" {A(0)} -attr @path {/sobel/sobel:core/conc#994.itm}
+load net {ACC1:acc#219.psp#1.sva(1)} -pin  "ACC1:acc#461" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#994.itm}
+load net {ACC1:acc#219.psp#1.sva(2)} -pin  "ACC1:acc#461" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#994.itm}
+load net {ACC1-1:and#5.itm} -pin  "ACC1:acc#461" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1590.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#461" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1590.itm}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1:acc#461" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1590.itm}
+load net {ACC1:acc#461.itm(0)} -pin  "ACC1:acc#461" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461.itm}
+load net {ACC1:acc#461.itm(1)} -pin  "ACC1:acc#461" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461.itm}
+load net {ACC1:acc#461.itm(2)} -pin  "ACC1:acc#461" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461.itm}
+load net {ACC1:acc#461.itm(3)} -pin  "ACC1:acc#461" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461.itm}
+load net {ACC1:acc#461.itm(4)} -pin  "ACC1:acc#461" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#461.itm}
+load inst "ACC1:acc#574" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 64442 -attr oid 1632 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#471.itm(1)} -pin  "ACC1:acc#574" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#139.itm}
+load net {ACC1:acc#471.itm(2)} -pin  "ACC1:acc#574" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#139.itm}
+load net {ACC1:acc#471.itm(3)} -pin  "ACC1:acc#574" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#139.itm}
+load net {ACC1:acc#471.itm(4)} -pin  "ACC1:acc#574" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#139.itm}
+load net {ACC1:acc#461.itm(1)} -pin  "ACC1:acc#574" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#129.itm}
+load net {ACC1:acc#461.itm(2)} -pin  "ACC1:acc#574" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#129.itm}
+load net {ACC1:acc#461.itm(3)} -pin  "ACC1:acc#574" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#129.itm}
+load net {ACC1:acc#461.itm(4)} -pin  "ACC1:acc#574" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#129.itm}
+load net {ACC1:acc#574.itm(0)} -pin  "ACC1:acc#574" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(1)} -pin  "ACC1:acc#574" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(2)} -pin  "ACC1:acc#574" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(3)} -pin  "ACC1:acc#574" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(4)} -pin  "ACC1:acc#574" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load inst "ACC1:acc#602" "add(5,1,5,1,6)" "INTERFACE" -attr xrf 64443 -attr oid 1633 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,1,5,1,6)"
+load net {ACC1:acc#575.itm(0)} -pin  "ACC1:acc#602" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(1)} -pin  "ACC1:acc#602" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(2)} -pin  "ACC1:acc#602" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(3)} -pin  "ACC1:acc#602" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#575.itm(4)} -pin  "ACC1:acc#602" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#575.itm}
+load net {ACC1:acc#574.itm(0)} -pin  "ACC1:acc#602" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(1)} -pin  "ACC1:acc#602" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(2)} -pin  "ACC1:acc#602" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(3)} -pin  "ACC1:acc#602" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#574.itm(4)} -pin  "ACC1:acc#602" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#574.itm}
+load net {ACC1:acc#602.itm(0)} -pin  "ACC1:acc#602" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(1)} -pin  "ACC1:acc#602" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(2)} -pin  "ACC1:acc#602" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(3)} -pin  "ACC1:acc#602" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(4)} -pin  "ACC1:acc#602" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(5)} -pin  "ACC1:acc#602" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load inst "ACC1:acc#621" "add(6,0,6,1,7)" "INTERFACE" -attr xrf 64444 -attr oid 1634 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {ACC1:acc#603.itm(0)} -pin  "ACC1:acc#621" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(1)} -pin  "ACC1:acc#621" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(2)} -pin  "ACC1:acc#621" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(3)} -pin  "ACC1:acc#621" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(4)} -pin  "ACC1:acc#621" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#603.itm(5)} -pin  "ACC1:acc#621" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#603.itm}
+load net {ACC1:acc#602.itm(0)} -pin  "ACC1:acc#621" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(1)} -pin  "ACC1:acc#621" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(2)} -pin  "ACC1:acc#621" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(3)} -pin  "ACC1:acc#621" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(4)} -pin  "ACC1:acc#621" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#602.itm(5)} -pin  "ACC1:acc#621" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#602.itm}
+load net {ACC1:acc#621.itm(0)} -pin  "ACC1:acc#621" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(1)} -pin  "ACC1:acc#621" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(2)} -pin  "ACC1:acc#621" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(3)} -pin  "ACC1:acc#621" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(4)} -pin  "ACC1:acc#621" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(5)} -pin  "ACC1:acc#621" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(6)} -pin  "ACC1:acc#621" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load inst "ACC1:acc#640" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 64445 -attr oid 1635 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#627.itm(0)} -pin  "ACC1:acc#640" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(1)} -pin  "ACC1:acc#640" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(2)} -pin  "ACC1:acc#640" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(3)} -pin  "ACC1:acc#640" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(4)} -pin  "ACC1:acc#640" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(5)} -pin  "ACC1:acc#640" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(6)} -pin  "ACC1:acc#640" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#627.itm(7)} -pin  "ACC1:acc#640" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#627.itm}
+load net {ACC1:acc#621.itm(0)} -pin  "ACC1:acc#640" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(1)} -pin  "ACC1:acc#640" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(2)} -pin  "ACC1:acc#640" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(3)} -pin  "ACC1:acc#640" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(4)} -pin  "ACC1:acc#640" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(5)} -pin  "ACC1:acc#640" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#621.itm(6)} -pin  "ACC1:acc#640" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#621.itm}
+load net {ACC1:acc#640.itm(0)} -pin  "ACC1:acc#640" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(1)} -pin  "ACC1:acc#640" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(2)} -pin  "ACC1:acc#640" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(3)} -pin  "ACC1:acc#640" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(4)} -pin  "ACC1:acc#640" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(5)} -pin  "ACC1:acc#640" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(6)} -pin  "ACC1:acc#640" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(7)} -pin  "ACC1:acc#640" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load inst "ACC1:acc#301" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 64446 -attr oid 1636 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#227.psp.sva(6)} -pin  "ACC1:acc#301" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#38.itm}
+load net {acc.psp#1.sva(6)} -pin  "ACC1:acc#301" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#46.itm}
+load net {ACC1:acc#301.itm(0)} -pin  "ACC1:acc#301" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {ACC1:acc#301.itm(1)} -pin  "ACC1:acc#301" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load inst "ACC1:acc#300" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 64447 -attr oid 1637 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#301.itm(0)} -pin  "ACC1:acc#300" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {ACC1:acc#301.itm(1)} -pin  "ACC1:acc#300" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {ACC1:acc#224.psp.sva(5)} -pin  "ACC1:acc#300" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#19.itm}
+load net {ACC1:acc#300.itm(0)} -pin  "ACC1:acc#300" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#300.itm(1)} -pin  "ACC1:acc#300" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load inst "ACC1:acc#299" "add(2,0,1,0,3)" "INTERFACE" -attr xrf 64448 -attr oid 1638 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#300.itm(0)} -pin  "ACC1:acc#299" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#300.itm(1)} -pin  "ACC1:acc#299" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#228.psp.sva(5)} -pin  "ACC1:acc#299" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#22.itm}
+load net {ACC1:acc#299.itm(0)} -pin  "ACC1:acc#299" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(1)} -pin  "ACC1:acc#299" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(2)} -pin  "ACC1:acc#299" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load inst "ACC1:acc#298" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 64449 -attr oid 1639 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#299.itm(0)} -pin  "ACC1:acc#298" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(1)} -pin  "ACC1:acc#298" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(2)} -pin  "ACC1:acc#298" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#226.psp.sva(5)} -pin  "ACC1:acc#298" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#17.itm}
+load net {ACC1:acc#298.itm(0)} -pin  "ACC1:acc#298" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(1)} -pin  "ACC1:acc#298" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(2)} -pin  "ACC1:acc#298" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load inst "ACC1:acc#297" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 64450 -attr oid 1640 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#298.itm(0)} -pin  "ACC1:acc#297" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(1)} -pin  "ACC1:acc#297" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(2)} -pin  "ACC1:acc#297" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#224.psp#1.sva(5)} -pin  "ACC1:acc#297" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#38.itm}
+load net {ACC1:acc#297.itm(0)} -pin  "ACC1:acc#297" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(1)} -pin  "ACC1:acc#297" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(2)} -pin  "ACC1:acc#297" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load inst "ACC1:acc#296" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 64451 -attr oid 1641 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#297.itm(0)} -pin  "ACC1:acc#296" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(1)} -pin  "ACC1:acc#296" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(2)} -pin  "ACC1:acc#296" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1-1:acc#25.psp.sva(6)} -pin  "ACC1:acc#296" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#50.itm}
+load net {ACC1:acc#296.itm(0)} -pin  "ACC1:acc#296" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(1)} -pin  "ACC1:acc#296" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(2)} -pin  "ACC1:acc#296" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load inst "ACC1:acc#295" "add(3,0,1,0,4)" "INTERFACE" -attr xrf 64452 -attr oid 1642 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {ACC1:acc#296.itm(0)} -pin  "ACC1:acc#295" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(1)} -pin  "ACC1:acc#295" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(2)} -pin  "ACC1:acc#295" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#295" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#73.itm}
+load net {ACC1:acc#295.itm(0)} -pin  "ACC1:acc#295" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(1)} -pin  "ACC1:acc#295" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(2)} -pin  "ACC1:acc#295" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(3)} -pin  "ACC1:acc#295" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load inst "ACC1:mul" "mul(4,0,5,0,8)" "INTERFACE" -attr xrf 64453 -attr oid 1643 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,5,0,8)"
+load net {ACC1:acc#295.itm(0)} -pin  "ACC1:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(1)} -pin  "ACC1:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(2)} -pin  "ACC1:mul" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(3)} -pin  "ACC1:mul" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {PWR} -pin  "ACC1:mul" {B(0)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul" {B(1)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul" {B(2)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul" {B(3)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul" {B(4)} -attr @path {/sobel/sobel:core/C21_5}
+load net {ACC1:mul.itm(0)} -pin  "ACC1:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(1)} -pin  "ACC1:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(2)} -pin  "ACC1:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(3)} -pin  "ACC1:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(4)} -pin  "ACC1:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(5)} -pin  "ACC1:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(6)} -pin  "ACC1:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(7)} -pin  "ACC1:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load inst "ACC1:acc#639" "add(8,0,8,0,9)" "INTERFACE" -attr xrf 64454 -attr oid 1644 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9)"
+load net {ACC1:mul.itm(0)} -pin  "ACC1:acc#639" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(1)} -pin  "ACC1:acc#639" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(2)} -pin  "ACC1:acc#639" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(3)} -pin  "ACC1:acc#639" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(4)} -pin  "ACC1:acc#639" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(5)} -pin  "ACC1:acc#639" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(6)} -pin  "ACC1:acc#639" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(7)} -pin  "ACC1:acc#639" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:acc#228.psp.sva(2)} -pin  "ACC1:acc#639" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {acc#20.psp#1.sva(8)} -pin  "ACC1:acc#639" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {GND} -pin  "ACC1:acc#639" {B(2)} -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {acc#20.psp#1.sva(8)} -pin  "ACC1:acc#639" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {GND} -pin  "ACC1:acc#639" {B(4)} -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {acc#20.psp#1.sva(8)} -pin  "ACC1:acc#639" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {GND} -pin  "ACC1:acc#639" {B(6)} -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {acc#20.psp#1.sva(8)} -pin  "ACC1:acc#639" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#995.itm}
+load net {ACC1:acc#639.itm(0)} -pin  "ACC1:acc#639" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(1)} -pin  "ACC1:acc#639" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(2)} -pin  "ACC1:acc#639" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(3)} -pin  "ACC1:acc#639" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(4)} -pin  "ACC1:acc#639" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(5)} -pin  "ACC1:acc#639" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(6)} -pin  "ACC1:acc#639" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(7)} -pin  "ACC1:acc#639" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(8)} -pin  "ACC1:acc#639" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load inst "ACC1:acc#647" "add(8,0,9,0,10)" "INTERFACE" -attr xrf 64455 -attr oid 1645 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,11)"
+load net {ACC1:acc#640.itm(0)} -pin  "ACC1:acc#647" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(1)} -pin  "ACC1:acc#647" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(2)} -pin  "ACC1:acc#647" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(3)} -pin  "ACC1:acc#647" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(4)} -pin  "ACC1:acc#647" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(5)} -pin  "ACC1:acc#647" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(6)} -pin  "ACC1:acc#647" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#640.itm(7)} -pin  "ACC1:acc#647" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#640.itm}
+load net {ACC1:acc#639.itm(0)} -pin  "ACC1:acc#647" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(1)} -pin  "ACC1:acc#647" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(2)} -pin  "ACC1:acc#647" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(3)} -pin  "ACC1:acc#647" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(4)} -pin  "ACC1:acc#647" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(5)} -pin  "ACC1:acc#647" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(6)} -pin  "ACC1:acc#647" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(7)} -pin  "ACC1:acc#647" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#639.itm(8)} -pin  "ACC1:acc#647" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#639.itm}
+load net {ACC1:acc#647.itm(0)} -pin  "ACC1:acc#647" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(1)} -pin  "ACC1:acc#647" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(2)} -pin  "ACC1:acc#647" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(3)} -pin  "ACC1:acc#647" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(4)} -pin  "ACC1:acc#647" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(5)} -pin  "ACC1:acc#647" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(6)} -pin  "ACC1:acc#647" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(7)} -pin  "ACC1:acc#647" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(8)} -pin  "ACC1:acc#647" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(9)} -pin  "ACC1:acc#647" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load inst "ACC1:acc#655" "add(11,1,10,0,12)" "INTERFACE" -attr xrf 64456 -attr oid 1646 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#650.itm(0)} -pin  "ACC1:acc#655" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(1)} -pin  "ACC1:acc#655" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(2)} -pin  "ACC1:acc#655" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(3)} -pin  "ACC1:acc#655" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(4)} -pin  "ACC1:acc#655" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(5)} -pin  "ACC1:acc#655" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(6)} -pin  "ACC1:acc#655" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(7)} -pin  "ACC1:acc#655" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(8)} -pin  "ACC1:acc#655" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(9)} -pin  "ACC1:acc#655" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#650.itm(10)} -pin  "ACC1:acc#655" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#650.itm}
+load net {ACC1:acc#647.itm(0)} -pin  "ACC1:acc#655" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(1)} -pin  "ACC1:acc#655" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(2)} -pin  "ACC1:acc#655" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(3)} -pin  "ACC1:acc#655" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(4)} -pin  "ACC1:acc#655" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(5)} -pin  "ACC1:acc#655" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(6)} -pin  "ACC1:acc#655" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(7)} -pin  "ACC1:acc#655" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(8)} -pin  "ACC1:acc#655" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#647.itm(9)} -pin  "ACC1:acc#655" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#647.itm}
+load net {ACC1:acc#655.itm(0)} -pin  "ACC1:acc#655" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(1)} -pin  "ACC1:acc#655" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(2)} -pin  "ACC1:acc#655" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(3)} -pin  "ACC1:acc#655" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(4)} -pin  "ACC1:acc#655" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(5)} -pin  "ACC1:acc#655" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(6)} -pin  "ACC1:acc#655" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(7)} -pin  "ACC1:acc#655" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(8)} -pin  "ACC1:acc#655" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(9)} -pin  "ACC1:acc#655" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(10)} -pin  "ACC1:acc#655" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(11)} -pin  "ACC1:acc#655" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load inst "reg(ACC1:acc#655.itm#1)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 64457 -attr oid 1647 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#655.itm#1)}
+load net {ACC1:acc#655.itm(0)} -pin  "reg(ACC1:acc#655.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(1)} -pin  "reg(ACC1:acc#655.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(2)} -pin  "reg(ACC1:acc#655.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(3)} -pin  "reg(ACC1:acc#655.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(4)} -pin  "reg(ACC1:acc#655.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(5)} -pin  "reg(ACC1:acc#655.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(6)} -pin  "reg(ACC1:acc#655.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(7)} -pin  "reg(ACC1:acc#655.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(8)} -pin  "reg(ACC1:acc#655.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(9)} -pin  "reg(ACC1:acc#655.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(10)} -pin  "reg(ACC1:acc#655.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {ACC1:acc#655.itm(11)} -pin  "reg(ACC1:acc#655.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#655.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(ACC1:acc#655.itm#1)" {clk} -attr xrf 64458 -attr oid 1648 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#655.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#655.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#655.itm#1(0)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(1)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(2)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(3)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(4)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(5)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(6)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(7)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(8)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(9)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(10)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(11)} -pin  "reg(ACC1:acc#655.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load inst "reg(main.stage_0#2)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 64459 -attr oid 1649 -attr @path {/sobel/sobel:core/reg(main.stage_0#2)}
+load net {PWR} -pin  "reg(main.stage_0#2)" {D(0)} -attr @path {/sobel/sobel:core/C0_10#10_Not}
+load net {GND} -pin  "reg(main.stage_0#2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#10}
+load net {clk} -pin  "reg(main.stage_0#2)" {clk} -attr xrf 64460 -attr oid 1650 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(main.stage_0#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(main.stage_0#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {main.stage_0#2} -pin  "reg(main.stage_0#2)" {Z(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load inst "reg(regs.regs:slc(regs.regs(2))#10.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 64461 -attr oid 1651 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#10.itm)}
+load net {reg(regs.regs(0).sva).cse(70)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(71)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(72)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(73)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(74)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(75)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(76)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(77)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(78)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(79)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {clk} -attr xrf 64462 -attr oid 1652 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#10.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#10.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#11.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 64463 -attr oid 1653 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#11.itm)}
+load net {reg(regs.regs(0).sva).cse(60)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(61)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(62)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(63)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(64)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(65)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(66)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(67)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(68)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(69)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {clk} -attr xrf 64464 -attr oid 1654 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#11.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#11.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#9.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 64465 -attr oid 1655 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#9.itm)}
+load net {reg(regs.regs(0).sva).cse(80)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(81)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(82)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(83)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(84)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(85)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(86)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(87)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(88)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {reg(regs.regs(0).sva).cse(89)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {clk} -attr xrf 64466 -attr oid 1656 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#9.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#9.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#4.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 64467 -attr oid 1657 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#4.itm)}
+load net {reg(regs.regs(0).sva).cse(40)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(41)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(42)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(43)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(44)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(45)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(46)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(47)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(48)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(49)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {clk} -attr xrf 64468 -attr oid 1658 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#4.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#4.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#5.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 64469 -attr oid 1659 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#5.itm)}
+load net {reg(regs.regs(0).sva).cse(30)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(31)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(32)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(33)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(34)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(35)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(36)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(37)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(38)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(39)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {clk} -attr xrf 64470 -attr oid 1660 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#5.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#5.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#3.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 64471 -attr oid 1661 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#3.itm)}
+load net {reg(regs.regs(0).sva).cse(50)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(51)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(52)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(53)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(54)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(55)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(56)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(57)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(58)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(59)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {clk} -attr xrf 64472 -attr oid 1662 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#3.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#3.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load inst "reg(regs.regs:slc(regs.regs(2)).itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 64473 -attr oid 1663 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2)).itm)}
+load net {reg(regs.regs(0).sva).cse(20)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(21)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(22)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(23)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(24)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(25)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(26)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(27)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(28)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {reg(regs.regs(0).sva).cse(29)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {clk} -attr xrf 64474 -attr oid 1664 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2)).itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#1.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 64475 -attr oid 1665 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#1.itm)}
+load net {reg(regs.regs(0).sva).cse(10)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(11)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(12)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(13)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(14)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(15)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(16)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(17)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(18)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {reg(regs.regs(0).sva).cse(19)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {clk} -attr xrf 64476 -attr oid 1666 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#1.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#1.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#2.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 64477 -attr oid 1667 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#2.itm)}
+load net {reg(regs.regs(0).sva).cse(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {reg(regs.regs(0).sva).cse(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#11}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {clk} -attr xrf 64478 -attr oid 1668 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#2.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#2.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load inst "reg(regs.regs(0).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 64479 -attr oid 1669 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva)}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "reg(regs.regs(0).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "reg(regs.regs(0).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "reg(regs.regs(0).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "reg(regs.regs(0).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "reg(regs.regs(0).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "reg(regs.regs(0).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "reg(regs.regs(0).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "reg(regs.regs(0).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "reg(regs.regs(0).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "reg(regs.regs(0).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "reg(regs.regs(0).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "reg(regs.regs(0).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "reg(regs.regs(0).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "reg(regs.regs(0).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "reg(regs.regs(0).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "reg(regs.regs(0).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "reg(regs.regs(0).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "reg(regs.regs(0).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "reg(regs.regs(0).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "reg(regs.regs(0).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "reg(regs.regs(0).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "reg(regs.regs(0).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "reg(regs.regs(0).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "reg(regs.regs(0).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "reg(regs.regs(0).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "reg(regs.regs(0).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "reg(regs.regs(0).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "reg(regs.regs(0).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "reg(regs.regs(0).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "reg(regs.regs(0).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "reg(regs.regs(0).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "reg(regs.regs(0).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "reg(regs.regs(0).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "reg(regs.regs(0).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "reg(regs.regs(0).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "reg(regs.regs(0).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "reg(regs.regs(0).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "reg(regs.regs(0).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "reg(regs.regs(0).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "reg(regs.regs(0).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "reg(regs.regs(0).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "reg(regs.regs(0).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "reg(regs.regs(0).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "reg(regs.regs(0).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "reg(regs.regs(0).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "reg(regs.regs(0).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "reg(regs.regs(0).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "reg(regs.regs(0).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "reg(regs.regs(0).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "reg(regs.regs(0).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "reg(regs.regs(0).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "reg(regs.regs(0).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "reg(regs.regs(0).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "reg(regs.regs(0).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "reg(regs.regs(0).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "reg(regs.regs(0).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "reg(regs.regs(0).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "reg(regs.regs(0).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "reg(regs.regs(0).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "reg(regs.regs(0).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "reg(regs.regs(0).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "reg(regs.regs(0).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "reg(regs.regs(0).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "reg(regs.regs(0).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "reg(regs.regs(0).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "reg(regs.regs(0).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "reg(regs.regs(0).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "reg(regs.regs(0).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "reg(regs.regs(0).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "reg(regs.regs(0).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "reg(regs.regs(0).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "reg(regs.regs(0).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "reg(regs.regs(0).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "reg(regs.regs(0).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "reg(regs.regs(0).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "reg(regs.regs(0).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "reg(regs.regs(0).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "reg(regs.regs(0).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "reg(regs.regs(0).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "reg(regs.regs(0).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "reg(regs.regs(0).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "reg(regs.regs(0).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "reg(regs.regs(0).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "reg(regs.regs(0).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "reg(regs.regs(0).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "reg(regs.regs(0).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "reg(regs.regs(0).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "reg(regs.regs(0).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "reg(regs.regs(0).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "reg(regs.regs(0).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {clk} -pin  "reg(regs.regs(0).sva)" {clk} -attr xrf 64480 -attr oid 1670 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(0).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(0).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {reg(regs.regs(0).sva).cse(0)} -pin  "reg(regs.regs(0).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(1)} -pin  "reg(regs.regs(0).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(2)} -pin  "reg(regs.regs(0).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(3)} -pin  "reg(regs.regs(0).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(4)} -pin  "reg(regs.regs(0).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(5)} -pin  "reg(regs.regs(0).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(6)} -pin  "reg(regs.regs(0).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(7)} -pin  "reg(regs.regs(0).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(8)} -pin  "reg(regs.regs(0).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(9)} -pin  "reg(regs.regs(0).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(10)} -pin  "reg(regs.regs(0).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(11)} -pin  "reg(regs.regs(0).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(12)} -pin  "reg(regs.regs(0).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(13)} -pin  "reg(regs.regs(0).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(14)} -pin  "reg(regs.regs(0).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(15)} -pin  "reg(regs.regs(0).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(16)} -pin  "reg(regs.regs(0).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(17)} -pin  "reg(regs.regs(0).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(18)} -pin  "reg(regs.regs(0).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(19)} -pin  "reg(regs.regs(0).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(20)} -pin  "reg(regs.regs(0).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(21)} -pin  "reg(regs.regs(0).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(22)} -pin  "reg(regs.regs(0).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(23)} -pin  "reg(regs.regs(0).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(24)} -pin  "reg(regs.regs(0).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(25)} -pin  "reg(regs.regs(0).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(26)} -pin  "reg(regs.regs(0).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(27)} -pin  "reg(regs.regs(0).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(28)} -pin  "reg(regs.regs(0).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(29)} -pin  "reg(regs.regs(0).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(30)} -pin  "reg(regs.regs(0).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(31)} -pin  "reg(regs.regs(0).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(32)} -pin  "reg(regs.regs(0).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(33)} -pin  "reg(regs.regs(0).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(34)} -pin  "reg(regs.regs(0).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(35)} -pin  "reg(regs.regs(0).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(36)} -pin  "reg(regs.regs(0).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(37)} -pin  "reg(regs.regs(0).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(38)} -pin  "reg(regs.regs(0).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(39)} -pin  "reg(regs.regs(0).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(40)} -pin  "reg(regs.regs(0).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(41)} -pin  "reg(regs.regs(0).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(42)} -pin  "reg(regs.regs(0).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(43)} -pin  "reg(regs.regs(0).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(44)} -pin  "reg(regs.regs(0).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(45)} -pin  "reg(regs.regs(0).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(46)} -pin  "reg(regs.regs(0).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(47)} -pin  "reg(regs.regs(0).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(48)} -pin  "reg(regs.regs(0).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(49)} -pin  "reg(regs.regs(0).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(50)} -pin  "reg(regs.regs(0).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(51)} -pin  "reg(regs.regs(0).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(52)} -pin  "reg(regs.regs(0).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(53)} -pin  "reg(regs.regs(0).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(54)} -pin  "reg(regs.regs(0).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(55)} -pin  "reg(regs.regs(0).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(56)} -pin  "reg(regs.regs(0).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(57)} -pin  "reg(regs.regs(0).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(58)} -pin  "reg(regs.regs(0).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(59)} -pin  "reg(regs.regs(0).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(60)} -pin  "reg(regs.regs(0).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(61)} -pin  "reg(regs.regs(0).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(62)} -pin  "reg(regs.regs(0).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(63)} -pin  "reg(regs.regs(0).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(64)} -pin  "reg(regs.regs(0).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(65)} -pin  "reg(regs.regs(0).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(66)} -pin  "reg(regs.regs(0).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(67)} -pin  "reg(regs.regs(0).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(68)} -pin  "reg(regs.regs(0).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(69)} -pin  "reg(regs.regs(0).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(70)} -pin  "reg(regs.regs(0).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(71)} -pin  "reg(regs.regs(0).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(72)} -pin  "reg(regs.regs(0).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(73)} -pin  "reg(regs.regs(0).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(74)} -pin  "reg(regs.regs(0).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(75)} -pin  "reg(regs.regs(0).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(76)} -pin  "reg(regs.regs(0).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(77)} -pin  "reg(regs.regs(0).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(78)} -pin  "reg(regs.regs(0).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(79)} -pin  "reg(regs.regs(0).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(80)} -pin  "reg(regs.regs(0).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(81)} -pin  "reg(regs.regs(0).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(82)} -pin  "reg(regs.regs(0).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(83)} -pin  "reg(regs.regs(0).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(84)} -pin  "reg(regs.regs(0).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(85)} -pin  "reg(regs.regs(0).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(86)} -pin  "reg(regs.regs(0).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(87)} -pin  "reg(regs.regs(0).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(88)} -pin  "reg(regs.regs(0).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load net {reg(regs.regs(0).sva).cse(89)} -pin  "reg(regs.regs(0).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva).cse}
+load inst "FRAME:mul" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 64481 -attr oid 1671 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,11,1,13)"
+load net {ACC1:acc.itm(13)} -pin  "FRAME:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#13.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#13.itm}
+load net {PWR} -pin  "FRAME:mul" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul.itm(0)} -pin  "FRAME:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(1)} -pin  "FRAME:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(2)} -pin  "FRAME:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(3)} -pin  "FRAME:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(4)} -pin  "FRAME:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(5)} -pin  "FRAME:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(6)} -pin  "FRAME:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(7)} -pin  "FRAME:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(8)} -pin  "FRAME:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(9)} -pin  "FRAME:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(10)} -pin  "FRAME:mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load inst "FRAME:mul#1" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 64482 -attr oid 1672 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc.itm(10)} -pin  "FRAME:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#1.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#1.itm}
+load net {ACC1:acc.itm(12)} -pin  "FRAME:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#1.itm}
+load net {PWR} -pin  "FRAME:mul#1" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#1.itm(0)} -pin  "FRAME:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "FRAME:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "FRAME:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "FRAME:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "FRAME:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "FRAME:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "FRAME:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "FRAME:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "FRAME:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load inst "FRAME:not#7" "not(1)" "INTERFACE" -attr xrf 64483 -attr oid 1673 -attr @path {/sobel/sobel:core/FRAME:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#24.sva(5)} -pin  "FRAME:not#7" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#6.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load inst "FRAME:not#5" "not(3)" "INTERFACE" -attr xrf 64484 -attr oid 1674 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#24.sva(3)} -pin  "FRAME:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#2.itm}
+load net {acc.imod#24.sva(4)} -pin  "FRAME:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#2.itm}
+load net {acc.imod#24.sva(5)} -pin  "FRAME:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#2.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load inst "FRAME:not#4" "not(1)" "INTERFACE" -attr xrf 64485 -attr oid 1675 -attr @path {/sobel/sobel:core/FRAME:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#24.sva(5)} -pin  "FRAME:not#4" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#3.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:not#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#4.itm}
+load inst "FRAME:acc#16" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 64486 -attr oid 1676 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "FRAME:acc#16" {A(0)} -attr @path {/sobel/sobel:core/conc#998.itm}
+load net {acc.imod#24.sva(0)} -pin  "FRAME:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#998.itm}
+load net {acc.imod#24.sva(1)} -pin  "FRAME:acc#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#998.itm}
+load net {acc.imod#24.sva(2)} -pin  "FRAME:acc#16" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#998.itm}
+load net {PWR} -pin  "FRAME:acc#16" {A(4)} -attr @path {/sobel/sobel:core/conc#998.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:acc#16" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:acc#16" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:acc#16" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:acc#16" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:acc#16.itm(0)} -pin  "FRAME:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "FRAME:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "FRAME:acc#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
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+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:acc#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
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+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:not#14" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#3.itm}
+load net {FRAME:not#14.itm} -pin  "FRAME:not#14" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
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+load net {FRAME:not#14.itm} -pin  "FRAME:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#997.itm}
+load net {PWR} -pin  "FRAME:acc#10" {A(1)} -attr @path {/sobel/sobel:core/conc#997.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#997.itm}
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+load net {acc.imod#24.sva(4)} -pin  "FRAME:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#4.itm}
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+load net {FRAME:acc#15.itm(8)} -pin  "FRAME:acc#15" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(9)} -pin  "FRAME:acc#15" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(10)} -pin  "FRAME:acc#15" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(11)} -pin  "FRAME:acc#15" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load inst "FRAME:acc#2" "add(12,-1,11,0,12)" "INTERFACE" -attr xrf 64495 -attr oid 1685 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(5)} -pin  "FRAME:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(6)} -pin  "FRAME:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(7)} -pin  "FRAME:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(8)} -pin  "FRAME:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(9)} -pin  "FRAME:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(10)} -pin  "FRAME:acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(11)} -pin  "FRAME:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(1)} -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(5)} -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(6)} -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(7)} -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/exs#103.itm}
+load net {FRAME:acc#2.psp.sva(0)} -pin  "FRAME:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "FRAME:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "FRAME:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "FRAME:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "FRAME:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "FRAME:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "FRAME:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "FRAME:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "FRAME:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "FRAME:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(10)} -pin  "FRAME:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(11)} -pin  "FRAME:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load inst "ACC1:acc#662" "add(13,1,13,1,14)" "INTERFACE" -attr xrf 64496 -attr oid 1686 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662} -attr area 14.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,1,13,1,14)"
+load net {ACC1:acc#659.itm#1(0)} -pin  "ACC1:acc#662" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(1)} -pin  "ACC1:acc#662" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(2)} -pin  "ACC1:acc#662" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(3)} -pin  "ACC1:acc#662" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(4)} -pin  "ACC1:acc#662" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(5)} -pin  "ACC1:acc#662" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(6)} -pin  "ACC1:acc#662" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(7)} -pin  "ACC1:acc#662" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(8)} -pin  "ACC1:acc#662" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(9)} -pin  "ACC1:acc#662" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(10)} -pin  "ACC1:acc#662" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(11)} -pin  "ACC1:acc#662" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#659.itm#1(12)} -pin  "ACC1:acc#662" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#659.itm#1}
+load net {ACC1:acc#658.itm#1(0)} -pin  "ACC1:acc#662" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(1)} -pin  "ACC1:acc#662" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(2)} -pin  "ACC1:acc#662" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(3)} -pin  "ACC1:acc#662" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(4)} -pin  "ACC1:acc#662" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(5)} -pin  "ACC1:acc#662" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(6)} -pin  "ACC1:acc#662" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(7)} -pin  "ACC1:acc#662" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(8)} -pin  "ACC1:acc#662" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(9)} -pin  "ACC1:acc#662" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(10)} -pin  "ACC1:acc#662" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(11)} -pin  "ACC1:acc#662" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#658.itm#1(12)} -pin  "ACC1:acc#662" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#658.itm#1}
+load net {ACC1:acc#662.itm(0)} -pin  "ACC1:acc#662" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(1)} -pin  "ACC1:acc#662" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(2)} -pin  "ACC1:acc#662" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(3)} -pin  "ACC1:acc#662" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(4)} -pin  "ACC1:acc#662" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(5)} -pin  "ACC1:acc#662" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(6)} -pin  "ACC1:acc#662" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(7)} -pin  "ACC1:acc#662" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(8)} -pin  "ACC1:acc#662" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(9)} -pin  "ACC1:acc#662" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(10)} -pin  "ACC1:acc#662" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(11)} -pin  "ACC1:acc#662" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(12)} -pin  "ACC1:acc#662" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(13)} -pin  "ACC1:acc#662" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load inst "ACC1:acc#664" "add(14,1,14,1,15)" "INTERFACE" -attr xrf 64497 -attr oid 1687 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664} -attr area 15.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(14,1,14,1,15)"
+load net {ACC1:acc#662.itm(0)} -pin  "ACC1:acc#664" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(1)} -pin  "ACC1:acc#664" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(2)} -pin  "ACC1:acc#664" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(3)} -pin  "ACC1:acc#664" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(4)} -pin  "ACC1:acc#664" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(5)} -pin  "ACC1:acc#664" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(6)} -pin  "ACC1:acc#664" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(7)} -pin  "ACC1:acc#664" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(8)} -pin  "ACC1:acc#664" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(9)} -pin  "ACC1:acc#664" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(10)} -pin  "ACC1:acc#664" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(11)} -pin  "ACC1:acc#664" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(12)} -pin  "ACC1:acc#664" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#662.itm(13)} -pin  "ACC1:acc#664" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#662.itm}
+load net {ACC1:acc#661.itm#1(0)} -pin  "ACC1:acc#664" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(1)} -pin  "ACC1:acc#664" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(2)} -pin  "ACC1:acc#664" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(3)} -pin  "ACC1:acc#664" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(4)} -pin  "ACC1:acc#664" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(5)} -pin  "ACC1:acc#664" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(6)} -pin  "ACC1:acc#664" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(7)} -pin  "ACC1:acc#664" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(8)} -pin  "ACC1:acc#664" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(9)} -pin  "ACC1:acc#664" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(10)} -pin  "ACC1:acc#664" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(11)} -pin  "ACC1:acc#664" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(12)} -pin  "ACC1:acc#664" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#661.itm#1(13)} -pin  "ACC1:acc#664" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#661.itm#1}
+load net {ACC1:acc#664.itm(0)} -pin  "ACC1:acc#664" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(1)} -pin  "ACC1:acc#664" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(2)} -pin  "ACC1:acc#664" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(3)} -pin  "ACC1:acc#664" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(4)} -pin  "ACC1:acc#664" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(5)} -pin  "ACC1:acc#664" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(6)} -pin  "ACC1:acc#664" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(7)} -pin  "ACC1:acc#664" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(8)} -pin  "ACC1:acc#664" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(9)} -pin  "ACC1:acc#664" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(10)} -pin  "ACC1:acc#664" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(11)} -pin  "ACC1:acc#664" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(12)} -pin  "ACC1:acc#664" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(13)} -pin  "ACC1:acc#664" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(14)} -pin  "ACC1:acc#664" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load inst "ACC1:acc#656" "add(12,-1,11,0,12)" "INTERFACE" -attr xrf 64498 -attr oid 1688 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1-3:slc(acc#10.psp)#62.itm#1} -pin  "ACC1:acc#656" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {ACC1-3:slc(acc#10.psp)#62.itm#1} -pin  "ACC1:acc#656" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {GND} -pin  "ACC1:acc#656" {A(2)} -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {ACC1:slc(ACC1:acc#228.psp)#55.itm#1} -pin  "ACC1:acc#656" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {slc(acc#20.psp#1)#93.itm#1} -pin  "ACC1:acc#656" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {GND} -pin  "ACC1:acc#656" {A(5)} -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {slc(acc#20.psp#1)#93.itm#1} -pin  "ACC1:acc#656" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {GND} -pin  "ACC1:acc#656" {A(7)} -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {slc(acc#20.psp#1)#93.itm#1} -pin  "ACC1:acc#656" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {GND} -pin  "ACC1:acc#656" {A(9)} -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {GND} -pin  "ACC1:acc#656" {A(10)} -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {slc(acc#20.psp#1)#93.itm#1} -pin  "ACC1:acc#656" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#1002.itm}
+load net {ACC1:acc#652.itm#1(0)} -pin  "ACC1:acc#656" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(1)} -pin  "ACC1:acc#656" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(2)} -pin  "ACC1:acc#656" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(3)} -pin  "ACC1:acc#656" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(4)} -pin  "ACC1:acc#656" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(5)} -pin  "ACC1:acc#656" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(6)} -pin  "ACC1:acc#656" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(7)} -pin  "ACC1:acc#656" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(8)} -pin  "ACC1:acc#656" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(9)} -pin  "ACC1:acc#656" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#652.itm#1(10)} -pin  "ACC1:acc#656" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#652.itm#1}
+load net {ACC1:acc#656.itm(0)} -pin  "ACC1:acc#656" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(1)} -pin  "ACC1:acc#656" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(2)} -pin  "ACC1:acc#656" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(3)} -pin  "ACC1:acc#656" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(4)} -pin  "ACC1:acc#656" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(5)} -pin  "ACC1:acc#656" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(6)} -pin  "ACC1:acc#656" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(7)} -pin  "ACC1:acc#656" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(8)} -pin  "ACC1:acc#656" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(9)} -pin  "ACC1:acc#656" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(10)} -pin  "ACC1:acc#656" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(11)} -pin  "ACC1:acc#656" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load inst "ACC1:acc#660" "add(12,1,12,1,13)" "INTERFACE" -attr xrf 64499 -attr oid 1689 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1:acc#656.itm(0)} -pin  "ACC1:acc#660" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(1)} -pin  "ACC1:acc#660" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(2)} -pin  "ACC1:acc#660" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(3)} -pin  "ACC1:acc#660" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(4)} -pin  "ACC1:acc#660" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(5)} -pin  "ACC1:acc#660" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(6)} -pin  "ACC1:acc#660" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(7)} -pin  "ACC1:acc#660" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(8)} -pin  "ACC1:acc#660" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(9)} -pin  "ACC1:acc#660" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(10)} -pin  "ACC1:acc#660" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#656.itm(11)} -pin  "ACC1:acc#660" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#656.itm}
+load net {ACC1:acc#655.itm#1(0)} -pin  "ACC1:acc#660" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(1)} -pin  "ACC1:acc#660" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(2)} -pin  "ACC1:acc#660" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(3)} -pin  "ACC1:acc#660" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(4)} -pin  "ACC1:acc#660" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(5)} -pin  "ACC1:acc#660" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(6)} -pin  "ACC1:acc#660" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(7)} -pin  "ACC1:acc#660" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(8)} -pin  "ACC1:acc#660" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(9)} -pin  "ACC1:acc#660" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(10)} -pin  "ACC1:acc#660" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#655.itm#1(11)} -pin  "ACC1:acc#660" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#655.itm#1}
+load net {ACC1:acc#660.itm(0)} -pin  "ACC1:acc#660" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(1)} -pin  "ACC1:acc#660" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(2)} -pin  "ACC1:acc#660" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(3)} -pin  "ACC1:acc#660" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(4)} -pin  "ACC1:acc#660" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(5)} -pin  "ACC1:acc#660" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(6)} -pin  "ACC1:acc#660" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(7)} -pin  "ACC1:acc#660" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(8)} -pin  "ACC1:acc#660" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(9)} -pin  "ACC1:acc#660" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(10)} -pin  "ACC1:acc#660" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(11)} -pin  "ACC1:acc#660" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(12)} -pin  "ACC1:acc#660" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load inst "ACC1:acc#663" "add(14,-1,13,1,14)" "INTERFACE" -attr xrf 64500 -attr oid 1690 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663} -attr area 15.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(14,1,14,1,15)"
+load net {ACC1:mul#57.itm#2(0)} -pin  "ACC1:acc#663" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:mul#57.itm#2(1)} -pin  "ACC1:acc#663" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(2)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(3)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(4)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(5)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(6)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(7)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {GND} -pin  "ACC1:acc#663" {A(8)} -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:mul#57.itm#1.sg2(0)} -pin  "ACC1:acc#663" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:mul#57.itm#1.sg2(1)} -pin  "ACC1:acc#663" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:mul#57.itm#1.sg2(2)} -pin  "ACC1:acc#663" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:mul#57.itm#1.sg2(3)} -pin  "ACC1:acc#663" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:mul#57.itm#1.sg2(4)} -pin  "ACC1:acc#663" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/conc#1001.itm}
+load net {ACC1:acc#660.itm(0)} -pin  "ACC1:acc#663" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(1)} -pin  "ACC1:acc#663" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(2)} -pin  "ACC1:acc#663" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(3)} -pin  "ACC1:acc#663" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(4)} -pin  "ACC1:acc#663" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(5)} -pin  "ACC1:acc#663" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(6)} -pin  "ACC1:acc#663" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(7)} -pin  "ACC1:acc#663" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(8)} -pin  "ACC1:acc#663" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(9)} -pin  "ACC1:acc#663" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(10)} -pin  "ACC1:acc#663" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(11)} -pin  "ACC1:acc#663" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#660.itm(12)} -pin  "ACC1:acc#663" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#660.itm}
+load net {ACC1:acc#663.itm(0)} -pin  "ACC1:acc#663" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(1)} -pin  "ACC1:acc#663" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(2)} -pin  "ACC1:acc#663" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(3)} -pin  "ACC1:acc#663" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(4)} -pin  "ACC1:acc#663" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(5)} -pin  "ACC1:acc#663" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(6)} -pin  "ACC1:acc#663" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(7)} -pin  "ACC1:acc#663" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(8)} -pin  "ACC1:acc#663" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(9)} -pin  "ACC1:acc#663" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(10)} -pin  "ACC1:acc#663" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(11)} -pin  "ACC1:acc#663" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(12)} -pin  "ACC1:acc#663" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(13)} -pin  "ACC1:acc#663" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load inst "ACC1:acc" "add(15,-1,14,1,15)" "INTERFACE" -attr xrf 64501 -attr oid 1691 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc} -attr area 16.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,14,1,15)"
+load net {ACC1:acc#664.itm(0)} -pin  "ACC1:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(1)} -pin  "ACC1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(2)} -pin  "ACC1:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(3)} -pin  "ACC1:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(4)} -pin  "ACC1:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(5)} -pin  "ACC1:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(6)} -pin  "ACC1:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(7)} -pin  "ACC1:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(8)} -pin  "ACC1:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(9)} -pin  "ACC1:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(10)} -pin  "ACC1:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(11)} -pin  "ACC1:acc" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(12)} -pin  "ACC1:acc" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(13)} -pin  "ACC1:acc" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#664.itm(14)} -pin  "ACC1:acc" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#664.itm}
+load net {ACC1:acc#663.itm(0)} -pin  "ACC1:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(1)} -pin  "ACC1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(2)} -pin  "ACC1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(3)} -pin  "ACC1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(4)} -pin  "ACC1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(5)} -pin  "ACC1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(6)} -pin  "ACC1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(7)} -pin  "ACC1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(8)} -pin  "ACC1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(9)} -pin  "ACC1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(10)} -pin  "ACC1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(11)} -pin  "ACC1:acc" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(12)} -pin  "ACC1:acc" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc#663.itm(13)} -pin  "ACC1:acc" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#663.itm}
+load net {ACC1:acc.itm(0)} -pin  "ACC1:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(1)} -pin  "ACC1:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(2)} -pin  "ACC1:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(3)} -pin  "ACC1:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(4)} -pin  "ACC1:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(5)} -pin  "ACC1:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(6)} -pin  "ACC1:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(7)} -pin  "ACC1:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(8)} -pin  "ACC1:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(9)} -pin  "ACC1:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(10)} -pin  "ACC1:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(11)} -pin  "ACC1:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(12)} -pin  "ACC1:acc" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(13)} -pin  "ACC1:acc" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(14)} -pin  "ACC1:acc" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load inst "FRAME:not#2" "not(3)" "INTERFACE" -attr xrf 64502 -attr oid 1692 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(10)} -pin  "FRAME:not#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#6.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:not#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#6.itm}
+load net {ACC1:acc.itm(12)} -pin  "FRAME:not#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#6.itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:not#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:not#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:not#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load inst "FRAME:acc#6" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64503 -attr oid 1693 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc.itm(7)} -pin  "FRAME:acc#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#5.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:acc#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#5.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:acc#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#5.itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:acc#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:acc#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:acc#6" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:acc#6.itm(0)} -pin  "FRAME:acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(1)} -pin  "FRAME:acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(2)} -pin  "FRAME:acc#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(3)} -pin  "FRAME:acc#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load inst "FRAME:not#12" "not(1)" "INTERFACE" -attr xrf 64504 -attr oid 1694 -attr @path {/sobel/sobel:core/FRAME:not#12} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc.itm(14)} -pin  "FRAME:not#12" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#29.itm}
+load net {FRAME:not#12.itm} -pin  "FRAME:not#12" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#12.itm}
+load inst "FRAME:not#16" "not(1)" "INTERFACE" -attr xrf 64505 -attr oid 1695 -attr @path {/sobel/sobel:core/FRAME:not#16} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc.itm(14)} -pin  "FRAME:not#16" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#11.itm}
+load net {FRAME:not#16.itm} -pin  "FRAME:not#16" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load inst "FRAME:acc#5" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 64506 -attr oid 1696 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {FRAME:not#16.itm} -pin  "FRAME:acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1003.itm}
+load net {PWR} -pin  "FRAME:acc#5" {A(1)} -attr @path {/sobel/sobel:core/conc#1003.itm}
+load net {FRAME:not#12.itm} -pin  "FRAME:acc#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1003.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#5" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva).itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#5" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva).itm}
+load net {FRAME:acc#5.itm(0)} -pin  "FRAME:acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(1)} -pin  "FRAME:acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(2)} -pin  "FRAME:acc#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(3)} -pin  "FRAME:acc#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load inst "FRAME:acc#8" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 64507 -attr oid 1697 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#6.itm(0)} -pin  "FRAME:acc#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(1)} -pin  "FRAME:acc#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(2)} -pin  "FRAME:acc#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(3)} -pin  "FRAME:acc#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#5.itm(0)} -pin  "FRAME:acc#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(1)} -pin  "FRAME:acc#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(2)} -pin  "FRAME:acc#8" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(3)} -pin  "FRAME:acc#8" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(4)} -pin  "FRAME:acc#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load inst "FRAME:not#1" "not(3)" "INTERFACE" -attr xrf 64508 -attr oid 1698 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(4)} -pin  "FRAME:not#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#8.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:not#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#8.itm}
+load net {ACC1:acc.itm(6)} -pin  "FRAME:not#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#8.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:not#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:not#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:not#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load inst "FRAME:acc#7" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64509 -attr oid 1699 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc.itm(1)} -pin  "FRAME:acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#7.itm}
+load net {ACC1:acc.itm(2)} -pin  "FRAME:acc#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#7.itm}
+load net {ACC1:acc.itm(3)} -pin  "FRAME:acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#7.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:acc#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:acc#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:acc#7" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load inst "FRAME:acc#9" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 64510 -attr oid 1700 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#9" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(4)} -pin  "FRAME:acc#9" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#9" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#9" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#9" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#9" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(4)} -pin  "FRAME:acc#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(5)} -pin  "FRAME:acc#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load inst "acc#30" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 64511 -attr oid 1701 -attr vt d -attr @path {/sobel/sobel:core/acc#30} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {FRAME:acc#9.itm(0)} -pin  "acc#30" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "acc#30" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "acc#30" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "acc#30" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(4)} -pin  "acc#30" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(5)} -pin  "acc#30" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {PWR} -pin  "acc#30" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#30" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#30" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#30" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#30" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#30" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#24.sva(0)} -pin  "acc#30" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load net {acc.imod#24.sva(1)} -pin  "acc#30" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load net {acc.imod#24.sva(2)} -pin  "acc#30" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load net {acc.imod#24.sva(3)} -pin  "acc#30" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load net {acc.imod#24.sva(4)} -pin  "acc#30" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load net {acc.imod#24.sva(5)} -pin  "acc#30" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#24.sva}
+load inst "ACC1:acc#416" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 64512 -attr oid 1702 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.regs:slc(regs.regs(2))#10.itm(0)} -pin  "ACC1:acc#416" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(1)} -pin  "ACC1:acc#416" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(2)} -pin  "ACC1:acc#416" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(3)} -pin  "ACC1:acc#416" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(4)} -pin  "ACC1:acc#416" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(5)} -pin  "ACC1:acc#416" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(6)} -pin  "ACC1:acc#416" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(7)} -pin  "ACC1:acc#416" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(8)} -pin  "ACC1:acc#416" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#10.itm(9)} -pin  "ACC1:acc#416" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#10.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(0)} -pin  "ACC1:acc#416" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(1)} -pin  "ACC1:acc#416" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(2)} -pin  "ACC1:acc#416" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(3)} -pin  "ACC1:acc#416" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(4)} -pin  "ACC1:acc#416" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(5)} -pin  "ACC1:acc#416" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(6)} -pin  "ACC1:acc#416" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(7)} -pin  "ACC1:acc#416" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(8)} -pin  "ACC1:acc#416" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {regs.regs:slc(regs.regs(2))#11.itm(9)} -pin  "ACC1:acc#416" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#11.itm}
+load net {ACC1:acc#416.itm(0)} -pin  "ACC1:acc#416" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(1)} -pin  "ACC1:acc#416" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(2)} -pin  "ACC1:acc#416" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(3)} -pin  "ACC1:acc#416" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(4)} -pin  "ACC1:acc#416" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(5)} -pin  "ACC1:acc#416" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(6)} -pin  "ACC1:acc#416" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(7)} -pin  "ACC1:acc#416" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(8)} -pin  "ACC1:acc#416" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(9)} -pin  "ACC1:acc#416" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(10)} -pin  "ACC1:acc#416" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load inst "ACC1-3:acc#20" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 64513 -attr oid 1703 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#20} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#416.itm(0)} -pin  "ACC1-3:acc#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(1)} -pin  "ACC1-3:acc#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(2)} -pin  "ACC1-3:acc#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(3)} -pin  "ACC1-3:acc#20" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(4)} -pin  "ACC1-3:acc#20" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(5)} -pin  "ACC1-3:acc#20" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(6)} -pin  "ACC1-3:acc#20" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(7)} -pin  "ACC1-3:acc#20" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(8)} -pin  "ACC1-3:acc#20" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(9)} -pin  "ACC1-3:acc#20" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {ACC1:acc#416.itm(10)} -pin  "ACC1-3:acc#20" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#416.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(0)} -pin  "ACC1-3:acc#20" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(1)} -pin  "ACC1-3:acc#20" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(2)} -pin  "ACC1-3:acc#20" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(3)} -pin  "ACC1-3:acc#20" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(4)} -pin  "ACC1-3:acc#20" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(5)} -pin  "ACC1-3:acc#20" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(6)} -pin  "ACC1-3:acc#20" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(7)} -pin  "ACC1-3:acc#20" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(8)} -pin  "ACC1-3:acc#20" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {regs.regs:slc(regs.regs(2))#9.itm(9)} -pin  "ACC1-3:acc#20" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#9.itm}
+load net {acc#20.psp#1.sva(0)} -pin  "ACC1-3:acc#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(1)} -pin  "ACC1-3:acc#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(2)} -pin  "ACC1-3:acc#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(3)} -pin  "ACC1-3:acc#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(4)} -pin  "ACC1-3:acc#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(5)} -pin  "ACC1-3:acc#20" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(6)} -pin  "ACC1-3:acc#20" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1-3:acc#20" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(8)} -pin  "ACC1-3:acc#20" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1-3:acc#20" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1-3:acc#20" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1-3:acc#20" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#1.sva}
+load inst "ACC1:not#309" "not(10)" "INTERFACE" -attr xrf 64514 -attr oid 1704 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {reg(regs.regs(0).sva).cse(0)} -pin  "ACC1:not#309" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(1)} -pin  "ACC1:not#309" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(2)} -pin  "ACC1:not#309" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(3)} -pin  "ACC1:not#309" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(4)} -pin  "ACC1:not#309" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(5)} -pin  "ACC1:not#309" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(6)} -pin  "ACC1:not#309" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(7)} -pin  "ACC1:not#309" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(8)} -pin  "ACC1:not#309" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {reg(regs.regs(0).sva).cse(9)} -pin  "ACC1:not#309" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {ACC1:not#309.itm(0)} -pin  "ACC1:not#309" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(1)} -pin  "ACC1:not#309" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(2)} -pin  "ACC1:not#309" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(3)} -pin  "ACC1:not#309" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(4)} -pin  "ACC1:not#309" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(5)} -pin  "ACC1:not#309" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(6)} -pin  "ACC1:not#309" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(7)} -pin  "ACC1:not#309" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(8)} -pin  "ACC1:not#309" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(9)} -pin  "ACC1:not#309" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load inst "ACC1:not#310" "not(10)" "INTERFACE" -attr xrf 64515 -attr oid 1705 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {reg(regs.regs(0).sva).cse(10)} -pin  "ACC1:not#310" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(11)} -pin  "ACC1:not#310" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(12)} -pin  "ACC1:not#310" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(13)} -pin  "ACC1:not#310" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(14)} -pin  "ACC1:not#310" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(15)} -pin  "ACC1:not#310" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(16)} -pin  "ACC1:not#310" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(17)} -pin  "ACC1:not#310" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(18)} -pin  "ACC1:not#310" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {reg(regs.regs(0).sva).cse(19)} -pin  "ACC1:not#310" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {ACC1:not#310.itm(0)} -pin  "ACC1:not#310" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(1)} -pin  "ACC1:not#310" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(2)} -pin  "ACC1:not#310" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(3)} -pin  "ACC1:not#310" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(4)} -pin  "ACC1:not#310" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(5)} -pin  "ACC1:not#310" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(6)} -pin  "ACC1:not#310" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(7)} -pin  "ACC1:not#310" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(8)} -pin  "ACC1:not#310" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(9)} -pin  "ACC1:not#310" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load inst "ACC1:acc#370" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 64516 -attr oid 1706 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#309.itm(0)} -pin  "ACC1:acc#370" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(1)} -pin  "ACC1:acc#370" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(2)} -pin  "ACC1:acc#370" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(3)} -pin  "ACC1:acc#370" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(4)} -pin  "ACC1:acc#370" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(5)} -pin  "ACC1:acc#370" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(6)} -pin  "ACC1:acc#370" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(7)} -pin  "ACC1:acc#370" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(8)} -pin  "ACC1:acc#370" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#309.itm(9)} -pin  "ACC1:acc#370" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#309.itm}
+load net {ACC1:not#310.itm(0)} -pin  "ACC1:acc#370" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(1)} -pin  "ACC1:acc#370" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(2)} -pin  "ACC1:acc#370" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(3)} -pin  "ACC1:acc#370" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(4)} -pin  "ACC1:acc#370" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(5)} -pin  "ACC1:acc#370" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(6)} -pin  "ACC1:acc#370" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(7)} -pin  "ACC1:acc#370" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(8)} -pin  "ACC1:acc#370" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:not#310.itm(9)} -pin  "ACC1:acc#370" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#310.itm}
+load net {ACC1:acc#370.itm(0)} -pin  "ACC1:acc#370" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(1)} -pin  "ACC1:acc#370" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(2)} -pin  "ACC1:acc#370" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(3)} -pin  "ACC1:acc#370" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(4)} -pin  "ACC1:acc#370" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(5)} -pin  "ACC1:acc#370" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(6)} -pin  "ACC1:acc#370" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(7)} -pin  "ACC1:acc#370" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(8)} -pin  "ACC1:acc#370" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(9)} -pin  "ACC1:acc#370" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(10)} -pin  "ACC1:acc#370" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load inst "ACC1:not#311" "not(10)" "INTERFACE" -attr xrf 64517 -attr oid 1707 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {reg(regs.regs(0).sva).cse(20)} -pin  "ACC1:not#311" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(21)} -pin  "ACC1:not#311" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(22)} -pin  "ACC1:not#311" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(23)} -pin  "ACC1:not#311" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(24)} -pin  "ACC1:not#311" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(25)} -pin  "ACC1:not#311" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(26)} -pin  "ACC1:not#311" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(27)} -pin  "ACC1:not#311" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(28)} -pin  "ACC1:not#311" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {reg(regs.regs(0).sva).cse(29)} -pin  "ACC1:not#311" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {ACC1:not#311.itm(0)} -pin  "ACC1:not#311" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(1)} -pin  "ACC1:not#311" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(2)} -pin  "ACC1:not#311" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(3)} -pin  "ACC1:not#311" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(4)} -pin  "ACC1:not#311" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(5)} -pin  "ACC1:not#311" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(6)} -pin  "ACC1:not#311" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(7)} -pin  "ACC1:not#311" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(8)} -pin  "ACC1:not#311" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(9)} -pin  "ACC1:not#311" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load inst "ACC1:acc#369" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 64518 -attr oid 1708 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#311.itm(0)} -pin  "ACC1:acc#369" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(1)} -pin  "ACC1:acc#369" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(2)} -pin  "ACC1:acc#369" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(3)} -pin  "ACC1:acc#369" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(4)} -pin  "ACC1:acc#369" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(5)} -pin  "ACC1:acc#369" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(6)} -pin  "ACC1:acc#369" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(7)} -pin  "ACC1:acc#369" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(8)} -pin  "ACC1:acc#369" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {ACC1:not#311.itm(9)} -pin  "ACC1:acc#369" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#311.itm}
+load net {PWR} -pin  "ACC1:acc#369" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#369" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#369.itm(0)} -pin  "ACC1:acc#369" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(1)} -pin  "ACC1:acc#369" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(2)} -pin  "ACC1:acc#369" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(3)} -pin  "ACC1:acc#369" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(4)} -pin  "ACC1:acc#369" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(5)} -pin  "ACC1:acc#369" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(6)} -pin  "ACC1:acc#369" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(7)} -pin  "ACC1:acc#369" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(8)} -pin  "ACC1:acc#369" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(9)} -pin  "ACC1:acc#369" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(10)} -pin  "ACC1:acc#369" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load inst "ACC1:acc#228" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 64519 -attr oid 1709 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#370.itm(0)} -pin  "ACC1:acc#228" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(1)} -pin  "ACC1:acc#228" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(2)} -pin  "ACC1:acc#228" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(3)} -pin  "ACC1:acc#228" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(4)} -pin  "ACC1:acc#228" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(5)} -pin  "ACC1:acc#228" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(6)} -pin  "ACC1:acc#228" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(7)} -pin  "ACC1:acc#228" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(8)} -pin  "ACC1:acc#228" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(9)} -pin  "ACC1:acc#228" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#370.itm(10)} -pin  "ACC1:acc#228" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#370.itm}
+load net {ACC1:acc#369.itm(0)} -pin  "ACC1:acc#228" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(1)} -pin  "ACC1:acc#228" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(2)} -pin  "ACC1:acc#228" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(3)} -pin  "ACC1:acc#228" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(4)} -pin  "ACC1:acc#228" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(5)} -pin  "ACC1:acc#228" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(6)} -pin  "ACC1:acc#228" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(7)} -pin  "ACC1:acc#228" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(8)} -pin  "ACC1:acc#228" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(9)} -pin  "ACC1:acc#228" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#369.itm(10)} -pin  "ACC1:acc#228" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#369.itm}
+load net {ACC1:acc#228.psp.sva(0)} -pin  "ACC1:acc#228" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(1)} -pin  "ACC1:acc#228" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(2)} -pin  "ACC1:acc#228" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(3)} -pin  "ACC1:acc#228" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(4)} -pin  "ACC1:acc#228" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(5)} -pin  "ACC1:acc#228" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(6)} -pin  "ACC1:acc#228" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(7)} -pin  "ACC1:acc#228" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(8)} -pin  "ACC1:acc#228" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(9)} -pin  "ACC1:acc#228" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(10)} -pin  "ACC1:acc#228" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#228" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.psp.sva}
+load inst "ACC1:acc#360" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 64520 -attr oid 1710 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "ACC1:acc#360" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "ACC1:acc#360" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "ACC1:acc#360" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "ACC1:acc#360" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "ACC1:acc#360" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "ACC1:acc#360" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "ACC1:acc#360" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "ACC1:acc#360" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "ACC1:acc#360" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:acc#360" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "ACC1:acc#360" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "ACC1:acc#360" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "ACC1:acc#360" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "ACC1:acc#360" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "ACC1:acc#360" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "ACC1:acc#360" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "ACC1:acc#360" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "ACC1:acc#360" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "ACC1:acc#360" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:acc#360" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {ACC1:acc#360.itm(0)} -pin  "ACC1:acc#360" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(1)} -pin  "ACC1:acc#360" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(2)} -pin  "ACC1:acc#360" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(3)} -pin  "ACC1:acc#360" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(4)} -pin  "ACC1:acc#360" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(5)} -pin  "ACC1:acc#360" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(6)} -pin  "ACC1:acc#360" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(7)} -pin  "ACC1:acc#360" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(8)} -pin  "ACC1:acc#360" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(9)} -pin  "ACC1:acc#360" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(10)} -pin  "ACC1:acc#360" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load inst "ACC1-1:acc#25" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 64521 -attr oid 1711 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#360.itm(0)} -pin  "ACC1-1:acc#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(1)} -pin  "ACC1-1:acc#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(2)} -pin  "ACC1-1:acc#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(3)} -pin  "ACC1-1:acc#25" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(4)} -pin  "ACC1-1:acc#25" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(5)} -pin  "ACC1-1:acc#25" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(6)} -pin  "ACC1-1:acc#25" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(7)} -pin  "ACC1-1:acc#25" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(8)} -pin  "ACC1-1:acc#25" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(9)} -pin  "ACC1-1:acc#25" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {ACC1:acc#360.itm(10)} -pin  "ACC1-1:acc#25" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#360.itm}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "ACC1-1:acc#25" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "ACC1-1:acc#25" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "ACC1-1:acc#25" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "ACC1-1:acc#25" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "ACC1-1:acc#25" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "ACC1-1:acc#25" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "ACC1-1:acc#25" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "ACC1-1:acc#25" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "ACC1-1:acc#25" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1-1:acc#25" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {ACC1-1:acc#25.psp.sva(0)} -pin  "ACC1-1:acc#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(1)} -pin  "ACC1-1:acc#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(2)} -pin  "ACC1-1:acc#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(3)} -pin  "ACC1-1:acc#25" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(4)} -pin  "ACC1-1:acc#25" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(5)} -pin  "ACC1-1:acc#25" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(6)} -pin  "ACC1-1:acc#25" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(7)} -pin  "ACC1-1:acc#25" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(8)} -pin  "ACC1-1:acc#25" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(9)} -pin  "ACC1-1:acc#25" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(10)} -pin  "ACC1-1:acc#25" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1-1:acc#25" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#25.psp.sva}
+load inst "ACC1:acc#509" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64522 -attr oid 1712 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#509" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1059.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#509" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1059.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#509" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1047.itm}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#509" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1047.itm}
+load net {ACC1:acc#509.cse(0)} -pin  "ACC1:acc#509" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(1)} -pin  "ACC1:acc#509" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load net {ACC1:acc#509.cse(2)} -pin  "ACC1:acc#509" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#509.cse}
+load inst "regs.operator[]:not#5" "not(10)" "INTERFACE" -attr xrf 64523 -attr oid 1713 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs:slc(regs.regs(2)).itm(0)} -pin  "regs.operator[]:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(1)} -pin  "regs.operator[]:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(2)} -pin  "regs.operator[]:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(3)} -pin  "regs.operator[]:not#5" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(4)} -pin  "regs.operator[]:not#5" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(5)} -pin  "regs.operator[]:not#5" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(6)} -pin  "regs.operator[]:not#5" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(7)} -pin  "regs.operator[]:not#5" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(8)} -pin  "regs.operator[]:not#5" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(9)} -pin  "regs.operator[]:not#5" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.operator[]:not#5.itm(0)} -pin  "regs.operator[]:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(1)} -pin  "regs.operator[]:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(2)} -pin  "regs.operator[]:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(3)} -pin  "regs.operator[]:not#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(4)} -pin  "regs.operator[]:not#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(5)} -pin  "regs.operator[]:not#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(6)} -pin  "regs.operator[]:not#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(7)} -pin  "regs.operator[]:not#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(8)} -pin  "regs.operator[]:not#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(9)} -pin  "regs.operator[]:not#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load inst "regs.operator[]#1:not#5" "not(10)" "INTERFACE" -attr xrf 64524 -attr oid 1714 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs:slc(regs.regs(2))#1.itm(0)} -pin  "regs.operator[]#1:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(1)} -pin  "regs.operator[]#1:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(2)} -pin  "regs.operator[]#1:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(3)} -pin  "regs.operator[]#1:not#5" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(4)} -pin  "regs.operator[]#1:not#5" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(5)} -pin  "regs.operator[]#1:not#5" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(6)} -pin  "regs.operator[]#1:not#5" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(7)} -pin  "regs.operator[]#1:not#5" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(8)} -pin  "regs.operator[]#1:not#5" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(9)} -pin  "regs.operator[]#1:not#5" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.operator[]#1:not#5.itm(0)} -pin  "regs.operator[]#1:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(1)} -pin  "regs.operator[]#1:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(2)} -pin  "regs.operator[]#1:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(3)} -pin  "regs.operator[]#1:not#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(4)} -pin  "regs.operator[]#1:not#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(5)} -pin  "regs.operator[]#1:not#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(6)} -pin  "regs.operator[]#1:not#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(7)} -pin  "regs.operator[]#1:not#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(8)} -pin  "regs.operator[]#1:not#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(9)} -pin  "regs.operator[]#1:not#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load inst "ACC1:acc#398" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 64525 -attr oid 1715 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.operator[]:not#5.itm(0)} -pin  "ACC1:acc#398" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(1)} -pin  "ACC1:acc#398" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(2)} -pin  "ACC1:acc#398" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(3)} -pin  "ACC1:acc#398" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(4)} -pin  "ACC1:acc#398" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(5)} -pin  "ACC1:acc#398" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(6)} -pin  "ACC1:acc#398" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(7)} -pin  "ACC1:acc#398" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(8)} -pin  "ACC1:acc#398" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]:not#5.itm(9)} -pin  "ACC1:acc#398" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(0)} -pin  "ACC1:acc#398" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(1)} -pin  "ACC1:acc#398" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(2)} -pin  "ACC1:acc#398" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(3)} -pin  "ACC1:acc#398" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(4)} -pin  "ACC1:acc#398" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(5)} -pin  "ACC1:acc#398" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(6)} -pin  "ACC1:acc#398" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(7)} -pin  "ACC1:acc#398" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(8)} -pin  "ACC1:acc#398" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {regs.operator[]#1:not#5.itm(9)} -pin  "ACC1:acc#398" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not#5.itm}
+load net {ACC1:acc#398.itm(0)} -pin  "ACC1:acc#398" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(1)} -pin  "ACC1:acc#398" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(2)} -pin  "ACC1:acc#398" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(3)} -pin  "ACC1:acc#398" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(4)} -pin  "ACC1:acc#398" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(5)} -pin  "ACC1:acc#398" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(6)} -pin  "ACC1:acc#398" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(7)} -pin  "ACC1:acc#398" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(8)} -pin  "ACC1:acc#398" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(9)} -pin  "ACC1:acc#398" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(10)} -pin  "ACC1:acc#398" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load inst "regs.operator[]#2:not#5" "not(10)" "INTERFACE" -attr xrf 64526 -attr oid 1716 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs:slc(regs.regs(2))#2.itm(0)} -pin  "regs.operator[]#2:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(1)} -pin  "regs.operator[]#2:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(2)} -pin  "regs.operator[]#2:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(3)} -pin  "regs.operator[]#2:not#5" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(4)} -pin  "regs.operator[]#2:not#5" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(5)} -pin  "regs.operator[]#2:not#5" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(6)} -pin  "regs.operator[]#2:not#5" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(7)} -pin  "regs.operator[]#2:not#5" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(8)} -pin  "regs.operator[]#2:not#5" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(9)} -pin  "regs.operator[]#2:not#5" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.operator[]#2:not#5.itm(0)} -pin  "regs.operator[]#2:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(1)} -pin  "regs.operator[]#2:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(2)} -pin  "regs.operator[]#2:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(3)} -pin  "regs.operator[]#2:not#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(4)} -pin  "regs.operator[]#2:not#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(5)} -pin  "regs.operator[]#2:not#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(6)} -pin  "regs.operator[]#2:not#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(7)} -pin  "regs.operator[]#2:not#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(8)} -pin  "regs.operator[]#2:not#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(9)} -pin  "regs.operator[]#2:not#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load inst "ACC1:acc#397" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 64527 -attr oid 1717 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.operator[]#2:not#5.itm(0)} -pin  "ACC1:acc#397" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(1)} -pin  "ACC1:acc#397" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(2)} -pin  "ACC1:acc#397" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(3)} -pin  "ACC1:acc#397" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(4)} -pin  "ACC1:acc#397" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(5)} -pin  "ACC1:acc#397" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(6)} -pin  "ACC1:acc#397" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(7)} -pin  "ACC1:acc#397" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(8)} -pin  "ACC1:acc#397" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {regs.operator[]#2:not#5.itm(9)} -pin  "ACC1:acc#397" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not#5.itm}
+load net {PWR} -pin  "ACC1:acc#397" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#397" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#397.itm(0)} -pin  "ACC1:acc#397" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(1)} -pin  "ACC1:acc#397" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(2)} -pin  "ACC1:acc#397" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(3)} -pin  "ACC1:acc#397" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(4)} -pin  "ACC1:acc#397" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(5)} -pin  "ACC1:acc#397" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(6)} -pin  "ACC1:acc#397" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(7)} -pin  "ACC1:acc#397" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(8)} -pin  "ACC1:acc#397" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(9)} -pin  "ACC1:acc#397" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(10)} -pin  "ACC1:acc#397" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load inst "ACC1:acc#227" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 64528 -attr oid 1718 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#398.itm(0)} -pin  "ACC1:acc#227" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(1)} -pin  "ACC1:acc#227" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(2)} -pin  "ACC1:acc#227" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(3)} -pin  "ACC1:acc#227" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(4)} -pin  "ACC1:acc#227" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(5)} -pin  "ACC1:acc#227" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(6)} -pin  "ACC1:acc#227" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(7)} -pin  "ACC1:acc#227" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(8)} -pin  "ACC1:acc#227" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(9)} -pin  "ACC1:acc#227" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#398.itm(10)} -pin  "ACC1:acc#227" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#398.itm}
+load net {ACC1:acc#397.itm(0)} -pin  "ACC1:acc#227" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(1)} -pin  "ACC1:acc#227" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(2)} -pin  "ACC1:acc#227" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(3)} -pin  "ACC1:acc#227" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(4)} -pin  "ACC1:acc#227" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(5)} -pin  "ACC1:acc#227" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(6)} -pin  "ACC1:acc#227" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(7)} -pin  "ACC1:acc#227" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(8)} -pin  "ACC1:acc#227" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(9)} -pin  "ACC1:acc#227" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#397.itm(10)} -pin  "ACC1:acc#227" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#397.itm}
+load net {ACC1:acc#227.psp.sva(0)} -pin  "ACC1:acc#227" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(1)} -pin  "ACC1:acc#227" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(2)} -pin  "ACC1:acc#227" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(3)} -pin  "ACC1:acc#227" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(4)} -pin  "ACC1:acc#227" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(5)} -pin  "ACC1:acc#227" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(6)} -pin  "ACC1:acc#227" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(7)} -pin  "ACC1:acc#227" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(8)} -pin  "ACC1:acc#227" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(9)} -pin  "ACC1:acc#227" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(10)} -pin  "ACC1:acc#227" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1:acc#227" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.psp.sva}
+load inst "ACC1:acc#506" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64529 -attr oid 1719 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#506" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1056.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#506" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1056.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#506" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1043.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#506" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1043.itm}
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#506" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#506" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#506" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load inst "ACC1:acc#562" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64530 -attr oid 1720 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#562" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#562" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#562" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(0)} -pin  "ACC1:acc#562" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(1)} -pin  "ACC1:acc#562" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#506.cse(2)} -pin  "ACC1:acc#562" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#506.cse}
+load net {ACC1:acc#562.ncse(0)} -pin  "ACC1:acc#562" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(1)} -pin  "ACC1:acc#562" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(2)} -pin  "ACC1:acc#562" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load net {ACC1:acc#562.ncse(3)} -pin  "ACC1:acc#562" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#562.ncse}
+load inst "ACC1:acc#502" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64531 -attr oid 1721 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#20.psp#1.sva(5)} -pin  "ACC1:acc#502" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#963.itm}
+load net {acc#20.psp#1.sva(5)} -pin  "ACC1:acc#502" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#963.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#502" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1055.itm}
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1:acc#502" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1055.itm}
+load net {ACC1:acc#502.cse(0)} -pin  "ACC1:acc#502" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#502.cse(1)} -pin  "ACC1:acc#502" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load net {ACC1:acc#502.cse(2)} -pin  "ACC1:acc#502" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#502.cse}
+load inst "ACC1:acc#489" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64532 -attr oid 1722 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#489" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1059.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#489" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1059.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#489" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1047.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#489" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1047.itm}
+load net {ACC1:acc#489.cse(0)} -pin  "ACC1:acc#489" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(1)} -pin  "ACC1:acc#489" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(2)} -pin  "ACC1:acc#489" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load inst "ACC1:acc#379" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 64533 -attr oid 1723 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {reg(regs.regs(0).sva).cse(70)} -pin  "ACC1:acc#379" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(71)} -pin  "ACC1:acc#379" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(72)} -pin  "ACC1:acc#379" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(73)} -pin  "ACC1:acc#379" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(74)} -pin  "ACC1:acc#379" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(75)} -pin  "ACC1:acc#379" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(76)} -pin  "ACC1:acc#379" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(77)} -pin  "ACC1:acc#379" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(78)} -pin  "ACC1:acc#379" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(79)} -pin  "ACC1:acc#379" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {reg(regs.regs(0).sva).cse(60)} -pin  "ACC1:acc#379" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(61)} -pin  "ACC1:acc#379" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(62)} -pin  "ACC1:acc#379" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(63)} -pin  "ACC1:acc#379" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(64)} -pin  "ACC1:acc#379" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(65)} -pin  "ACC1:acc#379" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(66)} -pin  "ACC1:acc#379" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(67)} -pin  "ACC1:acc#379" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(68)} -pin  "ACC1:acc#379" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {reg(regs.regs(0).sva).cse(69)} -pin  "ACC1:acc#379" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {ACC1:acc#379.itm(0)} -pin  "ACC1:acc#379" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(1)} -pin  "ACC1:acc#379" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(2)} -pin  "ACC1:acc#379" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(3)} -pin  "ACC1:acc#379" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(4)} -pin  "ACC1:acc#379" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(5)} -pin  "ACC1:acc#379" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(6)} -pin  "ACC1:acc#379" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(7)} -pin  "ACC1:acc#379" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(8)} -pin  "ACC1:acc#379" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(9)} -pin  "ACC1:acc#379" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(10)} -pin  "ACC1:acc#379" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load inst "ACC1:acc#226" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 64534 -attr oid 1724 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#379.itm(0)} -pin  "ACC1:acc#226" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(1)} -pin  "ACC1:acc#226" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(2)} -pin  "ACC1:acc#226" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(3)} -pin  "ACC1:acc#226" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(4)} -pin  "ACC1:acc#226" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(5)} -pin  "ACC1:acc#226" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(6)} -pin  "ACC1:acc#226" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(7)} -pin  "ACC1:acc#226" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(8)} -pin  "ACC1:acc#226" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(9)} -pin  "ACC1:acc#226" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {ACC1:acc#379.itm(10)} -pin  "ACC1:acc#226" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#379.itm}
+load net {reg(regs.regs(0).sva).cse(80)} -pin  "ACC1:acc#226" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(81)} -pin  "ACC1:acc#226" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(82)} -pin  "ACC1:acc#226" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(83)} -pin  "ACC1:acc#226" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(84)} -pin  "ACC1:acc#226" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(85)} -pin  "ACC1:acc#226" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(86)} -pin  "ACC1:acc#226" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(87)} -pin  "ACC1:acc#226" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(88)} -pin  "ACC1:acc#226" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {reg(regs.regs(0).sva).cse(89)} -pin  "ACC1:acc#226" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {ACC1:acc#226.psp.sva(0)} -pin  "ACC1:acc#226" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(1)} -pin  "ACC1:acc#226" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(2)} -pin  "ACC1:acc#226" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(3)} -pin  "ACC1:acc#226" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(4)} -pin  "ACC1:acc#226" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(5)} -pin  "ACC1:acc#226" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(6)} -pin  "ACC1:acc#226" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(7)} -pin  "ACC1:acc#226" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(8)} -pin  "ACC1:acc#226" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(9)} -pin  "ACC1:acc#226" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(10)} -pin  "ACC1:acc#226" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1:acc#226" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.psp.sva}
+load inst "ACC1:acc#553" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64535 -attr oid 1725 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#489.cse(0)} -pin  "ACC1:acc#553" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(1)} -pin  "ACC1:acc#553" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(2)} -pin  "ACC1:acc#553" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(0)} -pin  "ACC1:acc#553" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(1)} -pin  "ACC1:acc#553" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#489.cse(2)} -pin  "ACC1:acc#553" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#489.cse}
+load net {ACC1:acc#553.ncse(0)} -pin  "ACC1:acc#553" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(1)} -pin  "ACC1:acc#553" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(2)} -pin  "ACC1:acc#553" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load net {ACC1:acc#553.ncse(3)} -pin  "ACC1:acc#553" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#553.ncse}
+load inst "ACC1-1:not#60" "not(1)" "INTERFACE" -attr xrf 64536 -attr oid 1726 -attr @path {/sobel/sobel:core/ACC1-1:not#60} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#339.itm(2)} -pin  "ACC1-1:not#60" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#32.sva)#2.itm}
+load net {ACC1-1:not#60.itm} -pin  "ACC1-1:not#60" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#60.itm}
+load inst "ACC1-1:and#3" "and(3,1)" "INTERFACE" -attr xrf 64537 -attr oid 1727 -attr @path {/sobel/sobel:core/ACC1-1:and#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#50.itm}
+load net {ACC1-1:not#60.itm} -pin  "ACC1-1:and#3" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#60.itm}
+load net {ACC1:acc#339.itm(1)} -pin  "ACC1-1:and#3" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#32.sva)#1.itm}
+load net {ACC1-1:and#3.cse.sva} -pin  "ACC1-1:and#3" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#3.cse.sva}
+load inst "ACC1-1:not#319" "not(1)" "INTERFACE" -attr xrf 64538 -attr oid 1728 -attr @path {/sobel/sobel:core/ACC1-1:not#319} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:not#319" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#71.itm}
+load net {ACC1-1:not#319.itm} -pin  "ACC1-1:not#319" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#319.itm}
+load inst "ACC1-1:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 64539 -attr oid 1729 -attr vt c -attr @path {/sobel/sobel:core/ACC1-1:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#339.itm(2)} -pin  "ACC1-1:nand#1" {A0(0)} -attr vt c -attr @path {/sobel/sobel:core/slc(acc.imod#32.sva).itm}
+load net {ACC1-1:not#319.itm} -pin  "ACC1-1:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#319.itm}
+load net {ACC1-1:nand#1.cse.sva} -pin  "ACC1-1:nand#1" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/ACC1-1:nand#1.cse.sva}
+load inst "ACC1:acc#388" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 64540 -attr oid 1730 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.regs:slc(regs.regs(2))#1.itm(0)} -pin  "ACC1:acc#388" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(1)} -pin  "ACC1:acc#388" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(2)} -pin  "ACC1:acc#388" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(3)} -pin  "ACC1:acc#388" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(4)} -pin  "ACC1:acc#388" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(5)} -pin  "ACC1:acc#388" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(6)} -pin  "ACC1:acc#388" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(7)} -pin  "ACC1:acc#388" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(8)} -pin  "ACC1:acc#388" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#1.itm(9)} -pin  "ACC1:acc#388" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#1.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(0)} -pin  "ACC1:acc#388" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(1)} -pin  "ACC1:acc#388" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(2)} -pin  "ACC1:acc#388" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(3)} -pin  "ACC1:acc#388" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(4)} -pin  "ACC1:acc#388" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(5)} -pin  "ACC1:acc#388" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(6)} -pin  "ACC1:acc#388" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(7)} -pin  "ACC1:acc#388" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(8)} -pin  "ACC1:acc#388" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {regs.regs:slc(regs.regs(2))#2.itm(9)} -pin  "ACC1:acc#388" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#2.itm}
+load net {ACC1:acc#388.itm(0)} -pin  "ACC1:acc#388" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(1)} -pin  "ACC1:acc#388" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(2)} -pin  "ACC1:acc#388" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(3)} -pin  "ACC1:acc#388" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(4)} -pin  "ACC1:acc#388" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(5)} -pin  "ACC1:acc#388" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(6)} -pin  "ACC1:acc#388" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(7)} -pin  "ACC1:acc#388" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(8)} -pin  "ACC1:acc#388" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(9)} -pin  "ACC1:acc#388" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(10)} -pin  "ACC1:acc#388" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load inst "ACC1-3:acc" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 64541 -attr oid 1731 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#388.itm(0)} -pin  "ACC1-3:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(1)} -pin  "ACC1-3:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(2)} -pin  "ACC1-3:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(3)} -pin  "ACC1-3:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(4)} -pin  "ACC1-3:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(5)} -pin  "ACC1-3:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(6)} -pin  "ACC1-3:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(7)} -pin  "ACC1-3:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(8)} -pin  "ACC1-3:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(9)} -pin  "ACC1-3:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {ACC1:acc#388.itm(10)} -pin  "ACC1-3:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#388.itm}
+load net {regs.regs:slc(regs.regs(2)).itm(0)} -pin  "ACC1-3:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(1)} -pin  "ACC1-3:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(2)} -pin  "ACC1-3:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(3)} -pin  "ACC1-3:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(4)} -pin  "ACC1-3:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(5)} -pin  "ACC1-3:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(6)} -pin  "ACC1-3:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(7)} -pin  "ACC1-3:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(8)} -pin  "ACC1-3:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(9)} -pin  "ACC1-3:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {acc.psp#1.sva(0)} -pin  "ACC1-3:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(1)} -pin  "ACC1-3:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(2)} -pin  "ACC1-3:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(3)} -pin  "ACC1-3:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(4)} -pin  "ACC1-3:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(5)} -pin  "ACC1-3:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(6)} -pin  "ACC1-3:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(7)} -pin  "ACC1-3:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(8)} -pin  "ACC1-3:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(9)} -pin  "ACC1-3:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(10)} -pin  "ACC1-3:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load inst "ACC1-1:not#293" "not(2)" "INTERFACE" -attr xrf 64542 -attr oid 1732 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:not#293} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#220.psp#1.sva(1)} -pin  "ACC1-1:not#293" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva).itm}
+load net {ACC1:acc#220.psp#1.sva(2)} -pin  "ACC1-1:not#293" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp#1.sva).itm}
+load net {ACC1-1:not#293.itm(0)} -pin  "ACC1-1:not#293" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:not#293.itm}
+load net {ACC1-1:not#293.itm(1)} -pin  "ACC1-1:not#293" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:not#293.itm}
+load inst "ACC1:acc#338" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 64543 -attr oid 1733 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#338} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#338" {A(0)} -attr @path {/sobel/sobel:core/conc#1004.itm}
+load net {ACC1-1:not#293.itm(0)} -pin  "ACC1:acc#338" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1004.itm}
+load net {ACC1-1:not#293.itm(1)} -pin  "ACC1:acc#338" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1004.itm}
+load net {PWR} -pin  "ACC1:acc#338" {B(0)} -attr @path {/sobel/sobel:core/conc#1005.itm}
+load net {ACC1:acc#220.psp#1.sva(0)} -pin  "ACC1:acc#338" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1005.itm}
+load net {ACC1:acc#338.itm(0)} -pin  "ACC1:acc#338" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(1)} -pin  "ACC1:acc#338" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(2)} -pin  "ACC1:acc#338" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(3)} -pin  "ACC1:acc#338" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load inst "ACC1-1:not#311" "not(1)" "INTERFACE" -attr xrf 64544 -attr oid 1734 -attr @path {/sobel/sobel:core/ACC1-1:not#311} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:not#311" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#51.itm}
+load net {ACC1-1:not#311.itm} -pin  "ACC1-1:not#311" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#311.itm}
+load inst "ACC1-1:not#229" "not(1)" "INTERFACE" -attr xrf 64545 -attr oid 1735 -attr @path {/sobel/sobel:core/ACC1-1:not#229} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(1)} -pin  "ACC1-1:not#229" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#17.itm}
+load net {ACC1-1:not#229.itm} -pin  "ACC1-1:not#229" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#229.itm}
+load inst "ACC1:acc#334" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 64546 -attr oid 1736 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#334" {A(0)} -attr @path {/sobel/sobel:core/conc#1007.itm}
+load net {ACC1-1:not#311.itm} -pin  "ACC1:acc#334" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1007.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#334" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1133.itm}
+load net {ACC1-1:not#229.itm} -pin  "ACC1:acc#334" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1133.itm}
+load net {ACC1:acc#334.itm(0)} -pin  "ACC1:acc#334" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(1)} -pin  "ACC1:acc#334" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(2)} -pin  "ACC1:acc#334" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(3)} -pin  "ACC1:acc#334" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load inst "ACC1:acc#336" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 64547 -attr oid 1737 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#336" {A(0)} -attr @path {/sobel/sobel:core/conc#1006.itm}
+load net {ACC1:acc#334.itm(1)} -pin  "ACC1:acc#336" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1006.itm}
+load net {ACC1:acc#334.itm(2)} -pin  "ACC1:acc#336" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1006.itm}
+load net {ACC1:acc#334.itm(3)} -pin  "ACC1:acc#336" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1006.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#336" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1008.itm}
+load net {acc.psp#2.sva(0)} -pin  "ACC1:acc#336" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1008.itm}
+load net {GND} -pin  "ACC1:acc#336" {B(2)} -attr @path {/sobel/sobel:core/conc#1008.itm}
+load net {PWR} -pin  "ACC1:acc#336" {B(3)} -attr @path {/sobel/sobel:core/conc#1008.itm}
+load net {ACC1:acc#336.itm(0)} -pin  "ACC1:acc#336" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(1)} -pin  "ACC1:acc#336" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(2)} -pin  "ACC1:acc#336" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(3)} -pin  "ACC1:acc#336" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(4)} -pin  "ACC1:acc#336" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load inst "ACC1-1:not#230" "not(1)" "INTERFACE" -attr xrf 64548 -attr oid 1738 -attr @path {/sobel/sobel:core/ACC1-1:not#230} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(3)} -pin  "ACC1-1:not#230" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#16.itm}
+load net {ACC1-1:not#230.itm} -pin  "ACC1-1:not#230" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#230.itm}
+load inst "ACC1-1:not#232" "not(1)" "INTERFACE" -attr xrf 64549 -attr oid 1739 -attr @path {/sobel/sobel:core/ACC1-1:not#232} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(7)} -pin  "ACC1-1:not#232" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#6.itm}
+load net {ACC1-1:not#232.itm} -pin  "ACC1-1:not#232" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#232.itm}
+load inst "ACC1:acc#333" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64550 -attr oid 1740 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#333} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#333" {A(0)} -attr @path {/sobel/sobel:core/conc#1010.itm}
+load net {acc.psp#2.sva(2)} -pin  "ACC1:acc#333" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1010.itm}
+load net {ACC1-1:not#232.itm} -pin  "ACC1:acc#333" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1131.itm}
+load net {ACC1-1:not#230.itm} -pin  "ACC1:acc#333" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1131.itm}
+load net {ACC1:acc#333.itm(0)} -pin  "ACC1:acc#333" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(1)} -pin  "ACC1:acc#333" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(2)} -pin  "ACC1:acc#333" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load inst "ACC1-1:not#231" "not(1)" "INTERFACE" -attr xrf 64551 -attr oid 1741 -attr @path {/sobel/sobel:core/ACC1-1:not#231} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(5)} -pin  "ACC1-1:not#231" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#8.itm}
+load net {ACC1-1:not#231.itm} -pin  "ACC1-1:not#231" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#231.itm}
+load inst "ACC1:acc#332" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64552 -attr oid 1742 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#332" {A(0)} -attr @path {/sobel/sobel:core/conc#1011.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#332" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1011.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#332" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1129.itm}
+load net {ACC1-1:not#231.itm} -pin  "ACC1:acc#332" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1129.itm}
+load net {ACC1:acc#332.itm(0)} -pin  "ACC1:acc#332" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(1)} -pin  "ACC1:acc#332" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(2)} -pin  "ACC1:acc#332" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load inst "ACC1-1:not#233" "not(1)" "INTERFACE" -attr xrf 64553 -attr oid 1743 -attr @path {/sobel/sobel:core/ACC1-1:not#233} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(9)} -pin  "ACC1-1:not#233" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#93.itm}
+load net {ACC1-1:not#233.itm} -pin  "ACC1-1:not#233" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#233.itm}
+load inst "ACC1:acc#335" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64554 -attr oid 1744 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#335} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#335" {A(0)} -attr @path {/sobel/sobel:core/conc#1009.itm}
+load net {ACC1:acc#333.itm(1)} -pin  "ACC1:acc#335" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1009.itm}
+load net {ACC1:acc#333.itm(2)} -pin  "ACC1:acc#335" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1009.itm}
+load net {ACC1-1:not#233.itm} -pin  "ACC1:acc#335" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1135.itm}
+load net {ACC1:acc#332.itm(1)} -pin  "ACC1:acc#335" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1135.itm}
+load net {ACC1:acc#332.itm(2)} -pin  "ACC1:acc#335" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1135.itm}
+load net {ACC1:acc#335.itm(0)} -pin  "ACC1:acc#335" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(1)} -pin  "ACC1:acc#335" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(2)} -pin  "ACC1:acc#335" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(3)} -pin  "ACC1:acc#335" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load inst "ACC1-1:acc#210" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 64555 -attr oid 1745 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#210} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#336.itm(1)} -pin  "ACC1-1:acc#210" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#17.itm}
+load net {ACC1:acc#336.itm(2)} -pin  "ACC1-1:acc#210" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#17.itm}
+load net {ACC1:acc#336.itm(3)} -pin  "ACC1-1:acc#210" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#17.itm}
+load net {ACC1:acc#336.itm(4)} -pin  "ACC1-1:acc#210" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#17.itm}
+load net {ACC1:acc#335.itm(1)} -pin  "ACC1-1:acc#210" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#16.itm}
+load net {ACC1:acc#335.itm(2)} -pin  "ACC1-1:acc#210" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#16.itm}
+load net {ACC1:acc#335.itm(3)} -pin  "ACC1-1:acc#210" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#16.itm}
+load net {ACC1:acc#210.psp#2.sva(0)} -pin  "ACC1-1:acc#210" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#2.sva}
+load net {ACC1:acc#210.psp#2.sva(1)} -pin  "ACC1-1:acc#210" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#2.sva}
+load net {ACC1:acc#210.psp#2.sva(2)} -pin  "ACC1-1:acc#210" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#2.sva}
+load net {ACC1:acc#210.psp#2.sva(3)} -pin  "ACC1-1:acc#210" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#2.sva}
+load inst "regs.operator[]:not" "not(10)" "INTERFACE" -attr xrf 64556 -attr oid 1746 -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "regs.operator[]:not" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "regs.operator[]:not" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "regs.operator[]:not" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "regs.operator[]:not" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "regs.operator[]:not" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "regs.operator[]:not" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "regs.operator[]:not" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "regs.operator[]:not" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "regs.operator[]:not" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "regs.operator[]:not" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {regs.operator[]:not.itm(0)} -pin  "regs.operator[]:not" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(1)} -pin  "regs.operator[]:not" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(2)} -pin  "regs.operator[]:not" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(3)} -pin  "regs.operator[]:not" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(4)} -pin  "regs.operator[]:not" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(5)} -pin  "regs.operator[]:not" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(6)} -pin  "regs.operator[]:not" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(7)} -pin  "regs.operator[]:not" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(8)} -pin  "regs.operator[]:not" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(9)} -pin  "regs.operator[]:not" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load inst "regs.operator[]#1:not" "not(10)" "INTERFACE" -attr xrf 64557 -attr oid 1747 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "regs.operator[]#1:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "regs.operator[]#1:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "regs.operator[]#1:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "regs.operator[]#1:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "regs.operator[]#1:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "regs.operator[]#1:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "regs.operator[]#1:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "regs.operator[]#1:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "regs.operator[]#1:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "regs.operator[]#1:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {regs.operator[]#1:not.itm(0)} -pin  "regs.operator[]#1:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(1)} -pin  "regs.operator[]#1:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(2)} -pin  "regs.operator[]#1:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(3)} -pin  "regs.operator[]#1:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(4)} -pin  "regs.operator[]#1:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(5)} -pin  "regs.operator[]#1:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(6)} -pin  "regs.operator[]#1:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(7)} -pin  "regs.operator[]#1:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(8)} -pin  "regs.operator[]#1:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(9)} -pin  "regs.operator[]#1:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load inst "ACC1:acc#331" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 64558 -attr oid 1748 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.operator[]:not.itm(0)} -pin  "ACC1:acc#331" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(1)} -pin  "ACC1:acc#331" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(2)} -pin  "ACC1:acc#331" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(3)} -pin  "ACC1:acc#331" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(4)} -pin  "ACC1:acc#331" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(5)} -pin  "ACC1:acc#331" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(6)} -pin  "ACC1:acc#331" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(7)} -pin  "ACC1:acc#331" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(8)} -pin  "ACC1:acc#331" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]:not.itm(9)} -pin  "ACC1:acc#331" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]:not.itm}
+load net {regs.operator[]#1:not.itm(0)} -pin  "ACC1:acc#331" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(1)} -pin  "ACC1:acc#331" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(2)} -pin  "ACC1:acc#331" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(3)} -pin  "ACC1:acc#331" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(4)} -pin  "ACC1:acc#331" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(5)} -pin  "ACC1:acc#331" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(6)} -pin  "ACC1:acc#331" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(7)} -pin  "ACC1:acc#331" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(8)} -pin  "ACC1:acc#331" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {regs.operator[]#1:not.itm(9)} -pin  "ACC1:acc#331" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#1:not.itm}
+load net {ACC1:acc#331.itm(0)} -pin  "ACC1:acc#331" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(1)} -pin  "ACC1:acc#331" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(2)} -pin  "ACC1:acc#331" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(3)} -pin  "ACC1:acc#331" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(4)} -pin  "ACC1:acc#331" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(5)} -pin  "ACC1:acc#331" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(6)} -pin  "ACC1:acc#331" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(7)} -pin  "ACC1:acc#331" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(8)} -pin  "ACC1:acc#331" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(9)} -pin  "ACC1:acc#331" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(10)} -pin  "ACC1:acc#331" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load inst "regs.operator[]#2:not" "not(10)" "INTERFACE" -attr xrf 64559 -attr oid 1749 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "regs.operator[]#2:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "regs.operator[]#2:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "regs.operator[]#2:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "regs.operator[]#2:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "regs.operator[]#2:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "regs.operator[]#2:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "regs.operator[]#2:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "regs.operator[]#2:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "regs.operator[]#2:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "regs.operator[]#2:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {regs.operator[]#2:not.itm(0)} -pin  "regs.operator[]#2:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(1)} -pin  "regs.operator[]#2:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(2)} -pin  "regs.operator[]#2:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(3)} -pin  "regs.operator[]#2:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(4)} -pin  "regs.operator[]#2:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(5)} -pin  "regs.operator[]#2:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(6)} -pin  "regs.operator[]#2:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(7)} -pin  "regs.operator[]#2:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(8)} -pin  "regs.operator[]#2:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(9)} -pin  "regs.operator[]#2:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load inst "ACC1:acc#330" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 64560 -attr oid 1750 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.operator[]#2:not.itm(0)} -pin  "ACC1:acc#330" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(1)} -pin  "ACC1:acc#330" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(2)} -pin  "ACC1:acc#330" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(3)} -pin  "ACC1:acc#330" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(4)} -pin  "ACC1:acc#330" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(5)} -pin  "ACC1:acc#330" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(6)} -pin  "ACC1:acc#330" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(7)} -pin  "ACC1:acc#330" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(8)} -pin  "ACC1:acc#330" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {regs.operator[]#2:not.itm(9)} -pin  "ACC1:acc#330" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#2:not.itm}
+load net {PWR} -pin  "ACC1:acc#330" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#330" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#330.itm(0)} -pin  "ACC1:acc#330" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(1)} -pin  "ACC1:acc#330" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(2)} -pin  "ACC1:acc#330" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(3)} -pin  "ACC1:acc#330" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(4)} -pin  "ACC1:acc#330" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(5)} -pin  "ACC1:acc#330" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(6)} -pin  "ACC1:acc#330" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(7)} -pin  "ACC1:acc#330" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(8)} -pin  "ACC1:acc#330" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(9)} -pin  "ACC1:acc#330" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(10)} -pin  "ACC1:acc#330" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load inst "ACC1-1:acc" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 64561 -attr oid 1751 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#331.itm(0)} -pin  "ACC1-1:acc" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(1)} -pin  "ACC1-1:acc" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(2)} -pin  "ACC1-1:acc" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(3)} -pin  "ACC1-1:acc" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(4)} -pin  "ACC1-1:acc" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(5)} -pin  "ACC1-1:acc" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(6)} -pin  "ACC1-1:acc" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(7)} -pin  "ACC1-1:acc" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(8)} -pin  "ACC1-1:acc" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(9)} -pin  "ACC1-1:acc" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(10)} -pin  "ACC1-1:acc" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#330.itm(0)} -pin  "ACC1-1:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(1)} -pin  "ACC1-1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(2)} -pin  "ACC1-1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(3)} -pin  "ACC1-1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(4)} -pin  "ACC1-1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(5)} -pin  "ACC1-1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(6)} -pin  "ACC1-1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(7)} -pin  "ACC1-1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(8)} -pin  "ACC1-1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(9)} -pin  "ACC1-1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(10)} -pin  "ACC1-1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {acc.psp#2.sva(0)} -pin  "ACC1-1:acc" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(1)} -pin  "ACC1-1:acc" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(2)} -pin  "ACC1-1:acc" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(3)} -pin  "ACC1-1:acc" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(4)} -pin  "ACC1-1:acc" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(5)} -pin  "ACC1-1:acc" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(6)} -pin  "ACC1-1:acc" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(7)} -pin  "ACC1-1:acc" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(8)} -pin  "ACC1-1:acc" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(9)} -pin  "ACC1-1:acc" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(10)} -pin  "ACC1-1:acc" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load inst "ACC1:not" "not(10)" "INTERFACE" -attr xrf 64562 -attr oid 1752 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "ACC1:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "ACC1:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "ACC1:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "ACC1:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "ACC1:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "ACC1:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "ACC1:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "ACC1:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "ACC1:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "ACC1:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load inst "ACC1:not#307" "not(10)" "INTERFACE" -attr xrf 64563 -attr oid 1753 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "ACC1:not#307" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "ACC1:not#307" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "ACC1:not#307" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "ACC1:not#307" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "ACC1:not#307" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "ACC1:not#307" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "ACC1:not#307" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "ACC1:not#307" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "ACC1:not#307" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "ACC1:not#307" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {ACC1:not#307.itm(0)} -pin  "ACC1:not#307" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(1)} -pin  "ACC1:not#307" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(2)} -pin  "ACC1:not#307" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(3)} -pin  "ACC1:not#307" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(4)} -pin  "ACC1:not#307" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(5)} -pin  "ACC1:not#307" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(6)} -pin  "ACC1:not#307" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(7)} -pin  "ACC1:not#307" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(8)} -pin  "ACC1:not#307" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(9)} -pin  "ACC1:not#307" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load inst "ACC1:acc#341" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 64564 -attr oid 1754 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not.itm(0)} -pin  "ACC1:acc#341" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:acc#341" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:acc#341" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:acc#341" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:acc#341" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:acc#341" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:acc#341" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:acc#341" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:acc#341" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:acc#341" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not#307.itm(0)} -pin  "ACC1:acc#341" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(1)} -pin  "ACC1:acc#341" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(2)} -pin  "ACC1:acc#341" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(3)} -pin  "ACC1:acc#341" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(4)} -pin  "ACC1:acc#341" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(5)} -pin  "ACC1:acc#341" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(6)} -pin  "ACC1:acc#341" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(7)} -pin  "ACC1:acc#341" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(8)} -pin  "ACC1:acc#341" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:not#307.itm(9)} -pin  "ACC1:acc#341" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#307.itm}
+load net {ACC1:acc#341.itm(0)} -pin  "ACC1:acc#341" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(1)} -pin  "ACC1:acc#341" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(2)} -pin  "ACC1:acc#341" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(3)} -pin  "ACC1:acc#341" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(4)} -pin  "ACC1:acc#341" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(5)} -pin  "ACC1:acc#341" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(6)} -pin  "ACC1:acc#341" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(7)} -pin  "ACC1:acc#341" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(8)} -pin  "ACC1:acc#341" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(9)} -pin  "ACC1:acc#341" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(10)} -pin  "ACC1:acc#341" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load inst "ACC1:not#308" "not(10)" "INTERFACE" -attr xrf 64565 -attr oid 1755 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "ACC1:not#308" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "ACC1:not#308" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "ACC1:not#308" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "ACC1:not#308" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "ACC1:not#308" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "ACC1:not#308" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "ACC1:not#308" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "ACC1:not#308" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "ACC1:not#308" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "ACC1:not#308" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:not#308.itm(0)} -pin  "ACC1:not#308" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(1)} -pin  "ACC1:not#308" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(2)} -pin  "ACC1:not#308" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(3)} -pin  "ACC1:not#308" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(4)} -pin  "ACC1:not#308" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(5)} -pin  "ACC1:not#308" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(6)} -pin  "ACC1:not#308" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(7)} -pin  "ACC1:not#308" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(8)} -pin  "ACC1:not#308" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(9)} -pin  "ACC1:not#308" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load inst "ACC1:acc#340" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 64566 -attr oid 1756 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#308.itm(0)} -pin  "ACC1:acc#340" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(1)} -pin  "ACC1:acc#340" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(2)} -pin  "ACC1:acc#340" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(3)} -pin  "ACC1:acc#340" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(4)} -pin  "ACC1:acc#340" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(5)} -pin  "ACC1:acc#340" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(6)} -pin  "ACC1:acc#340" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(7)} -pin  "ACC1:acc#340" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(8)} -pin  "ACC1:acc#340" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {ACC1:not#308.itm(9)} -pin  "ACC1:acc#340" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#308.itm}
+load net {PWR} -pin  "ACC1:acc#340" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#340" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#340.itm(0)} -pin  "ACC1:acc#340" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(1)} -pin  "ACC1:acc#340" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(2)} -pin  "ACC1:acc#340" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(3)} -pin  "ACC1:acc#340" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(4)} -pin  "ACC1:acc#340" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(5)} -pin  "ACC1:acc#340" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(6)} -pin  "ACC1:acc#340" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(7)} -pin  "ACC1:acc#340" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(8)} -pin  "ACC1:acc#340" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(9)} -pin  "ACC1:acc#340" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(10)} -pin  "ACC1:acc#340" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load inst "ACC1-1:acc#224" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 64567 -attr oid 1757 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#224} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#341.itm(0)} -pin  "ACC1-1:acc#224" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(1)} -pin  "ACC1-1:acc#224" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(2)} -pin  "ACC1-1:acc#224" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(3)} -pin  "ACC1-1:acc#224" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(4)} -pin  "ACC1-1:acc#224" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(5)} -pin  "ACC1-1:acc#224" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(6)} -pin  "ACC1-1:acc#224" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(7)} -pin  "ACC1-1:acc#224" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(8)} -pin  "ACC1-1:acc#224" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(9)} -pin  "ACC1-1:acc#224" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(10)} -pin  "ACC1-1:acc#224" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#340.itm(0)} -pin  "ACC1-1:acc#224" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(1)} -pin  "ACC1-1:acc#224" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(2)} -pin  "ACC1-1:acc#224" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(3)} -pin  "ACC1-1:acc#224" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(4)} -pin  "ACC1-1:acc#224" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(5)} -pin  "ACC1-1:acc#224" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(6)} -pin  "ACC1-1:acc#224" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(7)} -pin  "ACC1-1:acc#224" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(8)} -pin  "ACC1-1:acc#224" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(9)} -pin  "ACC1-1:acc#224" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(10)} -pin  "ACC1-1:acc#224" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#224.psp#1.sva(0)} -pin  "ACC1-1:acc#224" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(1)} -pin  "ACC1-1:acc#224" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(2)} -pin  "ACC1-1:acc#224" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(3)} -pin  "ACC1-1:acc#224" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(4)} -pin  "ACC1-1:acc#224" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(5)} -pin  "ACC1-1:acc#224" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(6)} -pin  "ACC1-1:acc#224" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(7)} -pin  "ACC1-1:acc#224" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(8)} -pin  "ACC1-1:acc#224" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(9)} -pin  "ACC1-1:acc#224" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(10)} -pin  "ACC1-1:acc#224" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1-1:acc#224" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp#1.sva}
+load inst "ACC1-3:not#57" "not(1)" "INTERFACE" -attr xrf 64568 -attr oid 1758 -attr @path {/sobel/sobel:core/ACC1-3:not#57} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#405.itm(2)} -pin  "ACC1-3:not#57" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#3.itm}
+load net {ACC1-3:not#57.itm} -pin  "ACC1-3:not#57" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#57.itm}
+load inst "ACC1-3:not#58" "not(1)" "INTERFACE" -attr xrf 64569 -attr oid 1759 -attr @path {/sobel/sobel:core/ACC1-3:not#58} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#405.itm(3)} -pin  "ACC1-3:not#58" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva).itm}
+load net {ACC1-3:not#58.itm} -pin  "ACC1-3:not#58" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#58.itm}
+load inst "ACC1:acc#406" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 64570 -attr oid 1760 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#406} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#406" {A(0)} -attr @path {/sobel/sobel:core/conc#1012.itm}
+load net {ACC1:acc#405.itm(1)} -pin  "ACC1:acc#406" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1012.itm}
+load net {PWR} -pin  "ACC1:acc#406" {A(2)} -attr @path {/sobel/sobel:core/conc#1012.itm}
+load net {ACC1-3:not#58.itm} -pin  "ACC1:acc#406" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1270.itm}
+load net {ACC1-3:not#57.itm} -pin  "ACC1:acc#406" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1270.itm}
+load net {ACC1:acc#406.itm(0)} -pin  "ACC1:acc#406" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#406.itm}
+load net {ACC1:acc#406.itm(1)} -pin  "ACC1:acc#406" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#406.itm}
+load net {ACC1:acc#406.itm(2)} -pin  "ACC1:acc#406" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#406.itm}
+load inst "ACC1-1:not#185" "not(1)" "INTERFACE" -attr xrf 64571 -attr oid 1761 -attr @path {/sobel/sobel:core/ACC1-1:not#185} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#367.itm(2)} -pin  "ACC1-1:not#185" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#42.sva)#3.itm}
+load net {ACC1-1:not#185.itm} -pin  "ACC1-1:not#185" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#185.itm}
+load inst "ACC1-1:not#186" "not(1)" "INTERFACE" -attr xrf 64572 -attr oid 1762 -attr @path {/sobel/sobel:core/ACC1-1:not#186} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#367.itm(3)} -pin  "ACC1-1:not#186" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#42.sva)#1.itm}
+load net {ACC1-1:not#186.itm} -pin  "ACC1-1:not#186" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#186.itm}
+load inst "ACC1:acc#368" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 64573 -attr oid 1763 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#368} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#368" {A(0)} -attr @path {/sobel/sobel:core/conc#1013.itm}
+load net {ACC1:acc#367.itm(1)} -pin  "ACC1:acc#368" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1013.itm}
+load net {PWR} -pin  "ACC1:acc#368" {A(2)} -attr @path {/sobel/sobel:core/conc#1013.itm}
+load net {ACC1-1:not#186.itm} -pin  "ACC1:acc#368" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1198.itm}
+load net {ACC1-1:not#185.itm} -pin  "ACC1:acc#368" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1198.itm}
+load net {ACC1:acc#368.itm(0)} -pin  "ACC1:acc#368" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#368.itm}
+load net {ACC1:acc#368.itm(1)} -pin  "ACC1:acc#368" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#368.itm}
+load net {ACC1:acc#368.itm(2)} -pin  "ACC1:acc#368" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#368.itm}
+load inst "ACC1-1:not#291" "not(2)" "INTERFACE" -attr xrf 64574 -attr oid 1764 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#291} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#219.psp#1.sva(1)} -pin  "ACC1-1:not#291" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#1.sva).itm}
+load net {ACC1:acc#219.psp#1.sva(2)} -pin  "ACC1-1:not#291" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#1.sva).itm}
+load net {ACC1-1:not#291.itm(0)} -pin  "ACC1-1:not#291" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#291.itm}
+load net {ACC1-1:not#291.itm(1)} -pin  "ACC1-1:not#291" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#291.itm}
+load inst "ACC1:acc#367" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 64575 -attr oid 1765 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#367} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#367" {A(0)} -attr @path {/sobel/sobel:core/conc#1014.itm}
+load net {ACC1-1:not#291.itm(0)} -pin  "ACC1:acc#367" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1014.itm}
+load net {ACC1-1:not#291.itm(1)} -pin  "ACC1:acc#367" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1014.itm}
+load net {PWR} -pin  "ACC1:acc#367" {B(0)} -attr @path {/sobel/sobel:core/conc#1015.itm}
+load net {ACC1:acc#219.psp#1.sva(0)} -pin  "ACC1:acc#367" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1015.itm}
+load net {ACC1:acc#367.itm(0)} -pin  "ACC1:acc#367" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#367.itm}
+load net {ACC1:acc#367.itm(1)} -pin  "ACC1:acc#367" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#367.itm}
+load net {ACC1:acc#367.itm(2)} -pin  "ACC1:acc#367" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#367.itm}
+load net {ACC1:acc#367.itm(3)} -pin  "ACC1:acc#367" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#367.itm}
+load inst "ACC1-1:not#307" "not(1)" "INTERFACE" -attr xrf 64576 -attr oid 1766 -attr @path {/sobel/sobel:core/ACC1-1:not#307} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(11)} -pin  "ACC1-1:not#307" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#23.itm}
+load net {ACC1-1:not#307.itm} -pin  "ACC1-1:not#307" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#307.itm}
+load inst "ACC1-1:not#220" "not(1)" "INTERFACE" -attr xrf 64577 -attr oid 1767 -attr @path {/sobel/sobel:core/ACC1-1:not#220} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(1)} -pin  "ACC1-1:not#220" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#15.itm}
+load net {ACC1-1:not#220.itm} -pin  "ACC1-1:not#220" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#220.itm}
+load inst "ACC1:acc#363" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 64578 -attr oid 1768 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#363} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#363" {A(0)} -attr @path {/sobel/sobel:core/conc#1017.itm}
+load net {ACC1-1:not#307.itm} -pin  "ACC1:acc#363" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1017.itm}
+load net {ACC1-1:acc#25.psp.sva(8)} -pin  "ACC1:acc#363" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1187.itm}
+load net {ACC1-1:not#220.itm} -pin  "ACC1:acc#363" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1187.itm}
+load net {ACC1:acc#363.itm(0)} -pin  "ACC1:acc#363" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#363.itm}
+load net {ACC1:acc#363.itm(1)} -pin  "ACC1:acc#363" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#363.itm}
+load net {ACC1:acc#363.itm(2)} -pin  "ACC1:acc#363" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#363.itm}
+load net {ACC1:acc#363.itm(3)} -pin  "ACC1:acc#363" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#363.itm}
+load inst "ACC1:acc#365" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 64579 -attr oid 1769 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#365" {A(0)} -attr @path {/sobel/sobel:core/conc#1016.itm}
+load net {ACC1:acc#363.itm(1)} -pin  "ACC1:acc#365" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1016.itm}
+load net {ACC1:acc#363.itm(2)} -pin  "ACC1:acc#365" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1016.itm}
+load net {ACC1:acc#363.itm(3)} -pin  "ACC1:acc#365" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1016.itm}
+load net {ACC1-1:acc#25.psp.sva(10)} -pin  "ACC1:acc#365" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1018.itm}
+load net {ACC1-1:acc#25.psp.sva(0)} -pin  "ACC1:acc#365" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1018.itm}
+load net {GND} -pin  "ACC1:acc#365" {B(2)} -attr @path {/sobel/sobel:core/conc#1018.itm}
+load net {PWR} -pin  "ACC1:acc#365" {B(3)} -attr @path {/sobel/sobel:core/conc#1018.itm}
+load net {ACC1:acc#365.itm(0)} -pin  "ACC1:acc#365" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365.itm}
+load net {ACC1:acc#365.itm(1)} -pin  "ACC1:acc#365" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365.itm}
+load net {ACC1:acc#365.itm(2)} -pin  "ACC1:acc#365" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365.itm}
+load net {ACC1:acc#365.itm(3)} -pin  "ACC1:acc#365" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365.itm}
+load net {ACC1:acc#365.itm(4)} -pin  "ACC1:acc#365" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#365.itm}
+load inst "ACC1-1:not#221" "not(1)" "INTERFACE" -attr xrf 64580 -attr oid 1770 -attr @path {/sobel/sobel:core/ACC1-1:not#221} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(3)} -pin  "ACC1-1:not#221" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#17.itm}
+load net {ACC1-1:not#221.itm} -pin  "ACC1-1:not#221" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#221.itm}
+load inst "ACC1-1:not#223" "not(1)" "INTERFACE" -attr xrf 64581 -attr oid 1771 -attr @path {/sobel/sobel:core/ACC1-1:not#223} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(7)} -pin  "ACC1-1:not#223" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#2.itm}
+load net {ACC1-1:not#223.itm} -pin  "ACC1-1:not#223" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#223.itm}
+load inst "ACC1:acc#362" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64582 -attr oid 1772 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#362} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#362" {A(0)} -attr @path {/sobel/sobel:core/conc#1020.itm}
+load net {ACC1-1:acc#25.psp.sva(2)} -pin  "ACC1:acc#362" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1020.itm}
+load net {ACC1-1:not#223.itm} -pin  "ACC1:acc#362" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1185.itm}
+load net {ACC1-1:not#221.itm} -pin  "ACC1:acc#362" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1185.itm}
+load net {ACC1:acc#362.itm(0)} -pin  "ACC1:acc#362" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#362.itm}
+load net {ACC1:acc#362.itm(1)} -pin  "ACC1:acc#362" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#362.itm}
+load net {ACC1:acc#362.itm(2)} -pin  "ACC1:acc#362" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#362.itm}
+load inst "ACC1-1:not#222" "not(1)" "INTERFACE" -attr xrf 64583 -attr oid 1773 -attr @path {/sobel/sobel:core/ACC1-1:not#222} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(5)} -pin  "ACC1-1:not#222" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#5.itm}
+load net {ACC1-1:not#222.itm} -pin  "ACC1-1:not#222" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#222.itm}
+load inst "ACC1:acc#361" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64584 -attr oid 1774 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#361} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#361" {A(0)} -attr @path {/sobel/sobel:core/conc#1021.itm}
+load net {ACC1-1:acc#25.psp.sva(4)} -pin  "ACC1:acc#361" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1021.itm}
+load net {ACC1-1:acc#25.psp.sva(6)} -pin  "ACC1:acc#361" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1183.itm}
+load net {ACC1-1:not#222.itm} -pin  "ACC1:acc#361" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1183.itm}
+load net {ACC1:acc#361.itm(0)} -pin  "ACC1:acc#361" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#361.itm}
+load net {ACC1:acc#361.itm(1)} -pin  "ACC1:acc#361" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#361.itm}
+load net {ACC1:acc#361.itm(2)} -pin  "ACC1:acc#361" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#361.itm}
+load inst "ACC1-1:not#224" "not(1)" "INTERFACE" -attr xrf 64585 -attr oid 1775 -attr @path {/sobel/sobel:core/ACC1-1:not#224} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#25.psp.sva(9)} -pin  "ACC1-1:not#224" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#25.psp.sva)#3.itm}
+load net {ACC1-1:not#224.itm} -pin  "ACC1-1:not#224" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#224.itm}
+load inst "ACC1:acc#364" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64586 -attr oid 1776 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#364} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#364" {A(0)} -attr @path {/sobel/sobel:core/conc#1019.itm}
+load net {ACC1:acc#362.itm(1)} -pin  "ACC1:acc#364" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1019.itm}
+load net {ACC1:acc#362.itm(2)} -pin  "ACC1:acc#364" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1019.itm}
+load net {ACC1-1:not#224.itm} -pin  "ACC1:acc#364" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1189.itm}
+load net {ACC1:acc#361.itm(1)} -pin  "ACC1:acc#364" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1189.itm}
+load net {ACC1:acc#361.itm(2)} -pin  "ACC1:acc#364" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1189.itm}
+load net {ACC1:acc#364.itm(0)} -pin  "ACC1:acc#364" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#364.itm}
+load net {ACC1:acc#364.itm(1)} -pin  "ACC1:acc#364" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#364.itm}
+load net {ACC1:acc#364.itm(2)} -pin  "ACC1:acc#364" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#364.itm}
+load net {ACC1:acc#364.itm(3)} -pin  "ACC1:acc#364" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#364.itm}
+load inst "ACC1-1:acc#208" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 64587 -attr oid 1777 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#208} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#365.itm(1)} -pin  "ACC1-1:acc#208" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#41.itm}
+load net {ACC1:acc#365.itm(2)} -pin  "ACC1-1:acc#208" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#41.itm}
+load net {ACC1:acc#365.itm(3)} -pin  "ACC1-1:acc#208" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#41.itm}
+load net {ACC1:acc#365.itm(4)} -pin  "ACC1-1:acc#208" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#41.itm}
+load net {ACC1:acc#364.itm(1)} -pin  "ACC1-1:acc#208" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1:acc#364.itm(2)} -pin  "ACC1-1:acc#208" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1:acc#364.itm(3)} -pin  "ACC1-1:acc#208" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1-1:acc#208.psp.sva(0)} -pin  "ACC1-1:acc#208" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#208.psp.sva}
+load net {ACC1-1:acc#208.psp.sva(1)} -pin  "ACC1-1:acc#208" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#208.psp.sva}
+load net {ACC1-1:acc#208.psp.sva(2)} -pin  "ACC1-1:acc#208" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#208.psp.sva}
+load net {ACC1-1:acc#208.psp.sva(3)} -pin  "ACC1-1:acc#208" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#208.psp.sva}
+load inst "ACC1-1:not#89" "not(1)" "INTERFACE" -attr xrf 64588 -attr oid 1778 -attr @path {/sobel/sobel:core/ACC1-1:not#89} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#348.itm(2)} -pin  "ACC1-1:not#89" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#34.sva)#3.itm}
+load net {ACC1-1:not#89.itm} -pin  "ACC1-1:not#89" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#89.itm}
+load inst "ACC1-1:not#90" "not(1)" "INTERFACE" -attr xrf 64589 -attr oid 1779 -attr @path {/sobel/sobel:core/ACC1-1:not#90} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#348.itm(3)} -pin  "ACC1-1:not#90" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#34.sva)#1.itm}
+load net {ACC1-1:not#90.itm} -pin  "ACC1-1:not#90" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#90.itm}
+load inst "ACC1:acc#349" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 64590 -attr oid 1780 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#349} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#349" {A(0)} -attr @path {/sobel/sobel:core/conc#1022.itm}
+load net {ACC1:acc#348.itm(1)} -pin  "ACC1:acc#349" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1022.itm}
+load net {PWR} -pin  "ACC1:acc#349" {A(2)} -attr @path {/sobel/sobel:core/conc#1022.itm}
+load net {ACC1-1:not#90.itm} -pin  "ACC1:acc#349" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1162.itm}
+load net {ACC1-1:not#89.itm} -pin  "ACC1:acc#349" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1162.itm}
+load net {ACC1:acc#349.itm(0)} -pin  "ACC1:acc#349" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#349.itm}
+load net {ACC1:acc#349.itm(1)} -pin  "ACC1:acc#349" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#349.itm}
+load net {ACC1:acc#349.itm(2)} -pin  "ACC1:acc#349" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#349.itm}
+load inst "ACC1-1:not#297" "not(2)" "INTERFACE" -attr xrf 64591 -attr oid 1781 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#297} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#222.psp#1.sva(1)} -pin  "ACC1-1:not#297" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp#1.sva).itm}
+load net {ACC1:acc#222.psp#1.sva(2)} -pin  "ACC1-1:not#297" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp#1.sva).itm}
+load net {ACC1-1:not#297.itm(0)} -pin  "ACC1-1:not#297" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#297.itm}
+load net {ACC1-1:not#297.itm(1)} -pin  "ACC1-1:not#297" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#297.itm}
+load inst "ACC1:acc#348" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 64592 -attr oid 1782 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#348" {A(0)} -attr @path {/sobel/sobel:core/conc#1023.itm}
+load net {ACC1-1:not#297.itm(0)} -pin  "ACC1:acc#348" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1023.itm}
+load net {ACC1-1:not#297.itm(1)} -pin  "ACC1:acc#348" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1023.itm}
+load net {PWR} -pin  "ACC1:acc#348" {B(0)} -attr @path {/sobel/sobel:core/conc#1024.itm}
+load net {ACC1:acc#222.psp#1.sva(0)} -pin  "ACC1:acc#348" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1024.itm}
+load net {ACC1:acc#348.itm(0)} -pin  "ACC1:acc#348" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {ACC1:acc#348.itm(1)} -pin  "ACC1:acc#348" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {ACC1:acc#348.itm(2)} -pin  "ACC1:acc#348" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {ACC1:acc#348.itm(3)} -pin  "ACC1:acc#348" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load inst "ACC1:acc#407" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 64593 -attr oid 1783 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.regs:slc(regs.regs(2))#4.itm(0)} -pin  "ACC1:acc#407" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(1)} -pin  "ACC1:acc#407" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(2)} -pin  "ACC1:acc#407" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(3)} -pin  "ACC1:acc#407" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(4)} -pin  "ACC1:acc#407" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(5)} -pin  "ACC1:acc#407" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(6)} -pin  "ACC1:acc#407" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(7)} -pin  "ACC1:acc#407" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(8)} -pin  "ACC1:acc#407" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#4.itm(9)} -pin  "ACC1:acc#407" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#4.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(0)} -pin  "ACC1:acc#407" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(1)} -pin  "ACC1:acc#407" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(2)} -pin  "ACC1:acc#407" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(3)} -pin  "ACC1:acc#407" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(4)} -pin  "ACC1:acc#407" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(5)} -pin  "ACC1:acc#407" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(6)} -pin  "ACC1:acc#407" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(7)} -pin  "ACC1:acc#407" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(8)} -pin  "ACC1:acc#407" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {regs.regs:slc(regs.regs(2))#5.itm(9)} -pin  "ACC1:acc#407" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#5.itm}
+load net {ACC1:acc#407.itm(0)} -pin  "ACC1:acc#407" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(1)} -pin  "ACC1:acc#407" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(2)} -pin  "ACC1:acc#407" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(3)} -pin  "ACC1:acc#407" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(4)} -pin  "ACC1:acc#407" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(5)} -pin  "ACC1:acc#407" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(6)} -pin  "ACC1:acc#407" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(7)} -pin  "ACC1:acc#407" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(8)} -pin  "ACC1:acc#407" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(9)} -pin  "ACC1:acc#407" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(10)} -pin  "ACC1:acc#407" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load inst "ACC1-3:acc#224" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 64594 -attr oid 1784 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#224} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#407.itm(0)} -pin  "ACC1-3:acc#224" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(1)} -pin  "ACC1-3:acc#224" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(2)} -pin  "ACC1-3:acc#224" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(3)} -pin  "ACC1-3:acc#224" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(4)} -pin  "ACC1-3:acc#224" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(5)} -pin  "ACC1-3:acc#224" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(6)} -pin  "ACC1-3:acc#224" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(7)} -pin  "ACC1-3:acc#224" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(8)} -pin  "ACC1-3:acc#224" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(9)} -pin  "ACC1-3:acc#224" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {ACC1:acc#407.itm(10)} -pin  "ACC1-3:acc#224" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#407.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(0)} -pin  "ACC1-3:acc#224" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(1)} -pin  "ACC1-3:acc#224" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(2)} -pin  "ACC1-3:acc#224" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(3)} -pin  "ACC1-3:acc#224" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(4)} -pin  "ACC1-3:acc#224" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(5)} -pin  "ACC1-3:acc#224" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(6)} -pin  "ACC1-3:acc#224" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(7)} -pin  "ACC1-3:acc#224" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(8)} -pin  "ACC1-3:acc#224" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {regs.regs:slc(regs.regs(2))#3.itm(9)} -pin  "ACC1-3:acc#224" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#3.itm}
+load net {ACC1:acc#224.psp.sva(0)} -pin  "ACC1-3:acc#224" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(1)} -pin  "ACC1-3:acc#224" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(2)} -pin  "ACC1-3:acc#224" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(3)} -pin  "ACC1-3:acc#224" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(4)} -pin  "ACC1-3:acc#224" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(5)} -pin  "ACC1-3:acc#224" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(6)} -pin  "ACC1-3:acc#224" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(7)} -pin  "ACC1-3:acc#224" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(8)} -pin  "ACC1-3:acc#224" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(9)} -pin  "ACC1-3:acc#224" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(10)} -pin  "ACC1-3:acc#224" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1-3:acc#224" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.psp.sva}
+load inst "ACC1:acc#516" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64595 -attr oid 1785 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#516" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1051.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#516" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1051.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#516" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1043.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#516" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#1043.itm}
+load net {ACC1:acc#516.cse(0)} -pin  "ACC1:acc#516" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(1)} -pin  "ACC1:acc#516" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load net {ACC1:acc#516.cse(2)} -pin  "ACC1:acc#516" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#516.cse}
+load inst "ACC1-3:not#247" "not(1)" "INTERFACE" -attr xrf 64596 -attr oid 1786 -attr @path {/sobel/sobel:core/ACC1-3:not#247} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp.sva(0)} -pin  "ACC1-3:not#247" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#12.itm}
+load net {ACC1-3:not#247.itm} -pin  "ACC1-3:not#247" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#247.itm}
+load inst "ACC1-3:not#248" "not(1)" "INTERFACE" -attr xrf 64597 -attr oid 1787 -attr @path {/sobel/sobel:core/ACC1-3:not#248} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp.sva(2)} -pin  "ACC1-3:not#248" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#3.itm}
+load net {ACC1-3:not#248.itm} -pin  "ACC1-3:not#248" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#248.itm}
+load inst "ACC1-3:not#250" "not(1)" "INTERFACE" -attr xrf 64598 -attr oid 1788 -attr @path {/sobel/sobel:core/ACC1-3:not#250} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp.sva(6)} -pin  "ACC1-3:not#250" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva).itm}
+load net {ACC1-3:not#250.itm} -pin  "ACC1-3:not#250" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#250.itm}
+load inst "ACC1:acc#409" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64599 -attr oid 1789 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#409} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#409" {A(0)} -attr @path {/sobel/sobel:core/conc#1027.itm}
+load net {ACC1:acc#224.psp.sva(1)} -pin  "ACC1:acc#409" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1027.itm}
+load net {ACC1-3:not#250.itm} -pin  "ACC1:acc#409" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1275.itm}
+load net {ACC1-3:not#248.itm} -pin  "ACC1:acc#409" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1275.itm}
+load net {ACC1:acc#409.itm(0)} -pin  "ACC1:acc#409" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#409.itm}
+load net {ACC1:acc#409.itm(1)} -pin  "ACC1:acc#409" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#409.itm}
+load net {ACC1:acc#409.itm(2)} -pin  "ACC1:acc#409" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#409.itm}
+load inst "ACC1-3:not#251" "not(1)" "INTERFACE" -attr xrf 64600 -attr oid 1790 -attr @path {/sobel/sobel:core/ACC1-3:not#251} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp.sva(8)} -pin  "ACC1-3:not#251" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#15.itm}
+load net {ACC1-3:not#251.itm} -pin  "ACC1-3:not#251" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#251.itm}
+load inst "ACC1:acc#411" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 64601 -attr oid 1791 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#411} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#411" {A(0)} -attr @path {/sobel/sobel:core/conc#1026.itm}
+load net {ACC1-3:not#247.itm} -pin  "ACC1:acc#411" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1026.itm}
+load net {GND} -pin  "ACC1:acc#411" {A(2)} -attr @path {/sobel/sobel:core/conc#1026.itm}
+load net {PWR} -pin  "ACC1:acc#411" {A(3)} -attr @path {/sobel/sobel:core/conc#1026.itm}
+load net {ACC1-3:not#251.itm} -pin  "ACC1:acc#411" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1279.itm}
+load net {ACC1:acc#409.itm(1)} -pin  "ACC1:acc#411" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1279.itm}
+load net {ACC1:acc#409.itm(2)} -pin  "ACC1:acc#411" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1279.itm}
+load net {ACC1:acc#411.itm(0)} -pin  "ACC1:acc#411" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#411.itm}
+load net {ACC1:acc#411.itm(1)} -pin  "ACC1:acc#411" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#411.itm}
+load net {ACC1:acc#411.itm(2)} -pin  "ACC1:acc#411" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#411.itm}
+load net {ACC1:acc#411.itm(3)} -pin  "ACC1:acc#411" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#411.itm}
+load inst "ACC1-3:not#249" "not(1)" "INTERFACE" -attr xrf 64602 -attr oid 1792 -attr @path {/sobel/sobel:core/ACC1-3:not#249} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp.sva(4)} -pin  "ACC1-3:not#249" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#7.itm}
+load net {ACC1-3:not#249.itm} -pin  "ACC1-3:not#249" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#249.itm}
+load inst "ACC1:acc#408" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64603 -attr oid 1793 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#408} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#408" {A(0)} -attr @path {/sobel/sobel:core/conc#1029.itm}
+load net {ACC1:acc#224.psp.sva(3)} -pin  "ACC1:acc#408" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1029.itm}
+load net {ACC1:acc#224.psp.sva(5)} -pin  "ACC1:acc#408" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1273.itm}
+load net {ACC1-3:not#249.itm} -pin  "ACC1:acc#408" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1273.itm}
+load net {ACC1:acc#408.itm(0)} -pin  "ACC1:acc#408" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#408.itm}
+load net {ACC1:acc#408.itm(1)} -pin  "ACC1:acc#408" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#408.itm}
+load net {ACC1:acc#408.itm(2)} -pin  "ACC1:acc#408" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#408.itm}
+load inst "ACC1-3:not#252" "not(2)" "INTERFACE" -attr xrf 64604 -attr oid 1794 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#252} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#224.psp.sva(10)} -pin  "ACC1-3:not#252" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#14.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1-3:not#252" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#14.itm}
+load net {ACC1-3:not#252.itm(0)} -pin  "ACC1-3:not#252" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#252.itm}
+load net {ACC1-3:not#252.itm(1)} -pin  "ACC1-3:not#252" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#252.itm}
+load inst "ACC1:acc#410" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 64605 -attr oid 1795 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#410" {A(0)} -attr @path {/sobel/sobel:core/conc#1028.itm}
+load net {ACC1:acc#408.itm(1)} -pin  "ACC1:acc#410" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1028.itm}
+load net {ACC1:acc#408.itm(2)} -pin  "ACC1:acc#410" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1028.itm}
+load net {ACC1:acc#224.psp.sva(7)} -pin  "ACC1:acc#410" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1277.itm}
+load net {ACC1-3:not#252.itm(0)} -pin  "ACC1:acc#410" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1277.itm}
+load net {ACC1-3:not#252.itm(1)} -pin  "ACC1:acc#410" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1277.itm}
+load net {ACC1:acc#410.itm(0)} -pin  "ACC1:acc#410" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410.itm}
+load net {ACC1:acc#410.itm(1)} -pin  "ACC1:acc#410" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410.itm}
+load net {ACC1:acc#410.itm(2)} -pin  "ACC1:acc#410" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410.itm}
+load net {ACC1:acc#410.itm(3)} -pin  "ACC1:acc#410" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410.itm}
+load net {ACC1:acc#410.itm(4)} -pin  "ACC1:acc#410" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#410.itm}
+load inst "ACC1:acc#412" "add(4,1,5,-1,5)" "INTERFACE" -attr xrf 64606 -attr oid 1796 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "ACC1:acc#412" {A(0)} -attr @path {/sobel/sobel:core/conc#1025.itm}
+load net {ACC1:acc#411.itm(1)} -pin  "ACC1:acc#412" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1025.itm}
+load net {ACC1:acc#411.itm(2)} -pin  "ACC1:acc#412" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1025.itm}
+load net {ACC1:acc#411.itm(3)} -pin  "ACC1:acc#412" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1025.itm}
+load net {ACC1:acc#224.psp.sva(9)} -pin  "ACC1:acc#412" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1281.itm}
+load net {ACC1:acc#410.itm(1)} -pin  "ACC1:acc#412" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1281.itm}
+load net {ACC1:acc#410.itm(2)} -pin  "ACC1:acc#412" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1281.itm}
+load net {ACC1:acc#410.itm(3)} -pin  "ACC1:acc#412" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1281.itm}
+load net {ACC1:acc#410.itm(4)} -pin  "ACC1:acc#412" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1281.itm}
+load net {ACC1:acc#412.itm(0)} -pin  "ACC1:acc#412" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412.itm}
+load net {ACC1:acc#412.itm(1)} -pin  "ACC1:acc#412" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412.itm}
+load net {ACC1:acc#412.itm(2)} -pin  "ACC1:acc#412" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412.itm}
+load net {ACC1:acc#412.itm(3)} -pin  "ACC1:acc#412" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412.itm}
+load net {ACC1:acc#412.itm(4)} -pin  "ACC1:acc#412" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#412.itm}
+load inst "ACC1-3:not#299" "not(2)" "INTERFACE" -attr xrf 64607 -attr oid 1797 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#299} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#223.psp.sva(1)} -pin  "ACC1-3:not#299" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp.sva).itm}
+load net {ACC1:acc#223.psp.sva(2)} -pin  "ACC1-3:not#299" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp.sva).itm}
+load net {ACC1-3:not#299.itm(0)} -pin  "ACC1-3:not#299" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#299.itm}
+load net {ACC1-3:not#299.itm(1)} -pin  "ACC1-3:not#299" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#299.itm}
+load inst "ACC1:acc#423" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 64608 -attr oid 1798 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#423} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#423" {A(0)} -attr @path {/sobel/sobel:core/conc#1030.itm}
+load net {ACC1-3:not#299.itm(0)} -pin  "ACC1:acc#423" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1030.itm}
+load net {ACC1-3:not#299.itm(1)} -pin  "ACC1:acc#423" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1030.itm}
+load net {PWR} -pin  "ACC1:acc#423" {B(0)} -attr @path {/sobel/sobel:core/conc#1031.itm}
+load net {ACC1:acc#223.psp.sva(0)} -pin  "ACC1:acc#423" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1031.itm}
+load net {ACC1:acc#423.itm(0)} -pin  "ACC1:acc#423" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#423.itm}
+load net {ACC1:acc#423.itm(1)} -pin  "ACC1:acc#423" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#423.itm}
+load net {ACC1:acc#423.itm(2)} -pin  "ACC1:acc#423" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#423.itm}
+load net {ACC1:acc#423.itm(3)} -pin  "ACC1:acc#423" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#423.itm}
+load inst "ACC1-2:not#238" "not(1)" "INTERFACE" -attr xrf 64609 -attr oid 1799 -attr @path {/sobel/sobel:core/ACC1-2:not#238} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#228.psp.sva(0)} -pin  "ACC1-2:not#238" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#7.itm}
+load net {ACC1-2:not#238.itm} -pin  "ACC1-2:not#238" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#238.itm}
+load inst "ACC1-2:not#239" "not(1)" "INTERFACE" -attr xrf 64610 -attr oid 1800 -attr @path {/sobel/sobel:core/ACC1-2:not#239} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#228.psp.sva(2)} -pin  "ACC1-2:not#239" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#6.itm}
+load net {ACC1-2:not#239.itm} -pin  "ACC1-2:not#239" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#239.itm}
+load inst "ACC1-2:not#241" "not(1)" "INTERFACE" -attr xrf 64611 -attr oid 1801 -attr @path {/sobel/sobel:core/ACC1-2:not#241} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#228.psp.sva(6)} -pin  "ACC1-2:not#241" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#13.itm}
+load net {ACC1-2:not#241.itm} -pin  "ACC1-2:not#241" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#241.itm}
+load inst "ACC1:acc#372" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64612 -attr oid 1802 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#372} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#372" {A(0)} -attr @path {/sobel/sobel:core/conc#1034.itm}
+load net {ACC1:acc#228.psp.sva(1)} -pin  "ACC1:acc#372" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1034.itm}
+load net {ACC1-2:not#241.itm} -pin  "ACC1:acc#372" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1203.itm}
+load net {ACC1-2:not#239.itm} -pin  "ACC1:acc#372" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1203.itm}
+load net {ACC1:acc#372.itm(0)} -pin  "ACC1:acc#372" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#372.itm}
+load net {ACC1:acc#372.itm(1)} -pin  "ACC1:acc#372" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#372.itm}
+load net {ACC1:acc#372.itm(2)} -pin  "ACC1:acc#372" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#372.itm}
+load inst "ACC1-2:not#242" "not(1)" "INTERFACE" -attr xrf 64613 -attr oid 1803 -attr @path {/sobel/sobel:core/ACC1-2:not#242} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#228.psp.sva(8)} -pin  "ACC1-2:not#242" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#4.itm}
+load net {ACC1-2:not#242.itm} -pin  "ACC1-2:not#242" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#242.itm}
+load inst "ACC1:acc#374" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 64614 -attr oid 1804 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#374} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#374" {A(0)} -attr @path {/sobel/sobel:core/conc#1033.itm}
+load net {ACC1-2:not#238.itm} -pin  "ACC1:acc#374" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1033.itm}
+load net {GND} -pin  "ACC1:acc#374" {A(2)} -attr @path {/sobel/sobel:core/conc#1033.itm}
+load net {PWR} -pin  "ACC1:acc#374" {A(3)} -attr @path {/sobel/sobel:core/conc#1033.itm}
+load net {ACC1-2:not#242.itm} -pin  "ACC1:acc#374" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1207.itm}
+load net {ACC1:acc#372.itm(1)} -pin  "ACC1:acc#374" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1207.itm}
+load net {ACC1:acc#372.itm(2)} -pin  "ACC1:acc#374" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1207.itm}
+load net {ACC1:acc#374.itm(0)} -pin  "ACC1:acc#374" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#374.itm}
+load net {ACC1:acc#374.itm(1)} -pin  "ACC1:acc#374" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#374.itm}
+load net {ACC1:acc#374.itm(2)} -pin  "ACC1:acc#374" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#374.itm}
+load net {ACC1:acc#374.itm(3)} -pin  "ACC1:acc#374" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#374.itm}
+load inst "ACC1-2:not#240" "not(1)" "INTERFACE" -attr xrf 64615 -attr oid 1805 -attr @path {/sobel/sobel:core/ACC1-2:not#240} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#228.psp.sva(4)} -pin  "ACC1-2:not#240" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#3.itm}
+load net {ACC1-2:not#240.itm} -pin  "ACC1-2:not#240" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#240.itm}
+load inst "ACC1:acc#371" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64616 -attr oid 1806 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#371} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#371" {A(0)} -attr @path {/sobel/sobel:core/conc#1036.itm}
+load net {ACC1:acc#228.psp.sva(3)} -pin  "ACC1:acc#371" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1036.itm}
+load net {ACC1:acc#228.psp.sva(5)} -pin  "ACC1:acc#371" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1201.itm}
+load net {ACC1-2:not#240.itm} -pin  "ACC1:acc#371" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1201.itm}
+load net {ACC1:acc#371.itm(0)} -pin  "ACC1:acc#371" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#371.itm}
+load net {ACC1:acc#371.itm(1)} -pin  "ACC1:acc#371" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#371.itm}
+load net {ACC1:acc#371.itm(2)} -pin  "ACC1:acc#371" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#371.itm}
+load inst "ACC1-2:not#243" "not(2)" "INTERFACE" -attr xrf 64617 -attr oid 1807 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#243} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#228.psp.sva(10)} -pin  "ACC1-2:not#243" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#12.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1-2:not#243" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#12.itm}
+load net {ACC1-2:not#243.itm(0)} -pin  "ACC1-2:not#243" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#243.itm}
+load net {ACC1-2:not#243.itm(1)} -pin  "ACC1-2:not#243" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#243.itm}
+load inst "ACC1:acc#373" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 64618 -attr oid 1808 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#373" {A(0)} -attr @path {/sobel/sobel:core/conc#1035.itm}
+load net {ACC1:acc#371.itm(1)} -pin  "ACC1:acc#373" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1035.itm}
+load net {ACC1:acc#371.itm(2)} -pin  "ACC1:acc#373" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1035.itm}
+load net {ACC1:acc#228.psp.sva(7)} -pin  "ACC1:acc#373" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1205.itm}
+load net {ACC1-2:not#243.itm(0)} -pin  "ACC1:acc#373" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1205.itm}
+load net {ACC1-2:not#243.itm(1)} -pin  "ACC1:acc#373" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1205.itm}
+load net {ACC1:acc#373.itm(0)} -pin  "ACC1:acc#373" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373.itm}
+load net {ACC1:acc#373.itm(1)} -pin  "ACC1:acc#373" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373.itm}
+load net {ACC1:acc#373.itm(2)} -pin  "ACC1:acc#373" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373.itm}
+load net {ACC1:acc#373.itm(3)} -pin  "ACC1:acc#373" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373.itm}
+load net {ACC1:acc#373.itm(4)} -pin  "ACC1:acc#373" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#373.itm}
+load inst "ACC1:acc#375" "add(4,1,5,-1,5)" "INTERFACE" -attr xrf 64619 -attr oid 1809 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "ACC1:acc#375" {A(0)} -attr @path {/sobel/sobel:core/conc#1032.itm}
+load net {ACC1:acc#374.itm(1)} -pin  "ACC1:acc#375" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1032.itm}
+load net {ACC1:acc#374.itm(2)} -pin  "ACC1:acc#375" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1032.itm}
+load net {ACC1:acc#374.itm(3)} -pin  "ACC1:acc#375" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1032.itm}
+load net {ACC1:acc#228.psp.sva(9)} -pin  "ACC1:acc#375" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1209.itm}
+load net {ACC1:acc#373.itm(1)} -pin  "ACC1:acc#375" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1209.itm}
+load net {ACC1:acc#373.itm(2)} -pin  "ACC1:acc#375" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1209.itm}
+load net {ACC1:acc#373.itm(3)} -pin  "ACC1:acc#375" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1209.itm}
+load net {ACC1:acc#373.itm(4)} -pin  "ACC1:acc#375" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1209.itm}
+load net {ACC1:acc#375.itm(0)} -pin  "ACC1:acc#375" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375.itm}
+load net {ACC1:acc#375.itm(1)} -pin  "ACC1:acc#375" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375.itm}
+load net {ACC1:acc#375.itm(2)} -pin  "ACC1:acc#375" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375.itm}
+load net {ACC1:acc#375.itm(3)} -pin  "ACC1:acc#375" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375.itm}
+load net {ACC1:acc#375.itm(4)} -pin  "ACC1:acc#375" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#375.itm}
+load inst "ACC1-3:not#293" "not(2)" "INTERFACE" -attr xrf 64620 -attr oid 1810 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#293} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#220.psp.sva(1)} -pin  "ACC1-3:not#293" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp.sva).itm}
+load net {ACC1:acc#220.psp.sva(2)} -pin  "ACC1-3:not#293" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#220.psp.sva).itm}
+load net {ACC1-3:not#293.itm(0)} -pin  "ACC1-3:not#293" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#293.itm}
+load net {ACC1-3:not#293.itm(1)} -pin  "ACC1-3:not#293" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#293.itm}
+load inst "ACC1:acc#395" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 64621 -attr oid 1811 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#395} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#395" {A(0)} -attr @path {/sobel/sobel:core/conc#1037.itm}
+load net {ACC1-3:not#293.itm(0)} -pin  "ACC1:acc#395" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1037.itm}
+load net {ACC1-3:not#293.itm(1)} -pin  "ACC1:acc#395" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1037.itm}
+load net {PWR} -pin  "ACC1:acc#395" {B(0)} -attr @path {/sobel/sobel:core/conc#1038.itm}
+load net {ACC1:acc#220.psp.sva(0)} -pin  "ACC1:acc#395" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1038.itm}
+load net {ACC1:acc#395.itm(0)} -pin  "ACC1:acc#395" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#395.itm}
+load net {ACC1:acc#395.itm(1)} -pin  "ACC1:acc#395" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#395.itm}
+load net {ACC1:acc#395.itm(2)} -pin  "ACC1:acc#395" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#395.itm}
+load net {ACC1:acc#395.itm(3)} -pin  "ACC1:acc#395" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#395.itm}
+load inst "ACC1-2:not#220" "not(1)" "INTERFACE" -attr xrf 64622 -attr oid 1812 -attr @path {/sobel/sobel:core/ACC1-2:not#220} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#226.psp.sva(0)} -pin  "ACC1-2:not#220" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#7.itm}
+load net {ACC1-2:not#220.itm} -pin  "ACC1-2:not#220" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#220.itm}
+load inst "ACC1-2:not#221" "not(1)" "INTERFACE" -attr xrf 64623 -attr oid 1813 -attr @path {/sobel/sobel:core/ACC1-2:not#221} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#226.psp.sva(2)} -pin  "ACC1-2:not#221" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#6.itm}
+load net {ACC1-2:not#221.itm} -pin  "ACC1-2:not#221" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#221.itm}
+load inst "ACC1-2:not#223" "not(1)" "INTERFACE" -attr xrf 64624 -attr oid 1814 -attr @path {/sobel/sobel:core/ACC1-2:not#223} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#226.psp.sva(6)} -pin  "ACC1-2:not#223" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva).itm}
+load net {ACC1-2:not#223.itm} -pin  "ACC1-2:not#223" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#223.itm}
+load inst "ACC1:acc#381" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64625 -attr oid 1815 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#381} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#381" {A(0)} -attr @path {/sobel/sobel:core/conc#1041.itm}
+load net {ACC1:acc#226.psp.sva(1)} -pin  "ACC1:acc#381" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1041.itm}
+load net {ACC1-2:not#223.itm} -pin  "ACC1:acc#381" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1221.itm}
+load net {ACC1-2:not#221.itm} -pin  "ACC1:acc#381" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1221.itm}
+load net {ACC1:acc#381.itm(0)} -pin  "ACC1:acc#381" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#381.itm}
+load net {ACC1:acc#381.itm(1)} -pin  "ACC1:acc#381" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#381.itm}
+load net {ACC1:acc#381.itm(2)} -pin  "ACC1:acc#381" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#381.itm}
+load inst "ACC1-2:not#224" "not(1)" "INTERFACE" -attr xrf 64626 -attr oid 1816 -attr @path {/sobel/sobel:core/ACC1-2:not#224} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#226.psp.sva(8)} -pin  "ACC1-2:not#224" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#1.itm}
+load net {ACC1-2:not#224.itm} -pin  "ACC1-2:not#224" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#224.itm}
+load inst "ACC1:acc#383" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 64627 -attr oid 1817 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#383} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#383" {A(0)} -attr @path {/sobel/sobel:core/conc#1040.itm}
+load net {ACC1-2:not#220.itm} -pin  "ACC1:acc#383" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1040.itm}
+load net {GND} -pin  "ACC1:acc#383" {A(2)} -attr @path {/sobel/sobel:core/conc#1040.itm}
+load net {PWR} -pin  "ACC1:acc#383" {A(3)} -attr @path {/sobel/sobel:core/conc#1040.itm}
+load net {ACC1-2:not#224.itm} -pin  "ACC1:acc#383" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1225.itm}
+load net {ACC1:acc#381.itm(1)} -pin  "ACC1:acc#383" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1225.itm}
+load net {ACC1:acc#381.itm(2)} -pin  "ACC1:acc#383" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1225.itm}
+load net {ACC1:acc#383.itm(0)} -pin  "ACC1:acc#383" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#383.itm}
+load net {ACC1:acc#383.itm(1)} -pin  "ACC1:acc#383" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#383.itm}
+load net {ACC1:acc#383.itm(2)} -pin  "ACC1:acc#383" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#383.itm}
+load net {ACC1:acc#383.itm(3)} -pin  "ACC1:acc#383" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#383.itm}
+load inst "ACC1-2:not#222" "not(1)" "INTERFACE" -attr xrf 64628 -attr oid 1818 -attr @path {/sobel/sobel:core/ACC1-2:not#222} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#226.psp.sva(4)} -pin  "ACC1-2:not#222" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#4.itm}
+load net {ACC1-2:not#222.itm} -pin  "ACC1-2:not#222" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#222.itm}
+load inst "ACC1:acc#380" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64629 -attr oid 1819 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#380} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#380" {A(0)} -attr @path {/sobel/sobel:core/conc#1043.itm}
+load net {ACC1:acc#226.psp.sva(3)} -pin  "ACC1:acc#380" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1043.itm}
+load net {ACC1:acc#226.psp.sva(5)} -pin  "ACC1:acc#380" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1219.itm}
+load net {ACC1-2:not#222.itm} -pin  "ACC1:acc#380" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1219.itm}
+load net {ACC1:acc#380.itm(0)} -pin  "ACC1:acc#380" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#380.itm}
+load net {ACC1:acc#380.itm(1)} -pin  "ACC1:acc#380" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#380.itm}
+load net {ACC1:acc#380.itm(2)} -pin  "ACC1:acc#380" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#380.itm}
+load inst "ACC1-2:not#225" "not(2)" "INTERFACE" -attr xrf 64630 -attr oid 1820 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#225} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#226.psp.sva(10)} -pin  "ACC1-2:not#225" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#12.itm}
+load net {ACC1:acc#226.psp.sva(11)} -pin  "ACC1-2:not#225" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#226.psp.sva)#12.itm}
+load net {ACC1-2:not#225.itm(0)} -pin  "ACC1-2:not#225" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#225.itm}
+load net {ACC1-2:not#225.itm(1)} -pin  "ACC1-2:not#225" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#225.itm}
+load inst "ACC1:acc#382" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 64631 -attr oid 1821 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#382" {A(0)} -attr @path {/sobel/sobel:core/conc#1042.itm}
+load net {ACC1:acc#380.itm(1)} -pin  "ACC1:acc#382" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1042.itm}
+load net {ACC1:acc#380.itm(2)} -pin  "ACC1:acc#382" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1042.itm}
+load net {ACC1:acc#226.psp.sva(7)} -pin  "ACC1:acc#382" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1223.itm}
+load net {ACC1-2:not#225.itm(0)} -pin  "ACC1:acc#382" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1223.itm}
+load net {ACC1-2:not#225.itm(1)} -pin  "ACC1:acc#382" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1223.itm}
+load net {ACC1:acc#382.itm(0)} -pin  "ACC1:acc#382" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382.itm}
+load net {ACC1:acc#382.itm(1)} -pin  "ACC1:acc#382" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382.itm}
+load net {ACC1:acc#382.itm(2)} -pin  "ACC1:acc#382" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382.itm}
+load net {ACC1:acc#382.itm(3)} -pin  "ACC1:acc#382" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382.itm}
+load net {ACC1:acc#382.itm(4)} -pin  "ACC1:acc#382" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#382.itm}
+load inst "ACC1:acc#384" "add(4,1,5,-1,5)" "INTERFACE" -attr xrf 64632 -attr oid 1822 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "ACC1:acc#384" {A(0)} -attr @path {/sobel/sobel:core/conc#1039.itm}
+load net {ACC1:acc#383.itm(1)} -pin  "ACC1:acc#384" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1039.itm}
+load net {ACC1:acc#383.itm(2)} -pin  "ACC1:acc#384" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1039.itm}
+load net {ACC1:acc#383.itm(3)} -pin  "ACC1:acc#384" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1039.itm}
+load net {ACC1:acc#226.psp.sva(9)} -pin  "ACC1:acc#384" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1227.itm}
+load net {ACC1:acc#382.itm(1)} -pin  "ACC1:acc#384" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1227.itm}
+load net {ACC1:acc#382.itm(2)} -pin  "ACC1:acc#384" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1227.itm}
+load net {ACC1:acc#382.itm(3)} -pin  "ACC1:acc#384" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1227.itm}
+load net {ACC1:acc#382.itm(4)} -pin  "ACC1:acc#384" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1227.itm}
+load net {ACC1:acc#384.itm(0)} -pin  "ACC1:acc#384" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384.itm}
+load net {ACC1:acc#384.itm(1)} -pin  "ACC1:acc#384" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384.itm}
+load net {ACC1:acc#384.itm(2)} -pin  "ACC1:acc#384" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384.itm}
+load net {ACC1:acc#384.itm(3)} -pin  "ACC1:acc#384" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384.itm}
+load net {ACC1:acc#384.itm(4)} -pin  "ACC1:acc#384" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#384.itm}
+load inst "ACC1-3:not#309" "not(1)" "INTERFACE" -attr xrf 64633 -attr oid 1823 -attr @path {/sobel/sobel:core/ACC1-3:not#309} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(11)} -pin  "ACC1-3:not#309" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#24.itm}
+load net {ACC1-3:not#309.itm} -pin  "ACC1-3:not#309" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#309.itm}
+load inst "ACC1-3:not#238" "not(1)" "INTERFACE" -attr xrf 64634 -attr oid 1824 -attr @path {/sobel/sobel:core/ACC1-3:not#238} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(1)} -pin  "ACC1-3:not#238" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#14.itm}
+load net {ACC1-3:not#238.itm} -pin  "ACC1-3:not#238" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#238.itm}
+load inst "ACC1:acc#401" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 64635 -attr oid 1825 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#401} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#401" {A(0)} -attr @path {/sobel/sobel:core/conc#1045.itm}
+load net {ACC1-3:not#309.itm} -pin  "ACC1:acc#401" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1045.itm}
+load net {ACC1:acc#227.psp.sva(8)} -pin  "ACC1:acc#401" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1259.itm}
+load net {ACC1-3:not#238.itm} -pin  "ACC1:acc#401" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1259.itm}
+load net {ACC1:acc#401.itm(0)} -pin  "ACC1:acc#401" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#401.itm}
+load net {ACC1:acc#401.itm(1)} -pin  "ACC1:acc#401" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#401.itm}
+load net {ACC1:acc#401.itm(2)} -pin  "ACC1:acc#401" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#401.itm}
+load net {ACC1:acc#401.itm(3)} -pin  "ACC1:acc#401" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#401.itm}
+load inst "ACC1:acc#403" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 64636 -attr oid 1826 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#403" {A(0)} -attr @path {/sobel/sobel:core/conc#1044.itm}
+load net {ACC1:acc#401.itm(1)} -pin  "ACC1:acc#403" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1044.itm}
+load net {ACC1:acc#401.itm(2)} -pin  "ACC1:acc#403" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1044.itm}
+load net {ACC1:acc#401.itm(3)} -pin  "ACC1:acc#403" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1044.itm}
+load net {ACC1:acc#227.psp.sva(10)} -pin  "ACC1:acc#403" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1046.itm}
+load net {ACC1:acc#227.psp.sva(0)} -pin  "ACC1:acc#403" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1046.itm}
+load net {GND} -pin  "ACC1:acc#403" {B(2)} -attr @path {/sobel/sobel:core/conc#1046.itm}
+load net {PWR} -pin  "ACC1:acc#403" {B(3)} -attr @path {/sobel/sobel:core/conc#1046.itm}
+load net {ACC1:acc#403.itm(0)} -pin  "ACC1:acc#403" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403.itm}
+load net {ACC1:acc#403.itm(1)} -pin  "ACC1:acc#403" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403.itm}
+load net {ACC1:acc#403.itm(2)} -pin  "ACC1:acc#403" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403.itm}
+load net {ACC1:acc#403.itm(3)} -pin  "ACC1:acc#403" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403.itm}
+load net {ACC1:acc#403.itm(4)} -pin  "ACC1:acc#403" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#403.itm}
+load inst "ACC1-3:not#239" "not(1)" "INTERFACE" -attr xrf 64637 -attr oid 1827 -attr @path {/sobel/sobel:core/ACC1-3:not#239} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(3)} -pin  "ACC1-3:not#239" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#16.itm}
+load net {ACC1-3:not#239.itm} -pin  "ACC1-3:not#239" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#239.itm}
+load inst "ACC1-3:not#241" "not(1)" "INTERFACE" -attr xrf 64638 -attr oid 1828 -attr @path {/sobel/sobel:core/ACC1-3:not#241} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(7)} -pin  "ACC1-3:not#241" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#5.itm}
+load net {ACC1-3:not#241.itm} -pin  "ACC1-3:not#241" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#241.itm}
+load inst "ACC1:acc#400" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64639 -attr oid 1829 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#400} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#400" {A(0)} -attr @path {/sobel/sobel:core/conc#1048.itm}
+load net {ACC1:acc#227.psp.sva(2)} -pin  "ACC1:acc#400" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1048.itm}
+load net {ACC1-3:not#241.itm} -pin  "ACC1:acc#400" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1257.itm}
+load net {ACC1-3:not#239.itm} -pin  "ACC1:acc#400" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1257.itm}
+load net {ACC1:acc#400.itm(0)} -pin  "ACC1:acc#400" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#400.itm}
+load net {ACC1:acc#400.itm(1)} -pin  "ACC1:acc#400" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#400.itm}
+load net {ACC1:acc#400.itm(2)} -pin  "ACC1:acc#400" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#400.itm}
+load inst "ACC1-3:not#240" "not(1)" "INTERFACE" -attr xrf 64640 -attr oid 1830 -attr @path {/sobel/sobel:core/ACC1-3:not#240} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(5)} -pin  "ACC1-3:not#240" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#1.itm}
+load net {ACC1-3:not#240.itm} -pin  "ACC1-3:not#240" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#240.itm}
+load inst "ACC1:acc#399" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64641 -attr oid 1831 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#399} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#399" {A(0)} -attr @path {/sobel/sobel:core/conc#1049.itm}
+load net {ACC1:acc#227.psp.sva(4)} -pin  "ACC1:acc#399" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1049.itm}
+load net {ACC1:acc#227.psp.sva(6)} -pin  "ACC1:acc#399" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1255.itm}
+load net {ACC1-3:not#240.itm} -pin  "ACC1:acc#399" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1255.itm}
+load net {ACC1:acc#399.itm(0)} -pin  "ACC1:acc#399" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#399.itm}
+load net {ACC1:acc#399.itm(1)} -pin  "ACC1:acc#399" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#399.itm}
+load net {ACC1:acc#399.itm(2)} -pin  "ACC1:acc#399" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#399.itm}
+load inst "ACC1-3:not#242" "not(1)" "INTERFACE" -attr xrf 64642 -attr oid 1832 -attr @path {/sobel/sobel:core/ACC1-3:not#242} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#227.psp.sva(9)} -pin  "ACC1-3:not#242" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#227.psp.sva)#4.itm}
+load net {ACC1-3:not#242.itm} -pin  "ACC1-3:not#242" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#242.itm}
+load inst "ACC1:acc#402" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64643 -attr oid 1833 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#402} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#402" {A(0)} -attr @path {/sobel/sobel:core/conc#1047.itm}
+load net {ACC1:acc#400.itm(1)} -pin  "ACC1:acc#402" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1047.itm}
+load net {ACC1:acc#400.itm(2)} -pin  "ACC1:acc#402" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1047.itm}
+load net {ACC1-3:not#242.itm} -pin  "ACC1:acc#402" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1261.itm}
+load net {ACC1:acc#399.itm(1)} -pin  "ACC1:acc#402" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1261.itm}
+load net {ACC1:acc#399.itm(2)} -pin  "ACC1:acc#402" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1261.itm}
+load net {ACC1:acc#402.itm(0)} -pin  "ACC1:acc#402" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#402.itm}
+load net {ACC1:acc#402.itm(1)} -pin  "ACC1:acc#402" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#402.itm}
+load net {ACC1:acc#402.itm(2)} -pin  "ACC1:acc#402" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#402.itm}
+load net {ACC1:acc#402.itm(3)} -pin  "ACC1:acc#402" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#402.itm}
+load inst "ACC1-3:acc#212" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 64644 -attr oid 1834 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#212} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#403.itm(1)} -pin  "ACC1-3:acc#212" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#403.itm(2)} -pin  "ACC1-3:acc#212" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#403.itm(3)} -pin  "ACC1-3:acc#212" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#403.itm(4)} -pin  "ACC1-3:acc#212" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#402.itm(1)} -pin  "ACC1-3:acc#212" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#402.itm(2)} -pin  "ACC1-3:acc#212" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#402.itm(3)} -pin  "ACC1-3:acc#212" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1-3:acc#212.psp.sva(0)} -pin  "ACC1-3:acc#212" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#212.psp.sva}
+load net {ACC1-3:acc#212.psp.sva(1)} -pin  "ACC1-3:acc#212" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#212.psp.sva}
+load net {ACC1-3:acc#212.psp.sva(2)} -pin  "ACC1-3:acc#212" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#212.psp.sva}
+load net {ACC1-3:acc#212.psp.sva(3)} -pin  "ACC1-3:acc#212" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#212.psp.sva}
+load inst "ACC1-3:not#297" "not(2)" "INTERFACE" -attr xrf 64645 -attr oid 1835 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#297} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#222.psp.sva(1)} -pin  "ACC1-3:not#297" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp.sva).itm}
+load net {ACC1:acc#222.psp.sva(2)} -pin  "ACC1-3:not#297" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#222.psp.sva).itm}
+load net {ACC1-3:not#297.itm(0)} -pin  "ACC1-3:not#297" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#297.itm}
+load net {ACC1-3:not#297.itm(1)} -pin  "ACC1-3:not#297" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#297.itm}
+load inst "ACC1:acc#414" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 64646 -attr oid 1836 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#414} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#414" {A(0)} -attr @path {/sobel/sobel:core/conc#1050.itm}
+load net {ACC1-3:not#297.itm(0)} -pin  "ACC1:acc#414" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1050.itm}
+load net {ACC1-3:not#297.itm(1)} -pin  "ACC1:acc#414" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1050.itm}
+load net {PWR} -pin  "ACC1:acc#414" {B(0)} -attr @path {/sobel/sobel:core/conc#1051.itm}
+load net {ACC1:acc#222.psp.sva(0)} -pin  "ACC1:acc#414" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1051.itm}
+load net {ACC1:acc#414.itm(0)} -pin  "ACC1:acc#414" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#414.itm}
+load net {ACC1:acc#414.itm(1)} -pin  "ACC1:acc#414" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#414.itm}
+load net {ACC1:acc#414.itm(2)} -pin  "ACC1:acc#414" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#414.itm}
+load net {ACC1:acc#414.itm(3)} -pin  "ACC1:acc#414" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#414.itm}
+load inst "ACC1-2:not#295" "not(2)" "INTERFACE" -attr xrf 64647 -attr oid 1837 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#295} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#221.psp#2.sva(1)} -pin  "ACC1-2:not#295" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp#2.sva).itm}
+load net {ACC1:acc#221.psp#2.sva(2)} -pin  "ACC1-2:not#295" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp#2.sva).itm}
+load net {ACC1-2:not#295.itm(0)} -pin  "ACC1-2:not#295" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#295.itm}
+load net {ACC1-2:not#295.itm(1)} -pin  "ACC1-2:not#295" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#295.itm}
+load inst "ACC1:acc#377" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 64648 -attr oid 1838 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#377} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#377" {A(0)} -attr @path {/sobel/sobel:core/conc#1052.itm}
+load net {ACC1-2:not#295.itm(0)} -pin  "ACC1:acc#377" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1052.itm}
+load net {ACC1-2:not#295.itm(1)} -pin  "ACC1:acc#377" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1052.itm}
+load net {PWR} -pin  "ACC1:acc#377" {B(0)} -attr @path {/sobel/sobel:core/conc#1053.itm}
+load net {ACC1:acc#221.psp#2.sva(0)} -pin  "ACC1:acc#377" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1053.itm}
+load net {ACC1:acc#377.itm(0)} -pin  "ACC1:acc#377" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#377.itm}
+load net {ACC1:acc#377.itm(1)} -pin  "ACC1:acc#377" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#377.itm}
+load net {ACC1:acc#377.itm(2)} -pin  "ACC1:acc#377" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#377.itm}
+load net {ACC1:acc#377.itm(3)} -pin  "ACC1:acc#377" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#377.itm}
+load inst "ACC1-1:not#247" "not(1)" "INTERFACE" -attr xrf 64649 -attr oid 1839 -attr @path {/sobel/sobel:core/ACC1-1:not#247} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp#1.sva(0)} -pin  "ACC1-1:not#247" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#7.itm}
+load net {ACC1-1:not#247.itm} -pin  "ACC1-1:not#247" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#247.itm}
+load inst "ACC1-1:not#248" "not(1)" "INTERFACE" -attr xrf 64650 -attr oid 1840 -attr @path {/sobel/sobel:core/ACC1-1:not#248} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp#1.sva(2)} -pin  "ACC1-1:not#248" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#6.itm}
+load net {ACC1-1:not#248.itm} -pin  "ACC1-1:not#248" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#248.itm}
+load inst "ACC1-1:not#250" "not(1)" "INTERFACE" -attr xrf 64651 -attr oid 1841 -attr @path {/sobel/sobel:core/ACC1-1:not#250} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp#1.sva(6)} -pin  "ACC1-1:not#250" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#1.itm}
+load net {ACC1-1:not#250.itm} -pin  "ACC1-1:not#250" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#250.itm}
+load inst "ACC1:acc#343" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64652 -attr oid 1842 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#343} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#343" {A(0)} -attr @path {/sobel/sobel:core/conc#1056.itm}
+load net {ACC1:acc#224.psp#1.sva(1)} -pin  "ACC1:acc#343" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1056.itm}
+load net {ACC1-1:not#250.itm} -pin  "ACC1:acc#343" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1149.itm}
+load net {ACC1-1:not#248.itm} -pin  "ACC1:acc#343" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1149.itm}
+load net {ACC1:acc#343.itm(0)} -pin  "ACC1:acc#343" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#343.itm}
+load net {ACC1:acc#343.itm(1)} -pin  "ACC1:acc#343" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#343.itm}
+load net {ACC1:acc#343.itm(2)} -pin  "ACC1:acc#343" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#343.itm}
+load inst "ACC1-1:not#251" "not(1)" "INTERFACE" -attr xrf 64653 -attr oid 1843 -attr @path {/sobel/sobel:core/ACC1-1:not#251} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp#1.sva(8)} -pin  "ACC1-1:not#251" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#2.itm}
+load net {ACC1-1:not#251.itm} -pin  "ACC1-1:not#251" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#251.itm}
+load inst "ACC1:acc#345" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 64654 -attr oid 1844 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#345} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#345" {A(0)} -attr @path {/sobel/sobel:core/conc#1055.itm}
+load net {ACC1-1:not#247.itm} -pin  "ACC1:acc#345" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1055.itm}
+load net {GND} -pin  "ACC1:acc#345" {A(2)} -attr @path {/sobel/sobel:core/conc#1055.itm}
+load net {PWR} -pin  "ACC1:acc#345" {A(3)} -attr @path {/sobel/sobel:core/conc#1055.itm}
+load net {ACC1-1:not#251.itm} -pin  "ACC1:acc#345" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1153.itm}
+load net {ACC1:acc#343.itm(1)} -pin  "ACC1:acc#345" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1153.itm}
+load net {ACC1:acc#343.itm(2)} -pin  "ACC1:acc#345" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1153.itm}
+load net {ACC1:acc#345.itm(0)} -pin  "ACC1:acc#345" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#345.itm}
+load net {ACC1:acc#345.itm(1)} -pin  "ACC1:acc#345" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#345.itm}
+load net {ACC1:acc#345.itm(2)} -pin  "ACC1:acc#345" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#345.itm}
+load net {ACC1:acc#345.itm(3)} -pin  "ACC1:acc#345" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#345.itm}
+load inst "ACC1-1:not#249" "not(1)" "INTERFACE" -attr xrf 64655 -attr oid 1845 -attr @path {/sobel/sobel:core/ACC1-1:not#249} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#224.psp#1.sva(4)} -pin  "ACC1-1:not#249" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#4.itm}
+load net {ACC1-1:not#249.itm} -pin  "ACC1-1:not#249" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#249.itm}
+load inst "ACC1:acc#342" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64656 -attr oid 1846 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#342" {A(0)} -attr @path {/sobel/sobel:core/conc#1058.itm}
+load net {ACC1:acc#224.psp#1.sva(3)} -pin  "ACC1:acc#342" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1058.itm}
+load net {ACC1:acc#224.psp#1.sva(5)} -pin  "ACC1:acc#342" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1147.itm}
+load net {ACC1-1:not#249.itm} -pin  "ACC1:acc#342" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1147.itm}
+load net {ACC1:acc#342.itm(0)} -pin  "ACC1:acc#342" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(1)} -pin  "ACC1:acc#342" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(2)} -pin  "ACC1:acc#342" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load inst "ACC1-1:not#252" "not(2)" "INTERFACE" -attr xrf 64657 -attr oid 1847 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#252} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#224.psp#1.sva(10)} -pin  "ACC1-1:not#252" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#12.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1-1:not#252" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva)#12.itm}
+load net {ACC1-1:not#252.itm(0)} -pin  "ACC1-1:not#252" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#252.itm}
+load net {ACC1-1:not#252.itm(1)} -pin  "ACC1-1:not#252" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#252.itm}
+load inst "ACC1:acc#344" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 64658 -attr oid 1848 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#344" {A(0)} -attr @path {/sobel/sobel:core/conc#1057.itm}
+load net {ACC1:acc#342.itm(1)} -pin  "ACC1:acc#344" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1057.itm}
+load net {ACC1:acc#342.itm(2)} -pin  "ACC1:acc#344" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1057.itm}
+load net {ACC1:acc#224.psp#1.sva(7)} -pin  "ACC1:acc#344" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1151.itm}
+load net {ACC1-1:not#252.itm(0)} -pin  "ACC1:acc#344" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1151.itm}
+load net {ACC1-1:not#252.itm(1)} -pin  "ACC1:acc#344" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1151.itm}
+load net {ACC1:acc#344.itm(0)} -pin  "ACC1:acc#344" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:acc#344.itm(1)} -pin  "ACC1:acc#344" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:acc#344.itm(2)} -pin  "ACC1:acc#344" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:acc#344.itm(3)} -pin  "ACC1:acc#344" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:acc#344.itm(4)} -pin  "ACC1:acc#344" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load inst "ACC1:acc#346" "add(4,1,5,-1,5)" "INTERFACE" -attr xrf 64659 -attr oid 1849 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "ACC1:acc#346" {A(0)} -attr @path {/sobel/sobel:core/conc#1054.itm}
+load net {ACC1:acc#345.itm(1)} -pin  "ACC1:acc#346" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1054.itm}
+load net {ACC1:acc#345.itm(2)} -pin  "ACC1:acc#346" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1054.itm}
+load net {ACC1:acc#345.itm(3)} -pin  "ACC1:acc#346" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1054.itm}
+load net {ACC1:acc#224.psp#1.sva(9)} -pin  "ACC1:acc#346" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1155.itm}
+load net {ACC1:acc#344.itm(1)} -pin  "ACC1:acc#346" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1155.itm}
+load net {ACC1:acc#344.itm(2)} -pin  "ACC1:acc#346" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1155.itm}
+load net {ACC1:acc#344.itm(3)} -pin  "ACC1:acc#346" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1155.itm}
+load net {ACC1:acc#344.itm(4)} -pin  "ACC1:acc#346" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1155.itm}
+load net {ACC1:acc#346.itm(0)} -pin  "ACC1:acc#346" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:acc#346.itm(1)} -pin  "ACC1:acc#346" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:acc#346.itm(2)} -pin  "ACC1:acc#346" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:acc#346.itm(3)} -pin  "ACC1:acc#346" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:acc#346.itm(4)} -pin  "ACC1:acc#346" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load inst "ACC1-2:not#291" "not(2)" "INTERFACE" -attr xrf 64660 -attr oid 1850 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#291} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#219.psp#2.sva(1)} -pin  "ACC1-2:not#291" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#2.sva).itm}
+load net {ACC1:acc#219.psp#2.sva(2)} -pin  "ACC1-2:not#291" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#219.psp#2.sva).itm}
+load net {ACC1-2:not#291.itm(0)} -pin  "ACC1-2:not#291" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#291.itm}
+load net {ACC1-2:not#291.itm(1)} -pin  "ACC1-2:not#291" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:not#291.itm}
+load inst "ACC1:acc#386" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 64661 -attr oid 1851 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#386} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#386" {A(0)} -attr @path {/sobel/sobel:core/conc#1059.itm}
+load net {ACC1-2:not#291.itm(0)} -pin  "ACC1:acc#386" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1059.itm}
+load net {ACC1-2:not#291.itm(1)} -pin  "ACC1:acc#386" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1059.itm}
+load net {PWR} -pin  "ACC1:acc#386" {B(0)} -attr @path {/sobel/sobel:core/conc#1060.itm}
+load net {ACC1:acc#219.psp#2.sva(0)} -pin  "ACC1:acc#386" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1060.itm}
+load net {ACC1:acc#386.itm(0)} -pin  "ACC1:acc#386" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#386.itm}
+load net {ACC1:acc#386.itm(1)} -pin  "ACC1:acc#386" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#386.itm}
+load net {ACC1:acc#386.itm(2)} -pin  "ACC1:acc#386" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#386.itm}
+load net {ACC1:acc#386.itm(3)} -pin  "ACC1:acc#386" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#386.itm}
+load inst "ACC1-3:not#295" "not(2)" "INTERFACE" -attr xrf 64662 -attr oid 1852 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#295} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#221.psp.sva(1)} -pin  "ACC1-3:not#295" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp.sva).itm}
+load net {ACC1:acc#221.psp.sva(2)} -pin  "ACC1-3:not#295" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#221.psp.sva).itm}
+load net {ACC1-3:not#295.itm(0)} -pin  "ACC1-3:not#295" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#295.itm}
+load net {ACC1-3:not#295.itm(1)} -pin  "ACC1-3:not#295" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#295.itm}
+load inst "ACC1:acc#405" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 64663 -attr oid 1853 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#405} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#405" {A(0)} -attr @path {/sobel/sobel:core/conc#1061.itm}
+load net {ACC1-3:not#295.itm(0)} -pin  "ACC1:acc#405" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1061.itm}
+load net {ACC1-3:not#295.itm(1)} -pin  "ACC1:acc#405" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1061.itm}
+load net {PWR} -pin  "ACC1:acc#405" {B(0)} -attr @path {/sobel/sobel:core/conc#1062.itm}
+load net {ACC1:acc#221.psp.sva(0)} -pin  "ACC1:acc#405" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1062.itm}
+load net {ACC1:acc#405.itm(0)} -pin  "ACC1:acc#405" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#405.itm}
+load net {ACC1:acc#405.itm(1)} -pin  "ACC1:acc#405" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#405.itm}
+load net {ACC1:acc#405.itm(2)} -pin  "ACC1:acc#405" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#405.itm}
+load net {ACC1:acc#405.itm(3)} -pin  "ACC1:acc#405" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#405.itm}
+load inst "ACC1-3:not#277" "not(1)" "INTERFACE" -attr xrf 64664 -attr oid 1854 -attr @path {/sobel/sobel:core/ACC1-3:not#277} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-3:acc#212.psp.sva(1)} -pin  "ACC1-3:not#277" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-3:acc#212.psp.sva)#4.itm}
+load net {ACC1-3:not#277.itm} -pin  "ACC1-3:not#277" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#277.itm}
+load inst "ACC1:acc#404" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64665 -attr oid 1855 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#404} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#404" {A(0)} -attr @path {/sobel/sobel:core/conc#1063.itm}
+load net {ACC1-3:acc#212.psp.sva(0)} -pin  "ACC1:acc#404" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1063.itm}
+load net {ACC1-3:acc#212.psp.sva(2)} -pin  "ACC1:acc#404" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1265.itm}
+load net {ACC1-3:not#277.itm} -pin  "ACC1:acc#404" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1265.itm}
+load net {ACC1:acc#404.itm(0)} -pin  "ACC1:acc#404" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#404.itm}
+load net {ACC1:acc#404.itm(1)} -pin  "ACC1:acc#404" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#404.itm}
+load net {ACC1:acc#404.itm(2)} -pin  "ACC1:acc#404" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#404.itm}
+load inst "ACC1:not#320" "not(1)" "INTERFACE" -attr xrf 64666 -attr oid 1856 -attr @path {/sobel/sobel:core/ACC1:not#320} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-3:acc#212.psp.sva(3)} -pin  "ACC1:not#320" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-3:acc#212.psp.sva)#5.itm}
+load net {ACC1:not#320.itm} -pin  "ACC1:not#320" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#320.itm}
+load inst "ACC1-3:acc#221" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 64667 -attr oid 1857 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#221} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#404.itm(1)} -pin  "ACC1-3:acc#221" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:acc#404.itm(2)} -pin  "ACC1-3:acc#221" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:not#320.itm} -pin  "ACC1-3:acc#221" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#320.itm}
+load net {ACC1:acc#221.psp.sva(0)} -pin  "ACC1-3:acc#221" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp.sva}
+load net {ACC1:acc#221.psp.sva(1)} -pin  "ACC1-3:acc#221" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp.sva}
+load net {ACC1:acc#221.psp.sva(2)} -pin  "ACC1-3:acc#221" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp.sva}
+load inst "ACC1-2:not#277" "not(1)" "INTERFACE" -attr xrf 64668 -attr oid 1858 -attr @path {/sobel/sobel:core/ACC1-2:not#277} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#375.itm(2)} -pin  "ACC1-2:not#277" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-2:acc#212.psp.sva)#4.itm}
+load net {ACC1-2:not#277.itm} -pin  "ACC1-2:not#277" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#277.itm}
+load inst "ACC1:acc#376" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64669 -attr oid 1859 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#376} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#376" {A(0)} -attr @path {/sobel/sobel:core/conc#1064.itm}
+load net {ACC1:acc#375.itm(1)} -pin  "ACC1:acc#376" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1064.itm}
+load net {ACC1:acc#375.itm(3)} -pin  "ACC1:acc#376" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1211.itm}
+load net {ACC1-2:not#277.itm} -pin  "ACC1:acc#376" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1211.itm}
+load net {ACC1:acc#376.itm(0)} -pin  "ACC1:acc#376" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#376.itm}
+load net {ACC1:acc#376.itm(1)} -pin  "ACC1:acc#376" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#376.itm}
+load net {ACC1:acc#376.itm(2)} -pin  "ACC1:acc#376" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#376.itm}
+load inst "ACC1:not#318" "not(1)" "INTERFACE" -attr xrf 64670 -attr oid 1860 -attr @path {/sobel/sobel:core/ACC1:not#318} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#375.itm(4)} -pin  "ACC1:not#318" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-2:acc#212.psp.sva)#5.itm}
+load net {ACC1:not#318.itm} -pin  "ACC1:not#318" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#318.itm}
+load inst "ACC1-2:acc#221" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 64671 -attr oid 1861 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:acc#221} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#376.itm(1)} -pin  "ACC1-2:acc#221" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#376.itm(2)} -pin  "ACC1-2:acc#221" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:not#318.itm} -pin  "ACC1-2:acc#221" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#318.itm}
+load net {ACC1:acc#221.psp#2.sva(0)} -pin  "ACC1-2:acc#221" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp#2.sva}
+load net {ACC1:acc#221.psp#2.sva(1)} -pin  "ACC1-2:acc#221" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp#2.sva}
+load net {ACC1:acc#221.psp#2.sva(2)} -pin  "ACC1-2:acc#221" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.psp#2.sva}
+load inst "ACC1-2:not#269" "not(1)" "INTERFACE" -attr xrf 64672 -attr oid 1862 -attr @path {/sobel/sobel:core/ACC1-2:not#269} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#384.itm(2)} -pin  "ACC1-2:not#269" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-2:acc#208.psp.sva)#4.itm}
+load net {ACC1-2:not#269.itm} -pin  "ACC1-2:not#269" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#269.itm}
+load inst "ACC1:acc#385" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64673 -attr oid 1863 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#385} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#385" {A(0)} -attr @path {/sobel/sobel:core/conc#1065.itm}
+load net {ACC1:acc#384.itm(1)} -pin  "ACC1:acc#385" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1065.itm}
+load net {ACC1:acc#384.itm(3)} -pin  "ACC1:acc#385" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1229.itm}
+load net {ACC1-2:not#269.itm} -pin  "ACC1:acc#385" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1229.itm}
+load net {ACC1:acc#385.itm(0)} -pin  "ACC1:acc#385" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#385.itm}
+load net {ACC1:acc#385.itm(1)} -pin  "ACC1:acc#385" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#385.itm}
+load net {ACC1:acc#385.itm(2)} -pin  "ACC1:acc#385" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#385.itm}
+load inst "ACC1:not#319" "not(1)" "INTERFACE" -attr xrf 64674 -attr oid 1864 -attr @path {/sobel/sobel:core/ACC1:not#319} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#384.itm(4)} -pin  "ACC1:not#319" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-2:acc#208.psp.sva)#5.itm}
+load net {ACC1:not#319.itm} -pin  "ACC1:not#319" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#319.itm}
+load inst "ACC1-2:acc#219" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 64675 -attr oid 1865 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:acc#219} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#385.itm(1)} -pin  "ACC1-2:acc#219" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:acc#385.itm(2)} -pin  "ACC1-2:acc#219" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:not#319.itm} -pin  "ACC1-2:acc#219" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#319.itm}
+load net {ACC1:acc#219.psp#2.sva(0)} -pin  "ACC1-2:acc#219" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#2.sva}
+load net {ACC1:acc#219.psp#2.sva(1)} -pin  "ACC1-2:acc#219" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#2.sva}
+load net {ACC1:acc#219.psp#2.sva(2)} -pin  "ACC1-2:acc#219" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#2.sva}
+load inst "ACC1-1:not#281" "not(1)" "INTERFACE" -attr xrf 64676 -attr oid 1866 -attr @path {/sobel/sobel:core/ACC1-1:not#281} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#346.itm(2)} -pin  "ACC1-1:not#281" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#214.psp#2.sva)#4.itm}
+load net {ACC1-1:not#281.itm} -pin  "ACC1-1:not#281" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#281.itm}
+load inst "ACC1:acc#347" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64677 -attr oid 1867 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#347" {A(0)} -attr @path {/sobel/sobel:core/conc#1066.itm}
+load net {ACC1:acc#346.itm(1)} -pin  "ACC1:acc#347" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1066.itm}
+load net {ACC1:acc#346.itm(3)} -pin  "ACC1:acc#347" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1157.itm}
+load net {ACC1-1:not#281.itm} -pin  "ACC1:acc#347" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1157.itm}
+load net {ACC1:acc#347.itm(0)} -pin  "ACC1:acc#347" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load net {ACC1:acc#347.itm(1)} -pin  "ACC1:acc#347" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load net {ACC1:acc#347.itm(2)} -pin  "ACC1:acc#347" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load inst "ACC1-1:not#303" "not(1)" "INTERFACE" -attr xrf 64678 -attr oid 1868 -attr @path {/sobel/sobel:core/ACC1-1:not#303} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#346.itm(4)} -pin  "ACC1-1:not#303" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#214.psp#2.sva)#5.itm}
+load net {ACC1-1:not#303.itm} -pin  "ACC1-1:not#303" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#303.itm}
+load inst "ACC1-1:acc#225" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 64679 -attr oid 1869 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#225} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#347.itm(1)} -pin  "ACC1-1:acc#225" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#347.itm(2)} -pin  "ACC1-1:acc#225" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1-1:not#303.itm} -pin  "ACC1-1:acc#225" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#303.itm}
+load net {ACC1:acc#222.psp#1.sva(0)} -pin  "ACC1-1:acc#225" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp#1.sva}
+load net {ACC1:acc#222.psp#1.sva(1)} -pin  "ACC1-1:acc#225" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp#1.sva}
+load net {ACC1:acc#222.psp#1.sva(2)} -pin  "ACC1-1:acc#225" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp#1.sva}
+load inst "ACC1-1:not#269" "not(1)" "INTERFACE" -attr xrf 64680 -attr oid 1870 -attr @path {/sobel/sobel:core/ACC1-1:not#269} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#208.psp.sva(1)} -pin  "ACC1-1:not#269" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#208.psp.sva)#4.itm}
+load net {ACC1-1:not#269.itm} -pin  "ACC1-1:not#269" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#269.itm}
+load inst "ACC1:acc#366" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64681 -attr oid 1871 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#366} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#366" {A(0)} -attr @path {/sobel/sobel:core/conc#1067.itm}
+load net {ACC1-1:acc#208.psp.sva(0)} -pin  "ACC1:acc#366" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1067.itm}
+load net {ACC1-1:acc#208.psp.sva(2)} -pin  "ACC1:acc#366" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1193.itm}
+load net {ACC1-1:not#269.itm} -pin  "ACC1:acc#366" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1193.itm}
+load net {ACC1:acc#366.itm(0)} -pin  "ACC1:acc#366" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#366.itm}
+load net {ACC1:acc#366.itm(1)} -pin  "ACC1:acc#366" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#366.itm}
+load net {ACC1:acc#366.itm(2)} -pin  "ACC1:acc#366" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#366.itm}
+load inst "ACC1:not#317" "not(1)" "INTERFACE" -attr xrf 64682 -attr oid 1872 -attr @path {/sobel/sobel:core/ACC1:not#317} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1-1:acc#208.psp.sva(3)} -pin  "ACC1:not#317" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1-1:acc#208.psp.sva)#5.itm}
+load net {ACC1:not#317.itm} -pin  "ACC1:not#317" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#317.itm}
+load inst "ACC1-1:acc#219" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 64683 -attr oid 1873 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#219} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#366.itm(1)} -pin  "ACC1-1:acc#219" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#42.itm}
+load net {ACC1:acc#366.itm(2)} -pin  "ACC1-1:acc#219" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#42.itm}
+load net {ACC1:not#317.itm} -pin  "ACC1-1:acc#219" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#317.itm}
+load net {ACC1:acc#219.psp#1.sva(0)} -pin  "ACC1-1:acc#219" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#1.sva}
+load net {ACC1:acc#219.psp#1.sva(1)} -pin  "ACC1-1:acc#219" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#1.sva}
+load net {ACC1:acc#219.psp#1.sva(2)} -pin  "ACC1-1:acc#219" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.psp#1.sva}
+load inst "ACC1-2:not#185" "not(1)" "INTERFACE" -attr xrf 64684 -attr oid 1874 -attr @path {/sobel/sobel:core/ACC1-2:not#185} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#386.itm(2)} -pin  "ACC1-2:not#185" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#43.sva)#3.itm}
+load net {ACC1-2:not#185.itm} -pin  "ACC1-2:not#185" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#185.itm}
+load inst "ACC1-2:not#186" "not(1)" "INTERFACE" -attr xrf 64685 -attr oid 1875 -attr @path {/sobel/sobel:core/ACC1-2:not#186} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#386.itm(3)} -pin  "ACC1-2:not#186" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#43.sva).itm}
+load net {ACC1-2:not#186.itm} -pin  "ACC1-2:not#186" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#186.itm}
+load inst "ACC1:acc#387" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 64686 -attr oid 1876 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#387} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#387" {A(0)} -attr @path {/sobel/sobel:core/conc#1068.itm}
+load net {ACC1:acc#386.itm(1)} -pin  "ACC1:acc#387" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1068.itm}
+load net {PWR} -pin  "ACC1:acc#387" {A(2)} -attr @path {/sobel/sobel:core/conc#1068.itm}
+load net {ACC1-2:not#186.itm} -pin  "ACC1:acc#387" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1234.itm}
+load net {ACC1-2:not#185.itm} -pin  "ACC1:acc#387" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1234.itm}
+load net {ACC1:acc#387.itm(0)} -pin  "ACC1:acc#387" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#387.itm}
+load net {ACC1:acc#387.itm(1)} -pin  "ACC1:acc#387" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#387.itm}
+load net {ACC1:acc#387.itm(2)} -pin  "ACC1:acc#387" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#387.itm}
+load inst "ACC1-2:not#57" "not(1)" "INTERFACE" -attr xrf 64687 -attr oid 1877 -attr @path {/sobel/sobel:core/ACC1-2:not#57} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#377.itm(2)} -pin  "ACC1-2:not#57" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#31.sva)#3.itm}
+load net {ACC1-2:not#57.itm} -pin  "ACC1-2:not#57" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#57.itm}
+load inst "ACC1-2:not#58" "not(1)" "INTERFACE" -attr xrf 64688 -attr oid 1878 -attr @path {/sobel/sobel:core/ACC1-2:not#58} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#377.itm(3)} -pin  "ACC1-2:not#58" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#31.sva).itm}
+load net {ACC1-2:not#58.itm} -pin  "ACC1-2:not#58" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#58.itm}
+load inst "ACC1:acc#378" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 64689 -attr oid 1879 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#378} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#378" {A(0)} -attr @path {/sobel/sobel:core/conc#1069.itm}
+load net {ACC1:acc#377.itm(1)} -pin  "ACC1:acc#378" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1069.itm}
+load net {PWR} -pin  "ACC1:acc#378" {A(2)} -attr @path {/sobel/sobel:core/conc#1069.itm}
+load net {ACC1-2:not#58.itm} -pin  "ACC1:acc#378" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1216.itm}
+load net {ACC1-2:not#57.itm} -pin  "ACC1:acc#378" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1216.itm}
+load net {ACC1:acc#378.itm(0)} -pin  "ACC1:acc#378" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#378.itm}
+load net {ACC1:acc#378.itm(1)} -pin  "ACC1:acc#378" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#378.itm}
+load net {ACC1:acc#378.itm(2)} -pin  "ACC1:acc#378" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#378.itm}
+load inst "ACC1-3:not#89" "not(1)" "INTERFACE" -attr xrf 64690 -attr oid 1880 -attr @path {/sobel/sobel:core/ACC1-3:not#89} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#414.itm(2)} -pin  "ACC1-3:not#89" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#10.sva)#3.itm}
+load net {ACC1-3:not#89.itm} -pin  "ACC1-3:not#89" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#89.itm}
+load inst "ACC1-3:not#90" "not(1)" "INTERFACE" -attr xrf 64691 -attr oid 1881 -attr @path {/sobel/sobel:core/ACC1-3:not#90} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#414.itm(3)} -pin  "ACC1-3:not#90" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#10.sva).itm}
+load net {ACC1-3:not#90.itm} -pin  "ACC1-3:not#90" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#90.itm}
+load inst "ACC1:acc#415" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 64692 -attr oid 1882 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#415} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#415" {A(0)} -attr @path {/sobel/sobel:core/conc#1070.itm}
+load net {ACC1:acc#414.itm(1)} -pin  "ACC1:acc#415" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1070.itm}
+load net {PWR} -pin  "ACC1:acc#415" {A(2)} -attr @path {/sobel/sobel:core/conc#1070.itm}
+load net {ACC1-3:not#90.itm} -pin  "ACC1:acc#415" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1288.itm}
+load net {ACC1-3:not#89.itm} -pin  "ACC1:acc#415" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1288.itm}
+load net {ACC1:acc#415.itm(0)} -pin  "ACC1:acc#415" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#415.itm}
+load net {ACC1:acc#415.itm(1)} -pin  "ACC1:acc#415" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#415.itm}
+load net {ACC1:acc#415.itm(2)} -pin  "ACC1:acc#415" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#415.itm}
+load inst "ACC1-3:not#25" "not(1)" "INTERFACE" -attr xrf 64693 -attr oid 1883 -attr @path {/sobel/sobel:core/ACC1-3:not#25} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#395.itm(2)} -pin  "ACC1-3:not#25" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#3.itm}
+load net {ACC1-3:not#25.itm} -pin  "ACC1-3:not#25" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#25.itm}
+load inst "ACC1-3:not#26" "not(1)" "INTERFACE" -attr xrf 64694 -attr oid 1884 -attr @path {/sobel/sobel:core/ACC1-3:not#26} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#395.itm(3)} -pin  "ACC1-3:not#26" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva).itm}
+load net {ACC1-3:not#26.itm} -pin  "ACC1-3:not#26" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#26.itm}
+load inst "ACC1:acc#396" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 64695 -attr oid 1885 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#396} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#396" {A(0)} -attr @path {/sobel/sobel:core/conc#1071.itm}
+load net {ACC1:acc#395.itm(1)} -pin  "ACC1:acc#396" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1071.itm}
+load net {PWR} -pin  "ACC1:acc#396" {A(2)} -attr @path {/sobel/sobel:core/conc#1071.itm}
+load net {ACC1-3:not#26.itm} -pin  "ACC1:acc#396" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1252.itm}
+load net {ACC1-3:not#25.itm} -pin  "ACC1:acc#396" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1252.itm}
+load net {ACC1:acc#396.itm(0)} -pin  "ACC1:acc#396" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#396.itm}
+load net {ACC1:acc#396.itm(1)} -pin  "ACC1:acc#396" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#396.itm}
+load net {ACC1:acc#396.itm(2)} -pin  "ACC1:acc#396" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#396.itm}
+load inst "ACC1-3:not#311" "not(1)" "INTERFACE" -attr xrf 64696 -attr oid 1886 -attr @path {/sobel/sobel:core/ACC1-3:not#311} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:not#311" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#32.itm}
+load net {ACC1-3:not#311.itm} -pin  "ACC1-3:not#311" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#311.itm}
+load inst "ACC1-3:not#229" "not(1)" "INTERFACE" -attr xrf 64697 -attr oid 1887 -attr @path {/sobel/sobel:core/ACC1-3:not#229} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(1)} -pin  "ACC1-3:not#229" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#15.itm}
+load net {ACC1-3:not#229.itm} -pin  "ACC1-3:not#229" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#229.itm}
+load inst "ACC1:acc#391" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 64698 -attr oid 1888 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#391} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#391" {A(0)} -attr @path {/sobel/sobel:core/conc#1073.itm}
+load net {ACC1-3:not#311.itm} -pin  "ACC1:acc#391" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1073.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#391" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1241.itm}
+load net {ACC1-3:not#229.itm} -pin  "ACC1:acc#391" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1241.itm}
+load net {ACC1:acc#391.itm(0)} -pin  "ACC1:acc#391" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#391.itm}
+load net {ACC1:acc#391.itm(1)} -pin  "ACC1:acc#391" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#391.itm}
+load net {ACC1:acc#391.itm(2)} -pin  "ACC1:acc#391" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#391.itm}
+load net {ACC1:acc#391.itm(3)} -pin  "ACC1:acc#391" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#391.itm}
+load inst "ACC1:acc#393" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 64699 -attr oid 1889 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#393" {A(0)} -attr @path {/sobel/sobel:core/conc#1072.itm}
+load net {ACC1:acc#391.itm(1)} -pin  "ACC1:acc#393" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1072.itm}
+load net {ACC1:acc#391.itm(2)} -pin  "ACC1:acc#393" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1072.itm}
+load net {ACC1:acc#391.itm(3)} -pin  "ACC1:acc#393" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1072.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#393" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1074.itm}
+load net {acc.psp#1.sva(0)} -pin  "ACC1:acc#393" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1074.itm}
+load net {GND} -pin  "ACC1:acc#393" {B(2)} -attr @path {/sobel/sobel:core/conc#1074.itm}
+load net {PWR} -pin  "ACC1:acc#393" {B(3)} -attr @path {/sobel/sobel:core/conc#1074.itm}
+load net {ACC1:acc#393.itm(0)} -pin  "ACC1:acc#393" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393.itm}
+load net {ACC1:acc#393.itm(1)} -pin  "ACC1:acc#393" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393.itm}
+load net {ACC1:acc#393.itm(2)} -pin  "ACC1:acc#393" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393.itm}
+load net {ACC1:acc#393.itm(3)} -pin  "ACC1:acc#393" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393.itm}
+load net {ACC1:acc#393.itm(4)} -pin  "ACC1:acc#393" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#393.itm}
+load inst "ACC1-3:not#230" "not(1)" "INTERFACE" -attr xrf 64700 -attr oid 1890 -attr @path {/sobel/sobel:core/ACC1-3:not#230} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(3)} -pin  "ACC1-3:not#230" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#17.itm}
+load net {ACC1-3:not#230.itm} -pin  "ACC1-3:not#230" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#230.itm}
+load inst "ACC1-3:not#232" "not(1)" "INTERFACE" -attr xrf 64701 -attr oid 1891 -attr @path {/sobel/sobel:core/ACC1-3:not#232} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(7)} -pin  "ACC1-3:not#232" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#1.itm}
+load net {ACC1-3:not#232.itm} -pin  "ACC1-3:not#232" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#232.itm}
+load inst "ACC1:acc#390" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64702 -attr oid 1892 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#390} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#390" {A(0)} -attr @path {/sobel/sobel:core/conc#1076.itm}
+load net {acc.psp#1.sva(2)} -pin  "ACC1:acc#390" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1076.itm}
+load net {ACC1-3:not#232.itm} -pin  "ACC1:acc#390" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1239.itm}
+load net {ACC1-3:not#230.itm} -pin  "ACC1:acc#390" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1239.itm}
+load net {ACC1:acc#390.itm(0)} -pin  "ACC1:acc#390" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#390.itm}
+load net {ACC1:acc#390.itm(1)} -pin  "ACC1:acc#390" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#390.itm}
+load net {ACC1:acc#390.itm(2)} -pin  "ACC1:acc#390" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#390.itm}
+load inst "ACC1-3:not#231" "not(1)" "INTERFACE" -attr xrf 64703 -attr oid 1893 -attr @path {/sobel/sobel:core/ACC1-3:not#231} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(5)} -pin  "ACC1-3:not#231" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#4.itm}
+load net {ACC1-3:not#231.itm} -pin  "ACC1-3:not#231" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#231.itm}
+load inst "ACC1:acc#389" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64704 -attr oid 1894 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#389} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#389" {A(0)} -attr @path {/sobel/sobel:core/conc#1077.itm}
+load net {acc.psp#1.sva(4)} -pin  "ACC1:acc#389" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1077.itm}
+load net {acc.psp#1.sva(6)} -pin  "ACC1:acc#389" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1237.itm}
+load net {ACC1-3:not#231.itm} -pin  "ACC1:acc#389" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1237.itm}
+load net {ACC1:acc#389.itm(0)} -pin  "ACC1:acc#389" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#389.itm}
+load net {ACC1:acc#389.itm(1)} -pin  "ACC1:acc#389" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#389.itm}
+load net {ACC1:acc#389.itm(2)} -pin  "ACC1:acc#389" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#389.itm}
+load inst "ACC1-3:not#233" "not(1)" "INTERFACE" -attr xrf 64705 -attr oid 1895 -attr @path {/sobel/sobel:core/ACC1-3:not#233} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(9)} -pin  "ACC1-3:not#233" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#2.itm}
+load net {ACC1-3:not#233.itm} -pin  "ACC1-3:not#233" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#233.itm}
+load inst "ACC1:acc#392" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64706 -attr oid 1896 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#392} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#392" {A(0)} -attr @path {/sobel/sobel:core/conc#1075.itm}
+load net {ACC1:acc#390.itm(1)} -pin  "ACC1:acc#392" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1075.itm}
+load net {ACC1:acc#390.itm(2)} -pin  "ACC1:acc#392" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1075.itm}
+load net {ACC1-3:not#233.itm} -pin  "ACC1:acc#392" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1243.itm}
+load net {ACC1:acc#389.itm(1)} -pin  "ACC1:acc#392" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1243.itm}
+load net {ACC1:acc#389.itm(2)} -pin  "ACC1:acc#392" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1243.itm}
+load net {ACC1:acc#392.itm(0)} -pin  "ACC1:acc#392" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#392.itm}
+load net {ACC1:acc#392.itm(1)} -pin  "ACC1:acc#392" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#392.itm}
+load net {ACC1:acc#392.itm(2)} -pin  "ACC1:acc#392" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#392.itm}
+load net {ACC1:acc#392.itm(3)} -pin  "ACC1:acc#392" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#392.itm}
+load inst "ACC1-3:acc#210" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 64707 -attr oid 1897 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#210} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#393.itm(1)} -pin  "ACC1-3:acc#210" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#393.itm(2)} -pin  "ACC1-3:acc#210" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#393.itm(3)} -pin  "ACC1-3:acc#210" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#393.itm(4)} -pin  "ACC1-3:acc#210" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#392.itm(1)} -pin  "ACC1-3:acc#210" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#392.itm(2)} -pin  "ACC1-3:acc#210" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#392.itm(3)} -pin  "ACC1-3:acc#210" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#210.psp#1.sva(0)} -pin  "ACC1-3:acc#210" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#1.sva}
+load net {ACC1:acc#210.psp#1.sva(1)} -pin  "ACC1-3:acc#210" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#1.sva}
+load net {ACC1:acc#210.psp#1.sva(2)} -pin  "ACC1-3:acc#210" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#1.sva}
+load net {ACC1:acc#210.psp#1.sva(3)} -pin  "ACC1-3:acc#210" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.psp#1.sva}
+load inst "ACC1-3:not#307" "not(1)" "INTERFACE" -attr xrf 64708 -attr oid 1898 -attr @path {/sobel/sobel:core/ACC1-3:not#307} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(11)} -pin  "ACC1-3:not#307" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#24.itm}
+load net {ACC1-3:not#307.itm} -pin  "ACC1-3:not#307" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#307.itm}
+load inst "ACC1-3:not#260" "not(1)" "INTERFACE" -attr xrf 64709 -attr oid 1899 -attr @path {/sobel/sobel:core/ACC1-3:not#260} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(1)} -pin  "ACC1-3:not#260" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#15.itm}
+load net {ACC1-3:not#260.itm} -pin  "ACC1-3:not#260" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#260.itm}
+load inst "ACC1:acc#419" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 64710 -attr oid 1900 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#419} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#419" {A(0)} -attr @path {/sobel/sobel:core/conc#1079.itm}
+load net {ACC1-3:not#307.itm} -pin  "ACC1:acc#419" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1079.itm}
+load net {acc#20.psp#1.sva(8)} -pin  "ACC1:acc#419" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1295.itm}
+load net {ACC1-3:not#260.itm} -pin  "ACC1:acc#419" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1295.itm}
+load net {ACC1:acc#419.itm(0)} -pin  "ACC1:acc#419" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#419.itm}
+load net {ACC1:acc#419.itm(1)} -pin  "ACC1:acc#419" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#419.itm}
+load net {ACC1:acc#419.itm(2)} -pin  "ACC1:acc#419" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#419.itm}
+load net {ACC1:acc#419.itm(3)} -pin  "ACC1:acc#419" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#419.itm}
+load inst "ACC1:acc#421" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 64711 -attr oid 1901 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#421" {A(0)} -attr @path {/sobel/sobel:core/conc#1078.itm}
+load net {ACC1:acc#419.itm(1)} -pin  "ACC1:acc#421" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1078.itm}
+load net {ACC1:acc#419.itm(2)} -pin  "ACC1:acc#421" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1078.itm}
+load net {ACC1:acc#419.itm(3)} -pin  "ACC1:acc#421" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1078.itm}
+load net {acc#20.psp#1.sva(10)} -pin  "ACC1:acc#421" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1080.itm}
+load net {acc#20.psp#1.sva(0)} -pin  "ACC1:acc#421" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1080.itm}
+load net {GND} -pin  "ACC1:acc#421" {B(2)} -attr @path {/sobel/sobel:core/conc#1080.itm}
+load net {PWR} -pin  "ACC1:acc#421" {B(3)} -attr @path {/sobel/sobel:core/conc#1080.itm}
+load net {ACC1:acc#421.itm(0)} -pin  "ACC1:acc#421" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421.itm}
+load net {ACC1:acc#421.itm(1)} -pin  "ACC1:acc#421" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421.itm}
+load net {ACC1:acc#421.itm(2)} -pin  "ACC1:acc#421" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421.itm}
+load net {ACC1:acc#421.itm(3)} -pin  "ACC1:acc#421" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421.itm}
+load net {ACC1:acc#421.itm(4)} -pin  "ACC1:acc#421" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#421.itm}
+load inst "ACC1-3:not#261" "not(1)" "INTERFACE" -attr xrf 64712 -attr oid 1902 -attr @path {/sobel/sobel:core/ACC1-3:not#261} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(3)} -pin  "ACC1-3:not#261" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#17.itm}
+load net {ACC1-3:not#261.itm} -pin  "ACC1-3:not#261" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#261.itm}
+load inst "ACC1-3:not#263" "not(1)" "INTERFACE" -attr xrf 64713 -attr oid 1903 -attr @path {/sobel/sobel:core/ACC1-3:not#263} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(7)} -pin  "ACC1-3:not#263" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#2.itm}
+load net {ACC1-3:not#263.itm} -pin  "ACC1-3:not#263" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#263.itm}
+load inst "ACC1:acc#418" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64714 -attr oid 1904 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#418} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#418" {A(0)} -attr @path {/sobel/sobel:core/conc#1082.itm}
+load net {acc#20.psp#1.sva(2)} -pin  "ACC1:acc#418" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1082.itm}
+load net {ACC1-3:not#263.itm} -pin  "ACC1:acc#418" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1293.itm}
+load net {ACC1-3:not#261.itm} -pin  "ACC1:acc#418" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1293.itm}
+load net {ACC1:acc#418.itm(0)} -pin  "ACC1:acc#418" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#418.itm}
+load net {ACC1:acc#418.itm(1)} -pin  "ACC1:acc#418" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#418.itm}
+load net {ACC1:acc#418.itm(2)} -pin  "ACC1:acc#418" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#418.itm}
+load inst "ACC1-3:not#262" "not(1)" "INTERFACE" -attr xrf 64715 -attr oid 1905 -attr @path {/sobel/sobel:core/ACC1-3:not#262} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(5)} -pin  "ACC1-3:not#262" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#14.itm}
+load net {ACC1-3:not#262.itm} -pin  "ACC1-3:not#262" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#262.itm}
+load inst "ACC1:acc#417" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64716 -attr oid 1906 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#417} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#417" {A(0)} -attr @path {/sobel/sobel:core/conc#1083.itm}
+load net {acc#20.psp#1.sva(4)} -pin  "ACC1:acc#417" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1083.itm}
+load net {acc#20.psp#1.sva(6)} -pin  "ACC1:acc#417" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1291.itm}
+load net {ACC1-3:not#262.itm} -pin  "ACC1:acc#417" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1291.itm}
+load net {ACC1:acc#417.itm(0)} -pin  "ACC1:acc#417" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#417.itm}
+load net {ACC1:acc#417.itm(1)} -pin  "ACC1:acc#417" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#417.itm}
+load net {ACC1:acc#417.itm(2)} -pin  "ACC1:acc#417" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#417.itm}
+load inst "ACC1-3:not#264" "not(1)" "INTERFACE" -attr xrf 64717 -attr oid 1907 -attr @path {/sobel/sobel:core/ACC1-3:not#264} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#1.sva(9)} -pin  "ACC1-3:not#264" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#1.sva)#3.itm}
+load net {ACC1-3:not#264.itm} -pin  "ACC1-3:not#264" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#264.itm}
+load inst "ACC1:acc#420" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64718 -attr oid 1908 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#420} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#420" {A(0)} -attr @path {/sobel/sobel:core/conc#1081.itm}
+load net {ACC1:acc#418.itm(1)} -pin  "ACC1:acc#420" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1081.itm}
+load net {ACC1:acc#418.itm(2)} -pin  "ACC1:acc#420" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1081.itm}
+load net {ACC1-3:not#264.itm} -pin  "ACC1:acc#420" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1297.itm}
+load net {ACC1:acc#417.itm(1)} -pin  "ACC1:acc#420" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1297.itm}
+load net {ACC1:acc#417.itm(2)} -pin  "ACC1:acc#420" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1297.itm}
+load net {ACC1:acc#420.itm(0)} -pin  "ACC1:acc#420" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#420.itm}
+load net {ACC1:acc#420.itm(1)} -pin  "ACC1:acc#420" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#420.itm}
+load net {ACC1:acc#420.itm(2)} -pin  "ACC1:acc#420" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#420.itm}
+load net {ACC1:acc#420.itm(3)} -pin  "ACC1:acc#420" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#420.itm}
+load inst "ACC1-3:acc#217" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 64719 -attr oid 1909 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#217} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#421.itm(1)} -pin  "ACC1-3:acc#217" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#421.itm(2)} -pin  "ACC1-3:acc#217" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#421.itm(3)} -pin  "ACC1-3:acc#217" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#421.itm(4)} -pin  "ACC1-3:acc#217" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#420.itm(1)} -pin  "ACC1-3:acc#217" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#420.itm(2)} -pin  "ACC1-3:acc#217" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#420.itm(3)} -pin  "ACC1-3:acc#217" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#217.psp#1.sva(0)} -pin  "ACC1-3:acc#217" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#1.sva}
+load net {ACC1:acc#217.psp#1.sva(1)} -pin  "ACC1-3:acc#217" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#1.sva}
+load net {ACC1:acc#217.psp#1.sva(2)} -pin  "ACC1-3:acc#217" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#1.sva}
+load net {ACC1:acc#217.psp#1.sva(3)} -pin  "ACC1-3:acc#217" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#1.sva}
+load inst "ACC1-3:not#153" "not(1)" "INTERFACE" -attr xrf 64720 -attr oid 1910 -attr @path {/sobel/sobel:core/ACC1-3:not#153} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#423.itm(2)} -pin  "ACC1-3:not#153" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva)#3.itm}
+load net {ACC1-3:not#153.itm} -pin  "ACC1-3:not#153" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#153.itm}
+load inst "ACC1-3:not#154" "not(1)" "INTERFACE" -attr xrf 64721 -attr oid 1911 -attr @path {/sobel/sobel:core/ACC1-3:not#154} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#423.itm(3)} -pin  "ACC1-3:not#154" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva)#4.itm}
+load net {ACC1-3:not#154.itm} -pin  "ACC1-3:not#154" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#154.itm}
+load inst "ACC1:acc#424" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 64722 -attr oid 1912 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#424} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#424" {A(0)} -attr @path {/sobel/sobel:core/conc#1084.itm}
+load net {ACC1:acc#423.itm(1)} -pin  "ACC1:acc#424" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1084.itm}
+load net {PWR} -pin  "ACC1:acc#424" {A(2)} -attr @path {/sobel/sobel:core/conc#1084.itm}
+load net {ACC1-3:not#154.itm} -pin  "ACC1:acc#424" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1306.itm}
+load net {ACC1-3:not#153.itm} -pin  "ACC1:acc#424" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1306.itm}
+load net {ACC1:acc#424.itm(0)} -pin  "ACC1:acc#424" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#424.itm}
+load net {ACC1:acc#424.itm(1)} -pin  "ACC1:acc#424" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#424.itm}
+load net {ACC1:acc#424.itm(2)} -pin  "ACC1:acc#424" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#424.itm}
+load inst "ACC1:acc#724" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64723 -attr oid 1913 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#724} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#724" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1650.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#724" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1650.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#724" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1607.itm}
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#724" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1607.itm}
+load net {ACC1:acc#724.cse(0)} -pin  "ACC1:acc#724" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#724.cse}
+load net {ACC1:acc#724.cse(1)} -pin  "ACC1:acc#724" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#724.cse}
+load net {ACC1:acc#724.cse(2)} -pin  "ACC1:acc#724" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#724.cse}
+load inst "ACC1:acc#319" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 64724 -attr oid 1914 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#224.psp.sva(11)} -pin  "ACC1:acc#319" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp.sva)#1.itm}
+load net {ACC1:acc#228.psp.sva(11)} -pin  "ACC1:acc#319" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#228.psp.sva)#2.itm}
+load net {ACC1:acc#319.itm(0)} -pin  "ACC1:acc#319" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(1)} -pin  "ACC1:acc#319" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load inst "ACC1:acc#318" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 64725 -attr oid 1915 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#319.itm(0)} -pin  "ACC1:acc#318" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(1)} -pin  "ACC1:acc#318" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#224.psp#1.sva(11)} -pin  "ACC1:acc#318" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#224.psp#1.sva).itm}
+load net {ACC1:acc#318.itm(0)} -pin  "ACC1:acc#318" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(1)} -pin  "ACC1:acc#318" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load inst "ACC1:mul#57" "mul(2,0,12,1,14)" "INTERFACE" -attr xrf 64726 -attr oid 1916 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,14)"
+load net {ACC1:acc#318.itm(0)} -pin  "ACC1:mul#57" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(1)} -pin  "ACC1:mul#57" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {PWR} -pin  "ACC1:mul#57" {B(0)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(1)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(2)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(3)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(4)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(5)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(6)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(7)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(8)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {PWR} -pin  "ACC1:mul#57" {B(9)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#57" {B(10)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {PWR} -pin  "ACC1:mul#57" {B(11)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {ACC1:mul#57.itm(0)} -pin  "ACC1:mul#57" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(1)} -pin  "ACC1:mul#57" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(2)} -pin  "ACC1:mul#57" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(3)} -pin  "ACC1:mul#57" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(4)} -pin  "ACC1:mul#57" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(5)} -pin  "ACC1:mul#57" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(6)} -pin  "ACC1:mul#57" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(7)} -pin  "ACC1:mul#57" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(8)} -pin  "ACC1:mul#57" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(9)} -pin  "ACC1:mul#57" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(10)} -pin  "ACC1:mul#57" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(11)} -pin  "ACC1:mul#57" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(12)} -pin  "ACC1:mul#57" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load net {ACC1:mul#57.itm(13)} -pin  "ACC1:mul#57" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#57.itm}
+load inst "ACC1-3:not#287" "not(1)" "INTERFACE" -attr xrf 64727 -attr oid 1917 -attr @path {/sobel/sobel:core/ACC1-3:not#287} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#217.psp#1.sva(1)} -pin  "ACC1-3:not#287" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#217.psp#1.sva)#4.itm}
+load net {ACC1-3:not#287.itm} -pin  "ACC1-3:not#287" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#287.itm}
+load inst "ACC1:acc#422" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64728 -attr oid 1918 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#422} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#422" {A(0)} -attr @path {/sobel/sobel:core/conc#1085.itm}
+load net {ACC1:acc#217.psp#1.sva(0)} -pin  "ACC1:acc#422" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1085.itm}
+load net {ACC1:acc#217.psp#1.sva(2)} -pin  "ACC1:acc#422" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1301.itm}
+load net {ACC1-3:not#287.itm} -pin  "ACC1:acc#422" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1301.itm}
+load net {ACC1:acc#422.itm(0)} -pin  "ACC1:acc#422" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#422.itm}
+load net {ACC1:acc#422.itm(1)} -pin  "ACC1:acc#422" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#422.itm}
+load net {ACC1:acc#422.itm(2)} -pin  "ACC1:acc#422" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#422.itm}
+load inst "ACC1-3:not#306" "not(1)" "INTERFACE" -attr xrf 64729 -attr oid 1919 -attr @path {/sobel/sobel:core/ACC1-3:not#306} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#217.psp#1.sva(3)} -pin  "ACC1-3:not#306" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#217.psp#1.sva)#5.itm}
+load net {ACC1-3:not#306.itm} -pin  "ACC1-3:not#306" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#306.itm}
+load inst "ACC1-3:acc#223" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 64730 -attr oid 1920 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#223} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#422.itm(1)} -pin  "ACC1-3:acc#223" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1:acc#422.itm(2)} -pin  "ACC1-3:acc#223" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1-3:not#306.itm} -pin  "ACC1-3:acc#223" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#306.itm}
+load net {ACC1:acc#223.psp.sva(0)} -pin  "ACC1-3:acc#223" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp.sva}
+load net {ACC1:acc#223.psp.sva(1)} -pin  "ACC1-3:acc#223" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp.sva}
+load net {ACC1:acc#223.psp.sva(2)} -pin  "ACC1-3:acc#223" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp.sva}
+load inst "ACC1-1:not#273" "not(1)" "INTERFACE" -attr xrf 64731 -attr oid 1921 -attr @path {/sobel/sobel:core/ACC1-1:not#273} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#210.psp#2.sva(1)} -pin  "ACC1-1:not#273" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#210.psp#2.sva)#5.itm}
+load net {ACC1-1:not#273.itm} -pin  "ACC1-1:not#273" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#273.itm}
+load inst "ACC1:acc#337" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64732 -attr oid 1922 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#337} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#337" {A(0)} -attr @path {/sobel/sobel:core/conc#1086.itm}
+load net {ACC1:acc#210.psp#2.sva(0)} -pin  "ACC1:acc#337" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1086.itm}
+load net {ACC1:acc#210.psp#2.sva(2)} -pin  "ACC1:acc#337" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1139.itm}
+load net {ACC1-1:not#273.itm} -pin  "ACC1:acc#337" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1139.itm}
+load net {ACC1:acc#337.itm(0)} -pin  "ACC1:acc#337" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(1)} -pin  "ACC1:acc#337" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(2)} -pin  "ACC1:acc#337" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load inst "ACC1-1:not#305" "not(1)" "INTERFACE" -attr xrf 64733 -attr oid 1923 -attr @path {/sobel/sobel:core/ACC1-1:not#305} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#210.psp#2.sva(3)} -pin  "ACC1-1:not#305" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#210.psp#2.sva)#3.itm}
+load net {ACC1-1:not#305.itm} -pin  "ACC1-1:not#305" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#305.itm}
+load inst "ACC1-1:acc#220" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 64734 -attr oid 1924 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#220} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#337.itm(1)} -pin  "ACC1-1:acc#220" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#18.itm}
+load net {ACC1:acc#337.itm(2)} -pin  "ACC1-1:acc#220" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#18.itm}
+load net {ACC1-1:not#305.itm} -pin  "ACC1-1:acc#220" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#305.itm}
+load net {ACC1:acc#220.psp#1.sva(0)} -pin  "ACC1-1:acc#220" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#220.psp#1.sva}
+load net {ACC1:acc#220.psp#1.sva(1)} -pin  "ACC1-1:acc#220" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#220.psp#1.sva}
+load net {ACC1:acc#220.psp#1.sva(2)} -pin  "ACC1-1:acc#220" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#220.psp#1.sva}
+load inst "ACC1-3:not#273" "not(1)" "INTERFACE" -attr xrf 64735 -attr oid 1925 -attr @path {/sobel/sobel:core/ACC1-3:not#273} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#210.psp#1.sva(1)} -pin  "ACC1-3:not#273" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#210.psp#1.sva)#4.itm}
+load net {ACC1-3:not#273.itm} -pin  "ACC1-3:not#273" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#273.itm}
+load inst "ACC1:acc#394" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64736 -attr oid 1926 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#394} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#394" {A(0)} -attr @path {/sobel/sobel:core/conc#1087.itm}
+load net {ACC1:acc#210.psp#1.sva(0)} -pin  "ACC1:acc#394" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1087.itm}
+load net {ACC1:acc#210.psp#1.sva(2)} -pin  "ACC1:acc#394" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1247.itm}
+load net {ACC1-3:not#273.itm} -pin  "ACC1:acc#394" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1247.itm}
+load net {ACC1:acc#394.itm(0)} -pin  "ACC1:acc#394" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#394.itm}
+load net {ACC1:acc#394.itm(1)} -pin  "ACC1:acc#394" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#394.itm}
+load net {ACC1:acc#394.itm(2)} -pin  "ACC1:acc#394" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#394.itm}
+load inst "ACC1-3:not#305" "not(1)" "INTERFACE" -attr xrf 64737 -attr oid 1927 -attr @path {/sobel/sobel:core/ACC1-3:not#305} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#210.psp#1.sva(3)} -pin  "ACC1-3:not#305" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#210.psp#1.sva)#5.itm}
+load net {ACC1-3:not#305.itm} -pin  "ACC1-3:not#305" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#305.itm}
+load inst "ACC1-3:acc#220" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 64738 -attr oid 1928 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#220} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#394.itm(1)} -pin  "ACC1-3:acc#220" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1:acc#394.itm(2)} -pin  "ACC1-3:acc#220" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1-3:not#305.itm} -pin  "ACC1-3:acc#220" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#305.itm}
+load net {ACC1:acc#220.psp.sva(0)} -pin  "ACC1-3:acc#220" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.psp.sva}
+load net {ACC1:acc#220.psp.sva(1)} -pin  "ACC1-3:acc#220" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.psp.sva}
+load net {ACC1:acc#220.psp.sva(2)} -pin  "ACC1-3:acc#220" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.psp.sva}
+load inst "ACC1-3:not#281" "not(1)" "INTERFACE" -attr xrf 64739 -attr oid 1929 -attr @path {/sobel/sobel:core/ACC1-3:not#281} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#412.itm(2)} -pin  "ACC1-3:not#281" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#214.psp#1.sva)#4.itm}
+load net {ACC1-3:not#281.itm} -pin  "ACC1-3:not#281" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#281.itm}
+load inst "ACC1:acc#413" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64740 -attr oid 1930 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#413} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#413" {A(0)} -attr @path {/sobel/sobel:core/conc#1088.itm}
+load net {ACC1:acc#412.itm(1)} -pin  "ACC1:acc#413" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1088.itm}
+load net {ACC1:acc#412.itm(3)} -pin  "ACC1:acc#413" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1283.itm}
+load net {ACC1-3:not#281.itm} -pin  "ACC1:acc#413" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1283.itm}
+load net {ACC1:acc#413.itm(0)} -pin  "ACC1:acc#413" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#413.itm}
+load net {ACC1:acc#413.itm(1)} -pin  "ACC1:acc#413" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#413.itm}
+load net {ACC1:acc#413.itm(2)} -pin  "ACC1:acc#413" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#413.itm}
+load inst "ACC1-3:not#303" "not(1)" "INTERFACE" -attr xrf 64741 -attr oid 1931 -attr @path {/sobel/sobel:core/ACC1-3:not#303} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#412.itm(4)} -pin  "ACC1-3:not#303" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#214.psp#1.sva)#5.itm}
+load net {ACC1-3:not#303.itm} -pin  "ACC1-3:not#303" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#303.itm}
+load inst "ACC1-3:acc#225" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 64742 -attr oid 1932 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#225} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#413.itm(1)} -pin  "ACC1-3:acc#225" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#82.itm}
+load net {ACC1:acc#413.itm(2)} -pin  "ACC1-3:acc#225" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#82.itm}
+load net {ACC1-3:not#303.itm} -pin  "ACC1-3:acc#225" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#303.itm}
+load net {ACC1:acc#222.psp.sva(0)} -pin  "ACC1-3:acc#225" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp.sva}
+load net {ACC1:acc#222.psp.sva(1)} -pin  "ACC1-3:acc#225" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp.sva}
+load net {ACC1:acc#222.psp.sva(2)} -pin  "ACC1-3:acc#225" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.psp.sva}
+load inst "ACC1:acc#673" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64743 -attr oid 1933 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#673" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1641.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#673" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1641.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#673" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1599.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#673" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1599.itm}
+load net {ACC1:acc#673.cse(0)} -pin  "ACC1:acc#673" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#673.cse(1)} -pin  "ACC1:acc#673" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load net {ACC1:acc#673.cse(2)} -pin  "ACC1:acc#673" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#673.cse}
+load inst "regs.operator[]#12:not" "not(10)" "INTERFACE" -attr xrf 64744 -attr oid 1934 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "regs.operator[]#12:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "regs.operator[]#12:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "regs.operator[]#12:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "regs.operator[]#12:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "regs.operator[]#12:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "regs.operator[]#12:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "regs.operator[]#12:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "regs.operator[]#12:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "regs.operator[]#12:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "regs.operator[]#12:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {regs.operator[]#12:not.itm(0)} -pin  "regs.operator[]#12:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(1)} -pin  "regs.operator[]#12:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(2)} -pin  "regs.operator[]#12:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(3)} -pin  "regs.operator[]#12:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(4)} -pin  "regs.operator[]#12:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(5)} -pin  "regs.operator[]#12:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(6)} -pin  "regs.operator[]#12:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(7)} -pin  "regs.operator[]#12:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(8)} -pin  "regs.operator[]#12:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(9)} -pin  "regs.operator[]#12:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load inst "regs.operator[]#13:not" "not(10)" "INTERFACE" -attr xrf 64745 -attr oid 1935 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "regs.operator[]#13:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "regs.operator[]#13:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "regs.operator[]#13:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "regs.operator[]#13:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "regs.operator[]#13:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "regs.operator[]#13:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "regs.operator[]#13:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "regs.operator[]#13:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "regs.operator[]#13:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "regs.operator[]#13:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {regs.operator[]#13:not.itm(0)} -pin  "regs.operator[]#13:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(1)} -pin  "regs.operator[]#13:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(2)} -pin  "regs.operator[]#13:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(3)} -pin  "regs.operator[]#13:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(4)} -pin  "regs.operator[]#13:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(5)} -pin  "regs.operator[]#13:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(6)} -pin  "regs.operator[]#13:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(7)} -pin  "regs.operator[]#13:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(8)} -pin  "regs.operator[]#13:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(9)} -pin  "regs.operator[]#13:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load inst "ACC1:acc#351" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 64746 -attr oid 1936 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.operator[]#12:not.itm(0)} -pin  "ACC1:acc#351" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(1)} -pin  "ACC1:acc#351" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(2)} -pin  "ACC1:acc#351" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(3)} -pin  "ACC1:acc#351" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(4)} -pin  "ACC1:acc#351" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(5)} -pin  "ACC1:acc#351" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(6)} -pin  "ACC1:acc#351" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(7)} -pin  "ACC1:acc#351" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(8)} -pin  "ACC1:acc#351" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#12:not.itm(9)} -pin  "ACC1:acc#351" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:not.itm}
+load net {regs.operator[]#13:not.itm(0)} -pin  "ACC1:acc#351" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(1)} -pin  "ACC1:acc#351" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(2)} -pin  "ACC1:acc#351" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(3)} -pin  "ACC1:acc#351" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(4)} -pin  "ACC1:acc#351" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(5)} -pin  "ACC1:acc#351" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(6)} -pin  "ACC1:acc#351" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(7)} -pin  "ACC1:acc#351" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(8)} -pin  "ACC1:acc#351" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {regs.operator[]#13:not.itm(9)} -pin  "ACC1:acc#351" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:not.itm}
+load net {ACC1:acc#351.itm(0)} -pin  "ACC1:acc#351" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(1)} -pin  "ACC1:acc#351" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(2)} -pin  "ACC1:acc#351" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(3)} -pin  "ACC1:acc#351" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(4)} -pin  "ACC1:acc#351" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(5)} -pin  "ACC1:acc#351" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(6)} -pin  "ACC1:acc#351" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(7)} -pin  "ACC1:acc#351" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(8)} -pin  "ACC1:acc#351" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(9)} -pin  "ACC1:acc#351" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(10)} -pin  "ACC1:acc#351" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load inst "regs.operator[]#14:not" "not(10)" "INTERFACE" -attr xrf 64747 -attr oid 1937 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "regs.operator[]#14:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "regs.operator[]#14:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "regs.operator[]#14:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "regs.operator[]#14:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "regs.operator[]#14:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "regs.operator[]#14:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "regs.operator[]#14:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "regs.operator[]#14:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "regs.operator[]#14:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "regs.operator[]#14:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {regs.operator[]#14:not.itm(0)} -pin  "regs.operator[]#14:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(1)} -pin  "regs.operator[]#14:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(2)} -pin  "regs.operator[]#14:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(3)} -pin  "regs.operator[]#14:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(4)} -pin  "regs.operator[]#14:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(5)} -pin  "regs.operator[]#14:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(6)} -pin  "regs.operator[]#14:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(7)} -pin  "regs.operator[]#14:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(8)} -pin  "regs.operator[]#14:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(9)} -pin  "regs.operator[]#14:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load inst "ACC1:acc#350" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 64748 -attr oid 1938 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.operator[]#14:not.itm(0)} -pin  "ACC1:acc#350" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(1)} -pin  "ACC1:acc#350" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(2)} -pin  "ACC1:acc#350" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(3)} -pin  "ACC1:acc#350" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(4)} -pin  "ACC1:acc#350" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(5)} -pin  "ACC1:acc#350" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(6)} -pin  "ACC1:acc#350" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(7)} -pin  "ACC1:acc#350" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(8)} -pin  "ACC1:acc#350" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {regs.operator[]#14:not.itm(9)} -pin  "ACC1:acc#350" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:not.itm}
+load net {PWR} -pin  "ACC1:acc#350" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#350" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#350.itm(0)} -pin  "ACC1:acc#350" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(1)} -pin  "ACC1:acc#350" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(2)} -pin  "ACC1:acc#350" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(3)} -pin  "ACC1:acc#350" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(4)} -pin  "ACC1:acc#350" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(5)} -pin  "ACC1:acc#350" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(6)} -pin  "ACC1:acc#350" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(7)} -pin  "ACC1:acc#350" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(8)} -pin  "ACC1:acc#350" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(9)} -pin  "ACC1:acc#350" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(10)} -pin  "ACC1:acc#350" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load inst "ACC1-1:acc#20" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 64749 -attr oid 1939 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#20} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#351.itm(0)} -pin  "ACC1-1:acc#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(1)} -pin  "ACC1-1:acc#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(2)} -pin  "ACC1-1:acc#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(3)} -pin  "ACC1-1:acc#20" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(4)} -pin  "ACC1-1:acc#20" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(5)} -pin  "ACC1-1:acc#20" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(6)} -pin  "ACC1-1:acc#20" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(7)} -pin  "ACC1-1:acc#20" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(8)} -pin  "ACC1-1:acc#20" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(9)} -pin  "ACC1-1:acc#20" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#351.itm(10)} -pin  "ACC1-1:acc#20" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#351.itm}
+load net {ACC1:acc#350.itm(0)} -pin  "ACC1-1:acc#20" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(1)} -pin  "ACC1-1:acc#20" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(2)} -pin  "ACC1-1:acc#20" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(3)} -pin  "ACC1-1:acc#20" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(4)} -pin  "ACC1-1:acc#20" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(5)} -pin  "ACC1-1:acc#20" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(6)} -pin  "ACC1-1:acc#20" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(7)} -pin  "ACC1-1:acc#20" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(8)} -pin  "ACC1-1:acc#20" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(9)} -pin  "ACC1-1:acc#20" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {ACC1:acc#350.itm(10)} -pin  "ACC1-1:acc#20" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#350.itm}
+load net {acc#20.psp#2.sva(0)} -pin  "ACC1-1:acc#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(1)} -pin  "ACC1-1:acc#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(2)} -pin  "ACC1-1:acc#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(3)} -pin  "ACC1-1:acc#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(4)} -pin  "ACC1-1:acc#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(5)} -pin  "ACC1-1:acc#20" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(6)} -pin  "ACC1-1:acc#20" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(7)} -pin  "ACC1-1:acc#20" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(8)} -pin  "ACC1-1:acc#20" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1-1:acc#20" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1-1:acc#20" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:acc#20" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.psp#2.sva}
+load inst "ACC1-1:not#153" "not(1)" "INTERFACE" -attr xrf 64750 -attr oid 1940 -attr @path {/sobel/sobel:core/ACC1-1:not#153} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#358.itm(2)} -pin  "ACC1-1:not#153" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#38.sva)#3.itm}
+load net {ACC1-1:not#153.itm} -pin  "ACC1-1:not#153" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#153.itm}
+load inst "ACC1-1:not#315" "not(1)" "INTERFACE" -attr xrf 64751 -attr oid 1941 -attr @path {/sobel/sobel:core/ACC1-1:not#315} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#358.itm(3)} -pin  "ACC1-1:not#315" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#38.sva).itm}
+load net {ACC1-1:not#315.itm} -pin  "ACC1-1:not#315" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#315.itm}
+load inst "ACC1:acc#359" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 64752 -attr oid 1942 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#359} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#359" {A(0)} -attr @path {/sobel/sobel:core/conc#1089.itm}
+load net {ACC1:acc#358.itm(1)} -pin  "ACC1:acc#359" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1089.itm}
+load net {PWR} -pin  "ACC1:acc#359" {A(2)} -attr @path {/sobel/sobel:core/conc#1089.itm}
+load net {ACC1-1:not#315.itm} -pin  "ACC1:acc#359" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1180.itm}
+load net {ACC1-1:not#153.itm} -pin  "ACC1:acc#359" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1180.itm}
+load net {ACC1:acc#359.itm(0)} -pin  "ACC1:acc#359" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#359.itm}
+load net {ACC1:acc#359.itm(1)} -pin  "ACC1:acc#359" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#359.itm}
+load net {ACC1:acc#359.itm(2)} -pin  "ACC1:acc#359" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#359.itm}
+load inst "ACC1-1:not#299" "not(2)" "INTERFACE" -attr xrf 64753 -attr oid 1943 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#299} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#223.psp#1.sva(1)} -pin  "ACC1-1:not#299" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp#1.sva).itm}
+load net {ACC1:acc#223.psp#1.sva(2)} -pin  "ACC1-1:not#299" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#223.psp#1.sva).itm}
+load net {ACC1-1:not#299.itm(0)} -pin  "ACC1-1:not#299" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#299.itm}
+load net {ACC1-1:not#299.itm(1)} -pin  "ACC1-1:not#299" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#299.itm}
+load inst "ACC1:acc#358" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 64754 -attr oid 1944 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#358} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#358" {A(0)} -attr @path {/sobel/sobel:core/conc#1090.itm}
+load net {ACC1-1:not#299.itm(0)} -pin  "ACC1:acc#358" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1090.itm}
+load net {ACC1-1:not#299.itm(1)} -pin  "ACC1:acc#358" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1090.itm}
+load net {PWR} -pin  "ACC1:acc#358" {B(0)} -attr @path {/sobel/sobel:core/conc#1091.itm}
+load net {ACC1:acc#223.psp#1.sva(0)} -pin  "ACC1:acc#358" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1091.itm}
+load net {ACC1:acc#358.itm(0)} -pin  "ACC1:acc#358" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#358.itm}
+load net {ACC1:acc#358.itm(1)} -pin  "ACC1:acc#358" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#358.itm}
+load net {ACC1:acc#358.itm(2)} -pin  "ACC1:acc#358" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#358.itm}
+load net {ACC1:acc#358.itm(3)} -pin  "ACC1:acc#358" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#358.itm}
+load inst "ACC1-1:not#313" "not(1)" "INTERFACE" -attr xrf 64755 -attr oid 1945 -attr @path {/sobel/sobel:core/ACC1-1:not#313} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1-1:not#313" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#32.itm}
+load net {ACC1-1:not#313.itm} -pin  "ACC1-1:not#313" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#313.itm}
+load inst "ACC1-1:not#260" "not(1)" "INTERFACE" -attr xrf 64756 -attr oid 1946 -attr @path {/sobel/sobel:core/ACC1-1:not#260} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(1)} -pin  "ACC1-1:not#260" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#8.itm}
+load net {ACC1-1:not#260.itm} -pin  "ACC1-1:not#260" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#260.itm}
+load inst "ACC1:acc#354" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 64757 -attr oid 1947 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#354} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#354" {A(0)} -attr @path {/sobel/sobel:core/conc#1093.itm}
+load net {ACC1-1:not#313.itm} -pin  "ACC1:acc#354" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1093.itm}
+load net {acc#20.psp#2.sva(8)} -pin  "ACC1:acc#354" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1169.itm}
+load net {ACC1-1:not#260.itm} -pin  "ACC1:acc#354" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1169.itm}
+load net {ACC1:acc#354.itm(0)} -pin  "ACC1:acc#354" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#354.itm}
+load net {ACC1:acc#354.itm(1)} -pin  "ACC1:acc#354" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#354.itm}
+load net {ACC1:acc#354.itm(2)} -pin  "ACC1:acc#354" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#354.itm}
+load net {ACC1:acc#354.itm(3)} -pin  "ACC1:acc#354" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#354.itm}
+load inst "ACC1:acc#356" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 64758 -attr oid 1948 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#356" {A(0)} -attr @path {/sobel/sobel:core/conc#1092.itm}
+load net {ACC1:acc#354.itm(1)} -pin  "ACC1:acc#356" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1092.itm}
+load net {ACC1:acc#354.itm(2)} -pin  "ACC1:acc#356" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1092.itm}
+load net {ACC1:acc#354.itm(3)} -pin  "ACC1:acc#356" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#1092.itm}
+load net {acc#20.psp#2.sva(10)} -pin  "ACC1:acc#356" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#1094.itm}
+load net {acc#20.psp#2.sva(0)} -pin  "ACC1:acc#356" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1094.itm}
+load net {GND} -pin  "ACC1:acc#356" {B(2)} -attr @path {/sobel/sobel:core/conc#1094.itm}
+load net {PWR} -pin  "ACC1:acc#356" {B(3)} -attr @path {/sobel/sobel:core/conc#1094.itm}
+load net {ACC1:acc#356.itm(0)} -pin  "ACC1:acc#356" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356.itm}
+load net {ACC1:acc#356.itm(1)} -pin  "ACC1:acc#356" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356.itm}
+load net {ACC1:acc#356.itm(2)} -pin  "ACC1:acc#356" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356.itm}
+load net {ACC1:acc#356.itm(3)} -pin  "ACC1:acc#356" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356.itm}
+load net {ACC1:acc#356.itm(4)} -pin  "ACC1:acc#356" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#356.itm}
+load inst "ACC1-1:not#261" "not(1)" "INTERFACE" -attr xrf 64759 -attr oid 1949 -attr @path {/sobel/sobel:core/ACC1-1:not#261} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(3)} -pin  "ACC1-1:not#261" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#7.itm}
+load net {ACC1-1:not#261.itm} -pin  "ACC1-1:not#261" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#261.itm}
+load inst "ACC1-1:not#263" "not(1)" "INTERFACE" -attr xrf 64760 -attr oid 1950 -attr @path {/sobel/sobel:core/ACC1-1:not#263} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(7)} -pin  "ACC1-1:not#263" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#3.itm}
+load net {ACC1-1:not#263.itm} -pin  "ACC1-1:not#263" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#263.itm}
+load inst "ACC1:acc#353" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64761 -attr oid 1951 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#353} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#353" {A(0)} -attr @path {/sobel/sobel:core/conc#1096.itm}
+load net {acc#20.psp#2.sva(2)} -pin  "ACC1:acc#353" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1096.itm}
+load net {ACC1-1:not#263.itm} -pin  "ACC1:acc#353" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1167.itm}
+load net {ACC1-1:not#261.itm} -pin  "ACC1:acc#353" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1167.itm}
+load net {ACC1:acc#353.itm(0)} -pin  "ACC1:acc#353" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#353.itm}
+load net {ACC1:acc#353.itm(1)} -pin  "ACC1:acc#353" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#353.itm}
+load net {ACC1:acc#353.itm(2)} -pin  "ACC1:acc#353" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#353.itm}
+load inst "ACC1-1:not#262" "not(1)" "INTERFACE" -attr xrf 64762 -attr oid 1952 -attr @path {/sobel/sobel:core/ACC1-1:not#262} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(5)} -pin  "ACC1-1:not#262" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#2.itm}
+load net {ACC1-1:not#262.itm} -pin  "ACC1-1:not#262" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#262.itm}
+load inst "ACC1:acc#352" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64763 -attr oid 1953 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#352} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#352" {A(0)} -attr @path {/sobel/sobel:core/conc#1097.itm}
+load net {acc#20.psp#2.sva(4)} -pin  "ACC1:acc#352" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1097.itm}
+load net {acc#20.psp#2.sva(6)} -pin  "ACC1:acc#352" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1165.itm}
+load net {ACC1-1:not#262.itm} -pin  "ACC1:acc#352" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1165.itm}
+load net {ACC1:acc#352.itm(0)} -pin  "ACC1:acc#352" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#352.itm}
+load net {ACC1:acc#352.itm(1)} -pin  "ACC1:acc#352" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#352.itm}
+load net {ACC1:acc#352.itm(2)} -pin  "ACC1:acc#352" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#352.itm}
+load inst "ACC1-1:not#264" "not(1)" "INTERFACE" -attr xrf 64764 -attr oid 1954 -attr @path {/sobel/sobel:core/ACC1-1:not#264} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#20.psp#2.sva(9)} -pin  "ACC1-1:not#264" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#20.psp#2.sva)#59.itm}
+load net {ACC1-1:not#264.itm} -pin  "ACC1-1:not#264" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#264.itm}
+load inst "ACC1:acc#355" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 64765 -attr oid 1955 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#355} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#355" {A(0)} -attr @path {/sobel/sobel:core/conc#1095.itm}
+load net {ACC1:acc#353.itm(1)} -pin  "ACC1:acc#355" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1095.itm}
+load net {ACC1:acc#353.itm(2)} -pin  "ACC1:acc#355" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#1095.itm}
+load net {ACC1-1:not#264.itm} -pin  "ACC1:acc#355" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1171.itm}
+load net {ACC1:acc#352.itm(1)} -pin  "ACC1:acc#355" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1171.itm}
+load net {ACC1:acc#352.itm(2)} -pin  "ACC1:acc#355" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1171.itm}
+load net {ACC1:acc#355.itm(0)} -pin  "ACC1:acc#355" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#355.itm}
+load net {ACC1:acc#355.itm(1)} -pin  "ACC1:acc#355" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#355.itm}
+load net {ACC1:acc#355.itm(2)} -pin  "ACC1:acc#355" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#355.itm}
+load net {ACC1:acc#355.itm(3)} -pin  "ACC1:acc#355" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#355.itm}
+load inst "ACC1-1:acc#217" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 64766 -attr oid 1956 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#217} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#356.itm(1)} -pin  "ACC1-1:acc#217" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#356.itm(2)} -pin  "ACC1-1:acc#217" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#356.itm(3)} -pin  "ACC1-1:acc#217" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#356.itm(4)} -pin  "ACC1-1:acc#217" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#355.itm(1)} -pin  "ACC1-1:acc#217" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#32.itm}
+load net {ACC1:acc#355.itm(2)} -pin  "ACC1-1:acc#217" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#32.itm}
+load net {ACC1:acc#355.itm(3)} -pin  "ACC1-1:acc#217" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#32.itm}
+load net {ACC1:acc#217.psp#2.sva(0)} -pin  "ACC1-1:acc#217" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#2.sva}
+load net {ACC1:acc#217.psp#2.sva(1)} -pin  "ACC1-1:acc#217" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#2.sva}
+load net {ACC1:acc#217.psp#2.sva(2)} -pin  "ACC1-1:acc#217" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#2.sva}
+load net {ACC1:acc#217.psp#2.sva(3)} -pin  "ACC1-1:acc#217" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.psp#2.sva}
+load inst "ACC1-1:not#287" "not(1)" "INTERFACE" -attr xrf 64767 -attr oid 1957 -attr @path {/sobel/sobel:core/ACC1-1:not#287} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#217.psp#2.sva(1)} -pin  "ACC1-1:not#287" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#217.psp#2.sva)#4.itm}
+load net {ACC1-1:not#287.itm} -pin  "ACC1-1:not#287" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#287.itm}
+load inst "ACC1:acc#357" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64768 -attr oid 1958 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#357} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#357" {A(0)} -attr @path {/sobel/sobel:core/conc#1098.itm}
+load net {ACC1:acc#217.psp#2.sva(0)} -pin  "ACC1:acc#357" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#1098.itm}
+load net {ACC1:acc#217.psp#2.sva(2)} -pin  "ACC1:acc#357" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1175.itm}
+load net {ACC1-1:not#287.itm} -pin  "ACC1:acc#357" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1175.itm}
+load net {ACC1:acc#357.itm(0)} -pin  "ACC1:acc#357" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#357.itm}
+load net {ACC1:acc#357.itm(1)} -pin  "ACC1:acc#357" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#357.itm}
+load net {ACC1:acc#357.itm(2)} -pin  "ACC1:acc#357" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#357.itm}
+load inst "ACC1-1:not#306" "not(1)" "INTERFACE" -attr xrf 64769 -attr oid 1959 -attr @path {/sobel/sobel:core/ACC1-1:not#306} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#217.psp#2.sva(3)} -pin  "ACC1-1:not#306" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#217.psp#2.sva)#1.itm}
+load net {ACC1-1:not#306.itm} -pin  "ACC1-1:not#306" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#306.itm}
+load inst "ACC1-1:acc#223" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 64770 -attr oid 1960 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#223} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#357.itm(1)} -pin  "ACC1-1:acc#223" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#357.itm(2)} -pin  "ACC1-1:acc#223" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1-1:not#306.itm} -pin  "ACC1-1:acc#223" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#306.itm}
+load net {ACC1:acc#223.psp#1.sva(0)} -pin  "ACC1-1:acc#223" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp#1.sva}
+load net {ACC1:acc#223.psp#1.sva(1)} -pin  "ACC1-1:acc#223" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp#1.sva}
+load net {ACC1:acc#223.psp#1.sva(2)} -pin  "ACC1-1:acc#223" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.psp#1.sva}
+load inst "ACC1:acc#699" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 64771 -attr oid 1961 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#699" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1655.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#699" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1655.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#699" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1611.itm}
+load net {acc#20.psp#2.sva(11)} -pin  "ACC1:acc#699" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#1611.itm}
+load net {ACC1:acc#699.cse(0)} -pin  "ACC1:acc#699" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#699.cse(1)} -pin  "ACC1:acc#699" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load net {ACC1:acc#699.cse(2)} -pin  "ACC1:acc#699" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#699.cse}
+load inst "ACC1-1:not#25" "not(1)" "INTERFACE" -attr xrf 64772 -attr oid 1962 -attr @path {/sobel/sobel:core/ACC1-1:not#25} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#338.itm(2)} -pin  "ACC1-1:not#25" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#26.sva)#4.itm}
+load net {ACC1-1:not#25.itm} -pin  "ACC1-1:not#25" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#25.itm}
+load inst "ACC1-1:not#309" "not(1)" "INTERFACE" -attr xrf 64773 -attr oid 1963 -attr @path {/sobel/sobel:core/ACC1-1:not#309} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#338.itm(3)} -pin  "ACC1-1:not#309" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#26.sva)#2.itm}
+load net {ACC1-1:not#309.itm} -pin  "ACC1-1:not#309" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#309.itm}
+load inst "ACC1:acc#339" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 64774 -attr oid 1964 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#339} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#339" {A(0)} -attr @path {/sobel/sobel:core/conc#1099.itm}
+load net {ACC1:acc#338.itm(1)} -pin  "ACC1:acc#339" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#1099.itm}
+load net {PWR} -pin  "ACC1:acc#339" {A(2)} -attr @path {/sobel/sobel:core/conc#1099.itm}
+load net {ACC1-1:not#309.itm} -pin  "ACC1:acc#339" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1144.itm}
+load net {ACC1-1:not#25.itm} -pin  "ACC1:acc#339" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#1144.itm}
+load net {ACC1:acc#339.itm(0)} -pin  "ACC1:acc#339" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(1)} -pin  "ACC1:acc#339" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(2)} -pin  "ACC1:acc#339" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+### END MODULE 
+
+module new "sobel" "orig"
+load portBus {vin:rsc.z(89:0)} input 90 {vin:rsc.z(89)} {vin:rsc.z(88)} {vin:rsc.z(87)} {vin:rsc.z(86)} {vin:rsc.z(85)} {vin:rsc.z(84)} {vin:rsc.z(83)} {vin:rsc.z(82)} {vin:rsc.z(81)} {vin:rsc.z(80)} {vin:rsc.z(79)} {vin:rsc.z(78)} {vin:rsc.z(77)} {vin:rsc.z(76)} {vin:rsc.z(75)} {vin:rsc.z(74)} {vin:rsc.z(73)} {vin:rsc.z(72)} {vin:rsc.z(71)} {vin:rsc.z(70)} {vin:rsc.z(69)} {vin:rsc.z(68)} {vin:rsc.z(67)} {vin:rsc.z(66)} {vin:rsc.z(65)} {vin:rsc.z(64)} {vin:rsc.z(63)} {vin:rsc.z(62)} {vin:rsc.z(61)} {vin:rsc.z(60)} {vin:rsc.z(59)} {vin:rsc.z(58)} {vin:rsc.z(57)} {vin:rsc.z(56)} {vin:rsc.z(55)} {vin:rsc.z(54)} {vin:rsc.z(53)} {vin:rsc.z(52)} {vin:rsc.z(51)} {vin:rsc.z(50)} {vin:rsc.z(49)} {vin:rsc.z(48)} {vin:rsc.z(47)} {vin:rsc.z(46)} {vin:rsc.z(45)} {vin:rsc.z(44)} {vin:rsc.z(43)} {vin:rsc.z(42)} {vin:rsc.z(41)} {vin:rsc.z(40)} {vin:rsc.z(39)} {vin:rsc.z(38)} {vin:rsc.z(37)} {vin:rsc.z(36)} {vin:rsc.z(35)} {vin:rsc.z(34)} {vin:rsc.z(33)} {vin:rsc.z(32)} {vin:rsc.z(31)} {vin:rsc.z(30)} {vin:rsc.z(29)} {vin:rsc.z(28)} {vin:rsc.z(27)} {vin:rsc.z(26)} {vin:rsc.z(25)} {vin:rsc.z(24)} {vin:rsc.z(23)} {vin:rsc.z(22)} {vin:rsc.z(21)} {vin:rsc.z(20)} {vin:rsc.z(19)} {vin:rsc.z(18)} {vin:rsc.z(17)} {vin:rsc.z(16)} {vin:rsc.z(15)} {vin:rsc.z(14)} {vin:rsc.z(13)} {vin:rsc.z(12)} {vin:rsc.z(11)} {vin:rsc.z(10)} {vin:rsc.z(9)} {vin:rsc.z(8)} {vin:rsc.z(7)} {vin:rsc.z(6)} {vin:rsc.z(5)} {vin:rsc.z(4)} {vin:rsc.z(3)} {vin:rsc.z(2)} {vin:rsc.z(1)} {vin:rsc.z(0)} -attr xrf 64775 -attr oid 1965 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load portBus {vout:rsc.z(29:0)} output 30 {vout:rsc.z(29)} {vout:rsc.z(28)} {vout:rsc.z(27)} {vout:rsc.z(26)} {vout:rsc.z(25)} {vout:rsc.z(24)} {vout:rsc.z(23)} {vout:rsc.z(22)} {vout:rsc.z(21)} {vout:rsc.z(20)} {vout:rsc.z(19)} {vout:rsc.z(18)} {vout:rsc.z(17)} {vout:rsc.z(16)} {vout:rsc.z(15)} {vout:rsc.z(14)} {vout:rsc.z(13)} {vout:rsc.z(12)} {vout:rsc.z(11)} {vout:rsc.z(10)} {vout:rsc.z(9)} {vout:rsc.z(8)} {vout:rsc.z(7)} {vout:rsc.z(6)} {vout:rsc.z(5)} {vout:rsc.z(4)} {vout:rsc.z(3)} {vout:rsc.z(2)} {vout:rsc.z(1)} {vout:rsc.z(0)} -attr xrf 64776 -attr oid 1966 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load port {clk} input -attr xrf 64777 -attr oid 1967 -attr vt d -attr @path {/sobel/clk}
+load port {en} input -attr xrf 64778 -attr oid 1968 -attr vt d -attr @path {/sobel/en}
+load port {arst_n} input -attr xrf 64779 -attr oid 1969 -attr vt d -attr @path {/sobel/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(89:0)} output 90 {d(89)} {d(88)} {d(87)} {d(86)} {d(85)} {d(84)} {d(83)} {d(82)} {d(81)} {d(80)} {d(79)} {d(78)} {d(77)} {d(76)} {d(75)} {d(74)} {d(73)} {d(72)} {d(71)} {d(70)} {d(69)} {d(68)} {d(67)} {d(66)} {d(65)} {d(64)} {d(63)} {d(62)} {d(61)} {d(60)} {d(59)} {d(58)} {d(57)} {d(56)} {d(55)} {d(54)} {d(53)} {d(52)} {d(51)} {d(50)} {d(49)} {d(48)} {d(47)} {d(46)} {d(45)} {d(44)} {d(43)} {d(42)} {d(41)} {d(40)} {d(39)} {d(38)} {d(37)} {d(36)} {d(35)} {d(34)} {d(33)} {d(32)} {d(31)} {d(30)} {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(89:0)} input 90 {z(89)} {z(88)} {z(87)} {z(86)} {z(85)} {z(84)} {z(83)} {z(82)} {z(81)} {z(80)} {z(79)} {z(78)} {z(77)} {z(76)} {z(75)} {z(74)} {z(73)} {z(72)} {z(71)} {z(70)} {z(69)} {z(68)} {z(67)} {z(66)} {z(65)} {z(64)} {z(63)} {z(62)} {z(61)} {z(60)} {z(59)} {z(58)} {z(57)} {z(56)} {z(55)} {z(54)} {z(53)} {z(52)} {z(51)} {z(50)} {z(49)} {z(48)} {z(47)} {z(46)} {z(45)} {z(44)} {z(43)} {z(42)} {z(41)} {z(40)} {z(39)} {z(38)} {z(37)} {z(36)} {z(35)} {z(34)} {z(33)} {z(32)} {z(31)} {z(30)} {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(29:0)} input 30 {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(29:0)} output 30 {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "sobel:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} \
+     portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} \
+
+load net {vin:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d#1} 90 {vin:rsc:mgc_in_wire.d#1(0)} {vin:rsc:mgc_in_wire.d#1(1)} {vin:rsc:mgc_in_wire.d#1(2)} {vin:rsc:mgc_in_wire.d#1(3)} {vin:rsc:mgc_in_wire.d#1(4)} {vin:rsc:mgc_in_wire.d#1(5)} {vin:rsc:mgc_in_wire.d#1(6)} {vin:rsc:mgc_in_wire.d#1(7)} {vin:rsc:mgc_in_wire.d#1(8)} {vin:rsc:mgc_in_wire.d#1(9)} {vin:rsc:mgc_in_wire.d#1(10)} {vin:rsc:mgc_in_wire.d#1(11)} {vin:rsc:mgc_in_wire.d#1(12)} {vin:rsc:mgc_in_wire.d#1(13)} {vin:rsc:mgc_in_wire.d#1(14)} {vin:rsc:mgc_in_wire.d#1(15)} {vin:rsc:mgc_in_wire.d#1(16)} {vin:rsc:mgc_in_wire.d#1(17)} {vin:rsc:mgc_in_wire.d#1(18)} {vin:rsc:mgc_in_wire.d#1(19)} {vin:rsc:mgc_in_wire.d#1(20)} {vin:rsc:mgc_in_wire.d#1(21)} {vin:rsc:mgc_in_wire.d#1(22)} {vin:rsc:mgc_in_wire.d#1(23)} {vin:rsc:mgc_in_wire.d#1(24)} {vin:rsc:mgc_in_wire.d#1(25)} {vin:rsc:mgc_in_wire.d#1(26)} {vin:rsc:mgc_in_wire.d#1(27)} {vin:rsc:mgc_in_wire.d#1(28)} {vin:rsc:mgc_in_wire.d#1(29)} {vin:rsc:mgc_in_wire.d#1(30)} {vin:rsc:mgc_in_wire.d#1(31)} {vin:rsc:mgc_in_wire.d#1(32)} {vin:rsc:mgc_in_wire.d#1(33)} {vin:rsc:mgc_in_wire.d#1(34)} {vin:rsc:mgc_in_wire.d#1(35)} {vin:rsc:mgc_in_wire.d#1(36)} {vin:rsc:mgc_in_wire.d#1(37)} {vin:rsc:mgc_in_wire.d#1(38)} {vin:rsc:mgc_in_wire.d#1(39)} {vin:rsc:mgc_in_wire.d#1(40)} {vin:rsc:mgc_in_wire.d#1(41)} {vin:rsc:mgc_in_wire.d#1(42)} {vin:rsc:mgc_in_wire.d#1(43)} {vin:rsc:mgc_in_wire.d#1(44)} {vin:rsc:mgc_in_wire.d#1(45)} {vin:rsc:mgc_in_wire.d#1(46)} {vin:rsc:mgc_in_wire.d#1(47)} {vin:rsc:mgc_in_wire.d#1(48)} {vin:rsc:mgc_in_wire.d#1(49)} {vin:rsc:mgc_in_wire.d#1(50)} {vin:rsc:mgc_in_wire.d#1(51)} {vin:rsc:mgc_in_wire.d#1(52)} {vin:rsc:mgc_in_wire.d#1(53)} {vin:rsc:mgc_in_wire.d#1(54)} {vin:rsc:mgc_in_wire.d#1(55)} {vin:rsc:mgc_in_wire.d#1(56)} {vin:rsc:mgc_in_wire.d#1(57)} {vin:rsc:mgc_in_wire.d#1(58)} {vin:rsc:mgc_in_wire.d#1(59)} {vin:rsc:mgc_in_wire.d#1(60)} {vin:rsc:mgc_in_wire.d#1(61)} {vin:rsc:mgc_in_wire.d#1(62)} {vin:rsc:mgc_in_wire.d#1(63)} {vin:rsc:mgc_in_wire.d#1(64)} {vin:rsc:mgc_in_wire.d#1(65)} {vin:rsc:mgc_in_wire.d#1(66)} {vin:rsc:mgc_in_wire.d#1(67)} {vin:rsc:mgc_in_wire.d#1(68)} {vin:rsc:mgc_in_wire.d#1(69)} {vin:rsc:mgc_in_wire.d#1(70)} {vin:rsc:mgc_in_wire.d#1(71)} {vin:rsc:mgc_in_wire.d#1(72)} {vin:rsc:mgc_in_wire.d#1(73)} {vin:rsc:mgc_in_wire.d#1(74)} {vin:rsc:mgc_in_wire.d#1(75)} {vin:rsc:mgc_in_wire.d#1(76)} {vin:rsc:mgc_in_wire.d#1(77)} {vin:rsc:mgc_in_wire.d#1(78)} {vin:rsc:mgc_in_wire.d#1(79)} {vin:rsc:mgc_in_wire.d#1(80)} {vin:rsc:mgc_in_wire.d#1(81)} {vin:rsc:mgc_in_wire.d#1(82)} {vin:rsc:mgc_in_wire.d#1(83)} {vin:rsc:mgc_in_wire.d#1(84)} {vin:rsc:mgc_in_wire.d#1(85)} {vin:rsc:mgc_in_wire.d#1(86)} {vin:rsc:mgc_in_wire.d#1(87)} {vin:rsc:mgc_in_wire.d#1(88)} {vin:rsc:mgc_in_wire.d#1(89)} -attr xrf 64780 -attr oid 1970 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d#1} 30 {vout:rsc:mgc_out_stdreg.d#1(0)} {vout:rsc:mgc_out_stdreg.d#1(1)} {vout:rsc:mgc_out_stdreg.d#1(2)} {vout:rsc:mgc_out_stdreg.d#1(3)} {vout:rsc:mgc_out_stdreg.d#1(4)} {vout:rsc:mgc_out_stdreg.d#1(5)} {vout:rsc:mgc_out_stdreg.d#1(6)} {vout:rsc:mgc_out_stdreg.d#1(7)} {vout:rsc:mgc_out_stdreg.d#1(8)} {vout:rsc:mgc_out_stdreg.d#1(9)} {vout:rsc:mgc_out_stdreg.d#1(10)} {vout:rsc:mgc_out_stdreg.d#1(11)} {vout:rsc:mgc_out_stdreg.d#1(12)} {vout:rsc:mgc_out_stdreg.d#1(13)} {vout:rsc:mgc_out_stdreg.d#1(14)} {vout:rsc:mgc_out_stdreg.d#1(15)} {vout:rsc:mgc_out_stdreg.d#1(16)} {vout:rsc:mgc_out_stdreg.d#1(17)} {vout:rsc:mgc_out_stdreg.d#1(18)} {vout:rsc:mgc_out_stdreg.d#1(19)} {vout:rsc:mgc_out_stdreg.d#1(20)} {vout:rsc:mgc_out_stdreg.d#1(21)} {vout:rsc:mgc_out_stdreg.d#1(22)} {vout:rsc:mgc_out_stdreg.d#1(23)} {vout:rsc:mgc_out_stdreg.d#1(24)} {vout:rsc:mgc_out_stdreg.d#1(25)} {vout:rsc:mgc_out_stdreg.d#1(26)} {vout:rsc:mgc_out_stdreg.d#1(27)} {vout:rsc:mgc_out_stdreg.d#1(28)} {vout:rsc:mgc_out_stdreg.d#1(29)} -attr xrf 64781 -attr oid 1971 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -attr vt d
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+load net {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 64782 -attr oid 1972 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(0)} -port {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -port {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -port {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -port {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -port {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -port {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -port {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -port {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -port {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -port {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -port {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -port {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -port {vin:rsc.z(12)} -attr vt d
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+load net {vin:rsc.z(15)} -port {vin:rsc.z(15)} -attr vt d
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+load net {vin:rsc.z(20)} -port {vin:rsc.z(20)} -attr vt d
+load net {vin:rsc.z(21)} -port {vin:rsc.z(21)} -attr vt d
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+load net {vin:rsc.z(24)} -port {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -port {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -port {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -port {vin:rsc.z(27)} -attr vt d
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+load net {vin:rsc.z(38)} -port {vin:rsc.z(38)} -attr vt d
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+load net {vin:rsc.z(43)} -port {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -port {vin:rsc.z(44)} -attr vt d
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+load net {vin:rsc.z(55)} -port {vin:rsc.z(55)} -attr vt d
+load net {vin:rsc.z(56)} -port {vin:rsc.z(56)} -attr vt d
+load net {vin:rsc.z(57)} -port {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -port {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -port {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -port {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -port {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -port {vin:rsc.z(62)} -attr vt d
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+load net {vin:rsc.z(64)} -port {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -port {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -port {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -port {vin:rsc.z(67)} -attr vt d
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+load net {vin:rsc.z(89)} -port {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 64783 -attr oid 1973 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vout:rsc.z(0)} -attr vt d
+load net {vout:rsc.z(1)} -attr vt d
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+load net {vout:rsc.z(28)} -attr vt d
+load net {vout:rsc.z(29)} -attr vt d
+load netBundle {vout:rsc.z} 30 {vout:rsc.z(0)} {vout:rsc.z(1)} {vout:rsc.z(2)} {vout:rsc.z(3)} {vout:rsc.z(4)} {vout:rsc.z(5)} {vout:rsc.z(6)} {vout:rsc.z(7)} {vout:rsc.z(8)} {vout:rsc.z(9)} {vout:rsc.z(10)} {vout:rsc.z(11)} {vout:rsc.z(12)} {vout:rsc.z(13)} {vout:rsc.z(14)} {vout:rsc.z(15)} {vout:rsc.z(16)} {vout:rsc.z(17)} {vout:rsc.z(18)} {vout:rsc.z(19)} {vout:rsc.z(20)} {vout:rsc.z(21)} {vout:rsc.z(22)} {vout:rsc.z(23)} {vout:rsc.z(24)} {vout:rsc.z(25)} {vout:rsc.z(26)} {vout:rsc.z(27)} {vout:rsc.z(28)} {vout:rsc.z(29)} -attr xrf 64784 -attr oid 1974 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(0)} -port {vout:rsc.z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -port {vout:rsc.z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -port {vout:rsc.z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -port {vout:rsc.z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -port {vout:rsc.z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -port {vout:rsc.z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -port {vout:rsc.z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -port {vout:rsc.z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -port {vout:rsc.z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -port {vout:rsc.z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -port {vout:rsc.z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -port {vout:rsc.z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -port {vout:rsc.z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -port {vout:rsc.z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -port {vout:rsc.z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -port {vout:rsc.z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -port {vout:rsc.z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -port {vout:rsc.z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -port {vout:rsc.z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -port {vout:rsc.z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -port {vout:rsc.z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -port {vout:rsc.z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -port {vout:rsc.z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -port {vout:rsc.z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -port {vout:rsc.z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -port {vout:rsc.z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -port {vout:rsc.z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -port {vout:rsc.z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -port {vout:rsc.z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -port {vout:rsc.z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {clk} -attr xrf 64785 -attr oid 1975
+load net {clk} -port {clk} -attr xrf 64786 -attr oid 1976
+load net {en} -attr xrf 64787 -attr oid 1977
+load net {en} -port {en} -attr xrf 64788 -attr oid 1978
+load net {arst_n} -attr xrf 64789 -attr oid 1979
+load net {arst_n} -port {arst_n} -attr xrf 64790 -attr oid 1980
+load inst "sobel:core:inst" "sobel:core" "orig" -attr xrf 64791 -attr oid 1981 -attr vt dc -attr @path {/sobel/sobel:core:inst} -attr area 5445.659661 -attr delay 15.672745 -attr hier "/sobel/sobel:core" -pg 1 -lvl 3
+load net {clk} -pin  "sobel:core:inst" {clk#1} -attr xrf 64792 -attr oid 1982 -attr @path {/sobel/clk}
+load net {en} -pin  "sobel:core:inst" {en#1} -attr xrf 64793 -attr oid 1983 -attr @path {/sobel/en}
+load net {arst_n} -pin  "sobel:core:inst" {arst_n#1} -attr xrf 64794 -attr oid 1984 -attr @path {/sobel/arst_n}
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(8)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(9)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(10)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(11)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(12)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(13)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(14)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(15)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(16)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(17)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(18)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(19)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(20)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(21)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(22)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(23)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(24)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(25)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(26)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(27)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(28)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(29)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(30)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(31)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(32)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(33)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(34)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(35)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(36)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(37)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(38)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(39)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(40)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(41)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(42)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(43)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(44)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(45)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(46)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(47)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(48)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(49)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(50)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(51)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(52)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(53)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(54)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(55)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(56)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(57)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(58)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(59)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(60)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(61)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(62)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(63)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(64)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(65)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(66)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(67)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(68)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(69)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(70)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(71)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(72)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(73)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(74)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(75)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(76)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(77)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(78)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(79)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(80)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(81)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(82)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(83)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(84)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(85)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(86)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(87)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(88)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(89)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(8)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(9)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(10)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(11)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(12)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(13)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(14)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(15)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(16)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(17)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(18)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(19)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(20)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(21)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(22)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(23)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(24)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(25)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(26)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(27)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(28)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(29)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load inst "vin:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" -attr xrf 64795 -attr oid 1985 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,90)" -pg 1 -lvl 1
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "vin:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "vin:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "vin:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "vin:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "vin:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "vin:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "vin:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "vin:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "vin:rsc:mgc_in_wire" {d(8)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "vin:rsc:mgc_in_wire" {d(9)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "vin:rsc:mgc_in_wire" {d(10)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "vin:rsc:mgc_in_wire" {d(11)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "vin:rsc:mgc_in_wire" {d(12)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "vin:rsc:mgc_in_wire" {d(13)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "vin:rsc:mgc_in_wire" {d(14)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "vin:rsc:mgc_in_wire" {d(15)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "vin:rsc:mgc_in_wire" {d(16)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "vin:rsc:mgc_in_wire" {d(17)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "vin:rsc:mgc_in_wire" {d(18)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "vin:rsc:mgc_in_wire" {d(19)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "vin:rsc:mgc_in_wire" {d(20)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "vin:rsc:mgc_in_wire" {d(21)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "vin:rsc:mgc_in_wire" {d(22)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "vin:rsc:mgc_in_wire" {d(23)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "vin:rsc:mgc_in_wire" {d(24)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "vin:rsc:mgc_in_wire" {d(25)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "vin:rsc:mgc_in_wire" {d(26)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "vin:rsc:mgc_in_wire" {d(27)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "vin:rsc:mgc_in_wire" {d(28)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "vin:rsc:mgc_in_wire" {d(29)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "vin:rsc:mgc_in_wire" {d(30)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "vin:rsc:mgc_in_wire" {d(31)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "vin:rsc:mgc_in_wire" {d(32)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "vin:rsc:mgc_in_wire" {d(33)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "vin:rsc:mgc_in_wire" {d(34)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "vin:rsc:mgc_in_wire" {d(35)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "vin:rsc:mgc_in_wire" {d(36)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "vin:rsc:mgc_in_wire" {d(37)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "vin:rsc:mgc_in_wire" {d(38)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "vin:rsc:mgc_in_wire" {d(39)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "vin:rsc:mgc_in_wire" {d(40)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "vin:rsc:mgc_in_wire" {d(41)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "vin:rsc:mgc_in_wire" {d(42)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "vin:rsc:mgc_in_wire" {d(43)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "vin:rsc:mgc_in_wire" {d(44)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "vin:rsc:mgc_in_wire" {d(45)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "vin:rsc:mgc_in_wire" {d(46)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "vin:rsc:mgc_in_wire" {d(47)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "vin:rsc:mgc_in_wire" {d(48)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "vin:rsc:mgc_in_wire" {d(49)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "vin:rsc:mgc_in_wire" {d(50)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "vin:rsc:mgc_in_wire" {d(51)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "vin:rsc:mgc_in_wire" {d(52)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "vin:rsc:mgc_in_wire" {d(53)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "vin:rsc:mgc_in_wire" {d(54)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "vin:rsc:mgc_in_wire" {d(55)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "vin:rsc:mgc_in_wire" {d(56)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "vin:rsc:mgc_in_wire" {d(57)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "vin:rsc:mgc_in_wire" {d(58)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "vin:rsc:mgc_in_wire" {d(59)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "vin:rsc:mgc_in_wire" {d(60)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "vin:rsc:mgc_in_wire" {d(61)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "vin:rsc:mgc_in_wire" {d(62)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "vin:rsc:mgc_in_wire" {d(63)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "vin:rsc:mgc_in_wire" {d(64)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "vin:rsc:mgc_in_wire" {d(65)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "vin:rsc:mgc_in_wire" {d(66)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "vin:rsc:mgc_in_wire" {d(67)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "vin:rsc:mgc_in_wire" {d(68)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "vin:rsc:mgc_in_wire" {d(69)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "vin:rsc:mgc_in_wire" {d(70)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "vin:rsc:mgc_in_wire" {d(71)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "vin:rsc:mgc_in_wire" {d(72)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "vin:rsc:mgc_in_wire" {d(73)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "vin:rsc:mgc_in_wire" {d(74)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "vin:rsc:mgc_in_wire" {d(75)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "vin:rsc:mgc_in_wire" {d(76)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "vin:rsc:mgc_in_wire" {d(77)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "vin:rsc:mgc_in_wire" {d(78)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "vin:rsc:mgc_in_wire" {d(79)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "vin:rsc:mgc_in_wire" {d(80)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "vin:rsc:mgc_in_wire" {d(81)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "vin:rsc:mgc_in_wire" {d(82)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "vin:rsc:mgc_in_wire" {d(83)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "vin:rsc:mgc_in_wire" {d(84)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "vin:rsc:mgc_in_wire" {d(85)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "vin:rsc:mgc_in_wire" {d(86)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "vin:rsc:mgc_in_wire" {d(87)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "vin:rsc:mgc_in_wire" {d(88)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "vin:rsc:mgc_in_wire" {d(89)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc.z(0)} -pin  "vin:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(1)} -pin  "vin:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(2)} -pin  "vin:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(3)} -pin  "vin:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(4)} -pin  "vin:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(5)} -pin  "vin:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(6)} -pin  "vin:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(7)} -pin  "vin:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(8)} -pin  "vin:rsc:mgc_in_wire" {z(8)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(9)} -pin  "vin:rsc:mgc_in_wire" {z(9)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(10)} -pin  "vin:rsc:mgc_in_wire" {z(10)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(11)} -pin  "vin:rsc:mgc_in_wire" {z(11)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(12)} -pin  "vin:rsc:mgc_in_wire" {z(12)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(13)} -pin  "vin:rsc:mgc_in_wire" {z(13)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(14)} -pin  "vin:rsc:mgc_in_wire" {z(14)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(15)} -pin  "vin:rsc:mgc_in_wire" {z(15)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(16)} -pin  "vin:rsc:mgc_in_wire" {z(16)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(17)} -pin  "vin:rsc:mgc_in_wire" {z(17)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(18)} -pin  "vin:rsc:mgc_in_wire" {z(18)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(19)} -pin  "vin:rsc:mgc_in_wire" {z(19)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(20)} -pin  "vin:rsc:mgc_in_wire" {z(20)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(21)} -pin  "vin:rsc:mgc_in_wire" {z(21)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(22)} -pin  "vin:rsc:mgc_in_wire" {z(22)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(23)} -pin  "vin:rsc:mgc_in_wire" {z(23)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(24)} -pin  "vin:rsc:mgc_in_wire" {z(24)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(25)} -pin  "vin:rsc:mgc_in_wire" {z(25)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(26)} -pin  "vin:rsc:mgc_in_wire" {z(26)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(27)} -pin  "vin:rsc:mgc_in_wire" {z(27)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(28)} -pin  "vin:rsc:mgc_in_wire" {z(28)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(29)} -pin  "vin:rsc:mgc_in_wire" {z(29)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(30)} -pin  "vin:rsc:mgc_in_wire" {z(30)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(31)} -pin  "vin:rsc:mgc_in_wire" {z(31)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(32)} -pin  "vin:rsc:mgc_in_wire" {z(32)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(33)} -pin  "vin:rsc:mgc_in_wire" {z(33)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(34)} -pin  "vin:rsc:mgc_in_wire" {z(34)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(35)} -pin  "vin:rsc:mgc_in_wire" {z(35)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(36)} -pin  "vin:rsc:mgc_in_wire" {z(36)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(37)} -pin  "vin:rsc:mgc_in_wire" {z(37)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(38)} -pin  "vin:rsc:mgc_in_wire" {z(38)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(39)} -pin  "vin:rsc:mgc_in_wire" {z(39)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(40)} -pin  "vin:rsc:mgc_in_wire" {z(40)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(41)} -pin  "vin:rsc:mgc_in_wire" {z(41)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(42)} -pin  "vin:rsc:mgc_in_wire" {z(42)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(43)} -pin  "vin:rsc:mgc_in_wire" {z(43)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(44)} -pin  "vin:rsc:mgc_in_wire" {z(44)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(45)} -pin  "vin:rsc:mgc_in_wire" {z(45)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(46)} -pin  "vin:rsc:mgc_in_wire" {z(46)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(47)} -pin  "vin:rsc:mgc_in_wire" {z(47)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(48)} -pin  "vin:rsc:mgc_in_wire" {z(48)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(49)} -pin  "vin:rsc:mgc_in_wire" {z(49)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(50)} -pin  "vin:rsc:mgc_in_wire" {z(50)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(51)} -pin  "vin:rsc:mgc_in_wire" {z(51)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(52)} -pin  "vin:rsc:mgc_in_wire" {z(52)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(53)} -pin  "vin:rsc:mgc_in_wire" {z(53)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(54)} -pin  "vin:rsc:mgc_in_wire" {z(54)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(55)} -pin  "vin:rsc:mgc_in_wire" {z(55)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(56)} -pin  "vin:rsc:mgc_in_wire" {z(56)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(57)} -pin  "vin:rsc:mgc_in_wire" {z(57)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(58)} -pin  "vin:rsc:mgc_in_wire" {z(58)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(59)} -pin  "vin:rsc:mgc_in_wire" {z(59)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(60)} -pin  "vin:rsc:mgc_in_wire" {z(60)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(61)} -pin  "vin:rsc:mgc_in_wire" {z(61)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(62)} -pin  "vin:rsc:mgc_in_wire" {z(62)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(63)} -pin  "vin:rsc:mgc_in_wire" {z(63)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(64)} -pin  "vin:rsc:mgc_in_wire" {z(64)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(65)} -pin  "vin:rsc:mgc_in_wire" {z(65)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(66)} -pin  "vin:rsc:mgc_in_wire" {z(66)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(67)} -pin  "vin:rsc:mgc_in_wire" {z(67)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(68)} -pin  "vin:rsc:mgc_in_wire" {z(68)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(69)} -pin  "vin:rsc:mgc_in_wire" {z(69)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(70)} -pin  "vin:rsc:mgc_in_wire" {z(70)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(71)} -pin  "vin:rsc:mgc_in_wire" {z(71)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(72)} -pin  "vin:rsc:mgc_in_wire" {z(72)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(73)} -pin  "vin:rsc:mgc_in_wire" {z(73)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(74)} -pin  "vin:rsc:mgc_in_wire" {z(74)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(75)} -pin  "vin:rsc:mgc_in_wire" {z(75)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(76)} -pin  "vin:rsc:mgc_in_wire" {z(76)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(77)} -pin  "vin:rsc:mgc_in_wire" {z(77)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(78)} -pin  "vin:rsc:mgc_in_wire" {z(78)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(79)} -pin  "vin:rsc:mgc_in_wire" {z(79)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(80)} -pin  "vin:rsc:mgc_in_wire" {z(80)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(81)} -pin  "vin:rsc:mgc_in_wire" {z(81)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(82)} -pin  "vin:rsc:mgc_in_wire" {z(82)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(83)} -pin  "vin:rsc:mgc_in_wire" {z(83)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(84)} -pin  "vin:rsc:mgc_in_wire" {z(84)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(85)} -pin  "vin:rsc:mgc_in_wire" {z(85)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(86)} -pin  "vin:rsc:mgc_in_wire" {z(86)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(87)} -pin  "vin:rsc:mgc_in_wire" {z(87)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(88)} -pin  "vin:rsc:mgc_in_wire" {z(88)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(89)} -pin  "vin:rsc:mgc_in_wire" {z(89)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load inst "vout:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" -attr xrf 64796 -attr oid 1986 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(2,30)" -pg 1 -lvl 1002
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "vout:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "vout:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "vout:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "vout:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "vout:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "vout:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "vout:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "vout:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "vout:rsc:mgc_out_stdreg" {d(8)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "vout:rsc:mgc_out_stdreg" {d(9)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "vout:rsc:mgc_out_stdreg" {d(10)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "vout:rsc:mgc_out_stdreg" {d(11)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "vout:rsc:mgc_out_stdreg" {d(12)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "vout:rsc:mgc_out_stdreg" {d(13)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "vout:rsc:mgc_out_stdreg" {d(14)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "vout:rsc:mgc_out_stdreg" {d(15)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "vout:rsc:mgc_out_stdreg" {d(16)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "vout:rsc:mgc_out_stdreg" {d(17)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "vout:rsc:mgc_out_stdreg" {d(18)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "vout:rsc:mgc_out_stdreg" {d(19)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "vout:rsc:mgc_out_stdreg" {d(20)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "vout:rsc:mgc_out_stdreg" {d(21)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "vout:rsc:mgc_out_stdreg" {d(22)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "vout:rsc:mgc_out_stdreg" {d(23)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "vout:rsc:mgc_out_stdreg" {d(24)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "vout:rsc:mgc_out_stdreg" {d(25)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "vout:rsc:mgc_out_stdreg" {d(26)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "vout:rsc:mgc_out_stdreg" {d(27)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "vout:rsc:mgc_out_stdreg" {d(28)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "vout:rsc:mgc_out_stdreg" {d(29)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc.z(0)} -pin  "vout:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -pin  "vout:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -pin  "vout:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -pin  "vout:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -pin  "vout:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -pin  "vout:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -pin  "vout:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -pin  "vout:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -pin  "vout:rsc:mgc_out_stdreg" {z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -pin  "vout:rsc:mgc_out_stdreg" {z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -pin  "vout:rsc:mgc_out_stdreg" {z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -pin  "vout:rsc:mgc_out_stdreg" {z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -pin  "vout:rsc:mgc_out_stdreg" {z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -pin  "vout:rsc:mgc_out_stdreg" {z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -pin  "vout:rsc:mgc_out_stdreg" {z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -pin  "vout:rsc:mgc_out_stdreg" {z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -pin  "vout:rsc:mgc_out_stdreg" {z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -pin  "vout:rsc:mgc_out_stdreg" {z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -pin  "vout:rsc:mgc_out_stdreg" {z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -pin  "vout:rsc:mgc_out_stdreg" {z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -pin  "vout:rsc:mgc_out_stdreg" {z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -pin  "vout:rsc:mgc_out_stdreg" {z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -pin  "vout:rsc:mgc_out_stdreg" {z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -pin  "vout:rsc:mgc_out_stdreg" {z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -pin  "vout:rsc:mgc_out_stdreg" {z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -pin  "vout:rsc:mgc_out_stdreg" {z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -pin  "vout:rsc:mgc_out_stdreg" {z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -pin  "vout:rsc:mgc_out_stdreg" {z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -pin  "vout:rsc:mgc_out_stdreg" {z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -pin  "vout:rsc:mgc_out_stdreg" {z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+### END MODULE 
+
diff --git a/Sobel/sobel.v2/concat_rtl.v b/Sobel/sobel.v2/concat_rtl.v
new file mode 100644
index 0000000..06f40dd
--- /dev/null
+++ b/Sobel/sobel.v2/concat_rtl.v
@@ -0,0 +1,2093 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:10:01 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  wire and_dcpl;
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [89:0] regs_regs_2_lpi_1_dfm;
+  reg [15:0] r_0_sva_1;
+  reg [15:0] g_0_sva_1;
+  reg [15:0] b_0_sva_1;
+  reg [15:0] r_2_sva_1;
+  reg [15:0] g_2_sva_1;
+  reg [15:0] b_2_sva_1;
+  reg [1:0] i_6_sva_1;
+  reg exit_FRAME_lpi_1_dfm_1;
+  reg [10:0] FRAME_mul_2_itm_1;
+  wire [21:0] nl_FRAME_mul_2_itm_1;
+  reg [8:0] FRAME_mul_3_itm_1;
+  wire [17:0] nl_FRAME_mul_3_itm_1;
+  reg [5:0] green_slc_green_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_18_itm_1;
+  wire [5:0] nl_FRAME_acc_18_itm_1;
+  reg FRAME_slc_acc_imod_2_4_itm_1;
+  reg green_slc_green_2_sg1_12_itm_1;
+  reg [10:0] FRAME_mul_4_itm_1;
+  wire [21:0] nl_FRAME_mul_4_itm_1;
+  reg [8:0] FRAME_mul_5_itm_1;
+  wire [17:0] nl_FRAME_mul_5_itm_1;
+  reg [5:0] blue_slc_blue_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_30_itm_1;
+  wire [5:0] nl_FRAME_acc_30_itm_1;
+  reg FRAME_slc_acc_imod_4_4_itm_1;
+  reg blue_slc_blue_2_sg1_12_itm_1;
+  reg [8:0] FRAME_mul_1_itm_1;
+  wire [17:0] nl_FRAME_mul_1_itm_1;
+  reg [5:0] red_slc_red_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_37_itm_1;
+  wire [5:0] nl_FRAME_acc_37_itm_1;
+  reg FRAME_slc_acc_imod_4_itm_1;
+  reg exit_FRAME_for_sva_1_st_1;
+  reg main_stage_0_2;
+  reg [1:0] FRAME_acc_41_itm_1_sg2;
+  wire [2:0] nl_FRAME_acc_41_itm_1_sg2;
+  reg [1:0] FRAME_acc_41_itm_1_sg1;
+  reg [5:0] FRAME_acc_41_itm_3;
+  wire [6:0] nl_FRAME_acc_41_itm_3;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+  wire [11:0] FRAME_acc_3_psp_sva;
+  wire [13:0] nl_FRAME_acc_3_psp_sva;
+  wire [11:0] FRAME_acc_4_psp_sva;
+  wire [13:0] nl_FRAME_acc_4_psp_sva;
+  wire [1:0] i_6_sva_2;
+  wire [2:0] nl_i_6_sva_2;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire exit_FRAME_for_lpi_1_dfm;
+  wire [89:0] regs_regs_2_lpi_1_dfm_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire exit_FRAME_lpi_1_dfm_1_mx0;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [5:0] acc_imod_sva;
+  wire [7:0] nl_acc_imod_sva;
+  wire [9:0] FRAME_mul_sdt;
+  wire [19:0] nl_FRAME_mul_sdt;
+  wire [5:0] acc_imod_4_sva;
+  wire [7:0] nl_acc_imod_4_sva;
+  wire [5:0] acc_imod_2_sva;
+  wire [7:0] nl_acc_imod_2_sva;
+  wire [15:0] b_2_sva_3;
+  wire [16:0] nl_b_2_sva_3;
+  wire [15:0] b_0_sva_3;
+  wire [16:0] nl_b_0_sva_3;
+  wire [15:0] g_2_sva_3;
+  wire [16:0] nl_g_2_sva_3;
+  wire [15:0] g_0_sva_3;
+  wire [16:0] nl_g_0_sva_3;
+  wire [15:0] r_2_sva_3;
+  wire [16:0] nl_r_2_sva_3;
+  wire [15:0] r_0_sva_3;
+  wire [16:0] nl_r_0_sva_3;
+  wire FRAME_for_nor_cse;
+  wire [15:0] ACC1_acc_43_itm;
+  wire [16:0] nl_ACC1_acc_43_itm;
+  wire [15:0] ACC1_acc_45_itm;
+  wire [16:0] nl_ACC1_acc_45_itm;
+  wire [15:0] ACC1_acc_44_itm;
+  wire [16:0] nl_ACC1_acc_44_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_3_itm;
+
+  wire[15:0] FRAME_for_mux_10_nl;
+  wire[9:0] regs_operator_17_mux_nl;
+  wire[15:0] FRAME_for_mux_9_nl;
+  wire[9:0] regs_operator_11_mux_nl;
+  wire[15:0] FRAME_for_mux_8_nl;
+  wire[9:0] regs_operator_16_mux_nl;
+  wire[15:0] FRAME_for_mux_7_nl;
+  wire[9:0] regs_operator_10_mux_nl;
+  wire[15:0] FRAME_for_mux_6_nl;
+  wire[9:0] regs_operator_15_mux_nl;
+  wire[15:0] FRAME_for_mux_5_nl;
+  wire[9:0] regs_operator_9_mux_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_3_psp_sva = (conv_u2s_11_12(FRAME_mul_2_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_3_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(green_slc_green_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_18_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_2_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({green_slc_green_2_sg1_12_itm_1
+      , 3'b0 , ({{2{green_slc_green_2_sg1_12_itm_1}}, green_slc_green_2_sg1_12_itm_1})
+      , 1'b0 , green_slc_green_2_sg1_12_itm_1}));
+  assign FRAME_acc_3_psp_sva = nl_FRAME_acc_3_psp_sva[11:0];
+  assign nl_FRAME_acc_4_psp_sva = (conv_u2s_11_12(FRAME_mul_4_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_5_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(blue_slc_blue_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_30_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_4_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({blue_slc_blue_2_sg1_12_itm_1
+      , 3'b0 , ({{2{blue_slc_blue_2_sg1_12_itm_1}}, blue_slc_blue_2_sg1_12_itm_1})
+      , 1'b0 , blue_slc_blue_2_sg1_12_itm_1}));
+  assign FRAME_acc_4_psp_sva = nl_FRAME_acc_4_psp_sva[11:0];
+  assign nl_FRAME_for_acc_itm = i_6_sva_2 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  assign nl_i_6_sva_2 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_2 = nl_i_6_sva_2[1:0];
+  assign i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm));
+  assign exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva;
+  assign regs_regs_2_lpi_1_dfm_mx0 = MUX_v_90_2_2({regs_regs_1_sva , regs_regs_2_lpi_1_dfm},
+      and_dcpl);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_dcpl);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_dcpl);
+  assign exit_FRAME_lpi_1_dfm_1_mx0 = MUX_s_1_2_2({(~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+      + 8'b10110101)))) , (exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm))},
+      FRAME_for_acc_itm[1]);
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign nl_acc_imod_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_43_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_43_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_43_itm[15])) , 1'b1 , (~ (ACC1_acc_43_itm[15]))}) + conv_u2u_2_4(ACC1_acc_43_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_43_itm[3:1]) + conv_u2u_3_4(~ (ACC1_acc_43_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_sva = nl_acc_imod_sva[5:0];
+  assign nl_ACC1_acc_43_itm = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[59:50])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[59:50])
+      , 1'b1})))) + (r_2_sva_3[15:1])) , (readslicef_2_1_1((({(r_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + r_0_sva_3;
+  assign ACC1_acc_43_itm = nl_ACC1_acc_43_itm[15:0];
+  assign nl_FRAME_mul_sdt = conv_u2u_2_10(ACC1_acc_43_itm[14:13]) * 10'b111000111;
+  assign FRAME_mul_sdt = nl_FRAME_mul_sdt[9:0];
+  assign nl_ACC1_acc_45_itm = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[39:30])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[39:30])
+      , 1'b1})))) + (b_2_sva_3[15:1])) , (readslicef_2_1_1((({(b_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + b_0_sva_3;
+  assign ACC1_acc_45_itm = nl_ACC1_acc_45_itm[15:0];
+  assign nl_acc_imod_4_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_45_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_45_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_45_itm[15])) , 1'b1 , (~ (ACC1_acc_45_itm[15]))}) + conv_u2u_2_4(ACC1_acc_45_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_45_itm[3:1]) + conv_u2u_3_4(~ (ACC1_acc_45_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_4_sva = nl_acc_imod_4_sva[5:0];
+  assign nl_ACC1_acc_44_itm = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[49:40])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[49:40])
+      , 1'b1})))) + (g_2_sva_3[15:1])) , (readslicef_2_1_1((({(g_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + g_0_sva_3;
+  assign ACC1_acc_44_itm = nl_ACC1_acc_44_itm[15:0];
+  assign nl_acc_imod_2_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_44_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_44_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_44_itm[15])) , 1'b1 , (~ (ACC1_acc_44_itm[15]))}) + conv_u2u_2_4(ACC1_acc_44_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_44_itm[3:1]) + conv_u2u_3_4(~ (ACC1_acc_44_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_2_sva = nl_acc_imod_2_sva[5:0];
+  assign FRAME_for_mux_10_nl = MUX_v_16_2_2({b_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[69:60])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[69:60])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+      , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_mx0[69:60]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_b_2_sva_3 = (FRAME_for_mux_10_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_17_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign b_2_sva_3 = nl_b_2_sva_3[15:0];
+  assign FRAME_for_mux_9_nl = MUX_v_16_2_2({b_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[9:0])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[9:0])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_11_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0]) ,
+      (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_mx0[9:0]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_b_0_sva_3 = (FRAME_for_mux_9_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_11_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign b_0_sva_3 = nl_b_0_sva_3[15:0];
+  assign FRAME_for_mux_8_nl = MUX_v_16_2_2({g_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[79:70])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[79:70])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+      , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_mx0[79:70]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_g_2_sva_3 = (FRAME_for_mux_8_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_16_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign g_2_sva_3 = nl_g_2_sva_3[15:0];
+  assign FRAME_for_mux_7_nl = MUX_v_16_2_2({g_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[19:10])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[19:10])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_10_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+      , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_mx0[19:10]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_g_0_sva_3 = (FRAME_for_mux_7_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_10_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign g_0_sva_3 = nl_g_0_sva_3[15:0];
+  assign FRAME_for_mux_6_nl = MUX_v_16_2_2({r_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[89:80])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[89:80])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+      , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_mx0[89:80]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_r_2_sva_3 = (FRAME_for_mux_6_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_15_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign r_2_sva_3 = nl_r_2_sva_3[15:0];
+  assign FRAME_for_mux_5_nl = MUX_v_16_2_2({r_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[29:20])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[29:20])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_9_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+      , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_mx0[29:20]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_r_0_sva_3 = (FRAME_for_mux_5_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_9_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign r_0_sva_3 = nl_r_0_sva_3[15:0];
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_3_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) |
+      FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+  assign and_dcpl = ~(exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva);
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      FRAME_acc_41_itm_1_sg2 <= 2'b0;
+      FRAME_acc_41_itm_1_sg1 <= 2'b0;
+      FRAME_acc_41_itm_3 <= 6'b0;
+      FRAME_mul_1_itm_1 <= 9'b0;
+      red_slc_red_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_37_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_4_itm_1 <= 1'b0;
+      FRAME_mul_4_itm_1 <= 11'b0;
+      FRAME_mul_5_itm_1 <= 9'b0;
+      blue_slc_blue_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_30_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_4_4_itm_1 <= 1'b0;
+      blue_slc_blue_2_sg1_12_itm_1 <= 1'b0;
+      FRAME_mul_2_itm_1 <= 11'b0;
+      FRAME_mul_3_itm_1 <= 9'b0;
+      green_slc_green_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_18_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_2_4_itm_1 <= 1'b0;
+      green_slc_green_2_sg1_12_itm_1 <= 1'b0;
+      exit_FRAME_for_sva_1_st_1 <= 1'b0;
+      i_6_sva_1 <= 2'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_2_lpi_1_dfm <= 90'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_1 <= 1'b0;
+      b_2_sva_1 <= 16'b0;
+      b_0_sva_1 <= 16'b0;
+      g_2_sva_1 <= 16'b0;
+      g_0_sva_1 <= 16'b0;
+      r_2_sva_1 <= 16'b0;
+      r_0_sva_1 <= 16'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({({((({FRAME_acc_41_itm_1_sg2 ,
+            FRAME_acc_41_itm_1_sg1 , FRAME_acc_41_itm_3}) + (conv_u2s_9_10(FRAME_mul_1_itm_1)
+            + conv_s2s_8_10(conv_u2s_6_8(red_slc_red_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_37_itm_1
+            + ({4'b1001 , FRAME_slc_acc_imod_4_itm_1}))))) | ({8'b0 , (FRAME_acc_3_psp_sva[11:10])}))
+            , (FRAME_acc_3_psp_sva[9:6]) , ((FRAME_acc_3_psp_sva[5:0]) | ({4'b0 ,
+            (FRAME_acc_4_psp_sva[11:10])})) , (FRAME_acc_4_psp_sva[9:0])}) , vout_rsc_mgc_out_stdreg_d},
+            ~(exit_FRAME_for_sva_1_st_1 & main_stage_0_2));
+        FRAME_acc_41_itm_1_sg2 <= nl_FRAME_acc_41_itm_1_sg2[1:0];
+        FRAME_acc_41_itm_1_sg1 <= FRAME_mul_sdt[7:6];
+        FRAME_acc_41_itm_3 <= nl_FRAME_acc_41_itm_3[5:0];
+        FRAME_mul_1_itm_1 <= nl_FRAME_mul_1_itm_1[8:0];
+        red_slc_red_2_sg1_itm_1 <= ACC1_acc_43_itm[9:4];
+        FRAME_acc_37_itm_1 <= nl_FRAME_acc_37_itm_1[4:0];
+        FRAME_slc_acc_imod_4_itm_1 <= acc_imod_sva[5];
+        FRAME_mul_4_itm_1 <= nl_FRAME_mul_4_itm_1[10:0];
+        FRAME_mul_5_itm_1 <= nl_FRAME_mul_5_itm_1[8:0];
+        blue_slc_blue_2_sg1_itm_1 <= ACC1_acc_45_itm[9:4];
+        FRAME_acc_30_itm_1 <= nl_FRAME_acc_30_itm_1[4:0];
+        FRAME_slc_acc_imod_4_4_itm_1 <= acc_imod_4_sva[5];
+        blue_slc_blue_2_sg1_12_itm_1 <= ACC1_acc_45_itm[15];
+        FRAME_mul_2_itm_1 <= nl_FRAME_mul_2_itm_1[10:0];
+        FRAME_mul_3_itm_1 <= nl_FRAME_mul_3_itm_1[8:0];
+        green_slc_green_2_sg1_itm_1 <= ACC1_acc_44_itm[9:4];
+        FRAME_acc_18_itm_1 <= nl_FRAME_acc_18_itm_1[4:0];
+        FRAME_slc_acc_imod_2_4_itm_1 <= acc_imod_2_sva[5];
+        green_slc_green_2_sg1_12_itm_1 <= ACC1_acc_44_itm[15];
+        exit_FRAME_for_sva_1_st_1 <= ~ (FRAME_for_acc_itm[1]);
+        i_6_sva_1 <= i_6_sva_2;
+        exit_FRAME_1_sva <= (~ (FRAME_for_acc_itm[1])) & exit_FRAME_lpi_1_dfm_1_mx0;
+        main_stage_0_2 <= 1'b1;
+        regs_regs_2_lpi_1_dfm <= regs_regs_2_lpi_1_dfm_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_1 <= exit_FRAME_lpi_1_dfm_1_mx0;
+        b_2_sva_1 <= b_2_sva_3;
+        b_0_sva_1 <= b_0_sva_3;
+        g_2_sva_1 <= g_2_sva_3;
+        g_0_sva_1 <= g_0_sva_3;
+        r_2_sva_1 <= r_2_sva_3;
+        r_0_sva_1 <= r_0_sva_3;
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_sva_1 , FRAME_p_1_lpi_1_dfm},
+            FRAME_for_acc_itm[1]);
+      end
+    end
+  end
+  assign nl_FRAME_acc_41_itm_1_sg2  = (FRAME_mul_sdt[9:8]) + conv_s2u_1_2(ACC1_acc_43_itm[15]);
+  assign nl_FRAME_acc_41_itm_3  = conv_u2u_5_6(FRAME_mul_sdt[4:0]) + conv_u2u_5_6(signext_5_3({(ACC1_acc_43_itm[15])
+      , 1'b0 , (ACC1_acc_43_itm[15])}));
+  assign nl_FRAME_mul_1_itm_1  = conv_u2u_3_9(ACC1_acc_43_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_37_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_sva[5:3])) , (~ (acc_imod_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC1_acc_43_itm[9:7]));
+  assign nl_FRAME_mul_4_itm_1  = conv_u2u_2_11(ACC1_acc_45_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_5_itm_1  = conv_u2u_3_9(ACC1_acc_45_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_30_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_4_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_4_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_4_sva[5:3])) , (~ (acc_imod_4_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_4_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC1_acc_45_itm[9:7]));
+  assign nl_FRAME_mul_2_itm_1  = conv_u2u_2_11(ACC1_acc_44_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_3_itm_1  = conv_u2u_3_9(ACC1_acc_44_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_18_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_2_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_2_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_2_sva[5:3])) , (~ (acc_imod_2_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_2_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC1_acc_44_itm[9:7]));
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_2_1_1;
+    input [1:0] vector;
+    reg [1:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_2_1_1 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [15:0] signext_16_11;
+    input [10:0] vector;
+  begin
+    signext_16_11= {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_11_15 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_15 = {{4{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_s2u_1_2 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_2 = {vector[0], vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v2/cycle.rpt b/Sobel/sobel.v2/cycle.rpt
new file mode 100644
index 0000000..7d24aaf
--- /dev/null
+++ b/Sobel/sobel.v2/cycle.rpt
@@ -0,0 +1,85 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 14:09:35 +0000 2016                      
+
+Solution Settings: sobel.v2
+  Current state: schedule
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       161  921601     921600            0  1          
+    Design Total:                     161  921601     921600            0  0          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /sobel/core              
+    
+  I/O Data Ranges
+    Port       Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ---------- ---- -------- --------- --------- ------- -------- --------
+    vin:rsc.z  IN   Unsigned        90                                     
+    clk        IN   Unsigned         1                                     
+    en         IN   Unsigned         1                                     
+    arst_n     IN   Unsigned         1                                     
+    vout:rsc.z OUT  Unsigned        30                                     
+    
+  Memory Resources
+    Resource Name: /sobel/vin:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 90
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable   Indices Phys Memory Address     
+      ---------- ------- -----------------------
+      /sobel/vin    0:89 00000000-00000000 (0-0) 
+      
+    Resource Name: /sobel/vout:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 30
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable    Indices Phys Memory Address     
+      ----------- ------- -----------------------
+      /sobel/vout    0:29 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process     Loop             Iterations C-Steps Total Cycles  Duration  Unroll Init Comments 
+    ----------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
+    /sobel/core core:rlp           Infinite       0       921602  18.43 ms                       
+    /sobel/core   main             Infinite       3       921602  18.43 ms            1          
+    
+  Loop Execution Profile
+    Process     Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------- ---------------- ------------ -------------------------- ----------------- --------
+    /sobel/core core:rlp                   0                        0.00           921600           
+    /sobel/core   main                921602                      100.00           921600           
+    
+  End of Report
diff --git a/Sobel/sobel.v2/cycle.v b/Sobel/sobel.v2/cycle.v
new file mode 100644
index 0000000..ac4b67d
--- /dev/null
+++ b/Sobel/sobel.v2/cycle.v
@@ -0,0 +1,910 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:09:36 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg [18:0] FRAME_p_1_lpi_1;
+    reg [89:0] regs_regs_1_sva;
+    reg [89:0] regs_regs_0_sva;
+    reg exit_FRAME_1_sva;
+    reg [18:0] FRAME_p_1_lpi_1_dfm;
+    reg exit_FRAME_for_lpi_1_dfm;
+    reg [89:0] regs_regs_0_sva_1;
+    reg [89:0] regs_regs_0_sva_dfm;
+    reg [89:0] regs_regs_1_sva_dfm;
+    reg [89:0] regs_regs_2_lpi_1_dfm;
+    reg [1:0] i_6_lpi_1_dfm;
+    reg FRAME_for_slc_YMATRIX_rom_11_psp_sva;
+    reg [15:0] r_0_sva_1;
+    reg [15:0] g_0_sva_1;
+    reg [15:0] b_0_sva_1;
+    reg [15:0] r_2_sva_1;
+    reg [15:0] g_2_sva_1;
+    reg [15:0] b_2_sva_1;
+    reg [1:0] i_6_sva_1;
+    reg exit_FRAME_for_sva_1;
+    reg [14:0] red_2_sg1_sva;
+    reg [14:0] green_2_sg1_sva;
+    reg [14:0] blue_2_sg1_sva;
+    reg [5:0] acc_imod_sva;
+    reg [5:0] acc_imod_2_sva;
+    reg [11:0] FRAME_acc_3_psp_sva;
+    reg [5:0] acc_imod_4_sva;
+    reg [11:0] FRAME_acc_4_psp_sva;
+    reg [18:0] FRAME_p_1_sva_1;
+    reg exit_FRAME_lpi_1_dfm_1;
+    reg exit_FRAME_for_lpi_1_dfm_2;
+    reg [10:0] FRAME_mul_2_itm;
+    reg [10:0] FRAME_mul_2_itm_1;
+    reg [8:0] FRAME_mul_3_itm;
+    reg [8:0] FRAME_mul_3_itm_1;
+    reg [5:0] green_slc_green_2_sg1_itm;
+    reg [5:0] green_slc_green_2_sg1_itm_1;
+    reg [4:0] FRAME_acc_18_itm;
+    reg [4:0] FRAME_acc_18_itm_1;
+    reg FRAME_slc_acc_imod_2_4_itm;
+    reg FRAME_slc_acc_imod_2_4_itm_1;
+    reg green_slc_green_2_sg1_12_itm;
+    reg green_slc_green_2_sg1_12_itm_1;
+    reg green_slc_green_2_sg1_13_itm;
+    reg green_slc_green_2_sg1_13_itm_1;
+    reg green_slc_green_2_sg1_8_itm;
+    reg green_slc_green_2_sg1_8_itm_1;
+    reg [10:0] FRAME_mul_4_itm;
+    reg [10:0] FRAME_mul_4_itm_1;
+    reg [8:0] FRAME_mul_5_itm;
+    reg [8:0] FRAME_mul_5_itm_1;
+    reg [5:0] blue_slc_blue_2_sg1_itm;
+    reg [5:0] blue_slc_blue_2_sg1_itm_1;
+    reg [4:0] FRAME_acc_30_itm;
+    reg [4:0] FRAME_acc_30_itm_1;
+    reg FRAME_slc_acc_imod_4_4_itm;
+    reg FRAME_slc_acc_imod_4_4_itm_1;
+    reg blue_slc_blue_2_sg1_12_itm;
+    reg blue_slc_blue_2_sg1_12_itm_1;
+    reg blue_slc_blue_2_sg1_13_itm;
+    reg blue_slc_blue_2_sg1_13_itm_1;
+    reg blue_slc_blue_2_sg1_8_itm;
+    reg blue_slc_blue_2_sg1_8_itm_1;
+    reg [8:0] FRAME_mul_1_itm;
+    reg [8:0] FRAME_mul_1_itm_1;
+    reg [5:0] red_slc_red_2_sg1_itm;
+    reg [5:0] red_slc_red_2_sg1_itm_1;
+    reg [4:0] FRAME_acc_37_itm;
+    reg [4:0] FRAME_acc_37_itm_1;
+    reg FRAME_slc_acc_imod_4_itm;
+    reg FRAME_slc_acc_imod_4_itm_1;
+    reg exit_FRAME_for_sva_1_st_1;
+    reg main_stage_0_2;
+    reg [10:0] r_0_sva_2;
+    reg [10:0] g_0_sva_2;
+    reg [10:0] b_0_sva_2;
+    reg [10:0] r_2_sva_2;
+    reg [10:0] g_2_sva_2;
+    reg [10:0] b_2_sva_2;
+    reg [9:0] FRAME_mul_sdt;
+    reg FRAME_for_nor_cse;
+    reg FRAME_for_slc_XMATRIX_rom_11_psp_sva_1;
+    reg [1:0] FRAME_acc_41_itm_sg2;
+    reg [1:0] FRAME_acc_41_itm_sg1;
+    reg [5:0] FRAME_acc_41_itm_2;
+    reg [1:0] FRAME_acc_41_itm_1_sg2;
+    reg [1:0] FRAME_acc_41_itm_1_sg1;
+    reg [5:0] FRAME_acc_41_itm_3;
+
+    reg[15:0] FRAME_for_mux_5_nl;
+    reg[9:0] regs_operator_9_mux_nl;
+    reg[15:0] FRAME_for_mux_7_nl;
+    reg[9:0] regs_operator_10_mux_nl;
+    reg[15:0] FRAME_for_mux_9_nl;
+    reg[9:0] regs_operator_11_mux_nl;
+    reg[15:0] FRAME_for_mux_6_nl;
+    reg[9:0] regs_operator_15_mux_nl;
+    reg[15:0] FRAME_for_mux_8_nl;
+    reg[9:0] regs_operator_16_mux_nl;
+    reg[15:0] FRAME_for_mux_10_nl;
+    reg[9:0] regs_operator_17_mux_nl;
+    begin : core_rlpExit
+      forever begin : core_rlp
+        // C-Step 0 of Loop 'core_rlp'
+        FRAME_p_1_lpi_1 = 19'b0;
+        regs_regs_1_sva = 90'b0;
+        regs_regs_0_sva = 90'b0;
+        exit_FRAME_1_sva = 1'b1;
+        main_stage_0_2 = 1'b0;
+        begin : mainExit
+          forever begin : main
+            // C-Step 0 of Loop 'main'
+            begin : waitLoop0Exit
+              forever begin : waitLoop0
+                @(posedge clk or negedge ( arst_n ));
+                if ( ~ arst_n )
+                  disable core_rlpExit;
+                if ( en )
+                  disable waitLoop0Exit;
+              end
+            end
+            // C-Step 1 of Loop 'main'
+            if ( main_stage_0_2 ) begin
+              if ( exit_FRAME_for_sva_1_st_1 ) begin
+                FRAME_acc_3_psp_sva = (conv_u2s_11_12(FRAME_mul_2_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_3_itm_1)
+                    + conv_s2s_8_10(conv_u2s_6_8(green_slc_green_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_18_itm_1
+                    + ({4'b1001 , FRAME_slc_acc_imod_2_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({green_slc_green_2_sg1_12_itm_1
+                    , 3'b0 , ({{2{green_slc_green_2_sg1_13_itm_1}}, green_slc_green_2_sg1_13_itm_1})
+                    , 1'b0 , green_slc_green_2_sg1_8_itm_1}));
+                FRAME_acc_4_psp_sva = (conv_u2s_11_12(FRAME_mul_4_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_5_itm_1)
+                    + conv_s2s_8_10(conv_u2s_6_8(blue_slc_blue_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_30_itm_1
+                    + ({4'b1001 , FRAME_slc_acc_imod_4_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({blue_slc_blue_2_sg1_12_itm_1
+                    , 3'b0 , ({{2{blue_slc_blue_2_sg1_13_itm_1}}, blue_slc_blue_2_sg1_13_itm_1})
+                    , 1'b0 , blue_slc_blue_2_sg1_8_itm_1}));
+                vout_rsc_mgc_out_stdreg_d <= {((({FRAME_acc_41_itm_1_sg2 , FRAME_acc_41_itm_1_sg1
+                    , FRAME_acc_41_itm_3}) + (conv_u2s_9_10(FRAME_mul_1_itm_1) +
+                    conv_s2s_8_10(conv_u2s_6_8(red_slc_red_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_37_itm_1
+                    + ({4'b1001 , FRAME_slc_acc_imod_4_itm_1}))))) | ({8'b0, FRAME_acc_3_psp_sva[11:10]}))
+                    , (FRAME_acc_3_psp_sva[9:6]) , ((FRAME_acc_3_psp_sva[5:0]) |
+                    ({4'b0, FRAME_acc_4_psp_sva[11:10]})) , (FRAME_acc_4_psp_sva[9:0])};
+              end
+            end
+            FRAME_p_1_sva_1 = 19'b0;
+            b_2_sva_2 = 11'b0;
+            g_2_sva_2 = 11'b0;
+            r_2_sva_2 = 11'b0;
+            b_0_sva_2 = 11'b0;
+            g_0_sva_2 = 11'b0;
+            r_0_sva_2 = 11'b0;
+            FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+            exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_lpi_1_dfm_2 | exit_FRAME_1_sva;
+            if ( exit_FRAME_for_lpi_1_dfm ) begin
+              regs_regs_0_sva_1 = vin_rsc_mgc_in_wire_d;
+              r_0_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[29:20]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[29:20]) , 1'b1})));
+              g_0_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[19:10]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[19:10]) , 1'b1})));
+              b_0_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[9:0]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[9:0]) , 1'b1})));
+              r_2_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[89:80]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[89:80]) , 1'b1})));
+              g_2_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[79:70]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[79:70]) , 1'b1})));
+              b_2_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[69:60]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[69:60]) , 1'b1})));
+              regs_regs_0_sva_dfm = regs_regs_0_sva_1;
+              regs_regs_1_sva_dfm = regs_regs_0_sva;
+              regs_regs_2_lpi_1_dfm = regs_regs_1_sva;
+            end
+            else begin
+              regs_regs_0_sva_dfm = regs_regs_0_sva;
+              regs_regs_1_sva_dfm = regs_regs_1_sva;
+            end
+            i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm));
+            FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+            FRAME_for_slc_YMATRIX_rom_11_psp_sva = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1]))))
+                | FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+            FRAME_for_mux_5_nl = MUX_v_16_2_2({r_0_sva_1 , ({{5{r_0_sva_2[10]}},
+                r_0_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_9_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[29:20]) ,
+                (regs_regs_1_sva_dfm[29:20]) , (regs_regs_2_lpi_1_dfm[29:20]) , 10'b0},
+                i_6_lpi_1_dfm);
+            r_0_sva_1 = (FRAME_for_mux_5_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_9_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva})));
+            FRAME_for_mux_7_nl = MUX_v_16_2_2({g_0_sva_1 , ({{5{g_0_sva_2[10]}},
+                g_0_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_10_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[19:10])
+                , (regs_regs_1_sva_dfm[19:10]) , (regs_regs_2_lpi_1_dfm[19:10]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            g_0_sva_1 = (FRAME_for_mux_7_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_10_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva})));
+            FRAME_for_mux_9_nl = MUX_v_16_2_2({b_0_sva_1 , ({{5{b_0_sva_2[10]}},
+                b_0_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_11_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[9:0]) ,
+                (regs_regs_1_sva_dfm[9:0]) , (regs_regs_2_lpi_1_dfm[9:0]) , 10'b0},
+                i_6_lpi_1_dfm);
+            b_0_sva_1 = (FRAME_for_mux_9_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_11_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva})));
+            FRAME_for_slc_XMATRIX_rom_11_psp_sva_1 = (~((~ (i_6_lpi_1_dfm[1])) &
+                (i_6_lpi_1_dfm[0]))) | FRAME_for_nor_cse;
+            FRAME_for_mux_6_nl = MUX_v_16_2_2({r_2_sva_1 , ({{5{r_2_sva_2[10]}},
+                r_2_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[89:80])
+                , (regs_regs_1_sva_dfm[89:80]) , (regs_regs_2_lpi_1_dfm[89:80]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            r_2_sva_1 = (FRAME_for_mux_6_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_15_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+            FRAME_for_mux_8_nl = MUX_v_16_2_2({g_2_sva_1 , ({{5{g_2_sva_2[10]}},
+                g_2_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[79:70])
+                , (regs_regs_1_sva_dfm[79:70]) , (regs_regs_2_lpi_1_dfm[79:70]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            g_2_sva_1 = (FRAME_for_mux_8_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_16_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+            FRAME_for_mux_10_nl = MUX_v_16_2_2({b_2_sva_1 , ({{5{b_2_sva_2[10]}},
+                b_2_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[69:60])
+                , (regs_regs_1_sva_dfm[69:60]) , (regs_regs_2_lpi_1_dfm[69:60]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            b_2_sva_1 = (FRAME_for_mux_10_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_17_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+            i_6_sva_1 = i_6_lpi_1_dfm + 2'b1;
+            exit_FRAME_for_sva_1 = ~ (readslicef_3_1_2((({1'b1 , i_6_sva_1}) + 3'b1)));
+            if ( exit_FRAME_for_sva_1 ) begin
+              red_2_sg1_sva = readslicef_16_15_1((({(conv_s2u_10_15(~ (regs_regs_0_sva_dfm[59:50]))
+                  + conv_s2u_10_15(regs_regs_2_lpi_1_dfm[59:50]) + (r_2_sva_1[15:1])
+                  + 15'b1) , (readslicef_2_1_1((({(r_2_sva_1[0]) , 1'b1}) + 2'b11)))})
+                  + r_0_sva_1));
+              green_2_sg1_sva = readslicef_16_15_1((({(conv_s2u_10_15(~ (regs_regs_0_sva_dfm[49:40]))
+                  + conv_s2u_10_15(regs_regs_2_lpi_1_dfm[49:40]) + (g_2_sva_1[15:1])
+                  + 15'b1) , (readslicef_2_1_1((({(g_2_sva_1[0]) , 1'b1}) + 2'b11)))})
+                  + g_0_sva_1));
+              blue_2_sg1_sva = readslicef_16_15_1((({(conv_s2u_10_15(~ (regs_regs_0_sva_dfm[39:30]))
+                  + conv_s2u_10_15(regs_regs_2_lpi_1_dfm[39:30]) + (b_2_sva_1[15:1])
+                  + 15'b1) , (readslicef_2_1_1((({(b_2_sva_1[0]) , 1'b1}) + 2'b11)))})
+                  + b_0_sva_1));
+              acc_imod_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(red_2_sg1_sva[8:6])
+                  + conv_u2u_3_4(~ (red_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                  (red_2_sg1_sva[14])) , 1'b1 , (~ (red_2_sg1_sva[14]))}) + conv_u2u_2_4(red_2_sg1_sva[13:12])))
+                  + conv_u2u_4_6(conv_u2u_3_4(red_2_sg1_sva[2:0]) + conv_u2u_3_4(~
+                  (red_2_sg1_sva[5:3])))) + 6'b101011;
+              acc_imod_2_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(green_2_sg1_sva[8:6])
+                  + conv_u2u_3_4(~ (green_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                  (green_2_sg1_sva[14])) , 1'b1 , (~ (green_2_sg1_sva[14]))}) + conv_u2u_2_4(green_2_sg1_sva[13:12])))
+                  + conv_u2u_4_6(conv_u2u_3_4(green_2_sg1_sva[2:0]) + conv_u2u_3_4(~
+                  (green_2_sg1_sva[5:3])))) + 6'b101011;
+              FRAME_mul_2_itm = conv_u2u_22_11(conv_u2u_2_11(green_2_sg1_sva[13:12])
+                  * 11'b111000111);
+              FRAME_mul_3_itm = conv_u2u_18_9(conv_u2u_3_9(green_2_sg1_sva[11:9])
+                  * 9'b111001);
+              green_slc_green_2_sg1_itm = green_2_sg1_sva[8:3];
+              FRAME_acc_18_itm = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_2_sva[5]))
+                  , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_2_sva[2:0]) ,
+                  1'b1}) + conv_u2s_4_5({(~ (acc_imod_2_sva[5:3])) , (~ (acc_imod_2_sva[5]))})))))})
+                  + conv_u2u_2_4(acc_imod_2_sva[4:3])) + conv_u2u_3_5(~ (green_2_sg1_sva[8:6]));
+              FRAME_slc_acc_imod_2_4_itm = acc_imod_2_sva[5];
+              green_slc_green_2_sg1_12_itm = green_2_sg1_sva[14];
+              green_slc_green_2_sg1_13_itm = green_2_sg1_sva[14];
+              green_slc_green_2_sg1_8_itm = green_2_sg1_sva[14];
+              acc_imod_4_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(blue_2_sg1_sva[8:6])
+                  + conv_u2u_3_4(~ (blue_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                  (blue_2_sg1_sva[14])) , 1'b1 , (~ (blue_2_sg1_sva[14]))}) + conv_u2u_2_4(blue_2_sg1_sva[13:12])))
+                  + conv_u2u_4_6(conv_u2u_3_4(blue_2_sg1_sva[2:0]) + conv_u2u_3_4(~
+                  (blue_2_sg1_sva[5:3])))) + 6'b101011;
+              FRAME_mul_4_itm = conv_u2u_22_11(conv_u2u_2_11(blue_2_sg1_sva[13:12])
+                  * 11'b111000111);
+              FRAME_mul_5_itm = conv_u2u_18_9(conv_u2u_3_9(blue_2_sg1_sva[11:9])
+                  * 9'b111001);
+              blue_slc_blue_2_sg1_itm = blue_2_sg1_sva[8:3];
+              FRAME_acc_30_itm = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_4_sva[5]))
+                  , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_4_sva[2:0]) ,
+                  1'b1}) + conv_u2s_4_5({(~ (acc_imod_4_sva[5:3])) , (~ (acc_imod_4_sva[5]))})))))})
+                  + conv_u2u_2_4(acc_imod_4_sva[4:3])) + conv_u2u_3_5(~ (blue_2_sg1_sva[8:6]));
+              FRAME_slc_acc_imod_4_4_itm = acc_imod_4_sva[5];
+              blue_slc_blue_2_sg1_12_itm = blue_2_sg1_sva[14];
+              blue_slc_blue_2_sg1_13_itm = blue_2_sg1_sva[14];
+              blue_slc_blue_2_sg1_8_itm = blue_2_sg1_sva[14];
+              FRAME_mul_sdt = conv_u2u_20_10(conv_u2u_2_10(red_2_sg1_sva[13:12])
+                  * 10'b111000111);
+              FRAME_acc_41_itm_sg1 = FRAME_mul_sdt[7:6];
+              FRAME_acc_41_itm_2 = conv_u2u_5_6(FRAME_mul_sdt[4:0]) + conv_u2u_5_6(signext_5_3({(red_2_sg1_sva[14])
+                  , 1'b0 , (red_2_sg1_sva[14])}));
+              FRAME_acc_41_itm_sg2 = (FRAME_mul_sdt[9:8]) + conv_s2u_1_2(red_2_sg1_sva[14]);
+              FRAME_mul_1_itm = conv_u2u_18_9(conv_u2u_3_9(red_2_sg1_sva[11:9]) *
+                  9'b111001);
+              red_slc_red_2_sg1_itm = red_2_sg1_sva[8:3];
+              FRAME_acc_37_itm = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_sva[5]))
+                  , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_sva[2:0]) , 1'b1})
+                  + conv_u2s_4_5({(~ (acc_imod_sva[5:3])) , (~ (acc_imod_sva[5]))})))))})
+                  + conv_u2u_2_4(acc_imod_sva[4:3])) + conv_u2u_3_5(~ (red_2_sg1_sva[8:6]));
+              FRAME_slc_acc_imod_4_itm = acc_imod_sva[5];
+              FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+              exit_FRAME_lpi_1_dfm_1 = ~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+                  + 8'b10110101)));
+            end
+            else begin
+              exit_FRAME_lpi_1_dfm_1 = exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm);
+            end
+            exit_FRAME_for_lpi_1_dfm_2 = exit_FRAME_for_sva_1;
+            regs_regs_0_sva = regs_regs_0_sva_dfm;
+            regs_regs_1_sva = regs_regs_1_sva_dfm;
+            FRAME_p_1_lpi_1 = MUX_v_19_2_2({FRAME_p_1_lpi_1_dfm , FRAME_p_1_sva_1},
+                exit_FRAME_for_sva_1);
+            exit_FRAME_1_sva = exit_FRAME_for_sva_1 & exit_FRAME_lpi_1_dfm_1;
+            FRAME_mul_2_itm_1 = FRAME_mul_2_itm;
+            FRAME_mul_3_itm_1 = FRAME_mul_3_itm;
+            green_slc_green_2_sg1_itm_1 = green_slc_green_2_sg1_itm;
+            FRAME_acc_18_itm_1 = FRAME_acc_18_itm;
+            FRAME_slc_acc_imod_2_4_itm_1 = FRAME_slc_acc_imod_2_4_itm;
+            green_slc_green_2_sg1_12_itm_1 = green_slc_green_2_sg1_12_itm;
+            green_slc_green_2_sg1_13_itm_1 = green_slc_green_2_sg1_13_itm;
+            green_slc_green_2_sg1_8_itm_1 = green_slc_green_2_sg1_8_itm;
+            FRAME_mul_4_itm_1 = FRAME_mul_4_itm;
+            FRAME_mul_5_itm_1 = FRAME_mul_5_itm;
+            blue_slc_blue_2_sg1_itm_1 = blue_slc_blue_2_sg1_itm;
+            FRAME_acc_30_itm_1 = FRAME_acc_30_itm;
+            FRAME_slc_acc_imod_4_4_itm_1 = FRAME_slc_acc_imod_4_4_itm;
+            blue_slc_blue_2_sg1_12_itm_1 = blue_slc_blue_2_sg1_12_itm;
+            blue_slc_blue_2_sg1_13_itm_1 = blue_slc_blue_2_sg1_13_itm;
+            blue_slc_blue_2_sg1_8_itm_1 = blue_slc_blue_2_sg1_8_itm;
+            FRAME_acc_41_itm_1_sg1 = FRAME_acc_41_itm_sg1;
+            FRAME_acc_41_itm_3 = FRAME_acc_41_itm_2;
+            FRAME_acc_41_itm_1_sg2 = FRAME_acc_41_itm_sg2;
+            FRAME_mul_1_itm_1 = FRAME_mul_1_itm;
+            red_slc_red_2_sg1_itm_1 = red_slc_red_2_sg1_itm;
+            FRAME_acc_37_itm_1 = FRAME_acc_37_itm;
+            FRAME_slc_acc_imod_4_itm_1 = FRAME_slc_acc_imod_4_itm;
+            exit_FRAME_for_sva_1_st_1 = exit_FRAME_for_sva_1;
+            main_stage_0_2 = 1'b1;
+          end
+        end
+      end
+    end
+    FRAME_acc_41_itm_3 = 6'b0;
+    FRAME_acc_41_itm_1_sg1 = 2'b0;
+    FRAME_acc_41_itm_1_sg2 = 2'b0;
+    FRAME_acc_41_itm_2 = 6'b0;
+    FRAME_acc_41_itm_sg1 = 2'b0;
+    FRAME_acc_41_itm_sg2 = 2'b0;
+    FRAME_for_slc_XMATRIX_rom_11_psp_sva_1 = 1'b0;
+    FRAME_for_nor_cse = 1'b0;
+    FRAME_mul_sdt = 10'b0;
+    b_2_sva_2 = 11'b0;
+    g_2_sva_2 = 11'b0;
+    r_2_sva_2 = 11'b0;
+    b_0_sva_2 = 11'b0;
+    g_0_sva_2 = 11'b0;
+    r_0_sva_2 = 11'b0;
+    main_stage_0_2 = 1'b0;
+    exit_FRAME_for_sva_1_st_1 = 1'b0;
+    FRAME_slc_acc_imod_4_itm_1 = 1'b0;
+    FRAME_slc_acc_imod_4_itm = 1'b0;
+    FRAME_acc_37_itm_1 = 5'b0;
+    FRAME_acc_37_itm = 5'b0;
+    red_slc_red_2_sg1_itm_1 = 6'b0;
+    red_slc_red_2_sg1_itm = 6'b0;
+    FRAME_mul_1_itm_1 = 9'b0;
+    FRAME_mul_1_itm = 9'b0;
+    blue_slc_blue_2_sg1_8_itm_1 = 1'b0;
+    blue_slc_blue_2_sg1_8_itm = 1'b0;
+    blue_slc_blue_2_sg1_13_itm_1 = 1'b0;
+    blue_slc_blue_2_sg1_13_itm = 1'b0;
+    blue_slc_blue_2_sg1_12_itm_1 = 1'b0;
+    blue_slc_blue_2_sg1_12_itm = 1'b0;
+    FRAME_slc_acc_imod_4_4_itm_1 = 1'b0;
+    FRAME_slc_acc_imod_4_4_itm = 1'b0;
+    FRAME_acc_30_itm_1 = 5'b0;
+    FRAME_acc_30_itm = 5'b0;
+    blue_slc_blue_2_sg1_itm_1 = 6'b0;
+    blue_slc_blue_2_sg1_itm = 6'b0;
+    FRAME_mul_5_itm_1 = 9'b0;
+    FRAME_mul_5_itm = 9'b0;
+    FRAME_mul_4_itm_1 = 11'b0;
+    FRAME_mul_4_itm = 11'b0;
+    green_slc_green_2_sg1_8_itm_1 = 1'b0;
+    green_slc_green_2_sg1_8_itm = 1'b0;
+    green_slc_green_2_sg1_13_itm_1 = 1'b0;
+    green_slc_green_2_sg1_13_itm = 1'b0;
+    green_slc_green_2_sg1_12_itm_1 = 1'b0;
+    green_slc_green_2_sg1_12_itm = 1'b0;
+    FRAME_slc_acc_imod_2_4_itm_1 = 1'b0;
+    FRAME_slc_acc_imod_2_4_itm = 1'b0;
+    FRAME_acc_18_itm_1 = 5'b0;
+    FRAME_acc_18_itm = 5'b0;
+    green_slc_green_2_sg1_itm_1 = 6'b0;
+    green_slc_green_2_sg1_itm = 6'b0;
+    FRAME_mul_3_itm_1 = 9'b0;
+    FRAME_mul_3_itm = 9'b0;
+    FRAME_mul_2_itm_1 = 11'b0;
+    FRAME_mul_2_itm = 11'b0;
+    exit_FRAME_for_lpi_1_dfm_2 = 1'b0;
+    exit_FRAME_lpi_1_dfm_1 = 1'b0;
+    FRAME_p_1_sva_1 = 19'b0;
+    FRAME_acc_4_psp_sva = 12'b0;
+    acc_imod_4_sva = 6'b0;
+    FRAME_acc_3_psp_sva = 12'b0;
+    acc_imod_2_sva = 6'b0;
+    acc_imod_sva = 6'b0;
+    blue_2_sg1_sva = 15'b0;
+    green_2_sg1_sva = 15'b0;
+    red_2_sg1_sva = 15'b0;
+    exit_FRAME_for_sva_1 = 1'b0;
+    i_6_sva_1 = 2'b0;
+    b_2_sva_1 = 16'b0;
+    g_2_sva_1 = 16'b0;
+    r_2_sva_1 = 16'b0;
+    b_0_sva_1 = 16'b0;
+    g_0_sva_1 = 16'b0;
+    r_0_sva_1 = 16'b0;
+    FRAME_for_slc_YMATRIX_rom_11_psp_sva = 1'b0;
+    i_6_lpi_1_dfm = 2'b0;
+    regs_regs_2_lpi_1_dfm = 90'b0;
+    regs_regs_1_sva_dfm = 90'b0;
+    regs_regs_0_sva_dfm = 90'b0;
+    regs_regs_0_sva_1 = 90'b0;
+    exit_FRAME_for_lpi_1_dfm = 1'b0;
+    FRAME_p_1_lpi_1_dfm = 19'b0;
+    exit_FRAME_1_sva = 1'b0;
+    regs_regs_0_sva = 90'b0;
+    regs_regs_1_sva = 90'b0;
+    FRAME_p_1_lpi_1 = 19'b0;
+    vout_rsc_mgc_out_stdreg_d <= 30'b0;
+  end
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_3_1_2;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 2;
+    readslicef_3_1_2 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [14:0] readslicef_16_15_1;
+    input [15:0] vector;
+    reg [15:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_16_15_1 = tmp[14:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_2_1_1;
+    input [1:0] vector;
+    reg [1:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_2_1_1 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_10_15 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_15 = {{5{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_22_11 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_s2u_1_2 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_2 = {vector[0], vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v2/cycle_mgc_ioport.v b/Sobel/sobel.v2/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v2/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v2/cycle_mgc_ioport_v2001.v b/Sobel/sobel.v2/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v2/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v2/cycle_set.tcl b/Sobel/sobel.v2/cycle_set.tcl
new file mode 100644
index 0000000..0f1e219
--- /dev/null
+++ b/Sobel/sobel.v2/cycle_set.tcl
@@ -0,0 +1,113 @@
+
+# Loop constraints
+directive set /sobel/core/core:rlp CSTEPS_FROM {{. == 0}}
+directive set /sobel/core/core:rlp/main CSTEPS_FROM {{. == 3} {.. == 0}}
+
+# IO operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:io_read(vin:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:io_write(vout:rsc.d) CSTEPS_FROM {{.. == 2}}
+
+# Real operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:for:and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#48 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#49 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#50 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#51 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#52 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#5 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#9:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#7 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#10:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#9 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#11:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:or#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#6 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#15:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#8 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#16:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#12 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#10 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#17:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#53 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#54 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#43 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#55 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#56 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#44 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#57 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#58 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#45 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#9 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#11 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#13 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#12 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#15 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#23 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#17 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#18 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#19 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#20 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#21 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#22 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#24 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#27 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#26 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#28 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#35 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#29 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#30 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#31 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#32 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#33 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#34 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#4 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#41 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#42 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#36 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#37 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#38 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#39 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#40 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#2 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#23 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#24 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#19 CSTEPS_FROM {{.. == 1}}
diff --git a/Sobel/sobel.v2/directives.tcl b/Sobel/sobel.v2/directives.tcl
new file mode 100644
index 0000000..504c4bb
--- /dev/null
+++ b/Sobel/sobel.v2/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
+go extract
diff --git a/Sobel/sobel.v2/messages.txt b/Sobel/sobel.v2/messages.txt
new file mode 100644
index 0000000..d812a94
--- /dev/null
+++ b/Sobel/sobel.v2/messages.txt
@@ -0,0 +1,247 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v1': elapsed time 2.98 seconds, memory usage 181920kB, peak memory usage 304392kB (SOL-9)
+$PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.cpp(146): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+
+# Messages from "go compile"
+
+Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'sobel' specified by directive (CIN-52)
+Synthesizing routine 'sobel' (CIN-13)
+Inlining routine 'sobel' (CIN-14)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Optimizing block '/sobel' ... (CIN-4)
+Inout port 'vin' is only used as an input. (OPT-10)
+Inout port 'vout' is only used as an output. (OPT-11)
+Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+Design 'sobel' was read (SOL-1)
+Optimizing partition '/sobel': (Total ops = 504, Real ops = 116, Vars = 110) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 504, Real ops = 116, Vars = 108) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 464, Real ops = 108, Vars = 114) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 464, Real ops = 108, Vars = 116) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 464, Real ops = 108, Vars = 116) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 464, Real ops = 108, Vars = 114) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 400, Real ops = 107, Vars = 97) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 375, Real ops = 107, Vars = 96) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 375, Real ops = 107, Vars = 96) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 375, Real ops = 107, Vars = 98) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 375, Real ops = 107, Vars = 98) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 355, Real ops = 105, Vars = 146) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 31) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 392, Real ops = 104, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 303, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 303, Real ops = 94, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 298, Real ops = 94, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+Completed transformation 'compile' on solution 'sobel.v2': elapsed time 1.90 seconds, memory usage 184324kB, peak memory usage 304392kB (SOL-9)
+Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'sobel.v2' (SOL-8)
+Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+Loop '/sobel/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/sobel/core': (Total ops = 484, Real ops = 157, Vars = 23) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 294, Real ops = 94, Vars = 17) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 291, Real ops = 94, Vars = 16) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 291, Real ops = 94, Vars = 16) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 303, Real ops = 94, Vars = 22) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 94, Vars = 22) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 282, Real ops = 91, Vars = 19) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 282, Real ops = 91, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 22) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 267, Real ops = 91, Vars = 32) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 270, Real ops = 91, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 227, Real ops = 88, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 227, Real ops = 88, Vars = 26) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 227, Real ops = 88, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 227, Real ops = 88, Vars = 26) (SOL-10)
+Design 'sobel' contains '156' real operations. (SOL-11)
+Optimizing partition '/sobel/core': (Total ops = 234, Real ops = 89, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 233, Real ops = 89, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 483, Real ops = 120, Vars = 171) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 277, Real ops = 106, Vars = 50) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 276, Real ops = 106, Vars = 49) (SOL-10)
+Completed transformation 'architect' on solution 'sobel.v2': elapsed time 3.10 seconds, memory usage 184672kB, peak memory usage 304392kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'sobel.v2' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 5175.50, 0.00, 5175.50 (CRAAS-11)
+Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5172.06, 0.00, 5172.06 (CRAAS-10)
+Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5121.26, 0.00, 5121.26 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 5121.26, 0.00, 5121.26 (CRAAS-12)
+Completed transformation 'allocate' on solution 'sobel.v2': elapsed time 0.48 seconds, memory usage 184692kB, peak memory usage 304392kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'sobel.v2' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 441, Real ops = 157, Vars = 120) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 431, Real ops = 156, Vars = 112) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 411, Real ops = 156, Vars = 115) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 373, Real ops = 152, Vars = 85) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 366, Real ops = 151, Vars = 84) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 380, Real ops = 151, Vars = 96) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 371, Real ops = 151, Vars = 89) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 370, Real ops = 151, Vars = 92) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 369, Real ops = 151, Vars = 88) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 383, Real ops = 151, Vars = 100) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 374, Real ops = 151, Vars = 93) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 369, Real ops = 151, Vars = 88) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 383, Real ops = 151, Vars = 100) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 374, Real ops = 151, Vars = 93) (SOL-10)
+Completed transformation 'schedule' on solution 'sobel.v2': elapsed time 1.78 seconds, memory usage 195488kB, peak memory usage 304392kB (SOL-9)
+Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'sobel.v2' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 645, Real ops = 191, Vars = 448) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 636, Real ops = 191, Vars = 441) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 567, Real ops = 190, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 558, Real ops = 190, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+Completed transformation 'dpfsm' on solution 'sobel.v2': elapsed time 0.40 seconds, memory usage 195488kB, peak memory usage 304392kB (SOL-9)
+
+# Messages from "go extract"
+
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'sobel.v2' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 457, Real ops = 215, Vars = 454) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 448, Real ops = 215, Vars = 447) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 78) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 71) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 415, Real ops = 196, Vars = 412) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 406, Real ops = 196, Vars = 405) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 415, Real ops = 196, Vars = 412) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 406, Real ops = 196, Vars = 405) (SOL-10)
+Reassigned operation ACC1:acc#61:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+Reassigned operation ACC1:acc#69:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+Reassigned operation ACC1:acc#65:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+Reassigned operation ACC1:acc#62:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+Reassigned operation ACC1:acc#70:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+Reassigned operation ACC1:acc#66:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/sobel': (Total ops = 415, Real ops = 196, Vars = 412) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 406, Real ops = 196, Vars = 405) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 322, Real ops = 174, Vars = 78) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 313, Real ops = 174, Vars = 71) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 322, Real ops = 174, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 313, Real ops = 174, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 322, Real ops = 174, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 313, Real ops = 174, Vars = 68) (SOL-10)
+Completed transformation 'extract' on solution 'sobel.v2': elapsed time 5.79 seconds, memory usage 195488kB, peak memory usage 304392kB (SOL-9)
diff --git a/Sobel/sobel.v2/reg_sharing.tcl b/Sobel/sobel.v2/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v2/reg_sharing.tcl
diff --git a/Sobel/sobel.v2/res_sharing.tcl b/Sobel/sobel.v2/res_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v2/res_sharing.tcl
diff --git a/Sobel/sobel.v2/rtl.rpt b/Sobel/sobel.v2/rtl.rpt
new file mode 100644
index 0000000..5c98627
--- /dev/null
+++ b/Sobel/sobel.v2/rtl.rpt
@@ -0,0 +1,843 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 14:10:00 +0000 2016                      
+
+Solution Settings: sobel.v2
+  Current state: extract
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       161  921601     921600            0  1          
+    Design Total:                     161  921601     921600            0  0          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(10,0,10,0,10)                       11.241                       0.000     11.241 1.301          1           1 
+    mgc_add(10,0,9,1,10)                        11.000                       0.000     11.000 1.303          1           0 
+    mgc_add(11,0,10,1,12)                       12.000                       0.000     12.000 1.208          2           2 
+    mgc_add(11,1,11,1,12)                       12.000                       0.000     12.000 1.206          6           9 
+    mgc_add(12,1,12,1,13)                       13.000                       0.000     13.000 1.272          5           2 
+    mgc_add(15,0,11,1,15)                       16.000                       0.000     16.000 1.633          0           3 
+    mgc_add(16,0,12,1,16)                       17.000                       0.000     17.000 1.696          6           6 
+    mgc_add(16,0,16,0,16)                       17.189                       0.000     17.189 1.690          3           3 
+    mgc_add(17,0,13,1,17)                       18.000                       0.000     18.000 1.758          3           0 
+    mgc_add(19,0,2,1,19)                        20.000                       0.000     20.000 1.908          1           1 
+    mgc_add(2,0,1,0,2)                           3.315                       0.000      3.315 0.658          0           1 
+    mgc_add(2,0,1,1,2)                           3.000                       0.000      3.000 0.658          0           4 
+    mgc_add(2,0,2,0,2)                           3.311                       0.000      3.311 0.653          1           1 
+    mgc_add(3,0,3,0,3)                           4.302                       0.000      4.302 0.761          1           0 
+    mgc_add(3,0,3,0,4)                           4.302                       0.000      4.302 0.761         12          12 
+    mgc_add(4,0,4,0,5)                           5.293                       0.000      5.293 0.854          6           6 
+    mgc_add(5,0,4,0,6)                           6.288                       0.000      6.288 0.940          3           3 
+    mgc_add(5,0,5,0,5)                           6.285                       0.000      6.285 0.938          6           6 
+    mgc_add(5,0,5,0,6)                           6.285                       0.000      6.285 0.938          0           1 
+    mgc_add(6,0,5,1,8)                           7.000                       0.000      7.000 0.693          3           3 
+    mgc_add(6,0,6,0,6)                           7.276                       0.000      7.276 1.016          3           3 
+    mgc_add(8,0,7,0,8)                           9.262                       0.000      9.262 1.165          1           1 
+    mgc_add(9,0,8,1,10)                         10.000                       0.000     10.000 1.072          3           3 
+    mgc_and(1,2)                                 0.730                       0.000      0.730 0.263          0           3 
+    mgc_and(19,2)                               13.867                       0.000     13.867 0.263          1           1 
+    mgc_and(2,2)                                 1.460                       0.000      1.460 0.263          2           1 
+    mgc_mul(2,0,9,0,11)                        330.250                       2.000     10.250 3.044          3           3 
+    mgc_mul(2,1,10,1,12)                       330.000                       2.000     10.000 3.087          6           6 
+    mgc_mul(3,0,6,0,9)                         330.250                       2.000     10.250 2.846          3           3 
+    mgc_mux(1,1,2)                               0.919                       0.000      0.919 0.369          2           1 
+    mgc_mux(10,2,4)                             22.259                       0.000     22.259 0.936          6           6 
+    mgc_mux(16,1,2)                             14.711                       0.000     14.711 0.369          6           6 
+    mgc_mux(19,1,2)                             17.469                       0.000     17.469 0.369          1           1 
+    mgc_mux(30,1,2)                             27.583                       0.000     27.583 0.369          0           1 
+    mgc_mux(90,1,2)                             82.748                       0.000     82.748 0.369          3           3 
+    mgc_nand(1,2)                                0.730                       0.000      0.730 0.268          0           3 
+    mgc_nor(1,2)                                 0.730                       0.000      0.730 0.263          0           2 
+    mgc_not(1)                                   0.000                       0.000      0.000 0.000          0          24 
+    mgc_not(10)                                  0.000                       0.000      0.000 0.000          0           9 
+    mgc_not(3)                                   0.000                       0.000      0.000 0.000          0          12 
+    mgc_or(1,2)                                  0.730                       0.000      0.730 0.268          0           2 
+    mgc_or(1,3)                                  1.054                       0.000      1.054 0.425          0           1 
+    mgc_or(10,2)                                 7.298                       0.000      7.298 0.268          1           1 
+    mgc_or(2,2)                                  1.460                       0.000      1.460 0.268          1           0 
+    mgc_or(6,2)                                  4.379                       0.000      4.379 0.268          1           1 
+    mgc_reg_pos(1,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           9 
+    mgc_reg_pos(11,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(16,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           6 
+    mgc_reg_pos(19,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(2,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(30,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(5,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(6,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_reg_pos(9,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(90,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           3 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,90)                            0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(2,30)                         0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):            5150.657                      24.000   1311.000                              
+    
+  Area Scores
+                      Post-Scheduling   Post-DP & FSM Post-Assignment 
+    ----------------- --------------- --------------- ---------------
+    Total Area Score:   5121.3          5409.2          5150.7        
+    Total Reg:             0.0             0.0             0.0        
+                                                                      
+    DataPath:           5121.3 (100%)   5409.2 (100%)   5150.7 (100%) 
+      MUX:               489.4  (10%)    773.6  (14%)    516.0  (10%) 
+      FUNC:             4602.0  (90%)   4600.3  (85%)   4599.3  (89%) 
+      LOGIC:              29.9   (1%)     35.4   (1%)     35.4   (1%) 
+      BUFFER:              0.0             0.0             0.0        
+      MEM:                 0.0             0.0             0.0        
+      ROM:                 0.0             0.0             0.0        
+      REG:                 0.0             0.0             0.0        
+                                                                      
+    
+    FSM:                   0.0             0.0             0.0        
+      FSM-REG:             0.0             0.0             0.0        
+      FSM-COMB:            0.0             0.0             0.0        
+                                                                      
+    
+  Register-to-Variable Mappings
+    Register                        Size(bits) Gated Register CG Opt Done Variables                                             
+    ------------------------------- ---------- -------------- ----------- -----------------------------------------------------
+    regs.regs(0).sva                        90         Y                  regs.regs(0).sva                                      
+    regs.regs(1).sva                        90         Y                  regs.regs(1).sva                                      
+    regs.regs(2).lpi#1.dfm                  90         Y                  regs.regs(2).lpi#1.dfm                                
+    vout:rsc:mgc_out_stdreg.d               30         Y                  vout:rsc:mgc_out_stdreg.d                             
+    FRAME:p#1.lpi#1                         19         Y                  FRAME:p#1.lpi#1                                       
+    b(0).sva#1                              16         Y                  b(0).sva#1                                            
+    b(2).sva#1                              16         Y                  b(2).sva#1                                            
+    g(0).sva#1                              16         Y                  g(0).sva#1                                            
+    g(2).sva#1                              16         Y                  g(2).sva#1                                            
+    r(0).sva#1                              16         Y                  r(0).sva#1                                            
+    r(2).sva#1                              16         Y                  r(2).sva#1                                            
+    FRAME:mul#2.itm#1                       11         Y                  FRAME:mul#2.itm#1                                     
+    FRAME:mul#4.itm#1                       11         Y                  FRAME:mul#4.itm#1                                     
+    FRAME:mul#1.itm#1                        9         Y                  FRAME:mul#1.itm#1                                     
+    FRAME:mul#3.itm#1                        9         Y                  FRAME:mul#3.itm#1                                     
+    FRAME:mul#5.itm#1                        9         Y                  FRAME:mul#5.itm#1                                     
+    FRAME:acc#41.itm#3                       6         Y                  FRAME:acc#41.itm#3                                    
+    blue:slc(blue#2.sg1).itm#1               6         Y                  blue:slc(blue#2.sg1).itm#1                            
+    green:slc(green#2.sg1).itm#1             6         Y                  green:slc(green#2.sg1).itm#1                          
+    red:slc(red#2.sg1).itm#1                 6         Y                  red:slc(red#2.sg1).itm#1                              
+    FRAME:acc#18.itm#1                       5         Y                  FRAME:acc#18.itm#1                                    
+    FRAME:acc#30.itm#1                       5         Y                  FRAME:acc#30.itm#1                                    
+    FRAME:acc#37.itm#1                       5         Y                  FRAME:acc#37.itm#1                                    
+    FRAME:acc#41.itm#1.sg1                   2         Y                  FRAME:acc#41.itm#1.sg1                                
+    FRAME:acc#41.itm#1.sg2                   2         Y                  FRAME:acc#41.itm#1.sg2                                
+    i#6.sva#1                                2         Y                  i#6.sva#1                                             
+    FRAME:slc(acc.imod#2)#4.itm#1            1         Y                  FRAME:slc(acc.imod#2)#4.itm#1                         
+    FRAME:slc(acc.imod#4)#4.itm#1            1         Y                  FRAME:slc(acc.imod#4)#4.itm#1                         
+    FRAME:slc(acc.imod)#4.itm#1              1         Y                  FRAME:slc(acc.imod)#4.itm#1                           
+    blue:slc(blue#2.sg1)#12.itm#1            1         Y                  blue:slc(blue#2.sg1)#12.itm#1                         
+    exit:FRAME#1.sva                         1         Y                  exit:FRAME#1.sva                                      
+    exit:FRAME.lpi#1.dfm#1                   1         Y                  exit:FRAME.lpi#1.dfm#1                                
+    exit:FRAME:for.sva#1.st#1                1         Y                  exit:FRAME:for.sva#1.st#1                             
+    green:slc(green#2.sg1)#12.itm#1          1         Y                  green:slc(green#2.sg1)#12.itm#1                       
+    main.stage_0#2                           1         Y                  main.stage_0#2                                        
+                                                                                                                                
+    Total:                                 518            518           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  15.796510999999999
+      Slack:      4.203489000000001
+      
+      Path                                               Startpoint                                Endpoint                           Delay   Slack   
+      -------------------------------------------------- ----------------------------------------- ---------------------------------- ------- -------
+      1                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)                                                                                                 0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva).itm                                                                                             0.0000  9.6738  
+        sobel:core/FRAME:acc#8                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#8.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1.itm                                                                                            0.0000  13.2445 
+        sobel:core/conc#129                                                                                                           0.0000  13.2445 
+        sobel:core/conc#129.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      2                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#2                                                                                               0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#2.itm                                                                                           0.0000  9.6738  
+        sobel:core/FRAME:not#2                           mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#2.itm                                                                                                    0.0000  9.6738  
+        sobel:core/FRAME:acc#8                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#8.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1.itm                                                                                            0.0000  13.2445 
+        sobel:core/conc#129                                                                                                           0.0000  13.2445 
+        sobel:core/conc#129.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      3                                                  sobel:core/reg(exit:FRAME#1.sva)          sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME#1.sva)                 mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME#1.sva                                                                                                   0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#2                                                                                               0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#2.itm                                                                                           0.0000  9.6738  
+        sobel:core/FRAME:not#2                           mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#2.itm                                                                                                    0.0000  9.6738  
+        sobel:core/FRAME:acc#8                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#8.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1.itm                                                                                            0.0000  13.2445 
+        sobel:core/conc#129                                                                                                           0.0000  13.2445 
+        sobel:core/conc#129.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      4                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#18.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#16:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#16:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#7                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#7.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#12                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/g(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#66                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#66.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#47                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#47.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#44                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#44.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc#1                                                                                                         0.0000  9.6738  
+        sobel:core/green#2.sg1.sva                                                                                                    0.0000  9.6738  
+        sobel:core/slc(green#2.sg1.sva)#1                                                                                             0.0000  9.6738  
+        sobel:core/slc(green#2.sg1.sva)#1.itm                                                                                         0.0000  9.6738  
+        sobel:core/FRAME:acc#13                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#13.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#15                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#15.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#16.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc#2                                 mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod#2.sva                                                                                                     0.0000  13.2445 
+        sobel:core/slc(acc.imod#2.sva)#1                                                                                              0.0000  13.2445 
+        sobel:core/slc(acc.imod#2.sva)#1.itm                                                                                          0.0000  13.2445 
+        sobel:core/conc#133                                                                                                           0.0000  13.2445 
+        sobel:core/conc#133.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#23                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#23.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#5                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#5.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#43                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#43.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#132                                                                                                           0.0000  14.1821 
+        sobel:core/conc#132.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#17                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#17.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#18                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#18.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#18.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      5                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#18.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#2                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(1).sva.dfm:mx0                                                                                           0.0000  0.6315  
+        sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1                                                                                    0.0000  0.6315  
+        sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm                                                                                0.0000  0.6315  
+        sobel:core/regs.operator[]#16:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#16:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#7                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#7.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#12                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/g(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#66                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#66.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#47                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#47.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#44                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#44.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc#1                                                                                                         0.0000  9.6738  
+        sobel:core/green#2.sg1.sva                                                                                                    0.0000  9.6738  
+        sobel:core/slc(green#2.sg1.sva)#1                                                                                             0.0000  9.6738  
+        sobel:core/slc(green#2.sg1.sva)#1.itm                                                                                         0.0000  9.6738  
+        sobel:core/FRAME:acc#13                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#13.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#15                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#15.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#16.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc#2                                 mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod#2.sva                                                                                                     0.0000  13.2445 
+        sobel:core/slc(acc.imod#2.sva)#1                                                                                              0.0000  13.2445 
+        sobel:core/slc(acc.imod#2.sva)#1.itm                                                                                          0.0000  13.2445 
+        sobel:core/conc#133                                                                                                           0.0000  13.2445 
+        sobel:core/conc#133.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#23                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#23.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#5                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#5.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#43                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#43.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#132                                                                                                           0.0000  14.1821 
+        sobel:core/conc#132.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#17                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#17.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#18                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#18.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#18.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      6                                                  sobel:core/reg(exit:FRAME#1.sva)          sobel:core/reg(FRAME:acc#18.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME#1.sva)                 mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME#1.sva                                                                                                   0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#2                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(1).sva.dfm:mx0                                                                                           0.0000  0.6315  
+        sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1                                                                                    0.0000  0.6315  
+        sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm                                                                                0.0000  0.6315  
+        sobel:core/regs.operator[]#16:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#16:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#7                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#7.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#12                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/g(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#66                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#66.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#47                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#47.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#44                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#44.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc#1                                                                                                         0.0000  9.6738  
+        sobel:core/green#2.sg1.sva                                                                                                    0.0000  9.6738  
+        sobel:core/slc(green#2.sg1.sva)#1                                                                                             0.0000  9.6738  
+        sobel:core/slc(green#2.sg1.sva)#1.itm                                                                                         0.0000  9.6738  
+        sobel:core/FRAME:acc#13                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#13.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#15                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#15.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#16.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc#2                                 mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod#2.sva                                                                                                     0.0000  13.2445 
+        sobel:core/slc(acc.imod#2.sva)#1                                                                                              0.0000  13.2445 
+        sobel:core/slc(acc.imod#2.sva)#1.itm                                                                                          0.0000  13.2445 
+        sobel:core/conc#133                                                                                                           0.0000  13.2445 
+        sobel:core/conc#133.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#23                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#23.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#5                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#5.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#43                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#43.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#132                                                                                                           0.0000  14.1821 
+        sobel:core/conc#132.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#17                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#17.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#18                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#18.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#18.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      7                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#3                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(0).sva.dfm:mx0                                                                                           0.0000  0.6315  
+        sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5                                                                                    0.0000  0.6315  
+        sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm                                                                                0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#2                                                                                               0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#2.itm                                                                                           0.0000  9.6738  
+        sobel:core/FRAME:not#2                           mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#2.itm                                                                                                    0.0000  9.6738  
+        sobel:core/FRAME:acc#8                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#8.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1.itm                                                                                            0.0000  13.2445 
+        sobel:core/conc#129                                                                                                           0.0000  13.2445 
+        sobel:core/conc#129.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      8                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#20                                                                                              0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#20.itm                                                                                          0.0000  9.6738  
+        sobel:core/FRAME:not#35                          mgc_not_1                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#35.itm                                                                                                   0.0000  9.6738  
+        sobel:core/conc#140                                                                                                           0.0000  9.6738  
+        sobel:core/conc#140.itm                                                                                                       0.0000  9.6738  
+        sobel:core/FRAME:acc#7                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#7.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1.itm                                                                                            0.0000  13.2445 
+        sobel:core/conc#129                                                                                                           0.0000  13.2445 
+        sobel:core/conc#129.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      9                                                  sobel:core/reg(exit:FRAME#1.sva)          sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME#1.sva)                 mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME#1.sva                                                                                                   0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#20                                                                                              0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#20.itm                                                                                          0.0000  9.6738  
+        sobel:core/FRAME:not#35                          mgc_not_1                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#35.itm                                                                                                   0.0000  9.6738  
+        sobel:core/conc#140                                                                                                           0.0000  9.6738  
+        sobel:core/conc#140.itm                                                                                                       0.0000  9.6738  
+        sobel:core/FRAME:acc#7                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#7.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1.itm                                                                                            0.0000  13.2445 
+        sobel:core/conc#129                                                                                                           0.0000  13.2445 
+        sobel:core/conc#129.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      10                                                 sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)                                                                                                 0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva).itm                                                                                             0.0000  9.6738  
+        sobel:core/FRAME:acc#8                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#8.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#2                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#2.itm                                                                                            0.0000  13.2445 
+        sobel:core/FRAME:not#5                           mgc_not_3                                                                    0.0000  13.2445 
+        sobel:core/FRAME:not#5.itm                                                                                                    0.0000  13.2445 
+        sobel:core/FRAME:conc#33                                                                                                      0.0000  13.2445 
+        sobel:core/FRAME:conc#33.itm                                                                                                  0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                        Port                         Slack (Delay) Messages 
+      ----------------------------------------------- -------------------------- ------- ------- --------
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)       mux.itm                    14.1802  5.8198          
+      sobel:core/reg(FRAME:acc#41.itm#1.sg2)          FRAME:acc#43.itm            6.6243 13.3757          
+      sobel:core/reg(FRAME:acc#41.itm#1.sg1)          slc(FRAME:mul.sdt)#2.itm    7.2821 12.7179          
+      sobel:core/reg(FRAME:acc#41.itm#3)              FRAME:acc#44.itm            6.3445 13.6555          
+      sobel:core/reg(FRAME:mul#1.itm#1)               FRAME:mul#1.itm             7.4801 12.5199          
+      sobel:core/reg(red:slc(red#2.sg1).itm#1)        slc(red#2.sg1.sva)#1.itm   10.3262  9.6738          
+      sobel:core/reg(FRAME:acc#37.itm#1)              FRAME:acc#37.itm            4.2035 15.7965          
+      sobel:core/reg(FRAME:slc(acc.imod)#4.itm#1)     slc(acc.imod.sva).itm       6.7555 13.2445          
+      sobel:core/reg(FRAME:mul#4.itm#1)               FRAME:mul#4.itm             7.2821 12.7179          
+      sobel:core/reg(FRAME:mul#5.itm#1)               FRAME:mul#5.itm             7.4801 12.5199          
+      sobel:core/reg(blue:slc(blue#2.sg1).itm#1)      slc(blue#2.sg1.sva)#2.itm  10.3262  9.6738          
+      sobel:core/reg(FRAME:acc#30.itm#1)              FRAME:acc#30.itm            4.2035 15.7965          
+      sobel:core/reg(FRAME:slc(acc.imod#4)#4.itm#1)   slc(acc.imod#4.sva).itm     6.7555 13.2445          
+      sobel:core/reg(blue:slc(blue#2.sg1)#12.itm#1)   slc(blue#2.sg1.sva).itm    10.3262  9.6738          
+      sobel:core/reg(FRAME:mul#2.itm#1)               FRAME:mul#2.itm             7.2821 12.7179          
+      sobel:core/reg(FRAME:mul#3.itm#1)               FRAME:mul#3.itm             7.4801 12.5199          
+      sobel:core/reg(green:slc(green#2.sg1).itm#1)    slc(green#2.sg1.sva)#2.itm 10.3262  9.6738          
+      sobel:core/reg(FRAME:acc#18.itm#1)              FRAME:acc#18.itm            4.2035 15.7965          
+      sobel:core/reg(FRAME:slc(acc.imod#2)#4.itm#1)   slc(acc.imod#2.sva).itm     6.7555 13.2445          
+      sobel:core/reg(green:slc(green#2.sg1)#12.itm#1) slc(green#2.sg1.sva).itm   10.3262  9.6738          
+      sobel:core/reg(exit:FRAME:for.sva#1.st#1)       FRAME:for:not#7.itm        18.1594  1.8406          
+      sobel:core/reg(i#6.sva#1)                       i#6.sva#2                  17.5279  2.4721          
+      sobel:core/reg(exit:FRAME#1.sva)                FRAME:and.itm              16.0328  3.9672          
+      sobel:core/reg(main.stage_0#2)                  Cn1_1#2                    20.0000  0.0000          
+      sobel:core/reg(regs.regs(2).lpi#1.dfm)          regs.regs(2).lpi#1.dfm:mx0  4.2035 15.7965          
+      sobel:core/reg(regs.regs(1).sva)                regs.regs(1).sva.dfm:mx0    4.2035 15.7965          
+      sobel:core/reg(regs.regs(0).sva)                regs.regs(0).sva.dfm:mx0    4.2035 15.7965          
+      sobel:core/reg(exit:FRAME.lpi#1.dfm#1)          exit:FRAME.lpi#1.dfm#1:mx0 16.0328  3.9672          
+      sobel:core/reg(b(2).sva#1)                      b(2).sva#3                  4.2035 15.7965          
+      sobel:core/reg(b(0).sva#1)                      b(0).sva#3                  5.8368 14.1632          
+      sobel:core/reg(g(2).sva#1)                      g(2).sva#3                  4.2035 15.7965          
+      sobel:core/reg(g(0).sva#1)                      g(0).sva#3                  5.8368 14.1632          
+      sobel:core/reg(r(2).sva#1)                      r(2).sva#3                  4.2035 15.7965          
+      sobel:core/reg(r(0).sva#1)                      r(0).sva#3                  5.8368 14.1632          
+      sobel:core/reg(FRAME:p#1.lpi#1)                 mux#5.itm                  17.4604  2.5396          
+      sobel                                           vout:rsc.z                 20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                   19     1 
+    -                   16     9 
+    -                   15     3 
+    -                   13     2 
+    -                   12    11 
+    -                   10     4 
+    -                    8     4 
+    -                    6     7 
+    -                    5    12 
+    -                    4    12 
+    -                    2     6 
+    and                          
+    -                    2     5 
+    mul                          
+    -                   12     6 
+    -                   11     3 
+    -                    9     3 
+    mux                          
+    -                    2     6 
+    -                    1    12 
+    nand                         
+    -                    2     3 
+    nor                          
+    -                    2     2 
+    not                          
+    -                   10     9 
+    -                    3    12 
+    -                    1    24 
+    or                           
+    -                    3     1 
+    -                    2     4 
+    read_port                    
+    -                   90     1 
+    reg                          
+    -                   90     3 
+    -                   30     1 
+    -                   19     1 
+    -                   16     6 
+    -                   11     2 
+    -                    9     3 
+    -                    6     4 
+    -                    5     3 
+    -                    2     3 
+    -                    1     9 
+    write_port                   
+    -                   30     1 
+    
+  End of Report
diff --git a/Sobel/sobel.v2/rtl.v b/Sobel/sobel.v2/rtl.v
new file mode 100644
index 0000000..12be2eb
--- /dev/null
+++ b/Sobel/sobel.v2/rtl.v
@@ -0,0 +1,845 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:10:01 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  wire and_dcpl;
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [89:0] regs_regs_2_lpi_1_dfm;
+  reg [15:0] r_0_sva_1;
+  reg [15:0] g_0_sva_1;
+  reg [15:0] b_0_sva_1;
+  reg [15:0] r_2_sva_1;
+  reg [15:0] g_2_sva_1;
+  reg [15:0] b_2_sva_1;
+  reg [1:0] i_6_sva_1;
+  reg exit_FRAME_lpi_1_dfm_1;
+  reg [10:0] FRAME_mul_2_itm_1;
+  wire [21:0] nl_FRAME_mul_2_itm_1;
+  reg [8:0] FRAME_mul_3_itm_1;
+  wire [17:0] nl_FRAME_mul_3_itm_1;
+  reg [5:0] green_slc_green_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_18_itm_1;
+  wire [5:0] nl_FRAME_acc_18_itm_1;
+  reg FRAME_slc_acc_imod_2_4_itm_1;
+  reg green_slc_green_2_sg1_12_itm_1;
+  reg [10:0] FRAME_mul_4_itm_1;
+  wire [21:0] nl_FRAME_mul_4_itm_1;
+  reg [8:0] FRAME_mul_5_itm_1;
+  wire [17:0] nl_FRAME_mul_5_itm_1;
+  reg [5:0] blue_slc_blue_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_30_itm_1;
+  wire [5:0] nl_FRAME_acc_30_itm_1;
+  reg FRAME_slc_acc_imod_4_4_itm_1;
+  reg blue_slc_blue_2_sg1_12_itm_1;
+  reg [8:0] FRAME_mul_1_itm_1;
+  wire [17:0] nl_FRAME_mul_1_itm_1;
+  reg [5:0] red_slc_red_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_37_itm_1;
+  wire [5:0] nl_FRAME_acc_37_itm_1;
+  reg FRAME_slc_acc_imod_4_itm_1;
+  reg exit_FRAME_for_sva_1_st_1;
+  reg main_stage_0_2;
+  reg [1:0] FRAME_acc_41_itm_1_sg2;
+  wire [2:0] nl_FRAME_acc_41_itm_1_sg2;
+  reg [1:0] FRAME_acc_41_itm_1_sg1;
+  reg [5:0] FRAME_acc_41_itm_3;
+  wire [6:0] nl_FRAME_acc_41_itm_3;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+  wire [11:0] FRAME_acc_3_psp_sva;
+  wire [13:0] nl_FRAME_acc_3_psp_sva;
+  wire [11:0] FRAME_acc_4_psp_sva;
+  wire [13:0] nl_FRAME_acc_4_psp_sva;
+  wire [1:0] i_6_sva_2;
+  wire [2:0] nl_i_6_sva_2;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire exit_FRAME_for_lpi_1_dfm;
+  wire [89:0] regs_regs_2_lpi_1_dfm_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire exit_FRAME_lpi_1_dfm_1_mx0;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [5:0] acc_imod_sva;
+  wire [7:0] nl_acc_imod_sva;
+  wire [9:0] FRAME_mul_sdt;
+  wire [19:0] nl_FRAME_mul_sdt;
+  wire [5:0] acc_imod_4_sva;
+  wire [7:0] nl_acc_imod_4_sva;
+  wire [5:0] acc_imod_2_sva;
+  wire [7:0] nl_acc_imod_2_sva;
+  wire [15:0] b_2_sva_3;
+  wire [16:0] nl_b_2_sva_3;
+  wire [15:0] b_0_sva_3;
+  wire [16:0] nl_b_0_sva_3;
+  wire [15:0] g_2_sva_3;
+  wire [16:0] nl_g_2_sva_3;
+  wire [15:0] g_0_sva_3;
+  wire [16:0] nl_g_0_sva_3;
+  wire [15:0] r_2_sva_3;
+  wire [16:0] nl_r_2_sva_3;
+  wire [15:0] r_0_sva_3;
+  wire [16:0] nl_r_0_sva_3;
+  wire FRAME_for_nor_cse;
+  wire [15:0] ACC1_acc_43_itm;
+  wire [16:0] nl_ACC1_acc_43_itm;
+  wire [15:0] ACC1_acc_45_itm;
+  wire [16:0] nl_ACC1_acc_45_itm;
+  wire [15:0] ACC1_acc_44_itm;
+  wire [16:0] nl_ACC1_acc_44_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_3_itm;
+
+  wire[15:0] FRAME_for_mux_10_nl;
+  wire[9:0] regs_operator_17_mux_nl;
+  wire[15:0] FRAME_for_mux_9_nl;
+  wire[9:0] regs_operator_11_mux_nl;
+  wire[15:0] FRAME_for_mux_8_nl;
+  wire[9:0] regs_operator_16_mux_nl;
+  wire[15:0] FRAME_for_mux_7_nl;
+  wire[9:0] regs_operator_10_mux_nl;
+  wire[15:0] FRAME_for_mux_6_nl;
+  wire[9:0] regs_operator_15_mux_nl;
+  wire[15:0] FRAME_for_mux_5_nl;
+  wire[9:0] regs_operator_9_mux_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_3_psp_sva = (conv_u2s_11_12(FRAME_mul_2_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_3_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(green_slc_green_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_18_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_2_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({green_slc_green_2_sg1_12_itm_1
+      , 3'b0 , ({{2{green_slc_green_2_sg1_12_itm_1}}, green_slc_green_2_sg1_12_itm_1})
+      , 1'b0 , green_slc_green_2_sg1_12_itm_1}));
+  assign FRAME_acc_3_psp_sva = nl_FRAME_acc_3_psp_sva[11:0];
+  assign nl_FRAME_acc_4_psp_sva = (conv_u2s_11_12(FRAME_mul_4_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_5_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(blue_slc_blue_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_30_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_4_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({blue_slc_blue_2_sg1_12_itm_1
+      , 3'b0 , ({{2{blue_slc_blue_2_sg1_12_itm_1}}, blue_slc_blue_2_sg1_12_itm_1})
+      , 1'b0 , blue_slc_blue_2_sg1_12_itm_1}));
+  assign FRAME_acc_4_psp_sva = nl_FRAME_acc_4_psp_sva[11:0];
+  assign nl_FRAME_for_acc_itm = i_6_sva_2 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  assign nl_i_6_sva_2 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_2 = nl_i_6_sva_2[1:0];
+  assign i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm));
+  assign exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva;
+  assign regs_regs_2_lpi_1_dfm_mx0 = MUX_v_90_2_2({regs_regs_1_sva , regs_regs_2_lpi_1_dfm},
+      and_dcpl);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_dcpl);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_dcpl);
+  assign exit_FRAME_lpi_1_dfm_1_mx0 = MUX_s_1_2_2({(~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+      + 8'b10110101)))) , (exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm))},
+      FRAME_for_acc_itm[1]);
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign nl_acc_imod_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_43_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_43_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_43_itm[15])) , 1'b1 , (~ (ACC1_acc_43_itm[15]))}) + conv_u2u_2_4(ACC1_acc_43_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_43_itm[3:1]) + conv_u2u_3_4(~ (ACC1_acc_43_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_sva = nl_acc_imod_sva[5:0];
+  assign nl_ACC1_acc_43_itm = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[59:50])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[59:50])
+      , 1'b1})))) + (r_2_sva_3[15:1])) , (readslicef_2_1_1((({(r_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + r_0_sva_3;
+  assign ACC1_acc_43_itm = nl_ACC1_acc_43_itm[15:0];
+  assign nl_FRAME_mul_sdt = conv_u2u_2_10(ACC1_acc_43_itm[14:13]) * 10'b111000111;
+  assign FRAME_mul_sdt = nl_FRAME_mul_sdt[9:0];
+  assign nl_ACC1_acc_45_itm = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[39:30])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[39:30])
+      , 1'b1})))) + (b_2_sva_3[15:1])) , (readslicef_2_1_1((({(b_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + b_0_sva_3;
+  assign ACC1_acc_45_itm = nl_ACC1_acc_45_itm[15:0];
+  assign nl_acc_imod_4_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_45_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_45_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_45_itm[15])) , 1'b1 , (~ (ACC1_acc_45_itm[15]))}) + conv_u2u_2_4(ACC1_acc_45_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_45_itm[3:1]) + conv_u2u_3_4(~ (ACC1_acc_45_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_4_sva = nl_acc_imod_4_sva[5:0];
+  assign nl_ACC1_acc_44_itm = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[49:40])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[49:40])
+      , 1'b1})))) + (g_2_sva_3[15:1])) , (readslicef_2_1_1((({(g_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + g_0_sva_3;
+  assign ACC1_acc_44_itm = nl_ACC1_acc_44_itm[15:0];
+  assign nl_acc_imod_2_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_44_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_44_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_44_itm[15])) , 1'b1 , (~ (ACC1_acc_44_itm[15]))}) + conv_u2u_2_4(ACC1_acc_44_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_44_itm[3:1]) + conv_u2u_3_4(~ (ACC1_acc_44_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_2_sva = nl_acc_imod_2_sva[5:0];
+  assign FRAME_for_mux_10_nl = MUX_v_16_2_2({b_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[69:60])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[69:60])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+      , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_mx0[69:60]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_b_2_sva_3 = (FRAME_for_mux_10_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_17_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign b_2_sva_3 = nl_b_2_sva_3[15:0];
+  assign FRAME_for_mux_9_nl = MUX_v_16_2_2({b_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[9:0])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[9:0])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_11_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0]) ,
+      (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_mx0[9:0]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_b_0_sva_3 = (FRAME_for_mux_9_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_11_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign b_0_sva_3 = nl_b_0_sva_3[15:0];
+  assign FRAME_for_mux_8_nl = MUX_v_16_2_2({g_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[79:70])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[79:70])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+      , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_mx0[79:70]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_g_2_sva_3 = (FRAME_for_mux_8_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_16_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign g_2_sva_3 = nl_g_2_sva_3[15:0];
+  assign FRAME_for_mux_7_nl = MUX_v_16_2_2({g_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[19:10])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[19:10])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_10_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+      , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_mx0[19:10]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_g_0_sva_3 = (FRAME_for_mux_7_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_10_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign g_0_sva_3 = nl_g_0_sva_3[15:0];
+  assign FRAME_for_mux_6_nl = MUX_v_16_2_2({r_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[89:80])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[89:80])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+      , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_mx0[89:80]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_r_2_sva_3 = (FRAME_for_mux_6_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_15_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign r_2_sva_3 = nl_r_2_sva_3[15:0];
+  assign FRAME_for_mux_5_nl = MUX_v_16_2_2({r_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[29:20])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[29:20])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_9_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+      , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_mx0[29:20]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_r_0_sva_3 = (FRAME_for_mux_5_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_9_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign r_0_sva_3 = nl_r_0_sva_3[15:0];
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_3_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) |
+      FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+  assign and_dcpl = ~(exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva);
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      FRAME_acc_41_itm_1_sg2 <= 2'b0;
+      FRAME_acc_41_itm_1_sg1 <= 2'b0;
+      FRAME_acc_41_itm_3 <= 6'b0;
+      FRAME_mul_1_itm_1 <= 9'b0;
+      red_slc_red_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_37_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_4_itm_1 <= 1'b0;
+      FRAME_mul_4_itm_1 <= 11'b0;
+      FRAME_mul_5_itm_1 <= 9'b0;
+      blue_slc_blue_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_30_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_4_4_itm_1 <= 1'b0;
+      blue_slc_blue_2_sg1_12_itm_1 <= 1'b0;
+      FRAME_mul_2_itm_1 <= 11'b0;
+      FRAME_mul_3_itm_1 <= 9'b0;
+      green_slc_green_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_18_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_2_4_itm_1 <= 1'b0;
+      green_slc_green_2_sg1_12_itm_1 <= 1'b0;
+      exit_FRAME_for_sva_1_st_1 <= 1'b0;
+      i_6_sva_1 <= 2'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_2_lpi_1_dfm <= 90'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_1 <= 1'b0;
+      b_2_sva_1 <= 16'b0;
+      b_0_sva_1 <= 16'b0;
+      g_2_sva_1 <= 16'b0;
+      g_0_sva_1 <= 16'b0;
+      r_2_sva_1 <= 16'b0;
+      r_0_sva_1 <= 16'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({({((({FRAME_acc_41_itm_1_sg2 ,
+            FRAME_acc_41_itm_1_sg1 , FRAME_acc_41_itm_3}) + (conv_u2s_9_10(FRAME_mul_1_itm_1)
+            + conv_s2s_8_10(conv_u2s_6_8(red_slc_red_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_37_itm_1
+            + ({4'b1001 , FRAME_slc_acc_imod_4_itm_1}))))) | ({8'b0 , (FRAME_acc_3_psp_sva[11:10])}))
+            , (FRAME_acc_3_psp_sva[9:6]) , ((FRAME_acc_3_psp_sva[5:0]) | ({4'b0 ,
+            (FRAME_acc_4_psp_sva[11:10])})) , (FRAME_acc_4_psp_sva[9:0])}) , vout_rsc_mgc_out_stdreg_d},
+            ~(exit_FRAME_for_sva_1_st_1 & main_stage_0_2));
+        FRAME_acc_41_itm_1_sg2 <= nl_FRAME_acc_41_itm_1_sg2[1:0];
+        FRAME_acc_41_itm_1_sg1 <= FRAME_mul_sdt[7:6];
+        FRAME_acc_41_itm_3 <= nl_FRAME_acc_41_itm_3[5:0];
+        FRAME_mul_1_itm_1 <= nl_FRAME_mul_1_itm_1[8:0];
+        red_slc_red_2_sg1_itm_1 <= ACC1_acc_43_itm[9:4];
+        FRAME_acc_37_itm_1 <= nl_FRAME_acc_37_itm_1[4:0];
+        FRAME_slc_acc_imod_4_itm_1 <= acc_imod_sva[5];
+        FRAME_mul_4_itm_1 <= nl_FRAME_mul_4_itm_1[10:0];
+        FRAME_mul_5_itm_1 <= nl_FRAME_mul_5_itm_1[8:0];
+        blue_slc_blue_2_sg1_itm_1 <= ACC1_acc_45_itm[9:4];
+        FRAME_acc_30_itm_1 <= nl_FRAME_acc_30_itm_1[4:0];
+        FRAME_slc_acc_imod_4_4_itm_1 <= acc_imod_4_sva[5];
+        blue_slc_blue_2_sg1_12_itm_1 <= ACC1_acc_45_itm[15];
+        FRAME_mul_2_itm_1 <= nl_FRAME_mul_2_itm_1[10:0];
+        FRAME_mul_3_itm_1 <= nl_FRAME_mul_3_itm_1[8:0];
+        green_slc_green_2_sg1_itm_1 <= ACC1_acc_44_itm[9:4];
+        FRAME_acc_18_itm_1 <= nl_FRAME_acc_18_itm_1[4:0];
+        FRAME_slc_acc_imod_2_4_itm_1 <= acc_imod_2_sva[5];
+        green_slc_green_2_sg1_12_itm_1 <= ACC1_acc_44_itm[15];
+        exit_FRAME_for_sva_1_st_1 <= ~ (FRAME_for_acc_itm[1]);
+        i_6_sva_1 <= i_6_sva_2;
+        exit_FRAME_1_sva <= (~ (FRAME_for_acc_itm[1])) & exit_FRAME_lpi_1_dfm_1_mx0;
+        main_stage_0_2 <= 1'b1;
+        regs_regs_2_lpi_1_dfm <= regs_regs_2_lpi_1_dfm_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_1 <= exit_FRAME_lpi_1_dfm_1_mx0;
+        b_2_sva_1 <= b_2_sva_3;
+        b_0_sva_1 <= b_0_sva_3;
+        g_2_sva_1 <= g_2_sva_3;
+        g_0_sva_1 <= g_0_sva_3;
+        r_2_sva_1 <= r_2_sva_3;
+        r_0_sva_1 <= r_0_sva_3;
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_sva_1 , FRAME_p_1_lpi_1_dfm},
+            FRAME_for_acc_itm[1]);
+      end
+    end
+  end
+  assign nl_FRAME_acc_41_itm_1_sg2  = (FRAME_mul_sdt[9:8]) + conv_s2u_1_2(ACC1_acc_43_itm[15]);
+  assign nl_FRAME_acc_41_itm_3  = conv_u2u_5_6(FRAME_mul_sdt[4:0]) + conv_u2u_5_6(signext_5_3({(ACC1_acc_43_itm[15])
+      , 1'b0 , (ACC1_acc_43_itm[15])}));
+  assign nl_FRAME_mul_1_itm_1  = conv_u2u_3_9(ACC1_acc_43_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_37_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_sva[5:3])) , (~ (acc_imod_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC1_acc_43_itm[9:7]));
+  assign nl_FRAME_mul_4_itm_1  = conv_u2u_2_11(ACC1_acc_45_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_5_itm_1  = conv_u2u_3_9(ACC1_acc_45_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_30_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_4_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_4_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_4_sva[5:3])) , (~ (acc_imod_4_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_4_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC1_acc_45_itm[9:7]));
+  assign nl_FRAME_mul_2_itm_1  = conv_u2u_2_11(ACC1_acc_44_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_3_itm_1  = conv_u2u_3_9(ACC1_acc_44_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_18_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_2_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_2_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_2_sva[5:3])) , (~ (acc_imod_2_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_2_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC1_acc_44_itm[9:7]));
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_2_1_1;
+    input [1:0] vector;
+    reg [1:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_2_1_1 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [15:0] signext_16_11;
+    input [10:0] vector;
+  begin
+    signext_16_11= {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_11_15 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_15 = {{4{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_s2u_1_2 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_2 = {vector[0], vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v2/rtl.v.psr b/Sobel/sobel.v2/rtl.v.psr
new file mode 100644
index 0000000..bdf9240
--- /dev/null
+++ b/Sobel/sobel.v2/rtl.v.psr
@@ -0,0 +1,289 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v2/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v2/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v2/rtl.v}} -format verilog
+   setup_design -design=sobel
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'sobel': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'sobel': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'sobel'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'sobel'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to vout_rsc_z(29:0)
+   report_timing -from en -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from vin_rsc_z(89:0) -to vout_rsc_z(29:0)
+   report_timing -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock clk] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock en] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'sobel'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'sobel'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v2 mapped.v]
+          puts "-- Writing mapped netlist for 'sobel' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v2 gate.v]
+          set gate_sdf [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v2 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/Sobel/sobel.v2/rtl.v.psr_timing b/Sobel/sobel.v2/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/Sobel/sobel.v2/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/Sobel/sobel.v2/rtl.v_order.txt b/Sobel/sobel.v2/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/Sobel/sobel.v2/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/Sobel/sobel.v2/rtl_mgc_ioport.v b/Sobel/sobel.v2/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v2/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v2/rtl_mgc_ioport_v2001.v b/Sobel/sobel.v2/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v2/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v2/schedule.gnt b/Sobel/sobel.v2/schedule.gnt
new file mode 100644
index 0000000..b9f1601
--- /dev/null
+++ b/Sobel/sobel.v2/schedule.gnt
@@ -0,0 +1,445 @@
+set a(0-349) {NAME i:asn(i#6.lpi#1) TYPE ASSIGN PAR 0-348 XREFS 3451 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{258 0 0-363 {}}} CYCLES {}}
+set a(0-350) {NAME b:asn(b(2).lpi#1) TYPE ASSIGN PAR 0-348 XREFS 3452 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{258 0 0-363 {}}} CYCLES {}}
+set a(0-351) {NAME g:asn(g(2).lpi#1) TYPE ASSIGN PAR 0-348 XREFS 3453 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{258 0 0-363 {}}} CYCLES {}}
+set a(0-352) {NAME r:asn(r(2).lpi#1) TYPE ASSIGN PAR 0-348 XREFS 3454 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{258 0 0-363 {}}} CYCLES {}}
+set a(0-353) {NAME b:asn(b(0).lpi#1) TYPE ASSIGN PAR 0-348 XREFS 3455 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{258 0 0-363 {}}} CYCLES {}}
+set a(0-354) {NAME g:asn(g(0).lpi#1) TYPE ASSIGN PAR 0-348 XREFS 3456 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{258 0 0-363 {}}} CYCLES {}}
+set a(0-355) {NAME r:asn(r(0).lpi#1) TYPE ASSIGN PAR 0-348 XREFS 3457 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{258 0 0-363 {}}} CYCLES {}}
+set a(0-356) {NAME regs.regs:asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-348 XREFS 3458 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{258 0 0-363 {}}} CYCLES {}}
+set a(0-357) {NAME FRAME:asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-348 XREFS 3459 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{258 0 0-363 {}}} CYCLES {}}
+set a(0-358) {NAME FRAME:for:asn(exit:FRAME:for.lpi#1)#1 TYPE ASSIGN PAR 0-348 XREFS 3460 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{258 0 0-363 {}}} CYCLES {}}
+set a(0-359) {NAME FRAME:p:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-348 XREFS 3461 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{258 0 0-363 {}}} CYCLES {}}
+set a(0-360) {NAME asn(regs.regs(1))#1 TYPE ASSIGN PAR 0-348 XREFS 3462 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{258 0 0-363 {}}} CYCLES {}}
+set a(0-361) {NAME asn(regs.regs(0))#1 TYPE ASSIGN PAR 0-348 XREFS 3463 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{258 0 0-363 {}}} CYCLES {}}
+set a(0-362) {NAME FRAME:for:asn(exit:FRAME#1) TYPE ASSIGN PAR 0-348 XREFS 3464 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-363 {}}} SUCCS {{259 0 0-363 {}}} CYCLES {}}
+set a(0-364) {NAME FRAME:asn(exit:FRAME.sva#1) TYPE ASSIGN PAR 0-363 XREFS 3465 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {} SUCCS {{258 0 0-768 {}} {258 0 0-769 {}}} CYCLES {}}
+set a(0-365) {NAME FRAME:p:asn(FRAME:p#1.sva#1) TYPE ASSIGN PAR 0-363 XREFS 3466 LOC {0 1.0 1 0.9041241999999999 1 0.9041241999999999 3 0.364883325} PREDS {} SUCCS {{258 0 0-781 {}}} CYCLES {}}
+set a(0-366) {NAME b:asn(b(2).sva) TYPE ASSIGN PAR 0-363 XREFS 3467 LOC {0 1.0 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {} SUCCS {{258 0 0-525 {}}} CYCLES {}}
+set a(0-367) {NAME g:asn(g(2).sva) TYPE ASSIGN PAR 0-363 XREFS 3468 LOC {0 1.0 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {} SUCCS {{258 0 0-516 {}}} CYCLES {}}
+set a(0-368) {NAME r:asn(r(2).sva) TYPE ASSIGN PAR 0-363 XREFS 3469 LOC {0 1.0 1 0.27276455 1 0.27276455 2 0.005714625} PREDS {} SUCCS {{258 0 0-507 {}}} CYCLES {}}
+set a(0-369) {NAME b:asn(b(0).sva) TYPE ASSIGN PAR 0-363 XREFS 3470 LOC {0 1.0 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {} SUCCS {{258 0 0-480 {}}} CYCLES {}}
+set a(0-370) {NAME g:asn(g(0).sva) TYPE ASSIGN PAR 0-363 XREFS 3471 LOC {0 1.0 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {} SUCCS {{258 0 0-470 {}}} CYCLES {}}
+set a(0-371) {NAME r:asn(r(0).sva) TYPE ASSIGN PAR 0-363 XREFS 3472 LOC {0 1.0 1 0.382656675 1 0.382656675 2 0.11560675} PREDS {} SUCCS {{258 0 0-460 {}}} CYCLES {}}
+set a(0-372) {NAME regs.regs:asn(regs.regs(0).sva#1) TYPE ASSIGN PAR 0-363 XREFS 3473 LOC {0 1.0 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {} SUCCS {{258 0 0-438 {}}} CYCLES {}}
+set a(0-373) {NAME FRAME:for:asn TYPE ASSIGN PAR 0-363 XREFS 3474 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-786 {}}} SUCCS {{259 0 0-374 {}} {256 0 0-786 {}}} CYCLES {}}
+set a(0-374) {NAME FRAME:for:select TYPE SELECT PAR 0-363 XREFS 3475 LOC {0 1.0 0 1.0 0 1.0 3 1.0} PREDS {{259 0 0-373 {}}} SUCCS {} CYCLES {}}
+set a(0-375) {NAME FRAME:asn TYPE ASSIGN PAR 0-363 XREFS 3476 LOC {0 1.0 1 0.76845805 1 0.76845805 2 0.38794392499999997} PREDS {{262 0 0-786 {}}} SUCCS {{259 0 0-376 {}} {256 0 0-786 {}}} CYCLES {}}
+set a(0-376) {NAME FRAME:not#28 TYPE NOT PAR 0-363 XREFS 3477 LOC {1 0.0 1 0.76845805 1 0.76845805 2 0.38794392499999997} PREDS {{259 0 0-375 {}}} SUCCS {{259 0 0-377 {}}} CYCLES {}}
+set a(0-377) {NAME FRAME:for:exs TYPE SIGNEXTEND PAR 0-363 XREFS 3478 LOC {1 0.0 1 0.76845805 1 0.76845805 2 0.38794392499999997} PREDS {{259 0 0-376 {}}} SUCCS {{259 0 0-378 {}}} CYCLES {}}
+set a(0-378) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(19,2) AREA_SCORE 13.87 QUANTITY 1 NAME FRAME:for:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-363 XREFS 3479 LOC {1 0.0 1 0.76845805 1 0.76845805 1 0.784864781263854 2 0.40435065626385386} PREDS {{262 0 0-781 {}} {259 0 0-377 {}}} SUCCS {{258 0 0-761 {}} {258 0 0-781 {}}} CYCLES {}}
+set a(0-379) {NAME FRAME:for:asn#9 TYPE ASSIGN PAR 0-363 XREFS 3480 LOC {0 1.0 1 0.0 1 0.0 1 0.619485875} PREDS {{262 0 0-786 {}}} SUCCS {{259 0 0-380 {}} {256 0 0-786 {}}} CYCLES {}}
+set a(0-380) {NAME FRAME:for:or TYPE OR PAR 0-363 XREFS 3481 LOC {1 0.0 1 0.0 1 0.0 1 0.619485875} PREDS {{262 0 0-784 {}} {259 0 0-379 {}}} SUCCS {{259 0 0-381 {}} {258 0 0-438 {}} {258 0 0-441 {}} {258 0 0-443 {}} {258 0 0-444 {}} {258 0 0-462 {}} {258 0 0-472 {}} {258 0 0-482 {}} {258 0 0-509 {}} {258 0 0-518 {}} {258 0 0-527 {}} {258 0 0-766 {}} {256 0 0-784 {}}} CYCLES {}}
+set a(0-381) {NAME FRAME:for:select#1 TYPE SELECT PAR 0-363 XREFS 3482 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {{259 0 0-380 {}}} SUCCS {{146 0 0-382 {}} {146 0 0-383 {}} {146 0 0-384 {}} {146 0 0-385 {}} {146 0 0-386 {}} {146 0 0-387 {}} {146 0 0-388 {}} {146 0 0-389 {}} {146 0 0-390 {}} {146 0 0-391 {}} {146 0 0-392 {}} {146 0 0-393 {}} {146 0 0-394 {}} {146 0 0-395 {}} {146 0 0-396 {}} {146 0 0-397 {}} {146 0 0-398 {}} {146 0 0-399 {}} {146 0 0-400 {}} {146 0 0-401 {}} {146 0 0-402 {}} {146 0 0-403 {}} {146 0 0-404 {}} {146 0 0-405 {}} {146 0 0-406 {}} {146 0 0-407 {}} {146 0 0-408 {}} {146 0 0-409 {}} {146 0 0-410 {}} {146 0 0-411 {}} {146 0 0-412 {}} {146 0 0-413 {}} {146 0 0-414 {}} {146 0 0-415 {}} {146 0 0-416 {}} {146 0 0-417 {}} {146 0 0-418 {}} {146 0 0-419 {}} {146 0 0-420 {}} {146 0 0-421 {}} {146 0 0-422 {}} {146 0 0-423 {}} {146 0 0-424 {}} {146 0 0-425 {}} {146 0 0-426 {}} {146 0 0-427 {}} {146 0 0-428 {}} {146 0 0-429 {}} {146 0 0-430 {}} {146 0 0-431 {}} {146 0 0-432 {}} {146 0 0-433 {}} {146 0 0-434 {}} {146 0 0-435 {}} {146 0 0-436 {}}} CYCLES {}}
+set a(0-382) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,90) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_read(vin:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-363 XREFS 3483 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {{146 0 0-381 {}}} SUCCS {{259 0 0-383 {}} {258 0 0-392 {}} {258 0 0-401 {}} {258 0 0-410 {}} {258 0 0-419 {}} {258 0 0-428 {}} {258 0 0-438 {}}} CYCLES {}}
+set a(0-383) {NAME ACC1:slc(regs.regs(0))#3 TYPE READSLICE PAR 0-363 XREFS 3484 LOC {1 0.0 1 0.021312825 1 0.021312825 2 0.04023595} PREDS {{146 0 0-381 {}} {259 0 0-382 {}}} SUCCS {{259 0 0-384 {}}} CYCLES {}}
+set a(0-384) {NAME ACC1:not TYPE NOT PAR 0-363 XREFS 3485 LOC {1 0.0 1 0.307285875 1 0.307285875 2 0.04023595} PREDS {{146 0 0-381 {}} {259 0 0-383 {}}} SUCCS {{259 0 0-385 {}}} CYCLES {}}
+set a(0-385) {NAME ACC1:conc TYPE CONCATENATE PAR 0-363 XREFS 3486 LOC {1 0.0 1 0.307285875 1 0.307285875 2 0.04023595} PREDS {{146 0 0-381 {}} {259 0 0-384 {}}} SUCCS {{258 0 0-389 {}}} CYCLES {}}
+set a(0-386) {NAME ACC1:asn TYPE ASSIGN PAR 0-363 XREFS 3487 LOC {1 0.0 1 0.021312825 1 0.021312825 2 0.04023595} PREDS {{146 0 0-381 {}} {262 0 0-773 {}}} SUCCS {{259 0 0-387 {}} {256 0 0-773 {}}} CYCLES {}}
+set a(0-387) {NAME ACC1:slc(regs.regs(2))#3 TYPE READSLICE PAR 0-363 XREFS 3488 LOC {1 0.0 1 0.021312825 1 0.021312825 2 0.04023595} PREDS {{146 0 0-381 {}} {259 0 0-386 {}}} SUCCS {{259 0 0-388 {}}} CYCLES {}}
+set a(0-388) {NAME ACC1:conc#21 TYPE CONCATENATE PAR 0-363 XREFS 3489 LOC {1 0.0 1 0.307285875 1 0.307285875 2 0.04023595} PREDS {{146 0 0-381 {}} {259 0 0-387 {}}} SUCCS {{259 0 0-389 {}}} CYCLES {}}
+set a(0-389) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#48 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-363 XREFS 3490 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.38265663137342837 2 0.11560670637342838} PREDS {{146 0 0-381 {}} {258 0 0-385 {}} {259 0 0-388 {}}} SUCCS {{259 0 0-390 {}}} CYCLES {}}
+set a(0-390) {NAME ACC1:slc TYPE READSLICE PAR 0-363 XREFS 3491 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.11560675} PREDS {{146 0 0-381 {}} {259 0 0-389 {}}} SUCCS {{259 0 0-391 {}}} CYCLES {}}
+set a(0-391) {NAME ACC1:exs#47 TYPE SIGNEXTEND PAR 0-363 XREFS 3492 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.11560675} PREDS {{146 0 0-381 {}} {259 0 0-390 {}}} SUCCS {{258 0 0-460 {}}} CYCLES {}}
+set a(0-392) {NAME ACC1:slc(regs.regs(0))#4 TYPE READSLICE PAR 0-363 XREFS 3493 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {258 0 0-382 {}}} SUCCS {{259 0 0-393 {}}} CYCLES {}}
+set a(0-393) {NAME ACC1:not#15 TYPE NOT PAR 0-363 XREFS 3494 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {259 0 0-392 {}}} SUCCS {{259 0 0-394 {}}} CYCLES {}}
+set a(0-394) {NAME ACC1:conc#22 TYPE CONCATENATE PAR 0-363 XREFS 3495 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {259 0 0-393 {}}} SUCCS {{258 0 0-398 {}}} CYCLES {}}
+set a(0-395) {NAME ACC1:asn#11 TYPE ASSIGN PAR 0-363 XREFS 3496 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {262 0 0-773 {}}} SUCCS {{259 0 0-396 {}} {256 0 0-773 {}}} CYCLES {}}
+set a(0-396) {NAME ACC1:slc(regs.regs(2))#4 TYPE READSLICE PAR 0-363 XREFS 3497 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {259 0 0-395 {}}} SUCCS {{259 0 0-397 {}}} CYCLES {}}
+set a(0-397) {NAME ACC1:conc#23 TYPE CONCATENATE PAR 0-363 XREFS 3498 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {259 0 0-396 {}}} SUCCS {{259 0 0-398 {}}} CYCLES {}}
+set a(0-398) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-363 XREFS 3499 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.38265663137342837 1 0.9999999563734283} PREDS {{146 0 0-381 {}} {258 0 0-394 {}} {259 0 0-397 {}}} SUCCS {{259 0 0-399 {}}} CYCLES {}}
+set a(0-399) {NAME ACC1:slc#1 TYPE READSLICE PAR 0-363 XREFS 3500 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{146 0 0-381 {}} {259 0 0-398 {}}} SUCCS {{259 0 0-400 {}}} CYCLES {}}
+set a(0-400) {NAME ACC1:exs#48 TYPE SIGNEXTEND PAR 0-363 XREFS 3501 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{146 0 0-381 {}} {259 0 0-399 {}}} SUCCS {{258 0 0-470 {}}} CYCLES {}}
+set a(0-401) {NAME ACC1:slc(regs.regs(0))#5 TYPE READSLICE PAR 0-363 XREFS 3502 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {258 0 0-382 {}}} SUCCS {{259 0 0-402 {}}} CYCLES {}}
+set a(0-402) {NAME ACC1:not#16 TYPE NOT PAR 0-363 XREFS 3503 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {259 0 0-401 {}}} SUCCS {{259 0 0-403 {}}} CYCLES {}}
+set a(0-403) {NAME ACC1:conc#24 TYPE CONCATENATE PAR 0-363 XREFS 3504 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {259 0 0-402 {}}} SUCCS {{258 0 0-407 {}}} CYCLES {}}
+set a(0-404) {NAME ACC1:asn#12 TYPE ASSIGN PAR 0-363 XREFS 3505 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {262 0 0-773 {}}} SUCCS {{259 0 0-405 {}} {256 0 0-773 {}}} CYCLES {}}
+set a(0-405) {NAME ACC1:slc(regs.regs(2))#5 TYPE READSLICE PAR 0-363 XREFS 3506 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {259 0 0-404 {}}} SUCCS {{259 0 0-406 {}}} CYCLES {}}
+set a(0-406) {NAME ACC1:conc#25 TYPE CONCATENATE PAR 0-363 XREFS 3507 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {259 0 0-405 {}}} SUCCS {{259 0 0-407 {}}} CYCLES {}}
+set a(0-407) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#49 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-363 XREFS 3508 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.38265663137342837 1 0.9999999563734283} PREDS {{146 0 0-381 {}} {258 0 0-403 {}} {259 0 0-406 {}}} SUCCS {{259 0 0-408 {}}} CYCLES {}}
+set a(0-408) {NAME ACC1:slc#2 TYPE READSLICE PAR 0-363 XREFS 3509 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{146 0 0-381 {}} {259 0 0-407 {}}} SUCCS {{259 0 0-409 {}}} CYCLES {}}
+set a(0-409) {NAME ACC1:exs#49 TYPE SIGNEXTEND PAR 0-363 XREFS 3510 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{146 0 0-381 {}} {259 0 0-408 {}}} SUCCS {{258 0 0-480 {}}} CYCLES {}}
+set a(0-410) {NAME ACC1:slc(regs.regs(0)) TYPE READSLICE PAR 0-363 XREFS 3511 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {258 0 0-382 {}}} SUCCS {{259 0 0-411 {}}} CYCLES {}}
+set a(0-411) {NAME ACC1:not#12 TYPE NOT PAR 0-363 XREFS 3512 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {259 0 0-410 {}}} SUCCS {{259 0 0-412 {}}} CYCLES {}}
+set a(0-412) {NAME ACC1:conc#26 TYPE CONCATENATE PAR 0-363 XREFS 3513 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {259 0 0-411 {}}} SUCCS {{258 0 0-416 {}}} CYCLES {}}
+set a(0-413) {NAME ACC1:asn#13 TYPE ASSIGN PAR 0-363 XREFS 3514 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {262 0 0-773 {}}} SUCCS {{259 0 0-414 {}} {256 0 0-773 {}}} CYCLES {}}
+set a(0-414) {NAME ACC1:slc(regs.regs(2)) TYPE READSLICE PAR 0-363 XREFS 3515 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {259 0 0-413 {}}} SUCCS {{259 0 0-415 {}}} CYCLES {}}
+set a(0-415) {NAME ACC1:conc#27 TYPE CONCATENATE PAR 0-363 XREFS 3516 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.9246291999999999} PREDS {{146 0 0-381 {}} {259 0 0-414 {}}} SUCCS {{259 0 0-416 {}}} CYCLES {}}
+set a(0-416) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#50 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-363 XREFS 3517 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.27276450637342836 1 0.9999999563734283} PREDS {{146 0 0-381 {}} {258 0 0-412 {}} {259 0 0-415 {}}} SUCCS {{259 0 0-417 {}}} CYCLES {}}
+set a(0-417) {NAME ACC1:slc#3 TYPE READSLICE PAR 0-363 XREFS 3518 LOC {1 0.0753708 1 0.27276455 1 0.27276455 2 0.005714625} PREDS {{146 0 0-381 {}} {259 0 0-416 {}}} SUCCS {{259 0 0-418 {}}} CYCLES {}}
+set a(0-418) {NAME ACC1-3:exs TYPE SIGNEXTEND PAR 0-363 XREFS 3519 LOC {1 0.0753708 1 0.27276455 1 0.27276455 2 0.005714625} PREDS {{146 0 0-381 {}} {259 0 0-417 {}}} SUCCS {{258 0 0-507 {}}} CYCLES {}}
+set a(0-419) {NAME ACC1:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-363 XREFS 3520 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.7955668} PREDS {{146 0 0-381 {}} {258 0 0-382 {}}} SUCCS {{259 0 0-420 {}}} CYCLES {}}
+set a(0-420) {NAME ACC1:not#13 TYPE NOT PAR 0-363 XREFS 3521 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.7955668} PREDS {{146 0 0-381 {}} {259 0 0-419 {}}} SUCCS {{259 0 0-421 {}}} CYCLES {}}
+set a(0-421) {NAME ACC1:conc#28 TYPE CONCATENATE PAR 0-363 XREFS 3522 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.7955668} PREDS {{146 0 0-381 {}} {259 0 0-420 {}}} SUCCS {{258 0 0-425 {}}} CYCLES {}}
+set a(0-422) {NAME ACC1:asn#14 TYPE ASSIGN PAR 0-363 XREFS 3523 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.7955668} PREDS {{146 0 0-381 {}} {262 0 0-773 {}}} SUCCS {{259 0 0-423 {}} {256 0 0-773 {}}} CYCLES {}}
+set a(0-423) {NAME ACC1:slc(regs.regs(2))#1 TYPE READSLICE PAR 0-363 XREFS 3524 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.7955668} PREDS {{146 0 0-381 {}} {259 0 0-422 {}}} SUCCS {{259 0 0-424 {}}} CYCLES {}}
+set a(0-424) {NAME ACC1:conc#29 TYPE CONCATENATE PAR 0-363 XREFS 3525 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.7955668} PREDS {{146 0 0-381 {}} {259 0 0-423 {}}} SUCCS {{259 0 0-425 {}}} CYCLES {}}
+set a(0-425) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#51 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-363 XREFS 3526 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.27276450637342836 1 0.8709375563734284} PREDS {{146 0 0-381 {}} {258 0 0-421 {}} {259 0 0-424 {}}} SUCCS {{259 0 0-426 {}}} CYCLES {}}
+set a(0-426) {NAME ACC1:slc#4 TYPE READSLICE PAR 0-363 XREFS 3527 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{146 0 0-381 {}} {259 0 0-425 {}}} SUCCS {{259 0 0-427 {}}} CYCLES {}}
+set a(0-427) {NAME ACC1-3:exs#1 TYPE SIGNEXTEND PAR 0-363 XREFS 3528 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{146 0 0-381 {}} {259 0 0-426 {}}} SUCCS {{258 0 0-516 {}}} CYCLES {}}
+set a(0-428) {NAME ACC1:slc(regs.regs(0))#2 TYPE READSLICE PAR 0-363 XREFS 3529 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.7955668} PREDS {{146 0 0-381 {}} {258 0 0-382 {}}} SUCCS {{259 0 0-429 {}}} CYCLES {}}
+set a(0-429) {NAME ACC1:not#14 TYPE NOT PAR 0-363 XREFS 3530 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.7955668} PREDS {{146 0 0-381 {}} {259 0 0-428 {}}} SUCCS {{259 0 0-430 {}}} CYCLES {}}
+set a(0-430) {NAME ACC1:conc#30 TYPE CONCATENATE PAR 0-363 XREFS 3531 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.7955668} PREDS {{146 0 0-381 {}} {259 0 0-429 {}}} SUCCS {{258 0 0-434 {}}} CYCLES {}}
+set a(0-431) {NAME ACC1:asn#15 TYPE ASSIGN PAR 0-363 XREFS 3532 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.7955668} PREDS {{146 0 0-381 {}} {262 0 0-773 {}}} SUCCS {{259 0 0-432 {}} {256 0 0-773 {}}} CYCLES {}}
+set a(0-432) {NAME ACC1:slc(regs.regs(2))#2 TYPE READSLICE PAR 0-363 XREFS 3533 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.7955668} PREDS {{146 0 0-381 {}} {259 0 0-431 {}}} SUCCS {{259 0 0-433 {}}} CYCLES {}}
+set a(0-433) {NAME ACC1:conc#31 TYPE CONCATENATE PAR 0-363 XREFS 3534 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.7955668} PREDS {{146 0 0-381 {}} {259 0 0-432 {}}} SUCCS {{259 0 0-434 {}}} CYCLES {}}
+set a(0-434) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#52 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-363 XREFS 3535 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.27276450637342836 1 0.8709375563734284} PREDS {{146 0 0-381 {}} {258 0 0-430 {}} {259 0 0-433 {}}} SUCCS {{259 0 0-435 {}}} CYCLES {}}
+set a(0-435) {NAME ACC1:slc#5 TYPE READSLICE PAR 0-363 XREFS 3536 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{146 0 0-381 {}} {259 0 0-434 {}}} SUCCS {{259 0 0-436 {}}} CYCLES {}}
+set a(0-436) {NAME ACC1-3:exs#2 TYPE SIGNEXTEND PAR 0-363 XREFS 3537 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{146 0 0-381 {}} {259 0 0-435 {}}} SUCCS {{258 0 0-525 {}}} CYCLES {}}
+set a(0-437) {NAME FRAME:for:asn#10 TYPE ASSIGN PAR 0-363 XREFS 3538 LOC {0 1.0 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {{262 0 0-772 {}}} SUCCS {{259 0 0-438 {}} {256 0 0-772 {}}} CYCLES {}}
+set a(0-438) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#2 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-363 XREFS 3539 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.0443733875 1 0.6425464375} PREDS {{258 0 0-380 {}} {258 0 0-382 {}} {258 0 0-372 {}} {259 0 0-437 {}}} SUCCS {{258 0 0-465 {}} {258 0 0-475 {}} {258 0 0-485 {}} {258 0 0-512 {}} {258 0 0-521 {}} {258 0 0-530 {}} {258 0 0-542 {}} {258 0 0-557 {}} {258 0 0-572 {}} {258 0 0-772 {}}} CYCLES {}}
+set a(0-439) {NAME FRAME:for:asn#11 TYPE ASSIGN PAR 0-363 XREFS 3540 LOC {0 1.0 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {{262 0 0-772 {}}} SUCCS {{258 0 0-441 {}} {256 0 0-772 {}}} CYCLES {}}
+set a(0-440) {NAME FRAME:for:asn#12 TYPE ASSIGN PAR 0-363 XREFS 3541 LOC {0 1.0 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {{262 0 0-773 {}}} SUCCS {{259 0 0-441 {}} {256 0 0-773 {}}} CYCLES {}}
+set a(0-441) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#3 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-363 XREFS 3542 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.0443733875 1 0.6425464375} PREDS {{258 0 0-380 {}} {258 0 0-439 {}} {259 0 0-440 {}}} SUCCS {{258 0 0-464 {}} {258 0 0-474 {}} {258 0 0-484 {}} {258 0 0-511 {}} {258 0 0-520 {}} {258 0 0-529 {}} {258 0 0-773 {}}} CYCLES {}}
+set a(0-442) {NAME FRAME:for:asn#13 TYPE ASSIGN PAR 0-363 XREFS 3543 LOC {0 1.0 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {{262 0 0-773 {}}} SUCCS {{259 0 0-443 {}} {256 0 0-773 {}}} CYCLES {}}
+set a(0-443) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#4 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-363 XREFS 3544 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.0443733875 1 0.6425464375} PREDS {{258 0 0-380 {}} {262 0 0-774 {}} {259 0 0-442 {}}} SUCCS {{258 0 0-463 {}} {258 0 0-473 {}} {258 0 0-483 {}} {258 0 0-510 {}} {258 0 0-519 {}} {258 0 0-528 {}} {258 0 0-546 {}} {258 0 0-561 {}} {258 0 0-576 {}} {258 0 0-774 {}}} CYCLES {}}
+set a(0-444) {NAME not#15 TYPE NOT PAR 0-363 XREFS 3545 LOC {1 0.0 1 0.02796665 1 0.02796665 1 0.6261397} PREDS {{258 0 0-380 {}}} SUCCS {{259 0 0-445 {}}} CYCLES {}}
+set a(0-445) {NAME FRAME:for:exs#19 TYPE SIGNEXTEND PAR 0-363 XREFS 3546 LOC {1 0.0 1 0.02796665 1 0.02796665 1 0.6261397} PREDS {{259 0 0-444 {}}} SUCCS {{259 0 0-446 {}}} CYCLES {}}
+set a(0-446) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 2 NAME FRAME:for:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-363 XREFS 3547 LOC {1 0.0 1 0.02796665 1 0.02796665 1 0.04437338126385391 1 0.6425464312638539} PREDS {{262 0 0-782 {}} {259 0 0-445 {}}} SUCCS {{259 0 0-447 {}} {258 0 0-448 {}} {258 0 0-449 {}} {258 0 0-450 {}} {258 0 0-451 {}} {258 0 0-454 {}} {258 0 0-456 {}} {258 0 0-466 {}} {258 0 0-476 {}} {258 0 0-486 {}} {258 0 0-490 {}} {258 0 0-492 {}} {258 0 0-513 {}} {258 0 0-522 {}} {258 0 0-531 {}} {258 0 0-534 {}} {256 0 0-782 {}}} CYCLES {}}
+set a(0-447) {NAME slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-363 XREFS 3548 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{259 0 0-446 {}}} SUCCS {{258 0 0-455 {}}} CYCLES {}}
+set a(0-448) {NAME slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-363 XREFS 3549 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-446 {}}} SUCCS {{258 0 0-452 {}}} CYCLES {}}
+set a(0-449) {NAME slc(i#6.lpi#1.dfm)#2 TYPE READSLICE PAR 0-363 XREFS 3550 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-446 {}}} SUCCS {{258 0 0-458 {}}} CYCLES {}}
+set a(0-450) {NAME slc(i#6.lpi#1.dfm)#3 TYPE READSLICE PAR 0-363 XREFS 3551 LOC {1 0.016406775 1 0.044373425 1 0.044373425 3 1.0} PREDS {{258 0 0-446 {}}} SUCCS {} CYCLES {}}
+set a(0-451) {NAME FRAME:for:slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-363 XREFS 3552 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-446 {}}} SUCCS {{258 0 0-453 {}}} CYCLES {}}
+set a(0-452) {NAME FRAME:for:not#1 TYPE NOT PAR 0-363 XREFS 3553 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-448 {}}} SUCCS {{259 0 0-453 {}}} CYCLES {}}
+set a(0-453) {NAME FRAME:for:nand TYPE NAND PAR 0-363 XREFS 3554 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-451 {}} {259 0 0-452 {}}} SUCCS {{258 0 0-459 {}}} CYCLES {}}
+set a(0-454) {NAME FRAME:for:slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-363 XREFS 3555 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-446 {}}} SUCCS {{259 0 0-455 {}}} CYCLES {}}
+set a(0-455) {NAME FRAME:for:nor TYPE NOR PAR 0-363 XREFS 3556 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-447 {}} {259 0 0-454 {}}} SUCCS {{258 0 0-459 {}}} CYCLES {}}
+set a(0-456) {NAME FRAME:for:slc(i#6.lpi#1.dfm)#2 TYPE READSLICE PAR 0-363 XREFS 3557 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-446 {}}} SUCCS {{259 0 0-457 {}}} CYCLES {}}
+set a(0-457) {NAME FRAME:for:not#2 TYPE NOT PAR 0-363 XREFS 3558 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{259 0 0-456 {}}} SUCCS {{259 0 0-458 {}}} CYCLES {}}
+set a(0-458) {NAME FRAME:for:and#3 TYPE AND PAR 0-363 XREFS 3559 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-449 {}} {259 0 0-457 {}}} SUCCS {{259 0 0-459 {}}} CYCLES {}}
+set a(0-459) {NAME FRAME:for:or#3 TYPE OR PAR 0-363 XREFS 3560 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-455 {}} {258 0 0-453 {}} {259 0 0-458 {}}} SUCCS {{258 0 0-467 {}} {258 0 0-477 {}} {258 0 0-487 {}}} CYCLES {}}
+set a(0-460) {NAME FRAME:for:slc(r(0).sva) TYPE READSLICE PAR 0-363 XREFS 3561 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.11560675} PREDS {{258 0 0-391 {}} {258 0 0-371 {}}} SUCCS {{259 0 0-461 {}}} CYCLES {}}
+set a(0-461) {NAME FRAME:for:exs#20 TYPE SIGNEXTEND PAR 0-363 XREFS 3562 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.11560675} PREDS {{259 0 0-460 {}}} SUCCS {{259 0 0-462 {}}} CYCLES {}}
+set a(0-462) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#5 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-363 XREFS 3563 LOC {1 0.0753708 1 0.382656675 1 0.382656675 1 0.4057172375 2 0.1386673125} PREDS {{258 0 0-380 {}} {262 0 0-775 {}} {259 0 0-461 {}}} SUCCS {{258 0 0-469 {}} {256 0 0-775 {}}} CYCLES {}}
+set a(0-463) {NAME {regs.operator[]#9:slc(regs.regs(2))} TYPE READSLICE PAR 0-363 XREFS 3564 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-443 {}}} SUCCS {{258 0 0-466 {}}} CYCLES {}}
+set a(0-464) {NAME {regs.operator[]#9:slc(regs.regs(1))} TYPE READSLICE PAR 0-363 XREFS 3565 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-441 {}}} SUCCS {{258 0 0-466 {}}} CYCLES {}}
+set a(0-465) {NAME {regs.operator[]#9:slc(regs.regs(0))} TYPE READSLICE PAR 0-363 XREFS 3566 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-438 {}}} SUCCS {{259 0 0-466 {}}} CYCLES {}}
+set a(0-466) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#9:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3567 LOC {1 0.0230606 1 0.15426555 1 0.15426555 1 0.2127933 1 0.807076025} PREDS {{258 0 0-446 {}} {258 0 0-464 {}} {258 0 0-463 {}} {259 0 0-465 {}}} SUCCS {{258 0 0-468 {}}} CYCLES {}}
+set a(0-467) {NAME FRAME:for:conc#5 TYPE CONCATENATE PAR 0-363 XREFS 3568 LOC {1 0.016406775 1 0.21279335 1 0.21279335 1 0.807076075} PREDS {{258 0 0-459 {}}} SUCCS {{259 0 0-468 {}}} CYCLES {}}
+set a(0-468) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-363 XREFS 3569 LOC {1 0.08158839999999999 1 0.21279335 1 0.21279335 1 0.4057172125 1 0.9999999374999999} PREDS {{258 0 0-466 {}} {259 0 0-467 {}}} SUCCS {{259 0 0-469 {}}} CYCLES {}}
+set a(0-469) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#1 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-363 XREFS 3570 LOC {1 0.274512325 1 0.405717275 1 0.405717275 1 0.5117190163378799 2 0.24466909133787984} PREDS {{258 0 0-462 {}} {259 0 0-468 {}}} SUCCS {{258 0 0-554 {}} {258 0 0-775 {}}} CYCLES {}}
+set a(0-470) {NAME FRAME:for:slc(g(0).sva) TYPE READSLICE PAR 0-363 XREFS 3571 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{258 0 0-400 {}} {258 0 0-370 {}}} SUCCS {{259 0 0-471 {}}} CYCLES {}}
+set a(0-471) {NAME FRAME:for:exs#21 TYPE SIGNEXTEND PAR 0-363 XREFS 3572 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{259 0 0-470 {}}} SUCCS {{259 0 0-472 {}}} CYCLES {}}
+set a(0-472) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#7 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-363 XREFS 3573 LOC {1 0.0753708 1 0.382656675 1 0.382656675 1 0.4057172375 2 0.0650410125} PREDS {{258 0 0-380 {}} {262 0 0-777 {}} {259 0 0-471 {}}} SUCCS {{258 0 0-479 {}} {256 0 0-777 {}}} CYCLES {}}
+set a(0-473) {NAME {regs.operator[]#10:slc(regs.regs(2))} TYPE READSLICE PAR 0-363 XREFS 3574 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-443 {}}} SUCCS {{258 0 0-476 {}}} CYCLES {}}
+set a(0-474) {NAME {regs.operator[]#10:slc(regs.regs(1))} TYPE READSLICE PAR 0-363 XREFS 3575 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-441 {}}} SUCCS {{258 0 0-476 {}}} CYCLES {}}
+set a(0-475) {NAME {regs.operator[]#10:slc(regs.regs(0))} TYPE READSLICE PAR 0-363 XREFS 3576 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-438 {}}} SUCCS {{259 0 0-476 {}}} CYCLES {}}
+set a(0-476) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#10:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3577 LOC {1 0.0230606 1 0.15426555 1 0.15426555 1 0.2127933 1 0.807076025} PREDS {{258 0 0-446 {}} {258 0 0-474 {}} {258 0 0-473 {}} {259 0 0-475 {}}} SUCCS {{258 0 0-478 {}}} CYCLES {}}
+set a(0-477) {NAME FRAME:for:conc#6 TYPE CONCATENATE PAR 0-363 XREFS 3578 LOC {1 0.016406775 1 0.21279335 1 0.21279335 1 0.807076075} PREDS {{258 0 0-459 {}}} SUCCS {{259 0 0-478 {}}} CYCLES {}}
+set a(0-478) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#1 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-363 XREFS 3579 LOC {1 0.08158839999999999 1 0.21279335 1 0.21279335 1 0.4057172125 1 0.9999999374999999} PREDS {{258 0 0-476 {}} {259 0 0-477 {}}} SUCCS {{259 0 0-479 {}}} CYCLES {}}
+set a(0-479) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#2 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-363 XREFS 3580 LOC {1 0.274512325 1 0.405717275 1 0.405717275 1 0.5117190163378799 2 0.17104279133787986} PREDS {{258 0 0-472 {}} {259 0 0-478 {}}} SUCCS {{258 0 0-569 {}} {258 0 0-777 {}}} CYCLES {}}
+set a(0-480) {NAME FRAME:for:slc(b(0).sva) TYPE READSLICE PAR 0-363 XREFS 3581 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{258 0 0-409 {}} {258 0 0-369 {}}} SUCCS {{259 0 0-481 {}}} CYCLES {}}
+set a(0-481) {NAME FRAME:for:exs#22 TYPE SIGNEXTEND PAR 0-363 XREFS 3582 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{259 0 0-480 {}}} SUCCS {{259 0 0-482 {}}} CYCLES {}}
+set a(0-482) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#9 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-363 XREFS 3583 LOC {1 0.0753708 1 0.382656675 1 0.382656675 1 0.4057172375 2 0.0650410125} PREDS {{258 0 0-380 {}} {262 0 0-779 {}} {259 0 0-481 {}}} SUCCS {{258 0 0-489 {}} {256 0 0-779 {}}} CYCLES {}}
+set a(0-483) {NAME {regs.operator[]#11:slc(regs.regs(2))} TYPE READSLICE PAR 0-363 XREFS 3584 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-443 {}}} SUCCS {{258 0 0-486 {}}} CYCLES {}}
+set a(0-484) {NAME {regs.operator[]#11:slc(regs.regs(1))} TYPE READSLICE PAR 0-363 XREFS 3585 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-441 {}}} SUCCS {{258 0 0-486 {}}} CYCLES {}}
+set a(0-485) {NAME {regs.operator[]#11:slc(regs.regs(0))} TYPE READSLICE PAR 0-363 XREFS 3586 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-438 {}}} SUCCS {{259 0 0-486 {}}} CYCLES {}}
+set a(0-486) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#11:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3587 LOC {1 0.0230606 1 0.15426555 1 0.15426555 1 0.2127933 1 0.807076025} PREDS {{258 0 0-446 {}} {258 0 0-484 {}} {258 0 0-483 {}} {259 0 0-485 {}}} SUCCS {{258 0 0-488 {}}} CYCLES {}}
+set a(0-487) {NAME FRAME:for:conc#7 TYPE CONCATENATE PAR 0-363 XREFS 3588 LOC {1 0.016406775 1 0.21279335 1 0.21279335 1 0.807076075} PREDS {{258 0 0-459 {}}} SUCCS {{259 0 0-488 {}}} CYCLES {}}
+set a(0-488) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#2 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-363 XREFS 3589 LOC {1 0.08158839999999999 1 0.21279335 1 0.21279335 1 0.4057172125 1 0.9999999374999999} PREDS {{258 0 0-486 {}} {259 0 0-487 {}}} SUCCS {{259 0 0-489 {}}} CYCLES {}}
+set a(0-489) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#3 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-363 XREFS 3590 LOC {1 0.274512325 1 0.405717275 1 0.405717275 1 0.5117190163378799 2 0.17104279133787986} PREDS {{258 0 0-482 {}} {259 0 0-488 {}}} SUCCS {{258 0 0-584 {}} {258 0 0-779 {}}} CYCLES {}}
+set a(0-490) {NAME i:slc(i#3)#1 TYPE READSLICE PAR 0-363 XREFS 3591 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{258 0 0-446 {}}} SUCCS {{259 0 0-491 {}}} CYCLES {}}
+set a(0-491) {NAME FRAME:for:not#4 TYPE NOT PAR 0-363 XREFS 3592 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{259 0 0-490 {}}} SUCCS {{258 0 0-493 {}}} CYCLES {}}
+set a(0-492) {NAME i:slc(i#3)#2 TYPE READSLICE PAR 0-363 XREFS 3593 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{258 0 0-446 {}}} SUCCS {{259 0 0-493 {}}} CYCLES {}}
+set a(0-493) {NAME FRAME:for:conc TYPE CONCATENATE PAR 0-363 XREFS 3594 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{258 0 0-491 {}} {259 0 0-492 {}}} SUCCS {{259 0 0-494 {}} {258 0 0-495 {}} {258 0 0-496 {}} {258 0 0-497 {}} {258 0 0-498 {}} {258 0 0-502 {}}} CYCLES {}}
+set a(0-494) {NAME slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-363 XREFS 3595 LOC {1 0.016406775 1 0.044373425 1 0.044373425 3 1.0} PREDS {{259 0 0-493 {}}} SUCCS {} CYCLES {}}
+set a(0-495) {NAME slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-363 XREFS 3596 LOC {1 0.016406775 1 0.044373425 1 0.044373425 3 1.0} PREDS {{258 0 0-493 {}}} SUCCS {} CYCLES {}}
+set a(0-496) {NAME slc(FRAME:for:conc.tmp)#2 TYPE READSLICE PAR 0-363 XREFS 3597 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.6843317999999999} PREDS {{258 0 0-493 {}}} SUCCS {{258 0 0-504 {}}} CYCLES {}}
+set a(0-497) {NAME slc(FRAME:for:conc.tmp)#3 TYPE READSLICE PAR 0-363 XREFS 3598 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{258 0 0-493 {}}} SUCCS {{258 0 0-499 {}}} CYCLES {}}
+set a(0-498) {NAME FRAME:for:slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-363 XREFS 3599 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{258 0 0-493 {}}} SUCCS {{259 0 0-499 {}}} CYCLES {}}
+set a(0-499) {NAME FRAME:for:nand#1 TYPE NAND PAR 0-363 XREFS 3600 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{258 0 0-497 {}} {259 0 0-498 {}}} SUCCS {{259 0 0-500 {}}} CYCLES {}}
+set a(0-500) {NAME FRAME:for:exs#26 TYPE SIGNEXTEND PAR 0-363 XREFS 3601 LOC {1 0.016406775 1 0.069751975 1 0.069751975 1 0.667925025} PREDS {{259 0 0-499 {}}} SUCCS {{259 0 0-501 {}}} CYCLES {}}
+set a(0-501) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 2 NAME FRAME:for:and#4 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-363 XREFS 3602 LOC {1 0.016406775 1 0.069751975 1 0.069751975 1 0.0861587062638539 1 0.6843317562638539} PREDS {{259 0 0-500 {}}} SUCCS {{258 0 0-506 {}}} CYCLES {}}
+set a(0-502) {NAME FRAME:for:slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-363 XREFS 3603 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.6843317999999999} PREDS {{258 0 0-493 {}}} SUCCS {{259 0 0-503 {}}} CYCLES {}}
+set a(0-503) {NAME FRAME:for:not#3 TYPE NOT PAR 0-363 XREFS 3604 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.6843317999999999} PREDS {{259 0 0-502 {}}} SUCCS {{259 0 0-504 {}}} CYCLES {}}
+set a(0-504) {NAME FRAME:for:and#5 TYPE AND PAR 0-363 XREFS 3605 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.6843317999999999} PREDS {{258 0 0-496 {}} {259 0 0-503 {}}} SUCCS {{259 0 0-505 {}}} CYCLES {}}
+set a(0-505) {NAME FRAME:for:exs#27 TYPE SIGNEXTEND PAR 0-363 XREFS 3606 LOC {1 0.016406775 1 0.08615874999999999 1 0.08615874999999999 1 0.6843317999999999} PREDS {{259 0 0-504 {}}} SUCCS {{259 0 0-506 {}}} CYCLES {}}
+set a(0-506) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(2,2) AREA_SCORE 1.46 QUANTITY 1 NAME FRAME:for:or#4 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-363 XREFS 3607 LOC {1 0.03281355 1 0.08615874999999999 1 0.08615874999999999 1 0.10290118110773884 1 0.7010742311077388} PREDS {{258 0 0-501 {}} {259 0 0-505 {}}} SUCCS {{258 0 0-514 {}} {258 0 0-523 {}} {258 0 0-532 {}}} CYCLES {}}
+set a(0-507) {NAME FRAME:for:slc(r(2).sva) TYPE READSLICE PAR 0-363 XREFS 3608 LOC {1 0.0753708 1 0.27276455 1 0.27276455 2 0.005714625} PREDS {{258 0 0-418 {}} {258 0 0-368 {}}} SUCCS {{259 0 0-508 {}}} CYCLES {}}
+set a(0-508) {NAME FRAME:for:exs#23 TYPE SIGNEXTEND PAR 0-363 XREFS 3609 LOC {1 0.0753708 1 0.27276455 1 0.27276455 2 0.005714625} PREDS {{259 0 0-507 {}}} SUCCS {{259 0 0-509 {}}} CYCLES {}}
+set a(0-509) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#6 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-363 XREFS 3610 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.2958251125 2 0.0287751875} PREDS {{258 0 0-380 {}} {262 0 0-776 {}} {259 0 0-508 {}}} SUCCS {{258 0 0-515 {}} {256 0 0-776 {}}} CYCLES {}}
+set a(0-510) {NAME {regs.operator[]#15:slc(regs.regs(2))} TYPE READSLICE PAR 0-363 XREFS 3611 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-443 {}}} SUCCS {{258 0 0-513 {}}} CYCLES {}}
+set a(0-511) {NAME {regs.operator[]#15:slc(regs.regs(1))} TYPE READSLICE PAR 0-363 XREFS 3612 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-441 {}}} SUCCS {{258 0 0-513 {}}} CYCLES {}}
+set a(0-512) {NAME {regs.operator[]#15:slc(regs.regs(0))} TYPE READSLICE PAR 0-363 XREFS 3613 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-438 {}}} SUCCS {{259 0 0-513 {}}} CYCLES {}}
+set a(0-513) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#15:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3614 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.102901175 1 0.807076025} PREDS {{258 0 0-446 {}} {258 0 0-511 {}} {258 0 0-510 {}} {259 0 0-512 {}}} SUCCS {{259 0 0-514 {}}} CYCLES {}}
+set a(0-514) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#6 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-363 XREFS 3615 LOC {1 0.08158839999999999 1 0.102901225 1 0.102901225 1 0.2958250875 1 0.9999999374999999} PREDS {{258 0 0-506 {}} {259 0 0-513 {}}} SUCCS {{259 0 0-515 {}}} CYCLES {}}
+set a(0-515) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#10 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-363 XREFS 3616 LOC {1 0.274512325 1 0.29582515 1 0.29582515 1 0.40182689133787985 2 0.13477696633787986} PREDS {{258 0 0-509 {}} {259 0 0-514 {}}} SUCCS {{258 0 0-541 {}} {258 0 0-776 {}}} CYCLES {}}
+set a(0-516) {NAME FRAME:for:slc(g(2).sva) TYPE READSLICE PAR 0-363 XREFS 3617 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{258 0 0-427 {}} {258 0 0-367 {}}} SUCCS {{259 0 0-517 {}}} CYCLES {}}
+set a(0-517) {NAME FRAME:for:exs#24 TYPE SIGNEXTEND PAR 0-363 XREFS 3618 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{259 0 0-516 {}}} SUCCS {{259 0 0-518 {}}} CYCLES {}}
+set a(0-518) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#8 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-363 XREFS 3619 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.2958251125 1 0.8939981625} PREDS {{258 0 0-380 {}} {262 0 0-778 {}} {259 0 0-517 {}}} SUCCS {{258 0 0-524 {}} {256 0 0-778 {}}} CYCLES {}}
+set a(0-519) {NAME {regs.operator[]#16:slc(regs.regs(2))} TYPE READSLICE PAR 0-363 XREFS 3620 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.642546475} PREDS {{258 0 0-443 {}}} SUCCS {{258 0 0-522 {}}} CYCLES {}}
+set a(0-520) {NAME {regs.operator[]#16:slc(regs.regs(1))} TYPE READSLICE PAR 0-363 XREFS 3621 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.642546475} PREDS {{258 0 0-441 {}}} SUCCS {{258 0 0-522 {}}} CYCLES {}}
+set a(0-521) {NAME {regs.operator[]#16:slc(regs.regs(0))} TYPE READSLICE PAR 0-363 XREFS 3622 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.642546475} PREDS {{258 0 0-438 {}}} SUCCS {{259 0 0-522 {}}} CYCLES {}}
+set a(0-522) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#16:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3623 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.102901175 1 0.7010742249999999} PREDS {{258 0 0-446 {}} {258 0 0-520 {}} {258 0 0-519 {}} {259 0 0-521 {}}} SUCCS {{259 0 0-523 {}}} CYCLES {}}
+set a(0-523) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#7 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-363 XREFS 3624 LOC {1 0.08158839999999999 1 0.102901225 1 0.102901225 1 0.2958250875 1 0.8939981374999999} PREDS {{258 0 0-506 {}} {259 0 0-522 {}}} SUCCS {{259 0 0-524 {}}} CYCLES {}}
+set a(0-524) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#12 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-363 XREFS 3625 LOC {1 0.274512325 1 0.29582515 1 0.29582515 1 0.40182689133787985 1 0.9999999413378798} PREDS {{258 0 0-518 {}} {259 0 0-523 {}}} SUCCS {{258 0 0-556 {}} {258 0 0-778 {}}} CYCLES {}}
+set a(0-525) {NAME FRAME:for:slc(b(2).sva) TYPE READSLICE PAR 0-363 XREFS 3626 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{258 0 0-436 {}} {258 0 0-366 {}}} SUCCS {{259 0 0-526 {}}} CYCLES {}}
+set a(0-526) {NAME FRAME:for:exs#25 TYPE SIGNEXTEND PAR 0-363 XREFS 3627 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{259 0 0-525 {}}} SUCCS {{259 0 0-527 {}}} CYCLES {}}
+set a(0-527) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#10 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-363 XREFS 3628 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.2958251125 1 0.8939981625} PREDS {{258 0 0-380 {}} {262 0 0-780 {}} {259 0 0-526 {}}} SUCCS {{258 0 0-533 {}} {256 0 0-780 {}}} CYCLES {}}
+set a(0-528) {NAME {regs.operator[]#17:slc(regs.regs(2))} TYPE READSLICE PAR 0-363 XREFS 3629 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.642546475} PREDS {{258 0 0-443 {}}} SUCCS {{258 0 0-531 {}}} CYCLES {}}
+set a(0-529) {NAME {regs.operator[]#17:slc(regs.regs(1))} TYPE READSLICE PAR 0-363 XREFS 3630 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.642546475} PREDS {{258 0 0-441 {}}} SUCCS {{258 0 0-531 {}}} CYCLES {}}
+set a(0-530) {NAME {regs.operator[]#17:slc(regs.regs(0))} TYPE READSLICE PAR 0-363 XREFS 3631 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.642546475} PREDS {{258 0 0-438 {}}} SUCCS {{259 0 0-531 {}}} CYCLES {}}
+set a(0-531) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#17:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3632 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.102901175 1 0.7010742249999999} PREDS {{258 0 0-446 {}} {258 0 0-529 {}} {258 0 0-528 {}} {259 0 0-530 {}}} SUCCS {{259 0 0-532 {}}} CYCLES {}}
+set a(0-532) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#8 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-363 XREFS 3633 LOC {1 0.08158839999999999 1 0.102901225 1 0.102901225 1 0.2958250875 1 0.8939981374999999} PREDS {{258 0 0-506 {}} {259 0 0-531 {}}} SUCCS {{259 0 0-533 {}}} CYCLES {}}
+set a(0-533) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#14 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-363 XREFS 3634 LOC {1 0.274512325 1 0.29582515 1 0.29582515 1 0.40182689133787985 1 0.9999999413378798} PREDS {{258 0 0-527 {}} {259 0 0-532 {}}} SUCCS {{258 0 0-571 {}} {258 0 0-780 {}}} CYCLES {}}
+set a(0-534) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,2) AREA_SCORE 3.31 QUANTITY 1 NAME FRAME:for:acc#16 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-363 XREFS 3635 LOC {1 0.016406775 1 0.23399947499999998 1 0.23399947499999998 1 0.2747824850894752 1 0.8729555350894752} PREDS {{258 0 0-446 {}}} SUCCS {{259 0 0-535 {}} {258 0 0-782 {}}} CYCLES {}}
+set a(0-535) {NAME FRAME:for:asn#2 TYPE ASSIGN PAR 0-363 XREFS 3636 LOC {1 0.057189825 1 0.274782525 1 0.274782525 1 0.872955575} PREDS {{259 0 0-534 {}}} SUCCS {{259 0 0-536 {}}} CYCLES {}}
+set a(0-536) {NAME FRAME:for:conc#11 TYPE CONCATENATE PAR 0-363 XREFS 3637 LOC {1 0.057189825 1 0.274782525 1 0.274782525 1 0.872955575} PREDS {{259 0 0-535 {}}} SUCCS {{259 0 0-537 {}}} CYCLES {}}
+set a(0-537) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,3) AREA_SCORE 4.30 QUANTITY 1 NAME FRAME:for:acc TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-363 XREFS 3638 LOC {1 0.057189825 1 0.274782525 1 0.274782525 1 0.3223386520708272 1 0.9205117020708271} PREDS {{259 0 0-536 {}}} SUCCS {{259 0 0-538 {}}} CYCLES {}}
+set a(0-538) {NAME FRAME:for:slc TYPE READSLICE PAR 0-363 XREFS 3639 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{259 0 0-537 {}}} SUCCS {{259 0 0-539 {}}} CYCLES {}}
+set a(0-539) {NAME FRAME:for:not TYPE NOT PAR 0-363 XREFS 3640 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{259 0 0-538 {}}} SUCCS {{259 0 0-540 {}} {258 0 0-768 {}} {258 0 0-770 {}} {258 0 0-771 {}} {258 0 0-781 {}}} CYCLES {}}
+set a(0-540) {NAME FRAME:for:select#2 TYPE SELECT PAR 0-363 XREFS 3641 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{259 0 0-539 {}}} SUCCS {{146 0 0-541 {}} {146 0 0-542 {}} {146 0 0-543 {}} {146 0 0-544 {}} {146 0 0-545 {}} {146 0 0-546 {}} {146 0 0-547 {}} {146 0 0-548 {}} {146 0 0-549 {}} {146 0 0-550 {}} {146 0 0-551 {}} {146 0 0-552 {}} {146 0 0-553 {}} {146 0 0-554 {}} {146 0 0-555 {}} {146 0 0-556 {}} {146 0 0-557 {}} {146 0 0-558 {}} {146 0 0-559 {}} {146 0 0-560 {}} {146 0 0-561 {}} {146 0 0-562 {}} {146 0 0-563 {}} {146 0 0-564 {}} {146 0 0-565 {}} {146 0 0-566 {}} {146 0 0-567 {}} {146 0 0-568 {}} {146 0 0-569 {}} {146 0 0-570 {}} {146 0 0-571 {}} {146 0 0-572 {}} {146 0 0-573 {}} {146 0 0-574 {}} {146 0 0-575 {}} {146 0 0-576 {}} {146 0 0-577 {}} {146 0 0-578 {}} {146 0 0-579 {}} {146 0 0-580 {}} {146 0 0-581 {}} {146 0 0-582 {}} {146 0 0-583 {}} {146 0 0-584 {}} {146 0 0-585 {}} {146 0 0-586 {}} {146 0 0-587 {}} {146 0 0-588 {}} {146 0 0-589 {}} {146 0 0-590 {}} {146 0 0-591 {}} {146 0 0-592 {}} {146 0 0-593 {}} {146 0 0-594 {}} {146 0 0-595 {}} {146 0 0-596 {}} {146 0 0-597 {}} {146 0 0-598 {}} {146 0 0-599 {}} {146 0 0-600 {}} {146 0 0-601 {}} {146 0 0-602 {}} {146 0 0-603 {}} {146 0 0-604 {}} {146 0 0-605 {}} {146 0 0-606 {}} {146 0 0-607 {}} {146 0 0-608 {}} {146 0 0-609 {}} {146 0 0-610 {}} {146 0 0-611 {}} {146 0 0-612 {}} {146 0 0-613 {}} {146 0 0-614 {}} {146 0 0-615 {}} {146 0 0-616 {}} {146 0 0-617 {}} {146 0 0-618 {}} {146 0 0-619 {}} {146 0 0-620 {}} {146 0 0-621 {}} {146 0 0-622 {}} {146 0 0-623 {}} {146 0 0-624 {}} {146 0 0-625 {}} {146 0 0-626 {}} {146 0 0-627 {}} {146 0 0-628 {}} {146 0 0-629 {}} {146 0 0-630 {}} {146 0 0-631 {}} {146 0 0-632 {}} {146 0 0-633 {}} {146 0 0-634 {}} {146 0 0-635 {}} {146 0 0-636 {}} {146 0 0-637 {}} {146 0 0-638 {}} {146 0 0-639 {}} {146 0 0-640 {}} {146 0 0-641 {}} {146 0 0-642 {}} {146 0 0-643 {}} {146 0 0-644 {}} {146 0 0-645 {}} {146 0 0-646 {}} {146 0 0-647 {}} {146 0 0-648 {}} {146 0 0-649 {}} {146 0 0-650 {}} {146 0 0-651 {}} {146 0 0-652 {}} {146 0 0-653 {}} {146 0 0-654 {}} {146 0 0-655 {}} {146 0 0-656 {}} {146 0 0-657 {}} {146 0 0-658 {}} {146 0 0-659 {}} {146 0 0-660 {}} {146 0 0-661 {}} {146 0 0-662 {}} {146 0 0-663 {}} {146 0 0-664 {}} {146 0 0-665 {}} {146 0 0-666 {}} {146 0 0-667 {}} {146 0 0-668 {}} {146 0 0-669 {}} {146 0 0-670 {}} {146 0 0-671 {}} {146 0 0-672 {}} {146 0 0-673 {}} {146 0 0-674 {}} {146 0 0-675 {}} {146 0 0-676 {}} {146 0 0-677 {}} {146 0 0-678 {}} {146 0 0-679 {}} {146 0 0-680 {}} {146 0 0-681 {}} {146 0 0-682 {}} {146 0 0-683 {}} {146 0 0-684 {}} {146 0 0-685 {}} {146 0 0-686 {}} {146 0 0-687 {}} {146 0 0-688 {}} {146 0 0-689 {}} {146 0 0-690 {}} {146 0 0-691 {}} {146 0 0-692 {}} {146 0 0-693 {}} {146 0 0-694 {}} {146 0 0-695 {}} {146 0 0-696 {}} {146 0 0-697 {}} {146 0 0-698 {}} {146 0 0-699 {}} {146 0 0-700 {}} {146 0 0-701 {}} {146 0 0-702 {}} {146 0 0-703 {}} {146 0 0-704 {}} {146 0 0-705 {}} {146 0 0-706 {}} {146 0 0-707 {}} {146 0 0-708 {}} {146 0 0-709 {}} {146 0 0-710 {}} {146 0 0-711 {}} {146 0 0-712 {}} {146 0 0-713 {}} {146 0 0-714 {}} {146 0 0-715 {}} {146 0 0-716 {}} {146 0 0-717 {}} {146 0 0-718 {}} {146 0 0-719 {}} {146 0 0-720 {}} {146 0 0-721 {}} {146 0 0-722 {}} {146 0 0-723 {}} {146 0 0-724 {}} {146 0 0-725 {}} {146 0 0-726 {}} {146 0 0-727 {}} {146 0 0-728 {}} {146 0 0-729 {}} {146 0 0-730 {}} {146 0 0-731 {}} {146 0 0-732 {}} {146 0 0-733 {}} {146 0 0-734 {}} {146 0 0-735 {}} {146 0 0-736 {}} {146 0 0-737 {}} {146 0 0-738 {}} {146 0 0-739 {}} {146 0 0-740 {}} {146 0 0-741 {}} {146 0 0-742 {}} {146 0 0-743 {}} {146 0 0-744 {}} {146 0 0-745 {}} {146 0 0-746 {}} {146 0 0-747 {}} {146 0 0-748 {}} {146 0 0-749 {}} {146 0 0-750 {}} {146 0 0-751 {}} {146 0 0-752 {}} {146 0 0-753 {}} {146 0 0-754 {}} {146 0 0-755 {}} {146 0 0-756 {}} {146 0 0-757 {}} {146 0 0-758 {}} {146 0 0-759 {}} {130 0 0-760 {}} {146 0 0-761 {}} {146 0 0-762 {}} {146 0 0-763 {}} {146 0 0-764 {}} {146 0 0-765 {}}} CYCLES {}}
+set a(0-541) {NAME ACC1:conc#34 TYPE CONCATENATE PAR 0-363 XREFS 3642 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 2 0.134777025} PREDS {{146 0 0-540 {}} {258 0 0-515 {}}} SUCCS {{258 0 0-552 {}}} CYCLES {}}
+set a(0-542) {NAME ACC2:slc(regs.regs(0)) TYPE READSLICE PAR 0-363 XREFS 3643 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-540 {}} {258 0 0-438 {}}} SUCCS {{259 0 0-543 {}}} CYCLES {}}
+set a(0-543) {NAME ACC2:not TYPE NOT PAR 0-363 XREFS 3644 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-540 {}} {259 0 0-542 {}}} SUCCS {{259 0 0-544 {}}} CYCLES {}}
+set a(0-544) {NAME ACC2:conc TYPE CONCATENATE PAR 0-363 XREFS 3645 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-540 {}} {259 0 0-543 {}}} SUCCS {{259 0 0-545 {}}} CYCLES {}}
+set a(0-545) {NAME ACC1:conc#32 TYPE CONCATENATE PAR 0-363 XREFS 3646 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-540 {}} {259 0 0-544 {}}} SUCCS {{258 0 0-549 {}}} CYCLES {}}
+set a(0-546) {NAME ACC2:slc(regs.regs(2)) TYPE READSLICE PAR 0-363 XREFS 3647 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-540 {}} {258 0 0-443 {}}} SUCCS {{259 0 0-547 {}}} CYCLES {}}
+set a(0-547) {NAME ACC2:conc#1 TYPE CONCATENATE PAR 0-363 XREFS 3648 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-540 {}} {259 0 0-546 {}}} SUCCS {{259 0 0-548 {}}} CYCLES {}}
+set a(0-548) {NAME ACC1:conc#33 TYPE CONCATENATE PAR 0-363 XREFS 3649 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-540 {}} {259 0 0-547 {}}} SUCCS {{259 0 0-549 {}}} CYCLES {}}
+set a(0-549) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME ACC1:acc#53 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-363 XREFS 3650 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.4018269034997777 2 0.13477697849977766} PREDS {{146 0 0-540 {}} {258 0 0-545 {}} {259 0 0-548 {}}} SUCCS {{259 0 0-550 {}}} CYCLES {}}
+set a(0-550) {NAME ACC1:slc#6 TYPE READSLICE PAR 0-363 XREFS 3651 LOC {1 0.18423425 1 0.40182694999999996 1 0.40182694999999996 2 0.134777025} PREDS {{146 0 0-540 {}} {259 0 0-549 {}}} SUCCS {{259 0 0-551 {}}} CYCLES {}}
+set a(0-551) {NAME ACC1:conc#35 TYPE CONCATENATE PAR 0-363 XREFS 3652 LOC {1 0.18423425 1 0.40182694999999996 1 0.40182694999999996 2 0.134777025} PREDS {{146 0 0-540 {}} {259 0 0-550 {}}} SUCCS {{259 0 0-552 {}}} CYCLES {}}
+set a(0-552) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(17,0,13,1,17) AREA_SCORE 18.00 QUANTITY 3 NAME ACC1:acc#54 TYPE ACCU DELAY {1.76 ns} LIBRARY_DELAY {1.76 ns} PAR 0-363 XREFS 3653 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 1 0.5117190147236815 2 0.24466908972368157} PREDS {{146 0 0-540 {}} {258 0 0-541 {}} {259 0 0-551 {}}} SUCCS {{259 0 0-553 {}}} CYCLES {}}
+set a(0-553) {NAME ACC1:slc#7 TYPE READSLICE PAR 0-363 XREFS 3654 LOC {1 0.49040625 1 0.511719075 1 0.511719075 2 0.24466915} PREDS {{146 0 0-540 {}} {259 0 0-552 {}}} SUCCS {{259 0 0-554 {}}} CYCLES {}}
+set a(0-554) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 3 NAME ACC1:acc#43 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-363 XREFS 3655 LOC {1 0.49040625 1 0.511719075 1 0.511719075 1 0.617328805357901 2 0.350278880357901} PREDS {{146 0 0-540 {}} {258 0 0-469 {}} {259 0 0-553 {}}} SUCCS {{259 0 0-555 {}}} CYCLES {}}
+set a(0-555) {NAME ACC2:slc TYPE READSLICE PAR 0-363 XREFS 3656 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-540 {}} {259 0 0-554 {}}} SUCCS {{258 0 0-586 {}} {258 0 0-587 {}} {258 0 0-590 {}} {258 0 0-592 {}} {258 0 0-595 {}} {258 0 0-598 {}} {258 0 0-599 {}} {258 0 0-714 {}} {258 0 0-716 {}} {258 0 0-717 {}} {258 0 0-719 {}} {258 0 0-722 {}} {258 0 0-724 {}} {258 0 0-741 {}}} CYCLES {}}
+set a(0-556) {NAME ACC1:conc#38 TYPE CONCATENATE PAR 0-363 XREFS 3657 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 2 0.061150724999999996} PREDS {{146 0 0-540 {}} {258 0 0-524 {}}} SUCCS {{258 0 0-567 {}}} CYCLES {}}
+set a(0-557) {NAME ACC2:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-363 XREFS 3658 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {258 0 0-438 {}}} SUCCS {{259 0 0-558 {}}} CYCLES {}}
+set a(0-558) {NAME ACC2:not#1 TYPE NOT PAR 0-363 XREFS 3659 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {259 0 0-557 {}}} SUCCS {{259 0 0-559 {}}} CYCLES {}}
+set a(0-559) {NAME ACC2:conc#2 TYPE CONCATENATE PAR 0-363 XREFS 3660 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {259 0 0-558 {}}} SUCCS {{259 0 0-560 {}}} CYCLES {}}
+set a(0-560) {NAME ACC1:conc#36 TYPE CONCATENATE PAR 0-363 XREFS 3661 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {259 0 0-559 {}}} SUCCS {{258 0 0-564 {}}} CYCLES {}}
+set a(0-561) {NAME ACC2:slc(regs.regs(2))#1 TYPE READSLICE PAR 0-363 XREFS 3662 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {258 0 0-443 {}}} SUCCS {{259 0 0-562 {}}} CYCLES {}}
+set a(0-562) {NAME ACC2:conc#3 TYPE CONCATENATE PAR 0-363 XREFS 3663 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {259 0 0-561 {}}} SUCCS {{259 0 0-563 {}}} CYCLES {}}
+set a(0-563) {NAME ACC1:conc#37 TYPE CONCATENATE PAR 0-363 XREFS 3664 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {259 0 0-562 {}}} SUCCS {{259 0 0-564 {}}} CYCLES {}}
+set a(0-564) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME ACC1:acc#55 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-363 XREFS 3665 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.4018269034997777 1 0.9999999534997777} PREDS {{146 0 0-540 {}} {258 0 0-560 {}} {259 0 0-563 {}}} SUCCS {{259 0 0-565 {}}} CYCLES {}}
+set a(0-565) {NAME ACC1:slc#8 TYPE READSLICE PAR 0-363 XREFS 3666 LOC {1 0.18423425 1 0.40182694999999996 1 0.40182694999999996 2 0.061150724999999996} PREDS {{146 0 0-540 {}} {259 0 0-564 {}}} SUCCS {{259 0 0-566 {}}} CYCLES {}}
+set a(0-566) {NAME ACC1:conc#39 TYPE CONCATENATE PAR 0-363 XREFS 3667 LOC {1 0.18423425 1 0.40182694999999996 1 0.40182694999999996 2 0.061150724999999996} PREDS {{146 0 0-540 {}} {259 0 0-565 {}}} SUCCS {{259 0 0-567 {}}} CYCLES {}}
+set a(0-567) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(17,0,13,1,17) AREA_SCORE 18.00 QUANTITY 3 NAME ACC1:acc#56 TYPE ACCU DELAY {1.76 ns} LIBRARY_DELAY {1.76 ns} PAR 0-363 XREFS 3668 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 1 0.5117190147236815 2 0.17104278972368156} PREDS {{146 0 0-540 {}} {258 0 0-556 {}} {259 0 0-566 {}}} SUCCS {{259 0 0-568 {}}} CYCLES {}}
+set a(0-568) {NAME ACC1:slc#9 TYPE READSLICE PAR 0-363 XREFS 3669 LOC {1 0.49040625 1 0.511719075 1 0.511719075 2 0.17104285} PREDS {{146 0 0-540 {}} {259 0 0-567 {}}} SUCCS {{259 0 0-569 {}}} CYCLES {}}
+set a(0-569) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 3 NAME ACC1:acc#44 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-363 XREFS 3670 LOC {1 0.49040625 1 0.511719075 1 0.511719075 1 0.617328805357901 2 0.27665258035790097} PREDS {{146 0 0-540 {}} {258 0 0-479 {}} {259 0 0-568 {}}} SUCCS {{259 0 0-570 {}}} CYCLES {}}
+set a(0-570) {NAME ACC2:slc#1 TYPE READSLICE PAR 0-363 XREFS 3671 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {259 0 0-569 {}}} SUCCS {{258 0 0-604 {}} {258 0 0-605 {}} {258 0 0-608 {}} {258 0 0-610 {}} {258 0 0-613 {}} {258 0 0-616 {}} {258 0 0-617 {}} {258 0 0-622 {}} {258 0 0-624 {}} {258 0 0-626 {}} {258 0 0-643 {}} {258 0 0-652 {}} {258 0 0-653 {}} {258 0 0-655 {}}} CYCLES {}}
+set a(0-571) {NAME ACC1:conc#42 TYPE CONCATENATE PAR 0-363 XREFS 3672 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 2 0.061150724999999996} PREDS {{146 0 0-540 {}} {258 0 0-533 {}}} SUCCS {{258 0 0-582 {}}} CYCLES {}}
+set a(0-572) {NAME ACC2:slc(regs.regs(0))#2 TYPE READSLICE PAR 0-363 XREFS 3673 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {258 0 0-438 {}}} SUCCS {{259 0 0-573 {}}} CYCLES {}}
+set a(0-573) {NAME ACC2:not#2 TYPE NOT PAR 0-363 XREFS 3674 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {259 0 0-572 {}}} SUCCS {{259 0 0-574 {}}} CYCLES {}}
+set a(0-574) {NAME ACC2:conc#4 TYPE CONCATENATE PAR 0-363 XREFS 3675 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {259 0 0-573 {}}} SUCCS {{259 0 0-575 {}}} CYCLES {}}
+set a(0-575) {NAME ACC1:conc#40 TYPE CONCATENATE PAR 0-363 XREFS 3676 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {259 0 0-574 {}}} SUCCS {{258 0 0-579 {}}} CYCLES {}}
+set a(0-576) {NAME ACC2:slc(regs.regs(2))#2 TYPE READSLICE PAR 0-363 XREFS 3677 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {258 0 0-443 {}}} SUCCS {{259 0 0-577 {}}} CYCLES {}}
+set a(0-577) {NAME ACC2:conc#5 TYPE CONCATENATE PAR 0-363 XREFS 3678 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {259 0 0-576 {}}} SUCCS {{259 0 0-578 {}}} CYCLES {}}
+set a(0-578) {NAME ACC1:conc#41 TYPE CONCATENATE PAR 0-363 XREFS 3679 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-540 {}} {259 0 0-577 {}}} SUCCS {{259 0 0-579 {}}} CYCLES {}}
+set a(0-579) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME ACC1:acc#57 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-363 XREFS 3680 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.4018269034997777 1 0.9999999534997777} PREDS {{146 0 0-540 {}} {258 0 0-575 {}} {259 0 0-578 {}}} SUCCS {{259 0 0-580 {}}} CYCLES {}}
+set a(0-580) {NAME ACC1:slc#10 TYPE READSLICE PAR 0-363 XREFS 3681 LOC {1 0.18423425 1 0.40182694999999996 1 0.40182694999999996 2 0.061150724999999996} PREDS {{146 0 0-540 {}} {259 0 0-579 {}}} SUCCS {{259 0 0-581 {}}} CYCLES {}}
+set a(0-581) {NAME ACC1:conc#43 TYPE CONCATENATE PAR 0-363 XREFS 3682 LOC {1 0.18423425 1 0.40182694999999996 1 0.40182694999999996 2 0.061150724999999996} PREDS {{146 0 0-540 {}} {259 0 0-580 {}}} SUCCS {{259 0 0-582 {}}} CYCLES {}}
+set a(0-582) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(17,0,13,1,17) AREA_SCORE 18.00 QUANTITY 3 NAME ACC1:acc#58 TYPE ACCU DELAY {1.76 ns} LIBRARY_DELAY {1.76 ns} PAR 0-363 XREFS 3683 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 1 0.5117190147236815 2 0.17104278972368156} PREDS {{146 0 0-540 {}} {258 0 0-571 {}} {259 0 0-581 {}}} SUCCS {{259 0 0-583 {}}} CYCLES {}}
+set a(0-583) {NAME ACC1:slc#11 TYPE READSLICE PAR 0-363 XREFS 3684 LOC {1 0.49040625 1 0.511719075 1 0.511719075 2 0.17104285} PREDS {{146 0 0-540 {}} {259 0 0-582 {}}} SUCCS {{259 0 0-584 {}}} CYCLES {}}
+set a(0-584) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 3 NAME ACC1:acc#45 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-363 XREFS 3685 LOC {1 0.49040625 1 0.511719075 1 0.511719075 1 0.617328805357901 2 0.27665258035790097} PREDS {{146 0 0-540 {}} {258 0 0-489 {}} {259 0 0-583 {}}} SUCCS {{259 0 0-585 {}}} CYCLES {}}
+set a(0-585) {NAME ACC2:slc#2 TYPE READSLICE PAR 0-363 XREFS 3686 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {259 0 0-584 {}}} SUCCS {{258 0 0-659 {}} {258 0 0-660 {}} {258 0 0-663 {}} {258 0 0-665 {}} {258 0 0-668 {}} {258 0 0-671 {}} {258 0 0-672 {}} {258 0 0-677 {}} {258 0 0-679 {}} {258 0 0-681 {}} {258 0 0-698 {}} {258 0 0-707 {}} {258 0 0-708 {}} {258 0 0-710 {}}} CYCLES {}}
+set a(0-586) {NAME red:slc(red#2.sg1)#4 TYPE READSLICE PAR 0-363 XREFS 3687 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{258 0 0-589 {}}} CYCLES {}}
+set a(0-587) {NAME red:slc(red#2.sg1)#5 TYPE READSLICE PAR 0-363 XREFS 3688 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{259 0 0-588 {}}} CYCLES {}}
+set a(0-588) {NAME FRAME:not#2 TYPE NOT PAR 0-363 XREFS 3689 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-540 {}} {259 0 0-587 {}}} SUCCS {{259 0 0-589 {}}} CYCLES {}}
+set a(0-589) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#8 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-363 XREFS 3690 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.39783505207082714} PREDS {{146 0 0-540 {}} {258 0 0-586 {}} {259 0 0-588 {}}} SUCCS {{258 0 0-597 {}}} CYCLES {}}
+set a(0-590) {NAME red:slc(red#2.sg1)#6 TYPE READSLICE PAR 0-363 XREFS 3691 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{259 0 0-591 {}}} CYCLES {}}
+set a(0-591) {NAME FRAME:not#3 TYPE NOT PAR 0-363 XREFS 3692 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-540 {}} {259 0 0-590 {}}} SUCCS {{258 0 0-594 {}}} CYCLES {}}
+set a(0-592) {NAME red:slc(red#2.sg1)#7 TYPE READSLICE PAR 0-363 XREFS 3693 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{259 0 0-593 {}}} CYCLES {}}
+set a(0-593) {NAME FRAME:not#25 TYPE NOT PAR 0-363 XREFS 3694 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-540 {}} {259 0 0-592 {}}} SUCCS {{259 0 0-594 {}}} CYCLES {}}
+set a(0-594) {NAME FRAME:conc TYPE CONCATENATE PAR 0-363 XREFS 3695 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-540 {}} {258 0 0-591 {}} {259 0 0-593 {}}} SUCCS {{258 0 0-596 {}}} CYCLES {}}
+set a(0-595) {NAME red:slc(red#2.sg1)#1 TYPE READSLICE PAR 0-363 XREFS 3696 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{259 0 0-596 {}}} CYCLES {}}
+set a(0-596) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#7 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-363 XREFS 3697 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.39783505207082714} PREDS {{146 0 0-540 {}} {258 0 0-594 {}} {259 0 0-595 {}}} SUCCS {{259 0 0-597 {}}} CYCLES {}}
+set a(0-597) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#10 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-363 XREFS 3698 LOC {1 0.6435721999999999 1 0.664885025 1 0.664885025 1 0.7182320451789506 2 0.4511821201789505} PREDS {{146 0 0-540 {}} {258 0 0-589 {}} {259 0 0-596 {}}} SUCCS {{258 0 0-602 {}}} CYCLES {}}
+set a(0-598) {NAME red:slc(red#2.sg1)#2 TYPE READSLICE PAR 0-363 XREFS 3699 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.403626} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{258 0 0-601 {}}} CYCLES {}}
+set a(0-599) {NAME red:slc(red#2.sg1)#3 TYPE READSLICE PAR 0-363 XREFS 3700 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.403626} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{259 0 0-600 {}}} CYCLES {}}
+set a(0-600) {NAME FRAME:not#1 TYPE NOT PAR 0-363 XREFS 3701 LOC {1 0.596016025 1 0.670675925 1 0.670675925 2 0.403626} PREDS {{146 0 0-540 {}} {259 0 0-599 {}}} SUCCS {{259 0 0-601 {}}} CYCLES {}}
+set a(0-601) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#9 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-363 XREFS 3702 LOC {1 0.596016025 1 0.670675925 1 0.670675925 1 0.7182320520708271 2 0.45118212707082717} PREDS {{146 0 0-540 {}} {258 0 0-598 {}} {259 0 0-600 {}}} SUCCS {{259 0 0-602 {}}} CYCLES {}}
+set a(0-602) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,4,0,6) AREA_SCORE 6.29 QUANTITY 3 NAME FRAME:acc#11 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3703 LOC {1 0.696919275 1 0.7182320999999999 1 0.7182320999999999 1 0.7769849308637015 2 0.5099350058637016} PREDS {{146 0 0-540 {}} {258 0 0-597 {}} {259 0 0-601 {}}} SUCCS {{259 0 0-603 {}}} CYCLES {}}
+set a(0-603) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-363 XREFS 3704 LOC {1 0.75567215 1 0.776984975 1 0.776984975 1 0.8404969484103024 2 0.5734470234103024} PREDS {{146 0 0-540 {}} {259 0 0-602 {}}} SUCCS {{258 0 0-725 {}} {258 0 0-727 {}} {258 0 0-729 {}} {258 0 0-731 {}} {258 0 0-739 {}} {258 0 0-744 {}}} CYCLES {}}
+set a(0-604) {NAME green:slc(green#2.sg1)#4 TYPE READSLICE PAR 0-363 XREFS 3705 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{258 0 0-607 {}}} CYCLES {}}
+set a(0-605) {NAME green:slc(green#2.sg1)#5 TYPE READSLICE PAR 0-363 XREFS 3706 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{259 0 0-606 {}}} CYCLES {}}
+set a(0-606) {NAME FRAME:not#10 TYPE NOT PAR 0-363 XREFS 3707 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {259 0 0-605 {}}} SUCCS {{259 0 0-607 {}}} CYCLES {}}
+set a(0-607) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#13 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-363 XREFS 3708 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.32420875207082717} PREDS {{146 0 0-540 {}} {258 0 0-604 {}} {259 0 0-606 {}}} SUCCS {{258 0 0-615 {}}} CYCLES {}}
+set a(0-608) {NAME green:slc(green#2.sg1)#6 TYPE READSLICE PAR 0-363 XREFS 3709 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{259 0 0-609 {}}} CYCLES {}}
+set a(0-609) {NAME FRAME:not#11 TYPE NOT PAR 0-363 XREFS 3710 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {259 0 0-608 {}}} SUCCS {{258 0 0-612 {}}} CYCLES {}}
+set a(0-610) {NAME green:slc(green#2.sg1)#7 TYPE READSLICE PAR 0-363 XREFS 3711 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{259 0 0-611 {}}} CYCLES {}}
+set a(0-611) {NAME FRAME:not#26 TYPE NOT PAR 0-363 XREFS 3712 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {259 0 0-610 {}}} SUCCS {{259 0 0-612 {}}} CYCLES {}}
+set a(0-612) {NAME FRAME:conc#16 TYPE CONCATENATE PAR 0-363 XREFS 3713 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {258 0 0-609 {}} {259 0 0-611 {}}} SUCCS {{258 0 0-614 {}}} CYCLES {}}
+set a(0-613) {NAME green:slc(green#2.sg1)#1 TYPE READSLICE PAR 0-363 XREFS 3714 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{259 0 0-614 {}}} CYCLES {}}
+set a(0-614) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#12 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-363 XREFS 3715 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.32420875207082717} PREDS {{146 0 0-540 {}} {258 0 0-612 {}} {259 0 0-613 {}}} SUCCS {{259 0 0-615 {}}} CYCLES {}}
+set a(0-615) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#15 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-363 XREFS 3716 LOC {1 0.6435721999999999 1 0.664885025 1 0.664885025 1 0.7182320451789506 2 0.37755582017895045} PREDS {{146 0 0-540 {}} {258 0 0-607 {}} {259 0 0-614 {}}} SUCCS {{258 0 0-620 {}}} CYCLES {}}
+set a(0-616) {NAME green:slc(green#2.sg1)#2 TYPE READSLICE PAR 0-363 XREFS 3717 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.3299997} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{258 0 0-619 {}}} CYCLES {}}
+set a(0-617) {NAME green:slc(green#2.sg1)#3 TYPE READSLICE PAR 0-363 XREFS 3718 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.3299997} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{259 0 0-618 {}}} CYCLES {}}
+set a(0-618) {NAME FRAME:not#9 TYPE NOT PAR 0-363 XREFS 3719 LOC {1 0.596016025 1 0.670675925 1 0.670675925 2 0.3299997} PREDS {{146 0 0-540 {}} {259 0 0-617 {}}} SUCCS {{259 0 0-619 {}}} CYCLES {}}
+set a(0-619) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#14 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-363 XREFS 3720 LOC {1 0.596016025 1 0.670675925 1 0.670675925 1 0.7182320520708271 2 0.3775558270708272} PREDS {{146 0 0-540 {}} {258 0 0-616 {}} {259 0 0-618 {}}} SUCCS {{259 0 0-620 {}}} CYCLES {}}
+set a(0-620) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,4,0,6) AREA_SCORE 6.29 QUANTITY 3 NAME FRAME:acc#16 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3721 LOC {1 0.696919275 1 0.7182320999999999 1 0.7182320999999999 1 0.7769849308637015 2 0.4363087058637015} PREDS {{146 0 0-540 {}} {258 0 0-615 {}} {259 0 0-619 {}}} SUCCS {{259 0 0-621 {}}} CYCLES {}}
+set a(0-621) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc#2 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-363 XREFS 3722 LOC {1 0.75567215 1 0.776984975 1 0.776984975 1 0.8404969484103024 2 0.49982072341030237} PREDS {{146 0 0-540 {}} {259 0 0-620 {}}} SUCCS {{258 0 0-627 {}} {258 0 0-629 {}} {258 0 0-631 {}} {258 0 0-633 {}} {258 0 0-641 {}} {258 0 0-646 {}}} CYCLES {}}
+set a(0-622) {NAME green:slc(green#2.sg1)#9 TYPE READSLICE PAR 0-363 XREFS 3723 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.6380319249999999} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{259 0 0-623 {}}} CYCLES {}}
+set a(0-623) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#2 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-363 XREFS 3724 LOC {1 0.596016025 1 0.809739975 1 0.809739975 1 0.9999999562499999 2 0.8282919062499999} PREDS {{146 0 0-540 {}} {259 0 0-622 {}}} SUCCS {{258 0 0-651 {}}} CYCLES {}}
+set a(0-624) {NAME green:slc(green#2.sg1)#11 TYPE READSLICE PAR 0-363 XREFS 3725 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.5833817} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{259 0 0-625 {}}} CYCLES {}}
+set a(0-625) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#3 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-363 XREFS 3726 LOC {1 0.596016025 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.7612634921744312} PREDS {{146 0 0-540 {}} {259 0 0-624 {}}} SUCCS {{258 0 0-650 {}}} CYCLES {}}
+set a(0-626) {NAME green:slc(green#2.sg1) TYPE READSLICE PAR 0-363 XREFS 3727 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.717923525} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{258 0 0-649 {}}} CYCLES {}}
+set a(0-627) {NAME FRAME:slc(acc.imod#2)#6 TYPE READSLICE PAR 0-363 XREFS 3728 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.558420525} PREDS {{146 0 0-540 {}} {258 0 0-621 {}}} SUCCS {{259 0 0-628 {}}} CYCLES {}}
+set a(0-628) {NAME FRAME:not#15 TYPE NOT PAR 0-363 XREFS 3729 LOC {1 0.819184175 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-540 {}} {259 0 0-627 {}}} SUCCS {{258 0 0-640 {}}} CYCLES {}}
+set a(0-629) {NAME FRAME:slc(acc.imod#2)#1 TYPE READSLICE PAR 0-363 XREFS 3730 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {258 0 0-621 {}}} SUCCS {{259 0 0-630 {}}} CYCLES {}}
+set a(0-630) {NAME FRAME:conc#24 TYPE CONCATENATE PAR 0-363 XREFS 3731 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {259 0 0-629 {}}} SUCCS {{258 0 0-636 {}}} CYCLES {}}
+set a(0-631) {NAME FRAME:slc(acc.imod#2)#2 TYPE READSLICE PAR 0-363 XREFS 3732 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {258 0 0-621 {}}} SUCCS {{259 0 0-632 {}}} CYCLES {}}
+set a(0-632) {NAME FRAME:not#13 TYPE NOT PAR 0-363 XREFS 3733 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {259 0 0-631 {}}} SUCCS {{258 0 0-635 {}}} CYCLES {}}
+set a(0-633) {NAME FRAME:slc(acc.imod#2) TYPE READSLICE PAR 0-363 XREFS 3734 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {258 0 0-621 {}}} SUCCS {{259 0 0-634 {}}} CYCLES {}}
+set a(0-634) {NAME FRAME:not#12 TYPE NOT PAR 0-363 XREFS 3735 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {259 0 0-633 {}}} SUCCS {{259 0 0-635 {}}} CYCLES {}}
+set a(0-635) {NAME FRAME:conc#25 TYPE CONCATENATE PAR 0-363 XREFS 3736 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {258 0 0-632 {}} {259 0 0-634 {}}} SUCCS {{259 0 0-636 {}}} CYCLES {}}
+set a(0-636) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#23 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3737 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 1 0.899096709496936 2 0.558420484496936} PREDS {{146 0 0-540 {}} {258 0 0-630 {}} {259 0 0-635 {}}} SUCCS {{259 0 0-637 {}}} CYCLES {}}
+set a(0-637) {NAME FRAME:slc#5 TYPE READSLICE PAR 0-363 XREFS 3738 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-540 {}} {259 0 0-636 {}}} SUCCS {{259 0 0-638 {}}} CYCLES {}}
+set a(0-638) {NAME FRAME:slc#3 TYPE READSLICE PAR 0-363 XREFS 3739 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-540 {}} {259 0 0-637 {}}} SUCCS {{259 0 0-639 {}}} CYCLES {}}
+set a(0-639) {NAME FRAME:not#16 TYPE NOT PAR 0-363 XREFS 3740 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-540 {}} {259 0 0-638 {}}} SUCCS {{259 0 0-640 {}}} CYCLES {}}
+set a(0-640) {NAME FRAME:conc#7 TYPE CONCATENATE PAR 0-363 XREFS 3741 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-540 {}} {258 0 0-628 {}} {259 0 0-639 {}}} SUCCS {{258 0 0-642 {}}} CYCLES {}}
+set a(0-641) {NAME FRAME:slc(acc.imod#2)#5 TYPE READSLICE PAR 0-363 XREFS 3742 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.558420525} PREDS {{146 0 0-540 {}} {258 0 0-621 {}}} SUCCS {{259 0 0-642 {}}} CYCLES {}}
+set a(0-642) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#17 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-363 XREFS 3743 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 1 0.9466528770708271 2 0.6059766520708271} PREDS {{146 0 0-540 {}} {258 0 0-640 {}} {259 0 0-641 {}}} SUCCS {{258 0 0-645 {}}} CYCLES {}}
+set a(0-643) {NAME green:slc(green#2.sg1)#10 TYPE READSLICE PAR 0-363 XREFS 3744 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.6059766999999999} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{259 0 0-644 {}}} CYCLES {}}
+set a(0-644) {NAME FRAME:not#14 TYPE NOT PAR 0-363 XREFS 3745 LOC {1 0.596016025 1 0.946652925 1 0.946652925 2 0.6059766999999999} PREDS {{146 0 0-540 {}} {259 0 0-643 {}}} SUCCS {{259 0 0-645 {}}} CYCLES {}}
+set a(0-645) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#18 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-363 XREFS 3746 LOC {1 0.9253401 1 0.946652925 1 0.946652925 1 0.9999999451789505 2 0.6593237201789504} PREDS {{146 0 0-540 {}} {258 0 0-642 {}} {259 0 0-644 {}}} SUCCS {{258 0 0-648 {}}} CYCLES {}}
+set a(0-646) {NAME FRAME:slc(acc.imod#2)#4 TYPE READSLICE PAR 0-363 XREFS 3747 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.659323775} PREDS {{146 0 0-540 {}} {258 0 0-621 {}}} SUCCS {{259 0 0-647 {}}} CYCLES {}}
+set a(0-647) {NAME FRAME:conc#22 TYPE CONCATENATE PAR 0-363 XREFS 3748 LOC {1 0.819184175 2 0.659323775 2 0.659323775 2 0.659323775} PREDS {{146 0 0-540 {}} {259 0 0-646 {}}} SUCCS {{259 0 0-648 {}}} CYCLES {}}
+set a(0-648) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#19 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3749 LOC {2 0.0 2 0.659323775 2 0.659323775 2 0.717923484496936 2 0.717923484496936} PREDS {{146 0 0-540 {}} {258 0 0-645 {}} {259 0 0-647 {}}} SUCCS {{259 0 0-649 {}}} CYCLES {}}
+set a(0-649) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#20 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-363 XREFS 3750 LOC {2 0.05859975 2 0.717923525 2 0.717923525 2 0.7612634907468815 2 0.7612634907468815} PREDS {{146 0 0-540 {}} {258 0 0-626 {}} {259 0 0-648 {}}} SUCCS {{259 0 0-650 {}}} CYCLES {}}
+set a(0-650) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#21 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-363 XREFS 3751 LOC {2 0.101939775 2 0.76126355 2 0.76126355 2 0.82829190686502 2 0.82829190686502} PREDS {{146 0 0-540 {}} {258 0 0-625 {}} {259 0 0-649 {}}} SUCCS {{259 0 0-651 {}}} CYCLES {}}
+set a(0-651) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,10,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME FRAME:acc#22 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-363 XREFS 3752 LOC {2 0.168968175 2 0.82829195 2 0.82829195 2 0.9037692343138832 2 0.9037692343138832} PREDS {{146 0 0-540 {}} {258 0 0-623 {}} {259 0 0-650 {}}} SUCCS {{258 0 0-658 {}}} CYCLES {}}
+set a(0-652) {NAME green:slc(green#2.sg1)#12 TYPE READSLICE PAR 0-363 XREFS 3753 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.9037692749999999} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{258 0 0-656 {}}} CYCLES {}}
+set a(0-653) {NAME green:slc(green#2.sg1)#13 TYPE READSLICE PAR 0-363 XREFS 3754 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.9037692749999999} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{259 0 0-654 {}}} CYCLES {}}
+set a(0-654) {NAME FRAME:exs#3 TYPE SIGNEXTEND PAR 0-363 XREFS 3755 LOC {1 0.596016025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-540 {}} {259 0 0-653 {}}} SUCCS {{258 0 0-656 {}}} CYCLES {}}
+set a(0-655) {NAME green:slc(green#2.sg1)#8 TYPE READSLICE PAR 0-363 XREFS 3756 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.9037692749999999} PREDS {{146 0 0-540 {}} {258 0 0-570 {}}} SUCCS {{259 0 0-656 {}}} CYCLES {}}
+set a(0-656) {NAME FRAME:conc#6 TYPE CONCATENATE PAR 0-363 XREFS 3757 LOC {1 0.596016025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-540 {}} {258 0 0-654 {}} {258 0 0-652 {}} {259 0 0-655 {}}} SUCCS {{259 0 0-657 {}}} CYCLES {}}
+set a(0-657) {NAME FRAME:exs#2 TYPE SIGNEXTEND PAR 0-363 XREFS 3758 LOC {1 0.596016025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-540 {}} {259 0 0-656 {}}} SUCCS {{259 0 0-658 {}}} CYCLES {}}
+set a(0-658) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME FRAME:acc#3 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-363 XREFS 3759 LOC {2 0.24444549999999998 2 0.9037692749999999 2 0.9037692749999999 2 0.9832574784997776 2 0.9832574784997776} PREDS {{146 0 0-540 {}} {258 0 0-651 {}} {259 0 0-657 {}}} SUCCS {{258 0 0-750 {}} {258 0 0-753 {}} {258 0 0-754 {}}} CYCLES {}}
+set a(0-659) {NAME blue:slc(blue#2.sg1)#4 TYPE READSLICE PAR 0-363 XREFS 3760 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{258 0 0-662 {}}} CYCLES {}}
+set a(0-660) {NAME blue:slc(blue#2.sg1)#5 TYPE READSLICE PAR 0-363 XREFS 3761 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{259 0 0-661 {}}} CYCLES {}}
+set a(0-661) {NAME FRAME:not#18 TYPE NOT PAR 0-363 XREFS 3762 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {259 0 0-660 {}}} SUCCS {{259 0 0-662 {}}} CYCLES {}}
+set a(0-662) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#25 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-363 XREFS 3763 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.32420875207082717} PREDS {{146 0 0-540 {}} {258 0 0-659 {}} {259 0 0-661 {}}} SUCCS {{258 0 0-670 {}}} CYCLES {}}
+set a(0-663) {NAME blue:slc(blue#2.sg1)#6 TYPE READSLICE PAR 0-363 XREFS 3764 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{259 0 0-664 {}}} CYCLES {}}
+set a(0-664) {NAME FRAME:not#19 TYPE NOT PAR 0-363 XREFS 3765 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {259 0 0-663 {}}} SUCCS {{258 0 0-667 {}}} CYCLES {}}
+set a(0-665) {NAME blue:slc(blue#2.sg1)#7 TYPE READSLICE PAR 0-363 XREFS 3766 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{259 0 0-666 {}}} CYCLES {}}
+set a(0-666) {NAME FRAME:not#27 TYPE NOT PAR 0-363 XREFS 3767 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {259 0 0-665 {}}} SUCCS {{259 0 0-667 {}}} CYCLES {}}
+set a(0-667) {NAME FRAME:conc#17 TYPE CONCATENATE PAR 0-363 XREFS 3768 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {258 0 0-664 {}} {259 0 0-666 {}}} SUCCS {{258 0 0-669 {}}} CYCLES {}}
+set a(0-668) {NAME blue:slc(blue#2.sg1)#1 TYPE READSLICE PAR 0-363 XREFS 3769 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{259 0 0-669 {}}} CYCLES {}}
+set a(0-669) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#24 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-363 XREFS 3770 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.32420875207082717} PREDS {{146 0 0-540 {}} {258 0 0-667 {}} {259 0 0-668 {}}} SUCCS {{259 0 0-670 {}}} CYCLES {}}
+set a(0-670) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#27 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-363 XREFS 3771 LOC {1 0.6435721999999999 1 0.664885025 1 0.664885025 1 0.7182320451789506 2 0.37755582017895045} PREDS {{146 0 0-540 {}} {258 0 0-662 {}} {259 0 0-669 {}}} SUCCS {{258 0 0-675 {}}} CYCLES {}}
+set a(0-671) {NAME blue:slc(blue#2.sg1)#2 TYPE READSLICE PAR 0-363 XREFS 3772 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.3299997} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{258 0 0-674 {}}} CYCLES {}}
+set a(0-672) {NAME blue:slc(blue#2.sg1)#3 TYPE READSLICE PAR 0-363 XREFS 3773 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.3299997} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{259 0 0-673 {}}} CYCLES {}}
+set a(0-673) {NAME FRAME:not#17 TYPE NOT PAR 0-363 XREFS 3774 LOC {1 0.596016025 1 0.670675925 1 0.670675925 2 0.3299997} PREDS {{146 0 0-540 {}} {259 0 0-672 {}}} SUCCS {{259 0 0-674 {}}} CYCLES {}}
+set a(0-674) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#26 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-363 XREFS 3775 LOC {1 0.596016025 1 0.670675925 1 0.670675925 1 0.7182320520708271 2 0.3775558270708272} PREDS {{146 0 0-540 {}} {258 0 0-671 {}} {259 0 0-673 {}}} SUCCS {{259 0 0-675 {}}} CYCLES {}}
+set a(0-675) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,4,0,6) AREA_SCORE 6.29 QUANTITY 3 NAME FRAME:acc#28 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3776 LOC {1 0.696919275 1 0.7182320999999999 1 0.7182320999999999 1 0.7769849308637015 2 0.4363087058637015} PREDS {{146 0 0-540 {}} {258 0 0-670 {}} {259 0 0-674 {}}} SUCCS {{259 0 0-676 {}}} CYCLES {}}
+set a(0-676) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc#4 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-363 XREFS 3777 LOC {1 0.75567215 1 0.776984975 1 0.776984975 1 0.8404969484103024 2 0.49982072341030237} PREDS {{146 0 0-540 {}} {259 0 0-675 {}}} SUCCS {{258 0 0-682 {}} {258 0 0-684 {}} {258 0 0-686 {}} {258 0 0-688 {}} {258 0 0-696 {}} {258 0 0-701 {}}} CYCLES {}}
+set a(0-677) {NAME blue:slc(blue#2.sg1)#9 TYPE READSLICE PAR 0-363 XREFS 3778 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.6380319249999999} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{259 0 0-678 {}}} CYCLES {}}
+set a(0-678) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#4 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-363 XREFS 3779 LOC {1 0.596016025 1 0.809739975 1 0.809739975 1 0.9999999562499999 2 0.8282919062499999} PREDS {{146 0 0-540 {}} {259 0 0-677 {}}} SUCCS {{258 0 0-706 {}}} CYCLES {}}
+set a(0-679) {NAME blue:slc(blue#2.sg1)#11 TYPE READSLICE PAR 0-363 XREFS 3780 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.5833817} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{259 0 0-680 {}}} CYCLES {}}
+set a(0-680) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#5 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-363 XREFS 3781 LOC {1 0.596016025 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.7612634921744312} PREDS {{146 0 0-540 {}} {259 0 0-679 {}}} SUCCS {{258 0 0-705 {}}} CYCLES {}}
+set a(0-681) {NAME blue:slc(blue#2.sg1) TYPE READSLICE PAR 0-363 XREFS 3782 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.717923525} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{258 0 0-704 {}}} CYCLES {}}
+set a(0-682) {NAME FRAME:slc(acc.imod#4)#6 TYPE READSLICE PAR 0-363 XREFS 3783 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.558420525} PREDS {{146 0 0-540 {}} {258 0 0-676 {}}} SUCCS {{259 0 0-683 {}}} CYCLES {}}
+set a(0-683) {NAME FRAME:not#23 TYPE NOT PAR 0-363 XREFS 3784 LOC {1 0.819184175 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-540 {}} {259 0 0-682 {}}} SUCCS {{258 0 0-695 {}}} CYCLES {}}
+set a(0-684) {NAME FRAME:slc(acc.imod#4)#1 TYPE READSLICE PAR 0-363 XREFS 3785 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {258 0 0-676 {}}} SUCCS {{259 0 0-685 {}}} CYCLES {}}
+set a(0-685) {NAME FRAME:conc#28 TYPE CONCATENATE PAR 0-363 XREFS 3786 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {259 0 0-684 {}}} SUCCS {{258 0 0-691 {}}} CYCLES {}}
+set a(0-686) {NAME FRAME:slc(acc.imod#4)#2 TYPE READSLICE PAR 0-363 XREFS 3787 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {258 0 0-676 {}}} SUCCS {{259 0 0-687 {}}} CYCLES {}}
+set a(0-687) {NAME FRAME:not#21 TYPE NOT PAR 0-363 XREFS 3788 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {259 0 0-686 {}}} SUCCS {{258 0 0-690 {}}} CYCLES {}}
+set a(0-688) {NAME FRAME:slc(acc.imod#4) TYPE READSLICE PAR 0-363 XREFS 3789 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {258 0 0-676 {}}} SUCCS {{259 0 0-689 {}}} CYCLES {}}
+set a(0-689) {NAME FRAME:not#20 TYPE NOT PAR 0-363 XREFS 3790 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {259 0 0-688 {}}} SUCCS {{259 0 0-690 {}}} CYCLES {}}
+set a(0-690) {NAME FRAME:conc#29 TYPE CONCATENATE PAR 0-363 XREFS 3791 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-540 {}} {258 0 0-687 {}} {259 0 0-689 {}}} SUCCS {{259 0 0-691 {}}} CYCLES {}}
+set a(0-691) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#35 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3792 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 1 0.899096709496936 2 0.558420484496936} PREDS {{146 0 0-540 {}} {258 0 0-685 {}} {259 0 0-690 {}}} SUCCS {{259 0 0-692 {}}} CYCLES {}}
+set a(0-692) {NAME FRAME:slc#6 TYPE READSLICE PAR 0-363 XREFS 3793 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-540 {}} {259 0 0-691 {}}} SUCCS {{259 0 0-693 {}}} CYCLES {}}
+set a(0-693) {NAME FRAME:slc#4 TYPE READSLICE PAR 0-363 XREFS 3794 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-540 {}} {259 0 0-692 {}}} SUCCS {{259 0 0-694 {}}} CYCLES {}}
+set a(0-694) {NAME FRAME:not#24 TYPE NOT PAR 0-363 XREFS 3795 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-540 {}} {259 0 0-693 {}}} SUCCS {{259 0 0-695 {}}} CYCLES {}}
+set a(0-695) {NAME FRAME:conc#11 TYPE CONCATENATE PAR 0-363 XREFS 3796 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-540 {}} {258 0 0-683 {}} {259 0 0-694 {}}} SUCCS {{258 0 0-697 {}}} CYCLES {}}
+set a(0-696) {NAME FRAME:slc(acc.imod#4)#5 TYPE READSLICE PAR 0-363 XREFS 3797 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.558420525} PREDS {{146 0 0-540 {}} {258 0 0-676 {}}} SUCCS {{259 0 0-697 {}}} CYCLES {}}
+set a(0-697) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#29 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-363 XREFS 3798 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 1 0.9466528770708271 2 0.6059766520708271} PREDS {{146 0 0-540 {}} {258 0 0-695 {}} {259 0 0-696 {}}} SUCCS {{258 0 0-700 {}}} CYCLES {}}
+set a(0-698) {NAME blue:slc(blue#2.sg1)#10 TYPE READSLICE PAR 0-363 XREFS 3799 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.6059766999999999} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{259 0 0-699 {}}} CYCLES {}}
+set a(0-699) {NAME FRAME:not#22 TYPE NOT PAR 0-363 XREFS 3800 LOC {1 0.596016025 1 0.946652925 1 0.946652925 2 0.6059766999999999} PREDS {{146 0 0-540 {}} {259 0 0-698 {}}} SUCCS {{259 0 0-700 {}}} CYCLES {}}
+set a(0-700) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#30 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-363 XREFS 3801 LOC {1 0.9253401 1 0.946652925 1 0.946652925 1 0.9999999451789505 2 0.6593237201789504} PREDS {{146 0 0-540 {}} {258 0 0-697 {}} {259 0 0-699 {}}} SUCCS {{258 0 0-703 {}}} CYCLES {}}
+set a(0-701) {NAME FRAME:slc(acc.imod#4)#4 TYPE READSLICE PAR 0-363 XREFS 3802 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.659323775} PREDS {{146 0 0-540 {}} {258 0 0-676 {}}} SUCCS {{259 0 0-702 {}}} CYCLES {}}
+set a(0-702) {NAME FRAME:conc#26 TYPE CONCATENATE PAR 0-363 XREFS 3803 LOC {1 0.819184175 2 0.659323775 2 0.659323775 2 0.659323775} PREDS {{146 0 0-540 {}} {259 0 0-701 {}}} SUCCS {{259 0 0-703 {}}} CYCLES {}}
+set a(0-703) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#31 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3804 LOC {2 0.0 2 0.659323775 2 0.659323775 2 0.717923484496936 2 0.717923484496936} PREDS {{146 0 0-540 {}} {258 0 0-700 {}} {259 0 0-702 {}}} SUCCS {{259 0 0-704 {}}} CYCLES {}}
+set a(0-704) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#32 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-363 XREFS 3805 LOC {2 0.05859975 2 0.717923525 2 0.717923525 2 0.7612634907468815 2 0.7612634907468815} PREDS {{146 0 0-540 {}} {258 0 0-681 {}} {259 0 0-703 {}}} SUCCS {{259 0 0-705 {}}} CYCLES {}}
+set a(0-705) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#33 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-363 XREFS 3806 LOC {2 0.101939775 2 0.76126355 2 0.76126355 2 0.82829190686502 2 0.82829190686502} PREDS {{146 0 0-540 {}} {258 0 0-680 {}} {259 0 0-704 {}}} SUCCS {{259 0 0-706 {}}} CYCLES {}}
+set a(0-706) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,10,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME FRAME:acc#34 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-363 XREFS 3807 LOC {2 0.168968175 2 0.82829195 2 0.82829195 2 0.9037692343138832 2 0.9037692343138832} PREDS {{146 0 0-540 {}} {258 0 0-678 {}} {259 0 0-705 {}}} SUCCS {{258 0 0-713 {}}} CYCLES {}}
+set a(0-707) {NAME blue:slc(blue#2.sg1)#12 TYPE READSLICE PAR 0-363 XREFS 3808 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.9037692749999999} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{258 0 0-711 {}}} CYCLES {}}
+set a(0-708) {NAME blue:slc(blue#2.sg1)#13 TYPE READSLICE PAR 0-363 XREFS 3809 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.9037692749999999} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{259 0 0-709 {}}} CYCLES {}}
+set a(0-709) {NAME FRAME:exs#5 TYPE SIGNEXTEND PAR 0-363 XREFS 3810 LOC {1 0.596016025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-540 {}} {259 0 0-708 {}}} SUCCS {{258 0 0-711 {}}} CYCLES {}}
+set a(0-710) {NAME blue:slc(blue#2.sg1)#8 TYPE READSLICE PAR 0-363 XREFS 3811 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.9037692749999999} PREDS {{146 0 0-540 {}} {258 0 0-585 {}}} SUCCS {{259 0 0-711 {}}} CYCLES {}}
+set a(0-711) {NAME FRAME:conc#10 TYPE CONCATENATE PAR 0-363 XREFS 3812 LOC {1 0.596016025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-540 {}} {258 0 0-709 {}} {258 0 0-707 {}} {259 0 0-710 {}}} SUCCS {{259 0 0-712 {}}} CYCLES {}}
+set a(0-712) {NAME FRAME:exs#4 TYPE SIGNEXTEND PAR 0-363 XREFS 3813 LOC {1 0.596016025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-540 {}} {259 0 0-711 {}}} SUCCS {{259 0 0-713 {}}} CYCLES {}}
+set a(0-713) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME FRAME:acc#4 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-363 XREFS 3814 LOC {2 0.24444549999999998 2 0.9037692749999999 2 0.9037692749999999 2 0.9832574784997776 2 0.9832574784997776} PREDS {{146 0 0-540 {}} {258 0 0-706 {}} {259 0 0-712 {}}} SUCCS {{258 0 0-755 {}} {258 0 0-758 {}}} CYCLES {}}
+set a(0-714) {NAME red:slc(red#2.sg1)#13 TYPE READSLICE PAR 0-363 XREFS 3815 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.63020875} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{259 0 0-715 {}}} CYCLES {}}
+set a(0-715) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-363 XREFS 3816 LOC {1 0.596016025 1 0.7282905 1 0.7282905 1 0.9185504812499999 2 0.82046873125} PREDS {{146 0 0-540 {}} {259 0 0-714 {}}} SUCCS {{258 0 0-721 {}}} CYCLES {}}
+set a(0-716) {NAME red:slc(red#2.sg1)#11 TYPE READSLICE PAR 0-363 XREFS 3817 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.8204687749999999} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{258 0 0-720 {}}} CYCLES {}}
+set a(0-717) {NAME red:slc(red#2.sg1)#12 TYPE READSLICE PAR 0-363 XREFS 3818 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.8204687749999999} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{259 0 0-718 {}}} CYCLES {}}
+set a(0-718) {NAME FRAME:exs#1 TYPE SIGNEXTEND PAR 0-363 XREFS 3819 LOC {1 0.596016025 1 0.918550525 1 0.918550525 2 0.8204687749999999} PREDS {{146 0 0-540 {}} {259 0 0-717 {}}} SUCCS {{258 0 0-720 {}}} CYCLES {}}
+set a(0-719) {NAME red:slc(red#2.sg1)#8 TYPE READSLICE PAR 0-363 XREFS 3820 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.8204687749999999} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{259 0 0-720 {}}} CYCLES {}}
+set a(0-720) {NAME FRAME:conc#2 TYPE CONCATENATE PAR 0-363 XREFS 3821 LOC {1 0.596016025 1 0.918550525 1 0.918550525 2 0.8204687749999999} PREDS {{146 0 0-540 {}} {258 0 0-718 {}} {258 0 0-716 {}} {259 0 0-719 {}}} SUCCS {{259 0 0-721 {}}} CYCLES {}}
+set a(0-721) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,9,1,10) AREA_SCORE 11.00 QUANTITY 1 NAME FRAME:acc#41 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-363 XREFS 3822 LOC {1 0.78627605 1 0.918550525 1 0.918550525 1 0.9999999444798112 2 0.9019181944798111} PREDS {{146 0 0-540 {}} {258 0 0-715 {}} {259 0 0-720 {}}} SUCCS {{258 0 0-749 {}}} CYCLES {}}
+set a(0-722) {NAME red:slc(red#2.sg1)#10 TYPE READSLICE PAR 0-363 XREFS 3823 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.6570079999999999} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{259 0 0-723 {}}} CYCLES {}}
+set a(0-723) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#1 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-363 XREFS 3824 LOC {1 0.596016025 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.8348897921744312} PREDS {{146 0 0-540 {}} {259 0 0-722 {}}} SUCCS {{258 0 0-748 {}}} CYCLES {}}
+set a(0-724) {NAME red:slc(red#2.sg1) TYPE READSLICE PAR 0-363 XREFS 3825 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.7915498249999999} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{258 0 0-747 {}}} CYCLES {}}
+set a(0-725) {NAME FRAME:slc(acc.imod)#6 TYPE READSLICE PAR 0-363 XREFS 3826 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.632046825} PREDS {{146 0 0-540 {}} {258 0 0-603 {}}} SUCCS {{259 0 0-726 {}}} CYCLES {}}
+set a(0-726) {NAME FRAME:not#7 TYPE NOT PAR 0-363 XREFS 3827 LOC {1 0.819184175 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-540 {}} {259 0 0-725 {}}} SUCCS {{258 0 0-738 {}}} CYCLES {}}
+set a(0-727) {NAME FRAME:slc(acc.imod)#1 TYPE READSLICE PAR 0-363 XREFS 3828 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-540 {}} {258 0 0-603 {}}} SUCCS {{259 0 0-728 {}}} CYCLES {}}
+set a(0-728) {NAME FRAME:conc#32 TYPE CONCATENATE PAR 0-363 XREFS 3829 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-540 {}} {259 0 0-727 {}}} SUCCS {{258 0 0-734 {}}} CYCLES {}}
+set a(0-729) {NAME FRAME:slc(acc.imod)#2 TYPE READSLICE PAR 0-363 XREFS 3830 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-540 {}} {258 0 0-603 {}}} SUCCS {{259 0 0-730 {}}} CYCLES {}}
+set a(0-730) {NAME FRAME:not#5 TYPE NOT PAR 0-363 XREFS 3831 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-540 {}} {259 0 0-729 {}}} SUCCS {{258 0 0-733 {}}} CYCLES {}}
+set a(0-731) {NAME FRAME:slc(acc.imod) TYPE READSLICE PAR 0-363 XREFS 3832 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-540 {}} {258 0 0-603 {}}} SUCCS {{259 0 0-732 {}}} CYCLES {}}
+set a(0-732) {NAME FRAME:not#4 TYPE NOT PAR 0-363 XREFS 3833 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-540 {}} {259 0 0-731 {}}} SUCCS {{259 0 0-733 {}}} CYCLES {}}
+set a(0-733) {NAME FRAME:conc#33 TYPE CONCATENATE PAR 0-363 XREFS 3834 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-540 {}} {258 0 0-730 {}} {259 0 0-732 {}}} SUCCS {{259 0 0-734 {}}} CYCLES {}}
+set a(0-734) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#42 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3835 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 1 0.899096709496936 2 0.6320467844969361} PREDS {{146 0 0-540 {}} {258 0 0-728 {}} {259 0 0-733 {}}} SUCCS {{259 0 0-735 {}}} CYCLES {}}
+set a(0-735) {NAME FRAME:slc#7 TYPE READSLICE PAR 0-363 XREFS 3836 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-540 {}} {259 0 0-734 {}}} SUCCS {{259 0 0-736 {}}} CYCLES {}}
+set a(0-736) {NAME FRAME:slc#2 TYPE READSLICE PAR 0-363 XREFS 3837 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-540 {}} {259 0 0-735 {}}} SUCCS {{259 0 0-737 {}}} CYCLES {}}
+set a(0-737) {NAME FRAME:not#8 TYPE NOT PAR 0-363 XREFS 3838 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-540 {}} {259 0 0-736 {}}} SUCCS {{259 0 0-738 {}}} CYCLES {}}
+set a(0-738) {NAME FRAME:conc#3 TYPE CONCATENATE PAR 0-363 XREFS 3839 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-540 {}} {258 0 0-726 {}} {259 0 0-737 {}}} SUCCS {{258 0 0-740 {}}} CYCLES {}}
+set a(0-739) {NAME FRAME:slc(acc.imod)#5 TYPE READSLICE PAR 0-363 XREFS 3840 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.632046825} PREDS {{146 0 0-540 {}} {258 0 0-603 {}}} SUCCS {{259 0 0-740 {}}} CYCLES {}}
+set a(0-740) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#36 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-363 XREFS 3841 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 1 0.9466528770708271 2 0.6796029520708271} PREDS {{146 0 0-540 {}} {258 0 0-738 {}} {259 0 0-739 {}}} SUCCS {{258 0 0-743 {}}} CYCLES {}}
+set a(0-741) {NAME red:slc(red#2.sg1)#9 TYPE READSLICE PAR 0-363 XREFS 3842 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.679603} PREDS {{146 0 0-540 {}} {258 0 0-555 {}}} SUCCS {{259 0 0-742 {}}} CYCLES {}}
+set a(0-742) {NAME FRAME:not#6 TYPE NOT PAR 0-363 XREFS 3843 LOC {1 0.596016025 1 0.946652925 1 0.946652925 2 0.679603} PREDS {{146 0 0-540 {}} {259 0 0-741 {}}} SUCCS {{259 0 0-743 {}}} CYCLES {}}
+set a(0-743) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#37 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-363 XREFS 3844 LOC {1 0.9253401 1 0.946652925 1 0.946652925 1 0.9999999451789505 2 0.7329500201789505} PREDS {{146 0 0-540 {}} {258 0 0-740 {}} {259 0 0-742 {}}} SUCCS {{258 0 0-746 {}}} CYCLES {}}
+set a(0-744) {NAME FRAME:slc(acc.imod)#4 TYPE READSLICE PAR 0-363 XREFS 3845 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.732950075} PREDS {{146 0 0-540 {}} {258 0 0-603 {}}} SUCCS {{259 0 0-745 {}}} CYCLES {}}
+set a(0-745) {NAME FRAME:conc#30 TYPE CONCATENATE PAR 0-363 XREFS 3846 LOC {1 0.819184175 2 0.732950075 2 0.732950075 2 0.732950075} PREDS {{146 0 0-540 {}} {259 0 0-744 {}}} SUCCS {{259 0 0-746 {}}} CYCLES {}}
+set a(0-746) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#38 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-363 XREFS 3847 LOC {2 0.0 2 0.732950075 2 0.732950075 2 0.791549784496936 2 0.791549784496936} PREDS {{146 0 0-540 {}} {258 0 0-743 {}} {259 0 0-745 {}}} SUCCS {{259 0 0-747 {}}} CYCLES {}}
+set a(0-747) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#39 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-363 XREFS 3848 LOC {2 0.05859975 2 0.7915498249999999 2 0.7915498249999999 2 0.8348897907468814 2 0.8348897907468814} PREDS {{146 0 0-540 {}} {258 0 0-724 {}} {259 0 0-746 {}}} SUCCS {{259 0 0-748 {}}} CYCLES {}}
+set a(0-748) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#40 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-363 XREFS 3849 LOC {2 0.101939775 2 0.8348898499999999 2 0.8348898499999999 2 0.9019182068650199 2 0.9019182068650199} PREDS {{146 0 0-540 {}} {258 0 0-723 {}} {259 0 0-747 {}}} SUCCS {{259 0 0-749 {}}} CYCLES {}}
+set a(0-749) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,10) AREA_SCORE 11.24 QUANTITY 1 NAME FRAME:acc#2 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-363 XREFS 3850 LOC {2 0.168968175 2 0.9019182499999999 2 0.9019182499999999 2 0.9832574783364112 2 0.9832574783364112} PREDS {{146 0 0-540 {}} {258 0 0-721 {}} {259 0 0-748 {}}} SUCCS {{258 0 0-752 {}}} CYCLES {}}
+set a(0-750) {NAME green:slc(green) TYPE READSLICE PAR 0-363 XREFS 3851 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-540 {}} {258 0 0-658 {}}} SUCCS {{259 0 0-751 {}}} CYCLES {}}
+set a(0-751) {NAME FRAME:exu TYPE PADZEROES PAR 0-363 XREFS 3852 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-540 {}} {259 0 0-750 {}}} SUCCS {{259 0 0-752 {}}} CYCLES {}}
+set a(0-752) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(10,2) AREA_SCORE 7.30 QUANTITY 1 NAME FRAME:or TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-363 XREFS 3853 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{146 0 0-540 {}} {258 0 0-749 {}} {259 0 0-751 {}}} SUCCS {{258 0 0-759 {}}} CYCLES {}}
+set a(0-753) {NAME green:slc(green)#1 TYPE READSLICE PAR 0-363 XREFS 3854 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 1.0} PREDS {{146 0 0-540 {}} {258 0 0-658 {}}} SUCCS {{258 0 0-759 {}}} CYCLES {}}
+set a(0-754) {NAME green:slc(green)#2 TYPE READSLICE PAR 0-363 XREFS 3855 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-540 {}} {258 0 0-658 {}}} SUCCS {{258 0 0-757 {}}} CYCLES {}}
+set a(0-755) {NAME blue:slc(blue) TYPE READSLICE PAR 0-363 XREFS 3856 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-540 {}} {258 0 0-713 {}}} SUCCS {{259 0 0-756 {}}} CYCLES {}}
+set a(0-756) {NAME FRAME:exu#10 TYPE PADZEROES PAR 0-363 XREFS 3857 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-540 {}} {259 0 0-755 {}}} SUCCS {{259 0 0-757 {}}} CYCLES {}}
+set a(0-757) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(6,2) AREA_SCORE 4.38 QUANTITY 1 NAME FRAME:or#3 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-363 XREFS 3858 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{146 0 0-540 {}} {258 0 0-754 {}} {259 0 0-756 {}}} SUCCS {{258 0 0-759 {}}} CYCLES {}}
+set a(0-758) {NAME blue:slc(blue)#1 TYPE READSLICE PAR 0-363 XREFS 3859 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 1.0} PREDS {{146 0 0-540 {}} {258 0 0-713 {}}} SUCCS {{259 0 0-759 {}}} CYCLES {}}
+set a(0-759) {NAME FRAME:conc#21 TYPE CONCATENATE PAR 0-363 XREFS 3860 LOC {2 0.340676225 2 1.0 2 1.0 2 1.0} PREDS {{146 0 0-540 {}} {258 0 0-757 {}} {258 0 0-753 {}} {258 0 0-752 {}} {259 0 0-758 {}}} SUCCS {{259 0 0-760 {}}} CYCLES {}}
+set a(0-760) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(2,30) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_write(vout:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-363 XREFS 3861 LOC {2 1.0 2 1.0 2 1.0 3 0.0 2 0.9999} PREDS {{130 0 0-540 {}} {260 0 0-760 {}} {259 0 0-759 {}}} SUCCS {{260 0 0-760 {}}} CYCLES {}}
+set a(0-761) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(19,0,2,1,19) AREA_SCORE 20.00 QUANTITY 1 NAME FRAME:acc#6 TYPE ACCU DELAY {1.91 ns} LIBRARY_DELAY {1.91 ns} PAR 0-363 XREFS 3862 LOC {1 0.10474599999999999 1 0.784864825 1 0.784864825 1 0.9041241410815966 2 0.5236100160815965} PREDS {{146 0 0-540 {}} {258 0 0-378 {}}} SUCCS {{259 0 0-762 {}} {258 0 0-781 {}}} CYCLES {}}
+set a(0-762) {NAME FRAME:p:slc(FRAME:p)#1 TYPE READSLICE PAR 0-363 XREFS 3863 LOC {1 0.22400537499999998 1 0.9041241999999999 1 0.9041241999999999 2 0.523610075} PREDS {{146 0 0-540 {}} {259 0 0-761 {}}} SUCCS {{259 0 0-763 {}}} CYCLES {}}
+set a(0-763) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,7,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME FRAME:acc TYPE ACCU DELAY {1.17 ns} LIBRARY_DELAY {1.17 ns} PAR 0-363 XREFS 3864 LOC {1 0.22400537499999998 1 0.9041241999999999 1 0.9041241999999999 1 0.9769393617915235 2 0.5964252367915236} PREDS {{146 0 0-540 {}} {259 0 0-762 {}}} SUCCS {{259 0 0-764 {}}} CYCLES {}}
+set a(0-764) {NAME FRAME:slc TYPE READSLICE PAR 0-363 XREFS 3865 LOC {1 0.296820575 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {{146 0 0-540 {}} {259 0 0-763 {}}} SUCCS {{259 0 0-765 {}}} CYCLES {}}
+set a(0-765) {NAME FRAME:not TYPE NOT PAR 0-363 XREFS 3866 LOC {1 0.296820575 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {{146 0 0-540 {}} {259 0 0-764 {}}} SUCCS {{258 0 0-768 {}} {258 0 0-769 {}}} CYCLES {}}
+set a(0-766) {NAME not#1 TYPE NOT PAR 0-363 XREFS 3867 LOC {1 0.0 1 0.0 1 0.0 2 0.596425275} PREDS {{258 0 0-380 {}}} SUCCS {{259 0 0-767 {}}} CYCLES {}}
+set a(0-767) {NAME FRAME:for:and#2 TYPE AND PAR 0-363 XREFS 3868 LOC {1 0.0 1 0.0 1 0.0 2 0.596425275} PREDS {{262 0 0-783 {}} {259 0 0-766 {}}} SUCCS {{259 0 0-768 {}} {256 0 0-783 {}}} CYCLES {}}
+set a(0-768) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 2 NAME FRAME:for:mux#23 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-363 XREFS 3869 LOC {1 0.296820575 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.6194858375} PREDS {{258 0 0-539 {}} {258 0 0-765 {}} {258 0 0-364 {}} {259 0 0-767 {}}} SUCCS {{258 0 0-783 {}} {258 0 0-785 {}}} CYCLES {}}
+set a(0-769) {NAME not#2 TYPE NOT PAR 0-363 XREFS 3870 LOC {1 0.296820575 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {{258 0 0-765 {}} {258 0 0-364 {}}} SUCCS {{259 0 0-770 {}}} CYCLES {}}
+set a(0-770) {NAME FRAME:for:or#1 TYPE OR PAR 0-363 XREFS 3871 LOC {1 0.296820575 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {{258 0 0-539 {}} {259 0 0-769 {}}} SUCCS {{259 0 0-771 {}}} CYCLES {}}
+set a(0-771) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 2 NAME FRAME:for:mux#24 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-363 XREFS 3872 LOC {1 0.296820575 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.6194858375} PREDS {{258 0 0-539 {}} {259 0 0-770 {}}} SUCCS {{258 0 0-784 {}} {258 0 0-785 {}}} CYCLES {}}
+set a(0-772) {NAME FRAME:for:asn(regs.regs(0).sva) TYPE ASSIGN PAR 0-363 XREFS 3873 LOC {1 0.0230606 1 0.044373425 1 0.044373425 2 0.619485875} PREDS {{260 0 0-772 {}} {256 0 0-437 {}} {256 0 0-439 {}} {258 0 0-438 {}}} SUCCS {{262 0 0-437 {}} {262 0 0-439 {}} {260 0 0-772 {}}} CYCLES {}}
+set a(0-773) {NAME FRAME:for:asn(regs.regs(1).sva) TYPE ASSIGN PAR 0-363 XREFS 3874 LOC {1 0.0230606 1 0.044373425 1 0.044373425 2 0.619485875} PREDS {{260 0 0-773 {}} {256 0 0-386 {}} {256 0 0-395 {}} {256 0 0-404 {}} {256 0 0-413 {}} {256 0 0-422 {}} {256 0 0-431 {}} {256 0 0-440 {}} {256 0 0-442 {}} {258 0 0-441 {}}} SUCCS {{262 0 0-386 {}} {262 0 0-395 {}} {262 0 0-404 {}} {262 0 0-413 {}} {262 0 0-422 {}} {262 0 0-431 {}} {262 0 0-440 {}} {262 0 0-442 {}} {260 0 0-773 {}}} CYCLES {}}
+set a(0-774) {NAME FRAME:for:asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-363 XREFS 3875 LOC {1 0.0230606 1 0.044373425 1 0.044373425 2 0.619485875} PREDS {{260 0 0-774 {}} {258 0 0-443 {}}} SUCCS {{262 0 0-443 {}} {260 0 0-774 {}}} CYCLES {}}
+set a(0-775) {NAME FRAME:for:asn(r(0).lpi#1) TYPE ASSIGN PAR 0-363 XREFS 3876 LOC {1 0.380514125 1 0.511719075 1 0.511719075 3 0.11560675} PREDS {{260 0 0-775 {}} {256 0 0-462 {}} {258 0 0-469 {}}} SUCCS {{262 0 0-462 {}} {260 0 0-775 {}}} CYCLES {}}
+set a(0-776) {NAME FRAME:for:asn(r(2).lpi#1) TYPE ASSIGN PAR 0-363 XREFS 3877 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 3 0.005714625} PREDS {{260 0 0-776 {}} {256 0 0-509 {}} {258 0 0-515 {}}} SUCCS {{262 0 0-509 {}} {260 0 0-776 {}}} CYCLES {}}
+set a(0-777) {NAME FRAME:for:asn(g(0).lpi#1) TYPE ASSIGN PAR 0-363 XREFS 3878 LOC {1 0.380514125 1 0.511719075 1 0.511719075 3 0.041980449999999996} PREDS {{260 0 0-777 {}} {256 0 0-472 {}} {258 0 0-479 {}}} SUCCS {{262 0 0-472 {}} {260 0 0-777 {}}} CYCLES {}}
+set a(0-778) {NAME FRAME:for:asn(g(2).lpi#1) TYPE ASSIGN PAR 0-363 XREFS 3879 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 2 0.8709376} PREDS {{260 0 0-778 {}} {256 0 0-518 {}} {258 0 0-524 {}}} SUCCS {{262 0 0-518 {}} {260 0 0-778 {}}} CYCLES {}}
+set a(0-779) {NAME FRAME:for:asn(b(0).lpi#1) TYPE ASSIGN PAR 0-363 XREFS 3880 LOC {1 0.380514125 1 0.511719075 1 0.511719075 3 0.041980449999999996} PREDS {{260 0 0-779 {}} {256 0 0-482 {}} {258 0 0-489 {}}} SUCCS {{262 0 0-482 {}} {260 0 0-779 {}}} CYCLES {}}
+set a(0-780) {NAME FRAME:for:asn(b(2).lpi#1) TYPE ASSIGN PAR 0-363 XREFS 3881 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 2 0.8709376} PREDS {{260 0 0-780 {}} {256 0 0-527 {}} {258 0 0-533 {}}} SUCCS {{262 0 0-527 {}} {260 0 0-780 {}}} CYCLES {}}
+set a(0-781) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(19,1,2) AREA_SCORE 17.47 QUANTITY 1 NAME FRAME:for:mux#19 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-363 XREFS 3882 LOC {1 0.22400537499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.3879438875} PREDS {{260 0 0-781 {}} {258 0 0-539 {}} {258 0 0-378 {}} {258 0 0-761 {}} {258 0 0-365 {}}} SUCCS {{262 0 0-378 {}} {260 0 0-781 {}}} CYCLES {}}
+set a(0-782) {NAME FRAME:for:asn(i#6.lpi#1) TYPE ASSIGN PAR 0-363 XREFS 3883 LOC {1 0.057189825 1 0.274782525 1 0.274782525 2 0.6261397} PREDS {{260 0 0-782 {}} {256 0 0-446 {}} {258 0 0-534 {}}} SUCCS {{262 0 0-446 {}} {260 0 0-782 {}}} CYCLES {}}
+set a(0-783) {NAME FRAME:for:asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-363 XREFS 3884 LOC {1 0.31988117499999996 1 1.0 1 1.0 3 0.596425275} PREDS {{260 0 0-783 {}} {256 0 0-767 {}} {258 0 0-768 {}}} SUCCS {{262 0 0-767 {}} {260 0 0-783 {}}} CYCLES {}}
+set a(0-784) {NAME FRAME:for:asn(exit:FRAME:for.lpi#1) TYPE ASSIGN PAR 0-363 XREFS 3885 LOC {1 0.31988117499999996 1 1.0 1 1.0 2 0.619485875} PREDS {{260 0 0-784 {}} {256 0 0-380 {}} {258 0 0-771 {}}} SUCCS {{262 0 0-380 {}} {260 0 0-784 {}}} CYCLES {}}
+set a(0-785) {NAME FRAME:and TYPE AND PAR 0-363 XREFS 3886 LOC {1 0.31988117499999996 1 1.0 1 1.0 2 0.619485875} PREDS {{258 0 0-768 {}} {258 0 0-771 {}}} SUCCS {{259 0 0-786 {}}} CYCLES {}}
+set a(0-786) {NAME FRAME:asn#3 TYPE ASSIGN PAR 0-363 XREFS 3887 LOC {1 0.31988117499999996 1 1.0 1 1.0 2 0.619485875} PREDS {{260 0 0-786 {}} {256 0 0-373 {}} {256 0 0-375 {}} {256 0 0-379 {}} {259 0 0-785 {}}} SUCCS {{262 0 0-373 {}} {262 0 0-375 {}} {262 0 0-379 {}} {260 0 0-786 {}}} CYCLES {}}
+set a(0-363) {CHI {0-364 0-365 0-366 0-367 0-368 0-369 0-370 0-371 0-372 0-373 0-374 0-375 0-376 0-377 0-378 0-379 0-380 0-381 0-382 0-383 0-384 0-385 0-386 0-387 0-388 0-389 0-390 0-391 0-392 0-393 0-394 0-395 0-396 0-397 0-398 0-399 0-400 0-401 0-402 0-403 0-404 0-405 0-406 0-407 0-408 0-409 0-410 0-411 0-412 0-413 0-414 0-415 0-416 0-417 0-418 0-419 0-420 0-421 0-422 0-423 0-424 0-425 0-426 0-427 0-428 0-429 0-430 0-431 0-432 0-433 0-434 0-435 0-436 0-437 0-438 0-439 0-440 0-441 0-442 0-443 0-444 0-445 0-446 0-447 0-448 0-449 0-450 0-451 0-452 0-453 0-454 0-455 0-456 0-457 0-458 0-459 0-460 0-461 0-462 0-463 0-464 0-465 0-466 0-467 0-468 0-469 0-470 0-471 0-472 0-473 0-474 0-475 0-476 0-477 0-478 0-479 0-480 0-481 0-482 0-483 0-484 0-485 0-486 0-487 0-488 0-489 0-490 0-491 0-492 0-493 0-494 0-495 0-496 0-497 0-498 0-499 0-500 0-501 0-502 0-503 0-504 0-505 0-506 0-507 0-508 0-509 0-510 0-511 0-512 0-513 0-514 0-515 0-516 0-517 0-518 0-519 0-520 0-521 0-522 0-523 0-524 0-525 0-526 0-527 0-528 0-529 0-530 0-531 0-532 0-533 0-534 0-535 0-536 0-537 0-538 0-539 0-540 0-541 0-542 0-543 0-544 0-545 0-546 0-547 0-548 0-549 0-550 0-551 0-552 0-553 0-554 0-555 0-556 0-557 0-558 0-559 0-560 0-561 0-562 0-563 0-564 0-565 0-566 0-567 0-568 0-569 0-570 0-571 0-572 0-573 0-574 0-575 0-576 0-577 0-578 0-579 0-580 0-581 0-582 0-583 0-584 0-585 0-586 0-587 0-588 0-589 0-590 0-591 0-592 0-593 0-594 0-595 0-596 0-597 0-598 0-599 0-600 0-601 0-602 0-603 0-604 0-605 0-606 0-607 0-608 0-609 0-610 0-611 0-612 0-613 0-614 0-615 0-616 0-617 0-618 0-619 0-620 0-621 0-622 0-623 0-624 0-625 0-626 0-627 0-628 0-629 0-630 0-631 0-632 0-633 0-634 0-635 0-636 0-637 0-638 0-639 0-640 0-641 0-642 0-643 0-644 0-645 0-646 0-647 0-648 0-649 0-650 0-651 0-652 0-653 0-654 0-655 0-656 0-657 0-658 0-659 0-660 0-661 0-662 0-663 0-664 0-665 0-666 0-667 0-668 0-669 0-670 0-671 0-672 0-673 0-674 0-675 0-676 0-677 0-678 0-679 0-680 0-681 0-682 0-683 0-684 0-685 0-686 0-687 0-688 0-689 0-690 0-691 0-692 0-693 0-694 0-695 0-696 0-697 0-698 0-699 0-700 0-701 0-702 0-703 0-704 0-705 0-706 0-707 0-708 0-709 0-710 0-711 0-712 0-713 0-714 0-715 0-716 0-717 0-718 0-719 0-720 0-721 0-722 0-723 0-724 0-725 0-726 0-727 0-728 0-729 0-730 0-731 0-732 0-733 0-734 0-735 0-736 0-737 0-738 0-739 0-740 0-741 0-742 0-743 0-744 0-745 0-746 0-747 0-748 0-749 0-750 0-751 0-752 0-753 0-754 0-755 0-756 0-757 0-758 0-759 0-760 0-761 0-762 0-763 0-764 0-765 0-766 0-767 0-768 0-769 0-770 0-771 0-772 0-773 0-774 0-775 0-776 0-777 0-778 0-779 0-780 0-781 0-782 0-783 0-784 0-785 0-786} ITERATIONS Infinite LATENCY 921601 RESET_LATENCY 0 CSTEPS 3 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 921600 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 3.0 CYCLES_IN 921602 TOTAL_CYCLES_IN 921602 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 921602 NAME main TYPE LOOP DELAY {18432060.00 ns} PAR 0-348 XREFS 3888 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{258 0 0-357 {}} {258 0 0-350 {}} {258 0 0-351 {}} {258 0 0-352 {}} {258 0 0-353 {}} {258 0 0-354 {}} {258 0 0-355 {}} {258 0 0-349 {}} {258 0 0-356 {}} {258 0 0-361 {}} {258 0 0-360 {}} {258 0 0-358 {}} {258 0 0-359 {}} {259 0 0-362 {}}} SUCCS {{772 0 0-349 {}} {772 0 0-350 {}} {772 0 0-351 {}} {772 0 0-352 {}} {772 0 0-353 {}} {772 0 0-354 {}} {772 0 0-355 {}} {772 0 0-356 {}} {772 0 0-357 {}} {772 0 0-358 {}} {772 0 0-359 {}} {772 0 0-360 {}} {772 0 0-361 {}} {772 0 0-362 {}}} CYCLES {}}
+set a(0-348) {CHI {0-349 0-350 0-351 0-352 0-353 0-354 0-355 0-356 0-357 0-358 0-359 0-360 0-361 0-362 0-363} ITERATIONS Infinite LATENCY 921601 RESET_LATENCY 0 CSTEPS 0 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 921600 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 0 TOTAL_CYCLES_IN 0 TOTAL_CYCLES_UNDER 921602 TOTAL_CYCLES 921602 NAME core:rlp TYPE LOOP DELAY {18432060.00 ns} PAR {} XREFS 3889 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-348-TOTALCYCLES) {921602}
+set a(0-348-QMOD) {mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2) 0-378 mgc_ioport.mgc_in_wire(1,90) 0-382 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12) {0-389 0-398 0-407 0-416 0-425 0-434} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2) {0-438 0-441 0-443} mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2) {0-446 0-501} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2) {0-462 0-472 0-482 0-509 0-518 0-527} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4) {0-466 0-476 0-486 0-513 0-522 0-531} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12) {0-468 0-478 0-488 0-514 0-523 0-532} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16) {0-469 0-479 0-489 0-515 0-524 0-533} mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(2,2) 0-506 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2) 0-534 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) 0-537 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) {0-549 0-564 0-579 0-658 0-713} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(17,0,13,1,17) {0-552 0-567 0-582} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16) {0-554 0-569 0-584} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4) {0-589 0-596 0-601 0-607 0-614 0-619 0-642 0-662 0-669 0-674 0-697 0-740} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5) {0-597 0-615 0-645 0-670 0-700 0-743} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6) {0-602 0-620 0-675} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6) {0-603 0-621 0-676} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11) {0-623 0-678 0-715} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9) {0-625 0-680 0-723} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5) {0-636 0-648 0-691 0-703 0-734 0-746} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8) {0-649 0-704 0-747} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10) {0-650 0-705 0-748} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12) {0-651 0-706} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,9,1,10) 0-721 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,10) 0-749 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2) 0-752 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2) 0-757 mgc_ioport.mgc_out_stdreg(2,30) 0-760 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19) 0-761 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,7,0,8) 0-763 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2) {0-768 0-771} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2) 0-781}
+set a(0-348-PROC_NAME) {core}
+set a(0-348-HIER_NAME) {/sobel/core}
+set a(TOP) {0-348}
+
diff --git a/Sobel/sobel.v2/schematic.nlv b/Sobel/sobel.v2/schematic.nlv
new file mode 100644
index 0000000..e1fd0dc
--- /dev/null
+++ b/Sobel/sobel.v2/schematic.nlv
@@ -0,0 +1,10448 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "sobel:core" "orig"
+load port {clk} input -attr xrf 4867 -attr oid 1 -attr vt d -attr @path {/sobel/sobel:core/clk}
+load port {en} input -attr xrf 4868 -attr oid 2 -attr vt d -attr @path {/sobel/sobel:core/en}
+load port {arst_n} input -attr xrf 4869 -attr oid 3 -attr vt d -attr @path {/sobel/sobel:core/arst_n}
+load portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} -attr xrf 4870 -attr oid 4 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} -attr xrf 4871 -attr oid 5 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load symbol "add(5,-1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,-1,10,-1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,10)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,6)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(5:0)} input 6 {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(5:0)} input 6 {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nand(2,1)" "INTERFACE" NAND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,30)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(29:0)} input 30 {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(29:0)} input 30 {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(30,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(29:0)} input 30 {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(29:0)} input 30 {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,1,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "reg(2,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(1:0)} input 2 {D(1)} {D(0)} \
+     portBus {DRa(1:0)} input 2 {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(6,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(5:0)} input 6 {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(5:0)} input 6 {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,6,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(9,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(8:0)} input 9 {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(8:0)} input 9 {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "not(3)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(5,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(4:0)} input 5 {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(4:0)} input 5 {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(1,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(0:0)} input 1 {D(0)} \
+     portBus {DRa(0:0)} input 1 {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mul(2,0,9,0,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(11,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(10:0)} input 11 {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(10:0)} input 11 {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "reg(90,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(89:0)} input 90 {D(89)} {D(88)} {D(87)} {D(86)} {D(85)} {D(84)} {D(83)} {D(82)} {D(81)} {D(80)} {D(79)} {D(78)} {D(77)} {D(76)} {D(75)} {D(74)} {D(73)} {D(72)} {D(71)} {D(70)} {D(69)} {D(68)} {D(67)} {D(66)} {D(65)} {D(64)} {D(63)} {D(62)} {D(61)} {D(60)} {D(59)} {D(58)} {D(57)} {D(56)} {D(55)} {D(54)} {D(53)} {D(52)} {D(51)} {D(50)} {D(49)} {D(48)} {D(47)} {D(46)} {D(45)} {D(44)} {D(43)} {D(42)} {D(41)} {D(40)} {D(39)} {D(38)} {D(37)} {D(36)} {D(35)} {D(34)} {D(33)} {D(32)} {D(31)} {D(30)} {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(89:0)} input 90 {DRa(89)} {DRa(88)} {DRa(87)} {DRa(86)} {DRa(85)} {DRa(84)} {DRa(83)} {DRa(82)} {DRa(81)} {DRa(80)} {DRa(79)} {DRa(78)} {DRa(77)} {DRa(76)} {DRa(75)} {DRa(74)} {DRa(73)} {DRa(72)} {DRa(71)} {DRa(70)} {DRa(69)} {DRa(68)} {DRa(67)} {DRa(66)} {DRa(65)} {DRa(64)} {DRa(63)} {DRa(62)} {DRa(61)} {DRa(60)} {DRa(59)} {DRa(58)} {DRa(57)} {DRa(56)} {DRa(55)} {DRa(54)} {DRa(53)} {DRa(52)} {DRa(51)} {DRa(50)} {DRa(49)} {DRa(48)} {DRa(47)} {DRa(46)} {DRa(45)} {DRa(44)} {DRa(43)} {DRa(42)} {DRa(41)} {DRa(40)} {DRa(39)} {DRa(38)} {DRa(37)} {DRa(36)} {DRa(35)} {DRa(34)} {DRa(33)} {DRa(32)} {DRa(31)} {DRa(30)} {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(16,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(15:0)} input 16 {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(15:0)} input 16 {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,19)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(19,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(18:0)} input 19 {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(18:0)} input 19 {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,0,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,-1,11,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "and(2,2)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(1:0)} input 2 {A0(1)} {A0(0)} \
+     portBus {A1(1:0)} input 2 {A1(1)} {A1(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "or(2,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,90)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(89:0)} input 90 {A0(89)} {A0(88)} {A0(87)} {A0(86)} {A0(85)} {A0(84)} {A0(83)} {A0(82)} {A0(81)} {A0(80)} {A0(79)} {A0(78)} {A0(77)} {A0(76)} {A0(75)} {A0(74)} {A0(73)} {A0(72)} {A0(71)} {A0(70)} {A0(69)} {A0(68)} {A0(67)} {A0(66)} {A0(65)} {A0(64)} {A0(63)} {A0(62)} {A0(61)} {A0(60)} {A0(59)} {A0(58)} {A0(57)} {A0(56)} {A0(55)} {A0(54)} {A0(53)} {A0(52)} {A0(51)} {A0(50)} {A0(49)} {A0(48)} {A0(47)} {A0(46)} {A0(45)} {A0(44)} {A0(43)} {A0(42)} {A0(41)} {A0(40)} {A0(39)} {A0(38)} {A0(37)} {A0(36)} {A0(35)} {A0(34)} {A0(33)} {A0(32)} {A0(31)} {A0(30)} {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(89:0)} input 90 {A1(89)} {A1(88)} {A1(87)} {A1(86)} {A1(85)} {A1(84)} {A1(83)} {A1(82)} {A1(81)} {A1(80)} {A1(79)} {A1(78)} {A1(77)} {A1(76)} {A1(75)} {A1(74)} {A1(73)} {A1(72)} {A1(71)} {A1(70)} {A1(69)} {A1(68)} {A1(67)} {A1(66)} {A1(65)} {A1(64)} {A1(63)} {A1(62)} {A1(61)} {A1(60)} {A1(59)} {A1(58)} {A1(57)} {A1(56)} {A1(55)} {A1(54)} {A1(53)} {A1(52)} {A1(51)} {A1(50)} {A1(49)} {A1(48)} {A1(47)} {A1(46)} {A1(45)} {A1(44)} {A1(43)} {A1(42)} {A1(41)} {A1(40)} {A1(39)} {A1(38)} {A1(37)} {A1(36)} {A1(35)} {A1(34)} {A1(33)} {A1(32)} {A1(31)} {A1(30)} {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,8,-1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,1)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(19,-1,1,0,19)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(18:0)} input 19 {A(18)} {A(17)} {A(16)} {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,19)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,-1,6,-1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(10)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,11,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,15,-1,15)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(14:0)} input 15 {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,16,-1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,10)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,16)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(15:0)} input 16 {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(15:0)} input 16 {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(4,10)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {A2(9:0)} input 10 {A2(9)} {A2(8)} {A2(7)} {A2(6)} {A2(5)} {A2(4)} {A2(3)} {A2(2)} {A2(1)} {A2(0)} \
+     portBus {A3(9:0)} input 10 {A3(9)} {A3(8)} {A3(7)} {A3(6)} {A3(5)} {A3(4)} {A3(3)} {A3(2)} {A3(1)} {A3(0)} \
+     portBus {S(1:0)} input.top 2 {S(1)} {S(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,11,1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,12)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,12,1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nor(2,1)" "INTERFACE" NOR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "or(3,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load net {FRAME:p#1.lpi#1(0)} -attr vt d
+load net {FRAME:p#1.lpi#1(1)} -attr vt d
+load net {FRAME:p#1.lpi#1(2)} -attr vt d
+load net {FRAME:p#1.lpi#1(3)} -attr vt d
+load net {FRAME:p#1.lpi#1(4)} -attr vt d
+load net {FRAME:p#1.lpi#1(5)} -attr vt d
+load net {FRAME:p#1.lpi#1(6)} -attr vt d
+load net {FRAME:p#1.lpi#1(7)} -attr vt d
+load net {FRAME:p#1.lpi#1(8)} -attr vt d
+load net {FRAME:p#1.lpi#1(9)} -attr vt d
+load net {FRAME:p#1.lpi#1(10)} -attr vt d
+load net {FRAME:p#1.lpi#1(11)} -attr vt d
+load net {FRAME:p#1.lpi#1(12)} -attr vt d
+load net {FRAME:p#1.lpi#1(13)} -attr vt d
+load net {FRAME:p#1.lpi#1(14)} -attr vt d
+load net {FRAME:p#1.lpi#1(15)} -attr vt d
+load net {FRAME:p#1.lpi#1(16)} -attr vt d
+load net {FRAME:p#1.lpi#1(17)} -attr vt d
+load net {FRAME:p#1.lpi#1(18)} -attr vt d
+load netBundle {FRAME:p#1.lpi#1} 19 {FRAME:p#1.lpi#1(0)} {FRAME:p#1.lpi#1(1)} {FRAME:p#1.lpi#1(2)} {FRAME:p#1.lpi#1(3)} {FRAME:p#1.lpi#1(4)} {FRAME:p#1.lpi#1(5)} {FRAME:p#1.lpi#1(6)} {FRAME:p#1.lpi#1(7)} {FRAME:p#1.lpi#1(8)} {FRAME:p#1.lpi#1(9)} {FRAME:p#1.lpi#1(10)} {FRAME:p#1.lpi#1(11)} {FRAME:p#1.lpi#1(12)} {FRAME:p#1.lpi#1(13)} {FRAME:p#1.lpi#1(14)} {FRAME:p#1.lpi#1(15)} {FRAME:p#1.lpi#1(16)} {FRAME:p#1.lpi#1(17)} {FRAME:p#1.lpi#1(18)} -attr xrf 4872 -attr oid 6 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {regs.regs(1).sva(0)} -attr vt d
+load net {regs.regs(1).sva(1)} -attr vt d
+load net {regs.regs(1).sva(2)} -attr vt d
+load net {regs.regs(1).sva(3)} -attr vt d
+load net {regs.regs(1).sva(4)} -attr vt d
+load net {regs.regs(1).sva(5)} -attr vt d
+load net {regs.regs(1).sva(6)} -attr vt d
+load net {regs.regs(1).sva(7)} -attr vt d
+load net {regs.regs(1).sva(8)} -attr vt d
+load net {regs.regs(1).sva(9)} -attr vt d
+load net {regs.regs(1).sva(10)} -attr vt d
+load net {regs.regs(1).sva(11)} -attr vt d
+load net {regs.regs(1).sva(12)} -attr vt d
+load net {regs.regs(1).sva(13)} -attr vt d
+load net {regs.regs(1).sva(14)} -attr vt d
+load net {regs.regs(1).sva(15)} -attr vt d
+load net {regs.regs(1).sva(16)} -attr vt d
+load net {regs.regs(1).sva(17)} -attr vt d
+load net {regs.regs(1).sva(18)} -attr vt d
+load net {regs.regs(1).sva(19)} -attr vt d
+load net {regs.regs(1).sva(20)} -attr vt d
+load net {regs.regs(1).sva(21)} -attr vt d
+load net {regs.regs(1).sva(22)} -attr vt d
+load net {regs.regs(1).sva(23)} -attr vt d
+load net {regs.regs(1).sva(24)} -attr vt d
+load net {regs.regs(1).sva(25)} -attr vt d
+load net {regs.regs(1).sva(26)} -attr vt d
+load net {regs.regs(1).sva(27)} -attr vt d
+load net {regs.regs(1).sva(28)} -attr vt d
+load net {regs.regs(1).sva(29)} -attr vt d
+load net {regs.regs(1).sva(30)} -attr vt d
+load net {regs.regs(1).sva(31)} -attr vt d
+load net {regs.regs(1).sva(32)} -attr vt d
+load net {regs.regs(1).sva(33)} -attr vt d
+load net {regs.regs(1).sva(34)} -attr vt d
+load net {regs.regs(1).sva(35)} -attr vt d
+load net {regs.regs(1).sva(36)} -attr vt d
+load net {regs.regs(1).sva(37)} -attr vt d
+load net {regs.regs(1).sva(38)} -attr vt d
+load net {regs.regs(1).sva(39)} -attr vt d
+load net {regs.regs(1).sva(40)} -attr vt d
+load net {regs.regs(1).sva(41)} -attr vt d
+load net {regs.regs(1).sva(42)} -attr vt d
+load net {regs.regs(1).sva(43)} -attr vt d
+load net {regs.regs(1).sva(44)} -attr vt d
+load net {regs.regs(1).sva(45)} -attr vt d
+load net {regs.regs(1).sva(46)} -attr vt d
+load net {regs.regs(1).sva(47)} -attr vt d
+load net {regs.regs(1).sva(48)} -attr vt d
+load net {regs.regs(1).sva(49)} -attr vt d
+load net {regs.regs(1).sva(50)} -attr vt d
+load net {regs.regs(1).sva(51)} -attr vt d
+load net {regs.regs(1).sva(52)} -attr vt d
+load net {regs.regs(1).sva(53)} -attr vt d
+load net {regs.regs(1).sva(54)} -attr vt d
+load net {regs.regs(1).sva(55)} -attr vt d
+load net {regs.regs(1).sva(56)} -attr vt d
+load net {regs.regs(1).sva(57)} -attr vt d
+load net {regs.regs(1).sva(58)} -attr vt d
+load net {regs.regs(1).sva(59)} -attr vt d
+load net {regs.regs(1).sva(60)} -attr vt d
+load net {regs.regs(1).sva(61)} -attr vt d
+load net {regs.regs(1).sva(62)} -attr vt d
+load net {regs.regs(1).sva(63)} -attr vt d
+load net {regs.regs(1).sva(64)} -attr vt d
+load net {regs.regs(1).sva(65)} -attr vt d
+load net {regs.regs(1).sva(66)} -attr vt d
+load net {regs.regs(1).sva(67)} -attr vt d
+load net {regs.regs(1).sva(68)} -attr vt d
+load net {regs.regs(1).sva(69)} -attr vt d
+load net {regs.regs(1).sva(70)} -attr vt d
+load net {regs.regs(1).sva(71)} -attr vt d
+load net {regs.regs(1).sva(72)} -attr vt d
+load net {regs.regs(1).sva(73)} -attr vt d
+load net {regs.regs(1).sva(74)} -attr vt d
+load net {regs.regs(1).sva(75)} -attr vt d
+load net {regs.regs(1).sva(76)} -attr vt d
+load net {regs.regs(1).sva(77)} -attr vt d
+load net {regs.regs(1).sva(78)} -attr vt d
+load net {regs.regs(1).sva(79)} -attr vt d
+load net {regs.regs(1).sva(80)} -attr vt d
+load net {regs.regs(1).sva(81)} -attr vt d
+load net {regs.regs(1).sva(82)} -attr vt d
+load net {regs.regs(1).sva(83)} -attr vt d
+load net {regs.regs(1).sva(84)} -attr vt d
+load net {regs.regs(1).sva(85)} -attr vt d
+load net {regs.regs(1).sva(86)} -attr vt d
+load net {regs.regs(1).sva(87)} -attr vt d
+load net {regs.regs(1).sva(88)} -attr vt d
+load net {regs.regs(1).sva(89)} -attr vt d
+load netBundle {regs.regs(1).sva} 90 {regs.regs(1).sva(0)} {regs.regs(1).sva(1)} {regs.regs(1).sva(2)} {regs.regs(1).sva(3)} {regs.regs(1).sva(4)} {regs.regs(1).sva(5)} {regs.regs(1).sva(6)} {regs.regs(1).sva(7)} {regs.regs(1).sva(8)} {regs.regs(1).sva(9)} {regs.regs(1).sva(10)} {regs.regs(1).sva(11)} {regs.regs(1).sva(12)} {regs.regs(1).sva(13)} {regs.regs(1).sva(14)} {regs.regs(1).sva(15)} {regs.regs(1).sva(16)} {regs.regs(1).sva(17)} {regs.regs(1).sva(18)} {regs.regs(1).sva(19)} {regs.regs(1).sva(20)} {regs.regs(1).sva(21)} {regs.regs(1).sva(22)} {regs.regs(1).sva(23)} {regs.regs(1).sva(24)} {regs.regs(1).sva(25)} {regs.regs(1).sva(26)} {regs.regs(1).sva(27)} {regs.regs(1).sva(28)} {regs.regs(1).sva(29)} {regs.regs(1).sva(30)} {regs.regs(1).sva(31)} {regs.regs(1).sva(32)} {regs.regs(1).sva(33)} {regs.regs(1).sva(34)} {regs.regs(1).sva(35)} {regs.regs(1).sva(36)} {regs.regs(1).sva(37)} {regs.regs(1).sva(38)} {regs.regs(1).sva(39)} {regs.regs(1).sva(40)} {regs.regs(1).sva(41)} {regs.regs(1).sva(42)} {regs.regs(1).sva(43)} {regs.regs(1).sva(44)} {regs.regs(1).sva(45)} {regs.regs(1).sva(46)} {regs.regs(1).sva(47)} {regs.regs(1).sva(48)} {regs.regs(1).sva(49)} {regs.regs(1).sva(50)} {regs.regs(1).sva(51)} {regs.regs(1).sva(52)} {regs.regs(1).sva(53)} {regs.regs(1).sva(54)} {regs.regs(1).sva(55)} {regs.regs(1).sva(56)} {regs.regs(1).sva(57)} {regs.regs(1).sva(58)} {regs.regs(1).sva(59)} {regs.regs(1).sva(60)} {regs.regs(1).sva(61)} {regs.regs(1).sva(62)} {regs.regs(1).sva(63)} {regs.regs(1).sva(64)} {regs.regs(1).sva(65)} {regs.regs(1).sva(66)} {regs.regs(1).sva(67)} {regs.regs(1).sva(68)} {regs.regs(1).sva(69)} {regs.regs(1).sva(70)} {regs.regs(1).sva(71)} {regs.regs(1).sva(72)} {regs.regs(1).sva(73)} {regs.regs(1).sva(74)} {regs.regs(1).sva(75)} {regs.regs(1).sva(76)} {regs.regs(1).sva(77)} {regs.regs(1).sva(78)} {regs.regs(1).sva(79)} {regs.regs(1).sva(80)} {regs.regs(1).sva(81)} {regs.regs(1).sva(82)} {regs.regs(1).sva(83)} {regs.regs(1).sva(84)} {regs.regs(1).sva(85)} {regs.regs(1).sva(86)} {regs.regs(1).sva(87)} {regs.regs(1).sva(88)} {regs.regs(1).sva(89)} -attr xrf 4873 -attr oid 7 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -attr vt d
+load net {regs.regs(0).sva(1)} -attr vt d
+load net {regs.regs(0).sva(2)} -attr vt d
+load net {regs.regs(0).sva(3)} -attr vt d
+load net {regs.regs(0).sva(4)} -attr vt d
+load net {regs.regs(0).sva(5)} -attr vt d
+load net {regs.regs(0).sva(6)} -attr vt d
+load net {regs.regs(0).sva(7)} -attr vt d
+load net {regs.regs(0).sva(8)} -attr vt d
+load net {regs.regs(0).sva(9)} -attr vt d
+load net {regs.regs(0).sva(10)} -attr vt d
+load net {regs.regs(0).sva(11)} -attr vt d
+load net {regs.regs(0).sva(12)} -attr vt d
+load net {regs.regs(0).sva(13)} -attr vt d
+load net {regs.regs(0).sva(14)} -attr vt d
+load net {regs.regs(0).sva(15)} -attr vt d
+load net {regs.regs(0).sva(16)} -attr vt d
+load net {regs.regs(0).sva(17)} -attr vt d
+load net {regs.regs(0).sva(18)} -attr vt d
+load net {regs.regs(0).sva(19)} -attr vt d
+load net {regs.regs(0).sva(20)} -attr vt d
+load net {regs.regs(0).sva(21)} -attr vt d
+load net {regs.regs(0).sva(22)} -attr vt d
+load net {regs.regs(0).sva(23)} -attr vt d
+load net {regs.regs(0).sva(24)} -attr vt d
+load net {regs.regs(0).sva(25)} -attr vt d
+load net {regs.regs(0).sva(26)} -attr vt d
+load net {regs.regs(0).sva(27)} -attr vt d
+load net {regs.regs(0).sva(28)} -attr vt d
+load net {regs.regs(0).sva(29)} -attr vt d
+load net {regs.regs(0).sva(30)} -attr vt d
+load net {regs.regs(0).sva(31)} -attr vt d
+load net {regs.regs(0).sva(32)} -attr vt d
+load net {regs.regs(0).sva(33)} -attr vt d
+load net {regs.regs(0).sva(34)} -attr vt d
+load net {regs.regs(0).sva(35)} -attr vt d
+load net {regs.regs(0).sva(36)} -attr vt d
+load net {regs.regs(0).sva(37)} -attr vt d
+load net {regs.regs(0).sva(38)} -attr vt d
+load net {regs.regs(0).sva(39)} -attr vt d
+load net {regs.regs(0).sva(40)} -attr vt d
+load net {regs.regs(0).sva(41)} -attr vt d
+load net {regs.regs(0).sva(42)} -attr vt d
+load net {regs.regs(0).sva(43)} -attr vt d
+load net {regs.regs(0).sva(44)} -attr vt d
+load net {regs.regs(0).sva(45)} -attr vt d
+load net {regs.regs(0).sva(46)} -attr vt d
+load net {regs.regs(0).sva(47)} -attr vt d
+load net {regs.regs(0).sva(48)} -attr vt d
+load net {regs.regs(0).sva(49)} -attr vt d
+load net {regs.regs(0).sva(50)} -attr vt d
+load net {regs.regs(0).sva(51)} -attr vt d
+load net {regs.regs(0).sva(52)} -attr vt d
+load net {regs.regs(0).sva(53)} -attr vt d
+load net {regs.regs(0).sva(54)} -attr vt d
+load net {regs.regs(0).sva(55)} -attr vt d
+load net {regs.regs(0).sva(56)} -attr vt d
+load net {regs.regs(0).sva(57)} -attr vt d
+load net {regs.regs(0).sva(58)} -attr vt d
+load net {regs.regs(0).sva(59)} -attr vt d
+load net {regs.regs(0).sva(60)} -attr vt d
+load net {regs.regs(0).sva(61)} -attr vt d
+load net {regs.regs(0).sva(62)} -attr vt d
+load net {regs.regs(0).sva(63)} -attr vt d
+load net {regs.regs(0).sva(64)} -attr vt d
+load net {regs.regs(0).sva(65)} -attr vt d
+load net {regs.regs(0).sva(66)} -attr vt d
+load net {regs.regs(0).sva(67)} -attr vt d
+load net {regs.regs(0).sva(68)} -attr vt d
+load net {regs.regs(0).sva(69)} -attr vt d
+load net {regs.regs(0).sva(70)} -attr vt d
+load net {regs.regs(0).sva(71)} -attr vt d
+load net {regs.regs(0).sva(72)} -attr vt d
+load net {regs.regs(0).sva(73)} -attr vt d
+load net {regs.regs(0).sva(74)} -attr vt d
+load net {regs.regs(0).sva(75)} -attr vt d
+load net {regs.regs(0).sva(76)} -attr vt d
+load net {regs.regs(0).sva(77)} -attr vt d
+load net {regs.regs(0).sva(78)} -attr vt d
+load net {regs.regs(0).sva(79)} -attr vt d
+load net {regs.regs(0).sva(80)} -attr vt d
+load net {regs.regs(0).sva(81)} -attr vt d
+load net {regs.regs(0).sva(82)} -attr vt d
+load net {regs.regs(0).sva(83)} -attr vt d
+load net {regs.regs(0).sva(84)} -attr vt d
+load net {regs.regs(0).sva(85)} -attr vt d
+load net {regs.regs(0).sva(86)} -attr vt d
+load net {regs.regs(0).sva(87)} -attr vt d
+load net {regs.regs(0).sva(88)} -attr vt d
+load net {regs.regs(0).sva(89)} -attr vt d
+load netBundle {regs.regs(0).sva} 90 {regs.regs(0).sva(0)} {regs.regs(0).sva(1)} {regs.regs(0).sva(2)} {regs.regs(0).sva(3)} {regs.regs(0).sva(4)} {regs.regs(0).sva(5)} {regs.regs(0).sva(6)} {regs.regs(0).sva(7)} {regs.regs(0).sva(8)} {regs.regs(0).sva(9)} {regs.regs(0).sva(10)} {regs.regs(0).sva(11)} {regs.regs(0).sva(12)} {regs.regs(0).sva(13)} {regs.regs(0).sva(14)} {regs.regs(0).sva(15)} {regs.regs(0).sva(16)} {regs.regs(0).sva(17)} {regs.regs(0).sva(18)} {regs.regs(0).sva(19)} {regs.regs(0).sva(20)} {regs.regs(0).sva(21)} {regs.regs(0).sva(22)} {regs.regs(0).sva(23)} {regs.regs(0).sva(24)} {regs.regs(0).sva(25)} {regs.regs(0).sva(26)} {regs.regs(0).sva(27)} {regs.regs(0).sva(28)} {regs.regs(0).sva(29)} {regs.regs(0).sva(30)} {regs.regs(0).sva(31)} {regs.regs(0).sva(32)} {regs.regs(0).sva(33)} {regs.regs(0).sva(34)} {regs.regs(0).sva(35)} {regs.regs(0).sva(36)} {regs.regs(0).sva(37)} {regs.regs(0).sva(38)} {regs.regs(0).sva(39)} {regs.regs(0).sva(40)} {regs.regs(0).sva(41)} {regs.regs(0).sva(42)} {regs.regs(0).sva(43)} {regs.regs(0).sva(44)} {regs.regs(0).sva(45)} {regs.regs(0).sva(46)} {regs.regs(0).sva(47)} {regs.regs(0).sva(48)} {regs.regs(0).sva(49)} {regs.regs(0).sva(50)} {regs.regs(0).sva(51)} {regs.regs(0).sva(52)} {regs.regs(0).sva(53)} {regs.regs(0).sva(54)} {regs.regs(0).sva(55)} {regs.regs(0).sva(56)} {regs.regs(0).sva(57)} {regs.regs(0).sva(58)} {regs.regs(0).sva(59)} {regs.regs(0).sva(60)} {regs.regs(0).sva(61)} {regs.regs(0).sva(62)} {regs.regs(0).sva(63)} {regs.regs(0).sva(64)} {regs.regs(0).sva(65)} {regs.regs(0).sva(66)} {regs.regs(0).sva(67)} {regs.regs(0).sva(68)} {regs.regs(0).sva(69)} {regs.regs(0).sva(70)} {regs.regs(0).sva(71)} {regs.regs(0).sva(72)} {regs.regs(0).sva(73)} {regs.regs(0).sva(74)} {regs.regs(0).sva(75)} {regs.regs(0).sva(76)} {regs.regs(0).sva(77)} {regs.regs(0).sva(78)} {regs.regs(0).sva(79)} {regs.regs(0).sva(80)} {regs.regs(0).sva(81)} {regs.regs(0).sva(82)} {regs.regs(0).sva(83)} {regs.regs(0).sva(84)} {regs.regs(0).sva(85)} {regs.regs(0).sva(86)} {regs.regs(0).sva(87)} {regs.regs(0).sva(88)} {regs.regs(0).sva(89)} -attr xrf 4874 -attr oid 8 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(2).lpi#1.dfm(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(29)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(30)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(31)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(32)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(33)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(34)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(35)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(36)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(37)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(38)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(39)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(40)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(41)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(42)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(43)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(44)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(45)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(46)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(47)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(48)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(49)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(50)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(51)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(52)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(53)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(54)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(55)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(56)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(57)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(58)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(59)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(60)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(61)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(62)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(63)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(64)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(65)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(66)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(67)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(68)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(69)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(70)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(71)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(72)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(73)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(74)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(75)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(76)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(77)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(78)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(79)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(80)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(81)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(82)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(83)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(84)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(85)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(86)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(87)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(88)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(89)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm} 90 {regs.regs(2).lpi#1.dfm(0)} {regs.regs(2).lpi#1.dfm(1)} {regs.regs(2).lpi#1.dfm(2)} {regs.regs(2).lpi#1.dfm(3)} {regs.regs(2).lpi#1.dfm(4)} {regs.regs(2).lpi#1.dfm(5)} {regs.regs(2).lpi#1.dfm(6)} {regs.regs(2).lpi#1.dfm(7)} {regs.regs(2).lpi#1.dfm(8)} {regs.regs(2).lpi#1.dfm(9)} {regs.regs(2).lpi#1.dfm(10)} {regs.regs(2).lpi#1.dfm(11)} {regs.regs(2).lpi#1.dfm(12)} {regs.regs(2).lpi#1.dfm(13)} {regs.regs(2).lpi#1.dfm(14)} {regs.regs(2).lpi#1.dfm(15)} {regs.regs(2).lpi#1.dfm(16)} {regs.regs(2).lpi#1.dfm(17)} {regs.regs(2).lpi#1.dfm(18)} {regs.regs(2).lpi#1.dfm(19)} {regs.regs(2).lpi#1.dfm(20)} {regs.regs(2).lpi#1.dfm(21)} {regs.regs(2).lpi#1.dfm(22)} {regs.regs(2).lpi#1.dfm(23)} {regs.regs(2).lpi#1.dfm(24)} {regs.regs(2).lpi#1.dfm(25)} {regs.regs(2).lpi#1.dfm(26)} {regs.regs(2).lpi#1.dfm(27)} {regs.regs(2).lpi#1.dfm(28)} {regs.regs(2).lpi#1.dfm(29)} {regs.regs(2).lpi#1.dfm(30)} {regs.regs(2).lpi#1.dfm(31)} {regs.regs(2).lpi#1.dfm(32)} {regs.regs(2).lpi#1.dfm(33)} {regs.regs(2).lpi#1.dfm(34)} {regs.regs(2).lpi#1.dfm(35)} {regs.regs(2).lpi#1.dfm(36)} {regs.regs(2).lpi#1.dfm(37)} {regs.regs(2).lpi#1.dfm(38)} {regs.regs(2).lpi#1.dfm(39)} {regs.regs(2).lpi#1.dfm(40)} {regs.regs(2).lpi#1.dfm(41)} {regs.regs(2).lpi#1.dfm(42)} {regs.regs(2).lpi#1.dfm(43)} {regs.regs(2).lpi#1.dfm(44)} {regs.regs(2).lpi#1.dfm(45)} {regs.regs(2).lpi#1.dfm(46)} {regs.regs(2).lpi#1.dfm(47)} {regs.regs(2).lpi#1.dfm(48)} {regs.regs(2).lpi#1.dfm(49)} {regs.regs(2).lpi#1.dfm(50)} {regs.regs(2).lpi#1.dfm(51)} {regs.regs(2).lpi#1.dfm(52)} {regs.regs(2).lpi#1.dfm(53)} {regs.regs(2).lpi#1.dfm(54)} {regs.regs(2).lpi#1.dfm(55)} {regs.regs(2).lpi#1.dfm(56)} {regs.regs(2).lpi#1.dfm(57)} {regs.regs(2).lpi#1.dfm(58)} {regs.regs(2).lpi#1.dfm(59)} {regs.regs(2).lpi#1.dfm(60)} {regs.regs(2).lpi#1.dfm(61)} {regs.regs(2).lpi#1.dfm(62)} {regs.regs(2).lpi#1.dfm(63)} {regs.regs(2).lpi#1.dfm(64)} {regs.regs(2).lpi#1.dfm(65)} {regs.regs(2).lpi#1.dfm(66)} {regs.regs(2).lpi#1.dfm(67)} {regs.regs(2).lpi#1.dfm(68)} {regs.regs(2).lpi#1.dfm(69)} {regs.regs(2).lpi#1.dfm(70)} {regs.regs(2).lpi#1.dfm(71)} {regs.regs(2).lpi#1.dfm(72)} {regs.regs(2).lpi#1.dfm(73)} {regs.regs(2).lpi#1.dfm(74)} {regs.regs(2).lpi#1.dfm(75)} {regs.regs(2).lpi#1.dfm(76)} {regs.regs(2).lpi#1.dfm(77)} {regs.regs(2).lpi#1.dfm(78)} {regs.regs(2).lpi#1.dfm(79)} {regs.regs(2).lpi#1.dfm(80)} {regs.regs(2).lpi#1.dfm(81)} {regs.regs(2).lpi#1.dfm(82)} {regs.regs(2).lpi#1.dfm(83)} {regs.regs(2).lpi#1.dfm(84)} {regs.regs(2).lpi#1.dfm(85)} {regs.regs(2).lpi#1.dfm(86)} {regs.regs(2).lpi#1.dfm(87)} {regs.regs(2).lpi#1.dfm(88)} {regs.regs(2).lpi#1.dfm(89)} -attr xrf 4875 -attr oid 9 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {r(0).sva#1(0)} -attr vt d
+load net {r(0).sva#1(1)} -attr vt d
+load net {r(0).sva#1(2)} -attr vt d
+load net {r(0).sva#1(3)} -attr vt d
+load net {r(0).sva#1(4)} -attr vt d
+load net {r(0).sva#1(5)} -attr vt d
+load net {r(0).sva#1(6)} -attr vt d
+load net {r(0).sva#1(7)} -attr vt d
+load net {r(0).sva#1(8)} -attr vt d
+load net {r(0).sva#1(9)} -attr vt d
+load net {r(0).sva#1(10)} -attr vt d
+load net {r(0).sva#1(11)} -attr vt d
+load net {r(0).sva#1(12)} -attr vt d
+load net {r(0).sva#1(13)} -attr vt d
+load net {r(0).sva#1(14)} -attr vt d
+load net {r(0).sva#1(15)} -attr vt d
+load netBundle {r(0).sva#1} 16 {r(0).sva#1(0)} {r(0).sva#1(1)} {r(0).sva#1(2)} {r(0).sva#1(3)} {r(0).sva#1(4)} {r(0).sva#1(5)} {r(0).sva#1(6)} {r(0).sva#1(7)} {r(0).sva#1(8)} {r(0).sva#1(9)} {r(0).sva#1(10)} {r(0).sva#1(11)} {r(0).sva#1(12)} {r(0).sva#1(13)} {r(0).sva#1(14)} {r(0).sva#1(15)} -attr xrf 4876 -attr oid 10 -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {g(0).sva#1(0)} -attr vt d
+load net {g(0).sva#1(1)} -attr vt d
+load net {g(0).sva#1(2)} -attr vt d
+load net {g(0).sva#1(3)} -attr vt d
+load net {g(0).sva#1(4)} -attr vt d
+load net {g(0).sva#1(5)} -attr vt d
+load net {g(0).sva#1(6)} -attr vt d
+load net {g(0).sva#1(7)} -attr vt d
+load net {g(0).sva#1(8)} -attr vt d
+load net {g(0).sva#1(9)} -attr vt d
+load net {g(0).sva#1(10)} -attr vt d
+load net {g(0).sva#1(11)} -attr vt d
+load net {g(0).sva#1(12)} -attr vt d
+load net {g(0).sva#1(13)} -attr vt d
+load net {g(0).sva#1(14)} -attr vt d
+load net {g(0).sva#1(15)} -attr vt d
+load netBundle {g(0).sva#1} 16 {g(0).sva#1(0)} {g(0).sva#1(1)} {g(0).sva#1(2)} {g(0).sva#1(3)} {g(0).sva#1(4)} {g(0).sva#1(5)} {g(0).sva#1(6)} {g(0).sva#1(7)} {g(0).sva#1(8)} {g(0).sva#1(9)} {g(0).sva#1(10)} {g(0).sva#1(11)} {g(0).sva#1(12)} {g(0).sva#1(13)} {g(0).sva#1(14)} {g(0).sva#1(15)} -attr xrf 4877 -attr oid 11 -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {b(0).sva#1(0)} -attr vt d
+load net {b(0).sva#1(1)} -attr vt d
+load net {b(0).sva#1(2)} -attr vt d
+load net {b(0).sva#1(3)} -attr vt d
+load net {b(0).sva#1(4)} -attr vt d
+load net {b(0).sva#1(5)} -attr vt d
+load net {b(0).sva#1(6)} -attr vt d
+load net {b(0).sva#1(7)} -attr vt d
+load net {b(0).sva#1(8)} -attr vt d
+load net {b(0).sva#1(9)} -attr vt d
+load net {b(0).sva#1(10)} -attr vt d
+load net {b(0).sva#1(11)} -attr vt d
+load net {b(0).sva#1(12)} -attr vt d
+load net {b(0).sva#1(13)} -attr vt d
+load net {b(0).sva#1(14)} -attr vt d
+load net {b(0).sva#1(15)} -attr vt d
+load netBundle {b(0).sva#1} 16 {b(0).sva#1(0)} {b(0).sva#1(1)} {b(0).sva#1(2)} {b(0).sva#1(3)} {b(0).sva#1(4)} {b(0).sva#1(5)} {b(0).sva#1(6)} {b(0).sva#1(7)} {b(0).sva#1(8)} {b(0).sva#1(9)} {b(0).sva#1(10)} {b(0).sva#1(11)} {b(0).sva#1(12)} {b(0).sva#1(13)} {b(0).sva#1(14)} {b(0).sva#1(15)} -attr xrf 4878 -attr oid 12 -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {r(2).sva#1(0)} -attr vt d
+load net {r(2).sva#1(1)} -attr vt d
+load net {r(2).sva#1(2)} -attr vt d
+load net {r(2).sva#1(3)} -attr vt d
+load net {r(2).sva#1(4)} -attr vt d
+load net {r(2).sva#1(5)} -attr vt d
+load net {r(2).sva#1(6)} -attr vt d
+load net {r(2).sva#1(7)} -attr vt d
+load net {r(2).sva#1(8)} -attr vt d
+load net {r(2).sva#1(9)} -attr vt d
+load net {r(2).sva#1(10)} -attr vt d
+load net {r(2).sva#1(11)} -attr vt d
+load net {r(2).sva#1(12)} -attr vt d
+load net {r(2).sva#1(13)} -attr vt d
+load net {r(2).sva#1(14)} -attr vt d
+load net {r(2).sva#1(15)} -attr vt d
+load netBundle {r(2).sva#1} 16 {r(2).sva#1(0)} {r(2).sva#1(1)} {r(2).sva#1(2)} {r(2).sva#1(3)} {r(2).sva#1(4)} {r(2).sva#1(5)} {r(2).sva#1(6)} {r(2).sva#1(7)} {r(2).sva#1(8)} {r(2).sva#1(9)} {r(2).sva#1(10)} {r(2).sva#1(11)} {r(2).sva#1(12)} {r(2).sva#1(13)} {r(2).sva#1(14)} {r(2).sva#1(15)} -attr xrf 4879 -attr oid 13 -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {g(2).sva#1(0)} -attr vt d
+load net {g(2).sva#1(1)} -attr vt d
+load net {g(2).sva#1(2)} -attr vt d
+load net {g(2).sva#1(3)} -attr vt d
+load net {g(2).sva#1(4)} -attr vt d
+load net {g(2).sva#1(5)} -attr vt d
+load net {g(2).sva#1(6)} -attr vt d
+load net {g(2).sva#1(7)} -attr vt d
+load net {g(2).sva#1(8)} -attr vt d
+load net {g(2).sva#1(9)} -attr vt d
+load net {g(2).sva#1(10)} -attr vt d
+load net {g(2).sva#1(11)} -attr vt d
+load net {g(2).sva#1(12)} -attr vt d
+load net {g(2).sva#1(13)} -attr vt d
+load net {g(2).sva#1(14)} -attr vt d
+load net {g(2).sva#1(15)} -attr vt d
+load netBundle {g(2).sva#1} 16 {g(2).sva#1(0)} {g(2).sva#1(1)} {g(2).sva#1(2)} {g(2).sva#1(3)} {g(2).sva#1(4)} {g(2).sva#1(5)} {g(2).sva#1(6)} {g(2).sva#1(7)} {g(2).sva#1(8)} {g(2).sva#1(9)} {g(2).sva#1(10)} {g(2).sva#1(11)} {g(2).sva#1(12)} {g(2).sva#1(13)} {g(2).sva#1(14)} {g(2).sva#1(15)} -attr xrf 4880 -attr oid 14 -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {b(2).sva#1(0)} -attr vt d
+load net {b(2).sva#1(1)} -attr vt d
+load net {b(2).sva#1(2)} -attr vt d
+load net {b(2).sva#1(3)} -attr vt d
+load net {b(2).sva#1(4)} -attr vt d
+load net {b(2).sva#1(5)} -attr vt d
+load net {b(2).sva#1(6)} -attr vt d
+load net {b(2).sva#1(7)} -attr vt d
+load net {b(2).sva#1(8)} -attr vt d
+load net {b(2).sva#1(9)} -attr vt d
+load net {b(2).sva#1(10)} -attr vt d
+load net {b(2).sva#1(11)} -attr vt d
+load net {b(2).sva#1(12)} -attr vt d
+load net {b(2).sva#1(13)} -attr vt d
+load net {b(2).sva#1(14)} -attr vt d
+load net {b(2).sva#1(15)} -attr vt d
+load netBundle {b(2).sva#1} 16 {b(2).sva#1(0)} {b(2).sva#1(1)} {b(2).sva#1(2)} {b(2).sva#1(3)} {b(2).sva#1(4)} {b(2).sva#1(5)} {b(2).sva#1(6)} {b(2).sva#1(7)} {b(2).sva#1(8)} {b(2).sva#1(9)} {b(2).sva#1(10)} {b(2).sva#1(11)} {b(2).sva#1(12)} {b(2).sva#1(13)} {b(2).sva#1(14)} {b(2).sva#1(15)} -attr xrf 4881 -attr oid 15 -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {i#6.sva#1(0)} -attr vt d
+load net {i#6.sva#1(1)} -attr vt d
+load netBundle {i#6.sva#1} 2 {i#6.sva#1(0)} {i#6.sva#1(1)} -attr xrf 4882 -attr oid 16 -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {FRAME:mul#2.itm#1(0)} -attr vt d
+load net {FRAME:mul#2.itm#1(1)} -attr vt d
+load net {FRAME:mul#2.itm#1(2)} -attr vt d
+load net {FRAME:mul#2.itm#1(3)} -attr vt d
+load net {FRAME:mul#2.itm#1(4)} -attr vt d
+load net {FRAME:mul#2.itm#1(5)} -attr vt d
+load net {FRAME:mul#2.itm#1(6)} -attr vt d
+load net {FRAME:mul#2.itm#1(7)} -attr vt d
+load net {FRAME:mul#2.itm#1(8)} -attr vt d
+load net {FRAME:mul#2.itm#1(9)} -attr vt d
+load net {FRAME:mul#2.itm#1(10)} -attr vt d
+load netBundle {FRAME:mul#2.itm#1} 11 {FRAME:mul#2.itm#1(0)} {FRAME:mul#2.itm#1(1)} {FRAME:mul#2.itm#1(2)} {FRAME:mul#2.itm#1(3)} {FRAME:mul#2.itm#1(4)} {FRAME:mul#2.itm#1(5)} {FRAME:mul#2.itm#1(6)} {FRAME:mul#2.itm#1(7)} {FRAME:mul#2.itm#1(8)} {FRAME:mul#2.itm#1(9)} {FRAME:mul#2.itm#1(10)} -attr xrf 4883 -attr oid 17 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#3.itm#1(0)} -attr vt d
+load net {FRAME:mul#3.itm#1(1)} -attr vt d
+load net {FRAME:mul#3.itm#1(2)} -attr vt d
+load net {FRAME:mul#3.itm#1(3)} -attr vt d
+load net {FRAME:mul#3.itm#1(4)} -attr vt d
+load net {FRAME:mul#3.itm#1(5)} -attr vt d
+load net {FRAME:mul#3.itm#1(6)} -attr vt d
+load net {FRAME:mul#3.itm#1(7)} -attr vt d
+load net {FRAME:mul#3.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#3.itm#1} 9 {FRAME:mul#3.itm#1(0)} {FRAME:mul#3.itm#1(1)} {FRAME:mul#3.itm#1(2)} {FRAME:mul#3.itm#1(3)} {FRAME:mul#3.itm#1(4)} {FRAME:mul#3.itm#1(5)} {FRAME:mul#3.itm#1(6)} {FRAME:mul#3.itm#1(7)} {FRAME:mul#3.itm#1(8)} -attr xrf 4884 -attr oid 18 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {green:slc(green#2.sg1).itm#1(0)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(1)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(2)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(3)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(4)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(5)} -attr vt d
+load netBundle {green:slc(green#2.sg1).itm#1} 6 {green:slc(green#2.sg1).itm#1(0)} {green:slc(green#2.sg1).itm#1(1)} {green:slc(green#2.sg1).itm#1(2)} {green:slc(green#2.sg1).itm#1(3)} {green:slc(green#2.sg1).itm#1(4)} {green:slc(green#2.sg1).itm#1(5)} -attr xrf 4885 -attr oid 19 -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {FRAME:acc#18.itm#1(0)} -attr vt d
+load net {FRAME:acc#18.itm#1(1)} -attr vt d
+load net {FRAME:acc#18.itm#1(2)} -attr vt d
+load net {FRAME:acc#18.itm#1(3)} -attr vt d
+load net {FRAME:acc#18.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#18.itm#1} 5 {FRAME:acc#18.itm#1(0)} {FRAME:acc#18.itm#1(1)} {FRAME:acc#18.itm#1(2)} {FRAME:acc#18.itm#1(3)} {FRAME:acc#18.itm#1(4)} -attr xrf 4886 -attr oid 20 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:mul#4.itm#1(0)} -attr vt d
+load net {FRAME:mul#4.itm#1(1)} -attr vt d
+load net {FRAME:mul#4.itm#1(2)} -attr vt d
+load net {FRAME:mul#4.itm#1(3)} -attr vt d
+load net {FRAME:mul#4.itm#1(4)} -attr vt d
+load net {FRAME:mul#4.itm#1(5)} -attr vt d
+load net {FRAME:mul#4.itm#1(6)} -attr vt d
+load net {FRAME:mul#4.itm#1(7)} -attr vt d
+load net {FRAME:mul#4.itm#1(8)} -attr vt d
+load net {FRAME:mul#4.itm#1(9)} -attr vt d
+load net {FRAME:mul#4.itm#1(10)} -attr vt d
+load netBundle {FRAME:mul#4.itm#1} 11 {FRAME:mul#4.itm#1(0)} {FRAME:mul#4.itm#1(1)} {FRAME:mul#4.itm#1(2)} {FRAME:mul#4.itm#1(3)} {FRAME:mul#4.itm#1(4)} {FRAME:mul#4.itm#1(5)} {FRAME:mul#4.itm#1(6)} {FRAME:mul#4.itm#1(7)} {FRAME:mul#4.itm#1(8)} {FRAME:mul#4.itm#1(9)} {FRAME:mul#4.itm#1(10)} -attr xrf 4887 -attr oid 21 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#5.itm#1(0)} -attr vt d
+load net {FRAME:mul#5.itm#1(1)} -attr vt d
+load net {FRAME:mul#5.itm#1(2)} -attr vt d
+load net {FRAME:mul#5.itm#1(3)} -attr vt d
+load net {FRAME:mul#5.itm#1(4)} -attr vt d
+load net {FRAME:mul#5.itm#1(5)} -attr vt d
+load net {FRAME:mul#5.itm#1(6)} -attr vt d
+load net {FRAME:mul#5.itm#1(7)} -attr vt d
+load net {FRAME:mul#5.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#5.itm#1} 9 {FRAME:mul#5.itm#1(0)} {FRAME:mul#5.itm#1(1)} {FRAME:mul#5.itm#1(2)} {FRAME:mul#5.itm#1(3)} {FRAME:mul#5.itm#1(4)} {FRAME:mul#5.itm#1(5)} {FRAME:mul#5.itm#1(6)} {FRAME:mul#5.itm#1(7)} {FRAME:mul#5.itm#1(8)} -attr xrf 4888 -attr oid 22 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(0)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(1)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(2)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(3)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(4)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(5)} -attr vt d
+load netBundle {blue:slc(blue#2.sg1).itm#1} 6 {blue:slc(blue#2.sg1).itm#1(0)} {blue:slc(blue#2.sg1).itm#1(1)} {blue:slc(blue#2.sg1).itm#1(2)} {blue:slc(blue#2.sg1).itm#1(3)} {blue:slc(blue#2.sg1).itm#1(4)} {blue:slc(blue#2.sg1).itm#1(5)} -attr xrf 4889 -attr oid 23 -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {FRAME:acc#30.itm#1(0)} -attr vt d
+load net {FRAME:acc#30.itm#1(1)} -attr vt d
+load net {FRAME:acc#30.itm#1(2)} -attr vt d
+load net {FRAME:acc#30.itm#1(3)} -attr vt d
+load net {FRAME:acc#30.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#30.itm#1} 5 {FRAME:acc#30.itm#1(0)} {FRAME:acc#30.itm#1(1)} {FRAME:acc#30.itm#1(2)} {FRAME:acc#30.itm#1(3)} {FRAME:acc#30.itm#1(4)} -attr xrf 4890 -attr oid 24 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:mul#1.itm#1(0)} -attr vt d
+load net {FRAME:mul#1.itm#1(1)} -attr vt d
+load net {FRAME:mul#1.itm#1(2)} -attr vt d
+load net {FRAME:mul#1.itm#1(3)} -attr vt d
+load net {FRAME:mul#1.itm#1(4)} -attr vt d
+load net {FRAME:mul#1.itm#1(5)} -attr vt d
+load net {FRAME:mul#1.itm#1(6)} -attr vt d
+load net {FRAME:mul#1.itm#1(7)} -attr vt d
+load net {FRAME:mul#1.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#1.itm#1} 9 {FRAME:mul#1.itm#1(0)} {FRAME:mul#1.itm#1(1)} {FRAME:mul#1.itm#1(2)} {FRAME:mul#1.itm#1(3)} {FRAME:mul#1.itm#1(4)} {FRAME:mul#1.itm#1(5)} {FRAME:mul#1.itm#1(6)} {FRAME:mul#1.itm#1(7)} {FRAME:mul#1.itm#1(8)} -attr xrf 4891 -attr oid 25 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {red:slc(red#2.sg1).itm#1(0)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(1)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(2)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(3)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(4)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(5)} -attr vt d
+load netBundle {red:slc(red#2.sg1).itm#1} 6 {red:slc(red#2.sg1).itm#1(0)} {red:slc(red#2.sg1).itm#1(1)} {red:slc(red#2.sg1).itm#1(2)} {red:slc(red#2.sg1).itm#1(3)} {red:slc(red#2.sg1).itm#1(4)} {red:slc(red#2.sg1).itm#1(5)} -attr xrf 4892 -attr oid 26 -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {FRAME:acc#37.itm#1(0)} -attr vt d
+load net {FRAME:acc#37.itm#1(1)} -attr vt d
+load net {FRAME:acc#37.itm#1(2)} -attr vt d
+load net {FRAME:acc#37.itm#1(3)} -attr vt d
+load net {FRAME:acc#37.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#37.itm#1} 5 {FRAME:acc#37.itm#1(0)} {FRAME:acc#37.itm#1(1)} {FRAME:acc#37.itm#1(2)} {FRAME:acc#37.itm#1(3)} {FRAME:acc#37.itm#1(4)} -attr xrf 4893 -attr oid 27 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#41.itm#1.sg2(0)} -attr vt d
+load net {FRAME:acc#41.itm#1.sg2(1)} -attr vt d
+load netBundle {FRAME:acc#41.itm#1.sg2} 2 {FRAME:acc#41.itm#1.sg2(0)} {FRAME:acc#41.itm#1.sg2(1)} -attr xrf 4894 -attr oid 28 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg2}
+load net {FRAME:acc#41.itm#1.sg1(0)} -attr vt d
+load net {FRAME:acc#41.itm#1.sg1(1)} -attr vt d
+load netBundle {FRAME:acc#41.itm#1.sg1} 2 {FRAME:acc#41.itm#1.sg1(0)} {FRAME:acc#41.itm#1.sg1(1)} -attr xrf 4895 -attr oid 29 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg1}
+load net {FRAME:acc#41.itm#3(0)} -attr vt d
+load net {FRAME:acc#41.itm#3(1)} -attr vt d
+load net {FRAME:acc#41.itm#3(2)} -attr vt d
+load net {FRAME:acc#41.itm#3(3)} -attr vt d
+load net {FRAME:acc#41.itm#3(4)} -attr vt d
+load net {FRAME:acc#41.itm#3(5)} -attr vt d
+load netBundle {FRAME:acc#41.itm#3} 6 {FRAME:acc#41.itm#3(0)} {FRAME:acc#41.itm#3(1)} {FRAME:acc#41.itm#3(2)} {FRAME:acc#41.itm#3(3)} {FRAME:acc#41.itm#3(4)} {FRAME:acc#41.itm#3(5)} -attr xrf 4896 -attr oid 30 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:p#1.sva#1(0)} -attr vt d
+load net {FRAME:p#1.sva#1(1)} -attr vt d
+load net {FRAME:p#1.sva#1(2)} -attr vt d
+load net {FRAME:p#1.sva#1(3)} -attr vt d
+load net {FRAME:p#1.sva#1(4)} -attr vt d
+load net {FRAME:p#1.sva#1(5)} -attr vt d
+load net {FRAME:p#1.sva#1(6)} -attr vt d
+load net {FRAME:p#1.sva#1(7)} -attr vt d
+load net {FRAME:p#1.sva#1(8)} -attr vt d
+load net {FRAME:p#1.sva#1(9)} -attr vt d
+load net {FRAME:p#1.sva#1(10)} -attr vt d
+load net {FRAME:p#1.sva#1(11)} -attr vt d
+load net {FRAME:p#1.sva#1(12)} -attr vt d
+load net {FRAME:p#1.sva#1(13)} -attr vt d
+load net {FRAME:p#1.sva#1(14)} -attr vt d
+load net {FRAME:p#1.sva#1(15)} -attr vt d
+load net {FRAME:p#1.sva#1(16)} -attr vt d
+load net {FRAME:p#1.sva#1(17)} -attr vt d
+load net {FRAME:p#1.sva#1(18)} -attr vt d
+load netBundle {FRAME:p#1.sva#1} 19 {FRAME:p#1.sva#1(0)} {FRAME:p#1.sva#1(1)} {FRAME:p#1.sva#1(2)} {FRAME:p#1.sva#1(3)} {FRAME:p#1.sva#1(4)} {FRAME:p#1.sva#1(5)} {FRAME:p#1.sva#1(6)} {FRAME:p#1.sva#1(7)} {FRAME:p#1.sva#1(8)} {FRAME:p#1.sva#1(9)} {FRAME:p#1.sva#1(10)} {FRAME:p#1.sva#1(11)} {FRAME:p#1.sva#1(12)} {FRAME:p#1.sva#1(13)} {FRAME:p#1.sva#1(14)} {FRAME:p#1.sva#1(15)} {FRAME:p#1.sva#1(16)} {FRAME:p#1.sva#1(17)} {FRAME:p#1.sva#1(18)} -attr xrf 4897 -attr oid 31 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:acc#3.psp.sva(0)} -attr vt d
+load net {FRAME:acc#3.psp.sva(1)} -attr vt d
+load net {FRAME:acc#3.psp.sva(2)} -attr vt d
+load net {FRAME:acc#3.psp.sva(3)} -attr vt d
+load net {FRAME:acc#3.psp.sva(4)} -attr vt d
+load net {FRAME:acc#3.psp.sva(5)} -attr vt d
+load net {FRAME:acc#3.psp.sva(6)} -attr vt d
+load net {FRAME:acc#3.psp.sva(7)} -attr vt d
+load net {FRAME:acc#3.psp.sva(8)} -attr vt d
+load net {FRAME:acc#3.psp.sva(9)} -attr vt d
+load net {FRAME:acc#3.psp.sva(10)} -attr vt d
+load net {FRAME:acc#3.psp.sva(11)} -attr vt d
+load netBundle {FRAME:acc#3.psp.sva} 12 {FRAME:acc#3.psp.sva(0)} {FRAME:acc#3.psp.sva(1)} {FRAME:acc#3.psp.sva(2)} {FRAME:acc#3.psp.sva(3)} {FRAME:acc#3.psp.sva(4)} {FRAME:acc#3.psp.sva(5)} {FRAME:acc#3.psp.sva(6)} {FRAME:acc#3.psp.sva(7)} {FRAME:acc#3.psp.sva(8)} {FRAME:acc#3.psp.sva(9)} {FRAME:acc#3.psp.sva(10)} {FRAME:acc#3.psp.sva(11)} -attr xrf 4898 -attr oid 32 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#4.psp.sva(0)} -attr vt d
+load net {FRAME:acc#4.psp.sva(1)} -attr vt d
+load net {FRAME:acc#4.psp.sva(2)} -attr vt d
+load net {FRAME:acc#4.psp.sva(3)} -attr vt d
+load net {FRAME:acc#4.psp.sva(4)} -attr vt d
+load net {FRAME:acc#4.psp.sva(5)} -attr vt d
+load net {FRAME:acc#4.psp.sva(6)} -attr vt d
+load net {FRAME:acc#4.psp.sva(7)} -attr vt d
+load net {FRAME:acc#4.psp.sva(8)} -attr vt d
+load net {FRAME:acc#4.psp.sva(9)} -attr vt d
+load net {FRAME:acc#4.psp.sva(10)} -attr vt d
+load net {FRAME:acc#4.psp.sva(11)} -attr vt d
+load netBundle {FRAME:acc#4.psp.sva} 12 {FRAME:acc#4.psp.sva(0)} {FRAME:acc#4.psp.sva(1)} {FRAME:acc#4.psp.sva(2)} {FRAME:acc#4.psp.sva(3)} {FRAME:acc#4.psp.sva(4)} {FRAME:acc#4.psp.sva(5)} {FRAME:acc#4.psp.sva(6)} {FRAME:acc#4.psp.sva(7)} {FRAME:acc#4.psp.sva(8)} {FRAME:acc#4.psp.sva(9)} {FRAME:acc#4.psp.sva(10)} {FRAME:acc#4.psp.sva(11)} -attr xrf 4899 -attr oid 33 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {i#6.sva#2(0)} -attr vt d
+load net {i#6.sva#2(1)} -attr vt d
+load netBundle {i#6.sva#2} 2 {i#6.sva#2(0)} {i#6.sva#2(1)} -attr xrf 4900 -attr oid 34 -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.lpi#1.dfm(0)} -attr vt d
+load net {i#6.lpi#1.dfm(1)} -attr vt d
+load netBundle {i#6.lpi#1.dfm} 2 {i#6.lpi#1.dfm(0)} {i#6.lpi#1.dfm(1)} -attr xrf 4901 -attr oid 35 -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm:mx0} 90 {regs.regs(2).lpi#1.dfm:mx0(0)} {regs.regs(2).lpi#1.dfm:mx0(1)} {regs.regs(2).lpi#1.dfm:mx0(2)} {regs.regs(2).lpi#1.dfm:mx0(3)} {regs.regs(2).lpi#1.dfm:mx0(4)} {regs.regs(2).lpi#1.dfm:mx0(5)} {regs.regs(2).lpi#1.dfm:mx0(6)} {regs.regs(2).lpi#1.dfm:mx0(7)} {regs.regs(2).lpi#1.dfm:mx0(8)} {regs.regs(2).lpi#1.dfm:mx0(9)} {regs.regs(2).lpi#1.dfm:mx0(10)} {regs.regs(2).lpi#1.dfm:mx0(11)} {regs.regs(2).lpi#1.dfm:mx0(12)} {regs.regs(2).lpi#1.dfm:mx0(13)} {regs.regs(2).lpi#1.dfm:mx0(14)} {regs.regs(2).lpi#1.dfm:mx0(15)} {regs.regs(2).lpi#1.dfm:mx0(16)} {regs.regs(2).lpi#1.dfm:mx0(17)} {regs.regs(2).lpi#1.dfm:mx0(18)} {regs.regs(2).lpi#1.dfm:mx0(19)} {regs.regs(2).lpi#1.dfm:mx0(20)} {regs.regs(2).lpi#1.dfm:mx0(21)} {regs.regs(2).lpi#1.dfm:mx0(22)} {regs.regs(2).lpi#1.dfm:mx0(23)} {regs.regs(2).lpi#1.dfm:mx0(24)} {regs.regs(2).lpi#1.dfm:mx0(25)} {regs.regs(2).lpi#1.dfm:mx0(26)} {regs.regs(2).lpi#1.dfm:mx0(27)} {regs.regs(2).lpi#1.dfm:mx0(28)} {regs.regs(2).lpi#1.dfm:mx0(29)} {regs.regs(2).lpi#1.dfm:mx0(30)} {regs.regs(2).lpi#1.dfm:mx0(31)} {regs.regs(2).lpi#1.dfm:mx0(32)} {regs.regs(2).lpi#1.dfm:mx0(33)} {regs.regs(2).lpi#1.dfm:mx0(34)} {regs.regs(2).lpi#1.dfm:mx0(35)} {regs.regs(2).lpi#1.dfm:mx0(36)} {regs.regs(2).lpi#1.dfm:mx0(37)} {regs.regs(2).lpi#1.dfm:mx0(38)} {regs.regs(2).lpi#1.dfm:mx0(39)} {regs.regs(2).lpi#1.dfm:mx0(40)} {regs.regs(2).lpi#1.dfm:mx0(41)} {regs.regs(2).lpi#1.dfm:mx0(42)} {regs.regs(2).lpi#1.dfm:mx0(43)} {regs.regs(2).lpi#1.dfm:mx0(44)} {regs.regs(2).lpi#1.dfm:mx0(45)} {regs.regs(2).lpi#1.dfm:mx0(46)} {regs.regs(2).lpi#1.dfm:mx0(47)} {regs.regs(2).lpi#1.dfm:mx0(48)} {regs.regs(2).lpi#1.dfm:mx0(49)} {regs.regs(2).lpi#1.dfm:mx0(50)} {regs.regs(2).lpi#1.dfm:mx0(51)} {regs.regs(2).lpi#1.dfm:mx0(52)} {regs.regs(2).lpi#1.dfm:mx0(53)} {regs.regs(2).lpi#1.dfm:mx0(54)} {regs.regs(2).lpi#1.dfm:mx0(55)} {regs.regs(2).lpi#1.dfm:mx0(56)} {regs.regs(2).lpi#1.dfm:mx0(57)} {regs.regs(2).lpi#1.dfm:mx0(58)} {regs.regs(2).lpi#1.dfm:mx0(59)} {regs.regs(2).lpi#1.dfm:mx0(60)} {regs.regs(2).lpi#1.dfm:mx0(61)} {regs.regs(2).lpi#1.dfm:mx0(62)} {regs.regs(2).lpi#1.dfm:mx0(63)} {regs.regs(2).lpi#1.dfm:mx0(64)} {regs.regs(2).lpi#1.dfm:mx0(65)} {regs.regs(2).lpi#1.dfm:mx0(66)} {regs.regs(2).lpi#1.dfm:mx0(67)} {regs.regs(2).lpi#1.dfm:mx0(68)} {regs.regs(2).lpi#1.dfm:mx0(69)} {regs.regs(2).lpi#1.dfm:mx0(70)} {regs.regs(2).lpi#1.dfm:mx0(71)} {regs.regs(2).lpi#1.dfm:mx0(72)} {regs.regs(2).lpi#1.dfm:mx0(73)} {regs.regs(2).lpi#1.dfm:mx0(74)} {regs.regs(2).lpi#1.dfm:mx0(75)} {regs.regs(2).lpi#1.dfm:mx0(76)} {regs.regs(2).lpi#1.dfm:mx0(77)} {regs.regs(2).lpi#1.dfm:mx0(78)} {regs.regs(2).lpi#1.dfm:mx0(79)} {regs.regs(2).lpi#1.dfm:mx0(80)} {regs.regs(2).lpi#1.dfm:mx0(81)} {regs.regs(2).lpi#1.dfm:mx0(82)} {regs.regs(2).lpi#1.dfm:mx0(83)} {regs.regs(2).lpi#1.dfm:mx0(84)} {regs.regs(2).lpi#1.dfm:mx0(85)} {regs.regs(2).lpi#1.dfm:mx0(86)} {regs.regs(2).lpi#1.dfm:mx0(87)} {regs.regs(2).lpi#1.dfm:mx0(88)} {regs.regs(2).lpi#1.dfm:mx0(89)} -attr xrf 4902 -attr oid 36 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(1).sva.dfm:mx0} 90 {regs.regs(1).sva.dfm:mx0(0)} {regs.regs(1).sva.dfm:mx0(1)} {regs.regs(1).sva.dfm:mx0(2)} {regs.regs(1).sva.dfm:mx0(3)} {regs.regs(1).sva.dfm:mx0(4)} {regs.regs(1).sva.dfm:mx0(5)} {regs.regs(1).sva.dfm:mx0(6)} {regs.regs(1).sva.dfm:mx0(7)} {regs.regs(1).sva.dfm:mx0(8)} {regs.regs(1).sva.dfm:mx0(9)} {regs.regs(1).sva.dfm:mx0(10)} {regs.regs(1).sva.dfm:mx0(11)} {regs.regs(1).sva.dfm:mx0(12)} {regs.regs(1).sva.dfm:mx0(13)} {regs.regs(1).sva.dfm:mx0(14)} {regs.regs(1).sva.dfm:mx0(15)} {regs.regs(1).sva.dfm:mx0(16)} {regs.regs(1).sva.dfm:mx0(17)} {regs.regs(1).sva.dfm:mx0(18)} {regs.regs(1).sva.dfm:mx0(19)} {regs.regs(1).sva.dfm:mx0(20)} {regs.regs(1).sva.dfm:mx0(21)} {regs.regs(1).sva.dfm:mx0(22)} {regs.regs(1).sva.dfm:mx0(23)} {regs.regs(1).sva.dfm:mx0(24)} {regs.regs(1).sva.dfm:mx0(25)} {regs.regs(1).sva.dfm:mx0(26)} {regs.regs(1).sva.dfm:mx0(27)} {regs.regs(1).sva.dfm:mx0(28)} {regs.regs(1).sva.dfm:mx0(29)} {regs.regs(1).sva.dfm:mx0(30)} {regs.regs(1).sva.dfm:mx0(31)} {regs.regs(1).sva.dfm:mx0(32)} {regs.regs(1).sva.dfm:mx0(33)} {regs.regs(1).sva.dfm:mx0(34)} {regs.regs(1).sva.dfm:mx0(35)} {regs.regs(1).sva.dfm:mx0(36)} {regs.regs(1).sva.dfm:mx0(37)} {regs.regs(1).sva.dfm:mx0(38)} {regs.regs(1).sva.dfm:mx0(39)} {regs.regs(1).sva.dfm:mx0(40)} {regs.regs(1).sva.dfm:mx0(41)} {regs.regs(1).sva.dfm:mx0(42)} {regs.regs(1).sva.dfm:mx0(43)} {regs.regs(1).sva.dfm:mx0(44)} {regs.regs(1).sva.dfm:mx0(45)} {regs.regs(1).sva.dfm:mx0(46)} {regs.regs(1).sva.dfm:mx0(47)} {regs.regs(1).sva.dfm:mx0(48)} {regs.regs(1).sva.dfm:mx0(49)} {regs.regs(1).sva.dfm:mx0(50)} {regs.regs(1).sva.dfm:mx0(51)} {regs.regs(1).sva.dfm:mx0(52)} {regs.regs(1).sva.dfm:mx0(53)} {regs.regs(1).sva.dfm:mx0(54)} {regs.regs(1).sva.dfm:mx0(55)} {regs.regs(1).sva.dfm:mx0(56)} {regs.regs(1).sva.dfm:mx0(57)} {regs.regs(1).sva.dfm:mx0(58)} {regs.regs(1).sva.dfm:mx0(59)} {regs.regs(1).sva.dfm:mx0(60)} {regs.regs(1).sva.dfm:mx0(61)} {regs.regs(1).sva.dfm:mx0(62)} {regs.regs(1).sva.dfm:mx0(63)} {regs.regs(1).sva.dfm:mx0(64)} {regs.regs(1).sva.dfm:mx0(65)} {regs.regs(1).sva.dfm:mx0(66)} {regs.regs(1).sva.dfm:mx0(67)} {regs.regs(1).sva.dfm:mx0(68)} {regs.regs(1).sva.dfm:mx0(69)} {regs.regs(1).sva.dfm:mx0(70)} {regs.regs(1).sva.dfm:mx0(71)} {regs.regs(1).sva.dfm:mx0(72)} {regs.regs(1).sva.dfm:mx0(73)} {regs.regs(1).sva.dfm:mx0(74)} {regs.regs(1).sva.dfm:mx0(75)} {regs.regs(1).sva.dfm:mx0(76)} {regs.regs(1).sva.dfm:mx0(77)} {regs.regs(1).sva.dfm:mx0(78)} {regs.regs(1).sva.dfm:mx0(79)} {regs.regs(1).sva.dfm:mx0(80)} {regs.regs(1).sva.dfm:mx0(81)} {regs.regs(1).sva.dfm:mx0(82)} {regs.regs(1).sva.dfm:mx0(83)} {regs.regs(1).sva.dfm:mx0(84)} {regs.regs(1).sva.dfm:mx0(85)} {regs.regs(1).sva.dfm:mx0(86)} {regs.regs(1).sva.dfm:mx0(87)} {regs.regs(1).sva.dfm:mx0(88)} {regs.regs(1).sva.dfm:mx0(89)} -attr xrf 4903 -attr oid 37 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(0).sva.dfm:mx0} 90 {regs.regs(0).sva.dfm:mx0(0)} {regs.regs(0).sva.dfm:mx0(1)} {regs.regs(0).sva.dfm:mx0(2)} {regs.regs(0).sva.dfm:mx0(3)} {regs.regs(0).sva.dfm:mx0(4)} {regs.regs(0).sva.dfm:mx0(5)} {regs.regs(0).sva.dfm:mx0(6)} {regs.regs(0).sva.dfm:mx0(7)} {regs.regs(0).sva.dfm:mx0(8)} {regs.regs(0).sva.dfm:mx0(9)} {regs.regs(0).sva.dfm:mx0(10)} {regs.regs(0).sva.dfm:mx0(11)} {regs.regs(0).sva.dfm:mx0(12)} {regs.regs(0).sva.dfm:mx0(13)} {regs.regs(0).sva.dfm:mx0(14)} {regs.regs(0).sva.dfm:mx0(15)} {regs.regs(0).sva.dfm:mx0(16)} {regs.regs(0).sva.dfm:mx0(17)} {regs.regs(0).sva.dfm:mx0(18)} {regs.regs(0).sva.dfm:mx0(19)} {regs.regs(0).sva.dfm:mx0(20)} {regs.regs(0).sva.dfm:mx0(21)} {regs.regs(0).sva.dfm:mx0(22)} {regs.regs(0).sva.dfm:mx0(23)} {regs.regs(0).sva.dfm:mx0(24)} {regs.regs(0).sva.dfm:mx0(25)} {regs.regs(0).sva.dfm:mx0(26)} {regs.regs(0).sva.dfm:mx0(27)} {regs.regs(0).sva.dfm:mx0(28)} {regs.regs(0).sva.dfm:mx0(29)} {regs.regs(0).sva.dfm:mx0(30)} {regs.regs(0).sva.dfm:mx0(31)} {regs.regs(0).sva.dfm:mx0(32)} {regs.regs(0).sva.dfm:mx0(33)} {regs.regs(0).sva.dfm:mx0(34)} {regs.regs(0).sva.dfm:mx0(35)} {regs.regs(0).sva.dfm:mx0(36)} {regs.regs(0).sva.dfm:mx0(37)} {regs.regs(0).sva.dfm:mx0(38)} {regs.regs(0).sva.dfm:mx0(39)} {regs.regs(0).sva.dfm:mx0(40)} {regs.regs(0).sva.dfm:mx0(41)} {regs.regs(0).sva.dfm:mx0(42)} {regs.regs(0).sva.dfm:mx0(43)} {regs.regs(0).sva.dfm:mx0(44)} {regs.regs(0).sva.dfm:mx0(45)} {regs.regs(0).sva.dfm:mx0(46)} {regs.regs(0).sva.dfm:mx0(47)} {regs.regs(0).sva.dfm:mx0(48)} {regs.regs(0).sva.dfm:mx0(49)} {regs.regs(0).sva.dfm:mx0(50)} {regs.regs(0).sva.dfm:mx0(51)} {regs.regs(0).sva.dfm:mx0(52)} {regs.regs(0).sva.dfm:mx0(53)} {regs.regs(0).sva.dfm:mx0(54)} {regs.regs(0).sva.dfm:mx0(55)} {regs.regs(0).sva.dfm:mx0(56)} {regs.regs(0).sva.dfm:mx0(57)} {regs.regs(0).sva.dfm:mx0(58)} {regs.regs(0).sva.dfm:mx0(59)} {regs.regs(0).sva.dfm:mx0(60)} {regs.regs(0).sva.dfm:mx0(61)} {regs.regs(0).sva.dfm:mx0(62)} {regs.regs(0).sva.dfm:mx0(63)} {regs.regs(0).sva.dfm:mx0(64)} {regs.regs(0).sva.dfm:mx0(65)} {regs.regs(0).sva.dfm:mx0(66)} {regs.regs(0).sva.dfm:mx0(67)} {regs.regs(0).sva.dfm:mx0(68)} {regs.regs(0).sva.dfm:mx0(69)} {regs.regs(0).sva.dfm:mx0(70)} {regs.regs(0).sva.dfm:mx0(71)} {regs.regs(0).sva.dfm:mx0(72)} {regs.regs(0).sva.dfm:mx0(73)} {regs.regs(0).sva.dfm:mx0(74)} {regs.regs(0).sva.dfm:mx0(75)} {regs.regs(0).sva.dfm:mx0(76)} {regs.regs(0).sva.dfm:mx0(77)} {regs.regs(0).sva.dfm:mx0(78)} {regs.regs(0).sva.dfm:mx0(79)} {regs.regs(0).sva.dfm:mx0(80)} {regs.regs(0).sva.dfm:mx0(81)} {regs.regs(0).sva.dfm:mx0(82)} {regs.regs(0).sva.dfm:mx0(83)} {regs.regs(0).sva.dfm:mx0(84)} {regs.regs(0).sva.dfm:mx0(85)} {regs.regs(0).sva.dfm:mx0(86)} {regs.regs(0).sva.dfm:mx0(87)} {regs.regs(0).sva.dfm:mx0(88)} {regs.regs(0).sva.dfm:mx0(89)} -attr xrf 4904 -attr oid 38 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {FRAME:p#1.lpi#1.dfm(0)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(1)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(2)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(3)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(4)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(5)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(6)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(7)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(8)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(9)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(10)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(11)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(12)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(13)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(14)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(15)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(16)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(17)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(18)} -attr vt d
+load netBundle {FRAME:p#1.lpi#1.dfm} 19 {FRAME:p#1.lpi#1.dfm(0)} {FRAME:p#1.lpi#1.dfm(1)} {FRAME:p#1.lpi#1.dfm(2)} {FRAME:p#1.lpi#1.dfm(3)} {FRAME:p#1.lpi#1.dfm(4)} {FRAME:p#1.lpi#1.dfm(5)} {FRAME:p#1.lpi#1.dfm(6)} {FRAME:p#1.lpi#1.dfm(7)} {FRAME:p#1.lpi#1.dfm(8)} {FRAME:p#1.lpi#1.dfm(9)} {FRAME:p#1.lpi#1.dfm(10)} {FRAME:p#1.lpi#1.dfm(11)} {FRAME:p#1.lpi#1.dfm(12)} {FRAME:p#1.lpi#1.dfm(13)} {FRAME:p#1.lpi#1.dfm(14)} {FRAME:p#1.lpi#1.dfm(15)} {FRAME:p#1.lpi#1.dfm(16)} {FRAME:p#1.lpi#1.dfm(17)} {FRAME:p#1.lpi#1.dfm(18)} -attr xrf 4905 -attr oid 39 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {acc.imod.sva(0)} -attr vt d
+load net {acc.imod.sva(1)} -attr vt d
+load net {acc.imod.sva(2)} -attr vt d
+load net {acc.imod.sva(3)} -attr vt d
+load net {acc.imod.sva(4)} -attr vt d
+load net {acc.imod.sva(5)} -attr vt d
+load netBundle {acc.imod.sva} 6 {acc.imod.sva(0)} {acc.imod.sva(1)} {acc.imod.sva(2)} {acc.imod.sva(3)} {acc.imod.sva(4)} {acc.imod.sva(5)} -attr xrf 4906 -attr oid 40 -attr vt d -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {red#2.sg1.sva(0)} -attr vt d
+load net {red#2.sg1.sva(1)} -attr vt d
+load net {red#2.sg1.sva(2)} -attr vt d
+load net {red#2.sg1.sva(3)} -attr vt d
+load net {red#2.sg1.sva(4)} -attr vt d
+load net {red#2.sg1.sva(5)} -attr vt d
+load net {red#2.sg1.sva(6)} -attr vt d
+load net {red#2.sg1.sva(7)} -attr vt d
+load net {red#2.sg1.sva(8)} -attr vt d
+load net {red#2.sg1.sva(9)} -attr vt d
+load net {red#2.sg1.sva(10)} -attr vt d
+load net {red#2.sg1.sva(11)} -attr vt d
+load net {red#2.sg1.sva(12)} -attr vt d
+load net {red#2.sg1.sva(13)} -attr vt d
+load net {red#2.sg1.sva(14)} -attr vt d
+load netBundle {red#2.sg1.sva} 15 {red#2.sg1.sva(0)} {red#2.sg1.sva(1)} {red#2.sg1.sva(2)} {red#2.sg1.sva(3)} {red#2.sg1.sva(4)} {red#2.sg1.sva(5)} {red#2.sg1.sva(6)} {red#2.sg1.sva(7)} {red#2.sg1.sva(8)} {red#2.sg1.sva(9)} {red#2.sg1.sva(10)} {red#2.sg1.sva(11)} {red#2.sg1.sva(12)} {red#2.sg1.sva(13)} {red#2.sg1.sva(14)} -attr xrf 4907 -attr oid 41 -attr vt d -attr @path {/sobel/sobel:core/red#2.sg1.sva}
+load net {FRAME:mul.sdt(0)} -attr vt d
+load net {FRAME:mul.sdt(1)} -attr vt d
+load net {FRAME:mul.sdt(2)} -attr vt d
+load net {FRAME:mul.sdt(3)} -attr vt d
+load net {FRAME:mul.sdt(4)} -attr vt d
+load net {FRAME:mul.sdt(5)} -attr vt d
+load net {FRAME:mul.sdt(6)} -attr vt d
+load net {FRAME:mul.sdt(7)} -attr vt d
+load net {FRAME:mul.sdt(8)} -attr vt d
+load net {FRAME:mul.sdt(9)} -attr vt d
+load netBundle {FRAME:mul.sdt} 10 {FRAME:mul.sdt(0)} {FRAME:mul.sdt(1)} {FRAME:mul.sdt(2)} {FRAME:mul.sdt(3)} {FRAME:mul.sdt(4)} {FRAME:mul.sdt(5)} {FRAME:mul.sdt(6)} {FRAME:mul.sdt(7)} {FRAME:mul.sdt(8)} {FRAME:mul.sdt(9)} -attr xrf 4908 -attr oid 42 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {blue#2.sg1.sva(0)} -attr vt d
+load net {blue#2.sg1.sva(1)} -attr vt d
+load net {blue#2.sg1.sva(2)} -attr vt d
+load net {blue#2.sg1.sva(3)} -attr vt d
+load net {blue#2.sg1.sva(4)} -attr vt d
+load net {blue#2.sg1.sva(5)} -attr vt d
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+load net {FRAME:conc#36.itm(6)} -attr vt d
+load net {FRAME:conc#36.itm(7)} -attr vt d
+load net {FRAME:conc#36.itm(8)} -attr vt d
+load net {FRAME:conc#36.itm(9)} -attr vt d
+load netBundle {FRAME:conc#36.itm} 10 {FRAME:conc#36.itm(0)} {FRAME:conc#36.itm(1)} {FRAME:conc#36.itm(2)} {FRAME:conc#36.itm(3)} {FRAME:conc#36.itm(4)} {FRAME:conc#36.itm(5)} {FRAME:conc#36.itm(6)} {FRAME:conc#36.itm(7)} {FRAME:conc#36.itm(8)} {FRAME:conc#36.itm(9)} -attr xrf 4924 -attr oid 58 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#40.itm(0)} -attr vt d
+load net {FRAME:acc#40.itm(1)} -attr vt d
+load net {FRAME:acc#40.itm(2)} -attr vt d
+load net {FRAME:acc#40.itm(3)} -attr vt d
+load net {FRAME:acc#40.itm(4)} -attr vt d
+load net {FRAME:acc#40.itm(5)} -attr vt d
+load net {FRAME:acc#40.itm(6)} -attr vt d
+load net {FRAME:acc#40.itm(7)} -attr vt d
+load net {FRAME:acc#40.itm(8)} -attr vt d
+load net {FRAME:acc#40.itm(9)} -attr vt d
+load netBundle {FRAME:acc#40.itm} 10 {FRAME:acc#40.itm(0)} {FRAME:acc#40.itm(1)} {FRAME:acc#40.itm(2)} {FRAME:acc#40.itm(3)} {FRAME:acc#40.itm(4)} {FRAME:acc#40.itm(5)} {FRAME:acc#40.itm(6)} {FRAME:acc#40.itm(7)} {FRAME:acc#40.itm(8)} {FRAME:acc#40.itm(9)} -attr xrf 4925 -attr oid 59 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#39.itm(0)} -attr vt d
+load net {FRAME:acc#39.itm(1)} -attr vt d
+load net {FRAME:acc#39.itm(2)} -attr vt d
+load net {FRAME:acc#39.itm(3)} -attr vt d
+load net {FRAME:acc#39.itm(4)} -attr vt d
+load net {FRAME:acc#39.itm(5)} -attr vt d
+load net {FRAME:acc#39.itm(6)} -attr vt d
+load net {FRAME:acc#39.itm(7)} -attr vt d
+load netBundle {FRAME:acc#39.itm} 8 {FRAME:acc#39.itm(0)} {FRAME:acc#39.itm(1)} {FRAME:acc#39.itm(2)} {FRAME:acc#39.itm(3)} {FRAME:acc#39.itm(4)} {FRAME:acc#39.itm(5)} {FRAME:acc#39.itm(6)} {FRAME:acc#39.itm(7)} -attr xrf 4926 -attr oid 60 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#38.itm(0)} -attr vt d
+load net {FRAME:acc#38.itm(1)} -attr vt d
+load net {FRAME:acc#38.itm(2)} -attr vt d
+load net {FRAME:acc#38.itm(3)} -attr vt d
+load net {FRAME:acc#38.itm(4)} -attr vt d
+load netBundle {FRAME:acc#38.itm} 5 {FRAME:acc#38.itm(0)} {FRAME:acc#38.itm(1)} {FRAME:acc#38.itm(2)} {FRAME:acc#38.itm(3)} {FRAME:acc#38.itm(4)} -attr xrf 4927 -attr oid 61 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {conc#123.itm(0)} -attr vt d
+load net {conc#123.itm(1)} -attr vt d
+load net {conc#123.itm(2)} -attr vt d
+load net {conc#123.itm(3)} -attr vt d
+load net {conc#123.itm(4)} -attr vt d
+load netBundle {conc#123.itm} 5 {conc#123.itm(0)} {conc#123.itm(1)} {conc#123.itm(2)} {conc#123.itm(3)} {conc#123.itm(4)} -attr xrf 4928 -attr oid 62 -attr vt d -attr @path {/sobel/sobel:core/conc#123.itm}
+load net {conc#124.itm(0)} -attr vt d
+load net {conc#124.itm(1)} -attr vt d
+load net {conc#124.itm(2)} -attr vt d
+load net {conc#124.itm(3)} -attr vt d
+load net {conc#124.itm(4)} -attr vt d
+load net {conc#124.itm(5)} -attr vt d
+load net {conc#124.itm(6)} -attr vt d
+load net {conc#124.itm(7)} -attr vt d
+load net {conc#124.itm(8)} -attr vt d
+load net {conc#124.itm(9)} -attr vt d
+load netBundle {conc#124.itm} 10 {conc#124.itm(0)} {conc#124.itm(1)} {conc#124.itm(2)} {conc#124.itm(3)} {conc#124.itm(4)} {conc#124.itm(5)} {conc#124.itm(6)} {conc#124.itm(7)} {conc#124.itm(8)} {conc#124.itm(9)} -attr xrf 4929 -attr oid 63 -attr vt d -attr @path {/sobel/sobel:core/conc#124.itm}
+load net {slc(FRAME:acc#3.psp.sva).itm(0)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#3.psp.sva).itm} 2 {slc(FRAME:acc#3.psp.sva).itm(0)} {slc(FRAME:acc#3.psp.sva).itm(1)} -attr xrf 4930 -attr oid 64 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva).itm}
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(3)} -attr vt d
+load netBundle {slc(FRAME:acc#3.psp.sva)#1.itm} 4 {slc(FRAME:acc#3.psp.sva)#1.itm(0)} {slc(FRAME:acc#3.psp.sva)#1.itm(1)} {slc(FRAME:acc#3.psp.sva)#1.itm(2)} {slc(FRAME:acc#3.psp.sva)#1.itm(3)} -attr xrf 4931 -attr oid 65 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#1.itm}
+load net {FRAME:or#3.itm(0)} -attr vt d
+load net {FRAME:or#3.itm(1)} -attr vt d
+load net {FRAME:or#3.itm(2)} -attr vt d
+load net {FRAME:or#3.itm(3)} -attr vt d
+load net {FRAME:or#3.itm(4)} -attr vt d
+load net {FRAME:or#3.itm(5)} -attr vt d
+load netBundle {FRAME:or#3.itm} 6 {FRAME:or#3.itm(0)} {FRAME:or#3.itm(1)} {FRAME:or#3.itm(2)} {FRAME:or#3.itm(3)} {FRAME:or#3.itm(4)} {FRAME:or#3.itm(5)} -attr xrf 4932 -attr oid 66 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(2)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(3)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(4)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(FRAME:acc#3.psp.sva)#2.itm} 6 {slc(FRAME:acc#3.psp.sva)#2.itm(0)} {slc(FRAME:acc#3.psp.sva)#2.itm(1)} {slc(FRAME:acc#3.psp.sva)#2.itm(2)} {slc(FRAME:acc#3.psp.sva)#2.itm(3)} {slc(FRAME:acc#3.psp.sva)#2.itm(4)} {slc(FRAME:acc#3.psp.sva)#2.itm(5)} -attr xrf 4933 -attr oid 67 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {conc#125.itm(0)} -attr vt d
+load net {conc#125.itm(1)} -attr vt d
+load net {conc#125.itm(2)} -attr vt d
+load net {conc#125.itm(3)} -attr vt d
+load net {conc#125.itm(4)} -attr vt d
+load net {conc#125.itm(5)} -attr vt d
+load netBundle {conc#125.itm} 6 {conc#125.itm(0)} {conc#125.itm(1)} {conc#125.itm(2)} {conc#125.itm(3)} {conc#125.itm(4)} {conc#125.itm(5)} -attr xrf 4934 -attr oid 68 -attr vt d -attr @path {/sobel/sobel:core/conc#125.itm}
+load net {slc(FRAME:acc#4.psp.sva).itm(0)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#4.psp.sva).itm} 2 {slc(FRAME:acc#4.psp.sva).itm(0)} {slc(FRAME:acc#4.psp.sva).itm(1)} -attr xrf 4935 -attr oid 69 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#4.psp.sva).itm}
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(3)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(4)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(5)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(6)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(7)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(8)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(9)} -attr vt d
+load netBundle {slc(FRAME:acc#4.psp.sva)#1.itm} 10 {slc(FRAME:acc#4.psp.sva)#1.itm(0)} {slc(FRAME:acc#4.psp.sva)#1.itm(1)} {slc(FRAME:acc#4.psp.sva)#1.itm(2)} {slc(FRAME:acc#4.psp.sva)#1.itm(3)} {slc(FRAME:acc#4.psp.sva)#1.itm(4)} {slc(FRAME:acc#4.psp.sva)#1.itm(5)} {slc(FRAME:acc#4.psp.sva)#1.itm(6)} {slc(FRAME:acc#4.psp.sva)#1.itm(7)} {slc(FRAME:acc#4.psp.sva)#1.itm(8)} {slc(FRAME:acc#4.psp.sva)#1.itm(9)} -attr xrf 4936 -attr oid 70 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#4.psp.sva)#1.itm}
+load net {FRAME:acc#43.itm(0)} -attr vt d
+load net {FRAME:acc#43.itm(1)} -attr vt d
+load netBundle {FRAME:acc#43.itm} 2 {FRAME:acc#43.itm(0)} {FRAME:acc#43.itm(1)} -attr xrf 4937 -attr oid 71 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {slc(FRAME:mul.sdt).itm(0)} -attr vt d
+load net {slc(FRAME:mul.sdt).itm(1)} -attr vt d
+load netBundle {slc(FRAME:mul.sdt).itm} 2 {slc(FRAME:mul.sdt).itm(0)} {slc(FRAME:mul.sdt).itm(1)} -attr xrf 4938 -attr oid 72 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt).itm}
+load net {slc(FRAME:mul.sdt)#2.itm(0)} -attr vt d
+load net {slc(FRAME:mul.sdt)#2.itm(1)} -attr vt d
+load netBundle {slc(FRAME:mul.sdt)#2.itm} 2 {slc(FRAME:mul.sdt)#2.itm(0)} {slc(FRAME:mul.sdt)#2.itm(1)} -attr xrf 4939 -attr oid 73 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#2.itm}
+load net {FRAME:acc#44.itm(0)} -attr vt d
+load net {FRAME:acc#44.itm(1)} -attr vt d
+load net {FRAME:acc#44.itm(2)} -attr vt d
+load net {FRAME:acc#44.itm(3)} -attr vt d
+load net {FRAME:acc#44.itm(4)} -attr vt d
+load net {FRAME:acc#44.itm(5)} -attr vt d
+load netBundle {FRAME:acc#44.itm} 6 {FRAME:acc#44.itm(0)} {FRAME:acc#44.itm(1)} {FRAME:acc#44.itm(2)} {FRAME:acc#44.itm(3)} {FRAME:acc#44.itm(4)} {FRAME:acc#44.itm(5)} -attr xrf 4940 -attr oid 74 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {slc(FRAME:mul.sdt)#1.itm(0)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(1)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(2)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(3)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(4)} -attr vt d
+load netBundle {slc(FRAME:mul.sdt)#1.itm} 5 {slc(FRAME:mul.sdt)#1.itm(0)} {slc(FRAME:mul.sdt)#1.itm(1)} {slc(FRAME:mul.sdt)#1.itm(2)} {slc(FRAME:mul.sdt)#1.itm(3)} {slc(FRAME:mul.sdt)#1.itm(4)} -attr xrf 4941 -attr oid 75 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {exs.itm(0)} -attr vt d
+load net {exs.itm(1)} -attr vt d
+load net {exs.itm(2)} -attr vt d
+load net {exs.itm(3)} -attr vt d
+load net {exs.itm(4)} -attr vt d
+load netBundle {exs.itm} 5 {exs.itm(0)} {exs.itm(1)} {exs.itm(2)} {exs.itm(3)} {exs.itm(4)} -attr xrf 4942 -attr oid 76 -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {conc#126.itm(0)} -attr vt d
+load net {conc#126.itm(1)} -attr vt d
+load net {conc#126.itm(2)} -attr vt d
+load netBundle {conc#126.itm} 3 {conc#126.itm(0)} {conc#126.itm(1)} {conc#126.itm(2)} -attr xrf 4943 -attr oid 77 -attr vt d -attr @path {/sobel/sobel:core/conc#126.itm}
+load net {FRAME:mul#1.itm(0)} -attr vt d
+load net {FRAME:mul#1.itm(1)} -attr vt d
+load net {FRAME:mul#1.itm(2)} -attr vt d
+load net {FRAME:mul#1.itm(3)} -attr vt d
+load net {FRAME:mul#1.itm(4)} -attr vt d
+load net {FRAME:mul#1.itm(5)} -attr vt d
+load net {FRAME:mul#1.itm(6)} -attr vt d
+load net {FRAME:mul#1.itm(7)} -attr vt d
+load net {FRAME:mul#1.itm(8)} -attr vt d
+load netBundle {FRAME:mul#1.itm} 9 {FRAME:mul#1.itm(0)} {FRAME:mul#1.itm(1)} {FRAME:mul#1.itm(2)} {FRAME:mul#1.itm(3)} {FRAME:mul#1.itm(4)} {FRAME:mul#1.itm(5)} {FRAME:mul#1.itm(6)} {FRAME:mul#1.itm(7)} {FRAME:mul#1.itm(8)} -attr xrf 4944 -attr oid 78 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {slc(red#2.sg1.sva)#13.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#13.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#13.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#13.itm} 3 {slc(red#2.sg1.sva)#13.itm(0)} {slc(red#2.sg1.sva)#13.itm(1)} {slc(red#2.sg1.sva)#13.itm(2)} -attr xrf 4945 -attr oid 79 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {slc(red#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(2)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(3)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(4)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(5)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#1.itm} 6 {slc(red#2.sg1.sva)#1.itm(0)} {slc(red#2.sg1.sva)#1.itm(1)} {slc(red#2.sg1.sva)#1.itm(2)} {slc(red#2.sg1.sva)#1.itm(3)} {slc(red#2.sg1.sva)#1.itm(4)} {slc(red#2.sg1.sva)#1.itm(5)} -attr xrf 4946 -attr oid 80 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {FRAME:acc#37.itm(0)} -attr vt d
+load net {FRAME:acc#37.itm(1)} -attr vt d
+load net {FRAME:acc#37.itm(2)} -attr vt d
+load net {FRAME:acc#37.itm(3)} -attr vt d
+load net {FRAME:acc#37.itm(4)} -attr vt d
+load netBundle {FRAME:acc#37.itm} 5 {FRAME:acc#37.itm(0)} {FRAME:acc#37.itm(1)} {FRAME:acc#37.itm(2)} {FRAME:acc#37.itm(3)} {FRAME:acc#37.itm(4)} -attr xrf 4947 -attr oid 81 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#36.itm(0)} -attr vt d
+load net {FRAME:acc#36.itm(1)} -attr vt d
+load net {FRAME:acc#36.itm(2)} -attr vt d
+load net {FRAME:acc#36.itm(3)} -attr vt d
+load netBundle {FRAME:acc#36.itm} 4 {FRAME:acc#36.itm(0)} {FRAME:acc#36.itm(1)} {FRAME:acc#36.itm(2)} {FRAME:acc#36.itm(3)} -attr xrf 4948 -attr oid 82 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {conc#128.itm(0)} -attr vt d
+load net {conc#128.itm(1)} -attr vt d
+load net {conc#128.itm(2)} -attr vt d
+load netBundle {conc#128.itm} 3 {conc#128.itm(0)} {conc#128.itm(1)} {conc#128.itm(2)} -attr xrf 4949 -attr oid 83 -attr vt d -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {conc#129.itm(0)} -attr vt d
+load net {conc#129.itm(1)} -attr vt d
+load net {conc#129.itm(2)} -attr vt d
+load net {conc#129.itm(3)} -attr vt d
+load net {conc#129.itm(4)} -attr vt d
+load netBundle {conc#129.itm} 5 {conc#129.itm(0)} {conc#129.itm(1)} {conc#129.itm(2)} {conc#129.itm(3)} {conc#129.itm(4)} -attr xrf 4950 -attr oid 84 -attr vt d -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {slc(acc.imod.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod.sva)#1.itm} 3 {slc(acc.imod.sva)#1.itm(0)} {slc(acc.imod.sva)#1.itm(1)} {slc(acc.imod.sva)#1.itm(2)} -attr xrf 4951 -attr oid 85 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#1.itm}
+load net {FRAME:conc#33.itm(0)} -attr vt d
+load net {FRAME:conc#33.itm(1)} -attr vt d
+load net {FRAME:conc#33.itm(2)} -attr vt d
+load net {FRAME:conc#33.itm(3)} -attr vt d
+load netBundle {FRAME:conc#33.itm} 4 {FRAME:conc#33.itm(0)} {FRAME:conc#33.itm(1)} {FRAME:conc#33.itm(2)} {FRAME:conc#33.itm(3)} -attr xrf 4952 -attr oid 86 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(0)} -attr vt d
+load net {FRAME:not#5.itm(1)} -attr vt d
+load net {FRAME:not#5.itm(2)} -attr vt d
+load netBundle {FRAME:not#5.itm} 3 {FRAME:not#5.itm(0)} {FRAME:not#5.itm(1)} {FRAME:not#5.itm(2)} -attr xrf 4953 -attr oid 87 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {slc(acc.imod.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod.sva)#2.itm} 3 {slc(acc.imod.sva)#2.itm(0)} {slc(acc.imod.sva)#2.itm(1)} {slc(acc.imod.sva)#2.itm(2)} -attr xrf 4954 -attr oid 88 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#2.itm}
+load net {slc(acc.imod.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod.sva)#4.itm} 2 {slc(acc.imod.sva)#4.itm(0)} {slc(acc.imod.sva)#4.itm(1)} -attr xrf 4955 -attr oid 89 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#4.itm}
+load net {FRAME:not#6.itm(0)} -attr vt d
+load net {FRAME:not#6.itm(1)} -attr vt d
+load net {FRAME:not#6.itm(2)} -attr vt d
+load netBundle {FRAME:not#6.itm} 3 {FRAME:not#6.itm(0)} {FRAME:not#6.itm(1)} {FRAME:not#6.itm(2)} -attr xrf 4956 -attr oid 90 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {slc(red#2.sg1.sva)#8.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#8.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#8.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#8.itm} 3 {slc(red#2.sg1.sva)#8.itm(0)} {slc(red#2.sg1.sva)#8.itm(1)} {slc(red#2.sg1.sva)#8.itm(2)} -attr xrf 4957 -attr oid 91 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {FRAME:mul#4.itm(0)} -attr vt d
+load net {FRAME:mul#4.itm(1)} -attr vt d
+load net {FRAME:mul#4.itm(2)} -attr vt d
+load net {FRAME:mul#4.itm(3)} -attr vt d
+load net {FRAME:mul#4.itm(4)} -attr vt d
+load net {FRAME:mul#4.itm(5)} -attr vt d
+load net {FRAME:mul#4.itm(6)} -attr vt d
+load net {FRAME:mul#4.itm(7)} -attr vt d
+load net {FRAME:mul#4.itm(8)} -attr vt d
+load net {FRAME:mul#4.itm(9)} -attr vt d
+load net {FRAME:mul#4.itm(10)} -attr vt d
+load netBundle {FRAME:mul#4.itm} 11 {FRAME:mul#4.itm(0)} {FRAME:mul#4.itm(1)} {FRAME:mul#4.itm(2)} {FRAME:mul#4.itm(3)} {FRAME:mul#4.itm(4)} {FRAME:mul#4.itm(5)} {FRAME:mul#4.itm(6)} {FRAME:mul#4.itm(7)} {FRAME:mul#4.itm(8)} {FRAME:mul#4.itm(9)} {FRAME:mul#4.itm(10)} -attr xrf 4958 -attr oid 92 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {slc(blue#2.sg1.sva)#10.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#10.itm(1)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#10.itm} 2 {slc(blue#2.sg1.sva)#10.itm(0)} {slc(blue#2.sg1.sva)#10.itm(1)} -attr xrf 4959 -attr oid 93 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#10.itm}
+load net {FRAME:mul#5.itm(0)} -attr vt d
+load net {FRAME:mul#5.itm(1)} -attr vt d
+load net {FRAME:mul#5.itm(2)} -attr vt d
+load net {FRAME:mul#5.itm(3)} -attr vt d
+load net {FRAME:mul#5.itm(4)} -attr vt d
+load net {FRAME:mul#5.itm(5)} -attr vt d
+load net {FRAME:mul#5.itm(6)} -attr vt d
+load net {FRAME:mul#5.itm(7)} -attr vt d
+load net {FRAME:mul#5.itm(8)} -attr vt d
+load netBundle {FRAME:mul#5.itm} 9 {FRAME:mul#5.itm(0)} {FRAME:mul#5.itm(1)} {FRAME:mul#5.itm(2)} {FRAME:mul#5.itm(3)} {FRAME:mul#5.itm(4)} {FRAME:mul#5.itm(5)} {FRAME:mul#5.itm(6)} {FRAME:mul#5.itm(7)} {FRAME:mul#5.itm(8)} -attr xrf 4960 -attr oid 94 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {slc(blue#2.sg1.sva)#11.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#11.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#11.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#11.itm} 3 {slc(blue#2.sg1.sva)#11.itm(0)} {slc(blue#2.sg1.sva)#11.itm(1)} {slc(blue#2.sg1.sva)#11.itm(2)} -attr xrf 4961 -attr oid 95 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {slc(blue#2.sg1.sva)#2.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(2)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(3)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(4)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#2.itm} 6 {slc(blue#2.sg1.sva)#2.itm(0)} {slc(blue#2.sg1.sva)#2.itm(1)} {slc(blue#2.sg1.sva)#2.itm(2)} {slc(blue#2.sg1.sva)#2.itm(3)} {slc(blue#2.sg1.sva)#2.itm(4)} {slc(blue#2.sg1.sva)#2.itm(5)} -attr xrf 4962 -attr oid 96 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {FRAME:acc#30.itm(0)} -attr vt d
+load net {FRAME:acc#30.itm(1)} -attr vt d
+load net {FRAME:acc#30.itm(2)} -attr vt d
+load net {FRAME:acc#30.itm(3)} -attr vt d
+load net {FRAME:acc#30.itm(4)} -attr vt d
+load netBundle {FRAME:acc#30.itm} 5 {FRAME:acc#30.itm(0)} {FRAME:acc#30.itm(1)} {FRAME:acc#30.itm(2)} {FRAME:acc#30.itm(3)} {FRAME:acc#30.itm(4)} -attr xrf 4963 -attr oid 97 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#29.itm(0)} -attr vt d
+load net {FRAME:acc#29.itm(1)} -attr vt d
+load net {FRAME:acc#29.itm(2)} -attr vt d
+load net {FRAME:acc#29.itm(3)} -attr vt d
+load netBundle {FRAME:acc#29.itm} 4 {FRAME:acc#29.itm(0)} {FRAME:acc#29.itm(1)} {FRAME:acc#29.itm(2)} {FRAME:acc#29.itm(3)} -attr xrf 4964 -attr oid 98 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {conc#130.itm(0)} -attr vt d
+load net {conc#130.itm(1)} -attr vt d
+load net {conc#130.itm(2)} -attr vt d
+load netBundle {conc#130.itm} 3 {conc#130.itm(0)} {conc#130.itm(1)} {conc#130.itm(2)} -attr xrf 4965 -attr oid 99 -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {conc#131.itm(0)} -attr vt d
+load net {conc#131.itm(1)} -attr vt d
+load net {conc#131.itm(2)} -attr vt d
+load net {conc#131.itm(3)} -attr vt d
+load net {conc#131.itm(4)} -attr vt d
+load netBundle {conc#131.itm} 5 {conc#131.itm(0)} {conc#131.itm(1)} {conc#131.itm(2)} {conc#131.itm(3)} {conc#131.itm(4)} -attr xrf 4966 -attr oid 100 -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {slc(acc.imod#4.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#4.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#4.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#4.sva)#1.itm} 3 {slc(acc.imod#4.sva)#1.itm(0)} {slc(acc.imod#4.sva)#1.itm(1)} {slc(acc.imod#4.sva)#1.itm(2)} -attr xrf 4967 -attr oid 101 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#1.itm}
+load net {FRAME:conc#29.itm(0)} -attr vt d
+load net {FRAME:conc#29.itm(1)} -attr vt d
+load net {FRAME:conc#29.itm(2)} -attr vt d
+load net {FRAME:conc#29.itm(3)} -attr vt d
+load netBundle {FRAME:conc#29.itm} 4 {FRAME:conc#29.itm(0)} {FRAME:conc#29.itm(1)} {FRAME:conc#29.itm(2)} {FRAME:conc#29.itm(3)} -attr xrf 4968 -attr oid 102 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(0)} -attr vt d
+load net {FRAME:not#21.itm(1)} -attr vt d
+load net {FRAME:not#21.itm(2)} -attr vt d
+load netBundle {FRAME:not#21.itm} 3 {FRAME:not#21.itm(0)} {FRAME:not#21.itm(1)} {FRAME:not#21.itm(2)} -attr xrf 4969 -attr oid 103 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {slc(acc.imod#4.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#4.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#4.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#4.sva)#2.itm} 3 {slc(acc.imod#4.sva)#2.itm(0)} {slc(acc.imod#4.sva)#2.itm(1)} {slc(acc.imod#4.sva)#2.itm(2)} -attr xrf 4970 -attr oid 104 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#2.itm}
+load net {slc(acc.imod#4.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#4.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#4.sva)#4.itm} 2 {slc(acc.imod#4.sva)#4.itm(0)} {slc(acc.imod#4.sva)#4.itm(1)} -attr xrf 4971 -attr oid 105 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#4.itm}
+load net {FRAME:not#22.itm(0)} -attr vt d
+load net {FRAME:not#22.itm(1)} -attr vt d
+load net {FRAME:not#22.itm(2)} -attr vt d
+load netBundle {FRAME:not#22.itm} 3 {FRAME:not#22.itm(0)} {FRAME:not#22.itm(1)} {FRAME:not#22.itm(2)} -attr xrf 4972 -attr oid 106 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {slc(blue#2.sg1.sva)#9.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#9.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#9.itm} 3 {slc(blue#2.sg1.sva)#9.itm(0)} {slc(blue#2.sg1.sva)#9.itm(1)} {slc(blue#2.sg1.sva)#9.itm(2)} -attr xrf 4973 -attr oid 107 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {FRAME:mul#2.itm(0)} -attr vt d
+load net {FRAME:mul#2.itm(1)} -attr vt d
+load net {FRAME:mul#2.itm(2)} -attr vt d
+load net {FRAME:mul#2.itm(3)} -attr vt d
+load net {FRAME:mul#2.itm(4)} -attr vt d
+load net {FRAME:mul#2.itm(5)} -attr vt d
+load net {FRAME:mul#2.itm(6)} -attr vt d
+load net {FRAME:mul#2.itm(7)} -attr vt d
+load net {FRAME:mul#2.itm(8)} -attr vt d
+load net {FRAME:mul#2.itm(9)} -attr vt d
+load net {FRAME:mul#2.itm(10)} -attr vt d
+load netBundle {FRAME:mul#2.itm} 11 {FRAME:mul#2.itm(0)} {FRAME:mul#2.itm(1)} {FRAME:mul#2.itm(2)} {FRAME:mul#2.itm(3)} {FRAME:mul#2.itm(4)} {FRAME:mul#2.itm(5)} {FRAME:mul#2.itm(6)} {FRAME:mul#2.itm(7)} {FRAME:mul#2.itm(8)} {FRAME:mul#2.itm(9)} {FRAME:mul#2.itm(10)} -attr xrf 4974 -attr oid 108 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {slc(green#2.sg1.sva)#10.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#10.itm(1)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#10.itm} 2 {slc(green#2.sg1.sva)#10.itm(0)} {slc(green#2.sg1.sva)#10.itm(1)} -attr xrf 4975 -attr oid 109 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#10.itm}
+load net {FRAME:mul#3.itm(0)} -attr vt d
+load net {FRAME:mul#3.itm(1)} -attr vt d
+load net {FRAME:mul#3.itm(2)} -attr vt d
+load net {FRAME:mul#3.itm(3)} -attr vt d
+load net {FRAME:mul#3.itm(4)} -attr vt d
+load net {FRAME:mul#3.itm(5)} -attr vt d
+load net {FRAME:mul#3.itm(6)} -attr vt d
+load net {FRAME:mul#3.itm(7)} -attr vt d
+load net {FRAME:mul#3.itm(8)} -attr vt d
+load netBundle {FRAME:mul#3.itm} 9 {FRAME:mul#3.itm(0)} {FRAME:mul#3.itm(1)} {FRAME:mul#3.itm(2)} {FRAME:mul#3.itm(3)} {FRAME:mul#3.itm(4)} {FRAME:mul#3.itm(5)} {FRAME:mul#3.itm(6)} {FRAME:mul#3.itm(7)} {FRAME:mul#3.itm(8)} -attr xrf 4976 -attr oid 110 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {slc(green#2.sg1.sva)#11.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#11.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#11.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#11.itm} 3 {slc(green#2.sg1.sva)#11.itm(0)} {slc(green#2.sg1.sva)#11.itm(1)} {slc(green#2.sg1.sva)#11.itm(2)} -attr xrf 4977 -attr oid 111 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {slc(green#2.sg1.sva)#2.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(2)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(3)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(4)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#2.itm} 6 {slc(green#2.sg1.sva)#2.itm(0)} {slc(green#2.sg1.sva)#2.itm(1)} {slc(green#2.sg1.sva)#2.itm(2)} {slc(green#2.sg1.sva)#2.itm(3)} {slc(green#2.sg1.sva)#2.itm(4)} {slc(green#2.sg1.sva)#2.itm(5)} -attr xrf 4978 -attr oid 112 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {FRAME:acc#18.itm(0)} -attr vt d
+load net {FRAME:acc#18.itm(1)} -attr vt d
+load net {FRAME:acc#18.itm(2)} -attr vt d
+load net {FRAME:acc#18.itm(3)} -attr vt d
+load net {FRAME:acc#18.itm(4)} -attr vt d
+load netBundle {FRAME:acc#18.itm} 5 {FRAME:acc#18.itm(0)} {FRAME:acc#18.itm(1)} {FRAME:acc#18.itm(2)} {FRAME:acc#18.itm(3)} {FRAME:acc#18.itm(4)} -attr xrf 4979 -attr oid 113 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#17.itm(0)} -attr vt d
+load net {FRAME:acc#17.itm(1)} -attr vt d
+load net {FRAME:acc#17.itm(2)} -attr vt d
+load net {FRAME:acc#17.itm(3)} -attr vt d
+load netBundle {FRAME:acc#17.itm} 4 {FRAME:acc#17.itm(0)} {FRAME:acc#17.itm(1)} {FRAME:acc#17.itm(2)} {FRAME:acc#17.itm(3)} -attr xrf 4980 -attr oid 114 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {conc#132.itm(0)} -attr vt d
+load net {conc#132.itm(1)} -attr vt d
+load net {conc#132.itm(2)} -attr vt d
+load netBundle {conc#132.itm} 3 {conc#132.itm(0)} {conc#132.itm(1)} {conc#132.itm(2)} -attr xrf 4981 -attr oid 115 -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {conc#133.itm(0)} -attr vt d
+load net {conc#133.itm(1)} -attr vt d
+load net {conc#133.itm(2)} -attr vt d
+load net {conc#133.itm(3)} -attr vt d
+load net {conc#133.itm(4)} -attr vt d
+load netBundle {conc#133.itm} 5 {conc#133.itm(0)} {conc#133.itm(1)} {conc#133.itm(2)} {conc#133.itm(3)} {conc#133.itm(4)} -attr xrf 4982 -attr oid 116 -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {slc(acc.imod#2.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#2.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#2.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#2.sva)#1.itm} 3 {slc(acc.imod#2.sva)#1.itm(0)} {slc(acc.imod#2.sva)#1.itm(1)} {slc(acc.imod#2.sva)#1.itm(2)} -attr xrf 4983 -attr oid 117 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#1.itm}
+load net {FRAME:conc#25.itm(0)} -attr vt d
+load net {FRAME:conc#25.itm(1)} -attr vt d
+load net {FRAME:conc#25.itm(2)} -attr vt d
+load net {FRAME:conc#25.itm(3)} -attr vt d
+load netBundle {FRAME:conc#25.itm} 4 {FRAME:conc#25.itm(0)} {FRAME:conc#25.itm(1)} {FRAME:conc#25.itm(2)} {FRAME:conc#25.itm(3)} -attr xrf 4984 -attr oid 118 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(0)} -attr vt d
+load net {FRAME:not#13.itm(1)} -attr vt d
+load net {FRAME:not#13.itm(2)} -attr vt d
+load netBundle {FRAME:not#13.itm} 3 {FRAME:not#13.itm(0)} {FRAME:not#13.itm(1)} {FRAME:not#13.itm(2)} -attr xrf 4985 -attr oid 119 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {slc(acc.imod#2.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#2.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#2.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#2.sva)#2.itm} 3 {slc(acc.imod#2.sva)#2.itm(0)} {slc(acc.imod#2.sva)#2.itm(1)} {slc(acc.imod#2.sva)#2.itm(2)} -attr xrf 4986 -attr oid 120 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#2.itm}
+load net {slc(acc.imod#2.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#2.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#2.sva)#4.itm} 2 {slc(acc.imod#2.sva)#4.itm(0)} {slc(acc.imod#2.sva)#4.itm(1)} -attr xrf 4987 -attr oid 121 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#4.itm}
+load net {FRAME:not#14.itm(0)} -attr vt d
+load net {FRAME:not#14.itm(1)} -attr vt d
+load net {FRAME:not#14.itm(2)} -attr vt d
+load netBundle {FRAME:not#14.itm} 3 {FRAME:not#14.itm(0)} {FRAME:not#14.itm(1)} {FRAME:not#14.itm(2)} -attr xrf 4988 -attr oid 122 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {slc(green#2.sg1.sva)#9.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#9.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#9.itm} 3 {slc(green#2.sg1.sva)#9.itm(0)} {slc(green#2.sg1.sva)#9.itm(1)} {slc(green#2.sg1.sva)#9.itm(2)} -attr xrf 4989 -attr oid 123 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {mux#5.itm(0)} -attr vt d
+load net {mux#5.itm(1)} -attr vt d
+load net {mux#5.itm(2)} -attr vt d
+load net {mux#5.itm(3)} -attr vt d
+load net {mux#5.itm(4)} -attr vt d
+load net {mux#5.itm(5)} -attr vt d
+load net {mux#5.itm(6)} -attr vt d
+load net {mux#5.itm(7)} -attr vt d
+load net {mux#5.itm(8)} -attr vt d
+load net {mux#5.itm(9)} -attr vt d
+load net {mux#5.itm(10)} -attr vt d
+load net {mux#5.itm(11)} -attr vt d
+load net {mux#5.itm(12)} -attr vt d
+load net {mux#5.itm(13)} -attr vt d
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+load net {FRAME:acc#7.itm(3)} -attr vt d
+load netBundle {FRAME:acc#7.itm} 4 {FRAME:acc#7.itm(0)} {FRAME:acc#7.itm(1)} {FRAME:acc#7.itm(2)} {FRAME:acc#7.itm(3)} -attr xrf 5016 -attr oid 150 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {conc#140.itm(0)} -attr vt d
+load net {conc#140.itm(1)} -attr vt d
+load net {conc#140.itm(2)} -attr vt d
+load netBundle {conc#140.itm} 3 {conc#140.itm(0)} {conc#140.itm(1)} {conc#140.itm(2)} -attr xrf 5017 -attr oid 151 -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {slc(red#2.sg1.sva)#5.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#5.itm(1)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#5.itm} 2 {slc(red#2.sg1.sva)#5.itm(0)} {slc(red#2.sg1.sva)#5.itm(1)} -attr xrf 5018 -attr oid 152 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#5.itm}
+load net {FRAME:acc#9.itm(0)} -attr vt d
+load net {FRAME:acc#9.itm(1)} -attr vt d
+load net {FRAME:acc#9.itm(2)} -attr vt d
+load net {FRAME:acc#9.itm(3)} -attr vt d
+load netBundle {FRAME:acc#9.itm} 4 {FRAME:acc#9.itm(0)} {FRAME:acc#9.itm(1)} {FRAME:acc#9.itm(2)} {FRAME:acc#9.itm(3)} -attr xrf 5019 -attr oid 153 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {slc(red#2.sg1.sva)#6.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#6.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#6.itm} 3 {slc(red#2.sg1.sva)#6.itm(0)} {slc(red#2.sg1.sva)#6.itm(1)} {slc(red#2.sg1.sva)#6.itm(2)} -attr xrf 5020 -attr oid 154 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {FRAME:not#1.itm(0)} -attr vt d
+load net {FRAME:not#1.itm(1)} -attr vt d
+load net {FRAME:not#1.itm(2)} -attr vt d
+load netBundle {FRAME:not#1.itm} 3 {FRAME:not#1.itm(0)} {FRAME:not#1.itm(1)} {FRAME:not#1.itm(2)} -attr xrf 5021 -attr oid 155 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {slc(red#2.sg1.sva)#7.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#7.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#7.itm} 3 {slc(red#2.sg1.sva)#7.itm(0)} {slc(red#2.sg1.sva)#7.itm(1)} {slc(red#2.sg1.sva)#7.itm(2)} -attr xrf 5022 -attr oid 156 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {ACC1:acc#43.itm(0)} -attr vt d
+load net {ACC1:acc#43.itm(1)} -attr vt d
+load net {ACC1:acc#43.itm(2)} -attr vt d
+load net {ACC1:acc#43.itm(3)} -attr vt d
+load net {ACC1:acc#43.itm(4)} -attr vt d
+load net {ACC1:acc#43.itm(5)} -attr vt d
+load net {ACC1:acc#43.itm(6)} -attr vt d
+load net {ACC1:acc#43.itm(7)} -attr vt d
+load net {ACC1:acc#43.itm(8)} -attr vt d
+load net {ACC1:acc#43.itm(9)} -attr vt d
+load net {ACC1:acc#43.itm(10)} -attr vt d
+load net {ACC1:acc#43.itm(11)} -attr vt d
+load net {ACC1:acc#43.itm(12)} -attr vt d
+load net {ACC1:acc#43.itm(13)} -attr vt d
+load net {ACC1:acc#43.itm(14)} -attr vt d
+load net {ACC1:acc#43.itm(15)} -attr vt d
+load netBundle {ACC1:acc#43.itm} 16 {ACC1:acc#43.itm(0)} {ACC1:acc#43.itm(1)} {ACC1:acc#43.itm(2)} {ACC1:acc#43.itm(3)} {ACC1:acc#43.itm(4)} {ACC1:acc#43.itm(5)} {ACC1:acc#43.itm(6)} {ACC1:acc#43.itm(7)} {ACC1:acc#43.itm(8)} {ACC1:acc#43.itm(9)} {ACC1:acc#43.itm(10)} {ACC1:acc#43.itm(11)} {ACC1:acc#43.itm(12)} {ACC1:acc#43.itm(13)} {ACC1:acc#43.itm(14)} {ACC1:acc#43.itm(15)} -attr xrf 5023 -attr oid 157 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:conc#45.itm(0)} -attr vt d
+load net {ACC1:conc#45.itm(1)} -attr vt d
+load net {ACC1:conc#45.itm(2)} -attr vt d
+load net {ACC1:conc#45.itm(3)} -attr vt d
+load net {ACC1:conc#45.itm(4)} -attr vt d
+load net {ACC1:conc#45.itm(5)} -attr vt d
+load net {ACC1:conc#45.itm(6)} -attr vt d
+load net {ACC1:conc#45.itm(7)} -attr vt d
+load net {ACC1:conc#45.itm(8)} -attr vt d
+load net {ACC1:conc#45.itm(9)} -attr vt d
+load net {ACC1:conc#45.itm(10)} -attr vt d
+load net {ACC1:conc#45.itm(11)} -attr vt d
+load net {ACC1:conc#45.itm(12)} -attr vt d
+load net {ACC1:conc#45.itm(13)} -attr vt d
+load net {ACC1:conc#45.itm(14)} -attr vt d
+load net {ACC1:conc#45.itm(15)} -attr vt d
+load netBundle {ACC1:conc#45.itm} 16 {ACC1:conc#45.itm(0)} {ACC1:conc#45.itm(1)} {ACC1:conc#45.itm(2)} {ACC1:conc#45.itm(3)} {ACC1:conc#45.itm(4)} {ACC1:conc#45.itm(5)} {ACC1:conc#45.itm(6)} {ACC1:conc#45.itm(7)} {ACC1:conc#45.itm(8)} {ACC1:conc#45.itm(9)} {ACC1:conc#45.itm(10)} {ACC1:conc#45.itm(11)} {ACC1:conc#45.itm(12)} {ACC1:conc#45.itm(13)} {ACC1:conc#45.itm(14)} {ACC1:conc#45.itm(15)} -attr xrf 5024 -attr oid 158 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(0)} -attr vt d
+load net {ACC1:acc#62.itm(1)} -attr vt d
+load net {ACC1:acc#62.itm(2)} -attr vt d
+load net {ACC1:acc#62.itm(3)} -attr vt d
+load net {ACC1:acc#62.itm(4)} -attr vt d
+load net {ACC1:acc#62.itm(5)} -attr vt d
+load net {ACC1:acc#62.itm(6)} -attr vt d
+load net {ACC1:acc#62.itm(7)} -attr vt d
+load net {ACC1:acc#62.itm(8)} -attr vt d
+load net {ACC1:acc#62.itm(9)} -attr vt d
+load net {ACC1:acc#62.itm(10)} -attr vt d
+load net {ACC1:acc#62.itm(11)} -attr vt d
+load net {ACC1:acc#62.itm(12)} -attr vt d
+load net {ACC1:acc#62.itm(13)} -attr vt d
+load net {ACC1:acc#62.itm(14)} -attr vt d
+load netBundle {ACC1:acc#62.itm} 15 {ACC1:acc#62.itm(0)} {ACC1:acc#62.itm(1)} {ACC1:acc#62.itm(2)} {ACC1:acc#62.itm(3)} {ACC1:acc#62.itm(4)} {ACC1:acc#62.itm(5)} {ACC1:acc#62.itm(6)} {ACC1:acc#62.itm(7)} {ACC1:acc#62.itm(8)} {ACC1:acc#62.itm(9)} {ACC1:acc#62.itm(10)} {ACC1:acc#62.itm(11)} {ACC1:acc#62.itm(12)} {ACC1:acc#62.itm(13)} {ACC1:acc#62.itm(14)} -attr xrf 5025 -attr oid 159 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {slc.itm(0)} -attr vt d
+load net {slc.itm(1)} -attr vt d
+load net {slc.itm(2)} -attr vt d
+load net {slc.itm(3)} -attr vt d
+load net {slc.itm(4)} -attr vt d
+load net {slc.itm(5)} -attr vt d
+load net {slc.itm(6)} -attr vt d
+load net {slc.itm(7)} -attr vt d
+load net {slc.itm(8)} -attr vt d
+load net {slc.itm(9)} -attr vt d
+load net {slc.itm(10)} -attr vt d
+load netBundle {slc.itm} 11 {slc.itm(0)} {slc.itm(1)} {slc.itm(2)} {slc.itm(3)} {slc.itm(4)} {slc.itm(5)} {slc.itm(6)} {slc.itm(7)} {slc.itm(8)} {slc.itm(9)} {slc.itm(10)} -attr xrf 5026 -attr oid 160 -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(0)} -attr vt d
+load net {acc#5.itm(1)} -attr vt d
+load net {acc#5.itm(2)} -attr vt d
+load net {acc#5.itm(3)} -attr vt d
+load net {acc#5.itm(4)} -attr vt d
+load net {acc#5.itm(5)} -attr vt d
+load net {acc#5.itm(6)} -attr vt d
+load net {acc#5.itm(7)} -attr vt d
+load net {acc#5.itm(8)} -attr vt d
+load net {acc#5.itm(9)} -attr vt d
+load net {acc#5.itm(10)} -attr vt d
+load net {acc#5.itm(11)} -attr vt d
+load netBundle {acc#5.itm} 12 {acc#5.itm(0)} {acc#5.itm(1)} {acc#5.itm(2)} {acc#5.itm(3)} {acc#5.itm(4)} {acc#5.itm(5)} {acc#5.itm(6)} {acc#5.itm(7)} {acc#5.itm(8)} {acc#5.itm(9)} {acc#5.itm(10)} {acc#5.itm(11)} -attr xrf 5027 -attr oid 161 -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {conc#141.itm(0)} -attr vt d
+load net {conc#141.itm(1)} -attr vt d
+load net {conc#141.itm(2)} -attr vt d
+load net {conc#141.itm(3)} -attr vt d
+load net {conc#141.itm(4)} -attr vt d
+load net {conc#141.itm(5)} -attr vt d
+load net {conc#141.itm(6)} -attr vt d
+load net {conc#141.itm(7)} -attr vt d
+load net {conc#141.itm(8)} -attr vt d
+load net {conc#141.itm(9)} -attr vt d
+load net {conc#141.itm(10)} -attr vt d
+load netBundle {conc#141.itm} 11 {conc#141.itm(0)} {conc#141.itm(1)} {conc#141.itm(2)} {conc#141.itm(3)} {conc#141.itm(4)} {conc#141.itm(5)} {conc#141.itm(6)} {conc#141.itm(7)} {conc#141.itm(8)} {conc#141.itm(9)} {conc#141.itm(10)} -attr xrf 5028 -attr oid 162 -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(0)} -attr vt d
+load net {ACC2:not.itm(1)} -attr vt d
+load net {ACC2:not.itm(2)} -attr vt d
+load net {ACC2:not.itm(3)} -attr vt d
+load net {ACC2:not.itm(4)} -attr vt d
+load net {ACC2:not.itm(5)} -attr vt d
+load net {ACC2:not.itm(6)} -attr vt d
+load net {ACC2:not.itm(7)} -attr vt d
+load net {ACC2:not.itm(8)} -attr vt d
+load net {ACC2:not.itm(9)} -attr vt d
+load netBundle {ACC2:not.itm} 10 {ACC2:not.itm(0)} {ACC2:not.itm(1)} {ACC2:not.itm(2)} {ACC2:not.itm(3)} {ACC2:not.itm(4)} {ACC2:not.itm(5)} {ACC2:not.itm(6)} {ACC2:not.itm(7)} {ACC2:not.itm(8)} {ACC2:not.itm(9)} -attr xrf 5029 -attr oid 163 -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr xrf 5030 -attr oid 164 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {conc#142.itm(0)} -attr vt d
+load net {conc#142.itm(1)} -attr vt d
+load net {conc#142.itm(2)} -attr vt d
+load net {conc#142.itm(3)} -attr vt d
+load net {conc#142.itm(4)} -attr vt d
+load net {conc#142.itm(5)} -attr vt d
+load net {conc#142.itm(6)} -attr vt d
+load net {conc#142.itm(7)} -attr vt d
+load net {conc#142.itm(8)} -attr vt d
+load net {conc#142.itm(9)} -attr vt d
+load net {conc#142.itm(10)} -attr vt d
+load netBundle {conc#142.itm} 11 {conc#142.itm(0)} {conc#142.itm(1)} {conc#142.itm(2)} {conc#142.itm(3)} {conc#142.itm(4)} {conc#142.itm(5)} {conc#142.itm(6)} {conc#142.itm(7)} {conc#142.itm(8)} {conc#142.itm(9)} {conc#142.itm(10)} -attr xrf 5031 -attr oid 165 -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(9)} -attr xrf 5032 -attr oid 166 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {slc(r(2).sva#1).itm(0)} -attr vt d
+load net {slc(r(2).sva#1).itm(1)} -attr vt d
+load net {slc(r(2).sva#1).itm(2)} -attr vt d
+load net {slc(r(2).sva#1).itm(3)} -attr vt d
+load net {slc(r(2).sva#1).itm(4)} -attr vt d
+load net {slc(r(2).sva#1).itm(5)} -attr vt d
+load net {slc(r(2).sva#1).itm(6)} -attr vt d
+load net {slc(r(2).sva#1).itm(7)} -attr vt d
+load net {slc(r(2).sva#1).itm(8)} -attr vt d
+load net {slc(r(2).sva#1).itm(9)} -attr vt d
+load net {slc(r(2).sva#1).itm(10)} -attr vt d
+load net {slc(r(2).sva#1).itm(11)} -attr vt d
+load net {slc(r(2).sva#1).itm(12)} -attr vt d
+load net {slc(r(2).sva#1).itm(13)} -attr vt d
+load net {slc(r(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(r(2).sva#1).itm} 15 {slc(r(2).sva#1).itm(0)} {slc(r(2).sva#1).itm(1)} {slc(r(2).sva#1).itm(2)} {slc(r(2).sva#1).itm(3)} {slc(r(2).sva#1).itm(4)} {slc(r(2).sva#1).itm(5)} {slc(r(2).sva#1).itm(6)} {slc(r(2).sva#1).itm(7)} {slc(r(2).sva#1).itm(8)} {slc(r(2).sva#1).itm(9)} {slc(r(2).sva#1).itm(10)} {slc(r(2).sva#1).itm(11)} {slc(r(2).sva#1).itm(12)} {slc(r(2).sva#1).itm(13)} {slc(r(2).sva#1).itm(14)} -attr xrf 5033 -attr oid 167 -attr vt d -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {conc#143.itm(0)} -attr vt d
+load net {conc#143.itm(1)} -attr vt d
+load netBundle {conc#143.itm} 2 {conc#143.itm(0)} {conc#143.itm(1)} -attr xrf 5034 -attr oid 168 -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {slc(red#2.sg1.sva)#12.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#12.itm(1)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#12.itm} 2 {slc(red#2.sg1.sva)#12.itm(0)} {slc(red#2.sg1.sva)#12.itm(1)} -attr xrf 5035 -attr oid 169 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#12.itm}
+load net {ACC1:acc#45.itm(0)} -attr vt d
+load net {ACC1:acc#45.itm(1)} -attr vt d
+load net {ACC1:acc#45.itm(2)} -attr vt d
+load net {ACC1:acc#45.itm(3)} -attr vt d
+load net {ACC1:acc#45.itm(4)} -attr vt d
+load net {ACC1:acc#45.itm(5)} -attr vt d
+load net {ACC1:acc#45.itm(6)} -attr vt d
+load net {ACC1:acc#45.itm(7)} -attr vt d
+load net {ACC1:acc#45.itm(8)} -attr vt d
+load net {ACC1:acc#45.itm(9)} -attr vt d
+load net {ACC1:acc#45.itm(10)} -attr vt d
+load net {ACC1:acc#45.itm(11)} -attr vt d
+load net {ACC1:acc#45.itm(12)} -attr vt d
+load net {ACC1:acc#45.itm(13)} -attr vt d
+load net {ACC1:acc#45.itm(14)} -attr vt d
+load net {ACC1:acc#45.itm(15)} -attr vt d
+load netBundle {ACC1:acc#45.itm} 16 {ACC1:acc#45.itm(0)} {ACC1:acc#45.itm(1)} {ACC1:acc#45.itm(2)} {ACC1:acc#45.itm(3)} {ACC1:acc#45.itm(4)} {ACC1:acc#45.itm(5)} {ACC1:acc#45.itm(6)} {ACC1:acc#45.itm(7)} {ACC1:acc#45.itm(8)} {ACC1:acc#45.itm(9)} {ACC1:acc#45.itm(10)} {ACC1:acc#45.itm(11)} {ACC1:acc#45.itm(12)} {ACC1:acc#45.itm(13)} {ACC1:acc#45.itm(14)} {ACC1:acc#45.itm(15)} -attr xrf 5036 -attr oid 170 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:conc#49.itm(0)} -attr vt d
+load net {ACC1:conc#49.itm(1)} -attr vt d
+load net {ACC1:conc#49.itm(2)} -attr vt d
+load net {ACC1:conc#49.itm(3)} -attr vt d
+load net {ACC1:conc#49.itm(4)} -attr vt d
+load net {ACC1:conc#49.itm(5)} -attr vt d
+load net {ACC1:conc#49.itm(6)} -attr vt d
+load net {ACC1:conc#49.itm(7)} -attr vt d
+load net {ACC1:conc#49.itm(8)} -attr vt d
+load net {ACC1:conc#49.itm(9)} -attr vt d
+load net {ACC1:conc#49.itm(10)} -attr vt d
+load net {ACC1:conc#49.itm(11)} -attr vt d
+load net {ACC1:conc#49.itm(12)} -attr vt d
+load net {ACC1:conc#49.itm(13)} -attr vt d
+load net {ACC1:conc#49.itm(14)} -attr vt d
+load net {ACC1:conc#49.itm(15)} -attr vt d
+load netBundle {ACC1:conc#49.itm} 16 {ACC1:conc#49.itm(0)} {ACC1:conc#49.itm(1)} {ACC1:conc#49.itm(2)} {ACC1:conc#49.itm(3)} {ACC1:conc#49.itm(4)} {ACC1:conc#49.itm(5)} {ACC1:conc#49.itm(6)} {ACC1:conc#49.itm(7)} {ACC1:conc#49.itm(8)} {ACC1:conc#49.itm(9)} {ACC1:conc#49.itm(10)} {ACC1:conc#49.itm(11)} {ACC1:conc#49.itm(12)} {ACC1:conc#49.itm(13)} {ACC1:conc#49.itm(14)} {ACC1:conc#49.itm(15)} -attr xrf 5037 -attr oid 171 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(0)} -attr vt d
+load net {ACC1:acc#70.itm(1)} -attr vt d
+load net {ACC1:acc#70.itm(2)} -attr vt d
+load net {ACC1:acc#70.itm(3)} -attr vt d
+load net {ACC1:acc#70.itm(4)} -attr vt d
+load net {ACC1:acc#70.itm(5)} -attr vt d
+load net {ACC1:acc#70.itm(6)} -attr vt d
+load net {ACC1:acc#70.itm(7)} -attr vt d
+load net {ACC1:acc#70.itm(8)} -attr vt d
+load net {ACC1:acc#70.itm(9)} -attr vt d
+load net {ACC1:acc#70.itm(10)} -attr vt d
+load net {ACC1:acc#70.itm(11)} -attr vt d
+load net {ACC1:acc#70.itm(12)} -attr vt d
+load net {ACC1:acc#70.itm(13)} -attr vt d
+load net {ACC1:acc#70.itm(14)} -attr vt d
+load netBundle {ACC1:acc#70.itm} 15 {ACC1:acc#70.itm(0)} {ACC1:acc#70.itm(1)} {ACC1:acc#70.itm(2)} {ACC1:acc#70.itm(3)} {ACC1:acc#70.itm(4)} {ACC1:acc#70.itm(5)} {ACC1:acc#70.itm(6)} {ACC1:acc#70.itm(7)} {ACC1:acc#70.itm(8)} {ACC1:acc#70.itm(9)} {ACC1:acc#70.itm(10)} {ACC1:acc#70.itm(11)} {ACC1:acc#70.itm(12)} {ACC1:acc#70.itm(13)} {ACC1:acc#70.itm(14)} -attr xrf 5038 -attr oid 172 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {slc#1.itm(0)} -attr vt d
+load net {slc#1.itm(1)} -attr vt d
+load net {slc#1.itm(2)} -attr vt d
+load net {slc#1.itm(3)} -attr vt d
+load net {slc#1.itm(4)} -attr vt d
+load net {slc#1.itm(5)} -attr vt d
+load net {slc#1.itm(6)} -attr vt d
+load net {slc#1.itm(7)} -attr vt d
+load net {slc#1.itm(8)} -attr vt d
+load net {slc#1.itm(9)} -attr vt d
+load net {slc#1.itm(10)} -attr vt d
+load netBundle {slc#1.itm} 11 {slc#1.itm(0)} {slc#1.itm(1)} {slc#1.itm(2)} {slc#1.itm(3)} {slc#1.itm(4)} {slc#1.itm(5)} {slc#1.itm(6)} {slc#1.itm(7)} {slc#1.itm(8)} {slc#1.itm(9)} {slc#1.itm(10)} -attr xrf 5039 -attr oid 173 -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(0)} -attr vt d
+load net {acc#6.itm(1)} -attr vt d
+load net {acc#6.itm(2)} -attr vt d
+load net {acc#6.itm(3)} -attr vt d
+load net {acc#6.itm(4)} -attr vt d
+load net {acc#6.itm(5)} -attr vt d
+load net {acc#6.itm(6)} -attr vt d
+load net {acc#6.itm(7)} -attr vt d
+load net {acc#6.itm(8)} -attr vt d
+load net {acc#6.itm(9)} -attr vt d
+load net {acc#6.itm(10)} -attr vt d
+load net {acc#6.itm(11)} -attr vt d
+load netBundle {acc#6.itm} 12 {acc#6.itm(0)} {acc#6.itm(1)} {acc#6.itm(2)} {acc#6.itm(3)} {acc#6.itm(4)} {acc#6.itm(5)} {acc#6.itm(6)} {acc#6.itm(7)} {acc#6.itm(8)} {acc#6.itm(9)} {acc#6.itm(10)} {acc#6.itm(11)} -attr xrf 5040 -attr oid 174 -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {conc#144.itm(0)} -attr vt d
+load net {conc#144.itm(1)} -attr vt d
+load net {conc#144.itm(2)} -attr vt d
+load net {conc#144.itm(3)} -attr vt d
+load net {conc#144.itm(4)} -attr vt d
+load net {conc#144.itm(5)} -attr vt d
+load net {conc#144.itm(6)} -attr vt d
+load net {conc#144.itm(7)} -attr vt d
+load net {conc#144.itm(8)} -attr vt d
+load net {conc#144.itm(9)} -attr vt d
+load net {conc#144.itm(10)} -attr vt d
+load netBundle {conc#144.itm} 11 {conc#144.itm(0)} {conc#144.itm(1)} {conc#144.itm(2)} {conc#144.itm(3)} {conc#144.itm(4)} {conc#144.itm(5)} {conc#144.itm(6)} {conc#144.itm(7)} {conc#144.itm(8)} {conc#144.itm(9)} {conc#144.itm(10)} -attr xrf 5041 -attr oid 175 -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(0)} -attr vt d
+load net {ACC2:not#4.itm(1)} -attr vt d
+load net {ACC2:not#4.itm(2)} -attr vt d
+load net {ACC2:not#4.itm(3)} -attr vt d
+load net {ACC2:not#4.itm(4)} -attr vt d
+load net {ACC2:not#4.itm(5)} -attr vt d
+load net {ACC2:not#4.itm(6)} -attr vt d
+load net {ACC2:not#4.itm(7)} -attr vt d
+load net {ACC2:not#4.itm(8)} -attr vt d
+load net {ACC2:not#4.itm(9)} -attr vt d
+load netBundle {ACC2:not#4.itm} 10 {ACC2:not#4.itm(0)} {ACC2:not#4.itm(1)} {ACC2:not#4.itm(2)} {ACC2:not#4.itm(3)} {ACC2:not#4.itm(4)} {ACC2:not#4.itm(5)} {ACC2:not#4.itm(6)} {ACC2:not#4.itm(7)} {ACC2:not#4.itm(8)} {ACC2:not#4.itm(9)} -attr xrf 5042 -attr oid 176 -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0).itm} 10 {slc(regs.regs(0).sva.dfm:mx0).itm(0)} {slc(regs.regs(0).sva.dfm:mx0).itm(1)} {slc(regs.regs(0).sva.dfm:mx0).itm(2)} {slc(regs.regs(0).sva.dfm:mx0).itm(3)} {slc(regs.regs(0).sva.dfm:mx0).itm(4)} {slc(regs.regs(0).sva.dfm:mx0).itm(5)} {slc(regs.regs(0).sva.dfm:mx0).itm(6)} {slc(regs.regs(0).sva.dfm:mx0).itm(7)} {slc(regs.regs(0).sva.dfm:mx0).itm(8)} {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr xrf 5043 -attr oid 177 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {conc#145.itm(0)} -attr vt d
+load net {conc#145.itm(1)} -attr vt d
+load net {conc#145.itm(2)} -attr vt d
+load net {conc#145.itm(3)} -attr vt d
+load net {conc#145.itm(4)} -attr vt d
+load net {conc#145.itm(5)} -attr vt d
+load net {conc#145.itm(6)} -attr vt d
+load net {conc#145.itm(7)} -attr vt d
+load net {conc#145.itm(8)} -attr vt d
+load net {conc#145.itm(9)} -attr vt d
+load net {conc#145.itm(10)} -attr vt d
+load netBundle {conc#145.itm} 11 {conc#145.itm(0)} {conc#145.itm(1)} {conc#145.itm(2)} {conc#145.itm(3)} {conc#145.itm(4)} {conc#145.itm(5)} {conc#145.itm(6)} {conc#145.itm(7)} {conc#145.itm(8)} {conc#145.itm(9)} {conc#145.itm(10)} -attr xrf 5044 -attr oid 178 -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0).itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0).itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(9)} -attr xrf 5045 -attr oid 179 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {slc(b(2).sva#1).itm(0)} -attr vt d
+load net {slc(b(2).sva#1).itm(1)} -attr vt d
+load net {slc(b(2).sva#1).itm(2)} -attr vt d
+load net {slc(b(2).sva#1).itm(3)} -attr vt d
+load net {slc(b(2).sva#1).itm(4)} -attr vt d
+load net {slc(b(2).sva#1).itm(5)} -attr vt d
+load net {slc(b(2).sva#1).itm(6)} -attr vt d
+load net {slc(b(2).sva#1).itm(7)} -attr vt d
+load net {slc(b(2).sva#1).itm(8)} -attr vt d
+load net {slc(b(2).sva#1).itm(9)} -attr vt d
+load net {slc(b(2).sva#1).itm(10)} -attr vt d
+load net {slc(b(2).sva#1).itm(11)} -attr vt d
+load net {slc(b(2).sva#1).itm(12)} -attr vt d
+load net {slc(b(2).sva#1).itm(13)} -attr vt d
+load net {slc(b(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(b(2).sva#1).itm} 15 {slc(b(2).sva#1).itm(0)} {slc(b(2).sva#1).itm(1)} {slc(b(2).sva#1).itm(2)} {slc(b(2).sva#1).itm(3)} {slc(b(2).sva#1).itm(4)} {slc(b(2).sva#1).itm(5)} {slc(b(2).sva#1).itm(6)} {slc(b(2).sva#1).itm(7)} {slc(b(2).sva#1).itm(8)} {slc(b(2).sva#1).itm(9)} {slc(b(2).sva#1).itm(10)} {slc(b(2).sva#1).itm(11)} {slc(b(2).sva#1).itm(12)} {slc(b(2).sva#1).itm(13)} {slc(b(2).sva#1).itm(14)} -attr xrf 5046 -attr oid 180 -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {conc#146.itm(0)} -attr vt d
+load net {conc#146.itm(1)} -attr vt d
+load netBundle {conc#146.itm} 2 {conc#146.itm(0)} {conc#146.itm(1)} -attr xrf 5047 -attr oid 181 -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {FRAME:acc#28.itm(0)} -attr vt d
+load net {FRAME:acc#28.itm(1)} -attr vt d
+load net {FRAME:acc#28.itm(2)} -attr vt d
+load net {FRAME:acc#28.itm(3)} -attr vt d
+load net {FRAME:acc#28.itm(4)} -attr vt d
+load net {FRAME:acc#28.itm(5)} -attr vt d
+load netBundle {FRAME:acc#28.itm} 6 {FRAME:acc#28.itm(0)} {FRAME:acc#28.itm(1)} {FRAME:acc#28.itm(2)} {FRAME:acc#28.itm(3)} {FRAME:acc#28.itm(4)} {FRAME:acc#28.itm(5)} -attr xrf 5048 -attr oid 182 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#27.itm(0)} -attr vt d
+load net {FRAME:acc#27.itm(1)} -attr vt d
+load net {FRAME:acc#27.itm(2)} -attr vt d
+load net {FRAME:acc#27.itm(3)} -attr vt d
+load net {FRAME:acc#27.itm(4)} -attr vt d
+load netBundle {FRAME:acc#27.itm} 5 {FRAME:acc#27.itm(0)} {FRAME:acc#27.itm(1)} {FRAME:acc#27.itm(2)} {FRAME:acc#27.itm(3)} {FRAME:acc#27.itm(4)} -attr xrf 5049 -attr oid 183 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#25.itm(0)} -attr vt d
+load net {FRAME:acc#25.itm(1)} -attr vt d
+load net {FRAME:acc#25.itm(2)} -attr vt d
+load net {FRAME:acc#25.itm(3)} -attr vt d
+load netBundle {FRAME:acc#25.itm} 4 {FRAME:acc#25.itm(0)} {FRAME:acc#25.itm(1)} {FRAME:acc#25.itm(2)} {FRAME:acc#25.itm(3)} -attr xrf 5050 -attr oid 184 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {slc(blue#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#1.itm} 3 {slc(blue#2.sg1.sva)#1.itm(0)} {slc(blue#2.sg1.sva)#1.itm(1)} {slc(blue#2.sg1.sva)#1.itm(2)} -attr xrf 5051 -attr oid 185 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {FRAME:not#18.itm(0)} -attr vt d
+load net {FRAME:not#18.itm(1)} -attr vt d
+load net {FRAME:not#18.itm(2)} -attr vt d
+load netBundle {FRAME:not#18.itm} 3 {FRAME:not#18.itm(0)} {FRAME:not#18.itm(1)} {FRAME:not#18.itm(2)} -attr xrf 5052 -attr oid 186 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {slc(blue#2.sg1.sva)#3.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#3.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#3.itm} 3 {slc(blue#2.sg1.sva)#3.itm(0)} {slc(blue#2.sg1.sva)#3.itm(1)} {slc(blue#2.sg1.sva)#3.itm(2)} -attr xrf 5053 -attr oid 187 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {FRAME:acc#24.itm(0)} -attr vt d
+load net {FRAME:acc#24.itm(1)} -attr vt d
+load net {FRAME:acc#24.itm(2)} -attr vt d
+load net {FRAME:acc#24.itm(3)} -attr vt d
+load netBundle {FRAME:acc#24.itm} 4 {FRAME:acc#24.itm(0)} {FRAME:acc#24.itm(1)} {FRAME:acc#24.itm(2)} {FRAME:acc#24.itm(3)} -attr xrf 5054 -attr oid 188 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {conc#147.itm(0)} -attr vt d
+load net {conc#147.itm(1)} -attr vt d
+load net {conc#147.itm(2)} -attr vt d
+load netBundle {conc#147.itm} 3 {conc#147.itm(0)} {conc#147.itm(1)} {conc#147.itm(2)} -attr xrf 5055 -attr oid 189 -attr vt d -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {slc(blue#2.sg1.sva)#4.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#4.itm} 2 {slc(blue#2.sg1.sva)#4.itm(0)} {slc(blue#2.sg1.sva)#4.itm(1)} -attr xrf 5056 -attr oid 190 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#4.itm}
+load net {FRAME:acc#26.itm(0)} -attr vt d
+load net {FRAME:acc#26.itm(1)} -attr vt d
+load net {FRAME:acc#26.itm(2)} -attr vt d
+load net {FRAME:acc#26.itm(3)} -attr vt d
+load netBundle {FRAME:acc#26.itm} 4 {FRAME:acc#26.itm(0)} {FRAME:acc#26.itm(1)} {FRAME:acc#26.itm(2)} {FRAME:acc#26.itm(3)} -attr xrf 5057 -attr oid 191 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {slc(blue#2.sg1.sva)#5.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#5.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#5.itm} 3 {slc(blue#2.sg1.sva)#5.itm(0)} {slc(blue#2.sg1.sva)#5.itm(1)} {slc(blue#2.sg1.sva)#5.itm(2)} -attr xrf 5058 -attr oid 192 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {FRAME:not#17.itm(0)} -attr vt d
+load net {FRAME:not#17.itm(1)} -attr vt d
+load net {FRAME:not#17.itm(2)} -attr vt d
+load netBundle {FRAME:not#17.itm} 3 {FRAME:not#17.itm(0)} {FRAME:not#17.itm(1)} {FRAME:not#17.itm(2)} -attr xrf 5059 -attr oid 193 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {slc(blue#2.sg1.sva)#6.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#6.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#6.itm} 3 {slc(blue#2.sg1.sva)#6.itm(0)} {slc(blue#2.sg1.sva)#6.itm(1)} {slc(blue#2.sg1.sva)#6.itm(2)} -attr xrf 5060 -attr oid 194 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {ACC1:acc#44.itm(0)} -attr vt d
+load net {ACC1:acc#44.itm(1)} -attr vt d
+load net {ACC1:acc#44.itm(2)} -attr vt d
+load net {ACC1:acc#44.itm(3)} -attr vt d
+load net {ACC1:acc#44.itm(4)} -attr vt d
+load net {ACC1:acc#44.itm(5)} -attr vt d
+load net {ACC1:acc#44.itm(6)} -attr vt d
+load net {ACC1:acc#44.itm(7)} -attr vt d
+load net {ACC1:acc#44.itm(8)} -attr vt d
+load net {ACC1:acc#44.itm(9)} -attr vt d
+load net {ACC1:acc#44.itm(10)} -attr vt d
+load net {ACC1:acc#44.itm(11)} -attr vt d
+load net {ACC1:acc#44.itm(12)} -attr vt d
+load net {ACC1:acc#44.itm(13)} -attr vt d
+load net {ACC1:acc#44.itm(14)} -attr vt d
+load net {ACC1:acc#44.itm(15)} -attr vt d
+load netBundle {ACC1:acc#44.itm} 16 {ACC1:acc#44.itm(0)} {ACC1:acc#44.itm(1)} {ACC1:acc#44.itm(2)} {ACC1:acc#44.itm(3)} {ACC1:acc#44.itm(4)} {ACC1:acc#44.itm(5)} {ACC1:acc#44.itm(6)} {ACC1:acc#44.itm(7)} {ACC1:acc#44.itm(8)} {ACC1:acc#44.itm(9)} {ACC1:acc#44.itm(10)} {ACC1:acc#44.itm(11)} {ACC1:acc#44.itm(12)} {ACC1:acc#44.itm(13)} {ACC1:acc#44.itm(14)} {ACC1:acc#44.itm(15)} -attr xrf 5061 -attr oid 195 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:conc#47.itm(0)} -attr vt d
+load net {ACC1:conc#47.itm(1)} -attr vt d
+load net {ACC1:conc#47.itm(2)} -attr vt d
+load net {ACC1:conc#47.itm(3)} -attr vt d
+load net {ACC1:conc#47.itm(4)} -attr vt d
+load net {ACC1:conc#47.itm(5)} -attr vt d
+load net {ACC1:conc#47.itm(6)} -attr vt d
+load net {ACC1:conc#47.itm(7)} -attr vt d
+load net {ACC1:conc#47.itm(8)} -attr vt d
+load net {ACC1:conc#47.itm(9)} -attr vt d
+load net {ACC1:conc#47.itm(10)} -attr vt d
+load net {ACC1:conc#47.itm(11)} -attr vt d
+load net {ACC1:conc#47.itm(12)} -attr vt d
+load net {ACC1:conc#47.itm(13)} -attr vt d
+load net {ACC1:conc#47.itm(14)} -attr vt d
+load net {ACC1:conc#47.itm(15)} -attr vt d
+load netBundle {ACC1:conc#47.itm} 16 {ACC1:conc#47.itm(0)} {ACC1:conc#47.itm(1)} {ACC1:conc#47.itm(2)} {ACC1:conc#47.itm(3)} {ACC1:conc#47.itm(4)} {ACC1:conc#47.itm(5)} {ACC1:conc#47.itm(6)} {ACC1:conc#47.itm(7)} {ACC1:conc#47.itm(8)} {ACC1:conc#47.itm(9)} {ACC1:conc#47.itm(10)} {ACC1:conc#47.itm(11)} {ACC1:conc#47.itm(12)} {ACC1:conc#47.itm(13)} {ACC1:conc#47.itm(14)} {ACC1:conc#47.itm(15)} -attr xrf 5062 -attr oid 196 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(0)} -attr vt d
+load net {ACC1:acc#66.itm(1)} -attr vt d
+load net {ACC1:acc#66.itm(2)} -attr vt d
+load net {ACC1:acc#66.itm(3)} -attr vt d
+load net {ACC1:acc#66.itm(4)} -attr vt d
+load net {ACC1:acc#66.itm(5)} -attr vt d
+load net {ACC1:acc#66.itm(6)} -attr vt d
+load net {ACC1:acc#66.itm(7)} -attr vt d
+load net {ACC1:acc#66.itm(8)} -attr vt d
+load net {ACC1:acc#66.itm(9)} -attr vt d
+load net {ACC1:acc#66.itm(10)} -attr vt d
+load net {ACC1:acc#66.itm(11)} -attr vt d
+load net {ACC1:acc#66.itm(12)} -attr vt d
+load net {ACC1:acc#66.itm(13)} -attr vt d
+load net {ACC1:acc#66.itm(14)} -attr vt d
+load netBundle {ACC1:acc#66.itm} 15 {ACC1:acc#66.itm(0)} {ACC1:acc#66.itm(1)} {ACC1:acc#66.itm(2)} {ACC1:acc#66.itm(3)} {ACC1:acc#66.itm(4)} {ACC1:acc#66.itm(5)} {ACC1:acc#66.itm(6)} {ACC1:acc#66.itm(7)} {ACC1:acc#66.itm(8)} {ACC1:acc#66.itm(9)} {ACC1:acc#66.itm(10)} {ACC1:acc#66.itm(11)} {ACC1:acc#66.itm(12)} {ACC1:acc#66.itm(13)} {ACC1:acc#66.itm(14)} -attr xrf 5063 -attr oid 197 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {slc#2.itm(0)} -attr vt d
+load net {slc#2.itm(1)} -attr vt d
+load net {slc#2.itm(2)} -attr vt d
+load net {slc#2.itm(3)} -attr vt d
+load net {slc#2.itm(4)} -attr vt d
+load net {slc#2.itm(5)} -attr vt d
+load net {slc#2.itm(6)} -attr vt d
+load net {slc#2.itm(7)} -attr vt d
+load net {slc#2.itm(8)} -attr vt d
+load net {slc#2.itm(9)} -attr vt d
+load net {slc#2.itm(10)} -attr vt d
+load netBundle {slc#2.itm} 11 {slc#2.itm(0)} {slc#2.itm(1)} {slc#2.itm(2)} {slc#2.itm(3)} {slc#2.itm(4)} {slc#2.itm(5)} {slc#2.itm(6)} {slc#2.itm(7)} {slc#2.itm(8)} {slc#2.itm(9)} {slc#2.itm(10)} -attr xrf 5064 -attr oid 198 -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(0)} -attr vt d
+load net {acc#7.itm(1)} -attr vt d
+load net {acc#7.itm(2)} -attr vt d
+load net {acc#7.itm(3)} -attr vt d
+load net {acc#7.itm(4)} -attr vt d
+load net {acc#7.itm(5)} -attr vt d
+load net {acc#7.itm(6)} -attr vt d
+load net {acc#7.itm(7)} -attr vt d
+load net {acc#7.itm(8)} -attr vt d
+load net {acc#7.itm(9)} -attr vt d
+load net {acc#7.itm(10)} -attr vt d
+load net {acc#7.itm(11)} -attr vt d
+load netBundle {acc#7.itm} 12 {acc#7.itm(0)} {acc#7.itm(1)} {acc#7.itm(2)} {acc#7.itm(3)} {acc#7.itm(4)} {acc#7.itm(5)} {acc#7.itm(6)} {acc#7.itm(7)} {acc#7.itm(8)} {acc#7.itm(9)} {acc#7.itm(10)} {acc#7.itm(11)} -attr xrf 5065 -attr oid 199 -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {conc#148.itm(0)} -attr vt d
+load net {conc#148.itm(1)} -attr vt d
+load net {conc#148.itm(2)} -attr vt d
+load net {conc#148.itm(3)} -attr vt d
+load net {conc#148.itm(4)} -attr vt d
+load net {conc#148.itm(5)} -attr vt d
+load net {conc#148.itm(6)} -attr vt d
+load net {conc#148.itm(7)} -attr vt d
+load net {conc#148.itm(8)} -attr vt d
+load net {conc#148.itm(9)} -attr vt d
+load net {conc#148.itm(10)} -attr vt d
+load netBundle {conc#148.itm} 11 {conc#148.itm(0)} {conc#148.itm(1)} {conc#148.itm(2)} {conc#148.itm(3)} {conc#148.itm(4)} {conc#148.itm(5)} {conc#148.itm(6)} {conc#148.itm(7)} {conc#148.itm(8)} {conc#148.itm(9)} {conc#148.itm(10)} -attr xrf 5066 -attr oid 200 -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(0)} -attr vt d
+load net {ACC2:not#3.itm(1)} -attr vt d
+load net {ACC2:not#3.itm(2)} -attr vt d
+load net {ACC2:not#3.itm(3)} -attr vt d
+load net {ACC2:not#3.itm(4)} -attr vt d
+load net {ACC2:not#3.itm(5)} -attr vt d
+load net {ACC2:not#3.itm(6)} -attr vt d
+load net {ACC2:not#3.itm(7)} -attr vt d
+load net {ACC2:not#3.itm(8)} -attr vt d
+load net {ACC2:not#3.itm(9)} -attr vt d
+load netBundle {ACC2:not#3.itm} 10 {ACC2:not#3.itm(0)} {ACC2:not#3.itm(1)} {ACC2:not#3.itm(2)} {ACC2:not#3.itm(3)} {ACC2:not#3.itm(4)} {ACC2:not#3.itm(5)} {ACC2:not#3.itm(6)} {ACC2:not#3.itm(7)} {ACC2:not#3.itm(8)} {ACC2:not#3.itm(9)} -attr xrf 5067 -attr oid 201 -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr xrf 5068 -attr oid 202 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {conc#149.itm(0)} -attr vt d
+load net {conc#149.itm(1)} -attr vt d
+load net {conc#149.itm(2)} -attr vt d
+load net {conc#149.itm(3)} -attr vt d
+load net {conc#149.itm(4)} -attr vt d
+load net {conc#149.itm(5)} -attr vt d
+load net {conc#149.itm(6)} -attr vt d
+load net {conc#149.itm(7)} -attr vt d
+load net {conc#149.itm(8)} -attr vt d
+load net {conc#149.itm(9)} -attr vt d
+load net {conc#149.itm(10)} -attr vt d
+load netBundle {conc#149.itm} 11 {conc#149.itm(0)} {conc#149.itm(1)} {conc#149.itm(2)} {conc#149.itm(3)} {conc#149.itm(4)} {conc#149.itm(5)} {conc#149.itm(6)} {conc#149.itm(7)} {conc#149.itm(8)} {conc#149.itm(9)} {conc#149.itm(10)} -attr xrf 5069 -attr oid 203 -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(9)} -attr xrf 5070 -attr oid 204 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {slc(g(2).sva#1).itm(0)} -attr vt d
+load net {slc(g(2).sva#1).itm(1)} -attr vt d
+load net {slc(g(2).sva#1).itm(2)} -attr vt d
+load net {slc(g(2).sva#1).itm(3)} -attr vt d
+load net {slc(g(2).sva#1).itm(4)} -attr vt d
+load net {slc(g(2).sva#1).itm(5)} -attr vt d
+load net {slc(g(2).sva#1).itm(6)} -attr vt d
+load net {slc(g(2).sva#1).itm(7)} -attr vt d
+load net {slc(g(2).sva#1).itm(8)} -attr vt d
+load net {slc(g(2).sva#1).itm(9)} -attr vt d
+load net {slc(g(2).sva#1).itm(10)} -attr vt d
+load net {slc(g(2).sva#1).itm(11)} -attr vt d
+load net {slc(g(2).sva#1).itm(12)} -attr vt d
+load net {slc(g(2).sva#1).itm(13)} -attr vt d
+load net {slc(g(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(g(2).sva#1).itm} 15 {slc(g(2).sva#1).itm(0)} {slc(g(2).sva#1).itm(1)} {slc(g(2).sva#1).itm(2)} {slc(g(2).sva#1).itm(3)} {slc(g(2).sva#1).itm(4)} {slc(g(2).sva#1).itm(5)} {slc(g(2).sva#1).itm(6)} {slc(g(2).sva#1).itm(7)} {slc(g(2).sva#1).itm(8)} {slc(g(2).sva#1).itm(9)} {slc(g(2).sva#1).itm(10)} {slc(g(2).sva#1).itm(11)} {slc(g(2).sva#1).itm(12)} {slc(g(2).sva#1).itm(13)} {slc(g(2).sva#1).itm(14)} -attr xrf 5071 -attr oid 205 -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {conc#150.itm(0)} -attr vt d
+load net {conc#150.itm(1)} -attr vt d
+load netBundle {conc#150.itm} 2 {conc#150.itm(0)} {conc#150.itm(1)} -attr xrf 5072 -attr oid 206 -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {FRAME:acc#16.itm(0)} -attr vt d
+load net {FRAME:acc#16.itm(1)} -attr vt d
+load net {FRAME:acc#16.itm(2)} -attr vt d
+load net {FRAME:acc#16.itm(3)} -attr vt d
+load net {FRAME:acc#16.itm(4)} -attr vt d
+load net {FRAME:acc#16.itm(5)} -attr vt d
+load netBundle {FRAME:acc#16.itm} 6 {FRAME:acc#16.itm(0)} {FRAME:acc#16.itm(1)} {FRAME:acc#16.itm(2)} {FRAME:acc#16.itm(3)} {FRAME:acc#16.itm(4)} {FRAME:acc#16.itm(5)} -attr xrf 5073 -attr oid 207 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#15.itm(0)} -attr vt d
+load net {FRAME:acc#15.itm(1)} -attr vt d
+load net {FRAME:acc#15.itm(2)} -attr vt d
+load net {FRAME:acc#15.itm(3)} -attr vt d
+load net {FRAME:acc#15.itm(4)} -attr vt d
+load netBundle {FRAME:acc#15.itm} 5 {FRAME:acc#15.itm(0)} {FRAME:acc#15.itm(1)} {FRAME:acc#15.itm(2)} {FRAME:acc#15.itm(3)} {FRAME:acc#15.itm(4)} -attr xrf 5074 -attr oid 208 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#13.itm(0)} -attr vt d
+load net {FRAME:acc#13.itm(1)} -attr vt d
+load net {FRAME:acc#13.itm(2)} -attr vt d
+load net {FRAME:acc#13.itm(3)} -attr vt d
+load netBundle {FRAME:acc#13.itm} 4 {FRAME:acc#13.itm(0)} {FRAME:acc#13.itm(1)} {FRAME:acc#13.itm(2)} {FRAME:acc#13.itm(3)} -attr xrf 5075 -attr oid 209 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {slc(green#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#1.itm} 3 {slc(green#2.sg1.sva)#1.itm(0)} {slc(green#2.sg1.sva)#1.itm(1)} {slc(green#2.sg1.sva)#1.itm(2)} -attr xrf 5076 -attr oid 210 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {FRAME:not#10.itm(0)} -attr vt d
+load net {FRAME:not#10.itm(1)} -attr vt d
+load net {FRAME:not#10.itm(2)} -attr vt d
+load netBundle {FRAME:not#10.itm} 3 {FRAME:not#10.itm(0)} {FRAME:not#10.itm(1)} {FRAME:not#10.itm(2)} -attr xrf 5077 -attr oid 211 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {slc(green#2.sg1.sva)#3.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#3.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#3.itm} 3 {slc(green#2.sg1.sva)#3.itm(0)} {slc(green#2.sg1.sva)#3.itm(1)} {slc(green#2.sg1.sva)#3.itm(2)} -attr xrf 5078 -attr oid 212 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {FRAME:acc#12.itm(0)} -attr vt d
+load net {FRAME:acc#12.itm(1)} -attr vt d
+load net {FRAME:acc#12.itm(2)} -attr vt d
+load net {FRAME:acc#12.itm(3)} -attr vt d
+load netBundle {FRAME:acc#12.itm} 4 {FRAME:acc#12.itm(0)} {FRAME:acc#12.itm(1)} {FRAME:acc#12.itm(2)} {FRAME:acc#12.itm(3)} -attr xrf 5079 -attr oid 213 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {conc#151.itm(0)} -attr vt d
+load net {conc#151.itm(1)} -attr vt d
+load net {conc#151.itm(2)} -attr vt d
+load netBundle {conc#151.itm} 3 {conc#151.itm(0)} {conc#151.itm(1)} {conc#151.itm(2)} -attr xrf 5080 -attr oid 214 -attr vt d -attr @path {/sobel/sobel:core/conc#151.itm}
+load net {slc(green#2.sg1.sva)#4.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#4.itm} 2 {slc(green#2.sg1.sva)#4.itm(0)} {slc(green#2.sg1.sva)#4.itm(1)} -attr xrf 5081 -attr oid 215 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#4.itm}
+load net {FRAME:acc#14.itm(0)} -attr vt d
+load net {FRAME:acc#14.itm(1)} -attr vt d
+load net {FRAME:acc#14.itm(2)} -attr vt d
+load net {FRAME:acc#14.itm(3)} -attr vt d
+load netBundle {FRAME:acc#14.itm} 4 {FRAME:acc#14.itm(0)} {FRAME:acc#14.itm(1)} {FRAME:acc#14.itm(2)} {FRAME:acc#14.itm(3)} -attr xrf 5082 -attr oid 216 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {slc(green#2.sg1.sva)#5.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#5.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#5.itm} 3 {slc(green#2.sg1.sva)#5.itm(0)} {slc(green#2.sg1.sva)#5.itm(1)} {slc(green#2.sg1.sva)#5.itm(2)} -attr xrf 5083 -attr oid 217 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {FRAME:not#9.itm(0)} -attr vt d
+load net {FRAME:not#9.itm(1)} -attr vt d
+load net {FRAME:not#9.itm(2)} -attr vt d
+load netBundle {FRAME:not#9.itm} 3 {FRAME:not#9.itm(0)} {FRAME:not#9.itm(1)} {FRAME:not#9.itm(2)} -attr xrf 5084 -attr oid 218 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {slc(green#2.sg1.sva)#6.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#6.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#6.itm} 3 {slc(green#2.sg1.sva)#6.itm(0)} {slc(green#2.sg1.sva)#6.itm(1)} {slc(green#2.sg1.sva)#6.itm(2)} -attr xrf 5085 -attr oid 219 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {FRAME:for:mux#10.itm(0)} -attr vt d
+load net {FRAME:for:mux#10.itm(1)} -attr vt d
+load net {FRAME:for:mux#10.itm(2)} -attr vt d
+load net {FRAME:for:mux#10.itm(3)} -attr vt d
+load net {FRAME:for:mux#10.itm(4)} -attr vt d
+load net {FRAME:for:mux#10.itm(5)} -attr vt d
+load net {FRAME:for:mux#10.itm(6)} -attr vt d
+load net {FRAME:for:mux#10.itm(7)} -attr vt d
+load net {FRAME:for:mux#10.itm(8)} -attr vt d
+load net {FRAME:for:mux#10.itm(9)} -attr vt d
+load net {FRAME:for:mux#10.itm(10)} -attr vt d
+load net {FRAME:for:mux#10.itm(11)} -attr vt d
+load net {FRAME:for:mux#10.itm(12)} -attr vt d
+load net {FRAME:for:mux#10.itm(13)} -attr vt d
+load net {FRAME:for:mux#10.itm(14)} -attr vt d
+load net {FRAME:for:mux#10.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#10.itm} 16 {FRAME:for:mux#10.itm(0)} {FRAME:for:mux#10.itm(1)} {FRAME:for:mux#10.itm(2)} {FRAME:for:mux#10.itm(3)} {FRAME:for:mux#10.itm(4)} {FRAME:for:mux#10.itm(5)} {FRAME:for:mux#10.itm(6)} {FRAME:for:mux#10.itm(7)} {FRAME:for:mux#10.itm(8)} {FRAME:for:mux#10.itm(9)} {FRAME:for:mux#10.itm(10)} {FRAME:for:mux#10.itm(11)} {FRAME:for:mux#10.itm(12)} {FRAME:for:mux#10.itm(13)} {FRAME:for:mux#10.itm(14)} {FRAME:for:mux#10.itm(15)} -attr xrf 5086 -attr oid 220 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:exs#25.itm(0)} -attr vt d
+load net {FRAME:for:exs#25.itm(1)} -attr vt d
+load net {FRAME:for:exs#25.itm(2)} -attr vt d
+load net {FRAME:for:exs#25.itm(3)} -attr vt d
+load net {FRAME:for:exs#25.itm(4)} -attr vt d
+load net {FRAME:for:exs#25.itm(5)} -attr vt d
+load net {FRAME:for:exs#25.itm(6)} -attr vt d
+load net {FRAME:for:exs#25.itm(7)} -attr vt d
+load net {FRAME:for:exs#25.itm(8)} -attr vt d
+load net {FRAME:for:exs#25.itm(9)} -attr vt d
+load net {FRAME:for:exs#25.itm(10)} -attr vt d
+load net {FRAME:for:exs#25.itm(11)} -attr vt d
+load net {FRAME:for:exs#25.itm(12)} -attr vt d
+load net {FRAME:for:exs#25.itm(13)} -attr vt d
+load net {FRAME:for:exs#25.itm(14)} -attr vt d
+load net {FRAME:for:exs#25.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#25.itm} 16 {FRAME:for:exs#25.itm(0)} {FRAME:for:exs#25.itm(1)} {FRAME:for:exs#25.itm(2)} {FRAME:for:exs#25.itm(3)} {FRAME:for:exs#25.itm(4)} {FRAME:for:exs#25.itm(5)} {FRAME:for:exs#25.itm(6)} {FRAME:for:exs#25.itm(7)} {FRAME:for:exs#25.itm(8)} {FRAME:for:exs#25.itm(9)} {FRAME:for:exs#25.itm(10)} {FRAME:for:exs#25.itm(11)} {FRAME:for:exs#25.itm(12)} {FRAME:for:exs#25.itm(13)} {FRAME:for:exs#25.itm(14)} {FRAME:for:exs#25.itm(15)} -attr xrf 5087 -attr oid 221 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:slc#5.itm(0)} -attr vt d
+load net {ACC1:slc#5.itm(1)} -attr vt d
+load net {ACC1:slc#5.itm(2)} -attr vt d
+load net {ACC1:slc#5.itm(3)} -attr vt d
+load net {ACC1:slc#5.itm(4)} -attr vt d
+load net {ACC1:slc#5.itm(5)} -attr vt d
+load net {ACC1:slc#5.itm(6)} -attr vt d
+load net {ACC1:slc#5.itm(7)} -attr vt d
+load net {ACC1:slc#5.itm(8)} -attr vt d
+load net {ACC1:slc#5.itm(9)} -attr vt d
+load net {ACC1:slc#5.itm(10)} -attr vt d
+load netBundle {ACC1:slc#5.itm} 11 {ACC1:slc#5.itm(0)} {ACC1:slc#5.itm(1)} {ACC1:slc#5.itm(2)} {ACC1:slc#5.itm(3)} {ACC1:slc#5.itm(4)} {ACC1:slc#5.itm(5)} {ACC1:slc#5.itm(6)} {ACC1:slc#5.itm(7)} {ACC1:slc#5.itm(8)} {ACC1:slc#5.itm(9)} {ACC1:slc#5.itm(10)} -attr xrf 5088 -attr oid 222 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#5.itm}
+load net {ACC1:acc#52.itm(0)} -attr vt d
+load net {ACC1:acc#52.itm(1)} -attr vt d
+load net {ACC1:acc#52.itm(2)} -attr vt d
+load net {ACC1:acc#52.itm(3)} -attr vt d
+load net {ACC1:acc#52.itm(4)} -attr vt d
+load net {ACC1:acc#52.itm(5)} -attr vt d
+load net {ACC1:acc#52.itm(6)} -attr vt d
+load net {ACC1:acc#52.itm(7)} -attr vt d
+load net {ACC1:acc#52.itm(8)} -attr vt d
+load net {ACC1:acc#52.itm(9)} -attr vt d
+load net {ACC1:acc#52.itm(10)} -attr vt d
+load net {ACC1:acc#52.itm(11)} -attr vt d
+load netBundle {ACC1:acc#52.itm} 12 {ACC1:acc#52.itm(0)} {ACC1:acc#52.itm(1)} {ACC1:acc#52.itm(2)} {ACC1:acc#52.itm(3)} {ACC1:acc#52.itm(4)} {ACC1:acc#52.itm(5)} {ACC1:acc#52.itm(6)} {ACC1:acc#52.itm(7)} {ACC1:acc#52.itm(8)} {ACC1:acc#52.itm(9)} {ACC1:acc#52.itm(10)} {ACC1:acc#52.itm(11)} -attr xrf 5089 -attr oid 223 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {conc#152.itm(0)} -attr vt d
+load net {conc#152.itm(1)} -attr vt d
+load net {conc#152.itm(2)} -attr vt d
+load net {conc#152.itm(3)} -attr vt d
+load net {conc#152.itm(4)} -attr vt d
+load net {conc#152.itm(5)} -attr vt d
+load net {conc#152.itm(6)} -attr vt d
+load net {conc#152.itm(7)} -attr vt d
+load net {conc#152.itm(8)} -attr vt d
+load net {conc#152.itm(9)} -attr vt d
+load net {conc#152.itm(10)} -attr vt d
+load netBundle {conc#152.itm} 11 {conc#152.itm(0)} {conc#152.itm(1)} {conc#152.itm(2)} {conc#152.itm(3)} {conc#152.itm(4)} {conc#152.itm(5)} {conc#152.itm(6)} {conc#152.itm(7)} {conc#152.itm(8)} {conc#152.itm(9)} {conc#152.itm(10)} -attr xrf 5090 -attr oid 224 -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(0)} -attr vt d
+load net {ACC1:not#14.itm(1)} -attr vt d
+load net {ACC1:not#14.itm(2)} -attr vt d
+load net {ACC1:not#14.itm(3)} -attr vt d
+load net {ACC1:not#14.itm(4)} -attr vt d
+load net {ACC1:not#14.itm(5)} -attr vt d
+load net {ACC1:not#14.itm(6)} -attr vt d
+load net {ACC1:not#14.itm(7)} -attr vt d
+load net {ACC1:not#14.itm(8)} -attr vt d
+load net {ACC1:not#14.itm(9)} -attr vt d
+load netBundle {ACC1:not#14.itm} 10 {ACC1:not#14.itm(0)} {ACC1:not#14.itm(1)} {ACC1:not#14.itm(2)} {ACC1:not#14.itm(3)} {ACC1:not#14.itm(4)} {ACC1:not#14.itm(5)} {ACC1:not#14.itm(6)} {ACC1:not#14.itm(7)} {ACC1:not#14.itm(8)} {ACC1:not#14.itm(9)} -attr xrf 5091 -attr oid 225 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {slc(regs.regs(0).sva#1).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#1).itm} 10 {slc(regs.regs(0).sva#1).itm(0)} {slc(regs.regs(0).sva#1).itm(1)} {slc(regs.regs(0).sva#1).itm(2)} {slc(regs.regs(0).sva#1).itm(3)} {slc(regs.regs(0).sva#1).itm(4)} {slc(regs.regs(0).sva#1).itm(5)} {slc(regs.regs(0).sva#1).itm(6)} {slc(regs.regs(0).sva#1).itm(7)} {slc(regs.regs(0).sva#1).itm(8)} {slc(regs.regs(0).sva#1).itm(9)} -attr xrf 5092 -attr oid 226 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {conc#153.itm(0)} -attr vt d
+load net {conc#153.itm(1)} -attr vt d
+load net {conc#153.itm(2)} -attr vt d
+load net {conc#153.itm(3)} -attr vt d
+load net {conc#153.itm(4)} -attr vt d
+load net {conc#153.itm(5)} -attr vt d
+load net {conc#153.itm(6)} -attr vt d
+load net {conc#153.itm(7)} -attr vt d
+load net {conc#153.itm(8)} -attr vt d
+load net {conc#153.itm(9)} -attr vt d
+load net {conc#153.itm(10)} -attr vt d
+load netBundle {conc#153.itm} 11 {conc#153.itm(0)} {conc#153.itm(1)} {conc#153.itm(2)} {conc#153.itm(3)} {conc#153.itm(4)} {conc#153.itm(5)} {conc#153.itm(6)} {conc#153.itm(7)} {conc#153.itm(8)} {conc#153.itm(9)} {conc#153.itm(10)} -attr xrf 5093 -attr oid 227 -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {slc(regs.regs(1).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva).itm} 10 {slc(regs.regs(1).sva).itm(0)} {slc(regs.regs(1).sva).itm(1)} {slc(regs.regs(1).sva).itm(2)} {slc(regs.regs(1).sva).itm(3)} {slc(regs.regs(1).sva).itm(4)} {slc(regs.regs(1).sva).itm(5)} {slc(regs.regs(1).sva).itm(6)} {slc(regs.regs(1).sva).itm(7)} {slc(regs.regs(1).sva).itm(8)} {slc(regs.regs(1).sva).itm(9)} -attr xrf 5094 -attr oid 228 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {FRAME:for:mul#8.itm(0)} -attr vt d
+load net {FRAME:for:mul#8.itm(1)} -attr vt d
+load net {FRAME:for:mul#8.itm(2)} -attr vt d
+load net {FRAME:for:mul#8.itm(3)} -attr vt d
+load net {FRAME:for:mul#8.itm(4)} -attr vt d
+load net {FRAME:for:mul#8.itm(5)} -attr vt d
+load net {FRAME:for:mul#8.itm(6)} -attr vt d
+load net {FRAME:for:mul#8.itm(7)} -attr vt d
+load net {FRAME:for:mul#8.itm(8)} -attr vt d
+load net {FRAME:for:mul#8.itm(9)} -attr vt d
+load net {FRAME:for:mul#8.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#8.itm} 11 {FRAME:for:mul#8.itm(0)} {FRAME:for:mul#8.itm(1)} {FRAME:for:mul#8.itm(2)} {FRAME:for:mul#8.itm(3)} {FRAME:for:mul#8.itm(4)} {FRAME:for:mul#8.itm(5)} {FRAME:for:mul#8.itm(6)} {FRAME:for:mul#8.itm(7)} {FRAME:for:mul#8.itm(8)} {FRAME:for:mul#8.itm(9)} {FRAME:for:mul#8.itm(10)} -attr xrf 5095 -attr oid 229 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {regs.operator[]#17:mux.itm(0)} -attr vt d
+load net {regs.operator[]#17:mux.itm(1)} -attr vt d
+load net {regs.operator[]#17:mux.itm(2)} -attr vt d
+load net {regs.operator[]#17:mux.itm(3)} -attr vt d
+load net {regs.operator[]#17:mux.itm(4)} -attr vt d
+load net {regs.operator[]#17:mux.itm(5)} -attr vt d
+load net {regs.operator[]#17:mux.itm(6)} -attr vt d
+load net {regs.operator[]#17:mux.itm(7)} -attr vt d
+load net {regs.operator[]#17:mux.itm(8)} -attr vt d
+load net {regs.operator[]#17:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#17:mux.itm} 10 {regs.operator[]#17:mux.itm(0)} {regs.operator[]#17:mux.itm(1)} {regs.operator[]#17:mux.itm(2)} {regs.operator[]#17:mux.itm(3)} {regs.operator[]#17:mux.itm(4)} {regs.operator[]#17:mux.itm(5)} {regs.operator[]#17:mux.itm(6)} {regs.operator[]#17:mux.itm(7)} {regs.operator[]#17:mux.itm(8)} {regs.operator[]#17:mux.itm(9)} -attr xrf 5096 -attr oid 230 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(9)} -attr xrf 5097 -attr oid 231 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0).itm} 10 {slc(regs.regs(1).sva.dfm:mx0).itm(0)} {slc(regs.regs(1).sva.dfm:mx0).itm(1)} {slc(regs.regs(1).sva.dfm:mx0).itm(2)} {slc(regs.regs(1).sva.dfm:mx0).itm(3)} {slc(regs.regs(1).sva.dfm:mx0).itm(4)} {slc(regs.regs(1).sva.dfm:mx0).itm(5)} {slc(regs.regs(1).sva.dfm:mx0).itm(6)} {slc(regs.regs(1).sva.dfm:mx0).itm(7)} {slc(regs.regs(1).sva.dfm:mx0).itm(8)} {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr xrf 5098 -attr oid 232 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr xrf 5099 -attr oid 233 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {FRAME:for:mux#9.itm(0)} -attr vt d
+load net {FRAME:for:mux#9.itm(1)} -attr vt d
+load net {FRAME:for:mux#9.itm(2)} -attr vt d
+load net {FRAME:for:mux#9.itm(3)} -attr vt d
+load net {FRAME:for:mux#9.itm(4)} -attr vt d
+load net {FRAME:for:mux#9.itm(5)} -attr vt d
+load net {FRAME:for:mux#9.itm(6)} -attr vt d
+load net {FRAME:for:mux#9.itm(7)} -attr vt d
+load net {FRAME:for:mux#9.itm(8)} -attr vt d
+load net {FRAME:for:mux#9.itm(9)} -attr vt d
+load net {FRAME:for:mux#9.itm(10)} -attr vt d
+load net {FRAME:for:mux#9.itm(11)} -attr vt d
+load net {FRAME:for:mux#9.itm(12)} -attr vt d
+load net {FRAME:for:mux#9.itm(13)} -attr vt d
+load net {FRAME:for:mux#9.itm(14)} -attr vt d
+load net {FRAME:for:mux#9.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#9.itm} 16 {FRAME:for:mux#9.itm(0)} {FRAME:for:mux#9.itm(1)} {FRAME:for:mux#9.itm(2)} {FRAME:for:mux#9.itm(3)} {FRAME:for:mux#9.itm(4)} {FRAME:for:mux#9.itm(5)} {FRAME:for:mux#9.itm(6)} {FRAME:for:mux#9.itm(7)} {FRAME:for:mux#9.itm(8)} {FRAME:for:mux#9.itm(9)} {FRAME:for:mux#9.itm(10)} {FRAME:for:mux#9.itm(11)} {FRAME:for:mux#9.itm(12)} {FRAME:for:mux#9.itm(13)} {FRAME:for:mux#9.itm(14)} {FRAME:for:mux#9.itm(15)} -attr xrf 5100 -attr oid 234 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:exs#22.itm(0)} -attr vt d
+load net {FRAME:for:exs#22.itm(1)} -attr vt d
+load net {FRAME:for:exs#22.itm(2)} -attr vt d
+load net {FRAME:for:exs#22.itm(3)} -attr vt d
+load net {FRAME:for:exs#22.itm(4)} -attr vt d
+load net {FRAME:for:exs#22.itm(5)} -attr vt d
+load net {FRAME:for:exs#22.itm(6)} -attr vt d
+load net {FRAME:for:exs#22.itm(7)} -attr vt d
+load net {FRAME:for:exs#22.itm(8)} -attr vt d
+load net {FRAME:for:exs#22.itm(9)} -attr vt d
+load net {FRAME:for:exs#22.itm(10)} -attr vt d
+load net {FRAME:for:exs#22.itm(11)} -attr vt d
+load net {FRAME:for:exs#22.itm(12)} -attr vt d
+load net {FRAME:for:exs#22.itm(13)} -attr vt d
+load net {FRAME:for:exs#22.itm(14)} -attr vt d
+load net {FRAME:for:exs#22.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#22.itm} 16 {FRAME:for:exs#22.itm(0)} {FRAME:for:exs#22.itm(1)} {FRAME:for:exs#22.itm(2)} {FRAME:for:exs#22.itm(3)} {FRAME:for:exs#22.itm(4)} {FRAME:for:exs#22.itm(5)} {FRAME:for:exs#22.itm(6)} {FRAME:for:exs#22.itm(7)} {FRAME:for:exs#22.itm(8)} {FRAME:for:exs#22.itm(9)} {FRAME:for:exs#22.itm(10)} {FRAME:for:exs#22.itm(11)} {FRAME:for:exs#22.itm(12)} {FRAME:for:exs#22.itm(13)} {FRAME:for:exs#22.itm(14)} {FRAME:for:exs#22.itm(15)} -attr xrf 5101 -attr oid 235 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:slc#2.itm(0)} -attr vt d
+load net {ACC1:slc#2.itm(1)} -attr vt d
+load net {ACC1:slc#2.itm(2)} -attr vt d
+load net {ACC1:slc#2.itm(3)} -attr vt d
+load net {ACC1:slc#2.itm(4)} -attr vt d
+load net {ACC1:slc#2.itm(5)} -attr vt d
+load net {ACC1:slc#2.itm(6)} -attr vt d
+load net {ACC1:slc#2.itm(7)} -attr vt d
+load net {ACC1:slc#2.itm(8)} -attr vt d
+load net {ACC1:slc#2.itm(9)} -attr vt d
+load net {ACC1:slc#2.itm(10)} -attr vt d
+load netBundle {ACC1:slc#2.itm} 11 {ACC1:slc#2.itm(0)} {ACC1:slc#2.itm(1)} {ACC1:slc#2.itm(2)} {ACC1:slc#2.itm(3)} {ACC1:slc#2.itm(4)} {ACC1:slc#2.itm(5)} {ACC1:slc#2.itm(6)} {ACC1:slc#2.itm(7)} {ACC1:slc#2.itm(8)} {ACC1:slc#2.itm(9)} {ACC1:slc#2.itm(10)} -attr xrf 5102 -attr oid 236 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#49.itm(0)} -attr vt d
+load net {ACC1:acc#49.itm(1)} -attr vt d
+load net {ACC1:acc#49.itm(2)} -attr vt d
+load net {ACC1:acc#49.itm(3)} -attr vt d
+load net {ACC1:acc#49.itm(4)} -attr vt d
+load net {ACC1:acc#49.itm(5)} -attr vt d
+load net {ACC1:acc#49.itm(6)} -attr vt d
+load net {ACC1:acc#49.itm(7)} -attr vt d
+load net {ACC1:acc#49.itm(8)} -attr vt d
+load net {ACC1:acc#49.itm(9)} -attr vt d
+load net {ACC1:acc#49.itm(10)} -attr vt d
+load net {ACC1:acc#49.itm(11)} -attr vt d
+load netBundle {ACC1:acc#49.itm} 12 {ACC1:acc#49.itm(0)} {ACC1:acc#49.itm(1)} {ACC1:acc#49.itm(2)} {ACC1:acc#49.itm(3)} {ACC1:acc#49.itm(4)} {ACC1:acc#49.itm(5)} {ACC1:acc#49.itm(6)} {ACC1:acc#49.itm(7)} {ACC1:acc#49.itm(8)} {ACC1:acc#49.itm(9)} {ACC1:acc#49.itm(10)} {ACC1:acc#49.itm(11)} -attr xrf 5103 -attr oid 237 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {conc#154.itm(0)} -attr vt d
+load net {conc#154.itm(1)} -attr vt d
+load net {conc#154.itm(2)} -attr vt d
+load net {conc#154.itm(3)} -attr vt d
+load net {conc#154.itm(4)} -attr vt d
+load net {conc#154.itm(5)} -attr vt d
+load net {conc#154.itm(6)} -attr vt d
+load net {conc#154.itm(7)} -attr vt d
+load net {conc#154.itm(8)} -attr vt d
+load net {conc#154.itm(9)} -attr vt d
+load net {conc#154.itm(10)} -attr vt d
+load netBundle {conc#154.itm} 11 {conc#154.itm(0)} {conc#154.itm(1)} {conc#154.itm(2)} {conc#154.itm(3)} {conc#154.itm(4)} {conc#154.itm(5)} {conc#154.itm(6)} {conc#154.itm(7)} {conc#154.itm(8)} {conc#154.itm(9)} {conc#154.itm(10)} -attr xrf 5104 -attr oid 238 -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(0)} -attr vt d
+load net {ACC1:not#16.itm(1)} -attr vt d
+load net {ACC1:not#16.itm(2)} -attr vt d
+load net {ACC1:not#16.itm(3)} -attr vt d
+load net {ACC1:not#16.itm(4)} -attr vt d
+load net {ACC1:not#16.itm(5)} -attr vt d
+load net {ACC1:not#16.itm(6)} -attr vt d
+load net {ACC1:not#16.itm(7)} -attr vt d
+load net {ACC1:not#16.itm(8)} -attr vt d
+load net {ACC1:not#16.itm(9)} -attr vt d
+load netBundle {ACC1:not#16.itm} 10 {ACC1:not#16.itm(0)} {ACC1:not#16.itm(1)} {ACC1:not#16.itm(2)} {ACC1:not#16.itm(3)} {ACC1:not#16.itm(4)} {ACC1:not#16.itm(5)} {ACC1:not#16.itm(6)} {ACC1:not#16.itm(7)} {ACC1:not#16.itm(8)} {ACC1:not#16.itm(9)} -attr xrf 5105 -attr oid 239 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {slc(regs.regs(0).sva#4).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#4).itm} 10 {slc(regs.regs(0).sva#4).itm(0)} {slc(regs.regs(0).sva#4).itm(1)} {slc(regs.regs(0).sva#4).itm(2)} {slc(regs.regs(0).sva#4).itm(3)} {slc(regs.regs(0).sva#4).itm(4)} {slc(regs.regs(0).sva#4).itm(5)} {slc(regs.regs(0).sva#4).itm(6)} {slc(regs.regs(0).sva#4).itm(7)} {slc(regs.regs(0).sva#4).itm(8)} {slc(regs.regs(0).sva#4).itm(9)} -attr xrf 5106 -attr oid 240 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {conc#155.itm(0)} -attr vt d
+load net {conc#155.itm(1)} -attr vt d
+load net {conc#155.itm(2)} -attr vt d
+load net {conc#155.itm(3)} -attr vt d
+load net {conc#155.itm(4)} -attr vt d
+load net {conc#155.itm(5)} -attr vt d
+load net {conc#155.itm(6)} -attr vt d
+load net {conc#155.itm(7)} -attr vt d
+load net {conc#155.itm(8)} -attr vt d
+load net {conc#155.itm(9)} -attr vt d
+load net {conc#155.itm(10)} -attr vt d
+load netBundle {conc#155.itm} 11 {conc#155.itm(0)} {conc#155.itm(1)} {conc#155.itm(2)} {conc#155.itm(3)} {conc#155.itm(4)} {conc#155.itm(5)} {conc#155.itm(6)} {conc#155.itm(7)} {conc#155.itm(8)} {conc#155.itm(9)} {conc#155.itm(10)} -attr xrf 5107 -attr oid 241 -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {slc(regs.regs(1).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#3.itm} 10 {slc(regs.regs(1).sva)#3.itm(0)} {slc(regs.regs(1).sva)#3.itm(1)} {slc(regs.regs(1).sva)#3.itm(2)} {slc(regs.regs(1).sva)#3.itm(3)} {slc(regs.regs(1).sva)#3.itm(4)} {slc(regs.regs(1).sva)#3.itm(5)} {slc(regs.regs(1).sva)#3.itm(6)} {slc(regs.regs(1).sva)#3.itm(7)} {slc(regs.regs(1).sva)#3.itm(8)} {slc(regs.regs(1).sva)#3.itm(9)} -attr xrf 5108 -attr oid 242 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {FRAME:for:mul#2.itm(0)} -attr vt d
+load net {FRAME:for:mul#2.itm(1)} -attr vt d
+load net {FRAME:for:mul#2.itm(2)} -attr vt d
+load net {FRAME:for:mul#2.itm(3)} -attr vt d
+load net {FRAME:for:mul#2.itm(4)} -attr vt d
+load net {FRAME:for:mul#2.itm(5)} -attr vt d
+load net {FRAME:for:mul#2.itm(6)} -attr vt d
+load net {FRAME:for:mul#2.itm(7)} -attr vt d
+load net {FRAME:for:mul#2.itm(8)} -attr vt d
+load net {FRAME:for:mul#2.itm(9)} -attr vt d
+load net {FRAME:for:mul#2.itm(10)} -attr vt d
+load net {FRAME:for:mul#2.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul#2.itm} 12 {FRAME:for:mul#2.itm(0)} {FRAME:for:mul#2.itm(1)} {FRAME:for:mul#2.itm(2)} {FRAME:for:mul#2.itm(3)} {FRAME:for:mul#2.itm(4)} {FRAME:for:mul#2.itm(5)} {FRAME:for:mul#2.itm(6)} {FRAME:for:mul#2.itm(7)} {FRAME:for:mul#2.itm(8)} {FRAME:for:mul#2.itm(9)} {FRAME:for:mul#2.itm(10)} {FRAME:for:mul#2.itm(11)} -attr xrf 5109 -attr oid 243 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {regs.operator[]#11:mux.itm(0)} -attr vt d
+load net {regs.operator[]#11:mux.itm(1)} -attr vt d
+load net {regs.operator[]#11:mux.itm(2)} -attr vt d
+load net {regs.operator[]#11:mux.itm(3)} -attr vt d
+load net {regs.operator[]#11:mux.itm(4)} -attr vt d
+load net {regs.operator[]#11:mux.itm(5)} -attr vt d
+load net {regs.operator[]#11:mux.itm(6)} -attr vt d
+load net {regs.operator[]#11:mux.itm(7)} -attr vt d
+load net {regs.operator[]#11:mux.itm(8)} -attr vt d
+load net {regs.operator[]#11:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#11:mux.itm} 10 {regs.operator[]#11:mux.itm(0)} {regs.operator[]#11:mux.itm(1)} {regs.operator[]#11:mux.itm(2)} {regs.operator[]#11:mux.itm(3)} {regs.operator[]#11:mux.itm(4)} {regs.operator[]#11:mux.itm(5)} {regs.operator[]#11:mux.itm(6)} {regs.operator[]#11:mux.itm(7)} {regs.operator[]#11:mux.itm(8)} {regs.operator[]#11:mux.itm(9)} -attr xrf 5110 -attr oid 244 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(9)} -attr xrf 5111 -attr oid 245 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr xrf 5112 -attr oid 246 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#6.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#6.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(9)} -attr xrf 5113 -attr oid 247 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {conc#156.itm(0)} -attr vt d
+load net {conc#156.itm(1)} -attr vt d
+load netBundle {conc#156.itm} 2 {conc#156.itm(0)} {conc#156.itm(1)} -attr xrf 5114 -attr oid 248 -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {FRAME:for:mux#8.itm(0)} -attr vt d
+load net {FRAME:for:mux#8.itm(1)} -attr vt d
+load net {FRAME:for:mux#8.itm(2)} -attr vt d
+load net {FRAME:for:mux#8.itm(3)} -attr vt d
+load net {FRAME:for:mux#8.itm(4)} -attr vt d
+load net {FRAME:for:mux#8.itm(5)} -attr vt d
+load net {FRAME:for:mux#8.itm(6)} -attr vt d
+load net {FRAME:for:mux#8.itm(7)} -attr vt d
+load net {FRAME:for:mux#8.itm(8)} -attr vt d
+load net {FRAME:for:mux#8.itm(9)} -attr vt d
+load net {FRAME:for:mux#8.itm(10)} -attr vt d
+load net {FRAME:for:mux#8.itm(11)} -attr vt d
+load net {FRAME:for:mux#8.itm(12)} -attr vt d
+load net {FRAME:for:mux#8.itm(13)} -attr vt d
+load net {FRAME:for:mux#8.itm(14)} -attr vt d
+load net {FRAME:for:mux#8.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#8.itm} 16 {FRAME:for:mux#8.itm(0)} {FRAME:for:mux#8.itm(1)} {FRAME:for:mux#8.itm(2)} {FRAME:for:mux#8.itm(3)} {FRAME:for:mux#8.itm(4)} {FRAME:for:mux#8.itm(5)} {FRAME:for:mux#8.itm(6)} {FRAME:for:mux#8.itm(7)} {FRAME:for:mux#8.itm(8)} {FRAME:for:mux#8.itm(9)} {FRAME:for:mux#8.itm(10)} {FRAME:for:mux#8.itm(11)} {FRAME:for:mux#8.itm(12)} {FRAME:for:mux#8.itm(13)} {FRAME:for:mux#8.itm(14)} {FRAME:for:mux#8.itm(15)} -attr xrf 5115 -attr oid 249 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:exs#24.itm(0)} -attr vt d
+load net {FRAME:for:exs#24.itm(1)} -attr vt d
+load net {FRAME:for:exs#24.itm(2)} -attr vt d
+load net {FRAME:for:exs#24.itm(3)} -attr vt d
+load net {FRAME:for:exs#24.itm(4)} -attr vt d
+load net {FRAME:for:exs#24.itm(5)} -attr vt d
+load net {FRAME:for:exs#24.itm(6)} -attr vt d
+load net {FRAME:for:exs#24.itm(7)} -attr vt d
+load net {FRAME:for:exs#24.itm(8)} -attr vt d
+load net {FRAME:for:exs#24.itm(9)} -attr vt d
+load net {FRAME:for:exs#24.itm(10)} -attr vt d
+load net {FRAME:for:exs#24.itm(11)} -attr vt d
+load net {FRAME:for:exs#24.itm(12)} -attr vt d
+load net {FRAME:for:exs#24.itm(13)} -attr vt d
+load net {FRAME:for:exs#24.itm(14)} -attr vt d
+load net {FRAME:for:exs#24.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#24.itm} 16 {FRAME:for:exs#24.itm(0)} {FRAME:for:exs#24.itm(1)} {FRAME:for:exs#24.itm(2)} {FRAME:for:exs#24.itm(3)} {FRAME:for:exs#24.itm(4)} {FRAME:for:exs#24.itm(5)} {FRAME:for:exs#24.itm(6)} {FRAME:for:exs#24.itm(7)} {FRAME:for:exs#24.itm(8)} {FRAME:for:exs#24.itm(9)} {FRAME:for:exs#24.itm(10)} {FRAME:for:exs#24.itm(11)} {FRAME:for:exs#24.itm(12)} {FRAME:for:exs#24.itm(13)} {FRAME:for:exs#24.itm(14)} {FRAME:for:exs#24.itm(15)} -attr xrf 5116 -attr oid 250 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:slc#4.itm(0)} -attr vt d
+load net {ACC1:slc#4.itm(1)} -attr vt d
+load net {ACC1:slc#4.itm(2)} -attr vt d
+load net {ACC1:slc#4.itm(3)} -attr vt d
+load net {ACC1:slc#4.itm(4)} -attr vt d
+load net {ACC1:slc#4.itm(5)} -attr vt d
+load net {ACC1:slc#4.itm(6)} -attr vt d
+load net {ACC1:slc#4.itm(7)} -attr vt d
+load net {ACC1:slc#4.itm(8)} -attr vt d
+load net {ACC1:slc#4.itm(9)} -attr vt d
+load net {ACC1:slc#4.itm(10)} -attr vt d
+load netBundle {ACC1:slc#4.itm} 11 {ACC1:slc#4.itm(0)} {ACC1:slc#4.itm(1)} {ACC1:slc#4.itm(2)} {ACC1:slc#4.itm(3)} {ACC1:slc#4.itm(4)} {ACC1:slc#4.itm(5)} {ACC1:slc#4.itm(6)} {ACC1:slc#4.itm(7)} {ACC1:slc#4.itm(8)} {ACC1:slc#4.itm(9)} {ACC1:slc#4.itm(10)} -attr xrf 5117 -attr oid 251 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#4.itm}
+load net {ACC1:acc#51.itm(0)} -attr vt d
+load net {ACC1:acc#51.itm(1)} -attr vt d
+load net {ACC1:acc#51.itm(2)} -attr vt d
+load net {ACC1:acc#51.itm(3)} -attr vt d
+load net {ACC1:acc#51.itm(4)} -attr vt d
+load net {ACC1:acc#51.itm(5)} -attr vt d
+load net {ACC1:acc#51.itm(6)} -attr vt d
+load net {ACC1:acc#51.itm(7)} -attr vt d
+load net {ACC1:acc#51.itm(8)} -attr vt d
+load net {ACC1:acc#51.itm(9)} -attr vt d
+load net {ACC1:acc#51.itm(10)} -attr vt d
+load net {ACC1:acc#51.itm(11)} -attr vt d
+load netBundle {ACC1:acc#51.itm} 12 {ACC1:acc#51.itm(0)} {ACC1:acc#51.itm(1)} {ACC1:acc#51.itm(2)} {ACC1:acc#51.itm(3)} {ACC1:acc#51.itm(4)} {ACC1:acc#51.itm(5)} {ACC1:acc#51.itm(6)} {ACC1:acc#51.itm(7)} {ACC1:acc#51.itm(8)} {ACC1:acc#51.itm(9)} {ACC1:acc#51.itm(10)} {ACC1:acc#51.itm(11)} -attr xrf 5118 -attr oid 252 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {conc#157.itm(0)} -attr vt d
+load net {conc#157.itm(1)} -attr vt d
+load net {conc#157.itm(2)} -attr vt d
+load net {conc#157.itm(3)} -attr vt d
+load net {conc#157.itm(4)} -attr vt d
+load net {conc#157.itm(5)} -attr vt d
+load net {conc#157.itm(6)} -attr vt d
+load net {conc#157.itm(7)} -attr vt d
+load net {conc#157.itm(8)} -attr vt d
+load net {conc#157.itm(9)} -attr vt d
+load net {conc#157.itm(10)} -attr vt d
+load netBundle {conc#157.itm} 11 {conc#157.itm(0)} {conc#157.itm(1)} {conc#157.itm(2)} {conc#157.itm(3)} {conc#157.itm(4)} {conc#157.itm(5)} {conc#157.itm(6)} {conc#157.itm(7)} {conc#157.itm(8)} {conc#157.itm(9)} {conc#157.itm(10)} -attr xrf 5119 -attr oid 253 -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(0)} -attr vt d
+load net {ACC1:not#13.itm(1)} -attr vt d
+load net {ACC1:not#13.itm(2)} -attr vt d
+load net {ACC1:not#13.itm(3)} -attr vt d
+load net {ACC1:not#13.itm(4)} -attr vt d
+load net {ACC1:not#13.itm(5)} -attr vt d
+load net {ACC1:not#13.itm(6)} -attr vt d
+load net {ACC1:not#13.itm(7)} -attr vt d
+load net {ACC1:not#13.itm(8)} -attr vt d
+load net {ACC1:not#13.itm(9)} -attr vt d
+load netBundle {ACC1:not#13.itm} 10 {ACC1:not#13.itm(0)} {ACC1:not#13.itm(1)} {ACC1:not#13.itm(2)} {ACC1:not#13.itm(3)} {ACC1:not#13.itm(4)} {ACC1:not#13.itm(5)} {ACC1:not#13.itm(6)} {ACC1:not#13.itm(7)} {ACC1:not#13.itm(8)} {ACC1:not#13.itm(9)} -attr xrf 5120 -attr oid 254 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {slc(regs.regs(0).sva#2).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#2).itm} 10 {slc(regs.regs(0).sva#2).itm(0)} {slc(regs.regs(0).sva#2).itm(1)} {slc(regs.regs(0).sva#2).itm(2)} {slc(regs.regs(0).sva#2).itm(3)} {slc(regs.regs(0).sva#2).itm(4)} {slc(regs.regs(0).sva#2).itm(5)} {slc(regs.regs(0).sva#2).itm(6)} {slc(regs.regs(0).sva#2).itm(7)} {slc(regs.regs(0).sva#2).itm(8)} {slc(regs.regs(0).sva#2).itm(9)} -attr xrf 5121 -attr oid 255 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {conc#158.itm(0)} -attr vt d
+load net {conc#158.itm(1)} -attr vt d
+load net {conc#158.itm(2)} -attr vt d
+load net {conc#158.itm(3)} -attr vt d
+load net {conc#158.itm(4)} -attr vt d
+load net {conc#158.itm(5)} -attr vt d
+load net {conc#158.itm(6)} -attr vt d
+load net {conc#158.itm(7)} -attr vt d
+load net {conc#158.itm(8)} -attr vt d
+load net {conc#158.itm(9)} -attr vt d
+load net {conc#158.itm(10)} -attr vt d
+load netBundle {conc#158.itm} 11 {conc#158.itm(0)} {conc#158.itm(1)} {conc#158.itm(2)} {conc#158.itm(3)} {conc#158.itm(4)} {conc#158.itm(5)} {conc#158.itm(6)} {conc#158.itm(7)} {conc#158.itm(8)} {conc#158.itm(9)} {conc#158.itm(10)} -attr xrf 5122 -attr oid 256 -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {slc(regs.regs(1).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#1.itm} 10 {slc(regs.regs(1).sva)#1.itm(0)} {slc(regs.regs(1).sva)#1.itm(1)} {slc(regs.regs(1).sva)#1.itm(2)} {slc(regs.regs(1).sva)#1.itm(3)} {slc(regs.regs(1).sva)#1.itm(4)} {slc(regs.regs(1).sva)#1.itm(5)} {slc(regs.regs(1).sva)#1.itm(6)} {slc(regs.regs(1).sva)#1.itm(7)} {slc(regs.regs(1).sva)#1.itm(8)} {slc(regs.regs(1).sva)#1.itm(9)} -attr xrf 5123 -attr oid 257 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {FRAME:for:mul#7.itm(0)} -attr vt d
+load net {FRAME:for:mul#7.itm(1)} -attr vt d
+load net {FRAME:for:mul#7.itm(2)} -attr vt d
+load net {FRAME:for:mul#7.itm(3)} -attr vt d
+load net {FRAME:for:mul#7.itm(4)} -attr vt d
+load net {FRAME:for:mul#7.itm(5)} -attr vt d
+load net {FRAME:for:mul#7.itm(6)} -attr vt d
+load net {FRAME:for:mul#7.itm(7)} -attr vt d
+load net {FRAME:for:mul#7.itm(8)} -attr vt d
+load net {FRAME:for:mul#7.itm(9)} -attr vt d
+load net {FRAME:for:mul#7.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#7.itm} 11 {FRAME:for:mul#7.itm(0)} {FRAME:for:mul#7.itm(1)} {FRAME:for:mul#7.itm(2)} {FRAME:for:mul#7.itm(3)} {FRAME:for:mul#7.itm(4)} {FRAME:for:mul#7.itm(5)} {FRAME:for:mul#7.itm(6)} {FRAME:for:mul#7.itm(7)} {FRAME:for:mul#7.itm(8)} {FRAME:for:mul#7.itm(9)} {FRAME:for:mul#7.itm(10)} -attr xrf 5124 -attr oid 258 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {regs.operator[]#16:mux.itm(0)} -attr vt d
+load net {regs.operator[]#16:mux.itm(1)} -attr vt d
+load net {regs.operator[]#16:mux.itm(2)} -attr vt d
+load net {regs.operator[]#16:mux.itm(3)} -attr vt d
+load net {regs.operator[]#16:mux.itm(4)} -attr vt d
+load net {regs.operator[]#16:mux.itm(5)} -attr vt d
+load net {regs.operator[]#16:mux.itm(6)} -attr vt d
+load net {regs.operator[]#16:mux.itm(7)} -attr vt d
+load net {regs.operator[]#16:mux.itm(8)} -attr vt d
+load net {regs.operator[]#16:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#16:mux.itm} 10 {regs.operator[]#16:mux.itm(0)} {regs.operator[]#16:mux.itm(1)} {regs.operator[]#16:mux.itm(2)} {regs.operator[]#16:mux.itm(3)} {regs.operator[]#16:mux.itm(4)} {regs.operator[]#16:mux.itm(5)} {regs.operator[]#16:mux.itm(6)} {regs.operator[]#16:mux.itm(7)} {regs.operator[]#16:mux.itm(8)} {regs.operator[]#16:mux.itm(9)} -attr xrf 5125 -attr oid 259 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(9)} -attr xrf 5126 -attr oid 260 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr xrf 5127 -attr oid 261 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr xrf 5128 -attr oid 262 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {FRAME:for:mux#7.itm(0)} -attr vt d
+load net {FRAME:for:mux#7.itm(1)} -attr vt d
+load net {FRAME:for:mux#7.itm(2)} -attr vt d
+load net {FRAME:for:mux#7.itm(3)} -attr vt d
+load net {FRAME:for:mux#7.itm(4)} -attr vt d
+load net {FRAME:for:mux#7.itm(5)} -attr vt d
+load net {FRAME:for:mux#7.itm(6)} -attr vt d
+load net {FRAME:for:mux#7.itm(7)} -attr vt d
+load net {FRAME:for:mux#7.itm(8)} -attr vt d
+load net {FRAME:for:mux#7.itm(9)} -attr vt d
+load net {FRAME:for:mux#7.itm(10)} -attr vt d
+load net {FRAME:for:mux#7.itm(11)} -attr vt d
+load net {FRAME:for:mux#7.itm(12)} -attr vt d
+load net {FRAME:for:mux#7.itm(13)} -attr vt d
+load net {FRAME:for:mux#7.itm(14)} -attr vt d
+load net {FRAME:for:mux#7.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#7.itm} 16 {FRAME:for:mux#7.itm(0)} {FRAME:for:mux#7.itm(1)} {FRAME:for:mux#7.itm(2)} {FRAME:for:mux#7.itm(3)} {FRAME:for:mux#7.itm(4)} {FRAME:for:mux#7.itm(5)} {FRAME:for:mux#7.itm(6)} {FRAME:for:mux#7.itm(7)} {FRAME:for:mux#7.itm(8)} {FRAME:for:mux#7.itm(9)} {FRAME:for:mux#7.itm(10)} {FRAME:for:mux#7.itm(11)} {FRAME:for:mux#7.itm(12)} {FRAME:for:mux#7.itm(13)} {FRAME:for:mux#7.itm(14)} {FRAME:for:mux#7.itm(15)} -attr xrf 5129 -attr oid 263 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:exs#21.itm(0)} -attr vt d
+load net {FRAME:for:exs#21.itm(1)} -attr vt d
+load net {FRAME:for:exs#21.itm(2)} -attr vt d
+load net {FRAME:for:exs#21.itm(3)} -attr vt d
+load net {FRAME:for:exs#21.itm(4)} -attr vt d
+load net {FRAME:for:exs#21.itm(5)} -attr vt d
+load net {FRAME:for:exs#21.itm(6)} -attr vt d
+load net {FRAME:for:exs#21.itm(7)} -attr vt d
+load net {FRAME:for:exs#21.itm(8)} -attr vt d
+load net {FRAME:for:exs#21.itm(9)} -attr vt d
+load net {FRAME:for:exs#21.itm(10)} -attr vt d
+load net {FRAME:for:exs#21.itm(11)} -attr vt d
+load net {FRAME:for:exs#21.itm(12)} -attr vt d
+load net {FRAME:for:exs#21.itm(13)} -attr vt d
+load net {FRAME:for:exs#21.itm(14)} -attr vt d
+load net {FRAME:for:exs#21.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#21.itm} 16 {FRAME:for:exs#21.itm(0)} {FRAME:for:exs#21.itm(1)} {FRAME:for:exs#21.itm(2)} {FRAME:for:exs#21.itm(3)} {FRAME:for:exs#21.itm(4)} {FRAME:for:exs#21.itm(5)} {FRAME:for:exs#21.itm(6)} {FRAME:for:exs#21.itm(7)} {FRAME:for:exs#21.itm(8)} {FRAME:for:exs#21.itm(9)} {FRAME:for:exs#21.itm(10)} {FRAME:for:exs#21.itm(11)} {FRAME:for:exs#21.itm(12)} {FRAME:for:exs#21.itm(13)} {FRAME:for:exs#21.itm(14)} {FRAME:for:exs#21.itm(15)} -attr xrf 5130 -attr oid 264 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:slc#1.itm(0)} -attr vt d
+load net {ACC1:slc#1.itm(1)} -attr vt d
+load net {ACC1:slc#1.itm(2)} -attr vt d
+load net {ACC1:slc#1.itm(3)} -attr vt d
+load net {ACC1:slc#1.itm(4)} -attr vt d
+load net {ACC1:slc#1.itm(5)} -attr vt d
+load net {ACC1:slc#1.itm(6)} -attr vt d
+load net {ACC1:slc#1.itm(7)} -attr vt d
+load net {ACC1:slc#1.itm(8)} -attr vt d
+load net {ACC1:slc#1.itm(9)} -attr vt d
+load net {ACC1:slc#1.itm(10)} -attr vt d
+load netBundle {ACC1:slc#1.itm} 11 {ACC1:slc#1.itm(0)} {ACC1:slc#1.itm(1)} {ACC1:slc#1.itm(2)} {ACC1:slc#1.itm(3)} {ACC1:slc#1.itm(4)} {ACC1:slc#1.itm(5)} {ACC1:slc#1.itm(6)} {ACC1:slc#1.itm(7)} {ACC1:slc#1.itm(8)} {ACC1:slc#1.itm(9)} {ACC1:slc#1.itm(10)} -attr xrf 5131 -attr oid 265 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc.itm(0)} -attr vt d
+load net {ACC1:acc.itm(1)} -attr vt d
+load net {ACC1:acc.itm(2)} -attr vt d
+load net {ACC1:acc.itm(3)} -attr vt d
+load net {ACC1:acc.itm(4)} -attr vt d
+load net {ACC1:acc.itm(5)} -attr vt d
+load net {ACC1:acc.itm(6)} -attr vt d
+load net {ACC1:acc.itm(7)} -attr vt d
+load net {ACC1:acc.itm(8)} -attr vt d
+load net {ACC1:acc.itm(9)} -attr vt d
+load net {ACC1:acc.itm(10)} -attr vt d
+load net {ACC1:acc.itm(11)} -attr vt d
+load netBundle {ACC1:acc.itm} 12 {ACC1:acc.itm(0)} {ACC1:acc.itm(1)} {ACC1:acc.itm(2)} {ACC1:acc.itm(3)} {ACC1:acc.itm(4)} {ACC1:acc.itm(5)} {ACC1:acc.itm(6)} {ACC1:acc.itm(7)} {ACC1:acc.itm(8)} {ACC1:acc.itm(9)} {ACC1:acc.itm(10)} {ACC1:acc.itm(11)} -attr xrf 5132 -attr oid 266 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {conc#159.itm(0)} -attr vt d
+load net {conc#159.itm(1)} -attr vt d
+load net {conc#159.itm(2)} -attr vt d
+load net {conc#159.itm(3)} -attr vt d
+load net {conc#159.itm(4)} -attr vt d
+load net {conc#159.itm(5)} -attr vt d
+load net {conc#159.itm(6)} -attr vt d
+load net {conc#159.itm(7)} -attr vt d
+load net {conc#159.itm(8)} -attr vt d
+load net {conc#159.itm(9)} -attr vt d
+load net {conc#159.itm(10)} -attr vt d
+load netBundle {conc#159.itm} 11 {conc#159.itm(0)} {conc#159.itm(1)} {conc#159.itm(2)} {conc#159.itm(3)} {conc#159.itm(4)} {conc#159.itm(5)} {conc#159.itm(6)} {conc#159.itm(7)} {conc#159.itm(8)} {conc#159.itm(9)} {conc#159.itm(10)} -attr xrf 5133 -attr oid 267 -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(0)} -attr vt d
+load net {ACC1:not#15.itm(1)} -attr vt d
+load net {ACC1:not#15.itm(2)} -attr vt d
+load net {ACC1:not#15.itm(3)} -attr vt d
+load net {ACC1:not#15.itm(4)} -attr vt d
+load net {ACC1:not#15.itm(5)} -attr vt d
+load net {ACC1:not#15.itm(6)} -attr vt d
+load net {ACC1:not#15.itm(7)} -attr vt d
+load net {ACC1:not#15.itm(8)} -attr vt d
+load net {ACC1:not#15.itm(9)} -attr vt d
+load netBundle {ACC1:not#15.itm} 10 {ACC1:not#15.itm(0)} {ACC1:not#15.itm(1)} {ACC1:not#15.itm(2)} {ACC1:not#15.itm(3)} {ACC1:not#15.itm(4)} {ACC1:not#15.itm(5)} {ACC1:not#15.itm(6)} {ACC1:not#15.itm(7)} {ACC1:not#15.itm(8)} {ACC1:not#15.itm(9)} -attr xrf 5134 -attr oid 268 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {slc(regs.regs(0).sva#5).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#5).itm} 10 {slc(regs.regs(0).sva#5).itm(0)} {slc(regs.regs(0).sva#5).itm(1)} {slc(regs.regs(0).sva#5).itm(2)} {slc(regs.regs(0).sva#5).itm(3)} {slc(regs.regs(0).sva#5).itm(4)} {slc(regs.regs(0).sva#5).itm(5)} {slc(regs.regs(0).sva#5).itm(6)} {slc(regs.regs(0).sva#5).itm(7)} {slc(regs.regs(0).sva#5).itm(8)} {slc(regs.regs(0).sva#5).itm(9)} -attr xrf 5135 -attr oid 269 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {conc#160.itm(0)} -attr vt d
+load net {conc#160.itm(1)} -attr vt d
+load net {conc#160.itm(2)} -attr vt d
+load net {conc#160.itm(3)} -attr vt d
+load net {conc#160.itm(4)} -attr vt d
+load net {conc#160.itm(5)} -attr vt d
+load net {conc#160.itm(6)} -attr vt d
+load net {conc#160.itm(7)} -attr vt d
+load net {conc#160.itm(8)} -attr vt d
+load net {conc#160.itm(9)} -attr vt d
+load net {conc#160.itm(10)} -attr vt d
+load netBundle {conc#160.itm} 11 {conc#160.itm(0)} {conc#160.itm(1)} {conc#160.itm(2)} {conc#160.itm(3)} {conc#160.itm(4)} {conc#160.itm(5)} {conc#160.itm(6)} {conc#160.itm(7)} {conc#160.itm(8)} {conc#160.itm(9)} {conc#160.itm(10)} -attr xrf 5136 -attr oid 270 -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {slc(regs.regs(1).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#4.itm} 10 {slc(regs.regs(1).sva)#4.itm(0)} {slc(regs.regs(1).sva)#4.itm(1)} {slc(regs.regs(1).sva)#4.itm(2)} {slc(regs.regs(1).sva)#4.itm(3)} {slc(regs.regs(1).sva)#4.itm(4)} {slc(regs.regs(1).sva)#4.itm(5)} {slc(regs.regs(1).sva)#4.itm(6)} {slc(regs.regs(1).sva)#4.itm(7)} {slc(regs.regs(1).sva)#4.itm(8)} {slc(regs.regs(1).sva)#4.itm(9)} -attr xrf 5137 -attr oid 271 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {FRAME:for:mul#1.itm(0)} -attr vt d
+load net {FRAME:for:mul#1.itm(1)} -attr vt d
+load net {FRAME:for:mul#1.itm(2)} -attr vt d
+load net {FRAME:for:mul#1.itm(3)} -attr vt d
+load net {FRAME:for:mul#1.itm(4)} -attr vt d
+load net {FRAME:for:mul#1.itm(5)} -attr vt d
+load net {FRAME:for:mul#1.itm(6)} -attr vt d
+load net {FRAME:for:mul#1.itm(7)} -attr vt d
+load net {FRAME:for:mul#1.itm(8)} -attr vt d
+load net {FRAME:for:mul#1.itm(9)} -attr vt d
+load net {FRAME:for:mul#1.itm(10)} -attr vt d
+load net {FRAME:for:mul#1.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul#1.itm} 12 {FRAME:for:mul#1.itm(0)} {FRAME:for:mul#1.itm(1)} {FRAME:for:mul#1.itm(2)} {FRAME:for:mul#1.itm(3)} {FRAME:for:mul#1.itm(4)} {FRAME:for:mul#1.itm(5)} {FRAME:for:mul#1.itm(6)} {FRAME:for:mul#1.itm(7)} {FRAME:for:mul#1.itm(8)} {FRAME:for:mul#1.itm(9)} {FRAME:for:mul#1.itm(10)} {FRAME:for:mul#1.itm(11)} -attr xrf 5138 -attr oid 272 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {regs.operator[]#10:mux.itm(0)} -attr vt d
+load net {regs.operator[]#10:mux.itm(1)} -attr vt d
+load net {regs.operator[]#10:mux.itm(2)} -attr vt d
+load net {regs.operator[]#10:mux.itm(3)} -attr vt d
+load net {regs.operator[]#10:mux.itm(4)} -attr vt d
+load net {regs.operator[]#10:mux.itm(5)} -attr vt d
+load net {regs.operator[]#10:mux.itm(6)} -attr vt d
+load net {regs.operator[]#10:mux.itm(7)} -attr vt d
+load net {regs.operator[]#10:mux.itm(8)} -attr vt d
+load net {regs.operator[]#10:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#10:mux.itm} 10 {regs.operator[]#10:mux.itm(0)} {regs.operator[]#10:mux.itm(1)} {regs.operator[]#10:mux.itm(2)} {regs.operator[]#10:mux.itm(3)} {regs.operator[]#10:mux.itm(4)} {regs.operator[]#10:mux.itm(5)} {regs.operator[]#10:mux.itm(6)} {regs.operator[]#10:mux.itm(7)} {regs.operator[]#10:mux.itm(8)} {regs.operator[]#10:mux.itm(9)} -attr xrf 5139 -attr oid 273 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(9)} -attr xrf 5140 -attr oid 274 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr xrf 5141 -attr oid 275 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#7.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#7.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(9)} -attr xrf 5142 -attr oid 276 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {conc#161.itm(0)} -attr vt d
+load net {conc#161.itm(1)} -attr vt d
+load netBundle {conc#161.itm} 2 {conc#161.itm(0)} {conc#161.itm(1)} -attr xrf 5143 -attr oid 277 -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {FRAME:for:mux#6.itm(0)} -attr vt d
+load net {FRAME:for:mux#6.itm(1)} -attr vt d
+load net {FRAME:for:mux#6.itm(2)} -attr vt d
+load net {FRAME:for:mux#6.itm(3)} -attr vt d
+load net {FRAME:for:mux#6.itm(4)} -attr vt d
+load net {FRAME:for:mux#6.itm(5)} -attr vt d
+load net {FRAME:for:mux#6.itm(6)} -attr vt d
+load net {FRAME:for:mux#6.itm(7)} -attr vt d
+load net {FRAME:for:mux#6.itm(8)} -attr vt d
+load net {FRAME:for:mux#6.itm(9)} -attr vt d
+load net {FRAME:for:mux#6.itm(10)} -attr vt d
+load net {FRAME:for:mux#6.itm(11)} -attr vt d
+load net {FRAME:for:mux#6.itm(12)} -attr vt d
+load net {FRAME:for:mux#6.itm(13)} -attr vt d
+load net {FRAME:for:mux#6.itm(14)} -attr vt d
+load net {FRAME:for:mux#6.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#6.itm} 16 {FRAME:for:mux#6.itm(0)} {FRAME:for:mux#6.itm(1)} {FRAME:for:mux#6.itm(2)} {FRAME:for:mux#6.itm(3)} {FRAME:for:mux#6.itm(4)} {FRAME:for:mux#6.itm(5)} {FRAME:for:mux#6.itm(6)} {FRAME:for:mux#6.itm(7)} {FRAME:for:mux#6.itm(8)} {FRAME:for:mux#6.itm(9)} {FRAME:for:mux#6.itm(10)} {FRAME:for:mux#6.itm(11)} {FRAME:for:mux#6.itm(12)} {FRAME:for:mux#6.itm(13)} {FRAME:for:mux#6.itm(14)} {FRAME:for:mux#6.itm(15)} -attr xrf 5144 -attr oid 278 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:exs#23.itm(0)} -attr vt d
+load net {FRAME:for:exs#23.itm(1)} -attr vt d
+load net {FRAME:for:exs#23.itm(2)} -attr vt d
+load net {FRAME:for:exs#23.itm(3)} -attr vt d
+load net {FRAME:for:exs#23.itm(4)} -attr vt d
+load net {FRAME:for:exs#23.itm(5)} -attr vt d
+load net {FRAME:for:exs#23.itm(6)} -attr vt d
+load net {FRAME:for:exs#23.itm(7)} -attr vt d
+load net {FRAME:for:exs#23.itm(8)} -attr vt d
+load net {FRAME:for:exs#23.itm(9)} -attr vt d
+load net {FRAME:for:exs#23.itm(10)} -attr vt d
+load net {FRAME:for:exs#23.itm(11)} -attr vt d
+load net {FRAME:for:exs#23.itm(12)} -attr vt d
+load net {FRAME:for:exs#23.itm(13)} -attr vt d
+load net {FRAME:for:exs#23.itm(14)} -attr vt d
+load net {FRAME:for:exs#23.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#23.itm} 16 {FRAME:for:exs#23.itm(0)} {FRAME:for:exs#23.itm(1)} {FRAME:for:exs#23.itm(2)} {FRAME:for:exs#23.itm(3)} {FRAME:for:exs#23.itm(4)} {FRAME:for:exs#23.itm(5)} {FRAME:for:exs#23.itm(6)} {FRAME:for:exs#23.itm(7)} {FRAME:for:exs#23.itm(8)} {FRAME:for:exs#23.itm(9)} {FRAME:for:exs#23.itm(10)} {FRAME:for:exs#23.itm(11)} {FRAME:for:exs#23.itm(12)} {FRAME:for:exs#23.itm(13)} {FRAME:for:exs#23.itm(14)} {FRAME:for:exs#23.itm(15)} -attr xrf 5145 -attr oid 279 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:slc#3.itm(0)} -attr vt d
+load net {ACC1:slc#3.itm(1)} -attr vt d
+load net {ACC1:slc#3.itm(2)} -attr vt d
+load net {ACC1:slc#3.itm(3)} -attr vt d
+load net {ACC1:slc#3.itm(4)} -attr vt d
+load net {ACC1:slc#3.itm(5)} -attr vt d
+load net {ACC1:slc#3.itm(6)} -attr vt d
+load net {ACC1:slc#3.itm(7)} -attr vt d
+load net {ACC1:slc#3.itm(8)} -attr vt d
+load net {ACC1:slc#3.itm(9)} -attr vt d
+load net {ACC1:slc#3.itm(10)} -attr vt d
+load netBundle {ACC1:slc#3.itm} 11 {ACC1:slc#3.itm(0)} {ACC1:slc#3.itm(1)} {ACC1:slc#3.itm(2)} {ACC1:slc#3.itm(3)} {ACC1:slc#3.itm(4)} {ACC1:slc#3.itm(5)} {ACC1:slc#3.itm(6)} {ACC1:slc#3.itm(7)} {ACC1:slc#3.itm(8)} {ACC1:slc#3.itm(9)} {ACC1:slc#3.itm(10)} -attr xrf 5146 -attr oid 280 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#50.itm(0)} -attr vt d
+load net {ACC1:acc#50.itm(1)} -attr vt d
+load net {ACC1:acc#50.itm(2)} -attr vt d
+load net {ACC1:acc#50.itm(3)} -attr vt d
+load net {ACC1:acc#50.itm(4)} -attr vt d
+load net {ACC1:acc#50.itm(5)} -attr vt d
+load net {ACC1:acc#50.itm(6)} -attr vt d
+load net {ACC1:acc#50.itm(7)} -attr vt d
+load net {ACC1:acc#50.itm(8)} -attr vt d
+load net {ACC1:acc#50.itm(9)} -attr vt d
+load net {ACC1:acc#50.itm(10)} -attr vt d
+load net {ACC1:acc#50.itm(11)} -attr vt d
+load netBundle {ACC1:acc#50.itm} 12 {ACC1:acc#50.itm(0)} {ACC1:acc#50.itm(1)} {ACC1:acc#50.itm(2)} {ACC1:acc#50.itm(3)} {ACC1:acc#50.itm(4)} {ACC1:acc#50.itm(5)} {ACC1:acc#50.itm(6)} {ACC1:acc#50.itm(7)} {ACC1:acc#50.itm(8)} {ACC1:acc#50.itm(9)} {ACC1:acc#50.itm(10)} {ACC1:acc#50.itm(11)} -attr xrf 5147 -attr oid 281 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {conc#162.itm(0)} -attr vt d
+load net {conc#162.itm(1)} -attr vt d
+load net {conc#162.itm(2)} -attr vt d
+load net {conc#162.itm(3)} -attr vt d
+load net {conc#162.itm(4)} -attr vt d
+load net {conc#162.itm(5)} -attr vt d
+load net {conc#162.itm(6)} -attr vt d
+load net {conc#162.itm(7)} -attr vt d
+load net {conc#162.itm(8)} -attr vt d
+load net {conc#162.itm(9)} -attr vt d
+load net {conc#162.itm(10)} -attr vt d
+load netBundle {conc#162.itm} 11 {conc#162.itm(0)} {conc#162.itm(1)} {conc#162.itm(2)} {conc#162.itm(3)} {conc#162.itm(4)} {conc#162.itm(5)} {conc#162.itm(6)} {conc#162.itm(7)} {conc#162.itm(8)} {conc#162.itm(9)} {conc#162.itm(10)} -attr xrf 5148 -attr oid 282 -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(0)} -attr vt d
+load net {ACC1:not#12.itm(1)} -attr vt d
+load net {ACC1:not#12.itm(2)} -attr vt d
+load net {ACC1:not#12.itm(3)} -attr vt d
+load net {ACC1:not#12.itm(4)} -attr vt d
+load net {ACC1:not#12.itm(5)} -attr vt d
+load net {ACC1:not#12.itm(6)} -attr vt d
+load net {ACC1:not#12.itm(7)} -attr vt d
+load net {ACC1:not#12.itm(8)} -attr vt d
+load net {ACC1:not#12.itm(9)} -attr vt d
+load netBundle {ACC1:not#12.itm} 10 {ACC1:not#12.itm(0)} {ACC1:not#12.itm(1)} {ACC1:not#12.itm(2)} {ACC1:not#12.itm(3)} {ACC1:not#12.itm(4)} {ACC1:not#12.itm(5)} {ACC1:not#12.itm(6)} {ACC1:not#12.itm(7)} {ACC1:not#12.itm(8)} {ACC1:not#12.itm(9)} -attr xrf 5149 -attr oid 283 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {slc(regs.regs(0).sva#3).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#3).itm} 10 {slc(regs.regs(0).sva#3).itm(0)} {slc(regs.regs(0).sva#3).itm(1)} {slc(regs.regs(0).sva#3).itm(2)} {slc(regs.regs(0).sva#3).itm(3)} {slc(regs.regs(0).sva#3).itm(4)} {slc(regs.regs(0).sva#3).itm(5)} {slc(regs.regs(0).sva#3).itm(6)} {slc(regs.regs(0).sva#3).itm(7)} {slc(regs.regs(0).sva#3).itm(8)} {slc(regs.regs(0).sva#3).itm(9)} -attr xrf 5150 -attr oid 284 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {conc#163.itm(0)} -attr vt d
+load net {conc#163.itm(1)} -attr vt d
+load net {conc#163.itm(2)} -attr vt d
+load net {conc#163.itm(3)} -attr vt d
+load net {conc#163.itm(4)} -attr vt d
+load net {conc#163.itm(5)} -attr vt d
+load net {conc#163.itm(6)} -attr vt d
+load net {conc#163.itm(7)} -attr vt d
+load net {conc#163.itm(8)} -attr vt d
+load net {conc#163.itm(9)} -attr vt d
+load net {conc#163.itm(10)} -attr vt d
+load netBundle {conc#163.itm} 11 {conc#163.itm(0)} {conc#163.itm(1)} {conc#163.itm(2)} {conc#163.itm(3)} {conc#163.itm(4)} {conc#163.itm(5)} {conc#163.itm(6)} {conc#163.itm(7)} {conc#163.itm(8)} {conc#163.itm(9)} {conc#163.itm(10)} -attr xrf 5151 -attr oid 285 -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {slc(regs.regs(1).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#2.itm} 10 {slc(regs.regs(1).sva)#2.itm(0)} {slc(regs.regs(1).sva)#2.itm(1)} {slc(regs.regs(1).sva)#2.itm(2)} {slc(regs.regs(1).sva)#2.itm(3)} {slc(regs.regs(1).sva)#2.itm(4)} {slc(regs.regs(1).sva)#2.itm(5)} {slc(regs.regs(1).sva)#2.itm(6)} {slc(regs.regs(1).sva)#2.itm(7)} {slc(regs.regs(1).sva)#2.itm(8)} {slc(regs.regs(1).sva)#2.itm(9)} -attr xrf 5152 -attr oid 286 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {FRAME:for:mul#6.itm(0)} -attr vt d
+load net {FRAME:for:mul#6.itm(1)} -attr vt d
+load net {FRAME:for:mul#6.itm(2)} -attr vt d
+load net {FRAME:for:mul#6.itm(3)} -attr vt d
+load net {FRAME:for:mul#6.itm(4)} -attr vt d
+load net {FRAME:for:mul#6.itm(5)} -attr vt d
+load net {FRAME:for:mul#6.itm(6)} -attr vt d
+load net {FRAME:for:mul#6.itm(7)} -attr vt d
+load net {FRAME:for:mul#6.itm(8)} -attr vt d
+load net {FRAME:for:mul#6.itm(9)} -attr vt d
+load net {FRAME:for:mul#6.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#6.itm} 11 {FRAME:for:mul#6.itm(0)} {FRAME:for:mul#6.itm(1)} {FRAME:for:mul#6.itm(2)} {FRAME:for:mul#6.itm(3)} {FRAME:for:mul#6.itm(4)} {FRAME:for:mul#6.itm(5)} {FRAME:for:mul#6.itm(6)} {FRAME:for:mul#6.itm(7)} {FRAME:for:mul#6.itm(8)} {FRAME:for:mul#6.itm(9)} {FRAME:for:mul#6.itm(10)} -attr xrf 5153 -attr oid 287 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {regs.operator[]#15:mux.itm(0)} -attr vt d
+load net {regs.operator[]#15:mux.itm(1)} -attr vt d
+load net {regs.operator[]#15:mux.itm(2)} -attr vt d
+load net {regs.operator[]#15:mux.itm(3)} -attr vt d
+load net {regs.operator[]#15:mux.itm(4)} -attr vt d
+load net {regs.operator[]#15:mux.itm(5)} -attr vt d
+load net {regs.operator[]#15:mux.itm(6)} -attr vt d
+load net {regs.operator[]#15:mux.itm(7)} -attr vt d
+load net {regs.operator[]#15:mux.itm(8)} -attr vt d
+load net {regs.operator[]#15:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#15:mux.itm} 10 {regs.operator[]#15:mux.itm(0)} {regs.operator[]#15:mux.itm(1)} {regs.operator[]#15:mux.itm(2)} {regs.operator[]#15:mux.itm(3)} {regs.operator[]#15:mux.itm(4)} {regs.operator[]#15:mux.itm(5)} {regs.operator[]#15:mux.itm(6)} {regs.operator[]#15:mux.itm(7)} {regs.operator[]#15:mux.itm(8)} {regs.operator[]#15:mux.itm(9)} -attr xrf 5154 -attr oid 288 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(9)} -attr xrf 5155 -attr oid 289 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr xrf 5156 -attr oid 290 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr xrf 5157 -attr oid 291 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {FRAME:for:mux#5.itm(0)} -attr vt d
+load net {FRAME:for:mux#5.itm(1)} -attr vt d
+load net {FRAME:for:mux#5.itm(2)} -attr vt d
+load net {FRAME:for:mux#5.itm(3)} -attr vt d
+load net {FRAME:for:mux#5.itm(4)} -attr vt d
+load net {FRAME:for:mux#5.itm(5)} -attr vt d
+load net {FRAME:for:mux#5.itm(6)} -attr vt d
+load net {FRAME:for:mux#5.itm(7)} -attr vt d
+load net {FRAME:for:mux#5.itm(8)} -attr vt d
+load net {FRAME:for:mux#5.itm(9)} -attr vt d
+load net {FRAME:for:mux#5.itm(10)} -attr vt d
+load net {FRAME:for:mux#5.itm(11)} -attr vt d
+load net {FRAME:for:mux#5.itm(12)} -attr vt d
+load net {FRAME:for:mux#5.itm(13)} -attr vt d
+load net {FRAME:for:mux#5.itm(14)} -attr vt d
+load net {FRAME:for:mux#5.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#5.itm} 16 {FRAME:for:mux#5.itm(0)} {FRAME:for:mux#5.itm(1)} {FRAME:for:mux#5.itm(2)} {FRAME:for:mux#5.itm(3)} {FRAME:for:mux#5.itm(4)} {FRAME:for:mux#5.itm(5)} {FRAME:for:mux#5.itm(6)} {FRAME:for:mux#5.itm(7)} {FRAME:for:mux#5.itm(8)} {FRAME:for:mux#5.itm(9)} {FRAME:for:mux#5.itm(10)} {FRAME:for:mux#5.itm(11)} {FRAME:for:mux#5.itm(12)} {FRAME:for:mux#5.itm(13)} {FRAME:for:mux#5.itm(14)} {FRAME:for:mux#5.itm(15)} -attr xrf 5158 -attr oid 292 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:exs#20.itm(0)} -attr vt d
+load net {FRAME:for:exs#20.itm(1)} -attr vt d
+load net {FRAME:for:exs#20.itm(2)} -attr vt d
+load net {FRAME:for:exs#20.itm(3)} -attr vt d
+load net {FRAME:for:exs#20.itm(4)} -attr vt d
+load net {FRAME:for:exs#20.itm(5)} -attr vt d
+load net {FRAME:for:exs#20.itm(6)} -attr vt d
+load net {FRAME:for:exs#20.itm(7)} -attr vt d
+load net {FRAME:for:exs#20.itm(8)} -attr vt d
+load net {FRAME:for:exs#20.itm(9)} -attr vt d
+load net {FRAME:for:exs#20.itm(10)} -attr vt d
+load net {FRAME:for:exs#20.itm(11)} -attr vt d
+load net {FRAME:for:exs#20.itm(12)} -attr vt d
+load net {FRAME:for:exs#20.itm(13)} -attr vt d
+load net {FRAME:for:exs#20.itm(14)} -attr vt d
+load net {FRAME:for:exs#20.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#20.itm} 16 {FRAME:for:exs#20.itm(0)} {FRAME:for:exs#20.itm(1)} {FRAME:for:exs#20.itm(2)} {FRAME:for:exs#20.itm(3)} {FRAME:for:exs#20.itm(4)} {FRAME:for:exs#20.itm(5)} {FRAME:for:exs#20.itm(6)} {FRAME:for:exs#20.itm(7)} {FRAME:for:exs#20.itm(8)} {FRAME:for:exs#20.itm(9)} {FRAME:for:exs#20.itm(10)} {FRAME:for:exs#20.itm(11)} {FRAME:for:exs#20.itm(12)} {FRAME:for:exs#20.itm(13)} {FRAME:for:exs#20.itm(14)} {FRAME:for:exs#20.itm(15)} -attr xrf 5159 -attr oid 293 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:slc.itm(0)} -attr vt d
+load net {ACC1:slc.itm(1)} -attr vt d
+load net {ACC1:slc.itm(2)} -attr vt d
+load net {ACC1:slc.itm(3)} -attr vt d
+load net {ACC1:slc.itm(4)} -attr vt d
+load net {ACC1:slc.itm(5)} -attr vt d
+load net {ACC1:slc.itm(6)} -attr vt d
+load net {ACC1:slc.itm(7)} -attr vt d
+load net {ACC1:slc.itm(8)} -attr vt d
+load net {ACC1:slc.itm(9)} -attr vt d
+load net {ACC1:slc.itm(10)} -attr vt d
+load netBundle {ACC1:slc.itm} 11 {ACC1:slc.itm(0)} {ACC1:slc.itm(1)} {ACC1:slc.itm(2)} {ACC1:slc.itm(3)} {ACC1:slc.itm(4)} {ACC1:slc.itm(5)} {ACC1:slc.itm(6)} {ACC1:slc.itm(7)} {ACC1:slc.itm(8)} {ACC1:slc.itm(9)} {ACC1:slc.itm(10)} -attr xrf 5160 -attr oid 294 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#48.itm(0)} -attr vt d
+load net {ACC1:acc#48.itm(1)} -attr vt d
+load net {ACC1:acc#48.itm(2)} -attr vt d
+load net {ACC1:acc#48.itm(3)} -attr vt d
+load net {ACC1:acc#48.itm(4)} -attr vt d
+load net {ACC1:acc#48.itm(5)} -attr vt d
+load net {ACC1:acc#48.itm(6)} -attr vt d
+load net {ACC1:acc#48.itm(7)} -attr vt d
+load net {ACC1:acc#48.itm(8)} -attr vt d
+load net {ACC1:acc#48.itm(9)} -attr vt d
+load net {ACC1:acc#48.itm(10)} -attr vt d
+load net {ACC1:acc#48.itm(11)} -attr vt d
+load netBundle {ACC1:acc#48.itm} 12 {ACC1:acc#48.itm(0)} {ACC1:acc#48.itm(1)} {ACC1:acc#48.itm(2)} {ACC1:acc#48.itm(3)} {ACC1:acc#48.itm(4)} {ACC1:acc#48.itm(5)} {ACC1:acc#48.itm(6)} {ACC1:acc#48.itm(7)} {ACC1:acc#48.itm(8)} {ACC1:acc#48.itm(9)} {ACC1:acc#48.itm(10)} {ACC1:acc#48.itm(11)} -attr xrf 5161 -attr oid 295 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {conc#164.itm(0)} -attr vt d
+load net {conc#164.itm(1)} -attr vt d
+load net {conc#164.itm(2)} -attr vt d
+load net {conc#164.itm(3)} -attr vt d
+load net {conc#164.itm(4)} -attr vt d
+load net {conc#164.itm(5)} -attr vt d
+load net {conc#164.itm(6)} -attr vt d
+load net {conc#164.itm(7)} -attr vt d
+load net {conc#164.itm(8)} -attr vt d
+load net {conc#164.itm(9)} -attr vt d
+load net {conc#164.itm(10)} -attr vt d
+load netBundle {conc#164.itm} 11 {conc#164.itm(0)} {conc#164.itm(1)} {conc#164.itm(2)} {conc#164.itm(3)} {conc#164.itm(4)} {conc#164.itm(5)} {conc#164.itm(6)} {conc#164.itm(7)} {conc#164.itm(8)} {conc#164.itm(9)} {conc#164.itm(10)} -attr xrf 5162 -attr oid 296 -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(0)} -attr vt d
+load net {ACC1:not.itm(1)} -attr vt d
+load net {ACC1:not.itm(2)} -attr vt d
+load net {ACC1:not.itm(3)} -attr vt d
+load net {ACC1:not.itm(4)} -attr vt d
+load net {ACC1:not.itm(5)} -attr vt d
+load net {ACC1:not.itm(6)} -attr vt d
+load net {ACC1:not.itm(7)} -attr vt d
+load net {ACC1:not.itm(8)} -attr vt d
+load net {ACC1:not.itm(9)} -attr vt d
+load netBundle {ACC1:not.itm} 10 {ACC1:not.itm(0)} {ACC1:not.itm(1)} {ACC1:not.itm(2)} {ACC1:not.itm(3)} {ACC1:not.itm(4)} {ACC1:not.itm(5)} {ACC1:not.itm(6)} {ACC1:not.itm(7)} {ACC1:not.itm(8)} {ACC1:not.itm(9)} -attr xrf 5163 -attr oid 297 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {slc(regs.regs(0).sva#6).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#6).itm} 10 {slc(regs.regs(0).sva#6).itm(0)} {slc(regs.regs(0).sva#6).itm(1)} {slc(regs.regs(0).sva#6).itm(2)} {slc(regs.regs(0).sva#6).itm(3)} {slc(regs.regs(0).sva#6).itm(4)} {slc(regs.regs(0).sva#6).itm(5)} {slc(regs.regs(0).sva#6).itm(6)} {slc(regs.regs(0).sva#6).itm(7)} {slc(regs.regs(0).sva#6).itm(8)} {slc(regs.regs(0).sva#6).itm(9)} -attr xrf 5164 -attr oid 298 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {conc#165.itm(0)} -attr vt d
+load net {conc#165.itm(1)} -attr vt d
+load net {conc#165.itm(2)} -attr vt d
+load net {conc#165.itm(3)} -attr vt d
+load net {conc#165.itm(4)} -attr vt d
+load net {conc#165.itm(5)} -attr vt d
+load net {conc#165.itm(6)} -attr vt d
+load net {conc#165.itm(7)} -attr vt d
+load net {conc#165.itm(8)} -attr vt d
+load net {conc#165.itm(9)} -attr vt d
+load net {conc#165.itm(10)} -attr vt d
+load netBundle {conc#165.itm} 11 {conc#165.itm(0)} {conc#165.itm(1)} {conc#165.itm(2)} {conc#165.itm(3)} {conc#165.itm(4)} {conc#165.itm(5)} {conc#165.itm(6)} {conc#165.itm(7)} {conc#165.itm(8)} {conc#165.itm(9)} {conc#165.itm(10)} -attr xrf 5165 -attr oid 299 -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {slc(regs.regs(1).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#5.itm} 10 {slc(regs.regs(1).sva)#5.itm(0)} {slc(regs.regs(1).sva)#5.itm(1)} {slc(regs.regs(1).sva)#5.itm(2)} {slc(regs.regs(1).sva)#5.itm(3)} {slc(regs.regs(1).sva)#5.itm(4)} {slc(regs.regs(1).sva)#5.itm(5)} {slc(regs.regs(1).sva)#5.itm(6)} {slc(regs.regs(1).sva)#5.itm(7)} {slc(regs.regs(1).sva)#5.itm(8)} {slc(regs.regs(1).sva)#5.itm(9)} -attr xrf 5166 -attr oid 300 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {FRAME:for:mul.itm(0)} -attr vt d
+load net {FRAME:for:mul.itm(1)} -attr vt d
+load net {FRAME:for:mul.itm(2)} -attr vt d
+load net {FRAME:for:mul.itm(3)} -attr vt d
+load net {FRAME:for:mul.itm(4)} -attr vt d
+load net {FRAME:for:mul.itm(5)} -attr vt d
+load net {FRAME:for:mul.itm(6)} -attr vt d
+load net {FRAME:for:mul.itm(7)} -attr vt d
+load net {FRAME:for:mul.itm(8)} -attr vt d
+load net {FRAME:for:mul.itm(9)} -attr vt d
+load net {FRAME:for:mul.itm(10)} -attr vt d
+load net {FRAME:for:mul.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul.itm} 12 {FRAME:for:mul.itm(0)} {FRAME:for:mul.itm(1)} {FRAME:for:mul.itm(2)} {FRAME:for:mul.itm(3)} {FRAME:for:mul.itm(4)} {FRAME:for:mul.itm(5)} {FRAME:for:mul.itm(6)} {FRAME:for:mul.itm(7)} {FRAME:for:mul.itm(8)} {FRAME:for:mul.itm(9)} {FRAME:for:mul.itm(10)} {FRAME:for:mul.itm(11)} -attr xrf 5167 -attr oid 301 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {regs.operator[]#9:mux.itm(0)} -attr vt d
+load net {regs.operator[]#9:mux.itm(1)} -attr vt d
+load net {regs.operator[]#9:mux.itm(2)} -attr vt d
+load net {regs.operator[]#9:mux.itm(3)} -attr vt d
+load net {regs.operator[]#9:mux.itm(4)} -attr vt d
+load net {regs.operator[]#9:mux.itm(5)} -attr vt d
+load net {regs.operator[]#9:mux.itm(6)} -attr vt d
+load net {regs.operator[]#9:mux.itm(7)} -attr vt d
+load net {regs.operator[]#9:mux.itm(8)} -attr vt d
+load net {regs.operator[]#9:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#9:mux.itm} 10 {regs.operator[]#9:mux.itm(0)} {regs.operator[]#9:mux.itm(1)} {regs.operator[]#9:mux.itm(2)} {regs.operator[]#9:mux.itm(3)} {regs.operator[]#9:mux.itm(4)} {regs.operator[]#9:mux.itm(5)} {regs.operator[]#9:mux.itm(6)} {regs.operator[]#9:mux.itm(7)} {regs.operator[]#9:mux.itm(8)} {regs.operator[]#9:mux.itm(9)} -attr xrf 5168 -attr oid 302 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(9)} -attr xrf 5169 -attr oid 303 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr xrf 5170 -attr oid 304 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#8.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#8.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(9)} -attr xrf 5171 -attr oid 305 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {conc#166.itm(0)} -attr vt d
+load net {conc#166.itm(1)} -attr vt d
+load netBundle {conc#166.itm} 2 {conc#166.itm(0)} {conc#166.itm(1)} -attr xrf 5172 -attr oid 306 -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {clk} -attr xrf 5173 -attr oid 307
+load net {clk} -port {clk} -attr xrf 5174 -attr oid 308
+load net {en} -attr xrf 5175 -attr oid 309
+load net {en} -port {en} -attr xrf 5176 -attr oid 310
+load net {arst_n} -attr xrf 5177 -attr oid 311
+load net {arst_n} -port {arst_n} -attr xrf 5178 -attr oid 312
+load net {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 5179 -attr oid 313 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(0)} -port {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -port {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -port {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -port {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -port {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -port {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -port {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -port {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -port {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -port {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -port {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -port {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -port {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -port {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -port {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -port {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -port {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -port {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -port {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -port {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -port {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -port {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -port {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -port {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -port {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -port {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -port {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -port {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -port {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -port {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -port {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -port {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -port {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -port {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -port {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -port {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -port {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -port {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -port {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -port {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -port {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -port {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -port {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -port {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -port {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -port {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -port {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -port {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -port {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -port {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -port {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -port {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -port {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -port {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -port {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -port {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -port {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -port {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -port {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -port {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -port {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -port {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -port {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -port {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -port {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -port {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -port {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -port {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -port {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -port {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -port {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -port {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -port {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -port {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -port {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -port {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -port {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -port {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -port {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -port {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -port {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -port {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -port {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -port {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -port {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -port {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -port {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -port {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -port {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -port {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 5180 -attr oid 314 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d} 30 {vout:rsc:mgc_out_stdreg.d(0)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(29)} -attr xrf 5181 -attr oid 315 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -port {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -port {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -port {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -port {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -port {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -port {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -port {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -port {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -port {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -port {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -port {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -port {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -port {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -port {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -port {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -port {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -port {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -port {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -port {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -port {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -port {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -port {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -port {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -port {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -port {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -port {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -port {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -port {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -port {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -port {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:acc#38" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 5182 -attr oid 316 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {FRAME:acc#37.itm#1(0)} -pin  "FRAME:acc#38" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(1)} -pin  "FRAME:acc#38" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(2)} -pin  "FRAME:acc#38" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(3)} -pin  "FRAME:acc#38" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(4)} -pin  "FRAME:acc#38" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:slc(acc.imod)#4.itm#1} -pin  "FRAME:acc#38" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#123.itm}
+load net {PWR} -pin  "FRAME:acc#38" {B(1)} -attr @path {/sobel/sobel:core/conc#123.itm}
+load net {GND} -pin  "FRAME:acc#38" {B(2)} -attr @path {/sobel/sobel:core/conc#123.itm}
+load net {GND} -pin  "FRAME:acc#38" {B(3)} -attr @path {/sobel/sobel:core/conc#123.itm}
+load net {PWR} -pin  "FRAME:acc#38" {B(4)} -attr @path {/sobel/sobel:core/conc#123.itm}
+load net {FRAME:acc#38.itm(0)} -pin  "FRAME:acc#38" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(1)} -pin  "FRAME:acc#38" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(2)} -pin  "FRAME:acc#38" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(3)} -pin  "FRAME:acc#38" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(4)} -pin  "FRAME:acc#38" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load inst "FRAME:acc#39" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 5183 -attr oid 317 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {red:slc(red#2.sg1).itm#1(0)} -pin  "FRAME:acc#39" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
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+load inst "nand" "nand(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "nand" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {main.stage_0#2} -pin  "nand" {A1(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {nand.itm} -pin  "nand" {Z(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load inst "mux" "mux(2,30)" "INTERFACE" -attr xrf 5188 -attr oid 322 -attr vt d -attr @path {/sobel/sobel:core/mux} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "mux" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "mux" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "mux" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "mux" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "mux" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "mux" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "mux" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "mux" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "mux" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "mux" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "mux" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "mux" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "mux" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "mux" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "mux" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "mux" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "mux" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "mux" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "mux" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "mux" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "mux" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "mux" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "mux" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "mux" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "mux" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "mux" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "mux" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "mux" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "mux" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "mux" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {FRAME:acc#4.psp.sva(0)} -pin  "mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(1)} -pin  "mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(2)} -pin  "mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(3)} -pin  "mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(4)} -pin  "mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(5)} -pin  "mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(6)} -pin  "mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(7)} -pin  "mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(8)} -pin  "mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(9)} -pin  "mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(0)} -pin  "mux" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(1)} -pin  "mux" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(2)} -pin  "mux" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(3)} -pin  "mux" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(4)} -pin  "mux" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(5)} -pin  "mux" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(6)} -pin  "mux" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(7)} -pin  "mux" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(8)} -pin  "mux" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(9)} -pin  "mux" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(0)} -pin  "mux" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(1)} -pin  "mux" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(2)} -pin  "mux" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(3)} -pin  "mux" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(4)} -pin  "mux" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(5)} -pin  "mux" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(6)} -pin  "mux" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(7)} -pin  "mux" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(8)} -pin  "mux" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(9)} -pin  "mux" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {nand.itm} -pin  "mux" {S(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load net {mux.itm(0)} -pin  "mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "mux" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "mux" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "mux" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "mux" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "mux" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "mux" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "mux" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "mux" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "mux" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "mux" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "mux" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "mux" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "mux" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "mux" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "mux" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "mux" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "mux" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "mux" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "mux" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "mux" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 5189 -attr oid 323 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)}
+load net {mux.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 5190 -attr oid 324 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:acc#43" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 5191 -attr oid 325 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {FRAME:mul.sdt(8)} -pin  "FRAME:acc#43" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt).itm}
+load net {FRAME:mul.sdt(9)} -pin  "FRAME:acc#43" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt).itm}
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:acc#43" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#3.itm}
+load net {FRAME:acc#43.itm(0)} -pin  "FRAME:acc#43" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {FRAME:acc#43.itm(1)} -pin  "FRAME:acc#43" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load inst "reg(FRAME:acc#41.itm#1.sg2)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 5192 -attr oid 326 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#41.itm#1.sg2)}
+load net {FRAME:acc#43.itm(0)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {FRAME:acc#43.itm(1)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {clk} -attr xrf 5193 -attr oid 327 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#41.itm#1.sg2(0)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg2}
+load net {FRAME:acc#41.itm#1.sg2(1)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg2}
+load inst "reg(FRAME:acc#41.itm#1.sg1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 5194 -attr oid 328 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#41.itm#1.sg1)}
+load net {FRAME:mul.sdt(6)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#2.itm}
+load net {FRAME:mul.sdt(7)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#2.itm}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {clk} -attr xrf 5195 -attr oid 329 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#41.itm#1.sg1(0)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg1}
+load net {FRAME:acc#41.itm#1.sg1(1)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg1}
+load inst "FRAME:acc#44" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 5196 -attr oid 330 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44} -attr area 6.285690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {FRAME:mul.sdt(0)} -pin  "FRAME:acc#44" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(1)} -pin  "FRAME:acc#44" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(2)} -pin  "FRAME:acc#44" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(3)} -pin  "FRAME:acc#44" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(4)} -pin  "FRAME:acc#44" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:acc#44" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {GND} -pin  "FRAME:acc#44" {B(1)} -attr @path {/sobel/sobel:core/exs.itm}
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:acc#44" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:acc#44" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:acc#44" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:acc#44.itm(0)} -pin  "FRAME:acc#44" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(1)} -pin  "FRAME:acc#44" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(2)} -pin  "FRAME:acc#44" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(3)} -pin  "FRAME:acc#44" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(4)} -pin  "FRAME:acc#44" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(5)} -pin  "FRAME:acc#44" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load inst "reg(FRAME:acc#41.itm#3)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 5197 -attr oid 331 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#41.itm#3)}
+load net {FRAME:acc#44.itm(0)} -pin  "reg(FRAME:acc#41.itm#3)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(1)} -pin  "reg(FRAME:acc#41.itm#3)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(2)} -pin  "reg(FRAME:acc#41.itm#3)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(3)} -pin  "reg(FRAME:acc#41.itm#3)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(4)} -pin  "reg(FRAME:acc#41.itm#3)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(5)} -pin  "reg(FRAME:acc#41.itm#3)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(FRAME:acc#41.itm#3)" {clk} -attr xrf 5198 -attr oid 332 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#41.itm#3)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#41.itm#3)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#41.itm#3(0)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(1)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(2)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(3)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(4)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(5)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load inst "FRAME:mul#1" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 5199 -attr oid 333 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc#43.itm(10)} -pin  "FRAME:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {ACC1:acc#43.itm(11)} -pin  "FRAME:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {ACC1:acc#43.itm(12)} -pin  "FRAME:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {PWR} -pin  "FRAME:mul#1" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#1.itm(0)} -pin  "FRAME:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "FRAME:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "FRAME:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "FRAME:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "FRAME:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "FRAME:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "FRAME:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "FRAME:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "FRAME:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load inst "reg(FRAME:mul#1.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 5200 -attr oid 334 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#1.itm#1)}
+load net {FRAME:mul#1.itm(0)} -pin  "reg(FRAME:mul#1.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "reg(FRAME:mul#1.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "reg(FRAME:mul#1.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "reg(FRAME:mul#1.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "reg(FRAME:mul#1.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "reg(FRAME:mul#1.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "reg(FRAME:mul#1.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "reg(FRAME:mul#1.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "reg(FRAME:mul#1.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#1.itm#1)" {clk} -attr xrf 5201 -attr oid 335 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#1.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#1.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#1.itm#1(0)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(1)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(2)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(3)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(4)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(5)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(6)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(7)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(8)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load inst "reg(red:slc(red#2.sg1).itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 5202 -attr oid 336 -attr vt d -attr @path {/sobel/sobel:core/reg(red:slc(red#2.sg1).itm#1)}
+load net {ACC1:acc#43.itm(4)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC1:acc#43.itm(5)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC1:acc#43.itm(6)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC1:acc#43.itm(7)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC1:acc#43.itm(8)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC1:acc#43.itm(9)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(red:slc(red#2.sg1).itm#1)" {clk} -attr xrf 5203 -attr oid 337 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(red:slc(red#2.sg1).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {red:slc(red#2.sg1).itm#1(0)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(1)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(2)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(3)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(4)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(5)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load inst "FRAME:not#7" "not(1)" "INTERFACE" -attr xrf 5204 -attr oid 338 -attr @path {/sobel/sobel:core/FRAME:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod.sva(5)} -pin  "FRAME:not#7" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#6.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load inst "FRAME:not#5" "not(3)" "INTERFACE" -attr xrf 5205 -attr oid 339 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod.sva(3)} -pin  "FRAME:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#2.itm}
+load net {acc.imod.sva(4)} -pin  "FRAME:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#2.itm}
+load net {acc.imod.sva(5)} -pin  "FRAME:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#2.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load inst "FRAME:not#4" "not(1)" "INTERFACE" -attr xrf 5206 -attr oid 340 -attr @path {/sobel/sobel:core/FRAME:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod.sva(5)} -pin  "FRAME:not#4" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#3.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:not#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#4.itm}
+load inst "FRAME:acc#42" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 5207 -attr oid 341 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {PWR} -pin  "FRAME:acc#42" {A(0)} -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {acc.imod.sva(0)} -pin  "FRAME:acc#42" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {acc.imod.sva(1)} -pin  "FRAME:acc#42" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {acc.imod.sva(2)} -pin  "FRAME:acc#42" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {PWR} -pin  "FRAME:acc#42" {A(4)} -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:acc#42" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:acc#42" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:acc#42" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:acc#42" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:acc#42.itm(0)} -pin  "FRAME:acc#42" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(1)} -pin  "FRAME:acc#42" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(2)} -pin  "FRAME:acc#42" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(3)} -pin  "FRAME:acc#42" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(4)} -pin  "FRAME:acc#42" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load inst "FRAME:not#39" "not(1)" "INTERFACE" -attr xrf 5208 -attr oid 342 -attr vt c -attr @path {/sobel/sobel:core/FRAME:not#39} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#42.itm(4)} -pin  "FRAME:not#39" {A(0)} -attr vt c -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:not#39.itm} -pin  "FRAME:not#39" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/FRAME:not#39.itm}
+load inst "FRAME:acc#36" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 5209 -attr oid 343 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#39.itm} -pin  "FRAME:acc#36" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {PWR} -pin  "FRAME:acc#36" {A(1)} -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:acc#36" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {acc.imod.sva(3)} -pin  "FRAME:acc#36" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#4.itm}
+load net {acc.imod.sva(4)} -pin  "FRAME:acc#36" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#4.itm}
+load net {FRAME:acc#36.itm(0)} -pin  "FRAME:acc#36" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(1)} -pin  "FRAME:acc#36" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(2)} -pin  "FRAME:acc#36" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(3)} -pin  "FRAME:acc#36" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load inst "FRAME:not#6" "not(3)" "INTERFACE" -attr xrf 5210 -attr oid 344 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#43.itm(7)} -pin  "FRAME:not#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {ACC1:acc#43.itm(8)} -pin  "FRAME:not#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {ACC1:acc#43.itm(9)} -pin  "FRAME:not#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:not#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:not#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:not#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load inst "FRAME:acc#37" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 5211 -attr oid 345 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#36.itm(0)} -pin  "FRAME:acc#37" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(1)} -pin  "FRAME:acc#37" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(2)} -pin  "FRAME:acc#37" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(3)} -pin  "FRAME:acc#37" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:acc#37" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:acc#37" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:acc#37" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:acc#37.itm(0)} -pin  "FRAME:acc#37" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(1)} -pin  "FRAME:acc#37" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(2)} -pin  "FRAME:acc#37" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(3)} -pin  "FRAME:acc#37" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(4)} -pin  "FRAME:acc#37" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load inst "reg(FRAME:acc#37.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 5212 -attr oid 346 -attr vt dc -attr @path {/sobel/sobel:core/reg(FRAME:acc#37.itm#1)}
+load net {FRAME:acc#37.itm(0)} -pin  "reg(FRAME:acc#37.itm#1)" {D(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(1)} -pin  "reg(FRAME:acc#37.itm#1)" {D(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(2)} -pin  "reg(FRAME:acc#37.itm#1)" {D(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(3)} -pin  "reg(FRAME:acc#37.itm#1)" {D(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(4)} -pin  "reg(FRAME:acc#37.itm#1)" {D(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#37.itm#1)" {clk} -attr xrf 5213 -attr oid 347 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#37.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#37.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#37.itm#1(0)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(1)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(2)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(3)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(4)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load inst "reg(FRAME:slc(acc.imod)#4.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 5214 -attr oid 348 -attr @path {/sobel/sobel:core/reg(FRAME:slc(acc.imod)#4.itm#1)}
+load net {acc.imod.sva(5)} -pin  "reg(FRAME:slc(acc.imod)#4.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod.sva).itm}
+load net {GND} -pin  "reg(FRAME:slc(acc.imod)#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(FRAME:slc(acc.imod)#4.itm#1)" {clk} -attr xrf 5215 -attr oid 349 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(acc.imod)#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(acc.imod)#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(acc.imod)#4.itm#1} -pin  "reg(FRAME:slc(acc.imod)#4.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:slc(acc.imod)#4.itm#1}
+load inst "FRAME:mul#4" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 5216 -attr oid 350 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC1:acc#45.itm(13)} -pin  "FRAME:mul#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#10.itm}
+load net {ACC1:acc#45.itm(14)} -pin  "FRAME:mul#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#10.itm}
+load net {PWR} -pin  "FRAME:mul#4" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#4.itm(0)} -pin  "FRAME:mul#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(1)} -pin  "FRAME:mul#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(2)} -pin  "FRAME:mul#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(3)} -pin  "FRAME:mul#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(4)} -pin  "FRAME:mul#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(5)} -pin  "FRAME:mul#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(6)} -pin  "FRAME:mul#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(7)} -pin  "FRAME:mul#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(8)} -pin  "FRAME:mul#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(9)} -pin  "FRAME:mul#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(10)} -pin  "FRAME:mul#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load inst "reg(FRAME:mul#4.itm#1)" "reg(11,1,1,-1,0)" "INTERFACE" -attr xrf 5217 -attr oid 351 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#4.itm#1)}
+load net {FRAME:mul#4.itm(0)} -pin  "reg(FRAME:mul#4.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(1)} -pin  "reg(FRAME:mul#4.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(2)} -pin  "reg(FRAME:mul#4.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(3)} -pin  "reg(FRAME:mul#4.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(4)} -pin  "reg(FRAME:mul#4.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(5)} -pin  "reg(FRAME:mul#4.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(6)} -pin  "reg(FRAME:mul#4.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(7)} -pin  "reg(FRAME:mul#4.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(8)} -pin  "reg(FRAME:mul#4.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(9)} -pin  "reg(FRAME:mul#4.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(10)} -pin  "reg(FRAME:mul#4.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_11}
+load net {clk} -pin  "reg(FRAME:mul#4.itm#1)" {clk} -attr xrf 5218 -attr oid 352 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#4.itm#1(0)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(1)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(2)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(3)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(4)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(5)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(6)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(7)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(8)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(9)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(10)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load inst "FRAME:mul#5" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 5219 -attr oid 353 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc#45.itm(10)} -pin  "FRAME:mul#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "FRAME:mul#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {ACC1:acc#45.itm(12)} -pin  "FRAME:mul#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {PWR} -pin  "FRAME:mul#5" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#5" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#5" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#5.itm(0)} -pin  "FRAME:mul#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(1)} -pin  "FRAME:mul#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(2)} -pin  "FRAME:mul#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(3)} -pin  "FRAME:mul#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(4)} -pin  "FRAME:mul#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(5)} -pin  "FRAME:mul#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(6)} -pin  "FRAME:mul#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(7)} -pin  "FRAME:mul#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(8)} -pin  "FRAME:mul#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load inst "reg(FRAME:mul#5.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 5220 -attr oid 354 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#5.itm#1)}
+load net {FRAME:mul#5.itm(0)} -pin  "reg(FRAME:mul#5.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(1)} -pin  "reg(FRAME:mul#5.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(2)} -pin  "reg(FRAME:mul#5.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(3)} -pin  "reg(FRAME:mul#5.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(4)} -pin  "reg(FRAME:mul#5.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(5)} -pin  "reg(FRAME:mul#5.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(6)} -pin  "reg(FRAME:mul#5.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(7)} -pin  "reg(FRAME:mul#5.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(8)} -pin  "reg(FRAME:mul#5.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#5.itm#1)" {clk} -attr xrf 5221 -attr oid 355 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#5.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#5.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#5.itm#1(0)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(1)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(2)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(3)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(4)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(5)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(6)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(7)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(8)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load inst "reg(blue:slc(blue#2.sg1).itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 5222 -attr oid 356 -attr vt d -attr @path {/sobel/sobel:core/reg(blue:slc(blue#2.sg1).itm#1)}
+load net {ACC1:acc#45.itm(4)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC1:acc#45.itm(5)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC1:acc#45.itm(6)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC1:acc#45.itm(7)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC1:acc#45.itm(8)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC1:acc#45.itm(9)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {clk} -attr xrf 5223 -attr oid 357 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {blue:slc(blue#2.sg1).itm#1(0)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(1)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(2)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(3)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(4)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(5)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load inst "FRAME:not#23" "not(1)" "INTERFACE" -attr xrf 5224 -attr oid 358 -attr @path {/sobel/sobel:core/FRAME:not#23} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#4.sva(5)} -pin  "FRAME:not#23" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#6.itm}
+load net {FRAME:not#23.itm} -pin  "FRAME:not#23" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#23.itm}
+load inst "FRAME:not#21" "not(3)" "INTERFACE" -attr xrf 5225 -attr oid 359 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#4.sva(3)} -pin  "FRAME:not#21" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#2.itm}
+load net {acc.imod#4.sva(4)} -pin  "FRAME:not#21" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#2.itm}
+load net {acc.imod#4.sva(5)} -pin  "FRAME:not#21" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#2.itm}
+load net {FRAME:not#21.itm(0)} -pin  "FRAME:not#21" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {FRAME:not#21.itm(1)} -pin  "FRAME:not#21" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {FRAME:not#21.itm(2)} -pin  "FRAME:not#21" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load inst "FRAME:not#20" "not(1)" "INTERFACE" -attr xrf 5226 -attr oid 360 -attr @path {/sobel/sobel:core/FRAME:not#20} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#4.sva(5)} -pin  "FRAME:not#20" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#3.itm}
+load net {FRAME:not#20.itm} -pin  "FRAME:not#20" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load inst "FRAME:acc#35" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 5227 -attr oid 361 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {PWR} -pin  "FRAME:acc#35" {A(0)} -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {acc.imod#4.sva(0)} -pin  "FRAME:acc#35" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {acc.imod#4.sva(1)} -pin  "FRAME:acc#35" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {acc.imod#4.sva(2)} -pin  "FRAME:acc#35" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {PWR} -pin  "FRAME:acc#35" {A(4)} -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {FRAME:not#20.itm} -pin  "FRAME:acc#35" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(0)} -pin  "FRAME:acc#35" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(1)} -pin  "FRAME:acc#35" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(2)} -pin  "FRAME:acc#35" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:acc#35.itm(0)} -pin  "FRAME:acc#35" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(1)} -pin  "FRAME:acc#35" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(2)} -pin  "FRAME:acc#35" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(3)} -pin  "FRAME:acc#35" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(4)} -pin  "FRAME:acc#35" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load inst "FRAME:not#41" "not(1)" "INTERFACE" -attr xrf 5228 -attr oid 362 -attr @path {/sobel/sobel:core/FRAME:not#41} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#35.itm(4)} -pin  "FRAME:not#41" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#6.itm}
+load net {FRAME:not#41.itm} -pin  "FRAME:not#41" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#41.itm}
+load inst "FRAME:acc#29" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 5229 -attr oid 363 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#41.itm} -pin  "FRAME:acc#29" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {PWR} -pin  "FRAME:acc#29" {A(1)} -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {FRAME:not#23.itm} -pin  "FRAME:acc#29" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {acc.imod#4.sva(3)} -pin  "FRAME:acc#29" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#4.itm}
+load net {acc.imod#4.sva(4)} -pin  "FRAME:acc#29" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#4.itm}
+load net {FRAME:acc#29.itm(0)} -pin  "FRAME:acc#29" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(1)} -pin  "FRAME:acc#29" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(2)} -pin  "FRAME:acc#29" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(3)} -pin  "FRAME:acc#29" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load inst "FRAME:not#22" "not(3)" "INTERFACE" -attr xrf 5230 -attr oid 364 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#45.itm(7)} -pin  "FRAME:not#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {ACC1:acc#45.itm(8)} -pin  "FRAME:not#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {ACC1:acc#45.itm(9)} -pin  "FRAME:not#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {FRAME:not#22.itm(0)} -pin  "FRAME:not#22" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(1)} -pin  "FRAME:not#22" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(2)} -pin  "FRAME:not#22" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load inst "FRAME:acc#30" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 5231 -attr oid 365 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#29.itm(0)} -pin  "FRAME:acc#30" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(1)} -pin  "FRAME:acc#30" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(2)} -pin  "FRAME:acc#30" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(3)} -pin  "FRAME:acc#30" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:not#22.itm(0)} -pin  "FRAME:acc#30" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(1)} -pin  "FRAME:acc#30" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(2)} -pin  "FRAME:acc#30" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:acc#30.itm(0)} -pin  "FRAME:acc#30" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(1)} -pin  "FRAME:acc#30" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(2)} -pin  "FRAME:acc#30" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(3)} -pin  "FRAME:acc#30" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(4)} -pin  "FRAME:acc#30" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load inst "reg(FRAME:acc#30.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 5232 -attr oid 366 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#30.itm#1)}
+load net {FRAME:acc#30.itm(0)} -pin  "reg(FRAME:acc#30.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(1)} -pin  "reg(FRAME:acc#30.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(2)} -pin  "reg(FRAME:acc#30.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(3)} -pin  "reg(FRAME:acc#30.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(4)} -pin  "reg(FRAME:acc#30.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#30.itm#1)" {clk} -attr xrf 5233 -attr oid 367 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#30.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#30.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#30.itm#1(0)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(1)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(2)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(3)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(4)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load inst "reg(FRAME:slc(acc.imod#4)#4.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 5234 -attr oid 368 -attr @path {/sobel/sobel:core/reg(FRAME:slc(acc.imod#4)#4.itm#1)}
+load net {acc.imod#4.sva(5)} -pin  "reg(FRAME:slc(acc.imod#4)#4.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva).itm}
+load net {GND} -pin  "reg(FRAME:slc(acc.imod#4)#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(FRAME:slc(acc.imod#4)#4.itm#1)" {clk} -attr xrf 5235 -attr oid 369 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(acc.imod#4)#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(acc.imod#4)#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(acc.imod#4)#4.itm#1} -pin  "reg(FRAME:slc(acc.imod#4)#4.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:slc(acc.imod#4)#4.itm#1}
+load inst "reg(blue:slc(blue#2.sg1)#12.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 5236 -attr oid 370 -attr @path {/sobel/sobel:core/reg(blue:slc(blue#2.sg1)#12.itm#1)}
+load net {ACC1:acc#45.itm(15)} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva).itm}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {clk} -attr xrf 5237 -attr oid 371 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1)#12.itm#1}
+load inst "FRAME:mul#2" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 5238 -attr oid 372 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC1:acc#44.itm(13)} -pin  "FRAME:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#10.itm}
+load net {ACC1:acc#44.itm(14)} -pin  "FRAME:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#10.itm}
+load net {PWR} -pin  "FRAME:mul#2" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#2.itm(0)} -pin  "FRAME:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(1)} -pin  "FRAME:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(2)} -pin  "FRAME:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(3)} -pin  "FRAME:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(4)} -pin  "FRAME:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(5)} -pin  "FRAME:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(6)} -pin  "FRAME:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(7)} -pin  "FRAME:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(8)} -pin  "FRAME:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(9)} -pin  "FRAME:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(10)} -pin  "FRAME:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load inst "reg(FRAME:mul#2.itm#1)" "reg(11,1,1,-1,0)" "INTERFACE" -attr xrf 5239 -attr oid 373 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#2.itm#1)}
+load net {FRAME:mul#2.itm(0)} -pin  "reg(FRAME:mul#2.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(1)} -pin  "reg(FRAME:mul#2.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(2)} -pin  "reg(FRAME:mul#2.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(3)} -pin  "reg(FRAME:mul#2.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(4)} -pin  "reg(FRAME:mul#2.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(5)} -pin  "reg(FRAME:mul#2.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(6)} -pin  "reg(FRAME:mul#2.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(7)} -pin  "reg(FRAME:mul#2.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(8)} -pin  "reg(FRAME:mul#2.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(9)} -pin  "reg(FRAME:mul#2.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(10)} -pin  "reg(FRAME:mul#2.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_11}
+load net {clk} -pin  "reg(FRAME:mul#2.itm#1)" {clk} -attr xrf 5240 -attr oid 374 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#2.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#2.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#2.itm#1(0)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(1)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(2)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(3)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(4)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(5)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(6)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(7)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(8)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(9)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(10)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load inst "FRAME:mul#3" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 5241 -attr oid 375 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc#44.itm(10)} -pin  "FRAME:mul#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {ACC1:acc#44.itm(11)} -pin  "FRAME:mul#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {ACC1:acc#44.itm(12)} -pin  "FRAME:mul#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {PWR} -pin  "FRAME:mul#3" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#3" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#3" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#3.itm(0)} -pin  "FRAME:mul#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "FRAME:mul#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "FRAME:mul#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "FRAME:mul#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "FRAME:mul#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "FRAME:mul#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "FRAME:mul#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "FRAME:mul#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "FRAME:mul#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load inst "reg(FRAME:mul#3.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 5242 -attr oid 376 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#3.itm#1)}
+load net {FRAME:mul#3.itm(0)} -pin  "reg(FRAME:mul#3.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "reg(FRAME:mul#3.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "reg(FRAME:mul#3.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "reg(FRAME:mul#3.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "reg(FRAME:mul#3.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "reg(FRAME:mul#3.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "reg(FRAME:mul#3.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "reg(FRAME:mul#3.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "reg(FRAME:mul#3.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#3.itm#1)" {clk} -attr xrf 5243 -attr oid 377 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#3.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#3.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#3.itm#1(0)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(1)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(2)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(3)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(4)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(5)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(6)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(7)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(8)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load inst "reg(green:slc(green#2.sg1).itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 5244 -attr oid 378 -attr vt d -attr @path {/sobel/sobel:core/reg(green:slc(green#2.sg1).itm#1)}
+load net {ACC1:acc#44.itm(4)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC1:acc#44.itm(5)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC1:acc#44.itm(6)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC1:acc#44.itm(7)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC1:acc#44.itm(8)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC1:acc#44.itm(9)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(green:slc(green#2.sg1).itm#1)" {clk} -attr xrf 5245 -attr oid 379 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(green:slc(green#2.sg1).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {green:slc(green#2.sg1).itm#1(0)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(1)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(2)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(3)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(4)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(5)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load inst "FRAME:not#15" "not(1)" "INTERFACE" -attr xrf 5246 -attr oid 380 -attr @path {/sobel/sobel:core/FRAME:not#15} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#2.sva(5)} -pin  "FRAME:not#15" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#6.itm}
+load net {FRAME:not#15.itm} -pin  "FRAME:not#15" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#15.itm}
+load inst "FRAME:not#13" "not(3)" "INTERFACE" -attr xrf 5247 -attr oid 381 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#2.sva(3)} -pin  "FRAME:not#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#2.itm}
+load net {acc.imod#2.sva(4)} -pin  "FRAME:not#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#2.itm}
+load net {acc.imod#2.sva(5)} -pin  "FRAME:not#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#2.itm}
+load net {FRAME:not#13.itm(0)} -pin  "FRAME:not#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {FRAME:not#13.itm(1)} -pin  "FRAME:not#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {FRAME:not#13.itm(2)} -pin  "FRAME:not#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load inst "FRAME:not#12" "not(1)" "INTERFACE" -attr xrf 5248 -attr oid 382 -attr @path {/sobel/sobel:core/FRAME:not#12} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#2.sva(5)} -pin  "FRAME:not#12" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#3.itm}
+load net {FRAME:not#12.itm} -pin  "FRAME:not#12" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#12.itm}
+load inst "FRAME:acc#23" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 5249 -attr oid 383 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {PWR} -pin  "FRAME:acc#23" {A(0)} -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {acc.imod#2.sva(0)} -pin  "FRAME:acc#23" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {acc.imod#2.sva(1)} -pin  "FRAME:acc#23" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {acc.imod#2.sva(2)} -pin  "FRAME:acc#23" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {PWR} -pin  "FRAME:acc#23" {A(4)} -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {FRAME:not#12.itm} -pin  "FRAME:acc#23" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(0)} -pin  "FRAME:acc#23" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(1)} -pin  "FRAME:acc#23" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(2)} -pin  "FRAME:acc#23" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:acc#23.itm(0)} -pin  "FRAME:acc#23" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(1)} -pin  "FRAME:acc#23" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(2)} -pin  "FRAME:acc#23" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(3)} -pin  "FRAME:acc#23" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(4)} -pin  "FRAME:acc#23" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load inst "FRAME:not#43" "not(1)" "INTERFACE" -attr xrf 5250 -attr oid 384 -attr @path {/sobel/sobel:core/FRAME:not#43} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#23.itm(4)} -pin  "FRAME:not#43" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#5.itm}
+load net {FRAME:not#43.itm} -pin  "FRAME:not#43" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#43.itm}
+load inst "FRAME:acc#17" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 5251 -attr oid 385 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#43.itm} -pin  "FRAME:acc#17" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {PWR} -pin  "FRAME:acc#17" {A(1)} -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {FRAME:not#15.itm} -pin  "FRAME:acc#17" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {acc.imod#2.sva(3)} -pin  "FRAME:acc#17" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#4.itm}
+load net {acc.imod#2.sva(4)} -pin  "FRAME:acc#17" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#4.itm}
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:acc#17" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:acc#17" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load inst "FRAME:not#14" "not(3)" "INTERFACE" -attr xrf 5252 -attr oid 386 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#44.itm(7)} -pin  "FRAME:not#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {ACC1:acc#44.itm(8)} -pin  "FRAME:not#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {ACC1:acc#44.itm(9)} -pin  "FRAME:not#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {FRAME:not#14.itm(0)} -pin  "FRAME:not#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(1)} -pin  "FRAME:not#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(2)} -pin  "FRAME:not#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load inst "FRAME:acc#18" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 5253 -attr oid 387 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:acc#18" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:acc#18" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:not#14.itm(0)} -pin  "FRAME:acc#18" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(1)} -pin  "FRAME:acc#18" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(2)} -pin  "FRAME:acc#18" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:acc#18.itm(0)} -pin  "FRAME:acc#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(1)} -pin  "FRAME:acc#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(2)} -pin  "FRAME:acc#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(3)} -pin  "FRAME:acc#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(4)} -pin  "FRAME:acc#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load inst "reg(FRAME:acc#18.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 5254 -attr oid 388 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#18.itm#1)}
+load net {FRAME:acc#18.itm(0)} -pin  "reg(FRAME:acc#18.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(1)} -pin  "reg(FRAME:acc#18.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(2)} -pin  "reg(FRAME:acc#18.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(3)} -pin  "reg(FRAME:acc#18.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(4)} -pin  "reg(FRAME:acc#18.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#18.itm#1)" {clk} -attr xrf 5255 -attr oid 389 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#18.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#18.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#18.itm#1(0)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(1)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(2)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(3)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(4)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load inst "reg(FRAME:slc(acc.imod#2)#4.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 5256 -attr oid 390 -attr @path {/sobel/sobel:core/reg(FRAME:slc(acc.imod#2)#4.itm#1)}
+load net {acc.imod#2.sva(5)} -pin  "reg(FRAME:slc(acc.imod#2)#4.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva).itm}
+load net {GND} -pin  "reg(FRAME:slc(acc.imod#2)#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(FRAME:slc(acc.imod#2)#4.itm#1)" {clk} -attr xrf 5257 -attr oid 391 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(acc.imod#2)#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(acc.imod#2)#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(acc.imod#2)#4.itm#1} -pin  "reg(FRAME:slc(acc.imod#2)#4.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:slc(acc.imod#2)#4.itm#1}
+load inst "reg(green:slc(green#2.sg1)#12.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 5258 -attr oid 392 -attr @path {/sobel/sobel:core/reg(green:slc(green#2.sg1)#12.itm#1)}
+load net {ACC1:acc#44.itm(15)} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva).itm}
+load net {GND} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {clk} -attr xrf 5259 -attr oid 393 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {green:slc(green#2.sg1)#12.itm#1} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/green:slc(green#2.sg1)#12.itm#1}
+load inst "FRAME:for:not#7" "not(1)" "INTERFACE" -attr xrf 5260 -attr oid 394 -attr @path {/sobel/sobel:core/FRAME:for:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:not#7" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#21.itm}
+load net {FRAME:for:not#7.itm} -pin  "FRAME:for:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#7.itm}
+load inst "reg(exit:FRAME:for.sva#1.st#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 5261 -attr oid 395 -attr vt c -attr @path {/sobel/sobel:core/reg(exit:FRAME:for.sva#1.st#1)}
+load net {FRAME:for:not#7.itm} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#7.itm}
+load net {GND} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {clk} -attr xrf 5262 -attr oid 396 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for.sva#1.st#1} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load inst "reg(i#6.sva#1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 5263 -attr oid 397 -attr vt d -attr @path {/sobel/sobel:core/reg(i#6.sva#1)}
+load net {i#6.sva#2(0)} -pin  "reg(i#6.sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "reg(i#6.sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {GND} -pin  "reg(i#6.sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(i#6.sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(i#6.sva#1)" {clk} -attr xrf 5264 -attr oid 398 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(i#6.sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(i#6.sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {i#6.sva#1(0)} -pin  "reg(i#6.sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "reg(i#6.sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load inst "FRAME:for:not" "not(1)" "INTERFACE" -attr xrf 5265 -attr oid 399 -attr @path {/sobel/sobel:core/FRAME:for:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#1.itm}
+load net {FRAME:for:not.itm} -pin  "FRAME:for:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load inst "FRAME:and" "and(2,1)" "INTERFACE" -attr xrf 5266 -attr oid 400 -attr @path {/sobel/sobel:core/FRAME:and} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {FRAME:for:not.itm} -pin  "FRAME:and" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "FRAME:and" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load net {FRAME:and.itm} -pin  "FRAME:and" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load inst "reg(exit:FRAME#1.sva)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 5267 -attr oid 401 -attr @path {/sobel/sobel:core/reg(exit:FRAME#1.sva)}
+load net {FRAME:and.itm} -pin  "reg(exit:FRAME#1.sva)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load net {PWR} -pin  "reg(exit:FRAME#1.sva)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1_Not}
+load net {clk} -pin  "reg(exit:FRAME#1.sva)" {clk} -attr xrf 5268 -attr oid 402 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME#1.sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME#1.sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME#1.sva} -pin  "reg(exit:FRAME#1.sva)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load inst "reg(main.stage_0#2)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 5269 -attr oid 403 -attr @path {/sobel/sobel:core/reg(main.stage_0#2)}
+load net {PWR} -pin  "reg(main.stage_0#2)" {D(0)} -attr @path {/sobel/sobel:core/Cn1_1#2}
+load net {GND} -pin  "reg(main.stage_0#2)" {DRa(0)} -attr @path {/sobel/sobel:core/Cn2_2#4}
+load net {clk} -pin  "reg(main.stage_0#2)" {clk} -attr xrf 5270 -attr oid 404 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(main.stage_0#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(main.stage_0#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {main.stage_0#2} -pin  "reg(main.stage_0#2)" {Z(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load inst "reg(regs.regs(2).lpi#1.dfm)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 5271 -attr oid 405 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(2).lpi#1.dfm)}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(30)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(31)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(32)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(33)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(34)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(35)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(36)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(37)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(38)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(39)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(40)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(41)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(42)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(43)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(44)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(45)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(46)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(47)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(48)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(49)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(50)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(51)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(52)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(53)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(54)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(55)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(56)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(57)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(58)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(59)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(60)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(61)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(62)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(63)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(64)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(65)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(66)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(67)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(68)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(69)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(70)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(71)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(72)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(73)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(74)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(75)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(76)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(77)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(78)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(79)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(80)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(81)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(82)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(83)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(84)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(85)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(86)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(87)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(88)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(89)} -attr @path {/sobel/sobel:core/C0_90}
+load net {clk} -pin  "reg(regs.regs(2).lpi#1.dfm)" {clk} -attr xrf 5272 -attr oid 406 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(2).lpi#1.dfm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(2).lpi#1.dfm(0)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(1)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(2)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(3)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(4)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(5)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(6)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(7)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(8)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(9)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(10)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(11)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(12)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(13)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(14)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(15)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(16)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(17)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(18)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(19)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(20)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(21)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(22)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(23)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(24)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(25)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(26)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(27)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(28)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(29)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(30)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(31)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(32)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(33)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(34)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(35)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(36)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(37)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(38)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(39)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(40)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(41)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(42)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(43)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(44)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(45)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(46)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(47)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(48)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(49)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(50)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(51)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(52)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(53)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(54)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(55)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(56)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(57)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(58)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(59)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(60)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(61)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(62)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(63)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(64)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(65)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(66)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(67)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(68)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(69)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(70)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(71)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(72)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(73)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(74)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(75)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(76)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(77)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(78)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(79)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(80)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(81)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(82)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(83)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(84)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(85)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(86)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(87)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(88)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(89)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load inst "reg(regs.regs(1).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 5273 -attr oid 407 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(1).sva)}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "reg(regs.regs(1).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "reg(regs.regs(1).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "reg(regs.regs(1).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "reg(regs.regs(1).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "reg(regs.regs(1).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "reg(regs.regs(1).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "reg(regs.regs(1).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "reg(regs.regs(1).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "reg(regs.regs(1).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "reg(regs.regs(1).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "reg(regs.regs(1).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "reg(regs.regs(1).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "reg(regs.regs(1).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "reg(regs.regs(1).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "reg(regs.regs(1).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "reg(regs.regs(1).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "reg(regs.regs(1).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "reg(regs.regs(1).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "reg(regs.regs(1).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "reg(regs.regs(1).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "reg(regs.regs(1).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "reg(regs.regs(1).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "reg(regs.regs(1).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "reg(regs.regs(1).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "reg(regs.regs(1).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "reg(regs.regs(1).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "reg(regs.regs(1).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "reg(regs.regs(1).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "reg(regs.regs(1).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "reg(regs.regs(1).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "reg(regs.regs(1).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "reg(regs.regs(1).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "reg(regs.regs(1).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "reg(regs.regs(1).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "reg(regs.regs(1).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "reg(regs.regs(1).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "reg(regs.regs(1).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "reg(regs.regs(1).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "reg(regs.regs(1).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "reg(regs.regs(1).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "reg(regs.regs(1).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "reg(regs.regs(1).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "reg(regs.regs(1).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "reg(regs.regs(1).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "reg(regs.regs(1).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "reg(regs.regs(1).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "reg(regs.regs(1).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "reg(regs.regs(1).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "reg(regs.regs(1).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "reg(regs.regs(1).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "reg(regs.regs(1).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "reg(regs.regs(1).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "reg(regs.regs(1).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "reg(regs.regs(1).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "reg(regs.regs(1).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "reg(regs.regs(1).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "reg(regs.regs(1).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "reg(regs.regs(1).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "reg(regs.regs(1).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "reg(regs.regs(1).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "reg(regs.regs(1).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "reg(regs.regs(1).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "reg(regs.regs(1).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "reg(regs.regs(1).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "reg(regs.regs(1).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "reg(regs.regs(1).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "reg(regs.regs(1).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "reg(regs.regs(1).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "reg(regs.regs(1).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "reg(regs.regs(1).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "reg(regs.regs(1).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "reg(regs.regs(1).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "reg(regs.regs(1).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "reg(regs.regs(1).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "reg(regs.regs(1).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "reg(regs.regs(1).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "reg(regs.regs(1).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "reg(regs.regs(1).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "reg(regs.regs(1).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "reg(regs.regs(1).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "reg(regs.regs(1).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "reg(regs.regs(1).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "reg(regs.regs(1).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "reg(regs.regs(1).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "reg(regs.regs(1).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "reg(regs.regs(1).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "reg(regs.regs(1).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "reg(regs.regs(1).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "reg(regs.regs(1).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "reg(regs.regs(1).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {clk} -pin  "reg(regs.regs(1).sva)" {clk} -attr xrf 5274 -attr oid 408 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(1).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(1).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(1).sva(0)} -pin  "reg(regs.regs(1).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "reg(regs.regs(1).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "reg(regs.regs(1).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "reg(regs.regs(1).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "reg(regs.regs(1).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "reg(regs.regs(1).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "reg(regs.regs(1).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "reg(regs.regs(1).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "reg(regs.regs(1).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "reg(regs.regs(1).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "reg(regs.regs(1).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "reg(regs.regs(1).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "reg(regs.regs(1).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "reg(regs.regs(1).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "reg(regs.regs(1).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "reg(regs.regs(1).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "reg(regs.regs(1).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "reg(regs.regs(1).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "reg(regs.regs(1).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "reg(regs.regs(1).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "reg(regs.regs(1).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "reg(regs.regs(1).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "reg(regs.regs(1).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "reg(regs.regs(1).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "reg(regs.regs(1).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "reg(regs.regs(1).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "reg(regs.regs(1).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "reg(regs.regs(1).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "reg(regs.regs(1).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "reg(regs.regs(1).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "reg(regs.regs(1).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "reg(regs.regs(1).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "reg(regs.regs(1).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "reg(regs.regs(1).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "reg(regs.regs(1).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "reg(regs.regs(1).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "reg(regs.regs(1).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "reg(regs.regs(1).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "reg(regs.regs(1).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "reg(regs.regs(1).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "reg(regs.regs(1).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "reg(regs.regs(1).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "reg(regs.regs(1).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "reg(regs.regs(1).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "reg(regs.regs(1).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "reg(regs.regs(1).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "reg(regs.regs(1).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "reg(regs.regs(1).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "reg(regs.regs(1).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "reg(regs.regs(1).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "reg(regs.regs(1).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "reg(regs.regs(1).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "reg(regs.regs(1).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "reg(regs.regs(1).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "reg(regs.regs(1).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "reg(regs.regs(1).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "reg(regs.regs(1).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "reg(regs.regs(1).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "reg(regs.regs(1).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "reg(regs.regs(1).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "reg(regs.regs(1).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "reg(regs.regs(1).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "reg(regs.regs(1).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "reg(regs.regs(1).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "reg(regs.regs(1).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "reg(regs.regs(1).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "reg(regs.regs(1).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "reg(regs.regs(1).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "reg(regs.regs(1).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "reg(regs.regs(1).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "reg(regs.regs(1).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "reg(regs.regs(1).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "reg(regs.regs(1).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "reg(regs.regs(1).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "reg(regs.regs(1).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "reg(regs.regs(1).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "reg(regs.regs(1).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "reg(regs.regs(1).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "reg(regs.regs(1).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "reg(regs.regs(1).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "reg(regs.regs(1).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "reg(regs.regs(1).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "reg(regs.regs(1).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "reg(regs.regs(1).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "reg(regs.regs(1).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "reg(regs.regs(1).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "reg(regs.regs(1).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "reg(regs.regs(1).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "reg(regs.regs(1).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "reg(regs.regs(1).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load inst "reg(regs.regs(0).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 5275 -attr oid 409 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva)}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "reg(regs.regs(0).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "reg(regs.regs(0).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "reg(regs.regs(0).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "reg(regs.regs(0).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "reg(regs.regs(0).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "reg(regs.regs(0).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "reg(regs.regs(0).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "reg(regs.regs(0).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "reg(regs.regs(0).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "reg(regs.regs(0).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "reg(regs.regs(0).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "reg(regs.regs(0).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "reg(regs.regs(0).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "reg(regs.regs(0).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "reg(regs.regs(0).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "reg(regs.regs(0).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "reg(regs.regs(0).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "reg(regs.regs(0).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "reg(regs.regs(0).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "reg(regs.regs(0).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "reg(regs.regs(0).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "reg(regs.regs(0).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "reg(regs.regs(0).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "reg(regs.regs(0).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "reg(regs.regs(0).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "reg(regs.regs(0).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "reg(regs.regs(0).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "reg(regs.regs(0).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "reg(regs.regs(0).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "reg(regs.regs(0).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "reg(regs.regs(0).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "reg(regs.regs(0).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "reg(regs.regs(0).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "reg(regs.regs(0).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "reg(regs.regs(0).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "reg(regs.regs(0).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "reg(regs.regs(0).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "reg(regs.regs(0).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "reg(regs.regs(0).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "reg(regs.regs(0).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "reg(regs.regs(0).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "reg(regs.regs(0).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "reg(regs.regs(0).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "reg(regs.regs(0).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "reg(regs.regs(0).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "reg(regs.regs(0).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "reg(regs.regs(0).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "reg(regs.regs(0).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "reg(regs.regs(0).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "reg(regs.regs(0).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "reg(regs.regs(0).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "reg(regs.regs(0).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "reg(regs.regs(0).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "reg(regs.regs(0).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "reg(regs.regs(0).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "reg(regs.regs(0).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "reg(regs.regs(0).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "reg(regs.regs(0).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "reg(regs.regs(0).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "reg(regs.regs(0).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "reg(regs.regs(0).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "reg(regs.regs(0).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "reg(regs.regs(0).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "reg(regs.regs(0).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "reg(regs.regs(0).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "reg(regs.regs(0).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "reg(regs.regs(0).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "reg(regs.regs(0).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "reg(regs.regs(0).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "reg(regs.regs(0).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "reg(regs.regs(0).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "reg(regs.regs(0).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "reg(regs.regs(0).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "reg(regs.regs(0).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "reg(regs.regs(0).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "reg(regs.regs(0).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "reg(regs.regs(0).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "reg(regs.regs(0).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "reg(regs.regs(0).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "reg(regs.regs(0).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "reg(regs.regs(0).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "reg(regs.regs(0).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "reg(regs.regs(0).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "reg(regs.regs(0).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "reg(regs.regs(0).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "reg(regs.regs(0).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "reg(regs.regs(0).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "reg(regs.regs(0).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "reg(regs.regs(0).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "reg(regs.regs(0).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {clk} -pin  "reg(regs.regs(0).sva)" {clk} -attr xrf 5276 -attr oid 410 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(0).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(0).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(0).sva(0)} -pin  "reg(regs.regs(0).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "reg(regs.regs(0).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "reg(regs.regs(0).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "reg(regs.regs(0).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "reg(regs.regs(0).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "reg(regs.regs(0).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "reg(regs.regs(0).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "reg(regs.regs(0).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "reg(regs.regs(0).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "reg(regs.regs(0).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "reg(regs.regs(0).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "reg(regs.regs(0).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "reg(regs.regs(0).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "reg(regs.regs(0).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "reg(regs.regs(0).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "reg(regs.regs(0).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "reg(regs.regs(0).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "reg(regs.regs(0).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "reg(regs.regs(0).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "reg(regs.regs(0).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "reg(regs.regs(0).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "reg(regs.regs(0).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "reg(regs.regs(0).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "reg(regs.regs(0).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "reg(regs.regs(0).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "reg(regs.regs(0).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "reg(regs.regs(0).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "reg(regs.regs(0).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "reg(regs.regs(0).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "reg(regs.regs(0).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "reg(regs.regs(0).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "reg(regs.regs(0).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "reg(regs.regs(0).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "reg(regs.regs(0).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "reg(regs.regs(0).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "reg(regs.regs(0).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "reg(regs.regs(0).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "reg(regs.regs(0).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "reg(regs.regs(0).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "reg(regs.regs(0).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "reg(regs.regs(0).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "reg(regs.regs(0).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "reg(regs.regs(0).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "reg(regs.regs(0).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "reg(regs.regs(0).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "reg(regs.regs(0).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "reg(regs.regs(0).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "reg(regs.regs(0).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "reg(regs.regs(0).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "reg(regs.regs(0).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "reg(regs.regs(0).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "reg(regs.regs(0).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "reg(regs.regs(0).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "reg(regs.regs(0).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "reg(regs.regs(0).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "reg(regs.regs(0).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "reg(regs.regs(0).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "reg(regs.regs(0).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "reg(regs.regs(0).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "reg(regs.regs(0).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "reg(regs.regs(0).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "reg(regs.regs(0).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "reg(regs.regs(0).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "reg(regs.regs(0).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "reg(regs.regs(0).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "reg(regs.regs(0).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "reg(regs.regs(0).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "reg(regs.regs(0).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "reg(regs.regs(0).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "reg(regs.regs(0).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "reg(regs.regs(0).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "reg(regs.regs(0).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "reg(regs.regs(0).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "reg(regs.regs(0).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "reg(regs.regs(0).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "reg(regs.regs(0).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "reg(regs.regs(0).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "reg(regs.regs(0).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "reg(regs.regs(0).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "reg(regs.regs(0).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "reg(regs.regs(0).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "reg(regs.regs(0).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "reg(regs.regs(0).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "reg(regs.regs(0).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "reg(regs.regs(0).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "reg(regs.regs(0).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "reg(regs.regs(0).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "reg(regs.regs(0).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "reg(regs.regs(0).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "reg(regs.regs(0).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load inst "reg(exit:FRAME.lpi#1.dfm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 5277 -attr oid 411 -attr @path {/sobel/sobel:core/reg(exit:FRAME.lpi#1.dfm#1)}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {D(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load net {GND} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {clk} -attr xrf 5278 -attr oid 412 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME.lpi#1.dfm#1} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1}
+load inst "reg(b(2).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 5279 -attr oid 413 -attr vt d -attr @path {/sobel/sobel:core/reg(b(2).sva#1)}
+load net {b(2).sva#3(0)} -pin  "reg(b(2).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(1)} -pin  "reg(b(2).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(2)} -pin  "reg(b(2).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(3)} -pin  "reg(b(2).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(4)} -pin  "reg(b(2).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(5)} -pin  "reg(b(2).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(6)} -pin  "reg(b(2).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(7)} -pin  "reg(b(2).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(8)} -pin  "reg(b(2).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(9)} -pin  "reg(b(2).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(10)} -pin  "reg(b(2).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(11)} -pin  "reg(b(2).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(12)} -pin  "reg(b(2).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(13)} -pin  "reg(b(2).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(14)} -pin  "reg(b(2).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(15)} -pin  "reg(b(2).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(b(2).sva#1)" {clk} -attr xrf 5280 -attr oid 414 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(b(2).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(b(2).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {b(2).sva#1(0)} -pin  "reg(b(2).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(1)} -pin  "reg(b(2).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(2)} -pin  "reg(b(2).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(3)} -pin  "reg(b(2).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(4)} -pin  "reg(b(2).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(5)} -pin  "reg(b(2).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(6)} -pin  "reg(b(2).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(7)} -pin  "reg(b(2).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(8)} -pin  "reg(b(2).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(9)} -pin  "reg(b(2).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(10)} -pin  "reg(b(2).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(11)} -pin  "reg(b(2).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(12)} -pin  "reg(b(2).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(13)} -pin  "reg(b(2).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(14)} -pin  "reg(b(2).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(15)} -pin  "reg(b(2).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load inst "reg(b(0).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 5281 -attr oid 415 -attr vt d -attr @path {/sobel/sobel:core/reg(b(0).sva#1)}
+load net {b(0).sva#3(0)} -pin  "reg(b(0).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(1)} -pin  "reg(b(0).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(2)} -pin  "reg(b(0).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(3)} -pin  "reg(b(0).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(4)} -pin  "reg(b(0).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(5)} -pin  "reg(b(0).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(6)} -pin  "reg(b(0).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(7)} -pin  "reg(b(0).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(8)} -pin  "reg(b(0).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(9)} -pin  "reg(b(0).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(10)} -pin  "reg(b(0).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(11)} -pin  "reg(b(0).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(12)} -pin  "reg(b(0).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(13)} -pin  "reg(b(0).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(14)} -pin  "reg(b(0).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(15)} -pin  "reg(b(0).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(b(0).sva#1)" {clk} -attr xrf 5282 -attr oid 416 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(b(0).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(b(0).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {b(0).sva#1(0)} -pin  "reg(b(0).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(1)} -pin  "reg(b(0).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(2)} -pin  "reg(b(0).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(3)} -pin  "reg(b(0).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(4)} -pin  "reg(b(0).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(5)} -pin  "reg(b(0).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(6)} -pin  "reg(b(0).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(7)} -pin  "reg(b(0).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(8)} -pin  "reg(b(0).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(9)} -pin  "reg(b(0).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(10)} -pin  "reg(b(0).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(11)} -pin  "reg(b(0).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(12)} -pin  "reg(b(0).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(13)} -pin  "reg(b(0).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(14)} -pin  "reg(b(0).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(15)} -pin  "reg(b(0).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load inst "reg(g(2).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 5283 -attr oid 417 -attr vt d -attr @path {/sobel/sobel:core/reg(g(2).sva#1)}
+load net {g(2).sva#3(0)} -pin  "reg(g(2).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(1)} -pin  "reg(g(2).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(2)} -pin  "reg(g(2).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(3)} -pin  "reg(g(2).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(4)} -pin  "reg(g(2).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(5)} -pin  "reg(g(2).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(6)} -pin  "reg(g(2).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(7)} -pin  "reg(g(2).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(8)} -pin  "reg(g(2).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(9)} -pin  "reg(g(2).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(10)} -pin  "reg(g(2).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(11)} -pin  "reg(g(2).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(12)} -pin  "reg(g(2).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(13)} -pin  "reg(g(2).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(14)} -pin  "reg(g(2).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(15)} -pin  "reg(g(2).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(g(2).sva#1)" {clk} -attr xrf 5284 -attr oid 418 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(g(2).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(g(2).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {g(2).sva#1(0)} -pin  "reg(g(2).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(1)} -pin  "reg(g(2).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(2)} -pin  "reg(g(2).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(3)} -pin  "reg(g(2).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(4)} -pin  "reg(g(2).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(5)} -pin  "reg(g(2).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(6)} -pin  "reg(g(2).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(7)} -pin  "reg(g(2).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(8)} -pin  "reg(g(2).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(9)} -pin  "reg(g(2).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(10)} -pin  "reg(g(2).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(11)} -pin  "reg(g(2).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(12)} -pin  "reg(g(2).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(13)} -pin  "reg(g(2).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(14)} -pin  "reg(g(2).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(15)} -pin  "reg(g(2).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load inst "reg(g(0).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 5285 -attr oid 419 -attr vt d -attr @path {/sobel/sobel:core/reg(g(0).sva#1)}
+load net {g(0).sva#3(0)} -pin  "reg(g(0).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(1)} -pin  "reg(g(0).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(2)} -pin  "reg(g(0).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(3)} -pin  "reg(g(0).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(4)} -pin  "reg(g(0).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(5)} -pin  "reg(g(0).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(6)} -pin  "reg(g(0).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(7)} -pin  "reg(g(0).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(8)} -pin  "reg(g(0).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(9)} -pin  "reg(g(0).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(10)} -pin  "reg(g(0).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(11)} -pin  "reg(g(0).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(12)} -pin  "reg(g(0).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(13)} -pin  "reg(g(0).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(14)} -pin  "reg(g(0).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(15)} -pin  "reg(g(0).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(g(0).sva#1)" {clk} -attr xrf 5286 -attr oid 420 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(g(0).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(g(0).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {g(0).sva#1(0)} -pin  "reg(g(0).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(1)} -pin  "reg(g(0).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(2)} -pin  "reg(g(0).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(3)} -pin  "reg(g(0).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(4)} -pin  "reg(g(0).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(5)} -pin  "reg(g(0).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(6)} -pin  "reg(g(0).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(7)} -pin  "reg(g(0).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(8)} -pin  "reg(g(0).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(9)} -pin  "reg(g(0).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(10)} -pin  "reg(g(0).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(11)} -pin  "reg(g(0).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(12)} -pin  "reg(g(0).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(13)} -pin  "reg(g(0).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(14)} -pin  "reg(g(0).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(15)} -pin  "reg(g(0).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load inst "reg(r(2).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 5287 -attr oid 421 -attr vt d -attr @path {/sobel/sobel:core/reg(r(2).sva#1)}
+load net {r(2).sva#3(0)} -pin  "reg(r(2).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(1)} -pin  "reg(r(2).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(2)} -pin  "reg(r(2).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(3)} -pin  "reg(r(2).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(4)} -pin  "reg(r(2).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(5)} -pin  "reg(r(2).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(6)} -pin  "reg(r(2).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(7)} -pin  "reg(r(2).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(8)} -pin  "reg(r(2).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(9)} -pin  "reg(r(2).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(10)} -pin  "reg(r(2).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(11)} -pin  "reg(r(2).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(12)} -pin  "reg(r(2).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(13)} -pin  "reg(r(2).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(14)} -pin  "reg(r(2).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(15)} -pin  "reg(r(2).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(r(2).sva#1)" {clk} -attr xrf 5288 -attr oid 422 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(r(2).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(r(2).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {r(2).sva#1(0)} -pin  "reg(r(2).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(1)} -pin  "reg(r(2).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(2)} -pin  "reg(r(2).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(3)} -pin  "reg(r(2).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(4)} -pin  "reg(r(2).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(5)} -pin  "reg(r(2).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(6)} -pin  "reg(r(2).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(7)} -pin  "reg(r(2).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(8)} -pin  "reg(r(2).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(9)} -pin  "reg(r(2).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(10)} -pin  "reg(r(2).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(11)} -pin  "reg(r(2).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(12)} -pin  "reg(r(2).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(13)} -pin  "reg(r(2).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(14)} -pin  "reg(r(2).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(15)} -pin  "reg(r(2).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load inst "reg(r(0).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 5289 -attr oid 423 -attr vt d -attr @path {/sobel/sobel:core/reg(r(0).sva#1)}
+load net {r(0).sva#3(0)} -pin  "reg(r(0).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(1)} -pin  "reg(r(0).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(2)} -pin  "reg(r(0).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(3)} -pin  "reg(r(0).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(4)} -pin  "reg(r(0).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(5)} -pin  "reg(r(0).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(6)} -pin  "reg(r(0).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(7)} -pin  "reg(r(0).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(8)} -pin  "reg(r(0).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(9)} -pin  "reg(r(0).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(10)} -pin  "reg(r(0).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(11)} -pin  "reg(r(0).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(12)} -pin  "reg(r(0).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(13)} -pin  "reg(r(0).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(14)} -pin  "reg(r(0).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(15)} -pin  "reg(r(0).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(r(0).sva#1)" {clk} -attr xrf 5290 -attr oid 424 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(r(0).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(r(0).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {r(0).sva#1(0)} -pin  "reg(r(0).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(1)} -pin  "reg(r(0).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(2)} -pin  "reg(r(0).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(3)} -pin  "reg(r(0).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(4)} -pin  "reg(r(0).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(5)} -pin  "reg(r(0).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(6)} -pin  "reg(r(0).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(7)} -pin  "reg(r(0).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(8)} -pin  "reg(r(0).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(9)} -pin  "reg(r(0).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(10)} -pin  "reg(r(0).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(11)} -pin  "reg(r(0).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(12)} -pin  "reg(r(0).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(13)} -pin  "reg(r(0).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(14)} -pin  "reg(r(0).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(15)} -pin  "reg(r(0).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load inst "mux#5" "mux(2,19)" "INTERFACE" -attr xrf 5291 -attr oid 425 -attr vt d -attr @path {/sobel/sobel:core/mux#5} -attr area 17.470037 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2)"
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "mux#5" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "mux#5" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "mux#5" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "mux#5" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "mux#5" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "mux#5" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "mux#5" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "mux#5" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "mux#5" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "mux#5" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "mux#5" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "mux#5" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "mux#5" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "mux#5" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "mux#5" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "mux#5" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "mux#5" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "mux#5" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "mux#5" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.sva#1(0)} -pin  "mux#5" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "mux#5" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "mux#5" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "mux#5" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "mux#5" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "mux#5" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "mux#5" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "mux#5" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "mux#5" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "mux#5" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "mux#5" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "mux#5" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "mux#5" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "mux#5" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "mux#5" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "mux#5" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "mux#5" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "mux#5" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "mux#5" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:for:acc.itm(1)} -pin  "mux#5" {S(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#22.itm}
+load net {mux#5.itm(0)} -pin  "mux#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(1)} -pin  "mux#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(2)} -pin  "mux#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(3)} -pin  "mux#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(4)} -pin  "mux#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(5)} -pin  "mux#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(6)} -pin  "mux#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(7)} -pin  "mux#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(8)} -pin  "mux#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(9)} -pin  "mux#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(10)} -pin  "mux#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(11)} -pin  "mux#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(12)} -pin  "mux#5" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(13)} -pin  "mux#5" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(14)} -pin  "mux#5" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(15)} -pin  "mux#5" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(16)} -pin  "mux#5" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(17)} -pin  "mux#5" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(18)} -pin  "mux#5" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load inst "reg(FRAME:p#1.lpi#1)" "reg(19,1,1,-1,0)" "INTERFACE" -attr xrf 5292 -attr oid 426 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:p#1.lpi#1)}
+load net {mux#5.itm(0)} -pin  "reg(FRAME:p#1.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(1)} -pin  "reg(FRAME:p#1.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(2)} -pin  "reg(FRAME:p#1.lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(3)} -pin  "reg(FRAME:p#1.lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(4)} -pin  "reg(FRAME:p#1.lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(5)} -pin  "reg(FRAME:p#1.lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(6)} -pin  "reg(FRAME:p#1.lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(7)} -pin  "reg(FRAME:p#1.lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(8)} -pin  "reg(FRAME:p#1.lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(9)} -pin  "reg(FRAME:p#1.lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(10)} -pin  "reg(FRAME:p#1.lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(11)} -pin  "reg(FRAME:p#1.lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(12)} -pin  "reg(FRAME:p#1.lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(13)} -pin  "reg(FRAME:p#1.lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(14)} -pin  "reg(FRAME:p#1.lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(15)} -pin  "reg(FRAME:p#1.lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(16)} -pin  "reg(FRAME:p#1.lpi#1)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(17)} -pin  "reg(FRAME:p#1.lpi#1)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(18)} -pin  "reg(FRAME:p#1.lpi#1)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_19}
+load net {clk} -pin  "reg(FRAME:p#1.lpi#1)" {clk} -attr xrf 5293 -attr oid 427 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:p#1.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:p#1.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:p#1.lpi#1(0)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load inst "FRAME:acc#19" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 5294 -attr oid 428 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {FRAME:acc#18.itm#1(0)} -pin  "FRAME:acc#19" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(1)} -pin  "FRAME:acc#19" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(2)} -pin  "FRAME:acc#19" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(3)} -pin  "FRAME:acc#19" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(4)} -pin  "FRAME:acc#19" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:slc(acc.imod#2)#4.itm#1} -pin  "FRAME:acc#19" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {PWR} -pin  "FRAME:acc#19" {B(1)} -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {GND} -pin  "FRAME:acc#19" {B(2)} -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {GND} -pin  "FRAME:acc#19" {B(3)} -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {PWR} -pin  "FRAME:acc#19" {B(4)} -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#19" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#19" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#19" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(3)} -pin  "FRAME:acc#19" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(4)} -pin  "FRAME:acc#19" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load inst "FRAME:acc#20" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 5295 -attr oid 429 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {green:slc(green#2.sg1).itm#1(0)} -pin  "FRAME:acc#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(1)} -pin  "FRAME:acc#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(2)} -pin  "FRAME:acc#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(3)} -pin  "FRAME:acc#20" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(4)} -pin  "FRAME:acc#20" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(5)} -pin  "FRAME:acc#20" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#20" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#20" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#20" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(3)} -pin  "FRAME:acc#20" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(4)} -pin  "FRAME:acc#20" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#20.itm(0)} -pin  "FRAME:acc#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(1)} -pin  "FRAME:acc#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(2)} -pin  "FRAME:acc#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(3)} -pin  "FRAME:acc#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(4)} -pin  "FRAME:acc#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(5)} -pin  "FRAME:acc#20" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(6)} -pin  "FRAME:acc#20" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(7)} -pin  "FRAME:acc#20" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load inst "FRAME:acc#21" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 5296 -attr oid 430 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul#3.itm#1(0)} -pin  "FRAME:acc#21" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(1)} -pin  "FRAME:acc#21" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(2)} -pin  "FRAME:acc#21" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(3)} -pin  "FRAME:acc#21" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(4)} -pin  "FRAME:acc#21" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(5)} -pin  "FRAME:acc#21" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(6)} -pin  "FRAME:acc#21" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(7)} -pin  "FRAME:acc#21" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(8)} -pin  "FRAME:acc#21" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:acc#20.itm(0)} -pin  "FRAME:acc#21" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(1)} -pin  "FRAME:acc#21" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(2)} -pin  "FRAME:acc#21" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(3)} -pin  "FRAME:acc#21" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(4)} -pin  "FRAME:acc#21" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(5)} -pin  "FRAME:acc#21" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(6)} -pin  "FRAME:acc#21" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(7)} -pin  "FRAME:acc#21" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#21.itm(0)} -pin  "FRAME:acc#21" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(1)} -pin  "FRAME:acc#21" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(2)} -pin  "FRAME:acc#21" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(3)} -pin  "FRAME:acc#21" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(4)} -pin  "FRAME:acc#21" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(5)} -pin  "FRAME:acc#21" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(6)} -pin  "FRAME:acc#21" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(7)} -pin  "FRAME:acc#21" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(8)} -pin  "FRAME:acc#21" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(9)} -pin  "FRAME:acc#21" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load inst "FRAME:acc#22" "add(11,0,10,1,12)" "INTERFACE" -attr xrf 5297 -attr oid 431 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12)"
+load net {FRAME:mul#2.itm#1(0)} -pin  "FRAME:acc#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(1)} -pin  "FRAME:acc#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(2)} -pin  "FRAME:acc#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(3)} -pin  "FRAME:acc#22" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
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+load net {FRAME:acc#33.itm(6)} -pin  "FRAME:acc#33" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(7)} -pin  "FRAME:acc#33" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(8)} -pin  "FRAME:acc#33" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(9)} -pin  "FRAME:acc#33" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load inst "FRAME:acc#34" "add(11,0,10,1,12)" "INTERFACE" -attr xrf 5302 -attr oid 436 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12)"
+load net {FRAME:mul#4.itm#1(0)} -pin  "FRAME:acc#34" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(1)} -pin  "FRAME:acc#34" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(2)} -pin  "FRAME:acc#34" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(3)} -pin  "FRAME:acc#34" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(4)} -pin  "FRAME:acc#34" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(5)} -pin  "FRAME:acc#34" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(6)} -pin  "FRAME:acc#34" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(7)} -pin  "FRAME:acc#34" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(8)} -pin  "FRAME:acc#34" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(9)} -pin  "FRAME:acc#34" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(10)} -pin  "FRAME:acc#34" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:acc#33.itm(0)} -pin  "FRAME:acc#34" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(1)} -pin  "FRAME:acc#34" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(2)} -pin  "FRAME:acc#34" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(3)} -pin  "FRAME:acc#34" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(4)} -pin  "FRAME:acc#34" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(5)} -pin  "FRAME:acc#34" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(6)} -pin  "FRAME:acc#34" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(7)} -pin  "FRAME:acc#34" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(8)} -pin  "FRAME:acc#34" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(9)} -pin  "FRAME:acc#34" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#34.itm(0)} -pin  "FRAME:acc#34" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(1)} -pin  "FRAME:acc#34" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(2)} -pin  "FRAME:acc#34" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(3)} -pin  "FRAME:acc#34" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(4)} -pin  "FRAME:acc#34" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(5)} -pin  "FRAME:acc#34" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(6)} -pin  "FRAME:acc#34" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(7)} -pin  "FRAME:acc#34" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(8)} -pin  "FRAME:acc#34" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(9)} -pin  "FRAME:acc#34" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(10)} -pin  "FRAME:acc#34" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(11)} -pin  "FRAME:acc#34" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load inst "FRAME:acc#4" "add(12,-1,11,0,12)" "INTERFACE" -attr xrf 5303 -attr oid 437 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {FRAME:acc#34.itm(0)} -pin  "FRAME:acc#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(1)} -pin  "FRAME:acc#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(2)} -pin  "FRAME:acc#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(3)} -pin  "FRAME:acc#4" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(4)} -pin  "FRAME:acc#4" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(5)} -pin  "FRAME:acc#4" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(6)} -pin  "FRAME:acc#4" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(7)} -pin  "FRAME:acc#4" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(8)} -pin  "FRAME:acc#4" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(9)} -pin  "FRAME:acc#4" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(10)} -pin  "FRAME:acc#4" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(11)} -pin  "FRAME:acc#4" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(1)} -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(5)} -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(6)} -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(7)} -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {FRAME:acc#4.psp.sva(0)} -pin  "FRAME:acc#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(1)} -pin  "FRAME:acc#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(2)} -pin  "FRAME:acc#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(3)} -pin  "FRAME:acc#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(4)} -pin  "FRAME:acc#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(5)} -pin  "FRAME:acc#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(6)} -pin  "FRAME:acc#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(7)} -pin  "FRAME:acc#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(8)} -pin  "FRAME:acc#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(9)} -pin  "FRAME:acc#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(10)} -pin  "FRAME:acc#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(11)} -pin  "FRAME:acc#4" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load inst "FRAME:for:acc" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 5304 -attr oid 438 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2)"
+load net {i#6.sva#2(0)} -pin  "FRAME:for:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "FRAME:for:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {PWR} -pin  "FRAME:for:acc" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:for:acc.itm(0)} -pin  "FRAME:for:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+load inst "FRAME:for:acc#16" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 5305 -attr oid 439 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#16} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:for:acc#16" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {i#6.sva#2(0)} -pin  "FRAME:for:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "FRAME:for:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load inst "not#40" "not(1)" "INTERFACE" -attr xrf 5306 -attr oid 440 -attr @path {/sobel/sobel:core/not#40} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "not#40" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {not#40.itm} -pin  "not#40" {Z(0)} -attr @path {/sobel/sobel:core/not#40.itm}
+load inst "FRAME:for:and#1" "and(2,2)" "INTERFACE" -attr xrf 5307 -attr oid 441 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#1} -attr area 1.459665 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2)"
+load net {i#6.sva#1(0)} -pin  "FRAME:for:and#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "FRAME:for:and#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {not#40.itm} -pin  "FRAME:for:and#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#19.itm}
+load net {not#40.itm} -pin  "FRAME:for:and#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#19.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:and#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:and#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load inst "FRAME:for:or" "or(2,1)" "INTERFACE" -attr xrf 5308 -attr oid 442 -attr @path {/sobel/sobel:core/FRAME:for:or} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "FRAME:for:or" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {exit:FRAME#1.sva} -pin  "FRAME:for:or" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:or" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load inst "mux#1" "mux(2,90)" "INTERFACE" -attr xrf 5309 -attr oid 443 -attr vt dc -attr @path {/sobel/sobel:core/mux#1} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(2).lpi#1.dfm(0)} -pin  "mux#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(1)} -pin  "mux#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(2)} -pin  "mux#1" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(3)} -pin  "mux#1" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(4)} -pin  "mux#1" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(5)} -pin  "mux#1" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(6)} -pin  "mux#1" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(7)} -pin  "mux#1" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(8)} -pin  "mux#1" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(9)} -pin  "mux#1" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(10)} -pin  "mux#1" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(11)} -pin  "mux#1" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(12)} -pin  "mux#1" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(13)} -pin  "mux#1" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(14)} -pin  "mux#1" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(15)} -pin  "mux#1" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(16)} -pin  "mux#1" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(17)} -pin  "mux#1" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(18)} -pin  "mux#1" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(19)} -pin  "mux#1" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(20)} -pin  "mux#1" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(21)} -pin  "mux#1" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(22)} -pin  "mux#1" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(23)} -pin  "mux#1" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(24)} -pin  "mux#1" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(25)} -pin  "mux#1" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(26)} -pin  "mux#1" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(27)} -pin  "mux#1" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(28)} -pin  "mux#1" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(29)} -pin  "mux#1" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(30)} -pin  "mux#1" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(31)} -pin  "mux#1" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(32)} -pin  "mux#1" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(33)} -pin  "mux#1" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(34)} -pin  "mux#1" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(35)} -pin  "mux#1" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(36)} -pin  "mux#1" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(37)} -pin  "mux#1" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(38)} -pin  "mux#1" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(39)} -pin  "mux#1" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(40)} -pin  "mux#1" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(41)} -pin  "mux#1" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(42)} -pin  "mux#1" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(43)} -pin  "mux#1" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(44)} -pin  "mux#1" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(45)} -pin  "mux#1" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(46)} -pin  "mux#1" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(47)} -pin  "mux#1" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(48)} -pin  "mux#1" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(49)} -pin  "mux#1" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(50)} -pin  "mux#1" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(51)} -pin  "mux#1" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(52)} -pin  "mux#1" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(53)} -pin  "mux#1" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(54)} -pin  "mux#1" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(55)} -pin  "mux#1" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(56)} -pin  "mux#1" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(57)} -pin  "mux#1" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(58)} -pin  "mux#1" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(59)} -pin  "mux#1" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(60)} -pin  "mux#1" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(61)} -pin  "mux#1" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(62)} -pin  "mux#1" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(63)} -pin  "mux#1" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(64)} -pin  "mux#1" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(65)} -pin  "mux#1" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(66)} -pin  "mux#1" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(67)} -pin  "mux#1" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(68)} -pin  "mux#1" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(69)} -pin  "mux#1" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(70)} -pin  "mux#1" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(71)} -pin  "mux#1" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(72)} -pin  "mux#1" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(73)} -pin  "mux#1" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(74)} -pin  "mux#1" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(75)} -pin  "mux#1" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(76)} -pin  "mux#1" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(77)} -pin  "mux#1" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(78)} -pin  "mux#1" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(79)} -pin  "mux#1" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(80)} -pin  "mux#1" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(81)} -pin  "mux#1" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(82)} -pin  "mux#1" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(83)} -pin  "mux#1" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(84)} -pin  "mux#1" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(85)} -pin  "mux#1" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(86)} -pin  "mux#1" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(87)} -pin  "mux#1" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(88)} -pin  "mux#1" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(89)} -pin  "mux#1" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(1).sva(0)} -pin  "mux#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "mux#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "mux#1" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "mux#1" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "mux#1" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "mux#1" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "mux#1" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "mux#1" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "mux#1" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "mux#1" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "mux#1" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "mux#1" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "mux#1" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "mux#1" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "mux#1" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "mux#1" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "mux#1" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "mux#1" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "mux#1" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "mux#1" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "mux#1" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "mux#1" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "mux#1" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "mux#1" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "mux#1" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "mux#1" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "mux#1" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "mux#1" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "mux#1" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "mux#1" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "mux#1" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "mux#1" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "mux#1" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "mux#1" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "mux#1" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "mux#1" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "mux#1" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "mux#1" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "mux#1" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "mux#1" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "mux#1" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "mux#1" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "mux#1" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "mux#1" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "mux#1" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "mux#1" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "mux#1" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "mux#1" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "mux#1" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "mux#1" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "mux#1" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "mux#1" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "mux#1" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "mux#1" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "mux#1" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "mux#1" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "mux#1" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "mux#1" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "mux#1" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "mux#1" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "mux#1" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "mux#1" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "mux#1" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "mux#1" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "mux#1" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "mux#1" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "mux#1" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "mux#1" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "mux#1" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "mux#1" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "mux#1" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "mux#1" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "mux#1" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "mux#1" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "mux#1" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "mux#1" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "mux#1" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "mux#1" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "mux#1" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "mux#1" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "mux#1" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "mux#1" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "mux#1" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "mux#1" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "mux#1" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "mux#1" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "mux#1" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "mux#1" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "mux#1" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "mux#1" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {and.dcpl} -pin  "mux#1" {S(0)} -attr vt c -attr @path {/sobel/sobel:core/and.dcpl}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "mux#1" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "mux#1" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "mux#1" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "mux#1" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "mux#1" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "mux#1" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "mux#1" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "mux#1" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "mux#1" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "mux#1" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "mux#1" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "mux#1" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "mux#1" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "mux#1" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "mux#1" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "mux#1" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "mux#1" {Z(16)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "mux#1" {Z(17)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "mux#1" {Z(18)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "mux#1" {Z(19)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "mux#1" {Z(20)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "mux#1" {Z(21)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "mux#1" {Z(22)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "mux#1" {Z(23)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "mux#1" {Z(24)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "mux#1" {Z(25)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "mux#1" {Z(26)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "mux#1" {Z(27)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "mux#1" {Z(28)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "mux#1" {Z(29)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "mux#1" {Z(30)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "mux#1" {Z(31)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "mux#1" {Z(32)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "mux#1" {Z(33)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "mux#1" {Z(34)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "mux#1" {Z(35)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "mux#1" {Z(36)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "mux#1" {Z(37)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "mux#1" {Z(38)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "mux#1" {Z(39)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "mux#1" {Z(40)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "mux#1" {Z(41)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "mux#1" {Z(42)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "mux#1" {Z(43)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "mux#1" {Z(44)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "mux#1" {Z(45)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "mux#1" {Z(46)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "mux#1" {Z(47)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "mux#1" {Z(48)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "mux#1" {Z(49)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "mux#1" {Z(50)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "mux#1" {Z(51)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "mux#1" {Z(52)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "mux#1" {Z(53)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "mux#1" {Z(54)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "mux#1" {Z(55)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "mux#1" {Z(56)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "mux#1" {Z(57)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "mux#1" {Z(58)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "mux#1" {Z(59)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "mux#1" {Z(60)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "mux#1" {Z(61)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "mux#1" {Z(62)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "mux#1" {Z(63)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "mux#1" {Z(64)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "mux#1" {Z(65)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "mux#1" {Z(66)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "mux#1" {Z(67)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "mux#1" {Z(68)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "mux#1" {Z(69)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "mux#1" {Z(70)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "mux#1" {Z(71)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "mux#1" {Z(72)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "mux#1" {Z(73)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "mux#1" {Z(74)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "mux#1" {Z(75)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "mux#1" {Z(76)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "mux#1" {Z(77)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "mux#1" {Z(78)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "mux#1" {Z(79)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "mux#1" {Z(80)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "mux#1" {Z(81)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "mux#1" {Z(82)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "mux#1" {Z(83)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "mux#1" {Z(84)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "mux#1" {Z(85)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "mux#1" {Z(86)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "mux#1" {Z(87)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "mux#1" {Z(88)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "mux#1" {Z(89)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load inst "mux#2" "mux(2,90)" "INTERFACE" -attr xrf 5310 -attr oid 444 -attr vt d -attr @path {/sobel/sobel:core/mux#2} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(1).sva(0)} -pin  "mux#2" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "mux#2" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "mux#2" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "mux#2" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "mux#2" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "mux#2" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "mux#2" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "mux#2" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "mux#2" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "mux#2" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "mux#2" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "mux#2" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "mux#2" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "mux#2" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "mux#2" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "mux#2" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "mux#2" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "mux#2" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "mux#2" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "mux#2" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "mux#2" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "mux#2" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "mux#2" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "mux#2" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "mux#2" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "mux#2" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "mux#2" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "mux#2" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "mux#2" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "mux#2" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "mux#2" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "mux#2" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "mux#2" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "mux#2" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "mux#2" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "mux#2" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "mux#2" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "mux#2" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "mux#2" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "mux#2" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "mux#2" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "mux#2" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "mux#2" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "mux#2" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "mux#2" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "mux#2" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "mux#2" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "mux#2" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "mux#2" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "mux#2" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "mux#2" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "mux#2" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "mux#2" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "mux#2" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "mux#2" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "mux#2" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "mux#2" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "mux#2" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "mux#2" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "mux#2" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "mux#2" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "mux#2" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "mux#2" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "mux#2" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "mux#2" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "mux#2" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "mux#2" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "mux#2" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "mux#2" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "mux#2" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "mux#2" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "mux#2" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "mux#2" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "mux#2" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "mux#2" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "mux#2" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "mux#2" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "mux#2" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "mux#2" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "mux#2" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "mux#2" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "mux#2" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "mux#2" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "mux#2" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "mux#2" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "mux#2" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "mux#2" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "mux#2" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "mux#2" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "mux#2" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -pin  "mux#2" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#2" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#2" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#2" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#2" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#2" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#2" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#2" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#2" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#2" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#2" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#2" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#2" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#2" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#2" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#2" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#2" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#2" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#2" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#2" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#2" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#2" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#2" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#2" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#2" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#2" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#2" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#2" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#2" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#2" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#2" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#2" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#2" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#2" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#2" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#2" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#2" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#2" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#2" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#2" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#2" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#2" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#2" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#2" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#2" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#2" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#2" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#2" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#2" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#2" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#2" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#2" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#2" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#2" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#2" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#2" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#2" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#2" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#2" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#2" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#2" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#2" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#2" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#2" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#2" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#2" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#2" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#2" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#2" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#2" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#2" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#2" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#2" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#2" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#2" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#2" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#2" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#2" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#2" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#2" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#2" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#2" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#2" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#2" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#2" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#2" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#2" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#2" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#2" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#2" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {and.dcpl} -pin  "mux#2" {S(0)} -attr @path {/sobel/sobel:core/and.dcpl}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "mux#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "mux#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "mux#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "mux#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "mux#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "mux#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "mux#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "mux#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "mux#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "mux#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "mux#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "mux#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "mux#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "mux#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "mux#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "mux#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "mux#2" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "mux#2" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "mux#2" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "mux#2" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "mux#2" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "mux#2" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "mux#2" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "mux#2" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "mux#2" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "mux#2" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "mux#2" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "mux#2" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "mux#2" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "mux#2" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "mux#2" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "mux#2" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "mux#2" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "mux#2" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "mux#2" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "mux#2" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "mux#2" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "mux#2" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "mux#2" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "mux#2" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "mux#2" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "mux#2" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "mux#2" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "mux#2" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "mux#2" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "mux#2" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "mux#2" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "mux#2" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "mux#2" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "mux#2" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "mux#2" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "mux#2" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "mux#2" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "mux#2" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "mux#2" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "mux#2" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "mux#2" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "mux#2" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "mux#2" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "mux#2" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "mux#2" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "mux#2" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "mux#2" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "mux#2" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "mux#2" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "mux#2" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "mux#2" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "mux#2" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "mux#2" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "mux#2" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "mux#2" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "mux#2" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "mux#2" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "mux#2" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "mux#2" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "mux#2" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "mux#2" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "mux#2" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "mux#2" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "mux#2" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "mux#2" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "mux#2" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "mux#2" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "mux#2" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "mux#2" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "mux#2" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "mux#2" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "mux#2" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "mux#2" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "mux#2" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load inst "mux#3" "mux(2,90)" "INTERFACE" -attr xrf 5311 -attr oid 445 -attr vt d -attr @path {/sobel/sobel:core/mux#3} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(0).sva(0)} -pin  "mux#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#3" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#3" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#3" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#3" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#3" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#3" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#3" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#3" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#3" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#3" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#3" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#3" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#3" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#3" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#3" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#3" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#3" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#3" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#3" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#3" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#3" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#3" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#3" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#3" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#3" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#3" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#3" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#3" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#3" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#3" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#3" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#3" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#3" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#3" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#3" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#3" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#3" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#3" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#3" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#3" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#3" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#3" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#3" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#3" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#3" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#3" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#3" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#3" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#3" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#3" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#3" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#3" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#3" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#3" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#3" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#3" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#3" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#3" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#3" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#3" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#3" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#3" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#3" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#3" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#3" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#3" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#3" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#3" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#3" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#3" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#3" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#3" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#3" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#3" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#3" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#3" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#3" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#3" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#3" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#3" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#3" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#3" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#3" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#3" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#3" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "mux#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "mux#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "mux#3" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "mux#3" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "mux#3" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "mux#3" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "mux#3" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "mux#3" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "mux#3" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "mux#3" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "mux#3" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "mux#3" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "mux#3" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "mux#3" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "mux#3" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "mux#3" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "mux#3" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "mux#3" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "mux#3" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "mux#3" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "mux#3" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "mux#3" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "mux#3" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "mux#3" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "mux#3" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "mux#3" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "mux#3" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "mux#3" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "mux#3" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "mux#3" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "mux#3" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "mux#3" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "mux#3" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "mux#3" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "mux#3" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "mux#3" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "mux#3" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "mux#3" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "mux#3" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "mux#3" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "mux#3" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "mux#3" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "mux#3" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "mux#3" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "mux#3" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "mux#3" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "mux#3" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "mux#3" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "mux#3" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "mux#3" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "mux#3" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "mux#3" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "mux#3" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "mux#3" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "mux#3" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "mux#3" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "mux#3" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "mux#3" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "mux#3" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "mux#3" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "mux#3" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "mux#3" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "mux#3" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "mux#3" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "mux#3" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "mux#3" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "mux#3" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "mux#3" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "mux#3" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "mux#3" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "mux#3" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "mux#3" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "mux#3" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "mux#3" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "mux#3" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "mux#3" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "mux#3" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "mux#3" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "mux#3" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "mux#3" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "mux#3" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "mux#3" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "mux#3" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "mux#3" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "mux#3" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "mux#3" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "mux#3" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "mux#3" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "mux#3" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "mux#3" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {and.dcpl} -pin  "mux#3" {S(0)} -attr @path {/sobel/sobel:core/and.dcpl}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "mux#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "mux#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "mux#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "mux#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "mux#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "mux#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "mux#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "mux#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "mux#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "mux#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "mux#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "mux#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "mux#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "mux#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "mux#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "mux#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "mux#3" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "mux#3" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "mux#3" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "mux#3" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "mux#3" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "mux#3" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "mux#3" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "mux#3" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "mux#3" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "mux#3" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "mux#3" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "mux#3" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "mux#3" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "mux#3" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "mux#3" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "mux#3" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "mux#3" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "mux#3" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "mux#3" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "mux#3" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "mux#3" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "mux#3" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "mux#3" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "mux#3" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "mux#3" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "mux#3" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "mux#3" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "mux#3" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "mux#3" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "mux#3" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "mux#3" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "mux#3" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "mux#3" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "mux#3" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "mux#3" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "mux#3" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "mux#3" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "mux#3" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "mux#3" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "mux#3" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "mux#3" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "mux#3" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "mux#3" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "mux#3" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "mux#3" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "mux#3" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "mux#3" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "mux#3" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "mux#3" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "mux#3" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "mux#3" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "mux#3" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "mux#3" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "mux#3" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "mux#3" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "mux#3" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "mux#3" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "mux#3" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "mux#3" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "mux#3" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "mux#3" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "mux#3" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "mux#3" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "mux#3" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "mux#3" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "mux#3" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "mux#3" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "mux#3" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "mux#3" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "mux#3" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "mux#3" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "mux#3" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "mux#3" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "mux#3" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load inst "not#16" "not(1)" "INTERFACE" -attr xrf 5312 -attr oid 446 -attr @path {/sobel/sobel:core/not#16} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "not#16" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {not#16.itm} -pin  "not#16" {Z(0)} -attr @path {/sobel/sobel:core/not#16.itm}
+load inst "FRAME:for:and#2" "and(2,1)" "INTERFACE" -attr xrf 5313 -attr oid 447 -attr @path {/sobel/sobel:core/FRAME:for:and#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {exit:FRAME.lpi#1.dfm#1} -pin  "FRAME:for:and#2" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1}
+load net {not#16.itm} -pin  "FRAME:for:and#2" {A1(0)} -attr @path {/sobel/sobel:core/not#16.itm}
+load net {FRAME:for:and#2.itm} -pin  "FRAME:for:and#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#2.itm}
+load inst "FRAME:acc" "add(7,0,8,-1,8)" "INTERFACE" -attr xrf 5314 -attr oid 448 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc} -attr area 9.262368 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,7,0,8)"
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {PWR} -pin  "FRAME:acc" {B(0)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(1)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(2)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(3)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(4)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(5)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(6)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(7)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {FRAME:acc.itm(0)} -pin  "FRAME:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(1)} -pin  "FRAME:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(2)} -pin  "FRAME:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(3)} -pin  "FRAME:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(4)} -pin  "FRAME:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(5)} -pin  "FRAME:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(6)} -pin  "FRAME:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(7)} -pin  "FRAME:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load inst "FRAME:not" "not(1)" "INTERFACE" -attr xrf 5315 -attr oid 449 -attr @path {/sobel/sobel:core/FRAME:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc.itm(7)} -pin  "FRAME:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc.itm}
+load net {FRAME:not.itm} -pin  "FRAME:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load inst "mux#4" "mux(2,1)" "INTERFACE" -attr xrf 5316 -attr oid 450 -attr @path {/sobel/sobel:core/mux#4} -attr area 0.920423 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2)"
+load net {FRAME:for:and#2.itm} -pin  "mux#4" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#2.itm}
+load net {FRAME:not.itm} -pin  "mux#4" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "mux#4" {S(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc.itm}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "mux#4" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load inst "FRAME:acc#6" "add(19,-1,1,0,19)" "INTERFACE" -attr xrf 5317 -attr oid 451 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6} -attr area 20.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19)"
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "FRAME:acc#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "FRAME:acc#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "FRAME:acc#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "FRAME:acc#6" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "FRAME:acc#6" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "FRAME:acc#6" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "FRAME:acc#6" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "FRAME:acc#6" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "FRAME:acc#6" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "FRAME:acc#6" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "FRAME:acc#6" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "FRAME:acc#6" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "FRAME:acc#6" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "FRAME:acc#6" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "FRAME:acc#6" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "FRAME:acc#6" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "FRAME:acc#6" {A(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "FRAME:acc#6" {A(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "FRAME:acc#6" {A(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:acc#6" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:p#1.sva#1(0)} -pin  "FRAME:acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "FRAME:acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "FRAME:acc#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "FRAME:acc#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "FRAME:acc#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "FRAME:acc#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "FRAME:acc#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "FRAME:acc#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "FRAME:acc#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "FRAME:acc#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "FRAME:acc#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "FRAME:acc#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc#6" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc#6" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc#6" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc#6" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc#6" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc#6" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc#6" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load inst "FRAME:not#28" "not(1)" "INTERFACE" -attr xrf 5318 -attr oid 452 -attr @path {/sobel/sobel:core/FRAME:not#28} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME#1.sva} -pin  "FRAME:not#28" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {FRAME:not#28.itm} -pin  "FRAME:not#28" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#28.itm}
+load inst "FRAME:for:and" "and(2,19)" "INTERFACE" -attr xrf 5319 -attr oid 453 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and} -attr area 13.866816 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2)"
+load net {FRAME:p#1.lpi#1(0)} -pin  "FRAME:for:and" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "FRAME:for:and" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "FRAME:for:and" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "FRAME:for:and" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "FRAME:for:and" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "FRAME:for:and" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "FRAME:for:and" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "FRAME:for:and" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "FRAME:for:and" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "FRAME:for:and" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "FRAME:for:and" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "FRAME:for:and" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "FRAME:for:and" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "FRAME:for:and" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "FRAME:for:and" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "FRAME:for:and" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "FRAME:for:and" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "FRAME:for:and" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "FRAME:for:and" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "FRAME:for:and" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "FRAME:for:and" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "FRAME:for:and" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "FRAME:for:and" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "FRAME:for:and" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "FRAME:for:and" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "FRAME:for:and" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "FRAME:for:and" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "FRAME:for:and" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "FRAME:for:and" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "FRAME:for:and" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "FRAME:for:and" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "FRAME:for:and" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "FRAME:for:and" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "FRAME:for:and" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "FRAME:for:and" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "FRAME:for:and" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "FRAME:for:and" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "FRAME:for:and" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load inst "FRAME:not#2" "not(3)" "INTERFACE" -attr xrf 5320 -attr oid 454 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#43.itm(10)} -pin  "FRAME:not#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#2.itm}
+load net {ACC1:acc#43.itm(11)} -pin  "FRAME:not#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#2.itm}
+load net {ACC1:acc#43.itm(12)} -pin  "FRAME:not#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#2.itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:not#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:not#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:not#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load inst "FRAME:acc#8" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 5321 -attr oid 455 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#43.itm(7)} -pin  "FRAME:acc#8" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva).itm}
+load net {ACC1:acc#43.itm(8)} -pin  "FRAME:acc#8" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva).itm}
+load net {ACC1:acc#43.itm(9)} -pin  "FRAME:acc#8" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva).itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:acc#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:acc#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:acc#8" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#8" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#8" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#8" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#8" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load inst "FRAME:not#35" "not(1)" "INTERFACE" -attr xrf 5322 -attr oid 456 -attr @path {/sobel/sobel:core/FRAME:not#35} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:not#35" {A(0)} -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#20.itm}
+load net {FRAME:not#35.itm} -pin  "FRAME:not#35" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#35.itm}
+load inst "FRAME:not#45" "not(1)" "INTERFACE" -attr xrf 5323 -attr oid 457 -attr @path {/sobel/sobel:core/FRAME:not#45} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:not#45" {A(0)} -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#10.itm}
+load net {FRAME:not#45.itm} -pin  "FRAME:not#45" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#45.itm}
+load inst "FRAME:acc#7" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 5324 -attr oid 458 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#45.itm} -pin  "FRAME:acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {PWR} -pin  "FRAME:acc#7" {A(1)} -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {FRAME:not#35.itm} -pin  "FRAME:acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {ACC1:acc#43.itm(13)} -pin  "FRAME:acc#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#5.itm}
+load net {ACC1:acc#43.itm(14)} -pin  "FRAME:acc#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#5.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load inst "FRAME:acc#10" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 5325 -attr oid 459 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#10" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#10" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#10" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#10" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#10" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#10" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#10" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#10" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#10" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#10" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(4)} -pin  "FRAME:acc#10" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load inst "FRAME:not#1" "not(3)" "INTERFACE" -attr xrf 5326 -attr oid 460 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#43.itm(4)} -pin  "FRAME:not#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {ACC1:acc#43.itm(5)} -pin  "FRAME:not#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {ACC1:acc#43.itm(6)} -pin  "FRAME:not#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:not#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:not#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:not#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load inst "FRAME:acc#9" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 5327 -attr oid 461 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#43.itm(1)} -pin  "FRAME:acc#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {ACC1:acc#43.itm(2)} -pin  "FRAME:acc#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {ACC1:acc#43.itm(3)} -pin  "FRAME:acc#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:acc#9" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:acc#9" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:acc#9" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load inst "FRAME:acc#11" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 5328 -attr oid 462 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11} -attr area 6.288444 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6)"
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#11" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#11" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#11" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#11" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(4)} -pin  "FRAME:acc#11" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#11" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#11" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#11" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#11" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#11" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#11" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#11" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#11" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "FRAME:acc#11" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(5)} -pin  "FRAME:acc#11" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load inst "acc" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 5329 -attr oid 463 -attr vt dc -attr @path {/sobel/sobel:core/acc} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {FRAME:acc#11.itm(0)} -pin  "acc" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "acc" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "acc" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "acc" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "acc" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(5)} -pin  "acc" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {PWR} -pin  "acc" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod.sva(0)} -pin  "acc" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(1)} -pin  "acc" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(2)} -pin  "acc" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(3)} -pin  "acc" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(4)} -pin  "acc" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(5)} -pin  "acc" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load inst "ACC2:not" "not(10)" "INTERFACE" -attr xrf 5330 -attr oid 464 -attr vt d -attr @path {/sobel/sobel:core/ACC2:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "ACC2:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "ACC2:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "ACC2:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "ACC2:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "ACC2:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "ACC2:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "ACC2:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "ACC2:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "ACC2:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "ACC2:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {ACC2:not.itm(0)} -pin  "ACC2:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(1)} -pin  "ACC2:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(2)} -pin  "ACC2:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(3)} -pin  "ACC2:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(4)} -pin  "ACC2:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(5)} -pin  "ACC2:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(6)} -pin  "ACC2:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(7)} -pin  "ACC2:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(8)} -pin  "ACC2:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(9)} -pin  "ACC2:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load inst "acc#5" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 5331 -attr oid 465 -attr vt d -attr @path {/sobel/sobel:core/acc#5} -attr area 12.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "acc#5" {A(0)} -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(0)} -pin  "acc#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(1)} -pin  "acc#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(2)} -pin  "acc#5" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(3)} -pin  "acc#5" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(4)} -pin  "acc#5" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(5)} -pin  "acc#5" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(6)} -pin  "acc#5" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(7)} -pin  "acc#5" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(8)} -pin  "acc#5" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(9)} -pin  "acc#5" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {PWR} -pin  "acc#5" {B(0)} -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "acc#5" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "acc#5" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "acc#5" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "acc#5" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "acc#5" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "acc#5" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "acc#5" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "acc#5" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "acc#5" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "acc#5" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {acc#5.itm(0)} -pin  "acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(1)} -pin  "acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(2)} -pin  "acc#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(3)} -pin  "acc#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(4)} -pin  "acc#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(5)} -pin  "acc#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(6)} -pin  "acc#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(7)} -pin  "acc#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(8)} -pin  "acc#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(9)} -pin  "acc#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(10)} -pin  "acc#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(11)} -pin  "acc#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load inst "ACC1:acc#62" "add(11,1,15,-1,15)" "INTERFACE" -attr xrf 5332 -attr oid 466 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62} -attr area 16.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {acc#5.itm(1)} -pin  "ACC1:acc#62" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(2)} -pin  "ACC1:acc#62" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(3)} -pin  "ACC1:acc#62" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(4)} -pin  "ACC1:acc#62" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(5)} -pin  "ACC1:acc#62" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(6)} -pin  "ACC1:acc#62" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(7)} -pin  "ACC1:acc#62" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(8)} -pin  "ACC1:acc#62" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(9)} -pin  "ACC1:acc#62" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(10)} -pin  "ACC1:acc#62" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(11)} -pin  "ACC1:acc#62" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {r(2).sva#3(1)} -pin  "ACC1:acc#62" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(2)} -pin  "ACC1:acc#62" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(3)} -pin  "ACC1:acc#62" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(4)} -pin  "ACC1:acc#62" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(5)} -pin  "ACC1:acc#62" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(6)} -pin  "ACC1:acc#62" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(7)} -pin  "ACC1:acc#62" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(8)} -pin  "ACC1:acc#62" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(9)} -pin  "ACC1:acc#62" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(10)} -pin  "ACC1:acc#62" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(11)} -pin  "ACC1:acc#62" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(12)} -pin  "ACC1:acc#62" {B(11)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(13)} -pin  "ACC1:acc#62" {B(12)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(14)} -pin  "ACC1:acc#62" {B(13)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(15)} -pin  "ACC1:acc#62" {B(14)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {ACC1:acc#62.itm(0)} -pin  "ACC1:acc#62" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(1)} -pin  "ACC1:acc#62" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(2)} -pin  "ACC1:acc#62" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(3)} -pin  "ACC1:acc#62" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(4)} -pin  "ACC1:acc#62" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(5)} -pin  "ACC1:acc#62" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(6)} -pin  "ACC1:acc#62" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(7)} -pin  "ACC1:acc#62" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(8)} -pin  "ACC1:acc#62" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(9)} -pin  "ACC1:acc#62" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(10)} -pin  "ACC1:acc#62" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(11)} -pin  "ACC1:acc#62" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(12)} -pin  "ACC1:acc#62" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(13)} -pin  "ACC1:acc#62" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(14)} -pin  "ACC1:acc#62" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load inst "ACC1:acc#61" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 5333 -attr oid 467 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#61} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {PWR} -pin  "ACC1:acc#61" {A(0)} -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {r(2).sva#3(0)} -pin  "ACC1:acc#61" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {PWR} -pin  "ACC1:acc#61" {B(0)} -attr @path {/sobel/sobel:core/Cn1_1#3}
+load net {ACC1:acc#61.itm(0)} -pin  "ACC1:acc#61" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#61.itm}
+load net {ACC1:acc#61.itm(1)} -pin  "ACC1:acc#61" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#61.itm}
+load inst "ACC1:acc#43" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 5334 -attr oid 468 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {ACC1:acc#61.itm(1)} -pin  "ACC1:acc#43" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(0)} -pin  "ACC1:acc#43" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(1)} -pin  "ACC1:acc#43" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(2)} -pin  "ACC1:acc#43" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(3)} -pin  "ACC1:acc#43" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(4)} -pin  "ACC1:acc#43" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(5)} -pin  "ACC1:acc#43" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(6)} -pin  "ACC1:acc#43" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(7)} -pin  "ACC1:acc#43" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(8)} -pin  "ACC1:acc#43" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(9)} -pin  "ACC1:acc#43" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(10)} -pin  "ACC1:acc#43" {A(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(11)} -pin  "ACC1:acc#43" {A(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(12)} -pin  "ACC1:acc#43" {A(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(13)} -pin  "ACC1:acc#43" {A(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(14)} -pin  "ACC1:acc#43" {A(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {r(0).sva#3(0)} -pin  "ACC1:acc#43" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(1)} -pin  "ACC1:acc#43" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(2)} -pin  "ACC1:acc#43" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(3)} -pin  "ACC1:acc#43" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(4)} -pin  "ACC1:acc#43" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(5)} -pin  "ACC1:acc#43" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(6)} -pin  "ACC1:acc#43" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(7)} -pin  "ACC1:acc#43" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(8)} -pin  "ACC1:acc#43" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(9)} -pin  "ACC1:acc#43" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(10)} -pin  "ACC1:acc#43" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(11)} -pin  "ACC1:acc#43" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(12)} -pin  "ACC1:acc#43" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(13)} -pin  "ACC1:acc#43" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(14)} -pin  "ACC1:acc#43" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(15)} -pin  "ACC1:acc#43" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {ACC1:acc#43.itm(0)} -pin  "ACC1:acc#43" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(1)} -pin  "ACC1:acc#43" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(2)} -pin  "ACC1:acc#43" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(3)} -pin  "ACC1:acc#43" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(4)} -pin  "ACC1:acc#43" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(5)} -pin  "ACC1:acc#43" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(6)} -pin  "ACC1:acc#43" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(7)} -pin  "ACC1:acc#43" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(8)} -pin  "ACC1:acc#43" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(9)} -pin  "ACC1:acc#43" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(10)} -pin  "ACC1:acc#43" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(11)} -pin  "ACC1:acc#43" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(12)} -pin  "ACC1:acc#43" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(13)} -pin  "ACC1:acc#43" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(14)} -pin  "ACC1:acc#43" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(15)} -pin  "ACC1:acc#43" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load inst "FRAME:mul" "mul(2,0,9,0,10)" "INTERFACE" -attr xrf 5335 -attr oid 469 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC1:acc#43.itm(13)} -pin  "FRAME:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#12.itm}
+load net {ACC1:acc#43.itm(14)} -pin  "FRAME:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#12.itm}
+load net {PWR} -pin  "FRAME:mul" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul.sdt(0)} -pin  "FRAME:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(1)} -pin  "FRAME:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(2)} -pin  "FRAME:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(3)} -pin  "FRAME:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(4)} -pin  "FRAME:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(5)} -pin  "FRAME:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(6)} -pin  "FRAME:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(7)} -pin  "FRAME:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(8)} -pin  "FRAME:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(9)} -pin  "FRAME:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load inst "ACC2:not#4" "not(10)" "INTERFACE" -attr xrf 5336 -attr oid 470 -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "ACC2:not#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "ACC2:not#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "ACC2:not#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "ACC2:not#4" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "ACC2:not#4" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "ACC2:not#4" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "ACC2:not#4" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "ACC2:not#4" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "ACC2:not#4" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "ACC2:not#4" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {ACC2:not#4.itm(0)} -pin  "ACC2:not#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(1)} -pin  "ACC2:not#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(2)} -pin  "ACC2:not#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(3)} -pin  "ACC2:not#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(4)} -pin  "ACC2:not#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(5)} -pin  "ACC2:not#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(6)} -pin  "ACC2:not#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(7)} -pin  "ACC2:not#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(8)} -pin  "ACC2:not#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(9)} -pin  "ACC2:not#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load inst "acc#6" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 5337 -attr oid 471 -attr vt d -attr @path {/sobel/sobel:core/acc#6} -attr area 12.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "acc#6" {A(0)} -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(0)} -pin  "acc#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(1)} -pin  "acc#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(2)} -pin  "acc#6" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(3)} -pin  "acc#6" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(4)} -pin  "acc#6" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(5)} -pin  "acc#6" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(6)} -pin  "acc#6" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(7)} -pin  "acc#6" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(8)} -pin  "acc#6" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(9)} -pin  "acc#6" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {PWR} -pin  "acc#6" {B(0)} -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "acc#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "acc#6" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "acc#6" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "acc#6" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "acc#6" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "acc#6" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "acc#6" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "acc#6" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "acc#6" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "acc#6" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {acc#6.itm(0)} -pin  "acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(1)} -pin  "acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(2)} -pin  "acc#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(3)} -pin  "acc#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(4)} -pin  "acc#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(5)} -pin  "acc#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(6)} -pin  "acc#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(7)} -pin  "acc#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(8)} -pin  "acc#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(9)} -pin  "acc#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(10)} -pin  "acc#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(11)} -pin  "acc#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load inst "ACC1:acc#70" "add(11,1,15,-1,15)" "INTERFACE" -attr xrf 5338 -attr oid 472 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70} -attr area 16.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {acc#6.itm(1)} -pin  "ACC1:acc#70" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(2)} -pin  "ACC1:acc#70" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(3)} -pin  "ACC1:acc#70" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(4)} -pin  "ACC1:acc#70" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(5)} -pin  "ACC1:acc#70" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(6)} -pin  "ACC1:acc#70" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(7)} -pin  "ACC1:acc#70" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(8)} -pin  "ACC1:acc#70" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(9)} -pin  "ACC1:acc#70" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(10)} -pin  "ACC1:acc#70" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(11)} -pin  "ACC1:acc#70" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {b(2).sva#3(1)} -pin  "ACC1:acc#70" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(2)} -pin  "ACC1:acc#70" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(3)} -pin  "ACC1:acc#70" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(4)} -pin  "ACC1:acc#70" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(5)} -pin  "ACC1:acc#70" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(6)} -pin  "ACC1:acc#70" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(7)} -pin  "ACC1:acc#70" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(8)} -pin  "ACC1:acc#70" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(9)} -pin  "ACC1:acc#70" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(10)} -pin  "ACC1:acc#70" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(11)} -pin  "ACC1:acc#70" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(12)} -pin  "ACC1:acc#70" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(13)} -pin  "ACC1:acc#70" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(14)} -pin  "ACC1:acc#70" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(15)} -pin  "ACC1:acc#70" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {ACC1:acc#70.itm(0)} -pin  "ACC1:acc#70" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(1)} -pin  "ACC1:acc#70" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(2)} -pin  "ACC1:acc#70" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(3)} -pin  "ACC1:acc#70" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(4)} -pin  "ACC1:acc#70" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(5)} -pin  "ACC1:acc#70" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(6)} -pin  "ACC1:acc#70" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(7)} -pin  "ACC1:acc#70" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(8)} -pin  "ACC1:acc#70" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(9)} -pin  "ACC1:acc#70" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(10)} -pin  "ACC1:acc#70" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(11)} -pin  "ACC1:acc#70" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(12)} -pin  "ACC1:acc#70" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(13)} -pin  "ACC1:acc#70" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(14)} -pin  "ACC1:acc#70" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load inst "ACC1:acc#69" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 5339 -attr oid 473 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#69} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {PWR} -pin  "ACC1:acc#69" {A(0)} -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {b(2).sva#3(0)} -pin  "ACC1:acc#69" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {PWR} -pin  "ACC1:acc#69" {B(0)} -attr @path {/sobel/sobel:core/Cn1_1#3}
+load net {ACC1:acc#69.itm(0)} -pin  "ACC1:acc#69" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#69.itm}
+load net {ACC1:acc#69.itm(1)} -pin  "ACC1:acc#69" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#69.itm}
+load inst "ACC1:acc#45" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 5340 -attr oid 474 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {ACC1:acc#69.itm(1)} -pin  "ACC1:acc#45" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(0)} -pin  "ACC1:acc#45" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(1)} -pin  "ACC1:acc#45" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(2)} -pin  "ACC1:acc#45" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(3)} -pin  "ACC1:acc#45" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(4)} -pin  "ACC1:acc#45" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(5)} -pin  "ACC1:acc#45" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(6)} -pin  "ACC1:acc#45" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(7)} -pin  "ACC1:acc#45" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(8)} -pin  "ACC1:acc#45" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(9)} -pin  "ACC1:acc#45" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(10)} -pin  "ACC1:acc#45" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(11)} -pin  "ACC1:acc#45" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(12)} -pin  "ACC1:acc#45" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(13)} -pin  "ACC1:acc#45" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(14)} -pin  "ACC1:acc#45" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {b(0).sva#3(0)} -pin  "ACC1:acc#45" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(1)} -pin  "ACC1:acc#45" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(2)} -pin  "ACC1:acc#45" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(3)} -pin  "ACC1:acc#45" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(4)} -pin  "ACC1:acc#45" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(5)} -pin  "ACC1:acc#45" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(6)} -pin  "ACC1:acc#45" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(7)} -pin  "ACC1:acc#45" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(8)} -pin  "ACC1:acc#45" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(9)} -pin  "ACC1:acc#45" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(10)} -pin  "ACC1:acc#45" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(11)} -pin  "ACC1:acc#45" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(12)} -pin  "ACC1:acc#45" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(13)} -pin  "ACC1:acc#45" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(14)} -pin  "ACC1:acc#45" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(15)} -pin  "ACC1:acc#45" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {ACC1:acc#45.itm(0)} -pin  "ACC1:acc#45" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(1)} -pin  "ACC1:acc#45" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(2)} -pin  "ACC1:acc#45" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(3)} -pin  "ACC1:acc#45" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(4)} -pin  "ACC1:acc#45" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(5)} -pin  "ACC1:acc#45" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(6)} -pin  "ACC1:acc#45" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(7)} -pin  "ACC1:acc#45" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(8)} -pin  "ACC1:acc#45" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(9)} -pin  "ACC1:acc#45" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(10)} -pin  "ACC1:acc#45" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "ACC1:acc#45" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(12)} -pin  "ACC1:acc#45" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(13)} -pin  "ACC1:acc#45" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(14)} -pin  "ACC1:acc#45" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(15)} -pin  "ACC1:acc#45" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load inst "FRAME:not#18" "not(3)" "INTERFACE" -attr xrf 5341 -attr oid 475 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#45.itm(10)} -pin  "FRAME:not#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "FRAME:not#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {ACC1:acc#45.itm(12)} -pin  "FRAME:not#18" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {FRAME:not#18.itm(0)} -pin  "FRAME:not#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(1)} -pin  "FRAME:not#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(2)} -pin  "FRAME:not#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load inst "FRAME:acc#25" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 5342 -attr oid 476 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#45.itm(7)} -pin  "FRAME:acc#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {ACC1:acc#45.itm(8)} -pin  "FRAME:acc#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {ACC1:acc#45.itm(9)} -pin  "FRAME:acc#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {FRAME:not#18.itm(0)} -pin  "FRAME:acc#25" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(1)} -pin  "FRAME:acc#25" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(2)} -pin  "FRAME:acc#25" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:acc#25.itm(0)} -pin  "FRAME:acc#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(1)} -pin  "FRAME:acc#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(2)} -pin  "FRAME:acc#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(3)} -pin  "FRAME:acc#25" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load inst "FRAME:not#36" "not(1)" "INTERFACE" -attr xrf 5343 -attr oid 477 -attr @path {/sobel/sobel:core/FRAME:not#36} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#45.itm(15)} -pin  "FRAME:not#36" {A(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#12.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:not#36" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#36.itm}
+load inst "FRAME:not#47" "not(1)" "INTERFACE" -attr xrf 5344 -attr oid 478 -attr @path {/sobel/sobel:core/FRAME:not#47} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#45.itm(15)} -pin  "FRAME:not#47" {A(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#7.itm}
+load net {FRAME:not#47.itm} -pin  "FRAME:not#47" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#47.itm}
+load inst "FRAME:acc#24" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 5345 -attr oid 479 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#47.itm} -pin  "FRAME:acc#24" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {PWR} -pin  "FRAME:acc#24" {A(1)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:acc#24" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {ACC1:acc#45.itm(13)} -pin  "FRAME:acc#24" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#4.itm}
+load net {ACC1:acc#45.itm(14)} -pin  "FRAME:acc#24" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#4.itm}
+load net {FRAME:acc#24.itm(0)} -pin  "FRAME:acc#24" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(1)} -pin  "FRAME:acc#24" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(2)} -pin  "FRAME:acc#24" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(3)} -pin  "FRAME:acc#24" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load inst "FRAME:acc#27" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 5346 -attr oid 480 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#25.itm(0)} -pin  "FRAME:acc#27" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(1)} -pin  "FRAME:acc#27" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(2)} -pin  "FRAME:acc#27" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(3)} -pin  "FRAME:acc#27" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#24.itm(0)} -pin  "FRAME:acc#27" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(1)} -pin  "FRAME:acc#27" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(2)} -pin  "FRAME:acc#27" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(3)} -pin  "FRAME:acc#27" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#27.itm(0)} -pin  "FRAME:acc#27" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(1)} -pin  "FRAME:acc#27" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(2)} -pin  "FRAME:acc#27" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(3)} -pin  "FRAME:acc#27" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(4)} -pin  "FRAME:acc#27" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load inst "FRAME:not#17" "not(3)" "INTERFACE" -attr xrf 5347 -attr oid 481 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#45.itm(4)} -pin  "FRAME:not#17" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {ACC1:acc#45.itm(5)} -pin  "FRAME:not#17" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {ACC1:acc#45.itm(6)} -pin  "FRAME:not#17" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {FRAME:not#17.itm(0)} -pin  "FRAME:not#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(1)} -pin  "FRAME:not#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(2)} -pin  "FRAME:not#17" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load inst "FRAME:acc#26" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 5348 -attr oid 482 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#45.itm(1)} -pin  "FRAME:acc#26" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {ACC1:acc#45.itm(2)} -pin  "FRAME:acc#26" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {ACC1:acc#45.itm(3)} -pin  "FRAME:acc#26" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {FRAME:not#17.itm(0)} -pin  "FRAME:acc#26" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(1)} -pin  "FRAME:acc#26" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(2)} -pin  "FRAME:acc#26" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:acc#26.itm(0)} -pin  "FRAME:acc#26" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(1)} -pin  "FRAME:acc#26" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(2)} -pin  "FRAME:acc#26" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(3)} -pin  "FRAME:acc#26" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load inst "FRAME:acc#28" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 5349 -attr oid 483 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28} -attr area 6.288444 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6)"
+load net {FRAME:acc#27.itm(0)} -pin  "FRAME:acc#28" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(1)} -pin  "FRAME:acc#28" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(2)} -pin  "FRAME:acc#28" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(3)} -pin  "FRAME:acc#28" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(4)} -pin  "FRAME:acc#28" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#26.itm(0)} -pin  "FRAME:acc#28" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(1)} -pin  "FRAME:acc#28" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(2)} -pin  "FRAME:acc#28" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(3)} -pin  "FRAME:acc#28" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#28.itm(0)} -pin  "FRAME:acc#28" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(1)} -pin  "FRAME:acc#28" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(2)} -pin  "FRAME:acc#28" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(3)} -pin  "FRAME:acc#28" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(4)} -pin  "FRAME:acc#28" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(5)} -pin  "FRAME:acc#28" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load inst "acc#4" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 5350 -attr oid 484 -attr vt d -attr @path {/sobel/sobel:core/acc#4} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {FRAME:acc#28.itm(0)} -pin  "acc#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(1)} -pin  "acc#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(2)} -pin  "acc#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(3)} -pin  "acc#4" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(4)} -pin  "acc#4" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(5)} -pin  "acc#4" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {PWR} -pin  "acc#4" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#4" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#4" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#4" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#4" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#4" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#4.sva(0)} -pin  "acc#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#4.sva}
+load net {acc.imod#4.sva(1)} -pin  "acc#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#4.sva}
+load net {acc.imod#4.sva(2)} -pin  "acc#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#4.sva}
+load net {acc.imod#4.sva(3)} -pin  "acc#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#4.sva}
+load net {acc.imod#4.sva(4)} -pin  "acc#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#4.sva}
+load net {acc.imod#4.sva(5)} -pin  "acc#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#4.sva}
+load inst "ACC2:not#3" "not(10)" "INTERFACE" -attr xrf 5351 -attr oid 485 -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "ACC2:not#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "ACC2:not#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "ACC2:not#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "ACC2:not#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "ACC2:not#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "ACC2:not#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "ACC2:not#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "ACC2:not#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "ACC2:not#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "ACC2:not#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {ACC2:not#3.itm(0)} -pin  "ACC2:not#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(1)} -pin  "ACC2:not#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(2)} -pin  "ACC2:not#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(3)} -pin  "ACC2:not#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(4)} -pin  "ACC2:not#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(5)} -pin  "ACC2:not#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(6)} -pin  "ACC2:not#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(7)} -pin  "ACC2:not#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(8)} -pin  "ACC2:not#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(9)} -pin  "ACC2:not#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load inst "acc#7" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 5352 -attr oid 486 -attr vt d -attr @path {/sobel/sobel:core/acc#7} -attr area 12.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "acc#7" {A(0)} -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(0)} -pin  "acc#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(1)} -pin  "acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(2)} -pin  "acc#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(3)} -pin  "acc#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(4)} -pin  "acc#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(5)} -pin  "acc#7" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(6)} -pin  "acc#7" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(7)} -pin  "acc#7" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(8)} -pin  "acc#7" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(9)} -pin  "acc#7" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {PWR} -pin  "acc#7" {B(0)} -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "acc#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "acc#7" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "acc#7" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "acc#7" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "acc#7" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "acc#7" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "acc#7" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "acc#7" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "acc#7" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "acc#7" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {acc#7.itm(0)} -pin  "acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(1)} -pin  "acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(2)} -pin  "acc#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(3)} -pin  "acc#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(4)} -pin  "acc#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(5)} -pin  "acc#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(6)} -pin  "acc#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(7)} -pin  "acc#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(8)} -pin  "acc#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(9)} -pin  "acc#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(10)} -pin  "acc#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(11)} -pin  "acc#7" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load inst "ACC1:acc#66" "add(11,1,15,-1,15)" "INTERFACE" -attr xrf 5353 -attr oid 487 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66} -attr area 16.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {acc#7.itm(1)} -pin  "ACC1:acc#66" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(2)} -pin  "ACC1:acc#66" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(3)} -pin  "ACC1:acc#66" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(4)} -pin  "ACC1:acc#66" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(5)} -pin  "ACC1:acc#66" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(6)} -pin  "ACC1:acc#66" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(7)} -pin  "ACC1:acc#66" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(8)} -pin  "ACC1:acc#66" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(9)} -pin  "ACC1:acc#66" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(10)} -pin  "ACC1:acc#66" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(11)} -pin  "ACC1:acc#66" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {g(2).sva#3(1)} -pin  "ACC1:acc#66" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(2)} -pin  "ACC1:acc#66" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(3)} -pin  "ACC1:acc#66" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(4)} -pin  "ACC1:acc#66" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(5)} -pin  "ACC1:acc#66" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(6)} -pin  "ACC1:acc#66" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(7)} -pin  "ACC1:acc#66" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(8)} -pin  "ACC1:acc#66" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(9)} -pin  "ACC1:acc#66" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(10)} -pin  "ACC1:acc#66" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(11)} -pin  "ACC1:acc#66" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(12)} -pin  "ACC1:acc#66" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(13)} -pin  "ACC1:acc#66" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(14)} -pin  "ACC1:acc#66" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(15)} -pin  "ACC1:acc#66" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {ACC1:acc#66.itm(0)} -pin  "ACC1:acc#66" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(1)} -pin  "ACC1:acc#66" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(2)} -pin  "ACC1:acc#66" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(3)} -pin  "ACC1:acc#66" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(4)} -pin  "ACC1:acc#66" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(5)} -pin  "ACC1:acc#66" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(6)} -pin  "ACC1:acc#66" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(7)} -pin  "ACC1:acc#66" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(8)} -pin  "ACC1:acc#66" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(9)} -pin  "ACC1:acc#66" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(10)} -pin  "ACC1:acc#66" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(11)} -pin  "ACC1:acc#66" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(12)} -pin  "ACC1:acc#66" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(13)} -pin  "ACC1:acc#66" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(14)} -pin  "ACC1:acc#66" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load inst "ACC1:acc#65" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 5354 -attr oid 488 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#65} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {PWR} -pin  "ACC1:acc#65" {A(0)} -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {g(2).sva#3(0)} -pin  "ACC1:acc#65" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {PWR} -pin  "ACC1:acc#65" {B(0)} -attr @path {/sobel/sobel:core/Cn1_1#3}
+load net {ACC1:acc#65.itm(0)} -pin  "ACC1:acc#65" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#65.itm}
+load net {ACC1:acc#65.itm(1)} -pin  "ACC1:acc#65" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#65.itm}
+load inst "ACC1:acc#44" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 5355 -attr oid 489 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {ACC1:acc#65.itm(1)} -pin  "ACC1:acc#44" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(0)} -pin  "ACC1:acc#44" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(1)} -pin  "ACC1:acc#44" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(2)} -pin  "ACC1:acc#44" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(3)} -pin  "ACC1:acc#44" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(4)} -pin  "ACC1:acc#44" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(5)} -pin  "ACC1:acc#44" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(6)} -pin  "ACC1:acc#44" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(7)} -pin  "ACC1:acc#44" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(8)} -pin  "ACC1:acc#44" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(9)} -pin  "ACC1:acc#44" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(10)} -pin  "ACC1:acc#44" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(11)} -pin  "ACC1:acc#44" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(12)} -pin  "ACC1:acc#44" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(13)} -pin  "ACC1:acc#44" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(14)} -pin  "ACC1:acc#44" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {g(0).sva#3(0)} -pin  "ACC1:acc#44" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(1)} -pin  "ACC1:acc#44" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(2)} -pin  "ACC1:acc#44" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(3)} -pin  "ACC1:acc#44" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(4)} -pin  "ACC1:acc#44" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(5)} -pin  "ACC1:acc#44" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(6)} -pin  "ACC1:acc#44" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(7)} -pin  "ACC1:acc#44" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(8)} -pin  "ACC1:acc#44" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(9)} -pin  "ACC1:acc#44" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(10)} -pin  "ACC1:acc#44" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(11)} -pin  "ACC1:acc#44" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(12)} -pin  "ACC1:acc#44" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(13)} -pin  "ACC1:acc#44" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(14)} -pin  "ACC1:acc#44" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(15)} -pin  "ACC1:acc#44" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {ACC1:acc#44.itm(0)} -pin  "ACC1:acc#44" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(1)} -pin  "ACC1:acc#44" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(2)} -pin  "ACC1:acc#44" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(3)} -pin  "ACC1:acc#44" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(4)} -pin  "ACC1:acc#44" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(5)} -pin  "ACC1:acc#44" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(6)} -pin  "ACC1:acc#44" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(7)} -pin  "ACC1:acc#44" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(8)} -pin  "ACC1:acc#44" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(9)} -pin  "ACC1:acc#44" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(10)} -pin  "ACC1:acc#44" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(11)} -pin  "ACC1:acc#44" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(12)} -pin  "ACC1:acc#44" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(13)} -pin  "ACC1:acc#44" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(14)} -pin  "ACC1:acc#44" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(15)} -pin  "ACC1:acc#44" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load inst "FRAME:not#10" "not(3)" "INTERFACE" -attr xrf 5356 -attr oid 490 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#44.itm(10)} -pin  "FRAME:not#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {ACC1:acc#44.itm(11)} -pin  "FRAME:not#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {ACC1:acc#44.itm(12)} -pin  "FRAME:not#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {FRAME:not#10.itm(0)} -pin  "FRAME:not#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(1)} -pin  "FRAME:not#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(2)} -pin  "FRAME:not#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load inst "FRAME:acc#13" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 5357 -attr oid 491 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#44.itm(7)} -pin  "FRAME:acc#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {ACC1:acc#44.itm(8)} -pin  "FRAME:acc#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {ACC1:acc#44.itm(9)} -pin  "FRAME:acc#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {FRAME:not#10.itm(0)} -pin  "FRAME:acc#13" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(1)} -pin  "FRAME:acc#13" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(2)} -pin  "FRAME:acc#13" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load inst "FRAME:not#37" "not(1)" "INTERFACE" -attr xrf 5358 -attr oid 492 -attr @path {/sobel/sobel:core/FRAME:not#37} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#44.itm(15)} -pin  "FRAME:not#37" {A(0)} -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#12.itm}
+load net {FRAME:not#37.itm} -pin  "FRAME:not#37" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#37.itm}
+load inst "FRAME:not#49" "not(1)" "INTERFACE" -attr xrf 5359 -attr oid 493 -attr @path {/sobel/sobel:core/FRAME:not#49} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#44.itm(15)} -pin  "FRAME:not#49" {A(0)} -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#7.itm}
+load net {FRAME:not#49.itm} -pin  "FRAME:not#49" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#49.itm}
+load inst "FRAME:acc#12" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 5360 -attr oid 494 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#49.itm} -pin  "FRAME:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#151.itm}
+load net {PWR} -pin  "FRAME:acc#12" {A(1)} -attr @path {/sobel/sobel:core/conc#151.itm}
+load net {FRAME:not#37.itm} -pin  "FRAME:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#151.itm}
+load net {ACC1:acc#44.itm(13)} -pin  "FRAME:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#4.itm}
+load net {ACC1:acc#44.itm(14)} -pin  "FRAME:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#4.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load inst "FRAME:acc#15" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 5361 -attr oid 495 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#15" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#15" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#15" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#15" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#15" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load inst "FRAME:not#9" "not(3)" "INTERFACE" -attr xrf 5362 -attr oid 496 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#44.itm(4)} -pin  "FRAME:not#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {ACC1:acc#44.itm(5)} -pin  "FRAME:not#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {ACC1:acc#44.itm(6)} -pin  "FRAME:not#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {FRAME:not#9.itm(0)} -pin  "FRAME:not#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(1)} -pin  "FRAME:not#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(2)} -pin  "FRAME:not#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load inst "FRAME:acc#14" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 5363 -attr oid 497 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#44.itm(1)} -pin  "FRAME:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {ACC1:acc#44.itm(2)} -pin  "FRAME:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {ACC1:acc#44.itm(3)} -pin  "FRAME:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {FRAME:not#9.itm(0)} -pin  "FRAME:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(1)} -pin  "FRAME:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(2)} -pin  "FRAME:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load inst "FRAME:acc#16" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 5364 -attr oid 498 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16} -attr area 6.288444 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6)"
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#16" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#16" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#16" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#16" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#16" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#16" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#16.itm(0)} -pin  "FRAME:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "FRAME:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "FRAME:acc#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "FRAME:acc#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:acc#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(5)} -pin  "FRAME:acc#16" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load inst "acc#2" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 5365 -attr oid 499 -attr vt d -attr @path {/sobel/sobel:core/acc#2} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {FRAME:acc#16.itm(0)} -pin  "acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(5)} -pin  "acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {PWR} -pin  "acc#2" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#2" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#2" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#2" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#2" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#2" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#2.sva(0)} -pin  "acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#2.sva}
+load net {acc.imod#2.sva(1)} -pin  "acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#2.sva}
+load net {acc.imod#2.sva(2)} -pin  "acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#2.sva}
+load net {acc.imod#2.sva(3)} -pin  "acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#2.sva}
+load net {acc.imod#2.sva(4)} -pin  "acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#2.sva}
+load net {acc.imod#2.sva(5)} -pin  "acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#2.sva}
+load inst "ACC1:not#14" "not(10)" "INTERFACE" -attr xrf 5366 -attr oid 500 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "ACC1:not#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "ACC1:not#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "ACC1:not#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "ACC1:not#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "ACC1:not#14" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "ACC1:not#14" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "ACC1:not#14" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "ACC1:not#14" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "ACC1:not#14" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:not#14" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {ACC1:not#14.itm(0)} -pin  "ACC1:not#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(1)} -pin  "ACC1:not#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(2)} -pin  "ACC1:not#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(3)} -pin  "ACC1:not#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(4)} -pin  "ACC1:not#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(5)} -pin  "ACC1:not#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(6)} -pin  "ACC1:not#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(7)} -pin  "ACC1:not#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(8)} -pin  "ACC1:not#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(9)} -pin  "ACC1:not#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load inst "ACC1:acc#52" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 5367 -attr oid 501 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#52" {A(0)} -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(0)} -pin  "ACC1:acc#52" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(1)} -pin  "ACC1:acc#52" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(2)} -pin  "ACC1:acc#52" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(3)} -pin  "ACC1:acc#52" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(4)} -pin  "ACC1:acc#52" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(5)} -pin  "ACC1:acc#52" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(6)} -pin  "ACC1:acc#52" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(7)} -pin  "ACC1:acc#52" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(8)} -pin  "ACC1:acc#52" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(9)} -pin  "ACC1:acc#52" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {PWR} -pin  "ACC1:acc#52" {B(0)} -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(60)} -pin  "ACC1:acc#52" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(61)} -pin  "ACC1:acc#52" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(62)} -pin  "ACC1:acc#52" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(63)} -pin  "ACC1:acc#52" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(64)} -pin  "ACC1:acc#52" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(65)} -pin  "ACC1:acc#52" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(66)} -pin  "ACC1:acc#52" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(67)} -pin  "ACC1:acc#52" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(68)} -pin  "ACC1:acc#52" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(69)} -pin  "ACC1:acc#52" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {ACC1:acc#52.itm(0)} -pin  "ACC1:acc#52" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(1)} -pin  "ACC1:acc#52" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(2)} -pin  "ACC1:acc#52" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(3)} -pin  "ACC1:acc#52" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(4)} -pin  "ACC1:acc#52" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(5)} -pin  "ACC1:acc#52" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(6)} -pin  "ACC1:acc#52" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(7)} -pin  "ACC1:acc#52" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(8)} -pin  "ACC1:acc#52" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(9)} -pin  "ACC1:acc#52" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(10)} -pin  "ACC1:acc#52" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "ACC1:acc#52" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load inst "FRAME:for:mux#10" "mux(2,16)" "INTERFACE" -attr xrf 5368 -attr oid 502 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#52.itm(1)} -pin  "FRAME:for:mux#10" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(2)} -pin  "FRAME:for:mux#10" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(3)} -pin  "FRAME:for:mux#10" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(4)} -pin  "FRAME:for:mux#10" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(5)} -pin  "FRAME:for:mux#10" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(6)} -pin  "FRAME:for:mux#10" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(7)} -pin  "FRAME:for:mux#10" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(8)} -pin  "FRAME:for:mux#10" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(9)} -pin  "FRAME:for:mux#10" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(10)} -pin  "FRAME:for:mux#10" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "FRAME:for:mux#10" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "FRAME:for:mux#10" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "FRAME:for:mux#10" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "FRAME:for:mux#10" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "FRAME:for:mux#10" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "FRAME:for:mux#10" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {b(2).sva#1(0)} -pin  "FRAME:for:mux#10" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(1)} -pin  "FRAME:for:mux#10" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(2)} -pin  "FRAME:for:mux#10" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(3)} -pin  "FRAME:for:mux#10" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(4)} -pin  "FRAME:for:mux#10" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(5)} -pin  "FRAME:for:mux#10" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(6)} -pin  "FRAME:for:mux#10" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(7)} -pin  "FRAME:for:mux#10" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(8)} -pin  "FRAME:for:mux#10" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(9)} -pin  "FRAME:for:mux#10" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(10)} -pin  "FRAME:for:mux#10" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(11)} -pin  "FRAME:for:mux#10" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(12)} -pin  "FRAME:for:mux#10" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(13)} -pin  "FRAME:for:mux#10" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(14)} -pin  "FRAME:for:mux#10" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(15)} -pin  "FRAME:for:mux#10" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#10" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#10.itm(0)} -pin  "FRAME:for:mux#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(1)} -pin  "FRAME:for:mux#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(2)} -pin  "FRAME:for:mux#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(3)} -pin  "FRAME:for:mux#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(4)} -pin  "FRAME:for:mux#10" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(5)} -pin  "FRAME:for:mux#10" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(6)} -pin  "FRAME:for:mux#10" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(7)} -pin  "FRAME:for:mux#10" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(8)} -pin  "FRAME:for:mux#10" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(9)} -pin  "FRAME:for:mux#10" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(10)} -pin  "FRAME:for:mux#10" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(11)} -pin  "FRAME:for:mux#10" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(12)} -pin  "FRAME:for:mux#10" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(13)} -pin  "FRAME:for:mux#10" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(14)} -pin  "FRAME:for:mux#10" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(15)} -pin  "FRAME:for:mux#10" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load inst "regs.operator[]#17:mux" "mux(4,10)" "INTERFACE" -attr xrf 5369 -attr oid 503 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "regs.operator[]#17:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "regs.operator[]#17:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "regs.operator[]#17:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "regs.operator[]#17:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "regs.operator[]#17:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "regs.operator[]#17:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "regs.operator[]#17:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "regs.operator[]#17:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "regs.operator[]#17:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "regs.operator[]#17:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "regs.operator[]#17:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "regs.operator[]#17:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "regs.operator[]#17:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "regs.operator[]#17:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "regs.operator[]#17:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "regs.operator[]#17:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "regs.operator[]#17:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "regs.operator[]#17:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "regs.operator[]#17:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "regs.operator[]#17:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "regs.operator[]#17:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "regs.operator[]#17:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "regs.operator[]#17:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "regs.operator[]#17:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "regs.operator[]#17:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "regs.operator[]#17:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "regs.operator[]#17:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "regs.operator[]#17:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "regs.operator[]#17:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "regs.operator[]#17:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#17:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#17:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#17:mux.itm(0)} -pin  "regs.operator[]#17:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(1)} -pin  "regs.operator[]#17:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(2)} -pin  "regs.operator[]#17:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(3)} -pin  "regs.operator[]#17:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(4)} -pin  "regs.operator[]#17:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(5)} -pin  "regs.operator[]#17:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(6)} -pin  "regs.operator[]#17:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(7)} -pin  "regs.operator[]#17:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(8)} -pin  "regs.operator[]#17:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(9)} -pin  "regs.operator[]#17:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load inst "FRAME:for:mul#8" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 5370 -attr oid 504 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#17:mux.itm(0)} -pin  "FRAME:for:mul#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(1)} -pin  "FRAME:for:mul#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(2)} -pin  "FRAME:for:mul#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(3)} -pin  "FRAME:for:mul#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(4)} -pin  "FRAME:for:mul#8" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(5)} -pin  "FRAME:for:mul#8" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(6)} -pin  "FRAME:for:mul#8" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(7)} -pin  "FRAME:for:mul#8" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(8)} -pin  "FRAME:for:mul#8" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(9)} -pin  "FRAME:for:mul#8" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:mul#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:mul#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:mul#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:mul#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:mul#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:mul#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:mul#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:mul#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:mul#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:mul#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:mul#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load inst "FRAME:for:acc#14" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 5371 -attr oid 505 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#10.itm(0)} -pin  "FRAME:for:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(1)} -pin  "FRAME:for:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(2)} -pin  "FRAME:for:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(3)} -pin  "FRAME:for:acc#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(4)} -pin  "FRAME:for:acc#14" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(5)} -pin  "FRAME:for:acc#14" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(6)} -pin  "FRAME:for:acc#14" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(7)} -pin  "FRAME:for:acc#14" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(8)} -pin  "FRAME:for:acc#14" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(9)} -pin  "FRAME:for:acc#14" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(10)} -pin  "FRAME:for:acc#14" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(11)} -pin  "FRAME:for:acc#14" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(12)} -pin  "FRAME:for:acc#14" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(13)} -pin  "FRAME:for:acc#14" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(14)} -pin  "FRAME:for:acc#14" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(15)} -pin  "FRAME:for:acc#14" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:acc#14" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:acc#14" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:acc#14" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:acc#14" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:acc#14" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:acc#14" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:acc#14" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:acc#14" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {b(2).sva#3(0)} -pin  "FRAME:for:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(1)} -pin  "FRAME:for:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(2)} -pin  "FRAME:for:acc#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(3)} -pin  "FRAME:for:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(4)} -pin  "FRAME:for:acc#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(5)} -pin  "FRAME:for:acc#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(6)} -pin  "FRAME:for:acc#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(7)} -pin  "FRAME:for:acc#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(8)} -pin  "FRAME:for:acc#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(9)} -pin  "FRAME:for:acc#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(10)} -pin  "FRAME:for:acc#14" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(11)} -pin  "FRAME:for:acc#14" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(12)} -pin  "FRAME:for:acc#14" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(13)} -pin  "FRAME:for:acc#14" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(14)} -pin  "FRAME:for:acc#14" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(15)} -pin  "FRAME:for:acc#14" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load inst "ACC1:not#16" "not(10)" "INTERFACE" -attr xrf 5372 -attr oid 506 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "ACC1:not#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "ACC1:not#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "ACC1:not#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "ACC1:not#16" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "ACC1:not#16" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "ACC1:not#16" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "ACC1:not#16" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "ACC1:not#16" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "ACC1:not#16" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:not#16" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:not#16.itm(0)} -pin  "ACC1:not#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(1)} -pin  "ACC1:not#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(2)} -pin  "ACC1:not#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(3)} -pin  "ACC1:not#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(4)} -pin  "ACC1:not#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(5)} -pin  "ACC1:not#16" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(6)} -pin  "ACC1:not#16" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(7)} -pin  "ACC1:not#16" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(8)} -pin  "ACC1:not#16" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(9)} -pin  "ACC1:not#16" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load inst "ACC1:acc#49" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 5373 -attr oid 507 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#49" {A(0)} -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(0)} -pin  "ACC1:acc#49" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(1)} -pin  "ACC1:acc#49" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(2)} -pin  "ACC1:acc#49" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(3)} -pin  "ACC1:acc#49" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(4)} -pin  "ACC1:acc#49" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(5)} -pin  "ACC1:acc#49" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(6)} -pin  "ACC1:acc#49" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(7)} -pin  "ACC1:acc#49" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(8)} -pin  "ACC1:acc#49" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(9)} -pin  "ACC1:acc#49" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {PWR} -pin  "ACC1:acc#49" {B(0)} -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(0)} -pin  "ACC1:acc#49" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(1)} -pin  "ACC1:acc#49" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(2)} -pin  "ACC1:acc#49" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(3)} -pin  "ACC1:acc#49" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(4)} -pin  "ACC1:acc#49" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(5)} -pin  "ACC1:acc#49" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(6)} -pin  "ACC1:acc#49" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(7)} -pin  "ACC1:acc#49" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(8)} -pin  "ACC1:acc#49" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(9)} -pin  "ACC1:acc#49" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC1:acc#49.itm(0)} -pin  "ACC1:acc#49" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(1)} -pin  "ACC1:acc#49" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(2)} -pin  "ACC1:acc#49" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(3)} -pin  "ACC1:acc#49" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(4)} -pin  "ACC1:acc#49" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(5)} -pin  "ACC1:acc#49" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(6)} -pin  "ACC1:acc#49" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(7)} -pin  "ACC1:acc#49" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(8)} -pin  "ACC1:acc#49" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(9)} -pin  "ACC1:acc#49" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(10)} -pin  "ACC1:acc#49" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "ACC1:acc#49" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load inst "FRAME:for:mux#9" "mux(2,16)" "INTERFACE" -attr xrf 5374 -attr oid 508 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#49.itm(1)} -pin  "FRAME:for:mux#9" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(2)} -pin  "FRAME:for:mux#9" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(3)} -pin  "FRAME:for:mux#9" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(4)} -pin  "FRAME:for:mux#9" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(5)} -pin  "FRAME:for:mux#9" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(6)} -pin  "FRAME:for:mux#9" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(7)} -pin  "FRAME:for:mux#9" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(8)} -pin  "FRAME:for:mux#9" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(9)} -pin  "FRAME:for:mux#9" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(10)} -pin  "FRAME:for:mux#9" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#9" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#9" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#9" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#9" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#9" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#9" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {b(0).sva#1(0)} -pin  "FRAME:for:mux#9" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(1)} -pin  "FRAME:for:mux#9" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(2)} -pin  "FRAME:for:mux#9" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(3)} -pin  "FRAME:for:mux#9" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(4)} -pin  "FRAME:for:mux#9" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(5)} -pin  "FRAME:for:mux#9" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(6)} -pin  "FRAME:for:mux#9" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(7)} -pin  "FRAME:for:mux#9" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(8)} -pin  "FRAME:for:mux#9" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(9)} -pin  "FRAME:for:mux#9" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(10)} -pin  "FRAME:for:mux#9" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(11)} -pin  "FRAME:for:mux#9" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(12)} -pin  "FRAME:for:mux#9" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(13)} -pin  "FRAME:for:mux#9" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(14)} -pin  "FRAME:for:mux#9" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(15)} -pin  "FRAME:for:mux#9" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#9" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#9.itm(0)} -pin  "FRAME:for:mux#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(1)} -pin  "FRAME:for:mux#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(2)} -pin  "FRAME:for:mux#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(3)} -pin  "FRAME:for:mux#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(4)} -pin  "FRAME:for:mux#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(5)} -pin  "FRAME:for:mux#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(6)} -pin  "FRAME:for:mux#9" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(7)} -pin  "FRAME:for:mux#9" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(8)} -pin  "FRAME:for:mux#9" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(9)} -pin  "FRAME:for:mux#9" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(10)} -pin  "FRAME:for:mux#9" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(11)} -pin  "FRAME:for:mux#9" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(12)} -pin  "FRAME:for:mux#9" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(13)} -pin  "FRAME:for:mux#9" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(14)} -pin  "FRAME:for:mux#9" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(15)} -pin  "FRAME:for:mux#9" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load inst "regs.operator[]#11:mux" "mux(4,10)" "INTERFACE" -attr xrf 5375 -attr oid 509 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "regs.operator[]#11:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "regs.operator[]#11:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "regs.operator[]#11:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "regs.operator[]#11:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "regs.operator[]#11:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "regs.operator[]#11:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "regs.operator[]#11:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "regs.operator[]#11:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "regs.operator[]#11:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "regs.operator[]#11:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "regs.operator[]#11:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "regs.operator[]#11:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "regs.operator[]#11:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "regs.operator[]#11:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "regs.operator[]#11:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "regs.operator[]#11:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "regs.operator[]#11:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "regs.operator[]#11:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "regs.operator[]#11:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "regs.operator[]#11:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "regs.operator[]#11:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "regs.operator[]#11:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "regs.operator[]#11:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "regs.operator[]#11:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "regs.operator[]#11:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "regs.operator[]#11:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "regs.operator[]#11:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "regs.operator[]#11:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "regs.operator[]#11:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "regs.operator[]#11:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#11:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#11:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#11:mux.itm(0)} -pin  "regs.operator[]#11:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(1)} -pin  "regs.operator[]#11:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(2)} -pin  "regs.operator[]#11:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(3)} -pin  "regs.operator[]#11:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(4)} -pin  "regs.operator[]#11:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(5)} -pin  "regs.operator[]#11:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(6)} -pin  "regs.operator[]#11:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(7)} -pin  "regs.operator[]#11:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(8)} -pin  "regs.operator[]#11:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(9)} -pin  "regs.operator[]#11:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load inst "FRAME:for:mul#2" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 5376 -attr oid 510 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#11:mux.itm(0)} -pin  "FRAME:for:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(1)} -pin  "FRAME:for:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(2)} -pin  "FRAME:for:mul#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(3)} -pin  "FRAME:for:mul#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(4)} -pin  "FRAME:for:mul#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(5)} -pin  "FRAME:for:mul#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(6)} -pin  "FRAME:for:mul#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(7)} -pin  "FRAME:for:mul#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(8)} -pin  "FRAME:for:mul#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(9)} -pin  "FRAME:for:mul#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {PWR} -pin  "FRAME:for:mul#2" {B(1)} -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(11)} -pin  "FRAME:for:mul#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load inst "FRAME:for:acc#3" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 5377 -attr oid 511 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#9.itm(0)} -pin  "FRAME:for:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(1)} -pin  "FRAME:for:acc#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(2)} -pin  "FRAME:for:acc#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(3)} -pin  "FRAME:for:acc#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(4)} -pin  "FRAME:for:acc#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(5)} -pin  "FRAME:for:acc#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(6)} -pin  "FRAME:for:acc#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(7)} -pin  "FRAME:for:acc#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(8)} -pin  "FRAME:for:acc#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(9)} -pin  "FRAME:for:acc#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(10)} -pin  "FRAME:for:acc#3" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(11)} -pin  "FRAME:for:acc#3" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(12)} -pin  "FRAME:for:acc#3" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(13)} -pin  "FRAME:for:acc#3" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(14)} -pin  "FRAME:for:acc#3" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(15)} -pin  "FRAME:for:acc#3" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:acc#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:acc#3" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:acc#3" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:acc#3" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:acc#3" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:acc#3" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:acc#3" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:acc#3" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:acc#3" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:acc#3" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(11)} -pin  "FRAME:for:acc#3" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {b(0).sva#3(0)} -pin  "FRAME:for:acc#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(1)} -pin  "FRAME:for:acc#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(2)} -pin  "FRAME:for:acc#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(3)} -pin  "FRAME:for:acc#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(4)} -pin  "FRAME:for:acc#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(5)} -pin  "FRAME:for:acc#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(6)} -pin  "FRAME:for:acc#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(7)} -pin  "FRAME:for:acc#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(8)} -pin  "FRAME:for:acc#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(9)} -pin  "FRAME:for:acc#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(10)} -pin  "FRAME:for:acc#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(11)} -pin  "FRAME:for:acc#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(12)} -pin  "FRAME:for:acc#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(13)} -pin  "FRAME:for:acc#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(14)} -pin  "FRAME:for:acc#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(15)} -pin  "FRAME:for:acc#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load inst "ACC1:not#13" "not(10)" "INTERFACE" -attr xrf 5378 -attr oid 512 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "ACC1:not#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "ACC1:not#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "ACC1:not#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "ACC1:not#13" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "ACC1:not#13" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "ACC1:not#13" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "ACC1:not#13" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "ACC1:not#13" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "ACC1:not#13" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:not#13" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {ACC1:not#13.itm(0)} -pin  "ACC1:not#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(1)} -pin  "ACC1:not#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(2)} -pin  "ACC1:not#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(3)} -pin  "ACC1:not#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(4)} -pin  "ACC1:not#13" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(5)} -pin  "ACC1:not#13" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(6)} -pin  "ACC1:not#13" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(7)} -pin  "ACC1:not#13" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(8)} -pin  "ACC1:not#13" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(9)} -pin  "ACC1:not#13" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load inst "ACC1:acc#51" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 5379 -attr oid 513 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#51" {A(0)} -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(0)} -pin  "ACC1:acc#51" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(1)} -pin  "ACC1:acc#51" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(2)} -pin  "ACC1:acc#51" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(3)} -pin  "ACC1:acc#51" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(4)} -pin  "ACC1:acc#51" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(5)} -pin  "ACC1:acc#51" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(6)} -pin  "ACC1:acc#51" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(7)} -pin  "ACC1:acc#51" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(8)} -pin  "ACC1:acc#51" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(9)} -pin  "ACC1:acc#51" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {PWR} -pin  "ACC1:acc#51" {B(0)} -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(70)} -pin  "ACC1:acc#51" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(71)} -pin  "ACC1:acc#51" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(72)} -pin  "ACC1:acc#51" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(73)} -pin  "ACC1:acc#51" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(74)} -pin  "ACC1:acc#51" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(75)} -pin  "ACC1:acc#51" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(76)} -pin  "ACC1:acc#51" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(77)} -pin  "ACC1:acc#51" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(78)} -pin  "ACC1:acc#51" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(79)} -pin  "ACC1:acc#51" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {ACC1:acc#51.itm(0)} -pin  "ACC1:acc#51" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(1)} -pin  "ACC1:acc#51" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(2)} -pin  "ACC1:acc#51" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(3)} -pin  "ACC1:acc#51" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(4)} -pin  "ACC1:acc#51" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(5)} -pin  "ACC1:acc#51" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(6)} -pin  "ACC1:acc#51" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(7)} -pin  "ACC1:acc#51" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(8)} -pin  "ACC1:acc#51" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(9)} -pin  "ACC1:acc#51" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(10)} -pin  "ACC1:acc#51" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "ACC1:acc#51" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load inst "FRAME:for:mux#8" "mux(2,16)" "INTERFACE" -attr xrf 5380 -attr oid 514 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#51.itm(1)} -pin  "FRAME:for:mux#8" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(2)} -pin  "FRAME:for:mux#8" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(3)} -pin  "FRAME:for:mux#8" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(4)} -pin  "FRAME:for:mux#8" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(5)} -pin  "FRAME:for:mux#8" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(6)} -pin  "FRAME:for:mux#8" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(7)} -pin  "FRAME:for:mux#8" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(8)} -pin  "FRAME:for:mux#8" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(9)} -pin  "FRAME:for:mux#8" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(10)} -pin  "FRAME:for:mux#8" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "FRAME:for:mux#8" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "FRAME:for:mux#8" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "FRAME:for:mux#8" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "FRAME:for:mux#8" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "FRAME:for:mux#8" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "FRAME:for:mux#8" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {g(2).sva#1(0)} -pin  "FRAME:for:mux#8" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(1)} -pin  "FRAME:for:mux#8" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(2)} -pin  "FRAME:for:mux#8" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(3)} -pin  "FRAME:for:mux#8" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(4)} -pin  "FRAME:for:mux#8" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(5)} -pin  "FRAME:for:mux#8" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(6)} -pin  "FRAME:for:mux#8" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(7)} -pin  "FRAME:for:mux#8" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(8)} -pin  "FRAME:for:mux#8" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(9)} -pin  "FRAME:for:mux#8" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(10)} -pin  "FRAME:for:mux#8" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(11)} -pin  "FRAME:for:mux#8" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(12)} -pin  "FRAME:for:mux#8" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(13)} -pin  "FRAME:for:mux#8" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(14)} -pin  "FRAME:for:mux#8" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(15)} -pin  "FRAME:for:mux#8" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#8" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#8.itm(0)} -pin  "FRAME:for:mux#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(1)} -pin  "FRAME:for:mux#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(2)} -pin  "FRAME:for:mux#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(3)} -pin  "FRAME:for:mux#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(4)} -pin  "FRAME:for:mux#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(5)} -pin  "FRAME:for:mux#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(6)} -pin  "FRAME:for:mux#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(7)} -pin  "FRAME:for:mux#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(8)} -pin  "FRAME:for:mux#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(9)} -pin  "FRAME:for:mux#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(10)} -pin  "FRAME:for:mux#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(11)} -pin  "FRAME:for:mux#8" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(12)} -pin  "FRAME:for:mux#8" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(13)} -pin  "FRAME:for:mux#8" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(14)} -pin  "FRAME:for:mux#8" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(15)} -pin  "FRAME:for:mux#8" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load inst "regs.operator[]#16:mux" "mux(4,10)" "INTERFACE" -attr xrf 5381 -attr oid 515 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "regs.operator[]#16:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "regs.operator[]#16:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "regs.operator[]#16:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "regs.operator[]#16:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "regs.operator[]#16:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "regs.operator[]#16:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "regs.operator[]#16:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "regs.operator[]#16:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "regs.operator[]#16:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "regs.operator[]#16:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "regs.operator[]#16:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "regs.operator[]#16:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "regs.operator[]#16:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "regs.operator[]#16:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "regs.operator[]#16:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "regs.operator[]#16:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "regs.operator[]#16:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "regs.operator[]#16:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "regs.operator[]#16:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "regs.operator[]#16:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "regs.operator[]#16:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "regs.operator[]#16:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "regs.operator[]#16:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "regs.operator[]#16:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "regs.operator[]#16:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "regs.operator[]#16:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "regs.operator[]#16:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "regs.operator[]#16:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "regs.operator[]#16:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "regs.operator[]#16:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#16:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#16:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#16:mux.itm(0)} -pin  "regs.operator[]#16:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(1)} -pin  "regs.operator[]#16:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(2)} -pin  "regs.operator[]#16:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(3)} -pin  "regs.operator[]#16:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(4)} -pin  "regs.operator[]#16:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(5)} -pin  "regs.operator[]#16:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(6)} -pin  "regs.operator[]#16:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(7)} -pin  "regs.operator[]#16:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(8)} -pin  "regs.operator[]#16:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(9)} -pin  "regs.operator[]#16:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load inst "FRAME:for:mul#7" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 5382 -attr oid 516 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#16:mux.itm(0)} -pin  "FRAME:for:mul#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(1)} -pin  "FRAME:for:mul#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(2)} -pin  "FRAME:for:mul#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(3)} -pin  "FRAME:for:mul#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(4)} -pin  "FRAME:for:mul#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(5)} -pin  "FRAME:for:mul#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(6)} -pin  "FRAME:for:mul#7" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(7)} -pin  "FRAME:for:mul#7" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(8)} -pin  "FRAME:for:mul#7" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(9)} -pin  "FRAME:for:mul#7" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:mul#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:mul#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:mul#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:mul#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:mul#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:mul#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:mul#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:mul#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:mul#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:mul#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:mul#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load inst "FRAME:for:acc#12" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 5383 -attr oid 517 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#8.itm(0)} -pin  "FRAME:for:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(1)} -pin  "FRAME:for:acc#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(2)} -pin  "FRAME:for:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(3)} -pin  "FRAME:for:acc#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(4)} -pin  "FRAME:for:acc#12" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(5)} -pin  "FRAME:for:acc#12" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(6)} -pin  "FRAME:for:acc#12" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(7)} -pin  "FRAME:for:acc#12" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(8)} -pin  "FRAME:for:acc#12" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(9)} -pin  "FRAME:for:acc#12" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(10)} -pin  "FRAME:for:acc#12" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(11)} -pin  "FRAME:for:acc#12" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(12)} -pin  "FRAME:for:acc#12" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(13)} -pin  "FRAME:for:acc#12" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(14)} -pin  "FRAME:for:acc#12" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(15)} -pin  "FRAME:for:acc#12" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:acc#12" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:acc#12" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:acc#12" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:acc#12" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:acc#12" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:acc#12" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:acc#12" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:acc#12" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:acc#12" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {g(2).sva#3(0)} -pin  "FRAME:for:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(1)} -pin  "FRAME:for:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(2)} -pin  "FRAME:for:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(3)} -pin  "FRAME:for:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(4)} -pin  "FRAME:for:acc#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(5)} -pin  "FRAME:for:acc#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(6)} -pin  "FRAME:for:acc#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(7)} -pin  "FRAME:for:acc#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(8)} -pin  "FRAME:for:acc#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(9)} -pin  "FRAME:for:acc#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(10)} -pin  "FRAME:for:acc#12" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(11)} -pin  "FRAME:for:acc#12" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(12)} -pin  "FRAME:for:acc#12" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(13)} -pin  "FRAME:for:acc#12" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(14)} -pin  "FRAME:for:acc#12" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(15)} -pin  "FRAME:for:acc#12" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load inst "ACC1:not#15" "not(10)" "INTERFACE" -attr xrf 5384 -attr oid 518 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "ACC1:not#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "ACC1:not#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "ACC1:not#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "ACC1:not#15" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "ACC1:not#15" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "ACC1:not#15" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "ACC1:not#15" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "ACC1:not#15" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "ACC1:not#15" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:not#15" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {ACC1:not#15.itm(0)} -pin  "ACC1:not#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(1)} -pin  "ACC1:not#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(2)} -pin  "ACC1:not#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(3)} -pin  "ACC1:not#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(4)} -pin  "ACC1:not#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(5)} -pin  "ACC1:not#15" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(6)} -pin  "ACC1:not#15" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(7)} -pin  "ACC1:not#15" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(8)} -pin  "ACC1:not#15" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(9)} -pin  "ACC1:not#15" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load inst "ACC1:acc" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 5385 -attr oid 519 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc" {A(0)} -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(0)} -pin  "ACC1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(1)} -pin  "ACC1:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(2)} -pin  "ACC1:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(3)} -pin  "ACC1:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(4)} -pin  "ACC1:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(5)} -pin  "ACC1:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(6)} -pin  "ACC1:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(7)} -pin  "ACC1:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(8)} -pin  "ACC1:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(9)} -pin  "ACC1:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {PWR} -pin  "ACC1:acc" {B(0)} -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(10)} -pin  "ACC1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(11)} -pin  "ACC1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(12)} -pin  "ACC1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(13)} -pin  "ACC1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(14)} -pin  "ACC1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(15)} -pin  "ACC1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(16)} -pin  "ACC1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(17)} -pin  "ACC1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(18)} -pin  "ACC1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(19)} -pin  "ACC1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {ACC1:acc.itm(0)} -pin  "ACC1:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(1)} -pin  "ACC1:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(2)} -pin  "ACC1:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(3)} -pin  "ACC1:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(4)} -pin  "ACC1:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(5)} -pin  "ACC1:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(6)} -pin  "ACC1:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(7)} -pin  "ACC1:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(8)} -pin  "ACC1:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(9)} -pin  "ACC1:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(10)} -pin  "ACC1:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(11)} -pin  "ACC1:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load inst "FRAME:for:mux#7" "mux(2,16)" "INTERFACE" -attr xrf 5386 -attr oid 520 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc.itm(1)} -pin  "FRAME:for:mux#7" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(2)} -pin  "FRAME:for:mux#7" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(3)} -pin  "FRAME:for:mux#7" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(4)} -pin  "FRAME:for:mux#7" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:for:mux#7" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(6)} -pin  "FRAME:for:mux#7" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(7)} -pin  "FRAME:for:mux#7" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:for:mux#7" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:for:mux#7" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(10)} -pin  "FRAME:for:mux#7" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {g(0).sva#1(0)} -pin  "FRAME:for:mux#7" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(1)} -pin  "FRAME:for:mux#7" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(2)} -pin  "FRAME:for:mux#7" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(3)} -pin  "FRAME:for:mux#7" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(4)} -pin  "FRAME:for:mux#7" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(5)} -pin  "FRAME:for:mux#7" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(6)} -pin  "FRAME:for:mux#7" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(7)} -pin  "FRAME:for:mux#7" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(8)} -pin  "FRAME:for:mux#7" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(9)} -pin  "FRAME:for:mux#7" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(10)} -pin  "FRAME:for:mux#7" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(11)} -pin  "FRAME:for:mux#7" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(12)} -pin  "FRAME:for:mux#7" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(13)} -pin  "FRAME:for:mux#7" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(14)} -pin  "FRAME:for:mux#7" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(15)} -pin  "FRAME:for:mux#7" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#7" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#7.itm(0)} -pin  "FRAME:for:mux#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(1)} -pin  "FRAME:for:mux#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(2)} -pin  "FRAME:for:mux#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(3)} -pin  "FRAME:for:mux#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(4)} -pin  "FRAME:for:mux#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(5)} -pin  "FRAME:for:mux#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(6)} -pin  "FRAME:for:mux#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(7)} -pin  "FRAME:for:mux#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(8)} -pin  "FRAME:for:mux#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(9)} -pin  "FRAME:for:mux#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(10)} -pin  "FRAME:for:mux#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(11)} -pin  "FRAME:for:mux#7" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(12)} -pin  "FRAME:for:mux#7" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(13)} -pin  "FRAME:for:mux#7" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(14)} -pin  "FRAME:for:mux#7" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(15)} -pin  "FRAME:for:mux#7" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load inst "regs.operator[]#10:mux" "mux(4,10)" "INTERFACE" -attr xrf 5387 -attr oid 521 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "regs.operator[]#10:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "regs.operator[]#10:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "regs.operator[]#10:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "regs.operator[]#10:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "regs.operator[]#10:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "regs.operator[]#10:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "regs.operator[]#10:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "regs.operator[]#10:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "regs.operator[]#10:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "regs.operator[]#10:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "regs.operator[]#10:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "regs.operator[]#10:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "regs.operator[]#10:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "regs.operator[]#10:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "regs.operator[]#10:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "regs.operator[]#10:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "regs.operator[]#10:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "regs.operator[]#10:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "regs.operator[]#10:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "regs.operator[]#10:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "regs.operator[]#10:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "regs.operator[]#10:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "regs.operator[]#10:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "regs.operator[]#10:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "regs.operator[]#10:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "regs.operator[]#10:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "regs.operator[]#10:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "regs.operator[]#10:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "regs.operator[]#10:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "regs.operator[]#10:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#10:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#10:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#10:mux.itm(0)} -pin  "regs.operator[]#10:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(1)} -pin  "regs.operator[]#10:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(2)} -pin  "regs.operator[]#10:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(3)} -pin  "regs.operator[]#10:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(4)} -pin  "regs.operator[]#10:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(5)} -pin  "regs.operator[]#10:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(6)} -pin  "regs.operator[]#10:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(7)} -pin  "regs.operator[]#10:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(8)} -pin  "regs.operator[]#10:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(9)} -pin  "regs.operator[]#10:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load inst "FRAME:for:mul#1" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 5388 -attr oid 522 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#10:mux.itm(0)} -pin  "FRAME:for:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(1)} -pin  "FRAME:for:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(2)} -pin  "FRAME:for:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(3)} -pin  "FRAME:for:mul#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(4)} -pin  "FRAME:for:mul#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(5)} -pin  "FRAME:for:mul#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(6)} -pin  "FRAME:for:mul#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(7)} -pin  "FRAME:for:mul#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(8)} -pin  "FRAME:for:mul#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(9)} -pin  "FRAME:for:mul#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {PWR} -pin  "FRAME:for:mul#1" {B(1)} -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:mul#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:mul#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(11)} -pin  "FRAME:for:mul#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load inst "FRAME:for:acc#2" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 5389 -attr oid 523 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#7.itm(0)} -pin  "FRAME:for:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(1)} -pin  "FRAME:for:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(2)} -pin  "FRAME:for:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(3)} -pin  "FRAME:for:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(4)} -pin  "FRAME:for:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(5)} -pin  "FRAME:for:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(6)} -pin  "FRAME:for:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(7)} -pin  "FRAME:for:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(8)} -pin  "FRAME:for:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(9)} -pin  "FRAME:for:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(10)} -pin  "FRAME:for:acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(11)} -pin  "FRAME:for:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(12)} -pin  "FRAME:for:acc#2" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(13)} -pin  "FRAME:for:acc#2" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(14)} -pin  "FRAME:for:acc#2" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(15)} -pin  "FRAME:for:acc#2" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(11)} -pin  "FRAME:for:acc#2" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {g(0).sva#3(0)} -pin  "FRAME:for:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(1)} -pin  "FRAME:for:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(2)} -pin  "FRAME:for:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(3)} -pin  "FRAME:for:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(4)} -pin  "FRAME:for:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(5)} -pin  "FRAME:for:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(6)} -pin  "FRAME:for:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(7)} -pin  "FRAME:for:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(8)} -pin  "FRAME:for:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(9)} -pin  "FRAME:for:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(10)} -pin  "FRAME:for:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(11)} -pin  "FRAME:for:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(12)} -pin  "FRAME:for:acc#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(13)} -pin  "FRAME:for:acc#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(14)} -pin  "FRAME:for:acc#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(15)} -pin  "FRAME:for:acc#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load inst "ACC1:not#12" "not(10)" "INTERFACE" -attr xrf 5390 -attr oid 524 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "ACC1:not#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "ACC1:not#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "ACC1:not#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "ACC1:not#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "ACC1:not#12" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "ACC1:not#12" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "ACC1:not#12" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "ACC1:not#12" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "ACC1:not#12" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1:not#12" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {ACC1:not#12.itm(0)} -pin  "ACC1:not#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(1)} -pin  "ACC1:not#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(2)} -pin  "ACC1:not#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(3)} -pin  "ACC1:not#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(4)} -pin  "ACC1:not#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(5)} -pin  "ACC1:not#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(6)} -pin  "ACC1:not#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(7)} -pin  "ACC1:not#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(8)} -pin  "ACC1:not#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(9)} -pin  "ACC1:not#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load inst "ACC1:acc#50" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 5391 -attr oid 525 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#50" {A(0)} -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(0)} -pin  "ACC1:acc#50" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(1)} -pin  "ACC1:acc#50" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(2)} -pin  "ACC1:acc#50" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(3)} -pin  "ACC1:acc#50" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(4)} -pin  "ACC1:acc#50" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(5)} -pin  "ACC1:acc#50" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(6)} -pin  "ACC1:acc#50" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(7)} -pin  "ACC1:acc#50" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(8)} -pin  "ACC1:acc#50" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(9)} -pin  "ACC1:acc#50" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {PWR} -pin  "ACC1:acc#50" {B(0)} -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(80)} -pin  "ACC1:acc#50" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(81)} -pin  "ACC1:acc#50" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(82)} -pin  "ACC1:acc#50" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(83)} -pin  "ACC1:acc#50" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(84)} -pin  "ACC1:acc#50" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(85)} -pin  "ACC1:acc#50" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(86)} -pin  "ACC1:acc#50" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(87)} -pin  "ACC1:acc#50" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(88)} -pin  "ACC1:acc#50" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(89)} -pin  "ACC1:acc#50" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {ACC1:acc#50.itm(0)} -pin  "ACC1:acc#50" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(1)} -pin  "ACC1:acc#50" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(2)} -pin  "ACC1:acc#50" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(3)} -pin  "ACC1:acc#50" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(4)} -pin  "ACC1:acc#50" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(5)} -pin  "ACC1:acc#50" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(6)} -pin  "ACC1:acc#50" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(7)} -pin  "ACC1:acc#50" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(8)} -pin  "ACC1:acc#50" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(9)} -pin  "ACC1:acc#50" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(10)} -pin  "ACC1:acc#50" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "ACC1:acc#50" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load inst "FRAME:for:mux#6" "mux(2,16)" "INTERFACE" -attr xrf 5392 -attr oid 526 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#50.itm(1)} -pin  "FRAME:for:mux#6" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(2)} -pin  "FRAME:for:mux#6" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(3)} -pin  "FRAME:for:mux#6" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(4)} -pin  "FRAME:for:mux#6" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(5)} -pin  "FRAME:for:mux#6" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(6)} -pin  "FRAME:for:mux#6" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(7)} -pin  "FRAME:for:mux#6" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(8)} -pin  "FRAME:for:mux#6" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(9)} -pin  "FRAME:for:mux#6" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(10)} -pin  "FRAME:for:mux#6" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "FRAME:for:mux#6" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "FRAME:for:mux#6" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "FRAME:for:mux#6" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "FRAME:for:mux#6" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "FRAME:for:mux#6" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "FRAME:for:mux#6" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {r(2).sva#1(0)} -pin  "FRAME:for:mux#6" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(1)} -pin  "FRAME:for:mux#6" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(2)} -pin  "FRAME:for:mux#6" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(3)} -pin  "FRAME:for:mux#6" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(4)} -pin  "FRAME:for:mux#6" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(5)} -pin  "FRAME:for:mux#6" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(6)} -pin  "FRAME:for:mux#6" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(7)} -pin  "FRAME:for:mux#6" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(8)} -pin  "FRAME:for:mux#6" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(9)} -pin  "FRAME:for:mux#6" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(10)} -pin  "FRAME:for:mux#6" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(11)} -pin  "FRAME:for:mux#6" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(12)} -pin  "FRAME:for:mux#6" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(13)} -pin  "FRAME:for:mux#6" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(14)} -pin  "FRAME:for:mux#6" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(15)} -pin  "FRAME:for:mux#6" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#6" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#6.itm(0)} -pin  "FRAME:for:mux#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(1)} -pin  "FRAME:for:mux#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(2)} -pin  "FRAME:for:mux#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(3)} -pin  "FRAME:for:mux#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(4)} -pin  "FRAME:for:mux#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(5)} -pin  "FRAME:for:mux#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(6)} -pin  "FRAME:for:mux#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(7)} -pin  "FRAME:for:mux#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(8)} -pin  "FRAME:for:mux#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(9)} -pin  "FRAME:for:mux#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(10)} -pin  "FRAME:for:mux#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(11)} -pin  "FRAME:for:mux#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(12)} -pin  "FRAME:for:mux#6" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(13)} -pin  "FRAME:for:mux#6" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(14)} -pin  "FRAME:for:mux#6" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(15)} -pin  "FRAME:for:mux#6" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load inst "regs.operator[]#15:mux" "mux(4,10)" "INTERFACE" -attr xrf 5393 -attr oid 527 -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "regs.operator[]#15:mux" {A1(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "regs.operator[]#15:mux" {A1(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "regs.operator[]#15:mux" {A1(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "regs.operator[]#15:mux" {A1(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "regs.operator[]#15:mux" {A1(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "regs.operator[]#15:mux" {A1(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "regs.operator[]#15:mux" {A1(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "regs.operator[]#15:mux" {A1(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "regs.operator[]#15:mux" {A1(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "regs.operator[]#15:mux" {A1(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "regs.operator[]#15:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "regs.operator[]#15:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "regs.operator[]#15:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "regs.operator[]#15:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "regs.operator[]#15:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "regs.operator[]#15:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "regs.operator[]#15:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "regs.operator[]#15:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "regs.operator[]#15:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "regs.operator[]#15:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "regs.operator[]#15:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "regs.operator[]#15:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "regs.operator[]#15:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "regs.operator[]#15:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "regs.operator[]#15:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "regs.operator[]#15:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "regs.operator[]#15:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "regs.operator[]#15:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "regs.operator[]#15:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "regs.operator[]#15:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#15:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#15:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#15:mux.itm(0)} -pin  "regs.operator[]#15:mux" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(1)} -pin  "regs.operator[]#15:mux" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(2)} -pin  "regs.operator[]#15:mux" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(3)} -pin  "regs.operator[]#15:mux" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(4)} -pin  "regs.operator[]#15:mux" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(5)} -pin  "regs.operator[]#15:mux" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(6)} -pin  "regs.operator[]#15:mux" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(7)} -pin  "regs.operator[]#15:mux" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(8)} -pin  "regs.operator[]#15:mux" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(9)} -pin  "regs.operator[]#15:mux" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load inst "FRAME:for:mul#6" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 5394 -attr oid 528 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#15:mux.itm(0)} -pin  "FRAME:for:mul#6" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(1)} -pin  "FRAME:for:mul#6" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(2)} -pin  "FRAME:for:mul#6" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(3)} -pin  "FRAME:for:mul#6" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(4)} -pin  "FRAME:for:mul#6" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(5)} -pin  "FRAME:for:mul#6" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(6)} -pin  "FRAME:for:mul#6" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(7)} -pin  "FRAME:for:mul#6" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(8)} -pin  "FRAME:for:mul#6" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(9)} -pin  "FRAME:for:mul#6" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:mul#6" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:mul#6" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:mul#6" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:mul#6" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:mul#6" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:mul#6" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:mul#6" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:mul#6" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:mul#6" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:mul#6" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:mul#6" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load inst "FRAME:for:acc#10" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 5395 -attr oid 529 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:acc#10} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#6.itm(0)} -pin  "FRAME:for:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(1)} -pin  "FRAME:for:acc#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(2)} -pin  "FRAME:for:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(3)} -pin  "FRAME:for:acc#10" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(4)} -pin  "FRAME:for:acc#10" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(5)} -pin  "FRAME:for:acc#10" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(6)} -pin  "FRAME:for:acc#10" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(7)} -pin  "FRAME:for:acc#10" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(8)} -pin  "FRAME:for:acc#10" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(9)} -pin  "FRAME:for:acc#10" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(10)} -pin  "FRAME:for:acc#10" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(11)} -pin  "FRAME:for:acc#10" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(12)} -pin  "FRAME:for:acc#10" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(13)} -pin  "FRAME:for:acc#10" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(14)} -pin  "FRAME:for:acc#10" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(15)} -pin  "FRAME:for:acc#10" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:acc#10" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:acc#10" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:acc#10" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:acc#10" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:acc#10" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:acc#10" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:acc#10" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:acc#10" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:acc#10" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:acc#10" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:acc#10" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {r(2).sva#3(0)} -pin  "FRAME:for:acc#10" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(1)} -pin  "FRAME:for:acc#10" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(2)} -pin  "FRAME:for:acc#10" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(3)} -pin  "FRAME:for:acc#10" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(4)} -pin  "FRAME:for:acc#10" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(5)} -pin  "FRAME:for:acc#10" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(6)} -pin  "FRAME:for:acc#10" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(7)} -pin  "FRAME:for:acc#10" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(8)} -pin  "FRAME:for:acc#10" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(9)} -pin  "FRAME:for:acc#10" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(10)} -pin  "FRAME:for:acc#10" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(11)} -pin  "FRAME:for:acc#10" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(12)} -pin  "FRAME:for:acc#10" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(13)} -pin  "FRAME:for:acc#10" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(14)} -pin  "FRAME:for:acc#10" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(15)} -pin  "FRAME:for:acc#10" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load inst "ACC1:not" "not(10)" "INTERFACE" -attr xrf 5396 -attr oid 530 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "ACC1:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "ACC1:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "ACC1:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "ACC1:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "ACC1:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "ACC1:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "ACC1:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "ACC1:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "ACC1:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load inst "ACC1:acc#48" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 5397 -attr oid 531 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#48" {A(0)} -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:acc#48" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:acc#48" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:acc#48" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:acc#48" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:acc#48" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:acc#48" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:acc#48" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:acc#48" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:acc#48" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:acc#48" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {PWR} -pin  "ACC1:acc#48" {B(0)} -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(20)} -pin  "ACC1:acc#48" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(21)} -pin  "ACC1:acc#48" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(22)} -pin  "ACC1:acc#48" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(23)} -pin  "ACC1:acc#48" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(24)} -pin  "ACC1:acc#48" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(25)} -pin  "ACC1:acc#48" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(26)} -pin  "ACC1:acc#48" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(27)} -pin  "ACC1:acc#48" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(28)} -pin  "ACC1:acc#48" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(29)} -pin  "ACC1:acc#48" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {ACC1:acc#48.itm(0)} -pin  "ACC1:acc#48" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(1)} -pin  "ACC1:acc#48" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(2)} -pin  "ACC1:acc#48" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(3)} -pin  "ACC1:acc#48" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(4)} -pin  "ACC1:acc#48" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(5)} -pin  "ACC1:acc#48" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(6)} -pin  "ACC1:acc#48" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(7)} -pin  "ACC1:acc#48" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(8)} -pin  "ACC1:acc#48" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(9)} -pin  "ACC1:acc#48" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(10)} -pin  "ACC1:acc#48" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "ACC1:acc#48" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load inst "FRAME:for:mux#5" "mux(2,16)" "INTERFACE" -attr xrf 5398 -attr oid 532 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#48.itm(1)} -pin  "FRAME:for:mux#5" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(2)} -pin  "FRAME:for:mux#5" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(3)} -pin  "FRAME:for:mux#5" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(4)} -pin  "FRAME:for:mux#5" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(5)} -pin  "FRAME:for:mux#5" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(6)} -pin  "FRAME:for:mux#5" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(7)} -pin  "FRAME:for:mux#5" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(8)} -pin  "FRAME:for:mux#5" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(9)} -pin  "FRAME:for:mux#5" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(10)} -pin  "FRAME:for:mux#5" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#5" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#5" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#5" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#5" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#5" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#5" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {r(0).sva#1(0)} -pin  "FRAME:for:mux#5" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(1)} -pin  "FRAME:for:mux#5" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(2)} -pin  "FRAME:for:mux#5" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(3)} -pin  "FRAME:for:mux#5" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(4)} -pin  "FRAME:for:mux#5" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(5)} -pin  "FRAME:for:mux#5" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(6)} -pin  "FRAME:for:mux#5" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(7)} -pin  "FRAME:for:mux#5" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(8)} -pin  "FRAME:for:mux#5" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(9)} -pin  "FRAME:for:mux#5" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(10)} -pin  "FRAME:for:mux#5" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(11)} -pin  "FRAME:for:mux#5" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(12)} -pin  "FRAME:for:mux#5" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(13)} -pin  "FRAME:for:mux#5" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(14)} -pin  "FRAME:for:mux#5" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(15)} -pin  "FRAME:for:mux#5" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#5" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#5.itm(0)} -pin  "FRAME:for:mux#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(1)} -pin  "FRAME:for:mux#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(2)} -pin  "FRAME:for:mux#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(3)} -pin  "FRAME:for:mux#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(4)} -pin  "FRAME:for:mux#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(5)} -pin  "FRAME:for:mux#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(6)} -pin  "FRAME:for:mux#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(7)} -pin  "FRAME:for:mux#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(8)} -pin  "FRAME:for:mux#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(9)} -pin  "FRAME:for:mux#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(10)} -pin  "FRAME:for:mux#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(11)} -pin  "FRAME:for:mux#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(12)} -pin  "FRAME:for:mux#5" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(13)} -pin  "FRAME:for:mux#5" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(14)} -pin  "FRAME:for:mux#5" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(15)} -pin  "FRAME:for:mux#5" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load inst "regs.operator[]#9:mux" "mux(4,10)" "INTERFACE" -attr xrf 5399 -attr oid 533 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "regs.operator[]#9:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "regs.operator[]#9:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "regs.operator[]#9:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "regs.operator[]#9:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "regs.operator[]#9:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "regs.operator[]#9:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "regs.operator[]#9:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "regs.operator[]#9:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "regs.operator[]#9:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "regs.operator[]#9:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "regs.operator[]#9:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "regs.operator[]#9:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "regs.operator[]#9:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "regs.operator[]#9:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "regs.operator[]#9:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "regs.operator[]#9:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "regs.operator[]#9:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "regs.operator[]#9:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "regs.operator[]#9:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "regs.operator[]#9:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "regs.operator[]#9:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "regs.operator[]#9:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "regs.operator[]#9:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "regs.operator[]#9:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "regs.operator[]#9:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "regs.operator[]#9:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "regs.operator[]#9:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "regs.operator[]#9:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "regs.operator[]#9:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "regs.operator[]#9:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#9:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#9:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#9:mux.itm(0)} -pin  "regs.operator[]#9:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(1)} -pin  "regs.operator[]#9:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(2)} -pin  "regs.operator[]#9:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(3)} -pin  "regs.operator[]#9:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(4)} -pin  "regs.operator[]#9:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(5)} -pin  "regs.operator[]#9:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(6)} -pin  "regs.operator[]#9:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(7)} -pin  "regs.operator[]#9:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(8)} -pin  "regs.operator[]#9:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(9)} -pin  "regs.operator[]#9:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load inst "FRAME:for:mul" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 5400 -attr oid 534 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#9:mux.itm(0)} -pin  "FRAME:for:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(1)} -pin  "FRAME:for:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(2)} -pin  "FRAME:for:mul" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(3)} -pin  "FRAME:for:mul" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(4)} -pin  "FRAME:for:mul" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(5)} -pin  "FRAME:for:mul" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(6)} -pin  "FRAME:for:mul" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(7)} -pin  "FRAME:for:mul" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(8)} -pin  "FRAME:for:mul" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(9)} -pin  "FRAME:for:mul" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {PWR} -pin  "FRAME:for:mul" {B(1)} -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(11)} -pin  "FRAME:for:mul" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load inst "FRAME:for:acc#1" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 5401 -attr oid 535 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#5.itm(0)} -pin  "FRAME:for:acc#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(1)} -pin  "FRAME:for:acc#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(2)} -pin  "FRAME:for:acc#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(3)} -pin  "FRAME:for:acc#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(4)} -pin  "FRAME:for:acc#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(5)} -pin  "FRAME:for:acc#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(6)} -pin  "FRAME:for:acc#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(7)} -pin  "FRAME:for:acc#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(8)} -pin  "FRAME:for:acc#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(9)} -pin  "FRAME:for:acc#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(10)} -pin  "FRAME:for:acc#1" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(11)} -pin  "FRAME:for:acc#1" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(12)} -pin  "FRAME:for:acc#1" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(13)} -pin  "FRAME:for:acc#1" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(14)} -pin  "FRAME:for:acc#1" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(15)} -pin  "FRAME:for:acc#1" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:acc#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:acc#1" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:acc#1" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:acc#1" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:acc#1" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:acc#1" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:acc#1" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:acc#1" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:acc#1" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:acc#1" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:acc#1" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(11)} -pin  "FRAME:for:acc#1" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {r(0).sva#3(0)} -pin  "FRAME:for:acc#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(1)} -pin  "FRAME:for:acc#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(2)} -pin  "FRAME:for:acc#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(3)} -pin  "FRAME:for:acc#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(4)} -pin  "FRAME:for:acc#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(5)} -pin  "FRAME:for:acc#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(6)} -pin  "FRAME:for:acc#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(7)} -pin  "FRAME:for:acc#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(8)} -pin  "FRAME:for:acc#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(9)} -pin  "FRAME:for:acc#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(10)} -pin  "FRAME:for:acc#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(11)} -pin  "FRAME:for:acc#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(12)} -pin  "FRAME:for:acc#1" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(13)} -pin  "FRAME:for:acc#1" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(14)} -pin  "FRAME:for:acc#1" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(15)} -pin  "FRAME:for:acc#1" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load inst "FRAME:for:nor" "nor(2,1)" "INTERFACE" -attr xrf 5402 -attr oid 536 -attr @path {/sobel/sobel:core/FRAME:for:nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:nor" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#3.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nor" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#4.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:nor" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load inst "FRAME:for:not#8" "not(1)" "INTERFACE" -attr xrf 5403 -attr oid 537 -attr @path {/sobel/sobel:core/FRAME:for:not#8} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#8" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#10.itm}
+load net {FRAME:for:not#8.itm} -pin  "FRAME:for:not#8" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#8.itm}
+load inst "FRAME:for:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 5404 -attr oid 538 -attr @path {/sobel/sobel:core/FRAME:for:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {FRAME:for:not#8.itm} -pin  "FRAME:for:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#8.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#5.itm}
+load net {FRAME:for:nand#1.itm} -pin  "FRAME:for:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#1.itm}
+load inst "FRAME:for:or#4" "or(2,1)" "INTERFACE" -attr xrf 5405 -attr oid 539 -attr @path {/sobel/sobel:core/FRAME:for:or#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {FRAME:for:nand#1.itm} -pin  "FRAME:for:or#4" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#1.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or#4" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:or#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#4.itm}
+load inst "FRAME:for:not#5" "not(1)" "INTERFACE" -attr xrf 5406 -attr oid 540 -attr @path {/sobel/sobel:core/FRAME:for:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#5" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#8.itm}
+load net {FRAME:for:not#5.itm} -pin  "FRAME:for:not#5" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#5.itm}
+load inst "FRAME:for:nand" "nand(2,1)" "INTERFACE" -attr xrf 5407 -attr oid 541 -attr @path {/sobel/sobel:core/FRAME:for:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#6.itm}
+load net {FRAME:for:not#5.itm} -pin  "FRAME:for:nand" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#5.itm}
+load net {FRAME:for:nand.itm} -pin  "FRAME:for:nand" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand.itm}
+load inst "FRAME:for:not#2" "not(1)" "INTERFACE" -attr xrf 5408 -attr oid 542 -attr @path {/sobel/sobel:core/FRAME:for:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:not#2" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#7.itm}
+load net {FRAME:for:not#2.itm} -pin  "FRAME:for:not#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#2.itm}
+load inst "FRAME:for:and#3" "and(2,1)" "INTERFACE" -attr xrf 5409 -attr oid 543 -attr @path {/sobel/sobel:core/FRAME:for:and#3} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#9.itm}
+load net {FRAME:for:not#2.itm} -pin  "FRAME:for:and#3" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#2.itm}
+load net {FRAME:for:and#3.itm} -pin  "FRAME:for:and#3" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#3.itm}
+load inst "FRAME:for:or#3" "or(3,1)" "INTERFACE" -attr xrf 5410 -attr oid 544 -attr @path {/sobel/sobel:core/FRAME:for:or#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,3)"
+load net {FRAME:for:nand.itm} -pin  "FRAME:for:or#3" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or#3" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:and#3.itm} -pin  "FRAME:for:or#3" {A2(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#3.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:or#3" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#3.itm}
+load inst "nor" "nor(2,1)" "INTERFACE" -attr vt c -attr @path {/sobel/sobel:core/nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "nor" {A0(0)} -attr vt c -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {exit:FRAME#1.sva} -pin  "nor" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {and.dcpl} -pin  "nor" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/and.dcpl}
+### END MODULE 
+
+module new "sobel" "orig"
+load portBus {vin:rsc.z(89:0)} input 90 {vin:rsc.z(89)} {vin:rsc.z(88)} {vin:rsc.z(87)} {vin:rsc.z(86)} {vin:rsc.z(85)} {vin:rsc.z(84)} {vin:rsc.z(83)} {vin:rsc.z(82)} {vin:rsc.z(81)} {vin:rsc.z(80)} {vin:rsc.z(79)} {vin:rsc.z(78)} {vin:rsc.z(77)} {vin:rsc.z(76)} {vin:rsc.z(75)} {vin:rsc.z(74)} {vin:rsc.z(73)} {vin:rsc.z(72)} {vin:rsc.z(71)} {vin:rsc.z(70)} {vin:rsc.z(69)} {vin:rsc.z(68)} {vin:rsc.z(67)} {vin:rsc.z(66)} {vin:rsc.z(65)} {vin:rsc.z(64)} {vin:rsc.z(63)} {vin:rsc.z(62)} {vin:rsc.z(61)} {vin:rsc.z(60)} {vin:rsc.z(59)} {vin:rsc.z(58)} {vin:rsc.z(57)} {vin:rsc.z(56)} {vin:rsc.z(55)} {vin:rsc.z(54)} {vin:rsc.z(53)} {vin:rsc.z(52)} {vin:rsc.z(51)} {vin:rsc.z(50)} {vin:rsc.z(49)} {vin:rsc.z(48)} {vin:rsc.z(47)} {vin:rsc.z(46)} {vin:rsc.z(45)} {vin:rsc.z(44)} {vin:rsc.z(43)} {vin:rsc.z(42)} {vin:rsc.z(41)} {vin:rsc.z(40)} {vin:rsc.z(39)} {vin:rsc.z(38)} {vin:rsc.z(37)} {vin:rsc.z(36)} {vin:rsc.z(35)} {vin:rsc.z(34)} {vin:rsc.z(33)} {vin:rsc.z(32)} {vin:rsc.z(31)} {vin:rsc.z(30)} {vin:rsc.z(29)} {vin:rsc.z(28)} {vin:rsc.z(27)} {vin:rsc.z(26)} {vin:rsc.z(25)} {vin:rsc.z(24)} {vin:rsc.z(23)} {vin:rsc.z(22)} {vin:rsc.z(21)} {vin:rsc.z(20)} {vin:rsc.z(19)} {vin:rsc.z(18)} {vin:rsc.z(17)} {vin:rsc.z(16)} {vin:rsc.z(15)} {vin:rsc.z(14)} {vin:rsc.z(13)} {vin:rsc.z(12)} {vin:rsc.z(11)} {vin:rsc.z(10)} {vin:rsc.z(9)} {vin:rsc.z(8)} {vin:rsc.z(7)} {vin:rsc.z(6)} {vin:rsc.z(5)} {vin:rsc.z(4)} {vin:rsc.z(3)} {vin:rsc.z(2)} {vin:rsc.z(1)} {vin:rsc.z(0)} -attr xrf 5411 -attr oid 545 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load portBus {vout:rsc.z(29:0)} output 30 {vout:rsc.z(29)} {vout:rsc.z(28)} {vout:rsc.z(27)} {vout:rsc.z(26)} {vout:rsc.z(25)} {vout:rsc.z(24)} {vout:rsc.z(23)} {vout:rsc.z(22)} {vout:rsc.z(21)} {vout:rsc.z(20)} {vout:rsc.z(19)} {vout:rsc.z(18)} {vout:rsc.z(17)} {vout:rsc.z(16)} {vout:rsc.z(15)} {vout:rsc.z(14)} {vout:rsc.z(13)} {vout:rsc.z(12)} {vout:rsc.z(11)} {vout:rsc.z(10)} {vout:rsc.z(9)} {vout:rsc.z(8)} {vout:rsc.z(7)} {vout:rsc.z(6)} {vout:rsc.z(5)} {vout:rsc.z(4)} {vout:rsc.z(3)} {vout:rsc.z(2)} {vout:rsc.z(1)} {vout:rsc.z(0)} -attr xrf 5412 -attr oid 546 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load port {clk} input -attr xrf 5413 -attr oid 547 -attr vt d -attr @path {/sobel/clk}
+load port {en} input -attr xrf 5414 -attr oid 548 -attr vt d -attr @path {/sobel/en}
+load port {arst_n} input -attr xrf 5415 -attr oid 549 -attr vt d -attr @path {/sobel/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(89:0)} output 90 {d(89)} {d(88)} {d(87)} {d(86)} {d(85)} {d(84)} {d(83)} {d(82)} {d(81)} {d(80)} {d(79)} {d(78)} {d(77)} {d(76)} {d(75)} {d(74)} {d(73)} {d(72)} {d(71)} {d(70)} {d(69)} {d(68)} {d(67)} {d(66)} {d(65)} {d(64)} {d(63)} {d(62)} {d(61)} {d(60)} {d(59)} {d(58)} {d(57)} {d(56)} {d(55)} {d(54)} {d(53)} {d(52)} {d(51)} {d(50)} {d(49)} {d(48)} {d(47)} {d(46)} {d(45)} {d(44)} {d(43)} {d(42)} {d(41)} {d(40)} {d(39)} {d(38)} {d(37)} {d(36)} {d(35)} {d(34)} {d(33)} {d(32)} {d(31)} {d(30)} {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(89:0)} input 90 {z(89)} {z(88)} {z(87)} {z(86)} {z(85)} {z(84)} {z(83)} {z(82)} {z(81)} {z(80)} {z(79)} {z(78)} {z(77)} {z(76)} {z(75)} {z(74)} {z(73)} {z(72)} {z(71)} {z(70)} {z(69)} {z(68)} {z(67)} {z(66)} {z(65)} {z(64)} {z(63)} {z(62)} {z(61)} {z(60)} {z(59)} {z(58)} {z(57)} {z(56)} {z(55)} {z(54)} {z(53)} {z(52)} {z(51)} {z(50)} {z(49)} {z(48)} {z(47)} {z(46)} {z(45)} {z(44)} {z(43)} {z(42)} {z(41)} {z(40)} {z(39)} {z(38)} {z(37)} {z(36)} {z(35)} {z(34)} {z(33)} {z(32)} {z(31)} {z(30)} {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(29:0)} input 30 {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(29:0)} output 30 {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "sobel:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} \
+     portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} \
+
+load net {vin:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d#1} 90 {vin:rsc:mgc_in_wire.d#1(0)} {vin:rsc:mgc_in_wire.d#1(1)} {vin:rsc:mgc_in_wire.d#1(2)} {vin:rsc:mgc_in_wire.d#1(3)} {vin:rsc:mgc_in_wire.d#1(4)} {vin:rsc:mgc_in_wire.d#1(5)} {vin:rsc:mgc_in_wire.d#1(6)} {vin:rsc:mgc_in_wire.d#1(7)} {vin:rsc:mgc_in_wire.d#1(8)} {vin:rsc:mgc_in_wire.d#1(9)} {vin:rsc:mgc_in_wire.d#1(10)} {vin:rsc:mgc_in_wire.d#1(11)} {vin:rsc:mgc_in_wire.d#1(12)} {vin:rsc:mgc_in_wire.d#1(13)} {vin:rsc:mgc_in_wire.d#1(14)} {vin:rsc:mgc_in_wire.d#1(15)} {vin:rsc:mgc_in_wire.d#1(16)} {vin:rsc:mgc_in_wire.d#1(17)} {vin:rsc:mgc_in_wire.d#1(18)} {vin:rsc:mgc_in_wire.d#1(19)} {vin:rsc:mgc_in_wire.d#1(20)} {vin:rsc:mgc_in_wire.d#1(21)} {vin:rsc:mgc_in_wire.d#1(22)} {vin:rsc:mgc_in_wire.d#1(23)} {vin:rsc:mgc_in_wire.d#1(24)} {vin:rsc:mgc_in_wire.d#1(25)} {vin:rsc:mgc_in_wire.d#1(26)} {vin:rsc:mgc_in_wire.d#1(27)} {vin:rsc:mgc_in_wire.d#1(28)} {vin:rsc:mgc_in_wire.d#1(29)} {vin:rsc:mgc_in_wire.d#1(30)} {vin:rsc:mgc_in_wire.d#1(31)} {vin:rsc:mgc_in_wire.d#1(32)} {vin:rsc:mgc_in_wire.d#1(33)} {vin:rsc:mgc_in_wire.d#1(34)} {vin:rsc:mgc_in_wire.d#1(35)} {vin:rsc:mgc_in_wire.d#1(36)} {vin:rsc:mgc_in_wire.d#1(37)} {vin:rsc:mgc_in_wire.d#1(38)} {vin:rsc:mgc_in_wire.d#1(39)} {vin:rsc:mgc_in_wire.d#1(40)} {vin:rsc:mgc_in_wire.d#1(41)} {vin:rsc:mgc_in_wire.d#1(42)} {vin:rsc:mgc_in_wire.d#1(43)} {vin:rsc:mgc_in_wire.d#1(44)} {vin:rsc:mgc_in_wire.d#1(45)} {vin:rsc:mgc_in_wire.d#1(46)} {vin:rsc:mgc_in_wire.d#1(47)} {vin:rsc:mgc_in_wire.d#1(48)} {vin:rsc:mgc_in_wire.d#1(49)} {vin:rsc:mgc_in_wire.d#1(50)} {vin:rsc:mgc_in_wire.d#1(51)} {vin:rsc:mgc_in_wire.d#1(52)} {vin:rsc:mgc_in_wire.d#1(53)} {vin:rsc:mgc_in_wire.d#1(54)} {vin:rsc:mgc_in_wire.d#1(55)} {vin:rsc:mgc_in_wire.d#1(56)} {vin:rsc:mgc_in_wire.d#1(57)} {vin:rsc:mgc_in_wire.d#1(58)} {vin:rsc:mgc_in_wire.d#1(59)} {vin:rsc:mgc_in_wire.d#1(60)} {vin:rsc:mgc_in_wire.d#1(61)} {vin:rsc:mgc_in_wire.d#1(62)} {vin:rsc:mgc_in_wire.d#1(63)} {vin:rsc:mgc_in_wire.d#1(64)} {vin:rsc:mgc_in_wire.d#1(65)} {vin:rsc:mgc_in_wire.d#1(66)} {vin:rsc:mgc_in_wire.d#1(67)} {vin:rsc:mgc_in_wire.d#1(68)} {vin:rsc:mgc_in_wire.d#1(69)} {vin:rsc:mgc_in_wire.d#1(70)} {vin:rsc:mgc_in_wire.d#1(71)} {vin:rsc:mgc_in_wire.d#1(72)} {vin:rsc:mgc_in_wire.d#1(73)} {vin:rsc:mgc_in_wire.d#1(74)} {vin:rsc:mgc_in_wire.d#1(75)} {vin:rsc:mgc_in_wire.d#1(76)} {vin:rsc:mgc_in_wire.d#1(77)} {vin:rsc:mgc_in_wire.d#1(78)} {vin:rsc:mgc_in_wire.d#1(79)} {vin:rsc:mgc_in_wire.d#1(80)} {vin:rsc:mgc_in_wire.d#1(81)} {vin:rsc:mgc_in_wire.d#1(82)} {vin:rsc:mgc_in_wire.d#1(83)} {vin:rsc:mgc_in_wire.d#1(84)} {vin:rsc:mgc_in_wire.d#1(85)} {vin:rsc:mgc_in_wire.d#1(86)} {vin:rsc:mgc_in_wire.d#1(87)} {vin:rsc:mgc_in_wire.d#1(88)} {vin:rsc:mgc_in_wire.d#1(89)} -attr xrf 5416 -attr oid 550 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -attr vt d
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+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d#1} 30 {vout:rsc:mgc_out_stdreg.d#1(0)} {vout:rsc:mgc_out_stdreg.d#1(1)} {vout:rsc:mgc_out_stdreg.d#1(2)} {vout:rsc:mgc_out_stdreg.d#1(3)} {vout:rsc:mgc_out_stdreg.d#1(4)} {vout:rsc:mgc_out_stdreg.d#1(5)} {vout:rsc:mgc_out_stdreg.d#1(6)} {vout:rsc:mgc_out_stdreg.d#1(7)} {vout:rsc:mgc_out_stdreg.d#1(8)} {vout:rsc:mgc_out_stdreg.d#1(9)} {vout:rsc:mgc_out_stdreg.d#1(10)} {vout:rsc:mgc_out_stdreg.d#1(11)} {vout:rsc:mgc_out_stdreg.d#1(12)} {vout:rsc:mgc_out_stdreg.d#1(13)} {vout:rsc:mgc_out_stdreg.d#1(14)} {vout:rsc:mgc_out_stdreg.d#1(15)} {vout:rsc:mgc_out_stdreg.d#1(16)} {vout:rsc:mgc_out_stdreg.d#1(17)} {vout:rsc:mgc_out_stdreg.d#1(18)} {vout:rsc:mgc_out_stdreg.d#1(19)} {vout:rsc:mgc_out_stdreg.d#1(20)} {vout:rsc:mgc_out_stdreg.d#1(21)} {vout:rsc:mgc_out_stdreg.d#1(22)} {vout:rsc:mgc_out_stdreg.d#1(23)} {vout:rsc:mgc_out_stdreg.d#1(24)} {vout:rsc:mgc_out_stdreg.d#1(25)} {vout:rsc:mgc_out_stdreg.d#1(26)} {vout:rsc:mgc_out_stdreg.d#1(27)} {vout:rsc:mgc_out_stdreg.d#1(28)} {vout:rsc:mgc_out_stdreg.d#1(29)} -attr xrf 5417 -attr oid 551 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -attr vt d
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+load net {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 5418 -attr oid 552 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(0)} -port {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -port {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -port {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -port {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -port {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -port {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -port {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -port {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -port {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -port {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -port {vin:rsc.z(10)} -attr vt d
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+load net {vin:rsc.z(55)} -port {vin:rsc.z(55)} -attr vt d
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+load net {vin:rsc.z(58)} -port {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -port {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -port {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -port {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -port {vin:rsc.z(62)} -attr vt d
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+load net {vin:rsc.z(64)} -port {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -port {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -port {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -port {vin:rsc.z(67)} -attr vt d
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+load net {vin:rsc.z(89)} -port {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 5419 -attr oid 553 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vout:rsc.z(0)} -attr vt d
+load net {vout:rsc.z(1)} -attr vt d
+load net {vout:rsc.z(2)} -attr vt d
+load net {vout:rsc.z(3)} -attr vt d
+load net {vout:rsc.z(4)} -attr vt d
+load net {vout:rsc.z(5)} -attr vt d
+load net {vout:rsc.z(6)} -attr vt d
+load net {vout:rsc.z(7)} -attr vt d
+load net {vout:rsc.z(8)} -attr vt d
+load net {vout:rsc.z(9)} -attr vt d
+load net {vout:rsc.z(10)} -attr vt d
+load net {vout:rsc.z(11)} -attr vt d
+load net {vout:rsc.z(12)} -attr vt d
+load net {vout:rsc.z(13)} -attr vt d
+load net {vout:rsc.z(14)} -attr vt d
+load net {vout:rsc.z(15)} -attr vt d
+load net {vout:rsc.z(16)} -attr vt d
+load net {vout:rsc.z(17)} -attr vt d
+load net {vout:rsc.z(18)} -attr vt d
+load net {vout:rsc.z(19)} -attr vt d
+load net {vout:rsc.z(20)} -attr vt d
+load net {vout:rsc.z(21)} -attr vt d
+load net {vout:rsc.z(22)} -attr vt d
+load net {vout:rsc.z(23)} -attr vt d
+load net {vout:rsc.z(24)} -attr vt d
+load net {vout:rsc.z(25)} -attr vt d
+load net {vout:rsc.z(26)} -attr vt d
+load net {vout:rsc.z(27)} -attr vt d
+load net {vout:rsc.z(28)} -attr vt d
+load net {vout:rsc.z(29)} -attr vt d
+load netBundle {vout:rsc.z} 30 {vout:rsc.z(0)} {vout:rsc.z(1)} {vout:rsc.z(2)} {vout:rsc.z(3)} {vout:rsc.z(4)} {vout:rsc.z(5)} {vout:rsc.z(6)} {vout:rsc.z(7)} {vout:rsc.z(8)} {vout:rsc.z(9)} {vout:rsc.z(10)} {vout:rsc.z(11)} {vout:rsc.z(12)} {vout:rsc.z(13)} {vout:rsc.z(14)} {vout:rsc.z(15)} {vout:rsc.z(16)} {vout:rsc.z(17)} {vout:rsc.z(18)} {vout:rsc.z(19)} {vout:rsc.z(20)} {vout:rsc.z(21)} {vout:rsc.z(22)} {vout:rsc.z(23)} {vout:rsc.z(24)} {vout:rsc.z(25)} {vout:rsc.z(26)} {vout:rsc.z(27)} {vout:rsc.z(28)} {vout:rsc.z(29)} -attr xrf 5420 -attr oid 554 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(0)} -port {vout:rsc.z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -port {vout:rsc.z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -port {vout:rsc.z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -port {vout:rsc.z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -port {vout:rsc.z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -port {vout:rsc.z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -port {vout:rsc.z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -port {vout:rsc.z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -port {vout:rsc.z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -port {vout:rsc.z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -port {vout:rsc.z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -port {vout:rsc.z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -port {vout:rsc.z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -port {vout:rsc.z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -port {vout:rsc.z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -port {vout:rsc.z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -port {vout:rsc.z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -port {vout:rsc.z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -port {vout:rsc.z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -port {vout:rsc.z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -port {vout:rsc.z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -port {vout:rsc.z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -port {vout:rsc.z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -port {vout:rsc.z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -port {vout:rsc.z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -port {vout:rsc.z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -port {vout:rsc.z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -port {vout:rsc.z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -port {vout:rsc.z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -port {vout:rsc.z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {clk} -attr xrf 5421 -attr oid 555
+load net {clk} -port {clk} -attr xrf 5422 -attr oid 556
+load net {en} -attr xrf 5423 -attr oid 557
+load net {en} -port {en} -attr xrf 5424 -attr oid 558
+load net {arst_n} -attr xrf 5425 -attr oid 559
+load net {arst_n} -port {arst_n} -attr xrf 5426 -attr oid 560
+load inst "sobel:core:inst" "sobel:core" "orig" -attr xrf 5427 -attr oid 561 -attr vt dc -attr @path {/sobel/sobel:core:inst} -attr area 5150.730536 -attr delay 15.796511 -attr hier "/sobel/sobel:core" -pg 1 -lvl 3
+load net {clk} -pin  "sobel:core:inst" {clk#1} -attr xrf 5428 -attr oid 562 -attr @path {/sobel/clk}
+load net {en} -pin  "sobel:core:inst" {en#1} -attr xrf 5429 -attr oid 563 -attr @path {/sobel/en}
+load net {arst_n} -pin  "sobel:core:inst" {arst_n#1} -attr xrf 5430 -attr oid 564 -attr @path {/sobel/arst_n}
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(8)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(9)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(10)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(11)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(12)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(13)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(14)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(15)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(16)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(17)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(18)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(19)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(20)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(21)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(22)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(23)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(24)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(25)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(26)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(27)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(28)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(29)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(30)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(31)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(32)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(33)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(34)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(35)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(36)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(37)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(38)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(39)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(40)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(41)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(42)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(43)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(44)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(45)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(46)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(47)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(48)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(49)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(50)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(51)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(52)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(53)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(54)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(55)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(56)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(57)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(58)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(59)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(60)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(61)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(62)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(63)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(64)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(65)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(66)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(67)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(68)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(69)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(70)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(71)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(72)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(73)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(74)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(75)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(76)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(77)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(78)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(79)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(80)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(81)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(82)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(83)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(84)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(85)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(86)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(87)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(88)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(89)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(8)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(9)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(10)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(11)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(12)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(13)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(14)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(15)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(16)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(17)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(18)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(19)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(20)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(21)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(22)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(23)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(24)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(25)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(26)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(27)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(28)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(29)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load inst "vin:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" -attr xrf 5431 -attr oid 565 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,90)" -pg 1 -lvl 1
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "vin:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "vin:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "vin:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "vin:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "vin:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "vin:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "vin:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "vin:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "vin:rsc:mgc_in_wire" {d(8)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "vin:rsc:mgc_in_wire" {d(9)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "vin:rsc:mgc_in_wire" {d(10)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "vin:rsc:mgc_in_wire" {d(11)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "vin:rsc:mgc_in_wire" {d(12)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "vin:rsc:mgc_in_wire" {d(13)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "vin:rsc:mgc_in_wire" {d(14)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "vin:rsc:mgc_in_wire" {d(15)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "vin:rsc:mgc_in_wire" {d(16)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "vin:rsc:mgc_in_wire" {d(17)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "vin:rsc:mgc_in_wire" {d(18)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "vin:rsc:mgc_in_wire" {d(19)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "vin:rsc:mgc_in_wire" {d(20)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "vin:rsc:mgc_in_wire" {d(21)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "vin:rsc:mgc_in_wire" {d(22)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "vin:rsc:mgc_in_wire" {d(23)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "vin:rsc:mgc_in_wire" {d(24)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "vin:rsc:mgc_in_wire" {d(25)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "vin:rsc:mgc_in_wire" {d(26)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "vin:rsc:mgc_in_wire" {d(27)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "vin:rsc:mgc_in_wire" {d(28)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "vin:rsc:mgc_in_wire" {d(29)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "vin:rsc:mgc_in_wire" {d(30)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "vin:rsc:mgc_in_wire" {d(31)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "vin:rsc:mgc_in_wire" {d(32)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "vin:rsc:mgc_in_wire" {d(33)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "vin:rsc:mgc_in_wire" {d(34)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "vin:rsc:mgc_in_wire" {d(35)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "vin:rsc:mgc_in_wire" {d(36)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "vin:rsc:mgc_in_wire" {d(37)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "vin:rsc:mgc_in_wire" {d(38)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "vin:rsc:mgc_in_wire" {d(39)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "vin:rsc:mgc_in_wire" {d(40)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "vin:rsc:mgc_in_wire" {d(41)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "vin:rsc:mgc_in_wire" {d(42)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "vin:rsc:mgc_in_wire" {d(43)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "vin:rsc:mgc_in_wire" {d(44)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "vin:rsc:mgc_in_wire" {d(45)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "vin:rsc:mgc_in_wire" {d(46)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "vin:rsc:mgc_in_wire" {d(47)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "vin:rsc:mgc_in_wire" {d(48)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "vin:rsc:mgc_in_wire" {d(49)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "vin:rsc:mgc_in_wire" {d(50)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "vin:rsc:mgc_in_wire" {d(51)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "vin:rsc:mgc_in_wire" {d(52)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "vin:rsc:mgc_in_wire" {d(53)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "vin:rsc:mgc_in_wire" {d(54)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "vin:rsc:mgc_in_wire" {d(55)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "vin:rsc:mgc_in_wire" {d(56)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "vin:rsc:mgc_in_wire" {d(57)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "vin:rsc:mgc_in_wire" {d(58)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "vin:rsc:mgc_in_wire" {d(59)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "vin:rsc:mgc_in_wire" {d(60)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "vin:rsc:mgc_in_wire" {d(61)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "vin:rsc:mgc_in_wire" {d(62)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "vin:rsc:mgc_in_wire" {d(63)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "vin:rsc:mgc_in_wire" {d(64)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "vin:rsc:mgc_in_wire" {d(65)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "vin:rsc:mgc_in_wire" {d(66)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "vin:rsc:mgc_in_wire" {d(67)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "vin:rsc:mgc_in_wire" {d(68)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "vin:rsc:mgc_in_wire" {d(69)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "vin:rsc:mgc_in_wire" {d(70)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "vin:rsc:mgc_in_wire" {d(71)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "vin:rsc:mgc_in_wire" {d(72)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "vin:rsc:mgc_in_wire" {d(73)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "vin:rsc:mgc_in_wire" {d(74)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "vin:rsc:mgc_in_wire" {d(75)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "vin:rsc:mgc_in_wire" {d(76)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "vin:rsc:mgc_in_wire" {d(77)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "vin:rsc:mgc_in_wire" {d(78)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "vin:rsc:mgc_in_wire" {d(79)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "vin:rsc:mgc_in_wire" {d(80)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "vin:rsc:mgc_in_wire" {d(81)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "vin:rsc:mgc_in_wire" {d(82)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "vin:rsc:mgc_in_wire" {d(83)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "vin:rsc:mgc_in_wire" {d(84)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "vin:rsc:mgc_in_wire" {d(85)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "vin:rsc:mgc_in_wire" {d(86)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "vin:rsc:mgc_in_wire" {d(87)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "vin:rsc:mgc_in_wire" {d(88)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "vin:rsc:mgc_in_wire" {d(89)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc.z(0)} -pin  "vin:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(1)} -pin  "vin:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(2)} -pin  "vin:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(3)} -pin  "vin:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(4)} -pin  "vin:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(5)} -pin  "vin:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(6)} -pin  "vin:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(7)} -pin  "vin:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(8)} -pin  "vin:rsc:mgc_in_wire" {z(8)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(9)} -pin  "vin:rsc:mgc_in_wire" {z(9)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(10)} -pin  "vin:rsc:mgc_in_wire" {z(10)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(11)} -pin  "vin:rsc:mgc_in_wire" {z(11)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(12)} -pin  "vin:rsc:mgc_in_wire" {z(12)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(13)} -pin  "vin:rsc:mgc_in_wire" {z(13)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(14)} -pin  "vin:rsc:mgc_in_wire" {z(14)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(15)} -pin  "vin:rsc:mgc_in_wire" {z(15)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(16)} -pin  "vin:rsc:mgc_in_wire" {z(16)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(17)} -pin  "vin:rsc:mgc_in_wire" {z(17)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(18)} -pin  "vin:rsc:mgc_in_wire" {z(18)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(19)} -pin  "vin:rsc:mgc_in_wire" {z(19)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(20)} -pin  "vin:rsc:mgc_in_wire" {z(20)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(21)} -pin  "vin:rsc:mgc_in_wire" {z(21)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(22)} -pin  "vin:rsc:mgc_in_wire" {z(22)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(23)} -pin  "vin:rsc:mgc_in_wire" {z(23)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(24)} -pin  "vin:rsc:mgc_in_wire" {z(24)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(25)} -pin  "vin:rsc:mgc_in_wire" {z(25)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(26)} -pin  "vin:rsc:mgc_in_wire" {z(26)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(27)} -pin  "vin:rsc:mgc_in_wire" {z(27)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(28)} -pin  "vin:rsc:mgc_in_wire" {z(28)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(29)} -pin  "vin:rsc:mgc_in_wire" {z(29)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(30)} -pin  "vin:rsc:mgc_in_wire" {z(30)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(31)} -pin  "vin:rsc:mgc_in_wire" {z(31)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(32)} -pin  "vin:rsc:mgc_in_wire" {z(32)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(33)} -pin  "vin:rsc:mgc_in_wire" {z(33)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(34)} -pin  "vin:rsc:mgc_in_wire" {z(34)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(35)} -pin  "vin:rsc:mgc_in_wire" {z(35)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(36)} -pin  "vin:rsc:mgc_in_wire" {z(36)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(37)} -pin  "vin:rsc:mgc_in_wire" {z(37)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(38)} -pin  "vin:rsc:mgc_in_wire" {z(38)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(39)} -pin  "vin:rsc:mgc_in_wire" {z(39)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(40)} -pin  "vin:rsc:mgc_in_wire" {z(40)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(41)} -pin  "vin:rsc:mgc_in_wire" {z(41)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(42)} -pin  "vin:rsc:mgc_in_wire" {z(42)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(43)} -pin  "vin:rsc:mgc_in_wire" {z(43)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(44)} -pin  "vin:rsc:mgc_in_wire" {z(44)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(45)} -pin  "vin:rsc:mgc_in_wire" {z(45)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(46)} -pin  "vin:rsc:mgc_in_wire" {z(46)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(47)} -pin  "vin:rsc:mgc_in_wire" {z(47)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(48)} -pin  "vin:rsc:mgc_in_wire" {z(48)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(49)} -pin  "vin:rsc:mgc_in_wire" {z(49)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(50)} -pin  "vin:rsc:mgc_in_wire" {z(50)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(51)} -pin  "vin:rsc:mgc_in_wire" {z(51)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(52)} -pin  "vin:rsc:mgc_in_wire" {z(52)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(53)} -pin  "vin:rsc:mgc_in_wire" {z(53)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(54)} -pin  "vin:rsc:mgc_in_wire" {z(54)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(55)} -pin  "vin:rsc:mgc_in_wire" {z(55)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(56)} -pin  "vin:rsc:mgc_in_wire" {z(56)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(57)} -pin  "vin:rsc:mgc_in_wire" {z(57)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(58)} -pin  "vin:rsc:mgc_in_wire" {z(58)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(59)} -pin  "vin:rsc:mgc_in_wire" {z(59)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(60)} -pin  "vin:rsc:mgc_in_wire" {z(60)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(61)} -pin  "vin:rsc:mgc_in_wire" {z(61)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(62)} -pin  "vin:rsc:mgc_in_wire" {z(62)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(63)} -pin  "vin:rsc:mgc_in_wire" {z(63)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(64)} -pin  "vin:rsc:mgc_in_wire" {z(64)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(65)} -pin  "vin:rsc:mgc_in_wire" {z(65)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(66)} -pin  "vin:rsc:mgc_in_wire" {z(66)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(67)} -pin  "vin:rsc:mgc_in_wire" {z(67)} -attr vt d -attr @path {/sobel/vin:rsc.z}
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+load net {vin:rsc.z(70)} -pin  "vin:rsc:mgc_in_wire" {z(70)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(71)} -pin  "vin:rsc:mgc_in_wire" {z(71)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(72)} -pin  "vin:rsc:mgc_in_wire" {z(72)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(73)} -pin  "vin:rsc:mgc_in_wire" {z(73)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(74)} -pin  "vin:rsc:mgc_in_wire" {z(74)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(75)} -pin  "vin:rsc:mgc_in_wire" {z(75)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(76)} -pin  "vin:rsc:mgc_in_wire" {z(76)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(77)} -pin  "vin:rsc:mgc_in_wire" {z(77)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(78)} -pin  "vin:rsc:mgc_in_wire" {z(78)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(79)} -pin  "vin:rsc:mgc_in_wire" {z(79)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(80)} -pin  "vin:rsc:mgc_in_wire" {z(80)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(81)} -pin  "vin:rsc:mgc_in_wire" {z(81)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(82)} -pin  "vin:rsc:mgc_in_wire" {z(82)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(83)} -pin  "vin:rsc:mgc_in_wire" {z(83)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(84)} -pin  "vin:rsc:mgc_in_wire" {z(84)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(85)} -pin  "vin:rsc:mgc_in_wire" {z(85)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(86)} -pin  "vin:rsc:mgc_in_wire" {z(86)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(87)} -pin  "vin:rsc:mgc_in_wire" {z(87)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(88)} -pin  "vin:rsc:mgc_in_wire" {z(88)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(89)} -pin  "vin:rsc:mgc_in_wire" {z(89)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load inst "vout:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" -attr xrf 5432 -attr oid 566 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(2,30)" -pg 1 -lvl 1002
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "vout:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "vout:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "vout:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "vout:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "vout:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "vout:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "vout:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "vout:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "vout:rsc:mgc_out_stdreg" {d(8)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "vout:rsc:mgc_out_stdreg" {d(9)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "vout:rsc:mgc_out_stdreg" {d(10)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "vout:rsc:mgc_out_stdreg" {d(11)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "vout:rsc:mgc_out_stdreg" {d(12)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "vout:rsc:mgc_out_stdreg" {d(13)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "vout:rsc:mgc_out_stdreg" {d(14)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "vout:rsc:mgc_out_stdreg" {d(15)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "vout:rsc:mgc_out_stdreg" {d(16)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "vout:rsc:mgc_out_stdreg" {d(17)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "vout:rsc:mgc_out_stdreg" {d(18)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "vout:rsc:mgc_out_stdreg" {d(19)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "vout:rsc:mgc_out_stdreg" {d(20)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "vout:rsc:mgc_out_stdreg" {d(21)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "vout:rsc:mgc_out_stdreg" {d(22)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "vout:rsc:mgc_out_stdreg" {d(23)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "vout:rsc:mgc_out_stdreg" {d(24)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "vout:rsc:mgc_out_stdreg" {d(25)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "vout:rsc:mgc_out_stdreg" {d(26)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "vout:rsc:mgc_out_stdreg" {d(27)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "vout:rsc:mgc_out_stdreg" {d(28)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "vout:rsc:mgc_out_stdreg" {d(29)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc.z(0)} -pin  "vout:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -pin  "vout:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -pin  "vout:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -pin  "vout:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -pin  "vout:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -pin  "vout:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -pin  "vout:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -pin  "vout:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -pin  "vout:rsc:mgc_out_stdreg" {z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -pin  "vout:rsc:mgc_out_stdreg" {z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -pin  "vout:rsc:mgc_out_stdreg" {z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -pin  "vout:rsc:mgc_out_stdreg" {z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -pin  "vout:rsc:mgc_out_stdreg" {z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -pin  "vout:rsc:mgc_out_stdreg" {z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -pin  "vout:rsc:mgc_out_stdreg" {z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -pin  "vout:rsc:mgc_out_stdreg" {z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -pin  "vout:rsc:mgc_out_stdreg" {z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -pin  "vout:rsc:mgc_out_stdreg" {z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -pin  "vout:rsc:mgc_out_stdreg" {z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -pin  "vout:rsc:mgc_out_stdreg" {z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -pin  "vout:rsc:mgc_out_stdreg" {z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -pin  "vout:rsc:mgc_out_stdreg" {z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -pin  "vout:rsc:mgc_out_stdreg" {z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -pin  "vout:rsc:mgc_out_stdreg" {z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -pin  "vout:rsc:mgc_out_stdreg" {z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -pin  "vout:rsc:mgc_out_stdreg" {z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -pin  "vout:rsc:mgc_out_stdreg" {z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -pin  "vout:rsc:mgc_out_stdreg" {z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -pin  "vout:rsc:mgc_out_stdreg" {z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -pin  "vout:rsc:mgc_out_stdreg" {z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+### END MODULE 
+
diff --git a/Sobel/sobel.v3/concat_rtl.v b/Sobel/sobel.v3/concat_rtl.v
new file mode 100644
index 0000000..edaece8
--- /dev/null
+++ b/Sobel/sobel.v3/concat_rtl.v
@@ -0,0 +1,2093 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:11:10 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  wire and_dcpl;
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [89:0] regs_regs_2_lpi_1_dfm;
+  reg [15:0] r_0_sva_1;
+  reg [15:0] g_0_sva_1;
+  reg [15:0] b_0_sva_1;
+  reg [15:0] r_2_sva_1;
+  reg [15:0] g_2_sva_1;
+  reg [15:0] b_2_sva_1;
+  reg [1:0] i_6_sva_1;
+  reg exit_FRAME_lpi_1_dfm_1;
+  reg [10:0] FRAME_mul_2_itm_1;
+  wire [21:0] nl_FRAME_mul_2_itm_1;
+  reg [8:0] FRAME_mul_3_itm_1;
+  wire [17:0] nl_FRAME_mul_3_itm_1;
+  reg [5:0] green_slc_green_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_18_itm_1;
+  wire [5:0] nl_FRAME_acc_18_itm_1;
+  reg FRAME_slc_acc_imod_2_4_itm_1;
+  reg green_slc_green_2_sg1_12_itm_1;
+  reg [10:0] FRAME_mul_4_itm_1;
+  wire [21:0] nl_FRAME_mul_4_itm_1;
+  reg [8:0] FRAME_mul_5_itm_1;
+  wire [17:0] nl_FRAME_mul_5_itm_1;
+  reg [5:0] blue_slc_blue_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_30_itm_1;
+  wire [5:0] nl_FRAME_acc_30_itm_1;
+  reg FRAME_slc_acc_imod_4_4_itm_1;
+  reg blue_slc_blue_2_sg1_12_itm_1;
+  reg [8:0] FRAME_mul_1_itm_1;
+  wire [17:0] nl_FRAME_mul_1_itm_1;
+  reg [5:0] red_slc_red_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_37_itm_1;
+  wire [5:0] nl_FRAME_acc_37_itm_1;
+  reg FRAME_slc_acc_imod_4_itm_1;
+  reg exit_FRAME_for_sva_1_st_1;
+  reg main_stage_0_2;
+  reg [1:0] FRAME_acc_41_itm_1_sg2;
+  wire [2:0] nl_FRAME_acc_41_itm_1_sg2;
+  reg [1:0] FRAME_acc_41_itm_1_sg1;
+  reg [5:0] FRAME_acc_41_itm_3;
+  wire [6:0] nl_FRAME_acc_41_itm_3;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+  wire [11:0] FRAME_acc_3_psp_sva;
+  wire [13:0] nl_FRAME_acc_3_psp_sva;
+  wire [11:0] FRAME_acc_4_psp_sva;
+  wire [13:0] nl_FRAME_acc_4_psp_sva;
+  wire [1:0] i_6_sva_2;
+  wire [2:0] nl_i_6_sva_2;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire exit_FRAME_for_lpi_1_dfm;
+  wire [89:0] regs_regs_2_lpi_1_dfm_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire exit_FRAME_lpi_1_dfm_1_mx0;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [5:0] acc_imod_sva;
+  wire [7:0] nl_acc_imod_sva;
+  wire [9:0] FRAME_mul_sdt;
+  wire [19:0] nl_FRAME_mul_sdt;
+  wire [5:0] acc_imod_4_sva;
+  wire [7:0] nl_acc_imod_4_sva;
+  wire [5:0] acc_imod_2_sva;
+  wire [7:0] nl_acc_imod_2_sva;
+  wire [15:0] b_2_sva_3;
+  wire [16:0] nl_b_2_sva_3;
+  wire [15:0] b_0_sva_3;
+  wire [16:0] nl_b_0_sva_3;
+  wire [15:0] g_2_sva_3;
+  wire [16:0] nl_g_2_sva_3;
+  wire [15:0] g_0_sva_3;
+  wire [16:0] nl_g_0_sva_3;
+  wire [15:0] r_2_sva_3;
+  wire [16:0] nl_r_2_sva_3;
+  wire [15:0] r_0_sva_3;
+  wire [16:0] nl_r_0_sva_3;
+  wire FRAME_for_nor_cse;
+  wire [15:0] ACC1_acc_43_itm;
+  wire [16:0] nl_ACC1_acc_43_itm;
+  wire [15:0] ACC1_acc_45_itm;
+  wire [16:0] nl_ACC1_acc_45_itm;
+  wire [15:0] ACC1_acc_44_itm;
+  wire [16:0] nl_ACC1_acc_44_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_3_itm;
+
+  wire[15:0] FRAME_for_mux_10_nl;
+  wire[9:0] regs_operator_17_mux_nl;
+  wire[15:0] FRAME_for_mux_9_nl;
+  wire[9:0] regs_operator_11_mux_nl;
+  wire[15:0] FRAME_for_mux_8_nl;
+  wire[9:0] regs_operator_16_mux_nl;
+  wire[15:0] FRAME_for_mux_7_nl;
+  wire[9:0] regs_operator_10_mux_nl;
+  wire[15:0] FRAME_for_mux_6_nl;
+  wire[9:0] regs_operator_15_mux_nl;
+  wire[15:0] FRAME_for_mux_5_nl;
+  wire[9:0] regs_operator_9_mux_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_3_psp_sva = (conv_u2s_11_12(FRAME_mul_2_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_3_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(green_slc_green_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_18_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_2_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({green_slc_green_2_sg1_12_itm_1
+      , 3'b0 , ({{2{green_slc_green_2_sg1_12_itm_1}}, green_slc_green_2_sg1_12_itm_1})
+      , 1'b0 , green_slc_green_2_sg1_12_itm_1}));
+  assign FRAME_acc_3_psp_sva = nl_FRAME_acc_3_psp_sva[11:0];
+  assign nl_FRAME_acc_4_psp_sva = (conv_u2s_11_12(FRAME_mul_4_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_5_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(blue_slc_blue_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_30_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_4_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({blue_slc_blue_2_sg1_12_itm_1
+      , 3'b0 , ({{2{blue_slc_blue_2_sg1_12_itm_1}}, blue_slc_blue_2_sg1_12_itm_1})
+      , 1'b0 , blue_slc_blue_2_sg1_12_itm_1}));
+  assign FRAME_acc_4_psp_sva = nl_FRAME_acc_4_psp_sva[11:0];
+  assign nl_FRAME_for_acc_itm = i_6_sva_2 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  assign nl_i_6_sva_2 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_2 = nl_i_6_sva_2[1:0];
+  assign i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm));
+  assign exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva;
+  assign regs_regs_2_lpi_1_dfm_mx0 = MUX_v_90_2_2({regs_regs_1_sva , regs_regs_2_lpi_1_dfm},
+      and_dcpl);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_dcpl);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_dcpl);
+  assign exit_FRAME_lpi_1_dfm_1_mx0 = MUX_s_1_2_2({(~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+      + 8'b10110101)))) , (exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm))},
+      FRAME_for_acc_itm[1]);
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign nl_acc_imod_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_43_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_43_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_43_itm[15])) , 1'b1 , (~ (ACC1_acc_43_itm[15]))}) + conv_u2u_2_4(ACC1_acc_43_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_43_itm[3:1]) + conv_u2u_3_4(~ (ACC1_acc_43_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_sva = nl_acc_imod_sva[5:0];
+  assign nl_ACC1_acc_43_itm = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[59:50])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[59:50])
+      , 1'b1})))) + (r_2_sva_3[15:1])) , (readslicef_2_1_1((({(r_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + r_0_sva_3;
+  assign ACC1_acc_43_itm = nl_ACC1_acc_43_itm[15:0];
+  assign nl_FRAME_mul_sdt = conv_u2u_2_10(ACC1_acc_43_itm[14:13]) * 10'b111000111;
+  assign FRAME_mul_sdt = nl_FRAME_mul_sdt[9:0];
+  assign nl_ACC1_acc_45_itm = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[39:30])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[39:30])
+      , 1'b1})))) + (b_2_sva_3[15:1])) , (readslicef_2_1_1((({(b_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + b_0_sva_3;
+  assign ACC1_acc_45_itm = nl_ACC1_acc_45_itm[15:0];
+  assign nl_acc_imod_4_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_45_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_45_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_45_itm[15])) , 1'b1 , (~ (ACC1_acc_45_itm[15]))}) + conv_u2u_2_4(ACC1_acc_45_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_45_itm[3:1]) + conv_u2u_3_4(~ (ACC1_acc_45_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_4_sva = nl_acc_imod_4_sva[5:0];
+  assign nl_ACC1_acc_44_itm = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[49:40])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[49:40])
+      , 1'b1})))) + (g_2_sva_3[15:1])) , (readslicef_2_1_1((({(g_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + g_0_sva_3;
+  assign ACC1_acc_44_itm = nl_ACC1_acc_44_itm[15:0];
+  assign nl_acc_imod_2_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_44_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_44_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_44_itm[15])) , 1'b1 , (~ (ACC1_acc_44_itm[15]))}) + conv_u2u_2_4(ACC1_acc_44_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_44_itm[3:1]) + conv_u2u_3_4(~ (ACC1_acc_44_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_2_sva = nl_acc_imod_2_sva[5:0];
+  assign FRAME_for_mux_10_nl = MUX_v_16_2_2({b_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[69:60])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[69:60])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+      , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_mx0[69:60]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_b_2_sva_3 = (FRAME_for_mux_10_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_17_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign b_2_sva_3 = nl_b_2_sva_3[15:0];
+  assign FRAME_for_mux_9_nl = MUX_v_16_2_2({b_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[9:0])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[9:0])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_11_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0]) ,
+      (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_mx0[9:0]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_b_0_sva_3 = (FRAME_for_mux_9_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_11_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign b_0_sva_3 = nl_b_0_sva_3[15:0];
+  assign FRAME_for_mux_8_nl = MUX_v_16_2_2({g_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[79:70])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[79:70])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+      , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_mx0[79:70]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_g_2_sva_3 = (FRAME_for_mux_8_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_16_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign g_2_sva_3 = nl_g_2_sva_3[15:0];
+  assign FRAME_for_mux_7_nl = MUX_v_16_2_2({g_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[19:10])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[19:10])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_10_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+      , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_mx0[19:10]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_g_0_sva_3 = (FRAME_for_mux_7_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_10_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign g_0_sva_3 = nl_g_0_sva_3[15:0];
+  assign FRAME_for_mux_6_nl = MUX_v_16_2_2({r_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[89:80])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[89:80])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+      , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_mx0[89:80]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_r_2_sva_3 = (FRAME_for_mux_6_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_15_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign r_2_sva_3 = nl_r_2_sva_3[15:0];
+  assign FRAME_for_mux_5_nl = MUX_v_16_2_2({r_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[29:20])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[29:20])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_9_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+      , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_mx0[29:20]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_r_0_sva_3 = (FRAME_for_mux_5_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_9_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign r_0_sva_3 = nl_r_0_sva_3[15:0];
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_3_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) |
+      FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+  assign and_dcpl = ~(exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva);
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      FRAME_acc_41_itm_1_sg2 <= 2'b0;
+      FRAME_acc_41_itm_1_sg1 <= 2'b0;
+      FRAME_acc_41_itm_3 <= 6'b0;
+      FRAME_mul_1_itm_1 <= 9'b0;
+      red_slc_red_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_37_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_4_itm_1 <= 1'b0;
+      FRAME_mul_4_itm_1 <= 11'b0;
+      FRAME_mul_5_itm_1 <= 9'b0;
+      blue_slc_blue_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_30_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_4_4_itm_1 <= 1'b0;
+      blue_slc_blue_2_sg1_12_itm_1 <= 1'b0;
+      FRAME_mul_2_itm_1 <= 11'b0;
+      FRAME_mul_3_itm_1 <= 9'b0;
+      green_slc_green_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_18_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_2_4_itm_1 <= 1'b0;
+      green_slc_green_2_sg1_12_itm_1 <= 1'b0;
+      exit_FRAME_for_sva_1_st_1 <= 1'b0;
+      i_6_sva_1 <= 2'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_2_lpi_1_dfm <= 90'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_1 <= 1'b0;
+      b_2_sva_1 <= 16'b0;
+      b_0_sva_1 <= 16'b0;
+      g_2_sva_1 <= 16'b0;
+      g_0_sva_1 <= 16'b0;
+      r_2_sva_1 <= 16'b0;
+      r_0_sva_1 <= 16'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({({((({FRAME_acc_41_itm_1_sg2 ,
+            FRAME_acc_41_itm_1_sg1 , FRAME_acc_41_itm_3}) + (conv_u2s_9_10(FRAME_mul_1_itm_1)
+            + conv_s2s_8_10(conv_u2s_6_8(red_slc_red_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_37_itm_1
+            + ({4'b1001 , FRAME_slc_acc_imod_4_itm_1}))))) | ({8'b0 , (FRAME_acc_3_psp_sva[11:10])}))
+            , (FRAME_acc_3_psp_sva[9:6]) , ((FRAME_acc_3_psp_sva[5:0]) | ({4'b0 ,
+            (FRAME_acc_4_psp_sva[11:10])})) , (FRAME_acc_4_psp_sva[9:0])}) , vout_rsc_mgc_out_stdreg_d},
+            ~(exit_FRAME_for_sva_1_st_1 & main_stage_0_2));
+        FRAME_acc_41_itm_1_sg2 <= nl_FRAME_acc_41_itm_1_sg2[1:0];
+        FRAME_acc_41_itm_1_sg1 <= FRAME_mul_sdt[7:6];
+        FRAME_acc_41_itm_3 <= nl_FRAME_acc_41_itm_3[5:0];
+        FRAME_mul_1_itm_1 <= nl_FRAME_mul_1_itm_1[8:0];
+        red_slc_red_2_sg1_itm_1 <= ACC1_acc_43_itm[9:4];
+        FRAME_acc_37_itm_1 <= nl_FRAME_acc_37_itm_1[4:0];
+        FRAME_slc_acc_imod_4_itm_1 <= acc_imod_sva[5];
+        FRAME_mul_4_itm_1 <= nl_FRAME_mul_4_itm_1[10:0];
+        FRAME_mul_5_itm_1 <= nl_FRAME_mul_5_itm_1[8:0];
+        blue_slc_blue_2_sg1_itm_1 <= ACC1_acc_45_itm[9:4];
+        FRAME_acc_30_itm_1 <= nl_FRAME_acc_30_itm_1[4:0];
+        FRAME_slc_acc_imod_4_4_itm_1 <= acc_imod_4_sva[5];
+        blue_slc_blue_2_sg1_12_itm_1 <= ACC1_acc_45_itm[15];
+        FRAME_mul_2_itm_1 <= nl_FRAME_mul_2_itm_1[10:0];
+        FRAME_mul_3_itm_1 <= nl_FRAME_mul_3_itm_1[8:0];
+        green_slc_green_2_sg1_itm_1 <= ACC1_acc_44_itm[9:4];
+        FRAME_acc_18_itm_1 <= nl_FRAME_acc_18_itm_1[4:0];
+        FRAME_slc_acc_imod_2_4_itm_1 <= acc_imod_2_sva[5];
+        green_slc_green_2_sg1_12_itm_1 <= ACC1_acc_44_itm[15];
+        exit_FRAME_for_sva_1_st_1 <= ~ (FRAME_for_acc_itm[1]);
+        i_6_sva_1 <= i_6_sva_2;
+        exit_FRAME_1_sva <= (~ (FRAME_for_acc_itm[1])) & exit_FRAME_lpi_1_dfm_1_mx0;
+        main_stage_0_2 <= 1'b1;
+        regs_regs_2_lpi_1_dfm <= regs_regs_2_lpi_1_dfm_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_1 <= exit_FRAME_lpi_1_dfm_1_mx0;
+        b_2_sva_1 <= b_2_sva_3;
+        b_0_sva_1 <= b_0_sva_3;
+        g_2_sva_1 <= g_2_sva_3;
+        g_0_sva_1 <= g_0_sva_3;
+        r_2_sva_1 <= r_2_sva_3;
+        r_0_sva_1 <= r_0_sva_3;
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_sva_1 , FRAME_p_1_lpi_1_dfm},
+            FRAME_for_acc_itm[1]);
+      end
+    end
+  end
+  assign nl_FRAME_acc_41_itm_1_sg2  = (FRAME_mul_sdt[9:8]) + conv_s2u_1_2(ACC1_acc_43_itm[15]);
+  assign nl_FRAME_acc_41_itm_3  = conv_u2u_5_6(FRAME_mul_sdt[4:0]) + conv_u2u_5_6(signext_5_3({(ACC1_acc_43_itm[15])
+      , 1'b0 , (ACC1_acc_43_itm[15])}));
+  assign nl_FRAME_mul_1_itm_1  = conv_u2u_3_9(ACC1_acc_43_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_37_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_sva[5:3])) , (~ (acc_imod_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC1_acc_43_itm[9:7]));
+  assign nl_FRAME_mul_4_itm_1  = conv_u2u_2_11(ACC1_acc_45_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_5_itm_1  = conv_u2u_3_9(ACC1_acc_45_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_30_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_4_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_4_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_4_sva[5:3])) , (~ (acc_imod_4_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_4_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC1_acc_45_itm[9:7]));
+  assign nl_FRAME_mul_2_itm_1  = conv_u2u_2_11(ACC1_acc_44_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_3_itm_1  = conv_u2u_3_9(ACC1_acc_44_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_18_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_2_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_2_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_2_sva[5:3])) , (~ (acc_imod_2_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_2_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC1_acc_44_itm[9:7]));
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_2_1_1;
+    input [1:0] vector;
+    reg [1:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_2_1_1 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [15:0] signext_16_11;
+    input [10:0] vector;
+  begin
+    signext_16_11= {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_11_15 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_15 = {{4{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_s2u_1_2 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_2 = {vector[0], vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v3/cycle.rpt b/Sobel/sobel.v3/cycle.rpt
new file mode 100644
index 0000000..02e02ff
--- /dev/null
+++ b/Sobel/sobel.v3/cycle.rpt
@@ -0,0 +1,85 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 14:10:45 +0000 2016                      
+
+Solution Settings: sobel.v3
+  Current state: schedule
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       161  921601     921600            0  1          
+    Design Total:                     161  921601     921600            0  0          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /sobel/core              
+    
+  I/O Data Ranges
+    Port       Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ---------- ---- -------- --------- --------- ------- -------- --------
+    vin:rsc.z  IN   Unsigned        90                                     
+    clk        IN   Unsigned         1                                     
+    en         IN   Unsigned         1                                     
+    arst_n     IN   Unsigned         1                                     
+    vout:rsc.z OUT  Unsigned        30                                     
+    
+  Memory Resources
+    Resource Name: /sobel/vin:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 90
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable   Indices Phys Memory Address     
+      ---------- ------- -----------------------
+      /sobel/vin    0:89 00000000-00000000 (0-0) 
+      
+    Resource Name: /sobel/vout:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 30
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable    Indices Phys Memory Address     
+      ----------- ------- -----------------------
+      /sobel/vout    0:29 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process     Loop             Iterations C-Steps Total Cycles  Duration  Unroll Init Comments 
+    ----------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
+    /sobel/core core:rlp           Infinite       0       921602  18.43 ms                       
+    /sobel/core   main             Infinite       3       921602  18.43 ms            1          
+    
+  Loop Execution Profile
+    Process     Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------- ---------------- ------------ -------------------------- ----------------- --------
+    /sobel/core core:rlp                   0                        0.00           921600           
+    /sobel/core   main                921602                      100.00           921600           
+    
+  End of Report
diff --git a/Sobel/sobel.v3/cycle.v b/Sobel/sobel.v3/cycle.v
new file mode 100644
index 0000000..57c5ef0
--- /dev/null
+++ b/Sobel/sobel.v3/cycle.v
@@ -0,0 +1,910 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:10:46 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg [18:0] FRAME_p_1_lpi_1;
+    reg [89:0] regs_regs_1_sva;
+    reg [89:0] regs_regs_0_sva;
+    reg exit_FRAME_1_sva;
+    reg [18:0] FRAME_p_1_lpi_1_dfm;
+    reg exit_FRAME_for_lpi_1_dfm;
+    reg [89:0] regs_regs_0_sva_1;
+    reg [89:0] regs_regs_0_sva_dfm;
+    reg [89:0] regs_regs_1_sva_dfm;
+    reg [89:0] regs_regs_2_lpi_1_dfm;
+    reg [1:0] i_6_lpi_1_dfm;
+    reg FRAME_for_slc_YMATRIX_rom_11_psp_sva;
+    reg [15:0] r_0_sva_1;
+    reg [15:0] g_0_sva_1;
+    reg [15:0] b_0_sva_1;
+    reg [15:0] r_2_sva_1;
+    reg [15:0] g_2_sva_1;
+    reg [15:0] b_2_sva_1;
+    reg [1:0] i_6_sva_1;
+    reg exit_FRAME_for_sva_1;
+    reg [14:0] red_2_sg1_sva;
+    reg [14:0] green_2_sg1_sva;
+    reg [14:0] blue_2_sg1_sva;
+    reg [5:0] acc_imod_sva;
+    reg [5:0] acc_imod_2_sva;
+    reg [11:0] FRAME_acc_3_psp_sva;
+    reg [5:0] acc_imod_4_sva;
+    reg [11:0] FRAME_acc_4_psp_sva;
+    reg [18:0] FRAME_p_1_sva_1;
+    reg exit_FRAME_lpi_1_dfm_1;
+    reg exit_FRAME_for_lpi_1_dfm_2;
+    reg [10:0] FRAME_mul_2_itm;
+    reg [10:0] FRAME_mul_2_itm_1;
+    reg [8:0] FRAME_mul_3_itm;
+    reg [8:0] FRAME_mul_3_itm_1;
+    reg [5:0] green_slc_green_2_sg1_itm;
+    reg [5:0] green_slc_green_2_sg1_itm_1;
+    reg [4:0] FRAME_acc_18_itm;
+    reg [4:0] FRAME_acc_18_itm_1;
+    reg FRAME_slc_acc_imod_2_4_itm;
+    reg FRAME_slc_acc_imod_2_4_itm_1;
+    reg green_slc_green_2_sg1_12_itm;
+    reg green_slc_green_2_sg1_12_itm_1;
+    reg green_slc_green_2_sg1_13_itm;
+    reg green_slc_green_2_sg1_13_itm_1;
+    reg green_slc_green_2_sg1_8_itm;
+    reg green_slc_green_2_sg1_8_itm_1;
+    reg [10:0] FRAME_mul_4_itm;
+    reg [10:0] FRAME_mul_4_itm_1;
+    reg [8:0] FRAME_mul_5_itm;
+    reg [8:0] FRAME_mul_5_itm_1;
+    reg [5:0] blue_slc_blue_2_sg1_itm;
+    reg [5:0] blue_slc_blue_2_sg1_itm_1;
+    reg [4:0] FRAME_acc_30_itm;
+    reg [4:0] FRAME_acc_30_itm_1;
+    reg FRAME_slc_acc_imod_4_4_itm;
+    reg FRAME_slc_acc_imod_4_4_itm_1;
+    reg blue_slc_blue_2_sg1_12_itm;
+    reg blue_slc_blue_2_sg1_12_itm_1;
+    reg blue_slc_blue_2_sg1_13_itm;
+    reg blue_slc_blue_2_sg1_13_itm_1;
+    reg blue_slc_blue_2_sg1_8_itm;
+    reg blue_slc_blue_2_sg1_8_itm_1;
+    reg [8:0] FRAME_mul_1_itm;
+    reg [8:0] FRAME_mul_1_itm_1;
+    reg [5:0] red_slc_red_2_sg1_itm;
+    reg [5:0] red_slc_red_2_sg1_itm_1;
+    reg [4:0] FRAME_acc_37_itm;
+    reg [4:0] FRAME_acc_37_itm_1;
+    reg FRAME_slc_acc_imod_4_itm;
+    reg FRAME_slc_acc_imod_4_itm_1;
+    reg exit_FRAME_for_sva_1_st_1;
+    reg main_stage_0_2;
+    reg [10:0] r_0_sva_2;
+    reg [10:0] g_0_sva_2;
+    reg [10:0] b_0_sva_2;
+    reg [10:0] r_2_sva_2;
+    reg [10:0] g_2_sva_2;
+    reg [10:0] b_2_sva_2;
+    reg [9:0] FRAME_mul_sdt;
+    reg FRAME_for_nor_cse;
+    reg FRAME_for_slc_XMATRIX_rom_11_psp_sva_1;
+    reg [1:0] FRAME_acc_41_itm_sg2;
+    reg [1:0] FRAME_acc_41_itm_sg1;
+    reg [5:0] FRAME_acc_41_itm_2;
+    reg [1:0] FRAME_acc_41_itm_1_sg2;
+    reg [1:0] FRAME_acc_41_itm_1_sg1;
+    reg [5:0] FRAME_acc_41_itm_3;
+
+    reg[15:0] FRAME_for_mux_5_nl;
+    reg[9:0] regs_operator_9_mux_nl;
+    reg[15:0] FRAME_for_mux_7_nl;
+    reg[9:0] regs_operator_10_mux_nl;
+    reg[15:0] FRAME_for_mux_9_nl;
+    reg[9:0] regs_operator_11_mux_nl;
+    reg[15:0] FRAME_for_mux_6_nl;
+    reg[9:0] regs_operator_15_mux_nl;
+    reg[15:0] FRAME_for_mux_8_nl;
+    reg[9:0] regs_operator_16_mux_nl;
+    reg[15:0] FRAME_for_mux_10_nl;
+    reg[9:0] regs_operator_17_mux_nl;
+    begin : core_rlpExit
+      forever begin : core_rlp
+        // C-Step 0 of Loop 'core_rlp'
+        FRAME_p_1_lpi_1 = 19'b0;
+        regs_regs_1_sva = 90'b0;
+        regs_regs_0_sva = 90'b0;
+        exit_FRAME_1_sva = 1'b1;
+        main_stage_0_2 = 1'b0;
+        begin : mainExit
+          forever begin : main
+            // C-Step 0 of Loop 'main'
+            begin : waitLoop0Exit
+              forever begin : waitLoop0
+                @(posedge clk or negedge ( arst_n ));
+                if ( ~ arst_n )
+                  disable core_rlpExit;
+                if ( en )
+                  disable waitLoop0Exit;
+              end
+            end
+            // C-Step 1 of Loop 'main'
+            if ( main_stage_0_2 ) begin
+              if ( exit_FRAME_for_sva_1_st_1 ) begin
+                FRAME_acc_3_psp_sva = (conv_u2s_11_12(FRAME_mul_2_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_3_itm_1)
+                    + conv_s2s_8_10(conv_u2s_6_8(green_slc_green_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_18_itm_1
+                    + ({4'b1001 , FRAME_slc_acc_imod_2_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({green_slc_green_2_sg1_12_itm_1
+                    , 3'b0 , ({{2{green_slc_green_2_sg1_13_itm_1}}, green_slc_green_2_sg1_13_itm_1})
+                    , 1'b0 , green_slc_green_2_sg1_8_itm_1}));
+                FRAME_acc_4_psp_sva = (conv_u2s_11_12(FRAME_mul_4_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_5_itm_1)
+                    + conv_s2s_8_10(conv_u2s_6_8(blue_slc_blue_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_30_itm_1
+                    + ({4'b1001 , FRAME_slc_acc_imod_4_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({blue_slc_blue_2_sg1_12_itm_1
+                    , 3'b0 , ({{2{blue_slc_blue_2_sg1_13_itm_1}}, blue_slc_blue_2_sg1_13_itm_1})
+                    , 1'b0 , blue_slc_blue_2_sg1_8_itm_1}));
+                vout_rsc_mgc_out_stdreg_d <= {((({FRAME_acc_41_itm_1_sg2 , FRAME_acc_41_itm_1_sg1
+                    , FRAME_acc_41_itm_3}) + (conv_u2s_9_10(FRAME_mul_1_itm_1) +
+                    conv_s2s_8_10(conv_u2s_6_8(red_slc_red_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_37_itm_1
+                    + ({4'b1001 , FRAME_slc_acc_imod_4_itm_1}))))) | ({8'b0, FRAME_acc_3_psp_sva[11:10]}))
+                    , (FRAME_acc_3_psp_sva[9:6]) , ((FRAME_acc_3_psp_sva[5:0]) |
+                    ({4'b0, FRAME_acc_4_psp_sva[11:10]})) , (FRAME_acc_4_psp_sva[9:0])};
+              end
+            end
+            FRAME_p_1_sva_1 = 19'b0;
+            b_2_sva_2 = 11'b0;
+            g_2_sva_2 = 11'b0;
+            r_2_sva_2 = 11'b0;
+            b_0_sva_2 = 11'b0;
+            g_0_sva_2 = 11'b0;
+            r_0_sva_2 = 11'b0;
+            FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+            exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_lpi_1_dfm_2 | exit_FRAME_1_sva;
+            if ( exit_FRAME_for_lpi_1_dfm ) begin
+              regs_regs_0_sva_1 = vin_rsc_mgc_in_wire_d;
+              r_0_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[29:20]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[29:20]) , 1'b1})));
+              g_0_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[19:10]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[19:10]) , 1'b1})));
+              b_0_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[9:0]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[9:0]) , 1'b1})));
+              r_2_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[89:80]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[89:80]) , 1'b1})));
+              g_2_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[79:70]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[79:70]) , 1'b1})));
+              b_2_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[69:60]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[69:60]) , 1'b1})));
+              regs_regs_0_sva_dfm = regs_regs_0_sva_1;
+              regs_regs_1_sva_dfm = regs_regs_0_sva;
+              regs_regs_2_lpi_1_dfm = regs_regs_1_sva;
+            end
+            else begin
+              regs_regs_0_sva_dfm = regs_regs_0_sva;
+              regs_regs_1_sva_dfm = regs_regs_1_sva;
+            end
+            i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm));
+            FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+            FRAME_for_slc_YMATRIX_rom_11_psp_sva = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1]))))
+                | FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+            FRAME_for_mux_5_nl = MUX_v_16_2_2({r_0_sva_1 , ({{5{r_0_sva_2[10]}},
+                r_0_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_9_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[29:20]) ,
+                (regs_regs_1_sva_dfm[29:20]) , (regs_regs_2_lpi_1_dfm[29:20]) , 10'b0},
+                i_6_lpi_1_dfm);
+            r_0_sva_1 = (FRAME_for_mux_5_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_9_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva})));
+            FRAME_for_mux_7_nl = MUX_v_16_2_2({g_0_sva_1 , ({{5{g_0_sva_2[10]}},
+                g_0_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_10_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[19:10])
+                , (regs_regs_1_sva_dfm[19:10]) , (regs_regs_2_lpi_1_dfm[19:10]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            g_0_sva_1 = (FRAME_for_mux_7_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_10_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva})));
+            FRAME_for_mux_9_nl = MUX_v_16_2_2({b_0_sva_1 , ({{5{b_0_sva_2[10]}},
+                b_0_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_11_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[9:0]) ,
+                (regs_regs_1_sva_dfm[9:0]) , (regs_regs_2_lpi_1_dfm[9:0]) , 10'b0},
+                i_6_lpi_1_dfm);
+            b_0_sva_1 = (FRAME_for_mux_9_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_11_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva})));
+            FRAME_for_slc_XMATRIX_rom_11_psp_sva_1 = (~((~ (i_6_lpi_1_dfm[1])) &
+                (i_6_lpi_1_dfm[0]))) | FRAME_for_nor_cse;
+            FRAME_for_mux_6_nl = MUX_v_16_2_2({r_2_sva_1 , ({{5{r_2_sva_2[10]}},
+                r_2_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[89:80])
+                , (regs_regs_1_sva_dfm[89:80]) , (regs_regs_2_lpi_1_dfm[89:80]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            r_2_sva_1 = (FRAME_for_mux_6_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_15_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+            FRAME_for_mux_8_nl = MUX_v_16_2_2({g_2_sva_1 , ({{5{g_2_sva_2[10]}},
+                g_2_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[79:70])
+                , (regs_regs_1_sva_dfm[79:70]) , (regs_regs_2_lpi_1_dfm[79:70]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            g_2_sva_1 = (FRAME_for_mux_8_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_16_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+            FRAME_for_mux_10_nl = MUX_v_16_2_2({b_2_sva_1 , ({{5{b_2_sva_2[10]}},
+                b_2_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[69:60])
+                , (regs_regs_1_sva_dfm[69:60]) , (regs_regs_2_lpi_1_dfm[69:60]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            b_2_sva_1 = (FRAME_for_mux_10_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_17_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+            i_6_sva_1 = i_6_lpi_1_dfm + 2'b1;
+            exit_FRAME_for_sva_1 = ~ (readslicef_3_1_2((({1'b1 , i_6_sva_1}) + 3'b1)));
+            if ( exit_FRAME_for_sva_1 ) begin
+              red_2_sg1_sva = readslicef_16_15_1((({(conv_s2u_10_15(~ (regs_regs_0_sva_dfm[59:50]))
+                  + conv_s2u_10_15(regs_regs_2_lpi_1_dfm[59:50]) + (r_2_sva_1[15:1])
+                  + 15'b1) , (readslicef_2_1_1((({(r_2_sva_1[0]) , 1'b1}) + 2'b11)))})
+                  + r_0_sva_1));
+              green_2_sg1_sva = readslicef_16_15_1((({(conv_s2u_10_15(~ (regs_regs_0_sva_dfm[49:40]))
+                  + conv_s2u_10_15(regs_regs_2_lpi_1_dfm[49:40]) + (g_2_sva_1[15:1])
+                  + 15'b1) , (readslicef_2_1_1((({(g_2_sva_1[0]) , 1'b1}) + 2'b11)))})
+                  + g_0_sva_1));
+              blue_2_sg1_sva = readslicef_16_15_1((({(conv_s2u_10_15(~ (regs_regs_0_sva_dfm[39:30]))
+                  + conv_s2u_10_15(regs_regs_2_lpi_1_dfm[39:30]) + (b_2_sva_1[15:1])
+                  + 15'b1) , (readslicef_2_1_1((({(b_2_sva_1[0]) , 1'b1}) + 2'b11)))})
+                  + b_0_sva_1));
+              acc_imod_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(red_2_sg1_sva[8:6])
+                  + conv_u2u_3_4(~ (red_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                  (red_2_sg1_sva[14])) , 1'b1 , (~ (red_2_sg1_sva[14]))}) + conv_u2u_2_4(red_2_sg1_sva[13:12])))
+                  + conv_u2u_4_6(conv_u2u_3_4(red_2_sg1_sva[2:0]) + conv_u2u_3_4(~
+                  (red_2_sg1_sva[5:3])))) + 6'b101011;
+              acc_imod_2_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(green_2_sg1_sva[8:6])
+                  + conv_u2u_3_4(~ (green_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                  (green_2_sg1_sva[14])) , 1'b1 , (~ (green_2_sg1_sva[14]))}) + conv_u2u_2_4(green_2_sg1_sva[13:12])))
+                  + conv_u2u_4_6(conv_u2u_3_4(green_2_sg1_sva[2:0]) + conv_u2u_3_4(~
+                  (green_2_sg1_sva[5:3])))) + 6'b101011;
+              FRAME_mul_2_itm = conv_u2u_22_11(conv_u2u_2_11(green_2_sg1_sva[13:12])
+                  * 11'b111000111);
+              FRAME_mul_3_itm = conv_u2u_18_9(conv_u2u_3_9(green_2_sg1_sva[11:9])
+                  * 9'b111001);
+              green_slc_green_2_sg1_itm = green_2_sg1_sva[8:3];
+              FRAME_acc_18_itm = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_2_sva[5]))
+                  , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_2_sva[2:0]) ,
+                  1'b1}) + conv_u2s_4_5({(~ (acc_imod_2_sva[5:3])) , (~ (acc_imod_2_sva[5]))})))))})
+                  + conv_u2u_2_4(acc_imod_2_sva[4:3])) + conv_u2u_3_5(~ (green_2_sg1_sva[8:6]));
+              FRAME_slc_acc_imod_2_4_itm = acc_imod_2_sva[5];
+              green_slc_green_2_sg1_12_itm = green_2_sg1_sva[14];
+              green_slc_green_2_sg1_13_itm = green_2_sg1_sva[14];
+              green_slc_green_2_sg1_8_itm = green_2_sg1_sva[14];
+              acc_imod_4_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(blue_2_sg1_sva[8:6])
+                  + conv_u2u_3_4(~ (blue_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                  (blue_2_sg1_sva[14])) , 1'b1 , (~ (blue_2_sg1_sva[14]))}) + conv_u2u_2_4(blue_2_sg1_sva[13:12])))
+                  + conv_u2u_4_6(conv_u2u_3_4(blue_2_sg1_sva[2:0]) + conv_u2u_3_4(~
+                  (blue_2_sg1_sva[5:3])))) + 6'b101011;
+              FRAME_mul_4_itm = conv_u2u_22_11(conv_u2u_2_11(blue_2_sg1_sva[13:12])
+                  * 11'b111000111);
+              FRAME_mul_5_itm = conv_u2u_18_9(conv_u2u_3_9(blue_2_sg1_sva[11:9])
+                  * 9'b111001);
+              blue_slc_blue_2_sg1_itm = blue_2_sg1_sva[8:3];
+              FRAME_acc_30_itm = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_4_sva[5]))
+                  , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_4_sva[2:0]) ,
+                  1'b1}) + conv_u2s_4_5({(~ (acc_imod_4_sva[5:3])) , (~ (acc_imod_4_sva[5]))})))))})
+                  + conv_u2u_2_4(acc_imod_4_sva[4:3])) + conv_u2u_3_5(~ (blue_2_sg1_sva[8:6]));
+              FRAME_slc_acc_imod_4_4_itm = acc_imod_4_sva[5];
+              blue_slc_blue_2_sg1_12_itm = blue_2_sg1_sva[14];
+              blue_slc_blue_2_sg1_13_itm = blue_2_sg1_sva[14];
+              blue_slc_blue_2_sg1_8_itm = blue_2_sg1_sva[14];
+              FRAME_mul_sdt = conv_u2u_20_10(conv_u2u_2_10(red_2_sg1_sva[13:12])
+                  * 10'b111000111);
+              FRAME_acc_41_itm_sg1 = FRAME_mul_sdt[7:6];
+              FRAME_acc_41_itm_2 = conv_u2u_5_6(FRAME_mul_sdt[4:0]) + conv_u2u_5_6(signext_5_3({(red_2_sg1_sva[14])
+                  , 1'b0 , (red_2_sg1_sva[14])}));
+              FRAME_acc_41_itm_sg2 = (FRAME_mul_sdt[9:8]) + conv_s2u_1_2(red_2_sg1_sva[14]);
+              FRAME_mul_1_itm = conv_u2u_18_9(conv_u2u_3_9(red_2_sg1_sva[11:9]) *
+                  9'b111001);
+              red_slc_red_2_sg1_itm = red_2_sg1_sva[8:3];
+              FRAME_acc_37_itm = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_sva[5]))
+                  , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_sva[2:0]) , 1'b1})
+                  + conv_u2s_4_5({(~ (acc_imod_sva[5:3])) , (~ (acc_imod_sva[5]))})))))})
+                  + conv_u2u_2_4(acc_imod_sva[4:3])) + conv_u2u_3_5(~ (red_2_sg1_sva[8:6]));
+              FRAME_slc_acc_imod_4_itm = acc_imod_sva[5];
+              FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+              exit_FRAME_lpi_1_dfm_1 = ~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+                  + 8'b10110101)));
+            end
+            else begin
+              exit_FRAME_lpi_1_dfm_1 = exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm);
+            end
+            exit_FRAME_for_lpi_1_dfm_2 = exit_FRAME_for_sva_1;
+            regs_regs_0_sva = regs_regs_0_sva_dfm;
+            regs_regs_1_sva = regs_regs_1_sva_dfm;
+            FRAME_p_1_lpi_1 = MUX_v_19_2_2({FRAME_p_1_lpi_1_dfm , FRAME_p_1_sva_1},
+                exit_FRAME_for_sva_1);
+            exit_FRAME_1_sva = exit_FRAME_for_sva_1 & exit_FRAME_lpi_1_dfm_1;
+            FRAME_mul_2_itm_1 = FRAME_mul_2_itm;
+            FRAME_mul_3_itm_1 = FRAME_mul_3_itm;
+            green_slc_green_2_sg1_itm_1 = green_slc_green_2_sg1_itm;
+            FRAME_acc_18_itm_1 = FRAME_acc_18_itm;
+            FRAME_slc_acc_imod_2_4_itm_1 = FRAME_slc_acc_imod_2_4_itm;
+            green_slc_green_2_sg1_12_itm_1 = green_slc_green_2_sg1_12_itm;
+            green_slc_green_2_sg1_13_itm_1 = green_slc_green_2_sg1_13_itm;
+            green_slc_green_2_sg1_8_itm_1 = green_slc_green_2_sg1_8_itm;
+            FRAME_mul_4_itm_1 = FRAME_mul_4_itm;
+            FRAME_mul_5_itm_1 = FRAME_mul_5_itm;
+            blue_slc_blue_2_sg1_itm_1 = blue_slc_blue_2_sg1_itm;
+            FRAME_acc_30_itm_1 = FRAME_acc_30_itm;
+            FRAME_slc_acc_imod_4_4_itm_1 = FRAME_slc_acc_imod_4_4_itm;
+            blue_slc_blue_2_sg1_12_itm_1 = blue_slc_blue_2_sg1_12_itm;
+            blue_slc_blue_2_sg1_13_itm_1 = blue_slc_blue_2_sg1_13_itm;
+            blue_slc_blue_2_sg1_8_itm_1 = blue_slc_blue_2_sg1_8_itm;
+            FRAME_acc_41_itm_1_sg1 = FRAME_acc_41_itm_sg1;
+            FRAME_acc_41_itm_3 = FRAME_acc_41_itm_2;
+            FRAME_acc_41_itm_1_sg2 = FRAME_acc_41_itm_sg2;
+            FRAME_mul_1_itm_1 = FRAME_mul_1_itm;
+            red_slc_red_2_sg1_itm_1 = red_slc_red_2_sg1_itm;
+            FRAME_acc_37_itm_1 = FRAME_acc_37_itm;
+            FRAME_slc_acc_imod_4_itm_1 = FRAME_slc_acc_imod_4_itm;
+            exit_FRAME_for_sva_1_st_1 = exit_FRAME_for_sva_1;
+            main_stage_0_2 = 1'b1;
+          end
+        end
+      end
+    end
+    FRAME_acc_41_itm_3 = 6'b0;
+    FRAME_acc_41_itm_1_sg1 = 2'b0;
+    FRAME_acc_41_itm_1_sg2 = 2'b0;
+    FRAME_acc_41_itm_2 = 6'b0;
+    FRAME_acc_41_itm_sg1 = 2'b0;
+    FRAME_acc_41_itm_sg2 = 2'b0;
+    FRAME_for_slc_XMATRIX_rom_11_psp_sva_1 = 1'b0;
+    FRAME_for_nor_cse = 1'b0;
+    FRAME_mul_sdt = 10'b0;
+    b_2_sva_2 = 11'b0;
+    g_2_sva_2 = 11'b0;
+    r_2_sva_2 = 11'b0;
+    b_0_sva_2 = 11'b0;
+    g_0_sva_2 = 11'b0;
+    r_0_sva_2 = 11'b0;
+    main_stage_0_2 = 1'b0;
+    exit_FRAME_for_sva_1_st_1 = 1'b0;
+    FRAME_slc_acc_imod_4_itm_1 = 1'b0;
+    FRAME_slc_acc_imod_4_itm = 1'b0;
+    FRAME_acc_37_itm_1 = 5'b0;
+    FRAME_acc_37_itm = 5'b0;
+    red_slc_red_2_sg1_itm_1 = 6'b0;
+    red_slc_red_2_sg1_itm = 6'b0;
+    FRAME_mul_1_itm_1 = 9'b0;
+    FRAME_mul_1_itm = 9'b0;
+    blue_slc_blue_2_sg1_8_itm_1 = 1'b0;
+    blue_slc_blue_2_sg1_8_itm = 1'b0;
+    blue_slc_blue_2_sg1_13_itm_1 = 1'b0;
+    blue_slc_blue_2_sg1_13_itm = 1'b0;
+    blue_slc_blue_2_sg1_12_itm_1 = 1'b0;
+    blue_slc_blue_2_sg1_12_itm = 1'b0;
+    FRAME_slc_acc_imod_4_4_itm_1 = 1'b0;
+    FRAME_slc_acc_imod_4_4_itm = 1'b0;
+    FRAME_acc_30_itm_1 = 5'b0;
+    FRAME_acc_30_itm = 5'b0;
+    blue_slc_blue_2_sg1_itm_1 = 6'b0;
+    blue_slc_blue_2_sg1_itm = 6'b0;
+    FRAME_mul_5_itm_1 = 9'b0;
+    FRAME_mul_5_itm = 9'b0;
+    FRAME_mul_4_itm_1 = 11'b0;
+    FRAME_mul_4_itm = 11'b0;
+    green_slc_green_2_sg1_8_itm_1 = 1'b0;
+    green_slc_green_2_sg1_8_itm = 1'b0;
+    green_slc_green_2_sg1_13_itm_1 = 1'b0;
+    green_slc_green_2_sg1_13_itm = 1'b0;
+    green_slc_green_2_sg1_12_itm_1 = 1'b0;
+    green_slc_green_2_sg1_12_itm = 1'b0;
+    FRAME_slc_acc_imod_2_4_itm_1 = 1'b0;
+    FRAME_slc_acc_imod_2_4_itm = 1'b0;
+    FRAME_acc_18_itm_1 = 5'b0;
+    FRAME_acc_18_itm = 5'b0;
+    green_slc_green_2_sg1_itm_1 = 6'b0;
+    green_slc_green_2_sg1_itm = 6'b0;
+    FRAME_mul_3_itm_1 = 9'b0;
+    FRAME_mul_3_itm = 9'b0;
+    FRAME_mul_2_itm_1 = 11'b0;
+    FRAME_mul_2_itm = 11'b0;
+    exit_FRAME_for_lpi_1_dfm_2 = 1'b0;
+    exit_FRAME_lpi_1_dfm_1 = 1'b0;
+    FRAME_p_1_sva_1 = 19'b0;
+    FRAME_acc_4_psp_sva = 12'b0;
+    acc_imod_4_sva = 6'b0;
+    FRAME_acc_3_psp_sva = 12'b0;
+    acc_imod_2_sva = 6'b0;
+    acc_imod_sva = 6'b0;
+    blue_2_sg1_sva = 15'b0;
+    green_2_sg1_sva = 15'b0;
+    red_2_sg1_sva = 15'b0;
+    exit_FRAME_for_sva_1 = 1'b0;
+    i_6_sva_1 = 2'b0;
+    b_2_sva_1 = 16'b0;
+    g_2_sva_1 = 16'b0;
+    r_2_sva_1 = 16'b0;
+    b_0_sva_1 = 16'b0;
+    g_0_sva_1 = 16'b0;
+    r_0_sva_1 = 16'b0;
+    FRAME_for_slc_YMATRIX_rom_11_psp_sva = 1'b0;
+    i_6_lpi_1_dfm = 2'b0;
+    regs_regs_2_lpi_1_dfm = 90'b0;
+    regs_regs_1_sva_dfm = 90'b0;
+    regs_regs_0_sva_dfm = 90'b0;
+    regs_regs_0_sva_1 = 90'b0;
+    exit_FRAME_for_lpi_1_dfm = 1'b0;
+    FRAME_p_1_lpi_1_dfm = 19'b0;
+    exit_FRAME_1_sva = 1'b0;
+    regs_regs_0_sva = 90'b0;
+    regs_regs_1_sva = 90'b0;
+    FRAME_p_1_lpi_1 = 19'b0;
+    vout_rsc_mgc_out_stdreg_d <= 30'b0;
+  end
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_3_1_2;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 2;
+    readslicef_3_1_2 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [14:0] readslicef_16_15_1;
+    input [15:0] vector;
+    reg [15:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_16_15_1 = tmp[14:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_2_1_1;
+    input [1:0] vector;
+    reg [1:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_2_1_1 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_10_15 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_15 = {{5{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_22_11 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_s2u_1_2 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_2 = {vector[0], vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v3/cycle_mgc_ioport.v b/Sobel/sobel.v3/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v3/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v3/cycle_mgc_ioport_v2001.v b/Sobel/sobel.v3/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v3/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v3/cycle_set.tcl b/Sobel/sobel.v3/cycle_set.tcl
new file mode 100644
index 0000000..0f1e219
--- /dev/null
+++ b/Sobel/sobel.v3/cycle_set.tcl
@@ -0,0 +1,113 @@
+
+# Loop constraints
+directive set /sobel/core/core:rlp CSTEPS_FROM {{. == 0}}
+directive set /sobel/core/core:rlp/main CSTEPS_FROM {{. == 3} {.. == 0}}
+
+# IO operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:io_read(vin:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:io_write(vout:rsc.d) CSTEPS_FROM {{.. == 2}}
+
+# Real operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:for:and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#48 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#49 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#50 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#51 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#52 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#5 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#9:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#7 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#10:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#9 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#11:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:or#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#6 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#15:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#8 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#16:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#12 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#10 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#17:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#53 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#54 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#43 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#55 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#56 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#44 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#57 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#58 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#45 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#9 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#11 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#13 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#12 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#15 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#23 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#17 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#18 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#19 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#20 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#21 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#22 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#24 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#27 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#26 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#28 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#35 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#29 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#30 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#31 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#32 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#33 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#34 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#4 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#41 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#42 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#36 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#37 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#38 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#39 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#40 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#2 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#23 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#24 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#19 CSTEPS_FROM {{.. == 1}}
diff --git a/Sobel/sobel.v3/directives.tcl b/Sobel/sobel.v3/directives.tcl
new file mode 100644
index 0000000..504c4bb
--- /dev/null
+++ b/Sobel/sobel.v3/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
+go extract
diff --git a/Sobel/sobel.v3/messages.txt b/Sobel/sobel.v3/messages.txt
new file mode 100644
index 0000000..200504e
--- /dev/null
+++ b/Sobel/sobel.v3/messages.txt
@@ -0,0 +1,248 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.09 seconds, memory usage 192856kB, peak memory usage 315340kB (SOL-9)
+$PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.cpp(146): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+
+# Messages from "go compile"
+
+Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'sobel' specified by directive (CIN-52)
+Synthesizing routine 'sobel' (CIN-13)
+Inlining routine 'sobel' (CIN-14)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Optimizing block '/sobel' ... (CIN-4)
+Inout port 'vin' is only used as an input. (OPT-10)
+Inout port 'vout' is only used as an output. (OPT-11)
+Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+Design 'sobel' was read (SOL-1)
+Optimizing partition '/sobel': (Total ops = 504, Real ops = 116, Vars = 110) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 504, Real ops = 116, Vars = 108) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 464, Real ops = 108, Vars = 114) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 464, Real ops = 108, Vars = 116) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 464, Real ops = 108, Vars = 116) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 464, Real ops = 108, Vars = 114) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 400, Real ops = 107, Vars = 97) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 375, Real ops = 107, Vars = 96) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 375, Real ops = 107, Vars = 96) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 375, Real ops = 107, Vars = 98) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 375, Real ops = 107, Vars = 98) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 355, Real ops = 105, Vars = 146) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 31) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 392, Real ops = 104, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 303, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 303, Real ops = 94, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 298, Real ops = 94, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+Completed transformation 'compile' on solution 'sobel.v3': elapsed time 2.14 seconds, memory usage 197424kB, peak memory usage 315340kB (SOL-9)
+Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'sobel.v3' (SOL-8)
+Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+Loop '/sobel/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/sobel/core': (Total ops = 484, Real ops = 157, Vars = 23) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 294, Real ops = 94, Vars = 17) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 291, Real ops = 94, Vars = 16) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 291, Real ops = 94, Vars = 16) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 303, Real ops = 94, Vars = 22) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 94, Vars = 22) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 282, Real ops = 91, Vars = 19) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 282, Real ops = 91, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 22) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 267, Real ops = 91, Vars = 32) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 270, Real ops = 91, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 227, Real ops = 88, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 227, Real ops = 88, Vars = 26) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 227, Real ops = 88, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 227, Real ops = 88, Vars = 26) (SOL-10)
+Design 'sobel' contains '156' real operations. (SOL-11)
+Optimizing partition '/sobel/core': (Total ops = 234, Real ops = 89, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 233, Real ops = 89, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 483, Real ops = 120, Vars = 171) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 277, Real ops = 106, Vars = 50) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 276, Real ops = 106, Vars = 49) (SOL-10)
+Completed transformation 'architect' on solution 'sobel.v3': elapsed time 4.01 seconds, memory usage 197796kB, peak memory usage 315340kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'sobel.v3' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 5175.50, 0.00, 5175.50 (CRAAS-11)
+Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5172.06, 0.00, 5172.06 (CRAAS-10)
+Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5121.26, 0.00, 5121.26 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 5121.26, 0.00, 5121.26 (CRAAS-12)
+Completed transformation 'allocate' on solution 'sobel.v3': elapsed time 0.58 seconds, memory usage 197796kB, peak memory usage 315340kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'sobel.v3' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 441, Real ops = 157, Vars = 120) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 431, Real ops = 156, Vars = 112) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 411, Real ops = 156, Vars = 115) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 373, Real ops = 152, Vars = 85) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 366, Real ops = 151, Vars = 84) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 380, Real ops = 151, Vars = 96) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 371, Real ops = 151, Vars = 89) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 370, Real ops = 151, Vars = 92) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 369, Real ops = 151, Vars = 88) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 383, Real ops = 151, Vars = 100) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 374, Real ops = 151, Vars = 93) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 369, Real ops = 151, Vars = 88) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 383, Real ops = 151, Vars = 100) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 374, Real ops = 151, Vars = 93) (SOL-10)
+Completed transformation 'schedule' on solution 'sobel.v3': elapsed time 1.89 seconds, memory usage 203124kB, peak memory usage 315340kB (SOL-9)
+Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'sobel.v3' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 645, Real ops = 191, Vars = 448) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 636, Real ops = 191, Vars = 441) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 567, Real ops = 190, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 558, Real ops = 190, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+Completed transformation 'dpfsm' on solution 'sobel.v3': elapsed time 0.42 seconds, memory usage 203124kB, peak memory usage 315340kB (SOL-9)
+
+# Messages from "go extract"
+
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'sobel.v3' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 457, Real ops = 215, Vars = 454) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 448, Real ops = 215, Vars = 447) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 78) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 71) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 415, Real ops = 196, Vars = 412) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 406, Real ops = 196, Vars = 405) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 415, Real ops = 196, Vars = 412) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 406, Real ops = 196, Vars = 405) (SOL-10)
+Reassigned operation ACC1:acc#61:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+Reassigned operation ACC1:acc#69:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+Reassigned operation ACC1:acc#65:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+Reassigned operation ACC1:acc#62:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+Reassigned operation ACC1:acc#70:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+Reassigned operation ACC1:acc#66:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/sobel': (Total ops = 415, Real ops = 196, Vars = 412) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 406, Real ops = 196, Vars = 405) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 322, Real ops = 174, Vars = 78) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 313, Real ops = 174, Vars = 71) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 322, Real ops = 174, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 313, Real ops = 174, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 322, Real ops = 174, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 313, Real ops = 174, Vars = 68) (SOL-10)
+Completed transformation 'extract' on solution 'sobel.v3': elapsed time 5.87 seconds, memory usage 203124kB, peak memory usage 315340kB (SOL-9)
diff --git a/Sobel/sobel.v3/reg_sharing.tcl b/Sobel/sobel.v3/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v3/reg_sharing.tcl
diff --git a/Sobel/sobel.v3/res_sharing.tcl b/Sobel/sobel.v3/res_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v3/res_sharing.tcl
diff --git a/Sobel/sobel.v3/rtl.rpt b/Sobel/sobel.v3/rtl.rpt
new file mode 100644
index 0000000..1c00727
--- /dev/null
+++ b/Sobel/sobel.v3/rtl.rpt
@@ -0,0 +1,843 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 14:11:10 +0000 2016                      
+
+Solution Settings: sobel.v3
+  Current state: extract
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       161  921601     921600            0  1          
+    Design Total:                     161  921601     921600            0  0          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(10,0,10,0,10)                       11.241                       0.000     11.241 1.301          1           1 
+    mgc_add(10,0,9,1,10)                        11.000                       0.000     11.000 1.303          1           0 
+    mgc_add(11,0,10,1,12)                       12.000                       0.000     12.000 1.208          2           2 
+    mgc_add(11,1,11,1,12)                       12.000                       0.000     12.000 1.206          6           9 
+    mgc_add(12,1,12,1,13)                       13.000                       0.000     13.000 1.272          5           2 
+    mgc_add(15,0,11,1,15)                       16.000                       0.000     16.000 1.633          0           3 
+    mgc_add(16,0,12,1,16)                       17.000                       0.000     17.000 1.696          6           6 
+    mgc_add(16,0,16,0,16)                       17.189                       0.000     17.189 1.690          3           3 
+    mgc_add(17,0,13,1,17)                       18.000                       0.000     18.000 1.758          3           0 
+    mgc_add(19,0,2,1,19)                        20.000                       0.000     20.000 1.908          1           1 
+    mgc_add(2,0,1,0,2)                           3.315                       0.000      3.315 0.658          0           1 
+    mgc_add(2,0,1,1,2)                           3.000                       0.000      3.000 0.658          0           4 
+    mgc_add(2,0,2,0,2)                           3.311                       0.000      3.311 0.653          1           1 
+    mgc_add(3,0,3,0,3)                           4.302                       0.000      4.302 0.761          1           0 
+    mgc_add(3,0,3,0,4)                           4.302                       0.000      4.302 0.761         12          12 
+    mgc_add(4,0,4,0,5)                           5.293                       0.000      5.293 0.854          6           6 
+    mgc_add(5,0,4,0,6)                           6.288                       0.000      6.288 0.940          3           3 
+    mgc_add(5,0,5,0,5)                           6.285                       0.000      6.285 0.938          6           6 
+    mgc_add(5,0,5,0,6)                           6.285                       0.000      6.285 0.938          0           1 
+    mgc_add(6,0,5,1,8)                           7.000                       0.000      7.000 0.693          3           3 
+    mgc_add(6,0,6,0,6)                           7.276                       0.000      7.276 1.016          3           3 
+    mgc_add(8,0,7,0,8)                           9.262                       0.000      9.262 1.165          1           1 
+    mgc_add(9,0,8,1,10)                         10.000                       0.000     10.000 1.072          3           3 
+    mgc_and(1,2)                                 0.730                       0.000      0.730 0.263          0           3 
+    mgc_and(19,2)                               13.867                       0.000     13.867 0.263          1           1 
+    mgc_and(2,2)                                 1.460                       0.000      1.460 0.263          2           1 
+    mgc_mul(2,0,9,0,11)                        330.250                       2.000     10.250 3.044          3           3 
+    mgc_mul(2,1,10,1,12)                       330.000                       2.000     10.000 3.087          6           6 
+    mgc_mul(3,0,6,0,9)                         330.250                       2.000     10.250 2.846          3           3 
+    mgc_mux(1,1,2)                               0.919                       0.000      0.919 0.369          2           1 
+    mgc_mux(10,2,4)                             22.259                       0.000     22.259 0.936          6           6 
+    mgc_mux(16,1,2)                             14.711                       0.000     14.711 0.369          6           6 
+    mgc_mux(19,1,2)                             17.469                       0.000     17.469 0.369          1           1 
+    mgc_mux(30,1,2)                             27.583                       0.000     27.583 0.369          0           1 
+    mgc_mux(90,1,2)                             82.748                       0.000     82.748 0.369          3           3 
+    mgc_nand(1,2)                                0.730                       0.000      0.730 0.268          0           3 
+    mgc_nor(1,2)                                 0.730                       0.000      0.730 0.263          0           2 
+    mgc_not(1)                                   0.000                       0.000      0.000 0.000          0          24 
+    mgc_not(10)                                  0.000                       0.000      0.000 0.000          0           9 
+    mgc_not(3)                                   0.000                       0.000      0.000 0.000          0          12 
+    mgc_or(1,2)                                  0.730                       0.000      0.730 0.268          0           2 
+    mgc_or(1,3)                                  1.054                       0.000      1.054 0.425          0           1 
+    mgc_or(10,2)                                 7.298                       0.000      7.298 0.268          1           1 
+    mgc_or(2,2)                                  1.460                       0.000      1.460 0.268          1           0 
+    mgc_or(6,2)                                  4.379                       0.000      4.379 0.268          1           1 
+    mgc_reg_pos(1,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           9 
+    mgc_reg_pos(11,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(16,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           6 
+    mgc_reg_pos(19,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(2,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(30,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(5,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(6,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_reg_pos(9,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(90,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           3 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,90)                            0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(2,30)                         0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):            5150.657                      24.000   1311.000                              
+    
+  Area Scores
+                      Post-Scheduling   Post-DP & FSM Post-Assignment 
+    ----------------- --------------- --------------- ---------------
+    Total Area Score:   5121.3          5409.2          5150.7        
+    Total Reg:             0.0             0.0             0.0        
+                                                                      
+    DataPath:           5121.3 (100%)   5409.2 (100%)   5150.7 (100%) 
+      MUX:               489.4  (10%)    773.6  (14%)    516.0  (10%) 
+      FUNC:             4602.0  (90%)   4600.3  (85%)   4599.3  (89%) 
+      LOGIC:              29.9   (1%)     35.4   (1%)     35.4   (1%) 
+      BUFFER:              0.0             0.0             0.0        
+      MEM:                 0.0             0.0             0.0        
+      ROM:                 0.0             0.0             0.0        
+      REG:                 0.0             0.0             0.0        
+                                                                      
+    
+    FSM:                   0.0             0.0             0.0        
+      FSM-REG:             0.0             0.0             0.0        
+      FSM-COMB:            0.0             0.0             0.0        
+                                                                      
+    
+  Register-to-Variable Mappings
+    Register                        Size(bits) Gated Register CG Opt Done Variables                                             
+    ------------------------------- ---------- -------------- ----------- -----------------------------------------------------
+    regs.regs(0).sva                        90         Y                  regs.regs(0).sva                                      
+    regs.regs(1).sva                        90         Y                  regs.regs(1).sva                                      
+    regs.regs(2).lpi#1.dfm                  90         Y                  regs.regs(2).lpi#1.dfm                                
+    vout:rsc:mgc_out_stdreg.d               30         Y                  vout:rsc:mgc_out_stdreg.d                             
+    FRAME:p#1.lpi#1                         19         Y                  FRAME:p#1.lpi#1                                       
+    b(0).sva#1                              16         Y                  b(0).sva#1                                            
+    b(2).sva#1                              16         Y                  b(2).sva#1                                            
+    g(0).sva#1                              16         Y                  g(0).sva#1                                            
+    g(2).sva#1                              16         Y                  g(2).sva#1                                            
+    r(0).sva#1                              16         Y                  r(0).sva#1                                            
+    r(2).sva#1                              16         Y                  r(2).sva#1                                            
+    FRAME:mul#2.itm#1                       11         Y                  FRAME:mul#2.itm#1                                     
+    FRAME:mul#4.itm#1                       11         Y                  FRAME:mul#4.itm#1                                     
+    FRAME:mul#1.itm#1                        9         Y                  FRAME:mul#1.itm#1                                     
+    FRAME:mul#3.itm#1                        9         Y                  FRAME:mul#3.itm#1                                     
+    FRAME:mul#5.itm#1                        9         Y                  FRAME:mul#5.itm#1                                     
+    FRAME:acc#41.itm#3                       6         Y                  FRAME:acc#41.itm#3                                    
+    blue:slc(blue#2.sg1).itm#1               6         Y                  blue:slc(blue#2.sg1).itm#1                            
+    green:slc(green#2.sg1).itm#1             6         Y                  green:slc(green#2.sg1).itm#1                          
+    red:slc(red#2.sg1).itm#1                 6         Y                  red:slc(red#2.sg1).itm#1                              
+    FRAME:acc#18.itm#1                       5         Y                  FRAME:acc#18.itm#1                                    
+    FRAME:acc#30.itm#1                       5         Y                  FRAME:acc#30.itm#1                                    
+    FRAME:acc#37.itm#1                       5         Y                  FRAME:acc#37.itm#1                                    
+    FRAME:acc#41.itm#1.sg1                   2         Y                  FRAME:acc#41.itm#1.sg1                                
+    FRAME:acc#41.itm#1.sg2                   2         Y                  FRAME:acc#41.itm#1.sg2                                
+    i#6.sva#1                                2         Y                  i#6.sva#1                                             
+    FRAME:slc(acc.imod#2)#4.itm#1            1         Y                  FRAME:slc(acc.imod#2)#4.itm#1                         
+    FRAME:slc(acc.imod#4)#4.itm#1            1         Y                  FRAME:slc(acc.imod#4)#4.itm#1                         
+    FRAME:slc(acc.imod)#4.itm#1              1         Y                  FRAME:slc(acc.imod)#4.itm#1                           
+    blue:slc(blue#2.sg1)#12.itm#1            1         Y                  blue:slc(blue#2.sg1)#12.itm#1                         
+    exit:FRAME#1.sva                         1         Y                  exit:FRAME#1.sva                                      
+    exit:FRAME.lpi#1.dfm#1                   1         Y                  exit:FRAME.lpi#1.dfm#1                                
+    exit:FRAME:for.sva#1.st#1                1         Y                  exit:FRAME:for.sva#1.st#1                             
+    green:slc(green#2.sg1)#12.itm#1          1         Y                  green:slc(green#2.sg1)#12.itm#1                       
+    main.stage_0#2                           1         Y                  main.stage_0#2                                        
+                                                                                                                                
+    Total:                                 518            518           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  15.796510999999999
+      Slack:      4.203489000000001
+      
+      Path                                               Startpoint                                Endpoint                           Delay   Slack   
+      -------------------------------------------------- ----------------------------------------- ---------------------------------- ------- -------
+      1                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)                                                                                                 0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva).itm                                                                                             0.0000  9.6738  
+        sobel:core/FRAME:acc#8                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#8.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1.itm                                                                                            0.0000  13.2445 
+        sobel:core/conc#129                                                                                                           0.0000  13.2445 
+        sobel:core/conc#129.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      2                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#2                                                                                               0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#2.itm                                                                                           0.0000  9.6738  
+        sobel:core/FRAME:not#2                           mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#2.itm                                                                                                    0.0000  9.6738  
+        sobel:core/FRAME:acc#8                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#8.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1.itm                                                                                            0.0000  13.2445 
+        sobel:core/conc#129                                                                                                           0.0000  13.2445 
+        sobel:core/conc#129.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      3                                                  sobel:core/reg(exit:FRAME#1.sva)          sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME#1.sva)                 mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME#1.sva                                                                                                   0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#2                                                                                               0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#2.itm                                                                                           0.0000  9.6738  
+        sobel:core/FRAME:not#2                           mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#2.itm                                                                                                    0.0000  9.6738  
+        sobel:core/FRAME:acc#8                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#8.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1.itm                                                                                            0.0000  13.2445 
+        sobel:core/conc#129                                                                                                           0.0000  13.2445 
+        sobel:core/conc#129.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      4                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#18.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#16:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#16:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#7                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#7.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#12                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/g(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#66                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#66.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#47                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#47.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#44                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#44.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc#1                                                                                                         0.0000  9.6738  
+        sobel:core/green#2.sg1.sva                                                                                                    0.0000  9.6738  
+        sobel:core/slc(green#2.sg1.sva)#1                                                                                             0.0000  9.6738  
+        sobel:core/slc(green#2.sg1.sva)#1.itm                                                                                         0.0000  9.6738  
+        sobel:core/FRAME:acc#13                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#13.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#15                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#15.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#16.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc#2                                 mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod#2.sva                                                                                                     0.0000  13.2445 
+        sobel:core/slc(acc.imod#2.sva)#1                                                                                              0.0000  13.2445 
+        sobel:core/slc(acc.imod#2.sva)#1.itm                                                                                          0.0000  13.2445 
+        sobel:core/conc#133                                                                                                           0.0000  13.2445 
+        sobel:core/conc#133.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#23                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#23.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#5                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#5.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#43                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#43.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#132                                                                                                           0.0000  14.1821 
+        sobel:core/conc#132.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#17                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#17.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#18                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#18.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#18.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      5                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#18.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#2                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(1).sva.dfm:mx0                                                                                           0.0000  0.6315  
+        sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1                                                                                    0.0000  0.6315  
+        sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm                                                                                0.0000  0.6315  
+        sobel:core/regs.operator[]#16:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#16:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#7                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#7.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#12                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/g(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#66                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#66.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#47                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#47.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#44                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#44.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc#1                                                                                                         0.0000  9.6738  
+        sobel:core/green#2.sg1.sva                                                                                                    0.0000  9.6738  
+        sobel:core/slc(green#2.sg1.sva)#1                                                                                             0.0000  9.6738  
+        sobel:core/slc(green#2.sg1.sva)#1.itm                                                                                         0.0000  9.6738  
+        sobel:core/FRAME:acc#13                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#13.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#15                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#15.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#16.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc#2                                 mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod#2.sva                                                                                                     0.0000  13.2445 
+        sobel:core/slc(acc.imod#2.sva)#1                                                                                              0.0000  13.2445 
+        sobel:core/slc(acc.imod#2.sva)#1.itm                                                                                          0.0000  13.2445 
+        sobel:core/conc#133                                                                                                           0.0000  13.2445 
+        sobel:core/conc#133.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#23                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#23.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#5                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#5.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#43                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#43.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#132                                                                                                           0.0000  14.1821 
+        sobel:core/conc#132.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#17                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#17.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#18                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#18.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#18.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      6                                                  sobel:core/reg(exit:FRAME#1.sva)          sobel:core/reg(FRAME:acc#18.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME#1.sva)                 mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME#1.sva                                                                                                   0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#2                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(1).sva.dfm:mx0                                                                                           0.0000  0.6315  
+        sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1                                                                                    0.0000  0.6315  
+        sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm                                                                                0.0000  0.6315  
+        sobel:core/regs.operator[]#16:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#16:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#7                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#7.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#12                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/g(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#66                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#66.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#47                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#47.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#44                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#44.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc#1                                                                                                         0.0000  9.6738  
+        sobel:core/green#2.sg1.sva                                                                                                    0.0000  9.6738  
+        sobel:core/slc(green#2.sg1.sva)#1                                                                                             0.0000  9.6738  
+        sobel:core/slc(green#2.sg1.sva)#1.itm                                                                                         0.0000  9.6738  
+        sobel:core/FRAME:acc#13                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#13.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#15                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#15.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#16.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc#2                                 mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod#2.sva                                                                                                     0.0000  13.2445 
+        sobel:core/slc(acc.imod#2.sva)#1                                                                                              0.0000  13.2445 
+        sobel:core/slc(acc.imod#2.sva)#1.itm                                                                                          0.0000  13.2445 
+        sobel:core/conc#133                                                                                                           0.0000  13.2445 
+        sobel:core/conc#133.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#23                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#23.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#5                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#5.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#43                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#43.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#132                                                                                                           0.0000  14.1821 
+        sobel:core/conc#132.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#17                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#17.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#18                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#18.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#18.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      7                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#3                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(0).sva.dfm:mx0                                                                                           0.0000  0.6315  
+        sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5                                                                                    0.0000  0.6315  
+        sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm                                                                                0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#2                                                                                               0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#2.itm                                                                                           0.0000  9.6738  
+        sobel:core/FRAME:not#2                           mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#2.itm                                                                                                    0.0000  9.6738  
+        sobel:core/FRAME:acc#8                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#8.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1.itm                                                                                            0.0000  13.2445 
+        sobel:core/conc#129                                                                                                           0.0000  13.2445 
+        sobel:core/conc#129.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      8                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#20                                                                                              0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#20.itm                                                                                          0.0000  9.6738  
+        sobel:core/FRAME:not#35                          mgc_not_1                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#35.itm                                                                                                   0.0000  9.6738  
+        sobel:core/conc#140                                                                                                           0.0000  9.6738  
+        sobel:core/conc#140.itm                                                                                                       0.0000  9.6738  
+        sobel:core/FRAME:acc#7                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#7.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1.itm                                                                                            0.0000  13.2445 
+        sobel:core/conc#129                                                                                                           0.0000  13.2445 
+        sobel:core/conc#129.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      9                                                  sobel:core/reg(exit:FRAME#1.sva)          sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME#1.sva)                 mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME#1.sva                                                                                                   0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#20                                                                                              0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)#20.itm                                                                                          0.0000  9.6738  
+        sobel:core/FRAME:not#35                          mgc_not_1                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#35.itm                                                                                                   0.0000  9.6738  
+        sobel:core/conc#140                                                                                                           0.0000  9.6738  
+        sobel:core/conc#140.itm                                                                                                       0.0000  9.6738  
+        sobel:core/FRAME:acc#7                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#7.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#1.itm                                                                                            0.0000  13.2445 
+        sobel:core/conc#129                                                                                                           0.0000  13.2445 
+        sobel:core/conc#129.itm                                                                                                       0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      10                                                 sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#37.itm#1) 15.7965 4.2035  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#62                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#62.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC1:acc#43                           mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/ACC1:acc#43.itm                                                                                                    0.0000  9.6738  
+        sobel:core/ACC2:slc                                                                                                           0.0000  9.6738  
+        sobel:core/red#2.sg1.sva                                                                                                      0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva)                                                                                                 0.0000  9.6738  
+        sobel:core/slc(red#2.sg1.sva).itm                                                                                             0.0000  9.6738  
+        sobel:core/FRAME:acc#8                           mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#8.itm                                                                                                    0.0000  10.4347 
+        sobel:core/FRAME:acc#10                          mgc_add_4_0_4_0_5                                                            0.8536  11.2882 
+        sobel:core/FRAME:acc#10.itm                                                                                                   0.0000  11.2882 
+        sobel:core/FRAME:acc#11                          mgc_add_5_0_4_0_6                                                            0.9400  12.2283 
+        sobel:core/FRAME:acc#11.itm                                                                                                   0.0000  12.2283 
+        sobel:core/acc                                   mgc_add_6_0_6_0_6                                                            1.0162  13.2445 
+        sobel:core/acc.imod.sva                                                                                                       0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#2                                                                                                0.0000  13.2445 
+        sobel:core/slc(acc.imod.sva)#2.itm                                                                                            0.0000  13.2445 
+        sobel:core/FRAME:not#5                           mgc_not_3                                                                    0.0000  13.2445 
+        sobel:core/FRAME:not#5.itm                                                                                                    0.0000  13.2445 
+        sobel:core/FRAME:conc#33                                                                                                      0.0000  13.2445 
+        sobel:core/FRAME:conc#33.itm                                                                                                  0.0000  13.2445 
+        sobel:core/FRAME:acc#42                          mgc_add_5_0_5_0_5                                                            0.9376  14.1821 
+        sobel:core/FRAME:acc#42.itm                                                                                                   0.0000  14.1821 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.1821 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39                          mgc_not_1                                                                    0.0000  14.1821 
+        sobel:core/FRAME:not#39.itm                                                                                                   0.0000  14.1821 
+        sobel:core/conc#128                                                                                                           0.0000  14.1821 
+        sobel:core/conc#128.itm                                                                                                       0.0000  14.1821 
+        sobel:core/FRAME:acc#36                          mgc_add_3_0_3_0_4                                                            0.7609  14.9430 
+        sobel:core/FRAME:acc#36.itm                                                                                                   0.0000  14.9430 
+        sobel:core/FRAME:acc#37                          mgc_add_4_0_4_0_5                                                            0.8536  15.7965 
+        sobel:core/FRAME:acc#37.itm                                                                                                   0.0000  15.7965 
+        sobel:core/reg(FRAME:acc#37.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  15.7965 
+                                                                                                                                                      
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                        Port                         Slack (Delay) Messages 
+      ----------------------------------------------- -------------------------- ------- ------- --------
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)       mux.itm                    14.1802  5.8198          
+      sobel:core/reg(FRAME:acc#41.itm#1.sg2)          FRAME:acc#43.itm            6.6243 13.3757          
+      sobel:core/reg(FRAME:acc#41.itm#1.sg1)          slc(FRAME:mul.sdt)#2.itm    7.2821 12.7179          
+      sobel:core/reg(FRAME:acc#41.itm#3)              FRAME:acc#44.itm            6.3445 13.6555          
+      sobel:core/reg(FRAME:mul#1.itm#1)               FRAME:mul#1.itm             7.4801 12.5199          
+      sobel:core/reg(red:slc(red#2.sg1).itm#1)        slc(red#2.sg1.sva)#1.itm   10.3262  9.6738          
+      sobel:core/reg(FRAME:acc#37.itm#1)              FRAME:acc#37.itm            4.2035 15.7965          
+      sobel:core/reg(FRAME:slc(acc.imod)#4.itm#1)     slc(acc.imod.sva).itm       6.7555 13.2445          
+      sobel:core/reg(FRAME:mul#4.itm#1)               FRAME:mul#4.itm             7.2821 12.7179          
+      sobel:core/reg(FRAME:mul#5.itm#1)               FRAME:mul#5.itm             7.4801 12.5199          
+      sobel:core/reg(blue:slc(blue#2.sg1).itm#1)      slc(blue#2.sg1.sva)#2.itm  10.3262  9.6738          
+      sobel:core/reg(FRAME:acc#30.itm#1)              FRAME:acc#30.itm            4.2035 15.7965          
+      sobel:core/reg(FRAME:slc(acc.imod#4)#4.itm#1)   slc(acc.imod#4.sva).itm     6.7555 13.2445          
+      sobel:core/reg(blue:slc(blue#2.sg1)#12.itm#1)   slc(blue#2.sg1.sva).itm    10.3262  9.6738          
+      sobel:core/reg(FRAME:mul#2.itm#1)               FRAME:mul#2.itm             7.2821 12.7179          
+      sobel:core/reg(FRAME:mul#3.itm#1)               FRAME:mul#3.itm             7.4801 12.5199          
+      sobel:core/reg(green:slc(green#2.sg1).itm#1)    slc(green#2.sg1.sva)#2.itm 10.3262  9.6738          
+      sobel:core/reg(FRAME:acc#18.itm#1)              FRAME:acc#18.itm            4.2035 15.7965          
+      sobel:core/reg(FRAME:slc(acc.imod#2)#4.itm#1)   slc(acc.imod#2.sva).itm     6.7555 13.2445          
+      sobel:core/reg(green:slc(green#2.sg1)#12.itm#1) slc(green#2.sg1.sva).itm   10.3262  9.6738          
+      sobel:core/reg(exit:FRAME:for.sva#1.st#1)       FRAME:for:not#7.itm        18.1594  1.8406          
+      sobel:core/reg(i#6.sva#1)                       i#6.sva#2                  17.5279  2.4721          
+      sobel:core/reg(exit:FRAME#1.sva)                FRAME:and.itm              16.0328  3.9672          
+      sobel:core/reg(main.stage_0#2)                  Cn1_1#2                    20.0000  0.0000          
+      sobel:core/reg(regs.regs(2).lpi#1.dfm)          regs.regs(2).lpi#1.dfm:mx0  4.2035 15.7965          
+      sobel:core/reg(regs.regs(1).sva)                regs.regs(1).sva.dfm:mx0    4.2035 15.7965          
+      sobel:core/reg(regs.regs(0).sva)                regs.regs(0).sva.dfm:mx0    4.2035 15.7965          
+      sobel:core/reg(exit:FRAME.lpi#1.dfm#1)          exit:FRAME.lpi#1.dfm#1:mx0 16.0328  3.9672          
+      sobel:core/reg(b(2).sva#1)                      b(2).sva#3                  4.2035 15.7965          
+      sobel:core/reg(b(0).sva#1)                      b(0).sva#3                  5.8368 14.1632          
+      sobel:core/reg(g(2).sva#1)                      g(2).sva#3                  4.2035 15.7965          
+      sobel:core/reg(g(0).sva#1)                      g(0).sva#3                  5.8368 14.1632          
+      sobel:core/reg(r(2).sva#1)                      r(2).sva#3                  4.2035 15.7965          
+      sobel:core/reg(r(0).sva#1)                      r(0).sva#3                  5.8368 14.1632          
+      sobel:core/reg(FRAME:p#1.lpi#1)                 mux#5.itm                  17.4604  2.5396          
+      sobel                                           vout:rsc.z                 20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                   19     1 
+    -                   16     9 
+    -                   15     3 
+    -                   13     2 
+    -                   12    11 
+    -                   10     4 
+    -                    8     4 
+    -                    6     7 
+    -                    5    12 
+    -                    4    12 
+    -                    2     6 
+    and                          
+    -                    2     5 
+    mul                          
+    -                   12     6 
+    -                   11     3 
+    -                    9     3 
+    mux                          
+    -                    2     6 
+    -                    1    12 
+    nand                         
+    -                    2     3 
+    nor                          
+    -                    2     2 
+    not                          
+    -                   10     9 
+    -                    3    12 
+    -                    1    24 
+    or                           
+    -                    3     1 
+    -                    2     4 
+    read_port                    
+    -                   90     1 
+    reg                          
+    -                   90     3 
+    -                   30     1 
+    -                   19     1 
+    -                   16     6 
+    -                   11     2 
+    -                    9     3 
+    -                    6     4 
+    -                    5     3 
+    -                    2     3 
+    -                    1     9 
+    write_port                   
+    -                   30     1 
+    
+  End of Report
diff --git a/Sobel/sobel.v3/rtl.v b/Sobel/sobel.v3/rtl.v
new file mode 100644
index 0000000..42fb7a3
--- /dev/null
+++ b/Sobel/sobel.v3/rtl.v
@@ -0,0 +1,845 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:11:10 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  wire and_dcpl;
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [89:0] regs_regs_2_lpi_1_dfm;
+  reg [15:0] r_0_sva_1;
+  reg [15:0] g_0_sva_1;
+  reg [15:0] b_0_sva_1;
+  reg [15:0] r_2_sva_1;
+  reg [15:0] g_2_sva_1;
+  reg [15:0] b_2_sva_1;
+  reg [1:0] i_6_sva_1;
+  reg exit_FRAME_lpi_1_dfm_1;
+  reg [10:0] FRAME_mul_2_itm_1;
+  wire [21:0] nl_FRAME_mul_2_itm_1;
+  reg [8:0] FRAME_mul_3_itm_1;
+  wire [17:0] nl_FRAME_mul_3_itm_1;
+  reg [5:0] green_slc_green_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_18_itm_1;
+  wire [5:0] nl_FRAME_acc_18_itm_1;
+  reg FRAME_slc_acc_imod_2_4_itm_1;
+  reg green_slc_green_2_sg1_12_itm_1;
+  reg [10:0] FRAME_mul_4_itm_1;
+  wire [21:0] nl_FRAME_mul_4_itm_1;
+  reg [8:0] FRAME_mul_5_itm_1;
+  wire [17:0] nl_FRAME_mul_5_itm_1;
+  reg [5:0] blue_slc_blue_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_30_itm_1;
+  wire [5:0] nl_FRAME_acc_30_itm_1;
+  reg FRAME_slc_acc_imod_4_4_itm_1;
+  reg blue_slc_blue_2_sg1_12_itm_1;
+  reg [8:0] FRAME_mul_1_itm_1;
+  wire [17:0] nl_FRAME_mul_1_itm_1;
+  reg [5:0] red_slc_red_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_37_itm_1;
+  wire [5:0] nl_FRAME_acc_37_itm_1;
+  reg FRAME_slc_acc_imod_4_itm_1;
+  reg exit_FRAME_for_sva_1_st_1;
+  reg main_stage_0_2;
+  reg [1:0] FRAME_acc_41_itm_1_sg2;
+  wire [2:0] nl_FRAME_acc_41_itm_1_sg2;
+  reg [1:0] FRAME_acc_41_itm_1_sg1;
+  reg [5:0] FRAME_acc_41_itm_3;
+  wire [6:0] nl_FRAME_acc_41_itm_3;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+  wire [11:0] FRAME_acc_3_psp_sva;
+  wire [13:0] nl_FRAME_acc_3_psp_sva;
+  wire [11:0] FRAME_acc_4_psp_sva;
+  wire [13:0] nl_FRAME_acc_4_psp_sva;
+  wire [1:0] i_6_sva_2;
+  wire [2:0] nl_i_6_sva_2;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire exit_FRAME_for_lpi_1_dfm;
+  wire [89:0] regs_regs_2_lpi_1_dfm_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire exit_FRAME_lpi_1_dfm_1_mx0;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [5:0] acc_imod_sva;
+  wire [7:0] nl_acc_imod_sva;
+  wire [9:0] FRAME_mul_sdt;
+  wire [19:0] nl_FRAME_mul_sdt;
+  wire [5:0] acc_imod_4_sva;
+  wire [7:0] nl_acc_imod_4_sva;
+  wire [5:0] acc_imod_2_sva;
+  wire [7:0] nl_acc_imod_2_sva;
+  wire [15:0] b_2_sva_3;
+  wire [16:0] nl_b_2_sva_3;
+  wire [15:0] b_0_sva_3;
+  wire [16:0] nl_b_0_sva_3;
+  wire [15:0] g_2_sva_3;
+  wire [16:0] nl_g_2_sva_3;
+  wire [15:0] g_0_sva_3;
+  wire [16:0] nl_g_0_sva_3;
+  wire [15:0] r_2_sva_3;
+  wire [16:0] nl_r_2_sva_3;
+  wire [15:0] r_0_sva_3;
+  wire [16:0] nl_r_0_sva_3;
+  wire FRAME_for_nor_cse;
+  wire [15:0] ACC1_acc_43_itm;
+  wire [16:0] nl_ACC1_acc_43_itm;
+  wire [15:0] ACC1_acc_45_itm;
+  wire [16:0] nl_ACC1_acc_45_itm;
+  wire [15:0] ACC1_acc_44_itm;
+  wire [16:0] nl_ACC1_acc_44_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_3_itm;
+
+  wire[15:0] FRAME_for_mux_10_nl;
+  wire[9:0] regs_operator_17_mux_nl;
+  wire[15:0] FRAME_for_mux_9_nl;
+  wire[9:0] regs_operator_11_mux_nl;
+  wire[15:0] FRAME_for_mux_8_nl;
+  wire[9:0] regs_operator_16_mux_nl;
+  wire[15:0] FRAME_for_mux_7_nl;
+  wire[9:0] regs_operator_10_mux_nl;
+  wire[15:0] FRAME_for_mux_6_nl;
+  wire[9:0] regs_operator_15_mux_nl;
+  wire[15:0] FRAME_for_mux_5_nl;
+  wire[9:0] regs_operator_9_mux_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_3_psp_sva = (conv_u2s_11_12(FRAME_mul_2_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_3_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(green_slc_green_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_18_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_2_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({green_slc_green_2_sg1_12_itm_1
+      , 3'b0 , ({{2{green_slc_green_2_sg1_12_itm_1}}, green_slc_green_2_sg1_12_itm_1})
+      , 1'b0 , green_slc_green_2_sg1_12_itm_1}));
+  assign FRAME_acc_3_psp_sva = nl_FRAME_acc_3_psp_sva[11:0];
+  assign nl_FRAME_acc_4_psp_sva = (conv_u2s_11_12(FRAME_mul_4_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_5_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(blue_slc_blue_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_30_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_4_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({blue_slc_blue_2_sg1_12_itm_1
+      , 3'b0 , ({{2{blue_slc_blue_2_sg1_12_itm_1}}, blue_slc_blue_2_sg1_12_itm_1})
+      , 1'b0 , blue_slc_blue_2_sg1_12_itm_1}));
+  assign FRAME_acc_4_psp_sva = nl_FRAME_acc_4_psp_sva[11:0];
+  assign nl_FRAME_for_acc_itm = i_6_sva_2 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  assign nl_i_6_sva_2 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_2 = nl_i_6_sva_2[1:0];
+  assign i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm));
+  assign exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva;
+  assign regs_regs_2_lpi_1_dfm_mx0 = MUX_v_90_2_2({regs_regs_1_sva , regs_regs_2_lpi_1_dfm},
+      and_dcpl);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_dcpl);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_dcpl);
+  assign exit_FRAME_lpi_1_dfm_1_mx0 = MUX_s_1_2_2({(~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+      + 8'b10110101)))) , (exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm))},
+      FRAME_for_acc_itm[1]);
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign nl_acc_imod_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_43_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_43_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_43_itm[15])) , 1'b1 , (~ (ACC1_acc_43_itm[15]))}) + conv_u2u_2_4(ACC1_acc_43_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_43_itm[3:1]) + conv_u2u_3_4(~ (ACC1_acc_43_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_sva = nl_acc_imod_sva[5:0];
+  assign nl_ACC1_acc_43_itm = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[59:50])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[59:50])
+      , 1'b1})))) + (r_2_sva_3[15:1])) , (readslicef_2_1_1((({(r_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + r_0_sva_3;
+  assign ACC1_acc_43_itm = nl_ACC1_acc_43_itm[15:0];
+  assign nl_FRAME_mul_sdt = conv_u2u_2_10(ACC1_acc_43_itm[14:13]) * 10'b111000111;
+  assign FRAME_mul_sdt = nl_FRAME_mul_sdt[9:0];
+  assign nl_ACC1_acc_45_itm = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[39:30])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[39:30])
+      , 1'b1})))) + (b_2_sva_3[15:1])) , (readslicef_2_1_1((({(b_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + b_0_sva_3;
+  assign ACC1_acc_45_itm = nl_ACC1_acc_45_itm[15:0];
+  assign nl_acc_imod_4_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_45_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_45_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_45_itm[15])) , 1'b1 , (~ (ACC1_acc_45_itm[15]))}) + conv_u2u_2_4(ACC1_acc_45_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_45_itm[3:1]) + conv_u2u_3_4(~ (ACC1_acc_45_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_4_sva = nl_acc_imod_4_sva[5:0];
+  assign nl_ACC1_acc_44_itm = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[49:40])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[49:40])
+      , 1'b1})))) + (g_2_sva_3[15:1])) , (readslicef_2_1_1((({(g_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + g_0_sva_3;
+  assign ACC1_acc_44_itm = nl_ACC1_acc_44_itm[15:0];
+  assign nl_acc_imod_2_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_44_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_44_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC1_acc_44_itm[15])) , 1'b1 , (~ (ACC1_acc_44_itm[15]))}) + conv_u2u_2_4(ACC1_acc_44_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_44_itm[3:1]) + conv_u2u_3_4(~ (ACC1_acc_44_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_2_sva = nl_acc_imod_2_sva[5:0];
+  assign FRAME_for_mux_10_nl = MUX_v_16_2_2({b_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[69:60])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[69:60])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+      , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_mx0[69:60]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_b_2_sva_3 = (FRAME_for_mux_10_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_17_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign b_2_sva_3 = nl_b_2_sva_3[15:0];
+  assign FRAME_for_mux_9_nl = MUX_v_16_2_2({b_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[9:0])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[9:0])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_11_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0]) ,
+      (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_mx0[9:0]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_b_0_sva_3 = (FRAME_for_mux_9_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_11_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign b_0_sva_3 = nl_b_0_sva_3[15:0];
+  assign FRAME_for_mux_8_nl = MUX_v_16_2_2({g_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[79:70])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[79:70])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+      , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_mx0[79:70]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_g_2_sva_3 = (FRAME_for_mux_8_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_16_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign g_2_sva_3 = nl_g_2_sva_3[15:0];
+  assign FRAME_for_mux_7_nl = MUX_v_16_2_2({g_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[19:10])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[19:10])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_10_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+      , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_mx0[19:10]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_g_0_sva_3 = (FRAME_for_mux_7_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_10_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign g_0_sva_3 = nl_g_0_sva_3[15:0];
+  assign FRAME_for_mux_6_nl = MUX_v_16_2_2({r_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[89:80])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[89:80])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+      , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_mx0[89:80]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_r_2_sva_3 = (FRAME_for_mux_6_nl) + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_15_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign r_2_sva_3 = nl_r_2_sva_3[15:0];
+  assign FRAME_for_mux_5_nl = MUX_v_16_2_2({r_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[29:20])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[29:20])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_9_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+      , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_mx0[29:20]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_r_0_sva_3 = (FRAME_for_mux_5_nl) + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_9_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign r_0_sva_3 = nl_r_0_sva_3[15:0];
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_3_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) |
+      FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+  assign and_dcpl = ~(exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva);
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      FRAME_acc_41_itm_1_sg2 <= 2'b0;
+      FRAME_acc_41_itm_1_sg1 <= 2'b0;
+      FRAME_acc_41_itm_3 <= 6'b0;
+      FRAME_mul_1_itm_1 <= 9'b0;
+      red_slc_red_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_37_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_4_itm_1 <= 1'b0;
+      FRAME_mul_4_itm_1 <= 11'b0;
+      FRAME_mul_5_itm_1 <= 9'b0;
+      blue_slc_blue_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_30_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_4_4_itm_1 <= 1'b0;
+      blue_slc_blue_2_sg1_12_itm_1 <= 1'b0;
+      FRAME_mul_2_itm_1 <= 11'b0;
+      FRAME_mul_3_itm_1 <= 9'b0;
+      green_slc_green_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_18_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_2_4_itm_1 <= 1'b0;
+      green_slc_green_2_sg1_12_itm_1 <= 1'b0;
+      exit_FRAME_for_sva_1_st_1 <= 1'b0;
+      i_6_sva_1 <= 2'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_2_lpi_1_dfm <= 90'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_1 <= 1'b0;
+      b_2_sva_1 <= 16'b0;
+      b_0_sva_1 <= 16'b0;
+      g_2_sva_1 <= 16'b0;
+      g_0_sva_1 <= 16'b0;
+      r_2_sva_1 <= 16'b0;
+      r_0_sva_1 <= 16'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({({((({FRAME_acc_41_itm_1_sg2 ,
+            FRAME_acc_41_itm_1_sg1 , FRAME_acc_41_itm_3}) + (conv_u2s_9_10(FRAME_mul_1_itm_1)
+            + conv_s2s_8_10(conv_u2s_6_8(red_slc_red_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_37_itm_1
+            + ({4'b1001 , FRAME_slc_acc_imod_4_itm_1}))))) | ({8'b0 , (FRAME_acc_3_psp_sva[11:10])}))
+            , (FRAME_acc_3_psp_sva[9:6]) , ((FRAME_acc_3_psp_sva[5:0]) | ({4'b0 ,
+            (FRAME_acc_4_psp_sva[11:10])})) , (FRAME_acc_4_psp_sva[9:0])}) , vout_rsc_mgc_out_stdreg_d},
+            ~(exit_FRAME_for_sva_1_st_1 & main_stage_0_2));
+        FRAME_acc_41_itm_1_sg2 <= nl_FRAME_acc_41_itm_1_sg2[1:0];
+        FRAME_acc_41_itm_1_sg1 <= FRAME_mul_sdt[7:6];
+        FRAME_acc_41_itm_3 <= nl_FRAME_acc_41_itm_3[5:0];
+        FRAME_mul_1_itm_1 <= nl_FRAME_mul_1_itm_1[8:0];
+        red_slc_red_2_sg1_itm_1 <= ACC1_acc_43_itm[9:4];
+        FRAME_acc_37_itm_1 <= nl_FRAME_acc_37_itm_1[4:0];
+        FRAME_slc_acc_imod_4_itm_1 <= acc_imod_sva[5];
+        FRAME_mul_4_itm_1 <= nl_FRAME_mul_4_itm_1[10:0];
+        FRAME_mul_5_itm_1 <= nl_FRAME_mul_5_itm_1[8:0];
+        blue_slc_blue_2_sg1_itm_1 <= ACC1_acc_45_itm[9:4];
+        FRAME_acc_30_itm_1 <= nl_FRAME_acc_30_itm_1[4:0];
+        FRAME_slc_acc_imod_4_4_itm_1 <= acc_imod_4_sva[5];
+        blue_slc_blue_2_sg1_12_itm_1 <= ACC1_acc_45_itm[15];
+        FRAME_mul_2_itm_1 <= nl_FRAME_mul_2_itm_1[10:0];
+        FRAME_mul_3_itm_1 <= nl_FRAME_mul_3_itm_1[8:0];
+        green_slc_green_2_sg1_itm_1 <= ACC1_acc_44_itm[9:4];
+        FRAME_acc_18_itm_1 <= nl_FRAME_acc_18_itm_1[4:0];
+        FRAME_slc_acc_imod_2_4_itm_1 <= acc_imod_2_sva[5];
+        green_slc_green_2_sg1_12_itm_1 <= ACC1_acc_44_itm[15];
+        exit_FRAME_for_sva_1_st_1 <= ~ (FRAME_for_acc_itm[1]);
+        i_6_sva_1 <= i_6_sva_2;
+        exit_FRAME_1_sva <= (~ (FRAME_for_acc_itm[1])) & exit_FRAME_lpi_1_dfm_1_mx0;
+        main_stage_0_2 <= 1'b1;
+        regs_regs_2_lpi_1_dfm <= regs_regs_2_lpi_1_dfm_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_1 <= exit_FRAME_lpi_1_dfm_1_mx0;
+        b_2_sva_1 <= b_2_sva_3;
+        b_0_sva_1 <= b_0_sva_3;
+        g_2_sva_1 <= g_2_sva_3;
+        g_0_sva_1 <= g_0_sva_3;
+        r_2_sva_1 <= r_2_sva_3;
+        r_0_sva_1 <= r_0_sva_3;
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_sva_1 , FRAME_p_1_lpi_1_dfm},
+            FRAME_for_acc_itm[1]);
+      end
+    end
+  end
+  assign nl_FRAME_acc_41_itm_1_sg2  = (FRAME_mul_sdt[9:8]) + conv_s2u_1_2(ACC1_acc_43_itm[15]);
+  assign nl_FRAME_acc_41_itm_3  = conv_u2u_5_6(FRAME_mul_sdt[4:0]) + conv_u2u_5_6(signext_5_3({(ACC1_acc_43_itm[15])
+      , 1'b0 , (ACC1_acc_43_itm[15])}));
+  assign nl_FRAME_mul_1_itm_1  = conv_u2u_3_9(ACC1_acc_43_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_37_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_sva[5:3])) , (~ (acc_imod_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC1_acc_43_itm[9:7]));
+  assign nl_FRAME_mul_4_itm_1  = conv_u2u_2_11(ACC1_acc_45_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_5_itm_1  = conv_u2u_3_9(ACC1_acc_45_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_30_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_4_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_4_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_4_sva[5:3])) , (~ (acc_imod_4_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_4_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC1_acc_45_itm[9:7]));
+  assign nl_FRAME_mul_2_itm_1  = conv_u2u_2_11(ACC1_acc_44_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_3_itm_1  = conv_u2u_3_9(ACC1_acc_44_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_18_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_2_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_2_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_2_sva[5:3])) , (~ (acc_imod_2_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_2_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC1_acc_44_itm[9:7]));
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_2_1_1;
+    input [1:0] vector;
+    reg [1:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_2_1_1 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [15:0] signext_16_11;
+    input [10:0] vector;
+  begin
+    signext_16_11= {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_11_15 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_15 = {{4{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_s2u_1_2 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_2 = {vector[0], vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v3/rtl.v.psr b/Sobel/sobel.v3/rtl.v.psr
new file mode 100644
index 0000000..ba6e782
--- /dev/null
+++ b/Sobel/sobel.v3/rtl.v.psr
@@ -0,0 +1,289 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v3/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v3/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v3/rtl.v}} -format verilog
+   setup_design -design=sobel
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'sobel': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'sobel': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'sobel'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'sobel'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to vout_rsc_z(29:0)
+   report_timing -from en -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from vin_rsc_z(89:0) -to vout_rsc_z(29:0)
+   report_timing -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock clk] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock en] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'sobel'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'sobel'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v3 mapped.v]
+          puts "-- Writing mapped netlist for 'sobel' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v3 gate.v]
+          set gate_sdf [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v3 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/Sobel/sobel.v3/rtl.v.psr_timing b/Sobel/sobel.v3/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/Sobel/sobel.v3/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/Sobel/sobel.v3/rtl.v_order.txt b/Sobel/sobel.v3/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/Sobel/sobel.v3/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/Sobel/sobel.v3/rtl_mgc_ioport.v b/Sobel/sobel.v3/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v3/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v3/rtl_mgc_ioport_v2001.v b/Sobel/sobel.v3/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v3/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v3/schedule.gnt b/Sobel/sobel.v3/schedule.gnt
new file mode 100644
index 0000000..a19d764
--- /dev/null
+++ b/Sobel/sobel.v3/schedule.gnt
@@ -0,0 +1,445 @@
+set a(0-804) {NAME i:asn(i#6.lpi#1) TYPE ASSIGN PAR 0-803 XREFS 6864 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{258 0 0-818 {}}} CYCLES {}}
+set a(0-805) {NAME b:asn(b(2).lpi#1) TYPE ASSIGN PAR 0-803 XREFS 6865 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{258 0 0-818 {}}} CYCLES {}}
+set a(0-806) {NAME g:asn(g(2).lpi#1) TYPE ASSIGN PAR 0-803 XREFS 6866 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{258 0 0-818 {}}} CYCLES {}}
+set a(0-807) {NAME r:asn(r(2).lpi#1) TYPE ASSIGN PAR 0-803 XREFS 6867 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{258 0 0-818 {}}} CYCLES {}}
+set a(0-808) {NAME b:asn(b(0).lpi#1) TYPE ASSIGN PAR 0-803 XREFS 6868 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{258 0 0-818 {}}} CYCLES {}}
+set a(0-809) {NAME g:asn(g(0).lpi#1) TYPE ASSIGN PAR 0-803 XREFS 6869 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{258 0 0-818 {}}} CYCLES {}}
+set a(0-810) {NAME r:asn(r(0).lpi#1) TYPE ASSIGN PAR 0-803 XREFS 6870 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{258 0 0-818 {}}} CYCLES {}}
+set a(0-811) {NAME regs.regs:asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-803 XREFS 6871 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{258 0 0-818 {}}} CYCLES {}}
+set a(0-812) {NAME FRAME:asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-803 XREFS 6872 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{258 0 0-818 {}}} CYCLES {}}
+set a(0-813) {NAME FRAME:for:asn(exit:FRAME:for.lpi#1)#1 TYPE ASSIGN PAR 0-803 XREFS 6873 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{258 0 0-818 {}}} CYCLES {}}
+set a(0-814) {NAME FRAME:p:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-803 XREFS 6874 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{258 0 0-818 {}}} CYCLES {}}
+set a(0-815) {NAME asn(regs.regs(1))#1 TYPE ASSIGN PAR 0-803 XREFS 6875 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{258 0 0-818 {}}} CYCLES {}}
+set a(0-816) {NAME asn(regs.regs(0))#1 TYPE ASSIGN PAR 0-803 XREFS 6876 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{258 0 0-818 {}}} CYCLES {}}
+set a(0-817) {NAME FRAME:for:asn(exit:FRAME#1) TYPE ASSIGN PAR 0-803 XREFS 6877 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-818 {}}} SUCCS {{259 0 0-818 {}}} CYCLES {}}
+set a(0-819) {NAME FRAME:asn(exit:FRAME.sva#1) TYPE ASSIGN PAR 0-818 XREFS 6878 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {} SUCCS {{258 0 0-1223 {}} {258 0 0-1224 {}}} CYCLES {}}
+set a(0-820) {NAME FRAME:p:asn(FRAME:p#1.sva#1) TYPE ASSIGN PAR 0-818 XREFS 6879 LOC {0 1.0 1 0.9041241999999999 1 0.9041241999999999 3 0.364883325} PREDS {} SUCCS {{258 0 0-1236 {}}} CYCLES {}}
+set a(0-821) {NAME b:asn(b(2).sva) TYPE ASSIGN PAR 0-818 XREFS 6880 LOC {0 1.0 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {} SUCCS {{258 0 0-980 {}}} CYCLES {}}
+set a(0-822) {NAME g:asn(g(2).sva) TYPE ASSIGN PAR 0-818 XREFS 6881 LOC {0 1.0 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {} SUCCS {{258 0 0-971 {}}} CYCLES {}}
+set a(0-823) {NAME r:asn(r(2).sva) TYPE ASSIGN PAR 0-818 XREFS 6882 LOC {0 1.0 1 0.27276455 1 0.27276455 2 0.005714625} PREDS {} SUCCS {{258 0 0-962 {}}} CYCLES {}}
+set a(0-824) {NAME b:asn(b(0).sva) TYPE ASSIGN PAR 0-818 XREFS 6883 LOC {0 1.0 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {} SUCCS {{258 0 0-935 {}}} CYCLES {}}
+set a(0-825) {NAME g:asn(g(0).sva) TYPE ASSIGN PAR 0-818 XREFS 6884 LOC {0 1.0 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {} SUCCS {{258 0 0-925 {}}} CYCLES {}}
+set a(0-826) {NAME r:asn(r(0).sva) TYPE ASSIGN PAR 0-818 XREFS 6885 LOC {0 1.0 1 0.382656675 1 0.382656675 2 0.11560675} PREDS {} SUCCS {{258 0 0-915 {}}} CYCLES {}}
+set a(0-827) {NAME regs.regs:asn(regs.regs(0).sva#1) TYPE ASSIGN PAR 0-818 XREFS 6886 LOC {0 1.0 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {} SUCCS {{258 0 0-893 {}}} CYCLES {}}
+set a(0-828) {NAME FRAME:for:asn TYPE ASSIGN PAR 0-818 XREFS 6887 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-1241 {}}} SUCCS {{259 0 0-829 {}} {256 0 0-1241 {}}} CYCLES {}}
+set a(0-829) {NAME FRAME:for:select TYPE SELECT PAR 0-818 XREFS 6888 LOC {0 1.0 0 1.0 0 1.0 3 1.0} PREDS {{259 0 0-828 {}}} SUCCS {} CYCLES {}}
+set a(0-830) {NAME FRAME:asn TYPE ASSIGN PAR 0-818 XREFS 6889 LOC {0 1.0 1 0.76845805 1 0.76845805 2 0.38794392499999997} PREDS {{262 0 0-1241 {}}} SUCCS {{259 0 0-831 {}} {256 0 0-1241 {}}} CYCLES {}}
+set a(0-831) {NAME FRAME:not#28 TYPE NOT PAR 0-818 XREFS 6890 LOC {1 0.0 1 0.76845805 1 0.76845805 2 0.38794392499999997} PREDS {{259 0 0-830 {}}} SUCCS {{259 0 0-832 {}}} CYCLES {}}
+set a(0-832) {NAME FRAME:for:exs TYPE SIGNEXTEND PAR 0-818 XREFS 6891 LOC {1 0.0 1 0.76845805 1 0.76845805 2 0.38794392499999997} PREDS {{259 0 0-831 {}}} SUCCS {{259 0 0-833 {}}} CYCLES {}}
+set a(0-833) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(19,2) AREA_SCORE 13.87 QUANTITY 1 NAME FRAME:for:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-818 XREFS 6892 LOC {1 0.0 1 0.76845805 1 0.76845805 1 0.784864781263854 2 0.40435065626385386} PREDS {{262 0 0-1236 {}} {259 0 0-832 {}}} SUCCS {{258 0 0-1216 {}} {258 0 0-1236 {}}} CYCLES {}}
+set a(0-834) {NAME FRAME:for:asn#9 TYPE ASSIGN PAR 0-818 XREFS 6893 LOC {0 1.0 1 0.0 1 0.0 1 0.619485875} PREDS {{262 0 0-1241 {}}} SUCCS {{259 0 0-835 {}} {256 0 0-1241 {}}} CYCLES {}}
+set a(0-835) {NAME FRAME:for:or TYPE OR PAR 0-818 XREFS 6894 LOC {1 0.0 1 0.0 1 0.0 1 0.619485875} PREDS {{262 0 0-1239 {}} {259 0 0-834 {}}} SUCCS {{259 0 0-836 {}} {258 0 0-893 {}} {258 0 0-896 {}} {258 0 0-898 {}} {258 0 0-899 {}} {258 0 0-917 {}} {258 0 0-927 {}} {258 0 0-937 {}} {258 0 0-964 {}} {258 0 0-973 {}} {258 0 0-982 {}} {258 0 0-1221 {}} {256 0 0-1239 {}}} CYCLES {}}
+set a(0-836) {NAME FRAME:for:select#1 TYPE SELECT PAR 0-818 XREFS 6895 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {{259 0 0-835 {}}} SUCCS {{146 0 0-837 {}} {146 0 0-838 {}} {146 0 0-839 {}} {146 0 0-840 {}} {146 0 0-841 {}} {146 0 0-842 {}} {146 0 0-843 {}} {146 0 0-844 {}} {146 0 0-845 {}} {146 0 0-846 {}} {146 0 0-847 {}} {146 0 0-848 {}} {146 0 0-849 {}} {146 0 0-850 {}} {146 0 0-851 {}} {146 0 0-852 {}} {146 0 0-853 {}} {146 0 0-854 {}} {146 0 0-855 {}} {146 0 0-856 {}} {146 0 0-857 {}} {146 0 0-858 {}} {146 0 0-859 {}} {146 0 0-860 {}} {146 0 0-861 {}} {146 0 0-862 {}} {146 0 0-863 {}} {146 0 0-864 {}} {146 0 0-865 {}} {146 0 0-866 {}} {146 0 0-867 {}} {146 0 0-868 {}} {146 0 0-869 {}} {146 0 0-870 {}} {146 0 0-871 {}} {146 0 0-872 {}} {146 0 0-873 {}} {146 0 0-874 {}} {146 0 0-875 {}} {146 0 0-876 {}} {146 0 0-877 {}} {146 0 0-878 {}} {146 0 0-879 {}} {146 0 0-880 {}} {146 0 0-881 {}} {146 0 0-882 {}} {146 0 0-883 {}} {146 0 0-884 {}} {146 0 0-885 {}} {146 0 0-886 {}} {146 0 0-887 {}} {146 0 0-888 {}} {146 0 0-889 {}} {146 0 0-890 {}} {146 0 0-891 {}}} CYCLES {}}
+set a(0-837) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,90) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_read(vin:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-818 XREFS 6896 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {{146 0 0-836 {}}} SUCCS {{259 0 0-838 {}} {258 0 0-847 {}} {258 0 0-856 {}} {258 0 0-865 {}} {258 0 0-874 {}} {258 0 0-883 {}} {258 0 0-893 {}}} CYCLES {}}
+set a(0-838) {NAME ACC1:slc(regs.regs(0))#3 TYPE READSLICE PAR 0-818 XREFS 6897 LOC {1 0.0 1 0.021312825 1 0.021312825 2 0.04023595} PREDS {{146 0 0-836 {}} {259 0 0-837 {}}} SUCCS {{259 0 0-839 {}}} CYCLES {}}
+set a(0-839) {NAME ACC1:not TYPE NOT PAR 0-818 XREFS 6898 LOC {1 0.0 1 0.307285875 1 0.307285875 2 0.04023595} PREDS {{146 0 0-836 {}} {259 0 0-838 {}}} SUCCS {{259 0 0-840 {}}} CYCLES {}}
+set a(0-840) {NAME ACC1:conc TYPE CONCATENATE PAR 0-818 XREFS 6899 LOC {1 0.0 1 0.307285875 1 0.307285875 2 0.04023595} PREDS {{146 0 0-836 {}} {259 0 0-839 {}}} SUCCS {{258 0 0-844 {}}} CYCLES {}}
+set a(0-841) {NAME ACC1:asn TYPE ASSIGN PAR 0-818 XREFS 6900 LOC {1 0.0 1 0.021312825 1 0.021312825 2 0.04023595} PREDS {{146 0 0-836 {}} {262 0 0-1228 {}}} SUCCS {{259 0 0-842 {}} {256 0 0-1228 {}}} CYCLES {}}
+set a(0-842) {NAME ACC1:slc(regs.regs(2))#3 TYPE READSLICE PAR 0-818 XREFS 6901 LOC {1 0.0 1 0.021312825 1 0.021312825 2 0.04023595} PREDS {{146 0 0-836 {}} {259 0 0-841 {}}} SUCCS {{259 0 0-843 {}}} CYCLES {}}
+set a(0-843) {NAME ACC1:conc#21 TYPE CONCATENATE PAR 0-818 XREFS 6902 LOC {1 0.0 1 0.307285875 1 0.307285875 2 0.04023595} PREDS {{146 0 0-836 {}} {259 0 0-842 {}}} SUCCS {{259 0 0-844 {}}} CYCLES {}}
+set a(0-844) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#48 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-818 XREFS 6903 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.38265663137342837 2 0.11560670637342838} PREDS {{146 0 0-836 {}} {258 0 0-840 {}} {259 0 0-843 {}}} SUCCS {{259 0 0-845 {}}} CYCLES {}}
+set a(0-845) {NAME ACC1:slc TYPE READSLICE PAR 0-818 XREFS 6904 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.11560675} PREDS {{146 0 0-836 {}} {259 0 0-844 {}}} SUCCS {{259 0 0-846 {}}} CYCLES {}}
+set a(0-846) {NAME ACC1:exs#47 TYPE SIGNEXTEND PAR 0-818 XREFS 6905 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.11560675} PREDS {{146 0 0-836 {}} {259 0 0-845 {}}} SUCCS {{258 0 0-915 {}}} CYCLES {}}
+set a(0-847) {NAME ACC1:slc(regs.regs(0))#4 TYPE READSLICE PAR 0-818 XREFS 6906 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {258 0 0-837 {}}} SUCCS {{259 0 0-848 {}}} CYCLES {}}
+set a(0-848) {NAME ACC1:not#15 TYPE NOT PAR 0-818 XREFS 6907 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {259 0 0-847 {}}} SUCCS {{259 0 0-849 {}}} CYCLES {}}
+set a(0-849) {NAME ACC1:conc#22 TYPE CONCATENATE PAR 0-818 XREFS 6908 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {259 0 0-848 {}}} SUCCS {{258 0 0-853 {}}} CYCLES {}}
+set a(0-850) {NAME ACC1:asn#11 TYPE ASSIGN PAR 0-818 XREFS 6909 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {262 0 0-1228 {}}} SUCCS {{259 0 0-851 {}} {256 0 0-1228 {}}} CYCLES {}}
+set a(0-851) {NAME ACC1:slc(regs.regs(2))#4 TYPE READSLICE PAR 0-818 XREFS 6910 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {259 0 0-850 {}}} SUCCS {{259 0 0-852 {}}} CYCLES {}}
+set a(0-852) {NAME ACC1:conc#23 TYPE CONCATENATE PAR 0-818 XREFS 6911 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {259 0 0-851 {}}} SUCCS {{259 0 0-853 {}}} CYCLES {}}
+set a(0-853) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-818 XREFS 6912 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.38265663137342837 1 0.9999999563734283} PREDS {{146 0 0-836 {}} {258 0 0-849 {}} {259 0 0-852 {}}} SUCCS {{259 0 0-854 {}}} CYCLES {}}
+set a(0-854) {NAME ACC1:slc#1 TYPE READSLICE PAR 0-818 XREFS 6913 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{146 0 0-836 {}} {259 0 0-853 {}}} SUCCS {{259 0 0-855 {}}} CYCLES {}}
+set a(0-855) {NAME ACC1:exs#48 TYPE SIGNEXTEND PAR 0-818 XREFS 6914 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{146 0 0-836 {}} {259 0 0-854 {}}} SUCCS {{258 0 0-925 {}}} CYCLES {}}
+set a(0-856) {NAME ACC1:slc(regs.regs(0))#5 TYPE READSLICE PAR 0-818 XREFS 6915 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {258 0 0-837 {}}} SUCCS {{259 0 0-857 {}}} CYCLES {}}
+set a(0-857) {NAME ACC1:not#16 TYPE NOT PAR 0-818 XREFS 6916 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {259 0 0-856 {}}} SUCCS {{259 0 0-858 {}}} CYCLES {}}
+set a(0-858) {NAME ACC1:conc#24 TYPE CONCATENATE PAR 0-818 XREFS 6917 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {259 0 0-857 {}}} SUCCS {{258 0 0-862 {}}} CYCLES {}}
+set a(0-859) {NAME ACC1:asn#12 TYPE ASSIGN PAR 0-818 XREFS 6918 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {262 0 0-1228 {}}} SUCCS {{259 0 0-860 {}} {256 0 0-1228 {}}} CYCLES {}}
+set a(0-860) {NAME ACC1:slc(regs.regs(2))#5 TYPE READSLICE PAR 0-818 XREFS 6919 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {259 0 0-859 {}}} SUCCS {{259 0 0-861 {}}} CYCLES {}}
+set a(0-861) {NAME ACC1:conc#25 TYPE CONCATENATE PAR 0-818 XREFS 6920 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {259 0 0-860 {}}} SUCCS {{259 0 0-862 {}}} CYCLES {}}
+set a(0-862) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#49 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-818 XREFS 6921 LOC {1 0.0 1 0.307285875 1 0.307285875 1 0.38265663137342837 1 0.9999999563734283} PREDS {{146 0 0-836 {}} {258 0 0-858 {}} {259 0 0-861 {}}} SUCCS {{259 0 0-863 {}}} CYCLES {}}
+set a(0-863) {NAME ACC1:slc#2 TYPE READSLICE PAR 0-818 XREFS 6922 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{146 0 0-836 {}} {259 0 0-862 {}}} SUCCS {{259 0 0-864 {}}} CYCLES {}}
+set a(0-864) {NAME ACC1:exs#49 TYPE SIGNEXTEND PAR 0-818 XREFS 6923 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{146 0 0-836 {}} {259 0 0-863 {}}} SUCCS {{258 0 0-935 {}}} CYCLES {}}
+set a(0-865) {NAME ACC1:slc(regs.regs(0)) TYPE READSLICE PAR 0-818 XREFS 6924 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {258 0 0-837 {}}} SUCCS {{259 0 0-866 {}}} CYCLES {}}
+set a(0-866) {NAME ACC1:not#12 TYPE NOT PAR 0-818 XREFS 6925 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {259 0 0-865 {}}} SUCCS {{259 0 0-867 {}}} CYCLES {}}
+set a(0-867) {NAME ACC1:conc#26 TYPE CONCATENATE PAR 0-818 XREFS 6926 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {259 0 0-866 {}}} SUCCS {{258 0 0-871 {}}} CYCLES {}}
+set a(0-868) {NAME ACC1:asn#13 TYPE ASSIGN PAR 0-818 XREFS 6927 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {262 0 0-1228 {}}} SUCCS {{259 0 0-869 {}} {256 0 0-1228 {}}} CYCLES {}}
+set a(0-869) {NAME ACC1:slc(regs.regs(2)) TYPE READSLICE PAR 0-818 XREFS 6928 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {259 0 0-868 {}}} SUCCS {{259 0 0-870 {}}} CYCLES {}}
+set a(0-870) {NAME ACC1:conc#27 TYPE CONCATENATE PAR 0-818 XREFS 6929 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.9246291999999999} PREDS {{146 0 0-836 {}} {259 0 0-869 {}}} SUCCS {{259 0 0-871 {}}} CYCLES {}}
+set a(0-871) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#50 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-818 XREFS 6930 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.27276450637342836 1 0.9999999563734283} PREDS {{146 0 0-836 {}} {258 0 0-867 {}} {259 0 0-870 {}}} SUCCS {{259 0 0-872 {}}} CYCLES {}}
+set a(0-872) {NAME ACC1:slc#3 TYPE READSLICE PAR 0-818 XREFS 6931 LOC {1 0.0753708 1 0.27276455 1 0.27276455 2 0.005714625} PREDS {{146 0 0-836 {}} {259 0 0-871 {}}} SUCCS {{259 0 0-873 {}}} CYCLES {}}
+set a(0-873) {NAME ACC1-3:exs TYPE SIGNEXTEND PAR 0-818 XREFS 6932 LOC {1 0.0753708 1 0.27276455 1 0.27276455 2 0.005714625} PREDS {{146 0 0-836 {}} {259 0 0-872 {}}} SUCCS {{258 0 0-962 {}}} CYCLES {}}
+set a(0-874) {NAME ACC1:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-818 XREFS 6933 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.7955668} PREDS {{146 0 0-836 {}} {258 0 0-837 {}}} SUCCS {{259 0 0-875 {}}} CYCLES {}}
+set a(0-875) {NAME ACC1:not#13 TYPE NOT PAR 0-818 XREFS 6934 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.7955668} PREDS {{146 0 0-836 {}} {259 0 0-874 {}}} SUCCS {{259 0 0-876 {}}} CYCLES {}}
+set a(0-876) {NAME ACC1:conc#28 TYPE CONCATENATE PAR 0-818 XREFS 6935 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.7955668} PREDS {{146 0 0-836 {}} {259 0 0-875 {}}} SUCCS {{258 0 0-880 {}}} CYCLES {}}
+set a(0-877) {NAME ACC1:asn#14 TYPE ASSIGN PAR 0-818 XREFS 6936 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.7955668} PREDS {{146 0 0-836 {}} {262 0 0-1228 {}}} SUCCS {{259 0 0-878 {}} {256 0 0-1228 {}}} CYCLES {}}
+set a(0-878) {NAME ACC1:slc(regs.regs(2))#1 TYPE READSLICE PAR 0-818 XREFS 6937 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.7955668} PREDS {{146 0 0-836 {}} {259 0 0-877 {}}} SUCCS {{259 0 0-879 {}}} CYCLES {}}
+set a(0-879) {NAME ACC1:conc#29 TYPE CONCATENATE PAR 0-818 XREFS 6938 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.7955668} PREDS {{146 0 0-836 {}} {259 0 0-878 {}}} SUCCS {{259 0 0-880 {}}} CYCLES {}}
+set a(0-880) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#51 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-818 XREFS 6939 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.27276450637342836 1 0.8709375563734284} PREDS {{146 0 0-836 {}} {258 0 0-876 {}} {259 0 0-879 {}}} SUCCS {{259 0 0-881 {}}} CYCLES {}}
+set a(0-881) {NAME ACC1:slc#4 TYPE READSLICE PAR 0-818 XREFS 6940 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{146 0 0-836 {}} {259 0 0-880 {}}} SUCCS {{259 0 0-882 {}}} CYCLES {}}
+set a(0-882) {NAME ACC1-3:exs#1 TYPE SIGNEXTEND PAR 0-818 XREFS 6941 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{146 0 0-836 {}} {259 0 0-881 {}}} SUCCS {{258 0 0-971 {}}} CYCLES {}}
+set a(0-883) {NAME ACC1:slc(regs.regs(0))#2 TYPE READSLICE PAR 0-818 XREFS 6942 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.7955668} PREDS {{146 0 0-836 {}} {258 0 0-837 {}}} SUCCS {{259 0 0-884 {}}} CYCLES {}}
+set a(0-884) {NAME ACC1:not#14 TYPE NOT PAR 0-818 XREFS 6943 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.7955668} PREDS {{146 0 0-836 {}} {259 0 0-883 {}}} SUCCS {{259 0 0-885 {}}} CYCLES {}}
+set a(0-885) {NAME ACC1:conc#30 TYPE CONCATENATE PAR 0-818 XREFS 6944 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.7955668} PREDS {{146 0 0-836 {}} {259 0 0-884 {}}} SUCCS {{258 0 0-889 {}}} CYCLES {}}
+set a(0-886) {NAME ACC1:asn#15 TYPE ASSIGN PAR 0-818 XREFS 6945 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.7955668} PREDS {{146 0 0-836 {}} {262 0 0-1228 {}}} SUCCS {{259 0 0-887 {}} {256 0 0-1228 {}}} CYCLES {}}
+set a(0-887) {NAME ACC1:slc(regs.regs(2))#2 TYPE READSLICE PAR 0-818 XREFS 6946 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.7955668} PREDS {{146 0 0-836 {}} {259 0 0-886 {}}} SUCCS {{259 0 0-888 {}}} CYCLES {}}
+set a(0-888) {NAME ACC1:conc#31 TYPE CONCATENATE PAR 0-818 XREFS 6947 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.7955668} PREDS {{146 0 0-836 {}} {259 0 0-887 {}}} SUCCS {{259 0 0-889 {}}} CYCLES {}}
+set a(0-889) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#52 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-818 XREFS 6948 LOC {1 0.0 1 0.19739374999999998 1 0.19739374999999998 1 0.27276450637342836 1 0.8709375563734284} PREDS {{146 0 0-836 {}} {258 0 0-885 {}} {259 0 0-888 {}}} SUCCS {{259 0 0-890 {}}} CYCLES {}}
+set a(0-890) {NAME ACC1:slc#5 TYPE READSLICE PAR 0-818 XREFS 6949 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{146 0 0-836 {}} {259 0 0-889 {}}} SUCCS {{259 0 0-891 {}}} CYCLES {}}
+set a(0-891) {NAME ACC1-3:exs#2 TYPE SIGNEXTEND PAR 0-818 XREFS 6950 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{146 0 0-836 {}} {259 0 0-890 {}}} SUCCS {{258 0 0-980 {}}} CYCLES {}}
+set a(0-892) {NAME FRAME:for:asn#10 TYPE ASSIGN PAR 0-818 XREFS 6951 LOC {0 1.0 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {{262 0 0-1227 {}}} SUCCS {{259 0 0-893 {}} {256 0 0-1227 {}}} CYCLES {}}
+set a(0-893) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#2 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-818 XREFS 6952 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.0443733875 1 0.6425464375} PREDS {{258 0 0-835 {}} {258 0 0-837 {}} {258 0 0-827 {}} {259 0 0-892 {}}} SUCCS {{258 0 0-920 {}} {258 0 0-930 {}} {258 0 0-940 {}} {258 0 0-967 {}} {258 0 0-976 {}} {258 0 0-985 {}} {258 0 0-997 {}} {258 0 0-1012 {}} {258 0 0-1027 {}} {258 0 0-1227 {}}} CYCLES {}}
+set a(0-894) {NAME FRAME:for:asn#11 TYPE ASSIGN PAR 0-818 XREFS 6953 LOC {0 1.0 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {{262 0 0-1227 {}}} SUCCS {{258 0 0-896 {}} {256 0 0-1227 {}}} CYCLES {}}
+set a(0-895) {NAME FRAME:for:asn#12 TYPE ASSIGN PAR 0-818 XREFS 6954 LOC {0 1.0 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {{262 0 0-1228 {}}} SUCCS {{259 0 0-896 {}} {256 0 0-1228 {}}} CYCLES {}}
+set a(0-896) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#3 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-818 XREFS 6955 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.0443733875 1 0.6425464375} PREDS {{258 0 0-835 {}} {258 0 0-894 {}} {259 0 0-895 {}}} SUCCS {{258 0 0-919 {}} {258 0 0-929 {}} {258 0 0-939 {}} {258 0 0-966 {}} {258 0 0-975 {}} {258 0 0-984 {}} {258 0 0-1228 {}}} CYCLES {}}
+set a(0-897) {NAME FRAME:for:asn#13 TYPE ASSIGN PAR 0-818 XREFS 6956 LOC {0 1.0 1 0.021312825 1 0.021312825 1 0.619485875} PREDS {{262 0 0-1228 {}}} SUCCS {{259 0 0-898 {}} {256 0 0-1228 {}}} CYCLES {}}
+set a(0-898) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#4 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-818 XREFS 6957 LOC {1 0.0 1 0.021312825 1 0.021312825 1 0.0443733875 1 0.6425464375} PREDS {{258 0 0-835 {}} {262 0 0-1229 {}} {259 0 0-897 {}}} SUCCS {{258 0 0-918 {}} {258 0 0-928 {}} {258 0 0-938 {}} {258 0 0-965 {}} {258 0 0-974 {}} {258 0 0-983 {}} {258 0 0-1001 {}} {258 0 0-1016 {}} {258 0 0-1031 {}} {258 0 0-1229 {}}} CYCLES {}}
+set a(0-899) {NAME not#15 TYPE NOT PAR 0-818 XREFS 6958 LOC {1 0.0 1 0.02796665 1 0.02796665 1 0.6261397} PREDS {{258 0 0-835 {}}} SUCCS {{259 0 0-900 {}}} CYCLES {}}
+set a(0-900) {NAME FRAME:for:exs#19 TYPE SIGNEXTEND PAR 0-818 XREFS 6959 LOC {1 0.0 1 0.02796665 1 0.02796665 1 0.6261397} PREDS {{259 0 0-899 {}}} SUCCS {{259 0 0-901 {}}} CYCLES {}}
+set a(0-901) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 2 NAME FRAME:for:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-818 XREFS 6960 LOC {1 0.0 1 0.02796665 1 0.02796665 1 0.04437338126385391 1 0.6425464312638539} PREDS {{262 0 0-1237 {}} {259 0 0-900 {}}} SUCCS {{259 0 0-902 {}} {258 0 0-903 {}} {258 0 0-904 {}} {258 0 0-905 {}} {258 0 0-906 {}} {258 0 0-909 {}} {258 0 0-911 {}} {258 0 0-921 {}} {258 0 0-931 {}} {258 0 0-941 {}} {258 0 0-945 {}} {258 0 0-947 {}} {258 0 0-968 {}} {258 0 0-977 {}} {258 0 0-986 {}} {258 0 0-989 {}} {256 0 0-1237 {}}} CYCLES {}}
+set a(0-902) {NAME slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-818 XREFS 6961 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{259 0 0-901 {}}} SUCCS {{258 0 0-910 {}}} CYCLES {}}
+set a(0-903) {NAME slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-818 XREFS 6962 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-901 {}}} SUCCS {{258 0 0-907 {}}} CYCLES {}}
+set a(0-904) {NAME slc(i#6.lpi#1.dfm)#2 TYPE READSLICE PAR 0-818 XREFS 6963 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-901 {}}} SUCCS {{258 0 0-913 {}}} CYCLES {}}
+set a(0-905) {NAME slc(i#6.lpi#1.dfm)#3 TYPE READSLICE PAR 0-818 XREFS 6964 LOC {1 0.016406775 1 0.044373425 1 0.044373425 3 1.0} PREDS {{258 0 0-901 {}}} SUCCS {} CYCLES {}}
+set a(0-906) {NAME FRAME:for:slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-818 XREFS 6965 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-901 {}}} SUCCS {{258 0 0-908 {}}} CYCLES {}}
+set a(0-907) {NAME FRAME:for:not#1 TYPE NOT PAR 0-818 XREFS 6966 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-903 {}}} SUCCS {{259 0 0-908 {}}} CYCLES {}}
+set a(0-908) {NAME FRAME:for:nand TYPE NAND PAR 0-818 XREFS 6967 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-906 {}} {259 0 0-907 {}}} SUCCS {{258 0 0-914 {}}} CYCLES {}}
+set a(0-909) {NAME FRAME:for:slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-818 XREFS 6968 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-901 {}}} SUCCS {{259 0 0-910 {}}} CYCLES {}}
+set a(0-910) {NAME FRAME:for:nor TYPE NOR PAR 0-818 XREFS 6969 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-902 {}} {259 0 0-909 {}}} SUCCS {{258 0 0-914 {}}} CYCLES {}}
+set a(0-911) {NAME FRAME:for:slc(i#6.lpi#1.dfm)#2 TYPE READSLICE PAR 0-818 XREFS 6970 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-901 {}}} SUCCS {{259 0 0-912 {}}} CYCLES {}}
+set a(0-912) {NAME FRAME:for:not#2 TYPE NOT PAR 0-818 XREFS 6971 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{259 0 0-911 {}}} SUCCS {{259 0 0-913 {}}} CYCLES {}}
+set a(0-913) {NAME FRAME:for:and#3 TYPE AND PAR 0-818 XREFS 6972 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-904 {}} {259 0 0-912 {}}} SUCCS {{259 0 0-914 {}}} CYCLES {}}
+set a(0-914) {NAME FRAME:for:or#3 TYPE OR PAR 0-818 XREFS 6973 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.807076075} PREDS {{258 0 0-910 {}} {258 0 0-908 {}} {259 0 0-913 {}}} SUCCS {{258 0 0-922 {}} {258 0 0-932 {}} {258 0 0-942 {}}} CYCLES {}}
+set a(0-915) {NAME FRAME:for:slc(r(0).sva) TYPE READSLICE PAR 0-818 XREFS 6974 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.11560675} PREDS {{258 0 0-846 {}} {258 0 0-826 {}}} SUCCS {{259 0 0-916 {}}} CYCLES {}}
+set a(0-916) {NAME FRAME:for:exs#20 TYPE SIGNEXTEND PAR 0-818 XREFS 6975 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.11560675} PREDS {{259 0 0-915 {}}} SUCCS {{259 0 0-917 {}}} CYCLES {}}
+set a(0-917) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#5 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-818 XREFS 6976 LOC {1 0.0753708 1 0.382656675 1 0.382656675 1 0.4057172375 2 0.1386673125} PREDS {{258 0 0-835 {}} {262 0 0-1230 {}} {259 0 0-916 {}}} SUCCS {{258 0 0-924 {}} {256 0 0-1230 {}}} CYCLES {}}
+set a(0-918) {NAME {regs.operator[]#9:slc(regs.regs(2))} TYPE READSLICE PAR 0-818 XREFS 6977 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-898 {}}} SUCCS {{258 0 0-921 {}}} CYCLES {}}
+set a(0-919) {NAME {regs.operator[]#9:slc(regs.regs(1))} TYPE READSLICE PAR 0-818 XREFS 6978 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-896 {}}} SUCCS {{258 0 0-921 {}}} CYCLES {}}
+set a(0-920) {NAME {regs.operator[]#9:slc(regs.regs(0))} TYPE READSLICE PAR 0-818 XREFS 6979 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-893 {}}} SUCCS {{259 0 0-921 {}}} CYCLES {}}
+set a(0-921) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#9:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 6980 LOC {1 0.0230606 1 0.15426555 1 0.15426555 1 0.2127933 1 0.807076025} PREDS {{258 0 0-901 {}} {258 0 0-919 {}} {258 0 0-918 {}} {259 0 0-920 {}}} SUCCS {{258 0 0-923 {}}} CYCLES {}}
+set a(0-922) {NAME FRAME:for:conc#5 TYPE CONCATENATE PAR 0-818 XREFS 6981 LOC {1 0.016406775 1 0.21279335 1 0.21279335 1 0.807076075} PREDS {{258 0 0-914 {}}} SUCCS {{259 0 0-923 {}}} CYCLES {}}
+set a(0-923) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-818 XREFS 6982 LOC {1 0.08158839999999999 1 0.21279335 1 0.21279335 1 0.4057172125 1 0.9999999374999999} PREDS {{258 0 0-921 {}} {259 0 0-922 {}}} SUCCS {{259 0 0-924 {}}} CYCLES {}}
+set a(0-924) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#1 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-818 XREFS 6983 LOC {1 0.274512325 1 0.405717275 1 0.405717275 1 0.5117190163378799 2 0.24466909133787984} PREDS {{258 0 0-917 {}} {259 0 0-923 {}}} SUCCS {{258 0 0-1009 {}} {258 0 0-1230 {}}} CYCLES {}}
+set a(0-925) {NAME FRAME:for:slc(g(0).sva) TYPE READSLICE PAR 0-818 XREFS 6984 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{258 0 0-855 {}} {258 0 0-825 {}}} SUCCS {{259 0 0-926 {}}} CYCLES {}}
+set a(0-926) {NAME FRAME:for:exs#21 TYPE SIGNEXTEND PAR 0-818 XREFS 6985 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{259 0 0-925 {}}} SUCCS {{259 0 0-927 {}}} CYCLES {}}
+set a(0-927) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#7 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-818 XREFS 6986 LOC {1 0.0753708 1 0.382656675 1 0.382656675 1 0.4057172375 2 0.0650410125} PREDS {{258 0 0-835 {}} {262 0 0-1232 {}} {259 0 0-926 {}}} SUCCS {{258 0 0-934 {}} {256 0 0-1232 {}}} CYCLES {}}
+set a(0-928) {NAME {regs.operator[]#10:slc(regs.regs(2))} TYPE READSLICE PAR 0-818 XREFS 6987 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-898 {}}} SUCCS {{258 0 0-931 {}}} CYCLES {}}
+set a(0-929) {NAME {regs.operator[]#10:slc(regs.regs(1))} TYPE READSLICE PAR 0-818 XREFS 6988 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-896 {}}} SUCCS {{258 0 0-931 {}}} CYCLES {}}
+set a(0-930) {NAME {regs.operator[]#10:slc(regs.regs(0))} TYPE READSLICE PAR 0-818 XREFS 6989 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-893 {}}} SUCCS {{259 0 0-931 {}}} CYCLES {}}
+set a(0-931) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#10:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 6990 LOC {1 0.0230606 1 0.15426555 1 0.15426555 1 0.2127933 1 0.807076025} PREDS {{258 0 0-901 {}} {258 0 0-929 {}} {258 0 0-928 {}} {259 0 0-930 {}}} SUCCS {{258 0 0-933 {}}} CYCLES {}}
+set a(0-932) {NAME FRAME:for:conc#6 TYPE CONCATENATE PAR 0-818 XREFS 6991 LOC {1 0.016406775 1 0.21279335 1 0.21279335 1 0.807076075} PREDS {{258 0 0-914 {}}} SUCCS {{259 0 0-933 {}}} CYCLES {}}
+set a(0-933) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#1 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-818 XREFS 6992 LOC {1 0.08158839999999999 1 0.21279335 1 0.21279335 1 0.4057172125 1 0.9999999374999999} PREDS {{258 0 0-931 {}} {259 0 0-932 {}}} SUCCS {{259 0 0-934 {}}} CYCLES {}}
+set a(0-934) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#2 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-818 XREFS 6993 LOC {1 0.274512325 1 0.405717275 1 0.405717275 1 0.5117190163378799 2 0.17104279133787986} PREDS {{258 0 0-927 {}} {259 0 0-933 {}}} SUCCS {{258 0 0-1024 {}} {258 0 0-1232 {}}} CYCLES {}}
+set a(0-935) {NAME FRAME:for:slc(b(0).sva) TYPE READSLICE PAR 0-818 XREFS 6994 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{258 0 0-864 {}} {258 0 0-824 {}}} SUCCS {{259 0 0-936 {}}} CYCLES {}}
+set a(0-936) {NAME FRAME:for:exs#22 TYPE SIGNEXTEND PAR 0-818 XREFS 6995 LOC {1 0.0753708 1 0.382656675 1 0.382656675 2 0.041980449999999996} PREDS {{259 0 0-935 {}}} SUCCS {{259 0 0-937 {}}} CYCLES {}}
+set a(0-937) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#9 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-818 XREFS 6996 LOC {1 0.0753708 1 0.382656675 1 0.382656675 1 0.4057172375 2 0.0650410125} PREDS {{258 0 0-835 {}} {262 0 0-1234 {}} {259 0 0-936 {}}} SUCCS {{258 0 0-944 {}} {256 0 0-1234 {}}} CYCLES {}}
+set a(0-938) {NAME {regs.operator[]#11:slc(regs.regs(2))} TYPE READSLICE PAR 0-818 XREFS 6997 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-898 {}}} SUCCS {{258 0 0-941 {}}} CYCLES {}}
+set a(0-939) {NAME {regs.operator[]#11:slc(regs.regs(1))} TYPE READSLICE PAR 0-818 XREFS 6998 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-896 {}}} SUCCS {{258 0 0-941 {}}} CYCLES {}}
+set a(0-940) {NAME {regs.operator[]#11:slc(regs.regs(0))} TYPE READSLICE PAR 0-818 XREFS 6999 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-893 {}}} SUCCS {{259 0 0-941 {}}} CYCLES {}}
+set a(0-941) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#11:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 7000 LOC {1 0.0230606 1 0.15426555 1 0.15426555 1 0.2127933 1 0.807076025} PREDS {{258 0 0-901 {}} {258 0 0-939 {}} {258 0 0-938 {}} {259 0 0-940 {}}} SUCCS {{258 0 0-943 {}}} CYCLES {}}
+set a(0-942) {NAME FRAME:for:conc#7 TYPE CONCATENATE PAR 0-818 XREFS 7001 LOC {1 0.016406775 1 0.21279335 1 0.21279335 1 0.807076075} PREDS {{258 0 0-914 {}}} SUCCS {{259 0 0-943 {}}} CYCLES {}}
+set a(0-943) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#2 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-818 XREFS 7002 LOC {1 0.08158839999999999 1 0.21279335 1 0.21279335 1 0.4057172125 1 0.9999999374999999} PREDS {{258 0 0-941 {}} {259 0 0-942 {}}} SUCCS {{259 0 0-944 {}}} CYCLES {}}
+set a(0-944) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#3 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-818 XREFS 7003 LOC {1 0.274512325 1 0.405717275 1 0.405717275 1 0.5117190163378799 2 0.17104279133787986} PREDS {{258 0 0-937 {}} {259 0 0-943 {}}} SUCCS {{258 0 0-1039 {}} {258 0 0-1234 {}}} CYCLES {}}
+set a(0-945) {NAME i:slc(i#3)#1 TYPE READSLICE PAR 0-818 XREFS 7004 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{258 0 0-901 {}}} SUCCS {{259 0 0-946 {}}} CYCLES {}}
+set a(0-946) {NAME FRAME:for:not#4 TYPE NOT PAR 0-818 XREFS 7005 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{259 0 0-945 {}}} SUCCS {{258 0 0-948 {}}} CYCLES {}}
+set a(0-947) {NAME i:slc(i#3)#2 TYPE READSLICE PAR 0-818 XREFS 7006 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{258 0 0-901 {}}} SUCCS {{259 0 0-948 {}}} CYCLES {}}
+set a(0-948) {NAME FRAME:for:conc TYPE CONCATENATE PAR 0-818 XREFS 7007 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{258 0 0-946 {}} {259 0 0-947 {}}} SUCCS {{259 0 0-949 {}} {258 0 0-950 {}} {258 0 0-951 {}} {258 0 0-952 {}} {258 0 0-953 {}} {258 0 0-957 {}}} CYCLES {}}
+set a(0-949) {NAME slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-818 XREFS 7008 LOC {1 0.016406775 1 0.044373425 1 0.044373425 3 1.0} PREDS {{259 0 0-948 {}}} SUCCS {} CYCLES {}}
+set a(0-950) {NAME slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-818 XREFS 7009 LOC {1 0.016406775 1 0.044373425 1 0.044373425 3 1.0} PREDS {{258 0 0-948 {}}} SUCCS {} CYCLES {}}
+set a(0-951) {NAME slc(FRAME:for:conc.tmp)#2 TYPE READSLICE PAR 0-818 XREFS 7010 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.6843317999999999} PREDS {{258 0 0-948 {}}} SUCCS {{258 0 0-959 {}}} CYCLES {}}
+set a(0-952) {NAME slc(FRAME:for:conc.tmp)#3 TYPE READSLICE PAR 0-818 XREFS 7011 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{258 0 0-948 {}}} SUCCS {{258 0 0-954 {}}} CYCLES {}}
+set a(0-953) {NAME FRAME:for:slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-818 XREFS 7012 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{258 0 0-948 {}}} SUCCS {{259 0 0-954 {}}} CYCLES {}}
+set a(0-954) {NAME FRAME:for:nand#1 TYPE NAND PAR 0-818 XREFS 7013 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.667925025} PREDS {{258 0 0-952 {}} {259 0 0-953 {}}} SUCCS {{259 0 0-955 {}}} CYCLES {}}
+set a(0-955) {NAME FRAME:for:exs#26 TYPE SIGNEXTEND PAR 0-818 XREFS 7014 LOC {1 0.016406775 1 0.069751975 1 0.069751975 1 0.667925025} PREDS {{259 0 0-954 {}}} SUCCS {{259 0 0-956 {}}} CYCLES {}}
+set a(0-956) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 2 NAME FRAME:for:and#4 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-818 XREFS 7015 LOC {1 0.016406775 1 0.069751975 1 0.069751975 1 0.0861587062638539 1 0.6843317562638539} PREDS {{259 0 0-955 {}}} SUCCS {{258 0 0-961 {}}} CYCLES {}}
+set a(0-957) {NAME FRAME:for:slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-818 XREFS 7016 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.6843317999999999} PREDS {{258 0 0-948 {}}} SUCCS {{259 0 0-958 {}}} CYCLES {}}
+set a(0-958) {NAME FRAME:for:not#3 TYPE NOT PAR 0-818 XREFS 7017 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.6843317999999999} PREDS {{259 0 0-957 {}}} SUCCS {{259 0 0-959 {}}} CYCLES {}}
+set a(0-959) {NAME FRAME:for:and#5 TYPE AND PAR 0-818 XREFS 7018 LOC {1 0.016406775 1 0.044373425 1 0.044373425 1 0.6843317999999999} PREDS {{258 0 0-951 {}} {259 0 0-958 {}}} SUCCS {{259 0 0-960 {}}} CYCLES {}}
+set a(0-960) {NAME FRAME:for:exs#27 TYPE SIGNEXTEND PAR 0-818 XREFS 7019 LOC {1 0.016406775 1 0.08615874999999999 1 0.08615874999999999 1 0.6843317999999999} PREDS {{259 0 0-959 {}}} SUCCS {{259 0 0-961 {}}} CYCLES {}}
+set a(0-961) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(2,2) AREA_SCORE 1.46 QUANTITY 1 NAME FRAME:for:or#4 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-818 XREFS 7020 LOC {1 0.03281355 1 0.08615874999999999 1 0.08615874999999999 1 0.10290118110773884 1 0.7010742311077388} PREDS {{258 0 0-956 {}} {259 0 0-960 {}}} SUCCS {{258 0 0-969 {}} {258 0 0-978 {}} {258 0 0-987 {}}} CYCLES {}}
+set a(0-962) {NAME FRAME:for:slc(r(2).sva) TYPE READSLICE PAR 0-818 XREFS 7021 LOC {1 0.0753708 1 0.27276455 1 0.27276455 2 0.005714625} PREDS {{258 0 0-873 {}} {258 0 0-823 {}}} SUCCS {{259 0 0-963 {}}} CYCLES {}}
+set a(0-963) {NAME FRAME:for:exs#23 TYPE SIGNEXTEND PAR 0-818 XREFS 7022 LOC {1 0.0753708 1 0.27276455 1 0.27276455 2 0.005714625} PREDS {{259 0 0-962 {}}} SUCCS {{259 0 0-964 {}}} CYCLES {}}
+set a(0-964) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#6 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-818 XREFS 7023 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.2958251125 2 0.0287751875} PREDS {{258 0 0-835 {}} {262 0 0-1231 {}} {259 0 0-963 {}}} SUCCS {{258 0 0-970 {}} {256 0 0-1231 {}}} CYCLES {}}
+set a(0-965) {NAME {regs.operator[]#15:slc(regs.regs(2))} TYPE READSLICE PAR 0-818 XREFS 7024 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-898 {}}} SUCCS {{258 0 0-968 {}}} CYCLES {}}
+set a(0-966) {NAME {regs.operator[]#15:slc(regs.regs(1))} TYPE READSLICE PAR 0-818 XREFS 7025 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-896 {}}} SUCCS {{258 0 0-968 {}}} CYCLES {}}
+set a(0-967) {NAME {regs.operator[]#15:slc(regs.regs(0))} TYPE READSLICE PAR 0-818 XREFS 7026 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.748548275} PREDS {{258 0 0-893 {}}} SUCCS {{259 0 0-968 {}}} CYCLES {}}
+set a(0-968) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#15:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 7027 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.102901175 1 0.807076025} PREDS {{258 0 0-901 {}} {258 0 0-966 {}} {258 0 0-965 {}} {259 0 0-967 {}}} SUCCS {{259 0 0-969 {}}} CYCLES {}}
+set a(0-969) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#6 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-818 XREFS 7028 LOC {1 0.08158839999999999 1 0.102901225 1 0.102901225 1 0.2958250875 1 0.9999999374999999} PREDS {{258 0 0-961 {}} {259 0 0-968 {}}} SUCCS {{259 0 0-970 {}}} CYCLES {}}
+set a(0-970) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#10 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-818 XREFS 7029 LOC {1 0.274512325 1 0.29582515 1 0.29582515 1 0.40182689133787985 2 0.13477696633787986} PREDS {{258 0 0-964 {}} {259 0 0-969 {}}} SUCCS {{258 0 0-996 {}} {258 0 0-1231 {}}} CYCLES {}}
+set a(0-971) {NAME FRAME:for:slc(g(2).sva) TYPE READSLICE PAR 0-818 XREFS 7030 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{258 0 0-882 {}} {258 0 0-822 {}}} SUCCS {{259 0 0-972 {}}} CYCLES {}}
+set a(0-972) {NAME FRAME:for:exs#24 TYPE SIGNEXTEND PAR 0-818 XREFS 7031 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{259 0 0-971 {}}} SUCCS {{259 0 0-973 {}}} CYCLES {}}
+set a(0-973) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#8 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-818 XREFS 7032 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.2958251125 1 0.8939981625} PREDS {{258 0 0-835 {}} {262 0 0-1233 {}} {259 0 0-972 {}}} SUCCS {{258 0 0-979 {}} {256 0 0-1233 {}}} CYCLES {}}
+set a(0-974) {NAME {regs.operator[]#16:slc(regs.regs(2))} TYPE READSLICE PAR 0-818 XREFS 7033 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.642546475} PREDS {{258 0 0-898 {}}} SUCCS {{258 0 0-977 {}}} CYCLES {}}
+set a(0-975) {NAME {regs.operator[]#16:slc(regs.regs(1))} TYPE READSLICE PAR 0-818 XREFS 7034 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.642546475} PREDS {{258 0 0-896 {}}} SUCCS {{258 0 0-977 {}}} CYCLES {}}
+set a(0-976) {NAME {regs.operator[]#16:slc(regs.regs(0))} TYPE READSLICE PAR 0-818 XREFS 7035 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.642546475} PREDS {{258 0 0-893 {}}} SUCCS {{259 0 0-977 {}}} CYCLES {}}
+set a(0-977) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#16:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 7036 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.102901175 1 0.7010742249999999} PREDS {{258 0 0-901 {}} {258 0 0-975 {}} {258 0 0-974 {}} {259 0 0-976 {}}} SUCCS {{259 0 0-978 {}}} CYCLES {}}
+set a(0-978) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#7 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-818 XREFS 7037 LOC {1 0.08158839999999999 1 0.102901225 1 0.102901225 1 0.2958250875 1 0.8939981374999999} PREDS {{258 0 0-961 {}} {259 0 0-977 {}}} SUCCS {{259 0 0-979 {}}} CYCLES {}}
+set a(0-979) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#12 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-818 XREFS 7038 LOC {1 0.274512325 1 0.29582515 1 0.29582515 1 0.40182689133787985 1 0.9999999413378798} PREDS {{258 0 0-973 {}} {259 0 0-978 {}}} SUCCS {{258 0 0-1011 {}} {258 0 0-1233 {}}} CYCLES {}}
+set a(0-980) {NAME FRAME:for:slc(b(2).sva) TYPE READSLICE PAR 0-818 XREFS 7039 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{258 0 0-891 {}} {258 0 0-821 {}}} SUCCS {{259 0 0-981 {}}} CYCLES {}}
+set a(0-981) {NAME FRAME:for:exs#25 TYPE SIGNEXTEND PAR 0-818 XREFS 7040 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.8709376} PREDS {{259 0 0-980 {}}} SUCCS {{259 0 0-982 {}}} CYCLES {}}
+set a(0-982) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#10 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-818 XREFS 7041 LOC {1 0.0753708 1 0.27276455 1 0.27276455 1 0.2958251125 1 0.8939981625} PREDS {{258 0 0-835 {}} {262 0 0-1235 {}} {259 0 0-981 {}}} SUCCS {{258 0 0-988 {}} {256 0 0-1235 {}}} CYCLES {}}
+set a(0-983) {NAME {regs.operator[]#17:slc(regs.regs(2))} TYPE READSLICE PAR 0-818 XREFS 7042 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.642546475} PREDS {{258 0 0-898 {}}} SUCCS {{258 0 0-986 {}}} CYCLES {}}
+set a(0-984) {NAME {regs.operator[]#17:slc(regs.regs(1))} TYPE READSLICE PAR 0-818 XREFS 7043 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.642546475} PREDS {{258 0 0-896 {}}} SUCCS {{258 0 0-986 {}}} CYCLES {}}
+set a(0-985) {NAME {regs.operator[]#17:slc(regs.regs(0))} TYPE READSLICE PAR 0-818 XREFS 7044 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.642546475} PREDS {{258 0 0-893 {}}} SUCCS {{259 0 0-986 {}}} CYCLES {}}
+set a(0-986) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#17:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 7045 LOC {1 0.0230606 1 0.044373425 1 0.044373425 1 0.102901175 1 0.7010742249999999} PREDS {{258 0 0-901 {}} {258 0 0-984 {}} {258 0 0-983 {}} {259 0 0-985 {}}} SUCCS {{259 0 0-987 {}}} CYCLES {}}
+set a(0-987) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#8 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-818 XREFS 7046 LOC {1 0.08158839999999999 1 0.102901225 1 0.102901225 1 0.2958250875 1 0.8939981374999999} PREDS {{258 0 0-961 {}} {259 0 0-986 {}}} SUCCS {{259 0 0-988 {}}} CYCLES {}}
+set a(0-988) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#14 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-818 XREFS 7047 LOC {1 0.274512325 1 0.29582515 1 0.29582515 1 0.40182689133787985 1 0.9999999413378798} PREDS {{258 0 0-982 {}} {259 0 0-987 {}}} SUCCS {{258 0 0-1026 {}} {258 0 0-1235 {}}} CYCLES {}}
+set a(0-989) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,2) AREA_SCORE 3.31 QUANTITY 1 NAME FRAME:for:acc#16 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-818 XREFS 7048 LOC {1 0.016406775 1 0.23399947499999998 1 0.23399947499999998 1 0.2747824850894752 1 0.8729555350894752} PREDS {{258 0 0-901 {}}} SUCCS {{259 0 0-990 {}} {258 0 0-1237 {}}} CYCLES {}}
+set a(0-990) {NAME FRAME:for:asn#2 TYPE ASSIGN PAR 0-818 XREFS 7049 LOC {1 0.057189825 1 0.274782525 1 0.274782525 1 0.872955575} PREDS {{259 0 0-989 {}}} SUCCS {{259 0 0-991 {}}} CYCLES {}}
+set a(0-991) {NAME FRAME:for:conc#11 TYPE CONCATENATE PAR 0-818 XREFS 7050 LOC {1 0.057189825 1 0.274782525 1 0.274782525 1 0.872955575} PREDS {{259 0 0-990 {}}} SUCCS {{259 0 0-992 {}}} CYCLES {}}
+set a(0-992) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,3) AREA_SCORE 4.30 QUANTITY 1 NAME FRAME:for:acc TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-818 XREFS 7051 LOC {1 0.057189825 1 0.274782525 1 0.274782525 1 0.3223386520708272 1 0.9205117020708271} PREDS {{259 0 0-991 {}}} SUCCS {{259 0 0-993 {}}} CYCLES {}}
+set a(0-993) {NAME FRAME:for:slc TYPE READSLICE PAR 0-818 XREFS 7052 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{259 0 0-992 {}}} SUCCS {{259 0 0-994 {}}} CYCLES {}}
+set a(0-994) {NAME FRAME:for:not TYPE NOT PAR 0-818 XREFS 7053 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{259 0 0-993 {}}} SUCCS {{259 0 0-995 {}} {258 0 0-1223 {}} {258 0 0-1225 {}} {258 0 0-1226 {}} {258 0 0-1236 {}}} CYCLES {}}
+set a(0-995) {NAME FRAME:for:select#2 TYPE SELECT PAR 0-818 XREFS 7054 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{259 0 0-994 {}}} SUCCS {{146 0 0-996 {}} {146 0 0-997 {}} {146 0 0-998 {}} {146 0 0-999 {}} {146 0 0-1000 {}} {146 0 0-1001 {}} {146 0 0-1002 {}} {146 0 0-1003 {}} {146 0 0-1004 {}} {146 0 0-1005 {}} {146 0 0-1006 {}} {146 0 0-1007 {}} {146 0 0-1008 {}} {146 0 0-1009 {}} {146 0 0-1010 {}} {146 0 0-1011 {}} {146 0 0-1012 {}} {146 0 0-1013 {}} {146 0 0-1014 {}} {146 0 0-1015 {}} {146 0 0-1016 {}} {146 0 0-1017 {}} {146 0 0-1018 {}} {146 0 0-1019 {}} {146 0 0-1020 {}} {146 0 0-1021 {}} {146 0 0-1022 {}} {146 0 0-1023 {}} {146 0 0-1024 {}} {146 0 0-1025 {}} {146 0 0-1026 {}} {146 0 0-1027 {}} {146 0 0-1028 {}} {146 0 0-1029 {}} {146 0 0-1030 {}} {146 0 0-1031 {}} {146 0 0-1032 {}} {146 0 0-1033 {}} {146 0 0-1034 {}} {146 0 0-1035 {}} {146 0 0-1036 {}} {146 0 0-1037 {}} {146 0 0-1038 {}} {146 0 0-1039 {}} {146 0 0-1040 {}} {146 0 0-1041 {}} {146 0 0-1042 {}} {146 0 0-1043 {}} {146 0 0-1044 {}} {146 0 0-1045 {}} {146 0 0-1046 {}} {146 0 0-1047 {}} {146 0 0-1048 {}} {146 0 0-1049 {}} {146 0 0-1050 {}} {146 0 0-1051 {}} {146 0 0-1052 {}} {146 0 0-1053 {}} {146 0 0-1054 {}} {146 0 0-1055 {}} {146 0 0-1056 {}} {146 0 0-1057 {}} {146 0 0-1058 {}} {146 0 0-1059 {}} {146 0 0-1060 {}} {146 0 0-1061 {}} {146 0 0-1062 {}} {146 0 0-1063 {}} {146 0 0-1064 {}} {146 0 0-1065 {}} {146 0 0-1066 {}} {146 0 0-1067 {}} {146 0 0-1068 {}} {146 0 0-1069 {}} {146 0 0-1070 {}} {146 0 0-1071 {}} {146 0 0-1072 {}} {146 0 0-1073 {}} {146 0 0-1074 {}} {146 0 0-1075 {}} {146 0 0-1076 {}} {146 0 0-1077 {}} {146 0 0-1078 {}} {146 0 0-1079 {}} {146 0 0-1080 {}} {146 0 0-1081 {}} {146 0 0-1082 {}} {146 0 0-1083 {}} {146 0 0-1084 {}} {146 0 0-1085 {}} {146 0 0-1086 {}} {146 0 0-1087 {}} {146 0 0-1088 {}} {146 0 0-1089 {}} {146 0 0-1090 {}} {146 0 0-1091 {}} {146 0 0-1092 {}} {146 0 0-1093 {}} {146 0 0-1094 {}} {146 0 0-1095 {}} {146 0 0-1096 {}} {146 0 0-1097 {}} {146 0 0-1098 {}} {146 0 0-1099 {}} {146 0 0-1100 {}} {146 0 0-1101 {}} {146 0 0-1102 {}} {146 0 0-1103 {}} {146 0 0-1104 {}} {146 0 0-1105 {}} {146 0 0-1106 {}} {146 0 0-1107 {}} {146 0 0-1108 {}} {146 0 0-1109 {}} {146 0 0-1110 {}} {146 0 0-1111 {}} {146 0 0-1112 {}} {146 0 0-1113 {}} {146 0 0-1114 {}} {146 0 0-1115 {}} {146 0 0-1116 {}} {146 0 0-1117 {}} {146 0 0-1118 {}} {146 0 0-1119 {}} {146 0 0-1120 {}} {146 0 0-1121 {}} {146 0 0-1122 {}} {146 0 0-1123 {}} {146 0 0-1124 {}} {146 0 0-1125 {}} {146 0 0-1126 {}} {146 0 0-1127 {}} {146 0 0-1128 {}} {146 0 0-1129 {}} {146 0 0-1130 {}} {146 0 0-1131 {}} {146 0 0-1132 {}} {146 0 0-1133 {}} {146 0 0-1134 {}} {146 0 0-1135 {}} {146 0 0-1136 {}} {146 0 0-1137 {}} {146 0 0-1138 {}} {146 0 0-1139 {}} {146 0 0-1140 {}} {146 0 0-1141 {}} {146 0 0-1142 {}} {146 0 0-1143 {}} {146 0 0-1144 {}} {146 0 0-1145 {}} {146 0 0-1146 {}} {146 0 0-1147 {}} {146 0 0-1148 {}} {146 0 0-1149 {}} {146 0 0-1150 {}} {146 0 0-1151 {}} {146 0 0-1152 {}} {146 0 0-1153 {}} {146 0 0-1154 {}} {146 0 0-1155 {}} {146 0 0-1156 {}} {146 0 0-1157 {}} {146 0 0-1158 {}} {146 0 0-1159 {}} {146 0 0-1160 {}} {146 0 0-1161 {}} {146 0 0-1162 {}} {146 0 0-1163 {}} {146 0 0-1164 {}} {146 0 0-1165 {}} {146 0 0-1166 {}} {146 0 0-1167 {}} {146 0 0-1168 {}} {146 0 0-1169 {}} {146 0 0-1170 {}} {146 0 0-1171 {}} {146 0 0-1172 {}} {146 0 0-1173 {}} {146 0 0-1174 {}} {146 0 0-1175 {}} {146 0 0-1176 {}} {146 0 0-1177 {}} {146 0 0-1178 {}} {146 0 0-1179 {}} {146 0 0-1180 {}} {146 0 0-1181 {}} {146 0 0-1182 {}} {146 0 0-1183 {}} {146 0 0-1184 {}} {146 0 0-1185 {}} {146 0 0-1186 {}} {146 0 0-1187 {}} {146 0 0-1188 {}} {146 0 0-1189 {}} {146 0 0-1190 {}} {146 0 0-1191 {}} {146 0 0-1192 {}} {146 0 0-1193 {}} {146 0 0-1194 {}} {146 0 0-1195 {}} {146 0 0-1196 {}} {146 0 0-1197 {}} {146 0 0-1198 {}} {146 0 0-1199 {}} {146 0 0-1200 {}} {146 0 0-1201 {}} {146 0 0-1202 {}} {146 0 0-1203 {}} {146 0 0-1204 {}} {146 0 0-1205 {}} {146 0 0-1206 {}} {146 0 0-1207 {}} {146 0 0-1208 {}} {146 0 0-1209 {}} {146 0 0-1210 {}} {146 0 0-1211 {}} {146 0 0-1212 {}} {146 0 0-1213 {}} {146 0 0-1214 {}} {130 0 0-1215 {}} {146 0 0-1216 {}} {146 0 0-1217 {}} {146 0 0-1218 {}} {146 0 0-1219 {}} {146 0 0-1220 {}}} CYCLES {}}
+set a(0-996) {NAME ACC1:conc#34 TYPE CONCATENATE PAR 0-818 XREFS 7055 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 2 0.134777025} PREDS {{146 0 0-995 {}} {258 0 0-970 {}}} SUCCS {{258 0 0-1007 {}}} CYCLES {}}
+set a(0-997) {NAME ACC2:slc(regs.regs(0)) TYPE READSLICE PAR 0-818 XREFS 7056 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-995 {}} {258 0 0-893 {}}} SUCCS {{259 0 0-998 {}}} CYCLES {}}
+set a(0-998) {NAME ACC2:not TYPE NOT PAR 0-818 XREFS 7057 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-995 {}} {259 0 0-997 {}}} SUCCS {{259 0 0-999 {}}} CYCLES {}}
+set a(0-999) {NAME ACC2:conc TYPE CONCATENATE PAR 0-818 XREFS 7058 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-995 {}} {259 0 0-998 {}}} SUCCS {{259 0 0-1000 {}}} CYCLES {}}
+set a(0-1000) {NAME ACC1:conc#32 TYPE CONCATENATE PAR 0-818 XREFS 7059 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-995 {}} {259 0 0-999 {}}} SUCCS {{258 0 0-1004 {}}} CYCLES {}}
+set a(0-1001) {NAME ACC2:slc(regs.regs(2)) TYPE READSLICE PAR 0-818 XREFS 7060 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-995 {}} {258 0 0-898 {}}} SUCCS {{259 0 0-1002 {}}} CYCLES {}}
+set a(0-1002) {NAME ACC2:conc#1 TYPE CONCATENATE PAR 0-818 XREFS 7061 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-995 {}} {259 0 0-1001 {}}} SUCCS {{259 0 0-1003 {}}} CYCLES {}}
+set a(0-1003) {NAME ACC1:conc#33 TYPE CONCATENATE PAR 0-818 XREFS 7062 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 2 0.055288775} PREDS {{146 0 0-995 {}} {259 0 0-1002 {}}} SUCCS {{259 0 0-1004 {}}} CYCLES {}}
+set a(0-1004) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME ACC1:acc#53 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-818 XREFS 7063 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.4018269034997777 2 0.13477697849977766} PREDS {{146 0 0-995 {}} {258 0 0-1000 {}} {259 0 0-1003 {}}} SUCCS {{259 0 0-1005 {}}} CYCLES {}}
+set a(0-1005) {NAME ACC1:slc#6 TYPE READSLICE PAR 0-818 XREFS 7064 LOC {1 0.18423425 1 0.40182694999999996 1 0.40182694999999996 2 0.134777025} PREDS {{146 0 0-995 {}} {259 0 0-1004 {}}} SUCCS {{259 0 0-1006 {}}} CYCLES {}}
+set a(0-1006) {NAME ACC1:conc#35 TYPE CONCATENATE PAR 0-818 XREFS 7065 LOC {1 0.18423425 1 0.40182694999999996 1 0.40182694999999996 2 0.134777025} PREDS {{146 0 0-995 {}} {259 0 0-1005 {}}} SUCCS {{259 0 0-1007 {}}} CYCLES {}}
+set a(0-1007) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(17,0,13,1,17) AREA_SCORE 18.00 QUANTITY 3 NAME ACC1:acc#54 TYPE ACCU DELAY {1.76 ns} LIBRARY_DELAY {1.76 ns} PAR 0-818 XREFS 7066 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 1 0.5117190147236815 2 0.24466908972368157} PREDS {{146 0 0-995 {}} {258 0 0-996 {}} {259 0 0-1006 {}}} SUCCS {{259 0 0-1008 {}}} CYCLES {}}
+set a(0-1008) {NAME ACC1:slc#7 TYPE READSLICE PAR 0-818 XREFS 7067 LOC {1 0.49040625 1 0.511719075 1 0.511719075 2 0.24466915} PREDS {{146 0 0-995 {}} {259 0 0-1007 {}}} SUCCS {{259 0 0-1009 {}}} CYCLES {}}
+set a(0-1009) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 3 NAME ACC1:acc#43 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-818 XREFS 7068 LOC {1 0.49040625 1 0.511719075 1 0.511719075 1 0.617328805357901 2 0.350278880357901} PREDS {{146 0 0-995 {}} {258 0 0-924 {}} {259 0 0-1008 {}}} SUCCS {{259 0 0-1010 {}}} CYCLES {}}
+set a(0-1010) {NAME ACC2:slc TYPE READSLICE PAR 0-818 XREFS 7069 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-995 {}} {259 0 0-1009 {}}} SUCCS {{258 0 0-1041 {}} {258 0 0-1042 {}} {258 0 0-1045 {}} {258 0 0-1047 {}} {258 0 0-1050 {}} {258 0 0-1053 {}} {258 0 0-1054 {}} {258 0 0-1169 {}} {258 0 0-1171 {}} {258 0 0-1172 {}} {258 0 0-1174 {}} {258 0 0-1177 {}} {258 0 0-1179 {}} {258 0 0-1196 {}}} CYCLES {}}
+set a(0-1011) {NAME ACC1:conc#38 TYPE CONCATENATE PAR 0-818 XREFS 7070 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 2 0.061150724999999996} PREDS {{146 0 0-995 {}} {258 0 0-979 {}}} SUCCS {{258 0 0-1022 {}}} CYCLES {}}
+set a(0-1012) {NAME ACC2:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-818 XREFS 7071 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {258 0 0-893 {}}} SUCCS {{259 0 0-1013 {}}} CYCLES {}}
+set a(0-1013) {NAME ACC2:not#1 TYPE NOT PAR 0-818 XREFS 7072 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {259 0 0-1012 {}}} SUCCS {{259 0 0-1014 {}}} CYCLES {}}
+set a(0-1014) {NAME ACC2:conc#2 TYPE CONCATENATE PAR 0-818 XREFS 7073 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {259 0 0-1013 {}}} SUCCS {{259 0 0-1015 {}}} CYCLES {}}
+set a(0-1015) {NAME ACC1:conc#36 TYPE CONCATENATE PAR 0-818 XREFS 7074 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {259 0 0-1014 {}}} SUCCS {{258 0 0-1019 {}}} CYCLES {}}
+set a(0-1016) {NAME ACC2:slc(regs.regs(2))#1 TYPE READSLICE PAR 0-818 XREFS 7075 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {258 0 0-898 {}}} SUCCS {{259 0 0-1017 {}}} CYCLES {}}
+set a(0-1017) {NAME ACC2:conc#3 TYPE CONCATENATE PAR 0-818 XREFS 7076 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {259 0 0-1016 {}}} SUCCS {{259 0 0-1018 {}}} CYCLES {}}
+set a(0-1018) {NAME ACC1:conc#37 TYPE CONCATENATE PAR 0-818 XREFS 7077 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {259 0 0-1017 {}}} SUCCS {{259 0 0-1019 {}}} CYCLES {}}
+set a(0-1019) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME ACC1:acc#55 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-818 XREFS 7078 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.4018269034997777 1 0.9999999534997777} PREDS {{146 0 0-995 {}} {258 0 0-1015 {}} {259 0 0-1018 {}}} SUCCS {{259 0 0-1020 {}}} CYCLES {}}
+set a(0-1020) {NAME ACC1:slc#8 TYPE READSLICE PAR 0-818 XREFS 7079 LOC {1 0.18423425 1 0.40182694999999996 1 0.40182694999999996 2 0.061150724999999996} PREDS {{146 0 0-995 {}} {259 0 0-1019 {}}} SUCCS {{259 0 0-1021 {}}} CYCLES {}}
+set a(0-1021) {NAME ACC1:conc#39 TYPE CONCATENATE PAR 0-818 XREFS 7080 LOC {1 0.18423425 1 0.40182694999999996 1 0.40182694999999996 2 0.061150724999999996} PREDS {{146 0 0-995 {}} {259 0 0-1020 {}}} SUCCS {{259 0 0-1022 {}}} CYCLES {}}
+set a(0-1022) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(17,0,13,1,17) AREA_SCORE 18.00 QUANTITY 3 NAME ACC1:acc#56 TYPE ACCU DELAY {1.76 ns} LIBRARY_DELAY {1.76 ns} PAR 0-818 XREFS 7081 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 1 0.5117190147236815 2 0.17104278972368156} PREDS {{146 0 0-995 {}} {258 0 0-1011 {}} {259 0 0-1021 {}}} SUCCS {{259 0 0-1023 {}}} CYCLES {}}
+set a(0-1023) {NAME ACC1:slc#9 TYPE READSLICE PAR 0-818 XREFS 7082 LOC {1 0.49040625 1 0.511719075 1 0.511719075 2 0.17104285} PREDS {{146 0 0-995 {}} {259 0 0-1022 {}}} SUCCS {{259 0 0-1024 {}}} CYCLES {}}
+set a(0-1024) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 3 NAME ACC1:acc#44 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-818 XREFS 7083 LOC {1 0.49040625 1 0.511719075 1 0.511719075 1 0.617328805357901 2 0.27665258035790097} PREDS {{146 0 0-995 {}} {258 0 0-934 {}} {259 0 0-1023 {}}} SUCCS {{259 0 0-1025 {}}} CYCLES {}}
+set a(0-1025) {NAME ACC2:slc#1 TYPE READSLICE PAR 0-818 XREFS 7084 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {259 0 0-1024 {}}} SUCCS {{258 0 0-1059 {}} {258 0 0-1060 {}} {258 0 0-1063 {}} {258 0 0-1065 {}} {258 0 0-1068 {}} {258 0 0-1071 {}} {258 0 0-1072 {}} {258 0 0-1077 {}} {258 0 0-1079 {}} {258 0 0-1081 {}} {258 0 0-1098 {}} {258 0 0-1107 {}} {258 0 0-1108 {}} {258 0 0-1110 {}}} CYCLES {}}
+set a(0-1026) {NAME ACC1:conc#42 TYPE CONCATENATE PAR 0-818 XREFS 7085 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 2 0.061150724999999996} PREDS {{146 0 0-995 {}} {258 0 0-988 {}}} SUCCS {{258 0 0-1037 {}}} CYCLES {}}
+set a(0-1027) {NAME ACC2:slc(regs.regs(0))#2 TYPE READSLICE PAR 0-818 XREFS 7086 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {258 0 0-893 {}}} SUCCS {{259 0 0-1028 {}}} CYCLES {}}
+set a(0-1028) {NAME ACC2:not#2 TYPE NOT PAR 0-818 XREFS 7087 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {259 0 0-1027 {}}} SUCCS {{259 0 0-1029 {}}} CYCLES {}}
+set a(0-1029) {NAME ACC2:conc#4 TYPE CONCATENATE PAR 0-818 XREFS 7088 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {259 0 0-1028 {}}} SUCCS {{259 0 0-1030 {}}} CYCLES {}}
+set a(0-1030) {NAME ACC1:conc#40 TYPE CONCATENATE PAR 0-818 XREFS 7089 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {259 0 0-1029 {}}} SUCCS {{258 0 0-1034 {}}} CYCLES {}}
+set a(0-1031) {NAME ACC2:slc(regs.regs(2))#2 TYPE READSLICE PAR 0-818 XREFS 7090 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {258 0 0-898 {}}} SUCCS {{259 0 0-1032 {}}} CYCLES {}}
+set a(0-1032) {NAME ACC2:conc#5 TYPE CONCATENATE PAR 0-818 XREFS 7091 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {259 0 0-1031 {}}} SUCCS {{259 0 0-1033 {}}} CYCLES {}}
+set a(0-1033) {NAME ACC1:conc#41 TYPE CONCATENATE PAR 0-818 XREFS 7092 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.92051175} PREDS {{146 0 0-995 {}} {259 0 0-1032 {}}} SUCCS {{259 0 0-1034 {}}} CYCLES {}}
+set a(0-1034) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME ACC1:acc#57 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-818 XREFS 7093 LOC {1 0.10474599999999999 1 0.3223387 1 0.3223387 1 0.4018269034997777 1 0.9999999534997777} PREDS {{146 0 0-995 {}} {258 0 0-1030 {}} {259 0 0-1033 {}}} SUCCS {{259 0 0-1035 {}}} CYCLES {}}
+set a(0-1035) {NAME ACC1:slc#10 TYPE READSLICE PAR 0-818 XREFS 7094 LOC {1 0.18423425 1 0.40182694999999996 1 0.40182694999999996 2 0.061150724999999996} PREDS {{146 0 0-995 {}} {259 0 0-1034 {}}} SUCCS {{259 0 0-1036 {}}} CYCLES {}}
+set a(0-1036) {NAME ACC1:conc#43 TYPE CONCATENATE PAR 0-818 XREFS 7095 LOC {1 0.18423425 1 0.40182694999999996 1 0.40182694999999996 2 0.061150724999999996} PREDS {{146 0 0-995 {}} {259 0 0-1035 {}}} SUCCS {{259 0 0-1037 {}}} CYCLES {}}
+set a(0-1037) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(17,0,13,1,17) AREA_SCORE 18.00 QUANTITY 3 NAME ACC1:acc#58 TYPE ACCU DELAY {1.76 ns} LIBRARY_DELAY {1.76 ns} PAR 0-818 XREFS 7096 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 1 0.5117190147236815 2 0.17104278972368156} PREDS {{146 0 0-995 {}} {258 0 0-1026 {}} {259 0 0-1036 {}}} SUCCS {{259 0 0-1038 {}}} CYCLES {}}
+set a(0-1038) {NAME ACC1:slc#11 TYPE READSLICE PAR 0-818 XREFS 7097 LOC {1 0.49040625 1 0.511719075 1 0.511719075 2 0.17104285} PREDS {{146 0 0-995 {}} {259 0 0-1037 {}}} SUCCS {{259 0 0-1039 {}}} CYCLES {}}
+set a(0-1039) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 3 NAME ACC1:acc#45 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-818 XREFS 7098 LOC {1 0.49040625 1 0.511719075 1 0.511719075 1 0.617328805357901 2 0.27665258035790097} PREDS {{146 0 0-995 {}} {258 0 0-944 {}} {259 0 0-1038 {}}} SUCCS {{259 0 0-1040 {}}} CYCLES {}}
+set a(0-1040) {NAME ACC2:slc#2 TYPE READSLICE PAR 0-818 XREFS 7099 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {259 0 0-1039 {}}} SUCCS {{258 0 0-1114 {}} {258 0 0-1115 {}} {258 0 0-1118 {}} {258 0 0-1120 {}} {258 0 0-1123 {}} {258 0 0-1126 {}} {258 0 0-1127 {}} {258 0 0-1132 {}} {258 0 0-1134 {}} {258 0 0-1136 {}} {258 0 0-1153 {}} {258 0 0-1162 {}} {258 0 0-1163 {}} {258 0 0-1165 {}}} CYCLES {}}
+set a(0-1041) {NAME red:slc(red#2.sg1)#4 TYPE READSLICE PAR 0-818 XREFS 7100 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{258 0 0-1044 {}}} CYCLES {}}
+set a(0-1042) {NAME red:slc(red#2.sg1)#5 TYPE READSLICE PAR 0-818 XREFS 7101 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{259 0 0-1043 {}}} CYCLES {}}
+set a(0-1043) {NAME FRAME:not#2 TYPE NOT PAR 0-818 XREFS 7102 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-995 {}} {259 0 0-1042 {}}} SUCCS {{259 0 0-1044 {}}} CYCLES {}}
+set a(0-1044) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#8 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-818 XREFS 7103 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.39783505207082714} PREDS {{146 0 0-995 {}} {258 0 0-1041 {}} {259 0 0-1043 {}}} SUCCS {{258 0 0-1052 {}}} CYCLES {}}
+set a(0-1045) {NAME red:slc(red#2.sg1)#6 TYPE READSLICE PAR 0-818 XREFS 7104 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{259 0 0-1046 {}}} CYCLES {}}
+set a(0-1046) {NAME FRAME:not#3 TYPE NOT PAR 0-818 XREFS 7105 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-995 {}} {259 0 0-1045 {}}} SUCCS {{258 0 0-1049 {}}} CYCLES {}}
+set a(0-1047) {NAME red:slc(red#2.sg1)#7 TYPE READSLICE PAR 0-818 XREFS 7106 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{259 0 0-1048 {}}} CYCLES {}}
+set a(0-1048) {NAME FRAME:not#25 TYPE NOT PAR 0-818 XREFS 7107 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-995 {}} {259 0 0-1047 {}}} SUCCS {{259 0 0-1049 {}}} CYCLES {}}
+set a(0-1049) {NAME FRAME:conc TYPE CONCATENATE PAR 0-818 XREFS 7108 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-995 {}} {258 0 0-1046 {}} {259 0 0-1048 {}}} SUCCS {{258 0 0-1051 {}}} CYCLES {}}
+set a(0-1050) {NAME red:slc(red#2.sg1)#1 TYPE READSLICE PAR 0-818 XREFS 7109 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{259 0 0-1051 {}}} CYCLES {}}
+set a(0-1051) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#7 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-818 XREFS 7110 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.39783505207082714} PREDS {{146 0 0-995 {}} {258 0 0-1049 {}} {259 0 0-1050 {}}} SUCCS {{259 0 0-1052 {}}} CYCLES {}}
+set a(0-1052) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#10 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-818 XREFS 7111 LOC {1 0.6435721999999999 1 0.664885025 1 0.664885025 1 0.7182320451789506 2 0.4511821201789505} PREDS {{146 0 0-995 {}} {258 0 0-1044 {}} {259 0 0-1051 {}}} SUCCS {{258 0 0-1057 {}}} CYCLES {}}
+set a(0-1053) {NAME red:slc(red#2.sg1)#2 TYPE READSLICE PAR 0-818 XREFS 7112 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.403626} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{258 0 0-1056 {}}} CYCLES {}}
+set a(0-1054) {NAME red:slc(red#2.sg1)#3 TYPE READSLICE PAR 0-818 XREFS 7113 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.403626} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{259 0 0-1055 {}}} CYCLES {}}
+set a(0-1055) {NAME FRAME:not#1 TYPE NOT PAR 0-818 XREFS 7114 LOC {1 0.596016025 1 0.670675925 1 0.670675925 2 0.403626} PREDS {{146 0 0-995 {}} {259 0 0-1054 {}}} SUCCS {{259 0 0-1056 {}}} CYCLES {}}
+set a(0-1056) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#9 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-818 XREFS 7115 LOC {1 0.596016025 1 0.670675925 1 0.670675925 1 0.7182320520708271 2 0.45118212707082717} PREDS {{146 0 0-995 {}} {258 0 0-1053 {}} {259 0 0-1055 {}}} SUCCS {{259 0 0-1057 {}}} CYCLES {}}
+set a(0-1057) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,4,0,6) AREA_SCORE 6.29 QUANTITY 3 NAME FRAME:acc#11 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 7116 LOC {1 0.696919275 1 0.7182320999999999 1 0.7182320999999999 1 0.7769849308637015 2 0.5099350058637016} PREDS {{146 0 0-995 {}} {258 0 0-1052 {}} {259 0 0-1056 {}}} SUCCS {{259 0 0-1058 {}}} CYCLES {}}
+set a(0-1058) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-818 XREFS 7117 LOC {1 0.75567215 1 0.776984975 1 0.776984975 1 0.8404969484103024 2 0.5734470234103024} PREDS {{146 0 0-995 {}} {259 0 0-1057 {}}} SUCCS {{258 0 0-1180 {}} {258 0 0-1182 {}} {258 0 0-1184 {}} {258 0 0-1186 {}} {258 0 0-1194 {}} {258 0 0-1199 {}}} CYCLES {}}
+set a(0-1059) {NAME green:slc(green#2.sg1)#4 TYPE READSLICE PAR 0-818 XREFS 7118 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{258 0 0-1062 {}}} CYCLES {}}
+set a(0-1060) {NAME green:slc(green#2.sg1)#5 TYPE READSLICE PAR 0-818 XREFS 7119 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{259 0 0-1061 {}}} CYCLES {}}
+set a(0-1061) {NAME FRAME:not#10 TYPE NOT PAR 0-818 XREFS 7120 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {259 0 0-1060 {}}} SUCCS {{259 0 0-1062 {}}} CYCLES {}}
+set a(0-1062) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#13 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-818 XREFS 7121 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.32420875207082717} PREDS {{146 0 0-995 {}} {258 0 0-1059 {}} {259 0 0-1061 {}}} SUCCS {{258 0 0-1070 {}}} CYCLES {}}
+set a(0-1063) {NAME green:slc(green#2.sg1)#6 TYPE READSLICE PAR 0-818 XREFS 7122 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{259 0 0-1064 {}}} CYCLES {}}
+set a(0-1064) {NAME FRAME:not#11 TYPE NOT PAR 0-818 XREFS 7123 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {259 0 0-1063 {}}} SUCCS {{258 0 0-1067 {}}} CYCLES {}}
+set a(0-1065) {NAME green:slc(green#2.sg1)#7 TYPE READSLICE PAR 0-818 XREFS 7124 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{259 0 0-1066 {}}} CYCLES {}}
+set a(0-1066) {NAME FRAME:not#26 TYPE NOT PAR 0-818 XREFS 7125 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {259 0 0-1065 {}}} SUCCS {{259 0 0-1067 {}}} CYCLES {}}
+set a(0-1067) {NAME FRAME:conc#16 TYPE CONCATENATE PAR 0-818 XREFS 7126 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {258 0 0-1064 {}} {259 0 0-1066 {}}} SUCCS {{258 0 0-1069 {}}} CYCLES {}}
+set a(0-1068) {NAME green:slc(green#2.sg1)#1 TYPE READSLICE PAR 0-818 XREFS 7127 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{259 0 0-1069 {}}} CYCLES {}}
+set a(0-1069) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#12 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-818 XREFS 7128 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.32420875207082717} PREDS {{146 0 0-995 {}} {258 0 0-1067 {}} {259 0 0-1068 {}}} SUCCS {{259 0 0-1070 {}}} CYCLES {}}
+set a(0-1070) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#15 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-818 XREFS 7129 LOC {1 0.6435721999999999 1 0.664885025 1 0.664885025 1 0.7182320451789506 2 0.37755582017895045} PREDS {{146 0 0-995 {}} {258 0 0-1062 {}} {259 0 0-1069 {}}} SUCCS {{258 0 0-1075 {}}} CYCLES {}}
+set a(0-1071) {NAME green:slc(green#2.sg1)#2 TYPE READSLICE PAR 0-818 XREFS 7130 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.3299997} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{258 0 0-1074 {}}} CYCLES {}}
+set a(0-1072) {NAME green:slc(green#2.sg1)#3 TYPE READSLICE PAR 0-818 XREFS 7131 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.3299997} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{259 0 0-1073 {}}} CYCLES {}}
+set a(0-1073) {NAME FRAME:not#9 TYPE NOT PAR 0-818 XREFS 7132 LOC {1 0.596016025 1 0.670675925 1 0.670675925 2 0.3299997} PREDS {{146 0 0-995 {}} {259 0 0-1072 {}}} SUCCS {{259 0 0-1074 {}}} CYCLES {}}
+set a(0-1074) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#14 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-818 XREFS 7133 LOC {1 0.596016025 1 0.670675925 1 0.670675925 1 0.7182320520708271 2 0.3775558270708272} PREDS {{146 0 0-995 {}} {258 0 0-1071 {}} {259 0 0-1073 {}}} SUCCS {{259 0 0-1075 {}}} CYCLES {}}
+set a(0-1075) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,4,0,6) AREA_SCORE 6.29 QUANTITY 3 NAME FRAME:acc#16 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 7134 LOC {1 0.696919275 1 0.7182320999999999 1 0.7182320999999999 1 0.7769849308637015 2 0.4363087058637015} PREDS {{146 0 0-995 {}} {258 0 0-1070 {}} {259 0 0-1074 {}}} SUCCS {{259 0 0-1076 {}}} CYCLES {}}
+set a(0-1076) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc#2 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-818 XREFS 7135 LOC {1 0.75567215 1 0.776984975 1 0.776984975 1 0.8404969484103024 2 0.49982072341030237} PREDS {{146 0 0-995 {}} {259 0 0-1075 {}}} SUCCS {{258 0 0-1082 {}} {258 0 0-1084 {}} {258 0 0-1086 {}} {258 0 0-1088 {}} {258 0 0-1096 {}} {258 0 0-1101 {}}} CYCLES {}}
+set a(0-1077) {NAME green:slc(green#2.sg1)#9 TYPE READSLICE PAR 0-818 XREFS 7136 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.6380319249999999} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{259 0 0-1078 {}}} CYCLES {}}
+set a(0-1078) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#2 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-818 XREFS 7137 LOC {1 0.596016025 1 0.809739975 1 0.809739975 1 0.9999999562499999 2 0.8282919062499999} PREDS {{146 0 0-995 {}} {259 0 0-1077 {}}} SUCCS {{258 0 0-1106 {}}} CYCLES {}}
+set a(0-1079) {NAME green:slc(green#2.sg1)#11 TYPE READSLICE PAR 0-818 XREFS 7138 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.5833817} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{259 0 0-1080 {}}} CYCLES {}}
+set a(0-1080) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#3 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-818 XREFS 7139 LOC {1 0.596016025 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.7612634921744312} PREDS {{146 0 0-995 {}} {259 0 0-1079 {}}} SUCCS {{258 0 0-1105 {}}} CYCLES {}}
+set a(0-1081) {NAME green:slc(green#2.sg1) TYPE READSLICE PAR 0-818 XREFS 7140 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.717923525} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{258 0 0-1104 {}}} CYCLES {}}
+set a(0-1082) {NAME FRAME:slc(acc.imod#2)#6 TYPE READSLICE PAR 0-818 XREFS 7141 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.558420525} PREDS {{146 0 0-995 {}} {258 0 0-1076 {}}} SUCCS {{259 0 0-1083 {}}} CYCLES {}}
+set a(0-1083) {NAME FRAME:not#15 TYPE NOT PAR 0-818 XREFS 7142 LOC {1 0.819184175 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-995 {}} {259 0 0-1082 {}}} SUCCS {{258 0 0-1095 {}}} CYCLES {}}
+set a(0-1084) {NAME FRAME:slc(acc.imod#2)#1 TYPE READSLICE PAR 0-818 XREFS 7143 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {258 0 0-1076 {}}} SUCCS {{259 0 0-1085 {}}} CYCLES {}}
+set a(0-1085) {NAME FRAME:conc#24 TYPE CONCATENATE PAR 0-818 XREFS 7144 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {259 0 0-1084 {}}} SUCCS {{258 0 0-1091 {}}} CYCLES {}}
+set a(0-1086) {NAME FRAME:slc(acc.imod#2)#2 TYPE READSLICE PAR 0-818 XREFS 7145 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {258 0 0-1076 {}}} SUCCS {{259 0 0-1087 {}}} CYCLES {}}
+set a(0-1087) {NAME FRAME:not#13 TYPE NOT PAR 0-818 XREFS 7146 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {259 0 0-1086 {}}} SUCCS {{258 0 0-1090 {}}} CYCLES {}}
+set a(0-1088) {NAME FRAME:slc(acc.imod#2) TYPE READSLICE PAR 0-818 XREFS 7147 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {258 0 0-1076 {}}} SUCCS {{259 0 0-1089 {}}} CYCLES {}}
+set a(0-1089) {NAME FRAME:not#12 TYPE NOT PAR 0-818 XREFS 7148 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {259 0 0-1088 {}}} SUCCS {{259 0 0-1090 {}}} CYCLES {}}
+set a(0-1090) {NAME FRAME:conc#25 TYPE CONCATENATE PAR 0-818 XREFS 7149 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {258 0 0-1087 {}} {259 0 0-1089 {}}} SUCCS {{259 0 0-1091 {}}} CYCLES {}}
+set a(0-1091) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#23 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 7150 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 1 0.899096709496936 2 0.558420484496936} PREDS {{146 0 0-995 {}} {258 0 0-1085 {}} {259 0 0-1090 {}}} SUCCS {{259 0 0-1092 {}}} CYCLES {}}
+set a(0-1092) {NAME FRAME:slc#5 TYPE READSLICE PAR 0-818 XREFS 7151 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-995 {}} {259 0 0-1091 {}}} SUCCS {{259 0 0-1093 {}}} CYCLES {}}
+set a(0-1093) {NAME FRAME:slc#3 TYPE READSLICE PAR 0-818 XREFS 7152 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-995 {}} {259 0 0-1092 {}}} SUCCS {{259 0 0-1094 {}}} CYCLES {}}
+set a(0-1094) {NAME FRAME:not#16 TYPE NOT PAR 0-818 XREFS 7153 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-995 {}} {259 0 0-1093 {}}} SUCCS {{259 0 0-1095 {}}} CYCLES {}}
+set a(0-1095) {NAME FRAME:conc#7 TYPE CONCATENATE PAR 0-818 XREFS 7154 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-995 {}} {258 0 0-1083 {}} {259 0 0-1094 {}}} SUCCS {{258 0 0-1097 {}}} CYCLES {}}
+set a(0-1096) {NAME FRAME:slc(acc.imod#2)#5 TYPE READSLICE PAR 0-818 XREFS 7155 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.558420525} PREDS {{146 0 0-995 {}} {258 0 0-1076 {}}} SUCCS {{259 0 0-1097 {}}} CYCLES {}}
+set a(0-1097) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#17 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-818 XREFS 7156 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 1 0.9466528770708271 2 0.6059766520708271} PREDS {{146 0 0-995 {}} {258 0 0-1095 {}} {259 0 0-1096 {}}} SUCCS {{258 0 0-1100 {}}} CYCLES {}}
+set a(0-1098) {NAME green:slc(green#2.sg1)#10 TYPE READSLICE PAR 0-818 XREFS 7157 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.6059766999999999} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{259 0 0-1099 {}}} CYCLES {}}
+set a(0-1099) {NAME FRAME:not#14 TYPE NOT PAR 0-818 XREFS 7158 LOC {1 0.596016025 1 0.946652925 1 0.946652925 2 0.6059766999999999} PREDS {{146 0 0-995 {}} {259 0 0-1098 {}}} SUCCS {{259 0 0-1100 {}}} CYCLES {}}
+set a(0-1100) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#18 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-818 XREFS 7159 LOC {1 0.9253401 1 0.946652925 1 0.946652925 1 0.9999999451789505 2 0.6593237201789504} PREDS {{146 0 0-995 {}} {258 0 0-1097 {}} {259 0 0-1099 {}}} SUCCS {{258 0 0-1103 {}}} CYCLES {}}
+set a(0-1101) {NAME FRAME:slc(acc.imod#2)#4 TYPE READSLICE PAR 0-818 XREFS 7160 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.659323775} PREDS {{146 0 0-995 {}} {258 0 0-1076 {}}} SUCCS {{259 0 0-1102 {}}} CYCLES {}}
+set a(0-1102) {NAME FRAME:conc#22 TYPE CONCATENATE PAR 0-818 XREFS 7161 LOC {1 0.819184175 2 0.659323775 2 0.659323775 2 0.659323775} PREDS {{146 0 0-995 {}} {259 0 0-1101 {}}} SUCCS {{259 0 0-1103 {}}} CYCLES {}}
+set a(0-1103) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#19 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 7162 LOC {2 0.0 2 0.659323775 2 0.659323775 2 0.717923484496936 2 0.717923484496936} PREDS {{146 0 0-995 {}} {258 0 0-1100 {}} {259 0 0-1102 {}}} SUCCS {{259 0 0-1104 {}}} CYCLES {}}
+set a(0-1104) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#20 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-818 XREFS 7163 LOC {2 0.05859975 2 0.717923525 2 0.717923525 2 0.7612634907468815 2 0.7612634907468815} PREDS {{146 0 0-995 {}} {258 0 0-1081 {}} {259 0 0-1103 {}}} SUCCS {{259 0 0-1105 {}}} CYCLES {}}
+set a(0-1105) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#21 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-818 XREFS 7164 LOC {2 0.101939775 2 0.76126355 2 0.76126355 2 0.82829190686502 2 0.82829190686502} PREDS {{146 0 0-995 {}} {258 0 0-1080 {}} {259 0 0-1104 {}}} SUCCS {{259 0 0-1106 {}}} CYCLES {}}
+set a(0-1106) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,10,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME FRAME:acc#22 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-818 XREFS 7165 LOC {2 0.168968175 2 0.82829195 2 0.82829195 2 0.9037692343138832 2 0.9037692343138832} PREDS {{146 0 0-995 {}} {258 0 0-1078 {}} {259 0 0-1105 {}}} SUCCS {{258 0 0-1113 {}}} CYCLES {}}
+set a(0-1107) {NAME green:slc(green#2.sg1)#12 TYPE READSLICE PAR 0-818 XREFS 7166 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.9037692749999999} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{258 0 0-1111 {}}} CYCLES {}}
+set a(0-1108) {NAME green:slc(green#2.sg1)#13 TYPE READSLICE PAR 0-818 XREFS 7167 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.9037692749999999} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{259 0 0-1109 {}}} CYCLES {}}
+set a(0-1109) {NAME FRAME:exs#3 TYPE SIGNEXTEND PAR 0-818 XREFS 7168 LOC {1 0.596016025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-995 {}} {259 0 0-1108 {}}} SUCCS {{258 0 0-1111 {}}} CYCLES {}}
+set a(0-1110) {NAME green:slc(green#2.sg1)#8 TYPE READSLICE PAR 0-818 XREFS 7169 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.9037692749999999} PREDS {{146 0 0-995 {}} {258 0 0-1025 {}}} SUCCS {{259 0 0-1111 {}}} CYCLES {}}
+set a(0-1111) {NAME FRAME:conc#6 TYPE CONCATENATE PAR 0-818 XREFS 7170 LOC {1 0.596016025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-995 {}} {258 0 0-1109 {}} {258 0 0-1107 {}} {259 0 0-1110 {}}} SUCCS {{259 0 0-1112 {}}} CYCLES {}}
+set a(0-1112) {NAME FRAME:exs#2 TYPE SIGNEXTEND PAR 0-818 XREFS 7171 LOC {1 0.596016025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-995 {}} {259 0 0-1111 {}}} SUCCS {{259 0 0-1113 {}}} CYCLES {}}
+set a(0-1113) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME FRAME:acc#3 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-818 XREFS 7172 LOC {2 0.24444549999999998 2 0.9037692749999999 2 0.9037692749999999 2 0.9832574784997776 2 0.9832574784997776} PREDS {{146 0 0-995 {}} {258 0 0-1106 {}} {259 0 0-1112 {}}} SUCCS {{258 0 0-1205 {}} {258 0 0-1208 {}} {258 0 0-1209 {}}} CYCLES {}}
+set a(0-1114) {NAME blue:slc(blue#2.sg1)#4 TYPE READSLICE PAR 0-818 XREFS 7173 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{258 0 0-1117 {}}} CYCLES {}}
+set a(0-1115) {NAME blue:slc(blue#2.sg1)#5 TYPE READSLICE PAR 0-818 XREFS 7174 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{259 0 0-1116 {}}} CYCLES {}}
+set a(0-1116) {NAME FRAME:not#18 TYPE NOT PAR 0-818 XREFS 7175 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {259 0 0-1115 {}}} SUCCS {{259 0 0-1117 {}}} CYCLES {}}
+set a(0-1117) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#25 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-818 XREFS 7176 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.32420875207082717} PREDS {{146 0 0-995 {}} {258 0 0-1114 {}} {259 0 0-1116 {}}} SUCCS {{258 0 0-1125 {}}} CYCLES {}}
+set a(0-1118) {NAME blue:slc(blue#2.sg1)#6 TYPE READSLICE PAR 0-818 XREFS 7177 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{259 0 0-1119 {}}} CYCLES {}}
+set a(0-1119) {NAME FRAME:not#19 TYPE NOT PAR 0-818 XREFS 7178 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {259 0 0-1118 {}}} SUCCS {{258 0 0-1122 {}}} CYCLES {}}
+set a(0-1120) {NAME blue:slc(blue#2.sg1)#7 TYPE READSLICE PAR 0-818 XREFS 7179 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{259 0 0-1121 {}}} CYCLES {}}
+set a(0-1121) {NAME FRAME:not#27 TYPE NOT PAR 0-818 XREFS 7180 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {259 0 0-1120 {}}} SUCCS {{259 0 0-1122 {}}} CYCLES {}}
+set a(0-1122) {NAME FRAME:conc#17 TYPE CONCATENATE PAR 0-818 XREFS 7181 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {258 0 0-1119 {}} {259 0 0-1121 {}}} SUCCS {{258 0 0-1124 {}}} CYCLES {}}
+set a(0-1123) {NAME blue:slc(blue#2.sg1)#1 TYPE READSLICE PAR 0-818 XREFS 7182 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.276652625} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{259 0 0-1124 {}}} CYCLES {}}
+set a(0-1124) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#24 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-818 XREFS 7183 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.32420875207082717} PREDS {{146 0 0-995 {}} {258 0 0-1122 {}} {259 0 0-1123 {}}} SUCCS {{259 0 0-1125 {}}} CYCLES {}}
+set a(0-1125) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#27 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-818 XREFS 7184 LOC {1 0.6435721999999999 1 0.664885025 1 0.664885025 1 0.7182320451789506 2 0.37755582017895045} PREDS {{146 0 0-995 {}} {258 0 0-1117 {}} {259 0 0-1124 {}}} SUCCS {{258 0 0-1130 {}}} CYCLES {}}
+set a(0-1126) {NAME blue:slc(blue#2.sg1)#2 TYPE READSLICE PAR 0-818 XREFS 7185 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.3299997} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{258 0 0-1129 {}}} CYCLES {}}
+set a(0-1127) {NAME blue:slc(blue#2.sg1)#3 TYPE READSLICE PAR 0-818 XREFS 7186 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.3299997} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{259 0 0-1128 {}}} CYCLES {}}
+set a(0-1128) {NAME FRAME:not#17 TYPE NOT PAR 0-818 XREFS 7187 LOC {1 0.596016025 1 0.670675925 1 0.670675925 2 0.3299997} PREDS {{146 0 0-995 {}} {259 0 0-1127 {}}} SUCCS {{259 0 0-1129 {}}} CYCLES {}}
+set a(0-1129) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#26 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-818 XREFS 7188 LOC {1 0.596016025 1 0.670675925 1 0.670675925 1 0.7182320520708271 2 0.3775558270708272} PREDS {{146 0 0-995 {}} {258 0 0-1126 {}} {259 0 0-1128 {}}} SUCCS {{259 0 0-1130 {}}} CYCLES {}}
+set a(0-1130) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,4,0,6) AREA_SCORE 6.29 QUANTITY 3 NAME FRAME:acc#28 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 7189 LOC {1 0.696919275 1 0.7182320999999999 1 0.7182320999999999 1 0.7769849308637015 2 0.4363087058637015} PREDS {{146 0 0-995 {}} {258 0 0-1125 {}} {259 0 0-1129 {}}} SUCCS {{259 0 0-1131 {}}} CYCLES {}}
+set a(0-1131) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc#4 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-818 XREFS 7190 LOC {1 0.75567215 1 0.776984975 1 0.776984975 1 0.8404969484103024 2 0.49982072341030237} PREDS {{146 0 0-995 {}} {259 0 0-1130 {}}} SUCCS {{258 0 0-1137 {}} {258 0 0-1139 {}} {258 0 0-1141 {}} {258 0 0-1143 {}} {258 0 0-1151 {}} {258 0 0-1156 {}}} CYCLES {}}
+set a(0-1132) {NAME blue:slc(blue#2.sg1)#9 TYPE READSLICE PAR 0-818 XREFS 7191 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.6380319249999999} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{259 0 0-1133 {}}} CYCLES {}}
+set a(0-1133) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#4 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-818 XREFS 7192 LOC {1 0.596016025 1 0.809739975 1 0.809739975 1 0.9999999562499999 2 0.8282919062499999} PREDS {{146 0 0-995 {}} {259 0 0-1132 {}}} SUCCS {{258 0 0-1161 {}}} CYCLES {}}
+set a(0-1134) {NAME blue:slc(blue#2.sg1)#11 TYPE READSLICE PAR 0-818 XREFS 7193 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.5833817} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{259 0 0-1135 {}}} CYCLES {}}
+set a(0-1135) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#5 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-818 XREFS 7194 LOC {1 0.596016025 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.7612634921744312} PREDS {{146 0 0-995 {}} {259 0 0-1134 {}}} SUCCS {{258 0 0-1160 {}}} CYCLES {}}
+set a(0-1136) {NAME blue:slc(blue#2.sg1) TYPE READSLICE PAR 0-818 XREFS 7195 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.717923525} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{258 0 0-1159 {}}} CYCLES {}}
+set a(0-1137) {NAME FRAME:slc(acc.imod#4)#6 TYPE READSLICE PAR 0-818 XREFS 7196 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.558420525} PREDS {{146 0 0-995 {}} {258 0 0-1131 {}}} SUCCS {{259 0 0-1138 {}}} CYCLES {}}
+set a(0-1138) {NAME FRAME:not#23 TYPE NOT PAR 0-818 XREFS 7197 LOC {1 0.819184175 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-995 {}} {259 0 0-1137 {}}} SUCCS {{258 0 0-1150 {}}} CYCLES {}}
+set a(0-1139) {NAME FRAME:slc(acc.imod#4)#1 TYPE READSLICE PAR 0-818 XREFS 7198 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {258 0 0-1131 {}}} SUCCS {{259 0 0-1140 {}}} CYCLES {}}
+set a(0-1140) {NAME FRAME:conc#28 TYPE CONCATENATE PAR 0-818 XREFS 7199 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {259 0 0-1139 {}}} SUCCS {{258 0 0-1146 {}}} CYCLES {}}
+set a(0-1141) {NAME FRAME:slc(acc.imod#4)#2 TYPE READSLICE PAR 0-818 XREFS 7200 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {258 0 0-1131 {}}} SUCCS {{259 0 0-1142 {}}} CYCLES {}}
+set a(0-1142) {NAME FRAME:not#21 TYPE NOT PAR 0-818 XREFS 7201 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {259 0 0-1141 {}}} SUCCS {{258 0 0-1145 {}}} CYCLES {}}
+set a(0-1143) {NAME FRAME:slc(acc.imod#4) TYPE READSLICE PAR 0-818 XREFS 7202 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {258 0 0-1131 {}}} SUCCS {{259 0 0-1144 {}}} CYCLES {}}
+set a(0-1144) {NAME FRAME:not#20 TYPE NOT PAR 0-818 XREFS 7203 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {259 0 0-1143 {}}} SUCCS {{259 0 0-1145 {}}} CYCLES {}}
+set a(0-1145) {NAME FRAME:conc#29 TYPE CONCATENATE PAR 0-818 XREFS 7204 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.499820775} PREDS {{146 0 0-995 {}} {258 0 0-1142 {}} {259 0 0-1144 {}}} SUCCS {{259 0 0-1146 {}}} CYCLES {}}
+set a(0-1146) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#35 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 7205 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 1 0.899096709496936 2 0.558420484496936} PREDS {{146 0 0-995 {}} {258 0 0-1140 {}} {259 0 0-1145 {}}} SUCCS {{259 0 0-1147 {}}} CYCLES {}}
+set a(0-1147) {NAME FRAME:slc#6 TYPE READSLICE PAR 0-818 XREFS 7206 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-995 {}} {259 0 0-1146 {}}} SUCCS {{259 0 0-1148 {}}} CYCLES {}}
+set a(0-1148) {NAME FRAME:slc#4 TYPE READSLICE PAR 0-818 XREFS 7207 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-995 {}} {259 0 0-1147 {}}} SUCCS {{259 0 0-1149 {}}} CYCLES {}}
+set a(0-1149) {NAME FRAME:not#24 TYPE NOT PAR 0-818 XREFS 7208 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-995 {}} {259 0 0-1148 {}}} SUCCS {{259 0 0-1150 {}}} CYCLES {}}
+set a(0-1150) {NAME FRAME:conc#11 TYPE CONCATENATE PAR 0-818 XREFS 7209 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.558420525} PREDS {{146 0 0-995 {}} {258 0 0-1138 {}} {259 0 0-1149 {}}} SUCCS {{258 0 0-1152 {}}} CYCLES {}}
+set a(0-1151) {NAME FRAME:slc(acc.imod#4)#5 TYPE READSLICE PAR 0-818 XREFS 7210 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.558420525} PREDS {{146 0 0-995 {}} {258 0 0-1131 {}}} SUCCS {{259 0 0-1152 {}}} CYCLES {}}
+set a(0-1152) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#29 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-818 XREFS 7211 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 1 0.9466528770708271 2 0.6059766520708271} PREDS {{146 0 0-995 {}} {258 0 0-1150 {}} {259 0 0-1151 {}}} SUCCS {{258 0 0-1155 {}}} CYCLES {}}
+set a(0-1153) {NAME blue:slc(blue#2.sg1)#10 TYPE READSLICE PAR 0-818 XREFS 7212 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.6059766999999999} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{259 0 0-1154 {}}} CYCLES {}}
+set a(0-1154) {NAME FRAME:not#22 TYPE NOT PAR 0-818 XREFS 7213 LOC {1 0.596016025 1 0.946652925 1 0.946652925 2 0.6059766999999999} PREDS {{146 0 0-995 {}} {259 0 0-1153 {}}} SUCCS {{259 0 0-1155 {}}} CYCLES {}}
+set a(0-1155) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#30 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-818 XREFS 7214 LOC {1 0.9253401 1 0.946652925 1 0.946652925 1 0.9999999451789505 2 0.6593237201789504} PREDS {{146 0 0-995 {}} {258 0 0-1152 {}} {259 0 0-1154 {}}} SUCCS {{258 0 0-1158 {}}} CYCLES {}}
+set a(0-1156) {NAME FRAME:slc(acc.imod#4)#4 TYPE READSLICE PAR 0-818 XREFS 7215 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.659323775} PREDS {{146 0 0-995 {}} {258 0 0-1131 {}}} SUCCS {{259 0 0-1157 {}}} CYCLES {}}
+set a(0-1157) {NAME FRAME:conc#26 TYPE CONCATENATE PAR 0-818 XREFS 7216 LOC {1 0.819184175 2 0.659323775 2 0.659323775 2 0.659323775} PREDS {{146 0 0-995 {}} {259 0 0-1156 {}}} SUCCS {{259 0 0-1158 {}}} CYCLES {}}
+set a(0-1158) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#31 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 7217 LOC {2 0.0 2 0.659323775 2 0.659323775 2 0.717923484496936 2 0.717923484496936} PREDS {{146 0 0-995 {}} {258 0 0-1155 {}} {259 0 0-1157 {}}} SUCCS {{259 0 0-1159 {}}} CYCLES {}}
+set a(0-1159) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#32 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-818 XREFS 7218 LOC {2 0.05859975 2 0.717923525 2 0.717923525 2 0.7612634907468815 2 0.7612634907468815} PREDS {{146 0 0-995 {}} {258 0 0-1136 {}} {259 0 0-1158 {}}} SUCCS {{259 0 0-1160 {}}} CYCLES {}}
+set a(0-1160) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#33 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-818 XREFS 7219 LOC {2 0.101939775 2 0.76126355 2 0.76126355 2 0.82829190686502 2 0.82829190686502} PREDS {{146 0 0-995 {}} {258 0 0-1135 {}} {259 0 0-1159 {}}} SUCCS {{259 0 0-1161 {}}} CYCLES {}}
+set a(0-1161) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,10,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME FRAME:acc#34 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-818 XREFS 7220 LOC {2 0.168968175 2 0.82829195 2 0.82829195 2 0.9037692343138832 2 0.9037692343138832} PREDS {{146 0 0-995 {}} {258 0 0-1133 {}} {259 0 0-1160 {}}} SUCCS {{258 0 0-1168 {}}} CYCLES {}}
+set a(0-1162) {NAME blue:slc(blue#2.sg1)#12 TYPE READSLICE PAR 0-818 XREFS 7221 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.9037692749999999} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{258 0 0-1166 {}}} CYCLES {}}
+set a(0-1163) {NAME blue:slc(blue#2.sg1)#13 TYPE READSLICE PAR 0-818 XREFS 7222 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.9037692749999999} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{259 0 0-1164 {}}} CYCLES {}}
+set a(0-1164) {NAME FRAME:exs#5 TYPE SIGNEXTEND PAR 0-818 XREFS 7223 LOC {1 0.596016025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-995 {}} {259 0 0-1163 {}}} SUCCS {{258 0 0-1166 {}}} CYCLES {}}
+set a(0-1165) {NAME blue:slc(blue#2.sg1)#8 TYPE READSLICE PAR 0-818 XREFS 7224 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.9037692749999999} PREDS {{146 0 0-995 {}} {258 0 0-1040 {}}} SUCCS {{259 0 0-1166 {}}} CYCLES {}}
+set a(0-1166) {NAME FRAME:conc#10 TYPE CONCATENATE PAR 0-818 XREFS 7225 LOC {1 0.596016025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-995 {}} {258 0 0-1164 {}} {258 0 0-1162 {}} {259 0 0-1165 {}}} SUCCS {{259 0 0-1167 {}}} CYCLES {}}
+set a(0-1167) {NAME FRAME:exs#4 TYPE SIGNEXTEND PAR 0-818 XREFS 7226 LOC {1 0.596016025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-995 {}} {259 0 0-1166 {}}} SUCCS {{259 0 0-1168 {}}} CYCLES {}}
+set a(0-1168) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME FRAME:acc#4 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-818 XREFS 7227 LOC {2 0.24444549999999998 2 0.9037692749999999 2 0.9037692749999999 2 0.9832574784997776 2 0.9832574784997776} PREDS {{146 0 0-995 {}} {258 0 0-1161 {}} {259 0 0-1167 {}}} SUCCS {{258 0 0-1210 {}} {258 0 0-1213 {}}} CYCLES {}}
+set a(0-1169) {NAME red:slc(red#2.sg1)#13 TYPE READSLICE PAR 0-818 XREFS 7228 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.63020875} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{259 0 0-1170 {}}} CYCLES {}}
+set a(0-1170) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-818 XREFS 7229 LOC {1 0.596016025 1 0.7282905 1 0.7282905 1 0.9185504812499999 2 0.82046873125} PREDS {{146 0 0-995 {}} {259 0 0-1169 {}}} SUCCS {{258 0 0-1176 {}}} CYCLES {}}
+set a(0-1171) {NAME red:slc(red#2.sg1)#11 TYPE READSLICE PAR 0-818 XREFS 7230 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.8204687749999999} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{258 0 0-1175 {}}} CYCLES {}}
+set a(0-1172) {NAME red:slc(red#2.sg1)#12 TYPE READSLICE PAR 0-818 XREFS 7231 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.8204687749999999} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{259 0 0-1173 {}}} CYCLES {}}
+set a(0-1173) {NAME FRAME:exs#1 TYPE SIGNEXTEND PAR 0-818 XREFS 7232 LOC {1 0.596016025 1 0.918550525 1 0.918550525 2 0.8204687749999999} PREDS {{146 0 0-995 {}} {259 0 0-1172 {}}} SUCCS {{258 0 0-1175 {}}} CYCLES {}}
+set a(0-1174) {NAME red:slc(red#2.sg1)#8 TYPE READSLICE PAR 0-818 XREFS 7233 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.8204687749999999} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{259 0 0-1175 {}}} CYCLES {}}
+set a(0-1175) {NAME FRAME:conc#2 TYPE CONCATENATE PAR 0-818 XREFS 7234 LOC {1 0.596016025 1 0.918550525 1 0.918550525 2 0.8204687749999999} PREDS {{146 0 0-995 {}} {258 0 0-1173 {}} {258 0 0-1171 {}} {259 0 0-1174 {}}} SUCCS {{259 0 0-1176 {}}} CYCLES {}}
+set a(0-1176) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,9,1,10) AREA_SCORE 11.00 QUANTITY 1 NAME FRAME:acc#41 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-818 XREFS 7235 LOC {1 0.78627605 1 0.918550525 1 0.918550525 1 0.9999999444798112 2 0.9019181944798111} PREDS {{146 0 0-995 {}} {258 0 0-1170 {}} {259 0 0-1175 {}}} SUCCS {{258 0 0-1204 {}}} CYCLES {}}
+set a(0-1177) {NAME red:slc(red#2.sg1)#10 TYPE READSLICE PAR 0-818 XREFS 7236 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.6570079999999999} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{259 0 0-1178 {}}} CYCLES {}}
+set a(0-1178) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#1 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-818 XREFS 7237 LOC {1 0.596016025 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.8348897921744312} PREDS {{146 0 0-995 {}} {259 0 0-1177 {}}} SUCCS {{258 0 0-1203 {}}} CYCLES {}}
+set a(0-1179) {NAME red:slc(red#2.sg1) TYPE READSLICE PAR 0-818 XREFS 7238 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.7915498249999999} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{258 0 0-1202 {}}} CYCLES {}}
+set a(0-1180) {NAME FRAME:slc(acc.imod)#6 TYPE READSLICE PAR 0-818 XREFS 7239 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.632046825} PREDS {{146 0 0-995 {}} {258 0 0-1058 {}}} SUCCS {{259 0 0-1181 {}}} CYCLES {}}
+set a(0-1181) {NAME FRAME:not#7 TYPE NOT PAR 0-818 XREFS 7240 LOC {1 0.819184175 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-995 {}} {259 0 0-1180 {}}} SUCCS {{258 0 0-1193 {}}} CYCLES {}}
+set a(0-1182) {NAME FRAME:slc(acc.imod)#1 TYPE READSLICE PAR 0-818 XREFS 7241 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-995 {}} {258 0 0-1058 {}}} SUCCS {{259 0 0-1183 {}}} CYCLES {}}
+set a(0-1183) {NAME FRAME:conc#32 TYPE CONCATENATE PAR 0-818 XREFS 7242 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-995 {}} {259 0 0-1182 {}}} SUCCS {{258 0 0-1189 {}}} CYCLES {}}
+set a(0-1184) {NAME FRAME:slc(acc.imod)#2 TYPE READSLICE PAR 0-818 XREFS 7243 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-995 {}} {258 0 0-1058 {}}} SUCCS {{259 0 0-1185 {}}} CYCLES {}}
+set a(0-1185) {NAME FRAME:not#5 TYPE NOT PAR 0-818 XREFS 7244 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-995 {}} {259 0 0-1184 {}}} SUCCS {{258 0 0-1188 {}}} CYCLES {}}
+set a(0-1186) {NAME FRAME:slc(acc.imod) TYPE READSLICE PAR 0-818 XREFS 7245 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-995 {}} {258 0 0-1058 {}}} SUCCS {{259 0 0-1187 {}}} CYCLES {}}
+set a(0-1187) {NAME FRAME:not#4 TYPE NOT PAR 0-818 XREFS 7246 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-995 {}} {259 0 0-1186 {}}} SUCCS {{259 0 0-1188 {}}} CYCLES {}}
+set a(0-1188) {NAME FRAME:conc#33 TYPE CONCATENATE PAR 0-818 XREFS 7247 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-995 {}} {258 0 0-1185 {}} {259 0 0-1187 {}}} SUCCS {{259 0 0-1189 {}}} CYCLES {}}
+set a(0-1189) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#42 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 7248 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 1 0.899096709496936 2 0.6320467844969361} PREDS {{146 0 0-995 {}} {258 0 0-1183 {}} {259 0 0-1188 {}}} SUCCS {{259 0 0-1190 {}}} CYCLES {}}
+set a(0-1190) {NAME FRAME:slc#7 TYPE READSLICE PAR 0-818 XREFS 7249 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-995 {}} {259 0 0-1189 {}}} SUCCS {{259 0 0-1191 {}}} CYCLES {}}
+set a(0-1191) {NAME FRAME:slc#2 TYPE READSLICE PAR 0-818 XREFS 7250 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-995 {}} {259 0 0-1190 {}}} SUCCS {{259 0 0-1192 {}}} CYCLES {}}
+set a(0-1192) {NAME FRAME:not#8 TYPE NOT PAR 0-818 XREFS 7251 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-995 {}} {259 0 0-1191 {}}} SUCCS {{259 0 0-1193 {}}} CYCLES {}}
+set a(0-1193) {NAME FRAME:conc#3 TYPE CONCATENATE PAR 0-818 XREFS 7252 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-995 {}} {258 0 0-1181 {}} {259 0 0-1192 {}}} SUCCS {{258 0 0-1195 {}}} CYCLES {}}
+set a(0-1194) {NAME FRAME:slc(acc.imod)#5 TYPE READSLICE PAR 0-818 XREFS 7253 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.632046825} PREDS {{146 0 0-995 {}} {258 0 0-1058 {}}} SUCCS {{259 0 0-1195 {}}} CYCLES {}}
+set a(0-1195) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#36 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-818 XREFS 7254 LOC {1 0.8777839249999999 1 0.89909675 1 0.89909675 1 0.9466528770708271 2 0.6796029520708271} PREDS {{146 0 0-995 {}} {258 0 0-1193 {}} {259 0 0-1194 {}}} SUCCS {{258 0 0-1198 {}}} CYCLES {}}
+set a(0-1196) {NAME red:slc(red#2.sg1)#9 TYPE READSLICE PAR 0-818 XREFS 7255 LOC {1 0.596016025 1 0.6173288499999999 1 0.6173288499999999 2 0.679603} PREDS {{146 0 0-995 {}} {258 0 0-1010 {}}} SUCCS {{259 0 0-1197 {}}} CYCLES {}}
+set a(0-1197) {NAME FRAME:not#6 TYPE NOT PAR 0-818 XREFS 7256 LOC {1 0.596016025 1 0.946652925 1 0.946652925 2 0.679603} PREDS {{146 0 0-995 {}} {259 0 0-1196 {}}} SUCCS {{259 0 0-1198 {}}} CYCLES {}}
+set a(0-1198) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#37 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-818 XREFS 7257 LOC {1 0.9253401 1 0.946652925 1 0.946652925 1 0.9999999451789505 2 0.7329500201789505} PREDS {{146 0 0-995 {}} {258 0 0-1195 {}} {259 0 0-1197 {}}} SUCCS {{258 0 0-1201 {}}} CYCLES {}}
+set a(0-1199) {NAME FRAME:slc(acc.imod)#4 TYPE READSLICE PAR 0-818 XREFS 7258 LOC {1 0.819184175 1 0.8404969999999999 1 0.8404969999999999 2 0.732950075} PREDS {{146 0 0-995 {}} {258 0 0-1058 {}}} SUCCS {{259 0 0-1200 {}}} CYCLES {}}
+set a(0-1200) {NAME FRAME:conc#30 TYPE CONCATENATE PAR 0-818 XREFS 7259 LOC {1 0.819184175 2 0.732950075 2 0.732950075 2 0.732950075} PREDS {{146 0 0-995 {}} {259 0 0-1199 {}}} SUCCS {{259 0 0-1201 {}}} CYCLES {}}
+set a(0-1201) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#38 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-818 XREFS 7260 LOC {2 0.0 2 0.732950075 2 0.732950075 2 0.791549784496936 2 0.791549784496936} PREDS {{146 0 0-995 {}} {258 0 0-1198 {}} {259 0 0-1200 {}}} SUCCS {{259 0 0-1202 {}}} CYCLES {}}
+set a(0-1202) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#39 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-818 XREFS 7261 LOC {2 0.05859975 2 0.7915498249999999 2 0.7915498249999999 2 0.8348897907468814 2 0.8348897907468814} PREDS {{146 0 0-995 {}} {258 0 0-1179 {}} {259 0 0-1201 {}}} SUCCS {{259 0 0-1203 {}}} CYCLES {}}
+set a(0-1203) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#40 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-818 XREFS 7262 LOC {2 0.101939775 2 0.8348898499999999 2 0.8348898499999999 2 0.9019182068650199 2 0.9019182068650199} PREDS {{146 0 0-995 {}} {258 0 0-1178 {}} {259 0 0-1202 {}}} SUCCS {{259 0 0-1204 {}}} CYCLES {}}
+set a(0-1204) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,10) AREA_SCORE 11.24 QUANTITY 1 NAME FRAME:acc#2 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-818 XREFS 7263 LOC {2 0.168968175 2 0.9019182499999999 2 0.9019182499999999 2 0.9832574783364112 2 0.9832574783364112} PREDS {{146 0 0-995 {}} {258 0 0-1176 {}} {259 0 0-1203 {}}} SUCCS {{258 0 0-1207 {}}} CYCLES {}}
+set a(0-1205) {NAME green:slc(green) TYPE READSLICE PAR 0-818 XREFS 7264 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-995 {}} {258 0 0-1113 {}}} SUCCS {{259 0 0-1206 {}}} CYCLES {}}
+set a(0-1206) {NAME FRAME:exu TYPE PADZEROES PAR 0-818 XREFS 7265 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-995 {}} {259 0 0-1205 {}}} SUCCS {{259 0 0-1207 {}}} CYCLES {}}
+set a(0-1207) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(10,2) AREA_SCORE 7.30 QUANTITY 1 NAME FRAME:or TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-818 XREFS 7266 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{146 0 0-995 {}} {258 0 0-1204 {}} {259 0 0-1206 {}}} SUCCS {{258 0 0-1214 {}}} CYCLES {}}
+set a(0-1208) {NAME green:slc(green)#1 TYPE READSLICE PAR 0-818 XREFS 7267 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 1.0} PREDS {{146 0 0-995 {}} {258 0 0-1113 {}}} SUCCS {{258 0 0-1214 {}}} CYCLES {}}
+set a(0-1209) {NAME green:slc(green)#2 TYPE READSLICE PAR 0-818 XREFS 7268 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-995 {}} {258 0 0-1113 {}}} SUCCS {{258 0 0-1212 {}}} CYCLES {}}
+set a(0-1210) {NAME blue:slc(blue) TYPE READSLICE PAR 0-818 XREFS 7269 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-995 {}} {258 0 0-1168 {}}} SUCCS {{259 0 0-1211 {}}} CYCLES {}}
+set a(0-1211) {NAME FRAME:exu#10 TYPE PADZEROES PAR 0-818 XREFS 7270 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-995 {}} {259 0 0-1210 {}}} SUCCS {{259 0 0-1212 {}}} CYCLES {}}
+set a(0-1212) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(6,2) AREA_SCORE 4.38 QUANTITY 1 NAME FRAME:or#3 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-818 XREFS 7271 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{146 0 0-995 {}} {258 0 0-1209 {}} {259 0 0-1211 {}}} SUCCS {{258 0 0-1214 {}}} CYCLES {}}
+set a(0-1213) {NAME blue:slc(blue)#1 TYPE READSLICE PAR 0-818 XREFS 7272 LOC {2 0.32393374999999996 2 0.983257525 2 0.983257525 2 1.0} PREDS {{146 0 0-995 {}} {258 0 0-1168 {}}} SUCCS {{259 0 0-1214 {}}} CYCLES {}}
+set a(0-1214) {NAME FRAME:conc#21 TYPE CONCATENATE PAR 0-818 XREFS 7273 LOC {2 0.340676225 2 1.0 2 1.0 2 1.0} PREDS {{146 0 0-995 {}} {258 0 0-1212 {}} {258 0 0-1208 {}} {258 0 0-1207 {}} {259 0 0-1213 {}}} SUCCS {{259 0 0-1215 {}}} CYCLES {}}
+set a(0-1215) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(2,30) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_write(vout:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-818 XREFS 7274 LOC {2 1.0 2 1.0 2 1.0 3 0.0 2 0.9999} PREDS {{130 0 0-995 {}} {260 0 0-1215 {}} {259 0 0-1214 {}}} SUCCS {{260 0 0-1215 {}}} CYCLES {}}
+set a(0-1216) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(19,0,2,1,19) AREA_SCORE 20.00 QUANTITY 1 NAME FRAME:acc#6 TYPE ACCU DELAY {1.91 ns} LIBRARY_DELAY {1.91 ns} PAR 0-818 XREFS 7275 LOC {1 0.10474599999999999 1 0.784864825 1 0.784864825 1 0.9041241410815966 2 0.5236100160815965} PREDS {{146 0 0-995 {}} {258 0 0-833 {}}} SUCCS {{259 0 0-1217 {}} {258 0 0-1236 {}}} CYCLES {}}
+set a(0-1217) {NAME FRAME:p:slc(FRAME:p)#1 TYPE READSLICE PAR 0-818 XREFS 7276 LOC {1 0.22400537499999998 1 0.9041241999999999 1 0.9041241999999999 2 0.523610075} PREDS {{146 0 0-995 {}} {259 0 0-1216 {}}} SUCCS {{259 0 0-1218 {}}} CYCLES {}}
+set a(0-1218) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,7,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME FRAME:acc TYPE ACCU DELAY {1.17 ns} LIBRARY_DELAY {1.17 ns} PAR 0-818 XREFS 7277 LOC {1 0.22400537499999998 1 0.9041241999999999 1 0.9041241999999999 1 0.9769393617915235 2 0.5964252367915236} PREDS {{146 0 0-995 {}} {259 0 0-1217 {}}} SUCCS {{259 0 0-1219 {}}} CYCLES {}}
+set a(0-1219) {NAME FRAME:slc TYPE READSLICE PAR 0-818 XREFS 7278 LOC {1 0.296820575 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {{146 0 0-995 {}} {259 0 0-1218 {}}} SUCCS {{259 0 0-1220 {}}} CYCLES {}}
+set a(0-1220) {NAME FRAME:not TYPE NOT PAR 0-818 XREFS 7279 LOC {1 0.296820575 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {{146 0 0-995 {}} {259 0 0-1219 {}}} SUCCS {{258 0 0-1223 {}} {258 0 0-1224 {}}} CYCLES {}}
+set a(0-1221) {NAME not#1 TYPE NOT PAR 0-818 XREFS 7280 LOC {1 0.0 1 0.0 1 0.0 2 0.596425275} PREDS {{258 0 0-835 {}}} SUCCS {{259 0 0-1222 {}}} CYCLES {}}
+set a(0-1222) {NAME FRAME:for:and#2 TYPE AND PAR 0-818 XREFS 7281 LOC {1 0.0 1 0.0 1 0.0 2 0.596425275} PREDS {{262 0 0-1238 {}} {259 0 0-1221 {}}} SUCCS {{259 0 0-1223 {}} {256 0 0-1238 {}}} CYCLES {}}
+set a(0-1223) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 2 NAME FRAME:for:mux#23 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-818 XREFS 7282 LOC {1 0.296820575 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.6194858375} PREDS {{258 0 0-994 {}} {258 0 0-1220 {}} {258 0 0-819 {}} {259 0 0-1222 {}}} SUCCS {{258 0 0-1238 {}} {258 0 0-1240 {}}} CYCLES {}}
+set a(0-1224) {NAME not#2 TYPE NOT PAR 0-818 XREFS 7283 LOC {1 0.296820575 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {{258 0 0-1220 {}} {258 0 0-819 {}}} SUCCS {{259 0 0-1225 {}}} CYCLES {}}
+set a(0-1225) {NAME FRAME:for:or#1 TYPE OR PAR 0-818 XREFS 7284 LOC {1 0.296820575 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {{258 0 0-994 {}} {259 0 0-1224 {}}} SUCCS {{259 0 0-1226 {}}} CYCLES {}}
+set a(0-1226) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 2 NAME FRAME:for:mux#24 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-818 XREFS 7285 LOC {1 0.296820575 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.6194858375} PREDS {{258 0 0-994 {}} {259 0 0-1225 {}}} SUCCS {{258 0 0-1239 {}} {258 0 0-1240 {}}} CYCLES {}}
+set a(0-1227) {NAME FRAME:for:asn(regs.regs(0).sva) TYPE ASSIGN PAR 0-818 XREFS 7286 LOC {1 0.0230606 1 0.044373425 1 0.044373425 2 0.619485875} PREDS {{260 0 0-1227 {}} {256 0 0-892 {}} {256 0 0-894 {}} {258 0 0-893 {}}} SUCCS {{262 0 0-892 {}} {262 0 0-894 {}} {260 0 0-1227 {}}} CYCLES {}}
+set a(0-1228) {NAME FRAME:for:asn(regs.regs(1).sva) TYPE ASSIGN PAR 0-818 XREFS 7287 LOC {1 0.0230606 1 0.044373425 1 0.044373425 2 0.619485875} PREDS {{260 0 0-1228 {}} {256 0 0-841 {}} {256 0 0-850 {}} {256 0 0-859 {}} {256 0 0-868 {}} {256 0 0-877 {}} {256 0 0-886 {}} {256 0 0-895 {}} {256 0 0-897 {}} {258 0 0-896 {}}} SUCCS {{262 0 0-841 {}} {262 0 0-850 {}} {262 0 0-859 {}} {262 0 0-868 {}} {262 0 0-877 {}} {262 0 0-886 {}} {262 0 0-895 {}} {262 0 0-897 {}} {260 0 0-1228 {}}} CYCLES {}}
+set a(0-1229) {NAME FRAME:for:asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-818 XREFS 7288 LOC {1 0.0230606 1 0.044373425 1 0.044373425 2 0.619485875} PREDS {{260 0 0-1229 {}} {258 0 0-898 {}}} SUCCS {{262 0 0-898 {}} {260 0 0-1229 {}}} CYCLES {}}
+set a(0-1230) {NAME FRAME:for:asn(r(0).lpi#1) TYPE ASSIGN PAR 0-818 XREFS 7289 LOC {1 0.380514125 1 0.511719075 1 0.511719075 3 0.11560675} PREDS {{260 0 0-1230 {}} {256 0 0-917 {}} {258 0 0-924 {}}} SUCCS {{262 0 0-917 {}} {260 0 0-1230 {}}} CYCLES {}}
+set a(0-1231) {NAME FRAME:for:asn(r(2).lpi#1) TYPE ASSIGN PAR 0-818 XREFS 7290 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 3 0.005714625} PREDS {{260 0 0-1231 {}} {256 0 0-964 {}} {258 0 0-970 {}}} SUCCS {{262 0 0-964 {}} {260 0 0-1231 {}}} CYCLES {}}
+set a(0-1232) {NAME FRAME:for:asn(g(0).lpi#1) TYPE ASSIGN PAR 0-818 XREFS 7291 LOC {1 0.380514125 1 0.511719075 1 0.511719075 3 0.041980449999999996} PREDS {{260 0 0-1232 {}} {256 0 0-927 {}} {258 0 0-934 {}}} SUCCS {{262 0 0-927 {}} {260 0 0-1232 {}}} CYCLES {}}
+set a(0-1233) {NAME FRAME:for:asn(g(2).lpi#1) TYPE ASSIGN PAR 0-818 XREFS 7292 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 2 0.8709376} PREDS {{260 0 0-1233 {}} {256 0 0-973 {}} {258 0 0-979 {}}} SUCCS {{262 0 0-973 {}} {260 0 0-1233 {}}} CYCLES {}}
+set a(0-1234) {NAME FRAME:for:asn(b(0).lpi#1) TYPE ASSIGN PAR 0-818 XREFS 7293 LOC {1 0.380514125 1 0.511719075 1 0.511719075 3 0.041980449999999996} PREDS {{260 0 0-1234 {}} {256 0 0-937 {}} {258 0 0-944 {}}} SUCCS {{262 0 0-937 {}} {260 0 0-1234 {}}} CYCLES {}}
+set a(0-1235) {NAME FRAME:for:asn(b(2).lpi#1) TYPE ASSIGN PAR 0-818 XREFS 7294 LOC {1 0.380514125 1 0.40182694999999996 1 0.40182694999999996 2 0.8709376} PREDS {{260 0 0-1235 {}} {256 0 0-982 {}} {258 0 0-988 {}}} SUCCS {{262 0 0-982 {}} {260 0 0-1235 {}}} CYCLES {}}
+set a(0-1236) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(19,1,2) AREA_SCORE 17.47 QUANTITY 1 NAME FRAME:for:mux#19 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-818 XREFS 7295 LOC {1 0.22400537499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.3879438875} PREDS {{260 0 0-1236 {}} {258 0 0-994 {}} {258 0 0-833 {}} {258 0 0-1216 {}} {258 0 0-820 {}}} SUCCS {{262 0 0-833 {}} {260 0 0-1236 {}}} CYCLES {}}
+set a(0-1237) {NAME FRAME:for:asn(i#6.lpi#1) TYPE ASSIGN PAR 0-818 XREFS 7296 LOC {1 0.057189825 1 0.274782525 1 0.274782525 2 0.6261397} PREDS {{260 0 0-1237 {}} {256 0 0-901 {}} {258 0 0-989 {}}} SUCCS {{262 0 0-901 {}} {260 0 0-1237 {}}} CYCLES {}}
+set a(0-1238) {NAME FRAME:for:asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-818 XREFS 7297 LOC {1 0.31988117499999996 1 1.0 1 1.0 3 0.596425275} PREDS {{260 0 0-1238 {}} {256 0 0-1222 {}} {258 0 0-1223 {}}} SUCCS {{262 0 0-1222 {}} {260 0 0-1238 {}}} CYCLES {}}
+set a(0-1239) {NAME FRAME:for:asn(exit:FRAME:for.lpi#1) TYPE ASSIGN PAR 0-818 XREFS 7298 LOC {1 0.31988117499999996 1 1.0 1 1.0 2 0.619485875} PREDS {{260 0 0-1239 {}} {256 0 0-835 {}} {258 0 0-1226 {}}} SUCCS {{262 0 0-835 {}} {260 0 0-1239 {}}} CYCLES {}}
+set a(0-1240) {NAME FRAME:and TYPE AND PAR 0-818 XREFS 7299 LOC {1 0.31988117499999996 1 1.0 1 1.0 2 0.619485875} PREDS {{258 0 0-1223 {}} {258 0 0-1226 {}}} SUCCS {{259 0 0-1241 {}}} CYCLES {}}
+set a(0-1241) {NAME FRAME:asn#3 TYPE ASSIGN PAR 0-818 XREFS 7300 LOC {1 0.31988117499999996 1 1.0 1 1.0 2 0.619485875} PREDS {{260 0 0-1241 {}} {256 0 0-828 {}} {256 0 0-830 {}} {256 0 0-834 {}} {259 0 0-1240 {}}} SUCCS {{262 0 0-828 {}} {262 0 0-830 {}} {262 0 0-834 {}} {260 0 0-1241 {}}} CYCLES {}}
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+set a(0-803) {CHI {0-804 0-805 0-806 0-807 0-808 0-809 0-810 0-811 0-812 0-813 0-814 0-815 0-816 0-817 0-818} ITERATIONS Infinite LATENCY 921601 RESET_LATENCY 0 CSTEPS 0 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 921600 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 0 TOTAL_CYCLES_IN 0 TOTAL_CYCLES_UNDER 921602 TOTAL_CYCLES 921602 NAME core:rlp TYPE LOOP DELAY {18432060.00 ns} PAR {} XREFS 7302 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-803-TOTALCYCLES) {921602}
+set a(0-803-QMOD) {mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2) 0-833 mgc_ioport.mgc_in_wire(1,90) 0-837 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12) {0-844 0-853 0-862 0-871 0-880 0-889} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2) {0-893 0-896 0-898} mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2) {0-901 0-956} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2) {0-917 0-927 0-937 0-964 0-973 0-982} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4) {0-921 0-931 0-941 0-968 0-977 0-986} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12) {0-923 0-933 0-943 0-969 0-978 0-987} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16) {0-924 0-934 0-944 0-970 0-979 0-988} mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(2,2) 0-961 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2) 0-989 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) 0-992 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) {0-1004 0-1019 0-1034 0-1113 0-1168} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(17,0,13,1,17) {0-1007 0-1022 0-1037} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16) {0-1009 0-1024 0-1039} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4) {0-1044 0-1051 0-1056 0-1062 0-1069 0-1074 0-1097 0-1117 0-1124 0-1129 0-1152 0-1195} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5) {0-1052 0-1070 0-1100 0-1125 0-1155 0-1198} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6) {0-1057 0-1075 0-1130} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6) {0-1058 0-1076 0-1131} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11) {0-1078 0-1133 0-1170} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9) {0-1080 0-1135 0-1178} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5) {0-1091 0-1103 0-1146 0-1158 0-1189 0-1201} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8) {0-1104 0-1159 0-1202} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10) {0-1105 0-1160 0-1203} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12) {0-1106 0-1161} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,9,1,10) 0-1176 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,10) 0-1204 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2) 0-1207 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2) 0-1212 mgc_ioport.mgc_out_stdreg(2,30) 0-1215 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19) 0-1216 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,7,0,8) 0-1218 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2) {0-1223 0-1226} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2) 0-1236}
+set a(0-803-PROC_NAME) {core}
+set a(0-803-HIER_NAME) {/sobel/core}
+set a(TOP) {0-803}
+
diff --git a/Sobel/sobel.v3/schematic.nlv b/Sobel/sobel.v3/schematic.nlv
new file mode 100644
index 0000000..768d436
--- /dev/null
+++ b/Sobel/sobel.v3/schematic.nlv
@@ -0,0 +1,10448 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "sobel:core" "orig"
+load port {clk} input -attr xrf 8280 -attr oid 1 -attr vt d -attr @path {/sobel/sobel:core/clk}
+load port {en} input -attr xrf 8281 -attr oid 2 -attr vt d -attr @path {/sobel/sobel:core/en}
+load port {arst_n} input -attr xrf 8282 -attr oid 3 -attr vt d -attr @path {/sobel/sobel:core/arst_n}
+load portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} -attr xrf 8283 -attr oid 4 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} -attr xrf 8284 -attr oid 5 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load symbol "add(5,-1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,-1,10,-1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,10)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,6)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(5:0)} input 6 {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(5:0)} input 6 {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nand(2,1)" "INTERFACE" NAND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,30)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(29:0)} input 30 {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(29:0)} input 30 {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(30,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(29:0)} input 30 {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(29:0)} input 30 {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,1,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "reg(2,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(1:0)} input 2 {D(1)} {D(0)} \
+     portBus {DRa(1:0)} input 2 {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(6,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(5:0)} input 6 {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(5:0)} input 6 {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,6,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(9,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(8:0)} input 9 {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(8:0)} input 9 {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "not(3)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(5,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(4:0)} input 5 {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(4:0)} input 5 {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(1,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(0:0)} input 1 {D(0)} \
+     portBus {DRa(0:0)} input 1 {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mul(2,0,9,0,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(11,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(10:0)} input 11 {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(10:0)} input 11 {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "reg(90,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(89:0)} input 90 {D(89)} {D(88)} {D(87)} {D(86)} {D(85)} {D(84)} {D(83)} {D(82)} {D(81)} {D(80)} {D(79)} {D(78)} {D(77)} {D(76)} {D(75)} {D(74)} {D(73)} {D(72)} {D(71)} {D(70)} {D(69)} {D(68)} {D(67)} {D(66)} {D(65)} {D(64)} {D(63)} {D(62)} {D(61)} {D(60)} {D(59)} {D(58)} {D(57)} {D(56)} {D(55)} {D(54)} {D(53)} {D(52)} {D(51)} {D(50)} {D(49)} {D(48)} {D(47)} {D(46)} {D(45)} {D(44)} {D(43)} {D(42)} {D(41)} {D(40)} {D(39)} {D(38)} {D(37)} {D(36)} {D(35)} {D(34)} {D(33)} {D(32)} {D(31)} {D(30)} {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(89:0)} input 90 {DRa(89)} {DRa(88)} {DRa(87)} {DRa(86)} {DRa(85)} {DRa(84)} {DRa(83)} {DRa(82)} {DRa(81)} {DRa(80)} {DRa(79)} {DRa(78)} {DRa(77)} {DRa(76)} {DRa(75)} {DRa(74)} {DRa(73)} {DRa(72)} {DRa(71)} {DRa(70)} {DRa(69)} {DRa(68)} {DRa(67)} {DRa(66)} {DRa(65)} {DRa(64)} {DRa(63)} {DRa(62)} {DRa(61)} {DRa(60)} {DRa(59)} {DRa(58)} {DRa(57)} {DRa(56)} {DRa(55)} {DRa(54)} {DRa(53)} {DRa(52)} {DRa(51)} {DRa(50)} {DRa(49)} {DRa(48)} {DRa(47)} {DRa(46)} {DRa(45)} {DRa(44)} {DRa(43)} {DRa(42)} {DRa(41)} {DRa(40)} {DRa(39)} {DRa(38)} {DRa(37)} {DRa(36)} {DRa(35)} {DRa(34)} {DRa(33)} {DRa(32)} {DRa(31)} {DRa(30)} {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(16,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(15:0)} input 16 {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(15:0)} input 16 {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,19)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(19,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(18:0)} input 19 {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(18:0)} input 19 {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,0,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,-1,11,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "and(2,2)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(1:0)} input 2 {A0(1)} {A0(0)} \
+     portBus {A1(1:0)} input 2 {A1(1)} {A1(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "or(2,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,90)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(89:0)} input 90 {A0(89)} {A0(88)} {A0(87)} {A0(86)} {A0(85)} {A0(84)} {A0(83)} {A0(82)} {A0(81)} {A0(80)} {A0(79)} {A0(78)} {A0(77)} {A0(76)} {A0(75)} {A0(74)} {A0(73)} {A0(72)} {A0(71)} {A0(70)} {A0(69)} {A0(68)} {A0(67)} {A0(66)} {A0(65)} {A0(64)} {A0(63)} {A0(62)} {A0(61)} {A0(60)} {A0(59)} {A0(58)} {A0(57)} {A0(56)} {A0(55)} {A0(54)} {A0(53)} {A0(52)} {A0(51)} {A0(50)} {A0(49)} {A0(48)} {A0(47)} {A0(46)} {A0(45)} {A0(44)} {A0(43)} {A0(42)} {A0(41)} {A0(40)} {A0(39)} {A0(38)} {A0(37)} {A0(36)} {A0(35)} {A0(34)} {A0(33)} {A0(32)} {A0(31)} {A0(30)} {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(89:0)} input 90 {A1(89)} {A1(88)} {A1(87)} {A1(86)} {A1(85)} {A1(84)} {A1(83)} {A1(82)} {A1(81)} {A1(80)} {A1(79)} {A1(78)} {A1(77)} {A1(76)} {A1(75)} {A1(74)} {A1(73)} {A1(72)} {A1(71)} {A1(70)} {A1(69)} {A1(68)} {A1(67)} {A1(66)} {A1(65)} {A1(64)} {A1(63)} {A1(62)} {A1(61)} {A1(60)} {A1(59)} {A1(58)} {A1(57)} {A1(56)} {A1(55)} {A1(54)} {A1(53)} {A1(52)} {A1(51)} {A1(50)} {A1(49)} {A1(48)} {A1(47)} {A1(46)} {A1(45)} {A1(44)} {A1(43)} {A1(42)} {A1(41)} {A1(40)} {A1(39)} {A1(38)} {A1(37)} {A1(36)} {A1(35)} {A1(34)} {A1(33)} {A1(32)} {A1(31)} {A1(30)} {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,8,-1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,1)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(19,-1,1,0,19)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(18:0)} input 19 {A(18)} {A(17)} {A(16)} {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,19)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,-1,6,-1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(10)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,11,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,15,-1,15)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(14:0)} input 15 {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,16,-1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,10)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,16)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(15:0)} input 16 {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(15:0)} input 16 {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(4,10)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {A2(9:0)} input 10 {A2(9)} {A2(8)} {A2(7)} {A2(6)} {A2(5)} {A2(4)} {A2(3)} {A2(2)} {A2(1)} {A2(0)} \
+     portBus {A3(9:0)} input 10 {A3(9)} {A3(8)} {A3(7)} {A3(6)} {A3(5)} {A3(4)} {A3(3)} {A3(2)} {A3(1)} {A3(0)} \
+     portBus {S(1:0)} input.top 2 {S(1)} {S(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,11,1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,12)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,12,1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nor(2,1)" "INTERFACE" NOR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "or(3,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load net {FRAME:p#1.lpi#1(0)} -attr vt d
+load net {FRAME:p#1.lpi#1(1)} -attr vt d
+load net {FRAME:p#1.lpi#1(2)} -attr vt d
+load net {FRAME:p#1.lpi#1(3)} -attr vt d
+load net {FRAME:p#1.lpi#1(4)} -attr vt d
+load net {FRAME:p#1.lpi#1(5)} -attr vt d
+load net {FRAME:p#1.lpi#1(6)} -attr vt d
+load net {FRAME:p#1.lpi#1(7)} -attr vt d
+load net {FRAME:p#1.lpi#1(8)} -attr vt d
+load net {FRAME:p#1.lpi#1(9)} -attr vt d
+load net {FRAME:p#1.lpi#1(10)} -attr vt d
+load net {FRAME:p#1.lpi#1(11)} -attr vt d
+load net {FRAME:p#1.lpi#1(12)} -attr vt d
+load net {FRAME:p#1.lpi#1(13)} -attr vt d
+load net {FRAME:p#1.lpi#1(14)} -attr vt d
+load net {FRAME:p#1.lpi#1(15)} -attr vt d
+load net {FRAME:p#1.lpi#1(16)} -attr vt d
+load net {FRAME:p#1.lpi#1(17)} -attr vt d
+load net {FRAME:p#1.lpi#1(18)} -attr vt d
+load netBundle {FRAME:p#1.lpi#1} 19 {FRAME:p#1.lpi#1(0)} {FRAME:p#1.lpi#1(1)} {FRAME:p#1.lpi#1(2)} {FRAME:p#1.lpi#1(3)} {FRAME:p#1.lpi#1(4)} {FRAME:p#1.lpi#1(5)} {FRAME:p#1.lpi#1(6)} {FRAME:p#1.lpi#1(7)} {FRAME:p#1.lpi#1(8)} {FRAME:p#1.lpi#1(9)} {FRAME:p#1.lpi#1(10)} {FRAME:p#1.lpi#1(11)} {FRAME:p#1.lpi#1(12)} {FRAME:p#1.lpi#1(13)} {FRAME:p#1.lpi#1(14)} {FRAME:p#1.lpi#1(15)} {FRAME:p#1.lpi#1(16)} {FRAME:p#1.lpi#1(17)} {FRAME:p#1.lpi#1(18)} -attr xrf 8285 -attr oid 6 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {regs.regs(1).sva(0)} -attr vt d
+load net {regs.regs(1).sva(1)} -attr vt d
+load net {regs.regs(1).sva(2)} -attr vt d
+load net {regs.regs(1).sva(3)} -attr vt d
+load net {regs.regs(1).sva(4)} -attr vt d
+load net {regs.regs(1).sva(5)} -attr vt d
+load net {regs.regs(1).sva(6)} -attr vt d
+load net {regs.regs(1).sva(7)} -attr vt d
+load net {regs.regs(1).sva(8)} -attr vt d
+load net {regs.regs(1).sva(9)} -attr vt d
+load net {regs.regs(1).sva(10)} -attr vt d
+load net {regs.regs(1).sva(11)} -attr vt d
+load net {regs.regs(1).sva(12)} -attr vt d
+load net {regs.regs(1).sva(13)} -attr vt d
+load net {regs.regs(1).sva(14)} -attr vt d
+load net {regs.regs(1).sva(15)} -attr vt d
+load net {regs.regs(1).sva(16)} -attr vt d
+load net {regs.regs(1).sva(17)} -attr vt d
+load net {regs.regs(1).sva(18)} -attr vt d
+load net {regs.regs(1).sva(19)} -attr vt d
+load net {regs.regs(1).sva(20)} -attr vt d
+load net {regs.regs(1).sva(21)} -attr vt d
+load net {regs.regs(1).sva(22)} -attr vt d
+load net {regs.regs(1).sva(23)} -attr vt d
+load net {regs.regs(1).sva(24)} -attr vt d
+load net {regs.regs(1).sva(25)} -attr vt d
+load net {regs.regs(1).sva(26)} -attr vt d
+load net {regs.regs(1).sva(27)} -attr vt d
+load net {regs.regs(1).sva(28)} -attr vt d
+load net {regs.regs(1).sva(29)} -attr vt d
+load net {regs.regs(1).sva(30)} -attr vt d
+load net {regs.regs(1).sva(31)} -attr vt d
+load net {regs.regs(1).sva(32)} -attr vt d
+load net {regs.regs(1).sva(33)} -attr vt d
+load net {regs.regs(1).sva(34)} -attr vt d
+load net {regs.regs(1).sva(35)} -attr vt d
+load net {regs.regs(1).sva(36)} -attr vt d
+load net {regs.regs(1).sva(37)} -attr vt d
+load net {regs.regs(1).sva(38)} -attr vt d
+load net {regs.regs(1).sva(39)} -attr vt d
+load net {regs.regs(1).sva(40)} -attr vt d
+load net {regs.regs(1).sva(41)} -attr vt d
+load net {regs.regs(1).sva(42)} -attr vt d
+load net {regs.regs(1).sva(43)} -attr vt d
+load net {regs.regs(1).sva(44)} -attr vt d
+load net {regs.regs(1).sva(45)} -attr vt d
+load net {regs.regs(1).sva(46)} -attr vt d
+load net {regs.regs(1).sva(47)} -attr vt d
+load net {regs.regs(1).sva(48)} -attr vt d
+load net {regs.regs(1).sva(49)} -attr vt d
+load net {regs.regs(1).sva(50)} -attr vt d
+load net {regs.regs(1).sva(51)} -attr vt d
+load net {regs.regs(1).sva(52)} -attr vt d
+load net {regs.regs(1).sva(53)} -attr vt d
+load net {regs.regs(1).sva(54)} -attr vt d
+load net {regs.regs(1).sva(55)} -attr vt d
+load net {regs.regs(1).sva(56)} -attr vt d
+load net {regs.regs(1).sva(57)} -attr vt d
+load net {regs.regs(1).sva(58)} -attr vt d
+load net {regs.regs(1).sva(59)} -attr vt d
+load net {regs.regs(1).sva(60)} -attr vt d
+load net {regs.regs(1).sva(61)} -attr vt d
+load net {regs.regs(1).sva(62)} -attr vt d
+load net {regs.regs(1).sva(63)} -attr vt d
+load net {regs.regs(1).sva(64)} -attr vt d
+load net {regs.regs(1).sva(65)} -attr vt d
+load net {regs.regs(1).sva(66)} -attr vt d
+load net {regs.regs(1).sva(67)} -attr vt d
+load net {regs.regs(1).sva(68)} -attr vt d
+load net {regs.regs(1).sva(69)} -attr vt d
+load net {regs.regs(1).sva(70)} -attr vt d
+load net {regs.regs(1).sva(71)} -attr vt d
+load net {regs.regs(1).sva(72)} -attr vt d
+load net {regs.regs(1).sva(73)} -attr vt d
+load net {regs.regs(1).sva(74)} -attr vt d
+load net {regs.regs(1).sva(75)} -attr vt d
+load net {regs.regs(1).sva(76)} -attr vt d
+load net {regs.regs(1).sva(77)} -attr vt d
+load net {regs.regs(1).sva(78)} -attr vt d
+load net {regs.regs(1).sva(79)} -attr vt d
+load net {regs.regs(1).sva(80)} -attr vt d
+load net {regs.regs(1).sva(81)} -attr vt d
+load net {regs.regs(1).sva(82)} -attr vt d
+load net {regs.regs(1).sva(83)} -attr vt d
+load net {regs.regs(1).sva(84)} -attr vt d
+load net {regs.regs(1).sva(85)} -attr vt d
+load net {regs.regs(1).sva(86)} -attr vt d
+load net {regs.regs(1).sva(87)} -attr vt d
+load net {regs.regs(1).sva(88)} -attr vt d
+load net {regs.regs(1).sva(89)} -attr vt d
+load netBundle {regs.regs(1).sva} 90 {regs.regs(1).sva(0)} {regs.regs(1).sva(1)} {regs.regs(1).sva(2)} {regs.regs(1).sva(3)} {regs.regs(1).sva(4)} {regs.regs(1).sva(5)} {regs.regs(1).sva(6)} {regs.regs(1).sva(7)} {regs.regs(1).sva(8)} {regs.regs(1).sva(9)} {regs.regs(1).sva(10)} {regs.regs(1).sva(11)} {regs.regs(1).sva(12)} {regs.regs(1).sva(13)} {regs.regs(1).sva(14)} {regs.regs(1).sva(15)} {regs.regs(1).sva(16)} {regs.regs(1).sva(17)} {regs.regs(1).sva(18)} {regs.regs(1).sva(19)} {regs.regs(1).sva(20)} {regs.regs(1).sva(21)} {regs.regs(1).sva(22)} {regs.regs(1).sva(23)} {regs.regs(1).sva(24)} {regs.regs(1).sva(25)} {regs.regs(1).sva(26)} {regs.regs(1).sva(27)} {regs.regs(1).sva(28)} {regs.regs(1).sva(29)} {regs.regs(1).sva(30)} {regs.regs(1).sva(31)} {regs.regs(1).sva(32)} {regs.regs(1).sva(33)} {regs.regs(1).sva(34)} {regs.regs(1).sva(35)} {regs.regs(1).sva(36)} {regs.regs(1).sva(37)} {regs.regs(1).sva(38)} {regs.regs(1).sva(39)} {regs.regs(1).sva(40)} {regs.regs(1).sva(41)} {regs.regs(1).sva(42)} {regs.regs(1).sva(43)} {regs.regs(1).sva(44)} {regs.regs(1).sva(45)} {regs.regs(1).sva(46)} {regs.regs(1).sva(47)} {regs.regs(1).sva(48)} {regs.regs(1).sva(49)} {regs.regs(1).sva(50)} {regs.regs(1).sva(51)} {regs.regs(1).sva(52)} {regs.regs(1).sva(53)} {regs.regs(1).sva(54)} {regs.regs(1).sva(55)} {regs.regs(1).sva(56)} {regs.regs(1).sva(57)} {regs.regs(1).sva(58)} {regs.regs(1).sva(59)} {regs.regs(1).sva(60)} {regs.regs(1).sva(61)} {regs.regs(1).sva(62)} {regs.regs(1).sva(63)} {regs.regs(1).sva(64)} {regs.regs(1).sva(65)} {regs.regs(1).sva(66)} {regs.regs(1).sva(67)} {regs.regs(1).sva(68)} {regs.regs(1).sva(69)} {regs.regs(1).sva(70)} {regs.regs(1).sva(71)} {regs.regs(1).sva(72)} {regs.regs(1).sva(73)} {regs.regs(1).sva(74)} {regs.regs(1).sva(75)} {regs.regs(1).sva(76)} {regs.regs(1).sva(77)} {regs.regs(1).sva(78)} {regs.regs(1).sva(79)} {regs.regs(1).sva(80)} {regs.regs(1).sva(81)} {regs.regs(1).sva(82)} {regs.regs(1).sva(83)} {regs.regs(1).sva(84)} {regs.regs(1).sva(85)} {regs.regs(1).sva(86)} {regs.regs(1).sva(87)} {regs.regs(1).sva(88)} {regs.regs(1).sva(89)} -attr xrf 8286 -attr oid 7 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -attr vt d
+load net {regs.regs(0).sva(1)} -attr vt d
+load net {regs.regs(0).sva(2)} -attr vt d
+load net {regs.regs(0).sva(3)} -attr vt d
+load net {regs.regs(0).sva(4)} -attr vt d
+load net {regs.regs(0).sva(5)} -attr vt d
+load net {regs.regs(0).sva(6)} -attr vt d
+load net {regs.regs(0).sva(7)} -attr vt d
+load net {regs.regs(0).sva(8)} -attr vt d
+load net {regs.regs(0).sva(9)} -attr vt d
+load net {regs.regs(0).sva(10)} -attr vt d
+load net {regs.regs(0).sva(11)} -attr vt d
+load net {regs.regs(0).sva(12)} -attr vt d
+load net {regs.regs(0).sva(13)} -attr vt d
+load net {regs.regs(0).sva(14)} -attr vt d
+load net {regs.regs(0).sva(15)} -attr vt d
+load net {regs.regs(0).sva(16)} -attr vt d
+load net {regs.regs(0).sva(17)} -attr vt d
+load net {regs.regs(0).sva(18)} -attr vt d
+load net {regs.regs(0).sva(19)} -attr vt d
+load net {regs.regs(0).sva(20)} -attr vt d
+load net {regs.regs(0).sva(21)} -attr vt d
+load net {regs.regs(0).sva(22)} -attr vt d
+load net {regs.regs(0).sva(23)} -attr vt d
+load net {regs.regs(0).sva(24)} -attr vt d
+load net {regs.regs(0).sva(25)} -attr vt d
+load net {regs.regs(0).sva(26)} -attr vt d
+load net {regs.regs(0).sva(27)} -attr vt d
+load net {regs.regs(0).sva(28)} -attr vt d
+load net {regs.regs(0).sva(29)} -attr vt d
+load net {regs.regs(0).sva(30)} -attr vt d
+load net {regs.regs(0).sva(31)} -attr vt d
+load net {regs.regs(0).sva(32)} -attr vt d
+load net {regs.regs(0).sva(33)} -attr vt d
+load net {regs.regs(0).sva(34)} -attr vt d
+load net {regs.regs(0).sva(35)} -attr vt d
+load net {regs.regs(0).sva(36)} -attr vt d
+load net {regs.regs(0).sva(37)} -attr vt d
+load net {regs.regs(0).sva(38)} -attr vt d
+load net {regs.regs(0).sva(39)} -attr vt d
+load net {regs.regs(0).sva(40)} -attr vt d
+load net {regs.regs(0).sva(41)} -attr vt d
+load net {regs.regs(0).sva(42)} -attr vt d
+load net {regs.regs(0).sva(43)} -attr vt d
+load net {regs.regs(0).sva(44)} -attr vt d
+load net {regs.regs(0).sva(45)} -attr vt d
+load net {regs.regs(0).sva(46)} -attr vt d
+load net {regs.regs(0).sva(47)} -attr vt d
+load net {regs.regs(0).sva(48)} -attr vt d
+load net {regs.regs(0).sva(49)} -attr vt d
+load net {regs.regs(0).sva(50)} -attr vt d
+load net {regs.regs(0).sva(51)} -attr vt d
+load net {regs.regs(0).sva(52)} -attr vt d
+load net {regs.regs(0).sva(53)} -attr vt d
+load net {regs.regs(0).sva(54)} -attr vt d
+load net {regs.regs(0).sva(55)} -attr vt d
+load net {regs.regs(0).sva(56)} -attr vt d
+load net {regs.regs(0).sva(57)} -attr vt d
+load net {regs.regs(0).sva(58)} -attr vt d
+load net {regs.regs(0).sva(59)} -attr vt d
+load net {regs.regs(0).sva(60)} -attr vt d
+load net {regs.regs(0).sva(61)} -attr vt d
+load net {regs.regs(0).sva(62)} -attr vt d
+load net {regs.regs(0).sva(63)} -attr vt d
+load net {regs.regs(0).sva(64)} -attr vt d
+load net {regs.regs(0).sva(65)} -attr vt d
+load net {regs.regs(0).sva(66)} -attr vt d
+load net {regs.regs(0).sva(67)} -attr vt d
+load net {regs.regs(0).sva(68)} -attr vt d
+load net {regs.regs(0).sva(69)} -attr vt d
+load net {regs.regs(0).sva(70)} -attr vt d
+load net {regs.regs(0).sva(71)} -attr vt d
+load net {regs.regs(0).sva(72)} -attr vt d
+load net {regs.regs(0).sva(73)} -attr vt d
+load net {regs.regs(0).sva(74)} -attr vt d
+load net {regs.regs(0).sva(75)} -attr vt d
+load net {regs.regs(0).sva(76)} -attr vt d
+load net {regs.regs(0).sva(77)} -attr vt d
+load net {regs.regs(0).sva(78)} -attr vt d
+load net {regs.regs(0).sva(79)} -attr vt d
+load net {regs.regs(0).sva(80)} -attr vt d
+load net {regs.regs(0).sva(81)} -attr vt d
+load net {regs.regs(0).sva(82)} -attr vt d
+load net {regs.regs(0).sva(83)} -attr vt d
+load net {regs.regs(0).sva(84)} -attr vt d
+load net {regs.regs(0).sva(85)} -attr vt d
+load net {regs.regs(0).sva(86)} -attr vt d
+load net {regs.regs(0).sva(87)} -attr vt d
+load net {regs.regs(0).sva(88)} -attr vt d
+load net {regs.regs(0).sva(89)} -attr vt d
+load netBundle {regs.regs(0).sva} 90 {regs.regs(0).sva(0)} {regs.regs(0).sva(1)} {regs.regs(0).sva(2)} {regs.regs(0).sva(3)} {regs.regs(0).sva(4)} {regs.regs(0).sva(5)} {regs.regs(0).sva(6)} {regs.regs(0).sva(7)} {regs.regs(0).sva(8)} {regs.regs(0).sva(9)} {regs.regs(0).sva(10)} {regs.regs(0).sva(11)} {regs.regs(0).sva(12)} {regs.regs(0).sva(13)} {regs.regs(0).sva(14)} {regs.regs(0).sva(15)} {regs.regs(0).sva(16)} {regs.regs(0).sva(17)} {regs.regs(0).sva(18)} {regs.regs(0).sva(19)} {regs.regs(0).sva(20)} {regs.regs(0).sva(21)} {regs.regs(0).sva(22)} {regs.regs(0).sva(23)} {regs.regs(0).sva(24)} {regs.regs(0).sva(25)} {regs.regs(0).sva(26)} {regs.regs(0).sva(27)} {regs.regs(0).sva(28)} {regs.regs(0).sva(29)} {regs.regs(0).sva(30)} {regs.regs(0).sva(31)} {regs.regs(0).sva(32)} {regs.regs(0).sva(33)} {regs.regs(0).sva(34)} {regs.regs(0).sva(35)} {regs.regs(0).sva(36)} {regs.regs(0).sva(37)} {regs.regs(0).sva(38)} {regs.regs(0).sva(39)} {regs.regs(0).sva(40)} {regs.regs(0).sva(41)} {regs.regs(0).sva(42)} {regs.regs(0).sva(43)} {regs.regs(0).sva(44)} {regs.regs(0).sva(45)} {regs.regs(0).sva(46)} {regs.regs(0).sva(47)} {regs.regs(0).sva(48)} {regs.regs(0).sva(49)} {regs.regs(0).sva(50)} {regs.regs(0).sva(51)} {regs.regs(0).sva(52)} {regs.regs(0).sva(53)} {regs.regs(0).sva(54)} {regs.regs(0).sva(55)} {regs.regs(0).sva(56)} {regs.regs(0).sva(57)} {regs.regs(0).sva(58)} {regs.regs(0).sva(59)} {regs.regs(0).sva(60)} {regs.regs(0).sva(61)} {regs.regs(0).sva(62)} {regs.regs(0).sva(63)} {regs.regs(0).sva(64)} {regs.regs(0).sva(65)} {regs.regs(0).sva(66)} {regs.regs(0).sva(67)} {regs.regs(0).sva(68)} {regs.regs(0).sva(69)} {regs.regs(0).sva(70)} {regs.regs(0).sva(71)} {regs.regs(0).sva(72)} {regs.regs(0).sva(73)} {regs.regs(0).sva(74)} {regs.regs(0).sva(75)} {regs.regs(0).sva(76)} {regs.regs(0).sva(77)} {regs.regs(0).sva(78)} {regs.regs(0).sva(79)} {regs.regs(0).sva(80)} {regs.regs(0).sva(81)} {regs.regs(0).sva(82)} {regs.regs(0).sva(83)} {regs.regs(0).sva(84)} {regs.regs(0).sva(85)} {regs.regs(0).sva(86)} {regs.regs(0).sva(87)} {regs.regs(0).sva(88)} {regs.regs(0).sva(89)} -attr xrf 8287 -attr oid 8 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(2).lpi#1.dfm(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(29)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(30)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(31)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(32)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(33)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(34)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(35)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(36)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(37)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(38)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(39)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(40)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(41)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(42)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(43)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(44)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(45)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(46)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(47)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(48)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(49)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(50)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(51)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(52)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(53)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(54)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(55)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(56)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(57)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(58)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(59)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(60)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(61)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(62)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(63)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(64)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(65)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(66)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(67)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(68)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(69)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(70)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(71)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(72)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(73)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(74)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(75)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(76)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(77)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(78)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(79)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(80)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(81)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(82)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(83)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(84)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(85)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(86)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(87)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(88)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(89)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm} 90 {regs.regs(2).lpi#1.dfm(0)} {regs.regs(2).lpi#1.dfm(1)} {regs.regs(2).lpi#1.dfm(2)} {regs.regs(2).lpi#1.dfm(3)} {regs.regs(2).lpi#1.dfm(4)} {regs.regs(2).lpi#1.dfm(5)} {regs.regs(2).lpi#1.dfm(6)} {regs.regs(2).lpi#1.dfm(7)} {regs.regs(2).lpi#1.dfm(8)} {regs.regs(2).lpi#1.dfm(9)} {regs.regs(2).lpi#1.dfm(10)} {regs.regs(2).lpi#1.dfm(11)} {regs.regs(2).lpi#1.dfm(12)} {regs.regs(2).lpi#1.dfm(13)} {regs.regs(2).lpi#1.dfm(14)} {regs.regs(2).lpi#1.dfm(15)} {regs.regs(2).lpi#1.dfm(16)} {regs.regs(2).lpi#1.dfm(17)} {regs.regs(2).lpi#1.dfm(18)} {regs.regs(2).lpi#1.dfm(19)} {regs.regs(2).lpi#1.dfm(20)} {regs.regs(2).lpi#1.dfm(21)} {regs.regs(2).lpi#1.dfm(22)} {regs.regs(2).lpi#1.dfm(23)} {regs.regs(2).lpi#1.dfm(24)} {regs.regs(2).lpi#1.dfm(25)} {regs.regs(2).lpi#1.dfm(26)} {regs.regs(2).lpi#1.dfm(27)} {regs.regs(2).lpi#1.dfm(28)} {regs.regs(2).lpi#1.dfm(29)} {regs.regs(2).lpi#1.dfm(30)} {regs.regs(2).lpi#1.dfm(31)} {regs.regs(2).lpi#1.dfm(32)} {regs.regs(2).lpi#1.dfm(33)} {regs.regs(2).lpi#1.dfm(34)} {regs.regs(2).lpi#1.dfm(35)} {regs.regs(2).lpi#1.dfm(36)} {regs.regs(2).lpi#1.dfm(37)} {regs.regs(2).lpi#1.dfm(38)} {regs.regs(2).lpi#1.dfm(39)} {regs.regs(2).lpi#1.dfm(40)} {regs.regs(2).lpi#1.dfm(41)} {regs.regs(2).lpi#1.dfm(42)} {regs.regs(2).lpi#1.dfm(43)} {regs.regs(2).lpi#1.dfm(44)} {regs.regs(2).lpi#1.dfm(45)} {regs.regs(2).lpi#1.dfm(46)} {regs.regs(2).lpi#1.dfm(47)} {regs.regs(2).lpi#1.dfm(48)} {regs.regs(2).lpi#1.dfm(49)} {regs.regs(2).lpi#1.dfm(50)} {regs.regs(2).lpi#1.dfm(51)} {regs.regs(2).lpi#1.dfm(52)} {regs.regs(2).lpi#1.dfm(53)} {regs.regs(2).lpi#1.dfm(54)} {regs.regs(2).lpi#1.dfm(55)} {regs.regs(2).lpi#1.dfm(56)} {regs.regs(2).lpi#1.dfm(57)} {regs.regs(2).lpi#1.dfm(58)} {regs.regs(2).lpi#1.dfm(59)} {regs.regs(2).lpi#1.dfm(60)} {regs.regs(2).lpi#1.dfm(61)} {regs.regs(2).lpi#1.dfm(62)} {regs.regs(2).lpi#1.dfm(63)} {regs.regs(2).lpi#1.dfm(64)} {regs.regs(2).lpi#1.dfm(65)} {regs.regs(2).lpi#1.dfm(66)} {regs.regs(2).lpi#1.dfm(67)} {regs.regs(2).lpi#1.dfm(68)} {regs.regs(2).lpi#1.dfm(69)} {regs.regs(2).lpi#1.dfm(70)} {regs.regs(2).lpi#1.dfm(71)} {regs.regs(2).lpi#1.dfm(72)} {regs.regs(2).lpi#1.dfm(73)} {regs.regs(2).lpi#1.dfm(74)} {regs.regs(2).lpi#1.dfm(75)} {regs.regs(2).lpi#1.dfm(76)} {regs.regs(2).lpi#1.dfm(77)} {regs.regs(2).lpi#1.dfm(78)} {regs.regs(2).lpi#1.dfm(79)} {regs.regs(2).lpi#1.dfm(80)} {regs.regs(2).lpi#1.dfm(81)} {regs.regs(2).lpi#1.dfm(82)} {regs.regs(2).lpi#1.dfm(83)} {regs.regs(2).lpi#1.dfm(84)} {regs.regs(2).lpi#1.dfm(85)} {regs.regs(2).lpi#1.dfm(86)} {regs.regs(2).lpi#1.dfm(87)} {regs.regs(2).lpi#1.dfm(88)} {regs.regs(2).lpi#1.dfm(89)} -attr xrf 8288 -attr oid 9 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {r(0).sva#1(0)} -attr vt d
+load net {r(0).sva#1(1)} -attr vt d
+load net {r(0).sva#1(2)} -attr vt d
+load net {r(0).sva#1(3)} -attr vt d
+load net {r(0).sva#1(4)} -attr vt d
+load net {r(0).sva#1(5)} -attr vt d
+load net {r(0).sva#1(6)} -attr vt d
+load net {r(0).sva#1(7)} -attr vt d
+load net {r(0).sva#1(8)} -attr vt d
+load net {r(0).sva#1(9)} -attr vt d
+load net {r(0).sva#1(10)} -attr vt d
+load net {r(0).sva#1(11)} -attr vt d
+load net {r(0).sva#1(12)} -attr vt d
+load net {r(0).sva#1(13)} -attr vt d
+load net {r(0).sva#1(14)} -attr vt d
+load net {r(0).sva#1(15)} -attr vt d
+load netBundle {r(0).sva#1} 16 {r(0).sva#1(0)} {r(0).sva#1(1)} {r(0).sva#1(2)} {r(0).sva#1(3)} {r(0).sva#1(4)} {r(0).sva#1(5)} {r(0).sva#1(6)} {r(0).sva#1(7)} {r(0).sva#1(8)} {r(0).sva#1(9)} {r(0).sva#1(10)} {r(0).sva#1(11)} {r(0).sva#1(12)} {r(0).sva#1(13)} {r(0).sva#1(14)} {r(0).sva#1(15)} -attr xrf 8289 -attr oid 10 -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {g(0).sva#1(0)} -attr vt d
+load net {g(0).sva#1(1)} -attr vt d
+load net {g(0).sva#1(2)} -attr vt d
+load net {g(0).sva#1(3)} -attr vt d
+load net {g(0).sva#1(4)} -attr vt d
+load net {g(0).sva#1(5)} -attr vt d
+load net {g(0).sva#1(6)} -attr vt d
+load net {g(0).sva#1(7)} -attr vt d
+load net {g(0).sva#1(8)} -attr vt d
+load net {g(0).sva#1(9)} -attr vt d
+load net {g(0).sva#1(10)} -attr vt d
+load net {g(0).sva#1(11)} -attr vt d
+load net {g(0).sva#1(12)} -attr vt d
+load net {g(0).sva#1(13)} -attr vt d
+load net {g(0).sva#1(14)} -attr vt d
+load net {g(0).sva#1(15)} -attr vt d
+load netBundle {g(0).sva#1} 16 {g(0).sva#1(0)} {g(0).sva#1(1)} {g(0).sva#1(2)} {g(0).sva#1(3)} {g(0).sva#1(4)} {g(0).sva#1(5)} {g(0).sva#1(6)} {g(0).sva#1(7)} {g(0).sva#1(8)} {g(0).sva#1(9)} {g(0).sva#1(10)} {g(0).sva#1(11)} {g(0).sva#1(12)} {g(0).sva#1(13)} {g(0).sva#1(14)} {g(0).sva#1(15)} -attr xrf 8290 -attr oid 11 -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {b(0).sva#1(0)} -attr vt d
+load net {b(0).sva#1(1)} -attr vt d
+load net {b(0).sva#1(2)} -attr vt d
+load net {b(0).sva#1(3)} -attr vt d
+load net {b(0).sva#1(4)} -attr vt d
+load net {b(0).sva#1(5)} -attr vt d
+load net {b(0).sva#1(6)} -attr vt d
+load net {b(0).sva#1(7)} -attr vt d
+load net {b(0).sva#1(8)} -attr vt d
+load net {b(0).sva#1(9)} -attr vt d
+load net {b(0).sva#1(10)} -attr vt d
+load net {b(0).sva#1(11)} -attr vt d
+load net {b(0).sva#1(12)} -attr vt d
+load net {b(0).sva#1(13)} -attr vt d
+load net {b(0).sva#1(14)} -attr vt d
+load net {b(0).sva#1(15)} -attr vt d
+load netBundle {b(0).sva#1} 16 {b(0).sva#1(0)} {b(0).sva#1(1)} {b(0).sva#1(2)} {b(0).sva#1(3)} {b(0).sva#1(4)} {b(0).sva#1(5)} {b(0).sva#1(6)} {b(0).sva#1(7)} {b(0).sva#1(8)} {b(0).sva#1(9)} {b(0).sva#1(10)} {b(0).sva#1(11)} {b(0).sva#1(12)} {b(0).sva#1(13)} {b(0).sva#1(14)} {b(0).sva#1(15)} -attr xrf 8291 -attr oid 12 -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {r(2).sva#1(0)} -attr vt d
+load net {r(2).sva#1(1)} -attr vt d
+load net {r(2).sva#1(2)} -attr vt d
+load net {r(2).sva#1(3)} -attr vt d
+load net {r(2).sva#1(4)} -attr vt d
+load net {r(2).sva#1(5)} -attr vt d
+load net {r(2).sva#1(6)} -attr vt d
+load net {r(2).sva#1(7)} -attr vt d
+load net {r(2).sva#1(8)} -attr vt d
+load net {r(2).sva#1(9)} -attr vt d
+load net {r(2).sva#1(10)} -attr vt d
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+load net {r(2).sva#1(12)} -attr vt d
+load net {r(2).sva#1(13)} -attr vt d
+load net {r(2).sva#1(14)} -attr vt d
+load net {r(2).sva#1(15)} -attr vt d
+load netBundle {r(2).sva#1} 16 {r(2).sva#1(0)} {r(2).sva#1(1)} {r(2).sva#1(2)} {r(2).sva#1(3)} {r(2).sva#1(4)} {r(2).sva#1(5)} {r(2).sva#1(6)} {r(2).sva#1(7)} {r(2).sva#1(8)} {r(2).sva#1(9)} {r(2).sva#1(10)} {r(2).sva#1(11)} {r(2).sva#1(12)} {r(2).sva#1(13)} {r(2).sva#1(14)} {r(2).sva#1(15)} -attr xrf 8292 -attr oid 13 -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {g(2).sva#1(0)} -attr vt d
+load net {g(2).sva#1(1)} -attr vt d
+load net {g(2).sva#1(2)} -attr vt d
+load net {g(2).sva#1(3)} -attr vt d
+load net {g(2).sva#1(4)} -attr vt d
+load net {g(2).sva#1(5)} -attr vt d
+load net {g(2).sva#1(6)} -attr vt d
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+load net {g(2).sva#1(8)} -attr vt d
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+load net {g(2).sva#1(13)} -attr vt d
+load net {g(2).sva#1(14)} -attr vt d
+load net {g(2).sva#1(15)} -attr vt d
+load netBundle {g(2).sva#1} 16 {g(2).sva#1(0)} {g(2).sva#1(1)} {g(2).sva#1(2)} {g(2).sva#1(3)} {g(2).sva#1(4)} {g(2).sva#1(5)} {g(2).sva#1(6)} {g(2).sva#1(7)} {g(2).sva#1(8)} {g(2).sva#1(9)} {g(2).sva#1(10)} {g(2).sva#1(11)} {g(2).sva#1(12)} {g(2).sva#1(13)} {g(2).sva#1(14)} {g(2).sva#1(15)} -attr xrf 8293 -attr oid 14 -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {b(2).sva#1(0)} -attr vt d
+load net {b(2).sva#1(1)} -attr vt d
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+load net {b(2).sva#1(5)} -attr vt d
+load net {b(2).sva#1(6)} -attr vt d
+load net {b(2).sva#1(7)} -attr vt d
+load net {b(2).sva#1(8)} -attr vt d
+load net {b(2).sva#1(9)} -attr vt d
+load net {b(2).sva#1(10)} -attr vt d
+load net {b(2).sva#1(11)} -attr vt d
+load net {b(2).sva#1(12)} -attr vt d
+load net {b(2).sva#1(13)} -attr vt d
+load net {b(2).sva#1(14)} -attr vt d
+load net {b(2).sva#1(15)} -attr vt d
+load netBundle {b(2).sva#1} 16 {b(2).sva#1(0)} {b(2).sva#1(1)} {b(2).sva#1(2)} {b(2).sva#1(3)} {b(2).sva#1(4)} {b(2).sva#1(5)} {b(2).sva#1(6)} {b(2).sva#1(7)} {b(2).sva#1(8)} {b(2).sva#1(9)} {b(2).sva#1(10)} {b(2).sva#1(11)} {b(2).sva#1(12)} {b(2).sva#1(13)} {b(2).sva#1(14)} {b(2).sva#1(15)} -attr xrf 8294 -attr oid 15 -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {i#6.sva#1(0)} -attr vt d
+load net {i#6.sva#1(1)} -attr vt d
+load netBundle {i#6.sva#1} 2 {i#6.sva#1(0)} {i#6.sva#1(1)} -attr xrf 8295 -attr oid 16 -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {FRAME:mul#2.itm#1(0)} -attr vt d
+load net {FRAME:mul#2.itm#1(1)} -attr vt d
+load net {FRAME:mul#2.itm#1(2)} -attr vt d
+load net {FRAME:mul#2.itm#1(3)} -attr vt d
+load net {FRAME:mul#2.itm#1(4)} -attr vt d
+load net {FRAME:mul#2.itm#1(5)} -attr vt d
+load net {FRAME:mul#2.itm#1(6)} -attr vt d
+load net {FRAME:mul#2.itm#1(7)} -attr vt d
+load net {FRAME:mul#2.itm#1(8)} -attr vt d
+load net {FRAME:mul#2.itm#1(9)} -attr vt d
+load net {FRAME:mul#2.itm#1(10)} -attr vt d
+load netBundle {FRAME:mul#2.itm#1} 11 {FRAME:mul#2.itm#1(0)} {FRAME:mul#2.itm#1(1)} {FRAME:mul#2.itm#1(2)} {FRAME:mul#2.itm#1(3)} {FRAME:mul#2.itm#1(4)} {FRAME:mul#2.itm#1(5)} {FRAME:mul#2.itm#1(6)} {FRAME:mul#2.itm#1(7)} {FRAME:mul#2.itm#1(8)} {FRAME:mul#2.itm#1(9)} {FRAME:mul#2.itm#1(10)} -attr xrf 8296 -attr oid 17 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#3.itm#1(0)} -attr vt d
+load net {FRAME:mul#3.itm#1(1)} -attr vt d
+load net {FRAME:mul#3.itm#1(2)} -attr vt d
+load net {FRAME:mul#3.itm#1(3)} -attr vt d
+load net {FRAME:mul#3.itm#1(4)} -attr vt d
+load net {FRAME:mul#3.itm#1(5)} -attr vt d
+load net {FRAME:mul#3.itm#1(6)} -attr vt d
+load net {FRAME:mul#3.itm#1(7)} -attr vt d
+load net {FRAME:mul#3.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#3.itm#1} 9 {FRAME:mul#3.itm#1(0)} {FRAME:mul#3.itm#1(1)} {FRAME:mul#3.itm#1(2)} {FRAME:mul#3.itm#1(3)} {FRAME:mul#3.itm#1(4)} {FRAME:mul#3.itm#1(5)} {FRAME:mul#3.itm#1(6)} {FRAME:mul#3.itm#1(7)} {FRAME:mul#3.itm#1(8)} -attr xrf 8297 -attr oid 18 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {green:slc(green#2.sg1).itm#1(0)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(1)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(2)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(3)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(4)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(5)} -attr vt d
+load netBundle {green:slc(green#2.sg1).itm#1} 6 {green:slc(green#2.sg1).itm#1(0)} {green:slc(green#2.sg1).itm#1(1)} {green:slc(green#2.sg1).itm#1(2)} {green:slc(green#2.sg1).itm#1(3)} {green:slc(green#2.sg1).itm#1(4)} {green:slc(green#2.sg1).itm#1(5)} -attr xrf 8298 -attr oid 19 -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {FRAME:acc#18.itm#1(0)} -attr vt d
+load net {FRAME:acc#18.itm#1(1)} -attr vt d
+load net {FRAME:acc#18.itm#1(2)} -attr vt d
+load net {FRAME:acc#18.itm#1(3)} -attr vt d
+load net {FRAME:acc#18.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#18.itm#1} 5 {FRAME:acc#18.itm#1(0)} {FRAME:acc#18.itm#1(1)} {FRAME:acc#18.itm#1(2)} {FRAME:acc#18.itm#1(3)} {FRAME:acc#18.itm#1(4)} -attr xrf 8299 -attr oid 20 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:mul#4.itm#1(0)} -attr vt d
+load net {FRAME:mul#4.itm#1(1)} -attr vt d
+load net {FRAME:mul#4.itm#1(2)} -attr vt d
+load net {FRAME:mul#4.itm#1(3)} -attr vt d
+load net {FRAME:mul#4.itm#1(4)} -attr vt d
+load net {FRAME:mul#4.itm#1(5)} -attr vt d
+load net {FRAME:mul#4.itm#1(6)} -attr vt d
+load net {FRAME:mul#4.itm#1(7)} -attr vt d
+load net {FRAME:mul#4.itm#1(8)} -attr vt d
+load net {FRAME:mul#4.itm#1(9)} -attr vt d
+load net {FRAME:mul#4.itm#1(10)} -attr vt d
+load netBundle {FRAME:mul#4.itm#1} 11 {FRAME:mul#4.itm#1(0)} {FRAME:mul#4.itm#1(1)} {FRAME:mul#4.itm#1(2)} {FRAME:mul#4.itm#1(3)} {FRAME:mul#4.itm#1(4)} {FRAME:mul#4.itm#1(5)} {FRAME:mul#4.itm#1(6)} {FRAME:mul#4.itm#1(7)} {FRAME:mul#4.itm#1(8)} {FRAME:mul#4.itm#1(9)} {FRAME:mul#4.itm#1(10)} -attr xrf 8300 -attr oid 21 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#5.itm#1(0)} -attr vt d
+load net {FRAME:mul#5.itm#1(1)} -attr vt d
+load net {FRAME:mul#5.itm#1(2)} -attr vt d
+load net {FRAME:mul#5.itm#1(3)} -attr vt d
+load net {FRAME:mul#5.itm#1(4)} -attr vt d
+load net {FRAME:mul#5.itm#1(5)} -attr vt d
+load net {FRAME:mul#5.itm#1(6)} -attr vt d
+load net {FRAME:mul#5.itm#1(7)} -attr vt d
+load net {FRAME:mul#5.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#5.itm#1} 9 {FRAME:mul#5.itm#1(0)} {FRAME:mul#5.itm#1(1)} {FRAME:mul#5.itm#1(2)} {FRAME:mul#5.itm#1(3)} {FRAME:mul#5.itm#1(4)} {FRAME:mul#5.itm#1(5)} {FRAME:mul#5.itm#1(6)} {FRAME:mul#5.itm#1(7)} {FRAME:mul#5.itm#1(8)} -attr xrf 8301 -attr oid 22 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(0)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(1)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(2)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(3)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(4)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(5)} -attr vt d
+load netBundle {blue:slc(blue#2.sg1).itm#1} 6 {blue:slc(blue#2.sg1).itm#1(0)} {blue:slc(blue#2.sg1).itm#1(1)} {blue:slc(blue#2.sg1).itm#1(2)} {blue:slc(blue#2.sg1).itm#1(3)} {blue:slc(blue#2.sg1).itm#1(4)} {blue:slc(blue#2.sg1).itm#1(5)} -attr xrf 8302 -attr oid 23 -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {FRAME:acc#30.itm#1(0)} -attr vt d
+load net {FRAME:acc#30.itm#1(1)} -attr vt d
+load net {FRAME:acc#30.itm#1(2)} -attr vt d
+load net {FRAME:acc#30.itm#1(3)} -attr vt d
+load net {FRAME:acc#30.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#30.itm#1} 5 {FRAME:acc#30.itm#1(0)} {FRAME:acc#30.itm#1(1)} {FRAME:acc#30.itm#1(2)} {FRAME:acc#30.itm#1(3)} {FRAME:acc#30.itm#1(4)} -attr xrf 8303 -attr oid 24 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:mul#1.itm#1(0)} -attr vt d
+load net {FRAME:mul#1.itm#1(1)} -attr vt d
+load net {FRAME:mul#1.itm#1(2)} -attr vt d
+load net {FRAME:mul#1.itm#1(3)} -attr vt d
+load net {FRAME:mul#1.itm#1(4)} -attr vt d
+load net {FRAME:mul#1.itm#1(5)} -attr vt d
+load net {FRAME:mul#1.itm#1(6)} -attr vt d
+load net {FRAME:mul#1.itm#1(7)} -attr vt d
+load net {FRAME:mul#1.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#1.itm#1} 9 {FRAME:mul#1.itm#1(0)} {FRAME:mul#1.itm#1(1)} {FRAME:mul#1.itm#1(2)} {FRAME:mul#1.itm#1(3)} {FRAME:mul#1.itm#1(4)} {FRAME:mul#1.itm#1(5)} {FRAME:mul#1.itm#1(6)} {FRAME:mul#1.itm#1(7)} {FRAME:mul#1.itm#1(8)} -attr xrf 8304 -attr oid 25 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {red:slc(red#2.sg1).itm#1(0)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(1)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(2)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(3)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(4)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(5)} -attr vt d
+load netBundle {red:slc(red#2.sg1).itm#1} 6 {red:slc(red#2.sg1).itm#1(0)} {red:slc(red#2.sg1).itm#1(1)} {red:slc(red#2.sg1).itm#1(2)} {red:slc(red#2.sg1).itm#1(3)} {red:slc(red#2.sg1).itm#1(4)} {red:slc(red#2.sg1).itm#1(5)} -attr xrf 8305 -attr oid 26 -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {FRAME:acc#37.itm#1(0)} -attr vt d
+load net {FRAME:acc#37.itm#1(1)} -attr vt d
+load net {FRAME:acc#37.itm#1(2)} -attr vt d
+load net {FRAME:acc#37.itm#1(3)} -attr vt d
+load net {FRAME:acc#37.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#37.itm#1} 5 {FRAME:acc#37.itm#1(0)} {FRAME:acc#37.itm#1(1)} {FRAME:acc#37.itm#1(2)} {FRAME:acc#37.itm#1(3)} {FRAME:acc#37.itm#1(4)} -attr xrf 8306 -attr oid 27 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#41.itm#1.sg2(0)} -attr vt d
+load net {FRAME:acc#41.itm#1.sg2(1)} -attr vt d
+load netBundle {FRAME:acc#41.itm#1.sg2} 2 {FRAME:acc#41.itm#1.sg2(0)} {FRAME:acc#41.itm#1.sg2(1)} -attr xrf 8307 -attr oid 28 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg2}
+load net {FRAME:acc#41.itm#1.sg1(0)} -attr vt d
+load net {FRAME:acc#41.itm#1.sg1(1)} -attr vt d
+load netBundle {FRAME:acc#41.itm#1.sg1} 2 {FRAME:acc#41.itm#1.sg1(0)} {FRAME:acc#41.itm#1.sg1(1)} -attr xrf 8308 -attr oid 29 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg1}
+load net {FRAME:acc#41.itm#3(0)} -attr vt d
+load net {FRAME:acc#41.itm#3(1)} -attr vt d
+load net {FRAME:acc#41.itm#3(2)} -attr vt d
+load net {FRAME:acc#41.itm#3(3)} -attr vt d
+load net {FRAME:acc#41.itm#3(4)} -attr vt d
+load net {FRAME:acc#41.itm#3(5)} -attr vt d
+load netBundle {FRAME:acc#41.itm#3} 6 {FRAME:acc#41.itm#3(0)} {FRAME:acc#41.itm#3(1)} {FRAME:acc#41.itm#3(2)} {FRAME:acc#41.itm#3(3)} {FRAME:acc#41.itm#3(4)} {FRAME:acc#41.itm#3(5)} -attr xrf 8309 -attr oid 30 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:p#1.sva#1(0)} -attr vt d
+load net {FRAME:p#1.sva#1(1)} -attr vt d
+load net {FRAME:p#1.sva#1(2)} -attr vt d
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+load net {FRAME:p#1.sva#1(6)} -attr vt d
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+load net {FRAME:p#1.sva#1(11)} -attr vt d
+load net {FRAME:p#1.sva#1(12)} -attr vt d
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+load net {FRAME:p#1.sva#1(16)} -attr vt d
+load net {FRAME:p#1.sva#1(17)} -attr vt d
+load net {FRAME:p#1.sva#1(18)} -attr vt d
+load netBundle {FRAME:p#1.sva#1} 19 {FRAME:p#1.sva#1(0)} {FRAME:p#1.sva#1(1)} {FRAME:p#1.sva#1(2)} {FRAME:p#1.sva#1(3)} {FRAME:p#1.sva#1(4)} {FRAME:p#1.sva#1(5)} {FRAME:p#1.sva#1(6)} {FRAME:p#1.sva#1(7)} {FRAME:p#1.sva#1(8)} {FRAME:p#1.sva#1(9)} {FRAME:p#1.sva#1(10)} {FRAME:p#1.sva#1(11)} {FRAME:p#1.sva#1(12)} {FRAME:p#1.sva#1(13)} {FRAME:p#1.sva#1(14)} {FRAME:p#1.sva#1(15)} {FRAME:p#1.sva#1(16)} {FRAME:p#1.sva#1(17)} {FRAME:p#1.sva#1(18)} -attr xrf 8310 -attr oid 31 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:acc#3.psp.sva(0)} -attr vt d
+load net {FRAME:acc#3.psp.sva(1)} -attr vt d
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+load net {FRAME:acc#3.psp.sva(10)} -attr vt d
+load net {FRAME:acc#3.psp.sva(11)} -attr vt d
+load netBundle {FRAME:acc#3.psp.sva} 12 {FRAME:acc#3.psp.sva(0)} {FRAME:acc#3.psp.sva(1)} {FRAME:acc#3.psp.sva(2)} {FRAME:acc#3.psp.sva(3)} {FRAME:acc#3.psp.sva(4)} {FRAME:acc#3.psp.sva(5)} {FRAME:acc#3.psp.sva(6)} {FRAME:acc#3.psp.sva(7)} {FRAME:acc#3.psp.sva(8)} {FRAME:acc#3.psp.sva(9)} {FRAME:acc#3.psp.sva(10)} {FRAME:acc#3.psp.sva(11)} -attr xrf 8311 -attr oid 32 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#4.psp.sva(0)} -attr vt d
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+load net {FRAME:acc#4.psp.sva(2)} -attr vt d
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+load net {FRAME:acc#4.psp.sva(5)} -attr vt d
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+load net {FRAME:acc#4.psp.sva(9)} -attr vt d
+load net {FRAME:acc#4.psp.sva(10)} -attr vt d
+load net {FRAME:acc#4.psp.sva(11)} -attr vt d
+load netBundle {FRAME:acc#4.psp.sva} 12 {FRAME:acc#4.psp.sva(0)} {FRAME:acc#4.psp.sva(1)} {FRAME:acc#4.psp.sva(2)} {FRAME:acc#4.psp.sva(3)} {FRAME:acc#4.psp.sva(4)} {FRAME:acc#4.psp.sva(5)} {FRAME:acc#4.psp.sva(6)} {FRAME:acc#4.psp.sva(7)} {FRAME:acc#4.psp.sva(8)} {FRAME:acc#4.psp.sva(9)} {FRAME:acc#4.psp.sva(10)} {FRAME:acc#4.psp.sva(11)} -attr xrf 8312 -attr oid 33 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {i#6.sva#2(0)} -attr vt d
+load net {i#6.sva#2(1)} -attr vt d
+load netBundle {i#6.sva#2} 2 {i#6.sva#2(0)} {i#6.sva#2(1)} -attr xrf 8313 -attr oid 34 -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.lpi#1.dfm(0)} -attr vt d
+load net {i#6.lpi#1.dfm(1)} -attr vt d
+load netBundle {i#6.lpi#1.dfm} 2 {i#6.lpi#1.dfm(0)} {i#6.lpi#1.dfm(1)} -attr xrf 8314 -attr oid 35 -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm:mx0} 90 {regs.regs(2).lpi#1.dfm:mx0(0)} {regs.regs(2).lpi#1.dfm:mx0(1)} {regs.regs(2).lpi#1.dfm:mx0(2)} {regs.regs(2).lpi#1.dfm:mx0(3)} {regs.regs(2).lpi#1.dfm:mx0(4)} {regs.regs(2).lpi#1.dfm:mx0(5)} {regs.regs(2).lpi#1.dfm:mx0(6)} {regs.regs(2).lpi#1.dfm:mx0(7)} {regs.regs(2).lpi#1.dfm:mx0(8)} {regs.regs(2).lpi#1.dfm:mx0(9)} {regs.regs(2).lpi#1.dfm:mx0(10)} {regs.regs(2).lpi#1.dfm:mx0(11)} {regs.regs(2).lpi#1.dfm:mx0(12)} {regs.regs(2).lpi#1.dfm:mx0(13)} {regs.regs(2).lpi#1.dfm:mx0(14)} {regs.regs(2).lpi#1.dfm:mx0(15)} {regs.regs(2).lpi#1.dfm:mx0(16)} {regs.regs(2).lpi#1.dfm:mx0(17)} {regs.regs(2).lpi#1.dfm:mx0(18)} {regs.regs(2).lpi#1.dfm:mx0(19)} {regs.regs(2).lpi#1.dfm:mx0(20)} {regs.regs(2).lpi#1.dfm:mx0(21)} {regs.regs(2).lpi#1.dfm:mx0(22)} {regs.regs(2).lpi#1.dfm:mx0(23)} {regs.regs(2).lpi#1.dfm:mx0(24)} {regs.regs(2).lpi#1.dfm:mx0(25)} {regs.regs(2).lpi#1.dfm:mx0(26)} {regs.regs(2).lpi#1.dfm:mx0(27)} {regs.regs(2).lpi#1.dfm:mx0(28)} {regs.regs(2).lpi#1.dfm:mx0(29)} {regs.regs(2).lpi#1.dfm:mx0(30)} {regs.regs(2).lpi#1.dfm:mx0(31)} {regs.regs(2).lpi#1.dfm:mx0(32)} {regs.regs(2).lpi#1.dfm:mx0(33)} {regs.regs(2).lpi#1.dfm:mx0(34)} {regs.regs(2).lpi#1.dfm:mx0(35)} {regs.regs(2).lpi#1.dfm:mx0(36)} {regs.regs(2).lpi#1.dfm:mx0(37)} {regs.regs(2).lpi#1.dfm:mx0(38)} {regs.regs(2).lpi#1.dfm:mx0(39)} {regs.regs(2).lpi#1.dfm:mx0(40)} {regs.regs(2).lpi#1.dfm:mx0(41)} {regs.regs(2).lpi#1.dfm:mx0(42)} {regs.regs(2).lpi#1.dfm:mx0(43)} {regs.regs(2).lpi#1.dfm:mx0(44)} {regs.regs(2).lpi#1.dfm:mx0(45)} {regs.regs(2).lpi#1.dfm:mx0(46)} {regs.regs(2).lpi#1.dfm:mx0(47)} {regs.regs(2).lpi#1.dfm:mx0(48)} {regs.regs(2).lpi#1.dfm:mx0(49)} {regs.regs(2).lpi#1.dfm:mx0(50)} {regs.regs(2).lpi#1.dfm:mx0(51)} {regs.regs(2).lpi#1.dfm:mx0(52)} {regs.regs(2).lpi#1.dfm:mx0(53)} {regs.regs(2).lpi#1.dfm:mx0(54)} {regs.regs(2).lpi#1.dfm:mx0(55)} {regs.regs(2).lpi#1.dfm:mx0(56)} {regs.regs(2).lpi#1.dfm:mx0(57)} {regs.regs(2).lpi#1.dfm:mx0(58)} {regs.regs(2).lpi#1.dfm:mx0(59)} {regs.regs(2).lpi#1.dfm:mx0(60)} {regs.regs(2).lpi#1.dfm:mx0(61)} {regs.regs(2).lpi#1.dfm:mx0(62)} {regs.regs(2).lpi#1.dfm:mx0(63)} {regs.regs(2).lpi#1.dfm:mx0(64)} {regs.regs(2).lpi#1.dfm:mx0(65)} {regs.regs(2).lpi#1.dfm:mx0(66)} {regs.regs(2).lpi#1.dfm:mx0(67)} {regs.regs(2).lpi#1.dfm:mx0(68)} {regs.regs(2).lpi#1.dfm:mx0(69)} {regs.regs(2).lpi#1.dfm:mx0(70)} {regs.regs(2).lpi#1.dfm:mx0(71)} {regs.regs(2).lpi#1.dfm:mx0(72)} {regs.regs(2).lpi#1.dfm:mx0(73)} {regs.regs(2).lpi#1.dfm:mx0(74)} {regs.regs(2).lpi#1.dfm:mx0(75)} {regs.regs(2).lpi#1.dfm:mx0(76)} {regs.regs(2).lpi#1.dfm:mx0(77)} {regs.regs(2).lpi#1.dfm:mx0(78)} {regs.regs(2).lpi#1.dfm:mx0(79)} {regs.regs(2).lpi#1.dfm:mx0(80)} {regs.regs(2).lpi#1.dfm:mx0(81)} {regs.regs(2).lpi#1.dfm:mx0(82)} {regs.regs(2).lpi#1.dfm:mx0(83)} {regs.regs(2).lpi#1.dfm:mx0(84)} {regs.regs(2).lpi#1.dfm:mx0(85)} {regs.regs(2).lpi#1.dfm:mx0(86)} {regs.regs(2).lpi#1.dfm:mx0(87)} {regs.regs(2).lpi#1.dfm:mx0(88)} {regs.regs(2).lpi#1.dfm:mx0(89)} -attr xrf 8315 -attr oid 36 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(1).sva.dfm:mx0} 90 {regs.regs(1).sva.dfm:mx0(0)} {regs.regs(1).sva.dfm:mx0(1)} {regs.regs(1).sva.dfm:mx0(2)} {regs.regs(1).sva.dfm:mx0(3)} {regs.regs(1).sva.dfm:mx0(4)} {regs.regs(1).sva.dfm:mx0(5)} {regs.regs(1).sva.dfm:mx0(6)} {regs.regs(1).sva.dfm:mx0(7)} {regs.regs(1).sva.dfm:mx0(8)} {regs.regs(1).sva.dfm:mx0(9)} {regs.regs(1).sva.dfm:mx0(10)} {regs.regs(1).sva.dfm:mx0(11)} {regs.regs(1).sva.dfm:mx0(12)} {regs.regs(1).sva.dfm:mx0(13)} {regs.regs(1).sva.dfm:mx0(14)} {regs.regs(1).sva.dfm:mx0(15)} {regs.regs(1).sva.dfm:mx0(16)} {regs.regs(1).sva.dfm:mx0(17)} {regs.regs(1).sva.dfm:mx0(18)} {regs.regs(1).sva.dfm:mx0(19)} {regs.regs(1).sva.dfm:mx0(20)} {regs.regs(1).sva.dfm:mx0(21)} {regs.regs(1).sva.dfm:mx0(22)} {regs.regs(1).sva.dfm:mx0(23)} {regs.regs(1).sva.dfm:mx0(24)} {regs.regs(1).sva.dfm:mx0(25)} {regs.regs(1).sva.dfm:mx0(26)} {regs.regs(1).sva.dfm:mx0(27)} {regs.regs(1).sva.dfm:mx0(28)} {regs.regs(1).sva.dfm:mx0(29)} {regs.regs(1).sva.dfm:mx0(30)} {regs.regs(1).sva.dfm:mx0(31)} {regs.regs(1).sva.dfm:mx0(32)} {regs.regs(1).sva.dfm:mx0(33)} {regs.regs(1).sva.dfm:mx0(34)} {regs.regs(1).sva.dfm:mx0(35)} {regs.regs(1).sva.dfm:mx0(36)} {regs.regs(1).sva.dfm:mx0(37)} {regs.regs(1).sva.dfm:mx0(38)} {regs.regs(1).sva.dfm:mx0(39)} {regs.regs(1).sva.dfm:mx0(40)} {regs.regs(1).sva.dfm:mx0(41)} {regs.regs(1).sva.dfm:mx0(42)} {regs.regs(1).sva.dfm:mx0(43)} {regs.regs(1).sva.dfm:mx0(44)} {regs.regs(1).sva.dfm:mx0(45)} {regs.regs(1).sva.dfm:mx0(46)} {regs.regs(1).sva.dfm:mx0(47)} {regs.regs(1).sva.dfm:mx0(48)} {regs.regs(1).sva.dfm:mx0(49)} {regs.regs(1).sva.dfm:mx0(50)} {regs.regs(1).sva.dfm:mx0(51)} {regs.regs(1).sva.dfm:mx0(52)} {regs.regs(1).sva.dfm:mx0(53)} {regs.regs(1).sva.dfm:mx0(54)} {regs.regs(1).sva.dfm:mx0(55)} {regs.regs(1).sva.dfm:mx0(56)} {regs.regs(1).sva.dfm:mx0(57)} {regs.regs(1).sva.dfm:mx0(58)} {regs.regs(1).sva.dfm:mx0(59)} {regs.regs(1).sva.dfm:mx0(60)} {regs.regs(1).sva.dfm:mx0(61)} {regs.regs(1).sva.dfm:mx0(62)} {regs.regs(1).sva.dfm:mx0(63)} {regs.regs(1).sva.dfm:mx0(64)} {regs.regs(1).sva.dfm:mx0(65)} {regs.regs(1).sva.dfm:mx0(66)} {regs.regs(1).sva.dfm:mx0(67)} {regs.regs(1).sva.dfm:mx0(68)} {regs.regs(1).sva.dfm:mx0(69)} {regs.regs(1).sva.dfm:mx0(70)} {regs.regs(1).sva.dfm:mx0(71)} {regs.regs(1).sva.dfm:mx0(72)} {regs.regs(1).sva.dfm:mx0(73)} {regs.regs(1).sva.dfm:mx0(74)} {regs.regs(1).sva.dfm:mx0(75)} {regs.regs(1).sva.dfm:mx0(76)} {regs.regs(1).sva.dfm:mx0(77)} {regs.regs(1).sva.dfm:mx0(78)} {regs.regs(1).sva.dfm:mx0(79)} {regs.regs(1).sva.dfm:mx0(80)} {regs.regs(1).sva.dfm:mx0(81)} {regs.regs(1).sva.dfm:mx0(82)} {regs.regs(1).sva.dfm:mx0(83)} {regs.regs(1).sva.dfm:mx0(84)} {regs.regs(1).sva.dfm:mx0(85)} {regs.regs(1).sva.dfm:mx0(86)} {regs.regs(1).sva.dfm:mx0(87)} {regs.regs(1).sva.dfm:mx0(88)} {regs.regs(1).sva.dfm:mx0(89)} -attr xrf 8316 -attr oid 37 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(0).sva.dfm:mx0} 90 {regs.regs(0).sva.dfm:mx0(0)} {regs.regs(0).sva.dfm:mx0(1)} {regs.regs(0).sva.dfm:mx0(2)} {regs.regs(0).sva.dfm:mx0(3)} {regs.regs(0).sva.dfm:mx0(4)} {regs.regs(0).sva.dfm:mx0(5)} {regs.regs(0).sva.dfm:mx0(6)} {regs.regs(0).sva.dfm:mx0(7)} {regs.regs(0).sva.dfm:mx0(8)} {regs.regs(0).sva.dfm:mx0(9)} {regs.regs(0).sva.dfm:mx0(10)} {regs.regs(0).sva.dfm:mx0(11)} {regs.regs(0).sva.dfm:mx0(12)} {regs.regs(0).sva.dfm:mx0(13)} {regs.regs(0).sva.dfm:mx0(14)} {regs.regs(0).sva.dfm:mx0(15)} {regs.regs(0).sva.dfm:mx0(16)} {regs.regs(0).sva.dfm:mx0(17)} {regs.regs(0).sva.dfm:mx0(18)} {regs.regs(0).sva.dfm:mx0(19)} {regs.regs(0).sva.dfm:mx0(20)} {regs.regs(0).sva.dfm:mx0(21)} {regs.regs(0).sva.dfm:mx0(22)} {regs.regs(0).sva.dfm:mx0(23)} {regs.regs(0).sva.dfm:mx0(24)} {regs.regs(0).sva.dfm:mx0(25)} {regs.regs(0).sva.dfm:mx0(26)} {regs.regs(0).sva.dfm:mx0(27)} {regs.regs(0).sva.dfm:mx0(28)} {regs.regs(0).sva.dfm:mx0(29)} {regs.regs(0).sva.dfm:mx0(30)} {regs.regs(0).sva.dfm:mx0(31)} {regs.regs(0).sva.dfm:mx0(32)} {regs.regs(0).sva.dfm:mx0(33)} {regs.regs(0).sva.dfm:mx0(34)} {regs.regs(0).sva.dfm:mx0(35)} {regs.regs(0).sva.dfm:mx0(36)} {regs.regs(0).sva.dfm:mx0(37)} {regs.regs(0).sva.dfm:mx0(38)} {regs.regs(0).sva.dfm:mx0(39)} {regs.regs(0).sva.dfm:mx0(40)} {regs.regs(0).sva.dfm:mx0(41)} {regs.regs(0).sva.dfm:mx0(42)} {regs.regs(0).sva.dfm:mx0(43)} {regs.regs(0).sva.dfm:mx0(44)} {regs.regs(0).sva.dfm:mx0(45)} {regs.regs(0).sva.dfm:mx0(46)} {regs.regs(0).sva.dfm:mx0(47)} {regs.regs(0).sva.dfm:mx0(48)} {regs.regs(0).sva.dfm:mx0(49)} {regs.regs(0).sva.dfm:mx0(50)} {regs.regs(0).sva.dfm:mx0(51)} {regs.regs(0).sva.dfm:mx0(52)} {regs.regs(0).sva.dfm:mx0(53)} {regs.regs(0).sva.dfm:mx0(54)} {regs.regs(0).sva.dfm:mx0(55)} {regs.regs(0).sva.dfm:mx0(56)} {regs.regs(0).sva.dfm:mx0(57)} {regs.regs(0).sva.dfm:mx0(58)} {regs.regs(0).sva.dfm:mx0(59)} {regs.regs(0).sva.dfm:mx0(60)} {regs.regs(0).sva.dfm:mx0(61)} {regs.regs(0).sva.dfm:mx0(62)} {regs.regs(0).sva.dfm:mx0(63)} {regs.regs(0).sva.dfm:mx0(64)} {regs.regs(0).sva.dfm:mx0(65)} {regs.regs(0).sva.dfm:mx0(66)} {regs.regs(0).sva.dfm:mx0(67)} {regs.regs(0).sva.dfm:mx0(68)} {regs.regs(0).sva.dfm:mx0(69)} {regs.regs(0).sva.dfm:mx0(70)} {regs.regs(0).sva.dfm:mx0(71)} {regs.regs(0).sva.dfm:mx0(72)} {regs.regs(0).sva.dfm:mx0(73)} {regs.regs(0).sva.dfm:mx0(74)} {regs.regs(0).sva.dfm:mx0(75)} {regs.regs(0).sva.dfm:mx0(76)} {regs.regs(0).sva.dfm:mx0(77)} {regs.regs(0).sva.dfm:mx0(78)} {regs.regs(0).sva.dfm:mx0(79)} {regs.regs(0).sva.dfm:mx0(80)} {regs.regs(0).sva.dfm:mx0(81)} {regs.regs(0).sva.dfm:mx0(82)} {regs.regs(0).sva.dfm:mx0(83)} {regs.regs(0).sva.dfm:mx0(84)} {regs.regs(0).sva.dfm:mx0(85)} {regs.regs(0).sva.dfm:mx0(86)} {regs.regs(0).sva.dfm:mx0(87)} {regs.regs(0).sva.dfm:mx0(88)} {regs.regs(0).sva.dfm:mx0(89)} -attr xrf 8317 -attr oid 38 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {FRAME:p#1.lpi#1.dfm(0)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(1)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(2)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(3)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(4)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(5)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(6)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(7)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(8)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(9)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(10)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(11)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(12)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(13)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(14)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(15)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(16)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(17)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(18)} -attr vt d
+load netBundle {FRAME:p#1.lpi#1.dfm} 19 {FRAME:p#1.lpi#1.dfm(0)} {FRAME:p#1.lpi#1.dfm(1)} {FRAME:p#1.lpi#1.dfm(2)} {FRAME:p#1.lpi#1.dfm(3)} {FRAME:p#1.lpi#1.dfm(4)} {FRAME:p#1.lpi#1.dfm(5)} {FRAME:p#1.lpi#1.dfm(6)} {FRAME:p#1.lpi#1.dfm(7)} {FRAME:p#1.lpi#1.dfm(8)} {FRAME:p#1.lpi#1.dfm(9)} {FRAME:p#1.lpi#1.dfm(10)} {FRAME:p#1.lpi#1.dfm(11)} {FRAME:p#1.lpi#1.dfm(12)} {FRAME:p#1.lpi#1.dfm(13)} {FRAME:p#1.lpi#1.dfm(14)} {FRAME:p#1.lpi#1.dfm(15)} {FRAME:p#1.lpi#1.dfm(16)} {FRAME:p#1.lpi#1.dfm(17)} {FRAME:p#1.lpi#1.dfm(18)} -attr xrf 8318 -attr oid 39 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {acc.imod.sva(0)} -attr vt d
+load net {acc.imod.sva(1)} -attr vt d
+load net {acc.imod.sva(2)} -attr vt d
+load net {acc.imod.sva(3)} -attr vt d
+load net {acc.imod.sva(4)} -attr vt d
+load net {acc.imod.sva(5)} -attr vt d
+load netBundle {acc.imod.sva} 6 {acc.imod.sva(0)} {acc.imod.sva(1)} {acc.imod.sva(2)} {acc.imod.sva(3)} {acc.imod.sva(4)} {acc.imod.sva(5)} -attr xrf 8319 -attr oid 40 -attr vt d -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {red#2.sg1.sva(0)} -attr vt d
+load net {red#2.sg1.sva(1)} -attr vt d
+load net {red#2.sg1.sva(2)} -attr vt d
+load net {red#2.sg1.sva(3)} -attr vt d
+load net {red#2.sg1.sva(4)} -attr vt d
+load net {red#2.sg1.sva(5)} -attr vt d
+load net {red#2.sg1.sva(6)} -attr vt d
+load net {red#2.sg1.sva(7)} -attr vt d
+load net {red#2.sg1.sva(8)} -attr vt d
+load net {red#2.sg1.sva(9)} -attr vt d
+load net {red#2.sg1.sva(10)} -attr vt d
+load net {red#2.sg1.sva(11)} -attr vt d
+load net {red#2.sg1.sva(12)} -attr vt d
+load net {red#2.sg1.sva(13)} -attr vt d
+load net {red#2.sg1.sva(14)} -attr vt d
+load netBundle {red#2.sg1.sva} 15 {red#2.sg1.sva(0)} {red#2.sg1.sva(1)} {red#2.sg1.sva(2)} {red#2.sg1.sva(3)} {red#2.sg1.sva(4)} {red#2.sg1.sva(5)} {red#2.sg1.sva(6)} {red#2.sg1.sva(7)} {red#2.sg1.sva(8)} {red#2.sg1.sva(9)} {red#2.sg1.sva(10)} {red#2.sg1.sva(11)} {red#2.sg1.sva(12)} {red#2.sg1.sva(13)} {red#2.sg1.sva(14)} -attr xrf 8320 -attr oid 41 -attr vt d -attr @path {/sobel/sobel:core/red#2.sg1.sva}
+load net {FRAME:mul.sdt(0)} -attr vt d
+load net {FRAME:mul.sdt(1)} -attr vt d
+load net {FRAME:mul.sdt(2)} -attr vt d
+load net {FRAME:mul.sdt(3)} -attr vt d
+load net {FRAME:mul.sdt(4)} -attr vt d
+load net {FRAME:mul.sdt(5)} -attr vt d
+load net {FRAME:mul.sdt(6)} -attr vt d
+load net {FRAME:mul.sdt(7)} -attr vt d
+load net {FRAME:mul.sdt(8)} -attr vt d
+load net {FRAME:mul.sdt(9)} -attr vt d
+load netBundle {FRAME:mul.sdt} 10 {FRAME:mul.sdt(0)} {FRAME:mul.sdt(1)} {FRAME:mul.sdt(2)} {FRAME:mul.sdt(3)} {FRAME:mul.sdt(4)} {FRAME:mul.sdt(5)} {FRAME:mul.sdt(6)} {FRAME:mul.sdt(7)} {FRAME:mul.sdt(8)} {FRAME:mul.sdt(9)} -attr xrf 8321 -attr oid 42 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {blue#2.sg1.sva(0)} -attr vt d
+load net {blue#2.sg1.sva(1)} -attr vt d
+load net {blue#2.sg1.sva(2)} -attr vt d
+load net {blue#2.sg1.sva(3)} -attr vt d
+load net {blue#2.sg1.sva(4)} -attr vt d
+load net {blue#2.sg1.sva(5)} -attr vt d
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+load net {FRAME:conc#36.itm(6)} -attr vt d
+load net {FRAME:conc#36.itm(7)} -attr vt d
+load net {FRAME:conc#36.itm(8)} -attr vt d
+load net {FRAME:conc#36.itm(9)} -attr vt d
+load netBundle {FRAME:conc#36.itm} 10 {FRAME:conc#36.itm(0)} {FRAME:conc#36.itm(1)} {FRAME:conc#36.itm(2)} {FRAME:conc#36.itm(3)} {FRAME:conc#36.itm(4)} {FRAME:conc#36.itm(5)} {FRAME:conc#36.itm(6)} {FRAME:conc#36.itm(7)} {FRAME:conc#36.itm(8)} {FRAME:conc#36.itm(9)} -attr xrf 8337 -attr oid 58 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#40.itm(0)} -attr vt d
+load net {FRAME:acc#40.itm(1)} -attr vt d
+load net {FRAME:acc#40.itm(2)} -attr vt d
+load net {FRAME:acc#40.itm(3)} -attr vt d
+load net {FRAME:acc#40.itm(4)} -attr vt d
+load net {FRAME:acc#40.itm(5)} -attr vt d
+load net {FRAME:acc#40.itm(6)} -attr vt d
+load net {FRAME:acc#40.itm(7)} -attr vt d
+load net {FRAME:acc#40.itm(8)} -attr vt d
+load net {FRAME:acc#40.itm(9)} -attr vt d
+load netBundle {FRAME:acc#40.itm} 10 {FRAME:acc#40.itm(0)} {FRAME:acc#40.itm(1)} {FRAME:acc#40.itm(2)} {FRAME:acc#40.itm(3)} {FRAME:acc#40.itm(4)} {FRAME:acc#40.itm(5)} {FRAME:acc#40.itm(6)} {FRAME:acc#40.itm(7)} {FRAME:acc#40.itm(8)} {FRAME:acc#40.itm(9)} -attr xrf 8338 -attr oid 59 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#39.itm(0)} -attr vt d
+load net {FRAME:acc#39.itm(1)} -attr vt d
+load net {FRAME:acc#39.itm(2)} -attr vt d
+load net {FRAME:acc#39.itm(3)} -attr vt d
+load net {FRAME:acc#39.itm(4)} -attr vt d
+load net {FRAME:acc#39.itm(5)} -attr vt d
+load net {FRAME:acc#39.itm(6)} -attr vt d
+load net {FRAME:acc#39.itm(7)} -attr vt d
+load netBundle {FRAME:acc#39.itm} 8 {FRAME:acc#39.itm(0)} {FRAME:acc#39.itm(1)} {FRAME:acc#39.itm(2)} {FRAME:acc#39.itm(3)} {FRAME:acc#39.itm(4)} {FRAME:acc#39.itm(5)} {FRAME:acc#39.itm(6)} {FRAME:acc#39.itm(7)} -attr xrf 8339 -attr oid 60 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#38.itm(0)} -attr vt d
+load net {FRAME:acc#38.itm(1)} -attr vt d
+load net {FRAME:acc#38.itm(2)} -attr vt d
+load net {FRAME:acc#38.itm(3)} -attr vt d
+load net {FRAME:acc#38.itm(4)} -attr vt d
+load netBundle {FRAME:acc#38.itm} 5 {FRAME:acc#38.itm(0)} {FRAME:acc#38.itm(1)} {FRAME:acc#38.itm(2)} {FRAME:acc#38.itm(3)} {FRAME:acc#38.itm(4)} -attr xrf 8340 -attr oid 61 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {conc#123.itm(0)} -attr vt d
+load net {conc#123.itm(1)} -attr vt d
+load net {conc#123.itm(2)} -attr vt d
+load net {conc#123.itm(3)} -attr vt d
+load net {conc#123.itm(4)} -attr vt d
+load netBundle {conc#123.itm} 5 {conc#123.itm(0)} {conc#123.itm(1)} {conc#123.itm(2)} {conc#123.itm(3)} {conc#123.itm(4)} -attr xrf 8341 -attr oid 62 -attr vt d -attr @path {/sobel/sobel:core/conc#123.itm}
+load net {conc#124.itm(0)} -attr vt d
+load net {conc#124.itm(1)} -attr vt d
+load net {conc#124.itm(2)} -attr vt d
+load net {conc#124.itm(3)} -attr vt d
+load net {conc#124.itm(4)} -attr vt d
+load net {conc#124.itm(5)} -attr vt d
+load net {conc#124.itm(6)} -attr vt d
+load net {conc#124.itm(7)} -attr vt d
+load net {conc#124.itm(8)} -attr vt d
+load net {conc#124.itm(9)} -attr vt d
+load netBundle {conc#124.itm} 10 {conc#124.itm(0)} {conc#124.itm(1)} {conc#124.itm(2)} {conc#124.itm(3)} {conc#124.itm(4)} {conc#124.itm(5)} {conc#124.itm(6)} {conc#124.itm(7)} {conc#124.itm(8)} {conc#124.itm(9)} -attr xrf 8342 -attr oid 63 -attr vt d -attr @path {/sobel/sobel:core/conc#124.itm}
+load net {slc(FRAME:acc#3.psp.sva).itm(0)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#3.psp.sva).itm} 2 {slc(FRAME:acc#3.psp.sva).itm(0)} {slc(FRAME:acc#3.psp.sva).itm(1)} -attr xrf 8343 -attr oid 64 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva).itm}
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(3)} -attr vt d
+load netBundle {slc(FRAME:acc#3.psp.sva)#1.itm} 4 {slc(FRAME:acc#3.psp.sva)#1.itm(0)} {slc(FRAME:acc#3.psp.sva)#1.itm(1)} {slc(FRAME:acc#3.psp.sva)#1.itm(2)} {slc(FRAME:acc#3.psp.sva)#1.itm(3)} -attr xrf 8344 -attr oid 65 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#1.itm}
+load net {FRAME:or#3.itm(0)} -attr vt d
+load net {FRAME:or#3.itm(1)} -attr vt d
+load net {FRAME:or#3.itm(2)} -attr vt d
+load net {FRAME:or#3.itm(3)} -attr vt d
+load net {FRAME:or#3.itm(4)} -attr vt d
+load net {FRAME:or#3.itm(5)} -attr vt d
+load netBundle {FRAME:or#3.itm} 6 {FRAME:or#3.itm(0)} {FRAME:or#3.itm(1)} {FRAME:or#3.itm(2)} {FRAME:or#3.itm(3)} {FRAME:or#3.itm(4)} {FRAME:or#3.itm(5)} -attr xrf 8345 -attr oid 66 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(2)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(3)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(4)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(FRAME:acc#3.psp.sva)#2.itm} 6 {slc(FRAME:acc#3.psp.sva)#2.itm(0)} {slc(FRAME:acc#3.psp.sva)#2.itm(1)} {slc(FRAME:acc#3.psp.sva)#2.itm(2)} {slc(FRAME:acc#3.psp.sva)#2.itm(3)} {slc(FRAME:acc#3.psp.sva)#2.itm(4)} {slc(FRAME:acc#3.psp.sva)#2.itm(5)} -attr xrf 8346 -attr oid 67 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {conc#125.itm(0)} -attr vt d
+load net {conc#125.itm(1)} -attr vt d
+load net {conc#125.itm(2)} -attr vt d
+load net {conc#125.itm(3)} -attr vt d
+load net {conc#125.itm(4)} -attr vt d
+load net {conc#125.itm(5)} -attr vt d
+load netBundle {conc#125.itm} 6 {conc#125.itm(0)} {conc#125.itm(1)} {conc#125.itm(2)} {conc#125.itm(3)} {conc#125.itm(4)} {conc#125.itm(5)} -attr xrf 8347 -attr oid 68 -attr vt d -attr @path {/sobel/sobel:core/conc#125.itm}
+load net {slc(FRAME:acc#4.psp.sva).itm(0)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#4.psp.sva).itm} 2 {slc(FRAME:acc#4.psp.sva).itm(0)} {slc(FRAME:acc#4.psp.sva).itm(1)} -attr xrf 8348 -attr oid 69 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#4.psp.sva).itm}
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(3)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(4)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(5)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(6)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(7)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(8)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(9)} -attr vt d
+load netBundle {slc(FRAME:acc#4.psp.sva)#1.itm} 10 {slc(FRAME:acc#4.psp.sva)#1.itm(0)} {slc(FRAME:acc#4.psp.sva)#1.itm(1)} {slc(FRAME:acc#4.psp.sva)#1.itm(2)} {slc(FRAME:acc#4.psp.sva)#1.itm(3)} {slc(FRAME:acc#4.psp.sva)#1.itm(4)} {slc(FRAME:acc#4.psp.sva)#1.itm(5)} {slc(FRAME:acc#4.psp.sva)#1.itm(6)} {slc(FRAME:acc#4.psp.sva)#1.itm(7)} {slc(FRAME:acc#4.psp.sva)#1.itm(8)} {slc(FRAME:acc#4.psp.sva)#1.itm(9)} -attr xrf 8349 -attr oid 70 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#4.psp.sva)#1.itm}
+load net {FRAME:acc#43.itm(0)} -attr vt d
+load net {FRAME:acc#43.itm(1)} -attr vt d
+load netBundle {FRAME:acc#43.itm} 2 {FRAME:acc#43.itm(0)} {FRAME:acc#43.itm(1)} -attr xrf 8350 -attr oid 71 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {slc(FRAME:mul.sdt).itm(0)} -attr vt d
+load net {slc(FRAME:mul.sdt).itm(1)} -attr vt d
+load netBundle {slc(FRAME:mul.sdt).itm} 2 {slc(FRAME:mul.sdt).itm(0)} {slc(FRAME:mul.sdt).itm(1)} -attr xrf 8351 -attr oid 72 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt).itm}
+load net {slc(FRAME:mul.sdt)#2.itm(0)} -attr vt d
+load net {slc(FRAME:mul.sdt)#2.itm(1)} -attr vt d
+load netBundle {slc(FRAME:mul.sdt)#2.itm} 2 {slc(FRAME:mul.sdt)#2.itm(0)} {slc(FRAME:mul.sdt)#2.itm(1)} -attr xrf 8352 -attr oid 73 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#2.itm}
+load net {FRAME:acc#44.itm(0)} -attr vt d
+load net {FRAME:acc#44.itm(1)} -attr vt d
+load net {FRAME:acc#44.itm(2)} -attr vt d
+load net {FRAME:acc#44.itm(3)} -attr vt d
+load net {FRAME:acc#44.itm(4)} -attr vt d
+load net {FRAME:acc#44.itm(5)} -attr vt d
+load netBundle {FRAME:acc#44.itm} 6 {FRAME:acc#44.itm(0)} {FRAME:acc#44.itm(1)} {FRAME:acc#44.itm(2)} {FRAME:acc#44.itm(3)} {FRAME:acc#44.itm(4)} {FRAME:acc#44.itm(5)} -attr xrf 8353 -attr oid 74 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {slc(FRAME:mul.sdt)#1.itm(0)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(1)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(2)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(3)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(4)} -attr vt d
+load netBundle {slc(FRAME:mul.sdt)#1.itm} 5 {slc(FRAME:mul.sdt)#1.itm(0)} {slc(FRAME:mul.sdt)#1.itm(1)} {slc(FRAME:mul.sdt)#1.itm(2)} {slc(FRAME:mul.sdt)#1.itm(3)} {slc(FRAME:mul.sdt)#1.itm(4)} -attr xrf 8354 -attr oid 75 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {exs.itm(0)} -attr vt d
+load net {exs.itm(1)} -attr vt d
+load net {exs.itm(2)} -attr vt d
+load net {exs.itm(3)} -attr vt d
+load net {exs.itm(4)} -attr vt d
+load netBundle {exs.itm} 5 {exs.itm(0)} {exs.itm(1)} {exs.itm(2)} {exs.itm(3)} {exs.itm(4)} -attr xrf 8355 -attr oid 76 -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {conc#126.itm(0)} -attr vt d
+load net {conc#126.itm(1)} -attr vt d
+load net {conc#126.itm(2)} -attr vt d
+load netBundle {conc#126.itm} 3 {conc#126.itm(0)} {conc#126.itm(1)} {conc#126.itm(2)} -attr xrf 8356 -attr oid 77 -attr vt d -attr @path {/sobel/sobel:core/conc#126.itm}
+load net {FRAME:mul#1.itm(0)} -attr vt d
+load net {FRAME:mul#1.itm(1)} -attr vt d
+load net {FRAME:mul#1.itm(2)} -attr vt d
+load net {FRAME:mul#1.itm(3)} -attr vt d
+load net {FRAME:mul#1.itm(4)} -attr vt d
+load net {FRAME:mul#1.itm(5)} -attr vt d
+load net {FRAME:mul#1.itm(6)} -attr vt d
+load net {FRAME:mul#1.itm(7)} -attr vt d
+load net {FRAME:mul#1.itm(8)} -attr vt d
+load netBundle {FRAME:mul#1.itm} 9 {FRAME:mul#1.itm(0)} {FRAME:mul#1.itm(1)} {FRAME:mul#1.itm(2)} {FRAME:mul#1.itm(3)} {FRAME:mul#1.itm(4)} {FRAME:mul#1.itm(5)} {FRAME:mul#1.itm(6)} {FRAME:mul#1.itm(7)} {FRAME:mul#1.itm(8)} -attr xrf 8357 -attr oid 78 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {slc(red#2.sg1.sva)#13.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#13.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#13.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#13.itm} 3 {slc(red#2.sg1.sva)#13.itm(0)} {slc(red#2.sg1.sva)#13.itm(1)} {slc(red#2.sg1.sva)#13.itm(2)} -attr xrf 8358 -attr oid 79 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {slc(red#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(2)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(3)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(4)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(5)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#1.itm} 6 {slc(red#2.sg1.sva)#1.itm(0)} {slc(red#2.sg1.sva)#1.itm(1)} {slc(red#2.sg1.sva)#1.itm(2)} {slc(red#2.sg1.sva)#1.itm(3)} {slc(red#2.sg1.sva)#1.itm(4)} {slc(red#2.sg1.sva)#1.itm(5)} -attr xrf 8359 -attr oid 80 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {FRAME:acc#37.itm(0)} -attr vt d
+load net {FRAME:acc#37.itm(1)} -attr vt d
+load net {FRAME:acc#37.itm(2)} -attr vt d
+load net {FRAME:acc#37.itm(3)} -attr vt d
+load net {FRAME:acc#37.itm(4)} -attr vt d
+load netBundle {FRAME:acc#37.itm} 5 {FRAME:acc#37.itm(0)} {FRAME:acc#37.itm(1)} {FRAME:acc#37.itm(2)} {FRAME:acc#37.itm(3)} {FRAME:acc#37.itm(4)} -attr xrf 8360 -attr oid 81 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#36.itm(0)} -attr vt d
+load net {FRAME:acc#36.itm(1)} -attr vt d
+load net {FRAME:acc#36.itm(2)} -attr vt d
+load net {FRAME:acc#36.itm(3)} -attr vt d
+load netBundle {FRAME:acc#36.itm} 4 {FRAME:acc#36.itm(0)} {FRAME:acc#36.itm(1)} {FRAME:acc#36.itm(2)} {FRAME:acc#36.itm(3)} -attr xrf 8361 -attr oid 82 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {conc#128.itm(0)} -attr vt d
+load net {conc#128.itm(1)} -attr vt d
+load net {conc#128.itm(2)} -attr vt d
+load netBundle {conc#128.itm} 3 {conc#128.itm(0)} {conc#128.itm(1)} {conc#128.itm(2)} -attr xrf 8362 -attr oid 83 -attr vt d -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {conc#129.itm(0)} -attr vt d
+load net {conc#129.itm(1)} -attr vt d
+load net {conc#129.itm(2)} -attr vt d
+load net {conc#129.itm(3)} -attr vt d
+load net {conc#129.itm(4)} -attr vt d
+load netBundle {conc#129.itm} 5 {conc#129.itm(0)} {conc#129.itm(1)} {conc#129.itm(2)} {conc#129.itm(3)} {conc#129.itm(4)} -attr xrf 8363 -attr oid 84 -attr vt d -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {slc(acc.imod.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod.sva)#1.itm} 3 {slc(acc.imod.sva)#1.itm(0)} {slc(acc.imod.sva)#1.itm(1)} {slc(acc.imod.sva)#1.itm(2)} -attr xrf 8364 -attr oid 85 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#1.itm}
+load net {FRAME:conc#33.itm(0)} -attr vt d
+load net {FRAME:conc#33.itm(1)} -attr vt d
+load net {FRAME:conc#33.itm(2)} -attr vt d
+load net {FRAME:conc#33.itm(3)} -attr vt d
+load netBundle {FRAME:conc#33.itm} 4 {FRAME:conc#33.itm(0)} {FRAME:conc#33.itm(1)} {FRAME:conc#33.itm(2)} {FRAME:conc#33.itm(3)} -attr xrf 8365 -attr oid 86 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(0)} -attr vt d
+load net {FRAME:not#5.itm(1)} -attr vt d
+load net {FRAME:not#5.itm(2)} -attr vt d
+load netBundle {FRAME:not#5.itm} 3 {FRAME:not#5.itm(0)} {FRAME:not#5.itm(1)} {FRAME:not#5.itm(2)} -attr xrf 8366 -attr oid 87 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {slc(acc.imod.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod.sva)#2.itm} 3 {slc(acc.imod.sva)#2.itm(0)} {slc(acc.imod.sva)#2.itm(1)} {slc(acc.imod.sva)#2.itm(2)} -attr xrf 8367 -attr oid 88 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#2.itm}
+load net {slc(acc.imod.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod.sva)#4.itm} 2 {slc(acc.imod.sva)#4.itm(0)} {slc(acc.imod.sva)#4.itm(1)} -attr xrf 8368 -attr oid 89 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#4.itm}
+load net {FRAME:not#6.itm(0)} -attr vt d
+load net {FRAME:not#6.itm(1)} -attr vt d
+load net {FRAME:not#6.itm(2)} -attr vt d
+load netBundle {FRAME:not#6.itm} 3 {FRAME:not#6.itm(0)} {FRAME:not#6.itm(1)} {FRAME:not#6.itm(2)} -attr xrf 8369 -attr oid 90 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {slc(red#2.sg1.sva)#8.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#8.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#8.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#8.itm} 3 {slc(red#2.sg1.sva)#8.itm(0)} {slc(red#2.sg1.sva)#8.itm(1)} {slc(red#2.sg1.sva)#8.itm(2)} -attr xrf 8370 -attr oid 91 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {FRAME:mul#4.itm(0)} -attr vt d
+load net {FRAME:mul#4.itm(1)} -attr vt d
+load net {FRAME:mul#4.itm(2)} -attr vt d
+load net {FRAME:mul#4.itm(3)} -attr vt d
+load net {FRAME:mul#4.itm(4)} -attr vt d
+load net {FRAME:mul#4.itm(5)} -attr vt d
+load net {FRAME:mul#4.itm(6)} -attr vt d
+load net {FRAME:mul#4.itm(7)} -attr vt d
+load net {FRAME:mul#4.itm(8)} -attr vt d
+load net {FRAME:mul#4.itm(9)} -attr vt d
+load net {FRAME:mul#4.itm(10)} -attr vt d
+load netBundle {FRAME:mul#4.itm} 11 {FRAME:mul#4.itm(0)} {FRAME:mul#4.itm(1)} {FRAME:mul#4.itm(2)} {FRAME:mul#4.itm(3)} {FRAME:mul#4.itm(4)} {FRAME:mul#4.itm(5)} {FRAME:mul#4.itm(6)} {FRAME:mul#4.itm(7)} {FRAME:mul#4.itm(8)} {FRAME:mul#4.itm(9)} {FRAME:mul#4.itm(10)} -attr xrf 8371 -attr oid 92 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {slc(blue#2.sg1.sva)#10.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#10.itm(1)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#10.itm} 2 {slc(blue#2.sg1.sva)#10.itm(0)} {slc(blue#2.sg1.sva)#10.itm(1)} -attr xrf 8372 -attr oid 93 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#10.itm}
+load net {FRAME:mul#5.itm(0)} -attr vt d
+load net {FRAME:mul#5.itm(1)} -attr vt d
+load net {FRAME:mul#5.itm(2)} -attr vt d
+load net {FRAME:mul#5.itm(3)} -attr vt d
+load net {FRAME:mul#5.itm(4)} -attr vt d
+load net {FRAME:mul#5.itm(5)} -attr vt d
+load net {FRAME:mul#5.itm(6)} -attr vt d
+load net {FRAME:mul#5.itm(7)} -attr vt d
+load net {FRAME:mul#5.itm(8)} -attr vt d
+load netBundle {FRAME:mul#5.itm} 9 {FRAME:mul#5.itm(0)} {FRAME:mul#5.itm(1)} {FRAME:mul#5.itm(2)} {FRAME:mul#5.itm(3)} {FRAME:mul#5.itm(4)} {FRAME:mul#5.itm(5)} {FRAME:mul#5.itm(6)} {FRAME:mul#5.itm(7)} {FRAME:mul#5.itm(8)} -attr xrf 8373 -attr oid 94 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {slc(blue#2.sg1.sva)#11.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#11.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#11.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#11.itm} 3 {slc(blue#2.sg1.sva)#11.itm(0)} {slc(blue#2.sg1.sva)#11.itm(1)} {slc(blue#2.sg1.sva)#11.itm(2)} -attr xrf 8374 -attr oid 95 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {slc(blue#2.sg1.sva)#2.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(2)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(3)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(4)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#2.itm} 6 {slc(blue#2.sg1.sva)#2.itm(0)} {slc(blue#2.sg1.sva)#2.itm(1)} {slc(blue#2.sg1.sva)#2.itm(2)} {slc(blue#2.sg1.sva)#2.itm(3)} {slc(blue#2.sg1.sva)#2.itm(4)} {slc(blue#2.sg1.sva)#2.itm(5)} -attr xrf 8375 -attr oid 96 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {FRAME:acc#30.itm(0)} -attr vt d
+load net {FRAME:acc#30.itm(1)} -attr vt d
+load net {FRAME:acc#30.itm(2)} -attr vt d
+load net {FRAME:acc#30.itm(3)} -attr vt d
+load net {FRAME:acc#30.itm(4)} -attr vt d
+load netBundle {FRAME:acc#30.itm} 5 {FRAME:acc#30.itm(0)} {FRAME:acc#30.itm(1)} {FRAME:acc#30.itm(2)} {FRAME:acc#30.itm(3)} {FRAME:acc#30.itm(4)} -attr xrf 8376 -attr oid 97 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#29.itm(0)} -attr vt d
+load net {FRAME:acc#29.itm(1)} -attr vt d
+load net {FRAME:acc#29.itm(2)} -attr vt d
+load net {FRAME:acc#29.itm(3)} -attr vt d
+load netBundle {FRAME:acc#29.itm} 4 {FRAME:acc#29.itm(0)} {FRAME:acc#29.itm(1)} {FRAME:acc#29.itm(2)} {FRAME:acc#29.itm(3)} -attr xrf 8377 -attr oid 98 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {conc#130.itm(0)} -attr vt d
+load net {conc#130.itm(1)} -attr vt d
+load net {conc#130.itm(2)} -attr vt d
+load netBundle {conc#130.itm} 3 {conc#130.itm(0)} {conc#130.itm(1)} {conc#130.itm(2)} -attr xrf 8378 -attr oid 99 -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {conc#131.itm(0)} -attr vt d
+load net {conc#131.itm(1)} -attr vt d
+load net {conc#131.itm(2)} -attr vt d
+load net {conc#131.itm(3)} -attr vt d
+load net {conc#131.itm(4)} -attr vt d
+load netBundle {conc#131.itm} 5 {conc#131.itm(0)} {conc#131.itm(1)} {conc#131.itm(2)} {conc#131.itm(3)} {conc#131.itm(4)} -attr xrf 8379 -attr oid 100 -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {slc(acc.imod#4.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#4.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#4.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#4.sva)#1.itm} 3 {slc(acc.imod#4.sva)#1.itm(0)} {slc(acc.imod#4.sva)#1.itm(1)} {slc(acc.imod#4.sva)#1.itm(2)} -attr xrf 8380 -attr oid 101 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#1.itm}
+load net {FRAME:conc#29.itm(0)} -attr vt d
+load net {FRAME:conc#29.itm(1)} -attr vt d
+load net {FRAME:conc#29.itm(2)} -attr vt d
+load net {FRAME:conc#29.itm(3)} -attr vt d
+load netBundle {FRAME:conc#29.itm} 4 {FRAME:conc#29.itm(0)} {FRAME:conc#29.itm(1)} {FRAME:conc#29.itm(2)} {FRAME:conc#29.itm(3)} -attr xrf 8381 -attr oid 102 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(0)} -attr vt d
+load net {FRAME:not#21.itm(1)} -attr vt d
+load net {FRAME:not#21.itm(2)} -attr vt d
+load netBundle {FRAME:not#21.itm} 3 {FRAME:not#21.itm(0)} {FRAME:not#21.itm(1)} {FRAME:not#21.itm(2)} -attr xrf 8382 -attr oid 103 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {slc(acc.imod#4.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#4.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#4.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#4.sva)#2.itm} 3 {slc(acc.imod#4.sva)#2.itm(0)} {slc(acc.imod#4.sva)#2.itm(1)} {slc(acc.imod#4.sva)#2.itm(2)} -attr xrf 8383 -attr oid 104 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#2.itm}
+load net {slc(acc.imod#4.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#4.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#4.sva)#4.itm} 2 {slc(acc.imod#4.sva)#4.itm(0)} {slc(acc.imod#4.sva)#4.itm(1)} -attr xrf 8384 -attr oid 105 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#4.itm}
+load net {FRAME:not#22.itm(0)} -attr vt d
+load net {FRAME:not#22.itm(1)} -attr vt d
+load net {FRAME:not#22.itm(2)} -attr vt d
+load netBundle {FRAME:not#22.itm} 3 {FRAME:not#22.itm(0)} {FRAME:not#22.itm(1)} {FRAME:not#22.itm(2)} -attr xrf 8385 -attr oid 106 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {slc(blue#2.sg1.sva)#9.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#9.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#9.itm} 3 {slc(blue#2.sg1.sva)#9.itm(0)} {slc(blue#2.sg1.sva)#9.itm(1)} {slc(blue#2.sg1.sva)#9.itm(2)} -attr xrf 8386 -attr oid 107 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {FRAME:mul#2.itm(0)} -attr vt d
+load net {FRAME:mul#2.itm(1)} -attr vt d
+load net {FRAME:mul#2.itm(2)} -attr vt d
+load net {FRAME:mul#2.itm(3)} -attr vt d
+load net {FRAME:mul#2.itm(4)} -attr vt d
+load net {FRAME:mul#2.itm(5)} -attr vt d
+load net {FRAME:mul#2.itm(6)} -attr vt d
+load net {FRAME:mul#2.itm(7)} -attr vt d
+load net {FRAME:mul#2.itm(8)} -attr vt d
+load net {FRAME:mul#2.itm(9)} -attr vt d
+load net {FRAME:mul#2.itm(10)} -attr vt d
+load netBundle {FRAME:mul#2.itm} 11 {FRAME:mul#2.itm(0)} {FRAME:mul#2.itm(1)} {FRAME:mul#2.itm(2)} {FRAME:mul#2.itm(3)} {FRAME:mul#2.itm(4)} {FRAME:mul#2.itm(5)} {FRAME:mul#2.itm(6)} {FRAME:mul#2.itm(7)} {FRAME:mul#2.itm(8)} {FRAME:mul#2.itm(9)} {FRAME:mul#2.itm(10)} -attr xrf 8387 -attr oid 108 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {slc(green#2.sg1.sva)#10.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#10.itm(1)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#10.itm} 2 {slc(green#2.sg1.sva)#10.itm(0)} {slc(green#2.sg1.sva)#10.itm(1)} -attr xrf 8388 -attr oid 109 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#10.itm}
+load net {FRAME:mul#3.itm(0)} -attr vt d
+load net {FRAME:mul#3.itm(1)} -attr vt d
+load net {FRAME:mul#3.itm(2)} -attr vt d
+load net {FRAME:mul#3.itm(3)} -attr vt d
+load net {FRAME:mul#3.itm(4)} -attr vt d
+load net {FRAME:mul#3.itm(5)} -attr vt d
+load net {FRAME:mul#3.itm(6)} -attr vt d
+load net {FRAME:mul#3.itm(7)} -attr vt d
+load net {FRAME:mul#3.itm(8)} -attr vt d
+load netBundle {FRAME:mul#3.itm} 9 {FRAME:mul#3.itm(0)} {FRAME:mul#3.itm(1)} {FRAME:mul#3.itm(2)} {FRAME:mul#3.itm(3)} {FRAME:mul#3.itm(4)} {FRAME:mul#3.itm(5)} {FRAME:mul#3.itm(6)} {FRAME:mul#3.itm(7)} {FRAME:mul#3.itm(8)} -attr xrf 8389 -attr oid 110 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {slc(green#2.sg1.sva)#11.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#11.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#11.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#11.itm} 3 {slc(green#2.sg1.sva)#11.itm(0)} {slc(green#2.sg1.sva)#11.itm(1)} {slc(green#2.sg1.sva)#11.itm(2)} -attr xrf 8390 -attr oid 111 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {slc(green#2.sg1.sva)#2.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(2)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(3)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(4)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#2.itm} 6 {slc(green#2.sg1.sva)#2.itm(0)} {slc(green#2.sg1.sva)#2.itm(1)} {slc(green#2.sg1.sva)#2.itm(2)} {slc(green#2.sg1.sva)#2.itm(3)} {slc(green#2.sg1.sva)#2.itm(4)} {slc(green#2.sg1.sva)#2.itm(5)} -attr xrf 8391 -attr oid 112 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {FRAME:acc#18.itm(0)} -attr vt d
+load net {FRAME:acc#18.itm(1)} -attr vt d
+load net {FRAME:acc#18.itm(2)} -attr vt d
+load net {FRAME:acc#18.itm(3)} -attr vt d
+load net {FRAME:acc#18.itm(4)} -attr vt d
+load netBundle {FRAME:acc#18.itm} 5 {FRAME:acc#18.itm(0)} {FRAME:acc#18.itm(1)} {FRAME:acc#18.itm(2)} {FRAME:acc#18.itm(3)} {FRAME:acc#18.itm(4)} -attr xrf 8392 -attr oid 113 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#17.itm(0)} -attr vt d
+load net {FRAME:acc#17.itm(1)} -attr vt d
+load net {FRAME:acc#17.itm(2)} -attr vt d
+load net {FRAME:acc#17.itm(3)} -attr vt d
+load netBundle {FRAME:acc#17.itm} 4 {FRAME:acc#17.itm(0)} {FRAME:acc#17.itm(1)} {FRAME:acc#17.itm(2)} {FRAME:acc#17.itm(3)} -attr xrf 8393 -attr oid 114 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {conc#132.itm(0)} -attr vt d
+load net {conc#132.itm(1)} -attr vt d
+load net {conc#132.itm(2)} -attr vt d
+load netBundle {conc#132.itm} 3 {conc#132.itm(0)} {conc#132.itm(1)} {conc#132.itm(2)} -attr xrf 8394 -attr oid 115 -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {conc#133.itm(0)} -attr vt d
+load net {conc#133.itm(1)} -attr vt d
+load net {conc#133.itm(2)} -attr vt d
+load net {conc#133.itm(3)} -attr vt d
+load net {conc#133.itm(4)} -attr vt d
+load netBundle {conc#133.itm} 5 {conc#133.itm(0)} {conc#133.itm(1)} {conc#133.itm(2)} {conc#133.itm(3)} {conc#133.itm(4)} -attr xrf 8395 -attr oid 116 -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {slc(acc.imod#2.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#2.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#2.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#2.sva)#1.itm} 3 {slc(acc.imod#2.sva)#1.itm(0)} {slc(acc.imod#2.sva)#1.itm(1)} {slc(acc.imod#2.sva)#1.itm(2)} -attr xrf 8396 -attr oid 117 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#1.itm}
+load net {FRAME:conc#25.itm(0)} -attr vt d
+load net {FRAME:conc#25.itm(1)} -attr vt d
+load net {FRAME:conc#25.itm(2)} -attr vt d
+load net {FRAME:conc#25.itm(3)} -attr vt d
+load netBundle {FRAME:conc#25.itm} 4 {FRAME:conc#25.itm(0)} {FRAME:conc#25.itm(1)} {FRAME:conc#25.itm(2)} {FRAME:conc#25.itm(3)} -attr xrf 8397 -attr oid 118 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(0)} -attr vt d
+load net {FRAME:not#13.itm(1)} -attr vt d
+load net {FRAME:not#13.itm(2)} -attr vt d
+load netBundle {FRAME:not#13.itm} 3 {FRAME:not#13.itm(0)} {FRAME:not#13.itm(1)} {FRAME:not#13.itm(2)} -attr xrf 8398 -attr oid 119 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {slc(acc.imod#2.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#2.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#2.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#2.sva)#2.itm} 3 {slc(acc.imod#2.sva)#2.itm(0)} {slc(acc.imod#2.sva)#2.itm(1)} {slc(acc.imod#2.sva)#2.itm(2)} -attr xrf 8399 -attr oid 120 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#2.itm}
+load net {slc(acc.imod#2.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#2.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#2.sva)#4.itm} 2 {slc(acc.imod#2.sva)#4.itm(0)} {slc(acc.imod#2.sva)#4.itm(1)} -attr xrf 8400 -attr oid 121 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#4.itm}
+load net {FRAME:not#14.itm(0)} -attr vt d
+load net {FRAME:not#14.itm(1)} -attr vt d
+load net {FRAME:not#14.itm(2)} -attr vt d
+load netBundle {FRAME:not#14.itm} 3 {FRAME:not#14.itm(0)} {FRAME:not#14.itm(1)} {FRAME:not#14.itm(2)} -attr xrf 8401 -attr oid 122 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {slc(green#2.sg1.sva)#9.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#9.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#9.itm} 3 {slc(green#2.sg1.sva)#9.itm(0)} {slc(green#2.sg1.sva)#9.itm(1)} {slc(green#2.sg1.sva)#9.itm(2)} -attr xrf 8402 -attr oid 123 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {mux#5.itm(0)} -attr vt d
+load net {mux#5.itm(1)} -attr vt d
+load net {mux#5.itm(2)} -attr vt d
+load net {mux#5.itm(3)} -attr vt d
+load net {mux#5.itm(4)} -attr vt d
+load net {mux#5.itm(5)} -attr vt d
+load net {mux#5.itm(6)} -attr vt d
+load net {mux#5.itm(7)} -attr vt d
+load net {mux#5.itm(8)} -attr vt d
+load net {mux#5.itm(9)} -attr vt d
+load net {mux#5.itm(10)} -attr vt d
+load net {mux#5.itm(11)} -attr vt d
+load net {mux#5.itm(12)} -attr vt d
+load net {mux#5.itm(13)} -attr vt d
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+load net {FRAME:acc#7.itm(3)} -attr vt d
+load netBundle {FRAME:acc#7.itm} 4 {FRAME:acc#7.itm(0)} {FRAME:acc#7.itm(1)} {FRAME:acc#7.itm(2)} {FRAME:acc#7.itm(3)} -attr xrf 8429 -attr oid 150 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {conc#140.itm(0)} -attr vt d
+load net {conc#140.itm(1)} -attr vt d
+load net {conc#140.itm(2)} -attr vt d
+load netBundle {conc#140.itm} 3 {conc#140.itm(0)} {conc#140.itm(1)} {conc#140.itm(2)} -attr xrf 8430 -attr oid 151 -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {slc(red#2.sg1.sva)#5.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#5.itm(1)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#5.itm} 2 {slc(red#2.sg1.sva)#5.itm(0)} {slc(red#2.sg1.sva)#5.itm(1)} -attr xrf 8431 -attr oid 152 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#5.itm}
+load net {FRAME:acc#9.itm(0)} -attr vt d
+load net {FRAME:acc#9.itm(1)} -attr vt d
+load net {FRAME:acc#9.itm(2)} -attr vt d
+load net {FRAME:acc#9.itm(3)} -attr vt d
+load netBundle {FRAME:acc#9.itm} 4 {FRAME:acc#9.itm(0)} {FRAME:acc#9.itm(1)} {FRAME:acc#9.itm(2)} {FRAME:acc#9.itm(3)} -attr xrf 8432 -attr oid 153 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {slc(red#2.sg1.sva)#6.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#6.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#6.itm} 3 {slc(red#2.sg1.sva)#6.itm(0)} {slc(red#2.sg1.sva)#6.itm(1)} {slc(red#2.sg1.sva)#6.itm(2)} -attr xrf 8433 -attr oid 154 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {FRAME:not#1.itm(0)} -attr vt d
+load net {FRAME:not#1.itm(1)} -attr vt d
+load net {FRAME:not#1.itm(2)} -attr vt d
+load netBundle {FRAME:not#1.itm} 3 {FRAME:not#1.itm(0)} {FRAME:not#1.itm(1)} {FRAME:not#1.itm(2)} -attr xrf 8434 -attr oid 155 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {slc(red#2.sg1.sva)#7.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#7.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#7.itm} 3 {slc(red#2.sg1.sva)#7.itm(0)} {slc(red#2.sg1.sva)#7.itm(1)} {slc(red#2.sg1.sva)#7.itm(2)} -attr xrf 8435 -attr oid 156 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {ACC1:acc#43.itm(0)} -attr vt d
+load net {ACC1:acc#43.itm(1)} -attr vt d
+load net {ACC1:acc#43.itm(2)} -attr vt d
+load net {ACC1:acc#43.itm(3)} -attr vt d
+load net {ACC1:acc#43.itm(4)} -attr vt d
+load net {ACC1:acc#43.itm(5)} -attr vt d
+load net {ACC1:acc#43.itm(6)} -attr vt d
+load net {ACC1:acc#43.itm(7)} -attr vt d
+load net {ACC1:acc#43.itm(8)} -attr vt d
+load net {ACC1:acc#43.itm(9)} -attr vt d
+load net {ACC1:acc#43.itm(10)} -attr vt d
+load net {ACC1:acc#43.itm(11)} -attr vt d
+load net {ACC1:acc#43.itm(12)} -attr vt d
+load net {ACC1:acc#43.itm(13)} -attr vt d
+load net {ACC1:acc#43.itm(14)} -attr vt d
+load net {ACC1:acc#43.itm(15)} -attr vt d
+load netBundle {ACC1:acc#43.itm} 16 {ACC1:acc#43.itm(0)} {ACC1:acc#43.itm(1)} {ACC1:acc#43.itm(2)} {ACC1:acc#43.itm(3)} {ACC1:acc#43.itm(4)} {ACC1:acc#43.itm(5)} {ACC1:acc#43.itm(6)} {ACC1:acc#43.itm(7)} {ACC1:acc#43.itm(8)} {ACC1:acc#43.itm(9)} {ACC1:acc#43.itm(10)} {ACC1:acc#43.itm(11)} {ACC1:acc#43.itm(12)} {ACC1:acc#43.itm(13)} {ACC1:acc#43.itm(14)} {ACC1:acc#43.itm(15)} -attr xrf 8436 -attr oid 157 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:conc#45.itm(0)} -attr vt d
+load net {ACC1:conc#45.itm(1)} -attr vt d
+load net {ACC1:conc#45.itm(2)} -attr vt d
+load net {ACC1:conc#45.itm(3)} -attr vt d
+load net {ACC1:conc#45.itm(4)} -attr vt d
+load net {ACC1:conc#45.itm(5)} -attr vt d
+load net {ACC1:conc#45.itm(6)} -attr vt d
+load net {ACC1:conc#45.itm(7)} -attr vt d
+load net {ACC1:conc#45.itm(8)} -attr vt d
+load net {ACC1:conc#45.itm(9)} -attr vt d
+load net {ACC1:conc#45.itm(10)} -attr vt d
+load net {ACC1:conc#45.itm(11)} -attr vt d
+load net {ACC1:conc#45.itm(12)} -attr vt d
+load net {ACC1:conc#45.itm(13)} -attr vt d
+load net {ACC1:conc#45.itm(14)} -attr vt d
+load net {ACC1:conc#45.itm(15)} -attr vt d
+load netBundle {ACC1:conc#45.itm} 16 {ACC1:conc#45.itm(0)} {ACC1:conc#45.itm(1)} {ACC1:conc#45.itm(2)} {ACC1:conc#45.itm(3)} {ACC1:conc#45.itm(4)} {ACC1:conc#45.itm(5)} {ACC1:conc#45.itm(6)} {ACC1:conc#45.itm(7)} {ACC1:conc#45.itm(8)} {ACC1:conc#45.itm(9)} {ACC1:conc#45.itm(10)} {ACC1:conc#45.itm(11)} {ACC1:conc#45.itm(12)} {ACC1:conc#45.itm(13)} {ACC1:conc#45.itm(14)} {ACC1:conc#45.itm(15)} -attr xrf 8437 -attr oid 158 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(0)} -attr vt d
+load net {ACC1:acc#62.itm(1)} -attr vt d
+load net {ACC1:acc#62.itm(2)} -attr vt d
+load net {ACC1:acc#62.itm(3)} -attr vt d
+load net {ACC1:acc#62.itm(4)} -attr vt d
+load net {ACC1:acc#62.itm(5)} -attr vt d
+load net {ACC1:acc#62.itm(6)} -attr vt d
+load net {ACC1:acc#62.itm(7)} -attr vt d
+load net {ACC1:acc#62.itm(8)} -attr vt d
+load net {ACC1:acc#62.itm(9)} -attr vt d
+load net {ACC1:acc#62.itm(10)} -attr vt d
+load net {ACC1:acc#62.itm(11)} -attr vt d
+load net {ACC1:acc#62.itm(12)} -attr vt d
+load net {ACC1:acc#62.itm(13)} -attr vt d
+load net {ACC1:acc#62.itm(14)} -attr vt d
+load netBundle {ACC1:acc#62.itm} 15 {ACC1:acc#62.itm(0)} {ACC1:acc#62.itm(1)} {ACC1:acc#62.itm(2)} {ACC1:acc#62.itm(3)} {ACC1:acc#62.itm(4)} {ACC1:acc#62.itm(5)} {ACC1:acc#62.itm(6)} {ACC1:acc#62.itm(7)} {ACC1:acc#62.itm(8)} {ACC1:acc#62.itm(9)} {ACC1:acc#62.itm(10)} {ACC1:acc#62.itm(11)} {ACC1:acc#62.itm(12)} {ACC1:acc#62.itm(13)} {ACC1:acc#62.itm(14)} -attr xrf 8438 -attr oid 159 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {slc.itm(0)} -attr vt d
+load net {slc.itm(1)} -attr vt d
+load net {slc.itm(2)} -attr vt d
+load net {slc.itm(3)} -attr vt d
+load net {slc.itm(4)} -attr vt d
+load net {slc.itm(5)} -attr vt d
+load net {slc.itm(6)} -attr vt d
+load net {slc.itm(7)} -attr vt d
+load net {slc.itm(8)} -attr vt d
+load net {slc.itm(9)} -attr vt d
+load net {slc.itm(10)} -attr vt d
+load netBundle {slc.itm} 11 {slc.itm(0)} {slc.itm(1)} {slc.itm(2)} {slc.itm(3)} {slc.itm(4)} {slc.itm(5)} {slc.itm(6)} {slc.itm(7)} {slc.itm(8)} {slc.itm(9)} {slc.itm(10)} -attr xrf 8439 -attr oid 160 -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(0)} -attr vt d
+load net {acc#5.itm(1)} -attr vt d
+load net {acc#5.itm(2)} -attr vt d
+load net {acc#5.itm(3)} -attr vt d
+load net {acc#5.itm(4)} -attr vt d
+load net {acc#5.itm(5)} -attr vt d
+load net {acc#5.itm(6)} -attr vt d
+load net {acc#5.itm(7)} -attr vt d
+load net {acc#5.itm(8)} -attr vt d
+load net {acc#5.itm(9)} -attr vt d
+load net {acc#5.itm(10)} -attr vt d
+load net {acc#5.itm(11)} -attr vt d
+load netBundle {acc#5.itm} 12 {acc#5.itm(0)} {acc#5.itm(1)} {acc#5.itm(2)} {acc#5.itm(3)} {acc#5.itm(4)} {acc#5.itm(5)} {acc#5.itm(6)} {acc#5.itm(7)} {acc#5.itm(8)} {acc#5.itm(9)} {acc#5.itm(10)} {acc#5.itm(11)} -attr xrf 8440 -attr oid 161 -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {conc#141.itm(0)} -attr vt d
+load net {conc#141.itm(1)} -attr vt d
+load net {conc#141.itm(2)} -attr vt d
+load net {conc#141.itm(3)} -attr vt d
+load net {conc#141.itm(4)} -attr vt d
+load net {conc#141.itm(5)} -attr vt d
+load net {conc#141.itm(6)} -attr vt d
+load net {conc#141.itm(7)} -attr vt d
+load net {conc#141.itm(8)} -attr vt d
+load net {conc#141.itm(9)} -attr vt d
+load net {conc#141.itm(10)} -attr vt d
+load netBundle {conc#141.itm} 11 {conc#141.itm(0)} {conc#141.itm(1)} {conc#141.itm(2)} {conc#141.itm(3)} {conc#141.itm(4)} {conc#141.itm(5)} {conc#141.itm(6)} {conc#141.itm(7)} {conc#141.itm(8)} {conc#141.itm(9)} {conc#141.itm(10)} -attr xrf 8441 -attr oid 162 -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(0)} -attr vt d
+load net {ACC2:not.itm(1)} -attr vt d
+load net {ACC2:not.itm(2)} -attr vt d
+load net {ACC2:not.itm(3)} -attr vt d
+load net {ACC2:not.itm(4)} -attr vt d
+load net {ACC2:not.itm(5)} -attr vt d
+load net {ACC2:not.itm(6)} -attr vt d
+load net {ACC2:not.itm(7)} -attr vt d
+load net {ACC2:not.itm(8)} -attr vt d
+load net {ACC2:not.itm(9)} -attr vt d
+load netBundle {ACC2:not.itm} 10 {ACC2:not.itm(0)} {ACC2:not.itm(1)} {ACC2:not.itm(2)} {ACC2:not.itm(3)} {ACC2:not.itm(4)} {ACC2:not.itm(5)} {ACC2:not.itm(6)} {ACC2:not.itm(7)} {ACC2:not.itm(8)} {ACC2:not.itm(9)} -attr xrf 8442 -attr oid 163 -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr xrf 8443 -attr oid 164 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {conc#142.itm(0)} -attr vt d
+load net {conc#142.itm(1)} -attr vt d
+load net {conc#142.itm(2)} -attr vt d
+load net {conc#142.itm(3)} -attr vt d
+load net {conc#142.itm(4)} -attr vt d
+load net {conc#142.itm(5)} -attr vt d
+load net {conc#142.itm(6)} -attr vt d
+load net {conc#142.itm(7)} -attr vt d
+load net {conc#142.itm(8)} -attr vt d
+load net {conc#142.itm(9)} -attr vt d
+load net {conc#142.itm(10)} -attr vt d
+load netBundle {conc#142.itm} 11 {conc#142.itm(0)} {conc#142.itm(1)} {conc#142.itm(2)} {conc#142.itm(3)} {conc#142.itm(4)} {conc#142.itm(5)} {conc#142.itm(6)} {conc#142.itm(7)} {conc#142.itm(8)} {conc#142.itm(9)} {conc#142.itm(10)} -attr xrf 8444 -attr oid 165 -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(9)} -attr xrf 8445 -attr oid 166 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {slc(r(2).sva#1).itm(0)} -attr vt d
+load net {slc(r(2).sva#1).itm(1)} -attr vt d
+load net {slc(r(2).sva#1).itm(2)} -attr vt d
+load net {slc(r(2).sva#1).itm(3)} -attr vt d
+load net {slc(r(2).sva#1).itm(4)} -attr vt d
+load net {slc(r(2).sva#1).itm(5)} -attr vt d
+load net {slc(r(2).sva#1).itm(6)} -attr vt d
+load net {slc(r(2).sva#1).itm(7)} -attr vt d
+load net {slc(r(2).sva#1).itm(8)} -attr vt d
+load net {slc(r(2).sva#1).itm(9)} -attr vt d
+load net {slc(r(2).sva#1).itm(10)} -attr vt d
+load net {slc(r(2).sva#1).itm(11)} -attr vt d
+load net {slc(r(2).sva#1).itm(12)} -attr vt d
+load net {slc(r(2).sva#1).itm(13)} -attr vt d
+load net {slc(r(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(r(2).sva#1).itm} 15 {slc(r(2).sva#1).itm(0)} {slc(r(2).sva#1).itm(1)} {slc(r(2).sva#1).itm(2)} {slc(r(2).sva#1).itm(3)} {slc(r(2).sva#1).itm(4)} {slc(r(2).sva#1).itm(5)} {slc(r(2).sva#1).itm(6)} {slc(r(2).sva#1).itm(7)} {slc(r(2).sva#1).itm(8)} {slc(r(2).sva#1).itm(9)} {slc(r(2).sva#1).itm(10)} {slc(r(2).sva#1).itm(11)} {slc(r(2).sva#1).itm(12)} {slc(r(2).sva#1).itm(13)} {slc(r(2).sva#1).itm(14)} -attr xrf 8446 -attr oid 167 -attr vt d -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {conc#143.itm(0)} -attr vt d
+load net {conc#143.itm(1)} -attr vt d
+load netBundle {conc#143.itm} 2 {conc#143.itm(0)} {conc#143.itm(1)} -attr xrf 8447 -attr oid 168 -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {slc(red#2.sg1.sva)#12.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#12.itm(1)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#12.itm} 2 {slc(red#2.sg1.sva)#12.itm(0)} {slc(red#2.sg1.sva)#12.itm(1)} -attr xrf 8448 -attr oid 169 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#12.itm}
+load net {ACC1:acc#45.itm(0)} -attr vt d
+load net {ACC1:acc#45.itm(1)} -attr vt d
+load net {ACC1:acc#45.itm(2)} -attr vt d
+load net {ACC1:acc#45.itm(3)} -attr vt d
+load net {ACC1:acc#45.itm(4)} -attr vt d
+load net {ACC1:acc#45.itm(5)} -attr vt d
+load net {ACC1:acc#45.itm(6)} -attr vt d
+load net {ACC1:acc#45.itm(7)} -attr vt d
+load net {ACC1:acc#45.itm(8)} -attr vt d
+load net {ACC1:acc#45.itm(9)} -attr vt d
+load net {ACC1:acc#45.itm(10)} -attr vt d
+load net {ACC1:acc#45.itm(11)} -attr vt d
+load net {ACC1:acc#45.itm(12)} -attr vt d
+load net {ACC1:acc#45.itm(13)} -attr vt d
+load net {ACC1:acc#45.itm(14)} -attr vt d
+load net {ACC1:acc#45.itm(15)} -attr vt d
+load netBundle {ACC1:acc#45.itm} 16 {ACC1:acc#45.itm(0)} {ACC1:acc#45.itm(1)} {ACC1:acc#45.itm(2)} {ACC1:acc#45.itm(3)} {ACC1:acc#45.itm(4)} {ACC1:acc#45.itm(5)} {ACC1:acc#45.itm(6)} {ACC1:acc#45.itm(7)} {ACC1:acc#45.itm(8)} {ACC1:acc#45.itm(9)} {ACC1:acc#45.itm(10)} {ACC1:acc#45.itm(11)} {ACC1:acc#45.itm(12)} {ACC1:acc#45.itm(13)} {ACC1:acc#45.itm(14)} {ACC1:acc#45.itm(15)} -attr xrf 8449 -attr oid 170 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:conc#49.itm(0)} -attr vt d
+load net {ACC1:conc#49.itm(1)} -attr vt d
+load net {ACC1:conc#49.itm(2)} -attr vt d
+load net {ACC1:conc#49.itm(3)} -attr vt d
+load net {ACC1:conc#49.itm(4)} -attr vt d
+load net {ACC1:conc#49.itm(5)} -attr vt d
+load net {ACC1:conc#49.itm(6)} -attr vt d
+load net {ACC1:conc#49.itm(7)} -attr vt d
+load net {ACC1:conc#49.itm(8)} -attr vt d
+load net {ACC1:conc#49.itm(9)} -attr vt d
+load net {ACC1:conc#49.itm(10)} -attr vt d
+load net {ACC1:conc#49.itm(11)} -attr vt d
+load net {ACC1:conc#49.itm(12)} -attr vt d
+load net {ACC1:conc#49.itm(13)} -attr vt d
+load net {ACC1:conc#49.itm(14)} -attr vt d
+load net {ACC1:conc#49.itm(15)} -attr vt d
+load netBundle {ACC1:conc#49.itm} 16 {ACC1:conc#49.itm(0)} {ACC1:conc#49.itm(1)} {ACC1:conc#49.itm(2)} {ACC1:conc#49.itm(3)} {ACC1:conc#49.itm(4)} {ACC1:conc#49.itm(5)} {ACC1:conc#49.itm(6)} {ACC1:conc#49.itm(7)} {ACC1:conc#49.itm(8)} {ACC1:conc#49.itm(9)} {ACC1:conc#49.itm(10)} {ACC1:conc#49.itm(11)} {ACC1:conc#49.itm(12)} {ACC1:conc#49.itm(13)} {ACC1:conc#49.itm(14)} {ACC1:conc#49.itm(15)} -attr xrf 8450 -attr oid 171 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(0)} -attr vt d
+load net {ACC1:acc#70.itm(1)} -attr vt d
+load net {ACC1:acc#70.itm(2)} -attr vt d
+load net {ACC1:acc#70.itm(3)} -attr vt d
+load net {ACC1:acc#70.itm(4)} -attr vt d
+load net {ACC1:acc#70.itm(5)} -attr vt d
+load net {ACC1:acc#70.itm(6)} -attr vt d
+load net {ACC1:acc#70.itm(7)} -attr vt d
+load net {ACC1:acc#70.itm(8)} -attr vt d
+load net {ACC1:acc#70.itm(9)} -attr vt d
+load net {ACC1:acc#70.itm(10)} -attr vt d
+load net {ACC1:acc#70.itm(11)} -attr vt d
+load net {ACC1:acc#70.itm(12)} -attr vt d
+load net {ACC1:acc#70.itm(13)} -attr vt d
+load net {ACC1:acc#70.itm(14)} -attr vt d
+load netBundle {ACC1:acc#70.itm} 15 {ACC1:acc#70.itm(0)} {ACC1:acc#70.itm(1)} {ACC1:acc#70.itm(2)} {ACC1:acc#70.itm(3)} {ACC1:acc#70.itm(4)} {ACC1:acc#70.itm(5)} {ACC1:acc#70.itm(6)} {ACC1:acc#70.itm(7)} {ACC1:acc#70.itm(8)} {ACC1:acc#70.itm(9)} {ACC1:acc#70.itm(10)} {ACC1:acc#70.itm(11)} {ACC1:acc#70.itm(12)} {ACC1:acc#70.itm(13)} {ACC1:acc#70.itm(14)} -attr xrf 8451 -attr oid 172 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {slc#1.itm(0)} -attr vt d
+load net {slc#1.itm(1)} -attr vt d
+load net {slc#1.itm(2)} -attr vt d
+load net {slc#1.itm(3)} -attr vt d
+load net {slc#1.itm(4)} -attr vt d
+load net {slc#1.itm(5)} -attr vt d
+load net {slc#1.itm(6)} -attr vt d
+load net {slc#1.itm(7)} -attr vt d
+load net {slc#1.itm(8)} -attr vt d
+load net {slc#1.itm(9)} -attr vt d
+load net {slc#1.itm(10)} -attr vt d
+load netBundle {slc#1.itm} 11 {slc#1.itm(0)} {slc#1.itm(1)} {slc#1.itm(2)} {slc#1.itm(3)} {slc#1.itm(4)} {slc#1.itm(5)} {slc#1.itm(6)} {slc#1.itm(7)} {slc#1.itm(8)} {slc#1.itm(9)} {slc#1.itm(10)} -attr xrf 8452 -attr oid 173 -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(0)} -attr vt d
+load net {acc#6.itm(1)} -attr vt d
+load net {acc#6.itm(2)} -attr vt d
+load net {acc#6.itm(3)} -attr vt d
+load net {acc#6.itm(4)} -attr vt d
+load net {acc#6.itm(5)} -attr vt d
+load net {acc#6.itm(6)} -attr vt d
+load net {acc#6.itm(7)} -attr vt d
+load net {acc#6.itm(8)} -attr vt d
+load net {acc#6.itm(9)} -attr vt d
+load net {acc#6.itm(10)} -attr vt d
+load net {acc#6.itm(11)} -attr vt d
+load netBundle {acc#6.itm} 12 {acc#6.itm(0)} {acc#6.itm(1)} {acc#6.itm(2)} {acc#6.itm(3)} {acc#6.itm(4)} {acc#6.itm(5)} {acc#6.itm(6)} {acc#6.itm(7)} {acc#6.itm(8)} {acc#6.itm(9)} {acc#6.itm(10)} {acc#6.itm(11)} -attr xrf 8453 -attr oid 174 -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {conc#144.itm(0)} -attr vt d
+load net {conc#144.itm(1)} -attr vt d
+load net {conc#144.itm(2)} -attr vt d
+load net {conc#144.itm(3)} -attr vt d
+load net {conc#144.itm(4)} -attr vt d
+load net {conc#144.itm(5)} -attr vt d
+load net {conc#144.itm(6)} -attr vt d
+load net {conc#144.itm(7)} -attr vt d
+load net {conc#144.itm(8)} -attr vt d
+load net {conc#144.itm(9)} -attr vt d
+load net {conc#144.itm(10)} -attr vt d
+load netBundle {conc#144.itm} 11 {conc#144.itm(0)} {conc#144.itm(1)} {conc#144.itm(2)} {conc#144.itm(3)} {conc#144.itm(4)} {conc#144.itm(5)} {conc#144.itm(6)} {conc#144.itm(7)} {conc#144.itm(8)} {conc#144.itm(9)} {conc#144.itm(10)} -attr xrf 8454 -attr oid 175 -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(0)} -attr vt d
+load net {ACC2:not#4.itm(1)} -attr vt d
+load net {ACC2:not#4.itm(2)} -attr vt d
+load net {ACC2:not#4.itm(3)} -attr vt d
+load net {ACC2:not#4.itm(4)} -attr vt d
+load net {ACC2:not#4.itm(5)} -attr vt d
+load net {ACC2:not#4.itm(6)} -attr vt d
+load net {ACC2:not#4.itm(7)} -attr vt d
+load net {ACC2:not#4.itm(8)} -attr vt d
+load net {ACC2:not#4.itm(9)} -attr vt d
+load netBundle {ACC2:not#4.itm} 10 {ACC2:not#4.itm(0)} {ACC2:not#4.itm(1)} {ACC2:not#4.itm(2)} {ACC2:not#4.itm(3)} {ACC2:not#4.itm(4)} {ACC2:not#4.itm(5)} {ACC2:not#4.itm(6)} {ACC2:not#4.itm(7)} {ACC2:not#4.itm(8)} {ACC2:not#4.itm(9)} -attr xrf 8455 -attr oid 176 -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0).itm} 10 {slc(regs.regs(0).sva.dfm:mx0).itm(0)} {slc(regs.regs(0).sva.dfm:mx0).itm(1)} {slc(regs.regs(0).sva.dfm:mx0).itm(2)} {slc(regs.regs(0).sva.dfm:mx0).itm(3)} {slc(regs.regs(0).sva.dfm:mx0).itm(4)} {slc(regs.regs(0).sva.dfm:mx0).itm(5)} {slc(regs.regs(0).sva.dfm:mx0).itm(6)} {slc(regs.regs(0).sva.dfm:mx0).itm(7)} {slc(regs.regs(0).sva.dfm:mx0).itm(8)} {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr xrf 8456 -attr oid 177 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {conc#145.itm(0)} -attr vt d
+load net {conc#145.itm(1)} -attr vt d
+load net {conc#145.itm(2)} -attr vt d
+load net {conc#145.itm(3)} -attr vt d
+load net {conc#145.itm(4)} -attr vt d
+load net {conc#145.itm(5)} -attr vt d
+load net {conc#145.itm(6)} -attr vt d
+load net {conc#145.itm(7)} -attr vt d
+load net {conc#145.itm(8)} -attr vt d
+load net {conc#145.itm(9)} -attr vt d
+load net {conc#145.itm(10)} -attr vt d
+load netBundle {conc#145.itm} 11 {conc#145.itm(0)} {conc#145.itm(1)} {conc#145.itm(2)} {conc#145.itm(3)} {conc#145.itm(4)} {conc#145.itm(5)} {conc#145.itm(6)} {conc#145.itm(7)} {conc#145.itm(8)} {conc#145.itm(9)} {conc#145.itm(10)} -attr xrf 8457 -attr oid 178 -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0).itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0).itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(9)} -attr xrf 8458 -attr oid 179 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {slc(b(2).sva#1).itm(0)} -attr vt d
+load net {slc(b(2).sva#1).itm(1)} -attr vt d
+load net {slc(b(2).sva#1).itm(2)} -attr vt d
+load net {slc(b(2).sva#1).itm(3)} -attr vt d
+load net {slc(b(2).sva#1).itm(4)} -attr vt d
+load net {slc(b(2).sva#1).itm(5)} -attr vt d
+load net {slc(b(2).sva#1).itm(6)} -attr vt d
+load net {slc(b(2).sva#1).itm(7)} -attr vt d
+load net {slc(b(2).sva#1).itm(8)} -attr vt d
+load net {slc(b(2).sva#1).itm(9)} -attr vt d
+load net {slc(b(2).sva#1).itm(10)} -attr vt d
+load net {slc(b(2).sva#1).itm(11)} -attr vt d
+load net {slc(b(2).sva#1).itm(12)} -attr vt d
+load net {slc(b(2).sva#1).itm(13)} -attr vt d
+load net {slc(b(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(b(2).sva#1).itm} 15 {slc(b(2).sva#1).itm(0)} {slc(b(2).sva#1).itm(1)} {slc(b(2).sva#1).itm(2)} {slc(b(2).sva#1).itm(3)} {slc(b(2).sva#1).itm(4)} {slc(b(2).sva#1).itm(5)} {slc(b(2).sva#1).itm(6)} {slc(b(2).sva#1).itm(7)} {slc(b(2).sva#1).itm(8)} {slc(b(2).sva#1).itm(9)} {slc(b(2).sva#1).itm(10)} {slc(b(2).sva#1).itm(11)} {slc(b(2).sva#1).itm(12)} {slc(b(2).sva#1).itm(13)} {slc(b(2).sva#1).itm(14)} -attr xrf 8459 -attr oid 180 -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {conc#146.itm(0)} -attr vt d
+load net {conc#146.itm(1)} -attr vt d
+load netBundle {conc#146.itm} 2 {conc#146.itm(0)} {conc#146.itm(1)} -attr xrf 8460 -attr oid 181 -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {FRAME:acc#28.itm(0)} -attr vt d
+load net {FRAME:acc#28.itm(1)} -attr vt d
+load net {FRAME:acc#28.itm(2)} -attr vt d
+load net {FRAME:acc#28.itm(3)} -attr vt d
+load net {FRAME:acc#28.itm(4)} -attr vt d
+load net {FRAME:acc#28.itm(5)} -attr vt d
+load netBundle {FRAME:acc#28.itm} 6 {FRAME:acc#28.itm(0)} {FRAME:acc#28.itm(1)} {FRAME:acc#28.itm(2)} {FRAME:acc#28.itm(3)} {FRAME:acc#28.itm(4)} {FRAME:acc#28.itm(5)} -attr xrf 8461 -attr oid 182 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#27.itm(0)} -attr vt d
+load net {FRAME:acc#27.itm(1)} -attr vt d
+load net {FRAME:acc#27.itm(2)} -attr vt d
+load net {FRAME:acc#27.itm(3)} -attr vt d
+load net {FRAME:acc#27.itm(4)} -attr vt d
+load netBundle {FRAME:acc#27.itm} 5 {FRAME:acc#27.itm(0)} {FRAME:acc#27.itm(1)} {FRAME:acc#27.itm(2)} {FRAME:acc#27.itm(3)} {FRAME:acc#27.itm(4)} -attr xrf 8462 -attr oid 183 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#25.itm(0)} -attr vt d
+load net {FRAME:acc#25.itm(1)} -attr vt d
+load net {FRAME:acc#25.itm(2)} -attr vt d
+load net {FRAME:acc#25.itm(3)} -attr vt d
+load netBundle {FRAME:acc#25.itm} 4 {FRAME:acc#25.itm(0)} {FRAME:acc#25.itm(1)} {FRAME:acc#25.itm(2)} {FRAME:acc#25.itm(3)} -attr xrf 8463 -attr oid 184 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {slc(blue#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#1.itm} 3 {slc(blue#2.sg1.sva)#1.itm(0)} {slc(blue#2.sg1.sva)#1.itm(1)} {slc(blue#2.sg1.sva)#1.itm(2)} -attr xrf 8464 -attr oid 185 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {FRAME:not#18.itm(0)} -attr vt d
+load net {FRAME:not#18.itm(1)} -attr vt d
+load net {FRAME:not#18.itm(2)} -attr vt d
+load netBundle {FRAME:not#18.itm} 3 {FRAME:not#18.itm(0)} {FRAME:not#18.itm(1)} {FRAME:not#18.itm(2)} -attr xrf 8465 -attr oid 186 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {slc(blue#2.sg1.sva)#3.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#3.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#3.itm} 3 {slc(blue#2.sg1.sva)#3.itm(0)} {slc(blue#2.sg1.sva)#3.itm(1)} {slc(blue#2.sg1.sva)#3.itm(2)} -attr xrf 8466 -attr oid 187 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {FRAME:acc#24.itm(0)} -attr vt d
+load net {FRAME:acc#24.itm(1)} -attr vt d
+load net {FRAME:acc#24.itm(2)} -attr vt d
+load net {FRAME:acc#24.itm(3)} -attr vt d
+load netBundle {FRAME:acc#24.itm} 4 {FRAME:acc#24.itm(0)} {FRAME:acc#24.itm(1)} {FRAME:acc#24.itm(2)} {FRAME:acc#24.itm(3)} -attr xrf 8467 -attr oid 188 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {conc#147.itm(0)} -attr vt d
+load net {conc#147.itm(1)} -attr vt d
+load net {conc#147.itm(2)} -attr vt d
+load netBundle {conc#147.itm} 3 {conc#147.itm(0)} {conc#147.itm(1)} {conc#147.itm(2)} -attr xrf 8468 -attr oid 189 -attr vt d -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {slc(blue#2.sg1.sva)#4.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#4.itm} 2 {slc(blue#2.sg1.sva)#4.itm(0)} {slc(blue#2.sg1.sva)#4.itm(1)} -attr xrf 8469 -attr oid 190 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#4.itm}
+load net {FRAME:acc#26.itm(0)} -attr vt d
+load net {FRAME:acc#26.itm(1)} -attr vt d
+load net {FRAME:acc#26.itm(2)} -attr vt d
+load net {FRAME:acc#26.itm(3)} -attr vt d
+load netBundle {FRAME:acc#26.itm} 4 {FRAME:acc#26.itm(0)} {FRAME:acc#26.itm(1)} {FRAME:acc#26.itm(2)} {FRAME:acc#26.itm(3)} -attr xrf 8470 -attr oid 191 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {slc(blue#2.sg1.sva)#5.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#5.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#5.itm} 3 {slc(blue#2.sg1.sva)#5.itm(0)} {slc(blue#2.sg1.sva)#5.itm(1)} {slc(blue#2.sg1.sva)#5.itm(2)} -attr xrf 8471 -attr oid 192 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {FRAME:not#17.itm(0)} -attr vt d
+load net {FRAME:not#17.itm(1)} -attr vt d
+load net {FRAME:not#17.itm(2)} -attr vt d
+load netBundle {FRAME:not#17.itm} 3 {FRAME:not#17.itm(0)} {FRAME:not#17.itm(1)} {FRAME:not#17.itm(2)} -attr xrf 8472 -attr oid 193 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {slc(blue#2.sg1.sva)#6.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#6.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#6.itm} 3 {slc(blue#2.sg1.sva)#6.itm(0)} {slc(blue#2.sg1.sva)#6.itm(1)} {slc(blue#2.sg1.sva)#6.itm(2)} -attr xrf 8473 -attr oid 194 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {ACC1:acc#44.itm(0)} -attr vt d
+load net {ACC1:acc#44.itm(1)} -attr vt d
+load net {ACC1:acc#44.itm(2)} -attr vt d
+load net {ACC1:acc#44.itm(3)} -attr vt d
+load net {ACC1:acc#44.itm(4)} -attr vt d
+load net {ACC1:acc#44.itm(5)} -attr vt d
+load net {ACC1:acc#44.itm(6)} -attr vt d
+load net {ACC1:acc#44.itm(7)} -attr vt d
+load net {ACC1:acc#44.itm(8)} -attr vt d
+load net {ACC1:acc#44.itm(9)} -attr vt d
+load net {ACC1:acc#44.itm(10)} -attr vt d
+load net {ACC1:acc#44.itm(11)} -attr vt d
+load net {ACC1:acc#44.itm(12)} -attr vt d
+load net {ACC1:acc#44.itm(13)} -attr vt d
+load net {ACC1:acc#44.itm(14)} -attr vt d
+load net {ACC1:acc#44.itm(15)} -attr vt d
+load netBundle {ACC1:acc#44.itm} 16 {ACC1:acc#44.itm(0)} {ACC1:acc#44.itm(1)} {ACC1:acc#44.itm(2)} {ACC1:acc#44.itm(3)} {ACC1:acc#44.itm(4)} {ACC1:acc#44.itm(5)} {ACC1:acc#44.itm(6)} {ACC1:acc#44.itm(7)} {ACC1:acc#44.itm(8)} {ACC1:acc#44.itm(9)} {ACC1:acc#44.itm(10)} {ACC1:acc#44.itm(11)} {ACC1:acc#44.itm(12)} {ACC1:acc#44.itm(13)} {ACC1:acc#44.itm(14)} {ACC1:acc#44.itm(15)} -attr xrf 8474 -attr oid 195 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:conc#47.itm(0)} -attr vt d
+load net {ACC1:conc#47.itm(1)} -attr vt d
+load net {ACC1:conc#47.itm(2)} -attr vt d
+load net {ACC1:conc#47.itm(3)} -attr vt d
+load net {ACC1:conc#47.itm(4)} -attr vt d
+load net {ACC1:conc#47.itm(5)} -attr vt d
+load net {ACC1:conc#47.itm(6)} -attr vt d
+load net {ACC1:conc#47.itm(7)} -attr vt d
+load net {ACC1:conc#47.itm(8)} -attr vt d
+load net {ACC1:conc#47.itm(9)} -attr vt d
+load net {ACC1:conc#47.itm(10)} -attr vt d
+load net {ACC1:conc#47.itm(11)} -attr vt d
+load net {ACC1:conc#47.itm(12)} -attr vt d
+load net {ACC1:conc#47.itm(13)} -attr vt d
+load net {ACC1:conc#47.itm(14)} -attr vt d
+load net {ACC1:conc#47.itm(15)} -attr vt d
+load netBundle {ACC1:conc#47.itm} 16 {ACC1:conc#47.itm(0)} {ACC1:conc#47.itm(1)} {ACC1:conc#47.itm(2)} {ACC1:conc#47.itm(3)} {ACC1:conc#47.itm(4)} {ACC1:conc#47.itm(5)} {ACC1:conc#47.itm(6)} {ACC1:conc#47.itm(7)} {ACC1:conc#47.itm(8)} {ACC1:conc#47.itm(9)} {ACC1:conc#47.itm(10)} {ACC1:conc#47.itm(11)} {ACC1:conc#47.itm(12)} {ACC1:conc#47.itm(13)} {ACC1:conc#47.itm(14)} {ACC1:conc#47.itm(15)} -attr xrf 8475 -attr oid 196 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(0)} -attr vt d
+load net {ACC1:acc#66.itm(1)} -attr vt d
+load net {ACC1:acc#66.itm(2)} -attr vt d
+load net {ACC1:acc#66.itm(3)} -attr vt d
+load net {ACC1:acc#66.itm(4)} -attr vt d
+load net {ACC1:acc#66.itm(5)} -attr vt d
+load net {ACC1:acc#66.itm(6)} -attr vt d
+load net {ACC1:acc#66.itm(7)} -attr vt d
+load net {ACC1:acc#66.itm(8)} -attr vt d
+load net {ACC1:acc#66.itm(9)} -attr vt d
+load net {ACC1:acc#66.itm(10)} -attr vt d
+load net {ACC1:acc#66.itm(11)} -attr vt d
+load net {ACC1:acc#66.itm(12)} -attr vt d
+load net {ACC1:acc#66.itm(13)} -attr vt d
+load net {ACC1:acc#66.itm(14)} -attr vt d
+load netBundle {ACC1:acc#66.itm} 15 {ACC1:acc#66.itm(0)} {ACC1:acc#66.itm(1)} {ACC1:acc#66.itm(2)} {ACC1:acc#66.itm(3)} {ACC1:acc#66.itm(4)} {ACC1:acc#66.itm(5)} {ACC1:acc#66.itm(6)} {ACC1:acc#66.itm(7)} {ACC1:acc#66.itm(8)} {ACC1:acc#66.itm(9)} {ACC1:acc#66.itm(10)} {ACC1:acc#66.itm(11)} {ACC1:acc#66.itm(12)} {ACC1:acc#66.itm(13)} {ACC1:acc#66.itm(14)} -attr xrf 8476 -attr oid 197 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {slc#2.itm(0)} -attr vt d
+load net {slc#2.itm(1)} -attr vt d
+load net {slc#2.itm(2)} -attr vt d
+load net {slc#2.itm(3)} -attr vt d
+load net {slc#2.itm(4)} -attr vt d
+load net {slc#2.itm(5)} -attr vt d
+load net {slc#2.itm(6)} -attr vt d
+load net {slc#2.itm(7)} -attr vt d
+load net {slc#2.itm(8)} -attr vt d
+load net {slc#2.itm(9)} -attr vt d
+load net {slc#2.itm(10)} -attr vt d
+load netBundle {slc#2.itm} 11 {slc#2.itm(0)} {slc#2.itm(1)} {slc#2.itm(2)} {slc#2.itm(3)} {slc#2.itm(4)} {slc#2.itm(5)} {slc#2.itm(6)} {slc#2.itm(7)} {slc#2.itm(8)} {slc#2.itm(9)} {slc#2.itm(10)} -attr xrf 8477 -attr oid 198 -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(0)} -attr vt d
+load net {acc#7.itm(1)} -attr vt d
+load net {acc#7.itm(2)} -attr vt d
+load net {acc#7.itm(3)} -attr vt d
+load net {acc#7.itm(4)} -attr vt d
+load net {acc#7.itm(5)} -attr vt d
+load net {acc#7.itm(6)} -attr vt d
+load net {acc#7.itm(7)} -attr vt d
+load net {acc#7.itm(8)} -attr vt d
+load net {acc#7.itm(9)} -attr vt d
+load net {acc#7.itm(10)} -attr vt d
+load net {acc#7.itm(11)} -attr vt d
+load netBundle {acc#7.itm} 12 {acc#7.itm(0)} {acc#7.itm(1)} {acc#7.itm(2)} {acc#7.itm(3)} {acc#7.itm(4)} {acc#7.itm(5)} {acc#7.itm(6)} {acc#7.itm(7)} {acc#7.itm(8)} {acc#7.itm(9)} {acc#7.itm(10)} {acc#7.itm(11)} -attr xrf 8478 -attr oid 199 -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {conc#148.itm(0)} -attr vt d
+load net {conc#148.itm(1)} -attr vt d
+load net {conc#148.itm(2)} -attr vt d
+load net {conc#148.itm(3)} -attr vt d
+load net {conc#148.itm(4)} -attr vt d
+load net {conc#148.itm(5)} -attr vt d
+load net {conc#148.itm(6)} -attr vt d
+load net {conc#148.itm(7)} -attr vt d
+load net {conc#148.itm(8)} -attr vt d
+load net {conc#148.itm(9)} -attr vt d
+load net {conc#148.itm(10)} -attr vt d
+load netBundle {conc#148.itm} 11 {conc#148.itm(0)} {conc#148.itm(1)} {conc#148.itm(2)} {conc#148.itm(3)} {conc#148.itm(4)} {conc#148.itm(5)} {conc#148.itm(6)} {conc#148.itm(7)} {conc#148.itm(8)} {conc#148.itm(9)} {conc#148.itm(10)} -attr xrf 8479 -attr oid 200 -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(0)} -attr vt d
+load net {ACC2:not#3.itm(1)} -attr vt d
+load net {ACC2:not#3.itm(2)} -attr vt d
+load net {ACC2:not#3.itm(3)} -attr vt d
+load net {ACC2:not#3.itm(4)} -attr vt d
+load net {ACC2:not#3.itm(5)} -attr vt d
+load net {ACC2:not#3.itm(6)} -attr vt d
+load net {ACC2:not#3.itm(7)} -attr vt d
+load net {ACC2:not#3.itm(8)} -attr vt d
+load net {ACC2:not#3.itm(9)} -attr vt d
+load netBundle {ACC2:not#3.itm} 10 {ACC2:not#3.itm(0)} {ACC2:not#3.itm(1)} {ACC2:not#3.itm(2)} {ACC2:not#3.itm(3)} {ACC2:not#3.itm(4)} {ACC2:not#3.itm(5)} {ACC2:not#3.itm(6)} {ACC2:not#3.itm(7)} {ACC2:not#3.itm(8)} {ACC2:not#3.itm(9)} -attr xrf 8480 -attr oid 201 -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr xrf 8481 -attr oid 202 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {conc#149.itm(0)} -attr vt d
+load net {conc#149.itm(1)} -attr vt d
+load net {conc#149.itm(2)} -attr vt d
+load net {conc#149.itm(3)} -attr vt d
+load net {conc#149.itm(4)} -attr vt d
+load net {conc#149.itm(5)} -attr vt d
+load net {conc#149.itm(6)} -attr vt d
+load net {conc#149.itm(7)} -attr vt d
+load net {conc#149.itm(8)} -attr vt d
+load net {conc#149.itm(9)} -attr vt d
+load net {conc#149.itm(10)} -attr vt d
+load netBundle {conc#149.itm} 11 {conc#149.itm(0)} {conc#149.itm(1)} {conc#149.itm(2)} {conc#149.itm(3)} {conc#149.itm(4)} {conc#149.itm(5)} {conc#149.itm(6)} {conc#149.itm(7)} {conc#149.itm(8)} {conc#149.itm(9)} {conc#149.itm(10)} -attr xrf 8482 -attr oid 203 -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(9)} -attr xrf 8483 -attr oid 204 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {slc(g(2).sva#1).itm(0)} -attr vt d
+load net {slc(g(2).sva#1).itm(1)} -attr vt d
+load net {slc(g(2).sva#1).itm(2)} -attr vt d
+load net {slc(g(2).sva#1).itm(3)} -attr vt d
+load net {slc(g(2).sva#1).itm(4)} -attr vt d
+load net {slc(g(2).sva#1).itm(5)} -attr vt d
+load net {slc(g(2).sva#1).itm(6)} -attr vt d
+load net {slc(g(2).sva#1).itm(7)} -attr vt d
+load net {slc(g(2).sva#1).itm(8)} -attr vt d
+load net {slc(g(2).sva#1).itm(9)} -attr vt d
+load net {slc(g(2).sva#1).itm(10)} -attr vt d
+load net {slc(g(2).sva#1).itm(11)} -attr vt d
+load net {slc(g(2).sva#1).itm(12)} -attr vt d
+load net {slc(g(2).sva#1).itm(13)} -attr vt d
+load net {slc(g(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(g(2).sva#1).itm} 15 {slc(g(2).sva#1).itm(0)} {slc(g(2).sva#1).itm(1)} {slc(g(2).sva#1).itm(2)} {slc(g(2).sva#1).itm(3)} {slc(g(2).sva#1).itm(4)} {slc(g(2).sva#1).itm(5)} {slc(g(2).sva#1).itm(6)} {slc(g(2).sva#1).itm(7)} {slc(g(2).sva#1).itm(8)} {slc(g(2).sva#1).itm(9)} {slc(g(2).sva#1).itm(10)} {slc(g(2).sva#1).itm(11)} {slc(g(2).sva#1).itm(12)} {slc(g(2).sva#1).itm(13)} {slc(g(2).sva#1).itm(14)} -attr xrf 8484 -attr oid 205 -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {conc#150.itm(0)} -attr vt d
+load net {conc#150.itm(1)} -attr vt d
+load netBundle {conc#150.itm} 2 {conc#150.itm(0)} {conc#150.itm(1)} -attr xrf 8485 -attr oid 206 -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {FRAME:acc#16.itm(0)} -attr vt d
+load net {FRAME:acc#16.itm(1)} -attr vt d
+load net {FRAME:acc#16.itm(2)} -attr vt d
+load net {FRAME:acc#16.itm(3)} -attr vt d
+load net {FRAME:acc#16.itm(4)} -attr vt d
+load net {FRAME:acc#16.itm(5)} -attr vt d
+load netBundle {FRAME:acc#16.itm} 6 {FRAME:acc#16.itm(0)} {FRAME:acc#16.itm(1)} {FRAME:acc#16.itm(2)} {FRAME:acc#16.itm(3)} {FRAME:acc#16.itm(4)} {FRAME:acc#16.itm(5)} -attr xrf 8486 -attr oid 207 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#15.itm(0)} -attr vt d
+load net {FRAME:acc#15.itm(1)} -attr vt d
+load net {FRAME:acc#15.itm(2)} -attr vt d
+load net {FRAME:acc#15.itm(3)} -attr vt d
+load net {FRAME:acc#15.itm(4)} -attr vt d
+load netBundle {FRAME:acc#15.itm} 5 {FRAME:acc#15.itm(0)} {FRAME:acc#15.itm(1)} {FRAME:acc#15.itm(2)} {FRAME:acc#15.itm(3)} {FRAME:acc#15.itm(4)} -attr xrf 8487 -attr oid 208 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#13.itm(0)} -attr vt d
+load net {FRAME:acc#13.itm(1)} -attr vt d
+load net {FRAME:acc#13.itm(2)} -attr vt d
+load net {FRAME:acc#13.itm(3)} -attr vt d
+load netBundle {FRAME:acc#13.itm} 4 {FRAME:acc#13.itm(0)} {FRAME:acc#13.itm(1)} {FRAME:acc#13.itm(2)} {FRAME:acc#13.itm(3)} -attr xrf 8488 -attr oid 209 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {slc(green#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#1.itm} 3 {slc(green#2.sg1.sva)#1.itm(0)} {slc(green#2.sg1.sva)#1.itm(1)} {slc(green#2.sg1.sva)#1.itm(2)} -attr xrf 8489 -attr oid 210 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {FRAME:not#10.itm(0)} -attr vt d
+load net {FRAME:not#10.itm(1)} -attr vt d
+load net {FRAME:not#10.itm(2)} -attr vt d
+load netBundle {FRAME:not#10.itm} 3 {FRAME:not#10.itm(0)} {FRAME:not#10.itm(1)} {FRAME:not#10.itm(2)} -attr xrf 8490 -attr oid 211 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {slc(green#2.sg1.sva)#3.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#3.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#3.itm} 3 {slc(green#2.sg1.sva)#3.itm(0)} {slc(green#2.sg1.sva)#3.itm(1)} {slc(green#2.sg1.sva)#3.itm(2)} -attr xrf 8491 -attr oid 212 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {FRAME:acc#12.itm(0)} -attr vt d
+load net {FRAME:acc#12.itm(1)} -attr vt d
+load net {FRAME:acc#12.itm(2)} -attr vt d
+load net {FRAME:acc#12.itm(3)} -attr vt d
+load netBundle {FRAME:acc#12.itm} 4 {FRAME:acc#12.itm(0)} {FRAME:acc#12.itm(1)} {FRAME:acc#12.itm(2)} {FRAME:acc#12.itm(3)} -attr xrf 8492 -attr oid 213 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {conc#151.itm(0)} -attr vt d
+load net {conc#151.itm(1)} -attr vt d
+load net {conc#151.itm(2)} -attr vt d
+load netBundle {conc#151.itm} 3 {conc#151.itm(0)} {conc#151.itm(1)} {conc#151.itm(2)} -attr xrf 8493 -attr oid 214 -attr vt d -attr @path {/sobel/sobel:core/conc#151.itm}
+load net {slc(green#2.sg1.sva)#4.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#4.itm} 2 {slc(green#2.sg1.sva)#4.itm(0)} {slc(green#2.sg1.sva)#4.itm(1)} -attr xrf 8494 -attr oid 215 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#4.itm}
+load net {FRAME:acc#14.itm(0)} -attr vt d
+load net {FRAME:acc#14.itm(1)} -attr vt d
+load net {FRAME:acc#14.itm(2)} -attr vt d
+load net {FRAME:acc#14.itm(3)} -attr vt d
+load netBundle {FRAME:acc#14.itm} 4 {FRAME:acc#14.itm(0)} {FRAME:acc#14.itm(1)} {FRAME:acc#14.itm(2)} {FRAME:acc#14.itm(3)} -attr xrf 8495 -attr oid 216 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {slc(green#2.sg1.sva)#5.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#5.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#5.itm} 3 {slc(green#2.sg1.sva)#5.itm(0)} {slc(green#2.sg1.sva)#5.itm(1)} {slc(green#2.sg1.sva)#5.itm(2)} -attr xrf 8496 -attr oid 217 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {FRAME:not#9.itm(0)} -attr vt d
+load net {FRAME:not#9.itm(1)} -attr vt d
+load net {FRAME:not#9.itm(2)} -attr vt d
+load netBundle {FRAME:not#9.itm} 3 {FRAME:not#9.itm(0)} {FRAME:not#9.itm(1)} {FRAME:not#9.itm(2)} -attr xrf 8497 -attr oid 218 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {slc(green#2.sg1.sva)#6.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#6.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#6.itm} 3 {slc(green#2.sg1.sva)#6.itm(0)} {slc(green#2.sg1.sva)#6.itm(1)} {slc(green#2.sg1.sva)#6.itm(2)} -attr xrf 8498 -attr oid 219 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {FRAME:for:mux#10.itm(0)} -attr vt d
+load net {FRAME:for:mux#10.itm(1)} -attr vt d
+load net {FRAME:for:mux#10.itm(2)} -attr vt d
+load net {FRAME:for:mux#10.itm(3)} -attr vt d
+load net {FRAME:for:mux#10.itm(4)} -attr vt d
+load net {FRAME:for:mux#10.itm(5)} -attr vt d
+load net {FRAME:for:mux#10.itm(6)} -attr vt d
+load net {FRAME:for:mux#10.itm(7)} -attr vt d
+load net {FRAME:for:mux#10.itm(8)} -attr vt d
+load net {FRAME:for:mux#10.itm(9)} -attr vt d
+load net {FRAME:for:mux#10.itm(10)} -attr vt d
+load net {FRAME:for:mux#10.itm(11)} -attr vt d
+load net {FRAME:for:mux#10.itm(12)} -attr vt d
+load net {FRAME:for:mux#10.itm(13)} -attr vt d
+load net {FRAME:for:mux#10.itm(14)} -attr vt d
+load net {FRAME:for:mux#10.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#10.itm} 16 {FRAME:for:mux#10.itm(0)} {FRAME:for:mux#10.itm(1)} {FRAME:for:mux#10.itm(2)} {FRAME:for:mux#10.itm(3)} {FRAME:for:mux#10.itm(4)} {FRAME:for:mux#10.itm(5)} {FRAME:for:mux#10.itm(6)} {FRAME:for:mux#10.itm(7)} {FRAME:for:mux#10.itm(8)} {FRAME:for:mux#10.itm(9)} {FRAME:for:mux#10.itm(10)} {FRAME:for:mux#10.itm(11)} {FRAME:for:mux#10.itm(12)} {FRAME:for:mux#10.itm(13)} {FRAME:for:mux#10.itm(14)} {FRAME:for:mux#10.itm(15)} -attr xrf 8499 -attr oid 220 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:exs#25.itm(0)} -attr vt d
+load net {FRAME:for:exs#25.itm(1)} -attr vt d
+load net {FRAME:for:exs#25.itm(2)} -attr vt d
+load net {FRAME:for:exs#25.itm(3)} -attr vt d
+load net {FRAME:for:exs#25.itm(4)} -attr vt d
+load net {FRAME:for:exs#25.itm(5)} -attr vt d
+load net {FRAME:for:exs#25.itm(6)} -attr vt d
+load net {FRAME:for:exs#25.itm(7)} -attr vt d
+load net {FRAME:for:exs#25.itm(8)} -attr vt d
+load net {FRAME:for:exs#25.itm(9)} -attr vt d
+load net {FRAME:for:exs#25.itm(10)} -attr vt d
+load net {FRAME:for:exs#25.itm(11)} -attr vt d
+load net {FRAME:for:exs#25.itm(12)} -attr vt d
+load net {FRAME:for:exs#25.itm(13)} -attr vt d
+load net {FRAME:for:exs#25.itm(14)} -attr vt d
+load net {FRAME:for:exs#25.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#25.itm} 16 {FRAME:for:exs#25.itm(0)} {FRAME:for:exs#25.itm(1)} {FRAME:for:exs#25.itm(2)} {FRAME:for:exs#25.itm(3)} {FRAME:for:exs#25.itm(4)} {FRAME:for:exs#25.itm(5)} {FRAME:for:exs#25.itm(6)} {FRAME:for:exs#25.itm(7)} {FRAME:for:exs#25.itm(8)} {FRAME:for:exs#25.itm(9)} {FRAME:for:exs#25.itm(10)} {FRAME:for:exs#25.itm(11)} {FRAME:for:exs#25.itm(12)} {FRAME:for:exs#25.itm(13)} {FRAME:for:exs#25.itm(14)} {FRAME:for:exs#25.itm(15)} -attr xrf 8500 -attr oid 221 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:slc#5.itm(0)} -attr vt d
+load net {ACC1:slc#5.itm(1)} -attr vt d
+load net {ACC1:slc#5.itm(2)} -attr vt d
+load net {ACC1:slc#5.itm(3)} -attr vt d
+load net {ACC1:slc#5.itm(4)} -attr vt d
+load net {ACC1:slc#5.itm(5)} -attr vt d
+load net {ACC1:slc#5.itm(6)} -attr vt d
+load net {ACC1:slc#5.itm(7)} -attr vt d
+load net {ACC1:slc#5.itm(8)} -attr vt d
+load net {ACC1:slc#5.itm(9)} -attr vt d
+load net {ACC1:slc#5.itm(10)} -attr vt d
+load netBundle {ACC1:slc#5.itm} 11 {ACC1:slc#5.itm(0)} {ACC1:slc#5.itm(1)} {ACC1:slc#5.itm(2)} {ACC1:slc#5.itm(3)} {ACC1:slc#5.itm(4)} {ACC1:slc#5.itm(5)} {ACC1:slc#5.itm(6)} {ACC1:slc#5.itm(7)} {ACC1:slc#5.itm(8)} {ACC1:slc#5.itm(9)} {ACC1:slc#5.itm(10)} -attr xrf 8501 -attr oid 222 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#5.itm}
+load net {ACC1:acc#52.itm(0)} -attr vt d
+load net {ACC1:acc#52.itm(1)} -attr vt d
+load net {ACC1:acc#52.itm(2)} -attr vt d
+load net {ACC1:acc#52.itm(3)} -attr vt d
+load net {ACC1:acc#52.itm(4)} -attr vt d
+load net {ACC1:acc#52.itm(5)} -attr vt d
+load net {ACC1:acc#52.itm(6)} -attr vt d
+load net {ACC1:acc#52.itm(7)} -attr vt d
+load net {ACC1:acc#52.itm(8)} -attr vt d
+load net {ACC1:acc#52.itm(9)} -attr vt d
+load net {ACC1:acc#52.itm(10)} -attr vt d
+load net {ACC1:acc#52.itm(11)} -attr vt d
+load netBundle {ACC1:acc#52.itm} 12 {ACC1:acc#52.itm(0)} {ACC1:acc#52.itm(1)} {ACC1:acc#52.itm(2)} {ACC1:acc#52.itm(3)} {ACC1:acc#52.itm(4)} {ACC1:acc#52.itm(5)} {ACC1:acc#52.itm(6)} {ACC1:acc#52.itm(7)} {ACC1:acc#52.itm(8)} {ACC1:acc#52.itm(9)} {ACC1:acc#52.itm(10)} {ACC1:acc#52.itm(11)} -attr xrf 8502 -attr oid 223 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {conc#152.itm(0)} -attr vt d
+load net {conc#152.itm(1)} -attr vt d
+load net {conc#152.itm(2)} -attr vt d
+load net {conc#152.itm(3)} -attr vt d
+load net {conc#152.itm(4)} -attr vt d
+load net {conc#152.itm(5)} -attr vt d
+load net {conc#152.itm(6)} -attr vt d
+load net {conc#152.itm(7)} -attr vt d
+load net {conc#152.itm(8)} -attr vt d
+load net {conc#152.itm(9)} -attr vt d
+load net {conc#152.itm(10)} -attr vt d
+load netBundle {conc#152.itm} 11 {conc#152.itm(0)} {conc#152.itm(1)} {conc#152.itm(2)} {conc#152.itm(3)} {conc#152.itm(4)} {conc#152.itm(5)} {conc#152.itm(6)} {conc#152.itm(7)} {conc#152.itm(8)} {conc#152.itm(9)} {conc#152.itm(10)} -attr xrf 8503 -attr oid 224 -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(0)} -attr vt d
+load net {ACC1:not#14.itm(1)} -attr vt d
+load net {ACC1:not#14.itm(2)} -attr vt d
+load net {ACC1:not#14.itm(3)} -attr vt d
+load net {ACC1:not#14.itm(4)} -attr vt d
+load net {ACC1:not#14.itm(5)} -attr vt d
+load net {ACC1:not#14.itm(6)} -attr vt d
+load net {ACC1:not#14.itm(7)} -attr vt d
+load net {ACC1:not#14.itm(8)} -attr vt d
+load net {ACC1:not#14.itm(9)} -attr vt d
+load netBundle {ACC1:not#14.itm} 10 {ACC1:not#14.itm(0)} {ACC1:not#14.itm(1)} {ACC1:not#14.itm(2)} {ACC1:not#14.itm(3)} {ACC1:not#14.itm(4)} {ACC1:not#14.itm(5)} {ACC1:not#14.itm(6)} {ACC1:not#14.itm(7)} {ACC1:not#14.itm(8)} {ACC1:not#14.itm(9)} -attr xrf 8504 -attr oid 225 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {slc(regs.regs(0).sva#1).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#1).itm} 10 {slc(regs.regs(0).sva#1).itm(0)} {slc(regs.regs(0).sva#1).itm(1)} {slc(regs.regs(0).sva#1).itm(2)} {slc(regs.regs(0).sva#1).itm(3)} {slc(regs.regs(0).sva#1).itm(4)} {slc(regs.regs(0).sva#1).itm(5)} {slc(regs.regs(0).sva#1).itm(6)} {slc(regs.regs(0).sva#1).itm(7)} {slc(regs.regs(0).sva#1).itm(8)} {slc(regs.regs(0).sva#1).itm(9)} -attr xrf 8505 -attr oid 226 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {conc#153.itm(0)} -attr vt d
+load net {conc#153.itm(1)} -attr vt d
+load net {conc#153.itm(2)} -attr vt d
+load net {conc#153.itm(3)} -attr vt d
+load net {conc#153.itm(4)} -attr vt d
+load net {conc#153.itm(5)} -attr vt d
+load net {conc#153.itm(6)} -attr vt d
+load net {conc#153.itm(7)} -attr vt d
+load net {conc#153.itm(8)} -attr vt d
+load net {conc#153.itm(9)} -attr vt d
+load net {conc#153.itm(10)} -attr vt d
+load netBundle {conc#153.itm} 11 {conc#153.itm(0)} {conc#153.itm(1)} {conc#153.itm(2)} {conc#153.itm(3)} {conc#153.itm(4)} {conc#153.itm(5)} {conc#153.itm(6)} {conc#153.itm(7)} {conc#153.itm(8)} {conc#153.itm(9)} {conc#153.itm(10)} -attr xrf 8506 -attr oid 227 -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {slc(regs.regs(1).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva).itm} 10 {slc(regs.regs(1).sva).itm(0)} {slc(regs.regs(1).sva).itm(1)} {slc(regs.regs(1).sva).itm(2)} {slc(regs.regs(1).sva).itm(3)} {slc(regs.regs(1).sva).itm(4)} {slc(regs.regs(1).sva).itm(5)} {slc(regs.regs(1).sva).itm(6)} {slc(regs.regs(1).sva).itm(7)} {slc(regs.regs(1).sva).itm(8)} {slc(regs.regs(1).sva).itm(9)} -attr xrf 8507 -attr oid 228 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {FRAME:for:mul#8.itm(0)} -attr vt d
+load net {FRAME:for:mul#8.itm(1)} -attr vt d
+load net {FRAME:for:mul#8.itm(2)} -attr vt d
+load net {FRAME:for:mul#8.itm(3)} -attr vt d
+load net {FRAME:for:mul#8.itm(4)} -attr vt d
+load net {FRAME:for:mul#8.itm(5)} -attr vt d
+load net {FRAME:for:mul#8.itm(6)} -attr vt d
+load net {FRAME:for:mul#8.itm(7)} -attr vt d
+load net {FRAME:for:mul#8.itm(8)} -attr vt d
+load net {FRAME:for:mul#8.itm(9)} -attr vt d
+load net {FRAME:for:mul#8.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#8.itm} 11 {FRAME:for:mul#8.itm(0)} {FRAME:for:mul#8.itm(1)} {FRAME:for:mul#8.itm(2)} {FRAME:for:mul#8.itm(3)} {FRAME:for:mul#8.itm(4)} {FRAME:for:mul#8.itm(5)} {FRAME:for:mul#8.itm(6)} {FRAME:for:mul#8.itm(7)} {FRAME:for:mul#8.itm(8)} {FRAME:for:mul#8.itm(9)} {FRAME:for:mul#8.itm(10)} -attr xrf 8508 -attr oid 229 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {regs.operator[]#17:mux.itm(0)} -attr vt d
+load net {regs.operator[]#17:mux.itm(1)} -attr vt d
+load net {regs.operator[]#17:mux.itm(2)} -attr vt d
+load net {regs.operator[]#17:mux.itm(3)} -attr vt d
+load net {regs.operator[]#17:mux.itm(4)} -attr vt d
+load net {regs.operator[]#17:mux.itm(5)} -attr vt d
+load net {regs.operator[]#17:mux.itm(6)} -attr vt d
+load net {regs.operator[]#17:mux.itm(7)} -attr vt d
+load net {regs.operator[]#17:mux.itm(8)} -attr vt d
+load net {regs.operator[]#17:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#17:mux.itm} 10 {regs.operator[]#17:mux.itm(0)} {regs.operator[]#17:mux.itm(1)} {regs.operator[]#17:mux.itm(2)} {regs.operator[]#17:mux.itm(3)} {regs.operator[]#17:mux.itm(4)} {regs.operator[]#17:mux.itm(5)} {regs.operator[]#17:mux.itm(6)} {regs.operator[]#17:mux.itm(7)} {regs.operator[]#17:mux.itm(8)} {regs.operator[]#17:mux.itm(9)} -attr xrf 8509 -attr oid 230 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(9)} -attr xrf 8510 -attr oid 231 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0).itm} 10 {slc(regs.regs(1).sva.dfm:mx0).itm(0)} {slc(regs.regs(1).sva.dfm:mx0).itm(1)} {slc(regs.regs(1).sva.dfm:mx0).itm(2)} {slc(regs.regs(1).sva.dfm:mx0).itm(3)} {slc(regs.regs(1).sva.dfm:mx0).itm(4)} {slc(regs.regs(1).sva.dfm:mx0).itm(5)} {slc(regs.regs(1).sva.dfm:mx0).itm(6)} {slc(regs.regs(1).sva.dfm:mx0).itm(7)} {slc(regs.regs(1).sva.dfm:mx0).itm(8)} {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr xrf 8511 -attr oid 232 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr xrf 8512 -attr oid 233 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {FRAME:for:mux#9.itm(0)} -attr vt d
+load net {FRAME:for:mux#9.itm(1)} -attr vt d
+load net {FRAME:for:mux#9.itm(2)} -attr vt d
+load net {FRAME:for:mux#9.itm(3)} -attr vt d
+load net {FRAME:for:mux#9.itm(4)} -attr vt d
+load net {FRAME:for:mux#9.itm(5)} -attr vt d
+load net {FRAME:for:mux#9.itm(6)} -attr vt d
+load net {FRAME:for:mux#9.itm(7)} -attr vt d
+load net {FRAME:for:mux#9.itm(8)} -attr vt d
+load net {FRAME:for:mux#9.itm(9)} -attr vt d
+load net {FRAME:for:mux#9.itm(10)} -attr vt d
+load net {FRAME:for:mux#9.itm(11)} -attr vt d
+load net {FRAME:for:mux#9.itm(12)} -attr vt d
+load net {FRAME:for:mux#9.itm(13)} -attr vt d
+load net {FRAME:for:mux#9.itm(14)} -attr vt d
+load net {FRAME:for:mux#9.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#9.itm} 16 {FRAME:for:mux#9.itm(0)} {FRAME:for:mux#9.itm(1)} {FRAME:for:mux#9.itm(2)} {FRAME:for:mux#9.itm(3)} {FRAME:for:mux#9.itm(4)} {FRAME:for:mux#9.itm(5)} {FRAME:for:mux#9.itm(6)} {FRAME:for:mux#9.itm(7)} {FRAME:for:mux#9.itm(8)} {FRAME:for:mux#9.itm(9)} {FRAME:for:mux#9.itm(10)} {FRAME:for:mux#9.itm(11)} {FRAME:for:mux#9.itm(12)} {FRAME:for:mux#9.itm(13)} {FRAME:for:mux#9.itm(14)} {FRAME:for:mux#9.itm(15)} -attr xrf 8513 -attr oid 234 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:exs#22.itm(0)} -attr vt d
+load net {FRAME:for:exs#22.itm(1)} -attr vt d
+load net {FRAME:for:exs#22.itm(2)} -attr vt d
+load net {FRAME:for:exs#22.itm(3)} -attr vt d
+load net {FRAME:for:exs#22.itm(4)} -attr vt d
+load net {FRAME:for:exs#22.itm(5)} -attr vt d
+load net {FRAME:for:exs#22.itm(6)} -attr vt d
+load net {FRAME:for:exs#22.itm(7)} -attr vt d
+load net {FRAME:for:exs#22.itm(8)} -attr vt d
+load net {FRAME:for:exs#22.itm(9)} -attr vt d
+load net {FRAME:for:exs#22.itm(10)} -attr vt d
+load net {FRAME:for:exs#22.itm(11)} -attr vt d
+load net {FRAME:for:exs#22.itm(12)} -attr vt d
+load net {FRAME:for:exs#22.itm(13)} -attr vt d
+load net {FRAME:for:exs#22.itm(14)} -attr vt d
+load net {FRAME:for:exs#22.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#22.itm} 16 {FRAME:for:exs#22.itm(0)} {FRAME:for:exs#22.itm(1)} {FRAME:for:exs#22.itm(2)} {FRAME:for:exs#22.itm(3)} {FRAME:for:exs#22.itm(4)} {FRAME:for:exs#22.itm(5)} {FRAME:for:exs#22.itm(6)} {FRAME:for:exs#22.itm(7)} {FRAME:for:exs#22.itm(8)} {FRAME:for:exs#22.itm(9)} {FRAME:for:exs#22.itm(10)} {FRAME:for:exs#22.itm(11)} {FRAME:for:exs#22.itm(12)} {FRAME:for:exs#22.itm(13)} {FRAME:for:exs#22.itm(14)} {FRAME:for:exs#22.itm(15)} -attr xrf 8514 -attr oid 235 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:slc#2.itm(0)} -attr vt d
+load net {ACC1:slc#2.itm(1)} -attr vt d
+load net {ACC1:slc#2.itm(2)} -attr vt d
+load net {ACC1:slc#2.itm(3)} -attr vt d
+load net {ACC1:slc#2.itm(4)} -attr vt d
+load net {ACC1:slc#2.itm(5)} -attr vt d
+load net {ACC1:slc#2.itm(6)} -attr vt d
+load net {ACC1:slc#2.itm(7)} -attr vt d
+load net {ACC1:slc#2.itm(8)} -attr vt d
+load net {ACC1:slc#2.itm(9)} -attr vt d
+load net {ACC1:slc#2.itm(10)} -attr vt d
+load netBundle {ACC1:slc#2.itm} 11 {ACC1:slc#2.itm(0)} {ACC1:slc#2.itm(1)} {ACC1:slc#2.itm(2)} {ACC1:slc#2.itm(3)} {ACC1:slc#2.itm(4)} {ACC1:slc#2.itm(5)} {ACC1:slc#2.itm(6)} {ACC1:slc#2.itm(7)} {ACC1:slc#2.itm(8)} {ACC1:slc#2.itm(9)} {ACC1:slc#2.itm(10)} -attr xrf 8515 -attr oid 236 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#49.itm(0)} -attr vt d
+load net {ACC1:acc#49.itm(1)} -attr vt d
+load net {ACC1:acc#49.itm(2)} -attr vt d
+load net {ACC1:acc#49.itm(3)} -attr vt d
+load net {ACC1:acc#49.itm(4)} -attr vt d
+load net {ACC1:acc#49.itm(5)} -attr vt d
+load net {ACC1:acc#49.itm(6)} -attr vt d
+load net {ACC1:acc#49.itm(7)} -attr vt d
+load net {ACC1:acc#49.itm(8)} -attr vt d
+load net {ACC1:acc#49.itm(9)} -attr vt d
+load net {ACC1:acc#49.itm(10)} -attr vt d
+load net {ACC1:acc#49.itm(11)} -attr vt d
+load netBundle {ACC1:acc#49.itm} 12 {ACC1:acc#49.itm(0)} {ACC1:acc#49.itm(1)} {ACC1:acc#49.itm(2)} {ACC1:acc#49.itm(3)} {ACC1:acc#49.itm(4)} {ACC1:acc#49.itm(5)} {ACC1:acc#49.itm(6)} {ACC1:acc#49.itm(7)} {ACC1:acc#49.itm(8)} {ACC1:acc#49.itm(9)} {ACC1:acc#49.itm(10)} {ACC1:acc#49.itm(11)} -attr xrf 8516 -attr oid 237 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {conc#154.itm(0)} -attr vt d
+load net {conc#154.itm(1)} -attr vt d
+load net {conc#154.itm(2)} -attr vt d
+load net {conc#154.itm(3)} -attr vt d
+load net {conc#154.itm(4)} -attr vt d
+load net {conc#154.itm(5)} -attr vt d
+load net {conc#154.itm(6)} -attr vt d
+load net {conc#154.itm(7)} -attr vt d
+load net {conc#154.itm(8)} -attr vt d
+load net {conc#154.itm(9)} -attr vt d
+load net {conc#154.itm(10)} -attr vt d
+load netBundle {conc#154.itm} 11 {conc#154.itm(0)} {conc#154.itm(1)} {conc#154.itm(2)} {conc#154.itm(3)} {conc#154.itm(4)} {conc#154.itm(5)} {conc#154.itm(6)} {conc#154.itm(7)} {conc#154.itm(8)} {conc#154.itm(9)} {conc#154.itm(10)} -attr xrf 8517 -attr oid 238 -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(0)} -attr vt d
+load net {ACC1:not#16.itm(1)} -attr vt d
+load net {ACC1:not#16.itm(2)} -attr vt d
+load net {ACC1:not#16.itm(3)} -attr vt d
+load net {ACC1:not#16.itm(4)} -attr vt d
+load net {ACC1:not#16.itm(5)} -attr vt d
+load net {ACC1:not#16.itm(6)} -attr vt d
+load net {ACC1:not#16.itm(7)} -attr vt d
+load net {ACC1:not#16.itm(8)} -attr vt d
+load net {ACC1:not#16.itm(9)} -attr vt d
+load netBundle {ACC1:not#16.itm} 10 {ACC1:not#16.itm(0)} {ACC1:not#16.itm(1)} {ACC1:not#16.itm(2)} {ACC1:not#16.itm(3)} {ACC1:not#16.itm(4)} {ACC1:not#16.itm(5)} {ACC1:not#16.itm(6)} {ACC1:not#16.itm(7)} {ACC1:not#16.itm(8)} {ACC1:not#16.itm(9)} -attr xrf 8518 -attr oid 239 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {slc(regs.regs(0).sva#4).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#4).itm} 10 {slc(regs.regs(0).sva#4).itm(0)} {slc(regs.regs(0).sva#4).itm(1)} {slc(regs.regs(0).sva#4).itm(2)} {slc(regs.regs(0).sva#4).itm(3)} {slc(regs.regs(0).sva#4).itm(4)} {slc(regs.regs(0).sva#4).itm(5)} {slc(regs.regs(0).sva#4).itm(6)} {slc(regs.regs(0).sva#4).itm(7)} {slc(regs.regs(0).sva#4).itm(8)} {slc(regs.regs(0).sva#4).itm(9)} -attr xrf 8519 -attr oid 240 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {conc#155.itm(0)} -attr vt d
+load net {conc#155.itm(1)} -attr vt d
+load net {conc#155.itm(2)} -attr vt d
+load net {conc#155.itm(3)} -attr vt d
+load net {conc#155.itm(4)} -attr vt d
+load net {conc#155.itm(5)} -attr vt d
+load net {conc#155.itm(6)} -attr vt d
+load net {conc#155.itm(7)} -attr vt d
+load net {conc#155.itm(8)} -attr vt d
+load net {conc#155.itm(9)} -attr vt d
+load net {conc#155.itm(10)} -attr vt d
+load netBundle {conc#155.itm} 11 {conc#155.itm(0)} {conc#155.itm(1)} {conc#155.itm(2)} {conc#155.itm(3)} {conc#155.itm(4)} {conc#155.itm(5)} {conc#155.itm(6)} {conc#155.itm(7)} {conc#155.itm(8)} {conc#155.itm(9)} {conc#155.itm(10)} -attr xrf 8520 -attr oid 241 -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {slc(regs.regs(1).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#3.itm} 10 {slc(regs.regs(1).sva)#3.itm(0)} {slc(regs.regs(1).sva)#3.itm(1)} {slc(regs.regs(1).sva)#3.itm(2)} {slc(regs.regs(1).sva)#3.itm(3)} {slc(regs.regs(1).sva)#3.itm(4)} {slc(regs.regs(1).sva)#3.itm(5)} {slc(regs.regs(1).sva)#3.itm(6)} {slc(regs.regs(1).sva)#3.itm(7)} {slc(regs.regs(1).sva)#3.itm(8)} {slc(regs.regs(1).sva)#3.itm(9)} -attr xrf 8521 -attr oid 242 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {FRAME:for:mul#2.itm(0)} -attr vt d
+load net {FRAME:for:mul#2.itm(1)} -attr vt d
+load net {FRAME:for:mul#2.itm(2)} -attr vt d
+load net {FRAME:for:mul#2.itm(3)} -attr vt d
+load net {FRAME:for:mul#2.itm(4)} -attr vt d
+load net {FRAME:for:mul#2.itm(5)} -attr vt d
+load net {FRAME:for:mul#2.itm(6)} -attr vt d
+load net {FRAME:for:mul#2.itm(7)} -attr vt d
+load net {FRAME:for:mul#2.itm(8)} -attr vt d
+load net {FRAME:for:mul#2.itm(9)} -attr vt d
+load net {FRAME:for:mul#2.itm(10)} -attr vt d
+load net {FRAME:for:mul#2.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul#2.itm} 12 {FRAME:for:mul#2.itm(0)} {FRAME:for:mul#2.itm(1)} {FRAME:for:mul#2.itm(2)} {FRAME:for:mul#2.itm(3)} {FRAME:for:mul#2.itm(4)} {FRAME:for:mul#2.itm(5)} {FRAME:for:mul#2.itm(6)} {FRAME:for:mul#2.itm(7)} {FRAME:for:mul#2.itm(8)} {FRAME:for:mul#2.itm(9)} {FRAME:for:mul#2.itm(10)} {FRAME:for:mul#2.itm(11)} -attr xrf 8522 -attr oid 243 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {regs.operator[]#11:mux.itm(0)} -attr vt d
+load net {regs.operator[]#11:mux.itm(1)} -attr vt d
+load net {regs.operator[]#11:mux.itm(2)} -attr vt d
+load net {regs.operator[]#11:mux.itm(3)} -attr vt d
+load net {regs.operator[]#11:mux.itm(4)} -attr vt d
+load net {regs.operator[]#11:mux.itm(5)} -attr vt d
+load net {regs.operator[]#11:mux.itm(6)} -attr vt d
+load net {regs.operator[]#11:mux.itm(7)} -attr vt d
+load net {regs.operator[]#11:mux.itm(8)} -attr vt d
+load net {regs.operator[]#11:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#11:mux.itm} 10 {regs.operator[]#11:mux.itm(0)} {regs.operator[]#11:mux.itm(1)} {regs.operator[]#11:mux.itm(2)} {regs.operator[]#11:mux.itm(3)} {regs.operator[]#11:mux.itm(4)} {regs.operator[]#11:mux.itm(5)} {regs.operator[]#11:mux.itm(6)} {regs.operator[]#11:mux.itm(7)} {regs.operator[]#11:mux.itm(8)} {regs.operator[]#11:mux.itm(9)} -attr xrf 8523 -attr oid 244 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(9)} -attr xrf 8524 -attr oid 245 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr xrf 8525 -attr oid 246 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#6.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#6.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(9)} -attr xrf 8526 -attr oid 247 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {conc#156.itm(0)} -attr vt d
+load net {conc#156.itm(1)} -attr vt d
+load netBundle {conc#156.itm} 2 {conc#156.itm(0)} {conc#156.itm(1)} -attr xrf 8527 -attr oid 248 -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {FRAME:for:mux#8.itm(0)} -attr vt d
+load net {FRAME:for:mux#8.itm(1)} -attr vt d
+load net {FRAME:for:mux#8.itm(2)} -attr vt d
+load net {FRAME:for:mux#8.itm(3)} -attr vt d
+load net {FRAME:for:mux#8.itm(4)} -attr vt d
+load net {FRAME:for:mux#8.itm(5)} -attr vt d
+load net {FRAME:for:mux#8.itm(6)} -attr vt d
+load net {FRAME:for:mux#8.itm(7)} -attr vt d
+load net {FRAME:for:mux#8.itm(8)} -attr vt d
+load net {FRAME:for:mux#8.itm(9)} -attr vt d
+load net {FRAME:for:mux#8.itm(10)} -attr vt d
+load net {FRAME:for:mux#8.itm(11)} -attr vt d
+load net {FRAME:for:mux#8.itm(12)} -attr vt d
+load net {FRAME:for:mux#8.itm(13)} -attr vt d
+load net {FRAME:for:mux#8.itm(14)} -attr vt d
+load net {FRAME:for:mux#8.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#8.itm} 16 {FRAME:for:mux#8.itm(0)} {FRAME:for:mux#8.itm(1)} {FRAME:for:mux#8.itm(2)} {FRAME:for:mux#8.itm(3)} {FRAME:for:mux#8.itm(4)} {FRAME:for:mux#8.itm(5)} {FRAME:for:mux#8.itm(6)} {FRAME:for:mux#8.itm(7)} {FRAME:for:mux#8.itm(8)} {FRAME:for:mux#8.itm(9)} {FRAME:for:mux#8.itm(10)} {FRAME:for:mux#8.itm(11)} {FRAME:for:mux#8.itm(12)} {FRAME:for:mux#8.itm(13)} {FRAME:for:mux#8.itm(14)} {FRAME:for:mux#8.itm(15)} -attr xrf 8528 -attr oid 249 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:exs#24.itm(0)} -attr vt d
+load net {FRAME:for:exs#24.itm(1)} -attr vt d
+load net {FRAME:for:exs#24.itm(2)} -attr vt d
+load net {FRAME:for:exs#24.itm(3)} -attr vt d
+load net {FRAME:for:exs#24.itm(4)} -attr vt d
+load net {FRAME:for:exs#24.itm(5)} -attr vt d
+load net {FRAME:for:exs#24.itm(6)} -attr vt d
+load net {FRAME:for:exs#24.itm(7)} -attr vt d
+load net {FRAME:for:exs#24.itm(8)} -attr vt d
+load net {FRAME:for:exs#24.itm(9)} -attr vt d
+load net {FRAME:for:exs#24.itm(10)} -attr vt d
+load net {FRAME:for:exs#24.itm(11)} -attr vt d
+load net {FRAME:for:exs#24.itm(12)} -attr vt d
+load net {FRAME:for:exs#24.itm(13)} -attr vt d
+load net {FRAME:for:exs#24.itm(14)} -attr vt d
+load net {FRAME:for:exs#24.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#24.itm} 16 {FRAME:for:exs#24.itm(0)} {FRAME:for:exs#24.itm(1)} {FRAME:for:exs#24.itm(2)} {FRAME:for:exs#24.itm(3)} {FRAME:for:exs#24.itm(4)} {FRAME:for:exs#24.itm(5)} {FRAME:for:exs#24.itm(6)} {FRAME:for:exs#24.itm(7)} {FRAME:for:exs#24.itm(8)} {FRAME:for:exs#24.itm(9)} {FRAME:for:exs#24.itm(10)} {FRAME:for:exs#24.itm(11)} {FRAME:for:exs#24.itm(12)} {FRAME:for:exs#24.itm(13)} {FRAME:for:exs#24.itm(14)} {FRAME:for:exs#24.itm(15)} -attr xrf 8529 -attr oid 250 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:slc#4.itm(0)} -attr vt d
+load net {ACC1:slc#4.itm(1)} -attr vt d
+load net {ACC1:slc#4.itm(2)} -attr vt d
+load net {ACC1:slc#4.itm(3)} -attr vt d
+load net {ACC1:slc#4.itm(4)} -attr vt d
+load net {ACC1:slc#4.itm(5)} -attr vt d
+load net {ACC1:slc#4.itm(6)} -attr vt d
+load net {ACC1:slc#4.itm(7)} -attr vt d
+load net {ACC1:slc#4.itm(8)} -attr vt d
+load net {ACC1:slc#4.itm(9)} -attr vt d
+load net {ACC1:slc#4.itm(10)} -attr vt d
+load netBundle {ACC1:slc#4.itm} 11 {ACC1:slc#4.itm(0)} {ACC1:slc#4.itm(1)} {ACC1:slc#4.itm(2)} {ACC1:slc#4.itm(3)} {ACC1:slc#4.itm(4)} {ACC1:slc#4.itm(5)} {ACC1:slc#4.itm(6)} {ACC1:slc#4.itm(7)} {ACC1:slc#4.itm(8)} {ACC1:slc#4.itm(9)} {ACC1:slc#4.itm(10)} -attr xrf 8530 -attr oid 251 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#4.itm}
+load net {ACC1:acc#51.itm(0)} -attr vt d
+load net {ACC1:acc#51.itm(1)} -attr vt d
+load net {ACC1:acc#51.itm(2)} -attr vt d
+load net {ACC1:acc#51.itm(3)} -attr vt d
+load net {ACC1:acc#51.itm(4)} -attr vt d
+load net {ACC1:acc#51.itm(5)} -attr vt d
+load net {ACC1:acc#51.itm(6)} -attr vt d
+load net {ACC1:acc#51.itm(7)} -attr vt d
+load net {ACC1:acc#51.itm(8)} -attr vt d
+load net {ACC1:acc#51.itm(9)} -attr vt d
+load net {ACC1:acc#51.itm(10)} -attr vt d
+load net {ACC1:acc#51.itm(11)} -attr vt d
+load netBundle {ACC1:acc#51.itm} 12 {ACC1:acc#51.itm(0)} {ACC1:acc#51.itm(1)} {ACC1:acc#51.itm(2)} {ACC1:acc#51.itm(3)} {ACC1:acc#51.itm(4)} {ACC1:acc#51.itm(5)} {ACC1:acc#51.itm(6)} {ACC1:acc#51.itm(7)} {ACC1:acc#51.itm(8)} {ACC1:acc#51.itm(9)} {ACC1:acc#51.itm(10)} {ACC1:acc#51.itm(11)} -attr xrf 8531 -attr oid 252 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {conc#157.itm(0)} -attr vt d
+load net {conc#157.itm(1)} -attr vt d
+load net {conc#157.itm(2)} -attr vt d
+load net {conc#157.itm(3)} -attr vt d
+load net {conc#157.itm(4)} -attr vt d
+load net {conc#157.itm(5)} -attr vt d
+load net {conc#157.itm(6)} -attr vt d
+load net {conc#157.itm(7)} -attr vt d
+load net {conc#157.itm(8)} -attr vt d
+load net {conc#157.itm(9)} -attr vt d
+load net {conc#157.itm(10)} -attr vt d
+load netBundle {conc#157.itm} 11 {conc#157.itm(0)} {conc#157.itm(1)} {conc#157.itm(2)} {conc#157.itm(3)} {conc#157.itm(4)} {conc#157.itm(5)} {conc#157.itm(6)} {conc#157.itm(7)} {conc#157.itm(8)} {conc#157.itm(9)} {conc#157.itm(10)} -attr xrf 8532 -attr oid 253 -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(0)} -attr vt d
+load net {ACC1:not#13.itm(1)} -attr vt d
+load net {ACC1:not#13.itm(2)} -attr vt d
+load net {ACC1:not#13.itm(3)} -attr vt d
+load net {ACC1:not#13.itm(4)} -attr vt d
+load net {ACC1:not#13.itm(5)} -attr vt d
+load net {ACC1:not#13.itm(6)} -attr vt d
+load net {ACC1:not#13.itm(7)} -attr vt d
+load net {ACC1:not#13.itm(8)} -attr vt d
+load net {ACC1:not#13.itm(9)} -attr vt d
+load netBundle {ACC1:not#13.itm} 10 {ACC1:not#13.itm(0)} {ACC1:not#13.itm(1)} {ACC1:not#13.itm(2)} {ACC1:not#13.itm(3)} {ACC1:not#13.itm(4)} {ACC1:not#13.itm(5)} {ACC1:not#13.itm(6)} {ACC1:not#13.itm(7)} {ACC1:not#13.itm(8)} {ACC1:not#13.itm(9)} -attr xrf 8533 -attr oid 254 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {slc(regs.regs(0).sva#2).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#2).itm} 10 {slc(regs.regs(0).sva#2).itm(0)} {slc(regs.regs(0).sva#2).itm(1)} {slc(regs.regs(0).sva#2).itm(2)} {slc(regs.regs(0).sva#2).itm(3)} {slc(regs.regs(0).sva#2).itm(4)} {slc(regs.regs(0).sva#2).itm(5)} {slc(regs.regs(0).sva#2).itm(6)} {slc(regs.regs(0).sva#2).itm(7)} {slc(regs.regs(0).sva#2).itm(8)} {slc(regs.regs(0).sva#2).itm(9)} -attr xrf 8534 -attr oid 255 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {conc#158.itm(0)} -attr vt d
+load net {conc#158.itm(1)} -attr vt d
+load net {conc#158.itm(2)} -attr vt d
+load net {conc#158.itm(3)} -attr vt d
+load net {conc#158.itm(4)} -attr vt d
+load net {conc#158.itm(5)} -attr vt d
+load net {conc#158.itm(6)} -attr vt d
+load net {conc#158.itm(7)} -attr vt d
+load net {conc#158.itm(8)} -attr vt d
+load net {conc#158.itm(9)} -attr vt d
+load net {conc#158.itm(10)} -attr vt d
+load netBundle {conc#158.itm} 11 {conc#158.itm(0)} {conc#158.itm(1)} {conc#158.itm(2)} {conc#158.itm(3)} {conc#158.itm(4)} {conc#158.itm(5)} {conc#158.itm(6)} {conc#158.itm(7)} {conc#158.itm(8)} {conc#158.itm(9)} {conc#158.itm(10)} -attr xrf 8535 -attr oid 256 -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {slc(regs.regs(1).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#1.itm} 10 {slc(regs.regs(1).sva)#1.itm(0)} {slc(regs.regs(1).sva)#1.itm(1)} {slc(regs.regs(1).sva)#1.itm(2)} {slc(regs.regs(1).sva)#1.itm(3)} {slc(regs.regs(1).sva)#1.itm(4)} {slc(regs.regs(1).sva)#1.itm(5)} {slc(regs.regs(1).sva)#1.itm(6)} {slc(regs.regs(1).sva)#1.itm(7)} {slc(regs.regs(1).sva)#1.itm(8)} {slc(regs.regs(1).sva)#1.itm(9)} -attr xrf 8536 -attr oid 257 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {FRAME:for:mul#7.itm(0)} -attr vt d
+load net {FRAME:for:mul#7.itm(1)} -attr vt d
+load net {FRAME:for:mul#7.itm(2)} -attr vt d
+load net {FRAME:for:mul#7.itm(3)} -attr vt d
+load net {FRAME:for:mul#7.itm(4)} -attr vt d
+load net {FRAME:for:mul#7.itm(5)} -attr vt d
+load net {FRAME:for:mul#7.itm(6)} -attr vt d
+load net {FRAME:for:mul#7.itm(7)} -attr vt d
+load net {FRAME:for:mul#7.itm(8)} -attr vt d
+load net {FRAME:for:mul#7.itm(9)} -attr vt d
+load net {FRAME:for:mul#7.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#7.itm} 11 {FRAME:for:mul#7.itm(0)} {FRAME:for:mul#7.itm(1)} {FRAME:for:mul#7.itm(2)} {FRAME:for:mul#7.itm(3)} {FRAME:for:mul#7.itm(4)} {FRAME:for:mul#7.itm(5)} {FRAME:for:mul#7.itm(6)} {FRAME:for:mul#7.itm(7)} {FRAME:for:mul#7.itm(8)} {FRAME:for:mul#7.itm(9)} {FRAME:for:mul#7.itm(10)} -attr xrf 8537 -attr oid 258 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {regs.operator[]#16:mux.itm(0)} -attr vt d
+load net {regs.operator[]#16:mux.itm(1)} -attr vt d
+load net {regs.operator[]#16:mux.itm(2)} -attr vt d
+load net {regs.operator[]#16:mux.itm(3)} -attr vt d
+load net {regs.operator[]#16:mux.itm(4)} -attr vt d
+load net {regs.operator[]#16:mux.itm(5)} -attr vt d
+load net {regs.operator[]#16:mux.itm(6)} -attr vt d
+load net {regs.operator[]#16:mux.itm(7)} -attr vt d
+load net {regs.operator[]#16:mux.itm(8)} -attr vt d
+load net {regs.operator[]#16:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#16:mux.itm} 10 {regs.operator[]#16:mux.itm(0)} {regs.operator[]#16:mux.itm(1)} {regs.operator[]#16:mux.itm(2)} {regs.operator[]#16:mux.itm(3)} {regs.operator[]#16:mux.itm(4)} {regs.operator[]#16:mux.itm(5)} {regs.operator[]#16:mux.itm(6)} {regs.operator[]#16:mux.itm(7)} {regs.operator[]#16:mux.itm(8)} {regs.operator[]#16:mux.itm(9)} -attr xrf 8538 -attr oid 259 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(9)} -attr xrf 8539 -attr oid 260 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr xrf 8540 -attr oid 261 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr xrf 8541 -attr oid 262 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {FRAME:for:mux#7.itm(0)} -attr vt d
+load net {FRAME:for:mux#7.itm(1)} -attr vt d
+load net {FRAME:for:mux#7.itm(2)} -attr vt d
+load net {FRAME:for:mux#7.itm(3)} -attr vt d
+load net {FRAME:for:mux#7.itm(4)} -attr vt d
+load net {FRAME:for:mux#7.itm(5)} -attr vt d
+load net {FRAME:for:mux#7.itm(6)} -attr vt d
+load net {FRAME:for:mux#7.itm(7)} -attr vt d
+load net {FRAME:for:mux#7.itm(8)} -attr vt d
+load net {FRAME:for:mux#7.itm(9)} -attr vt d
+load net {FRAME:for:mux#7.itm(10)} -attr vt d
+load net {FRAME:for:mux#7.itm(11)} -attr vt d
+load net {FRAME:for:mux#7.itm(12)} -attr vt d
+load net {FRAME:for:mux#7.itm(13)} -attr vt d
+load net {FRAME:for:mux#7.itm(14)} -attr vt d
+load net {FRAME:for:mux#7.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#7.itm} 16 {FRAME:for:mux#7.itm(0)} {FRAME:for:mux#7.itm(1)} {FRAME:for:mux#7.itm(2)} {FRAME:for:mux#7.itm(3)} {FRAME:for:mux#7.itm(4)} {FRAME:for:mux#7.itm(5)} {FRAME:for:mux#7.itm(6)} {FRAME:for:mux#7.itm(7)} {FRAME:for:mux#7.itm(8)} {FRAME:for:mux#7.itm(9)} {FRAME:for:mux#7.itm(10)} {FRAME:for:mux#7.itm(11)} {FRAME:for:mux#7.itm(12)} {FRAME:for:mux#7.itm(13)} {FRAME:for:mux#7.itm(14)} {FRAME:for:mux#7.itm(15)} -attr xrf 8542 -attr oid 263 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:exs#21.itm(0)} -attr vt d
+load net {FRAME:for:exs#21.itm(1)} -attr vt d
+load net {FRAME:for:exs#21.itm(2)} -attr vt d
+load net {FRAME:for:exs#21.itm(3)} -attr vt d
+load net {FRAME:for:exs#21.itm(4)} -attr vt d
+load net {FRAME:for:exs#21.itm(5)} -attr vt d
+load net {FRAME:for:exs#21.itm(6)} -attr vt d
+load net {FRAME:for:exs#21.itm(7)} -attr vt d
+load net {FRAME:for:exs#21.itm(8)} -attr vt d
+load net {FRAME:for:exs#21.itm(9)} -attr vt d
+load net {FRAME:for:exs#21.itm(10)} -attr vt d
+load net {FRAME:for:exs#21.itm(11)} -attr vt d
+load net {FRAME:for:exs#21.itm(12)} -attr vt d
+load net {FRAME:for:exs#21.itm(13)} -attr vt d
+load net {FRAME:for:exs#21.itm(14)} -attr vt d
+load net {FRAME:for:exs#21.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#21.itm} 16 {FRAME:for:exs#21.itm(0)} {FRAME:for:exs#21.itm(1)} {FRAME:for:exs#21.itm(2)} {FRAME:for:exs#21.itm(3)} {FRAME:for:exs#21.itm(4)} {FRAME:for:exs#21.itm(5)} {FRAME:for:exs#21.itm(6)} {FRAME:for:exs#21.itm(7)} {FRAME:for:exs#21.itm(8)} {FRAME:for:exs#21.itm(9)} {FRAME:for:exs#21.itm(10)} {FRAME:for:exs#21.itm(11)} {FRAME:for:exs#21.itm(12)} {FRAME:for:exs#21.itm(13)} {FRAME:for:exs#21.itm(14)} {FRAME:for:exs#21.itm(15)} -attr xrf 8543 -attr oid 264 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:slc#1.itm(0)} -attr vt d
+load net {ACC1:slc#1.itm(1)} -attr vt d
+load net {ACC1:slc#1.itm(2)} -attr vt d
+load net {ACC1:slc#1.itm(3)} -attr vt d
+load net {ACC1:slc#1.itm(4)} -attr vt d
+load net {ACC1:slc#1.itm(5)} -attr vt d
+load net {ACC1:slc#1.itm(6)} -attr vt d
+load net {ACC1:slc#1.itm(7)} -attr vt d
+load net {ACC1:slc#1.itm(8)} -attr vt d
+load net {ACC1:slc#1.itm(9)} -attr vt d
+load net {ACC1:slc#1.itm(10)} -attr vt d
+load netBundle {ACC1:slc#1.itm} 11 {ACC1:slc#1.itm(0)} {ACC1:slc#1.itm(1)} {ACC1:slc#1.itm(2)} {ACC1:slc#1.itm(3)} {ACC1:slc#1.itm(4)} {ACC1:slc#1.itm(5)} {ACC1:slc#1.itm(6)} {ACC1:slc#1.itm(7)} {ACC1:slc#1.itm(8)} {ACC1:slc#1.itm(9)} {ACC1:slc#1.itm(10)} -attr xrf 8544 -attr oid 265 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc.itm(0)} -attr vt d
+load net {ACC1:acc.itm(1)} -attr vt d
+load net {ACC1:acc.itm(2)} -attr vt d
+load net {ACC1:acc.itm(3)} -attr vt d
+load net {ACC1:acc.itm(4)} -attr vt d
+load net {ACC1:acc.itm(5)} -attr vt d
+load net {ACC1:acc.itm(6)} -attr vt d
+load net {ACC1:acc.itm(7)} -attr vt d
+load net {ACC1:acc.itm(8)} -attr vt d
+load net {ACC1:acc.itm(9)} -attr vt d
+load net {ACC1:acc.itm(10)} -attr vt d
+load net {ACC1:acc.itm(11)} -attr vt d
+load netBundle {ACC1:acc.itm} 12 {ACC1:acc.itm(0)} {ACC1:acc.itm(1)} {ACC1:acc.itm(2)} {ACC1:acc.itm(3)} {ACC1:acc.itm(4)} {ACC1:acc.itm(5)} {ACC1:acc.itm(6)} {ACC1:acc.itm(7)} {ACC1:acc.itm(8)} {ACC1:acc.itm(9)} {ACC1:acc.itm(10)} {ACC1:acc.itm(11)} -attr xrf 8545 -attr oid 266 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {conc#159.itm(0)} -attr vt d
+load net {conc#159.itm(1)} -attr vt d
+load net {conc#159.itm(2)} -attr vt d
+load net {conc#159.itm(3)} -attr vt d
+load net {conc#159.itm(4)} -attr vt d
+load net {conc#159.itm(5)} -attr vt d
+load net {conc#159.itm(6)} -attr vt d
+load net {conc#159.itm(7)} -attr vt d
+load net {conc#159.itm(8)} -attr vt d
+load net {conc#159.itm(9)} -attr vt d
+load net {conc#159.itm(10)} -attr vt d
+load netBundle {conc#159.itm} 11 {conc#159.itm(0)} {conc#159.itm(1)} {conc#159.itm(2)} {conc#159.itm(3)} {conc#159.itm(4)} {conc#159.itm(5)} {conc#159.itm(6)} {conc#159.itm(7)} {conc#159.itm(8)} {conc#159.itm(9)} {conc#159.itm(10)} -attr xrf 8546 -attr oid 267 -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(0)} -attr vt d
+load net {ACC1:not#15.itm(1)} -attr vt d
+load net {ACC1:not#15.itm(2)} -attr vt d
+load net {ACC1:not#15.itm(3)} -attr vt d
+load net {ACC1:not#15.itm(4)} -attr vt d
+load net {ACC1:not#15.itm(5)} -attr vt d
+load net {ACC1:not#15.itm(6)} -attr vt d
+load net {ACC1:not#15.itm(7)} -attr vt d
+load net {ACC1:not#15.itm(8)} -attr vt d
+load net {ACC1:not#15.itm(9)} -attr vt d
+load netBundle {ACC1:not#15.itm} 10 {ACC1:not#15.itm(0)} {ACC1:not#15.itm(1)} {ACC1:not#15.itm(2)} {ACC1:not#15.itm(3)} {ACC1:not#15.itm(4)} {ACC1:not#15.itm(5)} {ACC1:not#15.itm(6)} {ACC1:not#15.itm(7)} {ACC1:not#15.itm(8)} {ACC1:not#15.itm(9)} -attr xrf 8547 -attr oid 268 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {slc(regs.regs(0).sva#5).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#5).itm} 10 {slc(regs.regs(0).sva#5).itm(0)} {slc(regs.regs(0).sva#5).itm(1)} {slc(regs.regs(0).sva#5).itm(2)} {slc(regs.regs(0).sva#5).itm(3)} {slc(regs.regs(0).sva#5).itm(4)} {slc(regs.regs(0).sva#5).itm(5)} {slc(regs.regs(0).sva#5).itm(6)} {slc(regs.regs(0).sva#5).itm(7)} {slc(regs.regs(0).sva#5).itm(8)} {slc(regs.regs(0).sva#5).itm(9)} -attr xrf 8548 -attr oid 269 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {conc#160.itm(0)} -attr vt d
+load net {conc#160.itm(1)} -attr vt d
+load net {conc#160.itm(2)} -attr vt d
+load net {conc#160.itm(3)} -attr vt d
+load net {conc#160.itm(4)} -attr vt d
+load net {conc#160.itm(5)} -attr vt d
+load net {conc#160.itm(6)} -attr vt d
+load net {conc#160.itm(7)} -attr vt d
+load net {conc#160.itm(8)} -attr vt d
+load net {conc#160.itm(9)} -attr vt d
+load net {conc#160.itm(10)} -attr vt d
+load netBundle {conc#160.itm} 11 {conc#160.itm(0)} {conc#160.itm(1)} {conc#160.itm(2)} {conc#160.itm(3)} {conc#160.itm(4)} {conc#160.itm(5)} {conc#160.itm(6)} {conc#160.itm(7)} {conc#160.itm(8)} {conc#160.itm(9)} {conc#160.itm(10)} -attr xrf 8549 -attr oid 270 -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {slc(regs.regs(1).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#4.itm} 10 {slc(regs.regs(1).sva)#4.itm(0)} {slc(regs.regs(1).sva)#4.itm(1)} {slc(regs.regs(1).sva)#4.itm(2)} {slc(regs.regs(1).sva)#4.itm(3)} {slc(regs.regs(1).sva)#4.itm(4)} {slc(regs.regs(1).sva)#4.itm(5)} {slc(regs.regs(1).sva)#4.itm(6)} {slc(regs.regs(1).sva)#4.itm(7)} {slc(regs.regs(1).sva)#4.itm(8)} {slc(regs.regs(1).sva)#4.itm(9)} -attr xrf 8550 -attr oid 271 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {FRAME:for:mul#1.itm(0)} -attr vt d
+load net {FRAME:for:mul#1.itm(1)} -attr vt d
+load net {FRAME:for:mul#1.itm(2)} -attr vt d
+load net {FRAME:for:mul#1.itm(3)} -attr vt d
+load net {FRAME:for:mul#1.itm(4)} -attr vt d
+load net {FRAME:for:mul#1.itm(5)} -attr vt d
+load net {FRAME:for:mul#1.itm(6)} -attr vt d
+load net {FRAME:for:mul#1.itm(7)} -attr vt d
+load net {FRAME:for:mul#1.itm(8)} -attr vt d
+load net {FRAME:for:mul#1.itm(9)} -attr vt d
+load net {FRAME:for:mul#1.itm(10)} -attr vt d
+load net {FRAME:for:mul#1.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul#1.itm} 12 {FRAME:for:mul#1.itm(0)} {FRAME:for:mul#1.itm(1)} {FRAME:for:mul#1.itm(2)} {FRAME:for:mul#1.itm(3)} {FRAME:for:mul#1.itm(4)} {FRAME:for:mul#1.itm(5)} {FRAME:for:mul#1.itm(6)} {FRAME:for:mul#1.itm(7)} {FRAME:for:mul#1.itm(8)} {FRAME:for:mul#1.itm(9)} {FRAME:for:mul#1.itm(10)} {FRAME:for:mul#1.itm(11)} -attr xrf 8551 -attr oid 272 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {regs.operator[]#10:mux.itm(0)} -attr vt d
+load net {regs.operator[]#10:mux.itm(1)} -attr vt d
+load net {regs.operator[]#10:mux.itm(2)} -attr vt d
+load net {regs.operator[]#10:mux.itm(3)} -attr vt d
+load net {regs.operator[]#10:mux.itm(4)} -attr vt d
+load net {regs.operator[]#10:mux.itm(5)} -attr vt d
+load net {regs.operator[]#10:mux.itm(6)} -attr vt d
+load net {regs.operator[]#10:mux.itm(7)} -attr vt d
+load net {regs.operator[]#10:mux.itm(8)} -attr vt d
+load net {regs.operator[]#10:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#10:mux.itm} 10 {regs.operator[]#10:mux.itm(0)} {regs.operator[]#10:mux.itm(1)} {regs.operator[]#10:mux.itm(2)} {regs.operator[]#10:mux.itm(3)} {regs.operator[]#10:mux.itm(4)} {regs.operator[]#10:mux.itm(5)} {regs.operator[]#10:mux.itm(6)} {regs.operator[]#10:mux.itm(7)} {regs.operator[]#10:mux.itm(8)} {regs.operator[]#10:mux.itm(9)} -attr xrf 8552 -attr oid 273 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(9)} -attr xrf 8553 -attr oid 274 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr xrf 8554 -attr oid 275 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#7.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#7.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(9)} -attr xrf 8555 -attr oid 276 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {conc#161.itm(0)} -attr vt d
+load net {conc#161.itm(1)} -attr vt d
+load netBundle {conc#161.itm} 2 {conc#161.itm(0)} {conc#161.itm(1)} -attr xrf 8556 -attr oid 277 -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {FRAME:for:mux#6.itm(0)} -attr vt d
+load net {FRAME:for:mux#6.itm(1)} -attr vt d
+load net {FRAME:for:mux#6.itm(2)} -attr vt d
+load net {FRAME:for:mux#6.itm(3)} -attr vt d
+load net {FRAME:for:mux#6.itm(4)} -attr vt d
+load net {FRAME:for:mux#6.itm(5)} -attr vt d
+load net {FRAME:for:mux#6.itm(6)} -attr vt d
+load net {FRAME:for:mux#6.itm(7)} -attr vt d
+load net {FRAME:for:mux#6.itm(8)} -attr vt d
+load net {FRAME:for:mux#6.itm(9)} -attr vt d
+load net {FRAME:for:mux#6.itm(10)} -attr vt d
+load net {FRAME:for:mux#6.itm(11)} -attr vt d
+load net {FRAME:for:mux#6.itm(12)} -attr vt d
+load net {FRAME:for:mux#6.itm(13)} -attr vt d
+load net {FRAME:for:mux#6.itm(14)} -attr vt d
+load net {FRAME:for:mux#6.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#6.itm} 16 {FRAME:for:mux#6.itm(0)} {FRAME:for:mux#6.itm(1)} {FRAME:for:mux#6.itm(2)} {FRAME:for:mux#6.itm(3)} {FRAME:for:mux#6.itm(4)} {FRAME:for:mux#6.itm(5)} {FRAME:for:mux#6.itm(6)} {FRAME:for:mux#6.itm(7)} {FRAME:for:mux#6.itm(8)} {FRAME:for:mux#6.itm(9)} {FRAME:for:mux#6.itm(10)} {FRAME:for:mux#6.itm(11)} {FRAME:for:mux#6.itm(12)} {FRAME:for:mux#6.itm(13)} {FRAME:for:mux#6.itm(14)} {FRAME:for:mux#6.itm(15)} -attr xrf 8557 -attr oid 278 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:exs#23.itm(0)} -attr vt d
+load net {FRAME:for:exs#23.itm(1)} -attr vt d
+load net {FRAME:for:exs#23.itm(2)} -attr vt d
+load net {FRAME:for:exs#23.itm(3)} -attr vt d
+load net {FRAME:for:exs#23.itm(4)} -attr vt d
+load net {FRAME:for:exs#23.itm(5)} -attr vt d
+load net {FRAME:for:exs#23.itm(6)} -attr vt d
+load net {FRAME:for:exs#23.itm(7)} -attr vt d
+load net {FRAME:for:exs#23.itm(8)} -attr vt d
+load net {FRAME:for:exs#23.itm(9)} -attr vt d
+load net {FRAME:for:exs#23.itm(10)} -attr vt d
+load net {FRAME:for:exs#23.itm(11)} -attr vt d
+load net {FRAME:for:exs#23.itm(12)} -attr vt d
+load net {FRAME:for:exs#23.itm(13)} -attr vt d
+load net {FRAME:for:exs#23.itm(14)} -attr vt d
+load net {FRAME:for:exs#23.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#23.itm} 16 {FRAME:for:exs#23.itm(0)} {FRAME:for:exs#23.itm(1)} {FRAME:for:exs#23.itm(2)} {FRAME:for:exs#23.itm(3)} {FRAME:for:exs#23.itm(4)} {FRAME:for:exs#23.itm(5)} {FRAME:for:exs#23.itm(6)} {FRAME:for:exs#23.itm(7)} {FRAME:for:exs#23.itm(8)} {FRAME:for:exs#23.itm(9)} {FRAME:for:exs#23.itm(10)} {FRAME:for:exs#23.itm(11)} {FRAME:for:exs#23.itm(12)} {FRAME:for:exs#23.itm(13)} {FRAME:for:exs#23.itm(14)} {FRAME:for:exs#23.itm(15)} -attr xrf 8558 -attr oid 279 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:slc#3.itm(0)} -attr vt d
+load net {ACC1:slc#3.itm(1)} -attr vt d
+load net {ACC1:slc#3.itm(2)} -attr vt d
+load net {ACC1:slc#3.itm(3)} -attr vt d
+load net {ACC1:slc#3.itm(4)} -attr vt d
+load net {ACC1:slc#3.itm(5)} -attr vt d
+load net {ACC1:slc#3.itm(6)} -attr vt d
+load net {ACC1:slc#3.itm(7)} -attr vt d
+load net {ACC1:slc#3.itm(8)} -attr vt d
+load net {ACC1:slc#3.itm(9)} -attr vt d
+load net {ACC1:slc#3.itm(10)} -attr vt d
+load netBundle {ACC1:slc#3.itm} 11 {ACC1:slc#3.itm(0)} {ACC1:slc#3.itm(1)} {ACC1:slc#3.itm(2)} {ACC1:slc#3.itm(3)} {ACC1:slc#3.itm(4)} {ACC1:slc#3.itm(5)} {ACC1:slc#3.itm(6)} {ACC1:slc#3.itm(7)} {ACC1:slc#3.itm(8)} {ACC1:slc#3.itm(9)} {ACC1:slc#3.itm(10)} -attr xrf 8559 -attr oid 280 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#50.itm(0)} -attr vt d
+load net {ACC1:acc#50.itm(1)} -attr vt d
+load net {ACC1:acc#50.itm(2)} -attr vt d
+load net {ACC1:acc#50.itm(3)} -attr vt d
+load net {ACC1:acc#50.itm(4)} -attr vt d
+load net {ACC1:acc#50.itm(5)} -attr vt d
+load net {ACC1:acc#50.itm(6)} -attr vt d
+load net {ACC1:acc#50.itm(7)} -attr vt d
+load net {ACC1:acc#50.itm(8)} -attr vt d
+load net {ACC1:acc#50.itm(9)} -attr vt d
+load net {ACC1:acc#50.itm(10)} -attr vt d
+load net {ACC1:acc#50.itm(11)} -attr vt d
+load netBundle {ACC1:acc#50.itm} 12 {ACC1:acc#50.itm(0)} {ACC1:acc#50.itm(1)} {ACC1:acc#50.itm(2)} {ACC1:acc#50.itm(3)} {ACC1:acc#50.itm(4)} {ACC1:acc#50.itm(5)} {ACC1:acc#50.itm(6)} {ACC1:acc#50.itm(7)} {ACC1:acc#50.itm(8)} {ACC1:acc#50.itm(9)} {ACC1:acc#50.itm(10)} {ACC1:acc#50.itm(11)} -attr xrf 8560 -attr oid 281 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {conc#162.itm(0)} -attr vt d
+load net {conc#162.itm(1)} -attr vt d
+load net {conc#162.itm(2)} -attr vt d
+load net {conc#162.itm(3)} -attr vt d
+load net {conc#162.itm(4)} -attr vt d
+load net {conc#162.itm(5)} -attr vt d
+load net {conc#162.itm(6)} -attr vt d
+load net {conc#162.itm(7)} -attr vt d
+load net {conc#162.itm(8)} -attr vt d
+load net {conc#162.itm(9)} -attr vt d
+load net {conc#162.itm(10)} -attr vt d
+load netBundle {conc#162.itm} 11 {conc#162.itm(0)} {conc#162.itm(1)} {conc#162.itm(2)} {conc#162.itm(3)} {conc#162.itm(4)} {conc#162.itm(5)} {conc#162.itm(6)} {conc#162.itm(7)} {conc#162.itm(8)} {conc#162.itm(9)} {conc#162.itm(10)} -attr xrf 8561 -attr oid 282 -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(0)} -attr vt d
+load net {ACC1:not#12.itm(1)} -attr vt d
+load net {ACC1:not#12.itm(2)} -attr vt d
+load net {ACC1:not#12.itm(3)} -attr vt d
+load net {ACC1:not#12.itm(4)} -attr vt d
+load net {ACC1:not#12.itm(5)} -attr vt d
+load net {ACC1:not#12.itm(6)} -attr vt d
+load net {ACC1:not#12.itm(7)} -attr vt d
+load net {ACC1:not#12.itm(8)} -attr vt d
+load net {ACC1:not#12.itm(9)} -attr vt d
+load netBundle {ACC1:not#12.itm} 10 {ACC1:not#12.itm(0)} {ACC1:not#12.itm(1)} {ACC1:not#12.itm(2)} {ACC1:not#12.itm(3)} {ACC1:not#12.itm(4)} {ACC1:not#12.itm(5)} {ACC1:not#12.itm(6)} {ACC1:not#12.itm(7)} {ACC1:not#12.itm(8)} {ACC1:not#12.itm(9)} -attr xrf 8562 -attr oid 283 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {slc(regs.regs(0).sva#3).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#3).itm} 10 {slc(regs.regs(0).sva#3).itm(0)} {slc(regs.regs(0).sva#3).itm(1)} {slc(regs.regs(0).sva#3).itm(2)} {slc(regs.regs(0).sva#3).itm(3)} {slc(regs.regs(0).sva#3).itm(4)} {slc(regs.regs(0).sva#3).itm(5)} {slc(regs.regs(0).sva#3).itm(6)} {slc(regs.regs(0).sva#3).itm(7)} {slc(regs.regs(0).sva#3).itm(8)} {slc(regs.regs(0).sva#3).itm(9)} -attr xrf 8563 -attr oid 284 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {conc#163.itm(0)} -attr vt d
+load net {conc#163.itm(1)} -attr vt d
+load net {conc#163.itm(2)} -attr vt d
+load net {conc#163.itm(3)} -attr vt d
+load net {conc#163.itm(4)} -attr vt d
+load net {conc#163.itm(5)} -attr vt d
+load net {conc#163.itm(6)} -attr vt d
+load net {conc#163.itm(7)} -attr vt d
+load net {conc#163.itm(8)} -attr vt d
+load net {conc#163.itm(9)} -attr vt d
+load net {conc#163.itm(10)} -attr vt d
+load netBundle {conc#163.itm} 11 {conc#163.itm(0)} {conc#163.itm(1)} {conc#163.itm(2)} {conc#163.itm(3)} {conc#163.itm(4)} {conc#163.itm(5)} {conc#163.itm(6)} {conc#163.itm(7)} {conc#163.itm(8)} {conc#163.itm(9)} {conc#163.itm(10)} -attr xrf 8564 -attr oid 285 -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {slc(regs.regs(1).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#2.itm} 10 {slc(regs.regs(1).sva)#2.itm(0)} {slc(regs.regs(1).sva)#2.itm(1)} {slc(regs.regs(1).sva)#2.itm(2)} {slc(regs.regs(1).sva)#2.itm(3)} {slc(regs.regs(1).sva)#2.itm(4)} {slc(regs.regs(1).sva)#2.itm(5)} {slc(regs.regs(1).sva)#2.itm(6)} {slc(regs.regs(1).sva)#2.itm(7)} {slc(regs.regs(1).sva)#2.itm(8)} {slc(regs.regs(1).sva)#2.itm(9)} -attr xrf 8565 -attr oid 286 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {FRAME:for:mul#6.itm(0)} -attr vt d
+load net {FRAME:for:mul#6.itm(1)} -attr vt d
+load net {FRAME:for:mul#6.itm(2)} -attr vt d
+load net {FRAME:for:mul#6.itm(3)} -attr vt d
+load net {FRAME:for:mul#6.itm(4)} -attr vt d
+load net {FRAME:for:mul#6.itm(5)} -attr vt d
+load net {FRAME:for:mul#6.itm(6)} -attr vt d
+load net {FRAME:for:mul#6.itm(7)} -attr vt d
+load net {FRAME:for:mul#6.itm(8)} -attr vt d
+load net {FRAME:for:mul#6.itm(9)} -attr vt d
+load net {FRAME:for:mul#6.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#6.itm} 11 {FRAME:for:mul#6.itm(0)} {FRAME:for:mul#6.itm(1)} {FRAME:for:mul#6.itm(2)} {FRAME:for:mul#6.itm(3)} {FRAME:for:mul#6.itm(4)} {FRAME:for:mul#6.itm(5)} {FRAME:for:mul#6.itm(6)} {FRAME:for:mul#6.itm(7)} {FRAME:for:mul#6.itm(8)} {FRAME:for:mul#6.itm(9)} {FRAME:for:mul#6.itm(10)} -attr xrf 8566 -attr oid 287 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {regs.operator[]#15:mux.itm(0)} -attr vt d
+load net {regs.operator[]#15:mux.itm(1)} -attr vt d
+load net {regs.operator[]#15:mux.itm(2)} -attr vt d
+load net {regs.operator[]#15:mux.itm(3)} -attr vt d
+load net {regs.operator[]#15:mux.itm(4)} -attr vt d
+load net {regs.operator[]#15:mux.itm(5)} -attr vt d
+load net {regs.operator[]#15:mux.itm(6)} -attr vt d
+load net {regs.operator[]#15:mux.itm(7)} -attr vt d
+load net {regs.operator[]#15:mux.itm(8)} -attr vt d
+load net {regs.operator[]#15:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#15:mux.itm} 10 {regs.operator[]#15:mux.itm(0)} {regs.operator[]#15:mux.itm(1)} {regs.operator[]#15:mux.itm(2)} {regs.operator[]#15:mux.itm(3)} {regs.operator[]#15:mux.itm(4)} {regs.operator[]#15:mux.itm(5)} {regs.operator[]#15:mux.itm(6)} {regs.operator[]#15:mux.itm(7)} {regs.operator[]#15:mux.itm(8)} {regs.operator[]#15:mux.itm(9)} -attr xrf 8567 -attr oid 288 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(9)} -attr xrf 8568 -attr oid 289 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr xrf 8569 -attr oid 290 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr xrf 8570 -attr oid 291 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {FRAME:for:mux#5.itm(0)} -attr vt d
+load net {FRAME:for:mux#5.itm(1)} -attr vt d
+load net {FRAME:for:mux#5.itm(2)} -attr vt d
+load net {FRAME:for:mux#5.itm(3)} -attr vt d
+load net {FRAME:for:mux#5.itm(4)} -attr vt d
+load net {FRAME:for:mux#5.itm(5)} -attr vt d
+load net {FRAME:for:mux#5.itm(6)} -attr vt d
+load net {FRAME:for:mux#5.itm(7)} -attr vt d
+load net {FRAME:for:mux#5.itm(8)} -attr vt d
+load net {FRAME:for:mux#5.itm(9)} -attr vt d
+load net {FRAME:for:mux#5.itm(10)} -attr vt d
+load net {FRAME:for:mux#5.itm(11)} -attr vt d
+load net {FRAME:for:mux#5.itm(12)} -attr vt d
+load net {FRAME:for:mux#5.itm(13)} -attr vt d
+load net {FRAME:for:mux#5.itm(14)} -attr vt d
+load net {FRAME:for:mux#5.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#5.itm} 16 {FRAME:for:mux#5.itm(0)} {FRAME:for:mux#5.itm(1)} {FRAME:for:mux#5.itm(2)} {FRAME:for:mux#5.itm(3)} {FRAME:for:mux#5.itm(4)} {FRAME:for:mux#5.itm(5)} {FRAME:for:mux#5.itm(6)} {FRAME:for:mux#5.itm(7)} {FRAME:for:mux#5.itm(8)} {FRAME:for:mux#5.itm(9)} {FRAME:for:mux#5.itm(10)} {FRAME:for:mux#5.itm(11)} {FRAME:for:mux#5.itm(12)} {FRAME:for:mux#5.itm(13)} {FRAME:for:mux#5.itm(14)} {FRAME:for:mux#5.itm(15)} -attr xrf 8571 -attr oid 292 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:exs#20.itm(0)} -attr vt d
+load net {FRAME:for:exs#20.itm(1)} -attr vt d
+load net {FRAME:for:exs#20.itm(2)} -attr vt d
+load net {FRAME:for:exs#20.itm(3)} -attr vt d
+load net {FRAME:for:exs#20.itm(4)} -attr vt d
+load net {FRAME:for:exs#20.itm(5)} -attr vt d
+load net {FRAME:for:exs#20.itm(6)} -attr vt d
+load net {FRAME:for:exs#20.itm(7)} -attr vt d
+load net {FRAME:for:exs#20.itm(8)} -attr vt d
+load net {FRAME:for:exs#20.itm(9)} -attr vt d
+load net {FRAME:for:exs#20.itm(10)} -attr vt d
+load net {FRAME:for:exs#20.itm(11)} -attr vt d
+load net {FRAME:for:exs#20.itm(12)} -attr vt d
+load net {FRAME:for:exs#20.itm(13)} -attr vt d
+load net {FRAME:for:exs#20.itm(14)} -attr vt d
+load net {FRAME:for:exs#20.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#20.itm} 16 {FRAME:for:exs#20.itm(0)} {FRAME:for:exs#20.itm(1)} {FRAME:for:exs#20.itm(2)} {FRAME:for:exs#20.itm(3)} {FRAME:for:exs#20.itm(4)} {FRAME:for:exs#20.itm(5)} {FRAME:for:exs#20.itm(6)} {FRAME:for:exs#20.itm(7)} {FRAME:for:exs#20.itm(8)} {FRAME:for:exs#20.itm(9)} {FRAME:for:exs#20.itm(10)} {FRAME:for:exs#20.itm(11)} {FRAME:for:exs#20.itm(12)} {FRAME:for:exs#20.itm(13)} {FRAME:for:exs#20.itm(14)} {FRAME:for:exs#20.itm(15)} -attr xrf 8572 -attr oid 293 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:slc.itm(0)} -attr vt d
+load net {ACC1:slc.itm(1)} -attr vt d
+load net {ACC1:slc.itm(2)} -attr vt d
+load net {ACC1:slc.itm(3)} -attr vt d
+load net {ACC1:slc.itm(4)} -attr vt d
+load net {ACC1:slc.itm(5)} -attr vt d
+load net {ACC1:slc.itm(6)} -attr vt d
+load net {ACC1:slc.itm(7)} -attr vt d
+load net {ACC1:slc.itm(8)} -attr vt d
+load net {ACC1:slc.itm(9)} -attr vt d
+load net {ACC1:slc.itm(10)} -attr vt d
+load netBundle {ACC1:slc.itm} 11 {ACC1:slc.itm(0)} {ACC1:slc.itm(1)} {ACC1:slc.itm(2)} {ACC1:slc.itm(3)} {ACC1:slc.itm(4)} {ACC1:slc.itm(5)} {ACC1:slc.itm(6)} {ACC1:slc.itm(7)} {ACC1:slc.itm(8)} {ACC1:slc.itm(9)} {ACC1:slc.itm(10)} -attr xrf 8573 -attr oid 294 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#48.itm(0)} -attr vt d
+load net {ACC1:acc#48.itm(1)} -attr vt d
+load net {ACC1:acc#48.itm(2)} -attr vt d
+load net {ACC1:acc#48.itm(3)} -attr vt d
+load net {ACC1:acc#48.itm(4)} -attr vt d
+load net {ACC1:acc#48.itm(5)} -attr vt d
+load net {ACC1:acc#48.itm(6)} -attr vt d
+load net {ACC1:acc#48.itm(7)} -attr vt d
+load net {ACC1:acc#48.itm(8)} -attr vt d
+load net {ACC1:acc#48.itm(9)} -attr vt d
+load net {ACC1:acc#48.itm(10)} -attr vt d
+load net {ACC1:acc#48.itm(11)} -attr vt d
+load netBundle {ACC1:acc#48.itm} 12 {ACC1:acc#48.itm(0)} {ACC1:acc#48.itm(1)} {ACC1:acc#48.itm(2)} {ACC1:acc#48.itm(3)} {ACC1:acc#48.itm(4)} {ACC1:acc#48.itm(5)} {ACC1:acc#48.itm(6)} {ACC1:acc#48.itm(7)} {ACC1:acc#48.itm(8)} {ACC1:acc#48.itm(9)} {ACC1:acc#48.itm(10)} {ACC1:acc#48.itm(11)} -attr xrf 8574 -attr oid 295 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {conc#164.itm(0)} -attr vt d
+load net {conc#164.itm(1)} -attr vt d
+load net {conc#164.itm(2)} -attr vt d
+load net {conc#164.itm(3)} -attr vt d
+load net {conc#164.itm(4)} -attr vt d
+load net {conc#164.itm(5)} -attr vt d
+load net {conc#164.itm(6)} -attr vt d
+load net {conc#164.itm(7)} -attr vt d
+load net {conc#164.itm(8)} -attr vt d
+load net {conc#164.itm(9)} -attr vt d
+load net {conc#164.itm(10)} -attr vt d
+load netBundle {conc#164.itm} 11 {conc#164.itm(0)} {conc#164.itm(1)} {conc#164.itm(2)} {conc#164.itm(3)} {conc#164.itm(4)} {conc#164.itm(5)} {conc#164.itm(6)} {conc#164.itm(7)} {conc#164.itm(8)} {conc#164.itm(9)} {conc#164.itm(10)} -attr xrf 8575 -attr oid 296 -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(0)} -attr vt d
+load net {ACC1:not.itm(1)} -attr vt d
+load net {ACC1:not.itm(2)} -attr vt d
+load net {ACC1:not.itm(3)} -attr vt d
+load net {ACC1:not.itm(4)} -attr vt d
+load net {ACC1:not.itm(5)} -attr vt d
+load net {ACC1:not.itm(6)} -attr vt d
+load net {ACC1:not.itm(7)} -attr vt d
+load net {ACC1:not.itm(8)} -attr vt d
+load net {ACC1:not.itm(9)} -attr vt d
+load netBundle {ACC1:not.itm} 10 {ACC1:not.itm(0)} {ACC1:not.itm(1)} {ACC1:not.itm(2)} {ACC1:not.itm(3)} {ACC1:not.itm(4)} {ACC1:not.itm(5)} {ACC1:not.itm(6)} {ACC1:not.itm(7)} {ACC1:not.itm(8)} {ACC1:not.itm(9)} -attr xrf 8576 -attr oid 297 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {slc(regs.regs(0).sva#6).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#6).itm} 10 {slc(regs.regs(0).sva#6).itm(0)} {slc(regs.regs(0).sva#6).itm(1)} {slc(regs.regs(0).sva#6).itm(2)} {slc(regs.regs(0).sva#6).itm(3)} {slc(regs.regs(0).sva#6).itm(4)} {slc(regs.regs(0).sva#6).itm(5)} {slc(regs.regs(0).sva#6).itm(6)} {slc(regs.regs(0).sva#6).itm(7)} {slc(regs.regs(0).sva#6).itm(8)} {slc(regs.regs(0).sva#6).itm(9)} -attr xrf 8577 -attr oid 298 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {conc#165.itm(0)} -attr vt d
+load net {conc#165.itm(1)} -attr vt d
+load net {conc#165.itm(2)} -attr vt d
+load net {conc#165.itm(3)} -attr vt d
+load net {conc#165.itm(4)} -attr vt d
+load net {conc#165.itm(5)} -attr vt d
+load net {conc#165.itm(6)} -attr vt d
+load net {conc#165.itm(7)} -attr vt d
+load net {conc#165.itm(8)} -attr vt d
+load net {conc#165.itm(9)} -attr vt d
+load net {conc#165.itm(10)} -attr vt d
+load netBundle {conc#165.itm} 11 {conc#165.itm(0)} {conc#165.itm(1)} {conc#165.itm(2)} {conc#165.itm(3)} {conc#165.itm(4)} {conc#165.itm(5)} {conc#165.itm(6)} {conc#165.itm(7)} {conc#165.itm(8)} {conc#165.itm(9)} {conc#165.itm(10)} -attr xrf 8578 -attr oid 299 -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {slc(regs.regs(1).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#5.itm} 10 {slc(regs.regs(1).sva)#5.itm(0)} {slc(regs.regs(1).sva)#5.itm(1)} {slc(regs.regs(1).sva)#5.itm(2)} {slc(regs.regs(1).sva)#5.itm(3)} {slc(regs.regs(1).sva)#5.itm(4)} {slc(regs.regs(1).sva)#5.itm(5)} {slc(regs.regs(1).sva)#5.itm(6)} {slc(regs.regs(1).sva)#5.itm(7)} {slc(regs.regs(1).sva)#5.itm(8)} {slc(regs.regs(1).sva)#5.itm(9)} -attr xrf 8579 -attr oid 300 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {FRAME:for:mul.itm(0)} -attr vt d
+load net {FRAME:for:mul.itm(1)} -attr vt d
+load net {FRAME:for:mul.itm(2)} -attr vt d
+load net {FRAME:for:mul.itm(3)} -attr vt d
+load net {FRAME:for:mul.itm(4)} -attr vt d
+load net {FRAME:for:mul.itm(5)} -attr vt d
+load net {FRAME:for:mul.itm(6)} -attr vt d
+load net {FRAME:for:mul.itm(7)} -attr vt d
+load net {FRAME:for:mul.itm(8)} -attr vt d
+load net {FRAME:for:mul.itm(9)} -attr vt d
+load net {FRAME:for:mul.itm(10)} -attr vt d
+load net {FRAME:for:mul.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul.itm} 12 {FRAME:for:mul.itm(0)} {FRAME:for:mul.itm(1)} {FRAME:for:mul.itm(2)} {FRAME:for:mul.itm(3)} {FRAME:for:mul.itm(4)} {FRAME:for:mul.itm(5)} {FRAME:for:mul.itm(6)} {FRAME:for:mul.itm(7)} {FRAME:for:mul.itm(8)} {FRAME:for:mul.itm(9)} {FRAME:for:mul.itm(10)} {FRAME:for:mul.itm(11)} -attr xrf 8580 -attr oid 301 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {regs.operator[]#9:mux.itm(0)} -attr vt d
+load net {regs.operator[]#9:mux.itm(1)} -attr vt d
+load net {regs.operator[]#9:mux.itm(2)} -attr vt d
+load net {regs.operator[]#9:mux.itm(3)} -attr vt d
+load net {regs.operator[]#9:mux.itm(4)} -attr vt d
+load net {regs.operator[]#9:mux.itm(5)} -attr vt d
+load net {regs.operator[]#9:mux.itm(6)} -attr vt d
+load net {regs.operator[]#9:mux.itm(7)} -attr vt d
+load net {regs.operator[]#9:mux.itm(8)} -attr vt d
+load net {regs.operator[]#9:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#9:mux.itm} 10 {regs.operator[]#9:mux.itm(0)} {regs.operator[]#9:mux.itm(1)} {regs.operator[]#9:mux.itm(2)} {regs.operator[]#9:mux.itm(3)} {regs.operator[]#9:mux.itm(4)} {regs.operator[]#9:mux.itm(5)} {regs.operator[]#9:mux.itm(6)} {regs.operator[]#9:mux.itm(7)} {regs.operator[]#9:mux.itm(8)} {regs.operator[]#9:mux.itm(9)} -attr xrf 8581 -attr oid 302 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(9)} -attr xrf 8582 -attr oid 303 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr xrf 8583 -attr oid 304 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#8.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#8.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(9)} -attr xrf 8584 -attr oid 305 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {conc#166.itm(0)} -attr vt d
+load net {conc#166.itm(1)} -attr vt d
+load netBundle {conc#166.itm} 2 {conc#166.itm(0)} {conc#166.itm(1)} -attr xrf 8585 -attr oid 306 -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {clk} -attr xrf 8586 -attr oid 307
+load net {clk} -port {clk} -attr xrf 8587 -attr oid 308
+load net {en} -attr xrf 8588 -attr oid 309
+load net {en} -port {en} -attr xrf 8589 -attr oid 310
+load net {arst_n} -attr xrf 8590 -attr oid 311
+load net {arst_n} -port {arst_n} -attr xrf 8591 -attr oid 312
+load net {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 8592 -attr oid 313 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(0)} -port {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -port {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -port {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -port {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -port {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -port {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -port {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -port {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -port {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -port {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -port {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -port {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -port {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -port {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -port {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -port {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -port {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -port {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -port {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -port {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -port {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -port {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -port {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -port {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -port {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -port {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -port {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -port {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -port {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -port {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -port {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -port {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -port {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -port {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -port {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -port {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -port {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -port {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -port {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -port {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -port {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -port {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -port {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -port {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -port {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -port {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -port {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -port {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -port {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -port {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -port {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -port {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -port {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -port {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -port {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -port {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -port {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -port {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -port {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -port {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -port {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -port {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -port {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -port {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -port {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -port {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -port {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -port {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -port {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -port {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -port {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -port {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -port {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -port {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -port {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -port {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -port {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -port {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -port {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -port {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -port {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -port {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -port {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -port {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -port {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -port {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -port {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -port {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -port {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -port {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 8593 -attr oid 314 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d} 30 {vout:rsc:mgc_out_stdreg.d(0)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(29)} -attr xrf 8594 -attr oid 315 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -port {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -port {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -port {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -port {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -port {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -port {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -port {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -port {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -port {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -port {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -port {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -port {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -port {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -port {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -port {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -port {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -port {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -port {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -port {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -port {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -port {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -port {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -port {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -port {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -port {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -port {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -port {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -port {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -port {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -port {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:acc#38" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 8595 -attr oid 316 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {FRAME:acc#37.itm#1(0)} -pin  "FRAME:acc#38" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(1)} -pin  "FRAME:acc#38" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(2)} -pin  "FRAME:acc#38" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(3)} -pin  "FRAME:acc#38" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(4)} -pin  "FRAME:acc#38" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:slc(acc.imod)#4.itm#1} -pin  "FRAME:acc#38" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#123.itm}
+load net {PWR} -pin  "FRAME:acc#38" {B(1)} -attr @path {/sobel/sobel:core/conc#123.itm}
+load net {GND} -pin  "FRAME:acc#38" {B(2)} -attr @path {/sobel/sobel:core/conc#123.itm}
+load net {GND} -pin  "FRAME:acc#38" {B(3)} -attr @path {/sobel/sobel:core/conc#123.itm}
+load net {PWR} -pin  "FRAME:acc#38" {B(4)} -attr @path {/sobel/sobel:core/conc#123.itm}
+load net {FRAME:acc#38.itm(0)} -pin  "FRAME:acc#38" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(1)} -pin  "FRAME:acc#38" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(2)} -pin  "FRAME:acc#38" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(3)} -pin  "FRAME:acc#38" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(4)} -pin  "FRAME:acc#38" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load inst "FRAME:acc#39" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 8596 -attr oid 317 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {red:slc(red#2.sg1).itm#1(0)} -pin  "FRAME:acc#39" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
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+load inst "nand" "nand(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "nand" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {main.stage_0#2} -pin  "nand" {A1(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {nand.itm} -pin  "nand" {Z(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load inst "mux" "mux(2,30)" "INTERFACE" -attr xrf 8601 -attr oid 322 -attr vt d -attr @path {/sobel/sobel:core/mux} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "mux" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "mux" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "mux" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "mux" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "mux" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "mux" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "mux" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "mux" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "mux" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "mux" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "mux" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "mux" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "mux" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "mux" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "mux" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "mux" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "mux" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "mux" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "mux" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "mux" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "mux" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "mux" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "mux" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "mux" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "mux" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "mux" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "mux" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "mux" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "mux" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "mux" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {FRAME:acc#4.psp.sva(0)} -pin  "mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(1)} -pin  "mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(2)} -pin  "mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(3)} -pin  "mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(4)} -pin  "mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(5)} -pin  "mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(6)} -pin  "mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(7)} -pin  "mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(8)} -pin  "mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(9)} -pin  "mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(0)} -pin  "mux" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(1)} -pin  "mux" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(2)} -pin  "mux" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(3)} -pin  "mux" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(4)} -pin  "mux" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(5)} -pin  "mux" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(6)} -pin  "mux" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(7)} -pin  "mux" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(8)} -pin  "mux" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(9)} -pin  "mux" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(0)} -pin  "mux" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(1)} -pin  "mux" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(2)} -pin  "mux" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(3)} -pin  "mux" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(4)} -pin  "mux" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(5)} -pin  "mux" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(6)} -pin  "mux" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(7)} -pin  "mux" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(8)} -pin  "mux" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(9)} -pin  "mux" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {nand.itm} -pin  "mux" {S(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load net {mux.itm(0)} -pin  "mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "mux" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "mux" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "mux" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "mux" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "mux" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "mux" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "mux" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "mux" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "mux" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "mux" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "mux" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "mux" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "mux" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "mux" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "mux" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "mux" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "mux" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "mux" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "mux" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "mux" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 8602 -attr oid 323 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)}
+load net {mux.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 8603 -attr oid 324 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:acc#43" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 8604 -attr oid 325 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {FRAME:mul.sdt(8)} -pin  "FRAME:acc#43" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt).itm}
+load net {FRAME:mul.sdt(9)} -pin  "FRAME:acc#43" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt).itm}
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:acc#43" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#3.itm}
+load net {FRAME:acc#43.itm(0)} -pin  "FRAME:acc#43" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {FRAME:acc#43.itm(1)} -pin  "FRAME:acc#43" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load inst "reg(FRAME:acc#41.itm#1.sg2)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 8605 -attr oid 326 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#41.itm#1.sg2)}
+load net {FRAME:acc#43.itm(0)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {FRAME:acc#43.itm(1)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {clk} -attr xrf 8606 -attr oid 327 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#41.itm#1.sg2(0)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg2}
+load net {FRAME:acc#41.itm#1.sg2(1)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg2}
+load inst "reg(FRAME:acc#41.itm#1.sg1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 8607 -attr oid 328 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#41.itm#1.sg1)}
+load net {FRAME:mul.sdt(6)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#2.itm}
+load net {FRAME:mul.sdt(7)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#2.itm}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {clk} -attr xrf 8608 -attr oid 329 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#41.itm#1.sg1(0)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg1}
+load net {FRAME:acc#41.itm#1.sg1(1)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg1}
+load inst "FRAME:acc#44" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 8609 -attr oid 330 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44} -attr area 6.285690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {FRAME:mul.sdt(0)} -pin  "FRAME:acc#44" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(1)} -pin  "FRAME:acc#44" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(2)} -pin  "FRAME:acc#44" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(3)} -pin  "FRAME:acc#44" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(4)} -pin  "FRAME:acc#44" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:acc#44" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {GND} -pin  "FRAME:acc#44" {B(1)} -attr @path {/sobel/sobel:core/exs.itm}
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:acc#44" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:acc#44" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:acc#44" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:acc#44.itm(0)} -pin  "FRAME:acc#44" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(1)} -pin  "FRAME:acc#44" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(2)} -pin  "FRAME:acc#44" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(3)} -pin  "FRAME:acc#44" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(4)} -pin  "FRAME:acc#44" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(5)} -pin  "FRAME:acc#44" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load inst "reg(FRAME:acc#41.itm#3)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 8610 -attr oid 331 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#41.itm#3)}
+load net {FRAME:acc#44.itm(0)} -pin  "reg(FRAME:acc#41.itm#3)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(1)} -pin  "reg(FRAME:acc#41.itm#3)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(2)} -pin  "reg(FRAME:acc#41.itm#3)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(3)} -pin  "reg(FRAME:acc#41.itm#3)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(4)} -pin  "reg(FRAME:acc#41.itm#3)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(5)} -pin  "reg(FRAME:acc#41.itm#3)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(FRAME:acc#41.itm#3)" {clk} -attr xrf 8611 -attr oid 332 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#41.itm#3)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#41.itm#3)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#41.itm#3(0)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(1)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(2)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(3)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(4)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(5)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load inst "FRAME:mul#1" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 8612 -attr oid 333 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc#43.itm(10)} -pin  "FRAME:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {ACC1:acc#43.itm(11)} -pin  "FRAME:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {ACC1:acc#43.itm(12)} -pin  "FRAME:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {PWR} -pin  "FRAME:mul#1" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#1.itm(0)} -pin  "FRAME:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "FRAME:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "FRAME:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "FRAME:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "FRAME:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "FRAME:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "FRAME:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "FRAME:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "FRAME:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load inst "reg(FRAME:mul#1.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 8613 -attr oid 334 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#1.itm#1)}
+load net {FRAME:mul#1.itm(0)} -pin  "reg(FRAME:mul#1.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "reg(FRAME:mul#1.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "reg(FRAME:mul#1.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "reg(FRAME:mul#1.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "reg(FRAME:mul#1.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "reg(FRAME:mul#1.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "reg(FRAME:mul#1.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "reg(FRAME:mul#1.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "reg(FRAME:mul#1.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#1.itm#1)" {clk} -attr xrf 8614 -attr oid 335 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#1.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#1.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#1.itm#1(0)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(1)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(2)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(3)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(4)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(5)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(6)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(7)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(8)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load inst "reg(red:slc(red#2.sg1).itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 8615 -attr oid 336 -attr vt d -attr @path {/sobel/sobel:core/reg(red:slc(red#2.sg1).itm#1)}
+load net {ACC1:acc#43.itm(4)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC1:acc#43.itm(5)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC1:acc#43.itm(6)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC1:acc#43.itm(7)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC1:acc#43.itm(8)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC1:acc#43.itm(9)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(red:slc(red#2.sg1).itm#1)" {clk} -attr xrf 8616 -attr oid 337 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(red:slc(red#2.sg1).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {red:slc(red#2.sg1).itm#1(0)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(1)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(2)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(3)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(4)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(5)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load inst "FRAME:not#7" "not(1)" "INTERFACE" -attr xrf 8617 -attr oid 338 -attr @path {/sobel/sobel:core/FRAME:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod.sva(5)} -pin  "FRAME:not#7" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#6.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load inst "FRAME:not#5" "not(3)" "INTERFACE" -attr xrf 8618 -attr oid 339 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod.sva(3)} -pin  "FRAME:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#2.itm}
+load net {acc.imod.sva(4)} -pin  "FRAME:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#2.itm}
+load net {acc.imod.sva(5)} -pin  "FRAME:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#2.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load inst "FRAME:not#4" "not(1)" "INTERFACE" -attr xrf 8619 -attr oid 340 -attr @path {/sobel/sobel:core/FRAME:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod.sva(5)} -pin  "FRAME:not#4" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#3.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:not#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#4.itm}
+load inst "FRAME:acc#42" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 8620 -attr oid 341 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {PWR} -pin  "FRAME:acc#42" {A(0)} -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {acc.imod.sva(0)} -pin  "FRAME:acc#42" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {acc.imod.sva(1)} -pin  "FRAME:acc#42" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {acc.imod.sva(2)} -pin  "FRAME:acc#42" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {PWR} -pin  "FRAME:acc#42" {A(4)} -attr @path {/sobel/sobel:core/conc#129.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:acc#42" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:acc#42" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:acc#42" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:acc#42" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:acc#42.itm(0)} -pin  "FRAME:acc#42" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(1)} -pin  "FRAME:acc#42" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(2)} -pin  "FRAME:acc#42" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(3)} -pin  "FRAME:acc#42" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(4)} -pin  "FRAME:acc#42" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load inst "FRAME:not#39" "not(1)" "INTERFACE" -attr xrf 8621 -attr oid 342 -attr vt c -attr @path {/sobel/sobel:core/FRAME:not#39} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#42.itm(4)} -pin  "FRAME:not#39" {A(0)} -attr vt c -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:not#39.itm} -pin  "FRAME:not#39" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/FRAME:not#39.itm}
+load inst "FRAME:acc#36" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 8622 -attr oid 343 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#39.itm} -pin  "FRAME:acc#36" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {PWR} -pin  "FRAME:acc#36" {A(1)} -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:acc#36" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#128.itm}
+load net {acc.imod.sva(3)} -pin  "FRAME:acc#36" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#4.itm}
+load net {acc.imod.sva(4)} -pin  "FRAME:acc#36" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#4.itm}
+load net {FRAME:acc#36.itm(0)} -pin  "FRAME:acc#36" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(1)} -pin  "FRAME:acc#36" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(2)} -pin  "FRAME:acc#36" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(3)} -pin  "FRAME:acc#36" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load inst "FRAME:not#6" "not(3)" "INTERFACE" -attr xrf 8623 -attr oid 344 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#43.itm(7)} -pin  "FRAME:not#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {ACC1:acc#43.itm(8)} -pin  "FRAME:not#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {ACC1:acc#43.itm(9)} -pin  "FRAME:not#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:not#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:not#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:not#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load inst "FRAME:acc#37" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 8624 -attr oid 345 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#36.itm(0)} -pin  "FRAME:acc#37" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(1)} -pin  "FRAME:acc#37" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(2)} -pin  "FRAME:acc#37" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(3)} -pin  "FRAME:acc#37" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:acc#37" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:acc#37" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:acc#37" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:acc#37.itm(0)} -pin  "FRAME:acc#37" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(1)} -pin  "FRAME:acc#37" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(2)} -pin  "FRAME:acc#37" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(3)} -pin  "FRAME:acc#37" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(4)} -pin  "FRAME:acc#37" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load inst "reg(FRAME:acc#37.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 8625 -attr oid 346 -attr vt dc -attr @path {/sobel/sobel:core/reg(FRAME:acc#37.itm#1)}
+load net {FRAME:acc#37.itm(0)} -pin  "reg(FRAME:acc#37.itm#1)" {D(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(1)} -pin  "reg(FRAME:acc#37.itm#1)" {D(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(2)} -pin  "reg(FRAME:acc#37.itm#1)" {D(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(3)} -pin  "reg(FRAME:acc#37.itm#1)" {D(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(4)} -pin  "reg(FRAME:acc#37.itm#1)" {D(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#37.itm#1)" {clk} -attr xrf 8626 -attr oid 347 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#37.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#37.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#37.itm#1(0)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(1)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(2)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(3)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(4)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load inst "reg(FRAME:slc(acc.imod)#4.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 8627 -attr oid 348 -attr @path {/sobel/sobel:core/reg(FRAME:slc(acc.imod)#4.itm#1)}
+load net {acc.imod.sva(5)} -pin  "reg(FRAME:slc(acc.imod)#4.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod.sva).itm}
+load net {GND} -pin  "reg(FRAME:slc(acc.imod)#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(FRAME:slc(acc.imod)#4.itm#1)" {clk} -attr xrf 8628 -attr oid 349 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(acc.imod)#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(acc.imod)#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(acc.imod)#4.itm#1} -pin  "reg(FRAME:slc(acc.imod)#4.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:slc(acc.imod)#4.itm#1}
+load inst "FRAME:mul#4" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 8629 -attr oid 350 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC1:acc#45.itm(13)} -pin  "FRAME:mul#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#10.itm}
+load net {ACC1:acc#45.itm(14)} -pin  "FRAME:mul#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#10.itm}
+load net {PWR} -pin  "FRAME:mul#4" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#4.itm(0)} -pin  "FRAME:mul#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(1)} -pin  "FRAME:mul#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(2)} -pin  "FRAME:mul#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(3)} -pin  "FRAME:mul#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(4)} -pin  "FRAME:mul#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(5)} -pin  "FRAME:mul#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(6)} -pin  "FRAME:mul#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(7)} -pin  "FRAME:mul#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(8)} -pin  "FRAME:mul#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(9)} -pin  "FRAME:mul#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(10)} -pin  "FRAME:mul#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load inst "reg(FRAME:mul#4.itm#1)" "reg(11,1,1,-1,0)" "INTERFACE" -attr xrf 8630 -attr oid 351 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#4.itm#1)}
+load net {FRAME:mul#4.itm(0)} -pin  "reg(FRAME:mul#4.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(1)} -pin  "reg(FRAME:mul#4.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(2)} -pin  "reg(FRAME:mul#4.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(3)} -pin  "reg(FRAME:mul#4.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(4)} -pin  "reg(FRAME:mul#4.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(5)} -pin  "reg(FRAME:mul#4.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(6)} -pin  "reg(FRAME:mul#4.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(7)} -pin  "reg(FRAME:mul#4.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(8)} -pin  "reg(FRAME:mul#4.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(9)} -pin  "reg(FRAME:mul#4.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(10)} -pin  "reg(FRAME:mul#4.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_11}
+load net {clk} -pin  "reg(FRAME:mul#4.itm#1)" {clk} -attr xrf 8631 -attr oid 352 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#4.itm#1(0)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(1)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(2)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(3)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(4)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(5)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(6)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(7)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(8)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(9)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(10)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load inst "FRAME:mul#5" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 8632 -attr oid 353 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc#45.itm(10)} -pin  "FRAME:mul#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "FRAME:mul#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {ACC1:acc#45.itm(12)} -pin  "FRAME:mul#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {PWR} -pin  "FRAME:mul#5" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#5" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#5" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#5.itm(0)} -pin  "FRAME:mul#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(1)} -pin  "FRAME:mul#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(2)} -pin  "FRAME:mul#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(3)} -pin  "FRAME:mul#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(4)} -pin  "FRAME:mul#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(5)} -pin  "FRAME:mul#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(6)} -pin  "FRAME:mul#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(7)} -pin  "FRAME:mul#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(8)} -pin  "FRAME:mul#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load inst "reg(FRAME:mul#5.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 8633 -attr oid 354 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#5.itm#1)}
+load net {FRAME:mul#5.itm(0)} -pin  "reg(FRAME:mul#5.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(1)} -pin  "reg(FRAME:mul#5.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(2)} -pin  "reg(FRAME:mul#5.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(3)} -pin  "reg(FRAME:mul#5.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(4)} -pin  "reg(FRAME:mul#5.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(5)} -pin  "reg(FRAME:mul#5.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(6)} -pin  "reg(FRAME:mul#5.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(7)} -pin  "reg(FRAME:mul#5.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(8)} -pin  "reg(FRAME:mul#5.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#5.itm#1)" {clk} -attr xrf 8634 -attr oid 355 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#5.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#5.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#5.itm#1(0)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(1)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(2)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(3)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(4)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(5)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(6)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(7)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(8)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load inst "reg(blue:slc(blue#2.sg1).itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 8635 -attr oid 356 -attr vt d -attr @path {/sobel/sobel:core/reg(blue:slc(blue#2.sg1).itm#1)}
+load net {ACC1:acc#45.itm(4)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC1:acc#45.itm(5)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC1:acc#45.itm(6)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC1:acc#45.itm(7)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC1:acc#45.itm(8)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC1:acc#45.itm(9)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {clk} -attr xrf 8636 -attr oid 357 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {blue:slc(blue#2.sg1).itm#1(0)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(1)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(2)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(3)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(4)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(5)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load inst "FRAME:not#23" "not(1)" "INTERFACE" -attr xrf 8637 -attr oid 358 -attr @path {/sobel/sobel:core/FRAME:not#23} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#4.sva(5)} -pin  "FRAME:not#23" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#6.itm}
+load net {FRAME:not#23.itm} -pin  "FRAME:not#23" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#23.itm}
+load inst "FRAME:not#21" "not(3)" "INTERFACE" -attr xrf 8638 -attr oid 359 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#4.sva(3)} -pin  "FRAME:not#21" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#2.itm}
+load net {acc.imod#4.sva(4)} -pin  "FRAME:not#21" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#2.itm}
+load net {acc.imod#4.sva(5)} -pin  "FRAME:not#21" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#2.itm}
+load net {FRAME:not#21.itm(0)} -pin  "FRAME:not#21" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {FRAME:not#21.itm(1)} -pin  "FRAME:not#21" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {FRAME:not#21.itm(2)} -pin  "FRAME:not#21" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load inst "FRAME:not#20" "not(1)" "INTERFACE" -attr xrf 8639 -attr oid 360 -attr @path {/sobel/sobel:core/FRAME:not#20} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#4.sva(5)} -pin  "FRAME:not#20" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#3.itm}
+load net {FRAME:not#20.itm} -pin  "FRAME:not#20" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load inst "FRAME:acc#35" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 8640 -attr oid 361 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {PWR} -pin  "FRAME:acc#35" {A(0)} -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {acc.imod#4.sva(0)} -pin  "FRAME:acc#35" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {acc.imod#4.sva(1)} -pin  "FRAME:acc#35" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {acc.imod#4.sva(2)} -pin  "FRAME:acc#35" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {PWR} -pin  "FRAME:acc#35" {A(4)} -attr @path {/sobel/sobel:core/conc#131.itm}
+load net {FRAME:not#20.itm} -pin  "FRAME:acc#35" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(0)} -pin  "FRAME:acc#35" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(1)} -pin  "FRAME:acc#35" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(2)} -pin  "FRAME:acc#35" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:acc#35.itm(0)} -pin  "FRAME:acc#35" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(1)} -pin  "FRAME:acc#35" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(2)} -pin  "FRAME:acc#35" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(3)} -pin  "FRAME:acc#35" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(4)} -pin  "FRAME:acc#35" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load inst "FRAME:not#41" "not(1)" "INTERFACE" -attr xrf 8641 -attr oid 362 -attr @path {/sobel/sobel:core/FRAME:not#41} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#35.itm(4)} -pin  "FRAME:not#41" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#6.itm}
+load net {FRAME:not#41.itm} -pin  "FRAME:not#41" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#41.itm}
+load inst "FRAME:acc#29" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 8642 -attr oid 363 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#41.itm} -pin  "FRAME:acc#29" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {PWR} -pin  "FRAME:acc#29" {A(1)} -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {FRAME:not#23.itm} -pin  "FRAME:acc#29" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#130.itm}
+load net {acc.imod#4.sva(3)} -pin  "FRAME:acc#29" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#4.itm}
+load net {acc.imod#4.sva(4)} -pin  "FRAME:acc#29" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva)#4.itm}
+load net {FRAME:acc#29.itm(0)} -pin  "FRAME:acc#29" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(1)} -pin  "FRAME:acc#29" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(2)} -pin  "FRAME:acc#29" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(3)} -pin  "FRAME:acc#29" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load inst "FRAME:not#22" "not(3)" "INTERFACE" -attr xrf 8643 -attr oid 364 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#45.itm(7)} -pin  "FRAME:not#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {ACC1:acc#45.itm(8)} -pin  "FRAME:not#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {ACC1:acc#45.itm(9)} -pin  "FRAME:not#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {FRAME:not#22.itm(0)} -pin  "FRAME:not#22" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(1)} -pin  "FRAME:not#22" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(2)} -pin  "FRAME:not#22" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load inst "FRAME:acc#30" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 8644 -attr oid 365 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#29.itm(0)} -pin  "FRAME:acc#30" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(1)} -pin  "FRAME:acc#30" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(2)} -pin  "FRAME:acc#30" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(3)} -pin  "FRAME:acc#30" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:not#22.itm(0)} -pin  "FRAME:acc#30" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(1)} -pin  "FRAME:acc#30" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(2)} -pin  "FRAME:acc#30" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:acc#30.itm(0)} -pin  "FRAME:acc#30" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(1)} -pin  "FRAME:acc#30" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(2)} -pin  "FRAME:acc#30" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(3)} -pin  "FRAME:acc#30" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(4)} -pin  "FRAME:acc#30" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load inst "reg(FRAME:acc#30.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 8645 -attr oid 366 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#30.itm#1)}
+load net {FRAME:acc#30.itm(0)} -pin  "reg(FRAME:acc#30.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(1)} -pin  "reg(FRAME:acc#30.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(2)} -pin  "reg(FRAME:acc#30.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(3)} -pin  "reg(FRAME:acc#30.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(4)} -pin  "reg(FRAME:acc#30.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#30.itm#1)" {clk} -attr xrf 8646 -attr oid 367 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#30.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#30.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#30.itm#1(0)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(1)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(2)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(3)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(4)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load inst "reg(FRAME:slc(acc.imod#4)#4.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 8647 -attr oid 368 -attr @path {/sobel/sobel:core/reg(FRAME:slc(acc.imod#4)#4.itm#1)}
+load net {acc.imod#4.sva(5)} -pin  "reg(FRAME:slc(acc.imod#4)#4.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#4.sva).itm}
+load net {GND} -pin  "reg(FRAME:slc(acc.imod#4)#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(FRAME:slc(acc.imod#4)#4.itm#1)" {clk} -attr xrf 8648 -attr oid 369 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(acc.imod#4)#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(acc.imod#4)#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(acc.imod#4)#4.itm#1} -pin  "reg(FRAME:slc(acc.imod#4)#4.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:slc(acc.imod#4)#4.itm#1}
+load inst "reg(blue:slc(blue#2.sg1)#12.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 8649 -attr oid 370 -attr @path {/sobel/sobel:core/reg(blue:slc(blue#2.sg1)#12.itm#1)}
+load net {ACC1:acc#45.itm(15)} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva).itm}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {clk} -attr xrf 8650 -attr oid 371 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1)#12.itm#1}
+load inst "FRAME:mul#2" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 8651 -attr oid 372 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC1:acc#44.itm(13)} -pin  "FRAME:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#10.itm}
+load net {ACC1:acc#44.itm(14)} -pin  "FRAME:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#10.itm}
+load net {PWR} -pin  "FRAME:mul#2" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#2.itm(0)} -pin  "FRAME:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(1)} -pin  "FRAME:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(2)} -pin  "FRAME:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(3)} -pin  "FRAME:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(4)} -pin  "FRAME:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(5)} -pin  "FRAME:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(6)} -pin  "FRAME:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(7)} -pin  "FRAME:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(8)} -pin  "FRAME:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(9)} -pin  "FRAME:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(10)} -pin  "FRAME:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load inst "reg(FRAME:mul#2.itm#1)" "reg(11,1,1,-1,0)" "INTERFACE" -attr xrf 8652 -attr oid 373 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#2.itm#1)}
+load net {FRAME:mul#2.itm(0)} -pin  "reg(FRAME:mul#2.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(1)} -pin  "reg(FRAME:mul#2.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(2)} -pin  "reg(FRAME:mul#2.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(3)} -pin  "reg(FRAME:mul#2.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(4)} -pin  "reg(FRAME:mul#2.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(5)} -pin  "reg(FRAME:mul#2.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(6)} -pin  "reg(FRAME:mul#2.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(7)} -pin  "reg(FRAME:mul#2.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(8)} -pin  "reg(FRAME:mul#2.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(9)} -pin  "reg(FRAME:mul#2.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(10)} -pin  "reg(FRAME:mul#2.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_11}
+load net {clk} -pin  "reg(FRAME:mul#2.itm#1)" {clk} -attr xrf 8653 -attr oid 374 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#2.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#2.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#2.itm#1(0)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(1)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(2)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(3)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(4)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(5)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(6)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(7)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(8)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(9)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(10)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load inst "FRAME:mul#3" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 8654 -attr oid 375 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc#44.itm(10)} -pin  "FRAME:mul#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {ACC1:acc#44.itm(11)} -pin  "FRAME:mul#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {ACC1:acc#44.itm(12)} -pin  "FRAME:mul#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {PWR} -pin  "FRAME:mul#3" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#3" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#3" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#3.itm(0)} -pin  "FRAME:mul#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "FRAME:mul#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "FRAME:mul#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "FRAME:mul#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "FRAME:mul#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "FRAME:mul#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "FRAME:mul#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "FRAME:mul#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "FRAME:mul#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load inst "reg(FRAME:mul#3.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 8655 -attr oid 376 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#3.itm#1)}
+load net {FRAME:mul#3.itm(0)} -pin  "reg(FRAME:mul#3.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "reg(FRAME:mul#3.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "reg(FRAME:mul#3.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "reg(FRAME:mul#3.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "reg(FRAME:mul#3.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "reg(FRAME:mul#3.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "reg(FRAME:mul#3.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "reg(FRAME:mul#3.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "reg(FRAME:mul#3.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#3.itm#1)" {clk} -attr xrf 8656 -attr oid 377 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#3.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#3.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#3.itm#1(0)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(1)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(2)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(3)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(4)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(5)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(6)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(7)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(8)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load inst "reg(green:slc(green#2.sg1).itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 8657 -attr oid 378 -attr vt d -attr @path {/sobel/sobel:core/reg(green:slc(green#2.sg1).itm#1)}
+load net {ACC1:acc#44.itm(4)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC1:acc#44.itm(5)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC1:acc#44.itm(6)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC1:acc#44.itm(7)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC1:acc#44.itm(8)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC1:acc#44.itm(9)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(green:slc(green#2.sg1).itm#1)" {clk} -attr xrf 8658 -attr oid 379 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(green:slc(green#2.sg1).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {green:slc(green#2.sg1).itm#1(0)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(1)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(2)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(3)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(4)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(5)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load inst "FRAME:not#15" "not(1)" "INTERFACE" -attr xrf 8659 -attr oid 380 -attr @path {/sobel/sobel:core/FRAME:not#15} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#2.sva(5)} -pin  "FRAME:not#15" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#6.itm}
+load net {FRAME:not#15.itm} -pin  "FRAME:not#15" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#15.itm}
+load inst "FRAME:not#13" "not(3)" "INTERFACE" -attr xrf 8660 -attr oid 381 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#2.sva(3)} -pin  "FRAME:not#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#2.itm}
+load net {acc.imod#2.sva(4)} -pin  "FRAME:not#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#2.itm}
+load net {acc.imod#2.sva(5)} -pin  "FRAME:not#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#2.itm}
+load net {FRAME:not#13.itm(0)} -pin  "FRAME:not#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {FRAME:not#13.itm(1)} -pin  "FRAME:not#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {FRAME:not#13.itm(2)} -pin  "FRAME:not#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load inst "FRAME:not#12" "not(1)" "INTERFACE" -attr xrf 8661 -attr oid 382 -attr @path {/sobel/sobel:core/FRAME:not#12} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#2.sva(5)} -pin  "FRAME:not#12" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#3.itm}
+load net {FRAME:not#12.itm} -pin  "FRAME:not#12" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#12.itm}
+load inst "FRAME:acc#23" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 8662 -attr oid 383 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {PWR} -pin  "FRAME:acc#23" {A(0)} -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {acc.imod#2.sva(0)} -pin  "FRAME:acc#23" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {acc.imod#2.sva(1)} -pin  "FRAME:acc#23" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {acc.imod#2.sva(2)} -pin  "FRAME:acc#23" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {PWR} -pin  "FRAME:acc#23" {A(4)} -attr @path {/sobel/sobel:core/conc#133.itm}
+load net {FRAME:not#12.itm} -pin  "FRAME:acc#23" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(0)} -pin  "FRAME:acc#23" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(1)} -pin  "FRAME:acc#23" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(2)} -pin  "FRAME:acc#23" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:acc#23.itm(0)} -pin  "FRAME:acc#23" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(1)} -pin  "FRAME:acc#23" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(2)} -pin  "FRAME:acc#23" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(3)} -pin  "FRAME:acc#23" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(4)} -pin  "FRAME:acc#23" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load inst "FRAME:not#43" "not(1)" "INTERFACE" -attr xrf 8663 -attr oid 384 -attr @path {/sobel/sobel:core/FRAME:not#43} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#23.itm(4)} -pin  "FRAME:not#43" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#5.itm}
+load net {FRAME:not#43.itm} -pin  "FRAME:not#43" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#43.itm}
+load inst "FRAME:acc#17" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 8664 -attr oid 385 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#43.itm} -pin  "FRAME:acc#17" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {PWR} -pin  "FRAME:acc#17" {A(1)} -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {FRAME:not#15.itm} -pin  "FRAME:acc#17" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#132.itm}
+load net {acc.imod#2.sva(3)} -pin  "FRAME:acc#17" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#4.itm}
+load net {acc.imod#2.sva(4)} -pin  "FRAME:acc#17" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#4.itm}
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:acc#17" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:acc#17" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load inst "FRAME:not#14" "not(3)" "INTERFACE" -attr xrf 8665 -attr oid 386 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#44.itm(7)} -pin  "FRAME:not#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {ACC1:acc#44.itm(8)} -pin  "FRAME:not#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {ACC1:acc#44.itm(9)} -pin  "FRAME:not#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {FRAME:not#14.itm(0)} -pin  "FRAME:not#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(1)} -pin  "FRAME:not#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(2)} -pin  "FRAME:not#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load inst "FRAME:acc#18" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 8666 -attr oid 387 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:acc#18" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:acc#18" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:not#14.itm(0)} -pin  "FRAME:acc#18" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(1)} -pin  "FRAME:acc#18" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(2)} -pin  "FRAME:acc#18" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:acc#18.itm(0)} -pin  "FRAME:acc#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(1)} -pin  "FRAME:acc#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(2)} -pin  "FRAME:acc#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(3)} -pin  "FRAME:acc#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(4)} -pin  "FRAME:acc#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load inst "reg(FRAME:acc#18.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 8667 -attr oid 388 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#18.itm#1)}
+load net {FRAME:acc#18.itm(0)} -pin  "reg(FRAME:acc#18.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(1)} -pin  "reg(FRAME:acc#18.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(2)} -pin  "reg(FRAME:acc#18.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(3)} -pin  "reg(FRAME:acc#18.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(4)} -pin  "reg(FRAME:acc#18.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#18.itm#1)" {clk} -attr xrf 8668 -attr oid 389 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#18.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#18.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#18.itm#1(0)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(1)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(2)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(3)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(4)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load inst "reg(FRAME:slc(acc.imod#2)#4.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 8669 -attr oid 390 -attr @path {/sobel/sobel:core/reg(FRAME:slc(acc.imod#2)#4.itm#1)}
+load net {acc.imod#2.sva(5)} -pin  "reg(FRAME:slc(acc.imod#2)#4.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva).itm}
+load net {GND} -pin  "reg(FRAME:slc(acc.imod#2)#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(FRAME:slc(acc.imod#2)#4.itm#1)" {clk} -attr xrf 8670 -attr oid 391 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(acc.imod#2)#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(acc.imod#2)#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(acc.imod#2)#4.itm#1} -pin  "reg(FRAME:slc(acc.imod#2)#4.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:slc(acc.imod#2)#4.itm#1}
+load inst "reg(green:slc(green#2.sg1)#12.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 8671 -attr oid 392 -attr @path {/sobel/sobel:core/reg(green:slc(green#2.sg1)#12.itm#1)}
+load net {ACC1:acc#44.itm(15)} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva).itm}
+load net {GND} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {clk} -attr xrf 8672 -attr oid 393 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {green:slc(green#2.sg1)#12.itm#1} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/green:slc(green#2.sg1)#12.itm#1}
+load inst "FRAME:for:not#7" "not(1)" "INTERFACE" -attr xrf 8673 -attr oid 394 -attr @path {/sobel/sobel:core/FRAME:for:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:not#7" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#21.itm}
+load net {FRAME:for:not#7.itm} -pin  "FRAME:for:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#7.itm}
+load inst "reg(exit:FRAME:for.sva#1.st#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 8674 -attr oid 395 -attr vt c -attr @path {/sobel/sobel:core/reg(exit:FRAME:for.sva#1.st#1)}
+load net {FRAME:for:not#7.itm} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#7.itm}
+load net {GND} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {clk} -attr xrf 8675 -attr oid 396 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for.sva#1.st#1} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load inst "reg(i#6.sva#1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 8676 -attr oid 397 -attr vt d -attr @path {/sobel/sobel:core/reg(i#6.sva#1)}
+load net {i#6.sva#2(0)} -pin  "reg(i#6.sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "reg(i#6.sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {GND} -pin  "reg(i#6.sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(i#6.sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(i#6.sva#1)" {clk} -attr xrf 8677 -attr oid 398 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(i#6.sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(i#6.sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {i#6.sva#1(0)} -pin  "reg(i#6.sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "reg(i#6.sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load inst "FRAME:for:not" "not(1)" "INTERFACE" -attr xrf 8678 -attr oid 399 -attr @path {/sobel/sobel:core/FRAME:for:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#1.itm}
+load net {FRAME:for:not.itm} -pin  "FRAME:for:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load inst "FRAME:and" "and(2,1)" "INTERFACE" -attr xrf 8679 -attr oid 400 -attr @path {/sobel/sobel:core/FRAME:and} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {FRAME:for:not.itm} -pin  "FRAME:and" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "FRAME:and" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load net {FRAME:and.itm} -pin  "FRAME:and" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load inst "reg(exit:FRAME#1.sva)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 8680 -attr oid 401 -attr @path {/sobel/sobel:core/reg(exit:FRAME#1.sva)}
+load net {FRAME:and.itm} -pin  "reg(exit:FRAME#1.sva)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load net {PWR} -pin  "reg(exit:FRAME#1.sva)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1_Not}
+load net {clk} -pin  "reg(exit:FRAME#1.sva)" {clk} -attr xrf 8681 -attr oid 402 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME#1.sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME#1.sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME#1.sva} -pin  "reg(exit:FRAME#1.sva)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load inst "reg(main.stage_0#2)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 8682 -attr oid 403 -attr @path {/sobel/sobel:core/reg(main.stage_0#2)}
+load net {PWR} -pin  "reg(main.stage_0#2)" {D(0)} -attr @path {/sobel/sobel:core/Cn1_1#2}
+load net {GND} -pin  "reg(main.stage_0#2)" {DRa(0)} -attr @path {/sobel/sobel:core/Cn2_2#4}
+load net {clk} -pin  "reg(main.stage_0#2)" {clk} -attr xrf 8683 -attr oid 404 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(main.stage_0#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(main.stage_0#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {main.stage_0#2} -pin  "reg(main.stage_0#2)" {Z(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load inst "reg(regs.regs(2).lpi#1.dfm)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 8684 -attr oid 405 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(2).lpi#1.dfm)}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(30)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(31)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(32)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(33)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(34)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(35)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(36)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(37)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(38)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(39)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(40)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(41)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(42)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(43)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(44)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(45)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(46)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(47)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(48)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(49)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(50)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(51)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(52)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(53)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(54)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(55)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(56)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(57)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(58)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(59)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(60)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(61)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(62)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(63)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(64)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(65)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(66)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(67)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(68)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(69)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(70)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(71)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(72)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(73)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(74)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(75)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(76)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(77)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(78)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(79)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(80)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(81)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(82)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(83)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(84)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(85)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(86)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(87)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(88)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(89)} -attr @path {/sobel/sobel:core/C0_90}
+load net {clk} -pin  "reg(regs.regs(2).lpi#1.dfm)" {clk} -attr xrf 8685 -attr oid 406 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(2).lpi#1.dfm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(2).lpi#1.dfm(0)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(1)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(2)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(3)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(4)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(5)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(6)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(7)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(8)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(9)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(10)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(11)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(12)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(13)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(14)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(15)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(16)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(17)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(18)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(19)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(20)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(21)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(22)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(23)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(24)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(25)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(26)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(27)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(28)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(29)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(30)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(31)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(32)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(33)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(34)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(35)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(36)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(37)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(38)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(39)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(40)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(41)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(42)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(43)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(44)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(45)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(46)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(47)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(48)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(49)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(50)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(51)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(52)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(53)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(54)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(55)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(56)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(57)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(58)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(59)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(60)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(61)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(62)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(63)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(64)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(65)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(66)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(67)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(68)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(69)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(70)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(71)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(72)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(73)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(74)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(75)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(76)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(77)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(78)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(79)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(80)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(81)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(82)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(83)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(84)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(85)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(86)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(87)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(88)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(89)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load inst "reg(regs.regs(1).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 8686 -attr oid 407 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(1).sva)}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "reg(regs.regs(1).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "reg(regs.regs(1).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "reg(regs.regs(1).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "reg(regs.regs(1).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "reg(regs.regs(1).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "reg(regs.regs(1).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "reg(regs.regs(1).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "reg(regs.regs(1).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "reg(regs.regs(1).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "reg(regs.regs(1).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "reg(regs.regs(1).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "reg(regs.regs(1).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "reg(regs.regs(1).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "reg(regs.regs(1).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "reg(regs.regs(1).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "reg(regs.regs(1).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "reg(regs.regs(1).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "reg(regs.regs(1).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "reg(regs.regs(1).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "reg(regs.regs(1).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "reg(regs.regs(1).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "reg(regs.regs(1).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "reg(regs.regs(1).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "reg(regs.regs(1).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "reg(regs.regs(1).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "reg(regs.regs(1).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "reg(regs.regs(1).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "reg(regs.regs(1).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "reg(regs.regs(1).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "reg(regs.regs(1).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "reg(regs.regs(1).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "reg(regs.regs(1).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "reg(regs.regs(1).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "reg(regs.regs(1).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "reg(regs.regs(1).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "reg(regs.regs(1).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "reg(regs.regs(1).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "reg(regs.regs(1).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "reg(regs.regs(1).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "reg(regs.regs(1).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "reg(regs.regs(1).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "reg(regs.regs(1).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "reg(regs.regs(1).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "reg(regs.regs(1).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "reg(regs.regs(1).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "reg(regs.regs(1).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "reg(regs.regs(1).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "reg(regs.regs(1).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "reg(regs.regs(1).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "reg(regs.regs(1).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "reg(regs.regs(1).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "reg(regs.regs(1).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "reg(regs.regs(1).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "reg(regs.regs(1).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "reg(regs.regs(1).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "reg(regs.regs(1).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "reg(regs.regs(1).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "reg(regs.regs(1).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "reg(regs.regs(1).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "reg(regs.regs(1).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "reg(regs.regs(1).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "reg(regs.regs(1).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "reg(regs.regs(1).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "reg(regs.regs(1).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "reg(regs.regs(1).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "reg(regs.regs(1).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "reg(regs.regs(1).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "reg(regs.regs(1).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "reg(regs.regs(1).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "reg(regs.regs(1).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "reg(regs.regs(1).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "reg(regs.regs(1).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "reg(regs.regs(1).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "reg(regs.regs(1).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "reg(regs.regs(1).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "reg(regs.regs(1).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "reg(regs.regs(1).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "reg(regs.regs(1).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "reg(regs.regs(1).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "reg(regs.regs(1).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "reg(regs.regs(1).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "reg(regs.regs(1).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "reg(regs.regs(1).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "reg(regs.regs(1).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "reg(regs.regs(1).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "reg(regs.regs(1).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "reg(regs.regs(1).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "reg(regs.regs(1).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "reg(regs.regs(1).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "reg(regs.regs(1).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {clk} -pin  "reg(regs.regs(1).sva)" {clk} -attr xrf 8687 -attr oid 408 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(1).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(1).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(1).sva(0)} -pin  "reg(regs.regs(1).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "reg(regs.regs(1).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "reg(regs.regs(1).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "reg(regs.regs(1).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "reg(regs.regs(1).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "reg(regs.regs(1).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "reg(regs.regs(1).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "reg(regs.regs(1).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "reg(regs.regs(1).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "reg(regs.regs(1).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "reg(regs.regs(1).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "reg(regs.regs(1).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "reg(regs.regs(1).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "reg(regs.regs(1).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "reg(regs.regs(1).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "reg(regs.regs(1).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "reg(regs.regs(1).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "reg(regs.regs(1).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "reg(regs.regs(1).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "reg(regs.regs(1).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "reg(regs.regs(1).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "reg(regs.regs(1).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "reg(regs.regs(1).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "reg(regs.regs(1).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "reg(regs.regs(1).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "reg(regs.regs(1).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "reg(regs.regs(1).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "reg(regs.regs(1).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "reg(regs.regs(1).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "reg(regs.regs(1).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "reg(regs.regs(1).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "reg(regs.regs(1).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "reg(regs.regs(1).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "reg(regs.regs(1).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "reg(regs.regs(1).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "reg(regs.regs(1).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "reg(regs.regs(1).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "reg(regs.regs(1).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "reg(regs.regs(1).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "reg(regs.regs(1).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "reg(regs.regs(1).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "reg(regs.regs(1).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "reg(regs.regs(1).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "reg(regs.regs(1).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "reg(regs.regs(1).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "reg(regs.regs(1).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "reg(regs.regs(1).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "reg(regs.regs(1).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "reg(regs.regs(1).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "reg(regs.regs(1).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "reg(regs.regs(1).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "reg(regs.regs(1).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "reg(regs.regs(1).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "reg(regs.regs(1).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "reg(regs.regs(1).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "reg(regs.regs(1).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "reg(regs.regs(1).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "reg(regs.regs(1).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "reg(regs.regs(1).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "reg(regs.regs(1).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "reg(regs.regs(1).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "reg(regs.regs(1).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "reg(regs.regs(1).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "reg(regs.regs(1).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "reg(regs.regs(1).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "reg(regs.regs(1).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "reg(regs.regs(1).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "reg(regs.regs(1).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "reg(regs.regs(1).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "reg(regs.regs(1).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "reg(regs.regs(1).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "reg(regs.regs(1).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "reg(regs.regs(1).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "reg(regs.regs(1).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "reg(regs.regs(1).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "reg(regs.regs(1).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "reg(regs.regs(1).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "reg(regs.regs(1).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "reg(regs.regs(1).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "reg(regs.regs(1).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "reg(regs.regs(1).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "reg(regs.regs(1).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "reg(regs.regs(1).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "reg(regs.regs(1).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "reg(regs.regs(1).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "reg(regs.regs(1).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "reg(regs.regs(1).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "reg(regs.regs(1).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "reg(regs.regs(1).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "reg(regs.regs(1).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load inst "reg(regs.regs(0).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 8688 -attr oid 409 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva)}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "reg(regs.regs(0).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "reg(regs.regs(0).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "reg(regs.regs(0).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "reg(regs.regs(0).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "reg(regs.regs(0).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "reg(regs.regs(0).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "reg(regs.regs(0).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "reg(regs.regs(0).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "reg(regs.regs(0).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "reg(regs.regs(0).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "reg(regs.regs(0).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "reg(regs.regs(0).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "reg(regs.regs(0).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "reg(regs.regs(0).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "reg(regs.regs(0).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "reg(regs.regs(0).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "reg(regs.regs(0).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "reg(regs.regs(0).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "reg(regs.regs(0).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "reg(regs.regs(0).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "reg(regs.regs(0).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "reg(regs.regs(0).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "reg(regs.regs(0).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "reg(regs.regs(0).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "reg(regs.regs(0).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "reg(regs.regs(0).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "reg(regs.regs(0).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "reg(regs.regs(0).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "reg(regs.regs(0).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "reg(regs.regs(0).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "reg(regs.regs(0).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "reg(regs.regs(0).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "reg(regs.regs(0).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "reg(regs.regs(0).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "reg(regs.regs(0).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "reg(regs.regs(0).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "reg(regs.regs(0).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "reg(regs.regs(0).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "reg(regs.regs(0).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "reg(regs.regs(0).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "reg(regs.regs(0).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "reg(regs.regs(0).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "reg(regs.regs(0).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "reg(regs.regs(0).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "reg(regs.regs(0).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "reg(regs.regs(0).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "reg(regs.regs(0).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "reg(regs.regs(0).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "reg(regs.regs(0).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "reg(regs.regs(0).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "reg(regs.regs(0).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "reg(regs.regs(0).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "reg(regs.regs(0).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "reg(regs.regs(0).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "reg(regs.regs(0).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "reg(regs.regs(0).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "reg(regs.regs(0).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "reg(regs.regs(0).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "reg(regs.regs(0).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "reg(regs.regs(0).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "reg(regs.regs(0).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "reg(regs.regs(0).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "reg(regs.regs(0).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "reg(regs.regs(0).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "reg(regs.regs(0).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "reg(regs.regs(0).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "reg(regs.regs(0).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "reg(regs.regs(0).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "reg(regs.regs(0).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "reg(regs.regs(0).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "reg(regs.regs(0).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "reg(regs.regs(0).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "reg(regs.regs(0).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "reg(regs.regs(0).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "reg(regs.regs(0).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "reg(regs.regs(0).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "reg(regs.regs(0).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "reg(regs.regs(0).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "reg(regs.regs(0).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "reg(regs.regs(0).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "reg(regs.regs(0).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "reg(regs.regs(0).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "reg(regs.regs(0).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "reg(regs.regs(0).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "reg(regs.regs(0).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "reg(regs.regs(0).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "reg(regs.regs(0).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "reg(regs.regs(0).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "reg(regs.regs(0).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "reg(regs.regs(0).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {clk} -pin  "reg(regs.regs(0).sva)" {clk} -attr xrf 8689 -attr oid 410 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(0).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(0).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(0).sva(0)} -pin  "reg(regs.regs(0).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "reg(regs.regs(0).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "reg(regs.regs(0).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "reg(regs.regs(0).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "reg(regs.regs(0).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "reg(regs.regs(0).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "reg(regs.regs(0).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "reg(regs.regs(0).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "reg(regs.regs(0).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "reg(regs.regs(0).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "reg(regs.regs(0).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "reg(regs.regs(0).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "reg(regs.regs(0).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "reg(regs.regs(0).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "reg(regs.regs(0).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "reg(regs.regs(0).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "reg(regs.regs(0).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "reg(regs.regs(0).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "reg(regs.regs(0).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "reg(regs.regs(0).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "reg(regs.regs(0).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "reg(regs.regs(0).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "reg(regs.regs(0).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "reg(regs.regs(0).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "reg(regs.regs(0).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "reg(regs.regs(0).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "reg(regs.regs(0).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "reg(regs.regs(0).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "reg(regs.regs(0).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "reg(regs.regs(0).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "reg(regs.regs(0).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "reg(regs.regs(0).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "reg(regs.regs(0).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "reg(regs.regs(0).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "reg(regs.regs(0).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "reg(regs.regs(0).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "reg(regs.regs(0).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "reg(regs.regs(0).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "reg(regs.regs(0).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "reg(regs.regs(0).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "reg(regs.regs(0).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "reg(regs.regs(0).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "reg(regs.regs(0).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "reg(regs.regs(0).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "reg(regs.regs(0).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "reg(regs.regs(0).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "reg(regs.regs(0).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "reg(regs.regs(0).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "reg(regs.regs(0).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "reg(regs.regs(0).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "reg(regs.regs(0).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "reg(regs.regs(0).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "reg(regs.regs(0).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "reg(regs.regs(0).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "reg(regs.regs(0).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "reg(regs.regs(0).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "reg(regs.regs(0).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "reg(regs.regs(0).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "reg(regs.regs(0).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "reg(regs.regs(0).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "reg(regs.regs(0).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "reg(regs.regs(0).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "reg(regs.regs(0).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "reg(regs.regs(0).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "reg(regs.regs(0).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "reg(regs.regs(0).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "reg(regs.regs(0).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "reg(regs.regs(0).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "reg(regs.regs(0).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "reg(regs.regs(0).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "reg(regs.regs(0).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "reg(regs.regs(0).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "reg(regs.regs(0).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "reg(regs.regs(0).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "reg(regs.regs(0).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "reg(regs.regs(0).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "reg(regs.regs(0).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "reg(regs.regs(0).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "reg(regs.regs(0).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "reg(regs.regs(0).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "reg(regs.regs(0).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "reg(regs.regs(0).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "reg(regs.regs(0).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "reg(regs.regs(0).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "reg(regs.regs(0).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "reg(regs.regs(0).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "reg(regs.regs(0).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "reg(regs.regs(0).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "reg(regs.regs(0).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "reg(regs.regs(0).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load inst "reg(exit:FRAME.lpi#1.dfm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 8690 -attr oid 411 -attr @path {/sobel/sobel:core/reg(exit:FRAME.lpi#1.dfm#1)}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {D(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load net {GND} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {clk} -attr xrf 8691 -attr oid 412 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME.lpi#1.dfm#1} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1}
+load inst "reg(b(2).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 8692 -attr oid 413 -attr vt d -attr @path {/sobel/sobel:core/reg(b(2).sva#1)}
+load net {b(2).sva#3(0)} -pin  "reg(b(2).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(1)} -pin  "reg(b(2).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(2)} -pin  "reg(b(2).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(3)} -pin  "reg(b(2).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(4)} -pin  "reg(b(2).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(5)} -pin  "reg(b(2).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(6)} -pin  "reg(b(2).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(7)} -pin  "reg(b(2).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(8)} -pin  "reg(b(2).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(9)} -pin  "reg(b(2).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(10)} -pin  "reg(b(2).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(11)} -pin  "reg(b(2).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(12)} -pin  "reg(b(2).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(13)} -pin  "reg(b(2).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(14)} -pin  "reg(b(2).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(15)} -pin  "reg(b(2).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(b(2).sva#1)" {clk} -attr xrf 8693 -attr oid 414 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(b(2).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(b(2).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {b(2).sva#1(0)} -pin  "reg(b(2).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(1)} -pin  "reg(b(2).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(2)} -pin  "reg(b(2).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(3)} -pin  "reg(b(2).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(4)} -pin  "reg(b(2).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(5)} -pin  "reg(b(2).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(6)} -pin  "reg(b(2).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(7)} -pin  "reg(b(2).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(8)} -pin  "reg(b(2).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(9)} -pin  "reg(b(2).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(10)} -pin  "reg(b(2).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(11)} -pin  "reg(b(2).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(12)} -pin  "reg(b(2).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(13)} -pin  "reg(b(2).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(14)} -pin  "reg(b(2).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(15)} -pin  "reg(b(2).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load inst "reg(b(0).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 8694 -attr oid 415 -attr vt d -attr @path {/sobel/sobel:core/reg(b(0).sva#1)}
+load net {b(0).sva#3(0)} -pin  "reg(b(0).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(1)} -pin  "reg(b(0).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(2)} -pin  "reg(b(0).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(3)} -pin  "reg(b(0).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(4)} -pin  "reg(b(0).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(5)} -pin  "reg(b(0).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(6)} -pin  "reg(b(0).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(7)} -pin  "reg(b(0).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(8)} -pin  "reg(b(0).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(9)} -pin  "reg(b(0).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(10)} -pin  "reg(b(0).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(11)} -pin  "reg(b(0).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(12)} -pin  "reg(b(0).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(13)} -pin  "reg(b(0).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(14)} -pin  "reg(b(0).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(15)} -pin  "reg(b(0).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(b(0).sva#1)" {clk} -attr xrf 8695 -attr oid 416 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(b(0).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(b(0).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {b(0).sva#1(0)} -pin  "reg(b(0).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(1)} -pin  "reg(b(0).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(2)} -pin  "reg(b(0).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(3)} -pin  "reg(b(0).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(4)} -pin  "reg(b(0).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(5)} -pin  "reg(b(0).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(6)} -pin  "reg(b(0).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(7)} -pin  "reg(b(0).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(8)} -pin  "reg(b(0).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(9)} -pin  "reg(b(0).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(10)} -pin  "reg(b(0).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(11)} -pin  "reg(b(0).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(12)} -pin  "reg(b(0).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(13)} -pin  "reg(b(0).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(14)} -pin  "reg(b(0).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(15)} -pin  "reg(b(0).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load inst "reg(g(2).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 8696 -attr oid 417 -attr vt d -attr @path {/sobel/sobel:core/reg(g(2).sva#1)}
+load net {g(2).sva#3(0)} -pin  "reg(g(2).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(1)} -pin  "reg(g(2).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(2)} -pin  "reg(g(2).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(3)} -pin  "reg(g(2).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(4)} -pin  "reg(g(2).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(5)} -pin  "reg(g(2).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(6)} -pin  "reg(g(2).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(7)} -pin  "reg(g(2).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(8)} -pin  "reg(g(2).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(9)} -pin  "reg(g(2).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(10)} -pin  "reg(g(2).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(11)} -pin  "reg(g(2).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(12)} -pin  "reg(g(2).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(13)} -pin  "reg(g(2).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(14)} -pin  "reg(g(2).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(15)} -pin  "reg(g(2).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(g(2).sva#1)" {clk} -attr xrf 8697 -attr oid 418 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(g(2).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(g(2).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {g(2).sva#1(0)} -pin  "reg(g(2).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(1)} -pin  "reg(g(2).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(2)} -pin  "reg(g(2).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(3)} -pin  "reg(g(2).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(4)} -pin  "reg(g(2).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(5)} -pin  "reg(g(2).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(6)} -pin  "reg(g(2).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(7)} -pin  "reg(g(2).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(8)} -pin  "reg(g(2).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(9)} -pin  "reg(g(2).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(10)} -pin  "reg(g(2).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(11)} -pin  "reg(g(2).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(12)} -pin  "reg(g(2).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(13)} -pin  "reg(g(2).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(14)} -pin  "reg(g(2).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(15)} -pin  "reg(g(2).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load inst "reg(g(0).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 8698 -attr oid 419 -attr vt d -attr @path {/sobel/sobel:core/reg(g(0).sva#1)}
+load net {g(0).sva#3(0)} -pin  "reg(g(0).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(1)} -pin  "reg(g(0).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(2)} -pin  "reg(g(0).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(3)} -pin  "reg(g(0).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(4)} -pin  "reg(g(0).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(5)} -pin  "reg(g(0).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(6)} -pin  "reg(g(0).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(7)} -pin  "reg(g(0).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(8)} -pin  "reg(g(0).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(9)} -pin  "reg(g(0).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(10)} -pin  "reg(g(0).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(11)} -pin  "reg(g(0).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(12)} -pin  "reg(g(0).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(13)} -pin  "reg(g(0).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(14)} -pin  "reg(g(0).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(15)} -pin  "reg(g(0).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(g(0).sva#1)" {clk} -attr xrf 8699 -attr oid 420 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(g(0).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(g(0).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {g(0).sva#1(0)} -pin  "reg(g(0).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(1)} -pin  "reg(g(0).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(2)} -pin  "reg(g(0).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(3)} -pin  "reg(g(0).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(4)} -pin  "reg(g(0).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(5)} -pin  "reg(g(0).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(6)} -pin  "reg(g(0).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(7)} -pin  "reg(g(0).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(8)} -pin  "reg(g(0).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(9)} -pin  "reg(g(0).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(10)} -pin  "reg(g(0).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(11)} -pin  "reg(g(0).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(12)} -pin  "reg(g(0).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(13)} -pin  "reg(g(0).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(14)} -pin  "reg(g(0).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(15)} -pin  "reg(g(0).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load inst "reg(r(2).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 8700 -attr oid 421 -attr vt d -attr @path {/sobel/sobel:core/reg(r(2).sva#1)}
+load net {r(2).sva#3(0)} -pin  "reg(r(2).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(1)} -pin  "reg(r(2).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(2)} -pin  "reg(r(2).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(3)} -pin  "reg(r(2).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(4)} -pin  "reg(r(2).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(5)} -pin  "reg(r(2).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(6)} -pin  "reg(r(2).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(7)} -pin  "reg(r(2).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(8)} -pin  "reg(r(2).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(9)} -pin  "reg(r(2).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(10)} -pin  "reg(r(2).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(11)} -pin  "reg(r(2).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(12)} -pin  "reg(r(2).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(13)} -pin  "reg(r(2).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(14)} -pin  "reg(r(2).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(15)} -pin  "reg(r(2).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(r(2).sva#1)" {clk} -attr xrf 8701 -attr oid 422 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(r(2).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(r(2).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {r(2).sva#1(0)} -pin  "reg(r(2).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(1)} -pin  "reg(r(2).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(2)} -pin  "reg(r(2).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(3)} -pin  "reg(r(2).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(4)} -pin  "reg(r(2).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(5)} -pin  "reg(r(2).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(6)} -pin  "reg(r(2).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(7)} -pin  "reg(r(2).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(8)} -pin  "reg(r(2).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(9)} -pin  "reg(r(2).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(10)} -pin  "reg(r(2).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(11)} -pin  "reg(r(2).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(12)} -pin  "reg(r(2).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(13)} -pin  "reg(r(2).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(14)} -pin  "reg(r(2).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(15)} -pin  "reg(r(2).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load inst "reg(r(0).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 8702 -attr oid 423 -attr vt d -attr @path {/sobel/sobel:core/reg(r(0).sva#1)}
+load net {r(0).sva#3(0)} -pin  "reg(r(0).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(1)} -pin  "reg(r(0).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(2)} -pin  "reg(r(0).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(3)} -pin  "reg(r(0).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(4)} -pin  "reg(r(0).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(5)} -pin  "reg(r(0).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(6)} -pin  "reg(r(0).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(7)} -pin  "reg(r(0).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(8)} -pin  "reg(r(0).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(9)} -pin  "reg(r(0).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(10)} -pin  "reg(r(0).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(11)} -pin  "reg(r(0).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(12)} -pin  "reg(r(0).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(13)} -pin  "reg(r(0).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(14)} -pin  "reg(r(0).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(15)} -pin  "reg(r(0).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(r(0).sva#1)" {clk} -attr xrf 8703 -attr oid 424 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(r(0).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(r(0).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {r(0).sva#1(0)} -pin  "reg(r(0).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(1)} -pin  "reg(r(0).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(2)} -pin  "reg(r(0).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(3)} -pin  "reg(r(0).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(4)} -pin  "reg(r(0).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(5)} -pin  "reg(r(0).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(6)} -pin  "reg(r(0).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(7)} -pin  "reg(r(0).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(8)} -pin  "reg(r(0).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(9)} -pin  "reg(r(0).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(10)} -pin  "reg(r(0).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(11)} -pin  "reg(r(0).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(12)} -pin  "reg(r(0).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(13)} -pin  "reg(r(0).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(14)} -pin  "reg(r(0).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(15)} -pin  "reg(r(0).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load inst "mux#5" "mux(2,19)" "INTERFACE" -attr xrf 8704 -attr oid 425 -attr vt d -attr @path {/sobel/sobel:core/mux#5} -attr area 17.470037 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2)"
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "mux#5" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "mux#5" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "mux#5" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "mux#5" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "mux#5" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "mux#5" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "mux#5" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "mux#5" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "mux#5" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "mux#5" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "mux#5" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "mux#5" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "mux#5" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "mux#5" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "mux#5" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "mux#5" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "mux#5" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "mux#5" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "mux#5" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.sva#1(0)} -pin  "mux#5" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "mux#5" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "mux#5" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "mux#5" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "mux#5" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "mux#5" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "mux#5" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "mux#5" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "mux#5" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "mux#5" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "mux#5" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "mux#5" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "mux#5" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "mux#5" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "mux#5" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "mux#5" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "mux#5" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "mux#5" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "mux#5" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:for:acc.itm(1)} -pin  "mux#5" {S(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#22.itm}
+load net {mux#5.itm(0)} -pin  "mux#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(1)} -pin  "mux#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(2)} -pin  "mux#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(3)} -pin  "mux#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(4)} -pin  "mux#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(5)} -pin  "mux#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(6)} -pin  "mux#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(7)} -pin  "mux#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(8)} -pin  "mux#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(9)} -pin  "mux#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(10)} -pin  "mux#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(11)} -pin  "mux#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(12)} -pin  "mux#5" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(13)} -pin  "mux#5" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(14)} -pin  "mux#5" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(15)} -pin  "mux#5" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(16)} -pin  "mux#5" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(17)} -pin  "mux#5" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(18)} -pin  "mux#5" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load inst "reg(FRAME:p#1.lpi#1)" "reg(19,1,1,-1,0)" "INTERFACE" -attr xrf 8705 -attr oid 426 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:p#1.lpi#1)}
+load net {mux#5.itm(0)} -pin  "reg(FRAME:p#1.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(1)} -pin  "reg(FRAME:p#1.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(2)} -pin  "reg(FRAME:p#1.lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(3)} -pin  "reg(FRAME:p#1.lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(4)} -pin  "reg(FRAME:p#1.lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(5)} -pin  "reg(FRAME:p#1.lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(6)} -pin  "reg(FRAME:p#1.lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(7)} -pin  "reg(FRAME:p#1.lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(8)} -pin  "reg(FRAME:p#1.lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(9)} -pin  "reg(FRAME:p#1.lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(10)} -pin  "reg(FRAME:p#1.lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(11)} -pin  "reg(FRAME:p#1.lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(12)} -pin  "reg(FRAME:p#1.lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(13)} -pin  "reg(FRAME:p#1.lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(14)} -pin  "reg(FRAME:p#1.lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(15)} -pin  "reg(FRAME:p#1.lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(16)} -pin  "reg(FRAME:p#1.lpi#1)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(17)} -pin  "reg(FRAME:p#1.lpi#1)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(18)} -pin  "reg(FRAME:p#1.lpi#1)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_19}
+load net {clk} -pin  "reg(FRAME:p#1.lpi#1)" {clk} -attr xrf 8706 -attr oid 427 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:p#1.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:p#1.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:p#1.lpi#1(0)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load inst "FRAME:acc#19" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 8707 -attr oid 428 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {FRAME:acc#18.itm#1(0)} -pin  "FRAME:acc#19" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(1)} -pin  "FRAME:acc#19" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(2)} -pin  "FRAME:acc#19" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(3)} -pin  "FRAME:acc#19" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(4)} -pin  "FRAME:acc#19" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:slc(acc.imod#2)#4.itm#1} -pin  "FRAME:acc#19" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {PWR} -pin  "FRAME:acc#19" {B(1)} -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {GND} -pin  "FRAME:acc#19" {B(2)} -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {GND} -pin  "FRAME:acc#19" {B(3)} -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {PWR} -pin  "FRAME:acc#19" {B(4)} -attr @path {/sobel/sobel:core/conc#134.itm}
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#19" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#19" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#19" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(3)} -pin  "FRAME:acc#19" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(4)} -pin  "FRAME:acc#19" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load inst "FRAME:acc#20" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 8708 -attr oid 429 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {green:slc(green#2.sg1).itm#1(0)} -pin  "FRAME:acc#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(1)} -pin  "FRAME:acc#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(2)} -pin  "FRAME:acc#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(3)} -pin  "FRAME:acc#20" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(4)} -pin  "FRAME:acc#20" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(5)} -pin  "FRAME:acc#20" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#20" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#20" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#20" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(3)} -pin  "FRAME:acc#20" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(4)} -pin  "FRAME:acc#20" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#20.itm(0)} -pin  "FRAME:acc#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(1)} -pin  "FRAME:acc#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(2)} -pin  "FRAME:acc#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(3)} -pin  "FRAME:acc#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(4)} -pin  "FRAME:acc#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(5)} -pin  "FRAME:acc#20" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(6)} -pin  "FRAME:acc#20" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(7)} -pin  "FRAME:acc#20" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load inst "FRAME:acc#21" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 8709 -attr oid 430 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul#3.itm#1(0)} -pin  "FRAME:acc#21" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(1)} -pin  "FRAME:acc#21" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(2)} -pin  "FRAME:acc#21" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(3)} -pin  "FRAME:acc#21" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(4)} -pin  "FRAME:acc#21" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(5)} -pin  "FRAME:acc#21" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(6)} -pin  "FRAME:acc#21" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(7)} -pin  "FRAME:acc#21" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(8)} -pin  "FRAME:acc#21" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:acc#20.itm(0)} -pin  "FRAME:acc#21" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(1)} -pin  "FRAME:acc#21" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(2)} -pin  "FRAME:acc#21" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(3)} -pin  "FRAME:acc#21" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(4)} -pin  "FRAME:acc#21" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(5)} -pin  "FRAME:acc#21" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(6)} -pin  "FRAME:acc#21" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(7)} -pin  "FRAME:acc#21" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#21.itm(0)} -pin  "FRAME:acc#21" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(1)} -pin  "FRAME:acc#21" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(2)} -pin  "FRAME:acc#21" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(3)} -pin  "FRAME:acc#21" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(4)} -pin  "FRAME:acc#21" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(5)} -pin  "FRAME:acc#21" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(6)} -pin  "FRAME:acc#21" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(7)} -pin  "FRAME:acc#21" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(8)} -pin  "FRAME:acc#21" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(9)} -pin  "FRAME:acc#21" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load inst "FRAME:acc#22" "add(11,0,10,1,12)" "INTERFACE" -attr xrf 8710 -attr oid 431 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12)"
+load net {FRAME:mul#2.itm#1(0)} -pin  "FRAME:acc#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(1)} -pin  "FRAME:acc#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(2)} -pin  "FRAME:acc#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(3)} -pin  "FRAME:acc#22" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
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+load net {FRAME:acc#33.itm(6)} -pin  "FRAME:acc#33" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(7)} -pin  "FRAME:acc#33" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(8)} -pin  "FRAME:acc#33" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(9)} -pin  "FRAME:acc#33" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load inst "FRAME:acc#34" "add(11,0,10,1,12)" "INTERFACE" -attr xrf 8715 -attr oid 436 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12)"
+load net {FRAME:mul#4.itm#1(0)} -pin  "FRAME:acc#34" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(1)} -pin  "FRAME:acc#34" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(2)} -pin  "FRAME:acc#34" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(3)} -pin  "FRAME:acc#34" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(4)} -pin  "FRAME:acc#34" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(5)} -pin  "FRAME:acc#34" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(6)} -pin  "FRAME:acc#34" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(7)} -pin  "FRAME:acc#34" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(8)} -pin  "FRAME:acc#34" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(9)} -pin  "FRAME:acc#34" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(10)} -pin  "FRAME:acc#34" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:acc#33.itm(0)} -pin  "FRAME:acc#34" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(1)} -pin  "FRAME:acc#34" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(2)} -pin  "FRAME:acc#34" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(3)} -pin  "FRAME:acc#34" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(4)} -pin  "FRAME:acc#34" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(5)} -pin  "FRAME:acc#34" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(6)} -pin  "FRAME:acc#34" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(7)} -pin  "FRAME:acc#34" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(8)} -pin  "FRAME:acc#34" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(9)} -pin  "FRAME:acc#34" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#34.itm(0)} -pin  "FRAME:acc#34" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(1)} -pin  "FRAME:acc#34" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(2)} -pin  "FRAME:acc#34" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(3)} -pin  "FRAME:acc#34" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(4)} -pin  "FRAME:acc#34" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(5)} -pin  "FRAME:acc#34" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(6)} -pin  "FRAME:acc#34" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(7)} -pin  "FRAME:acc#34" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(8)} -pin  "FRAME:acc#34" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(9)} -pin  "FRAME:acc#34" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(10)} -pin  "FRAME:acc#34" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(11)} -pin  "FRAME:acc#34" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load inst "FRAME:acc#4" "add(12,-1,11,0,12)" "INTERFACE" -attr xrf 8716 -attr oid 437 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {FRAME:acc#34.itm(0)} -pin  "FRAME:acc#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(1)} -pin  "FRAME:acc#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(2)} -pin  "FRAME:acc#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(3)} -pin  "FRAME:acc#4" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(4)} -pin  "FRAME:acc#4" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(5)} -pin  "FRAME:acc#4" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(6)} -pin  "FRAME:acc#4" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(7)} -pin  "FRAME:acc#4" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(8)} -pin  "FRAME:acc#4" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(9)} -pin  "FRAME:acc#4" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(10)} -pin  "FRAME:acc#4" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(11)} -pin  "FRAME:acc#4" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(1)} -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(5)} -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(6)} -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(7)} -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/exs#2.itm}
+load net {FRAME:acc#4.psp.sva(0)} -pin  "FRAME:acc#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(1)} -pin  "FRAME:acc#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(2)} -pin  "FRAME:acc#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(3)} -pin  "FRAME:acc#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(4)} -pin  "FRAME:acc#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(5)} -pin  "FRAME:acc#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(6)} -pin  "FRAME:acc#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(7)} -pin  "FRAME:acc#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(8)} -pin  "FRAME:acc#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(9)} -pin  "FRAME:acc#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(10)} -pin  "FRAME:acc#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(11)} -pin  "FRAME:acc#4" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load inst "FRAME:for:acc" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 8717 -attr oid 438 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2)"
+load net {i#6.sva#2(0)} -pin  "FRAME:for:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "FRAME:for:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {PWR} -pin  "FRAME:for:acc" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:for:acc.itm(0)} -pin  "FRAME:for:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+load inst "FRAME:for:acc#16" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 8718 -attr oid 439 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#16} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:for:acc#16" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {i#6.sva#2(0)} -pin  "FRAME:for:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "FRAME:for:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load inst "not#40" "not(1)" "INTERFACE" -attr xrf 8719 -attr oid 440 -attr @path {/sobel/sobel:core/not#40} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "not#40" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {not#40.itm} -pin  "not#40" {Z(0)} -attr @path {/sobel/sobel:core/not#40.itm}
+load inst "FRAME:for:and#1" "and(2,2)" "INTERFACE" -attr xrf 8720 -attr oid 441 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#1} -attr area 1.459665 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2)"
+load net {i#6.sva#1(0)} -pin  "FRAME:for:and#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "FRAME:for:and#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {not#40.itm} -pin  "FRAME:for:and#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#19.itm}
+load net {not#40.itm} -pin  "FRAME:for:and#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#19.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:and#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:and#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load inst "FRAME:for:or" "or(2,1)" "INTERFACE" -attr xrf 8721 -attr oid 442 -attr @path {/sobel/sobel:core/FRAME:for:or} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "FRAME:for:or" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {exit:FRAME#1.sva} -pin  "FRAME:for:or" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:or" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load inst "mux#1" "mux(2,90)" "INTERFACE" -attr xrf 8722 -attr oid 443 -attr vt dc -attr @path {/sobel/sobel:core/mux#1} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(2).lpi#1.dfm(0)} -pin  "mux#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(1)} -pin  "mux#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(2)} -pin  "mux#1" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(3)} -pin  "mux#1" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(4)} -pin  "mux#1" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(5)} -pin  "mux#1" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(6)} -pin  "mux#1" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(7)} -pin  "mux#1" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(8)} -pin  "mux#1" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(9)} -pin  "mux#1" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(10)} -pin  "mux#1" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(11)} -pin  "mux#1" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(12)} -pin  "mux#1" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(13)} -pin  "mux#1" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(14)} -pin  "mux#1" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(15)} -pin  "mux#1" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(16)} -pin  "mux#1" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(17)} -pin  "mux#1" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(18)} -pin  "mux#1" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(19)} -pin  "mux#1" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(20)} -pin  "mux#1" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(21)} -pin  "mux#1" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(22)} -pin  "mux#1" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(23)} -pin  "mux#1" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(24)} -pin  "mux#1" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(25)} -pin  "mux#1" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(26)} -pin  "mux#1" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(27)} -pin  "mux#1" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(28)} -pin  "mux#1" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(29)} -pin  "mux#1" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(30)} -pin  "mux#1" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(31)} -pin  "mux#1" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(32)} -pin  "mux#1" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(33)} -pin  "mux#1" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(34)} -pin  "mux#1" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(35)} -pin  "mux#1" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(36)} -pin  "mux#1" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(37)} -pin  "mux#1" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(38)} -pin  "mux#1" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(39)} -pin  "mux#1" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(40)} -pin  "mux#1" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(41)} -pin  "mux#1" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(42)} -pin  "mux#1" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(43)} -pin  "mux#1" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(44)} -pin  "mux#1" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(45)} -pin  "mux#1" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(46)} -pin  "mux#1" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(47)} -pin  "mux#1" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(48)} -pin  "mux#1" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(49)} -pin  "mux#1" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(50)} -pin  "mux#1" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(51)} -pin  "mux#1" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(52)} -pin  "mux#1" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(53)} -pin  "mux#1" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(54)} -pin  "mux#1" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(55)} -pin  "mux#1" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(56)} -pin  "mux#1" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(57)} -pin  "mux#1" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(58)} -pin  "mux#1" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(59)} -pin  "mux#1" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(60)} -pin  "mux#1" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(61)} -pin  "mux#1" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(62)} -pin  "mux#1" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(63)} -pin  "mux#1" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(64)} -pin  "mux#1" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(65)} -pin  "mux#1" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(66)} -pin  "mux#1" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(67)} -pin  "mux#1" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(68)} -pin  "mux#1" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(69)} -pin  "mux#1" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(70)} -pin  "mux#1" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(71)} -pin  "mux#1" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(72)} -pin  "mux#1" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(73)} -pin  "mux#1" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(74)} -pin  "mux#1" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(75)} -pin  "mux#1" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(76)} -pin  "mux#1" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(77)} -pin  "mux#1" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(78)} -pin  "mux#1" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(79)} -pin  "mux#1" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(80)} -pin  "mux#1" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(81)} -pin  "mux#1" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(82)} -pin  "mux#1" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(83)} -pin  "mux#1" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(84)} -pin  "mux#1" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(85)} -pin  "mux#1" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(86)} -pin  "mux#1" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(87)} -pin  "mux#1" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(88)} -pin  "mux#1" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(89)} -pin  "mux#1" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(1).sva(0)} -pin  "mux#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "mux#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "mux#1" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "mux#1" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "mux#1" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "mux#1" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "mux#1" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "mux#1" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "mux#1" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "mux#1" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "mux#1" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "mux#1" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "mux#1" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "mux#1" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "mux#1" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "mux#1" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "mux#1" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "mux#1" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "mux#1" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "mux#1" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "mux#1" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "mux#1" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "mux#1" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "mux#1" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "mux#1" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "mux#1" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "mux#1" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "mux#1" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "mux#1" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "mux#1" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "mux#1" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "mux#1" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "mux#1" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "mux#1" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "mux#1" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "mux#1" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "mux#1" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "mux#1" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "mux#1" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "mux#1" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "mux#1" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "mux#1" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "mux#1" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "mux#1" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "mux#1" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "mux#1" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "mux#1" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "mux#1" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "mux#1" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "mux#1" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "mux#1" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "mux#1" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "mux#1" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "mux#1" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "mux#1" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "mux#1" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "mux#1" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "mux#1" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "mux#1" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "mux#1" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "mux#1" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "mux#1" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "mux#1" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "mux#1" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "mux#1" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "mux#1" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "mux#1" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "mux#1" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "mux#1" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "mux#1" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "mux#1" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "mux#1" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "mux#1" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "mux#1" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "mux#1" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "mux#1" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "mux#1" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "mux#1" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "mux#1" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "mux#1" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "mux#1" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "mux#1" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "mux#1" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "mux#1" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "mux#1" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "mux#1" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "mux#1" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "mux#1" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "mux#1" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "mux#1" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {and.dcpl} -pin  "mux#1" {S(0)} -attr vt c -attr @path {/sobel/sobel:core/and.dcpl}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "mux#1" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "mux#1" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "mux#1" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "mux#1" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "mux#1" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "mux#1" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "mux#1" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "mux#1" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "mux#1" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "mux#1" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "mux#1" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "mux#1" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "mux#1" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "mux#1" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "mux#1" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "mux#1" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "mux#1" {Z(16)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "mux#1" {Z(17)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "mux#1" {Z(18)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "mux#1" {Z(19)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "mux#1" {Z(20)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "mux#1" {Z(21)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "mux#1" {Z(22)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "mux#1" {Z(23)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "mux#1" {Z(24)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "mux#1" {Z(25)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "mux#1" {Z(26)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "mux#1" {Z(27)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "mux#1" {Z(28)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "mux#1" {Z(29)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "mux#1" {Z(30)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "mux#1" {Z(31)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "mux#1" {Z(32)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "mux#1" {Z(33)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "mux#1" {Z(34)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "mux#1" {Z(35)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "mux#1" {Z(36)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "mux#1" {Z(37)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "mux#1" {Z(38)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "mux#1" {Z(39)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "mux#1" {Z(40)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "mux#1" {Z(41)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "mux#1" {Z(42)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "mux#1" {Z(43)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "mux#1" {Z(44)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "mux#1" {Z(45)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "mux#1" {Z(46)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "mux#1" {Z(47)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "mux#1" {Z(48)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "mux#1" {Z(49)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "mux#1" {Z(50)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "mux#1" {Z(51)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "mux#1" {Z(52)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "mux#1" {Z(53)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "mux#1" {Z(54)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "mux#1" {Z(55)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "mux#1" {Z(56)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "mux#1" {Z(57)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "mux#1" {Z(58)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "mux#1" {Z(59)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "mux#1" {Z(60)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "mux#1" {Z(61)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "mux#1" {Z(62)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "mux#1" {Z(63)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "mux#1" {Z(64)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "mux#1" {Z(65)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "mux#1" {Z(66)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "mux#1" {Z(67)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "mux#1" {Z(68)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "mux#1" {Z(69)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "mux#1" {Z(70)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "mux#1" {Z(71)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "mux#1" {Z(72)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "mux#1" {Z(73)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "mux#1" {Z(74)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "mux#1" {Z(75)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "mux#1" {Z(76)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "mux#1" {Z(77)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "mux#1" {Z(78)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "mux#1" {Z(79)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "mux#1" {Z(80)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "mux#1" {Z(81)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "mux#1" {Z(82)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "mux#1" {Z(83)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "mux#1" {Z(84)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "mux#1" {Z(85)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "mux#1" {Z(86)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "mux#1" {Z(87)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "mux#1" {Z(88)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "mux#1" {Z(89)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load inst "mux#2" "mux(2,90)" "INTERFACE" -attr xrf 8723 -attr oid 444 -attr vt d -attr @path {/sobel/sobel:core/mux#2} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(1).sva(0)} -pin  "mux#2" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "mux#2" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "mux#2" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "mux#2" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "mux#2" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "mux#2" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "mux#2" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "mux#2" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "mux#2" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "mux#2" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "mux#2" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "mux#2" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "mux#2" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "mux#2" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "mux#2" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "mux#2" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "mux#2" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "mux#2" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "mux#2" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "mux#2" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "mux#2" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "mux#2" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "mux#2" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "mux#2" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "mux#2" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "mux#2" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "mux#2" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "mux#2" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "mux#2" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "mux#2" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "mux#2" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "mux#2" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "mux#2" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "mux#2" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "mux#2" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "mux#2" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "mux#2" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "mux#2" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "mux#2" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "mux#2" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "mux#2" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "mux#2" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "mux#2" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "mux#2" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "mux#2" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "mux#2" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "mux#2" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "mux#2" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "mux#2" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "mux#2" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "mux#2" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "mux#2" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "mux#2" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "mux#2" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "mux#2" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "mux#2" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "mux#2" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "mux#2" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "mux#2" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "mux#2" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "mux#2" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "mux#2" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "mux#2" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "mux#2" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "mux#2" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "mux#2" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "mux#2" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "mux#2" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "mux#2" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "mux#2" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "mux#2" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "mux#2" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "mux#2" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "mux#2" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "mux#2" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "mux#2" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "mux#2" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "mux#2" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "mux#2" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "mux#2" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "mux#2" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "mux#2" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "mux#2" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "mux#2" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "mux#2" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "mux#2" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "mux#2" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "mux#2" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "mux#2" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "mux#2" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -pin  "mux#2" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#2" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#2" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#2" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#2" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#2" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#2" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#2" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#2" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#2" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#2" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#2" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#2" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#2" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#2" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#2" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#2" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#2" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#2" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#2" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#2" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#2" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#2" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#2" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#2" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#2" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#2" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#2" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#2" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#2" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#2" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#2" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#2" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#2" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#2" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#2" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#2" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#2" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#2" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#2" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#2" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#2" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#2" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#2" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#2" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#2" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#2" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#2" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#2" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#2" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#2" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#2" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#2" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#2" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#2" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#2" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#2" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#2" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#2" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#2" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#2" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#2" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#2" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#2" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#2" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#2" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#2" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#2" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#2" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#2" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#2" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#2" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#2" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#2" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#2" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#2" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#2" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#2" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#2" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#2" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#2" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#2" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#2" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#2" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#2" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#2" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#2" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#2" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#2" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#2" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {and.dcpl} -pin  "mux#2" {S(0)} -attr @path {/sobel/sobel:core/and.dcpl}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "mux#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "mux#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "mux#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "mux#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "mux#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "mux#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "mux#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "mux#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "mux#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "mux#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "mux#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "mux#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "mux#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "mux#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "mux#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "mux#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "mux#2" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "mux#2" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "mux#2" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "mux#2" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "mux#2" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "mux#2" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "mux#2" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "mux#2" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "mux#2" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "mux#2" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "mux#2" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "mux#2" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "mux#2" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "mux#2" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "mux#2" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "mux#2" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "mux#2" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "mux#2" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "mux#2" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "mux#2" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "mux#2" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "mux#2" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "mux#2" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "mux#2" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "mux#2" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "mux#2" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "mux#2" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "mux#2" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "mux#2" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "mux#2" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "mux#2" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "mux#2" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "mux#2" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "mux#2" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "mux#2" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "mux#2" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "mux#2" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "mux#2" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "mux#2" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "mux#2" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "mux#2" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "mux#2" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "mux#2" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "mux#2" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "mux#2" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "mux#2" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "mux#2" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "mux#2" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "mux#2" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "mux#2" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "mux#2" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "mux#2" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "mux#2" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "mux#2" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "mux#2" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "mux#2" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "mux#2" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "mux#2" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "mux#2" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "mux#2" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "mux#2" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "mux#2" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "mux#2" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "mux#2" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "mux#2" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "mux#2" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "mux#2" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "mux#2" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "mux#2" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "mux#2" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "mux#2" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "mux#2" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "mux#2" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "mux#2" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load inst "mux#3" "mux(2,90)" "INTERFACE" -attr xrf 8724 -attr oid 445 -attr vt d -attr @path {/sobel/sobel:core/mux#3} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(0).sva(0)} -pin  "mux#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#3" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#3" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#3" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#3" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#3" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#3" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#3" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#3" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#3" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#3" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#3" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#3" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#3" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#3" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#3" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#3" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#3" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#3" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#3" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#3" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#3" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#3" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#3" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#3" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#3" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#3" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#3" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#3" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#3" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#3" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#3" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#3" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#3" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#3" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#3" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#3" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#3" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#3" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#3" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#3" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#3" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#3" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#3" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#3" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#3" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#3" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#3" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#3" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#3" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#3" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#3" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#3" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#3" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#3" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#3" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#3" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#3" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#3" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#3" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#3" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#3" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#3" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#3" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#3" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#3" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#3" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#3" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#3" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#3" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#3" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#3" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#3" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#3" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#3" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#3" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#3" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#3" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#3" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#3" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#3" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#3" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#3" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#3" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#3" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#3" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "mux#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "mux#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "mux#3" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "mux#3" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "mux#3" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "mux#3" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "mux#3" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "mux#3" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "mux#3" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "mux#3" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "mux#3" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "mux#3" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "mux#3" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "mux#3" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "mux#3" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "mux#3" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "mux#3" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "mux#3" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "mux#3" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "mux#3" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "mux#3" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "mux#3" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "mux#3" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "mux#3" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "mux#3" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "mux#3" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "mux#3" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "mux#3" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "mux#3" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "mux#3" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "mux#3" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "mux#3" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "mux#3" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "mux#3" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "mux#3" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "mux#3" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "mux#3" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "mux#3" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "mux#3" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "mux#3" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "mux#3" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "mux#3" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "mux#3" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "mux#3" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "mux#3" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "mux#3" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "mux#3" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "mux#3" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "mux#3" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "mux#3" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "mux#3" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "mux#3" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "mux#3" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "mux#3" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "mux#3" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "mux#3" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "mux#3" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "mux#3" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "mux#3" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "mux#3" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "mux#3" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "mux#3" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "mux#3" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "mux#3" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "mux#3" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "mux#3" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "mux#3" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "mux#3" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "mux#3" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "mux#3" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "mux#3" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "mux#3" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "mux#3" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "mux#3" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "mux#3" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "mux#3" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "mux#3" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "mux#3" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "mux#3" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "mux#3" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "mux#3" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "mux#3" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "mux#3" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "mux#3" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "mux#3" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "mux#3" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "mux#3" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "mux#3" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "mux#3" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "mux#3" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {and.dcpl} -pin  "mux#3" {S(0)} -attr @path {/sobel/sobel:core/and.dcpl}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "mux#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "mux#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "mux#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "mux#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "mux#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "mux#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "mux#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "mux#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "mux#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "mux#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "mux#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "mux#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "mux#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "mux#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "mux#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "mux#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "mux#3" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "mux#3" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "mux#3" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "mux#3" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "mux#3" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "mux#3" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "mux#3" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "mux#3" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "mux#3" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "mux#3" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "mux#3" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "mux#3" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "mux#3" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "mux#3" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "mux#3" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "mux#3" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "mux#3" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "mux#3" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "mux#3" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "mux#3" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "mux#3" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "mux#3" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "mux#3" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "mux#3" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "mux#3" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "mux#3" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "mux#3" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "mux#3" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "mux#3" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "mux#3" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "mux#3" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "mux#3" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "mux#3" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "mux#3" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "mux#3" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "mux#3" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "mux#3" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "mux#3" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "mux#3" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "mux#3" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "mux#3" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "mux#3" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "mux#3" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "mux#3" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "mux#3" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "mux#3" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "mux#3" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "mux#3" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "mux#3" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "mux#3" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "mux#3" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "mux#3" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "mux#3" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "mux#3" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "mux#3" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "mux#3" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "mux#3" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "mux#3" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "mux#3" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "mux#3" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "mux#3" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "mux#3" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "mux#3" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "mux#3" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "mux#3" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "mux#3" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "mux#3" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "mux#3" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "mux#3" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "mux#3" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "mux#3" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "mux#3" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "mux#3" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "mux#3" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load inst "not#16" "not(1)" "INTERFACE" -attr xrf 8725 -attr oid 446 -attr @path {/sobel/sobel:core/not#16} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "not#16" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {not#16.itm} -pin  "not#16" {Z(0)} -attr @path {/sobel/sobel:core/not#16.itm}
+load inst "FRAME:for:and#2" "and(2,1)" "INTERFACE" -attr xrf 8726 -attr oid 447 -attr @path {/sobel/sobel:core/FRAME:for:and#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {exit:FRAME.lpi#1.dfm#1} -pin  "FRAME:for:and#2" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1}
+load net {not#16.itm} -pin  "FRAME:for:and#2" {A1(0)} -attr @path {/sobel/sobel:core/not#16.itm}
+load net {FRAME:for:and#2.itm} -pin  "FRAME:for:and#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#2.itm}
+load inst "FRAME:acc" "add(7,0,8,-1,8)" "INTERFACE" -attr xrf 8727 -attr oid 448 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc} -attr area 9.262368 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,7,0,8)"
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {PWR} -pin  "FRAME:acc" {B(0)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(1)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(2)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(3)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(4)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(5)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(6)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(7)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {FRAME:acc.itm(0)} -pin  "FRAME:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(1)} -pin  "FRAME:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(2)} -pin  "FRAME:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(3)} -pin  "FRAME:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(4)} -pin  "FRAME:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(5)} -pin  "FRAME:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(6)} -pin  "FRAME:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(7)} -pin  "FRAME:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load inst "FRAME:not" "not(1)" "INTERFACE" -attr xrf 8728 -attr oid 449 -attr @path {/sobel/sobel:core/FRAME:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc.itm(7)} -pin  "FRAME:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc.itm}
+load net {FRAME:not.itm} -pin  "FRAME:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load inst "mux#4" "mux(2,1)" "INTERFACE" -attr xrf 8729 -attr oid 450 -attr @path {/sobel/sobel:core/mux#4} -attr area 0.920423 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2)"
+load net {FRAME:for:and#2.itm} -pin  "mux#4" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#2.itm}
+load net {FRAME:not.itm} -pin  "mux#4" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "mux#4" {S(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc.itm}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "mux#4" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load inst "FRAME:acc#6" "add(19,-1,1,0,19)" "INTERFACE" -attr xrf 8730 -attr oid 451 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6} -attr area 20.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19)"
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "FRAME:acc#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "FRAME:acc#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "FRAME:acc#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "FRAME:acc#6" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "FRAME:acc#6" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "FRAME:acc#6" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "FRAME:acc#6" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "FRAME:acc#6" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "FRAME:acc#6" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "FRAME:acc#6" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "FRAME:acc#6" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "FRAME:acc#6" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "FRAME:acc#6" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "FRAME:acc#6" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "FRAME:acc#6" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "FRAME:acc#6" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "FRAME:acc#6" {A(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "FRAME:acc#6" {A(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "FRAME:acc#6" {A(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:acc#6" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:p#1.sva#1(0)} -pin  "FRAME:acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "FRAME:acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "FRAME:acc#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "FRAME:acc#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "FRAME:acc#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "FRAME:acc#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "FRAME:acc#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "FRAME:acc#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "FRAME:acc#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "FRAME:acc#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "FRAME:acc#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "FRAME:acc#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc#6" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc#6" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc#6" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc#6" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc#6" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc#6" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc#6" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load inst "FRAME:not#28" "not(1)" "INTERFACE" -attr xrf 8731 -attr oid 452 -attr @path {/sobel/sobel:core/FRAME:not#28} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME#1.sva} -pin  "FRAME:not#28" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {FRAME:not#28.itm} -pin  "FRAME:not#28" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#28.itm}
+load inst "FRAME:for:and" "and(2,19)" "INTERFACE" -attr xrf 8732 -attr oid 453 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and} -attr area 13.866816 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2)"
+load net {FRAME:p#1.lpi#1(0)} -pin  "FRAME:for:and" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "FRAME:for:and" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "FRAME:for:and" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "FRAME:for:and" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "FRAME:for:and" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "FRAME:for:and" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "FRAME:for:and" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "FRAME:for:and" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "FRAME:for:and" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "FRAME:for:and" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "FRAME:for:and" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "FRAME:for:and" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "FRAME:for:and" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "FRAME:for:and" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "FRAME:for:and" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "FRAME:for:and" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "FRAME:for:and" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "FRAME:for:and" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "FRAME:for:and" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "FRAME:for:and" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "FRAME:for:and" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "FRAME:for:and" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "FRAME:for:and" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "FRAME:for:and" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "FRAME:for:and" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "FRAME:for:and" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "FRAME:for:and" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "FRAME:for:and" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "FRAME:for:and" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "FRAME:for:and" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "FRAME:for:and" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "FRAME:for:and" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "FRAME:for:and" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "FRAME:for:and" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "FRAME:for:and" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "FRAME:for:and" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "FRAME:for:and" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "FRAME:for:and" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load inst "FRAME:not#2" "not(3)" "INTERFACE" -attr xrf 8733 -attr oid 454 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#43.itm(10)} -pin  "FRAME:not#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#2.itm}
+load net {ACC1:acc#43.itm(11)} -pin  "FRAME:not#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#2.itm}
+load net {ACC1:acc#43.itm(12)} -pin  "FRAME:not#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#2.itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:not#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:not#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:not#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load inst "FRAME:acc#8" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 8734 -attr oid 455 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#43.itm(7)} -pin  "FRAME:acc#8" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva).itm}
+load net {ACC1:acc#43.itm(8)} -pin  "FRAME:acc#8" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva).itm}
+load net {ACC1:acc#43.itm(9)} -pin  "FRAME:acc#8" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva).itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:acc#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:acc#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:acc#8" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#8" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#8" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#8" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#8" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load inst "FRAME:not#35" "not(1)" "INTERFACE" -attr xrf 8735 -attr oid 456 -attr @path {/sobel/sobel:core/FRAME:not#35} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:not#35" {A(0)} -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#20.itm}
+load net {FRAME:not#35.itm} -pin  "FRAME:not#35" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#35.itm}
+load inst "FRAME:not#45" "not(1)" "INTERFACE" -attr xrf 8736 -attr oid 457 -attr @path {/sobel/sobel:core/FRAME:not#45} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#43.itm(15)} -pin  "FRAME:not#45" {A(0)} -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#10.itm}
+load net {FRAME:not#45.itm} -pin  "FRAME:not#45" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#45.itm}
+load inst "FRAME:acc#7" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 8737 -attr oid 458 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#45.itm} -pin  "FRAME:acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {PWR} -pin  "FRAME:acc#7" {A(1)} -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {FRAME:not#35.itm} -pin  "FRAME:acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {ACC1:acc#43.itm(13)} -pin  "FRAME:acc#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#5.itm}
+load net {ACC1:acc#43.itm(14)} -pin  "FRAME:acc#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#5.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load inst "FRAME:acc#10" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 8738 -attr oid 459 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#10" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#10" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#10" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#10" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#10" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#10" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#10" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#10" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#10" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#10" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(4)} -pin  "FRAME:acc#10" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load inst "FRAME:not#1" "not(3)" "INTERFACE" -attr xrf 8739 -attr oid 460 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#43.itm(4)} -pin  "FRAME:not#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {ACC1:acc#43.itm(5)} -pin  "FRAME:not#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {ACC1:acc#43.itm(6)} -pin  "FRAME:not#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:not#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:not#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:not#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load inst "FRAME:acc#9" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 8740 -attr oid 461 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#43.itm(1)} -pin  "FRAME:acc#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {ACC1:acc#43.itm(2)} -pin  "FRAME:acc#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {ACC1:acc#43.itm(3)} -pin  "FRAME:acc#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:acc#9" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:acc#9" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:acc#9" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load inst "FRAME:acc#11" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 8741 -attr oid 462 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11} -attr area 6.288444 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6)"
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#11" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#11" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#11" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#11" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(4)} -pin  "FRAME:acc#11" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#11" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#11" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#11" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#11" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#11" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#11" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#11" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#11" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "FRAME:acc#11" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(5)} -pin  "FRAME:acc#11" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load inst "acc" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 8742 -attr oid 463 -attr vt dc -attr @path {/sobel/sobel:core/acc} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {FRAME:acc#11.itm(0)} -pin  "acc" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "acc" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "acc" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "acc" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "acc" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(5)} -pin  "acc" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {PWR} -pin  "acc" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod.sva(0)} -pin  "acc" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(1)} -pin  "acc" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(2)} -pin  "acc" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(3)} -pin  "acc" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(4)} -pin  "acc" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(5)} -pin  "acc" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load inst "ACC2:not" "not(10)" "INTERFACE" -attr xrf 8743 -attr oid 464 -attr vt d -attr @path {/sobel/sobel:core/ACC2:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "ACC2:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "ACC2:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "ACC2:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "ACC2:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "ACC2:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "ACC2:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "ACC2:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "ACC2:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "ACC2:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "ACC2:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {ACC2:not.itm(0)} -pin  "ACC2:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(1)} -pin  "ACC2:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(2)} -pin  "ACC2:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(3)} -pin  "ACC2:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(4)} -pin  "ACC2:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(5)} -pin  "ACC2:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(6)} -pin  "ACC2:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(7)} -pin  "ACC2:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(8)} -pin  "ACC2:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load net {ACC2:not.itm(9)} -pin  "ACC2:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load inst "acc#5" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 8744 -attr oid 465 -attr vt d -attr @path {/sobel/sobel:core/acc#5} -attr area 12.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "acc#5" {A(0)} -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(0)} -pin  "acc#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(1)} -pin  "acc#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(2)} -pin  "acc#5" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(3)} -pin  "acc#5" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(4)} -pin  "acc#5" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(5)} -pin  "acc#5" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(6)} -pin  "acc#5" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(7)} -pin  "acc#5" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(8)} -pin  "acc#5" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {ACC2:not.itm(9)} -pin  "acc#5" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {PWR} -pin  "acc#5" {B(0)} -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "acc#5" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "acc#5" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "acc#5" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "acc#5" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "acc#5" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "acc#5" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "acc#5" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "acc#5" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "acc#5" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "acc#5" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {acc#5.itm(0)} -pin  "acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(1)} -pin  "acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(2)} -pin  "acc#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(3)} -pin  "acc#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(4)} -pin  "acc#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(5)} -pin  "acc#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(6)} -pin  "acc#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(7)} -pin  "acc#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(8)} -pin  "acc#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(9)} -pin  "acc#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(10)} -pin  "acc#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load net {acc#5.itm(11)} -pin  "acc#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#5.itm}
+load inst "ACC1:acc#62" "add(11,1,15,-1,15)" "INTERFACE" -attr xrf 8745 -attr oid 466 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62} -attr area 16.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {acc#5.itm(1)} -pin  "ACC1:acc#62" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(2)} -pin  "ACC1:acc#62" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(3)} -pin  "ACC1:acc#62" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(4)} -pin  "ACC1:acc#62" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(5)} -pin  "ACC1:acc#62" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(6)} -pin  "ACC1:acc#62" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(7)} -pin  "ACC1:acc#62" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(8)} -pin  "ACC1:acc#62" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(9)} -pin  "ACC1:acc#62" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(10)} -pin  "ACC1:acc#62" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc#5.itm(11)} -pin  "ACC1:acc#62" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {r(2).sva#3(1)} -pin  "ACC1:acc#62" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(2)} -pin  "ACC1:acc#62" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(3)} -pin  "ACC1:acc#62" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(4)} -pin  "ACC1:acc#62" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(5)} -pin  "ACC1:acc#62" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(6)} -pin  "ACC1:acc#62" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(7)} -pin  "ACC1:acc#62" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(8)} -pin  "ACC1:acc#62" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(9)} -pin  "ACC1:acc#62" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(10)} -pin  "ACC1:acc#62" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(11)} -pin  "ACC1:acc#62" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(12)} -pin  "ACC1:acc#62" {B(11)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(13)} -pin  "ACC1:acc#62" {B(12)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(14)} -pin  "ACC1:acc#62" {B(13)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(15)} -pin  "ACC1:acc#62" {B(14)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {ACC1:acc#62.itm(0)} -pin  "ACC1:acc#62" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(1)} -pin  "ACC1:acc#62" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(2)} -pin  "ACC1:acc#62" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(3)} -pin  "ACC1:acc#62" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(4)} -pin  "ACC1:acc#62" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(5)} -pin  "ACC1:acc#62" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(6)} -pin  "ACC1:acc#62" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(7)} -pin  "ACC1:acc#62" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(8)} -pin  "ACC1:acc#62" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(9)} -pin  "ACC1:acc#62" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(10)} -pin  "ACC1:acc#62" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(11)} -pin  "ACC1:acc#62" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(12)} -pin  "ACC1:acc#62" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(13)} -pin  "ACC1:acc#62" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(14)} -pin  "ACC1:acc#62" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load inst "ACC1:acc#61" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 8746 -attr oid 467 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#61} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {PWR} -pin  "ACC1:acc#61" {A(0)} -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {r(2).sva#3(0)} -pin  "ACC1:acc#61" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {PWR} -pin  "ACC1:acc#61" {B(0)} -attr @path {/sobel/sobel:core/Cn1_1#3}
+load net {ACC1:acc#61.itm(0)} -pin  "ACC1:acc#61" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#61.itm}
+load net {ACC1:acc#61.itm(1)} -pin  "ACC1:acc#61" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#61.itm}
+load inst "ACC1:acc#43" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 8747 -attr oid 468 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {ACC1:acc#61.itm(1)} -pin  "ACC1:acc#43" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(0)} -pin  "ACC1:acc#43" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(1)} -pin  "ACC1:acc#43" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(2)} -pin  "ACC1:acc#43" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(3)} -pin  "ACC1:acc#43" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(4)} -pin  "ACC1:acc#43" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(5)} -pin  "ACC1:acc#43" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(6)} -pin  "ACC1:acc#43" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(7)} -pin  "ACC1:acc#43" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(8)} -pin  "ACC1:acc#43" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(9)} -pin  "ACC1:acc#43" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(10)} -pin  "ACC1:acc#43" {A(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(11)} -pin  "ACC1:acc#43" {A(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(12)} -pin  "ACC1:acc#43" {A(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(13)} -pin  "ACC1:acc#43" {A(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#62.itm(14)} -pin  "ACC1:acc#43" {A(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {r(0).sva#3(0)} -pin  "ACC1:acc#43" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(1)} -pin  "ACC1:acc#43" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(2)} -pin  "ACC1:acc#43" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(3)} -pin  "ACC1:acc#43" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(4)} -pin  "ACC1:acc#43" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(5)} -pin  "ACC1:acc#43" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(6)} -pin  "ACC1:acc#43" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(7)} -pin  "ACC1:acc#43" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(8)} -pin  "ACC1:acc#43" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(9)} -pin  "ACC1:acc#43" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(10)} -pin  "ACC1:acc#43" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(11)} -pin  "ACC1:acc#43" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(12)} -pin  "ACC1:acc#43" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(13)} -pin  "ACC1:acc#43" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(14)} -pin  "ACC1:acc#43" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(15)} -pin  "ACC1:acc#43" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {ACC1:acc#43.itm(0)} -pin  "ACC1:acc#43" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(1)} -pin  "ACC1:acc#43" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(2)} -pin  "ACC1:acc#43" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(3)} -pin  "ACC1:acc#43" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(4)} -pin  "ACC1:acc#43" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(5)} -pin  "ACC1:acc#43" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(6)} -pin  "ACC1:acc#43" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(7)} -pin  "ACC1:acc#43" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(8)} -pin  "ACC1:acc#43" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(9)} -pin  "ACC1:acc#43" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(10)} -pin  "ACC1:acc#43" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(11)} -pin  "ACC1:acc#43" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(12)} -pin  "ACC1:acc#43" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(13)} -pin  "ACC1:acc#43" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(14)} -pin  "ACC1:acc#43" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(15)} -pin  "ACC1:acc#43" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load inst "FRAME:mul" "mul(2,0,9,0,10)" "INTERFACE" -attr xrf 8748 -attr oid 469 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC1:acc#43.itm(13)} -pin  "FRAME:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#12.itm}
+load net {ACC1:acc#43.itm(14)} -pin  "FRAME:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#12.itm}
+load net {PWR} -pin  "FRAME:mul" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul.sdt(0)} -pin  "FRAME:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(1)} -pin  "FRAME:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(2)} -pin  "FRAME:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(3)} -pin  "FRAME:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(4)} -pin  "FRAME:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(5)} -pin  "FRAME:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(6)} -pin  "FRAME:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(7)} -pin  "FRAME:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(8)} -pin  "FRAME:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(9)} -pin  "FRAME:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load inst "ACC2:not#4" "not(10)" "INTERFACE" -attr xrf 8749 -attr oid 470 -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "ACC2:not#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "ACC2:not#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "ACC2:not#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "ACC2:not#4" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "ACC2:not#4" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "ACC2:not#4" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "ACC2:not#4" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "ACC2:not#4" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "ACC2:not#4" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "ACC2:not#4" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {ACC2:not#4.itm(0)} -pin  "ACC2:not#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(1)} -pin  "ACC2:not#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(2)} -pin  "ACC2:not#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(3)} -pin  "ACC2:not#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(4)} -pin  "ACC2:not#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(5)} -pin  "ACC2:not#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(6)} -pin  "ACC2:not#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(7)} -pin  "ACC2:not#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(8)} -pin  "ACC2:not#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load net {ACC2:not#4.itm(9)} -pin  "ACC2:not#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#4.itm}
+load inst "acc#6" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 8750 -attr oid 471 -attr vt d -attr @path {/sobel/sobel:core/acc#6} -attr area 12.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "acc#6" {A(0)} -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(0)} -pin  "acc#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(1)} -pin  "acc#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(2)} -pin  "acc#6" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(3)} -pin  "acc#6" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(4)} -pin  "acc#6" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(5)} -pin  "acc#6" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(6)} -pin  "acc#6" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(7)} -pin  "acc#6" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(8)} -pin  "acc#6" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {ACC2:not#4.itm(9)} -pin  "acc#6" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {PWR} -pin  "acc#6" {B(0)} -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "acc#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "acc#6" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "acc#6" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "acc#6" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "acc#6" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "acc#6" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "acc#6" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "acc#6" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "acc#6" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "acc#6" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {acc#6.itm(0)} -pin  "acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(1)} -pin  "acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(2)} -pin  "acc#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(3)} -pin  "acc#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(4)} -pin  "acc#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(5)} -pin  "acc#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(6)} -pin  "acc#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(7)} -pin  "acc#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(8)} -pin  "acc#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(9)} -pin  "acc#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(10)} -pin  "acc#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load net {acc#6.itm(11)} -pin  "acc#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#6.itm}
+load inst "ACC1:acc#70" "add(11,1,15,-1,15)" "INTERFACE" -attr xrf 8751 -attr oid 472 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70} -attr area 16.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {acc#6.itm(1)} -pin  "ACC1:acc#70" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(2)} -pin  "ACC1:acc#70" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(3)} -pin  "ACC1:acc#70" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(4)} -pin  "ACC1:acc#70" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(5)} -pin  "ACC1:acc#70" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(6)} -pin  "ACC1:acc#70" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(7)} -pin  "ACC1:acc#70" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(8)} -pin  "ACC1:acc#70" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(9)} -pin  "ACC1:acc#70" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(10)} -pin  "ACC1:acc#70" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#6.itm(11)} -pin  "ACC1:acc#70" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {b(2).sva#3(1)} -pin  "ACC1:acc#70" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(2)} -pin  "ACC1:acc#70" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(3)} -pin  "ACC1:acc#70" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(4)} -pin  "ACC1:acc#70" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(5)} -pin  "ACC1:acc#70" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(6)} -pin  "ACC1:acc#70" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(7)} -pin  "ACC1:acc#70" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(8)} -pin  "ACC1:acc#70" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(9)} -pin  "ACC1:acc#70" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(10)} -pin  "ACC1:acc#70" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(11)} -pin  "ACC1:acc#70" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(12)} -pin  "ACC1:acc#70" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(13)} -pin  "ACC1:acc#70" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(14)} -pin  "ACC1:acc#70" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(15)} -pin  "ACC1:acc#70" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {ACC1:acc#70.itm(0)} -pin  "ACC1:acc#70" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(1)} -pin  "ACC1:acc#70" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(2)} -pin  "ACC1:acc#70" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(3)} -pin  "ACC1:acc#70" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(4)} -pin  "ACC1:acc#70" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(5)} -pin  "ACC1:acc#70" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(6)} -pin  "ACC1:acc#70" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(7)} -pin  "ACC1:acc#70" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(8)} -pin  "ACC1:acc#70" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(9)} -pin  "ACC1:acc#70" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(10)} -pin  "ACC1:acc#70" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(11)} -pin  "ACC1:acc#70" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(12)} -pin  "ACC1:acc#70" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(13)} -pin  "ACC1:acc#70" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load net {ACC1:acc#70.itm(14)} -pin  "ACC1:acc#70" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#70.itm}
+load inst "ACC1:acc#69" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 8752 -attr oid 473 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#69} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {PWR} -pin  "ACC1:acc#69" {A(0)} -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {b(2).sva#3(0)} -pin  "ACC1:acc#69" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {PWR} -pin  "ACC1:acc#69" {B(0)} -attr @path {/sobel/sobel:core/Cn1_1#3}
+load net {ACC1:acc#69.itm(0)} -pin  "ACC1:acc#69" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#69.itm}
+load net {ACC1:acc#69.itm(1)} -pin  "ACC1:acc#69" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#69.itm}
+load inst "ACC1:acc#45" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 8753 -attr oid 474 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {ACC1:acc#69.itm(1)} -pin  "ACC1:acc#45" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(0)} -pin  "ACC1:acc#45" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(1)} -pin  "ACC1:acc#45" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(2)} -pin  "ACC1:acc#45" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(3)} -pin  "ACC1:acc#45" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(4)} -pin  "ACC1:acc#45" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(5)} -pin  "ACC1:acc#45" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(6)} -pin  "ACC1:acc#45" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(7)} -pin  "ACC1:acc#45" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(8)} -pin  "ACC1:acc#45" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(9)} -pin  "ACC1:acc#45" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(10)} -pin  "ACC1:acc#45" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(11)} -pin  "ACC1:acc#45" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(12)} -pin  "ACC1:acc#45" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(13)} -pin  "ACC1:acc#45" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#70.itm(14)} -pin  "ACC1:acc#45" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {b(0).sva#3(0)} -pin  "ACC1:acc#45" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(1)} -pin  "ACC1:acc#45" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(2)} -pin  "ACC1:acc#45" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(3)} -pin  "ACC1:acc#45" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(4)} -pin  "ACC1:acc#45" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(5)} -pin  "ACC1:acc#45" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(6)} -pin  "ACC1:acc#45" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(7)} -pin  "ACC1:acc#45" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(8)} -pin  "ACC1:acc#45" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(9)} -pin  "ACC1:acc#45" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(10)} -pin  "ACC1:acc#45" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(11)} -pin  "ACC1:acc#45" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(12)} -pin  "ACC1:acc#45" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(13)} -pin  "ACC1:acc#45" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(14)} -pin  "ACC1:acc#45" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(15)} -pin  "ACC1:acc#45" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {ACC1:acc#45.itm(0)} -pin  "ACC1:acc#45" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(1)} -pin  "ACC1:acc#45" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(2)} -pin  "ACC1:acc#45" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(3)} -pin  "ACC1:acc#45" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(4)} -pin  "ACC1:acc#45" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(5)} -pin  "ACC1:acc#45" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(6)} -pin  "ACC1:acc#45" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(7)} -pin  "ACC1:acc#45" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(8)} -pin  "ACC1:acc#45" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(9)} -pin  "ACC1:acc#45" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(10)} -pin  "ACC1:acc#45" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "ACC1:acc#45" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(12)} -pin  "ACC1:acc#45" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(13)} -pin  "ACC1:acc#45" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(14)} -pin  "ACC1:acc#45" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(15)} -pin  "ACC1:acc#45" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load inst "FRAME:not#18" "not(3)" "INTERFACE" -attr xrf 8754 -attr oid 475 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#45.itm(10)} -pin  "FRAME:not#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "FRAME:not#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {ACC1:acc#45.itm(12)} -pin  "FRAME:not#18" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {FRAME:not#18.itm(0)} -pin  "FRAME:not#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(1)} -pin  "FRAME:not#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(2)} -pin  "FRAME:not#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load inst "FRAME:acc#25" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 8755 -attr oid 476 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#45.itm(7)} -pin  "FRAME:acc#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {ACC1:acc#45.itm(8)} -pin  "FRAME:acc#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {ACC1:acc#45.itm(9)} -pin  "FRAME:acc#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {FRAME:not#18.itm(0)} -pin  "FRAME:acc#25" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(1)} -pin  "FRAME:acc#25" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(2)} -pin  "FRAME:acc#25" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:acc#25.itm(0)} -pin  "FRAME:acc#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(1)} -pin  "FRAME:acc#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(2)} -pin  "FRAME:acc#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(3)} -pin  "FRAME:acc#25" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load inst "FRAME:not#36" "not(1)" "INTERFACE" -attr xrf 8756 -attr oid 477 -attr @path {/sobel/sobel:core/FRAME:not#36} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#45.itm(15)} -pin  "FRAME:not#36" {A(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#12.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:not#36" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#36.itm}
+load inst "FRAME:not#47" "not(1)" "INTERFACE" -attr xrf 8757 -attr oid 478 -attr @path {/sobel/sobel:core/FRAME:not#47} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#45.itm(15)} -pin  "FRAME:not#47" {A(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#7.itm}
+load net {FRAME:not#47.itm} -pin  "FRAME:not#47" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#47.itm}
+load inst "FRAME:acc#24" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 8758 -attr oid 479 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#47.itm} -pin  "FRAME:acc#24" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {PWR} -pin  "FRAME:acc#24" {A(1)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:acc#24" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {ACC1:acc#45.itm(13)} -pin  "FRAME:acc#24" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#4.itm}
+load net {ACC1:acc#45.itm(14)} -pin  "FRAME:acc#24" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#4.itm}
+load net {FRAME:acc#24.itm(0)} -pin  "FRAME:acc#24" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(1)} -pin  "FRAME:acc#24" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(2)} -pin  "FRAME:acc#24" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(3)} -pin  "FRAME:acc#24" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load inst "FRAME:acc#27" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 8759 -attr oid 480 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#25.itm(0)} -pin  "FRAME:acc#27" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(1)} -pin  "FRAME:acc#27" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(2)} -pin  "FRAME:acc#27" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(3)} -pin  "FRAME:acc#27" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#24.itm(0)} -pin  "FRAME:acc#27" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(1)} -pin  "FRAME:acc#27" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(2)} -pin  "FRAME:acc#27" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(3)} -pin  "FRAME:acc#27" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#27.itm(0)} -pin  "FRAME:acc#27" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(1)} -pin  "FRAME:acc#27" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(2)} -pin  "FRAME:acc#27" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(3)} -pin  "FRAME:acc#27" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(4)} -pin  "FRAME:acc#27" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load inst "FRAME:not#17" "not(3)" "INTERFACE" -attr xrf 8760 -attr oid 481 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#45.itm(4)} -pin  "FRAME:not#17" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {ACC1:acc#45.itm(5)} -pin  "FRAME:not#17" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {ACC1:acc#45.itm(6)} -pin  "FRAME:not#17" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {FRAME:not#17.itm(0)} -pin  "FRAME:not#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(1)} -pin  "FRAME:not#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(2)} -pin  "FRAME:not#17" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load inst "FRAME:acc#26" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 8761 -attr oid 482 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#45.itm(1)} -pin  "FRAME:acc#26" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {ACC1:acc#45.itm(2)} -pin  "FRAME:acc#26" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {ACC1:acc#45.itm(3)} -pin  "FRAME:acc#26" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {FRAME:not#17.itm(0)} -pin  "FRAME:acc#26" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(1)} -pin  "FRAME:acc#26" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(2)} -pin  "FRAME:acc#26" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:acc#26.itm(0)} -pin  "FRAME:acc#26" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(1)} -pin  "FRAME:acc#26" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(2)} -pin  "FRAME:acc#26" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(3)} -pin  "FRAME:acc#26" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load inst "FRAME:acc#28" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 8762 -attr oid 483 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28} -attr area 6.288444 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6)"
+load net {FRAME:acc#27.itm(0)} -pin  "FRAME:acc#28" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(1)} -pin  "FRAME:acc#28" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(2)} -pin  "FRAME:acc#28" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(3)} -pin  "FRAME:acc#28" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(4)} -pin  "FRAME:acc#28" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#26.itm(0)} -pin  "FRAME:acc#28" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(1)} -pin  "FRAME:acc#28" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(2)} -pin  "FRAME:acc#28" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(3)} -pin  "FRAME:acc#28" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#28.itm(0)} -pin  "FRAME:acc#28" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(1)} -pin  "FRAME:acc#28" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(2)} -pin  "FRAME:acc#28" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(3)} -pin  "FRAME:acc#28" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(4)} -pin  "FRAME:acc#28" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(5)} -pin  "FRAME:acc#28" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load inst "acc#4" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 8763 -attr oid 484 -attr vt d -attr @path {/sobel/sobel:core/acc#4} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {FRAME:acc#28.itm(0)} -pin  "acc#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(1)} -pin  "acc#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(2)} -pin  "acc#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(3)} -pin  "acc#4" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(4)} -pin  "acc#4" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(5)} -pin  "acc#4" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {PWR} -pin  "acc#4" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#4" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#4" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#4" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#4" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#4" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#4.sva(0)} -pin  "acc#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#4.sva}
+load net {acc.imod#4.sva(1)} -pin  "acc#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#4.sva}
+load net {acc.imod#4.sva(2)} -pin  "acc#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#4.sva}
+load net {acc.imod#4.sva(3)} -pin  "acc#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#4.sva}
+load net {acc.imod#4.sva(4)} -pin  "acc#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#4.sva}
+load net {acc.imod#4.sva(5)} -pin  "acc#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#4.sva}
+load inst "ACC2:not#3" "not(10)" "INTERFACE" -attr xrf 8764 -attr oid 485 -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "ACC2:not#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "ACC2:not#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "ACC2:not#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "ACC2:not#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "ACC2:not#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "ACC2:not#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "ACC2:not#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "ACC2:not#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "ACC2:not#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "ACC2:not#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {ACC2:not#3.itm(0)} -pin  "ACC2:not#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(1)} -pin  "ACC2:not#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(2)} -pin  "ACC2:not#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(3)} -pin  "ACC2:not#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(4)} -pin  "ACC2:not#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(5)} -pin  "ACC2:not#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(6)} -pin  "ACC2:not#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(7)} -pin  "ACC2:not#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(8)} -pin  "ACC2:not#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load net {ACC2:not#3.itm(9)} -pin  "ACC2:not#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:not#3.itm}
+load inst "acc#7" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 8765 -attr oid 486 -attr vt d -attr @path {/sobel/sobel:core/acc#7} -attr area 12.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "acc#7" {A(0)} -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(0)} -pin  "acc#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(1)} -pin  "acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(2)} -pin  "acc#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(3)} -pin  "acc#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(4)} -pin  "acc#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(5)} -pin  "acc#7" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(6)} -pin  "acc#7" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(7)} -pin  "acc#7" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(8)} -pin  "acc#7" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {ACC2:not#3.itm(9)} -pin  "acc#7" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {PWR} -pin  "acc#7" {B(0)} -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "acc#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "acc#7" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "acc#7" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "acc#7" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "acc#7" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "acc#7" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "acc#7" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "acc#7" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "acc#7" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "acc#7" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {acc#7.itm(0)} -pin  "acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(1)} -pin  "acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(2)} -pin  "acc#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(3)} -pin  "acc#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(4)} -pin  "acc#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(5)} -pin  "acc#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(6)} -pin  "acc#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(7)} -pin  "acc#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(8)} -pin  "acc#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(9)} -pin  "acc#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(10)} -pin  "acc#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load net {acc#7.itm(11)} -pin  "acc#7" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#7.itm}
+load inst "ACC1:acc#66" "add(11,1,15,-1,15)" "INTERFACE" -attr xrf 8766 -attr oid 487 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66} -attr area 16.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {acc#7.itm(1)} -pin  "ACC1:acc#66" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(2)} -pin  "ACC1:acc#66" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(3)} -pin  "ACC1:acc#66" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(4)} -pin  "ACC1:acc#66" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(5)} -pin  "ACC1:acc#66" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(6)} -pin  "ACC1:acc#66" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(7)} -pin  "ACC1:acc#66" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(8)} -pin  "ACC1:acc#66" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(9)} -pin  "ACC1:acc#66" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(10)} -pin  "ACC1:acc#66" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#7.itm(11)} -pin  "ACC1:acc#66" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {g(2).sva#3(1)} -pin  "ACC1:acc#66" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(2)} -pin  "ACC1:acc#66" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(3)} -pin  "ACC1:acc#66" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(4)} -pin  "ACC1:acc#66" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(5)} -pin  "ACC1:acc#66" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(6)} -pin  "ACC1:acc#66" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(7)} -pin  "ACC1:acc#66" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(8)} -pin  "ACC1:acc#66" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(9)} -pin  "ACC1:acc#66" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(10)} -pin  "ACC1:acc#66" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(11)} -pin  "ACC1:acc#66" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(12)} -pin  "ACC1:acc#66" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(13)} -pin  "ACC1:acc#66" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(14)} -pin  "ACC1:acc#66" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(15)} -pin  "ACC1:acc#66" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {ACC1:acc#66.itm(0)} -pin  "ACC1:acc#66" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(1)} -pin  "ACC1:acc#66" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(2)} -pin  "ACC1:acc#66" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(3)} -pin  "ACC1:acc#66" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(4)} -pin  "ACC1:acc#66" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(5)} -pin  "ACC1:acc#66" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(6)} -pin  "ACC1:acc#66" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(7)} -pin  "ACC1:acc#66" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(8)} -pin  "ACC1:acc#66" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(9)} -pin  "ACC1:acc#66" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(10)} -pin  "ACC1:acc#66" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(11)} -pin  "ACC1:acc#66" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(12)} -pin  "ACC1:acc#66" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(13)} -pin  "ACC1:acc#66" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(14)} -pin  "ACC1:acc#66" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load inst "ACC1:acc#65" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 8767 -attr oid 488 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#65} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {PWR} -pin  "ACC1:acc#65" {A(0)} -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {g(2).sva#3(0)} -pin  "ACC1:acc#65" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {PWR} -pin  "ACC1:acc#65" {B(0)} -attr @path {/sobel/sobel:core/Cn1_1#3}
+load net {ACC1:acc#65.itm(0)} -pin  "ACC1:acc#65" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#65.itm}
+load net {ACC1:acc#65.itm(1)} -pin  "ACC1:acc#65" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#65.itm}
+load inst "ACC1:acc#44" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 8768 -attr oid 489 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {ACC1:acc#65.itm(1)} -pin  "ACC1:acc#44" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(0)} -pin  "ACC1:acc#44" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(1)} -pin  "ACC1:acc#44" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(2)} -pin  "ACC1:acc#44" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(3)} -pin  "ACC1:acc#44" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(4)} -pin  "ACC1:acc#44" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(5)} -pin  "ACC1:acc#44" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(6)} -pin  "ACC1:acc#44" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(7)} -pin  "ACC1:acc#44" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(8)} -pin  "ACC1:acc#44" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(9)} -pin  "ACC1:acc#44" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(10)} -pin  "ACC1:acc#44" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(11)} -pin  "ACC1:acc#44" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(12)} -pin  "ACC1:acc#44" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(13)} -pin  "ACC1:acc#44" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#66.itm(14)} -pin  "ACC1:acc#44" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {g(0).sva#3(0)} -pin  "ACC1:acc#44" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(1)} -pin  "ACC1:acc#44" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(2)} -pin  "ACC1:acc#44" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(3)} -pin  "ACC1:acc#44" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(4)} -pin  "ACC1:acc#44" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(5)} -pin  "ACC1:acc#44" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(6)} -pin  "ACC1:acc#44" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(7)} -pin  "ACC1:acc#44" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(8)} -pin  "ACC1:acc#44" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(9)} -pin  "ACC1:acc#44" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(10)} -pin  "ACC1:acc#44" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(11)} -pin  "ACC1:acc#44" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(12)} -pin  "ACC1:acc#44" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(13)} -pin  "ACC1:acc#44" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(14)} -pin  "ACC1:acc#44" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(15)} -pin  "ACC1:acc#44" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {ACC1:acc#44.itm(0)} -pin  "ACC1:acc#44" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(1)} -pin  "ACC1:acc#44" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(2)} -pin  "ACC1:acc#44" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(3)} -pin  "ACC1:acc#44" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(4)} -pin  "ACC1:acc#44" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(5)} -pin  "ACC1:acc#44" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(6)} -pin  "ACC1:acc#44" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(7)} -pin  "ACC1:acc#44" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(8)} -pin  "ACC1:acc#44" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(9)} -pin  "ACC1:acc#44" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(10)} -pin  "ACC1:acc#44" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(11)} -pin  "ACC1:acc#44" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(12)} -pin  "ACC1:acc#44" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(13)} -pin  "ACC1:acc#44" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(14)} -pin  "ACC1:acc#44" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load net {ACC1:acc#44.itm(15)} -pin  "ACC1:acc#44" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#44.itm}
+load inst "FRAME:not#10" "not(3)" "INTERFACE" -attr xrf 8769 -attr oid 490 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#44.itm(10)} -pin  "FRAME:not#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {ACC1:acc#44.itm(11)} -pin  "FRAME:not#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {ACC1:acc#44.itm(12)} -pin  "FRAME:not#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {FRAME:not#10.itm(0)} -pin  "FRAME:not#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(1)} -pin  "FRAME:not#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(2)} -pin  "FRAME:not#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load inst "FRAME:acc#13" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 8770 -attr oid 491 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#44.itm(7)} -pin  "FRAME:acc#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {ACC1:acc#44.itm(8)} -pin  "FRAME:acc#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {ACC1:acc#44.itm(9)} -pin  "FRAME:acc#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {FRAME:not#10.itm(0)} -pin  "FRAME:acc#13" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(1)} -pin  "FRAME:acc#13" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(2)} -pin  "FRAME:acc#13" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load inst "FRAME:not#37" "not(1)" "INTERFACE" -attr xrf 8771 -attr oid 492 -attr @path {/sobel/sobel:core/FRAME:not#37} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#44.itm(15)} -pin  "FRAME:not#37" {A(0)} -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#12.itm}
+load net {FRAME:not#37.itm} -pin  "FRAME:not#37" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#37.itm}
+load inst "FRAME:not#49" "not(1)" "INTERFACE" -attr xrf 8772 -attr oid 493 -attr @path {/sobel/sobel:core/FRAME:not#49} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#44.itm(15)} -pin  "FRAME:not#49" {A(0)} -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#7.itm}
+load net {FRAME:not#49.itm} -pin  "FRAME:not#49" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#49.itm}
+load inst "FRAME:acc#12" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 8773 -attr oid 494 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#49.itm} -pin  "FRAME:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#151.itm}
+load net {PWR} -pin  "FRAME:acc#12" {A(1)} -attr @path {/sobel/sobel:core/conc#151.itm}
+load net {FRAME:not#37.itm} -pin  "FRAME:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#151.itm}
+load net {ACC1:acc#44.itm(13)} -pin  "FRAME:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#4.itm}
+load net {ACC1:acc#44.itm(14)} -pin  "FRAME:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#4.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load inst "FRAME:acc#15" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 8774 -attr oid 495 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#15" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#15" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#15" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#15" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#15" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load inst "FRAME:not#9" "not(3)" "INTERFACE" -attr xrf 8775 -attr oid 496 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc#44.itm(4)} -pin  "FRAME:not#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {ACC1:acc#44.itm(5)} -pin  "FRAME:not#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {ACC1:acc#44.itm(6)} -pin  "FRAME:not#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {FRAME:not#9.itm(0)} -pin  "FRAME:not#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(1)} -pin  "FRAME:not#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(2)} -pin  "FRAME:not#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load inst "FRAME:acc#14" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 8776 -attr oid 497 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#44.itm(1)} -pin  "FRAME:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {ACC1:acc#44.itm(2)} -pin  "FRAME:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {ACC1:acc#44.itm(3)} -pin  "FRAME:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {FRAME:not#9.itm(0)} -pin  "FRAME:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(1)} -pin  "FRAME:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(2)} -pin  "FRAME:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load inst "FRAME:acc#16" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 8777 -attr oid 498 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16} -attr area 6.288444 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6)"
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#16" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#16" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#16" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#16" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#16" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#16" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#16.itm(0)} -pin  "FRAME:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "FRAME:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "FRAME:acc#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "FRAME:acc#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:acc#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(5)} -pin  "FRAME:acc#16" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load inst "acc#2" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 8778 -attr oid 499 -attr vt d -attr @path {/sobel/sobel:core/acc#2} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {FRAME:acc#16.itm(0)} -pin  "acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(5)} -pin  "acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {PWR} -pin  "acc#2" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#2" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#2" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#2" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#2" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#2" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#2.sva(0)} -pin  "acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#2.sva}
+load net {acc.imod#2.sva(1)} -pin  "acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#2.sva}
+load net {acc.imod#2.sva(2)} -pin  "acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#2.sva}
+load net {acc.imod#2.sva(3)} -pin  "acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#2.sva}
+load net {acc.imod#2.sva(4)} -pin  "acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#2.sva}
+load net {acc.imod#2.sva(5)} -pin  "acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#2.sva}
+load inst "ACC1:not#14" "not(10)" "INTERFACE" -attr xrf 8779 -attr oid 500 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "ACC1:not#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "ACC1:not#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "ACC1:not#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "ACC1:not#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "ACC1:not#14" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "ACC1:not#14" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "ACC1:not#14" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "ACC1:not#14" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "ACC1:not#14" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:not#14" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {ACC1:not#14.itm(0)} -pin  "ACC1:not#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(1)} -pin  "ACC1:not#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(2)} -pin  "ACC1:not#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(3)} -pin  "ACC1:not#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(4)} -pin  "ACC1:not#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(5)} -pin  "ACC1:not#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(6)} -pin  "ACC1:not#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(7)} -pin  "ACC1:not#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(8)} -pin  "ACC1:not#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(9)} -pin  "ACC1:not#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load inst "ACC1:acc#52" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 8780 -attr oid 501 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#52" {A(0)} -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(0)} -pin  "ACC1:acc#52" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(1)} -pin  "ACC1:acc#52" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(2)} -pin  "ACC1:acc#52" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(3)} -pin  "ACC1:acc#52" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(4)} -pin  "ACC1:acc#52" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(5)} -pin  "ACC1:acc#52" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(6)} -pin  "ACC1:acc#52" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(7)} -pin  "ACC1:acc#52" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(8)} -pin  "ACC1:acc#52" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {ACC1:not#14.itm(9)} -pin  "ACC1:acc#52" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {PWR} -pin  "ACC1:acc#52" {B(0)} -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(60)} -pin  "ACC1:acc#52" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(61)} -pin  "ACC1:acc#52" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(62)} -pin  "ACC1:acc#52" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(63)} -pin  "ACC1:acc#52" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(64)} -pin  "ACC1:acc#52" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(65)} -pin  "ACC1:acc#52" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(66)} -pin  "ACC1:acc#52" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(67)} -pin  "ACC1:acc#52" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(68)} -pin  "ACC1:acc#52" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {regs.regs(1).sva(69)} -pin  "ACC1:acc#52" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {ACC1:acc#52.itm(0)} -pin  "ACC1:acc#52" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(1)} -pin  "ACC1:acc#52" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(2)} -pin  "ACC1:acc#52" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(3)} -pin  "ACC1:acc#52" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(4)} -pin  "ACC1:acc#52" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(5)} -pin  "ACC1:acc#52" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(6)} -pin  "ACC1:acc#52" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(7)} -pin  "ACC1:acc#52" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(8)} -pin  "ACC1:acc#52" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(9)} -pin  "ACC1:acc#52" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(10)} -pin  "ACC1:acc#52" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "ACC1:acc#52" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#52.itm}
+load inst "FRAME:for:mux#10" "mux(2,16)" "INTERFACE" -attr xrf 8781 -attr oid 502 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#52.itm(1)} -pin  "FRAME:for:mux#10" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(2)} -pin  "FRAME:for:mux#10" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(3)} -pin  "FRAME:for:mux#10" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(4)} -pin  "FRAME:for:mux#10" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(5)} -pin  "FRAME:for:mux#10" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(6)} -pin  "FRAME:for:mux#10" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(7)} -pin  "FRAME:for:mux#10" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(8)} -pin  "FRAME:for:mux#10" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(9)} -pin  "FRAME:for:mux#10" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(10)} -pin  "FRAME:for:mux#10" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "FRAME:for:mux#10" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "FRAME:for:mux#10" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "FRAME:for:mux#10" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "FRAME:for:mux#10" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "FRAME:for:mux#10" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#52.itm(11)} -pin  "FRAME:for:mux#10" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {b(2).sva#1(0)} -pin  "FRAME:for:mux#10" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(1)} -pin  "FRAME:for:mux#10" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(2)} -pin  "FRAME:for:mux#10" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(3)} -pin  "FRAME:for:mux#10" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(4)} -pin  "FRAME:for:mux#10" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(5)} -pin  "FRAME:for:mux#10" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(6)} -pin  "FRAME:for:mux#10" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(7)} -pin  "FRAME:for:mux#10" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(8)} -pin  "FRAME:for:mux#10" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(9)} -pin  "FRAME:for:mux#10" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(10)} -pin  "FRAME:for:mux#10" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(11)} -pin  "FRAME:for:mux#10" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(12)} -pin  "FRAME:for:mux#10" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(13)} -pin  "FRAME:for:mux#10" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(14)} -pin  "FRAME:for:mux#10" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(15)} -pin  "FRAME:for:mux#10" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#10" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#10.itm(0)} -pin  "FRAME:for:mux#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(1)} -pin  "FRAME:for:mux#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(2)} -pin  "FRAME:for:mux#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(3)} -pin  "FRAME:for:mux#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(4)} -pin  "FRAME:for:mux#10" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(5)} -pin  "FRAME:for:mux#10" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(6)} -pin  "FRAME:for:mux#10" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(7)} -pin  "FRAME:for:mux#10" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(8)} -pin  "FRAME:for:mux#10" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(9)} -pin  "FRAME:for:mux#10" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(10)} -pin  "FRAME:for:mux#10" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(11)} -pin  "FRAME:for:mux#10" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(12)} -pin  "FRAME:for:mux#10" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(13)} -pin  "FRAME:for:mux#10" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(14)} -pin  "FRAME:for:mux#10" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(15)} -pin  "FRAME:for:mux#10" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load inst "regs.operator[]#17:mux" "mux(4,10)" "INTERFACE" -attr xrf 8782 -attr oid 503 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "regs.operator[]#17:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "regs.operator[]#17:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "regs.operator[]#17:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "regs.operator[]#17:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "regs.operator[]#17:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "regs.operator[]#17:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "regs.operator[]#17:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "regs.operator[]#17:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "regs.operator[]#17:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "regs.operator[]#17:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "regs.operator[]#17:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "regs.operator[]#17:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "regs.operator[]#17:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "regs.operator[]#17:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "regs.operator[]#17:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "regs.operator[]#17:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "regs.operator[]#17:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "regs.operator[]#17:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "regs.operator[]#17:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "regs.operator[]#17:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "regs.operator[]#17:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "regs.operator[]#17:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "regs.operator[]#17:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "regs.operator[]#17:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "regs.operator[]#17:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "regs.operator[]#17:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "regs.operator[]#17:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "regs.operator[]#17:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "regs.operator[]#17:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "regs.operator[]#17:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#17:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#17:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#17:mux.itm(0)} -pin  "regs.operator[]#17:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(1)} -pin  "regs.operator[]#17:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(2)} -pin  "regs.operator[]#17:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(3)} -pin  "regs.operator[]#17:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(4)} -pin  "regs.operator[]#17:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(5)} -pin  "regs.operator[]#17:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(6)} -pin  "regs.operator[]#17:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(7)} -pin  "regs.operator[]#17:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(8)} -pin  "regs.operator[]#17:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(9)} -pin  "regs.operator[]#17:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load inst "FRAME:for:mul#8" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 8783 -attr oid 504 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#17:mux.itm(0)} -pin  "FRAME:for:mul#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(1)} -pin  "FRAME:for:mul#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(2)} -pin  "FRAME:for:mul#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(3)} -pin  "FRAME:for:mul#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(4)} -pin  "FRAME:for:mul#8" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(5)} -pin  "FRAME:for:mul#8" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(6)} -pin  "FRAME:for:mul#8" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(7)} -pin  "FRAME:for:mul#8" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(8)} -pin  "FRAME:for:mul#8" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(9)} -pin  "FRAME:for:mul#8" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:mul#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:mul#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:mul#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:mul#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:mul#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:mul#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:mul#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:mul#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:mul#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:mul#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:mul#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load inst "FRAME:for:acc#14" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 8784 -attr oid 505 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#10.itm(0)} -pin  "FRAME:for:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(1)} -pin  "FRAME:for:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(2)} -pin  "FRAME:for:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(3)} -pin  "FRAME:for:acc#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(4)} -pin  "FRAME:for:acc#14" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(5)} -pin  "FRAME:for:acc#14" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(6)} -pin  "FRAME:for:acc#14" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(7)} -pin  "FRAME:for:acc#14" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(8)} -pin  "FRAME:for:acc#14" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(9)} -pin  "FRAME:for:acc#14" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(10)} -pin  "FRAME:for:acc#14" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(11)} -pin  "FRAME:for:acc#14" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(12)} -pin  "FRAME:for:acc#14" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(13)} -pin  "FRAME:for:acc#14" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(14)} -pin  "FRAME:for:acc#14" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(15)} -pin  "FRAME:for:acc#14" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:acc#14" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:acc#14" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:acc#14" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:acc#14" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:acc#14" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:acc#14" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:acc#14" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:acc#14" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {b(2).sva#3(0)} -pin  "FRAME:for:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(1)} -pin  "FRAME:for:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(2)} -pin  "FRAME:for:acc#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(3)} -pin  "FRAME:for:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(4)} -pin  "FRAME:for:acc#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(5)} -pin  "FRAME:for:acc#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(6)} -pin  "FRAME:for:acc#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(7)} -pin  "FRAME:for:acc#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(8)} -pin  "FRAME:for:acc#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(9)} -pin  "FRAME:for:acc#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(10)} -pin  "FRAME:for:acc#14" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(11)} -pin  "FRAME:for:acc#14" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(12)} -pin  "FRAME:for:acc#14" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(13)} -pin  "FRAME:for:acc#14" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(14)} -pin  "FRAME:for:acc#14" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(15)} -pin  "FRAME:for:acc#14" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load inst "ACC1:not#16" "not(10)" "INTERFACE" -attr xrf 8785 -attr oid 506 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "ACC1:not#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "ACC1:not#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "ACC1:not#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "ACC1:not#16" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "ACC1:not#16" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "ACC1:not#16" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "ACC1:not#16" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "ACC1:not#16" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "ACC1:not#16" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:not#16" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:not#16.itm(0)} -pin  "ACC1:not#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(1)} -pin  "ACC1:not#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(2)} -pin  "ACC1:not#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(3)} -pin  "ACC1:not#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(4)} -pin  "ACC1:not#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(5)} -pin  "ACC1:not#16" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(6)} -pin  "ACC1:not#16" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(7)} -pin  "ACC1:not#16" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(8)} -pin  "ACC1:not#16" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(9)} -pin  "ACC1:not#16" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load inst "ACC1:acc#49" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 8786 -attr oid 507 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#49" {A(0)} -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(0)} -pin  "ACC1:acc#49" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(1)} -pin  "ACC1:acc#49" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(2)} -pin  "ACC1:acc#49" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(3)} -pin  "ACC1:acc#49" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(4)} -pin  "ACC1:acc#49" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(5)} -pin  "ACC1:acc#49" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(6)} -pin  "ACC1:acc#49" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(7)} -pin  "ACC1:acc#49" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(8)} -pin  "ACC1:acc#49" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC1:not#16.itm(9)} -pin  "ACC1:acc#49" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {PWR} -pin  "ACC1:acc#49" {B(0)} -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(0)} -pin  "ACC1:acc#49" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(1)} -pin  "ACC1:acc#49" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(2)} -pin  "ACC1:acc#49" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(3)} -pin  "ACC1:acc#49" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(4)} -pin  "ACC1:acc#49" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(5)} -pin  "ACC1:acc#49" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(6)} -pin  "ACC1:acc#49" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(7)} -pin  "ACC1:acc#49" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(8)} -pin  "ACC1:acc#49" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {regs.regs(1).sva(9)} -pin  "ACC1:acc#49" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC1:acc#49.itm(0)} -pin  "ACC1:acc#49" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(1)} -pin  "ACC1:acc#49" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(2)} -pin  "ACC1:acc#49" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(3)} -pin  "ACC1:acc#49" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(4)} -pin  "ACC1:acc#49" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(5)} -pin  "ACC1:acc#49" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(6)} -pin  "ACC1:acc#49" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(7)} -pin  "ACC1:acc#49" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(8)} -pin  "ACC1:acc#49" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(9)} -pin  "ACC1:acc#49" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(10)} -pin  "ACC1:acc#49" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "ACC1:acc#49" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load inst "FRAME:for:mux#9" "mux(2,16)" "INTERFACE" -attr xrf 8787 -attr oid 508 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#49.itm(1)} -pin  "FRAME:for:mux#9" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(2)} -pin  "FRAME:for:mux#9" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(3)} -pin  "FRAME:for:mux#9" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(4)} -pin  "FRAME:for:mux#9" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(5)} -pin  "FRAME:for:mux#9" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(6)} -pin  "FRAME:for:mux#9" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(7)} -pin  "FRAME:for:mux#9" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(8)} -pin  "FRAME:for:mux#9" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(9)} -pin  "FRAME:for:mux#9" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(10)} -pin  "FRAME:for:mux#9" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#9" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#9" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#9" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#9" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#9" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#9" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {b(0).sva#1(0)} -pin  "FRAME:for:mux#9" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(1)} -pin  "FRAME:for:mux#9" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(2)} -pin  "FRAME:for:mux#9" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(3)} -pin  "FRAME:for:mux#9" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(4)} -pin  "FRAME:for:mux#9" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(5)} -pin  "FRAME:for:mux#9" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(6)} -pin  "FRAME:for:mux#9" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(7)} -pin  "FRAME:for:mux#9" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(8)} -pin  "FRAME:for:mux#9" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(9)} -pin  "FRAME:for:mux#9" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(10)} -pin  "FRAME:for:mux#9" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(11)} -pin  "FRAME:for:mux#9" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(12)} -pin  "FRAME:for:mux#9" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(13)} -pin  "FRAME:for:mux#9" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(14)} -pin  "FRAME:for:mux#9" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(15)} -pin  "FRAME:for:mux#9" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#9" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#9.itm(0)} -pin  "FRAME:for:mux#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(1)} -pin  "FRAME:for:mux#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(2)} -pin  "FRAME:for:mux#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(3)} -pin  "FRAME:for:mux#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(4)} -pin  "FRAME:for:mux#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(5)} -pin  "FRAME:for:mux#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(6)} -pin  "FRAME:for:mux#9" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(7)} -pin  "FRAME:for:mux#9" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(8)} -pin  "FRAME:for:mux#9" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(9)} -pin  "FRAME:for:mux#9" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(10)} -pin  "FRAME:for:mux#9" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(11)} -pin  "FRAME:for:mux#9" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(12)} -pin  "FRAME:for:mux#9" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(13)} -pin  "FRAME:for:mux#9" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(14)} -pin  "FRAME:for:mux#9" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(15)} -pin  "FRAME:for:mux#9" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load inst "regs.operator[]#11:mux" "mux(4,10)" "INTERFACE" -attr xrf 8788 -attr oid 509 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "regs.operator[]#11:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "regs.operator[]#11:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "regs.operator[]#11:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "regs.operator[]#11:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "regs.operator[]#11:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "regs.operator[]#11:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "regs.operator[]#11:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "regs.operator[]#11:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "regs.operator[]#11:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "regs.operator[]#11:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "regs.operator[]#11:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "regs.operator[]#11:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "regs.operator[]#11:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "regs.operator[]#11:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "regs.operator[]#11:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "regs.operator[]#11:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "regs.operator[]#11:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "regs.operator[]#11:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "regs.operator[]#11:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "regs.operator[]#11:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "regs.operator[]#11:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "regs.operator[]#11:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "regs.operator[]#11:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "regs.operator[]#11:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "regs.operator[]#11:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "regs.operator[]#11:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "regs.operator[]#11:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "regs.operator[]#11:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "regs.operator[]#11:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "regs.operator[]#11:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#11:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#11:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#11:mux.itm(0)} -pin  "regs.operator[]#11:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(1)} -pin  "regs.operator[]#11:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(2)} -pin  "regs.operator[]#11:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(3)} -pin  "regs.operator[]#11:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(4)} -pin  "regs.operator[]#11:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(5)} -pin  "regs.operator[]#11:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(6)} -pin  "regs.operator[]#11:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(7)} -pin  "regs.operator[]#11:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(8)} -pin  "regs.operator[]#11:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(9)} -pin  "regs.operator[]#11:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load inst "FRAME:for:mul#2" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 8789 -attr oid 510 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#11:mux.itm(0)} -pin  "FRAME:for:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(1)} -pin  "FRAME:for:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(2)} -pin  "FRAME:for:mul#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(3)} -pin  "FRAME:for:mul#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(4)} -pin  "FRAME:for:mul#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(5)} -pin  "FRAME:for:mul#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(6)} -pin  "FRAME:for:mul#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(7)} -pin  "FRAME:for:mul#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(8)} -pin  "FRAME:for:mul#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(9)} -pin  "FRAME:for:mul#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {PWR} -pin  "FRAME:for:mul#2" {B(1)} -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(11)} -pin  "FRAME:for:mul#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load inst "FRAME:for:acc#3" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 8790 -attr oid 511 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#9.itm(0)} -pin  "FRAME:for:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(1)} -pin  "FRAME:for:acc#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(2)} -pin  "FRAME:for:acc#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(3)} -pin  "FRAME:for:acc#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(4)} -pin  "FRAME:for:acc#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(5)} -pin  "FRAME:for:acc#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(6)} -pin  "FRAME:for:acc#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(7)} -pin  "FRAME:for:acc#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(8)} -pin  "FRAME:for:acc#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(9)} -pin  "FRAME:for:acc#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(10)} -pin  "FRAME:for:acc#3" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(11)} -pin  "FRAME:for:acc#3" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(12)} -pin  "FRAME:for:acc#3" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(13)} -pin  "FRAME:for:acc#3" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(14)} -pin  "FRAME:for:acc#3" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(15)} -pin  "FRAME:for:acc#3" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:acc#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:acc#3" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:acc#3" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:acc#3" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:acc#3" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:acc#3" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:acc#3" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:acc#3" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:acc#3" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:acc#3" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(11)} -pin  "FRAME:for:acc#3" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {b(0).sva#3(0)} -pin  "FRAME:for:acc#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(1)} -pin  "FRAME:for:acc#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(2)} -pin  "FRAME:for:acc#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(3)} -pin  "FRAME:for:acc#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(4)} -pin  "FRAME:for:acc#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(5)} -pin  "FRAME:for:acc#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(6)} -pin  "FRAME:for:acc#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(7)} -pin  "FRAME:for:acc#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(8)} -pin  "FRAME:for:acc#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(9)} -pin  "FRAME:for:acc#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(10)} -pin  "FRAME:for:acc#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(11)} -pin  "FRAME:for:acc#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(12)} -pin  "FRAME:for:acc#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(13)} -pin  "FRAME:for:acc#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(14)} -pin  "FRAME:for:acc#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(15)} -pin  "FRAME:for:acc#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load inst "ACC1:not#13" "not(10)" "INTERFACE" -attr xrf 8791 -attr oid 512 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "ACC1:not#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "ACC1:not#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "ACC1:not#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "ACC1:not#13" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "ACC1:not#13" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "ACC1:not#13" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "ACC1:not#13" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "ACC1:not#13" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "ACC1:not#13" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:not#13" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {ACC1:not#13.itm(0)} -pin  "ACC1:not#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(1)} -pin  "ACC1:not#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(2)} -pin  "ACC1:not#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(3)} -pin  "ACC1:not#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(4)} -pin  "ACC1:not#13" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(5)} -pin  "ACC1:not#13" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(6)} -pin  "ACC1:not#13" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(7)} -pin  "ACC1:not#13" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(8)} -pin  "ACC1:not#13" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(9)} -pin  "ACC1:not#13" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load inst "ACC1:acc#51" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 8792 -attr oid 513 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#51" {A(0)} -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(0)} -pin  "ACC1:acc#51" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(1)} -pin  "ACC1:acc#51" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(2)} -pin  "ACC1:acc#51" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(3)} -pin  "ACC1:acc#51" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(4)} -pin  "ACC1:acc#51" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(5)} -pin  "ACC1:acc#51" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(6)} -pin  "ACC1:acc#51" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(7)} -pin  "ACC1:acc#51" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(8)} -pin  "ACC1:acc#51" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {ACC1:not#13.itm(9)} -pin  "ACC1:acc#51" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {PWR} -pin  "ACC1:acc#51" {B(0)} -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(70)} -pin  "ACC1:acc#51" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(71)} -pin  "ACC1:acc#51" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(72)} -pin  "ACC1:acc#51" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(73)} -pin  "ACC1:acc#51" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(74)} -pin  "ACC1:acc#51" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(75)} -pin  "ACC1:acc#51" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(76)} -pin  "ACC1:acc#51" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(77)} -pin  "ACC1:acc#51" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(78)} -pin  "ACC1:acc#51" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {regs.regs(1).sva(79)} -pin  "ACC1:acc#51" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {ACC1:acc#51.itm(0)} -pin  "ACC1:acc#51" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(1)} -pin  "ACC1:acc#51" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(2)} -pin  "ACC1:acc#51" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(3)} -pin  "ACC1:acc#51" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(4)} -pin  "ACC1:acc#51" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(5)} -pin  "ACC1:acc#51" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(6)} -pin  "ACC1:acc#51" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(7)} -pin  "ACC1:acc#51" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(8)} -pin  "ACC1:acc#51" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(9)} -pin  "ACC1:acc#51" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(10)} -pin  "ACC1:acc#51" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "ACC1:acc#51" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#51.itm}
+load inst "FRAME:for:mux#8" "mux(2,16)" "INTERFACE" -attr xrf 8793 -attr oid 514 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#51.itm(1)} -pin  "FRAME:for:mux#8" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(2)} -pin  "FRAME:for:mux#8" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(3)} -pin  "FRAME:for:mux#8" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(4)} -pin  "FRAME:for:mux#8" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(5)} -pin  "FRAME:for:mux#8" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(6)} -pin  "FRAME:for:mux#8" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(7)} -pin  "FRAME:for:mux#8" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(8)} -pin  "FRAME:for:mux#8" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(9)} -pin  "FRAME:for:mux#8" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(10)} -pin  "FRAME:for:mux#8" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "FRAME:for:mux#8" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "FRAME:for:mux#8" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "FRAME:for:mux#8" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "FRAME:for:mux#8" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "FRAME:for:mux#8" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#51.itm(11)} -pin  "FRAME:for:mux#8" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {g(2).sva#1(0)} -pin  "FRAME:for:mux#8" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(1)} -pin  "FRAME:for:mux#8" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(2)} -pin  "FRAME:for:mux#8" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(3)} -pin  "FRAME:for:mux#8" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(4)} -pin  "FRAME:for:mux#8" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(5)} -pin  "FRAME:for:mux#8" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(6)} -pin  "FRAME:for:mux#8" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(7)} -pin  "FRAME:for:mux#8" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(8)} -pin  "FRAME:for:mux#8" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(9)} -pin  "FRAME:for:mux#8" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(10)} -pin  "FRAME:for:mux#8" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(11)} -pin  "FRAME:for:mux#8" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(12)} -pin  "FRAME:for:mux#8" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(13)} -pin  "FRAME:for:mux#8" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(14)} -pin  "FRAME:for:mux#8" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(15)} -pin  "FRAME:for:mux#8" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#8" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#8.itm(0)} -pin  "FRAME:for:mux#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(1)} -pin  "FRAME:for:mux#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(2)} -pin  "FRAME:for:mux#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(3)} -pin  "FRAME:for:mux#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(4)} -pin  "FRAME:for:mux#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(5)} -pin  "FRAME:for:mux#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(6)} -pin  "FRAME:for:mux#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(7)} -pin  "FRAME:for:mux#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(8)} -pin  "FRAME:for:mux#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(9)} -pin  "FRAME:for:mux#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(10)} -pin  "FRAME:for:mux#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(11)} -pin  "FRAME:for:mux#8" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(12)} -pin  "FRAME:for:mux#8" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(13)} -pin  "FRAME:for:mux#8" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(14)} -pin  "FRAME:for:mux#8" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(15)} -pin  "FRAME:for:mux#8" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load inst "regs.operator[]#16:mux" "mux(4,10)" "INTERFACE" -attr xrf 8794 -attr oid 515 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "regs.operator[]#16:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "regs.operator[]#16:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "regs.operator[]#16:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "regs.operator[]#16:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "regs.operator[]#16:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "regs.operator[]#16:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "regs.operator[]#16:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "regs.operator[]#16:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "regs.operator[]#16:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "regs.operator[]#16:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "regs.operator[]#16:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "regs.operator[]#16:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "regs.operator[]#16:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "regs.operator[]#16:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "regs.operator[]#16:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "regs.operator[]#16:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "regs.operator[]#16:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "regs.operator[]#16:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "regs.operator[]#16:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "regs.operator[]#16:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "regs.operator[]#16:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "regs.operator[]#16:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "regs.operator[]#16:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "regs.operator[]#16:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "regs.operator[]#16:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "regs.operator[]#16:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "regs.operator[]#16:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "regs.operator[]#16:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "regs.operator[]#16:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "regs.operator[]#16:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#16:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#16:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#16:mux.itm(0)} -pin  "regs.operator[]#16:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(1)} -pin  "regs.operator[]#16:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(2)} -pin  "regs.operator[]#16:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(3)} -pin  "regs.operator[]#16:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(4)} -pin  "regs.operator[]#16:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(5)} -pin  "regs.operator[]#16:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(6)} -pin  "regs.operator[]#16:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(7)} -pin  "regs.operator[]#16:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(8)} -pin  "regs.operator[]#16:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(9)} -pin  "regs.operator[]#16:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load inst "FRAME:for:mul#7" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 8795 -attr oid 516 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#16:mux.itm(0)} -pin  "FRAME:for:mul#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(1)} -pin  "FRAME:for:mul#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(2)} -pin  "FRAME:for:mul#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(3)} -pin  "FRAME:for:mul#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(4)} -pin  "FRAME:for:mul#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(5)} -pin  "FRAME:for:mul#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(6)} -pin  "FRAME:for:mul#7" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(7)} -pin  "FRAME:for:mul#7" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(8)} -pin  "FRAME:for:mul#7" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(9)} -pin  "FRAME:for:mul#7" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:mul#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:mul#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:mul#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:mul#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:mul#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:mul#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:mul#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:mul#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:mul#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:mul#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:mul#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load inst "FRAME:for:acc#12" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 8796 -attr oid 517 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#8.itm(0)} -pin  "FRAME:for:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(1)} -pin  "FRAME:for:acc#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(2)} -pin  "FRAME:for:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(3)} -pin  "FRAME:for:acc#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(4)} -pin  "FRAME:for:acc#12" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(5)} -pin  "FRAME:for:acc#12" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(6)} -pin  "FRAME:for:acc#12" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(7)} -pin  "FRAME:for:acc#12" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(8)} -pin  "FRAME:for:acc#12" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(9)} -pin  "FRAME:for:acc#12" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(10)} -pin  "FRAME:for:acc#12" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(11)} -pin  "FRAME:for:acc#12" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(12)} -pin  "FRAME:for:acc#12" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(13)} -pin  "FRAME:for:acc#12" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(14)} -pin  "FRAME:for:acc#12" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(15)} -pin  "FRAME:for:acc#12" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:acc#12" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:acc#12" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:acc#12" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:acc#12" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:acc#12" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:acc#12" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:acc#12" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:acc#12" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:acc#12" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {g(2).sva#3(0)} -pin  "FRAME:for:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(1)} -pin  "FRAME:for:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(2)} -pin  "FRAME:for:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(3)} -pin  "FRAME:for:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(4)} -pin  "FRAME:for:acc#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(5)} -pin  "FRAME:for:acc#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(6)} -pin  "FRAME:for:acc#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(7)} -pin  "FRAME:for:acc#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(8)} -pin  "FRAME:for:acc#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(9)} -pin  "FRAME:for:acc#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(10)} -pin  "FRAME:for:acc#12" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(11)} -pin  "FRAME:for:acc#12" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(12)} -pin  "FRAME:for:acc#12" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(13)} -pin  "FRAME:for:acc#12" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(14)} -pin  "FRAME:for:acc#12" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(15)} -pin  "FRAME:for:acc#12" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load inst "ACC1:not#15" "not(10)" "INTERFACE" -attr xrf 8797 -attr oid 518 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "ACC1:not#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "ACC1:not#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "ACC1:not#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "ACC1:not#15" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "ACC1:not#15" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "ACC1:not#15" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "ACC1:not#15" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "ACC1:not#15" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "ACC1:not#15" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:not#15" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {ACC1:not#15.itm(0)} -pin  "ACC1:not#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(1)} -pin  "ACC1:not#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(2)} -pin  "ACC1:not#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(3)} -pin  "ACC1:not#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(4)} -pin  "ACC1:not#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(5)} -pin  "ACC1:not#15" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(6)} -pin  "ACC1:not#15" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(7)} -pin  "ACC1:not#15" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(8)} -pin  "ACC1:not#15" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(9)} -pin  "ACC1:not#15" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load inst "ACC1:acc" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 8798 -attr oid 519 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc" {A(0)} -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(0)} -pin  "ACC1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(1)} -pin  "ACC1:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(2)} -pin  "ACC1:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(3)} -pin  "ACC1:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(4)} -pin  "ACC1:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(5)} -pin  "ACC1:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(6)} -pin  "ACC1:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(7)} -pin  "ACC1:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(8)} -pin  "ACC1:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {ACC1:not#15.itm(9)} -pin  "ACC1:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#159.itm}
+load net {PWR} -pin  "ACC1:acc" {B(0)} -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(10)} -pin  "ACC1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(11)} -pin  "ACC1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(12)} -pin  "ACC1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(13)} -pin  "ACC1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(14)} -pin  "ACC1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(15)} -pin  "ACC1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(16)} -pin  "ACC1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(17)} -pin  "ACC1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(18)} -pin  "ACC1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {regs.regs(1).sva(19)} -pin  "ACC1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {ACC1:acc.itm(0)} -pin  "ACC1:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(1)} -pin  "ACC1:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(2)} -pin  "ACC1:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(3)} -pin  "ACC1:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(4)} -pin  "ACC1:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(5)} -pin  "ACC1:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(6)} -pin  "ACC1:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(7)} -pin  "ACC1:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(8)} -pin  "ACC1:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(9)} -pin  "ACC1:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(10)} -pin  "ACC1:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(11)} -pin  "ACC1:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load inst "FRAME:for:mux#7" "mux(2,16)" "INTERFACE" -attr xrf 8799 -attr oid 520 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc.itm(1)} -pin  "FRAME:for:mux#7" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(2)} -pin  "FRAME:for:mux#7" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(3)} -pin  "FRAME:for:mux#7" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(4)} -pin  "FRAME:for:mux#7" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:for:mux#7" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(6)} -pin  "FRAME:for:mux#7" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(7)} -pin  "FRAME:for:mux#7" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:for:mux#7" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:for:mux#7" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(10)} -pin  "FRAME:for:mux#7" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {g(0).sva#1(0)} -pin  "FRAME:for:mux#7" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(1)} -pin  "FRAME:for:mux#7" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(2)} -pin  "FRAME:for:mux#7" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(3)} -pin  "FRAME:for:mux#7" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(4)} -pin  "FRAME:for:mux#7" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(5)} -pin  "FRAME:for:mux#7" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(6)} -pin  "FRAME:for:mux#7" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(7)} -pin  "FRAME:for:mux#7" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(8)} -pin  "FRAME:for:mux#7" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(9)} -pin  "FRAME:for:mux#7" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(10)} -pin  "FRAME:for:mux#7" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(11)} -pin  "FRAME:for:mux#7" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(12)} -pin  "FRAME:for:mux#7" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(13)} -pin  "FRAME:for:mux#7" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(14)} -pin  "FRAME:for:mux#7" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(15)} -pin  "FRAME:for:mux#7" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#7" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#7.itm(0)} -pin  "FRAME:for:mux#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(1)} -pin  "FRAME:for:mux#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(2)} -pin  "FRAME:for:mux#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(3)} -pin  "FRAME:for:mux#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(4)} -pin  "FRAME:for:mux#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(5)} -pin  "FRAME:for:mux#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(6)} -pin  "FRAME:for:mux#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(7)} -pin  "FRAME:for:mux#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(8)} -pin  "FRAME:for:mux#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(9)} -pin  "FRAME:for:mux#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(10)} -pin  "FRAME:for:mux#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(11)} -pin  "FRAME:for:mux#7" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(12)} -pin  "FRAME:for:mux#7" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(13)} -pin  "FRAME:for:mux#7" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(14)} -pin  "FRAME:for:mux#7" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(15)} -pin  "FRAME:for:mux#7" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load inst "regs.operator[]#10:mux" "mux(4,10)" "INTERFACE" -attr xrf 8800 -attr oid 521 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "regs.operator[]#10:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "regs.operator[]#10:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "regs.operator[]#10:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "regs.operator[]#10:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "regs.operator[]#10:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "regs.operator[]#10:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "regs.operator[]#10:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "regs.operator[]#10:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "regs.operator[]#10:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "regs.operator[]#10:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "regs.operator[]#10:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "regs.operator[]#10:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "regs.operator[]#10:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "regs.operator[]#10:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "regs.operator[]#10:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "regs.operator[]#10:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "regs.operator[]#10:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "regs.operator[]#10:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "regs.operator[]#10:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "regs.operator[]#10:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "regs.operator[]#10:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "regs.operator[]#10:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "regs.operator[]#10:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "regs.operator[]#10:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "regs.operator[]#10:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "regs.operator[]#10:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "regs.operator[]#10:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "regs.operator[]#10:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "regs.operator[]#10:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "regs.operator[]#10:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#10:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#10:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#10:mux.itm(0)} -pin  "regs.operator[]#10:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(1)} -pin  "regs.operator[]#10:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(2)} -pin  "regs.operator[]#10:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(3)} -pin  "regs.operator[]#10:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(4)} -pin  "regs.operator[]#10:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(5)} -pin  "regs.operator[]#10:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(6)} -pin  "regs.operator[]#10:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(7)} -pin  "regs.operator[]#10:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(8)} -pin  "regs.operator[]#10:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(9)} -pin  "regs.operator[]#10:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load inst "FRAME:for:mul#1" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 8801 -attr oid 522 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#10:mux.itm(0)} -pin  "FRAME:for:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(1)} -pin  "FRAME:for:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(2)} -pin  "FRAME:for:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(3)} -pin  "FRAME:for:mul#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(4)} -pin  "FRAME:for:mul#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(5)} -pin  "FRAME:for:mul#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(6)} -pin  "FRAME:for:mul#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(7)} -pin  "FRAME:for:mul#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(8)} -pin  "FRAME:for:mul#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(9)} -pin  "FRAME:for:mul#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {PWR} -pin  "FRAME:for:mul#1" {B(1)} -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:mul#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:mul#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(11)} -pin  "FRAME:for:mul#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load inst "FRAME:for:acc#2" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 8802 -attr oid 523 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#7.itm(0)} -pin  "FRAME:for:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(1)} -pin  "FRAME:for:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(2)} -pin  "FRAME:for:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(3)} -pin  "FRAME:for:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(4)} -pin  "FRAME:for:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(5)} -pin  "FRAME:for:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(6)} -pin  "FRAME:for:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(7)} -pin  "FRAME:for:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(8)} -pin  "FRAME:for:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(9)} -pin  "FRAME:for:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(10)} -pin  "FRAME:for:acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(11)} -pin  "FRAME:for:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(12)} -pin  "FRAME:for:acc#2" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(13)} -pin  "FRAME:for:acc#2" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(14)} -pin  "FRAME:for:acc#2" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(15)} -pin  "FRAME:for:acc#2" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(11)} -pin  "FRAME:for:acc#2" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {g(0).sva#3(0)} -pin  "FRAME:for:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(1)} -pin  "FRAME:for:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(2)} -pin  "FRAME:for:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(3)} -pin  "FRAME:for:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(4)} -pin  "FRAME:for:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(5)} -pin  "FRAME:for:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(6)} -pin  "FRAME:for:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(7)} -pin  "FRAME:for:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(8)} -pin  "FRAME:for:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(9)} -pin  "FRAME:for:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(10)} -pin  "FRAME:for:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(11)} -pin  "FRAME:for:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(12)} -pin  "FRAME:for:acc#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(13)} -pin  "FRAME:for:acc#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(14)} -pin  "FRAME:for:acc#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(15)} -pin  "FRAME:for:acc#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load inst "ACC1:not#12" "not(10)" "INTERFACE" -attr xrf 8803 -attr oid 524 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "ACC1:not#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "ACC1:not#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "ACC1:not#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "ACC1:not#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "ACC1:not#12" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "ACC1:not#12" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "ACC1:not#12" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "ACC1:not#12" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "ACC1:not#12" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1:not#12" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {ACC1:not#12.itm(0)} -pin  "ACC1:not#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(1)} -pin  "ACC1:not#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(2)} -pin  "ACC1:not#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(3)} -pin  "ACC1:not#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(4)} -pin  "ACC1:not#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(5)} -pin  "ACC1:not#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(6)} -pin  "ACC1:not#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(7)} -pin  "ACC1:not#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(8)} -pin  "ACC1:not#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(9)} -pin  "ACC1:not#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load inst "ACC1:acc#50" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 8804 -attr oid 525 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#50" {A(0)} -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(0)} -pin  "ACC1:acc#50" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(1)} -pin  "ACC1:acc#50" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(2)} -pin  "ACC1:acc#50" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(3)} -pin  "ACC1:acc#50" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(4)} -pin  "ACC1:acc#50" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(5)} -pin  "ACC1:acc#50" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(6)} -pin  "ACC1:acc#50" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(7)} -pin  "ACC1:acc#50" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(8)} -pin  "ACC1:acc#50" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:not#12.itm(9)} -pin  "ACC1:acc#50" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {PWR} -pin  "ACC1:acc#50" {B(0)} -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(80)} -pin  "ACC1:acc#50" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(81)} -pin  "ACC1:acc#50" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(82)} -pin  "ACC1:acc#50" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(83)} -pin  "ACC1:acc#50" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(84)} -pin  "ACC1:acc#50" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(85)} -pin  "ACC1:acc#50" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(86)} -pin  "ACC1:acc#50" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(87)} -pin  "ACC1:acc#50" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(88)} -pin  "ACC1:acc#50" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {regs.regs(1).sva(89)} -pin  "ACC1:acc#50" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {ACC1:acc#50.itm(0)} -pin  "ACC1:acc#50" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(1)} -pin  "ACC1:acc#50" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(2)} -pin  "ACC1:acc#50" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(3)} -pin  "ACC1:acc#50" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(4)} -pin  "ACC1:acc#50" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(5)} -pin  "ACC1:acc#50" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(6)} -pin  "ACC1:acc#50" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(7)} -pin  "ACC1:acc#50" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(8)} -pin  "ACC1:acc#50" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(9)} -pin  "ACC1:acc#50" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(10)} -pin  "ACC1:acc#50" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "ACC1:acc#50" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#50.itm}
+load inst "FRAME:for:mux#6" "mux(2,16)" "INTERFACE" -attr xrf 8805 -attr oid 526 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#50.itm(1)} -pin  "FRAME:for:mux#6" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(2)} -pin  "FRAME:for:mux#6" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(3)} -pin  "FRAME:for:mux#6" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(4)} -pin  "FRAME:for:mux#6" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(5)} -pin  "FRAME:for:mux#6" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(6)} -pin  "FRAME:for:mux#6" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(7)} -pin  "FRAME:for:mux#6" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(8)} -pin  "FRAME:for:mux#6" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(9)} -pin  "FRAME:for:mux#6" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(10)} -pin  "FRAME:for:mux#6" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "FRAME:for:mux#6" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "FRAME:for:mux#6" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "FRAME:for:mux#6" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "FRAME:for:mux#6" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "FRAME:for:mux#6" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#50.itm(11)} -pin  "FRAME:for:mux#6" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {r(2).sva#1(0)} -pin  "FRAME:for:mux#6" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(1)} -pin  "FRAME:for:mux#6" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(2)} -pin  "FRAME:for:mux#6" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(3)} -pin  "FRAME:for:mux#6" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(4)} -pin  "FRAME:for:mux#6" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(5)} -pin  "FRAME:for:mux#6" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(6)} -pin  "FRAME:for:mux#6" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(7)} -pin  "FRAME:for:mux#6" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(8)} -pin  "FRAME:for:mux#6" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(9)} -pin  "FRAME:for:mux#6" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(10)} -pin  "FRAME:for:mux#6" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(11)} -pin  "FRAME:for:mux#6" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(12)} -pin  "FRAME:for:mux#6" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(13)} -pin  "FRAME:for:mux#6" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(14)} -pin  "FRAME:for:mux#6" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(15)} -pin  "FRAME:for:mux#6" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#6" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#6.itm(0)} -pin  "FRAME:for:mux#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(1)} -pin  "FRAME:for:mux#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(2)} -pin  "FRAME:for:mux#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(3)} -pin  "FRAME:for:mux#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(4)} -pin  "FRAME:for:mux#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(5)} -pin  "FRAME:for:mux#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(6)} -pin  "FRAME:for:mux#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(7)} -pin  "FRAME:for:mux#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(8)} -pin  "FRAME:for:mux#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(9)} -pin  "FRAME:for:mux#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(10)} -pin  "FRAME:for:mux#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(11)} -pin  "FRAME:for:mux#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(12)} -pin  "FRAME:for:mux#6" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(13)} -pin  "FRAME:for:mux#6" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(14)} -pin  "FRAME:for:mux#6" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(15)} -pin  "FRAME:for:mux#6" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load inst "regs.operator[]#15:mux" "mux(4,10)" "INTERFACE" -attr xrf 8806 -attr oid 527 -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "regs.operator[]#15:mux" {A1(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "regs.operator[]#15:mux" {A1(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "regs.operator[]#15:mux" {A1(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "regs.operator[]#15:mux" {A1(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "regs.operator[]#15:mux" {A1(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "regs.operator[]#15:mux" {A1(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "regs.operator[]#15:mux" {A1(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "regs.operator[]#15:mux" {A1(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "regs.operator[]#15:mux" {A1(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "regs.operator[]#15:mux" {A1(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "regs.operator[]#15:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "regs.operator[]#15:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "regs.operator[]#15:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "regs.operator[]#15:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "regs.operator[]#15:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "regs.operator[]#15:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "regs.operator[]#15:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "regs.operator[]#15:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "regs.operator[]#15:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "regs.operator[]#15:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "regs.operator[]#15:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "regs.operator[]#15:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "regs.operator[]#15:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "regs.operator[]#15:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "regs.operator[]#15:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "regs.operator[]#15:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "regs.operator[]#15:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "regs.operator[]#15:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "regs.operator[]#15:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "regs.operator[]#15:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#15:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#15:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#15:mux.itm(0)} -pin  "regs.operator[]#15:mux" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(1)} -pin  "regs.operator[]#15:mux" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(2)} -pin  "regs.operator[]#15:mux" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(3)} -pin  "regs.operator[]#15:mux" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(4)} -pin  "regs.operator[]#15:mux" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(5)} -pin  "regs.operator[]#15:mux" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(6)} -pin  "regs.operator[]#15:mux" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(7)} -pin  "regs.operator[]#15:mux" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(8)} -pin  "regs.operator[]#15:mux" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(9)} -pin  "regs.operator[]#15:mux" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load inst "FRAME:for:mul#6" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 8807 -attr oid 528 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#15:mux.itm(0)} -pin  "FRAME:for:mul#6" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(1)} -pin  "FRAME:for:mul#6" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(2)} -pin  "FRAME:for:mul#6" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(3)} -pin  "FRAME:for:mul#6" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(4)} -pin  "FRAME:for:mul#6" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(5)} -pin  "FRAME:for:mul#6" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(6)} -pin  "FRAME:for:mul#6" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(7)} -pin  "FRAME:for:mul#6" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(8)} -pin  "FRAME:for:mul#6" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(9)} -pin  "FRAME:for:mul#6" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:mul#6" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:mul#6" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:mul#6" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:mul#6" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:mul#6" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:mul#6" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:mul#6" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:mul#6" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:mul#6" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:mul#6" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:mul#6" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load inst "FRAME:for:acc#10" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 8808 -attr oid 529 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:acc#10} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#6.itm(0)} -pin  "FRAME:for:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(1)} -pin  "FRAME:for:acc#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(2)} -pin  "FRAME:for:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(3)} -pin  "FRAME:for:acc#10" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(4)} -pin  "FRAME:for:acc#10" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(5)} -pin  "FRAME:for:acc#10" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(6)} -pin  "FRAME:for:acc#10" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(7)} -pin  "FRAME:for:acc#10" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(8)} -pin  "FRAME:for:acc#10" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(9)} -pin  "FRAME:for:acc#10" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(10)} -pin  "FRAME:for:acc#10" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(11)} -pin  "FRAME:for:acc#10" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(12)} -pin  "FRAME:for:acc#10" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(13)} -pin  "FRAME:for:acc#10" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(14)} -pin  "FRAME:for:acc#10" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(15)} -pin  "FRAME:for:acc#10" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:acc#10" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:acc#10" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:acc#10" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:acc#10" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:acc#10" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:acc#10" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:acc#10" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:acc#10" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:acc#10" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:acc#10" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:acc#10" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {r(2).sva#3(0)} -pin  "FRAME:for:acc#10" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(1)} -pin  "FRAME:for:acc#10" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(2)} -pin  "FRAME:for:acc#10" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(3)} -pin  "FRAME:for:acc#10" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(4)} -pin  "FRAME:for:acc#10" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(5)} -pin  "FRAME:for:acc#10" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(6)} -pin  "FRAME:for:acc#10" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(7)} -pin  "FRAME:for:acc#10" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(8)} -pin  "FRAME:for:acc#10" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(9)} -pin  "FRAME:for:acc#10" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(10)} -pin  "FRAME:for:acc#10" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(11)} -pin  "FRAME:for:acc#10" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(12)} -pin  "FRAME:for:acc#10" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(13)} -pin  "FRAME:for:acc#10" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(14)} -pin  "FRAME:for:acc#10" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(15)} -pin  "FRAME:for:acc#10" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load inst "ACC1:not" "not(10)" "INTERFACE" -attr xrf 8809 -attr oid 530 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "ACC1:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "ACC1:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "ACC1:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "ACC1:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "ACC1:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "ACC1:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "ACC1:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "ACC1:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "ACC1:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load inst "ACC1:acc#48" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 8810 -attr oid 531 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#48" {A(0)} -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:acc#48" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:acc#48" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:acc#48" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:acc#48" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:acc#48" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:acc#48" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:acc#48" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:acc#48" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:acc#48" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:acc#48" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {PWR} -pin  "ACC1:acc#48" {B(0)} -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(20)} -pin  "ACC1:acc#48" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(21)} -pin  "ACC1:acc#48" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(22)} -pin  "ACC1:acc#48" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(23)} -pin  "ACC1:acc#48" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(24)} -pin  "ACC1:acc#48" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(25)} -pin  "ACC1:acc#48" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(26)} -pin  "ACC1:acc#48" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(27)} -pin  "ACC1:acc#48" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(28)} -pin  "ACC1:acc#48" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {regs.regs(1).sva(29)} -pin  "ACC1:acc#48" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {ACC1:acc#48.itm(0)} -pin  "ACC1:acc#48" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(1)} -pin  "ACC1:acc#48" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(2)} -pin  "ACC1:acc#48" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(3)} -pin  "ACC1:acc#48" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(4)} -pin  "ACC1:acc#48" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(5)} -pin  "ACC1:acc#48" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(6)} -pin  "ACC1:acc#48" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(7)} -pin  "ACC1:acc#48" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(8)} -pin  "ACC1:acc#48" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(9)} -pin  "ACC1:acc#48" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(10)} -pin  "ACC1:acc#48" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "ACC1:acc#48" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load inst "FRAME:for:mux#5" "mux(2,16)" "INTERFACE" -attr xrf 8811 -attr oid 532 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#48.itm(1)} -pin  "FRAME:for:mux#5" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(2)} -pin  "FRAME:for:mux#5" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(3)} -pin  "FRAME:for:mux#5" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(4)} -pin  "FRAME:for:mux#5" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(5)} -pin  "FRAME:for:mux#5" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(6)} -pin  "FRAME:for:mux#5" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(7)} -pin  "FRAME:for:mux#5" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(8)} -pin  "FRAME:for:mux#5" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(9)} -pin  "FRAME:for:mux#5" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(10)} -pin  "FRAME:for:mux#5" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#5" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#5" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#5" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#5" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#5" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#5" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {r(0).sva#1(0)} -pin  "FRAME:for:mux#5" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(1)} -pin  "FRAME:for:mux#5" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(2)} -pin  "FRAME:for:mux#5" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(3)} -pin  "FRAME:for:mux#5" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(4)} -pin  "FRAME:for:mux#5" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(5)} -pin  "FRAME:for:mux#5" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(6)} -pin  "FRAME:for:mux#5" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(7)} -pin  "FRAME:for:mux#5" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(8)} -pin  "FRAME:for:mux#5" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(9)} -pin  "FRAME:for:mux#5" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(10)} -pin  "FRAME:for:mux#5" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(11)} -pin  "FRAME:for:mux#5" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(12)} -pin  "FRAME:for:mux#5" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(13)} -pin  "FRAME:for:mux#5" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(14)} -pin  "FRAME:for:mux#5" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(15)} -pin  "FRAME:for:mux#5" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#5" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#5.itm(0)} -pin  "FRAME:for:mux#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(1)} -pin  "FRAME:for:mux#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(2)} -pin  "FRAME:for:mux#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(3)} -pin  "FRAME:for:mux#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(4)} -pin  "FRAME:for:mux#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(5)} -pin  "FRAME:for:mux#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(6)} -pin  "FRAME:for:mux#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(7)} -pin  "FRAME:for:mux#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(8)} -pin  "FRAME:for:mux#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(9)} -pin  "FRAME:for:mux#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(10)} -pin  "FRAME:for:mux#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(11)} -pin  "FRAME:for:mux#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(12)} -pin  "FRAME:for:mux#5" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(13)} -pin  "FRAME:for:mux#5" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(14)} -pin  "FRAME:for:mux#5" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(15)} -pin  "FRAME:for:mux#5" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load inst "regs.operator[]#9:mux" "mux(4,10)" "INTERFACE" -attr xrf 8812 -attr oid 533 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "regs.operator[]#9:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "regs.operator[]#9:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "regs.operator[]#9:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "regs.operator[]#9:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "regs.operator[]#9:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "regs.operator[]#9:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "regs.operator[]#9:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "regs.operator[]#9:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "regs.operator[]#9:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "regs.operator[]#9:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "regs.operator[]#9:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "regs.operator[]#9:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "regs.operator[]#9:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "regs.operator[]#9:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "regs.operator[]#9:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "regs.operator[]#9:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "regs.operator[]#9:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "regs.operator[]#9:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "regs.operator[]#9:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "regs.operator[]#9:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "regs.operator[]#9:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "regs.operator[]#9:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "regs.operator[]#9:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "regs.operator[]#9:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "regs.operator[]#9:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "regs.operator[]#9:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "regs.operator[]#9:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "regs.operator[]#9:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "regs.operator[]#9:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "regs.operator[]#9:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#9:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#9:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#9:mux.itm(0)} -pin  "regs.operator[]#9:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(1)} -pin  "regs.operator[]#9:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(2)} -pin  "regs.operator[]#9:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(3)} -pin  "regs.operator[]#9:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(4)} -pin  "regs.operator[]#9:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(5)} -pin  "regs.operator[]#9:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(6)} -pin  "regs.operator[]#9:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(7)} -pin  "regs.operator[]#9:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(8)} -pin  "regs.operator[]#9:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(9)} -pin  "regs.operator[]#9:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load inst "FRAME:for:mul" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 8813 -attr oid 534 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#9:mux.itm(0)} -pin  "FRAME:for:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(1)} -pin  "FRAME:for:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(2)} -pin  "FRAME:for:mul" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(3)} -pin  "FRAME:for:mul" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(4)} -pin  "FRAME:for:mul" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(5)} -pin  "FRAME:for:mul" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(6)} -pin  "FRAME:for:mul" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(7)} -pin  "FRAME:for:mul" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(8)} -pin  "FRAME:for:mul" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(9)} -pin  "FRAME:for:mul" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {PWR} -pin  "FRAME:for:mul" {B(1)} -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(11)} -pin  "FRAME:for:mul" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load inst "FRAME:for:acc#1" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 8814 -attr oid 535 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#5.itm(0)} -pin  "FRAME:for:acc#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(1)} -pin  "FRAME:for:acc#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(2)} -pin  "FRAME:for:acc#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(3)} -pin  "FRAME:for:acc#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(4)} -pin  "FRAME:for:acc#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(5)} -pin  "FRAME:for:acc#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(6)} -pin  "FRAME:for:acc#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(7)} -pin  "FRAME:for:acc#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(8)} -pin  "FRAME:for:acc#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(9)} -pin  "FRAME:for:acc#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(10)} -pin  "FRAME:for:acc#1" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(11)} -pin  "FRAME:for:acc#1" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(12)} -pin  "FRAME:for:acc#1" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(13)} -pin  "FRAME:for:acc#1" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(14)} -pin  "FRAME:for:acc#1" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(15)} -pin  "FRAME:for:acc#1" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:acc#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:acc#1" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:acc#1" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:acc#1" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:acc#1" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:acc#1" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:acc#1" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:acc#1" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:acc#1" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:acc#1" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:acc#1" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(11)} -pin  "FRAME:for:acc#1" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {r(0).sva#3(0)} -pin  "FRAME:for:acc#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(1)} -pin  "FRAME:for:acc#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(2)} -pin  "FRAME:for:acc#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(3)} -pin  "FRAME:for:acc#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(4)} -pin  "FRAME:for:acc#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(5)} -pin  "FRAME:for:acc#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(6)} -pin  "FRAME:for:acc#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(7)} -pin  "FRAME:for:acc#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(8)} -pin  "FRAME:for:acc#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(9)} -pin  "FRAME:for:acc#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(10)} -pin  "FRAME:for:acc#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(11)} -pin  "FRAME:for:acc#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(12)} -pin  "FRAME:for:acc#1" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(13)} -pin  "FRAME:for:acc#1" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(14)} -pin  "FRAME:for:acc#1" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(15)} -pin  "FRAME:for:acc#1" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load inst "FRAME:for:nor" "nor(2,1)" "INTERFACE" -attr xrf 8815 -attr oid 536 -attr @path {/sobel/sobel:core/FRAME:for:nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:nor" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#3.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nor" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#4.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:nor" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load inst "FRAME:for:not#8" "not(1)" "INTERFACE" -attr xrf 8816 -attr oid 537 -attr @path {/sobel/sobel:core/FRAME:for:not#8} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#8" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#10.itm}
+load net {FRAME:for:not#8.itm} -pin  "FRAME:for:not#8" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#8.itm}
+load inst "FRAME:for:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 8817 -attr oid 538 -attr @path {/sobel/sobel:core/FRAME:for:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {FRAME:for:not#8.itm} -pin  "FRAME:for:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#8.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#5.itm}
+load net {FRAME:for:nand#1.itm} -pin  "FRAME:for:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#1.itm}
+load inst "FRAME:for:or#4" "or(2,1)" "INTERFACE" -attr xrf 8818 -attr oid 539 -attr @path {/sobel/sobel:core/FRAME:for:or#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {FRAME:for:nand#1.itm} -pin  "FRAME:for:or#4" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#1.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or#4" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:or#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#4.itm}
+load inst "FRAME:for:not#5" "not(1)" "INTERFACE" -attr xrf 8819 -attr oid 540 -attr @path {/sobel/sobel:core/FRAME:for:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#5" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#8.itm}
+load net {FRAME:for:not#5.itm} -pin  "FRAME:for:not#5" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#5.itm}
+load inst "FRAME:for:nand" "nand(2,1)" "INTERFACE" -attr xrf 8820 -attr oid 541 -attr @path {/sobel/sobel:core/FRAME:for:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#6.itm}
+load net {FRAME:for:not#5.itm} -pin  "FRAME:for:nand" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#5.itm}
+load net {FRAME:for:nand.itm} -pin  "FRAME:for:nand" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand.itm}
+load inst "FRAME:for:not#2" "not(1)" "INTERFACE" -attr xrf 8821 -attr oid 542 -attr @path {/sobel/sobel:core/FRAME:for:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:not#2" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#7.itm}
+load net {FRAME:for:not#2.itm} -pin  "FRAME:for:not#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#2.itm}
+load inst "FRAME:for:and#3" "and(2,1)" "INTERFACE" -attr xrf 8822 -attr oid 543 -attr @path {/sobel/sobel:core/FRAME:for:and#3} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#9.itm}
+load net {FRAME:for:not#2.itm} -pin  "FRAME:for:and#3" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#2.itm}
+load net {FRAME:for:and#3.itm} -pin  "FRAME:for:and#3" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#3.itm}
+load inst "FRAME:for:or#3" "or(3,1)" "INTERFACE" -attr xrf 8823 -attr oid 544 -attr @path {/sobel/sobel:core/FRAME:for:or#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,3)"
+load net {FRAME:for:nand.itm} -pin  "FRAME:for:or#3" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or#3" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:and#3.itm} -pin  "FRAME:for:or#3" {A2(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#3.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:or#3" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#3.itm}
+load inst "nor" "nor(2,1)" "INTERFACE" -attr vt c -attr @path {/sobel/sobel:core/nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "nor" {A0(0)} -attr vt c -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {exit:FRAME#1.sva} -pin  "nor" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {and.dcpl} -pin  "nor" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/and.dcpl}
+### END MODULE 
+
+module new "sobel" "orig"
+load portBus {vin:rsc.z(89:0)} input 90 {vin:rsc.z(89)} {vin:rsc.z(88)} {vin:rsc.z(87)} {vin:rsc.z(86)} {vin:rsc.z(85)} {vin:rsc.z(84)} {vin:rsc.z(83)} {vin:rsc.z(82)} {vin:rsc.z(81)} {vin:rsc.z(80)} {vin:rsc.z(79)} {vin:rsc.z(78)} {vin:rsc.z(77)} {vin:rsc.z(76)} {vin:rsc.z(75)} {vin:rsc.z(74)} {vin:rsc.z(73)} {vin:rsc.z(72)} {vin:rsc.z(71)} {vin:rsc.z(70)} {vin:rsc.z(69)} {vin:rsc.z(68)} {vin:rsc.z(67)} {vin:rsc.z(66)} {vin:rsc.z(65)} {vin:rsc.z(64)} {vin:rsc.z(63)} {vin:rsc.z(62)} {vin:rsc.z(61)} {vin:rsc.z(60)} {vin:rsc.z(59)} {vin:rsc.z(58)} {vin:rsc.z(57)} {vin:rsc.z(56)} {vin:rsc.z(55)} {vin:rsc.z(54)} {vin:rsc.z(53)} {vin:rsc.z(52)} {vin:rsc.z(51)} {vin:rsc.z(50)} {vin:rsc.z(49)} {vin:rsc.z(48)} {vin:rsc.z(47)} {vin:rsc.z(46)} {vin:rsc.z(45)} {vin:rsc.z(44)} {vin:rsc.z(43)} {vin:rsc.z(42)} {vin:rsc.z(41)} {vin:rsc.z(40)} {vin:rsc.z(39)} {vin:rsc.z(38)} {vin:rsc.z(37)} {vin:rsc.z(36)} {vin:rsc.z(35)} {vin:rsc.z(34)} {vin:rsc.z(33)} {vin:rsc.z(32)} {vin:rsc.z(31)} {vin:rsc.z(30)} {vin:rsc.z(29)} {vin:rsc.z(28)} {vin:rsc.z(27)} {vin:rsc.z(26)} {vin:rsc.z(25)} {vin:rsc.z(24)} {vin:rsc.z(23)} {vin:rsc.z(22)} {vin:rsc.z(21)} {vin:rsc.z(20)} {vin:rsc.z(19)} {vin:rsc.z(18)} {vin:rsc.z(17)} {vin:rsc.z(16)} {vin:rsc.z(15)} {vin:rsc.z(14)} {vin:rsc.z(13)} {vin:rsc.z(12)} {vin:rsc.z(11)} {vin:rsc.z(10)} {vin:rsc.z(9)} {vin:rsc.z(8)} {vin:rsc.z(7)} {vin:rsc.z(6)} {vin:rsc.z(5)} {vin:rsc.z(4)} {vin:rsc.z(3)} {vin:rsc.z(2)} {vin:rsc.z(1)} {vin:rsc.z(0)} -attr xrf 8824 -attr oid 545 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load portBus {vout:rsc.z(29:0)} output 30 {vout:rsc.z(29)} {vout:rsc.z(28)} {vout:rsc.z(27)} {vout:rsc.z(26)} {vout:rsc.z(25)} {vout:rsc.z(24)} {vout:rsc.z(23)} {vout:rsc.z(22)} {vout:rsc.z(21)} {vout:rsc.z(20)} {vout:rsc.z(19)} {vout:rsc.z(18)} {vout:rsc.z(17)} {vout:rsc.z(16)} {vout:rsc.z(15)} {vout:rsc.z(14)} {vout:rsc.z(13)} {vout:rsc.z(12)} {vout:rsc.z(11)} {vout:rsc.z(10)} {vout:rsc.z(9)} {vout:rsc.z(8)} {vout:rsc.z(7)} {vout:rsc.z(6)} {vout:rsc.z(5)} {vout:rsc.z(4)} {vout:rsc.z(3)} {vout:rsc.z(2)} {vout:rsc.z(1)} {vout:rsc.z(0)} -attr xrf 8825 -attr oid 546 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load port {clk} input -attr xrf 8826 -attr oid 547 -attr vt d -attr @path {/sobel/clk}
+load port {en} input -attr xrf 8827 -attr oid 548 -attr vt d -attr @path {/sobel/en}
+load port {arst_n} input -attr xrf 8828 -attr oid 549 -attr vt d -attr @path {/sobel/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(89:0)} output 90 {d(89)} {d(88)} {d(87)} {d(86)} {d(85)} {d(84)} {d(83)} {d(82)} {d(81)} {d(80)} {d(79)} {d(78)} {d(77)} {d(76)} {d(75)} {d(74)} {d(73)} {d(72)} {d(71)} {d(70)} {d(69)} {d(68)} {d(67)} {d(66)} {d(65)} {d(64)} {d(63)} {d(62)} {d(61)} {d(60)} {d(59)} {d(58)} {d(57)} {d(56)} {d(55)} {d(54)} {d(53)} {d(52)} {d(51)} {d(50)} {d(49)} {d(48)} {d(47)} {d(46)} {d(45)} {d(44)} {d(43)} {d(42)} {d(41)} {d(40)} {d(39)} {d(38)} {d(37)} {d(36)} {d(35)} {d(34)} {d(33)} {d(32)} {d(31)} {d(30)} {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(89:0)} input 90 {z(89)} {z(88)} {z(87)} {z(86)} {z(85)} {z(84)} {z(83)} {z(82)} {z(81)} {z(80)} {z(79)} {z(78)} {z(77)} {z(76)} {z(75)} {z(74)} {z(73)} {z(72)} {z(71)} {z(70)} {z(69)} {z(68)} {z(67)} {z(66)} {z(65)} {z(64)} {z(63)} {z(62)} {z(61)} {z(60)} {z(59)} {z(58)} {z(57)} {z(56)} {z(55)} {z(54)} {z(53)} {z(52)} {z(51)} {z(50)} {z(49)} {z(48)} {z(47)} {z(46)} {z(45)} {z(44)} {z(43)} {z(42)} {z(41)} {z(40)} {z(39)} {z(38)} {z(37)} {z(36)} {z(35)} {z(34)} {z(33)} {z(32)} {z(31)} {z(30)} {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(29:0)} input 30 {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(29:0)} output 30 {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "sobel:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} \
+     portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} \
+
+load net {vin:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d#1} 90 {vin:rsc:mgc_in_wire.d#1(0)} {vin:rsc:mgc_in_wire.d#1(1)} {vin:rsc:mgc_in_wire.d#1(2)} {vin:rsc:mgc_in_wire.d#1(3)} {vin:rsc:mgc_in_wire.d#1(4)} {vin:rsc:mgc_in_wire.d#1(5)} {vin:rsc:mgc_in_wire.d#1(6)} {vin:rsc:mgc_in_wire.d#1(7)} {vin:rsc:mgc_in_wire.d#1(8)} {vin:rsc:mgc_in_wire.d#1(9)} {vin:rsc:mgc_in_wire.d#1(10)} {vin:rsc:mgc_in_wire.d#1(11)} {vin:rsc:mgc_in_wire.d#1(12)} {vin:rsc:mgc_in_wire.d#1(13)} {vin:rsc:mgc_in_wire.d#1(14)} {vin:rsc:mgc_in_wire.d#1(15)} {vin:rsc:mgc_in_wire.d#1(16)} {vin:rsc:mgc_in_wire.d#1(17)} {vin:rsc:mgc_in_wire.d#1(18)} {vin:rsc:mgc_in_wire.d#1(19)} {vin:rsc:mgc_in_wire.d#1(20)} {vin:rsc:mgc_in_wire.d#1(21)} {vin:rsc:mgc_in_wire.d#1(22)} {vin:rsc:mgc_in_wire.d#1(23)} {vin:rsc:mgc_in_wire.d#1(24)} {vin:rsc:mgc_in_wire.d#1(25)} {vin:rsc:mgc_in_wire.d#1(26)} {vin:rsc:mgc_in_wire.d#1(27)} {vin:rsc:mgc_in_wire.d#1(28)} {vin:rsc:mgc_in_wire.d#1(29)} {vin:rsc:mgc_in_wire.d#1(30)} {vin:rsc:mgc_in_wire.d#1(31)} {vin:rsc:mgc_in_wire.d#1(32)} {vin:rsc:mgc_in_wire.d#1(33)} {vin:rsc:mgc_in_wire.d#1(34)} {vin:rsc:mgc_in_wire.d#1(35)} {vin:rsc:mgc_in_wire.d#1(36)} {vin:rsc:mgc_in_wire.d#1(37)} {vin:rsc:mgc_in_wire.d#1(38)} {vin:rsc:mgc_in_wire.d#1(39)} {vin:rsc:mgc_in_wire.d#1(40)} {vin:rsc:mgc_in_wire.d#1(41)} {vin:rsc:mgc_in_wire.d#1(42)} {vin:rsc:mgc_in_wire.d#1(43)} {vin:rsc:mgc_in_wire.d#1(44)} {vin:rsc:mgc_in_wire.d#1(45)} {vin:rsc:mgc_in_wire.d#1(46)} {vin:rsc:mgc_in_wire.d#1(47)} {vin:rsc:mgc_in_wire.d#1(48)} {vin:rsc:mgc_in_wire.d#1(49)} {vin:rsc:mgc_in_wire.d#1(50)} {vin:rsc:mgc_in_wire.d#1(51)} {vin:rsc:mgc_in_wire.d#1(52)} {vin:rsc:mgc_in_wire.d#1(53)} {vin:rsc:mgc_in_wire.d#1(54)} {vin:rsc:mgc_in_wire.d#1(55)} {vin:rsc:mgc_in_wire.d#1(56)} {vin:rsc:mgc_in_wire.d#1(57)} {vin:rsc:mgc_in_wire.d#1(58)} {vin:rsc:mgc_in_wire.d#1(59)} {vin:rsc:mgc_in_wire.d#1(60)} {vin:rsc:mgc_in_wire.d#1(61)} {vin:rsc:mgc_in_wire.d#1(62)} {vin:rsc:mgc_in_wire.d#1(63)} {vin:rsc:mgc_in_wire.d#1(64)} {vin:rsc:mgc_in_wire.d#1(65)} {vin:rsc:mgc_in_wire.d#1(66)} {vin:rsc:mgc_in_wire.d#1(67)} {vin:rsc:mgc_in_wire.d#1(68)} {vin:rsc:mgc_in_wire.d#1(69)} {vin:rsc:mgc_in_wire.d#1(70)} {vin:rsc:mgc_in_wire.d#1(71)} {vin:rsc:mgc_in_wire.d#1(72)} {vin:rsc:mgc_in_wire.d#1(73)} {vin:rsc:mgc_in_wire.d#1(74)} {vin:rsc:mgc_in_wire.d#1(75)} {vin:rsc:mgc_in_wire.d#1(76)} {vin:rsc:mgc_in_wire.d#1(77)} {vin:rsc:mgc_in_wire.d#1(78)} {vin:rsc:mgc_in_wire.d#1(79)} {vin:rsc:mgc_in_wire.d#1(80)} {vin:rsc:mgc_in_wire.d#1(81)} {vin:rsc:mgc_in_wire.d#1(82)} {vin:rsc:mgc_in_wire.d#1(83)} {vin:rsc:mgc_in_wire.d#1(84)} {vin:rsc:mgc_in_wire.d#1(85)} {vin:rsc:mgc_in_wire.d#1(86)} {vin:rsc:mgc_in_wire.d#1(87)} {vin:rsc:mgc_in_wire.d#1(88)} {vin:rsc:mgc_in_wire.d#1(89)} -attr xrf 8829 -attr oid 550 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -attr vt d
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+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -attr vt d
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+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d#1} 30 {vout:rsc:mgc_out_stdreg.d#1(0)} {vout:rsc:mgc_out_stdreg.d#1(1)} {vout:rsc:mgc_out_stdreg.d#1(2)} {vout:rsc:mgc_out_stdreg.d#1(3)} {vout:rsc:mgc_out_stdreg.d#1(4)} {vout:rsc:mgc_out_stdreg.d#1(5)} {vout:rsc:mgc_out_stdreg.d#1(6)} {vout:rsc:mgc_out_stdreg.d#1(7)} {vout:rsc:mgc_out_stdreg.d#1(8)} {vout:rsc:mgc_out_stdreg.d#1(9)} {vout:rsc:mgc_out_stdreg.d#1(10)} {vout:rsc:mgc_out_stdreg.d#1(11)} {vout:rsc:mgc_out_stdreg.d#1(12)} {vout:rsc:mgc_out_stdreg.d#1(13)} {vout:rsc:mgc_out_stdreg.d#1(14)} {vout:rsc:mgc_out_stdreg.d#1(15)} {vout:rsc:mgc_out_stdreg.d#1(16)} {vout:rsc:mgc_out_stdreg.d#1(17)} {vout:rsc:mgc_out_stdreg.d#1(18)} {vout:rsc:mgc_out_stdreg.d#1(19)} {vout:rsc:mgc_out_stdreg.d#1(20)} {vout:rsc:mgc_out_stdreg.d#1(21)} {vout:rsc:mgc_out_stdreg.d#1(22)} {vout:rsc:mgc_out_stdreg.d#1(23)} {vout:rsc:mgc_out_stdreg.d#1(24)} {vout:rsc:mgc_out_stdreg.d#1(25)} {vout:rsc:mgc_out_stdreg.d#1(26)} {vout:rsc:mgc_out_stdreg.d#1(27)} {vout:rsc:mgc_out_stdreg.d#1(28)} {vout:rsc:mgc_out_stdreg.d#1(29)} -attr xrf 8830 -attr oid 551 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -attr vt d
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+load net {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 8831 -attr oid 552 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(0)} -port {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -port {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -port {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -port {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -port {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -port {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -port {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -port {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -port {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -port {vin:rsc.z(9)} -attr vt d
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+load net {vin:rsc.z(60)} -port {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -port {vin:rsc.z(61)} -attr vt d
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+load net {vin:rsc.z(66)} -port {vin:rsc.z(66)} -attr vt d
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+load net {vin:rsc.z(89)} -port {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 8832 -attr oid 553 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vout:rsc.z(0)} -attr vt d
+load net {vout:rsc.z(1)} -attr vt d
+load net {vout:rsc.z(2)} -attr vt d
+load net {vout:rsc.z(3)} -attr vt d
+load net {vout:rsc.z(4)} -attr vt d
+load net {vout:rsc.z(5)} -attr vt d
+load net {vout:rsc.z(6)} -attr vt d
+load net {vout:rsc.z(7)} -attr vt d
+load net {vout:rsc.z(8)} -attr vt d
+load net {vout:rsc.z(9)} -attr vt d
+load net {vout:rsc.z(10)} -attr vt d
+load net {vout:rsc.z(11)} -attr vt d
+load net {vout:rsc.z(12)} -attr vt d
+load net {vout:rsc.z(13)} -attr vt d
+load net {vout:rsc.z(14)} -attr vt d
+load net {vout:rsc.z(15)} -attr vt d
+load net {vout:rsc.z(16)} -attr vt d
+load net {vout:rsc.z(17)} -attr vt d
+load net {vout:rsc.z(18)} -attr vt d
+load net {vout:rsc.z(19)} -attr vt d
+load net {vout:rsc.z(20)} -attr vt d
+load net {vout:rsc.z(21)} -attr vt d
+load net {vout:rsc.z(22)} -attr vt d
+load net {vout:rsc.z(23)} -attr vt d
+load net {vout:rsc.z(24)} -attr vt d
+load net {vout:rsc.z(25)} -attr vt d
+load net {vout:rsc.z(26)} -attr vt d
+load net {vout:rsc.z(27)} -attr vt d
+load net {vout:rsc.z(28)} -attr vt d
+load net {vout:rsc.z(29)} -attr vt d
+load netBundle {vout:rsc.z} 30 {vout:rsc.z(0)} {vout:rsc.z(1)} {vout:rsc.z(2)} {vout:rsc.z(3)} {vout:rsc.z(4)} {vout:rsc.z(5)} {vout:rsc.z(6)} {vout:rsc.z(7)} {vout:rsc.z(8)} {vout:rsc.z(9)} {vout:rsc.z(10)} {vout:rsc.z(11)} {vout:rsc.z(12)} {vout:rsc.z(13)} {vout:rsc.z(14)} {vout:rsc.z(15)} {vout:rsc.z(16)} {vout:rsc.z(17)} {vout:rsc.z(18)} {vout:rsc.z(19)} {vout:rsc.z(20)} {vout:rsc.z(21)} {vout:rsc.z(22)} {vout:rsc.z(23)} {vout:rsc.z(24)} {vout:rsc.z(25)} {vout:rsc.z(26)} {vout:rsc.z(27)} {vout:rsc.z(28)} {vout:rsc.z(29)} -attr xrf 8833 -attr oid 554 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(0)} -port {vout:rsc.z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -port {vout:rsc.z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -port {vout:rsc.z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -port {vout:rsc.z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -port {vout:rsc.z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -port {vout:rsc.z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -port {vout:rsc.z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -port {vout:rsc.z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -port {vout:rsc.z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -port {vout:rsc.z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -port {vout:rsc.z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -port {vout:rsc.z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -port {vout:rsc.z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -port {vout:rsc.z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -port {vout:rsc.z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -port {vout:rsc.z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -port {vout:rsc.z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -port {vout:rsc.z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -port {vout:rsc.z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -port {vout:rsc.z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -port {vout:rsc.z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -port {vout:rsc.z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -port {vout:rsc.z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -port {vout:rsc.z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -port {vout:rsc.z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -port {vout:rsc.z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -port {vout:rsc.z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -port {vout:rsc.z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -port {vout:rsc.z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -port {vout:rsc.z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {clk} -attr xrf 8834 -attr oid 555
+load net {clk} -port {clk} -attr xrf 8835 -attr oid 556
+load net {en} -attr xrf 8836 -attr oid 557
+load net {en} -port {en} -attr xrf 8837 -attr oid 558
+load net {arst_n} -attr xrf 8838 -attr oid 559
+load net {arst_n} -port {arst_n} -attr xrf 8839 -attr oid 560
+load inst "sobel:core:inst" "sobel:core" "orig" -attr xrf 8840 -attr oid 561 -attr vt dc -attr @path {/sobel/sobel:core:inst} -attr area 5150.730536 -attr delay 15.796511 -attr hier "/sobel/sobel:core" -pg 1 -lvl 3
+load net {clk} -pin  "sobel:core:inst" {clk#1} -attr xrf 8841 -attr oid 562 -attr @path {/sobel/clk}
+load net {en} -pin  "sobel:core:inst" {en#1} -attr xrf 8842 -attr oid 563 -attr @path {/sobel/en}
+load net {arst_n} -pin  "sobel:core:inst" {arst_n#1} -attr xrf 8843 -attr oid 564 -attr @path {/sobel/arst_n}
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(8)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(9)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(10)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(11)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(12)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(13)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(14)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(15)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(16)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(17)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(18)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(19)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(20)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(21)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(22)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(23)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(24)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(25)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(26)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(27)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(28)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(29)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(30)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(31)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(32)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(33)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(34)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(35)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(36)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(37)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(38)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(39)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(40)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(41)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(42)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(43)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(44)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(45)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(46)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(47)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(48)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(49)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(50)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(51)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(52)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(53)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(54)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(55)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(56)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(57)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(58)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(59)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(60)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(61)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(62)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(63)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(64)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(65)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(66)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(67)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(68)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(69)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(70)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(71)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(72)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(73)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(74)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(75)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(76)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(77)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(78)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(79)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(80)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(81)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(82)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(83)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(84)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(85)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(86)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(87)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(88)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(89)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(8)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(9)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(10)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(11)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(12)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(13)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(14)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(15)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(16)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(17)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(18)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(19)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(20)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(21)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(22)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(23)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(24)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(25)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(26)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(27)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(28)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(29)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load inst "vin:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" -attr xrf 8844 -attr oid 565 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,90)" -pg 1 -lvl 1
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "vin:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "vin:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "vin:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "vin:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "vin:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "vin:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "vin:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "vin:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "vin:rsc:mgc_in_wire" {d(8)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "vin:rsc:mgc_in_wire" {d(9)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "vin:rsc:mgc_in_wire" {d(10)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "vin:rsc:mgc_in_wire" {d(11)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "vin:rsc:mgc_in_wire" {d(12)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "vin:rsc:mgc_in_wire" {d(13)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "vin:rsc:mgc_in_wire" {d(14)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "vin:rsc:mgc_in_wire" {d(15)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "vin:rsc:mgc_in_wire" {d(16)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "vin:rsc:mgc_in_wire" {d(17)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "vin:rsc:mgc_in_wire" {d(18)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "vin:rsc:mgc_in_wire" {d(19)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "vin:rsc:mgc_in_wire" {d(20)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "vin:rsc:mgc_in_wire" {d(21)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "vin:rsc:mgc_in_wire" {d(22)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "vin:rsc:mgc_in_wire" {d(23)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "vin:rsc:mgc_in_wire" {d(24)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "vin:rsc:mgc_in_wire" {d(25)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "vin:rsc:mgc_in_wire" {d(26)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "vin:rsc:mgc_in_wire" {d(27)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "vin:rsc:mgc_in_wire" {d(28)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "vin:rsc:mgc_in_wire" {d(29)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "vin:rsc:mgc_in_wire" {d(30)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "vin:rsc:mgc_in_wire" {d(31)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "vin:rsc:mgc_in_wire" {d(32)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "vin:rsc:mgc_in_wire" {d(33)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "vin:rsc:mgc_in_wire" {d(34)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "vin:rsc:mgc_in_wire" {d(35)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "vin:rsc:mgc_in_wire" {d(36)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "vin:rsc:mgc_in_wire" {d(37)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "vin:rsc:mgc_in_wire" {d(38)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "vin:rsc:mgc_in_wire" {d(39)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "vin:rsc:mgc_in_wire" {d(40)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "vin:rsc:mgc_in_wire" {d(41)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "vin:rsc:mgc_in_wire" {d(42)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "vin:rsc:mgc_in_wire" {d(43)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "vin:rsc:mgc_in_wire" {d(44)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "vin:rsc:mgc_in_wire" {d(45)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "vin:rsc:mgc_in_wire" {d(46)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "vin:rsc:mgc_in_wire" {d(47)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "vin:rsc:mgc_in_wire" {d(48)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "vin:rsc:mgc_in_wire" {d(49)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "vin:rsc:mgc_in_wire" {d(50)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "vin:rsc:mgc_in_wire" {d(51)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "vin:rsc:mgc_in_wire" {d(52)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "vin:rsc:mgc_in_wire" {d(53)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "vin:rsc:mgc_in_wire" {d(54)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "vin:rsc:mgc_in_wire" {d(55)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "vin:rsc:mgc_in_wire" {d(56)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "vin:rsc:mgc_in_wire" {d(57)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "vin:rsc:mgc_in_wire" {d(58)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "vin:rsc:mgc_in_wire" {d(59)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "vin:rsc:mgc_in_wire" {d(60)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "vin:rsc:mgc_in_wire" {d(61)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "vin:rsc:mgc_in_wire" {d(62)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "vin:rsc:mgc_in_wire" {d(63)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "vin:rsc:mgc_in_wire" {d(64)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "vin:rsc:mgc_in_wire" {d(65)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "vin:rsc:mgc_in_wire" {d(66)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "vin:rsc:mgc_in_wire" {d(67)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "vin:rsc:mgc_in_wire" {d(68)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "vin:rsc:mgc_in_wire" {d(69)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "vin:rsc:mgc_in_wire" {d(70)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "vin:rsc:mgc_in_wire" {d(71)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "vin:rsc:mgc_in_wire" {d(72)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "vin:rsc:mgc_in_wire" {d(73)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "vin:rsc:mgc_in_wire" {d(74)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "vin:rsc:mgc_in_wire" {d(75)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "vin:rsc:mgc_in_wire" {d(76)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "vin:rsc:mgc_in_wire" {d(77)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "vin:rsc:mgc_in_wire" {d(78)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "vin:rsc:mgc_in_wire" {d(79)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "vin:rsc:mgc_in_wire" {d(80)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "vin:rsc:mgc_in_wire" {d(81)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "vin:rsc:mgc_in_wire" {d(82)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "vin:rsc:mgc_in_wire" {d(83)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "vin:rsc:mgc_in_wire" {d(84)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "vin:rsc:mgc_in_wire" {d(85)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "vin:rsc:mgc_in_wire" {d(86)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "vin:rsc:mgc_in_wire" {d(87)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "vin:rsc:mgc_in_wire" {d(88)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "vin:rsc:mgc_in_wire" {d(89)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc.z(0)} -pin  "vin:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(1)} -pin  "vin:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(2)} -pin  "vin:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(3)} -pin  "vin:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(4)} -pin  "vin:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(5)} -pin  "vin:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(6)} -pin  "vin:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(7)} -pin  "vin:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(8)} -pin  "vin:rsc:mgc_in_wire" {z(8)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(9)} -pin  "vin:rsc:mgc_in_wire" {z(9)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(10)} -pin  "vin:rsc:mgc_in_wire" {z(10)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(11)} -pin  "vin:rsc:mgc_in_wire" {z(11)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(12)} -pin  "vin:rsc:mgc_in_wire" {z(12)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(13)} -pin  "vin:rsc:mgc_in_wire" {z(13)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(14)} -pin  "vin:rsc:mgc_in_wire" {z(14)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(15)} -pin  "vin:rsc:mgc_in_wire" {z(15)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(16)} -pin  "vin:rsc:mgc_in_wire" {z(16)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(17)} -pin  "vin:rsc:mgc_in_wire" {z(17)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(18)} -pin  "vin:rsc:mgc_in_wire" {z(18)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(19)} -pin  "vin:rsc:mgc_in_wire" {z(19)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(20)} -pin  "vin:rsc:mgc_in_wire" {z(20)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(21)} -pin  "vin:rsc:mgc_in_wire" {z(21)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(22)} -pin  "vin:rsc:mgc_in_wire" {z(22)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(23)} -pin  "vin:rsc:mgc_in_wire" {z(23)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(24)} -pin  "vin:rsc:mgc_in_wire" {z(24)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(25)} -pin  "vin:rsc:mgc_in_wire" {z(25)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(26)} -pin  "vin:rsc:mgc_in_wire" {z(26)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(27)} -pin  "vin:rsc:mgc_in_wire" {z(27)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(28)} -pin  "vin:rsc:mgc_in_wire" {z(28)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(29)} -pin  "vin:rsc:mgc_in_wire" {z(29)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(30)} -pin  "vin:rsc:mgc_in_wire" {z(30)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(31)} -pin  "vin:rsc:mgc_in_wire" {z(31)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(32)} -pin  "vin:rsc:mgc_in_wire" {z(32)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(33)} -pin  "vin:rsc:mgc_in_wire" {z(33)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(34)} -pin  "vin:rsc:mgc_in_wire" {z(34)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(35)} -pin  "vin:rsc:mgc_in_wire" {z(35)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(36)} -pin  "vin:rsc:mgc_in_wire" {z(36)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(37)} -pin  "vin:rsc:mgc_in_wire" {z(37)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(38)} -pin  "vin:rsc:mgc_in_wire" {z(38)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(39)} -pin  "vin:rsc:mgc_in_wire" {z(39)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(40)} -pin  "vin:rsc:mgc_in_wire" {z(40)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(41)} -pin  "vin:rsc:mgc_in_wire" {z(41)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(42)} -pin  "vin:rsc:mgc_in_wire" {z(42)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(43)} -pin  "vin:rsc:mgc_in_wire" {z(43)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(44)} -pin  "vin:rsc:mgc_in_wire" {z(44)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(45)} -pin  "vin:rsc:mgc_in_wire" {z(45)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(46)} -pin  "vin:rsc:mgc_in_wire" {z(46)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(47)} -pin  "vin:rsc:mgc_in_wire" {z(47)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(48)} -pin  "vin:rsc:mgc_in_wire" {z(48)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(49)} -pin  "vin:rsc:mgc_in_wire" {z(49)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(50)} -pin  "vin:rsc:mgc_in_wire" {z(50)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(51)} -pin  "vin:rsc:mgc_in_wire" {z(51)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(52)} -pin  "vin:rsc:mgc_in_wire" {z(52)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(53)} -pin  "vin:rsc:mgc_in_wire" {z(53)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(54)} -pin  "vin:rsc:mgc_in_wire" {z(54)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(55)} -pin  "vin:rsc:mgc_in_wire" {z(55)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(56)} -pin  "vin:rsc:mgc_in_wire" {z(56)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(57)} -pin  "vin:rsc:mgc_in_wire" {z(57)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(58)} -pin  "vin:rsc:mgc_in_wire" {z(58)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(59)} -pin  "vin:rsc:mgc_in_wire" {z(59)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(60)} -pin  "vin:rsc:mgc_in_wire" {z(60)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(61)} -pin  "vin:rsc:mgc_in_wire" {z(61)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(62)} -pin  "vin:rsc:mgc_in_wire" {z(62)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(63)} -pin  "vin:rsc:mgc_in_wire" {z(63)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(64)} -pin  "vin:rsc:mgc_in_wire" {z(64)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(65)} -pin  "vin:rsc:mgc_in_wire" {z(65)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(66)} -pin  "vin:rsc:mgc_in_wire" {z(66)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(67)} -pin  "vin:rsc:mgc_in_wire" {z(67)} -attr vt d -attr @path {/sobel/vin:rsc.z}
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+load net {vin:rsc.z(70)} -pin  "vin:rsc:mgc_in_wire" {z(70)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(71)} -pin  "vin:rsc:mgc_in_wire" {z(71)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(72)} -pin  "vin:rsc:mgc_in_wire" {z(72)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(73)} -pin  "vin:rsc:mgc_in_wire" {z(73)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(74)} -pin  "vin:rsc:mgc_in_wire" {z(74)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(75)} -pin  "vin:rsc:mgc_in_wire" {z(75)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(76)} -pin  "vin:rsc:mgc_in_wire" {z(76)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(77)} -pin  "vin:rsc:mgc_in_wire" {z(77)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(78)} -pin  "vin:rsc:mgc_in_wire" {z(78)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(79)} -pin  "vin:rsc:mgc_in_wire" {z(79)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(80)} -pin  "vin:rsc:mgc_in_wire" {z(80)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(81)} -pin  "vin:rsc:mgc_in_wire" {z(81)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(82)} -pin  "vin:rsc:mgc_in_wire" {z(82)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(83)} -pin  "vin:rsc:mgc_in_wire" {z(83)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(84)} -pin  "vin:rsc:mgc_in_wire" {z(84)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(85)} -pin  "vin:rsc:mgc_in_wire" {z(85)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(86)} -pin  "vin:rsc:mgc_in_wire" {z(86)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(87)} -pin  "vin:rsc:mgc_in_wire" {z(87)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(88)} -pin  "vin:rsc:mgc_in_wire" {z(88)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(89)} -pin  "vin:rsc:mgc_in_wire" {z(89)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load inst "vout:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" -attr xrf 8845 -attr oid 566 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(2,30)" -pg 1 -lvl 1002
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "vout:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "vout:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "vout:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "vout:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "vout:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "vout:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "vout:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "vout:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "vout:rsc:mgc_out_stdreg" {d(8)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "vout:rsc:mgc_out_stdreg" {d(9)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "vout:rsc:mgc_out_stdreg" {d(10)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "vout:rsc:mgc_out_stdreg" {d(11)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "vout:rsc:mgc_out_stdreg" {d(12)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "vout:rsc:mgc_out_stdreg" {d(13)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "vout:rsc:mgc_out_stdreg" {d(14)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "vout:rsc:mgc_out_stdreg" {d(15)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "vout:rsc:mgc_out_stdreg" {d(16)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "vout:rsc:mgc_out_stdreg" {d(17)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "vout:rsc:mgc_out_stdreg" {d(18)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "vout:rsc:mgc_out_stdreg" {d(19)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "vout:rsc:mgc_out_stdreg" {d(20)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "vout:rsc:mgc_out_stdreg" {d(21)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "vout:rsc:mgc_out_stdreg" {d(22)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "vout:rsc:mgc_out_stdreg" {d(23)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "vout:rsc:mgc_out_stdreg" {d(24)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "vout:rsc:mgc_out_stdreg" {d(25)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "vout:rsc:mgc_out_stdreg" {d(26)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "vout:rsc:mgc_out_stdreg" {d(27)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "vout:rsc:mgc_out_stdreg" {d(28)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "vout:rsc:mgc_out_stdreg" {d(29)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc.z(0)} -pin  "vout:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -pin  "vout:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -pin  "vout:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -pin  "vout:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -pin  "vout:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -pin  "vout:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -pin  "vout:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -pin  "vout:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -pin  "vout:rsc:mgc_out_stdreg" {z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -pin  "vout:rsc:mgc_out_stdreg" {z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -pin  "vout:rsc:mgc_out_stdreg" {z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -pin  "vout:rsc:mgc_out_stdreg" {z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -pin  "vout:rsc:mgc_out_stdreg" {z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -pin  "vout:rsc:mgc_out_stdreg" {z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -pin  "vout:rsc:mgc_out_stdreg" {z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -pin  "vout:rsc:mgc_out_stdreg" {z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -pin  "vout:rsc:mgc_out_stdreg" {z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -pin  "vout:rsc:mgc_out_stdreg" {z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -pin  "vout:rsc:mgc_out_stdreg" {z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -pin  "vout:rsc:mgc_out_stdreg" {z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -pin  "vout:rsc:mgc_out_stdreg" {z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -pin  "vout:rsc:mgc_out_stdreg" {z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -pin  "vout:rsc:mgc_out_stdreg" {z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -pin  "vout:rsc:mgc_out_stdreg" {z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -pin  "vout:rsc:mgc_out_stdreg" {z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -pin  "vout:rsc:mgc_out_stdreg" {z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -pin  "vout:rsc:mgc_out_stdreg" {z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -pin  "vout:rsc:mgc_out_stdreg" {z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -pin  "vout:rsc:mgc_out_stdreg" {z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -pin  "vout:rsc:mgc_out_stdreg" {z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+### END MODULE 
+
diff --git a/Sobel/sobel.v4/concat_rtl.v b/Sobel/sobel.v4/concat_rtl.v
new file mode 100644
index 0000000..48bea34
--- /dev/null
+++ b/Sobel/sobel.v4/concat_rtl.v
@@ -0,0 +1,2049 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:22:40 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  wire and_dcpl;
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [89:0] regs_regs_2_lpi_1_dfm;
+  reg [15:0] r_0_sva_1;
+  reg [15:0] g_0_sva_1;
+  reg [15:0] b_0_sva_1;
+  reg [15:0] r_2_sva_1;
+  reg [15:0] g_2_sva_1;
+  reg [15:0] b_2_sva_1;
+  reg [1:0] i_6_sva_1;
+  reg exit_FRAME_lpi_1_dfm_1;
+  reg [8:0] FRAME_mul_2_itm_1;
+  wire [17:0] nl_FRAME_mul_2_itm_1;
+  reg [5:0] FRAME_slc_green_10_itm_1;
+  reg [4:0] FRAME_acc_25_itm_1;
+  wire [6:0] nl_FRAME_acc_25_itm_1;
+  reg [11:0] FRAME_mul_3_itm_1;
+  wire [23:0] nl_FRAME_mul_3_itm_1;
+  reg [8:0] FRAME_mul_itm_1;
+  wire [17:0] nl_FRAME_mul_itm_1;
+  reg [5:0] FRAME_slc_red_10_itm_1;
+  reg [4:0] FRAME_acc_35_itm_1;
+  wire [6:0] nl_FRAME_acc_35_itm_1;
+  reg [9:0] FRAME_mul_1_itm_1;
+  wire [19:0] nl_FRAME_mul_1_itm_1;
+  reg [8:0] FRAME_mul_4_itm_1;
+  wire [17:0] nl_FRAME_mul_4_itm_1;
+  reg [5:0] FRAME_slc_blue_10_itm_1;
+  reg [4:0] FRAME_acc_40_itm_1;
+  wire [6:0] nl_FRAME_acc_40_itm_1;
+  reg [11:0] FRAME_mul_5_itm_1;
+  wire [23:0] nl_FRAME_mul_5_itm_1;
+  reg exit_FRAME_for_sva_1_st_1;
+  reg main_stage_0_2;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+  wire [11:0] FRAME_acc_3_psp_sva;
+  wire [12:0] nl_FRAME_acc_3_psp_sva;
+  wire [1:0] i_6_sva_2;
+  wire [2:0] nl_i_6_sva_2;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire exit_FRAME_for_lpi_1_dfm;
+  wire [89:0] regs_regs_2_lpi_1_dfm_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire exit_FRAME_lpi_1_dfm_1_mx0;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [15:0] blue_2_sva;
+  wire [16:0] nl_blue_2_sva;
+  wire [5:0] FRAME_acc_11_psp_sva;
+  wire [6:0] nl_FRAME_acc_11_psp_sva;
+  wire [15:0] red_2_sva;
+  wire [16:0] nl_red_2_sva;
+  wire [5:0] FRAME_acc_7_psp_sva;
+  wire [6:0] nl_FRAME_acc_7_psp_sva;
+  wire [4:0] FRAME_acc_28_sdt;
+  wire [5:0] nl_FRAME_acc_28_sdt;
+  wire [15:0] green_2_sva;
+  wire [16:0] nl_green_2_sva;
+  wire [5:0] FRAME_acc_9_psp_sva;
+  wire [6:0] nl_FRAME_acc_9_psp_sva;
+  wire [4:0] FRAME_acc_18_sdt;
+  wire [5:0] nl_FRAME_acc_18_sdt;
+  wire [4:0] FRAME_acc_13_sdt;
+  wire [5:0] nl_FRAME_acc_13_sdt;
+  wire [15:0] b_2_sva_3;
+  wire [16:0] nl_b_2_sva_3;
+  wire [15:0] b_0_sva_3;
+  wire [16:0] nl_b_0_sva_3;
+  wire [15:0] g_2_sva_3;
+  wire [16:0] nl_g_2_sva_3;
+  wire [15:0] g_0_sva_3;
+  wire [16:0] nl_g_0_sva_3;
+  wire [15:0] r_2_sva_3;
+  wire [16:0] nl_r_2_sva_3;
+  wire [15:0] r_0_sva_3;
+  wire [16:0] nl_r_0_sva_3;
+  wire FRAME_for_nor_cse;
+  wire [4:0] FRAME_acc_32_itm;
+  wire [5:0] nl_FRAME_acc_32_itm;
+  wire [4:0] FRAME_acc_17_itm;
+  wire [5:0] nl_FRAME_acc_17_itm;
+  wire [4:0] FRAME_acc_22_itm;
+  wire [5:0] nl_FRAME_acc_22_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_3_itm;
+
+  wire[15:0] FRAME_for_mux_10_nl;
+  wire[9:0] regs_operator_17_mux_nl;
+  wire[15:0] FRAME_for_mux_9_nl;
+  wire[9:0] regs_operator_11_mux_nl;
+  wire[15:0] FRAME_for_mux_8_nl;
+  wire[9:0] regs_operator_16_mux_nl;
+  wire[15:0] FRAME_for_mux_7_nl;
+  wire[9:0] regs_operator_10_mux_nl;
+  wire[15:0] FRAME_for_mux_6_nl;
+  wire[9:0] regs_operator_15_mux_nl;
+  wire[15:0] FRAME_for_mux_5_nl;
+  wire[9:0] regs_operator_9_mux_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_3_psp_sva = conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_2_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(FRAME_slc_green_10_itm_1) + conv_s2s_5_8(FRAME_acc_25_itm_1)))
+      + FRAME_mul_3_itm_1;
+  assign FRAME_acc_3_psp_sva = nl_FRAME_acc_3_psp_sva[11:0];
+  assign nl_FRAME_for_acc_itm = i_6_sva_2 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  assign nl_i_6_sva_2 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_2 = nl_i_6_sva_2[1:0];
+  assign i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm));
+  assign exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva;
+  assign regs_regs_2_lpi_1_dfm_mx0 = MUX_v_90_2_2({regs_regs_1_sva , regs_regs_2_lpi_1_dfm},
+      and_dcpl);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_dcpl);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_dcpl);
+  assign exit_FRAME_lpi_1_dfm_1_mx0 = MUX_s_1_2_2({(~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+      + 8'b10110101)))) , (exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm))},
+      FRAME_for_acc_itm[1]);
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign nl_blue_2_sva = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[39:30])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[39:30])
+      , 1'b1})))) + (b_2_sva_3[15:1])) , (readslicef_2_1_1((({(b_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + b_0_sva_3;
+  assign blue_2_sva = nl_blue_2_sva[15:0];
+  assign nl_FRAME_acc_11_psp_sva = ({1'b1 , ((FRAME_acc_28_sdt[4:1]) + 4'b1001) ,
+      (FRAME_acc_28_sdt[0])}) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (blue_2_sva[6:4]))
+      + conv_u2u_3_4(blue_2_sva[9:7])) + conv_u2u_3_5(blue_2_sva[3:1]));
+  assign FRAME_acc_11_psp_sva = nl_FRAME_acc_11_psp_sva[5:0];
+  assign nl_FRAME_acc_32_itm = ({1'b1 , (FRAME_acc_11_psp_sva[2:0]) , 1'b1}) + conv_u2u_4_5({(~
+      (FRAME_acc_11_psp_sva[5:3])) , (~ (FRAME_acc_11_psp_sva[5]))});
+  assign FRAME_acc_32_itm = nl_FRAME_acc_32_itm[4:0];
+  assign nl_red_2_sva = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[59:50])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[59:50])
+      , 1'b1})))) + (r_2_sva_3[15:1])) , (readslicef_2_1_1((({(r_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + r_0_sva_3;
+  assign red_2_sva = nl_red_2_sva[15:0];
+  assign nl_FRAME_acc_7_psp_sva = ({1'b1 , ((FRAME_acc_13_sdt[4:1]) + 4'b1001) ,
+      (FRAME_acc_13_sdt[0])}) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (red_2_sva[6:4]))
+      + conv_u2u_3_4(red_2_sva[9:7])) + conv_u2u_3_5(red_2_sva[3:1]));
+  assign FRAME_acc_7_psp_sva = nl_FRAME_acc_7_psp_sva[5:0];
+  assign nl_FRAME_acc_17_itm = ({1'b1 , (FRAME_acc_7_psp_sva[2:0]) , 1'b1}) + conv_u2u_4_5({(~
+      (FRAME_acc_7_psp_sva[5:3])) , (~ (FRAME_acc_7_psp_sva[5]))});
+  assign FRAME_acc_17_itm = nl_FRAME_acc_17_itm[4:0];
+  assign nl_FRAME_acc_28_sdt = conv_u2s_3_5(~ (blue_2_sva[12:10])) + conv_s2s_3_5(blue_2_sva[15:13]);
+  assign FRAME_acc_28_sdt = nl_FRAME_acc_28_sdt[4:0];
+  assign nl_green_2_sva = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[49:40])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[49:40])
+      , 1'b1})))) + (g_2_sva_3[15:1])) , (readslicef_2_1_1((({(g_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + g_0_sva_3;
+  assign green_2_sva = nl_green_2_sva[15:0];
+  assign nl_FRAME_acc_9_psp_sva = ({1'b1 , ((FRAME_acc_18_sdt[4:1]) + 4'b1001) ,
+      (FRAME_acc_18_sdt[0])}) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (green_2_sva[6:4]))
+      + conv_u2u_3_4(green_2_sva[9:7])) + conv_u2u_3_5(green_2_sva[3:1]));
+  assign FRAME_acc_9_psp_sva = nl_FRAME_acc_9_psp_sva[5:0];
+  assign nl_FRAME_acc_22_itm = ({1'b1 , (FRAME_acc_9_psp_sva[2:0]) , 1'b1}) + conv_u2u_4_5({(~
+      (FRAME_acc_9_psp_sva[5:3])) , (~ (FRAME_acc_9_psp_sva[5]))});
+  assign FRAME_acc_22_itm = nl_FRAME_acc_22_itm[4:0];
+  assign nl_FRAME_acc_18_sdt = conv_u2s_3_5(~ (green_2_sva[12:10])) + conv_s2s_3_5(green_2_sva[15:13]);
+  assign FRAME_acc_18_sdt = nl_FRAME_acc_18_sdt[4:0];
+  assign nl_FRAME_acc_13_sdt = conv_u2s_3_5(~ (red_2_sva[12:10])) + conv_s2s_3_5(red_2_sva[15:13]);
+  assign FRAME_acc_13_sdt = nl_FRAME_acc_13_sdt[4:0];
+  assign FRAME_for_mux_10_nl = MUX_v_16_2_2({b_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[69:60])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[69:60])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+      , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_mx0[69:60]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_b_2_sva_3 = (FRAME_for_mux_10_nl) + conv_s2s_11_16(conv_s2s_22_11(conv_s2s_10_11(regs_operator_17_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign b_2_sva_3 = nl_b_2_sva_3[15:0];
+  assign FRAME_for_mux_9_nl = MUX_v_16_2_2({b_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[9:0])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[9:0])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_11_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0]) ,
+      (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_mx0[9:0]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_b_0_sva_3 = (FRAME_for_mux_9_nl) + conv_s2s_12_16(conv_s2s_24_12(conv_s2s_10_12(regs_operator_11_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign b_0_sva_3 = nl_b_0_sva_3[15:0];
+  assign FRAME_for_mux_8_nl = MUX_v_16_2_2({g_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[79:70])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[79:70])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+      , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_mx0[79:70]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_g_2_sva_3 = (FRAME_for_mux_8_nl) + conv_s2s_11_16(conv_s2s_22_11(conv_s2s_10_11(regs_operator_16_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign g_2_sva_3 = nl_g_2_sva_3[15:0];
+  assign FRAME_for_mux_7_nl = MUX_v_16_2_2({g_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[19:10])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[19:10])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_10_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+      , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_mx0[19:10]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_g_0_sva_3 = (FRAME_for_mux_7_nl) + conv_s2s_12_16(conv_s2s_24_12(conv_s2s_10_12(regs_operator_10_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign g_0_sva_3 = nl_g_0_sva_3[15:0];
+  assign FRAME_for_mux_6_nl = MUX_v_16_2_2({r_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[89:80])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[89:80])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+      , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_mx0[89:80]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_r_2_sva_3 = (FRAME_for_mux_6_nl) + conv_s2s_11_16(conv_s2s_22_11(conv_s2s_10_11(regs_operator_15_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign r_2_sva_3 = nl_r_2_sva_3[15:0];
+  assign FRAME_for_mux_5_nl = MUX_v_16_2_2({r_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[29:20])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[29:20])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_9_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+      , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_mx0[29:20]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_r_0_sva_3 = (FRAME_for_mux_5_nl) + conv_s2s_12_16(conv_s2s_24_12(conv_s2s_10_12(regs_operator_9_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign r_0_sva_3 = nl_r_0_sva_3[15:0];
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_3_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) |
+      FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+  assign and_dcpl = ~(exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva);
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      FRAME_mul_itm_1 <= 9'b0;
+      FRAME_slc_red_10_itm_1 <= 6'b0;
+      FRAME_acc_35_itm_1 <= 5'b0;
+      FRAME_mul_1_itm_1 <= 10'b0;
+      FRAME_mul_4_itm_1 <= 9'b0;
+      FRAME_slc_blue_10_itm_1 <= 6'b0;
+      FRAME_acc_40_itm_1 <= 5'b0;
+      FRAME_mul_5_itm_1 <= 12'b0;
+      FRAME_mul_2_itm_1 <= 9'b0;
+      FRAME_slc_green_10_itm_1 <= 6'b0;
+      FRAME_acc_25_itm_1 <= 5'b0;
+      FRAME_mul_3_itm_1 <= 12'b0;
+      exit_FRAME_for_sva_1_st_1 <= 1'b0;
+      i_6_sva_1 <= 2'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_2_lpi_1_dfm <= 90'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_1 <= 1'b0;
+      b_2_sva_1 <= 16'b0;
+      b_0_sva_1 <= 16'b0;
+      g_2_sva_1 <= 16'b0;
+      g_0_sva_1 <= 16'b0;
+      r_2_sva_1 <= 16'b0;
+      r_0_sva_1 <= 16'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({(({(((conv_u2s_9_10(FRAME_mul_itm_1)
+            + conv_s2s_8_10(conv_u2s_6_8(FRAME_slc_red_10_itm_1) + conv_s2s_5_8(FRAME_acc_35_itm_1)))
+            + FRAME_mul_1_itm_1) | (signext_10_2(FRAME_acc_3_psp_sva[11:10]))) ,
+            (FRAME_acc_3_psp_sva[9:0]) , 10'b0}) | (signext_30_12(conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_4_itm_1)
+            + conv_s2s_8_10(conv_u2s_6_8(FRAME_slc_blue_10_itm_1) + conv_s2s_5_8(FRAME_acc_40_itm_1)))
+            + FRAME_mul_5_itm_1))) , vout_rsc_mgc_out_stdreg_d}, ~(exit_FRAME_for_sva_1_st_1
+            & main_stage_0_2));
+        FRAME_mul_itm_1 <= nl_FRAME_mul_itm_1[8:0];
+        FRAME_slc_red_10_itm_1 <= red_2_sva[9:4];
+        FRAME_acc_35_itm_1 <= nl_FRAME_acc_35_itm_1[4:0];
+        FRAME_mul_1_itm_1 <= nl_FRAME_mul_1_itm_1[9:0];
+        FRAME_mul_4_itm_1 <= nl_FRAME_mul_4_itm_1[8:0];
+        FRAME_slc_blue_10_itm_1 <= blue_2_sva[9:4];
+        FRAME_acc_40_itm_1 <= nl_FRAME_acc_40_itm_1[4:0];
+        FRAME_mul_5_itm_1 <= nl_FRAME_mul_5_itm_1[11:0];
+        FRAME_mul_2_itm_1 <= nl_FRAME_mul_2_itm_1[8:0];
+        FRAME_slc_green_10_itm_1 <= green_2_sva[9:4];
+        FRAME_acc_25_itm_1 <= nl_FRAME_acc_25_itm_1[4:0];
+        FRAME_mul_3_itm_1 <= nl_FRAME_mul_3_itm_1[11:0];
+        exit_FRAME_for_sva_1_st_1 <= ~ (FRAME_for_acc_itm[1]);
+        i_6_sva_1 <= i_6_sva_2;
+        exit_FRAME_1_sva <= (~ (FRAME_for_acc_itm[1])) & exit_FRAME_lpi_1_dfm_1_mx0;
+        main_stage_0_2 <= 1'b1;
+        regs_regs_2_lpi_1_dfm <= regs_regs_2_lpi_1_dfm_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_1 <= exit_FRAME_lpi_1_dfm_1_mx0;
+        b_2_sva_1 <= b_2_sva_3;
+        b_0_sva_1 <= b_0_sva_3;
+        g_2_sva_1 <= g_2_sva_3;
+        g_0_sva_1 <= g_0_sva_3;
+        r_2_sva_1 <= r_2_sva_3;
+        r_0_sva_1 <= r_0_sva_3;
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_sva_1 , FRAME_p_1_lpi_1_dfm},
+            FRAME_for_acc_itm[1]);
+      end
+    end
+  end
+  assign nl_FRAME_mul_itm_1  = conv_u2u_3_9(red_2_sva[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_35_itm_1  = (conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(~
+      (FRAME_acc_7_psp_sva[5])) , 1'b1 , (~((FRAME_acc_17_itm[4]) & (~ (red_2_sva[15]))))
+      , 1'b1}) + conv_u2u_3_5({(FRAME_acc_7_psp_sva[4:3]) , ((red_2_sva[15]) & (~
+      (FRAME_acc_17_itm[4])) & ((FRAME_acc_17_itm[3]) | (FRAME_acc_17_itm[2]) | (FRAME_acc_17_itm[1])
+      | (red_2_sva[0])))})))) + conv_u2u_3_5(~ (red_2_sva[9:7]))) + ({4'b1001 , (FRAME_acc_7_psp_sva[5])});
+  assign nl_FRAME_mul_1_itm_1  = conv_s2s_3_10(red_2_sva[15:13]) * 10'b111000111;
+  assign nl_FRAME_mul_4_itm_1  = conv_u2u_3_9(blue_2_sva[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_40_itm_1  = (conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(~
+      (FRAME_acc_11_psp_sva[5])) , 1'b1 , (~((FRAME_acc_32_itm[4]) & (~ (blue_2_sva[15]))))
+      , 1'b1}) + conv_u2u_3_5({(FRAME_acc_11_psp_sva[4:3]) , ((blue_2_sva[15]) &
+      (~ (FRAME_acc_32_itm[4])) & ((FRAME_acc_32_itm[3]) | (FRAME_acc_32_itm[2])
+      | (FRAME_acc_32_itm[1]) | (blue_2_sva[0])))})))) + conv_u2u_3_5(~ (blue_2_sva[9:7])))
+      + ({4'b1001 , (FRAME_acc_11_psp_sva[5])});
+  assign nl_FRAME_mul_5_itm_1  = conv_s2s_3_12(blue_2_sva[15:13]) * 12'b111000111;
+  assign nl_FRAME_mul_2_itm_1  = conv_u2u_3_9(green_2_sva[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_25_itm_1  = (conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(~
+      (FRAME_acc_9_psp_sva[5])) , 1'b1 , (~((FRAME_acc_22_itm[4]) & (~ (green_2_sva[15]))))
+      , 1'b1}) + conv_u2u_3_5({(FRAME_acc_9_psp_sva[4:3]) , ((green_2_sva[15]) &
+      (~ (FRAME_acc_22_itm[4])) & ((FRAME_acc_22_itm[3]) | (FRAME_acc_22_itm[2])
+      | (FRAME_acc_22_itm[1]) | (green_2_sva[0])))})))) + conv_u2u_3_5(~ (green_2_sva[9:7])))
+      + ({4'b1001 , (FRAME_acc_9_psp_sva[5])});
+  assign nl_FRAME_mul_3_itm_1  = conv_s2s_3_12(green_2_sva[15:13]) * 12'b111000111;
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_2_1_1;
+    input [1:0] vector;
+    reg [1:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_2_1_1 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [15:0] signext_16_11;
+    input [10:0] vector;
+  begin
+    signext_16_11= {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [9:0] signext_10_2;
+    input [1:0] vector;
+  begin
+    signext_10_2= {{8{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [29:0] signext_30_12;
+    input [11:0] vector;
+  begin
+    signext_30_12= {{18{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_11_15 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_15 = {{4{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2s_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2s_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_3_10 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_10 = {{7{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_3_12 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_12 = {{9{vector[2]}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v4/cycle.rpt b/Sobel/sobel.v4/cycle.rpt
new file mode 100644
index 0000000..9512494
--- /dev/null
+++ b/Sobel/sobel.v4/cycle.rpt
@@ -0,0 +1,85 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 14:22:16 +0000 2016                      
+
+Solution Settings: sobel.v4
+  Current state: schedule
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       161  921601     921600            0  1          
+    Design Total:                     161  921601     921600            0  0          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /sobel/core              
+    
+  I/O Data Ranges
+    Port       Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ---------- ---- -------- --------- --------- ------- -------- --------
+    vin:rsc.z  IN   Unsigned        90                                     
+    clk        IN   Unsigned         1                                     
+    en         IN   Unsigned         1                                     
+    arst_n     IN   Unsigned         1                                     
+    vout:rsc.z OUT  Unsigned        30                                     
+    
+  Memory Resources
+    Resource Name: /sobel/vin:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 90
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable   Indices Phys Memory Address     
+      ---------- ------- -----------------------
+      /sobel/vin    0:89 00000000-00000000 (0-0) 
+      
+    Resource Name: /sobel/vout:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 30
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable    Indices Phys Memory Address     
+      ----------- ------- -----------------------
+      /sobel/vout    0:29 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process     Loop             Iterations C-Steps Total Cycles  Duration  Unroll Init Comments 
+    ----------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
+    /sobel/core core:rlp           Infinite       0       921602  18.43 ms                       
+    /sobel/core   main             Infinite       3       921602  18.43 ms            1          
+    
+  Loop Execution Profile
+    Process     Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------- ---------------- ------------ -------------------------- ----------------- --------
+    /sobel/core core:rlp                   0                        0.00           921600           
+    /sobel/core   main                921602                      100.00           921600           
+    
+  End of Report
diff --git a/Sobel/sobel.v4/cycle.v b/Sobel/sobel.v4/cycle.v
new file mode 100644
index 0000000..dab5328
--- /dev/null
+++ b/Sobel/sobel.v4/cycle.v
@@ -0,0 +1,813 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:22:16 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg [18:0] FRAME_p_1_lpi_1;
+    reg [89:0] regs_regs_1_sva;
+    reg [89:0] regs_regs_0_sva;
+    reg exit_FRAME_1_sva;
+    reg [18:0] FRAME_p_1_lpi_1_dfm;
+    reg exit_FRAME_for_lpi_1_dfm;
+    reg [89:0] regs_regs_0_sva_1;
+    reg [89:0] regs_regs_0_sva_dfm;
+    reg [89:0] regs_regs_1_sva_dfm;
+    reg [89:0] regs_regs_2_lpi_1_dfm;
+    reg [1:0] i_6_lpi_1_dfm;
+    reg FRAME_for_slc_YMATRIX_rom_11_psp_sva;
+    reg [15:0] r_0_sva_1;
+    reg [15:0] g_0_sva_1;
+    reg [15:0] b_0_sva_1;
+    reg [15:0] r_2_sva_1;
+    reg [15:0] g_2_sva_1;
+    reg [15:0] b_2_sva_1;
+    reg [1:0] i_6_sva_1;
+    reg exit_FRAME_for_sva_1;
+    reg [15:0] red_2_sva;
+    reg [15:0] green_2_sva;
+    reg [15:0] blue_2_sva;
+    reg [5:0] FRAME_acc_7_psp_sva;
+    reg [3:0] FRAME_acc_8_psp_sva;
+    reg [5:0] FRAME_acc_9_psp_sva;
+    reg [3:0] FRAME_acc_10_psp_sva;
+    reg [11:0] FRAME_acc_3_psp_sva;
+    reg [5:0] FRAME_acc_11_psp_sva;
+    reg [3:0] FRAME_acc_12_psp_sva;
+    reg [18:0] FRAME_p_1_sva_1;
+    reg exit_FRAME_lpi_1_dfm_1;
+    reg exit_FRAME_for_lpi_1_dfm_2;
+    reg [8:0] FRAME_mul_2_itm;
+    reg [8:0] FRAME_mul_2_itm_1;
+    reg [5:0] FRAME_slc_green_10_itm;
+    reg [5:0] FRAME_slc_green_10_itm_1;
+    reg [4:0] FRAME_acc_25_itm;
+    reg [4:0] FRAME_acc_25_itm_1;
+    reg [11:0] FRAME_mul_3_itm;
+    reg [11:0] FRAME_mul_3_itm_1;
+    reg [8:0] FRAME_mul_itm;
+    reg [8:0] FRAME_mul_itm_1;
+    reg [5:0] FRAME_slc_red_10_itm;
+    reg [5:0] FRAME_slc_red_10_itm_1;
+    reg [4:0] FRAME_acc_35_itm;
+    reg [4:0] FRAME_acc_35_itm_1;
+    reg [9:0] FRAME_mul_1_itm;
+    reg [9:0] FRAME_mul_1_itm_1;
+    reg [8:0] FRAME_mul_4_itm;
+    reg [8:0] FRAME_mul_4_itm_1;
+    reg [5:0] FRAME_slc_blue_10_itm;
+    reg [5:0] FRAME_slc_blue_10_itm_1;
+    reg [4:0] FRAME_acc_40_itm;
+    reg [4:0] FRAME_acc_40_itm_1;
+    reg [11:0] FRAME_mul_5_itm;
+    reg [11:0] FRAME_mul_5_itm_1;
+    reg exit_FRAME_for_sva_1_st_1;
+    reg main_stage_0_2;
+    reg [10:0] r_0_sva_2;
+    reg [10:0] g_0_sva_2;
+    reg [10:0] b_0_sva_2;
+    reg [10:0] r_2_sva_2;
+    reg [10:0] g_2_sva_2;
+    reg [10:0] b_2_sva_2;
+    reg [4:0] FRAME_acc_13_sdt;
+    reg [4:0] FRAME_acc_18_sdt;
+    reg [4:0] FRAME_acc_28_sdt;
+    reg FRAME_for_nor_cse;
+    reg FRAME_for_slc_XMATRIX_rom_11_psp_sva_1;
+
+    reg[15:0] FRAME_for_mux_5_nl;
+    reg[9:0] regs_operator_9_mux_nl;
+    reg[15:0] FRAME_for_mux_7_nl;
+    reg[9:0] regs_operator_10_mux_nl;
+    reg[15:0] FRAME_for_mux_9_nl;
+    reg[9:0] regs_operator_11_mux_nl;
+    reg[15:0] FRAME_for_mux_6_nl;
+    reg[9:0] regs_operator_15_mux_nl;
+    reg[15:0] FRAME_for_mux_8_nl;
+    reg[9:0] regs_operator_16_mux_nl;
+    reg[15:0] FRAME_for_mux_10_nl;
+    reg[9:0] regs_operator_17_mux_nl;
+    begin : core_rlpExit
+      forever begin : core_rlp
+        // C-Step 0 of Loop 'core_rlp'
+        FRAME_p_1_lpi_1 = 19'b0;
+        regs_regs_1_sva = 90'b0;
+        regs_regs_0_sva = 90'b0;
+        exit_FRAME_1_sva = 1'b1;
+        main_stage_0_2 = 1'b0;
+        begin : mainExit
+          forever begin : main
+            // C-Step 0 of Loop 'main'
+            begin : waitLoop0Exit
+              forever begin : waitLoop0
+                @(posedge clk or negedge ( arst_n ));
+                if ( ~ arst_n )
+                  disable core_rlpExit;
+                if ( en )
+                  disable waitLoop0Exit;
+              end
+            end
+            // C-Step 1 of Loop 'main'
+            if ( main_stage_0_2 ) begin
+              if ( exit_FRAME_for_sva_1_st_1 ) begin
+                FRAME_acc_3_psp_sva = conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_2_itm_1)
+                    + conv_s2s_8_10(conv_u2s_6_8(FRAME_slc_green_10_itm_1) + conv_s2s_5_8(FRAME_acc_25_itm_1)))
+                    + FRAME_mul_3_itm_1;
+                vout_rsc_mgc_out_stdreg_d <= ({(((conv_u2s_9_10(FRAME_mul_itm_1)
+                    + conv_s2s_8_10(conv_u2s_6_8(FRAME_slc_red_10_itm_1) + conv_s2s_5_8(FRAME_acc_35_itm_1)))
+                    + FRAME_mul_1_itm_1) | (signext_10_2(FRAME_acc_3_psp_sva[11:10])))
+                    , (FRAME_acc_3_psp_sva[9:0]) , 10'b0}) | (signext_30_12(conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_4_itm_1)
+                    + conv_s2s_8_10(conv_u2s_6_8(FRAME_slc_blue_10_itm_1) + conv_s2s_5_8(FRAME_acc_40_itm_1)))
+                    + FRAME_mul_5_itm_1));
+              end
+            end
+            FRAME_p_1_sva_1 = 19'b0;
+            b_2_sva_2 = 11'b0;
+            g_2_sva_2 = 11'b0;
+            r_2_sva_2 = 11'b0;
+            b_0_sva_2 = 11'b0;
+            g_0_sva_2 = 11'b0;
+            r_0_sva_2 = 11'b0;
+            FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+            exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_lpi_1_dfm_2 | exit_FRAME_1_sva;
+            if ( exit_FRAME_for_lpi_1_dfm ) begin
+              regs_regs_0_sva_1 = vin_rsc_mgc_in_wire_d;
+              r_0_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[29:20]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[29:20]) , 1'b1})));
+              g_0_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[19:10]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[19:10]) , 1'b1})));
+              b_0_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[9:0]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[9:0]) , 1'b1})));
+              r_2_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[89:80]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[89:80]) , 1'b1})));
+              g_2_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[79:70]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[79:70]) , 1'b1})));
+              b_2_sva_2 = readslicef_12_11_1((conv_s2s_11_12({(~ (regs_regs_0_sva_1[69:60]))
+                  , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[69:60]) , 1'b1})));
+              regs_regs_0_sva_dfm = regs_regs_0_sva_1;
+              regs_regs_1_sva_dfm = regs_regs_0_sva;
+              regs_regs_2_lpi_1_dfm = regs_regs_1_sva;
+            end
+            else begin
+              regs_regs_0_sva_dfm = regs_regs_0_sva;
+              regs_regs_1_sva_dfm = regs_regs_1_sva;
+            end
+            i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm));
+            FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+            FRAME_for_slc_YMATRIX_rom_11_psp_sva = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1]))))
+                | FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+            FRAME_for_mux_5_nl = MUX_v_16_2_2({r_0_sva_1 , ({{5{r_0_sva_2[10]}},
+                r_0_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_9_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[29:20]) ,
+                (regs_regs_1_sva_dfm[29:20]) , (regs_regs_2_lpi_1_dfm[29:20]) , 10'b0},
+                i_6_lpi_1_dfm);
+            r_0_sva_1 = (FRAME_for_mux_5_nl) + conv_s2s_12_16(conv_s2s_24_12(conv_s2s_10_12(regs_operator_9_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva})));
+            FRAME_for_mux_7_nl = MUX_v_16_2_2({g_0_sva_1 , ({{5{g_0_sva_2[10]}},
+                g_0_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_10_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[19:10])
+                , (regs_regs_1_sva_dfm[19:10]) , (regs_regs_2_lpi_1_dfm[19:10]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            g_0_sva_1 = (FRAME_for_mux_7_nl) + conv_s2s_12_16(conv_s2s_24_12(conv_s2s_10_12(regs_operator_10_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva})));
+            FRAME_for_mux_9_nl = MUX_v_16_2_2({b_0_sva_1 , ({{5{b_0_sva_2[10]}},
+                b_0_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_11_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[9:0]) ,
+                (regs_regs_1_sva_dfm[9:0]) , (regs_regs_2_lpi_1_dfm[9:0]) , 10'b0},
+                i_6_lpi_1_dfm);
+            b_0_sva_1 = (FRAME_for_mux_9_nl) + conv_s2s_12_16(conv_s2s_24_12(conv_s2s_10_12(regs_operator_11_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva})));
+            FRAME_for_slc_XMATRIX_rom_11_psp_sva_1 = (~((~ (i_6_lpi_1_dfm[1])) &
+                (i_6_lpi_1_dfm[0]))) | FRAME_for_nor_cse;
+            FRAME_for_mux_6_nl = MUX_v_16_2_2({r_2_sva_1 , ({{5{r_2_sva_2[10]}},
+                r_2_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[89:80])
+                , (regs_regs_1_sva_dfm[89:80]) , (regs_regs_2_lpi_1_dfm[89:80]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            r_2_sva_1 = (FRAME_for_mux_6_nl) + conv_s2s_11_16(conv_s2s_22_11(conv_s2s_10_11(regs_operator_15_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+            FRAME_for_mux_8_nl = MUX_v_16_2_2({g_2_sva_1 , ({{5{g_2_sva_2[10]}},
+                g_2_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[79:70])
+                , (regs_regs_1_sva_dfm[79:70]) , (regs_regs_2_lpi_1_dfm[79:70]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            g_2_sva_1 = (FRAME_for_mux_8_nl) + conv_s2s_11_16(conv_s2s_22_11(conv_s2s_10_11(regs_operator_16_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+            FRAME_for_mux_10_nl = MUX_v_16_2_2({b_2_sva_1 , ({{5{b_2_sva_2[10]}},
+                b_2_sva_2})}, exit_FRAME_for_lpi_1_dfm);
+            regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[69:60])
+                , (regs_regs_1_sva_dfm[69:60]) , (regs_regs_2_lpi_1_dfm[69:60]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            b_2_sva_1 = (FRAME_for_mux_10_nl) + conv_s2s_11_16(conv_s2s_22_11(conv_s2s_10_11(regs_operator_17_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+            i_6_sva_1 = i_6_lpi_1_dfm + 2'b1;
+            exit_FRAME_for_sva_1 = ~ (readslicef_3_1_2((({1'b1 , i_6_sva_1}) + 3'b1)));
+            if ( exit_FRAME_for_sva_1 ) begin
+              red_2_sva = ({(conv_s2u_10_15(~ (regs_regs_0_sva_dfm[59:50])) + conv_s2u_10_15(regs_regs_2_lpi_1_dfm[59:50])
+                  + (r_2_sva_1[15:1]) + 15'b1) , (readslicef_2_1_1((({(r_2_sva_1[0])
+                  , 1'b1}) + 2'b11)))}) + r_0_sva_1;
+              green_2_sva = ({(conv_s2u_10_15(~ (regs_regs_0_sva_dfm[49:40])) + conv_s2u_10_15(regs_regs_2_lpi_1_dfm[49:40])
+                  + (g_2_sva_1[15:1]) + 15'b1) , (readslicef_2_1_1((({(g_2_sva_1[0])
+                  , 1'b1}) + 2'b11)))}) + g_0_sva_1;
+              blue_2_sva = ({(conv_s2u_10_15(~ (regs_regs_0_sva_dfm[39:30])) + conv_s2u_10_15(regs_regs_2_lpi_1_dfm[39:30])
+                  + (b_2_sva_1[15:1]) + 15'b1) , (readslicef_2_1_1((({(b_2_sva_1[0])
+                  , 1'b1}) + 2'b11)))}) + b_0_sva_1;
+              FRAME_acc_13_sdt = conv_u2s_3_5(~ (red_2_sva[12:10])) + conv_s2s_3_5(red_2_sva[15:13]);
+              FRAME_acc_7_psp_sva = ({(conv_s2u_4_5(FRAME_acc_13_sdt[4:1]) + 5'b11001)
+                  , (FRAME_acc_13_sdt[0])}) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(~
+                  (red_2_sva[6:4])) + conv_u2u_3_4(red_2_sva[9:7])) + conv_u2u_3_5(red_2_sva[3:1]));
+              FRAME_acc_8_psp_sva = readslicef_5_4_1((({1'b1 , (FRAME_acc_7_psp_sva[2:0])
+                  , 1'b1}) + conv_u2u_4_5({(~ (FRAME_acc_7_psp_sva[5:3])) , (~ (FRAME_acc_7_psp_sva[5]))})));
+              FRAME_acc_18_sdt = conv_u2s_3_5(~ (green_2_sva[12:10])) + conv_s2s_3_5(green_2_sva[15:13]);
+              FRAME_acc_9_psp_sva = ({(conv_s2u_4_5(FRAME_acc_18_sdt[4:1]) + 5'b11001)
+                  , (FRAME_acc_18_sdt[0])}) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(~
+                  (green_2_sva[6:4])) + conv_u2u_3_4(green_2_sva[9:7])) + conv_u2u_3_5(green_2_sva[3:1]));
+              FRAME_acc_10_psp_sva = readslicef_5_4_1((({1'b1 , (FRAME_acc_9_psp_sva[2:0])
+                  , 1'b1}) + conv_u2u_4_5({(~ (FRAME_acc_9_psp_sva[5:3])) , (~ (FRAME_acc_9_psp_sva[5]))})));
+              FRAME_mul_2_itm = conv_u2u_18_9(conv_u2u_3_9(green_2_sva[12:10]) *
+                  9'b111001);
+              FRAME_slc_green_10_itm = green_2_sva[9:4];
+              FRAME_acc_25_itm = (conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(~
+                  (FRAME_acc_9_psp_sva[5])) , 1'b1 , (~((FRAME_acc_10_psp_sva[3])
+                  & (~ (green_2_sva[15])))) , 1'b1}) + conv_u2u_3_5({(FRAME_acc_9_psp_sva[4:3])
+                  , ((green_2_sva[15]) & (~ (FRAME_acc_10_psp_sva[3])) & ((FRAME_acc_10_psp_sva[2])
+                  | (FRAME_acc_10_psp_sva[1]) | (FRAME_acc_10_psp_sva[0]) | (green_2_sva[0])))}))))
+                  + conv_u2u_3_5(~ (green_2_sva[9:7]))) + ({4'b1001 , (FRAME_acc_9_psp_sva[5])});
+              FRAME_mul_3_itm = conv_u2u_24_12(conv_s2s_3_12(green_2_sva[15:13])
+                  * 12'b111000111);
+              FRAME_acc_28_sdt = conv_u2s_3_5(~ (blue_2_sva[12:10])) + conv_s2s_3_5(blue_2_sva[15:13]);
+              FRAME_acc_11_psp_sva = ({(conv_s2u_4_5(FRAME_acc_28_sdt[4:1]) + 5'b11001)
+                  , (FRAME_acc_28_sdt[0])}) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(~
+                  (blue_2_sva[6:4])) + conv_u2u_3_4(blue_2_sva[9:7])) + conv_u2u_3_5(blue_2_sva[3:1]));
+              FRAME_acc_12_psp_sva = readslicef_5_4_1((({1'b1 , (FRAME_acc_11_psp_sva[2:0])
+                  , 1'b1}) + conv_u2u_4_5({(~ (FRAME_acc_11_psp_sva[5:3])) , (~ (FRAME_acc_11_psp_sva[5]))})));
+              FRAME_mul_itm = conv_u2u_18_9(conv_u2u_3_9(red_2_sva[12:10]) * 9'b111001);
+              FRAME_slc_red_10_itm = red_2_sva[9:4];
+              FRAME_acc_35_itm = (conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(~
+                  (FRAME_acc_7_psp_sva[5])) , 1'b1 , (~((FRAME_acc_8_psp_sva[3])
+                  & (~ (red_2_sva[15])))) , 1'b1}) + conv_u2u_3_5({(FRAME_acc_7_psp_sva[4:3])
+                  , ((red_2_sva[15]) & (~ (FRAME_acc_8_psp_sva[3])) & ((FRAME_acc_8_psp_sva[2])
+                  | (FRAME_acc_8_psp_sva[1]) | (FRAME_acc_8_psp_sva[0]) | (red_2_sva[0])))}))))
+                  + conv_u2u_3_5(~ (red_2_sva[9:7]))) + ({4'b1001 , (FRAME_acc_7_psp_sva[5])});
+              FRAME_mul_1_itm = conv_u2u_20_10(conv_s2s_3_10(red_2_sva[15:13]) *
+                  10'b111000111);
+              FRAME_mul_4_itm = conv_u2u_18_9(conv_u2u_3_9(blue_2_sva[12:10]) * 9'b111001);
+              FRAME_slc_blue_10_itm = blue_2_sva[9:4];
+              FRAME_acc_40_itm = (conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(~
+                  (FRAME_acc_11_psp_sva[5])) , 1'b1 , (~((FRAME_acc_12_psp_sva[3])
+                  & (~ (blue_2_sva[15])))) , 1'b1}) + conv_u2u_3_5({(FRAME_acc_11_psp_sva[4:3])
+                  , ((blue_2_sva[15]) & (~ (FRAME_acc_12_psp_sva[3])) & ((FRAME_acc_12_psp_sva[2])
+                  | (FRAME_acc_12_psp_sva[1]) | (FRAME_acc_12_psp_sva[0]) | (blue_2_sva[0])))}))))
+                  + conv_u2u_3_5(~ (blue_2_sva[9:7]))) + ({4'b1001 , (FRAME_acc_11_psp_sva[5])});
+              FRAME_mul_5_itm = conv_u2u_24_12(conv_s2s_3_12(blue_2_sva[15:13]) *
+                  12'b111000111);
+              FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+              exit_FRAME_lpi_1_dfm_1 = ~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+                  + 8'b10110101)));
+            end
+            else begin
+              exit_FRAME_lpi_1_dfm_1 = exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm);
+            end
+            exit_FRAME_for_lpi_1_dfm_2 = exit_FRAME_for_sva_1;
+            regs_regs_0_sva = regs_regs_0_sva_dfm;
+            regs_regs_1_sva = regs_regs_1_sva_dfm;
+            FRAME_p_1_lpi_1 = MUX_v_19_2_2({FRAME_p_1_lpi_1_dfm , FRAME_p_1_sva_1},
+                exit_FRAME_for_sva_1);
+            exit_FRAME_1_sva = exit_FRAME_for_sva_1 & exit_FRAME_lpi_1_dfm_1;
+            FRAME_mul_2_itm_1 = FRAME_mul_2_itm;
+            FRAME_slc_green_10_itm_1 = FRAME_slc_green_10_itm;
+            FRAME_acc_25_itm_1 = FRAME_acc_25_itm;
+            FRAME_mul_3_itm_1 = FRAME_mul_3_itm;
+            FRAME_mul_itm_1 = FRAME_mul_itm;
+            FRAME_slc_red_10_itm_1 = FRAME_slc_red_10_itm;
+            FRAME_acc_35_itm_1 = FRAME_acc_35_itm;
+            FRAME_mul_1_itm_1 = FRAME_mul_1_itm;
+            FRAME_mul_4_itm_1 = FRAME_mul_4_itm;
+            FRAME_slc_blue_10_itm_1 = FRAME_slc_blue_10_itm;
+            FRAME_acc_40_itm_1 = FRAME_acc_40_itm;
+            FRAME_mul_5_itm_1 = FRAME_mul_5_itm;
+            exit_FRAME_for_sva_1_st_1 = exit_FRAME_for_sva_1;
+            main_stage_0_2 = 1'b1;
+          end
+        end
+      end
+    end
+    FRAME_for_slc_XMATRIX_rom_11_psp_sva_1 = 1'b0;
+    FRAME_for_nor_cse = 1'b0;
+    FRAME_acc_28_sdt = 5'b0;
+    FRAME_acc_18_sdt = 5'b0;
+    FRAME_acc_13_sdt = 5'b0;
+    b_2_sva_2 = 11'b0;
+    g_2_sva_2 = 11'b0;
+    r_2_sva_2 = 11'b0;
+    b_0_sva_2 = 11'b0;
+    g_0_sva_2 = 11'b0;
+    r_0_sva_2 = 11'b0;
+    main_stage_0_2 = 1'b0;
+    exit_FRAME_for_sva_1_st_1 = 1'b0;
+    FRAME_mul_5_itm_1 = 12'b0;
+    FRAME_mul_5_itm = 12'b0;
+    FRAME_acc_40_itm_1 = 5'b0;
+    FRAME_acc_40_itm = 5'b0;
+    FRAME_slc_blue_10_itm_1 = 6'b0;
+    FRAME_slc_blue_10_itm = 6'b0;
+    FRAME_mul_4_itm_1 = 9'b0;
+    FRAME_mul_4_itm = 9'b0;
+    FRAME_mul_1_itm_1 = 10'b0;
+    FRAME_mul_1_itm = 10'b0;
+    FRAME_acc_35_itm_1 = 5'b0;
+    FRAME_acc_35_itm = 5'b0;
+    FRAME_slc_red_10_itm_1 = 6'b0;
+    FRAME_slc_red_10_itm = 6'b0;
+    FRAME_mul_itm_1 = 9'b0;
+    FRAME_mul_itm = 9'b0;
+    FRAME_mul_3_itm_1 = 12'b0;
+    FRAME_mul_3_itm = 12'b0;
+    FRAME_acc_25_itm_1 = 5'b0;
+    FRAME_acc_25_itm = 5'b0;
+    FRAME_slc_green_10_itm_1 = 6'b0;
+    FRAME_slc_green_10_itm = 6'b0;
+    FRAME_mul_2_itm_1 = 9'b0;
+    FRAME_mul_2_itm = 9'b0;
+    exit_FRAME_for_lpi_1_dfm_2 = 1'b0;
+    exit_FRAME_lpi_1_dfm_1 = 1'b0;
+    FRAME_p_1_sva_1 = 19'b0;
+    FRAME_acc_12_psp_sva = 4'b0;
+    FRAME_acc_11_psp_sva = 6'b0;
+    FRAME_acc_3_psp_sva = 12'b0;
+    FRAME_acc_10_psp_sva = 4'b0;
+    FRAME_acc_9_psp_sva = 6'b0;
+    FRAME_acc_8_psp_sva = 4'b0;
+    FRAME_acc_7_psp_sva = 6'b0;
+    blue_2_sva = 16'b0;
+    green_2_sva = 16'b0;
+    red_2_sva = 16'b0;
+    exit_FRAME_for_sva_1 = 1'b0;
+    i_6_sva_1 = 2'b0;
+    b_2_sva_1 = 16'b0;
+    g_2_sva_1 = 16'b0;
+    r_2_sva_1 = 16'b0;
+    b_0_sva_1 = 16'b0;
+    g_0_sva_1 = 16'b0;
+    r_0_sva_1 = 16'b0;
+    FRAME_for_slc_YMATRIX_rom_11_psp_sva = 1'b0;
+    i_6_lpi_1_dfm = 2'b0;
+    regs_regs_2_lpi_1_dfm = 90'b0;
+    regs_regs_1_sva_dfm = 90'b0;
+    regs_regs_0_sva_dfm = 90'b0;
+    regs_regs_0_sva_1 = 90'b0;
+    exit_FRAME_for_lpi_1_dfm = 1'b0;
+    FRAME_p_1_lpi_1_dfm = 19'b0;
+    exit_FRAME_1_sva = 1'b0;
+    regs_regs_0_sva = 90'b0;
+    regs_regs_1_sva = 90'b0;
+    FRAME_p_1_lpi_1 = 19'b0;
+    vout_rsc_mgc_out_stdreg_d <= 30'b0;
+  end
+
+
+  function [9:0] signext_10_2;
+    input [1:0] vector;
+  begin
+    signext_10_2= {{8{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [29:0] signext_30_12;
+    input [11:0] vector;
+  begin
+    signext_30_12= {{18{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_3_1_2;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 2;
+    readslicef_3_1_2 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_2_1_1;
+    input [1:0] vector;
+    reg [1:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_2_1_1 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2s_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2s_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_10_15 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_15 = {{5{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_s2u_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2u_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_24_12 ;
+    input [23:0]  vector ;
+  begin
+    conv_u2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_3_12 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_12 = {{9{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_3_10 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_10 = {{7{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v4/cycle_mgc_ioport.v b/Sobel/sobel.v4/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v4/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v4/cycle_mgc_ioport_v2001.v b/Sobel/sobel.v4/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v4/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v4/cycle_set.tcl b/Sobel/sobel.v4/cycle_set.tcl
new file mode 100644
index 0000000..4b4b209
--- /dev/null
+++ b/Sobel/sobel.v4/cycle_set.tcl
@@ -0,0 +1,107 @@
+
+# Loop constraints
+directive set /sobel/core/core:rlp CSTEPS_FROM {{. == 0}}
+directive set /sobel/core/core:rlp/main CSTEPS_FROM {{. == 3} {.. == 0}}
+
+# IO operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:io_read(vin:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:io_write(vout:rsc.d) CSTEPS_FROM {{.. == 2}}
+
+# Real operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:for:and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#45 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#46 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#47 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#48 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#49 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#5 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#9:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#7 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#10:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#9 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#11:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:or#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#6 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#15:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#8 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#16:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#12 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#10 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#17:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#50 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#51 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2-3:acc#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#52 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#53 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2-3:acc#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#54 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#55 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2-3:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#13 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#15 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#17 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#18 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#21 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#19 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#20 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#9 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#22 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#23 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#24 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#26 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#27 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#28 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#31 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#29 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#30 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#11 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#32 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#33 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#34 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#35 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#36 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#37 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#2 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or#4 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#38 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#39 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#40 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#41 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#42 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#4 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#26 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#21 CSTEPS_FROM {{.. == 1}}
diff --git a/Sobel/sobel.v4/directives.tcl b/Sobel/sobel.v4/directives.tcl
new file mode 100644
index 0000000..504c4bb
--- /dev/null
+++ b/Sobel/sobel.v4/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
+go extract
diff --git a/Sobel/sobel.v4/messages.txt b/Sobel/sobel.v4/messages.txt
new file mode 100644
index 0000000..c631cca
--- /dev/null
+++ b/Sobel/sobel.v4/messages.txt
@@ -0,0 +1,248 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v2': elapsed time 2.75 seconds, memory usage 211704kB, peak memory usage 327424kB (SOL-9)
+$PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.cpp(146): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+
+# Messages from "go compile"
+
+Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'sobel' specified by directive (CIN-52)
+Synthesizing routine 'sobel' (CIN-13)
+Inlining routine 'sobel' (CIN-14)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Optimizing block '/sobel' ... (CIN-4)
+Inout port 'vin' is only used as an input. (OPT-10)
+Inout port 'vout' is only used as an output. (OPT-11)
+Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+Design 'sobel' was read (SOL-1)
+Optimizing partition '/sobel': (Total ops = 531, Real ops = 128, Vars = 107) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 531, Real ops = 128, Vars = 105) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 491, Real ops = 120, Vars = 111) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 491, Real ops = 120, Vars = 113) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 491, Real ops = 120, Vars = 113) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 491, Real ops = 120, Vars = 111) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 421, Real ops = 119, Vars = 94) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 396, Real ops = 119, Vars = 93) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 396, Real ops = 119, Vars = 93) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 396, Real ops = 119, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 396, Real ops = 119, Vars = 95) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 376, Real ops = 117, Vars = 137) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 350, Real ops = 111, Vars = 27) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 350, Real ops = 111, Vars = 29) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 350, Real ops = 111, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 350, Real ops = 111, Vars = 27) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 350, Real ops = 111, Vars = 29) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 350, Real ops = 111, Vars = 27) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 350, Real ops = 111, Vars = 29) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 350, Real ops = 111, Vars = 29) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 350, Real ops = 111, Vars = 27) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 390, Real ops = 110, Vars = 26) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 301, Real ops = 100, Vars = 25) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 301, Real ops = 100, Vars = 27) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 296, Real ops = 100, Vars = 30) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 293, Real ops = 100, Vars = 25) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 293, Real ops = 100, Vars = 27) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 293, Real ops = 100, Vars = 25) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 293, Real ops = 100, Vars = 27) (SOL-10)
+Completed transformation 'compile' on solution 'sobel.v4': elapsed time 2.40 seconds, memory usage 207912kB, peak memory usage 327424kB (SOL-9)
+Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'sobel.v4' (SOL-8)
+Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+Loop '/sobel/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/sobel/core': (Total ops = 482, Real ops = 163, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 292, Real ops = 100, Vars = 19) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 289, Real ops = 100, Vars = 18) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 289, Real ops = 100, Vars = 18) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 100, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 100, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 280, Real ops = 97, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 280, Real ops = 97, Vars = 26) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 280, Real ops = 97, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 280, Real ops = 97, Vars = 26) (SOL-10)
+I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+Optimizing partition '/sobel': (Total ops = 280, Real ops = 97, Vars = 26) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 280, Real ops = 97, Vars = 21) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 280, Real ops = 97, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 280, Real ops = 97, Vars = 26) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 262, Real ops = 97, Vars = 34) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 262, Real ops = 97, Vars = 35) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 222, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 222, Real ops = 94, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 222, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 222, Real ops = 94, Vars = 28) (SOL-10)
+Design 'sobel' contains '156' real operations. (SOL-11)
+Optimizing partition '/sobel/core': (Total ops = 229, Real ops = 95, Vars = 26) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 228, Real ops = 95, Vars = 26) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 496, Real ops = 128, Vars = 183) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 272, Real ops = 112, Vars = 52) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 271, Real ops = 112, Vars = 51) (SOL-10)
+Completed transformation 'architect' on solution 'sobel.v4': elapsed time 4.82 seconds, memory usage 208208kB, peak memory usage 327424kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'sobel.v4' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 5135.97, 0.00, 5135.97 (CRAAS-11)
+Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5134.54, 0.00, 5134.54 (CRAAS-10)
+Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5106.69, 0.00, 5106.69 (CRAAS-10)
+Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5100.36, 0.00, 5100.36 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 5100.36, 0.00, 5100.36 (CRAAS-12)
+Completed transformation 'allocate' on solution 'sobel.v4': elapsed time 0.69 seconds, memory usage 208316kB, peak memory usage 327424kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'sobel.v4' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 430, Real ops = 157, Vars = 104) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 420, Real ops = 156, Vars = 96) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 400, Real ops = 156, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 366, Real ops = 151, Vars = 71) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 359, Real ops = 150, Vars = 70) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 373, Real ops = 150, Vars = 82) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 364, Real ops = 150, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 361, Real ops = 150, Vars = 72) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 360, Real ops = 150, Vars = 70) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 374, Real ops = 150, Vars = 82) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 365, Real ops = 150, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 360, Real ops = 150, Vars = 70) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 374, Real ops = 150, Vars = 82) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 365, Real ops = 150, Vars = 75) (SOL-10)
+Completed transformation 'schedule' on solution 'sobel.v4': elapsed time 1.89 seconds, memory usage 212032kB, peak memory usage 327424kB (SOL-9)
+Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'sobel.v4' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 646, Real ops = 183, Vars = 414) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 637, Real ops = 183, Vars = 407) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 577, Real ops = 173, Vars = 72) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 568, Real ops = 173, Vars = 65) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 345, Real ops = 173, Vars = 72) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 336, Real ops = 173, Vars = 65) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 345, Real ops = 173, Vars = 72) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 336, Real ops = 173, Vars = 65) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 336, Real ops = 173, Vars = 65) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 345, Real ops = 173, Vars = 72) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 345, Real ops = 173, Vars = 72) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 336, Real ops = 173, Vars = 65) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 345, Real ops = 173, Vars = 72) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 336, Real ops = 173, Vars = 65) (SOL-10)
+Completed transformation 'dpfsm' on solution 'sobel.v4': elapsed time 0.41 seconds, memory usage 212168kB, peak memory usage 327424kB (SOL-9)
+
+# Messages from "go extract"
+
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'sobel.v4' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 442, Real ops = 200, Vars = 439) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 433, Real ops = 200, Vars = 432) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 329, Real ops = 164, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 320, Real ops = 164, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 329, Real ops = 164, Vars = 72) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 320, Real ops = 164, Vars = 65) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 320, Real ops = 164, Vars = 65) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 329, Real ops = 164, Vars = 72) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 329, Real ops = 164, Vars = 72) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 320, Real ops = 164, Vars = 65) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 329, Real ops = 164, Vars = 72) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 320, Real ops = 164, Vars = 65) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 414, Real ops = 188, Vars = 411) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 405, Real ops = 188, Vars = 404) (SOL-10)
+Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+Reassigned operation ACC1:acc#67:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+Reassigned operation ACC1:acc#59:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+Reassigned operation ACC1:acc#63:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+Reassigned operation ACC1:acc#66:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+Reassigned operation ACC1:acc#58:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+Reassigned operation ACC1:acc#62:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+Reassigned operation FRAME:acc#45:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5) (ASG-1)
+Reassigned operation FRAME:acc#43:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5) (ASG-1)
+Reassigned operation FRAME:acc#44:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5) (ASG-1)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/sobel': (Total ops = 414, Real ops = 188, Vars = 411) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 405, Real ops = 188, Vars = 404) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 324, Real ops = 164, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 315, Real ops = 164, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 324, Real ops = 164, Vars = 72) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 315, Real ops = 164, Vars = 65) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 324, Real ops = 164, Vars = 72) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 315, Real ops = 164, Vars = 65) (SOL-10)
+Completed transformation 'extract' on solution 'sobel.v4': elapsed time 5.65 seconds, memory usage 212732kB, peak memory usage 327424kB (SOL-9)
diff --git a/Sobel/sobel.v4/reg_sharing.tcl b/Sobel/sobel.v4/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v4/reg_sharing.tcl
diff --git a/Sobel/sobel.v4/res_sharing.tcl b/Sobel/sobel.v4/res_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v4/res_sharing.tcl
diff --git a/Sobel/sobel.v4/rtl.rpt b/Sobel/sobel.v4/rtl.rpt
new file mode 100644
index 0000000..f38a9bd
--- /dev/null
+++ b/Sobel/sobel.v4/rtl.rpt
@@ -0,0 +1,877 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 14:22:40 +0000 2016                      
+
+Solution Settings: sobel.v4
+  Current state: extract
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       161  921601     921600            0  1          
+    Design Total:                     161  921601     921600            0  0          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(10,0,10,0,10)                       11.241                       0.000     11.241 1.301          1           1 
+    mgc_add(11,1,11,1,12)                       12.000                       0.000     12.000 1.206          6           9 
+    mgc_add(12,1,12,1,13)                       13.000                       0.000     13.000 1.272          5           2 
+    mgc_add(15,0,11,1,15)                       16.000                       0.000     16.000 1.633          0           3 
+    mgc_add(16,0,12,1,16)                       17.000                       0.000     17.000 1.696          6           6 
+    mgc_add(16,0,16,0,16)                       17.189                       0.000     17.189 1.690          3           3 
+    mgc_add(17,0,13,1,17)                       18.000                       0.000     18.000 1.758          3           0 
+    mgc_add(19,0,2,1,19)                        20.000                       0.000     20.000 1.908          1           1 
+    mgc_add(2,0,1,0,2)                           3.315                       0.000      3.315 0.658          0           1 
+    mgc_add(2,0,1,1,2)                           3.000                       0.000      3.000 0.658          0           3 
+    mgc_add(2,0,2,0,2)                           3.311                       0.000      3.311 0.653          1           1 
+    mgc_add(3,0,3,0,4)                           4.302                       0.000      4.302 0.761          3           3 
+    mgc_add(3,0,3,1,5)                           4.000                       0.000      4.000 0.436          4           3 
+    mgc_add(4,0,3,0,5)                           5.297                       0.000      5.297 0.856          9           9 
+    mgc_add(4,1,4,1,5)                           5.000                       0.000      5.000 0.691          0           3 
+    mgc_add(5,1,5,1,6)                           6.000                       0.000      6.000 0.775          9           6 
+    mgc_add(6,0,5,0,6)                           7.280                       0.000      7.280 1.018          3           3 
+    mgc_add(6,0,5,1,8)                           7.000                       0.000      7.000 0.693          3           3 
+    mgc_add(8,0,7,0,8)                           9.262                       0.000      9.262 1.165          1           1 
+    mgc_add(9,0,8,1,10)                         10.000                       0.000     10.000 1.072          3           3 
+    mgc_and(1,2)                                 0.730                       0.000      0.730 0.263          0           3 
+    mgc_and(1,3)                                 1.054                       0.000      1.054 0.416          0           3 
+    mgc_and(19,2)                               13.867                       0.000     13.867 0.263          1           1 
+    mgc_and(2,2)                                 1.460                       0.000      1.460 0.263          2           1 
+    mgc_mul(2,1,10,1,12)                       330.000                       2.000     10.000 3.087          6           6 
+    mgc_mul(3,0,6,0,9)                         330.250                       2.000     10.250 2.846          3           3 
+    mgc_mul(3,1,9,0,10)                        331.000                       2.000     11.000 3.078          1           1 
+    mgc_mul(3,1,9,0,12)                        335.000                       2.000     15.000 3.021          2           2 
+    mgc_mux(1,1,2)                               0.919                       0.000      0.919 0.369          2           1 
+    mgc_mux(10,2,4)                             22.259                       0.000     22.259 0.936          6           6 
+    mgc_mux(16,1,2)                             14.711                       0.000     14.711 0.369          6           6 
+    mgc_mux(19,1,2)                             17.469                       0.000     17.469 0.369          1           1 
+    mgc_mux(30,1,2)                             27.583                       0.000     27.583 0.369          0           1 
+    mgc_mux(90,1,2)                             82.748                       0.000     82.748 0.369          3           3 
+    mgc_nand(1,2)                                0.730                       0.000      0.730 0.268          0           6 
+    mgc_nor(1,2)                                 0.730                       0.000      0.730 0.263          0           2 
+    mgc_not(1)                                   0.000                       0.000      0.000 0.000          0          21 
+    mgc_not(10)                                  0.000                       0.000      0.000 0.000          0           9 
+    mgc_not(3)                                   0.000                       0.000      0.000 0.000          0          12 
+    mgc_or(1,2)                                  0.730                       0.000      0.730 0.268          0           2 
+    mgc_or(1,3)                                  1.054                       0.000      1.054 0.425          0           1 
+    mgc_or(1,4)                                  1.379                       0.000      1.379 0.536          0           3 
+    mgc_or(10,2)                                 7.298                       0.000      7.298 0.268          1           1 
+    mgc_or(2,2)                                  1.460                       0.000      1.460 0.268          1           0 
+    mgc_or(30,2)                                21.895                       0.000     21.895 0.268          1           1 
+    mgc_reg_pos(1,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_reg_pos(10,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(12,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(16,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           6 
+    mgc_reg_pos(19,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(2,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(30,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(5,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(6,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(9,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(90,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           3 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,90)                            0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(2,30)                         0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):            5138.261                      24.000   1298.000                              
+    
+  Area Scores
+                      Post-Scheduling   Post-DP & FSM Post-Assignment 
+    ----------------- --------------- --------------- ---------------
+    Total Area Score:   5100.4          5393.8          5138.3        
+    Total Reg:             0.0             0.0             0.0        
+                                                                      
+    DataPath:           5100.4 (100%)   5393.8 (100%)   5138.3 (100%) 
+      MUX:               489.4  (10%)    770.8  (14%)    516.0  (10%) 
+      FUNC:             4563.6  (89%)   4560.6  (85%)   4559.9  (89%) 
+      LOGIC:              47.4   (1%)     62.4   (1%)     62.4   (1%) 
+      BUFFER:              0.0             0.0             0.0        
+      MEM:                 0.0             0.0             0.0        
+      ROM:                 0.0             0.0             0.0        
+      REG:                 0.0             0.0             0.0        
+                                                                      
+    
+    FSM:                   0.0             0.0             0.0        
+      FSM-REG:             0.0             0.0             0.0        
+      FSM-COMB:            0.0             0.0             0.0        
+                                                                      
+    
+  Register-to-Variable Mappings
+    Register                  Size(bits) Gated Register CG Opt Done Variables                                             
+    ------------------------- ---------- -------------- ----------- -----------------------------------------------------
+    regs.regs(0).sva                  90         Y                  regs.regs(0).sva                                      
+    regs.regs(1).sva                  90         Y                  regs.regs(1).sva                                      
+    regs.regs(2).lpi#1.dfm            90         Y                  regs.regs(2).lpi#1.dfm                                
+    vout:rsc:mgc_out_stdreg.d         30         Y                  vout:rsc:mgc_out_stdreg.d                             
+    FRAME:p#1.lpi#1                   19         Y                  FRAME:p#1.lpi#1                                       
+    b(0).sva#1                        16         Y                  b(0).sva#1                                            
+    b(2).sva#1                        16         Y                  b(2).sva#1                                            
+    g(0).sva#1                        16         Y                  g(0).sva#1                                            
+    g(2).sva#1                        16         Y                  g(2).sva#1                                            
+    r(0).sva#1                        16         Y                  r(0).sva#1                                            
+    r(2).sva#1                        16         Y                  r(2).sva#1                                            
+    FRAME:mul#3.itm#1                 12         Y                  FRAME:mul#3.itm#1                                     
+    FRAME:mul#5.itm#1                 12         Y                  FRAME:mul#5.itm#1                                     
+    FRAME:mul#1.itm#1                 10         Y                  FRAME:mul#1.itm#1                                     
+    FRAME:mul#2.itm#1                  9         Y                  FRAME:mul#2.itm#1                                     
+    FRAME:mul#4.itm#1                  9         Y                  FRAME:mul#4.itm#1                                     
+    FRAME:mul.itm#1                    9         Y                  FRAME:mul.itm#1                                       
+    FRAME:slc(blue)#10.itm#1           6         Y                  FRAME:slc(blue)#10.itm#1                              
+    FRAME:slc(green)#10.itm#1          6         Y                  FRAME:slc(green)#10.itm#1                             
+    FRAME:slc(red)#10.itm#1            6         Y                  FRAME:slc(red)#10.itm#1                               
+    FRAME:acc#25.itm#1                 5         Y                  FRAME:acc#25.itm#1                                    
+    FRAME:acc#35.itm#1                 5         Y                  FRAME:acc#35.itm#1                                    
+    FRAME:acc#40.itm#1                 5         Y                  FRAME:acc#40.itm#1                                    
+    i#6.sva#1                          2         Y                  i#6.sva#1                                             
+    exit:FRAME#1.sva                   1         Y                  exit:FRAME#1.sva                                      
+    exit:FRAME.lpi#1.dfm#1             1         Y                  exit:FRAME.lpi#1.dfm#1                                
+    exit:FRAME:for.sva#1.st#1          1         Y                  exit:FRAME:for.sva#1.st#1                             
+    main.stage_0#2                     1         Y                  main.stage_0#2                                        
+                                                                                                                          
+    Total:                           515            515           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  16.524269
+      Slack:      3.4757309999999997
+      
+      Path                                               Startpoint                                Endpoint                           Delay   Slack   
+      -------------------------------------------------- ----------------------------------------- ---------------------------------- ------- -------
+      1                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#35.itm#1) 16.5243 3.4757  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#59                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#59.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC2-3:acc#1                          mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/red#2.sva                                                                                                          0.0000  9.6738  
+        sobel:core/slc(red#2.sva)#6                                                                                                   0.0000  9.6738  
+        sobel:core/slc(red#2.sva)#6.itm                                                                                               0.0000  9.6738  
+        sobel:core/FRAME:not#1                           mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#1.itm                                                                                                    0.0000  9.6738  
+        sobel:core/FRAME:acc#14                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#14.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#15                          mgc_add_4_0_3_0_5                                                            0.8564  11.2911 
+        sobel:core/FRAME:acc#15.itm                                                                                                   0.0000  11.2911 
+        sobel:core/FRAME:acc#7                           mgc_add_6_0_5_0_6                                                            1.0184  12.3095 
+        sobel:core/FRAME:acc#7.psp.sva                                                                                                0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#7.psp.sva)#2                                                                                         0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#7.psp.sva)#2.itm                                                                                     0.0000  12.3095 
+        sobel:core/conc#154                                                                                                           0.0000  12.3095 
+        sobel:core/conc#154.itm                                                                                                       0.0000  12.3095 
+        sobel:core/FRAME:acc#17                          mgc_add_5_1_5_1_6                                                            0.7751  13.0846 
+        sobel:core/FRAME:acc#17.itm                                                                                                   0.0000  13.0846 
+        sobel:core/FRAME:slc#2                                                                                                        0.0000  13.0846 
+        sobel:core/FRAME:acc#8.psp.sva                                                                                                0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#8.psp.sva)#1                                                                                         0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#8.psp.sva)#1.itm                                                                                     0.0000  13.0846 
+        sobel:core/FRAME:or                              mgc_or_1_4                                                                   0.5358  13.6203 
+        sobel:core/FRAME:or.itm                                                                                                       0.0000  13.6203 
+        sobel:core/and#1                                 mgc_and_1_3                                                                  0.4161  14.0364 
+        sobel:core/and#1.itm                                                                                                          0.0000  14.0364 
+        sobel:core/FRAME:conc#79                                                                                                      0.0000  14.0364 
+        sobel:core/FRAME:conc#79.itm                                                                                                  0.0000  14.0364 
+        sobel:core/FRAME:acc#33                          mgc_add_4_0_3_0_5                                                            0.8564  14.8928 
+        sobel:core/FRAME:acc#33.itm                                                                                                   0.0000  14.8928 
+        sobel:core/FRAME:slc#6                                                                                                        0.0000  14.8928 
+        sobel:core/FRAME:slc#6.itm                                                                                                    0.0000  14.8928 
+        sobel:core/FRAME:acc#34                          mgc_add_4_0_3_0_5                                                            0.8564  15.7492 
+        sobel:core/FRAME:acc#34.itm                                                                                                   0.0000  15.7492 
+        sobel:core/FRAME:acc#35                          mgc_add_5_1_5_1_6                                                            0.7751  16.5243 
+        sobel:core/FRAME:acc#35.itm                                                                                                   0.0000  16.5243 
+        sobel:core/reg(FRAME:acc#35.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  16.5243 
+                                                                                                                                                      
+      2                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#35.itm#1) 16.5243 3.4757  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#59                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#59.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC2-3:acc#1                          mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/red#2.sva                                                                                                          0.0000  9.6738  
+        sobel:core/slc(red#2.sva)#7                                                                                                   0.0000  9.6738  
+        sobel:core/slc(red#2.sva)#7.itm                                                                                               0.0000  9.6738  
+        sobel:core/FRAME:acc#14                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#14.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#15                          mgc_add_4_0_3_0_5                                                            0.8564  11.2911 
+        sobel:core/FRAME:acc#15.itm                                                                                                   0.0000  11.2911 
+        sobel:core/FRAME:acc#7                           mgc_add_6_0_5_0_6                                                            1.0184  12.3095 
+        sobel:core/FRAME:acc#7.psp.sva                                                                                                0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#7.psp.sva)#2                                                                                         0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#7.psp.sva)#2.itm                                                                                     0.0000  12.3095 
+        sobel:core/conc#154                                                                                                           0.0000  12.3095 
+        sobel:core/conc#154.itm                                                                                                       0.0000  12.3095 
+        sobel:core/FRAME:acc#17                          mgc_add_5_1_5_1_6                                                            0.7751  13.0846 
+        sobel:core/FRAME:acc#17.itm                                                                                                   0.0000  13.0846 
+        sobel:core/FRAME:slc#2                                                                                                        0.0000  13.0846 
+        sobel:core/FRAME:acc#8.psp.sva                                                                                                0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#8.psp.sva)#1                                                                                         0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#8.psp.sva)#1.itm                                                                                     0.0000  13.0846 
+        sobel:core/FRAME:or                              mgc_or_1_4                                                                   0.5358  13.6203 
+        sobel:core/FRAME:or.itm                                                                                                       0.0000  13.6203 
+        sobel:core/and#1                                 mgc_and_1_3                                                                  0.4161  14.0364 
+        sobel:core/and#1.itm                                                                                                          0.0000  14.0364 
+        sobel:core/FRAME:conc#79                                                                                                      0.0000  14.0364 
+        sobel:core/FRAME:conc#79.itm                                                                                                  0.0000  14.0364 
+        sobel:core/FRAME:acc#33                          mgc_add_4_0_3_0_5                                                            0.8564  14.8928 
+        sobel:core/FRAME:acc#33.itm                                                                                                   0.0000  14.8928 
+        sobel:core/FRAME:slc#6                                                                                                        0.0000  14.8928 
+        sobel:core/FRAME:slc#6.itm                                                                                                    0.0000  14.8928 
+        sobel:core/FRAME:acc#34                          mgc_add_4_0_3_0_5                                                            0.8564  15.7492 
+        sobel:core/FRAME:acc#34.itm                                                                                                   0.0000  15.7492 
+        sobel:core/FRAME:acc#35                          mgc_add_5_1_5_1_6                                                            0.7751  16.5243 
+        sobel:core/FRAME:acc#35.itm                                                                                                   0.0000  16.5243 
+        sobel:core/reg(FRAME:acc#35.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  16.5243 
+                                                                                                                                                      
+      3                                                  sobel:core/reg(exit:FRAME#1.sva)          sobel:core/reg(FRAME:acc#35.itm#1) 16.5243 3.4757  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME#1.sva)                 mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME#1.sva                                                                                                   0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#59                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#59.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC2-3:acc#1                          mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/red#2.sva                                                                                                          0.0000  9.6738  
+        sobel:core/slc(red#2.sva)#7                                                                                                   0.0000  9.6738  
+        sobel:core/slc(red#2.sva)#7.itm                                                                                               0.0000  9.6738  
+        sobel:core/FRAME:acc#14                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#14.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#15                          mgc_add_4_0_3_0_5                                                            0.8564  11.2911 
+        sobel:core/FRAME:acc#15.itm                                                                                                   0.0000  11.2911 
+        sobel:core/FRAME:acc#7                           mgc_add_6_0_5_0_6                                                            1.0184  12.3095 
+        sobel:core/FRAME:acc#7.psp.sva                                                                                                0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#7.psp.sva)#2                                                                                         0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#7.psp.sva)#2.itm                                                                                     0.0000  12.3095 
+        sobel:core/conc#154                                                                                                           0.0000  12.3095 
+        sobel:core/conc#154.itm                                                                                                       0.0000  12.3095 
+        sobel:core/FRAME:acc#17                          mgc_add_5_1_5_1_6                                                            0.7751  13.0846 
+        sobel:core/FRAME:acc#17.itm                                                                                                   0.0000  13.0846 
+        sobel:core/FRAME:slc#2                                                                                                        0.0000  13.0846 
+        sobel:core/FRAME:acc#8.psp.sva                                                                                                0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#8.psp.sva)#1                                                                                         0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#8.psp.sva)#1.itm                                                                                     0.0000  13.0846 
+        sobel:core/FRAME:or                              mgc_or_1_4                                                                   0.5358  13.6203 
+        sobel:core/FRAME:or.itm                                                                                                       0.0000  13.6203 
+        sobel:core/and#1                                 mgc_and_1_3                                                                  0.4161  14.0364 
+        sobel:core/and#1.itm                                                                                                          0.0000  14.0364 
+        sobel:core/FRAME:conc#79                                                                                                      0.0000  14.0364 
+        sobel:core/FRAME:conc#79.itm                                                                                                  0.0000  14.0364 
+        sobel:core/FRAME:acc#33                          mgc_add_4_0_3_0_5                                                            0.8564  14.8928 
+        sobel:core/FRAME:acc#33.itm                                                                                                   0.0000  14.8928 
+        sobel:core/FRAME:slc#6                                                                                                        0.0000  14.8928 
+        sobel:core/FRAME:slc#6.itm                                                                                                    0.0000  14.8928 
+        sobel:core/FRAME:acc#34                          mgc_add_4_0_3_0_5                                                            0.8564  15.7492 
+        sobel:core/FRAME:acc#34.itm                                                                                                   0.0000  15.7492 
+        sobel:core/FRAME:acc#35                          mgc_add_5_1_5_1_6                                                            0.7751  16.5243 
+        sobel:core/FRAME:acc#35.itm                                                                                                   0.0000  16.5243 
+        sobel:core/reg(FRAME:acc#35.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  16.5243 
+                                                                                                                                                      
+      4                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#35.itm#1) 16.5243 3.4757  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#59                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#59.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC2-3:acc#1                          mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/red#2.sva                                                                                                          0.0000  9.6738  
+        sobel:core/slc(red#2.sva)#6                                                                                                   0.0000  9.6738  
+        sobel:core/slc(red#2.sva)#6.itm                                                                                               0.0000  9.6738  
+        sobel:core/FRAME:not#1                           mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#1.itm                                                                                                    0.0000  9.6738  
+        sobel:core/FRAME:acc#14                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#14.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#15                          mgc_add_4_0_3_0_5                                                            0.8564  11.2911 
+        sobel:core/FRAME:acc#15.itm                                                                                                   0.0000  11.2911 
+        sobel:core/FRAME:acc#7                           mgc_add_6_0_5_0_6                                                            1.0184  12.3095 
+        sobel:core/FRAME:acc#7.psp.sva                                                                                                0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#7.psp.sva)#2                                                                                         0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#7.psp.sva)#2.itm                                                                                     0.0000  12.3095 
+        sobel:core/conc#154                                                                                                           0.0000  12.3095 
+        sobel:core/conc#154.itm                                                                                                       0.0000  12.3095 
+        sobel:core/FRAME:acc#17                          mgc_add_5_1_5_1_6                                                            0.7751  13.0846 
+        sobel:core/FRAME:acc#17.itm                                                                                                   0.0000  13.0846 
+        sobel:core/FRAME:slc#2                                                                                                        0.0000  13.0846 
+        sobel:core/FRAME:acc#8.psp.sva                                                                                                0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#8.psp.sva)#2                                                                                         0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#8.psp.sva)#2.itm                                                                                     0.0000  13.0846 
+        sobel:core/FRAME:or                              mgc_or_1_4                                                                   0.5358  13.6203 
+        sobel:core/FRAME:or.itm                                                                                                       0.0000  13.6203 
+        sobel:core/and#1                                 mgc_and_1_3                                                                  0.4161  14.0364 
+        sobel:core/and#1.itm                                                                                                          0.0000  14.0364 
+        sobel:core/FRAME:conc#79                                                                                                      0.0000  14.0364 
+        sobel:core/FRAME:conc#79.itm                                                                                                  0.0000  14.0364 
+        sobel:core/FRAME:acc#33                          mgc_add_4_0_3_0_5                                                            0.8564  14.8928 
+        sobel:core/FRAME:acc#33.itm                                                                                                   0.0000  14.8928 
+        sobel:core/FRAME:slc#6                                                                                                        0.0000  14.8928 
+        sobel:core/FRAME:slc#6.itm                                                                                                    0.0000  14.8928 
+        sobel:core/FRAME:acc#34                          mgc_add_4_0_3_0_5                                                            0.8564  15.7492 
+        sobel:core/FRAME:acc#34.itm                                                                                                   0.0000  15.7492 
+        sobel:core/FRAME:acc#35                          mgc_add_5_1_5_1_6                                                            0.7751  16.5243 
+        sobel:core/FRAME:acc#35.itm                                                                                                   0.0000  16.5243 
+        sobel:core/reg(FRAME:acc#35.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  16.5243 
+                                                                                                                                                      
+      5                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#25.itm#1) 16.5243 3.4757  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#16:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#16:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#7                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#7.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#12                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/g(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#63                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#63.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#47                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#47.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC2-3:acc#2                          mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/green#2.sva                                                                                                        0.0000  9.6738  
+        sobel:core/slc(green#2.sva)#6                                                                                                 0.0000  9.6738  
+        sobel:core/slc(green#2.sva)#6.itm                                                                                             0.0000  9.6738  
+        sobel:core/FRAME:not#10                          mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#10.itm                                                                                                   0.0000  9.6738  
+        sobel:core/FRAME:acc#19                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#19.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#20                          mgc_add_4_0_3_0_5                                                            0.8564  11.2911 
+        sobel:core/FRAME:acc#20.itm                                                                                                   0.0000  11.2911 
+        sobel:core/FRAME:acc#9                           mgc_add_6_0_5_0_6                                                            1.0184  12.3095 
+        sobel:core/FRAME:acc#9.psp.sva                                                                                                0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#9.psp.sva)#2                                                                                         0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#9.psp.sva)#2.itm                                                                                     0.0000  12.3095 
+        sobel:core/conc#160                                                                                                           0.0000  12.3095 
+        sobel:core/conc#160.itm                                                                                                       0.0000  12.3095 
+        sobel:core/FRAME:acc#22                          mgc_add_5_1_5_1_6                                                            0.7751  13.0846 
+        sobel:core/FRAME:acc#22.itm                                                                                                   0.0000  13.0846 
+        sobel:core/FRAME:slc#3                                                                                                        0.0000  13.0846 
+        sobel:core/FRAME:acc#10.psp.sva                                                                                               0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#10.psp.sva)#1                                                                                        0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#10.psp.sva)#1.itm                                                                                    0.0000  13.0846 
+        sobel:core/FRAME:or#1                            mgc_or_1_4                                                                   0.5358  13.6203 
+        sobel:core/FRAME:or#1.itm                                                                                                     0.0000  13.6203 
+        sobel:core/and#3                                 mgc_and_1_3                                                                  0.4161  14.0364 
+        sobel:core/and#3.itm                                                                                                          0.0000  14.0364 
+        sobel:core/FRAME:conc#73                                                                                                      0.0000  14.0364 
+        sobel:core/FRAME:conc#73.itm                                                                                                  0.0000  14.0364 
+        sobel:core/FRAME:acc#23                          mgc_add_4_0_3_0_5                                                            0.8564  14.8928 
+        sobel:core/FRAME:acc#23.itm                                                                                                   0.0000  14.8928 
+        sobel:core/FRAME:slc#4                                                                                                        0.0000  14.8928 
+        sobel:core/FRAME:slc#4.itm                                                                                                    0.0000  14.8928 
+        sobel:core/FRAME:acc#24                          mgc_add_4_0_3_0_5                                                            0.8564  15.7492 
+        sobel:core/FRAME:acc#24.itm                                                                                                   0.0000  15.7492 
+        sobel:core/FRAME:acc#25                          mgc_add_5_1_5_1_6                                                            0.7751  16.5243 
+        sobel:core/FRAME:acc#25.itm                                                                                                   0.0000  16.5243 
+        sobel:core/reg(FRAME:acc#25.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  16.5243 
+                                                                                                                                                      
+      6                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#25.itm#1) 16.5243 3.4757  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#2                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(1).sva.dfm:mx0                                                                                           0.0000  0.6315  
+        sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1                                                                                    0.0000  0.6315  
+        sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm                                                                                0.0000  0.6315  
+        sobel:core/regs.operator[]#16:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#16:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#7                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#7.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#12                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/g(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#63                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#63.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#47                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#47.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC2-3:acc#2                          mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/green#2.sva                                                                                                        0.0000  9.6738  
+        sobel:core/slc(green#2.sva)#6                                                                                                 0.0000  9.6738  
+        sobel:core/slc(green#2.sva)#6.itm                                                                                             0.0000  9.6738  
+        sobel:core/FRAME:not#10                          mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#10.itm                                                                                                   0.0000  9.6738  
+        sobel:core/FRAME:acc#19                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#19.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#20                          mgc_add_4_0_3_0_5                                                            0.8564  11.2911 
+        sobel:core/FRAME:acc#20.itm                                                                                                   0.0000  11.2911 
+        sobel:core/FRAME:acc#9                           mgc_add_6_0_5_0_6                                                            1.0184  12.3095 
+        sobel:core/FRAME:acc#9.psp.sva                                                                                                0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#9.psp.sva)#2                                                                                         0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#9.psp.sva)#2.itm                                                                                     0.0000  12.3095 
+        sobel:core/conc#160                                                                                                           0.0000  12.3095 
+        sobel:core/conc#160.itm                                                                                                       0.0000  12.3095 
+        sobel:core/FRAME:acc#22                          mgc_add_5_1_5_1_6                                                            0.7751  13.0846 
+        sobel:core/FRAME:acc#22.itm                                                                                                   0.0000  13.0846 
+        sobel:core/FRAME:slc#3                                                                                                        0.0000  13.0846 
+        sobel:core/FRAME:acc#10.psp.sva                                                                                               0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#10.psp.sva)#1                                                                                        0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#10.psp.sva)#1.itm                                                                                    0.0000  13.0846 
+        sobel:core/FRAME:or#1                            mgc_or_1_4                                                                   0.5358  13.6203 
+        sobel:core/FRAME:or#1.itm                                                                                                     0.0000  13.6203 
+        sobel:core/and#3                                 mgc_and_1_3                                                                  0.4161  14.0364 
+        sobel:core/and#3.itm                                                                                                          0.0000  14.0364 
+        sobel:core/FRAME:conc#73                                                                                                      0.0000  14.0364 
+        sobel:core/FRAME:conc#73.itm                                                                                                  0.0000  14.0364 
+        sobel:core/FRAME:acc#23                          mgc_add_4_0_3_0_5                                                            0.8564  14.8928 
+        sobel:core/FRAME:acc#23.itm                                                                                                   0.0000  14.8928 
+        sobel:core/FRAME:slc#4                                                                                                        0.0000  14.8928 
+        sobel:core/FRAME:slc#4.itm                                                                                                    0.0000  14.8928 
+        sobel:core/FRAME:acc#24                          mgc_add_4_0_3_0_5                                                            0.8564  15.7492 
+        sobel:core/FRAME:acc#24.itm                                                                                                   0.0000  15.7492 
+        sobel:core/FRAME:acc#25                          mgc_add_5_1_5_1_6                                                            0.7751  16.5243 
+        sobel:core/FRAME:acc#25.itm                                                                                                   0.0000  16.5243 
+        sobel:core/reg(FRAME:acc#25.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  16.5243 
+                                                                                                                                                      
+      7                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#35.itm#1) 16.5243 3.4757  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#59                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#59.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC2-3:acc#1                          mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/red#2.sva                                                                                                          0.0000  9.6738  
+        sobel:core/slc(red#2.sva)#6                                                                                                   0.0000  9.6738  
+        sobel:core/slc(red#2.sva)#6.itm                                                                                               0.0000  9.6738  
+        sobel:core/FRAME:not#1                           mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#1.itm                                                                                                    0.0000  9.6738  
+        sobel:core/FRAME:acc#14                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#14.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#15                          mgc_add_4_0_3_0_5                                                            0.8564  11.2911 
+        sobel:core/FRAME:acc#15.itm                                                                                                   0.0000  11.2911 
+        sobel:core/FRAME:acc#7                           mgc_add_6_0_5_0_6                                                            1.0184  12.3095 
+        sobel:core/FRAME:acc#7.psp.sva                                                                                                0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#7.psp.sva)#3                                                                                         0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#7.psp.sva)#3.itm                                                                                     0.0000  12.3095 
+        sobel:core/FRAME:not#4                           mgc_not_3                                                                    0.0000  12.3095 
+        sobel:core/FRAME:not#4.itm                                                                                                    0.0000  12.3095 
+        sobel:core/FRAME:conc#67                                                                                                      0.0000  12.3095 
+        sobel:core/FRAME:conc#67.itm                                                                                                  0.0000  12.3095 
+        sobel:core/FRAME:acc#17                          mgc_add_5_1_5_1_6                                                            0.7751  13.0846 
+        sobel:core/FRAME:acc#17.itm                                                                                                   0.0000  13.0846 
+        sobel:core/FRAME:slc#2                                                                                                        0.0000  13.0846 
+        sobel:core/FRAME:acc#8.psp.sva                                                                                                0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#8.psp.sva)#2                                                                                         0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#8.psp.sva)#2.itm                                                                                     0.0000  13.0846 
+        sobel:core/FRAME:or                              mgc_or_1_4                                                                   0.5358  13.6203 
+        sobel:core/FRAME:or.itm                                                                                                       0.0000  13.6203 
+        sobel:core/and#1                                 mgc_and_1_3                                                                  0.4161  14.0364 
+        sobel:core/and#1.itm                                                                                                          0.0000  14.0364 
+        sobel:core/FRAME:conc#79                                                                                                      0.0000  14.0364 
+        sobel:core/FRAME:conc#79.itm                                                                                                  0.0000  14.0364 
+        sobel:core/FRAME:acc#33                          mgc_add_4_0_3_0_5                                                            0.8564  14.8928 
+        sobel:core/FRAME:acc#33.itm                                                                                                   0.0000  14.8928 
+        sobel:core/FRAME:slc#6                                                                                                        0.0000  14.8928 
+        sobel:core/FRAME:slc#6.itm                                                                                                    0.0000  14.8928 
+        sobel:core/FRAME:acc#34                          mgc_add_4_0_3_0_5                                                            0.8564  15.7492 
+        sobel:core/FRAME:acc#34.itm                                                                                                   0.0000  15.7492 
+        sobel:core/FRAME:acc#35                          mgc_add_5_1_5_1_6                                                            0.7751  16.5243 
+        sobel:core/FRAME:acc#35.itm                                                                                                   0.0000  16.5243 
+        sobel:core/reg(FRAME:acc#35.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  16.5243 
+                                                                                                                                                      
+      8                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#40.itm#1) 16.5243 3.4757  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#1                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(2).lpi#1.dfm:mx0                                                                                         0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3                                                                                  0.0000  0.6315  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm                                                                              0.0000  0.6315  
+        sobel:core/regs.operator[]#17:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#17:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#8                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#8.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#14                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/b(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(b(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(b(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#67                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#67.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#49                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#49.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC2-3:acc#3                          mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/blue#2.sva                                                                                                         0.0000  9.6738  
+        sobel:core/slc(blue#2.sva)#6                                                                                                  0.0000  9.6738  
+        sobel:core/slc(blue#2.sva)#6.itm                                                                                              0.0000  9.6738  
+        sobel:core/FRAME:not#19                          mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#19.itm                                                                                                   0.0000  9.6738  
+        sobel:core/FRAME:acc#29                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#29.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#30                          mgc_add_4_0_3_0_5                                                            0.8564  11.2911 
+        sobel:core/FRAME:acc#30.itm                                                                                                   0.0000  11.2911 
+        sobel:core/FRAME:acc#11                          mgc_add_6_0_5_0_6                                                            1.0184  12.3095 
+        sobel:core/FRAME:acc#11.psp.sva                                                                                               0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#11.psp.sva)#2                                                                                        0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#11.psp.sva)#2.itm                                                                                    0.0000  12.3095 
+        sobel:core/conc#148                                                                                                           0.0000  12.3095 
+        sobel:core/conc#148.itm                                                                                                       0.0000  12.3095 
+        sobel:core/FRAME:acc#32                          mgc_add_5_1_5_1_6                                                            0.7751  13.0846 
+        sobel:core/FRAME:acc#32.itm                                                                                                   0.0000  13.0846 
+        sobel:core/FRAME:slc#5                                                                                                        0.0000  13.0846 
+        sobel:core/FRAME:acc#12.psp.sva                                                                                               0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#12.psp.sva)#1                                                                                        0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#12.psp.sva)#1.itm                                                                                    0.0000  13.0846 
+        sobel:core/FRAME:or#2                            mgc_or_1_4                                                                   0.5358  13.6203 
+        sobel:core/FRAME:or#2.itm                                                                                                     0.0000  13.6203 
+        sobel:core/and#5                                 mgc_and_1_3                                                                  0.4161  14.0364 
+        sobel:core/and#5.itm                                                                                                          0.0000  14.0364 
+        sobel:core/FRAME:conc#82                                                                                                      0.0000  14.0364 
+        sobel:core/FRAME:conc#82.itm                                                                                                  0.0000  14.0364 
+        sobel:core/FRAME:acc#38                          mgc_add_4_0_3_0_5                                                            0.8564  14.8928 
+        sobel:core/FRAME:acc#38.itm                                                                                                   0.0000  14.8928 
+        sobel:core/FRAME:slc#7                                                                                                        0.0000  14.8928 
+        sobel:core/FRAME:slc#7.itm                                                                                                    0.0000  14.8928 
+        sobel:core/FRAME:acc#39                          mgc_add_4_0_3_0_5                                                            0.8564  15.7492 
+        sobel:core/FRAME:acc#39.itm                                                                                                   0.0000  15.7492 
+        sobel:core/FRAME:acc#40                          mgc_add_5_1_5_1_6                                                            0.7751  16.5243 
+        sobel:core/FRAME:acc#40.itm                                                                                                   0.0000  16.5243 
+        sobel:core/reg(FRAME:acc#40.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  16.5243 
+                                                                                                                                                      
+      9                                                  sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#25.itm#1) 16.5243 3.4757  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#3                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(0).sva.dfm:mx0                                                                                           0.0000  0.6315  
+        sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4                                                                                    0.0000  0.6315  
+        sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm                                                                                0.0000  0.6315  
+        sobel:core/regs.operator[]#16:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#16:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#7                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#7.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#12                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/g(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(g(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#63                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#63.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#47                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#47.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC2-3:acc#2                          mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/green#2.sva                                                                                                        0.0000  9.6738  
+        sobel:core/slc(green#2.sva)#6                                                                                                 0.0000  9.6738  
+        sobel:core/slc(green#2.sva)#6.itm                                                                                             0.0000  9.6738  
+        sobel:core/FRAME:not#10                          mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#10.itm                                                                                                   0.0000  9.6738  
+        sobel:core/FRAME:acc#19                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#19.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#20                          mgc_add_4_0_3_0_5                                                            0.8564  11.2911 
+        sobel:core/FRAME:acc#20.itm                                                                                                   0.0000  11.2911 
+        sobel:core/FRAME:acc#9                           mgc_add_6_0_5_0_6                                                            1.0184  12.3095 
+        sobel:core/FRAME:acc#9.psp.sva                                                                                                0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#9.psp.sva)#2                                                                                         0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#9.psp.sva)#2.itm                                                                                     0.0000  12.3095 
+        sobel:core/conc#160                                                                                                           0.0000  12.3095 
+        sobel:core/conc#160.itm                                                                                                       0.0000  12.3095 
+        sobel:core/FRAME:acc#22                          mgc_add_5_1_5_1_6                                                            0.7751  13.0846 
+        sobel:core/FRAME:acc#22.itm                                                                                                   0.0000  13.0846 
+        sobel:core/FRAME:slc#3                                                                                                        0.0000  13.0846 
+        sobel:core/FRAME:acc#10.psp.sva                                                                                               0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#10.psp.sva)#1                                                                                        0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#10.psp.sva)#1.itm                                                                                    0.0000  13.0846 
+        sobel:core/FRAME:or#1                            mgc_or_1_4                                                                   0.5358  13.6203 
+        sobel:core/FRAME:or#1.itm                                                                                                     0.0000  13.6203 
+        sobel:core/and#3                                 mgc_and_1_3                                                                  0.4161  14.0364 
+        sobel:core/and#3.itm                                                                                                          0.0000  14.0364 
+        sobel:core/FRAME:conc#73                                                                                                      0.0000  14.0364 
+        sobel:core/FRAME:conc#73.itm                                                                                                  0.0000  14.0364 
+        sobel:core/FRAME:acc#23                          mgc_add_4_0_3_0_5                                                            0.8564  14.8928 
+        sobel:core/FRAME:acc#23.itm                                                                                                   0.0000  14.8928 
+        sobel:core/FRAME:slc#4                                                                                                        0.0000  14.8928 
+        sobel:core/FRAME:slc#4.itm                                                                                                    0.0000  14.8928 
+        sobel:core/FRAME:acc#24                          mgc_add_4_0_3_0_5                                                            0.8564  15.7492 
+        sobel:core/FRAME:acc#24.itm                                                                                                   0.0000  15.7492 
+        sobel:core/FRAME:acc#25                          mgc_add_5_1_5_1_6                                                            0.7751  16.5243 
+        sobel:core/FRAME:acc#25.itm                                                                                                   0.0000  16.5243 
+        sobel:core/reg(FRAME:acc#25.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  16.5243 
+                                                                                                                                                      
+      10                                                 sobel:core/reg(exit:FRAME:for.sva#1.st#1) sobel:core/reg(FRAME:acc#35.itm#1) 16.5243 3.4757  
+                                                                                                                                                      
+        Instance                                         Component                                                                    Delta   Delay   
+        --------                                         ---------                                                                    -----   -----   
+        sobel:core/reg(exit:FRAME:for.sva#1.st#1)        mgc_reg_pos_1_1_0_0_0_1_1                                                    0.0000  0.0000  
+        sobel:core/exit:FRAME:for.sva#1.st#1                                                                                          0.0000  0.0000  
+        sobel:core/nor                                   mgc_nor_1_2                                                                  0.2625  0.2625  
+        sobel:core/and.dcpl                                                                                                           0.0000  0.2625  
+        sobel:core/mux#2                                 mgc_mux_90_1_2                                                               0.3690  0.6315  
+        sobel:core/regs.regs(1).sva.dfm:mx0                                                                                           0.0000  0.6315  
+        sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2                                                                                    0.0000  0.6315  
+        sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm                                                                                0.0000  0.6315  
+        sobel:core/regs.operator[]#15:mux                mgc_mux_10_2_4                                                               0.9364  1.5679  
+        sobel:core/regs.operator[]#15:mux.itm                                                                                         0.0000  1.5679  
+        sobel:core/FRAME:for:mul#6                       mgc_mul_2_1_10_1_12                                                          3.0868  4.6547  
+        sobel:core/FRAME:for:mul#6.itm                                                                                                0.0000  4.6547  
+        sobel:core/FRAME:for:acc#10                      mgc_add_16_0_12_1_16                                                         1.6960  6.3507  
+        sobel:core/r(2).sva#3                                                                                                         0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1)                                                                                                    0.0000  6.3507  
+        sobel:core/slc(r(2).sva#1).itm                                                                                                0.0000  6.3507  
+        sobel:core/ACC1:acc#59                           mgc_add_15_0_11_1_15                                                         1.6333  7.9840  
+        sobel:core/ACC1:acc#59.itm                                                                                                    0.0000  7.9840  
+        sobel:core/ACC1:conc#45                                                                                                       0.0000  7.9840  
+        sobel:core/ACC1:conc#45.itm                                                                                                   0.0000  7.9840  
+        sobel:core/ACC2-3:acc#1                          mgc_add_16_0_16_0_16                                                         1.6898  9.6738  
+        sobel:core/red#2.sva                                                                                                          0.0000  9.6738  
+        sobel:core/slc(red#2.sva)#6                                                                                                   0.0000  9.6738  
+        sobel:core/slc(red#2.sva)#6.itm                                                                                               0.0000  9.6738  
+        sobel:core/FRAME:not#1                           mgc_not_3                                                                    0.0000  9.6738  
+        sobel:core/FRAME:not#1.itm                                                                                                    0.0000  9.6738  
+        sobel:core/FRAME:acc#14                          mgc_add_3_0_3_0_4                                                            0.7609  10.4347 
+        sobel:core/FRAME:acc#14.itm                                                                                                   0.0000  10.4347 
+        sobel:core/FRAME:acc#15                          mgc_add_4_0_3_0_5                                                            0.8564  11.2911 
+        sobel:core/FRAME:acc#15.itm                                                                                                   0.0000  11.2911 
+        sobel:core/FRAME:acc#7                           mgc_add_6_0_5_0_6                                                            1.0184  12.3095 
+        sobel:core/FRAME:acc#7.psp.sva                                                                                                0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#7.psp.sva)#3                                                                                         0.0000  12.3095 
+        sobel:core/slc(FRAME:acc#7.psp.sva)#3.itm                                                                                     0.0000  12.3095 
+        sobel:core/FRAME:not#4                           mgc_not_3                                                                    0.0000  12.3095 
+        sobel:core/FRAME:not#4.itm                                                                                                    0.0000  12.3095 
+        sobel:core/FRAME:conc#67                                                                                                      0.0000  12.3095 
+        sobel:core/FRAME:conc#67.itm                                                                                                  0.0000  12.3095 
+        sobel:core/FRAME:acc#17                          mgc_add_5_1_5_1_6                                                            0.7751  13.0846 
+        sobel:core/FRAME:acc#17.itm                                                                                                   0.0000  13.0846 
+        sobel:core/FRAME:slc#2                                                                                                        0.0000  13.0846 
+        sobel:core/FRAME:acc#8.psp.sva                                                                                                0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#8.psp.sva)#2                                                                                         0.0000  13.0846 
+        sobel:core/slc(FRAME:acc#8.psp.sva)#2.itm                                                                                     0.0000  13.0846 
+        sobel:core/FRAME:or                              mgc_or_1_4                                                                   0.5358  13.6203 
+        sobel:core/FRAME:or.itm                                                                                                       0.0000  13.6203 
+        sobel:core/and#1                                 mgc_and_1_3                                                                  0.4161  14.0364 
+        sobel:core/and#1.itm                                                                                                          0.0000  14.0364 
+        sobel:core/FRAME:conc#79                                                                                                      0.0000  14.0364 
+        sobel:core/FRAME:conc#79.itm                                                                                                  0.0000  14.0364 
+        sobel:core/FRAME:acc#33                          mgc_add_4_0_3_0_5                                                            0.8564  14.8928 
+        sobel:core/FRAME:acc#33.itm                                                                                                   0.0000  14.8928 
+        sobel:core/FRAME:slc#6                                                                                                        0.0000  14.8928 
+        sobel:core/FRAME:slc#6.itm                                                                                                    0.0000  14.8928 
+        sobel:core/FRAME:acc#34                          mgc_add_4_0_3_0_5                                                            0.8564  15.7492 
+        sobel:core/FRAME:acc#34.itm                                                                                                   0.0000  15.7492 
+        sobel:core/FRAME:acc#35                          mgc_add_5_1_5_1_6                                                            0.7751  16.5243 
+        sobel:core/FRAME:acc#35.itm                                                                                                   0.0000  16.5243 
+        sobel:core/reg(FRAME:acc#35.itm#1)               mgc_reg_pos_5_1_0_0_0_1_1                                                    0.0000  16.5243 
+                                                                                                                                                      
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                  Port                         Slack (Delay) Messages 
+      ----------------------------------------- -------------------------- ------- ------- --------
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d) mux.itm                    16.0279  3.9721          
+      sobel:core/reg(FRAME:mul.itm#1)           FRAME:mul.itm               7.4801 12.5199          
+      sobel:core/reg(FRAME:slc(red)#10.itm#1)   slc(red#2.sva)#4.itm       10.3262  9.6738          
+      sobel:core/reg(FRAME:acc#35.itm#1)        FRAME:acc#35.itm            3.4757 16.5243          
+      sobel:core/reg(FRAME:mul#1.itm#1)         FRAME:mul#1.itm             7.2485 12.7515          
+      sobel:core/reg(FRAME:mul#4.itm#1)         FRAME:mul#4.itm             7.4801 12.5199          
+      sobel:core/reg(FRAME:slc(blue)#10.itm#1)  slc(blue#2.sva)#4.itm      10.3262  9.6738          
+      sobel:core/reg(FRAME:acc#40.itm#1)        FRAME:acc#40.itm            3.4757 16.5243          
+      sobel:core/reg(FRAME:mul#5.itm#1)         FRAME:mul#5.itm             7.3052 12.6948          
+      sobel:core/reg(FRAME:mul#2.itm#1)         FRAME:mul#2.itm             7.4801 12.5199          
+      sobel:core/reg(FRAME:slc(green)#10.itm#1) slc(green#2.sva)#4.itm     10.3262  9.6738          
+      sobel:core/reg(FRAME:acc#25.itm#1)        FRAME:acc#25.itm            3.4757 16.5243          
+      sobel:core/reg(FRAME:mul#3.itm#1)         FRAME:mul#3.itm             7.3052 12.6948          
+      sobel:core/reg(exit:FRAME:for.sva#1.st#1) FRAME:for:not#7.itm        18.1594  1.8406          
+      sobel:core/reg(i#6.sva#1)                 i#6.sva#2                  17.5279  2.4721          
+      sobel:core/reg(exit:FRAME#1.sva)          FRAME:and.itm              16.0328  3.9672          
+      sobel:core/reg(main.stage_0#2)            Cn1_1#2                    20.0000  0.0000          
+      sobel:core/reg(regs.regs(2).lpi#1.dfm)    regs.regs(2).lpi#1.dfm:mx0  3.4757 16.5243          
+      sobel:core/reg(regs.regs(1).sva)          regs.regs(1).sva.dfm:mx0    3.4757 16.5243          
+      sobel:core/reg(regs.regs(0).sva)          regs.regs(0).sva.dfm:mx0    3.4757 16.5243          
+      sobel:core/reg(exit:FRAME.lpi#1.dfm#1)    exit:FRAME.lpi#1.dfm#1:mx0 16.0328  3.9672          
+      sobel:core/reg(b(2).sva#1)                b(2).sva#3                  3.4757 16.5243          
+      sobel:core/reg(b(0).sva#1)                b(0).sva#3                  5.1090 14.8910          
+      sobel:core/reg(g(2).sva#1)                g(2).sva#3                  3.4757 16.5243          
+      sobel:core/reg(g(0).sva#1)                g(0).sva#3                  5.1090 14.8910          
+      sobel:core/reg(r(2).sva#1)                r(2).sva#3                  3.4757 16.5243          
+      sobel:core/reg(r(0).sva#1)                r(0).sva#3                  5.1090 14.8910          
+      sobel:core/reg(FRAME:p#1.lpi#1)           mux#5.itm                  17.4604  2.5396          
+      sobel                                     vout:rsc.z                 20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                   19     1 
+    -                   16     9 
+    -                   15     3 
+    -                   13     2 
+    -                   12     9 
+    -                   10     4 
+    -                    8     4 
+    -                    6     9 
+    -                    5    15 
+    -                    4     3 
+    -                    2     5 
+    and                          
+    -                    3     3 
+    -                    2     5 
+    mul                          
+    -                   12     8 
+    -                   10     1 
+    -                    9     3 
+    mux                          
+    -                    2     6 
+    -                    1    12 
+    nand                         
+    -                    2     6 
+    nor                          
+    -                    2     2 
+    not                          
+    -                   10     9 
+    -                    3    12 
+    -                    1    21 
+    or                           
+    -                    4     3 
+    -                    3     1 
+    -                    2     4 
+    read_port                    
+    -                   90     1 
+    reg                          
+    -                   90     3 
+    -                   30     1 
+    -                   19     1 
+    -                   16     6 
+    -                   12     2 
+    -                   10     1 
+    -                    9     3 
+    -                    6     3 
+    -                    5     3 
+    -                    2     1 
+    -                    1     4 
+    write_port                   
+    -                   30     1 
+    
+  End of Report
diff --git a/Sobel/sobel.v4/rtl.v b/Sobel/sobel.v4/rtl.v
new file mode 100644
index 0000000..0a86b60
--- /dev/null
+++ b/Sobel/sobel.v4/rtl.v
@@ -0,0 +1,801 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:22:40 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  wire and_dcpl;
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [89:0] regs_regs_2_lpi_1_dfm;
+  reg [15:0] r_0_sva_1;
+  reg [15:0] g_0_sva_1;
+  reg [15:0] b_0_sva_1;
+  reg [15:0] r_2_sva_1;
+  reg [15:0] g_2_sva_1;
+  reg [15:0] b_2_sva_1;
+  reg [1:0] i_6_sva_1;
+  reg exit_FRAME_lpi_1_dfm_1;
+  reg [8:0] FRAME_mul_2_itm_1;
+  wire [17:0] nl_FRAME_mul_2_itm_1;
+  reg [5:0] FRAME_slc_green_10_itm_1;
+  reg [4:0] FRAME_acc_25_itm_1;
+  wire [6:0] nl_FRAME_acc_25_itm_1;
+  reg [11:0] FRAME_mul_3_itm_1;
+  wire [23:0] nl_FRAME_mul_3_itm_1;
+  reg [8:0] FRAME_mul_itm_1;
+  wire [17:0] nl_FRAME_mul_itm_1;
+  reg [5:0] FRAME_slc_red_10_itm_1;
+  reg [4:0] FRAME_acc_35_itm_1;
+  wire [6:0] nl_FRAME_acc_35_itm_1;
+  reg [9:0] FRAME_mul_1_itm_1;
+  wire [19:0] nl_FRAME_mul_1_itm_1;
+  reg [8:0] FRAME_mul_4_itm_1;
+  wire [17:0] nl_FRAME_mul_4_itm_1;
+  reg [5:0] FRAME_slc_blue_10_itm_1;
+  reg [4:0] FRAME_acc_40_itm_1;
+  wire [6:0] nl_FRAME_acc_40_itm_1;
+  reg [11:0] FRAME_mul_5_itm_1;
+  wire [23:0] nl_FRAME_mul_5_itm_1;
+  reg exit_FRAME_for_sva_1_st_1;
+  reg main_stage_0_2;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+  wire [11:0] FRAME_acc_3_psp_sva;
+  wire [12:0] nl_FRAME_acc_3_psp_sva;
+  wire [1:0] i_6_sva_2;
+  wire [2:0] nl_i_6_sva_2;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire exit_FRAME_for_lpi_1_dfm;
+  wire [89:0] regs_regs_2_lpi_1_dfm_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire exit_FRAME_lpi_1_dfm_1_mx0;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [15:0] blue_2_sva;
+  wire [16:0] nl_blue_2_sva;
+  wire [5:0] FRAME_acc_11_psp_sva;
+  wire [6:0] nl_FRAME_acc_11_psp_sva;
+  wire [15:0] red_2_sva;
+  wire [16:0] nl_red_2_sva;
+  wire [5:0] FRAME_acc_7_psp_sva;
+  wire [6:0] nl_FRAME_acc_7_psp_sva;
+  wire [4:0] FRAME_acc_28_sdt;
+  wire [5:0] nl_FRAME_acc_28_sdt;
+  wire [15:0] green_2_sva;
+  wire [16:0] nl_green_2_sva;
+  wire [5:0] FRAME_acc_9_psp_sva;
+  wire [6:0] nl_FRAME_acc_9_psp_sva;
+  wire [4:0] FRAME_acc_18_sdt;
+  wire [5:0] nl_FRAME_acc_18_sdt;
+  wire [4:0] FRAME_acc_13_sdt;
+  wire [5:0] nl_FRAME_acc_13_sdt;
+  wire [15:0] b_2_sva_3;
+  wire [16:0] nl_b_2_sva_3;
+  wire [15:0] b_0_sva_3;
+  wire [16:0] nl_b_0_sva_3;
+  wire [15:0] g_2_sva_3;
+  wire [16:0] nl_g_2_sva_3;
+  wire [15:0] g_0_sva_3;
+  wire [16:0] nl_g_0_sva_3;
+  wire [15:0] r_2_sva_3;
+  wire [16:0] nl_r_2_sva_3;
+  wire [15:0] r_0_sva_3;
+  wire [16:0] nl_r_0_sva_3;
+  wire FRAME_for_nor_cse;
+  wire [4:0] FRAME_acc_32_itm;
+  wire [5:0] nl_FRAME_acc_32_itm;
+  wire [4:0] FRAME_acc_17_itm;
+  wire [5:0] nl_FRAME_acc_17_itm;
+  wire [4:0] FRAME_acc_22_itm;
+  wire [5:0] nl_FRAME_acc_22_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_3_itm;
+
+  wire[15:0] FRAME_for_mux_10_nl;
+  wire[9:0] regs_operator_17_mux_nl;
+  wire[15:0] FRAME_for_mux_9_nl;
+  wire[9:0] regs_operator_11_mux_nl;
+  wire[15:0] FRAME_for_mux_8_nl;
+  wire[9:0] regs_operator_16_mux_nl;
+  wire[15:0] FRAME_for_mux_7_nl;
+  wire[9:0] regs_operator_10_mux_nl;
+  wire[15:0] FRAME_for_mux_6_nl;
+  wire[9:0] regs_operator_15_mux_nl;
+  wire[15:0] FRAME_for_mux_5_nl;
+  wire[9:0] regs_operator_9_mux_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_3_psp_sva = conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_2_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(FRAME_slc_green_10_itm_1) + conv_s2s_5_8(FRAME_acc_25_itm_1)))
+      + FRAME_mul_3_itm_1;
+  assign FRAME_acc_3_psp_sva = nl_FRAME_acc_3_psp_sva[11:0];
+  assign nl_FRAME_for_acc_itm = i_6_sva_2 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  assign nl_i_6_sva_2 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_2 = nl_i_6_sva_2[1:0];
+  assign i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm));
+  assign exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva;
+  assign regs_regs_2_lpi_1_dfm_mx0 = MUX_v_90_2_2({regs_regs_1_sva , regs_regs_2_lpi_1_dfm},
+      and_dcpl);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_dcpl);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_dcpl);
+  assign exit_FRAME_lpi_1_dfm_1_mx0 = MUX_s_1_2_2({(~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+      + 8'b10110101)))) , (exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm))},
+      FRAME_for_acc_itm[1]);
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign nl_blue_2_sva = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[39:30])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[39:30])
+      , 1'b1})))) + (b_2_sva_3[15:1])) , (readslicef_2_1_1((({(b_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + b_0_sva_3;
+  assign blue_2_sva = nl_blue_2_sva[15:0];
+  assign nl_FRAME_acc_11_psp_sva = ({1'b1 , ((FRAME_acc_28_sdt[4:1]) + 4'b1001) ,
+      (FRAME_acc_28_sdt[0])}) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (blue_2_sva[6:4]))
+      + conv_u2u_3_4(blue_2_sva[9:7])) + conv_u2u_3_5(blue_2_sva[3:1]));
+  assign FRAME_acc_11_psp_sva = nl_FRAME_acc_11_psp_sva[5:0];
+  assign nl_FRAME_acc_32_itm = ({1'b1 , (FRAME_acc_11_psp_sva[2:0]) , 1'b1}) + conv_u2u_4_5({(~
+      (FRAME_acc_11_psp_sva[5:3])) , (~ (FRAME_acc_11_psp_sva[5]))});
+  assign FRAME_acc_32_itm = nl_FRAME_acc_32_itm[4:0];
+  assign nl_red_2_sva = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[59:50])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[59:50])
+      , 1'b1})))) + (r_2_sva_3[15:1])) , (readslicef_2_1_1((({(r_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + r_0_sva_3;
+  assign red_2_sva = nl_red_2_sva[15:0];
+  assign nl_FRAME_acc_7_psp_sva = ({1'b1 , ((FRAME_acc_13_sdt[4:1]) + 4'b1001) ,
+      (FRAME_acc_13_sdt[0])}) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (red_2_sva[6:4]))
+      + conv_u2u_3_4(red_2_sva[9:7])) + conv_u2u_3_5(red_2_sva[3:1]));
+  assign FRAME_acc_7_psp_sva = nl_FRAME_acc_7_psp_sva[5:0];
+  assign nl_FRAME_acc_17_itm = ({1'b1 , (FRAME_acc_7_psp_sva[2:0]) , 1'b1}) + conv_u2u_4_5({(~
+      (FRAME_acc_7_psp_sva[5:3])) , (~ (FRAME_acc_7_psp_sva[5]))});
+  assign FRAME_acc_17_itm = nl_FRAME_acc_17_itm[4:0];
+  assign nl_FRAME_acc_28_sdt = conv_u2s_3_5(~ (blue_2_sva[12:10])) + conv_s2s_3_5(blue_2_sva[15:13]);
+  assign FRAME_acc_28_sdt = nl_FRAME_acc_28_sdt[4:0];
+  assign nl_green_2_sva = ({(conv_s2u_11_15(readslicef_12_11_1((conv_s2s_11_12({(~
+      (regs_regs_0_sva_dfm_mx0[49:40])) , 1'b1}) + conv_s2s_11_12({(regs_regs_2_lpi_1_dfm_mx0[49:40])
+      , 1'b1})))) + (g_2_sva_3[15:1])) , (readslicef_2_1_1((({(g_2_sva_3[0]) , 1'b1})
+      + 2'b11)))}) + g_0_sva_3;
+  assign green_2_sva = nl_green_2_sva[15:0];
+  assign nl_FRAME_acc_9_psp_sva = ({1'b1 , ((FRAME_acc_18_sdt[4:1]) + 4'b1001) ,
+      (FRAME_acc_18_sdt[0])}) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (green_2_sva[6:4]))
+      + conv_u2u_3_4(green_2_sva[9:7])) + conv_u2u_3_5(green_2_sva[3:1]));
+  assign FRAME_acc_9_psp_sva = nl_FRAME_acc_9_psp_sva[5:0];
+  assign nl_FRAME_acc_22_itm = ({1'b1 , (FRAME_acc_9_psp_sva[2:0]) , 1'b1}) + conv_u2u_4_5({(~
+      (FRAME_acc_9_psp_sva[5:3])) , (~ (FRAME_acc_9_psp_sva[5]))});
+  assign FRAME_acc_22_itm = nl_FRAME_acc_22_itm[4:0];
+  assign nl_FRAME_acc_18_sdt = conv_u2s_3_5(~ (green_2_sva[12:10])) + conv_s2s_3_5(green_2_sva[15:13]);
+  assign FRAME_acc_18_sdt = nl_FRAME_acc_18_sdt[4:0];
+  assign nl_FRAME_acc_13_sdt = conv_u2s_3_5(~ (red_2_sva[12:10])) + conv_s2s_3_5(red_2_sva[15:13]);
+  assign FRAME_acc_13_sdt = nl_FRAME_acc_13_sdt[4:0];
+  assign FRAME_for_mux_10_nl = MUX_v_16_2_2({b_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[69:60])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[69:60])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+      , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_mx0[69:60]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_b_2_sva_3 = (FRAME_for_mux_10_nl) + conv_s2s_11_16(conv_s2s_22_11(conv_s2s_10_11(regs_operator_17_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign b_2_sva_3 = nl_b_2_sva_3[15:0];
+  assign FRAME_for_mux_9_nl = MUX_v_16_2_2({b_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[9:0])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[9:0])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_11_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0]) ,
+      (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_mx0[9:0]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_b_0_sva_3 = (FRAME_for_mux_9_nl) + conv_s2s_12_16(conv_s2s_24_12(conv_s2s_10_12(regs_operator_11_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign b_0_sva_3 = nl_b_0_sva_3[15:0];
+  assign FRAME_for_mux_8_nl = MUX_v_16_2_2({g_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[79:70])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[79:70])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+      , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_mx0[79:70]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_g_2_sva_3 = (FRAME_for_mux_8_nl) + conv_s2s_11_16(conv_s2s_22_11(conv_s2s_10_11(regs_operator_16_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign g_2_sva_3 = nl_g_2_sva_3[15:0];
+  assign FRAME_for_mux_7_nl = MUX_v_16_2_2({g_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[19:10])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[19:10])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_10_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+      , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_mx0[19:10]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_g_0_sva_3 = (FRAME_for_mux_7_nl) + conv_s2s_12_16(conv_s2s_24_12(conv_s2s_10_12(regs_operator_10_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign g_0_sva_3 = nl_g_0_sva_3[15:0];
+  assign FRAME_for_mux_6_nl = MUX_v_16_2_2({r_2_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[89:80])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[89:80])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+      , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_mx0[89:80]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_r_2_sva_3 = (FRAME_for_mux_6_nl) + conv_s2s_11_16(conv_s2s_22_11(conv_s2s_10_11(regs_operator_15_mux_nl)
+      * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign r_2_sva_3 = nl_r_2_sva_3[15:0];
+  assign FRAME_for_mux_5_nl = MUX_v_16_2_2({r_0_sva_1 , (signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      (vin_rsc_mgc_in_wire_d[29:20])) , 1'b1}) + conv_s2s_11_12({(regs_regs_1_sva[29:20])
+      , 1'b1})))))}, exit_FRAME_for_lpi_1_dfm);
+  assign regs_operator_9_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+      , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_mx0[29:20]) , 10'b0},
+      i_6_lpi_1_dfm);
+  assign nl_r_0_sva_3 = (FRAME_for_mux_5_nl) + conv_s2s_12_16(conv_s2s_24_12(conv_s2s_10_12(regs_operator_9_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign r_0_sva_3 = nl_r_0_sva_3[15:0];
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_3_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) |
+      FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+  assign and_dcpl = ~(exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva);
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      FRAME_mul_itm_1 <= 9'b0;
+      FRAME_slc_red_10_itm_1 <= 6'b0;
+      FRAME_acc_35_itm_1 <= 5'b0;
+      FRAME_mul_1_itm_1 <= 10'b0;
+      FRAME_mul_4_itm_1 <= 9'b0;
+      FRAME_slc_blue_10_itm_1 <= 6'b0;
+      FRAME_acc_40_itm_1 <= 5'b0;
+      FRAME_mul_5_itm_1 <= 12'b0;
+      FRAME_mul_2_itm_1 <= 9'b0;
+      FRAME_slc_green_10_itm_1 <= 6'b0;
+      FRAME_acc_25_itm_1 <= 5'b0;
+      FRAME_mul_3_itm_1 <= 12'b0;
+      exit_FRAME_for_sva_1_st_1 <= 1'b0;
+      i_6_sva_1 <= 2'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_2_lpi_1_dfm <= 90'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_1 <= 1'b0;
+      b_2_sva_1 <= 16'b0;
+      b_0_sva_1 <= 16'b0;
+      g_2_sva_1 <= 16'b0;
+      g_0_sva_1 <= 16'b0;
+      r_2_sva_1 <= 16'b0;
+      r_0_sva_1 <= 16'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({(({(((conv_u2s_9_10(FRAME_mul_itm_1)
+            + conv_s2s_8_10(conv_u2s_6_8(FRAME_slc_red_10_itm_1) + conv_s2s_5_8(FRAME_acc_35_itm_1)))
+            + FRAME_mul_1_itm_1) | (signext_10_2(FRAME_acc_3_psp_sva[11:10]))) ,
+            (FRAME_acc_3_psp_sva[9:0]) , 10'b0}) | (signext_30_12(conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_4_itm_1)
+            + conv_s2s_8_10(conv_u2s_6_8(FRAME_slc_blue_10_itm_1) + conv_s2s_5_8(FRAME_acc_40_itm_1)))
+            + FRAME_mul_5_itm_1))) , vout_rsc_mgc_out_stdreg_d}, ~(exit_FRAME_for_sva_1_st_1
+            & main_stage_0_2));
+        FRAME_mul_itm_1 <= nl_FRAME_mul_itm_1[8:0];
+        FRAME_slc_red_10_itm_1 <= red_2_sva[9:4];
+        FRAME_acc_35_itm_1 <= nl_FRAME_acc_35_itm_1[4:0];
+        FRAME_mul_1_itm_1 <= nl_FRAME_mul_1_itm_1[9:0];
+        FRAME_mul_4_itm_1 <= nl_FRAME_mul_4_itm_1[8:0];
+        FRAME_slc_blue_10_itm_1 <= blue_2_sva[9:4];
+        FRAME_acc_40_itm_1 <= nl_FRAME_acc_40_itm_1[4:0];
+        FRAME_mul_5_itm_1 <= nl_FRAME_mul_5_itm_1[11:0];
+        FRAME_mul_2_itm_1 <= nl_FRAME_mul_2_itm_1[8:0];
+        FRAME_slc_green_10_itm_1 <= green_2_sva[9:4];
+        FRAME_acc_25_itm_1 <= nl_FRAME_acc_25_itm_1[4:0];
+        FRAME_mul_3_itm_1 <= nl_FRAME_mul_3_itm_1[11:0];
+        exit_FRAME_for_sva_1_st_1 <= ~ (FRAME_for_acc_itm[1]);
+        i_6_sva_1 <= i_6_sva_2;
+        exit_FRAME_1_sva <= (~ (FRAME_for_acc_itm[1])) & exit_FRAME_lpi_1_dfm_1_mx0;
+        main_stage_0_2 <= 1'b1;
+        regs_regs_2_lpi_1_dfm <= regs_regs_2_lpi_1_dfm_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_1 <= exit_FRAME_lpi_1_dfm_1_mx0;
+        b_2_sva_1 <= b_2_sva_3;
+        b_0_sva_1 <= b_0_sva_3;
+        g_2_sva_1 <= g_2_sva_3;
+        g_0_sva_1 <= g_0_sva_3;
+        r_2_sva_1 <= r_2_sva_3;
+        r_0_sva_1 <= r_0_sva_3;
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_sva_1 , FRAME_p_1_lpi_1_dfm},
+            FRAME_for_acc_itm[1]);
+      end
+    end
+  end
+  assign nl_FRAME_mul_itm_1  = conv_u2u_3_9(red_2_sva[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_35_itm_1  = (conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(~
+      (FRAME_acc_7_psp_sva[5])) , 1'b1 , (~((FRAME_acc_17_itm[4]) & (~ (red_2_sva[15]))))
+      , 1'b1}) + conv_u2u_3_5({(FRAME_acc_7_psp_sva[4:3]) , ((red_2_sva[15]) & (~
+      (FRAME_acc_17_itm[4])) & ((FRAME_acc_17_itm[3]) | (FRAME_acc_17_itm[2]) | (FRAME_acc_17_itm[1])
+      | (red_2_sva[0])))})))) + conv_u2u_3_5(~ (red_2_sva[9:7]))) + ({4'b1001 , (FRAME_acc_7_psp_sva[5])});
+  assign nl_FRAME_mul_1_itm_1  = conv_s2s_3_10(red_2_sva[15:13]) * 10'b111000111;
+  assign nl_FRAME_mul_4_itm_1  = conv_u2u_3_9(blue_2_sva[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_40_itm_1  = (conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(~
+      (FRAME_acc_11_psp_sva[5])) , 1'b1 , (~((FRAME_acc_32_itm[4]) & (~ (blue_2_sva[15]))))
+      , 1'b1}) + conv_u2u_3_5({(FRAME_acc_11_psp_sva[4:3]) , ((blue_2_sva[15]) &
+      (~ (FRAME_acc_32_itm[4])) & ((FRAME_acc_32_itm[3]) | (FRAME_acc_32_itm[2])
+      | (FRAME_acc_32_itm[1]) | (blue_2_sva[0])))})))) + conv_u2u_3_5(~ (blue_2_sva[9:7])))
+      + ({4'b1001 , (FRAME_acc_11_psp_sva[5])});
+  assign nl_FRAME_mul_5_itm_1  = conv_s2s_3_12(blue_2_sva[15:13]) * 12'b111000111;
+  assign nl_FRAME_mul_2_itm_1  = conv_u2u_3_9(green_2_sva[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_25_itm_1  = (conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(~
+      (FRAME_acc_9_psp_sva[5])) , 1'b1 , (~((FRAME_acc_22_itm[4]) & (~ (green_2_sva[15]))))
+      , 1'b1}) + conv_u2u_3_5({(FRAME_acc_9_psp_sva[4:3]) , ((green_2_sva[15]) &
+      (~ (FRAME_acc_22_itm[4])) & ((FRAME_acc_22_itm[3]) | (FRAME_acc_22_itm[2])
+      | (FRAME_acc_22_itm[1]) | (green_2_sva[0])))})))) + conv_u2u_3_5(~ (green_2_sva[9:7])))
+      + ({4'b1001 , (FRAME_acc_9_psp_sva[5])});
+  assign nl_FRAME_mul_3_itm_1  = conv_s2s_3_12(green_2_sva[15:13]) * 12'b111000111;
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_2_1_1;
+    input [1:0] vector;
+    reg [1:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_2_1_1 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [15:0] signext_16_11;
+    input [10:0] vector;
+  begin
+    signext_16_11= {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [9:0] signext_10_2;
+    input [1:0] vector;
+  begin
+    signext_10_2= {{8{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [29:0] signext_30_12;
+    input [11:0] vector;
+  begin
+    signext_30_12= {{18{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_11_15 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_15 = {{4{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2s_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2s_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_3_10 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_10 = {{7{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_3_12 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_12 = {{9{vector[2]}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v4/rtl.v.psr b/Sobel/sobel.v4/rtl.v.psr
new file mode 100644
index 0000000..abc150c
--- /dev/null
+++ b/Sobel/sobel.v4/rtl.v.psr
@@ -0,0 +1,289 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v4/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v4/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v4/rtl.v}} -format verilog
+   setup_design -design=sobel
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'sobel': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'sobel': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'sobel'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'sobel'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to vout_rsc_z(29:0)
+   report_timing -from en -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from vin_rsc_z(89:0) -to vout_rsc_z(29:0)
+   report_timing -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock clk] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock en] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'sobel'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'sobel'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v4 mapped.v]
+          puts "-- Writing mapped netlist for 'sobel' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v4 gate.v]
+          set gate_sdf [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v4 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/Sobel/sobel.v4/rtl.v.psr_timing b/Sobel/sobel.v4/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/Sobel/sobel.v4/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/Sobel/sobel.v4/rtl.v_order.txt b/Sobel/sobel.v4/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/Sobel/sobel.v4/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/Sobel/sobel.v4/rtl_mgc_ioport.v b/Sobel/sobel.v4/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v4/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v4/rtl_mgc_ioport_v2001.v b/Sobel/sobel.v4/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v4/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v4/schedule.gnt b/Sobel/sobel.v4/schedule.gnt
new file mode 100644
index 0000000..f5f6708
--- /dev/null
+++ b/Sobel/sobel.v4/schedule.gnt
@@ -0,0 +1,443 @@
+set a(0-1263) {NAME i:asn(i#6.lpi#1) TYPE ASSIGN PAR 0-1262 XREFS 10289 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{258 0 0-1277 {}}} CYCLES {}}
+set a(0-1264) {NAME b:asn(b(2).lpi#1) TYPE ASSIGN PAR 0-1262 XREFS 10290 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{258 0 0-1277 {}}} CYCLES {}}
+set a(0-1265) {NAME g:asn(g(2).lpi#1) TYPE ASSIGN PAR 0-1262 XREFS 10291 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{258 0 0-1277 {}}} CYCLES {}}
+set a(0-1266) {NAME r:asn(r(2).lpi#1) TYPE ASSIGN PAR 0-1262 XREFS 10292 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{258 0 0-1277 {}}} CYCLES {}}
+set a(0-1267) {NAME b:asn(b(0).lpi#1) TYPE ASSIGN PAR 0-1262 XREFS 10293 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{258 0 0-1277 {}}} CYCLES {}}
+set a(0-1268) {NAME g:asn(g(0).lpi#1) TYPE ASSIGN PAR 0-1262 XREFS 10294 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{258 0 0-1277 {}}} CYCLES {}}
+set a(0-1269) {NAME r:asn(r(0).lpi#1) TYPE ASSIGN PAR 0-1262 XREFS 10295 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{258 0 0-1277 {}}} CYCLES {}}
+set a(0-1270) {NAME regs.regs:asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-1262 XREFS 10296 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{258 0 0-1277 {}}} CYCLES {}}
+set a(0-1271) {NAME FRAME:asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-1262 XREFS 10297 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{258 0 0-1277 {}}} CYCLES {}}
+set a(0-1272) {NAME FRAME:for:asn(exit:FRAME:for.lpi#1)#1 TYPE ASSIGN PAR 0-1262 XREFS 10298 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{258 0 0-1277 {}}} CYCLES {}}
+set a(0-1273) {NAME FRAME:p:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-1262 XREFS 10299 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{258 0 0-1277 {}}} CYCLES {}}
+set a(0-1274) {NAME asn(regs.regs(1))#1 TYPE ASSIGN PAR 0-1262 XREFS 10300 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{258 0 0-1277 {}}} CYCLES {}}
+set a(0-1275) {NAME asn(regs.regs(0))#1 TYPE ASSIGN PAR 0-1262 XREFS 10301 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{258 0 0-1277 {}}} CYCLES {}}
+set a(0-1276) {NAME FRAME:for:asn(exit:FRAME#1) TYPE ASSIGN PAR 0-1262 XREFS 10302 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1277 {}}} SUCCS {{259 0 0-1277 {}}} CYCLES {}}
+set a(0-1278) {NAME FRAME:asn(exit:FRAME.sva#1) TYPE ASSIGN PAR 0-1277 XREFS 10303 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 2 0.702427075} PREDS {} SUCCS {{258 0 0-1680 {}} {258 0 0-1681 {}}} CYCLES {}}
+set a(0-1279) {NAME FRAME:p:asn(FRAME:p#1.sva#1) TYPE ASSIGN PAR 0-1277 XREFS 10304 LOC {0 1.0 1 0.9041241999999999 1 0.9041241999999999 3 0.47088512499999996} PREDS {} SUCCS {{258 0 0-1693 {}}} CYCLES {}}
+set a(0-1280) {NAME b:asn(b(2).sva) TYPE ASSIGN PAR 0-1277 XREFS 10305 LOC {0 1.0 1 0.286768825 1 0.286768825 2 0.080169675} PREDS {} SUCCS {{258 0 0-1439 {}}} CYCLES {}}
+set a(0-1281) {NAME g:asn(g(2).sva) TYPE ASSIGN PAR 0-1277 XREFS 10306 LOC {0 1.0 1 0.286768825 1 0.286768825 2 0.0634272} PREDS {} SUCCS {{258 0 0-1430 {}}} CYCLES {}}
+set a(0-1282) {NAME r:asn(r(2).sva) TYPE ASSIGN PAR 0-1277 XREFS 10307 LOC {0 1.0 1 0.286768825 1 0.286768825 2 0.061576175} PREDS {} SUCCS {{258 0 0-1421 {}}} CYCLES {}}
+set a(0-1283) {NAME b:asn(b(0).sva) TYPE ASSIGN PAR 0-1277 XREFS 10308 LOC {0 1.0 1 0.39666094999999996 1 0.39666094999999996 2 0.1900618} PREDS {} SUCCS {{258 0 0-1394 {}}} CYCLES {}}
+set a(0-1284) {NAME g:asn(g(0).sva) TYPE ASSIGN PAR 0-1277 XREFS 10309 LOC {0 1.0 1 0.39666094999999996 1 0.39666094999999996 2 0.173319325} PREDS {} SUCCS {{258 0 0-1384 {}}} CYCLES {}}
+set a(0-1285) {NAME r:asn(r(0).sva) TYPE ASSIGN PAR 0-1277 XREFS 10310 LOC {0 1.0 1 0.39666094999999996 1 0.39666094999999996 2 0.1714683} PREDS {} SUCCS {{258 0 0-1374 {}}} CYCLES {}}
+set a(0-1286) {NAME regs.regs:asn(regs.regs(0).sva#1) TYPE ASSIGN PAR 0-1277 XREFS 10311 LOC {0 1.0 1 0.0353171 1 0.0353171 1 0.725487675} PREDS {} SUCCS {{258 0 0-1352 {}}} CYCLES {}}
+set a(0-1287) {NAME FRAME:for:asn TYPE ASSIGN PAR 0-1277 XREFS 10312 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-1698 {}}} SUCCS {{259 0 0-1288 {}} {256 0 0-1698 {}}} CYCLES {}}
+set a(0-1288) {NAME FRAME:for:select TYPE SELECT PAR 0-1277 XREFS 10313 LOC {0 1.0 0 1.0 0 1.0 3 1.0} PREDS {{259 0 0-1287 {}}} SUCCS {} CYCLES {}}
+set a(0-1289) {NAME FRAME:asn TYPE ASSIGN PAR 0-1277 XREFS 10314 LOC {0 1.0 1 0.76845805 1 0.76845805 2 0.493945725} PREDS {{262 0 0-1698 {}}} SUCCS {{259 0 0-1290 {}} {256 0 0-1698 {}}} CYCLES {}}
+set a(0-1290) {NAME FRAME:not#28 TYPE NOT PAR 0-1277 XREFS 10315 LOC {1 0.0 1 0.76845805 1 0.76845805 2 0.493945725} PREDS {{259 0 0-1289 {}}} SUCCS {{259 0 0-1291 {}}} CYCLES {}}
+set a(0-1291) {NAME FRAME:for:exs TYPE SIGNEXTEND PAR 0-1277 XREFS 10316 LOC {1 0.0 1 0.76845805 1 0.76845805 2 0.493945725} PREDS {{259 0 0-1290 {}}} SUCCS {{259 0 0-1292 {}}} CYCLES {}}
+set a(0-1292) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(19,2) AREA_SCORE 13.87 QUANTITY 1 NAME FRAME:for:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-1277 XREFS 10317 LOC {1 0.0 1 0.76845805 1 0.76845805 1 0.784864781263854 2 0.510352456263854} PREDS {{262 0 0-1693 {}} {259 0 0-1291 {}}} SUCCS {{258 0 0-1673 {}} {258 0 0-1693 {}}} CYCLES {}}
+set a(0-1293) {NAME FRAME:for:asn#3 TYPE ASSIGN PAR 0-1277 XREFS 10318 LOC {0 1.0 1 0.0 1 0.0 1 0.725487675} PREDS {{262 0 0-1698 {}}} SUCCS {{259 0 0-1294 {}} {256 0 0-1698 {}}} CYCLES {}}
+set a(0-1294) {NAME FRAME:for:or TYPE OR PAR 0-1277 XREFS 10319 LOC {1 0.0 1 0.0 1 0.0 1 0.725487675} PREDS {{262 0 0-1696 {}} {259 0 0-1293 {}}} SUCCS {{259 0 0-1295 {}} {258 0 0-1352 {}} {258 0 0-1355 {}} {258 0 0-1357 {}} {258 0 0-1358 {}} {258 0 0-1376 {}} {258 0 0-1386 {}} {258 0 0-1396 {}} {258 0 0-1423 {}} {258 0 0-1432 {}} {258 0 0-1441 {}} {258 0 0-1678 {}} {256 0 0-1696 {}}} CYCLES {}}
+set a(0-1295) {NAME FRAME:for:select#1 TYPE SELECT PAR 0-1277 XREFS 10320 LOC {1 0.0 1 0.0353171 1 0.0353171 1 0.725487675} PREDS {{259 0 0-1294 {}}} SUCCS {{146 0 0-1296 {}} {146 0 0-1297 {}} {146 0 0-1298 {}} {146 0 0-1299 {}} {146 0 0-1300 {}} {146 0 0-1301 {}} {146 0 0-1302 {}} {146 0 0-1303 {}} {146 0 0-1304 {}} {146 0 0-1305 {}} {146 0 0-1306 {}} {146 0 0-1307 {}} {146 0 0-1308 {}} {146 0 0-1309 {}} {146 0 0-1310 {}} {146 0 0-1311 {}} {146 0 0-1312 {}} {146 0 0-1313 {}} {146 0 0-1314 {}} {146 0 0-1315 {}} {146 0 0-1316 {}} {146 0 0-1317 {}} {146 0 0-1318 {}} {146 0 0-1319 {}} {146 0 0-1320 {}} {146 0 0-1321 {}} {146 0 0-1322 {}} {146 0 0-1323 {}} {146 0 0-1324 {}} {146 0 0-1325 {}} {146 0 0-1326 {}} {146 0 0-1327 {}} {146 0 0-1328 {}} {146 0 0-1329 {}} {146 0 0-1330 {}} {146 0 0-1331 {}} {146 0 0-1332 {}} {146 0 0-1333 {}} {146 0 0-1334 {}} {146 0 0-1335 {}} {146 0 0-1336 {}} {146 0 0-1337 {}} {146 0 0-1338 {}} {146 0 0-1339 {}} {146 0 0-1340 {}} {146 0 0-1341 {}} {146 0 0-1342 {}} {146 0 0-1343 {}} {146 0 0-1344 {}} {146 0 0-1345 {}} {146 0 0-1346 {}} {146 0 0-1347 {}} {146 0 0-1348 {}} {146 0 0-1349 {}} {146 0 0-1350 {}}} CYCLES {}}
+set a(0-1296) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,90) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_read(vin:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-1277 XREFS 10321 LOC {1 0.0 1 0.0353171 1 0.0353171 1 0.0353171 1 0.725487675} PREDS {{146 0 0-1295 {}}} SUCCS {{259 0 0-1297 {}} {258 0 0-1306 {}} {258 0 0-1315 {}} {258 0 0-1324 {}} {258 0 0-1333 {}} {258 0 0-1342 {}} {258 0 0-1352 {}}} CYCLES {}}
+set a(0-1297) {NAME ACC1:slc(regs.regs(0))#3 TYPE READSLICE PAR 0-1277 XREFS 10322 LOC {1 0.0 1 0.0353171 1 0.0353171 2 0.0960975} PREDS {{146 0 0-1295 {}} {259 0 0-1296 {}}} SUCCS {{259 0 0-1298 {}}} CYCLES {}}
+set a(0-1298) {NAME ACC1:not TYPE NOT PAR 0-1277 XREFS 10323 LOC {1 0.0 1 0.32129015 1 0.32129015 2 0.0960975} PREDS {{146 0 0-1295 {}} {259 0 0-1297 {}}} SUCCS {{259 0 0-1299 {}}} CYCLES {}}
+set a(0-1299) {NAME ACC1:conc TYPE CONCATENATE PAR 0-1277 XREFS 10324 LOC {1 0.0 1 0.32129015 1 0.32129015 2 0.0960975} PREDS {{146 0 0-1295 {}} {259 0 0-1298 {}}} SUCCS {{258 0 0-1303 {}}} CYCLES {}}
+set a(0-1300) {NAME ACC1:asn TYPE ASSIGN PAR 0-1277 XREFS 10325 LOC {1 0.0 1 0.0353171 1 0.0353171 2 0.0960975} PREDS {{146 0 0-1295 {}} {262 0 0-1685 {}}} SUCCS {{259 0 0-1301 {}} {256 0 0-1685 {}}} CYCLES {}}
+set a(0-1301) {NAME ACC1:slc(regs.regs(2))#3 TYPE READSLICE PAR 0-1277 XREFS 10326 LOC {1 0.0 1 0.0353171 1 0.0353171 2 0.0960975} PREDS {{146 0 0-1295 {}} {259 0 0-1300 {}}} SUCCS {{259 0 0-1302 {}}} CYCLES {}}
+set a(0-1302) {NAME ACC1:conc#21 TYPE CONCATENATE PAR 0-1277 XREFS 10327 LOC {1 0.0 1 0.32129015 1 0.32129015 2 0.0960975} PREDS {{146 0 0-1295 {}} {259 0 0-1301 {}}} SUCCS {{259 0 0-1303 {}}} CYCLES {}}
+set a(0-1303) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#45 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1277 XREFS 10328 LOC {1 0.0 1 0.32129015 1 0.32129015 1 0.3966609063734284 2 0.17146825637342838} PREDS {{146 0 0-1295 {}} {258 0 0-1299 {}} {259 0 0-1302 {}}} SUCCS {{259 0 0-1304 {}}} CYCLES {}}
+set a(0-1304) {NAME ACC1:slc TYPE READSLICE PAR 0-1277 XREFS 10329 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 2 0.1714683} PREDS {{146 0 0-1295 {}} {259 0 0-1303 {}}} SUCCS {{259 0 0-1305 {}}} CYCLES {}}
+set a(0-1305) {NAME ACC1:exs#47 TYPE SIGNEXTEND PAR 0-1277 XREFS 10330 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 2 0.1714683} PREDS {{146 0 0-1295 {}} {259 0 0-1304 {}}} SUCCS {{258 0 0-1374 {}}} CYCLES {}}
+set a(0-1306) {NAME ACC1:slc(regs.regs(0))#4 TYPE READSLICE PAR 0-1277 XREFS 10331 LOC {1 0.0 1 0.0353171 1 0.0353171 2 0.097948525} PREDS {{146 0 0-1295 {}} {258 0 0-1296 {}}} SUCCS {{259 0 0-1307 {}}} CYCLES {}}
+set a(0-1307) {NAME ACC1:not#15 TYPE NOT PAR 0-1277 XREFS 10332 LOC {1 0.0 1 0.32129015 1 0.32129015 2 0.097948525} PREDS {{146 0 0-1295 {}} {259 0 0-1306 {}}} SUCCS {{259 0 0-1308 {}}} CYCLES {}}
+set a(0-1308) {NAME ACC1:conc#22 TYPE CONCATENATE PAR 0-1277 XREFS 10333 LOC {1 0.0 1 0.32129015 1 0.32129015 2 0.097948525} PREDS {{146 0 0-1295 {}} {259 0 0-1307 {}}} SUCCS {{258 0 0-1312 {}}} CYCLES {}}
+set a(0-1309) {NAME ACC1:asn#6 TYPE ASSIGN PAR 0-1277 XREFS 10334 LOC {1 0.0 1 0.0353171 1 0.0353171 2 0.097948525} PREDS {{146 0 0-1295 {}} {262 0 0-1685 {}}} SUCCS {{259 0 0-1310 {}} {256 0 0-1685 {}}} CYCLES {}}
+set a(0-1310) {NAME ACC1:slc(regs.regs(2))#4 TYPE READSLICE PAR 0-1277 XREFS 10335 LOC {1 0.0 1 0.0353171 1 0.0353171 2 0.097948525} PREDS {{146 0 0-1295 {}} {259 0 0-1309 {}}} SUCCS {{259 0 0-1311 {}}} CYCLES {}}
+set a(0-1311) {NAME ACC1:conc#23 TYPE CONCATENATE PAR 0-1277 XREFS 10336 LOC {1 0.0 1 0.32129015 1 0.32129015 2 0.097948525} PREDS {{146 0 0-1295 {}} {259 0 0-1310 {}}} SUCCS {{259 0 0-1312 {}}} CYCLES {}}
+set a(0-1312) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1277 XREFS 10337 LOC {1 0.0 1 0.32129015 1 0.32129015 1 0.3966609063734284 2 0.17331928137342836} PREDS {{146 0 0-1295 {}} {258 0 0-1308 {}} {259 0 0-1311 {}}} SUCCS {{259 0 0-1313 {}}} CYCLES {}}
+set a(0-1313) {NAME ACC1:slc#1 TYPE READSLICE PAR 0-1277 XREFS 10338 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 2 0.173319325} PREDS {{146 0 0-1295 {}} {259 0 0-1312 {}}} SUCCS {{259 0 0-1314 {}}} CYCLES {}}
+set a(0-1314) {NAME ACC1:exs#48 TYPE SIGNEXTEND PAR 0-1277 XREFS 10339 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 2 0.173319325} PREDS {{146 0 0-1295 {}} {259 0 0-1313 {}}} SUCCS {{258 0 0-1384 {}}} CYCLES {}}
+set a(0-1315) {NAME ACC1:slc(regs.regs(0))#5 TYPE READSLICE PAR 0-1277 XREFS 10340 LOC {1 0.0 1 0.0353171 1 0.0353171 2 0.114691} PREDS {{146 0 0-1295 {}} {258 0 0-1296 {}}} SUCCS {{259 0 0-1316 {}}} CYCLES {}}
+set a(0-1316) {NAME ACC1:not#16 TYPE NOT PAR 0-1277 XREFS 10341 LOC {1 0.0 1 0.32129015 1 0.32129015 2 0.114691} PREDS {{146 0 0-1295 {}} {259 0 0-1315 {}}} SUCCS {{259 0 0-1317 {}}} CYCLES {}}
+set a(0-1317) {NAME ACC1:conc#24 TYPE CONCATENATE PAR 0-1277 XREFS 10342 LOC {1 0.0 1 0.32129015 1 0.32129015 2 0.114691} PREDS {{146 0 0-1295 {}} {259 0 0-1316 {}}} SUCCS {{258 0 0-1321 {}}} CYCLES {}}
+set a(0-1318) {NAME ACC1:asn#7 TYPE ASSIGN PAR 0-1277 XREFS 10343 LOC {1 0.0 1 0.0353171 1 0.0353171 2 0.114691} PREDS {{146 0 0-1295 {}} {262 0 0-1685 {}}} SUCCS {{259 0 0-1319 {}} {256 0 0-1685 {}}} CYCLES {}}
+set a(0-1319) {NAME ACC1:slc(regs.regs(2))#5 TYPE READSLICE PAR 0-1277 XREFS 10344 LOC {1 0.0 1 0.0353171 1 0.0353171 2 0.114691} PREDS {{146 0 0-1295 {}} {259 0 0-1318 {}}} SUCCS {{259 0 0-1320 {}}} CYCLES {}}
+set a(0-1320) {NAME ACC1:conc#25 TYPE CONCATENATE PAR 0-1277 XREFS 10345 LOC {1 0.0 1 0.32129015 1 0.32129015 2 0.114691} PREDS {{146 0 0-1295 {}} {259 0 0-1319 {}}} SUCCS {{259 0 0-1321 {}}} CYCLES {}}
+set a(0-1321) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#46 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1277 XREFS 10346 LOC {1 0.0 1 0.32129015 1 0.32129015 1 0.3966609063734284 2 0.19006175637342837} PREDS {{146 0 0-1295 {}} {258 0 0-1317 {}} {259 0 0-1320 {}}} SUCCS {{259 0 0-1322 {}}} CYCLES {}}
+set a(0-1322) {NAME ACC1:slc#2 TYPE READSLICE PAR 0-1277 XREFS 10347 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 2 0.1900618} PREDS {{146 0 0-1295 {}} {259 0 0-1321 {}}} SUCCS {{259 0 0-1323 {}}} CYCLES {}}
+set a(0-1323) {NAME ACC1:exs#49 TYPE SIGNEXTEND PAR 0-1277 XREFS 10348 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 2 0.1900618} PREDS {{146 0 0-1295 {}} {259 0 0-1322 {}}} SUCCS {{258 0 0-1394 {}}} CYCLES {}}
+set a(0-1324) {NAME ACC1:slc(regs.regs(0)) TYPE READSLICE PAR 0-1277 XREFS 10349 LOC {1 0.0 1 0.0353171 1 0.0353171 1 0.9246291999999999} PREDS {{146 0 0-1295 {}} {258 0 0-1296 {}}} SUCCS {{259 0 0-1325 {}}} CYCLES {}}
+set a(0-1325) {NAME ACC1:not#12 TYPE NOT PAR 0-1277 XREFS 10350 LOC {1 0.0 1 0.211398025 1 0.211398025 1 0.9246291999999999} PREDS {{146 0 0-1295 {}} {259 0 0-1324 {}}} SUCCS {{259 0 0-1326 {}}} CYCLES {}}
+set a(0-1326) {NAME ACC1:conc#26 TYPE CONCATENATE PAR 0-1277 XREFS 10351 LOC {1 0.0 1 0.211398025 1 0.211398025 1 0.9246291999999999} PREDS {{146 0 0-1295 {}} {259 0 0-1325 {}}} SUCCS {{258 0 0-1330 {}}} CYCLES {}}
+set a(0-1327) {NAME ACC1:asn#8 TYPE ASSIGN PAR 0-1277 XREFS 10352 LOC {1 0.0 1 0.0353171 1 0.0353171 1 0.9246291999999999} PREDS {{146 0 0-1295 {}} {262 0 0-1685 {}}} SUCCS {{259 0 0-1328 {}} {256 0 0-1685 {}}} CYCLES {}}
+set a(0-1328) {NAME ACC1:slc(regs.regs(2)) TYPE READSLICE PAR 0-1277 XREFS 10353 LOC {1 0.0 1 0.0353171 1 0.0353171 1 0.9246291999999999} PREDS {{146 0 0-1295 {}} {259 0 0-1327 {}}} SUCCS {{259 0 0-1329 {}}} CYCLES {}}
+set a(0-1329) {NAME ACC1:conc#27 TYPE CONCATENATE PAR 0-1277 XREFS 10354 LOC {1 0.0 1 0.211398025 1 0.211398025 1 0.9246291999999999} PREDS {{146 0 0-1295 {}} {259 0 0-1328 {}}} SUCCS {{259 0 0-1330 {}}} CYCLES {}}
+set a(0-1330) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#47 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1277 XREFS 10355 LOC {1 0.0 1 0.211398025 1 0.211398025 1 0.28676878137342837 1 0.9999999563734283} PREDS {{146 0 0-1295 {}} {258 0 0-1326 {}} {259 0 0-1329 {}}} SUCCS {{259 0 0-1331 {}}} CYCLES {}}
+set a(0-1331) {NAME ACC1:slc#3 TYPE READSLICE PAR 0-1277 XREFS 10356 LOC {1 0.0753708 1 0.286768825 1 0.286768825 2 0.061576175} PREDS {{146 0 0-1295 {}} {259 0 0-1330 {}}} SUCCS {{259 0 0-1332 {}}} CYCLES {}}
+set a(0-1332) {NAME ACC1-3:exs TYPE SIGNEXTEND PAR 0-1277 XREFS 10357 LOC {1 0.0753708 1 0.286768825 1 0.286768825 2 0.061576175} PREDS {{146 0 0-1295 {}} {259 0 0-1331 {}}} SUCCS {{258 0 0-1421 {}}} CYCLES {}}
+set a(0-1333) {NAME ACC1:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-1277 XREFS 10358 LOC {1 0.0 1 0.0353171 1 0.0353171 1 0.9246291999999999} PREDS {{146 0 0-1295 {}} {258 0 0-1296 {}}} SUCCS {{259 0 0-1334 {}}} CYCLES {}}
+set a(0-1334) {NAME ACC1:not#13 TYPE NOT PAR 0-1277 XREFS 10359 LOC {1 0.0 1 0.211398025 1 0.211398025 1 0.9246291999999999} PREDS {{146 0 0-1295 {}} {259 0 0-1333 {}}} SUCCS {{259 0 0-1335 {}}} CYCLES {}}
+set a(0-1335) {NAME ACC1:conc#28 TYPE CONCATENATE PAR 0-1277 XREFS 10360 LOC {1 0.0 1 0.211398025 1 0.211398025 1 0.9246291999999999} PREDS {{146 0 0-1295 {}} {259 0 0-1334 {}}} SUCCS {{258 0 0-1339 {}}} CYCLES {}}
+set a(0-1336) {NAME ACC1:asn#9 TYPE ASSIGN PAR 0-1277 XREFS 10361 LOC {1 0.0 1 0.0353171 1 0.0353171 1 0.9246291999999999} PREDS {{146 0 0-1295 {}} {262 0 0-1685 {}}} SUCCS {{259 0 0-1337 {}} {256 0 0-1685 {}}} CYCLES {}}
+set a(0-1337) {NAME ACC1:slc(regs.regs(2))#1 TYPE READSLICE PAR 0-1277 XREFS 10362 LOC {1 0.0 1 0.0353171 1 0.0353171 1 0.9246291999999999} PREDS {{146 0 0-1295 {}} {259 0 0-1336 {}}} SUCCS {{259 0 0-1338 {}}} CYCLES {}}
+set a(0-1338) {NAME ACC1:conc#29 TYPE CONCATENATE PAR 0-1277 XREFS 10363 LOC {1 0.0 1 0.211398025 1 0.211398025 1 0.9246291999999999} PREDS {{146 0 0-1295 {}} {259 0 0-1337 {}}} SUCCS {{259 0 0-1339 {}}} CYCLES {}}
+set a(0-1339) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#48 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1277 XREFS 10364 LOC {1 0.0 1 0.211398025 1 0.211398025 1 0.28676878137342837 1 0.9999999563734283} PREDS {{146 0 0-1295 {}} {258 0 0-1335 {}} {259 0 0-1338 {}}} SUCCS {{259 0 0-1340 {}}} CYCLES {}}
+set a(0-1340) {NAME ACC1:slc#4 TYPE READSLICE PAR 0-1277 XREFS 10365 LOC {1 0.0753708 1 0.286768825 1 0.286768825 2 0.0634272} PREDS {{146 0 0-1295 {}} {259 0 0-1339 {}}} SUCCS {{259 0 0-1341 {}}} CYCLES {}}
+set a(0-1341) {NAME ACC1-3:exs#1 TYPE SIGNEXTEND PAR 0-1277 XREFS 10366 LOC {1 0.0753708 1 0.286768825 1 0.286768825 2 0.0634272} PREDS {{146 0 0-1295 {}} {259 0 0-1340 {}}} SUCCS {{258 0 0-1430 {}}} CYCLES {}}
+set a(0-1342) {NAME ACC1:slc(regs.regs(0))#2 TYPE READSLICE PAR 0-1277 XREFS 10367 LOC {1 0.0 1 0.0353171 1 0.0353171 2 0.004798875} PREDS {{146 0 0-1295 {}} {258 0 0-1296 {}}} SUCCS {{259 0 0-1343 {}}} CYCLES {}}
+set a(0-1343) {NAME ACC1:not#14 TYPE NOT PAR 0-1277 XREFS 10368 LOC {1 0.0 1 0.211398025 1 0.211398025 2 0.004798875} PREDS {{146 0 0-1295 {}} {259 0 0-1342 {}}} SUCCS {{259 0 0-1344 {}}} CYCLES {}}
+set a(0-1344) {NAME ACC1:conc#30 TYPE CONCATENATE PAR 0-1277 XREFS 10369 LOC {1 0.0 1 0.211398025 1 0.211398025 2 0.004798875} PREDS {{146 0 0-1295 {}} {259 0 0-1343 {}}} SUCCS {{258 0 0-1348 {}}} CYCLES {}}
+set a(0-1345) {NAME ACC1:asn#10 TYPE ASSIGN PAR 0-1277 XREFS 10370 LOC {1 0.0 1 0.0353171 1 0.0353171 2 0.004798875} PREDS {{146 0 0-1295 {}} {262 0 0-1685 {}}} SUCCS {{259 0 0-1346 {}} {256 0 0-1685 {}}} CYCLES {}}
+set a(0-1346) {NAME ACC1:slc(regs.regs(2))#2 TYPE READSLICE PAR 0-1277 XREFS 10371 LOC {1 0.0 1 0.0353171 1 0.0353171 2 0.004798875} PREDS {{146 0 0-1295 {}} {259 0 0-1345 {}}} SUCCS {{259 0 0-1347 {}}} CYCLES {}}
+set a(0-1347) {NAME ACC1:conc#31 TYPE CONCATENATE PAR 0-1277 XREFS 10372 LOC {1 0.0 1 0.211398025 1 0.211398025 2 0.004798875} PREDS {{146 0 0-1295 {}} {259 0 0-1346 {}}} SUCCS {{259 0 0-1348 {}}} CYCLES {}}
+set a(0-1348) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#49 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1277 XREFS 10373 LOC {1 0.0 1 0.211398025 1 0.211398025 1 0.28676878137342837 2 0.08016963137342836} PREDS {{146 0 0-1295 {}} {258 0 0-1344 {}} {259 0 0-1347 {}}} SUCCS {{259 0 0-1349 {}}} CYCLES {}}
+set a(0-1349) {NAME ACC1:slc#5 TYPE READSLICE PAR 0-1277 XREFS 10374 LOC {1 0.0753708 1 0.286768825 1 0.286768825 2 0.080169675} PREDS {{146 0 0-1295 {}} {259 0 0-1348 {}}} SUCCS {{259 0 0-1350 {}}} CYCLES {}}
+set a(0-1350) {NAME ACC1-3:exs#2 TYPE SIGNEXTEND PAR 0-1277 XREFS 10375 LOC {1 0.0753708 1 0.286768825 1 0.286768825 2 0.080169675} PREDS {{146 0 0-1295 {}} {259 0 0-1349 {}}} SUCCS {{258 0 0-1439 {}}} CYCLES {}}
+set a(0-1351) {NAME FRAME:for:asn#4 TYPE ASSIGN PAR 0-1277 XREFS 10376 LOC {0 1.0 1 0.0353171 1 0.0353171 1 0.725487675} PREDS {{262 0 0-1684 {}}} SUCCS {{259 0 0-1352 {}} {256 0 0-1684 {}}} CYCLES {}}
+set a(0-1352) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#2 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-1277 XREFS 10377 LOC {1 0.0 1 0.0353171 1 0.0353171 1 0.0583776625 1 0.7485482375} PREDS {{258 0 0-1294 {}} {258 0 0-1296 {}} {258 0 0-1286 {}} {259 0 0-1351 {}}} SUCCS {{258 0 0-1379 {}} {258 0 0-1389 {}} {258 0 0-1399 {}} {258 0 0-1426 {}} {258 0 0-1435 {}} {258 0 0-1444 {}} {258 0 0-1456 {}} {258 0 0-1470 {}} {258 0 0-1484 {}} {258 0 0-1684 {}}} CYCLES {}}
+set a(0-1353) {NAME FRAME:for:asn#5 TYPE ASSIGN PAR 0-1277 XREFS 10378 LOC {0 1.0 1 0.0353171 1 0.0353171 1 0.725487675} PREDS {{262 0 0-1684 {}}} SUCCS {{258 0 0-1355 {}} {256 0 0-1684 {}}} CYCLES {}}
+set a(0-1354) {NAME FRAME:for:asn#6 TYPE ASSIGN PAR 0-1277 XREFS 10379 LOC {0 1.0 1 0.0353171 1 0.0353171 1 0.725487675} PREDS {{262 0 0-1685 {}}} SUCCS {{259 0 0-1355 {}} {256 0 0-1685 {}}} CYCLES {}}
+set a(0-1355) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#3 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-1277 XREFS 10380 LOC {1 0.0 1 0.0353171 1 0.0353171 1 0.0583776625 1 0.7485482375} PREDS {{258 0 0-1294 {}} {258 0 0-1353 {}} {259 0 0-1354 {}}} SUCCS {{258 0 0-1378 {}} {258 0 0-1388 {}} {258 0 0-1398 {}} {258 0 0-1425 {}} {258 0 0-1434 {}} {258 0 0-1443 {}} {258 0 0-1685 {}}} CYCLES {}}
+set a(0-1356) {NAME FRAME:for:asn#7 TYPE ASSIGN PAR 0-1277 XREFS 10381 LOC {0 1.0 1 0.0353171 1 0.0353171 1 0.725487675} PREDS {{262 0 0-1685 {}}} SUCCS {{259 0 0-1357 {}} {256 0 0-1685 {}}} CYCLES {}}
+set a(0-1357) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#4 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-1277 XREFS 10382 LOC {1 0.0 1 0.0353171 1 0.0353171 1 0.0583776625 1 0.7485482375} PREDS {{258 0 0-1294 {}} {262 0 0-1686 {}} {259 0 0-1356 {}}} SUCCS {{258 0 0-1377 {}} {258 0 0-1387 {}} {258 0 0-1397 {}} {258 0 0-1424 {}} {258 0 0-1433 {}} {258 0 0-1442 {}} {258 0 0-1460 {}} {258 0 0-1474 {}} {258 0 0-1488 {}} {258 0 0-1686 {}}} CYCLES {}}
+set a(0-1358) {NAME not#15 TYPE NOT PAR 0-1277 XREFS 10383 LOC {1 0.0 1 0.041970925 1 0.041970925 1 0.7321415} PREDS {{258 0 0-1294 {}}} SUCCS {{259 0 0-1359 {}}} CYCLES {}}
+set a(0-1359) {NAME FRAME:for:exs#19 TYPE SIGNEXTEND PAR 0-1277 XREFS 10384 LOC {1 0.0 1 0.041970925 1 0.041970925 1 0.7321415} PREDS {{259 0 0-1358 {}}} SUCCS {{259 0 0-1360 {}}} CYCLES {}}
+set a(0-1360) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 2 NAME FRAME:for:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-1277 XREFS 10385 LOC {1 0.0 1 0.041970925 1 0.041970925 1 0.05837765626385391 1 0.748548231263854} PREDS {{262 0 0-1694 {}} {259 0 0-1359 {}}} SUCCS {{259 0 0-1361 {}} {258 0 0-1362 {}} {258 0 0-1363 {}} {258 0 0-1364 {}} {258 0 0-1365 {}} {258 0 0-1368 {}} {258 0 0-1370 {}} {258 0 0-1380 {}} {258 0 0-1390 {}} {258 0 0-1400 {}} {258 0 0-1404 {}} {258 0 0-1406 {}} {258 0 0-1427 {}} {258 0 0-1436 {}} {258 0 0-1445 {}} {258 0 0-1448 {}} {256 0 0-1694 {}}} CYCLES {}}
+set a(0-1361) {NAME slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-1277 XREFS 10386 LOC {1 0.016406775 1 0.0583777 1 0.0583777 2 0.001604975} PREDS {{259 0 0-1360 {}}} SUCCS {{258 0 0-1369 {}}} CYCLES {}}
+set a(0-1362) {NAME slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-1277 XREFS 10387 LOC {1 0.016406775 1 0.0583777 1 0.0583777 2 0.001604975} PREDS {{258 0 0-1360 {}}} SUCCS {{258 0 0-1366 {}}} CYCLES {}}
+set a(0-1363) {NAME slc(i#6.lpi#1.dfm)#2 TYPE READSLICE PAR 0-1277 XREFS 10388 LOC {1 0.016406775 1 0.0583777 1 0.0583777 2 0.001604975} PREDS {{258 0 0-1360 {}}} SUCCS {{258 0 0-1372 {}}} CYCLES {}}
+set a(0-1364) {NAME slc(i#6.lpi#1.dfm)#3 TYPE READSLICE PAR 0-1277 XREFS 10389 LOC {1 0.016406775 1 0.0583777 1 0.0583777 3 1.0} PREDS {{258 0 0-1360 {}}} SUCCS {} CYCLES {}}
+set a(0-1365) {NAME FRAME:for:slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-1277 XREFS 10390 LOC {1 0.016406775 1 0.0583777 1 0.0583777 2 0.001604975} PREDS {{258 0 0-1360 {}}} SUCCS {{258 0 0-1367 {}}} CYCLES {}}
+set a(0-1366) {NAME FRAME:for:not#1 TYPE NOT PAR 0-1277 XREFS 10391 LOC {1 0.016406775 1 0.0583777 1 0.0583777 2 0.001604975} PREDS {{258 0 0-1362 {}}} SUCCS {{259 0 0-1367 {}}} CYCLES {}}
+set a(0-1367) {NAME FRAME:for:nand TYPE NAND PAR 0-1277 XREFS 10392 LOC {1 0.016406775 1 0.0583777 1 0.0583777 2 0.001604975} PREDS {{258 0 0-1365 {}} {259 0 0-1366 {}}} SUCCS {{258 0 0-1373 {}}} CYCLES {}}
+set a(0-1368) {NAME FRAME:for:slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-1277 XREFS 10393 LOC {1 0.016406775 1 0.0583777 1 0.0583777 2 0.001604975} PREDS {{258 0 0-1360 {}}} SUCCS {{259 0 0-1369 {}}} CYCLES {}}
+set a(0-1369) {NAME FRAME:for:nor TYPE NOR PAR 0-1277 XREFS 10394 LOC {1 0.016406775 1 0.0583777 1 0.0583777 2 0.001604975} PREDS {{258 0 0-1361 {}} {259 0 0-1368 {}}} SUCCS {{258 0 0-1373 {}}} CYCLES {}}
+set a(0-1370) {NAME FRAME:for:slc(i#6.lpi#1.dfm)#2 TYPE READSLICE PAR 0-1277 XREFS 10395 LOC {1 0.016406775 1 0.0583777 1 0.0583777 2 0.001604975} PREDS {{258 0 0-1360 {}}} SUCCS {{259 0 0-1371 {}}} CYCLES {}}
+set a(0-1371) {NAME FRAME:for:not#2 TYPE NOT PAR 0-1277 XREFS 10396 LOC {1 0.016406775 1 0.0583777 1 0.0583777 2 0.001604975} PREDS {{259 0 0-1370 {}}} SUCCS {{259 0 0-1372 {}}} CYCLES {}}
+set a(0-1372) {NAME FRAME:for:and#3 TYPE AND PAR 0-1277 XREFS 10397 LOC {1 0.016406775 1 0.0583777 1 0.0583777 2 0.001604975} PREDS {{258 0 0-1363 {}} {259 0 0-1371 {}}} SUCCS {{259 0 0-1373 {}}} CYCLES {}}
+set a(0-1373) {NAME FRAME:for:or#3 TYPE OR PAR 0-1277 XREFS 10398 LOC {1 0.016406775 1 0.0583777 1 0.0583777 2 0.001604975} PREDS {{258 0 0-1369 {}} {258 0 0-1367 {}} {259 0 0-1372 {}}} SUCCS {{258 0 0-1381 {}} {258 0 0-1391 {}} {258 0 0-1401 {}}} CYCLES {}}
+set a(0-1374) {NAME FRAME:for:slc(r(0).sva) TYPE READSLICE PAR 0-1277 XREFS 10399 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 2 0.1714683} PREDS {{258 0 0-1305 {}} {258 0 0-1285 {}}} SUCCS {{259 0 0-1375 {}}} CYCLES {}}
+set a(0-1375) {NAME FRAME:for:exs#20 TYPE SIGNEXTEND PAR 0-1277 XREFS 10400 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 2 0.1714683} PREDS {{259 0 0-1374 {}}} SUCCS {{259 0 0-1376 {}}} CYCLES {}}
+set a(0-1376) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#5 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-1277 XREFS 10401 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 1 0.41972151249999995 2 0.19452886249999998} PREDS {{258 0 0-1294 {}} {262 0 0-1687 {}} {259 0 0-1375 {}}} SUCCS {{258 0 0-1383 {}} {256 0 0-1687 {}}} CYCLES {}}
+set a(0-1377) {NAME {regs.operator[]#9:slc(regs.regs(2))} TYPE READSLICE PAR 0-1277 XREFS 10402 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.9414722} PREDS {{258 0 0-1357 {}}} SUCCS {{258 0 0-1380 {}}} CYCLES {}}
+set a(0-1378) {NAME {regs.operator[]#9:slc(regs.regs(1))} TYPE READSLICE PAR 0-1277 XREFS 10403 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.9414722} PREDS {{258 0 0-1355 {}}} SUCCS {{258 0 0-1380 {}}} CYCLES {}}
+set a(0-1379) {NAME {regs.operator[]#9:slc(regs.regs(0))} TYPE READSLICE PAR 0-1277 XREFS 10404 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.9414722} PREDS {{258 0 0-1352 {}}} SUCCS {{259 0 0-1380 {}}} CYCLES {}}
+set a(0-1380) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#9:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1277 XREFS 10405 LOC {1 0.0230606 1 0.16826982499999998 1 0.16826982499999998 1 0.22679757499999997 1 0.99999995} PREDS {{258 0 0-1360 {}} {258 0 0-1378 {}} {258 0 0-1377 {}} {259 0 0-1379 {}}} SUCCS {{258 0 0-1382 {}}} CYCLES {}}
+set a(0-1381) {NAME FRAME:for:conc#5 TYPE CONCATENATE PAR 0-1277 XREFS 10406 LOC {1 0.016406775 1 0.226797625 1 0.226797625 2 0.001604975} PREDS {{258 0 0-1373 {}}} SUCCS {{259 0 0-1382 {}}} CYCLES {}}
+set a(0-1382) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-1277 XREFS 10407 LOC {1 0.08158839999999999 1 0.226797625 1 0.226797625 1 0.4197214875 2 0.1945288375} PREDS {{258 0 0-1380 {}} {259 0 0-1381 {}}} SUCCS {{259 0 0-1383 {}}} CYCLES {}}
+set a(0-1383) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#1 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-1277 XREFS 10408 LOC {1 0.274512325 1 0.41972155 1 0.41972155 1 0.5257232913378799 2 0.3005306413378799} PREDS {{258 0 0-1376 {}} {259 0 0-1382 {}}} SUCCS {{258 0 0-1468 {}} {258 0 0-1687 {}}} CYCLES {}}
+set a(0-1384) {NAME FRAME:for:slc(g(0).sva) TYPE READSLICE PAR 0-1277 XREFS 10409 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 2 0.173319325} PREDS {{258 0 0-1314 {}} {258 0 0-1284 {}}} SUCCS {{259 0 0-1385 {}}} CYCLES {}}
+set a(0-1385) {NAME FRAME:for:exs#21 TYPE SIGNEXTEND PAR 0-1277 XREFS 10410 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 2 0.173319325} PREDS {{259 0 0-1384 {}}} SUCCS {{259 0 0-1386 {}}} CYCLES {}}
+set a(0-1386) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#7 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-1277 XREFS 10411 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 1 0.41972151249999995 2 0.1963798875} PREDS {{258 0 0-1294 {}} {262 0 0-1689 {}} {259 0 0-1385 {}}} SUCCS {{258 0 0-1393 {}} {256 0 0-1689 {}}} CYCLES {}}
+set a(0-1387) {NAME {regs.operator[]#10:slc(regs.regs(2))} TYPE READSLICE PAR 0-1277 XREFS 10412 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.9414722} PREDS {{258 0 0-1357 {}}} SUCCS {{258 0 0-1390 {}}} CYCLES {}}
+set a(0-1388) {NAME {regs.operator[]#10:slc(regs.regs(1))} TYPE READSLICE PAR 0-1277 XREFS 10413 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.9414722} PREDS {{258 0 0-1355 {}}} SUCCS {{258 0 0-1390 {}}} CYCLES {}}
+set a(0-1389) {NAME {regs.operator[]#10:slc(regs.regs(0))} TYPE READSLICE PAR 0-1277 XREFS 10414 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.9414722} PREDS {{258 0 0-1352 {}}} SUCCS {{259 0 0-1390 {}}} CYCLES {}}
+set a(0-1390) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#10:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1277 XREFS 10415 LOC {1 0.0230606 1 0.16826982499999998 1 0.16826982499999998 1 0.22679757499999997 1 0.99999995} PREDS {{258 0 0-1360 {}} {258 0 0-1388 {}} {258 0 0-1387 {}} {259 0 0-1389 {}}} SUCCS {{258 0 0-1392 {}}} CYCLES {}}
+set a(0-1391) {NAME FRAME:for:conc#6 TYPE CONCATENATE PAR 0-1277 XREFS 10416 LOC {1 0.016406775 1 0.226797625 1 0.226797625 2 0.003456} PREDS {{258 0 0-1373 {}}} SUCCS {{259 0 0-1392 {}}} CYCLES {}}
+set a(0-1392) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#1 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-1277 XREFS 10417 LOC {1 0.08158839999999999 1 0.226797625 1 0.226797625 1 0.4197214875 2 0.19637986249999997} PREDS {{258 0 0-1390 {}} {259 0 0-1391 {}}} SUCCS {{259 0 0-1393 {}}} CYCLES {}}
+set a(0-1393) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#2 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-1277 XREFS 10418 LOC {1 0.274512325 1 0.41972155 1 0.41972155 1 0.5257232913378799 2 0.30238166633787983} PREDS {{258 0 0-1386 {}} {259 0 0-1392 {}}} SUCCS {{258 0 0-1482 {}} {258 0 0-1689 {}}} CYCLES {}}
+set a(0-1394) {NAME FRAME:for:slc(b(0).sva) TYPE READSLICE PAR 0-1277 XREFS 10419 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 2 0.1900618} PREDS {{258 0 0-1323 {}} {258 0 0-1283 {}}} SUCCS {{259 0 0-1395 {}}} CYCLES {}}
+set a(0-1395) {NAME FRAME:for:exs#22 TYPE SIGNEXTEND PAR 0-1277 XREFS 10420 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 2 0.1900618} PREDS {{259 0 0-1394 {}}} SUCCS {{259 0 0-1396 {}}} CYCLES {}}
+set a(0-1396) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#9 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-1277 XREFS 10421 LOC {1 0.0753708 1 0.39666094999999996 1 0.39666094999999996 1 0.41972151249999995 2 0.2131223625} PREDS {{258 0 0-1294 {}} {262 0 0-1691 {}} {259 0 0-1395 {}}} SUCCS {{258 0 0-1403 {}} {256 0 0-1691 {}}} CYCLES {}}
+set a(0-1397) {NAME {regs.operator[]#11:slc(regs.regs(2))} TYPE READSLICE PAR 0-1277 XREFS 10422 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.9414722} PREDS {{258 0 0-1357 {}}} SUCCS {{258 0 0-1400 {}}} CYCLES {}}
+set a(0-1398) {NAME {regs.operator[]#11:slc(regs.regs(1))} TYPE READSLICE PAR 0-1277 XREFS 10423 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.9414722} PREDS {{258 0 0-1355 {}}} SUCCS {{258 0 0-1400 {}}} CYCLES {}}
+set a(0-1399) {NAME {regs.operator[]#11:slc(regs.regs(0))} TYPE READSLICE PAR 0-1277 XREFS 10424 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.9414722} PREDS {{258 0 0-1352 {}}} SUCCS {{259 0 0-1400 {}}} CYCLES {}}
+set a(0-1400) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#11:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1277 XREFS 10425 LOC {1 0.0230606 1 0.16826982499999998 1 0.16826982499999998 1 0.22679757499999997 1 0.99999995} PREDS {{258 0 0-1360 {}} {258 0 0-1398 {}} {258 0 0-1397 {}} {259 0 0-1399 {}}} SUCCS {{258 0 0-1402 {}}} CYCLES {}}
+set a(0-1401) {NAME FRAME:for:conc#7 TYPE CONCATENATE PAR 0-1277 XREFS 10426 LOC {1 0.016406775 1 0.226797625 1 0.226797625 2 0.020198475} PREDS {{258 0 0-1373 {}}} SUCCS {{259 0 0-1402 {}}} CYCLES {}}
+set a(0-1402) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#2 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-1277 XREFS 10427 LOC {1 0.08158839999999999 1 0.226797625 1 0.226797625 1 0.4197214875 2 0.21312233749999998} PREDS {{258 0 0-1400 {}} {259 0 0-1401 {}}} SUCCS {{259 0 0-1403 {}}} CYCLES {}}
+set a(0-1403) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#3 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-1277 XREFS 10428 LOC {1 0.274512325 1 0.41972155 1 0.41972155 1 0.5257232913378799 2 0.31912414133787986} PREDS {{258 0 0-1396 {}} {259 0 0-1402 {}}} SUCCS {{258 0 0-1496 {}} {258 0 0-1691 {}}} CYCLES {}}
+set a(0-1404) {NAME i:slc(i#3)#1 TYPE READSLICE PAR 0-1277 XREFS 10429 LOC {1 0.016406775 1 0.0583777 1 0.0583777 1 0.773926825} PREDS {{258 0 0-1360 {}}} SUCCS {{259 0 0-1405 {}}} CYCLES {}}
+set a(0-1405) {NAME FRAME:for:not#4 TYPE NOT PAR 0-1277 XREFS 10430 LOC {1 0.016406775 1 0.0583777 1 0.0583777 1 0.773926825} PREDS {{259 0 0-1404 {}}} SUCCS {{258 0 0-1407 {}}} CYCLES {}}
+set a(0-1406) {NAME i:slc(i#3)#2 TYPE READSLICE PAR 0-1277 XREFS 10431 LOC {1 0.016406775 1 0.0583777 1 0.0583777 1 0.773926825} PREDS {{258 0 0-1360 {}}} SUCCS {{259 0 0-1407 {}}} CYCLES {}}
+set a(0-1407) {NAME FRAME:for:conc TYPE CONCATENATE PAR 0-1277 XREFS 10432 LOC {1 0.016406775 1 0.0583777 1 0.0583777 1 0.773926825} PREDS {{258 0 0-1405 {}} {259 0 0-1406 {}}} SUCCS {{259 0 0-1408 {}} {258 0 0-1409 {}} {258 0 0-1410 {}} {258 0 0-1411 {}} {258 0 0-1412 {}} {258 0 0-1416 {}}} CYCLES {}}
+set a(0-1408) {NAME slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-1277 XREFS 10433 LOC {1 0.016406775 1 0.0583777 1 0.0583777 3 1.0} PREDS {{259 0 0-1407 {}}} SUCCS {} CYCLES {}}
+set a(0-1409) {NAME slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-1277 XREFS 10434 LOC {1 0.016406775 1 0.0583777 1 0.0583777 3 1.0} PREDS {{258 0 0-1407 {}}} SUCCS {} CYCLES {}}
+set a(0-1410) {NAME slc(FRAME:for:conc.tmp)#2 TYPE READSLICE PAR 0-1277 XREFS 10435 LOC {1 0.016406775 1 0.0583777 1 0.0583777 1 0.7903336} PREDS {{258 0 0-1407 {}}} SUCCS {{258 0 0-1418 {}}} CYCLES {}}
+set a(0-1411) {NAME slc(FRAME:for:conc.tmp)#3 TYPE READSLICE PAR 0-1277 XREFS 10436 LOC {1 0.016406775 1 0.0583777 1 0.0583777 1 0.773926825} PREDS {{258 0 0-1407 {}}} SUCCS {{258 0 0-1413 {}}} CYCLES {}}
+set a(0-1412) {NAME FRAME:for:slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-1277 XREFS 10437 LOC {1 0.016406775 1 0.0583777 1 0.0583777 1 0.773926825} PREDS {{258 0 0-1407 {}}} SUCCS {{259 0 0-1413 {}}} CYCLES {}}
+set a(0-1413) {NAME FRAME:for:nand#1 TYPE NAND PAR 0-1277 XREFS 10438 LOC {1 0.016406775 1 0.0583777 1 0.0583777 1 0.773926825} PREDS {{258 0 0-1411 {}} {259 0 0-1412 {}}} SUCCS {{259 0 0-1414 {}}} CYCLES {}}
+set a(0-1414) {NAME FRAME:for:exs#26 TYPE SIGNEXTEND PAR 0-1277 XREFS 10439 LOC {1 0.016406775 1 0.08375624999999999 1 0.08375624999999999 1 0.773926825} PREDS {{259 0 0-1413 {}}} SUCCS {{259 0 0-1415 {}}} CYCLES {}}
+set a(0-1415) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 2 NAME FRAME:for:and#4 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-1277 XREFS 10440 LOC {1 0.016406775 1 0.08375624999999999 1 0.08375624999999999 1 0.1001629812638539 1 0.7903335562638539} PREDS {{259 0 0-1414 {}}} SUCCS {{258 0 0-1420 {}}} CYCLES {}}
+set a(0-1416) {NAME FRAME:for:slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-1277 XREFS 10441 LOC {1 0.016406775 1 0.0583777 1 0.0583777 1 0.7903336} PREDS {{258 0 0-1407 {}}} SUCCS {{259 0 0-1417 {}}} CYCLES {}}
+set a(0-1417) {NAME FRAME:for:not#3 TYPE NOT PAR 0-1277 XREFS 10442 LOC {1 0.016406775 1 0.0583777 1 0.0583777 1 0.7903336} PREDS {{259 0 0-1416 {}}} SUCCS {{259 0 0-1418 {}}} CYCLES {}}
+set a(0-1418) {NAME FRAME:for:and#5 TYPE AND PAR 0-1277 XREFS 10443 LOC {1 0.016406775 1 0.0583777 1 0.0583777 1 0.7903336} PREDS {{258 0 0-1410 {}} {259 0 0-1417 {}}} SUCCS {{259 0 0-1419 {}}} CYCLES {}}
+set a(0-1419) {NAME FRAME:for:exs#27 TYPE SIGNEXTEND PAR 0-1277 XREFS 10444 LOC {1 0.016406775 1 0.10016302499999999 1 0.10016302499999999 1 0.7903336} PREDS {{259 0 0-1418 {}}} SUCCS {{259 0 0-1420 {}}} CYCLES {}}
+set a(0-1420) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(2,2) AREA_SCORE 1.46 QUANTITY 1 NAME FRAME:for:or#4 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-1277 XREFS 10445 LOC {1 0.03281355 1 0.10016302499999999 1 0.10016302499999999 1 0.11690545610773884 1 0.8070760311077388} PREDS {{258 0 0-1415 {}} {259 0 0-1419 {}}} SUCCS {{258 0 0-1428 {}} {258 0 0-1437 {}} {258 0 0-1446 {}}} CYCLES {}}
+set a(0-1421) {NAME FRAME:for:slc(r(2).sva) TYPE READSLICE PAR 0-1277 XREFS 10446 LOC {1 0.0753708 1 0.286768825 1 0.286768825 2 0.061576175} PREDS {{258 0 0-1332 {}} {258 0 0-1282 {}}} SUCCS {{259 0 0-1422 {}}} CYCLES {}}
+set a(0-1422) {NAME FRAME:for:exs#23 TYPE SIGNEXTEND PAR 0-1277 XREFS 10447 LOC {1 0.0753708 1 0.286768825 1 0.286768825 2 0.061576175} PREDS {{259 0 0-1421 {}}} SUCCS {{259 0 0-1423 {}}} CYCLES {}}
+set a(0-1423) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#6 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-1277 XREFS 10448 LOC {1 0.0753708 1 0.286768825 1 0.286768825 1 0.3098293875 2 0.0846367375} PREDS {{258 0 0-1294 {}} {262 0 0-1688 {}} {259 0 0-1422 {}}} SUCCS {{258 0 0-1429 {}} {256 0 0-1688 {}}} CYCLES {}}
+set a(0-1424) {NAME {regs.operator[]#15:slc(regs.regs(2))} TYPE READSLICE PAR 0-1277 XREFS 10449 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.748548275} PREDS {{258 0 0-1357 {}}} SUCCS {{258 0 0-1427 {}}} CYCLES {}}
+set a(0-1425) {NAME {regs.operator[]#15:slc(regs.regs(1))} TYPE READSLICE PAR 0-1277 XREFS 10450 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.748548275} PREDS {{258 0 0-1355 {}}} SUCCS {{258 0 0-1427 {}}} CYCLES {}}
+set a(0-1426) {NAME {regs.operator[]#15:slc(regs.regs(0))} TYPE READSLICE PAR 0-1277 XREFS 10451 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.748548275} PREDS {{258 0 0-1352 {}}} SUCCS {{259 0 0-1427 {}}} CYCLES {}}
+set a(0-1427) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#15:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1277 XREFS 10452 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.11690545 1 0.807076025} PREDS {{258 0 0-1360 {}} {258 0 0-1425 {}} {258 0 0-1424 {}} {259 0 0-1426 {}}} SUCCS {{259 0 0-1428 {}}} CYCLES {}}
+set a(0-1428) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#6 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-1277 XREFS 10453 LOC {1 0.08158839999999999 1 0.1169055 1 0.1169055 1 0.3098293625 1 0.9999999374999999} PREDS {{258 0 0-1420 {}} {259 0 0-1427 {}}} SUCCS {{259 0 0-1429 {}}} CYCLES {}}
+set a(0-1429) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#10 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-1277 XREFS 10454 LOC {1 0.274512325 1 0.309829425 1 0.309829425 1 0.41583116633787987 2 0.19063851633787987} PREDS {{258 0 0-1423 {}} {259 0 0-1428 {}}} SUCCS {{258 0 0-1455 {}} {258 0 0-1688 {}}} CYCLES {}}
+set a(0-1430) {NAME FRAME:for:slc(g(2).sva) TYPE READSLICE PAR 0-1277 XREFS 10455 LOC {1 0.0753708 1 0.286768825 1 0.286768825 2 0.0634272} PREDS {{258 0 0-1341 {}} {258 0 0-1281 {}}} SUCCS {{259 0 0-1431 {}}} CYCLES {}}
+set a(0-1431) {NAME FRAME:for:exs#24 TYPE SIGNEXTEND PAR 0-1277 XREFS 10456 LOC {1 0.0753708 1 0.286768825 1 0.286768825 2 0.0634272} PREDS {{259 0 0-1430 {}}} SUCCS {{259 0 0-1432 {}}} CYCLES {}}
+set a(0-1432) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#8 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-1277 XREFS 10457 LOC {1 0.0753708 1 0.286768825 1 0.286768825 1 0.3098293875 2 0.08648776250000001} PREDS {{258 0 0-1294 {}} {262 0 0-1690 {}} {259 0 0-1431 {}}} SUCCS {{258 0 0-1438 {}} {256 0 0-1690 {}}} CYCLES {}}
+set a(0-1433) {NAME {regs.operator[]#16:slc(regs.regs(2))} TYPE READSLICE PAR 0-1277 XREFS 10458 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.748548275} PREDS {{258 0 0-1357 {}}} SUCCS {{258 0 0-1436 {}}} CYCLES {}}
+set a(0-1434) {NAME {regs.operator[]#16:slc(regs.regs(1))} TYPE READSLICE PAR 0-1277 XREFS 10459 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.748548275} PREDS {{258 0 0-1355 {}}} SUCCS {{258 0 0-1436 {}}} CYCLES {}}
+set a(0-1435) {NAME {regs.operator[]#16:slc(regs.regs(0))} TYPE READSLICE PAR 0-1277 XREFS 10460 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.748548275} PREDS {{258 0 0-1352 {}}} SUCCS {{259 0 0-1436 {}}} CYCLES {}}
+set a(0-1436) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#16:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1277 XREFS 10461 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.11690545 1 0.807076025} PREDS {{258 0 0-1360 {}} {258 0 0-1434 {}} {258 0 0-1433 {}} {259 0 0-1435 {}}} SUCCS {{259 0 0-1437 {}}} CYCLES {}}
+set a(0-1437) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#7 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-1277 XREFS 10462 LOC {1 0.08158839999999999 1 0.1169055 1 0.1169055 1 0.3098293625 1 0.9999999374999999} PREDS {{258 0 0-1420 {}} {259 0 0-1436 {}}} SUCCS {{259 0 0-1438 {}}} CYCLES {}}
+set a(0-1438) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#12 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-1277 XREFS 10463 LOC {1 0.274512325 1 0.309829425 1 0.309829425 1 0.41583116633787987 2 0.19248954133787985} PREDS {{258 0 0-1432 {}} {259 0 0-1437 {}}} SUCCS {{258 0 0-1469 {}} {258 0 0-1690 {}}} CYCLES {}}
+set a(0-1439) {NAME FRAME:for:slc(b(2).sva) TYPE READSLICE PAR 0-1277 XREFS 10464 LOC {1 0.0753708 1 0.286768825 1 0.286768825 2 0.080169675} PREDS {{258 0 0-1350 {}} {258 0 0-1280 {}}} SUCCS {{259 0 0-1440 {}}} CYCLES {}}
+set a(0-1440) {NAME FRAME:for:exs#25 TYPE SIGNEXTEND PAR 0-1277 XREFS 10465 LOC {1 0.0753708 1 0.286768825 1 0.286768825 2 0.080169675} PREDS {{259 0 0-1439 {}}} SUCCS {{259 0 0-1441 {}}} CYCLES {}}
+set a(0-1441) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#10 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-1277 XREFS 10466 LOC {1 0.0753708 1 0.286768825 1 0.286768825 1 0.3098293875 2 0.10323023749999999} PREDS {{258 0 0-1294 {}} {262 0 0-1692 {}} {259 0 0-1440 {}}} SUCCS {{258 0 0-1447 {}} {256 0 0-1692 {}}} CYCLES {}}
+set a(0-1442) {NAME {regs.operator[]#17:slc(regs.regs(2))} TYPE READSLICE PAR 0-1277 XREFS 10467 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.748548275} PREDS {{258 0 0-1357 {}}} SUCCS {{258 0 0-1445 {}}} CYCLES {}}
+set a(0-1443) {NAME {regs.operator[]#17:slc(regs.regs(1))} TYPE READSLICE PAR 0-1277 XREFS 10468 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.748548275} PREDS {{258 0 0-1355 {}}} SUCCS {{258 0 0-1445 {}}} CYCLES {}}
+set a(0-1444) {NAME {regs.operator[]#17:slc(regs.regs(0))} TYPE READSLICE PAR 0-1277 XREFS 10469 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.748548275} PREDS {{258 0 0-1352 {}}} SUCCS {{259 0 0-1445 {}}} CYCLES {}}
+set a(0-1445) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#17:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1277 XREFS 10470 LOC {1 0.0230606 1 0.0583777 1 0.0583777 1 0.11690545 1 0.807076025} PREDS {{258 0 0-1360 {}} {258 0 0-1443 {}} {258 0 0-1442 {}} {259 0 0-1444 {}}} SUCCS {{259 0 0-1446 {}}} CYCLES {}}
+set a(0-1446) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#8 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-1277 XREFS 10471 LOC {1 0.08158839999999999 1 0.1169055 1 0.1169055 1 0.3098293625 1 0.9999999374999999} PREDS {{258 0 0-1420 {}} {259 0 0-1445 {}}} SUCCS {{259 0 0-1447 {}}} CYCLES {}}
+set a(0-1447) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 6 NAME FRAME:for:acc#14 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-1277 XREFS 10472 LOC {1 0.274512325 1 0.309829425 1 0.309829425 1 0.41583116633787987 2 0.20923201633787986} PREDS {{258 0 0-1441 {}} {259 0 0-1446 {}}} SUCCS {{258 0 0-1483 {}} {258 0 0-1692 {}}} CYCLES {}}
+set a(0-1448) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,2) AREA_SCORE 3.31 QUANTITY 1 NAME FRAME:for:acc#16 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1277 XREFS 10473 LOC {1 0.016406775 1 0.268314 1 0.268314 1 0.3090970100894752 2 0.08390436008947524} PREDS {{258 0 0-1360 {}}} SUCCS {{259 0 0-1449 {}} {258 0 0-1694 {}}} CYCLES {}}
+set a(0-1449) {NAME FRAME:for:asn#2 TYPE ASSIGN PAR 0-1277 XREFS 10474 LOC {1 0.057189825 1 0.30909705 1 0.30909705 2 0.08390439999999999} PREDS {{259 0 0-1448 {}}} SUCCS {{259 0 0-1450 {}}} CYCLES {}}
+set a(0-1450) {NAME FRAME:for:conc#11 TYPE CONCATENATE PAR 0-1277 XREFS 10475 LOC {1 0.057189825 1 0.30909705 1 0.30909705 2 0.08390439999999999} PREDS {{259 0 0-1449 {}}} SUCCS {{259 0 0-1451 {}}} CYCLES {}}
+set a(0-1451) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 4 NAME FRAME:for:acc TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-1277 XREFS 10476 LOC {1 0.057189825 1 0.30909705 1 0.30909705 1 0.33634292707082714 2 0.11115027707082717} PREDS {{259 0 0-1450 {}}} SUCCS {{259 0 0-1452 {}}} CYCLES {}}
+set a(0-1452) {NAME FRAME:for:slc TYPE READSLICE PAR 0-1277 XREFS 10477 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.111150325} PREDS {{259 0 0-1451 {}}} SUCCS {{259 0 0-1453 {}}} CYCLES {}}
+set a(0-1453) {NAME FRAME:for:not TYPE NOT PAR 0-1277 XREFS 10478 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.111150325} PREDS {{259 0 0-1452 {}}} SUCCS {{259 0 0-1454 {}} {258 0 0-1680 {}} {258 0 0-1682 {}} {258 0 0-1683 {}} {258 0 0-1693 {}}} CYCLES {}}
+set a(0-1454) {NAME FRAME:for:select#2 TYPE SELECT PAR 0-1277 XREFS 10479 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.111150325} PREDS {{259 0 0-1453 {}}} SUCCS {{146 0 0-1455 {}} {146 0 0-1456 {}} {146 0 0-1457 {}} {146 0 0-1458 {}} {146 0 0-1459 {}} {146 0 0-1460 {}} {146 0 0-1461 {}} {146 0 0-1462 {}} {146 0 0-1463 {}} {146 0 0-1464 {}} {146 0 0-1465 {}} {146 0 0-1466 {}} {146 0 0-1467 {}} {146 0 0-1468 {}} {146 0 0-1469 {}} {146 0 0-1470 {}} {146 0 0-1471 {}} {146 0 0-1472 {}} {146 0 0-1473 {}} {146 0 0-1474 {}} {146 0 0-1475 {}} {146 0 0-1476 {}} {146 0 0-1477 {}} {146 0 0-1478 {}} {146 0 0-1479 {}} {146 0 0-1480 {}} {146 0 0-1481 {}} {146 0 0-1482 {}} {146 0 0-1483 {}} {146 0 0-1484 {}} {146 0 0-1485 {}} {146 0 0-1486 {}} {146 0 0-1487 {}} {146 0 0-1488 {}} {146 0 0-1489 {}} {146 0 0-1490 {}} {146 0 0-1491 {}} {146 0 0-1492 {}} {146 0 0-1493 {}} {146 0 0-1494 {}} {146 0 0-1495 {}} {146 0 0-1496 {}} {146 0 0-1497 {}} {146 0 0-1498 {}} {146 0 0-1499 {}} {146 0 0-1500 {}} {146 0 0-1501 {}} {146 0 0-1502 {}} {146 0 0-1503 {}} {146 0 0-1504 {}} {146 0 0-1505 {}} {146 0 0-1506 {}} {146 0 0-1507 {}} {146 0 0-1508 {}} {146 0 0-1509 {}} {146 0 0-1510 {}} {146 0 0-1511 {}} {146 0 0-1512 {}} {146 0 0-1513 {}} {146 0 0-1514 {}} {146 0 0-1515 {}} {146 0 0-1516 {}} {146 0 0-1517 {}} {146 0 0-1518 {}} {146 0 0-1519 {}} {146 0 0-1520 {}} {146 0 0-1521 {}} {146 0 0-1522 {}} {146 0 0-1523 {}} {146 0 0-1524 {}} {146 0 0-1525 {}} {146 0 0-1526 {}} {146 0 0-1527 {}} {146 0 0-1528 {}} {146 0 0-1529 {}} {146 0 0-1530 {}} {146 0 0-1531 {}} {146 0 0-1532 {}} {146 0 0-1533 {}} {146 0 0-1534 {}} {146 0 0-1535 {}} {146 0 0-1536 {}} {146 0 0-1537 {}} {146 0 0-1538 {}} {146 0 0-1539 {}} {146 0 0-1540 {}} {146 0 0-1541 {}} {146 0 0-1542 {}} {146 0 0-1543 {}} {146 0 0-1544 {}} {146 0 0-1545 {}} {146 0 0-1546 {}} {146 0 0-1547 {}} {146 0 0-1548 {}} {146 0 0-1549 {}} {146 0 0-1550 {}} {146 0 0-1551 {}} {146 0 0-1552 {}} {146 0 0-1553 {}} {146 0 0-1554 {}} {146 0 0-1555 {}} {146 0 0-1556 {}} {146 0 0-1557 {}} {146 0 0-1558 {}} {146 0 0-1559 {}} {146 0 0-1560 {}} {146 0 0-1561 {}} {146 0 0-1562 {}} {146 0 0-1563 {}} {146 0 0-1564 {}} {146 0 0-1565 {}} {146 0 0-1566 {}} {146 0 0-1567 {}} {146 0 0-1568 {}} {146 0 0-1569 {}} {146 0 0-1570 {}} {146 0 0-1571 {}} {146 0 0-1572 {}} {146 0 0-1573 {}} {146 0 0-1574 {}} {146 0 0-1575 {}} {146 0 0-1576 {}} {146 0 0-1577 {}} {146 0 0-1578 {}} {146 0 0-1579 {}} {146 0 0-1580 {}} {146 0 0-1581 {}} {146 0 0-1582 {}} {146 0 0-1583 {}} {146 0 0-1584 {}} {146 0 0-1585 {}} {146 0 0-1586 {}} {146 0 0-1587 {}} {146 0 0-1588 {}} {146 0 0-1589 {}} {146 0 0-1590 {}} {146 0 0-1591 {}} {146 0 0-1592 {}} {146 0 0-1593 {}} {146 0 0-1594 {}} {146 0 0-1595 {}} {146 0 0-1596 {}} {146 0 0-1597 {}} {146 0 0-1598 {}} {146 0 0-1599 {}} {146 0 0-1600 {}} {146 0 0-1601 {}} {146 0 0-1602 {}} {146 0 0-1603 {}} {146 0 0-1604 {}} {146 0 0-1605 {}} {146 0 0-1606 {}} {146 0 0-1607 {}} {146 0 0-1608 {}} {146 0 0-1609 {}} {146 0 0-1610 {}} {146 0 0-1611 {}} {146 0 0-1612 {}} {146 0 0-1613 {}} {146 0 0-1614 {}} {146 0 0-1615 {}} {146 0 0-1616 {}} {146 0 0-1617 {}} {146 0 0-1618 {}} {146 0 0-1619 {}} {146 0 0-1620 {}} {146 0 0-1621 {}} {146 0 0-1622 {}} {146 0 0-1623 {}} {146 0 0-1624 {}} {146 0 0-1625 {}} {146 0 0-1626 {}} {146 0 0-1627 {}} {146 0 0-1628 {}} {146 0 0-1629 {}} {146 0 0-1630 {}} {146 0 0-1631 {}} {146 0 0-1632 {}} {146 0 0-1633 {}} {146 0 0-1634 {}} {146 0 0-1635 {}} {146 0 0-1636 {}} {146 0 0-1637 {}} {146 0 0-1638 {}} {146 0 0-1639 {}} {146 0 0-1640 {}} {146 0 0-1641 {}} {146 0 0-1642 {}} {146 0 0-1643 {}} {146 0 0-1644 {}} {146 0 0-1645 {}} {146 0 0-1646 {}} {146 0 0-1647 {}} {146 0 0-1648 {}} {146 0 0-1649 {}} {146 0 0-1650 {}} {146 0 0-1651 {}} {146 0 0-1652 {}} {146 0 0-1653 {}} {146 0 0-1654 {}} {146 0 0-1655 {}} {146 0 0-1656 {}} {146 0 0-1657 {}} {146 0 0-1658 {}} {146 0 0-1659 {}} {146 0 0-1660 {}} {146 0 0-1661 {}} {146 0 0-1662 {}} {146 0 0-1663 {}} {146 0 0-1664 {}} {146 0 0-1665 {}} {146 0 0-1666 {}} {146 0 0-1667 {}} {146 0 0-1668 {}} {146 0 0-1669 {}} {146 0 0-1670 {}} {146 0 0-1671 {}} {130 0 0-1672 {}} {146 0 0-1673 {}} {146 0 0-1674 {}} {146 0 0-1675 {}} {146 0 0-1676 {}} {146 0 0-1677 {}}} CYCLES {}}
+set a(0-1455) {NAME ACC1:conc#34 TYPE CONCATENATE PAR 0-1277 XREFS 10480 LOC {1 0.380514125 1 0.41583122499999997 1 0.41583122499999997 2 0.190638575} PREDS {{146 0 0-1454 {}} {258 0 0-1429 {}}} SUCCS {{258 0 0-1466 {}}} CYCLES {}}
+set a(0-1456) {NAME ACC2:slc(regs.regs(0)) TYPE READSLICE PAR 0-1277 XREFS 10481 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.111150325} PREDS {{146 0 0-1454 {}} {258 0 0-1352 {}}} SUCCS {{259 0 0-1457 {}}} CYCLES {}}
+set a(0-1457) {NAME ACC2:not TYPE NOT PAR 0-1277 XREFS 10482 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.111150325} PREDS {{146 0 0-1454 {}} {259 0 0-1456 {}}} SUCCS {{259 0 0-1458 {}}} CYCLES {}}
+set a(0-1458) {NAME ACC2:conc TYPE CONCATENATE PAR 0-1277 XREFS 10483 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.111150325} PREDS {{146 0 0-1454 {}} {259 0 0-1457 {}}} SUCCS {{259 0 0-1459 {}}} CYCLES {}}
+set a(0-1459) {NAME ACC1:conc#32 TYPE CONCATENATE PAR 0-1277 XREFS 10484 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.111150325} PREDS {{146 0 0-1454 {}} {259 0 0-1458 {}}} SUCCS {{258 0 0-1463 {}}} CYCLES {}}
+set a(0-1460) {NAME ACC2:slc(regs.regs(2)) TYPE READSLICE PAR 0-1277 XREFS 10485 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.111150325} PREDS {{146 0 0-1454 {}} {258 0 0-1357 {}}} SUCCS {{259 0 0-1461 {}}} CYCLES {}}
+set a(0-1461) {NAME ACC2:conc#1 TYPE CONCATENATE PAR 0-1277 XREFS 10486 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.111150325} PREDS {{146 0 0-1454 {}} {259 0 0-1460 {}}} SUCCS {{259 0 0-1462 {}}} CYCLES {}}
+set a(0-1462) {NAME ACC1:conc#33 TYPE CONCATENATE PAR 0-1277 XREFS 10487 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.111150325} PREDS {{146 0 0-1454 {}} {259 0 0-1461 {}}} SUCCS {{259 0 0-1463 {}}} CYCLES {}}
+set a(0-1463) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME ACC1:acc#50 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-1277 XREFS 10488 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 1 0.4158311784997777 2 0.19063852849977767} PREDS {{146 0 0-1454 {}} {258 0 0-1459 {}} {259 0 0-1462 {}}} SUCCS {{259 0 0-1464 {}}} CYCLES {}}
+set a(0-1464) {NAME ACC1:slc#6 TYPE READSLICE PAR 0-1277 XREFS 10489 LOC {1 0.163924 1 0.41583122499999997 1 0.41583122499999997 2 0.190638575} PREDS {{146 0 0-1454 {}} {259 0 0-1463 {}}} SUCCS {{259 0 0-1465 {}}} CYCLES {}}
+set a(0-1465) {NAME ACC1:conc#35 TYPE CONCATENATE PAR 0-1277 XREFS 10490 LOC {1 0.163924 1 0.41583122499999997 1 0.41583122499999997 2 0.190638575} PREDS {{146 0 0-1454 {}} {259 0 0-1464 {}}} SUCCS {{259 0 0-1466 {}}} CYCLES {}}
+set a(0-1466) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(17,0,13,1,17) AREA_SCORE 18.00 QUANTITY 3 NAME ACC1:acc#51 TYPE ACCU DELAY {1.76 ns} LIBRARY_DELAY {1.76 ns} PAR 0-1277 XREFS 10491 LOC {1 0.380514125 1 0.41583122499999997 1 0.41583122499999997 1 0.5257232897236815 2 0.30053063972368155} PREDS {{146 0 0-1454 {}} {258 0 0-1455 {}} {259 0 0-1465 {}}} SUCCS {{259 0 0-1467 {}}} CYCLES {}}
+set a(0-1467) {NAME ACC1:slc#7 TYPE READSLICE PAR 0-1277 XREFS 10492 LOC {1 0.49040625 1 0.5257233499999999 1 0.5257233499999999 2 0.3005307} PREDS {{146 0 0-1454 {}} {259 0 0-1466 {}}} SUCCS {{259 0 0-1468 {}}} CYCLES {}}
+set a(0-1468) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 3 NAME ACC2-3:acc#1 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-1277 XREFS 10493 LOC {1 0.49040625 1 0.5257233499999999 1 0.5257233499999999 1 0.6313330803579009 2 0.406140430357901} PREDS {{146 0 0-1454 {}} {258 0 0-1383 {}} {259 0 0-1467 {}}} SUCCS {{258 0 0-1497 {}} {258 0 0-1499 {}} {258 0 0-1502 {}} {258 0 0-1504 {}} {258 0 0-1506 {}} {258 0 0-1595 {}} {258 0 0-1597 {}} {258 0 0-1601 {}} {258 0 0-1607 {}} {258 0 0-1613 {}} {258 0 0-1619 {}} {258 0 0-1627 {}}} CYCLES {}}
+set a(0-1469) {NAME ACC1:conc#38 TYPE CONCATENATE PAR 0-1277 XREFS 10494 LOC {1 0.380514125 1 0.41583122499999997 1 0.41583122499999997 2 0.19248959999999998} PREDS {{146 0 0-1454 {}} {258 0 0-1438 {}}} SUCCS {{258 0 0-1480 {}}} CYCLES {}}
+set a(0-1470) {NAME ACC2:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-1277 XREFS 10495 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.11300135} PREDS {{146 0 0-1454 {}} {258 0 0-1352 {}}} SUCCS {{259 0 0-1471 {}}} CYCLES {}}
+set a(0-1471) {NAME ACC2:not#1 TYPE NOT PAR 0-1277 XREFS 10496 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.11300135} PREDS {{146 0 0-1454 {}} {259 0 0-1470 {}}} SUCCS {{259 0 0-1472 {}}} CYCLES {}}
+set a(0-1472) {NAME ACC2:conc#2 TYPE CONCATENATE PAR 0-1277 XREFS 10497 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.11300135} PREDS {{146 0 0-1454 {}} {259 0 0-1471 {}}} SUCCS {{259 0 0-1473 {}}} CYCLES {}}
+set a(0-1473) {NAME ACC1:conc#36 TYPE CONCATENATE PAR 0-1277 XREFS 10498 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.11300135} PREDS {{146 0 0-1454 {}} {259 0 0-1472 {}}} SUCCS {{258 0 0-1477 {}}} CYCLES {}}
+set a(0-1474) {NAME ACC2:slc(regs.regs(2))#1 TYPE READSLICE PAR 0-1277 XREFS 10499 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.11300135} PREDS {{146 0 0-1454 {}} {258 0 0-1357 {}}} SUCCS {{259 0 0-1475 {}}} CYCLES {}}
+set a(0-1475) {NAME ACC2:conc#3 TYPE CONCATENATE PAR 0-1277 XREFS 10500 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.11300135} PREDS {{146 0 0-1454 {}} {259 0 0-1474 {}}} SUCCS {{259 0 0-1476 {}}} CYCLES {}}
+set a(0-1476) {NAME ACC1:conc#37 TYPE CONCATENATE PAR 0-1277 XREFS 10501 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.11300135} PREDS {{146 0 0-1454 {}} {259 0 0-1475 {}}} SUCCS {{259 0 0-1477 {}}} CYCLES {}}
+set a(0-1477) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME ACC1:acc#52 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-1277 XREFS 10502 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 1 0.4158311784997777 2 0.19248955349977767} PREDS {{146 0 0-1454 {}} {258 0 0-1473 {}} {259 0 0-1476 {}}} SUCCS {{259 0 0-1478 {}}} CYCLES {}}
+set a(0-1478) {NAME ACC1:slc#8 TYPE READSLICE PAR 0-1277 XREFS 10503 LOC {1 0.163924 1 0.41583122499999997 1 0.41583122499999997 2 0.19248959999999998} PREDS {{146 0 0-1454 {}} {259 0 0-1477 {}}} SUCCS {{259 0 0-1479 {}}} CYCLES {}}
+set a(0-1479) {NAME ACC1:conc#39 TYPE CONCATENATE PAR 0-1277 XREFS 10504 LOC {1 0.163924 1 0.41583122499999997 1 0.41583122499999997 2 0.19248959999999998} PREDS {{146 0 0-1454 {}} {259 0 0-1478 {}}} SUCCS {{259 0 0-1480 {}}} CYCLES {}}
+set a(0-1480) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(17,0,13,1,17) AREA_SCORE 18.00 QUANTITY 3 NAME ACC1:acc#53 TYPE ACCU DELAY {1.76 ns} LIBRARY_DELAY {1.76 ns} PAR 0-1277 XREFS 10505 LOC {1 0.380514125 1 0.41583122499999997 1 0.41583122499999997 1 0.5257232897236815 2 0.30238166472368155} PREDS {{146 0 0-1454 {}} {258 0 0-1469 {}} {259 0 0-1479 {}}} SUCCS {{259 0 0-1481 {}}} CYCLES {}}
+set a(0-1481) {NAME ACC1:slc#9 TYPE READSLICE PAR 0-1277 XREFS 10506 LOC {1 0.49040625 1 0.5257233499999999 1 0.5257233499999999 2 0.302381725} PREDS {{146 0 0-1454 {}} {259 0 0-1480 {}}} SUCCS {{259 0 0-1482 {}}} CYCLES {}}
+set a(0-1482) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 3 NAME ACC2-3:acc#2 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-1277 XREFS 10507 LOC {1 0.49040625 1 0.5257233499999999 1 0.5257233499999999 1 0.6313330803579009 2 0.407991455357901} PREDS {{146 0 0-1454 {}} {258 0 0-1393 {}} {259 0 0-1481 {}}} SUCCS {{258 0 0-1518 {}} {258 0 0-1520 {}} {258 0 0-1523 {}} {258 0 0-1525 {}} {258 0 0-1527 {}} {258 0 0-1539 {}} {258 0 0-1541 {}} {258 0 0-1545 {}} {258 0 0-1551 {}} {258 0 0-1557 {}} {258 0 0-1563 {}} {258 0 0-1571 {}}} CYCLES {}}
+set a(0-1483) {NAME ACC1:conc#42 TYPE CONCATENATE PAR 0-1277 XREFS 10508 LOC {1 0.380514125 1 0.41583122499999997 1 0.41583122499999997 2 0.209232075} PREDS {{146 0 0-1454 {}} {258 0 0-1447 {}}} SUCCS {{258 0 0-1494 {}}} CYCLES {}}
+set a(0-1484) {NAME ACC2:slc(regs.regs(0))#2 TYPE READSLICE PAR 0-1277 XREFS 10509 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.129743825} PREDS {{146 0 0-1454 {}} {258 0 0-1352 {}}} SUCCS {{259 0 0-1485 {}}} CYCLES {}}
+set a(0-1485) {NAME ACC2:not#2 TYPE NOT PAR 0-1277 XREFS 10510 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.129743825} PREDS {{146 0 0-1454 {}} {259 0 0-1484 {}}} SUCCS {{259 0 0-1486 {}}} CYCLES {}}
+set a(0-1486) {NAME ACC2:conc#4 TYPE CONCATENATE PAR 0-1277 XREFS 10511 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.129743825} PREDS {{146 0 0-1454 {}} {259 0 0-1485 {}}} SUCCS {{259 0 0-1487 {}}} CYCLES {}}
+set a(0-1487) {NAME ACC1:conc#40 TYPE CONCATENATE PAR 0-1277 XREFS 10512 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.129743825} PREDS {{146 0 0-1454 {}} {259 0 0-1486 {}}} SUCCS {{258 0 0-1491 {}}} CYCLES {}}
+set a(0-1488) {NAME ACC2:slc(regs.regs(2))#2 TYPE READSLICE PAR 0-1277 XREFS 10513 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.129743825} PREDS {{146 0 0-1454 {}} {258 0 0-1357 {}}} SUCCS {{259 0 0-1489 {}}} CYCLES {}}
+set a(0-1489) {NAME ACC2:conc#5 TYPE CONCATENATE PAR 0-1277 XREFS 10514 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.129743825} PREDS {{146 0 0-1454 {}} {259 0 0-1488 {}}} SUCCS {{259 0 0-1490 {}}} CYCLES {}}
+set a(0-1490) {NAME ACC1:conc#41 TYPE CONCATENATE PAR 0-1277 XREFS 10515 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 2 0.129743825} PREDS {{146 0 0-1454 {}} {259 0 0-1489 {}}} SUCCS {{259 0 0-1491 {}}} CYCLES {}}
+set a(0-1491) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME ACC1:acc#54 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-1277 XREFS 10516 LOC {1 0.08443574999999999 1 0.336342975 1 0.336342975 1 0.4158311784997777 2 0.20923202849977768} PREDS {{146 0 0-1454 {}} {258 0 0-1487 {}} {259 0 0-1490 {}}} SUCCS {{259 0 0-1492 {}}} CYCLES {}}
+set a(0-1492) {NAME ACC1:slc#10 TYPE READSLICE PAR 0-1277 XREFS 10517 LOC {1 0.163924 1 0.41583122499999997 1 0.41583122499999997 2 0.209232075} PREDS {{146 0 0-1454 {}} {259 0 0-1491 {}}} SUCCS {{259 0 0-1493 {}}} CYCLES {}}
+set a(0-1493) {NAME ACC1:conc#43 TYPE CONCATENATE PAR 0-1277 XREFS 10518 LOC {1 0.163924 1 0.41583122499999997 1 0.41583122499999997 2 0.209232075} PREDS {{146 0 0-1454 {}} {259 0 0-1492 {}}} SUCCS {{259 0 0-1494 {}}} CYCLES {}}
+set a(0-1494) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(17,0,13,1,17) AREA_SCORE 18.00 QUANTITY 3 NAME ACC1:acc#55 TYPE ACCU DELAY {1.76 ns} LIBRARY_DELAY {1.76 ns} PAR 0-1277 XREFS 10519 LOC {1 0.380514125 1 0.41583122499999997 1 0.41583122499999997 1 0.5257232897236815 2 0.3191241397236816} PREDS {{146 0 0-1454 {}} {258 0 0-1483 {}} {259 0 0-1493 {}}} SUCCS {{259 0 0-1495 {}}} CYCLES {}}
+set a(0-1495) {NAME ACC1:slc#11 TYPE READSLICE PAR 0-1277 XREFS 10520 LOC {1 0.49040625 1 0.5257233499999999 1 0.5257233499999999 2 0.31912419999999997} PREDS {{146 0 0-1454 {}} {259 0 0-1494 {}}} SUCCS {{259 0 0-1496 {}}} CYCLES {}}
+set a(0-1496) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 3 NAME ACC2-3:acc#3 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-1277 XREFS 10521 LOC {1 0.49040625 1 0.5257233499999999 1 0.5257233499999999 1 0.6313330803579009 2 0.42473393035790097} PREDS {{146 0 0-1454 {}} {258 0 0-1403 {}} {259 0 0-1495 {}}} SUCCS {{258 0 0-1574 {}} {258 0 0-1576 {}} {258 0 0-1579 {}} {258 0 0-1581 {}} {258 0 0-1583 {}} {258 0 0-1635 {}} {258 0 0-1637 {}} {258 0 0-1641 {}} {258 0 0-1647 {}} {258 0 0-1653 {}} {258 0 0-1659 {}} {258 0 0-1667 {}}} CYCLES {}}
+set a(0-1497) {NAME FRAME:slc(red)#3 TYPE READSLICE PAR 0-1277 XREFS 10522 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.431529825} PREDS {{146 0 0-1454 {}} {258 0 0-1468 {}}} SUCCS {{259 0 0-1498 {}}} CYCLES {}}
+set a(0-1498) {NAME FRAME:not#2 TYPE NOT PAR 0-1277 XREFS 10523 LOC {1 0.596016025 1 0.6567224749999999 1 0.6567224749999999 2 0.431529825} PREDS {{146 0 0-1454 {}} {259 0 0-1497 {}}} SUCCS {{258 0 0-1500 {}}} CYCLES {}}
+set a(0-1499) {NAME FRAME:slc(red)#4 TYPE READSLICE PAR 0-1277 XREFS 10524 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.431529825} PREDS {{146 0 0-1454 {}} {258 0 0-1468 {}}} SUCCS {{259 0 0-1500 {}}} CYCLES {}}
+set a(0-1500) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 4 NAME FRAME:acc#13 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-1277 XREFS 10525 LOC {1 0.596016025 1 0.6567224749999999 1 0.6567224749999999 1 0.6839683520708271 2 0.4587757020708272} PREDS {{146 0 0-1454 {}} {258 0 0-1498 {}} {259 0 0-1499 {}}} SUCCS {{259 0 0-1501 {}}} CYCLES {}}
+set a(0-1501) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,1,5,1,6) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#16 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-1277 XREFS 10526 LOC {1 0.62326195 1 0.6839683999999999 1 0.6839683999999999 1 0.732412984496936 2 0.507220334496936} PREDS {{146 0 0-1454 {}} {259 0 0-1500 {}}} SUCCS {{258 0 0-1508 {}}} CYCLES {}}
+set a(0-1502) {NAME FRAME:slc(red)#1 TYPE READSLICE PAR 0-1277 XREFS 10527 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.406140475} PREDS {{146 0 0-1454 {}} {258 0 0-1468 {}}} SUCCS {{259 0 0-1503 {}}} CYCLES {}}
+set a(0-1503) {NAME FRAME:not#1 TYPE NOT PAR 0-1277 XREFS 10528 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.406140475} PREDS {{146 0 0-1454 {}} {259 0 0-1502 {}}} SUCCS {{258 0 0-1505 {}}} CYCLES {}}
+set a(0-1504) {NAME FRAME:slc(red)#2 TYPE READSLICE PAR 0-1277 XREFS 10529 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.406140475} PREDS {{146 0 0-1454 {}} {258 0 0-1468 {}}} SUCCS {{259 0 0-1505 {}}} CYCLES {}}
+set a(0-1505) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 3 NAME FRAME:acc#14 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1277 XREFS 10530 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 1 0.6788892520708271 2 0.4536966020708272} PREDS {{146 0 0-1454 {}} {258 0 0-1503 {}} {259 0 0-1504 {}}} SUCCS {{258 0 0-1507 {}}} CYCLES {}}
+set a(0-1506) {NAME FRAME:slc(red) TYPE READSLICE PAR 0-1277 XREFS 10531 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.45369665} PREDS {{146 0 0-1454 {}} {258 0 0-1468 {}}} SUCCS {{259 0 0-1507 {}}} CYCLES {}}
+set a(0-1507) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,5) AREA_SCORE 5.30 QUANTITY 9 NAME FRAME:acc#15 TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-1277 XREFS 10532 LOC {1 0.6435721999999999 1 0.6788892999999999 1 0.6788892999999999 1 0.7324129649089293 2 0.5072203149089294} PREDS {{146 0 0-1454 {}} {258 0 0-1505 {}} {259 0 0-1506 {}}} SUCCS {{259 0 0-1508 {}}} CYCLES {}}
+set a(0-1508) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME FRAME:acc#7 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-1277 XREFS 10533 LOC {1 0.697095925 1 0.7324130249999999 1 0.7324130249999999 1 0.7960632407468814 2 0.5708705907468814} PREDS {{146 0 0-1454 {}} {258 0 0-1501 {}} {259 0 0-1507 {}}} SUCCS {{259 0 0-1509 {}} {258 0 0-1511 {}} {258 0 0-1513 {}} {258 0 0-1598 {}} {258 0 0-1606 {}} {258 0 0-1622 {}}} CYCLES {}}
+set a(0-1509) {NAME FRAME:slc(acc.imod)#7 TYPE READSLICE PAR 0-1277 XREFS 10534 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5708706499999999} PREDS {{146 0 0-1454 {}} {259 0 0-1508 {}}} SUCCS {{259 0 0-1510 {}}} CYCLES {}}
+set a(0-1510) {NAME FRAME:conc TYPE CONCATENATE PAR 0-1277 XREFS 10535 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5708706499999999} PREDS {{146 0 0-1454 {}} {259 0 0-1509 {}}} SUCCS {{258 0 0-1516 {}}} CYCLES {}}
+set a(0-1511) {NAME FRAME:slc(acc.imod)#2 TYPE READSLICE PAR 0-1277 XREFS 10536 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5708706499999999} PREDS {{146 0 0-1454 {}} {258 0 0-1508 {}}} SUCCS {{259 0 0-1512 {}}} CYCLES {}}
+set a(0-1512) {NAME FRAME:not#4 TYPE NOT PAR 0-1277 XREFS 10537 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5708706499999999} PREDS {{146 0 0-1454 {}} {259 0 0-1511 {}}} SUCCS {{258 0 0-1515 {}}} CYCLES {}}
+set a(0-1513) {NAME FRAME:slc(acc.imod) TYPE READSLICE PAR 0-1277 XREFS 10538 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5708706499999999} PREDS {{146 0 0-1454 {}} {258 0 0-1508 {}}} SUCCS {{259 0 0-1514 {}}} CYCLES {}}
+set a(0-1514) {NAME FRAME:not#3 TYPE NOT PAR 0-1277 XREFS 10539 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5708706499999999} PREDS {{146 0 0-1454 {}} {259 0 0-1513 {}}} SUCCS {{259 0 0-1515 {}}} CYCLES {}}
+set a(0-1515) {NAME FRAME:conc#67 TYPE CONCATENATE PAR 0-1277 XREFS 10540 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5708706499999999} PREDS {{146 0 0-1454 {}} {258 0 0-1512 {}} {259 0 0-1514 {}}} SUCCS {{259 0 0-1516 {}}} CYCLES {}}
+set a(0-1516) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,1,5,1,6) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#17 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-1277 XREFS 10541 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 1 0.844507884496936 2 0.6193152344969359} PREDS {{146 0 0-1454 {}} {258 0 0-1510 {}} {259 0 0-1515 {}}} SUCCS {{259 0 0-1517 {}}} CYCLES {}}
+set a(0-1517) {NAME FRAME:slc#2 TYPE READSLICE PAR 0-1277 XREFS 10542 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {259 0 0-1516 {}}} SUCCS {{258 0 0-1600 {}} {258 0 0-1608 {}} {258 0 0-1610 {}} {258 0 0-1611 {}} {258 0 0-1612 {}}} CYCLES {}}
+set a(0-1518) {NAME FRAME:slc(green)#3 TYPE READSLICE PAR 0-1277 XREFS 10543 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.43338085} PREDS {{146 0 0-1454 {}} {258 0 0-1482 {}}} SUCCS {{259 0 0-1519 {}}} CYCLES {}}
+set a(0-1519) {NAME FRAME:not#11 TYPE NOT PAR 0-1277 XREFS 10544 LOC {1 0.596016025 1 0.6567224749999999 1 0.6567224749999999 2 0.43338085} PREDS {{146 0 0-1454 {}} {259 0 0-1518 {}}} SUCCS {{258 0 0-1521 {}}} CYCLES {}}
+set a(0-1520) {NAME FRAME:slc(green)#4 TYPE READSLICE PAR 0-1277 XREFS 10545 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.43338085} PREDS {{146 0 0-1454 {}} {258 0 0-1482 {}}} SUCCS {{259 0 0-1521 {}}} CYCLES {}}
+set a(0-1521) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 4 NAME FRAME:acc#18 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-1277 XREFS 10546 LOC {1 0.596016025 1 0.6567224749999999 1 0.6567224749999999 1 0.6839683520708271 2 0.4606267270708272} PREDS {{146 0 0-1454 {}} {258 0 0-1519 {}} {259 0 0-1520 {}}} SUCCS {{259 0 0-1522 {}}} CYCLES {}}
+set a(0-1522) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,1,5,1,6) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#21 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-1277 XREFS 10547 LOC {1 0.62326195 1 0.6839683999999999 1 0.6839683999999999 1 0.732412984496936 2 0.509071359496936} PREDS {{146 0 0-1454 {}} {259 0 0-1521 {}}} SUCCS {{258 0 0-1529 {}}} CYCLES {}}
+set a(0-1523) {NAME FRAME:slc(green)#1 TYPE READSLICE PAR 0-1277 XREFS 10548 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.4079915} PREDS {{146 0 0-1454 {}} {258 0 0-1482 {}}} SUCCS {{259 0 0-1524 {}}} CYCLES {}}
+set a(0-1524) {NAME FRAME:not#10 TYPE NOT PAR 0-1277 XREFS 10549 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.4079915} PREDS {{146 0 0-1454 {}} {259 0 0-1523 {}}} SUCCS {{258 0 0-1526 {}}} CYCLES {}}
+set a(0-1525) {NAME FRAME:slc(green)#2 TYPE READSLICE PAR 0-1277 XREFS 10550 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.4079915} PREDS {{146 0 0-1454 {}} {258 0 0-1482 {}}} SUCCS {{259 0 0-1526 {}}} CYCLES {}}
+set a(0-1526) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 3 NAME FRAME:acc#19 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1277 XREFS 10551 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 1 0.6788892520708271 2 0.4555476270708272} PREDS {{146 0 0-1454 {}} {258 0 0-1524 {}} {259 0 0-1525 {}}} SUCCS {{258 0 0-1528 {}}} CYCLES {}}
+set a(0-1527) {NAME FRAME:slc(green) TYPE READSLICE PAR 0-1277 XREFS 10552 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.455547675} PREDS {{146 0 0-1454 {}} {258 0 0-1482 {}}} SUCCS {{259 0 0-1528 {}}} CYCLES {}}
+set a(0-1528) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,5) AREA_SCORE 5.30 QUANTITY 9 NAME FRAME:acc#20 TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-1277 XREFS 10553 LOC {1 0.6435721999999999 1 0.6788892999999999 1 0.6788892999999999 1 0.7324129649089293 2 0.5090713399089294} PREDS {{146 0 0-1454 {}} {258 0 0-1526 {}} {259 0 0-1527 {}}} SUCCS {{259 0 0-1529 {}}} CYCLES {}}
+set a(0-1529) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME FRAME:acc#9 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-1277 XREFS 10554 LOC {1 0.697095925 1 0.7324130249999999 1 0.7324130249999999 1 0.7960632407468814 2 0.5727216157468814} PREDS {{146 0 0-1454 {}} {258 0 0-1522 {}} {259 0 0-1528 {}}} SUCCS {{259 0 0-1530 {}} {258 0 0-1532 {}} {258 0 0-1534 {}} {258 0 0-1542 {}} {258 0 0-1550 {}} {258 0 0-1566 {}}} CYCLES {}}
+set a(0-1530) {NAME FRAME:slc(acc.imod#2)#7 TYPE READSLICE PAR 0-1277 XREFS 10555 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5727216749999999} PREDS {{146 0 0-1454 {}} {259 0 0-1529 {}}} SUCCS {{259 0 0-1531 {}}} CYCLES {}}
+set a(0-1531) {NAME FRAME:conc#69 TYPE CONCATENATE PAR 0-1277 XREFS 10556 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5727216749999999} PREDS {{146 0 0-1454 {}} {259 0 0-1530 {}}} SUCCS {{258 0 0-1537 {}}} CYCLES {}}
+set a(0-1532) {NAME FRAME:slc(acc.imod#2)#2 TYPE READSLICE PAR 0-1277 XREFS 10557 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5727216749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1529 {}}} SUCCS {{259 0 0-1533 {}}} CYCLES {}}
+set a(0-1533) {NAME FRAME:not#13 TYPE NOT PAR 0-1277 XREFS 10558 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5727216749999999} PREDS {{146 0 0-1454 {}} {259 0 0-1532 {}}} SUCCS {{258 0 0-1536 {}}} CYCLES {}}
+set a(0-1534) {NAME FRAME:slc(acc.imod#2) TYPE READSLICE PAR 0-1277 XREFS 10559 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5727216749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1529 {}}} SUCCS {{259 0 0-1535 {}}} CYCLES {}}
+set a(0-1535) {NAME FRAME:not#12 TYPE NOT PAR 0-1277 XREFS 10560 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5727216749999999} PREDS {{146 0 0-1454 {}} {259 0 0-1534 {}}} SUCCS {{259 0 0-1536 {}}} CYCLES {}}
+set a(0-1536) {NAME FRAME:conc#70 TYPE CONCATENATE PAR 0-1277 XREFS 10561 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.5727216749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1533 {}} {259 0 0-1535 {}}} SUCCS {{259 0 0-1537 {}}} CYCLES {}}
+set a(0-1537) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,1,5,1,6) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#22 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-1277 XREFS 10562 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 1 0.844507884496936 2 0.621166259496936} PREDS {{146 0 0-1454 {}} {258 0 0-1531 {}} {259 0 0-1536 {}}} SUCCS {{259 0 0-1538 {}}} CYCLES {}}
+set a(0-1538) {NAME FRAME:slc#3 TYPE READSLICE PAR 0-1277 XREFS 10563 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {259 0 0-1537 {}}} SUCCS {{258 0 0-1544 {}} {258 0 0-1552 {}} {258 0 0-1554 {}} {258 0 0-1555 {}} {258 0 0-1556 {}}} CYCLES {}}
+set a(0-1539) {NAME FRAME:slc(green)#8 TYPE READSLICE PAR 0-1277 XREFS 10564 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.64211655} PREDS {{146 0 0-1454 {}} {258 0 0-1482 {}}} SUCCS {{259 0 0-1540 {}}} CYCLES {}}
+set a(0-1540) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#2 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-1277 XREFS 10565 LOC {1 0.596016025 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.8199983421744312} PREDS {{146 0 0-1454 {}} {259 0 0-1539 {}}} SUCCS {{258 0 0-1570 {}}} CYCLES {}}
+set a(0-1541) {NAME FRAME:slc(green)#10 TYPE READSLICE PAR 0-1277 XREFS 10566 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.776658375} PREDS {{146 0 0-1454 {}} {258 0 0-1482 {}}} SUCCS {{258 0 0-1569 {}}} CYCLES {}}
+set a(0-1542) {NAME FRAME:slc(acc.imod#2)#6 TYPE READSLICE PAR 0-1277 XREFS 10567 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1529 {}}} SUCCS {{259 0 0-1543 {}}} CYCLES {}}
+set a(0-1543) {NAME FRAME:not#17 TYPE NOT PAR 0-1277 XREFS 10568 LOC {1 0.7607461999999999 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {259 0 0-1542 {}}} SUCCS {{258 0 0-1548 {}}} CYCLES {}}
+set a(0-1544) {NAME FRAME:slc(acc.imod#3) TYPE READSLICE PAR 0-1277 XREFS 10569 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1538 {}}} SUCCS {{258 0 0-1547 {}}} CYCLES {}}
+set a(0-1545) {NAME FRAME:slc(green)#5 TYPE READSLICE PAR 0-1277 XREFS 10570 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1482 {}}} SUCCS {{259 0 0-1546 {}}} CYCLES {}}
+set a(0-1546) {NAME FRAME:not#14 TYPE NOT PAR 0-1277 XREFS 10571 LOC {1 0.596016025 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {259 0 0-1545 {}}} SUCCS {{259 0 0-1547 {}}} CYCLES {}}
+set a(0-1547) {NAME FRAME:nand#1 TYPE NAND PAR 0-1277 XREFS 10572 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1544 {}} {259 0 0-1546 {}}} SUCCS {{259 0 0-1548 {}}} CYCLES {}}
+set a(0-1548) {NAME FRAME:conc#15 TYPE CONCATENATE PAR 0-1277 XREFS 10573 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1543 {}} {259 0 0-1547 {}}} SUCCS {{259 0 0-1549 {}}} CYCLES {}}
+set a(0-1549) {NAME FRAME:conc#72 TYPE CONCATENATE PAR 0-1277 XREFS 10574 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {259 0 0-1548 {}}} SUCCS {{258 0 0-1561 {}}} CYCLES {}}
+set a(0-1550) {NAME FRAME:slc(acc.imod#2)#5 TYPE READSLICE PAR 0-1277 XREFS 10575 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1529 {}}} SUCCS {{258 0 0-1560 {}}} CYCLES {}}
+set a(0-1551) {NAME FRAME:slc(green)#6 TYPE READSLICE PAR 0-1277 XREFS 10576 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1482 {}}} SUCCS {{258 0 0-1559 {}}} CYCLES {}}
+set a(0-1552) {NAME FRAME:slc(acc.imod#3)#1 TYPE READSLICE PAR 0-1277 XREFS 10577 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1538 {}}} SUCCS {{259 0 0-1553 {}}} CYCLES {}}
+set a(0-1553) {NAME FRAME:not#15 TYPE NOT PAR 0-1277 XREFS 10578 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {259 0 0-1552 {}}} SUCCS {{258 0 0-1559 {}}} CYCLES {}}
+set a(0-1554) {NAME FRAME:slc(acc.imod#3)#2 TYPE READSLICE PAR 0-1277 XREFS 10579 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1538 {}}} SUCCS {{258 0 0-1558 {}}} CYCLES {}}
+set a(0-1555) {NAME FRAME:slc(acc.imod#3)#3 TYPE READSLICE PAR 0-1277 XREFS 10580 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1538 {}}} SUCCS {{258 0 0-1558 {}}} CYCLES {}}
+set a(0-1556) {NAME FRAME:slc(acc.imod#3)#4 TYPE READSLICE PAR 0-1277 XREFS 10581 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1538 {}}} SUCCS {{258 0 0-1558 {}}} CYCLES {}}
+set a(0-1557) {NAME FRAME:slc(green)#24 TYPE READSLICE PAR 0-1277 XREFS 10582 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1482 {}}} SUCCS {{259 0 0-1558 {}}} CYCLES {}}
+set a(0-1558) {NAME FRAME:or#1 TYPE OR PAR 0-1277 XREFS 10583 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1556 {}} {258 0 0-1555 {}} {258 0 0-1554 {}} {259 0 0-1557 {}}} SUCCS {{259 0 0-1559 {}}} CYCLES {}}
+set a(0-1559) {NAME and#3 TYPE AND PAR 0-1277 XREFS 10584 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1553 {}} {258 0 0-1551 {}} {259 0 0-1558 {}}} SUCCS {{259 0 0-1560 {}}} CYCLES {}}
+set a(0-1560) {NAME FRAME:conc#73 TYPE CONCATENATE PAR 0-1277 XREFS 10585 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6211663} PREDS {{146 0 0-1454 {}} {258 0 0-1550 {}} {259 0 0-1559 {}}} SUCCS {{259 0 0-1561 {}}} CYCLES {}}
+set a(0-1561) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,5) AREA_SCORE 5.30 QUANTITY 9 NAME FRAME:acc#23 TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-1277 XREFS 10586 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 1 0.8980315899089293 2 0.6746899649089293} PREDS {{146 0 0-1454 {}} {258 0 0-1549 {}} {259 0 0-1560 {}}} SUCCS {{259 0 0-1562 {}}} CYCLES {}}
+set a(0-1562) {NAME FRAME:slc#4 TYPE READSLICE PAR 0-1277 XREFS 10587 LOC {1 0.86271455 1 0.89803165 1 0.89803165 2 0.674690025} PREDS {{146 0 0-1454 {}} {259 0 0-1561 {}}} SUCCS {{258 0 0-1565 {}}} CYCLES {}}
+set a(0-1563) {NAME FRAME:slc(green)#7 TYPE READSLICE PAR 0-1277 XREFS 10588 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.674690025} PREDS {{146 0 0-1454 {}} {258 0 0-1482 {}}} SUCCS {{259 0 0-1564 {}}} CYCLES {}}
+set a(0-1564) {NAME FRAME:not#16 TYPE NOT PAR 0-1277 XREFS 10589 LOC {1 0.596016025 1 0.89803165 1 0.89803165 2 0.674690025} PREDS {{146 0 0-1454 {}} {259 0 0-1563 {}}} SUCCS {{259 0 0-1565 {}}} CYCLES {}}
+set a(0-1565) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,5) AREA_SCORE 5.30 QUANTITY 9 NAME FRAME:acc#24 TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-1277 XREFS 10590 LOC {1 0.86271455 1 0.89803165 1 0.89803165 1 0.9515553149089293 2 0.7282136899089293} PREDS {{146 0 0-1454 {}} {258 0 0-1562 {}} {259 0 0-1564 {}}} SUCCS {{258 0 0-1568 {}}} CYCLES {}}
+set a(0-1566) {NAME FRAME:slc(acc.imod#2)#4 TYPE READSLICE PAR 0-1277 XREFS 10591 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.72821375} PREDS {{146 0 0-1454 {}} {258 0 0-1529 {}}} SUCCS {{259 0 0-1567 {}}} CYCLES {}}
+set a(0-1567) {NAME FRAME:conc#71 TYPE CONCATENATE PAR 0-1277 XREFS 10592 LOC {1 0.7607461999999999 1 0.951555375 1 0.951555375 2 0.72821375} PREDS {{146 0 0-1454 {}} {259 0 0-1566 {}}} SUCCS {{259 0 0-1568 {}}} CYCLES {}}
+set a(0-1568) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,1,5,1,6) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#25 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-1277 XREFS 10593 LOC {1 0.916238275 1 0.951555375 1 0.951555375 1 0.999999959496936 2 0.776658334496936} PREDS {{146 0 0-1454 {}} {258 0 0-1565 {}} {259 0 0-1567 {}}} SUCCS {{259 0 0-1569 {}}} CYCLES {}}
+set a(0-1569) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#26 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-1277 XREFS 10594 LOC {2 0.0 2 0.776658375 2 0.776658375 2 0.8199983407468815 2 0.8199983407468815} PREDS {{146 0 0-1454 {}} {258 0 0-1541 {}} {259 0 0-1568 {}}} SUCCS {{259 0 0-1570 {}}} CYCLES {}}
+set a(0-1570) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#27 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-1277 XREFS 10595 LOC {2 0.043340025 2 0.8199984 2 0.8199984 2 0.88702675686502 2 0.88702675686502} PREDS {{146 0 0-1454 {}} {258 0 0-1540 {}} {259 0 0-1569 {}}} SUCCS {{258 0 0-1573 {}}} CYCLES {}}
+set a(0-1571) {NAME FRAME:slc(green)#9 TYPE READSLICE PAR 0-1277 XREFS 10596 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.6982106499999999} PREDS {{146 0 0-1454 {}} {258 0 0-1482 {}}} SUCCS {{259 0 0-1572 {}}} CYCLES {}}
+set a(0-1572) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,1,9,0,12) AREA_SCORE 335.00 QUANTITY 2 NAME FRAME:mul#3 TYPE MUL DELAY {3.02 ns} LIBRARY_DELAY {3.02 ns} PAR 0-1277 XREFS 10597 LOC {1 0.596016025 1 0.8111838499999999 1 0.8111838499999999 1 0.9999999556361009 2 0.8870267556361009} PREDS {{146 0 0-1454 {}} {259 0 0-1571 {}}} SUCCS {{259 0 0-1573 {}}} CYCLES {}}
+set a(0-1573) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME FRAME:acc#3 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-1277 XREFS 10598 LOC {2 0.11036842499999999 2 0.8870268 2 0.8870268 2 0.9665150034997777 2 0.9665150034997777} PREDS {{146 0 0-1454 {}} {258 0 0-1570 {}} {259 0 0-1572 {}}} SUCCS {{258 0 0-1630 {}} {258 0 0-1633 {}}} CYCLES {}}
+set a(0-1574) {NAME FRAME:slc(blue)#3 TYPE READSLICE PAR 0-1277 XREFS 10599 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.45012332499999996} PREDS {{146 0 0-1454 {}} {258 0 0-1496 {}}} SUCCS {{259 0 0-1575 {}}} CYCLES {}}
+set a(0-1575) {NAME FRAME:not#20 TYPE NOT PAR 0-1277 XREFS 10600 LOC {1 0.596016025 1 0.6567224749999999 1 0.6567224749999999 2 0.45012332499999996} PREDS {{146 0 0-1454 {}} {259 0 0-1574 {}}} SUCCS {{258 0 0-1577 {}}} CYCLES {}}
+set a(0-1576) {NAME FRAME:slc(blue)#4 TYPE READSLICE PAR 0-1277 XREFS 10601 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.45012332499999996} PREDS {{146 0 0-1454 {}} {258 0 0-1496 {}}} SUCCS {{259 0 0-1577 {}}} CYCLES {}}
+set a(0-1577) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 4 NAME FRAME:acc#28 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-1277 XREFS 10602 LOC {1 0.596016025 1 0.6567224749999999 1 0.6567224749999999 1 0.6839683520708271 2 0.4773692020708271} PREDS {{146 0 0-1454 {}} {258 0 0-1575 {}} {259 0 0-1576 {}}} SUCCS {{259 0 0-1578 {}}} CYCLES {}}
+set a(0-1578) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,1,5,1,6) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#31 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-1277 XREFS 10603 LOC {1 0.62326195 1 0.6839683999999999 1 0.6839683999999999 1 0.732412984496936 2 0.5258138344969361} PREDS {{146 0 0-1454 {}} {259 0 0-1577 {}}} SUCCS {{258 0 0-1585 {}}} CYCLES {}}
+set a(0-1579) {NAME FRAME:slc(blue)#1 TYPE READSLICE PAR 0-1277 XREFS 10604 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.424733975} PREDS {{146 0 0-1454 {}} {258 0 0-1496 {}}} SUCCS {{259 0 0-1580 {}}} CYCLES {}}
+set a(0-1580) {NAME FRAME:not#19 TYPE NOT PAR 0-1277 XREFS 10605 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.424733975} PREDS {{146 0 0-1454 {}} {259 0 0-1579 {}}} SUCCS {{258 0 0-1582 {}}} CYCLES {}}
+set a(0-1581) {NAME FRAME:slc(blue)#2 TYPE READSLICE PAR 0-1277 XREFS 10606 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.424733975} PREDS {{146 0 0-1454 {}} {258 0 0-1496 {}}} SUCCS {{259 0 0-1582 {}}} CYCLES {}}
+set a(0-1582) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 3 NAME FRAME:acc#29 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1277 XREFS 10607 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 1 0.6788892520708271 2 0.47229010207082717} PREDS {{146 0 0-1454 {}} {258 0 0-1580 {}} {259 0 0-1581 {}}} SUCCS {{258 0 0-1584 {}}} CYCLES {}}
+set a(0-1583) {NAME FRAME:slc(blue) TYPE READSLICE PAR 0-1277 XREFS 10608 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.47229014999999996} PREDS {{146 0 0-1454 {}} {258 0 0-1496 {}}} SUCCS {{259 0 0-1584 {}}} CYCLES {}}
+set a(0-1584) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,5) AREA_SCORE 5.30 QUANTITY 9 NAME FRAME:acc#30 TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-1277 XREFS 10609 LOC {1 0.6435721999999999 1 0.6788892999999999 1 0.6788892999999999 1 0.7324129649089293 2 0.5258138149089293} PREDS {{146 0 0-1454 {}} {258 0 0-1582 {}} {259 0 0-1583 {}}} SUCCS {{259 0 0-1585 {}}} CYCLES {}}
+set a(0-1585) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME FRAME:acc#11 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-1277 XREFS 10610 LOC {1 0.697095925 1 0.7324130249999999 1 0.7324130249999999 1 0.7960632407468814 2 0.5894640907468814} PREDS {{146 0 0-1454 {}} {258 0 0-1578 {}} {259 0 0-1584 {}}} SUCCS {{259 0 0-1586 {}} {258 0 0-1588 {}} {258 0 0-1590 {}} {258 0 0-1638 {}} {258 0 0-1646 {}} {258 0 0-1662 {}}} CYCLES {}}
+set a(0-1586) {NAME FRAME:slc(acc.imod#4)#7 TYPE READSLICE PAR 0-1277 XREFS 10611 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.58946415} PREDS {{146 0 0-1454 {}} {259 0 0-1585 {}}} SUCCS {{259 0 0-1587 {}}} CYCLES {}}
+set a(0-1587) {NAME FRAME:conc#75 TYPE CONCATENATE PAR 0-1277 XREFS 10612 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.58946415} PREDS {{146 0 0-1454 {}} {259 0 0-1586 {}}} SUCCS {{258 0 0-1593 {}}} CYCLES {}}
+set a(0-1588) {NAME FRAME:slc(acc.imod#4)#2 TYPE READSLICE PAR 0-1277 XREFS 10613 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.58946415} PREDS {{146 0 0-1454 {}} {258 0 0-1585 {}}} SUCCS {{259 0 0-1589 {}}} CYCLES {}}
+set a(0-1589) {NAME FRAME:not#22 TYPE NOT PAR 0-1277 XREFS 10614 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.58946415} PREDS {{146 0 0-1454 {}} {259 0 0-1588 {}}} SUCCS {{258 0 0-1592 {}}} CYCLES {}}
+set a(0-1590) {NAME FRAME:slc(acc.imod#4) TYPE READSLICE PAR 0-1277 XREFS 10615 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.58946415} PREDS {{146 0 0-1454 {}} {258 0 0-1585 {}}} SUCCS {{259 0 0-1591 {}}} CYCLES {}}
+set a(0-1591) {NAME FRAME:not#21 TYPE NOT PAR 0-1277 XREFS 10616 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.58946415} PREDS {{146 0 0-1454 {}} {259 0 0-1590 {}}} SUCCS {{259 0 0-1592 {}}} CYCLES {}}
+set a(0-1592) {NAME FRAME:conc#76 TYPE CONCATENATE PAR 0-1277 XREFS 10617 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.58946415} PREDS {{146 0 0-1454 {}} {258 0 0-1589 {}} {259 0 0-1591 {}}} SUCCS {{259 0 0-1593 {}}} CYCLES {}}
+set a(0-1593) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,1,5,1,6) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#32 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-1277 XREFS 10618 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 1 0.844507884496936 2 0.6379087344969361} PREDS {{146 0 0-1454 {}} {258 0 0-1587 {}} {259 0 0-1592 {}}} SUCCS {{259 0 0-1594 {}}} CYCLES {}}
+set a(0-1594) {NAME FRAME:slc#5 TYPE READSLICE PAR 0-1277 XREFS 10619 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {259 0 0-1593 {}}} SUCCS {{258 0 0-1640 {}} {258 0 0-1648 {}} {258 0 0-1650 {}} {258 0 0-1651 {}} {258 0 0-1652 {}}} CYCLES {}}
+set a(0-1595) {NAME FRAME:slc(red)#8 TYPE READSLICE PAR 0-1277 XREFS 10620 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.640265525} PREDS {{146 0 0-1454 {}} {258 0 0-1468 {}}} SUCCS {{259 0 0-1596 {}}} CYCLES {}}
+set a(0-1596) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-1277 XREFS 10621 LOC {1 0.596016025 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.8181473171744312} PREDS {{146 0 0-1454 {}} {259 0 0-1595 {}}} SUCCS {{258 0 0-1626 {}}} CYCLES {}}
+set a(0-1597) {NAME FRAME:slc(red)#10 TYPE READSLICE PAR 0-1277 XREFS 10622 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.77480735} PREDS {{146 0 0-1454 {}} {258 0 0-1468 {}}} SUCCS {{258 0 0-1625 {}}} CYCLES {}}
+set a(0-1598) {NAME FRAME:slc(acc.imod)#6 TYPE READSLICE PAR 0-1277 XREFS 10623 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1508 {}}} SUCCS {{259 0 0-1599 {}}} CYCLES {}}
+set a(0-1599) {NAME FRAME:not#8 TYPE NOT PAR 0-1277 XREFS 10624 LOC {1 0.7607461999999999 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {259 0 0-1598 {}}} SUCCS {{258 0 0-1604 {}}} CYCLES {}}
+set a(0-1600) {NAME FRAME:slc(acc.imod#1) TYPE READSLICE PAR 0-1277 XREFS 10625 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1517 {}}} SUCCS {{258 0 0-1603 {}}} CYCLES {}}
+set a(0-1601) {NAME FRAME:slc(red)#5 TYPE READSLICE PAR 0-1277 XREFS 10626 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1468 {}}} SUCCS {{259 0 0-1602 {}}} CYCLES {}}
+set a(0-1602) {NAME FRAME:not#5 TYPE NOT PAR 0-1277 XREFS 10627 LOC {1 0.596016025 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {259 0 0-1601 {}}} SUCCS {{259 0 0-1603 {}}} CYCLES {}}
+set a(0-1603) {NAME FRAME:nand TYPE NAND PAR 0-1277 XREFS 10628 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1600 {}} {259 0 0-1602 {}}} SUCCS {{259 0 0-1604 {}}} CYCLES {}}
+set a(0-1604) {NAME FRAME:conc#7 TYPE CONCATENATE PAR 0-1277 XREFS 10629 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1599 {}} {259 0 0-1603 {}}} SUCCS {{259 0 0-1605 {}}} CYCLES {}}
+set a(0-1605) {NAME FRAME:conc#78 TYPE CONCATENATE PAR 0-1277 XREFS 10630 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {259 0 0-1604 {}}} SUCCS {{258 0 0-1617 {}}} CYCLES {}}
+set a(0-1606) {NAME FRAME:slc(acc.imod)#5 TYPE READSLICE PAR 0-1277 XREFS 10631 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1508 {}}} SUCCS {{258 0 0-1616 {}}} CYCLES {}}
+set a(0-1607) {NAME FRAME:slc(red)#6 TYPE READSLICE PAR 0-1277 XREFS 10632 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1468 {}}} SUCCS {{258 0 0-1615 {}}} CYCLES {}}
+set a(0-1608) {NAME FRAME:slc(acc.imod#1)#1 TYPE READSLICE PAR 0-1277 XREFS 10633 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1517 {}}} SUCCS {{259 0 0-1609 {}}} CYCLES {}}
+set a(0-1609) {NAME FRAME:not#6 TYPE NOT PAR 0-1277 XREFS 10634 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {259 0 0-1608 {}}} SUCCS {{258 0 0-1615 {}}} CYCLES {}}
+set a(0-1610) {NAME FRAME:slc(acc.imod#1)#2 TYPE READSLICE PAR 0-1277 XREFS 10635 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1517 {}}} SUCCS {{258 0 0-1614 {}}} CYCLES {}}
+set a(0-1611) {NAME FRAME:slc(acc.imod#1)#3 TYPE READSLICE PAR 0-1277 XREFS 10636 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1517 {}}} SUCCS {{258 0 0-1614 {}}} CYCLES {}}
+set a(0-1612) {NAME FRAME:slc(acc.imod#1)#4 TYPE READSLICE PAR 0-1277 XREFS 10637 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1517 {}}} SUCCS {{258 0 0-1614 {}}} CYCLES {}}
+set a(0-1613) {NAME FRAME:slc(red)#23 TYPE READSLICE PAR 0-1277 XREFS 10638 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1468 {}}} SUCCS {{259 0 0-1614 {}}} CYCLES {}}
+set a(0-1614) {NAME FRAME:or TYPE OR PAR 0-1277 XREFS 10639 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1612 {}} {258 0 0-1611 {}} {258 0 0-1610 {}} {259 0 0-1613 {}}} SUCCS {{259 0 0-1615 {}}} CYCLES {}}
+set a(0-1615) {NAME and#1 TYPE AND PAR 0-1277 XREFS 10640 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1609 {}} {258 0 0-1607 {}} {259 0 0-1614 {}}} SUCCS {{259 0 0-1616 {}}} CYCLES {}}
+set a(0-1616) {NAME FRAME:conc#79 TYPE CONCATENATE PAR 0-1277 XREFS 10641 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.6193152749999999} PREDS {{146 0 0-1454 {}} {258 0 0-1606 {}} {259 0 0-1615 {}}} SUCCS {{259 0 0-1617 {}}} CYCLES {}}
+set a(0-1617) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,5) AREA_SCORE 5.30 QUANTITY 9 NAME FRAME:acc#33 TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-1277 XREFS 10642 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 1 0.8980315899089293 2 0.6728389399089293} PREDS {{146 0 0-1454 {}} {258 0 0-1605 {}} {259 0 0-1616 {}}} SUCCS {{259 0 0-1618 {}}} CYCLES {}}
+set a(0-1618) {NAME FRAME:slc#6 TYPE READSLICE PAR 0-1277 XREFS 10643 LOC {1 0.86271455 1 0.89803165 1 0.89803165 2 0.672839} PREDS {{146 0 0-1454 {}} {259 0 0-1617 {}}} SUCCS {{258 0 0-1621 {}}} CYCLES {}}
+set a(0-1619) {NAME FRAME:slc(red)#7 TYPE READSLICE PAR 0-1277 XREFS 10644 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.672839} PREDS {{146 0 0-1454 {}} {258 0 0-1468 {}}} SUCCS {{259 0 0-1620 {}}} CYCLES {}}
+set a(0-1620) {NAME FRAME:not#7 TYPE NOT PAR 0-1277 XREFS 10645 LOC {1 0.596016025 1 0.89803165 1 0.89803165 2 0.672839} PREDS {{146 0 0-1454 {}} {259 0 0-1619 {}}} SUCCS {{259 0 0-1621 {}}} CYCLES {}}
+set a(0-1621) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,5) AREA_SCORE 5.30 QUANTITY 9 NAME FRAME:acc#34 TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-1277 XREFS 10646 LOC {1 0.86271455 1 0.89803165 1 0.89803165 1 0.9515553149089293 2 0.7263626649089293} PREDS {{146 0 0-1454 {}} {258 0 0-1618 {}} {259 0 0-1620 {}}} SUCCS {{258 0 0-1624 {}}} CYCLES {}}
+set a(0-1622) {NAME FRAME:slc(acc.imod)#4 TYPE READSLICE PAR 0-1277 XREFS 10647 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.726362725} PREDS {{146 0 0-1454 {}} {258 0 0-1508 {}}} SUCCS {{259 0 0-1623 {}}} CYCLES {}}
+set a(0-1623) {NAME FRAME:conc#77 TYPE CONCATENATE PAR 0-1277 XREFS 10648 LOC {1 0.7607461999999999 1 0.951555375 1 0.951555375 2 0.726362725} PREDS {{146 0 0-1454 {}} {259 0 0-1622 {}}} SUCCS {{259 0 0-1624 {}}} CYCLES {}}
+set a(0-1624) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,1,5,1,6) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#35 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-1277 XREFS 10649 LOC {1 0.916238275 1 0.951555375 1 0.951555375 1 0.999999959496936 2 0.7748073094969361} PREDS {{146 0 0-1454 {}} {258 0 0-1621 {}} {259 0 0-1623 {}}} SUCCS {{259 0 0-1625 {}}} CYCLES {}}
+set a(0-1625) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#36 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-1277 XREFS 10650 LOC {2 0.0 2 0.77480735 2 0.77480735 2 0.8181473157468815 2 0.8181473157468815} PREDS {{146 0 0-1454 {}} {258 0 0-1597 {}} {259 0 0-1624 {}}} SUCCS {{259 0 0-1626 {}}} CYCLES {}}
+set a(0-1626) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#37 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-1277 XREFS 10651 LOC {2 0.043340025 2 0.818147375 2 0.818147375 2 0.88517573186502 2 0.88517573186502} PREDS {{146 0 0-1454 {}} {258 0 0-1596 {}} {259 0 0-1625 {}}} SUCCS {{258 0 0-1629 {}}} CYCLES {}}
+set a(0-1627) {NAME FRAME:slc(red)#9 TYPE READSLICE PAR 0-1277 XREFS 10652 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.6928151} PREDS {{146 0 0-1454 {}} {258 0 0-1468 {}}} SUCCS {{259 0 0-1628 {}}} CYCLES {}}
+set a(0-1628) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,1,9,0,10) AREA_SCORE 331.00 QUANTITY 1 NAME FRAME:mul#1 TYPE MUL DELAY {3.08 ns} LIBRARY_DELAY {3.08 ns} PAR 0-1277 XREFS 10653 LOC {1 0.596016025 1 0.8076393249999999 1 0.8076393249999999 1 0.999999945162675 2 0.8851757201626751} PREDS {{146 0 0-1454 {}} {259 0 0-1627 {}}} SUCCS {{259 0 0-1629 {}}} CYCLES {}}
+set a(0-1629) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,10) AREA_SCORE 11.24 QUANTITY 1 NAME FRAME:acc#2 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-1277 XREFS 10654 LOC {2 0.11036842499999999 2 0.885175775 2 0.885175775 2 0.9665150033364113 2 0.9665150033364113} PREDS {{146 0 0-1454 {}} {258 0 0-1626 {}} {259 0 0-1628 {}}} SUCCS {{258 0 0-1632 {}}} CYCLES {}}
+set a(0-1630) {NAME FRAME:slc(green)#12 TYPE READSLICE PAR 0-1277 XREFS 10655 LOC {2 0.189856675 2 0.9665150499999999 2 0.9665150499999999 2 0.9665150499999999} PREDS {{146 0 0-1454 {}} {258 0 0-1573 {}}} SUCCS {{259 0 0-1631 {}}} CYCLES {}}
+set a(0-1631) {NAME FRAME:exs#6 TYPE SIGNEXTEND PAR 0-1277 XREFS 10656 LOC {2 0.189856675 2 0.9665150499999999 2 0.9665150499999999 2 0.9665150499999999} PREDS {{146 0 0-1454 {}} {259 0 0-1630 {}}} SUCCS {{259 0 0-1632 {}}} CYCLES {}}
+set a(0-1632) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(10,2) AREA_SCORE 7.30 QUANTITY 1 NAME FRAME:or#4 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-1277 XREFS 10657 LOC {2 0.19170769999999998 2 0.9665150499999999 2 0.9665150499999999 2 0.9832574811077388 2 0.9832574811077388} PREDS {{146 0 0-1454 {}} {258 0 0-1629 {}} {259 0 0-1631 {}}} SUCCS {{258 0 0-1634 {}}} CYCLES {}}
+set a(0-1633) {NAME FRAME:slc(green)#13 TYPE READSLICE PAR 0-1277 XREFS 10658 LOC {2 0.189856675 2 0.9665150499999999 2 0.9665150499999999 2 0.983257525} PREDS {{146 0 0-1454 {}} {258 0 0-1573 {}}} SUCCS {{259 0 0-1634 {}}} CYCLES {}}
+set a(0-1634) {NAME FRAME:conc#32 TYPE CONCATENATE PAR 0-1277 XREFS 10659 LOC {2 0.208450175 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-1454 {}} {258 0 0-1632 {}} {259 0 0-1633 {}}} SUCCS {{258 0 0-1671 {}}} CYCLES {}}
+set a(0-1635) {NAME FRAME:slc(blue)#8 TYPE READSLICE PAR 0-1277 XREFS 10660 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.6588590249999999} PREDS {{146 0 0-1454 {}} {258 0 0-1496 {}}} SUCCS {{259 0 0-1636 {}}} CYCLES {}}
+set a(0-1636) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#4 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-1277 XREFS 10661 LOC {1 0.596016025 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.8367408171744312} PREDS {{146 0 0-1454 {}} {259 0 0-1635 {}}} SUCCS {{258 0 0-1666 {}}} CYCLES {}}
+set a(0-1637) {NAME FRAME:slc(blue)#10 TYPE READSLICE PAR 0-1277 XREFS 10662 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.7934008499999999} PREDS {{146 0 0-1454 {}} {258 0 0-1496 {}}} SUCCS {{258 0 0-1665 {}}} CYCLES {}}
+set a(0-1638) {NAME FRAME:slc(acc.imod#4)#6 TYPE READSLICE PAR 0-1277 XREFS 10663 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1585 {}}} SUCCS {{259 0 0-1639 {}}} CYCLES {}}
+set a(0-1639) {NAME FRAME:not#26 TYPE NOT PAR 0-1277 XREFS 10664 LOC {1 0.7607461999999999 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {259 0 0-1638 {}}} SUCCS {{258 0 0-1644 {}}} CYCLES {}}
+set a(0-1640) {NAME FRAME:slc(acc.imod#5) TYPE READSLICE PAR 0-1277 XREFS 10665 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1594 {}}} SUCCS {{258 0 0-1643 {}}} CYCLES {}}
+set a(0-1641) {NAME FRAME:slc(blue)#5 TYPE READSLICE PAR 0-1277 XREFS 10666 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1496 {}}} SUCCS {{259 0 0-1642 {}}} CYCLES {}}
+set a(0-1642) {NAME FRAME:not#23 TYPE NOT PAR 0-1277 XREFS 10667 LOC {1 0.596016025 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {259 0 0-1641 {}}} SUCCS {{259 0 0-1643 {}}} CYCLES {}}
+set a(0-1643) {NAME FRAME:nand#2 TYPE NAND PAR 0-1277 XREFS 10668 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1640 {}} {259 0 0-1642 {}}} SUCCS {{259 0 0-1644 {}}} CYCLES {}}
+set a(0-1644) {NAME FRAME:conc#23 TYPE CONCATENATE PAR 0-1277 XREFS 10669 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1639 {}} {259 0 0-1643 {}}} SUCCS {{259 0 0-1645 {}}} CYCLES {}}
+set a(0-1645) {NAME FRAME:conc#81 TYPE CONCATENATE PAR 0-1277 XREFS 10670 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {259 0 0-1644 {}}} SUCCS {{258 0 0-1657 {}}} CYCLES {}}
+set a(0-1646) {NAME FRAME:slc(acc.imod#4)#5 TYPE READSLICE PAR 0-1277 XREFS 10671 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1585 {}}} SUCCS {{258 0 0-1656 {}}} CYCLES {}}
+set a(0-1647) {NAME FRAME:slc(blue)#6 TYPE READSLICE PAR 0-1277 XREFS 10672 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1496 {}}} SUCCS {{258 0 0-1655 {}}} CYCLES {}}
+set a(0-1648) {NAME FRAME:slc(acc.imod#5)#1 TYPE READSLICE PAR 0-1277 XREFS 10673 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1594 {}}} SUCCS {{259 0 0-1649 {}}} CYCLES {}}
+set a(0-1649) {NAME FRAME:not#24 TYPE NOT PAR 0-1277 XREFS 10674 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {259 0 0-1648 {}}} SUCCS {{258 0 0-1655 {}}} CYCLES {}}
+set a(0-1650) {NAME FRAME:slc(acc.imod#5)#2 TYPE READSLICE PAR 0-1277 XREFS 10675 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1594 {}}} SUCCS {{258 0 0-1654 {}}} CYCLES {}}
+set a(0-1651) {NAME FRAME:slc(acc.imod#5)#3 TYPE READSLICE PAR 0-1277 XREFS 10676 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1594 {}}} SUCCS {{258 0 0-1654 {}}} CYCLES {}}
+set a(0-1652) {NAME FRAME:slc(acc.imod#5)#4 TYPE READSLICE PAR 0-1277 XREFS 10677 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1594 {}}} SUCCS {{258 0 0-1654 {}}} CYCLES {}}
+set a(0-1653) {NAME FRAME:slc(blue)#23 TYPE READSLICE PAR 0-1277 XREFS 10678 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1496 {}}} SUCCS {{259 0 0-1654 {}}} CYCLES {}}
+set a(0-1654) {NAME FRAME:or#2 TYPE OR PAR 0-1277 XREFS 10679 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1652 {}} {258 0 0-1651 {}} {258 0 0-1650 {}} {259 0 0-1653 {}}} SUCCS {{259 0 0-1655 {}}} CYCLES {}}
+set a(0-1655) {NAME and#5 TYPE AND PAR 0-1277 XREFS 10680 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1649 {}} {258 0 0-1647 {}} {259 0 0-1654 {}}} SUCCS {{259 0 0-1656 {}}} CYCLES {}}
+set a(0-1656) {NAME FRAME:conc#82 TYPE CONCATENATE PAR 0-1277 XREFS 10681 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 2 0.637908775} PREDS {{146 0 0-1454 {}} {258 0 0-1646 {}} {259 0 0-1655 {}}} SUCCS {{259 0 0-1657 {}}} CYCLES {}}
+set a(0-1657) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,5) AREA_SCORE 5.30 QUANTITY 9 NAME FRAME:acc#38 TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-1277 XREFS 10682 LOC {1 0.809190825 1 0.8445079249999999 1 0.8445079249999999 1 0.8980315899089293 2 0.6914324399089293} PREDS {{146 0 0-1454 {}} {258 0 0-1645 {}} {259 0 0-1656 {}}} SUCCS {{259 0 0-1658 {}}} CYCLES {}}
+set a(0-1658) {NAME FRAME:slc#7 TYPE READSLICE PAR 0-1277 XREFS 10683 LOC {1 0.86271455 1 0.89803165 1 0.89803165 2 0.6914325} PREDS {{146 0 0-1454 {}} {259 0 0-1657 {}}} SUCCS {{258 0 0-1661 {}}} CYCLES {}}
+set a(0-1659) {NAME FRAME:slc(blue)#7 TYPE READSLICE PAR 0-1277 XREFS 10684 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.6914325} PREDS {{146 0 0-1454 {}} {258 0 0-1496 {}}} SUCCS {{259 0 0-1660 {}}} CYCLES {}}
+set a(0-1660) {NAME FRAME:not#25 TYPE NOT PAR 0-1277 XREFS 10685 LOC {1 0.596016025 1 0.89803165 1 0.89803165 2 0.6914325} PREDS {{146 0 0-1454 {}} {259 0 0-1659 {}}} SUCCS {{259 0 0-1661 {}}} CYCLES {}}
+set a(0-1661) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,5) AREA_SCORE 5.30 QUANTITY 9 NAME FRAME:acc#39 TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-1277 XREFS 10686 LOC {1 0.86271455 1 0.89803165 1 0.89803165 1 0.9515553149089293 2 0.7449561649089294} PREDS {{146 0 0-1454 {}} {258 0 0-1658 {}} {259 0 0-1660 {}}} SUCCS {{258 0 0-1664 {}}} CYCLES {}}
+set a(0-1662) {NAME FRAME:slc(acc.imod#4)#4 TYPE READSLICE PAR 0-1277 XREFS 10687 LOC {1 0.7607461999999999 1 0.7960632999999999 1 0.7960632999999999 2 0.7449562249999999} PREDS {{146 0 0-1454 {}} {258 0 0-1585 {}}} SUCCS {{259 0 0-1663 {}}} CYCLES {}}
+set a(0-1663) {NAME FRAME:conc#80 TYPE CONCATENATE PAR 0-1277 XREFS 10688 LOC {1 0.7607461999999999 1 0.951555375 1 0.951555375 2 0.7449562249999999} PREDS {{146 0 0-1454 {}} {259 0 0-1662 {}}} SUCCS {{259 0 0-1664 {}}} CYCLES {}}
+set a(0-1664) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,1,5,1,6) AREA_SCORE 6.00 QUANTITY 9 NAME FRAME:acc#40 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-1277 XREFS 10689 LOC {1 0.916238275 1 0.951555375 1 0.951555375 1 0.999999959496936 2 0.793400809496936} PREDS {{146 0 0-1454 {}} {258 0 0-1661 {}} {259 0 0-1663 {}}} SUCCS {{259 0 0-1665 {}}} CYCLES {}}
+set a(0-1665) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#41 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-1277 XREFS 10690 LOC {2 0.0 2 0.7934008499999999 2 0.7934008499999999 2 0.8367408157468814 2 0.8367408157468814} PREDS {{146 0 0-1454 {}} {258 0 0-1637 {}} {259 0 0-1664 {}}} SUCCS {{259 0 0-1666 {}}} CYCLES {}}
+set a(0-1666) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#42 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-1277 XREFS 10691 LOC {2 0.043340025 2 0.8367408749999999 2 0.8367408749999999 2 0.9037692318650199 2 0.9037692318650199} PREDS {{146 0 0-1454 {}} {258 0 0-1636 {}} {259 0 0-1665 {}}} SUCCS {{258 0 0-1669 {}}} CYCLES {}}
+set a(0-1667) {NAME FRAME:slc(blue)#9 TYPE READSLICE PAR 0-1277 XREFS 10692 LOC {1 0.596016025 1 0.6313331249999999 1 0.6313331249999999 2 0.714953125} PREDS {{146 0 0-1454 {}} {258 0 0-1496 {}}} SUCCS {{259 0 0-1668 {}}} CYCLES {}}
+set a(0-1668) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,1,9,0,12) AREA_SCORE 335.00 QUANTITY 2 NAME FRAME:mul#5 TYPE MUL DELAY {3.02 ns} LIBRARY_DELAY {3.02 ns} PAR 0-1277 XREFS 10693 LOC {1 0.596016025 1 0.8111838499999999 1 0.8111838499999999 1 0.9999999556361009 2 0.9037692306361009} PREDS {{146 0 0-1454 {}} {259 0 0-1667 {}}} SUCCS {{259 0 0-1669 {}}} CYCLES {}}
+set a(0-1669) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 5 NAME FRAME:acc#4 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-1277 XREFS 10694 LOC {2 0.11036842499999999 2 0.9037692749999999 2 0.9037692749999999 2 0.9832574784997776 2 0.9832574784997776} PREDS {{146 0 0-1454 {}} {258 0 0-1666 {}} {259 0 0-1668 {}}} SUCCS {{259 0 0-1670 {}}} CYCLES {}}
+set a(0-1670) {NAME FRAME:exs#5 TYPE SIGNEXTEND PAR 0-1277 XREFS 10695 LOC {2 0.189856675 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-1454 {}} {259 0 0-1669 {}}} SUCCS {{259 0 0-1671 {}}} CYCLES {}}
+set a(0-1671) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(30,2) AREA_SCORE 21.89 QUANTITY 1 NAME FRAME:or#3 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-1277 XREFS 10696 LOC {2 0.208450175 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{146 0 0-1454 {}} {258 0 0-1634 {}} {259 0 0-1670 {}}} SUCCS {{259 0 0-1672 {}}} CYCLES {}}
+set a(0-1672) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(2,30) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_write(vout:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-1277 XREFS 10697 LOC {2 1.0 2 1.0 2 1.0 3 0.0 2 0.9999} PREDS {{130 0 0-1454 {}} {260 0 0-1672 {}} {259 0 0-1671 {}}} SUCCS {{260 0 0-1672 {}}} CYCLES {}}
+set a(0-1673) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(19,0,2,1,19) AREA_SCORE 20.00 QUANTITY 1 NAME FRAME:acc#6 TYPE ACCU DELAY {1.91 ns} LIBRARY_DELAY {1.91 ns} PAR 0-1277 XREFS 10698 LOC {1 0.08443574999999999 1 0.784864825 1 0.784864825 1 0.9041241410815966 2 0.6296118160815966} PREDS {{146 0 0-1454 {}} {258 0 0-1292 {}}} SUCCS {{259 0 0-1674 {}} {258 0 0-1693 {}}} CYCLES {}}
+set a(0-1674) {NAME FRAME:p:slc(FRAME:p)#1 TYPE READSLICE PAR 0-1277 XREFS 10699 LOC {1 0.203695125 1 0.9041241999999999 1 0.9041241999999999 2 0.6296118749999999} PREDS {{146 0 0-1454 {}} {259 0 0-1673 {}}} SUCCS {{259 0 0-1675 {}}} CYCLES {}}
+set a(0-1675) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,7,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME FRAME:acc TYPE ACCU DELAY {1.17 ns} LIBRARY_DELAY {1.17 ns} PAR 0-1277 XREFS 10700 LOC {1 0.203695125 1 0.9041241999999999 1 0.9041241999999999 1 0.9769393617915235 2 0.7024270367915235} PREDS {{146 0 0-1454 {}} {259 0 0-1674 {}}} SUCCS {{259 0 0-1676 {}}} CYCLES {}}
+set a(0-1676) {NAME FRAME:slc TYPE READSLICE PAR 0-1277 XREFS 10701 LOC {1 0.276510325 1 0.9769393999999999 1 0.9769393999999999 2 0.702427075} PREDS {{146 0 0-1454 {}} {259 0 0-1675 {}}} SUCCS {{259 0 0-1677 {}}} CYCLES {}}
+set a(0-1677) {NAME FRAME:not TYPE NOT PAR 0-1277 XREFS 10702 LOC {1 0.276510325 1 0.9769393999999999 1 0.9769393999999999 2 0.702427075} PREDS {{146 0 0-1454 {}} {259 0 0-1676 {}}} SUCCS {{258 0 0-1680 {}} {258 0 0-1681 {}}} CYCLES {}}
+set a(0-1678) {NAME not#1 TYPE NOT PAR 0-1277 XREFS 10703 LOC {1 0.0 1 0.0 1 0.0 2 0.702427075} PREDS {{258 0 0-1294 {}}} SUCCS {{259 0 0-1679 {}}} CYCLES {}}
+set a(0-1679) {NAME FRAME:for:and#2 TYPE AND PAR 0-1277 XREFS 10704 LOC {1 0.0 1 0.0 1 0.0 2 0.702427075} PREDS {{262 0 0-1695 {}} {259 0 0-1678 {}}} SUCCS {{259 0 0-1680 {}} {256 0 0-1695 {}}} CYCLES {}}
+set a(0-1680) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 2 NAME FRAME:for:mux#25 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-1277 XREFS 10705 LOC {1 0.276510325 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.7254876375} PREDS {{258 0 0-1453 {}} {258 0 0-1677 {}} {258 0 0-1278 {}} {259 0 0-1679 {}}} SUCCS {{258 0 0-1695 {}} {258 0 0-1697 {}}} CYCLES {}}
+set a(0-1681) {NAME not#2 TYPE NOT PAR 0-1277 XREFS 10706 LOC {1 0.276510325 1 0.9769393999999999 1 0.9769393999999999 2 0.702427075} PREDS {{258 0 0-1677 {}} {258 0 0-1278 {}}} SUCCS {{259 0 0-1682 {}}} CYCLES {}}
+set a(0-1682) {NAME FRAME:for:or#1 TYPE OR PAR 0-1277 XREFS 10707 LOC {1 0.276510325 1 0.9769393999999999 1 0.9769393999999999 2 0.702427075} PREDS {{258 0 0-1453 {}} {259 0 0-1681 {}}} SUCCS {{259 0 0-1683 {}}} CYCLES {}}
+set a(0-1683) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 2 NAME FRAME:for:mux#26 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-1277 XREFS 10708 LOC {1 0.276510325 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.7254876375} PREDS {{258 0 0-1453 {}} {259 0 0-1682 {}}} SUCCS {{258 0 0-1696 {}} {258 0 0-1697 {}}} CYCLES {}}
+set a(0-1684) {NAME FRAME:for:asn(regs.regs(0).sva) TYPE ASSIGN PAR 0-1277 XREFS 10709 LOC {1 0.0230606 1 0.0583777 1 0.0583777 2 0.725487675} PREDS {{260 0 0-1684 {}} {256 0 0-1351 {}} {256 0 0-1353 {}} {258 0 0-1352 {}}} SUCCS {{262 0 0-1351 {}} {262 0 0-1353 {}} {260 0 0-1684 {}}} CYCLES {}}
+set a(0-1685) {NAME FRAME:for:asn(regs.regs(1).sva) TYPE ASSIGN PAR 0-1277 XREFS 10710 LOC {1 0.0230606 1 0.0583777 1 0.0583777 2 0.725487675} PREDS {{260 0 0-1685 {}} {256 0 0-1300 {}} {256 0 0-1309 {}} {256 0 0-1318 {}} {256 0 0-1327 {}} {256 0 0-1336 {}} {256 0 0-1345 {}} {256 0 0-1354 {}} {256 0 0-1356 {}} {258 0 0-1355 {}}} SUCCS {{262 0 0-1300 {}} {262 0 0-1309 {}} {262 0 0-1318 {}} {262 0 0-1327 {}} {262 0 0-1336 {}} {262 0 0-1345 {}} {262 0 0-1354 {}} {262 0 0-1356 {}} {260 0 0-1685 {}}} CYCLES {}}
+set a(0-1686) {NAME FRAME:for:asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-1277 XREFS 10711 LOC {1 0.0230606 1 0.0583777 1 0.0583777 2 0.725487675} PREDS {{260 0 0-1686 {}} {258 0 0-1357 {}}} SUCCS {{262 0 0-1357 {}} {260 0 0-1686 {}}} CYCLES {}}
+set a(0-1687) {NAME FRAME:for:asn(r(0).lpi#1) TYPE ASSIGN PAR 0-1277 XREFS 10712 LOC {1 0.380514125 1 0.5257233499999999 1 0.5257233499999999 3 0.1714683} PREDS {{260 0 0-1687 {}} {256 0 0-1376 {}} {258 0 0-1383 {}}} SUCCS {{262 0 0-1376 {}} {260 0 0-1687 {}}} CYCLES {}}
+set a(0-1688) {NAME FRAME:for:asn(r(2).lpi#1) TYPE ASSIGN PAR 0-1277 XREFS 10713 LOC {1 0.380514125 1 0.41583122499999997 1 0.41583122499999997 3 0.061576175} PREDS {{260 0 0-1688 {}} {256 0 0-1423 {}} {258 0 0-1429 {}}} SUCCS {{262 0 0-1423 {}} {260 0 0-1688 {}}} CYCLES {}}
+set a(0-1689) {NAME FRAME:for:asn(g(0).lpi#1) TYPE ASSIGN PAR 0-1277 XREFS 10714 LOC {1 0.380514125 1 0.5257233499999999 1 0.5257233499999999 3 0.173319325} PREDS {{260 0 0-1689 {}} {256 0 0-1386 {}} {258 0 0-1393 {}}} SUCCS {{262 0 0-1386 {}} {260 0 0-1689 {}}} CYCLES {}}
+set a(0-1690) {NAME FRAME:for:asn(g(2).lpi#1) TYPE ASSIGN PAR 0-1277 XREFS 10715 LOC {1 0.380514125 1 0.41583122499999997 1 0.41583122499999997 3 0.0634272} PREDS {{260 0 0-1690 {}} {256 0 0-1432 {}} {258 0 0-1438 {}}} SUCCS {{262 0 0-1432 {}} {260 0 0-1690 {}}} CYCLES {}}
+set a(0-1691) {NAME FRAME:for:asn(b(0).lpi#1) TYPE ASSIGN PAR 0-1277 XREFS 10716 LOC {1 0.380514125 1 0.5257233499999999 1 0.5257233499999999 3 0.1900618} PREDS {{260 0 0-1691 {}} {256 0 0-1396 {}} {258 0 0-1403 {}}} SUCCS {{262 0 0-1396 {}} {260 0 0-1691 {}}} CYCLES {}}
+set a(0-1692) {NAME FRAME:for:asn(b(2).lpi#1) TYPE ASSIGN PAR 0-1277 XREFS 10717 LOC {1 0.380514125 1 0.41583122499999997 1 0.41583122499999997 3 0.080169675} PREDS {{260 0 0-1692 {}} {256 0 0-1441 {}} {258 0 0-1447 {}}} SUCCS {{262 0 0-1441 {}} {260 0 0-1692 {}}} CYCLES {}}
+set a(0-1693) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(19,1,2) AREA_SCORE 17.47 QUANTITY 1 NAME FRAME:for:mux#21 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-1277 XREFS 10718 LOC {1 0.203695125 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.49394568749999995} PREDS {{260 0 0-1693 {}} {258 0 0-1453 {}} {258 0 0-1292 {}} {258 0 0-1673 {}} {258 0 0-1279 {}}} SUCCS {{262 0 0-1292 {}} {260 0 0-1693 {}}} CYCLES {}}
+set a(0-1694) {NAME FRAME:for:asn(i#6.lpi#1) TYPE ASSIGN PAR 0-1277 XREFS 10719 LOC {1 0.057189825 1 0.30909705 1 0.30909705 2 0.7321415} PREDS {{260 0 0-1694 {}} {256 0 0-1360 {}} {258 0 0-1448 {}}} SUCCS {{262 0 0-1360 {}} {260 0 0-1694 {}}} CYCLES {}}
+set a(0-1695) {NAME FRAME:for:asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-1277 XREFS 10720 LOC {1 0.299570925 1 1.0 1 1.0 3 0.702427075} PREDS {{260 0 0-1695 {}} {256 0 0-1679 {}} {258 0 0-1680 {}}} SUCCS {{262 0 0-1679 {}} {260 0 0-1695 {}}} CYCLES {}}
+set a(0-1696) {NAME FRAME:for:asn(exit:FRAME:for.lpi#1) TYPE ASSIGN PAR 0-1277 XREFS 10721 LOC {1 0.299570925 1 1.0 1 1.0 2 0.725487675} PREDS {{260 0 0-1696 {}} {256 0 0-1294 {}} {258 0 0-1683 {}}} SUCCS {{262 0 0-1294 {}} {260 0 0-1696 {}}} CYCLES {}}
+set a(0-1697) {NAME FRAME:and TYPE AND PAR 0-1277 XREFS 10722 LOC {1 0.299570925 1 1.0 1 1.0 2 0.725487675} PREDS {{258 0 0-1680 {}} {258 0 0-1683 {}}} SUCCS {{259 0 0-1698 {}}} CYCLES {}}
+set a(0-1698) {NAME FRAME:asn#5 TYPE ASSIGN PAR 0-1277 XREFS 10723 LOC {1 0.299570925 1 1.0 1 1.0 2 0.725487675} PREDS {{260 0 0-1698 {}} {256 0 0-1287 {}} {256 0 0-1289 {}} {256 0 0-1293 {}} {259 0 0-1697 {}}} SUCCS {{262 0 0-1287 {}} {262 0 0-1289 {}} {262 0 0-1293 {}} {260 0 0-1698 {}}} CYCLES {}}
+set a(0-1277) {CHI {0-1278 0-1279 0-1280 0-1281 0-1282 0-1283 0-1284 0-1285 0-1286 0-1287 0-1288 0-1289 0-1290 0-1291 0-1292 0-1293 0-1294 0-1295 0-1296 0-1297 0-1298 0-1299 0-1300 0-1301 0-1302 0-1303 0-1304 0-1305 0-1306 0-1307 0-1308 0-1309 0-1310 0-1311 0-1312 0-1313 0-1314 0-1315 0-1316 0-1317 0-1318 0-1319 0-1320 0-1321 0-1322 0-1323 0-1324 0-1325 0-1326 0-1327 0-1328 0-1329 0-1330 0-1331 0-1332 0-1333 0-1334 0-1335 0-1336 0-1337 0-1338 0-1339 0-1340 0-1341 0-1342 0-1343 0-1344 0-1345 0-1346 0-1347 0-1348 0-1349 0-1350 0-1351 0-1352 0-1353 0-1354 0-1355 0-1356 0-1357 0-1358 0-1359 0-1360 0-1361 0-1362 0-1363 0-1364 0-1365 0-1366 0-1367 0-1368 0-1369 0-1370 0-1371 0-1372 0-1373 0-1374 0-1375 0-1376 0-1377 0-1378 0-1379 0-1380 0-1381 0-1382 0-1383 0-1384 0-1385 0-1386 0-1387 0-1388 0-1389 0-1390 0-1391 0-1392 0-1393 0-1394 0-1395 0-1396 0-1397 0-1398 0-1399 0-1400 0-1401 0-1402 0-1403 0-1404 0-1405 0-1406 0-1407 0-1408 0-1409 0-1410 0-1411 0-1412 0-1413 0-1414 0-1415 0-1416 0-1417 0-1418 0-1419 0-1420 0-1421 0-1422 0-1423 0-1424 0-1425 0-1426 0-1427 0-1428 0-1429 0-1430 0-1431 0-1432 0-1433 0-1434 0-1435 0-1436 0-1437 0-1438 0-1439 0-1440 0-1441 0-1442 0-1443 0-1444 0-1445 0-1446 0-1447 0-1448 0-1449 0-1450 0-1451 0-1452 0-1453 0-1454 0-1455 0-1456 0-1457 0-1458 0-1459 0-1460 0-1461 0-1462 0-1463 0-1464 0-1465 0-1466 0-1467 0-1468 0-1469 0-1470 0-1471 0-1472 0-1473 0-1474 0-1475 0-1476 0-1477 0-1478 0-1479 0-1480 0-1481 0-1482 0-1483 0-1484 0-1485 0-1486 0-1487 0-1488 0-1489 0-1490 0-1491 0-1492 0-1493 0-1494 0-1495 0-1496 0-1497 0-1498 0-1499 0-1500 0-1501 0-1502 0-1503 0-1504 0-1505 0-1506 0-1507 0-1508 0-1509 0-1510 0-1511 0-1512 0-1513 0-1514 0-1515 0-1516 0-1517 0-1518 0-1519 0-1520 0-1521 0-1522 0-1523 0-1524 0-1525 0-1526 0-1527 0-1528 0-1529 0-1530 0-1531 0-1532 0-1533 0-1534 0-1535 0-1536 0-1537 0-1538 0-1539 0-1540 0-1541 0-1542 0-1543 0-1544 0-1545 0-1546 0-1547 0-1548 0-1549 0-1550 0-1551 0-1552 0-1553 0-1554 0-1555 0-1556 0-1557 0-1558 0-1559 0-1560 0-1561 0-1562 0-1563 0-1564 0-1565 0-1566 0-1567 0-1568 0-1569 0-1570 0-1571 0-1572 0-1573 0-1574 0-1575 0-1576 0-1577 0-1578 0-1579 0-1580 0-1581 0-1582 0-1583 0-1584 0-1585 0-1586 0-1587 0-1588 0-1589 0-1590 0-1591 0-1592 0-1593 0-1594 0-1595 0-1596 0-1597 0-1598 0-1599 0-1600 0-1601 0-1602 0-1603 0-1604 0-1605 0-1606 0-1607 0-1608 0-1609 0-1610 0-1611 0-1612 0-1613 0-1614 0-1615 0-1616 0-1617 0-1618 0-1619 0-1620 0-1621 0-1622 0-1623 0-1624 0-1625 0-1626 0-1627 0-1628 0-1629 0-1630 0-1631 0-1632 0-1633 0-1634 0-1635 0-1636 0-1637 0-1638 0-1639 0-1640 0-1641 0-1642 0-1643 0-1644 0-1645 0-1646 0-1647 0-1648 0-1649 0-1650 0-1651 0-1652 0-1653 0-1654 0-1655 0-1656 0-1657 0-1658 0-1659 0-1660 0-1661 0-1662 0-1663 0-1664 0-1665 0-1666 0-1667 0-1668 0-1669 0-1670 0-1671 0-1672 0-1673 0-1674 0-1675 0-1676 0-1677 0-1678 0-1679 0-1680 0-1681 0-1682 0-1683 0-1684 0-1685 0-1686 0-1687 0-1688 0-1689 0-1690 0-1691 0-1692 0-1693 0-1694 0-1695 0-1696 0-1697 0-1698} ITERATIONS Infinite LATENCY 921601 RESET_LATENCY 0 CSTEPS 3 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 921600 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 3.0 CYCLES_IN 921602 TOTAL_CYCLES_IN 921602 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 921602 NAME main TYPE LOOP DELAY {18432060.00 ns} PAR 0-1262 XREFS 10724 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{258 0 0-1271 {}} {258 0 0-1264 {}} {258 0 0-1265 {}} {258 0 0-1266 {}} {258 0 0-1267 {}} {258 0 0-1268 {}} {258 0 0-1269 {}} {258 0 0-1263 {}} {258 0 0-1270 {}} {258 0 0-1275 {}} {258 0 0-1274 {}} {258 0 0-1272 {}} {258 0 0-1273 {}} {259 0 0-1276 {}}} SUCCS {{772 0 0-1263 {}} {772 0 0-1264 {}} {772 0 0-1265 {}} {772 0 0-1266 {}} {772 0 0-1267 {}} {772 0 0-1268 {}} {772 0 0-1269 {}} {772 0 0-1270 {}} {772 0 0-1271 {}} {772 0 0-1272 {}} {772 0 0-1273 {}} {772 0 0-1274 {}} {772 0 0-1275 {}} {772 0 0-1276 {}}} CYCLES {}}
+set a(0-1262) {CHI {0-1263 0-1264 0-1265 0-1266 0-1267 0-1268 0-1269 0-1270 0-1271 0-1272 0-1273 0-1274 0-1275 0-1276 0-1277} ITERATIONS Infinite LATENCY 921601 RESET_LATENCY 0 CSTEPS 0 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 921600 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 0 TOTAL_CYCLES_IN 0 TOTAL_CYCLES_UNDER 921602 TOTAL_CYCLES 921602 NAME core:rlp TYPE LOOP DELAY {18432060.00 ns} PAR {} XREFS 10725 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-1262-TOTALCYCLES) {921602}
+set a(0-1262-QMOD) {mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2) 0-1292 mgc_ioport.mgc_in_wire(1,90) 0-1296 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12) {0-1303 0-1312 0-1321 0-1330 0-1339 0-1348} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2) {0-1352 0-1355 0-1357} mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2) {0-1360 0-1415} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2) {0-1376 0-1386 0-1396 0-1423 0-1432 0-1441} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4) {0-1380 0-1390 0-1400 0-1427 0-1436 0-1445} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12) {0-1382 0-1392 0-1402 0-1428 0-1437 0-1446} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16) {0-1383 0-1393 0-1403 0-1429 0-1438 0-1447} mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(2,2) 0-1420 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2) 0-1448 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5) {0-1451 0-1500 0-1521 0-1577} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) {0-1463 0-1477 0-1491 0-1573 0-1669} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(17,0,13,1,17) {0-1466 0-1480 0-1494} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16) {0-1468 0-1482 0-1496} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,1,5,1,6) {0-1501 0-1516 0-1522 0-1537 0-1568 0-1578 0-1593 0-1624 0-1664} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4) {0-1505 0-1526 0-1582} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,5) {0-1507 0-1528 0-1561 0-1565 0-1584 0-1617 0-1621 0-1657 0-1661} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,0,6) {0-1508 0-1529 0-1585} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9) {0-1540 0-1596 0-1636} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8) {0-1569 0-1625 0-1665} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10) {0-1570 0-1626 0-1666} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,1,9,0,12) {0-1572 0-1668} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,1,9,0,10) 0-1628 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,10) 0-1629 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2) 0-1632 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(30,2) 0-1671 mgc_ioport.mgc_out_stdreg(2,30) 0-1672 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19) 0-1673 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,7,0,8) 0-1675 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2) {0-1680 0-1683} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2) 0-1693}
+set a(0-1262-PROC_NAME) {core}
+set a(0-1262-HIER_NAME) {/sobel/core}
+set a(TOP) {0-1262}
+
diff --git a/Sobel/sobel.v4/schematic.nlv b/Sobel/sobel.v4/schematic.nlv
new file mode 100644
index 0000000..0bfbe65
--- /dev/null
+++ b/Sobel/sobel.v4/schematic.nlv
@@ -0,0 +1,10333 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "sobel:core" "orig"
+load port {clk} input -attr xrf 11613 -attr oid 1 -attr vt d -attr @path {/sobel/sobel:core/clk}
+load port {en} input -attr xrf 11614 -attr oid 2 -attr vt d -attr @path {/sobel/sobel:core/en}
+load port {arst_n} input -attr xrf 11615 -attr oid 3 -attr vt d -attr @path {/sobel/sobel:core/arst_n}
+load portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} -attr xrf 11616 -attr oid 4 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} -attr xrf 11617 -attr oid 5 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load symbol "add(6,0,5,1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,-1,10,-1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,10)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,12,-1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,30)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(29:0)} input 30 {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(29:0)} input 30 {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nand(2,1)" "INTERFACE" NAND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,30)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(29:0)} input 30 {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(29:0)} input 30 {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(30,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(29:0)} input 30 {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(29:0)} input 30 {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,6,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(9,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(8:0)} input 9 {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(8:0)} input 9 {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(6,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(5:0)} input 6 {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(5:0)} input 6 {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "or(4,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {A3(0:0)} input 1 {A3(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "and(3,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(4,0,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(3)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(5,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(4:0)} input 5 {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(4:0)} input 5 {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,1,9,0,10)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(10,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(9:0)} input 10 {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(9:0)} input 10 {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,1,9,0,12)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(12,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(11:0)} input 12 {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(11:0)} input 12 {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(1,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(0:0)} input 1 {D(0)} \
+     portBus {DRa(0:0)} input 1 {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "reg(2,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(1:0)} input 2 {D(1)} {D(0)} \
+     portBus {DRa(1:0)} input 2 {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "and(2,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "reg(90,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(89:0)} input 90 {D(89)} {D(88)} {D(87)} {D(86)} {D(85)} {D(84)} {D(83)} {D(82)} {D(81)} {D(80)} {D(79)} {D(78)} {D(77)} {D(76)} {D(75)} {D(74)} {D(73)} {D(72)} {D(71)} {D(70)} {D(69)} {D(68)} {D(67)} {D(66)} {D(65)} {D(64)} {D(63)} {D(62)} {D(61)} {D(60)} {D(59)} {D(58)} {D(57)} {D(56)} {D(55)} {D(54)} {D(53)} {D(52)} {D(51)} {D(50)} {D(49)} {D(48)} {D(47)} {D(46)} {D(45)} {D(44)} {D(43)} {D(42)} {D(41)} {D(40)} {D(39)} {D(38)} {D(37)} {D(36)} {D(35)} {D(34)} {D(33)} {D(32)} {D(31)} {D(30)} {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(89:0)} input 90 {DRa(89)} {DRa(88)} {DRa(87)} {DRa(86)} {DRa(85)} {DRa(84)} {DRa(83)} {DRa(82)} {DRa(81)} {DRa(80)} {DRa(79)} {DRa(78)} {DRa(77)} {DRa(76)} {DRa(75)} {DRa(74)} {DRa(73)} {DRa(72)} {DRa(71)} {DRa(70)} {DRa(69)} {DRa(68)} {DRa(67)} {DRa(66)} {DRa(65)} {DRa(64)} {DRa(63)} {DRa(62)} {DRa(61)} {DRa(60)} {DRa(59)} {DRa(58)} {DRa(57)} {DRa(56)} {DRa(55)} {DRa(54)} {DRa(53)} {DRa(52)} {DRa(51)} {DRa(50)} {DRa(49)} {DRa(48)} {DRa(47)} {DRa(46)} {DRa(45)} {DRa(44)} {DRa(43)} {DRa(42)} {DRa(41)} {DRa(40)} {DRa(39)} {DRa(38)} {DRa(37)} {DRa(36)} {DRa(35)} {DRa(34)} {DRa(33)} {DRa(32)} {DRa(31)} {DRa(30)} {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(16,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(15:0)} input 16 {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(15:0)} input 16 {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,19)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(19,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(18:0)} input 19 {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(18:0)} input 19 {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "and(2,2)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(1:0)} input 2 {A0(1)} {A0(0)} \
+     portBus {A1(1:0)} input 2 {A1(1)} {A1(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "or(2,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,90)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(89:0)} input 90 {A0(89)} {A0(88)} {A0(87)} {A0(86)} {A0(85)} {A0(84)} {A0(83)} {A0(82)} {A0(81)} {A0(80)} {A0(79)} {A0(78)} {A0(77)} {A0(76)} {A0(75)} {A0(74)} {A0(73)} {A0(72)} {A0(71)} {A0(70)} {A0(69)} {A0(68)} {A0(67)} {A0(66)} {A0(65)} {A0(64)} {A0(63)} {A0(62)} {A0(61)} {A0(60)} {A0(59)} {A0(58)} {A0(57)} {A0(56)} {A0(55)} {A0(54)} {A0(53)} {A0(52)} {A0(51)} {A0(50)} {A0(49)} {A0(48)} {A0(47)} {A0(46)} {A0(45)} {A0(44)} {A0(43)} {A0(42)} {A0(41)} {A0(40)} {A0(39)} {A0(38)} {A0(37)} {A0(36)} {A0(35)} {A0(34)} {A0(33)} {A0(32)} {A0(31)} {A0(30)} {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(89:0)} input 90 {A1(89)} {A1(88)} {A1(87)} {A1(86)} {A1(85)} {A1(84)} {A1(83)} {A1(82)} {A1(81)} {A1(80)} {A1(79)} {A1(78)} {A1(77)} {A1(76)} {A1(75)} {A1(74)} {A1(73)} {A1(72)} {A1(71)} {A1(70)} {A1(69)} {A1(68)} {A1(67)} {A1(66)} {A1(65)} {A1(64)} {A1(63)} {A1(62)} {A1(61)} {A1(60)} {A1(59)} {A1(58)} {A1(57)} {A1(56)} {A1(55)} {A1(54)} {A1(53)} {A1(52)} {A1(51)} {A1(50)} {A1(49)} {A1(48)} {A1(47)} {A1(46)} {A1(45)} {A1(44)} {A1(43)} {A1(42)} {A1(41)} {A1(40)} {A1(39)} {A1(38)} {A1(37)} {A1(36)} {A1(35)} {A1(34)} {A1(33)} {A1(32)} {A1(31)} {A1(30)} {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,8,-1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,1)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(19,-1,1,0,19)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(18:0)} input 19 {A(18)} {A(17)} {A(16)} {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,19)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(10)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,11,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,15,-1,15)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(14:0)} input 15 {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,1,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,16,-1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,-1,4,-1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,-1,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,16)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(15:0)} input 16 {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(15:0)} input 16 {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(4,10)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {A2(9:0)} input 10 {A2(9)} {A2(8)} {A2(7)} {A2(6)} {A2(5)} {A2(4)} {A2(3)} {A2(2)} {A2(1)} {A2(0)} \
+     portBus {A3(9:0)} input 10 {A3(9)} {A3(8)} {A3(7)} {A3(6)} {A3(5)} {A3(4)} {A3(3)} {A3(2)} {A3(1)} {A3(0)} \
+     portBus {S(1:0)} input.top 2 {S(1)} {S(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,11,1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,12)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,12,1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nor(2,1)" "INTERFACE" NOR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "or(3,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load net {FRAME:p#1.lpi#1(0)} -attr vt d
+load net {FRAME:p#1.lpi#1(1)} -attr vt d
+load net {FRAME:p#1.lpi#1(2)} -attr vt d
+load net {FRAME:p#1.lpi#1(3)} -attr vt d
+load net {FRAME:p#1.lpi#1(4)} -attr vt d
+load net {FRAME:p#1.lpi#1(5)} -attr vt d
+load net {FRAME:p#1.lpi#1(6)} -attr vt d
+load net {FRAME:p#1.lpi#1(7)} -attr vt d
+load net {FRAME:p#1.lpi#1(8)} -attr vt d
+load net {FRAME:p#1.lpi#1(9)} -attr vt d
+load net {FRAME:p#1.lpi#1(10)} -attr vt d
+load net {FRAME:p#1.lpi#1(11)} -attr vt d
+load net {FRAME:p#1.lpi#1(12)} -attr vt d
+load net {FRAME:p#1.lpi#1(13)} -attr vt d
+load net {FRAME:p#1.lpi#1(14)} -attr vt d
+load net {FRAME:p#1.lpi#1(15)} -attr vt d
+load net {FRAME:p#1.lpi#1(16)} -attr vt d
+load net {FRAME:p#1.lpi#1(17)} -attr vt d
+load net {FRAME:p#1.lpi#1(18)} -attr vt d
+load netBundle {FRAME:p#1.lpi#1} 19 {FRAME:p#1.lpi#1(0)} {FRAME:p#1.lpi#1(1)} {FRAME:p#1.lpi#1(2)} {FRAME:p#1.lpi#1(3)} {FRAME:p#1.lpi#1(4)} {FRAME:p#1.lpi#1(5)} {FRAME:p#1.lpi#1(6)} {FRAME:p#1.lpi#1(7)} {FRAME:p#1.lpi#1(8)} {FRAME:p#1.lpi#1(9)} {FRAME:p#1.lpi#1(10)} {FRAME:p#1.lpi#1(11)} {FRAME:p#1.lpi#1(12)} {FRAME:p#1.lpi#1(13)} {FRAME:p#1.lpi#1(14)} {FRAME:p#1.lpi#1(15)} {FRAME:p#1.lpi#1(16)} {FRAME:p#1.lpi#1(17)} {FRAME:p#1.lpi#1(18)} -attr xrf 11618 -attr oid 6 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {regs.regs(1).sva(0)} -attr vt d
+load net {regs.regs(1).sva(1)} -attr vt d
+load net {regs.regs(1).sva(2)} -attr vt d
+load net {regs.regs(1).sva(3)} -attr vt d
+load net {regs.regs(1).sva(4)} -attr vt d
+load net {regs.regs(1).sva(5)} -attr vt d
+load net {regs.regs(1).sva(6)} -attr vt d
+load net {regs.regs(1).sva(7)} -attr vt d
+load net {regs.regs(1).sva(8)} -attr vt d
+load net {regs.regs(1).sva(9)} -attr vt d
+load net {regs.regs(1).sva(10)} -attr vt d
+load net {regs.regs(1).sva(11)} -attr vt d
+load net {regs.regs(1).sva(12)} -attr vt d
+load net {regs.regs(1).sva(13)} -attr vt d
+load net {regs.regs(1).sva(14)} -attr vt d
+load net {regs.regs(1).sva(15)} -attr vt d
+load net {regs.regs(1).sva(16)} -attr vt d
+load net {regs.regs(1).sva(17)} -attr vt d
+load net {regs.regs(1).sva(18)} -attr vt d
+load net {regs.regs(1).sva(19)} -attr vt d
+load net {regs.regs(1).sva(20)} -attr vt d
+load net {regs.regs(1).sva(21)} -attr vt d
+load net {regs.regs(1).sva(22)} -attr vt d
+load net {regs.regs(1).sva(23)} -attr vt d
+load net {regs.regs(1).sva(24)} -attr vt d
+load net {regs.regs(1).sva(25)} -attr vt d
+load net {regs.regs(1).sva(26)} -attr vt d
+load net {regs.regs(1).sva(27)} -attr vt d
+load net {regs.regs(1).sva(28)} -attr vt d
+load net {regs.regs(1).sva(29)} -attr vt d
+load net {regs.regs(1).sva(30)} -attr vt d
+load net {regs.regs(1).sva(31)} -attr vt d
+load net {regs.regs(1).sva(32)} -attr vt d
+load net {regs.regs(1).sva(33)} -attr vt d
+load net {regs.regs(1).sva(34)} -attr vt d
+load net {regs.regs(1).sva(35)} -attr vt d
+load net {regs.regs(1).sva(36)} -attr vt d
+load net {regs.regs(1).sva(37)} -attr vt d
+load net {regs.regs(1).sva(38)} -attr vt d
+load net {regs.regs(1).sva(39)} -attr vt d
+load net {regs.regs(1).sva(40)} -attr vt d
+load net {regs.regs(1).sva(41)} -attr vt d
+load net {regs.regs(1).sva(42)} -attr vt d
+load net {regs.regs(1).sva(43)} -attr vt d
+load net {regs.regs(1).sva(44)} -attr vt d
+load net {regs.regs(1).sva(45)} -attr vt d
+load net {regs.regs(1).sva(46)} -attr vt d
+load net {regs.regs(1).sva(47)} -attr vt d
+load net {regs.regs(1).sva(48)} -attr vt d
+load net {regs.regs(1).sva(49)} -attr vt d
+load net {regs.regs(1).sva(50)} -attr vt d
+load net {regs.regs(1).sva(51)} -attr vt d
+load net {regs.regs(1).sva(52)} -attr vt d
+load net {regs.regs(1).sva(53)} -attr vt d
+load net {regs.regs(1).sva(54)} -attr vt d
+load net {regs.regs(1).sva(55)} -attr vt d
+load net {regs.regs(1).sva(56)} -attr vt d
+load net {regs.regs(1).sva(57)} -attr vt d
+load net {regs.regs(1).sva(58)} -attr vt d
+load net {regs.regs(1).sva(59)} -attr vt d
+load net {regs.regs(1).sva(60)} -attr vt d
+load net {regs.regs(1).sva(61)} -attr vt d
+load net {regs.regs(1).sva(62)} -attr vt d
+load net {regs.regs(1).sva(63)} -attr vt d
+load net {regs.regs(1).sva(64)} -attr vt d
+load net {regs.regs(1).sva(65)} -attr vt d
+load net {regs.regs(1).sva(66)} -attr vt d
+load net {regs.regs(1).sva(67)} -attr vt d
+load net {regs.regs(1).sva(68)} -attr vt d
+load net {regs.regs(1).sva(69)} -attr vt d
+load net {regs.regs(1).sva(70)} -attr vt d
+load net {regs.regs(1).sva(71)} -attr vt d
+load net {regs.regs(1).sva(72)} -attr vt d
+load net {regs.regs(1).sva(73)} -attr vt d
+load net {regs.regs(1).sva(74)} -attr vt d
+load net {regs.regs(1).sva(75)} -attr vt d
+load net {regs.regs(1).sva(76)} -attr vt d
+load net {regs.regs(1).sva(77)} -attr vt d
+load net {regs.regs(1).sva(78)} -attr vt d
+load net {regs.regs(1).sva(79)} -attr vt d
+load net {regs.regs(1).sva(80)} -attr vt d
+load net {regs.regs(1).sva(81)} -attr vt d
+load net {regs.regs(1).sva(82)} -attr vt d
+load net {regs.regs(1).sva(83)} -attr vt d
+load net {regs.regs(1).sva(84)} -attr vt d
+load net {regs.regs(1).sva(85)} -attr vt d
+load net {regs.regs(1).sva(86)} -attr vt d
+load net {regs.regs(1).sva(87)} -attr vt d
+load net {regs.regs(1).sva(88)} -attr vt d
+load net {regs.regs(1).sva(89)} -attr vt d
+load netBundle {regs.regs(1).sva} 90 {regs.regs(1).sva(0)} {regs.regs(1).sva(1)} {regs.regs(1).sva(2)} {regs.regs(1).sva(3)} {regs.regs(1).sva(4)} {regs.regs(1).sva(5)} {regs.regs(1).sva(6)} {regs.regs(1).sva(7)} {regs.regs(1).sva(8)} {regs.regs(1).sva(9)} {regs.regs(1).sva(10)} {regs.regs(1).sva(11)} {regs.regs(1).sva(12)} {regs.regs(1).sva(13)} {regs.regs(1).sva(14)} {regs.regs(1).sva(15)} {regs.regs(1).sva(16)} {regs.regs(1).sva(17)} {regs.regs(1).sva(18)} {regs.regs(1).sva(19)} {regs.regs(1).sva(20)} {regs.regs(1).sva(21)} {regs.regs(1).sva(22)} {regs.regs(1).sva(23)} {regs.regs(1).sva(24)} {regs.regs(1).sva(25)} {regs.regs(1).sva(26)} {regs.regs(1).sva(27)} {regs.regs(1).sva(28)} {regs.regs(1).sva(29)} {regs.regs(1).sva(30)} {regs.regs(1).sva(31)} {regs.regs(1).sva(32)} {regs.regs(1).sva(33)} {regs.regs(1).sva(34)} {regs.regs(1).sva(35)} {regs.regs(1).sva(36)} {regs.regs(1).sva(37)} {regs.regs(1).sva(38)} {regs.regs(1).sva(39)} {regs.regs(1).sva(40)} {regs.regs(1).sva(41)} {regs.regs(1).sva(42)} {regs.regs(1).sva(43)} {regs.regs(1).sva(44)} {regs.regs(1).sva(45)} {regs.regs(1).sva(46)} {regs.regs(1).sva(47)} {regs.regs(1).sva(48)} {regs.regs(1).sva(49)} {regs.regs(1).sva(50)} {regs.regs(1).sva(51)} {regs.regs(1).sva(52)} {regs.regs(1).sva(53)} {regs.regs(1).sva(54)} {regs.regs(1).sva(55)} {regs.regs(1).sva(56)} {regs.regs(1).sva(57)} {regs.regs(1).sva(58)} {regs.regs(1).sva(59)} {regs.regs(1).sva(60)} {regs.regs(1).sva(61)} {regs.regs(1).sva(62)} {regs.regs(1).sva(63)} {regs.regs(1).sva(64)} {regs.regs(1).sva(65)} {regs.regs(1).sva(66)} {regs.regs(1).sva(67)} {regs.regs(1).sva(68)} {regs.regs(1).sva(69)} {regs.regs(1).sva(70)} {regs.regs(1).sva(71)} {regs.regs(1).sva(72)} {regs.regs(1).sva(73)} {regs.regs(1).sva(74)} {regs.regs(1).sva(75)} {regs.regs(1).sva(76)} {regs.regs(1).sva(77)} {regs.regs(1).sva(78)} {regs.regs(1).sva(79)} {regs.regs(1).sva(80)} {regs.regs(1).sva(81)} {regs.regs(1).sva(82)} {regs.regs(1).sva(83)} {regs.regs(1).sva(84)} {regs.regs(1).sva(85)} {regs.regs(1).sva(86)} {regs.regs(1).sva(87)} {regs.regs(1).sva(88)} {regs.regs(1).sva(89)} -attr xrf 11619 -attr oid 7 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -attr vt d
+load net {regs.regs(0).sva(1)} -attr vt d
+load net {regs.regs(0).sva(2)} -attr vt d
+load net {regs.regs(0).sva(3)} -attr vt d
+load net {regs.regs(0).sva(4)} -attr vt d
+load net {regs.regs(0).sva(5)} -attr vt d
+load net {regs.regs(0).sva(6)} -attr vt d
+load net {regs.regs(0).sva(7)} -attr vt d
+load net {regs.regs(0).sva(8)} -attr vt d
+load net {regs.regs(0).sva(9)} -attr vt d
+load net {regs.regs(0).sva(10)} -attr vt d
+load net {regs.regs(0).sva(11)} -attr vt d
+load net {regs.regs(0).sva(12)} -attr vt d
+load net {regs.regs(0).sva(13)} -attr vt d
+load net {regs.regs(0).sva(14)} -attr vt d
+load net {regs.regs(0).sva(15)} -attr vt d
+load net {regs.regs(0).sva(16)} -attr vt d
+load net {regs.regs(0).sva(17)} -attr vt d
+load net {regs.regs(0).sva(18)} -attr vt d
+load net {regs.regs(0).sva(19)} -attr vt d
+load net {regs.regs(0).sva(20)} -attr vt d
+load net {regs.regs(0).sva(21)} -attr vt d
+load net {regs.regs(0).sva(22)} -attr vt d
+load net {regs.regs(0).sva(23)} -attr vt d
+load net {regs.regs(0).sva(24)} -attr vt d
+load net {regs.regs(0).sva(25)} -attr vt d
+load net {regs.regs(0).sva(26)} -attr vt d
+load net {regs.regs(0).sva(27)} -attr vt d
+load net {regs.regs(0).sva(28)} -attr vt d
+load net {regs.regs(0).sva(29)} -attr vt d
+load net {regs.regs(0).sva(30)} -attr vt d
+load net {regs.regs(0).sva(31)} -attr vt d
+load net {regs.regs(0).sva(32)} -attr vt d
+load net {regs.regs(0).sva(33)} -attr vt d
+load net {regs.regs(0).sva(34)} -attr vt d
+load net {regs.regs(0).sva(35)} -attr vt d
+load net {regs.regs(0).sva(36)} -attr vt d
+load net {regs.regs(0).sva(37)} -attr vt d
+load net {regs.regs(0).sva(38)} -attr vt d
+load net {regs.regs(0).sva(39)} -attr vt d
+load net {regs.regs(0).sva(40)} -attr vt d
+load net {regs.regs(0).sva(41)} -attr vt d
+load net {regs.regs(0).sva(42)} -attr vt d
+load net {regs.regs(0).sva(43)} -attr vt d
+load net {regs.regs(0).sva(44)} -attr vt d
+load net {regs.regs(0).sva(45)} -attr vt d
+load net {regs.regs(0).sva(46)} -attr vt d
+load net {regs.regs(0).sva(47)} -attr vt d
+load net {regs.regs(0).sva(48)} -attr vt d
+load net {regs.regs(0).sva(49)} -attr vt d
+load net {regs.regs(0).sva(50)} -attr vt d
+load net {regs.regs(0).sva(51)} -attr vt d
+load net {regs.regs(0).sva(52)} -attr vt d
+load net {regs.regs(0).sva(53)} -attr vt d
+load net {regs.regs(0).sva(54)} -attr vt d
+load net {regs.regs(0).sva(55)} -attr vt d
+load net {regs.regs(0).sva(56)} -attr vt d
+load net {regs.regs(0).sva(57)} -attr vt d
+load net {regs.regs(0).sva(58)} -attr vt d
+load net {regs.regs(0).sva(59)} -attr vt d
+load net {regs.regs(0).sva(60)} -attr vt d
+load net {regs.regs(0).sva(61)} -attr vt d
+load net {regs.regs(0).sva(62)} -attr vt d
+load net {regs.regs(0).sva(63)} -attr vt d
+load net {regs.regs(0).sva(64)} -attr vt d
+load net {regs.regs(0).sva(65)} -attr vt d
+load net {regs.regs(0).sva(66)} -attr vt d
+load net {regs.regs(0).sva(67)} -attr vt d
+load net {regs.regs(0).sva(68)} -attr vt d
+load net {regs.regs(0).sva(69)} -attr vt d
+load net {regs.regs(0).sva(70)} -attr vt d
+load net {regs.regs(0).sva(71)} -attr vt d
+load net {regs.regs(0).sva(72)} -attr vt d
+load net {regs.regs(0).sva(73)} -attr vt d
+load net {regs.regs(0).sva(74)} -attr vt d
+load net {regs.regs(0).sva(75)} -attr vt d
+load net {regs.regs(0).sva(76)} -attr vt d
+load net {regs.regs(0).sva(77)} -attr vt d
+load net {regs.regs(0).sva(78)} -attr vt d
+load net {regs.regs(0).sva(79)} -attr vt d
+load net {regs.regs(0).sva(80)} -attr vt d
+load net {regs.regs(0).sva(81)} -attr vt d
+load net {regs.regs(0).sva(82)} -attr vt d
+load net {regs.regs(0).sva(83)} -attr vt d
+load net {regs.regs(0).sva(84)} -attr vt d
+load net {regs.regs(0).sva(85)} -attr vt d
+load net {regs.regs(0).sva(86)} -attr vt d
+load net {regs.regs(0).sva(87)} -attr vt d
+load net {regs.regs(0).sva(88)} -attr vt d
+load net {regs.regs(0).sva(89)} -attr vt d
+load netBundle {regs.regs(0).sva} 90 {regs.regs(0).sva(0)} {regs.regs(0).sva(1)} {regs.regs(0).sva(2)} {regs.regs(0).sva(3)} {regs.regs(0).sva(4)} {regs.regs(0).sva(5)} {regs.regs(0).sva(6)} {regs.regs(0).sva(7)} {regs.regs(0).sva(8)} {regs.regs(0).sva(9)} {regs.regs(0).sva(10)} {regs.regs(0).sva(11)} {regs.regs(0).sva(12)} {regs.regs(0).sva(13)} {regs.regs(0).sva(14)} {regs.regs(0).sva(15)} {regs.regs(0).sva(16)} {regs.regs(0).sva(17)} {regs.regs(0).sva(18)} {regs.regs(0).sva(19)} {regs.regs(0).sva(20)} {regs.regs(0).sva(21)} {regs.regs(0).sva(22)} {regs.regs(0).sva(23)} {regs.regs(0).sva(24)} {regs.regs(0).sva(25)} {regs.regs(0).sva(26)} {regs.regs(0).sva(27)} {regs.regs(0).sva(28)} {regs.regs(0).sva(29)} {regs.regs(0).sva(30)} {regs.regs(0).sva(31)} {regs.regs(0).sva(32)} {regs.regs(0).sva(33)} {regs.regs(0).sva(34)} {regs.regs(0).sva(35)} {regs.regs(0).sva(36)} {regs.regs(0).sva(37)} {regs.regs(0).sva(38)} {regs.regs(0).sva(39)} {regs.regs(0).sva(40)} {regs.regs(0).sva(41)} {regs.regs(0).sva(42)} {regs.regs(0).sva(43)} {regs.regs(0).sva(44)} {regs.regs(0).sva(45)} {regs.regs(0).sva(46)} {regs.regs(0).sva(47)} {regs.regs(0).sva(48)} {regs.regs(0).sva(49)} {regs.regs(0).sva(50)} {regs.regs(0).sva(51)} {regs.regs(0).sva(52)} {regs.regs(0).sva(53)} {regs.regs(0).sva(54)} {regs.regs(0).sva(55)} {regs.regs(0).sva(56)} {regs.regs(0).sva(57)} {regs.regs(0).sva(58)} {regs.regs(0).sva(59)} {regs.regs(0).sva(60)} {regs.regs(0).sva(61)} {regs.regs(0).sva(62)} {regs.regs(0).sva(63)} {regs.regs(0).sva(64)} {regs.regs(0).sva(65)} {regs.regs(0).sva(66)} {regs.regs(0).sva(67)} {regs.regs(0).sva(68)} {regs.regs(0).sva(69)} {regs.regs(0).sva(70)} {regs.regs(0).sva(71)} {regs.regs(0).sva(72)} {regs.regs(0).sva(73)} {regs.regs(0).sva(74)} {regs.regs(0).sva(75)} {regs.regs(0).sva(76)} {regs.regs(0).sva(77)} {regs.regs(0).sva(78)} {regs.regs(0).sva(79)} {regs.regs(0).sva(80)} {regs.regs(0).sva(81)} {regs.regs(0).sva(82)} {regs.regs(0).sva(83)} {regs.regs(0).sva(84)} {regs.regs(0).sva(85)} {regs.regs(0).sva(86)} {regs.regs(0).sva(87)} {regs.regs(0).sva(88)} {regs.regs(0).sva(89)} -attr xrf 11620 -attr oid 8 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(2).lpi#1.dfm(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(29)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(30)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(31)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(32)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(33)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(34)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(35)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(36)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(37)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(38)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(39)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(40)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(41)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(42)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(43)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(44)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(45)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(46)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(47)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(48)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(49)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(50)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(51)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(52)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(53)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(54)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(55)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(56)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(57)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(58)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(59)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(60)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(61)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(62)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(63)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(64)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(65)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(66)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(67)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(68)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(69)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(70)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(71)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(72)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(73)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(74)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(75)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(76)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(77)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(78)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(79)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(80)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(81)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(82)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(83)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(84)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(85)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(86)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(87)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(88)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(89)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm} 90 {regs.regs(2).lpi#1.dfm(0)} {regs.regs(2).lpi#1.dfm(1)} {regs.regs(2).lpi#1.dfm(2)} {regs.regs(2).lpi#1.dfm(3)} {regs.regs(2).lpi#1.dfm(4)} {regs.regs(2).lpi#1.dfm(5)} {regs.regs(2).lpi#1.dfm(6)} {regs.regs(2).lpi#1.dfm(7)} {regs.regs(2).lpi#1.dfm(8)} {regs.regs(2).lpi#1.dfm(9)} {regs.regs(2).lpi#1.dfm(10)} {regs.regs(2).lpi#1.dfm(11)} {regs.regs(2).lpi#1.dfm(12)} {regs.regs(2).lpi#1.dfm(13)} {regs.regs(2).lpi#1.dfm(14)} {regs.regs(2).lpi#1.dfm(15)} {regs.regs(2).lpi#1.dfm(16)} {regs.regs(2).lpi#1.dfm(17)} {regs.regs(2).lpi#1.dfm(18)} {regs.regs(2).lpi#1.dfm(19)} {regs.regs(2).lpi#1.dfm(20)} {regs.regs(2).lpi#1.dfm(21)} {regs.regs(2).lpi#1.dfm(22)} {regs.regs(2).lpi#1.dfm(23)} {regs.regs(2).lpi#1.dfm(24)} {regs.regs(2).lpi#1.dfm(25)} {regs.regs(2).lpi#1.dfm(26)} {regs.regs(2).lpi#1.dfm(27)} {regs.regs(2).lpi#1.dfm(28)} {regs.regs(2).lpi#1.dfm(29)} {regs.regs(2).lpi#1.dfm(30)} {regs.regs(2).lpi#1.dfm(31)} {regs.regs(2).lpi#1.dfm(32)} {regs.regs(2).lpi#1.dfm(33)} {regs.regs(2).lpi#1.dfm(34)} {regs.regs(2).lpi#1.dfm(35)} {regs.regs(2).lpi#1.dfm(36)} {regs.regs(2).lpi#1.dfm(37)} {regs.regs(2).lpi#1.dfm(38)} {regs.regs(2).lpi#1.dfm(39)} {regs.regs(2).lpi#1.dfm(40)} {regs.regs(2).lpi#1.dfm(41)} {regs.regs(2).lpi#1.dfm(42)} {regs.regs(2).lpi#1.dfm(43)} {regs.regs(2).lpi#1.dfm(44)} {regs.regs(2).lpi#1.dfm(45)} {regs.regs(2).lpi#1.dfm(46)} {regs.regs(2).lpi#1.dfm(47)} {regs.regs(2).lpi#1.dfm(48)} {regs.regs(2).lpi#1.dfm(49)} {regs.regs(2).lpi#1.dfm(50)} {regs.regs(2).lpi#1.dfm(51)} {regs.regs(2).lpi#1.dfm(52)} {regs.regs(2).lpi#1.dfm(53)} {regs.regs(2).lpi#1.dfm(54)} {regs.regs(2).lpi#1.dfm(55)} {regs.regs(2).lpi#1.dfm(56)} {regs.regs(2).lpi#1.dfm(57)} {regs.regs(2).lpi#1.dfm(58)} {regs.regs(2).lpi#1.dfm(59)} {regs.regs(2).lpi#1.dfm(60)} {regs.regs(2).lpi#1.dfm(61)} {regs.regs(2).lpi#1.dfm(62)} {regs.regs(2).lpi#1.dfm(63)} {regs.regs(2).lpi#1.dfm(64)} {regs.regs(2).lpi#1.dfm(65)} {regs.regs(2).lpi#1.dfm(66)} {regs.regs(2).lpi#1.dfm(67)} {regs.regs(2).lpi#1.dfm(68)} {regs.regs(2).lpi#1.dfm(69)} {regs.regs(2).lpi#1.dfm(70)} {regs.regs(2).lpi#1.dfm(71)} {regs.regs(2).lpi#1.dfm(72)} {regs.regs(2).lpi#1.dfm(73)} {regs.regs(2).lpi#1.dfm(74)} {regs.regs(2).lpi#1.dfm(75)} {regs.regs(2).lpi#1.dfm(76)} {regs.regs(2).lpi#1.dfm(77)} {regs.regs(2).lpi#1.dfm(78)} {regs.regs(2).lpi#1.dfm(79)} {regs.regs(2).lpi#1.dfm(80)} {regs.regs(2).lpi#1.dfm(81)} {regs.regs(2).lpi#1.dfm(82)} {regs.regs(2).lpi#1.dfm(83)} {regs.regs(2).lpi#1.dfm(84)} {regs.regs(2).lpi#1.dfm(85)} {regs.regs(2).lpi#1.dfm(86)} {regs.regs(2).lpi#1.dfm(87)} {regs.regs(2).lpi#1.dfm(88)} {regs.regs(2).lpi#1.dfm(89)} -attr xrf 11621 -attr oid 9 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {r(0).sva#1(0)} -attr vt d
+load net {r(0).sva#1(1)} -attr vt d
+load net {r(0).sva#1(2)} -attr vt d
+load net {r(0).sva#1(3)} -attr vt d
+load net {r(0).sva#1(4)} -attr vt d
+load net {r(0).sva#1(5)} -attr vt d
+load net {r(0).sva#1(6)} -attr vt d
+load net {r(0).sva#1(7)} -attr vt d
+load net {r(0).sva#1(8)} -attr vt d
+load net {r(0).sva#1(9)} -attr vt d
+load net {r(0).sva#1(10)} -attr vt d
+load net {r(0).sva#1(11)} -attr vt d
+load net {r(0).sva#1(12)} -attr vt d
+load net {r(0).sva#1(13)} -attr vt d
+load net {r(0).sva#1(14)} -attr vt d
+load net {r(0).sva#1(15)} -attr vt d
+load netBundle {r(0).sva#1} 16 {r(0).sva#1(0)} {r(0).sva#1(1)} {r(0).sva#1(2)} {r(0).sva#1(3)} {r(0).sva#1(4)} {r(0).sva#1(5)} {r(0).sva#1(6)} {r(0).sva#1(7)} {r(0).sva#1(8)} {r(0).sva#1(9)} {r(0).sva#1(10)} {r(0).sva#1(11)} {r(0).sva#1(12)} {r(0).sva#1(13)} {r(0).sva#1(14)} {r(0).sva#1(15)} -attr xrf 11622 -attr oid 10 -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {g(0).sva#1(0)} -attr vt d
+load net {g(0).sva#1(1)} -attr vt d
+load net {g(0).sva#1(2)} -attr vt d
+load net {g(0).sva#1(3)} -attr vt d
+load net {g(0).sva#1(4)} -attr vt d
+load net {g(0).sva#1(5)} -attr vt d
+load net {g(0).sva#1(6)} -attr vt d
+load net {g(0).sva#1(7)} -attr vt d
+load net {g(0).sva#1(8)} -attr vt d
+load net {g(0).sva#1(9)} -attr vt d
+load net {g(0).sva#1(10)} -attr vt d
+load net {g(0).sva#1(11)} -attr vt d
+load net {g(0).sva#1(12)} -attr vt d
+load net {g(0).sva#1(13)} -attr vt d
+load net {g(0).sva#1(14)} -attr vt d
+load net {g(0).sva#1(15)} -attr vt d
+load netBundle {g(0).sva#1} 16 {g(0).sva#1(0)} {g(0).sva#1(1)} {g(0).sva#1(2)} {g(0).sva#1(3)} {g(0).sva#1(4)} {g(0).sva#1(5)} {g(0).sva#1(6)} {g(0).sva#1(7)} {g(0).sva#1(8)} {g(0).sva#1(9)} {g(0).sva#1(10)} {g(0).sva#1(11)} {g(0).sva#1(12)} {g(0).sva#1(13)} {g(0).sva#1(14)} {g(0).sva#1(15)} -attr xrf 11623 -attr oid 11 -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {b(0).sva#1(0)} -attr vt d
+load net {b(0).sva#1(1)} -attr vt d
+load net {b(0).sva#1(2)} -attr vt d
+load net {b(0).sva#1(3)} -attr vt d
+load net {b(0).sva#1(4)} -attr vt d
+load net {b(0).sva#1(5)} -attr vt d
+load net {b(0).sva#1(6)} -attr vt d
+load net {b(0).sva#1(7)} -attr vt d
+load net {b(0).sva#1(8)} -attr vt d
+load net {b(0).sva#1(9)} -attr vt d
+load net {b(0).sva#1(10)} -attr vt d
+load net {b(0).sva#1(11)} -attr vt d
+load net {b(0).sva#1(12)} -attr vt d
+load net {b(0).sva#1(13)} -attr vt d
+load net {b(0).sva#1(14)} -attr vt d
+load net {b(0).sva#1(15)} -attr vt d
+load netBundle {b(0).sva#1} 16 {b(0).sva#1(0)} {b(0).sva#1(1)} {b(0).sva#1(2)} {b(0).sva#1(3)} {b(0).sva#1(4)} {b(0).sva#1(5)} {b(0).sva#1(6)} {b(0).sva#1(7)} {b(0).sva#1(8)} {b(0).sva#1(9)} {b(0).sva#1(10)} {b(0).sva#1(11)} {b(0).sva#1(12)} {b(0).sva#1(13)} {b(0).sva#1(14)} {b(0).sva#1(15)} -attr xrf 11624 -attr oid 12 -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {r(2).sva#1(0)} -attr vt d
+load net {r(2).sva#1(1)} -attr vt d
+load net {r(2).sva#1(2)} -attr vt d
+load net {r(2).sva#1(3)} -attr vt d
+load net {r(2).sva#1(4)} -attr vt d
+load net {r(2).sva#1(5)} -attr vt d
+load net {r(2).sva#1(6)} -attr vt d
+load net {r(2).sva#1(7)} -attr vt d
+load net {r(2).sva#1(8)} -attr vt d
+load net {r(2).sva#1(9)} -attr vt d
+load net {r(2).sva#1(10)} -attr vt d
+load net {r(2).sva#1(11)} -attr vt d
+load net {r(2).sva#1(12)} -attr vt d
+load net {r(2).sva#1(13)} -attr vt d
+load net {r(2).sva#1(14)} -attr vt d
+load net {r(2).sva#1(15)} -attr vt d
+load netBundle {r(2).sva#1} 16 {r(2).sva#1(0)} {r(2).sva#1(1)} {r(2).sva#1(2)} {r(2).sva#1(3)} {r(2).sva#1(4)} {r(2).sva#1(5)} {r(2).sva#1(6)} {r(2).sva#1(7)} {r(2).sva#1(8)} {r(2).sva#1(9)} {r(2).sva#1(10)} {r(2).sva#1(11)} {r(2).sva#1(12)} {r(2).sva#1(13)} {r(2).sva#1(14)} {r(2).sva#1(15)} -attr xrf 11625 -attr oid 13 -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {g(2).sva#1(0)} -attr vt d
+load net {g(2).sva#1(1)} -attr vt d
+load net {g(2).sva#1(2)} -attr vt d
+load net {g(2).sva#1(3)} -attr vt d
+load net {g(2).sva#1(4)} -attr vt d
+load net {g(2).sva#1(5)} -attr vt d
+load net {g(2).sva#1(6)} -attr vt d
+load net {g(2).sva#1(7)} -attr vt d
+load net {g(2).sva#1(8)} -attr vt d
+load net {g(2).sva#1(9)} -attr vt d
+load net {g(2).sva#1(10)} -attr vt d
+load net {g(2).sva#1(11)} -attr vt d
+load net {g(2).sva#1(12)} -attr vt d
+load net {g(2).sva#1(13)} -attr vt d
+load net {g(2).sva#1(14)} -attr vt d
+load net {g(2).sva#1(15)} -attr vt d
+load netBundle {g(2).sva#1} 16 {g(2).sva#1(0)} {g(2).sva#1(1)} {g(2).sva#1(2)} {g(2).sva#1(3)} {g(2).sva#1(4)} {g(2).sva#1(5)} {g(2).sva#1(6)} {g(2).sva#1(7)} {g(2).sva#1(8)} {g(2).sva#1(9)} {g(2).sva#1(10)} {g(2).sva#1(11)} {g(2).sva#1(12)} {g(2).sva#1(13)} {g(2).sva#1(14)} {g(2).sva#1(15)} -attr xrf 11626 -attr oid 14 -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {b(2).sva#1(0)} -attr vt d
+load net {b(2).sva#1(1)} -attr vt d
+load net {b(2).sva#1(2)} -attr vt d
+load net {b(2).sva#1(3)} -attr vt d
+load net {b(2).sva#1(4)} -attr vt d
+load net {b(2).sva#1(5)} -attr vt d
+load net {b(2).sva#1(6)} -attr vt d
+load net {b(2).sva#1(7)} -attr vt d
+load net {b(2).sva#1(8)} -attr vt d
+load net {b(2).sva#1(9)} -attr vt d
+load net {b(2).sva#1(10)} -attr vt d
+load net {b(2).sva#1(11)} -attr vt d
+load net {b(2).sva#1(12)} -attr vt d
+load net {b(2).sva#1(13)} -attr vt d
+load net {b(2).sva#1(14)} -attr vt d
+load net {b(2).sva#1(15)} -attr vt d
+load netBundle {b(2).sva#1} 16 {b(2).sva#1(0)} {b(2).sva#1(1)} {b(2).sva#1(2)} {b(2).sva#1(3)} {b(2).sva#1(4)} {b(2).sva#1(5)} {b(2).sva#1(6)} {b(2).sva#1(7)} {b(2).sva#1(8)} {b(2).sva#1(9)} {b(2).sva#1(10)} {b(2).sva#1(11)} {b(2).sva#1(12)} {b(2).sva#1(13)} {b(2).sva#1(14)} {b(2).sva#1(15)} -attr xrf 11627 -attr oid 15 -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {i#6.sva#1(0)} -attr vt d
+load net {i#6.sva#1(1)} -attr vt d
+load netBundle {i#6.sva#1} 2 {i#6.sva#1(0)} {i#6.sva#1(1)} -attr xrf 11628 -attr oid 16 -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {FRAME:mul#2.itm#1(0)} -attr vt d
+load net {FRAME:mul#2.itm#1(1)} -attr vt d
+load net {FRAME:mul#2.itm#1(2)} -attr vt d
+load net {FRAME:mul#2.itm#1(3)} -attr vt d
+load net {FRAME:mul#2.itm#1(4)} -attr vt d
+load net {FRAME:mul#2.itm#1(5)} -attr vt d
+load net {FRAME:mul#2.itm#1(6)} -attr vt d
+load net {FRAME:mul#2.itm#1(7)} -attr vt d
+load net {FRAME:mul#2.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#2.itm#1} 9 {FRAME:mul#2.itm#1(0)} {FRAME:mul#2.itm#1(1)} {FRAME:mul#2.itm#1(2)} {FRAME:mul#2.itm#1(3)} {FRAME:mul#2.itm#1(4)} {FRAME:mul#2.itm#1(5)} {FRAME:mul#2.itm#1(6)} {FRAME:mul#2.itm#1(7)} {FRAME:mul#2.itm#1(8)} -attr xrf 11629 -attr oid 17 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:slc(green)#10.itm#1(0)} -attr vt d
+load net {FRAME:slc(green)#10.itm#1(1)} -attr vt d
+load net {FRAME:slc(green)#10.itm#1(2)} -attr vt d
+load net {FRAME:slc(green)#10.itm#1(3)} -attr vt d
+load net {FRAME:slc(green)#10.itm#1(4)} -attr vt d
+load net {FRAME:slc(green)#10.itm#1(5)} -attr vt d
+load netBundle {FRAME:slc(green)#10.itm#1} 6 {FRAME:slc(green)#10.itm#1(0)} {FRAME:slc(green)#10.itm#1(1)} {FRAME:slc(green)#10.itm#1(2)} {FRAME:slc(green)#10.itm#1(3)} {FRAME:slc(green)#10.itm#1(4)} {FRAME:slc(green)#10.itm#1(5)} -attr xrf 11630 -attr oid 18 -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(green)#10.itm#1}
+load net {FRAME:acc#25.itm#1(0)} -attr vt d
+load net {FRAME:acc#25.itm#1(1)} -attr vt d
+load net {FRAME:acc#25.itm#1(2)} -attr vt d
+load net {FRAME:acc#25.itm#1(3)} -attr vt d
+load net {FRAME:acc#25.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#25.itm#1} 5 {FRAME:acc#25.itm#1(0)} {FRAME:acc#25.itm#1(1)} {FRAME:acc#25.itm#1(2)} {FRAME:acc#25.itm#1(3)} {FRAME:acc#25.itm#1(4)} -attr xrf 11631 -attr oid 19 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm#1}
+load net {FRAME:mul#3.itm#1(0)} -attr vt d
+load net {FRAME:mul#3.itm#1(1)} -attr vt d
+load net {FRAME:mul#3.itm#1(2)} -attr vt d
+load net {FRAME:mul#3.itm#1(3)} -attr vt d
+load net {FRAME:mul#3.itm#1(4)} -attr vt d
+load net {FRAME:mul#3.itm#1(5)} -attr vt d
+load net {FRAME:mul#3.itm#1(6)} -attr vt d
+load net {FRAME:mul#3.itm#1(7)} -attr vt d
+load net {FRAME:mul#3.itm#1(8)} -attr vt d
+load net {FRAME:mul#3.itm#1(9)} -attr vt d
+load net {FRAME:mul#3.itm#1(10)} -attr vt d
+load net {FRAME:mul#3.itm#1(11)} -attr vt d
+load netBundle {FRAME:mul#3.itm#1} 12 {FRAME:mul#3.itm#1(0)} {FRAME:mul#3.itm#1(1)} {FRAME:mul#3.itm#1(2)} {FRAME:mul#3.itm#1(3)} {FRAME:mul#3.itm#1(4)} {FRAME:mul#3.itm#1(5)} {FRAME:mul#3.itm#1(6)} {FRAME:mul#3.itm#1(7)} {FRAME:mul#3.itm#1(8)} {FRAME:mul#3.itm#1(9)} {FRAME:mul#3.itm#1(10)} {FRAME:mul#3.itm#1(11)} -attr xrf 11632 -attr oid 20 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul.itm#1(0)} -attr vt d
+load net {FRAME:mul.itm#1(1)} -attr vt d
+load net {FRAME:mul.itm#1(2)} -attr vt d
+load net {FRAME:mul.itm#1(3)} -attr vt d
+load net {FRAME:mul.itm#1(4)} -attr vt d
+load net {FRAME:mul.itm#1(5)} -attr vt d
+load net {FRAME:mul.itm#1(6)} -attr vt d
+load net {FRAME:mul.itm#1(7)} -attr vt d
+load net {FRAME:mul.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul.itm#1} 9 {FRAME:mul.itm#1(0)} {FRAME:mul.itm#1(1)} {FRAME:mul.itm#1(2)} {FRAME:mul.itm#1(3)} {FRAME:mul.itm#1(4)} {FRAME:mul.itm#1(5)} {FRAME:mul.itm#1(6)} {FRAME:mul.itm#1(7)} {FRAME:mul.itm#1(8)} -attr xrf 11633 -attr oid 21 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:slc(red)#10.itm#1(0)} -attr vt d
+load net {FRAME:slc(red)#10.itm#1(1)} -attr vt d
+load net {FRAME:slc(red)#10.itm#1(2)} -attr vt d
+load net {FRAME:slc(red)#10.itm#1(3)} -attr vt d
+load net {FRAME:slc(red)#10.itm#1(4)} -attr vt d
+load net {FRAME:slc(red)#10.itm#1(5)} -attr vt d
+load netBundle {FRAME:slc(red)#10.itm#1} 6 {FRAME:slc(red)#10.itm#1(0)} {FRAME:slc(red)#10.itm#1(1)} {FRAME:slc(red)#10.itm#1(2)} {FRAME:slc(red)#10.itm#1(3)} {FRAME:slc(red)#10.itm#1(4)} {FRAME:slc(red)#10.itm#1(5)} -attr xrf 11634 -attr oid 22 -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(red)#10.itm#1}
+load net {FRAME:acc#35.itm#1(0)} -attr vt d
+load net {FRAME:acc#35.itm#1(1)} -attr vt d
+load net {FRAME:acc#35.itm#1(2)} -attr vt d
+load net {FRAME:acc#35.itm#1(3)} -attr vt d
+load net {FRAME:acc#35.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#35.itm#1} 5 {FRAME:acc#35.itm#1(0)} {FRAME:acc#35.itm#1(1)} {FRAME:acc#35.itm#1(2)} {FRAME:acc#35.itm#1(3)} {FRAME:acc#35.itm#1(4)} -attr xrf 11635 -attr oid 23 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm#1}
+load net {FRAME:mul#1.itm#1(0)} -attr vt d
+load net {FRAME:mul#1.itm#1(1)} -attr vt d
+load net {FRAME:mul#1.itm#1(2)} -attr vt d
+load net {FRAME:mul#1.itm#1(3)} -attr vt d
+load net {FRAME:mul#1.itm#1(4)} -attr vt d
+load net {FRAME:mul#1.itm#1(5)} -attr vt d
+load net {FRAME:mul#1.itm#1(6)} -attr vt d
+load net {FRAME:mul#1.itm#1(7)} -attr vt d
+load net {FRAME:mul#1.itm#1(8)} -attr vt d
+load net {FRAME:mul#1.itm#1(9)} -attr vt d
+load netBundle {FRAME:mul#1.itm#1} 10 {FRAME:mul#1.itm#1(0)} {FRAME:mul#1.itm#1(1)} {FRAME:mul#1.itm#1(2)} {FRAME:mul#1.itm#1(3)} {FRAME:mul#1.itm#1(4)} {FRAME:mul#1.itm#1(5)} {FRAME:mul#1.itm#1(6)} {FRAME:mul#1.itm#1(7)} {FRAME:mul#1.itm#1(8)} {FRAME:mul#1.itm#1(9)} -attr xrf 11636 -attr oid 24 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#4.itm#1(0)} -attr vt d
+load net {FRAME:mul#4.itm#1(1)} -attr vt d
+load net {FRAME:mul#4.itm#1(2)} -attr vt d
+load net {FRAME:mul#4.itm#1(3)} -attr vt d
+load net {FRAME:mul#4.itm#1(4)} -attr vt d
+load net {FRAME:mul#4.itm#1(5)} -attr vt d
+load net {FRAME:mul#4.itm#1(6)} -attr vt d
+load net {FRAME:mul#4.itm#1(7)} -attr vt d
+load net {FRAME:mul#4.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#4.itm#1} 9 {FRAME:mul#4.itm#1(0)} {FRAME:mul#4.itm#1(1)} {FRAME:mul#4.itm#1(2)} {FRAME:mul#4.itm#1(3)} {FRAME:mul#4.itm#1(4)} {FRAME:mul#4.itm#1(5)} {FRAME:mul#4.itm#1(6)} {FRAME:mul#4.itm#1(7)} {FRAME:mul#4.itm#1(8)} -attr xrf 11637 -attr oid 25 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:slc(blue)#10.itm#1(0)} -attr vt d
+load net {FRAME:slc(blue)#10.itm#1(1)} -attr vt d
+load net {FRAME:slc(blue)#10.itm#1(2)} -attr vt d
+load net {FRAME:slc(blue)#10.itm#1(3)} -attr vt d
+load net {FRAME:slc(blue)#10.itm#1(4)} -attr vt d
+load net {FRAME:slc(blue)#10.itm#1(5)} -attr vt d
+load netBundle {FRAME:slc(blue)#10.itm#1} 6 {FRAME:slc(blue)#10.itm#1(0)} {FRAME:slc(blue)#10.itm#1(1)} {FRAME:slc(blue)#10.itm#1(2)} {FRAME:slc(blue)#10.itm#1(3)} {FRAME:slc(blue)#10.itm#1(4)} {FRAME:slc(blue)#10.itm#1(5)} -attr xrf 11638 -attr oid 26 -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(blue)#10.itm#1}
+load net {FRAME:acc#40.itm#1(0)} -attr vt d
+load net {FRAME:acc#40.itm#1(1)} -attr vt d
+load net {FRAME:acc#40.itm#1(2)} -attr vt d
+load net {FRAME:acc#40.itm#1(3)} -attr vt d
+load net {FRAME:acc#40.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#40.itm#1} 5 {FRAME:acc#40.itm#1(0)} {FRAME:acc#40.itm#1(1)} {FRAME:acc#40.itm#1(2)} {FRAME:acc#40.itm#1(3)} {FRAME:acc#40.itm#1(4)} -attr xrf 11639 -attr oid 27 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm#1}
+load net {FRAME:mul#5.itm#1(0)} -attr vt d
+load net {FRAME:mul#5.itm#1(1)} -attr vt d
+load net {FRAME:mul#5.itm#1(2)} -attr vt d
+load net {FRAME:mul#5.itm#1(3)} -attr vt d
+load net {FRAME:mul#5.itm#1(4)} -attr vt d
+load net {FRAME:mul#5.itm#1(5)} -attr vt d
+load net {FRAME:mul#5.itm#1(6)} -attr vt d
+load net {FRAME:mul#5.itm#1(7)} -attr vt d
+load net {FRAME:mul#5.itm#1(8)} -attr vt d
+load net {FRAME:mul#5.itm#1(9)} -attr vt d
+load net {FRAME:mul#5.itm#1(10)} -attr vt d
+load net {FRAME:mul#5.itm#1(11)} -attr vt d
+load netBundle {FRAME:mul#5.itm#1} 12 {FRAME:mul#5.itm#1(0)} {FRAME:mul#5.itm#1(1)} {FRAME:mul#5.itm#1(2)} {FRAME:mul#5.itm#1(3)} {FRAME:mul#5.itm#1(4)} {FRAME:mul#5.itm#1(5)} {FRAME:mul#5.itm#1(6)} {FRAME:mul#5.itm#1(7)} {FRAME:mul#5.itm#1(8)} {FRAME:mul#5.itm#1(9)} {FRAME:mul#5.itm#1(10)} {FRAME:mul#5.itm#1(11)} -attr xrf 11640 -attr oid 28 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:p#1.sva#1(0)} -attr vt d
+load net {FRAME:p#1.sva#1(1)} -attr vt d
+load net {FRAME:p#1.sva#1(2)} -attr vt d
+load net {FRAME:p#1.sva#1(3)} -attr vt d
+load net {FRAME:p#1.sva#1(4)} -attr vt d
+load net {FRAME:p#1.sva#1(5)} -attr vt d
+load net {FRAME:p#1.sva#1(6)} -attr vt d
+load net {FRAME:p#1.sva#1(7)} -attr vt d
+load net {FRAME:p#1.sva#1(8)} -attr vt d
+load net {FRAME:p#1.sva#1(9)} -attr vt d
+load net {FRAME:p#1.sva#1(10)} -attr vt d
+load net {FRAME:p#1.sva#1(11)} -attr vt d
+load net {FRAME:p#1.sva#1(12)} -attr vt d
+load net {FRAME:p#1.sva#1(13)} -attr vt d
+load net {FRAME:p#1.sva#1(14)} -attr vt d
+load net {FRAME:p#1.sva#1(15)} -attr vt d
+load net {FRAME:p#1.sva#1(16)} -attr vt d
+load net {FRAME:p#1.sva#1(17)} -attr vt d
+load net {FRAME:p#1.sva#1(18)} -attr vt d
+load netBundle {FRAME:p#1.sva#1} 19 {FRAME:p#1.sva#1(0)} {FRAME:p#1.sva#1(1)} {FRAME:p#1.sva#1(2)} {FRAME:p#1.sva#1(3)} {FRAME:p#1.sva#1(4)} {FRAME:p#1.sva#1(5)} {FRAME:p#1.sva#1(6)} {FRAME:p#1.sva#1(7)} {FRAME:p#1.sva#1(8)} {FRAME:p#1.sva#1(9)} {FRAME:p#1.sva#1(10)} {FRAME:p#1.sva#1(11)} {FRAME:p#1.sva#1(12)} {FRAME:p#1.sva#1(13)} {FRAME:p#1.sva#1(14)} {FRAME:p#1.sva#1(15)} {FRAME:p#1.sva#1(16)} {FRAME:p#1.sva#1(17)} {FRAME:p#1.sva#1(18)} -attr xrf 11641 -attr oid 29 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:acc#3.psp.sva(0)} -attr vt d
+load net {FRAME:acc#3.psp.sva(1)} -attr vt d
+load net {FRAME:acc#3.psp.sva(2)} -attr vt d
+load net {FRAME:acc#3.psp.sva(3)} -attr vt d
+load net {FRAME:acc#3.psp.sva(4)} -attr vt d
+load net {FRAME:acc#3.psp.sva(5)} -attr vt d
+load net {FRAME:acc#3.psp.sva(6)} -attr vt d
+load net {FRAME:acc#3.psp.sva(7)} -attr vt d
+load net {FRAME:acc#3.psp.sva(8)} -attr vt d
+load net {FRAME:acc#3.psp.sva(9)} -attr vt d
+load net {FRAME:acc#3.psp.sva(10)} -attr vt d
+load net {FRAME:acc#3.psp.sva(11)} -attr vt d
+load netBundle {FRAME:acc#3.psp.sva} 12 {FRAME:acc#3.psp.sva(0)} {FRAME:acc#3.psp.sva(1)} {FRAME:acc#3.psp.sva(2)} {FRAME:acc#3.psp.sva(3)} {FRAME:acc#3.psp.sva(4)} {FRAME:acc#3.psp.sva(5)} {FRAME:acc#3.psp.sva(6)} {FRAME:acc#3.psp.sva(7)} {FRAME:acc#3.psp.sva(8)} {FRAME:acc#3.psp.sva(9)} {FRAME:acc#3.psp.sva(10)} {FRAME:acc#3.psp.sva(11)} -attr xrf 11642 -attr oid 30 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {i#6.sva#2(0)} -attr vt d
+load net {i#6.sva#2(1)} -attr vt d
+load netBundle {i#6.sva#2} 2 {i#6.sva#2(0)} {i#6.sva#2(1)} -attr xrf 11643 -attr oid 31 -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.lpi#1.dfm(0)} -attr vt d
+load net {i#6.lpi#1.dfm(1)} -attr vt d
+load netBundle {i#6.lpi#1.dfm} 2 {i#6.lpi#1.dfm(0)} {i#6.lpi#1.dfm(1)} -attr xrf 11644 -attr oid 32 -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm:mx0} 90 {regs.regs(2).lpi#1.dfm:mx0(0)} {regs.regs(2).lpi#1.dfm:mx0(1)} {regs.regs(2).lpi#1.dfm:mx0(2)} {regs.regs(2).lpi#1.dfm:mx0(3)} {regs.regs(2).lpi#1.dfm:mx0(4)} {regs.regs(2).lpi#1.dfm:mx0(5)} {regs.regs(2).lpi#1.dfm:mx0(6)} {regs.regs(2).lpi#1.dfm:mx0(7)} {regs.regs(2).lpi#1.dfm:mx0(8)} {regs.regs(2).lpi#1.dfm:mx0(9)} {regs.regs(2).lpi#1.dfm:mx0(10)} {regs.regs(2).lpi#1.dfm:mx0(11)} {regs.regs(2).lpi#1.dfm:mx0(12)} {regs.regs(2).lpi#1.dfm:mx0(13)} {regs.regs(2).lpi#1.dfm:mx0(14)} {regs.regs(2).lpi#1.dfm:mx0(15)} {regs.regs(2).lpi#1.dfm:mx0(16)} {regs.regs(2).lpi#1.dfm:mx0(17)} {regs.regs(2).lpi#1.dfm:mx0(18)} {regs.regs(2).lpi#1.dfm:mx0(19)} {regs.regs(2).lpi#1.dfm:mx0(20)} {regs.regs(2).lpi#1.dfm:mx0(21)} {regs.regs(2).lpi#1.dfm:mx0(22)} {regs.regs(2).lpi#1.dfm:mx0(23)} {regs.regs(2).lpi#1.dfm:mx0(24)} {regs.regs(2).lpi#1.dfm:mx0(25)} {regs.regs(2).lpi#1.dfm:mx0(26)} {regs.regs(2).lpi#1.dfm:mx0(27)} {regs.regs(2).lpi#1.dfm:mx0(28)} {regs.regs(2).lpi#1.dfm:mx0(29)} {regs.regs(2).lpi#1.dfm:mx0(30)} {regs.regs(2).lpi#1.dfm:mx0(31)} {regs.regs(2).lpi#1.dfm:mx0(32)} {regs.regs(2).lpi#1.dfm:mx0(33)} {regs.regs(2).lpi#1.dfm:mx0(34)} {regs.regs(2).lpi#1.dfm:mx0(35)} {regs.regs(2).lpi#1.dfm:mx0(36)} {regs.regs(2).lpi#1.dfm:mx0(37)} {regs.regs(2).lpi#1.dfm:mx0(38)} {regs.regs(2).lpi#1.dfm:mx0(39)} {regs.regs(2).lpi#1.dfm:mx0(40)} {regs.regs(2).lpi#1.dfm:mx0(41)} {regs.regs(2).lpi#1.dfm:mx0(42)} {regs.regs(2).lpi#1.dfm:mx0(43)} {regs.regs(2).lpi#1.dfm:mx0(44)} {regs.regs(2).lpi#1.dfm:mx0(45)} {regs.regs(2).lpi#1.dfm:mx0(46)} {regs.regs(2).lpi#1.dfm:mx0(47)} {regs.regs(2).lpi#1.dfm:mx0(48)} {regs.regs(2).lpi#1.dfm:mx0(49)} {regs.regs(2).lpi#1.dfm:mx0(50)} {regs.regs(2).lpi#1.dfm:mx0(51)} {regs.regs(2).lpi#1.dfm:mx0(52)} {regs.regs(2).lpi#1.dfm:mx0(53)} {regs.regs(2).lpi#1.dfm:mx0(54)} {regs.regs(2).lpi#1.dfm:mx0(55)} {regs.regs(2).lpi#1.dfm:mx0(56)} {regs.regs(2).lpi#1.dfm:mx0(57)} {regs.regs(2).lpi#1.dfm:mx0(58)} {regs.regs(2).lpi#1.dfm:mx0(59)} {regs.regs(2).lpi#1.dfm:mx0(60)} {regs.regs(2).lpi#1.dfm:mx0(61)} {regs.regs(2).lpi#1.dfm:mx0(62)} {regs.regs(2).lpi#1.dfm:mx0(63)} {regs.regs(2).lpi#1.dfm:mx0(64)} {regs.regs(2).lpi#1.dfm:mx0(65)} {regs.regs(2).lpi#1.dfm:mx0(66)} {regs.regs(2).lpi#1.dfm:mx0(67)} {regs.regs(2).lpi#1.dfm:mx0(68)} {regs.regs(2).lpi#1.dfm:mx0(69)} {regs.regs(2).lpi#1.dfm:mx0(70)} {regs.regs(2).lpi#1.dfm:mx0(71)} {regs.regs(2).lpi#1.dfm:mx0(72)} {regs.regs(2).lpi#1.dfm:mx0(73)} {regs.regs(2).lpi#1.dfm:mx0(74)} {regs.regs(2).lpi#1.dfm:mx0(75)} {regs.regs(2).lpi#1.dfm:mx0(76)} {regs.regs(2).lpi#1.dfm:mx0(77)} {regs.regs(2).lpi#1.dfm:mx0(78)} {regs.regs(2).lpi#1.dfm:mx0(79)} {regs.regs(2).lpi#1.dfm:mx0(80)} {regs.regs(2).lpi#1.dfm:mx0(81)} {regs.regs(2).lpi#1.dfm:mx0(82)} {regs.regs(2).lpi#1.dfm:mx0(83)} {regs.regs(2).lpi#1.dfm:mx0(84)} {regs.regs(2).lpi#1.dfm:mx0(85)} {regs.regs(2).lpi#1.dfm:mx0(86)} {regs.regs(2).lpi#1.dfm:mx0(87)} {regs.regs(2).lpi#1.dfm:mx0(88)} {regs.regs(2).lpi#1.dfm:mx0(89)} -attr xrf 11645 -attr oid 33 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(1).sva.dfm:mx0} 90 {regs.regs(1).sva.dfm:mx0(0)} {regs.regs(1).sva.dfm:mx0(1)} {regs.regs(1).sva.dfm:mx0(2)} {regs.regs(1).sva.dfm:mx0(3)} {regs.regs(1).sva.dfm:mx0(4)} {regs.regs(1).sva.dfm:mx0(5)} {regs.regs(1).sva.dfm:mx0(6)} {regs.regs(1).sva.dfm:mx0(7)} {regs.regs(1).sva.dfm:mx0(8)} {regs.regs(1).sva.dfm:mx0(9)} {regs.regs(1).sva.dfm:mx0(10)} {regs.regs(1).sva.dfm:mx0(11)} {regs.regs(1).sva.dfm:mx0(12)} {regs.regs(1).sva.dfm:mx0(13)} {regs.regs(1).sva.dfm:mx0(14)} {regs.regs(1).sva.dfm:mx0(15)} {regs.regs(1).sva.dfm:mx0(16)} {regs.regs(1).sva.dfm:mx0(17)} {regs.regs(1).sva.dfm:mx0(18)} {regs.regs(1).sva.dfm:mx0(19)} {regs.regs(1).sva.dfm:mx0(20)} {regs.regs(1).sva.dfm:mx0(21)} {regs.regs(1).sva.dfm:mx0(22)} {regs.regs(1).sva.dfm:mx0(23)} {regs.regs(1).sva.dfm:mx0(24)} {regs.regs(1).sva.dfm:mx0(25)} {regs.regs(1).sva.dfm:mx0(26)} {regs.regs(1).sva.dfm:mx0(27)} {regs.regs(1).sva.dfm:mx0(28)} {regs.regs(1).sva.dfm:mx0(29)} {regs.regs(1).sva.dfm:mx0(30)} {regs.regs(1).sva.dfm:mx0(31)} {regs.regs(1).sva.dfm:mx0(32)} {regs.regs(1).sva.dfm:mx0(33)} {regs.regs(1).sva.dfm:mx0(34)} {regs.regs(1).sva.dfm:mx0(35)} {regs.regs(1).sva.dfm:mx0(36)} {regs.regs(1).sva.dfm:mx0(37)} {regs.regs(1).sva.dfm:mx0(38)} {regs.regs(1).sva.dfm:mx0(39)} {regs.regs(1).sva.dfm:mx0(40)} {regs.regs(1).sva.dfm:mx0(41)} {regs.regs(1).sva.dfm:mx0(42)} {regs.regs(1).sva.dfm:mx0(43)} {regs.regs(1).sva.dfm:mx0(44)} {regs.regs(1).sva.dfm:mx0(45)} {regs.regs(1).sva.dfm:mx0(46)} {regs.regs(1).sva.dfm:mx0(47)} {regs.regs(1).sva.dfm:mx0(48)} {regs.regs(1).sva.dfm:mx0(49)} {regs.regs(1).sva.dfm:mx0(50)} {regs.regs(1).sva.dfm:mx0(51)} {regs.regs(1).sva.dfm:mx0(52)} {regs.regs(1).sva.dfm:mx0(53)} {regs.regs(1).sva.dfm:mx0(54)} {regs.regs(1).sva.dfm:mx0(55)} {regs.regs(1).sva.dfm:mx0(56)} {regs.regs(1).sva.dfm:mx0(57)} {regs.regs(1).sva.dfm:mx0(58)} {regs.regs(1).sva.dfm:mx0(59)} {regs.regs(1).sva.dfm:mx0(60)} {regs.regs(1).sva.dfm:mx0(61)} {regs.regs(1).sva.dfm:mx0(62)} {regs.regs(1).sva.dfm:mx0(63)} {regs.regs(1).sva.dfm:mx0(64)} {regs.regs(1).sva.dfm:mx0(65)} {regs.regs(1).sva.dfm:mx0(66)} {regs.regs(1).sva.dfm:mx0(67)} {regs.regs(1).sva.dfm:mx0(68)} {regs.regs(1).sva.dfm:mx0(69)} {regs.regs(1).sva.dfm:mx0(70)} {regs.regs(1).sva.dfm:mx0(71)} {regs.regs(1).sva.dfm:mx0(72)} {regs.regs(1).sva.dfm:mx0(73)} {regs.regs(1).sva.dfm:mx0(74)} {regs.regs(1).sva.dfm:mx0(75)} {regs.regs(1).sva.dfm:mx0(76)} {regs.regs(1).sva.dfm:mx0(77)} {regs.regs(1).sva.dfm:mx0(78)} {regs.regs(1).sva.dfm:mx0(79)} {regs.regs(1).sva.dfm:mx0(80)} {regs.regs(1).sva.dfm:mx0(81)} {regs.regs(1).sva.dfm:mx0(82)} {regs.regs(1).sva.dfm:mx0(83)} {regs.regs(1).sva.dfm:mx0(84)} {regs.regs(1).sva.dfm:mx0(85)} {regs.regs(1).sva.dfm:mx0(86)} {regs.regs(1).sva.dfm:mx0(87)} {regs.regs(1).sva.dfm:mx0(88)} {regs.regs(1).sva.dfm:mx0(89)} -attr xrf 11646 -attr oid 34 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(0).sva.dfm:mx0} 90 {regs.regs(0).sva.dfm:mx0(0)} {regs.regs(0).sva.dfm:mx0(1)} {regs.regs(0).sva.dfm:mx0(2)} {regs.regs(0).sva.dfm:mx0(3)} {regs.regs(0).sva.dfm:mx0(4)} {regs.regs(0).sva.dfm:mx0(5)} {regs.regs(0).sva.dfm:mx0(6)} {regs.regs(0).sva.dfm:mx0(7)} {regs.regs(0).sva.dfm:mx0(8)} {regs.regs(0).sva.dfm:mx0(9)} {regs.regs(0).sva.dfm:mx0(10)} {regs.regs(0).sva.dfm:mx0(11)} {regs.regs(0).sva.dfm:mx0(12)} {regs.regs(0).sva.dfm:mx0(13)} {regs.regs(0).sva.dfm:mx0(14)} {regs.regs(0).sva.dfm:mx0(15)} {regs.regs(0).sva.dfm:mx0(16)} {regs.regs(0).sva.dfm:mx0(17)} {regs.regs(0).sva.dfm:mx0(18)} {regs.regs(0).sva.dfm:mx0(19)} {regs.regs(0).sva.dfm:mx0(20)} {regs.regs(0).sva.dfm:mx0(21)} {regs.regs(0).sva.dfm:mx0(22)} {regs.regs(0).sva.dfm:mx0(23)} {regs.regs(0).sva.dfm:mx0(24)} {regs.regs(0).sva.dfm:mx0(25)} {regs.regs(0).sva.dfm:mx0(26)} {regs.regs(0).sva.dfm:mx0(27)} {regs.regs(0).sva.dfm:mx0(28)} {regs.regs(0).sva.dfm:mx0(29)} {regs.regs(0).sva.dfm:mx0(30)} {regs.regs(0).sva.dfm:mx0(31)} {regs.regs(0).sva.dfm:mx0(32)} {regs.regs(0).sva.dfm:mx0(33)} {regs.regs(0).sva.dfm:mx0(34)} {regs.regs(0).sva.dfm:mx0(35)} {regs.regs(0).sva.dfm:mx0(36)} {regs.regs(0).sva.dfm:mx0(37)} {regs.regs(0).sva.dfm:mx0(38)} {regs.regs(0).sva.dfm:mx0(39)} {regs.regs(0).sva.dfm:mx0(40)} {regs.regs(0).sva.dfm:mx0(41)} {regs.regs(0).sva.dfm:mx0(42)} {regs.regs(0).sva.dfm:mx0(43)} {regs.regs(0).sva.dfm:mx0(44)} {regs.regs(0).sva.dfm:mx0(45)} {regs.regs(0).sva.dfm:mx0(46)} {regs.regs(0).sva.dfm:mx0(47)} {regs.regs(0).sva.dfm:mx0(48)} {regs.regs(0).sva.dfm:mx0(49)} {regs.regs(0).sva.dfm:mx0(50)} {regs.regs(0).sva.dfm:mx0(51)} {regs.regs(0).sva.dfm:mx0(52)} {regs.regs(0).sva.dfm:mx0(53)} {regs.regs(0).sva.dfm:mx0(54)} {regs.regs(0).sva.dfm:mx0(55)} {regs.regs(0).sva.dfm:mx0(56)} {regs.regs(0).sva.dfm:mx0(57)} {regs.regs(0).sva.dfm:mx0(58)} {regs.regs(0).sva.dfm:mx0(59)} {regs.regs(0).sva.dfm:mx0(60)} {regs.regs(0).sva.dfm:mx0(61)} {regs.regs(0).sva.dfm:mx0(62)} {regs.regs(0).sva.dfm:mx0(63)} {regs.regs(0).sva.dfm:mx0(64)} {regs.regs(0).sva.dfm:mx0(65)} {regs.regs(0).sva.dfm:mx0(66)} {regs.regs(0).sva.dfm:mx0(67)} {regs.regs(0).sva.dfm:mx0(68)} {regs.regs(0).sva.dfm:mx0(69)} {regs.regs(0).sva.dfm:mx0(70)} {regs.regs(0).sva.dfm:mx0(71)} {regs.regs(0).sva.dfm:mx0(72)} {regs.regs(0).sva.dfm:mx0(73)} {regs.regs(0).sva.dfm:mx0(74)} {regs.regs(0).sva.dfm:mx0(75)} {regs.regs(0).sva.dfm:mx0(76)} {regs.regs(0).sva.dfm:mx0(77)} {regs.regs(0).sva.dfm:mx0(78)} {regs.regs(0).sva.dfm:mx0(79)} {regs.regs(0).sva.dfm:mx0(80)} {regs.regs(0).sva.dfm:mx0(81)} {regs.regs(0).sva.dfm:mx0(82)} {regs.regs(0).sva.dfm:mx0(83)} {regs.regs(0).sva.dfm:mx0(84)} {regs.regs(0).sva.dfm:mx0(85)} {regs.regs(0).sva.dfm:mx0(86)} {regs.regs(0).sva.dfm:mx0(87)} {regs.regs(0).sva.dfm:mx0(88)} {regs.regs(0).sva.dfm:mx0(89)} -attr xrf 11647 -attr oid 35 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {FRAME:p#1.lpi#1.dfm(0)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(1)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(2)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(3)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(4)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(5)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(6)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(7)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(8)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(9)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(10)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(11)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(12)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(13)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(14)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(15)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(16)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(17)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(18)} -attr vt d
+load netBundle {FRAME:p#1.lpi#1.dfm} 19 {FRAME:p#1.lpi#1.dfm(0)} {FRAME:p#1.lpi#1.dfm(1)} {FRAME:p#1.lpi#1.dfm(2)} {FRAME:p#1.lpi#1.dfm(3)} {FRAME:p#1.lpi#1.dfm(4)} {FRAME:p#1.lpi#1.dfm(5)} {FRAME:p#1.lpi#1.dfm(6)} {FRAME:p#1.lpi#1.dfm(7)} {FRAME:p#1.lpi#1.dfm(8)} {FRAME:p#1.lpi#1.dfm(9)} {FRAME:p#1.lpi#1.dfm(10)} {FRAME:p#1.lpi#1.dfm(11)} {FRAME:p#1.lpi#1.dfm(12)} {FRAME:p#1.lpi#1.dfm(13)} {FRAME:p#1.lpi#1.dfm(14)} {FRAME:p#1.lpi#1.dfm(15)} {FRAME:p#1.lpi#1.dfm(16)} {FRAME:p#1.lpi#1.dfm(17)} {FRAME:p#1.lpi#1.dfm(18)} -attr xrf 11648 -attr oid 36 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {blue#2.sva(0)} -attr vt d
+load net {blue#2.sva(1)} -attr vt d
+load net {blue#2.sva(2)} -attr vt d
+load net {blue#2.sva(3)} -attr vt d
+load net {blue#2.sva(4)} -attr vt d
+load net {blue#2.sva(5)} -attr vt d
+load net {blue#2.sva(6)} -attr vt d
+load net {blue#2.sva(7)} -attr vt d
+load net {blue#2.sva(8)} -attr vt d
+load net {blue#2.sva(9)} -attr vt d
+load net {blue#2.sva(10)} -attr vt d
+load net {blue#2.sva(11)} -attr vt d
+load net {blue#2.sva(12)} -attr vt d
+load net {blue#2.sva(13)} -attr vt d
+load net {blue#2.sva(14)} -attr vt d
+load net {blue#2.sva(15)} -attr vt d
+load netBundle {blue#2.sva} 16 {blue#2.sva(0)} {blue#2.sva(1)} {blue#2.sva(2)} {blue#2.sva(3)} {blue#2.sva(4)} {blue#2.sva(5)} {blue#2.sva(6)} {blue#2.sva(7)} {blue#2.sva(8)} {blue#2.sva(9)} {blue#2.sva(10)} {blue#2.sva(11)} {blue#2.sva(12)} {blue#2.sva(13)} {blue#2.sva(14)} {blue#2.sva(15)} -attr xrf 11649 -attr oid 37 -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {FRAME:acc#11.psp.sva(0)} -attr vt d
+load net {FRAME:acc#11.psp.sva(1)} -attr vt d
+load net {FRAME:acc#11.psp.sva(2)} -attr vt d
+load net {FRAME:acc#11.psp.sva(3)} -attr vt d
+load net {FRAME:acc#11.psp.sva(4)} -attr vt d
+load net {FRAME:acc#11.psp.sva(5)} -attr vt d
+load netBundle {FRAME:acc#11.psp.sva} 6 {FRAME:acc#11.psp.sva(0)} {FRAME:acc#11.psp.sva(1)} {FRAME:acc#11.psp.sva(2)} {FRAME:acc#11.psp.sva(3)} {FRAME:acc#11.psp.sva(4)} {FRAME:acc#11.psp.sva(5)} -attr xrf 11650 -attr oid 38 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.psp.sva}
+load net {red#2.sva(0)} -attr vt d
+load net {red#2.sva(1)} -attr vt d
+load net {red#2.sva(2)} -attr vt d
+load net {red#2.sva(3)} -attr vt d
+load net {red#2.sva(4)} -attr vt d
+load net {red#2.sva(5)} -attr vt d
+load net {red#2.sva(6)} -attr vt d
+load net {red#2.sva(7)} -attr vt d
+load net {red#2.sva(8)} -attr vt d
+load net {red#2.sva(9)} -attr vt d
+load net {red#2.sva(10)} -attr vt d
+load net {red#2.sva(11)} -attr vt d
+load net {red#2.sva(12)} -attr vt d
+load net {red#2.sva(13)} -attr vt d
+load net {red#2.sva(14)} -attr vt d
+load net {red#2.sva(15)} -attr vt d
+load netBundle {red#2.sva} 16 {red#2.sva(0)} {red#2.sva(1)} {red#2.sva(2)} {red#2.sva(3)} {red#2.sva(4)} {red#2.sva(5)} {red#2.sva(6)} {red#2.sva(7)} {red#2.sva(8)} {red#2.sva(9)} {red#2.sva(10)} {red#2.sva(11)} {red#2.sva(12)} {red#2.sva(13)} {red#2.sva(14)} {red#2.sva(15)} -attr xrf 11651 -attr oid 39 -attr vt d -attr @path {/sobel/sobel:core/red#2.sva}
+load net {FRAME:acc#7.psp.sva(0)} -attr vt d
+load net {FRAME:acc#7.psp.sva(1)} -attr vt d
+load net {FRAME:acc#7.psp.sva(2)} -attr vt d
+load net {FRAME:acc#7.psp.sva(3)} -attr vt d
+load net {FRAME:acc#7.psp.sva(4)} -attr vt d
+load net {FRAME:acc#7.psp.sva(5)} -attr vt d
+load netBundle {FRAME:acc#7.psp.sva} 6 {FRAME:acc#7.psp.sva(0)} {FRAME:acc#7.psp.sva(1)} {FRAME:acc#7.psp.sva(2)} {FRAME:acc#7.psp.sva(3)} {FRAME:acc#7.psp.sva(4)} {FRAME:acc#7.psp.sva(5)} -attr xrf 11652 -attr oid 40 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.psp.sva}
+load net {FRAME:acc#28.sdt(0)} -attr vt d
+load net {FRAME:acc#28.sdt(1)} -attr vt d
+load net {FRAME:acc#28.sdt(2)} -attr vt d
+load net {FRAME:acc#28.sdt(3)} -attr vt d
+load net {FRAME:acc#28.sdt(4)} -attr vt d
+load netBundle {FRAME:acc#28.sdt} 5 {FRAME:acc#28.sdt(0)} {FRAME:acc#28.sdt(1)} {FRAME:acc#28.sdt(2)} {FRAME:acc#28.sdt(3)} {FRAME:acc#28.sdt(4)} -attr xrf 11653 -attr oid 41 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.sdt}
+load net {green#2.sva(0)} -attr vt d
+load net {green#2.sva(1)} -attr vt d
+load net {green#2.sva(2)} -attr vt d
+load net {green#2.sva(3)} -attr vt d
+load net {green#2.sva(4)} -attr vt d
+load net {green#2.sva(5)} -attr vt d
+load net {green#2.sva(6)} -attr vt d
+load net {green#2.sva(7)} -attr vt d
+load net {green#2.sva(8)} -attr vt d
+load net {green#2.sva(9)} -attr vt d
+load net {green#2.sva(10)} -attr vt d
+load net {green#2.sva(11)} -attr vt d
+load net {green#2.sva(12)} -attr vt d
+load net {green#2.sva(13)} -attr vt d
+load net {green#2.sva(14)} -attr vt d
+load net {green#2.sva(15)} -attr vt d
+load netBundle {green#2.sva} 16 {green#2.sva(0)} {green#2.sva(1)} {green#2.sva(2)} {green#2.sva(3)} {green#2.sva(4)} {green#2.sva(5)} {green#2.sva(6)} {green#2.sva(7)} {green#2.sva(8)} {green#2.sva(9)} {green#2.sva(10)} {green#2.sva(11)} {green#2.sva(12)} {green#2.sva(13)} {green#2.sva(14)} {green#2.sva(15)} -attr xrf 11654 -attr oid 42 -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {FRAME:acc#9.psp.sva(0)} -attr vt d
+load net {FRAME:acc#9.psp.sva(1)} -attr vt d
+load net {FRAME:acc#9.psp.sva(2)} -attr vt d
+load net {FRAME:acc#9.psp.sva(3)} -attr vt d
+load net {FRAME:acc#9.psp.sva(4)} -attr vt d
+load net {FRAME:acc#9.psp.sva(5)} -attr vt d
+load netBundle {FRAME:acc#9.psp.sva} 6 {FRAME:acc#9.psp.sva(0)} {FRAME:acc#9.psp.sva(1)} {FRAME:acc#9.psp.sva(2)} {FRAME:acc#9.psp.sva(3)} {FRAME:acc#9.psp.sva(4)} {FRAME:acc#9.psp.sva(5)} -attr xrf 11655 -attr oid 43 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.psp.sva}
+load net {FRAME:acc#18.sdt(0)} -attr vt d
+load net {FRAME:acc#18.sdt(1)} -attr vt d
+load net {FRAME:acc#18.sdt(2)} -attr vt d
+load net {FRAME:acc#18.sdt(3)} -attr vt d
+load net {FRAME:acc#18.sdt(4)} -attr vt d
+load netBundle {FRAME:acc#18.sdt} 5 {FRAME:acc#18.sdt(0)} {FRAME:acc#18.sdt(1)} {FRAME:acc#18.sdt(2)} {FRAME:acc#18.sdt(3)} {FRAME:acc#18.sdt(4)} -attr xrf 11656 -attr oid 44 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.sdt}
+load net {FRAME:acc#13.sdt(0)} -attr vt d
+load net {FRAME:acc#13.sdt(1)} -attr vt d
+load net {FRAME:acc#13.sdt(2)} -attr vt d
+load net {FRAME:acc#13.sdt(3)} -attr vt d
+load net {FRAME:acc#13.sdt(4)} -attr vt d
+load netBundle {FRAME:acc#13.sdt} 5 {FRAME:acc#13.sdt(0)} {FRAME:acc#13.sdt(1)} {FRAME:acc#13.sdt(2)} {FRAME:acc#13.sdt(3)} {FRAME:acc#13.sdt(4)} -attr xrf 11657 -attr oid 45 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.sdt}
+load net {b(2).sva#3(0)} -attr vt d
+load net {b(2).sva#3(1)} -attr vt d
+load net {b(2).sva#3(2)} -attr vt d
+load net {b(2).sva#3(3)} -attr vt d
+load net {b(2).sva#3(4)} -attr vt d
+load net {b(2).sva#3(5)} -attr vt d
+load net {b(2).sva#3(6)} -attr vt d
+load net {b(2).sva#3(7)} -attr vt d
+load net {b(2).sva#3(8)} -attr vt d
+load net {b(2).sva#3(9)} -attr vt d
+load net {b(2).sva#3(10)} -attr vt d
+load net {b(2).sva#3(11)} -attr vt d
+load net {b(2).sva#3(12)} -attr vt d
+load net {b(2).sva#3(13)} -attr vt d
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+load net {slc(FRAME:acc#3.psp.sva).itm(0)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva).itm(1)} -attr vt d
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+load net {slc(FRAME:acc#3.psp.sva)#1.itm(0)} -attr vt d
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+load net {FRAME:exs#5.itm(0)} -attr vt d
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+load net {FRAME:acc#4.itm(0)} -attr vt d
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+load net {FRAME:mul.itm(0)} -attr vt d
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+load netBundle {FRAME:mul.itm} 9 {FRAME:mul.itm(0)} {FRAME:mul.itm(1)} {FRAME:mul.itm(2)} {FRAME:mul.itm(3)} {FRAME:mul.itm(4)} {FRAME:mul.itm(5)} {FRAME:mul.itm(6)} {FRAME:mul.itm(7)} {FRAME:mul.itm(8)} -attr xrf 11679 -attr oid 67 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {slc(red#2.sva)#5.itm(0)} -attr vt d
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+load netBundle {slc(red#2.sva)#5.itm} 3 {slc(red#2.sva)#5.itm(0)} {slc(red#2.sva)#5.itm(1)} {slc(red#2.sva)#5.itm(2)} -attr xrf 11680 -attr oid 68 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#5.itm}
+load net {slc(red#2.sva)#4.itm(0)} -attr vt d
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+load netBundle {slc(red#2.sva)#4.itm} 6 {slc(red#2.sva)#4.itm(0)} {slc(red#2.sva)#4.itm(1)} {slc(red#2.sva)#4.itm(2)} {slc(red#2.sva)#4.itm(3)} {slc(red#2.sva)#4.itm(4)} {slc(red#2.sva)#4.itm(5)} -attr xrf 11681 -attr oid 69 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#4.itm}
+load net {FRAME:acc#35.itm(0)} -attr vt d
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+load net {FRAME:slc#6.itm(0)} -attr vt d
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+load net {FRAME:acc#33.itm(0)} -attr vt d
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+load net {conc#137.itm(0)} -attr vt d
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+load net {slc(FRAME:acc#7.psp.sva)#1.itm(0)} -attr vt d
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+load net {FRAME:not#7.itm(0)} -attr vt d
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+load net {slc(red#2.sva)#3.itm(0)} -attr vt d
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+load netBundle {slc(red#2.sva)#3.itm} 3 {slc(red#2.sva)#3.itm(0)} {slc(red#2.sva)#3.itm(1)} {slc(red#2.sva)#3.itm(2)} -attr xrf 11690 -attr oid 78 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#3.itm}
+load net {conc#138.itm(0)} -attr vt d
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+load net {FRAME:mul#1.itm(0)} -attr vt d
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+load net {slc(red#2.sva)#10.itm(0)} -attr vt d
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+load netBundle {slc(red#2.sva)#10.itm} 3 {slc(red#2.sva)#10.itm(0)} {slc(red#2.sva)#10.itm(1)} {slc(red#2.sva)#10.itm(2)} -attr xrf 11693 -attr oid 81 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#10.itm}
+load net {FRAME:mul#4.itm(0)} -attr vt d
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+load netBundle {FRAME:mul#4.itm} 9 {FRAME:mul#4.itm(0)} {FRAME:mul#4.itm(1)} {FRAME:mul#4.itm(2)} {FRAME:mul#4.itm(3)} {FRAME:mul#4.itm(4)} {FRAME:mul#4.itm(5)} {FRAME:mul#4.itm(6)} {FRAME:mul#4.itm(7)} {FRAME:mul#4.itm(8)} -attr xrf 11694 -attr oid 82 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {slc(blue#2.sva)#5.itm(0)} -attr vt d
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+load netBundle {slc(blue#2.sva)#5.itm} 3 {slc(blue#2.sva)#5.itm(0)} {slc(blue#2.sva)#5.itm(1)} {slc(blue#2.sva)#5.itm(2)} -attr xrf 11695 -attr oid 83 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#5.itm}
+load net {slc(blue#2.sva)#4.itm(0)} -attr vt d
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+load netBundle {slc(blue#2.sva)#4.itm} 6 {slc(blue#2.sva)#4.itm(0)} {slc(blue#2.sva)#4.itm(1)} {slc(blue#2.sva)#4.itm(2)} {slc(blue#2.sva)#4.itm(3)} {slc(blue#2.sva)#4.itm(4)} {slc(blue#2.sva)#4.itm(5)} -attr xrf 11696 -attr oid 84 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#4.itm}
+load net {FRAME:acc#40.itm(0)} -attr vt d
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+load net {FRAME:acc#40.itm(4)} -attr vt d
+load netBundle {FRAME:acc#40.itm} 5 {FRAME:acc#40.itm(0)} {FRAME:acc#40.itm(1)} {FRAME:acc#40.itm(2)} {FRAME:acc#40.itm(3)} {FRAME:acc#40.itm(4)} -attr xrf 11697 -attr oid 85 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#39.itm(0)} -attr vt d
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+load net {FRAME:acc#39.itm(3)} -attr vt d
+load net {FRAME:acc#39.itm(4)} -attr vt d
+load netBundle {FRAME:acc#39.itm} 5 {FRAME:acc#39.itm(0)} {FRAME:acc#39.itm(1)} {FRAME:acc#39.itm(2)} {FRAME:acc#39.itm(3)} {FRAME:acc#39.itm(4)} -attr xrf 11698 -attr oid 86 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:slc#7.itm(0)} -attr vt d
+load net {FRAME:slc#7.itm(1)} -attr vt d
+load net {FRAME:slc#7.itm(2)} -attr vt d
+load net {FRAME:slc#7.itm(3)} -attr vt d
+load netBundle {FRAME:slc#7.itm} 4 {FRAME:slc#7.itm(0)} {FRAME:slc#7.itm(1)} {FRAME:slc#7.itm(2)} {FRAME:slc#7.itm(3)} -attr xrf 11699 -attr oid 87 -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:acc#38.itm(0)} -attr vt d
+load net {FRAME:acc#38.itm(1)} -attr vt d
+load net {FRAME:acc#38.itm(2)} -attr vt d
+load net {FRAME:acc#38.itm(3)} -attr vt d
+load net {FRAME:acc#38.itm(4)} -attr vt d
+load netBundle {FRAME:acc#38.itm} 5 {FRAME:acc#38.itm(0)} {FRAME:acc#38.itm(1)} {FRAME:acc#38.itm(2)} {FRAME:acc#38.itm(3)} {FRAME:acc#38.itm(4)} -attr xrf 11700 -attr oid 88 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {conc#139.itm(0)} -attr vt d
+load net {conc#139.itm(1)} -attr vt d
+load net {conc#139.itm(2)} -attr vt d
+load net {conc#139.itm(3)} -attr vt d
+load netBundle {conc#139.itm} 4 {conc#139.itm(0)} {conc#139.itm(1)} {conc#139.itm(2)} {conc#139.itm(3)} -attr xrf 11701 -attr oid 89 -attr vt d -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {FRAME:conc#82.itm(0)} -attr vt d
+load net {FRAME:conc#82.itm(1)} -attr vt d
+load net {FRAME:conc#82.itm(2)} -attr vt d
+load netBundle {FRAME:conc#82.itm} 3 {FRAME:conc#82.itm(0)} {FRAME:conc#82.itm(1)} {FRAME:conc#82.itm(2)} -attr xrf 11702 -attr oid 90 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#82.itm}
+load net {slc(FRAME:acc#11.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#11.psp.sva)#1.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#11.psp.sva)#1.itm} 2 {slc(FRAME:acc#11.psp.sva)#1.itm(0)} {slc(FRAME:acc#11.psp.sva)#1.itm(1)} -attr xrf 11703 -attr oid 91 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#11.psp.sva)#1.itm}
+load net {FRAME:not#25.itm(0)} -attr vt d
+load net {FRAME:not#25.itm(1)} -attr vt d
+load net {FRAME:not#25.itm(2)} -attr vt d
+load netBundle {FRAME:not#25.itm} 3 {FRAME:not#25.itm(0)} {FRAME:not#25.itm(1)} {FRAME:not#25.itm(2)} -attr xrf 11704 -attr oid 92 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {slc(blue#2.sva)#3.itm(0)} -attr vt d
+load net {slc(blue#2.sva)#3.itm(1)} -attr vt d
+load net {slc(blue#2.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sva)#3.itm} 3 {slc(blue#2.sva)#3.itm(0)} {slc(blue#2.sva)#3.itm(1)} {slc(blue#2.sva)#3.itm(2)} -attr xrf 11705 -attr oid 93 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#3.itm}
+load net {conc#140.itm(0)} -attr vt d
+load net {conc#140.itm(1)} -attr vt d
+load net {conc#140.itm(2)} -attr vt d
+load net {conc#140.itm(3)} -attr vt d
+load net {conc#140.itm(4)} -attr vt d
+load netBundle {conc#140.itm} 5 {conc#140.itm(0)} {conc#140.itm(1)} {conc#140.itm(2)} {conc#140.itm(3)} {conc#140.itm(4)} -attr xrf 11706 -attr oid 94 -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {FRAME:mul#5.itm(0)} -attr vt d
+load net {FRAME:mul#5.itm(1)} -attr vt d
+load net {FRAME:mul#5.itm(2)} -attr vt d
+load net {FRAME:mul#5.itm(3)} -attr vt d
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+load net {FRAME:mul#5.itm(5)} -attr vt d
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+load net {FRAME:mul#5.itm(7)} -attr vt d
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+load net {FRAME:mul#5.itm(11)} -attr vt d
+load netBundle {FRAME:mul#5.itm} 12 {FRAME:mul#5.itm(0)} {FRAME:mul#5.itm(1)} {FRAME:mul#5.itm(2)} {FRAME:mul#5.itm(3)} {FRAME:mul#5.itm(4)} {FRAME:mul#5.itm(5)} {FRAME:mul#5.itm(6)} {FRAME:mul#5.itm(7)} {FRAME:mul#5.itm(8)} {FRAME:mul#5.itm(9)} {FRAME:mul#5.itm(10)} {FRAME:mul#5.itm(11)} -attr xrf 11707 -attr oid 95 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {slc(blue#2.sva)#10.itm(0)} -attr vt d
+load net {slc(blue#2.sva)#10.itm(1)} -attr vt d
+load net {slc(blue#2.sva)#10.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sva)#10.itm} 3 {slc(blue#2.sva)#10.itm(0)} {slc(blue#2.sva)#10.itm(1)} {slc(blue#2.sva)#10.itm(2)} -attr xrf 11708 -attr oid 96 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#10.itm}
+load net {FRAME:mul#2.itm(0)} -attr vt d
+load net {FRAME:mul#2.itm(1)} -attr vt d
+load net {FRAME:mul#2.itm(2)} -attr vt d
+load net {FRAME:mul#2.itm(3)} -attr vt d
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+load net {FRAME:mul#2.itm(7)} -attr vt d
+load net {FRAME:mul#2.itm(8)} -attr vt d
+load netBundle {FRAME:mul#2.itm} 9 {FRAME:mul#2.itm(0)} {FRAME:mul#2.itm(1)} {FRAME:mul#2.itm(2)} {FRAME:mul#2.itm(3)} {FRAME:mul#2.itm(4)} {FRAME:mul#2.itm(5)} {FRAME:mul#2.itm(6)} {FRAME:mul#2.itm(7)} {FRAME:mul#2.itm(8)} -attr xrf 11709 -attr oid 97 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {slc(green#2.sva)#5.itm(0)} -attr vt d
+load net {slc(green#2.sva)#5.itm(1)} -attr vt d
+load net {slc(green#2.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(green#2.sva)#5.itm} 3 {slc(green#2.sva)#5.itm(0)} {slc(green#2.sva)#5.itm(1)} {slc(green#2.sva)#5.itm(2)} -attr xrf 11710 -attr oid 98 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#5.itm}
+load net {slc(green#2.sva)#4.itm(0)} -attr vt d
+load net {slc(green#2.sva)#4.itm(1)} -attr vt d
+load net {slc(green#2.sva)#4.itm(2)} -attr vt d
+load net {slc(green#2.sva)#4.itm(3)} -attr vt d
+load net {slc(green#2.sva)#4.itm(4)} -attr vt d
+load net {slc(green#2.sva)#4.itm(5)} -attr vt d
+load netBundle {slc(green#2.sva)#4.itm} 6 {slc(green#2.sva)#4.itm(0)} {slc(green#2.sva)#4.itm(1)} {slc(green#2.sva)#4.itm(2)} {slc(green#2.sva)#4.itm(3)} {slc(green#2.sva)#4.itm(4)} {slc(green#2.sva)#4.itm(5)} -attr xrf 11711 -attr oid 99 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#4.itm}
+load net {FRAME:acc#25.itm(0)} -attr vt d
+load net {FRAME:acc#25.itm(1)} -attr vt d
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+load net {FRAME:acc#25.itm(3)} -attr vt d
+load net {FRAME:acc#25.itm(4)} -attr vt d
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+load net {FRAME:acc#24.itm(0)} -attr vt d
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+load net {FRAME:acc#24.itm(4)} -attr vt d
+load netBundle {FRAME:acc#24.itm} 5 {FRAME:acc#24.itm(0)} {FRAME:acc#24.itm(1)} {FRAME:acc#24.itm(2)} {FRAME:acc#24.itm(3)} {FRAME:acc#24.itm(4)} -attr xrf 11713 -attr oid 101 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:slc#4.itm(0)} -attr vt d
+load net {FRAME:slc#4.itm(1)} -attr vt d
+load net {FRAME:slc#4.itm(2)} -attr vt d
+load net {FRAME:slc#4.itm(3)} -attr vt d
+load netBundle {FRAME:slc#4.itm} 4 {FRAME:slc#4.itm(0)} {FRAME:slc#4.itm(1)} {FRAME:slc#4.itm(2)} {FRAME:slc#4.itm(3)} -attr xrf 11714 -attr oid 102 -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#4.itm}
+load net {FRAME:acc#23.itm(0)} -attr vt d
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+load net {FRAME:acc#23.itm(4)} -attr vt d
+load netBundle {FRAME:acc#23.itm} 5 {FRAME:acc#23.itm(0)} {FRAME:acc#23.itm(1)} {FRAME:acc#23.itm(2)} {FRAME:acc#23.itm(3)} {FRAME:acc#23.itm(4)} -attr xrf 11715 -attr oid 103 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {conc#141.itm(0)} -attr vt d
+load net {conc#141.itm(1)} -attr vt d
+load net {conc#141.itm(2)} -attr vt d
+load net {conc#141.itm(3)} -attr vt d
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+load net {FRAME:conc#73.itm(0)} -attr vt d
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+load net {FRAME:conc#73.itm(2)} -attr vt d
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+load net {slc(FRAME:acc#9.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#9.psp.sva)#1.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#9.psp.sva)#1.itm} 2 {slc(FRAME:acc#9.psp.sva)#1.itm(0)} {slc(FRAME:acc#9.psp.sva)#1.itm(1)} -attr xrf 11718 -attr oid 106 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#9.psp.sva)#1.itm}
+load net {FRAME:not#16.itm(0)} -attr vt d
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+load net {FRAME:not#16.itm(2)} -attr vt d
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+load net {slc(green#2.sva)#3.itm(0)} -attr vt d
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+load net {slc(green#2.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(green#2.sva)#3.itm} 3 {slc(green#2.sva)#3.itm(0)} {slc(green#2.sva)#3.itm(1)} {slc(green#2.sva)#3.itm(2)} -attr xrf 11720 -attr oid 108 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#3.itm}
+load net {conc#142.itm(0)} -attr vt d
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+load net {conc#142.itm(3)} -attr vt d
+load net {conc#142.itm(4)} -attr vt d
+load netBundle {conc#142.itm} 5 {conc#142.itm(0)} {conc#142.itm(1)} {conc#142.itm(2)} {conc#142.itm(3)} {conc#142.itm(4)} -attr xrf 11721 -attr oid 109 -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {FRAME:mul#3.itm(0)} -attr vt d
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+load net {FRAME:mul#3.itm(11)} -attr vt d
+load netBundle {FRAME:mul#3.itm} 12 {FRAME:mul#3.itm(0)} {FRAME:mul#3.itm(1)} {FRAME:mul#3.itm(2)} {FRAME:mul#3.itm(3)} {FRAME:mul#3.itm(4)} {FRAME:mul#3.itm(5)} {FRAME:mul#3.itm(6)} {FRAME:mul#3.itm(7)} {FRAME:mul#3.itm(8)} {FRAME:mul#3.itm(9)} {FRAME:mul#3.itm(10)} {FRAME:mul#3.itm(11)} -attr xrf 11722 -attr oid 110 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {slc(green#2.sva)#10.itm(0)} -attr vt d
+load net {slc(green#2.sva)#10.itm(1)} -attr vt d
+load net {slc(green#2.sva)#10.itm(2)} -attr vt d
+load netBundle {slc(green#2.sva)#10.itm} 3 {slc(green#2.sva)#10.itm(0)} {slc(green#2.sva)#10.itm(1)} {slc(green#2.sva)#10.itm(2)} -attr xrf 11723 -attr oid 111 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#10.itm}
+load net {mux#5.itm(0)} -attr vt d
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+load net {mux#5.itm(16)} -attr vt d
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+load net {mux#5.itm(18)} -attr vt d
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+load net {FRAME:acc#27.itm(0)} -attr vt d
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+load net {FRAME:acc#27.itm(9)} -attr vt d
+load netBundle {FRAME:acc#27.itm} 10 {FRAME:acc#27.itm(0)} {FRAME:acc#27.itm(1)} {FRAME:acc#27.itm(2)} {FRAME:acc#27.itm(3)} {FRAME:acc#27.itm(4)} {FRAME:acc#27.itm(5)} {FRAME:acc#27.itm(6)} {FRAME:acc#27.itm(7)} {FRAME:acc#27.itm(8)} {FRAME:acc#27.itm(9)} -attr xrf 11725 -attr oid 113 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#26.itm(0)} -attr vt d
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+load net {FRAME:acc#26.itm(7)} -attr vt d
+load netBundle {FRAME:acc#26.itm} 8 {FRAME:acc#26.itm(0)} {FRAME:acc#26.itm(1)} {FRAME:acc#26.itm(2)} {FRAME:acc#26.itm(3)} {FRAME:acc#26.itm(4)} {FRAME:acc#26.itm(5)} {FRAME:acc#26.itm(6)} {FRAME:acc#26.itm(7)} -attr xrf 11726 -attr oid 114 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:for:exs#19.itm(0)} -attr vt d
+load net {FRAME:for:exs#19.itm(1)} -attr vt d
+load netBundle {FRAME:for:exs#19.itm} 2 {FRAME:for:exs#19.itm(0)} {FRAME:for:exs#19.itm(1)} -attr xrf 11727 -attr oid 115 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#19.itm}
+load net {slc(FRAME:p#1.sva#2).itm(0)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(1)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(2)} -attr vt d
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+load net {slc(FRAME:p#1.sva#2).itm(4)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(5)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(6)} -attr vt d
+load netBundle {slc(FRAME:p#1.sva#2).itm} 7 {slc(FRAME:p#1.sva#2).itm(0)} {slc(FRAME:p#1.sva#2).itm(1)} {slc(FRAME:p#1.sva#2).itm(2)} {slc(FRAME:p#1.sva#2).itm(3)} {slc(FRAME:p#1.sva#2).itm(4)} {slc(FRAME:p#1.sva#2).itm(5)} {slc(FRAME:p#1.sva#2).itm(6)} -attr xrf 11728 -attr oid 116 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:for:exs.itm(0)} -attr vt d
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+load net {FRAME:for:exs.itm(2)} -attr vt d
+load net {FRAME:for:exs.itm(3)} -attr vt d
+load net {FRAME:for:exs.itm(4)} -attr vt d
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+load net {FRAME:for:exs.itm(6)} -attr vt d
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+load net {FRAME:for:exs.itm(8)} -attr vt d
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+load net {FRAME:for:exs.itm(10)} -attr vt d
+load net {FRAME:for:exs.itm(11)} -attr vt d
+load net {FRAME:for:exs.itm(12)} -attr vt d
+load net {FRAME:for:exs.itm(13)} -attr vt d
+load net {FRAME:for:exs.itm(14)} -attr vt d
+load net {FRAME:for:exs.itm(15)} -attr vt d
+load net {FRAME:for:exs.itm(16)} -attr vt d
+load net {FRAME:for:exs.itm(17)} -attr vt d
+load net {FRAME:for:exs.itm(18)} -attr vt d
+load netBundle {FRAME:for:exs.itm} 19 {FRAME:for:exs.itm(0)} {FRAME:for:exs.itm(1)} {FRAME:for:exs.itm(2)} {FRAME:for:exs.itm(3)} {FRAME:for:exs.itm(4)} {FRAME:for:exs.itm(5)} {FRAME:for:exs.itm(6)} {FRAME:for:exs.itm(7)} {FRAME:for:exs.itm(8)} {FRAME:for:exs.itm(9)} {FRAME:for:exs.itm(10)} {FRAME:for:exs.itm(11)} {FRAME:for:exs.itm(12)} {FRAME:for:exs.itm(13)} {FRAME:for:exs.itm(14)} {FRAME:for:exs.itm(15)} {FRAME:for:exs.itm(16)} {FRAME:for:exs.itm(17)} {FRAME:for:exs.itm(18)} -attr xrf 11729 -attr oid 117 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {ACC1:conc#49.itm(0)} -attr vt d
+load net {ACC1:conc#49.itm(1)} -attr vt d
+load net {ACC1:conc#49.itm(2)} -attr vt d
+load net {ACC1:conc#49.itm(3)} -attr vt d
+load net {ACC1:conc#49.itm(4)} -attr vt d
+load net {ACC1:conc#49.itm(5)} -attr vt d
+load net {ACC1:conc#49.itm(6)} -attr vt d
+load net {ACC1:conc#49.itm(7)} -attr vt d
+load net {ACC1:conc#49.itm(8)} -attr vt d
+load net {ACC1:conc#49.itm(9)} -attr vt d
+load net {ACC1:conc#49.itm(10)} -attr vt d
+load net {ACC1:conc#49.itm(11)} -attr vt d
+load net {ACC1:conc#49.itm(12)} -attr vt d
+load net {ACC1:conc#49.itm(13)} -attr vt d
+load net {ACC1:conc#49.itm(14)} -attr vt d
+load net {ACC1:conc#49.itm(15)} -attr vt d
+load netBundle {ACC1:conc#49.itm} 16 {ACC1:conc#49.itm(0)} {ACC1:conc#49.itm(1)} {ACC1:conc#49.itm(2)} {ACC1:conc#49.itm(3)} {ACC1:conc#49.itm(4)} {ACC1:conc#49.itm(5)} {ACC1:conc#49.itm(6)} {ACC1:conc#49.itm(7)} {ACC1:conc#49.itm(8)} {ACC1:conc#49.itm(9)} {ACC1:conc#49.itm(10)} {ACC1:conc#49.itm(11)} {ACC1:conc#49.itm(12)} {ACC1:conc#49.itm(13)} {ACC1:conc#49.itm(14)} {ACC1:conc#49.itm(15)} -attr xrf 11730 -attr oid 118 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(0)} -attr vt d
+load net {ACC1:acc#67.itm(1)} -attr vt d
+load net {ACC1:acc#67.itm(2)} -attr vt d
+load net {ACC1:acc#67.itm(3)} -attr vt d
+load net {ACC1:acc#67.itm(4)} -attr vt d
+load net {ACC1:acc#67.itm(5)} -attr vt d
+load net {ACC1:acc#67.itm(6)} -attr vt d
+load net {ACC1:acc#67.itm(7)} -attr vt d
+load net {ACC1:acc#67.itm(8)} -attr vt d
+load net {ACC1:acc#67.itm(9)} -attr vt d
+load net {ACC1:acc#67.itm(10)} -attr vt d
+load net {ACC1:acc#67.itm(11)} -attr vt d
+load net {ACC1:acc#67.itm(12)} -attr vt d
+load net {ACC1:acc#67.itm(13)} -attr vt d
+load net {ACC1:acc#67.itm(14)} -attr vt d
+load netBundle {ACC1:acc#67.itm} 15 {ACC1:acc#67.itm(0)} {ACC1:acc#67.itm(1)} {ACC1:acc#67.itm(2)} {ACC1:acc#67.itm(3)} {ACC1:acc#67.itm(4)} {ACC1:acc#67.itm(5)} {ACC1:acc#67.itm(6)} {ACC1:acc#67.itm(7)} {ACC1:acc#67.itm(8)} {ACC1:acc#67.itm(9)} {ACC1:acc#67.itm(10)} {ACC1:acc#67.itm(11)} {ACC1:acc#67.itm(12)} {ACC1:acc#67.itm(13)} {ACC1:acc#67.itm(14)} -attr xrf 11731 -attr oid 119 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {slc.itm(0)} -attr vt d
+load net {slc.itm(1)} -attr vt d
+load net {slc.itm(2)} -attr vt d
+load net {slc.itm(3)} -attr vt d
+load net {slc.itm(4)} -attr vt d
+load net {slc.itm(5)} -attr vt d
+load net {slc.itm(6)} -attr vt d
+load net {slc.itm(7)} -attr vt d
+load net {slc.itm(8)} -attr vt d
+load net {slc.itm(9)} -attr vt d
+load net {slc.itm(10)} -attr vt d
+load netBundle {slc.itm} 11 {slc.itm(0)} {slc.itm(1)} {slc.itm(2)} {slc.itm(3)} {slc.itm(4)} {slc.itm(5)} {slc.itm(6)} {slc.itm(7)} {slc.itm(8)} {slc.itm(9)} {slc.itm(10)} -attr xrf 11732 -attr oid 120 -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(0)} -attr vt d
+load net {acc.itm(1)} -attr vt d
+load net {acc.itm(2)} -attr vt d
+load net {acc.itm(3)} -attr vt d
+load net {acc.itm(4)} -attr vt d
+load net {acc.itm(5)} -attr vt d
+load net {acc.itm(6)} -attr vt d
+load net {acc.itm(7)} -attr vt d
+load net {acc.itm(8)} -attr vt d
+load net {acc.itm(9)} -attr vt d
+load net {acc.itm(10)} -attr vt d
+load net {acc.itm(11)} -attr vt d
+load netBundle {acc.itm} 12 {acc.itm(0)} {acc.itm(1)} {acc.itm(2)} {acc.itm(3)} {acc.itm(4)} {acc.itm(5)} {acc.itm(6)} {acc.itm(7)} {acc.itm(8)} {acc.itm(9)} {acc.itm(10)} {acc.itm(11)} -attr xrf 11733 -attr oid 121 -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {conc#143.itm(0)} -attr vt d
+load net {conc#143.itm(1)} -attr vt d
+load net {conc#143.itm(2)} -attr vt d
+load net {conc#143.itm(3)} -attr vt d
+load net {conc#143.itm(4)} -attr vt d
+load net {conc#143.itm(5)} -attr vt d
+load net {conc#143.itm(6)} -attr vt d
+load net {conc#143.itm(7)} -attr vt d
+load net {conc#143.itm(8)} -attr vt d
+load net {conc#143.itm(9)} -attr vt d
+load net {conc#143.itm(10)} -attr vt d
+load netBundle {conc#143.itm} 11 {conc#143.itm(0)} {conc#143.itm(1)} {conc#143.itm(2)} {conc#143.itm(3)} {conc#143.itm(4)} {conc#143.itm(5)} {conc#143.itm(6)} {conc#143.itm(7)} {conc#143.itm(8)} {conc#143.itm(9)} {conc#143.itm(10)} -attr xrf 11734 -attr oid 122 -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#19.itm(0)} -attr vt d
+load net {ACC1:not#19.itm(1)} -attr vt d
+load net {ACC1:not#19.itm(2)} -attr vt d
+load net {ACC1:not#19.itm(3)} -attr vt d
+load net {ACC1:not#19.itm(4)} -attr vt d
+load net {ACC1:not#19.itm(5)} -attr vt d
+load net {ACC1:not#19.itm(6)} -attr vt d
+load net {ACC1:not#19.itm(7)} -attr vt d
+load net {ACC1:not#19.itm(8)} -attr vt d
+load net {ACC1:not#19.itm(9)} -attr vt d
+load netBundle {ACC1:not#19.itm} 10 {ACC1:not#19.itm(0)} {ACC1:not#19.itm(1)} {ACC1:not#19.itm(2)} {ACC1:not#19.itm(3)} {ACC1:not#19.itm(4)} {ACC1:not#19.itm(5)} {ACC1:not#19.itm(6)} {ACC1:not#19.itm(7)} {ACC1:not#19.itm(8)} {ACC1:not#19.itm(9)} -attr xrf 11735 -attr oid 123 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#19.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0).itm} 10 {slc(regs.regs(0).sva.dfm:mx0).itm(0)} {slc(regs.regs(0).sva.dfm:mx0).itm(1)} {slc(regs.regs(0).sva.dfm:mx0).itm(2)} {slc(regs.regs(0).sva.dfm:mx0).itm(3)} {slc(regs.regs(0).sva.dfm:mx0).itm(4)} {slc(regs.regs(0).sva.dfm:mx0).itm(5)} {slc(regs.regs(0).sva.dfm:mx0).itm(6)} {slc(regs.regs(0).sva.dfm:mx0).itm(7)} {slc(regs.regs(0).sva.dfm:mx0).itm(8)} {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr xrf 11736 -attr oid 124 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {conc#144.itm(0)} -attr vt d
+load net {conc#144.itm(1)} -attr vt d
+load net {conc#144.itm(2)} -attr vt d
+load net {conc#144.itm(3)} -attr vt d
+load net {conc#144.itm(4)} -attr vt d
+load net {conc#144.itm(5)} -attr vt d
+load net {conc#144.itm(6)} -attr vt d
+load net {conc#144.itm(7)} -attr vt d
+load net {conc#144.itm(8)} -attr vt d
+load net {conc#144.itm(9)} -attr vt d
+load net {conc#144.itm(10)} -attr vt d
+load netBundle {conc#144.itm} 11 {conc#144.itm(0)} {conc#144.itm(1)} {conc#144.itm(2)} {conc#144.itm(3)} {conc#144.itm(4)} {conc#144.itm(5)} {conc#144.itm(6)} {conc#144.itm(7)} {conc#144.itm(8)} {conc#144.itm(9)} {conc#144.itm(10)} -attr xrf 11737 -attr oid 125 -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0).itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0).itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(9)} -attr xrf 11738 -attr oid 126 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {slc(b(2).sva#1).itm(0)} -attr vt d
+load net {slc(b(2).sva#1).itm(1)} -attr vt d
+load net {slc(b(2).sva#1).itm(2)} -attr vt d
+load net {slc(b(2).sva#1).itm(3)} -attr vt d
+load net {slc(b(2).sva#1).itm(4)} -attr vt d
+load net {slc(b(2).sva#1).itm(5)} -attr vt d
+load net {slc(b(2).sva#1).itm(6)} -attr vt d
+load net {slc(b(2).sva#1).itm(7)} -attr vt d
+load net {slc(b(2).sva#1).itm(8)} -attr vt d
+load net {slc(b(2).sva#1).itm(9)} -attr vt d
+load net {slc(b(2).sva#1).itm(10)} -attr vt d
+load net {slc(b(2).sva#1).itm(11)} -attr vt d
+load net {slc(b(2).sva#1).itm(12)} -attr vt d
+load net {slc(b(2).sva#1).itm(13)} -attr vt d
+load net {slc(b(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(b(2).sva#1).itm} 15 {slc(b(2).sva#1).itm(0)} {slc(b(2).sva#1).itm(1)} {slc(b(2).sva#1).itm(2)} {slc(b(2).sva#1).itm(3)} {slc(b(2).sva#1).itm(4)} {slc(b(2).sva#1).itm(5)} {slc(b(2).sva#1).itm(6)} {slc(b(2).sva#1).itm(7)} {slc(b(2).sva#1).itm(8)} {slc(b(2).sva#1).itm(9)} {slc(b(2).sva#1).itm(10)} {slc(b(2).sva#1).itm(11)} {slc(b(2).sva#1).itm(12)} {slc(b(2).sva#1).itm(13)} {slc(b(2).sva#1).itm(14)} -attr xrf 11739 -attr oid 127 -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {conc#145.itm(0)} -attr vt d
+load net {conc#145.itm(1)} -attr vt d
+load netBundle {conc#145.itm} 2 {conc#145.itm(0)} {conc#145.itm(1)} -attr xrf 11740 -attr oid 128 -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {conc#146.itm(0)} -attr vt d
+load net {conc#146.itm(1)} -attr vt d
+load net {conc#146.itm(2)} -attr vt d
+load net {conc#146.itm(3)} -attr vt d
+load net {conc#146.itm(4)} -attr vt d
+load net {conc#146.itm(5)} -attr vt d
+load netBundle {conc#146.itm} 6 {conc#146.itm(0)} {conc#146.itm(1)} {conc#146.itm(2)} {conc#146.itm(3)} {conc#146.itm(4)} {conc#146.itm(5)} -attr xrf 11741 -attr oid 129 -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {FRAME:acc#45.itm(0)} -attr vt d
+load net {FRAME:acc#45.itm(1)} -attr vt d
+load net {FRAME:acc#45.itm(2)} -attr vt d
+load net {FRAME:acc#45.itm(3)} -attr vt d
+load netBundle {FRAME:acc#45.itm} 4 {FRAME:acc#45.itm(0)} {FRAME:acc#45.itm(1)} {FRAME:acc#45.itm(2)} {FRAME:acc#45.itm(3)} -attr xrf 11742 -attr oid 130 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#45.itm}
+load net {slc(FRAME:acc#28.sdt).itm(0)} -attr vt d
+load net {slc(FRAME:acc#28.sdt).itm(1)} -attr vt d
+load net {slc(FRAME:acc#28.sdt).itm(2)} -attr vt d
+load net {slc(FRAME:acc#28.sdt).itm(3)} -attr vt d
+load netBundle {slc(FRAME:acc#28.sdt).itm} 4 {slc(FRAME:acc#28.sdt).itm(0)} {slc(FRAME:acc#28.sdt).itm(1)} {slc(FRAME:acc#28.sdt).itm(2)} {slc(FRAME:acc#28.sdt).itm(3)} -attr xrf 11743 -attr oid 131 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#28.sdt).itm}
+load net {FRAME:acc#30.itm(0)} -attr vt d
+load net {FRAME:acc#30.itm(1)} -attr vt d
+load net {FRAME:acc#30.itm(2)} -attr vt d
+load net {FRAME:acc#30.itm(3)} -attr vt d
+load net {FRAME:acc#30.itm(4)} -attr vt d
+load netBundle {FRAME:acc#30.itm} 5 {FRAME:acc#30.itm(0)} {FRAME:acc#30.itm(1)} {FRAME:acc#30.itm(2)} {FRAME:acc#30.itm(3)} {FRAME:acc#30.itm(4)} -attr xrf 11744 -attr oid 132 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#29.itm(0)} -attr vt d
+load net {FRAME:acc#29.itm(1)} -attr vt d
+load net {FRAME:acc#29.itm(2)} -attr vt d
+load net {FRAME:acc#29.itm(3)} -attr vt d
+load netBundle {FRAME:acc#29.itm} 4 {FRAME:acc#29.itm(0)} {FRAME:acc#29.itm(1)} {FRAME:acc#29.itm(2)} {FRAME:acc#29.itm(3)} -attr xrf 11745 -attr oid 133 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:not#19.itm(0)} -attr vt d
+load net {FRAME:not#19.itm(1)} -attr vt d
+load net {FRAME:not#19.itm(2)} -attr vt d
+load netBundle {FRAME:not#19.itm} 3 {FRAME:not#19.itm(0)} {FRAME:not#19.itm(1)} {FRAME:not#19.itm(2)} -attr xrf 11746 -attr oid 134 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#19.itm}
+load net {slc(blue#2.sva)#6.itm(0)} -attr vt d
+load net {slc(blue#2.sva)#6.itm(1)} -attr vt d
+load net {slc(blue#2.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sva)#6.itm} 3 {slc(blue#2.sva)#6.itm(0)} {slc(blue#2.sva)#6.itm(1)} {slc(blue#2.sva)#6.itm(2)} -attr xrf 11747 -attr oid 135 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#6.itm}
+load net {slc(blue#2.sva)#7.itm(0)} -attr vt d
+load net {slc(blue#2.sva)#7.itm(1)} -attr vt d
+load net {slc(blue#2.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sva)#7.itm} 3 {slc(blue#2.sva)#7.itm(0)} {slc(blue#2.sva)#7.itm(1)} {slc(blue#2.sva)#7.itm(2)} -attr xrf 11748 -attr oid 136 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#7.itm}
+load net {slc(blue#2.sva)#8.itm(0)} -attr vt d
+load net {slc(blue#2.sva)#8.itm(1)} -attr vt d
+load net {slc(blue#2.sva)#8.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sva)#8.itm} 3 {slc(blue#2.sva)#8.itm(0)} {slc(blue#2.sva)#8.itm(1)} {slc(blue#2.sva)#8.itm(2)} -attr xrf 11749 -attr oid 137 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#8.itm}
+load net {FRAME:acc#32.itm(0)} -attr vt d
+load net {FRAME:acc#32.itm(1)} -attr vt d
+load net {FRAME:acc#32.itm(2)} -attr vt d
+load net {FRAME:acc#32.itm(3)} -attr vt d
+load net {FRAME:acc#32.itm(4)} -attr vt d
+load netBundle {FRAME:acc#32.itm} 5 {FRAME:acc#32.itm(0)} {FRAME:acc#32.itm(1)} {FRAME:acc#32.itm(2)} {FRAME:acc#32.itm(3)} {FRAME:acc#32.itm(4)} -attr xrf 11750 -attr oid 138 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {conc#148.itm(0)} -attr vt d
+load net {conc#148.itm(1)} -attr vt d
+load net {conc#148.itm(2)} -attr vt d
+load net {conc#148.itm(3)} -attr vt d
+load net {conc#148.itm(4)} -attr vt d
+load netBundle {conc#148.itm} 5 {conc#148.itm(0)} {conc#148.itm(1)} {conc#148.itm(2)} {conc#148.itm(3)} {conc#148.itm(4)} -attr xrf 11751 -attr oid 139 -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {slc(FRAME:acc#11.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#11.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#11.psp.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(FRAME:acc#11.psp.sva)#2.itm} 3 {slc(FRAME:acc#11.psp.sva)#2.itm(0)} {slc(FRAME:acc#11.psp.sva)#2.itm(1)} {slc(FRAME:acc#11.psp.sva)#2.itm(2)} -attr xrf 11752 -attr oid 140 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#11.psp.sva)#2.itm}
+load net {FRAME:conc#76.itm(0)} -attr vt d
+load net {FRAME:conc#76.itm(1)} -attr vt d
+load net {FRAME:conc#76.itm(2)} -attr vt d
+load net {FRAME:conc#76.itm(3)} -attr vt d
+load netBundle {FRAME:conc#76.itm} 4 {FRAME:conc#76.itm(0)} {FRAME:conc#76.itm(1)} {FRAME:conc#76.itm(2)} {FRAME:conc#76.itm(3)} -attr xrf 11753 -attr oid 141 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#76.itm}
+load net {FRAME:not#22.itm(0)} -attr vt d
+load net {FRAME:not#22.itm(1)} -attr vt d
+load net {FRAME:not#22.itm(2)} -attr vt d
+load netBundle {FRAME:not#22.itm} 3 {FRAME:not#22.itm(0)} {FRAME:not#22.itm(1)} {FRAME:not#22.itm(2)} -attr xrf 11754 -attr oid 142 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {slc(FRAME:acc#11.psp.sva)#3.itm(0)} -attr vt d
+load net {slc(FRAME:acc#11.psp.sva)#3.itm(1)} -attr vt d
+load net {slc(FRAME:acc#11.psp.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(FRAME:acc#11.psp.sva)#3.itm} 3 {slc(FRAME:acc#11.psp.sva)#3.itm(0)} {slc(FRAME:acc#11.psp.sva)#3.itm(1)} {slc(FRAME:acc#11.psp.sva)#3.itm(2)} -attr xrf 11755 -attr oid 143 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#11.psp.sva)#3.itm}
+load net {ACC1:conc#45.itm(0)} -attr vt d
+load net {ACC1:conc#45.itm(1)} -attr vt d
+load net {ACC1:conc#45.itm(2)} -attr vt d
+load net {ACC1:conc#45.itm(3)} -attr vt d
+load net {ACC1:conc#45.itm(4)} -attr vt d
+load net {ACC1:conc#45.itm(5)} -attr vt d
+load net {ACC1:conc#45.itm(6)} -attr vt d
+load net {ACC1:conc#45.itm(7)} -attr vt d
+load net {ACC1:conc#45.itm(8)} -attr vt d
+load net {ACC1:conc#45.itm(9)} -attr vt d
+load net {ACC1:conc#45.itm(10)} -attr vt d
+load net {ACC1:conc#45.itm(11)} -attr vt d
+load net {ACC1:conc#45.itm(12)} -attr vt d
+load net {ACC1:conc#45.itm(13)} -attr vt d
+load net {ACC1:conc#45.itm(14)} -attr vt d
+load net {ACC1:conc#45.itm(15)} -attr vt d
+load netBundle {ACC1:conc#45.itm} 16 {ACC1:conc#45.itm(0)} {ACC1:conc#45.itm(1)} {ACC1:conc#45.itm(2)} {ACC1:conc#45.itm(3)} {ACC1:conc#45.itm(4)} {ACC1:conc#45.itm(5)} {ACC1:conc#45.itm(6)} {ACC1:conc#45.itm(7)} {ACC1:conc#45.itm(8)} {ACC1:conc#45.itm(9)} {ACC1:conc#45.itm(10)} {ACC1:conc#45.itm(11)} {ACC1:conc#45.itm(12)} {ACC1:conc#45.itm(13)} {ACC1:conc#45.itm(14)} {ACC1:conc#45.itm(15)} -attr xrf 11756 -attr oid 144 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(0)} -attr vt d
+load net {ACC1:acc#59.itm(1)} -attr vt d
+load net {ACC1:acc#59.itm(2)} -attr vt d
+load net {ACC1:acc#59.itm(3)} -attr vt d
+load net {ACC1:acc#59.itm(4)} -attr vt d
+load net {ACC1:acc#59.itm(5)} -attr vt d
+load net {ACC1:acc#59.itm(6)} -attr vt d
+load net {ACC1:acc#59.itm(7)} -attr vt d
+load net {ACC1:acc#59.itm(8)} -attr vt d
+load net {ACC1:acc#59.itm(9)} -attr vt d
+load net {ACC1:acc#59.itm(10)} -attr vt d
+load net {ACC1:acc#59.itm(11)} -attr vt d
+load net {ACC1:acc#59.itm(12)} -attr vt d
+load net {ACC1:acc#59.itm(13)} -attr vt d
+load net {ACC1:acc#59.itm(14)} -attr vt d
+load netBundle {ACC1:acc#59.itm} 15 {ACC1:acc#59.itm(0)} {ACC1:acc#59.itm(1)} {ACC1:acc#59.itm(2)} {ACC1:acc#59.itm(3)} {ACC1:acc#59.itm(4)} {ACC1:acc#59.itm(5)} {ACC1:acc#59.itm(6)} {ACC1:acc#59.itm(7)} {ACC1:acc#59.itm(8)} {ACC1:acc#59.itm(9)} {ACC1:acc#59.itm(10)} {ACC1:acc#59.itm(11)} {ACC1:acc#59.itm(12)} {ACC1:acc#59.itm(13)} {ACC1:acc#59.itm(14)} -attr xrf 11757 -attr oid 145 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {slc#1.itm(0)} -attr vt d
+load net {slc#1.itm(1)} -attr vt d
+load net {slc#1.itm(2)} -attr vt d
+load net {slc#1.itm(3)} -attr vt d
+load net {slc#1.itm(4)} -attr vt d
+load net {slc#1.itm(5)} -attr vt d
+load net {slc#1.itm(6)} -attr vt d
+load net {slc#1.itm(7)} -attr vt d
+load net {slc#1.itm(8)} -attr vt d
+load net {slc#1.itm(9)} -attr vt d
+load net {slc#1.itm(10)} -attr vt d
+load netBundle {slc#1.itm} 11 {slc#1.itm(0)} {slc#1.itm(1)} {slc#1.itm(2)} {slc#1.itm(3)} {slc#1.itm(4)} {slc#1.itm(5)} {slc#1.itm(6)} {slc#1.itm(7)} {slc#1.itm(8)} {slc#1.itm(9)} {slc#1.itm(10)} -attr xrf 11758 -attr oid 146 -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#1.itm(0)} -attr vt d
+load net {acc#1.itm(1)} -attr vt d
+load net {acc#1.itm(2)} -attr vt d
+load net {acc#1.itm(3)} -attr vt d
+load net {acc#1.itm(4)} -attr vt d
+load net {acc#1.itm(5)} -attr vt d
+load net {acc#1.itm(6)} -attr vt d
+load net {acc#1.itm(7)} -attr vt d
+load net {acc#1.itm(8)} -attr vt d
+load net {acc#1.itm(9)} -attr vt d
+load net {acc#1.itm(10)} -attr vt d
+load net {acc#1.itm(11)} -attr vt d
+load netBundle {acc#1.itm} 12 {acc#1.itm(0)} {acc#1.itm(1)} {acc#1.itm(2)} {acc#1.itm(3)} {acc#1.itm(4)} {acc#1.itm(5)} {acc#1.itm(6)} {acc#1.itm(7)} {acc#1.itm(8)} {acc#1.itm(9)} {acc#1.itm(10)} {acc#1.itm(11)} -attr xrf 11759 -attr oid 147 -attr vt d -attr @path {/sobel/sobel:core/acc#1.itm}
+load net {conc#149.itm(0)} -attr vt d
+load net {conc#149.itm(1)} -attr vt d
+load net {conc#149.itm(2)} -attr vt d
+load net {conc#149.itm(3)} -attr vt d
+load net {conc#149.itm(4)} -attr vt d
+load net {conc#149.itm(5)} -attr vt d
+load net {conc#149.itm(6)} -attr vt d
+load net {conc#149.itm(7)} -attr vt d
+load net {conc#149.itm(8)} -attr vt d
+load net {conc#149.itm(9)} -attr vt d
+load net {conc#149.itm(10)} -attr vt d
+load netBundle {conc#149.itm} 11 {conc#149.itm(0)} {conc#149.itm(1)} {conc#149.itm(2)} {conc#149.itm(3)} {conc#149.itm(4)} {conc#149.itm(5)} {conc#149.itm(6)} {conc#149.itm(7)} {conc#149.itm(8)} {conc#149.itm(9)} {conc#149.itm(10)} -attr xrf 11760 -attr oid 148 -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {ACC1:not#17.itm(0)} -attr vt d
+load net {ACC1:not#17.itm(1)} -attr vt d
+load net {ACC1:not#17.itm(2)} -attr vt d
+load net {ACC1:not#17.itm(3)} -attr vt d
+load net {ACC1:not#17.itm(4)} -attr vt d
+load net {ACC1:not#17.itm(5)} -attr vt d
+load net {ACC1:not#17.itm(6)} -attr vt d
+load net {ACC1:not#17.itm(7)} -attr vt d
+load net {ACC1:not#17.itm(8)} -attr vt d
+load net {ACC1:not#17.itm(9)} -attr vt d
+load netBundle {ACC1:not#17.itm} 10 {ACC1:not#17.itm(0)} {ACC1:not#17.itm(1)} {ACC1:not#17.itm(2)} {ACC1:not#17.itm(3)} {ACC1:not#17.itm(4)} {ACC1:not#17.itm(5)} {ACC1:not#17.itm(6)} {ACC1:not#17.itm(7)} {ACC1:not#17.itm(8)} {ACC1:not#17.itm(9)} -attr xrf 11761 -attr oid 149 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#17.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr xrf 11762 -attr oid 150 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {conc#150.itm(0)} -attr vt d
+load net {conc#150.itm(1)} -attr vt d
+load net {conc#150.itm(2)} -attr vt d
+load net {conc#150.itm(3)} -attr vt d
+load net {conc#150.itm(4)} -attr vt d
+load net {conc#150.itm(5)} -attr vt d
+load net {conc#150.itm(6)} -attr vt d
+load net {conc#150.itm(7)} -attr vt d
+load net {conc#150.itm(8)} -attr vt d
+load net {conc#150.itm(9)} -attr vt d
+load net {conc#150.itm(10)} -attr vt d
+load netBundle {conc#150.itm} 11 {conc#150.itm(0)} {conc#150.itm(1)} {conc#150.itm(2)} {conc#150.itm(3)} {conc#150.itm(4)} {conc#150.itm(5)} {conc#150.itm(6)} {conc#150.itm(7)} {conc#150.itm(8)} {conc#150.itm(9)} {conc#150.itm(10)} -attr xrf 11763 -attr oid 151 -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(9)} -attr xrf 11764 -attr oid 152 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {slc(r(2).sva#1).itm(0)} -attr vt d
+load net {slc(r(2).sva#1).itm(1)} -attr vt d
+load net {slc(r(2).sva#1).itm(2)} -attr vt d
+load net {slc(r(2).sva#1).itm(3)} -attr vt d
+load net {slc(r(2).sva#1).itm(4)} -attr vt d
+load net {slc(r(2).sva#1).itm(5)} -attr vt d
+load net {slc(r(2).sva#1).itm(6)} -attr vt d
+load net {slc(r(2).sva#1).itm(7)} -attr vt d
+load net {slc(r(2).sva#1).itm(8)} -attr vt d
+load net {slc(r(2).sva#1).itm(9)} -attr vt d
+load net {slc(r(2).sva#1).itm(10)} -attr vt d
+load net {slc(r(2).sva#1).itm(11)} -attr vt d
+load net {slc(r(2).sva#1).itm(12)} -attr vt d
+load net {slc(r(2).sva#1).itm(13)} -attr vt d
+load net {slc(r(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(r(2).sva#1).itm} 15 {slc(r(2).sva#1).itm(0)} {slc(r(2).sva#1).itm(1)} {slc(r(2).sva#1).itm(2)} {slc(r(2).sva#1).itm(3)} {slc(r(2).sva#1).itm(4)} {slc(r(2).sva#1).itm(5)} {slc(r(2).sva#1).itm(6)} {slc(r(2).sva#1).itm(7)} {slc(r(2).sva#1).itm(8)} {slc(r(2).sva#1).itm(9)} {slc(r(2).sva#1).itm(10)} {slc(r(2).sva#1).itm(11)} {slc(r(2).sva#1).itm(12)} {slc(r(2).sva#1).itm(13)} {slc(r(2).sva#1).itm(14)} -attr xrf 11765 -attr oid 153 -attr vt d -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {conc#151.itm(0)} -attr vt d
+load net {conc#151.itm(1)} -attr vt d
+load netBundle {conc#151.itm} 2 {conc#151.itm(0)} {conc#151.itm(1)} -attr xrf 11766 -attr oid 154 -attr vt d -attr @path {/sobel/sobel:core/conc#151.itm}
+load net {conc#152.itm(0)} -attr vt d
+load net {conc#152.itm(1)} -attr vt d
+load net {conc#152.itm(2)} -attr vt d
+load net {conc#152.itm(3)} -attr vt d
+load net {conc#152.itm(4)} -attr vt d
+load net {conc#152.itm(5)} -attr vt d
+load netBundle {conc#152.itm} 6 {conc#152.itm(0)} {conc#152.itm(1)} {conc#152.itm(2)} {conc#152.itm(3)} {conc#152.itm(4)} {conc#152.itm(5)} -attr xrf 11767 -attr oid 155 -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {FRAME:acc#43.itm(0)} -attr vt d
+load net {FRAME:acc#43.itm(1)} -attr vt d
+load net {FRAME:acc#43.itm(2)} -attr vt d
+load net {FRAME:acc#43.itm(3)} -attr vt d
+load netBundle {FRAME:acc#43.itm} 4 {FRAME:acc#43.itm(0)} {FRAME:acc#43.itm(1)} {FRAME:acc#43.itm(2)} {FRAME:acc#43.itm(3)} -attr xrf 11768 -attr oid 156 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {slc(FRAME:acc#13.sdt).itm(0)} -attr vt d
+load net {slc(FRAME:acc#13.sdt).itm(1)} -attr vt d
+load net {slc(FRAME:acc#13.sdt).itm(2)} -attr vt d
+load net {slc(FRAME:acc#13.sdt).itm(3)} -attr vt d
+load netBundle {slc(FRAME:acc#13.sdt).itm} 4 {slc(FRAME:acc#13.sdt).itm(0)} {slc(FRAME:acc#13.sdt).itm(1)} {slc(FRAME:acc#13.sdt).itm(2)} {slc(FRAME:acc#13.sdt).itm(3)} -attr xrf 11769 -attr oid 157 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#13.sdt).itm}
+load net {FRAME:acc#15.itm(0)} -attr vt d
+load net {FRAME:acc#15.itm(1)} -attr vt d
+load net {FRAME:acc#15.itm(2)} -attr vt d
+load net {FRAME:acc#15.itm(3)} -attr vt d
+load net {FRAME:acc#15.itm(4)} -attr vt d
+load netBundle {FRAME:acc#15.itm} 5 {FRAME:acc#15.itm(0)} {FRAME:acc#15.itm(1)} {FRAME:acc#15.itm(2)} {FRAME:acc#15.itm(3)} {FRAME:acc#15.itm(4)} -attr xrf 11770 -attr oid 158 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#14.itm(0)} -attr vt d
+load net {FRAME:acc#14.itm(1)} -attr vt d
+load net {FRAME:acc#14.itm(2)} -attr vt d
+load net {FRAME:acc#14.itm(3)} -attr vt d
+load netBundle {FRAME:acc#14.itm} 4 {FRAME:acc#14.itm(0)} {FRAME:acc#14.itm(1)} {FRAME:acc#14.itm(2)} {FRAME:acc#14.itm(3)} -attr xrf 11771 -attr oid 159 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:not#1.itm(0)} -attr vt d
+load net {FRAME:not#1.itm(1)} -attr vt d
+load net {FRAME:not#1.itm(2)} -attr vt d
+load netBundle {FRAME:not#1.itm} 3 {FRAME:not#1.itm(0)} {FRAME:not#1.itm(1)} {FRAME:not#1.itm(2)} -attr xrf 11772 -attr oid 160 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {slc(red#2.sva)#6.itm(0)} -attr vt d
+load net {slc(red#2.sva)#6.itm(1)} -attr vt d
+load net {slc(red#2.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(red#2.sva)#6.itm} 3 {slc(red#2.sva)#6.itm(0)} {slc(red#2.sva)#6.itm(1)} {slc(red#2.sva)#6.itm(2)} -attr xrf 11773 -attr oid 161 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#6.itm}
+load net {slc(red#2.sva)#7.itm(0)} -attr vt d
+load net {slc(red#2.sva)#7.itm(1)} -attr vt d
+load net {slc(red#2.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(red#2.sva)#7.itm} 3 {slc(red#2.sva)#7.itm(0)} {slc(red#2.sva)#7.itm(1)} {slc(red#2.sva)#7.itm(2)} -attr xrf 11774 -attr oid 162 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#7.itm}
+load net {slc(red#2.sva)#8.itm(0)} -attr vt d
+load net {slc(red#2.sva)#8.itm(1)} -attr vt d
+load net {slc(red#2.sva)#8.itm(2)} -attr vt d
+load netBundle {slc(red#2.sva)#8.itm} 3 {slc(red#2.sva)#8.itm(0)} {slc(red#2.sva)#8.itm(1)} {slc(red#2.sva)#8.itm(2)} -attr xrf 11775 -attr oid 163 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#8.itm}
+load net {FRAME:acc#17.itm(0)} -attr vt d
+load net {FRAME:acc#17.itm(1)} -attr vt d
+load net {FRAME:acc#17.itm(2)} -attr vt d
+load net {FRAME:acc#17.itm(3)} -attr vt d
+load net {FRAME:acc#17.itm(4)} -attr vt d
+load netBundle {FRAME:acc#17.itm} 5 {FRAME:acc#17.itm(0)} {FRAME:acc#17.itm(1)} {FRAME:acc#17.itm(2)} {FRAME:acc#17.itm(3)} {FRAME:acc#17.itm(4)} -attr xrf 11776 -attr oid 164 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {conc#154.itm(0)} -attr vt d
+load net {conc#154.itm(1)} -attr vt d
+load net {conc#154.itm(2)} -attr vt d
+load net {conc#154.itm(3)} -attr vt d
+load net {conc#154.itm(4)} -attr vt d
+load netBundle {conc#154.itm} 5 {conc#154.itm(0)} {conc#154.itm(1)} {conc#154.itm(2)} {conc#154.itm(3)} {conc#154.itm(4)} -attr xrf 11777 -attr oid 165 -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {slc(FRAME:acc#7.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#7.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#7.psp.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(FRAME:acc#7.psp.sva)#2.itm} 3 {slc(FRAME:acc#7.psp.sva)#2.itm(0)} {slc(FRAME:acc#7.psp.sva)#2.itm(1)} {slc(FRAME:acc#7.psp.sva)#2.itm(2)} -attr xrf 11778 -attr oid 166 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#7.psp.sva)#2.itm}
+load net {FRAME:conc#67.itm(0)} -attr vt d
+load net {FRAME:conc#67.itm(1)} -attr vt d
+load net {FRAME:conc#67.itm(2)} -attr vt d
+load net {FRAME:conc#67.itm(3)} -attr vt d
+load netBundle {FRAME:conc#67.itm} 4 {FRAME:conc#67.itm(0)} {FRAME:conc#67.itm(1)} {FRAME:conc#67.itm(2)} {FRAME:conc#67.itm(3)} -attr xrf 11779 -attr oid 167 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#67.itm}
+load net {FRAME:not#4.itm(0)} -attr vt d
+load net {FRAME:not#4.itm(1)} -attr vt d
+load net {FRAME:not#4.itm(2)} -attr vt d
+load netBundle {FRAME:not#4.itm} 3 {FRAME:not#4.itm(0)} {FRAME:not#4.itm(1)} {FRAME:not#4.itm(2)} -attr xrf 11780 -attr oid 168 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#4.itm}
+load net {slc(FRAME:acc#7.psp.sva)#3.itm(0)} -attr vt d
+load net {slc(FRAME:acc#7.psp.sva)#3.itm(1)} -attr vt d
+load net {slc(FRAME:acc#7.psp.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(FRAME:acc#7.psp.sva)#3.itm} 3 {slc(FRAME:acc#7.psp.sva)#3.itm(0)} {slc(FRAME:acc#7.psp.sva)#3.itm(1)} {slc(FRAME:acc#7.psp.sva)#3.itm(2)} -attr xrf 11781 -attr oid 169 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#7.psp.sva)#3.itm}
+load net {FRAME:not#20.itm(0)} -attr vt d
+load net {FRAME:not#20.itm(1)} -attr vt d
+load net {FRAME:not#20.itm(2)} -attr vt d
+load netBundle {FRAME:not#20.itm} 3 {FRAME:not#20.itm(0)} {FRAME:not#20.itm(1)} {FRAME:not#20.itm(2)} -attr xrf 11782 -attr oid 170 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load net {slc(blue#2.sva)#9.itm(0)} -attr vt d
+load net {slc(blue#2.sva)#9.itm(1)} -attr vt d
+load net {slc(blue#2.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sva)#9.itm} 3 {slc(blue#2.sva)#9.itm(0)} {slc(blue#2.sva)#9.itm(1)} {slc(blue#2.sva)#9.itm(2)} -attr xrf 11783 -attr oid 171 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#9.itm}
+load net {slc(blue#2.sva).itm(0)} -attr vt d
+load net {slc(blue#2.sva).itm(1)} -attr vt d
+load net {slc(blue#2.sva).itm(2)} -attr vt d
+load netBundle {slc(blue#2.sva).itm} 3 {slc(blue#2.sva).itm(0)} {slc(blue#2.sva).itm(1)} {slc(blue#2.sva).itm(2)} -attr xrf 11784 -attr oid 172 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva).itm}
+load net {ACC1:conc#47.itm(0)} -attr vt d
+load net {ACC1:conc#47.itm(1)} -attr vt d
+load net {ACC1:conc#47.itm(2)} -attr vt d
+load net {ACC1:conc#47.itm(3)} -attr vt d
+load net {ACC1:conc#47.itm(4)} -attr vt d
+load net {ACC1:conc#47.itm(5)} -attr vt d
+load net {ACC1:conc#47.itm(6)} -attr vt d
+load net {ACC1:conc#47.itm(7)} -attr vt d
+load net {ACC1:conc#47.itm(8)} -attr vt d
+load net {ACC1:conc#47.itm(9)} -attr vt d
+load net {ACC1:conc#47.itm(10)} -attr vt d
+load net {ACC1:conc#47.itm(11)} -attr vt d
+load net {ACC1:conc#47.itm(12)} -attr vt d
+load net {ACC1:conc#47.itm(13)} -attr vt d
+load net {ACC1:conc#47.itm(14)} -attr vt d
+load net {ACC1:conc#47.itm(15)} -attr vt d
+load netBundle {ACC1:conc#47.itm} 16 {ACC1:conc#47.itm(0)} {ACC1:conc#47.itm(1)} {ACC1:conc#47.itm(2)} {ACC1:conc#47.itm(3)} {ACC1:conc#47.itm(4)} {ACC1:conc#47.itm(5)} {ACC1:conc#47.itm(6)} {ACC1:conc#47.itm(7)} {ACC1:conc#47.itm(8)} {ACC1:conc#47.itm(9)} {ACC1:conc#47.itm(10)} {ACC1:conc#47.itm(11)} {ACC1:conc#47.itm(12)} {ACC1:conc#47.itm(13)} {ACC1:conc#47.itm(14)} {ACC1:conc#47.itm(15)} -attr xrf 11785 -attr oid 173 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(0)} -attr vt d
+load net {ACC1:acc#63.itm(1)} -attr vt d
+load net {ACC1:acc#63.itm(2)} -attr vt d
+load net {ACC1:acc#63.itm(3)} -attr vt d
+load net {ACC1:acc#63.itm(4)} -attr vt d
+load net {ACC1:acc#63.itm(5)} -attr vt d
+load net {ACC1:acc#63.itm(6)} -attr vt d
+load net {ACC1:acc#63.itm(7)} -attr vt d
+load net {ACC1:acc#63.itm(8)} -attr vt d
+load net {ACC1:acc#63.itm(9)} -attr vt d
+load net {ACC1:acc#63.itm(10)} -attr vt d
+load net {ACC1:acc#63.itm(11)} -attr vt d
+load net {ACC1:acc#63.itm(12)} -attr vt d
+load net {ACC1:acc#63.itm(13)} -attr vt d
+load net {ACC1:acc#63.itm(14)} -attr vt d
+load netBundle {ACC1:acc#63.itm} 15 {ACC1:acc#63.itm(0)} {ACC1:acc#63.itm(1)} {ACC1:acc#63.itm(2)} {ACC1:acc#63.itm(3)} {ACC1:acc#63.itm(4)} {ACC1:acc#63.itm(5)} {ACC1:acc#63.itm(6)} {ACC1:acc#63.itm(7)} {ACC1:acc#63.itm(8)} {ACC1:acc#63.itm(9)} {ACC1:acc#63.itm(10)} {ACC1:acc#63.itm(11)} {ACC1:acc#63.itm(12)} {ACC1:acc#63.itm(13)} {ACC1:acc#63.itm(14)} -attr xrf 11786 -attr oid 174 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {slc#2.itm(0)} -attr vt d
+load net {slc#2.itm(1)} -attr vt d
+load net {slc#2.itm(2)} -attr vt d
+load net {slc#2.itm(3)} -attr vt d
+load net {slc#2.itm(4)} -attr vt d
+load net {slc#2.itm(5)} -attr vt d
+load net {slc#2.itm(6)} -attr vt d
+load net {slc#2.itm(7)} -attr vt d
+load net {slc#2.itm(8)} -attr vt d
+load net {slc#2.itm(9)} -attr vt d
+load net {slc#2.itm(10)} -attr vt d
+load netBundle {slc#2.itm} 11 {slc#2.itm(0)} {slc#2.itm(1)} {slc#2.itm(2)} {slc#2.itm(3)} {slc#2.itm(4)} {slc#2.itm(5)} {slc#2.itm(6)} {slc#2.itm(7)} {slc#2.itm(8)} {slc#2.itm(9)} {slc#2.itm(10)} -attr xrf 11787 -attr oid 175 -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#2.itm(0)} -attr vt d
+load net {acc#2.itm(1)} -attr vt d
+load net {acc#2.itm(2)} -attr vt d
+load net {acc#2.itm(3)} -attr vt d
+load net {acc#2.itm(4)} -attr vt d
+load net {acc#2.itm(5)} -attr vt d
+load net {acc#2.itm(6)} -attr vt d
+load net {acc#2.itm(7)} -attr vt d
+load net {acc#2.itm(8)} -attr vt d
+load net {acc#2.itm(9)} -attr vt d
+load net {acc#2.itm(10)} -attr vt d
+load net {acc#2.itm(11)} -attr vt d
+load netBundle {acc#2.itm} 12 {acc#2.itm(0)} {acc#2.itm(1)} {acc#2.itm(2)} {acc#2.itm(3)} {acc#2.itm(4)} {acc#2.itm(5)} {acc#2.itm(6)} {acc#2.itm(7)} {acc#2.itm(8)} {acc#2.itm(9)} {acc#2.itm(10)} {acc#2.itm(11)} -attr xrf 11788 -attr oid 176 -attr vt d -attr @path {/sobel/sobel:core/acc#2.itm}
+load net {conc#155.itm(0)} -attr vt d
+load net {conc#155.itm(1)} -attr vt d
+load net {conc#155.itm(2)} -attr vt d
+load net {conc#155.itm(3)} -attr vt d
+load net {conc#155.itm(4)} -attr vt d
+load net {conc#155.itm(5)} -attr vt d
+load net {conc#155.itm(6)} -attr vt d
+load net {conc#155.itm(7)} -attr vt d
+load net {conc#155.itm(8)} -attr vt d
+load net {conc#155.itm(9)} -attr vt d
+load net {conc#155.itm(10)} -attr vt d
+load netBundle {conc#155.itm} 11 {conc#155.itm(0)} {conc#155.itm(1)} {conc#155.itm(2)} {conc#155.itm(3)} {conc#155.itm(4)} {conc#155.itm(5)} {conc#155.itm(6)} {conc#155.itm(7)} {conc#155.itm(8)} {conc#155.itm(9)} {conc#155.itm(10)} -attr xrf 11789 -attr oid 177 -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC1:not#18.itm(0)} -attr vt d
+load net {ACC1:not#18.itm(1)} -attr vt d
+load net {ACC1:not#18.itm(2)} -attr vt d
+load net {ACC1:not#18.itm(3)} -attr vt d
+load net {ACC1:not#18.itm(4)} -attr vt d
+load net {ACC1:not#18.itm(5)} -attr vt d
+load net {ACC1:not#18.itm(6)} -attr vt d
+load net {ACC1:not#18.itm(7)} -attr vt d
+load net {ACC1:not#18.itm(8)} -attr vt d
+load net {ACC1:not#18.itm(9)} -attr vt d
+load netBundle {ACC1:not#18.itm} 10 {ACC1:not#18.itm(0)} {ACC1:not#18.itm(1)} {ACC1:not#18.itm(2)} {ACC1:not#18.itm(3)} {ACC1:not#18.itm(4)} {ACC1:not#18.itm(5)} {ACC1:not#18.itm(6)} {ACC1:not#18.itm(7)} {ACC1:not#18.itm(8)} {ACC1:not#18.itm(9)} -attr xrf 11790 -attr oid 178 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#18.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr xrf 11791 -attr oid 179 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {conc#156.itm(0)} -attr vt d
+load net {conc#156.itm(1)} -attr vt d
+load net {conc#156.itm(2)} -attr vt d
+load net {conc#156.itm(3)} -attr vt d
+load net {conc#156.itm(4)} -attr vt d
+load net {conc#156.itm(5)} -attr vt d
+load net {conc#156.itm(6)} -attr vt d
+load net {conc#156.itm(7)} -attr vt d
+load net {conc#156.itm(8)} -attr vt d
+load net {conc#156.itm(9)} -attr vt d
+load net {conc#156.itm(10)} -attr vt d
+load netBundle {conc#156.itm} 11 {conc#156.itm(0)} {conc#156.itm(1)} {conc#156.itm(2)} {conc#156.itm(3)} {conc#156.itm(4)} {conc#156.itm(5)} {conc#156.itm(6)} {conc#156.itm(7)} {conc#156.itm(8)} {conc#156.itm(9)} {conc#156.itm(10)} -attr xrf 11792 -attr oid 180 -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(9)} -attr xrf 11793 -attr oid 181 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {slc(g(2).sva#1).itm(0)} -attr vt d
+load net {slc(g(2).sva#1).itm(1)} -attr vt d
+load net {slc(g(2).sva#1).itm(2)} -attr vt d
+load net {slc(g(2).sva#1).itm(3)} -attr vt d
+load net {slc(g(2).sva#1).itm(4)} -attr vt d
+load net {slc(g(2).sva#1).itm(5)} -attr vt d
+load net {slc(g(2).sva#1).itm(6)} -attr vt d
+load net {slc(g(2).sva#1).itm(7)} -attr vt d
+load net {slc(g(2).sva#1).itm(8)} -attr vt d
+load net {slc(g(2).sva#1).itm(9)} -attr vt d
+load net {slc(g(2).sva#1).itm(10)} -attr vt d
+load net {slc(g(2).sva#1).itm(11)} -attr vt d
+load net {slc(g(2).sva#1).itm(12)} -attr vt d
+load net {slc(g(2).sva#1).itm(13)} -attr vt d
+load net {slc(g(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(g(2).sva#1).itm} 15 {slc(g(2).sva#1).itm(0)} {slc(g(2).sva#1).itm(1)} {slc(g(2).sva#1).itm(2)} {slc(g(2).sva#1).itm(3)} {slc(g(2).sva#1).itm(4)} {slc(g(2).sva#1).itm(5)} {slc(g(2).sva#1).itm(6)} {slc(g(2).sva#1).itm(7)} {slc(g(2).sva#1).itm(8)} {slc(g(2).sva#1).itm(9)} {slc(g(2).sva#1).itm(10)} {slc(g(2).sva#1).itm(11)} {slc(g(2).sva#1).itm(12)} {slc(g(2).sva#1).itm(13)} {slc(g(2).sva#1).itm(14)} -attr xrf 11794 -attr oid 182 -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {conc#157.itm(0)} -attr vt d
+load net {conc#157.itm(1)} -attr vt d
+load netBundle {conc#157.itm} 2 {conc#157.itm(0)} {conc#157.itm(1)} -attr xrf 11795 -attr oid 183 -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {conc#158.itm(0)} -attr vt d
+load net {conc#158.itm(1)} -attr vt d
+load net {conc#158.itm(2)} -attr vt d
+load net {conc#158.itm(3)} -attr vt d
+load net {conc#158.itm(4)} -attr vt d
+load net {conc#158.itm(5)} -attr vt d
+load netBundle {conc#158.itm} 6 {conc#158.itm(0)} {conc#158.itm(1)} {conc#158.itm(2)} {conc#158.itm(3)} {conc#158.itm(4)} {conc#158.itm(5)} -attr xrf 11796 -attr oid 184 -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {FRAME:acc#44.itm(0)} -attr vt d
+load net {FRAME:acc#44.itm(1)} -attr vt d
+load net {FRAME:acc#44.itm(2)} -attr vt d
+load net {FRAME:acc#44.itm(3)} -attr vt d
+load netBundle {FRAME:acc#44.itm} 4 {FRAME:acc#44.itm(0)} {FRAME:acc#44.itm(1)} {FRAME:acc#44.itm(2)} {FRAME:acc#44.itm(3)} -attr xrf 11797 -attr oid 185 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {slc(FRAME:acc#18.sdt).itm(0)} -attr vt d
+load net {slc(FRAME:acc#18.sdt).itm(1)} -attr vt d
+load net {slc(FRAME:acc#18.sdt).itm(2)} -attr vt d
+load net {slc(FRAME:acc#18.sdt).itm(3)} -attr vt d
+load netBundle {slc(FRAME:acc#18.sdt).itm} 4 {slc(FRAME:acc#18.sdt).itm(0)} {slc(FRAME:acc#18.sdt).itm(1)} {slc(FRAME:acc#18.sdt).itm(2)} {slc(FRAME:acc#18.sdt).itm(3)} -attr xrf 11798 -attr oid 186 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#18.sdt).itm}
+load net {FRAME:acc#20.itm(0)} -attr vt d
+load net {FRAME:acc#20.itm(1)} -attr vt d
+load net {FRAME:acc#20.itm(2)} -attr vt d
+load net {FRAME:acc#20.itm(3)} -attr vt d
+load net {FRAME:acc#20.itm(4)} -attr vt d
+load netBundle {FRAME:acc#20.itm} 5 {FRAME:acc#20.itm(0)} {FRAME:acc#20.itm(1)} {FRAME:acc#20.itm(2)} {FRAME:acc#20.itm(3)} {FRAME:acc#20.itm(4)} -attr xrf 11799 -attr oid 187 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#19.itm(0)} -attr vt d
+load net {FRAME:acc#19.itm(1)} -attr vt d
+load net {FRAME:acc#19.itm(2)} -attr vt d
+load net {FRAME:acc#19.itm(3)} -attr vt d
+load netBundle {FRAME:acc#19.itm} 4 {FRAME:acc#19.itm(0)} {FRAME:acc#19.itm(1)} {FRAME:acc#19.itm(2)} {FRAME:acc#19.itm(3)} -attr xrf 11800 -attr oid 188 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:not#10.itm(0)} -attr vt d
+load net {FRAME:not#10.itm(1)} -attr vt d
+load net {FRAME:not#10.itm(2)} -attr vt d
+load netBundle {FRAME:not#10.itm} 3 {FRAME:not#10.itm(0)} {FRAME:not#10.itm(1)} {FRAME:not#10.itm(2)} -attr xrf 11801 -attr oid 189 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {slc(green#2.sva)#6.itm(0)} -attr vt d
+load net {slc(green#2.sva)#6.itm(1)} -attr vt d
+load net {slc(green#2.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(green#2.sva)#6.itm} 3 {slc(green#2.sva)#6.itm(0)} {slc(green#2.sva)#6.itm(1)} {slc(green#2.sva)#6.itm(2)} -attr xrf 11802 -attr oid 190 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#6.itm}
+load net {slc(green#2.sva)#7.itm(0)} -attr vt d
+load net {slc(green#2.sva)#7.itm(1)} -attr vt d
+load net {slc(green#2.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(green#2.sva)#7.itm} 3 {slc(green#2.sva)#7.itm(0)} {slc(green#2.sva)#7.itm(1)} {slc(green#2.sva)#7.itm(2)} -attr xrf 11803 -attr oid 191 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#7.itm}
+load net {slc(green#2.sva)#8.itm(0)} -attr vt d
+load net {slc(green#2.sva)#8.itm(1)} -attr vt d
+load net {slc(green#2.sva)#8.itm(2)} -attr vt d
+load netBundle {slc(green#2.sva)#8.itm} 3 {slc(green#2.sva)#8.itm(0)} {slc(green#2.sva)#8.itm(1)} {slc(green#2.sva)#8.itm(2)} -attr xrf 11804 -attr oid 192 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#8.itm}
+load net {FRAME:acc#22.itm(0)} -attr vt d
+load net {FRAME:acc#22.itm(1)} -attr vt d
+load net {FRAME:acc#22.itm(2)} -attr vt d
+load net {FRAME:acc#22.itm(3)} -attr vt d
+load net {FRAME:acc#22.itm(4)} -attr vt d
+load netBundle {FRAME:acc#22.itm} 5 {FRAME:acc#22.itm(0)} {FRAME:acc#22.itm(1)} {FRAME:acc#22.itm(2)} {FRAME:acc#22.itm(3)} {FRAME:acc#22.itm(4)} -attr xrf 11805 -attr oid 193 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {conc#160.itm(0)} -attr vt d
+load net {conc#160.itm(1)} -attr vt d
+load net {conc#160.itm(2)} -attr vt d
+load net {conc#160.itm(3)} -attr vt d
+load net {conc#160.itm(4)} -attr vt d
+load netBundle {conc#160.itm} 5 {conc#160.itm(0)} {conc#160.itm(1)} {conc#160.itm(2)} {conc#160.itm(3)} {conc#160.itm(4)} -attr xrf 11806 -attr oid 194 -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {slc(FRAME:acc#9.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#9.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#9.psp.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(FRAME:acc#9.psp.sva)#2.itm} 3 {slc(FRAME:acc#9.psp.sva)#2.itm(0)} {slc(FRAME:acc#9.psp.sva)#2.itm(1)} {slc(FRAME:acc#9.psp.sva)#2.itm(2)} -attr xrf 11807 -attr oid 195 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#9.psp.sva)#2.itm}
+load net {FRAME:conc#70.itm(0)} -attr vt d
+load net {FRAME:conc#70.itm(1)} -attr vt d
+load net {FRAME:conc#70.itm(2)} -attr vt d
+load net {FRAME:conc#70.itm(3)} -attr vt d
+load netBundle {FRAME:conc#70.itm} 4 {FRAME:conc#70.itm(0)} {FRAME:conc#70.itm(1)} {FRAME:conc#70.itm(2)} {FRAME:conc#70.itm(3)} -attr xrf 11808 -attr oid 196 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#70.itm}
+load net {FRAME:not#13.itm(0)} -attr vt d
+load net {FRAME:not#13.itm(1)} -attr vt d
+load net {FRAME:not#13.itm(2)} -attr vt d
+load netBundle {FRAME:not#13.itm} 3 {FRAME:not#13.itm(0)} {FRAME:not#13.itm(1)} {FRAME:not#13.itm(2)} -attr xrf 11809 -attr oid 197 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {slc(FRAME:acc#9.psp.sva)#3.itm(0)} -attr vt d
+load net {slc(FRAME:acc#9.psp.sva)#3.itm(1)} -attr vt d
+load net {slc(FRAME:acc#9.psp.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(FRAME:acc#9.psp.sva)#3.itm} 3 {slc(FRAME:acc#9.psp.sva)#3.itm(0)} {slc(FRAME:acc#9.psp.sva)#3.itm(1)} {slc(FRAME:acc#9.psp.sva)#3.itm(2)} -attr xrf 11810 -attr oid 198 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#9.psp.sva)#3.itm}
+load net {FRAME:not#11.itm(0)} -attr vt d
+load net {FRAME:not#11.itm(1)} -attr vt d
+load net {FRAME:not#11.itm(2)} -attr vt d
+load netBundle {FRAME:not#11.itm} 3 {FRAME:not#11.itm(0)} {FRAME:not#11.itm(1)} {FRAME:not#11.itm(2)} -attr xrf 11811 -attr oid 199 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#11.itm}
+load net {slc(green#2.sva)#9.itm(0)} -attr vt d
+load net {slc(green#2.sva)#9.itm(1)} -attr vt d
+load net {slc(green#2.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(green#2.sva)#9.itm} 3 {slc(green#2.sva)#9.itm(0)} {slc(green#2.sva)#9.itm(1)} {slc(green#2.sva)#9.itm(2)} -attr xrf 11812 -attr oid 200 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#9.itm}
+load net {slc(green#2.sva).itm(0)} -attr vt d
+load net {slc(green#2.sva).itm(1)} -attr vt d
+load net {slc(green#2.sva).itm(2)} -attr vt d
+load netBundle {slc(green#2.sva).itm} 3 {slc(green#2.sva).itm(0)} {slc(green#2.sva).itm(1)} {slc(green#2.sva).itm(2)} -attr xrf 11813 -attr oid 201 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva).itm}
+load net {FRAME:not#2.itm(0)} -attr vt d
+load net {FRAME:not#2.itm(1)} -attr vt d
+load net {FRAME:not#2.itm(2)} -attr vt d
+load netBundle {FRAME:not#2.itm} 3 {FRAME:not#2.itm(0)} {FRAME:not#2.itm(1)} {FRAME:not#2.itm(2)} -attr xrf 11814 -attr oid 202 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {slc(red#2.sva)#9.itm(0)} -attr vt d
+load net {slc(red#2.sva)#9.itm(1)} -attr vt d
+load net {slc(red#2.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(red#2.sva)#9.itm} 3 {slc(red#2.sva)#9.itm(0)} {slc(red#2.sva)#9.itm(1)} {slc(red#2.sva)#9.itm(2)} -attr xrf 11815 -attr oid 203 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#9.itm}
+load net {slc(red#2.sva).itm(0)} -attr vt d
+load net {slc(red#2.sva).itm(1)} -attr vt d
+load net {slc(red#2.sva).itm(2)} -attr vt d
+load netBundle {slc(red#2.sva).itm} 3 {slc(red#2.sva).itm(0)} {slc(red#2.sva).itm(1)} {slc(red#2.sva).itm(2)} -attr xrf 11816 -attr oid 204 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva).itm}
+load net {FRAME:for:mux#10.itm(0)} -attr vt d
+load net {FRAME:for:mux#10.itm(1)} -attr vt d
+load net {FRAME:for:mux#10.itm(2)} -attr vt d
+load net {FRAME:for:mux#10.itm(3)} -attr vt d
+load net {FRAME:for:mux#10.itm(4)} -attr vt d
+load net {FRAME:for:mux#10.itm(5)} -attr vt d
+load net {FRAME:for:mux#10.itm(6)} -attr vt d
+load net {FRAME:for:mux#10.itm(7)} -attr vt d
+load net {FRAME:for:mux#10.itm(8)} -attr vt d
+load net {FRAME:for:mux#10.itm(9)} -attr vt d
+load net {FRAME:for:mux#10.itm(10)} -attr vt d
+load net {FRAME:for:mux#10.itm(11)} -attr vt d
+load net {FRAME:for:mux#10.itm(12)} -attr vt d
+load net {FRAME:for:mux#10.itm(13)} -attr vt d
+load net {FRAME:for:mux#10.itm(14)} -attr vt d
+load net {FRAME:for:mux#10.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#10.itm} 16 {FRAME:for:mux#10.itm(0)} {FRAME:for:mux#10.itm(1)} {FRAME:for:mux#10.itm(2)} {FRAME:for:mux#10.itm(3)} {FRAME:for:mux#10.itm(4)} {FRAME:for:mux#10.itm(5)} {FRAME:for:mux#10.itm(6)} {FRAME:for:mux#10.itm(7)} {FRAME:for:mux#10.itm(8)} {FRAME:for:mux#10.itm(9)} {FRAME:for:mux#10.itm(10)} {FRAME:for:mux#10.itm(11)} {FRAME:for:mux#10.itm(12)} {FRAME:for:mux#10.itm(13)} {FRAME:for:mux#10.itm(14)} {FRAME:for:mux#10.itm(15)} -attr xrf 11817 -attr oid 205 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:exs#25.itm(0)} -attr vt d
+load net {FRAME:for:exs#25.itm(1)} -attr vt d
+load net {FRAME:for:exs#25.itm(2)} -attr vt d
+load net {FRAME:for:exs#25.itm(3)} -attr vt d
+load net {FRAME:for:exs#25.itm(4)} -attr vt d
+load net {FRAME:for:exs#25.itm(5)} -attr vt d
+load net {FRAME:for:exs#25.itm(6)} -attr vt d
+load net {FRAME:for:exs#25.itm(7)} -attr vt d
+load net {FRAME:for:exs#25.itm(8)} -attr vt d
+load net {FRAME:for:exs#25.itm(9)} -attr vt d
+load net {FRAME:for:exs#25.itm(10)} -attr vt d
+load net {FRAME:for:exs#25.itm(11)} -attr vt d
+load net {FRAME:for:exs#25.itm(12)} -attr vt d
+load net {FRAME:for:exs#25.itm(13)} -attr vt d
+load net {FRAME:for:exs#25.itm(14)} -attr vt d
+load net {FRAME:for:exs#25.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#25.itm} 16 {FRAME:for:exs#25.itm(0)} {FRAME:for:exs#25.itm(1)} {FRAME:for:exs#25.itm(2)} {FRAME:for:exs#25.itm(3)} {FRAME:for:exs#25.itm(4)} {FRAME:for:exs#25.itm(5)} {FRAME:for:exs#25.itm(6)} {FRAME:for:exs#25.itm(7)} {FRAME:for:exs#25.itm(8)} {FRAME:for:exs#25.itm(9)} {FRAME:for:exs#25.itm(10)} {FRAME:for:exs#25.itm(11)} {FRAME:for:exs#25.itm(12)} {FRAME:for:exs#25.itm(13)} {FRAME:for:exs#25.itm(14)} {FRAME:for:exs#25.itm(15)} -attr xrf 11818 -attr oid 206 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:slc#5.itm(0)} -attr vt d
+load net {ACC1:slc#5.itm(1)} -attr vt d
+load net {ACC1:slc#5.itm(2)} -attr vt d
+load net {ACC1:slc#5.itm(3)} -attr vt d
+load net {ACC1:slc#5.itm(4)} -attr vt d
+load net {ACC1:slc#5.itm(5)} -attr vt d
+load net {ACC1:slc#5.itm(6)} -attr vt d
+load net {ACC1:slc#5.itm(7)} -attr vt d
+load net {ACC1:slc#5.itm(8)} -attr vt d
+load net {ACC1:slc#5.itm(9)} -attr vt d
+load net {ACC1:slc#5.itm(10)} -attr vt d
+load netBundle {ACC1:slc#5.itm} 11 {ACC1:slc#5.itm(0)} {ACC1:slc#5.itm(1)} {ACC1:slc#5.itm(2)} {ACC1:slc#5.itm(3)} {ACC1:slc#5.itm(4)} {ACC1:slc#5.itm(5)} {ACC1:slc#5.itm(6)} {ACC1:slc#5.itm(7)} {ACC1:slc#5.itm(8)} {ACC1:slc#5.itm(9)} {ACC1:slc#5.itm(10)} -attr xrf 11819 -attr oid 207 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#5.itm}
+load net {ACC1:acc#49.itm(0)} -attr vt d
+load net {ACC1:acc#49.itm(1)} -attr vt d
+load net {ACC1:acc#49.itm(2)} -attr vt d
+load net {ACC1:acc#49.itm(3)} -attr vt d
+load net {ACC1:acc#49.itm(4)} -attr vt d
+load net {ACC1:acc#49.itm(5)} -attr vt d
+load net {ACC1:acc#49.itm(6)} -attr vt d
+load net {ACC1:acc#49.itm(7)} -attr vt d
+load net {ACC1:acc#49.itm(8)} -attr vt d
+load net {ACC1:acc#49.itm(9)} -attr vt d
+load net {ACC1:acc#49.itm(10)} -attr vt d
+load net {ACC1:acc#49.itm(11)} -attr vt d
+load netBundle {ACC1:acc#49.itm} 12 {ACC1:acc#49.itm(0)} {ACC1:acc#49.itm(1)} {ACC1:acc#49.itm(2)} {ACC1:acc#49.itm(3)} {ACC1:acc#49.itm(4)} {ACC1:acc#49.itm(5)} {ACC1:acc#49.itm(6)} {ACC1:acc#49.itm(7)} {ACC1:acc#49.itm(8)} {ACC1:acc#49.itm(9)} {ACC1:acc#49.itm(10)} {ACC1:acc#49.itm(11)} -attr xrf 11820 -attr oid 208 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {conc#161.itm(0)} -attr vt d
+load net {conc#161.itm(1)} -attr vt d
+load net {conc#161.itm(2)} -attr vt d
+load net {conc#161.itm(3)} -attr vt d
+load net {conc#161.itm(4)} -attr vt d
+load net {conc#161.itm(5)} -attr vt d
+load net {conc#161.itm(6)} -attr vt d
+load net {conc#161.itm(7)} -attr vt d
+load net {conc#161.itm(8)} -attr vt d
+load net {conc#161.itm(9)} -attr vt d
+load net {conc#161.itm(10)} -attr vt d
+load netBundle {conc#161.itm} 11 {conc#161.itm(0)} {conc#161.itm(1)} {conc#161.itm(2)} {conc#161.itm(3)} {conc#161.itm(4)} {conc#161.itm(5)} {conc#161.itm(6)} {conc#161.itm(7)} {conc#161.itm(8)} {conc#161.itm(9)} {conc#161.itm(10)} -attr xrf 11821 -attr oid 209 -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {ACC1:not#14.itm(0)} -attr vt d
+load net {ACC1:not#14.itm(1)} -attr vt d
+load net {ACC1:not#14.itm(2)} -attr vt d
+load net {ACC1:not#14.itm(3)} -attr vt d
+load net {ACC1:not#14.itm(4)} -attr vt d
+load net {ACC1:not#14.itm(5)} -attr vt d
+load net {ACC1:not#14.itm(6)} -attr vt d
+load net {ACC1:not#14.itm(7)} -attr vt d
+load net {ACC1:not#14.itm(8)} -attr vt d
+load net {ACC1:not#14.itm(9)} -attr vt d
+load netBundle {ACC1:not#14.itm} 10 {ACC1:not#14.itm(0)} {ACC1:not#14.itm(1)} {ACC1:not#14.itm(2)} {ACC1:not#14.itm(3)} {ACC1:not#14.itm(4)} {ACC1:not#14.itm(5)} {ACC1:not#14.itm(6)} {ACC1:not#14.itm(7)} {ACC1:not#14.itm(8)} {ACC1:not#14.itm(9)} -attr xrf 11822 -attr oid 210 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {slc(regs.regs(0).sva#1).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#1).itm} 10 {slc(regs.regs(0).sva#1).itm(0)} {slc(regs.regs(0).sva#1).itm(1)} {slc(regs.regs(0).sva#1).itm(2)} {slc(regs.regs(0).sva#1).itm(3)} {slc(regs.regs(0).sva#1).itm(4)} {slc(regs.regs(0).sva#1).itm(5)} {slc(regs.regs(0).sva#1).itm(6)} {slc(regs.regs(0).sva#1).itm(7)} {slc(regs.regs(0).sva#1).itm(8)} {slc(regs.regs(0).sva#1).itm(9)} -attr xrf 11823 -attr oid 211 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {conc#162.itm(0)} -attr vt d
+load net {conc#162.itm(1)} -attr vt d
+load net {conc#162.itm(2)} -attr vt d
+load net {conc#162.itm(3)} -attr vt d
+load net {conc#162.itm(4)} -attr vt d
+load net {conc#162.itm(5)} -attr vt d
+load net {conc#162.itm(6)} -attr vt d
+load net {conc#162.itm(7)} -attr vt d
+load net {conc#162.itm(8)} -attr vt d
+load net {conc#162.itm(9)} -attr vt d
+load net {conc#162.itm(10)} -attr vt d
+load netBundle {conc#162.itm} 11 {conc#162.itm(0)} {conc#162.itm(1)} {conc#162.itm(2)} {conc#162.itm(3)} {conc#162.itm(4)} {conc#162.itm(5)} {conc#162.itm(6)} {conc#162.itm(7)} {conc#162.itm(8)} {conc#162.itm(9)} {conc#162.itm(10)} -attr xrf 11824 -attr oid 212 -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {slc(regs.regs(1).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva).itm} 10 {slc(regs.regs(1).sva).itm(0)} {slc(regs.regs(1).sva).itm(1)} {slc(regs.regs(1).sva).itm(2)} {slc(regs.regs(1).sva).itm(3)} {slc(regs.regs(1).sva).itm(4)} {slc(regs.regs(1).sva).itm(5)} {slc(regs.regs(1).sva).itm(6)} {slc(regs.regs(1).sva).itm(7)} {slc(regs.regs(1).sva).itm(8)} {slc(regs.regs(1).sva).itm(9)} -attr xrf 11825 -attr oid 213 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {FRAME:for:mul#8.itm(0)} -attr vt d
+load net {FRAME:for:mul#8.itm(1)} -attr vt d
+load net {FRAME:for:mul#8.itm(2)} -attr vt d
+load net {FRAME:for:mul#8.itm(3)} -attr vt d
+load net {FRAME:for:mul#8.itm(4)} -attr vt d
+load net {FRAME:for:mul#8.itm(5)} -attr vt d
+load net {FRAME:for:mul#8.itm(6)} -attr vt d
+load net {FRAME:for:mul#8.itm(7)} -attr vt d
+load net {FRAME:for:mul#8.itm(8)} -attr vt d
+load net {FRAME:for:mul#8.itm(9)} -attr vt d
+load net {FRAME:for:mul#8.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#8.itm} 11 {FRAME:for:mul#8.itm(0)} {FRAME:for:mul#8.itm(1)} {FRAME:for:mul#8.itm(2)} {FRAME:for:mul#8.itm(3)} {FRAME:for:mul#8.itm(4)} {FRAME:for:mul#8.itm(5)} {FRAME:for:mul#8.itm(6)} {FRAME:for:mul#8.itm(7)} {FRAME:for:mul#8.itm(8)} {FRAME:for:mul#8.itm(9)} {FRAME:for:mul#8.itm(10)} -attr xrf 11826 -attr oid 214 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {regs.operator[]#17:mux.itm(0)} -attr vt d
+load net {regs.operator[]#17:mux.itm(1)} -attr vt d
+load net {regs.operator[]#17:mux.itm(2)} -attr vt d
+load net {regs.operator[]#17:mux.itm(3)} -attr vt d
+load net {regs.operator[]#17:mux.itm(4)} -attr vt d
+load net {regs.operator[]#17:mux.itm(5)} -attr vt d
+load net {regs.operator[]#17:mux.itm(6)} -attr vt d
+load net {regs.operator[]#17:mux.itm(7)} -attr vt d
+load net {regs.operator[]#17:mux.itm(8)} -attr vt d
+load net {regs.operator[]#17:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#17:mux.itm} 10 {regs.operator[]#17:mux.itm(0)} {regs.operator[]#17:mux.itm(1)} {regs.operator[]#17:mux.itm(2)} {regs.operator[]#17:mux.itm(3)} {regs.operator[]#17:mux.itm(4)} {regs.operator[]#17:mux.itm(5)} {regs.operator[]#17:mux.itm(6)} {regs.operator[]#17:mux.itm(7)} {regs.operator[]#17:mux.itm(8)} {regs.operator[]#17:mux.itm(9)} -attr xrf 11827 -attr oid 215 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(9)} -attr xrf 11828 -attr oid 216 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0).itm} 10 {slc(regs.regs(1).sva.dfm:mx0).itm(0)} {slc(regs.regs(1).sva.dfm:mx0).itm(1)} {slc(regs.regs(1).sva.dfm:mx0).itm(2)} {slc(regs.regs(1).sva.dfm:mx0).itm(3)} {slc(regs.regs(1).sva.dfm:mx0).itm(4)} {slc(regs.regs(1).sva.dfm:mx0).itm(5)} {slc(regs.regs(1).sva.dfm:mx0).itm(6)} {slc(regs.regs(1).sva.dfm:mx0).itm(7)} {slc(regs.regs(1).sva.dfm:mx0).itm(8)} {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr xrf 11829 -attr oid 217 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr xrf 11830 -attr oid 218 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {FRAME:for:mux#9.itm(0)} -attr vt d
+load net {FRAME:for:mux#9.itm(1)} -attr vt d
+load net {FRAME:for:mux#9.itm(2)} -attr vt d
+load net {FRAME:for:mux#9.itm(3)} -attr vt d
+load net {FRAME:for:mux#9.itm(4)} -attr vt d
+load net {FRAME:for:mux#9.itm(5)} -attr vt d
+load net {FRAME:for:mux#9.itm(6)} -attr vt d
+load net {FRAME:for:mux#9.itm(7)} -attr vt d
+load net {FRAME:for:mux#9.itm(8)} -attr vt d
+load net {FRAME:for:mux#9.itm(9)} -attr vt d
+load net {FRAME:for:mux#9.itm(10)} -attr vt d
+load net {FRAME:for:mux#9.itm(11)} -attr vt d
+load net {FRAME:for:mux#9.itm(12)} -attr vt d
+load net {FRAME:for:mux#9.itm(13)} -attr vt d
+load net {FRAME:for:mux#9.itm(14)} -attr vt d
+load net {FRAME:for:mux#9.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#9.itm} 16 {FRAME:for:mux#9.itm(0)} {FRAME:for:mux#9.itm(1)} {FRAME:for:mux#9.itm(2)} {FRAME:for:mux#9.itm(3)} {FRAME:for:mux#9.itm(4)} {FRAME:for:mux#9.itm(5)} {FRAME:for:mux#9.itm(6)} {FRAME:for:mux#9.itm(7)} {FRAME:for:mux#9.itm(8)} {FRAME:for:mux#9.itm(9)} {FRAME:for:mux#9.itm(10)} {FRAME:for:mux#9.itm(11)} {FRAME:for:mux#9.itm(12)} {FRAME:for:mux#9.itm(13)} {FRAME:for:mux#9.itm(14)} {FRAME:for:mux#9.itm(15)} -attr xrf 11831 -attr oid 219 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:exs#22.itm(0)} -attr vt d
+load net {FRAME:for:exs#22.itm(1)} -attr vt d
+load net {FRAME:for:exs#22.itm(2)} -attr vt d
+load net {FRAME:for:exs#22.itm(3)} -attr vt d
+load net {FRAME:for:exs#22.itm(4)} -attr vt d
+load net {FRAME:for:exs#22.itm(5)} -attr vt d
+load net {FRAME:for:exs#22.itm(6)} -attr vt d
+load net {FRAME:for:exs#22.itm(7)} -attr vt d
+load net {FRAME:for:exs#22.itm(8)} -attr vt d
+load net {FRAME:for:exs#22.itm(9)} -attr vt d
+load net {FRAME:for:exs#22.itm(10)} -attr vt d
+load net {FRAME:for:exs#22.itm(11)} -attr vt d
+load net {FRAME:for:exs#22.itm(12)} -attr vt d
+load net {FRAME:for:exs#22.itm(13)} -attr vt d
+load net {FRAME:for:exs#22.itm(14)} -attr vt d
+load net {FRAME:for:exs#22.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#22.itm} 16 {FRAME:for:exs#22.itm(0)} {FRAME:for:exs#22.itm(1)} {FRAME:for:exs#22.itm(2)} {FRAME:for:exs#22.itm(3)} {FRAME:for:exs#22.itm(4)} {FRAME:for:exs#22.itm(5)} {FRAME:for:exs#22.itm(6)} {FRAME:for:exs#22.itm(7)} {FRAME:for:exs#22.itm(8)} {FRAME:for:exs#22.itm(9)} {FRAME:for:exs#22.itm(10)} {FRAME:for:exs#22.itm(11)} {FRAME:for:exs#22.itm(12)} {FRAME:for:exs#22.itm(13)} {FRAME:for:exs#22.itm(14)} {FRAME:for:exs#22.itm(15)} -attr xrf 11832 -attr oid 220 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:slc#2.itm(0)} -attr vt d
+load net {ACC1:slc#2.itm(1)} -attr vt d
+load net {ACC1:slc#2.itm(2)} -attr vt d
+load net {ACC1:slc#2.itm(3)} -attr vt d
+load net {ACC1:slc#2.itm(4)} -attr vt d
+load net {ACC1:slc#2.itm(5)} -attr vt d
+load net {ACC1:slc#2.itm(6)} -attr vt d
+load net {ACC1:slc#2.itm(7)} -attr vt d
+load net {ACC1:slc#2.itm(8)} -attr vt d
+load net {ACC1:slc#2.itm(9)} -attr vt d
+load net {ACC1:slc#2.itm(10)} -attr vt d
+load netBundle {ACC1:slc#2.itm} 11 {ACC1:slc#2.itm(0)} {ACC1:slc#2.itm(1)} {ACC1:slc#2.itm(2)} {ACC1:slc#2.itm(3)} {ACC1:slc#2.itm(4)} {ACC1:slc#2.itm(5)} {ACC1:slc#2.itm(6)} {ACC1:slc#2.itm(7)} {ACC1:slc#2.itm(8)} {ACC1:slc#2.itm(9)} {ACC1:slc#2.itm(10)} -attr xrf 11833 -attr oid 221 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#46.itm(0)} -attr vt d
+load net {ACC1:acc#46.itm(1)} -attr vt d
+load net {ACC1:acc#46.itm(2)} -attr vt d
+load net {ACC1:acc#46.itm(3)} -attr vt d
+load net {ACC1:acc#46.itm(4)} -attr vt d
+load net {ACC1:acc#46.itm(5)} -attr vt d
+load net {ACC1:acc#46.itm(6)} -attr vt d
+load net {ACC1:acc#46.itm(7)} -attr vt d
+load net {ACC1:acc#46.itm(8)} -attr vt d
+load net {ACC1:acc#46.itm(9)} -attr vt d
+load net {ACC1:acc#46.itm(10)} -attr vt d
+load net {ACC1:acc#46.itm(11)} -attr vt d
+load netBundle {ACC1:acc#46.itm} 12 {ACC1:acc#46.itm(0)} {ACC1:acc#46.itm(1)} {ACC1:acc#46.itm(2)} {ACC1:acc#46.itm(3)} {ACC1:acc#46.itm(4)} {ACC1:acc#46.itm(5)} {ACC1:acc#46.itm(6)} {ACC1:acc#46.itm(7)} {ACC1:acc#46.itm(8)} {ACC1:acc#46.itm(9)} {ACC1:acc#46.itm(10)} {ACC1:acc#46.itm(11)} -attr xrf 11834 -attr oid 222 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46.itm}
+load net {conc#163.itm(0)} -attr vt d
+load net {conc#163.itm(1)} -attr vt d
+load net {conc#163.itm(2)} -attr vt d
+load net {conc#163.itm(3)} -attr vt d
+load net {conc#163.itm(4)} -attr vt d
+load net {conc#163.itm(5)} -attr vt d
+load net {conc#163.itm(6)} -attr vt d
+load net {conc#163.itm(7)} -attr vt d
+load net {conc#163.itm(8)} -attr vt d
+load net {conc#163.itm(9)} -attr vt d
+load net {conc#163.itm(10)} -attr vt d
+load netBundle {conc#163.itm} 11 {conc#163.itm(0)} {conc#163.itm(1)} {conc#163.itm(2)} {conc#163.itm(3)} {conc#163.itm(4)} {conc#163.itm(5)} {conc#163.itm(6)} {conc#163.itm(7)} {conc#163.itm(8)} {conc#163.itm(9)} {conc#163.itm(10)} -attr xrf 11835 -attr oid 223 -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {ACC1:not#16.itm(0)} -attr vt d
+load net {ACC1:not#16.itm(1)} -attr vt d
+load net {ACC1:not#16.itm(2)} -attr vt d
+load net {ACC1:not#16.itm(3)} -attr vt d
+load net {ACC1:not#16.itm(4)} -attr vt d
+load net {ACC1:not#16.itm(5)} -attr vt d
+load net {ACC1:not#16.itm(6)} -attr vt d
+load net {ACC1:not#16.itm(7)} -attr vt d
+load net {ACC1:not#16.itm(8)} -attr vt d
+load net {ACC1:not#16.itm(9)} -attr vt d
+load netBundle {ACC1:not#16.itm} 10 {ACC1:not#16.itm(0)} {ACC1:not#16.itm(1)} {ACC1:not#16.itm(2)} {ACC1:not#16.itm(3)} {ACC1:not#16.itm(4)} {ACC1:not#16.itm(5)} {ACC1:not#16.itm(6)} {ACC1:not#16.itm(7)} {ACC1:not#16.itm(8)} {ACC1:not#16.itm(9)} -attr xrf 11836 -attr oid 224 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {slc(regs.regs(0).sva#4).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#4).itm} 10 {slc(regs.regs(0).sva#4).itm(0)} {slc(regs.regs(0).sva#4).itm(1)} {slc(regs.regs(0).sva#4).itm(2)} {slc(regs.regs(0).sva#4).itm(3)} {slc(regs.regs(0).sva#4).itm(4)} {slc(regs.regs(0).sva#4).itm(5)} {slc(regs.regs(0).sva#4).itm(6)} {slc(regs.regs(0).sva#4).itm(7)} {slc(regs.regs(0).sva#4).itm(8)} {slc(regs.regs(0).sva#4).itm(9)} -attr xrf 11837 -attr oid 225 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {conc#164.itm(0)} -attr vt d
+load net {conc#164.itm(1)} -attr vt d
+load net {conc#164.itm(2)} -attr vt d
+load net {conc#164.itm(3)} -attr vt d
+load net {conc#164.itm(4)} -attr vt d
+load net {conc#164.itm(5)} -attr vt d
+load net {conc#164.itm(6)} -attr vt d
+load net {conc#164.itm(7)} -attr vt d
+load net {conc#164.itm(8)} -attr vt d
+load net {conc#164.itm(9)} -attr vt d
+load net {conc#164.itm(10)} -attr vt d
+load netBundle {conc#164.itm} 11 {conc#164.itm(0)} {conc#164.itm(1)} {conc#164.itm(2)} {conc#164.itm(3)} {conc#164.itm(4)} {conc#164.itm(5)} {conc#164.itm(6)} {conc#164.itm(7)} {conc#164.itm(8)} {conc#164.itm(9)} {conc#164.itm(10)} -attr xrf 11838 -attr oid 226 -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {slc(regs.regs(1).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#3.itm} 10 {slc(regs.regs(1).sva)#3.itm(0)} {slc(regs.regs(1).sva)#3.itm(1)} {slc(regs.regs(1).sva)#3.itm(2)} {slc(regs.regs(1).sva)#3.itm(3)} {slc(regs.regs(1).sva)#3.itm(4)} {slc(regs.regs(1).sva)#3.itm(5)} {slc(regs.regs(1).sva)#3.itm(6)} {slc(regs.regs(1).sva)#3.itm(7)} {slc(regs.regs(1).sva)#3.itm(8)} {slc(regs.regs(1).sva)#3.itm(9)} -attr xrf 11839 -attr oid 227 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {FRAME:for:mul#2.itm(0)} -attr vt d
+load net {FRAME:for:mul#2.itm(1)} -attr vt d
+load net {FRAME:for:mul#2.itm(2)} -attr vt d
+load net {FRAME:for:mul#2.itm(3)} -attr vt d
+load net {FRAME:for:mul#2.itm(4)} -attr vt d
+load net {FRAME:for:mul#2.itm(5)} -attr vt d
+load net {FRAME:for:mul#2.itm(6)} -attr vt d
+load net {FRAME:for:mul#2.itm(7)} -attr vt d
+load net {FRAME:for:mul#2.itm(8)} -attr vt d
+load net {FRAME:for:mul#2.itm(9)} -attr vt d
+load net {FRAME:for:mul#2.itm(10)} -attr vt d
+load net {FRAME:for:mul#2.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul#2.itm} 12 {FRAME:for:mul#2.itm(0)} {FRAME:for:mul#2.itm(1)} {FRAME:for:mul#2.itm(2)} {FRAME:for:mul#2.itm(3)} {FRAME:for:mul#2.itm(4)} {FRAME:for:mul#2.itm(5)} {FRAME:for:mul#2.itm(6)} {FRAME:for:mul#2.itm(7)} {FRAME:for:mul#2.itm(8)} {FRAME:for:mul#2.itm(9)} {FRAME:for:mul#2.itm(10)} {FRAME:for:mul#2.itm(11)} -attr xrf 11840 -attr oid 228 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {regs.operator[]#11:mux.itm(0)} -attr vt d
+load net {regs.operator[]#11:mux.itm(1)} -attr vt d
+load net {regs.operator[]#11:mux.itm(2)} -attr vt d
+load net {regs.operator[]#11:mux.itm(3)} -attr vt d
+load net {regs.operator[]#11:mux.itm(4)} -attr vt d
+load net {regs.operator[]#11:mux.itm(5)} -attr vt d
+load net {regs.operator[]#11:mux.itm(6)} -attr vt d
+load net {regs.operator[]#11:mux.itm(7)} -attr vt d
+load net {regs.operator[]#11:mux.itm(8)} -attr vt d
+load net {regs.operator[]#11:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#11:mux.itm} 10 {regs.operator[]#11:mux.itm(0)} {regs.operator[]#11:mux.itm(1)} {regs.operator[]#11:mux.itm(2)} {regs.operator[]#11:mux.itm(3)} {regs.operator[]#11:mux.itm(4)} {regs.operator[]#11:mux.itm(5)} {regs.operator[]#11:mux.itm(6)} {regs.operator[]#11:mux.itm(7)} {regs.operator[]#11:mux.itm(8)} {regs.operator[]#11:mux.itm(9)} -attr xrf 11841 -attr oid 229 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(9)} -attr xrf 11842 -attr oid 230 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr xrf 11843 -attr oid 231 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#6.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#6.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(9)} -attr xrf 11844 -attr oid 232 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {conc#165.itm(0)} -attr vt d
+load net {conc#165.itm(1)} -attr vt d
+load netBundle {conc#165.itm} 2 {conc#165.itm(0)} {conc#165.itm(1)} -attr xrf 11845 -attr oid 233 -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {FRAME:for:mux#8.itm(0)} -attr vt d
+load net {FRAME:for:mux#8.itm(1)} -attr vt d
+load net {FRAME:for:mux#8.itm(2)} -attr vt d
+load net {FRAME:for:mux#8.itm(3)} -attr vt d
+load net {FRAME:for:mux#8.itm(4)} -attr vt d
+load net {FRAME:for:mux#8.itm(5)} -attr vt d
+load net {FRAME:for:mux#8.itm(6)} -attr vt d
+load net {FRAME:for:mux#8.itm(7)} -attr vt d
+load net {FRAME:for:mux#8.itm(8)} -attr vt d
+load net {FRAME:for:mux#8.itm(9)} -attr vt d
+load net {FRAME:for:mux#8.itm(10)} -attr vt d
+load net {FRAME:for:mux#8.itm(11)} -attr vt d
+load net {FRAME:for:mux#8.itm(12)} -attr vt d
+load net {FRAME:for:mux#8.itm(13)} -attr vt d
+load net {FRAME:for:mux#8.itm(14)} -attr vt d
+load net {FRAME:for:mux#8.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#8.itm} 16 {FRAME:for:mux#8.itm(0)} {FRAME:for:mux#8.itm(1)} {FRAME:for:mux#8.itm(2)} {FRAME:for:mux#8.itm(3)} {FRAME:for:mux#8.itm(4)} {FRAME:for:mux#8.itm(5)} {FRAME:for:mux#8.itm(6)} {FRAME:for:mux#8.itm(7)} {FRAME:for:mux#8.itm(8)} {FRAME:for:mux#8.itm(9)} {FRAME:for:mux#8.itm(10)} {FRAME:for:mux#8.itm(11)} {FRAME:for:mux#8.itm(12)} {FRAME:for:mux#8.itm(13)} {FRAME:for:mux#8.itm(14)} {FRAME:for:mux#8.itm(15)} -attr xrf 11846 -attr oid 234 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:exs#24.itm(0)} -attr vt d
+load net {FRAME:for:exs#24.itm(1)} -attr vt d
+load net {FRAME:for:exs#24.itm(2)} -attr vt d
+load net {FRAME:for:exs#24.itm(3)} -attr vt d
+load net {FRAME:for:exs#24.itm(4)} -attr vt d
+load net {FRAME:for:exs#24.itm(5)} -attr vt d
+load net {FRAME:for:exs#24.itm(6)} -attr vt d
+load net {FRAME:for:exs#24.itm(7)} -attr vt d
+load net {FRAME:for:exs#24.itm(8)} -attr vt d
+load net {FRAME:for:exs#24.itm(9)} -attr vt d
+load net {FRAME:for:exs#24.itm(10)} -attr vt d
+load net {FRAME:for:exs#24.itm(11)} -attr vt d
+load net {FRAME:for:exs#24.itm(12)} -attr vt d
+load net {FRAME:for:exs#24.itm(13)} -attr vt d
+load net {FRAME:for:exs#24.itm(14)} -attr vt d
+load net {FRAME:for:exs#24.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#24.itm} 16 {FRAME:for:exs#24.itm(0)} {FRAME:for:exs#24.itm(1)} {FRAME:for:exs#24.itm(2)} {FRAME:for:exs#24.itm(3)} {FRAME:for:exs#24.itm(4)} {FRAME:for:exs#24.itm(5)} {FRAME:for:exs#24.itm(6)} {FRAME:for:exs#24.itm(7)} {FRAME:for:exs#24.itm(8)} {FRAME:for:exs#24.itm(9)} {FRAME:for:exs#24.itm(10)} {FRAME:for:exs#24.itm(11)} {FRAME:for:exs#24.itm(12)} {FRAME:for:exs#24.itm(13)} {FRAME:for:exs#24.itm(14)} {FRAME:for:exs#24.itm(15)} -attr xrf 11847 -attr oid 235 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:slc#4.itm(0)} -attr vt d
+load net {ACC1:slc#4.itm(1)} -attr vt d
+load net {ACC1:slc#4.itm(2)} -attr vt d
+load net {ACC1:slc#4.itm(3)} -attr vt d
+load net {ACC1:slc#4.itm(4)} -attr vt d
+load net {ACC1:slc#4.itm(5)} -attr vt d
+load net {ACC1:slc#4.itm(6)} -attr vt d
+load net {ACC1:slc#4.itm(7)} -attr vt d
+load net {ACC1:slc#4.itm(8)} -attr vt d
+load net {ACC1:slc#4.itm(9)} -attr vt d
+load net {ACC1:slc#4.itm(10)} -attr vt d
+load netBundle {ACC1:slc#4.itm} 11 {ACC1:slc#4.itm(0)} {ACC1:slc#4.itm(1)} {ACC1:slc#4.itm(2)} {ACC1:slc#4.itm(3)} {ACC1:slc#4.itm(4)} {ACC1:slc#4.itm(5)} {ACC1:slc#4.itm(6)} {ACC1:slc#4.itm(7)} {ACC1:slc#4.itm(8)} {ACC1:slc#4.itm(9)} {ACC1:slc#4.itm(10)} -attr xrf 11848 -attr oid 236 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#4.itm}
+load net {ACC1:acc#48.itm(0)} -attr vt d
+load net {ACC1:acc#48.itm(1)} -attr vt d
+load net {ACC1:acc#48.itm(2)} -attr vt d
+load net {ACC1:acc#48.itm(3)} -attr vt d
+load net {ACC1:acc#48.itm(4)} -attr vt d
+load net {ACC1:acc#48.itm(5)} -attr vt d
+load net {ACC1:acc#48.itm(6)} -attr vt d
+load net {ACC1:acc#48.itm(7)} -attr vt d
+load net {ACC1:acc#48.itm(8)} -attr vt d
+load net {ACC1:acc#48.itm(9)} -attr vt d
+load net {ACC1:acc#48.itm(10)} -attr vt d
+load net {ACC1:acc#48.itm(11)} -attr vt d
+load netBundle {ACC1:acc#48.itm} 12 {ACC1:acc#48.itm(0)} {ACC1:acc#48.itm(1)} {ACC1:acc#48.itm(2)} {ACC1:acc#48.itm(3)} {ACC1:acc#48.itm(4)} {ACC1:acc#48.itm(5)} {ACC1:acc#48.itm(6)} {ACC1:acc#48.itm(7)} {ACC1:acc#48.itm(8)} {ACC1:acc#48.itm(9)} {ACC1:acc#48.itm(10)} {ACC1:acc#48.itm(11)} -attr xrf 11849 -attr oid 237 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {conc#166.itm(0)} -attr vt d
+load net {conc#166.itm(1)} -attr vt d
+load net {conc#166.itm(2)} -attr vt d
+load net {conc#166.itm(3)} -attr vt d
+load net {conc#166.itm(4)} -attr vt d
+load net {conc#166.itm(5)} -attr vt d
+load net {conc#166.itm(6)} -attr vt d
+load net {conc#166.itm(7)} -attr vt d
+load net {conc#166.itm(8)} -attr vt d
+load net {conc#166.itm(9)} -attr vt d
+load net {conc#166.itm(10)} -attr vt d
+load netBundle {conc#166.itm} 11 {conc#166.itm(0)} {conc#166.itm(1)} {conc#166.itm(2)} {conc#166.itm(3)} {conc#166.itm(4)} {conc#166.itm(5)} {conc#166.itm(6)} {conc#166.itm(7)} {conc#166.itm(8)} {conc#166.itm(9)} {conc#166.itm(10)} -attr xrf 11850 -attr oid 238 -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {ACC1:not#13.itm(0)} -attr vt d
+load net {ACC1:not#13.itm(1)} -attr vt d
+load net {ACC1:not#13.itm(2)} -attr vt d
+load net {ACC1:not#13.itm(3)} -attr vt d
+load net {ACC1:not#13.itm(4)} -attr vt d
+load net {ACC1:not#13.itm(5)} -attr vt d
+load net {ACC1:not#13.itm(6)} -attr vt d
+load net {ACC1:not#13.itm(7)} -attr vt d
+load net {ACC1:not#13.itm(8)} -attr vt d
+load net {ACC1:not#13.itm(9)} -attr vt d
+load netBundle {ACC1:not#13.itm} 10 {ACC1:not#13.itm(0)} {ACC1:not#13.itm(1)} {ACC1:not#13.itm(2)} {ACC1:not#13.itm(3)} {ACC1:not#13.itm(4)} {ACC1:not#13.itm(5)} {ACC1:not#13.itm(6)} {ACC1:not#13.itm(7)} {ACC1:not#13.itm(8)} {ACC1:not#13.itm(9)} -attr xrf 11851 -attr oid 239 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {slc(regs.regs(0).sva#2).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#2).itm} 10 {slc(regs.regs(0).sva#2).itm(0)} {slc(regs.regs(0).sva#2).itm(1)} {slc(regs.regs(0).sva#2).itm(2)} {slc(regs.regs(0).sva#2).itm(3)} {slc(regs.regs(0).sva#2).itm(4)} {slc(regs.regs(0).sva#2).itm(5)} {slc(regs.regs(0).sva#2).itm(6)} {slc(regs.regs(0).sva#2).itm(7)} {slc(regs.regs(0).sva#2).itm(8)} {slc(regs.regs(0).sva#2).itm(9)} -attr xrf 11852 -attr oid 240 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {conc#167.itm(0)} -attr vt d
+load net {conc#167.itm(1)} -attr vt d
+load net {conc#167.itm(2)} -attr vt d
+load net {conc#167.itm(3)} -attr vt d
+load net {conc#167.itm(4)} -attr vt d
+load net {conc#167.itm(5)} -attr vt d
+load net {conc#167.itm(6)} -attr vt d
+load net {conc#167.itm(7)} -attr vt d
+load net {conc#167.itm(8)} -attr vt d
+load net {conc#167.itm(9)} -attr vt d
+load net {conc#167.itm(10)} -attr vt d
+load netBundle {conc#167.itm} 11 {conc#167.itm(0)} {conc#167.itm(1)} {conc#167.itm(2)} {conc#167.itm(3)} {conc#167.itm(4)} {conc#167.itm(5)} {conc#167.itm(6)} {conc#167.itm(7)} {conc#167.itm(8)} {conc#167.itm(9)} {conc#167.itm(10)} -attr xrf 11853 -attr oid 241 -attr vt d -attr @path {/sobel/sobel:core/conc#167.itm}
+load net {slc(regs.regs(1).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#1.itm} 10 {slc(regs.regs(1).sva)#1.itm(0)} {slc(regs.regs(1).sva)#1.itm(1)} {slc(regs.regs(1).sva)#1.itm(2)} {slc(regs.regs(1).sva)#1.itm(3)} {slc(regs.regs(1).sva)#1.itm(4)} {slc(regs.regs(1).sva)#1.itm(5)} {slc(regs.regs(1).sva)#1.itm(6)} {slc(regs.regs(1).sva)#1.itm(7)} {slc(regs.regs(1).sva)#1.itm(8)} {slc(regs.regs(1).sva)#1.itm(9)} -attr xrf 11854 -attr oid 242 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {FRAME:for:mul#7.itm(0)} -attr vt d
+load net {FRAME:for:mul#7.itm(1)} -attr vt d
+load net {FRAME:for:mul#7.itm(2)} -attr vt d
+load net {FRAME:for:mul#7.itm(3)} -attr vt d
+load net {FRAME:for:mul#7.itm(4)} -attr vt d
+load net {FRAME:for:mul#7.itm(5)} -attr vt d
+load net {FRAME:for:mul#7.itm(6)} -attr vt d
+load net {FRAME:for:mul#7.itm(7)} -attr vt d
+load net {FRAME:for:mul#7.itm(8)} -attr vt d
+load net {FRAME:for:mul#7.itm(9)} -attr vt d
+load net {FRAME:for:mul#7.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#7.itm} 11 {FRAME:for:mul#7.itm(0)} {FRAME:for:mul#7.itm(1)} {FRAME:for:mul#7.itm(2)} {FRAME:for:mul#7.itm(3)} {FRAME:for:mul#7.itm(4)} {FRAME:for:mul#7.itm(5)} {FRAME:for:mul#7.itm(6)} {FRAME:for:mul#7.itm(7)} {FRAME:for:mul#7.itm(8)} {FRAME:for:mul#7.itm(9)} {FRAME:for:mul#7.itm(10)} -attr xrf 11855 -attr oid 243 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {regs.operator[]#16:mux.itm(0)} -attr vt d
+load net {regs.operator[]#16:mux.itm(1)} -attr vt d
+load net {regs.operator[]#16:mux.itm(2)} -attr vt d
+load net {regs.operator[]#16:mux.itm(3)} -attr vt d
+load net {regs.operator[]#16:mux.itm(4)} -attr vt d
+load net {regs.operator[]#16:mux.itm(5)} -attr vt d
+load net {regs.operator[]#16:mux.itm(6)} -attr vt d
+load net {regs.operator[]#16:mux.itm(7)} -attr vt d
+load net {regs.operator[]#16:mux.itm(8)} -attr vt d
+load net {regs.operator[]#16:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#16:mux.itm} 10 {regs.operator[]#16:mux.itm(0)} {regs.operator[]#16:mux.itm(1)} {regs.operator[]#16:mux.itm(2)} {regs.operator[]#16:mux.itm(3)} {regs.operator[]#16:mux.itm(4)} {regs.operator[]#16:mux.itm(5)} {regs.operator[]#16:mux.itm(6)} {regs.operator[]#16:mux.itm(7)} {regs.operator[]#16:mux.itm(8)} {regs.operator[]#16:mux.itm(9)} -attr xrf 11856 -attr oid 244 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(9)} -attr xrf 11857 -attr oid 245 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr xrf 11858 -attr oid 246 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr xrf 11859 -attr oid 247 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {FRAME:for:mux#7.itm(0)} -attr vt d
+load net {FRAME:for:mux#7.itm(1)} -attr vt d
+load net {FRAME:for:mux#7.itm(2)} -attr vt d
+load net {FRAME:for:mux#7.itm(3)} -attr vt d
+load net {FRAME:for:mux#7.itm(4)} -attr vt d
+load net {FRAME:for:mux#7.itm(5)} -attr vt d
+load net {FRAME:for:mux#7.itm(6)} -attr vt d
+load net {FRAME:for:mux#7.itm(7)} -attr vt d
+load net {FRAME:for:mux#7.itm(8)} -attr vt d
+load net {FRAME:for:mux#7.itm(9)} -attr vt d
+load net {FRAME:for:mux#7.itm(10)} -attr vt d
+load net {FRAME:for:mux#7.itm(11)} -attr vt d
+load net {FRAME:for:mux#7.itm(12)} -attr vt d
+load net {FRAME:for:mux#7.itm(13)} -attr vt d
+load net {FRAME:for:mux#7.itm(14)} -attr vt d
+load net {FRAME:for:mux#7.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#7.itm} 16 {FRAME:for:mux#7.itm(0)} {FRAME:for:mux#7.itm(1)} {FRAME:for:mux#7.itm(2)} {FRAME:for:mux#7.itm(3)} {FRAME:for:mux#7.itm(4)} {FRAME:for:mux#7.itm(5)} {FRAME:for:mux#7.itm(6)} {FRAME:for:mux#7.itm(7)} {FRAME:for:mux#7.itm(8)} {FRAME:for:mux#7.itm(9)} {FRAME:for:mux#7.itm(10)} {FRAME:for:mux#7.itm(11)} {FRAME:for:mux#7.itm(12)} {FRAME:for:mux#7.itm(13)} {FRAME:for:mux#7.itm(14)} {FRAME:for:mux#7.itm(15)} -attr xrf 11860 -attr oid 248 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:exs#21.itm(0)} -attr vt d
+load net {FRAME:for:exs#21.itm(1)} -attr vt d
+load net {FRAME:for:exs#21.itm(2)} -attr vt d
+load net {FRAME:for:exs#21.itm(3)} -attr vt d
+load net {FRAME:for:exs#21.itm(4)} -attr vt d
+load net {FRAME:for:exs#21.itm(5)} -attr vt d
+load net {FRAME:for:exs#21.itm(6)} -attr vt d
+load net {FRAME:for:exs#21.itm(7)} -attr vt d
+load net {FRAME:for:exs#21.itm(8)} -attr vt d
+load net {FRAME:for:exs#21.itm(9)} -attr vt d
+load net {FRAME:for:exs#21.itm(10)} -attr vt d
+load net {FRAME:for:exs#21.itm(11)} -attr vt d
+load net {FRAME:for:exs#21.itm(12)} -attr vt d
+load net {FRAME:for:exs#21.itm(13)} -attr vt d
+load net {FRAME:for:exs#21.itm(14)} -attr vt d
+load net {FRAME:for:exs#21.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#21.itm} 16 {FRAME:for:exs#21.itm(0)} {FRAME:for:exs#21.itm(1)} {FRAME:for:exs#21.itm(2)} {FRAME:for:exs#21.itm(3)} {FRAME:for:exs#21.itm(4)} {FRAME:for:exs#21.itm(5)} {FRAME:for:exs#21.itm(6)} {FRAME:for:exs#21.itm(7)} {FRAME:for:exs#21.itm(8)} {FRAME:for:exs#21.itm(9)} {FRAME:for:exs#21.itm(10)} {FRAME:for:exs#21.itm(11)} {FRAME:for:exs#21.itm(12)} {FRAME:for:exs#21.itm(13)} {FRAME:for:exs#21.itm(14)} {FRAME:for:exs#21.itm(15)} -attr xrf 11861 -attr oid 249 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:slc#1.itm(0)} -attr vt d
+load net {ACC1:slc#1.itm(1)} -attr vt d
+load net {ACC1:slc#1.itm(2)} -attr vt d
+load net {ACC1:slc#1.itm(3)} -attr vt d
+load net {ACC1:slc#1.itm(4)} -attr vt d
+load net {ACC1:slc#1.itm(5)} -attr vt d
+load net {ACC1:slc#1.itm(6)} -attr vt d
+load net {ACC1:slc#1.itm(7)} -attr vt d
+load net {ACC1:slc#1.itm(8)} -attr vt d
+load net {ACC1:slc#1.itm(9)} -attr vt d
+load net {ACC1:slc#1.itm(10)} -attr vt d
+load netBundle {ACC1:slc#1.itm} 11 {ACC1:slc#1.itm(0)} {ACC1:slc#1.itm(1)} {ACC1:slc#1.itm(2)} {ACC1:slc#1.itm(3)} {ACC1:slc#1.itm(4)} {ACC1:slc#1.itm(5)} {ACC1:slc#1.itm(6)} {ACC1:slc#1.itm(7)} {ACC1:slc#1.itm(8)} {ACC1:slc#1.itm(9)} {ACC1:slc#1.itm(10)} -attr xrf 11862 -attr oid 250 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc.itm(0)} -attr vt d
+load net {ACC1:acc.itm(1)} -attr vt d
+load net {ACC1:acc.itm(2)} -attr vt d
+load net {ACC1:acc.itm(3)} -attr vt d
+load net {ACC1:acc.itm(4)} -attr vt d
+load net {ACC1:acc.itm(5)} -attr vt d
+load net {ACC1:acc.itm(6)} -attr vt d
+load net {ACC1:acc.itm(7)} -attr vt d
+load net {ACC1:acc.itm(8)} -attr vt d
+load net {ACC1:acc.itm(9)} -attr vt d
+load net {ACC1:acc.itm(10)} -attr vt d
+load net {ACC1:acc.itm(11)} -attr vt d
+load netBundle {ACC1:acc.itm} 12 {ACC1:acc.itm(0)} {ACC1:acc.itm(1)} {ACC1:acc.itm(2)} {ACC1:acc.itm(3)} {ACC1:acc.itm(4)} {ACC1:acc.itm(5)} {ACC1:acc.itm(6)} {ACC1:acc.itm(7)} {ACC1:acc.itm(8)} {ACC1:acc.itm(9)} {ACC1:acc.itm(10)} {ACC1:acc.itm(11)} -attr xrf 11863 -attr oid 251 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {conc#168.itm(0)} -attr vt d
+load net {conc#168.itm(1)} -attr vt d
+load net {conc#168.itm(2)} -attr vt d
+load net {conc#168.itm(3)} -attr vt d
+load net {conc#168.itm(4)} -attr vt d
+load net {conc#168.itm(5)} -attr vt d
+load net {conc#168.itm(6)} -attr vt d
+load net {conc#168.itm(7)} -attr vt d
+load net {conc#168.itm(8)} -attr vt d
+load net {conc#168.itm(9)} -attr vt d
+load net {conc#168.itm(10)} -attr vt d
+load netBundle {conc#168.itm} 11 {conc#168.itm(0)} {conc#168.itm(1)} {conc#168.itm(2)} {conc#168.itm(3)} {conc#168.itm(4)} {conc#168.itm(5)} {conc#168.itm(6)} {conc#168.itm(7)} {conc#168.itm(8)} {conc#168.itm(9)} {conc#168.itm(10)} -attr xrf 11864 -attr oid 252 -attr vt d -attr @path {/sobel/sobel:core/conc#168.itm}
+load net {ACC1:not#15.itm(0)} -attr vt d
+load net {ACC1:not#15.itm(1)} -attr vt d
+load net {ACC1:not#15.itm(2)} -attr vt d
+load net {ACC1:not#15.itm(3)} -attr vt d
+load net {ACC1:not#15.itm(4)} -attr vt d
+load net {ACC1:not#15.itm(5)} -attr vt d
+load net {ACC1:not#15.itm(6)} -attr vt d
+load net {ACC1:not#15.itm(7)} -attr vt d
+load net {ACC1:not#15.itm(8)} -attr vt d
+load net {ACC1:not#15.itm(9)} -attr vt d
+load netBundle {ACC1:not#15.itm} 10 {ACC1:not#15.itm(0)} {ACC1:not#15.itm(1)} {ACC1:not#15.itm(2)} {ACC1:not#15.itm(3)} {ACC1:not#15.itm(4)} {ACC1:not#15.itm(5)} {ACC1:not#15.itm(6)} {ACC1:not#15.itm(7)} {ACC1:not#15.itm(8)} {ACC1:not#15.itm(9)} -attr xrf 11865 -attr oid 253 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {slc(regs.regs(0).sva#5).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#5).itm} 10 {slc(regs.regs(0).sva#5).itm(0)} {slc(regs.regs(0).sva#5).itm(1)} {slc(regs.regs(0).sva#5).itm(2)} {slc(regs.regs(0).sva#5).itm(3)} {slc(regs.regs(0).sva#5).itm(4)} {slc(regs.regs(0).sva#5).itm(5)} {slc(regs.regs(0).sva#5).itm(6)} {slc(regs.regs(0).sva#5).itm(7)} {slc(regs.regs(0).sva#5).itm(8)} {slc(regs.regs(0).sva#5).itm(9)} -attr xrf 11866 -attr oid 254 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {conc#169.itm(0)} -attr vt d
+load net {conc#169.itm(1)} -attr vt d
+load net {conc#169.itm(2)} -attr vt d
+load net {conc#169.itm(3)} -attr vt d
+load net {conc#169.itm(4)} -attr vt d
+load net {conc#169.itm(5)} -attr vt d
+load net {conc#169.itm(6)} -attr vt d
+load net {conc#169.itm(7)} -attr vt d
+load net {conc#169.itm(8)} -attr vt d
+load net {conc#169.itm(9)} -attr vt d
+load net {conc#169.itm(10)} -attr vt d
+load netBundle {conc#169.itm} 11 {conc#169.itm(0)} {conc#169.itm(1)} {conc#169.itm(2)} {conc#169.itm(3)} {conc#169.itm(4)} {conc#169.itm(5)} {conc#169.itm(6)} {conc#169.itm(7)} {conc#169.itm(8)} {conc#169.itm(9)} {conc#169.itm(10)} -attr xrf 11867 -attr oid 255 -attr vt d -attr @path {/sobel/sobel:core/conc#169.itm}
+load net {slc(regs.regs(1).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#4.itm} 10 {slc(regs.regs(1).sva)#4.itm(0)} {slc(regs.regs(1).sva)#4.itm(1)} {slc(regs.regs(1).sva)#4.itm(2)} {slc(regs.regs(1).sva)#4.itm(3)} {slc(regs.regs(1).sva)#4.itm(4)} {slc(regs.regs(1).sva)#4.itm(5)} {slc(regs.regs(1).sva)#4.itm(6)} {slc(regs.regs(1).sva)#4.itm(7)} {slc(regs.regs(1).sva)#4.itm(8)} {slc(regs.regs(1).sva)#4.itm(9)} -attr xrf 11868 -attr oid 256 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {FRAME:for:mul#1.itm(0)} -attr vt d
+load net {FRAME:for:mul#1.itm(1)} -attr vt d
+load net {FRAME:for:mul#1.itm(2)} -attr vt d
+load net {FRAME:for:mul#1.itm(3)} -attr vt d
+load net {FRAME:for:mul#1.itm(4)} -attr vt d
+load net {FRAME:for:mul#1.itm(5)} -attr vt d
+load net {FRAME:for:mul#1.itm(6)} -attr vt d
+load net {FRAME:for:mul#1.itm(7)} -attr vt d
+load net {FRAME:for:mul#1.itm(8)} -attr vt d
+load net {FRAME:for:mul#1.itm(9)} -attr vt d
+load net {FRAME:for:mul#1.itm(10)} -attr vt d
+load net {FRAME:for:mul#1.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul#1.itm} 12 {FRAME:for:mul#1.itm(0)} {FRAME:for:mul#1.itm(1)} {FRAME:for:mul#1.itm(2)} {FRAME:for:mul#1.itm(3)} {FRAME:for:mul#1.itm(4)} {FRAME:for:mul#1.itm(5)} {FRAME:for:mul#1.itm(6)} {FRAME:for:mul#1.itm(7)} {FRAME:for:mul#1.itm(8)} {FRAME:for:mul#1.itm(9)} {FRAME:for:mul#1.itm(10)} {FRAME:for:mul#1.itm(11)} -attr xrf 11869 -attr oid 257 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {regs.operator[]#10:mux.itm(0)} -attr vt d
+load net {regs.operator[]#10:mux.itm(1)} -attr vt d
+load net {regs.operator[]#10:mux.itm(2)} -attr vt d
+load net {regs.operator[]#10:mux.itm(3)} -attr vt d
+load net {regs.operator[]#10:mux.itm(4)} -attr vt d
+load net {regs.operator[]#10:mux.itm(5)} -attr vt d
+load net {regs.operator[]#10:mux.itm(6)} -attr vt d
+load net {regs.operator[]#10:mux.itm(7)} -attr vt d
+load net {regs.operator[]#10:mux.itm(8)} -attr vt d
+load net {regs.operator[]#10:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#10:mux.itm} 10 {regs.operator[]#10:mux.itm(0)} {regs.operator[]#10:mux.itm(1)} {regs.operator[]#10:mux.itm(2)} {regs.operator[]#10:mux.itm(3)} {regs.operator[]#10:mux.itm(4)} {regs.operator[]#10:mux.itm(5)} {regs.operator[]#10:mux.itm(6)} {regs.operator[]#10:mux.itm(7)} {regs.operator[]#10:mux.itm(8)} {regs.operator[]#10:mux.itm(9)} -attr xrf 11870 -attr oid 258 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(9)} -attr xrf 11871 -attr oid 259 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr xrf 11872 -attr oid 260 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#7.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#7.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(9)} -attr xrf 11873 -attr oid 261 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {conc#170.itm(0)} -attr vt d
+load net {conc#170.itm(1)} -attr vt d
+load netBundle {conc#170.itm} 2 {conc#170.itm(0)} {conc#170.itm(1)} -attr xrf 11874 -attr oid 262 -attr vt d -attr @path {/sobel/sobel:core/conc#170.itm}
+load net {FRAME:for:mux#6.itm(0)} -attr vt d
+load net {FRAME:for:mux#6.itm(1)} -attr vt d
+load net {FRAME:for:mux#6.itm(2)} -attr vt d
+load net {FRAME:for:mux#6.itm(3)} -attr vt d
+load net {FRAME:for:mux#6.itm(4)} -attr vt d
+load net {FRAME:for:mux#6.itm(5)} -attr vt d
+load net {FRAME:for:mux#6.itm(6)} -attr vt d
+load net {FRAME:for:mux#6.itm(7)} -attr vt d
+load net {FRAME:for:mux#6.itm(8)} -attr vt d
+load net {FRAME:for:mux#6.itm(9)} -attr vt d
+load net {FRAME:for:mux#6.itm(10)} -attr vt d
+load net {FRAME:for:mux#6.itm(11)} -attr vt d
+load net {FRAME:for:mux#6.itm(12)} -attr vt d
+load net {FRAME:for:mux#6.itm(13)} -attr vt d
+load net {FRAME:for:mux#6.itm(14)} -attr vt d
+load net {FRAME:for:mux#6.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#6.itm} 16 {FRAME:for:mux#6.itm(0)} {FRAME:for:mux#6.itm(1)} {FRAME:for:mux#6.itm(2)} {FRAME:for:mux#6.itm(3)} {FRAME:for:mux#6.itm(4)} {FRAME:for:mux#6.itm(5)} {FRAME:for:mux#6.itm(6)} {FRAME:for:mux#6.itm(7)} {FRAME:for:mux#6.itm(8)} {FRAME:for:mux#6.itm(9)} {FRAME:for:mux#6.itm(10)} {FRAME:for:mux#6.itm(11)} {FRAME:for:mux#6.itm(12)} {FRAME:for:mux#6.itm(13)} {FRAME:for:mux#6.itm(14)} {FRAME:for:mux#6.itm(15)} -attr xrf 11875 -attr oid 263 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:exs#23.itm(0)} -attr vt d
+load net {FRAME:for:exs#23.itm(1)} -attr vt d
+load net {FRAME:for:exs#23.itm(2)} -attr vt d
+load net {FRAME:for:exs#23.itm(3)} -attr vt d
+load net {FRAME:for:exs#23.itm(4)} -attr vt d
+load net {FRAME:for:exs#23.itm(5)} -attr vt d
+load net {FRAME:for:exs#23.itm(6)} -attr vt d
+load net {FRAME:for:exs#23.itm(7)} -attr vt d
+load net {FRAME:for:exs#23.itm(8)} -attr vt d
+load net {FRAME:for:exs#23.itm(9)} -attr vt d
+load net {FRAME:for:exs#23.itm(10)} -attr vt d
+load net {FRAME:for:exs#23.itm(11)} -attr vt d
+load net {FRAME:for:exs#23.itm(12)} -attr vt d
+load net {FRAME:for:exs#23.itm(13)} -attr vt d
+load net {FRAME:for:exs#23.itm(14)} -attr vt d
+load net {FRAME:for:exs#23.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#23.itm} 16 {FRAME:for:exs#23.itm(0)} {FRAME:for:exs#23.itm(1)} {FRAME:for:exs#23.itm(2)} {FRAME:for:exs#23.itm(3)} {FRAME:for:exs#23.itm(4)} {FRAME:for:exs#23.itm(5)} {FRAME:for:exs#23.itm(6)} {FRAME:for:exs#23.itm(7)} {FRAME:for:exs#23.itm(8)} {FRAME:for:exs#23.itm(9)} {FRAME:for:exs#23.itm(10)} {FRAME:for:exs#23.itm(11)} {FRAME:for:exs#23.itm(12)} {FRAME:for:exs#23.itm(13)} {FRAME:for:exs#23.itm(14)} {FRAME:for:exs#23.itm(15)} -attr xrf 11876 -attr oid 264 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:slc#3.itm(0)} -attr vt d
+load net {ACC1:slc#3.itm(1)} -attr vt d
+load net {ACC1:slc#3.itm(2)} -attr vt d
+load net {ACC1:slc#3.itm(3)} -attr vt d
+load net {ACC1:slc#3.itm(4)} -attr vt d
+load net {ACC1:slc#3.itm(5)} -attr vt d
+load net {ACC1:slc#3.itm(6)} -attr vt d
+load net {ACC1:slc#3.itm(7)} -attr vt d
+load net {ACC1:slc#3.itm(8)} -attr vt d
+load net {ACC1:slc#3.itm(9)} -attr vt d
+load net {ACC1:slc#3.itm(10)} -attr vt d
+load netBundle {ACC1:slc#3.itm} 11 {ACC1:slc#3.itm(0)} {ACC1:slc#3.itm(1)} {ACC1:slc#3.itm(2)} {ACC1:slc#3.itm(3)} {ACC1:slc#3.itm(4)} {ACC1:slc#3.itm(5)} {ACC1:slc#3.itm(6)} {ACC1:slc#3.itm(7)} {ACC1:slc#3.itm(8)} {ACC1:slc#3.itm(9)} {ACC1:slc#3.itm(10)} -attr xrf 11877 -attr oid 265 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#47.itm(0)} -attr vt d
+load net {ACC1:acc#47.itm(1)} -attr vt d
+load net {ACC1:acc#47.itm(2)} -attr vt d
+load net {ACC1:acc#47.itm(3)} -attr vt d
+load net {ACC1:acc#47.itm(4)} -attr vt d
+load net {ACC1:acc#47.itm(5)} -attr vt d
+load net {ACC1:acc#47.itm(6)} -attr vt d
+load net {ACC1:acc#47.itm(7)} -attr vt d
+load net {ACC1:acc#47.itm(8)} -attr vt d
+load net {ACC1:acc#47.itm(9)} -attr vt d
+load net {ACC1:acc#47.itm(10)} -attr vt d
+load net {ACC1:acc#47.itm(11)} -attr vt d
+load netBundle {ACC1:acc#47.itm} 12 {ACC1:acc#47.itm(0)} {ACC1:acc#47.itm(1)} {ACC1:acc#47.itm(2)} {ACC1:acc#47.itm(3)} {ACC1:acc#47.itm(4)} {ACC1:acc#47.itm(5)} {ACC1:acc#47.itm(6)} {ACC1:acc#47.itm(7)} {ACC1:acc#47.itm(8)} {ACC1:acc#47.itm(9)} {ACC1:acc#47.itm(10)} {ACC1:acc#47.itm(11)} -attr xrf 11878 -attr oid 266 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {conc#171.itm(0)} -attr vt d
+load net {conc#171.itm(1)} -attr vt d
+load net {conc#171.itm(2)} -attr vt d
+load net {conc#171.itm(3)} -attr vt d
+load net {conc#171.itm(4)} -attr vt d
+load net {conc#171.itm(5)} -attr vt d
+load net {conc#171.itm(6)} -attr vt d
+load net {conc#171.itm(7)} -attr vt d
+load net {conc#171.itm(8)} -attr vt d
+load net {conc#171.itm(9)} -attr vt d
+load net {conc#171.itm(10)} -attr vt d
+load netBundle {conc#171.itm} 11 {conc#171.itm(0)} {conc#171.itm(1)} {conc#171.itm(2)} {conc#171.itm(3)} {conc#171.itm(4)} {conc#171.itm(5)} {conc#171.itm(6)} {conc#171.itm(7)} {conc#171.itm(8)} {conc#171.itm(9)} {conc#171.itm(10)} -attr xrf 11879 -attr oid 267 -attr vt d -attr @path {/sobel/sobel:core/conc#171.itm}
+load net {ACC1:not#12.itm(0)} -attr vt d
+load net {ACC1:not#12.itm(1)} -attr vt d
+load net {ACC1:not#12.itm(2)} -attr vt d
+load net {ACC1:not#12.itm(3)} -attr vt d
+load net {ACC1:not#12.itm(4)} -attr vt d
+load net {ACC1:not#12.itm(5)} -attr vt d
+load net {ACC1:not#12.itm(6)} -attr vt d
+load net {ACC1:not#12.itm(7)} -attr vt d
+load net {ACC1:not#12.itm(8)} -attr vt d
+load net {ACC1:not#12.itm(9)} -attr vt d
+load netBundle {ACC1:not#12.itm} 10 {ACC1:not#12.itm(0)} {ACC1:not#12.itm(1)} {ACC1:not#12.itm(2)} {ACC1:not#12.itm(3)} {ACC1:not#12.itm(4)} {ACC1:not#12.itm(5)} {ACC1:not#12.itm(6)} {ACC1:not#12.itm(7)} {ACC1:not#12.itm(8)} {ACC1:not#12.itm(9)} -attr xrf 11880 -attr oid 268 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {slc(regs.regs(0).sva#3).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#3).itm} 10 {slc(regs.regs(0).sva#3).itm(0)} {slc(regs.regs(0).sva#3).itm(1)} {slc(regs.regs(0).sva#3).itm(2)} {slc(regs.regs(0).sva#3).itm(3)} {slc(regs.regs(0).sva#3).itm(4)} {slc(regs.regs(0).sva#3).itm(5)} {slc(regs.regs(0).sva#3).itm(6)} {slc(regs.regs(0).sva#3).itm(7)} {slc(regs.regs(0).sva#3).itm(8)} {slc(regs.regs(0).sva#3).itm(9)} -attr xrf 11881 -attr oid 269 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {conc#172.itm(0)} -attr vt d
+load net {conc#172.itm(1)} -attr vt d
+load net {conc#172.itm(2)} -attr vt d
+load net {conc#172.itm(3)} -attr vt d
+load net {conc#172.itm(4)} -attr vt d
+load net {conc#172.itm(5)} -attr vt d
+load net {conc#172.itm(6)} -attr vt d
+load net {conc#172.itm(7)} -attr vt d
+load net {conc#172.itm(8)} -attr vt d
+load net {conc#172.itm(9)} -attr vt d
+load net {conc#172.itm(10)} -attr vt d
+load netBundle {conc#172.itm} 11 {conc#172.itm(0)} {conc#172.itm(1)} {conc#172.itm(2)} {conc#172.itm(3)} {conc#172.itm(4)} {conc#172.itm(5)} {conc#172.itm(6)} {conc#172.itm(7)} {conc#172.itm(8)} {conc#172.itm(9)} {conc#172.itm(10)} -attr xrf 11882 -attr oid 270 -attr vt d -attr @path {/sobel/sobel:core/conc#172.itm}
+load net {slc(regs.regs(1).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#2.itm} 10 {slc(regs.regs(1).sva)#2.itm(0)} {slc(regs.regs(1).sva)#2.itm(1)} {slc(regs.regs(1).sva)#2.itm(2)} {slc(regs.regs(1).sva)#2.itm(3)} {slc(regs.regs(1).sva)#2.itm(4)} {slc(regs.regs(1).sva)#2.itm(5)} {slc(regs.regs(1).sva)#2.itm(6)} {slc(regs.regs(1).sva)#2.itm(7)} {slc(regs.regs(1).sva)#2.itm(8)} {slc(regs.regs(1).sva)#2.itm(9)} -attr xrf 11883 -attr oid 271 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {FRAME:for:mul#6.itm(0)} -attr vt d
+load net {FRAME:for:mul#6.itm(1)} -attr vt d
+load net {FRAME:for:mul#6.itm(2)} -attr vt d
+load net {FRAME:for:mul#6.itm(3)} -attr vt d
+load net {FRAME:for:mul#6.itm(4)} -attr vt d
+load net {FRAME:for:mul#6.itm(5)} -attr vt d
+load net {FRAME:for:mul#6.itm(6)} -attr vt d
+load net {FRAME:for:mul#6.itm(7)} -attr vt d
+load net {FRAME:for:mul#6.itm(8)} -attr vt d
+load net {FRAME:for:mul#6.itm(9)} -attr vt d
+load net {FRAME:for:mul#6.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#6.itm} 11 {FRAME:for:mul#6.itm(0)} {FRAME:for:mul#6.itm(1)} {FRAME:for:mul#6.itm(2)} {FRAME:for:mul#6.itm(3)} {FRAME:for:mul#6.itm(4)} {FRAME:for:mul#6.itm(5)} {FRAME:for:mul#6.itm(6)} {FRAME:for:mul#6.itm(7)} {FRAME:for:mul#6.itm(8)} {FRAME:for:mul#6.itm(9)} {FRAME:for:mul#6.itm(10)} -attr xrf 11884 -attr oid 272 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {regs.operator[]#15:mux.itm(0)} -attr vt d
+load net {regs.operator[]#15:mux.itm(1)} -attr vt d
+load net {regs.operator[]#15:mux.itm(2)} -attr vt d
+load net {regs.operator[]#15:mux.itm(3)} -attr vt d
+load net {regs.operator[]#15:mux.itm(4)} -attr vt d
+load net {regs.operator[]#15:mux.itm(5)} -attr vt d
+load net {regs.operator[]#15:mux.itm(6)} -attr vt d
+load net {regs.operator[]#15:mux.itm(7)} -attr vt d
+load net {regs.operator[]#15:mux.itm(8)} -attr vt d
+load net {regs.operator[]#15:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#15:mux.itm} 10 {regs.operator[]#15:mux.itm(0)} {regs.operator[]#15:mux.itm(1)} {regs.operator[]#15:mux.itm(2)} {regs.operator[]#15:mux.itm(3)} {regs.operator[]#15:mux.itm(4)} {regs.operator[]#15:mux.itm(5)} {regs.operator[]#15:mux.itm(6)} {regs.operator[]#15:mux.itm(7)} {regs.operator[]#15:mux.itm(8)} {regs.operator[]#15:mux.itm(9)} -attr xrf 11885 -attr oid 273 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(9)} -attr xrf 11886 -attr oid 274 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr xrf 11887 -attr oid 275 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr xrf 11888 -attr oid 276 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {FRAME:for:mux#5.itm(0)} -attr vt d
+load net {FRAME:for:mux#5.itm(1)} -attr vt d
+load net {FRAME:for:mux#5.itm(2)} -attr vt d
+load net {FRAME:for:mux#5.itm(3)} -attr vt d
+load net {FRAME:for:mux#5.itm(4)} -attr vt d
+load net {FRAME:for:mux#5.itm(5)} -attr vt d
+load net {FRAME:for:mux#5.itm(6)} -attr vt d
+load net {FRAME:for:mux#5.itm(7)} -attr vt d
+load net {FRAME:for:mux#5.itm(8)} -attr vt d
+load net {FRAME:for:mux#5.itm(9)} -attr vt d
+load net {FRAME:for:mux#5.itm(10)} -attr vt d
+load net {FRAME:for:mux#5.itm(11)} -attr vt d
+load net {FRAME:for:mux#5.itm(12)} -attr vt d
+load net {FRAME:for:mux#5.itm(13)} -attr vt d
+load net {FRAME:for:mux#5.itm(14)} -attr vt d
+load net {FRAME:for:mux#5.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#5.itm} 16 {FRAME:for:mux#5.itm(0)} {FRAME:for:mux#5.itm(1)} {FRAME:for:mux#5.itm(2)} {FRAME:for:mux#5.itm(3)} {FRAME:for:mux#5.itm(4)} {FRAME:for:mux#5.itm(5)} {FRAME:for:mux#5.itm(6)} {FRAME:for:mux#5.itm(7)} {FRAME:for:mux#5.itm(8)} {FRAME:for:mux#5.itm(9)} {FRAME:for:mux#5.itm(10)} {FRAME:for:mux#5.itm(11)} {FRAME:for:mux#5.itm(12)} {FRAME:for:mux#5.itm(13)} {FRAME:for:mux#5.itm(14)} {FRAME:for:mux#5.itm(15)} -attr xrf 11889 -attr oid 277 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:exs#20.itm(0)} -attr vt d
+load net {FRAME:for:exs#20.itm(1)} -attr vt d
+load net {FRAME:for:exs#20.itm(2)} -attr vt d
+load net {FRAME:for:exs#20.itm(3)} -attr vt d
+load net {FRAME:for:exs#20.itm(4)} -attr vt d
+load net {FRAME:for:exs#20.itm(5)} -attr vt d
+load net {FRAME:for:exs#20.itm(6)} -attr vt d
+load net {FRAME:for:exs#20.itm(7)} -attr vt d
+load net {FRAME:for:exs#20.itm(8)} -attr vt d
+load net {FRAME:for:exs#20.itm(9)} -attr vt d
+load net {FRAME:for:exs#20.itm(10)} -attr vt d
+load net {FRAME:for:exs#20.itm(11)} -attr vt d
+load net {FRAME:for:exs#20.itm(12)} -attr vt d
+load net {FRAME:for:exs#20.itm(13)} -attr vt d
+load net {FRAME:for:exs#20.itm(14)} -attr vt d
+load net {FRAME:for:exs#20.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#20.itm} 16 {FRAME:for:exs#20.itm(0)} {FRAME:for:exs#20.itm(1)} {FRAME:for:exs#20.itm(2)} {FRAME:for:exs#20.itm(3)} {FRAME:for:exs#20.itm(4)} {FRAME:for:exs#20.itm(5)} {FRAME:for:exs#20.itm(6)} {FRAME:for:exs#20.itm(7)} {FRAME:for:exs#20.itm(8)} {FRAME:for:exs#20.itm(9)} {FRAME:for:exs#20.itm(10)} {FRAME:for:exs#20.itm(11)} {FRAME:for:exs#20.itm(12)} {FRAME:for:exs#20.itm(13)} {FRAME:for:exs#20.itm(14)} {FRAME:for:exs#20.itm(15)} -attr xrf 11890 -attr oid 278 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:slc.itm(0)} -attr vt d
+load net {ACC1:slc.itm(1)} -attr vt d
+load net {ACC1:slc.itm(2)} -attr vt d
+load net {ACC1:slc.itm(3)} -attr vt d
+load net {ACC1:slc.itm(4)} -attr vt d
+load net {ACC1:slc.itm(5)} -attr vt d
+load net {ACC1:slc.itm(6)} -attr vt d
+load net {ACC1:slc.itm(7)} -attr vt d
+load net {ACC1:slc.itm(8)} -attr vt d
+load net {ACC1:slc.itm(9)} -attr vt d
+load net {ACC1:slc.itm(10)} -attr vt d
+load netBundle {ACC1:slc.itm} 11 {ACC1:slc.itm(0)} {ACC1:slc.itm(1)} {ACC1:slc.itm(2)} {ACC1:slc.itm(3)} {ACC1:slc.itm(4)} {ACC1:slc.itm(5)} {ACC1:slc.itm(6)} {ACC1:slc.itm(7)} {ACC1:slc.itm(8)} {ACC1:slc.itm(9)} {ACC1:slc.itm(10)} -attr xrf 11891 -attr oid 279 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#45.itm(0)} -attr vt d
+load net {ACC1:acc#45.itm(1)} -attr vt d
+load net {ACC1:acc#45.itm(2)} -attr vt d
+load net {ACC1:acc#45.itm(3)} -attr vt d
+load net {ACC1:acc#45.itm(4)} -attr vt d
+load net {ACC1:acc#45.itm(5)} -attr vt d
+load net {ACC1:acc#45.itm(6)} -attr vt d
+load net {ACC1:acc#45.itm(7)} -attr vt d
+load net {ACC1:acc#45.itm(8)} -attr vt d
+load net {ACC1:acc#45.itm(9)} -attr vt d
+load net {ACC1:acc#45.itm(10)} -attr vt d
+load net {ACC1:acc#45.itm(11)} -attr vt d
+load netBundle {ACC1:acc#45.itm} 12 {ACC1:acc#45.itm(0)} {ACC1:acc#45.itm(1)} {ACC1:acc#45.itm(2)} {ACC1:acc#45.itm(3)} {ACC1:acc#45.itm(4)} {ACC1:acc#45.itm(5)} {ACC1:acc#45.itm(6)} {ACC1:acc#45.itm(7)} {ACC1:acc#45.itm(8)} {ACC1:acc#45.itm(9)} {ACC1:acc#45.itm(10)} {ACC1:acc#45.itm(11)} -attr xrf 11892 -attr oid 280 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {conc#173.itm(0)} -attr vt d
+load net {conc#173.itm(1)} -attr vt d
+load net {conc#173.itm(2)} -attr vt d
+load net {conc#173.itm(3)} -attr vt d
+load net {conc#173.itm(4)} -attr vt d
+load net {conc#173.itm(5)} -attr vt d
+load net {conc#173.itm(6)} -attr vt d
+load net {conc#173.itm(7)} -attr vt d
+load net {conc#173.itm(8)} -attr vt d
+load net {conc#173.itm(9)} -attr vt d
+load net {conc#173.itm(10)} -attr vt d
+load netBundle {conc#173.itm} 11 {conc#173.itm(0)} {conc#173.itm(1)} {conc#173.itm(2)} {conc#173.itm(3)} {conc#173.itm(4)} {conc#173.itm(5)} {conc#173.itm(6)} {conc#173.itm(7)} {conc#173.itm(8)} {conc#173.itm(9)} {conc#173.itm(10)} -attr xrf 11893 -attr oid 281 -attr vt d -attr @path {/sobel/sobel:core/conc#173.itm}
+load net {ACC1:not.itm(0)} -attr vt d
+load net {ACC1:not.itm(1)} -attr vt d
+load net {ACC1:not.itm(2)} -attr vt d
+load net {ACC1:not.itm(3)} -attr vt d
+load net {ACC1:not.itm(4)} -attr vt d
+load net {ACC1:not.itm(5)} -attr vt d
+load net {ACC1:not.itm(6)} -attr vt d
+load net {ACC1:not.itm(7)} -attr vt d
+load net {ACC1:not.itm(8)} -attr vt d
+load net {ACC1:not.itm(9)} -attr vt d
+load netBundle {ACC1:not.itm} 10 {ACC1:not.itm(0)} {ACC1:not.itm(1)} {ACC1:not.itm(2)} {ACC1:not.itm(3)} {ACC1:not.itm(4)} {ACC1:not.itm(5)} {ACC1:not.itm(6)} {ACC1:not.itm(7)} {ACC1:not.itm(8)} {ACC1:not.itm(9)} -attr xrf 11894 -attr oid 282 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {slc(regs.regs(0).sva#6).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#6).itm} 10 {slc(regs.regs(0).sva#6).itm(0)} {slc(regs.regs(0).sva#6).itm(1)} {slc(regs.regs(0).sva#6).itm(2)} {slc(regs.regs(0).sva#6).itm(3)} {slc(regs.regs(0).sva#6).itm(4)} {slc(regs.regs(0).sva#6).itm(5)} {slc(regs.regs(0).sva#6).itm(6)} {slc(regs.regs(0).sva#6).itm(7)} {slc(regs.regs(0).sva#6).itm(8)} {slc(regs.regs(0).sva#6).itm(9)} -attr xrf 11895 -attr oid 283 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {conc#174.itm(0)} -attr vt d
+load net {conc#174.itm(1)} -attr vt d
+load net {conc#174.itm(2)} -attr vt d
+load net {conc#174.itm(3)} -attr vt d
+load net {conc#174.itm(4)} -attr vt d
+load net {conc#174.itm(5)} -attr vt d
+load net {conc#174.itm(6)} -attr vt d
+load net {conc#174.itm(7)} -attr vt d
+load net {conc#174.itm(8)} -attr vt d
+load net {conc#174.itm(9)} -attr vt d
+load net {conc#174.itm(10)} -attr vt d
+load netBundle {conc#174.itm} 11 {conc#174.itm(0)} {conc#174.itm(1)} {conc#174.itm(2)} {conc#174.itm(3)} {conc#174.itm(4)} {conc#174.itm(5)} {conc#174.itm(6)} {conc#174.itm(7)} {conc#174.itm(8)} {conc#174.itm(9)} {conc#174.itm(10)} -attr xrf 11896 -attr oid 284 -attr vt d -attr @path {/sobel/sobel:core/conc#174.itm}
+load net {slc(regs.regs(1).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#5.itm} 10 {slc(regs.regs(1).sva)#5.itm(0)} {slc(regs.regs(1).sva)#5.itm(1)} {slc(regs.regs(1).sva)#5.itm(2)} {slc(regs.regs(1).sva)#5.itm(3)} {slc(regs.regs(1).sva)#5.itm(4)} {slc(regs.regs(1).sva)#5.itm(5)} {slc(regs.regs(1).sva)#5.itm(6)} {slc(regs.regs(1).sva)#5.itm(7)} {slc(regs.regs(1).sva)#5.itm(8)} {slc(regs.regs(1).sva)#5.itm(9)} -attr xrf 11897 -attr oid 285 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {FRAME:for:mul.itm(0)} -attr vt d
+load net {FRAME:for:mul.itm(1)} -attr vt d
+load net {FRAME:for:mul.itm(2)} -attr vt d
+load net {FRAME:for:mul.itm(3)} -attr vt d
+load net {FRAME:for:mul.itm(4)} -attr vt d
+load net {FRAME:for:mul.itm(5)} -attr vt d
+load net {FRAME:for:mul.itm(6)} -attr vt d
+load net {FRAME:for:mul.itm(7)} -attr vt d
+load net {FRAME:for:mul.itm(8)} -attr vt d
+load net {FRAME:for:mul.itm(9)} -attr vt d
+load net {FRAME:for:mul.itm(10)} -attr vt d
+load net {FRAME:for:mul.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul.itm} 12 {FRAME:for:mul.itm(0)} {FRAME:for:mul.itm(1)} {FRAME:for:mul.itm(2)} {FRAME:for:mul.itm(3)} {FRAME:for:mul.itm(4)} {FRAME:for:mul.itm(5)} {FRAME:for:mul.itm(6)} {FRAME:for:mul.itm(7)} {FRAME:for:mul.itm(8)} {FRAME:for:mul.itm(9)} {FRAME:for:mul.itm(10)} {FRAME:for:mul.itm(11)} -attr xrf 11898 -attr oid 286 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {regs.operator[]#9:mux.itm(0)} -attr vt d
+load net {regs.operator[]#9:mux.itm(1)} -attr vt d
+load net {regs.operator[]#9:mux.itm(2)} -attr vt d
+load net {regs.operator[]#9:mux.itm(3)} -attr vt d
+load net {regs.operator[]#9:mux.itm(4)} -attr vt d
+load net {regs.operator[]#9:mux.itm(5)} -attr vt d
+load net {regs.operator[]#9:mux.itm(6)} -attr vt d
+load net {regs.operator[]#9:mux.itm(7)} -attr vt d
+load net {regs.operator[]#9:mux.itm(8)} -attr vt d
+load net {regs.operator[]#9:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#9:mux.itm} 10 {regs.operator[]#9:mux.itm(0)} {regs.operator[]#9:mux.itm(1)} {regs.operator[]#9:mux.itm(2)} {regs.operator[]#9:mux.itm(3)} {regs.operator[]#9:mux.itm(4)} {regs.operator[]#9:mux.itm(5)} {regs.operator[]#9:mux.itm(6)} {regs.operator[]#9:mux.itm(7)} {regs.operator[]#9:mux.itm(8)} {regs.operator[]#9:mux.itm(9)} -attr xrf 11899 -attr oid 287 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(9)} -attr xrf 11900 -attr oid 288 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr xrf 11901 -attr oid 289 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#8.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#8.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(9)} -attr xrf 11902 -attr oid 290 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {conc#175.itm(0)} -attr vt d
+load net {conc#175.itm(1)} -attr vt d
+load netBundle {conc#175.itm} 2 {conc#175.itm(0)} {conc#175.itm(1)} -attr xrf 11903 -attr oid 291 -attr vt d -attr @path {/sobel/sobel:core/conc#175.itm}
+load net {clk} -attr xrf 11904 -attr oid 292
+load net {clk} -port {clk} -attr xrf 11905 -attr oid 293
+load net {en} -attr xrf 11906 -attr oid 294
+load net {en} -port {en} -attr xrf 11907 -attr oid 295
+load net {arst_n} -attr xrf 11908 -attr oid 296
+load net {arst_n} -port {arst_n} -attr xrf 11909 -attr oid 297
+load net {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 11910 -attr oid 298 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(0)} -port {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -port {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -port {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -port {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -port {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -port {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -port {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -port {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -port {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -port {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -port {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -port {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -port {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -port {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -port {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -port {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -port {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -port {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -port {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -port {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -port {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -port {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -port {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -port {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -port {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -port {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -port {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -port {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -port {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -port {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -port {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -port {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -port {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -port {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -port {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -port {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -port {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -port {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -port {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -port {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -port {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -port {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -port {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -port {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -port {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -port {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -port {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -port {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -port {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -port {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -port {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -port {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -port {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -port {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -port {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -port {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -port {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -port {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -port {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -port {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -port {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -port {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -port {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -port {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -port {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -port {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -port {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -port {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -port {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -port {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -port {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -port {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -port {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -port {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -port {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -port {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -port {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -port {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -port {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -port {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -port {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -port {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -port {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -port {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -port {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -port {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -port {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -port {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -port {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -port {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 11911 -attr oid 299 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d} 30 {vout:rsc:mgc_out_stdreg.d(0)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(29)} -attr xrf 11912 -attr oid 300 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -port {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -port {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -port {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -port {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -port {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -port {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -port {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -port {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -port {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -port {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -port {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -port {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -port {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -port {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -port {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -port {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -port {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -port {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -port {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -port {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -port {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -port {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -port {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -port {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -port {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -port {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -port {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -port {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -port {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -port {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:acc#36" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 11913 -attr oid 301 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {FRAME:slc(red)#10.itm#1(0)} -pin  "FRAME:acc#36" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(red)#10.itm#1}
+load net {FRAME:slc(red)#10.itm#1(1)} -pin  "FRAME:acc#36" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(red)#10.itm#1}
+load net {FRAME:slc(red)#10.itm#1(2)} -pin  "FRAME:acc#36" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(red)#10.itm#1}
+load net {FRAME:slc(red)#10.itm#1(3)} -pin  "FRAME:acc#36" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(red)#10.itm#1}
+load net {FRAME:slc(red)#10.itm#1(4)} -pin  "FRAME:acc#36" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(red)#10.itm#1}
+load net {FRAME:slc(red)#10.itm#1(5)} -pin  "FRAME:acc#36" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(red)#10.itm#1}
+load net {FRAME:acc#35.itm#1(0)} -pin  "FRAME:acc#36" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm#1}
+load net {FRAME:acc#35.itm#1(1)} -pin  "FRAME:acc#36" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm#1}
+load net {FRAME:acc#35.itm#1(2)} -pin  "FRAME:acc#36" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm#1}
+load net {FRAME:acc#35.itm#1(3)} -pin  "FRAME:acc#36" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm#1}
+load net {FRAME:acc#35.itm#1(4)} -pin  "FRAME:acc#36" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm#1}
+load net {FRAME:acc#36.itm(0)} -pin  "FRAME:acc#36" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(1)} -pin  "FRAME:acc#36" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(2)} -pin  "FRAME:acc#36" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(3)} -pin  "FRAME:acc#36" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(4)} -pin  "FRAME:acc#36" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(5)} -pin  "FRAME:acc#36" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(6)} -pin  "FRAME:acc#36" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(7)} -pin  "FRAME:acc#36" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load inst "FRAME:acc#37" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 11914 -attr oid 302 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul.itm#1(0)} -pin  "FRAME:acc#37" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(1)} -pin  "FRAME:acc#37" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(2)} -pin  "FRAME:acc#37" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(3)} -pin  "FRAME:acc#37" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(4)} -pin  "FRAME:acc#37" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(5)} -pin  "FRAME:acc#37" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(6)} -pin  "FRAME:acc#37" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(7)} -pin  "FRAME:acc#37" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(8)} -pin  "FRAME:acc#37" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:acc#36.itm(0)} -pin  "FRAME:acc#37" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(1)} -pin  "FRAME:acc#37" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(2)} -pin  "FRAME:acc#37" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(3)} -pin  "FRAME:acc#37" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(4)} -pin  "FRAME:acc#37" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(5)} -pin  "FRAME:acc#37" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(6)} -pin  "FRAME:acc#37" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(7)} -pin  "FRAME:acc#37" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#37.itm(0)} -pin  "FRAME:acc#37" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(1)} -pin  "FRAME:acc#37" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(2)} -pin  "FRAME:acc#37" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(3)} -pin  "FRAME:acc#37" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(4)} -pin  "FRAME:acc#37" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(5)} -pin  "FRAME:acc#37" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(6)} -pin  "FRAME:acc#37" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(7)} -pin  "FRAME:acc#37" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(8)} -pin  "FRAME:acc#37" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(9)} -pin  "FRAME:acc#37" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load inst "FRAME:acc#2" "add(10,-1,10,-1,10)" "INTERFACE" -attr xrf 11915 -attr oid 303 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2} -attr area 11.241230 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,10)"
+load net {FRAME:acc#37.itm(0)} -pin  "FRAME:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(1)} -pin  "FRAME:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(2)} -pin  "FRAME:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(3)} -pin  "FRAME:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(4)} -pin  "FRAME:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(5)} -pin  "FRAME:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(6)} -pin  "FRAME:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(7)} -pin  "FRAME:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(8)} -pin  "FRAME:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(9)} -pin  "FRAME:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:mul#1.itm#1(0)} -pin  "FRAME:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(1)} -pin  "FRAME:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(2)} -pin  "FRAME:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(3)} -pin  "FRAME:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(4)} -pin  "FRAME:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(5)} -pin  "FRAME:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(6)} -pin  "FRAME:acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(7)} -pin  "FRAME:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(8)} -pin  "FRAME:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(9)} -pin  "FRAME:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:acc#2.itm(0)} -pin  "FRAME:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(1)} -pin  "FRAME:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(2)} -pin  "FRAME:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(3)} -pin  "FRAME:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(4)} -pin  "FRAME:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(5)} -pin  "FRAME:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(6)} -pin  "FRAME:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(7)} -pin  "FRAME:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(8)} -pin  "FRAME:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(9)} -pin  "FRAME:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load inst "FRAME:or#4" "or(2,10)" "INTERFACE" -attr xrf 11916 -attr oid 304 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#4} -attr area 7.298324 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2)"
+load net {FRAME:acc#2.itm(0)} -pin  "FRAME:or#4" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(1)} -pin  "FRAME:or#4" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(2)} -pin  "FRAME:or#4" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(3)} -pin  "FRAME:or#4" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(4)} -pin  "FRAME:or#4" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(5)} -pin  "FRAME:or#4" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(6)} -pin  "FRAME:or#4" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(7)} -pin  "FRAME:or#4" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(8)} -pin  "FRAME:or#4" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(9)} -pin  "FRAME:or#4" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#3.psp.sva(10)} -pin  "FRAME:or#4" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#6.itm}
+load net {FRAME:acc#3.psp.sva(11)} -pin  "FRAME:or#4" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#6.itm}
+load net {FRAME:acc#3.psp.sva(11)} -pin  "FRAME:or#4" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#6.itm}
+load net {FRAME:acc#3.psp.sva(11)} -pin  "FRAME:or#4" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#6.itm}
+load net {FRAME:acc#3.psp.sva(11)} -pin  "FRAME:or#4" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#6.itm}
+load net {FRAME:acc#3.psp.sva(11)} -pin  "FRAME:or#4" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#6.itm}
+load net {FRAME:acc#3.psp.sva(11)} -pin  "FRAME:or#4" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#6.itm}
+load net {FRAME:acc#3.psp.sva(11)} -pin  "FRAME:or#4" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#6.itm}
+load net {FRAME:acc#3.psp.sva(11)} -pin  "FRAME:or#4" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#6.itm}
+load net {FRAME:acc#3.psp.sva(11)} -pin  "FRAME:or#4" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#6.itm}
+load net {FRAME:or#4.itm(0)} -pin  "FRAME:or#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#4.itm}
+load net {FRAME:or#4.itm(1)} -pin  "FRAME:or#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#4.itm}
+load net {FRAME:or#4.itm(2)} -pin  "FRAME:or#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#4.itm}
+load net {FRAME:or#4.itm(3)} -pin  "FRAME:or#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#4.itm}
+load net {FRAME:or#4.itm(4)} -pin  "FRAME:or#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#4.itm}
+load net {FRAME:or#4.itm(5)} -pin  "FRAME:or#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#4.itm}
+load net {FRAME:or#4.itm(6)} -pin  "FRAME:or#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#4.itm}
+load net {FRAME:or#4.itm(7)} -pin  "FRAME:or#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#4.itm}
+load net {FRAME:or#4.itm(8)} -pin  "FRAME:or#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#4.itm}
+load net {FRAME:or#4.itm(9)} -pin  "FRAME:or#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#4.itm}
+load inst "FRAME:acc#41" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 11917 -attr oid 305 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {FRAME:slc(blue)#10.itm#1(0)} -pin  "FRAME:acc#41" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(blue)#10.itm#1}
+load net {FRAME:slc(blue)#10.itm#1(1)} -pin  "FRAME:acc#41" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(blue)#10.itm#1}
+load net {FRAME:slc(blue)#10.itm#1(2)} -pin  "FRAME:acc#41" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(blue)#10.itm#1}
+load net {FRAME:slc(blue)#10.itm#1(3)} -pin  "FRAME:acc#41" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(blue)#10.itm#1}
+load net {FRAME:slc(blue)#10.itm#1(4)} -pin  "FRAME:acc#41" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(blue)#10.itm#1}
+load net {FRAME:slc(blue)#10.itm#1(5)} -pin  "FRAME:acc#41" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(blue)#10.itm#1}
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+load net {FRAME:acc#4.itm(11)} -pin  "FRAME:or#3" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#5.itm}
+load net {FRAME:acc#4.itm(11)} -pin  "FRAME:or#3" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#5.itm}
+load net {FRAME:acc#4.itm(11)} -pin  "FRAME:or#3" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#5.itm}
+load net {FRAME:acc#4.itm(11)} -pin  "FRAME:or#3" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#5.itm}
+load net {FRAME:acc#4.itm(11)} -pin  "FRAME:or#3" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#5.itm}
+load net {FRAME:acc#4.itm(11)} -pin  "FRAME:or#3" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#5.itm}
+load net {FRAME:or#3.itm(0)} -pin  "FRAME:or#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(1)} -pin  "FRAME:or#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(2)} -pin  "FRAME:or#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(3)} -pin  "FRAME:or#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(4)} -pin  "FRAME:or#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(5)} -pin  "FRAME:or#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(6)} -pin  "FRAME:or#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(7)} -pin  "FRAME:or#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(8)} -pin  "FRAME:or#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(9)} -pin  "FRAME:or#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(10)} -pin  "FRAME:or#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(11)} -pin  "FRAME:or#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(12)} -pin  "FRAME:or#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(13)} -pin  "FRAME:or#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(14)} -pin  "FRAME:or#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(15)} -pin  "FRAME:or#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(16)} -pin  "FRAME:or#3" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(17)} -pin  "FRAME:or#3" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(18)} -pin  "FRAME:or#3" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(19)} -pin  "FRAME:or#3" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(20)} -pin  "FRAME:or#3" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(21)} -pin  "FRAME:or#3" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(22)} -pin  "FRAME:or#3" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(23)} -pin  "FRAME:or#3" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(24)} -pin  "FRAME:or#3" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(25)} -pin  "FRAME:or#3" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(26)} -pin  "FRAME:or#3" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(27)} -pin  "FRAME:or#3" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(28)} -pin  "FRAME:or#3" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(29)} -pin  "FRAME:or#3" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load inst "nand" "nand(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "nand" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {main.stage_0#2} -pin  "nand" {A1(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {nand.itm} -pin  "nand" {Z(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load inst "mux" "mux(2,30)" "INTERFACE" -attr xrf 11921 -attr oid 309 -attr vt d -attr @path {/sobel/sobel:core/mux} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "mux" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "mux" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "mux" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "mux" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "mux" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "mux" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "mux" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "mux" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "mux" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "mux" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "mux" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "mux" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "mux" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "mux" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "mux" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "mux" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "mux" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "mux" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "mux" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "mux" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "mux" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "mux" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "mux" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "mux" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "mux" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "mux" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "mux" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "mux" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "mux" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "mux" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {FRAME:or#3.itm(0)} -pin  "mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(1)} -pin  "mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(2)} -pin  "mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(3)} -pin  "mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(4)} -pin  "mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(5)} -pin  "mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(6)} -pin  "mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(7)} -pin  "mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(8)} -pin  "mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(9)} -pin  "mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(10)} -pin  "mux" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(11)} -pin  "mux" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(12)} -pin  "mux" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(13)} -pin  "mux" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(14)} -pin  "mux" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(15)} -pin  "mux" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(16)} -pin  "mux" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(17)} -pin  "mux" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(18)} -pin  "mux" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(19)} -pin  "mux" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(20)} -pin  "mux" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(21)} -pin  "mux" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(22)} -pin  "mux" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(23)} -pin  "mux" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(24)} -pin  "mux" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(25)} -pin  "mux" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(26)} -pin  "mux" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(27)} -pin  "mux" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(28)} -pin  "mux" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(29)} -pin  "mux" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {nand.itm} -pin  "mux" {S(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load net {mux.itm(0)} -pin  "mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "mux" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "mux" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "mux" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "mux" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "mux" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "mux" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "mux" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "mux" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "mux" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "mux" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "mux" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "mux" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "mux" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "mux" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "mux" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "mux" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "mux" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "mux" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "mux" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "mux" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 11922 -attr oid 310 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)}
+load net {mux.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 11923 -attr oid 311 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:mul" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 11924 -attr oid 312 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {red#2.sva(10)} -pin  "FRAME:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#5.itm}
+load net {red#2.sva(11)} -pin  "FRAME:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#5.itm}
+load net {red#2.sva(12)} -pin  "FRAME:mul" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#5.itm}
+load net {PWR} -pin  "FRAME:mul" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul.itm(0)} -pin  "FRAME:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(1)} -pin  "FRAME:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(2)} -pin  "FRAME:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(3)} -pin  "FRAME:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(4)} -pin  "FRAME:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(5)} -pin  "FRAME:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(6)} -pin  "FRAME:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(7)} -pin  "FRAME:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(8)} -pin  "FRAME:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load inst "reg(FRAME:mul.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 11925 -attr oid 313 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul.itm#1)}
+load net {FRAME:mul.itm(0)} -pin  "reg(FRAME:mul.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(1)} -pin  "reg(FRAME:mul.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(2)} -pin  "reg(FRAME:mul.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(3)} -pin  "reg(FRAME:mul.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(4)} -pin  "reg(FRAME:mul.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(5)} -pin  "reg(FRAME:mul.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(6)} -pin  "reg(FRAME:mul.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(7)} -pin  "reg(FRAME:mul.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(8)} -pin  "reg(FRAME:mul.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {GND} -pin  "reg(FRAME:mul.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul.itm#1)" {clk} -attr xrf 11926 -attr oid 314 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul.itm#1(0)} -pin  "reg(FRAME:mul.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(1)} -pin  "reg(FRAME:mul.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(2)} -pin  "reg(FRAME:mul.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(3)} -pin  "reg(FRAME:mul.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(4)} -pin  "reg(FRAME:mul.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(5)} -pin  "reg(FRAME:mul.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(6)} -pin  "reg(FRAME:mul.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(7)} -pin  "reg(FRAME:mul.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load net {FRAME:mul.itm#1(8)} -pin  "reg(FRAME:mul.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm#1}
+load inst "reg(FRAME:slc(red)#10.itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 11927 -attr oid 315 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:slc(red)#10.itm#1)}
+load net {red#2.sva(4)} -pin  "reg(FRAME:slc(red)#10.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#4.itm}
+load net {red#2.sva(5)} -pin  "reg(FRAME:slc(red)#10.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#4.itm}
+load net {red#2.sva(6)} -pin  "reg(FRAME:slc(red)#10.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#4.itm}
+load net {red#2.sva(7)} -pin  "reg(FRAME:slc(red)#10.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#4.itm}
+load net {red#2.sva(8)} -pin  "reg(FRAME:slc(red)#10.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#4.itm}
+load net {red#2.sva(9)} -pin  "reg(FRAME:slc(red)#10.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#4.itm}
+load net {GND} -pin  "reg(FRAME:slc(red)#10.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(red)#10.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(red)#10.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(red)#10.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(red)#10.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(red)#10.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(FRAME:slc(red)#10.itm#1)" {clk} -attr xrf 11928 -attr oid 316 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(red)#10.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(red)#10.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(red)#10.itm#1(0)} -pin  "reg(FRAME:slc(red)#10.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(red)#10.itm#1}
+load net {FRAME:slc(red)#10.itm#1(1)} -pin  "reg(FRAME:slc(red)#10.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(red)#10.itm#1}
+load net {FRAME:slc(red)#10.itm#1(2)} -pin  "reg(FRAME:slc(red)#10.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(red)#10.itm#1}
+load net {FRAME:slc(red)#10.itm#1(3)} -pin  "reg(FRAME:slc(red)#10.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(red)#10.itm#1}
+load net {FRAME:slc(red)#10.itm#1(4)} -pin  "reg(FRAME:slc(red)#10.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(red)#10.itm#1}
+load net {FRAME:slc(red)#10.itm#1(5)} -pin  "reg(FRAME:slc(red)#10.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(red)#10.itm#1}
+load inst "FRAME:not#36" "not(1)" "INTERFACE" -attr xrf 11929 -attr oid 317 -attr @path {/sobel/sobel:core/FRAME:not#36} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#7.psp.sva(5)} -pin  "FRAME:not#36" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#7.psp.sva)#6.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:not#36" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#36.itm}
+load inst "FRAME:not#5" "not(1)" "INTERFACE" -attr xrf 11930 -attr oid 318 -attr @path {/sobel/sobel:core/FRAME:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {red#2.sva(15)} -pin  "FRAME:not#5" {A(0)} -attr @path {/sobel/sobel:core/slc(red#2.sva)#11.itm}
+load net {FRAME:not#5.itm} -pin  "FRAME:not#5" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load inst "FRAME:nand" "nand(2,1)" "INTERFACE" -attr xrf 11931 -attr oid 319 -attr @path {/sobel/sobel:core/FRAME:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {FRAME:acc#17.itm(4)} -pin  "FRAME:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#8.psp.sva)#4.itm}
+load net {FRAME:not#5.itm} -pin  "FRAME:nand" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:nand.itm} -pin  "FRAME:nand" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:nand.itm}
+load inst "FRAME:not#6" "not(1)" "INTERFACE" -attr xrf 11932 -attr oid 320 -attr @path {/sobel/sobel:core/FRAME:not#6} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#17.itm(4)} -pin  "FRAME:not#6" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#8.psp.sva).itm}
+load net {FRAME:not#6.itm} -pin  "FRAME:not#6" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load inst "FRAME:or" "or(4,1)" "INTERFACE" -attr xrf 11933 -attr oid 321 -attr vt c -attr @path {/sobel/sobel:core/FRAME:or} -attr area 1.380120 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,4)"
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:or" {A0(0)} -attr vt c -attr @path {/sobel/sobel:core/slc(FRAME:acc#8.psp.sva)#1.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:or" {A1(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#8.psp.sva)#2.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:or" {A2(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#8.psp.sva)#3.itm}
+load net {red#2.sva(0)} -pin  "FRAME:or" {A3(0)} -attr @path {/sobel/sobel:core/slc(red#2.sva)#2.itm}
+load net {FRAME:or.itm} -pin  "FRAME:or" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load inst "and#1" "and(3,1)" "INTERFACE" -attr xrf 11934 -attr oid 322 -attr vt c -attr @path {/sobel/sobel:core/and#1} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {red#2.sva(15)} -pin  "and#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(red#2.sva)#1.itm}
+load net {FRAME:not#6.itm} -pin  "and#1" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:or.itm} -pin  "and#1" {A2(0)} -attr vt c -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {and#1.itm} -pin  "and#1" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/and#1.itm}
+load inst "FRAME:acc#33" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 11935 -attr oid 323 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#33} -attr area 5.297136 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,5)"
+load net {PWR} -pin  "FRAME:acc#33" {A(0)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {FRAME:nand.itm} -pin  "FRAME:acc#33" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {PWR} -pin  "FRAME:acc#33" {A(2)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:acc#33" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {and#1.itm} -pin  "FRAME:acc#33" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:conc#79.itm}
+load net {FRAME:acc#7.psp.sva(3)} -pin  "FRAME:acc#33" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:conc#79.itm}
+load net {FRAME:acc#7.psp.sva(4)} -pin  "FRAME:acc#33" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:conc#79.itm}
+load net {FRAME:acc#33.itm(0)} -pin  "FRAME:acc#33" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(1)} -pin  "FRAME:acc#33" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(2)} -pin  "FRAME:acc#33" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(3)} -pin  "FRAME:acc#33" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(4)} -pin  "FRAME:acc#33" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load inst "FRAME:not#7" "not(3)" "INTERFACE" -attr xrf 11936 -attr oid 324 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {red#2.sva(7)} -pin  "FRAME:not#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#3.itm}
+load net {red#2.sva(8)} -pin  "FRAME:not#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#3.itm}
+load net {red#2.sva(9)} -pin  "FRAME:not#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#3.itm}
+load net {FRAME:not#7.itm(0)} -pin  "FRAME:not#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load net {FRAME:not#7.itm(1)} -pin  "FRAME:not#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load net {FRAME:not#7.itm(2)} -pin  "FRAME:not#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load inst "FRAME:acc#34" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 11937 -attr oid 325 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#34} -attr area 5.297136 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,5)"
+load net {FRAME:acc#33.itm(1)} -pin  "FRAME:acc#34" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:slc#6.itm}
+load net {FRAME:acc#33.itm(2)} -pin  "FRAME:acc#34" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:slc#6.itm}
+load net {FRAME:acc#33.itm(3)} -pin  "FRAME:acc#34" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:slc#6.itm}
+load net {FRAME:acc#33.itm(4)} -pin  "FRAME:acc#34" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:slc#6.itm}
+load net {FRAME:not#7.itm(0)} -pin  "FRAME:acc#34" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load net {FRAME:not#7.itm(1)} -pin  "FRAME:acc#34" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load net {FRAME:not#7.itm(2)} -pin  "FRAME:acc#34" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load net {FRAME:acc#34.itm(0)} -pin  "FRAME:acc#34" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(1)} -pin  "FRAME:acc#34" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(2)} -pin  "FRAME:acc#34" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(3)} -pin  "FRAME:acc#34" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(4)} -pin  "FRAME:acc#34" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load inst "FRAME:acc#35" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 11938 -attr oid 326 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#35} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,1,5,1,6)"
+load net {FRAME:acc#34.itm(0)} -pin  "FRAME:acc#35" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(1)} -pin  "FRAME:acc#35" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(2)} -pin  "FRAME:acc#35" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(3)} -pin  "FRAME:acc#35" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(4)} -pin  "FRAME:acc#35" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#7.psp.sva(5)} -pin  "FRAME:acc#35" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {PWR} -pin  "FRAME:acc#35" {B(1)} -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {GND} -pin  "FRAME:acc#35" {B(2)} -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {GND} -pin  "FRAME:acc#35" {B(3)} -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {PWR} -pin  "FRAME:acc#35" {B(4)} -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {FRAME:acc#35.itm(0)} -pin  "FRAME:acc#35" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(1)} -pin  "FRAME:acc#35" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(2)} -pin  "FRAME:acc#35" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(3)} -pin  "FRAME:acc#35" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(4)} -pin  "FRAME:acc#35" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load inst "reg(FRAME:acc#35.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 11939 -attr oid 327 -attr vt dc -attr @path {/sobel/sobel:core/reg(FRAME:acc#35.itm#1)}
+load net {FRAME:acc#35.itm(0)} -pin  "reg(FRAME:acc#35.itm#1)" {D(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(1)} -pin  "reg(FRAME:acc#35.itm#1)" {D(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(2)} -pin  "reg(FRAME:acc#35.itm#1)" {D(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(3)} -pin  "reg(FRAME:acc#35.itm#1)" {D(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(4)} -pin  "reg(FRAME:acc#35.itm#1)" {D(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {GND} -pin  "reg(FRAME:acc#35.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#35.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#35.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#35.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#35.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#35.itm#1)" {clk} -attr xrf 11940 -attr oid 328 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#35.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#35.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#35.itm#1(0)} -pin  "reg(FRAME:acc#35.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm#1}
+load net {FRAME:acc#35.itm#1(1)} -pin  "reg(FRAME:acc#35.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm#1}
+load net {FRAME:acc#35.itm#1(2)} -pin  "reg(FRAME:acc#35.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm#1}
+load net {FRAME:acc#35.itm#1(3)} -pin  "reg(FRAME:acc#35.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm#1}
+load net {FRAME:acc#35.itm#1(4)} -pin  "reg(FRAME:acc#35.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm#1}
+load inst "FRAME:mul#1" "mul(3,1,9,0,10)" "INTERFACE" -attr xrf 11941 -attr oid 329 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1} -attr area 331.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,1,9,0,10)"
+load net {red#2.sva(13)} -pin  "FRAME:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#10.itm}
+load net {red#2.sva(14)} -pin  "FRAME:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#10.itm}
+load net {red#2.sva(15)} -pin  "FRAME:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#10.itm}
+load net {PWR} -pin  "FRAME:mul#1" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#1" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#1" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#1" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#1" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#1" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#1" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#1" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#1" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#1.itm(0)} -pin  "FRAME:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "FRAME:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "FRAME:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "FRAME:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "FRAME:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "FRAME:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "FRAME:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "FRAME:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "FRAME:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(9)} -pin  "FRAME:mul#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load inst "reg(FRAME:mul#1.itm#1)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 11942 -attr oid 330 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#1.itm#1)}
+load net {FRAME:mul#1.itm(0)} -pin  "reg(FRAME:mul#1.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "reg(FRAME:mul#1.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "reg(FRAME:mul#1.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "reg(FRAME:mul#1.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "reg(FRAME:mul#1.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "reg(FRAME:mul#1.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "reg(FRAME:mul#1.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "reg(FRAME:mul#1.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "reg(FRAME:mul#1.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(9)} -pin  "reg(FRAME:mul#1.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10}
+load net {clk} -pin  "reg(FRAME:mul#1.itm#1)" {clk} -attr xrf 11943 -attr oid 331 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#1.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#1.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#1.itm#1(0)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(1)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(2)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(3)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(4)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(5)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(6)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(7)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(8)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(9)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load inst "FRAME:mul#4" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 11944 -attr oid 332 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {blue#2.sva(10)} -pin  "FRAME:mul#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#5.itm}
+load net {blue#2.sva(11)} -pin  "FRAME:mul#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#5.itm}
+load net {blue#2.sva(12)} -pin  "FRAME:mul#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#5.itm}
+load net {PWR} -pin  "FRAME:mul#4" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#4" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#4" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#4" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#4" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#4" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#4.itm(0)} -pin  "FRAME:mul#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(1)} -pin  "FRAME:mul#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(2)} -pin  "FRAME:mul#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(3)} -pin  "FRAME:mul#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(4)} -pin  "FRAME:mul#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(5)} -pin  "FRAME:mul#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(6)} -pin  "FRAME:mul#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(7)} -pin  "FRAME:mul#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(8)} -pin  "FRAME:mul#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load inst "reg(FRAME:mul#4.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 11945 -attr oid 333 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#4.itm#1)}
+load net {FRAME:mul#4.itm(0)} -pin  "reg(FRAME:mul#4.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(1)} -pin  "reg(FRAME:mul#4.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(2)} -pin  "reg(FRAME:mul#4.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(3)} -pin  "reg(FRAME:mul#4.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(4)} -pin  "reg(FRAME:mul#4.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(5)} -pin  "reg(FRAME:mul#4.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(6)} -pin  "reg(FRAME:mul#4.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(7)} -pin  "reg(FRAME:mul#4.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(8)} -pin  "reg(FRAME:mul#4.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#4.itm#1)" {clk} -attr xrf 11946 -attr oid 334 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#4.itm#1(0)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(1)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(2)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(3)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(4)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(5)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(6)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(7)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(8)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load inst "reg(FRAME:slc(blue)#10.itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 11947 -attr oid 335 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:slc(blue)#10.itm#1)}
+load net {blue#2.sva(4)} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#4.itm}
+load net {blue#2.sva(5)} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#4.itm}
+load net {blue#2.sva(6)} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#4.itm}
+load net {blue#2.sva(7)} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#4.itm}
+load net {blue#2.sva(8)} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#4.itm}
+load net {blue#2.sva(9)} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#4.itm}
+load net {GND} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {clk} -attr xrf 11948 -attr oid 336 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(blue)#10.itm#1(0)} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(blue)#10.itm#1}
+load net {FRAME:slc(blue)#10.itm#1(1)} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(blue)#10.itm#1}
+load net {FRAME:slc(blue)#10.itm#1(2)} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(blue)#10.itm#1}
+load net {FRAME:slc(blue)#10.itm#1(3)} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(blue)#10.itm#1}
+load net {FRAME:slc(blue)#10.itm#1(4)} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(blue)#10.itm#1}
+load net {FRAME:slc(blue)#10.itm#1(5)} -pin  "reg(FRAME:slc(blue)#10.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(blue)#10.itm#1}
+load inst "FRAME:not#35" "not(1)" "INTERFACE" -attr xrf 11949 -attr oid 337 -attr @path {/sobel/sobel:core/FRAME:not#35} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#11.psp.sva(5)} -pin  "FRAME:not#35" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#11.psp.sva)#6.itm}
+load net {FRAME:not#35.itm} -pin  "FRAME:not#35" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#35.itm}
+load inst "FRAME:not#23" "not(1)" "INTERFACE" -attr xrf 11950 -attr oid 338 -attr @path {/sobel/sobel:core/FRAME:not#23} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {blue#2.sva(15)} -pin  "FRAME:not#23" {A(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sva)#11.itm}
+load net {FRAME:not#23.itm} -pin  "FRAME:not#23" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#23.itm}
+load inst "FRAME:nand#2" "nand(2,1)" "INTERFACE" -attr xrf 11951 -attr oid 339 -attr @path {/sobel/sobel:core/FRAME:nand#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {FRAME:acc#32.itm(4)} -pin  "FRAME:nand#2" {A0(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#12.psp.sva)#4.itm}
+load net {FRAME:not#23.itm} -pin  "FRAME:nand#2" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:not#23.itm}
+load net {FRAME:nand#2.itm} -pin  "FRAME:nand#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:nand#2.itm}
+load inst "FRAME:not#24" "not(1)" "INTERFACE" -attr xrf 11952 -attr oid 340 -attr @path {/sobel/sobel:core/FRAME:not#24} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#32.itm(4)} -pin  "FRAME:not#24" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#12.psp.sva).itm}
+load net {FRAME:not#24.itm} -pin  "FRAME:not#24" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#24.itm}
+load inst "FRAME:or#2" "or(4,1)" "INTERFACE" -attr xrf 11953 -attr oid 341 -attr @path {/sobel/sobel:core/FRAME:or#2} -attr area 1.380120 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,4)"
+load net {FRAME:acc#32.itm(3)} -pin  "FRAME:or#2" {A0(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#12.psp.sva)#1.itm}
+load net {FRAME:acc#32.itm(2)} -pin  "FRAME:or#2" {A1(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#12.psp.sva)#2.itm}
+load net {FRAME:acc#32.itm(1)} -pin  "FRAME:or#2" {A2(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#12.psp.sva)#3.itm}
+load net {blue#2.sva(0)} -pin  "FRAME:or#2" {A3(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sva)#2.itm}
+load net {FRAME:or#2.itm} -pin  "FRAME:or#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:or#2.itm}
+load inst "and#5" "and(3,1)" "INTERFACE" -attr xrf 11954 -attr oid 342 -attr @path {/sobel/sobel:core/and#5} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {blue#2.sva(15)} -pin  "and#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sva)#1.itm}
+load net {FRAME:not#24.itm} -pin  "and#5" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:not#24.itm}
+load net {FRAME:or#2.itm} -pin  "and#5" {A2(0)} -attr @path {/sobel/sobel:core/FRAME:or#2.itm}
+load net {and#5.itm} -pin  "and#5" {Z(0)} -attr @path {/sobel/sobel:core/and#5.itm}
+load inst "FRAME:acc#38" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 11955 -attr oid 343 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38} -attr area 5.297136 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,5)"
+load net {PWR} -pin  "FRAME:acc#38" {A(0)} -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {FRAME:nand#2.itm} -pin  "FRAME:acc#38" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {PWR} -pin  "FRAME:acc#38" {A(2)} -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {FRAME:not#35.itm} -pin  "FRAME:acc#38" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {and#5.itm} -pin  "FRAME:acc#38" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#82.itm}
+load net {FRAME:acc#11.psp.sva(3)} -pin  "FRAME:acc#38" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#82.itm}
+load net {FRAME:acc#11.psp.sva(4)} -pin  "FRAME:acc#38" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#82.itm}
+load net {FRAME:acc#38.itm(0)} -pin  "FRAME:acc#38" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(1)} -pin  "FRAME:acc#38" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(2)} -pin  "FRAME:acc#38" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(3)} -pin  "FRAME:acc#38" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(4)} -pin  "FRAME:acc#38" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load inst "FRAME:not#25" "not(3)" "INTERFACE" -attr xrf 11956 -attr oid 344 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {blue#2.sva(7)} -pin  "FRAME:not#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#3.itm}
+load net {blue#2.sva(8)} -pin  "FRAME:not#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#3.itm}
+load net {blue#2.sva(9)} -pin  "FRAME:not#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#3.itm}
+load net {FRAME:not#25.itm(0)} -pin  "FRAME:not#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:not#25.itm(1)} -pin  "FRAME:not#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:not#25.itm(2)} -pin  "FRAME:not#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load inst "FRAME:acc#39" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 11957 -attr oid 345 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39} -attr area 5.297136 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,5)"
+load net {FRAME:acc#38.itm(1)} -pin  "FRAME:acc#39" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:acc#38.itm(2)} -pin  "FRAME:acc#39" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:acc#38.itm(3)} -pin  "FRAME:acc#39" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:acc#38.itm(4)} -pin  "FRAME:acc#39" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:not#25.itm(0)} -pin  "FRAME:acc#39" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:not#25.itm(1)} -pin  "FRAME:acc#39" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:not#25.itm(2)} -pin  "FRAME:acc#39" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:acc#39.itm(0)} -pin  "FRAME:acc#39" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(1)} -pin  "FRAME:acc#39" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(2)} -pin  "FRAME:acc#39" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(3)} -pin  "FRAME:acc#39" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(4)} -pin  "FRAME:acc#39" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load inst "FRAME:acc#40" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 11958 -attr oid 346 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,1,5,1,6)"
+load net {FRAME:acc#39.itm(0)} -pin  "FRAME:acc#40" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(1)} -pin  "FRAME:acc#40" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(2)} -pin  "FRAME:acc#40" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(3)} -pin  "FRAME:acc#40" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(4)} -pin  "FRAME:acc#40" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#11.psp.sva(5)} -pin  "FRAME:acc#40" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {PWR} -pin  "FRAME:acc#40" {B(1)} -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {GND} -pin  "FRAME:acc#40" {B(2)} -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {GND} -pin  "FRAME:acc#40" {B(3)} -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {PWR} -pin  "FRAME:acc#40" {B(4)} -attr @path {/sobel/sobel:core/conc#140.itm}
+load net {FRAME:acc#40.itm(0)} -pin  "FRAME:acc#40" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(1)} -pin  "FRAME:acc#40" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(2)} -pin  "FRAME:acc#40" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(3)} -pin  "FRAME:acc#40" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(4)} -pin  "FRAME:acc#40" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load inst "reg(FRAME:acc#40.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 11959 -attr oid 347 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#40.itm#1)}
+load net {FRAME:acc#40.itm(0)} -pin  "reg(FRAME:acc#40.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(1)} -pin  "reg(FRAME:acc#40.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(2)} -pin  "reg(FRAME:acc#40.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(3)} -pin  "reg(FRAME:acc#40.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(4)} -pin  "reg(FRAME:acc#40.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {GND} -pin  "reg(FRAME:acc#40.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#40.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#40.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#40.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#40.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#40.itm#1)" {clk} -attr xrf 11960 -attr oid 348 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#40.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#40.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#40.itm#1(0)} -pin  "reg(FRAME:acc#40.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm#1}
+load net {FRAME:acc#40.itm#1(1)} -pin  "reg(FRAME:acc#40.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm#1}
+load net {FRAME:acc#40.itm#1(2)} -pin  "reg(FRAME:acc#40.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm#1}
+load net {FRAME:acc#40.itm#1(3)} -pin  "reg(FRAME:acc#40.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm#1}
+load net {FRAME:acc#40.itm#1(4)} -pin  "reg(FRAME:acc#40.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm#1}
+load inst "FRAME:mul#5" "mul(3,1,9,0,12)" "INTERFACE" -attr xrf 11961 -attr oid 349 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5} -attr area 335.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,1,9,0,12)"
+load net {blue#2.sva(13)} -pin  "FRAME:mul#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#10.itm}
+load net {blue#2.sva(14)} -pin  "FRAME:mul#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#10.itm}
+load net {blue#2.sva(15)} -pin  "FRAME:mul#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#10.itm}
+load net {PWR} -pin  "FRAME:mul#5" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#5" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#5" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#5" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#5" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#5" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#5" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#5" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#5" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#5.itm(0)} -pin  "FRAME:mul#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(1)} -pin  "FRAME:mul#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(2)} -pin  "FRAME:mul#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(3)} -pin  "FRAME:mul#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(4)} -pin  "FRAME:mul#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(5)} -pin  "FRAME:mul#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(6)} -pin  "FRAME:mul#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(7)} -pin  "FRAME:mul#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(8)} -pin  "FRAME:mul#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(9)} -pin  "FRAME:mul#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(10)} -pin  "FRAME:mul#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(11)} -pin  "FRAME:mul#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load inst "reg(FRAME:mul#5.itm#1)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 11962 -attr oid 350 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#5.itm#1)}
+load net {FRAME:mul#5.itm(0)} -pin  "reg(FRAME:mul#5.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(1)} -pin  "reg(FRAME:mul#5.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(2)} -pin  "reg(FRAME:mul#5.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(3)} -pin  "reg(FRAME:mul#5.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(4)} -pin  "reg(FRAME:mul#5.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(5)} -pin  "reg(FRAME:mul#5.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(6)} -pin  "reg(FRAME:mul#5.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(7)} -pin  "reg(FRAME:mul#5.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(8)} -pin  "reg(FRAME:mul#5.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(9)} -pin  "reg(FRAME:mul#5.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(10)} -pin  "reg(FRAME:mul#5.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(11)} -pin  "reg(FRAME:mul#5.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(FRAME:mul#5.itm#1)" {clk} -attr xrf 11963 -attr oid 351 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#5.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#5.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#5.itm#1(0)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(1)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(2)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(3)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(4)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(5)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(6)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(7)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(8)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(9)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(10)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(11)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load inst "FRAME:mul#2" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 11964 -attr oid 352 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {green#2.sva(10)} -pin  "FRAME:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#5.itm}
+load net {green#2.sva(11)} -pin  "FRAME:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#5.itm}
+load net {green#2.sva(12)} -pin  "FRAME:mul#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#5.itm}
+load net {PWR} -pin  "FRAME:mul#2" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#2" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#2" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#2" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#2" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#2" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#2.itm(0)} -pin  "FRAME:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(1)} -pin  "FRAME:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(2)} -pin  "FRAME:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(3)} -pin  "FRAME:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(4)} -pin  "FRAME:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(5)} -pin  "FRAME:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(6)} -pin  "FRAME:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(7)} -pin  "FRAME:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(8)} -pin  "FRAME:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load inst "reg(FRAME:mul#2.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 11965 -attr oid 353 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#2.itm#1)}
+load net {FRAME:mul#2.itm(0)} -pin  "reg(FRAME:mul#2.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(1)} -pin  "reg(FRAME:mul#2.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(2)} -pin  "reg(FRAME:mul#2.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(3)} -pin  "reg(FRAME:mul#2.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(4)} -pin  "reg(FRAME:mul#2.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(5)} -pin  "reg(FRAME:mul#2.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(6)} -pin  "reg(FRAME:mul#2.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(7)} -pin  "reg(FRAME:mul#2.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(8)} -pin  "reg(FRAME:mul#2.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#2.itm#1)" {clk} -attr xrf 11966 -attr oid 354 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#2.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#2.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#2.itm#1(0)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(1)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(2)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(3)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(4)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(5)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(6)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(7)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(8)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load inst "reg(FRAME:slc(green)#10.itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 11967 -attr oid 355 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:slc(green)#10.itm#1)}
+load net {green#2.sva(4)} -pin  "reg(FRAME:slc(green)#10.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#4.itm}
+load net {green#2.sva(5)} -pin  "reg(FRAME:slc(green)#10.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#4.itm}
+load net {green#2.sva(6)} -pin  "reg(FRAME:slc(green)#10.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#4.itm}
+load net {green#2.sva(7)} -pin  "reg(FRAME:slc(green)#10.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#4.itm}
+load net {green#2.sva(8)} -pin  "reg(FRAME:slc(green)#10.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#4.itm}
+load net {green#2.sva(9)} -pin  "reg(FRAME:slc(green)#10.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#4.itm}
+load net {GND} -pin  "reg(FRAME:slc(green)#10.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(green)#10.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(green)#10.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(green)#10.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(green)#10.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:slc(green)#10.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(FRAME:slc(green)#10.itm#1)" {clk} -attr xrf 11968 -attr oid 356 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(green)#10.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(green)#10.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(green)#10.itm#1(0)} -pin  "reg(FRAME:slc(green)#10.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(green)#10.itm#1}
+load net {FRAME:slc(green)#10.itm#1(1)} -pin  "reg(FRAME:slc(green)#10.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(green)#10.itm#1}
+load net {FRAME:slc(green)#10.itm#1(2)} -pin  "reg(FRAME:slc(green)#10.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(green)#10.itm#1}
+load net {FRAME:slc(green)#10.itm#1(3)} -pin  "reg(FRAME:slc(green)#10.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(green)#10.itm#1}
+load net {FRAME:slc(green)#10.itm#1(4)} -pin  "reg(FRAME:slc(green)#10.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(green)#10.itm#1}
+load net {FRAME:slc(green)#10.itm#1(5)} -pin  "reg(FRAME:slc(green)#10.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(green)#10.itm#1}
+load inst "FRAME:not#37" "not(1)" "INTERFACE" -attr xrf 11969 -attr oid 357 -attr @path {/sobel/sobel:core/FRAME:not#37} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#9.psp.sva(5)} -pin  "FRAME:not#37" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#9.psp.sva)#6.itm}
+load net {FRAME:not#37.itm} -pin  "FRAME:not#37" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#37.itm}
+load inst "FRAME:not#14" "not(1)" "INTERFACE" -attr xrf 11970 -attr oid 358 -attr @path {/sobel/sobel:core/FRAME:not#14} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {green#2.sva(15)} -pin  "FRAME:not#14" {A(0)} -attr @path {/sobel/sobel:core/slc(green#2.sva)#11.itm}
+load net {FRAME:not#14.itm} -pin  "FRAME:not#14" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load inst "FRAME:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 11971 -attr oid 359 -attr @path {/sobel/sobel:core/FRAME:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {FRAME:acc#22.itm(4)} -pin  "FRAME:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#10.psp.sva)#4.itm}
+load net {FRAME:not#14.itm} -pin  "FRAME:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:nand#1.itm} -pin  "FRAME:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:nand#1.itm}
+load inst "FRAME:not#15" "not(1)" "INTERFACE" -attr xrf 11972 -attr oid 360 -attr @path {/sobel/sobel:core/FRAME:not#15} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#22.itm(4)} -pin  "FRAME:not#15" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#10.psp.sva).itm}
+load net {FRAME:not#15.itm} -pin  "FRAME:not#15" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#15.itm}
+load inst "FRAME:or#1" "or(4,1)" "INTERFACE" -attr xrf 11973 -attr oid 361 -attr @path {/sobel/sobel:core/FRAME:or#1} -attr area 1.380120 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,4)"
+load net {FRAME:acc#22.itm(3)} -pin  "FRAME:or#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#10.psp.sva)#1.itm}
+load net {FRAME:acc#22.itm(2)} -pin  "FRAME:or#1" {A1(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#10.psp.sva)#2.itm}
+load net {FRAME:acc#22.itm(1)} -pin  "FRAME:or#1" {A2(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#10.psp.sva)#3.itm}
+load net {green#2.sva(0)} -pin  "FRAME:or#1" {A3(0)} -attr @path {/sobel/sobel:core/slc(green#2.sva)#2.itm}
+load net {FRAME:or#1.itm} -pin  "FRAME:or#1" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:or#1.itm}
+load inst "and#3" "and(3,1)" "INTERFACE" -attr xrf 11974 -attr oid 362 -attr @path {/sobel/sobel:core/and#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {green#2.sva(15)} -pin  "and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(green#2.sva)#1.itm}
+load net {FRAME:not#15.itm} -pin  "and#3" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:not#15.itm}
+load net {FRAME:or#1.itm} -pin  "and#3" {A2(0)} -attr @path {/sobel/sobel:core/FRAME:or#1.itm}
+load net {and#3.itm} -pin  "and#3" {Z(0)} -attr @path {/sobel/sobel:core/and#3.itm}
+load inst "FRAME:acc#23" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 11975 -attr oid 363 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23} -attr area 5.297136 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,5)"
+load net {PWR} -pin  "FRAME:acc#23" {A(0)} -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {FRAME:nand#1.itm} -pin  "FRAME:acc#23" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {PWR} -pin  "FRAME:acc#23" {A(2)} -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {FRAME:not#37.itm} -pin  "FRAME:acc#23" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {and#3.itm} -pin  "FRAME:acc#23" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#73.itm}
+load net {FRAME:acc#9.psp.sva(3)} -pin  "FRAME:acc#23" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#73.itm}
+load net {FRAME:acc#9.psp.sva(4)} -pin  "FRAME:acc#23" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#73.itm}
+load net {FRAME:acc#23.itm(0)} -pin  "FRAME:acc#23" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(1)} -pin  "FRAME:acc#23" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(2)} -pin  "FRAME:acc#23" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(3)} -pin  "FRAME:acc#23" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(4)} -pin  "FRAME:acc#23" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load inst "FRAME:not#16" "not(3)" "INTERFACE" -attr xrf 11976 -attr oid 364 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {green#2.sva(7)} -pin  "FRAME:not#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#3.itm}
+load net {green#2.sva(8)} -pin  "FRAME:not#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#3.itm}
+load net {green#2.sva(9)} -pin  "FRAME:not#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#3.itm}
+load net {FRAME:not#16.itm(0)} -pin  "FRAME:not#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load net {FRAME:not#16.itm(1)} -pin  "FRAME:not#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load net {FRAME:not#16.itm(2)} -pin  "FRAME:not#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load inst "FRAME:acc#24" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 11977 -attr oid 365 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24} -attr area 5.297136 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,5)"
+load net {FRAME:acc#23.itm(1)} -pin  "FRAME:acc#24" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#4.itm}
+load net {FRAME:acc#23.itm(2)} -pin  "FRAME:acc#24" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#4.itm}
+load net {FRAME:acc#23.itm(3)} -pin  "FRAME:acc#24" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#4.itm}
+load net {FRAME:acc#23.itm(4)} -pin  "FRAME:acc#24" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc#4.itm}
+load net {FRAME:not#16.itm(0)} -pin  "FRAME:acc#24" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load net {FRAME:not#16.itm(1)} -pin  "FRAME:acc#24" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load net {FRAME:not#16.itm(2)} -pin  "FRAME:acc#24" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#16.itm}
+load net {FRAME:acc#24.itm(0)} -pin  "FRAME:acc#24" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(1)} -pin  "FRAME:acc#24" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(2)} -pin  "FRAME:acc#24" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(3)} -pin  "FRAME:acc#24" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(4)} -pin  "FRAME:acc#24" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load inst "FRAME:acc#25" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 11978 -attr oid 366 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,1,5,1,6)"
+load net {FRAME:acc#24.itm(0)} -pin  "FRAME:acc#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(1)} -pin  "FRAME:acc#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(2)} -pin  "FRAME:acc#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(3)} -pin  "FRAME:acc#25" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(4)} -pin  "FRAME:acc#25" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#9.psp.sva(5)} -pin  "FRAME:acc#25" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {PWR} -pin  "FRAME:acc#25" {B(1)} -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {GND} -pin  "FRAME:acc#25" {B(2)} -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {GND} -pin  "FRAME:acc#25" {B(3)} -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {PWR} -pin  "FRAME:acc#25" {B(4)} -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {FRAME:acc#25.itm(0)} -pin  "FRAME:acc#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(1)} -pin  "FRAME:acc#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(2)} -pin  "FRAME:acc#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(3)} -pin  "FRAME:acc#25" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(4)} -pin  "FRAME:acc#25" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load inst "reg(FRAME:acc#25.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 11979 -attr oid 367 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#25.itm#1)}
+load net {FRAME:acc#25.itm(0)} -pin  "reg(FRAME:acc#25.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(1)} -pin  "reg(FRAME:acc#25.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(2)} -pin  "reg(FRAME:acc#25.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(3)} -pin  "reg(FRAME:acc#25.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(4)} -pin  "reg(FRAME:acc#25.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {GND} -pin  "reg(FRAME:acc#25.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#25.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#25.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#25.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#25.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#25.itm#1)" {clk} -attr xrf 11980 -attr oid 368 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#25.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#25.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#25.itm#1(0)} -pin  "reg(FRAME:acc#25.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm#1}
+load net {FRAME:acc#25.itm#1(1)} -pin  "reg(FRAME:acc#25.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm#1}
+load net {FRAME:acc#25.itm#1(2)} -pin  "reg(FRAME:acc#25.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm#1}
+load net {FRAME:acc#25.itm#1(3)} -pin  "reg(FRAME:acc#25.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm#1}
+load net {FRAME:acc#25.itm#1(4)} -pin  "reg(FRAME:acc#25.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm#1}
+load inst "FRAME:mul#3" "mul(3,1,9,0,12)" "INTERFACE" -attr xrf 11981 -attr oid 369 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3} -attr area 335.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,1,9,0,12)"
+load net {green#2.sva(13)} -pin  "FRAME:mul#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#10.itm}
+load net {green#2.sva(14)} -pin  "FRAME:mul#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#10.itm}
+load net {green#2.sva(15)} -pin  "FRAME:mul#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#10.itm}
+load net {PWR} -pin  "FRAME:mul#3" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#3" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#3" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#3" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#3" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#3" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#3" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#3" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#3" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#3.itm(0)} -pin  "FRAME:mul#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "FRAME:mul#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "FRAME:mul#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "FRAME:mul#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "FRAME:mul#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "FRAME:mul#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "FRAME:mul#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "FRAME:mul#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "FRAME:mul#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(9)} -pin  "FRAME:mul#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(10)} -pin  "FRAME:mul#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(11)} -pin  "FRAME:mul#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load inst "reg(FRAME:mul#3.itm#1)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 11982 -attr oid 370 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#3.itm#1)}
+load net {FRAME:mul#3.itm(0)} -pin  "reg(FRAME:mul#3.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "reg(FRAME:mul#3.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "reg(FRAME:mul#3.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "reg(FRAME:mul#3.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "reg(FRAME:mul#3.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "reg(FRAME:mul#3.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "reg(FRAME:mul#3.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "reg(FRAME:mul#3.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "reg(FRAME:mul#3.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(9)} -pin  "reg(FRAME:mul#3.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(10)} -pin  "reg(FRAME:mul#3.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(11)} -pin  "reg(FRAME:mul#3.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(FRAME:mul#3.itm#1)" {clk} -attr xrf 11983 -attr oid 371 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#3.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#3.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#3.itm#1(0)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(1)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(2)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(3)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(4)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(5)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(6)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(7)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(8)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(9)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(10)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(11)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load inst "FRAME:for:not#7" "not(1)" "INTERFACE" -attr xrf 11984 -attr oid 372 -attr @path {/sobel/sobel:core/FRAME:for:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:not#7" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#14.itm}
+load net {FRAME:for:not#7.itm} -pin  "FRAME:for:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#7.itm}
+load inst "reg(exit:FRAME:for.sva#1.st#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 11985 -attr oid 373 -attr vt c -attr @path {/sobel/sobel:core/reg(exit:FRAME:for.sva#1.st#1)}
+load net {FRAME:for:not#7.itm} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#7.itm}
+load net {GND} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {clk} -attr xrf 11986 -attr oid 374 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for.sva#1.st#1} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load inst "reg(i#6.sva#1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 11987 -attr oid 375 -attr vt d -attr @path {/sobel/sobel:core/reg(i#6.sva#1)}
+load net {i#6.sva#2(0)} -pin  "reg(i#6.sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "reg(i#6.sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {GND} -pin  "reg(i#6.sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(i#6.sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(i#6.sva#1)" {clk} -attr xrf 11988 -attr oid 376 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(i#6.sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(i#6.sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {i#6.sva#1(0)} -pin  "reg(i#6.sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "reg(i#6.sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load inst "FRAME:for:not" "not(1)" "INTERFACE" -attr xrf 11989 -attr oid 377 -attr @path {/sobel/sobel:core/FRAME:for:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#1.itm}
+load net {FRAME:for:not.itm} -pin  "FRAME:for:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load inst "FRAME:and" "and(2,1)" "INTERFACE" -attr xrf 11990 -attr oid 378 -attr @path {/sobel/sobel:core/FRAME:and} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {FRAME:for:not.itm} -pin  "FRAME:and" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "FRAME:and" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load net {FRAME:and.itm} -pin  "FRAME:and" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load inst "reg(exit:FRAME#1.sva)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 11991 -attr oid 379 -attr @path {/sobel/sobel:core/reg(exit:FRAME#1.sva)}
+load net {FRAME:and.itm} -pin  "reg(exit:FRAME#1.sva)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load net {PWR} -pin  "reg(exit:FRAME#1.sva)" {DRa(0)} -attr @path {/sobel/sobel:core/C1_1_Not_Not}
+load net {clk} -pin  "reg(exit:FRAME#1.sva)" {clk} -attr xrf 11992 -attr oid 380 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME#1.sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME#1.sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME#1.sva} -pin  "reg(exit:FRAME#1.sva)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load inst "reg(main.stage_0#2)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 11993 -attr oid 381 -attr @path {/sobel/sobel:core/reg(main.stage_0#2)}
+load net {PWR} -pin  "reg(main.stage_0#2)" {D(0)} -attr @path {/sobel/sobel:core/Cn1_1#2}
+load net {GND} -pin  "reg(main.stage_0#2)" {DRa(0)} -attr @path {/sobel/sobel:core/Cn2_2#4}
+load net {clk} -pin  "reg(main.stage_0#2)" {clk} -attr xrf 11994 -attr oid 382 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(main.stage_0#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(main.stage_0#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {main.stage_0#2} -pin  "reg(main.stage_0#2)" {Z(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load inst "reg(regs.regs(2).lpi#1.dfm)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 11995 -attr oid 383 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(2).lpi#1.dfm)}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(30)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(31)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(32)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(33)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(34)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(35)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(36)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(37)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(38)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(39)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(40)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(41)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(42)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(43)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(44)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(45)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(46)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(47)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(48)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(49)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(50)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(51)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(52)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(53)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(54)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(55)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(56)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(57)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(58)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(59)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(60)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(61)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(62)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(63)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(64)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(65)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(66)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(67)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(68)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(69)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(70)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(71)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(72)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(73)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(74)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(75)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(76)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(77)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(78)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(79)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(80)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(81)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(82)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(83)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(84)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(85)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(86)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(87)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(88)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(89)} -attr @path {/sobel/sobel:core/C0_90}
+load net {clk} -pin  "reg(regs.regs(2).lpi#1.dfm)" {clk} -attr xrf 11996 -attr oid 384 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(2).lpi#1.dfm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(2).lpi#1.dfm(0)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(1)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(2)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(3)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(4)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(5)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(6)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(7)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(8)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(9)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(10)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(11)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(12)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(13)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(14)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(15)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(16)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(17)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(18)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(19)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(20)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(21)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(22)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(23)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(24)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(25)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(26)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(27)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(28)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(29)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(30)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(31)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(32)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(33)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(34)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(35)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(36)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(37)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(38)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(39)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(40)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(41)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(42)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(43)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(44)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(45)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(46)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(47)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(48)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(49)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(50)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(51)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(52)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(53)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(54)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(55)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(56)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(57)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(58)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(59)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(60)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(61)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(62)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(63)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(64)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(65)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(66)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(67)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(68)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(69)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(70)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(71)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(72)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(73)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(74)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(75)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(76)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(77)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(78)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(79)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(80)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(81)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(82)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(83)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(84)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(85)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(86)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(87)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(88)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(89)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load inst "reg(regs.regs(1).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 11997 -attr oid 385 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(1).sva)}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "reg(regs.regs(1).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "reg(regs.regs(1).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "reg(regs.regs(1).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "reg(regs.regs(1).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "reg(regs.regs(1).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "reg(regs.regs(1).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "reg(regs.regs(1).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "reg(regs.regs(1).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "reg(regs.regs(1).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "reg(regs.regs(1).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "reg(regs.regs(1).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "reg(regs.regs(1).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "reg(regs.regs(1).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "reg(regs.regs(1).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "reg(regs.regs(1).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "reg(regs.regs(1).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "reg(regs.regs(1).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "reg(regs.regs(1).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "reg(regs.regs(1).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "reg(regs.regs(1).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "reg(regs.regs(1).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "reg(regs.regs(1).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "reg(regs.regs(1).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "reg(regs.regs(1).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "reg(regs.regs(1).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "reg(regs.regs(1).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "reg(regs.regs(1).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "reg(regs.regs(1).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "reg(regs.regs(1).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "reg(regs.regs(1).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "reg(regs.regs(1).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "reg(regs.regs(1).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "reg(regs.regs(1).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "reg(regs.regs(1).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "reg(regs.regs(1).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "reg(regs.regs(1).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "reg(regs.regs(1).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "reg(regs.regs(1).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "reg(regs.regs(1).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "reg(regs.regs(1).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "reg(regs.regs(1).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "reg(regs.regs(1).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "reg(regs.regs(1).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "reg(regs.regs(1).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "reg(regs.regs(1).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "reg(regs.regs(1).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "reg(regs.regs(1).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "reg(regs.regs(1).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "reg(regs.regs(1).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "reg(regs.regs(1).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "reg(regs.regs(1).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "reg(regs.regs(1).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "reg(regs.regs(1).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "reg(regs.regs(1).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "reg(regs.regs(1).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "reg(regs.regs(1).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "reg(regs.regs(1).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "reg(regs.regs(1).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "reg(regs.regs(1).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "reg(regs.regs(1).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "reg(regs.regs(1).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "reg(regs.regs(1).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "reg(regs.regs(1).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "reg(regs.regs(1).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "reg(regs.regs(1).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "reg(regs.regs(1).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "reg(regs.regs(1).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "reg(regs.regs(1).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "reg(regs.regs(1).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "reg(regs.regs(1).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "reg(regs.regs(1).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "reg(regs.regs(1).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "reg(regs.regs(1).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "reg(regs.regs(1).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "reg(regs.regs(1).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "reg(regs.regs(1).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "reg(regs.regs(1).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "reg(regs.regs(1).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "reg(regs.regs(1).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "reg(regs.regs(1).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "reg(regs.regs(1).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "reg(regs.regs(1).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "reg(regs.regs(1).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "reg(regs.regs(1).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "reg(regs.regs(1).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "reg(regs.regs(1).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "reg(regs.regs(1).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "reg(regs.regs(1).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "reg(regs.regs(1).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "reg(regs.regs(1).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {clk} -pin  "reg(regs.regs(1).sva)" {clk} -attr xrf 11998 -attr oid 386 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(1).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(1).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(1).sva(0)} -pin  "reg(regs.regs(1).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "reg(regs.regs(1).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "reg(regs.regs(1).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "reg(regs.regs(1).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "reg(regs.regs(1).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "reg(regs.regs(1).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "reg(regs.regs(1).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "reg(regs.regs(1).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "reg(regs.regs(1).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "reg(regs.regs(1).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "reg(regs.regs(1).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "reg(regs.regs(1).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "reg(regs.regs(1).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "reg(regs.regs(1).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "reg(regs.regs(1).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "reg(regs.regs(1).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "reg(regs.regs(1).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "reg(regs.regs(1).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "reg(regs.regs(1).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "reg(regs.regs(1).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "reg(regs.regs(1).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "reg(regs.regs(1).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "reg(regs.regs(1).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "reg(regs.regs(1).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "reg(regs.regs(1).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "reg(regs.regs(1).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "reg(regs.regs(1).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "reg(regs.regs(1).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "reg(regs.regs(1).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "reg(regs.regs(1).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "reg(regs.regs(1).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "reg(regs.regs(1).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "reg(regs.regs(1).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "reg(regs.regs(1).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "reg(regs.regs(1).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "reg(regs.regs(1).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "reg(regs.regs(1).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "reg(regs.regs(1).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "reg(regs.regs(1).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "reg(regs.regs(1).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "reg(regs.regs(1).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "reg(regs.regs(1).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "reg(regs.regs(1).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "reg(regs.regs(1).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "reg(regs.regs(1).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "reg(regs.regs(1).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "reg(regs.regs(1).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "reg(regs.regs(1).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "reg(regs.regs(1).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "reg(regs.regs(1).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "reg(regs.regs(1).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "reg(regs.regs(1).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "reg(regs.regs(1).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "reg(regs.regs(1).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "reg(regs.regs(1).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "reg(regs.regs(1).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "reg(regs.regs(1).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "reg(regs.regs(1).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "reg(regs.regs(1).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "reg(regs.regs(1).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "reg(regs.regs(1).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "reg(regs.regs(1).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "reg(regs.regs(1).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "reg(regs.regs(1).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "reg(regs.regs(1).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "reg(regs.regs(1).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "reg(regs.regs(1).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "reg(regs.regs(1).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "reg(regs.regs(1).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "reg(regs.regs(1).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "reg(regs.regs(1).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "reg(regs.regs(1).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "reg(regs.regs(1).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "reg(regs.regs(1).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "reg(regs.regs(1).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "reg(regs.regs(1).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "reg(regs.regs(1).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "reg(regs.regs(1).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "reg(regs.regs(1).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "reg(regs.regs(1).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "reg(regs.regs(1).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "reg(regs.regs(1).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "reg(regs.regs(1).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "reg(regs.regs(1).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "reg(regs.regs(1).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "reg(regs.regs(1).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "reg(regs.regs(1).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "reg(regs.regs(1).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "reg(regs.regs(1).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "reg(regs.regs(1).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load inst "reg(regs.regs(0).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 11999 -attr oid 387 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva)}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "reg(regs.regs(0).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "reg(regs.regs(0).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "reg(regs.regs(0).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "reg(regs.regs(0).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "reg(regs.regs(0).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "reg(regs.regs(0).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "reg(regs.regs(0).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "reg(regs.regs(0).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "reg(regs.regs(0).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "reg(regs.regs(0).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "reg(regs.regs(0).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "reg(regs.regs(0).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "reg(regs.regs(0).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "reg(regs.regs(0).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "reg(regs.regs(0).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "reg(regs.regs(0).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "reg(regs.regs(0).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "reg(regs.regs(0).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "reg(regs.regs(0).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "reg(regs.regs(0).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "reg(regs.regs(0).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "reg(regs.regs(0).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "reg(regs.regs(0).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "reg(regs.regs(0).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "reg(regs.regs(0).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "reg(regs.regs(0).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "reg(regs.regs(0).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "reg(regs.regs(0).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "reg(regs.regs(0).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "reg(regs.regs(0).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "reg(regs.regs(0).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "reg(regs.regs(0).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "reg(regs.regs(0).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "reg(regs.regs(0).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "reg(regs.regs(0).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "reg(regs.regs(0).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "reg(regs.regs(0).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "reg(regs.regs(0).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "reg(regs.regs(0).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "reg(regs.regs(0).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "reg(regs.regs(0).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "reg(regs.regs(0).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "reg(regs.regs(0).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "reg(regs.regs(0).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "reg(regs.regs(0).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "reg(regs.regs(0).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "reg(regs.regs(0).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "reg(regs.regs(0).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "reg(regs.regs(0).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "reg(regs.regs(0).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "reg(regs.regs(0).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "reg(regs.regs(0).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "reg(regs.regs(0).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "reg(regs.regs(0).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "reg(regs.regs(0).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "reg(regs.regs(0).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "reg(regs.regs(0).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "reg(regs.regs(0).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "reg(regs.regs(0).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "reg(regs.regs(0).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "reg(regs.regs(0).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "reg(regs.regs(0).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "reg(regs.regs(0).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "reg(regs.regs(0).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "reg(regs.regs(0).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "reg(regs.regs(0).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "reg(regs.regs(0).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "reg(regs.regs(0).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "reg(regs.regs(0).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "reg(regs.regs(0).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "reg(regs.regs(0).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "reg(regs.regs(0).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "reg(regs.regs(0).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "reg(regs.regs(0).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "reg(regs.regs(0).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "reg(regs.regs(0).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "reg(regs.regs(0).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "reg(regs.regs(0).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "reg(regs.regs(0).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "reg(regs.regs(0).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "reg(regs.regs(0).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "reg(regs.regs(0).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "reg(regs.regs(0).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "reg(regs.regs(0).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "reg(regs.regs(0).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "reg(regs.regs(0).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "reg(regs.regs(0).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "reg(regs.regs(0).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "reg(regs.regs(0).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "reg(regs.regs(0).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {clk} -pin  "reg(regs.regs(0).sva)" {clk} -attr xrf 12000 -attr oid 388 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(0).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(0).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(0).sva(0)} -pin  "reg(regs.regs(0).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "reg(regs.regs(0).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "reg(regs.regs(0).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "reg(regs.regs(0).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "reg(regs.regs(0).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "reg(regs.regs(0).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "reg(regs.regs(0).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "reg(regs.regs(0).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "reg(regs.regs(0).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "reg(regs.regs(0).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "reg(regs.regs(0).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "reg(regs.regs(0).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "reg(regs.regs(0).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "reg(regs.regs(0).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "reg(regs.regs(0).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "reg(regs.regs(0).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "reg(regs.regs(0).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "reg(regs.regs(0).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "reg(regs.regs(0).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "reg(regs.regs(0).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "reg(regs.regs(0).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "reg(regs.regs(0).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "reg(regs.regs(0).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "reg(regs.regs(0).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "reg(regs.regs(0).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "reg(regs.regs(0).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "reg(regs.regs(0).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "reg(regs.regs(0).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "reg(regs.regs(0).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "reg(regs.regs(0).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "reg(regs.regs(0).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "reg(regs.regs(0).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "reg(regs.regs(0).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "reg(regs.regs(0).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "reg(regs.regs(0).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "reg(regs.regs(0).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "reg(regs.regs(0).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "reg(regs.regs(0).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "reg(regs.regs(0).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "reg(regs.regs(0).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "reg(regs.regs(0).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "reg(regs.regs(0).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "reg(regs.regs(0).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "reg(regs.regs(0).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "reg(regs.regs(0).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "reg(regs.regs(0).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "reg(regs.regs(0).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "reg(regs.regs(0).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "reg(regs.regs(0).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "reg(regs.regs(0).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "reg(regs.regs(0).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "reg(regs.regs(0).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "reg(regs.regs(0).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "reg(regs.regs(0).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "reg(regs.regs(0).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "reg(regs.regs(0).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "reg(regs.regs(0).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "reg(regs.regs(0).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "reg(regs.regs(0).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "reg(regs.regs(0).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "reg(regs.regs(0).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "reg(regs.regs(0).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "reg(regs.regs(0).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "reg(regs.regs(0).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "reg(regs.regs(0).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "reg(regs.regs(0).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "reg(regs.regs(0).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "reg(regs.regs(0).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "reg(regs.regs(0).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "reg(regs.regs(0).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "reg(regs.regs(0).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "reg(regs.regs(0).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "reg(regs.regs(0).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "reg(regs.regs(0).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "reg(regs.regs(0).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "reg(regs.regs(0).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "reg(regs.regs(0).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "reg(regs.regs(0).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "reg(regs.regs(0).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "reg(regs.regs(0).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "reg(regs.regs(0).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "reg(regs.regs(0).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "reg(regs.regs(0).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "reg(regs.regs(0).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "reg(regs.regs(0).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "reg(regs.regs(0).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "reg(regs.regs(0).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "reg(regs.regs(0).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "reg(regs.regs(0).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "reg(regs.regs(0).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load inst "reg(exit:FRAME.lpi#1.dfm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 12001 -attr oid 389 -attr @path {/sobel/sobel:core/reg(exit:FRAME.lpi#1.dfm#1)}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {D(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load net {GND} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {clk} -attr xrf 12002 -attr oid 390 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME.lpi#1.dfm#1} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1}
+load inst "reg(b(2).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 12003 -attr oid 391 -attr vt d -attr @path {/sobel/sobel:core/reg(b(2).sva#1)}
+load net {b(2).sva#3(0)} -pin  "reg(b(2).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(1)} -pin  "reg(b(2).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(2)} -pin  "reg(b(2).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(3)} -pin  "reg(b(2).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(4)} -pin  "reg(b(2).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(5)} -pin  "reg(b(2).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(6)} -pin  "reg(b(2).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(7)} -pin  "reg(b(2).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(8)} -pin  "reg(b(2).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(9)} -pin  "reg(b(2).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(10)} -pin  "reg(b(2).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(11)} -pin  "reg(b(2).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(12)} -pin  "reg(b(2).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(13)} -pin  "reg(b(2).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(14)} -pin  "reg(b(2).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(15)} -pin  "reg(b(2).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(b(2).sva#1)" {clk} -attr xrf 12004 -attr oid 392 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(b(2).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(b(2).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {b(2).sva#1(0)} -pin  "reg(b(2).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(1)} -pin  "reg(b(2).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(2)} -pin  "reg(b(2).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(3)} -pin  "reg(b(2).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(4)} -pin  "reg(b(2).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(5)} -pin  "reg(b(2).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(6)} -pin  "reg(b(2).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(7)} -pin  "reg(b(2).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(8)} -pin  "reg(b(2).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(9)} -pin  "reg(b(2).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(10)} -pin  "reg(b(2).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(11)} -pin  "reg(b(2).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(12)} -pin  "reg(b(2).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(13)} -pin  "reg(b(2).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(14)} -pin  "reg(b(2).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(15)} -pin  "reg(b(2).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load inst "reg(b(0).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 12005 -attr oid 393 -attr vt d -attr @path {/sobel/sobel:core/reg(b(0).sva#1)}
+load net {b(0).sva#3(0)} -pin  "reg(b(0).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(1)} -pin  "reg(b(0).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(2)} -pin  "reg(b(0).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(3)} -pin  "reg(b(0).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(4)} -pin  "reg(b(0).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(5)} -pin  "reg(b(0).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(6)} -pin  "reg(b(0).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(7)} -pin  "reg(b(0).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(8)} -pin  "reg(b(0).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(9)} -pin  "reg(b(0).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(10)} -pin  "reg(b(0).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(11)} -pin  "reg(b(0).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(12)} -pin  "reg(b(0).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(13)} -pin  "reg(b(0).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(14)} -pin  "reg(b(0).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(15)} -pin  "reg(b(0).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(b(0).sva#1)" {clk} -attr xrf 12006 -attr oid 394 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(b(0).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(b(0).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {b(0).sva#1(0)} -pin  "reg(b(0).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(1)} -pin  "reg(b(0).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(2)} -pin  "reg(b(0).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(3)} -pin  "reg(b(0).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(4)} -pin  "reg(b(0).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(5)} -pin  "reg(b(0).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(6)} -pin  "reg(b(0).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(7)} -pin  "reg(b(0).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(8)} -pin  "reg(b(0).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(9)} -pin  "reg(b(0).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(10)} -pin  "reg(b(0).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(11)} -pin  "reg(b(0).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(12)} -pin  "reg(b(0).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(13)} -pin  "reg(b(0).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(14)} -pin  "reg(b(0).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(15)} -pin  "reg(b(0).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load inst "reg(g(2).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 12007 -attr oid 395 -attr vt d -attr @path {/sobel/sobel:core/reg(g(2).sva#1)}
+load net {g(2).sva#3(0)} -pin  "reg(g(2).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(1)} -pin  "reg(g(2).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(2)} -pin  "reg(g(2).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(3)} -pin  "reg(g(2).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(4)} -pin  "reg(g(2).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(5)} -pin  "reg(g(2).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(6)} -pin  "reg(g(2).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(7)} -pin  "reg(g(2).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(8)} -pin  "reg(g(2).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(9)} -pin  "reg(g(2).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(10)} -pin  "reg(g(2).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(11)} -pin  "reg(g(2).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(12)} -pin  "reg(g(2).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(13)} -pin  "reg(g(2).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(14)} -pin  "reg(g(2).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(15)} -pin  "reg(g(2).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(g(2).sva#1)" {clk} -attr xrf 12008 -attr oid 396 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(g(2).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(g(2).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {g(2).sva#1(0)} -pin  "reg(g(2).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(1)} -pin  "reg(g(2).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(2)} -pin  "reg(g(2).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(3)} -pin  "reg(g(2).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(4)} -pin  "reg(g(2).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(5)} -pin  "reg(g(2).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(6)} -pin  "reg(g(2).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(7)} -pin  "reg(g(2).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(8)} -pin  "reg(g(2).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(9)} -pin  "reg(g(2).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(10)} -pin  "reg(g(2).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(11)} -pin  "reg(g(2).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(12)} -pin  "reg(g(2).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(13)} -pin  "reg(g(2).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(14)} -pin  "reg(g(2).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(15)} -pin  "reg(g(2).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load inst "reg(g(0).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 12009 -attr oid 397 -attr vt d -attr @path {/sobel/sobel:core/reg(g(0).sva#1)}
+load net {g(0).sva#3(0)} -pin  "reg(g(0).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(1)} -pin  "reg(g(0).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(2)} -pin  "reg(g(0).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(3)} -pin  "reg(g(0).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(4)} -pin  "reg(g(0).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(5)} -pin  "reg(g(0).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(6)} -pin  "reg(g(0).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(7)} -pin  "reg(g(0).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(8)} -pin  "reg(g(0).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(9)} -pin  "reg(g(0).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(10)} -pin  "reg(g(0).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(11)} -pin  "reg(g(0).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(12)} -pin  "reg(g(0).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(13)} -pin  "reg(g(0).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(14)} -pin  "reg(g(0).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(15)} -pin  "reg(g(0).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(g(0).sva#1)" {clk} -attr xrf 12010 -attr oid 398 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(g(0).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(g(0).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {g(0).sva#1(0)} -pin  "reg(g(0).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(1)} -pin  "reg(g(0).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(2)} -pin  "reg(g(0).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(3)} -pin  "reg(g(0).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(4)} -pin  "reg(g(0).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(5)} -pin  "reg(g(0).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(6)} -pin  "reg(g(0).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(7)} -pin  "reg(g(0).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(8)} -pin  "reg(g(0).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(9)} -pin  "reg(g(0).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(10)} -pin  "reg(g(0).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(11)} -pin  "reg(g(0).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(12)} -pin  "reg(g(0).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(13)} -pin  "reg(g(0).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(14)} -pin  "reg(g(0).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(15)} -pin  "reg(g(0).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load inst "reg(r(2).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 12011 -attr oid 399 -attr vt d -attr @path {/sobel/sobel:core/reg(r(2).sva#1)}
+load net {r(2).sva#3(0)} -pin  "reg(r(2).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(1)} -pin  "reg(r(2).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(2)} -pin  "reg(r(2).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(3)} -pin  "reg(r(2).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(4)} -pin  "reg(r(2).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(5)} -pin  "reg(r(2).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(6)} -pin  "reg(r(2).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(7)} -pin  "reg(r(2).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(8)} -pin  "reg(r(2).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(9)} -pin  "reg(r(2).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(10)} -pin  "reg(r(2).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(11)} -pin  "reg(r(2).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(12)} -pin  "reg(r(2).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(13)} -pin  "reg(r(2).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(14)} -pin  "reg(r(2).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(15)} -pin  "reg(r(2).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(r(2).sva#1)" {clk} -attr xrf 12012 -attr oid 400 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(r(2).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(r(2).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {r(2).sva#1(0)} -pin  "reg(r(2).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(1)} -pin  "reg(r(2).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(2)} -pin  "reg(r(2).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(3)} -pin  "reg(r(2).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(4)} -pin  "reg(r(2).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(5)} -pin  "reg(r(2).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(6)} -pin  "reg(r(2).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(7)} -pin  "reg(r(2).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(8)} -pin  "reg(r(2).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(9)} -pin  "reg(r(2).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(10)} -pin  "reg(r(2).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(11)} -pin  "reg(r(2).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(12)} -pin  "reg(r(2).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(13)} -pin  "reg(r(2).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(14)} -pin  "reg(r(2).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(15)} -pin  "reg(r(2).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load inst "reg(r(0).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 12013 -attr oid 401 -attr vt d -attr @path {/sobel/sobel:core/reg(r(0).sva#1)}
+load net {r(0).sva#3(0)} -pin  "reg(r(0).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(1)} -pin  "reg(r(0).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(2)} -pin  "reg(r(0).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(3)} -pin  "reg(r(0).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(4)} -pin  "reg(r(0).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(5)} -pin  "reg(r(0).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(6)} -pin  "reg(r(0).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(7)} -pin  "reg(r(0).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(8)} -pin  "reg(r(0).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(9)} -pin  "reg(r(0).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(10)} -pin  "reg(r(0).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(11)} -pin  "reg(r(0).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(12)} -pin  "reg(r(0).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(13)} -pin  "reg(r(0).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(14)} -pin  "reg(r(0).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(15)} -pin  "reg(r(0).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(r(0).sva#1)" {clk} -attr xrf 12014 -attr oid 402 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(r(0).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(r(0).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {r(0).sva#1(0)} -pin  "reg(r(0).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(1)} -pin  "reg(r(0).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(2)} -pin  "reg(r(0).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(3)} -pin  "reg(r(0).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(4)} -pin  "reg(r(0).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(5)} -pin  "reg(r(0).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(6)} -pin  "reg(r(0).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(7)} -pin  "reg(r(0).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(8)} -pin  "reg(r(0).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(9)} -pin  "reg(r(0).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(10)} -pin  "reg(r(0).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(11)} -pin  "reg(r(0).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(12)} -pin  "reg(r(0).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(13)} -pin  "reg(r(0).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(14)} -pin  "reg(r(0).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(15)} -pin  "reg(r(0).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load inst "mux#5" "mux(2,19)" "INTERFACE" -attr xrf 12015 -attr oid 403 -attr vt d -attr @path {/sobel/sobel:core/mux#5} -attr area 17.470037 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2)"
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "mux#5" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "mux#5" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "mux#5" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "mux#5" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "mux#5" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "mux#5" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "mux#5" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "mux#5" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "mux#5" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "mux#5" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "mux#5" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "mux#5" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "mux#5" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "mux#5" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "mux#5" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "mux#5" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "mux#5" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "mux#5" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "mux#5" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.sva#1(0)} -pin  "mux#5" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "mux#5" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "mux#5" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "mux#5" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "mux#5" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "mux#5" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "mux#5" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "mux#5" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "mux#5" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "mux#5" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "mux#5" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "mux#5" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "mux#5" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "mux#5" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "mux#5" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "mux#5" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "mux#5" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "mux#5" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "mux#5" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:for:acc.itm(1)} -pin  "mux#5" {S(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#15.itm}
+load net {mux#5.itm(0)} -pin  "mux#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(1)} -pin  "mux#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(2)} -pin  "mux#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(3)} -pin  "mux#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(4)} -pin  "mux#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(5)} -pin  "mux#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(6)} -pin  "mux#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(7)} -pin  "mux#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(8)} -pin  "mux#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(9)} -pin  "mux#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(10)} -pin  "mux#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(11)} -pin  "mux#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(12)} -pin  "mux#5" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(13)} -pin  "mux#5" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(14)} -pin  "mux#5" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(15)} -pin  "mux#5" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(16)} -pin  "mux#5" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(17)} -pin  "mux#5" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(18)} -pin  "mux#5" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load inst "reg(FRAME:p#1.lpi#1)" "reg(19,1,1,-1,0)" "INTERFACE" -attr xrf 12016 -attr oid 404 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:p#1.lpi#1)}
+load net {mux#5.itm(0)} -pin  "reg(FRAME:p#1.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(1)} -pin  "reg(FRAME:p#1.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(2)} -pin  "reg(FRAME:p#1.lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(3)} -pin  "reg(FRAME:p#1.lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(4)} -pin  "reg(FRAME:p#1.lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(5)} -pin  "reg(FRAME:p#1.lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(6)} -pin  "reg(FRAME:p#1.lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(7)} -pin  "reg(FRAME:p#1.lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(8)} -pin  "reg(FRAME:p#1.lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(9)} -pin  "reg(FRAME:p#1.lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(10)} -pin  "reg(FRAME:p#1.lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(11)} -pin  "reg(FRAME:p#1.lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(12)} -pin  "reg(FRAME:p#1.lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(13)} -pin  "reg(FRAME:p#1.lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(14)} -pin  "reg(FRAME:p#1.lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(15)} -pin  "reg(FRAME:p#1.lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(16)} -pin  "reg(FRAME:p#1.lpi#1)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(17)} -pin  "reg(FRAME:p#1.lpi#1)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {mux#5.itm(18)} -pin  "reg(FRAME:p#1.lpi#1)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#5.itm}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_19}
+load net {clk} -pin  "reg(FRAME:p#1.lpi#1)" {clk} -attr xrf 12017 -attr oid 405 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:p#1.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:p#1.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:p#1.lpi#1(0)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load inst "FRAME:acc#26" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 12018 -attr oid 406 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {FRAME:slc(green)#10.itm#1(0)} -pin  "FRAME:acc#26" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(green)#10.itm#1}
+load net {FRAME:slc(green)#10.itm#1(1)} -pin  "FRAME:acc#26" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(green)#10.itm#1}
+load net {FRAME:slc(green)#10.itm#1(2)} -pin  "FRAME:acc#26" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(green)#10.itm#1}
+load net {FRAME:slc(green)#10.itm#1(3)} -pin  "FRAME:acc#26" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(green)#10.itm#1}
+load net {FRAME:slc(green)#10.itm#1(4)} -pin  "FRAME:acc#26" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(green)#10.itm#1}
+load net {FRAME:slc(green)#10.itm#1(5)} -pin  "FRAME:acc#26" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:slc(green)#10.itm#1}
+load net {FRAME:acc#25.itm#1(0)} -pin  "FRAME:acc#26" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm#1}
+load net {FRAME:acc#25.itm#1(1)} -pin  "FRAME:acc#26" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm#1}
+load net {FRAME:acc#25.itm#1(2)} -pin  "FRAME:acc#26" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm#1}
+load net {FRAME:acc#25.itm#1(3)} -pin  "FRAME:acc#26" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm#1}
+load net {FRAME:acc#25.itm#1(4)} -pin  "FRAME:acc#26" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm#1}
+load net {FRAME:acc#26.itm(0)} -pin  "FRAME:acc#26" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(1)} -pin  "FRAME:acc#26" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(2)} -pin  "FRAME:acc#26" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(3)} -pin  "FRAME:acc#26" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(4)} -pin  "FRAME:acc#26" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(5)} -pin  "FRAME:acc#26" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(6)} -pin  "FRAME:acc#26" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(7)} -pin  "FRAME:acc#26" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load inst "FRAME:acc#27" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 12019 -attr oid 407 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul#2.itm#1(0)} -pin  "FRAME:acc#27" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(1)} -pin  "FRAME:acc#27" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(2)} -pin  "FRAME:acc#27" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(3)} -pin  "FRAME:acc#27" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(4)} -pin  "FRAME:acc#27" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(5)} -pin  "FRAME:acc#27" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(6)} -pin  "FRAME:acc#27" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(7)} -pin  "FRAME:acc#27" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(8)} -pin  "FRAME:acc#27" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:acc#26.itm(0)} -pin  "FRAME:acc#27" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(1)} -pin  "FRAME:acc#27" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(2)} -pin  "FRAME:acc#27" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(3)} -pin  "FRAME:acc#27" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(4)} -pin  "FRAME:acc#27" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(5)} -pin  "FRAME:acc#27" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(6)} -pin  "FRAME:acc#27" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(7)} -pin  "FRAME:acc#27" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#27.itm(0)} -pin  "FRAME:acc#27" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(1)} -pin  "FRAME:acc#27" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(2)} -pin  "FRAME:acc#27" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(3)} -pin  "FRAME:acc#27" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(4)} -pin  "FRAME:acc#27" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(5)} -pin  "FRAME:acc#27" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(6)} -pin  "FRAME:acc#27" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(7)} -pin  "FRAME:acc#27" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(8)} -pin  "FRAME:acc#27" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(9)} -pin  "FRAME:acc#27" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load inst "FRAME:acc#3" "add(10,1,12,-1,12)" "INTERFACE" -attr xrf 12020 -attr oid 408 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {FRAME:acc#27.itm(0)} -pin  "FRAME:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(1)} -pin  "FRAME:acc#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(2)} -pin  "FRAME:acc#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(3)} -pin  "FRAME:acc#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(4)} -pin  "FRAME:acc#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(5)} -pin  "FRAME:acc#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(6)} -pin  "FRAME:acc#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(7)} -pin  "FRAME:acc#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(8)} -pin  "FRAME:acc#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(9)} -pin  "FRAME:acc#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:mul#3.itm#1(0)} -pin  "FRAME:acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(1)} -pin  "FRAME:acc#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(2)} -pin  "FRAME:acc#3" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(3)} -pin  "FRAME:acc#3" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(4)} -pin  "FRAME:acc#3" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(5)} -pin  "FRAME:acc#3" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(6)} -pin  "FRAME:acc#3" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(7)} -pin  "FRAME:acc#3" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(8)} -pin  "FRAME:acc#3" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(9)} -pin  "FRAME:acc#3" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(10)} -pin  "FRAME:acc#3" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(11)} -pin  "FRAME:acc#3" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:acc#3.psp.sva(0)} -pin  "FRAME:acc#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#3.psp.sva(1)} -pin  "FRAME:acc#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#3.psp.sva(2)} -pin  "FRAME:acc#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#3.psp.sva(3)} -pin  "FRAME:acc#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#3.psp.sva(4)} -pin  "FRAME:acc#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#3.psp.sva(5)} -pin  "FRAME:acc#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#3.psp.sva(6)} -pin  "FRAME:acc#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#3.psp.sva(7)} -pin  "FRAME:acc#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#3.psp.sva(8)} -pin  "FRAME:acc#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#3.psp.sva(9)} -pin  "FRAME:acc#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#3.psp.sva(10)} -pin  "FRAME:acc#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#3.psp.sva(11)} -pin  "FRAME:acc#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load inst "FRAME:for:acc" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 12021 -attr oid 409 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2)"
+load net {i#6.sva#2(0)} -pin  "FRAME:for:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "FRAME:for:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {PWR} -pin  "FRAME:for:acc" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:for:acc.itm(0)} -pin  "FRAME:for:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+load inst "FRAME:for:acc#16" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 12022 -attr oid 410 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#16} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:for:acc#16" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {i#6.sva#2(0)} -pin  "FRAME:for:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "FRAME:for:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load inst "not#33" "not(1)" "INTERFACE" -attr xrf 12023 -attr oid 411 -attr @path {/sobel/sobel:core/not#33} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "not#33" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {not#33.itm} -pin  "not#33" {Z(0)} -attr @path {/sobel/sobel:core/not#33.itm}
+load inst "FRAME:for:and#1" "and(2,2)" "INTERFACE" -attr xrf 12024 -attr oid 412 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#1} -attr area 1.459665 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2)"
+load net {i#6.sva#1(0)} -pin  "FRAME:for:and#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "FRAME:for:and#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {not#33.itm} -pin  "FRAME:for:and#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#19.itm}
+load net {not#33.itm} -pin  "FRAME:for:and#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#19.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:and#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:and#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load inst "FRAME:for:or" "or(2,1)" "INTERFACE" -attr xrf 12025 -attr oid 413 -attr @path {/sobel/sobel:core/FRAME:for:or} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "FRAME:for:or" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {exit:FRAME#1.sva} -pin  "FRAME:for:or" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:or" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load inst "mux#1" "mux(2,90)" "INTERFACE" -attr xrf 12026 -attr oid 414 -attr vt dc -attr @path {/sobel/sobel:core/mux#1} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(2).lpi#1.dfm(0)} -pin  "mux#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(1)} -pin  "mux#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(2)} -pin  "mux#1" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(3)} -pin  "mux#1" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(4)} -pin  "mux#1" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(5)} -pin  "mux#1" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(6)} -pin  "mux#1" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(7)} -pin  "mux#1" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(8)} -pin  "mux#1" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(9)} -pin  "mux#1" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(10)} -pin  "mux#1" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(11)} -pin  "mux#1" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(12)} -pin  "mux#1" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(13)} -pin  "mux#1" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(14)} -pin  "mux#1" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(15)} -pin  "mux#1" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(16)} -pin  "mux#1" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(17)} -pin  "mux#1" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(18)} -pin  "mux#1" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(19)} -pin  "mux#1" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(20)} -pin  "mux#1" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(21)} -pin  "mux#1" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(22)} -pin  "mux#1" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(23)} -pin  "mux#1" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(24)} -pin  "mux#1" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(25)} -pin  "mux#1" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(26)} -pin  "mux#1" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(27)} -pin  "mux#1" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(28)} -pin  "mux#1" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(29)} -pin  "mux#1" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(30)} -pin  "mux#1" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(31)} -pin  "mux#1" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(32)} -pin  "mux#1" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(33)} -pin  "mux#1" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(34)} -pin  "mux#1" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(35)} -pin  "mux#1" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(36)} -pin  "mux#1" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(37)} -pin  "mux#1" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(38)} -pin  "mux#1" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(39)} -pin  "mux#1" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(40)} -pin  "mux#1" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(41)} -pin  "mux#1" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(42)} -pin  "mux#1" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(43)} -pin  "mux#1" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(44)} -pin  "mux#1" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(45)} -pin  "mux#1" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(46)} -pin  "mux#1" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(47)} -pin  "mux#1" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(48)} -pin  "mux#1" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(49)} -pin  "mux#1" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(50)} -pin  "mux#1" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(51)} -pin  "mux#1" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(52)} -pin  "mux#1" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(53)} -pin  "mux#1" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(54)} -pin  "mux#1" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(55)} -pin  "mux#1" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(56)} -pin  "mux#1" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(57)} -pin  "mux#1" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(58)} -pin  "mux#1" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(59)} -pin  "mux#1" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(60)} -pin  "mux#1" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(61)} -pin  "mux#1" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(62)} -pin  "mux#1" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(63)} -pin  "mux#1" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(64)} -pin  "mux#1" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(65)} -pin  "mux#1" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(66)} -pin  "mux#1" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(67)} -pin  "mux#1" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(68)} -pin  "mux#1" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(69)} -pin  "mux#1" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(70)} -pin  "mux#1" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(71)} -pin  "mux#1" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(72)} -pin  "mux#1" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(73)} -pin  "mux#1" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(74)} -pin  "mux#1" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(75)} -pin  "mux#1" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(76)} -pin  "mux#1" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(77)} -pin  "mux#1" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(78)} -pin  "mux#1" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(79)} -pin  "mux#1" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(80)} -pin  "mux#1" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(81)} -pin  "mux#1" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(82)} -pin  "mux#1" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(83)} -pin  "mux#1" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(84)} -pin  "mux#1" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(85)} -pin  "mux#1" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(86)} -pin  "mux#1" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(87)} -pin  "mux#1" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(88)} -pin  "mux#1" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(89)} -pin  "mux#1" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(1).sva(0)} -pin  "mux#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "mux#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "mux#1" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "mux#1" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "mux#1" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "mux#1" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "mux#1" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "mux#1" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "mux#1" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "mux#1" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "mux#1" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "mux#1" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "mux#1" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "mux#1" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "mux#1" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "mux#1" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "mux#1" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "mux#1" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "mux#1" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "mux#1" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "mux#1" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "mux#1" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "mux#1" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "mux#1" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "mux#1" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "mux#1" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "mux#1" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "mux#1" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "mux#1" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "mux#1" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "mux#1" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "mux#1" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "mux#1" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "mux#1" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "mux#1" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "mux#1" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "mux#1" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "mux#1" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "mux#1" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "mux#1" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "mux#1" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "mux#1" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "mux#1" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "mux#1" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "mux#1" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "mux#1" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "mux#1" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "mux#1" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "mux#1" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "mux#1" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "mux#1" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "mux#1" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "mux#1" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "mux#1" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "mux#1" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "mux#1" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "mux#1" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "mux#1" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "mux#1" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "mux#1" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "mux#1" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "mux#1" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "mux#1" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "mux#1" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "mux#1" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "mux#1" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "mux#1" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "mux#1" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "mux#1" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "mux#1" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "mux#1" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "mux#1" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "mux#1" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "mux#1" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "mux#1" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "mux#1" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "mux#1" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "mux#1" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "mux#1" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "mux#1" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "mux#1" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "mux#1" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "mux#1" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "mux#1" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "mux#1" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "mux#1" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "mux#1" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "mux#1" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "mux#1" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "mux#1" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {and.dcpl} -pin  "mux#1" {S(0)} -attr vt c -attr @path {/sobel/sobel:core/and.dcpl}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "mux#1" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "mux#1" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "mux#1" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "mux#1" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "mux#1" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "mux#1" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "mux#1" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "mux#1" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "mux#1" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "mux#1" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "mux#1" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "mux#1" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "mux#1" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "mux#1" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "mux#1" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "mux#1" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "mux#1" {Z(16)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "mux#1" {Z(17)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "mux#1" {Z(18)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "mux#1" {Z(19)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "mux#1" {Z(20)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "mux#1" {Z(21)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "mux#1" {Z(22)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "mux#1" {Z(23)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "mux#1" {Z(24)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "mux#1" {Z(25)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "mux#1" {Z(26)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "mux#1" {Z(27)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "mux#1" {Z(28)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "mux#1" {Z(29)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "mux#1" {Z(30)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "mux#1" {Z(31)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "mux#1" {Z(32)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "mux#1" {Z(33)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "mux#1" {Z(34)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "mux#1" {Z(35)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "mux#1" {Z(36)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "mux#1" {Z(37)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "mux#1" {Z(38)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "mux#1" {Z(39)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "mux#1" {Z(40)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "mux#1" {Z(41)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "mux#1" {Z(42)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "mux#1" {Z(43)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "mux#1" {Z(44)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "mux#1" {Z(45)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "mux#1" {Z(46)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "mux#1" {Z(47)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "mux#1" {Z(48)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "mux#1" {Z(49)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "mux#1" {Z(50)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "mux#1" {Z(51)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "mux#1" {Z(52)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "mux#1" {Z(53)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "mux#1" {Z(54)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "mux#1" {Z(55)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "mux#1" {Z(56)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "mux#1" {Z(57)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "mux#1" {Z(58)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "mux#1" {Z(59)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "mux#1" {Z(60)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "mux#1" {Z(61)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "mux#1" {Z(62)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "mux#1" {Z(63)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "mux#1" {Z(64)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "mux#1" {Z(65)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "mux#1" {Z(66)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "mux#1" {Z(67)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "mux#1" {Z(68)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "mux#1" {Z(69)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "mux#1" {Z(70)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "mux#1" {Z(71)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "mux#1" {Z(72)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "mux#1" {Z(73)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "mux#1" {Z(74)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "mux#1" {Z(75)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "mux#1" {Z(76)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "mux#1" {Z(77)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "mux#1" {Z(78)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "mux#1" {Z(79)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "mux#1" {Z(80)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "mux#1" {Z(81)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "mux#1" {Z(82)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "mux#1" {Z(83)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "mux#1" {Z(84)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "mux#1" {Z(85)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "mux#1" {Z(86)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "mux#1" {Z(87)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "mux#1" {Z(88)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "mux#1" {Z(89)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load inst "mux#2" "mux(2,90)" "INTERFACE" -attr xrf 12027 -attr oid 415 -attr vt d -attr @path {/sobel/sobel:core/mux#2} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(1).sva(0)} -pin  "mux#2" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "mux#2" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "mux#2" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "mux#2" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "mux#2" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "mux#2" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "mux#2" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "mux#2" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "mux#2" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "mux#2" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "mux#2" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "mux#2" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "mux#2" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "mux#2" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "mux#2" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "mux#2" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "mux#2" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "mux#2" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "mux#2" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "mux#2" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "mux#2" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "mux#2" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "mux#2" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "mux#2" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "mux#2" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "mux#2" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "mux#2" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "mux#2" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "mux#2" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "mux#2" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "mux#2" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "mux#2" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "mux#2" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "mux#2" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "mux#2" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "mux#2" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "mux#2" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "mux#2" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "mux#2" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "mux#2" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "mux#2" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "mux#2" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "mux#2" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "mux#2" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "mux#2" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "mux#2" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "mux#2" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "mux#2" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "mux#2" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "mux#2" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "mux#2" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "mux#2" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "mux#2" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "mux#2" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "mux#2" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "mux#2" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "mux#2" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "mux#2" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "mux#2" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "mux#2" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "mux#2" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "mux#2" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "mux#2" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "mux#2" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "mux#2" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "mux#2" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "mux#2" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "mux#2" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "mux#2" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "mux#2" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "mux#2" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "mux#2" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "mux#2" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "mux#2" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "mux#2" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "mux#2" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "mux#2" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "mux#2" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "mux#2" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "mux#2" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "mux#2" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "mux#2" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "mux#2" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "mux#2" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "mux#2" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "mux#2" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "mux#2" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "mux#2" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "mux#2" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "mux#2" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -pin  "mux#2" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#2" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#2" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#2" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#2" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#2" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#2" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#2" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#2" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#2" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#2" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#2" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#2" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#2" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#2" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#2" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#2" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#2" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#2" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#2" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#2" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#2" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#2" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#2" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#2" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#2" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#2" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#2" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#2" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#2" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#2" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#2" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#2" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#2" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#2" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#2" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#2" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#2" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#2" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#2" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#2" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#2" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#2" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#2" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#2" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#2" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#2" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#2" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#2" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#2" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#2" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#2" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#2" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#2" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#2" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#2" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#2" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#2" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#2" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#2" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#2" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#2" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#2" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#2" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#2" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#2" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#2" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#2" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#2" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#2" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#2" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#2" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#2" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#2" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#2" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#2" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#2" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#2" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#2" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#2" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#2" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#2" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#2" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#2" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#2" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#2" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#2" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#2" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#2" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#2" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {and.dcpl} -pin  "mux#2" {S(0)} -attr @path {/sobel/sobel:core/and.dcpl}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "mux#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "mux#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "mux#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "mux#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "mux#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "mux#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "mux#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "mux#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "mux#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "mux#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "mux#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "mux#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "mux#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "mux#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "mux#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "mux#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "mux#2" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "mux#2" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "mux#2" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "mux#2" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "mux#2" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "mux#2" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "mux#2" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "mux#2" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "mux#2" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "mux#2" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "mux#2" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "mux#2" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "mux#2" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "mux#2" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "mux#2" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "mux#2" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "mux#2" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "mux#2" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "mux#2" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "mux#2" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "mux#2" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "mux#2" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "mux#2" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "mux#2" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "mux#2" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "mux#2" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "mux#2" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "mux#2" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "mux#2" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "mux#2" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "mux#2" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "mux#2" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "mux#2" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "mux#2" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "mux#2" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "mux#2" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "mux#2" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "mux#2" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "mux#2" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "mux#2" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "mux#2" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "mux#2" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "mux#2" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "mux#2" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "mux#2" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "mux#2" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "mux#2" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "mux#2" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "mux#2" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "mux#2" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "mux#2" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "mux#2" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "mux#2" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "mux#2" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "mux#2" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "mux#2" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "mux#2" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "mux#2" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "mux#2" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "mux#2" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "mux#2" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "mux#2" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "mux#2" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "mux#2" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "mux#2" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "mux#2" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "mux#2" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "mux#2" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "mux#2" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "mux#2" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "mux#2" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "mux#2" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "mux#2" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "mux#2" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load inst "mux#3" "mux(2,90)" "INTERFACE" -attr xrf 12028 -attr oid 416 -attr vt d -attr @path {/sobel/sobel:core/mux#3} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(0).sva(0)} -pin  "mux#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#3" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#3" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#3" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#3" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#3" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#3" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#3" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#3" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#3" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#3" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#3" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#3" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#3" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#3" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#3" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#3" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#3" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#3" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#3" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#3" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#3" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#3" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#3" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#3" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#3" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#3" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#3" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#3" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#3" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#3" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#3" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#3" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#3" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#3" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#3" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#3" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#3" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#3" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#3" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#3" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#3" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#3" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#3" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#3" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#3" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#3" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#3" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#3" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#3" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#3" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#3" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#3" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#3" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#3" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#3" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#3" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#3" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#3" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#3" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#3" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#3" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#3" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#3" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#3" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#3" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#3" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#3" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#3" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#3" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#3" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#3" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#3" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#3" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#3" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#3" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#3" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#3" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#3" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#3" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#3" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#3" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#3" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#3" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#3" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#3" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "mux#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "mux#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "mux#3" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "mux#3" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "mux#3" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "mux#3" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "mux#3" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "mux#3" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "mux#3" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "mux#3" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "mux#3" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "mux#3" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "mux#3" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "mux#3" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "mux#3" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "mux#3" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "mux#3" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "mux#3" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "mux#3" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "mux#3" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "mux#3" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "mux#3" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "mux#3" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "mux#3" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "mux#3" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "mux#3" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "mux#3" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "mux#3" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "mux#3" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "mux#3" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "mux#3" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "mux#3" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "mux#3" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "mux#3" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "mux#3" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "mux#3" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "mux#3" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "mux#3" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "mux#3" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "mux#3" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "mux#3" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "mux#3" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "mux#3" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "mux#3" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "mux#3" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "mux#3" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "mux#3" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "mux#3" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "mux#3" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "mux#3" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "mux#3" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "mux#3" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "mux#3" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "mux#3" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "mux#3" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "mux#3" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "mux#3" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "mux#3" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "mux#3" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "mux#3" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "mux#3" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "mux#3" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "mux#3" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "mux#3" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "mux#3" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "mux#3" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "mux#3" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "mux#3" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "mux#3" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "mux#3" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "mux#3" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "mux#3" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "mux#3" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "mux#3" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "mux#3" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "mux#3" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "mux#3" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "mux#3" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "mux#3" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "mux#3" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "mux#3" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "mux#3" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "mux#3" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "mux#3" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "mux#3" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "mux#3" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "mux#3" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "mux#3" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "mux#3" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "mux#3" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {and.dcpl} -pin  "mux#3" {S(0)} -attr @path {/sobel/sobel:core/and.dcpl}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "mux#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "mux#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "mux#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "mux#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "mux#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "mux#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "mux#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "mux#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "mux#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "mux#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "mux#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "mux#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "mux#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "mux#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "mux#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "mux#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "mux#3" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "mux#3" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "mux#3" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "mux#3" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "mux#3" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "mux#3" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "mux#3" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "mux#3" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "mux#3" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "mux#3" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "mux#3" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "mux#3" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "mux#3" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "mux#3" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "mux#3" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "mux#3" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "mux#3" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "mux#3" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "mux#3" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "mux#3" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "mux#3" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "mux#3" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "mux#3" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "mux#3" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "mux#3" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "mux#3" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "mux#3" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "mux#3" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "mux#3" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "mux#3" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "mux#3" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "mux#3" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "mux#3" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "mux#3" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "mux#3" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "mux#3" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "mux#3" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "mux#3" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "mux#3" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "mux#3" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "mux#3" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "mux#3" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "mux#3" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "mux#3" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "mux#3" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "mux#3" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "mux#3" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "mux#3" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "mux#3" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "mux#3" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "mux#3" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "mux#3" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "mux#3" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "mux#3" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "mux#3" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "mux#3" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "mux#3" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "mux#3" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "mux#3" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "mux#3" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "mux#3" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "mux#3" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "mux#3" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "mux#3" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "mux#3" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "mux#3" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "mux#3" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "mux#3" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "mux#3" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "mux#3" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "mux#3" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "mux#3" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "mux#3" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "mux#3" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load inst "not#16" "not(1)" "INTERFACE" -attr xrf 12029 -attr oid 417 -attr @path {/sobel/sobel:core/not#16} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "not#16" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {not#16.itm} -pin  "not#16" {Z(0)} -attr @path {/sobel/sobel:core/not#16.itm}
+load inst "FRAME:for:and#2" "and(2,1)" "INTERFACE" -attr xrf 12030 -attr oid 418 -attr @path {/sobel/sobel:core/FRAME:for:and#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {exit:FRAME.lpi#1.dfm#1} -pin  "FRAME:for:and#2" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1}
+load net {not#16.itm} -pin  "FRAME:for:and#2" {A1(0)} -attr @path {/sobel/sobel:core/not#16.itm}
+load net {FRAME:for:and#2.itm} -pin  "FRAME:for:and#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#2.itm}
+load inst "FRAME:acc" "add(7,0,8,-1,8)" "INTERFACE" -attr xrf 12031 -attr oid 419 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc} -attr area 9.262368 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,7,0,8)"
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {PWR} -pin  "FRAME:acc" {B(0)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(1)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(2)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(3)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(4)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(5)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(6)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(7)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {FRAME:acc.itm(0)} -pin  "FRAME:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(1)} -pin  "FRAME:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(2)} -pin  "FRAME:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(3)} -pin  "FRAME:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(4)} -pin  "FRAME:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(5)} -pin  "FRAME:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(6)} -pin  "FRAME:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(7)} -pin  "FRAME:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load inst "FRAME:not" "not(1)" "INTERFACE" -attr xrf 12032 -attr oid 420 -attr @path {/sobel/sobel:core/FRAME:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc.itm(7)} -pin  "FRAME:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc.itm}
+load net {FRAME:not.itm} -pin  "FRAME:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load inst "mux#4" "mux(2,1)" "INTERFACE" -attr xrf 12033 -attr oid 421 -attr @path {/sobel/sobel:core/mux#4} -attr area 0.920423 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2)"
+load net {FRAME:for:and#2.itm} -pin  "mux#4" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#2.itm}
+load net {FRAME:not.itm} -pin  "mux#4" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "mux#4" {S(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc.itm}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "mux#4" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load inst "FRAME:acc#6" "add(19,-1,1,0,19)" "INTERFACE" -attr xrf 12034 -attr oid 422 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6} -attr area 20.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19)"
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "FRAME:acc#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "FRAME:acc#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "FRAME:acc#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "FRAME:acc#6" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "FRAME:acc#6" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "FRAME:acc#6" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "FRAME:acc#6" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "FRAME:acc#6" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "FRAME:acc#6" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "FRAME:acc#6" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "FRAME:acc#6" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "FRAME:acc#6" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "FRAME:acc#6" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "FRAME:acc#6" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "FRAME:acc#6" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "FRAME:acc#6" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "FRAME:acc#6" {A(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "FRAME:acc#6" {A(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "FRAME:acc#6" {A(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:acc#6" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:p#1.sva#1(0)} -pin  "FRAME:acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "FRAME:acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "FRAME:acc#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "FRAME:acc#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "FRAME:acc#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "FRAME:acc#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "FRAME:acc#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "FRAME:acc#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "FRAME:acc#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "FRAME:acc#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "FRAME:acc#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "FRAME:acc#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc#6" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc#6" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc#6" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc#6" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc#6" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc#6" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc#6" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load inst "FRAME:not#28" "not(1)" "INTERFACE" -attr xrf 12035 -attr oid 423 -attr @path {/sobel/sobel:core/FRAME:not#28} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME#1.sva} -pin  "FRAME:not#28" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {FRAME:not#28.itm} -pin  "FRAME:not#28" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#28.itm}
+load inst "FRAME:for:and" "and(2,19)" "INTERFACE" -attr xrf 12036 -attr oid 424 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and} -attr area 13.866816 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2)"
+load net {FRAME:p#1.lpi#1(0)} -pin  "FRAME:for:and" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "FRAME:for:and" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "FRAME:for:and" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "FRAME:for:and" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "FRAME:for:and" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "FRAME:for:and" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "FRAME:for:and" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "FRAME:for:and" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "FRAME:for:and" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "FRAME:for:and" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "FRAME:for:and" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "FRAME:for:and" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "FRAME:for:and" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "FRAME:for:and" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "FRAME:for:and" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "FRAME:for:and" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "FRAME:for:and" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "FRAME:for:and" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "FRAME:for:and" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:for:and" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "FRAME:for:and" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "FRAME:for:and" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "FRAME:for:and" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "FRAME:for:and" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "FRAME:for:and" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "FRAME:for:and" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "FRAME:for:and" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "FRAME:for:and" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "FRAME:for:and" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "FRAME:for:and" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "FRAME:for:and" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "FRAME:for:and" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "FRAME:for:and" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "FRAME:for:and" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "FRAME:for:and" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "FRAME:for:and" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "FRAME:for:and" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "FRAME:for:and" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "FRAME:for:and" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load inst "ACC1:not#19" "not(10)" "INTERFACE" -attr xrf 12037 -attr oid 425 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#19} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "ACC1:not#19" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "ACC1:not#19" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "ACC1:not#19" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "ACC1:not#19" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "ACC1:not#19" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "ACC1:not#19" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "ACC1:not#19" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "ACC1:not#19" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "ACC1:not#19" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "ACC1:not#19" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {ACC1:not#19.itm(0)} -pin  "ACC1:not#19" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#19.itm}
+load net {ACC1:not#19.itm(1)} -pin  "ACC1:not#19" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#19.itm}
+load net {ACC1:not#19.itm(2)} -pin  "ACC1:not#19" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#19.itm}
+load net {ACC1:not#19.itm(3)} -pin  "ACC1:not#19" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#19.itm}
+load net {ACC1:not#19.itm(4)} -pin  "ACC1:not#19" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#19.itm}
+load net {ACC1:not#19.itm(5)} -pin  "ACC1:not#19" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#19.itm}
+load net {ACC1:not#19.itm(6)} -pin  "ACC1:not#19" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#19.itm}
+load net {ACC1:not#19.itm(7)} -pin  "ACC1:not#19" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#19.itm}
+load net {ACC1:not#19.itm(8)} -pin  "ACC1:not#19" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#19.itm}
+load net {ACC1:not#19.itm(9)} -pin  "ACC1:not#19" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#19.itm}
+load inst "acc" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 12038 -attr oid 426 -attr vt d -attr @path {/sobel/sobel:core/acc} -attr area 12.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "acc" {A(0)} -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#19.itm(0)} -pin  "acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#19.itm(1)} -pin  "acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#19.itm(2)} -pin  "acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#19.itm(3)} -pin  "acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#19.itm(4)} -pin  "acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#19.itm(5)} -pin  "acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#19.itm(6)} -pin  "acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#19.itm(7)} -pin  "acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#19.itm(8)} -pin  "acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {ACC1:not#19.itm(9)} -pin  "acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {PWR} -pin  "acc" {B(0)} -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {acc.itm(0)} -pin  "acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(1)} -pin  "acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(2)} -pin  "acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(3)} -pin  "acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(4)} -pin  "acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(5)} -pin  "acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(6)} -pin  "acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(7)} -pin  "acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(8)} -pin  "acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(9)} -pin  "acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(10)} -pin  "acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(11)} -pin  "acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load inst "ACC1:acc#67" "add(11,1,15,-1,15)" "INTERFACE" -attr xrf 12039 -attr oid 427 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67} -attr area 16.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {acc.itm(1)} -pin  "ACC1:acc#67" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(2)} -pin  "ACC1:acc#67" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(3)} -pin  "ACC1:acc#67" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(4)} -pin  "ACC1:acc#67" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(5)} -pin  "ACC1:acc#67" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(6)} -pin  "ACC1:acc#67" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(7)} -pin  "ACC1:acc#67" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(8)} -pin  "ACC1:acc#67" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(9)} -pin  "ACC1:acc#67" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(10)} -pin  "ACC1:acc#67" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(11)} -pin  "ACC1:acc#67" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {b(2).sva#3(1)} -pin  "ACC1:acc#67" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(2)} -pin  "ACC1:acc#67" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(3)} -pin  "ACC1:acc#67" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(4)} -pin  "ACC1:acc#67" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(5)} -pin  "ACC1:acc#67" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(6)} -pin  "ACC1:acc#67" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(7)} -pin  "ACC1:acc#67" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(8)} -pin  "ACC1:acc#67" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(9)} -pin  "ACC1:acc#67" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(10)} -pin  "ACC1:acc#67" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(11)} -pin  "ACC1:acc#67" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(12)} -pin  "ACC1:acc#67" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(13)} -pin  "ACC1:acc#67" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(14)} -pin  "ACC1:acc#67" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#3(15)} -pin  "ACC1:acc#67" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {ACC1:acc#67.itm(0)} -pin  "ACC1:acc#67" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(1)} -pin  "ACC1:acc#67" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(2)} -pin  "ACC1:acc#67" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(3)} -pin  "ACC1:acc#67" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(4)} -pin  "ACC1:acc#67" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(5)} -pin  "ACC1:acc#67" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(6)} -pin  "ACC1:acc#67" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(7)} -pin  "ACC1:acc#67" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(8)} -pin  "ACC1:acc#67" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(9)} -pin  "ACC1:acc#67" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(10)} -pin  "ACC1:acc#67" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(11)} -pin  "ACC1:acc#67" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(12)} -pin  "ACC1:acc#67" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(13)} -pin  "ACC1:acc#67" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load net {ACC1:acc#67.itm(14)} -pin  "ACC1:acc#67" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#67.itm}
+load inst "ACC1:acc#66" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 12040 -attr oid 428 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {PWR} -pin  "ACC1:acc#66" {A(0)} -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {b(2).sva#3(0)} -pin  "ACC1:acc#66" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {PWR} -pin  "ACC1:acc#66" {B(0)} -attr @path {/sobel/sobel:core/Cn1_1#3}
+load net {ACC1:acc#66.itm(0)} -pin  "ACC1:acc#66" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load net {ACC1:acc#66.itm(1)} -pin  "ACC1:acc#66" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#66.itm}
+load inst "ACC2-3:acc#3" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 12041 -attr oid 429 -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {ACC1:acc#66.itm(1)} -pin  "ACC2-3:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(0)} -pin  "ACC2-3:acc#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(1)} -pin  "ACC2-3:acc#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(2)} -pin  "ACC2-3:acc#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(3)} -pin  "ACC2-3:acc#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(4)} -pin  "ACC2-3:acc#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(5)} -pin  "ACC2-3:acc#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(6)} -pin  "ACC2-3:acc#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(7)} -pin  "ACC2-3:acc#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(8)} -pin  "ACC2-3:acc#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(9)} -pin  "ACC2-3:acc#3" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(10)} -pin  "ACC2-3:acc#3" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(11)} -pin  "ACC2-3:acc#3" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(12)} -pin  "ACC2-3:acc#3" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(13)} -pin  "ACC2-3:acc#3" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {ACC1:acc#67.itm(14)} -pin  "ACC2-3:acc#3" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#49.itm}
+load net {b(0).sva#3(0)} -pin  "ACC2-3:acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(1)} -pin  "ACC2-3:acc#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(2)} -pin  "ACC2-3:acc#3" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(3)} -pin  "ACC2-3:acc#3" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(4)} -pin  "ACC2-3:acc#3" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(5)} -pin  "ACC2-3:acc#3" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(6)} -pin  "ACC2-3:acc#3" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(7)} -pin  "ACC2-3:acc#3" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(8)} -pin  "ACC2-3:acc#3" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(9)} -pin  "ACC2-3:acc#3" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(10)} -pin  "ACC2-3:acc#3" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(11)} -pin  "ACC2-3:acc#3" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(12)} -pin  "ACC2-3:acc#3" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(13)} -pin  "ACC2-3:acc#3" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(14)} -pin  "ACC2-3:acc#3" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(15)} -pin  "ACC2-3:acc#3" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {blue#2.sva(0)} -pin  "ACC2-3:acc#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(1)} -pin  "ACC2-3:acc#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(2)} -pin  "ACC2-3:acc#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(3)} -pin  "ACC2-3:acc#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(4)} -pin  "ACC2-3:acc#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(5)} -pin  "ACC2-3:acc#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(6)} -pin  "ACC2-3:acc#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(7)} -pin  "ACC2-3:acc#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(8)} -pin  "ACC2-3:acc#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(9)} -pin  "ACC2-3:acc#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(10)} -pin  "ACC2-3:acc#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(11)} -pin  "ACC2-3:acc#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(12)} -pin  "ACC2-3:acc#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(13)} -pin  "ACC2-3:acc#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(14)} -pin  "ACC2-3:acc#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load net {blue#2.sva(15)} -pin  "ACC2-3:acc#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/blue#2.sva}
+load inst "FRAME:acc#45" "add(4,-1,4,-1,4)" "INTERFACE" -attr xrf 12042 -attr oid 430 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#45} -attr area 5.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {FRAME:acc#28.sdt(1)} -pin  "FRAME:acc#45" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#28.sdt).itm}
+load net {FRAME:acc#28.sdt(2)} -pin  "FRAME:acc#45" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#28.sdt).itm}
+load net {FRAME:acc#28.sdt(3)} -pin  "FRAME:acc#45" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#28.sdt).itm}
+load net {FRAME:acc#28.sdt(4)} -pin  "FRAME:acc#45" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#28.sdt).itm}
+load net {PWR} -pin  "FRAME:acc#45" {B(0)} -attr @path {/sobel/sobel:core/Cn7_4#1}
+load net {GND} -pin  "FRAME:acc#45" {B(1)} -attr @path {/sobel/sobel:core/Cn7_4#1}
+load net {GND} -pin  "FRAME:acc#45" {B(2)} -attr @path {/sobel/sobel:core/Cn7_4#1}
+load net {PWR} -pin  "FRAME:acc#45" {B(3)} -attr @path {/sobel/sobel:core/Cn7_4#1}
+load net {FRAME:acc#45.itm(0)} -pin  "FRAME:acc#45" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#45.itm}
+load net {FRAME:acc#45.itm(1)} -pin  "FRAME:acc#45" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#45.itm}
+load net {FRAME:acc#45.itm(2)} -pin  "FRAME:acc#45" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#45.itm}
+load net {FRAME:acc#45.itm(3)} -pin  "FRAME:acc#45" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#45.itm}
+load inst "FRAME:not#19" "not(3)" "INTERFACE" -attr xrf 12043 -attr oid 431 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#19} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {blue#2.sva(4)} -pin  "FRAME:not#19" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#6.itm}
+load net {blue#2.sva(5)} -pin  "FRAME:not#19" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#6.itm}
+load net {blue#2.sva(6)} -pin  "FRAME:not#19" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#6.itm}
+load net {FRAME:not#19.itm(0)} -pin  "FRAME:not#19" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#19.itm}
+load net {FRAME:not#19.itm(1)} -pin  "FRAME:not#19" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#19.itm}
+load net {FRAME:not#19.itm(2)} -pin  "FRAME:not#19" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#19.itm}
+load inst "FRAME:acc#29" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 12044 -attr oid 432 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#19.itm(0)} -pin  "FRAME:acc#29" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#19.itm}
+load net {FRAME:not#19.itm(1)} -pin  "FRAME:acc#29" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#19.itm}
+load net {FRAME:not#19.itm(2)} -pin  "FRAME:acc#29" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#19.itm}
+load net {blue#2.sva(7)} -pin  "FRAME:acc#29" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#7.itm}
+load net {blue#2.sva(8)} -pin  "FRAME:acc#29" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#7.itm}
+load net {blue#2.sva(9)} -pin  "FRAME:acc#29" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#7.itm}
+load net {FRAME:acc#29.itm(0)} -pin  "FRAME:acc#29" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(1)} -pin  "FRAME:acc#29" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(2)} -pin  "FRAME:acc#29" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(3)} -pin  "FRAME:acc#29" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load inst "FRAME:acc#30" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 12045 -attr oid 433 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30} -attr area 5.297136 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,5)"
+load net {FRAME:acc#29.itm(0)} -pin  "FRAME:acc#30" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(1)} -pin  "FRAME:acc#30" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(2)} -pin  "FRAME:acc#30" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(3)} -pin  "FRAME:acc#30" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {blue#2.sva(1)} -pin  "FRAME:acc#30" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#8.itm}
+load net {blue#2.sva(2)} -pin  "FRAME:acc#30" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#8.itm}
+load net {blue#2.sva(3)} -pin  "FRAME:acc#30" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#8.itm}
+load net {FRAME:acc#30.itm(0)} -pin  "FRAME:acc#30" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(1)} -pin  "FRAME:acc#30" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(2)} -pin  "FRAME:acc#30" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(3)} -pin  "FRAME:acc#30" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(4)} -pin  "FRAME:acc#30" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load inst "FRAME:acc#11" "add(6,-1,5,0,6)" "INTERFACE" -attr xrf 12046 -attr oid 434 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11} -attr area 7.279752 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,0,6)"
+load net {FRAME:acc#28.sdt(0)} -pin  "FRAME:acc#11" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {FRAME:acc#45.itm(0)} -pin  "FRAME:acc#11" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {FRAME:acc#45.itm(1)} -pin  "FRAME:acc#11" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {FRAME:acc#45.itm(2)} -pin  "FRAME:acc#11" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {FRAME:acc#45.itm(3)} -pin  "FRAME:acc#11" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {PWR} -pin  "FRAME:acc#11" {A(5)} -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {FRAME:acc#30.itm(0)} -pin  "FRAME:acc#11" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(1)} -pin  "FRAME:acc#11" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(2)} -pin  "FRAME:acc#11" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(3)} -pin  "FRAME:acc#11" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(4)} -pin  "FRAME:acc#11" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#11.psp.sva(0)} -pin  "FRAME:acc#11" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.psp.sva}
+load net {FRAME:acc#11.psp.sva(1)} -pin  "FRAME:acc#11" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.psp.sva}
+load net {FRAME:acc#11.psp.sva(2)} -pin  "FRAME:acc#11" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.psp.sva}
+load net {FRAME:acc#11.psp.sva(3)} -pin  "FRAME:acc#11" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.psp.sva}
+load net {FRAME:acc#11.psp.sva(4)} -pin  "FRAME:acc#11" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.psp.sva}
+load net {FRAME:acc#11.psp.sva(5)} -pin  "FRAME:acc#11" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.psp.sva}
+load inst "FRAME:not#22" "not(3)" "INTERFACE" -attr xrf 12047 -attr oid 435 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {FRAME:acc#11.psp.sva(3)} -pin  "FRAME:not#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#11.psp.sva)#3.itm}
+load net {FRAME:acc#11.psp.sva(4)} -pin  "FRAME:not#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#11.psp.sva)#3.itm}
+load net {FRAME:acc#11.psp.sva(5)} -pin  "FRAME:not#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#11.psp.sva)#3.itm}
+load net {FRAME:not#22.itm(0)} -pin  "FRAME:not#22" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(1)} -pin  "FRAME:not#22" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(2)} -pin  "FRAME:not#22" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load inst "FRAME:not#29" "not(1)" "INTERFACE" -attr xrf 12048 -attr oid 436 -attr @path {/sobel/sobel:core/FRAME:not#29} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#11.psp.sva(5)} -pin  "FRAME:not#29" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#11.psp.sva)#4.itm}
+load net {FRAME:not#29.itm} -pin  "FRAME:not#29" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#29.itm}
+load inst "FRAME:acc#32" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 12049 -attr oid 437 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,1,5,1,6)"
+load net {PWR} -pin  "FRAME:acc#32" {A(0)} -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {FRAME:acc#11.psp.sva(0)} -pin  "FRAME:acc#32" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {FRAME:acc#11.psp.sva(1)} -pin  "FRAME:acc#32" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {FRAME:acc#11.psp.sva(2)} -pin  "FRAME:acc#32" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {PWR} -pin  "FRAME:acc#32" {A(4)} -attr @path {/sobel/sobel:core/conc#148.itm}
+load net {FRAME:not#29.itm} -pin  "FRAME:acc#32" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#76.itm}
+load net {FRAME:not#22.itm(0)} -pin  "FRAME:acc#32" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#76.itm}
+load net {FRAME:not#22.itm(1)} -pin  "FRAME:acc#32" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#76.itm}
+load net {FRAME:not#22.itm(2)} -pin  "FRAME:acc#32" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#76.itm}
+load net {FRAME:acc#32.itm(0)} -pin  "FRAME:acc#32" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(1)} -pin  "FRAME:acc#32" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(2)} -pin  "FRAME:acc#32" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(3)} -pin  "FRAME:acc#32" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(4)} -pin  "FRAME:acc#32" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load inst "ACC1:not#17" "not(10)" "INTERFACE" -attr xrf 12050 -attr oid 438 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#17} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "ACC1:not#17" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "ACC1:not#17" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "ACC1:not#17" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "ACC1:not#17" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "ACC1:not#17" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "ACC1:not#17" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "ACC1:not#17" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "ACC1:not#17" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "ACC1:not#17" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "ACC1:not#17" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {ACC1:not#17.itm(0)} -pin  "ACC1:not#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#17.itm}
+load net {ACC1:not#17.itm(1)} -pin  "ACC1:not#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#17.itm}
+load net {ACC1:not#17.itm(2)} -pin  "ACC1:not#17" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#17.itm}
+load net {ACC1:not#17.itm(3)} -pin  "ACC1:not#17" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#17.itm}
+load net {ACC1:not#17.itm(4)} -pin  "ACC1:not#17" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#17.itm}
+load net {ACC1:not#17.itm(5)} -pin  "ACC1:not#17" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#17.itm}
+load net {ACC1:not#17.itm(6)} -pin  "ACC1:not#17" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#17.itm}
+load net {ACC1:not#17.itm(7)} -pin  "ACC1:not#17" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#17.itm}
+load net {ACC1:not#17.itm(8)} -pin  "ACC1:not#17" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#17.itm}
+load net {ACC1:not#17.itm(9)} -pin  "ACC1:not#17" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#17.itm}
+load inst "acc#1" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 12051 -attr oid 439 -attr vt d -attr @path {/sobel/sobel:core/acc#1} -attr area 12.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "acc#1" {A(0)} -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {ACC1:not#17.itm(0)} -pin  "acc#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {ACC1:not#17.itm(1)} -pin  "acc#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {ACC1:not#17.itm(2)} -pin  "acc#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {ACC1:not#17.itm(3)} -pin  "acc#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {ACC1:not#17.itm(4)} -pin  "acc#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {ACC1:not#17.itm(5)} -pin  "acc#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {ACC1:not#17.itm(6)} -pin  "acc#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {ACC1:not#17.itm(7)} -pin  "acc#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {ACC1:not#17.itm(8)} -pin  "acc#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {ACC1:not#17.itm(9)} -pin  "acc#1" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#149.itm}
+load net {PWR} -pin  "acc#1" {B(0)} -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "acc#1" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "acc#1" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "acc#1" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "acc#1" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "acc#1" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "acc#1" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "acc#1" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "acc#1" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "acc#1" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "acc#1" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#150.itm}
+load net {acc#1.itm(0)} -pin  "acc#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#1.itm}
+load net {acc#1.itm(1)} -pin  "acc#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#1.itm}
+load net {acc#1.itm(2)} -pin  "acc#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#1.itm}
+load net {acc#1.itm(3)} -pin  "acc#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#1.itm}
+load net {acc#1.itm(4)} -pin  "acc#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#1.itm}
+load net {acc#1.itm(5)} -pin  "acc#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#1.itm}
+load net {acc#1.itm(6)} -pin  "acc#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#1.itm}
+load net {acc#1.itm(7)} -pin  "acc#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#1.itm}
+load net {acc#1.itm(8)} -pin  "acc#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#1.itm}
+load net {acc#1.itm(9)} -pin  "acc#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#1.itm}
+load net {acc#1.itm(10)} -pin  "acc#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#1.itm}
+load net {acc#1.itm(11)} -pin  "acc#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#1.itm}
+load inst "ACC1:acc#59" "add(11,1,15,-1,15)" "INTERFACE" -attr xrf 12052 -attr oid 440 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59} -attr area 16.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {acc#1.itm(1)} -pin  "ACC1:acc#59" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#1.itm(2)} -pin  "ACC1:acc#59" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#1.itm(3)} -pin  "ACC1:acc#59" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#1.itm(4)} -pin  "ACC1:acc#59" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#1.itm(5)} -pin  "ACC1:acc#59" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#1.itm(6)} -pin  "ACC1:acc#59" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#1.itm(7)} -pin  "ACC1:acc#59" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#1.itm(8)} -pin  "ACC1:acc#59" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#1.itm(9)} -pin  "ACC1:acc#59" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#1.itm(10)} -pin  "ACC1:acc#59" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#1.itm(11)} -pin  "ACC1:acc#59" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {r(2).sva#3(1)} -pin  "ACC1:acc#59" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(2)} -pin  "ACC1:acc#59" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(3)} -pin  "ACC1:acc#59" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(4)} -pin  "ACC1:acc#59" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(5)} -pin  "ACC1:acc#59" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(6)} -pin  "ACC1:acc#59" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(7)} -pin  "ACC1:acc#59" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(8)} -pin  "ACC1:acc#59" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(9)} -pin  "ACC1:acc#59" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(10)} -pin  "ACC1:acc#59" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(11)} -pin  "ACC1:acc#59" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(12)} -pin  "ACC1:acc#59" {B(11)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(13)} -pin  "ACC1:acc#59" {B(12)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(14)} -pin  "ACC1:acc#59" {B(13)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#3(15)} -pin  "ACC1:acc#59" {B(14)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {ACC1:acc#59.itm(0)} -pin  "ACC1:acc#59" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(1)} -pin  "ACC1:acc#59" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(2)} -pin  "ACC1:acc#59" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(3)} -pin  "ACC1:acc#59" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(4)} -pin  "ACC1:acc#59" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(5)} -pin  "ACC1:acc#59" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(6)} -pin  "ACC1:acc#59" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(7)} -pin  "ACC1:acc#59" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(8)} -pin  "ACC1:acc#59" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(9)} -pin  "ACC1:acc#59" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(10)} -pin  "ACC1:acc#59" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(11)} -pin  "ACC1:acc#59" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(12)} -pin  "ACC1:acc#59" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(13)} -pin  "ACC1:acc#59" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load net {ACC1:acc#59.itm(14)} -pin  "ACC1:acc#59" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#59.itm}
+load inst "ACC1:acc#58" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 12053 -attr oid 441 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {PWR} -pin  "ACC1:acc#58" {A(0)} -attr @path {/sobel/sobel:core/conc#151.itm}
+load net {r(2).sva#3(0)} -pin  "ACC1:acc#58" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#151.itm}
+load net {PWR} -pin  "ACC1:acc#58" {B(0)} -attr @path {/sobel/sobel:core/Cn1_1#3}
+load net {ACC1:acc#58.itm(0)} -pin  "ACC1:acc#58" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load net {ACC1:acc#58.itm(1)} -pin  "ACC1:acc#58" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#58.itm}
+load inst "ACC2-3:acc#1" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 12054 -attr oid 442 -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {ACC1:acc#58.itm(1)} -pin  "ACC2-3:acc#1" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(0)} -pin  "ACC2-3:acc#1" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(1)} -pin  "ACC2-3:acc#1" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(2)} -pin  "ACC2-3:acc#1" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(3)} -pin  "ACC2-3:acc#1" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(4)} -pin  "ACC2-3:acc#1" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(5)} -pin  "ACC2-3:acc#1" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(6)} -pin  "ACC2-3:acc#1" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(7)} -pin  "ACC2-3:acc#1" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(8)} -pin  "ACC2-3:acc#1" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(9)} -pin  "ACC2-3:acc#1" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(10)} -pin  "ACC2-3:acc#1" {A(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(11)} -pin  "ACC2-3:acc#1" {A(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(12)} -pin  "ACC2-3:acc#1" {A(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(13)} -pin  "ACC2-3:acc#1" {A(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {ACC1:acc#59.itm(14)} -pin  "ACC2-3:acc#1" {A(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:conc#45.itm}
+load net {r(0).sva#3(0)} -pin  "ACC2-3:acc#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(1)} -pin  "ACC2-3:acc#1" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(2)} -pin  "ACC2-3:acc#1" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(3)} -pin  "ACC2-3:acc#1" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(4)} -pin  "ACC2-3:acc#1" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(5)} -pin  "ACC2-3:acc#1" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(6)} -pin  "ACC2-3:acc#1" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(7)} -pin  "ACC2-3:acc#1" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(8)} -pin  "ACC2-3:acc#1" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(9)} -pin  "ACC2-3:acc#1" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(10)} -pin  "ACC2-3:acc#1" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(11)} -pin  "ACC2-3:acc#1" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(12)} -pin  "ACC2-3:acc#1" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(13)} -pin  "ACC2-3:acc#1" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(14)} -pin  "ACC2-3:acc#1" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(15)} -pin  "ACC2-3:acc#1" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {red#2.sva(0)} -pin  "ACC2-3:acc#1" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(1)} -pin  "ACC2-3:acc#1" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(2)} -pin  "ACC2-3:acc#1" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(3)} -pin  "ACC2-3:acc#1" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(4)} -pin  "ACC2-3:acc#1" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(5)} -pin  "ACC2-3:acc#1" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(6)} -pin  "ACC2-3:acc#1" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(7)} -pin  "ACC2-3:acc#1" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(8)} -pin  "ACC2-3:acc#1" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(9)} -pin  "ACC2-3:acc#1" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(10)} -pin  "ACC2-3:acc#1" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(11)} -pin  "ACC2-3:acc#1" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(12)} -pin  "ACC2-3:acc#1" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(13)} -pin  "ACC2-3:acc#1" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(14)} -pin  "ACC2-3:acc#1" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load net {red#2.sva(15)} -pin  "ACC2-3:acc#1" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/red#2.sva}
+load inst "FRAME:acc#43" "add(4,-1,4,-1,4)" "INTERFACE" -attr xrf 12055 -attr oid 443 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43} -attr area 5.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {FRAME:acc#13.sdt(1)} -pin  "FRAME:acc#43" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#13.sdt).itm}
+load net {FRAME:acc#13.sdt(2)} -pin  "FRAME:acc#43" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#13.sdt).itm}
+load net {FRAME:acc#13.sdt(3)} -pin  "FRAME:acc#43" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#13.sdt).itm}
+load net {FRAME:acc#13.sdt(4)} -pin  "FRAME:acc#43" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#13.sdt).itm}
+load net {PWR} -pin  "FRAME:acc#43" {B(0)} -attr @path {/sobel/sobel:core/Cn7_4#1}
+load net {GND} -pin  "FRAME:acc#43" {B(1)} -attr @path {/sobel/sobel:core/Cn7_4#1}
+load net {GND} -pin  "FRAME:acc#43" {B(2)} -attr @path {/sobel/sobel:core/Cn7_4#1}
+load net {PWR} -pin  "FRAME:acc#43" {B(3)} -attr @path {/sobel/sobel:core/Cn7_4#1}
+load net {FRAME:acc#43.itm(0)} -pin  "FRAME:acc#43" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {FRAME:acc#43.itm(1)} -pin  "FRAME:acc#43" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {FRAME:acc#43.itm(2)} -pin  "FRAME:acc#43" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {FRAME:acc#43.itm(3)} -pin  "FRAME:acc#43" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load inst "FRAME:not#1" "not(3)" "INTERFACE" -attr xrf 12056 -attr oid 444 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:not#1} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {red#2.sva(4)} -pin  "FRAME:not#1" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sva)#6.itm}
+load net {red#2.sva(5)} -pin  "FRAME:not#1" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sva)#6.itm}
+load net {red#2.sva(6)} -pin  "FRAME:not#1" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sva)#6.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:not#1" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:not#1" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:not#1" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load inst "FRAME:acc#14" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 12057 -attr oid 445 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:acc#14" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:acc#14" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:acc#14" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {red#2.sva(7)} -pin  "FRAME:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#7.itm}
+load net {red#2.sva(8)} -pin  "FRAME:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#7.itm}
+load net {red#2.sva(9)} -pin  "FRAME:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#7.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#14" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#14" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#14" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#14" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load inst "FRAME:acc#15" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 12058 -attr oid 446 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15} -attr area 5.297136 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,5)"
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#15" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#15" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#15" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#15" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {red#2.sva(1)} -pin  "FRAME:acc#15" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#8.itm}
+load net {red#2.sva(2)} -pin  "FRAME:acc#15" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#8.itm}
+load net {red#2.sva(3)} -pin  "FRAME:acc#15" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#8.itm}
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#15" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#15" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#15" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#15" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#15" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load inst "FRAME:acc#7" "add(6,-1,5,0,6)" "INTERFACE" -attr xrf 12059 -attr oid 447 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#7} -attr area 7.279752 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,0,6)"
+load net {FRAME:acc#13.sdt(0)} -pin  "FRAME:acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {FRAME:acc#43.itm(0)} -pin  "FRAME:acc#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {FRAME:acc#43.itm(1)} -pin  "FRAME:acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {FRAME:acc#43.itm(2)} -pin  "FRAME:acc#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {FRAME:acc#43.itm(3)} -pin  "FRAME:acc#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {PWR} -pin  "FRAME:acc#7" {A(5)} -attr @path {/sobel/sobel:core/conc#152.itm}
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#7" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#7" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#7" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#7" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#7" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#7.psp.sva(0)} -pin  "FRAME:acc#7" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#7.psp.sva}
+load net {FRAME:acc#7.psp.sva(1)} -pin  "FRAME:acc#7" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#7.psp.sva}
+load net {FRAME:acc#7.psp.sva(2)} -pin  "FRAME:acc#7" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#7.psp.sva}
+load net {FRAME:acc#7.psp.sva(3)} -pin  "FRAME:acc#7" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#7.psp.sva}
+load net {FRAME:acc#7.psp.sva(4)} -pin  "FRAME:acc#7" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#7.psp.sva}
+load net {FRAME:acc#7.psp.sva(5)} -pin  "FRAME:acc#7" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#7.psp.sva}
+load inst "FRAME:not#4" "not(3)" "INTERFACE" -attr xrf 12060 -attr oid 448 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {FRAME:acc#7.psp.sva(3)} -pin  "FRAME:not#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#7.psp.sva)#3.itm}
+load net {FRAME:acc#7.psp.sva(4)} -pin  "FRAME:not#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#7.psp.sva)#3.itm}
+load net {FRAME:acc#7.psp.sva(5)} -pin  "FRAME:not#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#7.psp.sva)#3.itm}
+load net {FRAME:not#4.itm(0)} -pin  "FRAME:not#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#4.itm}
+load net {FRAME:not#4.itm(1)} -pin  "FRAME:not#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#4.itm}
+load net {FRAME:not#4.itm(2)} -pin  "FRAME:not#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#4.itm}
+load inst "FRAME:not#31" "not(1)" "INTERFACE" -attr xrf 12061 -attr oid 449 -attr @path {/sobel/sobel:core/FRAME:not#31} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#7.psp.sva(5)} -pin  "FRAME:not#31" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#7.psp.sva)#4.itm}
+load net {FRAME:not#31.itm} -pin  "FRAME:not#31" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#31.itm}
+load inst "FRAME:acc#17" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 12062 -attr oid 450 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,1,5,1,6)"
+load net {PWR} -pin  "FRAME:acc#17" {A(0)} -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {FRAME:acc#7.psp.sva(0)} -pin  "FRAME:acc#17" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {FRAME:acc#7.psp.sva(1)} -pin  "FRAME:acc#17" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {FRAME:acc#7.psp.sva(2)} -pin  "FRAME:acc#17" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {PWR} -pin  "FRAME:acc#17" {A(4)} -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {FRAME:not#31.itm} -pin  "FRAME:acc#17" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#67.itm}
+load net {FRAME:not#4.itm(0)} -pin  "FRAME:acc#17" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#67.itm}
+load net {FRAME:not#4.itm(1)} -pin  "FRAME:acc#17" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#67.itm}
+load net {FRAME:not#4.itm(2)} -pin  "FRAME:acc#17" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#67.itm}
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#17" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#17" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:acc#17" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:acc#17" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(4)} -pin  "FRAME:acc#17" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load inst "FRAME:not#20" "not(3)" "INTERFACE" -attr xrf 12063 -attr oid 451 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#20} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {blue#2.sva(10)} -pin  "FRAME:not#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#9.itm}
+load net {blue#2.sva(11)} -pin  "FRAME:not#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#9.itm}
+load net {blue#2.sva(12)} -pin  "FRAME:not#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva)#9.itm}
+load net {FRAME:not#20.itm(0)} -pin  "FRAME:not#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load net {FRAME:not#20.itm(1)} -pin  "FRAME:not#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load net {FRAME:not#20.itm(2)} -pin  "FRAME:not#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load inst "FRAME:acc#28" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 12064 -attr oid 452 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {FRAME:not#20.itm(0)} -pin  "FRAME:acc#28" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load net {FRAME:not#20.itm(1)} -pin  "FRAME:acc#28" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load net {FRAME:not#20.itm(2)} -pin  "FRAME:acc#28" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load net {blue#2.sva(13)} -pin  "FRAME:acc#28" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva).itm}
+load net {blue#2.sva(14)} -pin  "FRAME:acc#28" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva).itm}
+load net {blue#2.sva(15)} -pin  "FRAME:acc#28" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sva).itm}
+load net {FRAME:acc#28.sdt(0)} -pin  "FRAME:acc#28" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.sdt}
+load net {FRAME:acc#28.sdt(1)} -pin  "FRAME:acc#28" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.sdt}
+load net {FRAME:acc#28.sdt(2)} -pin  "FRAME:acc#28" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.sdt}
+load net {FRAME:acc#28.sdt(3)} -pin  "FRAME:acc#28" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.sdt}
+load net {FRAME:acc#28.sdt(4)} -pin  "FRAME:acc#28" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.sdt}
+load inst "ACC1:not#18" "not(10)" "INTERFACE" -attr xrf 12065 -attr oid 453 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#18} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "ACC1:not#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "ACC1:not#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "ACC1:not#18" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "ACC1:not#18" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "ACC1:not#18" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "ACC1:not#18" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "ACC1:not#18" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "ACC1:not#18" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "ACC1:not#18" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "ACC1:not#18" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {ACC1:not#18.itm(0)} -pin  "ACC1:not#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#18.itm}
+load net {ACC1:not#18.itm(1)} -pin  "ACC1:not#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#18.itm}
+load net {ACC1:not#18.itm(2)} -pin  "ACC1:not#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#18.itm}
+load net {ACC1:not#18.itm(3)} -pin  "ACC1:not#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#18.itm}
+load net {ACC1:not#18.itm(4)} -pin  "ACC1:not#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#18.itm}
+load net {ACC1:not#18.itm(5)} -pin  "ACC1:not#18" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#18.itm}
+load net {ACC1:not#18.itm(6)} -pin  "ACC1:not#18" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#18.itm}
+load net {ACC1:not#18.itm(7)} -pin  "ACC1:not#18" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#18.itm}
+load net {ACC1:not#18.itm(8)} -pin  "ACC1:not#18" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#18.itm}
+load net {ACC1:not#18.itm(9)} -pin  "ACC1:not#18" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#18.itm}
+load inst "acc#2" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 12066 -attr oid 454 -attr vt d -attr @path {/sobel/sobel:core/acc#2} -attr area 12.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "acc#2" {A(0)} -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC1:not#18.itm(0)} -pin  "acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC1:not#18.itm(1)} -pin  "acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC1:not#18.itm(2)} -pin  "acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC1:not#18.itm(3)} -pin  "acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC1:not#18.itm(4)} -pin  "acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC1:not#18.itm(5)} -pin  "acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC1:not#18.itm(6)} -pin  "acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC1:not#18.itm(7)} -pin  "acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC1:not#18.itm(8)} -pin  "acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC1:not#18.itm(9)} -pin  "acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {PWR} -pin  "acc#2" {B(0)} -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {acc#2.itm(0)} -pin  "acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#2.itm}
+load net {acc#2.itm(1)} -pin  "acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#2.itm}
+load net {acc#2.itm(2)} -pin  "acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#2.itm}
+load net {acc#2.itm(3)} -pin  "acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#2.itm}
+load net {acc#2.itm(4)} -pin  "acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#2.itm}
+load net {acc#2.itm(5)} -pin  "acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#2.itm}
+load net {acc#2.itm(6)} -pin  "acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#2.itm}
+load net {acc#2.itm(7)} -pin  "acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#2.itm}
+load net {acc#2.itm(8)} -pin  "acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#2.itm}
+load net {acc#2.itm(9)} -pin  "acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#2.itm}
+load net {acc#2.itm(10)} -pin  "acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#2.itm}
+load net {acc#2.itm(11)} -pin  "acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#2.itm}
+load inst "ACC1:acc#63" "add(11,1,15,-1,15)" "INTERFACE" -attr xrf 12067 -attr oid 455 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63} -attr area 16.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {acc#2.itm(1)} -pin  "ACC1:acc#63" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#2.itm(2)} -pin  "ACC1:acc#63" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#2.itm(3)} -pin  "ACC1:acc#63" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#2.itm(4)} -pin  "ACC1:acc#63" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#2.itm(5)} -pin  "ACC1:acc#63" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#2.itm(6)} -pin  "ACC1:acc#63" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#2.itm(7)} -pin  "ACC1:acc#63" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#2.itm(8)} -pin  "ACC1:acc#63" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#2.itm(9)} -pin  "ACC1:acc#63" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#2.itm(10)} -pin  "ACC1:acc#63" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#2.itm(11)} -pin  "ACC1:acc#63" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {g(2).sva#3(1)} -pin  "ACC1:acc#63" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(2)} -pin  "ACC1:acc#63" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(3)} -pin  "ACC1:acc#63" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(4)} -pin  "ACC1:acc#63" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(5)} -pin  "ACC1:acc#63" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(6)} -pin  "ACC1:acc#63" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(7)} -pin  "ACC1:acc#63" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(8)} -pin  "ACC1:acc#63" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(9)} -pin  "ACC1:acc#63" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(10)} -pin  "ACC1:acc#63" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(11)} -pin  "ACC1:acc#63" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(12)} -pin  "ACC1:acc#63" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(13)} -pin  "ACC1:acc#63" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(14)} -pin  "ACC1:acc#63" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#3(15)} -pin  "ACC1:acc#63" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {ACC1:acc#63.itm(0)} -pin  "ACC1:acc#63" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(1)} -pin  "ACC1:acc#63" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(2)} -pin  "ACC1:acc#63" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(3)} -pin  "ACC1:acc#63" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(4)} -pin  "ACC1:acc#63" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(5)} -pin  "ACC1:acc#63" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(6)} -pin  "ACC1:acc#63" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(7)} -pin  "ACC1:acc#63" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(8)} -pin  "ACC1:acc#63" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(9)} -pin  "ACC1:acc#63" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(10)} -pin  "ACC1:acc#63" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(11)} -pin  "ACC1:acc#63" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(12)} -pin  "ACC1:acc#63" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(13)} -pin  "ACC1:acc#63" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load net {ACC1:acc#63.itm(14)} -pin  "ACC1:acc#63" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#63.itm}
+load inst "ACC1:acc#62" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 12068 -attr oid 456 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#62} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {PWR} -pin  "ACC1:acc#62" {A(0)} -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {g(2).sva#3(0)} -pin  "ACC1:acc#62" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {PWR} -pin  "ACC1:acc#62" {B(0)} -attr @path {/sobel/sobel:core/Cn1_1#3}
+load net {ACC1:acc#62.itm(0)} -pin  "ACC1:acc#62" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load net {ACC1:acc#62.itm(1)} -pin  "ACC1:acc#62" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#62.itm}
+load inst "ACC2-3:acc#2" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 12069 -attr oid 457 -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {ACC1:acc#62.itm(1)} -pin  "ACC2-3:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(0)} -pin  "ACC2-3:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(1)} -pin  "ACC2-3:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(2)} -pin  "ACC2-3:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(3)} -pin  "ACC2-3:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(4)} -pin  "ACC2-3:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(5)} -pin  "ACC2-3:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(6)} -pin  "ACC2-3:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(7)} -pin  "ACC2-3:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(8)} -pin  "ACC2-3:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(9)} -pin  "ACC2-3:acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(10)} -pin  "ACC2-3:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(11)} -pin  "ACC2-3:acc#2" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(12)} -pin  "ACC2-3:acc#2" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(13)} -pin  "ACC2-3:acc#2" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {ACC1:acc#63.itm(14)} -pin  "ACC2-3:acc#2" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#47.itm}
+load net {g(0).sva#3(0)} -pin  "ACC2-3:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(1)} -pin  "ACC2-3:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(2)} -pin  "ACC2-3:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(3)} -pin  "ACC2-3:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(4)} -pin  "ACC2-3:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(5)} -pin  "ACC2-3:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(6)} -pin  "ACC2-3:acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(7)} -pin  "ACC2-3:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(8)} -pin  "ACC2-3:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(9)} -pin  "ACC2-3:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(10)} -pin  "ACC2-3:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(11)} -pin  "ACC2-3:acc#2" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(12)} -pin  "ACC2-3:acc#2" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(13)} -pin  "ACC2-3:acc#2" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(14)} -pin  "ACC2-3:acc#2" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(15)} -pin  "ACC2-3:acc#2" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {green#2.sva(0)} -pin  "ACC2-3:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(1)} -pin  "ACC2-3:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(2)} -pin  "ACC2-3:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(3)} -pin  "ACC2-3:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(4)} -pin  "ACC2-3:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(5)} -pin  "ACC2-3:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(6)} -pin  "ACC2-3:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(7)} -pin  "ACC2-3:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(8)} -pin  "ACC2-3:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(9)} -pin  "ACC2-3:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(10)} -pin  "ACC2-3:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(11)} -pin  "ACC2-3:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(12)} -pin  "ACC2-3:acc#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(13)} -pin  "ACC2-3:acc#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(14)} -pin  "ACC2-3:acc#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load net {green#2.sva(15)} -pin  "ACC2-3:acc#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/green#2.sva}
+load inst "FRAME:acc#44" "add(4,-1,4,-1,4)" "INTERFACE" -attr xrf 12070 -attr oid 458 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44} -attr area 5.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {FRAME:acc#18.sdt(1)} -pin  "FRAME:acc#44" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#18.sdt).itm}
+load net {FRAME:acc#18.sdt(2)} -pin  "FRAME:acc#44" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#18.sdt).itm}
+load net {FRAME:acc#18.sdt(3)} -pin  "FRAME:acc#44" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#18.sdt).itm}
+load net {FRAME:acc#18.sdt(4)} -pin  "FRAME:acc#44" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#18.sdt).itm}
+load net {PWR} -pin  "FRAME:acc#44" {B(0)} -attr @path {/sobel/sobel:core/Cn7_4#1}
+load net {GND} -pin  "FRAME:acc#44" {B(1)} -attr @path {/sobel/sobel:core/Cn7_4#1}
+load net {GND} -pin  "FRAME:acc#44" {B(2)} -attr @path {/sobel/sobel:core/Cn7_4#1}
+load net {PWR} -pin  "FRAME:acc#44" {B(3)} -attr @path {/sobel/sobel:core/Cn7_4#1}
+load net {FRAME:acc#44.itm(0)} -pin  "FRAME:acc#44" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(1)} -pin  "FRAME:acc#44" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(2)} -pin  "FRAME:acc#44" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(3)} -pin  "FRAME:acc#44" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load inst "FRAME:not#10" "not(3)" "INTERFACE" -attr xrf 12071 -attr oid 459 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {green#2.sva(4)} -pin  "FRAME:not#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#6.itm}
+load net {green#2.sva(5)} -pin  "FRAME:not#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#6.itm}
+load net {green#2.sva(6)} -pin  "FRAME:not#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#6.itm}
+load net {FRAME:not#10.itm(0)} -pin  "FRAME:not#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(1)} -pin  "FRAME:not#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(2)} -pin  "FRAME:not#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load inst "FRAME:acc#19" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 12072 -attr oid 460 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#10.itm(0)} -pin  "FRAME:acc#19" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(1)} -pin  "FRAME:acc#19" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(2)} -pin  "FRAME:acc#19" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {green#2.sva(7)} -pin  "FRAME:acc#19" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#7.itm}
+load net {green#2.sva(8)} -pin  "FRAME:acc#19" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#7.itm}
+load net {green#2.sva(9)} -pin  "FRAME:acc#19" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#7.itm}
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#19" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#19" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#19" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(3)} -pin  "FRAME:acc#19" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load inst "FRAME:acc#20" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 12073 -attr oid 461 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20} -attr area 5.297136 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,5)"
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(3)} -pin  "FRAME:acc#20" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {green#2.sva(1)} -pin  "FRAME:acc#20" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#8.itm}
+load net {green#2.sva(2)} -pin  "FRAME:acc#20" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#8.itm}
+load net {green#2.sva(3)} -pin  "FRAME:acc#20" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#8.itm}
+load net {FRAME:acc#20.itm(0)} -pin  "FRAME:acc#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(1)} -pin  "FRAME:acc#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(2)} -pin  "FRAME:acc#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(3)} -pin  "FRAME:acc#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(4)} -pin  "FRAME:acc#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load inst "FRAME:acc#9" "add(6,-1,5,0,6)" "INTERFACE" -attr xrf 12074 -attr oid 462 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9} -attr area 7.279752 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,0,6)"
+load net {FRAME:acc#18.sdt(0)} -pin  "FRAME:acc#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {FRAME:acc#44.itm(0)} -pin  "FRAME:acc#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {FRAME:acc#44.itm(1)} -pin  "FRAME:acc#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {FRAME:acc#44.itm(2)} -pin  "FRAME:acc#9" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {FRAME:acc#44.itm(3)} -pin  "FRAME:acc#9" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {PWR} -pin  "FRAME:acc#9" {A(5)} -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {FRAME:acc#20.itm(0)} -pin  "FRAME:acc#9" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(1)} -pin  "FRAME:acc#9" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(2)} -pin  "FRAME:acc#9" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(3)} -pin  "FRAME:acc#9" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(4)} -pin  "FRAME:acc#9" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#9.psp.sva(0)} -pin  "FRAME:acc#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.psp.sva}
+load net {FRAME:acc#9.psp.sva(1)} -pin  "FRAME:acc#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.psp.sva}
+load net {FRAME:acc#9.psp.sva(2)} -pin  "FRAME:acc#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.psp.sva}
+load net {FRAME:acc#9.psp.sva(3)} -pin  "FRAME:acc#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.psp.sva}
+load net {FRAME:acc#9.psp.sva(4)} -pin  "FRAME:acc#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.psp.sva}
+load net {FRAME:acc#9.psp.sva(5)} -pin  "FRAME:acc#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.psp.sva}
+load inst "FRAME:not#13" "not(3)" "INTERFACE" -attr xrf 12075 -attr oid 463 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {FRAME:acc#9.psp.sva(3)} -pin  "FRAME:not#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#9.psp.sva)#3.itm}
+load net {FRAME:acc#9.psp.sva(4)} -pin  "FRAME:not#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#9.psp.sva)#3.itm}
+load net {FRAME:acc#9.psp.sva(5)} -pin  "FRAME:not#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#9.psp.sva)#3.itm}
+load net {FRAME:not#13.itm(0)} -pin  "FRAME:not#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {FRAME:not#13.itm(1)} -pin  "FRAME:not#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {FRAME:not#13.itm(2)} -pin  "FRAME:not#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load inst "FRAME:not#33" "not(1)" "INTERFACE" -attr xrf 12076 -attr oid 464 -attr @path {/sobel/sobel:core/FRAME:not#33} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#9.psp.sva(5)} -pin  "FRAME:not#33" {A(0)} -attr @path {/sobel/sobel:core/slc(FRAME:acc#9.psp.sva)#4.itm}
+load net {FRAME:not#33.itm} -pin  "FRAME:not#33" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#33.itm}
+load inst "FRAME:acc#22" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 12077 -attr oid 465 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,1,5,1,6)"
+load net {PWR} -pin  "FRAME:acc#22" {A(0)} -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {FRAME:acc#9.psp.sva(0)} -pin  "FRAME:acc#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {FRAME:acc#9.psp.sva(1)} -pin  "FRAME:acc#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {FRAME:acc#9.psp.sva(2)} -pin  "FRAME:acc#22" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {PWR} -pin  "FRAME:acc#22" {A(4)} -attr @path {/sobel/sobel:core/conc#160.itm}
+load net {FRAME:not#33.itm} -pin  "FRAME:acc#22" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#70.itm}
+load net {FRAME:not#13.itm(0)} -pin  "FRAME:acc#22" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#70.itm}
+load net {FRAME:not#13.itm(1)} -pin  "FRAME:acc#22" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#70.itm}
+load net {FRAME:not#13.itm(2)} -pin  "FRAME:acc#22" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#70.itm}
+load net {FRAME:acc#22.itm(0)} -pin  "FRAME:acc#22" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(1)} -pin  "FRAME:acc#22" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(2)} -pin  "FRAME:acc#22" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(3)} -pin  "FRAME:acc#22" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load net {FRAME:acc#22.itm(4)} -pin  "FRAME:acc#22" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.itm}
+load inst "FRAME:not#11" "not(3)" "INTERFACE" -attr xrf 12078 -attr oid 466 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#11} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {green#2.sva(10)} -pin  "FRAME:not#11" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#9.itm}
+load net {green#2.sva(11)} -pin  "FRAME:not#11" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#9.itm}
+load net {green#2.sva(12)} -pin  "FRAME:not#11" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva)#9.itm}
+load net {FRAME:not#11.itm(0)} -pin  "FRAME:not#11" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#11.itm}
+load net {FRAME:not#11.itm(1)} -pin  "FRAME:not#11" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#11.itm}
+load net {FRAME:not#11.itm(2)} -pin  "FRAME:not#11" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#11.itm}
+load inst "FRAME:acc#18" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 12079 -attr oid 467 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {FRAME:not#11.itm(0)} -pin  "FRAME:acc#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#11.itm}
+load net {FRAME:not#11.itm(1)} -pin  "FRAME:acc#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#11.itm}
+load net {FRAME:not#11.itm(2)} -pin  "FRAME:acc#18" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#11.itm}
+load net {green#2.sva(13)} -pin  "FRAME:acc#18" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva).itm}
+load net {green#2.sva(14)} -pin  "FRAME:acc#18" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva).itm}
+load net {green#2.sva(15)} -pin  "FRAME:acc#18" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sva).itm}
+load net {FRAME:acc#18.sdt(0)} -pin  "FRAME:acc#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.sdt}
+load net {FRAME:acc#18.sdt(1)} -pin  "FRAME:acc#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.sdt}
+load net {FRAME:acc#18.sdt(2)} -pin  "FRAME:acc#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.sdt}
+load net {FRAME:acc#18.sdt(3)} -pin  "FRAME:acc#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.sdt}
+load net {FRAME:acc#18.sdt(4)} -pin  "FRAME:acc#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.sdt}
+load inst "FRAME:not#2" "not(3)" "INTERFACE" -attr xrf 12080 -attr oid 468 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {red#2.sva(10)} -pin  "FRAME:not#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#9.itm}
+load net {red#2.sva(11)} -pin  "FRAME:not#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#9.itm}
+load net {red#2.sva(12)} -pin  "FRAME:not#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva)#9.itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:not#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:not#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:not#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load inst "FRAME:acc#13" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 12081 -attr oid 469 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:acc#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:acc#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:acc#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {red#2.sva(13)} -pin  "FRAME:acc#13" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva).itm}
+load net {red#2.sva(14)} -pin  "FRAME:acc#13" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva).itm}
+load net {red#2.sva(15)} -pin  "FRAME:acc#13" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sva).itm}
+load net {FRAME:acc#13.sdt(0)} -pin  "FRAME:acc#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.sdt}
+load net {FRAME:acc#13.sdt(1)} -pin  "FRAME:acc#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.sdt}
+load net {FRAME:acc#13.sdt(2)} -pin  "FRAME:acc#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.sdt}
+load net {FRAME:acc#13.sdt(3)} -pin  "FRAME:acc#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.sdt}
+load net {FRAME:acc#13.sdt(4)} -pin  "FRAME:acc#13" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.sdt}
+load inst "ACC1:not#14" "not(10)" "INTERFACE" -attr xrf 12082 -attr oid 470 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "ACC1:not#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "ACC1:not#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "ACC1:not#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "ACC1:not#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "ACC1:not#14" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "ACC1:not#14" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "ACC1:not#14" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "ACC1:not#14" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "ACC1:not#14" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:not#14" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {ACC1:not#14.itm(0)} -pin  "ACC1:not#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(1)} -pin  "ACC1:not#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(2)} -pin  "ACC1:not#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(3)} -pin  "ACC1:not#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(4)} -pin  "ACC1:not#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(5)} -pin  "ACC1:not#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(6)} -pin  "ACC1:not#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(7)} -pin  "ACC1:not#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(8)} -pin  "ACC1:not#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load net {ACC1:not#14.itm(9)} -pin  "ACC1:not#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#14.itm}
+load inst "ACC1:acc#49" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 12083 -attr oid 471 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#49" {A(0)} -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {ACC1:not#14.itm(0)} -pin  "ACC1:acc#49" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {ACC1:not#14.itm(1)} -pin  "ACC1:acc#49" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {ACC1:not#14.itm(2)} -pin  "ACC1:acc#49" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {ACC1:not#14.itm(3)} -pin  "ACC1:acc#49" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {ACC1:not#14.itm(4)} -pin  "ACC1:acc#49" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {ACC1:not#14.itm(5)} -pin  "ACC1:acc#49" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {ACC1:not#14.itm(6)} -pin  "ACC1:acc#49" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {ACC1:not#14.itm(7)} -pin  "ACC1:acc#49" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {ACC1:not#14.itm(8)} -pin  "ACC1:acc#49" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {ACC1:not#14.itm(9)} -pin  "ACC1:acc#49" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#161.itm}
+load net {PWR} -pin  "ACC1:acc#49" {B(0)} -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {regs.regs(1).sva(60)} -pin  "ACC1:acc#49" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {regs.regs(1).sva(61)} -pin  "ACC1:acc#49" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {regs.regs(1).sva(62)} -pin  "ACC1:acc#49" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {regs.regs(1).sva(63)} -pin  "ACC1:acc#49" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {regs.regs(1).sva(64)} -pin  "ACC1:acc#49" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {regs.regs(1).sva(65)} -pin  "ACC1:acc#49" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {regs.regs(1).sva(66)} -pin  "ACC1:acc#49" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {regs.regs(1).sva(67)} -pin  "ACC1:acc#49" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {regs.regs(1).sva(68)} -pin  "ACC1:acc#49" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {regs.regs(1).sva(69)} -pin  "ACC1:acc#49" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#162.itm}
+load net {ACC1:acc#49.itm(0)} -pin  "ACC1:acc#49" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(1)} -pin  "ACC1:acc#49" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(2)} -pin  "ACC1:acc#49" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(3)} -pin  "ACC1:acc#49" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(4)} -pin  "ACC1:acc#49" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(5)} -pin  "ACC1:acc#49" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(6)} -pin  "ACC1:acc#49" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(7)} -pin  "ACC1:acc#49" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(8)} -pin  "ACC1:acc#49" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(9)} -pin  "ACC1:acc#49" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(10)} -pin  "ACC1:acc#49" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "ACC1:acc#49" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#49.itm}
+load inst "FRAME:for:mux#10" "mux(2,16)" "INTERFACE" -attr xrf 12084 -attr oid 472 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#49.itm(1)} -pin  "FRAME:for:mux#10" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(2)} -pin  "FRAME:for:mux#10" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(3)} -pin  "FRAME:for:mux#10" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(4)} -pin  "FRAME:for:mux#10" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(5)} -pin  "FRAME:for:mux#10" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(6)} -pin  "FRAME:for:mux#10" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(7)} -pin  "FRAME:for:mux#10" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(8)} -pin  "FRAME:for:mux#10" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(9)} -pin  "FRAME:for:mux#10" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(10)} -pin  "FRAME:for:mux#10" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#10" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#10" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#10" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#10" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#10" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {ACC1:acc#49.itm(11)} -pin  "FRAME:for:mux#10" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#25.itm}
+load net {b(2).sva#1(0)} -pin  "FRAME:for:mux#10" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(1)} -pin  "FRAME:for:mux#10" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(2)} -pin  "FRAME:for:mux#10" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(3)} -pin  "FRAME:for:mux#10" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(4)} -pin  "FRAME:for:mux#10" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(5)} -pin  "FRAME:for:mux#10" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(6)} -pin  "FRAME:for:mux#10" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(7)} -pin  "FRAME:for:mux#10" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(8)} -pin  "FRAME:for:mux#10" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(9)} -pin  "FRAME:for:mux#10" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(10)} -pin  "FRAME:for:mux#10" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(11)} -pin  "FRAME:for:mux#10" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(12)} -pin  "FRAME:for:mux#10" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(13)} -pin  "FRAME:for:mux#10" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(14)} -pin  "FRAME:for:mux#10" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(15)} -pin  "FRAME:for:mux#10" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#10" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#10.itm(0)} -pin  "FRAME:for:mux#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(1)} -pin  "FRAME:for:mux#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(2)} -pin  "FRAME:for:mux#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(3)} -pin  "FRAME:for:mux#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(4)} -pin  "FRAME:for:mux#10" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(5)} -pin  "FRAME:for:mux#10" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(6)} -pin  "FRAME:for:mux#10" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(7)} -pin  "FRAME:for:mux#10" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(8)} -pin  "FRAME:for:mux#10" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(9)} -pin  "FRAME:for:mux#10" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(10)} -pin  "FRAME:for:mux#10" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(11)} -pin  "FRAME:for:mux#10" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(12)} -pin  "FRAME:for:mux#10" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(13)} -pin  "FRAME:for:mux#10" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(14)} -pin  "FRAME:for:mux#10" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(15)} -pin  "FRAME:for:mux#10" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load inst "regs.operator[]#17:mux" "mux(4,10)" "INTERFACE" -attr xrf 12085 -attr oid 473 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "regs.operator[]#17:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "regs.operator[]#17:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "regs.operator[]#17:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "regs.operator[]#17:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "regs.operator[]#17:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "regs.operator[]#17:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "regs.operator[]#17:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "regs.operator[]#17:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "regs.operator[]#17:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "regs.operator[]#17:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "regs.operator[]#17:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "regs.operator[]#17:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "regs.operator[]#17:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "regs.operator[]#17:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "regs.operator[]#17:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "regs.operator[]#17:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "regs.operator[]#17:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "regs.operator[]#17:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "regs.operator[]#17:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "regs.operator[]#17:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "regs.operator[]#17:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "regs.operator[]#17:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "regs.operator[]#17:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "regs.operator[]#17:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "regs.operator[]#17:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "regs.operator[]#17:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "regs.operator[]#17:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "regs.operator[]#17:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "regs.operator[]#17:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "regs.operator[]#17:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#17:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#17:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#17:mux.itm(0)} -pin  "regs.operator[]#17:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(1)} -pin  "regs.operator[]#17:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(2)} -pin  "regs.operator[]#17:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(3)} -pin  "regs.operator[]#17:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(4)} -pin  "regs.operator[]#17:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(5)} -pin  "regs.operator[]#17:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(6)} -pin  "regs.operator[]#17:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(7)} -pin  "regs.operator[]#17:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(8)} -pin  "regs.operator[]#17:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(9)} -pin  "regs.operator[]#17:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load inst "FRAME:for:mul#8" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 12086 -attr oid 474 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#17:mux.itm(0)} -pin  "FRAME:for:mul#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(1)} -pin  "FRAME:for:mul#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(2)} -pin  "FRAME:for:mul#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(3)} -pin  "FRAME:for:mul#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(4)} -pin  "FRAME:for:mul#8" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(5)} -pin  "FRAME:for:mul#8" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(6)} -pin  "FRAME:for:mul#8" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(7)} -pin  "FRAME:for:mul#8" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(8)} -pin  "FRAME:for:mul#8" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(9)} -pin  "FRAME:for:mul#8" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:mul#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:mul#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:mul#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:mul#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:mul#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:mul#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:mul#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:mul#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:mul#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:mul#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:mul#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load inst "FRAME:for:acc#14" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 12087 -attr oid 475 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#10.itm(0)} -pin  "FRAME:for:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(1)} -pin  "FRAME:for:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(2)} -pin  "FRAME:for:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(3)} -pin  "FRAME:for:acc#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(4)} -pin  "FRAME:for:acc#14" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(5)} -pin  "FRAME:for:acc#14" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(6)} -pin  "FRAME:for:acc#14" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(7)} -pin  "FRAME:for:acc#14" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(8)} -pin  "FRAME:for:acc#14" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(9)} -pin  "FRAME:for:acc#14" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(10)} -pin  "FRAME:for:acc#14" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(11)} -pin  "FRAME:for:acc#14" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(12)} -pin  "FRAME:for:acc#14" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(13)} -pin  "FRAME:for:acc#14" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(14)} -pin  "FRAME:for:acc#14" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mux#10.itm(15)} -pin  "FRAME:for:acc#14" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#10.itm}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:acc#14" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:acc#14" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:acc#14" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:acc#14" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:acc#14" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:acc#14" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:acc#14" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:acc#14" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {b(2).sva#3(0)} -pin  "FRAME:for:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(1)} -pin  "FRAME:for:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(2)} -pin  "FRAME:for:acc#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(3)} -pin  "FRAME:for:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(4)} -pin  "FRAME:for:acc#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(5)} -pin  "FRAME:for:acc#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(6)} -pin  "FRAME:for:acc#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(7)} -pin  "FRAME:for:acc#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(8)} -pin  "FRAME:for:acc#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(9)} -pin  "FRAME:for:acc#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(10)} -pin  "FRAME:for:acc#14" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(11)} -pin  "FRAME:for:acc#14" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(12)} -pin  "FRAME:for:acc#14" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(13)} -pin  "FRAME:for:acc#14" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(14)} -pin  "FRAME:for:acc#14" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load net {b(2).sva#3(15)} -pin  "FRAME:for:acc#14" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#3}
+load inst "ACC1:not#16" "not(10)" "INTERFACE" -attr xrf 12088 -attr oid 476 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "ACC1:not#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "ACC1:not#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "ACC1:not#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "ACC1:not#16" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "ACC1:not#16" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "ACC1:not#16" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "ACC1:not#16" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "ACC1:not#16" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "ACC1:not#16" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:not#16" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:not#16.itm(0)} -pin  "ACC1:not#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(1)} -pin  "ACC1:not#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(2)} -pin  "ACC1:not#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(3)} -pin  "ACC1:not#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(4)} -pin  "ACC1:not#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(5)} -pin  "ACC1:not#16" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(6)} -pin  "ACC1:not#16" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(7)} -pin  "ACC1:not#16" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(8)} -pin  "ACC1:not#16" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load net {ACC1:not#16.itm(9)} -pin  "ACC1:not#16" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#16.itm}
+load inst "ACC1:acc#46" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 12089 -attr oid 477 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#46" {A(0)} -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {ACC1:not#16.itm(0)} -pin  "ACC1:acc#46" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {ACC1:not#16.itm(1)} -pin  "ACC1:acc#46" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {ACC1:not#16.itm(2)} -pin  "ACC1:acc#46" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {ACC1:not#16.itm(3)} -pin  "ACC1:acc#46" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {ACC1:not#16.itm(4)} -pin  "ACC1:acc#46" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {ACC1:not#16.itm(5)} -pin  "ACC1:acc#46" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {ACC1:not#16.itm(6)} -pin  "ACC1:acc#46" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {ACC1:not#16.itm(7)} -pin  "ACC1:acc#46" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {ACC1:not#16.itm(8)} -pin  "ACC1:acc#46" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {ACC1:not#16.itm(9)} -pin  "ACC1:acc#46" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#163.itm}
+load net {PWR} -pin  "ACC1:acc#46" {B(0)} -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {regs.regs(1).sva(0)} -pin  "ACC1:acc#46" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {regs.regs(1).sva(1)} -pin  "ACC1:acc#46" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {regs.regs(1).sva(2)} -pin  "ACC1:acc#46" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {regs.regs(1).sva(3)} -pin  "ACC1:acc#46" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {regs.regs(1).sva(4)} -pin  "ACC1:acc#46" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {regs.regs(1).sva(5)} -pin  "ACC1:acc#46" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {regs.regs(1).sva(6)} -pin  "ACC1:acc#46" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {regs.regs(1).sva(7)} -pin  "ACC1:acc#46" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {regs.regs(1).sva(8)} -pin  "ACC1:acc#46" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {regs.regs(1).sva(9)} -pin  "ACC1:acc#46" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#164.itm}
+load net {ACC1:acc#46.itm(0)} -pin  "ACC1:acc#46" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46.itm}
+load net {ACC1:acc#46.itm(1)} -pin  "ACC1:acc#46" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46.itm}
+load net {ACC1:acc#46.itm(2)} -pin  "ACC1:acc#46" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46.itm}
+load net {ACC1:acc#46.itm(3)} -pin  "ACC1:acc#46" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46.itm}
+load net {ACC1:acc#46.itm(4)} -pin  "ACC1:acc#46" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46.itm}
+load net {ACC1:acc#46.itm(5)} -pin  "ACC1:acc#46" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46.itm}
+load net {ACC1:acc#46.itm(6)} -pin  "ACC1:acc#46" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46.itm}
+load net {ACC1:acc#46.itm(7)} -pin  "ACC1:acc#46" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46.itm}
+load net {ACC1:acc#46.itm(8)} -pin  "ACC1:acc#46" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46.itm}
+load net {ACC1:acc#46.itm(9)} -pin  "ACC1:acc#46" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46.itm}
+load net {ACC1:acc#46.itm(10)} -pin  "ACC1:acc#46" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46.itm}
+load net {ACC1:acc#46.itm(11)} -pin  "ACC1:acc#46" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#46.itm}
+load inst "FRAME:for:mux#9" "mux(2,16)" "INTERFACE" -attr xrf 12090 -attr oid 478 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#46.itm(1)} -pin  "FRAME:for:mux#9" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(2)} -pin  "FRAME:for:mux#9" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(3)} -pin  "FRAME:for:mux#9" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(4)} -pin  "FRAME:for:mux#9" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(5)} -pin  "FRAME:for:mux#9" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(6)} -pin  "FRAME:for:mux#9" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(7)} -pin  "FRAME:for:mux#9" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(8)} -pin  "FRAME:for:mux#9" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(9)} -pin  "FRAME:for:mux#9" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(10)} -pin  "FRAME:for:mux#9" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(11)} -pin  "FRAME:for:mux#9" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(11)} -pin  "FRAME:for:mux#9" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(11)} -pin  "FRAME:for:mux#9" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(11)} -pin  "FRAME:for:mux#9" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(11)} -pin  "FRAME:for:mux#9" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {ACC1:acc#46.itm(11)} -pin  "FRAME:for:mux#9" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#22.itm}
+load net {b(0).sva#1(0)} -pin  "FRAME:for:mux#9" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(1)} -pin  "FRAME:for:mux#9" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(2)} -pin  "FRAME:for:mux#9" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(3)} -pin  "FRAME:for:mux#9" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(4)} -pin  "FRAME:for:mux#9" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(5)} -pin  "FRAME:for:mux#9" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(6)} -pin  "FRAME:for:mux#9" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(7)} -pin  "FRAME:for:mux#9" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(8)} -pin  "FRAME:for:mux#9" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(9)} -pin  "FRAME:for:mux#9" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(10)} -pin  "FRAME:for:mux#9" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(11)} -pin  "FRAME:for:mux#9" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(12)} -pin  "FRAME:for:mux#9" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(13)} -pin  "FRAME:for:mux#9" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(14)} -pin  "FRAME:for:mux#9" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(15)} -pin  "FRAME:for:mux#9" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#9" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#9.itm(0)} -pin  "FRAME:for:mux#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(1)} -pin  "FRAME:for:mux#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(2)} -pin  "FRAME:for:mux#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(3)} -pin  "FRAME:for:mux#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(4)} -pin  "FRAME:for:mux#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(5)} -pin  "FRAME:for:mux#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(6)} -pin  "FRAME:for:mux#9" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(7)} -pin  "FRAME:for:mux#9" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(8)} -pin  "FRAME:for:mux#9" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(9)} -pin  "FRAME:for:mux#9" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(10)} -pin  "FRAME:for:mux#9" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(11)} -pin  "FRAME:for:mux#9" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(12)} -pin  "FRAME:for:mux#9" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(13)} -pin  "FRAME:for:mux#9" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(14)} -pin  "FRAME:for:mux#9" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(15)} -pin  "FRAME:for:mux#9" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load inst "regs.operator[]#11:mux" "mux(4,10)" "INTERFACE" -attr xrf 12091 -attr oid 479 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "regs.operator[]#11:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "regs.operator[]#11:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "regs.operator[]#11:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "regs.operator[]#11:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "regs.operator[]#11:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "regs.operator[]#11:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "regs.operator[]#11:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "regs.operator[]#11:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "regs.operator[]#11:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "regs.operator[]#11:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "regs.operator[]#11:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "regs.operator[]#11:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "regs.operator[]#11:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "regs.operator[]#11:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "regs.operator[]#11:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "regs.operator[]#11:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "regs.operator[]#11:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "regs.operator[]#11:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "regs.operator[]#11:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "regs.operator[]#11:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "regs.operator[]#11:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "regs.operator[]#11:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "regs.operator[]#11:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "regs.operator[]#11:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "regs.operator[]#11:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "regs.operator[]#11:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "regs.operator[]#11:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "regs.operator[]#11:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "regs.operator[]#11:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "regs.operator[]#11:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#11:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#11:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#11:mux.itm(0)} -pin  "regs.operator[]#11:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(1)} -pin  "regs.operator[]#11:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(2)} -pin  "regs.operator[]#11:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(3)} -pin  "regs.operator[]#11:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(4)} -pin  "regs.operator[]#11:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(5)} -pin  "regs.operator[]#11:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(6)} -pin  "regs.operator[]#11:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(7)} -pin  "regs.operator[]#11:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(8)} -pin  "regs.operator[]#11:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(9)} -pin  "regs.operator[]#11:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load inst "FRAME:for:mul#2" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 12092 -attr oid 480 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#11:mux.itm(0)} -pin  "FRAME:for:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(1)} -pin  "FRAME:for:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(2)} -pin  "FRAME:for:mul#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(3)} -pin  "FRAME:for:mul#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(4)} -pin  "FRAME:for:mul#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(5)} -pin  "FRAME:for:mul#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(6)} -pin  "FRAME:for:mul#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(7)} -pin  "FRAME:for:mul#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(8)} -pin  "FRAME:for:mul#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(9)} -pin  "FRAME:for:mul#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {PWR} -pin  "FRAME:for:mul#2" {B(1)} -attr @path {/sobel/sobel:core/conc#165.itm}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(11)} -pin  "FRAME:for:mul#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load inst "FRAME:for:acc#3" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 12093 -attr oid 481 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#9.itm(0)} -pin  "FRAME:for:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(1)} -pin  "FRAME:for:acc#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(2)} -pin  "FRAME:for:acc#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(3)} -pin  "FRAME:for:acc#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(4)} -pin  "FRAME:for:acc#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(5)} -pin  "FRAME:for:acc#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(6)} -pin  "FRAME:for:acc#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(7)} -pin  "FRAME:for:acc#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(8)} -pin  "FRAME:for:acc#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(9)} -pin  "FRAME:for:acc#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(10)} -pin  "FRAME:for:acc#3" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(11)} -pin  "FRAME:for:acc#3" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(12)} -pin  "FRAME:for:acc#3" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(13)} -pin  "FRAME:for:acc#3" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(14)} -pin  "FRAME:for:acc#3" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mux#9.itm(15)} -pin  "FRAME:for:acc#3" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#9.itm}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:acc#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:acc#3" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:acc#3" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:acc#3" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:acc#3" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:acc#3" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:acc#3" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:acc#3" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:acc#3" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:acc#3" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(11)} -pin  "FRAME:for:acc#3" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {b(0).sva#3(0)} -pin  "FRAME:for:acc#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(1)} -pin  "FRAME:for:acc#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(2)} -pin  "FRAME:for:acc#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(3)} -pin  "FRAME:for:acc#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(4)} -pin  "FRAME:for:acc#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(5)} -pin  "FRAME:for:acc#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(6)} -pin  "FRAME:for:acc#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(7)} -pin  "FRAME:for:acc#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(8)} -pin  "FRAME:for:acc#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(9)} -pin  "FRAME:for:acc#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(10)} -pin  "FRAME:for:acc#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(11)} -pin  "FRAME:for:acc#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(12)} -pin  "FRAME:for:acc#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(13)} -pin  "FRAME:for:acc#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(14)} -pin  "FRAME:for:acc#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load net {b(0).sva#3(15)} -pin  "FRAME:for:acc#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#3}
+load inst "ACC1:not#13" "not(10)" "INTERFACE" -attr xrf 12094 -attr oid 482 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "ACC1:not#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "ACC1:not#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "ACC1:not#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "ACC1:not#13" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "ACC1:not#13" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "ACC1:not#13" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "ACC1:not#13" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "ACC1:not#13" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "ACC1:not#13" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:not#13" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {ACC1:not#13.itm(0)} -pin  "ACC1:not#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(1)} -pin  "ACC1:not#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(2)} -pin  "ACC1:not#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(3)} -pin  "ACC1:not#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(4)} -pin  "ACC1:not#13" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(5)} -pin  "ACC1:not#13" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(6)} -pin  "ACC1:not#13" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(7)} -pin  "ACC1:not#13" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(8)} -pin  "ACC1:not#13" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load net {ACC1:not#13.itm(9)} -pin  "ACC1:not#13" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#13.itm}
+load inst "ACC1:acc#48" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 12095 -attr oid 483 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#48" {A(0)} -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {ACC1:not#13.itm(0)} -pin  "ACC1:acc#48" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {ACC1:not#13.itm(1)} -pin  "ACC1:acc#48" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {ACC1:not#13.itm(2)} -pin  "ACC1:acc#48" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {ACC1:not#13.itm(3)} -pin  "ACC1:acc#48" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {ACC1:not#13.itm(4)} -pin  "ACC1:acc#48" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {ACC1:not#13.itm(5)} -pin  "ACC1:acc#48" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {ACC1:not#13.itm(6)} -pin  "ACC1:acc#48" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {ACC1:not#13.itm(7)} -pin  "ACC1:acc#48" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {ACC1:not#13.itm(8)} -pin  "ACC1:acc#48" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {ACC1:not#13.itm(9)} -pin  "ACC1:acc#48" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#166.itm}
+load net {PWR} -pin  "ACC1:acc#48" {B(0)} -attr @path {/sobel/sobel:core/conc#167.itm}
+load net {regs.regs(1).sva(70)} -pin  "ACC1:acc#48" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#167.itm}
+load net {regs.regs(1).sva(71)} -pin  "ACC1:acc#48" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#167.itm}
+load net {regs.regs(1).sva(72)} -pin  "ACC1:acc#48" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#167.itm}
+load net {regs.regs(1).sva(73)} -pin  "ACC1:acc#48" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#167.itm}
+load net {regs.regs(1).sva(74)} -pin  "ACC1:acc#48" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#167.itm}
+load net {regs.regs(1).sva(75)} -pin  "ACC1:acc#48" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#167.itm}
+load net {regs.regs(1).sva(76)} -pin  "ACC1:acc#48" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#167.itm}
+load net {regs.regs(1).sva(77)} -pin  "ACC1:acc#48" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#167.itm}
+load net {regs.regs(1).sva(78)} -pin  "ACC1:acc#48" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#167.itm}
+load net {regs.regs(1).sva(79)} -pin  "ACC1:acc#48" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#167.itm}
+load net {ACC1:acc#48.itm(0)} -pin  "ACC1:acc#48" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(1)} -pin  "ACC1:acc#48" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(2)} -pin  "ACC1:acc#48" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(3)} -pin  "ACC1:acc#48" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(4)} -pin  "ACC1:acc#48" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(5)} -pin  "ACC1:acc#48" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(6)} -pin  "ACC1:acc#48" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(7)} -pin  "ACC1:acc#48" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(8)} -pin  "ACC1:acc#48" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(9)} -pin  "ACC1:acc#48" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(10)} -pin  "ACC1:acc#48" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "ACC1:acc#48" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#48.itm}
+load inst "FRAME:for:mux#8" "mux(2,16)" "INTERFACE" -attr xrf 12096 -attr oid 484 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#48.itm(1)} -pin  "FRAME:for:mux#8" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(2)} -pin  "FRAME:for:mux#8" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(3)} -pin  "FRAME:for:mux#8" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(4)} -pin  "FRAME:for:mux#8" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(5)} -pin  "FRAME:for:mux#8" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(6)} -pin  "FRAME:for:mux#8" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(7)} -pin  "FRAME:for:mux#8" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(8)} -pin  "FRAME:for:mux#8" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(9)} -pin  "FRAME:for:mux#8" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(10)} -pin  "FRAME:for:mux#8" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#8" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#8" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#8" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#8" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#8" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {ACC1:acc#48.itm(11)} -pin  "FRAME:for:mux#8" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#24.itm}
+load net {g(2).sva#1(0)} -pin  "FRAME:for:mux#8" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(1)} -pin  "FRAME:for:mux#8" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(2)} -pin  "FRAME:for:mux#8" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(3)} -pin  "FRAME:for:mux#8" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(4)} -pin  "FRAME:for:mux#8" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(5)} -pin  "FRAME:for:mux#8" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(6)} -pin  "FRAME:for:mux#8" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(7)} -pin  "FRAME:for:mux#8" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(8)} -pin  "FRAME:for:mux#8" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(9)} -pin  "FRAME:for:mux#8" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(10)} -pin  "FRAME:for:mux#8" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(11)} -pin  "FRAME:for:mux#8" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(12)} -pin  "FRAME:for:mux#8" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(13)} -pin  "FRAME:for:mux#8" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(14)} -pin  "FRAME:for:mux#8" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(15)} -pin  "FRAME:for:mux#8" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#8" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#8.itm(0)} -pin  "FRAME:for:mux#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(1)} -pin  "FRAME:for:mux#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(2)} -pin  "FRAME:for:mux#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(3)} -pin  "FRAME:for:mux#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(4)} -pin  "FRAME:for:mux#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(5)} -pin  "FRAME:for:mux#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(6)} -pin  "FRAME:for:mux#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(7)} -pin  "FRAME:for:mux#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(8)} -pin  "FRAME:for:mux#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(9)} -pin  "FRAME:for:mux#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(10)} -pin  "FRAME:for:mux#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(11)} -pin  "FRAME:for:mux#8" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(12)} -pin  "FRAME:for:mux#8" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(13)} -pin  "FRAME:for:mux#8" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(14)} -pin  "FRAME:for:mux#8" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(15)} -pin  "FRAME:for:mux#8" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load inst "regs.operator[]#16:mux" "mux(4,10)" "INTERFACE" -attr xrf 12097 -attr oid 485 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "regs.operator[]#16:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "regs.operator[]#16:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "regs.operator[]#16:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "regs.operator[]#16:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "regs.operator[]#16:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "regs.operator[]#16:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "regs.operator[]#16:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "regs.operator[]#16:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "regs.operator[]#16:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "regs.operator[]#16:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "regs.operator[]#16:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "regs.operator[]#16:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "regs.operator[]#16:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "regs.operator[]#16:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "regs.operator[]#16:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "regs.operator[]#16:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "regs.operator[]#16:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "regs.operator[]#16:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "regs.operator[]#16:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "regs.operator[]#16:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "regs.operator[]#16:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "regs.operator[]#16:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "regs.operator[]#16:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "regs.operator[]#16:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "regs.operator[]#16:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "regs.operator[]#16:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "regs.operator[]#16:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "regs.operator[]#16:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "regs.operator[]#16:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "regs.operator[]#16:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#16:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#16:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#16:mux.itm(0)} -pin  "regs.operator[]#16:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(1)} -pin  "regs.operator[]#16:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(2)} -pin  "regs.operator[]#16:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(3)} -pin  "regs.operator[]#16:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(4)} -pin  "regs.operator[]#16:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(5)} -pin  "regs.operator[]#16:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(6)} -pin  "regs.operator[]#16:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(7)} -pin  "regs.operator[]#16:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(8)} -pin  "regs.operator[]#16:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(9)} -pin  "regs.operator[]#16:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load inst "FRAME:for:mul#7" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 12098 -attr oid 486 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#16:mux.itm(0)} -pin  "FRAME:for:mul#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(1)} -pin  "FRAME:for:mul#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(2)} -pin  "FRAME:for:mul#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(3)} -pin  "FRAME:for:mul#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(4)} -pin  "FRAME:for:mul#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(5)} -pin  "FRAME:for:mul#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(6)} -pin  "FRAME:for:mul#7" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(7)} -pin  "FRAME:for:mul#7" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(8)} -pin  "FRAME:for:mul#7" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(9)} -pin  "FRAME:for:mul#7" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:mul#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:mul#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:mul#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:mul#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:mul#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:mul#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:mul#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:mul#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:mul#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:mul#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:mul#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load inst "FRAME:for:acc#12" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 12099 -attr oid 487 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#8.itm(0)} -pin  "FRAME:for:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(1)} -pin  "FRAME:for:acc#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(2)} -pin  "FRAME:for:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(3)} -pin  "FRAME:for:acc#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(4)} -pin  "FRAME:for:acc#12" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(5)} -pin  "FRAME:for:acc#12" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(6)} -pin  "FRAME:for:acc#12" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(7)} -pin  "FRAME:for:acc#12" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(8)} -pin  "FRAME:for:acc#12" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(9)} -pin  "FRAME:for:acc#12" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(10)} -pin  "FRAME:for:acc#12" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(11)} -pin  "FRAME:for:acc#12" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(12)} -pin  "FRAME:for:acc#12" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(13)} -pin  "FRAME:for:acc#12" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(14)} -pin  "FRAME:for:acc#12" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mux#8.itm(15)} -pin  "FRAME:for:acc#12" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#8.itm}
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:acc#12" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:acc#12" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:acc#12" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:acc#12" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:acc#12" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:acc#12" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:acc#12" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:acc#12" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:acc#12" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {g(2).sva#3(0)} -pin  "FRAME:for:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(1)} -pin  "FRAME:for:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(2)} -pin  "FRAME:for:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(3)} -pin  "FRAME:for:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(4)} -pin  "FRAME:for:acc#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(5)} -pin  "FRAME:for:acc#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(6)} -pin  "FRAME:for:acc#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(7)} -pin  "FRAME:for:acc#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(8)} -pin  "FRAME:for:acc#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(9)} -pin  "FRAME:for:acc#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(10)} -pin  "FRAME:for:acc#12" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(11)} -pin  "FRAME:for:acc#12" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(12)} -pin  "FRAME:for:acc#12" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(13)} -pin  "FRAME:for:acc#12" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(14)} -pin  "FRAME:for:acc#12" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load net {g(2).sva#3(15)} -pin  "FRAME:for:acc#12" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#3}
+load inst "ACC1:not#15" "not(10)" "INTERFACE" -attr xrf 12100 -attr oid 488 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "ACC1:not#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "ACC1:not#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "ACC1:not#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "ACC1:not#15" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "ACC1:not#15" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "ACC1:not#15" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "ACC1:not#15" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "ACC1:not#15" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "ACC1:not#15" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:not#15" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {ACC1:not#15.itm(0)} -pin  "ACC1:not#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(1)} -pin  "ACC1:not#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(2)} -pin  "ACC1:not#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(3)} -pin  "ACC1:not#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(4)} -pin  "ACC1:not#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(5)} -pin  "ACC1:not#15" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(6)} -pin  "ACC1:not#15" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(7)} -pin  "ACC1:not#15" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(8)} -pin  "ACC1:not#15" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load net {ACC1:not#15.itm(9)} -pin  "ACC1:not#15" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#15.itm}
+load inst "ACC1:acc" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 12101 -attr oid 489 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc" {A(0)} -attr @path {/sobel/sobel:core/conc#168.itm}
+load net {ACC1:not#15.itm(0)} -pin  "ACC1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#168.itm}
+load net {ACC1:not#15.itm(1)} -pin  "ACC1:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#168.itm}
+load net {ACC1:not#15.itm(2)} -pin  "ACC1:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#168.itm}
+load net {ACC1:not#15.itm(3)} -pin  "ACC1:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#168.itm}
+load net {ACC1:not#15.itm(4)} -pin  "ACC1:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#168.itm}
+load net {ACC1:not#15.itm(5)} -pin  "ACC1:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#168.itm}
+load net {ACC1:not#15.itm(6)} -pin  "ACC1:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#168.itm}
+load net {ACC1:not#15.itm(7)} -pin  "ACC1:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#168.itm}
+load net {ACC1:not#15.itm(8)} -pin  "ACC1:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#168.itm}
+load net {ACC1:not#15.itm(9)} -pin  "ACC1:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#168.itm}
+load net {PWR} -pin  "ACC1:acc" {B(0)} -attr @path {/sobel/sobel:core/conc#169.itm}
+load net {regs.regs(1).sva(10)} -pin  "ACC1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#169.itm}
+load net {regs.regs(1).sva(11)} -pin  "ACC1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#169.itm}
+load net {regs.regs(1).sva(12)} -pin  "ACC1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#169.itm}
+load net {regs.regs(1).sva(13)} -pin  "ACC1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#169.itm}
+load net {regs.regs(1).sva(14)} -pin  "ACC1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#169.itm}
+load net {regs.regs(1).sva(15)} -pin  "ACC1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#169.itm}
+load net {regs.regs(1).sva(16)} -pin  "ACC1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#169.itm}
+load net {regs.regs(1).sva(17)} -pin  "ACC1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#169.itm}
+load net {regs.regs(1).sva(18)} -pin  "ACC1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#169.itm}
+load net {regs.regs(1).sva(19)} -pin  "ACC1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#169.itm}
+load net {ACC1:acc.itm(0)} -pin  "ACC1:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(1)} -pin  "ACC1:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(2)} -pin  "ACC1:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(3)} -pin  "ACC1:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(4)} -pin  "ACC1:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(5)} -pin  "ACC1:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(6)} -pin  "ACC1:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(7)} -pin  "ACC1:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(8)} -pin  "ACC1:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(9)} -pin  "ACC1:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(10)} -pin  "ACC1:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(11)} -pin  "ACC1:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load inst "FRAME:for:mux#7" "mux(2,16)" "INTERFACE" -attr xrf 12102 -attr oid 490 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc.itm(1)} -pin  "FRAME:for:mux#7" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(2)} -pin  "FRAME:for:mux#7" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(3)} -pin  "FRAME:for:mux#7" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(4)} -pin  "FRAME:for:mux#7" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:for:mux#7" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(6)} -pin  "FRAME:for:mux#7" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(7)} -pin  "FRAME:for:mux#7" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:for:mux#7" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:for:mux#7" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(10)} -pin  "FRAME:for:mux#7" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:for:mux#7" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {g(0).sva#1(0)} -pin  "FRAME:for:mux#7" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(1)} -pin  "FRAME:for:mux#7" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(2)} -pin  "FRAME:for:mux#7" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(3)} -pin  "FRAME:for:mux#7" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(4)} -pin  "FRAME:for:mux#7" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(5)} -pin  "FRAME:for:mux#7" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(6)} -pin  "FRAME:for:mux#7" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(7)} -pin  "FRAME:for:mux#7" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(8)} -pin  "FRAME:for:mux#7" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(9)} -pin  "FRAME:for:mux#7" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(10)} -pin  "FRAME:for:mux#7" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(11)} -pin  "FRAME:for:mux#7" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(12)} -pin  "FRAME:for:mux#7" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(13)} -pin  "FRAME:for:mux#7" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(14)} -pin  "FRAME:for:mux#7" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(15)} -pin  "FRAME:for:mux#7" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#7" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#7.itm(0)} -pin  "FRAME:for:mux#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(1)} -pin  "FRAME:for:mux#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(2)} -pin  "FRAME:for:mux#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(3)} -pin  "FRAME:for:mux#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(4)} -pin  "FRAME:for:mux#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(5)} -pin  "FRAME:for:mux#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(6)} -pin  "FRAME:for:mux#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(7)} -pin  "FRAME:for:mux#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(8)} -pin  "FRAME:for:mux#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(9)} -pin  "FRAME:for:mux#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(10)} -pin  "FRAME:for:mux#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(11)} -pin  "FRAME:for:mux#7" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(12)} -pin  "FRAME:for:mux#7" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(13)} -pin  "FRAME:for:mux#7" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(14)} -pin  "FRAME:for:mux#7" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(15)} -pin  "FRAME:for:mux#7" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load inst "regs.operator[]#10:mux" "mux(4,10)" "INTERFACE" -attr xrf 12103 -attr oid 491 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "regs.operator[]#10:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "regs.operator[]#10:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "regs.operator[]#10:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "regs.operator[]#10:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "regs.operator[]#10:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "regs.operator[]#10:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "regs.operator[]#10:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "regs.operator[]#10:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "regs.operator[]#10:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "regs.operator[]#10:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "regs.operator[]#10:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "regs.operator[]#10:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "regs.operator[]#10:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "regs.operator[]#10:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "regs.operator[]#10:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "regs.operator[]#10:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "regs.operator[]#10:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "regs.operator[]#10:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "regs.operator[]#10:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "regs.operator[]#10:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "regs.operator[]#10:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "regs.operator[]#10:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "regs.operator[]#10:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "regs.operator[]#10:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "regs.operator[]#10:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "regs.operator[]#10:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "regs.operator[]#10:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "regs.operator[]#10:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "regs.operator[]#10:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "regs.operator[]#10:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#10:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#10:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#10:mux.itm(0)} -pin  "regs.operator[]#10:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(1)} -pin  "regs.operator[]#10:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(2)} -pin  "regs.operator[]#10:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(3)} -pin  "regs.operator[]#10:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(4)} -pin  "regs.operator[]#10:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(5)} -pin  "regs.operator[]#10:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(6)} -pin  "regs.operator[]#10:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(7)} -pin  "regs.operator[]#10:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(8)} -pin  "regs.operator[]#10:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(9)} -pin  "regs.operator[]#10:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load inst "FRAME:for:mul#1" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 12104 -attr oid 492 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#10:mux.itm(0)} -pin  "FRAME:for:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(1)} -pin  "FRAME:for:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(2)} -pin  "FRAME:for:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(3)} -pin  "FRAME:for:mul#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(4)} -pin  "FRAME:for:mul#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(5)} -pin  "FRAME:for:mul#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(6)} -pin  "FRAME:for:mul#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(7)} -pin  "FRAME:for:mul#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(8)} -pin  "FRAME:for:mul#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(9)} -pin  "FRAME:for:mul#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#170.itm}
+load net {PWR} -pin  "FRAME:for:mul#1" {B(1)} -attr @path {/sobel/sobel:core/conc#170.itm}
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:mul#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:mul#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(11)} -pin  "FRAME:for:mul#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load inst "FRAME:for:acc#2" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 12105 -attr oid 493 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#7.itm(0)} -pin  "FRAME:for:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(1)} -pin  "FRAME:for:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(2)} -pin  "FRAME:for:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(3)} -pin  "FRAME:for:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(4)} -pin  "FRAME:for:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(5)} -pin  "FRAME:for:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(6)} -pin  "FRAME:for:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(7)} -pin  "FRAME:for:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(8)} -pin  "FRAME:for:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(9)} -pin  "FRAME:for:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(10)} -pin  "FRAME:for:acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(11)} -pin  "FRAME:for:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(12)} -pin  "FRAME:for:acc#2" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(13)} -pin  "FRAME:for:acc#2" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(14)} -pin  "FRAME:for:acc#2" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mux#7.itm(15)} -pin  "FRAME:for:acc#2" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#7.itm}
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(11)} -pin  "FRAME:for:acc#2" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {g(0).sva#3(0)} -pin  "FRAME:for:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(1)} -pin  "FRAME:for:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(2)} -pin  "FRAME:for:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(3)} -pin  "FRAME:for:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(4)} -pin  "FRAME:for:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(5)} -pin  "FRAME:for:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(6)} -pin  "FRAME:for:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(7)} -pin  "FRAME:for:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(8)} -pin  "FRAME:for:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(9)} -pin  "FRAME:for:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(10)} -pin  "FRAME:for:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(11)} -pin  "FRAME:for:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(12)} -pin  "FRAME:for:acc#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(13)} -pin  "FRAME:for:acc#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(14)} -pin  "FRAME:for:acc#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load net {g(0).sva#3(15)} -pin  "FRAME:for:acc#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#3}
+load inst "ACC1:not#12" "not(10)" "INTERFACE" -attr xrf 12106 -attr oid 494 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "ACC1:not#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "ACC1:not#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "ACC1:not#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "ACC1:not#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "ACC1:not#12" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "ACC1:not#12" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "ACC1:not#12" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "ACC1:not#12" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "ACC1:not#12" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1:not#12" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {ACC1:not#12.itm(0)} -pin  "ACC1:not#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(1)} -pin  "ACC1:not#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(2)} -pin  "ACC1:not#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(3)} -pin  "ACC1:not#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(4)} -pin  "ACC1:not#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(5)} -pin  "ACC1:not#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(6)} -pin  "ACC1:not#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(7)} -pin  "ACC1:not#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(8)} -pin  "ACC1:not#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load net {ACC1:not#12.itm(9)} -pin  "ACC1:not#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#12.itm}
+load inst "ACC1:acc#47" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 12107 -attr oid 495 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#47" {A(0)} -attr @path {/sobel/sobel:core/conc#171.itm}
+load net {ACC1:not#12.itm(0)} -pin  "ACC1:acc#47" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#171.itm}
+load net {ACC1:not#12.itm(1)} -pin  "ACC1:acc#47" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#171.itm}
+load net {ACC1:not#12.itm(2)} -pin  "ACC1:acc#47" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#171.itm}
+load net {ACC1:not#12.itm(3)} -pin  "ACC1:acc#47" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#171.itm}
+load net {ACC1:not#12.itm(4)} -pin  "ACC1:acc#47" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#171.itm}
+load net {ACC1:not#12.itm(5)} -pin  "ACC1:acc#47" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#171.itm}
+load net {ACC1:not#12.itm(6)} -pin  "ACC1:acc#47" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#171.itm}
+load net {ACC1:not#12.itm(7)} -pin  "ACC1:acc#47" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#171.itm}
+load net {ACC1:not#12.itm(8)} -pin  "ACC1:acc#47" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#171.itm}
+load net {ACC1:not#12.itm(9)} -pin  "ACC1:acc#47" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#171.itm}
+load net {PWR} -pin  "ACC1:acc#47" {B(0)} -attr @path {/sobel/sobel:core/conc#172.itm}
+load net {regs.regs(1).sva(80)} -pin  "ACC1:acc#47" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#172.itm}
+load net {regs.regs(1).sva(81)} -pin  "ACC1:acc#47" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#172.itm}
+load net {regs.regs(1).sva(82)} -pin  "ACC1:acc#47" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#172.itm}
+load net {regs.regs(1).sva(83)} -pin  "ACC1:acc#47" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#172.itm}
+load net {regs.regs(1).sva(84)} -pin  "ACC1:acc#47" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#172.itm}
+load net {regs.regs(1).sva(85)} -pin  "ACC1:acc#47" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#172.itm}
+load net {regs.regs(1).sva(86)} -pin  "ACC1:acc#47" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#172.itm}
+load net {regs.regs(1).sva(87)} -pin  "ACC1:acc#47" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#172.itm}
+load net {regs.regs(1).sva(88)} -pin  "ACC1:acc#47" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#172.itm}
+load net {regs.regs(1).sva(89)} -pin  "ACC1:acc#47" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#172.itm}
+load net {ACC1:acc#47.itm(0)} -pin  "ACC1:acc#47" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(1)} -pin  "ACC1:acc#47" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(2)} -pin  "ACC1:acc#47" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(3)} -pin  "ACC1:acc#47" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(4)} -pin  "ACC1:acc#47" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(5)} -pin  "ACC1:acc#47" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(6)} -pin  "ACC1:acc#47" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(7)} -pin  "ACC1:acc#47" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(8)} -pin  "ACC1:acc#47" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(9)} -pin  "ACC1:acc#47" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(10)} -pin  "ACC1:acc#47" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load net {ACC1:acc#47.itm(11)} -pin  "ACC1:acc#47" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#47.itm}
+load inst "FRAME:for:mux#6" "mux(2,16)" "INTERFACE" -attr xrf 12108 -attr oid 496 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#47.itm(1)} -pin  "FRAME:for:mux#6" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(2)} -pin  "FRAME:for:mux#6" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(3)} -pin  "FRAME:for:mux#6" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(4)} -pin  "FRAME:for:mux#6" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(5)} -pin  "FRAME:for:mux#6" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(6)} -pin  "FRAME:for:mux#6" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(7)} -pin  "FRAME:for:mux#6" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(8)} -pin  "FRAME:for:mux#6" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(9)} -pin  "FRAME:for:mux#6" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(10)} -pin  "FRAME:for:mux#6" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(11)} -pin  "FRAME:for:mux#6" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(11)} -pin  "FRAME:for:mux#6" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(11)} -pin  "FRAME:for:mux#6" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(11)} -pin  "FRAME:for:mux#6" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(11)} -pin  "FRAME:for:mux#6" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {ACC1:acc#47.itm(11)} -pin  "FRAME:for:mux#6" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#23.itm}
+load net {r(2).sva#1(0)} -pin  "FRAME:for:mux#6" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(1)} -pin  "FRAME:for:mux#6" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(2)} -pin  "FRAME:for:mux#6" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(3)} -pin  "FRAME:for:mux#6" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(4)} -pin  "FRAME:for:mux#6" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(5)} -pin  "FRAME:for:mux#6" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(6)} -pin  "FRAME:for:mux#6" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(7)} -pin  "FRAME:for:mux#6" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(8)} -pin  "FRAME:for:mux#6" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(9)} -pin  "FRAME:for:mux#6" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(10)} -pin  "FRAME:for:mux#6" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(11)} -pin  "FRAME:for:mux#6" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(12)} -pin  "FRAME:for:mux#6" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(13)} -pin  "FRAME:for:mux#6" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(14)} -pin  "FRAME:for:mux#6" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(15)} -pin  "FRAME:for:mux#6" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#6" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#6.itm(0)} -pin  "FRAME:for:mux#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(1)} -pin  "FRAME:for:mux#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(2)} -pin  "FRAME:for:mux#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(3)} -pin  "FRAME:for:mux#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(4)} -pin  "FRAME:for:mux#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(5)} -pin  "FRAME:for:mux#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(6)} -pin  "FRAME:for:mux#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(7)} -pin  "FRAME:for:mux#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(8)} -pin  "FRAME:for:mux#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(9)} -pin  "FRAME:for:mux#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(10)} -pin  "FRAME:for:mux#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(11)} -pin  "FRAME:for:mux#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(12)} -pin  "FRAME:for:mux#6" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(13)} -pin  "FRAME:for:mux#6" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(14)} -pin  "FRAME:for:mux#6" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(15)} -pin  "FRAME:for:mux#6" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load inst "regs.operator[]#15:mux" "mux(4,10)" "INTERFACE" -attr xrf 12109 -attr oid 497 -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "regs.operator[]#15:mux" {A1(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "regs.operator[]#15:mux" {A1(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "regs.operator[]#15:mux" {A1(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "regs.operator[]#15:mux" {A1(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "regs.operator[]#15:mux" {A1(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "regs.operator[]#15:mux" {A1(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "regs.operator[]#15:mux" {A1(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "regs.operator[]#15:mux" {A1(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "regs.operator[]#15:mux" {A1(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "regs.operator[]#15:mux" {A1(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "regs.operator[]#15:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "regs.operator[]#15:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "regs.operator[]#15:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "regs.operator[]#15:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "regs.operator[]#15:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "regs.operator[]#15:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "regs.operator[]#15:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "regs.operator[]#15:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "regs.operator[]#15:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "regs.operator[]#15:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "regs.operator[]#15:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "regs.operator[]#15:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "regs.operator[]#15:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "regs.operator[]#15:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "regs.operator[]#15:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "regs.operator[]#15:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "regs.operator[]#15:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "regs.operator[]#15:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "regs.operator[]#15:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "regs.operator[]#15:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#15:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#15:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#15:mux.itm(0)} -pin  "regs.operator[]#15:mux" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(1)} -pin  "regs.operator[]#15:mux" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(2)} -pin  "regs.operator[]#15:mux" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(3)} -pin  "regs.operator[]#15:mux" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(4)} -pin  "regs.operator[]#15:mux" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(5)} -pin  "regs.operator[]#15:mux" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(6)} -pin  "regs.operator[]#15:mux" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(7)} -pin  "regs.operator[]#15:mux" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(8)} -pin  "regs.operator[]#15:mux" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(9)} -pin  "regs.operator[]#15:mux" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load inst "FRAME:for:mul#6" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 12110 -attr oid 498 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#15:mux.itm(0)} -pin  "FRAME:for:mul#6" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(1)} -pin  "FRAME:for:mul#6" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(2)} -pin  "FRAME:for:mul#6" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(3)} -pin  "FRAME:for:mul#6" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(4)} -pin  "FRAME:for:mul#6" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(5)} -pin  "FRAME:for:mul#6" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(6)} -pin  "FRAME:for:mul#6" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(7)} -pin  "FRAME:for:mul#6" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(8)} -pin  "FRAME:for:mul#6" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(9)} -pin  "FRAME:for:mul#6" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:mul#6" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:mul#6" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:mul#6" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:mul#6" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:mul#6" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:mul#6" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:mul#6" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:mul#6" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:mul#6" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:mul#6" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:mul#6" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load inst "FRAME:for:acc#10" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 12111 -attr oid 499 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:acc#10} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#6.itm(0)} -pin  "FRAME:for:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(1)} -pin  "FRAME:for:acc#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(2)} -pin  "FRAME:for:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(3)} -pin  "FRAME:for:acc#10" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(4)} -pin  "FRAME:for:acc#10" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(5)} -pin  "FRAME:for:acc#10" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(6)} -pin  "FRAME:for:acc#10" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(7)} -pin  "FRAME:for:acc#10" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(8)} -pin  "FRAME:for:acc#10" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(9)} -pin  "FRAME:for:acc#10" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(10)} -pin  "FRAME:for:acc#10" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(11)} -pin  "FRAME:for:acc#10" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(12)} -pin  "FRAME:for:acc#10" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(13)} -pin  "FRAME:for:acc#10" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(14)} -pin  "FRAME:for:acc#10" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mux#6.itm(15)} -pin  "FRAME:for:acc#10" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#6.itm}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:acc#10" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:acc#10" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:acc#10" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:acc#10" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:acc#10" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:acc#10" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:acc#10" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:acc#10" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:acc#10" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:acc#10" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:acc#10" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {r(2).sva#3(0)} -pin  "FRAME:for:acc#10" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(1)} -pin  "FRAME:for:acc#10" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(2)} -pin  "FRAME:for:acc#10" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(3)} -pin  "FRAME:for:acc#10" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(4)} -pin  "FRAME:for:acc#10" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(5)} -pin  "FRAME:for:acc#10" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(6)} -pin  "FRAME:for:acc#10" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(7)} -pin  "FRAME:for:acc#10" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(8)} -pin  "FRAME:for:acc#10" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(9)} -pin  "FRAME:for:acc#10" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(10)} -pin  "FRAME:for:acc#10" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(11)} -pin  "FRAME:for:acc#10" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(12)} -pin  "FRAME:for:acc#10" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(13)} -pin  "FRAME:for:acc#10" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(14)} -pin  "FRAME:for:acc#10" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load net {r(2).sva#3(15)} -pin  "FRAME:for:acc#10" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#3}
+load inst "ACC1:not" "not(10)" "INTERFACE" -attr xrf 12112 -attr oid 500 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "ACC1:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "ACC1:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "ACC1:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "ACC1:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "ACC1:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "ACC1:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "ACC1:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "ACC1:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "ACC1:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load inst "ACC1:acc#45" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 12113 -attr oid 501 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#45" {A(0)} -attr @path {/sobel/sobel:core/conc#173.itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:acc#45" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#173.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:acc#45" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#173.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:acc#45" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#173.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:acc#45" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#173.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:acc#45" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#173.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:acc#45" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#173.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:acc#45" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#173.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:acc#45" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#173.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:acc#45" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#173.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:acc#45" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#173.itm}
+load net {PWR} -pin  "ACC1:acc#45" {B(0)} -attr @path {/sobel/sobel:core/conc#174.itm}
+load net {regs.regs(1).sva(20)} -pin  "ACC1:acc#45" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#174.itm}
+load net {regs.regs(1).sva(21)} -pin  "ACC1:acc#45" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#174.itm}
+load net {regs.regs(1).sva(22)} -pin  "ACC1:acc#45" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#174.itm}
+load net {regs.regs(1).sva(23)} -pin  "ACC1:acc#45" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#174.itm}
+load net {regs.regs(1).sva(24)} -pin  "ACC1:acc#45" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#174.itm}
+load net {regs.regs(1).sva(25)} -pin  "ACC1:acc#45" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#174.itm}
+load net {regs.regs(1).sva(26)} -pin  "ACC1:acc#45" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#174.itm}
+load net {regs.regs(1).sva(27)} -pin  "ACC1:acc#45" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#174.itm}
+load net {regs.regs(1).sva(28)} -pin  "ACC1:acc#45" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#174.itm}
+load net {regs.regs(1).sva(29)} -pin  "ACC1:acc#45" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#174.itm}
+load net {ACC1:acc#45.itm(0)} -pin  "ACC1:acc#45" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(1)} -pin  "ACC1:acc#45" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(2)} -pin  "ACC1:acc#45" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(3)} -pin  "ACC1:acc#45" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(4)} -pin  "ACC1:acc#45" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(5)} -pin  "ACC1:acc#45" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(6)} -pin  "ACC1:acc#45" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(7)} -pin  "ACC1:acc#45" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(8)} -pin  "ACC1:acc#45" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(9)} -pin  "ACC1:acc#45" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(10)} -pin  "ACC1:acc#45" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "ACC1:acc#45" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#45.itm}
+load inst "FRAME:for:mux#5" "mux(2,16)" "INTERFACE" -attr xrf 12114 -attr oid 502 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {ACC1:acc#45.itm(1)} -pin  "FRAME:for:mux#5" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(2)} -pin  "FRAME:for:mux#5" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(3)} -pin  "FRAME:for:mux#5" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(4)} -pin  "FRAME:for:mux#5" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(5)} -pin  "FRAME:for:mux#5" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(6)} -pin  "FRAME:for:mux#5" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(7)} -pin  "FRAME:for:mux#5" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(8)} -pin  "FRAME:for:mux#5" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(9)} -pin  "FRAME:for:mux#5" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(10)} -pin  "FRAME:for:mux#5" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "FRAME:for:mux#5" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "FRAME:for:mux#5" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "FRAME:for:mux#5" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "FRAME:for:mux#5" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "FRAME:for:mux#5" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {ACC1:acc#45.itm(11)} -pin  "FRAME:for:mux#5" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {r(0).sva#1(0)} -pin  "FRAME:for:mux#5" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(1)} -pin  "FRAME:for:mux#5" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(2)} -pin  "FRAME:for:mux#5" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(3)} -pin  "FRAME:for:mux#5" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(4)} -pin  "FRAME:for:mux#5" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(5)} -pin  "FRAME:for:mux#5" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(6)} -pin  "FRAME:for:mux#5" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(7)} -pin  "FRAME:for:mux#5" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(8)} -pin  "FRAME:for:mux#5" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(9)} -pin  "FRAME:for:mux#5" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(10)} -pin  "FRAME:for:mux#5" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(11)} -pin  "FRAME:for:mux#5" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(12)} -pin  "FRAME:for:mux#5" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(13)} -pin  "FRAME:for:mux#5" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(14)} -pin  "FRAME:for:mux#5" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(15)} -pin  "FRAME:for:mux#5" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:mux#5" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {FRAME:for:mux#5.itm(0)} -pin  "FRAME:for:mux#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(1)} -pin  "FRAME:for:mux#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(2)} -pin  "FRAME:for:mux#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(3)} -pin  "FRAME:for:mux#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(4)} -pin  "FRAME:for:mux#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(5)} -pin  "FRAME:for:mux#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(6)} -pin  "FRAME:for:mux#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(7)} -pin  "FRAME:for:mux#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(8)} -pin  "FRAME:for:mux#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(9)} -pin  "FRAME:for:mux#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(10)} -pin  "FRAME:for:mux#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(11)} -pin  "FRAME:for:mux#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(12)} -pin  "FRAME:for:mux#5" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(13)} -pin  "FRAME:for:mux#5" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(14)} -pin  "FRAME:for:mux#5" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(15)} -pin  "FRAME:for:mux#5" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load inst "regs.operator[]#9:mux" "mux(4,10)" "INTERFACE" -attr xrf 12115 -attr oid 503 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "regs.operator[]#9:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "regs.operator[]#9:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "regs.operator[]#9:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "regs.operator[]#9:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "regs.operator[]#9:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "regs.operator[]#9:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "regs.operator[]#9:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "regs.operator[]#9:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "regs.operator[]#9:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "regs.operator[]#9:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "regs.operator[]#9:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "regs.operator[]#9:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "regs.operator[]#9:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "regs.operator[]#9:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "regs.operator[]#9:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "regs.operator[]#9:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "regs.operator[]#9:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "regs.operator[]#9:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "regs.operator[]#9:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "regs.operator[]#9:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "regs.operator[]#9:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "regs.operator[]#9:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "regs.operator[]#9:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "regs.operator[]#9:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "regs.operator[]#9:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "regs.operator[]#9:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "regs.operator[]#9:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "regs.operator[]#9:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "regs.operator[]#9:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "regs.operator[]#9:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#9:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#9:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#9:mux.itm(0)} -pin  "regs.operator[]#9:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(1)} -pin  "regs.operator[]#9:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(2)} -pin  "regs.operator[]#9:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(3)} -pin  "regs.operator[]#9:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(4)} -pin  "regs.operator[]#9:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(5)} -pin  "regs.operator[]#9:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(6)} -pin  "regs.operator[]#9:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(7)} -pin  "regs.operator[]#9:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(8)} -pin  "regs.operator[]#9:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(9)} -pin  "regs.operator[]#9:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load inst "FRAME:for:mul" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 12116 -attr oid 504 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#9:mux.itm(0)} -pin  "FRAME:for:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(1)} -pin  "FRAME:for:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(2)} -pin  "FRAME:for:mul" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(3)} -pin  "FRAME:for:mul" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(4)} -pin  "FRAME:for:mul" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(5)} -pin  "FRAME:for:mul" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(6)} -pin  "FRAME:for:mul" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(7)} -pin  "FRAME:for:mul" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(8)} -pin  "FRAME:for:mul" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(9)} -pin  "FRAME:for:mul" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#175.itm}
+load net {PWR} -pin  "FRAME:for:mul" {B(1)} -attr @path {/sobel/sobel:core/conc#175.itm}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(11)} -pin  "FRAME:for:mul" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load inst "FRAME:for:acc#1" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 12117 -attr oid 505 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {FRAME:for:mux#5.itm(0)} -pin  "FRAME:for:acc#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(1)} -pin  "FRAME:for:acc#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(2)} -pin  "FRAME:for:acc#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(3)} -pin  "FRAME:for:acc#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(4)} -pin  "FRAME:for:acc#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(5)} -pin  "FRAME:for:acc#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(6)} -pin  "FRAME:for:acc#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(7)} -pin  "FRAME:for:acc#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(8)} -pin  "FRAME:for:acc#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(9)} -pin  "FRAME:for:acc#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(10)} -pin  "FRAME:for:acc#1" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(11)} -pin  "FRAME:for:acc#1" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(12)} -pin  "FRAME:for:acc#1" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(13)} -pin  "FRAME:for:acc#1" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(14)} -pin  "FRAME:for:acc#1" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mux#5.itm(15)} -pin  "FRAME:for:acc#1" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#5.itm}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:acc#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:acc#1" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:acc#1" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:acc#1" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:acc#1" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:acc#1" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:acc#1" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:acc#1" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:acc#1" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:acc#1" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:acc#1" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(11)} -pin  "FRAME:for:acc#1" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {r(0).sva#3(0)} -pin  "FRAME:for:acc#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(1)} -pin  "FRAME:for:acc#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(2)} -pin  "FRAME:for:acc#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(3)} -pin  "FRAME:for:acc#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(4)} -pin  "FRAME:for:acc#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(5)} -pin  "FRAME:for:acc#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(6)} -pin  "FRAME:for:acc#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(7)} -pin  "FRAME:for:acc#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(8)} -pin  "FRAME:for:acc#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(9)} -pin  "FRAME:for:acc#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(10)} -pin  "FRAME:for:acc#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(11)} -pin  "FRAME:for:acc#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(12)} -pin  "FRAME:for:acc#1" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(13)} -pin  "FRAME:for:acc#1" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(14)} -pin  "FRAME:for:acc#1" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load net {r(0).sva#3(15)} -pin  "FRAME:for:acc#1" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#3}
+load inst "FRAME:for:nor" "nor(2,1)" "INTERFACE" -attr xrf 12118 -attr oid 506 -attr @path {/sobel/sobel:core/FRAME:for:nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:nor" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#3.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nor" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#4.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:nor" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load inst "FRAME:for:not#8" "not(1)" "INTERFACE" -attr xrf 12119 -attr oid 507 -attr @path {/sobel/sobel:core/FRAME:for:not#8} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#8" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#10.itm}
+load net {FRAME:for:not#8.itm} -pin  "FRAME:for:not#8" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#8.itm}
+load inst "FRAME:for:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 12120 -attr oid 508 -attr @path {/sobel/sobel:core/FRAME:for:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {FRAME:for:not#8.itm} -pin  "FRAME:for:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#8.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#5.itm}
+load net {FRAME:for:nand#1.itm} -pin  "FRAME:for:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#1.itm}
+load inst "FRAME:for:or#4" "or(2,1)" "INTERFACE" -attr xrf 12121 -attr oid 509 -attr @path {/sobel/sobel:core/FRAME:for:or#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {FRAME:for:nand#1.itm} -pin  "FRAME:for:or#4" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#1.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or#4" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:or#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#4.itm}
+load inst "FRAME:for:not#5" "not(1)" "INTERFACE" -attr xrf 12122 -attr oid 510 -attr @path {/sobel/sobel:core/FRAME:for:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#5" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#8.itm}
+load net {FRAME:for:not#5.itm} -pin  "FRAME:for:not#5" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#5.itm}
+load inst "FRAME:for:nand" "nand(2,1)" "INTERFACE" -attr xrf 12123 -attr oid 511 -attr @path {/sobel/sobel:core/FRAME:for:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#6.itm}
+load net {FRAME:for:not#5.itm} -pin  "FRAME:for:nand" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#5.itm}
+load net {FRAME:for:nand.itm} -pin  "FRAME:for:nand" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand.itm}
+load inst "FRAME:for:not#2" "not(1)" "INTERFACE" -attr xrf 12124 -attr oid 512 -attr @path {/sobel/sobel:core/FRAME:for:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:not#2" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#7.itm}
+load net {FRAME:for:not#2.itm} -pin  "FRAME:for:not#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#2.itm}
+load inst "FRAME:for:and#3" "and(2,1)" "INTERFACE" -attr xrf 12125 -attr oid 513 -attr @path {/sobel/sobel:core/FRAME:for:and#3} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#9.itm}
+load net {FRAME:for:not#2.itm} -pin  "FRAME:for:and#3" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#2.itm}
+load net {FRAME:for:and#3.itm} -pin  "FRAME:for:and#3" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#3.itm}
+load inst "FRAME:for:or#3" "or(3,1)" "INTERFACE" -attr xrf 12126 -attr oid 514 -attr @path {/sobel/sobel:core/FRAME:for:or#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,3)"
+load net {FRAME:for:nand.itm} -pin  "FRAME:for:or#3" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or#3" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:and#3.itm} -pin  "FRAME:for:or#3" {A2(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#3.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:or#3" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#3.itm}
+load inst "nor" "nor(2,1)" "INTERFACE" -attr vt c -attr @path {/sobel/sobel:core/nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "nor" {A0(0)} -attr vt c -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {exit:FRAME#1.sva} -pin  "nor" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {and.dcpl} -pin  "nor" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/and.dcpl}
+### END MODULE 
+
+module new "sobel" "orig"
+load portBus {vin:rsc.z(89:0)} input 90 {vin:rsc.z(89)} {vin:rsc.z(88)} {vin:rsc.z(87)} {vin:rsc.z(86)} {vin:rsc.z(85)} {vin:rsc.z(84)} {vin:rsc.z(83)} {vin:rsc.z(82)} {vin:rsc.z(81)} {vin:rsc.z(80)} {vin:rsc.z(79)} {vin:rsc.z(78)} {vin:rsc.z(77)} {vin:rsc.z(76)} {vin:rsc.z(75)} {vin:rsc.z(74)} {vin:rsc.z(73)} {vin:rsc.z(72)} {vin:rsc.z(71)} {vin:rsc.z(70)} {vin:rsc.z(69)} {vin:rsc.z(68)} {vin:rsc.z(67)} {vin:rsc.z(66)} {vin:rsc.z(65)} {vin:rsc.z(64)} {vin:rsc.z(63)} {vin:rsc.z(62)} {vin:rsc.z(61)} {vin:rsc.z(60)} {vin:rsc.z(59)} {vin:rsc.z(58)} {vin:rsc.z(57)} {vin:rsc.z(56)} {vin:rsc.z(55)} {vin:rsc.z(54)} {vin:rsc.z(53)} {vin:rsc.z(52)} {vin:rsc.z(51)} {vin:rsc.z(50)} {vin:rsc.z(49)} {vin:rsc.z(48)} {vin:rsc.z(47)} {vin:rsc.z(46)} {vin:rsc.z(45)} {vin:rsc.z(44)} {vin:rsc.z(43)} {vin:rsc.z(42)} {vin:rsc.z(41)} {vin:rsc.z(40)} {vin:rsc.z(39)} {vin:rsc.z(38)} {vin:rsc.z(37)} {vin:rsc.z(36)} {vin:rsc.z(35)} {vin:rsc.z(34)} {vin:rsc.z(33)} {vin:rsc.z(32)} {vin:rsc.z(31)} {vin:rsc.z(30)} {vin:rsc.z(29)} {vin:rsc.z(28)} {vin:rsc.z(27)} {vin:rsc.z(26)} {vin:rsc.z(25)} {vin:rsc.z(24)} {vin:rsc.z(23)} {vin:rsc.z(22)} {vin:rsc.z(21)} {vin:rsc.z(20)} {vin:rsc.z(19)} {vin:rsc.z(18)} {vin:rsc.z(17)} {vin:rsc.z(16)} {vin:rsc.z(15)} {vin:rsc.z(14)} {vin:rsc.z(13)} {vin:rsc.z(12)} {vin:rsc.z(11)} {vin:rsc.z(10)} {vin:rsc.z(9)} {vin:rsc.z(8)} {vin:rsc.z(7)} {vin:rsc.z(6)} {vin:rsc.z(5)} {vin:rsc.z(4)} {vin:rsc.z(3)} {vin:rsc.z(2)} {vin:rsc.z(1)} {vin:rsc.z(0)} -attr xrf 12127 -attr oid 515 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load portBus {vout:rsc.z(29:0)} output 30 {vout:rsc.z(29)} {vout:rsc.z(28)} {vout:rsc.z(27)} {vout:rsc.z(26)} {vout:rsc.z(25)} {vout:rsc.z(24)} {vout:rsc.z(23)} {vout:rsc.z(22)} {vout:rsc.z(21)} {vout:rsc.z(20)} {vout:rsc.z(19)} {vout:rsc.z(18)} {vout:rsc.z(17)} {vout:rsc.z(16)} {vout:rsc.z(15)} {vout:rsc.z(14)} {vout:rsc.z(13)} {vout:rsc.z(12)} {vout:rsc.z(11)} {vout:rsc.z(10)} {vout:rsc.z(9)} {vout:rsc.z(8)} {vout:rsc.z(7)} {vout:rsc.z(6)} {vout:rsc.z(5)} {vout:rsc.z(4)} {vout:rsc.z(3)} {vout:rsc.z(2)} {vout:rsc.z(1)} {vout:rsc.z(0)} -attr xrf 12128 -attr oid 516 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load port {clk} input -attr xrf 12129 -attr oid 517 -attr vt d -attr @path {/sobel/clk}
+load port {en} input -attr xrf 12130 -attr oid 518 -attr vt d -attr @path {/sobel/en}
+load port {arst_n} input -attr xrf 12131 -attr oid 519 -attr vt d -attr @path {/sobel/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(89:0)} output 90 {d(89)} {d(88)} {d(87)} {d(86)} {d(85)} {d(84)} {d(83)} {d(82)} {d(81)} {d(80)} {d(79)} {d(78)} {d(77)} {d(76)} {d(75)} {d(74)} {d(73)} {d(72)} {d(71)} {d(70)} {d(69)} {d(68)} {d(67)} {d(66)} {d(65)} {d(64)} {d(63)} {d(62)} {d(61)} {d(60)} {d(59)} {d(58)} {d(57)} {d(56)} {d(55)} {d(54)} {d(53)} {d(52)} {d(51)} {d(50)} {d(49)} {d(48)} {d(47)} {d(46)} {d(45)} {d(44)} {d(43)} {d(42)} {d(41)} {d(40)} {d(39)} {d(38)} {d(37)} {d(36)} {d(35)} {d(34)} {d(33)} {d(32)} {d(31)} {d(30)} {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(89:0)} input 90 {z(89)} {z(88)} {z(87)} {z(86)} {z(85)} {z(84)} {z(83)} {z(82)} {z(81)} {z(80)} {z(79)} {z(78)} {z(77)} {z(76)} {z(75)} {z(74)} {z(73)} {z(72)} {z(71)} {z(70)} {z(69)} {z(68)} {z(67)} {z(66)} {z(65)} {z(64)} {z(63)} {z(62)} {z(61)} {z(60)} {z(59)} {z(58)} {z(57)} {z(56)} {z(55)} {z(54)} {z(53)} {z(52)} {z(51)} {z(50)} {z(49)} {z(48)} {z(47)} {z(46)} {z(45)} {z(44)} {z(43)} {z(42)} {z(41)} {z(40)} {z(39)} {z(38)} {z(37)} {z(36)} {z(35)} {z(34)} {z(33)} {z(32)} {z(31)} {z(30)} {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(29:0)} input 30 {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(29:0)} output 30 {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "sobel:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} \
+     portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} \
+
+load net {vin:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d#1} 90 {vin:rsc:mgc_in_wire.d#1(0)} {vin:rsc:mgc_in_wire.d#1(1)} {vin:rsc:mgc_in_wire.d#1(2)} {vin:rsc:mgc_in_wire.d#1(3)} {vin:rsc:mgc_in_wire.d#1(4)} {vin:rsc:mgc_in_wire.d#1(5)} {vin:rsc:mgc_in_wire.d#1(6)} {vin:rsc:mgc_in_wire.d#1(7)} {vin:rsc:mgc_in_wire.d#1(8)} {vin:rsc:mgc_in_wire.d#1(9)} {vin:rsc:mgc_in_wire.d#1(10)} {vin:rsc:mgc_in_wire.d#1(11)} {vin:rsc:mgc_in_wire.d#1(12)} {vin:rsc:mgc_in_wire.d#1(13)} {vin:rsc:mgc_in_wire.d#1(14)} {vin:rsc:mgc_in_wire.d#1(15)} {vin:rsc:mgc_in_wire.d#1(16)} {vin:rsc:mgc_in_wire.d#1(17)} {vin:rsc:mgc_in_wire.d#1(18)} {vin:rsc:mgc_in_wire.d#1(19)} {vin:rsc:mgc_in_wire.d#1(20)} {vin:rsc:mgc_in_wire.d#1(21)} {vin:rsc:mgc_in_wire.d#1(22)} {vin:rsc:mgc_in_wire.d#1(23)} {vin:rsc:mgc_in_wire.d#1(24)} {vin:rsc:mgc_in_wire.d#1(25)} {vin:rsc:mgc_in_wire.d#1(26)} {vin:rsc:mgc_in_wire.d#1(27)} {vin:rsc:mgc_in_wire.d#1(28)} {vin:rsc:mgc_in_wire.d#1(29)} {vin:rsc:mgc_in_wire.d#1(30)} {vin:rsc:mgc_in_wire.d#1(31)} {vin:rsc:mgc_in_wire.d#1(32)} {vin:rsc:mgc_in_wire.d#1(33)} {vin:rsc:mgc_in_wire.d#1(34)} {vin:rsc:mgc_in_wire.d#1(35)} {vin:rsc:mgc_in_wire.d#1(36)} {vin:rsc:mgc_in_wire.d#1(37)} {vin:rsc:mgc_in_wire.d#1(38)} {vin:rsc:mgc_in_wire.d#1(39)} {vin:rsc:mgc_in_wire.d#1(40)} {vin:rsc:mgc_in_wire.d#1(41)} {vin:rsc:mgc_in_wire.d#1(42)} {vin:rsc:mgc_in_wire.d#1(43)} {vin:rsc:mgc_in_wire.d#1(44)} {vin:rsc:mgc_in_wire.d#1(45)} {vin:rsc:mgc_in_wire.d#1(46)} {vin:rsc:mgc_in_wire.d#1(47)} {vin:rsc:mgc_in_wire.d#1(48)} {vin:rsc:mgc_in_wire.d#1(49)} {vin:rsc:mgc_in_wire.d#1(50)} {vin:rsc:mgc_in_wire.d#1(51)} {vin:rsc:mgc_in_wire.d#1(52)} {vin:rsc:mgc_in_wire.d#1(53)} {vin:rsc:mgc_in_wire.d#1(54)} {vin:rsc:mgc_in_wire.d#1(55)} {vin:rsc:mgc_in_wire.d#1(56)} {vin:rsc:mgc_in_wire.d#1(57)} {vin:rsc:mgc_in_wire.d#1(58)} {vin:rsc:mgc_in_wire.d#1(59)} {vin:rsc:mgc_in_wire.d#1(60)} {vin:rsc:mgc_in_wire.d#1(61)} {vin:rsc:mgc_in_wire.d#1(62)} {vin:rsc:mgc_in_wire.d#1(63)} {vin:rsc:mgc_in_wire.d#1(64)} {vin:rsc:mgc_in_wire.d#1(65)} {vin:rsc:mgc_in_wire.d#1(66)} {vin:rsc:mgc_in_wire.d#1(67)} {vin:rsc:mgc_in_wire.d#1(68)} {vin:rsc:mgc_in_wire.d#1(69)} {vin:rsc:mgc_in_wire.d#1(70)} {vin:rsc:mgc_in_wire.d#1(71)} {vin:rsc:mgc_in_wire.d#1(72)} {vin:rsc:mgc_in_wire.d#1(73)} {vin:rsc:mgc_in_wire.d#1(74)} {vin:rsc:mgc_in_wire.d#1(75)} {vin:rsc:mgc_in_wire.d#1(76)} {vin:rsc:mgc_in_wire.d#1(77)} {vin:rsc:mgc_in_wire.d#1(78)} {vin:rsc:mgc_in_wire.d#1(79)} {vin:rsc:mgc_in_wire.d#1(80)} {vin:rsc:mgc_in_wire.d#1(81)} {vin:rsc:mgc_in_wire.d#1(82)} {vin:rsc:mgc_in_wire.d#1(83)} {vin:rsc:mgc_in_wire.d#1(84)} {vin:rsc:mgc_in_wire.d#1(85)} {vin:rsc:mgc_in_wire.d#1(86)} {vin:rsc:mgc_in_wire.d#1(87)} {vin:rsc:mgc_in_wire.d#1(88)} {vin:rsc:mgc_in_wire.d#1(89)} -attr xrf 12132 -attr oid 520 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d#1} 30 {vout:rsc:mgc_out_stdreg.d#1(0)} {vout:rsc:mgc_out_stdreg.d#1(1)} {vout:rsc:mgc_out_stdreg.d#1(2)} {vout:rsc:mgc_out_stdreg.d#1(3)} {vout:rsc:mgc_out_stdreg.d#1(4)} {vout:rsc:mgc_out_stdreg.d#1(5)} {vout:rsc:mgc_out_stdreg.d#1(6)} {vout:rsc:mgc_out_stdreg.d#1(7)} {vout:rsc:mgc_out_stdreg.d#1(8)} {vout:rsc:mgc_out_stdreg.d#1(9)} {vout:rsc:mgc_out_stdreg.d#1(10)} {vout:rsc:mgc_out_stdreg.d#1(11)} {vout:rsc:mgc_out_stdreg.d#1(12)} {vout:rsc:mgc_out_stdreg.d#1(13)} {vout:rsc:mgc_out_stdreg.d#1(14)} {vout:rsc:mgc_out_stdreg.d#1(15)} {vout:rsc:mgc_out_stdreg.d#1(16)} {vout:rsc:mgc_out_stdreg.d#1(17)} {vout:rsc:mgc_out_stdreg.d#1(18)} {vout:rsc:mgc_out_stdreg.d#1(19)} {vout:rsc:mgc_out_stdreg.d#1(20)} {vout:rsc:mgc_out_stdreg.d#1(21)} {vout:rsc:mgc_out_stdreg.d#1(22)} {vout:rsc:mgc_out_stdreg.d#1(23)} {vout:rsc:mgc_out_stdreg.d#1(24)} {vout:rsc:mgc_out_stdreg.d#1(25)} {vout:rsc:mgc_out_stdreg.d#1(26)} {vout:rsc:mgc_out_stdreg.d#1(27)} {vout:rsc:mgc_out_stdreg.d#1(28)} {vout:rsc:mgc_out_stdreg.d#1(29)} -attr xrf 12133 -attr oid 521 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -attr vt d
+load net {vin:rsc.z(13)} -attr vt d
+load net {vin:rsc.z(14)} -attr vt d
+load net {vin:rsc.z(15)} -attr vt d
+load net {vin:rsc.z(16)} -attr vt d
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+load net {vin:rsc.z(22)} -attr vt d
+load net {vin:rsc.z(23)} -attr vt d
+load net {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -attr vt d
+load net {vin:rsc.z(28)} -attr vt d
+load net {vin:rsc.z(29)} -attr vt d
+load net {vin:rsc.z(30)} -attr vt d
+load net {vin:rsc.z(31)} -attr vt d
+load net {vin:rsc.z(32)} -attr vt d
+load net {vin:rsc.z(33)} -attr vt d
+load net {vin:rsc.z(34)} -attr vt d
+load net {vin:rsc.z(35)} -attr vt d
+load net {vin:rsc.z(36)} -attr vt d
+load net {vin:rsc.z(37)} -attr vt d
+load net {vin:rsc.z(38)} -attr vt d
+load net {vin:rsc.z(39)} -attr vt d
+load net {vin:rsc.z(40)} -attr vt d
+load net {vin:rsc.z(41)} -attr vt d
+load net {vin:rsc.z(42)} -attr vt d
+load net {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -attr vt d
+load net {vin:rsc.z(45)} -attr vt d
+load net {vin:rsc.z(46)} -attr vt d
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+load net {vin:rsc.z(48)} -attr vt d
+load net {vin:rsc.z(49)} -attr vt d
+load net {vin:rsc.z(50)} -attr vt d
+load net {vin:rsc.z(51)} -attr vt d
+load net {vin:rsc.z(52)} -attr vt d
+load net {vin:rsc.z(53)} -attr vt d
+load net {vin:rsc.z(54)} -attr vt d
+load net {vin:rsc.z(55)} -attr vt d
+load net {vin:rsc.z(56)} -attr vt d
+load net {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -attr vt d
+load net {vin:rsc.z(63)} -attr vt d
+load net {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -attr vt d
+load net {vin:rsc.z(68)} -attr vt d
+load net {vin:rsc.z(69)} -attr vt d
+load net {vin:rsc.z(70)} -attr vt d
+load net {vin:rsc.z(71)} -attr vt d
+load net {vin:rsc.z(72)} -attr vt d
+load net {vin:rsc.z(73)} -attr vt d
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+load net {vin:rsc.z(75)} -attr vt d
+load net {vin:rsc.z(76)} -attr vt d
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+load net {vin:rsc.z(85)} -attr vt d
+load net {vin:rsc.z(86)} -attr vt d
+load net {vin:rsc.z(87)} -attr vt d
+load net {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 12134 -attr oid 522 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(0)} -port {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -port {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -port {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -port {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -port {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -port {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -port {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -port {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -port {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -port {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -port {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -port {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -port {vin:rsc.z(12)} -attr vt d
+load net {vin:rsc.z(13)} -port {vin:rsc.z(13)} -attr vt d
+load net {vin:rsc.z(14)} -port {vin:rsc.z(14)} -attr vt d
+load net {vin:rsc.z(15)} -port {vin:rsc.z(15)} -attr vt d
+load net {vin:rsc.z(16)} -port {vin:rsc.z(16)} -attr vt d
+load net {vin:rsc.z(17)} -port {vin:rsc.z(17)} -attr vt d
+load net {vin:rsc.z(18)} -port {vin:rsc.z(18)} -attr vt d
+load net {vin:rsc.z(19)} -port {vin:rsc.z(19)} -attr vt d
+load net {vin:rsc.z(20)} -port {vin:rsc.z(20)} -attr vt d
+load net {vin:rsc.z(21)} -port {vin:rsc.z(21)} -attr vt d
+load net {vin:rsc.z(22)} -port {vin:rsc.z(22)} -attr vt d
+load net {vin:rsc.z(23)} -port {vin:rsc.z(23)} -attr vt d
+load net {vin:rsc.z(24)} -port {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -port {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -port {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -port {vin:rsc.z(27)} -attr vt d
+load net {vin:rsc.z(28)} -port {vin:rsc.z(28)} -attr vt d
+load net {vin:rsc.z(29)} -port {vin:rsc.z(29)} -attr vt d
+load net {vin:rsc.z(30)} -port {vin:rsc.z(30)} -attr vt d
+load net {vin:rsc.z(31)} -port {vin:rsc.z(31)} -attr vt d
+load net {vin:rsc.z(32)} -port {vin:rsc.z(32)} -attr vt d
+load net {vin:rsc.z(33)} -port {vin:rsc.z(33)} -attr vt d
+load net {vin:rsc.z(34)} -port {vin:rsc.z(34)} -attr vt d
+load net {vin:rsc.z(35)} -port {vin:rsc.z(35)} -attr vt d
+load net {vin:rsc.z(36)} -port {vin:rsc.z(36)} -attr vt d
+load net {vin:rsc.z(37)} -port {vin:rsc.z(37)} -attr vt d
+load net {vin:rsc.z(38)} -port {vin:rsc.z(38)} -attr vt d
+load net {vin:rsc.z(39)} -port {vin:rsc.z(39)} -attr vt d
+load net {vin:rsc.z(40)} -port {vin:rsc.z(40)} -attr vt d
+load net {vin:rsc.z(41)} -port {vin:rsc.z(41)} -attr vt d
+load net {vin:rsc.z(42)} -port {vin:rsc.z(42)} -attr vt d
+load net {vin:rsc.z(43)} -port {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -port {vin:rsc.z(44)} -attr vt d
+load net {vin:rsc.z(45)} -port {vin:rsc.z(45)} -attr vt d
+load net {vin:rsc.z(46)} -port {vin:rsc.z(46)} -attr vt d
+load net {vin:rsc.z(47)} -port {vin:rsc.z(47)} -attr vt d
+load net {vin:rsc.z(48)} -port {vin:rsc.z(48)} -attr vt d
+load net {vin:rsc.z(49)} -port {vin:rsc.z(49)} -attr vt d
+load net {vin:rsc.z(50)} -port {vin:rsc.z(50)} -attr vt d
+load net {vin:rsc.z(51)} -port {vin:rsc.z(51)} -attr vt d
+load net {vin:rsc.z(52)} -port {vin:rsc.z(52)} -attr vt d
+load net {vin:rsc.z(53)} -port {vin:rsc.z(53)} -attr vt d
+load net {vin:rsc.z(54)} -port {vin:rsc.z(54)} -attr vt d
+load net {vin:rsc.z(55)} -port {vin:rsc.z(55)} -attr vt d
+load net {vin:rsc.z(56)} -port {vin:rsc.z(56)} -attr vt d
+load net {vin:rsc.z(57)} -port {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -port {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -port {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -port {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -port {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -port {vin:rsc.z(62)} -attr vt d
+load net {vin:rsc.z(63)} -port {vin:rsc.z(63)} -attr vt d
+load net {vin:rsc.z(64)} -port {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -port {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -port {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -port {vin:rsc.z(67)} -attr vt d
+load net {vin:rsc.z(68)} -port {vin:rsc.z(68)} -attr vt d
+load net {vin:rsc.z(69)} -port {vin:rsc.z(69)} -attr vt d
+load net {vin:rsc.z(70)} -port {vin:rsc.z(70)} -attr vt d
+load net {vin:rsc.z(71)} -port {vin:rsc.z(71)} -attr vt d
+load net {vin:rsc.z(72)} -port {vin:rsc.z(72)} -attr vt d
+load net {vin:rsc.z(73)} -port {vin:rsc.z(73)} -attr vt d
+load net {vin:rsc.z(74)} -port {vin:rsc.z(74)} -attr vt d
+load net {vin:rsc.z(75)} -port {vin:rsc.z(75)} -attr vt d
+load net {vin:rsc.z(76)} -port {vin:rsc.z(76)} -attr vt d
+load net {vin:rsc.z(77)} -port {vin:rsc.z(77)} -attr vt d
+load net {vin:rsc.z(78)} -port {vin:rsc.z(78)} -attr vt d
+load net {vin:rsc.z(79)} -port {vin:rsc.z(79)} -attr vt d
+load net {vin:rsc.z(80)} -port {vin:rsc.z(80)} -attr vt d
+load net {vin:rsc.z(81)} -port {vin:rsc.z(81)} -attr vt d
+load net {vin:rsc.z(82)} -port {vin:rsc.z(82)} -attr vt d
+load net {vin:rsc.z(83)} -port {vin:rsc.z(83)} -attr vt d
+load net {vin:rsc.z(84)} -port {vin:rsc.z(84)} -attr vt d
+load net {vin:rsc.z(85)} -port {vin:rsc.z(85)} -attr vt d
+load net {vin:rsc.z(86)} -port {vin:rsc.z(86)} -attr vt d
+load net {vin:rsc.z(87)} -port {vin:rsc.z(87)} -attr vt d
+load net {vin:rsc.z(88)} -port {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -port {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 12135 -attr oid 523 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vout:rsc.z(0)} -attr vt d
+load net {vout:rsc.z(1)} -attr vt d
+load net {vout:rsc.z(2)} -attr vt d
+load net {vout:rsc.z(3)} -attr vt d
+load net {vout:rsc.z(4)} -attr vt d
+load net {vout:rsc.z(5)} -attr vt d
+load net {vout:rsc.z(6)} -attr vt d
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+load net {vout:rsc.z(9)} -attr vt d
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+load net {vout:rsc.z(11)} -attr vt d
+load net {vout:rsc.z(12)} -attr vt d
+load net {vout:rsc.z(13)} -attr vt d
+load net {vout:rsc.z(14)} -attr vt d
+load net {vout:rsc.z(15)} -attr vt d
+load net {vout:rsc.z(16)} -attr vt d
+load net {vout:rsc.z(17)} -attr vt d
+load net {vout:rsc.z(18)} -attr vt d
+load net {vout:rsc.z(19)} -attr vt d
+load net {vout:rsc.z(20)} -attr vt d
+load net {vout:rsc.z(21)} -attr vt d
+load net {vout:rsc.z(22)} -attr vt d
+load net {vout:rsc.z(23)} -attr vt d
+load net {vout:rsc.z(24)} -attr vt d
+load net {vout:rsc.z(25)} -attr vt d
+load net {vout:rsc.z(26)} -attr vt d
+load net {vout:rsc.z(27)} -attr vt d
+load net {vout:rsc.z(28)} -attr vt d
+load net {vout:rsc.z(29)} -attr vt d
+load netBundle {vout:rsc.z} 30 {vout:rsc.z(0)} {vout:rsc.z(1)} {vout:rsc.z(2)} {vout:rsc.z(3)} {vout:rsc.z(4)} {vout:rsc.z(5)} {vout:rsc.z(6)} {vout:rsc.z(7)} {vout:rsc.z(8)} {vout:rsc.z(9)} {vout:rsc.z(10)} {vout:rsc.z(11)} {vout:rsc.z(12)} {vout:rsc.z(13)} {vout:rsc.z(14)} {vout:rsc.z(15)} {vout:rsc.z(16)} {vout:rsc.z(17)} {vout:rsc.z(18)} {vout:rsc.z(19)} {vout:rsc.z(20)} {vout:rsc.z(21)} {vout:rsc.z(22)} {vout:rsc.z(23)} {vout:rsc.z(24)} {vout:rsc.z(25)} {vout:rsc.z(26)} {vout:rsc.z(27)} {vout:rsc.z(28)} {vout:rsc.z(29)} -attr xrf 12136 -attr oid 524 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(0)} -port {vout:rsc.z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -port {vout:rsc.z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -port {vout:rsc.z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -port {vout:rsc.z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -port {vout:rsc.z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -port {vout:rsc.z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -port {vout:rsc.z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -port {vout:rsc.z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -port {vout:rsc.z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -port {vout:rsc.z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -port {vout:rsc.z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -port {vout:rsc.z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -port {vout:rsc.z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -port {vout:rsc.z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -port {vout:rsc.z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -port {vout:rsc.z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -port {vout:rsc.z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -port {vout:rsc.z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -port {vout:rsc.z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -port {vout:rsc.z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -port {vout:rsc.z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -port {vout:rsc.z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -port {vout:rsc.z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -port {vout:rsc.z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -port {vout:rsc.z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -port {vout:rsc.z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -port {vout:rsc.z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -port {vout:rsc.z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -port {vout:rsc.z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -port {vout:rsc.z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {clk} -attr xrf 12137 -attr oid 525
+load net {clk} -port {clk} -attr xrf 12138 -attr oid 526
+load net {en} -attr xrf 12139 -attr oid 527
+load net {en} -port {en} -attr xrf 12140 -attr oid 528
+load net {arst_n} -attr xrf 12141 -attr oid 529
+load net {arst_n} -port {arst_n} -attr xrf 12142 -attr oid 530
+load inst "sobel:core:inst" "sobel:core" "orig" -attr xrf 12143 -attr oid 531 -attr vt dc -attr @path {/sobel/sobel:core:inst} -attr area 5138.342405 -attr delay 16.524269 -attr hier "/sobel/sobel:core" -pg 1 -lvl 3
+load net {clk} -pin  "sobel:core:inst" {clk#1} -attr xrf 12144 -attr oid 532 -attr @path {/sobel/clk}
+load net {en} -pin  "sobel:core:inst" {en#1} -attr xrf 12145 -attr oid 533 -attr @path {/sobel/en}
+load net {arst_n} -pin  "sobel:core:inst" {arst_n#1} -attr xrf 12146 -attr oid 534 -attr @path {/sobel/arst_n}
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(8)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(9)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(10)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(11)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(12)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(13)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(14)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(15)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(16)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(17)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(18)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(19)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(20)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(21)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(22)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(23)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(24)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(25)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(26)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(27)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(28)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(29)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(30)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(31)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(32)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(33)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(34)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(35)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(36)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(37)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(38)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(39)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(40)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(41)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(42)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(43)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(44)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(45)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(46)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(47)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(48)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(49)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(50)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(51)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(52)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(53)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(54)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(55)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(56)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(57)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(58)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(59)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(60)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(61)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(62)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(63)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(64)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(65)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(66)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(67)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(68)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(69)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(70)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(71)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(72)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(73)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(74)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(75)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(76)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(77)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(78)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(79)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(80)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(81)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(82)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(83)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(84)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(85)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(86)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(87)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(88)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(89)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(8)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(9)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(10)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(11)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(12)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(13)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(14)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(15)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(16)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(17)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(18)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(19)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(20)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(21)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(22)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(23)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(24)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(25)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(26)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(27)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(28)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(29)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load inst "vin:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" -attr xrf 12147 -attr oid 535 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,90)" -pg 1 -lvl 1
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "vin:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "vin:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "vin:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "vin:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "vin:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "vin:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "vin:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "vin:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "vin:rsc:mgc_in_wire" {d(8)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "vin:rsc:mgc_in_wire" {d(9)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "vin:rsc:mgc_in_wire" {d(10)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "vin:rsc:mgc_in_wire" {d(11)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "vin:rsc:mgc_in_wire" {d(12)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "vin:rsc:mgc_in_wire" {d(13)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "vin:rsc:mgc_in_wire" {d(14)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "vin:rsc:mgc_in_wire" {d(15)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "vin:rsc:mgc_in_wire" {d(16)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "vin:rsc:mgc_in_wire" {d(17)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "vin:rsc:mgc_in_wire" {d(18)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "vin:rsc:mgc_in_wire" {d(19)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "vin:rsc:mgc_in_wire" {d(20)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "vin:rsc:mgc_in_wire" {d(21)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "vin:rsc:mgc_in_wire" {d(22)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "vin:rsc:mgc_in_wire" {d(23)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "vin:rsc:mgc_in_wire" {d(24)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "vin:rsc:mgc_in_wire" {d(25)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "vin:rsc:mgc_in_wire" {d(26)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "vin:rsc:mgc_in_wire" {d(27)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "vin:rsc:mgc_in_wire" {d(28)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "vin:rsc:mgc_in_wire" {d(29)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "vin:rsc:mgc_in_wire" {d(30)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "vin:rsc:mgc_in_wire" {d(31)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "vin:rsc:mgc_in_wire" {d(32)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "vin:rsc:mgc_in_wire" {d(33)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "vin:rsc:mgc_in_wire" {d(34)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "vin:rsc:mgc_in_wire" {d(35)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "vin:rsc:mgc_in_wire" {d(36)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "vin:rsc:mgc_in_wire" {d(37)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "vin:rsc:mgc_in_wire" {d(38)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "vin:rsc:mgc_in_wire" {d(39)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "vin:rsc:mgc_in_wire" {d(40)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "vin:rsc:mgc_in_wire" {d(41)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "vin:rsc:mgc_in_wire" {d(42)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "vin:rsc:mgc_in_wire" {d(43)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "vin:rsc:mgc_in_wire" {d(44)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "vin:rsc:mgc_in_wire" {d(45)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "vin:rsc:mgc_in_wire" {d(46)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "vin:rsc:mgc_in_wire" {d(47)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "vin:rsc:mgc_in_wire" {d(48)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "vin:rsc:mgc_in_wire" {d(49)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "vin:rsc:mgc_in_wire" {d(50)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "vin:rsc:mgc_in_wire" {d(51)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "vin:rsc:mgc_in_wire" {d(52)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "vin:rsc:mgc_in_wire" {d(53)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "vin:rsc:mgc_in_wire" {d(54)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "vin:rsc:mgc_in_wire" {d(55)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "vin:rsc:mgc_in_wire" {d(56)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "vin:rsc:mgc_in_wire" {d(57)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "vin:rsc:mgc_in_wire" {d(58)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "vin:rsc:mgc_in_wire" {d(59)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "vin:rsc:mgc_in_wire" {d(60)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "vin:rsc:mgc_in_wire" {d(61)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "vin:rsc:mgc_in_wire" {d(62)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "vin:rsc:mgc_in_wire" {d(63)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "vin:rsc:mgc_in_wire" {d(64)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "vin:rsc:mgc_in_wire" {d(65)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "vin:rsc:mgc_in_wire" {d(66)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "vin:rsc:mgc_in_wire" {d(67)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "vin:rsc:mgc_in_wire" {d(68)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "vin:rsc:mgc_in_wire" {d(69)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "vin:rsc:mgc_in_wire" {d(70)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "vin:rsc:mgc_in_wire" {d(71)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "vin:rsc:mgc_in_wire" {d(72)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "vin:rsc:mgc_in_wire" {d(73)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "vin:rsc:mgc_in_wire" {d(74)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "vin:rsc:mgc_in_wire" {d(75)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "vin:rsc:mgc_in_wire" {d(76)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "vin:rsc:mgc_in_wire" {d(77)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "vin:rsc:mgc_in_wire" {d(78)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "vin:rsc:mgc_in_wire" {d(79)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "vin:rsc:mgc_in_wire" {d(80)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "vin:rsc:mgc_in_wire" {d(81)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "vin:rsc:mgc_in_wire" {d(82)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "vin:rsc:mgc_in_wire" {d(83)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "vin:rsc:mgc_in_wire" {d(84)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "vin:rsc:mgc_in_wire" {d(85)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "vin:rsc:mgc_in_wire" {d(86)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "vin:rsc:mgc_in_wire" {d(87)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "vin:rsc:mgc_in_wire" {d(88)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "vin:rsc:mgc_in_wire" {d(89)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc.z(0)} -pin  "vin:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(1)} -pin  "vin:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(2)} -pin  "vin:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(3)} -pin  "vin:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(4)} -pin  "vin:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(5)} -pin  "vin:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(6)} -pin  "vin:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(7)} -pin  "vin:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(8)} -pin  "vin:rsc:mgc_in_wire" {z(8)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(9)} -pin  "vin:rsc:mgc_in_wire" {z(9)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(10)} -pin  "vin:rsc:mgc_in_wire" {z(10)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(11)} -pin  "vin:rsc:mgc_in_wire" {z(11)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(12)} -pin  "vin:rsc:mgc_in_wire" {z(12)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(13)} -pin  "vin:rsc:mgc_in_wire" {z(13)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(14)} -pin  "vin:rsc:mgc_in_wire" {z(14)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(15)} -pin  "vin:rsc:mgc_in_wire" {z(15)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(16)} -pin  "vin:rsc:mgc_in_wire" {z(16)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(17)} -pin  "vin:rsc:mgc_in_wire" {z(17)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(18)} -pin  "vin:rsc:mgc_in_wire" {z(18)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(19)} -pin  "vin:rsc:mgc_in_wire" {z(19)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(20)} -pin  "vin:rsc:mgc_in_wire" {z(20)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(21)} -pin  "vin:rsc:mgc_in_wire" {z(21)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(22)} -pin  "vin:rsc:mgc_in_wire" {z(22)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(23)} -pin  "vin:rsc:mgc_in_wire" {z(23)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(24)} -pin  "vin:rsc:mgc_in_wire" {z(24)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(25)} -pin  "vin:rsc:mgc_in_wire" {z(25)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(26)} -pin  "vin:rsc:mgc_in_wire" {z(26)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(27)} -pin  "vin:rsc:mgc_in_wire" {z(27)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(28)} -pin  "vin:rsc:mgc_in_wire" {z(28)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(29)} -pin  "vin:rsc:mgc_in_wire" {z(29)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(30)} -pin  "vin:rsc:mgc_in_wire" {z(30)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(31)} -pin  "vin:rsc:mgc_in_wire" {z(31)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(32)} -pin  "vin:rsc:mgc_in_wire" {z(32)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(33)} -pin  "vin:rsc:mgc_in_wire" {z(33)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(34)} -pin  "vin:rsc:mgc_in_wire" {z(34)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(35)} -pin  "vin:rsc:mgc_in_wire" {z(35)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(36)} -pin  "vin:rsc:mgc_in_wire" {z(36)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(37)} -pin  "vin:rsc:mgc_in_wire" {z(37)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(38)} -pin  "vin:rsc:mgc_in_wire" {z(38)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(39)} -pin  "vin:rsc:mgc_in_wire" {z(39)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(40)} -pin  "vin:rsc:mgc_in_wire" {z(40)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(41)} -pin  "vin:rsc:mgc_in_wire" {z(41)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(42)} -pin  "vin:rsc:mgc_in_wire" {z(42)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(43)} -pin  "vin:rsc:mgc_in_wire" {z(43)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(44)} -pin  "vin:rsc:mgc_in_wire" {z(44)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(45)} -pin  "vin:rsc:mgc_in_wire" {z(45)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(46)} -pin  "vin:rsc:mgc_in_wire" {z(46)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(47)} -pin  "vin:rsc:mgc_in_wire" {z(47)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(48)} -pin  "vin:rsc:mgc_in_wire" {z(48)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(49)} -pin  "vin:rsc:mgc_in_wire" {z(49)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(50)} -pin  "vin:rsc:mgc_in_wire" {z(50)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(51)} -pin  "vin:rsc:mgc_in_wire" {z(51)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(52)} -pin  "vin:rsc:mgc_in_wire" {z(52)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(53)} -pin  "vin:rsc:mgc_in_wire" {z(53)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(54)} -pin  "vin:rsc:mgc_in_wire" {z(54)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(55)} -pin  "vin:rsc:mgc_in_wire" {z(55)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(56)} -pin  "vin:rsc:mgc_in_wire" {z(56)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(57)} -pin  "vin:rsc:mgc_in_wire" {z(57)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(58)} -pin  "vin:rsc:mgc_in_wire" {z(58)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(59)} -pin  "vin:rsc:mgc_in_wire" {z(59)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(60)} -pin  "vin:rsc:mgc_in_wire" {z(60)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(61)} -pin  "vin:rsc:mgc_in_wire" {z(61)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(62)} -pin  "vin:rsc:mgc_in_wire" {z(62)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(63)} -pin  "vin:rsc:mgc_in_wire" {z(63)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(64)} -pin  "vin:rsc:mgc_in_wire" {z(64)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(65)} -pin  "vin:rsc:mgc_in_wire" {z(65)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(66)} -pin  "vin:rsc:mgc_in_wire" {z(66)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(67)} -pin  "vin:rsc:mgc_in_wire" {z(67)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(68)} -pin  "vin:rsc:mgc_in_wire" {z(68)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(69)} -pin  "vin:rsc:mgc_in_wire" {z(69)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(70)} -pin  "vin:rsc:mgc_in_wire" {z(70)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(71)} -pin  "vin:rsc:mgc_in_wire" {z(71)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(72)} -pin  "vin:rsc:mgc_in_wire" {z(72)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(73)} -pin  "vin:rsc:mgc_in_wire" {z(73)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(74)} -pin  "vin:rsc:mgc_in_wire" {z(74)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(75)} -pin  "vin:rsc:mgc_in_wire" {z(75)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(76)} -pin  "vin:rsc:mgc_in_wire" {z(76)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(77)} -pin  "vin:rsc:mgc_in_wire" {z(77)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(78)} -pin  "vin:rsc:mgc_in_wire" {z(78)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(79)} -pin  "vin:rsc:mgc_in_wire" {z(79)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(80)} -pin  "vin:rsc:mgc_in_wire" {z(80)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(81)} -pin  "vin:rsc:mgc_in_wire" {z(81)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(82)} -pin  "vin:rsc:mgc_in_wire" {z(82)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(83)} -pin  "vin:rsc:mgc_in_wire" {z(83)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(84)} -pin  "vin:rsc:mgc_in_wire" {z(84)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(85)} -pin  "vin:rsc:mgc_in_wire" {z(85)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(86)} -pin  "vin:rsc:mgc_in_wire" {z(86)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(87)} -pin  "vin:rsc:mgc_in_wire" {z(87)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(88)} -pin  "vin:rsc:mgc_in_wire" {z(88)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(89)} -pin  "vin:rsc:mgc_in_wire" {z(89)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load inst "vout:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" -attr xrf 12148 -attr oid 536 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(2,30)" -pg 1 -lvl 1002
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "vout:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "vout:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "vout:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "vout:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "vout:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "vout:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "vout:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "vout:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "vout:rsc:mgc_out_stdreg" {d(8)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "vout:rsc:mgc_out_stdreg" {d(9)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "vout:rsc:mgc_out_stdreg" {d(10)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "vout:rsc:mgc_out_stdreg" {d(11)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "vout:rsc:mgc_out_stdreg" {d(12)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "vout:rsc:mgc_out_stdreg" {d(13)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "vout:rsc:mgc_out_stdreg" {d(14)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "vout:rsc:mgc_out_stdreg" {d(15)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "vout:rsc:mgc_out_stdreg" {d(16)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "vout:rsc:mgc_out_stdreg" {d(17)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "vout:rsc:mgc_out_stdreg" {d(18)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "vout:rsc:mgc_out_stdreg" {d(19)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "vout:rsc:mgc_out_stdreg" {d(20)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "vout:rsc:mgc_out_stdreg" {d(21)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "vout:rsc:mgc_out_stdreg" {d(22)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "vout:rsc:mgc_out_stdreg" {d(23)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "vout:rsc:mgc_out_stdreg" {d(24)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "vout:rsc:mgc_out_stdreg" {d(25)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "vout:rsc:mgc_out_stdreg" {d(26)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "vout:rsc:mgc_out_stdreg" {d(27)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "vout:rsc:mgc_out_stdreg" {d(28)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "vout:rsc:mgc_out_stdreg" {d(29)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc.z(0)} -pin  "vout:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -pin  "vout:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -pin  "vout:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -pin  "vout:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -pin  "vout:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -pin  "vout:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -pin  "vout:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -pin  "vout:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -pin  "vout:rsc:mgc_out_stdreg" {z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -pin  "vout:rsc:mgc_out_stdreg" {z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -pin  "vout:rsc:mgc_out_stdreg" {z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -pin  "vout:rsc:mgc_out_stdreg" {z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -pin  "vout:rsc:mgc_out_stdreg" {z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -pin  "vout:rsc:mgc_out_stdreg" {z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -pin  "vout:rsc:mgc_out_stdreg" {z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -pin  "vout:rsc:mgc_out_stdreg" {z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -pin  "vout:rsc:mgc_out_stdreg" {z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -pin  "vout:rsc:mgc_out_stdreg" {z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -pin  "vout:rsc:mgc_out_stdreg" {z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -pin  "vout:rsc:mgc_out_stdreg" {z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -pin  "vout:rsc:mgc_out_stdreg" {z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -pin  "vout:rsc:mgc_out_stdreg" {z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -pin  "vout:rsc:mgc_out_stdreg" {z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -pin  "vout:rsc:mgc_out_stdreg" {z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -pin  "vout:rsc:mgc_out_stdreg" {z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -pin  "vout:rsc:mgc_out_stdreg" {z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -pin  "vout:rsc:mgc_out_stdreg" {z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -pin  "vout:rsc:mgc_out_stdreg" {z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -pin  "vout:rsc:mgc_out_stdreg" {z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -pin  "vout:rsc:mgc_out_stdreg" {z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+### END MODULE 
+
diff --git a/Sobel/sobel.v5/concat_rtl.v b/Sobel/sobel.v5/concat_rtl.v
new file mode 100644
index 0000000..3d4fb59
--- /dev/null
+++ b/Sobel/sobel.v5/concat_rtl.v
@@ -0,0 +1,1700 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:36:28 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [29:0] regs_regs_1_1_sva;
+  reg [29:0] regs_regs_1_sg2_sva;
+  reg [9:0] ACC1_slc_regs_regs_2_sg2_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_sg2_1_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_sg2_2_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_1_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_1_1_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_1_2_itm;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  wire [10:0] nl_reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  reg [5:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_2;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_3;
+  wire [9:0] FRAME_acc_22_cse;
+  wire [10:0] nl_FRAME_acc_22_cse;
+  wire [10:0] FRAME_acc_5_psp_sva;
+  wire [11:0] nl_FRAME_acc_5_psp_sva;
+  wire [6:0] acc_imod_sva;
+  wire [8:0] nl_acc_imod_sva;
+  wire [13:0] ACC1_acc_itm;
+  wire [14:0] nl_ACC1_acc_itm;
+  wire [7:0] FRAME_acc_33_itm;
+  wire [8:0] nl_FRAME_acc_33_itm;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign vout_rsc_mgc_out_stdreg_d = {reg_vout_rsc_mgc_out_stdreg_d_tmp , (reg_vout_rsc_mgc_out_stdreg_d_tmp_3[9:6])
+      , reg_vout_rsc_mgc_out_stdreg_d_tmp_2 , reg_vout_rsc_mgc_out_stdreg_d_tmp_3};
+  assign nl_ACC1_acc_itm = conv_s2s_13_14(conv_s2s_12_13(conv_s2s_11_12(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[79:70])
+      + conv_s2s_10_11(vin_rsc_mgc_in_wire_d[89:80])) + conv_s2s_11_12(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_sg2_itm
+      , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_sg2_1_itm , 1'b1}))))) + conv_s2s_12_13(conv_s2s_11_12(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_sg2_2_itm
+      , 1'b1}) + conv_s2s_11_12({(~ ACC1_slc_regs_regs_2_1_itm) , 1'b1})))) + conv_s2s_11_12(readslicef_12_11_1((conv_s2s_11_12({(~
+      ACC1_slc_regs_regs_2_1_1_itm) , 1'b1}) + conv_s2s_11_12({(~ ACC1_slc_regs_regs_2_1_2_itm)
+      , 1'b1})))))) + conv_s2s_12_14(conv_s2s_11_12(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[9:0])
+      + conv_s2s_10_11(vin_rsc_mgc_in_wire_d[19:10])) + conv_s2s_11_12(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[29:20])
+      + conv_s2s_10_11(vin_rsc_mgc_in_wire_d[69:60])));
+  assign ACC1_acc_itm = nl_ACC1_acc_itm[13:0];
+  assign nl_FRAME_acc_22_cse = conv_u2s_9_11(conv_u2s_18_10(conv_u2u_4_9(ACC1_acc_itm[13:10])
+      * 9'b10011)) + conv_s2s_6_10(conv_s2s_4_6(conv_u2s_3_4(conv_u2u_2_3(conv_u2u_1_2(ACC1_acc_itm[5])
+      + conv_u2u_1_2(acc_imod_sva[4])) + conv_u2u_2_3(ACC1_acc_itm[9:8])) + conv_s2s_3_4(conv_s2s_2_3(acc_imod_sva[6:5])
+      + conv_s2s_1_3(readslicef_5_1_4(((({(acc_imod_sva[4]) , 1'b0 , (acc_imod_sva[4])
+      , 1'b0 , (acc_imod_sva[4])}) + conv_u2s_4_5(acc_imod_sva[3:0])) + ({(conv_s2u_2_3(acc_imod_sva[6:5])
+      + conv_s2u_1_3(acc_imod_sva[6])) , (acc_imod_sva[6:5])})))))) + conv_u2s_4_6(ACC1_acc_itm[9:6]));
+  assign FRAME_acc_22_cse = nl_FRAME_acc_22_cse[9:0];
+  assign nl_FRAME_acc_5_psp_sva = conv_u2u_10_11({(ACC1_acc_itm[13]) , (ACC1_acc_itm[13])
+      , FRAME_acc_33_itm}) + conv_s2u_10_11(FRAME_acc_22_cse);
+  assign FRAME_acc_5_psp_sva = nl_FRAME_acc_5_psp_sva[10:0];
+  assign nl_acc_imod_sva = (conv_s2s_6_7(conv_u2s_5_6(conv_u2u_4_5({(ACC1_acc_itm[7:6])
+      , (ACC1_acc_itm[7:6])}) + conv_u2u_3_5({(conv_u2u_1_2(ACC1_acc_itm[9]) + conv_u2u_1_2(~
+      (ACC1_acc_itm[13]))) , (ACC1_acc_itm[8])})) + conv_s2s_5_6({(ACC1_acc_itm[5])
+      , 1'b0 , (ACC1_acc_itm[5]) , 1'b0 , (ACC1_acc_itm[5])})) + conv_u2s_6_7(conv_u2u_5_6({(~
+      (ACC1_acc_itm[9:8])) , (~ (ACC1_acc_itm[12:10]))}) + conv_u2u_4_6(ACC1_acc_itm[4:1])))
+      + 7'b1011111;
+  assign acc_imod_sva = nl_acc_imod_sva[6:0];
+  assign nl_FRAME_acc_33_itm = conv_u2u_7_8({(ACC1_acc_itm[13]) , 1'b0 , (signext_5_1(ACC1_acc_itm[13]))})
+      + conv_u2u_6_8({(ACC1_acc_itm[13]) , 1'b0 , (signext_4_1(ACC1_acc_itm[13]))});
+  assign FRAME_acc_33_itm = nl_FRAME_acc_33_itm[7:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      ACC1_slc_regs_regs_2_sg2_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_sg2_1_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_sg2_2_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_1_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_1_1_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_1_2_itm <= 10'b0;
+      regs_regs_1_1_sva <= 30'b0;
+      regs_regs_1_sg2_sva <= 30'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= 6'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= 10'b0;
+    end
+    else begin
+      if ( en ) begin
+        ACC1_slc_regs_regs_2_sg2_itm <= regs_regs_1_sg2_sva[9:0];
+        ACC1_slc_regs_regs_2_sg2_1_itm <= regs_regs_1_sg2_sva[19:10];
+        ACC1_slc_regs_regs_2_sg2_2_itm <= regs_regs_1_sg2_sva[29:20];
+        ACC1_slc_regs_regs_2_1_itm <= regs_regs_1_1_sva[9:0];
+        ACC1_slc_regs_regs_2_1_1_itm <= regs_regs_1_1_sva[19:10];
+        ACC1_slc_regs_regs_2_1_2_itm <= regs_regs_1_1_sva[29:20];
+        regs_regs_1_1_sva <= vin_rsc_mgc_in_wire_d[29:0];
+        regs_regs_1_sg2_sva <= vin_rsc_mgc_in_wire_d[89:60];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp <= (({(ACC1_acc_itm[13]) , (ACC1_acc_itm[13])
+            , FRAME_acc_33_itm}) + FRAME_acc_22_cse) | ({9'b0 , (FRAME_acc_5_psp_sva[10])});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= (FRAME_acc_5_psp_sva[5:0]) | ({5'b0
+            , (FRAME_acc_5_psp_sva[10])});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= FRAME_acc_5_psp_sva[9:0];
+      end
+    end
+  end
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_1;
+    input [0:0] vector;
+  begin
+    signext_5_1= {{4{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [3:0] signext_4_1;
+    input [0:0] vector;
+  begin
+    signext_4_1= {{3{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_13_14 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_14 = {vector[12], vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_12_14 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_14 = {{2{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_4_9 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_9 = {{5{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_6_10 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_10 = {{4{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_s2u_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2u_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_s2u_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v5/cycle.rpt b/Sobel/sobel.v5/cycle.rpt
new file mode 100644
index 0000000..92eeaae
--- /dev/null
+++ b/Sobel/sobel.v5/cycle.rpt
@@ -0,0 +1,85 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 14:36:15 +0000 2016                      
+
+Solution Settings: sobel.v5
+  Current state: schedule
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                        56  307200     307200            0  1          
+    Design Total:                      56  307200     307200            0  0          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /sobel/core              
+    
+  I/O Data Ranges
+    Port       Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ---------- ---- -------- --------- --------- ------- -------- --------
+    vin:rsc.z  IN   Unsigned        90                                     
+    clk        IN   Unsigned         1                                     
+    en         IN   Unsigned         1                                     
+    arst_n     IN   Unsigned         1                                     
+    vout:rsc.z OUT  Unsigned        30                                     
+    
+  Memory Resources
+    Resource Name: /sobel/vin:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 90
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable   Indices Phys Memory Address     
+      ---------- ------- -----------------------
+      /sobel/vin    0:89 00000000-00000000 (0-0) 
+      
+    Resource Name: /sobel/vout:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 30
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable    Indices Phys Memory Address     
+      ----------- ------- -----------------------
+      /sobel/vout    0:29 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process     Loop             Iterations C-Steps Total Cycles  Duration  Unroll Init Comments 
+    ----------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
+    /sobel/core core:rlp           Infinite       0       307201   6.14 ms                       
+    /sobel/core   main             Infinite       2       307201   6.14 ms            1          
+    
+  Loop Execution Profile
+    Process     Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------- ---------------- ------------ -------------------------- ----------------- --------
+    /sobel/core core:rlp                   0                        0.00           307200           
+    /sobel/core   main                307201                      100.00           307200           
+    
+  End of Report
diff --git a/Sobel/sobel.v5/cycle.v b/Sobel/sobel.v5/cycle.v
new file mode 100644
index 0000000..008d3b4
--- /dev/null
+++ b/Sobel/sobel.v5/cycle.v
@@ -0,0 +1,482 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:36:15 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg [29:0] regs_regs_1_1_sva;
+    reg [29:0] regs_regs_1_sg2_sva;
+    reg [89:0] regs_regs_0_sva_1;
+    reg [12:0] ACC1_slc_psp_sva;
+    reg [6:0] acc_imod_sva;
+    reg [10:0] FRAME_acc_5_psp_sva;
+    reg [9:0] ACC1_slc_regs_regs_2_sg2_itm;
+    reg [9:0] ACC1_slc_regs_regs_2_sg2_1_itm;
+    reg [9:0] ACC1_slc_regs_regs_2_sg2_2_itm;
+    reg [9:0] ACC1_slc_regs_regs_2_1_itm;
+    reg [9:0] ACC1_slc_regs_regs_2_1_1_itm;
+    reg [9:0] ACC1_slc_regs_regs_2_1_2_itm;
+    reg [29:0] regs_regs_0_sva_sg2;
+    reg [29:0] regs_regs_0_sva_2;
+    reg [7:0] FRAME_acc_33_cse;
+    reg [9:0] FRAME_acc_22_cse;
+
+    begin : core_rlpExit
+      forever begin : core_rlp
+        // C-Step 0 of Loop 'core_rlp'
+        regs_regs_1_1_sva = 30'b0;
+        regs_regs_1_sg2_sva = 30'b0;
+        regs_regs_0_sva_2 = 30'b0;
+        regs_regs_0_sva_sg2 = 30'b0;
+        begin : mainExit
+          forever begin : main
+            // C-Step 0 of Loop 'main'
+            ACC1_slc_regs_regs_2_sg2_itm = regs_regs_1_sg2_sva[9:0];
+            ACC1_slc_regs_regs_2_sg2_1_itm = regs_regs_1_sg2_sva[19:10];
+            ACC1_slc_regs_regs_2_sg2_2_itm = regs_regs_1_sg2_sva[29:20];
+            ACC1_slc_regs_regs_2_1_itm = regs_regs_1_1_sva[9:0];
+            ACC1_slc_regs_regs_2_1_1_itm = regs_regs_1_1_sva[19:10];
+            ACC1_slc_regs_regs_2_1_2_itm = regs_regs_1_1_sva[29:20];
+            regs_regs_1_sg2_sva = regs_regs_0_sva_sg2;
+            regs_regs_1_1_sva = regs_regs_0_sva_2;
+            begin : waitLoop0Exit
+              forever begin : waitLoop0
+                @(posedge clk or negedge ( arst_n ));
+                if ( ~ arst_n )
+                  disable core_rlpExit;
+                if ( en )
+                  disable waitLoop0Exit;
+              end
+            end
+            // C-Step 1 of Loop 'main'
+            regs_regs_0_sva_1 = vin_rsc_mgc_in_wire_d;
+            ACC1_slc_psp_sva = readslicef_14_13_1((conv_s2s_13_14(conv_s2s_12_13(conv_s2s_11_12(conv_s2s_10_11(regs_regs_0_sva_1[79:70])
+                + conv_s2s_10_11(regs_regs_0_sva_1[89:80])) + conv_s2s_11_12(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_sg2_itm
+                , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_sg2_1_itm , 1'b1})))))
+                + conv_s2s_12_13(conv_s2s_11_12(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_sg2_2_itm
+                , 1'b1}) + conv_s2s_11_12({(~ ACC1_slc_regs_regs_2_1_itm) , 1'b1}))))
+                + conv_s2s_11_12(readslicef_12_11_1((conv_s2s_11_12({(~ ACC1_slc_regs_regs_2_1_1_itm)
+                , 1'b1}) + conv_s2s_11_12({(~ ACC1_slc_regs_regs_2_1_2_itm) , 1'b1}))))))
+                + conv_s2s_12_14(conv_s2s_11_12(conv_s2s_10_11(regs_regs_0_sva_1[9:0])
+                + conv_s2s_10_11(regs_regs_0_sva_1[19:10])) + conv_s2s_11_12(conv_s2s_10_11(regs_regs_0_sva_1[29:20])
+                + conv_s2s_10_11(regs_regs_0_sva_1[69:60])))));
+            acc_imod_sva = (conv_s2s_6_7(conv_u2s_5_6(conv_u2u_4_5({(ACC1_slc_psp_sva[6:5])
+                , (ACC1_slc_psp_sva[6:5])}) + conv_u2u_3_5({(conv_u2u_1_2(ACC1_slc_psp_sva[8])
+                + conv_u2u_1_2(~ (ACC1_slc_psp_sva[12]))) , (ACC1_slc_psp_sva[7])}))
+                + conv_s2s_5_6({(ACC1_slc_psp_sva[4]) , 1'b0 , (ACC1_slc_psp_sva[4])
+                , 1'b0 , (ACC1_slc_psp_sva[4])})) + conv_u2s_6_7(conv_u2u_5_6({(~
+                (ACC1_slc_psp_sva[8:7])) , (~ (ACC1_slc_psp_sva[11:9]))}) + conv_u2u_4_6(ACC1_slc_psp_sva[3:0])))
+                + 7'b1011111;
+            FRAME_acc_33_cse = conv_u2u_7_8({(ACC1_slc_psp_sva[12]) , 1'b0 , (signext_5_1(ACC1_slc_psp_sva[12]))})
+                + conv_u2u_6_8({(ACC1_slc_psp_sva[12]) , 1'b0 , (signext_4_1(ACC1_slc_psp_sva[12]))});
+            FRAME_acc_22_cse = conv_u2s_9_11(conv_u2s_18_10(conv_u2u_4_9(ACC1_slc_psp_sva[12:9])
+                * 9'b10011)) + conv_s2s_6_10(conv_s2s_4_6(conv_u2s_3_4(conv_u2u_2_3(conv_u2u_1_2(ACC1_slc_psp_sva[4])
+                + conv_u2u_1_2(acc_imod_sva[4])) + conv_u2u_2_3(ACC1_slc_psp_sva[8:7]))
+                + conv_s2s_3_4(conv_s2s_2_3(acc_imod_sva[6:5]) + conv_s2s_1_3(readslicef_5_1_4(((({(acc_imod_sva[4])
+                , 1'b0 , (acc_imod_sva[4]) , 1'b0 , (acc_imod_sva[4])}) + conv_u2s_4_5(acc_imod_sva[3:0]))
+                + ({(conv_s2u_2_3(acc_imod_sva[6:5]) + conv_s2u_1_3(acc_imod_sva[6]))
+                , (acc_imod_sva[6:5])})))))) + conv_u2s_4_6(ACC1_slc_psp_sva[8:5]));
+            FRAME_acc_5_psp_sva = conv_u2u_10_11({(ACC1_slc_psp_sva[12]) , (ACC1_slc_psp_sva[12])
+                , FRAME_acc_33_cse}) + conv_s2u_10_11(FRAME_acc_22_cse);
+            vout_rsc_mgc_out_stdreg_d <= {((({(ACC1_slc_psp_sva[12]) , (ACC1_slc_psp_sva[12])
+                , FRAME_acc_33_cse}) + FRAME_acc_22_cse) | ({9'b0, FRAME_acc_5_psp_sva[10]}))
+                , (FRAME_acc_5_psp_sva[9:6]) , ((FRAME_acc_5_psp_sva[5:0]) | ({5'b0,
+                FRAME_acc_5_psp_sva[10]})) , (FRAME_acc_5_psp_sva[9:0])};
+            regs_regs_0_sva_2 = regs_regs_0_sva_1[29:0];
+            regs_regs_0_sva_sg2 = regs_regs_0_sva_1[89:60];
+          end
+        end
+      end
+    end
+    FRAME_acc_22_cse = 10'b0;
+    FRAME_acc_33_cse = 8'b0;
+    regs_regs_0_sva_2 = 30'b0;
+    regs_regs_0_sva_sg2 = 30'b0;
+    ACC1_slc_regs_regs_2_1_2_itm = 10'b0;
+    ACC1_slc_regs_regs_2_1_1_itm = 10'b0;
+    ACC1_slc_regs_regs_2_1_itm = 10'b0;
+    ACC1_slc_regs_regs_2_sg2_2_itm = 10'b0;
+    ACC1_slc_regs_regs_2_sg2_1_itm = 10'b0;
+    ACC1_slc_regs_regs_2_sg2_itm = 10'b0;
+    FRAME_acc_5_psp_sva = 11'b0;
+    acc_imod_sva = 7'b0;
+    ACC1_slc_psp_sva = 13'b0;
+    regs_regs_0_sva_1 = 90'b0;
+    regs_regs_1_sg2_sva = 30'b0;
+    regs_regs_1_1_sva = 30'b0;
+    vout_rsc_mgc_out_stdreg_d <= 30'b0;
+  end
+
+
+  function [12:0] readslicef_14_13_1;
+    input [13:0] vector;
+    reg [13:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_14_13_1 = tmp[12:0];
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_1;
+    input [0:0] vector;
+  begin
+    signext_5_1= {{4{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [3:0] signext_4_1;
+    input [0:0] vector;
+  begin
+    signext_4_1= {{3{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_13_14 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_14 = {vector[12], vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_12_14 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_14 = {{2{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_4_9 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_9 = {{5{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_6_10 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_10 = {{4{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_s2u_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2u_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_s2u_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v5/cycle_mgc_ioport.v b/Sobel/sobel.v5/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v5/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v5/cycle_mgc_ioport_v2001.v b/Sobel/sobel.v5/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v5/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v5/cycle_set.tcl b/Sobel/sobel.v5/cycle_set.tcl
new file mode 100644
index 0000000..3603b71
--- /dev/null
+++ b/Sobel/sobel.v5/cycle_set.tcl
@@ -0,0 +1,52 @@
+
+# Loop constraints
+directive set /sobel/core/core:rlp CSTEPS_FROM {{. == 0}}
+directive set /sobel/core/core:rlp/main CSTEPS_FROM {{. == 2} {.. == 0}}
+
+# IO operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:io_read(vin:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:io_write(vout:rsc.d) CSTEPS_FROM {{.. == 1}}
+
+# Real operation constraints
+directive set /sobel/core/core:rlp/main/ACC1:acc#37 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#36 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#41 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#35 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#34 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#40 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#43 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#39 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#38 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#42 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#11 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#13 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#12 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#15 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#23 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#17 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#19 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#18 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#20 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#21 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#22 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#30 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#24 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#26 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#27 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#28 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#29 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:or CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:or#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#9 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc CSTEPS_FROM {{.. == 1}}
diff --git a/Sobel/sobel.v5/directives.tcl b/Sobel/sobel.v5/directives.tcl
new file mode 100644
index 0000000..504c4bb
--- /dev/null
+++ b/Sobel/sobel.v5/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
+go extract
diff --git a/Sobel/sobel.v5/messages.txt b/Sobel/sobel.v5/messages.txt
new file mode 100644
index 0000000..ac40a37
--- /dev/null
+++ b/Sobel/sobel.v5/messages.txt
@@ -0,0 +1,225 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.26 seconds, memory usage 216924kB, peak memory usage 339848kB (SOL-9)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.cpp(130): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+
+# Messages from "go compile"
+
+Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'sobel' specified by directive (CIN-52)
+Synthesizing routine 'sobel' (CIN-13)
+Inlining routine 'sobel' (CIN-14)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Optimizing block '/sobel' ... (CIN-4)
+Inout port 'vin' is only used as an input. (OPT-10)
+Inout port 'vout' is only used as an output. (OPT-11)
+Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+Design 'sobel' was read (SOL-1)
+Optimizing partition '/sobel': (Total ops = 454, Real ops = 107, Vars = 89) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 454, Real ops = 107, Vars = 87) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 395, Real ops = 93, Vars = 92) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 395, Real ops = 93, Vars = 94) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 395, Real ops = 93, Vars = 94) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 395, Real ops = 93, Vars = 92) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 340, Real ops = 92, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 324, Real ops = 92, Vars = 74) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 324, Real ops = 92, Vars = 74) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 324, Real ops = 92, Vars = 76) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 324, Real ops = 92, Vars = 76) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 313, Real ops = 90, Vars = 103) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 328, Real ops = 86, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 328, Real ops = 86, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 328, Real ops = 86, Vars = 26) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 328, Real ops = 86, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 328, Real ops = 86, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 328, Real ops = 86, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 328, Real ops = 86, Vars = 25) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 328, Real ops = 86, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 328, Real ops = 86, Vars = 23) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 361, Real ops = 86, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 268, Real ops = 72, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 268, Real ops = 72, Vars = 23) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 264, Real ops = 72, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 262, Real ops = 72, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 262, Real ops = 72, Vars = 23) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 262, Real ops = 72, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 262, Real ops = 72, Vars = 23) (SOL-10)
+Completed transformation 'compile' on solution 'sobel.v5': elapsed time 2.76 seconds, memory usage 217440kB, peak memory usage 339848kB (SOL-9)
+Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'sobel.v5' (SOL-8)
+Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+Loop '/sobel/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/sobel/core': (Total ops = 433, Real ops = 135, Vars = 21) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 252, Real ops = 72, Vars = 17) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 234, Real ops = 57, Vars = 16) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 234, Real ops = 57, Vars = 16) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 161, Real ops = 30, Vars = 19) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 137, Real ops = 30, Vars = 16) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 134, Real ops = 27, Vars = 13) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 134, Real ops = 27, Vars = 18) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 134, Real ops = 27, Vars = 15) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 134, Real ops = 27, Vars = 13) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 134, Real ops = 27, Vars = 18) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 134, Real ops = 27, Vars = 13) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 134, Real ops = 27, Vars = 18) (SOL-10)
+I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+Optimizing partition '/sobel': (Total ops = 134, Real ops = 27, Vars = 18) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 134, Real ops = 27, Vars = 13) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 134, Real ops = 27, Vars = 13) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 134, Real ops = 27, Vars = 18) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 128, Real ops = 27, Vars = 26) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 132, Real ops = 27, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 107, Real ops = 20, Vars = 11) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 107, Real ops = 20, Vars = 11) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 107, Real ops = 20, Vars = 16) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 107, Real ops = 20, Vars = 11) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 107, Real ops = 20, Vars = 16) (SOL-10)
+Design 'sobel' contains '55' real operations. (SOL-11)
+Optimizing partition '/sobel/core': (Total ops = 110, Real ops = 20, Vars = 12) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 209, Real ops = 24, Vars = 72) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 114, Real ops = 22, Vars = 15) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 113, Real ops = 22, Vars = 14) (SOL-10)
+Completed transformation 'architect' on solution 'sobel.v5': elapsed time 5.57 seconds, memory usage 217692kB, peak memory usage 339848kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'sobel.v5' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 307200, Area (Datapath, Register, Total) = 677.70, 0.00, 677.70 (CRAAS-11)
+Optimized LOOP 'main': Latency = 307200, Area (Datapath, Register, Total) = 675.96, 0.00, 675.96 (CRAAS-10)
+Optimized LOOP 'main': Latency = 307200, Area (Datapath, Register, Total) = 670.96, 0.00, 670.96 (CRAAS-10)
+Optimized LOOP 'main': Latency = 307200, Area (Datapath, Register, Total) = 668.89, 0.00, 668.89 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 307200, Area (Datapath, Register, Total) = 668.89, 0.00, 668.89 (CRAAS-12)
+Completed transformation 'allocate' on solution 'sobel.v5': elapsed time 0.34 seconds, memory usage 217892kB, peak memory usage 339848kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'sobel.v5' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 184, Real ops = 56, Vars = 36) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 174, Real ops = 55, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 169, Real ops = 55, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 123, Real ops = 39, Vars = 16) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 137, Real ops = 39, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 39, Vars = 21) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 123, Real ops = 39, Vars = 16) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 137, Real ops = 39, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 39, Vars = 21) (SOL-10)
+Completed transformation 'schedule' on solution 'sobel.v5': elapsed time 0.86 seconds, memory usage 219240kB, peak memory usage 339848kB (SOL-9)
+Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'sobel.v5' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 205, Real ops = 47, Vars = 127) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 196, Real ops = 47, Vars = 120) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 250, Real ops = 47, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 241, Real ops = 47, Vars = 18) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 138, Real ops = 50, Vars = 29) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 129, Real ops = 50, Vars = 22) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 138, Real ops = 50, Vars = 29) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 129, Real ops = 50, Vars = 22) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 22) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+Completed transformation 'dpfsm' on solution 'sobel.v5': elapsed time 0.23 seconds, memory usage 219620kB, peak memory usage 339848kB (SOL-9)
+
+# Messages from "go extract"
+
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'sobel.v5' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 134) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 127) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 134) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 127) (SOL-10)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 134) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 127) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 139, Real ops = 49, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 130, Real ops = 49, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 139, Real ops = 49, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 130, Real ops = 49, Vars = 21) (SOL-10)
+Completed transformation 'extract' on solution 'sobel.v5': elapsed time 3.42 seconds, memory usage 219996kB, peak memory usage 339848kB (SOL-9)
diff --git a/Sobel/sobel.v5/reg_sharing.tcl b/Sobel/sobel.v5/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v5/reg_sharing.tcl
diff --git a/Sobel/sobel.v5/res_sharing.tcl b/Sobel/sobel.v5/res_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v5/res_sharing.tcl
diff --git a/Sobel/sobel.v5/rtl.rpt b/Sobel/sobel.v5/rtl.rpt
new file mode 100644
index 0000000..2264c8c
--- /dev/null
+++ b/Sobel/sobel.v5/rtl.rpt
@@ -0,0 +1,793 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 14:36:28 +0000 2016                      
+
+Solution Settings: sobel.v5
+  Current state: extract
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                        56  307200     307200            0  1          
+    Design Total:                      56  307200     307200            0  0          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(1,0,1,0,2)                           2.319                       0.000      2.319 0.506          2           2 
+    mgc_add(10,0,10,1,11)                       11.000                       0.000     11.000 1.139          1           1 
+    mgc_add(10,1,10,1,11)                       11.000                       0.000     11.000 1.139          6           4 
+    mgc_add(11,1,11,1,12)                       12.000                       0.000     12.000 1.206          6           6 
+    mgc_add(12,1,12,1,13)                       13.000                       0.000     13.000 1.272          1           1 
+    mgc_add(13,1,12,1,14)                       14.000                       0.000     14.000 1.338          1           1 
+    mgc_add(19,0,2,1,19)                        20.000                       0.000     20.000 1.908          1           0 
+    mgc_add(2,0,2,0,3)                           3.311                       0.000      3.311 0.653          3           1 
+    mgc_add(2,1,1,1,3)                           3.000                       0.000      3.000 0.495          2           2 
+    mgc_add(3,0,3,1,4)                           4.000                       0.000      4.000 0.598          2           1 
+    mgc_add(4,0,4,1,6)                           5.000                       0.000      5.000 0.529          3           2 
+    mgc_add(4,1,2,1,5)                           5.000                       0.000      5.000 0.697          1           0 
+    mgc_add(5,0,5,1,6)                           6.000                       0.000      6.000 0.775          4           4 
+    mgc_add(6,0,6,1,7)                           7.000                       0.000      7.000 0.854          1           1 
+    mgc_add(7,0,6,0,8)                           8.271                       0.000      8.271 1.093          0           1 
+    mgc_add(7,0,7,0,7)                           8.267                       0.000      8.267 1.091          1           1 
+    mgc_add(8,0,7,0,8)                           9.262                       0.000      9.262 1.165          1           0 
+    mgc_add(9,0,6,1,10)                         10.000                       0.000     10.000 1.076          2           1 
+    mgc_and(19,2)                               13.867                       0.000     13.867 0.263          1           0 
+    mgc_mul(4,0,5,0,9)                         330.250                       2.000     10.250 2.700          1           1 
+    mgc_not(1)                                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_not(10)                                  0.000                       0.000      0.000 0.000          0           3 
+    mgc_not(2)                                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_not(3)                                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_or(10,2)                                 7.298                       0.000      7.298 0.268          1           1 
+    mgc_or(6,2)                                  4.379                       0.000      4.379 0.268          1           1 
+    mgc_reg_pos(10,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           8 
+    mgc_reg_pos(30,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(6,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,90)                            0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(2,30)                         0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):             581.415                       2.000    261.000                              
+    
+  Area Scores
+                      Post-Scheduling  Post-DP & FSM Post-Assignment 
+    ----------------- --------------- -------------- ---------------
+    Total Area Score:    668.9          581.4           581.4        
+    Total Reg:             0.0            0.0             0.0        
+                                                                     
+    DataPath:            668.9 (100%)   581.4 (100%)    581.4 (100%) 
+      MUX:                 0.0            0.0             0.0        
+      FUNC:              643.4  (96%)   569.7  (98%)    569.7  (98%) 
+      LOGIC:              25.5   (4%)    11.7   (2%)     11.7   (2%) 
+      BUFFER:              0.0            0.0             0.0        
+      MEM:                 0.0            0.0             0.0        
+      ROM:                 0.0            0.0             0.0        
+      REG:                 0.0            0.0             0.0        
+                                                                     
+    
+    FSM:                   0.0            0.0             0.0        
+      FSM-REG:             0.0            0.0             0.0        
+      FSM-COMB:            0.0            0.0             0.0        
+                                                                     
+    
+  Register-to-Variable Mappings
+    Register                             Size(bits) Gated Register CG Opt Done Variables                                             
+    ------------------------------------ ---------- -------------- ----------- -----------------------------------------------------
+    regs.regs(1)#1.sva                           30         Y                  regs.regs(1)#1.sva                                    
+    regs.regs(1).sg2.sva                         30         Y                  regs.regs(1).sg2.sva                                  
+    ACC1:slc(regs.regs(2)#1)#1.itm               10         Y                  ACC1:slc(regs.regs(2)#1)#1.itm                        
+    ACC1:slc(regs.regs(2)#1)#2.itm               10         Y                  ACC1:slc(regs.regs(2)#1)#2.itm                        
+    ACC1:slc(regs.regs(2)#1).itm                 10         Y                  ACC1:slc(regs.regs(2)#1).itm                          
+    ACC1:slc(regs.regs(2).sg2)#1.itm             10         Y                  ACC1:slc(regs.regs(2).sg2)#1.itm                      
+    ACC1:slc(regs.regs(2).sg2)#2.itm             10         Y                  ACC1:slc(regs.regs(2).sg2)#2.itm                      
+    ACC1:slc(regs.regs(2).sg2).itm               10         Y                  ACC1:slc(regs.regs(2).sg2).itm                        
+    reg(vout:rsc:mgc_out_stdreg.d).tmp           10         Y                  reg(vout:rsc:mgc_out_stdreg.d).tmp                    
+    reg(vout:rsc:mgc_out_stdreg.d).tmp#3         10         Y                  reg(vout:rsc:mgc_out_stdreg.d).tmp#3                  
+    reg(vout:rsc:mgc_out_stdreg.d).tmp#2          6         Y                  reg(vout:rsc:mgc_out_stdreg.d).tmp#2                  
+                                                                                                                                     
+    Total:                                      146            146           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  14.432002
+      Slack:      5.567997999999999
+      
+      Path                                               Startpoint                                       Endpoint                                    Delay   Slack   
+      -------------------------------------------------- ------------------------------------------------ ------------------------------------------- ------- -------
+      1                                                  sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   sobel:core/reg(vout:rsc:mgc_out_stdreg.d)   14.4320 5.5680  
+                                                                                                                                                                      
+        Instance                                         Component                                                                                    Delta   Delay   
+        --------                                         ---------                                                                                    -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2).sg2).itm                                                                                                     0.0000  0.0000  
+        sobel:core/conc                                                                                                                               0.0000  0.0000  
+        sobel:core/conc.itm                                                                                                                           0.0000  0.0000  
+        sobel:core/ACC1:acc#36                           mgc_add_11_1_11_1_12                                                                         1.2059  1.2059  
+        sobel:core/ACC1:acc#36.itm                                                                                                                    0.0000  1.2059  
+        sobel:core/ACC1:slc#3                                                                                                                         0.0000  1.2059  
+        sobel:core/ACC1:slc#3.itm                                                                                                                     0.0000  1.2059  
+        sobel:core/ACC1:acc#41                           mgc_add_11_1_11_1_12                                                                         1.2059  2.4119  
+        sobel:core/ACC1:acc#41.itm                                                                                                                    0.0000  2.4119  
+        sobel:core/ACC1:acc#43                           mgc_add_12_1_12_1_13                                                                         1.2718  3.6837  
+        sobel:core/ACC1:acc#43.itm                                                                                                                    0.0000  3.6837  
+        sobel:core/ACC1:acc                              mgc_add_13_1_12_1_14                                                                         1.3384  5.0221  
+        sobel:core/ACC1:acc.itm                                                                                                                       0.0000  5.0221  
+        sobel:core/ACC1:slc                                                                                                                           0.0000  5.0221  
+        sobel:core/ACC1:slc.psp.sva                                                                                                                   0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6                                                                                                            0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6.itm                                                                                                        0.0000  5.0221  
+        sobel:core/FRAME:acc#31                          mgc_add_1_0_1_0_2                                                                            0.5058  5.5278  
+        sobel:core/FRAME:acc#31.itm                                                                                                                   0.0000  5.5278  
+        sobel:core/FRAME:conc#29                                                                                                                      0.0000  5.5278  
+        sobel:core/FRAME:conc#29.itm                                                                                                                  0.0000  5.5278  
+        sobel:core/FRAME:acc#11                          mgc_add_4_0_4_1_6                                                                            0.5286  6.0564  
+        sobel:core/FRAME:acc#11.itm                                                                                                                   0.0000  6.0564  
+        sobel:core/FRAME:acc#13                          mgc_add_5_0_5_1_6                                                                            0.7751  6.8315  
+        sobel:core/FRAME:acc#13.itm                                                                                                                   0.0000  6.8315  
+        sobel:core/FRAME:acc#14                          mgc_add_6_0_6_1_7                                                                            0.8537  7.6852  
+        sobel:core/FRAME:acc#14.itm                                                                                                                   0.0000  7.6852  
+        sobel:core/acc                                   mgc_add_7_0_7_0_7                                                                            1.0910  8.7763  
+        sobel:core/acc.imod.sva                                                                                                                       0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#12                                                                                                               0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#12.itm                                                                                                           0.0000  8.7763  
+        sobel:core/conc#55                                                                                                                            0.0000  8.7763  
+        sobel:core/conc#55.itm                                                                                                                        0.0000  8.7763  
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_5_1_6                                                                            0.7751  9.5514  
+        sobel:core/FRAME:acc#16.itm                                                                                                                   0.0000  9.5514  
+        sobel:core/acc#3                                 mgc_add_5_0_5_1_6                                                                            0.7751  10.3265 
+        sobel:core/acc#3.itm                                                                                                                          0.0000  10.3265 
+        sobel:core/FRAME:slc#5                                                                                                                        0.0000  10.3265 
+        sobel:core/FRAME:slc#5.itm                                                                                                                    0.0000  10.3265 
+        sobel:core/FRAME:acc#18                          mgc_add_2_1_1_1_3                                                                            0.4952  10.8217 
+        sobel:core/FRAME:acc#18.itm                                                                                                                   0.0000  10.8217 
+        sobel:core/FRAME:acc#20                          mgc_add_3_0_3_1_4                                                                            0.5984  11.4202 
+        sobel:core/FRAME:acc#20.itm                                                                                                                   0.0000  11.4202 
+        sobel:core/FRAME:acc#21                          mgc_add_4_0_4_1_6                                                                            0.5286  11.9487 
+        sobel:core/FRAME:acc#21.itm                                                                                                                   0.0000  11.9487 
+        sobel:core/FRAME:acc#22                          mgc_add_9_0_6_1_10                                                                           1.0764  13.0252 
+        sobel:core/FRAME:acc#22.cse                                                                                                                   0.0000  13.0252 
+        sobel:core/FRAME:acc#3                           mgc_add_10_1_10_1_11                                                                         1.1389  14.1641 
+        sobel:core/FRAME:acc#3.itm                                                                                                                    0.0000  14.1641 
+        sobel:core/FRAME:or                              mgc_or_10_2                                                                                  0.2679  14.4320 
+        sobel:core/FRAME:or.itm                                                                                                                       0.0000  14.4320 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)        mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  14.4320 
+                                                                                                                                                                      
+      2                                                  sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2 14.4320 5.5680  
+                                                                                                                                                                      
+        Instance                                         Component                                                                                    Delta   Delay   
+        --------                                         ---------                                                                                    -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2).sg2).itm                                                                                                     0.0000  0.0000  
+        sobel:core/conc                                                                                                                               0.0000  0.0000  
+        sobel:core/conc.itm                                                                                                                           0.0000  0.0000  
+        sobel:core/ACC1:acc#36                           mgc_add_11_1_11_1_12                                                                         1.2059  1.2059  
+        sobel:core/ACC1:acc#36.itm                                                                                                                    0.0000  1.2059  
+        sobel:core/ACC1:slc#3                                                                                                                         0.0000  1.2059  
+        sobel:core/ACC1:slc#3.itm                                                                                                                     0.0000  1.2059  
+        sobel:core/ACC1:acc#41                           mgc_add_11_1_11_1_12                                                                         1.2059  2.4119  
+        sobel:core/ACC1:acc#41.itm                                                                                                                    0.0000  2.4119  
+        sobel:core/ACC1:acc#43                           mgc_add_12_1_12_1_13                                                                         1.2718  3.6837  
+        sobel:core/ACC1:acc#43.itm                                                                                                                    0.0000  3.6837  
+        sobel:core/ACC1:acc                              mgc_add_13_1_12_1_14                                                                         1.3384  5.0221  
+        sobel:core/ACC1:acc.itm                                                                                                                       0.0000  5.0221  
+        sobel:core/ACC1:slc                                                                                                                           0.0000  5.0221  
+        sobel:core/ACC1:slc.psp.sva                                                                                                                   0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6                                                                                                            0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6.itm                                                                                                        0.0000  5.0221  
+        sobel:core/FRAME:acc#31                          mgc_add_1_0_1_0_2                                                                            0.5058  5.5278  
+        sobel:core/FRAME:acc#31.itm                                                                                                                   0.0000  5.5278  
+        sobel:core/FRAME:conc#29                                                                                                                      0.0000  5.5278  
+        sobel:core/FRAME:conc#29.itm                                                                                                                  0.0000  5.5278  
+        sobel:core/FRAME:acc#11                          mgc_add_4_0_4_1_6                                                                            0.5286  6.0564  
+        sobel:core/FRAME:acc#11.itm                                                                                                                   0.0000  6.0564  
+        sobel:core/FRAME:acc#13                          mgc_add_5_0_5_1_6                                                                            0.7751  6.8315  
+        sobel:core/FRAME:acc#13.itm                                                                                                                   0.0000  6.8315  
+        sobel:core/FRAME:acc#14                          mgc_add_6_0_6_1_7                                                                            0.8537  7.6852  
+        sobel:core/FRAME:acc#14.itm                                                                                                                   0.0000  7.6852  
+        sobel:core/acc                                   mgc_add_7_0_7_0_7                                                                            1.0910  8.7763  
+        sobel:core/acc.imod.sva                                                                                                                       0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#12                                                                                                               0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#12.itm                                                                                                           0.0000  8.7763  
+        sobel:core/conc#55                                                                                                                            0.0000  8.7763  
+        sobel:core/conc#55.itm                                                                                                                        0.0000  8.7763  
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_5_1_6                                                                            0.7751  9.5514  
+        sobel:core/FRAME:acc#16.itm                                                                                                                   0.0000  9.5514  
+        sobel:core/acc#3                                 mgc_add_5_0_5_1_6                                                                            0.7751  10.3265 
+        sobel:core/acc#3.itm                                                                                                                          0.0000  10.3265 
+        sobel:core/FRAME:slc#5                                                                                                                        0.0000  10.3265 
+        sobel:core/FRAME:slc#5.itm                                                                                                                    0.0000  10.3265 
+        sobel:core/FRAME:acc#18                          mgc_add_2_1_1_1_3                                                                            0.4952  10.8217 
+        sobel:core/FRAME:acc#18.itm                                                                                                                   0.0000  10.8217 
+        sobel:core/FRAME:acc#20                          mgc_add_3_0_3_1_4                                                                            0.5984  11.4202 
+        sobel:core/FRAME:acc#20.itm                                                                                                                   0.0000  11.4202 
+        sobel:core/FRAME:acc#21                          mgc_add_4_0_4_1_6                                                                            0.5286  11.9487 
+        sobel:core/FRAME:acc#21.itm                                                                                                                   0.0000  11.9487 
+        sobel:core/FRAME:acc#22                          mgc_add_9_0_6_1_10                                                                           1.0764  13.0252 
+        sobel:core/FRAME:acc#22.cse                                                                                                                   0.0000  13.0252 
+        sobel:core/FRAME:acc#5                           mgc_add_10_0_10_1_11                                                                         1.1389  14.1641 
+        sobel:core/FRAME:acc#5.psp.sva                                                                                                                0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#2                                                                                                         0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#2.itm                                                                                                     0.0000  14.1641 
+        sobel:core/FRAME:or#3                            mgc_or_6_2                                                                                   0.2679  14.4320 
+        sobel:core/FRAME:or#3.itm                                                                                                                     0.0000  14.4320 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2      mgc_reg_pos_6_1_0_0_0_1_1                                                                    0.0000  14.4320 
+                                                                                                                                                                      
+      3                                                  sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   sobel:core/reg(vout:rsc:mgc_out_stdreg.d)   14.4320 5.5680  
+                                                                                                                                                                      
+        Instance                                         Component                                                                                    Delta   Delay   
+        --------                                         ---------                                                                                    -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2).sg2).itm                                                                                                     0.0000  0.0000  
+        sobel:core/conc                                                                                                                               0.0000  0.0000  
+        sobel:core/conc.itm                                                                                                                           0.0000  0.0000  
+        sobel:core/ACC1:acc#36                           mgc_add_11_1_11_1_12                                                                         1.2059  1.2059  
+        sobel:core/ACC1:acc#36.itm                                                                                                                    0.0000  1.2059  
+        sobel:core/ACC1:slc#3                                                                                                                         0.0000  1.2059  
+        sobel:core/ACC1:slc#3.itm                                                                                                                     0.0000  1.2059  
+        sobel:core/ACC1:acc#41                           mgc_add_11_1_11_1_12                                                                         1.2059  2.4119  
+        sobel:core/ACC1:acc#41.itm                                                                                                                    0.0000  2.4119  
+        sobel:core/ACC1:acc#43                           mgc_add_12_1_12_1_13                                                                         1.2718  3.6837  
+        sobel:core/ACC1:acc#43.itm                                                                                                                    0.0000  3.6837  
+        sobel:core/ACC1:acc                              mgc_add_13_1_12_1_14                                                                         1.3384  5.0221  
+        sobel:core/ACC1:acc.itm                                                                                                                       0.0000  5.0221  
+        sobel:core/ACC1:slc                                                                                                                           0.0000  5.0221  
+        sobel:core/ACC1:slc.psp.sva                                                                                                                   0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6                                                                                                            0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6.itm                                                                                                        0.0000  5.0221  
+        sobel:core/FRAME:acc#31                          mgc_add_1_0_1_0_2                                                                            0.5058  5.5278  
+        sobel:core/FRAME:acc#31.itm                                                                                                                   0.0000  5.5278  
+        sobel:core/FRAME:conc#29                                                                                                                      0.0000  5.5278  
+        sobel:core/FRAME:conc#29.itm                                                                                                                  0.0000  5.5278  
+        sobel:core/FRAME:acc#11                          mgc_add_4_0_4_1_6                                                                            0.5286  6.0564  
+        sobel:core/FRAME:acc#11.itm                                                                                                                   0.0000  6.0564  
+        sobel:core/FRAME:acc#13                          mgc_add_5_0_5_1_6                                                                            0.7751  6.8315  
+        sobel:core/FRAME:acc#13.itm                                                                                                                   0.0000  6.8315  
+        sobel:core/FRAME:acc#14                          mgc_add_6_0_6_1_7                                                                            0.8537  7.6852  
+        sobel:core/FRAME:acc#14.itm                                                                                                                   0.0000  7.6852  
+        sobel:core/acc                                   mgc_add_7_0_7_0_7                                                                            1.0910  8.7763  
+        sobel:core/acc.imod.sva                                                                                                                       0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#12                                                                                                               0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#12.itm                                                                                                           0.0000  8.7763  
+        sobel:core/conc#55                                                                                                                            0.0000  8.7763  
+        sobel:core/conc#55.itm                                                                                                                        0.0000  8.7763  
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_5_1_6                                                                            0.7751  9.5514  
+        sobel:core/FRAME:acc#16.itm                                                                                                                   0.0000  9.5514  
+        sobel:core/acc#3                                 mgc_add_5_0_5_1_6                                                                            0.7751  10.3265 
+        sobel:core/acc#3.itm                                                                                                                          0.0000  10.3265 
+        sobel:core/FRAME:slc#5                                                                                                                        0.0000  10.3265 
+        sobel:core/FRAME:slc#5.itm                                                                                                                    0.0000  10.3265 
+        sobel:core/FRAME:acc#18                          mgc_add_2_1_1_1_3                                                                            0.4952  10.8217 
+        sobel:core/FRAME:acc#18.itm                                                                                                                   0.0000  10.8217 
+        sobel:core/FRAME:acc#20                          mgc_add_3_0_3_1_4                                                                            0.5984  11.4202 
+        sobel:core/FRAME:acc#20.itm                                                                                                                   0.0000  11.4202 
+        sobel:core/FRAME:acc#21                          mgc_add_4_0_4_1_6                                                                            0.5286  11.9487 
+        sobel:core/FRAME:acc#21.itm                                                                                                                   0.0000  11.9487 
+        sobel:core/FRAME:acc#22                          mgc_add_9_0_6_1_10                                                                           1.0764  13.0252 
+        sobel:core/FRAME:acc#22.cse                                                                                                                   0.0000  13.0252 
+        sobel:core/FRAME:acc#5                           mgc_add_10_0_10_1_11                                                                         1.1389  14.1641 
+        sobel:core/FRAME:acc#5.psp.sva                                                                                                                0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4                                                                                                         0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm                                                                                                     0.0000  14.1641 
+        sobel:core/conc#59                                                                                                                            0.0000  14.1641 
+        sobel:core/conc#59.itm                                                                                                                        0.0000  14.1641 
+        sobel:core/FRAME:or                              mgc_or_10_2                                                                                  0.2679  14.4320 
+        sobel:core/FRAME:or.itm                                                                                                                       0.0000  14.4320 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)        mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  14.4320 
+                                                                                                                                                                      
+      4                                                  sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   sobel:core/reg(vout:rsc:mgc_out_stdreg.d)   14.4320 5.5680  
+                                                                                                                                                                      
+        Instance                                         Component                                                                                    Delta   Delay   
+        --------                                         ---------                                                                                    -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2).sg2).itm                                                                                                     0.0000  0.0000  
+        sobel:core/conc                                                                                                                               0.0000  0.0000  
+        sobel:core/conc.itm                                                                                                                           0.0000  0.0000  
+        sobel:core/ACC1:acc#36                           mgc_add_11_1_11_1_12                                                                         1.2059  1.2059  
+        sobel:core/ACC1:acc#36.itm                                                                                                                    0.0000  1.2059  
+        sobel:core/ACC1:slc#3                                                                                                                         0.0000  1.2059  
+        sobel:core/ACC1:slc#3.itm                                                                                                                     0.0000  1.2059  
+        sobel:core/ACC1:acc#41                           mgc_add_11_1_11_1_12                                                                         1.2059  2.4119  
+        sobel:core/ACC1:acc#41.itm                                                                                                                    0.0000  2.4119  
+        sobel:core/ACC1:acc#43                           mgc_add_12_1_12_1_13                                                                         1.2718  3.6837  
+        sobel:core/ACC1:acc#43.itm                                                                                                                    0.0000  3.6837  
+        sobel:core/ACC1:acc                              mgc_add_13_1_12_1_14                                                                         1.3384  5.0221  
+        sobel:core/ACC1:acc.itm                                                                                                                       0.0000  5.0221  
+        sobel:core/ACC1:slc                                                                                                                           0.0000  5.0221  
+        sobel:core/ACC1:slc.psp.sva                                                                                                                   0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6                                                                                                            0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6.itm                                                                                                        0.0000  5.0221  
+        sobel:core/FRAME:acc#31                          mgc_add_1_0_1_0_2                                                                            0.5058  5.5278  
+        sobel:core/FRAME:acc#31.itm                                                                                                                   0.0000  5.5278  
+        sobel:core/FRAME:conc#29                                                                                                                      0.0000  5.5278  
+        sobel:core/FRAME:conc#29.itm                                                                                                                  0.0000  5.5278  
+        sobel:core/FRAME:acc#11                          mgc_add_4_0_4_1_6                                                                            0.5286  6.0564  
+        sobel:core/FRAME:acc#11.itm                                                                                                                   0.0000  6.0564  
+        sobel:core/FRAME:acc#13                          mgc_add_5_0_5_1_6                                                                            0.7751  6.8315  
+        sobel:core/FRAME:acc#13.itm                                                                                                                   0.0000  6.8315  
+        sobel:core/FRAME:acc#14                          mgc_add_6_0_6_1_7                                                                            0.8537  7.6852  
+        sobel:core/FRAME:acc#14.itm                                                                                                                   0.0000  7.6852  
+        sobel:core/acc                                   mgc_add_7_0_7_0_7                                                                            1.0910  8.7763  
+        sobel:core/acc.imod.sva                                                                                                                       0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#10                                                                                                               0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#10.itm                                                                                                           0.0000  8.7763  
+        sobel:core/conc#55                                                                                                                            0.0000  8.7763  
+        sobel:core/conc#55.itm                                                                                                                        0.0000  8.7763  
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_5_1_6                                                                            0.7751  9.5514  
+        sobel:core/FRAME:acc#16.itm                                                                                                                   0.0000  9.5514  
+        sobel:core/acc#3                                 mgc_add_5_0_5_1_6                                                                            0.7751  10.3265 
+        sobel:core/acc#3.itm                                                                                                                          0.0000  10.3265 
+        sobel:core/FRAME:slc#5                                                                                                                        0.0000  10.3265 
+        sobel:core/FRAME:slc#5.itm                                                                                                                    0.0000  10.3265 
+        sobel:core/FRAME:acc#18                          mgc_add_2_1_1_1_3                                                                            0.4952  10.8217 
+        sobel:core/FRAME:acc#18.itm                                                                                                                   0.0000  10.8217 
+        sobel:core/FRAME:acc#20                          mgc_add_3_0_3_1_4                                                                            0.5984  11.4202 
+        sobel:core/FRAME:acc#20.itm                                                                                                                   0.0000  11.4202 
+        sobel:core/FRAME:acc#21                          mgc_add_4_0_4_1_6                                                                            0.5286  11.9487 
+        sobel:core/FRAME:acc#21.itm                                                                                                                   0.0000  11.9487 
+        sobel:core/FRAME:acc#22                          mgc_add_9_0_6_1_10                                                                           1.0764  13.0252 
+        sobel:core/FRAME:acc#22.cse                                                                                                                   0.0000  13.0252 
+        sobel:core/FRAME:acc#5                           mgc_add_10_0_10_1_11                                                                         1.1389  14.1641 
+        sobel:core/FRAME:acc#5.psp.sva                                                                                                                0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4                                                                                                         0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm                                                                                                     0.0000  14.1641 
+        sobel:core/conc#59                                                                                                                            0.0000  14.1641 
+        sobel:core/conc#59.itm                                                                                                                        0.0000  14.1641 
+        sobel:core/FRAME:or                              mgc_or_10_2                                                                                  0.2679  14.4320 
+        sobel:core/FRAME:or.itm                                                                                                                       0.0000  14.4320 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)        mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  14.4320 
+                                                                                                                                                                      
+      5                                                  sobel:core/reg(ACC1:slc(regs.regs(2).sg2)#2.itm) sobel:core/reg(vout:rsc:mgc_out_stdreg.d)   14.4320 5.5680  
+                                                                                                                                                                      
+        Instance                                         Component                                                                                    Delta   Delay   
+        --------                                         ---------                                                                                    -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2).sg2)#2.itm) mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2).sg2)#2.itm                                                                                                   0.0000  0.0000  
+        sobel:core/conc#51                                                                                                                            0.0000  0.0000  
+        sobel:core/conc#51.itm                                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#35                           mgc_add_11_1_11_1_12                                                                         1.2059  1.2059  
+        sobel:core/ACC1:acc#35.itm                                                                                                                    0.0000  1.2059  
+        sobel:core/ACC1:slc#2                                                                                                                         0.0000  1.2059  
+        sobel:core/ACC1:slc#2.itm                                                                                                                     0.0000  1.2059  
+        sobel:core/ACC1:acc#40                           mgc_add_11_1_11_1_12                                                                         1.2059  2.4119  
+        sobel:core/ACC1:acc#40.itm                                                                                                                    0.0000  2.4119  
+        sobel:core/ACC1:acc#43                           mgc_add_12_1_12_1_13                                                                         1.2718  3.6837  
+        sobel:core/ACC1:acc#43.itm                                                                                                                    0.0000  3.6837  
+        sobel:core/ACC1:acc                              mgc_add_13_1_12_1_14                                                                         1.3384  5.0221  
+        sobel:core/ACC1:acc.itm                                                                                                                       0.0000  5.0221  
+        sobel:core/ACC1:slc                                                                                                                           0.0000  5.0221  
+        sobel:core/ACC1:slc.psp.sva                                                                                                                   0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6                                                                                                            0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6.itm                                                                                                        0.0000  5.0221  
+        sobel:core/FRAME:acc#31                          mgc_add_1_0_1_0_2                                                                            0.5058  5.5278  
+        sobel:core/FRAME:acc#31.itm                                                                                                                   0.0000  5.5278  
+        sobel:core/FRAME:conc#29                                                                                                                      0.0000  5.5278  
+        sobel:core/FRAME:conc#29.itm                                                                                                                  0.0000  5.5278  
+        sobel:core/FRAME:acc#11                          mgc_add_4_0_4_1_6                                                                            0.5286  6.0564  
+        sobel:core/FRAME:acc#11.itm                                                                                                                   0.0000  6.0564  
+        sobel:core/FRAME:acc#13                          mgc_add_5_0_5_1_6                                                                            0.7751  6.8315  
+        sobel:core/FRAME:acc#13.itm                                                                                                                   0.0000  6.8315  
+        sobel:core/FRAME:acc#14                          mgc_add_6_0_6_1_7                                                                            0.8537  7.6852  
+        sobel:core/FRAME:acc#14.itm                                                                                                                   0.0000  7.6852  
+        sobel:core/acc                                   mgc_add_7_0_7_0_7                                                                            1.0910  8.7763  
+        sobel:core/acc.imod.sva                                                                                                                       0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#10                                                                                                               0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#10.itm                                                                                                           0.0000  8.7763  
+        sobel:core/conc#55                                                                                                                            0.0000  8.7763  
+        sobel:core/conc#55.itm                                                                                                                        0.0000  8.7763  
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_5_1_6                                                                            0.7751  9.5514  
+        sobel:core/FRAME:acc#16.itm                                                                                                                   0.0000  9.5514  
+        sobel:core/acc#3                                 mgc_add_5_0_5_1_6                                                                            0.7751  10.3265 
+        sobel:core/acc#3.itm                                                                                                                          0.0000  10.3265 
+        sobel:core/FRAME:slc#5                                                                                                                        0.0000  10.3265 
+        sobel:core/FRAME:slc#5.itm                                                                                                                    0.0000  10.3265 
+        sobel:core/FRAME:acc#18                          mgc_add_2_1_1_1_3                                                                            0.4952  10.8217 
+        sobel:core/FRAME:acc#18.itm                                                                                                                   0.0000  10.8217 
+        sobel:core/FRAME:acc#20                          mgc_add_3_0_3_1_4                                                                            0.5984  11.4202 
+        sobel:core/FRAME:acc#20.itm                                                                                                                   0.0000  11.4202 
+        sobel:core/FRAME:acc#21                          mgc_add_4_0_4_1_6                                                                            0.5286  11.9487 
+        sobel:core/FRAME:acc#21.itm                                                                                                                   0.0000  11.9487 
+        sobel:core/FRAME:acc#22                          mgc_add_9_0_6_1_10                                                                           1.0764  13.0252 
+        sobel:core/FRAME:acc#22.cse                                                                                                                   0.0000  13.0252 
+        sobel:core/FRAME:acc#5                           mgc_add_10_0_10_1_11                                                                         1.1389  14.1641 
+        sobel:core/FRAME:acc#5.psp.sva                                                                                                                0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4                                                                                                         0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm                                                                                                     0.0000  14.1641 
+        sobel:core/conc#59                                                                                                                            0.0000  14.1641 
+        sobel:core/conc#59.itm                                                                                                                        0.0000  14.1641 
+        sobel:core/FRAME:or                              mgc_or_10_2                                                                                  0.2679  14.4320 
+        sobel:core/FRAME:or.itm                                                                                                                       0.0000  14.4320 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)        mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  14.4320 
+                                                                                                                                                                      
+      6                                                  sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   sobel:core/reg(vout:rsc:mgc_out_stdreg.d)   14.4320 5.5680  
+                                                                                                                                                                      
+        Instance                                         Component                                                                                    Delta   Delay   
+        --------                                         ---------                                                                                    -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2).sg2).itm                                                                                                     0.0000  0.0000  
+        sobel:core/conc                                                                                                                               0.0000  0.0000  
+        sobel:core/conc.itm                                                                                                                           0.0000  0.0000  
+        sobel:core/ACC1:acc#36                           mgc_add_11_1_11_1_12                                                                         1.2059  1.2059  
+        sobel:core/ACC1:acc#36.itm                                                                                                                    0.0000  1.2059  
+        sobel:core/ACC1:slc#3                                                                                                                         0.0000  1.2059  
+        sobel:core/ACC1:slc#3.itm                                                                                                                     0.0000  1.2059  
+        sobel:core/ACC1:acc#41                           mgc_add_11_1_11_1_12                                                                         1.2059  2.4119  
+        sobel:core/ACC1:acc#41.itm                                                                                                                    0.0000  2.4119  
+        sobel:core/ACC1:acc#43                           mgc_add_12_1_12_1_13                                                                         1.2718  3.6837  
+        sobel:core/ACC1:acc#43.itm                                                                                                                    0.0000  3.6837  
+        sobel:core/ACC1:acc                              mgc_add_13_1_12_1_14                                                                         1.3384  5.0221  
+        sobel:core/ACC1:acc.itm                                                                                                                       0.0000  5.0221  
+        sobel:core/ACC1:slc                                                                                                                           0.0000  5.0221  
+        sobel:core/ACC1:slc.psp.sva                                                                                                                   0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6                                                                                                            0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6.itm                                                                                                        0.0000  5.0221  
+        sobel:core/FRAME:acc#31                          mgc_add_1_0_1_0_2                                                                            0.5058  5.5278  
+        sobel:core/FRAME:acc#31.itm                                                                                                                   0.0000  5.5278  
+        sobel:core/FRAME:conc#29                                                                                                                      0.0000  5.5278  
+        sobel:core/FRAME:conc#29.itm                                                                                                                  0.0000  5.5278  
+        sobel:core/FRAME:acc#11                          mgc_add_4_0_4_1_6                                                                            0.5286  6.0564  
+        sobel:core/FRAME:acc#11.itm                                                                                                                   0.0000  6.0564  
+        sobel:core/FRAME:acc#13                          mgc_add_5_0_5_1_6                                                                            0.7751  6.8315  
+        sobel:core/FRAME:acc#13.itm                                                                                                                   0.0000  6.8315  
+        sobel:core/FRAME:acc#14                          mgc_add_6_0_6_1_7                                                                            0.8537  7.6852  
+        sobel:core/FRAME:acc#14.itm                                                                                                                   0.0000  7.6852  
+        sobel:core/acc                                   mgc_add_7_0_7_0_7                                                                            1.0910  8.7763  
+        sobel:core/acc.imod.sva                                                                                                                       0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#4                                                                                                                0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#4.itm                                                                                                            0.0000  8.7763  
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_5_1_6                                                                            0.7751  9.5514  
+        sobel:core/FRAME:acc#16.itm                                                                                                                   0.0000  9.5514  
+        sobel:core/acc#3                                 mgc_add_5_0_5_1_6                                                                            0.7751  10.3265 
+        sobel:core/acc#3.itm                                                                                                                          0.0000  10.3265 
+        sobel:core/FRAME:slc#5                                                                                                                        0.0000  10.3265 
+        sobel:core/FRAME:slc#5.itm                                                                                                                    0.0000  10.3265 
+        sobel:core/FRAME:acc#18                          mgc_add_2_1_1_1_3                                                                            0.4952  10.8217 
+        sobel:core/FRAME:acc#18.itm                                                                                                                   0.0000  10.8217 
+        sobel:core/FRAME:acc#20                          mgc_add_3_0_3_1_4                                                                            0.5984  11.4202 
+        sobel:core/FRAME:acc#20.itm                                                                                                                   0.0000  11.4202 
+        sobel:core/FRAME:acc#21                          mgc_add_4_0_4_1_6                                                                            0.5286  11.9487 
+        sobel:core/FRAME:acc#21.itm                                                                                                                   0.0000  11.9487 
+        sobel:core/FRAME:acc#22                          mgc_add_9_0_6_1_10                                                                           1.0764  13.0252 
+        sobel:core/FRAME:acc#22.cse                                                                                                                   0.0000  13.0252 
+        sobel:core/FRAME:acc#5                           mgc_add_10_0_10_1_11                                                                         1.1389  14.1641 
+        sobel:core/FRAME:acc#5.psp.sva                                                                                                                0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4                                                                                                         0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm                                                                                                     0.0000  14.1641 
+        sobel:core/conc#59                                                                                                                            0.0000  14.1641 
+        sobel:core/conc#59.itm                                                                                                                        0.0000  14.1641 
+        sobel:core/FRAME:or                              mgc_or_10_2                                                                                  0.2679  14.4320 
+        sobel:core/FRAME:or.itm                                                                                                                       0.0000  14.4320 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)        mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  14.4320 
+                                                                                                                                                                      
+      7                                                  sobel:core/reg(ACC1:slc(regs.regs(2)#1)#1.itm)   sobel:core/reg(vout:rsc:mgc_out_stdreg.d)   14.4320 5.5680  
+                                                                                                                                                                      
+        Instance                                         Component                                                                                    Delta   Delay   
+        --------                                         ---------                                                                                    -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2)#1)#1.itm)   mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm                                                                                                     0.0000  0.0000  
+        sobel:core/ACC1:not#9                            mgc_not_10                                                                                   0.0000  0.0000  
+        sobel:core/ACC1:not#9.itm                                                                                                                     0.0000  0.0000  
+        sobel:core/conc#53                                                                                                                            0.0000  0.0000  
+        sobel:core/conc#53.itm                                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#34                           mgc_add_11_1_11_1_12                                                                         1.2059  1.2059  
+        sobel:core/ACC1:acc#34.itm                                                                                                                    0.0000  1.2059  
+        sobel:core/ACC1:slc#1                                                                                                                         0.0000  1.2059  
+        sobel:core/ACC1:slc#1.itm                                                                                                                     0.0000  1.2059  
+        sobel:core/ACC1:acc#40                           mgc_add_11_1_11_1_12                                                                         1.2059  2.4119  
+        sobel:core/ACC1:acc#40.itm                                                                                                                    0.0000  2.4119  
+        sobel:core/ACC1:acc#43                           mgc_add_12_1_12_1_13                                                                         1.2718  3.6837  
+        sobel:core/ACC1:acc#43.itm                                                                                                                    0.0000  3.6837  
+        sobel:core/ACC1:acc                              mgc_add_13_1_12_1_14                                                                         1.3384  5.0221  
+        sobel:core/ACC1:acc.itm                                                                                                                       0.0000  5.0221  
+        sobel:core/ACC1:slc                                                                                                                           0.0000  5.0221  
+        sobel:core/ACC1:slc.psp.sva                                                                                                                   0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6                                                                                                            0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6.itm                                                                                                        0.0000  5.0221  
+        sobel:core/FRAME:acc#31                          mgc_add_1_0_1_0_2                                                                            0.5058  5.5278  
+        sobel:core/FRAME:acc#31.itm                                                                                                                   0.0000  5.5278  
+        sobel:core/FRAME:conc#29                                                                                                                      0.0000  5.5278  
+        sobel:core/FRAME:conc#29.itm                                                                                                                  0.0000  5.5278  
+        sobel:core/FRAME:acc#11                          mgc_add_4_0_4_1_6                                                                            0.5286  6.0564  
+        sobel:core/FRAME:acc#11.itm                                                                                                                   0.0000  6.0564  
+        sobel:core/FRAME:acc#13                          mgc_add_5_0_5_1_6                                                                            0.7751  6.8315  
+        sobel:core/FRAME:acc#13.itm                                                                                                                   0.0000  6.8315  
+        sobel:core/FRAME:acc#14                          mgc_add_6_0_6_1_7                                                                            0.8537  7.6852  
+        sobel:core/FRAME:acc#14.itm                                                                                                                   0.0000  7.6852  
+        sobel:core/acc                                   mgc_add_7_0_7_0_7                                                                            1.0910  8.7763  
+        sobel:core/acc.imod.sva                                                                                                                       0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#10                                                                                                               0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#10.itm                                                                                                           0.0000  8.7763  
+        sobel:core/conc#55                                                                                                                            0.0000  8.7763  
+        sobel:core/conc#55.itm                                                                                                                        0.0000  8.7763  
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_5_1_6                                                                            0.7751  9.5514  
+        sobel:core/FRAME:acc#16.itm                                                                                                                   0.0000  9.5514  
+        sobel:core/acc#3                                 mgc_add_5_0_5_1_6                                                                            0.7751  10.3265 
+        sobel:core/acc#3.itm                                                                                                                          0.0000  10.3265 
+        sobel:core/FRAME:slc#5                                                                                                                        0.0000  10.3265 
+        sobel:core/FRAME:slc#5.itm                                                                                                                    0.0000  10.3265 
+        sobel:core/FRAME:acc#18                          mgc_add_2_1_1_1_3                                                                            0.4952  10.8217 
+        sobel:core/FRAME:acc#18.itm                                                                                                                   0.0000  10.8217 
+        sobel:core/FRAME:acc#20                          mgc_add_3_0_3_1_4                                                                            0.5984  11.4202 
+        sobel:core/FRAME:acc#20.itm                                                                                                                   0.0000  11.4202 
+        sobel:core/FRAME:acc#21                          mgc_add_4_0_4_1_6                                                                            0.5286  11.9487 
+        sobel:core/FRAME:acc#21.itm                                                                                                                   0.0000  11.9487 
+        sobel:core/FRAME:acc#22                          mgc_add_9_0_6_1_10                                                                           1.0764  13.0252 
+        sobel:core/FRAME:acc#22.cse                                                                                                                   0.0000  13.0252 
+        sobel:core/FRAME:acc#5                           mgc_add_10_0_10_1_11                                                                         1.1389  14.1641 
+        sobel:core/FRAME:acc#5.psp.sva                                                                                                                0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4                                                                                                         0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm                                                                                                     0.0000  14.1641 
+        sobel:core/conc#59                                                                                                                            0.0000  14.1641 
+        sobel:core/conc#59.itm                                                                                                                        0.0000  14.1641 
+        sobel:core/FRAME:or                              mgc_or_10_2                                                                                  0.2679  14.4320 
+        sobel:core/FRAME:or.itm                                                                                                                       0.0000  14.4320 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)        mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  14.4320 
+                                                                                                                                                                      
+      8                                                  sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   sobel:core/reg(vout:rsc:mgc_out_stdreg.d)   14.4320 5.5680  
+                                                                                                                                                                      
+        Instance                                         Component                                                                                    Delta   Delay   
+        --------                                         ---------                                                                                    -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2).sg2).itm                                                                                                     0.0000  0.0000  
+        sobel:core/conc                                                                                                                               0.0000  0.0000  
+        sobel:core/conc.itm                                                                                                                           0.0000  0.0000  
+        sobel:core/ACC1:acc#36                           mgc_add_11_1_11_1_12                                                                         1.2059  1.2059  
+        sobel:core/ACC1:acc#36.itm                                                                                                                    0.0000  1.2059  
+        sobel:core/ACC1:slc#3                                                                                                                         0.0000  1.2059  
+        sobel:core/ACC1:slc#3.itm                                                                                                                     0.0000  1.2059  
+        sobel:core/ACC1:acc#41                           mgc_add_11_1_11_1_12                                                                         1.2059  2.4119  
+        sobel:core/ACC1:acc#41.itm                                                                                                                    0.0000  2.4119  
+        sobel:core/ACC1:acc#43                           mgc_add_12_1_12_1_13                                                                         1.2718  3.6837  
+        sobel:core/ACC1:acc#43.itm                                                                                                                    0.0000  3.6837  
+        sobel:core/ACC1:acc                              mgc_add_13_1_12_1_14                                                                         1.3384  5.0221  
+        sobel:core/ACC1:acc.itm                                                                                                                       0.0000  5.0221  
+        sobel:core/ACC1:slc                                                                                                                           0.0000  5.0221  
+        sobel:core/ACC1:slc.psp.sva                                                                                                                   0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6                                                                                                            0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6.itm                                                                                                        0.0000  5.0221  
+        sobel:core/FRAME:acc#31                          mgc_add_1_0_1_0_2                                                                            0.5058  5.5278  
+        sobel:core/FRAME:acc#31.itm                                                                                                                   0.0000  5.5278  
+        sobel:core/FRAME:conc#29                                                                                                                      0.0000  5.5278  
+        sobel:core/FRAME:conc#29.itm                                                                                                                  0.0000  5.5278  
+        sobel:core/FRAME:acc#11                          mgc_add_4_0_4_1_6                                                                            0.5286  6.0564  
+        sobel:core/FRAME:acc#11.itm                                                                                                                   0.0000  6.0564  
+        sobel:core/FRAME:acc#13                          mgc_add_5_0_5_1_6                                                                            0.7751  6.8315  
+        sobel:core/FRAME:acc#13.itm                                                                                                                   0.0000  6.8315  
+        sobel:core/FRAME:acc#14                          mgc_add_6_0_6_1_7                                                                            0.8537  7.6852  
+        sobel:core/FRAME:acc#14.itm                                                                                                                   0.0000  7.6852  
+        sobel:core/acc                                   mgc_add_7_0_7_0_7                                                                            1.0910  8.7763  
+        sobel:core/acc.imod.sva                                                                                                                       0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#15                                                                                                               0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#15.itm                                                                                                           0.0000  8.7763  
+        sobel:core/conc#55                                                                                                                            0.0000  8.7763  
+        sobel:core/conc#55.itm                                                                                                                        0.0000  8.7763  
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_5_1_6                                                                            0.7751  9.5514  
+        sobel:core/FRAME:acc#16.itm                                                                                                                   0.0000  9.5514  
+        sobel:core/acc#3                                 mgc_add_5_0_5_1_6                                                                            0.7751  10.3265 
+        sobel:core/acc#3.itm                                                                                                                          0.0000  10.3265 
+        sobel:core/FRAME:slc#5                                                                                                                        0.0000  10.3265 
+        sobel:core/FRAME:slc#5.itm                                                                                                                    0.0000  10.3265 
+        sobel:core/FRAME:acc#18                          mgc_add_2_1_1_1_3                                                                            0.4952  10.8217 
+        sobel:core/FRAME:acc#18.itm                                                                                                                   0.0000  10.8217 
+        sobel:core/FRAME:acc#20                          mgc_add_3_0_3_1_4                                                                            0.5984  11.4202 
+        sobel:core/FRAME:acc#20.itm                                                                                                                   0.0000  11.4202 
+        sobel:core/FRAME:acc#21                          mgc_add_4_0_4_1_6                                                                            0.5286  11.9487 
+        sobel:core/FRAME:acc#21.itm                                                                                                                   0.0000  11.9487 
+        sobel:core/FRAME:acc#22                          mgc_add_9_0_6_1_10                                                                           1.0764  13.0252 
+        sobel:core/FRAME:acc#22.cse                                                                                                                   0.0000  13.0252 
+        sobel:core/FRAME:acc#5                           mgc_add_10_0_10_1_11                                                                         1.1389  14.1641 
+        sobel:core/FRAME:acc#5.psp.sva                                                                                                                0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4                                                                                                         0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm                                                                                                     0.0000  14.1641 
+        sobel:core/conc#59                                                                                                                            0.0000  14.1641 
+        sobel:core/conc#59.itm                                                                                                                        0.0000  14.1641 
+        sobel:core/FRAME:or                              mgc_or_10_2                                                                                  0.2679  14.4320 
+        sobel:core/FRAME:or.itm                                                                                                                       0.0000  14.4320 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)        mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  14.4320 
+                                                                                                                                                                      
+      9                                                  sobel:core/reg(ACC1:slc(regs.regs(2)#1)#2.itm)   sobel:core/reg(vout:rsc:mgc_out_stdreg.d)   14.4320 5.5680  
+                                                                                                                                                                      
+        Instance                                         Component                                                                                    Delta   Delay   
+        --------                                         ---------                                                                                    -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2)#1)#2.itm)   mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm                                                                                                     0.0000  0.0000  
+        sobel:core/ACC1:not#10                           mgc_not_10                                                                                   0.0000  0.0000  
+        sobel:core/ACC1:not#10.itm                                                                                                                    0.0000  0.0000  
+        sobel:core/conc#54                                                                                                                            0.0000  0.0000  
+        sobel:core/conc#54.itm                                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#34                           mgc_add_11_1_11_1_12                                                                         1.2059  1.2059  
+        sobel:core/ACC1:acc#34.itm                                                                                                                    0.0000  1.2059  
+        sobel:core/ACC1:slc#1                                                                                                                         0.0000  1.2059  
+        sobel:core/ACC1:slc#1.itm                                                                                                                     0.0000  1.2059  
+        sobel:core/ACC1:acc#40                           mgc_add_11_1_11_1_12                                                                         1.2059  2.4119  
+        sobel:core/ACC1:acc#40.itm                                                                                                                    0.0000  2.4119  
+        sobel:core/ACC1:acc#43                           mgc_add_12_1_12_1_13                                                                         1.2718  3.6837  
+        sobel:core/ACC1:acc#43.itm                                                                                                                    0.0000  3.6837  
+        sobel:core/ACC1:acc                              mgc_add_13_1_12_1_14                                                                         1.3384  5.0221  
+        sobel:core/ACC1:acc.itm                                                                                                                       0.0000  5.0221  
+        sobel:core/ACC1:slc                                                                                                                           0.0000  5.0221  
+        sobel:core/ACC1:slc.psp.sva                                                                                                                   0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6                                                                                                            0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#6.itm                                                                                                        0.0000  5.0221  
+        sobel:core/FRAME:acc#31                          mgc_add_1_0_1_0_2                                                                            0.5058  5.5278  
+        sobel:core/FRAME:acc#31.itm                                                                                                                   0.0000  5.5278  
+        sobel:core/FRAME:conc#29                                                                                                                      0.0000  5.5278  
+        sobel:core/FRAME:conc#29.itm                                                                                                                  0.0000  5.5278  
+        sobel:core/FRAME:acc#11                          mgc_add_4_0_4_1_6                                                                            0.5286  6.0564  
+        sobel:core/FRAME:acc#11.itm                                                                                                                   0.0000  6.0564  
+        sobel:core/FRAME:acc#13                          mgc_add_5_0_5_1_6                                                                            0.7751  6.8315  
+        sobel:core/FRAME:acc#13.itm                                                                                                                   0.0000  6.8315  
+        sobel:core/FRAME:acc#14                          mgc_add_6_0_6_1_7                                                                            0.8537  7.6852  
+        sobel:core/FRAME:acc#14.itm                                                                                                                   0.0000  7.6852  
+        sobel:core/acc                                   mgc_add_7_0_7_0_7                                                                            1.0910  8.7763  
+        sobel:core/acc.imod.sva                                                                                                                       0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#10                                                                                                               0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#10.itm                                                                                                           0.0000  8.7763  
+        sobel:core/conc#55                                                                                                                            0.0000  8.7763  
+        sobel:core/conc#55.itm                                                                                                                        0.0000  8.7763  
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_5_1_6                                                                            0.7751  9.5514  
+        sobel:core/FRAME:acc#16.itm                                                                                                                   0.0000  9.5514  
+        sobel:core/acc#3                                 mgc_add_5_0_5_1_6                                                                            0.7751  10.3265 
+        sobel:core/acc#3.itm                                                                                                                          0.0000  10.3265 
+        sobel:core/FRAME:slc#5                                                                                                                        0.0000  10.3265 
+        sobel:core/FRAME:slc#5.itm                                                                                                                    0.0000  10.3265 
+        sobel:core/FRAME:acc#18                          mgc_add_2_1_1_1_3                                                                            0.4952  10.8217 
+        sobel:core/FRAME:acc#18.itm                                                                                                                   0.0000  10.8217 
+        sobel:core/FRAME:acc#20                          mgc_add_3_0_3_1_4                                                                            0.5984  11.4202 
+        sobel:core/FRAME:acc#20.itm                                                                                                                   0.0000  11.4202 
+        sobel:core/FRAME:acc#21                          mgc_add_4_0_4_1_6                                                                            0.5286  11.9487 
+        sobel:core/FRAME:acc#21.itm                                                                                                                   0.0000  11.9487 
+        sobel:core/FRAME:acc#22                          mgc_add_9_0_6_1_10                                                                           1.0764  13.0252 
+        sobel:core/FRAME:acc#22.cse                                                                                                                   0.0000  13.0252 
+        sobel:core/FRAME:acc#5                           mgc_add_10_0_10_1_11                                                                         1.1389  14.1641 
+        sobel:core/FRAME:acc#5.psp.sva                                                                                                                0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4                                                                                                         0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm                                                                                                     0.0000  14.1641 
+        sobel:core/conc#59                                                                                                                            0.0000  14.1641 
+        sobel:core/conc#59.itm                                                                                                                        0.0000  14.1641 
+        sobel:core/FRAME:or                              mgc_or_10_2                                                                                  0.2679  14.4320 
+        sobel:core/FRAME:or.itm                                                                                                                       0.0000  14.4320 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)        mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  14.4320 
+                                                                                                                                                                      
+      10                                                 sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   sobel:core/reg(vout:rsc:mgc_out_stdreg.d)   14.4320 5.5680  
+                                                                                                                                                                      
+        Instance                                         Component                                                                                    Delta   Delay   
+        --------                                         ---------                                                                                    -----   -----   
+        sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  0.0000  
+        sobel:core/ACC1:slc(regs.regs(2).sg2).itm                                                                                                     0.0000  0.0000  
+        sobel:core/conc                                                                                                                               0.0000  0.0000  
+        sobel:core/conc.itm                                                                                                                           0.0000  0.0000  
+        sobel:core/ACC1:acc#36                           mgc_add_11_1_11_1_12                                                                         1.2059  1.2059  
+        sobel:core/ACC1:acc#36.itm                                                                                                                    0.0000  1.2059  
+        sobel:core/ACC1:slc#3                                                                                                                         0.0000  1.2059  
+        sobel:core/ACC1:slc#3.itm                                                                                                                     0.0000  1.2059  
+        sobel:core/ACC1:acc#41                           mgc_add_11_1_11_1_12                                                                         1.2059  2.4119  
+        sobel:core/ACC1:acc#41.itm                                                                                                                    0.0000  2.4119  
+        sobel:core/ACC1:acc#43                           mgc_add_12_1_12_1_13                                                                         1.2718  3.6837  
+        sobel:core/ACC1:acc#43.itm                                                                                                                    0.0000  3.6837  
+        sobel:core/ACC1:acc                              mgc_add_13_1_12_1_14                                                                         1.3384  5.0221  
+        sobel:core/ACC1:acc.itm                                                                                                                       0.0000  5.0221  
+        sobel:core/ACC1:slc                                                                                                                           0.0000  5.0221  
+        sobel:core/ACC1:slc.psp.sva                                                                                                                   0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#15                                                                                                           0.0000  5.0221  
+        sobel:core/slc(ACC1:slc.psp.sva)#15.itm                                                                                                       0.0000  5.0221  
+        sobel:core/FRAME:not#19                          mgc_not_1                                                                                    0.0000  5.0221  
+        sobel:core/FRAME:not#19.itm                                                                                                                   0.0000  5.0221  
+        sobel:core/FRAME:acc#31                          mgc_add_1_0_1_0_2                                                                            0.5058  5.5278  
+        sobel:core/FRAME:acc#31.itm                                                                                                                   0.0000  5.5278  
+        sobel:core/FRAME:conc#29                                                                                                                      0.0000  5.5278  
+        sobel:core/FRAME:conc#29.itm                                                                                                                  0.0000  5.5278  
+        sobel:core/FRAME:acc#11                          mgc_add_4_0_4_1_6                                                                            0.5286  6.0564  
+        sobel:core/FRAME:acc#11.itm                                                                                                                   0.0000  6.0564  
+        sobel:core/FRAME:acc#13                          mgc_add_5_0_5_1_6                                                                            0.7751  6.8315  
+        sobel:core/FRAME:acc#13.itm                                                                                                                   0.0000  6.8315  
+        sobel:core/FRAME:acc#14                          mgc_add_6_0_6_1_7                                                                            0.8537  7.6852  
+        sobel:core/FRAME:acc#14.itm                                                                                                                   0.0000  7.6852  
+        sobel:core/acc                                   mgc_add_7_0_7_0_7                                                                            1.0910  8.7763  
+        sobel:core/acc.imod.sva                                                                                                                       0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#15                                                                                                               0.0000  8.7763  
+        sobel:core/slc(acc.imod.sva)#15.itm                                                                                                           0.0000  8.7763  
+        sobel:core/conc#55                                                                                                                            0.0000  8.7763  
+        sobel:core/conc#55.itm                                                                                                                        0.0000  8.7763  
+        sobel:core/FRAME:acc#16                          mgc_add_5_0_5_1_6                                                                            0.7751  9.5514  
+        sobel:core/FRAME:acc#16.itm                                                                                                                   0.0000  9.5514  
+        sobel:core/acc#3                                 mgc_add_5_0_5_1_6                                                                            0.7751  10.3265 
+        sobel:core/acc#3.itm                                                                                                                          0.0000  10.3265 
+        sobel:core/FRAME:slc#5                                                                                                                        0.0000  10.3265 
+        sobel:core/FRAME:slc#5.itm                                                                                                                    0.0000  10.3265 
+        sobel:core/FRAME:acc#18                          mgc_add_2_1_1_1_3                                                                            0.4952  10.8217 
+        sobel:core/FRAME:acc#18.itm                                                                                                                   0.0000  10.8217 
+        sobel:core/FRAME:acc#20                          mgc_add_3_0_3_1_4                                                                            0.5984  11.4202 
+        sobel:core/FRAME:acc#20.itm                                                                                                                   0.0000  11.4202 
+        sobel:core/FRAME:acc#21                          mgc_add_4_0_4_1_6                                                                            0.5286  11.9487 
+        sobel:core/FRAME:acc#21.itm                                                                                                                   0.0000  11.9487 
+        sobel:core/FRAME:acc#22                          mgc_add_9_0_6_1_10                                                                           1.0764  13.0252 
+        sobel:core/FRAME:acc#22.cse                                                                                                                   0.0000  13.0252 
+        sobel:core/FRAME:acc#5                           mgc_add_10_0_10_1_11                                                                         1.1389  14.1641 
+        sobel:core/FRAME:acc#5.psp.sva                                                                                                                0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4                                                                                                         0.0000  14.1641 
+        sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm                                                                                                     0.0000  14.1641 
+        sobel:core/conc#59                                                                                                                            0.0000  14.1641 
+        sobel:core/conc#59.itm                                                                                                                        0.0000  14.1641 
+        sobel:core/FRAME:or                              mgc_or_10_2                                                                                  0.2679  14.4320 
+        sobel:core/FRAME:or.itm                                                                                                                       0.0000  14.4320 
+        sobel:core/reg(vout:rsc:mgc_out_stdreg.d)        mgc_reg_pos_10_1_0_0_0_1_1                                                                   0.0000  14.4320 
+                                                                                                                                                                      
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                         Port                              Slack (Delay) Messages 
+      ------------------------------------------------ ------------------------------- ------- ------- --------
+      sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)   slc(regs.regs(1).sg2.sva)#2.itm 20.0000  0.0000          
+      sobel:core/reg(ACC1:slc(regs.regs(2).sg2)#1.itm) slc(regs.regs(1).sg2.sva)#1.itm 20.0000  0.0000          
+      sobel:core/reg(ACC1:slc(regs.regs(2).sg2)#2.itm) slc(regs.regs(1).sg2.sva).itm   20.0000  0.0000          
+      sobel:core/reg(ACC1:slc(regs.regs(2)#1).itm)     slc(regs.regs(1)#1.sva)#2.itm   20.0000  0.0000          
+      sobel:core/reg(ACC1:slc(regs.regs(2)#1)#1.itm)   slc(regs.regs(1)#1.sva)#1.itm   20.0000  0.0000          
+      sobel:core/reg(ACC1:slc(regs.regs(2)#1)#2.itm)   slc(regs.regs(1)#1.sva).itm     20.0000  0.0000          
+      sobel:core/reg(regs.regs(1)#1.sva)               slc(regs.regs(0).sva#8).itm     20.0000  0.0000          
+      sobel:core/reg(regs.regs(1).sg2.sva)             slc(regs.regs(0).sva#7).itm     20.0000  0.0000          
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)        FRAME:or.itm                     5.5680 14.4320          
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2      FRAME:or#3.itm                   5.5680 14.4320          
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3      slc(FRAME:acc#5.psp.sva)#3.itm   5.8359 14.1641          
+      sobel                                            vout:rsc.z                      20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                   14     1 
+    -                   13     1 
+    -                   12     6 
+    -                   11     5 
+    -                   10     1 
+    -                    8     1 
+    -                    7     2 
+    -                    6     6 
+    -                    4     1 
+    -                    3     3 
+    -                    2     2 
+    mul                          
+    -                    9     1 
+    not                          
+    -                   10     3 
+    -                    3     1 
+    -                    2     1 
+    -                    1     1 
+    or                           
+    -                    2     2 
+    read_port                    
+    -                   90     1 
+    reg                          
+    -                   30     2 
+    -                   10     8 
+    -                    6     1 
+    write_port                   
+    -                   30     1 
+    
+  End of Report
diff --git a/Sobel/sobel.v5/rtl.v b/Sobel/sobel.v5/rtl.v
new file mode 100644
index 0000000..89f6e2b
--- /dev/null
+++ b/Sobel/sobel.v5/rtl.v
@@ -0,0 +1,452 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:36:28 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [29:0] regs_regs_1_1_sva;
+  reg [29:0] regs_regs_1_sg2_sva;
+  reg [9:0] ACC1_slc_regs_regs_2_sg2_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_sg2_1_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_sg2_2_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_1_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_1_1_itm;
+  reg [9:0] ACC1_slc_regs_regs_2_1_2_itm;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  wire [10:0] nl_reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  reg [5:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_2;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_3;
+  wire [9:0] FRAME_acc_22_cse;
+  wire [10:0] nl_FRAME_acc_22_cse;
+  wire [10:0] FRAME_acc_5_psp_sva;
+  wire [11:0] nl_FRAME_acc_5_psp_sva;
+  wire [6:0] acc_imod_sva;
+  wire [8:0] nl_acc_imod_sva;
+  wire [13:0] ACC1_acc_itm;
+  wire [14:0] nl_ACC1_acc_itm;
+  wire [7:0] FRAME_acc_33_itm;
+  wire [8:0] nl_FRAME_acc_33_itm;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign vout_rsc_mgc_out_stdreg_d = {reg_vout_rsc_mgc_out_stdreg_d_tmp , (reg_vout_rsc_mgc_out_stdreg_d_tmp_3[9:6])
+      , reg_vout_rsc_mgc_out_stdreg_d_tmp_2 , reg_vout_rsc_mgc_out_stdreg_d_tmp_3};
+  assign nl_ACC1_acc_itm = conv_s2s_13_14(conv_s2s_12_13(conv_s2s_11_12(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[79:70])
+      + conv_s2s_10_11(vin_rsc_mgc_in_wire_d[89:80])) + conv_s2s_11_12(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_sg2_itm
+      , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_sg2_1_itm , 1'b1}))))) + conv_s2s_12_13(conv_s2s_11_12(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_sg2_2_itm
+      , 1'b1}) + conv_s2s_11_12({(~ ACC1_slc_regs_regs_2_1_itm) , 1'b1})))) + conv_s2s_11_12(readslicef_12_11_1((conv_s2s_11_12({(~
+      ACC1_slc_regs_regs_2_1_1_itm) , 1'b1}) + conv_s2s_11_12({(~ ACC1_slc_regs_regs_2_1_2_itm)
+      , 1'b1})))))) + conv_s2s_12_14(conv_s2s_11_12(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[9:0])
+      + conv_s2s_10_11(vin_rsc_mgc_in_wire_d[19:10])) + conv_s2s_11_12(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[29:20])
+      + conv_s2s_10_11(vin_rsc_mgc_in_wire_d[69:60])));
+  assign ACC1_acc_itm = nl_ACC1_acc_itm[13:0];
+  assign nl_FRAME_acc_22_cse = conv_u2s_9_11(conv_u2s_18_10(conv_u2u_4_9(ACC1_acc_itm[13:10])
+      * 9'b10011)) + conv_s2s_6_10(conv_s2s_4_6(conv_u2s_3_4(conv_u2u_2_3(conv_u2u_1_2(ACC1_acc_itm[5])
+      + conv_u2u_1_2(acc_imod_sva[4])) + conv_u2u_2_3(ACC1_acc_itm[9:8])) + conv_s2s_3_4(conv_s2s_2_3(acc_imod_sva[6:5])
+      + conv_s2s_1_3(readslicef_5_1_4(((({(acc_imod_sva[4]) , 1'b0 , (acc_imod_sva[4])
+      , 1'b0 , (acc_imod_sva[4])}) + conv_u2s_4_5(acc_imod_sva[3:0])) + ({(conv_s2u_2_3(acc_imod_sva[6:5])
+      + conv_s2u_1_3(acc_imod_sva[6])) , (acc_imod_sva[6:5])})))))) + conv_u2s_4_6(ACC1_acc_itm[9:6]));
+  assign FRAME_acc_22_cse = nl_FRAME_acc_22_cse[9:0];
+  assign nl_FRAME_acc_5_psp_sva = conv_u2u_10_11({(ACC1_acc_itm[13]) , (ACC1_acc_itm[13])
+      , FRAME_acc_33_itm}) + conv_s2u_10_11(FRAME_acc_22_cse);
+  assign FRAME_acc_5_psp_sva = nl_FRAME_acc_5_psp_sva[10:0];
+  assign nl_acc_imod_sva = (conv_s2s_6_7(conv_u2s_5_6(conv_u2u_4_5({(ACC1_acc_itm[7:6])
+      , (ACC1_acc_itm[7:6])}) + conv_u2u_3_5({(conv_u2u_1_2(ACC1_acc_itm[9]) + conv_u2u_1_2(~
+      (ACC1_acc_itm[13]))) , (ACC1_acc_itm[8])})) + conv_s2s_5_6({(ACC1_acc_itm[5])
+      , 1'b0 , (ACC1_acc_itm[5]) , 1'b0 , (ACC1_acc_itm[5])})) + conv_u2s_6_7(conv_u2u_5_6({(~
+      (ACC1_acc_itm[9:8])) , (~ (ACC1_acc_itm[12:10]))}) + conv_u2u_4_6(ACC1_acc_itm[4:1])))
+      + 7'b1011111;
+  assign acc_imod_sva = nl_acc_imod_sva[6:0];
+  assign nl_FRAME_acc_33_itm = conv_u2u_7_8({(ACC1_acc_itm[13]) , 1'b0 , (signext_5_1(ACC1_acc_itm[13]))})
+      + conv_u2u_6_8({(ACC1_acc_itm[13]) , 1'b0 , (signext_4_1(ACC1_acc_itm[13]))});
+  assign FRAME_acc_33_itm = nl_FRAME_acc_33_itm[7:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      ACC1_slc_regs_regs_2_sg2_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_sg2_1_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_sg2_2_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_1_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_1_1_itm <= 10'b0;
+      ACC1_slc_regs_regs_2_1_2_itm <= 10'b0;
+      regs_regs_1_1_sva <= 30'b0;
+      regs_regs_1_sg2_sva <= 30'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= 6'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= 10'b0;
+    end
+    else begin
+      if ( en ) begin
+        ACC1_slc_regs_regs_2_sg2_itm <= regs_regs_1_sg2_sva[9:0];
+        ACC1_slc_regs_regs_2_sg2_1_itm <= regs_regs_1_sg2_sva[19:10];
+        ACC1_slc_regs_regs_2_sg2_2_itm <= regs_regs_1_sg2_sva[29:20];
+        ACC1_slc_regs_regs_2_1_itm <= regs_regs_1_1_sva[9:0];
+        ACC1_slc_regs_regs_2_1_1_itm <= regs_regs_1_1_sva[19:10];
+        ACC1_slc_regs_regs_2_1_2_itm <= regs_regs_1_1_sva[29:20];
+        regs_regs_1_1_sva <= vin_rsc_mgc_in_wire_d[29:0];
+        regs_regs_1_sg2_sva <= vin_rsc_mgc_in_wire_d[89:60];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp <= (({(ACC1_acc_itm[13]) , (ACC1_acc_itm[13])
+            , FRAME_acc_33_itm}) + FRAME_acc_22_cse) | ({9'b0 , (FRAME_acc_5_psp_sva[10])});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= (FRAME_acc_5_psp_sva[5:0]) | ({5'b0
+            , (FRAME_acc_5_psp_sva[10])});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= FRAME_acc_5_psp_sva[9:0];
+      end
+    end
+  end
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_1;
+    input [0:0] vector;
+  begin
+    signext_5_1= {{4{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [3:0] signext_4_1;
+    input [0:0] vector;
+  begin
+    signext_4_1= {{3{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_13_14 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_14 = {vector[12], vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_12_14 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_14 = {{2{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_4_9 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_9 = {{5{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_6_10 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_10 = {{4{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_s2u_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2u_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_s2u_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_6_7 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_7 = {vector[5], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v5/rtl.v.psr b/Sobel/sobel.v5/rtl.v.psr
new file mode 100644
index 0000000..373f00f
--- /dev/null
+++ b/Sobel/sobel.v5/rtl.v.psr
@@ -0,0 +1,289 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v5/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v5/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v5/rtl.v}} -format verilog
+   setup_design -design=sobel
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'sobel': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'sobel': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'sobel'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'sobel'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to vout_rsc_z(29:0)
+   report_timing -from en -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from vin_rsc_z(89:0) -to vout_rsc_z(29:0)
+   report_timing -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock clk] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock en] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'sobel'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'sobel'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v5 mapped.v]
+          puts "-- Writing mapped netlist for 'sobel' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v5 gate.v]
+          set gate_sdf [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v5 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/Sobel/sobel.v5/rtl.v.psr_timing b/Sobel/sobel.v5/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/Sobel/sobel.v5/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/Sobel/sobel.v5/rtl.v_order.txt b/Sobel/sobel.v5/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/Sobel/sobel.v5/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/Sobel/sobel.v5/rtl_mgc_ioport.v b/Sobel/sobel.v5/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v5/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v5/rtl_mgc_ioport_v2001.v b/Sobel/sobel.v5/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v5/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v5/schedule.gnt b/Sobel/sobel.v5/schedule.gnt
new file mode 100644
index 0000000..feb183a
--- /dev/null
+++ b/Sobel/sobel.v5/schedule.gnt
@@ -0,0 +1,174 @@
+set a(0-1720) {NAME FRAME:p:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-1719 XREFS 13649 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1725 {}}} SUCCS {{258 0 0-1725 {}}} CYCLES {}}
+set a(0-1721) {NAME asn(regs.regs(1)) TYPE ASSIGN PAR 0-1719 XREFS 13650 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1725 {}}} SUCCS {{258 0 0-1725 {}}} CYCLES {}}
+set a(0-1722) {NAME asn(regs.regs(1).sg2)#1 TYPE ASSIGN PAR 0-1719 XREFS 13651 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1725 {}}} SUCCS {{258 0 0-1725 {}}} CYCLES {}}
+set a(0-1723) {NAME asn(regs.regs(0))#1 TYPE ASSIGN PAR 0-1719 XREFS 13652 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1725 {}}} SUCCS {{258 0 0-1725 {}}} CYCLES {}}
+set a(0-1724) {NAME FRAME:asn(exit:FRAME) TYPE ASSIGN PAR 0-1719 XREFS 13653 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1725 {}}} SUCCS {{259 0 0-1725 {}}} CYCLES {}}
+set a(0-1726) {NAME FRAME:asn TYPE ASSIGN PAR 0-1725 XREFS 13654 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-1886 {}}} SUCCS {{259 0 0-1727 {}} {256 0 0-1886 {}}} CYCLES {}}
+set a(0-1727) {NAME FRAME:select TYPE SELECT PAR 0-1725 XREFS 13655 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{259 0 0-1726 {}}} SUCCS {} CYCLES {}}
+set a(0-1728) {NAME SHIFT:if:else:else:else:asn TYPE ASSIGN PAR 0-1725 XREFS 13656 LOC {0 1.0 0 1.0 0 1.0 2 0.08882785} PREDS {{262 0 0-1878 {}}} SUCCS {{259 0 0-1729 {}} {256 0 0-1878 {}}} CYCLES {}}
+set a(0-1729) {NAME SHIFT:if:else:else:else:slc(regs.regs(0)) TYPE READSLICE PAR 0-1725 XREFS 13657 LOC {0 1.0 0 1.0 0 1.0 2 0.08882785} PREDS {{259 0 0-1728 {}}} SUCCS {{258 0 0-1881 {}}} CYCLES {}}
+set a(0-1730) {NAME SHIFT:if:else:else:else:asn#1 TYPE ASSIGN PAR 0-1725 XREFS 13658 LOC {0 1.0 0 1.0 0 1.0 2 0.08882785} PREDS {{262 0 0-1878 {}}} SUCCS {{259 0 0-1731 {}} {256 0 0-1878 {}}} CYCLES {}}
+set a(0-1731) {NAME SHIFT:if:else:else:else:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-1725 XREFS 13659 LOC {0 1.0 0 1.0 0 1.0 2 0.08882785} PREDS {{259 0 0-1730 {}}} SUCCS {{258 0 0-1880 {}}} CYCLES {}}
+set a(0-1732) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,90) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_read(vin:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-1725 XREFS 13660 LOC {1 0.0 1 0.0930145 1 0.0930145 1 0.0930145 1 0.0930145} PREDS {} SUCCS {{259 0 0-1733 {}} {258 0 0-1734 {}} {258 0 0-1766 {}} {258 0 0-1767 {}} {258 0 0-1769 {}} {258 0 0-1770 {}} {258 0 0-1878 {}}} CYCLES {}}
+set a(0-1733) {NAME ACC1:slc(regs.regs(0))#4 TYPE READSLICE PAR 0-1725 XREFS 13661 LOC {1 0.0 1 0.0930145 1 0.0930145 1 0.0930145} PREDS {{259 0 0-1732 {}}} SUCCS {{258 0 0-1735 {}}} CYCLES {}}
+set a(0-1734) {NAME ACC1:slc(regs.regs(0))#5 TYPE READSLICE PAR 0-1725 XREFS 13662 LOC {1 0.0 1 0.0930145 1 0.0930145 1 0.0930145} PREDS {{258 0 0-1732 {}}} SUCCS {{259 0 0-1735 {}}} CYCLES {}}
+set a(0-1735) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#37 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-1725 XREFS 13663 LOC {1 0.0 1 0.0930145 1 0.0930145 1 0.16419860333641131 1 0.16419860333641131} PREDS {{258 0 0-1733 {}} {259 0 0-1734 {}}} SUCCS {{258 0 0-1744 {}}} CYCLES {}}
+set a(0-1736) {NAME ACC1:asn TYPE ASSIGN PAR 0-1725 XREFS 13664 LOC {0 1.0 0 1.0 0 1.0 1 0.08882785} PREDS {{262 0 0-1880 {}}} SUCCS {{259 0 0-1737 {}} {256 0 0-1880 {}}} CYCLES {}}
+set a(0-1737) {NAME ACC1:slc(regs.regs(2).sg2) TYPE READSLICE PAR 0-1725 XREFS 13665 LOC {0 1.0 0 1.0 0 1.0 1 0.08882785} PREDS {{259 0 0-1736 {}}} SUCCS {{259 0 0-1738 {}}} CYCLES {}}
+set a(0-1738) {NAME ACC1:conc#30 TYPE CONCATENATE PAR 0-1725 XREFS 13666 LOC {0 1.0 1 0.08882785 1 0.08882785 1 0.08882785} PREDS {{259 0 0-1737 {}}} SUCCS {{258 0 0-1742 {}}} CYCLES {}}
+set a(0-1739) {NAME ACC1:asn#4 TYPE ASSIGN PAR 0-1725 XREFS 13667 LOC {0 1.0 0 1.0 0 1.0 1 0.08882785} PREDS {{262 0 0-1880 {}}} SUCCS {{259 0 0-1740 {}} {256 0 0-1880 {}}} CYCLES {}}
+set a(0-1740) {NAME ACC1:slc(regs.regs(2).sg2)#1 TYPE READSLICE PAR 0-1725 XREFS 13668 LOC {0 1.0 0 1.0 0 1.0 1 0.08882785} PREDS {{259 0 0-1739 {}}} SUCCS {{259 0 0-1741 {}}} CYCLES {}}
+set a(0-1741) {NAME ACC1:conc#31 TYPE CONCATENATE PAR 0-1725 XREFS 13669 LOC {0 1.0 1 0.08882785 1 0.08882785 1 0.08882785} PREDS {{259 0 0-1740 {}}} SUCCS {{259 0 0-1742 {}}} CYCLES {}}
+set a(0-1742) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#36 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1725 XREFS 13670 LOC {1 0.0 1 0.08882785 1 0.08882785 1 0.16419860637342837 1 0.16419860637342837} PREDS {{258 0 0-1738 {}} {259 0 0-1741 {}}} SUCCS {{259 0 0-1743 {}}} CYCLES {}}
+set a(0-1743) {NAME ACC1:slc#3 TYPE READSLICE PAR 0-1725 XREFS 13671 LOC {1 0.0753708 1 0.16419865 1 0.16419865 1 0.16419865} PREDS {{259 0 0-1742 {}}} SUCCS {{259 0 0-1744 {}}} CYCLES {}}
+set a(0-1744) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#41 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1725 XREFS 13672 LOC {1 0.0753708 1 0.16419865 1 0.16419865 1 0.23956940637342838 1 0.23956940637342838} PREDS {{258 0 0-1735 {}} {259 0 0-1743 {}}} SUCCS {{258 0 0-1765 {}}} CYCLES {}}
+set a(0-1745) {NAME ACC1:asn#5 TYPE ASSIGN PAR 0-1725 XREFS 13673 LOC {0 1.0 0 1.0 0 1.0 1 0.08882785} PREDS {{262 0 0-1880 {}}} SUCCS {{259 0 0-1746 {}} {256 0 0-1880 {}}} CYCLES {}}
+set a(0-1746) {NAME ACC1:slc(regs.regs(2).sg2)#2 TYPE READSLICE PAR 0-1725 XREFS 13674 LOC {0 1.0 0 1.0 0 1.0 1 0.08882785} PREDS {{259 0 0-1745 {}}} SUCCS {{259 0 0-1747 {}}} CYCLES {}}
+set a(0-1747) {NAME ACC1:conc#28 TYPE CONCATENATE PAR 0-1725 XREFS 13675 LOC {0 1.0 1 0.08882785 1 0.08882785 1 0.08882785} PREDS {{259 0 0-1746 {}}} SUCCS {{258 0 0-1752 {}}} CYCLES {}}
+set a(0-1748) {NAME ACC1:asn#6 TYPE ASSIGN PAR 0-1725 XREFS 13676 LOC {0 1.0 0 1.0 0 1.0 1 0.08882785} PREDS {{262 0 0-1881 {}}} SUCCS {{259 0 0-1749 {}} {256 0 0-1881 {}}} CYCLES {}}
+set a(0-1749) {NAME ACC1:slc(regs.regs(2)#1) TYPE READSLICE PAR 0-1725 XREFS 13677 LOC {0 1.0 0 1.0 0 1.0 1 0.08882785} PREDS {{259 0 0-1748 {}}} SUCCS {{259 0 0-1750 {}}} CYCLES {}}
+set a(0-1750) {NAME ACC1:not TYPE NOT PAR 0-1725 XREFS 13678 LOC {0 1.0 1 0.08882785 1 0.08882785 1 0.08882785} PREDS {{259 0 0-1749 {}}} SUCCS {{259 0 0-1751 {}}} CYCLES {}}
+set a(0-1751) {NAME ACC1:conc#29 TYPE CONCATENATE PAR 0-1725 XREFS 13679 LOC {0 1.0 1 0.08882785 1 0.08882785 1 0.08882785} PREDS {{259 0 0-1750 {}}} SUCCS {{259 0 0-1752 {}}} CYCLES {}}
+set a(0-1752) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#35 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1725 XREFS 13680 LOC {1 0.0 1 0.08882785 1 0.08882785 1 0.16419860637342837 1 0.16419860637342837} PREDS {{258 0 0-1747 {}} {259 0 0-1751 {}}} SUCCS {{259 0 0-1753 {}}} CYCLES {}}
+set a(0-1753) {NAME ACC1:slc#2 TYPE READSLICE PAR 0-1725 XREFS 13681 LOC {1 0.0753708 1 0.16419865 1 0.16419865 1 0.16419865} PREDS {{259 0 0-1752 {}}} SUCCS {{258 0 0-1764 {}}} CYCLES {}}
+set a(0-1754) {NAME ACC1:asn#7 TYPE ASSIGN PAR 0-1725 XREFS 13682 LOC {0 1.0 0 1.0 0 1.0 1 0.08882785} PREDS {{262 0 0-1881 {}}} SUCCS {{259 0 0-1755 {}} {256 0 0-1881 {}}} CYCLES {}}
+set a(0-1755) {NAME ACC1:slc(regs.regs(2)#1)#1 TYPE READSLICE PAR 0-1725 XREFS 13683 LOC {0 1.0 0 1.0 0 1.0 1 0.08882785} PREDS {{259 0 0-1754 {}}} SUCCS {{259 0 0-1756 {}}} CYCLES {}}
+set a(0-1756) {NAME ACC1:not#9 TYPE NOT PAR 0-1725 XREFS 13684 LOC {0 1.0 1 0.08882785 1 0.08882785 1 0.08882785} PREDS {{259 0 0-1755 {}}} SUCCS {{259 0 0-1757 {}}} CYCLES {}}
+set a(0-1757) {NAME ACC1:conc TYPE CONCATENATE PAR 0-1725 XREFS 13685 LOC {0 1.0 1 0.08882785 1 0.08882785 1 0.08882785} PREDS {{259 0 0-1756 {}}} SUCCS {{258 0 0-1762 {}}} CYCLES {}}
+set a(0-1758) {NAME ACC1:asn#8 TYPE ASSIGN PAR 0-1725 XREFS 13686 LOC {0 1.0 0 1.0 0 1.0 1 0.08882785} PREDS {{262 0 0-1881 {}}} SUCCS {{259 0 0-1759 {}} {256 0 0-1881 {}}} CYCLES {}}
+set a(0-1759) {NAME ACC1:slc(regs.regs(2)#1)#2 TYPE READSLICE PAR 0-1725 XREFS 13687 LOC {0 1.0 0 1.0 0 1.0 1 0.08882785} PREDS {{259 0 0-1758 {}}} SUCCS {{259 0 0-1760 {}}} CYCLES {}}
+set a(0-1760) {NAME ACC1:not#10 TYPE NOT PAR 0-1725 XREFS 13688 LOC {0 1.0 1 0.08882785 1 0.08882785 1 0.08882785} PREDS {{259 0 0-1759 {}}} SUCCS {{259 0 0-1761 {}}} CYCLES {}}
+set a(0-1761) {NAME ACC1:conc#27 TYPE CONCATENATE PAR 0-1725 XREFS 13689 LOC {0 1.0 1 0.08882785 1 0.08882785 1 0.08882785} PREDS {{259 0 0-1760 {}}} SUCCS {{259 0 0-1762 {}}} CYCLES {}}
+set a(0-1762) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#34 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1725 XREFS 13690 LOC {1 0.0 1 0.08882785 1 0.08882785 1 0.16419860637342837 1 0.16419860637342837} PREDS {{258 0 0-1757 {}} {259 0 0-1761 {}}} SUCCS {{259 0 0-1763 {}}} CYCLES {}}
+set a(0-1763) {NAME ACC1:slc#1 TYPE READSLICE PAR 0-1725 XREFS 13691 LOC {1 0.0753708 1 0.16419865 1 0.16419865 1 0.16419865} PREDS {{259 0 0-1762 {}}} SUCCS {{259 0 0-1764 {}}} CYCLES {}}
+set a(0-1764) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#40 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1725 XREFS 13692 LOC {1 0.0753708 1 0.16419865 1 0.16419865 1 0.23956940637342838 1 0.23956940637342838} PREDS {{258 0 0-1753 {}} {259 0 0-1763 {}}} SUCCS {{259 0 0-1765 {}}} CYCLES {}}
+set a(0-1765) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 1 NAME ACC1:acc#43 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-1725 XREFS 13693 LOC {1 0.1507416 1 0.23956945 1 0.23956945 1 0.31905765349977766 1 0.31905765349977766} PREDS {{258 0 0-1744 {}} {259 0 0-1764 {}}} SUCCS {{258 0 0-1773 {}}} CYCLES {}}
+set a(0-1766) {NAME ACC1:slc(regs.regs(0)) TYPE READSLICE PAR 0-1725 XREFS 13694 LOC {1 0.0 1 0.0930145 1 0.0930145 1 0.17250274999999998} PREDS {{258 0 0-1732 {}}} SUCCS {{258 0 0-1768 {}}} CYCLES {}}
+set a(0-1767) {NAME ACC1:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-1725 XREFS 13695 LOC {1 0.0 1 0.0930145 1 0.0930145 1 0.17250274999999998} PREDS {{258 0 0-1732 {}}} SUCCS {{259 0 0-1768 {}}} CYCLES {}}
+set a(0-1768) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#39 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-1725 XREFS 13696 LOC {1 0.0 1 0.17250274999999998 1 0.17250274999999998 1 0.2436868533364113 1 0.2436868533364113} PREDS {{258 0 0-1766 {}} {259 0 0-1767 {}}} SUCCS {{258 0 0-1772 {}}} CYCLES {}}
+set a(0-1769) {NAME ACC1:slc(regs.regs(0))#2 TYPE READSLICE PAR 0-1725 XREFS 13697 LOC {1 0.0 1 0.0930145 1 0.0930145 1 0.17250274999999998} PREDS {{258 0 0-1732 {}}} SUCCS {{258 0 0-1771 {}}} CYCLES {}}
+set a(0-1770) {NAME ACC1:slc(regs.regs(0))#3 TYPE READSLICE PAR 0-1725 XREFS 13698 LOC {1 0.0 1 0.0930145 1 0.0930145 1 0.17250274999999998} PREDS {{258 0 0-1732 {}}} SUCCS {{259 0 0-1771 {}}} CYCLES {}}
+set a(0-1771) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#38 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-1725 XREFS 13699 LOC {1 0.0 1 0.17250274999999998 1 0.17250274999999998 1 0.2436868533364113 1 0.2436868533364113} PREDS {{258 0 0-1769 {}} {259 0 0-1770 {}}} SUCCS {{259 0 0-1772 {}}} CYCLES {}}
+set a(0-1772) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#42 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1725 XREFS 13700 LOC {1 0.07118415 1 0.24368689999999998 1 0.24368689999999998 1 0.31905765637342837 1 0.31905765637342837} PREDS {{258 0 0-1768 {}} {259 0 0-1771 {}}} SUCCS {{259 0 0-1773 {}}} CYCLES {}}
+set a(0-1773) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,1,12,1,14) AREA_SCORE 14.00 QUANTITY 1 NAME ACC1:acc TYPE ACCU DELAY {1.34 ns} LIBRARY_DELAY {1.34 ns} PAR 0-1725 XREFS 13701 LOC {1 0.23022984999999999 1 0.3190577 1 0.3190577 1 0.40270620021669123 1 0.40270620021669123} PREDS {{258 0 0-1765 {}} {259 0 0-1772 {}}} SUCCS {{259 0 0-1774 {}}} CYCLES {}}
+set a(0-1774) {NAME ACC1:slc TYPE READSLICE PAR 0-1725 XREFS 13702 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.40270625} PREDS {{259 0 0-1773 {}}} SUCCS {{259 0 0-1775 {}} {258 0 0-1776 {}} {258 0 0-1778 {}} {258 0 0-1779 {}} {258 0 0-1784 {}} {258 0 0-1785 {}} {258 0 0-1786 {}} {258 0 0-1789 {}} {258 0 0-1791 {}} {258 0 0-1794 {}} {258 0 0-1810 {}} {258 0 0-1812 {}} {258 0 0-1813 {}} {258 0 0-1814 {}} {258 0 0-1817 {}} {258 0 0-1818 {}} {258 0 0-1819 {}} {258 0 0-1823 {}} {258 0 0-1826 {}} {258 0 0-1833 {}} {258 0 0-1837 {}} {258 0 0-1838 {}} {258 0 0-1839 {}} {258 0 0-1842 {}} {258 0 0-1843 {}} {258 0 0-1844 {}} {258 0 0-1848 {}} {258 0 0-1851 {}} {258 0 0-1858 {}}} CYCLES {}}
+set a(0-1775) {NAME FRAME:slc(ACC1:slc.psp)#3 TYPE READSLICE PAR 0-1725 XREFS 13703 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.4434893} PREDS {{259 0 0-1774 {}}} SUCCS {{258 0 0-1777 {}}} CYCLES {}}
+set a(0-1776) {NAME FRAME:slc(ACC1:slc.psp)#4 TYPE READSLICE PAR 0-1725 XREFS 13704 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.4434893} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1777 {}}} CYCLES {}}
+set a(0-1777) {NAME FRAME:conc#27 TYPE CONCATENATE PAR 0-1725 XREFS 13705 LOC {1 0.3138784 1 0.4434893 1 0.4434893 1 0.4434893} PREDS {{258 0 0-1775 {}} {259 0 0-1776 {}}} SUCCS {{258 0 0-1783 {}}} CYCLES {}}
+set a(0-1778) {NAME FRAME:slc(ACC1:slc.psp) TYPE READSLICE PAR 0-1725 XREFS 13706 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.40270625} PREDS {{258 0 0-1774 {}}} SUCCS {{258 0 0-1782 {}}} CYCLES {}}
+set a(0-1779) {NAME FRAME:slc(ACC1:slc.psp)#1 TYPE READSLICE PAR 0-1725 XREFS 13707 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.40270625} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1780 {}}} CYCLES {}}
+set a(0-1780) {NAME FRAME:not#19 TYPE NOT PAR 0-1725 XREFS 13708 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.40270625} PREDS {{259 0 0-1779 {}}} SUCCS {{259 0 0-1781 {}}} CYCLES {}}
+set a(0-1781) {NAME FRAME:conc#26 TYPE CONCATENATE PAR 0-1725 XREFS 13709 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.40270625} PREDS {{259 0 0-1780 {}}} SUCCS {{259 0 0-1782 {}}} CYCLES {}}
+set a(0-1782) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 3 NAME FRAME:acc#10 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1725 XREFS 13710 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.4434892600894752 1 0.4434892600894752} PREDS {{258 0 0-1778 {}} {259 0 0-1781 {}}} SUCCS {{259 0 0-1783 {}}} CYCLES {}}
+set a(0-1783) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 3 NAME FRAME:acc#11 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-1725 XREFS 13711 LOC {1 0.35466145 1 0.4434893 1 0.4434893 1 0.4765260701789505 1 0.4765260701789505} PREDS {{258 0 0-1777 {}} {259 0 0-1782 {}}} SUCCS {{258 0 0-1788 {}}} CYCLES {}}
+set a(0-1784) {NAME slc(ACC1:slc.psp)#1 TYPE READSLICE PAR 0-1725 XREFS 13712 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.47652612499999997} PREDS {{258 0 0-1774 {}}} SUCCS {{258 0 0-1787 {}}} CYCLES {}}
+set a(0-1785) {NAME slc(ACC1:slc.psp)#2 TYPE READSLICE PAR 0-1725 XREFS 13713 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.47652612499999997} PREDS {{258 0 0-1774 {}}} SUCCS {{258 0 0-1787 {}}} CYCLES {}}
+set a(0-1786) {NAME slc(ACC1:slc.psp) TYPE READSLICE PAR 0-1725 XREFS 13714 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.47652612499999997} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1787 {}}} CYCLES {}}
+set a(0-1787) {NAME FRAME:conc TYPE CONCATENATE PAR 0-1725 XREFS 13715 LOC {1 0.3138784 1 0.47652612499999997 1 0.47652612499999997 1 0.47652612499999997} PREDS {{258 0 0-1785 {}} {258 0 0-1784 {}} {259 0 0-1786 {}}} SUCCS {{259 0 0-1788 {}}} CYCLES {}}
+set a(0-1788) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,6) AREA_SCORE 6.00 QUANTITY 4 NAME FRAME:acc#13 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-1725 XREFS 13716 LOC {1 0.387698275 1 0.47652612499999997 1 0.47652612499999997 1 0.524970709496936 1 0.524970709496936} PREDS {{258 0 0-1783 {}} {259 0 0-1787 {}}} SUCCS {{258 0 0-1796 {}}} CYCLES {}}
+set a(0-1789) {NAME FRAME:slc(ACC1:slc.psp)#5 TYPE READSLICE PAR 0-1725 XREFS 13717 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.47652612499999997} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1790 {}}} CYCLES {}}
+set a(0-1790) {NAME FRAME:not#20 TYPE NOT PAR 0-1725 XREFS 13718 LOC {1 0.3138784 1 0.47652612499999997 1 0.47652612499999997 1 0.47652612499999997} PREDS {{259 0 0-1789 {}}} SUCCS {{258 0 0-1793 {}}} CYCLES {}}
+set a(0-1791) {NAME FRAME:slc(ACC1:slc.psp)#6 TYPE READSLICE PAR 0-1725 XREFS 13719 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.47652612499999997} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1792 {}}} CYCLES {}}
+set a(0-1792) {NAME FRAME:not#21 TYPE NOT PAR 0-1725 XREFS 13720 LOC {1 0.3138784 1 0.47652612499999997 1 0.47652612499999997 1 0.47652612499999997} PREDS {{259 0 0-1791 {}}} SUCCS {{259 0 0-1793 {}}} CYCLES {}}
+set a(0-1793) {NAME FRAME:conc#28 TYPE CONCATENATE PAR 0-1725 XREFS 13721 LOC {1 0.3138784 1 0.47652612499999997 1 0.47652612499999997 1 0.47652612499999997} PREDS {{258 0 0-1790 {}} {259 0 0-1792 {}}} SUCCS {{258 0 0-1795 {}}} CYCLES {}}
+set a(0-1794) {NAME FRAME:slc(ACC1:slc.psp)#2 TYPE READSLICE PAR 0-1725 XREFS 13722 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.47652612499999997} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1795 {}}} CYCLES {}}
+set a(0-1795) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,6) AREA_SCORE 6.00 QUANTITY 4 NAME FRAME:acc#12 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-1725 XREFS 13723 LOC {1 0.3138784 1 0.47652612499999997 1 0.47652612499999997 1 0.524970709496936 1 0.524970709496936} PREDS {{258 0 0-1793 {}} {259 0 0-1794 {}}} SUCCS {{259 0 0-1796 {}}} CYCLES {}}
+set a(0-1796) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,7) AREA_SCORE 7.00 QUANTITY 1 NAME FRAME:acc#14 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1725 XREFS 13724 LOC {1 0.4361429 1 0.5249707499999999 1 0.5249707499999999 1 0.5783275984103023 1 0.5783275984103023} PREDS {{258 0 0-1788 {}} {259 0 0-1795 {}}} SUCCS {{259 0 0-1797 {}}} CYCLES {}}
+set a(0-1797) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,7) AREA_SCORE 8.27 QUANTITY 1 NAME acc TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-1725 XREFS 13725 LOC {1 0.4894998 1 0.57832765 1 0.57832765 1 0.6465169629329679 1 0.6465169629329679} PREDS {{259 0 0-1796 {}}} SUCCS {{259 0 0-1798 {}} {258 0 0-1799 {}} {258 0 0-1800 {}} {258 0 0-1802 {}} {258 0 0-1804 {}} {258 0 0-1806 {}} {258 0 0-1824 {}} {258 0 0-1828 {}} {258 0 0-1849 {}} {258 0 0-1853 {}}} CYCLES {}}
+set a(0-1798) {NAME slc(acc.imod#2)#1 TYPE READSLICE PAR 0-1725 XREFS 13726 LOC {1 0.5576891749999999 1 0.646517025 1 0.646517025 1 0.646517025} PREDS {{259 0 0-1797 {}}} SUCCS {{258 0 0-1801 {}}} CYCLES {}}
+set a(0-1799) {NAME slc(acc.imod#2)#2 TYPE READSLICE PAR 0-1725 XREFS 13727 LOC {1 0.5576891749999999 1 0.646517025 1 0.646517025 1 0.646517025} PREDS {{258 0 0-1797 {}}} SUCCS {{258 0 0-1801 {}}} CYCLES {}}
+set a(0-1800) {NAME slc(acc.imod#2) TYPE READSLICE PAR 0-1725 XREFS 13728 LOC {1 0.5576891749999999 1 0.646517025 1 0.646517025 1 0.646517025} PREDS {{258 0 0-1797 {}}} SUCCS {{259 0 0-1801 {}}} CYCLES {}}
+set a(0-1801) {NAME FRAME:conc#8 TYPE CONCATENATE PAR 0-1725 XREFS 13729 LOC {1 0.5576891749999999 1 0.646517025 1 0.646517025 1 0.646517025} PREDS {{258 0 0-1799 {}} {258 0 0-1798 {}} {259 0 0-1800 {}}} SUCCS {{258 0 0-1803 {}}} CYCLES {}}
+set a(0-1802) {NAME FRAME:slc(acc.imod#2)#1 TYPE READSLICE PAR 0-1725 XREFS 13730 LOC {1 0.5576891749999999 1 0.646517025 1 0.646517025 1 0.646517025} PREDS {{258 0 0-1797 {}}} SUCCS {{259 0 0-1803 {}}} CYCLES {}}
+set a(0-1803) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,6) AREA_SCORE 6.00 QUANTITY 4 NAME FRAME:acc#16 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-1725 XREFS 13731 LOC {1 0.5576891749999999 1 0.646517025 1 0.646517025 1 0.694961609496936 1 0.694961609496936} PREDS {{258 0 0-1801 {}} {259 0 0-1802 {}}} SUCCS {{258 0 0-1808 {}}} CYCLES {}}
+set a(0-1804) {NAME FRAME:slc(acc.imod#2)#2 TYPE READSLICE PAR 0-1725 XREFS 13732 LOC {1 0.5576891749999999 1 0.646517025 1 0.646517025 1 0.651373475} PREDS {{258 0 0-1797 {}}} SUCCS {{259 0 0-1805 {}}} CYCLES {}}
+set a(0-1805) {NAME FRAME:conc#9 TYPE CONCATENATE PAR 0-1725 XREFS 13733 LOC {1 0.5576891749999999 1 0.651373475 1 0.651373475 1 0.651373475} PREDS {{259 0 0-1804 {}}} SUCCS {{258 0 0-1807 {}}} CYCLES {}}
+set a(0-1806) {NAME FRAME:slc(acc.imod#2) TYPE READSLICE PAR 0-1725 XREFS 13734 LOC {1 0.5576891749999999 1 0.646517025 1 0.646517025 1 0.651373475} PREDS {{258 0 0-1797 {}}} SUCCS {{259 0 0-1807 {}}} CYCLES {}}
+set a(0-1807) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,2,1,5) AREA_SCORE 5.00 QUANTITY 1 NAME FRAME:acc#15 TYPE ACCU DELAY {0.70 ns} LIBRARY_DELAY {0.70 ns} PAR 0-1725 XREFS 13735 LOC {1 0.5576891749999999 1 0.651373475 1 0.651373475 1 0.6949615898622739 1 0.6949615898622739} PREDS {{258 0 0-1805 {}} {259 0 0-1806 {}}} SUCCS {{259 0 0-1808 {}}} CYCLES {}}
+set a(0-1808) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,6) AREA_SCORE 6.00 QUANTITY 4 NAME acc#3 TYPE ACCU DELAY {0.78 ns} LIBRARY_DELAY {0.78 ns} PAR 0-1725 XREFS 13736 LOC {1 0.6061338 1 0.69496165 1 0.69496165 1 0.7434062344969361 1 0.7434062344969361} PREDS {{258 0 0-1803 {}} {259 0 0-1807 {}}} SUCCS {{259 0 0-1809 {}}} CYCLES {}}
+set a(0-1809) {NAME FRAME:slc#5 TYPE READSLICE PAR 0-1725 XREFS 13737 LOC {1 0.654578425 1 0.743406275 1 0.743406275 1 0.743406275} PREDS {{259 0 0-1808 {}}} SUCCS {{258 0 0-1829 {}} {258 0 0-1854 {}}} CYCLES {}}
+set a(0-1810) {NAME red:slc(red#2.sg1)#19 TYPE READSLICE PAR 0-1725 XREFS 13738 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.676038525} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1811 {}}} CYCLES {}}
+set a(0-1811) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(4,0,5,0,9) AREA_SCORE 330.25 QUANTITY 1 NAME FRAME:mul#3 TYPE MUL DELAY {2.70 ns} LIBRARY_DELAY {2.70 ns} PAR 0-1725 XREFS 13739 LOC {1 0.3138784 1 0.676038525 1 0.676038525 1 0.8447964778773613 1 0.8447964778773613} PREDS {{259 0 0-1810 {}}} SUCCS {{258 0 0-1835 {}} {258 0 0-1860 {}}} CYCLES {}}
+set a(0-1812) {NAME red:slc(red#2.sg1)#24 TYPE READSLICE PAR 0-1725 XREFS 13740 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.840889225} PREDS {{258 0 0-1774 {}}} SUCCS {{258 0 0-1816 {}}} CYCLES {}}
+set a(0-1813) {NAME red:slc(red#2.sg1)#25 TYPE READSLICE PAR 0-1725 XREFS 13741 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.840889225} PREDS {{258 0 0-1774 {}}} SUCCS {{258 0 0-1816 {}}} CYCLES {}}
+set a(0-1814) {NAME red:slc(red#2.sg1)#26 TYPE READSLICE PAR 0-1725 XREFS 13742 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.840889225} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1815 {}}} CYCLES {}}
+set a(0-1815) {NAME FRAME:exs#3 TYPE SIGNEXTEND PAR 0-1725 XREFS 13743 LOC {1 0.3138784 1 0.840889225 1 0.840889225 1 0.840889225} PREDS {{259 0 0-1814 {}}} SUCCS {{259 0 0-1816 {}}} CYCLES {}}
+set a(0-1816) {NAME FRAME:conc#11 TYPE CONCATENATE PAR 0-1725 XREFS 13744 LOC {1 0.3138784 1 0.840889225 1 0.840889225 1 0.840889225} PREDS {{258 0 0-1813 {}} {258 0 0-1812 {}} {259 0 0-1815 {}}} SUCCS {{258 0 0-1822 {}}} CYCLES {}}
+set a(0-1817) {NAME red:slc(red#2.sg1)#21 TYPE READSLICE PAR 0-1725 XREFS 13745 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.840889225} PREDS {{258 0 0-1774 {}}} SUCCS {{258 0 0-1821 {}}} CYCLES {}}
+set a(0-1818) {NAME red:slc(red#2.sg1)#22 TYPE READSLICE PAR 0-1725 XREFS 13746 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.840889225} PREDS {{258 0 0-1774 {}}} SUCCS {{258 0 0-1821 {}}} CYCLES {}}
+set a(0-1819) {NAME red:slc(red#2.sg1)#23 TYPE READSLICE PAR 0-1725 XREFS 13747 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.840889225} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1820 {}}} CYCLES {}}
+set a(0-1820) {NAME FRAME:exs#2 TYPE SIGNEXTEND PAR 0-1725 XREFS 13748 LOC {1 0.3138784 1 0.840889225 1 0.840889225 1 0.840889225} PREDS {{259 0 0-1819 {}}} SUCCS {{259 0 0-1821 {}}} CYCLES {}}
+set a(0-1821) {NAME FRAME:conc#10 TYPE CONCATENATE PAR 0-1725 XREFS 13749 LOC {1 0.3138784 1 0.840889225 1 0.840889225 1 0.840889225} PREDS {{258 0 0-1818 {}} {258 0 0-1817 {}} {259 0 0-1820 {}}} SUCCS {{259 0 0-1822 {}}} CYCLES {}}
+set a(0-1822) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME FRAME:acc#23 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-1725 XREFS 13750 LOC {1 0.3138784 1 0.840889225 1 0.840889225 1 0.9120733283364113 1 0.9120733283364113} PREDS {{258 0 0-1816 {}} {259 0 0-1821 {}}} SUCCS {{258 0 0-1836 {}}} CYCLES {}}
+set a(0-1823) {NAME red:slc(red#2.sg1)#20 TYPE READSLICE PAR 0-1725 XREFS 13751 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.701964725} PREDS {{258 0 0-1774 {}}} SUCCS {{258 0 0-1825 {}}} CYCLES {}}
+set a(0-1824) {NAME FRAME:slc(acc.imod#2)#3 TYPE READSLICE PAR 0-1725 XREFS 13752 LOC {1 0.5576891749999999 1 0.646517025 1 0.646517025 1 0.701964725} PREDS {{258 0 0-1797 {}}} SUCCS {{259 0 0-1825 {}}} CYCLES {}}
+set a(0-1825) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 2 NAME FRAME:acc#17 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1725 XREFS 13753 LOC {1 0.5576891749999999 1 0.701964725 1 0.701964725 1 0.7335755612499999 1 0.7335755612499999} PREDS {{258 0 0-1823 {}} {259 0 0-1824 {}}} SUCCS {{258 0 0-1827 {}}} CYCLES {}}
+set a(0-1826) {NAME red:slc(red#2.sg1)#27 TYPE READSLICE PAR 0-1725 XREFS 13754 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.7335756} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1827 {}}} CYCLES {}}
+set a(0-1827) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 3 NAME FRAME:acc#19 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1725 XREFS 13755 LOC {1 0.58930005 1 0.7335756 1 0.7335756 1 0.7743586100894753 1 0.7743586100894753} PREDS {{258 0 0-1825 {}} {259 0 0-1826 {}}} SUCCS {{258 0 0-1832 {}}} CYCLES {}}
+set a(0-1828) {NAME FRAME:slc(acc.imod#2)#4 TYPE READSLICE PAR 0-1725 XREFS 13756 LOC {1 0.5576891749999999 1 0.646517025 1 0.646517025 1 0.743406275} PREDS {{258 0 0-1797 {}}} SUCCS {{258 0 0-1831 {}}} CYCLES {}}
+set a(0-1829) {NAME FRAME:not#12 TYPE NOT PAR 0-1725 XREFS 13757 LOC {1 0.654578425 1 0.743406275 1 0.743406275 1 0.743406275} PREDS {{258 0 0-1809 {}}} SUCCS {{259 0 0-1830 {}}} CYCLES {}}
+set a(0-1830) {NAME FRAME:xor TYPE XOR PAR 0-1725 XREFS 13758 LOC {1 0.654578425 1 0.743406275 1 0.743406275 1 0.743406275} PREDS {{259 0 0-1829 {}}} SUCCS {{259 0 0-1831 {}}} CYCLES {}}
+set a(0-1831) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,1,1,1,3) AREA_SCORE 3.00 QUANTITY 2 NAME FRAME:acc#18 TYPE ACCU DELAY {0.50 ns} LIBRARY_DELAY {0.50 ns} PAR 0-1725 XREFS 13759 LOC {1 0.654578425 1 0.743406275 1 0.743406275 1 0.7743585910227986 1 0.7743585910227986} PREDS {{258 0 0-1828 {}} {259 0 0-1830 {}}} SUCCS {{259 0 0-1832 {}}} CYCLES {}}
+set a(0-1832) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,4) AREA_SCORE 4.00 QUANTITY 2 NAME FRAME:acc#20 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-1725 XREFS 13760 LOC {1 0.6855308 1 0.7743586499999999 1 0.7743586499999999 1 0.8117596520708271 1 0.8117596520708271} PREDS {{258 0 0-1827 {}} {259 0 0-1831 {}}} SUCCS {{258 0 0-1834 {}}} CYCLES {}}
+set a(0-1833) {NAME red:slc(red#2.sg1)#28 TYPE READSLICE PAR 0-1725 XREFS 13761 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.8117597} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1834 {}}} CYCLES {}}
+set a(0-1834) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 3 NAME FRAME:acc#21 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-1725 XREFS 13762 LOC {1 0.7229318499999999 1 0.8117597 1 0.8117597 1 0.8447964701789504 1 0.8447964701789504} PREDS {{258 0 0-1832 {}} {259 0 0-1833 {}}} SUCCS {{259 0 0-1835 {}}} CYCLES {}}
+set a(0-1835) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,6,1,10) AREA_SCORE 10.00 QUANTITY 2 NAME FRAME:acc#22 TYPE ACCU DELAY {1.08 ns} LIBRARY_DELAY {1.08 ns} PAR 0-1725 XREFS 13763 LOC {1 0.755968675 1 0.8447965249999999 1 0.8447965249999999 1 0.9120733153449988 1 0.9120733153449988} PREDS {{258 0 0-1811 {}} {259 0 0-1834 {}}} SUCCS {{259 0 0-1836 {}}} CYCLES {}}
+set a(0-1836) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,11) AREA_SCORE 11.00 QUANTITY 1 NAME FRAME:acc#5 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-1725 XREFS 13764 LOC {1 0.8232455249999999 1 0.912073375 1 0.912073375 1 0.9832574783364113 1 0.9832574783364113} PREDS {{258 0 0-1822 {}} {259 0 0-1835 {}}} SUCCS {{258 0 0-1862 {}} {258 0 0-1865 {}} {258 0 0-1866 {}} {258 0 0-1867 {}} {258 0 0-1870 {}}} CYCLES {}}
+set a(0-1837) {NAME red:slc(red#2.sg1)#17 TYPE READSLICE PAR 0-1725 XREFS 13765 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.840889225} PREDS {{258 0 0-1774 {}}} SUCCS {{258 0 0-1841 {}}} CYCLES {}}
+set a(0-1838) {NAME red:slc(red#2.sg1)#18 TYPE READSLICE PAR 0-1725 XREFS 13766 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.840889225} PREDS {{258 0 0-1774 {}}} SUCCS {{258 0 0-1841 {}}} CYCLES {}}
+set a(0-1839) {NAME red:slc(red#2.sg1)#12 TYPE READSLICE PAR 0-1725 XREFS 13767 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.840889225} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1840 {}}} CYCLES {}}
+set a(0-1840) {NAME FRAME:exs#1 TYPE SIGNEXTEND PAR 0-1725 XREFS 13768 LOC {1 0.3138784 1 0.840889225 1 0.840889225 1 0.840889225} PREDS {{259 0 0-1839 {}}} SUCCS {{259 0 0-1841 {}}} CYCLES {}}
+set a(0-1841) {NAME FRAME:conc#5 TYPE CONCATENATE PAR 0-1725 XREFS 13769 LOC {1 0.3138784 1 0.840889225 1 0.840889225 1 0.840889225} PREDS {{258 0 0-1838 {}} {258 0 0-1837 {}} {259 0 0-1840 {}}} SUCCS {{258 0 0-1847 {}}} CYCLES {}}
+set a(0-1842) {NAME red:slc(red#2.sg1)#15 TYPE READSLICE PAR 0-1725 XREFS 13770 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.840889225} PREDS {{258 0 0-1774 {}}} SUCCS {{258 0 0-1846 {}}} CYCLES {}}
+set a(0-1843) {NAME red:slc(red#2.sg1)#16 TYPE READSLICE PAR 0-1725 XREFS 13771 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.840889225} PREDS {{258 0 0-1774 {}}} SUCCS {{258 0 0-1846 {}}} CYCLES {}}
+set a(0-1844) {NAME red:slc(red#2.sg1)#11 TYPE READSLICE PAR 0-1725 XREFS 13772 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.840889225} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1845 {}}} CYCLES {}}
+set a(0-1845) {NAME FRAME:exs TYPE SIGNEXTEND PAR 0-1725 XREFS 13773 LOC {1 0.3138784 1 0.840889225 1 0.840889225 1 0.840889225} PREDS {{259 0 0-1844 {}}} SUCCS {{259 0 0-1846 {}}} CYCLES {}}
+set a(0-1846) {NAME FRAME:conc#4 TYPE CONCATENATE PAR 0-1725 XREFS 13774 LOC {1 0.3138784 1 0.840889225 1 0.840889225 1 0.840889225} PREDS {{258 0 0-1843 {}} {258 0 0-1842 {}} {259 0 0-1845 {}}} SUCCS {{259 0 0-1847 {}}} CYCLES {}}
+set a(0-1847) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME FRAME:acc#30 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-1725 XREFS 13775 LOC {1 0.3138784 1 0.840889225 1 0.840889225 1 0.9120733283364113 1 0.9120733283364113} PREDS {{258 0 0-1841 {}} {259 0 0-1846 {}}} SUCCS {{258 0 0-1861 {}}} CYCLES {}}
+set a(0-1848) {NAME red:slc(red#2.sg1)#13 TYPE READSLICE PAR 0-1725 XREFS 13776 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.701964725} PREDS {{258 0 0-1774 {}}} SUCCS {{258 0 0-1850 {}}} CYCLES {}}
+set a(0-1849) {NAME FRAME:slc(acc.imod)#3 TYPE READSLICE PAR 0-1725 XREFS 13777 LOC {1 0.5576891749999999 1 0.646517025 1 0.646517025 1 0.701964725} PREDS {{258 0 0-1797 {}}} SUCCS {{259 0 0-1850 {}}} CYCLES {}}
+set a(0-1850) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 2 NAME FRAME:acc#24 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1725 XREFS 13778 LOC {1 0.5576891749999999 1 0.701964725 1 0.701964725 1 0.7335755612499999 1 0.7335755612499999} PREDS {{258 0 0-1848 {}} {259 0 0-1849 {}}} SUCCS {{258 0 0-1852 {}}} CYCLES {}}
+set a(0-1851) {NAME red:slc(red#2.sg1)#14 TYPE READSLICE PAR 0-1725 XREFS 13779 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.7335756} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1852 {}}} CYCLES {}}
+set a(0-1852) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 3 NAME FRAME:acc#26 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1725 XREFS 13780 LOC {1 0.58930005 1 0.7335756 1 0.7335756 1 0.7743586100894753 1 0.7743586100894753} PREDS {{258 0 0-1850 {}} {259 0 0-1851 {}}} SUCCS {{258 0 0-1857 {}}} CYCLES {}}
+set a(0-1853) {NAME FRAME:slc(acc.imod)#4 TYPE READSLICE PAR 0-1725 XREFS 13781 LOC {1 0.5576891749999999 1 0.646517025 1 0.646517025 1 0.743406275} PREDS {{258 0 0-1797 {}}} SUCCS {{258 0 0-1856 {}}} CYCLES {}}
+set a(0-1854) {NAME FRAME:not#6 TYPE NOT PAR 0-1725 XREFS 13782 LOC {1 0.654578425 1 0.743406275 1 0.743406275 1 0.743406275} PREDS {{258 0 0-1809 {}}} SUCCS {{259 0 0-1855 {}}} CYCLES {}}
+set a(0-1855) {NAME FRAME:xor#1 TYPE XOR PAR 0-1725 XREFS 13783 LOC {1 0.654578425 1 0.743406275 1 0.743406275 1 0.743406275} PREDS {{259 0 0-1854 {}}} SUCCS {{259 0 0-1856 {}}} CYCLES {}}
+set a(0-1856) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,1,1,1,3) AREA_SCORE 3.00 QUANTITY 2 NAME FRAME:acc#25 TYPE ACCU DELAY {0.50 ns} LIBRARY_DELAY {0.50 ns} PAR 0-1725 XREFS 13784 LOC {1 0.654578425 1 0.743406275 1 0.743406275 1 0.7743585910227986 1 0.7743585910227986} PREDS {{258 0 0-1853 {}} {259 0 0-1855 {}}} SUCCS {{259 0 0-1857 {}}} CYCLES {}}
+set a(0-1857) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,4) AREA_SCORE 4.00 QUANTITY 2 NAME FRAME:acc#27 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-1725 XREFS 13785 LOC {1 0.6855308 1 0.7743586499999999 1 0.7743586499999999 1 0.8117596520708271 1 0.8117596520708271} PREDS {{258 0 0-1852 {}} {259 0 0-1856 {}}} SUCCS {{258 0 0-1859 {}}} CYCLES {}}
+set a(0-1858) {NAME red:slc(red#2.sg1) TYPE READSLICE PAR 0-1725 XREFS 13786 LOC {1 0.3138784 1 0.40270625 1 0.40270625 1 0.8117597} PREDS {{258 0 0-1774 {}}} SUCCS {{259 0 0-1859 {}}} CYCLES {}}
+set a(0-1859) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 3 NAME FRAME:acc#28 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-1725 XREFS 13787 LOC {1 0.7229318499999999 1 0.8117597 1 0.8117597 1 0.8447964701789504 1 0.8447964701789504} PREDS {{258 0 0-1857 {}} {259 0 0-1858 {}}} SUCCS {{259 0 0-1860 {}}} CYCLES {}}
+set a(0-1860) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,6,1,10) AREA_SCORE 10.00 QUANTITY 2 NAME FRAME:acc#29 TYPE ACCU DELAY {1.08 ns} LIBRARY_DELAY {1.08 ns} PAR 0-1725 XREFS 13788 LOC {1 0.755968675 1 0.8447965249999999 1 0.8447965249999999 1 0.9120733153449988 1 0.9120733153449988} PREDS {{258 0 0-1811 {}} {259 0 0-1859 {}}} SUCCS {{259 0 0-1861 {}}} CYCLES {}}
+set a(0-1861) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME FRAME:acc#3 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-1725 XREFS 13789 LOC {1 0.8232455249999999 1 0.912073375 1 0.912073375 1 0.9832574783364113 1 0.9832574783364113} PREDS {{258 0 0-1847 {}} {259 0 0-1860 {}}} SUCCS {{258 0 0-1864 {}}} CYCLES {}}
+set a(0-1862) {NAME green:slc(green) TYPE READSLICE PAR 0-1725 XREFS 13790 LOC {1 0.8944296749999999 1 0.983257525 1 0.983257525 1 0.983257525} PREDS {{258 0 0-1836 {}}} SUCCS {{259 0 0-1863 {}}} CYCLES {}}
+set a(0-1863) {NAME FRAME:exu#6 TYPE PADZEROES PAR 0-1725 XREFS 13791 LOC {1 0.8944296749999999 1 0.983257525 1 0.983257525 1 0.983257525} PREDS {{259 0 0-1862 {}}} SUCCS {{259 0 0-1864 {}}} CYCLES {}}
+set a(0-1864) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(10,2) AREA_SCORE 7.30 QUANTITY 1 NAME FRAME:or TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-1725 XREFS 13792 LOC {1 0.8944296749999999 1 0.983257525 1 0.983257525 1 0.9999999561077388 1 0.9999999561077388} PREDS {{258 0 0-1861 {}} {259 0 0-1863 {}}} SUCCS {{258 0 0-1871 {}}} CYCLES {}}
+set a(0-1865) {NAME green:slc(green)#1 TYPE READSLICE PAR 0-1725 XREFS 13793 LOC {1 0.8944296749999999 1 0.983257525 1 0.983257525 1 1.0} PREDS {{258 0 0-1836 {}}} SUCCS {{258 0 0-1871 {}}} CYCLES {}}
+set a(0-1866) {NAME green:slc(green)#2 TYPE READSLICE PAR 0-1725 XREFS 13794 LOC {1 0.8944296749999999 1 0.983257525 1 0.983257525 1 0.983257525} PREDS {{258 0 0-1836 {}}} SUCCS {{258 0 0-1869 {}}} CYCLES {}}
+set a(0-1867) {NAME blue:slc(blue) TYPE READSLICE PAR 0-1725 XREFS 13795 LOC {1 0.8944296749999999 1 0.983257525 1 0.983257525 1 0.983257525} PREDS {{258 0 0-1836 {}}} SUCCS {{259 0 0-1868 {}}} CYCLES {}}
+set a(0-1868) {NAME FRAME:exu#8 TYPE PADZEROES PAR 0-1725 XREFS 13796 LOC {1 0.8944296749999999 1 0.983257525 1 0.983257525 1 0.983257525} PREDS {{259 0 0-1867 {}}} SUCCS {{259 0 0-1869 {}}} CYCLES {}}
+set a(0-1869) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(6,2) AREA_SCORE 4.38 QUANTITY 1 NAME FRAME:or#3 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-1725 XREFS 13797 LOC {1 0.8944296749999999 1 0.983257525 1 0.983257525 1 0.9999999561077388 1 0.9999999561077388} PREDS {{258 0 0-1866 {}} {259 0 0-1868 {}}} SUCCS {{258 0 0-1871 {}}} CYCLES {}}
+set a(0-1870) {NAME blue:slc(blue)#1 TYPE READSLICE PAR 0-1725 XREFS 13798 LOC {1 0.8944296749999999 1 0.983257525 1 0.983257525 1 1.0} PREDS {{258 0 0-1836 {}}} SUCCS {{259 0 0-1871 {}}} CYCLES {}}
+set a(0-1871) {NAME FRAME:conc#25 TYPE CONCATENATE PAR 0-1725 XREFS 13799 LOC {1 0.91117215 1 1.0 1 1.0 1 1.0} PREDS {{258 0 0-1869 {}} {258 0 0-1865 {}} {258 0 0-1864 {}} {259 0 0-1870 {}}} SUCCS {{259 0 0-1872 {}}} CYCLES {}}
+set a(0-1872) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(2,30) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_write(vout:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-1725 XREFS 13800 LOC {1 1.0 1 1.0 1 1.0 2 0.0 1 0.9999} PREDS {{260 0 0-1872 {}} {259 0 0-1871 {}}} SUCCS {{260 0 0-1872 {}}} CYCLES {}}
+set a(0-1873) {NAME FRAME:asn#13 TYPE ASSIGN PAR 0-1725 XREFS 13801 LOC {0 1.0 1 0.79151865 1 0.79151865 2 0.79151865} PREDS {{262 0 0-1886 {}}} SUCCS {{259 0 0-1874 {}} {256 0 0-1886 {}}} CYCLES {}}
+set a(0-1874) {NAME FRAME:not#22 TYPE NOT PAR 0-1725 XREFS 13802 LOC {1 0.0 1 0.79151865 1 0.79151865 2 0.79151865} PREDS {{259 0 0-1873 {}}} SUCCS {{259 0 0-1875 {}}} CYCLES {}}
+set a(0-1875) {NAME FRAME:exs#8 TYPE SIGNEXTEND PAR 0-1725 XREFS 13803 LOC {1 0.0 1 0.79151865 1 0.79151865 2 0.79151865} PREDS {{259 0 0-1874 {}}} SUCCS {{259 0 0-1876 {}}} CYCLES {}}
+set a(0-1876) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(19,2) AREA_SCORE 13.87 QUANTITY 1 NAME FRAME:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-1725 XREFS 13804 LOC {1 0.0 1 0.79151865 1 0.79151865 1 0.8079253812638539 2 0.8079253812638539} PREDS {{262 0 0-1879 {}} {259 0 0-1875 {}}} SUCCS {{259 0 0-1877 {}} {256 0 0-1879 {}}} CYCLES {}}
+set a(0-1877) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(19,0,2,1,19) AREA_SCORE 20.00 QUANTITY 1 NAME FRAME:acc#9 TYPE ACCU DELAY {1.91 ns} LIBRARY_DELAY {1.91 ns} PAR 0-1725 XREFS 13805 LOC {1 0.016406775 1 0.807925425 1 0.807925425 1 0.9271847410815965 2 0.9271847410815965} PREDS {{259 0 0-1876 {}}} SUCCS {{258 0 0-1879 {}} {258 0 0-1882 {}}} CYCLES {}}
+set a(0-1878) {NAME FRAME:asn(regs.regs(0).sva) TYPE ASSIGN PAR 0-1725 XREFS 13806 LOC {1 0.0 1 0.0930145 1 0.0930145 2 1.0} PREDS {{260 0 0-1878 {}} {256 0 0-1728 {}} {256 0 0-1730 {}} {258 0 0-1732 {}}} SUCCS {{262 0 0-1728 {}} {262 0 0-1730 {}} {260 0 0-1878 {}}} CYCLES {}}
+set a(0-1879) {NAME FRAME:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-1725 XREFS 13807 LOC {1 0.13566614999999999 1 0.9271847999999999 1 0.9271847999999999 2 1.0} PREDS {{260 0 0-1879 {}} {256 0 0-1876 {}} {258 0 0-1877 {}}} SUCCS {{262 0 0-1876 {}} {260 0 0-1879 {}}} CYCLES {}}
+set a(0-1880) {NAME FRAME:asn(regs.regs(1).sg2.sva) TYPE ASSIGN PAR 0-1725 XREFS 13808 LOC {0 1.0 0 1.0 0 1.0 2 0.08882785} PREDS {{260 0 0-1880 {}} {256 0 0-1736 {}} {256 0 0-1739 {}} {256 0 0-1745 {}} {258 0 0-1731 {}}} SUCCS {{262 0 0-1736 {}} {262 0 0-1739 {}} {262 0 0-1745 {}} {260 0 0-1880 {}}} CYCLES {}}
+set a(0-1881) {NAME FRAME:asn(regs.regs(1)#1.sva) TYPE ASSIGN PAR 0-1725 XREFS 13809 LOC {0 1.0 0 1.0 0 1.0 2 0.08882785} PREDS {{260 0 0-1881 {}} {256 0 0-1748 {}} {256 0 0-1754 {}} {256 0 0-1758 {}} {258 0 0-1729 {}}} SUCCS {{262 0 0-1748 {}} {262 0 0-1754 {}} {262 0 0-1758 {}} {260 0 0-1881 {}}} CYCLES {}}
+set a(0-1882) {NAME FRAME:p:slc(FRAME:p)#1 TYPE READSLICE PAR 0-1725 XREFS 13810 LOC {1 0.13566614999999999 1 0.9271847999999999 1 0.9271847999999999 2 0.9271847999999999} PREDS {{258 0 0-1877 {}}} SUCCS {{259 0 0-1883 {}}} CYCLES {}}
+set a(0-1883) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,7,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME FRAME:acc TYPE ACCU DELAY {1.17 ns} LIBRARY_DELAY {1.17 ns} PAR 0-1725 XREFS 13811 LOC {1 0.13566614999999999 1 0.9271847999999999 1 0.9271847999999999 1 0.9999999617915235 2 0.9999999617915235} PREDS {{259 0 0-1882 {}}} SUCCS {{259 0 0-1884 {}}} CYCLES {}}
+set a(0-1884) {NAME FRAME:slc TYPE READSLICE PAR 0-1725 XREFS 13812 LOC {1 0.20848134999999998 1 1.0 1 1.0 2 1.0} PREDS {{259 0 0-1883 {}}} SUCCS {{259 0 0-1885 {}}} CYCLES {}}
+set a(0-1885) {NAME FRAME:not TYPE NOT PAR 0-1725 XREFS 13813 LOC {1 0.20848134999999998 1 1.0 1 1.0 2 1.0} PREDS {{259 0 0-1884 {}}} SUCCS {{259 0 0-1886 {}}} CYCLES {}}
+set a(0-1886) {NAME FRAME:asn#14 TYPE ASSIGN PAR 0-1725 XREFS 13814 LOC {1 0.20848134999999998 1 1.0 1 1.0 2 1.0} PREDS {{260 0 0-1886 {}} {256 0 0-1726 {}} {256 0 0-1873 {}} {259 0 0-1885 {}}} SUCCS {{262 0 0-1726 {}} {262 0 0-1873 {}} {260 0 0-1886 {}}} CYCLES {}}
+set a(0-1725) {CHI {0-1726 0-1727 0-1728 0-1729 0-1730 0-1731 0-1732 0-1733 0-1734 0-1735 0-1736 0-1737 0-1738 0-1739 0-1740 0-1741 0-1742 0-1743 0-1744 0-1745 0-1746 0-1747 0-1748 0-1749 0-1750 0-1751 0-1752 0-1753 0-1754 0-1755 0-1756 0-1757 0-1758 0-1759 0-1760 0-1761 0-1762 0-1763 0-1764 0-1765 0-1766 0-1767 0-1768 0-1769 0-1770 0-1771 0-1772 0-1773 0-1774 0-1775 0-1776 0-1777 0-1778 0-1779 0-1780 0-1781 0-1782 0-1783 0-1784 0-1785 0-1786 0-1787 0-1788 0-1789 0-1790 0-1791 0-1792 0-1793 0-1794 0-1795 0-1796 0-1797 0-1798 0-1799 0-1800 0-1801 0-1802 0-1803 0-1804 0-1805 0-1806 0-1807 0-1808 0-1809 0-1810 0-1811 0-1812 0-1813 0-1814 0-1815 0-1816 0-1817 0-1818 0-1819 0-1820 0-1821 0-1822 0-1823 0-1824 0-1825 0-1826 0-1827 0-1828 0-1829 0-1830 0-1831 0-1832 0-1833 0-1834 0-1835 0-1836 0-1837 0-1838 0-1839 0-1840 0-1841 0-1842 0-1843 0-1844 0-1845 0-1846 0-1847 0-1848 0-1849 0-1850 0-1851 0-1852 0-1853 0-1854 0-1855 0-1856 0-1857 0-1858 0-1859 0-1860 0-1861 0-1862 0-1863 0-1864 0-1865 0-1866 0-1867 0-1868 0-1869 0-1870 0-1871 0-1872 0-1873 0-1874 0-1875 0-1876 0-1877 0-1878 0-1879 0-1880 0-1881 0-1882 0-1883 0-1884 0-1885 0-1886} ITERATIONS Infinite LATENCY 307200 RESET_LATENCY 0 CSTEPS 2 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 307200 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 2.0 CYCLES_IN 307201 TOTAL_CYCLES_IN 307201 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 307201 NAME main TYPE LOOP DELAY {6144040.00 ns} PAR 0-1719 XREFS 13815 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{258 0 0-1720 {}} {258 0 0-1721 {}} {258 0 0-1722 {}} {258 0 0-1723 {}} {259 0 0-1724 {}}} SUCCS {{772 0 0-1720 {}} {772 0 0-1721 {}} {772 0 0-1722 {}} {772 0 0-1723 {}} {772 0 0-1724 {}}} CYCLES {}}
+set a(0-1719) {CHI {0-1720 0-1721 0-1722 0-1723 0-1724 0-1725} ITERATIONS Infinite LATENCY 307200 RESET_LATENCY 0 CSTEPS 0 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 307200 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 0 TOTAL_CYCLES_IN 0 TOTAL_CYCLES_UNDER 307201 TOTAL_CYCLES 307201 NAME core:rlp TYPE LOOP DELAY {6144040.00 ns} PAR {} XREFS 13816 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-1719-TOTALCYCLES) {307201}
+set a(0-1719-QMOD) {mgc_ioport.mgc_in_wire(1,90) 0-1732 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11) {0-1735 0-1768 0-1771 0-1822 0-1847 0-1861} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12) {0-1742 0-1744 0-1752 0-1762 0-1764 0-1772} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) 0-1765 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,1,12,1,14) 0-1773 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3) {0-1782 0-1827 0-1852} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6) {0-1783 0-1834 0-1859} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,6) {0-1788 0-1795 0-1803 0-1808} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,7) 0-1796 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,7) 0-1797 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,2,1,5) 0-1807 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,5,0,9) 0-1811 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2) {0-1825 0-1850} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,1,1,1,3) {0-1831 0-1856} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,4) {0-1832 0-1857} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,6,1,10) {0-1835 0-1860} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11) 0-1836 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2) 0-1864 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2) 0-1869 mgc_ioport.mgc_out_stdreg(2,30) 0-1872 mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2) 0-1876 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19) 0-1877 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,7,0,8) 0-1883}
+set a(0-1719-PROC_NAME) {core}
+set a(0-1719-HIER_NAME) {/sobel/core}
+set a(TOP) {0-1719}
+
diff --git a/Sobel/sobel.v5/schematic.nlv b/Sobel/sobel.v5/schematic.nlv
new file mode 100644
index 0000000..4964765
--- /dev/null
+++ b/Sobel/sobel.v5/schematic.nlv
@@ -0,0 +1,3433 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "sobel:core" "orig"
+load port {clk} input -attr xrf 14128 -attr oid 1 -attr vt d -attr @path {/sobel/sobel:core/clk}
+load port {en} input -attr xrf 14129 -attr oid 2 -attr vt d -attr @path {/sobel/sobel:core/en}
+load port {arst_n} input -attr xrf 14130 -attr oid 3 -attr vt d -attr @path {/sobel/sobel:core/arst_n}
+load portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} -attr xrf 14131 -attr oid 4 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} -attr xrf 14132 -attr oid 5 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load symbol "reg(10,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(9:0)} input 10 {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(9:0)} input 10 {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(30,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(29:0)} input 30 {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(29:0)} input 30 {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,10,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,11,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(10)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,1,12,1,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(13,1,12,1,14)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(12:0)} input 13 {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(13:0)} output 14 {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(4,0,5,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(1,0,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,1,1,1,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,6,1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,10,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(4,0,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,5,1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(2)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "not(3)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,1,6,0,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,-1,7,-1,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,6,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,-1,10,-1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,10)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,6)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(5:0)} input 6 {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(5:0)} input 6 {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(6,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(5:0)} input 6 {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(5:0)} input 6 {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load net {regs.regs(1)#1.sva(0)} -attr vt d
+load net {regs.regs(1)#1.sva(1)} -attr vt d
+load net {regs.regs(1)#1.sva(2)} -attr vt d
+load net {regs.regs(1)#1.sva(3)} -attr vt d
+load net {regs.regs(1)#1.sva(4)} -attr vt d
+load net {regs.regs(1)#1.sva(5)} -attr vt d
+load net {regs.regs(1)#1.sva(6)} -attr vt d
+load net {regs.regs(1)#1.sva(7)} -attr vt d
+load net {regs.regs(1)#1.sva(8)} -attr vt d
+load net {regs.regs(1)#1.sva(9)} -attr vt d
+load net {regs.regs(1)#1.sva(10)} -attr vt d
+load net {regs.regs(1)#1.sva(11)} -attr vt d
+load net {regs.regs(1)#1.sva(12)} -attr vt d
+load net {regs.regs(1)#1.sva(13)} -attr vt d
+load net {regs.regs(1)#1.sva(14)} -attr vt d
+load net {regs.regs(1)#1.sva(15)} -attr vt d
+load net {regs.regs(1)#1.sva(16)} -attr vt d
+load net {regs.regs(1)#1.sva(17)} -attr vt d
+load net {regs.regs(1)#1.sva(18)} -attr vt d
+load net {regs.regs(1)#1.sva(19)} -attr vt d
+load net {regs.regs(1)#1.sva(20)} -attr vt d
+load net {regs.regs(1)#1.sva(21)} -attr vt d
+load net {regs.regs(1)#1.sva(22)} -attr vt d
+load net {regs.regs(1)#1.sva(23)} -attr vt d
+load net {regs.regs(1)#1.sva(24)} -attr vt d
+load net {regs.regs(1)#1.sva(25)} -attr vt d
+load net {regs.regs(1)#1.sva(26)} -attr vt d
+load net {regs.regs(1)#1.sva(27)} -attr vt d
+load net {regs.regs(1)#1.sva(28)} -attr vt d
+load net {regs.regs(1)#1.sva(29)} -attr vt d
+load netBundle {regs.regs(1)#1.sva} 30 {regs.regs(1)#1.sva(0)} {regs.regs(1)#1.sva(1)} {regs.regs(1)#1.sva(2)} {regs.regs(1)#1.sva(3)} {regs.regs(1)#1.sva(4)} {regs.regs(1)#1.sva(5)} {regs.regs(1)#1.sva(6)} {regs.regs(1)#1.sva(7)} {regs.regs(1)#1.sva(8)} {regs.regs(1)#1.sva(9)} {regs.regs(1)#1.sva(10)} {regs.regs(1)#1.sva(11)} {regs.regs(1)#1.sva(12)} {regs.regs(1)#1.sva(13)} {regs.regs(1)#1.sva(14)} {regs.regs(1)#1.sva(15)} {regs.regs(1)#1.sva(16)} {regs.regs(1)#1.sva(17)} {regs.regs(1)#1.sva(18)} {regs.regs(1)#1.sva(19)} {regs.regs(1)#1.sva(20)} {regs.regs(1)#1.sva(21)} {regs.regs(1)#1.sva(22)} {regs.regs(1)#1.sva(23)} {regs.regs(1)#1.sva(24)} {regs.regs(1)#1.sva(25)} {regs.regs(1)#1.sva(26)} {regs.regs(1)#1.sva(27)} {regs.regs(1)#1.sva(28)} {regs.regs(1)#1.sva(29)} -attr xrf 14133 -attr oid 6 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1).sg2.sva(0)} -attr vt d
+load net {regs.regs(1).sg2.sva(1)} -attr vt d
+load net {regs.regs(1).sg2.sva(2)} -attr vt d
+load net {regs.regs(1).sg2.sva(3)} -attr vt d
+load net {regs.regs(1).sg2.sva(4)} -attr vt d
+load net {regs.regs(1).sg2.sva(5)} -attr vt d
+load net {regs.regs(1).sg2.sva(6)} -attr vt d
+load net {regs.regs(1).sg2.sva(7)} -attr vt d
+load net {regs.regs(1).sg2.sva(8)} -attr vt d
+load net {regs.regs(1).sg2.sva(9)} -attr vt d
+load net {regs.regs(1).sg2.sva(10)} -attr vt d
+load net {regs.regs(1).sg2.sva(11)} -attr vt d
+load net {regs.regs(1).sg2.sva(12)} -attr vt d
+load net {regs.regs(1).sg2.sva(13)} -attr vt d
+load net {regs.regs(1).sg2.sva(14)} -attr vt d
+load net {regs.regs(1).sg2.sva(15)} -attr vt d
+load net {regs.regs(1).sg2.sva(16)} -attr vt d
+load net {regs.regs(1).sg2.sva(17)} -attr vt d
+load net {regs.regs(1).sg2.sva(18)} -attr vt d
+load net {regs.regs(1).sg2.sva(19)} -attr vt d
+load net {regs.regs(1).sg2.sva(20)} -attr vt d
+load net {regs.regs(1).sg2.sva(21)} -attr vt d
+load net {regs.regs(1).sg2.sva(22)} -attr vt d
+load net {regs.regs(1).sg2.sva(23)} -attr vt d
+load net {regs.regs(1).sg2.sva(24)} -attr vt d
+load net {regs.regs(1).sg2.sva(25)} -attr vt d
+load net {regs.regs(1).sg2.sva(26)} -attr vt d
+load net {regs.regs(1).sg2.sva(27)} -attr vt d
+load net {regs.regs(1).sg2.sva(28)} -attr vt d
+load net {regs.regs(1).sg2.sva(29)} -attr vt d
+load netBundle {regs.regs(1).sg2.sva} 30 {regs.regs(1).sg2.sva(0)} {regs.regs(1).sg2.sva(1)} {regs.regs(1).sg2.sva(2)} {regs.regs(1).sg2.sva(3)} {regs.regs(1).sg2.sva(4)} {regs.regs(1).sg2.sva(5)} {regs.regs(1).sg2.sva(6)} {regs.regs(1).sg2.sva(7)} {regs.regs(1).sg2.sva(8)} {regs.regs(1).sg2.sva(9)} {regs.regs(1).sg2.sva(10)} {regs.regs(1).sg2.sva(11)} {regs.regs(1).sg2.sva(12)} {regs.regs(1).sg2.sva(13)} {regs.regs(1).sg2.sva(14)} {regs.regs(1).sg2.sva(15)} {regs.regs(1).sg2.sva(16)} {regs.regs(1).sg2.sva(17)} {regs.regs(1).sg2.sva(18)} {regs.regs(1).sg2.sva(19)} {regs.regs(1).sg2.sva(20)} {regs.regs(1).sg2.sva(21)} {regs.regs(1).sg2.sva(22)} {regs.regs(1).sg2.sva(23)} {regs.regs(1).sg2.sva(24)} {regs.regs(1).sg2.sva(25)} {regs.regs(1).sg2.sva(26)} {regs.regs(1).sg2.sva(27)} {regs.regs(1).sg2.sva(28)} {regs.regs(1).sg2.sva(29)} -attr xrf 14134 -attr oid 7 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {ACC1:slc(regs.regs(2).sg2).itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2).itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2).itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2).itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2).itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2).itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2).itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2).itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2).itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2).itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2).sg2).itm} 10 {ACC1:slc(regs.regs(2).sg2).itm(0)} {ACC1:slc(regs.regs(2).sg2).itm(1)} {ACC1:slc(regs.regs(2).sg2).itm(2)} {ACC1:slc(regs.regs(2).sg2).itm(3)} {ACC1:slc(regs.regs(2).sg2).itm(4)} {ACC1:slc(regs.regs(2).sg2).itm(5)} {ACC1:slc(regs.regs(2).sg2).itm(6)} {ACC1:slc(regs.regs(2).sg2).itm(7)} {ACC1:slc(regs.regs(2).sg2).itm(8)} {ACC1:slc(regs.regs(2).sg2).itm(9)} -attr xrf 14135 -attr oid 8 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2).itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2).sg2)#1.itm} 10 {ACC1:slc(regs.regs(2).sg2)#1.itm(0)} {ACC1:slc(regs.regs(2).sg2)#1.itm(1)} {ACC1:slc(regs.regs(2).sg2)#1.itm(2)} {ACC1:slc(regs.regs(2).sg2)#1.itm(3)} {ACC1:slc(regs.regs(2).sg2)#1.itm(4)} {ACC1:slc(regs.regs(2).sg2)#1.itm(5)} {ACC1:slc(regs.regs(2).sg2)#1.itm(6)} {ACC1:slc(regs.regs(2).sg2)#1.itm(7)} {ACC1:slc(regs.regs(2).sg2)#1.itm(8)} {ACC1:slc(regs.regs(2).sg2)#1.itm(9)} -attr xrf 14136 -attr oid 9 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#1.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2).sg2)#2.itm} 10 {ACC1:slc(regs.regs(2).sg2)#2.itm(0)} {ACC1:slc(regs.regs(2).sg2)#2.itm(1)} {ACC1:slc(regs.regs(2).sg2)#2.itm(2)} {ACC1:slc(regs.regs(2).sg2)#2.itm(3)} {ACC1:slc(regs.regs(2).sg2)#2.itm(4)} {ACC1:slc(regs.regs(2).sg2)#2.itm(5)} {ACC1:slc(regs.regs(2).sg2)#2.itm(6)} {ACC1:slc(regs.regs(2).sg2)#2.itm(7)} {ACC1:slc(regs.regs(2).sg2)#2.itm(8)} {ACC1:slc(regs.regs(2).sg2)#2.itm(9)} -attr xrf 14137 -attr oid 10 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1).itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1).itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1).itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1).itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1).itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1).itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1).itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1).itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1).itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2)#1).itm} 10 {ACC1:slc(regs.regs(2)#1).itm(0)} {ACC1:slc(regs.regs(2)#1).itm(1)} {ACC1:slc(regs.regs(2)#1).itm(2)} {ACC1:slc(regs.regs(2)#1).itm(3)} {ACC1:slc(regs.regs(2)#1).itm(4)} {ACC1:slc(regs.regs(2)#1).itm(5)} {ACC1:slc(regs.regs(2)#1).itm(6)} {ACC1:slc(regs.regs(2)#1).itm(7)} {ACC1:slc(regs.regs(2)#1).itm(8)} {ACC1:slc(regs.regs(2)#1).itm(9)} -attr xrf 14138 -attr oid 11 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2)#1)#1.itm} 10 {ACC1:slc(regs.regs(2)#1)#1.itm(0)} {ACC1:slc(regs.regs(2)#1)#1.itm(1)} {ACC1:slc(regs.regs(2)#1)#1.itm(2)} {ACC1:slc(regs.regs(2)#1)#1.itm(3)} {ACC1:slc(regs.regs(2)#1)#1.itm(4)} {ACC1:slc(regs.regs(2)#1)#1.itm(5)} {ACC1:slc(regs.regs(2)#1)#1.itm(6)} {ACC1:slc(regs.regs(2)#1)#1.itm(7)} {ACC1:slc(regs.regs(2)#1)#1.itm(8)} {ACC1:slc(regs.regs(2)#1)#1.itm(9)} -attr xrf 14139 -attr oid 12 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(0)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(1)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(2)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(3)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(4)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(5)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(6)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(7)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(8)} -attr vt d
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(9)} -attr vt d
+load netBundle {ACC1:slc(regs.regs(2)#1)#2.itm} 10 {ACC1:slc(regs.regs(2)#1)#2.itm(0)} {ACC1:slc(regs.regs(2)#1)#2.itm(1)} {ACC1:slc(regs.regs(2)#1)#2.itm(2)} {ACC1:slc(regs.regs(2)#1)#2.itm(3)} {ACC1:slc(regs.regs(2)#1)#2.itm(4)} {ACC1:slc(regs.regs(2)#1)#2.itm(5)} {ACC1:slc(regs.regs(2)#1)#2.itm(6)} {ACC1:slc(regs.regs(2)#1)#2.itm(7)} {ACC1:slc(regs.regs(2)#1)#2.itm(8)} {ACC1:slc(regs.regs(2)#1)#2.itm(9)} -attr xrf 14140 -attr oid 13 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(0)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(1)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(2)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(3)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(4)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(5)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(6)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(7)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(8)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(9)} -attr vt d
+load netBundle {reg(vout:rsc:mgc_out_stdreg.d).tmp} 10 {reg(vout:rsc:mgc_out_stdreg.d).tmp(0)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(1)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(2)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(3)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(4)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(5)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(6)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(7)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(8)} {reg(vout:rsc:mgc_out_stdreg.d).tmp(9)} -attr xrf 14141 -attr oid 14 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(0)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(1)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(2)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(3)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(4)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(5)} -attr vt d
+load netBundle {reg(vout:rsc:mgc_out_stdreg.d).tmp#2} 6 {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(0)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(1)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(2)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(3)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(4)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(5)} -attr xrf 14142 -attr oid 15 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#2}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(0)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(1)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(2)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(3)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(4)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(5)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(6)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(7)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(8)} -attr vt d
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(9)} -attr vt d
+load netBundle {reg(vout:rsc:mgc_out_stdreg.d).tmp#3} 10 {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(0)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(1)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(2)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(3)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(4)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(5)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(6)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(7)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(8)} {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(9)} -attr xrf 14143 -attr oid 16 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#3}
+load net {ACC1:slc.psp.sva(0)} -attr vt d
+load net {ACC1:slc.psp.sva(1)} -attr vt d
+load net {ACC1:slc.psp.sva(2)} -attr vt d
+load net {ACC1:slc.psp.sva(3)} -attr vt d
+load net {ACC1:slc.psp.sva(4)} -attr vt d
+load net {ACC1:slc.psp.sva(5)} -attr vt d
+load net {ACC1:slc.psp.sva(6)} -attr vt d
+load net {ACC1:slc.psp.sva(7)} -attr vt d
+load net {ACC1:slc.psp.sva(8)} -attr vt d
+load net {ACC1:slc.psp.sva(9)} -attr vt d
+load net {ACC1:slc.psp.sva(10)} -attr vt d
+load net {ACC1:slc.psp.sva(11)} -attr vt d
+load net {ACC1:slc.psp.sva(12)} -attr vt d
+load netBundle {ACC1:slc.psp.sva} 13 {ACC1:slc.psp.sva(0)} {ACC1:slc.psp.sva(1)} {ACC1:slc.psp.sva(2)} {ACC1:slc.psp.sva(3)} {ACC1:slc.psp.sva(4)} {ACC1:slc.psp.sva(5)} {ACC1:slc.psp.sva(6)} {ACC1:slc.psp.sva(7)} {ACC1:slc.psp.sva(8)} {ACC1:slc.psp.sva(9)} {ACC1:slc.psp.sva(10)} {ACC1:slc.psp.sva(11)} {ACC1:slc.psp.sva(12)} -attr xrf 14144 -attr oid 17 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.psp.sva}
+load net {FRAME:acc#22.cse(0)} -attr vt d
+load net {FRAME:acc#22.cse(1)} -attr vt d
+load net {FRAME:acc#22.cse(2)} -attr vt d
+load net {FRAME:acc#22.cse(3)} -attr vt d
+load net {FRAME:acc#22.cse(4)} -attr vt d
+load net {FRAME:acc#22.cse(5)} -attr vt d
+load net {FRAME:acc#22.cse(6)} -attr vt d
+load net {FRAME:acc#22.cse(7)} -attr vt d
+load net {FRAME:acc#22.cse(8)} -attr vt d
+load net {FRAME:acc#22.cse(9)} -attr vt d
+load netBundle {FRAME:acc#22.cse} 10 {FRAME:acc#22.cse(0)} {FRAME:acc#22.cse(1)} {FRAME:acc#22.cse(2)} {FRAME:acc#22.cse(3)} {FRAME:acc#22.cse(4)} {FRAME:acc#22.cse(5)} {FRAME:acc#22.cse(6)} {FRAME:acc#22.cse(7)} {FRAME:acc#22.cse(8)} {FRAME:acc#22.cse(9)} -attr xrf 14145 -attr oid 18 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#5.psp.sva(0)} -attr vt d
+load net {FRAME:acc#5.psp.sva(1)} -attr vt d
+load net {FRAME:acc#5.psp.sva(2)} -attr vt d
+load net {FRAME:acc#5.psp.sva(3)} -attr vt d
+load net {FRAME:acc#5.psp.sva(4)} -attr vt d
+load net {FRAME:acc#5.psp.sva(5)} -attr vt d
+load net {FRAME:acc#5.psp.sva(6)} -attr vt d
+load net {FRAME:acc#5.psp.sva(7)} -attr vt d
+load net {FRAME:acc#5.psp.sva(8)} -attr vt d
+load net {FRAME:acc#5.psp.sva(9)} -attr vt d
+load net {FRAME:acc#5.psp.sva(10)} -attr vt d
+load netBundle {FRAME:acc#5.psp.sva} 11 {FRAME:acc#5.psp.sva(0)} {FRAME:acc#5.psp.sva(1)} {FRAME:acc#5.psp.sva(2)} {FRAME:acc#5.psp.sva(3)} {FRAME:acc#5.psp.sva(4)} {FRAME:acc#5.psp.sva(5)} {FRAME:acc#5.psp.sva(6)} {FRAME:acc#5.psp.sva(7)} {FRAME:acc#5.psp.sva(8)} {FRAME:acc#5.psp.sva(9)} {FRAME:acc#5.psp.sva(10)} -attr xrf 14146 -attr oid 19 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {acc.imod.sva(0)} -attr vt d
+load net {acc.imod.sva(1)} -attr vt d
+load net {acc.imod.sva(2)} -attr vt d
+load net {acc.imod.sva(3)} -attr vt d
+load net {acc.imod.sva(4)} -attr vt d
+load net {acc.imod.sva(5)} -attr vt d
+load net {acc.imod.sva(6)} -attr vt d
+load netBundle {acc.imod.sva} 7 {acc.imod.sva(0)} {acc.imod.sva(1)} {acc.imod.sva(2)} {acc.imod.sva(3)} {acc.imod.sva(4)} {acc.imod.sva(5)} {acc.imod.sva(6)} -attr xrf 14147 -attr oid 20 -attr vt d -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {FRAME:conc#34(0)} -attr vt d
+load net {FRAME:conc#34(1)} -attr vt d
+load net {FRAME:conc#34(2)} -attr vt d
+load net {FRAME:conc#34(3)} -attr vt d
+load net {FRAME:conc#34(4)} -attr vt d
+load net {FRAME:conc#34(5)} -attr vt d
+load net {FRAME:conc#34(6)} -attr vt d
+load net {FRAME:conc#34(7)} -attr vt d
+load net {FRAME:conc#34(8)} -attr vt d
+load net {FRAME:conc#34(9)} -attr vt d
+load netBundle {FRAME:conc#34} 10 {FRAME:conc#34(0)} {FRAME:conc#34(1)} {FRAME:conc#34(2)} {FRAME:conc#34(3)} {FRAME:conc#34(4)} {FRAME:conc#34(5)} {FRAME:conc#34(6)} {FRAME:conc#34(7)} {FRAME:conc#34(8)} {FRAME:conc#34(9)} -attr xrf 14148 -attr oid 21 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {slc(reg(vout:rsc:mgc_out_stdreg.d).tmp#3).itm(0)} -attr vt d
+load net {slc(reg(vout:rsc:mgc_out_stdreg.d).tmp#3).itm(1)} -attr vt d
+load net {slc(reg(vout:rsc:mgc_out_stdreg.d).tmp#3).itm(2)} -attr vt d
+load net {slc(reg(vout:rsc:mgc_out_stdreg.d).tmp#3).itm(3)} -attr vt d
+load netBundle {slc(reg(vout:rsc:mgc_out_stdreg.d).tmp#3).itm} 4 {slc(reg(vout:rsc:mgc_out_stdreg.d).tmp#3).itm(0)} {slc(reg(vout:rsc:mgc_out_stdreg.d).tmp#3).itm(1)} {slc(reg(vout:rsc:mgc_out_stdreg.d).tmp#3).itm(2)} {slc(reg(vout:rsc:mgc_out_stdreg.d).tmp#3).itm(3)} -attr xrf 14149 -attr oid 22 -attr vt d -attr @path {/sobel/sobel:core/slc(reg(vout:rsc:mgc_out_stdreg.d).tmp#3).itm}
+load net {slc(regs.regs(1).sg2.sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sg2.sva)#2.itm} 10 {slc(regs.regs(1).sg2.sva)#2.itm(0)} {slc(regs.regs(1).sg2.sva)#2.itm(1)} {slc(regs.regs(1).sg2.sva)#2.itm(2)} {slc(regs.regs(1).sg2.sva)#2.itm(3)} {slc(regs.regs(1).sg2.sva)#2.itm(4)} {slc(regs.regs(1).sg2.sva)#2.itm(5)} {slc(regs.regs(1).sg2.sva)#2.itm(6)} {slc(regs.regs(1).sg2.sva)#2.itm(7)} {slc(regs.regs(1).sg2.sva)#2.itm(8)} {slc(regs.regs(1).sg2.sva)#2.itm(9)} -attr xrf 14150 -attr oid 23 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {slc(regs.regs(1).sg2.sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sg2.sva)#1.itm} 10 {slc(regs.regs(1).sg2.sva)#1.itm(0)} {slc(regs.regs(1).sg2.sva)#1.itm(1)} {slc(regs.regs(1).sg2.sva)#1.itm(2)} {slc(regs.regs(1).sg2.sva)#1.itm(3)} {slc(regs.regs(1).sg2.sva)#1.itm(4)} {slc(regs.regs(1).sg2.sva)#1.itm(5)} {slc(regs.regs(1).sg2.sva)#1.itm(6)} {slc(regs.regs(1).sg2.sva)#1.itm(7)} {slc(regs.regs(1).sg2.sva)#1.itm(8)} {slc(regs.regs(1).sg2.sva)#1.itm(9)} -attr xrf 14151 -attr oid 24 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {slc(regs.regs(1).sg2.sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sg2.sva).itm} 10 {slc(regs.regs(1).sg2.sva).itm(0)} {slc(regs.regs(1).sg2.sva).itm(1)} {slc(regs.regs(1).sg2.sva).itm(2)} {slc(regs.regs(1).sg2.sva).itm(3)} {slc(regs.regs(1).sg2.sva).itm(4)} {slc(regs.regs(1).sg2.sva).itm(5)} {slc(regs.regs(1).sg2.sva).itm(6)} {slc(regs.regs(1).sg2.sva).itm(7)} {slc(regs.regs(1).sg2.sva).itm(8)} {slc(regs.regs(1).sg2.sva).itm(9)} -attr xrf 14152 -attr oid 25 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {slc(regs.regs(1)#1.sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1)#1.sva)#2.itm} 10 {slc(regs.regs(1)#1.sva)#2.itm(0)} {slc(regs.regs(1)#1.sva)#2.itm(1)} {slc(regs.regs(1)#1.sva)#2.itm(2)} {slc(regs.regs(1)#1.sva)#2.itm(3)} {slc(regs.regs(1)#1.sva)#2.itm(4)} {slc(regs.regs(1)#1.sva)#2.itm(5)} {slc(regs.regs(1)#1.sva)#2.itm(6)} {slc(regs.regs(1)#1.sva)#2.itm(7)} {slc(regs.regs(1)#1.sva)#2.itm(8)} {slc(regs.regs(1)#1.sva)#2.itm(9)} -attr xrf 14153 -attr oid 26 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {slc(regs.regs(1)#1.sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1)#1.sva)#1.itm} 10 {slc(regs.regs(1)#1.sva)#1.itm(0)} {slc(regs.regs(1)#1.sva)#1.itm(1)} {slc(regs.regs(1)#1.sva)#1.itm(2)} {slc(regs.regs(1)#1.sva)#1.itm(3)} {slc(regs.regs(1)#1.sva)#1.itm(4)} {slc(regs.regs(1)#1.sva)#1.itm(5)} {slc(regs.regs(1)#1.sva)#1.itm(6)} {slc(regs.regs(1)#1.sva)#1.itm(7)} {slc(regs.regs(1)#1.sva)#1.itm(8)} {slc(regs.regs(1)#1.sva)#1.itm(9)} -attr xrf 14154 -attr oid 27 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {slc(regs.regs(1)#1.sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1)#1.sva).itm} 10 {slc(regs.regs(1)#1.sva).itm(0)} {slc(regs.regs(1)#1.sva).itm(1)} {slc(regs.regs(1)#1.sva).itm(2)} {slc(regs.regs(1)#1.sva).itm(3)} {slc(regs.regs(1)#1.sva).itm(4)} {slc(regs.regs(1)#1.sva).itm(5)} {slc(regs.regs(1)#1.sva).itm(6)} {slc(regs.regs(1)#1.sva).itm(7)} {slc(regs.regs(1)#1.sva).itm(8)} {slc(regs.regs(1)#1.sva).itm(9)} -attr xrf 14155 -attr oid 28 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {slc(regs.regs(0).sva#8).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(9)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(10)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(11)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(12)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(13)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(14)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(15)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(16)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(17)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(18)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(19)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(20)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(21)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(22)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(23)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(24)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(25)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(26)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(27)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(28)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(29)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#8).itm} 30 {slc(regs.regs(0).sva#8).itm(0)} {slc(regs.regs(0).sva#8).itm(1)} {slc(regs.regs(0).sva#8).itm(2)} {slc(regs.regs(0).sva#8).itm(3)} {slc(regs.regs(0).sva#8).itm(4)} {slc(regs.regs(0).sva#8).itm(5)} {slc(regs.regs(0).sva#8).itm(6)} {slc(regs.regs(0).sva#8).itm(7)} {slc(regs.regs(0).sva#8).itm(8)} {slc(regs.regs(0).sva#8).itm(9)} {slc(regs.regs(0).sva#8).itm(10)} {slc(regs.regs(0).sva#8).itm(11)} {slc(regs.regs(0).sva#8).itm(12)} {slc(regs.regs(0).sva#8).itm(13)} {slc(regs.regs(0).sva#8).itm(14)} {slc(regs.regs(0).sva#8).itm(15)} {slc(regs.regs(0).sva#8).itm(16)} {slc(regs.regs(0).sva#8).itm(17)} {slc(regs.regs(0).sva#8).itm(18)} {slc(regs.regs(0).sva#8).itm(19)} {slc(regs.regs(0).sva#8).itm(20)} {slc(regs.regs(0).sva#8).itm(21)} {slc(regs.regs(0).sva#8).itm(22)} {slc(regs.regs(0).sva#8).itm(23)} {slc(regs.regs(0).sva#8).itm(24)} {slc(regs.regs(0).sva#8).itm(25)} {slc(regs.regs(0).sva#8).itm(26)} {slc(regs.regs(0).sva#8).itm(27)} {slc(regs.regs(0).sva#8).itm(28)} {slc(regs.regs(0).sva#8).itm(29)} -attr xrf 14156 -attr oid 29 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {slc(regs.regs(0).sva#7).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(9)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(10)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(11)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(12)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(13)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(14)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(15)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(16)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(17)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(18)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(19)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(20)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(21)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(22)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(23)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(24)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(25)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(26)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(27)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(28)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(29)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#7).itm} 30 {slc(regs.regs(0).sva#7).itm(0)} {slc(regs.regs(0).sva#7).itm(1)} {slc(regs.regs(0).sva#7).itm(2)} {slc(regs.regs(0).sva#7).itm(3)} {slc(regs.regs(0).sva#7).itm(4)} {slc(regs.regs(0).sva#7).itm(5)} {slc(regs.regs(0).sva#7).itm(6)} {slc(regs.regs(0).sva#7).itm(7)} {slc(regs.regs(0).sva#7).itm(8)} {slc(regs.regs(0).sva#7).itm(9)} {slc(regs.regs(0).sva#7).itm(10)} {slc(regs.regs(0).sva#7).itm(11)} {slc(regs.regs(0).sva#7).itm(12)} {slc(regs.regs(0).sva#7).itm(13)} {slc(regs.regs(0).sva#7).itm(14)} {slc(regs.regs(0).sva#7).itm(15)} {slc(regs.regs(0).sva#7).itm(16)} {slc(regs.regs(0).sva#7).itm(17)} {slc(regs.regs(0).sva#7).itm(18)} {slc(regs.regs(0).sva#7).itm(19)} {slc(regs.regs(0).sva#7).itm(20)} {slc(regs.regs(0).sva#7).itm(21)} {slc(regs.regs(0).sva#7).itm(22)} {slc(regs.regs(0).sva#7).itm(23)} {slc(regs.regs(0).sva#7).itm(24)} {slc(regs.regs(0).sva#7).itm(25)} {slc(regs.regs(0).sva#7).itm(26)} {slc(regs.regs(0).sva#7).itm(27)} {slc(regs.regs(0).sva#7).itm(28)} {slc(regs.regs(0).sva#7).itm(29)} -attr xrf 14157 -attr oid 30 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {ACC1:acc.itm(0)} -attr vt d
+load net {ACC1:acc.itm(1)} -attr vt d
+load net {ACC1:acc.itm(2)} -attr vt d
+load net {ACC1:acc.itm(3)} -attr vt d
+load net {ACC1:acc.itm(4)} -attr vt d
+load net {ACC1:acc.itm(5)} -attr vt d
+load net {ACC1:acc.itm(6)} -attr vt d
+load net {ACC1:acc.itm(7)} -attr vt d
+load net {ACC1:acc.itm(8)} -attr vt d
+load net {ACC1:acc.itm(9)} -attr vt d
+load net {ACC1:acc.itm(10)} -attr vt d
+load net {ACC1:acc.itm(11)} -attr vt d
+load net {ACC1:acc.itm(12)} -attr vt d
+load net {ACC1:acc.itm(13)} -attr vt d
+load netBundle {ACC1:acc.itm} 14 {ACC1:acc.itm(0)} {ACC1:acc.itm(1)} {ACC1:acc.itm(2)} {ACC1:acc.itm(3)} {ACC1:acc.itm(4)} {ACC1:acc.itm(5)} {ACC1:acc.itm(6)} {ACC1:acc.itm(7)} {ACC1:acc.itm(8)} {ACC1:acc.itm(9)} {ACC1:acc.itm(10)} {ACC1:acc.itm(11)} {ACC1:acc.itm(12)} {ACC1:acc.itm(13)} -attr xrf 14158 -attr oid 31 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc#43.itm(0)} -attr vt d
+load net {ACC1:acc#43.itm(1)} -attr vt d
+load net {ACC1:acc#43.itm(2)} -attr vt d
+load net {ACC1:acc#43.itm(3)} -attr vt d
+load net {ACC1:acc#43.itm(4)} -attr vt d
+load net {ACC1:acc#43.itm(5)} -attr vt d
+load net {ACC1:acc#43.itm(6)} -attr vt d
+load net {ACC1:acc#43.itm(7)} -attr vt d
+load net {ACC1:acc#43.itm(8)} -attr vt d
+load net {ACC1:acc#43.itm(9)} -attr vt d
+load net {ACC1:acc#43.itm(10)} -attr vt d
+load net {ACC1:acc#43.itm(11)} -attr vt d
+load net {ACC1:acc#43.itm(12)} -attr vt d
+load netBundle {ACC1:acc#43.itm} 13 {ACC1:acc#43.itm(0)} {ACC1:acc#43.itm(1)} {ACC1:acc#43.itm(2)} {ACC1:acc#43.itm(3)} {ACC1:acc#43.itm(4)} {ACC1:acc#43.itm(5)} {ACC1:acc#43.itm(6)} {ACC1:acc#43.itm(7)} {ACC1:acc#43.itm(8)} {ACC1:acc#43.itm(9)} {ACC1:acc#43.itm(10)} {ACC1:acc#43.itm(11)} {ACC1:acc#43.itm(12)} -attr xrf 14159 -attr oid 32 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#41.itm(0)} -attr vt d
+load net {ACC1:acc#41.itm(1)} -attr vt d
+load net {ACC1:acc#41.itm(2)} -attr vt d
+load net {ACC1:acc#41.itm(3)} -attr vt d
+load net {ACC1:acc#41.itm(4)} -attr vt d
+load net {ACC1:acc#41.itm(5)} -attr vt d
+load net {ACC1:acc#41.itm(6)} -attr vt d
+load net {ACC1:acc#41.itm(7)} -attr vt d
+load net {ACC1:acc#41.itm(8)} -attr vt d
+load net {ACC1:acc#41.itm(9)} -attr vt d
+load net {ACC1:acc#41.itm(10)} -attr vt d
+load net {ACC1:acc#41.itm(11)} -attr vt d
+load netBundle {ACC1:acc#41.itm} 12 {ACC1:acc#41.itm(0)} {ACC1:acc#41.itm(1)} {ACC1:acc#41.itm(2)} {ACC1:acc#41.itm(3)} {ACC1:acc#41.itm(4)} {ACC1:acc#41.itm(5)} {ACC1:acc#41.itm(6)} {ACC1:acc#41.itm(7)} {ACC1:acc#41.itm(8)} {ACC1:acc#41.itm(9)} {ACC1:acc#41.itm(10)} {ACC1:acc#41.itm(11)} -attr xrf 14160 -attr oid 33 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#37.itm(0)} -attr vt d
+load net {ACC1:acc#37.itm(1)} -attr vt d
+load net {ACC1:acc#37.itm(2)} -attr vt d
+load net {ACC1:acc#37.itm(3)} -attr vt d
+load net {ACC1:acc#37.itm(4)} -attr vt d
+load net {ACC1:acc#37.itm(5)} -attr vt d
+load net {ACC1:acc#37.itm(6)} -attr vt d
+load net {ACC1:acc#37.itm(7)} -attr vt d
+load net {ACC1:acc#37.itm(8)} -attr vt d
+load net {ACC1:acc#37.itm(9)} -attr vt d
+load net {ACC1:acc#37.itm(10)} -attr vt d
+load netBundle {ACC1:acc#37.itm} 11 {ACC1:acc#37.itm(0)} {ACC1:acc#37.itm(1)} {ACC1:acc#37.itm(2)} {ACC1:acc#37.itm(3)} {ACC1:acc#37.itm(4)} {ACC1:acc#37.itm(5)} {ACC1:acc#37.itm(6)} {ACC1:acc#37.itm(7)} {ACC1:acc#37.itm(8)} {ACC1:acc#37.itm(9)} {ACC1:acc#37.itm(10)} -attr xrf 14161 -attr oid 34 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {slc(regs.regs(0).sva#1).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#1).itm} 10 {slc(regs.regs(0).sva#1).itm(0)} {slc(regs.regs(0).sva#1).itm(1)} {slc(regs.regs(0).sva#1).itm(2)} {slc(regs.regs(0).sva#1).itm(3)} {slc(regs.regs(0).sva#1).itm(4)} {slc(regs.regs(0).sva#1).itm(5)} {slc(regs.regs(0).sva#1).itm(6)} {slc(regs.regs(0).sva#1).itm(7)} {slc(regs.regs(0).sva#1).itm(8)} {slc(regs.regs(0).sva#1).itm(9)} -attr xrf 14162 -attr oid 35 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {slc(regs.regs(0).sva#2).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#2).itm} 10 {slc(regs.regs(0).sva#2).itm(0)} {slc(regs.regs(0).sva#2).itm(1)} {slc(regs.regs(0).sva#2).itm(2)} {slc(regs.regs(0).sva#2).itm(3)} {slc(regs.regs(0).sva#2).itm(4)} {slc(regs.regs(0).sva#2).itm(5)} {slc(regs.regs(0).sva#2).itm(6)} {slc(regs.regs(0).sva#2).itm(7)} {slc(regs.regs(0).sva#2).itm(8)} {slc(regs.regs(0).sva#2).itm(9)} -attr xrf 14163 -attr oid 36 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {ACC1:slc#3.itm(0)} -attr vt d
+load net {ACC1:slc#3.itm(1)} -attr vt d
+load net {ACC1:slc#3.itm(2)} -attr vt d
+load net {ACC1:slc#3.itm(3)} -attr vt d
+load net {ACC1:slc#3.itm(4)} -attr vt d
+load net {ACC1:slc#3.itm(5)} -attr vt d
+load net {ACC1:slc#3.itm(6)} -attr vt d
+load net {ACC1:slc#3.itm(7)} -attr vt d
+load net {ACC1:slc#3.itm(8)} -attr vt d
+load net {ACC1:slc#3.itm(9)} -attr vt d
+load net {ACC1:slc#3.itm(10)} -attr vt d
+load netBundle {ACC1:slc#3.itm} 11 {ACC1:slc#3.itm(0)} {ACC1:slc#3.itm(1)} {ACC1:slc#3.itm(2)} {ACC1:slc#3.itm(3)} {ACC1:slc#3.itm(4)} {ACC1:slc#3.itm(5)} {ACC1:slc#3.itm(6)} {ACC1:slc#3.itm(7)} {ACC1:slc#3.itm(8)} {ACC1:slc#3.itm(9)} {ACC1:slc#3.itm(10)} -attr xrf 14164 -attr oid 37 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#36.itm(0)} -attr vt d
+load net {ACC1:acc#36.itm(1)} -attr vt d
+load net {ACC1:acc#36.itm(2)} -attr vt d
+load net {ACC1:acc#36.itm(3)} -attr vt d
+load net {ACC1:acc#36.itm(4)} -attr vt d
+load net {ACC1:acc#36.itm(5)} -attr vt d
+load net {ACC1:acc#36.itm(6)} -attr vt d
+load net {ACC1:acc#36.itm(7)} -attr vt d
+load net {ACC1:acc#36.itm(8)} -attr vt d
+load net {ACC1:acc#36.itm(9)} -attr vt d
+load net {ACC1:acc#36.itm(10)} -attr vt d
+load net {ACC1:acc#36.itm(11)} -attr vt d
+load netBundle {ACC1:acc#36.itm} 12 {ACC1:acc#36.itm(0)} {ACC1:acc#36.itm(1)} {ACC1:acc#36.itm(2)} {ACC1:acc#36.itm(3)} {ACC1:acc#36.itm(4)} {ACC1:acc#36.itm(5)} {ACC1:acc#36.itm(6)} {ACC1:acc#36.itm(7)} {ACC1:acc#36.itm(8)} {ACC1:acc#36.itm(9)} {ACC1:acc#36.itm(10)} {ACC1:acc#36.itm(11)} -attr xrf 14165 -attr oid 38 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#36.itm}
+load net {conc.itm(0)} -attr vt d
+load net {conc.itm(1)} -attr vt d
+load net {conc.itm(2)} -attr vt d
+load net {conc.itm(3)} -attr vt d
+load net {conc.itm(4)} -attr vt d
+load net {conc.itm(5)} -attr vt d
+load net {conc.itm(6)} -attr vt d
+load net {conc.itm(7)} -attr vt d
+load net {conc.itm(8)} -attr vt d
+load net {conc.itm(9)} -attr vt d
+load net {conc.itm(10)} -attr vt d
+load netBundle {conc.itm} 11 {conc.itm(0)} {conc.itm(1)} {conc.itm(2)} {conc.itm(3)} {conc.itm(4)} {conc.itm(5)} {conc.itm(6)} {conc.itm(7)} {conc.itm(8)} {conc.itm(9)} {conc.itm(10)} -attr xrf 14166 -attr oid 39 -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {conc#50.itm(0)} -attr vt d
+load net {conc#50.itm(1)} -attr vt d
+load net {conc#50.itm(2)} -attr vt d
+load net {conc#50.itm(3)} -attr vt d
+load net {conc#50.itm(4)} -attr vt d
+load net {conc#50.itm(5)} -attr vt d
+load net {conc#50.itm(6)} -attr vt d
+load net {conc#50.itm(7)} -attr vt d
+load net {conc#50.itm(8)} -attr vt d
+load net {conc#50.itm(9)} -attr vt d
+load net {conc#50.itm(10)} -attr vt d
+load netBundle {conc#50.itm} 11 {conc#50.itm(0)} {conc#50.itm(1)} {conc#50.itm(2)} {conc#50.itm(3)} {conc#50.itm(4)} {conc#50.itm(5)} {conc#50.itm(6)} {conc#50.itm(7)} {conc#50.itm(8)} {conc#50.itm(9)} {conc#50.itm(10)} -attr xrf 14167 -attr oid 40 -attr vt d -attr @path {/sobel/sobel:core/conc#50.itm}
+load net {ACC1:acc#40.itm(0)} -attr vt d
+load net {ACC1:acc#40.itm(1)} -attr vt d
+load net {ACC1:acc#40.itm(2)} -attr vt d
+load net {ACC1:acc#40.itm(3)} -attr vt d
+load net {ACC1:acc#40.itm(4)} -attr vt d
+load net {ACC1:acc#40.itm(5)} -attr vt d
+load net {ACC1:acc#40.itm(6)} -attr vt d
+load net {ACC1:acc#40.itm(7)} -attr vt d
+load net {ACC1:acc#40.itm(8)} -attr vt d
+load net {ACC1:acc#40.itm(9)} -attr vt d
+load net {ACC1:acc#40.itm(10)} -attr vt d
+load net {ACC1:acc#40.itm(11)} -attr vt d
+load netBundle {ACC1:acc#40.itm} 12 {ACC1:acc#40.itm(0)} {ACC1:acc#40.itm(1)} {ACC1:acc#40.itm(2)} {ACC1:acc#40.itm(3)} {ACC1:acc#40.itm(4)} {ACC1:acc#40.itm(5)} {ACC1:acc#40.itm(6)} {ACC1:acc#40.itm(7)} {ACC1:acc#40.itm(8)} {ACC1:acc#40.itm(9)} {ACC1:acc#40.itm(10)} {ACC1:acc#40.itm(11)} -attr xrf 14168 -attr oid 41 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:slc#2.itm(0)} -attr vt d
+load net {ACC1:slc#2.itm(1)} -attr vt d
+load net {ACC1:slc#2.itm(2)} -attr vt d
+load net {ACC1:slc#2.itm(3)} -attr vt d
+load net {ACC1:slc#2.itm(4)} -attr vt d
+load net {ACC1:slc#2.itm(5)} -attr vt d
+load net {ACC1:slc#2.itm(6)} -attr vt d
+load net {ACC1:slc#2.itm(7)} -attr vt d
+load net {ACC1:slc#2.itm(8)} -attr vt d
+load net {ACC1:slc#2.itm(9)} -attr vt d
+load net {ACC1:slc#2.itm(10)} -attr vt d
+load netBundle {ACC1:slc#2.itm} 11 {ACC1:slc#2.itm(0)} {ACC1:slc#2.itm(1)} {ACC1:slc#2.itm(2)} {ACC1:slc#2.itm(3)} {ACC1:slc#2.itm(4)} {ACC1:slc#2.itm(5)} {ACC1:slc#2.itm(6)} {ACC1:slc#2.itm(7)} {ACC1:slc#2.itm(8)} {ACC1:slc#2.itm(9)} {ACC1:slc#2.itm(10)} -attr xrf 14169 -attr oid 42 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#35.itm(0)} -attr vt d
+load net {ACC1:acc#35.itm(1)} -attr vt d
+load net {ACC1:acc#35.itm(2)} -attr vt d
+load net {ACC1:acc#35.itm(3)} -attr vt d
+load net {ACC1:acc#35.itm(4)} -attr vt d
+load net {ACC1:acc#35.itm(5)} -attr vt d
+load net {ACC1:acc#35.itm(6)} -attr vt d
+load net {ACC1:acc#35.itm(7)} -attr vt d
+load net {ACC1:acc#35.itm(8)} -attr vt d
+load net {ACC1:acc#35.itm(9)} -attr vt d
+load net {ACC1:acc#35.itm(10)} -attr vt d
+load net {ACC1:acc#35.itm(11)} -attr vt d
+load netBundle {ACC1:acc#35.itm} 12 {ACC1:acc#35.itm(0)} {ACC1:acc#35.itm(1)} {ACC1:acc#35.itm(2)} {ACC1:acc#35.itm(3)} {ACC1:acc#35.itm(4)} {ACC1:acc#35.itm(5)} {ACC1:acc#35.itm(6)} {ACC1:acc#35.itm(7)} {ACC1:acc#35.itm(8)} {ACC1:acc#35.itm(9)} {ACC1:acc#35.itm(10)} {ACC1:acc#35.itm(11)} -attr xrf 14170 -attr oid 43 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35.itm}
+load net {conc#51.itm(0)} -attr vt d
+load net {conc#51.itm(1)} -attr vt d
+load net {conc#51.itm(2)} -attr vt d
+load net {conc#51.itm(3)} -attr vt d
+load net {conc#51.itm(4)} -attr vt d
+load net {conc#51.itm(5)} -attr vt d
+load net {conc#51.itm(6)} -attr vt d
+load net {conc#51.itm(7)} -attr vt d
+load net {conc#51.itm(8)} -attr vt d
+load net {conc#51.itm(9)} -attr vt d
+load net {conc#51.itm(10)} -attr vt d
+load netBundle {conc#51.itm} 11 {conc#51.itm(0)} {conc#51.itm(1)} {conc#51.itm(2)} {conc#51.itm(3)} {conc#51.itm(4)} {conc#51.itm(5)} {conc#51.itm(6)} {conc#51.itm(7)} {conc#51.itm(8)} {conc#51.itm(9)} {conc#51.itm(10)} -attr xrf 14171 -attr oid 44 -attr vt d -attr @path {/sobel/sobel:core/conc#51.itm}
+load net {conc#52.itm(0)} -attr vt d
+load net {conc#52.itm(1)} -attr vt d
+load net {conc#52.itm(2)} -attr vt d
+load net {conc#52.itm(3)} -attr vt d
+load net {conc#52.itm(4)} -attr vt d
+load net {conc#52.itm(5)} -attr vt d
+load net {conc#52.itm(6)} -attr vt d
+load net {conc#52.itm(7)} -attr vt d
+load net {conc#52.itm(8)} -attr vt d
+load net {conc#52.itm(9)} -attr vt d
+load net {conc#52.itm(10)} -attr vt d
+load netBundle {conc#52.itm} 11 {conc#52.itm(0)} {conc#52.itm(1)} {conc#52.itm(2)} {conc#52.itm(3)} {conc#52.itm(4)} {conc#52.itm(5)} {conc#52.itm(6)} {conc#52.itm(7)} {conc#52.itm(8)} {conc#52.itm(9)} {conc#52.itm(10)} -attr xrf 14172 -attr oid 45 -attr vt d -attr @path {/sobel/sobel:core/conc#52.itm}
+load net {ACC1:not.itm(0)} -attr vt d
+load net {ACC1:not.itm(1)} -attr vt d
+load net {ACC1:not.itm(2)} -attr vt d
+load net {ACC1:not.itm(3)} -attr vt d
+load net {ACC1:not.itm(4)} -attr vt d
+load net {ACC1:not.itm(5)} -attr vt d
+load net {ACC1:not.itm(6)} -attr vt d
+load net {ACC1:not.itm(7)} -attr vt d
+load net {ACC1:not.itm(8)} -attr vt d
+load net {ACC1:not.itm(9)} -attr vt d
+load netBundle {ACC1:not.itm} 10 {ACC1:not.itm(0)} {ACC1:not.itm(1)} {ACC1:not.itm(2)} {ACC1:not.itm(3)} {ACC1:not.itm(4)} {ACC1:not.itm(5)} {ACC1:not.itm(6)} {ACC1:not.itm(7)} {ACC1:not.itm(8)} {ACC1:not.itm(9)} -attr xrf 14173 -attr oid 46 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:slc#1.itm(0)} -attr vt d
+load net {ACC1:slc#1.itm(1)} -attr vt d
+load net {ACC1:slc#1.itm(2)} -attr vt d
+load net {ACC1:slc#1.itm(3)} -attr vt d
+load net {ACC1:slc#1.itm(4)} -attr vt d
+load net {ACC1:slc#1.itm(5)} -attr vt d
+load net {ACC1:slc#1.itm(6)} -attr vt d
+load net {ACC1:slc#1.itm(7)} -attr vt d
+load net {ACC1:slc#1.itm(8)} -attr vt d
+load net {ACC1:slc#1.itm(9)} -attr vt d
+load net {ACC1:slc#1.itm(10)} -attr vt d
+load netBundle {ACC1:slc#1.itm} 11 {ACC1:slc#1.itm(0)} {ACC1:slc#1.itm(1)} {ACC1:slc#1.itm(2)} {ACC1:slc#1.itm(3)} {ACC1:slc#1.itm(4)} {ACC1:slc#1.itm(5)} {ACC1:slc#1.itm(6)} {ACC1:slc#1.itm(7)} {ACC1:slc#1.itm(8)} {ACC1:slc#1.itm(9)} {ACC1:slc#1.itm(10)} -attr xrf 14174 -attr oid 47 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc#34.itm(0)} -attr vt d
+load net {ACC1:acc#34.itm(1)} -attr vt d
+load net {ACC1:acc#34.itm(2)} -attr vt d
+load net {ACC1:acc#34.itm(3)} -attr vt d
+load net {ACC1:acc#34.itm(4)} -attr vt d
+load net {ACC1:acc#34.itm(5)} -attr vt d
+load net {ACC1:acc#34.itm(6)} -attr vt d
+load net {ACC1:acc#34.itm(7)} -attr vt d
+load net {ACC1:acc#34.itm(8)} -attr vt d
+load net {ACC1:acc#34.itm(9)} -attr vt d
+load net {ACC1:acc#34.itm(10)} -attr vt d
+load net {ACC1:acc#34.itm(11)} -attr vt d
+load netBundle {ACC1:acc#34.itm} 12 {ACC1:acc#34.itm(0)} {ACC1:acc#34.itm(1)} {ACC1:acc#34.itm(2)} {ACC1:acc#34.itm(3)} {ACC1:acc#34.itm(4)} {ACC1:acc#34.itm(5)} {ACC1:acc#34.itm(6)} {ACC1:acc#34.itm(7)} {ACC1:acc#34.itm(8)} {ACC1:acc#34.itm(9)} {ACC1:acc#34.itm(10)} {ACC1:acc#34.itm(11)} -attr xrf 14175 -attr oid 48 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34.itm}
+load net {conc#53.itm(0)} -attr vt d
+load net {conc#53.itm(1)} -attr vt d
+load net {conc#53.itm(2)} -attr vt d
+load net {conc#53.itm(3)} -attr vt d
+load net {conc#53.itm(4)} -attr vt d
+load net {conc#53.itm(5)} -attr vt d
+load net {conc#53.itm(6)} -attr vt d
+load net {conc#53.itm(7)} -attr vt d
+load net {conc#53.itm(8)} -attr vt d
+load net {conc#53.itm(9)} -attr vt d
+load net {conc#53.itm(10)} -attr vt d
+load netBundle {conc#53.itm} 11 {conc#53.itm(0)} {conc#53.itm(1)} {conc#53.itm(2)} {conc#53.itm(3)} {conc#53.itm(4)} {conc#53.itm(5)} {conc#53.itm(6)} {conc#53.itm(7)} {conc#53.itm(8)} {conc#53.itm(9)} {conc#53.itm(10)} -attr xrf 14176 -attr oid 49 -attr vt d -attr @path {/sobel/sobel:core/conc#53.itm}
+load net {ACC1:not#9.itm(0)} -attr vt d
+load net {ACC1:not#9.itm(1)} -attr vt d
+load net {ACC1:not#9.itm(2)} -attr vt d
+load net {ACC1:not#9.itm(3)} -attr vt d
+load net {ACC1:not#9.itm(4)} -attr vt d
+load net {ACC1:not#9.itm(5)} -attr vt d
+load net {ACC1:not#9.itm(6)} -attr vt d
+load net {ACC1:not#9.itm(7)} -attr vt d
+load net {ACC1:not#9.itm(8)} -attr vt d
+load net {ACC1:not#9.itm(9)} -attr vt d
+load netBundle {ACC1:not#9.itm} 10 {ACC1:not#9.itm(0)} {ACC1:not#9.itm(1)} {ACC1:not#9.itm(2)} {ACC1:not#9.itm(3)} {ACC1:not#9.itm(4)} {ACC1:not#9.itm(5)} {ACC1:not#9.itm(6)} {ACC1:not#9.itm(7)} {ACC1:not#9.itm(8)} {ACC1:not#9.itm(9)} -attr xrf 14177 -attr oid 50 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#9.itm}
+load net {conc#54.itm(0)} -attr vt d
+load net {conc#54.itm(1)} -attr vt d
+load net {conc#54.itm(2)} -attr vt d
+load net {conc#54.itm(3)} -attr vt d
+load net {conc#54.itm(4)} -attr vt d
+load net {conc#54.itm(5)} -attr vt d
+load net {conc#54.itm(6)} -attr vt d
+load net {conc#54.itm(7)} -attr vt d
+load net {conc#54.itm(8)} -attr vt d
+load net {conc#54.itm(9)} -attr vt d
+load net {conc#54.itm(10)} -attr vt d
+load netBundle {conc#54.itm} 11 {conc#54.itm(0)} {conc#54.itm(1)} {conc#54.itm(2)} {conc#54.itm(3)} {conc#54.itm(4)} {conc#54.itm(5)} {conc#54.itm(6)} {conc#54.itm(7)} {conc#54.itm(8)} {conc#54.itm(9)} {conc#54.itm(10)} -attr xrf 14178 -attr oid 51 -attr vt d -attr @path {/sobel/sobel:core/conc#54.itm}
+load net {ACC1:not#10.itm(0)} -attr vt d
+load net {ACC1:not#10.itm(1)} -attr vt d
+load net {ACC1:not#10.itm(2)} -attr vt d
+load net {ACC1:not#10.itm(3)} -attr vt d
+load net {ACC1:not#10.itm(4)} -attr vt d
+load net {ACC1:not#10.itm(5)} -attr vt d
+load net {ACC1:not#10.itm(6)} -attr vt d
+load net {ACC1:not#10.itm(7)} -attr vt d
+load net {ACC1:not#10.itm(8)} -attr vt d
+load net {ACC1:not#10.itm(9)} -attr vt d
+load netBundle {ACC1:not#10.itm} 10 {ACC1:not#10.itm(0)} {ACC1:not#10.itm(1)} {ACC1:not#10.itm(2)} {ACC1:not#10.itm(3)} {ACC1:not#10.itm(4)} {ACC1:not#10.itm(5)} {ACC1:not#10.itm(6)} {ACC1:not#10.itm(7)} {ACC1:not#10.itm(8)} {ACC1:not#10.itm(9)} -attr xrf 14179 -attr oid 52 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#10.itm}
+load net {ACC1:acc#42.itm(0)} -attr vt d
+load net {ACC1:acc#42.itm(1)} -attr vt d
+load net {ACC1:acc#42.itm(2)} -attr vt d
+load net {ACC1:acc#42.itm(3)} -attr vt d
+load net {ACC1:acc#42.itm(4)} -attr vt d
+load net {ACC1:acc#42.itm(5)} -attr vt d
+load net {ACC1:acc#42.itm(6)} -attr vt d
+load net {ACC1:acc#42.itm(7)} -attr vt d
+load net {ACC1:acc#42.itm(8)} -attr vt d
+load net {ACC1:acc#42.itm(9)} -attr vt d
+load net {ACC1:acc#42.itm(10)} -attr vt d
+load net {ACC1:acc#42.itm(11)} -attr vt d
+load netBundle {ACC1:acc#42.itm} 12 {ACC1:acc#42.itm(0)} {ACC1:acc#42.itm(1)} {ACC1:acc#42.itm(2)} {ACC1:acc#42.itm(3)} {ACC1:acc#42.itm(4)} {ACC1:acc#42.itm(5)} {ACC1:acc#42.itm(6)} {ACC1:acc#42.itm(7)} {ACC1:acc#42.itm(8)} {ACC1:acc#42.itm(9)} {ACC1:acc#42.itm(10)} {ACC1:acc#42.itm(11)} -attr xrf 14180 -attr oid 53 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#39.itm(0)} -attr vt d
+load net {ACC1:acc#39.itm(1)} -attr vt d
+load net {ACC1:acc#39.itm(2)} -attr vt d
+load net {ACC1:acc#39.itm(3)} -attr vt d
+load net {ACC1:acc#39.itm(4)} -attr vt d
+load net {ACC1:acc#39.itm(5)} -attr vt d
+load net {ACC1:acc#39.itm(6)} -attr vt d
+load net {ACC1:acc#39.itm(7)} -attr vt d
+load net {ACC1:acc#39.itm(8)} -attr vt d
+load net {ACC1:acc#39.itm(9)} -attr vt d
+load net {ACC1:acc#39.itm(10)} -attr vt d
+load netBundle {ACC1:acc#39.itm} 11 {ACC1:acc#39.itm(0)} {ACC1:acc#39.itm(1)} {ACC1:acc#39.itm(2)} {ACC1:acc#39.itm(3)} {ACC1:acc#39.itm(4)} {ACC1:acc#39.itm(5)} {ACC1:acc#39.itm(6)} {ACC1:acc#39.itm(7)} {ACC1:acc#39.itm(8)} {ACC1:acc#39.itm(9)} {ACC1:acc#39.itm(10)} -attr xrf 14181 -attr oid 54 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {slc(regs.regs(0).sva#3).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#3).itm} 10 {slc(regs.regs(0).sva#3).itm(0)} {slc(regs.regs(0).sva#3).itm(1)} {slc(regs.regs(0).sva#3).itm(2)} {slc(regs.regs(0).sva#3).itm(3)} {slc(regs.regs(0).sva#3).itm(4)} {slc(regs.regs(0).sva#3).itm(5)} {slc(regs.regs(0).sva#3).itm(6)} {slc(regs.regs(0).sva#3).itm(7)} {slc(regs.regs(0).sva#3).itm(8)} {slc(regs.regs(0).sva#3).itm(9)} -attr xrf 14182 -attr oid 55 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {slc(regs.regs(0).sva#4).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#4).itm} 10 {slc(regs.regs(0).sva#4).itm(0)} {slc(regs.regs(0).sva#4).itm(1)} {slc(regs.regs(0).sva#4).itm(2)} {slc(regs.regs(0).sva#4).itm(3)} {slc(regs.regs(0).sva#4).itm(4)} {slc(regs.regs(0).sva#4).itm(5)} {slc(regs.regs(0).sva#4).itm(6)} {slc(regs.regs(0).sva#4).itm(7)} {slc(regs.regs(0).sva#4).itm(8)} {slc(regs.regs(0).sva#4).itm(9)} -attr xrf 14183 -attr oid 56 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:acc#38.itm(0)} -attr vt d
+load net {ACC1:acc#38.itm(1)} -attr vt d
+load net {ACC1:acc#38.itm(2)} -attr vt d
+load net {ACC1:acc#38.itm(3)} -attr vt d
+load net {ACC1:acc#38.itm(4)} -attr vt d
+load net {ACC1:acc#38.itm(5)} -attr vt d
+load net {ACC1:acc#38.itm(6)} -attr vt d
+load net {ACC1:acc#38.itm(7)} -attr vt d
+load net {ACC1:acc#38.itm(8)} -attr vt d
+load net {ACC1:acc#38.itm(9)} -attr vt d
+load net {ACC1:acc#38.itm(10)} -attr vt d
+load netBundle {ACC1:acc#38.itm} 11 {ACC1:acc#38.itm(0)} {ACC1:acc#38.itm(1)} {ACC1:acc#38.itm(2)} {ACC1:acc#38.itm(3)} {ACC1:acc#38.itm(4)} {ACC1:acc#38.itm(5)} {ACC1:acc#38.itm(6)} {ACC1:acc#38.itm(7)} {ACC1:acc#38.itm(8)} {ACC1:acc#38.itm(9)} {ACC1:acc#38.itm(10)} -attr xrf 14184 -attr oid 57 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {slc(regs.regs(0).sva#5).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#5).itm} 10 {slc(regs.regs(0).sva#5).itm(0)} {slc(regs.regs(0).sva#5).itm(1)} {slc(regs.regs(0).sva#5).itm(2)} {slc(regs.regs(0).sva#5).itm(3)} {slc(regs.regs(0).sva#5).itm(4)} {slc(regs.regs(0).sva#5).itm(5)} {slc(regs.regs(0).sva#5).itm(6)} {slc(regs.regs(0).sva#5).itm(7)} {slc(regs.regs(0).sva#5).itm(8)} {slc(regs.regs(0).sva#5).itm(9)} -attr xrf 14185 -attr oid 58 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {slc(regs.regs(0).sva#6).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#6).itm} 10 {slc(regs.regs(0).sva#6).itm(0)} {slc(regs.regs(0).sva#6).itm(1)} {slc(regs.regs(0).sva#6).itm(2)} {slc(regs.regs(0).sva#6).itm(3)} {slc(regs.regs(0).sva#6).itm(4)} {slc(regs.regs(0).sva#6).itm(5)} {slc(regs.regs(0).sva#6).itm(6)} {slc(regs.regs(0).sva#6).itm(7)} {slc(regs.regs(0).sva#6).itm(8)} {slc(regs.regs(0).sva#6).itm(9)} -attr xrf 14186 -attr oid 59 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {FRAME:mul#3.itm(0)} -attr vt d
+load net {FRAME:mul#3.itm(1)} -attr vt d
+load net {FRAME:mul#3.itm(2)} -attr vt d
+load net {FRAME:mul#3.itm(3)} -attr vt d
+load net {FRAME:mul#3.itm(4)} -attr vt d
+load net {FRAME:mul#3.itm(5)} -attr vt d
+load net {FRAME:mul#3.itm(6)} -attr vt d
+load net {FRAME:mul#3.itm(7)} -attr vt d
+load net {FRAME:mul#3.itm(8)} -attr vt d
+load netBundle {FRAME:mul#3.itm} 9 {FRAME:mul#3.itm(0)} {FRAME:mul#3.itm(1)} {FRAME:mul#3.itm(2)} {FRAME:mul#3.itm(3)} {FRAME:mul#3.itm(4)} {FRAME:mul#3.itm(5)} {FRAME:mul#3.itm(6)} {FRAME:mul#3.itm(7)} {FRAME:mul#3.itm(8)} -attr xrf 14187 -attr oid 60 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {slc(ACC1:slc.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#1.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#1.itm(2)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#1.itm(3)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#1.itm} 4 {slc(ACC1:slc.psp.sva)#1.itm(0)} {slc(ACC1:slc.psp.sva)#1.itm(1)} {slc(ACC1:slc.psp.sva)#1.itm(2)} {slc(ACC1:slc.psp.sva)#1.itm(3)} -attr xrf 14188 -attr oid 61 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#1.itm}
+load net {FRAME:acc#21.itm(0)} -attr vt d
+load net {FRAME:acc#21.itm(1)} -attr vt d
+load net {FRAME:acc#21.itm(2)} -attr vt d
+load net {FRAME:acc#21.itm(3)} -attr vt d
+load net {FRAME:acc#21.itm(4)} -attr vt d
+load net {FRAME:acc#21.itm(5)} -attr vt d
+load netBundle {FRAME:acc#21.itm} 6 {FRAME:acc#21.itm(0)} {FRAME:acc#21.itm(1)} {FRAME:acc#21.itm(2)} {FRAME:acc#21.itm(3)} {FRAME:acc#21.itm(4)} {FRAME:acc#21.itm(5)} -attr xrf 14189 -attr oid 62 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#20.itm(0)} -attr vt d
+load net {FRAME:acc#20.itm(1)} -attr vt d
+load net {FRAME:acc#20.itm(2)} -attr vt d
+load net {FRAME:acc#20.itm(3)} -attr vt d
+load netBundle {FRAME:acc#20.itm} 4 {FRAME:acc#20.itm(0)} {FRAME:acc#20.itm(1)} {FRAME:acc#20.itm(2)} {FRAME:acc#20.itm(3)} -attr xrf 14190 -attr oid 63 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#19.itm(0)} -attr vt d
+load net {FRAME:acc#19.itm(1)} -attr vt d
+load net {FRAME:acc#19.itm(2)} -attr vt d
+load netBundle {FRAME:acc#19.itm} 3 {FRAME:acc#19.itm(0)} {FRAME:acc#19.itm(1)} {FRAME:acc#19.itm(2)} -attr xrf 14191 -attr oid 64 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#17.itm(0)} -attr vt d
+load net {FRAME:acc#17.itm(1)} -attr vt d
+load netBundle {FRAME:acc#17.itm} 2 {FRAME:acc#17.itm(0)} {FRAME:acc#17.itm(1)} -attr xrf 14192 -attr oid 65 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {slc(ACC1:slc.psp.sva)#20.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#20.itm(1)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#20.itm} 2 {slc(ACC1:slc.psp.sva)#20.itm(0)} {slc(ACC1:slc.psp.sva)#20.itm(1)} -attr xrf 14193 -attr oid 66 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#20.itm}
+load net {FRAME:acc#18.itm(0)} -attr vt d
+load net {FRAME:acc#18.itm(1)} -attr vt d
+load net {FRAME:acc#18.itm(2)} -attr vt d
+load netBundle {FRAME:acc#18.itm} 3 {FRAME:acc#18.itm(0)} {FRAME:acc#18.itm(1)} {FRAME:acc#18.itm(2)} -attr xrf 14194 -attr oid 67 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {slc(acc.imod.sva)#6.itm(0)} -attr vt d
+load net {slc(acc.imod.sva)#6.itm(1)} -attr vt d
+load netBundle {slc(acc.imod.sva)#6.itm} 2 {slc(acc.imod.sva)#6.itm(0)} {slc(acc.imod.sva)#6.itm(1)} -attr xrf 14195 -attr oid 68 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#6.itm}
+load net {FRAME:acc#16.itm(0)} -attr vt d
+load net {FRAME:acc#16.itm(1)} -attr vt d
+load net {FRAME:acc#16.itm(2)} -attr vt d
+load net {FRAME:acc#16.itm(3)} -attr vt d
+load net {FRAME:acc#16.itm(4)} -attr vt d
+load netBundle {FRAME:acc#16.itm} 5 {FRAME:acc#16.itm(0)} {FRAME:acc#16.itm(1)} {FRAME:acc#16.itm(2)} {FRAME:acc#16.itm(3)} {FRAME:acc#16.itm(4)} -attr xrf 14196 -attr oid 69 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {conc#55.itm(0)} -attr vt d
+load net {conc#55.itm(1)} -attr vt d
+load net {conc#55.itm(2)} -attr vt d
+load net {conc#55.itm(3)} -attr vt d
+load net {conc#55.itm(4)} -attr vt d
+load netBundle {conc#55.itm} 5 {conc#55.itm(0)} {conc#55.itm(1)} {conc#55.itm(2)} {conc#55.itm(3)} {conc#55.itm(4)} -attr xrf 14197 -attr oid 70 -attr vt d -attr @path {/sobel/sobel:core/conc#55.itm}
+load net {slc(acc.imod.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod.sva)#4.itm(1)} -attr vt d
+load net {slc(acc.imod.sva)#4.itm(2)} -attr vt d
+load net {slc(acc.imod.sva)#4.itm(3)} -attr vt d
+load netBundle {slc(acc.imod.sva)#4.itm} 4 {slc(acc.imod.sva)#4.itm(0)} {slc(acc.imod.sva)#4.itm(1)} {slc(acc.imod.sva)#4.itm(2)} {slc(acc.imod.sva)#4.itm(3)} -attr xrf 14198 -attr oid 71 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#4.itm}
+load net {FRAME:conc#30.itm(0)} -attr vt d
+load net {FRAME:conc#30.itm(1)} -attr vt d
+load net {FRAME:conc#30.itm(2)} -attr vt d
+load net {FRAME:conc#30.itm(3)} -attr vt d
+load net {FRAME:conc#30.itm(4)} -attr vt d
+load netBundle {FRAME:conc#30.itm} 5 {FRAME:conc#30.itm(0)} {FRAME:conc#30.itm(1)} {FRAME:conc#30.itm(2)} {FRAME:conc#30.itm(3)} {FRAME:conc#30.itm(4)} -attr xrf 14199 -attr oid 72 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#30.itm}
+load net {FRAME:acc#32.itm(0)} -attr vt d
+load net {FRAME:acc#32.itm(1)} -attr vt d
+load net {FRAME:acc#32.itm(2)} -attr vt d
+load netBundle {FRAME:acc#32.itm} 3 {FRAME:acc#32.itm(0)} {FRAME:acc#32.itm(1)} {FRAME:acc#32.itm(2)} -attr xrf 14200 -attr oid 73 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {slc(acc.imod.sva)#7.itm(0)} -attr vt d
+load net {slc(acc.imod.sva)#7.itm(1)} -attr vt d
+load netBundle {slc(acc.imod.sva)#7.itm} 2 {slc(acc.imod.sva)#7.itm(0)} {slc(acc.imod.sva)#7.itm(1)} -attr xrf 14201 -attr oid 74 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#7.itm}
+load net {slc(acc.imod.sva)#3.itm(0)} -attr vt d
+load net {slc(acc.imod.sva)#3.itm(1)} -attr vt d
+load netBundle {slc(acc.imod.sva)#3.itm} 2 {slc(acc.imod.sva)#3.itm(0)} {slc(acc.imod.sva)#3.itm(1)} -attr xrf 14202 -attr oid 75 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#3.itm}
+load net {slc(ACC1:slc.psp.sva)#4.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#4.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#4.itm(2)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#4.itm(3)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#4.itm} 4 {slc(ACC1:slc.psp.sva)#4.itm(0)} {slc(ACC1:slc.psp.sva)#4.itm(1)} {slc(ACC1:slc.psp.sva)#4.itm(2)} {slc(ACC1:slc.psp.sva)#4.itm(3)} -attr xrf 14203 -attr oid 76 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#4.itm}
+load net {FRAME:acc#14.itm(0)} -attr vt d
+load net {FRAME:acc#14.itm(1)} -attr vt d
+load net {FRAME:acc#14.itm(2)} -attr vt d
+load net {FRAME:acc#14.itm(3)} -attr vt d
+load net {FRAME:acc#14.itm(4)} -attr vt d
+load net {FRAME:acc#14.itm(5)} -attr vt d
+load net {FRAME:acc#14.itm(6)} -attr vt d
+load netBundle {FRAME:acc#14.itm} 7 {FRAME:acc#14.itm(0)} {FRAME:acc#14.itm(1)} {FRAME:acc#14.itm(2)} {FRAME:acc#14.itm(3)} {FRAME:acc#14.itm(4)} {FRAME:acc#14.itm(5)} {FRAME:acc#14.itm(6)} -attr xrf 14204 -attr oid 77 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#13.itm(0)} -attr vt d
+load net {FRAME:acc#13.itm(1)} -attr vt d
+load net {FRAME:acc#13.itm(2)} -attr vt d
+load net {FRAME:acc#13.itm(3)} -attr vt d
+load net {FRAME:acc#13.itm(4)} -attr vt d
+load net {FRAME:acc#13.itm(5)} -attr vt d
+load netBundle {FRAME:acc#13.itm} 6 {FRAME:acc#13.itm(0)} {FRAME:acc#13.itm(1)} {FRAME:acc#13.itm(2)} {FRAME:acc#13.itm(3)} {FRAME:acc#13.itm(4)} {FRAME:acc#13.itm(5)} -attr xrf 14205 -attr oid 78 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#11.itm(0)} -attr vt d
+load net {FRAME:acc#11.itm(1)} -attr vt d
+load net {FRAME:acc#11.itm(2)} -attr vt d
+load net {FRAME:acc#11.itm(3)} -attr vt d
+load net {FRAME:acc#11.itm(4)} -attr vt d
+load netBundle {FRAME:acc#11.itm} 5 {FRAME:acc#11.itm(0)} {FRAME:acc#11.itm(1)} {FRAME:acc#11.itm(2)} {FRAME:acc#11.itm(3)} {FRAME:acc#11.itm(4)} -attr xrf 14206 -attr oid 79 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:conc#27.itm(0)} -attr vt d
+load net {FRAME:conc#27.itm(1)} -attr vt d
+load net {FRAME:conc#27.itm(2)} -attr vt d
+load net {FRAME:conc#27.itm(3)} -attr vt d
+load netBundle {FRAME:conc#27.itm} 4 {FRAME:conc#27.itm(0)} {FRAME:conc#27.itm(1)} {FRAME:conc#27.itm(2)} {FRAME:conc#27.itm(3)} -attr xrf 14207 -attr oid 80 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#27.itm}
+load net {slc(ACC1:slc.psp.sva)#16.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#16.itm(1)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#16.itm} 2 {slc(ACC1:slc.psp.sva)#16.itm(0)} {slc(ACC1:slc.psp.sva)#16.itm(1)} -attr xrf 14208 -attr oid 81 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#16.itm}
+load net {slc(ACC1:slc.psp.sva)#5.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#5.itm(1)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#5.itm} 2 {slc(ACC1:slc.psp.sva)#5.itm(0)} {slc(ACC1:slc.psp.sva)#5.itm(1)} -attr xrf 14209 -attr oid 82 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#5.itm}
+load net {FRAME:conc#29.itm(0)} -attr vt d
+load net {FRAME:conc#29.itm(1)} -attr vt d
+load net {FRAME:conc#29.itm(2)} -attr vt d
+load netBundle {FRAME:conc#29.itm} 3 {FRAME:conc#29.itm(0)} {FRAME:conc#29.itm(1)} {FRAME:conc#29.itm(2)} -attr xrf 14210 -attr oid 83 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:acc#31.itm(0)} -attr vt d
+load net {FRAME:acc#31.itm(1)} -attr vt d
+load netBundle {FRAME:acc#31.itm} 2 {FRAME:acc#31.itm(0)} {FRAME:acc#31.itm(1)} -attr xrf 14211 -attr oid 84 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#31.itm}
+load net {conc#56.itm(0)} -attr vt d
+load net {conc#56.itm(1)} -attr vt d
+load net {conc#56.itm(2)} -attr vt d
+load net {conc#56.itm(3)} -attr vt d
+load net {conc#56.itm(4)} -attr vt d
+load netBundle {conc#56.itm} 5 {conc#56.itm(0)} {conc#56.itm(1)} {conc#56.itm(2)} {conc#56.itm(3)} {conc#56.itm(4)} -attr xrf 14212 -attr oid 85 -attr vt d -attr @path {/sobel/sobel:core/conc#56.itm}
+load net {FRAME:acc#12.itm(0)} -attr vt d
+load net {FRAME:acc#12.itm(1)} -attr vt d
+load net {FRAME:acc#12.itm(2)} -attr vt d
+load net {FRAME:acc#12.itm(3)} -attr vt d
+load net {FRAME:acc#12.itm(4)} -attr vt d
+load net {FRAME:acc#12.itm(5)} -attr vt d
+load netBundle {FRAME:acc#12.itm} 6 {FRAME:acc#12.itm(0)} {FRAME:acc#12.itm(1)} {FRAME:acc#12.itm(2)} {FRAME:acc#12.itm(3)} {FRAME:acc#12.itm(4)} {FRAME:acc#12.itm(5)} -attr xrf 14213 -attr oid 86 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:conc#28.itm(0)} -attr vt d
+load net {FRAME:conc#28.itm(1)} -attr vt d
+load net {FRAME:conc#28.itm(2)} -attr vt d
+load net {FRAME:conc#28.itm(3)} -attr vt d
+load net {FRAME:conc#28.itm(4)} -attr vt d
+load netBundle {FRAME:conc#28.itm} 5 {FRAME:conc#28.itm(0)} {FRAME:conc#28.itm(1)} {FRAME:conc#28.itm(2)} {FRAME:conc#28.itm(3)} {FRAME:conc#28.itm(4)} -attr xrf 14214 -attr oid 87 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#28.itm}
+load net {FRAME:not#20.itm(0)} -attr vt d
+load net {FRAME:not#20.itm(1)} -attr vt d
+load netBundle {FRAME:not#20.itm} 2 {FRAME:not#20.itm(0)} {FRAME:not#20.itm(1)} -attr xrf 14215 -attr oid 88 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load net {slc(ACC1:slc.psp.sva)#3.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#3.itm(1)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#3.itm} 2 {slc(ACC1:slc.psp.sva)#3.itm(0)} {slc(ACC1:slc.psp.sva)#3.itm(1)} -attr xrf 14216 -attr oid 89 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#3.itm}
+load net {FRAME:not#21.itm(0)} -attr vt d
+load net {FRAME:not#21.itm(1)} -attr vt d
+load net {FRAME:not#21.itm(2)} -attr vt d
+load netBundle {FRAME:not#21.itm} 3 {FRAME:not#21.itm(0)} {FRAME:not#21.itm(1)} {FRAME:not#21.itm(2)} -attr xrf 14217 -attr oid 90 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {slc(ACC1:slc.psp.sva)#8.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#8.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#8.itm(2)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#8.itm} 3 {slc(ACC1:slc.psp.sva)#8.itm(0)} {slc(ACC1:slc.psp.sva)#8.itm(1)} {slc(ACC1:slc.psp.sva)#8.itm(2)} -attr xrf 14218 -attr oid 91 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#8.itm}
+load net {slc(ACC1:slc.psp.sva)#9.itm(0)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#9.itm(1)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#9.itm(2)} -attr vt d
+load net {slc(ACC1:slc.psp.sva)#9.itm(3)} -attr vt d
+load netBundle {slc(ACC1:slc.psp.sva)#9.itm} 4 {slc(ACC1:slc.psp.sva)#9.itm(0)} {slc(ACC1:slc.psp.sva)#9.itm(1)} {slc(ACC1:slc.psp.sva)#9.itm(2)} {slc(ACC1:slc.psp.sva)#9.itm(3)} -attr xrf 14219 -attr oid 92 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#9.itm}
+load net {FRAME:acc#33.itm(0)} -attr vt d
+load net {FRAME:acc#33.itm(1)} -attr vt d
+load net {FRAME:acc#33.itm(2)} -attr vt d
+load net {FRAME:acc#33.itm(3)} -attr vt d
+load net {FRAME:acc#33.itm(4)} -attr vt d
+load net {FRAME:acc#33.itm(5)} -attr vt d
+load net {FRAME:acc#33.itm(6)} -attr vt d
+load net {FRAME:acc#33.itm(7)} -attr vt d
+load netBundle {FRAME:acc#33.itm} 8 {FRAME:acc#33.itm(0)} {FRAME:acc#33.itm(1)} {FRAME:acc#33.itm(2)} {FRAME:acc#33.itm(3)} {FRAME:acc#33.itm(4)} {FRAME:acc#33.itm(5)} {FRAME:acc#33.itm(6)} {FRAME:acc#33.itm(7)} -attr xrf 14220 -attr oid 93 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {conc#57.itm(0)} -attr vt d
+load net {conc#57.itm(1)} -attr vt d
+load net {conc#57.itm(2)} -attr vt d
+load net {conc#57.itm(3)} -attr vt d
+load net {conc#57.itm(4)} -attr vt d
+load net {conc#57.itm(5)} -attr vt d
+load net {conc#57.itm(6)} -attr vt d
+load netBundle {conc#57.itm} 7 {conc#57.itm(0)} {conc#57.itm(1)} {conc#57.itm(2)} {conc#57.itm(3)} {conc#57.itm(4)} {conc#57.itm(5)} {conc#57.itm(6)} -attr xrf 14221 -attr oid 94 -attr vt d -attr @path {/sobel/sobel:core/conc#57.itm}
+load net {FRAME:exs#4.itm(0)} -attr vt d
+load net {FRAME:exs#4.itm(1)} -attr vt d
+load net {FRAME:exs#4.itm(2)} -attr vt d
+load net {FRAME:exs#4.itm(3)} -attr vt d
+load net {FRAME:exs#4.itm(4)} -attr vt d
+load netBundle {FRAME:exs#4.itm} 5 {FRAME:exs#4.itm(0)} {FRAME:exs#4.itm(1)} {FRAME:exs#4.itm(2)} {FRAME:exs#4.itm(3)} {FRAME:exs#4.itm(4)} -attr xrf 14222 -attr oid 95 -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#4.itm}
+load net {conc#58.itm(0)} -attr vt d
+load net {conc#58.itm(1)} -attr vt d
+load net {conc#58.itm(2)} -attr vt d
+load net {conc#58.itm(3)} -attr vt d
+load net {conc#58.itm(4)} -attr vt d
+load net {conc#58.itm(5)} -attr vt d
+load netBundle {conc#58.itm} 6 {conc#58.itm(0)} {conc#58.itm(1)} {conc#58.itm(2)} {conc#58.itm(3)} {conc#58.itm(4)} {conc#58.itm(5)} -attr xrf 14223 -attr oid 96 -attr vt d -attr @path {/sobel/sobel:core/conc#58.itm}
+load net {FRAME:exs#5.itm(0)} -attr vt d
+load net {FRAME:exs#5.itm(1)} -attr vt d
+load net {FRAME:exs#5.itm(2)} -attr vt d
+load net {FRAME:exs#5.itm(3)} -attr vt d
+load netBundle {FRAME:exs#5.itm} 4 {FRAME:exs#5.itm(0)} {FRAME:exs#5.itm(1)} {FRAME:exs#5.itm(2)} {FRAME:exs#5.itm(3)} -attr xrf 14224 -attr oid 97 -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#5.itm}
+load net {FRAME:or.itm(0)} -attr vt d
+load net {FRAME:or.itm(1)} -attr vt d
+load net {FRAME:or.itm(2)} -attr vt d
+load net {FRAME:or.itm(3)} -attr vt d
+load net {FRAME:or.itm(4)} -attr vt d
+load net {FRAME:or.itm(5)} -attr vt d
+load net {FRAME:or.itm(6)} -attr vt d
+load net {FRAME:or.itm(7)} -attr vt d
+load net {FRAME:or.itm(8)} -attr vt d
+load net {FRAME:or.itm(9)} -attr vt d
+load netBundle {FRAME:or.itm} 10 {FRAME:or.itm(0)} {FRAME:or.itm(1)} {FRAME:or.itm(2)} {FRAME:or.itm(3)} {FRAME:or.itm(4)} {FRAME:or.itm(5)} {FRAME:or.itm(6)} {FRAME:or.itm(7)} {FRAME:or.itm(8)} {FRAME:or.itm(9)} -attr xrf 14225 -attr oid 98 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:acc#3.itm(0)} -attr vt d
+load net {FRAME:acc#3.itm(1)} -attr vt d
+load net {FRAME:acc#3.itm(2)} -attr vt d
+load net {FRAME:acc#3.itm(3)} -attr vt d
+load net {FRAME:acc#3.itm(4)} -attr vt d
+load net {FRAME:acc#3.itm(5)} -attr vt d
+load net {FRAME:acc#3.itm(6)} -attr vt d
+load net {FRAME:acc#3.itm(7)} -attr vt d
+load net {FRAME:acc#3.itm(8)} -attr vt d
+load net {FRAME:acc#3.itm(9)} -attr vt d
+load netBundle {FRAME:acc#3.itm} 10 {FRAME:acc#3.itm(0)} {FRAME:acc#3.itm(1)} {FRAME:acc#3.itm(2)} {FRAME:acc#3.itm(3)} {FRAME:acc#3.itm(4)} {FRAME:acc#3.itm(5)} {FRAME:acc#3.itm(6)} {FRAME:acc#3.itm(7)} {FRAME:acc#3.itm(8)} {FRAME:acc#3.itm(9)} -attr xrf 14226 -attr oid 99 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {conc#59.itm(0)} -attr vt d
+load net {conc#59.itm(1)} -attr vt d
+load net {conc#59.itm(2)} -attr vt d
+load net {conc#59.itm(3)} -attr vt d
+load net {conc#59.itm(4)} -attr vt d
+load net {conc#59.itm(5)} -attr vt d
+load net {conc#59.itm(6)} -attr vt d
+load net {conc#59.itm(7)} -attr vt d
+load net {conc#59.itm(8)} -attr vt d
+load net {conc#59.itm(9)} -attr vt d
+load netBundle {conc#59.itm} 10 {conc#59.itm(0)} {conc#59.itm(1)} {conc#59.itm(2)} {conc#59.itm(3)} {conc#59.itm(4)} {conc#59.itm(5)} {conc#59.itm(6)} {conc#59.itm(7)} {conc#59.itm(8)} {conc#59.itm(9)} -attr xrf 14227 -attr oid 100 -attr vt d -attr @path {/sobel/sobel:core/conc#59.itm}
+load net {FRAME:or#3.itm(0)} -attr vt d
+load net {FRAME:or#3.itm(1)} -attr vt d
+load net {FRAME:or#3.itm(2)} -attr vt d
+load net {FRAME:or#3.itm(3)} -attr vt d
+load net {FRAME:or#3.itm(4)} -attr vt d
+load net {FRAME:or#3.itm(5)} -attr vt d
+load netBundle {FRAME:or#3.itm} 6 {FRAME:or#3.itm(0)} {FRAME:or#3.itm(1)} {FRAME:or#3.itm(2)} {FRAME:or#3.itm(3)} {FRAME:or#3.itm(4)} {FRAME:or#3.itm(5)} -attr xrf 14228 -attr oid 101 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {slc(FRAME:acc#5.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#2.itm(2)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#2.itm(3)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#2.itm(4)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(FRAME:acc#5.psp.sva)#2.itm} 6 {slc(FRAME:acc#5.psp.sva)#2.itm(0)} {slc(FRAME:acc#5.psp.sva)#2.itm(1)} {slc(FRAME:acc#5.psp.sva)#2.itm(2)} {slc(FRAME:acc#5.psp.sva)#2.itm(3)} {slc(FRAME:acc#5.psp.sva)#2.itm(4)} {slc(FRAME:acc#5.psp.sva)#2.itm(5)} -attr xrf 14229 -attr oid 102 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#2.itm}
+load net {conc#60.itm(0)} -attr vt d
+load net {conc#60.itm(1)} -attr vt d
+load net {conc#60.itm(2)} -attr vt d
+load net {conc#60.itm(3)} -attr vt d
+load net {conc#60.itm(4)} -attr vt d
+load net {conc#60.itm(5)} -attr vt d
+load netBundle {conc#60.itm} 6 {conc#60.itm(0)} {conc#60.itm(1)} {conc#60.itm(2)} {conc#60.itm(3)} {conc#60.itm(4)} {conc#60.itm(5)} -attr xrf 14230 -attr oid 103 -attr vt d -attr @path {/sobel/sobel:core/conc#60.itm}
+load net {slc(FRAME:acc#5.psp.sva)#3.itm(0)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#3.itm(1)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#3.itm(2)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#3.itm(3)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#3.itm(4)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#3.itm(5)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#3.itm(6)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#3.itm(7)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#3.itm(8)} -attr vt d
+load net {slc(FRAME:acc#5.psp.sva)#3.itm(9)} -attr vt d
+load netBundle {slc(FRAME:acc#5.psp.sva)#3.itm} 10 {slc(FRAME:acc#5.psp.sva)#3.itm(0)} {slc(FRAME:acc#5.psp.sva)#3.itm(1)} {slc(FRAME:acc#5.psp.sva)#3.itm(2)} {slc(FRAME:acc#5.psp.sva)#3.itm(3)} {slc(FRAME:acc#5.psp.sva)#3.itm(4)} {slc(FRAME:acc#5.psp.sva)#3.itm(5)} {slc(FRAME:acc#5.psp.sva)#3.itm(6)} {slc(FRAME:acc#5.psp.sva)#3.itm(7)} {slc(FRAME:acc#5.psp.sva)#3.itm(8)} {slc(FRAME:acc#5.psp.sva)#3.itm(9)} -attr xrf 14231 -attr oid 104 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {clk} -attr xrf 14232 -attr oid 105
+load net {clk} -port {clk} -attr xrf 14233 -attr oid 106
+load net {en} -attr xrf 14234 -attr oid 107
+load net {en} -port {en} -attr xrf 14235 -attr oid 108
+load net {arst_n} -attr xrf 14236 -attr oid 109
+load net {arst_n} -port {arst_n} -attr xrf 14237 -attr oid 110
+load net {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 14238 -attr oid 111 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(0)} -port {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -port {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -port {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -port {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -port {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -port {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -port {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -port {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -port {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -port {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -port {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -port {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -port {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -port {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -port {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -port {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -port {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -port {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -port {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -port {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -port {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -port {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -port {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -port {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -port {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -port {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -port {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -port {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -port {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -port {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -port {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -port {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -port {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -port {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -port {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -port {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -port {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -port {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -port {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -port {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -port {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -port {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -port {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -port {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -port {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -port {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -port {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -port {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -port {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -port {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -port {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -port {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -port {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -port {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -port {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -port {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -port {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -port {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -port {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -port {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -port {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -port {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -port {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -port {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -port {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -port {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -port {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -port {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -port {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -port {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -port {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -port {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -port {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -port {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -port {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -port {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -port {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -port {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -port {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -port {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -port {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -port {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -port {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -port {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -port {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -port {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -port {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -port {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -port {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -port {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 14239 -attr oid 112 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d} 30 {vout:rsc:mgc_out_stdreg.d(0)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(29)} -attr xrf 14240 -attr oid 113 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(0)} -port {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(1)} -port {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(2)} -port {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(3)} -port {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(4)} -port {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(5)} -port {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(6)} -port {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(7)} -port {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(8)} -port {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(9)} -port {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(0)} -port {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(1)} -port {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(2)} -port {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(3)} -port {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(4)} -port {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(5)} -port {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(6)} -port {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(7)} -port {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(8)} -port {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(9)} -port {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(0)} -port {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(1)} -port {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(2)} -port {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(3)} -port {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(4)} -port {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(5)} -port {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(6)} -port {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(7)} -port {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(8)} -port {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(9)} -port {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "reg(ACC1:slc(regs.regs(2).sg2).itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 14241 -attr oid 114 -attr vt dc -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2).sg2).itm)}
+load net {regs.regs(1).sg2.sva(0)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(1)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(2)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(3)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(4)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(5)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(6)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(7)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(8)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(9)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {clk} -attr xrf 14242 -attr oid 115 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2).sg2).itm(0)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2).itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(1)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2).itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(2)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2).itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(3)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2).itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(4)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2).itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(5)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2).itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(6)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2).itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(7)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2).itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(8)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2).itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(9)} -pin  "reg(ACC1:slc(regs.regs(2).sg2).itm)" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2).itm}
+load inst "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 14243 -attr oid 116 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2).sg2)#1.itm)}
+load net {regs.regs(1).sg2.sva(10)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(11)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(12)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(13)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(14)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(15)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(16)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(17)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(18)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(19)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {clk} -attr xrf 14244 -attr oid 117 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(0)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#1.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(1)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#1.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(2)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#1.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(3)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#1.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(4)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#1.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(5)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#1.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(6)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#1.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(7)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#1.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(8)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#1.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(9)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#1.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#1.itm}
+load inst "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 14245 -attr oid 118 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2).sg2)#2.itm)}
+load net {regs.regs(1).sg2.sva(20)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(21)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(22)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(23)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(24)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(25)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(26)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(27)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(28)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(29)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {clk} -attr xrf 14246 -attr oid 119 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(0)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#2.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(1)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#2.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(2)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#2.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(3)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#2.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(4)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#2.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(5)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#2.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(6)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#2.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(7)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#2.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(8)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#2.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(9)} -pin  "reg(ACC1:slc(regs.regs(2).sg2)#2.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2).sg2)#2.itm}
+load inst "reg(ACC1:slc(regs.regs(2)#1).itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 14247 -attr oid 120 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2)#1).itm)}
+load net {regs.regs(1)#1.sva(0)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(1)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(2)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(3)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(4)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(5)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(6)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(7)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(8)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(9)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {clk} -attr xrf 14248 -attr oid 121 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2)#1).itm(0)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(1)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(2)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(3)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(4)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(5)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(6)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(7)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(8)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(9)} -pin  "reg(ACC1:slc(regs.regs(2)#1).itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load inst "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 14249 -attr oid 122 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2)#1)#1.itm)}
+load net {regs.regs(1)#1.sva(10)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(11)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(12)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(13)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(14)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(15)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(16)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(17)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(18)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(19)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {clk} -attr xrf 14250 -attr oid 123 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(0)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(1)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(2)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(3)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(4)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(5)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(6)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(7)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(8)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(9)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#1.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load inst "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 14251 -attr oid 124 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:slc(regs.regs(2)#1)#2.itm)}
+load net {regs.regs(1)#1.sva(20)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(21)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(22)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(23)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(24)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(25)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(26)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(27)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(28)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(29)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {clk} -attr xrf 14252 -attr oid 125 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(0)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(1)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(2)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(3)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(4)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(5)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(6)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(7)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(8)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(9)} -pin  "reg(ACC1:slc(regs.regs(2)#1)#2.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load inst "reg(regs.regs(1)#1.sva)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 14253 -attr oid 126 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(1)#1.sva)}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "reg(regs.regs(1)#1.sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "reg(regs.regs(1)#1.sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "reg(regs.regs(1)#1.sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "reg(regs.regs(1)#1.sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "reg(regs.regs(1)#1.sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "reg(regs.regs(1)#1.sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "reg(regs.regs(1)#1.sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "reg(regs.regs(1)#1.sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "reg(regs.regs(1)#1.sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "reg(regs.regs(1)#1.sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "reg(regs.regs(1)#1.sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "reg(regs.regs(1)#1.sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "reg(regs.regs(1)#1.sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "reg(regs.regs(1)#1.sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "reg(regs.regs(1)#1.sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "reg(regs.regs(1)#1.sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "reg(regs.regs(1)#1.sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "reg(regs.regs(1)#1.sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "reg(regs.regs(1)#1.sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "reg(regs.regs(1)#1.sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "reg(regs.regs(1)#1.sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "reg(regs.regs(1)#1.sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "reg(regs.regs(1)#1.sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "reg(regs.regs(1)#1.sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "reg(regs.regs(1)#1.sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "reg(regs.regs(1)#1.sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "reg(regs.regs(1)#1.sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "reg(regs.regs(1)#1.sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "reg(regs.regs(1)#1.sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "reg(regs.regs(1)#1.sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(regs.regs(1)#1.sva)" {clk} -attr xrf 14254 -attr oid 127 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(1)#1.sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(1)#1.sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(1)#1.sva(0)} -pin  "reg(regs.regs(1)#1.sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(1)} -pin  "reg(regs.regs(1)#1.sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(2)} -pin  "reg(regs.regs(1)#1.sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(3)} -pin  "reg(regs.regs(1)#1.sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(4)} -pin  "reg(regs.regs(1)#1.sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(5)} -pin  "reg(regs.regs(1)#1.sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(6)} -pin  "reg(regs.regs(1)#1.sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(7)} -pin  "reg(regs.regs(1)#1.sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(8)} -pin  "reg(regs.regs(1)#1.sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(9)} -pin  "reg(regs.regs(1)#1.sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(10)} -pin  "reg(regs.regs(1)#1.sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(11)} -pin  "reg(regs.regs(1)#1.sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(12)} -pin  "reg(regs.regs(1)#1.sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(13)} -pin  "reg(regs.regs(1)#1.sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(14)} -pin  "reg(regs.regs(1)#1.sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(15)} -pin  "reg(regs.regs(1)#1.sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(16)} -pin  "reg(regs.regs(1)#1.sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(17)} -pin  "reg(regs.regs(1)#1.sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(18)} -pin  "reg(regs.regs(1)#1.sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(19)} -pin  "reg(regs.regs(1)#1.sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(20)} -pin  "reg(regs.regs(1)#1.sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(21)} -pin  "reg(regs.regs(1)#1.sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(22)} -pin  "reg(regs.regs(1)#1.sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(23)} -pin  "reg(regs.regs(1)#1.sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(24)} -pin  "reg(regs.regs(1)#1.sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(25)} -pin  "reg(regs.regs(1)#1.sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(26)} -pin  "reg(regs.regs(1)#1.sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(27)} -pin  "reg(regs.regs(1)#1.sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(28)} -pin  "reg(regs.regs(1)#1.sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(29)} -pin  "reg(regs.regs(1)#1.sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load inst "reg(regs.regs(1).sg2.sva)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 14255 -attr oid 128 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(1).sg2.sva)}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "reg(regs.regs(1).sg2.sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "reg(regs.regs(1).sg2.sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "reg(regs.regs(1).sg2.sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "reg(regs.regs(1).sg2.sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "reg(regs.regs(1).sg2.sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "reg(regs.regs(1).sg2.sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "reg(regs.regs(1).sg2.sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "reg(regs.regs(1).sg2.sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "reg(regs.regs(1).sg2.sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "reg(regs.regs(1).sg2.sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "reg(regs.regs(1).sg2.sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "reg(regs.regs(1).sg2.sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "reg(regs.regs(1).sg2.sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "reg(regs.regs(1).sg2.sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "reg(regs.regs(1).sg2.sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "reg(regs.regs(1).sg2.sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "reg(regs.regs(1).sg2.sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "reg(regs.regs(1).sg2.sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "reg(regs.regs(1).sg2.sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "reg(regs.regs(1).sg2.sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "reg(regs.regs(1).sg2.sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "reg(regs.regs(1).sg2.sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "reg(regs.regs(1).sg2.sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "reg(regs.regs(1).sg2.sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "reg(regs.regs(1).sg2.sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "reg(regs.regs(1).sg2.sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "reg(regs.regs(1).sg2.sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "reg(regs.regs(1).sg2.sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "reg(regs.regs(1).sg2.sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "reg(regs.regs(1).sg2.sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(regs.regs(1).sg2.sva)" {clk} -attr xrf 14256 -attr oid 129 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(1).sg2.sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(1).sg2.sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(1).sg2.sva(0)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(1)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(2)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(3)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(4)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(5)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(6)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(7)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(8)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(9)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(10)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(11)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(12)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(13)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(14)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(15)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(16)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(17)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(18)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(19)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(20)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(21)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(22)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(23)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(24)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(25)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(26)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(27)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(28)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(29)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load inst "ACC1:acc#37" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 14257 -attr oid 130 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "ACC1:acc#37" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "ACC1:acc#37" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "ACC1:acc#37" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "ACC1:acc#37" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "ACC1:acc#37" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "ACC1:acc#37" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "ACC1:acc#37" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "ACC1:acc#37" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "ACC1:acc#37" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:acc#37" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "ACC1:acc#37" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "ACC1:acc#37" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "ACC1:acc#37" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "ACC1:acc#37" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "ACC1:acc#37" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "ACC1:acc#37" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "ACC1:acc#37" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "ACC1:acc#37" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "ACC1:acc#37" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1:acc#37" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {ACC1:acc#37.itm(0)} -pin  "ACC1:acc#37" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(1)} -pin  "ACC1:acc#37" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(2)} -pin  "ACC1:acc#37" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(3)} -pin  "ACC1:acc#37" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(4)} -pin  "ACC1:acc#37" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(5)} -pin  "ACC1:acc#37" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(6)} -pin  "ACC1:acc#37" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(7)} -pin  "ACC1:acc#37" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(8)} -pin  "ACC1:acc#37" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(9)} -pin  "ACC1:acc#37" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(10)} -pin  "ACC1:acc#37" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load inst "ACC1:acc#36" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 14258 -attr oid 131 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#36} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#36" {A(0)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(0)} -pin  "ACC1:acc#36" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(1)} -pin  "ACC1:acc#36" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(2)} -pin  "ACC1:acc#36" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(3)} -pin  "ACC1:acc#36" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(4)} -pin  "ACC1:acc#36" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(5)} -pin  "ACC1:acc#36" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(6)} -pin  "ACC1:acc#36" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(7)} -pin  "ACC1:acc#36" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(8)} -pin  "ACC1:acc#36" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/conc.itm}
+load net {ACC1:slc(regs.regs(2).sg2).itm(9)} -pin  "ACC1:acc#36" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/conc.itm}
+load net {PWR} -pin  "ACC1:acc#36" {B(0)} -attr @path {/sobel/sobel:core/conc#50.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(0)} -pin  "ACC1:acc#36" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#50.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(1)} -pin  "ACC1:acc#36" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#50.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(2)} -pin  "ACC1:acc#36" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#50.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(3)} -pin  "ACC1:acc#36" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#50.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(4)} -pin  "ACC1:acc#36" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#50.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(5)} -pin  "ACC1:acc#36" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#50.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(6)} -pin  "ACC1:acc#36" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#50.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(7)} -pin  "ACC1:acc#36" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#50.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(8)} -pin  "ACC1:acc#36" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#50.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#1.itm(9)} -pin  "ACC1:acc#36" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#50.itm}
+load net {ACC1:acc#36.itm(0)} -pin  "ACC1:acc#36" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#36.itm}
+load net {ACC1:acc#36.itm(1)} -pin  "ACC1:acc#36" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#36.itm}
+load net {ACC1:acc#36.itm(2)} -pin  "ACC1:acc#36" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#36.itm}
+load net {ACC1:acc#36.itm(3)} -pin  "ACC1:acc#36" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#36.itm}
+load net {ACC1:acc#36.itm(4)} -pin  "ACC1:acc#36" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#36.itm}
+load net {ACC1:acc#36.itm(5)} -pin  "ACC1:acc#36" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#36.itm}
+load net {ACC1:acc#36.itm(6)} -pin  "ACC1:acc#36" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#36.itm}
+load net {ACC1:acc#36.itm(7)} -pin  "ACC1:acc#36" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#36.itm}
+load net {ACC1:acc#36.itm(8)} -pin  "ACC1:acc#36" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#36.itm}
+load net {ACC1:acc#36.itm(9)} -pin  "ACC1:acc#36" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#36.itm}
+load net {ACC1:acc#36.itm(10)} -pin  "ACC1:acc#36" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#36.itm}
+load net {ACC1:acc#36.itm(11)} -pin  "ACC1:acc#36" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#36.itm}
+load inst "ACC1:acc#41" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 14259 -attr oid 132 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#37.itm(0)} -pin  "ACC1:acc#41" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(1)} -pin  "ACC1:acc#41" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(2)} -pin  "ACC1:acc#41" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(3)} -pin  "ACC1:acc#41" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(4)} -pin  "ACC1:acc#41" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(5)} -pin  "ACC1:acc#41" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(6)} -pin  "ACC1:acc#41" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(7)} -pin  "ACC1:acc#41" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(8)} -pin  "ACC1:acc#41" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(9)} -pin  "ACC1:acc#41" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#37.itm(10)} -pin  "ACC1:acc#41" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#37.itm}
+load net {ACC1:acc#36.itm(1)} -pin  "ACC1:acc#41" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#36.itm(2)} -pin  "ACC1:acc#41" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#36.itm(3)} -pin  "ACC1:acc#41" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#36.itm(4)} -pin  "ACC1:acc#41" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#36.itm(5)} -pin  "ACC1:acc#41" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#36.itm(6)} -pin  "ACC1:acc#41" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#36.itm(7)} -pin  "ACC1:acc#41" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#36.itm(8)} -pin  "ACC1:acc#41" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#36.itm(9)} -pin  "ACC1:acc#41" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#36.itm(10)} -pin  "ACC1:acc#41" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#36.itm(11)} -pin  "ACC1:acc#41" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#3.itm}
+load net {ACC1:acc#41.itm(0)} -pin  "ACC1:acc#41" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(1)} -pin  "ACC1:acc#41" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(2)} -pin  "ACC1:acc#41" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(3)} -pin  "ACC1:acc#41" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(4)} -pin  "ACC1:acc#41" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(5)} -pin  "ACC1:acc#41" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(6)} -pin  "ACC1:acc#41" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(7)} -pin  "ACC1:acc#41" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(8)} -pin  "ACC1:acc#41" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(9)} -pin  "ACC1:acc#41" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(10)} -pin  "ACC1:acc#41" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(11)} -pin  "ACC1:acc#41" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load inst "ACC1:not" "not(10)" "INTERFACE" -attr xrf 14260 -attr oid 133 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {ACC1:slc(regs.regs(2)#1).itm(0)} -pin  "ACC1:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(1)} -pin  "ACC1:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(2)} -pin  "ACC1:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(3)} -pin  "ACC1:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(4)} -pin  "ACC1:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(5)} -pin  "ACC1:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(6)} -pin  "ACC1:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(7)} -pin  "ACC1:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(8)} -pin  "ACC1:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:slc(regs.regs(2)#1).itm(9)} -pin  "ACC1:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1).itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load inst "ACC1:acc#35" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 14261 -attr oid 134 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#35" {A(0)} -attr @path {/sobel/sobel:core/conc#51.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(0)} -pin  "ACC1:acc#35" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#51.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(1)} -pin  "ACC1:acc#35" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#51.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(2)} -pin  "ACC1:acc#35" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#51.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(3)} -pin  "ACC1:acc#35" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#51.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(4)} -pin  "ACC1:acc#35" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#51.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(5)} -pin  "ACC1:acc#35" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#51.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(6)} -pin  "ACC1:acc#35" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#51.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(7)} -pin  "ACC1:acc#35" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#51.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(8)} -pin  "ACC1:acc#35" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#51.itm}
+load net {ACC1:slc(regs.regs(2).sg2)#2.itm(9)} -pin  "ACC1:acc#35" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#51.itm}
+load net {PWR} -pin  "ACC1:acc#35" {B(0)} -attr @path {/sobel/sobel:core/conc#52.itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:acc#35" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#52.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:acc#35" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#52.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:acc#35" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#52.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:acc#35" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#52.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:acc#35" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#52.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:acc#35" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#52.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:acc#35" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#52.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:acc#35" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#52.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:acc#35" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#52.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:acc#35" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#52.itm}
+load net {ACC1:acc#35.itm(0)} -pin  "ACC1:acc#35" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35.itm}
+load net {ACC1:acc#35.itm(1)} -pin  "ACC1:acc#35" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35.itm}
+load net {ACC1:acc#35.itm(2)} -pin  "ACC1:acc#35" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35.itm}
+load net {ACC1:acc#35.itm(3)} -pin  "ACC1:acc#35" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35.itm}
+load net {ACC1:acc#35.itm(4)} -pin  "ACC1:acc#35" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35.itm}
+load net {ACC1:acc#35.itm(5)} -pin  "ACC1:acc#35" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35.itm}
+load net {ACC1:acc#35.itm(6)} -pin  "ACC1:acc#35" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35.itm}
+load net {ACC1:acc#35.itm(7)} -pin  "ACC1:acc#35" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35.itm}
+load net {ACC1:acc#35.itm(8)} -pin  "ACC1:acc#35" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35.itm}
+load net {ACC1:acc#35.itm(9)} -pin  "ACC1:acc#35" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35.itm}
+load net {ACC1:acc#35.itm(10)} -pin  "ACC1:acc#35" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35.itm}
+load net {ACC1:acc#35.itm(11)} -pin  "ACC1:acc#35" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#35.itm}
+load inst "ACC1:not#9" "not(10)" "INTERFACE" -attr xrf 14262 -attr oid 135 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#9} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(0)} -pin  "ACC1:not#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(1)} -pin  "ACC1:not#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(2)} -pin  "ACC1:not#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(3)} -pin  "ACC1:not#9" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(4)} -pin  "ACC1:not#9" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(5)} -pin  "ACC1:not#9" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(6)} -pin  "ACC1:not#9" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(7)} -pin  "ACC1:not#9" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(8)} -pin  "ACC1:not#9" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:slc(regs.regs(2)#1)#1.itm(9)} -pin  "ACC1:not#9" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#1.itm}
+load net {ACC1:not#9.itm(0)} -pin  "ACC1:not#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#9.itm}
+load net {ACC1:not#9.itm(1)} -pin  "ACC1:not#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#9.itm}
+load net {ACC1:not#9.itm(2)} -pin  "ACC1:not#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#9.itm}
+load net {ACC1:not#9.itm(3)} -pin  "ACC1:not#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#9.itm}
+load net {ACC1:not#9.itm(4)} -pin  "ACC1:not#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#9.itm}
+load net {ACC1:not#9.itm(5)} -pin  "ACC1:not#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#9.itm}
+load net {ACC1:not#9.itm(6)} -pin  "ACC1:not#9" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#9.itm}
+load net {ACC1:not#9.itm(7)} -pin  "ACC1:not#9" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#9.itm}
+load net {ACC1:not#9.itm(8)} -pin  "ACC1:not#9" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#9.itm}
+load net {ACC1:not#9.itm(9)} -pin  "ACC1:not#9" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#9.itm}
+load inst "ACC1:not#10" "not(10)" "INTERFACE" -attr xrf 14263 -attr oid 136 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#10} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(0)} -pin  "ACC1:not#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(1)} -pin  "ACC1:not#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(2)} -pin  "ACC1:not#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(3)} -pin  "ACC1:not#10" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(4)} -pin  "ACC1:not#10" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(5)} -pin  "ACC1:not#10" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(6)} -pin  "ACC1:not#10" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(7)} -pin  "ACC1:not#10" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(8)} -pin  "ACC1:not#10" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:slc(regs.regs(2)#1)#2.itm(9)} -pin  "ACC1:not#10" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc(regs.regs(2)#1)#2.itm}
+load net {ACC1:not#10.itm(0)} -pin  "ACC1:not#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#10.itm}
+load net {ACC1:not#10.itm(1)} -pin  "ACC1:not#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#10.itm}
+load net {ACC1:not#10.itm(2)} -pin  "ACC1:not#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#10.itm}
+load net {ACC1:not#10.itm(3)} -pin  "ACC1:not#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#10.itm}
+load net {ACC1:not#10.itm(4)} -pin  "ACC1:not#10" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#10.itm}
+load net {ACC1:not#10.itm(5)} -pin  "ACC1:not#10" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#10.itm}
+load net {ACC1:not#10.itm(6)} -pin  "ACC1:not#10" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#10.itm}
+load net {ACC1:not#10.itm(7)} -pin  "ACC1:not#10" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#10.itm}
+load net {ACC1:not#10.itm(8)} -pin  "ACC1:not#10" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#10.itm}
+load net {ACC1:not#10.itm(9)} -pin  "ACC1:not#10" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#10.itm}
+load inst "ACC1:acc#34" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 14264 -attr oid 137 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#34" {A(0)} -attr @path {/sobel/sobel:core/conc#53.itm}
+load net {ACC1:not#9.itm(0)} -pin  "ACC1:acc#34" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#53.itm}
+load net {ACC1:not#9.itm(1)} -pin  "ACC1:acc#34" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#53.itm}
+load net {ACC1:not#9.itm(2)} -pin  "ACC1:acc#34" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#53.itm}
+load net {ACC1:not#9.itm(3)} -pin  "ACC1:acc#34" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#53.itm}
+load net {ACC1:not#9.itm(4)} -pin  "ACC1:acc#34" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#53.itm}
+load net {ACC1:not#9.itm(5)} -pin  "ACC1:acc#34" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#53.itm}
+load net {ACC1:not#9.itm(6)} -pin  "ACC1:acc#34" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#53.itm}
+load net {ACC1:not#9.itm(7)} -pin  "ACC1:acc#34" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#53.itm}
+load net {ACC1:not#9.itm(8)} -pin  "ACC1:acc#34" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#53.itm}
+load net {ACC1:not#9.itm(9)} -pin  "ACC1:acc#34" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#53.itm}
+load net {PWR} -pin  "ACC1:acc#34" {B(0)} -attr @path {/sobel/sobel:core/conc#54.itm}
+load net {ACC1:not#10.itm(0)} -pin  "ACC1:acc#34" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#54.itm}
+load net {ACC1:not#10.itm(1)} -pin  "ACC1:acc#34" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#54.itm}
+load net {ACC1:not#10.itm(2)} -pin  "ACC1:acc#34" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#54.itm}
+load net {ACC1:not#10.itm(3)} -pin  "ACC1:acc#34" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#54.itm}
+load net {ACC1:not#10.itm(4)} -pin  "ACC1:acc#34" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#54.itm}
+load net {ACC1:not#10.itm(5)} -pin  "ACC1:acc#34" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#54.itm}
+load net {ACC1:not#10.itm(6)} -pin  "ACC1:acc#34" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#54.itm}
+load net {ACC1:not#10.itm(7)} -pin  "ACC1:acc#34" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#54.itm}
+load net {ACC1:not#10.itm(8)} -pin  "ACC1:acc#34" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#54.itm}
+load net {ACC1:not#10.itm(9)} -pin  "ACC1:acc#34" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#54.itm}
+load net {ACC1:acc#34.itm(0)} -pin  "ACC1:acc#34" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34.itm}
+load net {ACC1:acc#34.itm(1)} -pin  "ACC1:acc#34" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34.itm}
+load net {ACC1:acc#34.itm(2)} -pin  "ACC1:acc#34" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34.itm}
+load net {ACC1:acc#34.itm(3)} -pin  "ACC1:acc#34" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34.itm}
+load net {ACC1:acc#34.itm(4)} -pin  "ACC1:acc#34" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34.itm}
+load net {ACC1:acc#34.itm(5)} -pin  "ACC1:acc#34" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34.itm}
+load net {ACC1:acc#34.itm(6)} -pin  "ACC1:acc#34" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34.itm}
+load net {ACC1:acc#34.itm(7)} -pin  "ACC1:acc#34" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34.itm}
+load net {ACC1:acc#34.itm(8)} -pin  "ACC1:acc#34" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34.itm}
+load net {ACC1:acc#34.itm(9)} -pin  "ACC1:acc#34" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34.itm}
+load net {ACC1:acc#34.itm(10)} -pin  "ACC1:acc#34" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34.itm}
+load net {ACC1:acc#34.itm(11)} -pin  "ACC1:acc#34" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#34.itm}
+load inst "ACC1:acc#40" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 14265 -attr oid 138 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#35.itm(1)} -pin  "ACC1:acc#40" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#35.itm(2)} -pin  "ACC1:acc#40" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#35.itm(3)} -pin  "ACC1:acc#40" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#35.itm(4)} -pin  "ACC1:acc#40" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#35.itm(5)} -pin  "ACC1:acc#40" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#35.itm(6)} -pin  "ACC1:acc#40" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#35.itm(7)} -pin  "ACC1:acc#40" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#35.itm(8)} -pin  "ACC1:acc#40" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#35.itm(9)} -pin  "ACC1:acc#40" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#35.itm(10)} -pin  "ACC1:acc#40" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#35.itm(11)} -pin  "ACC1:acc#40" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#2.itm}
+load net {ACC1:acc#34.itm(1)} -pin  "ACC1:acc#40" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc#34.itm(2)} -pin  "ACC1:acc#40" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc#34.itm(3)} -pin  "ACC1:acc#40" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc#34.itm(4)} -pin  "ACC1:acc#40" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc#34.itm(5)} -pin  "ACC1:acc#40" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc#34.itm(6)} -pin  "ACC1:acc#40" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc#34.itm(7)} -pin  "ACC1:acc#40" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc#34.itm(8)} -pin  "ACC1:acc#40" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc#34.itm(9)} -pin  "ACC1:acc#40" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc#34.itm(10)} -pin  "ACC1:acc#40" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc#34.itm(11)} -pin  "ACC1:acc#40" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#1.itm}
+load net {ACC1:acc#40.itm(0)} -pin  "ACC1:acc#40" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(1)} -pin  "ACC1:acc#40" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(2)} -pin  "ACC1:acc#40" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(3)} -pin  "ACC1:acc#40" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(4)} -pin  "ACC1:acc#40" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(5)} -pin  "ACC1:acc#40" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(6)} -pin  "ACC1:acc#40" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(7)} -pin  "ACC1:acc#40" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(8)} -pin  "ACC1:acc#40" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(9)} -pin  "ACC1:acc#40" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(10)} -pin  "ACC1:acc#40" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(11)} -pin  "ACC1:acc#40" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load inst "ACC1:acc#43" "add(12,1,12,1,13)" "INTERFACE" -attr xrf 14266 -attr oid 139 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1:acc#41.itm(0)} -pin  "ACC1:acc#43" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(1)} -pin  "ACC1:acc#43" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(2)} -pin  "ACC1:acc#43" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(3)} -pin  "ACC1:acc#43" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(4)} -pin  "ACC1:acc#43" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(5)} -pin  "ACC1:acc#43" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(6)} -pin  "ACC1:acc#43" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(7)} -pin  "ACC1:acc#43" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(8)} -pin  "ACC1:acc#43" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(9)} -pin  "ACC1:acc#43" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(10)} -pin  "ACC1:acc#43" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#41.itm(11)} -pin  "ACC1:acc#43" {A(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#41.itm}
+load net {ACC1:acc#40.itm(0)} -pin  "ACC1:acc#43" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(1)} -pin  "ACC1:acc#43" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(2)} -pin  "ACC1:acc#43" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(3)} -pin  "ACC1:acc#43" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(4)} -pin  "ACC1:acc#43" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(5)} -pin  "ACC1:acc#43" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(6)} -pin  "ACC1:acc#43" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(7)} -pin  "ACC1:acc#43" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(8)} -pin  "ACC1:acc#43" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(9)} -pin  "ACC1:acc#43" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(10)} -pin  "ACC1:acc#43" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#40.itm(11)} -pin  "ACC1:acc#43" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#40.itm}
+load net {ACC1:acc#43.itm(0)} -pin  "ACC1:acc#43" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(1)} -pin  "ACC1:acc#43" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(2)} -pin  "ACC1:acc#43" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(3)} -pin  "ACC1:acc#43" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(4)} -pin  "ACC1:acc#43" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(5)} -pin  "ACC1:acc#43" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(6)} -pin  "ACC1:acc#43" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(7)} -pin  "ACC1:acc#43" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(8)} -pin  "ACC1:acc#43" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(9)} -pin  "ACC1:acc#43" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(10)} -pin  "ACC1:acc#43" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(11)} -pin  "ACC1:acc#43" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(12)} -pin  "ACC1:acc#43" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load inst "ACC1:acc#39" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 14267 -attr oid 140 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "ACC1:acc#39" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "ACC1:acc#39" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "ACC1:acc#39" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "ACC1:acc#39" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "ACC1:acc#39" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "ACC1:acc#39" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "ACC1:acc#39" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "ACC1:acc#39" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "ACC1:acc#39" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:acc#39" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "ACC1:acc#39" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "ACC1:acc#39" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "ACC1:acc#39" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "ACC1:acc#39" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "ACC1:acc#39" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "ACC1:acc#39" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "ACC1:acc#39" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "ACC1:acc#39" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "ACC1:acc#39" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:acc#39" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:acc#39.itm(0)} -pin  "ACC1:acc#39" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(1)} -pin  "ACC1:acc#39" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(2)} -pin  "ACC1:acc#39" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(3)} -pin  "ACC1:acc#39" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(4)} -pin  "ACC1:acc#39" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(5)} -pin  "ACC1:acc#39" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(6)} -pin  "ACC1:acc#39" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(7)} -pin  "ACC1:acc#39" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(8)} -pin  "ACC1:acc#39" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(9)} -pin  "ACC1:acc#39" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(10)} -pin  "ACC1:acc#39" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load inst "ACC1:acc#38" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 14268 -attr oid 141 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "ACC1:acc#38" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "ACC1:acc#38" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "ACC1:acc#38" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "ACC1:acc#38" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "ACC1:acc#38" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "ACC1:acc#38" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "ACC1:acc#38" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "ACC1:acc#38" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "ACC1:acc#38" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1:acc#38" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "ACC1:acc#38" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "ACC1:acc#38" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "ACC1:acc#38" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "ACC1:acc#38" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "ACC1:acc#38" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "ACC1:acc#38" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "ACC1:acc#38" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "ACC1:acc#38" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "ACC1:acc#38" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:acc#38" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:acc#38.itm(0)} -pin  "ACC1:acc#38" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(1)} -pin  "ACC1:acc#38" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(2)} -pin  "ACC1:acc#38" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(3)} -pin  "ACC1:acc#38" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(4)} -pin  "ACC1:acc#38" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(5)} -pin  "ACC1:acc#38" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(6)} -pin  "ACC1:acc#38" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(7)} -pin  "ACC1:acc#38" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(8)} -pin  "ACC1:acc#38" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(9)} -pin  "ACC1:acc#38" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(10)} -pin  "ACC1:acc#38" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load inst "ACC1:acc#42" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 14269 -attr oid 142 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#39.itm(0)} -pin  "ACC1:acc#42" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(1)} -pin  "ACC1:acc#42" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(2)} -pin  "ACC1:acc#42" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(3)} -pin  "ACC1:acc#42" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(4)} -pin  "ACC1:acc#42" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(5)} -pin  "ACC1:acc#42" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(6)} -pin  "ACC1:acc#42" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(7)} -pin  "ACC1:acc#42" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(8)} -pin  "ACC1:acc#42" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(9)} -pin  "ACC1:acc#42" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#39.itm(10)} -pin  "ACC1:acc#42" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#39.itm}
+load net {ACC1:acc#38.itm(0)} -pin  "ACC1:acc#42" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(1)} -pin  "ACC1:acc#42" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(2)} -pin  "ACC1:acc#42" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(3)} -pin  "ACC1:acc#42" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(4)} -pin  "ACC1:acc#42" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(5)} -pin  "ACC1:acc#42" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(6)} -pin  "ACC1:acc#42" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(7)} -pin  "ACC1:acc#42" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(8)} -pin  "ACC1:acc#42" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(9)} -pin  "ACC1:acc#42" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#38.itm(10)} -pin  "ACC1:acc#42" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#38.itm}
+load net {ACC1:acc#42.itm(0)} -pin  "ACC1:acc#42" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(1)} -pin  "ACC1:acc#42" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(2)} -pin  "ACC1:acc#42" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(3)} -pin  "ACC1:acc#42" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(4)} -pin  "ACC1:acc#42" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(5)} -pin  "ACC1:acc#42" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(6)} -pin  "ACC1:acc#42" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(7)} -pin  "ACC1:acc#42" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(8)} -pin  "ACC1:acc#42" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(9)} -pin  "ACC1:acc#42" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(10)} -pin  "ACC1:acc#42" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(11)} -pin  "ACC1:acc#42" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load inst "ACC1:acc" "add(13,1,12,1,14)" "INTERFACE" -attr xrf 14270 -attr oid 143 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc} -attr area 14.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,1,12,1,14)"
+load net {ACC1:acc#43.itm(0)} -pin  "ACC1:acc" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(1)} -pin  "ACC1:acc" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(2)} -pin  "ACC1:acc" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(3)} -pin  "ACC1:acc" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(4)} -pin  "ACC1:acc" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(5)} -pin  "ACC1:acc" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(6)} -pin  "ACC1:acc" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(7)} -pin  "ACC1:acc" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(8)} -pin  "ACC1:acc" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(9)} -pin  "ACC1:acc" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(10)} -pin  "ACC1:acc" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(11)} -pin  "ACC1:acc" {A(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#43.itm(12)} -pin  "ACC1:acc" {A(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#43.itm}
+load net {ACC1:acc#42.itm(0)} -pin  "ACC1:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(1)} -pin  "ACC1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(2)} -pin  "ACC1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(3)} -pin  "ACC1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(4)} -pin  "ACC1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(5)} -pin  "ACC1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(6)} -pin  "ACC1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(7)} -pin  "ACC1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(8)} -pin  "ACC1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(9)} -pin  "ACC1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(10)} -pin  "ACC1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc#42.itm(11)} -pin  "ACC1:acc" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#42.itm}
+load net {ACC1:acc.itm(0)} -pin  "ACC1:acc" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(1)} -pin  "ACC1:acc" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(2)} -pin  "ACC1:acc" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(3)} -pin  "ACC1:acc" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(4)} -pin  "ACC1:acc" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(5)} -pin  "ACC1:acc" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(6)} -pin  "ACC1:acc" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(7)} -pin  "ACC1:acc" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(8)} -pin  "ACC1:acc" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(9)} -pin  "ACC1:acc" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(10)} -pin  "ACC1:acc" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(11)} -pin  "ACC1:acc" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(12)} -pin  "ACC1:acc" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(13)} -pin  "ACC1:acc" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load inst "FRAME:mul#3" "mul(4,0,5,0,9)" "INTERFACE" -attr xrf 14271 -attr oid 144 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(4,0,5,0,9)"
+load net {ACC1:acc.itm(10)} -pin  "FRAME:mul#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#1.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:mul#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#1.itm}
+load net {ACC1:acc.itm(12)} -pin  "FRAME:mul#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#1.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:mul#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#1.itm}
+load net {PWR} -pin  "FRAME:mul#3" {B(0)} -attr @path {/sobel/sobel:core/C19_5}
+load net {PWR} -pin  "FRAME:mul#3" {B(1)} -attr @path {/sobel/sobel:core/C19_5}
+load net {GND} -pin  "FRAME:mul#3" {B(2)} -attr @path {/sobel/sobel:core/C19_5}
+load net {GND} -pin  "FRAME:mul#3" {B(3)} -attr @path {/sobel/sobel:core/C19_5}
+load net {PWR} -pin  "FRAME:mul#3" {B(4)} -attr @path {/sobel/sobel:core/C19_5}
+load net {FRAME:mul#3.itm(0)} -pin  "FRAME:mul#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "FRAME:mul#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "FRAME:mul#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "FRAME:mul#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "FRAME:mul#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "FRAME:mul#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "FRAME:mul#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "FRAME:mul#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "FRAME:mul#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load inst "FRAME:acc#17" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 14272 -attr oid 145 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc.itm(5)} -pin  "FRAME:acc#17" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#17.itm}
+load net {acc.imod.sva(4)} -pin  "FRAME:acc#17" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#8.itm}
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load inst "FRAME:acc#19" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 14273 -attr oid 146 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#19" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#19" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:acc#19" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#20.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:acc#19" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#20.itm}
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#19" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#19" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#19" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load inst "FRAME:acc#16" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 14274 -attr oid 147 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#16} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,6)"
+load net {acc.imod.sva(4)} -pin  "FRAME:acc#16" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/conc#55.itm}
+load net {GND} -pin  "FRAME:acc#16" {A(1)} -attr @path {/sobel/sobel:core/conc#55.itm}
+load net {acc.imod.sva(4)} -pin  "FRAME:acc#16" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#55.itm}
+load net {GND} -pin  "FRAME:acc#16" {A(3)} -attr @path {/sobel/sobel:core/conc#55.itm}
+load net {acc.imod.sva(4)} -pin  "FRAME:acc#16" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/conc#55.itm}
+load net {acc.imod.sva(0)} -pin  "FRAME:acc#16" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#4.itm}
+load net {acc.imod.sva(1)} -pin  "FRAME:acc#16" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#4.itm}
+load net {acc.imod.sva(2)} -pin  "FRAME:acc#16" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#4.itm}
+load net {acc.imod.sva(3)} -pin  "FRAME:acc#16" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#4.itm}
+load net {FRAME:acc#16.itm(0)} -pin  "FRAME:acc#16" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "FRAME:acc#16" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "FRAME:acc#16" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "FRAME:acc#16" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:acc#16" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load inst "FRAME:acc#32" "add(2,1,1,1,3)" "INTERFACE" -attr xrf 14275 -attr oid 148 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,1,1,1,3)"
+load net {acc.imod.sva(5)} -pin  "FRAME:acc#32" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#7.itm}
+load net {acc.imod.sva(6)} -pin  "FRAME:acc#32" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#7.itm}
+load net {acc.imod.sva(6)} -pin  "FRAME:acc#32" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#5.itm}
+load net {FRAME:acc#32.itm(0)} -pin  "FRAME:acc#32" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(1)} -pin  "FRAME:acc#32" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(2)} -pin  "FRAME:acc#32" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load inst "acc#3" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 14276 -attr oid 149 -attr vt dc -attr @path {/sobel/sobel:core/acc#3} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,6)"
+load net {FRAME:acc#16.itm(0)} -pin  "acc#3" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "acc#3" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "acc#3" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "acc#3" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "acc#3" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {acc.imod.sva(5)} -pin  "acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#30.itm}
+load net {acc.imod.sva(6)} -pin  "acc#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#30.itm}
+load net {FRAME:acc#32.itm(0)} -pin  "acc#3" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#30.itm}
+load net {FRAME:acc#32.itm(1)} -pin  "acc#3" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#30.itm}
+load net {FRAME:acc#32.itm(2)} -pin  "acc#3" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#30.itm}
+load net {acc#3.itm(0)} -pin  "acc#3" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/acc#3.itm}
+load net {acc#3.itm(1)} -pin  "acc#3" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/acc#3.itm}
+load net {acc#3.itm(2)} -pin  "acc#3" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/acc#3.itm}
+load net {acc#3.itm(3)} -pin  "acc#3" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/acc#3.itm}
+load net {acc#3.itm(4)} -pin  "acc#3" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/acc#3.itm}
+load inst "FRAME:acc#18" "add(2,1,1,1,3)" "INTERFACE" -attr xrf 14277 -attr oid 150 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,1,1,1,3)"
+load net {acc.imod.sva(5)} -pin  "FRAME:acc#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#6.itm}
+load net {acc.imod.sva(6)} -pin  "FRAME:acc#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#6.itm}
+load net {acc#3.itm(4)} -pin  "FRAME:acc#18" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:slc#5.itm}
+load net {FRAME:acc#18.itm(0)} -pin  "FRAME:acc#18" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(1)} -pin  "FRAME:acc#18" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(2)} -pin  "FRAME:acc#18" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load inst "FRAME:acc#20" "add(3,0,3,1,4)" "INTERFACE" -attr xrf 14278 -attr oid 151 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,4)"
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#18.itm(0)} -pin  "FRAME:acc#20" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(1)} -pin  "FRAME:acc#20" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(2)} -pin  "FRAME:acc#20" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#20.itm(0)} -pin  "FRAME:acc#20" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(1)} -pin  "FRAME:acc#20" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(2)} -pin  "FRAME:acc#20" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(3)} -pin  "FRAME:acc#20" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load inst "FRAME:acc#21" "add(4,1,4,0,6)" "INTERFACE" -attr xrf 14279 -attr oid 152 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {FRAME:acc#20.itm(0)} -pin  "FRAME:acc#21" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(1)} -pin  "FRAME:acc#21" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(2)} -pin  "FRAME:acc#21" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(3)} -pin  "FRAME:acc#21" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {ACC1:acc.itm(6)} -pin  "FRAME:acc#21" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#4.itm}
+load net {ACC1:acc.itm(7)} -pin  "FRAME:acc#21" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#4.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:acc#21" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#4.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:acc#21" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#4.itm}
+load net {FRAME:acc#21.itm(0)} -pin  "FRAME:acc#21" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(1)} -pin  "FRAME:acc#21" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(2)} -pin  "FRAME:acc#21" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(3)} -pin  "FRAME:acc#21" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(4)} -pin  "FRAME:acc#21" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(5)} -pin  "FRAME:acc#21" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load inst "FRAME:acc#22" "add(9,0,6,1,10)" "INTERFACE" -attr xrf 14280 -attr oid 153 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,6,1,10)"
+load net {FRAME:mul#3.itm(0)} -pin  "FRAME:acc#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "FRAME:acc#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "FRAME:acc#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "FRAME:acc#22" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "FRAME:acc#22" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "FRAME:acc#22" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "FRAME:acc#22" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "FRAME:acc#22" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "FRAME:acc#22" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:acc#21.itm(0)} -pin  "FRAME:acc#22" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(1)} -pin  "FRAME:acc#22" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(2)} -pin  "FRAME:acc#22" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(3)} -pin  "FRAME:acc#22" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(4)} -pin  "FRAME:acc#22" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#21.itm(5)} -pin  "FRAME:acc#22" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#21.itm}
+load net {FRAME:acc#22.cse(0)} -pin  "FRAME:acc#22" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(1)} -pin  "FRAME:acc#22" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(2)} -pin  "FRAME:acc#22" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(3)} -pin  "FRAME:acc#22" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(4)} -pin  "FRAME:acc#22" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(5)} -pin  "FRAME:acc#22" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(6)} -pin  "FRAME:acc#22" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(7)} -pin  "FRAME:acc#22" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(8)} -pin  "FRAME:acc#22" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(9)} -pin  "FRAME:acc#22" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load inst "FRAME:acc#5" "add(10,0,10,1,11)" "INTERFACE" -attr xrf 14281 -attr oid 154 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11)"
+load net {FRAME:acc#33.itm(0)} -pin  "FRAME:acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(1)} -pin  "FRAME:acc#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(2)} -pin  "FRAME:acc#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(3)} -pin  "FRAME:acc#5" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(4)} -pin  "FRAME:acc#5" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(5)} -pin  "FRAME:acc#5" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(6)} -pin  "FRAME:acc#5" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(7)} -pin  "FRAME:acc#5" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#5" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#5" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#22.cse(0)} -pin  "FRAME:acc#5" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(1)} -pin  "FRAME:acc#5" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(2)} -pin  "FRAME:acc#5" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(3)} -pin  "FRAME:acc#5" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(4)} -pin  "FRAME:acc#5" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(5)} -pin  "FRAME:acc#5" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(6)} -pin  "FRAME:acc#5" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(7)} -pin  "FRAME:acc#5" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(8)} -pin  "FRAME:acc#5" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(9)} -pin  "FRAME:acc#5" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#5.psp.sva(0)} -pin  "FRAME:acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(1)} -pin  "FRAME:acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(2)} -pin  "FRAME:acc#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(3)} -pin  "FRAME:acc#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(4)} -pin  "FRAME:acc#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(5)} -pin  "FRAME:acc#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(6)} -pin  "FRAME:acc#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(7)} -pin  "FRAME:acc#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(8)} -pin  "FRAME:acc#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(9)} -pin  "FRAME:acc#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(10)} -pin  "FRAME:acc#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load inst "FRAME:not#19" "not(1)" "INTERFACE" -attr xrf 14282 -attr oid 155 -attr @path {/sobel/sobel:core/FRAME:not#19} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc.itm(13)} -pin  "FRAME:not#19" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#15.itm}
+load net {FRAME:not#19.itm} -pin  "FRAME:not#19" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#19.itm}
+load inst "FRAME:acc#31" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 14283 -attr oid 156 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#31} -attr area 2.320458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc.itm(9)} -pin  "FRAME:acc#31" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#6.itm}
+load net {FRAME:not#19.itm} -pin  "FRAME:acc#31" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#19.itm}
+load net {FRAME:acc#31.itm(0)} -pin  "FRAME:acc#31" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#31.itm}
+load net {FRAME:acc#31.itm(1)} -pin  "FRAME:acc#31" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#31.itm}
+load inst "FRAME:acc#11" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 14284 -attr oid 157 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc.itm(6)} -pin  "FRAME:acc#11" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#27.itm}
+load net {ACC1:acc.itm(7)} -pin  "FRAME:acc#11" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#27.itm}
+load net {ACC1:acc.itm(6)} -pin  "FRAME:acc#11" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#27.itm}
+load net {ACC1:acc.itm(7)} -pin  "FRAME:acc#11" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#27.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:acc#11" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:acc#31.itm(0)} -pin  "FRAME:acc#11" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:acc#31.itm(1)} -pin  "FRAME:acc#11" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#11" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#11" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#11" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#11" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "FRAME:acc#11" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load inst "FRAME:acc#13" "add(5,0,5,1,6)" "INTERFACE" -attr xrf 14285 -attr oid 158 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#13} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,6)"
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#13" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#13" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#13" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#13" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "FRAME:acc#13" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:acc#13" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#56.itm}
+load net {GND} -pin  "FRAME:acc#13" {B(1)} -attr @path {/sobel/sobel:core/conc#56.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:acc#13" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#56.itm}
+load net {GND} -pin  "FRAME:acc#13" {B(3)} -attr @path {/sobel/sobel:core/conc#56.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:acc#13" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#56.itm}
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#13" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#13" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#13" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#13" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(4)} -pin  "FRAME:acc#13" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(5)} -pin  "FRAME:acc#13" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load inst "FRAME:not#20" "not(2)" "INTERFACE" -attr xrf 14286 -attr oid 159 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#20} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc.itm(8)} -pin  "FRAME:not#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#3.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:not#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#3.itm}
+load net {FRAME:not#20.itm(0)} -pin  "FRAME:not#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load net {FRAME:not#20.itm(1)} -pin  "FRAME:not#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load inst "FRAME:not#21" "not(3)" "INTERFACE" -attr xrf 14287 -attr oid 160 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(10)} -pin  "FRAME:not#21" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#8.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:not#21" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#8.itm}
+load net {ACC1:acc.itm(12)} -pin  "FRAME:not#21" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#8.itm}
+load net {FRAME:not#21.itm(0)} -pin  "FRAME:not#21" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {FRAME:not#21.itm(1)} -pin  "FRAME:not#21" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {FRAME:not#21.itm(2)} -pin  "FRAME:not#21" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load inst "FRAME:acc#12" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 14288 -attr oid 161 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,6)"
+load net {FRAME:not#21.itm(0)} -pin  "FRAME:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#28.itm}
+load net {FRAME:not#21.itm(1)} -pin  "FRAME:acc#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#28.itm}
+load net {FRAME:not#21.itm(2)} -pin  "FRAME:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#28.itm}
+load net {FRAME:not#20.itm(0)} -pin  "FRAME:acc#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#28.itm}
+load net {FRAME:not#20.itm(1)} -pin  "FRAME:acc#12" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#28.itm}
+load net {ACC1:acc.itm(1)} -pin  "FRAME:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#9.itm}
+load net {ACC1:acc.itm(2)} -pin  "FRAME:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#9.itm}
+load net {ACC1:acc.itm(3)} -pin  "FRAME:acc#12" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#9.itm}
+load net {ACC1:acc.itm(4)} -pin  "FRAME:acc#12" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:slc.psp.sva)#9.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(4)} -pin  "FRAME:acc#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(5)} -pin  "FRAME:acc#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
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+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#14" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#14" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#14" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#14" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(4)} -pin  "FRAME:acc#14" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(5)} -pin  "FRAME:acc#14" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#14" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(4)} -pin  "FRAME:acc#14" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(5)} -pin  "FRAME:acc#14" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#14" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#14" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#14" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#14" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(4)} -pin  "FRAME:acc#14" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(5)} -pin  "FRAME:acc#14" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(6)} -pin  "FRAME:acc#14" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load inst "acc" "add(7,-1,7,-1,7)" "INTERFACE" -attr xrf 14290 -attr oid 163 -attr vt dc -attr @path {/sobel/sobel:core/acc} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,7)"
+load net {FRAME:acc#14.itm(0)} -pin  "acc" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "acc" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "acc" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "acc" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(4)} -pin  "acc" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(5)} -pin  "acc" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(6)} -pin  "acc" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {PWR} -pin  "acc" {B(0)} -attr @path {/sobel/sobel:core/Cn33_7}
+load net {PWR} -pin  "acc" {B(1)} -attr @path {/sobel/sobel:core/Cn33_7}
+load net {PWR} -pin  "acc" {B(2)} -attr @path {/sobel/sobel:core/Cn33_7}
+load net {PWR} -pin  "acc" {B(3)} -attr @path {/sobel/sobel:core/Cn33_7}
+load net {PWR} -pin  "acc" {B(4)} -attr @path {/sobel/sobel:core/Cn33_7}
+load net {GND} -pin  "acc" {B(5)} -attr @path {/sobel/sobel:core/Cn33_7}
+load net {PWR} -pin  "acc" {B(6)} -attr @path {/sobel/sobel:core/Cn33_7}
+load net {acc.imod.sva(0)} -pin  "acc" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(1)} -pin  "acc" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(2)} -pin  "acc" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(3)} -pin  "acc" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(4)} -pin  "acc" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(5)} -pin  "acc" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load net {acc.imod.sva(6)} -pin  "acc" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod.sva}
+load inst "FRAME:acc#33" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 14291 -attr oid 164 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33} -attr area 8.272060 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,6,0,8)"
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#33" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#57.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#33" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#57.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#33" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#57.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#33" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#57.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#33" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#57.itm}
+load net {GND} -pin  "FRAME:acc#33" {A(5)} -attr @path {/sobel/sobel:core/conc#57.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#33" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#57.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#33" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#58.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#33" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#58.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#33" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#58.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#33" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#58.itm}
+load net {GND} -pin  "FRAME:acc#33" {B(4)} -attr @path {/sobel/sobel:core/conc#58.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#33" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#58.itm}
+load net {FRAME:acc#33.itm(0)} -pin  "FRAME:acc#33" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(1)} -pin  "FRAME:acc#33" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(2)} -pin  "FRAME:acc#33" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(3)} -pin  "FRAME:acc#33" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(4)} -pin  "FRAME:acc#33" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(5)} -pin  "FRAME:acc#33" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(6)} -pin  "FRAME:acc#33" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(7)} -pin  "FRAME:acc#33" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load inst "FRAME:acc#3" "add(10,-1,10,-1,10)" "INTERFACE" -attr xrf 14292 -attr oid 165 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {FRAME:acc#33.itm(0)} -pin  "FRAME:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(1)} -pin  "FRAME:acc#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(2)} -pin  "FRAME:acc#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(3)} -pin  "FRAME:acc#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(4)} -pin  "FRAME:acc#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(5)} -pin  "FRAME:acc#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(6)} -pin  "FRAME:acc#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#33.itm(7)} -pin  "FRAME:acc#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#34}
+load net {FRAME:acc#22.cse(0)} -pin  "FRAME:acc#3" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(1)} -pin  "FRAME:acc#3" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(2)} -pin  "FRAME:acc#3" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(3)} -pin  "FRAME:acc#3" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(4)} -pin  "FRAME:acc#3" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(5)} -pin  "FRAME:acc#3" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(6)} -pin  "FRAME:acc#3" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(7)} -pin  "FRAME:acc#3" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(8)} -pin  "FRAME:acc#3" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#22.cse(9)} -pin  "FRAME:acc#3" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#22.cse}
+load net {FRAME:acc#3.itm(0)} -pin  "FRAME:acc#3" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(1)} -pin  "FRAME:acc#3" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(2)} -pin  "FRAME:acc#3" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(3)} -pin  "FRAME:acc#3" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(4)} -pin  "FRAME:acc#3" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(5)} -pin  "FRAME:acc#3" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(6)} -pin  "FRAME:acc#3" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(7)} -pin  "FRAME:acc#3" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(8)} -pin  "FRAME:acc#3" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(9)} -pin  "FRAME:acc#3" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load inst "FRAME:or" "or(2,10)" "INTERFACE" -attr xrf 14293 -attr oid 166 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or} -attr area 7.298324 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2)"
+load net {FRAME:acc#3.itm(0)} -pin  "FRAME:or" {A0(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(1)} -pin  "FRAME:or" {A0(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(2)} -pin  "FRAME:or" {A0(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(3)} -pin  "FRAME:or" {A0(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(4)} -pin  "FRAME:or" {A0(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(5)} -pin  "FRAME:or" {A0(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(6)} -pin  "FRAME:or" {A0(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(7)} -pin  "FRAME:or" {A0(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(8)} -pin  "FRAME:or" {A0(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#3.itm(9)} -pin  "FRAME:or" {A0(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#3.itm}
+load net {FRAME:acc#5.psp.sva(10)} -pin  "FRAME:or" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#59.itm}
+load net {GND} -pin  "FRAME:or" {A1(1)} -attr @path {/sobel/sobel:core/conc#59.itm}
+load net {GND} -pin  "FRAME:or" {A1(2)} -attr @path {/sobel/sobel:core/conc#59.itm}
+load net {GND} -pin  "FRAME:or" {A1(3)} -attr @path {/sobel/sobel:core/conc#59.itm}
+load net {GND} -pin  "FRAME:or" {A1(4)} -attr @path {/sobel/sobel:core/conc#59.itm}
+load net {GND} -pin  "FRAME:or" {A1(5)} -attr @path {/sobel/sobel:core/conc#59.itm}
+load net {GND} -pin  "FRAME:or" {A1(6)} -attr @path {/sobel/sobel:core/conc#59.itm}
+load net {GND} -pin  "FRAME:or" {A1(7)} -attr @path {/sobel/sobel:core/conc#59.itm}
+load net {GND} -pin  "FRAME:or" {A1(8)} -attr @path {/sobel/sobel:core/conc#59.itm}
+load net {GND} -pin  "FRAME:or" {A1(9)} -attr @path {/sobel/sobel:core/conc#59.itm}
+load net {FRAME:or.itm(0)} -pin  "FRAME:or" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(1)} -pin  "FRAME:or" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(2)} -pin  "FRAME:or" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(3)} -pin  "FRAME:or" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(4)} -pin  "FRAME:or" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(5)} -pin  "FRAME:or" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(6)} -pin  "FRAME:or" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(7)} -pin  "FRAME:or" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(8)} -pin  "FRAME:or" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(9)} -pin  "FRAME:or" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 14294 -attr oid 167 -attr vt dc -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)}
+load net {FRAME:or.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#8}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#8}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#8}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#8}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#8}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#8}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#8}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#8}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#8}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#8}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 14295 -attr oid 168 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp}
+load inst "FRAME:or#3" "or(2,6)" "INTERFACE" -attr xrf 14296 -attr oid 169 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3} -attr area 4.378994 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2)"
+load net {FRAME:acc#5.psp.sva(0)} -pin  "FRAME:or#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#2.itm}
+load net {FRAME:acc#5.psp.sva(1)} -pin  "FRAME:or#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#2.itm}
+load net {FRAME:acc#5.psp.sva(2)} -pin  "FRAME:or#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#2.itm}
+load net {FRAME:acc#5.psp.sva(3)} -pin  "FRAME:or#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#2.itm}
+load net {FRAME:acc#5.psp.sva(4)} -pin  "FRAME:or#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#2.itm}
+load net {FRAME:acc#5.psp.sva(5)} -pin  "FRAME:or#3" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#2.itm}
+load net {FRAME:acc#5.psp.sva(10)} -pin  "FRAME:or#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#60.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(1)} -attr @path {/sobel/sobel:core/conc#60.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(2)} -attr @path {/sobel/sobel:core/conc#60.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(3)} -attr @path {/sobel/sobel:core/conc#60.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(4)} -attr @path {/sobel/sobel:core/conc#60.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(5)} -attr @path {/sobel/sobel:core/conc#60.itm}
+load net {FRAME:or#3.itm(0)} -pin  "FRAME:or#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(1)} -pin  "FRAME:or#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(2)} -pin  "FRAME:or#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(3)} -pin  "FRAME:or#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(4)} -pin  "FRAME:or#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(5)} -pin  "FRAME:or#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)#2" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 14297 -attr oid 170 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#2}
+load net {FRAME:or#3.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#10}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#10}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#10}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#10}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#10}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#10}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {clk} -attr xrf 14298 -attr oid 171 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#2}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#2}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#2}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#2}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#2}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#2(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#2}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)#3" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 14299 -attr oid 172 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)#3}
+load net {FRAME:acc#5.psp.sva(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#11}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#11}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#11}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#11}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#11}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#11}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#11}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#11}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#11}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#11}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {clk} -attr xrf 14300 -attr oid 173 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#3}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#3}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#3}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#3}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#3}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#3}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#3}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#3}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#3}
+load net {reg(vout:rsc:mgc_out_stdreg.d).tmp#3(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d).tmp#3}
+### END MODULE 
+
+module new "sobel" "orig"
+load portBus {vin:rsc.z(89:0)} input 90 {vin:rsc.z(89)} {vin:rsc.z(88)} {vin:rsc.z(87)} {vin:rsc.z(86)} {vin:rsc.z(85)} {vin:rsc.z(84)} {vin:rsc.z(83)} {vin:rsc.z(82)} {vin:rsc.z(81)} {vin:rsc.z(80)} {vin:rsc.z(79)} {vin:rsc.z(78)} {vin:rsc.z(77)} {vin:rsc.z(76)} {vin:rsc.z(75)} {vin:rsc.z(74)} {vin:rsc.z(73)} {vin:rsc.z(72)} {vin:rsc.z(71)} {vin:rsc.z(70)} {vin:rsc.z(69)} {vin:rsc.z(68)} {vin:rsc.z(67)} {vin:rsc.z(66)} {vin:rsc.z(65)} {vin:rsc.z(64)} {vin:rsc.z(63)} {vin:rsc.z(62)} {vin:rsc.z(61)} {vin:rsc.z(60)} {vin:rsc.z(59)} {vin:rsc.z(58)} {vin:rsc.z(57)} {vin:rsc.z(56)} {vin:rsc.z(55)} {vin:rsc.z(54)} {vin:rsc.z(53)} {vin:rsc.z(52)} {vin:rsc.z(51)} {vin:rsc.z(50)} {vin:rsc.z(49)} {vin:rsc.z(48)} {vin:rsc.z(47)} {vin:rsc.z(46)} {vin:rsc.z(45)} {vin:rsc.z(44)} {vin:rsc.z(43)} {vin:rsc.z(42)} {vin:rsc.z(41)} {vin:rsc.z(40)} {vin:rsc.z(39)} {vin:rsc.z(38)} {vin:rsc.z(37)} {vin:rsc.z(36)} {vin:rsc.z(35)} {vin:rsc.z(34)} {vin:rsc.z(33)} {vin:rsc.z(32)} {vin:rsc.z(31)} {vin:rsc.z(30)} {vin:rsc.z(29)} {vin:rsc.z(28)} {vin:rsc.z(27)} {vin:rsc.z(26)} {vin:rsc.z(25)} {vin:rsc.z(24)} {vin:rsc.z(23)} {vin:rsc.z(22)} {vin:rsc.z(21)} {vin:rsc.z(20)} {vin:rsc.z(19)} {vin:rsc.z(18)} {vin:rsc.z(17)} {vin:rsc.z(16)} {vin:rsc.z(15)} {vin:rsc.z(14)} {vin:rsc.z(13)} {vin:rsc.z(12)} {vin:rsc.z(11)} {vin:rsc.z(10)} {vin:rsc.z(9)} {vin:rsc.z(8)} {vin:rsc.z(7)} {vin:rsc.z(6)} {vin:rsc.z(5)} {vin:rsc.z(4)} {vin:rsc.z(3)} {vin:rsc.z(2)} {vin:rsc.z(1)} {vin:rsc.z(0)} -attr xrf 14301 -attr oid 174 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load portBus {vout:rsc.z(29:0)} output 30 {vout:rsc.z(29)} {vout:rsc.z(28)} {vout:rsc.z(27)} {vout:rsc.z(26)} {vout:rsc.z(25)} {vout:rsc.z(24)} {vout:rsc.z(23)} {vout:rsc.z(22)} {vout:rsc.z(21)} {vout:rsc.z(20)} {vout:rsc.z(19)} {vout:rsc.z(18)} {vout:rsc.z(17)} {vout:rsc.z(16)} {vout:rsc.z(15)} {vout:rsc.z(14)} {vout:rsc.z(13)} {vout:rsc.z(12)} {vout:rsc.z(11)} {vout:rsc.z(10)} {vout:rsc.z(9)} {vout:rsc.z(8)} {vout:rsc.z(7)} {vout:rsc.z(6)} {vout:rsc.z(5)} {vout:rsc.z(4)} {vout:rsc.z(3)} {vout:rsc.z(2)} {vout:rsc.z(1)} {vout:rsc.z(0)} -attr xrf 14302 -attr oid 175 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load port {clk} input -attr xrf 14303 -attr oid 176 -attr vt d -attr @path {/sobel/clk}
+load port {en} input -attr xrf 14304 -attr oid 177 -attr vt d -attr @path {/sobel/en}
+load port {arst_n} input -attr xrf 14305 -attr oid 178 -attr vt d -attr @path {/sobel/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(89:0)} output 90 {d(89)} {d(88)} {d(87)} {d(86)} {d(85)} {d(84)} {d(83)} {d(82)} {d(81)} {d(80)} {d(79)} {d(78)} {d(77)} {d(76)} {d(75)} {d(74)} {d(73)} {d(72)} {d(71)} {d(70)} {d(69)} {d(68)} {d(67)} {d(66)} {d(65)} {d(64)} {d(63)} {d(62)} {d(61)} {d(60)} {d(59)} {d(58)} {d(57)} {d(56)} {d(55)} {d(54)} {d(53)} {d(52)} {d(51)} {d(50)} {d(49)} {d(48)} {d(47)} {d(46)} {d(45)} {d(44)} {d(43)} {d(42)} {d(41)} {d(40)} {d(39)} {d(38)} {d(37)} {d(36)} {d(35)} {d(34)} {d(33)} {d(32)} {d(31)} {d(30)} {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(89:0)} input 90 {z(89)} {z(88)} {z(87)} {z(86)} {z(85)} {z(84)} {z(83)} {z(82)} {z(81)} {z(80)} {z(79)} {z(78)} {z(77)} {z(76)} {z(75)} {z(74)} {z(73)} {z(72)} {z(71)} {z(70)} {z(69)} {z(68)} {z(67)} {z(66)} {z(65)} {z(64)} {z(63)} {z(62)} {z(61)} {z(60)} {z(59)} {z(58)} {z(57)} {z(56)} {z(55)} {z(54)} {z(53)} {z(52)} {z(51)} {z(50)} {z(49)} {z(48)} {z(47)} {z(46)} {z(45)} {z(44)} {z(43)} {z(42)} {z(41)} {z(40)} {z(39)} {z(38)} {z(37)} {z(36)} {z(35)} {z(34)} {z(33)} {z(32)} {z(31)} {z(30)} {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(29:0)} input 30 {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(29:0)} output 30 {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "sobel:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} \
+     portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} \
+
+load net {vin:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d#1} 90 {vin:rsc:mgc_in_wire.d#1(0)} {vin:rsc:mgc_in_wire.d#1(1)} {vin:rsc:mgc_in_wire.d#1(2)} {vin:rsc:mgc_in_wire.d#1(3)} {vin:rsc:mgc_in_wire.d#1(4)} {vin:rsc:mgc_in_wire.d#1(5)} {vin:rsc:mgc_in_wire.d#1(6)} {vin:rsc:mgc_in_wire.d#1(7)} {vin:rsc:mgc_in_wire.d#1(8)} {vin:rsc:mgc_in_wire.d#1(9)} {vin:rsc:mgc_in_wire.d#1(10)} {vin:rsc:mgc_in_wire.d#1(11)} {vin:rsc:mgc_in_wire.d#1(12)} {vin:rsc:mgc_in_wire.d#1(13)} {vin:rsc:mgc_in_wire.d#1(14)} {vin:rsc:mgc_in_wire.d#1(15)} {vin:rsc:mgc_in_wire.d#1(16)} {vin:rsc:mgc_in_wire.d#1(17)} {vin:rsc:mgc_in_wire.d#1(18)} {vin:rsc:mgc_in_wire.d#1(19)} {vin:rsc:mgc_in_wire.d#1(20)} {vin:rsc:mgc_in_wire.d#1(21)} {vin:rsc:mgc_in_wire.d#1(22)} {vin:rsc:mgc_in_wire.d#1(23)} {vin:rsc:mgc_in_wire.d#1(24)} {vin:rsc:mgc_in_wire.d#1(25)} {vin:rsc:mgc_in_wire.d#1(26)} {vin:rsc:mgc_in_wire.d#1(27)} {vin:rsc:mgc_in_wire.d#1(28)} {vin:rsc:mgc_in_wire.d#1(29)} {vin:rsc:mgc_in_wire.d#1(30)} {vin:rsc:mgc_in_wire.d#1(31)} {vin:rsc:mgc_in_wire.d#1(32)} {vin:rsc:mgc_in_wire.d#1(33)} {vin:rsc:mgc_in_wire.d#1(34)} {vin:rsc:mgc_in_wire.d#1(35)} {vin:rsc:mgc_in_wire.d#1(36)} {vin:rsc:mgc_in_wire.d#1(37)} {vin:rsc:mgc_in_wire.d#1(38)} {vin:rsc:mgc_in_wire.d#1(39)} {vin:rsc:mgc_in_wire.d#1(40)} {vin:rsc:mgc_in_wire.d#1(41)} {vin:rsc:mgc_in_wire.d#1(42)} {vin:rsc:mgc_in_wire.d#1(43)} {vin:rsc:mgc_in_wire.d#1(44)} {vin:rsc:mgc_in_wire.d#1(45)} {vin:rsc:mgc_in_wire.d#1(46)} {vin:rsc:mgc_in_wire.d#1(47)} {vin:rsc:mgc_in_wire.d#1(48)} {vin:rsc:mgc_in_wire.d#1(49)} {vin:rsc:mgc_in_wire.d#1(50)} {vin:rsc:mgc_in_wire.d#1(51)} {vin:rsc:mgc_in_wire.d#1(52)} {vin:rsc:mgc_in_wire.d#1(53)} {vin:rsc:mgc_in_wire.d#1(54)} {vin:rsc:mgc_in_wire.d#1(55)} {vin:rsc:mgc_in_wire.d#1(56)} {vin:rsc:mgc_in_wire.d#1(57)} {vin:rsc:mgc_in_wire.d#1(58)} {vin:rsc:mgc_in_wire.d#1(59)} {vin:rsc:mgc_in_wire.d#1(60)} {vin:rsc:mgc_in_wire.d#1(61)} {vin:rsc:mgc_in_wire.d#1(62)} {vin:rsc:mgc_in_wire.d#1(63)} {vin:rsc:mgc_in_wire.d#1(64)} {vin:rsc:mgc_in_wire.d#1(65)} {vin:rsc:mgc_in_wire.d#1(66)} {vin:rsc:mgc_in_wire.d#1(67)} {vin:rsc:mgc_in_wire.d#1(68)} {vin:rsc:mgc_in_wire.d#1(69)} {vin:rsc:mgc_in_wire.d#1(70)} {vin:rsc:mgc_in_wire.d#1(71)} {vin:rsc:mgc_in_wire.d#1(72)} {vin:rsc:mgc_in_wire.d#1(73)} {vin:rsc:mgc_in_wire.d#1(74)} {vin:rsc:mgc_in_wire.d#1(75)} {vin:rsc:mgc_in_wire.d#1(76)} {vin:rsc:mgc_in_wire.d#1(77)} {vin:rsc:mgc_in_wire.d#1(78)} {vin:rsc:mgc_in_wire.d#1(79)} {vin:rsc:mgc_in_wire.d#1(80)} {vin:rsc:mgc_in_wire.d#1(81)} {vin:rsc:mgc_in_wire.d#1(82)} {vin:rsc:mgc_in_wire.d#1(83)} {vin:rsc:mgc_in_wire.d#1(84)} {vin:rsc:mgc_in_wire.d#1(85)} {vin:rsc:mgc_in_wire.d#1(86)} {vin:rsc:mgc_in_wire.d#1(87)} {vin:rsc:mgc_in_wire.d#1(88)} {vin:rsc:mgc_in_wire.d#1(89)} -attr xrf 14306 -attr oid 179 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d#1} 30 {vout:rsc:mgc_out_stdreg.d#1(0)} {vout:rsc:mgc_out_stdreg.d#1(1)} {vout:rsc:mgc_out_stdreg.d#1(2)} {vout:rsc:mgc_out_stdreg.d#1(3)} {vout:rsc:mgc_out_stdreg.d#1(4)} {vout:rsc:mgc_out_stdreg.d#1(5)} {vout:rsc:mgc_out_stdreg.d#1(6)} {vout:rsc:mgc_out_stdreg.d#1(7)} {vout:rsc:mgc_out_stdreg.d#1(8)} {vout:rsc:mgc_out_stdreg.d#1(9)} {vout:rsc:mgc_out_stdreg.d#1(10)} {vout:rsc:mgc_out_stdreg.d#1(11)} {vout:rsc:mgc_out_stdreg.d#1(12)} {vout:rsc:mgc_out_stdreg.d#1(13)} {vout:rsc:mgc_out_stdreg.d#1(14)} {vout:rsc:mgc_out_stdreg.d#1(15)} {vout:rsc:mgc_out_stdreg.d#1(16)} {vout:rsc:mgc_out_stdreg.d#1(17)} {vout:rsc:mgc_out_stdreg.d#1(18)} {vout:rsc:mgc_out_stdreg.d#1(19)} {vout:rsc:mgc_out_stdreg.d#1(20)} {vout:rsc:mgc_out_stdreg.d#1(21)} {vout:rsc:mgc_out_stdreg.d#1(22)} {vout:rsc:mgc_out_stdreg.d#1(23)} {vout:rsc:mgc_out_stdreg.d#1(24)} {vout:rsc:mgc_out_stdreg.d#1(25)} {vout:rsc:mgc_out_stdreg.d#1(26)} {vout:rsc:mgc_out_stdreg.d#1(27)} {vout:rsc:mgc_out_stdreg.d#1(28)} {vout:rsc:mgc_out_stdreg.d#1(29)} -attr xrf 14307 -attr oid 180 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -attr vt d
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+load net {vin:rsc.z(87)} -attr vt d
+load net {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 14308 -attr oid 181 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(0)} -port {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -port {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -port {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -port {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -port {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -port {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -port {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -port {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -port {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -port {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -port {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -port {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -port {vin:rsc.z(12)} -attr vt d
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+load net {vin:rsc.z(15)} -port {vin:rsc.z(15)} -attr vt d
+load net {vin:rsc.z(16)} -port {vin:rsc.z(16)} -attr vt d
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+load net {vin:rsc.z(18)} -port {vin:rsc.z(18)} -attr vt d
+load net {vin:rsc.z(19)} -port {vin:rsc.z(19)} -attr vt d
+load net {vin:rsc.z(20)} -port {vin:rsc.z(20)} -attr vt d
+load net {vin:rsc.z(21)} -port {vin:rsc.z(21)} -attr vt d
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+load net {vin:rsc.z(23)} -port {vin:rsc.z(23)} -attr vt d
+load net {vin:rsc.z(24)} -port {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -port {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -port {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -port {vin:rsc.z(27)} -attr vt d
+load net {vin:rsc.z(28)} -port {vin:rsc.z(28)} -attr vt d
+load net {vin:rsc.z(29)} -port {vin:rsc.z(29)} -attr vt d
+load net {vin:rsc.z(30)} -port {vin:rsc.z(30)} -attr vt d
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+load net {vin:rsc.z(38)} -port {vin:rsc.z(38)} -attr vt d
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+load net {vin:rsc.z(42)} -port {vin:rsc.z(42)} -attr vt d
+load net {vin:rsc.z(43)} -port {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -port {vin:rsc.z(44)} -attr vt d
+load net {vin:rsc.z(45)} -port {vin:rsc.z(45)} -attr vt d
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+load net {vin:rsc.z(55)} -port {vin:rsc.z(55)} -attr vt d
+load net {vin:rsc.z(56)} -port {vin:rsc.z(56)} -attr vt d
+load net {vin:rsc.z(57)} -port {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -port {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -port {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -port {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -port {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -port {vin:rsc.z(62)} -attr vt d
+load net {vin:rsc.z(63)} -port {vin:rsc.z(63)} -attr vt d
+load net {vin:rsc.z(64)} -port {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -port {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -port {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -port {vin:rsc.z(67)} -attr vt d
+load net {vin:rsc.z(68)} -port {vin:rsc.z(68)} -attr vt d
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+load net {vin:rsc.z(76)} -port {vin:rsc.z(76)} -attr vt d
+load net {vin:rsc.z(77)} -port {vin:rsc.z(77)} -attr vt d
+load net {vin:rsc.z(78)} -port {vin:rsc.z(78)} -attr vt d
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+load net {vin:rsc.z(89)} -port {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 14309 -attr oid 182 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vout:rsc.z(0)} -attr vt d
+load net {vout:rsc.z(1)} -attr vt d
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+load net {vout:rsc.z(3)} -attr vt d
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+load net {vout:rsc.z(27)} -attr vt d
+load net {vout:rsc.z(28)} -attr vt d
+load net {vout:rsc.z(29)} -attr vt d
+load netBundle {vout:rsc.z} 30 {vout:rsc.z(0)} {vout:rsc.z(1)} {vout:rsc.z(2)} {vout:rsc.z(3)} {vout:rsc.z(4)} {vout:rsc.z(5)} {vout:rsc.z(6)} {vout:rsc.z(7)} {vout:rsc.z(8)} {vout:rsc.z(9)} {vout:rsc.z(10)} {vout:rsc.z(11)} {vout:rsc.z(12)} {vout:rsc.z(13)} {vout:rsc.z(14)} {vout:rsc.z(15)} {vout:rsc.z(16)} {vout:rsc.z(17)} {vout:rsc.z(18)} {vout:rsc.z(19)} {vout:rsc.z(20)} {vout:rsc.z(21)} {vout:rsc.z(22)} {vout:rsc.z(23)} {vout:rsc.z(24)} {vout:rsc.z(25)} {vout:rsc.z(26)} {vout:rsc.z(27)} {vout:rsc.z(28)} {vout:rsc.z(29)} -attr xrf 14310 -attr oid 183 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(0)} -port {vout:rsc.z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -port {vout:rsc.z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -port {vout:rsc.z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -port {vout:rsc.z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -port {vout:rsc.z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -port {vout:rsc.z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -port {vout:rsc.z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -port {vout:rsc.z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -port {vout:rsc.z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -port {vout:rsc.z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -port {vout:rsc.z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -port {vout:rsc.z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -port {vout:rsc.z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -port {vout:rsc.z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -port {vout:rsc.z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -port {vout:rsc.z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -port {vout:rsc.z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -port {vout:rsc.z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -port {vout:rsc.z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -port {vout:rsc.z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -port {vout:rsc.z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -port {vout:rsc.z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -port {vout:rsc.z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -port {vout:rsc.z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -port {vout:rsc.z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -port {vout:rsc.z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -port {vout:rsc.z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -port {vout:rsc.z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -port {vout:rsc.z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -port {vout:rsc.z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {clk} -attr xrf 14311 -attr oid 184
+load net {clk} -port {clk} -attr xrf 14312 -attr oid 185
+load net {en} -attr xrf 14313 -attr oid 186
+load net {en} -port {en} -attr xrf 14314 -attr oid 187
+load net {arst_n} -attr xrf 14315 -attr oid 188
+load net {arst_n} -port {arst_n} -attr xrf 14316 -attr oid 189
+load inst "sobel:core:inst" "sobel:core" "orig" -attr xrf 14317 -attr oid 190 -attr vt dc -attr @path {/sobel/sobel:core:inst} -attr area 581.424289 -attr delay 14.432003 -attr hier "/sobel/sobel:core" -pg 1 -lvl 3
+load net {clk} -pin  "sobel:core:inst" {clk#1} -attr xrf 14318 -attr oid 191 -attr @path {/sobel/clk}
+load net {en} -pin  "sobel:core:inst" {en#1} -attr xrf 14319 -attr oid 192 -attr @path {/sobel/en}
+load net {arst_n} -pin  "sobel:core:inst" {arst_n#1} -attr xrf 14320 -attr oid 193 -attr @path {/sobel/arst_n}
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(8)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(9)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(10)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(11)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(12)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(13)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(14)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(15)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(16)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(17)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(18)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(19)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(20)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(21)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(22)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(23)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(24)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(25)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(26)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(27)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(28)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(29)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(30)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(31)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(32)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(33)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(34)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(35)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(36)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(37)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(38)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(39)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(40)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(41)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(42)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(43)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(44)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(45)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(46)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(47)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(48)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(49)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(50)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(51)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(52)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(53)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(54)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(55)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(56)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(57)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(58)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(59)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(60)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(61)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(62)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(63)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(64)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(65)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(66)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(67)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(68)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(69)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(70)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(71)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(72)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(73)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(74)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(75)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(76)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(77)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(78)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(79)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(80)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(81)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(82)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(83)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(84)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(85)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(86)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(87)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(88)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(89)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(8)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(9)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(10)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(11)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(12)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(13)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(14)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(15)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(16)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(17)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(18)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(19)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(20)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(21)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(22)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(23)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(24)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(25)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(26)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(27)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(28)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(29)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load inst "vin:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" -attr xrf 14321 -attr oid 194 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,90)" -pg 1 -lvl 1
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "vin:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "vin:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "vin:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "vin:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "vin:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "vin:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "vin:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "vin:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "vin:rsc:mgc_in_wire" {d(8)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "vin:rsc:mgc_in_wire" {d(9)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "vin:rsc:mgc_in_wire" {d(10)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "vin:rsc:mgc_in_wire" {d(11)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "vin:rsc:mgc_in_wire" {d(12)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "vin:rsc:mgc_in_wire" {d(13)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "vin:rsc:mgc_in_wire" {d(14)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "vin:rsc:mgc_in_wire" {d(15)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "vin:rsc:mgc_in_wire" {d(16)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "vin:rsc:mgc_in_wire" {d(17)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "vin:rsc:mgc_in_wire" {d(18)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "vin:rsc:mgc_in_wire" {d(19)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "vin:rsc:mgc_in_wire" {d(20)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "vin:rsc:mgc_in_wire" {d(21)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "vin:rsc:mgc_in_wire" {d(22)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "vin:rsc:mgc_in_wire" {d(23)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "vin:rsc:mgc_in_wire" {d(24)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "vin:rsc:mgc_in_wire" {d(25)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "vin:rsc:mgc_in_wire" {d(26)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "vin:rsc:mgc_in_wire" {d(27)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "vin:rsc:mgc_in_wire" {d(28)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "vin:rsc:mgc_in_wire" {d(29)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "vin:rsc:mgc_in_wire" {d(30)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "vin:rsc:mgc_in_wire" {d(31)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "vin:rsc:mgc_in_wire" {d(32)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "vin:rsc:mgc_in_wire" {d(33)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "vin:rsc:mgc_in_wire" {d(34)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "vin:rsc:mgc_in_wire" {d(35)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "vin:rsc:mgc_in_wire" {d(36)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "vin:rsc:mgc_in_wire" {d(37)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "vin:rsc:mgc_in_wire" {d(38)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "vin:rsc:mgc_in_wire" {d(39)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "vin:rsc:mgc_in_wire" {d(40)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "vin:rsc:mgc_in_wire" {d(41)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "vin:rsc:mgc_in_wire" {d(42)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "vin:rsc:mgc_in_wire" {d(43)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "vin:rsc:mgc_in_wire" {d(44)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "vin:rsc:mgc_in_wire" {d(45)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "vin:rsc:mgc_in_wire" {d(46)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "vin:rsc:mgc_in_wire" {d(47)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "vin:rsc:mgc_in_wire" {d(48)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "vin:rsc:mgc_in_wire" {d(49)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "vin:rsc:mgc_in_wire" {d(50)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "vin:rsc:mgc_in_wire" {d(51)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "vin:rsc:mgc_in_wire" {d(52)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "vin:rsc:mgc_in_wire" {d(53)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "vin:rsc:mgc_in_wire" {d(54)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "vin:rsc:mgc_in_wire" {d(55)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "vin:rsc:mgc_in_wire" {d(56)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "vin:rsc:mgc_in_wire" {d(57)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "vin:rsc:mgc_in_wire" {d(58)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "vin:rsc:mgc_in_wire" {d(59)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "vin:rsc:mgc_in_wire" {d(60)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "vin:rsc:mgc_in_wire" {d(61)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "vin:rsc:mgc_in_wire" {d(62)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "vin:rsc:mgc_in_wire" {d(63)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "vin:rsc:mgc_in_wire" {d(64)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "vin:rsc:mgc_in_wire" {d(65)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "vin:rsc:mgc_in_wire" {d(66)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "vin:rsc:mgc_in_wire" {d(67)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "vin:rsc:mgc_in_wire" {d(68)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "vin:rsc:mgc_in_wire" {d(69)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "vin:rsc:mgc_in_wire" {d(70)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "vin:rsc:mgc_in_wire" {d(71)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "vin:rsc:mgc_in_wire" {d(72)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "vin:rsc:mgc_in_wire" {d(73)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "vin:rsc:mgc_in_wire" {d(74)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "vin:rsc:mgc_in_wire" {d(75)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "vin:rsc:mgc_in_wire" {d(76)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "vin:rsc:mgc_in_wire" {d(77)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "vin:rsc:mgc_in_wire" {d(78)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "vin:rsc:mgc_in_wire" {d(79)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "vin:rsc:mgc_in_wire" {d(80)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "vin:rsc:mgc_in_wire" {d(81)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "vin:rsc:mgc_in_wire" {d(82)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "vin:rsc:mgc_in_wire" {d(83)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "vin:rsc:mgc_in_wire" {d(84)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "vin:rsc:mgc_in_wire" {d(85)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "vin:rsc:mgc_in_wire" {d(86)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "vin:rsc:mgc_in_wire" {d(87)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "vin:rsc:mgc_in_wire" {d(88)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "vin:rsc:mgc_in_wire" {d(89)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc.z(0)} -pin  "vin:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(1)} -pin  "vin:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(2)} -pin  "vin:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(3)} -pin  "vin:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(4)} -pin  "vin:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(5)} -pin  "vin:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(6)} -pin  "vin:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(7)} -pin  "vin:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(8)} -pin  "vin:rsc:mgc_in_wire" {z(8)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(9)} -pin  "vin:rsc:mgc_in_wire" {z(9)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(10)} -pin  "vin:rsc:mgc_in_wire" {z(10)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(11)} -pin  "vin:rsc:mgc_in_wire" {z(11)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(12)} -pin  "vin:rsc:mgc_in_wire" {z(12)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(13)} -pin  "vin:rsc:mgc_in_wire" {z(13)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(14)} -pin  "vin:rsc:mgc_in_wire" {z(14)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(15)} -pin  "vin:rsc:mgc_in_wire" {z(15)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(16)} -pin  "vin:rsc:mgc_in_wire" {z(16)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(17)} -pin  "vin:rsc:mgc_in_wire" {z(17)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(18)} -pin  "vin:rsc:mgc_in_wire" {z(18)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(19)} -pin  "vin:rsc:mgc_in_wire" {z(19)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(20)} -pin  "vin:rsc:mgc_in_wire" {z(20)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(21)} -pin  "vin:rsc:mgc_in_wire" {z(21)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(22)} -pin  "vin:rsc:mgc_in_wire" {z(22)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(23)} -pin  "vin:rsc:mgc_in_wire" {z(23)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(24)} -pin  "vin:rsc:mgc_in_wire" {z(24)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(25)} -pin  "vin:rsc:mgc_in_wire" {z(25)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(26)} -pin  "vin:rsc:mgc_in_wire" {z(26)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(27)} -pin  "vin:rsc:mgc_in_wire" {z(27)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(28)} -pin  "vin:rsc:mgc_in_wire" {z(28)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(29)} -pin  "vin:rsc:mgc_in_wire" {z(29)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(30)} -pin  "vin:rsc:mgc_in_wire" {z(30)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(31)} -pin  "vin:rsc:mgc_in_wire" {z(31)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(32)} -pin  "vin:rsc:mgc_in_wire" {z(32)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(33)} -pin  "vin:rsc:mgc_in_wire" {z(33)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(34)} -pin  "vin:rsc:mgc_in_wire" {z(34)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(35)} -pin  "vin:rsc:mgc_in_wire" {z(35)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(36)} -pin  "vin:rsc:mgc_in_wire" {z(36)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(37)} -pin  "vin:rsc:mgc_in_wire" {z(37)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(38)} -pin  "vin:rsc:mgc_in_wire" {z(38)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(39)} -pin  "vin:rsc:mgc_in_wire" {z(39)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(40)} -pin  "vin:rsc:mgc_in_wire" {z(40)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(41)} -pin  "vin:rsc:mgc_in_wire" {z(41)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(42)} -pin  "vin:rsc:mgc_in_wire" {z(42)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(43)} -pin  "vin:rsc:mgc_in_wire" {z(43)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(44)} -pin  "vin:rsc:mgc_in_wire" {z(44)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(45)} -pin  "vin:rsc:mgc_in_wire" {z(45)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(46)} -pin  "vin:rsc:mgc_in_wire" {z(46)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(47)} -pin  "vin:rsc:mgc_in_wire" {z(47)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(48)} -pin  "vin:rsc:mgc_in_wire" {z(48)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(49)} -pin  "vin:rsc:mgc_in_wire" {z(49)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(50)} -pin  "vin:rsc:mgc_in_wire" {z(50)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(51)} -pin  "vin:rsc:mgc_in_wire" {z(51)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(52)} -pin  "vin:rsc:mgc_in_wire" {z(52)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(53)} -pin  "vin:rsc:mgc_in_wire" {z(53)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(54)} -pin  "vin:rsc:mgc_in_wire" {z(54)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(55)} -pin  "vin:rsc:mgc_in_wire" {z(55)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(56)} -pin  "vin:rsc:mgc_in_wire" {z(56)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(57)} -pin  "vin:rsc:mgc_in_wire" {z(57)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(58)} -pin  "vin:rsc:mgc_in_wire" {z(58)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(59)} -pin  "vin:rsc:mgc_in_wire" {z(59)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(60)} -pin  "vin:rsc:mgc_in_wire" {z(60)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(61)} -pin  "vin:rsc:mgc_in_wire" {z(61)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(62)} -pin  "vin:rsc:mgc_in_wire" {z(62)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(63)} -pin  "vin:rsc:mgc_in_wire" {z(63)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(64)} -pin  "vin:rsc:mgc_in_wire" {z(64)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(65)} -pin  "vin:rsc:mgc_in_wire" {z(65)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(66)} -pin  "vin:rsc:mgc_in_wire" {z(66)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(67)} -pin  "vin:rsc:mgc_in_wire" {z(67)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(68)} -pin  "vin:rsc:mgc_in_wire" {z(68)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(69)} -pin  "vin:rsc:mgc_in_wire" {z(69)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(70)} -pin  "vin:rsc:mgc_in_wire" {z(70)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(71)} -pin  "vin:rsc:mgc_in_wire" {z(71)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(72)} -pin  "vin:rsc:mgc_in_wire" {z(72)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(73)} -pin  "vin:rsc:mgc_in_wire" {z(73)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(74)} -pin  "vin:rsc:mgc_in_wire" {z(74)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(75)} -pin  "vin:rsc:mgc_in_wire" {z(75)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(76)} -pin  "vin:rsc:mgc_in_wire" {z(76)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(77)} -pin  "vin:rsc:mgc_in_wire" {z(77)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(78)} -pin  "vin:rsc:mgc_in_wire" {z(78)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(79)} -pin  "vin:rsc:mgc_in_wire" {z(79)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(80)} -pin  "vin:rsc:mgc_in_wire" {z(80)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(81)} -pin  "vin:rsc:mgc_in_wire" {z(81)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(82)} -pin  "vin:rsc:mgc_in_wire" {z(82)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(83)} -pin  "vin:rsc:mgc_in_wire" {z(83)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(84)} -pin  "vin:rsc:mgc_in_wire" {z(84)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(85)} -pin  "vin:rsc:mgc_in_wire" {z(85)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(86)} -pin  "vin:rsc:mgc_in_wire" {z(86)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(87)} -pin  "vin:rsc:mgc_in_wire" {z(87)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(88)} -pin  "vin:rsc:mgc_in_wire" {z(88)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(89)} -pin  "vin:rsc:mgc_in_wire" {z(89)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load inst "vout:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" -attr xrf 14322 -attr oid 195 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(2,30)" -pg 1 -lvl 1002
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "vout:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "vout:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "vout:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "vout:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "vout:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "vout:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "vout:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "vout:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "vout:rsc:mgc_out_stdreg" {d(8)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "vout:rsc:mgc_out_stdreg" {d(9)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "vout:rsc:mgc_out_stdreg" {d(10)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "vout:rsc:mgc_out_stdreg" {d(11)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "vout:rsc:mgc_out_stdreg" {d(12)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "vout:rsc:mgc_out_stdreg" {d(13)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "vout:rsc:mgc_out_stdreg" {d(14)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "vout:rsc:mgc_out_stdreg" {d(15)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "vout:rsc:mgc_out_stdreg" {d(16)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "vout:rsc:mgc_out_stdreg" {d(17)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "vout:rsc:mgc_out_stdreg" {d(18)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "vout:rsc:mgc_out_stdreg" {d(19)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "vout:rsc:mgc_out_stdreg" {d(20)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "vout:rsc:mgc_out_stdreg" {d(21)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "vout:rsc:mgc_out_stdreg" {d(22)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "vout:rsc:mgc_out_stdreg" {d(23)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "vout:rsc:mgc_out_stdreg" {d(24)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "vout:rsc:mgc_out_stdreg" {d(25)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "vout:rsc:mgc_out_stdreg" {d(26)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "vout:rsc:mgc_out_stdreg" {d(27)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "vout:rsc:mgc_out_stdreg" {d(28)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "vout:rsc:mgc_out_stdreg" {d(29)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc.z(0)} -pin  "vout:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -pin  "vout:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -pin  "vout:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -pin  "vout:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -pin  "vout:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -pin  "vout:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -pin  "vout:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -pin  "vout:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -pin  "vout:rsc:mgc_out_stdreg" {z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -pin  "vout:rsc:mgc_out_stdreg" {z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -pin  "vout:rsc:mgc_out_stdreg" {z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -pin  "vout:rsc:mgc_out_stdreg" {z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -pin  "vout:rsc:mgc_out_stdreg" {z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -pin  "vout:rsc:mgc_out_stdreg" {z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -pin  "vout:rsc:mgc_out_stdreg" {z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -pin  "vout:rsc:mgc_out_stdreg" {z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -pin  "vout:rsc:mgc_out_stdreg" {z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -pin  "vout:rsc:mgc_out_stdreg" {z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -pin  "vout:rsc:mgc_out_stdreg" {z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -pin  "vout:rsc:mgc_out_stdreg" {z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -pin  "vout:rsc:mgc_out_stdreg" {z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -pin  "vout:rsc:mgc_out_stdreg" {z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -pin  "vout:rsc:mgc_out_stdreg" {z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -pin  "vout:rsc:mgc_out_stdreg" {z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -pin  "vout:rsc:mgc_out_stdreg" {z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -pin  "vout:rsc:mgc_out_stdreg" {z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -pin  "vout:rsc:mgc_out_stdreg" {z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -pin  "vout:rsc:mgc_out_stdreg" {z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -pin  "vout:rsc:mgc_out_stdreg" {z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -pin  "vout:rsc:mgc_out_stdreg" {z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+### END MODULE 
+
diff --git a/Sobel/sobel.v6/concat_rtl.v b/Sobel/sobel.v6/concat_rtl.v
new file mode 100644
index 0000000..870e3e7
--- /dev/null
+++ b/Sobel/sobel.v6/concat_rtl.v
@@ -0,0 +1,2350 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:54:00 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [29:0] regs_regs_1_1_sva;
+  reg [29:0] regs_regs_1_sg2_sva;
+  reg [9:0] regs_regs_slc_regs_regs_2_6_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_7_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_sg2_1_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_sg2_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_sg2_itm;
+  reg [15:0] ACC1_acc_281_itm_1;
+  wire [18:0] nl_ACC1_acc_281_itm_1;
+  reg [12:0] mul_1_itm_1;
+  wire [25:0] nl_mul_1_itm_1;
+  reg ACC1_2_slc_acc_idiv_131_itm_1;
+  reg [7:0] ACC1_mul_99_itm_1;
+  wire [15:0] nl_ACC1_mul_99_itm_1;
+  reg ACC1_slc_acc_imod_17_8_itm_1;
+  reg ACC1_2_slc_acc_idiv_106_itm_1;
+  reg [9:0] ACC1_acc_264_itm_1;
+  wire [10:0] nl_ACC1_acc_264_itm_1;
+  reg [11:0] ACC1_mul_90_itm_1;
+  wire [23:0] nl_ACC1_mul_90_itm_1;
+  reg [13:0] ACC1_mul_91_itm_1;
+  wire [27:0] nl_ACC1_mul_91_itm_1;
+  reg [9:0] ACC1_mul_104_itm_1;
+  wire [19:0] nl_ACC1_mul_104_itm_1;
+  reg ACC1_slc_acc_idiv_2_90_itm_1;
+  reg ACC1_3_slc_acc_idiv_132_itm_1;
+  reg [7:0] ACC1_mul_103_itm_1;
+  wire [15:0] nl_ACC1_mul_103_itm_1;
+  reg ACC1_slc_acc_idiv_91_itm_1;
+  reg ACC1_3_slc_acc_idiv_131_itm_1;
+  reg [5:0] ACC1_mul_98_itm_1;
+  wire [11:0] nl_ACC1_mul_98_itm_1;
+  reg ACC1_slc_acc_idiv_3_36_itm_1;
+  reg ACC1_2_slc_acc_idiv_132_itm_1;
+  reg [5:0] ACC1_acc_252_itm_1;
+  wire [6:0] nl_ACC1_acc_252_itm_1;
+  reg [5:0] ACC1_acc_251_itm_1;
+  wire [6:0] nl_ACC1_acc_251_itm_1;
+  reg [6:0] ACC1_acc_255_itm_1;
+  wire [7:0] nl_ACC1_acc_255_itm_1;
+  reg [9:0] ACC1_mul_89_itm_1;
+  wire [19:0] nl_ACC1_mul_89_itm_1;
+  reg [11:0] ACC1_acc_268_itm_1;
+  wire [12:0] nl_ACC1_acc_268_itm_1;
+  reg [13:0] ACC1_mul_96_itm_1;
+  wire [27:0] nl_ACC1_mul_96_itm_1;
+  reg ACC1_slc_acc_imod_28_itm_1;
+  reg [5:0] FRAME_acc_12_itm_1;
+  wire [6:0] nl_FRAME_acc_12_itm_1;
+  reg [1:0] intensity_slc_intensity_2_sg1_9_itm_1;
+  reg [2:0] intensity_slc_intensity_2_sg1_11_itm_1;
+  reg [5:0] intensity_slc_intensity_2_sg1_itm_1;
+  reg intensity_slc_intensity_2_sg1_12_itm_1;
+  reg main_stage_0_2;
+  reg main_stage_0_3;
+  wire [11:0] FRAME_acc_5_psp_sva;
+  wire [13:0] nl_FRAME_acc_5_psp_sva;
+  wire [5:0] acc_imod_15_sva;
+  wire [6:0] nl_acc_imod_15_sva;
+  wire [17:0] acc_idiv_3_sva;
+  wire [18:0] nl_acc_idiv_3_sva;
+  wire [17:0] acc_idiv_7_sva;
+  wire [18:0] nl_acc_idiv_7_sva;
+  wire [17:0] acc_idiv_sva;
+  wire [18:0] nl_acc_idiv_sva;
+  wire [17:0] acc_idiv_2_sva;
+  wire [18:0] nl_acc_idiv_2_sva;
+  wire [2:0] acc_imod_19_sva;
+  wire [3:0] nl_acc_imod_19_sva;
+  wire [2:0] acc_imod_7_sva;
+  wire [3:0] nl_acc_imod_7_sva;
+  wire [3:0] ACC1_acc_230_sdt;
+  wire [4:0] nl_ACC1_acc_230_sdt;
+  wire [2:0] acc_imod_1_sva;
+  wire [3:0] nl_acc_imod_1_sva;
+  wire [2:0] acc_imod_27_sva;
+  wire [3:0] nl_acc_imod_27_sva;
+  wire [15:0] ACC1_acc_itm;
+  wire [18:0] nl_ACC1_acc_itm;
+  wire [5:0] ACC1_acc_189_itm;
+  wire [6:0] nl_ACC1_acc_189_itm;
+  wire [5:0] ACC1_acc_162_itm;
+  wire [6:0] nl_ACC1_acc_162_itm;
+  wire [5:0] ACC1_acc_201_itm;
+  wire [6:0] nl_ACC1_acc_201_itm;
+  wire [5:0] ACC1_acc_174_itm;
+  wire [6:0] nl_ACC1_acc_174_itm;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_5_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(intensity_slc_intensity_2_sg1_9_itm_1)
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(intensity_slc_intensity_2_sg1_11_itm_1)
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(intensity_slc_intensity_2_sg1_itm_1)
+      + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_15_sva[5])) , 1'b1
+      , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_15_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_15_sva[5:3])) , (~ (acc_imod_15_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_15_sva[4:3]))
+      + conv_u2u_3_5(~ (intensity_slc_intensity_2_sg1_itm_1[5:3]))) + ({4'b1001 ,
+      (acc_imod_15_sva[5])}))))) + conv_u2u_11_12(signext_11_9({intensity_slc_intensity_2_sg1_12_itm_1
+      , 3'b0 , ({{2{intensity_slc_intensity_2_sg1_12_itm_1}}, intensity_slc_intensity_2_sg1_12_itm_1})
+      , 1'b0 , intensity_slc_intensity_2_sg1_12_itm_1}));
+  assign FRAME_acc_5_psp_sva = nl_FRAME_acc_5_psp_sva[11:0];
+  assign nl_acc_imod_15_sva = FRAME_acc_12_itm_1 + 6'b101011;
+  assign acc_imod_15_sva = nl_acc_imod_15_sva[5:0];
+  assign nl_ACC1_acc_itm = ACC1_acc_281_itm_1 + ((({mul_1_itm_1 , 1'b0 , ({{1{ACC1_2_slc_acc_idiv_131_itm_1}},
+      ACC1_2_slc_acc_idiv_131_itm_1})}) + conv_s2s_15_16(conv_s2s_14_15(conv_s2s_12_14(conv_u2s_11_12({ACC1_mul_99_itm_1
+      , ACC1_slc_acc_imod_17_8_itm_1 , ({{1{ACC1_2_slc_acc_idiv_106_itm_1}}, ACC1_2_slc_acc_idiv_106_itm_1})})
+      + conv_s2s_10_12(ACC1_acc_264_itm_1)) + conv_u2s_12_14(ACC1_mul_90_itm_1))
+      + conv_u2s_14_15(ACC1_mul_91_itm_1))) + (conv_u2u_15_16(conv_u2u_14_15({ACC1_mul_104_itm_1
+      , ACC1_slc_acc_idiv_2_90_itm_1 , 1'b0 , ({{1{ACC1_3_slc_acc_idiv_132_itm_1}},
+      ACC1_3_slc_acc_idiv_132_itm_1})}) + conv_u2u_13_15(conv_u2u_12_13(({ACC1_mul_103_itm_1
+      , ACC1_slc_acc_idiv_91_itm_1 , 1'b0 , ({{1{ACC1_3_slc_acc_idiv_131_itm_1}},
+      ACC1_3_slc_acc_idiv_131_itm_1})}) + conv_u2u_11_12(conv_u2u_10_11(conv_u2u_9_10({ACC1_mul_98_itm_1
+      , ACC1_slc_acc_idiv_3_36_itm_1 , ({{1{ACC1_2_slc_acc_idiv_132_itm_1}}, ACC1_2_slc_acc_idiv_132_itm_1})})
+      + conv_u2u_8_10(conv_u2u_7_8(conv_u2u_6_7(ACC1_acc_252_itm_1) + conv_u2u_6_7(ACC1_acc_251_itm_1))
+      + conv_u2u_7_8(ACC1_acc_255_itm_1))) + conv_u2u_10_11(ACC1_mul_89_itm_1)))
+      + conv_u2u_12_13(ACC1_acc_268_itm_1))) + conv_u2u_15_16({ACC1_mul_96_itm_1
+      , ACC1_slc_acc_imod_28_itm_1})));
+  assign ACC1_acc_itm = nl_ACC1_acc_itm[15:0];
+  assign nl_ACC1_acc_189_itm = ({(readslicef_6_5_1((conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_sva[8])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_sva[9])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (acc_idiv_sva[1])) , (~ (acc_idiv_sva[13]))})))) , 1'b1}) + conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_sva[3])) , (acc_idiv_sva[12])})))) ,
+      (~ (acc_idiv_sva[15]))})))) , 1'b1}) + conv_u2u_4_6({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_sva[5])) , (~ (acc_idiv_sva[11]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_sva[6])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_sva[7])) , (acc_idiv_sva[10])})))) ,
+      (acc_idiv_sva[14])})))) , (acc_idiv_sva[16])})))) , 1'b1}) + ({4'b1011 , (acc_idiv_sva[0])
+      , (~ (acc_idiv_sva[17]))});
+  assign ACC1_acc_189_itm = nl_ACC1_acc_189_itm[5:0];
+  assign nl_acc_idiv_3_sva = conv_u2u_17_18(conv_u2u_16_17(signext_16_10(vin_rsc_mgc_in_wire_d[19:10]))
+      + conv_u2u_16_17(signext_16_10(vin_rsc_mgc_in_wire_d[9:0]))) + conv_u2u_16_18(signext_16_10(vin_rsc_mgc_in_wire_d[29:20]));
+  assign acc_idiv_3_sva = nl_acc_idiv_3_sva[17:0];
+  assign nl_acc_idiv_7_sva = conv_u2u_17_18(conv_u2u_16_17(signext_16_10(vin_rsc_mgc_in_wire_d[79:70]))
+      + conv_u2u_16_17(signext_16_10(vin_rsc_mgc_in_wire_d[69:60]))) + conv_u2u_16_18(signext_16_10(vin_rsc_mgc_in_wire_d[89:80]));
+  assign acc_idiv_7_sva = nl_acc_idiv_7_sva[17:0];
+  assign nl_acc_idiv_sva = conv_u2u_17_18(conv_u2u_16_17(signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      regs_regs_slc_regs_regs_2_6_itm) , 1'b1}) + conv_s2s_11_12({(vin_rsc_mgc_in_wire_d[19:10])
+      , 1'b1}))))) + conv_u2u_16_17(signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      regs_regs_slc_regs_regs_2_7_itm) , 1'b1}) + conv_s2s_11_12({(vin_rsc_mgc_in_wire_d[9:0])
+      , 1'b1})))))) + conv_u2u_16_18(signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      regs_regs_slc_regs_regs_2_itm) , 1'b1}) + conv_s2s_11_12({(vin_rsc_mgc_in_wire_d[29:20])
+      , 1'b1})))));
+  assign acc_idiv_sva = nl_acc_idiv_sva[17:0];
+  assign nl_acc_idiv_2_sva = conv_u2u_17_18(conv_u2u_16_17(signext_16_11(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[79:70])
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_sg2_1_itm))) + conv_u2u_16_17(signext_16_11(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[69:60])
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_sg2_2_itm)))) + conv_u2u_16_18(signext_16_11(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[89:80])
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_sg2_itm)));
+  assign acc_idiv_2_sva = nl_acc_idiv_2_sva[17:0];
+  assign nl_ACC1_acc_162_itm = ({(readslicef_6_5_1((conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_3_sva[8])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_3_sva[9])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (acc_idiv_3_sva[1])) , (~ (acc_idiv_3_sva[13]))})))) , 1'b1}) + conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_3_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_3_sva[3])) , (acc_idiv_3_sva[12])}))))
+      , (~ (acc_idiv_3_sva[15]))})))) , 1'b1}) + conv_u2u_4_6({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_3_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_3_sva[5])) , (~ (acc_idiv_3_sva[11]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_3_sva[6])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_3_sva[7])) , (acc_idiv_3_sva[10])}))))
+      , (acc_idiv_3_sva[14])})))) , (acc_idiv_3_sva[16])})))) , 1'b1}) + ({4'b1011
+      , (acc_idiv_3_sva[0]) , (~ (acc_idiv_3_sva[17]))});
+  assign ACC1_acc_162_itm = nl_ACC1_acc_162_itm[5:0];
+  assign nl_acc_imod_19_sva = (readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_162_itm[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_162_itm[4])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (ACC1_acc_162_itm[2])) , (~ (ACC1_acc_162_itm[5]))})))) + ({2'b10 , (ACC1_acc_162_itm[1])});
+  assign acc_imod_19_sva = nl_acc_imod_19_sva[2:0];
+  assign nl_ACC1_acc_201_itm = ({(readslicef_6_5_1((conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_2_sva[8])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_2_sva[9])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (acc_idiv_2_sva[1])) , (~ (acc_idiv_2_sva[13]))})))) , 1'b1}) + conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_2_sva[3])) , (acc_idiv_2_sva[12])}))))
+      , (~ (acc_idiv_2_sva[15]))})))) , 1'b1}) + conv_u2u_4_6({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_2_sva[5])) , (~ (acc_idiv_2_sva[11]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_2_sva[6])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_2_sva[7])) , (acc_idiv_2_sva[10])}))))
+      , (acc_idiv_2_sva[14])})))) , (acc_idiv_2_sva[16])})))) , 1'b1}) + ({4'b1011
+      , (acc_idiv_2_sva[0]) , (~ (acc_idiv_2_sva[17]))});
+  assign ACC1_acc_201_itm = nl_ACC1_acc_201_itm[5:0];
+  assign nl_ACC1_acc_174_itm = ({(readslicef_6_5_1((conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[8])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_7_sva[9])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (acc_idiv_7_sva[1])) , (~ (acc_idiv_7_sva[13]))})))) , 1'b1}) + conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_7_sva[3])) , (acc_idiv_7_sva[12])}))))
+      , (~ (acc_idiv_7_sva[15]))})))) , 1'b1}) + conv_u2u_4_6({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_7_sva[5])) , (~ (acc_idiv_7_sva[11]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[6])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_7_sva[7])) , (acc_idiv_7_sva[10])}))))
+      , (acc_idiv_7_sva[14])})))) , (acc_idiv_7_sva[16])})))) , 1'b1}) + ({4'b1011
+      , (acc_idiv_7_sva[0]) , (~ (acc_idiv_7_sva[17]))});
+  assign ACC1_acc_174_itm = nl_ACC1_acc_174_itm[5:0];
+  assign nl_acc_imod_7_sva = (readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_201_itm[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_201_itm[4])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (ACC1_acc_201_itm[2])) , (~ (ACC1_acc_201_itm[5]))})))) + ({2'b10 , (ACC1_acc_201_itm[1])});
+  assign acc_imod_7_sva = nl_acc_imod_7_sva[2:0];
+  assign nl_ACC1_acc_230_sdt = conv_u2u_3_4(conv_u2u_2_3({(~ (ACC1_acc_174_itm[5]))
+      , (~ (ACC1_acc_189_itm[5]))}) + conv_u2u_2_3({(acc_imod_27_sva[1]) , 1'b1}))
+      + conv_u2u_3_4(conv_u2u_2_3({(~ (acc_imod_27_sva[2])) , (~ (acc_imod_1_sva[2]))})
+      + conv_u2u_2_3({(~ (readslicef_3_1_2((({1'b1 , (acc_imod_27_sva[0]) , 1'b1})
+      + conv_u2s_2_3({(~ (acc_imod_27_sva[1])) , (~ (acc_imod_27_sva[2]))}))))) ,
+      (~ (readslicef_3_1_2((({1'b1 , (acc_imod_1_sva[0]) , 1'b1}) + conv_u2s_2_3({(~
+      (acc_imod_1_sva[1])) , (~ (acc_imod_1_sva[2]))})))))}));
+  assign ACC1_acc_230_sdt = nl_ACC1_acc_230_sdt[3:0];
+  assign nl_acc_imod_1_sva = (readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_189_itm[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_189_itm[4])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (ACC1_acc_189_itm[2])) , (~ (ACC1_acc_189_itm[5]))})))) + ({2'b10 , (ACC1_acc_189_itm[1])});
+  assign acc_imod_1_sva = nl_acc_imod_1_sva[2:0];
+  assign nl_acc_imod_27_sva = (readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_174_itm[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_174_itm[4])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (ACC1_acc_174_itm[2])) , (~ (ACC1_acc_174_itm[5]))})))) + ({2'b10 , (ACC1_acc_174_itm[1])});
+  assign acc_imod_27_sva = nl_acc_imod_27_sva[2:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      intensity_slc_intensity_2_sg1_9_itm_1 <= 2'b0;
+      intensity_slc_intensity_2_sg1_11_itm_1 <= 3'b0;
+      intensity_slc_intensity_2_sg1_itm_1 <= 6'b0;
+      intensity_slc_intensity_2_sg1_12_itm_1 <= 1'b0;
+      FRAME_acc_12_itm_1 <= 6'b0;
+      main_stage_0_2 <= 1'b0;
+      main_stage_0_3 <= 1'b0;
+      ACC1_acc_281_itm_1 <= 16'b0;
+      mul_1_itm_1 <= 13'b0;
+      ACC1_2_slc_acc_idiv_131_itm_1 <= 1'b0;
+      ACC1_mul_99_itm_1 <= 8'b0;
+      ACC1_slc_acc_imod_17_8_itm_1 <= 1'b0;
+      ACC1_2_slc_acc_idiv_106_itm_1 <= 1'b0;
+      ACC1_acc_264_itm_1 <= 10'b0;
+      ACC1_mul_90_itm_1 <= 12'b0;
+      ACC1_mul_91_itm_1 <= 14'b0;
+      ACC1_mul_104_itm_1 <= 10'b0;
+      ACC1_slc_acc_idiv_2_90_itm_1 <= 1'b0;
+      ACC1_3_slc_acc_idiv_132_itm_1 <= 1'b0;
+      ACC1_mul_103_itm_1 <= 8'b0;
+      ACC1_slc_acc_idiv_91_itm_1 <= 1'b0;
+      ACC1_3_slc_acc_idiv_131_itm_1 <= 1'b0;
+      ACC1_mul_98_itm_1 <= 6'b0;
+      ACC1_slc_acc_idiv_3_36_itm_1 <= 1'b0;
+      ACC1_2_slc_acc_idiv_132_itm_1 <= 1'b0;
+      ACC1_acc_252_itm_1 <= 6'b0;
+      ACC1_acc_251_itm_1 <= 6'b0;
+      ACC1_acc_255_itm_1 <= 7'b0;
+      ACC1_mul_89_itm_1 <= 10'b0;
+      ACC1_acc_268_itm_1 <= 12'b0;
+      ACC1_mul_96_itm_1 <= 14'b0;
+      ACC1_slc_acc_imod_28_itm_1 <= 1'b0;
+      regs_regs_slc_regs_regs_2_sg2_1_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_sg2_2_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_sg2_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_6_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_7_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_itm <= 10'b0;
+      regs_regs_1_sg2_sva <= 30'b0;
+      regs_regs_1_1_sva <= 30'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({vout_rsc_mgc_out_stdreg_d , ({((FRAME_acc_5_psp_sva[9:0])
+            | ({8'b0 , (FRAME_acc_5_psp_sva[11:10])})) , (FRAME_acc_5_psp_sva[9:6])
+            , ((FRAME_acc_5_psp_sva[5:0]) | ({4'b0 , (FRAME_acc_5_psp_sva[11:10])}))
+            , (FRAME_acc_5_psp_sva[9:0])})}, main_stage_0_3);
+        intensity_slc_intensity_2_sg1_9_itm_1 <= ACC1_acc_itm[14:13];
+        intensity_slc_intensity_2_sg1_11_itm_1 <= ACC1_acc_itm[12:10];
+        intensity_slc_intensity_2_sg1_itm_1 <= ACC1_acc_itm[9:4];
+        intensity_slc_intensity_2_sg1_12_itm_1 <= ACC1_acc_itm[15];
+        FRAME_acc_12_itm_1 <= nl_FRAME_acc_12_itm_1[5:0];
+        main_stage_0_2 <= 1'b1;
+        main_stage_0_3 <= main_stage_0_2;
+        ACC1_acc_281_itm_1 <= nl_ACC1_acc_281_itm_1[15:0];
+        mul_1_itm_1 <= nl_mul_1_itm_1[12:0];
+        ACC1_2_slc_acc_idiv_131_itm_1 <= acc_idiv_3_sva[13];
+        ACC1_mul_99_itm_1 <= nl_ACC1_mul_99_itm_1[7:0];
+        ACC1_slc_acc_imod_17_8_itm_1 <= ACC1_acc_162_itm[4];
+        ACC1_2_slc_acc_idiv_106_itm_1 <= acc_idiv_3_sva[17];
+        ACC1_acc_264_itm_1 <= nl_ACC1_acc_264_itm_1[9:0];
+        ACC1_mul_90_itm_1 <= nl_ACC1_mul_90_itm_1[11:0];
+        ACC1_mul_91_itm_1 <= nl_ACC1_mul_91_itm_1[13:0];
+        ACC1_mul_104_itm_1 <= nl_ACC1_mul_104_itm_1[9:0];
+        ACC1_slc_acc_idiv_2_90_itm_1 <= acc_idiv_2_sva[5];
+        ACC1_3_slc_acc_idiv_132_itm_1 <= acc_idiv_sva[15];
+        ACC1_mul_103_itm_1 <= nl_ACC1_mul_103_itm_1[7:0];
+        ACC1_slc_acc_idiv_91_itm_1 <= acc_idiv_sva[7];
+        ACC1_3_slc_acc_idiv_131_itm_1 <= acc_idiv_sva[13];
+        ACC1_mul_98_itm_1 <= nl_ACC1_mul_98_itm_1[5:0];
+        ACC1_slc_acc_idiv_3_36_itm_1 <= acc_idiv_3_sva[3];
+        ACC1_2_slc_acc_idiv_132_itm_1 <= acc_idiv_3_sva[15];
+        ACC1_acc_252_itm_1 <= nl_ACC1_acc_252_itm_1[5:0];
+        ACC1_acc_251_itm_1 <= nl_ACC1_acc_251_itm_1[5:0];
+        ACC1_acc_255_itm_1 <= nl_ACC1_acc_255_itm_1[6:0];
+        ACC1_mul_89_itm_1 <= nl_ACC1_mul_89_itm_1[9:0];
+        ACC1_acc_268_itm_1 <= nl_ACC1_acc_268_itm_1[11:0];
+        ACC1_mul_96_itm_1 <= nl_ACC1_mul_96_itm_1[13:0];
+        ACC1_slc_acc_imod_28_itm_1 <= ACC1_acc_189_itm[4];
+        regs_regs_slc_regs_regs_2_sg2_1_itm <= regs_regs_1_sg2_sva[19:10];
+        regs_regs_slc_regs_regs_2_sg2_2_itm <= regs_regs_1_sg2_sva[9:0];
+        regs_regs_slc_regs_regs_2_sg2_itm <= regs_regs_1_sg2_sva[29:20];
+        regs_regs_slc_regs_regs_2_6_itm <= regs_regs_1_1_sva[19:10];
+        regs_regs_slc_regs_regs_2_7_itm <= regs_regs_1_1_sva[9:0];
+        regs_regs_slc_regs_regs_2_itm <= regs_regs_1_1_sva[29:20];
+        regs_regs_1_sg2_sva <= vin_rsc_mgc_in_wire_d[89:60];
+        regs_regs_1_1_sva <= vin_rsc_mgc_in_wire_d[29:0];
+      end
+    end
+  end
+  assign nl_FRAME_acc_12_itm_1  = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~ (ACC1_acc_itm[15]))
+      , 1'b1 , (~ (ACC1_acc_itm[15]))}) + conv_u2u_2_4(ACC1_acc_itm[14:13]))) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_itm[3:1])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[6:4])));
+  assign nl_ACC1_acc_281_itm_1  = ((conv_u2u_15_16({conv_u2u_24_12(conv_u2u_2_12(conv_u2u_1_2(acc_idiv_sva[15])
+      + conv_u2u_1_2(acc_idiv_2_sva[15])) * 12'b10101010101) , (ACC1_acc_174_itm[4])
+      , (signext_2_1(acc_idiv_sva[17]))}) + conv_u2u_14_16(conv_u2u_13_14({conv_u2u_24_12(conv_u2u_2_12(conv_u2u_1_2(acc_idiv_3_sva[12])
+      + conv_u2u_1_2(acc_idiv_7_sva[12])) * 12'b10101010101) , (ACC1_acc_189_itm[3])})
+      + conv_u2u_13_14({conv_u2u_20_10(conv_u2u_2_10(conv_u2u_1_2(acc_idiv_sva[13])
+      + conv_u2u_1_2(acc_idiv_2_sva[13])) * 10'b101010101) , (acc_idiv_7_sva[3])
+      , (signext_2_1(acc_idiv_3_sva[5]))}))) + ({conv_u2u_30_15(conv_u2s_2_15(conv_u2u_1_2(acc_idiv_3_sva[16])
+      + conv_u2u_1_2(acc_idiv_7_sva[16])) * 15'b101010101010101) , (acc_imod_1_sva[1])}))
+      + (({conv_u2u_24_12(conv_u2u_3_12(conv_u2u_2_3((conv_u2u_1_2(acc_idiv_3_sva[15])
+      + conv_u2u_1_2(acc_idiv_7_sva[15])) + conv_u2u_1_2(acc_idiv_7_sva[17])) + conv_u2u_1_3(acc_idiv_3_sva[17]))
+      * 12'b10101010101) , (acc_idiv_2_sva[7]) , 1'b0 , (signext_2_1(acc_idiv_3_sva[7]))})
+      + conv_u2u_32_16(conv_u2u_2_16(conv_u2u_1_2(acc_idiv_sva[16]) + conv_u2u_1_2(acc_idiv_2_sva[16]))
+      * 16'b101010101010101));
+  assign nl_mul_1_itm_1  = conv_u2s_2_13(conv_u2u_1_2(acc_idiv_sva[17]) + conv_u2u_1_2(acc_idiv_2_sva[17]))
+      * 13'b1010101010101;
+  assign nl_ACC1_mul_99_itm_1  = conv_u2u_2_8(conv_u2u_1_2(acc_idiv_sva[11]) + conv_u2u_1_2(acc_idiv_2_sva[11]))
+      * 8'b1010101;
+  assign nl_ACC1_acc_264_itm_1  = conv_s2s_9_10(conv_s2s_7_9(({5'b10101 , (signext_2_1(acc_idiv_sva[9]))})
+      + ({conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(acc_idiv_3_sva[6]) + conv_u2u_1_2(acc_idiv_7_sva[6]))
+      * 6'b10101) , (acc_idiv_2_sva[3])})) + conv_u2s_7_9(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[13]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[15]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[17])))) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[5]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[7]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[9]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[11]))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[13]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[15]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[5]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[7])))) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[9]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[11]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[13]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[15])))))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[7]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[9]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[13])))) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[15]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[17]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[5]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[17]))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3({(acc_idiv_sva[3])
+      , (acc_idiv_sva[1])}) + conv_u2u_2_3({(acc_idiv_2_sva[3]) , (acc_idiv_sva[2])}))
+      + conv_u2u_3_4(conv_u2u_2_3({(acc_idiv_3_sva[1]) , (acc_idiv_sva[3])}) + conv_u2u_2_3({(acc_idiv_3_sva[2])
+      , (acc_idiv_sva[4])}))) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3({(acc_idiv_3_sva[3])
+      , (acc_idiv_2_sva[1])}) + conv_u2u_2_3({(acc_idiv_3_sva[4]) , (acc_idiv_2_sva[2])}))
+      + conv_u2u_3_4(conv_u2u_2_3({(ACC1_acc_189_itm[4]) , (ACC1_acc_201_itm[2])})
+      + conv_u2u_2_3({(ACC1_acc_162_itm[2]) , (ACC1_acc_201_itm[3])}))))))) + conv_u2s_9_10({conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(acc_idiv_3_sva[8])
+      + conv_u2u_1_2(acc_idiv_7_sva[8])) * 8'b1010101) , (acc_idiv_2_sva[4])});
+  assign nl_ACC1_mul_90_itm_1  = conv_u2u_2_12(conv_u2u_1_2(acc_idiv_sva[12]) + conv_u2u_1_2(acc_idiv_2_sva[12]))
+      * 12'b10101010101;
+  assign nl_ACC1_mul_91_itm_1  = conv_u2u_2_14(conv_u2u_1_2(acc_idiv_sva[14]) + conv_u2u_1_2(acc_idiv_2_sva[14]))
+      * 14'b1010101010101;
+  assign nl_ACC1_mul_104_itm_1  = conv_u2u_2_10(conv_u2u_1_2(acc_idiv_3_sva[13])
+      + conv_u2u_1_2(acc_idiv_7_sva[13])) * 10'b101010101;
+  assign nl_ACC1_mul_103_itm_1  = conv_u2u_2_8(conv_u2u_1_2(acc_idiv_3_sva[11]) +
+      conv_u2u_1_2(acc_idiv_7_sva[11])) * 8'b1010101;
+  assign nl_ACC1_mul_98_itm_1  = conv_u2u_2_6(conv_u2u_1_2(acc_idiv_sva[9]) + conv_u2u_1_2(acc_idiv_2_sva[9]))
+      * 6'b10101;
+  assign nl_ACC1_acc_252_itm_1  = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3({(ACC1_acc_162_itm[3])
+      , (ACC1_acc_201_itm[4])}) + conv_u2u_2_3({(ACC1_acc_162_itm[4]) , (acc_imod_7_sva[1])}))
+      + conv_u2u_3_4({(conv_u2u_1_2(acc_imod_19_sva[1]) + conv_u2u_1_2(~ (acc_imod_19_sva[2])))
+      , (~ (readslicef_3_1_2((({1'b1 , (acc_imod_7_sva[0]) , 1'b1}) + conv_u2s_2_3({(~
+      (acc_imod_7_sva[1])) , (~ (acc_imod_7_sva[2]))})))))})) + conv_u2u_4_5({(conv_u2u_2_3(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(acc_idiv_7_sva[3]) , (acc_idiv_7_sva[4])})))) + conv_u2u_1_3(acc_idiv_7_sva[1]))
+      , 1'b1})) + conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_201_itm[4])
+      , 1'b1}) + conv_u2u_2_3({(ACC1_acc_174_itm[2]) , (ACC1_acc_174_itm[3])}))))
+      , 1'b1}) + conv_u2u_4_5({(ACC1_acc_230_sdt[3:1]) , (ACC1_acc_174_itm[4])}))))
+      , (ACC1_acc_230_sdt[0])});
+  assign nl_ACC1_acc_251_itm_1  = conv_u2u_5_6(conv_u2u_4_5({(~ (ACC1_acc_162_itm[5]))
+      , (~ (ACC1_acc_189_itm[5])) , (~ (readslicef_3_1_2((({1'b1 , (acc_imod_19_sva[0])
+      , 1'b1}) + conv_u2s_2_3({(~ (acc_imod_19_sva[1])) , (~ (acc_imod_19_sva[2]))})))))
+      , (~ (ACC1_acc_201_itm[5]))}) + conv_u2u_4_5({(~ (ACC1_acc_174_itm[5])) , (~
+      (ACC1_acc_201_itm[5])) , (~ (ACC1_acc_162_itm[5])) , (~ (acc_imod_7_sva[2]))}))
+      + conv_u2u_5_6({(acc_idiv_7_sva[5]) , (acc_idiv_3_sva[4]) , 1'b0 , (signext_2_1(acc_idiv_3_sva[9]))});
+  assign nl_ACC1_acc_255_itm_1  = conv_u2u_6_7(conv_u2u_5_6({(acc_idiv_7_sva[7])
+      , (acc_idiv_7_sva[4]) , 1'b0 , (signext_2_1(acc_idiv_3_sva[11]))}) + conv_u2u_4_6(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[17]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[5]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[7]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[9]))))) + conv_u2u_6_7(conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(acc_idiv_sva[6])
+      + conv_u2u_1_2(acc_idiv_2_sva[6])) * 6'b10101));
+  assign nl_ACC1_mul_89_itm_1  = conv_u2u_2_10(conv_u2u_1_2(acc_idiv_sva[10]) + conv_u2u_1_2(acc_idiv_2_sva[10]))
+      * 10'b101010101;
+  assign nl_ACC1_acc_268_itm_1  = conv_u2u_11_12(conv_u2u_10_11({conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(acc_idiv_3_sva[9])
+      + conv_u2u_1_2(acc_idiv_7_sva[9])) * 6'b10101) , (acc_idiv_sva[5]) , 1'b0 ,
+      (signext_2_1(acc_idiv_sva[11]))}) + conv_u2u_9_11(conv_u2u_8_9({(conv_u2u_3_4({(acc_idiv_3_sva[7])
+      , (acc_idiv_sva[7]) , (acc_idiv_3_sva[5])}) + conv_u2u_3_4({(acc_idiv_7_sva[7])
+      , (acc_idiv_2_sva[7]) , (acc_idiv_3_sva[7])})) , (conv_u2u_3_4({(acc_idiv_sva[4])
+      , (signext_2_1(acc_idiv_sva[5]))}) + conv_u2u_3_4({(acc_idiv_2_sva[4]) , (signext_2_1(acc_idiv_sva[7]))}))})
+      + conv_u2u_8_9(conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(acc_idiv_sva[8]) + conv_u2u_1_2(acc_idiv_2_sva[8]))
+      * 8'b1010101)))) + conv_u2u_11_12({conv_u2u_20_10(conv_u2u_2_10(conv_u2u_1_2(acc_idiv_3_sva[10])
+      + conv_u2u_1_2(acc_idiv_7_sva[10])) * 10'b101010101) , (ACC1_acc_189_itm[2])});
+  assign nl_ACC1_mul_96_itm_1  = conv_u2u_2_14(conv_u2u_1_2(acc_idiv_3_sva[14]) +
+      conv_u2u_1_2(acc_idiv_7_sva[14])) * 14'b1010101010101;
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [4:0] readslicef_6_5_1;
+    input [5:0] vector;
+    reg [5:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_6_5_1 = tmp[4:0];
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [15:0] signext_16_10;
+    input [9:0] vector;
+  begin
+    signext_16_10= {{6{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [15:0] signext_16_11;
+    input [10:0] vector;
+  begin
+    signext_16_11= {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_3_1_2;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 2;
+    readslicef_3_1_2 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_15_16 ;
+    input signed [14:0]  vector ;
+  begin
+    conv_s2s_15_16 = {vector[14], vector};
+  end
+  endfunction
+
+
+  function signed [14:0] conv_s2s_14_15 ;
+    input signed [13:0]  vector ;
+  begin
+    conv_s2s_14_15 = {vector[13], vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_12_14 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_14 = {{2{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [14:0] conv_u2s_14_15 ;
+    input [13:0]  vector ;
+  begin
+    conv_u2s_14_15 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_u2u_15_16 ;
+    input [14:0]  vector ;
+  begin
+    conv_u2u_15_16 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_u2u_14_15 ;
+    input [13:0]  vector ;
+  begin
+    conv_u2u_14_15 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_u2u_13_15 ;
+    input [12:0]  vector ;
+  begin
+    conv_u2u_13_15 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [17:0] conv_u2u_17_18 ;
+    input [16:0]  vector ;
+  begin
+    conv_u2u_17_18 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [16:0] conv_u2u_16_17 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_17 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [17:0] conv_u2u_16_18 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_18 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_24_12 ;
+    input [23:0]  vector ;
+  begin
+    conv_u2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_2_12 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_12 = {{10{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_u2u_14_16 ;
+    input [13:0]  vector ;
+  begin
+    conv_u2u_14_16 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_13_14 ;
+    input [12:0]  vector ;
+  begin
+    conv_u2u_13_14 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_u2u_30_15 ;
+    input [29:0]  vector ;
+  begin
+    conv_u2u_30_15 = vector[14:0];
+  end
+  endfunction
+
+
+  function signed [14:0] conv_u2s_2_15 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_15 = {{13{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_3_12 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_12 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_u2u_32_16 ;
+    input [31:0]  vector ;
+  begin
+    conv_u2u_32_16 = vector[15:0];
+  end
+  endfunction
+
+
+  function  [15:0] conv_u2u_2_16 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_16 = {{14{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_2_8 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_8 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_9_10 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_10 = {vector[8], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_12_6 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_6 = vector[5:0];
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_2_6 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_6 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_2_14 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_14 = {{12{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v6/cycle.rpt b/Sobel/sobel.v6/cycle.rpt
new file mode 100644
index 0000000..e043083
--- /dev/null
+++ b/Sobel/sobel.v6/cycle.rpt
@@ -0,0 +1,85 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 14:53:30 +0000 2016                      
+
+Solution Settings: sobel.v6
+  Current state: schedule
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       298  307202     307200            0  1          
+    Design Total:                     298  307202     307200            0  0          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /sobel/core              
+    
+  I/O Data Ranges
+    Port       Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ---------- ---- -------- --------- --------- ------- -------- --------
+    vin:rsc.z  IN   Unsigned        90                                     
+    clk        IN   Unsigned         1                                     
+    en         IN   Unsigned         1                                     
+    arst_n     IN   Unsigned         1                                     
+    vout:rsc.z OUT  Unsigned        30                                     
+    
+  Memory Resources
+    Resource Name: /sobel/vin:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 90
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable   Indices Phys Memory Address     
+      ---------- ------- -----------------------
+      /sobel/vin    0:89 00000000-00000000 (0-0) 
+      
+    Resource Name: /sobel/vout:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 30
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable    Indices Phys Memory Address     
+      ----------- ------- -----------------------
+      /sobel/vout    0:29 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process     Loop             Iterations C-Steps Total Cycles  Duration  Unroll Init Comments 
+    ----------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
+    /sobel/core core:rlp           Infinite       0       307203   6.14 ms                       
+    /sobel/core   main             Infinite       4       307203   6.14 ms            1          
+    
+  Loop Execution Profile
+    Process     Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------- ---------------- ------------ -------------------------- ----------------- --------
+    /sobel/core core:rlp                   0                        0.00           307200           
+    /sobel/core   main                307203                      100.00           307200           
+    
+  End of Report
diff --git a/Sobel/sobel.v6/cycle.v b/Sobel/sobel.v6/cycle.v
new file mode 100644
index 0000000..b7babfa
--- /dev/null
+++ b/Sobel/sobel.v6/cycle.v
@@ -0,0 +1,1150 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:53:31 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg [29:0] regs_regs_1_1_sva;
+    reg [29:0] regs_regs_1_sg2_sva;
+    reg [89:0] regs_regs_0_sva_1;
+    reg [17:0] acc_idiv_3_sva;
+    reg [4:0] acc_imod_17_sva;
+    reg [2:0] acc_imod_19_sva;
+    reg [17:0] acc_idiv_7_sva;
+    reg [4:0] acc_imod_25_sva;
+    reg [2:0] acc_imod_27_sva;
+    reg [17:0] acc_idiv_sva;
+    reg [4:0] acc_imod_sva;
+    reg [2:0] acc_imod_1_sva;
+    reg [17:0] acc_idiv_2_sva;
+    reg [4:0] acc_imod_6_sva;
+    reg [2:0] acc_imod_7_sva;
+    reg [14:0] intensity_2_sg1_sva;
+    reg [5:0] acc_imod_15_sva;
+    reg [11:0] FRAME_acc_5_psp_sva;
+    reg [9:0] regs_regs_slc_regs_regs_2_6_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_7_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_sg2_1_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_sg2_2_itm;
+    reg [9:0] regs_regs_slc_regs_regs_2_sg2_itm;
+    reg [15:0] ACC1_acc_281_itm_1;
+    reg [12:0] mul_1_itm_1;
+    reg ACC1_2_slc_acc_idiv_131_itm_1;
+    reg [7:0] ACC1_mul_99_itm_1;
+    reg ACC1_slc_acc_imod_17_8_itm_1;
+    reg ACC1_2_slc_acc_idiv_106_itm_1;
+    reg [9:0] ACC1_acc_264_itm_1;
+    reg [11:0] ACC1_mul_90_itm_1;
+    reg [13:0] ACC1_mul_91_itm_1;
+    reg [9:0] ACC1_mul_104_itm_1;
+    reg ACC1_slc_acc_idiv_2_90_itm_1;
+    reg ACC1_3_slc_acc_idiv_132_itm_1;
+    reg [7:0] ACC1_mul_103_itm_1;
+    reg ACC1_slc_acc_idiv_91_itm_1;
+    reg ACC1_3_slc_acc_idiv_131_itm_1;
+    reg [5:0] ACC1_mul_98_itm_1;
+    reg ACC1_slc_acc_idiv_3_36_itm_1;
+    reg ACC1_2_slc_acc_idiv_132_itm_1;
+    reg [5:0] ACC1_acc_252_itm_1;
+    reg [5:0] ACC1_acc_251_itm_1;
+    reg [6:0] ACC1_acc_255_itm_1;
+    reg [9:0] ACC1_mul_89_itm_1;
+    reg [11:0] ACC1_acc_268_itm_1;
+    reg [13:0] ACC1_mul_96_itm_1;
+    reg ACC1_slc_acc_imod_28_itm_1;
+    reg [5:0] FRAME_acc_12_itm;
+    reg [5:0] FRAME_acc_12_itm_1;
+    reg [1:0] intensity_slc_intensity_2_sg1_9_itm;
+    reg [1:0] intensity_slc_intensity_2_sg1_9_itm_1;
+    reg [2:0] intensity_slc_intensity_2_sg1_11_itm;
+    reg [2:0] intensity_slc_intensity_2_sg1_11_itm_1;
+    reg [5:0] intensity_slc_intensity_2_sg1_itm;
+    reg [5:0] intensity_slc_intensity_2_sg1_itm_1;
+    reg [2:0] intensity_slc_intensity_2_sg1_10_itm;
+    reg [2:0] intensity_slc_intensity_2_sg1_10_itm_1;
+    reg intensity_slc_intensity_2_sg1_12_itm;
+    reg intensity_slc_intensity_2_sg1_12_itm_1;
+    reg intensity_slc_intensity_2_sg1_13_itm;
+    reg intensity_slc_intensity_2_sg1_13_itm_1;
+    reg intensity_slc_intensity_2_sg1_8_itm;
+    reg intensity_slc_intensity_2_sg1_8_itm_1;
+    reg main_stage_0_2;
+    reg main_stage_0_3;
+    reg [29:0] regs_regs_0_sva_sg2;
+    reg [29:0] regs_regs_0_sva_2;
+    reg [3:0] ACC1_acc_230_sdt;
+
+    begin : core_rlpExit
+      forever begin : core_rlp
+        // C-Step 0 of Loop 'core_rlp'
+        regs_regs_1_1_sva = 30'b0;
+        regs_regs_1_sg2_sva = 30'b0;
+        regs_regs_0_sva_2 = 30'b0;
+        regs_regs_0_sva_sg2 = 30'b0;
+        main_stage_0_2 = 1'b0;
+        main_stage_0_3 = 1'b0;
+        begin : mainExit
+          forever begin : main
+            // C-Step 0 of Loop 'main'
+            regs_regs_slc_regs_regs_2_6_itm = regs_regs_1_1_sva[19:10];
+            regs_regs_slc_regs_regs_2_7_itm = regs_regs_1_1_sva[9:0];
+            regs_regs_slc_regs_regs_2_itm = regs_regs_1_1_sva[29:20];
+            regs_regs_slc_regs_regs_2_sg2_1_itm = regs_regs_1_sg2_sva[19:10];
+            regs_regs_slc_regs_regs_2_sg2_2_itm = regs_regs_1_sg2_sva[9:0];
+            regs_regs_slc_regs_regs_2_sg2_itm = regs_regs_1_sg2_sva[29:20];
+            regs_regs_1_sg2_sva = regs_regs_0_sva_sg2;
+            regs_regs_1_1_sva = regs_regs_0_sva_2;
+            begin : waitLoop0Exit
+              forever begin : waitLoop0
+                @(posedge clk or negedge ( arst_n ));
+                if ( ~ arst_n )
+                  disable core_rlpExit;
+                if ( en )
+                  disable waitLoop0Exit;
+              end
+            end
+            // C-Step 1 of Loop 'main'
+            if ( main_stage_0_3 ) begin
+              acc_imod_15_sva = FRAME_acc_12_itm_1 + 6'b101011;
+              FRAME_acc_5_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(intensity_slc_intensity_2_sg1_9_itm_1)
+                  * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(intensity_slc_intensity_2_sg1_11_itm_1)
+                  * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(intensity_slc_intensity_2_sg1_itm_1)
+                  + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_15_sva[5]))
+                  , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_15_sva[2:0])
+                  , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_15_sva[5:3])) , (~ (acc_imod_15_sva[5]))})))))})
+                  + conv_u2u_2_4(acc_imod_15_sva[4:3])) + conv_u2u_3_5(~ intensity_slc_intensity_2_sg1_10_itm_1))
+                  + ({4'b1001 , (acc_imod_15_sva[5])}))))) + conv_u2u_11_12(signext_11_9({intensity_slc_intensity_2_sg1_12_itm_1
+                  , 3'b0 , ({{2{intensity_slc_intensity_2_sg1_13_itm_1}}, intensity_slc_intensity_2_sg1_13_itm_1})
+                  , 1'b0 , intensity_slc_intensity_2_sg1_8_itm_1}));
+              vout_rsc_mgc_out_stdreg_d <= {((FRAME_acc_5_psp_sva[9:0]) | ({8'b0,
+                  FRAME_acc_5_psp_sva[11:10]})) , (FRAME_acc_5_psp_sva[9:6]) , ((FRAME_acc_5_psp_sva[5:0])
+                  | ({4'b0, FRAME_acc_5_psp_sva[11:10]})) , (FRAME_acc_5_psp_sva[9:0])};
+            end
+            if ( main_stage_0_2 ) begin
+              intensity_2_sg1_sva = readslicef_16_15_1((ACC1_acc_281_itm_1 + ((({mul_1_itm_1
+                  , 1'b0 , ({{1{ACC1_2_slc_acc_idiv_131_itm_1}}, ACC1_2_slc_acc_idiv_131_itm_1})})
+                  + conv_s2s_15_16(conv_s2s_14_15(conv_s2s_12_14(conv_u2s_11_12({ACC1_mul_99_itm_1
+                  , ACC1_slc_acc_imod_17_8_itm_1 , ({{1{ACC1_2_slc_acc_idiv_106_itm_1}},
+                  ACC1_2_slc_acc_idiv_106_itm_1})}) + conv_s2s_10_12(ACC1_acc_264_itm_1))
+                  + conv_u2s_12_14(ACC1_mul_90_itm_1)) + conv_u2s_14_15(ACC1_mul_91_itm_1)))
+                  + (conv_u2u_15_16(conv_u2u_14_15({ACC1_mul_104_itm_1 , ACC1_slc_acc_idiv_2_90_itm_1
+                  , 1'b0 , ({{1{ACC1_3_slc_acc_idiv_132_itm_1}}, ACC1_3_slc_acc_idiv_132_itm_1})})
+                  + conv_u2u_13_15(conv_u2u_12_13(({ACC1_mul_103_itm_1 , ACC1_slc_acc_idiv_91_itm_1
+                  , 1'b0 , ({{1{ACC1_3_slc_acc_idiv_131_itm_1}}, ACC1_3_slc_acc_idiv_131_itm_1})})
+                  + conv_u2u_11_12(conv_u2u_10_11(conv_u2u_9_10({ACC1_mul_98_itm_1
+                  , ACC1_slc_acc_idiv_3_36_itm_1 , ({{1{ACC1_2_slc_acc_idiv_132_itm_1}},
+                  ACC1_2_slc_acc_idiv_132_itm_1})}) + conv_u2u_8_10(conv_u2u_7_8(conv_u2u_6_7(ACC1_acc_252_itm_1)
+                  + conv_u2u_6_7(ACC1_acc_251_itm_1)) + conv_u2u_7_8(ACC1_acc_255_itm_1)))
+                  + conv_u2u_10_11(ACC1_mul_89_itm_1))) + conv_u2u_12_13(ACC1_acc_268_itm_1)))
+                  + conv_u2u_15_16({ACC1_mul_96_itm_1 , ACC1_slc_acc_imod_28_itm_1})))));
+              FRAME_acc_12_itm = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(intensity_2_sg1_sva[8:6])
+                  + conv_u2u_3_4(~ (intensity_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                  (intensity_2_sg1_sva[14])) , 1'b1 , (~ (intensity_2_sg1_sva[14]))})
+                  + conv_u2u_2_4(intensity_2_sg1_sva[13:12]))) + conv_u2u_4_6(conv_u2u_3_4(intensity_2_sg1_sva[2:0])
+                  + conv_u2u_3_4(~ (intensity_2_sg1_sva[5:3])));
+              intensity_slc_intensity_2_sg1_9_itm = intensity_2_sg1_sva[13:12];
+              intensity_slc_intensity_2_sg1_11_itm = intensity_2_sg1_sva[11:9];
+              intensity_slc_intensity_2_sg1_itm = intensity_2_sg1_sva[8:3];
+              intensity_slc_intensity_2_sg1_10_itm = intensity_2_sg1_sva[8:6];
+              intensity_slc_intensity_2_sg1_12_itm = intensity_2_sg1_sva[14];
+              intensity_slc_intensity_2_sg1_13_itm = intensity_2_sg1_sva[14];
+              intensity_slc_intensity_2_sg1_8_itm = intensity_2_sg1_sva[14];
+            end
+            regs_regs_0_sva_1 = vin_rsc_mgc_in_wire_d;
+            acc_idiv_3_sva = conv_u2u_17_18(conv_u2u_16_17(signext_16_10(regs_regs_0_sva_1[19:10]))
+                + conv_u2u_16_17(signext_16_10(regs_regs_0_sva_1[9:0]))) + conv_u2u_16_18(signext_16_10(regs_regs_0_sva_1[29:20]));
+            acc_imod_17_sva = readslicef_6_5_1((({(readslicef_6_5_1((conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_3_sva[8])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_3_sva[9])) , 1'b1})))) , 1'b1})
+                + conv_u2u_2_4({(~ (acc_idiv_3_sva[1])) , (~ (acc_idiv_3_sva[13]))}))))
+                , 1'b1}) + conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_3_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_3_sva[3])) , (acc_idiv_3_sva[12])}))))
+                , (~ (acc_idiv_3_sva[15]))})))) , 1'b1}) + conv_u2u_4_6({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_3_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_3_sva[5])) , (~ (acc_idiv_3_sva[11]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_3_sva[6])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_3_sva[7])) , (acc_idiv_3_sva[10])}))))
+                , (acc_idiv_3_sva[14])})))) , (acc_idiv_3_sva[16])})))) , 1'b1})
+                + ({4'b1011 , (acc_idiv_3_sva[0]) , (~ (acc_idiv_3_sva[17]))})));
+            acc_imod_19_sva = (readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_imod_17_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_imod_17_sva[3])) , 1'b1})))) , 1'b1})
+                + conv_u2u_2_4({(~ (acc_imod_17_sva[1])) , (~ (acc_imod_17_sva[4]))}))))
+                + ({2'b10 , (acc_imod_17_sva[0])});
+            acc_idiv_7_sva = conv_u2u_17_18(conv_u2u_16_17(signext_16_10(regs_regs_0_sva_1[79:70]))
+                + conv_u2u_16_17(signext_16_10(regs_regs_0_sva_1[69:60]))) + conv_u2u_16_18(signext_16_10(regs_regs_0_sva_1[89:80]));
+            acc_imod_25_sva = readslicef_6_5_1((({(readslicef_6_5_1((conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[8])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_7_sva[9])) , 1'b1})))) , 1'b1})
+                + conv_u2u_2_4({(~ (acc_idiv_7_sva[1])) , (~ (acc_idiv_7_sva[13]))}))))
+                , 1'b1}) + conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_7_sva[3])) , (acc_idiv_7_sva[12])}))))
+                , (~ (acc_idiv_7_sva[15]))})))) , 1'b1}) + conv_u2u_4_6({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_7_sva[5])) , (~ (acc_idiv_7_sva[11]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[6])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_7_sva[7])) , (acc_idiv_7_sva[10])}))))
+                , (acc_idiv_7_sva[14])})))) , (acc_idiv_7_sva[16])})))) , 1'b1})
+                + ({4'b1011 , (acc_idiv_7_sva[0]) , (~ (acc_idiv_7_sva[17]))})));
+            acc_imod_27_sva = (readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_imod_25_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_imod_25_sva[3])) , 1'b1})))) , 1'b1})
+                + conv_u2u_2_4({(~ (acc_imod_25_sva[1])) , (~ (acc_imod_25_sva[4]))}))))
+                + ({2'b10 , (acc_imod_25_sva[0])});
+            acc_idiv_sva = conv_u2u_17_18(conv_u2u_16_17(signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+                regs_regs_slc_regs_regs_2_6_itm) , 1'b1}) + conv_s2s_11_12({(regs_regs_0_sva_1[19:10])
+                , 1'b1}))))) + conv_u2u_16_17(signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+                regs_regs_slc_regs_regs_2_7_itm) , 1'b1}) + conv_s2s_11_12({(regs_regs_0_sva_1[9:0])
+                , 1'b1})))))) + conv_u2u_16_18(signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+                regs_regs_slc_regs_regs_2_itm) , 1'b1}) + conv_s2s_11_12({(regs_regs_0_sva_1[29:20])
+                , 1'b1})))));
+            acc_imod_sva = readslicef_6_5_1((({(readslicef_6_5_1((conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_sva[8])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_sva[9])) , 1'b1})))) , 1'b1})
+                + conv_u2u_2_4({(~ (acc_idiv_sva[1])) , (~ (acc_idiv_sva[13]))}))))
+                , 1'b1}) + conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_sva[3])) , (acc_idiv_sva[12])}))))
+                , (~ (acc_idiv_sva[15]))})))) , 1'b1}) + conv_u2u_4_6({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_sva[5])) , (~ (acc_idiv_sva[11]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_sva[6])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_sva[7])) , (acc_idiv_sva[10])}))))
+                , (acc_idiv_sva[14])})))) , (acc_idiv_sva[16])})))) , 1'b1}) + ({4'b1011
+                , (acc_idiv_sva[0]) , (~ (acc_idiv_sva[17]))})));
+            acc_imod_1_sva = (readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_imod_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_imod_sva[3])) , 1'b1})))) , 1'b1})
+                + conv_u2u_2_4({(~ (acc_imod_sva[1])) , (~ (acc_imod_sva[4]))}))))
+                + ({2'b10 , (acc_imod_sva[0])});
+            acc_idiv_2_sva = conv_u2u_17_18(conv_u2u_16_17(signext_16_11(conv_s2s_10_11(regs_regs_0_sva_1[79:70])
+                + conv_s2s_10_11(regs_regs_slc_regs_regs_2_sg2_1_itm))) + conv_u2u_16_17(signext_16_11(conv_s2s_10_11(regs_regs_0_sva_1[69:60])
+                + conv_s2s_10_11(regs_regs_slc_regs_regs_2_sg2_2_itm)))) + conv_u2u_16_18(signext_16_11(conv_s2s_10_11(regs_regs_0_sva_1[89:80])
+                + conv_s2s_10_11(regs_regs_slc_regs_regs_2_sg2_itm)));
+            acc_imod_6_sva = readslicef_6_5_1((({(readslicef_6_5_1((conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_2_sva[8])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_2_sva[9])) , 1'b1})))) , 1'b1})
+                + conv_u2u_2_4({(~ (acc_idiv_2_sva[1])) , (~ (acc_idiv_2_sva[13]))}))))
+                , 1'b1}) + conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_2_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_2_sva[3])) , (acc_idiv_2_sva[12])}))))
+                , (~ (acc_idiv_2_sva[15]))})))) , 1'b1}) + conv_u2u_4_6({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_2_sva[4])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_2_sva[5])) , (~ (acc_idiv_2_sva[11]))}))))
+                , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_2_sva[6])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_2_sva[7])) , (acc_idiv_2_sva[10])}))))
+                , (acc_idiv_2_sva[14])})))) , (acc_idiv_2_sva[16])})))) , 1'b1})
+                + ({4'b1011 , (acc_idiv_2_sva[0]) , (~ (acc_idiv_2_sva[17]))})));
+            acc_imod_7_sva = (readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_imod_6_sva[2])
+                , 1'b1}) + conv_u2u_2_3({(~ (acc_imod_6_sva[3])) , 1'b1})))) , 1'b1})
+                + conv_u2u_2_4({(~ (acc_imod_6_sva[1])) , (~ (acc_imod_6_sva[4]))}))))
+                + ({2'b10 , (acc_imod_6_sva[0])});
+            ACC1_acc_230_sdt = conv_u2u_3_4(conv_u2u_2_3({(~ (acc_imod_25_sva[4]))
+                , (~ (acc_imod_sva[4]))}) + conv_u2u_2_3({(acc_imod_27_sva[1]) ,
+                1'b1})) + conv_u2u_3_4(conv_u2u_2_3({(~ (acc_imod_27_sva[2])) , (~
+                (acc_imod_1_sva[2]))}) + conv_u2u_2_3({(~ (readslicef_3_1_2((({1'b1
+                , (acc_imod_27_sva[0]) , 1'b1}) + conv_u2s_2_3({(~ (acc_imod_27_sva[1]))
+                , (~ (acc_imod_27_sva[2]))}))))) , (~ (readslicef_3_1_2((({1'b1 ,
+                (acc_imod_1_sva[0]) , 1'b1}) + conv_u2s_2_3({(~ (acc_imod_1_sva[1]))
+                , (~ (acc_imod_1_sva[2]))})))))}));
+            regs_regs_0_sva_2 = regs_regs_0_sva_1[29:0];
+            regs_regs_0_sva_sg2 = regs_regs_0_sva_1[89:60];
+            ACC1_acc_281_itm_1 = ((conv_u2u_15_16({conv_u2u_24_12(conv_u2u_2_12(conv_u2u_1_2(acc_idiv_sva[15])
+                + conv_u2u_1_2(acc_idiv_2_sva[15])) * 12'b10101010101) , (acc_imod_25_sva[3])
+                , (signext_2_1(acc_idiv_sva[17]))}) + conv_u2u_14_16(conv_u2u_13_14({conv_u2u_24_12(conv_u2u_2_12(conv_u2u_1_2(acc_idiv_3_sva[12])
+                + conv_u2u_1_2(acc_idiv_7_sva[12])) * 12'b10101010101) , (acc_imod_sva[2])})
+                + conv_u2u_13_14({conv_u2u_20_10(conv_u2u_2_10(conv_u2u_1_2(acc_idiv_sva[13])
+                + conv_u2u_1_2(acc_idiv_2_sva[13])) * 10'b101010101) , (acc_idiv_7_sva[3])
+                , (signext_2_1(acc_idiv_3_sva[5]))}))) + ({conv_u2u_30_15(conv_u2s_2_15(conv_u2u_1_2(acc_idiv_3_sva[16])
+                + conv_u2u_1_2(acc_idiv_7_sva[16])) * 15'b101010101010101) , (acc_imod_1_sva[1])}))
+                + (({conv_u2u_24_12(conv_u2u_3_12(conv_u2u_2_3((conv_u2u_1_2(acc_idiv_3_sva[15])
+                + conv_u2u_1_2(acc_idiv_7_sva[15])) + conv_u2u_1_2(acc_idiv_7_sva[17]))
+                + conv_u2u_1_3(acc_idiv_3_sva[17])) * 12'b10101010101) , (acc_idiv_2_sva[7])
+                , 1'b0 , (signext_2_1(acc_idiv_3_sva[7]))}) + conv_u2u_32_16(conv_u2u_2_16(conv_u2u_1_2(acc_idiv_sva[16])
+                + conv_u2u_1_2(acc_idiv_2_sva[16])) * 16'b101010101010101));
+            mul_1_itm_1 = conv_u2u_26_13(conv_u2s_2_13(conv_u2u_1_2(acc_idiv_sva[17])
+                + conv_u2u_1_2(acc_idiv_2_sva[17])) * 13'b1010101010101);
+            ACC1_2_slc_acc_idiv_131_itm_1 = acc_idiv_3_sva[13];
+            ACC1_mul_99_itm_1 = conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(acc_idiv_sva[11])
+                + conv_u2u_1_2(acc_idiv_2_sva[11])) * 8'b1010101);
+            ACC1_slc_acc_imod_17_8_itm_1 = acc_imod_17_sva[3];
+            ACC1_2_slc_acc_idiv_106_itm_1 = acc_idiv_3_sva[17];
+            ACC1_acc_264_itm_1 = conv_s2s_9_10(conv_s2s_7_9(({5'b10101 , (signext_2_1(acc_idiv_sva[9]))})
+                + ({conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(acc_idiv_3_sva[6]) +
+                conv_u2u_1_2(acc_idiv_7_sva[6])) * 6'b10101) , (acc_idiv_2_sva[3])}))
+                + conv_u2s_7_9(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[11]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[13]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[15]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[17])))) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[5]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[7]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[9]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[11]))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[13]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[15]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[5]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[7])))) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[9]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[11]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[13]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[15])))))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[7]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[9]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[11]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[13])))) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[15]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[17]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[5]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[17]))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3({(acc_idiv_sva[3])
+                , (acc_idiv_sva[1])}) + conv_u2u_2_3({(acc_idiv_2_sva[3]) , (acc_idiv_sva[2])}))
+                + conv_u2u_3_4(conv_u2u_2_3({(acc_idiv_3_sva[1]) , (acc_idiv_sva[3])})
+                + conv_u2u_2_3({(acc_idiv_3_sva[2]) , (acc_idiv_sva[4])}))) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3({(acc_idiv_3_sva[3])
+                , (acc_idiv_2_sva[1])}) + conv_u2u_2_3({(acc_idiv_3_sva[4]) , (acc_idiv_2_sva[2])}))
+                + conv_u2u_3_4(conv_u2u_2_3({(acc_imod_sva[3]) , (acc_imod_6_sva[1])})
+                + conv_u2u_2_3({(acc_imod_17_sva[1]) , (acc_imod_6_sva[2])})))))))
+                + conv_u2s_9_10({conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(acc_idiv_3_sva[8])
+                + conv_u2u_1_2(acc_idiv_7_sva[8])) * 8'b1010101) , (acc_idiv_2_sva[4])});
+            ACC1_mul_90_itm_1 = conv_u2u_24_12(conv_u2u_2_12(conv_u2u_1_2(acc_idiv_sva[12])
+                + conv_u2u_1_2(acc_idiv_2_sva[12])) * 12'b10101010101);
+            ACC1_mul_91_itm_1 = conv_u2u_28_14(conv_u2u_2_14(conv_u2u_1_2(acc_idiv_sva[14])
+                + conv_u2u_1_2(acc_idiv_2_sva[14])) * 14'b1010101010101);
+            ACC1_mul_104_itm_1 = conv_u2u_20_10(conv_u2u_2_10(conv_u2u_1_2(acc_idiv_3_sva[13])
+                + conv_u2u_1_2(acc_idiv_7_sva[13])) * 10'b101010101);
+            ACC1_slc_acc_idiv_2_90_itm_1 = acc_idiv_2_sva[5];
+            ACC1_3_slc_acc_idiv_132_itm_1 = acc_idiv_sva[15];
+            ACC1_mul_103_itm_1 = conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(acc_idiv_3_sva[11])
+                + conv_u2u_1_2(acc_idiv_7_sva[11])) * 8'b1010101);
+            ACC1_slc_acc_idiv_91_itm_1 = acc_idiv_sva[7];
+            ACC1_3_slc_acc_idiv_131_itm_1 = acc_idiv_sva[13];
+            ACC1_mul_98_itm_1 = conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(acc_idiv_sva[9])
+                + conv_u2u_1_2(acc_idiv_2_sva[9])) * 6'b10101);
+            ACC1_slc_acc_idiv_3_36_itm_1 = acc_idiv_3_sva[3];
+            ACC1_2_slc_acc_idiv_132_itm_1 = acc_idiv_3_sva[15];
+            ACC1_acc_252_itm_1 = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3({(acc_imod_17_sva[2])
+                , (acc_imod_6_sva[3])}) + conv_u2u_2_3({(acc_imod_17_sva[3]) , (acc_imod_7_sva[1])}))
+                + conv_u2u_3_4({(conv_u2u_1_2(acc_imod_19_sva[1]) + conv_u2u_1_2(~
+                (acc_imod_19_sva[2]))) , (~ (readslicef_3_1_2((({1'b1 , (acc_imod_7_sva[0])
+                , 1'b1}) + conv_u2s_2_3({(~ (acc_imod_7_sva[1])) , (~ (acc_imod_7_sva[2]))})))))}))
+                + conv_u2u_4_5({(conv_u2u_1_3(acc_idiv_7_sva[1]) + conv_u2u_1_3(acc_idiv_7_sva[2])
+                + conv_u2u_1_3(acc_idiv_7_sva[3]) + conv_u2u_1_3(acc_idiv_7_sva[4]))
+                , 1'b1})) + conv_u2u_5_6({(conv_u2u_1_4(acc_imod_6_sva[3]) + conv_u2u_1_4(acc_imod_25_sva[1])
+                + conv_u2u_1_4(acc_imod_25_sva[2]) + conv_u2u_1_4(acc_imod_25_sva[3])
+                + conv_u2u_3_4(ACC1_acc_230_sdt[3:1])) , (ACC1_acc_230_sdt[0])});
+            ACC1_acc_251_itm_1 = conv_u2u_5_6(conv_u2u_4_5({(~ (acc_imod_17_sva[4]))
+                , (~ (acc_imod_sva[4])) , (~ (readslicef_3_1_2((({1'b1 , (acc_imod_19_sva[0])
+                , 1'b1}) + conv_u2s_2_3({(~ (acc_imod_19_sva[1])) , (~ (acc_imod_19_sva[2]))})))))
+                , (~ (acc_imod_6_sva[4]))}) + conv_u2u_4_5({(~ (acc_imod_25_sva[4]))
+                , (~ (acc_imod_6_sva[4])) , (~ (acc_imod_17_sva[4])) , (~ (acc_imod_7_sva[2]))}))
+                + conv_u2u_5_6({(acc_idiv_7_sva[5]) , (acc_idiv_3_sva[4]) , 1'b0
+                , (signext_2_1(acc_idiv_3_sva[9]))});
+            ACC1_acc_255_itm_1 = conv_u2u_6_7(conv_u2u_5_6({(acc_idiv_7_sva[7]) ,
+                (acc_idiv_7_sva[4]) , 1'b0 , (signext_2_1(acc_idiv_3_sva[11]))})
+                + conv_u2u_4_6(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[17]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[5]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[7]))
+                + conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[9]))))) + conv_u2u_6_7(conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(acc_idiv_sva[6])
+                + conv_u2u_1_2(acc_idiv_2_sva[6])) * 6'b10101));
+            ACC1_mul_89_itm_1 = conv_u2u_20_10(conv_u2u_2_10(conv_u2u_1_2(acc_idiv_sva[10])
+                + conv_u2u_1_2(acc_idiv_2_sva[10])) * 10'b101010101);
+            ACC1_acc_268_itm_1 = conv_u2u_11_12(conv_u2u_10_11({conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(acc_idiv_3_sva[9])
+                + conv_u2u_1_2(acc_idiv_7_sva[9])) * 6'b10101) , (acc_idiv_sva[5])
+                , 1'b0 , (signext_2_1(acc_idiv_sva[11]))}) + conv_u2u_9_11(conv_u2u_8_9({(conv_u2u_3_4({(acc_idiv_3_sva[7])
+                , (acc_idiv_sva[7]) , (acc_idiv_3_sva[5])}) + conv_u2u_3_4({(acc_idiv_7_sva[7])
+                , (acc_idiv_2_sva[7]) , (acc_idiv_3_sva[7])})) , (conv_u2u_3_4({(acc_idiv_sva[4])
+                , (signext_2_1(acc_idiv_sva[5]))}) + conv_u2u_3_4({(acc_idiv_2_sva[4])
+                , (signext_2_1(acc_idiv_sva[7]))}))}) + conv_u2u_8_9(conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(acc_idiv_sva[8])
+                + conv_u2u_1_2(acc_idiv_2_sva[8])) * 8'b1010101)))) + conv_u2u_11_12({conv_u2u_20_10(conv_u2u_2_10(conv_u2u_1_2(acc_idiv_3_sva[10])
+                + conv_u2u_1_2(acc_idiv_7_sva[10])) * 10'b101010101) , (acc_imod_sva[1])});
+            ACC1_mul_96_itm_1 = conv_u2u_28_14(conv_u2u_2_14(conv_u2u_1_2(acc_idiv_3_sva[14])
+                + conv_u2u_1_2(acc_idiv_7_sva[14])) * 14'b1010101010101);
+            ACC1_slc_acc_imod_28_itm_1 = acc_imod_sva[3];
+            FRAME_acc_12_itm_1 = FRAME_acc_12_itm;
+            intensity_slc_intensity_2_sg1_9_itm_1 = intensity_slc_intensity_2_sg1_9_itm;
+            intensity_slc_intensity_2_sg1_11_itm_1 = intensity_slc_intensity_2_sg1_11_itm;
+            intensity_slc_intensity_2_sg1_itm_1 = intensity_slc_intensity_2_sg1_itm;
+            intensity_slc_intensity_2_sg1_10_itm_1 = intensity_slc_intensity_2_sg1_10_itm;
+            intensity_slc_intensity_2_sg1_12_itm_1 = intensity_slc_intensity_2_sg1_12_itm;
+            intensity_slc_intensity_2_sg1_13_itm_1 = intensity_slc_intensity_2_sg1_13_itm;
+            intensity_slc_intensity_2_sg1_8_itm_1 = intensity_slc_intensity_2_sg1_8_itm;
+            main_stage_0_3 = main_stage_0_2;
+            main_stage_0_2 = 1'b1;
+          end
+        end
+      end
+    end
+    ACC1_acc_230_sdt = 4'b0;
+    regs_regs_0_sva_2 = 30'b0;
+    regs_regs_0_sva_sg2 = 30'b0;
+    main_stage_0_3 = 1'b0;
+    main_stage_0_2 = 1'b0;
+    intensity_slc_intensity_2_sg1_8_itm_1 = 1'b0;
+    intensity_slc_intensity_2_sg1_8_itm = 1'b0;
+    intensity_slc_intensity_2_sg1_13_itm_1 = 1'b0;
+    intensity_slc_intensity_2_sg1_13_itm = 1'b0;
+    intensity_slc_intensity_2_sg1_12_itm_1 = 1'b0;
+    intensity_slc_intensity_2_sg1_12_itm = 1'b0;
+    intensity_slc_intensity_2_sg1_10_itm_1 = 3'b0;
+    intensity_slc_intensity_2_sg1_10_itm = 3'b0;
+    intensity_slc_intensity_2_sg1_itm_1 = 6'b0;
+    intensity_slc_intensity_2_sg1_itm = 6'b0;
+    intensity_slc_intensity_2_sg1_11_itm_1 = 3'b0;
+    intensity_slc_intensity_2_sg1_11_itm = 3'b0;
+    intensity_slc_intensity_2_sg1_9_itm_1 = 2'b0;
+    intensity_slc_intensity_2_sg1_9_itm = 2'b0;
+    FRAME_acc_12_itm_1 = 6'b0;
+    FRAME_acc_12_itm = 6'b0;
+    ACC1_slc_acc_imod_28_itm_1 = 1'b0;
+    ACC1_mul_96_itm_1 = 14'b0;
+    ACC1_acc_268_itm_1 = 12'b0;
+    ACC1_mul_89_itm_1 = 10'b0;
+    ACC1_acc_255_itm_1 = 7'b0;
+    ACC1_acc_251_itm_1 = 6'b0;
+    ACC1_acc_252_itm_1 = 6'b0;
+    ACC1_2_slc_acc_idiv_132_itm_1 = 1'b0;
+    ACC1_slc_acc_idiv_3_36_itm_1 = 1'b0;
+    ACC1_mul_98_itm_1 = 6'b0;
+    ACC1_3_slc_acc_idiv_131_itm_1 = 1'b0;
+    ACC1_slc_acc_idiv_91_itm_1 = 1'b0;
+    ACC1_mul_103_itm_1 = 8'b0;
+    ACC1_3_slc_acc_idiv_132_itm_1 = 1'b0;
+    ACC1_slc_acc_idiv_2_90_itm_1 = 1'b0;
+    ACC1_mul_104_itm_1 = 10'b0;
+    ACC1_mul_91_itm_1 = 14'b0;
+    ACC1_mul_90_itm_1 = 12'b0;
+    ACC1_acc_264_itm_1 = 10'b0;
+    ACC1_2_slc_acc_idiv_106_itm_1 = 1'b0;
+    ACC1_slc_acc_imod_17_8_itm_1 = 1'b0;
+    ACC1_mul_99_itm_1 = 8'b0;
+    ACC1_2_slc_acc_idiv_131_itm_1 = 1'b0;
+    mul_1_itm_1 = 13'b0;
+    ACC1_acc_281_itm_1 = 16'b0;
+    regs_regs_slc_regs_regs_2_sg2_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_sg2_2_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_sg2_1_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_7_itm = 10'b0;
+    regs_regs_slc_regs_regs_2_6_itm = 10'b0;
+    FRAME_acc_5_psp_sva = 12'b0;
+    acc_imod_15_sva = 6'b0;
+    intensity_2_sg1_sva = 15'b0;
+    acc_imod_7_sva = 3'b0;
+    acc_imod_6_sva = 5'b0;
+    acc_idiv_2_sva = 18'b0;
+    acc_imod_1_sva = 3'b0;
+    acc_imod_sva = 5'b0;
+    acc_idiv_sva = 18'b0;
+    acc_imod_27_sva = 3'b0;
+    acc_imod_25_sva = 5'b0;
+    acc_idiv_7_sva = 18'b0;
+    acc_imod_19_sva = 3'b0;
+    acc_imod_17_sva = 5'b0;
+    acc_idiv_3_sva = 18'b0;
+    regs_regs_0_sva_1 = 90'b0;
+    regs_regs_1_sg2_sva = 30'b0;
+    regs_regs_1_1_sva = 30'b0;
+    vout_rsc_mgc_out_stdreg_d <= 30'b0;
+  end
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [14:0] readslicef_16_15_1;
+    input [15:0] vector;
+    reg [15:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_16_15_1 = tmp[14:0];
+  end
+  endfunction
+
+
+  function [15:0] signext_16_10;
+    input [9:0] vector;
+  begin
+    signext_16_10= {{6{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function [4:0] readslicef_6_5_1;
+    input [5:0] vector;
+    reg [5:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_6_5_1 = tmp[4:0];
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [15:0] signext_16_11;
+    input [10:0] vector;
+  begin
+    signext_16_11= {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_3_1_2;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 2;
+    readslicef_3_1_2 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_15_16 ;
+    input signed [14:0]  vector ;
+  begin
+    conv_s2s_15_16 = {vector[14], vector};
+  end
+  endfunction
+
+
+  function signed [14:0] conv_s2s_14_15 ;
+    input signed [13:0]  vector ;
+  begin
+    conv_s2s_14_15 = {vector[13], vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_12_14 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_14 = {{2{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [14:0] conv_u2s_14_15 ;
+    input [13:0]  vector ;
+  begin
+    conv_u2s_14_15 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_u2u_15_16 ;
+    input [14:0]  vector ;
+  begin
+    conv_u2u_15_16 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_u2u_14_15 ;
+    input [13:0]  vector ;
+  begin
+    conv_u2u_14_15 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_u2u_13_15 ;
+    input [12:0]  vector ;
+  begin
+    conv_u2u_13_15 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [17:0] conv_u2u_17_18 ;
+    input [16:0]  vector ;
+  begin
+    conv_u2u_17_18 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [16:0] conv_u2u_16_17 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_17 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [17:0] conv_u2u_16_18 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_18 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_24_12 ;
+    input [23:0]  vector ;
+  begin
+    conv_u2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_2_12 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_12 = {{10{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_u2u_14_16 ;
+    input [13:0]  vector ;
+  begin
+    conv_u2u_14_16 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_13_14 ;
+    input [12:0]  vector ;
+  begin
+    conv_u2u_13_14 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_u2u_30_15 ;
+    input [29:0]  vector ;
+  begin
+    conv_u2u_30_15 = vector[14:0];
+  end
+  endfunction
+
+
+  function signed [14:0] conv_u2s_2_15 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_15 = {{13{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_3_12 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_12 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_u2u_32_16 ;
+    input [31:0]  vector ;
+  begin
+    conv_u2u_32_16 = vector[15:0];
+  end
+  endfunction
+
+
+  function  [15:0] conv_u2u_2_16 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_16 = {{14{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_26_13 ;
+    input [25:0]  vector ;
+  begin
+    conv_u2u_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_2_8 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_8 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_9_10 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_10 = {vector[8], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_12_6 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_6 = vector[5:0];
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_2_6 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_6 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_28_14 ;
+    input [27:0]  vector ;
+  begin
+    conv_u2u_28_14 = vector[13:0];
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_2_14 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_14 = {{12{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_1_4 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_4 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v6/cycle_mgc_ioport.v b/Sobel/sobel.v6/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v6/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v6/cycle_mgc_ioport_v2001.v b/Sobel/sobel.v6/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v6/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v6/cycle_set.tcl b/Sobel/sobel.v6/cycle_set.tcl
new file mode 100644
index 0000000..27d4ac4
--- /dev/null
+++ b/Sobel/sobel.v6/cycle_set.tcl
@@ -0,0 +1,220 @@
+
+# Loop constraints
+directive set /sobel/core/core:rlp CSTEPS_FROM {{. == 0}}
+directive set /sobel/core/core:rlp/main CSTEPS_FROM {{. == 4} {.. == 0}}
+
+# IO operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:io_read(vin:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:io_write(vout:rsc.d) CSTEPS_FROM {{.. == 3}}
+
+# Real operation constraints
+directive set /sobel/core/core:rlp/main/ACC1:acc#153 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#154 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#158 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#157 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#160 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#156 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#155 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#159 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#161 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#162 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#163 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#164 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#165 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#26 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#166 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#170 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#169 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#172 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#168 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#167 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#171 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#173 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#174 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#175 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#176 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#28 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#178 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#179 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#177 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#180 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#181 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#185 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#184 CSTEPS_FROM {{.. == 1}}
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+directive set /sobel/core/core:rlp/main/ACC1:acc#182 CSTEPS_FROM {{.. == 1}}
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+directive set /sobel/core/core:rlp/main/ACC1:acc#188 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#189 CSTEPS_FROM {{.. == 1}}
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+directive set /sobel/core/core:rlp/main/ACC1:acc#191 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#22 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#192 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#19 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#26 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#193 CSTEPS_FROM {{.. == 1}}
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+directive set /sobel/core/core:rlp/main/ACC1:acc#194 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#198 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#200 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#201 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#202 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#203 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#28 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#144 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#101 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#138 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#95 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#143 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#100 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#272 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#275 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#140 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#97 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#279 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#150 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#149 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#148 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#105 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#151 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#278 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#281 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#152 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/mul#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#142 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#99 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#135 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#92 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#259 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#227 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#226 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#241 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#225 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#224 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#240 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#249 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#223 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#222 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#239 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#221 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#220 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#238 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#248 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#254 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#219 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#218 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#237 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#217 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#216 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#236 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#247 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#215 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#214 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#235 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#213 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#212 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#234 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#246 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#253 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#257 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#261 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#136 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#93 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#264 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#267 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#133 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#90 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#270 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#134 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#91 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#274 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#277 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#147 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#104 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#146 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#103 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#141 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#98 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#211 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#282 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#210 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#233 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#209 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#208 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#232 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#245 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#207 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#206 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#231 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#205 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#283 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#284 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#204 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#230 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#244 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#252 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#285 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#243 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#251 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#256 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#229 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#228 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#242 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#250 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#130 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#255 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#260 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#263 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#132 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#89 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#266 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#269 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#145 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#102 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#258 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#131 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#88 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#262 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#265 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#137 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#94 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#268 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#271 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#273 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#139 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#96 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#276 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#280 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#9 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#8 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#11 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#10 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#12 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/acc#18 CSTEPS_FROM {{.. == 3}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#6 CSTEPS_FROM {{.. == 3}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#7 CSTEPS_FROM {{.. == 3}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#19 CSTEPS_FROM {{.. == 3}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#13 CSTEPS_FROM {{.. == 3}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#14 CSTEPS_FROM {{.. == 3}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#15 CSTEPS_FROM {{.. == 3}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#16 CSTEPS_FROM {{.. == 3}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#17 CSTEPS_FROM {{.. == 3}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#18 CSTEPS_FROM {{.. == 3}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#5 CSTEPS_FROM {{.. == 3}}
+directive set /sobel/core/core:rlp/main/FRAME:or CSTEPS_FROM {{.. == 3}}
+directive set /sobel/core/core:rlp/main/FRAME:or#3 CSTEPS_FROM {{.. == 3}}
+directive set /sobel/core/core:rlp/main/FRAME:and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc CSTEPS_FROM {{.. == 1}}
diff --git a/Sobel/sobel.v6/directives.tcl b/Sobel/sobel.v6/directives.tcl
new file mode 100644
index 0000000..504c4bb
--- /dev/null
+++ b/Sobel/sobel.v6/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
+go extract
diff --git a/Sobel/sobel.v6/messages.txt b/Sobel/sobel.v6/messages.txt
new file mode 100644
index 0000000..e0a9ac3
--- /dev/null
+++ b/Sobel/sobel.v6/messages.txt
@@ -0,0 +1,234 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.14 seconds, memory usage 217816kB, peak memory usage 349092kB (SOL-9)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.cpp(137): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+
+# Messages from "go compile"
+
+Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'sobel' specified by directive (CIN-52)
+Synthesizing routine 'sobel' (CIN-13)
+Inlining routine 'sobel' (CIN-14)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Optimizing block '/sobel' ... (CIN-4)
+Inout port 'vin' is only used as an input. (OPT-10)
+Inout port 'vout' is only used as an output. (OPT-11)
+Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'in', optimizing loop 'RESET' (LOOP-12)
+Design 'sobel' was read (SOL-1)
+Optimizing partition '/sobel': (Total ops = 784, Real ops = 193, Vars = 149) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 784, Real ops = 193, Vars = 147) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 741, Real ops = 183, Vars = 151) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 741, Real ops = 183, Vars = 153) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 741, Real ops = 183, Vars = 153) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 741, Real ops = 183, Vars = 151) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 541, Real ops = 140, Vars = 114) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 525, Real ops = 140, Vars = 113) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 525, Real ops = 140, Vars = 113) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 525, Real ops = 140, Vars = 115) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 525, Real ops = 140, Vars = 115) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 515, Real ops = 138, Vars = 143) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 696, Real ops = 130, Vars = 27) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 696, Real ops = 130, Vars = 29) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 696, Real ops = 130, Vars = 30) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 696, Real ops = 130, Vars = 27) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 696, Real ops = 130, Vars = 29) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 696, Real ops = 130, Vars = 27) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 696, Real ops = 130, Vars = 29) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 696, Real ops = 130, Vars = 29) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 696, Real ops = 130, Vars = 27) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 721, Real ops = 130, Vars = 37) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 628, Real ops = 116, Vars = 34) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 628, Real ops = 116, Vars = 31) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 628, Real ops = 116, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 624, Real ops = 116, Vars = 35) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 622, Real ops = 116, Vars = 31) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 622, Real ops = 116, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 622, Real ops = 116, Vars = 31) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 622, Real ops = 116, Vars = 33) (SOL-10)
+Completed transformation 'compile' on solution 'sobel.v6': elapsed time 3.40 seconds, memory usage 222280kB, peak memory usage 349092kB (SOL-9)
+Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'sobel.v6' (SOL-8)
+Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+Loop '/sobel/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/sobel/core': (Total ops = 1727, Real ops = 311, Vars = 31) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1566, Real ops = 252, Vars = 49) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1394, Real ops = 214, Vars = 36) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1394, Real ops = 214, Vars = 36) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1401, Real ops = 214, Vars = 46) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1097, Real ops = 274, Vars = 37) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 256, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1047, Real ops = 256, Vars = 40) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 256, Vars = 37) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 256, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1047, Real ops = 256, Vars = 40) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 256, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1047, Real ops = 256, Vars = 40) (SOL-10)
+I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+Optimizing partition '/sobel': (Total ops = 1047, Real ops = 256, Vars = 40) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 256, Vars = 35) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 256, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1047, Real ops = 256, Vars = 40) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1034, Real ops = 256, Vars = 50) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1038, Real ops = 256, Vars = 49) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 702, Real ops = 186, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 589, Real ops = 162, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 589, Real ops = 162, Vars = 26) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 589, Real ops = 162, Vars = 21) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 589, Real ops = 162, Vars = 26) (SOL-10)
+Design 'sobel' contains '297' real operations. (SOL-11)
+Optimizing partition '/sobel/core': (Total ops = 592, Real ops = 162, Vars = 22) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 761, Real ops = 166, Vars = 122) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 596, Real ops = 164, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 595, Real ops = 164, Vars = 24) (SOL-10)
+Completed transformation 'architect' on solution 'sobel.v6': elapsed time 9.61 seconds, memory usage 222648kB, peak memory usage 349092kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Prescheduled LOOP 'main' (4 c-steps) (SCHD-7)
+Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 4 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'sobel.v6' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 307202, Area (Datapath, Register, Total) = 8953.75, 0.00, 8953.75 (CRAAS-11)
+Optimized LOOP 'main': Latency = 307202, Area (Datapath, Register, Total) = 8953.01, 0.00, 8953.01 (CRAAS-10)
+Optimized LOOP 'main': Latency = 307202, Area (Datapath, Register, Total) = 8801.09, 0.00, 8801.09 (CRAAS-10)
+Optimized LOOP 'main': Latency = 307202, Area (Datapath, Register, Total) = 8799.57, 0.00, 8799.57 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 307202, Area (Datapath, Register, Total) = 8799.57, 0.00, 8799.57 (CRAAS-12)
+Completed transformation 'allocate' on solution 'sobel.v6': elapsed time 3.67 seconds, memory usage 225368kB, peak memory usage 349092kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'sobel.v6' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 956, Real ops = 298, Vars = 114) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 946, Real ops = 297, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 941, Real ops = 297, Vars = 103) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 904, Real ops = 288, Vars = 85) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 879, Real ops = 288, Vars = 70) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 893, Real ops = 288, Vars = 82) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 884, Real ops = 288, Vars = 75) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 879, Real ops = 288, Vars = 70) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 893, Real ops = 288, Vars = 82) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 884, Real ops = 288, Vars = 75) (SOL-10)
+Completed transformation 'schedule' on solution 'sobel.v6': elapsed time 3.10 seconds, memory usage 256952kB, peak memory usage 349092kB (SOL-9)
+Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'sobel.v6' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 1129, Real ops = 326, Vars = 703) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1120, Real ops = 326, Vars = 696) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1567, Real ops = 329, Vars = 69) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1558, Real ops = 329, Vars = 62) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 909, Real ops = 328, Vars = 69) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 900, Real ops = 328, Vars = 62) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 909, Real ops = 328, Vars = 69) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 900, Real ops = 328, Vars = 62) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 900, Real ops = 328, Vars = 62) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 909, Real ops = 328, Vars = 69) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 909, Real ops = 328, Vars = 69) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 900, Real ops = 328, Vars = 62) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 909, Real ops = 328, Vars = 69) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 900, Real ops = 328, Vars = 62) (SOL-10)
+Completed transformation 'dpfsm' on solution 'sobel.v6': elapsed time 1.56 seconds, memory usage 257960kB, peak memory usage 349092kB (SOL-9)
+
+# Messages from "go extract"
+
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'sobel.v6' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 931, Real ops = 332, Vars = 928) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 922, Real ops = 332, Vars = 921) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 914, Real ops = 330, Vars = 72) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 905, Real ops = 330, Vars = 65) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 914, Real ops = 330, Vars = 69) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 905, Real ops = 330, Vars = 62) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 904, Real ops = 329, Vars = 62) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 904, Real ops = 329, Vars = 61) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 913, Real ops = 329, Vars = 68) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 913, Real ops = 329, Vars = 68) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 904, Real ops = 329, Vars = 61) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 913, Real ops = 329, Vars = 68) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 904, Real ops = 329, Vars = 61) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 924, Real ops = 331, Vars = 921) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 915, Real ops = 331, Vars = 914) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 924, Real ops = 331, Vars = 921) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 915, Real ops = 331, Vars = 914) (SOL-10)
+Reassigned operation ACC1:acc#294:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,3) (ASG-1)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/sobel': (Total ops = 924, Real ops = 331, Vars = 921) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 915, Real ops = 331, Vars = 914) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 908, Real ops = 329, Vars = 71) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 899, Real ops = 329, Vars = 64) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 908, Real ops = 329, Vars = 68) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 899, Real ops = 329, Vars = 61) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 908, Real ops = 329, Vars = 68) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 899, Real ops = 329, Vars = 61) (SOL-10)
+Completed transformation 'extract' on solution 'sobel.v6': elapsed time 7.89 seconds, memory usage 260480kB, peak memory usage 349092kB (SOL-9)
diff --git a/Sobel/sobel.v6/reg_sharing.tcl b/Sobel/sobel.v6/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v6/reg_sharing.tcl
diff --git a/Sobel/sobel.v6/res_sharing.tcl b/Sobel/sobel.v6/res_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v6/res_sharing.tcl
diff --git a/Sobel/sobel.v6/rtl.rpt b/Sobel/sobel.v6/rtl.rpt
new file mode 100644
index 0000000..2fe0a15
--- /dev/null
+++ b/Sobel/sobel.v6/rtl.rpt
@@ -0,0 +1,760 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 14:54:00 +0000 2016                      
+
+Solution Settings: sobel.v6
+  Current state: extract
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       298  307202     307200            0  1          
+    Design Total:                     298  307202     307200            0  0          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(1,0,1,0,2)                           2.319                       0.000      2.319 0.506         21          22 
+    mgc_add(10,0,10,0,11)                       11.241                       0.000     11.241 1.301          2           2 
+    mgc_add(10,1,10,1,11)                       11.000                       0.000     11.000 1.139          3           3 
+    mgc_add(11,0,10,1,12)                       12.000                       0.000     12.000 1.208          2           2 
+    mgc_add(11,0,11,0,12)                       12.233                       0.000     12.233 1.368          1           1 
+    mgc_add(11,1,11,1,12)                       12.000                       0.000     12.000 1.206          3           3 
+    mgc_add(12,0,12,0,13)                       13.224                       0.000     13.224 1.434          1           1 
+    mgc_add(12,0,12,1,14)                       13.000                       0.000     13.000 1.109          3           3 
+    mgc_add(13,0,13,0,14)                       14.215                       0.000     14.215 1.499          1           1 
+    mgc_add(14,0,14,1,15)                       15.000                       0.000     15.000 1.401          2           2 
+    mgc_add(15,0,15,0,16)                       16.198                       0.000     16.198 1.627          2           2 
+    mgc_add(16,0,15,1,16)                       17.000                       0.000     17.000 1.691          1           1 
+    mgc_add(16,0,16,0,17)                       17.189                       0.000     17.189 1.690          9           9 
+    mgc_add(17,0,16,0,18)                       18.184                       0.000     18.184 1.754          4           4 
+    mgc_add(19,0,2,1,19)                        20.000                       0.000     20.000 1.908          1           0 
+    mgc_add(2,0,1,0,3)                           3.315                       0.000      3.315 0.658          0           1 
+    mgc_add(2,0,2,0,3)                           3.311                       0.000      3.311 0.653         48          45 
+    mgc_add(3,0,3,0,4)                           4.302                       0.000      4.302 0.761         37          37 
+    mgc_add(4,0,3,0,5)                           5.297                       0.000      5.297 0.856          0           1 
+    mgc_add(4,0,4,0,5)                           5.293                       0.000      5.293 0.854         13          12 
+    mgc_add(5,0,5,0,6)                           6.285                       0.000      6.285 0.938         12          12 
+    mgc_add(6,0,5,1,8)                           7.000                       0.000      7.000 0.693          1           1 
+    mgc_add(6,0,6,0,6)                           7.276                       0.000      7.276 1.016          5           5 
+    mgc_add(6,0,6,0,7)                           7.276                       0.000      7.276 1.016          3           3 
+    mgc_add(7,0,7,0,8)                           8.267                       0.000      8.267 1.091          2           1 
+    mgc_add(7,0,7,1,9)                           8.000                       0.000      8.000 0.766          2           2 
+    mgc_add(8,0,8,0,9)                           9.259                       0.000      9.259 1.163          2           1 
+    mgc_add(9,0,9,1,10)                         10.000                       0.000     10.000 1.071          3           3 
+    mgc_and(19,2)                               13.867                       0.000     13.867 0.263          1           0 
+    mgc_mul(2,0,11,0,12)                       330.250                       2.000     10.250 3.181          3           3 
+    mgc_mul(2,0,13,0,14)                       330.250                       2.000     10.250 3.266          3           3 
+    mgc_mul(2,0,15,0,16)                       330.250                       2.000     10.250 3.352          2           2 
+    mgc_mul(2,0,7,0,8)                         330.250                       2.000     10.250 3.011          4           4 
+    mgc_mul(2,0,9,0,11)                        330.250                       2.000     10.250 3.044          5           5 
+    mgc_mul(3,0,11,0,12)                       330.250                       2.000     10.250 3.194          1           1 
+    mgc_mul(3,0,6,0,9)                         330.250                       2.000     10.250 2.846          5           5 
+    mgc_mux(30,1,2)                             27.583                       0.000     27.583 0.369          0           1 
+    mgc_not(1)                                   0.000                       0.000      0.000 0.000          0          77 
+    mgc_not(10)                                  0.000                       0.000      0.000 0.000          0           3 
+    mgc_not(3)                                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_or(10,2)                                 7.298                       0.000      7.298 0.268          1           1 
+    mgc_or(6,2)                                  4.379                       0.000      4.379 0.268          1           1 
+    mgc_reg_pos(1,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0          13 
+    mgc_reg_pos(10,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           9 
+    mgc_reg_pos(12,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(13,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(14,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(16,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(2,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(3,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(30,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(6,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           5 
+    mgc_reg_pos(7,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(8,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           2 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,90)                            0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(2,30)                         0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):            8771.468                      46.000   1411.000                              
+    
+  Area Scores
+                      Post-Scheduling   Post-DP & FSM Post-Assignment 
+    ----------------- --------------- --------------- ---------------
+    Total Area Score:   8799.6          8790.6          8771.5        
+    Total Reg:             0.0             0.0             0.0        
+                                                                      
+    DataPath:           8799.6 (100%)   8790.6 (100%)   8771.5 (100%) 
+      MUX:                 0.0            46.7   (1%)     27.6   (0%) 
+      FUNC:             8774.0 (100%)   8732.2  (99%)   8732.2 (100%) 
+      LOGIC:              25.5   (0%)     11.7   (0%)     11.7   (0%) 
+      BUFFER:              0.0             0.0             0.0        
+      MEM:                 0.0             0.0             0.0        
+      ROM:                 0.0             0.0             0.0        
+      REG:                 0.0             0.0             0.0        
+                                                                      
+    
+    FSM:                   0.0             0.0             0.0        
+      FSM-REG:             0.0             0.0             0.0        
+      FSM-COMB:            0.0             0.0             0.0        
+                                                                      
+    
+  Register-to-Variable Mappings
+    Register                                Size(bits) Gated Register CG Opt Done Variables                                             
+    --------------------------------------- ---------- -------------- ----------- -----------------------------------------------------
+    regs.regs(1)#1.sva                              30         Y                  regs.regs(1)#1.sva                                    
+    regs.regs(1).sg2.sva                            30         Y                  regs.regs(1).sg2.sva                                  
+    vout:rsc:mgc_out_stdreg.d                       30         Y                  vout:rsc:mgc_out_stdreg.d                             
+    ACC1:acc#281.itm#1                              16         Y                  ACC1:acc#281.itm#1                                    
+    ACC1:mul#91.itm#1                               14         Y                  ACC1:mul#91.itm#1                                     
+    ACC1:mul#96.itm#1                               14         Y                  ACC1:mul#96.itm#1                                     
+    mul#1.itm#1                                     13         Y                  mul#1.itm#1                                           
+    ACC1:acc#268.itm#1                              12         Y                  ACC1:acc#268.itm#1                                    
+    ACC1:mul#90.itm#1                               12         Y                  ACC1:mul#90.itm#1                                     
+    ACC1:acc#264.itm#1                              10         Y                  ACC1:acc#264.itm#1                                    
+    ACC1:mul#104.itm#1                              10         Y                  ACC1:mul#104.itm#1                                    
+    ACC1:mul#89.itm#1                               10         Y                  ACC1:mul#89.itm#1                                     
+    regs.regs:slc(regs.regs(2))#6.itm               10         Y                  regs.regs:slc(regs.regs(2))#6.itm                     
+    regs.regs:slc(regs.regs(2))#7.itm               10         Y                  regs.regs:slc(regs.regs(2))#7.itm                     
+    regs.regs:slc(regs.regs(2)).itm                 10         Y                  regs.regs:slc(regs.regs(2)).itm                       
+    regs.regs:slc(regs.regs(2).sg2)#1.itm           10         Y                  regs.regs:slc(regs.regs(2).sg2)#1.itm                 
+    regs.regs:slc(regs.regs(2).sg2)#2.itm           10         Y                  regs.regs:slc(regs.regs(2).sg2)#2.itm                 
+    regs.regs:slc(regs.regs(2).sg2).itm             10         Y                  regs.regs:slc(regs.regs(2).sg2).itm                   
+    ACC1:mul#103.itm#1                               8         Y                  ACC1:mul#103.itm#1                                    
+    ACC1:mul#99.itm#1                                8         Y                  ACC1:mul#99.itm#1                                     
+    ACC1:acc#255.itm#1                               7         Y                  ACC1:acc#255.itm#1                                    
+    ACC1:acc#251.itm#1                               6         Y                  ACC1:acc#251.itm#1                                    
+    ACC1:acc#252.itm#1                               6         Y                  ACC1:acc#252.itm#1                                    
+    ACC1:mul#98.itm#1                                6         Y                  ACC1:mul#98.itm#1                                     
+    FRAME:acc#12.itm#1                               6         Y                  FRAME:acc#12.itm#1                                    
+    intensity:slc(intensity#2.sg1).itm#1             6         Y                  intensity:slc(intensity#2.sg1).itm#1                  
+    intensity:slc(intensity#2.sg1)#11.itm#1          3         Y                  intensity:slc(intensity#2.sg1)#11.itm#1               
+    intensity:slc(intensity#2.sg1)#9.itm#1           2         Y                  intensity:slc(intensity#2.sg1)#9.itm#1                
+    ACC1-2:slc(acc.idiv)#106.itm#1                   1         Y                  ACC1-2:slc(acc.idiv)#106.itm#1                        
+    ACC1-2:slc(acc.idiv)#131.itm#1                   1         Y                  ACC1-2:slc(acc.idiv)#131.itm#1                        
+    ACC1-2:slc(acc.idiv)#132.itm#1                   1         Y                  ACC1-2:slc(acc.idiv)#132.itm#1                        
+    ACC1-3:slc(acc.idiv)#131.itm#1                   1         Y                  ACC1-3:slc(acc.idiv)#131.itm#1                        
+    ACC1-3:slc(acc.idiv)#132.itm#1                   1         Y                  ACC1-3:slc(acc.idiv)#132.itm#1                        
+    ACC1:slc(acc.idiv#2)#90.itm#1                    1         Y                  ACC1:slc(acc.idiv#2)#90.itm#1                         
+    ACC1:slc(acc.idiv#3)#36.itm#1                    1         Y                  ACC1:slc(acc.idiv#3)#36.itm#1                         
+    ACC1:slc(acc.idiv)#91.itm#1                      1         Y                  ACC1:slc(acc.idiv)#91.itm#1                           
+    ACC1:slc(acc.imod#17)#8.itm#1                    1         Y                  ACC1:slc(acc.imod#17)#8.itm#1                         
+    ACC1:slc(acc.imod)#28.itm#1                      1         Y                  ACC1:slc(acc.imod)#28.itm#1                           
+    intensity:slc(intensity#2.sg1)#12.itm#1          1         Y                  intensity:slc(intensity#2.sg1)#12.itm#1               
+    main.stage_0#2                                   1         Y                  main.stage_0#2                                        
+    main.stage_0#3                                   1         Y                  main.stage_0#3                                        
+                                                                                                                                        
+    Total:                                         332            332           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  15.982251999999999
+      Slack:      4.017748000000001
+      
+      Path                                                Startpoint                                        Endpoint                           Delay   Slack   
+      --------------------------------------------------- ------------------------------------------------- ---------------------------------- ------- -------
+      1                                                   sobel:core/reg(ACC1:acc#252.itm#1)                sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177  
+                                                                                                                                                               
+        Instance                                          Component                                                                            Delta   Delay   
+        --------                                          ---------                                                                            -----   -----   
+        sobel:core/reg(ACC1:acc#252.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#252.itm#1                                                                                                          0.0000  0.0000  
+        sobel:core/ACC1:acc#256                           mgc_add_6_0_6_0_7                                                                    1.0162  1.0162  
+        sobel:core/ACC1:acc#256.itm                                                                                                            0.0000  1.0162  
+        sobel:core/ACC1:acc#260                           mgc_add_7_0_7_0_8                                                                    1.0910  2.1072  
+        sobel:core/ACC1:acc#260.itm                                                                                                            0.0000  2.1072  
+        sobel:core/ACC1:acc#263                           mgc_add_9_0_9_1_10                                                                   1.0706  3.1778  
+        sobel:core/ACC1:acc#263.itm                                                                                                            0.0000  3.1778  
+        sobel:core/ACC1:acc#266                           mgc_add_10_0_10_0_11                                                                 1.3014  4.4793  
+        sobel:core/ACC1:acc#266.itm                                                                                                            0.0000  4.4793  
+        sobel:core/ACC1:acc#269                           mgc_add_12_0_12_1_14                                                                 1.1093  5.5886  
+        sobel:core/ACC1:acc#269.itm                                                                                                            0.0000  5.5886  
+        sobel:core/ACC1:acc#271                           mgc_add_12_0_12_0_13                                                                 1.4343  7.0229  
+        sobel:core/ACC1:acc#271.itm                                                                                                            0.0000  7.0229  
+        sobel:core/ACC1:acc#273                           mgc_add_14_0_14_1_15                                                                 1.4009  8.4238  
+        sobel:core/ACC1:acc#273.itm                                                                                                            0.0000  8.4238  
+        sobel:core/ACC1:acc#276                           mgc_add_15_0_15_0_16                                                                 1.6269  10.0507 
+        sobel:core/ACC1:acc#276.itm                                                                                                            0.0000  10.0507 
+        sobel:core/ACC1:acc#280                           mgc_add_16_0_16_0_17                                                                 1.6898  11.7404 
+        sobel:core/ACC1:acc#280.itm                                                                                                            0.0000  11.7404 
+        sobel:core/ACC1:acc                               mgc_add_16_0_16_0_17                                                                 1.6898  13.4302 
+        sobel:core/ACC1:acc.itm                                                                                                                0.0000  13.4302 
+        sobel:core/ACC1:slc                                                                                                                    0.0000  13.4302 
+        sobel:core/intensity#2.sg1.sva                                                                                                         0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#8                                                                                                  0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#8.itm                                                                                              0.0000  13.4302 
+        sobel:core/FRAME:acc#9                            mgc_add_3_0_3_0_4                                                                    0.7609  14.1911 
+        sobel:core/FRAME:acc#9.itm                                                                                                             0.0000  14.1911 
+        sobel:core/FRAME:acc#11                           mgc_add_4_0_4_0_5                                                                    0.8536  15.0447 
+        sobel:core/FRAME:acc#11.itm                                                                                                            0.0000  15.0447 
+        sobel:core/FRAME:acc#12                           mgc_add_5_0_5_0_6                                                                    0.9376  15.9823 
+        sobel:core/FRAME:acc#12.itm                                                                                                            0.0000  15.9823 
+        sobel:core/reg(FRAME:acc#12.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  15.9823 
+                                                                                                                                                               
+      2                                                   sobel:core/reg(ACC1:acc#252.itm#1)                sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177  
+                                                                                                                                                               
+        Instance                                          Component                                                                            Delta   Delay   
+        --------                                          ---------                                                                            -----   -----   
+        sobel:core/reg(ACC1:acc#252.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#252.itm#1                                                                                                          0.0000  0.0000  
+        sobel:core/ACC1:acc#256                           mgc_add_6_0_6_0_7                                                                    1.0162  1.0162  
+        sobel:core/ACC1:acc#256.itm                                                                                                            0.0000  1.0162  
+        sobel:core/ACC1:acc#260                           mgc_add_7_0_7_0_8                                                                    1.0910  2.1072  
+        sobel:core/ACC1:acc#260.itm                                                                                                            0.0000  2.1072  
+        sobel:core/ACC1:acc#263                           mgc_add_9_0_9_1_10                                                                   1.0706  3.1778  
+        sobel:core/ACC1:acc#263.itm                                                                                                            0.0000  3.1778  
+        sobel:core/ACC1:acc#266                           mgc_add_10_0_10_0_11                                                                 1.3014  4.4793  
+        sobel:core/ACC1:acc#266.itm                                                                                                            0.0000  4.4793  
+        sobel:core/ACC1:acc#269                           mgc_add_12_0_12_1_14                                                                 1.1093  5.5886  
+        sobel:core/ACC1:acc#269.itm                                                                                                            0.0000  5.5886  
+        sobel:core/ACC1:acc#271                           mgc_add_12_0_12_0_13                                                                 1.4343  7.0229  
+        sobel:core/ACC1:acc#271.itm                                                                                                            0.0000  7.0229  
+        sobel:core/ACC1:acc#273                           mgc_add_14_0_14_1_15                                                                 1.4009  8.4238  
+        sobel:core/ACC1:acc#273.itm                                                                                                            0.0000  8.4238  
+        sobel:core/ACC1:acc#276                           mgc_add_15_0_15_0_16                                                                 1.6269  10.0507 
+        sobel:core/ACC1:acc#276.itm                                                                                                            0.0000  10.0507 
+        sobel:core/ACC1:acc#280                           mgc_add_16_0_16_0_17                                                                 1.6898  11.7404 
+        sobel:core/ACC1:acc#280.itm                                                                                                            0.0000  11.7404 
+        sobel:core/ACC1:acc                               mgc_add_16_0_16_0_17                                                                 1.6898  13.4302 
+        sobel:core/ACC1:acc.itm                                                                                                                0.0000  13.4302 
+        sobel:core/ACC1:slc                                                                                                                    0.0000  13.4302 
+        sobel:core/intensity#2.sg1.sva                                                                                                         0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#12                                                                                                 0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#12.itm                                                                                             0.0000  13.4302 
+        sobel:core/FRAME:not#36                           mgc_not_1                                                                            0.0000  13.4302 
+        sobel:core/FRAME:not#36.itm                                                                                                            0.0000  13.4302 
+        sobel:core/conc#311                                                                                                                    0.0000  13.4302 
+        sobel:core/conc#311.itm                                                                                                                0.0000  13.4302 
+        sobel:core/FRAME:acc#8                            mgc_add_3_0_3_0_4                                                                    0.7609  14.1911 
+        sobel:core/FRAME:acc#8.itm                                                                                                             0.0000  14.1911 
+        sobel:core/FRAME:acc#11                           mgc_add_4_0_4_0_5                                                                    0.8536  15.0447 
+        sobel:core/FRAME:acc#11.itm                                                                                                            0.0000  15.0447 
+        sobel:core/FRAME:acc#12                           mgc_add_5_0_5_0_6                                                                    0.9376  15.9823 
+        sobel:core/FRAME:acc#12.itm                                                                                                            0.0000  15.9823 
+        sobel:core/reg(FRAME:acc#12.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  15.9823 
+                                                                                                                                                               
+      3                                                   sobel:core/reg(ACC1:acc#252.itm#1)                sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177  
+                                                                                                                                                               
+        Instance                                          Component                                                                            Delta   Delay   
+        --------                                          ---------                                                                            -----   -----   
+        sobel:core/reg(ACC1:acc#252.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#252.itm#1                                                                                                          0.0000  0.0000  
+        sobel:core/ACC1:acc#256                           mgc_add_6_0_6_0_7                                                                    1.0162  1.0162  
+        sobel:core/ACC1:acc#256.itm                                                                                                            0.0000  1.0162  
+        sobel:core/ACC1:acc#260                           mgc_add_7_0_7_0_8                                                                    1.0910  2.1072  
+        sobel:core/ACC1:acc#260.itm                                                                                                            0.0000  2.1072  
+        sobel:core/ACC1:acc#263                           mgc_add_9_0_9_1_10                                                                   1.0706  3.1778  
+        sobel:core/ACC1:acc#263.itm                                                                                                            0.0000  3.1778  
+        sobel:core/ACC1:acc#266                           mgc_add_10_0_10_0_11                                                                 1.3014  4.4793  
+        sobel:core/ACC1:acc#266.itm                                                                                                            0.0000  4.4793  
+        sobel:core/ACC1:acc#269                           mgc_add_12_0_12_1_14                                                                 1.1093  5.5886  
+        sobel:core/ACC1:acc#269.itm                                                                                                            0.0000  5.5886  
+        sobel:core/ACC1:acc#271                           mgc_add_12_0_12_0_13                                                                 1.4343  7.0229  
+        sobel:core/ACC1:acc#271.itm                                                                                                            0.0000  7.0229  
+        sobel:core/ACC1:acc#273                           mgc_add_14_0_14_1_15                                                                 1.4009  8.4238  
+        sobel:core/ACC1:acc#273.itm                                                                                                            0.0000  8.4238  
+        sobel:core/ACC1:acc#276                           mgc_add_15_0_15_0_16                                                                 1.6269  10.0507 
+        sobel:core/ACC1:acc#276.itm                                                                                                            0.0000  10.0507 
+        sobel:core/ACC1:acc#280                           mgc_add_16_0_16_0_17                                                                 1.6898  11.7404 
+        sobel:core/ACC1:acc#280.itm                                                                                                            0.0000  11.7404 
+        sobel:core/ACC1:acc                               mgc_add_16_0_16_0_17                                                                 1.6898  13.4302 
+        sobel:core/ACC1:acc.itm                                                                                                                0.0000  13.4302 
+        sobel:core/ACC1:slc                                                                                                                    0.0000  13.4302 
+        sobel:core/intensity#2.sg1.sva                                                                                                         0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#7                                                                                                  0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#7.itm                                                                                              0.0000  13.4302 
+        sobel:core/FRAME:not#38                           mgc_not_1                                                                            0.0000  13.4302 
+        sobel:core/FRAME:not#38.itm                                                                                                            0.0000  13.4302 
+        sobel:core/conc#311                                                                                                                    0.0000  13.4302 
+        sobel:core/conc#311.itm                                                                                                                0.0000  13.4302 
+        sobel:core/FRAME:acc#8                            mgc_add_3_0_3_0_4                                                                    0.7609  14.1911 
+        sobel:core/FRAME:acc#8.itm                                                                                                             0.0000  14.1911 
+        sobel:core/FRAME:acc#11                           mgc_add_4_0_4_0_5                                                                    0.8536  15.0447 
+        sobel:core/FRAME:acc#11.itm                                                                                                            0.0000  15.0447 
+        sobel:core/FRAME:acc#12                           mgc_add_5_0_5_0_6                                                                    0.9376  15.9823 
+        sobel:core/FRAME:acc#12.itm                                                                                                            0.0000  15.9823 
+        sobel:core/reg(FRAME:acc#12.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  15.9823 
+                                                                                                                                                               
+      4                                                   sobel:core/reg(ACC1:acc#252.itm#1)                sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177  
+                                                                                                                                                               
+        Instance                                          Component                                                                            Delta   Delay   
+        --------                                          ---------                                                                            -----   -----   
+        sobel:core/reg(ACC1:acc#252.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#252.itm#1                                                                                                          0.0000  0.0000  
+        sobel:core/ACC1:acc#256                           mgc_add_6_0_6_0_7                                                                    1.0162  1.0162  
+        sobel:core/ACC1:acc#256.itm                                                                                                            0.0000  1.0162  
+        sobel:core/ACC1:acc#260                           mgc_add_7_0_7_0_8                                                                    1.0910  2.1072  
+        sobel:core/ACC1:acc#260.itm                                                                                                            0.0000  2.1072  
+        sobel:core/ACC1:acc#263                           mgc_add_9_0_9_1_10                                                                   1.0706  3.1778  
+        sobel:core/ACC1:acc#263.itm                                                                                                            0.0000  3.1778  
+        sobel:core/ACC1:acc#266                           mgc_add_10_0_10_0_11                                                                 1.3014  4.4793  
+        sobel:core/ACC1:acc#266.itm                                                                                                            0.0000  4.4793  
+        sobel:core/ACC1:acc#269                           mgc_add_12_0_12_1_14                                                                 1.1093  5.5886  
+        sobel:core/ACC1:acc#269.itm                                                                                                            0.0000  5.5886  
+        sobel:core/ACC1:acc#271                           mgc_add_12_0_12_0_13                                                                 1.4343  7.0229  
+        sobel:core/ACC1:acc#271.itm                                                                                                            0.0000  7.0229  
+        sobel:core/ACC1:acc#273                           mgc_add_14_0_14_1_15                                                                 1.4009  8.4238  
+        sobel:core/ACC1:acc#273.itm                                                                                                            0.0000  8.4238  
+        sobel:core/ACC1:acc#276                           mgc_add_15_0_15_0_16                                                                 1.6269  10.0507 
+        sobel:core/ACC1:acc#276.itm                                                                                                            0.0000  10.0507 
+        sobel:core/ACC1:acc#280                           mgc_add_16_0_16_0_17                                                                 1.6898  11.7404 
+        sobel:core/ACC1:acc#280.itm                                                                                                            0.0000  11.7404 
+        sobel:core/ACC1:acc                               mgc_add_16_0_16_0_17                                                                 1.6898  13.4302 
+        sobel:core/ACC1:acc.itm                                                                                                                0.0000  13.4302 
+        sobel:core/ACC1:slc                                                                                                                    0.0000  13.4302 
+        sobel:core/intensity#2.sg1.sva                                                                                                         0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#10                                                                                                 0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#10.itm                                                                                             0.0000  13.4302 
+        sobel:core/FRAME:acc#8                            mgc_add_3_0_3_0_4                                                                    0.7609  14.1911 
+        sobel:core/FRAME:acc#8.itm                                                                                                             0.0000  14.1911 
+        sobel:core/FRAME:acc#11                           mgc_add_4_0_4_0_5                                                                    0.8536  15.0447 
+        sobel:core/FRAME:acc#11.itm                                                                                                            0.0000  15.0447 
+        sobel:core/FRAME:acc#12                           mgc_add_5_0_5_0_6                                                                    0.9376  15.9823 
+        sobel:core/FRAME:acc#12.itm                                                                                                            0.0000  15.9823 
+        sobel:core/reg(FRAME:acc#12.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  15.9823 
+                                                                                                                                                               
+      5                                                   sobel:core/reg(ACC1:acc#251.itm#1)                sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177  
+                                                                                                                                                               
+        Instance                                          Component                                                                            Delta   Delay   
+        --------                                          ---------                                                                            -----   -----   
+        sobel:core/reg(ACC1:acc#251.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#251.itm#1                                                                                                          0.0000  0.0000  
+        sobel:core/ACC1:acc#256                           mgc_add_6_0_6_0_7                                                                    1.0162  1.0162  
+        sobel:core/ACC1:acc#256.itm                                                                                                            0.0000  1.0162  
+        sobel:core/ACC1:acc#260                           mgc_add_7_0_7_0_8                                                                    1.0910  2.1072  
+        sobel:core/ACC1:acc#260.itm                                                                                                            0.0000  2.1072  
+        sobel:core/ACC1:acc#263                           mgc_add_9_0_9_1_10                                                                   1.0706  3.1778  
+        sobel:core/ACC1:acc#263.itm                                                                                                            0.0000  3.1778  
+        sobel:core/ACC1:acc#266                           mgc_add_10_0_10_0_11                                                                 1.3014  4.4793  
+        sobel:core/ACC1:acc#266.itm                                                                                                            0.0000  4.4793  
+        sobel:core/ACC1:acc#269                           mgc_add_12_0_12_1_14                                                                 1.1093  5.5886  
+        sobel:core/ACC1:acc#269.itm                                                                                                            0.0000  5.5886  
+        sobel:core/ACC1:acc#271                           mgc_add_12_0_12_0_13                                                                 1.4343  7.0229  
+        sobel:core/ACC1:acc#271.itm                                                                                                            0.0000  7.0229  
+        sobel:core/ACC1:acc#273                           mgc_add_14_0_14_1_15                                                                 1.4009  8.4238  
+        sobel:core/ACC1:acc#273.itm                                                                                                            0.0000  8.4238  
+        sobel:core/ACC1:acc#276                           mgc_add_15_0_15_0_16                                                                 1.6269  10.0507 
+        sobel:core/ACC1:acc#276.itm                                                                                                            0.0000  10.0507 
+        sobel:core/ACC1:acc#280                           mgc_add_16_0_16_0_17                                                                 1.6898  11.7404 
+        sobel:core/ACC1:acc#280.itm                                                                                                            0.0000  11.7404 
+        sobel:core/ACC1:acc                               mgc_add_16_0_16_0_17                                                                 1.6898  13.4302 
+        sobel:core/ACC1:acc.itm                                                                                                                0.0000  13.4302 
+        sobel:core/ACC1:slc                                                                                                                    0.0000  13.4302 
+        sobel:core/intensity#2.sg1.sva                                                                                                         0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#10                                                                                                 0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#10.itm                                                                                             0.0000  13.4302 
+        sobel:core/FRAME:acc#8                            mgc_add_3_0_3_0_4                                                                    0.7609  14.1911 
+        sobel:core/FRAME:acc#8.itm                                                                                                             0.0000  14.1911 
+        sobel:core/FRAME:acc#11                           mgc_add_4_0_4_0_5                                                                    0.8536  15.0447 
+        sobel:core/FRAME:acc#11.itm                                                                                                            0.0000  15.0447 
+        sobel:core/FRAME:acc#12                           mgc_add_5_0_5_0_6                                                                    0.9376  15.9823 
+        sobel:core/FRAME:acc#12.itm                                                                                                            0.0000  15.9823 
+        sobel:core/reg(FRAME:acc#12.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  15.9823 
+                                                                                                                                                               
+      6                                                   sobel:core/reg(ACC1:acc#252.itm#1)                sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177  
+                                                                                                                                                               
+        Instance                                          Component                                                                            Delta   Delay   
+        --------                                          ---------                                                                            -----   -----   
+        sobel:core/reg(ACC1:acc#252.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#252.itm#1                                                                                                          0.0000  0.0000  
+        sobel:core/ACC1:acc#256                           mgc_add_6_0_6_0_7                                                                    1.0162  1.0162  
+        sobel:core/ACC1:acc#256.itm                                                                                                            0.0000  1.0162  
+        sobel:core/ACC1:acc#260                           mgc_add_7_0_7_0_8                                                                    1.0910  2.1072  
+        sobel:core/ACC1:acc#260.itm                                                                                                            0.0000  2.1072  
+        sobel:core/ACC1:acc#263                           mgc_add_9_0_9_1_10                                                                   1.0706  3.1778  
+        sobel:core/ACC1:acc#263.itm                                                                                                            0.0000  3.1778  
+        sobel:core/ACC1:acc#266                           mgc_add_10_0_10_0_11                                                                 1.3014  4.4793  
+        sobel:core/ACC1:acc#266.itm                                                                                                            0.0000  4.4793  
+        sobel:core/ACC1:acc#269                           mgc_add_12_0_12_1_14                                                                 1.1093  5.5886  
+        sobel:core/ACC1:acc#269.itm                                                                                                            0.0000  5.5886  
+        sobel:core/ACC1:acc#271                           mgc_add_12_0_12_0_13                                                                 1.4343  7.0229  
+        sobel:core/ACC1:acc#271.itm                                                                                                            0.0000  7.0229  
+        sobel:core/ACC1:acc#273                           mgc_add_14_0_14_1_15                                                                 1.4009  8.4238  
+        sobel:core/ACC1:acc#273.itm                                                                                                            0.0000  8.4238  
+        sobel:core/ACC1:acc#276                           mgc_add_15_0_15_0_16                                                                 1.6269  10.0507 
+        sobel:core/ACC1:acc#276.itm                                                                                                            0.0000  10.0507 
+        sobel:core/ACC1:acc#280                           mgc_add_16_0_16_0_17                                                                 1.6898  11.7404 
+        sobel:core/ACC1:acc#280.itm                                                                                                            0.0000  11.7404 
+        sobel:core/ACC1:acc                               mgc_add_16_0_16_0_17                                                                 1.6898  13.4302 
+        sobel:core/ACC1:acc.itm                                                                                                                0.0000  13.4302 
+        sobel:core/ACC1:slc                                                                                                                    0.0000  13.4302 
+        sobel:core/intensity#2.sg1.sva                                                                                                         0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#9                                                                                                  0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#9.itm                                                                                              0.0000  13.4302 
+        sobel:core/FRAME:not#26                           mgc_not_3                                                                            0.0000  13.4302 
+        sobel:core/FRAME:not#26.itm                                                                                                            0.0000  13.4302 
+        sobel:core/FRAME:acc#9                            mgc_add_3_0_3_0_4                                                                    0.7609  14.1911 
+        sobel:core/FRAME:acc#9.itm                                                                                                             0.0000  14.1911 
+        sobel:core/FRAME:acc#11                           mgc_add_4_0_4_0_5                                                                    0.8536  15.0447 
+        sobel:core/FRAME:acc#11.itm                                                                                                            0.0000  15.0447 
+        sobel:core/FRAME:acc#12                           mgc_add_5_0_5_0_6                                                                    0.9376  15.9823 
+        sobel:core/FRAME:acc#12.itm                                                                                                            0.0000  15.9823 
+        sobel:core/reg(FRAME:acc#12.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  15.9823 
+                                                                                                                                                               
+      7                                                   sobel:core/reg(ACC1:acc#251.itm#1)                sobel:core/reg(FRAME:acc#12.itm#1) 15.9823 4.0177  
+                                                                                                                                                               
+        Instance                                          Component                                                                            Delta   Delay   
+        --------                                          ---------                                                                            -----   -----   
+        sobel:core/reg(ACC1:acc#251.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  0.0000  
+        sobel:core/ACC1:acc#251.itm#1                                                                                                          0.0000  0.0000  
+        sobel:core/ACC1:acc#256                           mgc_add_6_0_6_0_7                                                                    1.0162  1.0162  
+        sobel:core/ACC1:acc#256.itm                                                                                                            0.0000  1.0162  
+        sobel:core/ACC1:acc#260                           mgc_add_7_0_7_0_8                                                                    1.0910  2.1072  
+        sobel:core/ACC1:acc#260.itm                                                                                                            0.0000  2.1072  
+        sobel:core/ACC1:acc#263                           mgc_add_9_0_9_1_10                                                                   1.0706  3.1778  
+        sobel:core/ACC1:acc#263.itm                                                                                                            0.0000  3.1778  
+        sobel:core/ACC1:acc#266                           mgc_add_10_0_10_0_11                                                                 1.3014  4.4793  
+        sobel:core/ACC1:acc#266.itm                                                                                                            0.0000  4.4793  
+        sobel:core/ACC1:acc#269                           mgc_add_12_0_12_1_14                                                                 1.1093  5.5886  
+        sobel:core/ACC1:acc#269.itm                                                                                                            0.0000  5.5886  
+        sobel:core/ACC1:acc#271                           mgc_add_12_0_12_0_13                                                                 1.4343  7.0229  
+        sobel:core/ACC1:acc#271.itm                                                                                                            0.0000  7.0229  
+        sobel:core/ACC1:acc#273                           mgc_add_14_0_14_1_15                                                                 1.4009  8.4238  
+        sobel:core/ACC1:acc#273.itm                                                                                                            0.0000  8.4238  
+        sobel:core/ACC1:acc#276                           mgc_add_15_0_15_0_16                                                                 1.6269  10.0507 
+        sobel:core/ACC1:acc#276.itm                                                                                                            0.0000  10.0507 
+        sobel:core/ACC1:acc#280                           mgc_add_16_0_16_0_17                                                                 1.6898  11.7404 
+        sobel:core/ACC1:acc#280.itm                                                                                                            0.0000  11.7404 
+        sobel:core/ACC1:acc                               mgc_add_16_0_16_0_17                                                                 1.6898  13.4302 
+        sobel:core/ACC1:acc.itm                                                                                                                0.0000  13.4302 
+        sobel:core/ACC1:slc                                                                                                                    0.0000  13.4302 
+        sobel:core/intensity#2.sg1.sva                                                                                                         0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#9                                                                                                  0.0000  13.4302 
+        sobel:core/slc(intensity#2.sg1.sva)#9.itm                                                                                              0.0000  13.4302 
+        sobel:core/FRAME:not#26                           mgc_not_3                                                                            0.0000  13.4302 
+        sobel:core/FRAME:not#26.itm                                                                                                            0.0000  13.4302 
+        sobel:core/FRAME:acc#9                            mgc_add_3_0_3_0_4                                                                    0.7609  14.1911 
+        sobel:core/FRAME:acc#9.itm                                                                                                             0.0000  14.1911 
+        sobel:core/FRAME:acc#11                           mgc_add_4_0_4_0_5                                                                    0.8536  15.0447 
+        sobel:core/FRAME:acc#11.itm                                                                                                            0.0000  15.0447 
+        sobel:core/FRAME:acc#12                           mgc_add_5_0_5_0_6                                                                    0.9376  15.9823 
+        sobel:core/FRAME:acc#12.itm                                                                                                            0.0000  15.9823 
+        sobel:core/reg(FRAME:acc#12.itm#1)                mgc_reg_pos_6_1_0_0_0_1_1                                                            0.0000  15.9823 
+                                                                                                                                                               
+      8                                                   sobel:core/reg(regs.regs:slc(regs.regs(2))#6.itm) sobel:core/reg(ACC1:acc#281.itm#1) 15.3757 4.6243  
+                                                                                                                                                               
+        Instance                                          Component                                                                            Delta   Delay   
+        --------                                          ---------                                                                            -----   -----   
+        sobel:core/reg(regs.regs:slc(regs.regs(2))#6.itm) mgc_reg_pos_10_1_0_0_0_1_1                                                           0.0000  0.0000  
+        sobel:core/regs.regs:slc(regs.regs(2))#6.itm                                                                                           0.0000  0.0000  
+        sobel:core/ACC1:not#73                            mgc_not_10                                                                           0.0000  0.0000  
+        sobel:core/ACC1:not#73.itm                                                                                                             0.0000  0.0000  
+        sobel:core/conc#342                                                                                                                    0.0000  0.0000  
+        sobel:core/conc#342.itm                                                                                                                0.0000  0.0000  
+        sobel:core/ACC1:acc#178                           mgc_add_11_1_11_1_12                                                                 1.2059  1.2059  
+        sobel:core/ACC1:acc#178.itm                                                                                                            0.0000  1.2059  
+        sobel:core/ACC1:slc#27                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:slc#27.itm                                                                                                             0.0000  1.2059  
+        sobel:core/ACC1:exs#95                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:exs#95.itm                                                                                                             0.0000  1.2059  
+        sobel:core/ACC1:acc#177                           mgc_add_16_0_16_0_17                                                                 1.6898  2.8957  
+        sobel:core/ACC1:acc#177.itm                                                                                                            0.0000  2.8957  
+        sobel:core/ACC1-3:acc                             mgc_add_17_0_16_0_18                                                                 1.7536  4.6493  
+        sobel:core/acc.idiv.sva                                                                                                                0.0000  4.6493  
+        sobel:core/slc(acc.idiv.sva)#4                                                                                                         0.0000  4.6493  
+        sobel:core/slc(acc.idiv.sva)#4.itm                                                                                                     0.0000  4.6493  
+        sobel:core/conc#335                                                                                                                    0.0000  4.6493  
+        sobel:core/conc#335.itm                                                                                                                0.0000  4.6493  
+        sobel:core/ACC1:acc#181                           mgc_add_2_0_2_0_3                                                                    0.6525  5.3018  
+        sobel:core/ACC1:acc#181.itm                                                                                                            0.0000  5.3018  
+        sobel:core/ACC1:slc#30                                                                                                                 0.0000  5.3018  
+        sobel:core/ACC1:slc#30.itm                                                                                                             0.0000  5.3018  
+        sobel:core/conc#334                                                                                                                    0.0000  5.3018  
+        sobel:core/conc#334.itm                                                                                                                0.0000  5.3018  
+        sobel:core/ACC1:acc#185                           mgc_add_3_0_3_0_4                                                                    0.7609  6.0627  
+        sobel:core/ACC1:acc#185.itm                                                                                                            0.0000  6.0627  
+        sobel:core/ACC1:slc#34                                                                                                                 0.0000  6.0627  
+        sobel:core/ACC1:slc#34.itm                                                                                                             0.0000  6.0627  
+        sobel:core/conc#333                                                                                                                    0.0000  6.0627  
+        sobel:core/conc#333.itm                                                                                                                0.0000  6.0627  
+        sobel:core/ACC1:acc#187                           mgc_add_4_0_4_0_5                                                                    0.8536  6.9163  
+        sobel:core/ACC1:acc#187.itm                                                                                                            0.0000  6.9163  
+        sobel:core/ACC1:slc#36                                                                                                                 0.0000  6.9163  
+        sobel:core/ACC1:slc#36.itm                                                                                                             0.0000  6.9163  
+        sobel:core/conc#332                                                                                                                    0.0000  6.9163  
+        sobel:core/conc#332.itm                                                                                                                0.0000  6.9163  
+        sobel:core/ACC1:acc#188                           mgc_add_5_0_5_0_6                                                                    0.9376  7.8539  
+        sobel:core/ACC1:acc#188.itm                                                                                                            0.0000  7.8539  
+        sobel:core/ACC1:slc#37                                                                                                                 0.0000  7.8539  
+        sobel:core/ACC1:slc#37.itm                                                                                                             0.0000  7.8539  
+        sobel:core/conc#331                                                                                                                    0.0000  7.8539  
+        sobel:core/conc#331.itm                                                                                                                0.0000  7.8539  
+        sobel:core/ACC1:acc#189                           mgc_add_6_0_6_0_6                                                                    1.0162  8.8701  
+        sobel:core/ACC1:acc#189.itm                                                                                                            0.0000  8.8701  
+        sobel:core/ACC1:slc#38                                                                                                                 0.0000  8.8701  
+        sobel:core/acc.imod.sva                                                                                                                0.0000  8.8701  
+        sobel:core/slc(acc.imod.sva)#10                                                                                                        0.0000  8.8701  
+        sobel:core/slc(acc.imod.sva)#10.itm                                                                                                    0.0000  8.8701  
+        sobel:core/ACC1:conc#253                                                                                                               0.0000  8.8701  
+        sobel:core/ACC1:conc#253.itm                                                                                                           0.0000  8.8701  
+        sobel:core/ACC1:acc#272                           mgc_add_13_0_13_0_14                                                                 1.4992  10.3693 
+        sobel:core/ACC1:acc#272.itm                                                                                                            0.0000  10.3693 
+        sobel:core/ACC1:acc#275                           mgc_add_15_0_15_0_16                                                                 1.6269  11.9962 
+        sobel:core/ACC1:acc#275.itm                                                                                                            0.0000  11.9962 
+        sobel:core/ACC1:acc#279                           mgc_add_16_0_16_0_17                                                                 1.6898  13.6860 
+        sobel:core/ACC1:acc#279.itm                                                                                                            0.0000  13.6860 
+        sobel:core/ACC1:acc#281                           mgc_add_16_0_16_0_17                                                                 1.6898  15.3757 
+        sobel:core/ACC1:acc#281.itm                                                                                                            0.0000  15.3757 
+        sobel:core/reg(ACC1:acc#281.itm#1)                mgc_reg_pos_16_1_0_0_0_1_1                                                           0.0000  15.3757 
+                                                                                                                                                               
+      9                                                   sobel:core/reg(regs.regs:slc(regs.regs(2))#6.itm) sobel:core/reg(ACC1:acc#281.itm#1) 15.3757 4.6243  
+                                                                                                                                                               
+        Instance                                          Component                                                                            Delta   Delay   
+        --------                                          ---------                                                                            -----   -----   
+        sobel:core/reg(regs.regs:slc(regs.regs(2))#6.itm) mgc_reg_pos_10_1_0_0_0_1_1                                                           0.0000  0.0000  
+        sobel:core/regs.regs:slc(regs.regs(2))#6.itm                                                                                           0.0000  0.0000  
+        sobel:core/ACC1:not#73                            mgc_not_10                                                                           0.0000  0.0000  
+        sobel:core/ACC1:not#73.itm                                                                                                             0.0000  0.0000  
+        sobel:core/conc#342                                                                                                                    0.0000  0.0000  
+        sobel:core/conc#342.itm                                                                                                                0.0000  0.0000  
+        sobel:core/ACC1:acc#178                           mgc_add_11_1_11_1_12                                                                 1.2059  1.2059  
+        sobel:core/ACC1:acc#178.itm                                                                                                            0.0000  1.2059  
+        sobel:core/ACC1:slc#27                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:slc#27.itm                                                                                                             0.0000  1.2059  
+        sobel:core/ACC1:exs#95                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:exs#95.itm                                                                                                             0.0000  1.2059  
+        sobel:core/ACC1:acc#177                           mgc_add_16_0_16_0_17                                                                 1.6898  2.8957  
+        sobel:core/ACC1:acc#177.itm                                                                                                            0.0000  2.8957  
+        sobel:core/ACC1-3:acc                             mgc_add_17_0_16_0_18                                                                 1.7536  4.6493  
+        sobel:core/acc.idiv.sva                                                                                                                0.0000  4.6493  
+        sobel:core/slc(acc.idiv.sva)#7                                                                                                         0.0000  4.6493  
+        sobel:core/slc(acc.idiv.sva)#7.itm                                                                                                     0.0000  4.6493  
+        sobel:core/ACC1-3:not#5                           mgc_not_1                                                                            0.0000  4.6493  
+        sobel:core/ACC1-3:not#5.itm                                                                                                            0.0000  4.6493  
+        sobel:core/conc#336                                                                                                                    0.0000  4.6493  
+        sobel:core/conc#336.itm                                                                                                                0.0000  4.6493  
+        sobel:core/ACC1:acc#181                           mgc_add_2_0_2_0_3                                                                    0.6525  5.3018  
+        sobel:core/ACC1:acc#181.itm                                                                                                            0.0000  5.3018  
+        sobel:core/ACC1:slc#30                                                                                                                 0.0000  5.3018  
+        sobel:core/ACC1:slc#30.itm                                                                                                             0.0000  5.3018  
+        sobel:core/conc#334                                                                                                                    0.0000  5.3018  
+        sobel:core/conc#334.itm                                                                                                                0.0000  5.3018  
+        sobel:core/ACC1:acc#185                           mgc_add_3_0_3_0_4                                                                    0.7609  6.0627  
+        sobel:core/ACC1:acc#185.itm                                                                                                            0.0000  6.0627  
+        sobel:core/ACC1:slc#34                                                                                                                 0.0000  6.0627  
+        sobel:core/ACC1:slc#34.itm                                                                                                             0.0000  6.0627  
+        sobel:core/conc#333                                                                                                                    0.0000  6.0627  
+        sobel:core/conc#333.itm                                                                                                                0.0000  6.0627  
+        sobel:core/ACC1:acc#187                           mgc_add_4_0_4_0_5                                                                    0.8536  6.9163  
+        sobel:core/ACC1:acc#187.itm                                                                                                            0.0000  6.9163  
+        sobel:core/ACC1:slc#36                                                                                                                 0.0000  6.9163  
+        sobel:core/ACC1:slc#36.itm                                                                                                             0.0000  6.9163  
+        sobel:core/conc#332                                                                                                                    0.0000  6.9163  
+        sobel:core/conc#332.itm                                                                                                                0.0000  6.9163  
+        sobel:core/ACC1:acc#188                           mgc_add_5_0_5_0_6                                                                    0.9376  7.8539  
+        sobel:core/ACC1:acc#188.itm                                                                                                            0.0000  7.8539  
+        sobel:core/ACC1:slc#37                                                                                                                 0.0000  7.8539  
+        sobel:core/ACC1:slc#37.itm                                                                                                             0.0000  7.8539  
+        sobel:core/conc#331                                                                                                                    0.0000  7.8539  
+        sobel:core/conc#331.itm                                                                                                                0.0000  7.8539  
+        sobel:core/ACC1:acc#189                           mgc_add_6_0_6_0_6                                                                    1.0162  8.8701  
+        sobel:core/ACC1:acc#189.itm                                                                                                            0.0000  8.8701  
+        sobel:core/ACC1:slc#38                                                                                                                 0.0000  8.8701  
+        sobel:core/acc.imod.sva                                                                                                                0.0000  8.8701  
+        sobel:core/slc(acc.imod.sva)#10                                                                                                        0.0000  8.8701  
+        sobel:core/slc(acc.imod.sva)#10.itm                                                                                                    0.0000  8.8701  
+        sobel:core/ACC1:conc#253                                                                                                               0.0000  8.8701  
+        sobel:core/ACC1:conc#253.itm                                                                                                           0.0000  8.8701  
+        sobel:core/ACC1:acc#272                           mgc_add_13_0_13_0_14                                                                 1.4992  10.3693 
+        sobel:core/ACC1:acc#272.itm                                                                                                            0.0000  10.3693 
+        sobel:core/ACC1:acc#275                           mgc_add_15_0_15_0_16                                                                 1.6269  11.9962 
+        sobel:core/ACC1:acc#275.itm                                                                                                            0.0000  11.9962 
+        sobel:core/ACC1:acc#279                           mgc_add_16_0_16_0_17                                                                 1.6898  13.6860 
+        sobel:core/ACC1:acc#279.itm                                                                                                            0.0000  13.6860 
+        sobel:core/ACC1:acc#281                           mgc_add_16_0_16_0_17                                                                 1.6898  15.3757 
+        sobel:core/ACC1:acc#281.itm                                                                                                            0.0000  15.3757 
+        sobel:core/reg(ACC1:acc#281.itm#1)                mgc_reg_pos_16_1_0_0_0_1_1                                                           0.0000  15.3757 
+                                                                                                                                                               
+      10                                                  sobel:core/vin:rsc:mgc_in_wire.d                  sobel:core/reg(ACC1:acc#281.itm#1) 15.3757 4.6243  
+                                                                                                                                                               
+        Instance                                          Component                                                                            Delta   Delay   
+        --------                                          ---------                                                                            -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                                       0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#4)#1                                                                                                   0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#4)#1.itm                                                                                               0.0000  0.0000  
+        sobel:core/conc#343                                                                                                                    0.0000  0.0000  
+        sobel:core/conc#343.itm                                                                                                                0.0000  0.0000  
+        sobel:core/ACC1:acc#178                           mgc_add_11_1_11_1_12                                                                 1.2059  1.2059  
+        sobel:core/ACC1:acc#178.itm                                                                                                            0.0000  1.2059  
+        sobel:core/ACC1:slc#27                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:slc#27.itm                                                                                                             0.0000  1.2059  
+        sobel:core/ACC1:exs#95                                                                                                                 0.0000  1.2059  
+        sobel:core/ACC1:exs#95.itm                                                                                                             0.0000  1.2059  
+        sobel:core/ACC1:acc#177                           mgc_add_16_0_16_0_17                                                                 1.6898  2.8957  
+        sobel:core/ACC1:acc#177.itm                                                                                                            0.0000  2.8957  
+        sobel:core/ACC1-3:acc                             mgc_add_17_0_16_0_18                                                                 1.7536  4.6493  
+        sobel:core/acc.idiv.sva                                                                                                                0.0000  4.6493  
+        sobel:core/slc(acc.idiv.sva)#7                                                                                                         0.0000  4.6493  
+        sobel:core/slc(acc.idiv.sva)#7.itm                                                                                                     0.0000  4.6493  
+        sobel:core/ACC1-3:not#5                           mgc_not_1                                                                            0.0000  4.6493  
+        sobel:core/ACC1-3:not#5.itm                                                                                                            0.0000  4.6493  
+        sobel:core/conc#336                                                                                                                    0.0000  4.6493  
+        sobel:core/conc#336.itm                                                                                                                0.0000  4.6493  
+        sobel:core/ACC1:acc#181                           mgc_add_2_0_2_0_3                                                                    0.6525  5.3018  
+        sobel:core/ACC1:acc#181.itm                                                                                                            0.0000  5.3018  
+        sobel:core/ACC1:slc#30                                                                                                                 0.0000  5.3018  
+        sobel:core/ACC1:slc#30.itm                                                                                                             0.0000  5.3018  
+        sobel:core/conc#334                                                                                                                    0.0000  5.3018  
+        sobel:core/conc#334.itm                                                                                                                0.0000  5.3018  
+        sobel:core/ACC1:acc#185                           mgc_add_3_0_3_0_4                                                                    0.7609  6.0627  
+        sobel:core/ACC1:acc#185.itm                                                                                                            0.0000  6.0627  
+        sobel:core/ACC1:slc#34                                                                                                                 0.0000  6.0627  
+        sobel:core/ACC1:slc#34.itm                                                                                                             0.0000  6.0627  
+        sobel:core/conc#333                                                                                                                    0.0000  6.0627  
+        sobel:core/conc#333.itm                                                                                                                0.0000  6.0627  
+        sobel:core/ACC1:acc#187                           mgc_add_4_0_4_0_5                                                                    0.8536  6.9163  
+        sobel:core/ACC1:acc#187.itm                                                                                                            0.0000  6.9163  
+        sobel:core/ACC1:slc#36                                                                                                                 0.0000  6.9163  
+        sobel:core/ACC1:slc#36.itm                                                                                                             0.0000  6.9163  
+        sobel:core/conc#332                                                                                                                    0.0000  6.9163  
+        sobel:core/conc#332.itm                                                                                                                0.0000  6.9163  
+        sobel:core/ACC1:acc#188                           mgc_add_5_0_5_0_6                                                                    0.9376  7.8539  
+        sobel:core/ACC1:acc#188.itm                                                                                                            0.0000  7.8539  
+        sobel:core/ACC1:slc#37                                                                                                                 0.0000  7.8539  
+        sobel:core/ACC1:slc#37.itm                                                                                                             0.0000  7.8539  
+        sobel:core/conc#331                                                                                                                    0.0000  7.8539  
+        sobel:core/conc#331.itm                                                                                                                0.0000  7.8539  
+        sobel:core/ACC1:acc#189                           mgc_add_6_0_6_0_6                                                                    1.0162  8.8701  
+        sobel:core/ACC1:acc#189.itm                                                                                                            0.0000  8.8701  
+        sobel:core/ACC1:slc#38                                                                                                                 0.0000  8.8701  
+        sobel:core/acc.imod.sva                                                                                                                0.0000  8.8701  
+        sobel:core/slc(acc.imod.sva)#10                                                                                                        0.0000  8.8701  
+        sobel:core/slc(acc.imod.sva)#10.itm                                                                                                    0.0000  8.8701  
+        sobel:core/ACC1:conc#253                                                                                                               0.0000  8.8701  
+        sobel:core/ACC1:conc#253.itm                                                                                                           0.0000  8.8701  
+        sobel:core/ACC1:acc#272                           mgc_add_13_0_13_0_14                                                                 1.4992  10.3693 
+        sobel:core/ACC1:acc#272.itm                                                                                                            0.0000  10.3693 
+        sobel:core/ACC1:acc#275                           mgc_add_15_0_15_0_16                                                                 1.6269  11.9962 
+        sobel:core/ACC1:acc#275.itm                                                                                                            0.0000  11.9962 
+        sobel:core/ACC1:acc#279                           mgc_add_16_0_16_0_17                                                                 1.6898  13.6860 
+        sobel:core/ACC1:acc#279.itm                                                                                                            0.0000  13.6860 
+        sobel:core/ACC1:acc#281                           mgc_add_16_0_16_0_17                                                                 1.6898  15.3757 
+        sobel:core/ACC1:acc#281.itm                                                                                                            0.0000  15.3757 
+        sobel:core/reg(ACC1:acc#281.itm#1)                mgc_reg_pos_16_1_0_0_0_1_1                                                           0.0000  15.3757 
+                                                                                                                                                               
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                                Port                              Slack (Delay) Messages 
+      ------------------------------------------------------- ------------------------------- ------- ------- --------
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)               mux.itm                         10.7763  9.2237          
+      sobel:core/reg(intensity:slc(intensity#2.sg1)#9.itm#1)  slc(intensity#2.sg1.sva)#4.itm   6.5698 13.4302          
+      sobel:core/reg(intensity:slc(intensity#2.sg1)#11.itm#1) slc(intensity#2.sg1.sva)#3.itm   6.5698 13.4302          
+      sobel:core/reg(intensity:slc(intensity#2.sg1).itm#1)    slc(intensity#2.sg1.sva)#2.itm   6.5698 13.4302          
+      sobel:core/reg(intensity:slc(intensity#2.sg1)#12.itm#1) slc(intensity#2.sg1.sva).itm     6.5698 13.4302          
+      sobel:core/reg(FRAME:acc#12.itm#1)                      FRAME:acc#12.itm                 4.0177 15.9823          
+      sobel:core/reg(main.stage_0#2)                          C1365_11#67                     20.0000  0.0000          
+      sobel:core/reg(main.stage_0#3)                          main.stage_0#2                  20.0000  0.0000          
+      sobel:core/reg(ACC1:acc#281.itm#1)                      ACC1:acc#281.itm                 4.6243 15.3757          
+      sobel:core/reg(mul#1.itm#1)                             mul#1.itm                       11.5784  8.4216          
+      sobel:core/reg(ACC1-2:slc(acc.idiv)#131.itm#1)          slc(acc.idiv#3.sva)#27.itm      16.5566  3.4434          
+      sobel:core/reg(ACC1:mul#99.itm#1)                       ACC1:mul#99.itm                 11.8342  8.1658          
+      sobel:core/reg(ACC1:slc(acc.imod#17)#8.itm#1)           slc(acc.imod#17.sva)#2.itm      12.3359  7.6641          
+      sobel:core/reg(ACC1-2:slc(acc.idiv)#106.itm#1)          slc(acc.idiv#3.sva)#19.itm      16.5566  3.4434          
+      sobel:core/reg(ACC1:acc#264.itm#1)                      ACC1:acc#264.itm                 5.0725 14.9275          
+      sobel:core/reg(ACC1:mul#90.itm#1)                       ACC1:mul#90.itm                 11.6637  8.3363          
+      sobel:core/reg(ACC1:mul#91.itm#1)                       ACC1:mul#91.itm                 11.5784  8.4216          
+      sobel:core/reg(ACC1:mul#104.itm#1)                      ACC1:mul#104.itm                13.0067  6.9933          
+      sobel:core/reg(ACC1:slc(acc.idiv#2)#90.itm#1)           slc(acc.idiv#2.sva)#19.itm      15.4177  4.5823          
+      sobel:core/reg(ACC1-3:slc(acc.idiv)#132.itm#1)          slc(acc.idiv.sva)#24.itm        15.3507  4.6493          
+      sobel:core/reg(ACC1:mul#103.itm#1)                      ACC1:mul#103.itm                13.0401  6.9599          
+      sobel:core/reg(ACC1:slc(acc.idiv)#91.itm#1)             slc(acc.idiv.sva)#19.itm        15.3507  4.6493          
+      sobel:core/reg(ACC1-3:slc(acc.idiv)#131.itm#1)          slc(acc.idiv.sva)#22.itm        15.3507  4.6493          
+      sobel:core/reg(ACC1:mul#98.itm#1)                       ACC1:mul#98.itm                 11.9988  8.0012          
+      sobel:core/reg(ACC1:slc(acc.idiv#3)#36.itm#1)           slc(acc.idiv#3.sva)#25.itm      16.5566  3.4434          
+      sobel:core/reg(ACC1-2:slc(acc.idiv)#132.itm#1)          slc(acc.idiv#3.sva)#22.itm      16.5566  3.4434          
+      sobel:core/reg(ACC1:acc#252.itm#1)                      ACC1:acc#252.itm                 4.9873 15.0127          
+      sobel:core/reg(ACC1:acc#251.itm#1)                      ACC1:acc#251.itm                 7.2314 12.7686          
+      sobel:core/reg(ACC1:acc#255.itm#1)                      ACC1:acc#255.itm                10.9826  9.0174          
+      sobel:core/reg(ACC1:mul#89.itm#1)                       ACC1:mul#89.itm                 11.8008  8.1992          
+      sobel:core/reg(ACC1:acc#268.itm#1)                      ACC1:acc#268.itm                 8.0012 11.9988          
+      sobel:core/reg(ACC1:mul#96.itm#1)                       ACC1:mul#96.itm                 12.7844  7.2156          
+      sobel:core/reg(ACC1:slc(acc.imod)#28.itm#1)             slc(acc.imod.sva).itm           11.1299  8.8701          
+      sobel:core/reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)   slc(regs.regs(1).sg2.sva)#2.itm 20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)   slc(regs.regs(1).sg2.sva)#1.itm 20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2).sg2).itm)     slc(regs.regs(1).sg2.sva).itm   20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#6.itm)       slc(regs.regs(1)#1.sva)#2.itm   20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2))#7.itm)       slc(regs.regs(1)#1.sva)#1.itm   20.0000  0.0000          
+      sobel:core/reg(regs.regs:slc(regs.regs(2)).itm)         slc(regs.regs(1)#1.sva).itm     20.0000  0.0000          
+      sobel:core/reg(regs.regs(1).sg2.sva)                    slc(regs.regs(0).sva#7).itm     20.0000  0.0000          
+      sobel:core/reg(regs.regs(1)#1.sva)                      slc(regs.regs(0).sva#8).itm     20.0000  0.0000          
+      sobel                                                   vout:rsc.z                      20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                   18     4 
+    -                   17     9 
+    -                   16     3 
+    -                   15     2 
+    -                   14     4 
+    -                   13     1 
+    -                   12     6 
+    -                   11     5 
+    -                   10     3 
+    -                    9     3 
+    -                    8     2 
+    -                    7     3 
+    -                    6    17 
+    -                    5    13 
+    -                    4    37 
+    -                    3    46 
+    -                    2    22 
+    mul                          
+    -                   16     2 
+    -                   14     3 
+    -                   12     4 
+    -                   11     5 
+    -                    9     5 
+    -                    8     4 
+    mux                          
+    -                    1     1 
+    not                          
+    -                   10     3 
+    -                    3     4 
+    -                    1    77 
+    or                           
+    -                    2     2 
+    read_port                    
+    -                   90     1 
+    reg                          
+    -                   30     3 
+    -                   16     1 
+    -                   14     2 
+    -                   13     1 
+    -                   12     2 
+    -                   10     9 
+    -                    8     2 
+    -                    7     1 
+    -                    6     5 
+    -                    3     1 
+    -                    2     1 
+    -                    1    13 
+    write_port                   
+    -                   30     1 
+    
+  End of Report
diff --git a/Sobel/sobel.v6/rtl.v b/Sobel/sobel.v6/rtl.v
new file mode 100644
index 0000000..a14bdfc
--- /dev/null
+++ b/Sobel/sobel.v6/rtl.v
@@ -0,0 +1,1102 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 14:54:00 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [29:0] regs_regs_1_1_sva;
+  reg [29:0] regs_regs_1_sg2_sva;
+  reg [9:0] regs_regs_slc_regs_regs_2_6_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_7_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_sg2_1_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_sg2_2_itm;
+  reg [9:0] regs_regs_slc_regs_regs_2_sg2_itm;
+  reg [15:0] ACC1_acc_281_itm_1;
+  wire [18:0] nl_ACC1_acc_281_itm_1;
+  reg [12:0] mul_1_itm_1;
+  wire [25:0] nl_mul_1_itm_1;
+  reg ACC1_2_slc_acc_idiv_131_itm_1;
+  reg [7:0] ACC1_mul_99_itm_1;
+  wire [15:0] nl_ACC1_mul_99_itm_1;
+  reg ACC1_slc_acc_imod_17_8_itm_1;
+  reg ACC1_2_slc_acc_idiv_106_itm_1;
+  reg [9:0] ACC1_acc_264_itm_1;
+  wire [10:0] nl_ACC1_acc_264_itm_1;
+  reg [11:0] ACC1_mul_90_itm_1;
+  wire [23:0] nl_ACC1_mul_90_itm_1;
+  reg [13:0] ACC1_mul_91_itm_1;
+  wire [27:0] nl_ACC1_mul_91_itm_1;
+  reg [9:0] ACC1_mul_104_itm_1;
+  wire [19:0] nl_ACC1_mul_104_itm_1;
+  reg ACC1_slc_acc_idiv_2_90_itm_1;
+  reg ACC1_3_slc_acc_idiv_132_itm_1;
+  reg [7:0] ACC1_mul_103_itm_1;
+  wire [15:0] nl_ACC1_mul_103_itm_1;
+  reg ACC1_slc_acc_idiv_91_itm_1;
+  reg ACC1_3_slc_acc_idiv_131_itm_1;
+  reg [5:0] ACC1_mul_98_itm_1;
+  wire [11:0] nl_ACC1_mul_98_itm_1;
+  reg ACC1_slc_acc_idiv_3_36_itm_1;
+  reg ACC1_2_slc_acc_idiv_132_itm_1;
+  reg [5:0] ACC1_acc_252_itm_1;
+  wire [6:0] nl_ACC1_acc_252_itm_1;
+  reg [5:0] ACC1_acc_251_itm_1;
+  wire [6:0] nl_ACC1_acc_251_itm_1;
+  reg [6:0] ACC1_acc_255_itm_1;
+  wire [7:0] nl_ACC1_acc_255_itm_1;
+  reg [9:0] ACC1_mul_89_itm_1;
+  wire [19:0] nl_ACC1_mul_89_itm_1;
+  reg [11:0] ACC1_acc_268_itm_1;
+  wire [12:0] nl_ACC1_acc_268_itm_1;
+  reg [13:0] ACC1_mul_96_itm_1;
+  wire [27:0] nl_ACC1_mul_96_itm_1;
+  reg ACC1_slc_acc_imod_28_itm_1;
+  reg [5:0] FRAME_acc_12_itm_1;
+  wire [6:0] nl_FRAME_acc_12_itm_1;
+  reg [1:0] intensity_slc_intensity_2_sg1_9_itm_1;
+  reg [2:0] intensity_slc_intensity_2_sg1_11_itm_1;
+  reg [5:0] intensity_slc_intensity_2_sg1_itm_1;
+  reg intensity_slc_intensity_2_sg1_12_itm_1;
+  reg main_stage_0_2;
+  reg main_stage_0_3;
+  wire [11:0] FRAME_acc_5_psp_sva;
+  wire [13:0] nl_FRAME_acc_5_psp_sva;
+  wire [5:0] acc_imod_15_sva;
+  wire [6:0] nl_acc_imod_15_sva;
+  wire [17:0] acc_idiv_3_sva;
+  wire [18:0] nl_acc_idiv_3_sva;
+  wire [17:0] acc_idiv_7_sva;
+  wire [18:0] nl_acc_idiv_7_sva;
+  wire [17:0] acc_idiv_sva;
+  wire [18:0] nl_acc_idiv_sva;
+  wire [17:0] acc_idiv_2_sva;
+  wire [18:0] nl_acc_idiv_2_sva;
+  wire [2:0] acc_imod_19_sva;
+  wire [3:0] nl_acc_imod_19_sva;
+  wire [2:0] acc_imod_7_sva;
+  wire [3:0] nl_acc_imod_7_sva;
+  wire [3:0] ACC1_acc_230_sdt;
+  wire [4:0] nl_ACC1_acc_230_sdt;
+  wire [2:0] acc_imod_1_sva;
+  wire [3:0] nl_acc_imod_1_sva;
+  wire [2:0] acc_imod_27_sva;
+  wire [3:0] nl_acc_imod_27_sva;
+  wire [15:0] ACC1_acc_itm;
+  wire [18:0] nl_ACC1_acc_itm;
+  wire [5:0] ACC1_acc_189_itm;
+  wire [6:0] nl_ACC1_acc_189_itm;
+  wire [5:0] ACC1_acc_162_itm;
+  wire [6:0] nl_ACC1_acc_162_itm;
+  wire [5:0] ACC1_acc_201_itm;
+  wire [6:0] nl_ACC1_acc_201_itm;
+  wire [5:0] ACC1_acc_174_itm;
+  wire [6:0] nl_ACC1_acc_174_itm;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_5_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(intensity_slc_intensity_2_sg1_9_itm_1)
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(intensity_slc_intensity_2_sg1_11_itm_1)
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(intensity_slc_intensity_2_sg1_itm_1)
+      + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_15_sva[5])) , 1'b1
+      , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_15_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_15_sva[5:3])) , (~ (acc_imod_15_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_15_sva[4:3]))
+      + conv_u2u_3_5(~ (intensity_slc_intensity_2_sg1_itm_1[5:3]))) + ({4'b1001 ,
+      (acc_imod_15_sva[5])}))))) + conv_u2u_11_12(signext_11_9({intensity_slc_intensity_2_sg1_12_itm_1
+      , 3'b0 , ({{2{intensity_slc_intensity_2_sg1_12_itm_1}}, intensity_slc_intensity_2_sg1_12_itm_1})
+      , 1'b0 , intensity_slc_intensity_2_sg1_12_itm_1}));
+  assign FRAME_acc_5_psp_sva = nl_FRAME_acc_5_psp_sva[11:0];
+  assign nl_acc_imod_15_sva = FRAME_acc_12_itm_1 + 6'b101011;
+  assign acc_imod_15_sva = nl_acc_imod_15_sva[5:0];
+  assign nl_ACC1_acc_itm = ACC1_acc_281_itm_1 + ((({mul_1_itm_1 , 1'b0 , ({{1{ACC1_2_slc_acc_idiv_131_itm_1}},
+      ACC1_2_slc_acc_idiv_131_itm_1})}) + conv_s2s_15_16(conv_s2s_14_15(conv_s2s_12_14(conv_u2s_11_12({ACC1_mul_99_itm_1
+      , ACC1_slc_acc_imod_17_8_itm_1 , ({{1{ACC1_2_slc_acc_idiv_106_itm_1}}, ACC1_2_slc_acc_idiv_106_itm_1})})
+      + conv_s2s_10_12(ACC1_acc_264_itm_1)) + conv_u2s_12_14(ACC1_mul_90_itm_1))
+      + conv_u2s_14_15(ACC1_mul_91_itm_1))) + (conv_u2u_15_16(conv_u2u_14_15({ACC1_mul_104_itm_1
+      , ACC1_slc_acc_idiv_2_90_itm_1 , 1'b0 , ({{1{ACC1_3_slc_acc_idiv_132_itm_1}},
+      ACC1_3_slc_acc_idiv_132_itm_1})}) + conv_u2u_13_15(conv_u2u_12_13(({ACC1_mul_103_itm_1
+      , ACC1_slc_acc_idiv_91_itm_1 , 1'b0 , ({{1{ACC1_3_slc_acc_idiv_131_itm_1}},
+      ACC1_3_slc_acc_idiv_131_itm_1})}) + conv_u2u_11_12(conv_u2u_10_11(conv_u2u_9_10({ACC1_mul_98_itm_1
+      , ACC1_slc_acc_idiv_3_36_itm_1 , ({{1{ACC1_2_slc_acc_idiv_132_itm_1}}, ACC1_2_slc_acc_idiv_132_itm_1})})
+      + conv_u2u_8_10(conv_u2u_7_8(conv_u2u_6_7(ACC1_acc_252_itm_1) + conv_u2u_6_7(ACC1_acc_251_itm_1))
+      + conv_u2u_7_8(ACC1_acc_255_itm_1))) + conv_u2u_10_11(ACC1_mul_89_itm_1)))
+      + conv_u2u_12_13(ACC1_acc_268_itm_1))) + conv_u2u_15_16({ACC1_mul_96_itm_1
+      , ACC1_slc_acc_imod_28_itm_1})));
+  assign ACC1_acc_itm = nl_ACC1_acc_itm[15:0];
+  assign nl_ACC1_acc_189_itm = ({(readslicef_6_5_1((conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_sva[8])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_sva[9])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (acc_idiv_sva[1])) , (~ (acc_idiv_sva[13]))})))) , 1'b1}) + conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_sva[3])) , (acc_idiv_sva[12])})))) ,
+      (~ (acc_idiv_sva[15]))})))) , 1'b1}) + conv_u2u_4_6({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_sva[5])) , (~ (acc_idiv_sva[11]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_sva[6])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_sva[7])) , (acc_idiv_sva[10])})))) ,
+      (acc_idiv_sva[14])})))) , (acc_idiv_sva[16])})))) , 1'b1}) + ({4'b1011 , (acc_idiv_sva[0])
+      , (~ (acc_idiv_sva[17]))});
+  assign ACC1_acc_189_itm = nl_ACC1_acc_189_itm[5:0];
+  assign nl_acc_idiv_3_sva = conv_u2u_17_18(conv_u2u_16_17(signext_16_10(vin_rsc_mgc_in_wire_d[19:10]))
+      + conv_u2u_16_17(signext_16_10(vin_rsc_mgc_in_wire_d[9:0]))) + conv_u2u_16_18(signext_16_10(vin_rsc_mgc_in_wire_d[29:20]));
+  assign acc_idiv_3_sva = nl_acc_idiv_3_sva[17:0];
+  assign nl_acc_idiv_7_sva = conv_u2u_17_18(conv_u2u_16_17(signext_16_10(vin_rsc_mgc_in_wire_d[79:70]))
+      + conv_u2u_16_17(signext_16_10(vin_rsc_mgc_in_wire_d[69:60]))) + conv_u2u_16_18(signext_16_10(vin_rsc_mgc_in_wire_d[89:80]));
+  assign acc_idiv_7_sva = nl_acc_idiv_7_sva[17:0];
+  assign nl_acc_idiv_sva = conv_u2u_17_18(conv_u2u_16_17(signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      regs_regs_slc_regs_regs_2_6_itm) , 1'b1}) + conv_s2s_11_12({(vin_rsc_mgc_in_wire_d[19:10])
+      , 1'b1}))))) + conv_u2u_16_17(signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      regs_regs_slc_regs_regs_2_7_itm) , 1'b1}) + conv_s2s_11_12({(vin_rsc_mgc_in_wire_d[9:0])
+      , 1'b1})))))) + conv_u2u_16_18(signext_16_11(readslicef_12_11_1((conv_s2s_11_12({(~
+      regs_regs_slc_regs_regs_2_itm) , 1'b1}) + conv_s2s_11_12({(vin_rsc_mgc_in_wire_d[29:20])
+      , 1'b1})))));
+  assign acc_idiv_sva = nl_acc_idiv_sva[17:0];
+  assign nl_acc_idiv_2_sva = conv_u2u_17_18(conv_u2u_16_17(signext_16_11(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[79:70])
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_sg2_1_itm))) + conv_u2u_16_17(signext_16_11(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[69:60])
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_sg2_2_itm)))) + conv_u2u_16_18(signext_16_11(conv_s2s_10_11(vin_rsc_mgc_in_wire_d[89:80])
+      + conv_s2s_10_11(regs_regs_slc_regs_regs_2_sg2_itm)));
+  assign acc_idiv_2_sva = nl_acc_idiv_2_sva[17:0];
+  assign nl_ACC1_acc_162_itm = ({(readslicef_6_5_1((conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_3_sva[8])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_3_sva[9])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (acc_idiv_3_sva[1])) , (~ (acc_idiv_3_sva[13]))})))) , 1'b1}) + conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_3_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_3_sva[3])) , (acc_idiv_3_sva[12])}))))
+      , (~ (acc_idiv_3_sva[15]))})))) , 1'b1}) + conv_u2u_4_6({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_3_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_3_sva[5])) , (~ (acc_idiv_3_sva[11]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_3_sva[6])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_3_sva[7])) , (acc_idiv_3_sva[10])}))))
+      , (acc_idiv_3_sva[14])})))) , (acc_idiv_3_sva[16])})))) , 1'b1}) + ({4'b1011
+      , (acc_idiv_3_sva[0]) , (~ (acc_idiv_3_sva[17]))});
+  assign ACC1_acc_162_itm = nl_ACC1_acc_162_itm[5:0];
+  assign nl_acc_imod_19_sva = (readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_162_itm[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_162_itm[4])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (ACC1_acc_162_itm[2])) , (~ (ACC1_acc_162_itm[5]))})))) + ({2'b10 , (ACC1_acc_162_itm[1])});
+  assign acc_imod_19_sva = nl_acc_imod_19_sva[2:0];
+  assign nl_ACC1_acc_201_itm = ({(readslicef_6_5_1((conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_2_sva[8])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_2_sva[9])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (acc_idiv_2_sva[1])) , (~ (acc_idiv_2_sva[13]))})))) , 1'b1}) + conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_2_sva[3])) , (acc_idiv_2_sva[12])}))))
+      , (~ (acc_idiv_2_sva[15]))})))) , 1'b1}) + conv_u2u_4_6({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_2_sva[5])) , (~ (acc_idiv_2_sva[11]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_2_sva[6])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_2_sva[7])) , (acc_idiv_2_sva[10])}))))
+      , (acc_idiv_2_sva[14])})))) , (acc_idiv_2_sva[16])})))) , 1'b1}) + ({4'b1011
+      , (acc_idiv_2_sva[0]) , (~ (acc_idiv_2_sva[17]))});
+  assign ACC1_acc_201_itm = nl_ACC1_acc_201_itm[5:0];
+  assign nl_ACC1_acc_174_itm = ({(readslicef_6_5_1((conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[8])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_7_sva[9])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (acc_idiv_7_sva[1])) , (~ (acc_idiv_7_sva[13]))})))) , 1'b1}) + conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_7_sva[3])) , (acc_idiv_7_sva[12])}))))
+      , (~ (acc_idiv_7_sva[15]))})))) , 1'b1}) + conv_u2u_4_6({(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_7_sva[5])) , (~ (acc_idiv_7_sva[11]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[6])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_idiv_7_sva[7])) , (acc_idiv_7_sva[10])}))))
+      , (acc_idiv_7_sva[14])})))) , (acc_idiv_7_sva[16])})))) , 1'b1}) + ({4'b1011
+      , (acc_idiv_7_sva[0]) , (~ (acc_idiv_7_sva[17]))});
+  assign ACC1_acc_174_itm = nl_ACC1_acc_174_itm[5:0];
+  assign nl_acc_imod_7_sva = (readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_201_itm[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_201_itm[4])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (ACC1_acc_201_itm[2])) , (~ (ACC1_acc_201_itm[5]))})))) + ({2'b10 , (ACC1_acc_201_itm[1])});
+  assign acc_imod_7_sva = nl_acc_imod_7_sva[2:0];
+  assign nl_ACC1_acc_230_sdt = conv_u2u_3_4(conv_u2u_2_3({(~ (ACC1_acc_174_itm[5]))
+      , (~ (ACC1_acc_189_itm[5]))}) + conv_u2u_2_3({(acc_imod_27_sva[1]) , 1'b1}))
+      + conv_u2u_3_4(conv_u2u_2_3({(~ (acc_imod_27_sva[2])) , (~ (acc_imod_1_sva[2]))})
+      + conv_u2u_2_3({(~ (readslicef_3_1_2((({1'b1 , (acc_imod_27_sva[0]) , 1'b1})
+      + conv_u2s_2_3({(~ (acc_imod_27_sva[1])) , (~ (acc_imod_27_sva[2]))}))))) ,
+      (~ (readslicef_3_1_2((({1'b1 , (acc_imod_1_sva[0]) , 1'b1}) + conv_u2s_2_3({(~
+      (acc_imod_1_sva[1])) , (~ (acc_imod_1_sva[2]))})))))}));
+  assign ACC1_acc_230_sdt = nl_ACC1_acc_230_sdt[3:0];
+  assign nl_acc_imod_1_sva = (readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_189_itm[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_189_itm[4])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (ACC1_acc_189_itm[2])) , (~ (ACC1_acc_189_itm[5]))})))) + ({2'b10 , (ACC1_acc_189_itm[1])});
+  assign acc_imod_1_sva = nl_acc_imod_1_sva[2:0];
+  assign nl_acc_imod_27_sva = (readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_174_itm[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_174_itm[4])) , 1'b1})))) , 1'b1}) + conv_u2u_2_4({(~
+      (ACC1_acc_174_itm[2])) , (~ (ACC1_acc_174_itm[5]))})))) + ({2'b10 , (ACC1_acc_174_itm[1])});
+  assign acc_imod_27_sva = nl_acc_imod_27_sva[2:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      intensity_slc_intensity_2_sg1_9_itm_1 <= 2'b0;
+      intensity_slc_intensity_2_sg1_11_itm_1 <= 3'b0;
+      intensity_slc_intensity_2_sg1_itm_1 <= 6'b0;
+      intensity_slc_intensity_2_sg1_12_itm_1 <= 1'b0;
+      FRAME_acc_12_itm_1 <= 6'b0;
+      main_stage_0_2 <= 1'b0;
+      main_stage_0_3 <= 1'b0;
+      ACC1_acc_281_itm_1 <= 16'b0;
+      mul_1_itm_1 <= 13'b0;
+      ACC1_2_slc_acc_idiv_131_itm_1 <= 1'b0;
+      ACC1_mul_99_itm_1 <= 8'b0;
+      ACC1_slc_acc_imod_17_8_itm_1 <= 1'b0;
+      ACC1_2_slc_acc_idiv_106_itm_1 <= 1'b0;
+      ACC1_acc_264_itm_1 <= 10'b0;
+      ACC1_mul_90_itm_1 <= 12'b0;
+      ACC1_mul_91_itm_1 <= 14'b0;
+      ACC1_mul_104_itm_1 <= 10'b0;
+      ACC1_slc_acc_idiv_2_90_itm_1 <= 1'b0;
+      ACC1_3_slc_acc_idiv_132_itm_1 <= 1'b0;
+      ACC1_mul_103_itm_1 <= 8'b0;
+      ACC1_slc_acc_idiv_91_itm_1 <= 1'b0;
+      ACC1_3_slc_acc_idiv_131_itm_1 <= 1'b0;
+      ACC1_mul_98_itm_1 <= 6'b0;
+      ACC1_slc_acc_idiv_3_36_itm_1 <= 1'b0;
+      ACC1_2_slc_acc_idiv_132_itm_1 <= 1'b0;
+      ACC1_acc_252_itm_1 <= 6'b0;
+      ACC1_acc_251_itm_1 <= 6'b0;
+      ACC1_acc_255_itm_1 <= 7'b0;
+      ACC1_mul_89_itm_1 <= 10'b0;
+      ACC1_acc_268_itm_1 <= 12'b0;
+      ACC1_mul_96_itm_1 <= 14'b0;
+      ACC1_slc_acc_imod_28_itm_1 <= 1'b0;
+      regs_regs_slc_regs_regs_2_sg2_1_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_sg2_2_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_sg2_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_6_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_7_itm <= 10'b0;
+      regs_regs_slc_regs_regs_2_itm <= 10'b0;
+      regs_regs_1_sg2_sva <= 30'b0;
+      regs_regs_1_1_sva <= 30'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({vout_rsc_mgc_out_stdreg_d , ({((FRAME_acc_5_psp_sva[9:0])
+            | ({8'b0 , (FRAME_acc_5_psp_sva[11:10])})) , (FRAME_acc_5_psp_sva[9:6])
+            , ((FRAME_acc_5_psp_sva[5:0]) | ({4'b0 , (FRAME_acc_5_psp_sva[11:10])}))
+            , (FRAME_acc_5_psp_sva[9:0])})}, main_stage_0_3);
+        intensity_slc_intensity_2_sg1_9_itm_1 <= ACC1_acc_itm[14:13];
+        intensity_slc_intensity_2_sg1_11_itm_1 <= ACC1_acc_itm[12:10];
+        intensity_slc_intensity_2_sg1_itm_1 <= ACC1_acc_itm[9:4];
+        intensity_slc_intensity_2_sg1_12_itm_1 <= ACC1_acc_itm[15];
+        FRAME_acc_12_itm_1 <= nl_FRAME_acc_12_itm_1[5:0];
+        main_stage_0_2 <= 1'b1;
+        main_stage_0_3 <= main_stage_0_2;
+        ACC1_acc_281_itm_1 <= nl_ACC1_acc_281_itm_1[15:0];
+        mul_1_itm_1 <= nl_mul_1_itm_1[12:0];
+        ACC1_2_slc_acc_idiv_131_itm_1 <= acc_idiv_3_sva[13];
+        ACC1_mul_99_itm_1 <= nl_ACC1_mul_99_itm_1[7:0];
+        ACC1_slc_acc_imod_17_8_itm_1 <= ACC1_acc_162_itm[4];
+        ACC1_2_slc_acc_idiv_106_itm_1 <= acc_idiv_3_sva[17];
+        ACC1_acc_264_itm_1 <= nl_ACC1_acc_264_itm_1[9:0];
+        ACC1_mul_90_itm_1 <= nl_ACC1_mul_90_itm_1[11:0];
+        ACC1_mul_91_itm_1 <= nl_ACC1_mul_91_itm_1[13:0];
+        ACC1_mul_104_itm_1 <= nl_ACC1_mul_104_itm_1[9:0];
+        ACC1_slc_acc_idiv_2_90_itm_1 <= acc_idiv_2_sva[5];
+        ACC1_3_slc_acc_idiv_132_itm_1 <= acc_idiv_sva[15];
+        ACC1_mul_103_itm_1 <= nl_ACC1_mul_103_itm_1[7:0];
+        ACC1_slc_acc_idiv_91_itm_1 <= acc_idiv_sva[7];
+        ACC1_3_slc_acc_idiv_131_itm_1 <= acc_idiv_sva[13];
+        ACC1_mul_98_itm_1 <= nl_ACC1_mul_98_itm_1[5:0];
+        ACC1_slc_acc_idiv_3_36_itm_1 <= acc_idiv_3_sva[3];
+        ACC1_2_slc_acc_idiv_132_itm_1 <= acc_idiv_3_sva[15];
+        ACC1_acc_252_itm_1 <= nl_ACC1_acc_252_itm_1[5:0];
+        ACC1_acc_251_itm_1 <= nl_ACC1_acc_251_itm_1[5:0];
+        ACC1_acc_255_itm_1 <= nl_ACC1_acc_255_itm_1[6:0];
+        ACC1_mul_89_itm_1 <= nl_ACC1_mul_89_itm_1[9:0];
+        ACC1_acc_268_itm_1 <= nl_ACC1_acc_268_itm_1[11:0];
+        ACC1_mul_96_itm_1 <= nl_ACC1_mul_96_itm_1[13:0];
+        ACC1_slc_acc_imod_28_itm_1 <= ACC1_acc_189_itm[4];
+        regs_regs_slc_regs_regs_2_sg2_1_itm <= regs_regs_1_sg2_sva[19:10];
+        regs_regs_slc_regs_regs_2_sg2_2_itm <= regs_regs_1_sg2_sva[9:0];
+        regs_regs_slc_regs_regs_2_sg2_itm <= regs_regs_1_sg2_sva[29:20];
+        regs_regs_slc_regs_regs_2_6_itm <= regs_regs_1_1_sva[19:10];
+        regs_regs_slc_regs_regs_2_7_itm <= regs_regs_1_1_sva[9:0];
+        regs_regs_slc_regs_regs_2_itm <= regs_regs_1_1_sva[29:20];
+        regs_regs_1_sg2_sva <= vin_rsc_mgc_in_wire_d[89:60];
+        regs_regs_1_1_sva <= vin_rsc_mgc_in_wire_d[29:0];
+      end
+    end
+  end
+  assign nl_FRAME_acc_12_itm_1  = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~ (ACC1_acc_itm[15]))
+      , 1'b1 , (~ (ACC1_acc_itm[15]))}) + conv_u2u_2_4(ACC1_acc_itm[14:13]))) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_itm[3:1])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[6:4])));
+  assign nl_ACC1_acc_281_itm_1  = ((conv_u2u_15_16({conv_u2u_24_12(conv_u2u_2_12(conv_u2u_1_2(acc_idiv_sva[15])
+      + conv_u2u_1_2(acc_idiv_2_sva[15])) * 12'b10101010101) , (ACC1_acc_174_itm[4])
+      , (signext_2_1(acc_idiv_sva[17]))}) + conv_u2u_14_16(conv_u2u_13_14({conv_u2u_24_12(conv_u2u_2_12(conv_u2u_1_2(acc_idiv_3_sva[12])
+      + conv_u2u_1_2(acc_idiv_7_sva[12])) * 12'b10101010101) , (ACC1_acc_189_itm[3])})
+      + conv_u2u_13_14({conv_u2u_20_10(conv_u2u_2_10(conv_u2u_1_2(acc_idiv_sva[13])
+      + conv_u2u_1_2(acc_idiv_2_sva[13])) * 10'b101010101) , (acc_idiv_7_sva[3])
+      , (signext_2_1(acc_idiv_3_sva[5]))}))) + ({conv_u2u_30_15(conv_u2s_2_15(conv_u2u_1_2(acc_idiv_3_sva[16])
+      + conv_u2u_1_2(acc_idiv_7_sva[16])) * 15'b101010101010101) , (acc_imod_1_sva[1])}))
+      + (({conv_u2u_24_12(conv_u2u_3_12(conv_u2u_2_3((conv_u2u_1_2(acc_idiv_3_sva[15])
+      + conv_u2u_1_2(acc_idiv_7_sva[15])) + conv_u2u_1_2(acc_idiv_7_sva[17])) + conv_u2u_1_3(acc_idiv_3_sva[17]))
+      * 12'b10101010101) , (acc_idiv_2_sva[7]) , 1'b0 , (signext_2_1(acc_idiv_3_sva[7]))})
+      + conv_u2u_32_16(conv_u2u_2_16(conv_u2u_1_2(acc_idiv_sva[16]) + conv_u2u_1_2(acc_idiv_2_sva[16]))
+      * 16'b101010101010101));
+  assign nl_mul_1_itm_1  = conv_u2s_2_13(conv_u2u_1_2(acc_idiv_sva[17]) + conv_u2u_1_2(acc_idiv_2_sva[17]))
+      * 13'b1010101010101;
+  assign nl_ACC1_mul_99_itm_1  = conv_u2u_2_8(conv_u2u_1_2(acc_idiv_sva[11]) + conv_u2u_1_2(acc_idiv_2_sva[11]))
+      * 8'b1010101;
+  assign nl_ACC1_acc_264_itm_1  = conv_s2s_9_10(conv_s2s_7_9(({5'b10101 , (signext_2_1(acc_idiv_sva[9]))})
+      + ({conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(acc_idiv_3_sva[6]) + conv_u2u_1_2(acc_idiv_7_sva[6]))
+      * 6'b10101) , (acc_idiv_2_sva[3])})) + conv_u2s_7_9(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[13]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[15]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[17])))) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[5]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[7]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[9]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[11]))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[13]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[15]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[5]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[7])))) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[9]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[11]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[13]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[15])))))) + conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[7]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[9]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[11]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[13])))) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[15]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[17]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_7_sva[5]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_2_sva[17]))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3({(acc_idiv_sva[3])
+      , (acc_idiv_sva[1])}) + conv_u2u_2_3({(acc_idiv_2_sva[3]) , (acc_idiv_sva[2])}))
+      + conv_u2u_3_4(conv_u2u_2_3({(acc_idiv_3_sva[1]) , (acc_idiv_sva[3])}) + conv_u2u_2_3({(acc_idiv_3_sva[2])
+      , (acc_idiv_sva[4])}))) + conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3({(acc_idiv_3_sva[3])
+      , (acc_idiv_2_sva[1])}) + conv_u2u_2_3({(acc_idiv_3_sva[4]) , (acc_idiv_2_sva[2])}))
+      + conv_u2u_3_4(conv_u2u_2_3({(ACC1_acc_189_itm[4]) , (ACC1_acc_201_itm[2])})
+      + conv_u2u_2_3({(ACC1_acc_162_itm[2]) , (ACC1_acc_201_itm[3])}))))))) + conv_u2s_9_10({conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(acc_idiv_3_sva[8])
+      + conv_u2u_1_2(acc_idiv_7_sva[8])) * 8'b1010101) , (acc_idiv_2_sva[4])});
+  assign nl_ACC1_mul_90_itm_1  = conv_u2u_2_12(conv_u2u_1_2(acc_idiv_sva[12]) + conv_u2u_1_2(acc_idiv_2_sva[12]))
+      * 12'b10101010101;
+  assign nl_ACC1_mul_91_itm_1  = conv_u2u_2_14(conv_u2u_1_2(acc_idiv_sva[14]) + conv_u2u_1_2(acc_idiv_2_sva[14]))
+      * 14'b1010101010101;
+  assign nl_ACC1_mul_104_itm_1  = conv_u2u_2_10(conv_u2u_1_2(acc_idiv_3_sva[13])
+      + conv_u2u_1_2(acc_idiv_7_sva[13])) * 10'b101010101;
+  assign nl_ACC1_mul_103_itm_1  = conv_u2u_2_8(conv_u2u_1_2(acc_idiv_3_sva[11]) +
+      conv_u2u_1_2(acc_idiv_7_sva[11])) * 8'b1010101;
+  assign nl_ACC1_mul_98_itm_1  = conv_u2u_2_6(conv_u2u_1_2(acc_idiv_sva[9]) + conv_u2u_1_2(acc_idiv_2_sva[9]))
+      * 6'b10101;
+  assign nl_ACC1_acc_252_itm_1  = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(conv_u2u_2_3({(ACC1_acc_162_itm[3])
+      , (ACC1_acc_201_itm[4])}) + conv_u2u_2_3({(ACC1_acc_162_itm[4]) , (acc_imod_7_sva[1])}))
+      + conv_u2u_3_4({(conv_u2u_1_2(acc_imod_19_sva[1]) + conv_u2u_1_2(~ (acc_imod_19_sva[2])))
+      , (~ (readslicef_3_1_2((({1'b1 , (acc_imod_7_sva[0]) , 1'b1}) + conv_u2s_2_3({(~
+      (acc_imod_7_sva[1])) , (~ (acc_imod_7_sva[2]))})))))})) + conv_u2u_4_5({(conv_u2u_2_3(readslicef_3_2_1((conv_u2u_2_3({(acc_idiv_7_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(acc_idiv_7_sva[3]) , (acc_idiv_7_sva[4])})))) + conv_u2u_1_3(acc_idiv_7_sva[1]))
+      , 1'b1})) + conv_u2u_5_6({(readslicef_5_4_1((conv_u2u_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_201_itm[4])
+      , 1'b1}) + conv_u2u_2_3({(ACC1_acc_174_itm[2]) , (ACC1_acc_174_itm[3])}))))
+      , 1'b1}) + conv_u2u_4_5({(ACC1_acc_230_sdt[3:1]) , (ACC1_acc_174_itm[4])}))))
+      , (ACC1_acc_230_sdt[0])});
+  assign nl_ACC1_acc_251_itm_1  = conv_u2u_5_6(conv_u2u_4_5({(~ (ACC1_acc_162_itm[5]))
+      , (~ (ACC1_acc_189_itm[5])) , (~ (readslicef_3_1_2((({1'b1 , (acc_imod_19_sva[0])
+      , 1'b1}) + conv_u2s_2_3({(~ (acc_imod_19_sva[1])) , (~ (acc_imod_19_sva[2]))})))))
+      , (~ (ACC1_acc_201_itm[5]))}) + conv_u2u_4_5({(~ (ACC1_acc_174_itm[5])) , (~
+      (ACC1_acc_201_itm[5])) , (~ (ACC1_acc_162_itm[5])) , (~ (acc_imod_7_sva[2]))}))
+      + conv_u2u_5_6({(acc_idiv_7_sva[5]) , (acc_idiv_3_sva[4]) , 1'b0 , (signext_2_1(acc_idiv_3_sva[9]))});
+  assign nl_ACC1_acc_255_itm_1  = conv_u2u_6_7(conv_u2u_5_6({(acc_idiv_7_sva[7])
+      , (acc_idiv_7_sva[4]) , 1'b0 , (signext_2_1(acc_idiv_3_sva[11]))}) + conv_u2u_4_6(conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[17]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[5]))) + conv_u2u_3_4(conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[7]))
+      + conv_u2u_2_3(signext_2_1(acc_idiv_3_sva[9]))))) + conv_u2u_6_7(conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(acc_idiv_sva[6])
+      + conv_u2u_1_2(acc_idiv_2_sva[6])) * 6'b10101));
+  assign nl_ACC1_mul_89_itm_1  = conv_u2u_2_10(conv_u2u_1_2(acc_idiv_sva[10]) + conv_u2u_1_2(acc_idiv_2_sva[10]))
+      * 10'b101010101;
+  assign nl_ACC1_acc_268_itm_1  = conv_u2u_11_12(conv_u2u_10_11({conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(acc_idiv_3_sva[9])
+      + conv_u2u_1_2(acc_idiv_7_sva[9])) * 6'b10101) , (acc_idiv_sva[5]) , 1'b0 ,
+      (signext_2_1(acc_idiv_sva[11]))}) + conv_u2u_9_11(conv_u2u_8_9({(conv_u2u_3_4({(acc_idiv_3_sva[7])
+      , (acc_idiv_sva[7]) , (acc_idiv_3_sva[5])}) + conv_u2u_3_4({(acc_idiv_7_sva[7])
+      , (acc_idiv_2_sva[7]) , (acc_idiv_3_sva[7])})) , (conv_u2u_3_4({(acc_idiv_sva[4])
+      , (signext_2_1(acc_idiv_sva[5]))}) + conv_u2u_3_4({(acc_idiv_2_sva[4]) , (signext_2_1(acc_idiv_sva[7]))}))})
+      + conv_u2u_8_9(conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(acc_idiv_sva[8]) + conv_u2u_1_2(acc_idiv_2_sva[8]))
+      * 8'b1010101)))) + conv_u2u_11_12({conv_u2u_20_10(conv_u2u_2_10(conv_u2u_1_2(acc_idiv_3_sva[10])
+      + conv_u2u_1_2(acc_idiv_7_sva[10])) * 10'b101010101) , (ACC1_acc_189_itm[2])});
+  assign nl_ACC1_mul_96_itm_1  = conv_u2u_2_14(conv_u2u_1_2(acc_idiv_3_sva[14]) +
+      conv_u2u_1_2(acc_idiv_7_sva[14])) * 14'b1010101010101;
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [4:0] readslicef_6_5_1;
+    input [5:0] vector;
+    reg [5:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_6_5_1 = tmp[4:0];
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [15:0] signext_16_10;
+    input [9:0] vector;
+  begin
+    signext_16_10= {{6{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function [15:0] signext_16_11;
+    input [10:0] vector;
+  begin
+    signext_16_11= {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_3_1_2;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 2;
+    readslicef_3_1_2 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_15_16 ;
+    input signed [14:0]  vector ;
+  begin
+    conv_s2s_15_16 = {vector[14], vector};
+  end
+  endfunction
+
+
+  function signed [14:0] conv_s2s_14_15 ;
+    input signed [13:0]  vector ;
+  begin
+    conv_s2s_14_15 = {vector[13], vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_s2s_12_14 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_14 = {{2{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [13:0] conv_u2s_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2s_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [14:0] conv_u2s_14_15 ;
+    input [13:0]  vector ;
+  begin
+    conv_u2s_14_15 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_u2u_15_16 ;
+    input [14:0]  vector ;
+  begin
+    conv_u2u_15_16 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_u2u_14_15 ;
+    input [13:0]  vector ;
+  begin
+    conv_u2u_14_15 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_u2u_13_15 ;
+    input [12:0]  vector ;
+  begin
+    conv_u2u_13_15 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [17:0] conv_u2u_17_18 ;
+    input [16:0]  vector ;
+  begin
+    conv_u2u_17_18 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [16:0] conv_u2u_16_17 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_17 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [17:0] conv_u2u_16_18 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_18 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_24_12 ;
+    input [23:0]  vector ;
+  begin
+    conv_u2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_2_12 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_12 = {{10{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_u2u_14_16 ;
+    input [13:0]  vector ;
+  begin
+    conv_u2u_14_16 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_13_14 ;
+    input [12:0]  vector ;
+  begin
+    conv_u2u_13_14 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_u2u_30_15 ;
+    input [29:0]  vector ;
+  begin
+    conv_u2u_30_15 = vector[14:0];
+  end
+  endfunction
+
+
+  function signed [14:0] conv_u2s_2_15 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_15 = {{13{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_3_12 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_12 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_u2u_32_16 ;
+    input [31:0]  vector ;
+  begin
+    conv_u2u_32_16 = vector[15:0];
+  end
+  endfunction
+
+
+  function  [15:0] conv_u2u_2_16 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_16 = {{14{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_2_8 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_8 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_9_10 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_10 = {vector[8], vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_12_6 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_6 = vector[5:0];
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_2_6 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_6 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_2_14 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_14 = {{12{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_8_9 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_9 = {1'b0, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v6/rtl.v.psr b/Sobel/sobel.v6/rtl.v.psr
new file mode 100644
index 0000000..6cb641c
--- /dev/null
+++ b/Sobel/sobel.v6/rtl.v.psr
@@ -0,0 +1,289 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v6/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v6/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v6/rtl.v}} -format verilog
+   setup_design -design=sobel
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'sobel': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'sobel': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'sobel'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'sobel'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to vout_rsc_z(29:0)
+   report_timing -from en -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from vin_rsc_z(89:0) -to vout_rsc_z(29:0)
+   report_timing -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock clk] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock en] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'sobel'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'sobel'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v6 mapped.v]
+          puts "-- Writing mapped netlist for 'sobel' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v6 gate.v]
+          set gate_sdf [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v6 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/Sobel/sobel.v6/rtl.v.psr_timing b/Sobel/sobel.v6/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/Sobel/sobel.v6/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/Sobel/sobel.v6/rtl.v_order.txt b/Sobel/sobel.v6/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/Sobel/sobel.v6/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/Sobel/sobel.v6/rtl_mgc_ioport.v b/Sobel/sobel.v6/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v6/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v6/rtl_mgc_ioport_v2001.v b/Sobel/sobel.v6/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v6/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v6/schedule.gnt b/Sobel/sobel.v6/schedule.gnt
new file mode 100644
index 0000000..ee7976e
--- /dev/null
+++ b/Sobel/sobel.v6/schedule.gnt
@@ -0,0 +1,909 @@
+set a(0-1908) {NAME FRAME:p:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-1907 XREFS 15605 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1913 {}}} SUCCS {{258 0 0-1913 {}}} CYCLES {}}
+set a(0-1909) {NAME asn(regs.regs(1)) TYPE ASSIGN PAR 0-1907 XREFS 15606 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1913 {}}} SUCCS {{258 0 0-1913 {}}} CYCLES {}}
+set a(0-1910) {NAME asn(regs.regs(1).sg2)#1 TYPE ASSIGN PAR 0-1907 XREFS 15607 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1913 {}}} SUCCS {{258 0 0-1913 {}}} CYCLES {}}
+set a(0-1911) {NAME asn(regs.regs(0))#1 TYPE ASSIGN PAR 0-1907 XREFS 15608 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1913 {}}} SUCCS {{258 0 0-1913 {}}} CYCLES {}}
+set a(0-1912) {NAME FRAME:asn(exit:FRAME) TYPE ASSIGN PAR 0-1907 XREFS 15609 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-1913 {}}} SUCCS {{259 0 0-1913 {}}} CYCLES {}}
+set a(0-1914) {NAME FRAME:asn TYPE ASSIGN PAR 0-1913 XREFS 15610 LOC {0 1.0 0 1.0 0 1.0 4 1.0} PREDS {{262 0 0-2809 {}}} SUCCS {{259 0 0-1915 {}} {256 0 0-2809 {}}} CYCLES {}}
+set a(0-1915) {NAME FRAME:select TYPE SELECT PAR 0-1913 XREFS 15611 LOC {0 1.0 0 1.0 0 1.0 4 1.0} PREDS {{259 0 0-1914 {}}} SUCCS {} CYCLES {}}
+set a(0-1916) {NAME SHIFT:if:else:else:else:asn TYPE ASSIGN PAR 0-1913 XREFS 15612 LOC {0 1.0 0 1.0 0 1.0 2 0.40483722499999997} PREDS {{262 0 0-2801 {}}} SUCCS {{259 0 0-1917 {}} {256 0 0-2801 {}}} CYCLES {}}
+set a(0-1917) {NAME SHIFT:if:else:else:else:slc(regs.regs(0)) TYPE READSLICE PAR 0-1913 XREFS 15613 LOC {0 1.0 0 1.0 0 1.0 2 0.40483722499999997} PREDS {{259 0 0-1916 {}}} SUCCS {{258 0 0-2804 {}}} CYCLES {}}
+set a(0-1918) {NAME SHIFT:if:else:else:else:asn#1 TYPE ASSIGN PAR 0-1913 XREFS 15614 LOC {0 1.0 0 1.0 0 1.0 2 0.409023875} PREDS {{262 0 0-2801 {}}} SUCCS {{259 0 0-1919 {}} {256 0 0-2801 {}}} CYCLES {}}
+set a(0-1919) {NAME SHIFT:if:else:else:else:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-1913 XREFS 15615 LOC {0 1.0 0 1.0 0 1.0 2 0.409023875} PREDS {{259 0 0-1918 {}}} SUCCS {{258 0 0-2803 {}}} CYCLES {}}
+set a(0-1920) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,90) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_read(vin:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-1913 XREFS 15616 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.039018275 1 0.40483722499999997} PREDS {} SUCCS {{259 0 0-1921 {}} {258 0 0-1923 {}} {258 0 0-1926 {}} {258 0 0-2010 {}} {258 0 0-2012 {}} {258 0 0-2015 {}} {258 0 0-2103 {}} {258 0 0-2112 {}} {258 0 0-2122 {}} {258 0 0-2209 {}} {258 0 0-2214 {}} {258 0 0-2220 {}} {258 0 0-2801 {}}} CYCLES {}}
+set a(0-1921) {NAME regs.regs:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-1913 XREFS 15617 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.520991075} PREDS {{259 0 0-1920 {}}} SUCCS {{259 0 0-1922 {}}} CYCLES {}}
+set a(0-1922) {NAME ACC1:exs#56 TYPE SIGNEXTEND PAR 0-1913 XREFS 15618 LOC {1 0.0 1 0.142400175 1 0.142400175 1 0.520991075} PREDS {{259 0 0-1921 {}}} SUCCS {{258 0 0-1925 {}}} CYCLES {}}
+set a(0-1923) {NAME regs.regs:slc(regs.regs(0))#2 TYPE READSLICE PAR 0-1913 XREFS 15619 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.520991075} PREDS {{258 0 0-1920 {}}} SUCCS {{259 0 0-1924 {}}} CYCLES {}}
+set a(0-1924) {NAME ACC1:exs#57 TYPE SIGNEXTEND PAR 0-1913 XREFS 15620 LOC {1 0.0 1 0.142400175 1 0.142400175 1 0.520991075} PREDS {{259 0 0-1923 {}}} SUCCS {{259 0 0-1925 {}}} CYCLES {}}
+set a(0-1925) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,17) AREA_SCORE 17.19 QUANTITY 9 NAME ACC1:acc#153 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-1913 XREFS 15621 LOC {1 0.0 1 0.142400175 1 0.142400175 1 0.24800990535790096 1 0.626600805357901} PREDS {{258 0 0-1922 {}} {259 0 0-1924 {}}} SUCCS {{258 0 0-1928 {}}} CYCLES {}}
+set a(0-1926) {NAME regs.regs:slc(regs.regs(0)) TYPE READSLICE PAR 0-1913 XREFS 15622 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.62660085} PREDS {{258 0 0-1920 {}}} SUCCS {{259 0 0-1927 {}}} CYCLES {}}
+set a(0-1927) {NAME ACC1:exs TYPE SIGNEXTEND PAR 0-1913 XREFS 15623 LOC {1 0.0 1 0.24800994999999998 1 0.24800994999999998 1 0.62660085} PREDS {{259 0 0-1926 {}}} SUCCS {{259 0 0-1928 {}}} CYCLES {}}
+set a(0-1928) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(17,0,16,0,18) AREA_SCORE 18.18 QUANTITY 4 NAME ACC1-1:acc TYPE ACCU DELAY {1.75 ns} LIBRARY_DELAY {1.75 ns} PAR 0-1913 XREFS 15624 LOC {1 0.10560977499999999 1 0.24800994999999998 1 0.24800994999999998 1 0.35761096691003574 1 0.7362018669100358} PREDS {{258 0 0-1925 {}} {259 0 0-1927 {}}} SUCCS {{259 0 0-1929 {}} {258 0 0-1931 {}} {258 0 0-1937 {}} {258 0 0-1939 {}} {258 0 0-1945 {}} {258 0 0-1947 {}} {258 0 0-1949 {}} {258 0 0-1953 {}} {258 0 0-1959 {}} {258 0 0-1961 {}} {258 0 0-1963 {}} {258 0 0-1969 {}} {258 0 0-1971 {}} {258 0 0-1973 {}} {258 0 0-1977 {}} {258 0 0-1981 {}} {258 0 0-1986 {}} {258 0 0-1987 {}} {258 0 0-2315 {}} {258 0 0-2326 {}} {258 0 0-2331 {}} {258 0 0-2338 {}} {258 0 0-2343 {}} {258 0 0-2347 {}} {258 0 0-2360 {}} {258 0 0-2368 {}} {258 0 0-2374 {}} {258 0 0-2381 {}} {258 0 0-2383 {}} {258 0 0-2386 {}} {258 0 0-2458 {}} {258 0 0-2461 {}} {258 0 0-2466 {}} {258 0 0-2469 {}} {258 0 0-2485 {}} {258 0 0-2504 {}} {258 0 0-2512 {}} {258 0 0-2524 {}} {258 0 0-2525 {}} {258 0 0-2645 {}} {258 0 0-2646 {}} {258 0 0-2653 {}} {258 0 0-2656 {}} {258 0 0-2658 {}} {258 0 0-2661 {}} {258 0 0-2663 {}} {258 0 0-2681 {}} {258 0 0-2689 {}} {258 0 0-2691 {}} {258 0 0-2698 {}} {258 0 0-2710 {}} {258 0 0-2719 {}}} CYCLES {}}
+set a(0-1929) {NAME ACC1-1:slc(acc.idiv)#8 TYPE READSLICE PAR 0-1913 XREFS 15625 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.7362019249999999} PREDS {{259 0 0-1928 {}}} SUCCS {{259 0 0-1930 {}}} CYCLES {}}
+set a(0-1930) {NAME ACC1:conc#290 TYPE CONCATENATE PAR 0-1913 XREFS 15626 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.7362019249999999} PREDS {{259 0 0-1929 {}}} SUCCS {{258 0 0-1934 {}}} CYCLES {}}
+set a(0-1931) {NAME ACC1-1:slc(acc.idiv)#9 TYPE READSLICE PAR 0-1913 XREFS 15627 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.7362019249999999} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1932 {}}} CYCLES {}}
+set a(0-1932) {NAME ACC1-1:not#5 TYPE NOT PAR 0-1913 XREFS 15628 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.7362019249999999} PREDS {{259 0 0-1931 {}}} SUCCS {{259 0 0-1933 {}}} CYCLES {}}
+set a(0-1933) {NAME ACC1:conc#291 TYPE CONCATENATE PAR 0-1913 XREFS 15629 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.7362019249999999} PREDS {{259 0 0-1932 {}}} SUCCS {{259 0 0-1934 {}}} CYCLES {}}
+set a(0-1934) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#154 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15630 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.39839403508947524 1 0.7769849350894752} PREDS {{258 0 0-1930 {}} {259 0 0-1933 {}}} SUCCS {{259 0 0-1935 {}}} CYCLES {}}
+set a(0-1935) {NAME ACC1:slc#5 TYPE READSLICE PAR 0-1913 XREFS 15631 LOC {1 0.2559939 1 0.39839407499999996 1 0.39839407499999996 1 0.776984975} PREDS {{259 0 0-1934 {}}} SUCCS {{259 0 0-1936 {}}} CYCLES {}}
+set a(0-1936) {NAME ACC1:conc#298 TYPE CONCATENATE PAR 0-1913 XREFS 15632 LOC {1 0.2559939 1 0.39839407499999996 1 0.39839407499999996 1 0.776984975} PREDS {{259 0 0-1935 {}}} SUCCS {{258 0 0-1942 {}}} CYCLES {}}
+set a(0-1937) {NAME ACC1-1:slc(acc.idiv)#1 TYPE READSLICE PAR 0-1913 XREFS 15633 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.776984975} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1938 {}}} CYCLES {}}
+set a(0-1938) {NAME ACC1-1:not#1 TYPE NOT PAR 0-1913 XREFS 15634 LOC {1 0.21521084999999998 1 0.39839407499999996 1 0.39839407499999996 1 0.776984975} PREDS {{259 0 0-1937 {}}} SUCCS {{258 0 0-1941 {}}} CYCLES {}}
+set a(0-1939) {NAME ACC1-1:slc(acc.idiv)#13 TYPE READSLICE PAR 0-1913 XREFS 15635 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.776984975} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1940 {}}} CYCLES {}}
+set a(0-1940) {NAME ACC1-1:not#7 TYPE NOT PAR 0-1913 XREFS 15636 LOC {1 0.21521084999999998 1 0.39839407499999996 1 0.39839407499999996 1 0.776984975} PREDS {{259 0 0-1939 {}}} SUCCS {{259 0 0-1941 {}}} CYCLES {}}
+set a(0-1941) {NAME ACC1:conc#299 TYPE CONCATENATE PAR 0-1913 XREFS 15637 LOC {1 0.21521084999999998 1 0.39839407499999996 1 0.39839407499999996 1 0.776984975} PREDS {{258 0 0-1938 {}} {259 0 0-1940 {}}} SUCCS {{259 0 0-1942 {}}} CYCLES {}}
+set a(0-1942) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#158 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15638 LOC {1 0.2559939 1 0.39839407499999996 1 0.39839407499999996 1 0.44595020207082714 1 0.8245411020708271} PREDS {{258 0 0-1936 {}} {259 0 0-1941 {}}} SUCCS {{259 0 0-1943 {}}} CYCLES {}}
+set a(0-1943) {NAME ACC1:slc#9 TYPE READSLICE PAR 0-1913 XREFS 15639 LOC {1 0.303550075 1 0.44595025 1 0.44595025 1 0.82454115} PREDS {{259 0 0-1942 {}}} SUCCS {{259 0 0-1944 {}}} CYCLES {}}
+set a(0-1944) {NAME ACC1:conc#302 TYPE CONCATENATE PAR 0-1913 XREFS 15640 LOC {1 0.303550075 1 0.44595025 1 0.44595025 1 0.82454115} PREDS {{259 0 0-1943 {}}} SUCCS {{258 0 0-1956 {}}} CYCLES {}}
+set a(0-1945) {NAME ACC1-1:slc(acc.idiv)#2 TYPE READSLICE PAR 0-1913 XREFS 15641 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.7837581} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1946 {}}} CYCLES {}}
+set a(0-1946) {NAME ACC1:conc#296 TYPE CONCATENATE PAR 0-1913 XREFS 15642 LOC {1 0.21521084999999998 1 0.4051672 1 0.4051672 1 0.7837581} PREDS {{259 0 0-1945 {}}} SUCCS {{258 0 0-1951 {}}} CYCLES {}}
+set a(0-1947) {NAME ACC1-1:slc(acc.idiv)#3 TYPE READSLICE PAR 0-1913 XREFS 15643 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.7837581} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1948 {}}} CYCLES {}}
+set a(0-1948) {NAME ACC1-1:not#2 TYPE NOT PAR 0-1913 XREFS 15644 LOC {1 0.21521084999999998 1 0.4051672 1 0.4051672 1 0.7837581} PREDS {{259 0 0-1947 {}}} SUCCS {{258 0 0-1950 {}}} CYCLES {}}
+set a(0-1949) {NAME ACC1-1:slc(acc.idiv)#12 TYPE READSLICE PAR 0-1913 XREFS 15645 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.7837581} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1950 {}}} CYCLES {}}
+set a(0-1950) {NAME ACC1:conc#297 TYPE CONCATENATE PAR 0-1913 XREFS 15646 LOC {1 0.21521084999999998 1 0.4051672 1 0.4051672 1 0.7837581} PREDS {{258 0 0-1948 {}} {259 0 0-1949 {}}} SUCCS {{259 0 0-1951 {}}} CYCLES {}}
+set a(0-1951) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#157 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15647 LOC {1 0.21521084999999998 1 0.4051672 1 0.4051672 1 0.4459502100894752 1 0.8245411100894753} PREDS {{258 0 0-1946 {}} {259 0 0-1950 {}}} SUCCS {{259 0 0-1952 {}}} CYCLES {}}
+set a(0-1952) {NAME ACC1:slc#8 TYPE READSLICE PAR 0-1913 XREFS 15648 LOC {1 0.2559939 1 0.44595025 1 0.44595025 1 0.82454115} PREDS {{259 0 0-1951 {}}} SUCCS {{258 0 0-1955 {}}} CYCLES {}}
+set a(0-1953) {NAME ACC1-1:slc(acc.idiv)#15 TYPE READSLICE PAR 0-1913 XREFS 15649 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.82454115} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1954 {}}} CYCLES {}}
+set a(0-1954) {NAME ACC1-1:not#8 TYPE NOT PAR 0-1913 XREFS 15650 LOC {1 0.21521084999999998 1 0.44595025 1 0.44595025 1 0.82454115} PREDS {{259 0 0-1953 {}}} SUCCS {{259 0 0-1955 {}}} CYCLES {}}
+set a(0-1955) {NAME ACC1:conc#303 TYPE CONCATENATE PAR 0-1913 XREFS 15651 LOC {1 0.2559939 1 0.44595025 1 0.44595025 1 0.82454115} PREDS {{258 0 0-1952 {}} {259 0 0-1954 {}}} SUCCS {{259 0 0-1956 {}}} CYCLES {}}
+set a(0-1956) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 13 NAME ACC1:acc#160 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1913 XREFS 15652 LOC {1 0.303550075 1 0.44595025 1 0.44595025 1 0.4992972701789505 1 0.8778881701789505} PREDS {{258 0 0-1944 {}} {259 0 0-1955 {}}} SUCCS {{259 0 0-1957 {}}} CYCLES {}}
+set a(0-1957) {NAME ACC1:slc#11 TYPE READSLICE PAR 0-1913 XREFS 15653 LOC {1 0.35689715 1 0.49929732499999996 1 0.49929732499999996 1 0.877888225} PREDS {{259 0 0-1956 {}}} SUCCS {{259 0 0-1958 {}}} CYCLES {}}
+set a(0-1958) {NAME ACC1:conc#304 TYPE CONCATENATE PAR 0-1913 XREFS 15654 LOC {1 0.35689715 1 0.49929732499999996 1 0.49929732499999996 1 0.877888225} PREDS {{259 0 0-1957 {}}} SUCCS {{258 0 0-1983 {}}} CYCLES {}}
+set a(0-1959) {NAME ACC1-1:slc(acc.idiv)#4 TYPE READSLICE PAR 0-1913 XREFS 15655 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.789549} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1960 {}}} CYCLES {}}
+set a(0-1960) {NAME ACC1:conc#294 TYPE CONCATENATE PAR 0-1913 XREFS 15656 LOC {1 0.21521084999999998 1 0.4109581 1 0.4109581 1 0.789549} PREDS {{259 0 0-1959 {}}} SUCCS {{258 0 0-1966 {}}} CYCLES {}}
+set a(0-1961) {NAME ACC1-1:slc(acc.idiv)#5 TYPE READSLICE PAR 0-1913 XREFS 15657 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.789549} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1962 {}}} CYCLES {}}
+set a(0-1962) {NAME ACC1-1:not#3 TYPE NOT PAR 0-1913 XREFS 15658 LOC {1 0.21521084999999998 1 0.4109581 1 0.4109581 1 0.789549} PREDS {{259 0 0-1961 {}}} SUCCS {{258 0 0-1965 {}}} CYCLES {}}
+set a(0-1963) {NAME ACC1-1:slc(acc.idiv)#11 TYPE READSLICE PAR 0-1913 XREFS 15659 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.789549} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1964 {}}} CYCLES {}}
+set a(0-1964) {NAME ACC1-1:not#6 TYPE NOT PAR 0-1913 XREFS 15660 LOC {1 0.21521084999999998 1 0.4109581 1 0.4109581 1 0.789549} PREDS {{259 0 0-1963 {}}} SUCCS {{259 0 0-1965 {}}} CYCLES {}}
+set a(0-1965) {NAME ACC1:conc#295 TYPE CONCATENATE PAR 0-1913 XREFS 15661 LOC {1 0.21521084999999998 1 0.4109581 1 0.4109581 1 0.789549} PREDS {{258 0 0-1962 {}} {259 0 0-1964 {}}} SUCCS {{259 0 0-1966 {}}} CYCLES {}}
+set a(0-1966) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#156 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15662 LOC {1 0.21521084999999998 1 0.4109581 1 0.4109581 1 0.45174111008947526 1 0.8303320100894752} PREDS {{258 0 0-1960 {}} {259 0 0-1965 {}}} SUCCS {{259 0 0-1967 {}}} CYCLES {}}
+set a(0-1967) {NAME ACC1:slc#7 TYPE READSLICE PAR 0-1913 XREFS 15663 LOC {1 0.2559939 1 0.45174115 1 0.45174115 1 0.83033205} PREDS {{259 0 0-1966 {}}} SUCCS {{259 0 0-1968 {}}} CYCLES {}}
+set a(0-1968) {NAME ACC1:conc#300 TYPE CONCATENATE PAR 0-1913 XREFS 15664 LOC {1 0.2559939 1 0.45174115 1 0.45174115 1 0.83033205} PREDS {{259 0 0-1967 {}}} SUCCS {{258 0 0-1979 {}}} CYCLES {}}
+set a(0-1969) {NAME ACC1-1:slc(acc.idiv)#6 TYPE READSLICE PAR 0-1913 XREFS 15665 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.789549} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1970 {}}} CYCLES {}}
+set a(0-1970) {NAME ACC1:conc#292 TYPE CONCATENATE PAR 0-1913 XREFS 15666 LOC {1 0.21521084999999998 1 0.4109581 1 0.4109581 1 0.789549} PREDS {{259 0 0-1969 {}}} SUCCS {{258 0 0-1975 {}}} CYCLES {}}
+set a(0-1971) {NAME ACC1-1:slc(acc.idiv)#7 TYPE READSLICE PAR 0-1913 XREFS 15667 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.789549} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1972 {}}} CYCLES {}}
+set a(0-1972) {NAME ACC1-1:not#4 TYPE NOT PAR 0-1913 XREFS 15668 LOC {1 0.21521084999999998 1 0.4109581 1 0.4109581 1 0.789549} PREDS {{259 0 0-1971 {}}} SUCCS {{258 0 0-1974 {}}} CYCLES {}}
+set a(0-1973) {NAME ACC1-1:slc(acc.idiv)#10 TYPE READSLICE PAR 0-1913 XREFS 15669 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.789549} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1974 {}}} CYCLES {}}
+set a(0-1974) {NAME ACC1:conc#293 TYPE CONCATENATE PAR 0-1913 XREFS 15670 LOC {1 0.21521084999999998 1 0.4109581 1 0.4109581 1 0.789549} PREDS {{258 0 0-1972 {}} {259 0 0-1973 {}}} SUCCS {{259 0 0-1975 {}}} CYCLES {}}
+set a(0-1975) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#155 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15671 LOC {1 0.21521084999999998 1 0.4109581 1 0.4109581 1 0.45174111008947526 1 0.8303320100894752} PREDS {{258 0 0-1970 {}} {259 0 0-1974 {}}} SUCCS {{259 0 0-1976 {}}} CYCLES {}}
+set a(0-1976) {NAME ACC1:slc#6 TYPE READSLICE PAR 0-1913 XREFS 15672 LOC {1 0.2559939 1 0.45174115 1 0.45174115 1 0.83033205} PREDS {{259 0 0-1975 {}}} SUCCS {{258 0 0-1978 {}}} CYCLES {}}
+set a(0-1977) {NAME ACC1-1:slc(acc.idiv)#14 TYPE READSLICE PAR 0-1913 XREFS 15673 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.83033205} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1978 {}}} CYCLES {}}
+set a(0-1978) {NAME ACC1:conc#301 TYPE CONCATENATE PAR 0-1913 XREFS 15674 LOC {1 0.2559939 1 0.45174115 1 0.45174115 1 0.83033205} PREDS {{258 0 0-1976 {}} {259 0 0-1977 {}}} SUCCS {{259 0 0-1979 {}}} CYCLES {}}
+set a(0-1979) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#159 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15675 LOC {1 0.2559939 1 0.45174115 1 0.45174115 1 0.49929727707082716 1 0.8778881770708271} PREDS {{258 0 0-1968 {}} {259 0 0-1978 {}}} SUCCS {{259 0 0-1980 {}}} CYCLES {}}
+set a(0-1980) {NAME ACC1:slc#10 TYPE READSLICE PAR 0-1913 XREFS 15676 LOC {1 0.303550075 1 0.49929732499999996 1 0.49929732499999996 1 0.877888225} PREDS {{259 0 0-1979 {}}} SUCCS {{258 0 0-1982 {}}} CYCLES {}}
+set a(0-1981) {NAME ACC1-1:slc(acc.idiv)#16 TYPE READSLICE PAR 0-1913 XREFS 15677 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.877888225} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1982 {}}} CYCLES {}}
+set a(0-1982) {NAME ACC1:conc#305 TYPE CONCATENATE PAR 0-1913 XREFS 15678 LOC {1 0.303550075 1 0.49929732499999996 1 0.49929732499999996 1 0.877888225} PREDS {{258 0 0-1980 {}} {259 0 0-1981 {}}} SUCCS {{259 0 0-1983 {}}} CYCLES {}}
+set a(0-1983) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 12 NAME ACC1:acc#161 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1913 XREFS 15679 LOC {1 0.35689715 1 0.49929732499999996 1 0.49929732499999996 1 0.5578970344969361 1 0.936487934496936} PREDS {{258 0 0-1958 {}} {259 0 0-1982 {}}} SUCCS {{259 0 0-1984 {}}} CYCLES {}}
+set a(0-1984) {NAME ACC1:slc#12 TYPE READSLICE PAR 0-1913 XREFS 15680 LOC {1 0.4154969 1 0.557897075 1 0.557897075 1 0.9364879749999999} PREDS {{259 0 0-1983 {}}} SUCCS {{259 0 0-1985 {}}} CYCLES {}}
+set a(0-1985) {NAME ACC1:conc#306 TYPE CONCATENATE PAR 0-1913 XREFS 15681 LOC {1 0.4154969 1 0.557897075 1 0.557897075 1 0.9364879749999999} PREDS {{259 0 0-1984 {}}} SUCCS {{258 0 0-1990 {}}} CYCLES {}}
+set a(0-1986) {NAME ACC1-1:slc(acc.idiv) TYPE READSLICE PAR 0-1913 XREFS 15682 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.9364879749999999} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-1989 {}}} CYCLES {}}
+set a(0-1987) {NAME ACC1-1:slc(acc.idiv)#17 TYPE READSLICE PAR 0-1913 XREFS 15683 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 1 0.9364879749999999} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-1988 {}}} CYCLES {}}
+set a(0-1988) {NAME ACC1-1:not#9 TYPE NOT PAR 0-1913 XREFS 15684 LOC {1 0.21521084999999998 1 0.557897075 1 0.557897075 1 0.9364879749999999} PREDS {{259 0 0-1987 {}}} SUCCS {{259 0 0-1989 {}}} CYCLES {}}
+set a(0-1989) {NAME ACC1:conc#307 TYPE CONCATENATE PAR 0-1913 XREFS 15685 LOC {1 0.21521084999999998 1 0.557897075 1 0.557897075 1 0.9364879749999999} PREDS {{258 0 0-1986 {}} {259 0 0-1988 {}}} SUCCS {{259 0 0-1990 {}}} CYCLES {}}
+set a(0-1990) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 5 NAME ACC1:acc#162 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-1913 XREFS 15686 LOC {1 0.4154969 1 0.557897075 1 0.557897075 1 0.6214090484103024 1 0.9999999484103024} PREDS {{258 0 0-1985 {}} {259 0 0-1989 {}}} SUCCS {{259 0 0-1991 {}}} CYCLES {}}
+set a(0-1991) {NAME ACC1:slc#13 TYPE READSLICE PAR 0-1913 XREFS 15687 LOC {1 0.479008925 1 0.6214090999999999 1 0.6214090999999999 2 0.0356505} PREDS {{259 0 0-1990 {}}} SUCCS {{259 0 0-1992 {}} {258 0 0-1994 {}} {258 0 0-2000 {}} {258 0 0-2002 {}} {258 0 0-2007 {}} {258 0 0-2367 {}} {258 0 0-2476 {}} {258 0 0-2528 {}} {258 0 0-2531 {}} {258 0 0-2616 {}} {258 0 0-2638 {}}} CYCLES {}}
+set a(0-1992) {NAME ACC1-1:slc(acc.imod)#2 TYPE READSLICE PAR 0-1913 XREFS 15688 LOC {1 0.479008925 1 0.6214090999999999 1 0.6214090999999999 2 0.0356505} PREDS {{259 0 0-1991 {}}} SUCCS {{259 0 0-1993 {}}} CYCLES {}}
+set a(0-1993) {NAME ACC1:conc#309 TYPE CONCATENATE PAR 0-1913 XREFS 15689 LOC {1 0.479008925 1 0.66381855 1 0.66381855 2 0.0356505} PREDS {{259 0 0-1992 {}}} SUCCS {{258 0 0-1997 {}}} CYCLES {}}
+set a(0-1994) {NAME ACC1-1:slc(acc.imod)#3 TYPE READSLICE PAR 0-1913 XREFS 15690 LOC {1 0.479008925 1 0.6214090999999999 1 0.6214090999999999 2 0.0356505} PREDS {{258 0 0-1991 {}}} SUCCS {{259 0 0-1995 {}}} CYCLES {}}
+set a(0-1995) {NAME ACC1-1:not#11 TYPE NOT PAR 0-1913 XREFS 15691 LOC {1 0.479008925 1 0.66381855 1 0.66381855 2 0.0356505} PREDS {{259 0 0-1994 {}}} SUCCS {{259 0 0-1996 {}}} CYCLES {}}
+set a(0-1996) {NAME ACC1:conc#310 TYPE CONCATENATE PAR 0-1913 XREFS 15692 LOC {1 0.479008925 1 0.66381855 1 0.66381855 2 0.0356505} PREDS {{259 0 0-1995 {}}} SUCCS {{259 0 0-1997 {}}} CYCLES {}}
+set a(0-1997) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#163 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15693 LOC {1 0.479008925 1 0.66381855 1 0.66381855 1 0.7046015600894753 2 0.07643351008947524} PREDS {{258 0 0-1993 {}} {259 0 0-1996 {}}} SUCCS {{259 0 0-1998 {}}} CYCLES {}}
+set a(0-1998) {NAME ACC1:slc#14 TYPE READSLICE PAR 0-1913 XREFS 15694 LOC {1 0.519791975 1 0.7046015999999999 1 0.7046015999999999 2 0.07643355} PREDS {{259 0 0-1997 {}}} SUCCS {{259 0 0-1999 {}}} CYCLES {}}
+set a(0-1999) {NAME ACC1:conc#311 TYPE CONCATENATE PAR 0-1913 XREFS 15695 LOC {1 0.519791975 1 0.7046015999999999 1 0.7046015999999999 2 0.07643355} PREDS {{259 0 0-1998 {}}} SUCCS {{258 0 0-2005 {}}} CYCLES {}}
+set a(0-2000) {NAME ACC1-1:slc(acc.imod)#1 TYPE READSLICE PAR 0-1913 XREFS 15696 LOC {1 0.479008925 1 0.6214090999999999 1 0.6214090999999999 2 0.07643355} PREDS {{258 0 0-1991 {}}} SUCCS {{259 0 0-2001 {}}} CYCLES {}}
+set a(0-2001) {NAME ACC1-1:not#10 TYPE NOT PAR 0-1913 XREFS 15697 LOC {1 0.479008925 1 0.7046015999999999 1 0.7046015999999999 2 0.07643355} PREDS {{259 0 0-2000 {}}} SUCCS {{258 0 0-2004 {}}} CYCLES {}}
+set a(0-2002) {NAME ACC1-1:slc(acc.imod)#4 TYPE READSLICE PAR 0-1913 XREFS 15698 LOC {1 0.479008925 1 0.6214090999999999 1 0.6214090999999999 2 0.07643355} PREDS {{258 0 0-1991 {}}} SUCCS {{259 0 0-2003 {}}} CYCLES {}}
+set a(0-2003) {NAME ACC1-1:not#12 TYPE NOT PAR 0-1913 XREFS 15699 LOC {1 0.479008925 1 0.7046015999999999 1 0.7046015999999999 2 0.07643355} PREDS {{259 0 0-2002 {}}} SUCCS {{259 0 0-2004 {}}} CYCLES {}}
+set a(0-2004) {NAME ACC1:conc#312 TYPE CONCATENATE PAR 0-1913 XREFS 15700 LOC {1 0.479008925 1 0.7046015999999999 1 0.7046015999999999 2 0.07643355} PREDS {{258 0 0-2001 {}} {259 0 0-2003 {}}} SUCCS {{259 0 0-2005 {}}} CYCLES {}}
+set a(0-2005) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#164 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15701 LOC {1 0.519791975 1 0.7046015999999999 1 0.7046015999999999 1 0.7521577270708271 2 0.12398967707082717} PREDS {{258 0 0-1999 {}} {259 0 0-2004 {}}} SUCCS {{259 0 0-2006 {}}} CYCLES {}}
+set a(0-2006) {NAME ACC1:slc#15 TYPE READSLICE PAR 0-1913 XREFS 15702 LOC {1 0.5673481499999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{259 0 0-2005 {}}} SUCCS {{258 0 0-2009 {}}} CYCLES {}}
+set a(0-2007) {NAME ACC1-1:slc(acc.imod) TYPE READSLICE PAR 0-1913 XREFS 15703 LOC {1 0.479008925 1 0.6214090999999999 1 0.6214090999999999 2 0.123989725} PREDS {{258 0 0-1991 {}}} SUCCS {{259 0 0-2008 {}}} CYCLES {}}
+set a(0-2008) {NAME ACC1:conc#308 TYPE CONCATENATE PAR 0-1913 XREFS 15704 LOC {1 0.479008925 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{259 0 0-2007 {}}} SUCCS {{259 0 0-2009 {}}} CYCLES {}}
+set a(0-2009) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1-1:acc#5 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15705 LOC {1 0.5673481499999999 1 0.7521577749999999 1 0.7521577749999999 1 0.799713902070827 2 0.17154585207082718} PREDS {{258 0 0-2006 {}} {259 0 0-2008 {}}} SUCCS {{258 0 0-2535 {}} {258 0 0-2537 {}} {258 0 0-2620 {}} {258 0 0-2622 {}} {258 0 0-2624 {}}} CYCLES {}}
+set a(0-2010) {NAME regs.regs:slc(regs.regs(0))#7 TYPE READSLICE PAR 0-1913 XREFS 15706 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.480208025} PREDS {{258 0 0-1920 {}}} SUCCS {{259 0 0-2011 {}}} CYCLES {}}
+set a(0-2011) {NAME ACC1:exs#68 TYPE SIGNEXTEND PAR 0-1913 XREFS 15707 LOC {1 0.0 1 0.13725345 1 0.13725345 1 0.480208025} PREDS {{259 0 0-2010 {}}} SUCCS {{258 0 0-2014 {}}} CYCLES {}}
+set a(0-2012) {NAME regs.regs:slc(regs.regs(0))#8 TYPE READSLICE PAR 0-1913 XREFS 15708 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.480208025} PREDS {{258 0 0-1920 {}}} SUCCS {{259 0 0-2013 {}}} CYCLES {}}
+set a(0-2013) {NAME ACC1:exs#69 TYPE SIGNEXTEND PAR 0-1913 XREFS 15709 LOC {1 0.0 1 0.13725345 1 0.13725345 1 0.480208025} PREDS {{259 0 0-2012 {}}} SUCCS {{259 0 0-2014 {}}} CYCLES {}}
+set a(0-2014) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,17) AREA_SCORE 17.19 QUANTITY 9 NAME ACC1:acc#165 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-1913 XREFS 15710 LOC {1 0.0 1 0.13725345 1 0.13725345 1 0.242863180357901 1 0.5858177553579009} PREDS {{258 0 0-2011 {}} {259 0 0-2013 {}}} SUCCS {{258 0 0-2017 {}}} CYCLES {}}
+set a(0-2015) {NAME regs.regs:slc(regs.regs(0))#6 TYPE READSLICE PAR 0-1913 XREFS 15711 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.5858177999999999} PREDS {{258 0 0-1920 {}}} SUCCS {{259 0 0-2016 {}}} CYCLES {}}
+set a(0-2016) {NAME ACC1:exs#67 TYPE SIGNEXTEND PAR 0-1913 XREFS 15712 LOC {1 0.0 1 0.242863225 1 0.242863225 1 0.5858177999999999} PREDS {{259 0 0-2015 {}}} SUCCS {{259 0 0-2017 {}}} CYCLES {}}
+set a(0-2017) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(17,0,16,0,18) AREA_SCORE 18.18 QUANTITY 4 NAME ACC1-1:acc#26 TYPE ACCU DELAY {1.75 ns} LIBRARY_DELAY {1.75 ns} PAR 0-1913 XREFS 15713 LOC {1 0.10560977499999999 1 0.242863225 1 0.242863225 1 0.3524642419100358 1 0.6954188169100357} PREDS {{258 0 0-2014 {}} {259 0 0-2016 {}}} SUCCS {{259 0 0-2018 {}} {258 0 0-2020 {}} {258 0 0-2026 {}} {258 0 0-2028 {}} {258 0 0-2034 {}} {258 0 0-2036 {}} {258 0 0-2038 {}} {258 0 0-2042 {}} {258 0 0-2048 {}} {258 0 0-2050 {}} {258 0 0-2052 {}} {258 0 0-2058 {}} {258 0 0-2060 {}} {258 0 0-2062 {}} {258 0 0-2066 {}} {258 0 0-2070 {}} {258 0 0-2075 {}} {258 0 0-2076 {}} {258 0 0-2316 {}} {258 0 0-2325 {}} {258 0 0-2332 {}} {258 0 0-2339 {}} {258 0 0-2341 {}} {258 0 0-2375 {}} {258 0 0-2388 {}} {258 0 0-2392 {}} {258 0 0-2394 {}} {258 0 0-2397 {}} {258 0 0-2399 {}} {258 0 0-2404 {}} {258 0 0-2406 {}} {258 0 0-2428 {}} {258 0 0-2430 {}} {258 0 0-2433 {}} {258 0 0-2435 {}} {258 0 0-2439 {}} {258 0 0-2441 {}} {258 0 0-2444 {}} {258 0 0-2486 {}} {258 0 0-2505 {}} {258 0 0-2513 {}} {258 0 0-2553 {}} {258 0 0-2555 {}} {258 0 0-2558 {}} {258 0 0-2560 {}} {258 0 0-2644 {}} {258 0 0-2651 {}} {258 0 0-2652 {}} {258 0 0-2682 {}} {258 0 0-2696 {}} {258 0 0-2711 {}} {258 0 0-2720 {}}} CYCLES {}}
+set a(0-2018) {NAME ACC1-1:slc(acc.idiv#2)#8 TYPE READSLICE PAR 0-1913 XREFS 15714 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.695418875} PREDS {{259 0 0-2017 {}}} SUCCS {{259 0 0-2019 {}}} CYCLES {}}
+set a(0-2019) {NAME ACC1:conc#314 TYPE CONCATENATE PAR 0-1913 XREFS 15715 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.695418875} PREDS {{259 0 0-2018 {}}} SUCCS {{258 0 0-2023 {}}} CYCLES {}}
+set a(0-2020) {NAME ACC1-1:slc(acc.idiv#2)#9 TYPE READSLICE PAR 0-1913 XREFS 15716 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.695418875} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2021 {}}} CYCLES {}}
+set a(0-2021) {NAME ACC1-1:not#41 TYPE NOT PAR 0-1913 XREFS 15717 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.695418875} PREDS {{259 0 0-2020 {}}} SUCCS {{259 0 0-2022 {}}} CYCLES {}}
+set a(0-2022) {NAME ACC1:conc#315 TYPE CONCATENATE PAR 0-1913 XREFS 15718 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.695418875} PREDS {{259 0 0-2021 {}}} SUCCS {{259 0 0-2023 {}}} CYCLES {}}
+set a(0-2023) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#166 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15719 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.3932473100894752 1 0.7362018850894753} PREDS {{258 0 0-2019 {}} {259 0 0-2022 {}}} SUCCS {{259 0 0-2024 {}}} CYCLES {}}
+set a(0-2024) {NAME ACC1:slc#16 TYPE READSLICE PAR 0-1913 XREFS 15720 LOC {1 0.2559939 1 0.39324735 1 0.39324735 1 0.7362019249999999} PREDS {{259 0 0-2023 {}}} SUCCS {{259 0 0-2025 {}}} CYCLES {}}
+set a(0-2025) {NAME ACC1:conc#322 TYPE CONCATENATE PAR 0-1913 XREFS 15721 LOC {1 0.2559939 1 0.39324735 1 0.39324735 1 0.7362019249999999} PREDS {{259 0 0-2024 {}}} SUCCS {{258 0 0-2031 {}}} CYCLES {}}
+set a(0-2026) {NAME ACC1-1:slc(acc.idiv#2)#1 TYPE READSLICE PAR 0-1913 XREFS 15722 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.7362019249999999} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2027 {}}} CYCLES {}}
+set a(0-2027) {NAME ACC1-1:not#37 TYPE NOT PAR 0-1913 XREFS 15723 LOC {1 0.21521084999999998 1 0.39324735 1 0.39324735 1 0.7362019249999999} PREDS {{259 0 0-2026 {}}} SUCCS {{258 0 0-2030 {}}} CYCLES {}}
+set a(0-2028) {NAME ACC1-1:slc(acc.idiv#2)#13 TYPE READSLICE PAR 0-1913 XREFS 15724 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.7362019249999999} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2029 {}}} CYCLES {}}
+set a(0-2029) {NAME ACC1-1:not#43 TYPE NOT PAR 0-1913 XREFS 15725 LOC {1 0.21521084999999998 1 0.39324735 1 0.39324735 1 0.7362019249999999} PREDS {{259 0 0-2028 {}}} SUCCS {{259 0 0-2030 {}}} CYCLES {}}
+set a(0-2030) {NAME ACC1:conc#323 TYPE CONCATENATE PAR 0-1913 XREFS 15726 LOC {1 0.21521084999999998 1 0.39324735 1 0.39324735 1 0.7362019249999999} PREDS {{258 0 0-2027 {}} {259 0 0-2029 {}}} SUCCS {{259 0 0-2031 {}}} CYCLES {}}
+set a(0-2031) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#170 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15727 LOC {1 0.2559939 1 0.39324735 1 0.39324735 1 0.4408034770708272 1 0.783758052070827} PREDS {{258 0 0-2025 {}} {259 0 0-2030 {}}} SUCCS {{259 0 0-2032 {}}} CYCLES {}}
+set a(0-2032) {NAME ACC1:slc#20 TYPE READSLICE PAR 0-1913 XREFS 15728 LOC {1 0.303550075 1 0.440803525 1 0.440803525 1 0.7837581} PREDS {{259 0 0-2031 {}}} SUCCS {{259 0 0-2033 {}}} CYCLES {}}
+set a(0-2033) {NAME ACC1:conc#326 TYPE CONCATENATE PAR 0-1913 XREFS 15729 LOC {1 0.303550075 1 0.440803525 1 0.440803525 1 0.7837581} PREDS {{259 0 0-2032 {}}} SUCCS {{258 0 0-2045 {}}} CYCLES {}}
+set a(0-2034) {NAME ACC1-1:slc(acc.idiv#2)#2 TYPE READSLICE PAR 0-1913 XREFS 15730 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.74297505} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2035 {}}} CYCLES {}}
+set a(0-2035) {NAME ACC1:conc#320 TYPE CONCATENATE PAR 0-1913 XREFS 15731 LOC {1 0.21521084999999998 1 0.400020475 1 0.400020475 1 0.74297505} PREDS {{259 0 0-2034 {}}} SUCCS {{258 0 0-2040 {}}} CYCLES {}}
+set a(0-2036) {NAME ACC1-1:slc(acc.idiv#2)#3 TYPE READSLICE PAR 0-1913 XREFS 15732 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.74297505} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2037 {}}} CYCLES {}}
+set a(0-2037) {NAME ACC1-1:not#38 TYPE NOT PAR 0-1913 XREFS 15733 LOC {1 0.21521084999999998 1 0.400020475 1 0.400020475 1 0.74297505} PREDS {{259 0 0-2036 {}}} SUCCS {{258 0 0-2039 {}}} CYCLES {}}
+set a(0-2038) {NAME ACC1-1:slc(acc.idiv#2)#12 TYPE READSLICE PAR 0-1913 XREFS 15734 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.74297505} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2039 {}}} CYCLES {}}
+set a(0-2039) {NAME ACC1:conc#321 TYPE CONCATENATE PAR 0-1913 XREFS 15735 LOC {1 0.21521084999999998 1 0.400020475 1 0.400020475 1 0.74297505} PREDS {{258 0 0-2037 {}} {259 0 0-2038 {}}} SUCCS {{259 0 0-2040 {}}} CYCLES {}}
+set a(0-2040) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#169 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15736 LOC {1 0.21521084999999998 1 0.400020475 1 0.400020475 1 0.4408034850894752 1 0.7837580600894752} PREDS {{258 0 0-2035 {}} {259 0 0-2039 {}}} SUCCS {{259 0 0-2041 {}}} CYCLES {}}
+set a(0-2041) {NAME ACC1:slc#19 TYPE READSLICE PAR 0-1913 XREFS 15737 LOC {1 0.2559939 1 0.440803525 1 0.440803525 1 0.7837581} PREDS {{259 0 0-2040 {}}} SUCCS {{258 0 0-2044 {}}} CYCLES {}}
+set a(0-2042) {NAME ACC1-1:slc(acc.idiv#2)#15 TYPE READSLICE PAR 0-1913 XREFS 15738 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.7837581} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2043 {}}} CYCLES {}}
+set a(0-2043) {NAME ACC1-1:not#44 TYPE NOT PAR 0-1913 XREFS 15739 LOC {1 0.21521084999999998 1 0.440803525 1 0.440803525 1 0.7837581} PREDS {{259 0 0-2042 {}}} SUCCS {{259 0 0-2044 {}}} CYCLES {}}
+set a(0-2044) {NAME ACC1:conc#327 TYPE CONCATENATE PAR 0-1913 XREFS 15740 LOC {1 0.2559939 1 0.440803525 1 0.440803525 1 0.7837581} PREDS {{258 0 0-2041 {}} {259 0 0-2043 {}}} SUCCS {{259 0 0-2045 {}}} CYCLES {}}
+set a(0-2045) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 13 NAME ACC1:acc#172 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1913 XREFS 15741 LOC {1 0.303550075 1 0.440803525 1 0.440803525 1 0.49415054517895046 1 0.8371051201789506} PREDS {{258 0 0-2033 {}} {259 0 0-2044 {}}} SUCCS {{259 0 0-2046 {}}} CYCLES {}}
+set a(0-2046) {NAME ACC1:slc#22 TYPE READSLICE PAR 0-1913 XREFS 15742 LOC {1 0.35689715 1 0.4941506 1 0.4941506 1 0.8371051749999999} PREDS {{259 0 0-2045 {}}} SUCCS {{259 0 0-2047 {}}} CYCLES {}}
+set a(0-2047) {NAME ACC1:conc#328 TYPE CONCATENATE PAR 0-1913 XREFS 15743 LOC {1 0.35689715 1 0.4941506 1 0.4941506 1 0.8371051749999999} PREDS {{259 0 0-2046 {}}} SUCCS {{258 0 0-2072 {}}} CYCLES {}}
+set a(0-2048) {NAME ACC1-1:slc(acc.idiv#2)#4 TYPE READSLICE PAR 0-1913 XREFS 15744 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.74876595} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2049 {}}} CYCLES {}}
+set a(0-2049) {NAME ACC1:conc#318 TYPE CONCATENATE PAR 0-1913 XREFS 15745 LOC {1 0.21521084999999998 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{259 0 0-2048 {}}} SUCCS {{258 0 0-2055 {}}} CYCLES {}}
+set a(0-2050) {NAME ACC1-1:slc(acc.idiv#2)#5 TYPE READSLICE PAR 0-1913 XREFS 15746 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.74876595} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2051 {}}} CYCLES {}}
+set a(0-2051) {NAME ACC1-1:not#39 TYPE NOT PAR 0-1913 XREFS 15747 LOC {1 0.21521084999999998 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{259 0 0-2050 {}}} SUCCS {{258 0 0-2054 {}}} CYCLES {}}
+set a(0-2052) {NAME ACC1-1:slc(acc.idiv#2)#11 TYPE READSLICE PAR 0-1913 XREFS 15748 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.74876595} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2053 {}}} CYCLES {}}
+set a(0-2053) {NAME ACC1-1:not#42 TYPE NOT PAR 0-1913 XREFS 15749 LOC {1 0.21521084999999998 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{259 0 0-2052 {}}} SUCCS {{259 0 0-2054 {}}} CYCLES {}}
+set a(0-2054) {NAME ACC1:conc#319 TYPE CONCATENATE PAR 0-1913 XREFS 15750 LOC {1 0.21521084999999998 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{258 0 0-2051 {}} {259 0 0-2053 {}}} SUCCS {{259 0 0-2055 {}}} CYCLES {}}
+set a(0-2055) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#168 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15751 LOC {1 0.21521084999999998 1 0.405811375 1 0.405811375 1 0.44659438508947524 1 0.7895489600894753} PREDS {{258 0 0-2049 {}} {259 0 0-2054 {}}} SUCCS {{259 0 0-2056 {}}} CYCLES {}}
+set a(0-2056) {NAME ACC1:slc#18 TYPE READSLICE PAR 0-1913 XREFS 15752 LOC {1 0.2559939 1 0.44659442499999996 1 0.44659442499999996 1 0.789549} PREDS {{259 0 0-2055 {}}} SUCCS {{259 0 0-2057 {}}} CYCLES {}}
+set a(0-2057) {NAME ACC1:conc#324 TYPE CONCATENATE PAR 0-1913 XREFS 15753 LOC {1 0.2559939 1 0.44659442499999996 1 0.44659442499999996 1 0.789549} PREDS {{259 0 0-2056 {}}} SUCCS {{258 0 0-2068 {}}} CYCLES {}}
+set a(0-2058) {NAME ACC1-1:slc(acc.idiv#2)#6 TYPE READSLICE PAR 0-1913 XREFS 15754 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.74876595} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2059 {}}} CYCLES {}}
+set a(0-2059) {NAME ACC1:conc#316 TYPE CONCATENATE PAR 0-1913 XREFS 15755 LOC {1 0.21521084999999998 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{259 0 0-2058 {}}} SUCCS {{258 0 0-2064 {}}} CYCLES {}}
+set a(0-2060) {NAME ACC1-1:slc(acc.idiv#2)#7 TYPE READSLICE PAR 0-1913 XREFS 15756 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.74876595} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2061 {}}} CYCLES {}}
+set a(0-2061) {NAME ACC1-1:not#40 TYPE NOT PAR 0-1913 XREFS 15757 LOC {1 0.21521084999999998 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{259 0 0-2060 {}}} SUCCS {{258 0 0-2063 {}}} CYCLES {}}
+set a(0-2062) {NAME ACC1-1:slc(acc.idiv#2)#10 TYPE READSLICE PAR 0-1913 XREFS 15758 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.74876595} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2063 {}}} CYCLES {}}
+set a(0-2063) {NAME ACC1:conc#317 TYPE CONCATENATE PAR 0-1913 XREFS 15759 LOC {1 0.21521084999999998 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{258 0 0-2061 {}} {259 0 0-2062 {}}} SUCCS {{259 0 0-2064 {}}} CYCLES {}}
+set a(0-2064) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#167 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15760 LOC {1 0.21521084999999998 1 0.405811375 1 0.405811375 1 0.44659438508947524 1 0.7895489600894753} PREDS {{258 0 0-2059 {}} {259 0 0-2063 {}}} SUCCS {{259 0 0-2065 {}}} CYCLES {}}
+set a(0-2065) {NAME ACC1:slc#17 TYPE READSLICE PAR 0-1913 XREFS 15761 LOC {1 0.2559939 1 0.44659442499999996 1 0.44659442499999996 1 0.789549} PREDS {{259 0 0-2064 {}}} SUCCS {{258 0 0-2067 {}}} CYCLES {}}
+set a(0-2066) {NAME ACC1-1:slc(acc.idiv#2)#14 TYPE READSLICE PAR 0-1913 XREFS 15762 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.789549} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2067 {}}} CYCLES {}}
+set a(0-2067) {NAME ACC1:conc#325 TYPE CONCATENATE PAR 0-1913 XREFS 15763 LOC {1 0.2559939 1 0.44659442499999996 1 0.44659442499999996 1 0.789549} PREDS {{258 0 0-2065 {}} {259 0 0-2066 {}}} SUCCS {{259 0 0-2068 {}}} CYCLES {}}
+set a(0-2068) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#171 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15764 LOC {1 0.2559939 1 0.44659442499999996 1 0.44659442499999996 1 0.49415055207082714 1 0.8371051270708271} PREDS {{258 0 0-2057 {}} {259 0 0-2067 {}}} SUCCS {{259 0 0-2069 {}}} CYCLES {}}
+set a(0-2069) {NAME ACC1:slc#21 TYPE READSLICE PAR 0-1913 XREFS 15765 LOC {1 0.303550075 1 0.4941506 1 0.4941506 1 0.8371051749999999} PREDS {{259 0 0-2068 {}}} SUCCS {{258 0 0-2071 {}}} CYCLES {}}
+set a(0-2070) {NAME ACC1-1:slc(acc.idiv#2)#16 TYPE READSLICE PAR 0-1913 XREFS 15766 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.8371051749999999} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2071 {}}} CYCLES {}}
+set a(0-2071) {NAME ACC1:conc#329 TYPE CONCATENATE PAR 0-1913 XREFS 15767 LOC {1 0.303550075 1 0.4941506 1 0.4941506 1 0.8371051749999999} PREDS {{258 0 0-2069 {}} {259 0 0-2070 {}}} SUCCS {{259 0 0-2072 {}}} CYCLES {}}
+set a(0-2072) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 12 NAME ACC1:acc#173 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1913 XREFS 15768 LOC {1 0.35689715 1 0.4941506 1 0.4941506 1 0.552750309496936 1 0.895704884496936} PREDS {{258 0 0-2047 {}} {259 0 0-2071 {}}} SUCCS {{259 0 0-2073 {}}} CYCLES {}}
+set a(0-2073) {NAME ACC1:slc#23 TYPE READSLICE PAR 0-1913 XREFS 15769 LOC {1 0.4154969 1 0.55275035 1 0.55275035 1 0.895704925} PREDS {{259 0 0-2072 {}}} SUCCS {{259 0 0-2074 {}}} CYCLES {}}
+set a(0-2074) {NAME ACC1:conc#330 TYPE CONCATENATE PAR 0-1913 XREFS 15770 LOC {1 0.4154969 1 0.55275035 1 0.55275035 1 0.895704925} PREDS {{259 0 0-2073 {}}} SUCCS {{258 0 0-2079 {}}} CYCLES {}}
+set a(0-2075) {NAME ACC1-1:slc(acc.idiv#2) TYPE READSLICE PAR 0-1913 XREFS 15771 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.895704925} PREDS {{258 0 0-2017 {}}} SUCCS {{258 0 0-2078 {}}} CYCLES {}}
+set a(0-2076) {NAME ACC1-1:slc(acc.idiv#2)#17 TYPE READSLICE PAR 0-1913 XREFS 15772 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 1 0.895704925} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2077 {}}} CYCLES {}}
+set a(0-2077) {NAME ACC1-1:not#45 TYPE NOT PAR 0-1913 XREFS 15773 LOC {1 0.21521084999999998 1 0.55275035 1 0.55275035 1 0.895704925} PREDS {{259 0 0-2076 {}}} SUCCS {{259 0 0-2078 {}}} CYCLES {}}
+set a(0-2078) {NAME ACC1:conc#331 TYPE CONCATENATE PAR 0-1913 XREFS 15774 LOC {1 0.21521084999999998 1 0.55275035 1 0.55275035 1 0.895704925} PREDS {{258 0 0-2075 {}} {259 0 0-2077 {}}} SUCCS {{259 0 0-2079 {}}} CYCLES {}}
+set a(0-2079) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 5 NAME ACC1:acc#174 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-1913 XREFS 15775 LOC {1 0.4154969 1 0.55275035 1 0.55275035 1 0.6162623234103024 1 0.9592168984103024} PREDS {{258 0 0-2074 {}} {259 0 0-2078 {}}} SUCCS {{259 0 0-2080 {}}} CYCLES {}}
+set a(0-2080) {NAME ACC1:slc#24 TYPE READSLICE PAR 0-1913 XREFS 15776 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{259 0 0-2079 {}}} SUCCS {{259 0 0-2081 {}} {258 0 0-2083 {}} {258 0 0-2089 {}} {258 0 0-2091 {}} {258 0 0-2096 {}} {258 0 0-2311 {}} {258 0 0-2567 {}} {258 0 0-2570 {}} {258 0 0-2572 {}} {258 0 0-2576 {}} {258 0 0-2634 {}}} CYCLES {}}
+set a(0-2081) {NAME ACC1-1:slc(acc.imod#6)#2 TYPE READSLICE PAR 0-1913 XREFS 15777 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{259 0 0-2080 {}}} SUCCS {{259 0 0-2082 {}}} CYCLES {}}
+set a(0-2082) {NAME ACC1:conc#333 TYPE CONCATENATE PAR 0-1913 XREFS 15778 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{259 0 0-2081 {}}} SUCCS {{258 0 0-2086 {}}} CYCLES {}}
+set a(0-2083) {NAME ACC1-1:slc(acc.imod#6)#3 TYPE READSLICE PAR 0-1913 XREFS 15779 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{258 0 0-2080 {}}} SUCCS {{259 0 0-2084 {}}} CYCLES {}}
+set a(0-2084) {NAME ACC1-1:not#47 TYPE NOT PAR 0-1913 XREFS 15780 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{259 0 0-2083 {}}} SUCCS {{259 0 0-2085 {}}} CYCLES {}}
+set a(0-2085) {NAME ACC1:conc#334 TYPE CONCATENATE PAR 0-1913 XREFS 15781 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{259 0 0-2084 {}}} SUCCS {{259 0 0-2086 {}}} CYCLES {}}
+set a(0-2086) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#175 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15782 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 1 0.6570453850894752 1 0.9999999600894752} PREDS {{258 0 0-2082 {}} {259 0 0-2085 {}}} SUCCS {{259 0 0-2087 {}}} CYCLES {}}
+set a(0-2087) {NAME ACC1:slc#25 TYPE READSLICE PAR 0-1913 XREFS 15783 LOC {1 0.519791975 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{259 0 0-2086 {}}} SUCCS {{259 0 0-2088 {}}} CYCLES {}}
+set a(0-2088) {NAME ACC1:conc#335 TYPE CONCATENATE PAR 0-1913 XREFS 15784 LOC {1 0.519791975 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{259 0 0-2087 {}}} SUCCS {{258 0 0-2094 {}}} CYCLES {}}
+set a(0-2089) {NAME ACC1-1:slc(acc.imod#6)#1 TYPE READSLICE PAR 0-1913 XREFS 15785 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 2 0.028877375} PREDS {{258 0 0-2080 {}}} SUCCS {{259 0 0-2090 {}}} CYCLES {}}
+set a(0-2090) {NAME ACC1-1:not#46 TYPE NOT PAR 0-1913 XREFS 15786 LOC {1 0.479008925 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{259 0 0-2089 {}}} SUCCS {{258 0 0-2093 {}}} CYCLES {}}
+set a(0-2091) {NAME ACC1-1:slc(acc.imod#6)#4 TYPE READSLICE PAR 0-1913 XREFS 15787 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 2 0.028877375} PREDS {{258 0 0-2080 {}}} SUCCS {{259 0 0-2092 {}}} CYCLES {}}
+set a(0-2092) {NAME ACC1-1:not#48 TYPE NOT PAR 0-1913 XREFS 15788 LOC {1 0.479008925 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{259 0 0-2091 {}}} SUCCS {{259 0 0-2093 {}}} CYCLES {}}
+set a(0-2093) {NAME ACC1:conc#336 TYPE CONCATENATE PAR 0-1913 XREFS 15789 LOC {1 0.479008925 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{258 0 0-2090 {}} {259 0 0-2092 {}}} SUCCS {{259 0 0-2094 {}}} CYCLES {}}
+set a(0-2094) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#176 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15790 LOC {1 0.519791975 1 0.657045425 1 0.657045425 1 0.7046015520708271 2 0.07643350207082718} PREDS {{258 0 0-2088 {}} {259 0 0-2093 {}}} SUCCS {{259 0 0-2095 {}}} CYCLES {}}
+set a(0-2095) {NAME ACC1:slc#26 TYPE READSLICE PAR 0-1913 XREFS 15791 LOC {1 0.5673481499999999 1 0.7046015999999999 1 0.7046015999999999 2 0.07643355} PREDS {{259 0 0-2094 {}}} SUCCS {{258 0 0-2098 {}}} CYCLES {}}
+set a(0-2096) {NAME ACC1-1:slc(acc.imod#6) TYPE READSLICE PAR 0-1913 XREFS 15792 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 2 0.07643355} PREDS {{258 0 0-2080 {}}} SUCCS {{259 0 0-2097 {}}} CYCLES {}}
+set a(0-2097) {NAME ACC1:conc#332 TYPE CONCATENATE PAR 0-1913 XREFS 15793 LOC {1 0.479008925 1 0.7046015999999999 1 0.7046015999999999 2 0.07643355} PREDS {{259 0 0-2096 {}}} SUCCS {{259 0 0-2098 {}}} CYCLES {}}
+set a(0-2098) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1-1:acc#28 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15794 LOC {1 0.5673481499999999 1 0.7046015999999999 1 0.7046015999999999 1 0.7521577270708271 2 0.12398967707082717} PREDS {{258 0 0-2095 {}} {259 0 0-2097 {}}} SUCCS {{258 0 0-2581 {}} {258 0 0-2584 {}} {258 0 0-2589 {}} {258 0 0-2591 {}} {258 0 0-2593 {}}} CYCLES {}}
+set a(0-2099) {NAME regs.regs:asn TYPE ASSIGN PAR 0-1913 XREFS 15795 LOC {0 1.0 0 1.0 0 1.0 1 0.40483722499999997} PREDS {{262 0 0-2804 {}}} SUCCS {{259 0 0-2100 {}} {256 0 0-2804 {}}} CYCLES {}}
+set a(0-2100) {NAME regs.regs:slc(regs.regs(2))#6 TYPE READSLICE PAR 0-1913 XREFS 15796 LOC {0 1.0 0 1.0 0 1.0 1 0.40483722499999997} PREDS {{259 0 0-2099 {}}} SUCCS {{259 0 0-2101 {}}} CYCLES {}}
+set a(0-2101) {NAME ACC1:not#73 TYPE NOT PAR 0-1913 XREFS 15797 LOC {0 1.0 1 0.039018275 1 0.039018275 1 0.40483722499999997} PREDS {{259 0 0-2100 {}}} SUCCS {{259 0 0-2102 {}}} CYCLES {}}
+set a(0-2102) {NAME ACC1:conc#337 TYPE CONCATENATE PAR 0-1913 XREFS 15798 LOC {0 1.0 1 0.039018275 1 0.039018275 1 0.40483722499999997} PREDS {{259 0 0-2101 {}}} SUCCS {{258 0 0-2105 {}}} CYCLES {}}
+set a(0-2103) {NAME regs.regs:slc(regs.regs(0))#4 TYPE READSLICE PAR 0-1913 XREFS 15799 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.40483722499999997} PREDS {{258 0 0-1920 {}}} SUCCS {{259 0 0-2104 {}}} CYCLES {}}
+set a(0-2104) {NAME ACC1:conc#338 TYPE CONCATENATE PAR 0-1913 XREFS 15800 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.40483722499999997} PREDS {{259 0 0-2103 {}}} SUCCS {{259 0 0-2105 {}}} CYCLES {}}
+set a(0-2105) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 3 NAME ACC1:acc#178 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1913 XREFS 15801 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.11438903137342837 1 0.48020798137342835} PREDS {{258 0 0-2102 {}} {259 0 0-2104 {}}} SUCCS {{259 0 0-2106 {}}} CYCLES {}}
+set a(0-2106) {NAME ACC1:slc#27 TYPE READSLICE PAR 0-1913 XREFS 15802 LOC {1 0.0753708 1 0.11438907499999999 1 0.11438907499999999 1 0.480208025} PREDS {{259 0 0-2105 {}}} SUCCS {{259 0 0-2107 {}}} CYCLES {}}
+set a(0-2107) {NAME ACC1:exs#95 TYPE SIGNEXTEND PAR 0-1913 XREFS 15803 LOC {1 0.0753708 1 0.11438907499999999 1 0.11438907499999999 1 0.480208025} PREDS {{259 0 0-2106 {}}} SUCCS {{258 0 0-2117 {}}} CYCLES {}}
+set a(0-2108) {NAME regs.regs:asn#1 TYPE ASSIGN PAR 0-1913 XREFS 15804 LOC {0 1.0 0 1.0 0 1.0 1 0.40483722499999997} PREDS {{262 0 0-2804 {}}} SUCCS {{259 0 0-2109 {}} {256 0 0-2804 {}}} CYCLES {}}
+set a(0-2109) {NAME regs.regs:slc(regs.regs(2))#7 TYPE READSLICE PAR 0-1913 XREFS 15805 LOC {0 1.0 0 1.0 0 1.0 1 0.40483722499999997} PREDS {{259 0 0-2108 {}}} SUCCS {{259 0 0-2110 {}}} CYCLES {}}
+set a(0-2110) {NAME ACC1:not#74 TYPE NOT PAR 0-1913 XREFS 15806 LOC {0 1.0 1 0.039018275 1 0.039018275 1 0.40483722499999997} PREDS {{259 0 0-2109 {}}} SUCCS {{259 0 0-2111 {}}} CYCLES {}}
+set a(0-2111) {NAME ACC1:conc#339 TYPE CONCATENATE PAR 0-1913 XREFS 15807 LOC {0 1.0 1 0.039018275 1 0.039018275 1 0.40483722499999997} PREDS {{259 0 0-2110 {}}} SUCCS {{258 0 0-2114 {}}} CYCLES {}}
+set a(0-2112) {NAME regs.regs:slc(regs.regs(0))#5 TYPE READSLICE PAR 0-1913 XREFS 15808 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.40483722499999997} PREDS {{258 0 0-1920 {}}} SUCCS {{259 0 0-2113 {}}} CYCLES {}}
+set a(0-2113) {NAME ACC1:conc#340 TYPE CONCATENATE PAR 0-1913 XREFS 15809 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.40483722499999997} PREDS {{259 0 0-2112 {}}} SUCCS {{259 0 0-2114 {}}} CYCLES {}}
+set a(0-2114) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 3 NAME ACC1:acc#179 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1913 XREFS 15810 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.11438903137342837 1 0.48020798137342835} PREDS {{258 0 0-2111 {}} {259 0 0-2113 {}}} SUCCS {{259 0 0-2115 {}}} CYCLES {}}
+set a(0-2115) {NAME ACC1:slc#28 TYPE READSLICE PAR 0-1913 XREFS 15811 LOC {1 0.0753708 1 0.11438907499999999 1 0.11438907499999999 1 0.480208025} PREDS {{259 0 0-2114 {}}} SUCCS {{259 0 0-2116 {}}} CYCLES {}}
+set a(0-2116) {NAME ACC1:exs#96 TYPE SIGNEXTEND PAR 0-1913 XREFS 15812 LOC {1 0.0753708 1 0.11438907499999999 1 0.11438907499999999 1 0.480208025} PREDS {{259 0 0-2115 {}}} SUCCS {{259 0 0-2117 {}}} CYCLES {}}
+set a(0-2117) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,17) AREA_SCORE 17.19 QUANTITY 9 NAME ACC1:acc#177 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-1913 XREFS 15813 LOC {1 0.0753708 1 0.11438907499999999 1 0.11438907499999999 1 0.21999880535790098 1 0.5858177553579009} PREDS {{258 0 0-2107 {}} {259 0 0-2116 {}}} SUCCS {{258 0 0-2127 {}}} CYCLES {}}
+set a(0-2118) {NAME regs.regs:asn#2 TYPE ASSIGN PAR 0-1913 XREFS 15814 LOC {0 1.0 0 1.0 0 1.0 1 0.510447} PREDS {{262 0 0-2804 {}}} SUCCS {{259 0 0-2119 {}} {256 0 0-2804 {}}} CYCLES {}}
+set a(0-2119) {NAME regs.regs:slc(regs.regs(2)) TYPE READSLICE PAR 0-1913 XREFS 15815 LOC {0 1.0 0 1.0 0 1.0 1 0.510447} PREDS {{259 0 0-2118 {}}} SUCCS {{259 0 0-2120 {}}} CYCLES {}}
+set a(0-2120) {NAME ACC1:not#72 TYPE NOT PAR 0-1913 XREFS 15816 LOC {0 1.0 1 0.14462804999999998 1 0.14462804999999998 1 0.510447} PREDS {{259 0 0-2119 {}}} SUCCS {{259 0 0-2121 {}}} CYCLES {}}
+set a(0-2121) {NAME ACC1:conc#341 TYPE CONCATENATE PAR 0-1913 XREFS 15817 LOC {0 1.0 1 0.14462804999999998 1 0.14462804999999998 1 0.510447} PREDS {{259 0 0-2120 {}}} SUCCS {{258 0 0-2124 {}}} CYCLES {}}
+set a(0-2122) {NAME regs.regs:slc(regs.regs(0))#3 TYPE READSLICE PAR 0-1913 XREFS 15818 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.510447} PREDS {{258 0 0-1920 {}}} SUCCS {{259 0 0-2123 {}}} CYCLES {}}
+set a(0-2123) {NAME ACC1:conc#342 TYPE CONCATENATE PAR 0-1913 XREFS 15819 LOC {1 0.0 1 0.14462804999999998 1 0.14462804999999998 1 0.510447} PREDS {{259 0 0-2122 {}}} SUCCS {{259 0 0-2124 {}}} CYCLES {}}
+set a(0-2124) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 3 NAME ACC1:acc#180 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1913 XREFS 15820 LOC {1 0.0 1 0.14462804999999998 1 0.14462804999999998 1 0.21999880637342834 1 0.5858177563734284} PREDS {{258 0 0-2121 {}} {259 0 0-2123 {}}} SUCCS {{259 0 0-2125 {}}} CYCLES {}}
+set a(0-2125) {NAME ACC1:slc#29 TYPE READSLICE PAR 0-1913 XREFS 15821 LOC {1 0.0753708 1 0.21999885 1 0.21999885 1 0.5858177999999999} PREDS {{259 0 0-2124 {}}} SUCCS {{259 0 0-2126 {}}} CYCLES {}}
+set a(0-2126) {NAME ACC1:exs#94 TYPE SIGNEXTEND PAR 0-1913 XREFS 15822 LOC {1 0.0753708 1 0.21999885 1 0.21999885 1 0.5858177999999999} PREDS {{259 0 0-2125 {}}} SUCCS {{259 0 0-2127 {}}} CYCLES {}}
+set a(0-2127) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(17,0,16,0,18) AREA_SCORE 18.18 QUANTITY 4 NAME ACC1-3:acc TYPE ACCU DELAY {1.75 ns} LIBRARY_DELAY {1.75 ns} PAR 0-1913 XREFS 15823 LOC {1 0.180980575 1 0.21999885 1 0.21999885 1 0.3295998669100358 1 0.6954188169100357} PREDS {{258 0 0-2117 {}} {259 0 0-2126 {}}} SUCCS {{259 0 0-2128 {}} {258 0 0-2130 {}} {258 0 0-2136 {}} {258 0 0-2138 {}} {258 0 0-2144 {}} {258 0 0-2146 {}} {258 0 0-2148 {}} {258 0 0-2152 {}} {258 0 0-2158 {}} {258 0 0-2160 {}} {258 0 0-2162 {}} {258 0 0-2168 {}} {258 0 0-2170 {}} {258 0 0-2172 {}} {258 0 0-2176 {}} {258 0 0-2180 {}} {258 0 0-2185 {}} {258 0 0-2186 {}} {258 0 0-2307 {}} {258 0 0-2312 {}} {258 0 0-2321 {}} {258 0 0-2350 {}} {258 0 0-2356 {}} {258 0 0-2363 {}} {258 0 0-2371 {}} {258 0 0-2451 {}} {258 0 0-2452 {}} {258 0 0-2455 {}} {258 0 0-2459 {}} {258 0 0-2462 {}} {258 0 0-2493 {}} {258 0 0-2498 {}} {258 0 0-2509 {}} {258 0 0-2516 {}} {258 0 0-2517 {}} {258 0 0-2520 {}} {258 0 0-2668 {}} {258 0 0-2675 {}} {258 0 0-2685 {}} {258 0 0-2686 {}} {258 0 0-2690 {}} {258 0 0-2692 {}} {258 0 0-2693 {}} {258 0 0-2700 {}} {258 0 0-2704 {}}} CYCLES {}}
+set a(0-2128) {NAME ACC1-3:slc(acc.idiv)#8 TYPE READSLICE PAR 0-1913 XREFS 15824 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.695418875} PREDS {{259 0 0-2127 {}}} SUCCS {{259 0 0-2129 {}}} CYCLES {}}
+set a(0-2129) {NAME ACC1:conc#344 TYPE CONCATENATE PAR 0-1913 XREFS 15825 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.695418875} PREDS {{259 0 0-2128 {}}} SUCCS {{258 0 0-2133 {}}} CYCLES {}}
+set a(0-2130) {NAME ACC1-3:slc(acc.idiv)#9 TYPE READSLICE PAR 0-1913 XREFS 15826 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.695418875} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2131 {}}} CYCLES {}}
+set a(0-2131) {NAME ACC1-3:not#5 TYPE NOT PAR 0-1913 XREFS 15827 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.695418875} PREDS {{259 0 0-2130 {}}} SUCCS {{259 0 0-2132 {}}} CYCLES {}}
+set a(0-2132) {NAME ACC1:conc#345 TYPE CONCATENATE PAR 0-1913 XREFS 15828 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.695418875} PREDS {{259 0 0-2131 {}}} SUCCS {{259 0 0-2133 {}}} CYCLES {}}
+set a(0-2133) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#181 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15829 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.3703829350894752 1 0.7362018850894753} PREDS {{258 0 0-2129 {}} {259 0 0-2132 {}}} SUCCS {{259 0 0-2134 {}}} CYCLES {}}
+set a(0-2134) {NAME ACC1:slc#30 TYPE READSLICE PAR 0-1913 XREFS 15830 LOC {1 0.3313647 1 0.370382975 1 0.370382975 1 0.7362019249999999} PREDS {{259 0 0-2133 {}}} SUCCS {{259 0 0-2135 {}}} CYCLES {}}
+set a(0-2135) {NAME ACC1:conc#352 TYPE CONCATENATE PAR 0-1913 XREFS 15831 LOC {1 0.3313647 1 0.370382975 1 0.370382975 1 0.7362019249999999} PREDS {{259 0 0-2134 {}}} SUCCS {{258 0 0-2141 {}}} CYCLES {}}
+set a(0-2136) {NAME ACC1-3:slc(acc.idiv)#1 TYPE READSLICE PAR 0-1913 XREFS 15832 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.7362019249999999} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2137 {}}} CYCLES {}}
+set a(0-2137) {NAME ACC1-3:not#1 TYPE NOT PAR 0-1913 XREFS 15833 LOC {1 0.29058164999999997 1 0.370382975 1 0.370382975 1 0.7362019249999999} PREDS {{259 0 0-2136 {}}} SUCCS {{258 0 0-2140 {}}} CYCLES {}}
+set a(0-2138) {NAME ACC1-3:slc(acc.idiv)#13 TYPE READSLICE PAR 0-1913 XREFS 15834 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.7362019249999999} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2139 {}}} CYCLES {}}
+set a(0-2139) {NAME ACC1-3:not#7 TYPE NOT PAR 0-1913 XREFS 15835 LOC {1 0.29058164999999997 1 0.370382975 1 0.370382975 1 0.7362019249999999} PREDS {{259 0 0-2138 {}}} SUCCS {{259 0 0-2140 {}}} CYCLES {}}
+set a(0-2140) {NAME ACC1:conc#353 TYPE CONCATENATE PAR 0-1913 XREFS 15836 LOC {1 0.29058164999999997 1 0.370382975 1 0.370382975 1 0.7362019249999999} PREDS {{258 0 0-2137 {}} {259 0 0-2139 {}}} SUCCS {{259 0 0-2141 {}}} CYCLES {}}
+set a(0-2141) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#185 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15837 LOC {1 0.3313647 1 0.370382975 1 0.370382975 1 0.4179391020708272 1 0.783758052070827} PREDS {{258 0 0-2135 {}} {259 0 0-2140 {}}} SUCCS {{259 0 0-2142 {}}} CYCLES {}}
+set a(0-2142) {NAME ACC1:slc#34 TYPE READSLICE PAR 0-1913 XREFS 15838 LOC {1 0.378920875 1 0.41793915 1 0.41793915 1 0.7837581} PREDS {{259 0 0-2141 {}}} SUCCS {{259 0 0-2143 {}}} CYCLES {}}
+set a(0-2143) {NAME ACC1:conc#356 TYPE CONCATENATE PAR 0-1913 XREFS 15839 LOC {1 0.378920875 1 0.41793915 1 0.41793915 1 0.7837581} PREDS {{259 0 0-2142 {}}} SUCCS {{258 0 0-2155 {}}} CYCLES {}}
+set a(0-2144) {NAME ACC1-3:slc(acc.idiv)#2 TYPE READSLICE PAR 0-1913 XREFS 15840 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.74297505} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2145 {}}} CYCLES {}}
+set a(0-2145) {NAME ACC1:conc#350 TYPE CONCATENATE PAR 0-1913 XREFS 15841 LOC {1 0.29058164999999997 1 0.3771561 1 0.3771561 1 0.74297505} PREDS {{259 0 0-2144 {}}} SUCCS {{258 0 0-2150 {}}} CYCLES {}}
+set a(0-2146) {NAME ACC1-3:slc(acc.idiv)#3 TYPE READSLICE PAR 0-1913 XREFS 15842 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.74297505} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2147 {}}} CYCLES {}}
+set a(0-2147) {NAME ACC1-3:not#2 TYPE NOT PAR 0-1913 XREFS 15843 LOC {1 0.29058164999999997 1 0.3771561 1 0.3771561 1 0.74297505} PREDS {{259 0 0-2146 {}}} SUCCS {{258 0 0-2149 {}}} CYCLES {}}
+set a(0-2148) {NAME ACC1-3:slc(acc.idiv)#12 TYPE READSLICE PAR 0-1913 XREFS 15844 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.74297505} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2149 {}}} CYCLES {}}
+set a(0-2149) {NAME ACC1:conc#351 TYPE CONCATENATE PAR 0-1913 XREFS 15845 LOC {1 0.29058164999999997 1 0.3771561 1 0.3771561 1 0.74297505} PREDS {{258 0 0-2147 {}} {259 0 0-2148 {}}} SUCCS {{259 0 0-2150 {}}} CYCLES {}}
+set a(0-2150) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#184 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15846 LOC {1 0.29058164999999997 1 0.3771561 1 0.3771561 1 0.41793911008947526 1 0.7837580600894752} PREDS {{258 0 0-2145 {}} {259 0 0-2149 {}}} SUCCS {{259 0 0-2151 {}}} CYCLES {}}
+set a(0-2151) {NAME ACC1:slc#33 TYPE READSLICE PAR 0-1913 XREFS 15847 LOC {1 0.3313647 1 0.41793915 1 0.41793915 1 0.7837581} PREDS {{259 0 0-2150 {}}} SUCCS {{258 0 0-2154 {}}} CYCLES {}}
+set a(0-2152) {NAME ACC1-3:slc(acc.idiv)#15 TYPE READSLICE PAR 0-1913 XREFS 15848 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.7837581} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2153 {}}} CYCLES {}}
+set a(0-2153) {NAME ACC1-3:not#8 TYPE NOT PAR 0-1913 XREFS 15849 LOC {1 0.29058164999999997 1 0.41793915 1 0.41793915 1 0.7837581} PREDS {{259 0 0-2152 {}}} SUCCS {{259 0 0-2154 {}}} CYCLES {}}
+set a(0-2154) {NAME ACC1:conc#357 TYPE CONCATENATE PAR 0-1913 XREFS 15850 LOC {1 0.3313647 1 0.41793915 1 0.41793915 1 0.7837581} PREDS {{258 0 0-2151 {}} {259 0 0-2153 {}}} SUCCS {{259 0 0-2155 {}}} CYCLES {}}
+set a(0-2155) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 13 NAME ACC1:acc#187 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1913 XREFS 15851 LOC {1 0.378920875 1 0.41793915 1 0.41793915 1 0.47128617017895047 1 0.8371051201789506} PREDS {{258 0 0-2143 {}} {259 0 0-2154 {}}} SUCCS {{259 0 0-2156 {}}} CYCLES {}}
+set a(0-2156) {NAME ACC1:slc#36 TYPE READSLICE PAR 0-1913 XREFS 15852 LOC {1 0.43226794999999996 1 0.471286225 1 0.471286225 1 0.8371051749999999} PREDS {{259 0 0-2155 {}}} SUCCS {{259 0 0-2157 {}}} CYCLES {}}
+set a(0-2157) {NAME ACC1:conc#358 TYPE CONCATENATE PAR 0-1913 XREFS 15853 LOC {1 0.43226794999999996 1 0.471286225 1 0.471286225 1 0.8371051749999999} PREDS {{259 0 0-2156 {}}} SUCCS {{258 0 0-2182 {}}} CYCLES {}}
+set a(0-2158) {NAME ACC1-3:slc(acc.idiv)#4 TYPE READSLICE PAR 0-1913 XREFS 15854 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.74876595} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2159 {}}} CYCLES {}}
+set a(0-2159) {NAME ACC1:conc#348 TYPE CONCATENATE PAR 0-1913 XREFS 15855 LOC {1 0.29058164999999997 1 0.382947 1 0.382947 1 0.74876595} PREDS {{259 0 0-2158 {}}} SUCCS {{258 0 0-2165 {}}} CYCLES {}}
+set a(0-2160) {NAME ACC1-3:slc(acc.idiv)#5 TYPE READSLICE PAR 0-1913 XREFS 15856 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.74876595} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2161 {}}} CYCLES {}}
+set a(0-2161) {NAME ACC1-3:not#3 TYPE NOT PAR 0-1913 XREFS 15857 LOC {1 0.29058164999999997 1 0.382947 1 0.382947 1 0.74876595} PREDS {{259 0 0-2160 {}}} SUCCS {{258 0 0-2164 {}}} CYCLES {}}
+set a(0-2162) {NAME ACC1-3:slc(acc.idiv)#11 TYPE READSLICE PAR 0-1913 XREFS 15858 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.74876595} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2163 {}}} CYCLES {}}
+set a(0-2163) {NAME ACC1-3:not#6 TYPE NOT PAR 0-1913 XREFS 15859 LOC {1 0.29058164999999997 1 0.382947 1 0.382947 1 0.74876595} PREDS {{259 0 0-2162 {}}} SUCCS {{259 0 0-2164 {}}} CYCLES {}}
+set a(0-2164) {NAME ACC1:conc#349 TYPE CONCATENATE PAR 0-1913 XREFS 15860 LOC {1 0.29058164999999997 1 0.382947 1 0.382947 1 0.74876595} PREDS {{258 0 0-2161 {}} {259 0 0-2163 {}}} SUCCS {{259 0 0-2165 {}}} CYCLES {}}
+set a(0-2165) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#183 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15861 LOC {1 0.29058164999999997 1 0.382947 1 0.382947 1 0.4237300100894752 1 0.7895489600894753} PREDS {{258 0 0-2159 {}} {259 0 0-2164 {}}} SUCCS {{259 0 0-2166 {}}} CYCLES {}}
+set a(0-2166) {NAME ACC1:slc#32 TYPE READSLICE PAR 0-1913 XREFS 15862 LOC {1 0.3313647 1 0.42373004999999997 1 0.42373004999999997 1 0.789549} PREDS {{259 0 0-2165 {}}} SUCCS {{259 0 0-2167 {}}} CYCLES {}}
+set a(0-2167) {NAME ACC1:conc#354 TYPE CONCATENATE PAR 0-1913 XREFS 15863 LOC {1 0.3313647 1 0.42373004999999997 1 0.42373004999999997 1 0.789549} PREDS {{259 0 0-2166 {}}} SUCCS {{258 0 0-2178 {}}} CYCLES {}}
+set a(0-2168) {NAME ACC1-3:slc(acc.idiv)#6 TYPE READSLICE PAR 0-1913 XREFS 15864 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.74876595} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2169 {}}} CYCLES {}}
+set a(0-2169) {NAME ACC1:conc#346 TYPE CONCATENATE PAR 0-1913 XREFS 15865 LOC {1 0.29058164999999997 1 0.382947 1 0.382947 1 0.74876595} PREDS {{259 0 0-2168 {}}} SUCCS {{258 0 0-2174 {}}} CYCLES {}}
+set a(0-2170) {NAME ACC1-3:slc(acc.idiv)#7 TYPE READSLICE PAR 0-1913 XREFS 15866 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.74876595} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2171 {}}} CYCLES {}}
+set a(0-2171) {NAME ACC1-3:not#4 TYPE NOT PAR 0-1913 XREFS 15867 LOC {1 0.29058164999999997 1 0.382947 1 0.382947 1 0.74876595} PREDS {{259 0 0-2170 {}}} SUCCS {{258 0 0-2173 {}}} CYCLES {}}
+set a(0-2172) {NAME ACC1-3:slc(acc.idiv)#10 TYPE READSLICE PAR 0-1913 XREFS 15868 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.74876595} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2173 {}}} CYCLES {}}
+set a(0-2173) {NAME ACC1:conc#347 TYPE CONCATENATE PAR 0-1913 XREFS 15869 LOC {1 0.29058164999999997 1 0.382947 1 0.382947 1 0.74876595} PREDS {{258 0 0-2171 {}} {259 0 0-2172 {}}} SUCCS {{259 0 0-2174 {}}} CYCLES {}}
+set a(0-2174) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#182 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15870 LOC {1 0.29058164999999997 1 0.382947 1 0.382947 1 0.4237300100894752 1 0.7895489600894753} PREDS {{258 0 0-2169 {}} {259 0 0-2173 {}}} SUCCS {{259 0 0-2175 {}}} CYCLES {}}
+set a(0-2175) {NAME ACC1:slc#31 TYPE READSLICE PAR 0-1913 XREFS 15871 LOC {1 0.3313647 1 0.42373004999999997 1 0.42373004999999997 1 0.789549} PREDS {{259 0 0-2174 {}}} SUCCS {{258 0 0-2177 {}}} CYCLES {}}
+set a(0-2176) {NAME ACC1-3:slc(acc.idiv)#14 TYPE READSLICE PAR 0-1913 XREFS 15872 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.789549} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2177 {}}} CYCLES {}}
+set a(0-2177) {NAME ACC1:conc#355 TYPE CONCATENATE PAR 0-1913 XREFS 15873 LOC {1 0.3313647 1 0.42373004999999997 1 0.42373004999999997 1 0.789549} PREDS {{258 0 0-2175 {}} {259 0 0-2176 {}}} SUCCS {{259 0 0-2178 {}}} CYCLES {}}
+set a(0-2178) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#186 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15874 LOC {1 0.3313647 1 0.42373004999999997 1 0.42373004999999997 1 0.47128617707082715 1 0.8371051270708271} PREDS {{258 0 0-2167 {}} {259 0 0-2177 {}}} SUCCS {{259 0 0-2179 {}}} CYCLES {}}
+set a(0-2179) {NAME ACC1:slc#35 TYPE READSLICE PAR 0-1913 XREFS 15875 LOC {1 0.378920875 1 0.471286225 1 0.471286225 1 0.8371051749999999} PREDS {{259 0 0-2178 {}}} SUCCS {{258 0 0-2181 {}}} CYCLES {}}
+set a(0-2180) {NAME ACC1-3:slc(acc.idiv)#16 TYPE READSLICE PAR 0-1913 XREFS 15876 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.8371051749999999} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2181 {}}} CYCLES {}}
+set a(0-2181) {NAME ACC1:conc#359 TYPE CONCATENATE PAR 0-1913 XREFS 15877 LOC {1 0.378920875 1 0.471286225 1 0.471286225 1 0.8371051749999999} PREDS {{258 0 0-2179 {}} {259 0 0-2180 {}}} SUCCS {{259 0 0-2182 {}}} CYCLES {}}
+set a(0-2182) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 12 NAME ACC1:acc#188 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1913 XREFS 15878 LOC {1 0.43226794999999996 1 0.471286225 1 0.471286225 1 0.5298859344969361 1 0.895704884496936} PREDS {{258 0 0-2157 {}} {259 0 0-2181 {}}} SUCCS {{259 0 0-2183 {}}} CYCLES {}}
+set a(0-2183) {NAME ACC1:slc#37 TYPE READSLICE PAR 0-1913 XREFS 15879 LOC {1 0.49086769999999996 1 0.529885975 1 0.529885975 1 0.895704925} PREDS {{259 0 0-2182 {}}} SUCCS {{259 0 0-2184 {}}} CYCLES {}}
+set a(0-2184) {NAME ACC1:conc#360 TYPE CONCATENATE PAR 0-1913 XREFS 15880 LOC {1 0.49086769999999996 1 0.529885975 1 0.529885975 1 0.895704925} PREDS {{259 0 0-2183 {}}} SUCCS {{258 0 0-2189 {}}} CYCLES {}}
+set a(0-2185) {NAME ACC1-3:slc(acc.idiv) TYPE READSLICE PAR 0-1913 XREFS 15881 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.895704925} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2188 {}}} CYCLES {}}
+set a(0-2186) {NAME ACC1-3:slc(acc.idiv)#17 TYPE READSLICE PAR 0-1913 XREFS 15882 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 1 0.895704925} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2187 {}}} CYCLES {}}
+set a(0-2187) {NAME ACC1-3:not#9 TYPE NOT PAR 0-1913 XREFS 15883 LOC {1 0.29058164999999997 1 0.529885975 1 0.529885975 1 0.895704925} PREDS {{259 0 0-2186 {}}} SUCCS {{259 0 0-2188 {}}} CYCLES {}}
+set a(0-2188) {NAME ACC1:conc#361 TYPE CONCATENATE PAR 0-1913 XREFS 15884 LOC {1 0.29058164999999997 1 0.529885975 1 0.529885975 1 0.895704925} PREDS {{258 0 0-2185 {}} {259 0 0-2187 {}}} SUCCS {{259 0 0-2189 {}}} CYCLES {}}
+set a(0-2189) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 5 NAME ACC1:acc#189 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-1913 XREFS 15885 LOC {1 0.49086769999999996 1 0.529885975 1 0.529885975 1 0.5933979484103025 1 0.9592168984103024} PREDS {{258 0 0-2184 {}} {259 0 0-2188 {}}} SUCCS {{259 0 0-2190 {}}} CYCLES {}}
+set a(0-2190) {NAME ACC1:slc#38 TYPE READSLICE PAR 0-1913 XREFS 15886 LOC {1 0.554379725 1 0.593398 1 0.593398 1 0.95921695} PREDS {{259 0 0-2189 {}}} SUCCS {{259 0 0-2191 {}} {258 0 0-2193 {}} {258 0 0-2199 {}} {258 0 0-2201 {}} {258 0 0-2206 {}} {258 0 0-2319 {}} {258 0 0-2473 {}} {258 0 0-2578 {}} {258 0 0-2618 {}} {258 0 0-2714 {}} {258 0 0-2723 {}}} CYCLES {}}
+set a(0-2191) {NAME ACC1-3:slc(acc.imod)#2 TYPE READSLICE PAR 0-1913 XREFS 15887 LOC {1 0.554379725 1 0.593398 1 0.593398 1 0.95921695} PREDS {{259 0 0-2190 {}}} SUCCS {{259 0 0-2192 {}}} CYCLES {}}
+set a(0-2192) {NAME ACC1:conc#363 TYPE CONCATENATE PAR 0-1913 XREFS 15888 LOC {1 0.554379725 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{259 0 0-2191 {}}} SUCCS {{258 0 0-2196 {}}} CYCLES {}}
+set a(0-2193) {NAME ACC1-3:slc(acc.imod)#3 TYPE READSLICE PAR 0-1913 XREFS 15889 LOC {1 0.554379725 1 0.593398 1 0.593398 1 0.95921695} PREDS {{258 0 0-2190 {}}} SUCCS {{259 0 0-2194 {}}} CYCLES {}}
+set a(0-2194) {NAME ACC1-3:not#11 TYPE NOT PAR 0-1913 XREFS 15890 LOC {1 0.554379725 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{259 0 0-2193 {}}} SUCCS {{259 0 0-2195 {}}} CYCLES {}}
+set a(0-2195) {NAME ACC1:conc#364 TYPE CONCATENATE PAR 0-1913 XREFS 15891 LOC {1 0.554379725 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{259 0 0-2194 {}}} SUCCS {{259 0 0-2196 {}}} CYCLES {}}
+set a(0-2196) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#190 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15892 LOC {1 0.554379725 1 0.6162623749999999 1 0.6162623749999999 1 0.6570453850894752 1 0.9999999600894752} PREDS {{258 0 0-2192 {}} {259 0 0-2195 {}}} SUCCS {{259 0 0-2197 {}}} CYCLES {}}
+set a(0-2197) {NAME ACC1:slc#39 TYPE READSLICE PAR 0-1913 XREFS 15893 LOC {1 0.5951627749999999 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{259 0 0-2196 {}}} SUCCS {{259 0 0-2198 {}}} CYCLES {}}
+set a(0-2198) {NAME ACC1:conc#365 TYPE CONCATENATE PAR 0-1913 XREFS 15894 LOC {1 0.5951627749999999 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{259 0 0-2197 {}}} SUCCS {{258 0 0-2204 {}}} CYCLES {}}
+set a(0-2199) {NAME ACC1-3:slc(acc.imod)#1 TYPE READSLICE PAR 0-1913 XREFS 15895 LOC {1 0.554379725 1 0.593398 1 0.593398 2 0.028877375} PREDS {{258 0 0-2190 {}}} SUCCS {{259 0 0-2200 {}}} CYCLES {}}
+set a(0-2200) {NAME ACC1-3:not#10 TYPE NOT PAR 0-1913 XREFS 15896 LOC {1 0.554379725 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{259 0 0-2199 {}}} SUCCS {{258 0 0-2203 {}}} CYCLES {}}
+set a(0-2201) {NAME ACC1-3:slc(acc.imod)#4 TYPE READSLICE PAR 0-1913 XREFS 15897 LOC {1 0.554379725 1 0.593398 1 0.593398 2 0.028877375} PREDS {{258 0 0-2190 {}}} SUCCS {{259 0 0-2202 {}}} CYCLES {}}
+set a(0-2202) {NAME ACC1-3:not#12 TYPE NOT PAR 0-1913 XREFS 15898 LOC {1 0.554379725 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{259 0 0-2201 {}}} SUCCS {{259 0 0-2203 {}}} CYCLES {}}
+set a(0-2203) {NAME ACC1:conc#366 TYPE CONCATENATE PAR 0-1913 XREFS 15899 LOC {1 0.554379725 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{258 0 0-2200 {}} {259 0 0-2202 {}}} SUCCS {{259 0 0-2204 {}}} CYCLES {}}
+set a(0-2204) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#191 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15900 LOC {1 0.5951627749999999 1 0.657045425 1 0.657045425 1 0.7046015520708271 2 0.07643350207082718} PREDS {{258 0 0-2198 {}} {259 0 0-2203 {}}} SUCCS {{259 0 0-2205 {}}} CYCLES {}}
+set a(0-2205) {NAME ACC1:slc#40 TYPE READSLICE PAR 0-1913 XREFS 15901 LOC {1 0.64271895 1 0.7046015999999999 1 0.7046015999999999 2 0.07643355} PREDS {{259 0 0-2204 {}}} SUCCS {{258 0 0-2208 {}}} CYCLES {}}
+set a(0-2206) {NAME ACC1-3:slc(acc.imod) TYPE READSLICE PAR 0-1913 XREFS 15902 LOC {1 0.554379725 1 0.593398 1 0.593398 2 0.07643355} PREDS {{258 0 0-2190 {}}} SUCCS {{259 0 0-2207 {}}} CYCLES {}}
+set a(0-2207) {NAME ACC1:conc#362 TYPE CONCATENATE PAR 0-1913 XREFS 15903 LOC {1 0.554379725 1 0.7046015999999999 1 0.7046015999999999 2 0.07643355} PREDS {{259 0 0-2206 {}}} SUCCS {{259 0 0-2208 {}}} CYCLES {}}
+set a(0-2208) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1-3:acc#5 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15904 LOC {1 0.64271895 1 0.7046015999999999 1 0.7046015999999999 1 0.7521577270708271 2 0.12398967707082717} PREDS {{258 0 0-2205 {}} {259 0 0-2207 {}}} SUCCS {{258 0 0-2335 {}} {258 0 0-2586 {}} {258 0 0-2600 {}} {258 0 0-2602 {}} {258 0 0-2604 {}}} CYCLES {}}
+set a(0-2209) {NAME regs.regs:slc(regs.regs(0))#10 TYPE READSLICE PAR 0-1913 XREFS 15905 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.409023875} PREDS {{258 0 0-1920 {}}} SUCCS {{258 0 0-2212 {}}} CYCLES {}}
+set a(0-2210) {NAME regs.regs:asn#3 TYPE ASSIGN PAR 0-1913 XREFS 15906 LOC {0 1.0 0 1.0 0 1.0 1 0.409023875} PREDS {{262 0 0-2803 {}}} SUCCS {{259 0 0-2211 {}} {256 0 0-2803 {}}} CYCLES {}}
+set a(0-2211) {NAME regs.regs:slc(regs.regs(2).sg2)#1 TYPE READSLICE PAR 0-1913 XREFS 15907 LOC {0 1.0 0 1.0 0 1.0 1 0.409023875} PREDS {{259 0 0-2210 {}}} SUCCS {{259 0 0-2212 {}}} CYCLES {}}
+set a(0-2212) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 3 NAME ACC1-3:acc#22 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-1913 XREFS 15908 LOC {1 0.0 1 0.0660693 1 0.0660693 1 0.1372534033364113 1 0.48020797833641127} PREDS {{258 0 0-2209 {}} {259 0 0-2211 {}}} SUCCS {{259 0 0-2213 {}}} CYCLES {}}
+set a(0-2213) {NAME ACC1:exs#74 TYPE SIGNEXTEND PAR 0-1913 XREFS 15909 LOC {1 0.07118415 1 0.13725345 1 0.13725345 1 0.480208025} PREDS {{259 0 0-2212 {}}} SUCCS {{258 0 0-2219 {}}} CYCLES {}}
+set a(0-2214) {NAME regs.regs:slc(regs.regs(0))#11 TYPE READSLICE PAR 0-1913 XREFS 15910 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.409023875} PREDS {{258 0 0-1920 {}}} SUCCS {{258 0 0-2217 {}}} CYCLES {}}
+set a(0-2215) {NAME regs.regs:asn#4 TYPE ASSIGN PAR 0-1913 XREFS 15911 LOC {0 1.0 0 1.0 0 1.0 1 0.409023875} PREDS {{262 0 0-2803 {}}} SUCCS {{259 0 0-2216 {}} {256 0 0-2803 {}}} CYCLES {}}
+set a(0-2216) {NAME regs.regs:slc(regs.regs(2).sg2)#2 TYPE READSLICE PAR 0-1913 XREFS 15912 LOC {0 1.0 0 1.0 0 1.0 1 0.409023875} PREDS {{259 0 0-2215 {}}} SUCCS {{259 0 0-2217 {}}} CYCLES {}}
+set a(0-2217) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 3 NAME ACC1-3:acc#25 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-1913 XREFS 15913 LOC {1 0.0 1 0.0660693 1 0.0660693 1 0.1372534033364113 1 0.48020797833641127} PREDS {{258 0 0-2214 {}} {259 0 0-2216 {}}} SUCCS {{259 0 0-2218 {}}} CYCLES {}}
+set a(0-2218) {NAME ACC1:exs#75 TYPE SIGNEXTEND PAR 0-1913 XREFS 15914 LOC {1 0.07118415 1 0.13725345 1 0.13725345 1 0.480208025} PREDS {{259 0 0-2217 {}}} SUCCS {{259 0 0-2219 {}}} CYCLES {}}
+set a(0-2219) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,17) AREA_SCORE 17.19 QUANTITY 9 NAME ACC1:acc#192 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-1913 XREFS 15915 LOC {1 0.07118415 1 0.13725345 1 0.13725345 1 0.242863180357901 1 0.5858177553579009} PREDS {{258 0 0-2213 {}} {259 0 0-2218 {}}} SUCCS {{258 0 0-2225 {}}} CYCLES {}}
+set a(0-2220) {NAME regs.regs:slc(regs.regs(0))#9 TYPE READSLICE PAR 0-1913 XREFS 15916 LOC {1 0.0 1 0.039018275 1 0.039018275 1 0.5146336499999999} PREDS {{258 0 0-1920 {}}} SUCCS {{258 0 0-2223 {}}} CYCLES {}}
+set a(0-2221) {NAME regs.regs:asn#5 TYPE ASSIGN PAR 0-1913 XREFS 15917 LOC {0 1.0 0 1.0 0 1.0 1 0.5146336499999999} PREDS {{262 0 0-2803 {}}} SUCCS {{259 0 0-2222 {}} {256 0 0-2803 {}}} CYCLES {}}
+set a(0-2222) {NAME regs.regs:slc(regs.regs(2).sg2) TYPE READSLICE PAR 0-1913 XREFS 15918 LOC {0 1.0 0 1.0 0 1.0 1 0.5146336499999999} PREDS {{259 0 0-2221 {}}} SUCCS {{259 0 0-2223 {}}} CYCLES {}}
+set a(0-2223) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 3 NAME ACC1-3:acc#19 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-1913 XREFS 15919 LOC {1 0.0 1 0.171679075 1 0.171679075 1 0.2428631783364113 1 0.5858177533364113} PREDS {{258 0 0-2220 {}} {259 0 0-2222 {}}} SUCCS {{259 0 0-2224 {}}} CYCLES {}}
+set a(0-2224) {NAME ACC1:exs#73 TYPE SIGNEXTEND PAR 0-1913 XREFS 15920 LOC {1 0.07118415 1 0.242863225 1 0.242863225 1 0.5858177999999999} PREDS {{259 0 0-2223 {}}} SUCCS {{259 0 0-2225 {}}} CYCLES {}}
+set a(0-2225) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(17,0,16,0,18) AREA_SCORE 18.18 QUANTITY 4 NAME ACC1-3:acc#26 TYPE ACCU DELAY {1.75 ns} LIBRARY_DELAY {1.75 ns} PAR 0-1913 XREFS 15921 LOC {1 0.176793925 1 0.242863225 1 0.242863225 1 0.3524642419100358 1 0.6954188169100357} PREDS {{258 0 0-2219 {}} {259 0 0-2224 {}}} SUCCS {{259 0 0-2226 {}} {258 0 0-2228 {}} {258 0 0-2234 {}} {258 0 0-2236 {}} {258 0 0-2242 {}} {258 0 0-2244 {}} {258 0 0-2246 {}} {258 0 0-2250 {}} {258 0 0-2256 {}} {258 0 0-2258 {}} {258 0 0-2260 {}} {258 0 0-2266 {}} {258 0 0-2268 {}} {258 0 0-2270 {}} {258 0 0-2274 {}} {258 0 0-2278 {}} {258 0 0-2283 {}} {258 0 0-2284 {}} {258 0 0-2308 {}} {258 0 0-2322 {}} {258 0 0-2346 {}} {258 0 0-2351 {}} {258 0 0-2357 {}} {258 0 0-2364 {}} {258 0 0-2378 {}} {258 0 0-2409 {}} {258 0 0-2411 {}} {258 0 0-2415 {}} {258 0 0-2417 {}} {258 0 0-2420 {}} {258 0 0-2422 {}} {258 0 0-2446 {}} {258 0 0-2454 {}} {258 0 0-2467 {}} {258 0 0-2470 {}} {258 0 0-2489 {}} {258 0 0-2494 {}} {258 0 0-2499 {}} {258 0 0-2508 {}} {258 0 0-2521 {}} {258 0 0-2669 {}} {258 0 0-2676 {}} {258 0 0-2697 {}} {258 0 0-2699 {}} {258 0 0-2705 {}}} CYCLES {}}
+set a(0-2226) {NAME ACC1-3:slc(acc.idiv#2)#8 TYPE READSLICE PAR 0-1913 XREFS 15922 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.695418875} PREDS {{259 0 0-2225 {}}} SUCCS {{259 0 0-2227 {}}} CYCLES {}}
+set a(0-2227) {NAME ACC1:conc#368 TYPE CONCATENATE PAR 0-1913 XREFS 15923 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.695418875} PREDS {{259 0 0-2226 {}}} SUCCS {{258 0 0-2231 {}}} CYCLES {}}
+set a(0-2228) {NAME ACC1-3:slc(acc.idiv#2)#9 TYPE READSLICE PAR 0-1913 XREFS 15924 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.695418875} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2229 {}}} CYCLES {}}
+set a(0-2229) {NAME ACC1-3:not#41 TYPE NOT PAR 0-1913 XREFS 15925 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.695418875} PREDS {{259 0 0-2228 {}}} SUCCS {{259 0 0-2230 {}}} CYCLES {}}
+set a(0-2230) {NAME ACC1:conc#369 TYPE CONCATENATE PAR 0-1913 XREFS 15926 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.695418875} PREDS {{259 0 0-2229 {}}} SUCCS {{259 0 0-2231 {}}} CYCLES {}}
+set a(0-2231) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#193 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15927 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.3932473100894752 1 0.7362018850894753} PREDS {{258 0 0-2227 {}} {259 0 0-2230 {}}} SUCCS {{259 0 0-2232 {}}} CYCLES {}}
+set a(0-2232) {NAME ACC1:slc#41 TYPE READSLICE PAR 0-1913 XREFS 15928 LOC {1 0.32717805 1 0.39324735 1 0.39324735 1 0.7362019249999999} PREDS {{259 0 0-2231 {}}} SUCCS {{259 0 0-2233 {}}} CYCLES {}}
+set a(0-2233) {NAME ACC1:conc#376 TYPE CONCATENATE PAR 0-1913 XREFS 15929 LOC {1 0.32717805 1 0.39324735 1 0.39324735 1 0.7362019249999999} PREDS {{259 0 0-2232 {}}} SUCCS {{258 0 0-2239 {}}} CYCLES {}}
+set a(0-2234) {NAME ACC1-3:slc(acc.idiv#2)#1 TYPE READSLICE PAR 0-1913 XREFS 15930 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.7362019249999999} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2235 {}}} CYCLES {}}
+set a(0-2235) {NAME ACC1-3:not#37 TYPE NOT PAR 0-1913 XREFS 15931 LOC {1 0.286395 1 0.39324735 1 0.39324735 1 0.7362019249999999} PREDS {{259 0 0-2234 {}}} SUCCS {{258 0 0-2238 {}}} CYCLES {}}
+set a(0-2236) {NAME ACC1-3:slc(acc.idiv#2)#13 TYPE READSLICE PAR 0-1913 XREFS 15932 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.7362019249999999} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2237 {}}} CYCLES {}}
+set a(0-2237) {NAME ACC1-3:not#43 TYPE NOT PAR 0-1913 XREFS 15933 LOC {1 0.286395 1 0.39324735 1 0.39324735 1 0.7362019249999999} PREDS {{259 0 0-2236 {}}} SUCCS {{259 0 0-2238 {}}} CYCLES {}}
+set a(0-2238) {NAME ACC1:conc#377 TYPE CONCATENATE PAR 0-1913 XREFS 15934 LOC {1 0.286395 1 0.39324735 1 0.39324735 1 0.7362019249999999} PREDS {{258 0 0-2235 {}} {259 0 0-2237 {}}} SUCCS {{259 0 0-2239 {}}} CYCLES {}}
+set a(0-2239) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#197 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15935 LOC {1 0.32717805 1 0.39324735 1 0.39324735 1 0.4408034770708272 1 0.783758052070827} PREDS {{258 0 0-2233 {}} {259 0 0-2238 {}}} SUCCS {{259 0 0-2240 {}}} CYCLES {}}
+set a(0-2240) {NAME ACC1:slc#45 TYPE READSLICE PAR 0-1913 XREFS 15936 LOC {1 0.374734225 1 0.440803525 1 0.440803525 1 0.7837581} PREDS {{259 0 0-2239 {}}} SUCCS {{259 0 0-2241 {}}} CYCLES {}}
+set a(0-2241) {NAME ACC1:conc#380 TYPE CONCATENATE PAR 0-1913 XREFS 15937 LOC {1 0.374734225 1 0.440803525 1 0.440803525 1 0.7837581} PREDS {{259 0 0-2240 {}}} SUCCS {{258 0 0-2253 {}}} CYCLES {}}
+set a(0-2242) {NAME ACC1-3:slc(acc.idiv#2)#2 TYPE READSLICE PAR 0-1913 XREFS 15938 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.74297505} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2243 {}}} CYCLES {}}
+set a(0-2243) {NAME ACC1:conc#374 TYPE CONCATENATE PAR 0-1913 XREFS 15939 LOC {1 0.286395 1 0.400020475 1 0.400020475 1 0.74297505} PREDS {{259 0 0-2242 {}}} SUCCS {{258 0 0-2248 {}}} CYCLES {}}
+set a(0-2244) {NAME ACC1-3:slc(acc.idiv#2)#3 TYPE READSLICE PAR 0-1913 XREFS 15940 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.74297505} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2245 {}}} CYCLES {}}
+set a(0-2245) {NAME ACC1-3:not#38 TYPE NOT PAR 0-1913 XREFS 15941 LOC {1 0.286395 1 0.400020475 1 0.400020475 1 0.74297505} PREDS {{259 0 0-2244 {}}} SUCCS {{258 0 0-2247 {}}} CYCLES {}}
+set a(0-2246) {NAME ACC1-3:slc(acc.idiv#2)#12 TYPE READSLICE PAR 0-1913 XREFS 15942 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.74297505} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2247 {}}} CYCLES {}}
+set a(0-2247) {NAME ACC1:conc#375 TYPE CONCATENATE PAR 0-1913 XREFS 15943 LOC {1 0.286395 1 0.400020475 1 0.400020475 1 0.74297505} PREDS {{258 0 0-2245 {}} {259 0 0-2246 {}}} SUCCS {{259 0 0-2248 {}}} CYCLES {}}
+set a(0-2248) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#196 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15944 LOC {1 0.286395 1 0.400020475 1 0.400020475 1 0.4408034850894752 1 0.7837580600894752} PREDS {{258 0 0-2243 {}} {259 0 0-2247 {}}} SUCCS {{259 0 0-2249 {}}} CYCLES {}}
+set a(0-2249) {NAME ACC1:slc#44 TYPE READSLICE PAR 0-1913 XREFS 15945 LOC {1 0.32717805 1 0.440803525 1 0.440803525 1 0.7837581} PREDS {{259 0 0-2248 {}}} SUCCS {{258 0 0-2252 {}}} CYCLES {}}
+set a(0-2250) {NAME ACC1-3:slc(acc.idiv#2)#15 TYPE READSLICE PAR 0-1913 XREFS 15946 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.7837581} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2251 {}}} CYCLES {}}
+set a(0-2251) {NAME ACC1-3:not#44 TYPE NOT PAR 0-1913 XREFS 15947 LOC {1 0.286395 1 0.440803525 1 0.440803525 1 0.7837581} PREDS {{259 0 0-2250 {}}} SUCCS {{259 0 0-2252 {}}} CYCLES {}}
+set a(0-2252) {NAME ACC1:conc#381 TYPE CONCATENATE PAR 0-1913 XREFS 15948 LOC {1 0.32717805 1 0.440803525 1 0.440803525 1 0.7837581} PREDS {{258 0 0-2249 {}} {259 0 0-2251 {}}} SUCCS {{259 0 0-2253 {}}} CYCLES {}}
+set a(0-2253) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 13 NAME ACC1:acc#199 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1913 XREFS 15949 LOC {1 0.374734225 1 0.440803525 1 0.440803525 1 0.49415054517895046 1 0.8371051201789506} PREDS {{258 0 0-2241 {}} {259 0 0-2252 {}}} SUCCS {{259 0 0-2254 {}}} CYCLES {}}
+set a(0-2254) {NAME ACC1:slc#47 TYPE READSLICE PAR 0-1913 XREFS 15950 LOC {1 0.4280813 1 0.4941506 1 0.4941506 1 0.8371051749999999} PREDS {{259 0 0-2253 {}}} SUCCS {{259 0 0-2255 {}}} CYCLES {}}
+set a(0-2255) {NAME ACC1:conc#382 TYPE CONCATENATE PAR 0-1913 XREFS 15951 LOC {1 0.4280813 1 0.4941506 1 0.4941506 1 0.8371051749999999} PREDS {{259 0 0-2254 {}}} SUCCS {{258 0 0-2280 {}}} CYCLES {}}
+set a(0-2256) {NAME ACC1-3:slc(acc.idiv#2)#4 TYPE READSLICE PAR 0-1913 XREFS 15952 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.74876595} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2257 {}}} CYCLES {}}
+set a(0-2257) {NAME ACC1:conc#372 TYPE CONCATENATE PAR 0-1913 XREFS 15953 LOC {1 0.286395 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{259 0 0-2256 {}}} SUCCS {{258 0 0-2263 {}}} CYCLES {}}
+set a(0-2258) {NAME ACC1-3:slc(acc.idiv#2)#5 TYPE READSLICE PAR 0-1913 XREFS 15954 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.74876595} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2259 {}}} CYCLES {}}
+set a(0-2259) {NAME ACC1-3:not#39 TYPE NOT PAR 0-1913 XREFS 15955 LOC {1 0.286395 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{259 0 0-2258 {}}} SUCCS {{258 0 0-2262 {}}} CYCLES {}}
+set a(0-2260) {NAME ACC1-3:slc(acc.idiv#2)#11 TYPE READSLICE PAR 0-1913 XREFS 15956 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.74876595} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2261 {}}} CYCLES {}}
+set a(0-2261) {NAME ACC1-3:not#42 TYPE NOT PAR 0-1913 XREFS 15957 LOC {1 0.286395 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{259 0 0-2260 {}}} SUCCS {{259 0 0-2262 {}}} CYCLES {}}
+set a(0-2262) {NAME ACC1:conc#373 TYPE CONCATENATE PAR 0-1913 XREFS 15958 LOC {1 0.286395 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{258 0 0-2259 {}} {259 0 0-2261 {}}} SUCCS {{259 0 0-2263 {}}} CYCLES {}}
+set a(0-2263) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#195 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15959 LOC {1 0.286395 1 0.405811375 1 0.405811375 1 0.44659438508947524 1 0.7895489600894753} PREDS {{258 0 0-2257 {}} {259 0 0-2262 {}}} SUCCS {{259 0 0-2264 {}}} CYCLES {}}
+set a(0-2264) {NAME ACC1:slc#43 TYPE READSLICE PAR 0-1913 XREFS 15960 LOC {1 0.32717805 1 0.44659442499999996 1 0.44659442499999996 1 0.789549} PREDS {{259 0 0-2263 {}}} SUCCS {{259 0 0-2265 {}}} CYCLES {}}
+set a(0-2265) {NAME ACC1:conc#378 TYPE CONCATENATE PAR 0-1913 XREFS 15961 LOC {1 0.32717805 1 0.44659442499999996 1 0.44659442499999996 1 0.789549} PREDS {{259 0 0-2264 {}}} SUCCS {{258 0 0-2276 {}}} CYCLES {}}
+set a(0-2266) {NAME ACC1-3:slc(acc.idiv#2)#6 TYPE READSLICE PAR 0-1913 XREFS 15962 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.74876595} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2267 {}}} CYCLES {}}
+set a(0-2267) {NAME ACC1:conc#370 TYPE CONCATENATE PAR 0-1913 XREFS 15963 LOC {1 0.286395 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{259 0 0-2266 {}}} SUCCS {{258 0 0-2272 {}}} CYCLES {}}
+set a(0-2268) {NAME ACC1-3:slc(acc.idiv#2)#7 TYPE READSLICE PAR 0-1913 XREFS 15964 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.74876595} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2269 {}}} CYCLES {}}
+set a(0-2269) {NAME ACC1-3:not#40 TYPE NOT PAR 0-1913 XREFS 15965 LOC {1 0.286395 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{259 0 0-2268 {}}} SUCCS {{258 0 0-2271 {}}} CYCLES {}}
+set a(0-2270) {NAME ACC1-3:slc(acc.idiv#2)#10 TYPE READSLICE PAR 0-1913 XREFS 15966 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.74876595} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2271 {}}} CYCLES {}}
+set a(0-2271) {NAME ACC1:conc#371 TYPE CONCATENATE PAR 0-1913 XREFS 15967 LOC {1 0.286395 1 0.405811375 1 0.405811375 1 0.74876595} PREDS {{258 0 0-2269 {}} {259 0 0-2270 {}}} SUCCS {{259 0 0-2272 {}}} CYCLES {}}
+set a(0-2272) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#194 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15968 LOC {1 0.286395 1 0.405811375 1 0.405811375 1 0.44659438508947524 1 0.7895489600894753} PREDS {{258 0 0-2267 {}} {259 0 0-2271 {}}} SUCCS {{259 0 0-2273 {}}} CYCLES {}}
+set a(0-2273) {NAME ACC1:slc#42 TYPE READSLICE PAR 0-1913 XREFS 15969 LOC {1 0.32717805 1 0.44659442499999996 1 0.44659442499999996 1 0.789549} PREDS {{259 0 0-2272 {}}} SUCCS {{258 0 0-2275 {}}} CYCLES {}}
+set a(0-2274) {NAME ACC1-3:slc(acc.idiv#2)#14 TYPE READSLICE PAR 0-1913 XREFS 15970 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.789549} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2275 {}}} CYCLES {}}
+set a(0-2275) {NAME ACC1:conc#379 TYPE CONCATENATE PAR 0-1913 XREFS 15971 LOC {1 0.32717805 1 0.44659442499999996 1 0.44659442499999996 1 0.789549} PREDS {{258 0 0-2273 {}} {259 0 0-2274 {}}} SUCCS {{259 0 0-2276 {}}} CYCLES {}}
+set a(0-2276) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#198 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15972 LOC {1 0.32717805 1 0.44659442499999996 1 0.44659442499999996 1 0.49415055207082714 1 0.8371051270708271} PREDS {{258 0 0-2265 {}} {259 0 0-2275 {}}} SUCCS {{259 0 0-2277 {}}} CYCLES {}}
+set a(0-2277) {NAME ACC1:slc#46 TYPE READSLICE PAR 0-1913 XREFS 15973 LOC {1 0.374734225 1 0.4941506 1 0.4941506 1 0.8371051749999999} PREDS {{259 0 0-2276 {}}} SUCCS {{258 0 0-2279 {}}} CYCLES {}}
+set a(0-2278) {NAME ACC1-3:slc(acc.idiv#2)#16 TYPE READSLICE PAR 0-1913 XREFS 15974 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.8371051749999999} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2279 {}}} CYCLES {}}
+set a(0-2279) {NAME ACC1:conc#383 TYPE CONCATENATE PAR 0-1913 XREFS 15975 LOC {1 0.374734225 1 0.4941506 1 0.4941506 1 0.8371051749999999} PREDS {{258 0 0-2277 {}} {259 0 0-2278 {}}} SUCCS {{259 0 0-2280 {}}} CYCLES {}}
+set a(0-2280) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 12 NAME ACC1:acc#200 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1913 XREFS 15976 LOC {1 0.4280813 1 0.4941506 1 0.4941506 1 0.552750309496936 1 0.895704884496936} PREDS {{258 0 0-2255 {}} {259 0 0-2279 {}}} SUCCS {{259 0 0-2281 {}}} CYCLES {}}
+set a(0-2281) {NAME ACC1:slc#48 TYPE READSLICE PAR 0-1913 XREFS 15977 LOC {1 0.48668105 1 0.55275035 1 0.55275035 1 0.895704925} PREDS {{259 0 0-2280 {}}} SUCCS {{259 0 0-2282 {}}} CYCLES {}}
+set a(0-2282) {NAME ACC1:conc#384 TYPE CONCATENATE PAR 0-1913 XREFS 15978 LOC {1 0.48668105 1 0.55275035 1 0.55275035 1 0.895704925} PREDS {{259 0 0-2281 {}}} SUCCS {{258 0 0-2287 {}}} CYCLES {}}
+set a(0-2283) {NAME ACC1-3:slc(acc.idiv#2) TYPE READSLICE PAR 0-1913 XREFS 15979 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.895704925} PREDS {{258 0 0-2225 {}}} SUCCS {{258 0 0-2286 {}}} CYCLES {}}
+set a(0-2284) {NAME ACC1-3:slc(acc.idiv#2)#17 TYPE READSLICE PAR 0-1913 XREFS 15980 LOC {1 0.286395 1 0.3524643 1 0.3524643 1 0.895704925} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2285 {}}} CYCLES {}}
+set a(0-2285) {NAME ACC1-3:not#45 TYPE NOT PAR 0-1913 XREFS 15981 LOC {1 0.286395 1 0.55275035 1 0.55275035 1 0.895704925} PREDS {{259 0 0-2284 {}}} SUCCS {{259 0 0-2286 {}}} CYCLES {}}
+set a(0-2286) {NAME ACC1:conc#385 TYPE CONCATENATE PAR 0-1913 XREFS 15982 LOC {1 0.286395 1 0.55275035 1 0.55275035 1 0.895704925} PREDS {{258 0 0-2283 {}} {259 0 0-2285 {}}} SUCCS {{259 0 0-2287 {}}} CYCLES {}}
+set a(0-2287) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 5 NAME ACC1:acc#201 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-1913 XREFS 15983 LOC {1 0.48668105 1 0.55275035 1 0.55275035 1 0.6162623234103024 1 0.9592168984103024} PREDS {{258 0 0-2282 {}} {259 0 0-2286 {}}} SUCCS {{259 0 0-2288 {}}} CYCLES {}}
+set a(0-2288) {NAME ACC1:slc#49 TYPE READSLICE PAR 0-1913 XREFS 15984 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{259 0 0-2287 {}}} SUCCS {{259 0 0-2289 {}} {258 0 0-2291 {}} {258 0 0-2297 {}} {258 0 0-2299 {}} {258 0 0-2304 {}} {258 0 0-2474 {}} {258 0 0-2477 {}} {258 0 0-2529 {}} {258 0 0-2565 {}} {258 0 0-2631 {}} {258 0 0-2636 {}}} CYCLES {}}
+set a(0-2289) {NAME ACC1-3:slc(acc.imod#6)#2 TYPE READSLICE PAR 0-1913 XREFS 15985 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{259 0 0-2288 {}}} SUCCS {{259 0 0-2290 {}}} CYCLES {}}
+set a(0-2290) {NAME ACC1:conc#387 TYPE CONCATENATE PAR 0-1913 XREFS 15986 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{259 0 0-2289 {}}} SUCCS {{258 0 0-2294 {}}} CYCLES {}}
+set a(0-2291) {NAME ACC1-3:slc(acc.imod#6)#3 TYPE READSLICE PAR 0-1913 XREFS 15987 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{258 0 0-2288 {}}} SUCCS {{259 0 0-2292 {}}} CYCLES {}}
+set a(0-2292) {NAME ACC1-3:not#47 TYPE NOT PAR 0-1913 XREFS 15988 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{259 0 0-2291 {}}} SUCCS {{259 0 0-2293 {}}} CYCLES {}}
+set a(0-2293) {NAME ACC1:conc#388 TYPE CONCATENATE PAR 0-1913 XREFS 15989 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 1 0.95921695} PREDS {{259 0 0-2292 {}}} SUCCS {{259 0 0-2294 {}}} CYCLES {}}
+set a(0-2294) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#202 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 15990 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 1 0.6570453850894752 1 0.9999999600894752} PREDS {{258 0 0-2290 {}} {259 0 0-2293 {}}} SUCCS {{259 0 0-2295 {}}} CYCLES {}}
+set a(0-2295) {NAME ACC1:slc#50 TYPE READSLICE PAR 0-1913 XREFS 15991 LOC {1 0.590976125 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{259 0 0-2294 {}}} SUCCS {{259 0 0-2296 {}}} CYCLES {}}
+set a(0-2296) {NAME ACC1:conc#389 TYPE CONCATENATE PAR 0-1913 XREFS 15992 LOC {1 0.590976125 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{259 0 0-2295 {}}} SUCCS {{258 0 0-2302 {}}} CYCLES {}}
+set a(0-2297) {NAME ACC1-3:slc(acc.imod#6)#1 TYPE READSLICE PAR 0-1913 XREFS 15993 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 2 0.028877375} PREDS {{258 0 0-2288 {}}} SUCCS {{259 0 0-2298 {}}} CYCLES {}}
+set a(0-2298) {NAME ACC1-3:not#46 TYPE NOT PAR 0-1913 XREFS 15994 LOC {1 0.5501930749999999 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{259 0 0-2297 {}}} SUCCS {{258 0 0-2301 {}}} CYCLES {}}
+set a(0-2299) {NAME ACC1-3:slc(acc.imod#6)#4 TYPE READSLICE PAR 0-1913 XREFS 15995 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 2 0.028877375} PREDS {{258 0 0-2288 {}}} SUCCS {{259 0 0-2300 {}}} CYCLES {}}
+set a(0-2300) {NAME ACC1-3:not#48 TYPE NOT PAR 0-1913 XREFS 15996 LOC {1 0.5501930749999999 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{259 0 0-2299 {}}} SUCCS {{259 0 0-2301 {}}} CYCLES {}}
+set a(0-2301) {NAME ACC1:conc#390 TYPE CONCATENATE PAR 0-1913 XREFS 15997 LOC {1 0.5501930749999999 1 0.657045425 1 0.657045425 2 0.028877375} PREDS {{258 0 0-2298 {}} {259 0 0-2300 {}}} SUCCS {{259 0 0-2302 {}}} CYCLES {}}
+set a(0-2302) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#203 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 15998 LOC {1 0.590976125 1 0.657045425 1 0.657045425 1 0.7046015520708271 2 0.07643350207082718} PREDS {{258 0 0-2296 {}} {259 0 0-2301 {}}} SUCCS {{259 0 0-2303 {}}} CYCLES {}}
+set a(0-2303) {NAME ACC1:slc#51 TYPE READSLICE PAR 0-1913 XREFS 15999 LOC {1 0.6385322999999999 1 0.7046015999999999 1 0.7046015999999999 2 0.07643355} PREDS {{259 0 0-2302 {}}} SUCCS {{258 0 0-2306 {}}} CYCLES {}}
+set a(0-2304) {NAME ACC1-3:slc(acc.imod#6) TYPE READSLICE PAR 0-1913 XREFS 16000 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 2 0.07643355} PREDS {{258 0 0-2288 {}}} SUCCS {{259 0 0-2305 {}}} CYCLES {}}
+set a(0-2305) {NAME ACC1:conc#386 TYPE CONCATENATE PAR 0-1913 XREFS 16001 LOC {1 0.5501930749999999 1 0.7046015999999999 1 0.7046015999999999 2 0.07643355} PREDS {{259 0 0-2304 {}}} SUCCS {{259 0 0-2306 {}}} CYCLES {}}
+set a(0-2306) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1-3:acc#28 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16002 LOC {1 0.6385322999999999 1 0.7046015999999999 1 0.7046015999999999 1 0.7521577270708271 2 0.12398967707082717} PREDS {{258 0 0-2303 {}} {259 0 0-2305 {}}} SUCCS {{258 0 0-2532 {}} {258 0 0-2539 {}} {258 0 0-2541 {}} {258 0 0-2543 {}} {258 0 0-2640 {}}} CYCLES {}}
+set a(0-2307) {NAME ACC1:slc(acc.idiv)#89 TYPE READSLICE PAR 0-1913 XREFS 16003 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.562272425} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2309 {}}} CYCLES {}}
+set a(0-2308) {NAME ACC1:slc(acc.idiv#2)#89 TYPE READSLICE PAR 0-1913 XREFS 16004 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.562272425} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2309 {}}} CYCLES {}}
+set a(0-2309) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#144 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16005 LOC {1 0.29058164999999997 1 0.45666265 1 0.45666265 1 0.48827348625 2 0.59388326125} PREDS {{258 0 0-2307 {}} {259 0 0-2308 {}}} SUCCS {{259 0 0-2310 {}}} CYCLES {}}
+set a(0-2310) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,11,0,12) AREA_SCORE 330.25 QUANTITY 3 NAME ACC1:mul#101 TYPE MUL DELAY {3.18 ns} LIBRARY_DELAY {3.18 ns} PAR 0-1913 XREFS 16006 LOC {1 0.322192525 1 0.488273525 1 0.488273525 1 0.68710065 2 0.792710425} PREDS {{259 0 0-2309 {}}} SUCCS {{258 0 0-2314 {}}} CYCLES {}}
+set a(0-2311) {NAME ACC1:slc(acc.imod#25)#9 TYPE READSLICE PAR 0-1913 XREFS 16007 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 2 0.7927104749999999} PREDS {{258 0 0-2080 {}}} SUCCS {{258 0 0-2314 {}}} CYCLES {}}
+set a(0-2312) {NAME ACC1-3:slc(acc.idiv)#106 TYPE READSLICE PAR 0-1913 XREFS 16008 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.7927104749999999} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2313 {}}} CYCLES {}}
+set a(0-2313) {NAME ACC1-3:exs#6 TYPE SIGNEXTEND PAR 0-1913 XREFS 16009 LOC {1 0.29058164999999997 1 0.6871007 1 0.6871007 2 0.7927104749999999} PREDS {{259 0 0-2312 {}}} SUCCS {{259 0 0-2314 {}}} CYCLES {}}
+set a(0-2314) {NAME ACC1:conc#277 TYPE CONCATENATE PAR 0-1913 XREFS 16010 LOC {1 0.5210197 1 0.6871007 1 0.6871007 2 0.7927104749999999} PREDS {{258 0 0-2311 {}} {258 0 0-2310 {}} {259 0 0-2313 {}}} SUCCS {{258 0 0-2330 {}}} CYCLES {}}
+set a(0-2315) {NAME ACC1:slc(acc.idiv#3)#34 TYPE READSLICE PAR 0-1913 XREFS 16011 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.468569725} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2317 {}}} CYCLES {}}
+set a(0-2316) {NAME ACC1:slc(acc.idiv#7)#12 TYPE READSLICE PAR 0-1913 XREFS 16012 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.468569725} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2317 {}}} CYCLES {}}
+set a(0-2317) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#138 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16013 LOC {1 0.21521084999999998 1 0.36295995 1 0.36295995 1 0.39457078624999997 2 0.50018056125} PREDS {{258 0 0-2315 {}} {259 0 0-2316 {}}} SUCCS {{259 0 0-2318 {}}} CYCLES {}}
+set a(0-2318) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,11,0,12) AREA_SCORE 330.25 QUANTITY 3 NAME ACC1:mul#95 TYPE MUL DELAY {3.18 ns} LIBRARY_DELAY {3.18 ns} PAR 0-1913 XREFS 16014 LOC {1 0.246821725 1 0.39457082499999996 1 0.39457082499999996 1 0.59339795 2 0.699007725} PREDS {{259 0 0-2317 {}}} SUCCS {{258 0 0-2320 {}}} CYCLES {}}
+set a(0-2319) {NAME ACC1:slc(acc.imod)#27 TYPE READSLICE PAR 0-1913 XREFS 16015 LOC {1 0.554379725 1 0.593398 1 0.593398 2 0.699007775} PREDS {{258 0 0-2190 {}}} SUCCS {{259 0 0-2320 {}}} CYCLES {}}
+set a(0-2320) {NAME ACC1:conc#253 TYPE CONCATENATE PAR 0-1913 XREFS 16016 LOC {1 0.554379725 1 0.593398 1 0.593398 2 0.699007775} PREDS {{258 0 0-2318 {}} {259 0 0-2319 {}}} SUCCS {{258 0 0-2329 {}}} CYCLES {}}
+set a(0-2321) {NAME ACC1:slc(acc.idiv)#88 TYPE READSLICE PAR 0-1913 XREFS 16017 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.47713687499999996} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2323 {}}} CYCLES {}}
+set a(0-2322) {NAME ACC1:slc(acc.idiv#2)#88 TYPE READSLICE PAR 0-1913 XREFS 16018 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.47713687499999996} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2323 {}}} CYCLES {}}
+set a(0-2323) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#143 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16019 LOC {1 0.29058164999999997 1 0.3715271 1 0.3715271 1 0.40313793625 2 0.50874771125} PREDS {{258 0 0-2321 {}} {259 0 0-2322 {}}} SUCCS {{259 0 0-2324 {}}} CYCLES {}}
+set a(0-2324) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 5 NAME ACC1:mul#100 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-1913 XREFS 16020 LOC {1 0.322192525 1 0.403137975 1 0.403137975 1 0.59339795625 2 0.6990077312499999} PREDS {{259 0 0-2323 {}}} SUCCS {{258 0 0-2328 {}}} CYCLES {}}
+set a(0-2325) {NAME ACC1:slc(acc.idiv#7)#19 TYPE READSLICE PAR 0-1913 XREFS 16021 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.699007775} PREDS {{258 0 0-2017 {}}} SUCCS {{258 0 0-2328 {}}} CYCLES {}}
+set a(0-2326) {NAME ACC1-2:slc(acc.idiv)#109 TYPE READSLICE PAR 0-1913 XREFS 16022 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.699007775} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2327 {}}} CYCLES {}}
+set a(0-2327) {NAME ACC1-2:exs TYPE SIGNEXTEND PAR 0-1913 XREFS 16023 LOC {1 0.21521084999999998 1 0.593398 1 0.593398 2 0.699007775} PREDS {{259 0 0-2326 {}}} SUCCS {{259 0 0-2328 {}}} CYCLES {}}
+set a(0-2328) {NAME ACC1:conc#276 TYPE CONCATENATE PAR 0-1913 XREFS 16024 LOC {1 0.51245255 1 0.593398 1 0.593398 2 0.699007775} PREDS {{258 0 0-2325 {}} {258 0 0-2324 {}} {259 0 0-2327 {}}} SUCCS {{259 0 0-2329 {}}} CYCLES {}}
+set a(0-2329) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,0,13,0,14) AREA_SCORE 14.22 QUANTITY 1 NAME ACC1:acc#272 TYPE ACCU DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-1913 XREFS 16025 LOC {1 0.554379725 1 0.593398 1 0.593398 1 0.6871006620503581 2 0.7927104370503582} PREDS {{258 0 0-2320 {}} {259 0 0-2328 {}}} SUCCS {{259 0 0-2330 {}}} CYCLES {}}
+set a(0-2330) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(15,0,15,0,16) AREA_SCORE 16.20 QUANTITY 2 NAME ACC1:acc#275 TYPE ACCU DELAY {1.63 ns} LIBRARY_DELAY {1.63 ns} PAR 0-1913 XREFS 16026 LOC {1 0.648082425 1 0.6871007 1 0.6871007 1 0.7887803903177633 2 0.8943901653177632} PREDS {{258 0 0-2314 {}} {259 0 0-2329 {}}} SUCCS {{258 0 0-2337 {}}} CYCLES {}}
+set a(0-2331) {NAME slc(acc.idiv#3) TYPE READSLICE PAR 0-1913 XREFS 16027 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.6532966499999999} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2333 {}}} CYCLES {}}
+set a(0-2332) {NAME ACC1:slc(acc.idiv#7)#14 TYPE READSLICE PAR 0-1913 XREFS 16028 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.6532966499999999} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2333 {}}} CYCLES {}}
+set a(0-2333) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#140 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16029 LOC {1 0.21521084999999998 1 0.547686875 1 0.547686875 1 0.57929771125 2 0.68490748625} PREDS {{258 0 0-2331 {}} {259 0 0-2332 {}}} SUCCS {{259 0 0-2334 {}}} CYCLES {}}
+set a(0-2334) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,15,0,16) AREA_SCORE 330.25 QUANTITY 2 NAME ACC1:mul#97 TYPE MUL DELAY {3.35 ns} LIBRARY_DELAY {3.35 ns} PAR 0-1913 XREFS 16030 LOC {1 0.246821725 1 0.57929775 1 0.57929775 1 0.7887803999999999 2 0.894390175} PREDS {{259 0 0-2333 {}}} SUCCS {{258 0 0-2336 {}}} CYCLES {}}
+set a(0-2335) {NAME ACC1:slc(acc.imod#1) TYPE READSLICE PAR 0-1913 XREFS 16031 LOC {1 0.690275125 1 0.7521577749999999 1 0.7521577749999999 2 0.894390225} PREDS {{258 0 0-2208 {}}} SUCCS {{259 0 0-2336 {}}} CYCLES {}}
+set a(0-2336) {NAME ACC1:conc#255 TYPE CONCATENATE PAR 0-1913 XREFS 16032 LOC {1 0.690275125 1 0.78878045 1 0.78878045 2 0.894390225} PREDS {{258 0 0-2334 {}} {259 0 0-2335 {}}} SUCCS {{259 0 0-2337 {}}} CYCLES {}}
+set a(0-2337) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,17) AREA_SCORE 17.19 QUANTITY 9 NAME ACC1:acc#279 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-1913 XREFS 16033 LOC {1 0.749762175 1 0.78878045 1 0.78878045 1 0.894390180357901 2 0.999999955357901} PREDS {{258 0 0-2330 {}} {259 0 0-2336 {}}} SUCCS {{258 0 0-2355 {}}} CYCLES {}}
+set a(0-2338) {NAME ACC1:slc(acc.idiv#3)#40 TYPE READSLICE PAR 0-1913 XREFS 16034 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.58156305} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2340 {}}} CYCLES {}}
+set a(0-2339) {NAME ACC1:slc(acc.idiv#7)#23 TYPE READSLICE PAR 0-1913 XREFS 16035 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.58156305} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2340 {}}} CYCLES {}}
+set a(0-2340) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#150 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16036 LOC {1 0.21521084999999998 1 0.47595327499999995 1 0.47595327499999995 1 0.50756411125 2 0.61317388625} PREDS {{258 0 0-2338 {}} {259 0 0-2339 {}}} SUCCS {{258 0 0-2342 {}}} CYCLES {}}
+set a(0-2341) {NAME ACC1:slc(acc.idiv#7)#24 TYPE READSLICE PAR 0-1913 XREFS 16037 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.613173925} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2342 {}}} CYCLES {}}
+set a(0-2342) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#149 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16038 LOC {1 0.246821725 1 0.50756415 1 0.50756415 1 0.5483471600894753 2 0.6539569350894753} PREDS {{258 0 0-2340 {}} {259 0 0-2341 {}}} SUCCS {{258 0 0-2344 {}}} CYCLES {}}
+set a(0-2343) {NAME slc(acc.idiv#3)#1 TYPE READSLICE PAR 0-1913 XREFS 16039 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.6539569749999999} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2344 {}}} CYCLES {}}
+set a(0-2344) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#148 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16040 LOC {1 0.287604775 1 0.5483471999999999 1 0.5483471999999999 1 0.5891302100894752 2 0.6947399850894752} PREDS {{258 0 0-2342 {}} {259 0 0-2343 {}}} SUCCS {{259 0 0-2345 {}}} CYCLES {}}
+set a(0-2345) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,11,0,12) AREA_SCORE 330.25 QUANTITY 1 NAME ACC1:mul#105 TYPE MUL DELAY {3.19 ns} LIBRARY_DELAY {3.19 ns} PAR 0-1913 XREFS 16041 LOC {1 0.32838782499999997 1 0.58913025 1 0.58913025 1 0.7887804124704548 2 0.8943901874704548} PREDS {{259 0 0-2344 {}}} SUCCS {{258 0 0-2349 {}}} CYCLES {}}
+set a(0-2346) {NAME ACC1:slc(acc.idiv#2)#91 TYPE READSLICE PAR 0-1913 XREFS 16042 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.894390225} PREDS {{258 0 0-2225 {}}} SUCCS {{258 0 0-2349 {}}} CYCLES {}}
+set a(0-2347) {NAME ACC1-2:slc(acc.idiv)#113 TYPE READSLICE PAR 0-1913 XREFS 16043 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.894390225} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2348 {}}} CYCLES {}}
+set a(0-2348) {NAME ACC1-2:exs#1 TYPE SIGNEXTEND PAR 0-1913 XREFS 16044 LOC {1 0.21521084999999998 1 0.78878045 1 0.78878045 2 0.894390225} PREDS {{259 0 0-2347 {}}} SUCCS {{259 0 0-2349 {}}} CYCLES {}}
+set a(0-2349) {NAME ACC1:conc#283 TYPE CONCATENATE PAR 0-1913 XREFS 16045 LOC {1 0.528038025 1 0.78878045 1 0.78878045 2 0.894390225} PREDS {{258 0 0-2346 {}} {258 0 0-2345 {}} {259 0 0-2348 {}}} SUCCS {{258 0 0-2354 {}}} CYCLES {}}
+set a(0-2350) {NAME ACC1:slc(acc.idiv)#94 TYPE READSLICE PAR 0-1913 XREFS 16046 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.6532966499999999} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2352 {}}} CYCLES {}}
+set a(0-2351) {NAME ACC1:slc(acc.idiv#2)#94 TYPE READSLICE PAR 0-1913 XREFS 16047 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.6532966499999999} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2352 {}}} CYCLES {}}
+set a(0-2352) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#151 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16048 LOC {1 0.29058164999999997 1 0.547686875 1 0.547686875 1 0.57929771125 2 0.68490748625} PREDS {{258 0 0-2350 {}} {259 0 0-2351 {}}} SUCCS {{259 0 0-2353 {}}} CYCLES {}}
+set a(0-2353) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,15,0,16) AREA_SCORE 330.25 QUANTITY 2 NAME mul TYPE MUL DELAY {3.35 ns} LIBRARY_DELAY {3.35 ns} PAR 0-1913 XREFS 16049 LOC {1 0.322192525 1 0.57929775 1 0.57929775 1 0.7887803999999999 2 0.894390175} PREDS {{259 0 0-2352 {}}} SUCCS {{259 0 0-2354 {}}} CYCLES {}}
+set a(0-2354) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,17) AREA_SCORE 17.19 QUANTITY 9 NAME ACC1:acc#278 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-1913 XREFS 16050 LOC {1 0.531675225 1 0.78878045 1 0.78878045 1 0.894390180357901 2 0.999999955357901} PREDS {{258 0 0-2349 {}} {259 0 0-2353 {}}} SUCCS {{259 0 0-2355 {}}} CYCLES {}}
+set a(0-2355) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,17) AREA_SCORE 17.19 QUANTITY 9 NAME ACC1:acc#281 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-1913 XREFS 16051 LOC {1 0.85537195 1 0.894390225 1 0.894390225 1 0.999999955357901 3 0.181465755357901} PREDS {{258 0 0-2337 {}} {259 0 0-2354 {}}} SUCCS {{258 0 0-2727 {}}} CYCLES {}}
+set a(0-2356) {NAME ACC1:slc(acc.idiv)#95 TYPE READSLICE PAR 0-1913 XREFS 16052 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.6585291} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2358 {}}} CYCLES {}}
+set a(0-2357) {NAME ACC1:slc(acc.idiv#2)#95 TYPE READSLICE PAR 0-1913 XREFS 16053 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.6585291} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2358 {}}} CYCLES {}}
+set a(0-2358) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#152 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16054 LOC {1 0.29058164999999997 1 0.7642342 1 0.7642342 1 0.79584503625 2 0.69013993625} PREDS {{258 0 0-2356 {}} {259 0 0-2357 {}}} SUCCS {{259 0 0-2359 {}}} CYCLES {}}
+set a(0-2359) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,13,0,14) AREA_SCORE 330.25 QUANTITY 3 NAME mul#1 TYPE MUL DELAY {3.27 ns} LIBRARY_DELAY {3.27 ns} PAR 0-1913 XREFS 16055 LOC {1 0.322192525 1 0.795845075 1 0.795845075 1 0.9999999625 2 0.8942948625} PREDS {{259 0 0-2358 {}}} SUCCS {{258 0 0-2362 {}}} CYCLES {}}
+set a(0-2360) {NAME ACC1-2:slc(acc.idiv)#131 TYPE READSLICE PAR 0-1913 XREFS 16056 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.8942949} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2361 {}}} CYCLES {}}
+set a(0-2361) {NAME ACC1-2:exs#4 TYPE SIGNEXTEND PAR 0-1913 XREFS 16057 LOC {1 0.21521084999999998 2 0.52357235 2 0.52357235 2 0.8942949} PREDS {{259 0 0-2360 {}}} SUCCS {{259 0 0-2362 {}}} CYCLES {}}
+set a(0-2362) {NAME ACC1:conc#288 TYPE CONCATENATE PAR 0-1913 XREFS 16058 LOC {1 0.5263474499999999 2 0.52357235 2 0.52357235 2 0.8942949} PREDS {{258 0 0-2359 {}} {259 0 0-2361 {}}} SUCCS {{258 0 0-2503 {}}} CYCLES {}}
+set a(0-2363) {NAME ACC1:slc(acc.idiv)#87 TYPE READSLICE PAR 0-1913 XREFS 16059 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.4421445} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2365 {}}} CYCLES {}}
+set a(0-2364) {NAME ACC1:slc(acc.idiv#2)#87 TYPE READSLICE PAR 0-1913 XREFS 16060 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.4421445} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2365 {}}} CYCLES {}}
+set a(0-2365) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#142 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16061 LOC {1 0.29058164999999997 1 0.7802174749999999 1 0.7802174749999999 1 0.81182831125 2 0.47375533625} PREDS {{258 0 0-2363 {}} {259 0 0-2364 {}}} SUCCS {{259 0 0-2366 {}}} CYCLES {}}
+set a(0-2366) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,7,0,8) AREA_SCORE 330.25 QUANTITY 4 NAME ACC1:mul#99 TYPE MUL DELAY {3.01 ns} LIBRARY_DELAY {3.01 ns} PAR 0-1913 XREFS 16062 LOC {1 0.322192525 1 0.81182835 1 0.81182835 1 0.99999995 2 0.661926975} PREDS {{259 0 0-2365 {}}} SUCCS {{258 0 0-2370 {}}} CYCLES {}}
+set a(0-2367) {NAME ACC1:slc(acc.imod#17)#8 TYPE READSLICE PAR 0-1913 XREFS 16063 LOC {1 0.479008925 1 0.6214090999999999 1 0.6214090999999999 2 0.661927025} PREDS {{258 0 0-1991 {}}} SUCCS {{258 0 0-2370 {}}} CYCLES {}}
+set a(0-2368) {NAME ACC1-2:slc(acc.idiv)#106 TYPE READSLICE PAR 0-1913 XREFS 16064 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.661927025} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2369 {}}} CYCLES {}}
+set a(0-2369) {NAME ACC1-2:exs#6 TYPE SIGNEXTEND PAR 0-1913 XREFS 16065 LOC {1 0.21521084999999998 2 0.29120447499999996 2 0.29120447499999996 2 0.661927025} PREDS {{259 0 0-2368 {}}} SUCCS {{259 0 0-2370 {}}} CYCLES {}}
+set a(0-2370) {NAME ACC1:conc#275 TYPE CONCATENATE PAR 0-1913 XREFS 16066 LOC {1 0.510364175 2 0.29120447499999996 2 0.29120447499999996 2 0.661927025} PREDS {{258 0 0-2367 {}} {258 0 0-2366 {}} {259 0 0-2369 {}}} SUCCS {{258 0 0-2492 {}}} CYCLES {}}
+set a(0-2371) {NAME ACC1-3:slc(acc.idiv)#118 TYPE READSLICE PAR 0-1913 XREFS 16067 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.499255075} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2372 {}}} CYCLES {}}
+set a(0-2372) {NAME ACC1-3:exs#2 TYPE SIGNEXTEND PAR 0-1913 XREFS 16068 LOC {1 0.29058164999999997 1 0.83732805 1 0.83732805 2 0.499255075} PREDS {{259 0 0-2371 {}}} SUCCS {{259 0 0-2373 {}}} CYCLES {}}
+set a(0-2373) {NAME ACC1:conc#391 TYPE CONCATENATE PAR 0-1913 XREFS 16069 LOC {1 0.29058164999999997 1 0.83732805 1 0.83732805 2 0.499255075} PREDS {{259 0 0-2372 {}}} SUCCS {{258 0 0-2380 {}}} CYCLES {}}
+set a(0-2374) {NAME ACC1:slc(acc.idiv#3)#31 TYPE READSLICE PAR 0-1913 XREFS 16070 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.28976235} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2376 {}}} CYCLES {}}
+set a(0-2375) {NAME ACC1:slc(acc.idiv#7) TYPE READSLICE PAR 0-1913 XREFS 16071 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.28976235} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2376 {}}} CYCLES {}}
+set a(0-2376) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#135 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16072 LOC {1 0.21521084999999998 1 0.6278353249999999 1 0.6278353249999999 1 0.65944616125 2 0.32137318625} PREDS {{258 0 0-2374 {}} {259 0 0-2375 {}}} SUCCS {{259 0 0-2377 {}}} CYCLES {}}
+set a(0-2377) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 5 NAME ACC1:mul#92 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-1913 XREFS 16073 LOC {1 0.246821725 1 0.6594462 1 0.6594462 1 0.8373279921744312 2 0.4992550171744312} PREDS {{259 0 0-2376 {}}} SUCCS {{258 0 0-2379 {}}} CYCLES {}}
+set a(0-2378) {NAME ACC1:slc(acc.idiv#2)#84 TYPE READSLICE PAR 0-1913 XREFS 16074 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.499255075} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2379 {}}} CYCLES {}}
+set a(0-2379) {NAME ACC1:conc#250 TYPE CONCATENATE PAR 0-1913 XREFS 16075 LOC {1 0.424703575 1 0.83732805 1 0.83732805 2 0.499255075} PREDS {{258 0 0-2377 {}} {259 0 0-2378 {}}} SUCCS {{259 0 0-2380 {}}} CYCLES {}}
+set a(0-2380) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 2 NAME ACC1:acc#259 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-1913 XREFS 16076 LOC {1 0.424703575 1 0.83732805 1 0.83732805 1 0.8852071129329679 2 0.547134137932968} PREDS {{258 0 0-2373 {}} {259 0 0-2379 {}}} SUCCS {{258 0 0-2484 {}}} CYCLES {}}
+set a(0-2381) {NAME ACC1-1:slc(acc.idiv)#124 TYPE READSLICE PAR 0-1913 XREFS 16077 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.283336125} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2382 {}}} CYCLES {}}
+set a(0-2382) {NAME ACC1-1:exs#3 TYPE SIGNEXTEND PAR 0-1913 XREFS 16078 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2381 {}}} SUCCS {{258 0 0-2385 {}}} CYCLES {}}
+set a(0-2383) {NAME ACC1-1:slc(acc.idiv)#131 TYPE READSLICE PAR 0-1913 XREFS 16079 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.283336125} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2384 {}}} CYCLES {}}
+set a(0-2384) {NAME ACC1-1:exs#4 TYPE SIGNEXTEND PAR 0-1913 XREFS 16080 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2383 {}}} SUCCS {{259 0 0-2385 {}}} CYCLES {}}
+set a(0-2385) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#227 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16081 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2382 {}} {259 0 0-2384 {}}} SUCCS {{258 0 0-2391 {}}} CYCLES {}}
+set a(0-2386) {NAME ACC1-1:slc(acc.idiv)#132 TYPE READSLICE PAR 0-1913 XREFS 16082 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.283336125} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2387 {}}} CYCLES {}}
+set a(0-2387) {NAME ACC1-1:exs#5 TYPE SIGNEXTEND PAR 0-1913 XREFS 16083 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2386 {}}} SUCCS {{258 0 0-2390 {}}} CYCLES {}}
+set a(0-2388) {NAME ACC1-1:slc(acc.idiv#2)#106 TYPE READSLICE PAR 0-1913 XREFS 16084 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2389 {}}} CYCLES {}}
+set a(0-2389) {NAME ACC1-1:exs#20 TYPE SIGNEXTEND PAR 0-1913 XREFS 16085 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2388 {}}} SUCCS {{259 0 0-2390 {}}} CYCLES {}}
+set a(0-2390) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#226 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16086 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2387 {}} {259 0 0-2389 {}}} SUCCS {{259 0 0-2391 {}}} CYCLES {}}
+set a(0-2391) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#241 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16087 LOC {1 0.2559939 1 0.66219215 1 0.66219215 1 0.7097482770708271 2 0.37167530207082716} PREDS {{258 0 0-2385 {}} {259 0 0-2390 {}}} SUCCS {{258 0 0-2403 {}}} CYCLES {}}
+set a(0-2392) {NAME ACC1-1:slc(acc.idiv#2)#109 TYPE READSLICE PAR 0-1913 XREFS 16088 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2393 {}}} CYCLES {}}
+set a(0-2393) {NAME ACC1-1:exs#14 TYPE SIGNEXTEND PAR 0-1913 XREFS 16089 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2392 {}}} SUCCS {{258 0 0-2396 {}}} CYCLES {}}
+set a(0-2394) {NAME ACC1-1:slc(acc.idiv#2)#113 TYPE READSLICE PAR 0-1913 XREFS 16090 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2395 {}}} CYCLES {}}
+set a(0-2395) {NAME ACC1-1:exs#15 TYPE SIGNEXTEND PAR 0-1913 XREFS 16091 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2394 {}}} SUCCS {{259 0 0-2396 {}}} CYCLES {}}
+set a(0-2396) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#225 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16092 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2393 {}} {259 0 0-2395 {}}} SUCCS {{258 0 0-2402 {}}} CYCLES {}}
+set a(0-2397) {NAME ACC1-1:slc(acc.idiv#2)#118 TYPE READSLICE PAR 0-1913 XREFS 16093 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2398 {}}} CYCLES {}}
+set a(0-2398) {NAME ACC1-1:exs#16 TYPE SIGNEXTEND PAR 0-1913 XREFS 16094 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2397 {}}} SUCCS {{258 0 0-2401 {}}} CYCLES {}}
+set a(0-2399) {NAME ACC1-1:slc(acc.idiv#2)#124 TYPE READSLICE PAR 0-1913 XREFS 16095 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2400 {}}} CYCLES {}}
+set a(0-2400) {NAME ACC1-1:exs#17 TYPE SIGNEXTEND PAR 0-1913 XREFS 16096 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2399 {}}} SUCCS {{259 0 0-2401 {}}} CYCLES {}}
+set a(0-2401) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#224 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16097 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2398 {}} {259 0 0-2400 {}}} SUCCS {{259 0 0-2402 {}}} CYCLES {}}
+set a(0-2402) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#240 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16098 LOC {1 0.2559939 1 0.66219215 1 0.66219215 1 0.7097482770708271 2 0.37167530207082716} PREDS {{258 0 0-2396 {}} {259 0 0-2401 {}}} SUCCS {{259 0 0-2403 {}}} CYCLES {}}
+set a(0-2403) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 13 NAME ACC1:acc#249 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1913 XREFS 16099 LOC {1 0.303550075 1 0.709748325 1 0.709748325 1 0.7630953451789504 2 0.42502237017895045} PREDS {{258 0 0-2391 {}} {259 0 0-2402 {}}} SUCCS {{258 0 0-2427 {}}} CYCLES {}}
+set a(0-2404) {NAME ACC1-1:slc(acc.idiv#2)#131 TYPE READSLICE PAR 0-1913 XREFS 16100 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2405 {}}} CYCLES {}}
+set a(0-2405) {NAME ACC1-1:exs#18 TYPE SIGNEXTEND PAR 0-1913 XREFS 16101 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2404 {}}} SUCCS {{258 0 0-2408 {}}} CYCLES {}}
+set a(0-2406) {NAME ACC1-1:slc(acc.idiv#2)#132 TYPE READSLICE PAR 0-1913 XREFS 16102 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2407 {}}} CYCLES {}}
+set a(0-2407) {NAME ACC1-1:exs#19 TYPE SIGNEXTEND PAR 0-1913 XREFS 16103 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2406 {}}} SUCCS {{259 0 0-2408 {}}} CYCLES {}}
+set a(0-2408) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#223 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16104 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2405 {}} {259 0 0-2407 {}}} SUCCS {{258 0 0-2414 {}}} CYCLES {}}
+set a(0-2409) {NAME ACC1-3:slc(acc.idiv#2)#109 TYPE READSLICE PAR 0-1913 XREFS 16105 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2410 {}}} CYCLES {}}
+set a(0-2410) {NAME ACC1-3:exs#14 TYPE SIGNEXTEND PAR 0-1913 XREFS 16106 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2409 {}}} SUCCS {{258 0 0-2413 {}}} CYCLES {}}
+set a(0-2411) {NAME ACC1-3:slc(acc.idiv#2)#113 TYPE READSLICE PAR 0-1913 XREFS 16107 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2412 {}}} CYCLES {}}
+set a(0-2412) {NAME ACC1-3:exs#15 TYPE SIGNEXTEND PAR 0-1913 XREFS 16108 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2411 {}}} SUCCS {{259 0 0-2413 {}}} CYCLES {}}
+set a(0-2413) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#222 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16109 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2410 {}} {259 0 0-2412 {}}} SUCCS {{259 0 0-2414 {}}} CYCLES {}}
+set a(0-2414) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#239 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16110 LOC {1 0.32717805 1 0.66219215 1 0.66219215 1 0.7097482770708271 2 0.37167530207082716} PREDS {{258 0 0-2408 {}} {259 0 0-2413 {}}} SUCCS {{258 0 0-2426 {}}} CYCLES {}}
+set a(0-2415) {NAME ACC1-3:slc(acc.idiv#2)#118 TYPE READSLICE PAR 0-1913 XREFS 16111 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2416 {}}} CYCLES {}}
+set a(0-2416) {NAME ACC1-3:exs#16 TYPE SIGNEXTEND PAR 0-1913 XREFS 16112 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2415 {}}} SUCCS {{258 0 0-2419 {}}} CYCLES {}}
+set a(0-2417) {NAME ACC1-3:slc(acc.idiv#2)#124 TYPE READSLICE PAR 0-1913 XREFS 16113 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2418 {}}} CYCLES {}}
+set a(0-2418) {NAME ACC1-3:exs#17 TYPE SIGNEXTEND PAR 0-1913 XREFS 16114 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2417 {}}} SUCCS {{259 0 0-2419 {}}} CYCLES {}}
+set a(0-2419) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#221 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16115 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2416 {}} {259 0 0-2418 {}}} SUCCS {{258 0 0-2425 {}}} CYCLES {}}
+set a(0-2420) {NAME ACC1-3:slc(acc.idiv#2)#131 TYPE READSLICE PAR 0-1913 XREFS 16116 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2421 {}}} CYCLES {}}
+set a(0-2421) {NAME ACC1-3:exs#18 TYPE SIGNEXTEND PAR 0-1913 XREFS 16117 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2420 {}}} SUCCS {{258 0 0-2424 {}}} CYCLES {}}
+set a(0-2422) {NAME ACC1-3:slc(acc.idiv#2)#132 TYPE READSLICE PAR 0-1913 XREFS 16118 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2423 {}}} CYCLES {}}
+set a(0-2423) {NAME ACC1-3:exs#19 TYPE SIGNEXTEND PAR 0-1913 XREFS 16119 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2422 {}}} SUCCS {{259 0 0-2424 {}}} CYCLES {}}
+set a(0-2424) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#220 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16120 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2421 {}} {259 0 0-2423 {}}} SUCCS {{259 0 0-2425 {}}} CYCLES {}}
+set a(0-2425) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#238 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16121 LOC {1 0.32717805 1 0.66219215 1 0.66219215 1 0.7097482770708271 2 0.37167530207082716} PREDS {{258 0 0-2419 {}} {259 0 0-2424 {}}} SUCCS {{259 0 0-2426 {}}} CYCLES {}}
+set a(0-2426) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 13 NAME ACC1:acc#248 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1913 XREFS 16122 LOC {1 0.374734225 1 0.709748325 1 0.709748325 1 0.7630953451789504 2 0.42502237017895045} PREDS {{258 0 0-2414 {}} {259 0 0-2425 {}}} SUCCS {{259 0 0-2427 {}}} CYCLES {}}
+set a(0-2427) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 12 NAME ACC1:acc#254 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1913 XREFS 16123 LOC {1 0.4280813 1 0.7630954 1 0.7630954 1 0.821695109496936 2 0.48362213449693603} PREDS {{258 0 0-2403 {}} {259 0 0-2426 {}}} SUCCS {{258 0 0-2483 {}}} CYCLES {}}
+set a(0-2428) {NAME ACC1-2:slc(acc.idiv#2)#113 TYPE READSLICE PAR 0-1913 XREFS 16124 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2429 {}}} CYCLES {}}
+set a(0-2429) {NAME ACC1-2:exs#15 TYPE SIGNEXTEND PAR 0-1913 XREFS 16125 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2428 {}}} SUCCS {{258 0 0-2432 {}}} CYCLES {}}
+set a(0-2430) {NAME ACC1-2:slc(acc.idiv#2)#118 TYPE READSLICE PAR 0-1913 XREFS 16126 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2431 {}}} CYCLES {}}
+set a(0-2431) {NAME ACC1-2:exs#16 TYPE SIGNEXTEND PAR 0-1913 XREFS 16127 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2430 {}}} SUCCS {{259 0 0-2432 {}}} CYCLES {}}
+set a(0-2432) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#219 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16128 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2429 {}} {259 0 0-2431 {}}} SUCCS {{258 0 0-2438 {}}} CYCLES {}}
+set a(0-2433) {NAME ACC1-2:slc(acc.idiv#2)#124 TYPE READSLICE PAR 0-1913 XREFS 16129 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2434 {}}} CYCLES {}}
+set a(0-2434) {NAME ACC1-2:exs#17 TYPE SIGNEXTEND PAR 0-1913 XREFS 16130 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2433 {}}} SUCCS {{258 0 0-2437 {}}} CYCLES {}}
+set a(0-2435) {NAME ACC1-2:slc(acc.idiv#2)#131 TYPE READSLICE PAR 0-1913 XREFS 16131 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2436 {}}} CYCLES {}}
+set a(0-2436) {NAME ACC1-2:exs#18 TYPE SIGNEXTEND PAR 0-1913 XREFS 16132 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2435 {}}} SUCCS {{259 0 0-2437 {}}} CYCLES {}}
+set a(0-2437) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#218 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16133 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2434 {}} {259 0 0-2436 {}}} SUCCS {{259 0 0-2438 {}}} CYCLES {}}
+set a(0-2438) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#237 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16134 LOC {1 0.2559939 1 0.66219215 1 0.66219215 1 0.7097482770708271 2 0.37167530207082716} PREDS {{258 0 0-2432 {}} {259 0 0-2437 {}}} SUCCS {{258 0 0-2450 {}}} CYCLES {}}
+set a(0-2439) {NAME ACC1-2:slc(acc.idiv#2)#132 TYPE READSLICE PAR 0-1913 XREFS 16135 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2440 {}}} CYCLES {}}
+set a(0-2440) {NAME ACC1-2:exs#19 TYPE SIGNEXTEND PAR 0-1913 XREFS 16136 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2439 {}}} SUCCS {{258 0 0-2443 {}}} CYCLES {}}
+set a(0-2441) {NAME ACC1-2:slc(acc.idiv#2)#106 TYPE READSLICE PAR 0-1913 XREFS 16137 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2442 {}}} CYCLES {}}
+set a(0-2442) {NAME ACC1-2:exs#20 TYPE SIGNEXTEND PAR 0-1913 XREFS 16138 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2441 {}}} SUCCS {{259 0 0-2443 {}}} CYCLES {}}
+set a(0-2443) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#217 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16139 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2440 {}} {259 0 0-2442 {}}} SUCCS {{258 0 0-2449 {}}} CYCLES {}}
+set a(0-2444) {NAME ACC1-2:slc(acc.idiv#2)#109 TYPE READSLICE PAR 0-1913 XREFS 16140 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2445 {}}} CYCLES {}}
+set a(0-2445) {NAME ACC1-2:exs#14 TYPE SIGNEXTEND PAR 0-1913 XREFS 16141 LOC {1 0.21521084999999998 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2444 {}}} SUCCS {{258 0 0-2448 {}}} CYCLES {}}
+set a(0-2446) {NAME ACC1-3:slc(acc.idiv#2)#106 TYPE READSLICE PAR 0-1913 XREFS 16142 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2447 {}}} CYCLES {}}
+set a(0-2447) {NAME ACC1-3:exs#20 TYPE SIGNEXTEND PAR 0-1913 XREFS 16143 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{259 0 0-2446 {}}} SUCCS {{259 0 0-2448 {}}} CYCLES {}}
+set a(0-2448) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#216 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16144 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2445 {}} {259 0 0-2447 {}}} SUCCS {{259 0 0-2449 {}}} CYCLES {}}
+set a(0-2449) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#236 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16145 LOC {1 0.32717805 1 0.66219215 1 0.66219215 1 0.7097482770708271 2 0.37167530207082716} PREDS {{258 0 0-2443 {}} {259 0 0-2448 {}}} SUCCS {{259 0 0-2450 {}}} CYCLES {}}
+set a(0-2450) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 13 NAME ACC1:acc#247 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1913 XREFS 16146 LOC {1 0.374734225 1 0.709748325 1 0.709748325 1 0.7630953451789504 2 0.42502237017895045} PREDS {{258 0 0-2438 {}} {259 0 0-2449 {}}} SUCCS {{258 0 0-2482 {}}} CYCLES {}}
+set a(0-2451) {NAME ACC1:slc(acc.idiv)#81 TYPE READSLICE PAR 0-1913 XREFS 16147 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.283336125} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2453 {}}} CYCLES {}}
+set a(0-2452) {NAME ACC1:slc(acc.idiv)#82 TYPE READSLICE PAR 0-1913 XREFS 16148 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.283336125} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2453 {}}} CYCLES {}}
+set a(0-2453) {NAME ACC1:conc TYPE CONCATENATE PAR 0-1913 XREFS 16149 LOC {1 0.29058164999999997 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{258 0 0-2451 {}} {259 0 0-2452 {}}} SUCCS {{258 0 0-2457 {}}} CYCLES {}}
+set a(0-2454) {NAME ACC1:slc(acc.idiv#2)#81 TYPE READSLICE PAR 0-1913 XREFS 16150 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2225 {}}} SUCCS {{258 0 0-2456 {}}} CYCLES {}}
+set a(0-2455) {NAME ACC1:slc(acc.idiv)#83 TYPE READSLICE PAR 0-1913 XREFS 16151 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.283336125} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2456 {}}} CYCLES {}}
+set a(0-2456) {NAME ACC1:conc#245 TYPE CONCATENATE PAR 0-1913 XREFS 16152 LOC {1 0.29058164999999997 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{258 0 0-2454 {}} {259 0 0-2455 {}}} SUCCS {{259 0 0-2457 {}}} CYCLES {}}
+set a(0-2457) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#215 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16153 LOC {1 0.29058164999999997 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2453 {}} {259 0 0-2456 {}}} SUCCS {{258 0 0-2465 {}}} CYCLES {}}
+set a(0-2458) {NAME ACC1:slc(acc.idiv#3) TYPE READSLICE PAR 0-1913 XREFS 16154 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.283336125} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2460 {}}} CYCLES {}}
+set a(0-2459) {NAME ACC1:slc(acc.idiv)#84 TYPE READSLICE PAR 0-1913 XREFS 16155 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.283336125} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2460 {}}} CYCLES {}}
+set a(0-2460) {NAME ACC1:conc#246 TYPE CONCATENATE PAR 0-1913 XREFS 16156 LOC {1 0.29058164999999997 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{258 0 0-2458 {}} {259 0 0-2459 {}}} SUCCS {{258 0 0-2464 {}}} CYCLES {}}
+set a(0-2461) {NAME ACC1:slc(acc.idiv#3)#28 TYPE READSLICE PAR 0-1913 XREFS 16157 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.283336125} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2463 {}}} CYCLES {}}
+set a(0-2462) {NAME ACC1:slc(acc.idiv)#85 TYPE READSLICE PAR 0-1913 XREFS 16158 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.283336125} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2463 {}}} CYCLES {}}
+set a(0-2463) {NAME ACC1:conc#247 TYPE CONCATENATE PAR 0-1913 XREFS 16159 LOC {1 0.29058164999999997 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{258 0 0-2461 {}} {259 0 0-2462 {}}} SUCCS {{259 0 0-2464 {}}} CYCLES {}}
+set a(0-2464) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#214 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16160 LOC {1 0.29058164999999997 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2460 {}} {259 0 0-2463 {}}} SUCCS {{259 0 0-2465 {}}} CYCLES {}}
+set a(0-2465) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#235 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16161 LOC {1 0.3313647 1 0.66219215 1 0.66219215 1 0.7097482770708271 2 0.37167530207082716} PREDS {{258 0 0-2457 {}} {259 0 0-2464 {}}} SUCCS {{258 0 0-2481 {}}} CYCLES {}}
+set a(0-2466) {NAME ACC1:slc(acc.idiv#3)#29 TYPE READSLICE PAR 0-1913 XREFS 16162 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.283336125} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2468 {}}} CYCLES {}}
+set a(0-2467) {NAME ACC1:slc(acc.idiv#2)#82 TYPE READSLICE PAR 0-1913 XREFS 16163 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2468 {}}} CYCLES {}}
+set a(0-2468) {NAME ACC1:conc#248 TYPE CONCATENATE PAR 0-1913 XREFS 16164 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{258 0 0-2466 {}} {259 0 0-2467 {}}} SUCCS {{258 0 0-2472 {}}} CYCLES {}}
+set a(0-2469) {NAME ACC1:slc(acc.idiv#3)#30 TYPE READSLICE PAR 0-1913 XREFS 16165 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.283336125} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2471 {}}} CYCLES {}}
+set a(0-2470) {NAME ACC1:slc(acc.idiv#2)#83 TYPE READSLICE PAR 0-1913 XREFS 16166 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.283336125} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2471 {}}} CYCLES {}}
+set a(0-2471) {NAME ACC1:conc#249 TYPE CONCATENATE PAR 0-1913 XREFS 16167 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{258 0 0-2469 {}} {259 0 0-2470 {}}} SUCCS {{259 0 0-2472 {}}} CYCLES {}}
+set a(0-2472) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#213 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16168 LOC {1 0.286395 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2468 {}} {259 0 0-2471 {}}} SUCCS {{258 0 0-2480 {}}} CYCLES {}}
+set a(0-2473) {NAME ACC1:slc(acc.imod)#29 TYPE READSLICE PAR 0-1913 XREFS 16169 LOC {1 0.554379725 1 0.593398 1 0.593398 2 0.283336125} PREDS {{258 0 0-2190 {}}} SUCCS {{258 0 0-2475 {}}} CYCLES {}}
+set a(0-2474) {NAME ACC1:slc(acc.imod#6) TYPE READSLICE PAR 0-1913 XREFS 16170 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 2 0.283336125} PREDS {{258 0 0-2288 {}}} SUCCS {{259 0 0-2475 {}}} CYCLES {}}
+set a(0-2475) {NAME ACC1:conc#256 TYPE CONCATENATE PAR 0-1913 XREFS 16171 LOC {1 0.554379725 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{258 0 0-2473 {}} {259 0 0-2474 {}}} SUCCS {{258 0 0-2479 {}}} CYCLES {}}
+set a(0-2476) {NAME ACC1:slc(acc.imod#17) TYPE READSLICE PAR 0-1913 XREFS 16172 LOC {1 0.479008925 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{258 0 0-1991 {}}} SUCCS {{258 0 0-2478 {}}} CYCLES {}}
+set a(0-2477) {NAME ACC1:slc(acc.imod#6)#27 TYPE READSLICE PAR 0-1913 XREFS 16173 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 2 0.283336125} PREDS {{258 0 0-2288 {}}} SUCCS {{259 0 0-2478 {}}} CYCLES {}}
+set a(0-2478) {NAME ACC1:conc#257 TYPE CONCATENATE PAR 0-1913 XREFS 16174 LOC {1 0.5501930749999999 1 0.6214090999999999 1 0.6214090999999999 2 0.283336125} PREDS {{258 0 0-2476 {}} {259 0 0-2477 {}}} SUCCS {{259 0 0-2479 {}}} CYCLES {}}
+set a(0-2479) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#212 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16175 LOC {1 0.554379725 1 0.6214090999999999 1 0.6214090999999999 1 0.6621921100894752 2 0.3241191350894752} PREDS {{258 0 0-2475 {}} {259 0 0-2478 {}}} SUCCS {{259 0 0-2480 {}}} CYCLES {}}
+set a(0-2480) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#234 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16176 LOC {1 0.5951627749999999 1 0.66219215 1 0.66219215 1 0.7097482770708271 2 0.37167530207082716} PREDS {{258 0 0-2472 {}} {259 0 0-2479 {}}} SUCCS {{259 0 0-2481 {}}} CYCLES {}}
+set a(0-2481) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 13 NAME ACC1:acc#246 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1913 XREFS 16177 LOC {1 0.64271895 1 0.709748325 1 0.709748325 1 0.7630953451789504 2 0.42502237017895045} PREDS {{258 0 0-2465 {}} {259 0 0-2480 {}}} SUCCS {{259 0 0-2482 {}}} CYCLES {}}
+set a(0-2482) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 12 NAME ACC1:acc#253 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1913 XREFS 16178 LOC {1 0.6960660249999999 1 0.7630954 1 0.7630954 1 0.821695109496936 2 0.48362213449693603} PREDS {{258 0 0-2450 {}} {259 0 0-2481 {}}} SUCCS {{259 0 0-2483 {}}} CYCLES {}}
+set a(0-2483) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 3 NAME ACC1:acc#257 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-1913 XREFS 16179 LOC {1 0.754665775 1 0.8216951499999999 1 0.8216951499999999 1 0.8852071234103024 2 0.5471341484103024} PREDS {{258 0 0-2427 {}} {259 0 0-2482 {}}} SUCCS {{259 0 0-2484 {}}} CYCLES {}}
+set a(0-2484) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 2 NAME ACC1:acc#261 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-1913 XREFS 16180 LOC {1 0.8181778 1 0.885207175 1 0.885207175 1 0.933086237932968 2 0.595013262932968} PREDS {{258 0 0-2380 {}} {259 0 0-2483 {}}} SUCCS {{258 0 0-2491 {}}} CYCLES {}}
+set a(0-2485) {NAME ACC1:slc(acc.idiv#3)#32 TYPE READSLICE PAR 0-1913 XREFS 16181 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.3752308} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2487 {}}} CYCLES {}}
+set a(0-2486) {NAME ACC1:slc(acc.idiv#7)#10 TYPE READSLICE PAR 0-1913 XREFS 16182 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.3752308} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2487 {}}} CYCLES {}}
+set a(0-2487) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#136 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16183 LOC {1 0.21521084999999998 1 0.713303775 1 0.713303775 1 0.74491461125 2 0.40684163624999997} PREDS {{258 0 0-2485 {}} {259 0 0-2486 {}}} SUCCS {{259 0 0-2488 {}}} CYCLES {}}
+set a(0-2488) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,7,0,8) AREA_SCORE 330.25 QUANTITY 4 NAME ACC1:mul#93 TYPE MUL DELAY {3.01 ns} LIBRARY_DELAY {3.01 ns} PAR 0-1913 XREFS 16184 LOC {1 0.246821725 1 0.74491465 1 0.74491465 1 0.93308625 2 0.5950132749999999} PREDS {{259 0 0-2487 {}}} SUCCS {{258 0 0-2490 {}}} CYCLES {}}
+set a(0-2489) {NAME ACC1:slc(acc.idiv#2)#85 TYPE READSLICE PAR 0-1913 XREFS 16185 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.5950133249999999} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2490 {}}} CYCLES {}}
+set a(0-2490) {NAME ACC1:conc#251 TYPE CONCATENATE PAR 0-1913 XREFS 16186 LOC {1 0.43499337499999996 1 0.9330862999999999 1 0.9330862999999999 2 0.5950133249999999} PREDS {{258 0 0-2488 {}} {259 0 0-2489 {}}} SUCCS {{259 0 0-2491 {}}} CYCLES {}}
+set a(0-2491) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME ACC1:acc#264 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-1913 XREFS 16187 LOC {1 0.866056925 1 0.9330862999999999 1 0.9330862999999999 1 0.9999999378916543 2 0.6619269628916543} PREDS {{258 0 0-2484 {}} {259 0 0-2490 {}}} SUCCS {{259 0 0-2492 {}}} CYCLES {}}
+set a(0-2492) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,10,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME ACC1:acc#267 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1913 XREFS 16188 LOC {2 0.0 2 0.29120447499999996 2 0.29120447499999996 2 0.36668175931388314 2 0.7374043093138832} PREDS {{258 0 0-2370 {}} {259 0 0-2491 {}}} SUCCS {{258 0 0-2497 {}}} CYCLES {}}
+set a(0-2493) {NAME ACC1:slc(acc.idiv)#79 TYPE READSLICE PAR 0-1913 XREFS 16189 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.5069663} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2495 {}}} CYCLES {}}
+set a(0-2494) {NAME ACC1:slc(acc.idiv#2)#79 TYPE READSLICE PAR 0-1913 XREFS 16190 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.5069663} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2495 {}}} CYCLES {}}
+set a(0-2495) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#133 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16191 LOC {1 0.29058164999999997 1 0.7695619499999999 1 0.7695619499999999 1 0.80117278625 2 0.53857713625} PREDS {{258 0 0-2493 {}} {259 0 0-2494 {}}} SUCCS {{259 0 0-2496 {}}} CYCLES {}}
+set a(0-2496) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,11,0,12) AREA_SCORE 330.25 QUANTITY 3 NAME ACC1:mul#90 TYPE MUL DELAY {3.18 ns} LIBRARY_DELAY {3.18 ns} PAR 0-1913 XREFS 16192 LOC {1 0.322192525 1 0.801172825 1 0.801172825 1 0.99999995 2 0.7374043} PREDS {{259 0 0-2495 {}}} SUCCS {{259 0 0-2497 {}}} CYCLES {}}
+set a(0-2497) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,12,1,14) AREA_SCORE 13.00 QUANTITY 3 NAME ACC1:acc#270 TYPE ACCU DELAY {1.11 ns} LIBRARY_DELAY {1.11 ns} PAR 0-1913 XREFS 16193 LOC {2 0.075477325 2 0.3666818 2 0.3666818 2 0.43601487849977766 2 0.8067374284997776} PREDS {{258 0 0-2492 {}} {259 0 0-2496 {}}} SUCCS {{258 0 0-2502 {}}} CYCLES {}}
+set a(0-2498) {NAME ACC1:slc(acc.idiv)#80 TYPE READSLICE PAR 0-1913 XREFS 16194 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.570971675} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2500 {}}} CYCLES {}}
+set a(0-2499) {NAME ACC1:slc(acc.idiv#2)#80 TYPE READSLICE PAR 0-1913 XREFS 16195 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.570971675} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2500 {}}} CYCLES {}}
+set a(0-2500) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#134 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16196 LOC {1 0.29058164999999997 1 0.7642342 1 0.7642342 1 0.79584503625 2 0.6025825112500001} PREDS {{258 0 0-2498 {}} {259 0 0-2499 {}}} SUCCS {{259 0 0-2501 {}}} CYCLES {}}
+set a(0-2501) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,13,0,14) AREA_SCORE 330.25 QUANTITY 3 NAME ACC1:mul#91 TYPE MUL DELAY {3.27 ns} LIBRARY_DELAY {3.27 ns} PAR 0-1913 XREFS 16197 LOC {1 0.322192525 1 0.795845075 1 0.795845075 1 0.9999999625 2 0.8067374374999999} PREDS {{259 0 0-2500 {}}} SUCCS {{259 0 0-2502 {}}} CYCLES {}}
+set a(0-2502) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(14,0,14,1,15) AREA_SCORE 15.00 QUANTITY 2 NAME ACC1:acc#274 TYPE ACCU DELAY {1.40 ns} LIBRARY_DELAY {1.40 ns} PAR 0-1913 XREFS 16198 LOC {2 0.14481045 2 0.436014925 2 0.436014925 2 0.5235723042724432 2 0.8942948542724432} PREDS {{258 0 0-2497 {}} {259 0 0-2501 {}}} SUCCS {{259 0 0-2503 {}}} CYCLES {}}
+set a(0-2503) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,15,1,16) AREA_SCORE 17.00 QUANTITY 1 NAME ACC1:acc#277 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-1913 XREFS 16199 LOC {2 0.232367875 2 0.52357235 2 0.52357235 2 0.6292773924711144 2 0.9999999424711143} PREDS {{258 0 0-2362 {}} {259 0 0-2502 {}}} SUCCS {{258 0 0-2726 {}}} CYCLES {}}
+set a(0-2504) {NAME ACC1:slc(acc.idiv#3)#39 TYPE READSLICE PAR 0-1913 XREFS 16200 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.588891925} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2506 {}}} CYCLES {}}
+set a(0-2505) {NAME ACC1:slc(acc.idiv#7)#22 TYPE READSLICE PAR 0-1913 XREFS 16201 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.588891925} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2506 {}}} CYCLES {}}
+set a(0-2506) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#147 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16202 LOC {1 0.21521084999999998 1 0.7781291 1 0.7781291 1 0.80973993625 2 0.62050276125} PREDS {{258 0 0-2504 {}} {259 0 0-2505 {}}} SUCCS {{259 0 0-2507 {}}} CYCLES {}}
+set a(0-2507) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 5 NAME ACC1:mul#104 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-1913 XREFS 16203 LOC {1 0.246821725 1 0.809739975 1 0.809739975 1 0.9999999562499999 2 0.81076278125} PREDS {{259 0 0-2506 {}}} SUCCS {{258 0 0-2511 {}}} CYCLES {}}
+set a(0-2508) {NAME ACC1:slc(acc.idiv#2)#90 TYPE READSLICE PAR 0-1913 XREFS 16204 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.810762825} PREDS {{258 0 0-2225 {}}} SUCCS {{258 0 0-2511 {}}} CYCLES {}}
+set a(0-2509) {NAME ACC1-3:slc(acc.idiv)#132 TYPE READSLICE PAR 0-1913 XREFS 16205 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.810762825} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2510 {}}} CYCLES {}}
+set a(0-2510) {NAME ACC1-3:exs#5 TYPE SIGNEXTEND PAR 0-1913 XREFS 16206 LOC {1 0.29058164999999997 2 0.440040275 2 0.440040275 2 0.810762825} PREDS {{259 0 0-2509 {}}} SUCCS {{259 0 0-2511 {}}} CYCLES {}}
+set a(0-2511) {NAME ACC1:conc#282 TYPE CONCATENATE PAR 0-1913 XREFS 16207 LOC {1 0.43708175 2 0.440040275 2 0.440040275 2 0.810762825} PREDS {{258 0 0-2508 {}} {258 0 0-2507 {}} {259 0 0-2510 {}}} SUCCS {{258 0 0-2718 {}}} CYCLES {}}
+set a(0-2512) {NAME ACC1:slc(acc.idiv#3)#38 TYPE READSLICE PAR 0-1913 XREFS 16208 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.4320038} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2514 {}}} CYCLES {}}
+set a(0-2513) {NAME ACC1:slc(acc.idiv#7)#21 TYPE READSLICE PAR 0-1913 XREFS 16209 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.4320038} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2514 {}}} CYCLES {}}
+set a(0-2514) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#146 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16210 LOC {1 0.21521084999999998 1 0.7802174749999999 1 0.7802174749999999 1 0.81182831125 2 0.46361463625} PREDS {{258 0 0-2512 {}} {259 0 0-2513 {}}} SUCCS {{259 0 0-2515 {}}} CYCLES {}}
+set a(0-2515) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,7,0,8) AREA_SCORE 330.25 QUANTITY 4 NAME ACC1:mul#103 TYPE MUL DELAY {3.01 ns} LIBRARY_DELAY {3.01 ns} PAR 0-1913 XREFS 16211 LOC {1 0.246821725 1 0.81182835 1 0.81182835 1 0.99999995 2 0.651786275} PREDS {{259 0 0-2514 {}}} SUCCS {{258 0 0-2519 {}}} CYCLES {}}
+set a(0-2516) {NAME ACC1:slc(acc.idiv)#91 TYPE READSLICE PAR 0-1913 XREFS 16212 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.651786325} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2519 {}}} CYCLES {}}
+set a(0-2517) {NAME ACC1-3:slc(acc.idiv)#131 TYPE READSLICE PAR 0-1913 XREFS 16213 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.651786325} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2518 {}}} CYCLES {}}
+set a(0-2518) {NAME ACC1-3:exs#4 TYPE SIGNEXTEND PAR 0-1913 XREFS 16214 LOC {1 0.29058164999999997 2 0.28106377499999996 2 0.28106377499999996 2 0.651786325} PREDS {{259 0 0-2517 {}}} SUCCS {{259 0 0-2519 {}}} CYCLES {}}
+set a(0-2519) {NAME ACC1:conc#281 TYPE CONCATENATE PAR 0-1913 XREFS 16215 LOC {1 0.43499337499999996 2 0.28106377499999996 2 0.28106377499999996 2 0.651786325} PREDS {{258 0 0-2516 {}} {258 0 0-2515 {}} {259 0 0-2518 {}}} SUCCS {{258 0 0-2680 {}}} CYCLES {}}
+set a(0-2520) {NAME ACC1:slc(acc.idiv)#86 TYPE READSLICE PAR 0-1913 XREFS 16216 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.294040625} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2522 {}}} CYCLES {}}
+set a(0-2521) {NAME ACC1:slc(acc.idiv#2)#86 TYPE READSLICE PAR 0-1913 XREFS 16217 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.294040625} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2522 {}}} CYCLES {}}
+set a(0-2522) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#141 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16218 LOC {1 0.29058164999999997 1 0.790507275 1 0.790507275 1 0.82211811125 2 0.32565146125} PREDS {{258 0 0-2520 {}} {259 0 0-2521 {}}} SUCCS {{259 0 0-2523 {}}} CYCLES {}}
+set a(0-2523) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 5 NAME ACC1:mul#98 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-1913 XREFS 16219 LOC {1 0.322192525 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.5035332921744312} PREDS {{259 0 0-2522 {}}} SUCCS {{258 0 0-2527 {}}} CYCLES {}}
+set a(0-2524) {NAME ACC1:slc(acc.idiv#3)#36 TYPE READSLICE PAR 0-1913 XREFS 16220 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.50353335} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2527 {}}} CYCLES {}}
+set a(0-2525) {NAME ACC1-2:slc(acc.idiv)#132 TYPE READSLICE PAR 0-1913 XREFS 16221 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.50353335} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2526 {}}} CYCLES {}}
+set a(0-2526) {NAME ACC1-2:exs#5 TYPE SIGNEXTEND PAR 0-1913 XREFS 16222 LOC {1 0.21521084999999998 2 0.1328108 2 0.1328108 2 0.50353335} PREDS {{259 0 0-2525 {}}} SUCCS {{259 0 0-2527 {}}} CYCLES {}}
+set a(0-2527) {NAME ACC1:conc#274 TYPE CONCATENATE PAR 0-1913 XREFS 16223 LOC {1 0.500074375 2 0.1328108 2 0.1328108 2 0.50353335} PREDS {{258 0 0-2524 {}} {258 0 0-2523 {}} {259 0 0-2526 {}}} SUCCS {{258 0 0-2674 {}}} CYCLES {}}
+set a(0-2528) {NAME ACC1:slc(acc.imod#17)#6 TYPE READSLICE PAR 0-1913 XREFS 16224 LOC {1 0.479008925 1 0.6214090999999999 1 0.6214090999999999 2 0.1715459} PREDS {{258 0 0-1991 {}}} SUCCS {{258 0 0-2530 {}}} CYCLES {}}
+set a(0-2529) {NAME ACC1:slc(acc.imod#6)#28 TYPE READSLICE PAR 0-1913 XREFS 16225 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 2 0.1715459} PREDS {{258 0 0-2288 {}}} SUCCS {{259 0 0-2530 {}}} CYCLES {}}
+set a(0-2530) {NAME ACC1:conc#258 TYPE CONCATENATE PAR 0-1913 XREFS 16226 LOC {1 0.5501930749999999 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{258 0 0-2528 {}} {259 0 0-2529 {}}} SUCCS {{258 0 0-2534 {}}} CYCLES {}}
+set a(0-2531) {NAME ACC1:slc(acc.imod#17)#7 TYPE READSLICE PAR 0-1913 XREFS 16227 LOC {1 0.479008925 1 0.6214090999999999 1 0.6214090999999999 2 0.1715459} PREDS {{258 0 0-1991 {}}} SUCCS {{258 0 0-2533 {}}} CYCLES {}}
+set a(0-2532) {NAME ACC1:slc(acc.imod#7) TYPE READSLICE PAR 0-1913 XREFS 16228 LOC {1 0.6860884749999999 1 0.7521577749999999 1 0.7521577749999999 2 0.1715459} PREDS {{258 0 0-2306 {}}} SUCCS {{259 0 0-2533 {}}} CYCLES {}}
+set a(0-2533) {NAME ACC1:conc#259 TYPE CONCATENATE PAR 0-1913 XREFS 16229 LOC {1 0.6860884749999999 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{258 0 0-2531 {}} {259 0 0-2532 {}}} SUCCS {{259 0 0-2534 {}}} CYCLES {}}
+set a(0-2534) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#211 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16230 LOC {1 0.6860884749999999 1 0.79971395 1 0.79971395 1 0.8404969600894753 2 0.21232891008947524} PREDS {{258 0 0-2530 {}} {259 0 0-2533 {}}} SUCCS {{258 0 0-2552 {}}} CYCLES {}}
+set a(0-2535) {NAME ACC1:slc(acc.imod#19) TYPE READSLICE PAR 0-1913 XREFS 16231 LOC {1 0.6149043249999999 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{258 0 0-2009 {}}} SUCCS {{259 0 0-2536 {}}} CYCLES {}}
+set a(0-2536) {NAME ACC1:conc#260 TYPE CONCATENATE PAR 0-1913 XREFS 16232 LOC {1 0.6149043249999999 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2535 {}}} SUCCS {{258 0 0-2551 {}}} CYCLES {}}
+set a(0-2537) {NAME ACC1:slc(acc.imod#19)#2 TYPE READSLICE PAR 0-1913 XREFS 16233 LOC {1 0.6149043249999999 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{258 0 0-2009 {}}} SUCCS {{259 0 0-2538 {}}} CYCLES {}}
+set a(0-2538) {NAME ACC1:not TYPE NOT PAR 0-1913 XREFS 16234 LOC {1 0.6149043249999999 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2537 {}}} SUCCS {{258 0 0-2550 {}}} CYCLES {}}
+set a(0-2539) {NAME ACC1-3:slc(acc.imod#7) TYPE READSLICE PAR 0-1913 XREFS 16235 LOC {1 0.6860884749999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{258 0 0-2306 {}}} SUCCS {{259 0 0-2540 {}}} CYCLES {}}
+set a(0-2540) {NAME ACC1:conc#393 TYPE CONCATENATE PAR 0-1913 XREFS 16236 LOC {1 0.6860884749999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{259 0 0-2539 {}}} SUCCS {{258 0 0-2546 {}}} CYCLES {}}
+set a(0-2541) {NAME ACC1-3:slc(acc.imod#7)#1 TYPE READSLICE PAR 0-1913 XREFS 16237 LOC {1 0.6860884749999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{258 0 0-2306 {}}} SUCCS {{259 0 0-2542 {}}} CYCLES {}}
+set a(0-2542) {NAME ACC1-3:not#49 TYPE NOT PAR 0-1913 XREFS 16238 LOC {1 0.6860884749999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{259 0 0-2541 {}}} SUCCS {{258 0 0-2545 {}}} CYCLES {}}
+set a(0-2543) {NAME ACC1-3:slc(acc.imod#7)#2 TYPE READSLICE PAR 0-1913 XREFS 16239 LOC {1 0.6860884749999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{258 0 0-2306 {}}} SUCCS {{259 0 0-2544 {}}} CYCLES {}}
+set a(0-2544) {NAME ACC1-3:not#50 TYPE NOT PAR 0-1913 XREFS 16240 LOC {1 0.6860884749999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{259 0 0-2543 {}}} SUCCS {{259 0 0-2545 {}}} CYCLES {}}
+set a(0-2545) {NAME ACC1:conc#394 TYPE CONCATENATE PAR 0-1913 XREFS 16241 LOC {1 0.6860884749999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{258 0 0-2542 {}} {259 0 0-2544 {}}} SUCCS {{259 0 0-2546 {}}} CYCLES {}}
+set a(0-2546) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#282 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16242 LOC {1 0.6860884749999999 1 0.7521577749999999 1 0.7521577749999999 1 0.799713902070827 2 0.17154585207082718} PREDS {{258 0 0-2540 {}} {259 0 0-2545 {}}} SUCCS {{259 0 0-2547 {}}} CYCLES {}}
+set a(0-2547) {NAME ACC1:slc#52 TYPE READSLICE PAR 0-1913 XREFS 16243 LOC {1 0.73364465 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2546 {}}} SUCCS {{259 0 0-2548 {}}} CYCLES {}}
+set a(0-2548) {NAME ACC1-3:slc#3 TYPE READSLICE PAR 0-1913 XREFS 16244 LOC {1 0.73364465 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2547 {}}} SUCCS {{259 0 0-2549 {}}} CYCLES {}}
+set a(0-2549) {NAME ACC1:not#120 TYPE NOT PAR 0-1913 XREFS 16245 LOC {1 0.73364465 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2548 {}}} SUCCS {{259 0 0-2550 {}}} CYCLES {}}
+set a(0-2550) {NAME ACC1:conc#261 TYPE CONCATENATE PAR 0-1913 XREFS 16246 LOC {1 0.73364465 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{258 0 0-2538 {}} {259 0 0-2549 {}}} SUCCS {{259 0 0-2551 {}}} CYCLES {}}
+set a(0-2551) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#210 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16247 LOC {1 0.73364465 1 0.79971395 1 0.79971395 1 0.8404969600894753 2 0.21232891008947524} PREDS {{258 0 0-2536 {}} {259 0 0-2550 {}}} SUCCS {{259 0 0-2552 {}}} CYCLES {}}
+set a(0-2552) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#233 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16248 LOC {1 0.7744276999999999 1 0.8404969999999999 1 0.8404969999999999 1 0.8880531270708271 2 0.25988507707082714} PREDS {{258 0 0-2534 {}} {259 0 0-2551 {}}} SUCCS {{258 0 0-2564 {}}} CYCLES {}}
+set a(0-2553) {NAME ACC1:slc(acc.idiv#7)#15 TYPE READSLICE PAR 0-1913 XREFS 16249 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.1715459} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2554 {}}} CYCLES {}}
+set a(0-2554) {NAME ACC1:conc#262 TYPE CONCATENATE PAR 0-1913 XREFS 16250 LOC {1 0.21521084999999998 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2553 {}}} SUCCS {{258 0 0-2557 {}}} CYCLES {}}
+set a(0-2555) {NAME ACC1:slc(acc.idiv#7)#16 TYPE READSLICE PAR 0-1913 XREFS 16251 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.1715459} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2556 {}}} CYCLES {}}
+set a(0-2556) {NAME ACC1:conc#263 TYPE CONCATENATE PAR 0-1913 XREFS 16252 LOC {1 0.21521084999999998 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2555 {}}} SUCCS {{259 0 0-2557 {}}} CYCLES {}}
+set a(0-2557) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#209 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16253 LOC {1 0.21521084999999998 1 0.79971395 1 0.79971395 1 0.8404969600894753 2 0.21232891008947524} PREDS {{258 0 0-2554 {}} {259 0 0-2556 {}}} SUCCS {{258 0 0-2563 {}}} CYCLES {}}
+set a(0-2558) {NAME ACC1:slc(acc.idiv#7)#17 TYPE READSLICE PAR 0-1913 XREFS 16254 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.1715459} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2559 {}}} CYCLES {}}
+set a(0-2559) {NAME ACC1:conc#264 TYPE CONCATENATE PAR 0-1913 XREFS 16255 LOC {1 0.21521084999999998 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2558 {}}} SUCCS {{258 0 0-2562 {}}} CYCLES {}}
+set a(0-2560) {NAME ACC1:slc(acc.idiv#7)#18 TYPE READSLICE PAR 0-1913 XREFS 16256 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.1715459} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2561 {}}} CYCLES {}}
+set a(0-2561) {NAME ACC1:conc#265 TYPE CONCATENATE PAR 0-1913 XREFS 16257 LOC {1 0.21521084999999998 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2560 {}}} SUCCS {{259 0 0-2562 {}}} CYCLES {}}
+set a(0-2562) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#208 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16258 LOC {1 0.21521084999999998 1 0.79971395 1 0.79971395 1 0.8404969600894753 2 0.21232891008947524} PREDS {{258 0 0-2559 {}} {259 0 0-2561 {}}} SUCCS {{259 0 0-2563 {}}} CYCLES {}}
+set a(0-2563) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#232 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16259 LOC {1 0.2559939 1 0.8404969999999999 1 0.8404969999999999 1 0.8880531270708271 2 0.25988507707082714} PREDS {{258 0 0-2557 {}} {259 0 0-2562 {}}} SUCCS {{259 0 0-2564 {}}} CYCLES {}}
+set a(0-2564) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 13 NAME ACC1:acc#245 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1913 XREFS 16260 LOC {1 0.8219838749999999 1 0.8880531749999999 1 0.8880531749999999 1 0.9414001951789503 2 0.3132321451789505} PREDS {{258 0 0-2552 {}} {259 0 0-2563 {}}} SUCCS {{258 0 0-2615 {}}} CYCLES {}}
+set a(0-2565) {NAME ACC1:slc(acc.imod#6)#29 TYPE READSLICE PAR 0-1913 XREFS 16261 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 2 0.1715459} PREDS {{258 0 0-2288 {}}} SUCCS {{259 0 0-2566 {}}} CYCLES {}}
+set a(0-2566) {NAME ACC1:conc#266 TYPE CONCATENATE PAR 0-1913 XREFS 16262 LOC {1 0.5501930749999999 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2565 {}}} SUCCS {{258 0 0-2569 {}}} CYCLES {}}
+set a(0-2567) {NAME ACC1:slc(acc.imod#25) TYPE READSLICE PAR 0-1913 XREFS 16263 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 2 0.1715459} PREDS {{258 0 0-2080 {}}} SUCCS {{259 0 0-2568 {}}} CYCLES {}}
+set a(0-2568) {NAME ACC1:conc#267 TYPE CONCATENATE PAR 0-1913 XREFS 16264 LOC {1 0.479008925 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2567 {}}} SUCCS {{259 0 0-2569 {}}} CYCLES {}}
+set a(0-2569) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#207 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16265 LOC {1 0.5501930749999999 1 0.79971395 1 0.79971395 1 0.8404969600894753 2 0.21232891008947524} PREDS {{258 0 0-2566 {}} {259 0 0-2568 {}}} SUCCS {{258 0 0-2575 {}}} CYCLES {}}
+set a(0-2570) {NAME ACC1:slc(acc.imod#25)#6 TYPE READSLICE PAR 0-1913 XREFS 16266 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 2 0.1715459} PREDS {{258 0 0-2080 {}}} SUCCS {{259 0 0-2571 {}}} CYCLES {}}
+set a(0-2571) {NAME ACC1:conc#268 TYPE CONCATENATE PAR 0-1913 XREFS 16267 LOC {1 0.479008925 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2570 {}}} SUCCS {{258 0 0-2574 {}}} CYCLES {}}
+set a(0-2572) {NAME ACC1:slc(acc.imod#25)#7 TYPE READSLICE PAR 0-1913 XREFS 16268 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 2 0.1715459} PREDS {{258 0 0-2080 {}}} SUCCS {{259 0 0-2573 {}}} CYCLES {}}
+set a(0-2573) {NAME ACC1:conc#269 TYPE CONCATENATE PAR 0-1913 XREFS 16269 LOC {1 0.479008925 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2572 {}}} SUCCS {{259 0 0-2574 {}}} CYCLES {}}
+set a(0-2574) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#206 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16270 LOC {1 0.479008925 1 0.79971395 1 0.79971395 1 0.8404969600894753 2 0.21232891008947524} PREDS {{258 0 0-2571 {}} {259 0 0-2573 {}}} SUCCS {{259 0 0-2575 {}}} CYCLES {}}
+set a(0-2575) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#231 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16271 LOC {1 0.590976125 1 0.8404969999999999 1 0.8404969999999999 1 0.8880531270708271 2 0.25988507707082714} PREDS {{258 0 0-2569 {}} {259 0 0-2574 {}}} SUCCS {{258 0 0-2614 {}}} CYCLES {}}
+set a(0-2576) {NAME ACC1:slc(acc.imod#25)#8 TYPE READSLICE PAR 0-1913 XREFS 16272 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 2 0.1715459} PREDS {{258 0 0-2080 {}}} SUCCS {{259 0 0-2577 {}}} CYCLES {}}
+set a(0-2577) {NAME ACC1:not#121 TYPE NOT PAR 0-1913 XREFS 16273 LOC {1 0.479008925 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2576 {}}} SUCCS {{258 0 0-2580 {}}} CYCLES {}}
+set a(0-2578) {NAME ACC1:slc(acc.imod)#30 TYPE READSLICE PAR 0-1913 XREFS 16274 LOC {1 0.554379725 1 0.593398 1 0.593398 2 0.1715459} PREDS {{258 0 0-2190 {}}} SUCCS {{259 0 0-2579 {}}} CYCLES {}}
+set a(0-2579) {NAME ACC1:not#122 TYPE NOT PAR 0-1913 XREFS 16275 LOC {1 0.554379725 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2578 {}}} SUCCS {{259 0 0-2580 {}}} CYCLES {}}
+set a(0-2580) {NAME ACC1:conc#270 TYPE CONCATENATE PAR 0-1913 XREFS 16276 LOC {1 0.554379725 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{258 0 0-2577 {}} {259 0 0-2579 {}}} SUCCS {{258 0 0-2583 {}}} CYCLES {}}
+set a(0-2581) {NAME ACC1:slc(acc.imod#27) TYPE READSLICE PAR 0-1913 XREFS 16277 LOC {1 0.6149043249999999 1 0.7521577749999999 1 0.7521577749999999 2 0.1715459} PREDS {{258 0 0-2098 {}}} SUCCS {{259 0 0-2582 {}}} CYCLES {}}
+set a(0-2582) {NAME ACC1:conc#271 TYPE CONCATENATE PAR 0-1913 XREFS 16278 LOC {1 0.6149043249999999 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2581 {}}} SUCCS {{259 0 0-2583 {}}} CYCLES {}}
+set a(0-2583) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#205 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16279 LOC {1 0.6149043249999999 1 0.79971395 1 0.79971395 1 0.8404969600894753 2 0.21232891008947524} PREDS {{258 0 0-2580 {}} {259 0 0-2582 {}}} SUCCS {{258 0 0-2613 {}}} CYCLES {}}
+set a(0-2584) {NAME ACC1:slc(acc.imod#27)#2 TYPE READSLICE PAR 0-1913 XREFS 16280 LOC {1 0.6149043249999999 1 0.7521577749999999 1 0.7521577749999999 2 0.1715459} PREDS {{258 0 0-2098 {}}} SUCCS {{259 0 0-2585 {}}} CYCLES {}}
+set a(0-2585) {NAME ACC1:not#123 TYPE NOT PAR 0-1913 XREFS 16281 LOC {1 0.6149043249999999 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2584 {}}} SUCCS {{258 0 0-2588 {}}} CYCLES {}}
+set a(0-2586) {NAME ACC1:slc(acc.imod#1)#9 TYPE READSLICE PAR 0-1913 XREFS 16282 LOC {1 0.690275125 1 0.7521577749999999 1 0.7521577749999999 2 0.1715459} PREDS {{258 0 0-2208 {}}} SUCCS {{259 0 0-2587 {}}} CYCLES {}}
+set a(0-2587) {NAME ACC1:not#124 TYPE NOT PAR 0-1913 XREFS 16283 LOC {1 0.690275125 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2586 {}}} SUCCS {{259 0 0-2588 {}}} CYCLES {}}
+set a(0-2588) {NAME ACC1:conc#272 TYPE CONCATENATE PAR 0-1913 XREFS 16284 LOC {1 0.690275125 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{258 0 0-2585 {}} {259 0 0-2587 {}}} SUCCS {{258 0 0-2612 {}}} CYCLES {}}
+set a(0-2589) {NAME ACC1-1:slc(acc.imod#7) TYPE READSLICE PAR 0-1913 XREFS 16285 LOC {1 0.6149043249999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{258 0 0-2098 {}}} SUCCS {{259 0 0-2590 {}}} CYCLES {}}
+set a(0-2590) {NAME ACC1:conc#396 TYPE CONCATENATE PAR 0-1913 XREFS 16286 LOC {1 0.6149043249999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{259 0 0-2589 {}}} SUCCS {{258 0 0-2596 {}}} CYCLES {}}
+set a(0-2591) {NAME ACC1-1:slc(acc.imod#7)#1 TYPE READSLICE PAR 0-1913 XREFS 16287 LOC {1 0.6149043249999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{258 0 0-2098 {}}} SUCCS {{259 0 0-2592 {}}} CYCLES {}}
+set a(0-2592) {NAME ACC1-1:not#49 TYPE NOT PAR 0-1913 XREFS 16288 LOC {1 0.6149043249999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{259 0 0-2591 {}}} SUCCS {{258 0 0-2595 {}}} CYCLES {}}
+set a(0-2593) {NAME ACC1-1:slc(acc.imod#7)#2 TYPE READSLICE PAR 0-1913 XREFS 16289 LOC {1 0.6149043249999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{258 0 0-2098 {}}} SUCCS {{259 0 0-2594 {}}} CYCLES {}}
+set a(0-2594) {NAME ACC1-1:not#50 TYPE NOT PAR 0-1913 XREFS 16290 LOC {1 0.6149043249999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{259 0 0-2593 {}}} SUCCS {{259 0 0-2595 {}}} CYCLES {}}
+set a(0-2595) {NAME ACC1:conc#397 TYPE CONCATENATE PAR 0-1913 XREFS 16291 LOC {1 0.6149043249999999 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{258 0 0-2592 {}} {259 0 0-2594 {}}} SUCCS {{259 0 0-2596 {}}} CYCLES {}}
+set a(0-2596) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#283 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16292 LOC {1 0.6149043249999999 1 0.7521577749999999 1 0.7521577749999999 1 0.799713902070827 2 0.17154585207082718} PREDS {{258 0 0-2590 {}} {259 0 0-2595 {}}} SUCCS {{259 0 0-2597 {}}} CYCLES {}}
+set a(0-2597) {NAME ACC1:slc#53 TYPE READSLICE PAR 0-1913 XREFS 16293 LOC {1 0.6624605 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2596 {}}} SUCCS {{259 0 0-2598 {}}} CYCLES {}}
+set a(0-2598) {NAME ACC1:slc#4 TYPE READSLICE PAR 0-1913 XREFS 16294 LOC {1 0.6624605 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2597 {}}} SUCCS {{259 0 0-2599 {}}} CYCLES {}}
+set a(0-2599) {NAME ACC1:not#125 TYPE NOT PAR 0-1913 XREFS 16295 LOC {1 0.6624605 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2598 {}}} SUCCS {{258 0 0-2611 {}}} CYCLES {}}
+set a(0-2600) {NAME ACC1-3:slc(acc.imod#1) TYPE READSLICE PAR 0-1913 XREFS 16296 LOC {1 0.690275125 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{258 0 0-2208 {}}} SUCCS {{259 0 0-2601 {}}} CYCLES {}}
+set a(0-2601) {NAME ACC1:conc#399 TYPE CONCATENATE PAR 0-1913 XREFS 16297 LOC {1 0.690275125 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{259 0 0-2600 {}}} SUCCS {{258 0 0-2607 {}}} CYCLES {}}
+set a(0-2602) {NAME ACC1-3:slc(acc.imod#1)#1 TYPE READSLICE PAR 0-1913 XREFS 16298 LOC {1 0.690275125 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{258 0 0-2208 {}}} SUCCS {{259 0 0-2603 {}}} CYCLES {}}
+set a(0-2603) {NAME ACC1-3:not#13 TYPE NOT PAR 0-1913 XREFS 16299 LOC {1 0.690275125 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{259 0 0-2602 {}}} SUCCS {{258 0 0-2606 {}}} CYCLES {}}
+set a(0-2604) {NAME ACC1-3:slc(acc.imod#1)#2 TYPE READSLICE PAR 0-1913 XREFS 16300 LOC {1 0.690275125 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{258 0 0-2208 {}}} SUCCS {{259 0 0-2605 {}}} CYCLES {}}
+set a(0-2605) {NAME ACC1-3:not#14 TYPE NOT PAR 0-1913 XREFS 16301 LOC {1 0.690275125 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{259 0 0-2604 {}}} SUCCS {{259 0 0-2606 {}}} CYCLES {}}
+set a(0-2606) {NAME ACC1:conc#400 TYPE CONCATENATE PAR 0-1913 XREFS 16302 LOC {1 0.690275125 1 0.7521577749999999 1 0.7521577749999999 2 0.123989725} PREDS {{258 0 0-2603 {}} {259 0 0-2605 {}}} SUCCS {{259 0 0-2607 {}}} CYCLES {}}
+set a(0-2607) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#284 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16303 LOC {1 0.690275125 1 0.7521577749999999 1 0.7521577749999999 1 0.799713902070827 2 0.17154585207082718} PREDS {{258 0 0-2601 {}} {259 0 0-2606 {}}} SUCCS {{259 0 0-2608 {}}} CYCLES {}}
+set a(0-2608) {NAME ACC1:slc#54 TYPE READSLICE PAR 0-1913 XREFS 16304 LOC {1 0.7378313 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2607 {}}} SUCCS {{259 0 0-2609 {}}} CYCLES {}}
+set a(0-2609) {NAME ACC1-3:slc#1 TYPE READSLICE PAR 0-1913 XREFS 16305 LOC {1 0.7378313 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2608 {}}} SUCCS {{259 0 0-2610 {}}} CYCLES {}}
+set a(0-2610) {NAME ACC1:not#126 TYPE NOT PAR 0-1913 XREFS 16306 LOC {1 0.7378313 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{259 0 0-2609 {}}} SUCCS {{259 0 0-2611 {}}} CYCLES {}}
+set a(0-2611) {NAME ACC1:conc#273 TYPE CONCATENATE PAR 0-1913 XREFS 16307 LOC {1 0.7378313 1 0.79971395 1 0.79971395 2 0.1715459} PREDS {{258 0 0-2599 {}} {259 0 0-2610 {}}} SUCCS {{259 0 0-2612 {}}} CYCLES {}}
+set a(0-2612) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#204 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16308 LOC {1 0.7378313 1 0.79971395 1 0.79971395 1 0.8404969600894753 2 0.21232891008947524} PREDS {{258 0 0-2588 {}} {259 0 0-2611 {}}} SUCCS {{259 0 0-2613 {}}} CYCLES {}}
+set a(0-2613) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#230 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16309 LOC {1 0.77861435 1 0.8404969999999999 1 0.8404969999999999 1 0.8880531270708271 2 0.25988507707082714} PREDS {{258 0 0-2583 {}} {259 0 0-2612 {}}} SUCCS {{259 0 0-2614 {}}} CYCLES {}}
+set a(0-2614) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 13 NAME ACC1:acc#244 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1913 XREFS 16310 LOC {1 0.826170525 1 0.8880531749999999 1 0.8880531749999999 1 0.9414001951789503 2 0.3132321451789505} PREDS {{258 0 0-2575 {}} {259 0 0-2613 {}}} SUCCS {{259 0 0-2615 {}}} CYCLES {}}
+set a(0-2615) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 12 NAME ACC1:acc#252 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1913 XREFS 16311 LOC {1 0.8795176 1 0.9414002499999999 1 0.9414002499999999 1 0.999999959496936 2 0.371831909496936} PREDS {{258 0 0-2564 {}} {259 0 0-2614 {}}} SUCCS {{258 0 0-2650 {}}} CYCLES {}}
+set a(0-2616) {NAME ACC1:slc(acc.imod#17)#9 TYPE READSLICE PAR 0-1913 XREFS 16312 LOC {1 0.479008925 1 0.6214090999999999 1 0.6214090999999999 2 0.259885125} PREDS {{258 0 0-1991 {}}} SUCCS {{259 0 0-2617 {}}} CYCLES {}}
+set a(0-2617) {NAME ACC1:not#127 TYPE NOT PAR 0-1913 XREFS 16313 LOC {1 0.479008925 1 0.8880531749999999 1 0.8880531749999999 2 0.259885125} PREDS {{259 0 0-2616 {}}} SUCCS {{258 0 0-2633 {}}} CYCLES {}}
+set a(0-2618) {NAME ACC1:slc(acc.imod)#31 TYPE READSLICE PAR 0-1913 XREFS 16314 LOC {1 0.554379725 1 0.593398 1 0.593398 2 0.259885125} PREDS {{258 0 0-2190 {}}} SUCCS {{259 0 0-2619 {}}} CYCLES {}}
+set a(0-2619) {NAME ACC1:not#128 TYPE NOT PAR 0-1913 XREFS 16315 LOC {1 0.554379725 1 0.8880531749999999 1 0.8880531749999999 2 0.259885125} PREDS {{259 0 0-2618 {}}} SUCCS {{258 0 0-2633 {}}} CYCLES {}}
+set a(0-2620) {NAME ACC1-2:slc(acc.imod#1) TYPE READSLICE PAR 0-1913 XREFS 16316 LOC {1 0.6149043249999999 1 0.79971395 1 0.79971395 2 0.21232895} PREDS {{258 0 0-2009 {}}} SUCCS {{259 0 0-2621 {}}} CYCLES {}}
+set a(0-2621) {NAME ACC1:conc#402 TYPE CONCATENATE PAR 0-1913 XREFS 16317 LOC {1 0.6149043249999999 1 0.8404969999999999 1 0.8404969999999999 2 0.21232895} PREDS {{259 0 0-2620 {}}} SUCCS {{258 0 0-2627 {}}} CYCLES {}}
+set a(0-2622) {NAME ACC1-2:slc(acc.imod#1)#1 TYPE READSLICE PAR 0-1913 XREFS 16318 LOC {1 0.6149043249999999 1 0.79971395 1 0.79971395 2 0.21232895} PREDS {{258 0 0-2009 {}}} SUCCS {{259 0 0-2623 {}}} CYCLES {}}
+set a(0-2623) {NAME ACC1-2:not#13 TYPE NOT PAR 0-1913 XREFS 16319 LOC {1 0.6149043249999999 1 0.8404969999999999 1 0.8404969999999999 2 0.21232895} PREDS {{259 0 0-2622 {}}} SUCCS {{258 0 0-2626 {}}} CYCLES {}}
+set a(0-2624) {NAME ACC1-2:slc(acc.imod#1)#2 TYPE READSLICE PAR 0-1913 XREFS 16320 LOC {1 0.6149043249999999 1 0.79971395 1 0.79971395 2 0.21232895} PREDS {{258 0 0-2009 {}}} SUCCS {{259 0 0-2625 {}}} CYCLES {}}
+set a(0-2625) {NAME ACC1-2:not#14 TYPE NOT PAR 0-1913 XREFS 16321 LOC {1 0.6149043249999999 1 0.8404969999999999 1 0.8404969999999999 2 0.21232895} PREDS {{259 0 0-2624 {}}} SUCCS {{259 0 0-2626 {}}} CYCLES {}}
+set a(0-2626) {NAME ACC1:conc#403 TYPE CONCATENATE PAR 0-1913 XREFS 16322 LOC {1 0.6149043249999999 1 0.8404969999999999 1 0.8404969999999999 2 0.21232895} PREDS {{258 0 0-2623 {}} {259 0 0-2625 {}}} SUCCS {{259 0 0-2627 {}}} CYCLES {}}
+set a(0-2627) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#285 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16323 LOC {1 0.6149043249999999 1 0.8404969999999999 1 0.8404969999999999 1 0.8880531270708271 2 0.25988507707082714} PREDS {{258 0 0-2621 {}} {259 0 0-2626 {}}} SUCCS {{259 0 0-2628 {}}} CYCLES {}}
+set a(0-2628) {NAME ACC1:slc#55 TYPE READSLICE PAR 0-1913 XREFS 16324 LOC {1 0.6624605 1 0.8880531749999999 1 0.8880531749999999 2 0.259885125} PREDS {{259 0 0-2627 {}}} SUCCS {{259 0 0-2629 {}}} CYCLES {}}
+set a(0-2629) {NAME ACC1:slc(ACC1-2:acc#7.cse) TYPE READSLICE PAR 0-1913 XREFS 16325 LOC {1 0.6624605 1 0.8880531749999999 1 0.8880531749999999 2 0.259885125} PREDS {{259 0 0-2628 {}}} SUCCS {{259 0 0-2630 {}}} CYCLES {}}
+set a(0-2630) {NAME ACC1:not#129 TYPE NOT PAR 0-1913 XREFS 16326 LOC {1 0.6624605 1 0.8880531749999999 1 0.8880531749999999 2 0.259885125} PREDS {{259 0 0-2629 {}}} SUCCS {{258 0 0-2633 {}}} CYCLES {}}
+set a(0-2631) {NAME ACC1:slc(acc.imod#6)#30 TYPE READSLICE PAR 0-1913 XREFS 16327 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 2 0.259885125} PREDS {{258 0 0-2288 {}}} SUCCS {{259 0 0-2632 {}}} CYCLES {}}
+set a(0-2632) {NAME ACC1:not#130 TYPE NOT PAR 0-1913 XREFS 16328 LOC {1 0.5501930749999999 1 0.8880531749999999 1 0.8880531749999999 2 0.259885125} PREDS {{259 0 0-2631 {}}} SUCCS {{259 0 0-2633 {}}} CYCLES {}}
+set a(0-2633) {NAME ACC1:conc#278 TYPE CONCATENATE PAR 0-1913 XREFS 16329 LOC {1 0.6624605 1 0.8880531749999999 1 0.8880531749999999 2 0.259885125} PREDS {{258 0 0-2630 {}} {258 0 0-2619 {}} {258 0 0-2617 {}} {259 0 0-2632 {}}} SUCCS {{258 0 0-2643 {}}} CYCLES {}}
+set a(0-2634) {NAME ACC1:slc(acc.imod#25)#10 TYPE READSLICE PAR 0-1913 XREFS 16330 LOC {1 0.479008925 1 0.6162623749999999 1 0.6162623749999999 2 0.259885125} PREDS {{258 0 0-2080 {}}} SUCCS {{259 0 0-2635 {}}} CYCLES {}}
+set a(0-2635) {NAME ACC1:not#131 TYPE NOT PAR 0-1913 XREFS 16331 LOC {1 0.479008925 1 0.8880531749999999 1 0.8880531749999999 2 0.259885125} PREDS {{259 0 0-2634 {}}} SUCCS {{258 0 0-2642 {}}} CYCLES {}}
+set a(0-2636) {NAME ACC1:slc(acc.imod#6)#31 TYPE READSLICE PAR 0-1913 XREFS 16332 LOC {1 0.5501930749999999 1 0.6162623749999999 1 0.6162623749999999 2 0.259885125} PREDS {{258 0 0-2288 {}}} SUCCS {{259 0 0-2637 {}}} CYCLES {}}
+set a(0-2637) {NAME ACC1:not#132 TYPE NOT PAR 0-1913 XREFS 16333 LOC {1 0.5501930749999999 1 0.8880531749999999 1 0.8880531749999999 2 0.259885125} PREDS {{259 0 0-2636 {}}} SUCCS {{258 0 0-2642 {}}} CYCLES {}}
+set a(0-2638) {NAME ACC1:slc(acc.imod#17)#10 TYPE READSLICE PAR 0-1913 XREFS 16334 LOC {1 0.479008925 1 0.6214090999999999 1 0.6214090999999999 2 0.259885125} PREDS {{258 0 0-1991 {}}} SUCCS {{259 0 0-2639 {}}} CYCLES {}}
+set a(0-2639) {NAME ACC1:not#133 TYPE NOT PAR 0-1913 XREFS 16335 LOC {1 0.479008925 1 0.8880531749999999 1 0.8880531749999999 2 0.259885125} PREDS {{259 0 0-2638 {}}} SUCCS {{258 0 0-2642 {}}} CYCLES {}}
+set a(0-2640) {NAME ACC1:slc(acc.imod#7)#9 TYPE READSLICE PAR 0-1913 XREFS 16336 LOC {1 0.6860884749999999 1 0.7521577749999999 1 0.7521577749999999 2 0.259885125} PREDS {{258 0 0-2306 {}}} SUCCS {{259 0 0-2641 {}}} CYCLES {}}
+set a(0-2641) {NAME ACC1:not#134 TYPE NOT PAR 0-1913 XREFS 16337 LOC {1 0.6860884749999999 1 0.8880531749999999 1 0.8880531749999999 2 0.259885125} PREDS {{259 0 0-2640 {}}} SUCCS {{259 0 0-2642 {}}} CYCLES {}}
+set a(0-2642) {NAME ACC1:conc#279 TYPE CONCATENATE PAR 0-1913 XREFS 16338 LOC {1 0.6860884749999999 1 0.8880531749999999 1 0.8880531749999999 2 0.259885125} PREDS {{258 0 0-2639 {}} {258 0 0-2637 {}} {258 0 0-2635 {}} {259 0 0-2641 {}}} SUCCS {{259 0 0-2643 {}}} CYCLES {}}
+set a(0-2643) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 13 NAME ACC1:acc#243 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1913 XREFS 16339 LOC {1 0.6860884749999999 1 0.8880531749999999 1 0.8880531749999999 1 0.9414001951789503 2 0.3132321451789505} PREDS {{258 0 0-2633 {}} {259 0 0-2642 {}}} SUCCS {{258 0 0-2649 {}}} CYCLES {}}
+set a(0-2644) {NAME ACC1:slc(acc.idiv#7)#25 TYPE READSLICE PAR 0-1913 XREFS 16340 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.31323219999999996} PREDS {{258 0 0-2017 {}}} SUCCS {{258 0 0-2648 {}}} CYCLES {}}
+set a(0-2645) {NAME ACC1:slc(acc.idiv#3)#41 TYPE READSLICE PAR 0-1913 XREFS 16341 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.31323219999999996} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2648 {}}} CYCLES {}}
+set a(0-2646) {NAME ACC1-2:slc(acc.idiv)#118 TYPE READSLICE PAR 0-1913 XREFS 16342 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.31323219999999996} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2647 {}}} CYCLES {}}
+set a(0-2647) {NAME ACC1-2:exs#2 TYPE SIGNEXTEND PAR 0-1913 XREFS 16343 LOC {1 0.21521084999999998 1 0.9414002499999999 1 0.9414002499999999 2 0.31323219999999996} PREDS {{259 0 0-2646 {}}} SUCCS {{259 0 0-2648 {}}} CYCLES {}}
+set a(0-2648) {NAME ACC1:conc#284 TYPE CONCATENATE PAR 0-1913 XREFS 16344 LOC {1 0.21521084999999998 1 0.9414002499999999 1 0.9414002499999999 2 0.31323219999999996} PREDS {{258 0 0-2645 {}} {258 0 0-2644 {}} {259 0 0-2647 {}}} SUCCS {{259 0 0-2649 {}}} CYCLES {}}
+set a(0-2649) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 12 NAME ACC1:acc#251 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1913 XREFS 16345 LOC {1 0.7394355499999999 1 0.9414002499999999 1 0.9414002499999999 1 0.999999959496936 2 0.371831909496936} PREDS {{258 0 0-2643 {}} {259 0 0-2648 {}}} SUCCS {{259 0 0-2650 {}}} CYCLES {}}
+set a(0-2650) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 3 NAME ACC1:acc#256 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-1913 XREFS 16346 LOC {2 0.0 2 0.0011094 2 0.0011094 2 0.06462137341030243 2 0.43534392341030237} PREDS {{258 0 0-2615 {}} {259 0 0-2649 {}}} SUCCS {{258 0 0-2673 {}}} CYCLES {}}
+set a(0-2651) {NAME ACC1:slc(acc.idiv#7)#26 TYPE READSLICE PAR 0-1913 XREFS 16347 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.31323219999999996} PREDS {{258 0 0-2017 {}}} SUCCS {{258 0 0-2655 {}}} CYCLES {}}
+set a(0-2652) {NAME ACC1:slc(acc.idiv#7)#27 TYPE READSLICE PAR 0-1913 XREFS 16348 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.31323219999999996} PREDS {{258 0 0-2017 {}}} SUCCS {{258 0 0-2655 {}}} CYCLES {}}
+set a(0-2653) {NAME ACC1-2:slc(acc.idiv)#124 TYPE READSLICE PAR 0-1913 XREFS 16349 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.31323219999999996} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2654 {}}} CYCLES {}}
+set a(0-2654) {NAME ACC1-2:exs#3 TYPE SIGNEXTEND PAR 0-1913 XREFS 16350 LOC {1 0.21521084999999998 1 0.877888225 1 0.877888225 2 0.31323219999999996} PREDS {{259 0 0-2653 {}}} SUCCS {{259 0 0-2655 {}}} CYCLES {}}
+set a(0-2655) {NAME ACC1:conc#285 TYPE CONCATENATE PAR 0-1913 XREFS 16351 LOC {1 0.21521084999999998 1 0.877888225 1 0.877888225 2 0.31323219999999996} PREDS {{258 0 0-2652 {}} {258 0 0-2651 {}} {259 0 0-2654 {}}} SUCCS {{258 0 0-2667 {}}} CYCLES {}}
+set a(0-2656) {NAME ACC1-1:slc(acc.idiv)#106 TYPE READSLICE PAR 0-1913 XREFS 16352 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.224892975} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2657 {}}} CYCLES {}}
+set a(0-2657) {NAME ACC1-1:exs#6 TYPE SIGNEXTEND PAR 0-1913 XREFS 16353 LOC {1 0.21521084999999998 1 0.789549 1 0.789549 2 0.224892975} PREDS {{259 0 0-2656 {}}} SUCCS {{258 0 0-2660 {}}} CYCLES {}}
+set a(0-2658) {NAME ACC1-1:slc(acc.idiv)#109 TYPE READSLICE PAR 0-1913 XREFS 16354 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.224892975} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2659 {}}} CYCLES {}}
+set a(0-2659) {NAME ACC1-1:exs TYPE SIGNEXTEND PAR 0-1913 XREFS 16355 LOC {1 0.21521084999999998 1 0.789549 1 0.789549 2 0.224892975} PREDS {{259 0 0-2658 {}}} SUCCS {{259 0 0-2660 {}}} CYCLES {}}
+set a(0-2660) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#229 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16356 LOC {1 0.21521084999999998 1 0.789549 1 0.789549 1 0.8303320100894752 2 0.2656759850894752} PREDS {{258 0 0-2657 {}} {259 0 0-2659 {}}} SUCCS {{258 0 0-2666 {}}} CYCLES {}}
+set a(0-2661) {NAME ACC1-1:slc(acc.idiv)#113 TYPE READSLICE PAR 0-1913 XREFS 16357 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.224892975} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2662 {}}} CYCLES {}}
+set a(0-2662) {NAME ACC1-1:exs#1 TYPE SIGNEXTEND PAR 0-1913 XREFS 16358 LOC {1 0.21521084999999998 1 0.789549 1 0.789549 2 0.224892975} PREDS {{259 0 0-2661 {}}} SUCCS {{258 0 0-2665 {}}} CYCLES {}}
+set a(0-2663) {NAME ACC1-1:slc(acc.idiv)#118 TYPE READSLICE PAR 0-1913 XREFS 16359 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.224892975} PREDS {{258 0 0-1928 {}}} SUCCS {{259 0 0-2664 {}}} CYCLES {}}
+set a(0-2664) {NAME ACC1-1:exs#2 TYPE SIGNEXTEND PAR 0-1913 XREFS 16360 LOC {1 0.21521084999999998 1 0.789549 1 0.789549 2 0.224892975} PREDS {{259 0 0-2663 {}}} SUCCS {{259 0 0-2665 {}}} CYCLES {}}
+set a(0-2665) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 48 NAME ACC1:acc#228 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-1913 XREFS 16361 LOC {1 0.21521084999999998 1 0.789549 1 0.789549 1 0.8303320100894752 2 0.2656759850894752} PREDS {{258 0 0-2662 {}} {259 0 0-2664 {}}} SUCCS {{259 0 0-2666 {}}} CYCLES {}}
+set a(0-2666) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME ACC1:acc#242 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16362 LOC {1 0.2559939 1 0.83033205 1 0.83033205 1 0.8778881770708271 2 0.31323215207082716} PREDS {{258 0 0-2660 {}} {259 0 0-2665 {}}} SUCCS {{259 0 0-2667 {}}} CYCLES {}}
+set a(0-2667) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 12 NAME ACC1:acc#250 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1913 XREFS 16363 LOC {1 0.303550075 1 0.877888225 1 0.877888225 1 0.936487934496936 2 0.371831909496936} PREDS {{258 0 0-2655 {}} {259 0 0-2666 {}}} SUCCS {{258 0 0-2672 {}}} CYCLES {}}
+set a(0-2668) {NAME ACC1:slc(acc.idiv) TYPE READSLICE PAR 0-1913 XREFS 16364 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.162339225} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2670 {}}} CYCLES {}}
+set a(0-2669) {NAME ACC1:slc(acc.idiv#2) TYPE READSLICE PAR 0-1913 XREFS 16365 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.162339225} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2670 {}}} CYCLES {}}
+set a(0-2670) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#130 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16366 LOC {1 0.29058164999999997 1 0.72699525 1 0.72699525 1 0.7586060862499999 2 0.19395006125} PREDS {{258 0 0-2668 {}} {259 0 0-2669 {}}} SUCCS {{259 0 0-2671 {}}} CYCLES {}}
+set a(0-2671) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 5 NAME ACC1:mul TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-1913 XREFS 16367 LOC {1 0.322192525 1 0.758606125 1 0.758606125 1 0.9364879171744313 2 0.37183189217443124} PREDS {{259 0 0-2670 {}}} SUCCS {{259 0 0-2672 {}}} CYCLES {}}
+set a(0-2672) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 3 NAME ACC1:acc#255 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-1913 XREFS 16368 LOC {1 0.500074375 1 0.9364879749999999 1 0.9364879749999999 1 0.9999999484103024 2 0.43534392341030237} PREDS {{258 0 0-2667 {}} {259 0 0-2671 {}}} SUCCS {{259 0 0-2673 {}}} CYCLES {}}
+set a(0-2673) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 2 NAME ACC1:acc#260 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-1913 XREFS 16369 LOC {2 0.063512025 2 0.064621425 2 0.064621425 2 0.1328107379329679 2 0.5035332879329679} PREDS {{258 0 0-2650 {}} {259 0 0-2672 {}}} SUCCS {{259 0 0-2674 {}}} CYCLES {}}
+set a(0-2674) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME ACC1:acc#263 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-1913 XREFS 16370 LOC {2 0.1317014 2 0.1328108 2 0.1328108 2 0.19972443789165437 2 0.5704469878916544} PREDS {{258 0 0-2527 {}} {259 0 0-2673 {}}} SUCCS {{258 0 0-2679 {}}} CYCLES {}}
+set a(0-2675) {NAME ACC1:slc(acc.idiv)#78 TYPE READSLICE PAR 0-1913 XREFS 16371 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.34857615} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2677 {}}} CYCLES {}}
+set a(0-2676) {NAME ACC1:slc(acc.idiv#2)#78 TYPE READSLICE PAR 0-1913 XREFS 16372 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.34857615} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2677 {}}} CYCLES {}}
+set a(0-2677) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#132 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16373 LOC {1 0.29058164999999997 1 0.7781291 1 0.7781291 1 0.80973993625 2 0.38018698624999997} PREDS {{258 0 0-2675 {}} {259 0 0-2676 {}}} SUCCS {{259 0 0-2678 {}}} CYCLES {}}
+set a(0-2678) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 5 NAME ACC1:mul#89 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-1913 XREFS 16374 LOC {1 0.322192525 1 0.809739975 1 0.809739975 1 0.9999999562499999 2 0.57044700625} PREDS {{259 0 0-2677 {}}} SUCCS {{259 0 0-2679 {}}} CYCLES {}}
+set a(0-2679) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,11) AREA_SCORE 11.24 QUANTITY 2 NAME ACC1:acc#266 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-1913 XREFS 16375 LOC {2 0.1986151 2 0.1997245 2 0.1997245 2 0.2810637283364113 2 0.6517862783364112} PREDS {{258 0 0-2674 {}} {259 0 0-2678 {}}} SUCCS {{259 0 0-2680 {}}} CYCLES {}}
+set a(0-2680) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,12,1,14) AREA_SCORE 13.00 QUANTITY 3 NAME ACC1:acc#269 TYPE ACCU DELAY {1.11 ns} LIBRARY_DELAY {1.11 ns} PAR 0-1913 XREFS 16376 LOC {2 0.279954375 2 0.28106377499999996 2 0.28106377499999996 2 0.3503968534997776 2 0.7211194034997777} PREDS {{258 0 0-2519 {}} {259 0 0-2679 {}}} SUCCS {{258 0 0-2717 {}}} CYCLES {}}
+set a(0-2681) {NAME ACC1:slc(acc.idiv#3)#37 TYPE READSLICE PAR 0-1913 XREFS 16377 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.34476152499999996} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2683 {}}} CYCLES {}}
+set a(0-2682) {NAME ACC1:slc(acc.idiv#7)#20 TYPE READSLICE PAR 0-1913 XREFS 16378 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.34476152499999996} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2683 {}}} CYCLES {}}
+set a(0-2683) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#145 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16379 LOC {1 0.21521084999999998 1 0.623642075 1 0.623642075 1 0.6552529112500001 2 0.37637236124999995} PREDS {{258 0 0-2681 {}} {259 0 0-2682 {}}} SUCCS {{259 0 0-2684 {}}} CYCLES {}}
+set a(0-2684) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 5 NAME ACC1:mul#102 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-1913 XREFS 16380 LOC {1 0.246821725 1 0.65525295 1 0.65525295 1 0.8331347421744312 2 0.5542541921744313} PREDS {{259 0 0-2683 {}}} SUCCS {{258 0 0-2688 {}}} CYCLES {}}
+set a(0-2685) {NAME ACC1:slc(acc.idiv)#90 TYPE READSLICE PAR 0-1913 XREFS 16381 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.55425425} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2688 {}}} CYCLES {}}
+set a(0-2686) {NAME ACC1-3:slc(acc.idiv)#124 TYPE READSLICE PAR 0-1913 XREFS 16382 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.55425425} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2687 {}}} CYCLES {}}
+set a(0-2687) {NAME ACC1-3:exs#3 TYPE SIGNEXTEND PAR 0-1913 XREFS 16383 LOC {1 0.29058164999999997 1 0.8331348 1 0.8331348 2 0.55425425} PREDS {{259 0 0-2686 {}}} SUCCS {{259 0 0-2688 {}}} CYCLES {}}
+set a(0-2688) {NAME ACC1:conc#280 TYPE CONCATENATE PAR 0-1913 XREFS 16384 LOC {1 0.424703575 1 0.8331348 1 0.8331348 2 0.55425425} PREDS {{258 0 0-2685 {}} {258 0 0-2684 {}} {259 0 0-2687 {}}} SUCCS {{258 0 0-2709 {}}} CYCLES {}}
+set a(0-2689) {NAME ACC1:slc(acc.idiv#3)#42 TYPE READSLICE PAR 0-1913 XREFS 16385 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.413370125} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2695 {}}} CYCLES {}}
+set a(0-2690) {NAME ACC1:slc(acc.idiv)#92 TYPE READSLICE PAR 0-1913 XREFS 16386 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.413370125} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2695 {}}} CYCLES {}}
+set a(0-2691) {NAME ACC1:slc(acc.idiv#3)#43 TYPE READSLICE PAR 0-1913 XREFS 16387 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.413370125} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2695 {}}} CYCLES {}}
+set a(0-2692) {NAME ACC1:slc(acc.idiv)#93 TYPE READSLICE PAR 0-1913 XREFS 16388 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.413370125} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2695 {}}} CYCLES {}}
+set a(0-2693) {NAME ACC1-3:slc(acc.idiv)#109 TYPE READSLICE PAR 0-1913 XREFS 16389 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.413370125} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2694 {}}} CYCLES {}}
+set a(0-2694) {NAME ACC1-3:exs TYPE SIGNEXTEND PAR 0-1913 XREFS 16390 LOC {1 0.29058164999999997 1 0.6922506749999999 1 0.6922506749999999 2 0.413370125} PREDS {{259 0 0-2693 {}}} SUCCS {{259 0 0-2695 {}}} CYCLES {}}
+set a(0-2695) {NAME ACC1:conc#286 TYPE CONCATENATE PAR 0-1913 XREFS 16391 LOC {1 0.29058164999999997 1 0.6922506749999999 1 0.6922506749999999 2 0.413370125} PREDS {{258 0 0-2692 {}} {258 0 0-2691 {}} {258 0 0-2690 {}} {258 0 0-2689 {}} {259 0 0-2694 {}}} SUCCS {{258 0 0-2703 {}}} CYCLES {}}
+set a(0-2696) {NAME ACC1:slc(acc.idiv#7)#28 TYPE READSLICE PAR 0-1913 XREFS 16392 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.413370125} PREDS {{258 0 0-2017 {}}} SUCCS {{258 0 0-2702 {}}} CYCLES {}}
+set a(0-2697) {NAME ACC1:slc(acc.idiv#2)#92 TYPE READSLICE PAR 0-1913 XREFS 16393 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.413370125} PREDS {{258 0 0-2225 {}}} SUCCS {{258 0 0-2702 {}}} CYCLES {}}
+set a(0-2698) {NAME ACC1:slc(acc.idiv#3)#44 TYPE READSLICE PAR 0-1913 XREFS 16394 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.413370125} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2702 {}}} CYCLES {}}
+set a(0-2699) {NAME ACC1:slc(acc.idiv#2)#93 TYPE READSLICE PAR 0-1913 XREFS 16395 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.413370125} PREDS {{258 0 0-2225 {}}} SUCCS {{258 0 0-2702 {}}} CYCLES {}}
+set a(0-2700) {NAME ACC1-3:slc(acc.idiv)#113 TYPE READSLICE PAR 0-1913 XREFS 16396 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.413370125} PREDS {{258 0 0-2127 {}}} SUCCS {{259 0 0-2701 {}}} CYCLES {}}
+set a(0-2701) {NAME ACC1-3:exs#1 TYPE SIGNEXTEND PAR 0-1913 XREFS 16397 LOC {1 0.29058164999999997 1 0.6922506749999999 1 0.6922506749999999 2 0.413370125} PREDS {{259 0 0-2700 {}}} SUCCS {{259 0 0-2702 {}}} CYCLES {}}
+set a(0-2702) {NAME ACC1:conc#287 TYPE CONCATENATE PAR 0-1913 XREFS 16398 LOC {1 0.29058164999999997 1 0.6922506749999999 1 0.6922506749999999 2 0.413370125} PREDS {{258 0 0-2699 {}} {258 0 0-2698 {}} {258 0 0-2697 {}} {258 0 0-2696 {}} {259 0 0-2701 {}}} SUCCS {{259 0 0-2703 {}}} CYCLES {}}
+set a(0-2703) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,0,8) AREA_SCORE 8.27 QUANTITY 2 NAME ACC1:acc#258 TYPE ACCU DELAY {1.09 ns} LIBRARY_DELAY {1.09 ns} PAR 0-1913 XREFS 16399 LOC {1 0.29058164999999997 1 0.6922506749999999 1 0.6922506749999999 1 0.7604399879329679 2 0.4815594379329679} PREDS {{258 0 0-2695 {}} {259 0 0-2702 {}}} SUCCS {{258 0 0-2708 {}}} CYCLES {}}
+set a(0-2704) {NAME ACC1:slc(acc.idiv)#77 TYPE READSLICE PAR 0-1913 XREFS 16400 LOC {1 0.29058164999999997 1 0.32959992499999996 1 0.32959992499999996 2 0.26177697499999997} PREDS {{258 0 0-2127 {}}} SUCCS {{258 0 0-2706 {}}} CYCLES {}}
+set a(0-2705) {NAME ACC1:slc(acc.idiv#2)#77 TYPE READSLICE PAR 0-1913 XREFS 16401 LOC {1 0.286395 1 0.3524643 1 0.3524643 2 0.26177697499999997} PREDS {{258 0 0-2225 {}}} SUCCS {{259 0 0-2706 {}}} CYCLES {}}
+set a(0-2706) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#131 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16402 LOC {1 0.29058164999999997 1 0.540657525 1 0.540657525 1 0.5722683612499999 2 0.29338781124999996} PREDS {{258 0 0-2704 {}} {259 0 0-2705 {}}} SUCCS {{259 0 0-2707 {}}} CYCLES {}}
+set a(0-2707) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,7,0,8) AREA_SCORE 330.25 QUANTITY 4 NAME ACC1:mul#88 TYPE MUL DELAY {3.01 ns} LIBRARY_DELAY {3.01 ns} PAR 0-1913 XREFS 16403 LOC {1 0.322192525 1 0.5722684 1 0.5722684 1 0.76044 2 0.48155945} PREDS {{259 0 0-2706 {}}} SUCCS {{259 0 0-2708 {}}} CYCLES {}}
+set a(0-2708) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,9) AREA_SCORE 9.26 QUANTITY 2 NAME ACC1:acc#262 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-1913 XREFS 16404 LOC {1 0.510364175 1 0.7604400499999999 1 0.7604400499999999 1 0.8331347527684256 2 0.5542542027684257} PREDS {{258 0 0-2703 {}} {259 0 0-2707 {}}} SUCCS {{259 0 0-2709 {}}} CYCLES {}}
+set a(0-2709) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,11) AREA_SCORE 11.24 QUANTITY 2 NAME ACC1:acc#265 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-1913 XREFS 16405 LOC {1 0.583058925 1 0.8331348 1 0.8331348 1 0.9144740283364112 2 0.6355934783364112} PREDS {{258 0 0-2688 {}} {259 0 0-2708 {}}} SUCCS {{258 0 0-2716 {}}} CYCLES {}}
+set a(0-2710) {NAME ACC1:slc(acc.idiv#3)#33 TYPE READSLICE PAR 0-1913 XREFS 16406 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.41372262499999995} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2712 {}}} CYCLES {}}
+set a(0-2711) {NAME ACC1:slc(acc.idiv#7)#11 TYPE READSLICE PAR 0-1913 XREFS 16407 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.41372262499999995} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2712 {}}} CYCLES {}}
+set a(0-2712) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#137 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16408 LOC {1 0.21521084999999998 1 0.692603175 1 0.692603175 1 0.72421401125 2 0.44533346124999995} PREDS {{258 0 0-2710 {}} {259 0 0-2711 {}}} SUCCS {{259 0 0-2713 {}}} CYCLES {}}
+set a(0-2713) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 5 NAME ACC1:mul#94 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-1913 XREFS 16409 LOC {1 0.246821725 1 0.7242140499999999 1 0.7242140499999999 1 0.9144740312499999 2 0.6355934812499999} PREDS {{259 0 0-2712 {}}} SUCCS {{258 0 0-2715 {}}} CYCLES {}}
+set a(0-2714) {NAME ACC1:slc(acc.imod) TYPE READSLICE PAR 0-1913 XREFS 16410 LOC {1 0.554379725 1 0.593398 1 0.593398 2 0.635593525} PREDS {{258 0 0-2190 {}}} SUCCS {{259 0 0-2715 {}}} CYCLES {}}
+set a(0-2715) {NAME ACC1:conc#252 TYPE CONCATENATE PAR 0-1913 XREFS 16411 LOC {1 0.554379725 1 0.914474075 1 0.914474075 2 0.635593525} PREDS {{258 0 0-2713 {}} {259 0 0-2714 {}}} SUCCS {{259 0 0-2716 {}}} CYCLES {}}
+set a(0-2716) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,0,12) AREA_SCORE 12.23 QUANTITY 1 NAME ACC1:acc#268 TYPE ACCU DELAY {1.37 ns} LIBRARY_DELAY {1.37 ns} PAR 0-1913 XREFS 16412 LOC {1 0.6643981999999999 1 0.914474075 1 0.914474075 1 0.9999999563734283 2 0.7211194063734283} PREDS {{258 0 0-2709 {}} {259 0 0-2715 {}}} SUCCS {{259 0 0-2717 {}}} CYCLES {}}
+set a(0-2717) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,12,0,13) AREA_SCORE 13.22 QUANTITY 1 NAME ACC1:acc#271 TYPE ACCU DELAY {1.43 ns} LIBRARY_DELAY {1.43 ns} PAR 0-1913 XREFS 16413 LOC {2 0.3492875 2 0.3503969 2 0.3503969 2 0.4400402284997777 2 0.8107627784997776} PREDS {{258 0 0-2680 {}} {259 0 0-2716 {}}} SUCCS {{259 0 0-2718 {}}} CYCLES {}}
+set a(0-2718) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(14,0,14,1,15) AREA_SCORE 15.00 QUANTITY 2 NAME ACC1:acc#273 TYPE ACCU DELAY {1.40 ns} LIBRARY_DELAY {1.40 ns} PAR 0-1913 XREFS 16414 LOC {2 0.438930875 2 0.440040275 2 0.440040275 2 0.5275976542724432 2 0.8983202042724432} PREDS {{258 0 0-2511 {}} {259 0 0-2717 {}}} SUCCS {{258 0 0-2725 {}}} CYCLES {}}
+set a(0-2719) {NAME ACC1:slc(acc.idiv#3)#35 TYPE READSLICE PAR 0-1913 XREFS 16415 LOC {1 0.21521084999999998 1 0.35761102499999997 1 0.35761102499999997 2 0.66255445} PREDS {{258 0 0-1928 {}}} SUCCS {{258 0 0-2721 {}}} CYCLES {}}
+set a(0-2720) {NAME ACC1:slc(acc.idiv#7)#13 TYPE READSLICE PAR 0-1913 XREFS 16416 LOC {1 0.21521084999999998 1 0.3524643 1 0.3524643 2 0.66255445} PREDS {{258 0 0-2017 {}}} SUCCS {{259 0 0-2721 {}}} CYCLES {}}
+set a(0-2721) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 21 NAME ACC1:acc#139 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-1913 XREFS 16417 LOC {1 0.21521084999999998 1 0.7642342 1 0.7642342 1 0.79584503625 2 0.6941652862500001} PREDS {{258 0 0-2719 {}} {259 0 0-2720 {}}} SUCCS {{259 0 0-2722 {}}} CYCLES {}}
+set a(0-2722) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,13,0,14) AREA_SCORE 330.25 QUANTITY 3 NAME ACC1:mul#96 TYPE MUL DELAY {3.27 ns} LIBRARY_DELAY {3.27 ns} PAR 0-1913 XREFS 16418 LOC {1 0.246821725 1 0.795845075 1 0.795845075 1 0.9999999625 2 0.8983202124999999} PREDS {{259 0 0-2721 {}}} SUCCS {{258 0 0-2724 {}}} CYCLES {}}
+set a(0-2723) {NAME ACC1:slc(acc.imod)#28 TYPE READSLICE PAR 0-1913 XREFS 16419 LOC {1 0.554379725 1 0.593398 1 0.593398 2 0.8983202499999999} PREDS {{258 0 0-2190 {}}} SUCCS {{259 0 0-2724 {}}} CYCLES {}}
+set a(0-2724) {NAME ACC1:conc#254 TYPE CONCATENATE PAR 0-1913 XREFS 16420 LOC {1 0.554379725 2 0.5275977 2 0.5275977 2 0.8983202499999999} PREDS {{258 0 0-2722 {}} {259 0 0-2723 {}}} SUCCS {{259 0 0-2725 {}}} CYCLES {}}
+set a(0-2725) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(15,0,15,0,16) AREA_SCORE 16.20 QUANTITY 2 NAME ACC1:acc#276 TYPE ACCU DELAY {1.63 ns} LIBRARY_DELAY {1.63 ns} PAR 0-1913 XREFS 16421 LOC {2 0.5264883 2 0.5275977 2 0.5275977 2 0.6292773903177632 2 0.9999999403177632} PREDS {{258 0 0-2718 {}} {259 0 0-2724 {}}} SUCCS {{259 0 0-2726 {}}} CYCLES {}}
+set a(0-2726) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,17) AREA_SCORE 17.19 QUANTITY 9 NAME ACC1:acc#280 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-1913 XREFS 16422 LOC {2 0.62816805 2 0.62927745 2 0.62927745 2 0.734887180357901 3 0.181465755357901} PREDS {{258 0 0-2503 {}} {259 0 0-2725 {}}} SUCCS {{259 0 0-2727 {}}} CYCLES {}}
+set a(0-2727) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,17) AREA_SCORE 17.19 QUANTITY 9 NAME ACC1:acc TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-1913 XREFS 16423 LOC {2 0.733777825 2 0.7348872249999999 2 0.7348872249999999 2 0.8404969553579009 3 0.28707553035790095} PREDS {{258 0 0-2355 {}} {259 0 0-2726 {}}} SUCCS {{259 0 0-2728 {}}} CYCLES {}}
+set a(0-2728) {NAME ACC1:slc TYPE READSLICE PAR 0-1913 XREFS 16424 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.28707557499999997} PREDS {{259 0 0-2727 {}}} SUCCS {{259 0 0-2729 {}} {258 0 0-2730 {}} {258 0 0-2733 {}} {258 0 0-2735 {}} {258 0 0-2738 {}} {258 0 0-2741 {}} {258 0 0-2742 {}} {258 0 0-2747 {}} {258 0 0-2749 {}} {258 0 0-2751 {}} {258 0 0-2768 {}} {258 0 0-2777 {}} {258 0 0-2778 {}} {258 0 0-2780 {}}} CYCLES {}}
+set a(0-2729) {NAME intensity:slc(intensity#2.sg1)#4 TYPE READSLICE PAR 0-1913 XREFS 16425 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.28707557499999997} PREDS {{259 0 0-2728 {}}} SUCCS {{258 0 0-2732 {}}} CYCLES {}}
+set a(0-2730) {NAME intensity:slc(intensity#2.sg1)#5 TYPE READSLICE PAR 0-1913 XREFS 16426 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.28707557499999997} PREDS {{258 0 0-2728 {}}} SUCCS {{259 0 0-2731 {}}} CYCLES {}}
+set a(0-2731) {NAME FRAME:not#26 TYPE NOT PAR 0-1913 XREFS 16427 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.28707557499999997} PREDS {{259 0 0-2730 {}}} SUCCS {{259 0 0-2732 {}}} CYCLES {}}
+set a(0-2732) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME FRAME:acc#9 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16428 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 2 0.8880531270708271 3 0.33463170207082715} PREDS {{258 0 0-2729 {}} {259 0 0-2731 {}}} SUCCS {{258 0 0-2740 {}}} CYCLES {}}
+set a(0-2733) {NAME intensity:slc(intensity#2.sg1)#6 TYPE READSLICE PAR 0-1913 XREFS 16429 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.28707557499999997} PREDS {{258 0 0-2728 {}}} SUCCS {{259 0 0-2734 {}}} CYCLES {}}
+set a(0-2734) {NAME FRAME:not#27 TYPE NOT PAR 0-1913 XREFS 16430 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.28707557499999997} PREDS {{259 0 0-2733 {}}} SUCCS {{258 0 0-2737 {}}} CYCLES {}}
+set a(0-2735) {NAME intensity:slc(intensity#2.sg1)#7 TYPE READSLICE PAR 0-1913 XREFS 16431 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.28707557499999997} PREDS {{258 0 0-2728 {}}} SUCCS {{259 0 0-2736 {}}} CYCLES {}}
+set a(0-2736) {NAME FRAME:not#33 TYPE NOT PAR 0-1913 XREFS 16432 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.28707557499999997} PREDS {{259 0 0-2735 {}}} SUCCS {{259 0 0-2737 {}}} CYCLES {}}
+set a(0-2737) {NAME FRAME:conc TYPE CONCATENATE PAR 0-1913 XREFS 16433 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.28707557499999997} PREDS {{258 0 0-2734 {}} {259 0 0-2736 {}}} SUCCS {{258 0 0-2739 {}}} CYCLES {}}
+set a(0-2738) {NAME intensity:slc(intensity#2.sg1)#1 TYPE READSLICE PAR 0-1913 XREFS 16434 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.28707557499999997} PREDS {{258 0 0-2728 {}}} SUCCS {{259 0 0-2739 {}}} CYCLES {}}
+set a(0-2739) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME FRAME:acc#8 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16435 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 2 0.8880531270708271 3 0.33463170207082715} PREDS {{258 0 0-2737 {}} {259 0 0-2738 {}}} SUCCS {{259 0 0-2740 {}}} CYCLES {}}
+set a(0-2740) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 13 NAME FRAME:acc#11 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1913 XREFS 16436 LOC {2 0.886943775 2 0.8880531749999999 2 0.8880531749999999 2 0.9414001951789503 3 0.3879787701789505} PREDS {{258 0 0-2732 {}} {259 0 0-2739 {}}} SUCCS {{258 0 0-2745 {}}} CYCLES {}}
+set a(0-2741) {NAME intensity:slc(intensity#2.sg1)#2 TYPE READSLICE PAR 0-1913 XREFS 16437 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.34042265} PREDS {{258 0 0-2728 {}}} SUCCS {{258 0 0-2744 {}}} CYCLES {}}
+set a(0-2742) {NAME intensity:slc(intensity#2.sg1)#3 TYPE READSLICE PAR 0-1913 XREFS 16438 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.34042265} PREDS {{258 0 0-2728 {}}} SUCCS {{259 0 0-2743 {}}} CYCLES {}}
+set a(0-2743) {NAME FRAME:not#25 TYPE NOT PAR 0-1913 XREFS 16439 LOC {2 0.8393876 2 0.893844075 2 0.893844075 3 0.34042265} PREDS {{259 0 0-2742 {}}} SUCCS {{259 0 0-2744 {}}} CYCLES {}}
+set a(0-2744) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME FRAME:acc#10 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16440 LOC {2 0.8393876 2 0.893844075 2 0.893844075 2 0.9414002020708271 3 0.3879787770708272} PREDS {{258 0 0-2741 {}} {259 0 0-2743 {}}} SUCCS {{259 0 0-2745 {}}} CYCLES {}}
+set a(0-2745) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 12 NAME FRAME:acc#12 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1913 XREFS 16441 LOC {2 0.94029085 2 0.9414002499999999 2 0.9414002499999999 2 0.999999959496936 3 0.446578534496936} PREDS {{258 0 0-2740 {}} {259 0 0-2744 {}}} SUCCS {{259 0 0-2746 {}}} CYCLES {}}
+set a(0-2746) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 5 NAME acc#18 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-1913 XREFS 16442 LOC {3 0.0 3 0.446578575 3 0.446578575 3 0.5100905484103024 3 0.5100905484103024} PREDS {{259 0 0-2745 {}}} SUCCS {{258 0 0-2752 {}} {258 0 0-2754 {}} {258 0 0-2756 {}} {258 0 0-2758 {}} {258 0 0-2766 {}} {258 0 0-2771 {}}} CYCLES {}}
+set a(0-2747) {NAME intensity:slc(intensity#2.sg1)#9 TYPE READSLICE PAR 0-1913 XREFS 16443 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.64818705} PREDS {{258 0 0-2728 {}}} SUCCS {{259 0 0-2748 {}}} CYCLES {}}
+set a(0-2748) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 5 NAME FRAME:mul#6 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-1913 XREFS 16444 LOC {3 0.0 3 0.64818705 3 0.64818705 3 0.83844703125 3 0.83844703125} PREDS {{259 0 0-2747 {}}} SUCCS {{258 0 0-2776 {}}} CYCLES {}}
+set a(0-2749) {NAME intensity:slc(intensity#2.sg1)#11 TYPE READSLICE PAR 0-1913 XREFS 16445 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.593651525} PREDS {{258 0 0-2728 {}}} SUCCS {{259 0 0-2750 {}}} CYCLES {}}
+set a(0-2750) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 5 NAME FRAME:mul#7 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-1913 XREFS 16446 LOC {3 0.0 3 0.593651525 3 0.593651525 3 0.7715333171744312 3 0.7715333171744312} PREDS {{259 0 0-2749 {}}} SUCCS {{258 0 0-2775 {}}} CYCLES {}}
+set a(0-2751) {NAME intensity:slc(intensity#2.sg1) TYPE READSLICE PAR 0-1913 XREFS 16447 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.72819335} PREDS {{258 0 0-2728 {}}} SUCCS {{258 0 0-2774 {}}} CYCLES {}}
+set a(0-2752) {NAME FRAME:slc(acc.imod#15)#6 TYPE READSLICE PAR 0-1913 XREFS 16448 LOC {3 0.063512025 3 0.5100906 3 0.5100906 3 0.56869035} PREDS {{258 0 0-2746 {}}} SUCCS {{259 0 0-2753 {}}} CYCLES {}}
+set a(0-2753) {NAME FRAME:not#31 TYPE NOT PAR 0-1913 XREFS 16449 LOC {3 0.063512025 3 0.56869035 3 0.56869035 3 0.56869035} PREDS {{259 0 0-2752 {}}} SUCCS {{258 0 0-2765 {}}} CYCLES {}}
+set a(0-2754) {NAME FRAME:slc(acc.imod#15)#1 TYPE READSLICE PAR 0-1913 XREFS 16450 LOC {3 0.063512025 3 0.5100906 3 0.5100906 3 0.5100906} PREDS {{258 0 0-2746 {}}} SUCCS {{259 0 0-2755 {}}} CYCLES {}}
+set a(0-2755) {NAME FRAME:conc#25 TYPE CONCATENATE PAR 0-1913 XREFS 16451 LOC {3 0.063512025 3 0.5100906 3 0.5100906 3 0.5100906} PREDS {{259 0 0-2754 {}}} SUCCS {{258 0 0-2761 {}}} CYCLES {}}
+set a(0-2756) {NAME FRAME:slc(acc.imod#15)#2 TYPE READSLICE PAR 0-1913 XREFS 16452 LOC {3 0.063512025 3 0.5100906 3 0.5100906 3 0.5100906} PREDS {{258 0 0-2746 {}}} SUCCS {{259 0 0-2757 {}}} CYCLES {}}
+set a(0-2757) {NAME FRAME:not#29 TYPE NOT PAR 0-1913 XREFS 16453 LOC {3 0.063512025 3 0.5100906 3 0.5100906 3 0.5100906} PREDS {{259 0 0-2756 {}}} SUCCS {{258 0 0-2760 {}}} CYCLES {}}
+set a(0-2758) {NAME FRAME:slc(acc.imod#15) TYPE READSLICE PAR 0-1913 XREFS 16454 LOC {3 0.063512025 3 0.5100906 3 0.5100906 3 0.5100906} PREDS {{258 0 0-2746 {}}} SUCCS {{259 0 0-2759 {}}} CYCLES {}}
+set a(0-2759) {NAME FRAME:not#28 TYPE NOT PAR 0-1913 XREFS 16455 LOC {3 0.063512025 3 0.5100906 3 0.5100906 3 0.5100906} PREDS {{259 0 0-2758 {}}} SUCCS {{259 0 0-2760 {}}} CYCLES {}}
+set a(0-2760) {NAME FRAME:conc#26 TYPE CONCATENATE PAR 0-1913 XREFS 16456 LOC {3 0.063512025 3 0.5100906 3 0.5100906 3 0.5100906} PREDS {{258 0 0-2757 {}} {259 0 0-2759 {}}} SUCCS {{259 0 0-2761 {}}} CYCLES {}}
+set a(0-2761) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 12 NAME FRAME:acc#19 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1913 XREFS 16457 LOC {3 0.063512025 3 0.5100906 3 0.5100906 3 0.568690309496936 3 0.568690309496936} PREDS {{258 0 0-2755 {}} {259 0 0-2760 {}}} SUCCS {{259 0 0-2762 {}}} CYCLES {}}
+set a(0-2762) {NAME FRAME:slc#3 TYPE READSLICE PAR 0-1913 XREFS 16458 LOC {3 0.12211177499999999 3 0.56869035 3 0.56869035 3 0.56869035} PREDS {{259 0 0-2761 {}}} SUCCS {{259 0 0-2763 {}}} CYCLES {}}
+set a(0-2763) {NAME FRAME:slc#2 TYPE READSLICE PAR 0-1913 XREFS 16459 LOC {3 0.12211177499999999 3 0.56869035 3 0.56869035 3 0.56869035} PREDS {{259 0 0-2762 {}}} SUCCS {{259 0 0-2764 {}}} CYCLES {}}
+set a(0-2764) {NAME FRAME:not#32 TYPE NOT PAR 0-1913 XREFS 16460 LOC {3 0.12211177499999999 3 0.56869035 3 0.56869035 3 0.56869035} PREDS {{259 0 0-2763 {}}} SUCCS {{259 0 0-2765 {}}} CYCLES {}}
+set a(0-2765) {NAME FRAME:conc#15 TYPE CONCATENATE PAR 0-1913 XREFS 16461 LOC {3 0.12211177499999999 3 0.56869035 3 0.56869035 3 0.56869035} PREDS {{258 0 0-2753 {}} {259 0 0-2764 {}}} SUCCS {{258 0 0-2767 {}}} CYCLES {}}
+set a(0-2766) {NAME FRAME:slc(acc.imod#15)#5 TYPE READSLICE PAR 0-1913 XREFS 16462 LOC {3 0.063512025 3 0.5100906 3 0.5100906 3 0.56869035} PREDS {{258 0 0-2746 {}}} SUCCS {{259 0 0-2767 {}}} CYCLES {}}
+set a(0-2767) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 37 NAME FRAME:acc#13 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-1913 XREFS 16463 LOC {3 0.12211177499999999 3 0.56869035 3 0.56869035 3 0.6162464770708271 3 0.6162464770708271} PREDS {{258 0 0-2765 {}} {259 0 0-2766 {}}} SUCCS {{258 0 0-2770 {}}} CYCLES {}}
+set a(0-2768) {NAME intensity:slc(intensity#2.sg1)#10 TYPE READSLICE PAR 0-1913 XREFS 16464 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.616246525} PREDS {{258 0 0-2728 {}}} SUCCS {{259 0 0-2769 {}}} CYCLES {}}
+set a(0-2769) {NAME FRAME:not#30 TYPE NOT PAR 0-1913 XREFS 16465 LOC {2 0.8393876 3 0.616246525 3 0.616246525 3 0.616246525} PREDS {{259 0 0-2768 {}}} SUCCS {{259 0 0-2770 {}}} CYCLES {}}
+set a(0-2770) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 13 NAME FRAME:acc#14 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-1913 XREFS 16466 LOC {3 0.16966794999999998 3 0.616246525 3 0.616246525 3 0.6695935451789505 3 0.6695935451789505} PREDS {{258 0 0-2767 {}} {259 0 0-2769 {}}} SUCCS {{258 0 0-2773 {}}} CYCLES {}}
+set a(0-2771) {NAME FRAME:slc(acc.imod#15)#4 TYPE READSLICE PAR 0-1913 XREFS 16467 LOC {3 0.063512025 3 0.5100906 3 0.5100906 3 0.6695936} PREDS {{258 0 0-2746 {}}} SUCCS {{259 0 0-2772 {}}} CYCLES {}}
+set a(0-2772) {NAME FRAME:conc#23 TYPE CONCATENATE PAR 0-1913 XREFS 16468 LOC {3 0.063512025 3 0.6695936 3 0.6695936 3 0.6695936} PREDS {{259 0 0-2771 {}}} SUCCS {{259 0 0-2773 {}}} CYCLES {}}
+set a(0-2773) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 12 NAME FRAME:acc#15 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-1913 XREFS 16469 LOC {3 0.22301502499999998 3 0.6695936 3 0.6695936 3 0.7281933094969361 3 0.7281933094969361} PREDS {{258 0 0-2770 {}} {259 0 0-2772 {}}} SUCCS {{259 0 0-2774 {}}} CYCLES {}}
+set a(0-2774) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 1 NAME FRAME:acc#16 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-1913 XREFS 16470 LOC {3 0.281614775 3 0.72819335 3 0.72819335 3 0.7715333157468814 3 0.7715333157468814} PREDS {{258 0 0-2751 {}} {259 0 0-2773 {}}} SUCCS {{259 0 0-2775 {}}} CYCLES {}}
+set a(0-2775) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,9,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#17 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-1913 XREFS 16471 LOC {3 0.3249548 3 0.771533375 3 0.771533375 3 0.8384470128916544 3 0.8384470128916544} PREDS {{258 0 0-2750 {}} {259 0 0-2774 {}}} SUCCS {{259 0 0-2776 {}}} CYCLES {}}
+set a(0-2776) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,10,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME FRAME:acc#18 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-1913 XREFS 16472 LOC {3 0.3918685 3 0.8384470749999999 3 0.8384470749999999 3 0.9139243593138832 3 0.9139243593138832} PREDS {{258 0 0-2748 {}} {259 0 0-2775 {}}} SUCCS {{258 0 0-2783 {}}} CYCLES {}}
+set a(0-2777) {NAME intensity:slc(intensity#2.sg1)#12 TYPE READSLICE PAR 0-1913 XREFS 16473 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.9139244} PREDS {{258 0 0-2728 {}}} SUCCS {{258 0 0-2781 {}}} CYCLES {}}
+set a(0-2778) {NAME intensity:slc(intensity#2.sg1)#13 TYPE READSLICE PAR 0-1913 XREFS 16474 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.9139244} PREDS {{258 0 0-2728 {}}} SUCCS {{259 0 0-2779 {}}} CYCLES {}}
+set a(0-2779) {NAME FRAME:exs#7 TYPE SIGNEXTEND PAR 0-1913 XREFS 16475 LOC {2 0.8393876 3 0.9139244 3 0.9139244 3 0.9139244} PREDS {{259 0 0-2778 {}}} SUCCS {{258 0 0-2781 {}}} CYCLES {}}
+set a(0-2780) {NAME intensity:slc(intensity#2.sg1)#8 TYPE READSLICE PAR 0-1913 XREFS 16476 LOC {2 0.8393876 2 0.8404969999999999 2 0.8404969999999999 3 0.9139244} PREDS {{258 0 0-2728 {}}} SUCCS {{259 0 0-2781 {}}} CYCLES {}}
+set a(0-2781) {NAME FRAME:conc#14 TYPE CONCATENATE PAR 0-1913 XREFS 16477 LOC {2 0.8393876 3 0.9139244 3 0.9139244 3 0.9139244} PREDS {{258 0 0-2779 {}} {258 0 0-2777 {}} {259 0 0-2780 {}}} SUCCS {{259 0 0-2782 {}}} CYCLES {}}
+set a(0-2782) {NAME FRAME:exs#6 TYPE SIGNEXTEND PAR 0-1913 XREFS 16478 LOC {2 0.8393876 3 0.9139244 3 0.9139244 3 0.9139244} PREDS {{259 0 0-2781 {}}} SUCCS {{259 0 0-2783 {}}} CYCLES {}}
+set a(0-2783) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,12,1,14) AREA_SCORE 13.00 QUANTITY 3 NAME FRAME:acc#5 TYPE ACCU DELAY {1.11 ns} LIBRARY_DELAY {1.11 ns} PAR 0-1913 XREFS 16479 LOC {3 0.467345825 3 0.9139244 3 0.9139244 3 0.9832574784997776 3 0.9832574784997776} PREDS {{258 0 0-2776 {}} {259 0 0-2782 {}}} SUCCS {{259 0 0-2784 {}} {258 0 0-2785 {}} {258 0 0-2788 {}} {258 0 0-2789 {}} {258 0 0-2790 {}} {258 0 0-2793 {}}} CYCLES {}}
+set a(0-2784) {NAME intensity:slc(intensity) TYPE READSLICE PAR 0-1913 XREFS 16480 LOC {3 0.53667895 3 0.983257525 3 0.983257525 3 0.983257525} PREDS {{259 0 0-2783 {}}} SUCCS {{258 0 0-2787 {}}} CYCLES {}}
+set a(0-2785) {NAME intensity:slc(intensity)#1 TYPE READSLICE PAR 0-1913 XREFS 16481 LOC {3 0.53667895 3 0.983257525 3 0.983257525 3 0.983257525} PREDS {{258 0 0-2783 {}}} SUCCS {{259 0 0-2786 {}}} CYCLES {}}
+set a(0-2786) {NAME FRAME:exu TYPE PADZEROES PAR 0-1913 XREFS 16482 LOC {3 0.53667895 3 0.983257525 3 0.983257525 3 0.983257525} PREDS {{259 0 0-2785 {}}} SUCCS {{259 0 0-2787 {}}} CYCLES {}}
+set a(0-2787) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(10,2) AREA_SCORE 7.30 QUANTITY 1 NAME FRAME:or TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-1913 XREFS 16483 LOC {3 0.53667895 3 0.983257525 3 0.983257525 3 0.9999999561077388 3 0.9999999561077388} PREDS {{258 0 0-2784 {}} {259 0 0-2786 {}}} SUCCS {{258 0 0-2794 {}}} CYCLES {}}
+set a(0-2788) {NAME intensity:slc(intensity)#2 TYPE READSLICE PAR 0-1913 XREFS 16484 LOC {3 0.53667895 3 0.983257525 3 0.983257525 3 1.0} PREDS {{258 0 0-2783 {}}} SUCCS {{258 0 0-2794 {}}} CYCLES {}}
+set a(0-2789) {NAME intensity:slc(intensity)#3 TYPE READSLICE PAR 0-1913 XREFS 16485 LOC {3 0.53667895 3 0.983257525 3 0.983257525 3 0.983257525} PREDS {{258 0 0-2783 {}}} SUCCS {{258 0 0-2792 {}}} CYCLES {}}
+set a(0-2790) {NAME intensity:slc(intensity)#4 TYPE READSLICE PAR 0-1913 XREFS 16486 LOC {3 0.53667895 3 0.983257525 3 0.983257525 3 0.983257525} PREDS {{258 0 0-2783 {}}} SUCCS {{259 0 0-2791 {}}} CYCLES {}}
+set a(0-2791) {NAME FRAME:exu#12 TYPE PADZEROES PAR 0-1913 XREFS 16487 LOC {3 0.53667895 3 0.983257525 3 0.983257525 3 0.983257525} PREDS {{259 0 0-2790 {}}} SUCCS {{259 0 0-2792 {}}} CYCLES {}}
+set a(0-2792) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(6,2) AREA_SCORE 4.38 QUANTITY 1 NAME FRAME:or#3 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-1913 XREFS 16488 LOC {3 0.53667895 3 0.983257525 3 0.983257525 3 0.9999999561077388 3 0.9999999561077388} PREDS {{258 0 0-2789 {}} {259 0 0-2791 {}}} SUCCS {{258 0 0-2794 {}}} CYCLES {}}
+set a(0-2793) {NAME intensity:slc(intensity)#5 TYPE READSLICE PAR 0-1913 XREFS 16489 LOC {3 0.53667895 3 0.983257525 3 0.983257525 3 1.0} PREDS {{258 0 0-2783 {}}} SUCCS {{259 0 0-2794 {}}} CYCLES {}}
+set a(0-2794) {NAME FRAME:conc#22 TYPE CONCATENATE PAR 0-1913 XREFS 16490 LOC {3 0.553421425 3 1.0 3 1.0 3 1.0} PREDS {{258 0 0-2792 {}} {258 0 0-2788 {}} {258 0 0-2787 {}} {259 0 0-2793 {}}} SUCCS {{259 0 0-2795 {}}} CYCLES {}}
+set a(0-2795) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(2,30) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_write(vout:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-1913 XREFS 16491 LOC {3 1.0 3 1.0 3 1.0 4 0.0 3 0.9999} PREDS {{260 0 0-2795 {}} {259 0 0-2794 {}}} SUCCS {{260 0 0-2795 {}}} CYCLES {}}
+set a(0-2796) {NAME FRAME:asn#3 TYPE ASSIGN PAR 0-1913 XREFS 16492 LOC {0 1.0 1 0.7916390999999999 1 0.7916390999999999 4 0.7916390999999999} PREDS {{262 0 0-2809 {}}} SUCCS {{259 0 0-2797 {}} {256 0 0-2809 {}}} CYCLES {}}
+set a(0-2797) {NAME FRAME:not#34 TYPE NOT PAR 0-1913 XREFS 16493 LOC {1 0.0 1 0.7916390999999999 1 0.7916390999999999 4 0.7916390999999999} PREDS {{259 0 0-2796 {}}} SUCCS {{259 0 0-2798 {}}} CYCLES {}}
+set a(0-2798) {NAME FRAME:exs TYPE SIGNEXTEND PAR 0-1913 XREFS 16494 LOC {1 0.0 1 0.7916390999999999 1 0.7916390999999999 4 0.7916390999999999} PREDS {{259 0 0-2797 {}}} SUCCS {{259 0 0-2799 {}}} CYCLES {}}
+set a(0-2799) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(19,2) AREA_SCORE 13.87 QUANTITY 1 NAME FRAME:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-1913 XREFS 16495 LOC {1 0.0 1 0.7916390999999999 1 0.7916390999999999 1 0.8080458312638539 4 0.8080458312638539} PREDS {{262 0 0-2802 {}} {259 0 0-2798 {}}} SUCCS {{259 0 0-2800 {}} {256 0 0-2802 {}}} CYCLES {}}
+set a(0-2800) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(19,0,2,1,19) AREA_SCORE 20.00 QUANTITY 1 NAME FRAME:acc#7 TYPE ACCU DELAY {1.91 ns} LIBRARY_DELAY {1.91 ns} PAR 0-1913 XREFS 16496 LOC {1 0.016406775 1 0.8080458749999999 1 0.8080458749999999 1 0.9273051910815965 4 0.9273051910815965} PREDS {{259 0 0-2799 {}}} SUCCS {{258 0 0-2802 {}} {258 0 0-2805 {}}} CYCLES {}}
+set a(0-2801) {NAME FRAME:asn(regs.regs(0).sva) TYPE ASSIGN PAR 0-1913 XREFS 16497 LOC {1 0.0 1 0.039018275 1 0.039018275 3 0.40483722499999997} PREDS {{260 0 0-2801 {}} {256 0 0-1916 {}} {256 0 0-1918 {}} {258 0 0-1920 {}}} SUCCS {{262 0 0-1916 {}} {262 0 0-1918 {}} {260 0 0-2801 {}}} CYCLES {}}
+set a(0-2802) {NAME FRAME:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-1913 XREFS 16498 LOC {1 0.13566614999999999 1 0.92730525 1 0.92730525 4 1.0} PREDS {{260 0 0-2802 {}} {256 0 0-2799 {}} {258 0 0-2800 {}}} SUCCS {{262 0 0-2799 {}} {260 0 0-2802 {}}} CYCLES {}}
+set a(0-2803) {NAME FRAME:asn(regs.regs(1).sg2.sva) TYPE ASSIGN PAR 0-1913 XREFS 16499 LOC {0 1.0 0 1.0 0 1.0 2 0.409023875} PREDS {{260 0 0-2803 {}} {256 0 0-2210 {}} {256 0 0-2215 {}} {256 0 0-2221 {}} {258 0 0-1919 {}}} SUCCS {{262 0 0-2210 {}} {262 0 0-2215 {}} {262 0 0-2221 {}} {260 0 0-2803 {}}} CYCLES {}}
+set a(0-2804) {NAME FRAME:asn(regs.regs(1)#1.sva) TYPE ASSIGN PAR 0-1913 XREFS 16500 LOC {0 1.0 0 1.0 0 1.0 2 0.40483722499999997} PREDS {{260 0 0-2804 {}} {256 0 0-2099 {}} {256 0 0-2108 {}} {256 0 0-2118 {}} {258 0 0-1917 {}}} SUCCS {{262 0 0-2099 {}} {262 0 0-2108 {}} {262 0 0-2118 {}} {260 0 0-2804 {}}} CYCLES {}}
+set a(0-2805) {NAME FRAME:p:slc(FRAME:p)#1 TYPE READSLICE PAR 0-1913 XREFS 16501 LOC {1 0.13566614999999999 1 0.92730525 1 0.92730525 4 0.92730525} PREDS {{258 0 0-2800 {}}} SUCCS {{259 0 0-2806 {}}} CYCLES {}}
+set a(0-2806) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,9) AREA_SCORE 9.26 QUANTITY 2 NAME FRAME:acc TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-1913 XREFS 16502 LOC {1 0.13566614999999999 1 0.92730525 1 0.92730525 1 0.9999999527684257 4 0.9999999527684257} PREDS {{259 0 0-2805 {}}} SUCCS {{259 0 0-2807 {}}} CYCLES {}}
+set a(0-2807) {NAME FRAME:slc TYPE READSLICE PAR 0-1913 XREFS 16503 LOC {1 0.2083609 1 1.0 1 1.0 4 1.0} PREDS {{259 0 0-2806 {}}} SUCCS {{259 0 0-2808 {}}} CYCLES {}}
+set a(0-2808) {NAME FRAME:not TYPE NOT PAR 0-1913 XREFS 16504 LOC {1 0.2083609 1 1.0 1 1.0 4 1.0} PREDS {{259 0 0-2807 {}}} SUCCS {{259 0 0-2809 {}}} CYCLES {}}
+set a(0-2809) {NAME FRAME:asn#4 TYPE ASSIGN PAR 0-1913 XREFS 16505 LOC {1 0.2083609 1 1.0 1 1.0 4 1.0} PREDS {{260 0 0-2809 {}} {256 0 0-1914 {}} {256 0 0-2796 {}} {259 0 0-2808 {}}} SUCCS {{262 0 0-1914 {}} {262 0 0-2796 {}} {260 0 0-2809 {}}} CYCLES {}}
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0-2626 0-2627 0-2628 0-2629 0-2630 0-2631 0-2632 0-2633 0-2634 0-2635 0-2636 0-2637 0-2638 0-2639 0-2640 0-2641 0-2642 0-2643 0-2644 0-2645 0-2646 0-2647 0-2648 0-2649 0-2650 0-2651 0-2652 0-2653 0-2654 0-2655 0-2656 0-2657 0-2658 0-2659 0-2660 0-2661 0-2662 0-2663 0-2664 0-2665 0-2666 0-2667 0-2668 0-2669 0-2670 0-2671 0-2672 0-2673 0-2674 0-2675 0-2676 0-2677 0-2678 0-2679 0-2680 0-2681 0-2682 0-2683 0-2684 0-2685 0-2686 0-2687 0-2688 0-2689 0-2690 0-2691 0-2692 0-2693 0-2694 0-2695 0-2696 0-2697 0-2698 0-2699 0-2700 0-2701 0-2702 0-2703 0-2704 0-2705 0-2706 0-2707 0-2708 0-2709 0-2710 0-2711 0-2712 0-2713 0-2714 0-2715 0-2716 0-2717 0-2718 0-2719 0-2720 0-2721 0-2722 0-2723 0-2724 0-2725 0-2726 0-2727 0-2728 0-2729 0-2730 0-2731 0-2732 0-2733 0-2734 0-2735 0-2736 0-2737 0-2738 0-2739 0-2740 0-2741 0-2742 0-2743 0-2744 0-2745 0-2746 0-2747 0-2748 0-2749 0-2750 0-2751 0-2752 0-2753 0-2754 0-2755 0-2756 0-2757 0-2758 0-2759 0-2760 0-2761 0-2762 0-2763 0-2764 0-2765 0-2766 0-2767 0-2768 0-2769 0-2770 0-2771 0-2772 0-2773 0-2774 0-2775 0-2776 0-2777 0-2778 0-2779 0-2780 0-2781 0-2782 0-2783 0-2784 0-2785 0-2786 0-2787 0-2788 0-2789 0-2790 0-2791 0-2792 0-2793 0-2794 0-2795 0-2796 0-2797 0-2798 0-2799 0-2800 0-2801 0-2802 0-2803 0-2804 0-2805 0-2806 0-2807 0-2808 0-2809} ITERATIONS Infinite LATENCY 307202 RESET_LATENCY 0 CSTEPS 4 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 307200 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 4.0 CYCLES_IN 307203 TOTAL_CYCLES_IN 307203 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 307203 NAME main TYPE LOOP DELAY {6144080.00 ns} PAR 0-1907 XREFS 16506 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{258 0 0-1908 {}} {258 0 0-1910 {}} {258 0 0-1909 {}} {258 0 0-1911 {}} {259 0 0-1912 {}}} SUCCS {{772 0 0-1908 {}} {772 0 0-1909 {}} {772 0 0-1910 {}} {772 0 0-1911 {}} {772 0 0-1912 {}}} CYCLES {}}
+set a(0-1907) {CHI {0-1908 0-1909 0-1910 0-1911 0-1912 0-1913} ITERATIONS Infinite LATENCY 307202 RESET_LATENCY 0 CSTEPS 0 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 307200 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 0 TOTAL_CYCLES_IN 0 TOTAL_CYCLES_UNDER 307203 TOTAL_CYCLES 307203 NAME core:rlp TYPE LOOP DELAY {6144080.00 ns} PAR {} XREFS 16507 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-1907-TOTALCYCLES) {307203}
+set a(0-1907-QMOD) {mgc_ioport.mgc_in_wire(1,90) 0-1920 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,17) {0-1925 0-2014 0-2117 0-2219 0-2337 0-2354 0-2355 0-2726 0-2727} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(17,0,16,0,18) {0-1928 0-2017 0-2127 0-2225} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3) {0-1934 0-1951 0-1966 0-1975 0-1997 0-2023 0-2040 0-2055 0-2064 0-2086 0-2133 0-2150 0-2165 0-2174 0-2196 0-2231 0-2248 0-2263 0-2272 0-2294 0-2342 0-2344 0-2385 0-2390 0-2396 0-2401 0-2408 0-2413 0-2419 0-2424 0-2432 0-2437 0-2443 0-2448 0-2457 0-2464 0-2472 0-2479 0-2534 0-2551 0-2557 0-2562 0-2569 0-2574 0-2583 0-2612 0-2660 0-2665} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4) {0-1942 0-1979 0-2005 0-2009 0-2031 0-2068 0-2094 0-2098 0-2141 0-2178 0-2204 0-2208 0-2239 0-2276 0-2302 0-2306 0-2391 0-2402 0-2414 0-2425 0-2438 0-2449 0-2465 0-2480 0-2546 0-2552 0-2563 0-2575 0-2596 0-2607 0-2613 0-2627 0-2666 0-2732 0-2739 0-2744 0-2767} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5) {0-1956 0-2045 0-2155 0-2253 0-2403 0-2426 0-2450 0-2481 0-2564 0-2614 0-2643 0-2740 0-2770} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6) {0-1983 0-2072 0-2182 0-2280 0-2427 0-2482 0-2615 0-2649 0-2667 0-2745 0-2761 0-2773} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6) {0-1990 0-2079 0-2189 0-2287 0-2746} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12) {0-2105 0-2114 0-2124} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11) {0-2212 0-2217 0-2223} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2) {0-2309 0-2317 0-2323 0-2333 0-2340 0-2352 0-2358 0-2365 0-2376 0-2487 0-2495 0-2500 0-2506 0-2514 0-2522 0-2670 0-2677 0-2683 0-2706 0-2712 0-2721} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,11,0,12) {0-2310 0-2318 0-2496} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11) {0-2324 0-2507 0-2678 0-2713 0-2748} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,0,13,0,14) 0-2329 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,15,0,16) {0-2330 0-2725} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,15,0,16) {0-2334 0-2353} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,11,0,12) 0-2345 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,13,0,14) {0-2359 0-2501 0-2722} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,7,0,8) {0-2366 0-2488 0-2515 0-2707} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9) {0-2377 0-2523 0-2671 0-2684 0-2750} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9) {0-2380 0-2484} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7) {0-2483 0-2650 0-2672} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,10) {0-2491 0-2674 0-2775} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12) {0-2492 0-2776} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,12,1,14) {0-2497 0-2680 0-2783} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(14,0,14,1,15) {0-2502 0-2718} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,15,1,16) 0-2503 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8) {0-2673 0-2703} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,11) {0-2679 0-2709} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9) {0-2708 0-2806} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,0,12) 0-2716 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,12,0,13) 0-2717 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8) 0-2774 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2) 0-2787 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2) 0-2792 mgc_ioport.mgc_out_stdreg(2,30) 0-2795 mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2) 0-2799 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19) 0-2800}
+set a(0-1907-PROC_NAME) {core}
+set a(0-1907-HIER_NAME) {/sobel/core}
+set a(TOP) {0-1907}
+
diff --git a/Sobel/sobel.v6/schematic.nlv b/Sobel/sobel.v6/schematic.nlv
new file mode 100644
index 0000000..b4bfc9d
--- /dev/null
+++ b/Sobel/sobel.v6/schematic.nlv
@@ -0,0 +1,10181 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "sobel:core" "orig"
+load port {clk} input -attr xrf 17855 -attr oid 1 -attr vt d -attr @path {/sobel/sobel:core/clk}
+load port {en} input -attr xrf 17856 -attr oid 2 -attr vt d -attr @path {/sobel/sobel:core/en}
+load port {arst_n} input -attr xrf 17857 -attr oid 3 -attr vt d -attr @path {/sobel/sobel:core/arst_n}
+load portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} -attr xrf 17858 -attr oid 4 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} -attr xrf 17859 -attr oid 5 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load symbol "or(2,10)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,6)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(5:0)} input 6 {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(5:0)} input 6 {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,30)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(29:0)} input 30 {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(29:0)} input 30 {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(30,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(29:0)} input 30 {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(29:0)} input 30 {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(2,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(1:0)} input 2 {D(1)} {D(0)} \
+     portBus {DRa(1:0)} input 2 {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "reg(3,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(2:0)} input 3 {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(2:0)} input 3 {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(6,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(5:0)} input 6 {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(5:0)} input 6 {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(1,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(0:0)} input 1 {D(0)} \
+     portBus {DRa(0:0)} input 1 {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "not(3)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(3,0,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(1,0,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,11,0,12)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,10)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(13,0,13,0,14)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(12:0)} input 13 {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(12:0)} input 13 {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(13:0)} output 14 {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(15,0,14,0,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(14:0)} input 15 {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(13:0)} input 14 {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,15,-1,15)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(14:0)} input 15 {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,16,-1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,1,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,11,0,12)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,15,0,16)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(14:0)} input 15 {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(16,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(15:0)} input 16 {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(15:0)} input 16 {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,13,-1,13)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(12:0)} input 13 {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(13,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(12:0)} input 13 {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(12:0)} input 13 {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,7,0,8)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(8,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(7:0)} input 8 {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(7:0)} input 8 {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,5,0,6)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,-1,7,-1,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,6,0,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,1,7,0,9)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,1,9,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(10,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(9:0)} input 10 {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(9:0)} input 10 {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(12,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(11:0)} input 12 {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(11:0)} input 12 {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,13,0,14)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(12:0)} input 13 {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(13:0)} output 14 {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(14,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(13:0)} input 14 {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(13:0)} input 14 {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(13:0)} output 14 {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(7,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(6:0)} input 7 {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(6:0)} input 7 {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,0,8,0,9)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,9,0,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,0,11,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,6,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,0,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,-1,11,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,-1,6,-1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,1,12,0,14)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(13:0)} output 14 {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(14,1,14,0,15)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(13:0)} input 14 {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(13:0)} input 14 {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,15,1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(14:0)} input 15 {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,7,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,10,0,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,0,12,0,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(14,0,13,0,15)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(13:0)} input 14 {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(12:0)} input 13 {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(15,0,15,0,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(14:0)} input 15 {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(14:0)} input 15 {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,0,16,0,17)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(16:0)} output 17 {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(17,0,16,0,18)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(16:0)} input 17 {A(16)} {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(17:0)} output 18 {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(10)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,11,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,10,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,3,-1,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load net {regs.regs(1)#1.sva(0)} -attr vt d
+load net {regs.regs(1)#1.sva(1)} -attr vt d
+load net {regs.regs(1)#1.sva(2)} -attr vt d
+load net {regs.regs(1)#1.sva(3)} -attr vt d
+load net {regs.regs(1)#1.sva(4)} -attr vt d
+load net {regs.regs(1)#1.sva(5)} -attr vt d
+load net {regs.regs(1)#1.sva(6)} -attr vt d
+load net {regs.regs(1)#1.sva(7)} -attr vt d
+load net {regs.regs(1)#1.sva(8)} -attr vt d
+load net {regs.regs(1)#1.sva(9)} -attr vt d
+load net {regs.regs(1)#1.sva(10)} -attr vt d
+load net {regs.regs(1)#1.sva(11)} -attr vt d
+load net {regs.regs(1)#1.sva(12)} -attr vt d
+load net {regs.regs(1)#1.sva(13)} -attr vt d
+load net {regs.regs(1)#1.sva(14)} -attr vt d
+load net {regs.regs(1)#1.sva(15)} -attr vt d
+load net {regs.regs(1)#1.sva(16)} -attr vt d
+load net {regs.regs(1)#1.sva(17)} -attr vt d
+load net {regs.regs(1)#1.sva(18)} -attr vt d
+load net {regs.regs(1)#1.sva(19)} -attr vt d
+load net {regs.regs(1)#1.sva(20)} -attr vt d
+load net {regs.regs(1)#1.sva(21)} -attr vt d
+load net {regs.regs(1)#1.sva(22)} -attr vt d
+load net {regs.regs(1)#1.sva(23)} -attr vt d
+load net {regs.regs(1)#1.sva(24)} -attr vt d
+load net {regs.regs(1)#1.sva(25)} -attr vt d
+load net {regs.regs(1)#1.sva(26)} -attr vt d
+load net {regs.regs(1)#1.sva(27)} -attr vt d
+load net {regs.regs(1)#1.sva(28)} -attr vt d
+load net {regs.regs(1)#1.sva(29)} -attr vt d
+load netBundle {regs.regs(1)#1.sva} 30 {regs.regs(1)#1.sva(0)} {regs.regs(1)#1.sva(1)} {regs.regs(1)#1.sva(2)} {regs.regs(1)#1.sva(3)} {regs.regs(1)#1.sva(4)} {regs.regs(1)#1.sva(5)} {regs.regs(1)#1.sva(6)} {regs.regs(1)#1.sva(7)} {regs.regs(1)#1.sva(8)} {regs.regs(1)#1.sva(9)} {regs.regs(1)#1.sva(10)} {regs.regs(1)#1.sva(11)} {regs.regs(1)#1.sva(12)} {regs.regs(1)#1.sva(13)} {regs.regs(1)#1.sva(14)} {regs.regs(1)#1.sva(15)} {regs.regs(1)#1.sva(16)} {regs.regs(1)#1.sva(17)} {regs.regs(1)#1.sva(18)} {regs.regs(1)#1.sva(19)} {regs.regs(1)#1.sva(20)} {regs.regs(1)#1.sva(21)} {regs.regs(1)#1.sva(22)} {regs.regs(1)#1.sva(23)} {regs.regs(1)#1.sva(24)} {regs.regs(1)#1.sva(25)} {regs.regs(1)#1.sva(26)} {regs.regs(1)#1.sva(27)} {regs.regs(1)#1.sva(28)} {regs.regs(1)#1.sva(29)} -attr xrf 17860 -attr oid 6 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1).sg2.sva(0)} -attr vt d
+load net {regs.regs(1).sg2.sva(1)} -attr vt d
+load net {regs.regs(1).sg2.sva(2)} -attr vt d
+load net {regs.regs(1).sg2.sva(3)} -attr vt d
+load net {regs.regs(1).sg2.sva(4)} -attr vt d
+load net {regs.regs(1).sg2.sva(5)} -attr vt d
+load net {regs.regs(1).sg2.sva(6)} -attr vt d
+load net {regs.regs(1).sg2.sva(7)} -attr vt d
+load net {regs.regs(1).sg2.sva(8)} -attr vt d
+load net {regs.regs(1).sg2.sva(9)} -attr vt d
+load net {regs.regs(1).sg2.sva(10)} -attr vt d
+load net {regs.regs(1).sg2.sva(11)} -attr vt d
+load net {regs.regs(1).sg2.sva(12)} -attr vt d
+load net {regs.regs(1).sg2.sva(13)} -attr vt d
+load net {regs.regs(1).sg2.sva(14)} -attr vt d
+load net {regs.regs(1).sg2.sva(15)} -attr vt d
+load net {regs.regs(1).sg2.sva(16)} -attr vt d
+load net {regs.regs(1).sg2.sva(17)} -attr vt d
+load net {regs.regs(1).sg2.sva(18)} -attr vt d
+load net {regs.regs(1).sg2.sva(19)} -attr vt d
+load net {regs.regs(1).sg2.sva(20)} -attr vt d
+load net {regs.regs(1).sg2.sva(21)} -attr vt d
+load net {regs.regs(1).sg2.sva(22)} -attr vt d
+load net {regs.regs(1).sg2.sva(23)} -attr vt d
+load net {regs.regs(1).sg2.sva(24)} -attr vt d
+load net {regs.regs(1).sg2.sva(25)} -attr vt d
+load net {regs.regs(1).sg2.sva(26)} -attr vt d
+load net {regs.regs(1).sg2.sva(27)} -attr vt d
+load net {regs.regs(1).sg2.sva(28)} -attr vt d
+load net {regs.regs(1).sg2.sva(29)} -attr vt d
+load netBundle {regs.regs(1).sg2.sva} 30 {regs.regs(1).sg2.sva(0)} {regs.regs(1).sg2.sva(1)} {regs.regs(1).sg2.sva(2)} {regs.regs(1).sg2.sva(3)} {regs.regs(1).sg2.sva(4)} {regs.regs(1).sg2.sva(5)} {regs.regs(1).sg2.sva(6)} {regs.regs(1).sg2.sva(7)} {regs.regs(1).sg2.sva(8)} {regs.regs(1).sg2.sva(9)} {regs.regs(1).sg2.sva(10)} {regs.regs(1).sg2.sva(11)} {regs.regs(1).sg2.sva(12)} {regs.regs(1).sg2.sva(13)} {regs.regs(1).sg2.sva(14)} {regs.regs(1).sg2.sva(15)} {regs.regs(1).sg2.sva(16)} {regs.regs(1).sg2.sva(17)} {regs.regs(1).sg2.sva(18)} {regs.regs(1).sg2.sva(19)} {regs.regs(1).sg2.sva(20)} {regs.regs(1).sg2.sva(21)} {regs.regs(1).sg2.sva(22)} {regs.regs(1).sg2.sva(23)} {regs.regs(1).sg2.sva(24)} {regs.regs(1).sg2.sva(25)} {regs.regs(1).sg2.sva(26)} {regs.regs(1).sg2.sva(27)} {regs.regs(1).sg2.sva(28)} {regs.regs(1).sg2.sva(29)} -attr xrf 17861 -attr oid 7 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs:slc(regs.regs(2))#6.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#6.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#6.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#6.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#6.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#6.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#6.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#6.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#6.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#6.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#6.itm} 10 {regs.regs:slc(regs.regs(2))#6.itm(0)} {regs.regs:slc(regs.regs(2))#6.itm(1)} {regs.regs:slc(regs.regs(2))#6.itm(2)} {regs.regs:slc(regs.regs(2))#6.itm(3)} {regs.regs:slc(regs.regs(2))#6.itm(4)} {regs.regs:slc(regs.regs(2))#6.itm(5)} {regs.regs:slc(regs.regs(2))#6.itm(6)} {regs.regs:slc(regs.regs(2))#6.itm(7)} {regs.regs:slc(regs.regs(2))#6.itm(8)} {regs.regs:slc(regs.regs(2))#6.itm(9)} -attr xrf 17862 -attr oid 8 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#7.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#7.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#7.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#7.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#7.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#7.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#7.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#7.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2))#7.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2))#7.itm} 10 {regs.regs:slc(regs.regs(2))#7.itm(0)} {regs.regs:slc(regs.regs(2))#7.itm(1)} {regs.regs:slc(regs.regs(2))#7.itm(2)} {regs.regs:slc(regs.regs(2))#7.itm(3)} {regs.regs:slc(regs.regs(2))#7.itm(4)} {regs.regs:slc(regs.regs(2))#7.itm(5)} {regs.regs:slc(regs.regs(2))#7.itm(6)} {regs.regs:slc(regs.regs(2))#7.itm(7)} {regs.regs:slc(regs.regs(2))#7.itm(8)} {regs.regs:slc(regs.regs(2))#7.itm(9)} -attr xrf 17863 -attr oid 9 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2)).itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2)).itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2)).itm} 10 {regs.regs:slc(regs.regs(2)).itm(0)} {regs.regs:slc(regs.regs(2)).itm(1)} {regs.regs:slc(regs.regs(2)).itm(2)} {regs.regs:slc(regs.regs(2)).itm(3)} {regs.regs:slc(regs.regs(2)).itm(4)} {regs.regs:slc(regs.regs(2)).itm(5)} {regs.regs:slc(regs.regs(2)).itm(6)} {regs.regs:slc(regs.regs(2)).itm(7)} {regs.regs:slc(regs.regs(2)).itm(8)} {regs.regs:slc(regs.regs(2)).itm(9)} -attr xrf 17864 -attr oid 10 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2).sg2)#1.itm} 10 {regs.regs:slc(regs.regs(2).sg2)#1.itm(0)} {regs.regs:slc(regs.regs(2).sg2)#1.itm(1)} {regs.regs:slc(regs.regs(2).sg2)#1.itm(2)} {regs.regs:slc(regs.regs(2).sg2)#1.itm(3)} {regs.regs:slc(regs.regs(2).sg2)#1.itm(4)} {regs.regs:slc(regs.regs(2).sg2)#1.itm(5)} {regs.regs:slc(regs.regs(2).sg2)#1.itm(6)} {regs.regs:slc(regs.regs(2).sg2)#1.itm(7)} {regs.regs:slc(regs.regs(2).sg2)#1.itm(8)} {regs.regs:slc(regs.regs(2).sg2)#1.itm(9)} -attr xrf 17865 -attr oid 11 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2).sg2)#2.itm} 10 {regs.regs:slc(regs.regs(2).sg2)#2.itm(0)} {regs.regs:slc(regs.regs(2).sg2)#2.itm(1)} {regs.regs:slc(regs.regs(2).sg2)#2.itm(2)} {regs.regs:slc(regs.regs(2).sg2)#2.itm(3)} {regs.regs:slc(regs.regs(2).sg2)#2.itm(4)} {regs.regs:slc(regs.regs(2).sg2)#2.itm(5)} {regs.regs:slc(regs.regs(2).sg2)#2.itm(6)} {regs.regs:slc(regs.regs(2).sg2)#2.itm(7)} {regs.regs:slc(regs.regs(2).sg2)#2.itm(8)} {regs.regs:slc(regs.regs(2).sg2)#2.itm(9)} -attr xrf 17866 -attr oid 12 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(0)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2).itm(1)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2).itm(2)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2).itm(3)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2).itm(4)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2).itm(5)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2).itm(6)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2).itm(7)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2).itm(8)} -attr vt d
+load net {regs.regs:slc(regs.regs(2).sg2).itm(9)} -attr vt d
+load netBundle {regs.regs:slc(regs.regs(2).sg2).itm} 10 {regs.regs:slc(regs.regs(2).sg2).itm(0)} {regs.regs:slc(regs.regs(2).sg2).itm(1)} {regs.regs:slc(regs.regs(2).sg2).itm(2)} {regs.regs:slc(regs.regs(2).sg2).itm(3)} {regs.regs:slc(regs.regs(2).sg2).itm(4)} {regs.regs:slc(regs.regs(2).sg2).itm(5)} {regs.regs:slc(regs.regs(2).sg2).itm(6)} {regs.regs:slc(regs.regs(2).sg2).itm(7)} {regs.regs:slc(regs.regs(2).sg2).itm(8)} {regs.regs:slc(regs.regs(2).sg2).itm(9)} -attr xrf 17867 -attr oid 13 -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {ACC1:acc#281.itm#1(0)} -attr vt d
+load net {ACC1:acc#281.itm#1(1)} -attr vt d
+load net {ACC1:acc#281.itm#1(2)} -attr vt d
+load net {ACC1:acc#281.itm#1(3)} -attr vt d
+load net {ACC1:acc#281.itm#1(4)} -attr vt d
+load net {ACC1:acc#281.itm#1(5)} -attr vt d
+load net {ACC1:acc#281.itm#1(6)} -attr vt d
+load net {ACC1:acc#281.itm#1(7)} -attr vt d
+load net {ACC1:acc#281.itm#1(8)} -attr vt d
+load net {ACC1:acc#281.itm#1(9)} -attr vt d
+load net {ACC1:acc#281.itm#1(10)} -attr vt d
+load net {ACC1:acc#281.itm#1(11)} -attr vt d
+load net {ACC1:acc#281.itm#1(12)} -attr vt d
+load net {ACC1:acc#281.itm#1(13)} -attr vt d
+load net {ACC1:acc#281.itm#1(14)} -attr vt d
+load net {ACC1:acc#281.itm#1(15)} -attr vt d
+load netBundle {ACC1:acc#281.itm#1} 16 {ACC1:acc#281.itm#1(0)} {ACC1:acc#281.itm#1(1)} {ACC1:acc#281.itm#1(2)} {ACC1:acc#281.itm#1(3)} {ACC1:acc#281.itm#1(4)} {ACC1:acc#281.itm#1(5)} {ACC1:acc#281.itm#1(6)} {ACC1:acc#281.itm#1(7)} {ACC1:acc#281.itm#1(8)} {ACC1:acc#281.itm#1(9)} {ACC1:acc#281.itm#1(10)} {ACC1:acc#281.itm#1(11)} {ACC1:acc#281.itm#1(12)} {ACC1:acc#281.itm#1(13)} {ACC1:acc#281.itm#1(14)} {ACC1:acc#281.itm#1(15)} -attr xrf 17868 -attr oid 14 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {mul#1.itm#1(0)} -attr vt d
+load net {mul#1.itm#1(1)} -attr vt d
+load net {mul#1.itm#1(2)} -attr vt d
+load net {mul#1.itm#1(3)} -attr vt d
+load net {mul#1.itm#1(4)} -attr vt d
+load net {mul#1.itm#1(5)} -attr vt d
+load net {mul#1.itm#1(6)} -attr vt d
+load net {mul#1.itm#1(7)} -attr vt d
+load net {mul#1.itm#1(8)} -attr vt d
+load net {mul#1.itm#1(9)} -attr vt d
+load net {mul#1.itm#1(10)} -attr vt d
+load net {mul#1.itm#1(11)} -attr vt d
+load net {mul#1.itm#1(12)} -attr vt d
+load netBundle {mul#1.itm#1} 13 {mul#1.itm#1(0)} {mul#1.itm#1(1)} {mul#1.itm#1(2)} {mul#1.itm#1(3)} {mul#1.itm#1(4)} {mul#1.itm#1(5)} {mul#1.itm#1(6)} {mul#1.itm#1(7)} {mul#1.itm#1(8)} {mul#1.itm#1(9)} {mul#1.itm#1(10)} {mul#1.itm#1(11)} {mul#1.itm#1(12)} -attr xrf 17869 -attr oid 15 -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load net {ACC1:mul#99.itm#1(0)} -attr vt d
+load net {ACC1:mul#99.itm#1(1)} -attr vt d
+load net {ACC1:mul#99.itm#1(2)} -attr vt d
+load net {ACC1:mul#99.itm#1(3)} -attr vt d
+load net {ACC1:mul#99.itm#1(4)} -attr vt d
+load net {ACC1:mul#99.itm#1(5)} -attr vt d
+load net {ACC1:mul#99.itm#1(6)} -attr vt d
+load net {ACC1:mul#99.itm#1(7)} -attr vt d
+load netBundle {ACC1:mul#99.itm#1} 8 {ACC1:mul#99.itm#1(0)} {ACC1:mul#99.itm#1(1)} {ACC1:mul#99.itm#1(2)} {ACC1:mul#99.itm#1(3)} {ACC1:mul#99.itm#1(4)} {ACC1:mul#99.itm#1(5)} {ACC1:mul#99.itm#1(6)} {ACC1:mul#99.itm#1(7)} -attr xrf 17870 -attr oid 16 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm#1}
+load net {ACC1:acc#264.itm#1(0)} -attr vt d
+load net {ACC1:acc#264.itm#1(1)} -attr vt d
+load net {ACC1:acc#264.itm#1(2)} -attr vt d
+load net {ACC1:acc#264.itm#1(3)} -attr vt d
+load net {ACC1:acc#264.itm#1(4)} -attr vt d
+load net {ACC1:acc#264.itm#1(5)} -attr vt d
+load net {ACC1:acc#264.itm#1(6)} -attr vt d
+load net {ACC1:acc#264.itm#1(7)} -attr vt d
+load net {ACC1:acc#264.itm#1(8)} -attr vt d
+load net {ACC1:acc#264.itm#1(9)} -attr vt d
+load netBundle {ACC1:acc#264.itm#1} 10 {ACC1:acc#264.itm#1(0)} {ACC1:acc#264.itm#1(1)} {ACC1:acc#264.itm#1(2)} {ACC1:acc#264.itm#1(3)} {ACC1:acc#264.itm#1(4)} {ACC1:acc#264.itm#1(5)} {ACC1:acc#264.itm#1(6)} {ACC1:acc#264.itm#1(7)} {ACC1:acc#264.itm#1(8)} {ACC1:acc#264.itm#1(9)} -attr xrf 17871 -attr oid 17 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:mul#90.itm#1(0)} -attr vt d
+load net {ACC1:mul#90.itm#1(1)} -attr vt d
+load net {ACC1:mul#90.itm#1(2)} -attr vt d
+load net {ACC1:mul#90.itm#1(3)} -attr vt d
+load net {ACC1:mul#90.itm#1(4)} -attr vt d
+load net {ACC1:mul#90.itm#1(5)} -attr vt d
+load net {ACC1:mul#90.itm#1(6)} -attr vt d
+load net {ACC1:mul#90.itm#1(7)} -attr vt d
+load net {ACC1:mul#90.itm#1(8)} -attr vt d
+load net {ACC1:mul#90.itm#1(9)} -attr vt d
+load net {ACC1:mul#90.itm#1(10)} -attr vt d
+load net {ACC1:mul#90.itm#1(11)} -attr vt d
+load netBundle {ACC1:mul#90.itm#1} 12 {ACC1:mul#90.itm#1(0)} {ACC1:mul#90.itm#1(1)} {ACC1:mul#90.itm#1(2)} {ACC1:mul#90.itm#1(3)} {ACC1:mul#90.itm#1(4)} {ACC1:mul#90.itm#1(5)} {ACC1:mul#90.itm#1(6)} {ACC1:mul#90.itm#1(7)} {ACC1:mul#90.itm#1(8)} {ACC1:mul#90.itm#1(9)} {ACC1:mul#90.itm#1(10)} {ACC1:mul#90.itm#1(11)} -attr xrf 17872 -attr oid 18 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#91.itm#1(0)} -attr vt d
+load net {ACC1:mul#91.itm#1(1)} -attr vt d
+load net {ACC1:mul#91.itm#1(2)} -attr vt d
+load net {ACC1:mul#91.itm#1(3)} -attr vt d
+load net {ACC1:mul#91.itm#1(4)} -attr vt d
+load net {ACC1:mul#91.itm#1(5)} -attr vt d
+load net {ACC1:mul#91.itm#1(6)} -attr vt d
+load net {ACC1:mul#91.itm#1(7)} -attr vt d
+load net {ACC1:mul#91.itm#1(8)} -attr vt d
+load net {ACC1:mul#91.itm#1(9)} -attr vt d
+load net {ACC1:mul#91.itm#1(10)} -attr vt d
+load net {ACC1:mul#91.itm#1(11)} -attr vt d
+load net {ACC1:mul#91.itm#1(12)} -attr vt d
+load net {ACC1:mul#91.itm#1(13)} -attr vt d
+load netBundle {ACC1:mul#91.itm#1} 14 {ACC1:mul#91.itm#1(0)} {ACC1:mul#91.itm#1(1)} {ACC1:mul#91.itm#1(2)} {ACC1:mul#91.itm#1(3)} {ACC1:mul#91.itm#1(4)} {ACC1:mul#91.itm#1(5)} {ACC1:mul#91.itm#1(6)} {ACC1:mul#91.itm#1(7)} {ACC1:mul#91.itm#1(8)} {ACC1:mul#91.itm#1(9)} {ACC1:mul#91.itm#1(10)} {ACC1:mul#91.itm#1(11)} {ACC1:mul#91.itm#1(12)} {ACC1:mul#91.itm#1(13)} -attr xrf 17873 -attr oid 19 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#104.itm#1(0)} -attr vt d
+load net {ACC1:mul#104.itm#1(1)} -attr vt d
+load net {ACC1:mul#104.itm#1(2)} -attr vt d
+load net {ACC1:mul#104.itm#1(3)} -attr vt d
+load net {ACC1:mul#104.itm#1(4)} -attr vt d
+load net {ACC1:mul#104.itm#1(5)} -attr vt d
+load net {ACC1:mul#104.itm#1(6)} -attr vt d
+load net {ACC1:mul#104.itm#1(7)} -attr vt d
+load net {ACC1:mul#104.itm#1(8)} -attr vt d
+load net {ACC1:mul#104.itm#1(9)} -attr vt d
+load netBundle {ACC1:mul#104.itm#1} 10 {ACC1:mul#104.itm#1(0)} {ACC1:mul#104.itm#1(1)} {ACC1:mul#104.itm#1(2)} {ACC1:mul#104.itm#1(3)} {ACC1:mul#104.itm#1(4)} {ACC1:mul#104.itm#1(5)} {ACC1:mul#104.itm#1(6)} {ACC1:mul#104.itm#1(7)} {ACC1:mul#104.itm#1(8)} {ACC1:mul#104.itm#1(9)} -attr xrf 17874 -attr oid 20 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm#1}
+load net {ACC1:mul#103.itm#1(0)} -attr vt d
+load net {ACC1:mul#103.itm#1(1)} -attr vt d
+load net {ACC1:mul#103.itm#1(2)} -attr vt d
+load net {ACC1:mul#103.itm#1(3)} -attr vt d
+load net {ACC1:mul#103.itm#1(4)} -attr vt d
+load net {ACC1:mul#103.itm#1(5)} -attr vt d
+load net {ACC1:mul#103.itm#1(6)} -attr vt d
+load net {ACC1:mul#103.itm#1(7)} -attr vt d
+load netBundle {ACC1:mul#103.itm#1} 8 {ACC1:mul#103.itm#1(0)} {ACC1:mul#103.itm#1(1)} {ACC1:mul#103.itm#1(2)} {ACC1:mul#103.itm#1(3)} {ACC1:mul#103.itm#1(4)} {ACC1:mul#103.itm#1(5)} {ACC1:mul#103.itm#1(6)} {ACC1:mul#103.itm#1(7)} -attr xrf 17875 -attr oid 21 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm#1}
+load net {ACC1:mul#98.itm#1(0)} -attr vt d
+load net {ACC1:mul#98.itm#1(1)} -attr vt d
+load net {ACC1:mul#98.itm#1(2)} -attr vt d
+load net {ACC1:mul#98.itm#1(3)} -attr vt d
+load net {ACC1:mul#98.itm#1(4)} -attr vt d
+load net {ACC1:mul#98.itm#1(5)} -attr vt d
+load netBundle {ACC1:mul#98.itm#1} 6 {ACC1:mul#98.itm#1(0)} {ACC1:mul#98.itm#1(1)} {ACC1:mul#98.itm#1(2)} {ACC1:mul#98.itm#1(3)} {ACC1:mul#98.itm#1(4)} {ACC1:mul#98.itm#1(5)} -attr xrf 17876 -attr oid 22 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm#1}
+load net {ACC1:acc#252.itm#1(0)} -attr vt d
+load net {ACC1:acc#252.itm#1(1)} -attr vt d
+load net {ACC1:acc#252.itm#1(2)} -attr vt d
+load net {ACC1:acc#252.itm#1(3)} -attr vt d
+load net {ACC1:acc#252.itm#1(4)} -attr vt d
+load net {ACC1:acc#252.itm#1(5)} -attr vt d
+load netBundle {ACC1:acc#252.itm#1} 6 {ACC1:acc#252.itm#1(0)} {ACC1:acc#252.itm#1(1)} {ACC1:acc#252.itm#1(2)} {ACC1:acc#252.itm#1(3)} {ACC1:acc#252.itm#1(4)} {ACC1:acc#252.itm#1(5)} -attr xrf 17877 -attr oid 23 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm#1}
+load net {ACC1:acc#251.itm#1(0)} -attr vt d
+load net {ACC1:acc#251.itm#1(1)} -attr vt d
+load net {ACC1:acc#251.itm#1(2)} -attr vt d
+load net {ACC1:acc#251.itm#1(3)} -attr vt d
+load net {ACC1:acc#251.itm#1(4)} -attr vt d
+load net {ACC1:acc#251.itm#1(5)} -attr vt d
+load netBundle {ACC1:acc#251.itm#1} 6 {ACC1:acc#251.itm#1(0)} {ACC1:acc#251.itm#1(1)} {ACC1:acc#251.itm#1(2)} {ACC1:acc#251.itm#1(3)} {ACC1:acc#251.itm#1(4)} {ACC1:acc#251.itm#1(5)} -attr xrf 17878 -attr oid 24 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm#1}
+load net {ACC1:acc#255.itm#1(0)} -attr vt d
+load net {ACC1:acc#255.itm#1(1)} -attr vt d
+load net {ACC1:acc#255.itm#1(2)} -attr vt d
+load net {ACC1:acc#255.itm#1(3)} -attr vt d
+load net {ACC1:acc#255.itm#1(4)} -attr vt d
+load net {ACC1:acc#255.itm#1(5)} -attr vt d
+load net {ACC1:acc#255.itm#1(6)} -attr vt d
+load netBundle {ACC1:acc#255.itm#1} 7 {ACC1:acc#255.itm#1(0)} {ACC1:acc#255.itm#1(1)} {ACC1:acc#255.itm#1(2)} {ACC1:acc#255.itm#1(3)} {ACC1:acc#255.itm#1(4)} {ACC1:acc#255.itm#1(5)} {ACC1:acc#255.itm#1(6)} -attr xrf 17879 -attr oid 25 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:mul#89.itm#1(0)} -attr vt d
+load net {ACC1:mul#89.itm#1(1)} -attr vt d
+load net {ACC1:mul#89.itm#1(2)} -attr vt d
+load net {ACC1:mul#89.itm#1(3)} -attr vt d
+load net {ACC1:mul#89.itm#1(4)} -attr vt d
+load net {ACC1:mul#89.itm#1(5)} -attr vt d
+load net {ACC1:mul#89.itm#1(6)} -attr vt d
+load net {ACC1:mul#89.itm#1(7)} -attr vt d
+load net {ACC1:mul#89.itm#1(8)} -attr vt d
+load net {ACC1:mul#89.itm#1(9)} -attr vt d
+load netBundle {ACC1:mul#89.itm#1} 10 {ACC1:mul#89.itm#1(0)} {ACC1:mul#89.itm#1(1)} {ACC1:mul#89.itm#1(2)} {ACC1:mul#89.itm#1(3)} {ACC1:mul#89.itm#1(4)} {ACC1:mul#89.itm#1(5)} {ACC1:mul#89.itm#1(6)} {ACC1:mul#89.itm#1(7)} {ACC1:mul#89.itm#1(8)} {ACC1:mul#89.itm#1(9)} -attr xrf 17880 -attr oid 26 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:acc#268.itm#1(0)} -attr vt d
+load net {ACC1:acc#268.itm#1(1)} -attr vt d
+load net {ACC1:acc#268.itm#1(2)} -attr vt d
+load net {ACC1:acc#268.itm#1(3)} -attr vt d
+load net {ACC1:acc#268.itm#1(4)} -attr vt d
+load net {ACC1:acc#268.itm#1(5)} -attr vt d
+load net {ACC1:acc#268.itm#1(6)} -attr vt d
+load net {ACC1:acc#268.itm#1(7)} -attr vt d
+load net {ACC1:acc#268.itm#1(8)} -attr vt d
+load net {ACC1:acc#268.itm#1(9)} -attr vt d
+load net {ACC1:acc#268.itm#1(10)} -attr vt d
+load net {ACC1:acc#268.itm#1(11)} -attr vt d
+load netBundle {ACC1:acc#268.itm#1} 12 {ACC1:acc#268.itm#1(0)} {ACC1:acc#268.itm#1(1)} {ACC1:acc#268.itm#1(2)} {ACC1:acc#268.itm#1(3)} {ACC1:acc#268.itm#1(4)} {ACC1:acc#268.itm#1(5)} {ACC1:acc#268.itm#1(6)} {ACC1:acc#268.itm#1(7)} {ACC1:acc#268.itm#1(8)} {ACC1:acc#268.itm#1(9)} {ACC1:acc#268.itm#1(10)} {ACC1:acc#268.itm#1(11)} -attr xrf 17881 -attr oid 27 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:mul#96.itm#1(0)} -attr vt d
+load net {ACC1:mul#96.itm#1(1)} -attr vt d
+load net {ACC1:mul#96.itm#1(2)} -attr vt d
+load net {ACC1:mul#96.itm#1(3)} -attr vt d
+load net {ACC1:mul#96.itm#1(4)} -attr vt d
+load net {ACC1:mul#96.itm#1(5)} -attr vt d
+load net {ACC1:mul#96.itm#1(6)} -attr vt d
+load net {ACC1:mul#96.itm#1(7)} -attr vt d
+load net {ACC1:mul#96.itm#1(8)} -attr vt d
+load net {ACC1:mul#96.itm#1(9)} -attr vt d
+load net {ACC1:mul#96.itm#1(10)} -attr vt d
+load net {ACC1:mul#96.itm#1(11)} -attr vt d
+load net {ACC1:mul#96.itm#1(12)} -attr vt d
+load net {ACC1:mul#96.itm#1(13)} -attr vt d
+load netBundle {ACC1:mul#96.itm#1} 14 {ACC1:mul#96.itm#1(0)} {ACC1:mul#96.itm#1(1)} {ACC1:mul#96.itm#1(2)} {ACC1:mul#96.itm#1(3)} {ACC1:mul#96.itm#1(4)} {ACC1:mul#96.itm#1(5)} {ACC1:mul#96.itm#1(6)} {ACC1:mul#96.itm#1(7)} {ACC1:mul#96.itm#1(8)} {ACC1:mul#96.itm#1(9)} {ACC1:mul#96.itm#1(10)} {ACC1:mul#96.itm#1(11)} {ACC1:mul#96.itm#1(12)} {ACC1:mul#96.itm#1(13)} -attr xrf 17882 -attr oid 28 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {FRAME:acc#12.itm#1(0)} -attr vt d
+load net {FRAME:acc#12.itm#1(1)} -attr vt d
+load net {FRAME:acc#12.itm#1(2)} -attr vt d
+load net {FRAME:acc#12.itm#1(3)} -attr vt d
+load net {FRAME:acc#12.itm#1(4)} -attr vt d
+load net {FRAME:acc#12.itm#1(5)} -attr vt d
+load netBundle {FRAME:acc#12.itm#1} 6 {FRAME:acc#12.itm#1(0)} {FRAME:acc#12.itm#1(1)} {FRAME:acc#12.itm#1(2)} {FRAME:acc#12.itm#1(3)} {FRAME:acc#12.itm#1(4)} {FRAME:acc#12.itm#1(5)} -attr xrf 17883 -attr oid 29 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm#1}
+load net {intensity:slc(intensity#2.sg1)#9.itm#1(0)} -attr vt d
+load net {intensity:slc(intensity#2.sg1)#9.itm#1(1)} -attr vt d
+load netBundle {intensity:slc(intensity#2.sg1)#9.itm#1} 2 {intensity:slc(intensity#2.sg1)#9.itm#1(0)} {intensity:slc(intensity#2.sg1)#9.itm#1(1)} -attr xrf 17884 -attr oid 30 -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1)#9.itm#1}
+load net {intensity:slc(intensity#2.sg1)#11.itm#1(0)} -attr vt d
+load net {intensity:slc(intensity#2.sg1)#11.itm#1(1)} -attr vt d
+load net {intensity:slc(intensity#2.sg1)#11.itm#1(2)} -attr vt d
+load netBundle {intensity:slc(intensity#2.sg1)#11.itm#1} 3 {intensity:slc(intensity#2.sg1)#11.itm#1(0)} {intensity:slc(intensity#2.sg1)#11.itm#1(1)} {intensity:slc(intensity#2.sg1)#11.itm#1(2)} -attr xrf 17885 -attr oid 31 -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1)#11.itm#1}
+load net {intensity:slc(intensity#2.sg1).itm#1(0)} -attr vt d
+load net {intensity:slc(intensity#2.sg1).itm#1(1)} -attr vt d
+load net {intensity:slc(intensity#2.sg1).itm#1(2)} -attr vt d
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+load net {FRAME:acc#5.psp.sva(0)} -attr vt d
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+load net {acc.imod#15.sva(0)} -attr vt d
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+load net {intensity#2.sg1.sva(0)} -attr vt d
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+load net {ACC1:acc#230.sdt(0)} -attr vt d
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+load net {mux.itm(0)} -attr vt d
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+load net {FRAME:conc#22.itm(0)} -attr vt d
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+load net {FRAME:or.itm(0)} -attr vt d
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+load net {conc#309.itm(0)} -attr vt d
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+load net {FRAME:or#3.itm(0)} -attr vt d
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+load net {conc#310.itm(0)} -attr vt d
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+load net {slc(FRAME:acc#5.psp.sva).itm(0)} -attr vt d
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+load net {slc(intensity#2.sg1.sva)#4.itm(0)} -attr vt d
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+load netBundle {slc(intensity#2.sg1.sva)#4.itm} 2 {slc(intensity#2.sg1.sva)#4.itm(0)} {slc(intensity#2.sg1.sva)#4.itm(1)} -attr xrf 17903 -attr oid 49 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#4.itm}
+load net {slc(intensity#2.sg1.sva)#3.itm(0)} -attr vt d
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+load net {slc(intensity#2.sg1.sva)#2.itm(0)} -attr vt d
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+load net {slc(intensity#2.sg1.sva)#2.itm(4)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#2.itm} 6 {slc(intensity#2.sg1.sva)#2.itm(0)} {slc(intensity#2.sg1.sva)#2.itm(1)} {slc(intensity#2.sg1.sva)#2.itm(2)} {slc(intensity#2.sg1.sva)#2.itm(3)} {slc(intensity#2.sg1.sva)#2.itm(4)} {slc(intensity#2.sg1.sva)#2.itm(5)} -attr xrf 17905 -attr oid 51 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {FRAME:acc#12.itm(0)} -attr vt d
+load net {FRAME:acc#12.itm(1)} -attr vt d
+load net {FRAME:acc#12.itm(2)} -attr vt d
+load net {FRAME:acc#12.itm(3)} -attr vt d
+load net {FRAME:acc#12.itm(4)} -attr vt d
+load net {FRAME:acc#12.itm(5)} -attr vt d
+load netBundle {FRAME:acc#12.itm} 6 {FRAME:acc#12.itm(0)} {FRAME:acc#12.itm(1)} {FRAME:acc#12.itm(2)} {FRAME:acc#12.itm(3)} {FRAME:acc#12.itm(4)} {FRAME:acc#12.itm(5)} -attr xrf 17906 -attr oid 52 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#11.itm(0)} -attr vt d
+load net {FRAME:acc#11.itm(1)} -attr vt d
+load net {FRAME:acc#11.itm(2)} -attr vt d
+load net {FRAME:acc#11.itm(3)} -attr vt d
+load net {FRAME:acc#11.itm(4)} -attr vt d
+load netBundle {FRAME:acc#11.itm} 5 {FRAME:acc#11.itm(0)} {FRAME:acc#11.itm(1)} {FRAME:acc#11.itm(2)} {FRAME:acc#11.itm(3)} {FRAME:acc#11.itm(4)} -attr xrf 17907 -attr oid 53 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#9.itm(0)} -attr vt d
+load net {FRAME:acc#9.itm(1)} -attr vt d
+load net {FRAME:acc#9.itm(2)} -attr vt d
+load net {FRAME:acc#9.itm(3)} -attr vt d
+load netBundle {FRAME:acc#9.itm} 4 {FRAME:acc#9.itm(0)} {FRAME:acc#9.itm(1)} {FRAME:acc#9.itm(2)} {FRAME:acc#9.itm(3)} -attr xrf 17908 -attr oid 54 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {slc(intensity#2.sg1.sva)#8.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#8.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#8.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#8.itm} 3 {slc(intensity#2.sg1.sva)#8.itm(0)} {slc(intensity#2.sg1.sva)#8.itm(1)} {slc(intensity#2.sg1.sva)#8.itm(2)} -attr xrf 17909 -attr oid 55 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#8.itm}
+load net {FRAME:not#26.itm(0)} -attr vt d
+load net {FRAME:not#26.itm(1)} -attr vt d
+load net {FRAME:not#26.itm(2)} -attr vt d
+load netBundle {FRAME:not#26.itm} 3 {FRAME:not#26.itm(0)} {FRAME:not#26.itm(1)} {FRAME:not#26.itm(2)} -attr xrf 17910 -attr oid 56 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#26.itm}
+load net {slc(intensity#2.sg1.sva)#9.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#9.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#9.itm} 3 {slc(intensity#2.sg1.sva)#9.itm(0)} {slc(intensity#2.sg1.sva)#9.itm(1)} {slc(intensity#2.sg1.sva)#9.itm(2)} -attr xrf 17911 -attr oid 57 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#9.itm}
+load net {FRAME:acc#8.itm(0)} -attr vt d
+load net {FRAME:acc#8.itm(1)} -attr vt d
+load net {FRAME:acc#8.itm(2)} -attr vt d
+load net {FRAME:acc#8.itm(3)} -attr vt d
+load netBundle {FRAME:acc#8.itm} 4 {FRAME:acc#8.itm(0)} {FRAME:acc#8.itm(1)} {FRAME:acc#8.itm(2)} {FRAME:acc#8.itm(3)} -attr xrf 17912 -attr oid 58 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {conc#311.itm(0)} -attr vt d
+load net {conc#311.itm(1)} -attr vt d
+load net {conc#311.itm(2)} -attr vt d
+load netBundle {conc#311.itm} 3 {conc#311.itm(0)} {conc#311.itm(1)} {conc#311.itm(2)} -attr xrf 17913 -attr oid 59 -attr vt d -attr @path {/sobel/sobel:core/conc#311.itm}
+load net {slc(intensity#2.sg1.sva)#10.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#10.itm(1)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#10.itm} 2 {slc(intensity#2.sg1.sva)#10.itm(0)} {slc(intensity#2.sg1.sva)#10.itm(1)} -attr xrf 17914 -attr oid 60 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#10.itm}
+load net {FRAME:acc#10.itm(0)} -attr vt d
+load net {FRAME:acc#10.itm(1)} -attr vt d
+load net {FRAME:acc#10.itm(2)} -attr vt d
+load net {FRAME:acc#10.itm(3)} -attr vt d
+load netBundle {FRAME:acc#10.itm} 4 {FRAME:acc#10.itm(0)} {FRAME:acc#10.itm(1)} {FRAME:acc#10.itm(2)} {FRAME:acc#10.itm(3)} -attr xrf 17915 -attr oid 61 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {slc(intensity#2.sg1.sva)#5.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#5.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#5.itm} 3 {slc(intensity#2.sg1.sva)#5.itm(0)} {slc(intensity#2.sg1.sva)#5.itm(1)} {slc(intensity#2.sg1.sva)#5.itm(2)} -attr xrf 17916 -attr oid 62 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#5.itm}
+load net {FRAME:not#25.itm(0)} -attr vt d
+load net {FRAME:not#25.itm(1)} -attr vt d
+load net {FRAME:not#25.itm(2)} -attr vt d
+load netBundle {FRAME:not#25.itm} 3 {FRAME:not#25.itm(0)} {FRAME:not#25.itm(1)} {FRAME:not#25.itm(2)} -attr xrf 17917 -attr oid 63 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {slc(intensity#2.sg1.sva)#6.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#6.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#6.itm} 3 {slc(intensity#2.sg1.sva)#6.itm(0)} {slc(intensity#2.sg1.sva)#6.itm(1)} {slc(intensity#2.sg1.sva)#6.itm(2)} -attr xrf 17918 -attr oid 64 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#6.itm}
+load net {ACC1:acc#281.itm(0)} -attr vt d
+load net {ACC1:acc#281.itm(1)} -attr vt d
+load net {ACC1:acc#281.itm(2)} -attr vt d
+load net {ACC1:acc#281.itm(3)} -attr vt d
+load net {ACC1:acc#281.itm(4)} -attr vt d
+load net {ACC1:acc#281.itm(5)} -attr vt d
+load net {ACC1:acc#281.itm(6)} -attr vt d
+load net {ACC1:acc#281.itm(7)} -attr vt d
+load net {ACC1:acc#281.itm(8)} -attr vt d
+load net {ACC1:acc#281.itm(9)} -attr vt d
+load net {ACC1:acc#281.itm(10)} -attr vt d
+load net {ACC1:acc#281.itm(11)} -attr vt d
+load net {ACC1:acc#281.itm(12)} -attr vt d
+load net {ACC1:acc#281.itm(13)} -attr vt d
+load net {ACC1:acc#281.itm(14)} -attr vt d
+load net {ACC1:acc#281.itm(15)} -attr vt d
+load netBundle {ACC1:acc#281.itm} 16 {ACC1:acc#281.itm(0)} {ACC1:acc#281.itm(1)} {ACC1:acc#281.itm(2)} {ACC1:acc#281.itm(3)} {ACC1:acc#281.itm(4)} {ACC1:acc#281.itm(5)} {ACC1:acc#281.itm(6)} {ACC1:acc#281.itm(7)} {ACC1:acc#281.itm(8)} {ACC1:acc#281.itm(9)} {ACC1:acc#281.itm(10)} {ACC1:acc#281.itm(11)} {ACC1:acc#281.itm(12)} {ACC1:acc#281.itm(13)} {ACC1:acc#281.itm(14)} {ACC1:acc#281.itm(15)} -attr xrf 17919 -attr oid 65 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#279.itm(0)} -attr vt d
+load net {ACC1:acc#279.itm(1)} -attr vt d
+load net {ACC1:acc#279.itm(2)} -attr vt d
+load net {ACC1:acc#279.itm(3)} -attr vt d
+load net {ACC1:acc#279.itm(4)} -attr vt d
+load net {ACC1:acc#279.itm(5)} -attr vt d
+load net {ACC1:acc#279.itm(6)} -attr vt d
+load net {ACC1:acc#279.itm(7)} -attr vt d
+load net {ACC1:acc#279.itm(8)} -attr vt d
+load net {ACC1:acc#279.itm(9)} -attr vt d
+load net {ACC1:acc#279.itm(10)} -attr vt d
+load net {ACC1:acc#279.itm(11)} -attr vt d
+load net {ACC1:acc#279.itm(12)} -attr vt d
+load net {ACC1:acc#279.itm(13)} -attr vt d
+load net {ACC1:acc#279.itm(14)} -attr vt d
+load net {ACC1:acc#279.itm(15)} -attr vt d
+load netBundle {ACC1:acc#279.itm} 16 {ACC1:acc#279.itm(0)} {ACC1:acc#279.itm(1)} {ACC1:acc#279.itm(2)} {ACC1:acc#279.itm(3)} {ACC1:acc#279.itm(4)} {ACC1:acc#279.itm(5)} {ACC1:acc#279.itm(6)} {ACC1:acc#279.itm(7)} {ACC1:acc#279.itm(8)} {ACC1:acc#279.itm(9)} {ACC1:acc#279.itm(10)} {ACC1:acc#279.itm(11)} {ACC1:acc#279.itm(12)} {ACC1:acc#279.itm(13)} {ACC1:acc#279.itm(14)} {ACC1:acc#279.itm(15)} -attr xrf 17920 -attr oid 66 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#275.itm(0)} -attr vt d
+load net {ACC1:acc#275.itm(1)} -attr vt d
+load net {ACC1:acc#275.itm(2)} -attr vt d
+load net {ACC1:acc#275.itm(3)} -attr vt d
+load net {ACC1:acc#275.itm(4)} -attr vt d
+load net {ACC1:acc#275.itm(5)} -attr vt d
+load net {ACC1:acc#275.itm(6)} -attr vt d
+load net {ACC1:acc#275.itm(7)} -attr vt d
+load net {ACC1:acc#275.itm(8)} -attr vt d
+load net {ACC1:acc#275.itm(9)} -attr vt d
+load net {ACC1:acc#275.itm(10)} -attr vt d
+load net {ACC1:acc#275.itm(11)} -attr vt d
+load net {ACC1:acc#275.itm(12)} -attr vt d
+load net {ACC1:acc#275.itm(13)} -attr vt d
+load net {ACC1:acc#275.itm(14)} -attr vt d
+load net {ACC1:acc#275.itm(15)} -attr vt d
+load netBundle {ACC1:acc#275.itm} 16 {ACC1:acc#275.itm(0)} {ACC1:acc#275.itm(1)} {ACC1:acc#275.itm(2)} {ACC1:acc#275.itm(3)} {ACC1:acc#275.itm(4)} {ACC1:acc#275.itm(5)} {ACC1:acc#275.itm(6)} {ACC1:acc#275.itm(7)} {ACC1:acc#275.itm(8)} {ACC1:acc#275.itm(9)} {ACC1:acc#275.itm(10)} {ACC1:acc#275.itm(11)} {ACC1:acc#275.itm(12)} {ACC1:acc#275.itm(13)} {ACC1:acc#275.itm(14)} {ACC1:acc#275.itm(15)} -attr xrf 17921 -attr oid 67 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:conc#277.itm(0)} -attr vt d
+load net {ACC1:conc#277.itm(1)} -attr vt d
+load net {ACC1:conc#277.itm(2)} -attr vt d
+load net {ACC1:conc#277.itm(3)} -attr vt d
+load net {ACC1:conc#277.itm(4)} -attr vt d
+load net {ACC1:conc#277.itm(5)} -attr vt d
+load net {ACC1:conc#277.itm(6)} -attr vt d
+load net {ACC1:conc#277.itm(7)} -attr vt d
+load net {ACC1:conc#277.itm(8)} -attr vt d
+load net {ACC1:conc#277.itm(9)} -attr vt d
+load net {ACC1:conc#277.itm(10)} -attr vt d
+load net {ACC1:conc#277.itm(11)} -attr vt d
+load net {ACC1:conc#277.itm(12)} -attr vt d
+load net {ACC1:conc#277.itm(13)} -attr vt d
+load net {ACC1:conc#277.itm(14)} -attr vt d
+load netBundle {ACC1:conc#277.itm} 15 {ACC1:conc#277.itm(0)} {ACC1:conc#277.itm(1)} {ACC1:conc#277.itm(2)} {ACC1:conc#277.itm(3)} {ACC1:conc#277.itm(4)} {ACC1:conc#277.itm(5)} {ACC1:conc#277.itm(6)} {ACC1:conc#277.itm(7)} {ACC1:conc#277.itm(8)} {ACC1:conc#277.itm(9)} {ACC1:conc#277.itm(10)} {ACC1:conc#277.itm(11)} {ACC1:conc#277.itm(12)} {ACC1:conc#277.itm(13)} {ACC1:conc#277.itm(14)} -attr xrf 17922 -attr oid 68 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:mul#101.itm(0)} -attr vt d
+load net {ACC1:mul#101.itm(1)} -attr vt d
+load net {ACC1:mul#101.itm(2)} -attr vt d
+load net {ACC1:mul#101.itm(3)} -attr vt d
+load net {ACC1:mul#101.itm(4)} -attr vt d
+load net {ACC1:mul#101.itm(5)} -attr vt d
+load net {ACC1:mul#101.itm(6)} -attr vt d
+load net {ACC1:mul#101.itm(7)} -attr vt d
+load net {ACC1:mul#101.itm(8)} -attr vt d
+load net {ACC1:mul#101.itm(9)} -attr vt d
+load net {ACC1:mul#101.itm(10)} -attr vt d
+load net {ACC1:mul#101.itm(11)} -attr vt d
+load netBundle {ACC1:mul#101.itm} 12 {ACC1:mul#101.itm(0)} {ACC1:mul#101.itm(1)} {ACC1:mul#101.itm(2)} {ACC1:mul#101.itm(3)} {ACC1:mul#101.itm(4)} {ACC1:mul#101.itm(5)} {ACC1:mul#101.itm(6)} {ACC1:mul#101.itm(7)} {ACC1:mul#101.itm(8)} {ACC1:mul#101.itm(9)} {ACC1:mul#101.itm(10)} {ACC1:mul#101.itm(11)} -attr xrf 17923 -attr oid 69 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101.itm}
+load net {ACC1:acc#144.itm(0)} -attr vt d
+load net {ACC1:acc#144.itm(1)} -attr vt d
+load netBundle {ACC1:acc#144.itm} 2 {ACC1:acc#144.itm(0)} {ACC1:acc#144.itm(1)} -attr xrf 17924 -attr oid 70 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144.itm}
+load net {ACC1-3:exs#6.itm(0)} -attr vt d
+load net {ACC1-3:exs#6.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#6.itm} 2 {ACC1-3:exs#6.itm(0)} {ACC1-3:exs#6.itm(1)} -attr xrf 17925 -attr oid 71 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#6.itm}
+load net {ACC1:acc#272.itm(0)} -attr vt d
+load net {ACC1:acc#272.itm(1)} -attr vt d
+load net {ACC1:acc#272.itm(2)} -attr vt d
+load net {ACC1:acc#272.itm(3)} -attr vt d
+load net {ACC1:acc#272.itm(4)} -attr vt d
+load net {ACC1:acc#272.itm(5)} -attr vt d
+load net {ACC1:acc#272.itm(6)} -attr vt d
+load net {ACC1:acc#272.itm(7)} -attr vt d
+load net {ACC1:acc#272.itm(8)} -attr vt d
+load net {ACC1:acc#272.itm(9)} -attr vt d
+load net {ACC1:acc#272.itm(10)} -attr vt d
+load net {ACC1:acc#272.itm(11)} -attr vt d
+load net {ACC1:acc#272.itm(12)} -attr vt d
+load net {ACC1:acc#272.itm(13)} -attr vt d
+load netBundle {ACC1:acc#272.itm} 14 {ACC1:acc#272.itm(0)} {ACC1:acc#272.itm(1)} {ACC1:acc#272.itm(2)} {ACC1:acc#272.itm(3)} {ACC1:acc#272.itm(4)} {ACC1:acc#272.itm(5)} {ACC1:acc#272.itm(6)} {ACC1:acc#272.itm(7)} {ACC1:acc#272.itm(8)} {ACC1:acc#272.itm(9)} {ACC1:acc#272.itm(10)} {ACC1:acc#272.itm(11)} {ACC1:acc#272.itm(12)} {ACC1:acc#272.itm(13)} -attr xrf 17926 -attr oid 72 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:conc#253.itm(0)} -attr vt d
+load net {ACC1:conc#253.itm(1)} -attr vt d
+load net {ACC1:conc#253.itm(2)} -attr vt d
+load net {ACC1:conc#253.itm(3)} -attr vt d
+load net {ACC1:conc#253.itm(4)} -attr vt d
+load net {ACC1:conc#253.itm(5)} -attr vt d
+load net {ACC1:conc#253.itm(6)} -attr vt d
+load net {ACC1:conc#253.itm(7)} -attr vt d
+load net {ACC1:conc#253.itm(8)} -attr vt d
+load net {ACC1:conc#253.itm(9)} -attr vt d
+load net {ACC1:conc#253.itm(10)} -attr vt d
+load net {ACC1:conc#253.itm(11)} -attr vt d
+load net {ACC1:conc#253.itm(12)} -attr vt d
+load netBundle {ACC1:conc#253.itm} 13 {ACC1:conc#253.itm(0)} {ACC1:conc#253.itm(1)} {ACC1:conc#253.itm(2)} {ACC1:conc#253.itm(3)} {ACC1:conc#253.itm(4)} {ACC1:conc#253.itm(5)} {ACC1:conc#253.itm(6)} {ACC1:conc#253.itm(7)} {ACC1:conc#253.itm(8)} {ACC1:conc#253.itm(9)} {ACC1:conc#253.itm(10)} {ACC1:conc#253.itm(11)} {ACC1:conc#253.itm(12)} -attr xrf 17927 -attr oid 73 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {ACC1:mul#95.itm(0)} -attr vt d
+load net {ACC1:mul#95.itm(1)} -attr vt d
+load net {ACC1:mul#95.itm(2)} -attr vt d
+load net {ACC1:mul#95.itm(3)} -attr vt d
+load net {ACC1:mul#95.itm(4)} -attr vt d
+load net {ACC1:mul#95.itm(5)} -attr vt d
+load net {ACC1:mul#95.itm(6)} -attr vt d
+load net {ACC1:mul#95.itm(7)} -attr vt d
+load net {ACC1:mul#95.itm(8)} -attr vt d
+load net {ACC1:mul#95.itm(9)} -attr vt d
+load net {ACC1:mul#95.itm(10)} -attr vt d
+load net {ACC1:mul#95.itm(11)} -attr vt d
+load netBundle {ACC1:mul#95.itm} 12 {ACC1:mul#95.itm(0)} {ACC1:mul#95.itm(1)} {ACC1:mul#95.itm(2)} {ACC1:mul#95.itm(3)} {ACC1:mul#95.itm(4)} {ACC1:mul#95.itm(5)} {ACC1:mul#95.itm(6)} {ACC1:mul#95.itm(7)} {ACC1:mul#95.itm(8)} {ACC1:mul#95.itm(9)} {ACC1:mul#95.itm(10)} {ACC1:mul#95.itm(11)} -attr xrf 17928 -attr oid 74 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95.itm}
+load net {ACC1:acc#138.itm(0)} -attr vt d
+load net {ACC1:acc#138.itm(1)} -attr vt d
+load netBundle {ACC1:acc#138.itm} 2 {ACC1:acc#138.itm(0)} {ACC1:acc#138.itm(1)} -attr xrf 17929 -attr oid 75 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {ACC1:conc#276.itm(0)} -attr vt d
+load net {ACC1:conc#276.itm(1)} -attr vt d
+load net {ACC1:conc#276.itm(2)} -attr vt d
+load net {ACC1:conc#276.itm(3)} -attr vt d
+load net {ACC1:conc#276.itm(4)} -attr vt d
+load net {ACC1:conc#276.itm(5)} -attr vt d
+load net {ACC1:conc#276.itm(6)} -attr vt d
+load net {ACC1:conc#276.itm(7)} -attr vt d
+load net {ACC1:conc#276.itm(8)} -attr vt d
+load net {ACC1:conc#276.itm(9)} -attr vt d
+load net {ACC1:conc#276.itm(10)} -attr vt d
+load net {ACC1:conc#276.itm(11)} -attr vt d
+load net {ACC1:conc#276.itm(12)} -attr vt d
+load netBundle {ACC1:conc#276.itm} 13 {ACC1:conc#276.itm(0)} {ACC1:conc#276.itm(1)} {ACC1:conc#276.itm(2)} {ACC1:conc#276.itm(3)} {ACC1:conc#276.itm(4)} {ACC1:conc#276.itm(5)} {ACC1:conc#276.itm(6)} {ACC1:conc#276.itm(7)} {ACC1:conc#276.itm(8)} {ACC1:conc#276.itm(9)} {ACC1:conc#276.itm(10)} {ACC1:conc#276.itm(11)} {ACC1:conc#276.itm(12)} -attr xrf 17930 -attr oid 76 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {ACC1:mul#100.itm(0)} -attr vt d
+load net {ACC1:mul#100.itm(1)} -attr vt d
+load net {ACC1:mul#100.itm(2)} -attr vt d
+load net {ACC1:mul#100.itm(3)} -attr vt d
+load net {ACC1:mul#100.itm(4)} -attr vt d
+load net {ACC1:mul#100.itm(5)} -attr vt d
+load net {ACC1:mul#100.itm(6)} -attr vt d
+load net {ACC1:mul#100.itm(7)} -attr vt d
+load net {ACC1:mul#100.itm(8)} -attr vt d
+load net {ACC1:mul#100.itm(9)} -attr vt d
+load netBundle {ACC1:mul#100.itm} 10 {ACC1:mul#100.itm(0)} {ACC1:mul#100.itm(1)} {ACC1:mul#100.itm(2)} {ACC1:mul#100.itm(3)} {ACC1:mul#100.itm(4)} {ACC1:mul#100.itm(5)} {ACC1:mul#100.itm(6)} {ACC1:mul#100.itm(7)} {ACC1:mul#100.itm(8)} {ACC1:mul#100.itm(9)} -attr xrf 17931 -attr oid 77 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#100.itm}
+load net {ACC1:acc#143.itm(0)} -attr vt d
+load net {ACC1:acc#143.itm(1)} -attr vt d
+load netBundle {ACC1:acc#143.itm} 2 {ACC1:acc#143.itm(0)} {ACC1:acc#143.itm(1)} -attr xrf 17932 -attr oid 78 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1-2:exs.itm(0)} -attr vt d
+load net {ACC1-2:exs.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs.itm} 2 {ACC1-2:exs.itm(0)} {ACC1-2:exs.itm(1)} -attr xrf 17933 -attr oid 79 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs.itm}
+load net {ACC1:conc#255.itm(0)} -attr vt d
+load net {ACC1:conc#255.itm(1)} -attr vt d
+load net {ACC1:conc#255.itm(2)} -attr vt d
+load net {ACC1:conc#255.itm(3)} -attr vt d
+load net {ACC1:conc#255.itm(4)} -attr vt d
+load net {ACC1:conc#255.itm(5)} -attr vt d
+load net {ACC1:conc#255.itm(6)} -attr vt d
+load net {ACC1:conc#255.itm(7)} -attr vt d
+load net {ACC1:conc#255.itm(8)} -attr vt d
+load net {ACC1:conc#255.itm(9)} -attr vt d
+load net {ACC1:conc#255.itm(10)} -attr vt d
+load net {ACC1:conc#255.itm(11)} -attr vt d
+load net {ACC1:conc#255.itm(12)} -attr vt d
+load net {ACC1:conc#255.itm(13)} -attr vt d
+load net {ACC1:conc#255.itm(14)} -attr vt d
+load net {ACC1:conc#255.itm(15)} -attr vt d
+load netBundle {ACC1:conc#255.itm} 16 {ACC1:conc#255.itm(0)} {ACC1:conc#255.itm(1)} {ACC1:conc#255.itm(2)} {ACC1:conc#255.itm(3)} {ACC1:conc#255.itm(4)} {ACC1:conc#255.itm(5)} {ACC1:conc#255.itm(6)} {ACC1:conc#255.itm(7)} {ACC1:conc#255.itm(8)} {ACC1:conc#255.itm(9)} {ACC1:conc#255.itm(10)} {ACC1:conc#255.itm(11)} {ACC1:conc#255.itm(12)} {ACC1:conc#255.itm(13)} {ACC1:conc#255.itm(14)} {ACC1:conc#255.itm(15)} -attr xrf 17934 -attr oid 80 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(0)} -attr vt d
+load net {ACC1:mul#97.itm(1)} -attr vt d
+load net {ACC1:mul#97.itm(2)} -attr vt d
+load net {ACC1:mul#97.itm(3)} -attr vt d
+load net {ACC1:mul#97.itm(4)} -attr vt d
+load net {ACC1:mul#97.itm(5)} -attr vt d
+load net {ACC1:mul#97.itm(6)} -attr vt d
+load net {ACC1:mul#97.itm(7)} -attr vt d
+load net {ACC1:mul#97.itm(8)} -attr vt d
+load net {ACC1:mul#97.itm(9)} -attr vt d
+load net {ACC1:mul#97.itm(10)} -attr vt d
+load net {ACC1:mul#97.itm(11)} -attr vt d
+load net {ACC1:mul#97.itm(12)} -attr vt d
+load net {ACC1:mul#97.itm(13)} -attr vt d
+load net {ACC1:mul#97.itm(14)} -attr vt d
+load netBundle {ACC1:mul#97.itm} 15 {ACC1:mul#97.itm(0)} {ACC1:mul#97.itm(1)} {ACC1:mul#97.itm(2)} {ACC1:mul#97.itm(3)} {ACC1:mul#97.itm(4)} {ACC1:mul#97.itm(5)} {ACC1:mul#97.itm(6)} {ACC1:mul#97.itm(7)} {ACC1:mul#97.itm(8)} {ACC1:mul#97.itm(9)} {ACC1:mul#97.itm(10)} {ACC1:mul#97.itm(11)} {ACC1:mul#97.itm(12)} {ACC1:mul#97.itm(13)} {ACC1:mul#97.itm(14)} -attr xrf 17935 -attr oid 81 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:acc#140.itm(0)} -attr vt d
+load net {ACC1:acc#140.itm(1)} -attr vt d
+load netBundle {ACC1:acc#140.itm} 2 {ACC1:acc#140.itm(0)} {ACC1:acc#140.itm(1)} -attr xrf 17936 -attr oid 82 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load net {ACC1:acc#278.itm(0)} -attr vt d
+load net {ACC1:acc#278.itm(1)} -attr vt d
+load net {ACC1:acc#278.itm(2)} -attr vt d
+load net {ACC1:acc#278.itm(3)} -attr vt d
+load net {ACC1:acc#278.itm(4)} -attr vt d
+load net {ACC1:acc#278.itm(5)} -attr vt d
+load net {ACC1:acc#278.itm(6)} -attr vt d
+load net {ACC1:acc#278.itm(7)} -attr vt d
+load net {ACC1:acc#278.itm(8)} -attr vt d
+load net {ACC1:acc#278.itm(9)} -attr vt d
+load net {ACC1:acc#278.itm(10)} -attr vt d
+load net {ACC1:acc#278.itm(11)} -attr vt d
+load net {ACC1:acc#278.itm(12)} -attr vt d
+load net {ACC1:acc#278.itm(13)} -attr vt d
+load net {ACC1:acc#278.itm(14)} -attr vt d
+load net {ACC1:acc#278.itm(15)} -attr vt d
+load netBundle {ACC1:acc#278.itm} 16 {ACC1:acc#278.itm(0)} {ACC1:acc#278.itm(1)} {ACC1:acc#278.itm(2)} {ACC1:acc#278.itm(3)} {ACC1:acc#278.itm(4)} {ACC1:acc#278.itm(5)} {ACC1:acc#278.itm(6)} {ACC1:acc#278.itm(7)} {ACC1:acc#278.itm(8)} {ACC1:acc#278.itm(9)} {ACC1:acc#278.itm(10)} {ACC1:acc#278.itm(11)} {ACC1:acc#278.itm(12)} {ACC1:acc#278.itm(13)} {ACC1:acc#278.itm(14)} {ACC1:acc#278.itm(15)} -attr xrf 17937 -attr oid 83 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {conc#312.itm(0)} -attr vt d
+load net {conc#312.itm(1)} -attr vt d
+load net {conc#312.itm(2)} -attr vt d
+load net {conc#312.itm(3)} -attr vt d
+load net {conc#312.itm(4)} -attr vt d
+load net {conc#312.itm(5)} -attr vt d
+load net {conc#312.itm(6)} -attr vt d
+load net {conc#312.itm(7)} -attr vt d
+load net {conc#312.itm(8)} -attr vt d
+load net {conc#312.itm(9)} -attr vt d
+load net {conc#312.itm(10)} -attr vt d
+load net {conc#312.itm(11)} -attr vt d
+load net {conc#312.itm(12)} -attr vt d
+load net {conc#312.itm(13)} -attr vt d
+load net {conc#312.itm(14)} -attr vt d
+load net {conc#312.itm(15)} -attr vt d
+load netBundle {conc#312.itm} 16 {conc#312.itm(0)} {conc#312.itm(1)} {conc#312.itm(2)} {conc#312.itm(3)} {conc#312.itm(4)} {conc#312.itm(5)} {conc#312.itm(6)} {conc#312.itm(7)} {conc#312.itm(8)} {conc#312.itm(9)} {conc#312.itm(10)} {conc#312.itm(11)} {conc#312.itm(12)} {conc#312.itm(13)} {conc#312.itm(14)} {conc#312.itm(15)} -attr xrf 17938 -attr oid 84 -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {ACC1:mul#105.itm(0)} -attr vt d
+load net {ACC1:mul#105.itm(1)} -attr vt d
+load net {ACC1:mul#105.itm(2)} -attr vt d
+load net {ACC1:mul#105.itm(3)} -attr vt d
+load net {ACC1:mul#105.itm(4)} -attr vt d
+load net {ACC1:mul#105.itm(5)} -attr vt d
+load net {ACC1:mul#105.itm(6)} -attr vt d
+load net {ACC1:mul#105.itm(7)} -attr vt d
+load net {ACC1:mul#105.itm(8)} -attr vt d
+load net {ACC1:mul#105.itm(9)} -attr vt d
+load net {ACC1:mul#105.itm(10)} -attr vt d
+load net {ACC1:mul#105.itm(11)} -attr vt d
+load netBundle {ACC1:mul#105.itm} 12 {ACC1:mul#105.itm(0)} {ACC1:mul#105.itm(1)} {ACC1:mul#105.itm(2)} {ACC1:mul#105.itm(3)} {ACC1:mul#105.itm(4)} {ACC1:mul#105.itm(5)} {ACC1:mul#105.itm(6)} {ACC1:mul#105.itm(7)} {ACC1:mul#105.itm(8)} {ACC1:mul#105.itm(9)} {ACC1:mul#105.itm(10)} {ACC1:mul#105.itm(11)} -attr xrf 17939 -attr oid 85 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105.itm}
+load net {ACC1:acc#148.itm(0)} -attr vt d
+load net {ACC1:acc#148.itm(1)} -attr vt d
+load net {ACC1:acc#148.itm(2)} -attr vt d
+load netBundle {ACC1:acc#148.itm} 3 {ACC1:acc#148.itm(0)} {ACC1:acc#148.itm(1)} {ACC1:acc#148.itm(2)} -attr xrf 17940 -attr oid 86 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {ACC1:acc#149.itm(0)} -attr vt d
+load net {ACC1:acc#149.itm(1)} -attr vt d
+load netBundle {ACC1:acc#149.itm} 2 {ACC1:acc#149.itm(0)} {ACC1:acc#149.itm(1)} -attr xrf 17941 -attr oid 87 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149.itm}
+load net {ACC1:acc#150.itm(0)} -attr vt d
+load net {ACC1:acc#150.itm(1)} -attr vt d
+load netBundle {ACC1:acc#150.itm} 2 {ACC1:acc#150.itm(0)} {ACC1:acc#150.itm(1)} -attr xrf 17942 -attr oid 88 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load net {ACC1-2:exs#21.itm(0)} -attr vt d
+load net {ACC1-2:exs#21.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#21.itm} 2 {ACC1-2:exs#21.itm(0)} {ACC1-2:exs#21.itm(1)} -attr xrf 17943 -attr oid 89 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#21.itm}
+load net {mul.itm(0)} -attr vt d
+load net {mul.itm(1)} -attr vt d
+load net {mul.itm(2)} -attr vt d
+load net {mul.itm(3)} -attr vt d
+load net {mul.itm(4)} -attr vt d
+load net {mul.itm(5)} -attr vt d
+load net {mul.itm(6)} -attr vt d
+load net {mul.itm(7)} -attr vt d
+load net {mul.itm(8)} -attr vt d
+load net {mul.itm(9)} -attr vt d
+load net {mul.itm(10)} -attr vt d
+load net {mul.itm(11)} -attr vt d
+load net {mul.itm(12)} -attr vt d
+load net {mul.itm(13)} -attr vt d
+load net {mul.itm(14)} -attr vt d
+load net {mul.itm(15)} -attr vt d
+load netBundle {mul.itm} 16 {mul.itm(0)} {mul.itm(1)} {mul.itm(2)} {mul.itm(3)} {mul.itm(4)} {mul.itm(5)} {mul.itm(6)} {mul.itm(7)} {mul.itm(8)} {mul.itm(9)} {mul.itm(10)} {mul.itm(11)} {mul.itm(12)} {mul.itm(13)} {mul.itm(14)} {mul.itm(15)} -attr xrf 17944 -attr oid 90 -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {ACC1:acc#151.itm(0)} -attr vt d
+load net {ACC1:acc#151.itm(1)} -attr vt d
+load netBundle {ACC1:acc#151.itm} 2 {ACC1:acc#151.itm(0)} {ACC1:acc#151.itm(1)} -attr xrf 17945 -attr oid 91 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151.itm}
+load net {mul#1.itm(0)} -attr vt d
+load net {mul#1.itm(1)} -attr vt d
+load net {mul#1.itm(2)} -attr vt d
+load net {mul#1.itm(3)} -attr vt d
+load net {mul#1.itm(4)} -attr vt d
+load net {mul#1.itm(5)} -attr vt d
+load net {mul#1.itm(6)} -attr vt d
+load net {mul#1.itm(7)} -attr vt d
+load net {mul#1.itm(8)} -attr vt d
+load net {mul#1.itm(9)} -attr vt d
+load net {mul#1.itm(10)} -attr vt d
+load net {mul#1.itm(11)} -attr vt d
+load net {mul#1.itm(12)} -attr vt d
+load netBundle {mul#1.itm} 13 {mul#1.itm(0)} {mul#1.itm(1)} {mul#1.itm(2)} {mul#1.itm(3)} {mul#1.itm(4)} {mul#1.itm(5)} {mul#1.itm(6)} {mul#1.itm(7)} {mul#1.itm(8)} {mul#1.itm(9)} {mul#1.itm(10)} {mul#1.itm(11)} {mul#1.itm(12)} -attr xrf 17946 -attr oid 92 -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {ACC1:acc#152.itm(0)} -attr vt d
+load net {ACC1:acc#152.itm(1)} -attr vt d
+load netBundle {ACC1:acc#152.itm} 2 {ACC1:acc#152.itm(0)} {ACC1:acc#152.itm(1)} -attr xrf 17947 -attr oid 93 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:mul#99.itm(0)} -attr vt d
+load net {ACC1:mul#99.itm(1)} -attr vt d
+load net {ACC1:mul#99.itm(2)} -attr vt d
+load net {ACC1:mul#99.itm(3)} -attr vt d
+load net {ACC1:mul#99.itm(4)} -attr vt d
+load net {ACC1:mul#99.itm(5)} -attr vt d
+load net {ACC1:mul#99.itm(6)} -attr vt d
+load net {ACC1:mul#99.itm(7)} -attr vt d
+load netBundle {ACC1:mul#99.itm} 8 {ACC1:mul#99.itm(0)} {ACC1:mul#99.itm(1)} {ACC1:mul#99.itm(2)} {ACC1:mul#99.itm(3)} {ACC1:mul#99.itm(4)} {ACC1:mul#99.itm(5)} {ACC1:mul#99.itm(6)} {ACC1:mul#99.itm(7)} -attr xrf 17948 -attr oid 94 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:acc#142.itm(0)} -attr vt d
+load net {ACC1:acc#142.itm(1)} -attr vt d
+load netBundle {ACC1:acc#142.itm} 2 {ACC1:acc#142.itm(0)} {ACC1:acc#142.itm(1)} -attr xrf 17949 -attr oid 95 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#264.itm(0)} -attr vt d
+load net {ACC1:acc#264.itm(1)} -attr vt d
+load net {ACC1:acc#264.itm(2)} -attr vt d
+load net {ACC1:acc#264.itm(3)} -attr vt d
+load net {ACC1:acc#264.itm(4)} -attr vt d
+load net {ACC1:acc#264.itm(5)} -attr vt d
+load net {ACC1:acc#264.itm(6)} -attr vt d
+load net {ACC1:acc#264.itm(7)} -attr vt d
+load net {ACC1:acc#264.itm(8)} -attr vt d
+load net {ACC1:acc#264.itm(9)} -attr vt d
+load netBundle {ACC1:acc#264.itm} 10 {ACC1:acc#264.itm(0)} {ACC1:acc#264.itm(1)} {ACC1:acc#264.itm(2)} {ACC1:acc#264.itm(3)} {ACC1:acc#264.itm(4)} {ACC1:acc#264.itm(5)} {ACC1:acc#264.itm(6)} {ACC1:acc#264.itm(7)} {ACC1:acc#264.itm(8)} {ACC1:acc#264.itm(9)} -attr xrf 17950 -attr oid 96 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#261.itm(0)} -attr vt d
+load net {ACC1:acc#261.itm(1)} -attr vt d
+load net {ACC1:acc#261.itm(2)} -attr vt d
+load net {ACC1:acc#261.itm(3)} -attr vt d
+load net {ACC1:acc#261.itm(4)} -attr vt d
+load net {ACC1:acc#261.itm(5)} -attr vt d
+load net {ACC1:acc#261.itm(6)} -attr vt d
+load net {ACC1:acc#261.itm(7)} -attr vt d
+load net {ACC1:acc#261.itm(8)} -attr vt d
+load netBundle {ACC1:acc#261.itm} 9 {ACC1:acc#261.itm(0)} {ACC1:acc#261.itm(1)} {ACC1:acc#261.itm(2)} {ACC1:acc#261.itm(3)} {ACC1:acc#261.itm(4)} {ACC1:acc#261.itm(5)} {ACC1:acc#261.itm(6)} {ACC1:acc#261.itm(7)} {ACC1:acc#261.itm(8)} -attr xrf 17951 -attr oid 97 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#259.itm(0)} -attr vt d
+load net {ACC1:acc#259.itm(1)} -attr vt d
+load net {ACC1:acc#259.itm(2)} -attr vt d
+load net {ACC1:acc#259.itm(3)} -attr vt d
+load net {ACC1:acc#259.itm(4)} -attr vt d
+load net {ACC1:acc#259.itm(5)} -attr vt d
+load net {ACC1:acc#259.itm(6)} -attr vt d
+load netBundle {ACC1:acc#259.itm} 7 {ACC1:acc#259.itm(0)} {ACC1:acc#259.itm(1)} {ACC1:acc#259.itm(2)} {ACC1:acc#259.itm(3)} {ACC1:acc#259.itm(4)} {ACC1:acc#259.itm(5)} {ACC1:acc#259.itm(6)} -attr xrf 17952 -attr oid 98 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {conc#313.itm(0)} -attr vt d
+load net {conc#313.itm(1)} -attr vt d
+load net {conc#313.itm(2)} -attr vt d
+load net {conc#313.itm(3)} -attr vt d
+load net {conc#313.itm(4)} -attr vt d
+load net {conc#313.itm(5)} -attr vt d
+load net {conc#313.itm(6)} -attr vt d
+load netBundle {conc#313.itm} 7 {conc#313.itm(0)} {conc#313.itm(1)} {conc#313.itm(2)} {conc#313.itm(3)} {conc#313.itm(4)} {conc#313.itm(5)} {conc#313.itm(6)} -attr xrf 17953 -attr oid 99 -attr vt d -attr @path {/sobel/sobel:core/conc#313.itm}
+load net {ACC1-3:exs#2.itm(0)} -attr vt d
+load net {ACC1-3:exs#2.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#2.itm} 2 {ACC1-3:exs#2.itm(0)} {ACC1-3:exs#2.itm(1)} -attr xrf 17954 -attr oid 100 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#2.itm}
+load net {ACC1:conc#250.itm(0)} -attr vt d
+load net {ACC1:conc#250.itm(1)} -attr vt d
+load net {ACC1:conc#250.itm(2)} -attr vt d
+load net {ACC1:conc#250.itm(3)} -attr vt d
+load net {ACC1:conc#250.itm(4)} -attr vt d
+load net {ACC1:conc#250.itm(5)} -attr vt d
+load net {ACC1:conc#250.itm(6)} -attr vt d
+load netBundle {ACC1:conc#250.itm} 7 {ACC1:conc#250.itm(0)} {ACC1:conc#250.itm(1)} {ACC1:conc#250.itm(2)} {ACC1:conc#250.itm(3)} {ACC1:conc#250.itm(4)} {ACC1:conc#250.itm(5)} {ACC1:conc#250.itm(6)} -attr xrf 17955 -attr oid 101 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#250.itm}
+load net {ACC1:mul#92.itm(0)} -attr vt d
+load net {ACC1:mul#92.itm(1)} -attr vt d
+load net {ACC1:mul#92.itm(2)} -attr vt d
+load net {ACC1:mul#92.itm(3)} -attr vt d
+load net {ACC1:mul#92.itm(4)} -attr vt d
+load net {ACC1:mul#92.itm(5)} -attr vt d
+load netBundle {ACC1:mul#92.itm} 6 {ACC1:mul#92.itm(0)} {ACC1:mul#92.itm(1)} {ACC1:mul#92.itm(2)} {ACC1:mul#92.itm(3)} {ACC1:mul#92.itm(4)} {ACC1:mul#92.itm(5)} -attr xrf 17956 -attr oid 102 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#92.itm}
+load net {ACC1:acc#135.itm(0)} -attr vt d
+load net {ACC1:acc#135.itm(1)} -attr vt d
+load netBundle {ACC1:acc#135.itm} 2 {ACC1:acc#135.itm(0)} {ACC1:acc#135.itm(1)} -attr xrf 17957 -attr oid 103 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135.itm}
+load net {ACC1:acc#257.itm(0)} -attr vt d
+load net {ACC1:acc#257.itm(1)} -attr vt d
+load net {ACC1:acc#257.itm(2)} -attr vt d
+load net {ACC1:acc#257.itm(3)} -attr vt d
+load net {ACC1:acc#257.itm(4)} -attr vt d
+load net {ACC1:acc#257.itm(5)} -attr vt d
+load net {ACC1:acc#257.itm(6)} -attr vt d
+load netBundle {ACC1:acc#257.itm} 7 {ACC1:acc#257.itm(0)} {ACC1:acc#257.itm(1)} {ACC1:acc#257.itm(2)} {ACC1:acc#257.itm(3)} {ACC1:acc#257.itm(4)} {ACC1:acc#257.itm(5)} {ACC1:acc#257.itm(6)} -attr xrf 17958 -attr oid 104 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#254.itm(0)} -attr vt d
+load net {ACC1:acc#254.itm(1)} -attr vt d
+load net {ACC1:acc#254.itm(2)} -attr vt d
+load net {ACC1:acc#254.itm(3)} -attr vt d
+load net {ACC1:acc#254.itm(4)} -attr vt d
+load net {ACC1:acc#254.itm(5)} -attr vt d
+load netBundle {ACC1:acc#254.itm} 6 {ACC1:acc#254.itm(0)} {ACC1:acc#254.itm(1)} {ACC1:acc#254.itm(2)} {ACC1:acc#254.itm(3)} {ACC1:acc#254.itm(4)} {ACC1:acc#254.itm(5)} -attr xrf 17959 -attr oid 105 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#249.itm(0)} -attr vt d
+load net {ACC1:acc#249.itm(1)} -attr vt d
+load net {ACC1:acc#249.itm(2)} -attr vt d
+load net {ACC1:acc#249.itm(3)} -attr vt d
+load net {ACC1:acc#249.itm(4)} -attr vt d
+load netBundle {ACC1:acc#249.itm} 5 {ACC1:acc#249.itm(0)} {ACC1:acc#249.itm(1)} {ACC1:acc#249.itm(2)} {ACC1:acc#249.itm(3)} {ACC1:acc#249.itm(4)} -attr xrf 17960 -attr oid 106 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#249.itm}
+load net {ACC1:acc#241.itm(0)} -attr vt d
+load net {ACC1:acc#241.itm(1)} -attr vt d
+load net {ACC1:acc#241.itm(2)} -attr vt d
+load net {ACC1:acc#241.itm(3)} -attr vt d
+load netBundle {ACC1:acc#241.itm} 4 {ACC1:acc#241.itm(0)} {ACC1:acc#241.itm(1)} {ACC1:acc#241.itm(2)} {ACC1:acc#241.itm(3)} -attr xrf 17961 -attr oid 107 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#227.itm(0)} -attr vt d
+load net {ACC1:acc#227.itm(1)} -attr vt d
+load net {ACC1:acc#227.itm(2)} -attr vt d
+load netBundle {ACC1:acc#227.itm} 3 {ACC1:acc#227.itm(0)} {ACC1:acc#227.itm(1)} {ACC1:acc#227.itm(2)} -attr xrf 17962 -attr oid 108 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1-1:exs#3.itm(0)} -attr vt d
+load net {ACC1-1:exs#3.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#3.itm} 2 {ACC1-1:exs#3.itm(0)} {ACC1-1:exs#3.itm(1)} -attr xrf 17963 -attr oid 109 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#3.itm}
+load net {ACC1-1:exs#4.itm(0)} -attr vt d
+load net {ACC1-1:exs#4.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#4.itm} 2 {ACC1-1:exs#4.itm(0)} {ACC1-1:exs#4.itm(1)} -attr xrf 17964 -attr oid 110 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#4.itm}
+load net {ACC1:acc#226.itm(0)} -attr vt d
+load net {ACC1:acc#226.itm(1)} -attr vt d
+load net {ACC1:acc#226.itm(2)} -attr vt d
+load netBundle {ACC1:acc#226.itm} 3 {ACC1:acc#226.itm(0)} {ACC1:acc#226.itm(1)} {ACC1:acc#226.itm(2)} -attr xrf 17965 -attr oid 111 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1-1:exs#5.itm(0)} -attr vt d
+load net {ACC1-1:exs#5.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#5.itm} 2 {ACC1-1:exs#5.itm(0)} {ACC1-1:exs#5.itm(1)} -attr xrf 17966 -attr oid 112 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#5.itm}
+load net {ACC1-1:exs#40.itm(0)} -attr vt d
+load net {ACC1-1:exs#40.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#40.itm} 2 {ACC1-1:exs#40.itm(0)} {ACC1-1:exs#40.itm(1)} -attr xrf 17967 -attr oid 113 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#40.itm}
+load net {ACC1:acc#240.itm(0)} -attr vt d
+load net {ACC1:acc#240.itm(1)} -attr vt d
+load net {ACC1:acc#240.itm(2)} -attr vt d
+load net {ACC1:acc#240.itm(3)} -attr vt d
+load netBundle {ACC1:acc#240.itm} 4 {ACC1:acc#240.itm(0)} {ACC1:acc#240.itm(1)} {ACC1:acc#240.itm(2)} {ACC1:acc#240.itm(3)} -attr xrf 17968 -attr oid 114 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#240.itm}
+load net {ACC1:acc#225.itm(0)} -attr vt d
+load net {ACC1:acc#225.itm(1)} -attr vt d
+load net {ACC1:acc#225.itm(2)} -attr vt d
+load netBundle {ACC1:acc#225.itm} 3 {ACC1:acc#225.itm(0)} {ACC1:acc#225.itm(1)} {ACC1:acc#225.itm(2)} -attr xrf 17969 -attr oid 115 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1-1:exs#35.itm(0)} -attr vt d
+load net {ACC1-1:exs#35.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#35.itm} 2 {ACC1-1:exs#35.itm(0)} {ACC1-1:exs#35.itm(1)} -attr xrf 17970 -attr oid 116 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#35.itm}
+load net {ACC1-1:exs#39.itm(0)} -attr vt d
+load net {ACC1-1:exs#39.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#39.itm} 2 {ACC1-1:exs#39.itm(0)} {ACC1-1:exs#39.itm(1)} -attr xrf 17971 -attr oid 117 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#39.itm}
+load net {ACC1:acc#224.itm(0)} -attr vt d
+load net {ACC1:acc#224.itm(1)} -attr vt d
+load net {ACC1:acc#224.itm(2)} -attr vt d
+load netBundle {ACC1:acc#224.itm} 3 {ACC1:acc#224.itm(0)} {ACC1:acc#224.itm(1)} {ACC1:acc#224.itm(2)} -attr xrf 17972 -attr oid 118 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.itm}
+load net {ACC1-1:exs#37.itm(0)} -attr vt d
+load net {ACC1-1:exs#37.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#37.itm} 2 {ACC1-1:exs#37.itm(0)} {ACC1-1:exs#37.itm(1)} -attr xrf 17973 -attr oid 119 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#37.itm}
+load net {ACC1-1:exs#41.itm(0)} -attr vt d
+load net {ACC1-1:exs#41.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#41.itm} 2 {ACC1-1:exs#41.itm(0)} {ACC1-1:exs#41.itm(1)} -attr xrf 17974 -attr oid 120 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#41.itm}
+load net {ACC1:acc#248.itm(0)} -attr vt d
+load net {ACC1:acc#248.itm(1)} -attr vt d
+load net {ACC1:acc#248.itm(2)} -attr vt d
+load net {ACC1:acc#248.itm(3)} -attr vt d
+load net {ACC1:acc#248.itm(4)} -attr vt d
+load netBundle {ACC1:acc#248.itm} 5 {ACC1:acc#248.itm(0)} {ACC1:acc#248.itm(1)} {ACC1:acc#248.itm(2)} {ACC1:acc#248.itm(3)} {ACC1:acc#248.itm(4)} -attr xrf 17975 -attr oid 121 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#239.itm(0)} -attr vt d
+load net {ACC1:acc#239.itm(1)} -attr vt d
+load net {ACC1:acc#239.itm(2)} -attr vt d
+load net {ACC1:acc#239.itm(3)} -attr vt d
+load netBundle {ACC1:acc#239.itm} 4 {ACC1:acc#239.itm(0)} {ACC1:acc#239.itm(1)} {ACC1:acc#239.itm(2)} {ACC1:acc#239.itm(3)} -attr xrf 17976 -attr oid 122 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#223.itm(0)} -attr vt d
+load net {ACC1:acc#223.itm(1)} -attr vt d
+load net {ACC1:acc#223.itm(2)} -attr vt d
+load netBundle {ACC1:acc#223.itm} 3 {ACC1:acc#223.itm(0)} {ACC1:acc#223.itm(1)} {ACC1:acc#223.itm(2)} -attr xrf 17977 -attr oid 123 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.itm}
+load net {ACC1-1:exs#38.itm(0)} -attr vt d
+load net {ACC1-1:exs#38.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#38.itm} 2 {ACC1-1:exs#38.itm(0)} {ACC1-1:exs#38.itm(1)} -attr xrf 17978 -attr oid 124 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#38.itm}
+load net {ACC1-1:exs#36.itm(0)} -attr vt d
+load net {ACC1-1:exs#36.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#36.itm} 2 {ACC1-1:exs#36.itm(0)} {ACC1-1:exs#36.itm(1)} -attr xrf 17979 -attr oid 125 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#36.itm}
+load net {ACC1:acc#222.itm(0)} -attr vt d
+load net {ACC1:acc#222.itm(1)} -attr vt d
+load net {ACC1:acc#222.itm(2)} -attr vt d
+load netBundle {ACC1:acc#222.itm} 3 {ACC1:acc#222.itm(0)} {ACC1:acc#222.itm(1)} {ACC1:acc#222.itm(2)} -attr xrf 17980 -attr oid 126 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {ACC1-3:exs#14.itm(0)} -attr vt d
+load net {ACC1-3:exs#14.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#14.itm} 2 {ACC1-3:exs#14.itm(0)} {ACC1-3:exs#14.itm(1)} -attr xrf 17981 -attr oid 127 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#14.itm}
+load net {ACC1-3:exs#15.itm(0)} -attr vt d
+load net {ACC1-3:exs#15.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#15.itm} 2 {ACC1-3:exs#15.itm(0)} {ACC1-3:exs#15.itm(1)} -attr xrf 17982 -attr oid 128 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#15.itm}
+load net {ACC1:acc#238.itm(0)} -attr vt d
+load net {ACC1:acc#238.itm(1)} -attr vt d
+load net {ACC1:acc#238.itm(2)} -attr vt d
+load net {ACC1:acc#238.itm(3)} -attr vt d
+load netBundle {ACC1:acc#238.itm} 4 {ACC1:acc#238.itm(0)} {ACC1:acc#238.itm(1)} {ACC1:acc#238.itm(2)} {ACC1:acc#238.itm(3)} -attr xrf 17983 -attr oid 129 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#221.itm(0)} -attr vt d
+load net {ACC1:acc#221.itm(1)} -attr vt d
+load net {ACC1:acc#221.itm(2)} -attr vt d
+load netBundle {ACC1:acc#221.itm} 3 {ACC1:acc#221.itm(0)} {ACC1:acc#221.itm(1)} {ACC1:acc#221.itm(2)} -attr xrf 17984 -attr oid 130 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {ACC1-3:exs#16.itm(0)} -attr vt d
+load net {ACC1-3:exs#16.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#16.itm} 2 {ACC1-3:exs#16.itm(0)} {ACC1-3:exs#16.itm(1)} -attr xrf 17985 -attr oid 131 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#16.itm}
+load net {ACC1-3:exs#17.itm(0)} -attr vt d
+load net {ACC1-3:exs#17.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#17.itm} 2 {ACC1-3:exs#17.itm(0)} {ACC1-3:exs#17.itm(1)} -attr xrf 17986 -attr oid 132 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#17.itm}
+load net {ACC1:acc#220.itm(0)} -attr vt d
+load net {ACC1:acc#220.itm(1)} -attr vt d
+load net {ACC1:acc#220.itm(2)} -attr vt d
+load netBundle {ACC1:acc#220.itm} 3 {ACC1:acc#220.itm(0)} {ACC1:acc#220.itm(1)} {ACC1:acc#220.itm(2)} -attr xrf 17987 -attr oid 133 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {ACC1-3:exs#18.itm(0)} -attr vt d
+load net {ACC1-3:exs#18.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#18.itm} 2 {ACC1-3:exs#18.itm(0)} {ACC1-3:exs#18.itm(1)} -attr xrf 17988 -attr oid 134 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#18.itm}
+load net {ACC1-3:exs#19.itm(0)} -attr vt d
+load net {ACC1-3:exs#19.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#19.itm} 2 {ACC1-3:exs#19.itm(0)} {ACC1-3:exs#19.itm(1)} -attr xrf 17989 -attr oid 135 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#19.itm}
+load net {ACC1:acc#253.itm(0)} -attr vt d
+load net {ACC1:acc#253.itm(1)} -attr vt d
+load net {ACC1:acc#253.itm(2)} -attr vt d
+load net {ACC1:acc#253.itm(3)} -attr vt d
+load net {ACC1:acc#253.itm(4)} -attr vt d
+load net {ACC1:acc#253.itm(5)} -attr vt d
+load netBundle {ACC1:acc#253.itm} 6 {ACC1:acc#253.itm(0)} {ACC1:acc#253.itm(1)} {ACC1:acc#253.itm(2)} {ACC1:acc#253.itm(3)} {ACC1:acc#253.itm(4)} {ACC1:acc#253.itm(5)} -attr xrf 17990 -attr oid 136 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#247.itm(0)} -attr vt d
+load net {ACC1:acc#247.itm(1)} -attr vt d
+load net {ACC1:acc#247.itm(2)} -attr vt d
+load net {ACC1:acc#247.itm(3)} -attr vt d
+load net {ACC1:acc#247.itm(4)} -attr vt d
+load netBundle {ACC1:acc#247.itm} 5 {ACC1:acc#247.itm(0)} {ACC1:acc#247.itm(1)} {ACC1:acc#247.itm(2)} {ACC1:acc#247.itm(3)} {ACC1:acc#247.itm(4)} -attr xrf 17991 -attr oid 137 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#237.itm(0)} -attr vt d
+load net {ACC1:acc#237.itm(1)} -attr vt d
+load net {ACC1:acc#237.itm(2)} -attr vt d
+load net {ACC1:acc#237.itm(3)} -attr vt d
+load netBundle {ACC1:acc#237.itm} 4 {ACC1:acc#237.itm(0)} {ACC1:acc#237.itm(1)} {ACC1:acc#237.itm(2)} {ACC1:acc#237.itm(3)} -attr xrf 17992 -attr oid 138 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#219.itm(0)} -attr vt d
+load net {ACC1:acc#219.itm(1)} -attr vt d
+load net {ACC1:acc#219.itm(2)} -attr vt d
+load netBundle {ACC1:acc#219.itm} 3 {ACC1:acc#219.itm(0)} {ACC1:acc#219.itm(1)} {ACC1:acc#219.itm(2)} -attr xrf 17993 -attr oid 139 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {ACC1-1:exs#29.itm(0)} -attr vt d
+load net {ACC1-1:exs#29.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#29.itm} 2 {ACC1-1:exs#29.itm(0)} {ACC1-1:exs#29.itm(1)} -attr xrf 17994 -attr oid 140 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#29.itm}
+load net {ACC1-1:exs#25.itm(0)} -attr vt d
+load net {ACC1-1:exs#25.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#25.itm} 2 {ACC1-1:exs#25.itm(0)} {ACC1-1:exs#25.itm(1)} -attr xrf 17995 -attr oid 141 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#25.itm}
+load net {ACC1:acc#218.itm(0)} -attr vt d
+load net {ACC1:acc#218.itm(1)} -attr vt d
+load net {ACC1:acc#218.itm(2)} -attr vt d
+load netBundle {ACC1:acc#218.itm} 3 {ACC1:acc#218.itm(0)} {ACC1:acc#218.itm(1)} {ACC1:acc#218.itm(2)} -attr xrf 17996 -attr oid 142 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {ACC1-1:exs#33.itm(0)} -attr vt d
+load net {ACC1-1:exs#33.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#33.itm} 2 {ACC1-1:exs#33.itm(0)} {ACC1-1:exs#33.itm(1)} -attr xrf 17997 -attr oid 143 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#33.itm}
+load net {ACC1-1:exs#27.itm(0)} -attr vt d
+load net {ACC1-1:exs#27.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#27.itm} 2 {ACC1-1:exs#27.itm(0)} {ACC1-1:exs#27.itm(1)} -attr xrf 17998 -attr oid 144 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#27.itm}
+load net {ACC1:acc#236.itm(0)} -attr vt d
+load net {ACC1:acc#236.itm(1)} -attr vt d
+load net {ACC1:acc#236.itm(2)} -attr vt d
+load net {ACC1:acc#236.itm(3)} -attr vt d
+load netBundle {ACC1:acc#236.itm} 4 {ACC1:acc#236.itm(0)} {ACC1:acc#236.itm(1)} {ACC1:acc#236.itm(2)} {ACC1:acc#236.itm(3)} -attr xrf 17999 -attr oid 145 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#217.itm(0)} -attr vt d
+load net {ACC1:acc#217.itm(1)} -attr vt d
+load net {ACC1:acc#217.itm(2)} -attr vt d
+load netBundle {ACC1:acc#217.itm} 3 {ACC1:acc#217.itm(0)} {ACC1:acc#217.itm(1)} {ACC1:acc#217.itm(2)} -attr xrf 18000 -attr oid 146 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1-1:exs#23.itm(0)} -attr vt d
+load net {ACC1-1:exs#23.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#23.itm} 2 {ACC1-1:exs#23.itm(0)} {ACC1-1:exs#23.itm(1)} -attr xrf 18001 -attr oid 147 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#23.itm}
+load net {ACC1-1:exs#31.itm(0)} -attr vt d
+load net {ACC1-1:exs#31.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#31.itm} 2 {ACC1-1:exs#31.itm(0)} {ACC1-1:exs#31.itm(1)} -attr xrf 18002 -attr oid 148 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#31.itm}
+load net {ACC1:acc#216.itm(0)} -attr vt d
+load net {ACC1:acc#216.itm(1)} -attr vt d
+load net {ACC1:acc#216.itm(2)} -attr vt d
+load netBundle {ACC1:acc#216.itm} 3 {ACC1:acc#216.itm(0)} {ACC1:acc#216.itm(1)} {ACC1:acc#216.itm(2)} -attr xrf 18003 -attr oid 149 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {ACC1-1:exs#21.itm(0)} -attr vt d
+load net {ACC1-1:exs#21.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#21.itm} 2 {ACC1-1:exs#21.itm(0)} {ACC1-1:exs#21.itm(1)} -attr xrf 18004 -attr oid 150 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#21.itm}
+load net {ACC1-3:exs#20.itm(0)} -attr vt d
+load net {ACC1-3:exs#20.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#20.itm} 2 {ACC1-3:exs#20.itm(0)} {ACC1-3:exs#20.itm(1)} -attr xrf 18005 -attr oid 151 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#20.itm}
+load net {ACC1:acc#246.itm(0)} -attr vt d
+load net {ACC1:acc#246.itm(1)} -attr vt d
+load net {ACC1:acc#246.itm(2)} -attr vt d
+load net {ACC1:acc#246.itm(3)} -attr vt d
+load net {ACC1:acc#246.itm(4)} -attr vt d
+load netBundle {ACC1:acc#246.itm} 5 {ACC1:acc#246.itm(0)} {ACC1:acc#246.itm(1)} {ACC1:acc#246.itm(2)} {ACC1:acc#246.itm(3)} {ACC1:acc#246.itm(4)} -attr xrf 18006 -attr oid 152 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#235.itm(0)} -attr vt d
+load net {ACC1:acc#235.itm(1)} -attr vt d
+load net {ACC1:acc#235.itm(2)} -attr vt d
+load net {ACC1:acc#235.itm(3)} -attr vt d
+load netBundle {ACC1:acc#235.itm} 4 {ACC1:acc#235.itm(0)} {ACC1:acc#235.itm(1)} {ACC1:acc#235.itm(2)} {ACC1:acc#235.itm(3)} -attr xrf 18007 -attr oid 153 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#215.itm(0)} -attr vt d
+load net {ACC1:acc#215.itm(1)} -attr vt d
+load net {ACC1:acc#215.itm(2)} -attr vt d
+load netBundle {ACC1:acc#215.itm} 3 {ACC1:acc#215.itm(0)} {ACC1:acc#215.itm(1)} {ACC1:acc#215.itm(2)} -attr xrf 18008 -attr oid 154 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:conc.itm(0)} -attr vt d
+load net {ACC1:conc.itm(1)} -attr vt d
+load netBundle {ACC1:conc.itm} 2 {ACC1:conc.itm(0)} {ACC1:conc.itm(1)} -attr xrf 18009 -attr oid 155 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:conc#245.itm(0)} -attr vt d
+load net {ACC1:conc#245.itm(1)} -attr vt d
+load netBundle {ACC1:conc#245.itm} 2 {ACC1:conc#245.itm(0)} {ACC1:conc#245.itm(1)} -attr xrf 18010 -attr oid 156 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#245.itm}
+load net {ACC1:acc#214.itm(0)} -attr vt d
+load net {ACC1:acc#214.itm(1)} -attr vt d
+load net {ACC1:acc#214.itm(2)} -attr vt d
+load netBundle {ACC1:acc#214.itm} 3 {ACC1:acc#214.itm(0)} {ACC1:acc#214.itm(1)} {ACC1:acc#214.itm(2)} -attr xrf 18011 -attr oid 157 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:conc#246.itm(0)} -attr vt d
+load net {ACC1:conc#246.itm(1)} -attr vt d
+load netBundle {ACC1:conc#246.itm} 2 {ACC1:conc#246.itm(0)} {ACC1:conc#246.itm(1)} -attr xrf 18012 -attr oid 158 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#246.itm}
+load net {ACC1:conc#247.itm(0)} -attr vt d
+load net {ACC1:conc#247.itm(1)} -attr vt d
+load netBundle {ACC1:conc#247.itm} 2 {ACC1:conc#247.itm(0)} {ACC1:conc#247.itm(1)} -attr xrf 18013 -attr oid 159 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#247.itm}
+load net {ACC1:acc#234.itm(0)} -attr vt d
+load net {ACC1:acc#234.itm(1)} -attr vt d
+load net {ACC1:acc#234.itm(2)} -attr vt d
+load net {ACC1:acc#234.itm(3)} -attr vt d
+load netBundle {ACC1:acc#234.itm} 4 {ACC1:acc#234.itm(0)} {ACC1:acc#234.itm(1)} {ACC1:acc#234.itm(2)} {ACC1:acc#234.itm(3)} -attr xrf 18014 -attr oid 160 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#213.itm(0)} -attr vt d
+load net {ACC1:acc#213.itm(1)} -attr vt d
+load net {ACC1:acc#213.itm(2)} -attr vt d
+load netBundle {ACC1:acc#213.itm} 3 {ACC1:acc#213.itm(0)} {ACC1:acc#213.itm(1)} {ACC1:acc#213.itm(2)} -attr xrf 18015 -attr oid 161 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:conc#248.itm(0)} -attr vt d
+load net {ACC1:conc#248.itm(1)} -attr vt d
+load netBundle {ACC1:conc#248.itm} 2 {ACC1:conc#248.itm(0)} {ACC1:conc#248.itm(1)} -attr xrf 18016 -attr oid 162 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#248.itm}
+load net {ACC1:conc#249.itm(0)} -attr vt d
+load net {ACC1:conc#249.itm(1)} -attr vt d
+load netBundle {ACC1:conc#249.itm} 2 {ACC1:conc#249.itm(0)} {ACC1:conc#249.itm(1)} -attr xrf 18017 -attr oid 163 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#249.itm}
+load net {ACC1:acc#212.itm(0)} -attr vt d
+load net {ACC1:acc#212.itm(1)} -attr vt d
+load net {ACC1:acc#212.itm(2)} -attr vt d
+load netBundle {ACC1:acc#212.itm} 3 {ACC1:acc#212.itm(0)} {ACC1:acc#212.itm(1)} {ACC1:acc#212.itm(2)} -attr xrf 18018 -attr oid 164 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:conc#256.itm(0)} -attr vt d
+load net {ACC1:conc#256.itm(1)} -attr vt d
+load netBundle {ACC1:conc#256.itm} 2 {ACC1:conc#256.itm(0)} {ACC1:conc#256.itm(1)} -attr xrf 18019 -attr oid 165 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#256.itm}
+load net {ACC1:conc#257.itm(0)} -attr vt d
+load net {ACC1:conc#257.itm(1)} -attr vt d
+load netBundle {ACC1:conc#257.itm} 2 {ACC1:conc#257.itm(0)} {ACC1:conc#257.itm(1)} -attr xrf 18020 -attr oid 166 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#257.itm}
+load net {ACC1:conc#251.itm(0)} -attr vt d
+load net {ACC1:conc#251.itm(1)} -attr vt d
+load net {ACC1:conc#251.itm(2)} -attr vt d
+load net {ACC1:conc#251.itm(3)} -attr vt d
+load net {ACC1:conc#251.itm(4)} -attr vt d
+load net {ACC1:conc#251.itm(5)} -attr vt d
+load net {ACC1:conc#251.itm(6)} -attr vt d
+load net {ACC1:conc#251.itm(7)} -attr vt d
+load net {ACC1:conc#251.itm(8)} -attr vt d
+load netBundle {ACC1:conc#251.itm} 9 {ACC1:conc#251.itm(0)} {ACC1:conc#251.itm(1)} {ACC1:conc#251.itm(2)} {ACC1:conc#251.itm(3)} {ACC1:conc#251.itm(4)} {ACC1:conc#251.itm(5)} {ACC1:conc#251.itm(6)} {ACC1:conc#251.itm(7)} {ACC1:conc#251.itm(8)} -attr xrf 18021 -attr oid 167 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#251.itm}
+load net {ACC1:mul#93.itm(0)} -attr vt d
+load net {ACC1:mul#93.itm(1)} -attr vt d
+load net {ACC1:mul#93.itm(2)} -attr vt d
+load net {ACC1:mul#93.itm(3)} -attr vt d
+load net {ACC1:mul#93.itm(4)} -attr vt d
+load net {ACC1:mul#93.itm(5)} -attr vt d
+load net {ACC1:mul#93.itm(6)} -attr vt d
+load net {ACC1:mul#93.itm(7)} -attr vt d
+load netBundle {ACC1:mul#93.itm} 8 {ACC1:mul#93.itm(0)} {ACC1:mul#93.itm(1)} {ACC1:mul#93.itm(2)} {ACC1:mul#93.itm(3)} {ACC1:mul#93.itm(4)} {ACC1:mul#93.itm(5)} {ACC1:mul#93.itm(6)} {ACC1:mul#93.itm(7)} -attr xrf 18022 -attr oid 168 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#93.itm}
+load net {ACC1:acc#136.itm(0)} -attr vt d
+load net {ACC1:acc#136.itm(1)} -attr vt d
+load netBundle {ACC1:acc#136.itm} 2 {ACC1:acc#136.itm(0)} {ACC1:acc#136.itm(1)} -attr xrf 18023 -attr oid 169 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load net {ACC1:mul#90.itm(0)} -attr vt d
+load net {ACC1:mul#90.itm(1)} -attr vt d
+load net {ACC1:mul#90.itm(2)} -attr vt d
+load net {ACC1:mul#90.itm(3)} -attr vt d
+load net {ACC1:mul#90.itm(4)} -attr vt d
+load net {ACC1:mul#90.itm(5)} -attr vt d
+load net {ACC1:mul#90.itm(6)} -attr vt d
+load net {ACC1:mul#90.itm(7)} -attr vt d
+load net {ACC1:mul#90.itm(8)} -attr vt d
+load net {ACC1:mul#90.itm(9)} -attr vt d
+load net {ACC1:mul#90.itm(10)} -attr vt d
+load net {ACC1:mul#90.itm(11)} -attr vt d
+load netBundle {ACC1:mul#90.itm} 12 {ACC1:mul#90.itm(0)} {ACC1:mul#90.itm(1)} {ACC1:mul#90.itm(2)} {ACC1:mul#90.itm(3)} {ACC1:mul#90.itm(4)} {ACC1:mul#90.itm(5)} {ACC1:mul#90.itm(6)} {ACC1:mul#90.itm(7)} {ACC1:mul#90.itm(8)} {ACC1:mul#90.itm(9)} {ACC1:mul#90.itm(10)} {ACC1:mul#90.itm(11)} -attr xrf 18024 -attr oid 170 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:acc#133.itm(0)} -attr vt d
+load net {ACC1:acc#133.itm(1)} -attr vt d
+load netBundle {ACC1:acc#133.itm} 2 {ACC1:acc#133.itm(0)} {ACC1:acc#133.itm(1)} -attr xrf 18025 -attr oid 171 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:mul#91.itm(0)} -attr vt d
+load net {ACC1:mul#91.itm(1)} -attr vt d
+load net {ACC1:mul#91.itm(2)} -attr vt d
+load net {ACC1:mul#91.itm(3)} -attr vt d
+load net {ACC1:mul#91.itm(4)} -attr vt d
+load net {ACC1:mul#91.itm(5)} -attr vt d
+load net {ACC1:mul#91.itm(6)} -attr vt d
+load net {ACC1:mul#91.itm(7)} -attr vt d
+load net {ACC1:mul#91.itm(8)} -attr vt d
+load net {ACC1:mul#91.itm(9)} -attr vt d
+load net {ACC1:mul#91.itm(10)} -attr vt d
+load net {ACC1:mul#91.itm(11)} -attr vt d
+load net {ACC1:mul#91.itm(12)} -attr vt d
+load net {ACC1:mul#91.itm(13)} -attr vt d
+load netBundle {ACC1:mul#91.itm} 14 {ACC1:mul#91.itm(0)} {ACC1:mul#91.itm(1)} {ACC1:mul#91.itm(2)} {ACC1:mul#91.itm(3)} {ACC1:mul#91.itm(4)} {ACC1:mul#91.itm(5)} {ACC1:mul#91.itm(6)} {ACC1:mul#91.itm(7)} {ACC1:mul#91.itm(8)} {ACC1:mul#91.itm(9)} {ACC1:mul#91.itm(10)} {ACC1:mul#91.itm(11)} {ACC1:mul#91.itm(12)} {ACC1:mul#91.itm(13)} -attr xrf 18026 -attr oid 172 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:acc#134.itm(0)} -attr vt d
+load net {ACC1:acc#134.itm(1)} -attr vt d
+load netBundle {ACC1:acc#134.itm} 2 {ACC1:acc#134.itm(0)} {ACC1:acc#134.itm(1)} -attr xrf 18027 -attr oid 173 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134.itm}
+load net {ACC1:mul#104.itm(0)} -attr vt d
+load net {ACC1:mul#104.itm(1)} -attr vt d
+load net {ACC1:mul#104.itm(2)} -attr vt d
+load net {ACC1:mul#104.itm(3)} -attr vt d
+load net {ACC1:mul#104.itm(4)} -attr vt d
+load net {ACC1:mul#104.itm(5)} -attr vt d
+load net {ACC1:mul#104.itm(6)} -attr vt d
+load net {ACC1:mul#104.itm(7)} -attr vt d
+load net {ACC1:mul#104.itm(8)} -attr vt d
+load net {ACC1:mul#104.itm(9)} -attr vt d
+load netBundle {ACC1:mul#104.itm} 10 {ACC1:mul#104.itm(0)} {ACC1:mul#104.itm(1)} {ACC1:mul#104.itm(2)} {ACC1:mul#104.itm(3)} {ACC1:mul#104.itm(4)} {ACC1:mul#104.itm(5)} {ACC1:mul#104.itm(6)} {ACC1:mul#104.itm(7)} {ACC1:mul#104.itm(8)} {ACC1:mul#104.itm(9)} -attr xrf 18028 -attr oid 174 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:acc#147.itm(0)} -attr vt d
+load net {ACC1:acc#147.itm(1)} -attr vt d
+load netBundle {ACC1:acc#147.itm} 2 {ACC1:acc#147.itm(0)} {ACC1:acc#147.itm(1)} -attr xrf 18029 -attr oid 175 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load net {ACC1:mul#103.itm(0)} -attr vt d
+load net {ACC1:mul#103.itm(1)} -attr vt d
+load net {ACC1:mul#103.itm(2)} -attr vt d
+load net {ACC1:mul#103.itm(3)} -attr vt d
+load net {ACC1:mul#103.itm(4)} -attr vt d
+load net {ACC1:mul#103.itm(5)} -attr vt d
+load net {ACC1:mul#103.itm(6)} -attr vt d
+load net {ACC1:mul#103.itm(7)} -attr vt d
+load netBundle {ACC1:mul#103.itm} 8 {ACC1:mul#103.itm(0)} {ACC1:mul#103.itm(1)} {ACC1:mul#103.itm(2)} {ACC1:mul#103.itm(3)} {ACC1:mul#103.itm(4)} {ACC1:mul#103.itm(5)} {ACC1:mul#103.itm(6)} {ACC1:mul#103.itm(7)} -attr xrf 18030 -attr oid 176 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:acc#146.itm(0)} -attr vt d
+load net {ACC1:acc#146.itm(1)} -attr vt d
+load netBundle {ACC1:acc#146.itm} 2 {ACC1:acc#146.itm(0)} {ACC1:acc#146.itm(1)} -attr xrf 18031 -attr oid 177 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {ACC1:mul#98.itm(0)} -attr vt d
+load net {ACC1:mul#98.itm(1)} -attr vt d
+load net {ACC1:mul#98.itm(2)} -attr vt d
+load net {ACC1:mul#98.itm(3)} -attr vt d
+load net {ACC1:mul#98.itm(4)} -attr vt d
+load net {ACC1:mul#98.itm(5)} -attr vt d
+load netBundle {ACC1:mul#98.itm} 6 {ACC1:mul#98.itm(0)} {ACC1:mul#98.itm(1)} {ACC1:mul#98.itm(2)} {ACC1:mul#98.itm(3)} {ACC1:mul#98.itm(4)} {ACC1:mul#98.itm(5)} -attr xrf 18032 -attr oid 178 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm}
+load net {ACC1:acc#141.itm(0)} -attr vt d
+load net {ACC1:acc#141.itm(1)} -attr vt d
+load netBundle {ACC1:acc#141.itm} 2 {ACC1:acc#141.itm(0)} {ACC1:acc#141.itm(1)} -attr xrf 18033 -attr oid 179 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141.itm}
+load net {ACC1:acc#252.itm(0)} -attr vt d
+load net {ACC1:acc#252.itm(1)} -attr vt d
+load net {ACC1:acc#252.itm(2)} -attr vt d
+load net {ACC1:acc#252.itm(3)} -attr vt d
+load net {ACC1:acc#252.itm(4)} -attr vt d
+load net {ACC1:acc#252.itm(5)} -attr vt d
+load netBundle {ACC1:acc#252.itm} 6 {ACC1:acc#252.itm(0)} {ACC1:acc#252.itm(1)} {ACC1:acc#252.itm(2)} {ACC1:acc#252.itm(3)} {ACC1:acc#252.itm(4)} {ACC1:acc#252.itm(5)} -attr xrf 18034 -attr oid 180 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#245.itm(0)} -attr vt d
+load net {ACC1:acc#245.itm(1)} -attr vt d
+load net {ACC1:acc#245.itm(2)} -attr vt d
+load net {ACC1:acc#245.itm(3)} -attr vt d
+load net {ACC1:acc#245.itm(4)} -attr vt d
+load netBundle {ACC1:acc#245.itm} 5 {ACC1:acc#245.itm(0)} {ACC1:acc#245.itm(1)} {ACC1:acc#245.itm(2)} {ACC1:acc#245.itm(3)} {ACC1:acc#245.itm(4)} -attr xrf 18035 -attr oid 181 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#233.itm(0)} -attr vt d
+load net {ACC1:acc#233.itm(1)} -attr vt d
+load net {ACC1:acc#233.itm(2)} -attr vt d
+load net {ACC1:acc#233.itm(3)} -attr vt d
+load netBundle {ACC1:acc#233.itm} 4 {ACC1:acc#233.itm(0)} {ACC1:acc#233.itm(1)} {ACC1:acc#233.itm(2)} {ACC1:acc#233.itm(3)} -attr xrf 18036 -attr oid 182 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#211.itm(0)} -attr vt d
+load net {ACC1:acc#211.itm(1)} -attr vt d
+load net {ACC1:acc#211.itm(2)} -attr vt d
+load netBundle {ACC1:acc#211.itm} 3 {ACC1:acc#211.itm(0)} {ACC1:acc#211.itm(1)} {ACC1:acc#211.itm(2)} -attr xrf 18037 -attr oid 183 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:conc#258.itm(0)} -attr vt d
+load net {ACC1:conc#258.itm(1)} -attr vt d
+load netBundle {ACC1:conc#258.itm} 2 {ACC1:conc#258.itm(0)} {ACC1:conc#258.itm(1)} -attr xrf 18038 -attr oid 184 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#258.itm}
+load net {ACC1:conc#259.itm(0)} -attr vt d
+load net {ACC1:conc#259.itm(1)} -attr vt d
+load netBundle {ACC1:conc#259.itm} 2 {ACC1:conc#259.itm(0)} {ACC1:conc#259.itm(1)} -attr xrf 18039 -attr oid 185 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#259.itm}
+load net {ACC1:conc#404.itm(0)} -attr vt d
+load net {ACC1:conc#404.itm(1)} -attr vt d
+load net {ACC1:conc#404.itm(2)} -attr vt d
+load netBundle {ACC1:conc#404.itm} 3 {ACC1:conc#404.itm(0)} {ACC1:conc#404.itm(1)} {ACC1:conc#404.itm(2)} -attr xrf 18040 -attr oid 186 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#404.itm}
+load net {ACC1:acc#286.itm(0)} -attr vt d
+load net {ACC1:acc#286.itm(1)} -attr vt d
+load netBundle {ACC1:acc#286.itm} 2 {ACC1:acc#286.itm(0)} {ACC1:acc#286.itm(1)} -attr xrf 18041 -attr oid 187 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {conc#314.itm(0)} -attr vt d
+load net {conc#314.itm(1)} -attr vt d
+load net {conc#314.itm(2)} -attr vt d
+load netBundle {conc#314.itm} 3 {conc#314.itm(0)} {conc#314.itm(1)} {conc#314.itm(2)} -attr xrf 18042 -attr oid 188 -attr vt d -attr @path {/sobel/sobel:core/conc#314.itm}
+load net {ACC1:conc#394.itm(0)} -attr vt d
+load net {ACC1:conc#394.itm(1)} -attr vt d
+load netBundle {ACC1:conc#394.itm} 2 {ACC1:conc#394.itm(0)} {ACC1:conc#394.itm(1)} -attr xrf 18043 -attr oid 189 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#394.itm}
+load net {conc#315.itm(0)} -attr vt d
+load net {conc#315.itm(1)} -attr vt d
+load net {conc#315.itm(2)} -attr vt d
+load net {conc#315.itm(3)} -attr vt d
+load netBundle {conc#315.itm} 4 {conc#315.itm(0)} {conc#315.itm(1)} {conc#315.itm(2)} {conc#315.itm(3)} -attr xrf 18044 -attr oid 190 -attr vt d -attr @path {/sobel/sobel:core/conc#315.itm}
+load net {ACC1:acc#294.itm(0)} -attr vt d
+load net {ACC1:acc#294.itm(1)} -attr vt d
+load net {ACC1:acc#294.itm(2)} -attr vt d
+load netBundle {ACC1:acc#294.itm} 3 {ACC1:acc#294.itm(0)} {ACC1:acc#294.itm(1)} {ACC1:acc#294.itm(2)} -attr xrf 18045 -attr oid 191 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {slc.itm(0)} -attr vt d
+load net {slc.itm(1)} -attr vt d
+load netBundle {slc.itm} 2 {slc.itm(0)} {slc.itm(1)} -attr xrf 18046 -attr oid 192 -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(0)} -attr vt d
+load net {acc.itm(1)} -attr vt d
+load net {acc.itm(2)} -attr vt d
+load netBundle {acc.itm} 3 {acc.itm(0)} {acc.itm(1)} {acc.itm(2)} -attr xrf 18047 -attr oid 193 -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {conc#316.itm(0)} -attr vt d
+load net {conc#316.itm(1)} -attr vt d
+load netBundle {conc#316.itm} 2 {conc#316.itm(0)} {conc#316.itm(1)} -attr xrf 18048 -attr oid 194 -attr vt d -attr @path {/sobel/sobel:core/conc#316.itm}
+load net {conc#304.itm(0)} -attr vt d
+load net {conc#304.itm(1)} -attr vt d
+load netBundle {conc#304.itm} 2 {conc#304.itm(0)} {conc#304.itm(1)} -attr xrf 18049 -attr oid 195 -attr vt d -attr @path {/sobel/sobel:core/conc#304.itm}
+load net {ACC1:conc#411.itm(0)} -attr vt d
+load net {ACC1:conc#411.itm(1)} -attr vt d
+load net {ACC1:conc#411.itm(2)} -attr vt d
+load net {ACC1:conc#411.itm(3)} -attr vt d
+load net {ACC1:conc#411.itm(4)} -attr vt d
+load netBundle {ACC1:conc#411.itm} 5 {ACC1:conc#411.itm(0)} {ACC1:conc#411.itm(1)} {ACC1:conc#411.itm(2)} {ACC1:conc#411.itm(3)} {ACC1:conc#411.itm(4)} -attr xrf 18050 -attr oid 196 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#411.itm}
+load net {slc#2.itm(0)} -attr vt d
+load net {slc#2.itm(1)} -attr vt d
+load net {slc#2.itm(2)} -attr vt d
+load net {slc#2.itm(3)} -attr vt d
+load netBundle {slc#2.itm} 4 {slc#2.itm(0)} {slc#2.itm(1)} {slc#2.itm(2)} {slc#2.itm(3)} -attr xrf 18051 -attr oid 197 -attr vt d -attr @path {/sobel/sobel:core/slc#2.itm}
+load net {acc#20.itm(0)} -attr vt d
+load net {acc#20.itm(1)} -attr vt d
+load net {acc#20.itm(2)} -attr vt d
+load net {acc#20.itm(3)} -attr vt d
+load net {acc#20.itm(4)} -attr vt d
+load netBundle {acc#20.itm} 5 {acc#20.itm(0)} {acc#20.itm(1)} {acc#20.itm(2)} {acc#20.itm(3)} {acc#20.itm(4)} -attr xrf 18052 -attr oid 198 -attr vt d -attr @path {/sobel/sobel:core/acc#20.itm}
+load net {conc#317.itm(0)} -attr vt d
+load net {conc#317.itm(1)} -attr vt d
+load net {conc#317.itm(2)} -attr vt d
+load netBundle {conc#317.itm} 3 {conc#317.itm(0)} {conc#317.itm(1)} {conc#317.itm(2)} -attr xrf 18053 -attr oid 199 -attr vt d -attr @path {/sobel/sobel:core/conc#317.itm}
+load net {slc#1.itm(0)} -attr vt d
+load net {slc#1.itm(1)} -attr vt d
+load netBundle {slc#1.itm} 2 {slc#1.itm(0)} {slc#1.itm(1)} -attr xrf 18054 -attr oid 200 -attr vt d -attr @path {/sobel/sobel:core/slc#1.itm}
+load net {acc#19.itm(0)} -attr vt d
+load net {acc#19.itm(1)} -attr vt d
+load net {acc#19.itm(2)} -attr vt d
+load netBundle {acc#19.itm} 3 {acc#19.itm(0)} {acc#19.itm(1)} {acc#19.itm(2)} -attr xrf 18055 -attr oid 201 -attr vt d -attr @path {/sobel/sobel:core/acc#19.itm}
+load net {conc#318.itm(0)} -attr vt d
+load net {conc#318.itm(1)} -attr vt d
+load netBundle {conc#318.itm} 2 {conc#318.itm(0)} {conc#318.itm(1)} -attr xrf 18056 -attr oid 202 -attr vt d -attr @path {/sobel/sobel:core/conc#318.itm}
+load net {conc#306.itm(0)} -attr vt d
+load net {conc#306.itm(1)} -attr vt d
+load netBundle {conc#306.itm} 2 {conc#306.itm(0)} {conc#306.itm(1)} -attr xrf 18057 -attr oid 203 -attr vt d -attr @path {/sobel/sobel:core/conc#306.itm}
+load net {conc#308.itm(0)} -attr vt d
+load net {conc#308.itm(1)} -attr vt d
+load net {conc#308.itm(2)} -attr vt d
+load net {conc#308.itm(3)} -attr vt d
+load netBundle {conc#308.itm} 4 {conc#308.itm(0)} {conc#308.itm(1)} {conc#308.itm(2)} {conc#308.itm(3)} -attr xrf 18058 -attr oid 204 -attr vt d -attr @path {/sobel/sobel:core/conc#308.itm}
+load net {slc(ACC1:acc#230.sdt).itm(0)} -attr vt d
+load net {slc(ACC1:acc#230.sdt).itm(1)} -attr vt d
+load net {slc(ACC1:acc#230.sdt).itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#230.sdt).itm} 3 {slc(ACC1:acc#230.sdt).itm(0)} {slc(ACC1:acc#230.sdt).itm(1)} {slc(ACC1:acc#230.sdt).itm(2)} -attr xrf 18059 -attr oid 205 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#230.sdt).itm}
+load net {ACC1:acc#251.itm(0)} -attr vt d
+load net {ACC1:acc#251.itm(1)} -attr vt d
+load net {ACC1:acc#251.itm(2)} -attr vt d
+load net {ACC1:acc#251.itm(3)} -attr vt d
+load net {ACC1:acc#251.itm(4)} -attr vt d
+load net {ACC1:acc#251.itm(5)} -attr vt d
+load netBundle {ACC1:acc#251.itm} 6 {ACC1:acc#251.itm(0)} {ACC1:acc#251.itm(1)} {ACC1:acc#251.itm(2)} {ACC1:acc#251.itm(3)} {ACC1:acc#251.itm(4)} {ACC1:acc#251.itm(5)} -attr xrf 18060 -attr oid 206 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#243.itm(0)} -attr vt d
+load net {ACC1:acc#243.itm(1)} -attr vt d
+load net {ACC1:acc#243.itm(2)} -attr vt d
+load net {ACC1:acc#243.itm(3)} -attr vt d
+load net {ACC1:acc#243.itm(4)} -attr vt d
+load netBundle {ACC1:acc#243.itm} 5 {ACC1:acc#243.itm(0)} {ACC1:acc#243.itm(1)} {ACC1:acc#243.itm(2)} {ACC1:acc#243.itm(3)} {ACC1:acc#243.itm(4)} -attr xrf 18061 -attr oid 207 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:conc#278.itm(0)} -attr vt d
+load net {ACC1:conc#278.itm(1)} -attr vt d
+load net {ACC1:conc#278.itm(2)} -attr vt d
+load net {ACC1:conc#278.itm(3)} -attr vt d
+load netBundle {ACC1:conc#278.itm} 4 {ACC1:conc#278.itm(0)} {ACC1:conc#278.itm(1)} {ACC1:conc#278.itm(2)} {ACC1:conc#278.itm(3)} -attr xrf 18062 -attr oid 208 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#278.itm}
+load net {conc#319.itm(0)} -attr vt d
+load net {conc#319.itm(1)} -attr vt d
+load net {conc#319.itm(2)} -attr vt d
+load netBundle {conc#319.itm} 3 {conc#319.itm(0)} {conc#319.itm(1)} {conc#319.itm(2)} -attr xrf 18063 -attr oid 209 -attr vt d -attr @path {/sobel/sobel:core/conc#319.itm}
+load net {ACC1:conc#403.itm(0)} -attr vt d
+load net {ACC1:conc#403.itm(1)} -attr vt d
+load netBundle {ACC1:conc#403.itm} 2 {ACC1:conc#403.itm(0)} {ACC1:conc#403.itm(1)} -attr xrf 18064 -attr oid 210 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#403.itm}
+load net {ACC1:conc#279.itm(0)} -attr vt d
+load net {ACC1:conc#279.itm(1)} -attr vt d
+load net {ACC1:conc#279.itm(2)} -attr vt d
+load net {ACC1:conc#279.itm(3)} -attr vt d
+load netBundle {ACC1:conc#279.itm} 4 {ACC1:conc#279.itm(0)} {ACC1:conc#279.itm(1)} {ACC1:conc#279.itm(2)} {ACC1:conc#279.itm(3)} -attr xrf 18065 -attr oid 211 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#279.itm}
+load net {conc#320.itm(0)} -attr vt d
+load net {conc#320.itm(1)} -attr vt d
+load net {conc#320.itm(2)} -attr vt d
+load net {conc#320.itm(3)} -attr vt d
+load net {conc#320.itm(4)} -attr vt d
+load netBundle {conc#320.itm} 5 {conc#320.itm(0)} {conc#320.itm(1)} {conc#320.itm(2)} {conc#320.itm(3)} {conc#320.itm(4)} -attr xrf 18066 -attr oid 212 -attr vt d -attr @path {/sobel/sobel:core/conc#320.itm}
+load net {ACC1-2:exs#22.itm(0)} -attr vt d
+load net {ACC1-2:exs#22.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#22.itm} 2 {ACC1-2:exs#22.itm(0)} {ACC1-2:exs#22.itm(1)} -attr xrf 18067 -attr oid 213 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#22.itm}
+load net {ACC1:acc#255.itm(0)} -attr vt d
+load net {ACC1:acc#255.itm(1)} -attr vt d
+load net {ACC1:acc#255.itm(2)} -attr vt d
+load net {ACC1:acc#255.itm(3)} -attr vt d
+load net {ACC1:acc#255.itm(4)} -attr vt d
+load net {ACC1:acc#255.itm(5)} -attr vt d
+load net {ACC1:acc#255.itm(6)} -attr vt d
+load netBundle {ACC1:acc#255.itm} 7 {ACC1:acc#255.itm(0)} {ACC1:acc#255.itm(1)} {ACC1:acc#255.itm(2)} {ACC1:acc#255.itm(3)} {ACC1:acc#255.itm(4)} {ACC1:acc#255.itm(5)} {ACC1:acc#255.itm(6)} -attr xrf 18068 -attr oid 214 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#250.itm(0)} -attr vt d
+load net {ACC1:acc#250.itm(1)} -attr vt d
+load net {ACC1:acc#250.itm(2)} -attr vt d
+load net {ACC1:acc#250.itm(3)} -attr vt d
+load net {ACC1:acc#250.itm(4)} -attr vt d
+load net {ACC1:acc#250.itm(5)} -attr vt d
+load netBundle {ACC1:acc#250.itm} 6 {ACC1:acc#250.itm(0)} {ACC1:acc#250.itm(1)} {ACC1:acc#250.itm(2)} {ACC1:acc#250.itm(3)} {ACC1:acc#250.itm(4)} {ACC1:acc#250.itm(5)} -attr xrf 18069 -attr oid 215 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.itm}
+load net {conc#321.itm(0)} -attr vt d
+load net {conc#321.itm(1)} -attr vt d
+load net {conc#321.itm(2)} -attr vt d
+load net {conc#321.itm(3)} -attr vt d
+load net {conc#321.itm(4)} -attr vt d
+load netBundle {conc#321.itm} 5 {conc#321.itm(0)} {conc#321.itm(1)} {conc#321.itm(2)} {conc#321.itm(3)} {conc#321.itm(4)} -attr xrf 18070 -attr oid 216 -attr vt d -attr @path {/sobel/sobel:core/conc#321.itm}
+load net {ACC1-2:exs#23.itm(0)} -attr vt d
+load net {ACC1-2:exs#23.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#23.itm} 2 {ACC1-2:exs#23.itm(0)} {ACC1-2:exs#23.itm(1)} -attr xrf 18071 -attr oid 217 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#23.itm}
+load net {ACC1:acc#242.itm(0)} -attr vt d
+load net {ACC1:acc#242.itm(1)} -attr vt d
+load net {ACC1:acc#242.itm(2)} -attr vt d
+load net {ACC1:acc#242.itm(3)} -attr vt d
+load netBundle {ACC1:acc#242.itm} 4 {ACC1:acc#242.itm(0)} {ACC1:acc#242.itm(1)} {ACC1:acc#242.itm(2)} {ACC1:acc#242.itm(3)} -attr xrf 18072 -attr oid 218 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#229.itm(0)} -attr vt d
+load net {ACC1:acc#229.itm(1)} -attr vt d
+load net {ACC1:acc#229.itm(2)} -attr vt d
+load netBundle {ACC1:acc#229.itm} 3 {ACC1:acc#229.itm(0)} {ACC1:acc#229.itm(1)} {ACC1:acc#229.itm(2)} -attr xrf 18073 -attr oid 219 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1-1:exs#6.itm(0)} -attr vt d
+load net {ACC1-1:exs#6.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#6.itm} 2 {ACC1-1:exs#6.itm(0)} {ACC1-1:exs#6.itm(1)} -attr xrf 18074 -attr oid 220 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#6.itm}
+load net {ACC1-1:exs.itm(0)} -attr vt d
+load net {ACC1-1:exs.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs.itm} 2 {ACC1-1:exs.itm(0)} {ACC1-1:exs.itm(1)} -attr xrf 18075 -attr oid 221 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs.itm}
+load net {ACC1:acc#228.itm(0)} -attr vt d
+load net {ACC1:acc#228.itm(1)} -attr vt d
+load net {ACC1:acc#228.itm(2)} -attr vt d
+load netBundle {ACC1:acc#228.itm} 3 {ACC1:acc#228.itm(0)} {ACC1:acc#228.itm(1)} {ACC1:acc#228.itm(2)} -attr xrf 18076 -attr oid 222 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1-1:exs#1.itm(0)} -attr vt d
+load net {ACC1-1:exs#1.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#1.itm} 2 {ACC1-1:exs#1.itm(0)} {ACC1-1:exs#1.itm(1)} -attr xrf 18077 -attr oid 223 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1.itm}
+load net {ACC1-1:exs#2.itm(0)} -attr vt d
+load net {ACC1-1:exs#2.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#2.itm} 2 {ACC1-1:exs#2.itm(0)} {ACC1-1:exs#2.itm(1)} -attr xrf 18078 -attr oid 224 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#2.itm}
+load net {ACC1:mul.itm(0)} -attr vt d
+load net {ACC1:mul.itm(1)} -attr vt d
+load net {ACC1:mul.itm(2)} -attr vt d
+load net {ACC1:mul.itm(3)} -attr vt d
+load net {ACC1:mul.itm(4)} -attr vt d
+load net {ACC1:mul.itm(5)} -attr vt d
+load netBundle {ACC1:mul.itm} 6 {ACC1:mul.itm(0)} {ACC1:mul.itm(1)} {ACC1:mul.itm(2)} {ACC1:mul.itm(3)} {ACC1:mul.itm(4)} {ACC1:mul.itm(5)} -attr xrf 18079 -attr oid 225 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:acc#130.itm(0)} -attr vt d
+load net {ACC1:acc#130.itm(1)} -attr vt d
+load netBundle {ACC1:acc#130.itm} 2 {ACC1:acc#130.itm(0)} {ACC1:acc#130.itm(1)} -attr xrf 18080 -attr oid 226 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#130.itm}
+load net {ACC1:mul#89.itm(0)} -attr vt d
+load net {ACC1:mul#89.itm(1)} -attr vt d
+load net {ACC1:mul#89.itm(2)} -attr vt d
+load net {ACC1:mul#89.itm(3)} -attr vt d
+load net {ACC1:mul#89.itm(4)} -attr vt d
+load net {ACC1:mul#89.itm(5)} -attr vt d
+load net {ACC1:mul#89.itm(6)} -attr vt d
+load net {ACC1:mul#89.itm(7)} -attr vt d
+load net {ACC1:mul#89.itm(8)} -attr vt d
+load net {ACC1:mul#89.itm(9)} -attr vt d
+load netBundle {ACC1:mul#89.itm} 10 {ACC1:mul#89.itm(0)} {ACC1:mul#89.itm(1)} {ACC1:mul#89.itm(2)} {ACC1:mul#89.itm(3)} {ACC1:mul#89.itm(4)} {ACC1:mul#89.itm(5)} {ACC1:mul#89.itm(6)} {ACC1:mul#89.itm(7)} {ACC1:mul#89.itm(8)} {ACC1:mul#89.itm(9)} -attr xrf 18081 -attr oid 227 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:acc#132.itm(0)} -attr vt d
+load net {ACC1:acc#132.itm(1)} -attr vt d
+load netBundle {ACC1:acc#132.itm} 2 {ACC1:acc#132.itm(0)} {ACC1:acc#132.itm(1)} -attr xrf 18082 -attr oid 228 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#268.itm(0)} -attr vt d
+load net {ACC1:acc#268.itm(1)} -attr vt d
+load net {ACC1:acc#268.itm(2)} -attr vt d
+load net {ACC1:acc#268.itm(3)} -attr vt d
+load net {ACC1:acc#268.itm(4)} -attr vt d
+load net {ACC1:acc#268.itm(5)} -attr vt d
+load net {ACC1:acc#268.itm(6)} -attr vt d
+load net {ACC1:acc#268.itm(7)} -attr vt d
+load net {ACC1:acc#268.itm(8)} -attr vt d
+load net {ACC1:acc#268.itm(9)} -attr vt d
+load net {ACC1:acc#268.itm(10)} -attr vt d
+load net {ACC1:acc#268.itm(11)} -attr vt d
+load netBundle {ACC1:acc#268.itm} 12 {ACC1:acc#268.itm(0)} {ACC1:acc#268.itm(1)} {ACC1:acc#268.itm(2)} {ACC1:acc#268.itm(3)} {ACC1:acc#268.itm(4)} {ACC1:acc#268.itm(5)} {ACC1:acc#268.itm(6)} {ACC1:acc#268.itm(7)} {ACC1:acc#268.itm(8)} {ACC1:acc#268.itm(9)} {ACC1:acc#268.itm(10)} {ACC1:acc#268.itm(11)} -attr xrf 18083 -attr oid 229 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#265.itm(0)} -attr vt d
+load net {ACC1:acc#265.itm(1)} -attr vt d
+load net {ACC1:acc#265.itm(2)} -attr vt d
+load net {ACC1:acc#265.itm(3)} -attr vt d
+load net {ACC1:acc#265.itm(4)} -attr vt d
+load net {ACC1:acc#265.itm(5)} -attr vt d
+load net {ACC1:acc#265.itm(6)} -attr vt d
+load net {ACC1:acc#265.itm(7)} -attr vt d
+load net {ACC1:acc#265.itm(8)} -attr vt d
+load net {ACC1:acc#265.itm(9)} -attr vt d
+load net {ACC1:acc#265.itm(10)} -attr vt d
+load netBundle {ACC1:acc#265.itm} 11 {ACC1:acc#265.itm(0)} {ACC1:acc#265.itm(1)} {ACC1:acc#265.itm(2)} {ACC1:acc#265.itm(3)} {ACC1:acc#265.itm(4)} {ACC1:acc#265.itm(5)} {ACC1:acc#265.itm(6)} {ACC1:acc#265.itm(7)} {ACC1:acc#265.itm(8)} {ACC1:acc#265.itm(9)} {ACC1:acc#265.itm(10)} -attr xrf 18084 -attr oid 230 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {conc#322.itm(0)} -attr vt d
+load net {conc#322.itm(1)} -attr vt d
+load net {conc#322.itm(2)} -attr vt d
+load net {conc#322.itm(3)} -attr vt d
+load net {conc#322.itm(4)} -attr vt d
+load net {conc#322.itm(5)} -attr vt d
+load net {conc#322.itm(6)} -attr vt d
+load net {conc#322.itm(7)} -attr vt d
+load net {conc#322.itm(8)} -attr vt d
+load net {conc#322.itm(9)} -attr vt d
+load netBundle {conc#322.itm} 10 {conc#322.itm(0)} {conc#322.itm(1)} {conc#322.itm(2)} {conc#322.itm(3)} {conc#322.itm(4)} {conc#322.itm(5)} {conc#322.itm(6)} {conc#322.itm(7)} {conc#322.itm(8)} {conc#322.itm(9)} -attr xrf 18085 -attr oid 231 -attr vt d -attr @path {/sobel/sobel:core/conc#322.itm}
+load net {ACC1:mul#102.itm(0)} -attr vt d
+load net {ACC1:mul#102.itm(1)} -attr vt d
+load net {ACC1:mul#102.itm(2)} -attr vt d
+load net {ACC1:mul#102.itm(3)} -attr vt d
+load net {ACC1:mul#102.itm(4)} -attr vt d
+load net {ACC1:mul#102.itm(5)} -attr vt d
+load netBundle {ACC1:mul#102.itm} 6 {ACC1:mul#102.itm(0)} {ACC1:mul#102.itm(1)} {ACC1:mul#102.itm(2)} {ACC1:mul#102.itm(3)} {ACC1:mul#102.itm(4)} {ACC1:mul#102.itm(5)} -attr xrf 18086 -attr oid 232 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#102.itm}
+load net {ACC1:acc#145.itm(0)} -attr vt d
+load net {ACC1:acc#145.itm(1)} -attr vt d
+load netBundle {ACC1:acc#145.itm} 2 {ACC1:acc#145.itm(0)} {ACC1:acc#145.itm(1)} -attr xrf 18087 -attr oid 233 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145.itm}
+load net {ACC1-3:exs#21.itm(0)} -attr vt d
+load net {ACC1-3:exs#21.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#21.itm} 2 {ACC1-3:exs#21.itm(0)} {ACC1-3:exs#21.itm(1)} -attr xrf 18088 -attr oid 234 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#21.itm}
+load net {ACC1:acc#262.itm(0)} -attr vt d
+load net {ACC1:acc#262.itm(1)} -attr vt d
+load net {ACC1:acc#262.itm(2)} -attr vt d
+load net {ACC1:acc#262.itm(3)} -attr vt d
+load net {ACC1:acc#262.itm(4)} -attr vt d
+load net {ACC1:acc#262.itm(5)} -attr vt d
+load net {ACC1:acc#262.itm(6)} -attr vt d
+load net {ACC1:acc#262.itm(7)} -attr vt d
+load net {ACC1:acc#262.itm(8)} -attr vt d
+load netBundle {ACC1:acc#262.itm} 9 {ACC1:acc#262.itm(0)} {ACC1:acc#262.itm(1)} {ACC1:acc#262.itm(2)} {ACC1:acc#262.itm(3)} {ACC1:acc#262.itm(4)} {ACC1:acc#262.itm(5)} {ACC1:acc#262.itm(6)} {ACC1:acc#262.itm(7)} {ACC1:acc#262.itm(8)} -attr xrf 18089 -attr oid 235 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:conc#412.itm(0)} -attr vt d
+load net {ACC1:conc#412.itm(1)} -attr vt d
+load net {ACC1:conc#412.itm(2)} -attr vt d
+load net {ACC1:conc#412.itm(3)} -attr vt d
+load net {ACC1:conc#412.itm(4)} -attr vt d
+load net {ACC1:conc#412.itm(5)} -attr vt d
+load net {ACC1:conc#412.itm(6)} -attr vt d
+load net {ACC1:conc#412.itm(7)} -attr vt d
+load netBundle {ACC1:conc#412.itm} 8 {ACC1:conc#412.itm(0)} {ACC1:conc#412.itm(1)} {ACC1:conc#412.itm(2)} {ACC1:conc#412.itm(3)} {ACC1:conc#412.itm(4)} {ACC1:conc#412.itm(5)} {ACC1:conc#412.itm(6)} {ACC1:conc#412.itm(7)} -attr xrf 18090 -attr oid 236 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#412.itm}
+load net {ACC1:acc#296.itm(0)} -attr vt d
+load net {ACC1:acc#296.itm(1)} -attr vt d
+load net {ACC1:acc#296.itm(2)} -attr vt d
+load net {ACC1:acc#296.itm(3)} -attr vt d
+load netBundle {ACC1:acc#296.itm} 4 {ACC1:acc#296.itm(0)} {ACC1:acc#296.itm(1)} {ACC1:acc#296.itm(2)} {ACC1:acc#296.itm(3)} -attr xrf 18091 -attr oid 237 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:conc#286.itm(0)} -attr vt d
+load net {ACC1:conc#286.itm(1)} -attr vt d
+load net {ACC1:conc#286.itm(2)} -attr vt d
+load netBundle {ACC1:conc#286.itm} 3 {ACC1:conc#286.itm(0)} {ACC1:conc#286.itm(1)} {ACC1:conc#286.itm(2)} -attr xrf 18092 -attr oid 238 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#286.itm}
+load net {ACC1:conc#287.itm(0)} -attr vt d
+load net {ACC1:conc#287.itm(1)} -attr vt d
+load net {ACC1:conc#287.itm(2)} -attr vt d
+load netBundle {ACC1:conc#287.itm} 3 {ACC1:conc#287.itm(0)} {ACC1:conc#287.itm(1)} {ACC1:conc#287.itm(2)} -attr xrf 18093 -attr oid 239 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#287.itm}
+load net {ACC1:acc#297.itm(0)} -attr vt d
+load net {ACC1:acc#297.itm(1)} -attr vt d
+load net {ACC1:acc#297.itm(2)} -attr vt d
+load net {ACC1:acc#297.itm(3)} -attr vt d
+load netBundle {ACC1:acc#297.itm} 4 {ACC1:acc#297.itm(0)} {ACC1:acc#297.itm(1)} {ACC1:acc#297.itm(2)} {ACC1:acc#297.itm(3)} -attr xrf 18094 -attr oid 240 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:conc#413.itm(0)} -attr vt d
+load net {ACC1:conc#413.itm(1)} -attr vt d
+load net {ACC1:conc#413.itm(2)} -attr vt d
+load netBundle {ACC1:conc#413.itm} 3 {ACC1:conc#413.itm(0)} {ACC1:conc#413.itm(1)} {ACC1:conc#413.itm(2)} -attr xrf 18095 -attr oid 241 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#413.itm}
+load net {ACC1-3:exs.itm(0)} -attr vt d
+load net {ACC1-3:exs.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs.itm} 2 {ACC1-3:exs.itm(0)} {ACC1-3:exs.itm(1)} -attr xrf 18096 -attr oid 242 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs.itm}
+load net {ACC1:conc#414.itm(0)} -attr vt d
+load net {ACC1:conc#414.itm(1)} -attr vt d
+load net {ACC1:conc#414.itm(2)} -attr vt d
+load netBundle {ACC1:conc#414.itm} 3 {ACC1:conc#414.itm(0)} {ACC1:conc#414.itm(1)} {ACC1:conc#414.itm(2)} -attr xrf 18097 -attr oid 243 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#414.itm}
+load net {ACC1-3:exs#1.itm(0)} -attr vt d
+load net {ACC1-3:exs#1.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#1.itm} 2 {ACC1-3:exs#1.itm(0)} {ACC1-3:exs#1.itm(1)} -attr xrf 18098 -attr oid 244 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#1.itm}
+load net {ACC1:mul#88.itm(0)} -attr vt d
+load net {ACC1:mul#88.itm(1)} -attr vt d
+load net {ACC1:mul#88.itm(2)} -attr vt d
+load net {ACC1:mul#88.itm(3)} -attr vt d
+load net {ACC1:mul#88.itm(4)} -attr vt d
+load net {ACC1:mul#88.itm(5)} -attr vt d
+load net {ACC1:mul#88.itm(6)} -attr vt d
+load net {ACC1:mul#88.itm(7)} -attr vt d
+load netBundle {ACC1:mul#88.itm} 8 {ACC1:mul#88.itm(0)} {ACC1:mul#88.itm(1)} {ACC1:mul#88.itm(2)} {ACC1:mul#88.itm(3)} {ACC1:mul#88.itm(4)} {ACC1:mul#88.itm(5)} {ACC1:mul#88.itm(6)} {ACC1:mul#88.itm(7)} -attr xrf 18099 -attr oid 245 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:acc#131.itm(0)} -attr vt d
+load net {ACC1:acc#131.itm(1)} -attr vt d
+load netBundle {ACC1:acc#131.itm} 2 {ACC1:acc#131.itm(0)} {ACC1:acc#131.itm(1)} -attr xrf 18100 -attr oid 246 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#131.itm}
+load net {ACC1:conc#252.itm(0)} -attr vt d
+load net {ACC1:conc#252.itm(1)} -attr vt d
+load net {ACC1:conc#252.itm(2)} -attr vt d
+load net {ACC1:conc#252.itm(3)} -attr vt d
+load net {ACC1:conc#252.itm(4)} -attr vt d
+load net {ACC1:conc#252.itm(5)} -attr vt d
+load net {ACC1:conc#252.itm(6)} -attr vt d
+load net {ACC1:conc#252.itm(7)} -attr vt d
+load net {ACC1:conc#252.itm(8)} -attr vt d
+load net {ACC1:conc#252.itm(9)} -attr vt d
+load net {ACC1:conc#252.itm(10)} -attr vt d
+load netBundle {ACC1:conc#252.itm} 11 {ACC1:conc#252.itm(0)} {ACC1:conc#252.itm(1)} {ACC1:conc#252.itm(2)} {ACC1:conc#252.itm(3)} {ACC1:conc#252.itm(4)} {ACC1:conc#252.itm(5)} {ACC1:conc#252.itm(6)} {ACC1:conc#252.itm(7)} {ACC1:conc#252.itm(8)} {ACC1:conc#252.itm(9)} {ACC1:conc#252.itm(10)} -attr xrf 18101 -attr oid 247 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#252.itm}
+load net {ACC1:mul#94.itm(0)} -attr vt d
+load net {ACC1:mul#94.itm(1)} -attr vt d
+load net {ACC1:mul#94.itm(2)} -attr vt d
+load net {ACC1:mul#94.itm(3)} -attr vt d
+load net {ACC1:mul#94.itm(4)} -attr vt d
+load net {ACC1:mul#94.itm(5)} -attr vt d
+load net {ACC1:mul#94.itm(6)} -attr vt d
+load net {ACC1:mul#94.itm(7)} -attr vt d
+load net {ACC1:mul#94.itm(8)} -attr vt d
+load net {ACC1:mul#94.itm(9)} -attr vt d
+load netBundle {ACC1:mul#94.itm} 10 {ACC1:mul#94.itm(0)} {ACC1:mul#94.itm(1)} {ACC1:mul#94.itm(2)} {ACC1:mul#94.itm(3)} {ACC1:mul#94.itm(4)} {ACC1:mul#94.itm(5)} {ACC1:mul#94.itm(6)} {ACC1:mul#94.itm(7)} {ACC1:mul#94.itm(8)} {ACC1:mul#94.itm(9)} -attr xrf 18102 -attr oid 248 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#94.itm}
+load net {ACC1:acc#137.itm(0)} -attr vt d
+load net {ACC1:acc#137.itm(1)} -attr vt d
+load netBundle {ACC1:acc#137.itm} 2 {ACC1:acc#137.itm(0)} {ACC1:acc#137.itm(1)} -attr xrf 18103 -attr oid 249 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load net {ACC1:mul#96.itm(0)} -attr vt d
+load net {ACC1:mul#96.itm(1)} -attr vt d
+load net {ACC1:mul#96.itm(2)} -attr vt d
+load net {ACC1:mul#96.itm(3)} -attr vt d
+load net {ACC1:mul#96.itm(4)} -attr vt d
+load net {ACC1:mul#96.itm(5)} -attr vt d
+load net {ACC1:mul#96.itm(6)} -attr vt d
+load net {ACC1:mul#96.itm(7)} -attr vt d
+load net {ACC1:mul#96.itm(8)} -attr vt d
+load net {ACC1:mul#96.itm(9)} -attr vt d
+load net {ACC1:mul#96.itm(10)} -attr vt d
+load net {ACC1:mul#96.itm(11)} -attr vt d
+load net {ACC1:mul#96.itm(12)} -attr vt d
+load net {ACC1:mul#96.itm(13)} -attr vt d
+load netBundle {ACC1:mul#96.itm} 14 {ACC1:mul#96.itm(0)} {ACC1:mul#96.itm(1)} {ACC1:mul#96.itm(2)} {ACC1:mul#96.itm(3)} {ACC1:mul#96.itm(4)} {ACC1:mul#96.itm(5)} {ACC1:mul#96.itm(6)} {ACC1:mul#96.itm(7)} {ACC1:mul#96.itm(8)} {ACC1:mul#96.itm(9)} {ACC1:mul#96.itm(10)} {ACC1:mul#96.itm(11)} {ACC1:mul#96.itm(12)} {ACC1:mul#96.itm(13)} -attr xrf 18104 -attr oid 250 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:acc#139.itm(0)} -attr vt d
+load net {ACC1:acc#139.itm(1)} -attr vt d
+load netBundle {ACC1:acc#139.itm} 2 {ACC1:acc#139.itm(0)} {ACC1:acc#139.itm(1)} -attr xrf 18105 -attr oid 251 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139.itm}
+load net {slc(regs.regs(1).sg2.sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sg2.sva)#2.itm} 10 {slc(regs.regs(1).sg2.sva)#2.itm(0)} {slc(regs.regs(1).sg2.sva)#2.itm(1)} {slc(regs.regs(1).sg2.sva)#2.itm(2)} {slc(regs.regs(1).sg2.sva)#2.itm(3)} {slc(regs.regs(1).sg2.sva)#2.itm(4)} {slc(regs.regs(1).sg2.sva)#2.itm(5)} {slc(regs.regs(1).sg2.sva)#2.itm(6)} {slc(regs.regs(1).sg2.sva)#2.itm(7)} {slc(regs.regs(1).sg2.sva)#2.itm(8)} {slc(regs.regs(1).sg2.sva)#2.itm(9)} -attr xrf 18106 -attr oid 252 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {slc(regs.regs(1).sg2.sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sg2.sva)#1.itm} 10 {slc(regs.regs(1).sg2.sva)#1.itm(0)} {slc(regs.regs(1).sg2.sva)#1.itm(1)} {slc(regs.regs(1).sg2.sva)#1.itm(2)} {slc(regs.regs(1).sg2.sva)#1.itm(3)} {slc(regs.regs(1).sg2.sva)#1.itm(4)} {slc(regs.regs(1).sg2.sva)#1.itm(5)} {slc(regs.regs(1).sg2.sva)#1.itm(6)} {slc(regs.regs(1).sg2.sva)#1.itm(7)} {slc(regs.regs(1).sg2.sva)#1.itm(8)} {slc(regs.regs(1).sg2.sva)#1.itm(9)} -attr xrf 18107 -attr oid 253 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {slc(regs.regs(1).sg2.sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sg2.sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sg2.sva).itm} 10 {slc(regs.regs(1).sg2.sva).itm(0)} {slc(regs.regs(1).sg2.sva).itm(1)} {slc(regs.regs(1).sg2.sva).itm(2)} {slc(regs.regs(1).sg2.sva).itm(3)} {slc(regs.regs(1).sg2.sva).itm(4)} {slc(regs.regs(1).sg2.sva).itm(5)} {slc(regs.regs(1).sg2.sva).itm(6)} {slc(regs.regs(1).sg2.sva).itm(7)} {slc(regs.regs(1).sg2.sva).itm(8)} {slc(regs.regs(1).sg2.sva).itm(9)} -attr xrf 18108 -attr oid 254 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {slc(regs.regs(1)#1.sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1)#1.sva)#2.itm} 10 {slc(regs.regs(1)#1.sva)#2.itm(0)} {slc(regs.regs(1)#1.sva)#2.itm(1)} {slc(regs.regs(1)#1.sva)#2.itm(2)} {slc(regs.regs(1)#1.sva)#2.itm(3)} {slc(regs.regs(1)#1.sva)#2.itm(4)} {slc(regs.regs(1)#1.sva)#2.itm(5)} {slc(regs.regs(1)#1.sva)#2.itm(6)} {slc(regs.regs(1)#1.sva)#2.itm(7)} {slc(regs.regs(1)#1.sva)#2.itm(8)} {slc(regs.regs(1)#1.sva)#2.itm(9)} -attr xrf 18109 -attr oid 255 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {slc(regs.regs(1)#1.sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1)#1.sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1)#1.sva)#1.itm} 10 {slc(regs.regs(1)#1.sva)#1.itm(0)} {slc(regs.regs(1)#1.sva)#1.itm(1)} {slc(regs.regs(1)#1.sva)#1.itm(2)} {slc(regs.regs(1)#1.sva)#1.itm(3)} {slc(regs.regs(1)#1.sva)#1.itm(4)} {slc(regs.regs(1)#1.sva)#1.itm(5)} {slc(regs.regs(1)#1.sva)#1.itm(6)} {slc(regs.regs(1)#1.sva)#1.itm(7)} {slc(regs.regs(1)#1.sva)#1.itm(8)} {slc(regs.regs(1)#1.sva)#1.itm(9)} -attr xrf 18110 -attr oid 256 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {slc(regs.regs(1)#1.sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1)#1.sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1)#1.sva).itm} 10 {slc(regs.regs(1)#1.sva).itm(0)} {slc(regs.regs(1)#1.sva).itm(1)} {slc(regs.regs(1)#1.sva).itm(2)} {slc(regs.regs(1)#1.sva).itm(3)} {slc(regs.regs(1)#1.sva).itm(4)} {slc(regs.regs(1)#1.sva).itm(5)} {slc(regs.regs(1)#1.sva).itm(6)} {slc(regs.regs(1)#1.sva).itm(7)} {slc(regs.regs(1)#1.sva).itm(8)} {slc(regs.regs(1)#1.sva).itm(9)} -attr xrf 18111 -attr oid 257 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {slc(regs.regs(0).sva#7).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(9)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(10)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(11)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(12)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(13)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(14)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(15)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(16)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(17)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(18)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(19)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(20)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(21)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(22)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(23)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(24)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(25)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(26)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(27)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(28)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(29)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#7).itm} 30 {slc(regs.regs(0).sva#7).itm(0)} {slc(regs.regs(0).sva#7).itm(1)} {slc(regs.regs(0).sva#7).itm(2)} {slc(regs.regs(0).sva#7).itm(3)} {slc(regs.regs(0).sva#7).itm(4)} {slc(regs.regs(0).sva#7).itm(5)} {slc(regs.regs(0).sva#7).itm(6)} {slc(regs.regs(0).sva#7).itm(7)} {slc(regs.regs(0).sva#7).itm(8)} {slc(regs.regs(0).sva#7).itm(9)} {slc(regs.regs(0).sva#7).itm(10)} {slc(regs.regs(0).sva#7).itm(11)} {slc(regs.regs(0).sva#7).itm(12)} {slc(regs.regs(0).sva#7).itm(13)} {slc(regs.regs(0).sva#7).itm(14)} {slc(regs.regs(0).sva#7).itm(15)} {slc(regs.regs(0).sva#7).itm(16)} {slc(regs.regs(0).sva#7).itm(17)} {slc(regs.regs(0).sva#7).itm(18)} {slc(regs.regs(0).sva#7).itm(19)} {slc(regs.regs(0).sva#7).itm(20)} {slc(regs.regs(0).sva#7).itm(21)} {slc(regs.regs(0).sva#7).itm(22)} {slc(regs.regs(0).sva#7).itm(23)} {slc(regs.regs(0).sva#7).itm(24)} {slc(regs.regs(0).sva#7).itm(25)} {slc(regs.regs(0).sva#7).itm(26)} {slc(regs.regs(0).sva#7).itm(27)} {slc(regs.regs(0).sva#7).itm(28)} {slc(regs.regs(0).sva#7).itm(29)} -attr xrf 18112 -attr oid 258 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {slc(regs.regs(0).sva#8).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(9)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(10)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(11)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(12)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(13)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(14)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(15)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(16)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(17)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(18)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(19)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(20)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(21)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(22)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(23)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(24)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(25)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(26)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(27)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(28)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(29)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#8).itm} 30 {slc(regs.regs(0).sva#8).itm(0)} {slc(regs.regs(0).sva#8).itm(1)} {slc(regs.regs(0).sva#8).itm(2)} {slc(regs.regs(0).sva#8).itm(3)} {slc(regs.regs(0).sva#8).itm(4)} {slc(regs.regs(0).sva#8).itm(5)} {slc(regs.regs(0).sva#8).itm(6)} {slc(regs.regs(0).sva#8).itm(7)} {slc(regs.regs(0).sva#8).itm(8)} {slc(regs.regs(0).sva#8).itm(9)} {slc(regs.regs(0).sva#8).itm(10)} {slc(regs.regs(0).sva#8).itm(11)} {slc(regs.regs(0).sva#8).itm(12)} {slc(regs.regs(0).sva#8).itm(13)} {slc(regs.regs(0).sva#8).itm(14)} {slc(regs.regs(0).sva#8).itm(15)} {slc(regs.regs(0).sva#8).itm(16)} {slc(regs.regs(0).sva#8).itm(17)} {slc(regs.regs(0).sva#8).itm(18)} {slc(regs.regs(0).sva#8).itm(19)} {slc(regs.regs(0).sva#8).itm(20)} {slc(regs.regs(0).sva#8).itm(21)} {slc(regs.regs(0).sva#8).itm(22)} {slc(regs.regs(0).sva#8).itm(23)} {slc(regs.regs(0).sva#8).itm(24)} {slc(regs.regs(0).sva#8).itm(25)} {slc(regs.regs(0).sva#8).itm(26)} {slc(regs.regs(0).sva#8).itm(27)} {slc(regs.regs(0).sva#8).itm(28)} {slc(regs.regs(0).sva#8).itm(29)} -attr xrf 18113 -attr oid 259 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {FRAME:acc#18.itm(0)} -attr vt d
+load net {FRAME:acc#18.itm(1)} -attr vt d
+load net {FRAME:acc#18.itm(2)} -attr vt d
+load net {FRAME:acc#18.itm(3)} -attr vt d
+load net {FRAME:acc#18.itm(4)} -attr vt d
+load net {FRAME:acc#18.itm(5)} -attr vt d
+load net {FRAME:acc#18.itm(6)} -attr vt d
+load net {FRAME:acc#18.itm(7)} -attr vt d
+load net {FRAME:acc#18.itm(8)} -attr vt d
+load net {FRAME:acc#18.itm(9)} -attr vt d
+load net {FRAME:acc#18.itm(10)} -attr vt d
+load net {FRAME:acc#18.itm(11)} -attr vt d
+load netBundle {FRAME:acc#18.itm} 12 {FRAME:acc#18.itm(0)} {FRAME:acc#18.itm(1)} {FRAME:acc#18.itm(2)} {FRAME:acc#18.itm(3)} {FRAME:acc#18.itm(4)} {FRAME:acc#18.itm(5)} {FRAME:acc#18.itm(6)} {FRAME:acc#18.itm(7)} {FRAME:acc#18.itm(8)} {FRAME:acc#18.itm(9)} {FRAME:acc#18.itm(10)} {FRAME:acc#18.itm(11)} -attr xrf 18114 -attr oid 260 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:mul#6.itm(0)} -attr vt d
+load net {FRAME:mul#6.itm(1)} -attr vt d
+load net {FRAME:mul#6.itm(2)} -attr vt d
+load net {FRAME:mul#6.itm(3)} -attr vt d
+load net {FRAME:mul#6.itm(4)} -attr vt d
+load net {FRAME:mul#6.itm(5)} -attr vt d
+load net {FRAME:mul#6.itm(6)} -attr vt d
+load net {FRAME:mul#6.itm(7)} -attr vt d
+load net {FRAME:mul#6.itm(8)} -attr vt d
+load net {FRAME:mul#6.itm(9)} -attr vt d
+load net {FRAME:mul#6.itm(10)} -attr vt d
+load netBundle {FRAME:mul#6.itm} 11 {FRAME:mul#6.itm(0)} {FRAME:mul#6.itm(1)} {FRAME:mul#6.itm(2)} {FRAME:mul#6.itm(3)} {FRAME:mul#6.itm(4)} {FRAME:mul#6.itm(5)} {FRAME:mul#6.itm(6)} {FRAME:mul#6.itm(7)} {FRAME:mul#6.itm(8)} {FRAME:mul#6.itm(9)} {FRAME:mul#6.itm(10)} -attr xrf 18115 -attr oid 261 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:acc#17.itm(0)} -attr vt d
+load net {FRAME:acc#17.itm(1)} -attr vt d
+load net {FRAME:acc#17.itm(2)} -attr vt d
+load net {FRAME:acc#17.itm(3)} -attr vt d
+load net {FRAME:acc#17.itm(4)} -attr vt d
+load net {FRAME:acc#17.itm(5)} -attr vt d
+load net {FRAME:acc#17.itm(6)} -attr vt d
+load net {FRAME:acc#17.itm(7)} -attr vt d
+load net {FRAME:acc#17.itm(8)} -attr vt d
+load net {FRAME:acc#17.itm(9)} -attr vt d
+load netBundle {FRAME:acc#17.itm} 10 {FRAME:acc#17.itm(0)} {FRAME:acc#17.itm(1)} {FRAME:acc#17.itm(2)} {FRAME:acc#17.itm(3)} {FRAME:acc#17.itm(4)} {FRAME:acc#17.itm(5)} {FRAME:acc#17.itm(6)} {FRAME:acc#17.itm(7)} {FRAME:acc#17.itm(8)} {FRAME:acc#17.itm(9)} -attr xrf 18116 -attr oid 262 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:mul#7.itm(0)} -attr vt d
+load net {FRAME:mul#7.itm(1)} -attr vt d
+load net {FRAME:mul#7.itm(2)} -attr vt d
+load net {FRAME:mul#7.itm(3)} -attr vt d
+load net {FRAME:mul#7.itm(4)} -attr vt d
+load net {FRAME:mul#7.itm(5)} -attr vt d
+load net {FRAME:mul#7.itm(6)} -attr vt d
+load net {FRAME:mul#7.itm(7)} -attr vt d
+load net {FRAME:mul#7.itm(8)} -attr vt d
+load netBundle {FRAME:mul#7.itm} 9 {FRAME:mul#7.itm(0)} {FRAME:mul#7.itm(1)} {FRAME:mul#7.itm(2)} {FRAME:mul#7.itm(3)} {FRAME:mul#7.itm(4)} {FRAME:mul#7.itm(5)} {FRAME:mul#7.itm(6)} {FRAME:mul#7.itm(7)} {FRAME:mul#7.itm(8)} -attr xrf 18117 -attr oid 263 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:acc#16.itm(0)} -attr vt d
+load net {FRAME:acc#16.itm(1)} -attr vt d
+load net {FRAME:acc#16.itm(2)} -attr vt d
+load net {FRAME:acc#16.itm(3)} -attr vt d
+load net {FRAME:acc#16.itm(4)} -attr vt d
+load net {FRAME:acc#16.itm(5)} -attr vt d
+load net {FRAME:acc#16.itm(6)} -attr vt d
+load net {FRAME:acc#16.itm(7)} -attr vt d
+load netBundle {FRAME:acc#16.itm} 8 {FRAME:acc#16.itm(0)} {FRAME:acc#16.itm(1)} {FRAME:acc#16.itm(2)} {FRAME:acc#16.itm(3)} {FRAME:acc#16.itm(4)} {FRAME:acc#16.itm(5)} {FRAME:acc#16.itm(6)} {FRAME:acc#16.itm(7)} -attr xrf 18118 -attr oid 264 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#15.itm(0)} -attr vt d
+load net {FRAME:acc#15.itm(1)} -attr vt d
+load net {FRAME:acc#15.itm(2)} -attr vt d
+load net {FRAME:acc#15.itm(3)} -attr vt d
+load net {FRAME:acc#15.itm(4)} -attr vt d
+load netBundle {FRAME:acc#15.itm} 5 {FRAME:acc#15.itm(0)} {FRAME:acc#15.itm(1)} {FRAME:acc#15.itm(2)} {FRAME:acc#15.itm(3)} {FRAME:acc#15.itm(4)} -attr xrf 18119 -attr oid 265 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#14.itm(0)} -attr vt d
+load net {FRAME:acc#14.itm(1)} -attr vt d
+load net {FRAME:acc#14.itm(2)} -attr vt d
+load net {FRAME:acc#14.itm(3)} -attr vt d
+load net {FRAME:acc#14.itm(4)} -attr vt d
+load netBundle {FRAME:acc#14.itm} 5 {FRAME:acc#14.itm(0)} {FRAME:acc#14.itm(1)} {FRAME:acc#14.itm(2)} {FRAME:acc#14.itm(3)} {FRAME:acc#14.itm(4)} -attr xrf 18120 -attr oid 266 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#13.itm(0)} -attr vt d
+load net {FRAME:acc#13.itm(1)} -attr vt d
+load net {FRAME:acc#13.itm(2)} -attr vt d
+load net {FRAME:acc#13.itm(3)} -attr vt d
+load netBundle {FRAME:acc#13.itm} 4 {FRAME:acc#13.itm(0)} {FRAME:acc#13.itm(1)} {FRAME:acc#13.itm(2)} {FRAME:acc#13.itm(3)} -attr xrf 18121 -attr oid 267 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {conc#323.itm(0)} -attr vt d
+load net {conc#323.itm(1)} -attr vt d
+load net {conc#323.itm(2)} -attr vt d
+load netBundle {conc#323.itm} 3 {conc#323.itm(0)} {conc#323.itm(1)} {conc#323.itm(2)} -attr xrf 18122 -attr oid 268 -attr vt d -attr @path {/sobel/sobel:core/conc#323.itm}
+load net {conc#324.itm(0)} -attr vt d
+load net {conc#324.itm(1)} -attr vt d
+load net {conc#324.itm(2)} -attr vt d
+load net {conc#324.itm(3)} -attr vt d
+load net {conc#324.itm(4)} -attr vt d
+load netBundle {conc#324.itm} 5 {conc#324.itm(0)} {conc#324.itm(1)} {conc#324.itm(2)} {conc#324.itm(3)} {conc#324.itm(4)} -attr xrf 18123 -attr oid 269 -attr vt d -attr @path {/sobel/sobel:core/conc#324.itm}
+load net {slc(acc.imod#15.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#15.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#15.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#15.sva)#1.itm} 3 {slc(acc.imod#15.sva)#1.itm(0)} {slc(acc.imod#15.sva)#1.itm(1)} {slc(acc.imod#15.sva)#1.itm(2)} -attr xrf 18124 -attr oid 270 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#15.sva)#1.itm}
+load net {FRAME:conc#26.itm(0)} -attr vt d
+load net {FRAME:conc#26.itm(1)} -attr vt d
+load net {FRAME:conc#26.itm(2)} -attr vt d
+load net {FRAME:conc#26.itm(3)} -attr vt d
+load netBundle {FRAME:conc#26.itm} 4 {FRAME:conc#26.itm(0)} {FRAME:conc#26.itm(1)} {FRAME:conc#26.itm(2)} {FRAME:conc#26.itm(3)} -attr xrf 18125 -attr oid 271 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#26.itm}
+load net {FRAME:not#29.itm(0)} -attr vt d
+load net {FRAME:not#29.itm(1)} -attr vt d
+load net {FRAME:not#29.itm(2)} -attr vt d
+load netBundle {FRAME:not#29.itm} 3 {FRAME:not#29.itm(0)} {FRAME:not#29.itm(1)} {FRAME:not#29.itm(2)} -attr xrf 18126 -attr oid 272 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#29.itm}
+load net {slc(acc.imod#15.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#15.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#15.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#15.sva)#2.itm} 3 {slc(acc.imod#15.sva)#2.itm(0)} {slc(acc.imod#15.sva)#2.itm(1)} {slc(acc.imod#15.sva)#2.itm(2)} -attr xrf 18127 -attr oid 273 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#15.sva)#2.itm}
+load net {slc(acc.imod#15.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#15.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#15.sva)#4.itm} 2 {slc(acc.imod#15.sva)#4.itm(0)} {slc(acc.imod#15.sva)#4.itm(1)} -attr xrf 18128 -attr oid 274 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#15.sva)#4.itm}
+load net {FRAME:not#30.itm(0)} -attr vt d
+load net {FRAME:not#30.itm(1)} -attr vt d
+load net {FRAME:not#30.itm(2)} -attr vt d
+load netBundle {FRAME:not#30.itm} 3 {FRAME:not#30.itm(0)} {FRAME:not#30.itm(1)} {FRAME:not#30.itm(2)} -attr xrf 18129 -attr oid 275 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#30.itm}
+load net {slc(intensity:slc(intensity#2.sg1).itm#1).itm(0)} -attr vt d
+load net {slc(intensity:slc(intensity#2.sg1).itm#1).itm(1)} -attr vt d
+load net {slc(intensity:slc(intensity#2.sg1).itm#1).itm(2)} -attr vt d
+load netBundle {slc(intensity:slc(intensity#2.sg1).itm#1).itm} 3 {slc(intensity:slc(intensity#2.sg1).itm#1).itm(0)} {slc(intensity:slc(intensity#2.sg1).itm#1).itm(1)} {slc(intensity:slc(intensity#2.sg1).itm#1).itm(2)} -attr xrf 18130 -attr oid 276 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity:slc(intensity#2.sg1).itm#1).itm}
+load net {conc#325.itm(0)} -attr vt d
+load net {conc#325.itm(1)} -attr vt d
+load net {conc#325.itm(2)} -attr vt d
+load net {conc#325.itm(3)} -attr vt d
+load net {conc#325.itm(4)} -attr vt d
+load netBundle {conc#325.itm} 5 {conc#325.itm(0)} {conc#325.itm(1)} {conc#325.itm(2)} {conc#325.itm(3)} {conc#325.itm(4)} -attr xrf 18131 -attr oid 277 -attr vt d -attr @path {/sobel/sobel:core/conc#325.itm}
+load net {exs.itm(0)} -attr vt d
+load net {exs.itm(1)} -attr vt d
+load net {exs.itm(2)} -attr vt d
+load net {exs.itm(3)} -attr vt d
+load net {exs.itm(4)} -attr vt d
+load net {exs.itm(5)} -attr vt d
+load net {exs.itm(6)} -attr vt d
+load net {exs.itm(7)} -attr vt d
+load net {exs.itm(8)} -attr vt d
+load net {exs.itm(9)} -attr vt d
+load net {exs.itm(10)} -attr vt d
+load netBundle {exs.itm} 11 {exs.itm(0)} {exs.itm(1)} {exs.itm(2)} {exs.itm(3)} {exs.itm(4)} {exs.itm(5)} {exs.itm(6)} {exs.itm(7)} {exs.itm(8)} {exs.itm(9)} {exs.itm(10)} -attr xrf 18132 -attr oid 278 -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {conc#326.itm(0)} -attr vt d
+load net {conc#326.itm(1)} -attr vt d
+load net {conc#326.itm(2)} -attr vt d
+load net {conc#326.itm(3)} -attr vt d
+load net {conc#326.itm(4)} -attr vt d
+load net {conc#326.itm(5)} -attr vt d
+load net {conc#326.itm(6)} -attr vt d
+load net {conc#326.itm(7)} -attr vt d
+load net {conc#326.itm(8)} -attr vt d
+load netBundle {conc#326.itm} 9 {conc#326.itm(0)} {conc#326.itm(1)} {conc#326.itm(2)} {conc#326.itm(3)} {conc#326.itm(4)} {conc#326.itm(5)} {conc#326.itm(6)} {conc#326.itm(7)} {conc#326.itm(8)} -attr xrf 18133 -attr oid 279 -attr vt d -attr @path {/sobel/sobel:core/conc#326.itm}
+load net {FRAME:exs#11.itm(0)} -attr vt d
+load net {FRAME:exs#11.itm(1)} -attr vt d
+load net {FRAME:exs#11.itm(2)} -attr vt d
+load netBundle {FRAME:exs#11.itm} 3 {FRAME:exs#11.itm(0)} {FRAME:exs#11.itm(1)} {FRAME:exs#11.itm(2)} -attr xrf 18134 -attr oid 280 -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#11.itm}
+load net {ACC1:acc.itm(0)} -attr vt d
+load net {ACC1:acc.itm(1)} -attr vt d
+load net {ACC1:acc.itm(2)} -attr vt d
+load net {ACC1:acc.itm(3)} -attr vt d
+load net {ACC1:acc.itm(4)} -attr vt d
+load net {ACC1:acc.itm(5)} -attr vt d
+load net {ACC1:acc.itm(6)} -attr vt d
+load net {ACC1:acc.itm(7)} -attr vt d
+load net {ACC1:acc.itm(8)} -attr vt d
+load net {ACC1:acc.itm(9)} -attr vt d
+load net {ACC1:acc.itm(10)} -attr vt d
+load net {ACC1:acc.itm(11)} -attr vt d
+load net {ACC1:acc.itm(12)} -attr vt d
+load net {ACC1:acc.itm(13)} -attr vt d
+load net {ACC1:acc.itm(14)} -attr vt d
+load net {ACC1:acc.itm(15)} -attr vt d
+load netBundle {ACC1:acc.itm} 16 {ACC1:acc.itm(0)} {ACC1:acc.itm(1)} {ACC1:acc.itm(2)} {ACC1:acc.itm(3)} {ACC1:acc.itm(4)} {ACC1:acc.itm(5)} {ACC1:acc.itm(6)} {ACC1:acc.itm(7)} {ACC1:acc.itm(8)} {ACC1:acc.itm(9)} {ACC1:acc.itm(10)} {ACC1:acc.itm(11)} {ACC1:acc.itm(12)} {ACC1:acc.itm(13)} {ACC1:acc.itm(14)} {ACC1:acc.itm(15)} -attr xrf 18135 -attr oid 281 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc#280.itm(0)} -attr vt d
+load net {ACC1:acc#280.itm(1)} -attr vt d
+load net {ACC1:acc#280.itm(2)} -attr vt d
+load net {ACC1:acc#280.itm(3)} -attr vt d
+load net {ACC1:acc#280.itm(4)} -attr vt d
+load net {ACC1:acc#280.itm(5)} -attr vt d
+load net {ACC1:acc#280.itm(6)} -attr vt d
+load net {ACC1:acc#280.itm(7)} -attr vt d
+load net {ACC1:acc#280.itm(8)} -attr vt d
+load net {ACC1:acc#280.itm(9)} -attr vt d
+load net {ACC1:acc#280.itm(10)} -attr vt d
+load net {ACC1:acc#280.itm(11)} -attr vt d
+load net {ACC1:acc#280.itm(12)} -attr vt d
+load net {ACC1:acc#280.itm(13)} -attr vt d
+load net {ACC1:acc#280.itm(14)} -attr vt d
+load net {ACC1:acc#280.itm(15)} -attr vt d
+load netBundle {ACC1:acc#280.itm} 16 {ACC1:acc#280.itm(0)} {ACC1:acc#280.itm(1)} {ACC1:acc#280.itm(2)} {ACC1:acc#280.itm(3)} {ACC1:acc#280.itm(4)} {ACC1:acc#280.itm(5)} {ACC1:acc#280.itm(6)} {ACC1:acc#280.itm(7)} {ACC1:acc#280.itm(8)} {ACC1:acc#280.itm(9)} {ACC1:acc#280.itm(10)} {ACC1:acc#280.itm(11)} {ACC1:acc#280.itm(12)} {ACC1:acc#280.itm(13)} {ACC1:acc#280.itm(14)} {ACC1:acc#280.itm(15)} -attr xrf 18136 -attr oid 282 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#277.itm(0)} -attr vt d
+load net {ACC1:acc#277.itm(1)} -attr vt d
+load net {ACC1:acc#277.itm(2)} -attr vt d
+load net {ACC1:acc#277.itm(3)} -attr vt d
+load net {ACC1:acc#277.itm(4)} -attr vt d
+load net {ACC1:acc#277.itm(5)} -attr vt d
+load net {ACC1:acc#277.itm(6)} -attr vt d
+load net {ACC1:acc#277.itm(7)} -attr vt d
+load net {ACC1:acc#277.itm(8)} -attr vt d
+load net {ACC1:acc#277.itm(9)} -attr vt d
+load net {ACC1:acc#277.itm(10)} -attr vt d
+load net {ACC1:acc#277.itm(11)} -attr vt d
+load net {ACC1:acc#277.itm(12)} -attr vt d
+load net {ACC1:acc#277.itm(13)} -attr vt d
+load net {ACC1:acc#277.itm(14)} -attr vt d
+load net {ACC1:acc#277.itm(15)} -attr vt d
+load netBundle {ACC1:acc#277.itm} 16 {ACC1:acc#277.itm(0)} {ACC1:acc#277.itm(1)} {ACC1:acc#277.itm(2)} {ACC1:acc#277.itm(3)} {ACC1:acc#277.itm(4)} {ACC1:acc#277.itm(5)} {ACC1:acc#277.itm(6)} {ACC1:acc#277.itm(7)} {ACC1:acc#277.itm(8)} {ACC1:acc#277.itm(9)} {ACC1:acc#277.itm(10)} {ACC1:acc#277.itm(11)} {ACC1:acc#277.itm(12)} {ACC1:acc#277.itm(13)} {ACC1:acc#277.itm(14)} {ACC1:acc#277.itm(15)} -attr xrf 18137 -attr oid 283 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {conc#328.itm(0)} -attr vt d
+load net {conc#328.itm(1)} -attr vt d
+load net {conc#328.itm(2)} -attr vt d
+load net {conc#328.itm(3)} -attr vt d
+load net {conc#328.itm(4)} -attr vt d
+load net {conc#328.itm(5)} -attr vt d
+load net {conc#328.itm(6)} -attr vt d
+load net {conc#328.itm(7)} -attr vt d
+load net {conc#328.itm(8)} -attr vt d
+load net {conc#328.itm(9)} -attr vt d
+load net {conc#328.itm(10)} -attr vt d
+load net {conc#328.itm(11)} -attr vt d
+load net {conc#328.itm(12)} -attr vt d
+load net {conc#328.itm(13)} -attr vt d
+load net {conc#328.itm(14)} -attr vt d
+load net {conc#328.itm(15)} -attr vt d
+load netBundle {conc#328.itm} 16 {conc#328.itm(0)} {conc#328.itm(1)} {conc#328.itm(2)} {conc#328.itm(3)} {conc#328.itm(4)} {conc#328.itm(5)} {conc#328.itm(6)} {conc#328.itm(7)} {conc#328.itm(8)} {conc#328.itm(9)} {conc#328.itm(10)} {conc#328.itm(11)} {conc#328.itm(12)} {conc#328.itm(13)} {conc#328.itm(14)} {conc#328.itm(15)} -attr xrf 18138 -attr oid 284 -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {ACC1-2:exs#24.itm(0)} -attr vt d
+load net {ACC1-2:exs#24.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#24.itm} 2 {ACC1-2:exs#24.itm(0)} {ACC1-2:exs#24.itm(1)} -attr xrf 18139 -attr oid 285 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#24.itm}
+load net {ACC1:acc#274.itm(0)} -attr vt d
+load net {ACC1:acc#274.itm(1)} -attr vt d
+load net {ACC1:acc#274.itm(2)} -attr vt d
+load net {ACC1:acc#274.itm(3)} -attr vt d
+load net {ACC1:acc#274.itm(4)} -attr vt d
+load net {ACC1:acc#274.itm(5)} -attr vt d
+load net {ACC1:acc#274.itm(6)} -attr vt d
+load net {ACC1:acc#274.itm(7)} -attr vt d
+load net {ACC1:acc#274.itm(8)} -attr vt d
+load net {ACC1:acc#274.itm(9)} -attr vt d
+load net {ACC1:acc#274.itm(10)} -attr vt d
+load net {ACC1:acc#274.itm(11)} -attr vt d
+load net {ACC1:acc#274.itm(12)} -attr vt d
+load net {ACC1:acc#274.itm(13)} -attr vt d
+load net {ACC1:acc#274.itm(14)} -attr vt d
+load netBundle {ACC1:acc#274.itm} 15 {ACC1:acc#274.itm(0)} {ACC1:acc#274.itm(1)} {ACC1:acc#274.itm(2)} {ACC1:acc#274.itm(3)} {ACC1:acc#274.itm(4)} {ACC1:acc#274.itm(5)} {ACC1:acc#274.itm(6)} {ACC1:acc#274.itm(7)} {ACC1:acc#274.itm(8)} {ACC1:acc#274.itm(9)} {ACC1:acc#274.itm(10)} {ACC1:acc#274.itm(11)} {ACC1:acc#274.itm(12)} {ACC1:acc#274.itm(13)} {ACC1:acc#274.itm(14)} -attr xrf 18140 -attr oid 286 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#270.itm(0)} -attr vt d
+load net {ACC1:acc#270.itm(1)} -attr vt d
+load net {ACC1:acc#270.itm(2)} -attr vt d
+load net {ACC1:acc#270.itm(3)} -attr vt d
+load net {ACC1:acc#270.itm(4)} -attr vt d
+load net {ACC1:acc#270.itm(5)} -attr vt d
+load net {ACC1:acc#270.itm(6)} -attr vt d
+load net {ACC1:acc#270.itm(7)} -attr vt d
+load net {ACC1:acc#270.itm(8)} -attr vt d
+load net {ACC1:acc#270.itm(9)} -attr vt d
+load net {ACC1:acc#270.itm(10)} -attr vt d
+load net {ACC1:acc#270.itm(11)} -attr vt d
+load net {ACC1:acc#270.itm(12)} -attr vt d
+load net {ACC1:acc#270.itm(13)} -attr vt d
+load netBundle {ACC1:acc#270.itm} 14 {ACC1:acc#270.itm(0)} {ACC1:acc#270.itm(1)} {ACC1:acc#270.itm(2)} {ACC1:acc#270.itm(3)} {ACC1:acc#270.itm(4)} {ACC1:acc#270.itm(5)} {ACC1:acc#270.itm(6)} {ACC1:acc#270.itm(7)} {ACC1:acc#270.itm(8)} {ACC1:acc#270.itm(9)} {ACC1:acc#270.itm(10)} {ACC1:acc#270.itm(11)} {ACC1:acc#270.itm(12)} {ACC1:acc#270.itm(13)} -attr xrf 18141 -attr oid 287 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#267.itm(0)} -attr vt d
+load net {ACC1:acc#267.itm(1)} -attr vt d
+load net {ACC1:acc#267.itm(2)} -attr vt d
+load net {ACC1:acc#267.itm(3)} -attr vt d
+load net {ACC1:acc#267.itm(4)} -attr vt d
+load net {ACC1:acc#267.itm(5)} -attr vt d
+load net {ACC1:acc#267.itm(6)} -attr vt d
+load net {ACC1:acc#267.itm(7)} -attr vt d
+load net {ACC1:acc#267.itm(8)} -attr vt d
+load net {ACC1:acc#267.itm(9)} -attr vt d
+load net {ACC1:acc#267.itm(10)} -attr vt d
+load net {ACC1:acc#267.itm(11)} -attr vt d
+load netBundle {ACC1:acc#267.itm} 12 {ACC1:acc#267.itm(0)} {ACC1:acc#267.itm(1)} {ACC1:acc#267.itm(2)} {ACC1:acc#267.itm(3)} {ACC1:acc#267.itm(4)} {ACC1:acc#267.itm(5)} {ACC1:acc#267.itm(6)} {ACC1:acc#267.itm(7)} {ACC1:acc#267.itm(8)} {ACC1:acc#267.itm(9)} {ACC1:acc#267.itm(10)} {ACC1:acc#267.itm(11)} -attr xrf 18142 -attr oid 288 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:conc#275.itm(0)} -attr vt d
+load net {ACC1:conc#275.itm(1)} -attr vt d
+load net {ACC1:conc#275.itm(2)} -attr vt d
+load net {ACC1:conc#275.itm(3)} -attr vt d
+load net {ACC1:conc#275.itm(4)} -attr vt d
+load net {ACC1:conc#275.itm(5)} -attr vt d
+load net {ACC1:conc#275.itm(6)} -attr vt d
+load net {ACC1:conc#275.itm(7)} -attr vt d
+load net {ACC1:conc#275.itm(8)} -attr vt d
+load net {ACC1:conc#275.itm(9)} -attr vt d
+load net {ACC1:conc#275.itm(10)} -attr vt d
+load netBundle {ACC1:conc#275.itm} 11 {ACC1:conc#275.itm(0)} {ACC1:conc#275.itm(1)} {ACC1:conc#275.itm(2)} {ACC1:conc#275.itm(3)} {ACC1:conc#275.itm(4)} {ACC1:conc#275.itm(5)} {ACC1:conc#275.itm(6)} {ACC1:conc#275.itm(7)} {ACC1:conc#275.itm(8)} {ACC1:conc#275.itm(9)} {ACC1:conc#275.itm(10)} -attr xrf 18143 -attr oid 289 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#275.itm}
+load net {ACC1-2:exs#6.itm(0)} -attr vt d
+load net {ACC1-2:exs#6.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#6.itm} 2 {ACC1-2:exs#6.itm(0)} {ACC1-2:exs#6.itm(1)} -attr xrf 18144 -attr oid 290 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#6.itm}
+load net {ACC1:acc#276.itm(0)} -attr vt d
+load net {ACC1:acc#276.itm(1)} -attr vt d
+load net {ACC1:acc#276.itm(2)} -attr vt d
+load net {ACC1:acc#276.itm(3)} -attr vt d
+load net {ACC1:acc#276.itm(4)} -attr vt d
+load net {ACC1:acc#276.itm(5)} -attr vt d
+load net {ACC1:acc#276.itm(6)} -attr vt d
+load net {ACC1:acc#276.itm(7)} -attr vt d
+load net {ACC1:acc#276.itm(8)} -attr vt d
+load net {ACC1:acc#276.itm(9)} -attr vt d
+load net {ACC1:acc#276.itm(10)} -attr vt d
+load net {ACC1:acc#276.itm(11)} -attr vt d
+load net {ACC1:acc#276.itm(12)} -attr vt d
+load net {ACC1:acc#276.itm(13)} -attr vt d
+load net {ACC1:acc#276.itm(14)} -attr vt d
+load net {ACC1:acc#276.itm(15)} -attr vt d
+load netBundle {ACC1:acc#276.itm} 16 {ACC1:acc#276.itm(0)} {ACC1:acc#276.itm(1)} {ACC1:acc#276.itm(2)} {ACC1:acc#276.itm(3)} {ACC1:acc#276.itm(4)} {ACC1:acc#276.itm(5)} {ACC1:acc#276.itm(6)} {ACC1:acc#276.itm(7)} {ACC1:acc#276.itm(8)} {ACC1:acc#276.itm(9)} {ACC1:acc#276.itm(10)} {ACC1:acc#276.itm(11)} {ACC1:acc#276.itm(12)} {ACC1:acc#276.itm(13)} {ACC1:acc#276.itm(14)} {ACC1:acc#276.itm(15)} -attr xrf 18145 -attr oid 291 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#273.itm(0)} -attr vt d
+load net {ACC1:acc#273.itm(1)} -attr vt d
+load net {ACC1:acc#273.itm(2)} -attr vt d
+load net {ACC1:acc#273.itm(3)} -attr vt d
+load net {ACC1:acc#273.itm(4)} -attr vt d
+load net {ACC1:acc#273.itm(5)} -attr vt d
+load net {ACC1:acc#273.itm(6)} -attr vt d
+load net {ACC1:acc#273.itm(7)} -attr vt d
+load net {ACC1:acc#273.itm(8)} -attr vt d
+load net {ACC1:acc#273.itm(9)} -attr vt d
+load net {ACC1:acc#273.itm(10)} -attr vt d
+load net {ACC1:acc#273.itm(11)} -attr vt d
+load net {ACC1:acc#273.itm(12)} -attr vt d
+load net {ACC1:acc#273.itm(13)} -attr vt d
+load net {ACC1:acc#273.itm(14)} -attr vt d
+load netBundle {ACC1:acc#273.itm} 15 {ACC1:acc#273.itm(0)} {ACC1:acc#273.itm(1)} {ACC1:acc#273.itm(2)} {ACC1:acc#273.itm(3)} {ACC1:acc#273.itm(4)} {ACC1:acc#273.itm(5)} {ACC1:acc#273.itm(6)} {ACC1:acc#273.itm(7)} {ACC1:acc#273.itm(8)} {ACC1:acc#273.itm(9)} {ACC1:acc#273.itm(10)} {ACC1:acc#273.itm(11)} {ACC1:acc#273.itm(12)} {ACC1:acc#273.itm(13)} {ACC1:acc#273.itm(14)} -attr xrf 18146 -attr oid 292 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {conc#329.itm(0)} -attr vt d
+load net {conc#329.itm(1)} -attr vt d
+load net {conc#329.itm(2)} -attr vt d
+load net {conc#329.itm(3)} -attr vt d
+load net {conc#329.itm(4)} -attr vt d
+load net {conc#329.itm(5)} -attr vt d
+load net {conc#329.itm(6)} -attr vt d
+load net {conc#329.itm(7)} -attr vt d
+load net {conc#329.itm(8)} -attr vt d
+load net {conc#329.itm(9)} -attr vt d
+load net {conc#329.itm(10)} -attr vt d
+load net {conc#329.itm(11)} -attr vt d
+load net {conc#329.itm(12)} -attr vt d
+load net {conc#329.itm(13)} -attr vt d
+load netBundle {conc#329.itm} 14 {conc#329.itm(0)} {conc#329.itm(1)} {conc#329.itm(2)} {conc#329.itm(3)} {conc#329.itm(4)} {conc#329.itm(5)} {conc#329.itm(6)} {conc#329.itm(7)} {conc#329.itm(8)} {conc#329.itm(9)} {conc#329.itm(10)} {conc#329.itm(11)} {conc#329.itm(12)} {conc#329.itm(13)} -attr xrf 18147 -attr oid 293 -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1-3:exs#22.itm(0)} -attr vt d
+load net {ACC1-3:exs#22.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#22.itm} 2 {ACC1-3:exs#22.itm(0)} {ACC1-3:exs#22.itm(1)} -attr xrf 18148 -attr oid 294 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#22.itm}
+load net {ACC1:acc#271.itm(0)} -attr vt d
+load net {ACC1:acc#271.itm(1)} -attr vt d
+load net {ACC1:acc#271.itm(2)} -attr vt d
+load net {ACC1:acc#271.itm(3)} -attr vt d
+load net {ACC1:acc#271.itm(4)} -attr vt d
+load net {ACC1:acc#271.itm(5)} -attr vt d
+load net {ACC1:acc#271.itm(6)} -attr vt d
+load net {ACC1:acc#271.itm(7)} -attr vt d
+load net {ACC1:acc#271.itm(8)} -attr vt d
+load net {ACC1:acc#271.itm(9)} -attr vt d
+load net {ACC1:acc#271.itm(10)} -attr vt d
+load net {ACC1:acc#271.itm(11)} -attr vt d
+load net {ACC1:acc#271.itm(12)} -attr vt d
+load netBundle {ACC1:acc#271.itm} 13 {ACC1:acc#271.itm(0)} {ACC1:acc#271.itm(1)} {ACC1:acc#271.itm(2)} {ACC1:acc#271.itm(3)} {ACC1:acc#271.itm(4)} {ACC1:acc#271.itm(5)} {ACC1:acc#271.itm(6)} {ACC1:acc#271.itm(7)} {ACC1:acc#271.itm(8)} {ACC1:acc#271.itm(9)} {ACC1:acc#271.itm(10)} {ACC1:acc#271.itm(11)} {ACC1:acc#271.itm(12)} -attr xrf 18149 -attr oid 295 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#269.itm(0)} -attr vt d
+load net {ACC1:acc#269.itm(1)} -attr vt d
+load net {ACC1:acc#269.itm(2)} -attr vt d
+load net {ACC1:acc#269.itm(3)} -attr vt d
+load net {ACC1:acc#269.itm(4)} -attr vt d
+load net {ACC1:acc#269.itm(5)} -attr vt d
+load net {ACC1:acc#269.itm(6)} -attr vt d
+load net {ACC1:acc#269.itm(7)} -attr vt d
+load net {ACC1:acc#269.itm(8)} -attr vt d
+load net {ACC1:acc#269.itm(9)} -attr vt d
+load net {ACC1:acc#269.itm(10)} -attr vt d
+load net {ACC1:acc#269.itm(11)} -attr vt d
+load netBundle {ACC1:acc#269.itm} 12 {ACC1:acc#269.itm(0)} {ACC1:acc#269.itm(1)} {ACC1:acc#269.itm(2)} {ACC1:acc#269.itm(3)} {ACC1:acc#269.itm(4)} {ACC1:acc#269.itm(5)} {ACC1:acc#269.itm(6)} {ACC1:acc#269.itm(7)} {ACC1:acc#269.itm(8)} {ACC1:acc#269.itm(9)} {ACC1:acc#269.itm(10)} {ACC1:acc#269.itm(11)} -attr xrf 18150 -attr oid 296 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {conc#330.itm(0)} -attr vt d
+load net {conc#330.itm(1)} -attr vt d
+load net {conc#330.itm(2)} -attr vt d
+load net {conc#330.itm(3)} -attr vt d
+load net {conc#330.itm(4)} -attr vt d
+load net {conc#330.itm(5)} -attr vt d
+load net {conc#330.itm(6)} -attr vt d
+load net {conc#330.itm(7)} -attr vt d
+load net {conc#330.itm(8)} -attr vt d
+load net {conc#330.itm(9)} -attr vt d
+load net {conc#330.itm(10)} -attr vt d
+load net {conc#330.itm(11)} -attr vt d
+load netBundle {conc#330.itm} 12 {conc#330.itm(0)} {conc#330.itm(1)} {conc#330.itm(2)} {conc#330.itm(3)} {conc#330.itm(4)} {conc#330.itm(5)} {conc#330.itm(6)} {conc#330.itm(7)} {conc#330.itm(8)} {conc#330.itm(9)} {conc#330.itm(10)} {conc#330.itm(11)} -attr xrf 18151 -attr oid 297 -attr vt d -attr @path {/sobel/sobel:core/conc#330.itm}
+load net {ACC1-3:exs#23.itm(0)} -attr vt d
+load net {ACC1-3:exs#23.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#23.itm} 2 {ACC1-3:exs#23.itm(0)} {ACC1-3:exs#23.itm(1)} -attr xrf 18152 -attr oid 298 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#23.itm}
+load net {ACC1:acc#266.itm(0)} -attr vt d
+load net {ACC1:acc#266.itm(1)} -attr vt d
+load net {ACC1:acc#266.itm(2)} -attr vt d
+load net {ACC1:acc#266.itm(3)} -attr vt d
+load net {ACC1:acc#266.itm(4)} -attr vt d
+load net {ACC1:acc#266.itm(5)} -attr vt d
+load net {ACC1:acc#266.itm(6)} -attr vt d
+load net {ACC1:acc#266.itm(7)} -attr vt d
+load net {ACC1:acc#266.itm(8)} -attr vt d
+load net {ACC1:acc#266.itm(9)} -attr vt d
+load net {ACC1:acc#266.itm(10)} -attr vt d
+load netBundle {ACC1:acc#266.itm} 11 {ACC1:acc#266.itm(0)} {ACC1:acc#266.itm(1)} {ACC1:acc#266.itm(2)} {ACC1:acc#266.itm(3)} {ACC1:acc#266.itm(4)} {ACC1:acc#266.itm(5)} {ACC1:acc#266.itm(6)} {ACC1:acc#266.itm(7)} {ACC1:acc#266.itm(8)} {ACC1:acc#266.itm(9)} {ACC1:acc#266.itm(10)} -attr xrf 18153 -attr oid 299 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#263.itm(0)} -attr vt d
+load net {ACC1:acc#263.itm(1)} -attr vt d
+load net {ACC1:acc#263.itm(2)} -attr vt d
+load net {ACC1:acc#263.itm(3)} -attr vt d
+load net {ACC1:acc#263.itm(4)} -attr vt d
+load net {ACC1:acc#263.itm(5)} -attr vt d
+load net {ACC1:acc#263.itm(6)} -attr vt d
+load net {ACC1:acc#263.itm(7)} -attr vt d
+load net {ACC1:acc#263.itm(8)} -attr vt d
+load net {ACC1:acc#263.itm(9)} -attr vt d
+load netBundle {ACC1:acc#263.itm} 10 {ACC1:acc#263.itm(0)} {ACC1:acc#263.itm(1)} {ACC1:acc#263.itm(2)} {ACC1:acc#263.itm(3)} {ACC1:acc#263.itm(4)} {ACC1:acc#263.itm(5)} {ACC1:acc#263.itm(6)} {ACC1:acc#263.itm(7)} {ACC1:acc#263.itm(8)} {ACC1:acc#263.itm(9)} -attr xrf 18154 -attr oid 300 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:conc#274.itm(0)} -attr vt d
+load net {ACC1:conc#274.itm(1)} -attr vt d
+load net {ACC1:conc#274.itm(2)} -attr vt d
+load net {ACC1:conc#274.itm(3)} -attr vt d
+load net {ACC1:conc#274.itm(4)} -attr vt d
+load net {ACC1:conc#274.itm(5)} -attr vt d
+load net {ACC1:conc#274.itm(6)} -attr vt d
+load net {ACC1:conc#274.itm(7)} -attr vt d
+load net {ACC1:conc#274.itm(8)} -attr vt d
+load netBundle {ACC1:conc#274.itm} 9 {ACC1:conc#274.itm(0)} {ACC1:conc#274.itm(1)} {ACC1:conc#274.itm(2)} {ACC1:conc#274.itm(3)} {ACC1:conc#274.itm(4)} {ACC1:conc#274.itm(5)} {ACC1:conc#274.itm(6)} {ACC1:conc#274.itm(7)} {ACC1:conc#274.itm(8)} -attr xrf 18155 -attr oid 301 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#274.itm}
+load net {ACC1-2:exs#5.itm(0)} -attr vt d
+load net {ACC1-2:exs#5.itm(1)} -attr vt d
+load netBundle {ACC1-2:exs#5.itm} 2 {ACC1-2:exs#5.itm(0)} {ACC1-2:exs#5.itm(1)} -attr xrf 18156 -attr oid 302 -attr vt d -attr @path {/sobel/sobel:core/ACC1-2:exs#5.itm}
+load net {ACC1:acc#260.itm(0)} -attr vt d
+load net {ACC1:acc#260.itm(1)} -attr vt d
+load net {ACC1:acc#260.itm(2)} -attr vt d
+load net {ACC1:acc#260.itm(3)} -attr vt d
+load net {ACC1:acc#260.itm(4)} -attr vt d
+load net {ACC1:acc#260.itm(5)} -attr vt d
+load net {ACC1:acc#260.itm(6)} -attr vt d
+load net {ACC1:acc#260.itm(7)} -attr vt d
+load netBundle {ACC1:acc#260.itm} 8 {ACC1:acc#260.itm(0)} {ACC1:acc#260.itm(1)} {ACC1:acc#260.itm(2)} {ACC1:acc#260.itm(3)} {ACC1:acc#260.itm(4)} {ACC1:acc#260.itm(5)} {ACC1:acc#260.itm(6)} {ACC1:acc#260.itm(7)} -attr xrf 18157 -attr oid 303 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#256.itm(0)} -attr vt d
+load net {ACC1:acc#256.itm(1)} -attr vt d
+load net {ACC1:acc#256.itm(2)} -attr vt d
+load net {ACC1:acc#256.itm(3)} -attr vt d
+load net {ACC1:acc#256.itm(4)} -attr vt d
+load net {ACC1:acc#256.itm(5)} -attr vt d
+load net {ACC1:acc#256.itm(6)} -attr vt d
+load netBundle {ACC1:acc#256.itm} 7 {ACC1:acc#256.itm(0)} {ACC1:acc#256.itm(1)} {ACC1:acc#256.itm(2)} {ACC1:acc#256.itm(3)} {ACC1:acc#256.itm(4)} {ACC1:acc#256.itm(5)} {ACC1:acc#256.itm(6)} -attr xrf 18158 -attr oid 304 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:conc#254.itm(0)} -attr vt d
+load net {ACC1:conc#254.itm(1)} -attr vt d
+load net {ACC1:conc#254.itm(2)} -attr vt d
+load net {ACC1:conc#254.itm(3)} -attr vt d
+load net {ACC1:conc#254.itm(4)} -attr vt d
+load net {ACC1:conc#254.itm(5)} -attr vt d
+load net {ACC1:conc#254.itm(6)} -attr vt d
+load net {ACC1:conc#254.itm(7)} -attr vt d
+load net {ACC1:conc#254.itm(8)} -attr vt d
+load net {ACC1:conc#254.itm(9)} -attr vt d
+load net {ACC1:conc#254.itm(10)} -attr vt d
+load net {ACC1:conc#254.itm(11)} -attr vt d
+load net {ACC1:conc#254.itm(12)} -attr vt d
+load net {ACC1:conc#254.itm(13)} -attr vt d
+load net {ACC1:conc#254.itm(14)} -attr vt d
+load netBundle {ACC1:conc#254.itm} 15 {ACC1:conc#254.itm(0)} {ACC1:conc#254.itm(1)} {ACC1:conc#254.itm(2)} {ACC1:conc#254.itm(3)} {ACC1:conc#254.itm(4)} {ACC1:conc#254.itm(5)} {ACC1:conc#254.itm(6)} {ACC1:conc#254.itm(7)} {ACC1:conc#254.itm(8)} {ACC1:conc#254.itm(9)} {ACC1:conc#254.itm(10)} {ACC1:conc#254.itm(11)} {ACC1:conc#254.itm(12)} {ACC1:conc#254.itm(13)} {ACC1:conc#254.itm(14)} -attr xrf 18159 -attr oid 305 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:acc#189.itm(0)} -attr vt d
+load net {ACC1:acc#189.itm(1)} -attr vt d
+load net {ACC1:acc#189.itm(2)} -attr vt d
+load net {ACC1:acc#189.itm(3)} -attr vt d
+load net {ACC1:acc#189.itm(4)} -attr vt d
+load net {ACC1:acc#189.itm(5)} -attr vt d
+load netBundle {ACC1:acc#189.itm} 6 {ACC1:acc#189.itm(0)} {ACC1:acc#189.itm(1)} {ACC1:acc#189.itm(2)} {ACC1:acc#189.itm(3)} {ACC1:acc#189.itm(4)} {ACC1:acc#189.itm(5)} -attr xrf 18160 -attr oid 306 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {conc#331.itm(0)} -attr vt d
+load net {conc#331.itm(1)} -attr vt d
+load net {conc#331.itm(2)} -attr vt d
+load net {conc#331.itm(3)} -attr vt d
+load net {conc#331.itm(4)} -attr vt d
+load net {conc#331.itm(5)} -attr vt d
+load netBundle {conc#331.itm} 6 {conc#331.itm(0)} {conc#331.itm(1)} {conc#331.itm(2)} {conc#331.itm(3)} {conc#331.itm(4)} {conc#331.itm(5)} -attr xrf 18161 -attr oid 307 -attr vt d -attr @path {/sobel/sobel:core/conc#331.itm}
+load net {ACC1:slc#37.itm(0)} -attr vt d
+load net {ACC1:slc#37.itm(1)} -attr vt d
+load net {ACC1:slc#37.itm(2)} -attr vt d
+load net {ACC1:slc#37.itm(3)} -attr vt d
+load net {ACC1:slc#37.itm(4)} -attr vt d
+load netBundle {ACC1:slc#37.itm} 5 {ACC1:slc#37.itm(0)} {ACC1:slc#37.itm(1)} {ACC1:slc#37.itm(2)} {ACC1:slc#37.itm(3)} {ACC1:slc#37.itm(4)} -attr xrf 18162 -attr oid 308 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#37.itm}
+load net {ACC1:acc#188.itm(0)} -attr vt d
+load net {ACC1:acc#188.itm(1)} -attr vt d
+load net {ACC1:acc#188.itm(2)} -attr vt d
+load net {ACC1:acc#188.itm(3)} -attr vt d
+load net {ACC1:acc#188.itm(4)} -attr vt d
+load net {ACC1:acc#188.itm(5)} -attr vt d
+load netBundle {ACC1:acc#188.itm} 6 {ACC1:acc#188.itm(0)} {ACC1:acc#188.itm(1)} {ACC1:acc#188.itm(2)} {ACC1:acc#188.itm(3)} {ACC1:acc#188.itm(4)} {ACC1:acc#188.itm(5)} -attr xrf 18163 -attr oid 309 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load net {conc#332.itm(0)} -attr vt d
+load net {conc#332.itm(1)} -attr vt d
+load net {conc#332.itm(2)} -attr vt d
+load net {conc#332.itm(3)} -attr vt d
+load net {conc#332.itm(4)} -attr vt d
+load netBundle {conc#332.itm} 5 {conc#332.itm(0)} {conc#332.itm(1)} {conc#332.itm(2)} {conc#332.itm(3)} {conc#332.itm(4)} -attr xrf 18164 -attr oid 310 -attr vt d -attr @path {/sobel/sobel:core/conc#332.itm}
+load net {ACC1:slc#36.itm(0)} -attr vt d
+load net {ACC1:slc#36.itm(1)} -attr vt d
+load net {ACC1:slc#36.itm(2)} -attr vt d
+load net {ACC1:slc#36.itm(3)} -attr vt d
+load netBundle {ACC1:slc#36.itm} 4 {ACC1:slc#36.itm(0)} {ACC1:slc#36.itm(1)} {ACC1:slc#36.itm(2)} {ACC1:slc#36.itm(3)} -attr xrf 18165 -attr oid 311 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#36.itm}
+load net {ACC1:acc#187.itm(0)} -attr vt d
+load net {ACC1:acc#187.itm(1)} -attr vt d
+load net {ACC1:acc#187.itm(2)} -attr vt d
+load net {ACC1:acc#187.itm(3)} -attr vt d
+load net {ACC1:acc#187.itm(4)} -attr vt d
+load netBundle {ACC1:acc#187.itm} 5 {ACC1:acc#187.itm(0)} {ACC1:acc#187.itm(1)} {ACC1:acc#187.itm(2)} {ACC1:acc#187.itm(3)} {ACC1:acc#187.itm(4)} -attr xrf 18166 -attr oid 312 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load net {conc#333.itm(0)} -attr vt d
+load net {conc#333.itm(1)} -attr vt d
+load net {conc#333.itm(2)} -attr vt d
+load net {conc#333.itm(3)} -attr vt d
+load netBundle {conc#333.itm} 4 {conc#333.itm(0)} {conc#333.itm(1)} {conc#333.itm(2)} {conc#333.itm(3)} -attr xrf 18167 -attr oid 313 -attr vt d -attr @path {/sobel/sobel:core/conc#333.itm}
+load net {ACC1:slc#34.itm(0)} -attr vt d
+load net {ACC1:slc#34.itm(1)} -attr vt d
+load net {ACC1:slc#34.itm(2)} -attr vt d
+load netBundle {ACC1:slc#34.itm} 3 {ACC1:slc#34.itm(0)} {ACC1:slc#34.itm(1)} {ACC1:slc#34.itm(2)} -attr xrf 18168 -attr oid 314 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#185.itm(0)} -attr vt d
+load net {ACC1:acc#185.itm(1)} -attr vt d
+load net {ACC1:acc#185.itm(2)} -attr vt d
+load net {ACC1:acc#185.itm(3)} -attr vt d
+load netBundle {ACC1:acc#185.itm} 4 {ACC1:acc#185.itm(0)} {ACC1:acc#185.itm(1)} {ACC1:acc#185.itm(2)} {ACC1:acc#185.itm(3)} -attr xrf 18169 -attr oid 315 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {conc#334.itm(0)} -attr vt d
+load net {conc#334.itm(1)} -attr vt d
+load net {conc#334.itm(2)} -attr vt d
+load netBundle {conc#334.itm} 3 {conc#334.itm(0)} {conc#334.itm(1)} {conc#334.itm(2)} -attr xrf 18170 -attr oid 316 -attr vt d -attr @path {/sobel/sobel:core/conc#334.itm}
+load net {ACC1:slc#30.itm(0)} -attr vt d
+load net {ACC1:slc#30.itm(1)} -attr vt d
+load netBundle {ACC1:slc#30.itm} 2 {ACC1:slc#30.itm(0)} {ACC1:slc#30.itm(1)} -attr xrf 18171 -attr oid 317 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#30.itm}
+load net {ACC1:acc#181.itm(0)} -attr vt d
+load net {ACC1:acc#181.itm(1)} -attr vt d
+load net {ACC1:acc#181.itm(2)} -attr vt d
+load netBundle {ACC1:acc#181.itm} 3 {ACC1:acc#181.itm(0)} {ACC1:acc#181.itm(1)} {ACC1:acc#181.itm(2)} -attr xrf 18172 -attr oid 318 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181.itm}
+load net {conc#335.itm(0)} -attr vt d
+load net {conc#335.itm(1)} -attr vt d
+load netBundle {conc#335.itm} 2 {conc#335.itm(0)} {conc#335.itm(1)} -attr xrf 18173 -attr oid 319 -attr vt d -attr @path {/sobel/sobel:core/conc#335.itm}
+load net {conc#336.itm(0)} -attr vt d
+load net {conc#336.itm(1)} -attr vt d
+load netBundle {conc#336.itm} 2 {conc#336.itm(0)} {conc#336.itm(1)} -attr xrf 18174 -attr oid 320 -attr vt d -attr @path {/sobel/sobel:core/conc#336.itm}
+load net {ACC1:conc#353.itm(0)} -attr vt d
+load net {ACC1:conc#353.itm(1)} -attr vt d
+load netBundle {ACC1:conc#353.itm} 2 {ACC1:conc#353.itm(0)} {ACC1:conc#353.itm(1)} -attr xrf 18175 -attr oid 321 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#353.itm}
+load net {ACC1:conc#357.itm(0)} -attr vt d
+load net {ACC1:conc#357.itm(1)} -attr vt d
+load net {ACC1:conc#357.itm(2)} -attr vt d
+load netBundle {ACC1:conc#357.itm} 3 {ACC1:conc#357.itm(0)} {ACC1:conc#357.itm(1)} {ACC1:conc#357.itm(2)} -attr xrf 18176 -attr oid 322 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#357.itm}
+load net {ACC1:slc#33.itm(0)} -attr vt d
+load net {ACC1:slc#33.itm(1)} -attr vt d
+load netBundle {ACC1:slc#33.itm} 2 {ACC1:slc#33.itm(0)} {ACC1:slc#33.itm(1)} -attr xrf 18177 -attr oid 323 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#184.itm(0)} -attr vt d
+load net {ACC1:acc#184.itm(1)} -attr vt d
+load net {ACC1:acc#184.itm(2)} -attr vt d
+load netBundle {ACC1:acc#184.itm} 3 {ACC1:acc#184.itm(0)} {ACC1:acc#184.itm(1)} {ACC1:acc#184.itm(2)} -attr xrf 18178 -attr oid 324 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load net {conc#337.itm(0)} -attr vt d
+load net {conc#337.itm(1)} -attr vt d
+load netBundle {conc#337.itm} 2 {conc#337.itm(0)} {conc#337.itm(1)} -attr xrf 18179 -attr oid 325 -attr vt d -attr @path {/sobel/sobel:core/conc#337.itm}
+load net {ACC1:conc#351.itm(0)} -attr vt d
+load net {ACC1:conc#351.itm(1)} -attr vt d
+load netBundle {ACC1:conc#351.itm} 2 {ACC1:conc#351.itm(0)} {ACC1:conc#351.itm(1)} -attr xrf 18180 -attr oid 326 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#351.itm}
+load net {ACC1:conc#359.itm(0)} -attr vt d
+load net {ACC1:conc#359.itm(1)} -attr vt d
+load net {ACC1:conc#359.itm(2)} -attr vt d
+load net {ACC1:conc#359.itm(3)} -attr vt d
+load netBundle {ACC1:conc#359.itm} 4 {ACC1:conc#359.itm(0)} {ACC1:conc#359.itm(1)} {ACC1:conc#359.itm(2)} {ACC1:conc#359.itm(3)} -attr xrf 18181 -attr oid 327 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#359.itm}
+load net {ACC1:slc#35.itm(0)} -attr vt d
+load net {ACC1:slc#35.itm(1)} -attr vt d
+load net {ACC1:slc#35.itm(2)} -attr vt d
+load netBundle {ACC1:slc#35.itm} 3 {ACC1:slc#35.itm(0)} {ACC1:slc#35.itm(1)} {ACC1:slc#35.itm(2)} -attr xrf 18182 -attr oid 328 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#35.itm}
+load net {ACC1:acc#186.itm(0)} -attr vt d
+load net {ACC1:acc#186.itm(1)} -attr vt d
+load net {ACC1:acc#186.itm(2)} -attr vt d
+load net {ACC1:acc#186.itm(3)} -attr vt d
+load netBundle {ACC1:acc#186.itm} 4 {ACC1:acc#186.itm(0)} {ACC1:acc#186.itm(1)} {ACC1:acc#186.itm(2)} {ACC1:acc#186.itm(3)} -attr xrf 18183 -attr oid 329 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186.itm}
+load net {conc#338.itm(0)} -attr vt d
+load net {conc#338.itm(1)} -attr vt d
+load net {conc#338.itm(2)} -attr vt d
+load netBundle {conc#338.itm} 3 {conc#338.itm(0)} {conc#338.itm(1)} {conc#338.itm(2)} -attr xrf 18184 -attr oid 330 -attr vt d -attr @path {/sobel/sobel:core/conc#338.itm}
+load net {ACC1:slc#32.itm(0)} -attr vt d
+load net {ACC1:slc#32.itm(1)} -attr vt d
+load netBundle {ACC1:slc#32.itm} 2 {ACC1:slc#32.itm(0)} {ACC1:slc#32.itm(1)} -attr xrf 18185 -attr oid 331 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#32.itm}
+load net {ACC1:acc#183.itm(0)} -attr vt d
+load net {ACC1:acc#183.itm(1)} -attr vt d
+load net {ACC1:acc#183.itm(2)} -attr vt d
+load netBundle {ACC1:acc#183.itm} 3 {ACC1:acc#183.itm(0)} {ACC1:acc#183.itm(1)} {ACC1:acc#183.itm(2)} -attr xrf 18186 -attr oid 332 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load net {conc#339.itm(0)} -attr vt d
+load net {conc#339.itm(1)} -attr vt d
+load netBundle {conc#339.itm} 2 {conc#339.itm(0)} {conc#339.itm(1)} -attr xrf 18187 -attr oid 333 -attr vt d -attr @path {/sobel/sobel:core/conc#339.itm}
+load net {ACC1:conc#349.itm(0)} -attr vt d
+load net {ACC1:conc#349.itm(1)} -attr vt d
+load netBundle {ACC1:conc#349.itm} 2 {ACC1:conc#349.itm(0)} {ACC1:conc#349.itm(1)} -attr xrf 18188 -attr oid 334 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#349.itm}
+load net {ACC1:conc#355.itm(0)} -attr vt d
+load net {ACC1:conc#355.itm(1)} -attr vt d
+load net {ACC1:conc#355.itm(2)} -attr vt d
+load netBundle {ACC1:conc#355.itm} 3 {ACC1:conc#355.itm(0)} {ACC1:conc#355.itm(1)} {ACC1:conc#355.itm(2)} -attr xrf 18189 -attr oid 335 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#355.itm}
+load net {ACC1:slc#31.itm(0)} -attr vt d
+load net {ACC1:slc#31.itm(1)} -attr vt d
+load netBundle {ACC1:slc#31.itm} 2 {ACC1:slc#31.itm(0)} {ACC1:slc#31.itm(1)} -attr xrf 18190 -attr oid 336 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#31.itm}
+load net {ACC1:acc#182.itm(0)} -attr vt d
+load net {ACC1:acc#182.itm(1)} -attr vt d
+load net {ACC1:acc#182.itm(2)} -attr vt d
+load netBundle {ACC1:acc#182.itm} 3 {ACC1:acc#182.itm(0)} {ACC1:acc#182.itm(1)} {ACC1:acc#182.itm(2)} -attr xrf 18191 -attr oid 337 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182.itm}
+load net {conc#340.itm(0)} -attr vt d
+load net {conc#340.itm(1)} -attr vt d
+load netBundle {conc#340.itm} 2 {conc#340.itm(0)} {conc#340.itm(1)} -attr xrf 18192 -attr oid 338 -attr vt d -attr @path {/sobel/sobel:core/conc#340.itm}
+load net {ACC1:conc#347.itm(0)} -attr vt d
+load net {ACC1:conc#347.itm(1)} -attr vt d
+load netBundle {ACC1:conc#347.itm} 2 {ACC1:conc#347.itm(0)} {ACC1:conc#347.itm(1)} -attr xrf 18193 -attr oid 339 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#347.itm}
+load net {conc#341.itm(0)} -attr vt d
+load net {conc#341.itm(1)} -attr vt d
+load net {conc#341.itm(2)} -attr vt d
+load net {conc#341.itm(3)} -attr vt d
+load net {conc#341.itm(4)} -attr vt d
+load net {conc#341.itm(5)} -attr vt d
+load netBundle {conc#341.itm} 6 {conc#341.itm(0)} {conc#341.itm(1)} {conc#341.itm(2)} {conc#341.itm(3)} {conc#341.itm(4)} {conc#341.itm(5)} -attr xrf 18194 -attr oid 340 -attr vt d -attr @path {/sobel/sobel:core/conc#341.itm}
+load net {ACC1:acc#153.itm(0)} -attr vt d
+load net {ACC1:acc#153.itm(1)} -attr vt d
+load net {ACC1:acc#153.itm(2)} -attr vt d
+load net {ACC1:acc#153.itm(3)} -attr vt d
+load net {ACC1:acc#153.itm(4)} -attr vt d
+load net {ACC1:acc#153.itm(5)} -attr vt d
+load net {ACC1:acc#153.itm(6)} -attr vt d
+load net {ACC1:acc#153.itm(7)} -attr vt d
+load net {ACC1:acc#153.itm(8)} -attr vt d
+load net {ACC1:acc#153.itm(9)} -attr vt d
+load net {ACC1:acc#153.itm(10)} -attr vt d
+load net {ACC1:acc#153.itm(11)} -attr vt d
+load net {ACC1:acc#153.itm(12)} -attr vt d
+load net {ACC1:acc#153.itm(13)} -attr vt d
+load net {ACC1:acc#153.itm(14)} -attr vt d
+load net {ACC1:acc#153.itm(15)} -attr vt d
+load net {ACC1:acc#153.itm(16)} -attr vt d
+load netBundle {ACC1:acc#153.itm} 17 {ACC1:acc#153.itm(0)} {ACC1:acc#153.itm(1)} {ACC1:acc#153.itm(2)} {ACC1:acc#153.itm(3)} {ACC1:acc#153.itm(4)} {ACC1:acc#153.itm(5)} {ACC1:acc#153.itm(6)} {ACC1:acc#153.itm(7)} {ACC1:acc#153.itm(8)} {ACC1:acc#153.itm(9)} {ACC1:acc#153.itm(10)} {ACC1:acc#153.itm(11)} {ACC1:acc#153.itm(12)} {ACC1:acc#153.itm(13)} {ACC1:acc#153.itm(14)} {ACC1:acc#153.itm(15)} {ACC1:acc#153.itm(16)} -attr xrf 18195 -attr oid 341 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:exs#56.itm(0)} -attr vt d
+load net {ACC1:exs#56.itm(1)} -attr vt d
+load net {ACC1:exs#56.itm(2)} -attr vt d
+load net {ACC1:exs#56.itm(3)} -attr vt d
+load net {ACC1:exs#56.itm(4)} -attr vt d
+load net {ACC1:exs#56.itm(5)} -attr vt d
+load net {ACC1:exs#56.itm(6)} -attr vt d
+load net {ACC1:exs#56.itm(7)} -attr vt d
+load net {ACC1:exs#56.itm(8)} -attr vt d
+load net {ACC1:exs#56.itm(9)} -attr vt d
+load net {ACC1:exs#56.itm(10)} -attr vt d
+load net {ACC1:exs#56.itm(11)} -attr vt d
+load net {ACC1:exs#56.itm(12)} -attr vt d
+load net {ACC1:exs#56.itm(13)} -attr vt d
+load net {ACC1:exs#56.itm(14)} -attr vt d
+load net {ACC1:exs#56.itm(15)} -attr vt d
+load netBundle {ACC1:exs#56.itm} 16 {ACC1:exs#56.itm(0)} {ACC1:exs#56.itm(1)} {ACC1:exs#56.itm(2)} {ACC1:exs#56.itm(3)} {ACC1:exs#56.itm(4)} {ACC1:exs#56.itm(5)} {ACC1:exs#56.itm(6)} {ACC1:exs#56.itm(7)} {ACC1:exs#56.itm(8)} {ACC1:exs#56.itm(9)} {ACC1:exs#56.itm(10)} {ACC1:exs#56.itm(11)} {ACC1:exs#56.itm(12)} {ACC1:exs#56.itm(13)} {ACC1:exs#56.itm(14)} {ACC1:exs#56.itm(15)} -attr xrf 18196 -attr oid 342 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {slc(regs.regs(0).sva#4).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#4).itm} 10 {slc(regs.regs(0).sva#4).itm(0)} {slc(regs.regs(0).sva#4).itm(1)} {slc(regs.regs(0).sva#4).itm(2)} {slc(regs.regs(0).sva#4).itm(3)} {slc(regs.regs(0).sva#4).itm(4)} {slc(regs.regs(0).sva#4).itm(5)} {slc(regs.regs(0).sva#4).itm(6)} {slc(regs.regs(0).sva#4).itm(7)} {slc(regs.regs(0).sva#4).itm(8)} {slc(regs.regs(0).sva#4).itm(9)} -attr xrf 18197 -attr oid 343 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:exs#57.itm(0)} -attr vt d
+load net {ACC1:exs#57.itm(1)} -attr vt d
+load net {ACC1:exs#57.itm(2)} -attr vt d
+load net {ACC1:exs#57.itm(3)} -attr vt d
+load net {ACC1:exs#57.itm(4)} -attr vt d
+load net {ACC1:exs#57.itm(5)} -attr vt d
+load net {ACC1:exs#57.itm(6)} -attr vt d
+load net {ACC1:exs#57.itm(7)} -attr vt d
+load net {ACC1:exs#57.itm(8)} -attr vt d
+load net {ACC1:exs#57.itm(9)} -attr vt d
+load net {ACC1:exs#57.itm(10)} -attr vt d
+load net {ACC1:exs#57.itm(11)} -attr vt d
+load net {ACC1:exs#57.itm(12)} -attr vt d
+load net {ACC1:exs#57.itm(13)} -attr vt d
+load net {ACC1:exs#57.itm(14)} -attr vt d
+load net {ACC1:exs#57.itm(15)} -attr vt d
+load netBundle {ACC1:exs#57.itm} 16 {ACC1:exs#57.itm(0)} {ACC1:exs#57.itm(1)} {ACC1:exs#57.itm(2)} {ACC1:exs#57.itm(3)} {ACC1:exs#57.itm(4)} {ACC1:exs#57.itm(5)} {ACC1:exs#57.itm(6)} {ACC1:exs#57.itm(7)} {ACC1:exs#57.itm(8)} {ACC1:exs#57.itm(9)} {ACC1:exs#57.itm(10)} {ACC1:exs#57.itm(11)} {ACC1:exs#57.itm(12)} {ACC1:exs#57.itm(13)} {ACC1:exs#57.itm(14)} {ACC1:exs#57.itm(15)} -attr xrf 18198 -attr oid 344 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {slc(regs.regs(0).sva#5).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#5).itm} 10 {slc(regs.regs(0).sva#5).itm(0)} {slc(regs.regs(0).sva#5).itm(1)} {slc(regs.regs(0).sva#5).itm(2)} {slc(regs.regs(0).sva#5).itm(3)} {slc(regs.regs(0).sva#5).itm(4)} {slc(regs.regs(0).sva#5).itm(5)} {slc(regs.regs(0).sva#5).itm(6)} {slc(regs.regs(0).sva#5).itm(7)} {slc(regs.regs(0).sva#5).itm(8)} {slc(regs.regs(0).sva#5).itm(9)} -attr xrf 18199 -attr oid 345 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {ACC1:exs.itm(0)} -attr vt d
+load net {ACC1:exs.itm(1)} -attr vt d
+load net {ACC1:exs.itm(2)} -attr vt d
+load net {ACC1:exs.itm(3)} -attr vt d
+load net {ACC1:exs.itm(4)} -attr vt d
+load net {ACC1:exs.itm(5)} -attr vt d
+load net {ACC1:exs.itm(6)} -attr vt d
+load net {ACC1:exs.itm(7)} -attr vt d
+load net {ACC1:exs.itm(8)} -attr vt d
+load net {ACC1:exs.itm(9)} -attr vt d
+load net {ACC1:exs.itm(10)} -attr vt d
+load net {ACC1:exs.itm(11)} -attr vt d
+load net {ACC1:exs.itm(12)} -attr vt d
+load net {ACC1:exs.itm(13)} -attr vt d
+load net {ACC1:exs.itm(14)} -attr vt d
+load net {ACC1:exs.itm(15)} -attr vt d
+load netBundle {ACC1:exs.itm} 16 {ACC1:exs.itm(0)} {ACC1:exs.itm(1)} {ACC1:exs.itm(2)} {ACC1:exs.itm(3)} {ACC1:exs.itm(4)} {ACC1:exs.itm(5)} {ACC1:exs.itm(6)} {ACC1:exs.itm(7)} {ACC1:exs.itm(8)} {ACC1:exs.itm(9)} {ACC1:exs.itm(10)} {ACC1:exs.itm(11)} {ACC1:exs.itm(12)} {ACC1:exs.itm(13)} {ACC1:exs.itm(14)} {ACC1:exs.itm(15)} -attr xrf 18200 -attr oid 346 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {slc(regs.regs(0).sva#6).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#6).itm} 10 {slc(regs.regs(0).sva#6).itm(0)} {slc(regs.regs(0).sva#6).itm(1)} {slc(regs.regs(0).sva#6).itm(2)} {slc(regs.regs(0).sva#6).itm(3)} {slc(regs.regs(0).sva#6).itm(4)} {slc(regs.regs(0).sva#6).itm(5)} {slc(regs.regs(0).sva#6).itm(6)} {slc(regs.regs(0).sva#6).itm(7)} {slc(regs.regs(0).sva#6).itm(8)} {slc(regs.regs(0).sva#6).itm(9)} -attr xrf 18201 -attr oid 347 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:acc#165.itm(0)} -attr vt d
+load net {ACC1:acc#165.itm(1)} -attr vt d
+load net {ACC1:acc#165.itm(2)} -attr vt d
+load net {ACC1:acc#165.itm(3)} -attr vt d
+load net {ACC1:acc#165.itm(4)} -attr vt d
+load net {ACC1:acc#165.itm(5)} -attr vt d
+load net {ACC1:acc#165.itm(6)} -attr vt d
+load net {ACC1:acc#165.itm(7)} -attr vt d
+load net {ACC1:acc#165.itm(8)} -attr vt d
+load net {ACC1:acc#165.itm(9)} -attr vt d
+load net {ACC1:acc#165.itm(10)} -attr vt d
+load net {ACC1:acc#165.itm(11)} -attr vt d
+load net {ACC1:acc#165.itm(12)} -attr vt d
+load net {ACC1:acc#165.itm(13)} -attr vt d
+load net {ACC1:acc#165.itm(14)} -attr vt d
+load net {ACC1:acc#165.itm(15)} -attr vt d
+load net {ACC1:acc#165.itm(16)} -attr vt d
+load netBundle {ACC1:acc#165.itm} 17 {ACC1:acc#165.itm(0)} {ACC1:acc#165.itm(1)} {ACC1:acc#165.itm(2)} {ACC1:acc#165.itm(3)} {ACC1:acc#165.itm(4)} {ACC1:acc#165.itm(5)} {ACC1:acc#165.itm(6)} {ACC1:acc#165.itm(7)} {ACC1:acc#165.itm(8)} {ACC1:acc#165.itm(9)} {ACC1:acc#165.itm(10)} {ACC1:acc#165.itm(11)} {ACC1:acc#165.itm(12)} {ACC1:acc#165.itm(13)} {ACC1:acc#165.itm(14)} {ACC1:acc#165.itm(15)} {ACC1:acc#165.itm(16)} -attr xrf 18202 -attr oid 348 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:exs#68.itm(0)} -attr vt d
+load net {ACC1:exs#68.itm(1)} -attr vt d
+load net {ACC1:exs#68.itm(2)} -attr vt d
+load net {ACC1:exs#68.itm(3)} -attr vt d
+load net {ACC1:exs#68.itm(4)} -attr vt d
+load net {ACC1:exs#68.itm(5)} -attr vt d
+load net {ACC1:exs#68.itm(6)} -attr vt d
+load net {ACC1:exs#68.itm(7)} -attr vt d
+load net {ACC1:exs#68.itm(8)} -attr vt d
+load net {ACC1:exs#68.itm(9)} -attr vt d
+load net {ACC1:exs#68.itm(10)} -attr vt d
+load net {ACC1:exs#68.itm(11)} -attr vt d
+load net {ACC1:exs#68.itm(12)} -attr vt d
+load net {ACC1:exs#68.itm(13)} -attr vt d
+load net {ACC1:exs#68.itm(14)} -attr vt d
+load net {ACC1:exs#68.itm(15)} -attr vt d
+load netBundle {ACC1:exs#68.itm} 16 {ACC1:exs#68.itm(0)} {ACC1:exs#68.itm(1)} {ACC1:exs#68.itm(2)} {ACC1:exs#68.itm(3)} {ACC1:exs#68.itm(4)} {ACC1:exs#68.itm(5)} {ACC1:exs#68.itm(6)} {ACC1:exs#68.itm(7)} {ACC1:exs#68.itm(8)} {ACC1:exs#68.itm(9)} {ACC1:exs#68.itm(10)} {ACC1:exs#68.itm(11)} {ACC1:exs#68.itm(12)} {ACC1:exs#68.itm(13)} {ACC1:exs#68.itm(14)} {ACC1:exs#68.itm(15)} -attr xrf 18203 -attr oid 349 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {slc(regs.regs(0).sva#1).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#1).itm} 10 {slc(regs.regs(0).sva#1).itm(0)} {slc(regs.regs(0).sva#1).itm(1)} {slc(regs.regs(0).sva#1).itm(2)} {slc(regs.regs(0).sva#1).itm(3)} {slc(regs.regs(0).sva#1).itm(4)} {slc(regs.regs(0).sva#1).itm(5)} {slc(regs.regs(0).sva#1).itm(6)} {slc(regs.regs(0).sva#1).itm(7)} {slc(regs.regs(0).sva#1).itm(8)} {slc(regs.regs(0).sva#1).itm(9)} -attr xrf 18204 -attr oid 350 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {ACC1:exs#69.itm(0)} -attr vt d
+load net {ACC1:exs#69.itm(1)} -attr vt d
+load net {ACC1:exs#69.itm(2)} -attr vt d
+load net {ACC1:exs#69.itm(3)} -attr vt d
+load net {ACC1:exs#69.itm(4)} -attr vt d
+load net {ACC1:exs#69.itm(5)} -attr vt d
+load net {ACC1:exs#69.itm(6)} -attr vt d
+load net {ACC1:exs#69.itm(7)} -attr vt d
+load net {ACC1:exs#69.itm(8)} -attr vt d
+load net {ACC1:exs#69.itm(9)} -attr vt d
+load net {ACC1:exs#69.itm(10)} -attr vt d
+load net {ACC1:exs#69.itm(11)} -attr vt d
+load net {ACC1:exs#69.itm(12)} -attr vt d
+load net {ACC1:exs#69.itm(13)} -attr vt d
+load net {ACC1:exs#69.itm(14)} -attr vt d
+load net {ACC1:exs#69.itm(15)} -attr vt d
+load netBundle {ACC1:exs#69.itm} 16 {ACC1:exs#69.itm(0)} {ACC1:exs#69.itm(1)} {ACC1:exs#69.itm(2)} {ACC1:exs#69.itm(3)} {ACC1:exs#69.itm(4)} {ACC1:exs#69.itm(5)} {ACC1:exs#69.itm(6)} {ACC1:exs#69.itm(7)} {ACC1:exs#69.itm(8)} {ACC1:exs#69.itm(9)} {ACC1:exs#69.itm(10)} {ACC1:exs#69.itm(11)} {ACC1:exs#69.itm(12)} {ACC1:exs#69.itm(13)} {ACC1:exs#69.itm(14)} {ACC1:exs#69.itm(15)} -attr xrf 18205 -attr oid 351 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {slc(regs.regs(0).sva#2).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#2).itm} 10 {slc(regs.regs(0).sva#2).itm(0)} {slc(regs.regs(0).sva#2).itm(1)} {slc(regs.regs(0).sva#2).itm(2)} {slc(regs.regs(0).sva#2).itm(3)} {slc(regs.regs(0).sva#2).itm(4)} {slc(regs.regs(0).sva#2).itm(5)} {slc(regs.regs(0).sva#2).itm(6)} {slc(regs.regs(0).sva#2).itm(7)} {slc(regs.regs(0).sva#2).itm(8)} {slc(regs.regs(0).sva#2).itm(9)} -attr xrf 18206 -attr oid 352 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {ACC1:exs#67.itm(0)} -attr vt d
+load net {ACC1:exs#67.itm(1)} -attr vt d
+load net {ACC1:exs#67.itm(2)} -attr vt d
+load net {ACC1:exs#67.itm(3)} -attr vt d
+load net {ACC1:exs#67.itm(4)} -attr vt d
+load net {ACC1:exs#67.itm(5)} -attr vt d
+load net {ACC1:exs#67.itm(6)} -attr vt d
+load net {ACC1:exs#67.itm(7)} -attr vt d
+load net {ACC1:exs#67.itm(8)} -attr vt d
+load net {ACC1:exs#67.itm(9)} -attr vt d
+load net {ACC1:exs#67.itm(10)} -attr vt d
+load net {ACC1:exs#67.itm(11)} -attr vt d
+load net {ACC1:exs#67.itm(12)} -attr vt d
+load net {ACC1:exs#67.itm(13)} -attr vt d
+load net {ACC1:exs#67.itm(14)} -attr vt d
+load net {ACC1:exs#67.itm(15)} -attr vt d
+load netBundle {ACC1:exs#67.itm} 16 {ACC1:exs#67.itm(0)} {ACC1:exs#67.itm(1)} {ACC1:exs#67.itm(2)} {ACC1:exs#67.itm(3)} {ACC1:exs#67.itm(4)} {ACC1:exs#67.itm(5)} {ACC1:exs#67.itm(6)} {ACC1:exs#67.itm(7)} {ACC1:exs#67.itm(8)} {ACC1:exs#67.itm(9)} {ACC1:exs#67.itm(10)} {ACC1:exs#67.itm(11)} {ACC1:exs#67.itm(12)} {ACC1:exs#67.itm(13)} {ACC1:exs#67.itm(14)} {ACC1:exs#67.itm(15)} -attr xrf 18207 -attr oid 353 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {slc(regs.regs(0).sva#3).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#3).itm} 10 {slc(regs.regs(0).sva#3).itm(0)} {slc(regs.regs(0).sva#3).itm(1)} {slc(regs.regs(0).sva#3).itm(2)} {slc(regs.regs(0).sva#3).itm(3)} {slc(regs.regs(0).sva#3).itm(4)} {slc(regs.regs(0).sva#3).itm(5)} {slc(regs.regs(0).sva#3).itm(6)} {slc(regs.regs(0).sva#3).itm(7)} {slc(regs.regs(0).sva#3).itm(8)} {slc(regs.regs(0).sva#3).itm(9)} -attr xrf 18208 -attr oid 354 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {ACC1:acc#177.itm(0)} -attr vt d
+load net {ACC1:acc#177.itm(1)} -attr vt d
+load net {ACC1:acc#177.itm(2)} -attr vt d
+load net {ACC1:acc#177.itm(3)} -attr vt d
+load net {ACC1:acc#177.itm(4)} -attr vt d
+load net {ACC1:acc#177.itm(5)} -attr vt d
+load net {ACC1:acc#177.itm(6)} -attr vt d
+load net {ACC1:acc#177.itm(7)} -attr vt d
+load net {ACC1:acc#177.itm(8)} -attr vt d
+load net {ACC1:acc#177.itm(9)} -attr vt d
+load net {ACC1:acc#177.itm(10)} -attr vt d
+load net {ACC1:acc#177.itm(11)} -attr vt d
+load net {ACC1:acc#177.itm(12)} -attr vt d
+load net {ACC1:acc#177.itm(13)} -attr vt d
+load net {ACC1:acc#177.itm(14)} -attr vt d
+load net {ACC1:acc#177.itm(15)} -attr vt d
+load net {ACC1:acc#177.itm(16)} -attr vt d
+load netBundle {ACC1:acc#177.itm} 17 {ACC1:acc#177.itm(0)} {ACC1:acc#177.itm(1)} {ACC1:acc#177.itm(2)} {ACC1:acc#177.itm(3)} {ACC1:acc#177.itm(4)} {ACC1:acc#177.itm(5)} {ACC1:acc#177.itm(6)} {ACC1:acc#177.itm(7)} {ACC1:acc#177.itm(8)} {ACC1:acc#177.itm(9)} {ACC1:acc#177.itm(10)} {ACC1:acc#177.itm(11)} {ACC1:acc#177.itm(12)} {ACC1:acc#177.itm(13)} {ACC1:acc#177.itm(14)} {ACC1:acc#177.itm(15)} {ACC1:acc#177.itm(16)} -attr xrf 18209 -attr oid 355 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:exs#95.itm(0)} -attr vt d
+load net {ACC1:exs#95.itm(1)} -attr vt d
+load net {ACC1:exs#95.itm(2)} -attr vt d
+load net {ACC1:exs#95.itm(3)} -attr vt d
+load net {ACC1:exs#95.itm(4)} -attr vt d
+load net {ACC1:exs#95.itm(5)} -attr vt d
+load net {ACC1:exs#95.itm(6)} -attr vt d
+load net {ACC1:exs#95.itm(7)} -attr vt d
+load net {ACC1:exs#95.itm(8)} -attr vt d
+load net {ACC1:exs#95.itm(9)} -attr vt d
+load net {ACC1:exs#95.itm(10)} -attr vt d
+load net {ACC1:exs#95.itm(11)} -attr vt d
+load net {ACC1:exs#95.itm(12)} -attr vt d
+load net {ACC1:exs#95.itm(13)} -attr vt d
+load net {ACC1:exs#95.itm(14)} -attr vt d
+load net {ACC1:exs#95.itm(15)} -attr vt d
+load netBundle {ACC1:exs#95.itm} 16 {ACC1:exs#95.itm(0)} {ACC1:exs#95.itm(1)} {ACC1:exs#95.itm(2)} {ACC1:exs#95.itm(3)} {ACC1:exs#95.itm(4)} {ACC1:exs#95.itm(5)} {ACC1:exs#95.itm(6)} {ACC1:exs#95.itm(7)} {ACC1:exs#95.itm(8)} {ACC1:exs#95.itm(9)} {ACC1:exs#95.itm(10)} {ACC1:exs#95.itm(11)} {ACC1:exs#95.itm(12)} {ACC1:exs#95.itm(13)} {ACC1:exs#95.itm(14)} {ACC1:exs#95.itm(15)} -attr xrf 18210 -attr oid 356 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:slc#27.itm(0)} -attr vt d
+load net {ACC1:slc#27.itm(1)} -attr vt d
+load net {ACC1:slc#27.itm(2)} -attr vt d
+load net {ACC1:slc#27.itm(3)} -attr vt d
+load net {ACC1:slc#27.itm(4)} -attr vt d
+load net {ACC1:slc#27.itm(5)} -attr vt d
+load net {ACC1:slc#27.itm(6)} -attr vt d
+load net {ACC1:slc#27.itm(7)} -attr vt d
+load net {ACC1:slc#27.itm(8)} -attr vt d
+load net {ACC1:slc#27.itm(9)} -attr vt d
+load net {ACC1:slc#27.itm(10)} -attr vt d
+load netBundle {ACC1:slc#27.itm} 11 {ACC1:slc#27.itm(0)} {ACC1:slc#27.itm(1)} {ACC1:slc#27.itm(2)} {ACC1:slc#27.itm(3)} {ACC1:slc#27.itm(4)} {ACC1:slc#27.itm(5)} {ACC1:slc#27.itm(6)} {ACC1:slc#27.itm(7)} {ACC1:slc#27.itm(8)} {ACC1:slc#27.itm(9)} {ACC1:slc#27.itm(10)} -attr xrf 18211 -attr oid 357 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#27.itm}
+load net {ACC1:acc#178.itm(0)} -attr vt d
+load net {ACC1:acc#178.itm(1)} -attr vt d
+load net {ACC1:acc#178.itm(2)} -attr vt d
+load net {ACC1:acc#178.itm(3)} -attr vt d
+load net {ACC1:acc#178.itm(4)} -attr vt d
+load net {ACC1:acc#178.itm(5)} -attr vt d
+load net {ACC1:acc#178.itm(6)} -attr vt d
+load net {ACC1:acc#178.itm(7)} -attr vt d
+load net {ACC1:acc#178.itm(8)} -attr vt d
+load net {ACC1:acc#178.itm(9)} -attr vt d
+load net {ACC1:acc#178.itm(10)} -attr vt d
+load net {ACC1:acc#178.itm(11)} -attr vt d
+load netBundle {ACC1:acc#178.itm} 12 {ACC1:acc#178.itm(0)} {ACC1:acc#178.itm(1)} {ACC1:acc#178.itm(2)} {ACC1:acc#178.itm(3)} {ACC1:acc#178.itm(4)} {ACC1:acc#178.itm(5)} {ACC1:acc#178.itm(6)} {ACC1:acc#178.itm(7)} {ACC1:acc#178.itm(8)} {ACC1:acc#178.itm(9)} {ACC1:acc#178.itm(10)} {ACC1:acc#178.itm(11)} -attr xrf 18212 -attr oid 358 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {conc#342.itm(0)} -attr vt d
+load net {conc#342.itm(1)} -attr vt d
+load net {conc#342.itm(2)} -attr vt d
+load net {conc#342.itm(3)} -attr vt d
+load net {conc#342.itm(4)} -attr vt d
+load net {conc#342.itm(5)} -attr vt d
+load net {conc#342.itm(6)} -attr vt d
+load net {conc#342.itm(7)} -attr vt d
+load net {conc#342.itm(8)} -attr vt d
+load net {conc#342.itm(9)} -attr vt d
+load net {conc#342.itm(10)} -attr vt d
+load netBundle {conc#342.itm} 11 {conc#342.itm(0)} {conc#342.itm(1)} {conc#342.itm(2)} {conc#342.itm(3)} {conc#342.itm(4)} {conc#342.itm(5)} {conc#342.itm(6)} {conc#342.itm(7)} {conc#342.itm(8)} {conc#342.itm(9)} {conc#342.itm(10)} -attr xrf 18213 -attr oid 359 -attr vt d -attr @path {/sobel/sobel:core/conc#342.itm}
+load net {ACC1:not#73.itm(0)} -attr vt d
+load net {ACC1:not#73.itm(1)} -attr vt d
+load net {ACC1:not#73.itm(2)} -attr vt d
+load net {ACC1:not#73.itm(3)} -attr vt d
+load net {ACC1:not#73.itm(4)} -attr vt d
+load net {ACC1:not#73.itm(5)} -attr vt d
+load net {ACC1:not#73.itm(6)} -attr vt d
+load net {ACC1:not#73.itm(7)} -attr vt d
+load net {ACC1:not#73.itm(8)} -attr vt d
+load net {ACC1:not#73.itm(9)} -attr vt d
+load netBundle {ACC1:not#73.itm} 10 {ACC1:not#73.itm(0)} {ACC1:not#73.itm(1)} {ACC1:not#73.itm(2)} {ACC1:not#73.itm(3)} {ACC1:not#73.itm(4)} {ACC1:not#73.itm(5)} {ACC1:not#73.itm(6)} {ACC1:not#73.itm(7)} {ACC1:not#73.itm(8)} {ACC1:not#73.itm(9)} -attr xrf 18214 -attr oid 360 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#73.itm}
+load net {conc#343.itm(0)} -attr vt d
+load net {conc#343.itm(1)} -attr vt d
+load net {conc#343.itm(2)} -attr vt d
+load net {conc#343.itm(3)} -attr vt d
+load net {conc#343.itm(4)} -attr vt d
+load net {conc#343.itm(5)} -attr vt d
+load net {conc#343.itm(6)} -attr vt d
+load net {conc#343.itm(7)} -attr vt d
+load net {conc#343.itm(8)} -attr vt d
+load net {conc#343.itm(9)} -attr vt d
+load net {conc#343.itm(10)} -attr vt d
+load netBundle {conc#343.itm} 11 {conc#343.itm(0)} {conc#343.itm(1)} {conc#343.itm(2)} {conc#343.itm(3)} {conc#343.itm(4)} {conc#343.itm(5)} {conc#343.itm(6)} {conc#343.itm(7)} {conc#343.itm(8)} {conc#343.itm(9)} {conc#343.itm(10)} -attr xrf 18215 -attr oid 361 -attr vt d -attr @path {/sobel/sobel:core/conc#343.itm}
+load net {slc(regs.regs(0).sva#4)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#4)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#4)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#4)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#4)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#4)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#4)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#4)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#4)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#4)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#4)#1.itm} 10 {slc(regs.regs(0).sva#4)#1.itm(0)} {slc(regs.regs(0).sva#4)#1.itm(1)} {slc(regs.regs(0).sva#4)#1.itm(2)} {slc(regs.regs(0).sva#4)#1.itm(3)} {slc(regs.regs(0).sva#4)#1.itm(4)} {slc(regs.regs(0).sva#4)#1.itm(5)} {slc(regs.regs(0).sva#4)#1.itm(6)} {slc(regs.regs(0).sva#4)#1.itm(7)} {slc(regs.regs(0).sva#4)#1.itm(8)} {slc(regs.regs(0).sva#4)#1.itm(9)} -attr xrf 18216 -attr oid 362 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4)#1.itm}
+load net {ACC1:exs#96.itm(0)} -attr vt d
+load net {ACC1:exs#96.itm(1)} -attr vt d
+load net {ACC1:exs#96.itm(2)} -attr vt d
+load net {ACC1:exs#96.itm(3)} -attr vt d
+load net {ACC1:exs#96.itm(4)} -attr vt d
+load net {ACC1:exs#96.itm(5)} -attr vt d
+load net {ACC1:exs#96.itm(6)} -attr vt d
+load net {ACC1:exs#96.itm(7)} -attr vt d
+load net {ACC1:exs#96.itm(8)} -attr vt d
+load net {ACC1:exs#96.itm(9)} -attr vt d
+load net {ACC1:exs#96.itm(10)} -attr vt d
+load net {ACC1:exs#96.itm(11)} -attr vt d
+load net {ACC1:exs#96.itm(12)} -attr vt d
+load net {ACC1:exs#96.itm(13)} -attr vt d
+load net {ACC1:exs#96.itm(14)} -attr vt d
+load net {ACC1:exs#96.itm(15)} -attr vt d
+load netBundle {ACC1:exs#96.itm} 16 {ACC1:exs#96.itm(0)} {ACC1:exs#96.itm(1)} {ACC1:exs#96.itm(2)} {ACC1:exs#96.itm(3)} {ACC1:exs#96.itm(4)} {ACC1:exs#96.itm(5)} {ACC1:exs#96.itm(6)} {ACC1:exs#96.itm(7)} {ACC1:exs#96.itm(8)} {ACC1:exs#96.itm(9)} {ACC1:exs#96.itm(10)} {ACC1:exs#96.itm(11)} {ACC1:exs#96.itm(12)} {ACC1:exs#96.itm(13)} {ACC1:exs#96.itm(14)} {ACC1:exs#96.itm(15)} -attr xrf 18217 -attr oid 363 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:slc#28.itm(0)} -attr vt d
+load net {ACC1:slc#28.itm(1)} -attr vt d
+load net {ACC1:slc#28.itm(2)} -attr vt d
+load net {ACC1:slc#28.itm(3)} -attr vt d
+load net {ACC1:slc#28.itm(4)} -attr vt d
+load net {ACC1:slc#28.itm(5)} -attr vt d
+load net {ACC1:slc#28.itm(6)} -attr vt d
+load net {ACC1:slc#28.itm(7)} -attr vt d
+load net {ACC1:slc#28.itm(8)} -attr vt d
+load net {ACC1:slc#28.itm(9)} -attr vt d
+load net {ACC1:slc#28.itm(10)} -attr vt d
+load netBundle {ACC1:slc#28.itm} 11 {ACC1:slc#28.itm(0)} {ACC1:slc#28.itm(1)} {ACC1:slc#28.itm(2)} {ACC1:slc#28.itm(3)} {ACC1:slc#28.itm(4)} {ACC1:slc#28.itm(5)} {ACC1:slc#28.itm(6)} {ACC1:slc#28.itm(7)} {ACC1:slc#28.itm(8)} {ACC1:slc#28.itm(9)} {ACC1:slc#28.itm(10)} -attr xrf 18218 -attr oid 364 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#28.itm}
+load net {ACC1:acc#179.itm(0)} -attr vt d
+load net {ACC1:acc#179.itm(1)} -attr vt d
+load net {ACC1:acc#179.itm(2)} -attr vt d
+load net {ACC1:acc#179.itm(3)} -attr vt d
+load net {ACC1:acc#179.itm(4)} -attr vt d
+load net {ACC1:acc#179.itm(5)} -attr vt d
+load net {ACC1:acc#179.itm(6)} -attr vt d
+load net {ACC1:acc#179.itm(7)} -attr vt d
+load net {ACC1:acc#179.itm(8)} -attr vt d
+load net {ACC1:acc#179.itm(9)} -attr vt d
+load net {ACC1:acc#179.itm(10)} -attr vt d
+load net {ACC1:acc#179.itm(11)} -attr vt d
+load netBundle {ACC1:acc#179.itm} 12 {ACC1:acc#179.itm(0)} {ACC1:acc#179.itm(1)} {ACC1:acc#179.itm(2)} {ACC1:acc#179.itm(3)} {ACC1:acc#179.itm(4)} {ACC1:acc#179.itm(5)} {ACC1:acc#179.itm(6)} {ACC1:acc#179.itm(7)} {ACC1:acc#179.itm(8)} {ACC1:acc#179.itm(9)} {ACC1:acc#179.itm(10)} {ACC1:acc#179.itm(11)} -attr xrf 18219 -attr oid 365 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {conc#344.itm(0)} -attr vt d
+load net {conc#344.itm(1)} -attr vt d
+load net {conc#344.itm(2)} -attr vt d
+load net {conc#344.itm(3)} -attr vt d
+load net {conc#344.itm(4)} -attr vt d
+load net {conc#344.itm(5)} -attr vt d
+load net {conc#344.itm(6)} -attr vt d
+load net {conc#344.itm(7)} -attr vt d
+load net {conc#344.itm(8)} -attr vt d
+load net {conc#344.itm(9)} -attr vt d
+load net {conc#344.itm(10)} -attr vt d
+load netBundle {conc#344.itm} 11 {conc#344.itm(0)} {conc#344.itm(1)} {conc#344.itm(2)} {conc#344.itm(3)} {conc#344.itm(4)} {conc#344.itm(5)} {conc#344.itm(6)} {conc#344.itm(7)} {conc#344.itm(8)} {conc#344.itm(9)} {conc#344.itm(10)} -attr xrf 18220 -attr oid 366 -attr vt d -attr @path {/sobel/sobel:core/conc#344.itm}
+load net {ACC1:not#74.itm(0)} -attr vt d
+load net {ACC1:not#74.itm(1)} -attr vt d
+load net {ACC1:not#74.itm(2)} -attr vt d
+load net {ACC1:not#74.itm(3)} -attr vt d
+load net {ACC1:not#74.itm(4)} -attr vt d
+load net {ACC1:not#74.itm(5)} -attr vt d
+load net {ACC1:not#74.itm(6)} -attr vt d
+load net {ACC1:not#74.itm(7)} -attr vt d
+load net {ACC1:not#74.itm(8)} -attr vt d
+load net {ACC1:not#74.itm(9)} -attr vt d
+load netBundle {ACC1:not#74.itm} 10 {ACC1:not#74.itm(0)} {ACC1:not#74.itm(1)} {ACC1:not#74.itm(2)} {ACC1:not#74.itm(3)} {ACC1:not#74.itm(4)} {ACC1:not#74.itm(5)} {ACC1:not#74.itm(6)} {ACC1:not#74.itm(7)} {ACC1:not#74.itm(8)} {ACC1:not#74.itm(9)} -attr xrf 18221 -attr oid 367 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#74.itm}
+load net {conc#345.itm(0)} -attr vt d
+load net {conc#345.itm(1)} -attr vt d
+load net {conc#345.itm(2)} -attr vt d
+load net {conc#345.itm(3)} -attr vt d
+load net {conc#345.itm(4)} -attr vt d
+load net {conc#345.itm(5)} -attr vt d
+load net {conc#345.itm(6)} -attr vt d
+load net {conc#345.itm(7)} -attr vt d
+load net {conc#345.itm(8)} -attr vt d
+load net {conc#345.itm(9)} -attr vt d
+load net {conc#345.itm(10)} -attr vt d
+load netBundle {conc#345.itm} 11 {conc#345.itm(0)} {conc#345.itm(1)} {conc#345.itm(2)} {conc#345.itm(3)} {conc#345.itm(4)} {conc#345.itm(5)} {conc#345.itm(6)} {conc#345.itm(7)} {conc#345.itm(8)} {conc#345.itm(9)} {conc#345.itm(10)} -attr xrf 18222 -attr oid 368 -attr vt d -attr @path {/sobel/sobel:core/conc#345.itm}
+load net {slc(regs.regs(0).sva#5)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#5)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#5)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#5)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#5)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#5)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#5)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#5)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#5)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#5)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#5)#1.itm} 10 {slc(regs.regs(0).sva#5)#1.itm(0)} {slc(regs.regs(0).sva#5)#1.itm(1)} {slc(regs.regs(0).sva#5)#1.itm(2)} {slc(regs.regs(0).sva#5)#1.itm(3)} {slc(regs.regs(0).sva#5)#1.itm(4)} {slc(regs.regs(0).sva#5)#1.itm(5)} {slc(regs.regs(0).sva#5)#1.itm(6)} {slc(regs.regs(0).sva#5)#1.itm(7)} {slc(regs.regs(0).sva#5)#1.itm(8)} {slc(regs.regs(0).sva#5)#1.itm(9)} -attr xrf 18223 -attr oid 369 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5)#1.itm}
+load net {ACC1:exs#94.itm(0)} -attr vt d
+load net {ACC1:exs#94.itm(1)} -attr vt d
+load net {ACC1:exs#94.itm(2)} -attr vt d
+load net {ACC1:exs#94.itm(3)} -attr vt d
+load net {ACC1:exs#94.itm(4)} -attr vt d
+load net {ACC1:exs#94.itm(5)} -attr vt d
+load net {ACC1:exs#94.itm(6)} -attr vt d
+load net {ACC1:exs#94.itm(7)} -attr vt d
+load net {ACC1:exs#94.itm(8)} -attr vt d
+load net {ACC1:exs#94.itm(9)} -attr vt d
+load net {ACC1:exs#94.itm(10)} -attr vt d
+load net {ACC1:exs#94.itm(11)} -attr vt d
+load net {ACC1:exs#94.itm(12)} -attr vt d
+load net {ACC1:exs#94.itm(13)} -attr vt d
+load net {ACC1:exs#94.itm(14)} -attr vt d
+load net {ACC1:exs#94.itm(15)} -attr vt d
+load netBundle {ACC1:exs#94.itm} 16 {ACC1:exs#94.itm(0)} {ACC1:exs#94.itm(1)} {ACC1:exs#94.itm(2)} {ACC1:exs#94.itm(3)} {ACC1:exs#94.itm(4)} {ACC1:exs#94.itm(5)} {ACC1:exs#94.itm(6)} {ACC1:exs#94.itm(7)} {ACC1:exs#94.itm(8)} {ACC1:exs#94.itm(9)} {ACC1:exs#94.itm(10)} {ACC1:exs#94.itm(11)} {ACC1:exs#94.itm(12)} {ACC1:exs#94.itm(13)} {ACC1:exs#94.itm(14)} {ACC1:exs#94.itm(15)} -attr xrf 18224 -attr oid 370 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:slc#29.itm(0)} -attr vt d
+load net {ACC1:slc#29.itm(1)} -attr vt d
+load net {ACC1:slc#29.itm(2)} -attr vt d
+load net {ACC1:slc#29.itm(3)} -attr vt d
+load net {ACC1:slc#29.itm(4)} -attr vt d
+load net {ACC1:slc#29.itm(5)} -attr vt d
+load net {ACC1:slc#29.itm(6)} -attr vt d
+load net {ACC1:slc#29.itm(7)} -attr vt d
+load net {ACC1:slc#29.itm(8)} -attr vt d
+load net {ACC1:slc#29.itm(9)} -attr vt d
+load net {ACC1:slc#29.itm(10)} -attr vt d
+load netBundle {ACC1:slc#29.itm} 11 {ACC1:slc#29.itm(0)} {ACC1:slc#29.itm(1)} {ACC1:slc#29.itm(2)} {ACC1:slc#29.itm(3)} {ACC1:slc#29.itm(4)} {ACC1:slc#29.itm(5)} {ACC1:slc#29.itm(6)} {ACC1:slc#29.itm(7)} {ACC1:slc#29.itm(8)} {ACC1:slc#29.itm(9)} {ACC1:slc#29.itm(10)} -attr xrf 18225 -attr oid 371 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#29.itm}
+load net {ACC1:acc#180.itm(0)} -attr vt d
+load net {ACC1:acc#180.itm(1)} -attr vt d
+load net {ACC1:acc#180.itm(2)} -attr vt d
+load net {ACC1:acc#180.itm(3)} -attr vt d
+load net {ACC1:acc#180.itm(4)} -attr vt d
+load net {ACC1:acc#180.itm(5)} -attr vt d
+load net {ACC1:acc#180.itm(6)} -attr vt d
+load net {ACC1:acc#180.itm(7)} -attr vt d
+load net {ACC1:acc#180.itm(8)} -attr vt d
+load net {ACC1:acc#180.itm(9)} -attr vt d
+load net {ACC1:acc#180.itm(10)} -attr vt d
+load net {ACC1:acc#180.itm(11)} -attr vt d
+load netBundle {ACC1:acc#180.itm} 12 {ACC1:acc#180.itm(0)} {ACC1:acc#180.itm(1)} {ACC1:acc#180.itm(2)} {ACC1:acc#180.itm(3)} {ACC1:acc#180.itm(4)} {ACC1:acc#180.itm(5)} {ACC1:acc#180.itm(6)} {ACC1:acc#180.itm(7)} {ACC1:acc#180.itm(8)} {ACC1:acc#180.itm(9)} {ACC1:acc#180.itm(10)} {ACC1:acc#180.itm(11)} -attr xrf 18226 -attr oid 372 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {conc#346.itm(0)} -attr vt d
+load net {conc#346.itm(1)} -attr vt d
+load net {conc#346.itm(2)} -attr vt d
+load net {conc#346.itm(3)} -attr vt d
+load net {conc#346.itm(4)} -attr vt d
+load net {conc#346.itm(5)} -attr vt d
+load net {conc#346.itm(6)} -attr vt d
+load net {conc#346.itm(7)} -attr vt d
+load net {conc#346.itm(8)} -attr vt d
+load net {conc#346.itm(9)} -attr vt d
+load net {conc#346.itm(10)} -attr vt d
+load netBundle {conc#346.itm} 11 {conc#346.itm(0)} {conc#346.itm(1)} {conc#346.itm(2)} {conc#346.itm(3)} {conc#346.itm(4)} {conc#346.itm(5)} {conc#346.itm(6)} {conc#346.itm(7)} {conc#346.itm(8)} {conc#346.itm(9)} {conc#346.itm(10)} -attr xrf 18227 -attr oid 373 -attr vt d -attr @path {/sobel/sobel:core/conc#346.itm}
+load net {ACC1:not#72.itm(0)} -attr vt d
+load net {ACC1:not#72.itm(1)} -attr vt d
+load net {ACC1:not#72.itm(2)} -attr vt d
+load net {ACC1:not#72.itm(3)} -attr vt d
+load net {ACC1:not#72.itm(4)} -attr vt d
+load net {ACC1:not#72.itm(5)} -attr vt d
+load net {ACC1:not#72.itm(6)} -attr vt d
+load net {ACC1:not#72.itm(7)} -attr vt d
+load net {ACC1:not#72.itm(8)} -attr vt d
+load net {ACC1:not#72.itm(9)} -attr vt d
+load netBundle {ACC1:not#72.itm} 10 {ACC1:not#72.itm(0)} {ACC1:not#72.itm(1)} {ACC1:not#72.itm(2)} {ACC1:not#72.itm(3)} {ACC1:not#72.itm(4)} {ACC1:not#72.itm(5)} {ACC1:not#72.itm(6)} {ACC1:not#72.itm(7)} {ACC1:not#72.itm(8)} {ACC1:not#72.itm(9)} -attr xrf 18228 -attr oid 374 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#72.itm}
+load net {conc#347.itm(0)} -attr vt d
+load net {conc#347.itm(1)} -attr vt d
+load net {conc#347.itm(2)} -attr vt d
+load net {conc#347.itm(3)} -attr vt d
+load net {conc#347.itm(4)} -attr vt d
+load net {conc#347.itm(5)} -attr vt d
+load net {conc#347.itm(6)} -attr vt d
+load net {conc#347.itm(7)} -attr vt d
+load net {conc#347.itm(8)} -attr vt d
+load net {conc#347.itm(9)} -attr vt d
+load net {conc#347.itm(10)} -attr vt d
+load netBundle {conc#347.itm} 11 {conc#347.itm(0)} {conc#347.itm(1)} {conc#347.itm(2)} {conc#347.itm(3)} {conc#347.itm(4)} {conc#347.itm(5)} {conc#347.itm(6)} {conc#347.itm(7)} {conc#347.itm(8)} {conc#347.itm(9)} {conc#347.itm(10)} -attr xrf 18229 -attr oid 375 -attr vt d -attr @path {/sobel/sobel:core/conc#347.itm}
+load net {slc(regs.regs(0).sva#6)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#6)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#6)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#6)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#6)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#6)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#6)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#6)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#6)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#6)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#6)#1.itm} 10 {slc(regs.regs(0).sva#6)#1.itm(0)} {slc(regs.regs(0).sva#6)#1.itm(1)} {slc(regs.regs(0).sva#6)#1.itm(2)} {slc(regs.regs(0).sva#6)#1.itm(3)} {slc(regs.regs(0).sva#6)#1.itm(4)} {slc(regs.regs(0).sva#6)#1.itm(5)} {slc(regs.regs(0).sva#6)#1.itm(6)} {slc(regs.regs(0).sva#6)#1.itm(7)} {slc(regs.regs(0).sva#6)#1.itm(8)} {slc(regs.regs(0).sva#6)#1.itm(9)} -attr xrf 18230 -attr oid 376 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6)#1.itm}
+load net {ACC1:acc#192.itm(0)} -attr vt d
+load net {ACC1:acc#192.itm(1)} -attr vt d
+load net {ACC1:acc#192.itm(2)} -attr vt d
+load net {ACC1:acc#192.itm(3)} -attr vt d
+load net {ACC1:acc#192.itm(4)} -attr vt d
+load net {ACC1:acc#192.itm(5)} -attr vt d
+load net {ACC1:acc#192.itm(6)} -attr vt d
+load net {ACC1:acc#192.itm(7)} -attr vt d
+load net {ACC1:acc#192.itm(8)} -attr vt d
+load net {ACC1:acc#192.itm(9)} -attr vt d
+load net {ACC1:acc#192.itm(10)} -attr vt d
+load net {ACC1:acc#192.itm(11)} -attr vt d
+load net {ACC1:acc#192.itm(12)} -attr vt d
+load net {ACC1:acc#192.itm(13)} -attr vt d
+load net {ACC1:acc#192.itm(14)} -attr vt d
+load net {ACC1:acc#192.itm(15)} -attr vt d
+load net {ACC1:acc#192.itm(16)} -attr vt d
+load netBundle {ACC1:acc#192.itm} 17 {ACC1:acc#192.itm(0)} {ACC1:acc#192.itm(1)} {ACC1:acc#192.itm(2)} {ACC1:acc#192.itm(3)} {ACC1:acc#192.itm(4)} {ACC1:acc#192.itm(5)} {ACC1:acc#192.itm(6)} {ACC1:acc#192.itm(7)} {ACC1:acc#192.itm(8)} {ACC1:acc#192.itm(9)} {ACC1:acc#192.itm(10)} {ACC1:acc#192.itm(11)} {ACC1:acc#192.itm(12)} {ACC1:acc#192.itm(13)} {ACC1:acc#192.itm(14)} {ACC1:acc#192.itm(15)} {ACC1:acc#192.itm(16)} -attr xrf 18231 -attr oid 377 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:exs#74.itm(0)} -attr vt d
+load net {ACC1:exs#74.itm(1)} -attr vt d
+load net {ACC1:exs#74.itm(2)} -attr vt d
+load net {ACC1:exs#74.itm(3)} -attr vt d
+load net {ACC1:exs#74.itm(4)} -attr vt d
+load net {ACC1:exs#74.itm(5)} -attr vt d
+load net {ACC1:exs#74.itm(6)} -attr vt d
+load net {ACC1:exs#74.itm(7)} -attr vt d
+load net {ACC1:exs#74.itm(8)} -attr vt d
+load net {ACC1:exs#74.itm(9)} -attr vt d
+load net {ACC1:exs#74.itm(10)} -attr vt d
+load net {ACC1:exs#74.itm(11)} -attr vt d
+load net {ACC1:exs#74.itm(12)} -attr vt d
+load net {ACC1:exs#74.itm(13)} -attr vt d
+load net {ACC1:exs#74.itm(14)} -attr vt d
+load net {ACC1:exs#74.itm(15)} -attr vt d
+load netBundle {ACC1:exs#74.itm} 16 {ACC1:exs#74.itm(0)} {ACC1:exs#74.itm(1)} {ACC1:exs#74.itm(2)} {ACC1:exs#74.itm(3)} {ACC1:exs#74.itm(4)} {ACC1:exs#74.itm(5)} {ACC1:exs#74.itm(6)} {ACC1:exs#74.itm(7)} {ACC1:exs#74.itm(8)} {ACC1:exs#74.itm(9)} {ACC1:exs#74.itm(10)} {ACC1:exs#74.itm(11)} {ACC1:exs#74.itm(12)} {ACC1:exs#74.itm(13)} {ACC1:exs#74.itm(14)} {ACC1:exs#74.itm(15)} -attr xrf 18232 -attr oid 378 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(0)} -attr vt d
+load net {ACC1-3:acc#22.itm(1)} -attr vt d
+load net {ACC1-3:acc#22.itm(2)} -attr vt d
+load net {ACC1-3:acc#22.itm(3)} -attr vt d
+load net {ACC1-3:acc#22.itm(4)} -attr vt d
+load net {ACC1-3:acc#22.itm(5)} -attr vt d
+load net {ACC1-3:acc#22.itm(6)} -attr vt d
+load net {ACC1-3:acc#22.itm(7)} -attr vt d
+load net {ACC1-3:acc#22.itm(8)} -attr vt d
+load net {ACC1-3:acc#22.itm(9)} -attr vt d
+load net {ACC1-3:acc#22.itm(10)} -attr vt d
+load netBundle {ACC1-3:acc#22.itm} 11 {ACC1-3:acc#22.itm(0)} {ACC1-3:acc#22.itm(1)} {ACC1-3:acc#22.itm(2)} {ACC1-3:acc#22.itm(3)} {ACC1-3:acc#22.itm(4)} {ACC1-3:acc#22.itm(5)} {ACC1-3:acc#22.itm(6)} {ACC1-3:acc#22.itm(7)} {ACC1-3:acc#22.itm(8)} {ACC1-3:acc#22.itm(9)} {ACC1-3:acc#22.itm(10)} -attr xrf 18233 -attr oid 379 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#22.itm}
+load net {slc(regs.regs(0).sva#1)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#1)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#1)#1.itm} 10 {slc(regs.regs(0).sva#1)#1.itm(0)} {slc(regs.regs(0).sva#1)#1.itm(1)} {slc(regs.regs(0).sva#1)#1.itm(2)} {slc(regs.regs(0).sva#1)#1.itm(3)} {slc(regs.regs(0).sva#1)#1.itm(4)} {slc(regs.regs(0).sva#1)#1.itm(5)} {slc(regs.regs(0).sva#1)#1.itm(6)} {slc(regs.regs(0).sva#1)#1.itm(7)} {slc(regs.regs(0).sva#1)#1.itm(8)} {slc(regs.regs(0).sva#1)#1.itm(9)} -attr xrf 18234 -attr oid 380 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {ACC1:exs#75.itm(0)} -attr vt d
+load net {ACC1:exs#75.itm(1)} -attr vt d
+load net {ACC1:exs#75.itm(2)} -attr vt d
+load net {ACC1:exs#75.itm(3)} -attr vt d
+load net {ACC1:exs#75.itm(4)} -attr vt d
+load net {ACC1:exs#75.itm(5)} -attr vt d
+load net {ACC1:exs#75.itm(6)} -attr vt d
+load net {ACC1:exs#75.itm(7)} -attr vt d
+load net {ACC1:exs#75.itm(8)} -attr vt d
+load net {ACC1:exs#75.itm(9)} -attr vt d
+load net {ACC1:exs#75.itm(10)} -attr vt d
+load net {ACC1:exs#75.itm(11)} -attr vt d
+load net {ACC1:exs#75.itm(12)} -attr vt d
+load net {ACC1:exs#75.itm(13)} -attr vt d
+load net {ACC1:exs#75.itm(14)} -attr vt d
+load net {ACC1:exs#75.itm(15)} -attr vt d
+load netBundle {ACC1:exs#75.itm} 16 {ACC1:exs#75.itm(0)} {ACC1:exs#75.itm(1)} {ACC1:exs#75.itm(2)} {ACC1:exs#75.itm(3)} {ACC1:exs#75.itm(4)} {ACC1:exs#75.itm(5)} {ACC1:exs#75.itm(6)} {ACC1:exs#75.itm(7)} {ACC1:exs#75.itm(8)} {ACC1:exs#75.itm(9)} {ACC1:exs#75.itm(10)} {ACC1:exs#75.itm(11)} {ACC1:exs#75.itm(12)} {ACC1:exs#75.itm(13)} {ACC1:exs#75.itm(14)} {ACC1:exs#75.itm(15)} -attr xrf 18235 -attr oid 381 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(0)} -attr vt d
+load net {ACC1-3:acc#25.itm(1)} -attr vt d
+load net {ACC1-3:acc#25.itm(2)} -attr vt d
+load net {ACC1-3:acc#25.itm(3)} -attr vt d
+load net {ACC1-3:acc#25.itm(4)} -attr vt d
+load net {ACC1-3:acc#25.itm(5)} -attr vt d
+load net {ACC1-3:acc#25.itm(6)} -attr vt d
+load net {ACC1-3:acc#25.itm(7)} -attr vt d
+load net {ACC1-3:acc#25.itm(8)} -attr vt d
+load net {ACC1-3:acc#25.itm(9)} -attr vt d
+load net {ACC1-3:acc#25.itm(10)} -attr vt d
+load netBundle {ACC1-3:acc#25.itm} 11 {ACC1-3:acc#25.itm(0)} {ACC1-3:acc#25.itm(1)} {ACC1-3:acc#25.itm(2)} {ACC1-3:acc#25.itm(3)} {ACC1-3:acc#25.itm(4)} {ACC1-3:acc#25.itm(5)} {ACC1-3:acc#25.itm(6)} {ACC1-3:acc#25.itm(7)} {ACC1-3:acc#25.itm(8)} {ACC1-3:acc#25.itm(9)} {ACC1-3:acc#25.itm(10)} -attr xrf 18236 -attr oid 382 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#25.itm}
+load net {slc(regs.regs(0).sva#2)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#2)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#2)#1.itm} 10 {slc(regs.regs(0).sva#2)#1.itm(0)} {slc(regs.regs(0).sva#2)#1.itm(1)} {slc(regs.regs(0).sva#2)#1.itm(2)} {slc(regs.regs(0).sva#2)#1.itm(3)} {slc(regs.regs(0).sva#2)#1.itm(4)} {slc(regs.regs(0).sva#2)#1.itm(5)} {slc(regs.regs(0).sva#2)#1.itm(6)} {slc(regs.regs(0).sva#2)#1.itm(7)} {slc(regs.regs(0).sva#2)#1.itm(8)} {slc(regs.regs(0).sva#2)#1.itm(9)} -attr xrf 18237 -attr oid 383 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {ACC1:exs#73.itm(0)} -attr vt d
+load net {ACC1:exs#73.itm(1)} -attr vt d
+load net {ACC1:exs#73.itm(2)} -attr vt d
+load net {ACC1:exs#73.itm(3)} -attr vt d
+load net {ACC1:exs#73.itm(4)} -attr vt d
+load net {ACC1:exs#73.itm(5)} -attr vt d
+load net {ACC1:exs#73.itm(6)} -attr vt d
+load net {ACC1:exs#73.itm(7)} -attr vt d
+load net {ACC1:exs#73.itm(8)} -attr vt d
+load net {ACC1:exs#73.itm(9)} -attr vt d
+load net {ACC1:exs#73.itm(10)} -attr vt d
+load net {ACC1:exs#73.itm(11)} -attr vt d
+load net {ACC1:exs#73.itm(12)} -attr vt d
+load net {ACC1:exs#73.itm(13)} -attr vt d
+load net {ACC1:exs#73.itm(14)} -attr vt d
+load net {ACC1:exs#73.itm(15)} -attr vt d
+load netBundle {ACC1:exs#73.itm} 16 {ACC1:exs#73.itm(0)} {ACC1:exs#73.itm(1)} {ACC1:exs#73.itm(2)} {ACC1:exs#73.itm(3)} {ACC1:exs#73.itm(4)} {ACC1:exs#73.itm(5)} {ACC1:exs#73.itm(6)} {ACC1:exs#73.itm(7)} {ACC1:exs#73.itm(8)} {ACC1:exs#73.itm(9)} {ACC1:exs#73.itm(10)} {ACC1:exs#73.itm(11)} {ACC1:exs#73.itm(12)} {ACC1:exs#73.itm(13)} {ACC1:exs#73.itm(14)} {ACC1:exs#73.itm(15)} -attr xrf 18238 -attr oid 384 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(0)} -attr vt d
+load net {ACC1-3:acc#19.itm(1)} -attr vt d
+load net {ACC1-3:acc#19.itm(2)} -attr vt d
+load net {ACC1-3:acc#19.itm(3)} -attr vt d
+load net {ACC1-3:acc#19.itm(4)} -attr vt d
+load net {ACC1-3:acc#19.itm(5)} -attr vt d
+load net {ACC1-3:acc#19.itm(6)} -attr vt d
+load net {ACC1-3:acc#19.itm(7)} -attr vt d
+load net {ACC1-3:acc#19.itm(8)} -attr vt d
+load net {ACC1-3:acc#19.itm(9)} -attr vt d
+load net {ACC1-3:acc#19.itm(10)} -attr vt d
+load netBundle {ACC1-3:acc#19.itm} 11 {ACC1-3:acc#19.itm(0)} {ACC1-3:acc#19.itm(1)} {ACC1-3:acc#19.itm(2)} {ACC1-3:acc#19.itm(3)} {ACC1-3:acc#19.itm(4)} {ACC1-3:acc#19.itm(5)} {ACC1-3:acc#19.itm(6)} {ACC1-3:acc#19.itm(7)} {ACC1-3:acc#19.itm(8)} {ACC1-3:acc#19.itm(9)} {ACC1-3:acc#19.itm(10)} -attr xrf 18239 -attr oid 385 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#19.itm}
+load net {slc(regs.regs(0).sva#3)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#3)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#3)#1.itm} 10 {slc(regs.regs(0).sva#3)#1.itm(0)} {slc(regs.regs(0).sva#3)#1.itm(1)} {slc(regs.regs(0).sva#3)#1.itm(2)} {slc(regs.regs(0).sva#3)#1.itm(3)} {slc(regs.regs(0).sva#3)#1.itm(4)} {slc(regs.regs(0).sva#3)#1.itm(5)} {slc(regs.regs(0).sva#3)#1.itm(6)} {slc(regs.regs(0).sva#3)#1.itm(7)} {slc(regs.regs(0).sva#3)#1.itm(8)} {slc(regs.regs(0).sva#3)#1.itm(9)} -attr xrf 18240 -attr oid 386 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {ACC1:acc#162.itm(0)} -attr vt d
+load net {ACC1:acc#162.itm(1)} -attr vt d
+load net {ACC1:acc#162.itm(2)} -attr vt d
+load net {ACC1:acc#162.itm(3)} -attr vt d
+load net {ACC1:acc#162.itm(4)} -attr vt d
+load net {ACC1:acc#162.itm(5)} -attr vt d
+load netBundle {ACC1:acc#162.itm} 6 {ACC1:acc#162.itm(0)} {ACC1:acc#162.itm(1)} {ACC1:acc#162.itm(2)} {ACC1:acc#162.itm(3)} {ACC1:acc#162.itm(4)} {ACC1:acc#162.itm(5)} -attr xrf 18241 -attr oid 387 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {conc#348.itm(0)} -attr vt d
+load net {conc#348.itm(1)} -attr vt d
+load net {conc#348.itm(2)} -attr vt d
+load net {conc#348.itm(3)} -attr vt d
+load net {conc#348.itm(4)} -attr vt d
+load net {conc#348.itm(5)} -attr vt d
+load netBundle {conc#348.itm} 6 {conc#348.itm(0)} {conc#348.itm(1)} {conc#348.itm(2)} {conc#348.itm(3)} {conc#348.itm(4)} {conc#348.itm(5)} -attr xrf 18242 -attr oid 388 -attr vt d -attr @path {/sobel/sobel:core/conc#348.itm}
+load net {ACC1:slc#12.itm(0)} -attr vt d
+load net {ACC1:slc#12.itm(1)} -attr vt d
+load net {ACC1:slc#12.itm(2)} -attr vt d
+load net {ACC1:slc#12.itm(3)} -attr vt d
+load net {ACC1:slc#12.itm(4)} -attr vt d
+load netBundle {ACC1:slc#12.itm} 5 {ACC1:slc#12.itm(0)} {ACC1:slc#12.itm(1)} {ACC1:slc#12.itm(2)} {ACC1:slc#12.itm(3)} {ACC1:slc#12.itm(4)} -attr xrf 18243 -attr oid 389 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#12.itm}
+load net {ACC1:acc#161.itm(0)} -attr vt d
+load net {ACC1:acc#161.itm(1)} -attr vt d
+load net {ACC1:acc#161.itm(2)} -attr vt d
+load net {ACC1:acc#161.itm(3)} -attr vt d
+load net {ACC1:acc#161.itm(4)} -attr vt d
+load net {ACC1:acc#161.itm(5)} -attr vt d
+load netBundle {ACC1:acc#161.itm} 6 {ACC1:acc#161.itm(0)} {ACC1:acc#161.itm(1)} {ACC1:acc#161.itm(2)} {ACC1:acc#161.itm(3)} {ACC1:acc#161.itm(4)} {ACC1:acc#161.itm(5)} -attr xrf 18244 -attr oid 390 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load net {conc#349.itm(0)} -attr vt d
+load net {conc#349.itm(1)} -attr vt d
+load net {conc#349.itm(2)} -attr vt d
+load net {conc#349.itm(3)} -attr vt d
+load net {conc#349.itm(4)} -attr vt d
+load netBundle {conc#349.itm} 5 {conc#349.itm(0)} {conc#349.itm(1)} {conc#349.itm(2)} {conc#349.itm(3)} {conc#349.itm(4)} -attr xrf 18245 -attr oid 391 -attr vt d -attr @path {/sobel/sobel:core/conc#349.itm}
+load net {ACC1:slc#11.itm(0)} -attr vt d
+load net {ACC1:slc#11.itm(1)} -attr vt d
+load net {ACC1:slc#11.itm(2)} -attr vt d
+load net {ACC1:slc#11.itm(3)} -attr vt d
+load netBundle {ACC1:slc#11.itm} 4 {ACC1:slc#11.itm(0)} {ACC1:slc#11.itm(1)} {ACC1:slc#11.itm(2)} {ACC1:slc#11.itm(3)} -attr xrf 18246 -attr oid 392 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#160.itm(0)} -attr vt d
+load net {ACC1:acc#160.itm(1)} -attr vt d
+load net {ACC1:acc#160.itm(2)} -attr vt d
+load net {ACC1:acc#160.itm(3)} -attr vt d
+load net {ACC1:acc#160.itm(4)} -attr vt d
+load netBundle {ACC1:acc#160.itm} 5 {ACC1:acc#160.itm(0)} {ACC1:acc#160.itm(1)} {ACC1:acc#160.itm(2)} {ACC1:acc#160.itm(3)} {ACC1:acc#160.itm(4)} -attr xrf 18247 -attr oid 393 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load net {conc#350.itm(0)} -attr vt d
+load net {conc#350.itm(1)} -attr vt d
+load net {conc#350.itm(2)} -attr vt d
+load net {conc#350.itm(3)} -attr vt d
+load netBundle {conc#350.itm} 4 {conc#350.itm(0)} {conc#350.itm(1)} {conc#350.itm(2)} {conc#350.itm(3)} -attr xrf 18248 -attr oid 394 -attr vt d -attr @path {/sobel/sobel:core/conc#350.itm}
+load net {ACC1:slc#9.itm(0)} -attr vt d
+load net {ACC1:slc#9.itm(1)} -attr vt d
+load net {ACC1:slc#9.itm(2)} -attr vt d
+load netBundle {ACC1:slc#9.itm} 3 {ACC1:slc#9.itm(0)} {ACC1:slc#9.itm(1)} {ACC1:slc#9.itm(2)} -attr xrf 18249 -attr oid 395 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#9.itm}
+load net {ACC1:acc#158.itm(0)} -attr vt d
+load net {ACC1:acc#158.itm(1)} -attr vt d
+load net {ACC1:acc#158.itm(2)} -attr vt d
+load net {ACC1:acc#158.itm(3)} -attr vt d
+load netBundle {ACC1:acc#158.itm} 4 {ACC1:acc#158.itm(0)} {ACC1:acc#158.itm(1)} {ACC1:acc#158.itm(2)} {ACC1:acc#158.itm(3)} -attr xrf 18250 -attr oid 396 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {conc#351.itm(0)} -attr vt d
+load net {conc#351.itm(1)} -attr vt d
+load net {conc#351.itm(2)} -attr vt d
+load netBundle {conc#351.itm} 3 {conc#351.itm(0)} {conc#351.itm(1)} {conc#351.itm(2)} -attr xrf 18251 -attr oid 397 -attr vt d -attr @path {/sobel/sobel:core/conc#351.itm}
+load net {ACC1:slc#5.itm(0)} -attr vt d
+load net {ACC1:slc#5.itm(1)} -attr vt d
+load netBundle {ACC1:slc#5.itm} 2 {ACC1:slc#5.itm(0)} {ACC1:slc#5.itm(1)} -attr xrf 18252 -attr oid 398 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#5.itm}
+load net {ACC1:acc#154.itm(0)} -attr vt d
+load net {ACC1:acc#154.itm(1)} -attr vt d
+load net {ACC1:acc#154.itm(2)} -attr vt d
+load netBundle {ACC1:acc#154.itm} 3 {ACC1:acc#154.itm(0)} {ACC1:acc#154.itm(1)} {ACC1:acc#154.itm(2)} -attr xrf 18253 -attr oid 399 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154.itm}
+load net {conc#352.itm(0)} -attr vt d
+load net {conc#352.itm(1)} -attr vt d
+load netBundle {conc#352.itm} 2 {conc#352.itm(0)} {conc#352.itm(1)} -attr xrf 18254 -attr oid 400 -attr vt d -attr @path {/sobel/sobel:core/conc#352.itm}
+load net {conc#353.itm(0)} -attr vt d
+load net {conc#353.itm(1)} -attr vt d
+load netBundle {conc#353.itm} 2 {conc#353.itm(0)} {conc#353.itm(1)} -attr xrf 18255 -attr oid 401 -attr vt d -attr @path {/sobel/sobel:core/conc#353.itm}
+load net {ACC1:conc#299.itm(0)} -attr vt d
+load net {ACC1:conc#299.itm(1)} -attr vt d
+load netBundle {ACC1:conc#299.itm} 2 {ACC1:conc#299.itm(0)} {ACC1:conc#299.itm(1)} -attr xrf 18256 -attr oid 402 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#299.itm}
+load net {ACC1:conc#303.itm(0)} -attr vt d
+load net {ACC1:conc#303.itm(1)} -attr vt d
+load net {ACC1:conc#303.itm(2)} -attr vt d
+load netBundle {ACC1:conc#303.itm} 3 {ACC1:conc#303.itm(0)} {ACC1:conc#303.itm(1)} {ACC1:conc#303.itm(2)} -attr xrf 18257 -attr oid 403 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#303.itm}
+load net {ACC1:slc#8.itm(0)} -attr vt d
+load net {ACC1:slc#8.itm(1)} -attr vt d
+load netBundle {ACC1:slc#8.itm} 2 {ACC1:slc#8.itm(0)} {ACC1:slc#8.itm(1)} -attr xrf 18258 -attr oid 404 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#8.itm}
+load net {ACC1:acc#157.itm(0)} -attr vt d
+load net {ACC1:acc#157.itm(1)} -attr vt d
+load net {ACC1:acc#157.itm(2)} -attr vt d
+load netBundle {ACC1:acc#157.itm} 3 {ACC1:acc#157.itm(0)} {ACC1:acc#157.itm(1)} {ACC1:acc#157.itm(2)} -attr xrf 18259 -attr oid 405 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load net {conc#354.itm(0)} -attr vt d
+load net {conc#354.itm(1)} -attr vt d
+load netBundle {conc#354.itm} 2 {conc#354.itm(0)} {conc#354.itm(1)} -attr xrf 18260 -attr oid 406 -attr vt d -attr @path {/sobel/sobel:core/conc#354.itm}
+load net {ACC1:conc#297.itm(0)} -attr vt d
+load net {ACC1:conc#297.itm(1)} -attr vt d
+load netBundle {ACC1:conc#297.itm} 2 {ACC1:conc#297.itm(0)} {ACC1:conc#297.itm(1)} -attr xrf 18261 -attr oid 407 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#297.itm}
+load net {ACC1:conc#305.itm(0)} -attr vt d
+load net {ACC1:conc#305.itm(1)} -attr vt d
+load net {ACC1:conc#305.itm(2)} -attr vt d
+load net {ACC1:conc#305.itm(3)} -attr vt d
+load netBundle {ACC1:conc#305.itm} 4 {ACC1:conc#305.itm(0)} {ACC1:conc#305.itm(1)} {ACC1:conc#305.itm(2)} {ACC1:conc#305.itm(3)} -attr xrf 18262 -attr oid 408 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#305.itm}
+load net {ACC1:slc#10.itm(0)} -attr vt d
+load net {ACC1:slc#10.itm(1)} -attr vt d
+load net {ACC1:slc#10.itm(2)} -attr vt d
+load netBundle {ACC1:slc#10.itm} 3 {ACC1:slc#10.itm(0)} {ACC1:slc#10.itm(1)} {ACC1:slc#10.itm(2)} -attr xrf 18263 -attr oid 409 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#10.itm}
+load net {ACC1:acc#159.itm(0)} -attr vt d
+load net {ACC1:acc#159.itm(1)} -attr vt d
+load net {ACC1:acc#159.itm(2)} -attr vt d
+load net {ACC1:acc#159.itm(3)} -attr vt d
+load netBundle {ACC1:acc#159.itm} 4 {ACC1:acc#159.itm(0)} {ACC1:acc#159.itm(1)} {ACC1:acc#159.itm(2)} {ACC1:acc#159.itm(3)} -attr xrf 18264 -attr oid 410 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#159.itm}
+load net {conc#355.itm(0)} -attr vt d
+load net {conc#355.itm(1)} -attr vt d
+load net {conc#355.itm(2)} -attr vt d
+load netBundle {conc#355.itm} 3 {conc#355.itm(0)} {conc#355.itm(1)} {conc#355.itm(2)} -attr xrf 18265 -attr oid 411 -attr vt d -attr @path {/sobel/sobel:core/conc#355.itm}
+load net {ACC1:slc#7.itm(0)} -attr vt d
+load net {ACC1:slc#7.itm(1)} -attr vt d
+load netBundle {ACC1:slc#7.itm} 2 {ACC1:slc#7.itm(0)} {ACC1:slc#7.itm(1)} -attr xrf 18266 -attr oid 412 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#156.itm(0)} -attr vt d
+load net {ACC1:acc#156.itm(1)} -attr vt d
+load net {ACC1:acc#156.itm(2)} -attr vt d
+load netBundle {ACC1:acc#156.itm} 3 {ACC1:acc#156.itm(0)} {ACC1:acc#156.itm(1)} {ACC1:acc#156.itm(2)} -attr xrf 18267 -attr oid 413 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load net {conc#356.itm(0)} -attr vt d
+load net {conc#356.itm(1)} -attr vt d
+load netBundle {conc#356.itm} 2 {conc#356.itm(0)} {conc#356.itm(1)} -attr xrf 18268 -attr oid 414 -attr vt d -attr @path {/sobel/sobel:core/conc#356.itm}
+load net {ACC1:conc#295.itm(0)} -attr vt d
+load net {ACC1:conc#295.itm(1)} -attr vt d
+load netBundle {ACC1:conc#295.itm} 2 {ACC1:conc#295.itm(0)} {ACC1:conc#295.itm(1)} -attr xrf 18269 -attr oid 415 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#295.itm}
+load net {ACC1:conc#301.itm(0)} -attr vt d
+load net {ACC1:conc#301.itm(1)} -attr vt d
+load net {ACC1:conc#301.itm(2)} -attr vt d
+load netBundle {ACC1:conc#301.itm} 3 {ACC1:conc#301.itm(0)} {ACC1:conc#301.itm(1)} {ACC1:conc#301.itm(2)} -attr xrf 18270 -attr oid 416 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#301.itm}
+load net {ACC1:slc#6.itm(0)} -attr vt d
+load net {ACC1:slc#6.itm(1)} -attr vt d
+load netBundle {ACC1:slc#6.itm} 2 {ACC1:slc#6.itm(0)} {ACC1:slc#6.itm(1)} -attr xrf 18271 -attr oid 417 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#6.itm}
+load net {ACC1:acc#155.itm(0)} -attr vt d
+load net {ACC1:acc#155.itm(1)} -attr vt d
+load net {ACC1:acc#155.itm(2)} -attr vt d
+load netBundle {ACC1:acc#155.itm} 3 {ACC1:acc#155.itm(0)} {ACC1:acc#155.itm(1)} {ACC1:acc#155.itm(2)} -attr xrf 18272 -attr oid 418 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#155.itm}
+load net {conc#357.itm(0)} -attr vt d
+load net {conc#357.itm(1)} -attr vt d
+load netBundle {conc#357.itm} 2 {conc#357.itm(0)} {conc#357.itm(1)} -attr xrf 18273 -attr oid 419 -attr vt d -attr @path {/sobel/sobel:core/conc#357.itm}
+load net {ACC1:conc#293.itm(0)} -attr vt d
+load net {ACC1:conc#293.itm(1)} -attr vt d
+load netBundle {ACC1:conc#293.itm} 2 {ACC1:conc#293.itm(0)} {ACC1:conc#293.itm(1)} -attr xrf 18274 -attr oid 420 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#293.itm}
+load net {conc#358.itm(0)} -attr vt d
+load net {conc#358.itm(1)} -attr vt d
+load net {conc#358.itm(2)} -attr vt d
+load net {conc#358.itm(3)} -attr vt d
+load net {conc#358.itm(4)} -attr vt d
+load net {conc#358.itm(5)} -attr vt d
+load netBundle {conc#358.itm} 6 {conc#358.itm(0)} {conc#358.itm(1)} {conc#358.itm(2)} {conc#358.itm(3)} {conc#358.itm(4)} {conc#358.itm(5)} -attr xrf 18275 -attr oid 421 -attr vt d -attr @path {/sobel/sobel:core/conc#358.itm}
+load net {ACC1:slc#15.itm(0)} -attr vt d
+load net {ACC1:slc#15.itm(1)} -attr vt d
+load net {ACC1:slc#15.itm(2)} -attr vt d
+load netBundle {ACC1:slc#15.itm} 3 {ACC1:slc#15.itm(0)} {ACC1:slc#15.itm(1)} {ACC1:slc#15.itm(2)} -attr xrf 18276 -attr oid 422 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#15.itm}
+load net {ACC1:acc#164.itm(0)} -attr vt d
+load net {ACC1:acc#164.itm(1)} -attr vt d
+load net {ACC1:acc#164.itm(2)} -attr vt d
+load net {ACC1:acc#164.itm(3)} -attr vt d
+load netBundle {ACC1:acc#164.itm} 4 {ACC1:acc#164.itm(0)} {ACC1:acc#164.itm(1)} {ACC1:acc#164.itm(2)} {ACC1:acc#164.itm(3)} -attr xrf 18277 -attr oid 423 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164.itm}
+load net {conc#359.itm(0)} -attr vt d
+load net {conc#359.itm(1)} -attr vt d
+load net {conc#359.itm(2)} -attr vt d
+load netBundle {conc#359.itm} 3 {conc#359.itm(0)} {conc#359.itm(1)} {conc#359.itm(2)} -attr xrf 18278 -attr oid 424 -attr vt d -attr @path {/sobel/sobel:core/conc#359.itm}
+load net {ACC1:slc#14.itm(0)} -attr vt d
+load net {ACC1:slc#14.itm(1)} -attr vt d
+load netBundle {ACC1:slc#14.itm} 2 {ACC1:slc#14.itm(0)} {ACC1:slc#14.itm(1)} -attr xrf 18279 -attr oid 425 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#14.itm}
+load net {ACC1:acc#163.itm(0)} -attr vt d
+load net {ACC1:acc#163.itm(1)} -attr vt d
+load net {ACC1:acc#163.itm(2)} -attr vt d
+load netBundle {ACC1:acc#163.itm} 3 {ACC1:acc#163.itm(0)} {ACC1:acc#163.itm(1)} {ACC1:acc#163.itm(2)} -attr xrf 18280 -attr oid 426 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163.itm}
+load net {conc#360.itm(0)} -attr vt d
+load net {conc#360.itm(1)} -attr vt d
+load netBundle {conc#360.itm} 2 {conc#360.itm(0)} {conc#360.itm(1)} -attr xrf 18281 -attr oid 427 -attr vt d -attr @path {/sobel/sobel:core/conc#360.itm}
+load net {conc#361.itm(0)} -attr vt d
+load net {conc#361.itm(1)} -attr vt d
+load netBundle {conc#361.itm} 2 {conc#361.itm(0)} {conc#361.itm(1)} -attr xrf 18282 -attr oid 428 -attr vt d -attr @path {/sobel/sobel:core/conc#361.itm}
+load net {ACC1:conc#312.itm(0)} -attr vt d
+load net {ACC1:conc#312.itm(1)} -attr vt d
+load netBundle {ACC1:conc#312.itm} 2 {ACC1:conc#312.itm(0)} {ACC1:conc#312.itm(1)} -attr xrf 18283 -attr oid 429 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#312.itm}
+load net {conc#362.itm(0)} -attr vt d
+load net {conc#362.itm(1)} -attr vt d
+load net {conc#362.itm(2)} -attr vt d
+load netBundle {conc#362.itm} 3 {conc#362.itm(0)} {conc#362.itm(1)} {conc#362.itm(2)} -attr xrf 18284 -attr oid 430 -attr vt d -attr @path {/sobel/sobel:core/conc#362.itm}
+load net {ACC1:acc#201.itm(0)} -attr vt d
+load net {ACC1:acc#201.itm(1)} -attr vt d
+load net {ACC1:acc#201.itm(2)} -attr vt d
+load net {ACC1:acc#201.itm(3)} -attr vt d
+load net {ACC1:acc#201.itm(4)} -attr vt d
+load net {ACC1:acc#201.itm(5)} -attr vt d
+load netBundle {ACC1:acc#201.itm} 6 {ACC1:acc#201.itm(0)} {ACC1:acc#201.itm(1)} {ACC1:acc#201.itm(2)} {ACC1:acc#201.itm(3)} {ACC1:acc#201.itm(4)} {ACC1:acc#201.itm(5)} -attr xrf 18285 -attr oid 431 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {conc#363.itm(0)} -attr vt d
+load net {conc#363.itm(1)} -attr vt d
+load net {conc#363.itm(2)} -attr vt d
+load net {conc#363.itm(3)} -attr vt d
+load net {conc#363.itm(4)} -attr vt d
+load net {conc#363.itm(5)} -attr vt d
+load netBundle {conc#363.itm} 6 {conc#363.itm(0)} {conc#363.itm(1)} {conc#363.itm(2)} {conc#363.itm(3)} {conc#363.itm(4)} {conc#363.itm(5)} -attr xrf 18286 -attr oid 432 -attr vt d -attr @path {/sobel/sobel:core/conc#363.itm}
+load net {ACC1:slc#48.itm(0)} -attr vt d
+load net {ACC1:slc#48.itm(1)} -attr vt d
+load net {ACC1:slc#48.itm(2)} -attr vt d
+load net {ACC1:slc#48.itm(3)} -attr vt d
+load net {ACC1:slc#48.itm(4)} -attr vt d
+load netBundle {ACC1:slc#48.itm} 5 {ACC1:slc#48.itm(0)} {ACC1:slc#48.itm(1)} {ACC1:slc#48.itm(2)} {ACC1:slc#48.itm(3)} {ACC1:slc#48.itm(4)} -attr xrf 18287 -attr oid 433 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#48.itm}
+load net {ACC1:acc#200.itm(0)} -attr vt d
+load net {ACC1:acc#200.itm(1)} -attr vt d
+load net {ACC1:acc#200.itm(2)} -attr vt d
+load net {ACC1:acc#200.itm(3)} -attr vt d
+load net {ACC1:acc#200.itm(4)} -attr vt d
+load net {ACC1:acc#200.itm(5)} -attr vt d
+load netBundle {ACC1:acc#200.itm} 6 {ACC1:acc#200.itm(0)} {ACC1:acc#200.itm(1)} {ACC1:acc#200.itm(2)} {ACC1:acc#200.itm(3)} {ACC1:acc#200.itm(4)} {ACC1:acc#200.itm(5)} -attr xrf 18288 -attr oid 434 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {conc#364.itm(0)} -attr vt d
+load net {conc#364.itm(1)} -attr vt d
+load net {conc#364.itm(2)} -attr vt d
+load net {conc#364.itm(3)} -attr vt d
+load net {conc#364.itm(4)} -attr vt d
+load netBundle {conc#364.itm} 5 {conc#364.itm(0)} {conc#364.itm(1)} {conc#364.itm(2)} {conc#364.itm(3)} {conc#364.itm(4)} -attr xrf 18289 -attr oid 435 -attr vt d -attr @path {/sobel/sobel:core/conc#364.itm}
+load net {ACC1:slc#47.itm(0)} -attr vt d
+load net {ACC1:slc#47.itm(1)} -attr vt d
+load net {ACC1:slc#47.itm(2)} -attr vt d
+load net {ACC1:slc#47.itm(3)} -attr vt d
+load netBundle {ACC1:slc#47.itm} 4 {ACC1:slc#47.itm(0)} {ACC1:slc#47.itm(1)} {ACC1:slc#47.itm(2)} {ACC1:slc#47.itm(3)} -attr xrf 18290 -attr oid 436 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#47.itm}
+load net {ACC1:acc#199.itm(0)} -attr vt d
+load net {ACC1:acc#199.itm(1)} -attr vt d
+load net {ACC1:acc#199.itm(2)} -attr vt d
+load net {ACC1:acc#199.itm(3)} -attr vt d
+load net {ACC1:acc#199.itm(4)} -attr vt d
+load netBundle {ACC1:acc#199.itm} 5 {ACC1:acc#199.itm(0)} {ACC1:acc#199.itm(1)} {ACC1:acc#199.itm(2)} {ACC1:acc#199.itm(3)} {ACC1:acc#199.itm(4)} -attr xrf 18291 -attr oid 437 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {conc#365.itm(0)} -attr vt d
+load net {conc#365.itm(1)} -attr vt d
+load net {conc#365.itm(2)} -attr vt d
+load net {conc#365.itm(3)} -attr vt d
+load netBundle {conc#365.itm} 4 {conc#365.itm(0)} {conc#365.itm(1)} {conc#365.itm(2)} {conc#365.itm(3)} -attr xrf 18292 -attr oid 438 -attr vt d -attr @path {/sobel/sobel:core/conc#365.itm}
+load net {ACC1:slc#45.itm(0)} -attr vt d
+load net {ACC1:slc#45.itm(1)} -attr vt d
+load net {ACC1:slc#45.itm(2)} -attr vt d
+load netBundle {ACC1:slc#45.itm} 3 {ACC1:slc#45.itm(0)} {ACC1:slc#45.itm(1)} {ACC1:slc#45.itm(2)} -attr xrf 18293 -attr oid 439 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#45.itm}
+load net {ACC1:acc#197.itm(0)} -attr vt d
+load net {ACC1:acc#197.itm(1)} -attr vt d
+load net {ACC1:acc#197.itm(2)} -attr vt d
+load net {ACC1:acc#197.itm(3)} -attr vt d
+load netBundle {ACC1:acc#197.itm} 4 {ACC1:acc#197.itm(0)} {ACC1:acc#197.itm(1)} {ACC1:acc#197.itm(2)} {ACC1:acc#197.itm(3)} -attr xrf 18294 -attr oid 440 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.itm}
+load net {conc#366.itm(0)} -attr vt d
+load net {conc#366.itm(1)} -attr vt d
+load net {conc#366.itm(2)} -attr vt d
+load netBundle {conc#366.itm} 3 {conc#366.itm(0)} {conc#366.itm(1)} {conc#366.itm(2)} -attr xrf 18295 -attr oid 441 -attr vt d -attr @path {/sobel/sobel:core/conc#366.itm}
+load net {ACC1:slc#41.itm(0)} -attr vt d
+load net {ACC1:slc#41.itm(1)} -attr vt d
+load netBundle {ACC1:slc#41.itm} 2 {ACC1:slc#41.itm(0)} {ACC1:slc#41.itm(1)} -attr xrf 18296 -attr oid 442 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#41.itm}
+load net {ACC1:acc#193.itm(0)} -attr vt d
+load net {ACC1:acc#193.itm(1)} -attr vt d
+load net {ACC1:acc#193.itm(2)} -attr vt d
+load netBundle {ACC1:acc#193.itm} 3 {ACC1:acc#193.itm(0)} {ACC1:acc#193.itm(1)} {ACC1:acc#193.itm(2)} -attr xrf 18297 -attr oid 443 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load net {conc#367.itm(0)} -attr vt d
+load net {conc#367.itm(1)} -attr vt d
+load netBundle {conc#367.itm} 2 {conc#367.itm(0)} {conc#367.itm(1)} -attr xrf 18298 -attr oid 444 -attr vt d -attr @path {/sobel/sobel:core/conc#367.itm}
+load net {conc#368.itm(0)} -attr vt d
+load net {conc#368.itm(1)} -attr vt d
+load netBundle {conc#368.itm} 2 {conc#368.itm(0)} {conc#368.itm(1)} -attr xrf 18299 -attr oid 445 -attr vt d -attr @path {/sobel/sobel:core/conc#368.itm}
+load net {ACC1:conc#377.itm(0)} -attr vt d
+load net {ACC1:conc#377.itm(1)} -attr vt d
+load netBundle {ACC1:conc#377.itm} 2 {ACC1:conc#377.itm(0)} {ACC1:conc#377.itm(1)} -attr xrf 18300 -attr oid 446 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#377.itm}
+load net {ACC1:conc#381.itm(0)} -attr vt d
+load net {ACC1:conc#381.itm(1)} -attr vt d
+load net {ACC1:conc#381.itm(2)} -attr vt d
+load netBundle {ACC1:conc#381.itm} 3 {ACC1:conc#381.itm(0)} {ACC1:conc#381.itm(1)} {ACC1:conc#381.itm(2)} -attr xrf 18301 -attr oid 447 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#381.itm}
+load net {ACC1:slc#44.itm(0)} -attr vt d
+load net {ACC1:slc#44.itm(1)} -attr vt d
+load netBundle {ACC1:slc#44.itm} 2 {ACC1:slc#44.itm(0)} {ACC1:slc#44.itm(1)} -attr xrf 18302 -attr oid 448 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#44.itm}
+load net {ACC1:acc#196.itm(0)} -attr vt d
+load net {ACC1:acc#196.itm(1)} -attr vt d
+load net {ACC1:acc#196.itm(2)} -attr vt d
+load netBundle {ACC1:acc#196.itm} 3 {ACC1:acc#196.itm(0)} {ACC1:acc#196.itm(1)} {ACC1:acc#196.itm(2)} -attr xrf 18303 -attr oid 449 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#196.itm}
+load net {conc#369.itm(0)} -attr vt d
+load net {conc#369.itm(1)} -attr vt d
+load netBundle {conc#369.itm} 2 {conc#369.itm(0)} {conc#369.itm(1)} -attr xrf 18304 -attr oid 450 -attr vt d -attr @path {/sobel/sobel:core/conc#369.itm}
+load net {ACC1:conc#375.itm(0)} -attr vt d
+load net {ACC1:conc#375.itm(1)} -attr vt d
+load netBundle {ACC1:conc#375.itm} 2 {ACC1:conc#375.itm(0)} {ACC1:conc#375.itm(1)} -attr xrf 18305 -attr oid 451 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#375.itm}
+load net {ACC1:conc#383.itm(0)} -attr vt d
+load net {ACC1:conc#383.itm(1)} -attr vt d
+load net {ACC1:conc#383.itm(2)} -attr vt d
+load net {ACC1:conc#383.itm(3)} -attr vt d
+load netBundle {ACC1:conc#383.itm} 4 {ACC1:conc#383.itm(0)} {ACC1:conc#383.itm(1)} {ACC1:conc#383.itm(2)} {ACC1:conc#383.itm(3)} -attr xrf 18306 -attr oid 452 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#383.itm}
+load net {ACC1:slc#46.itm(0)} -attr vt d
+load net {ACC1:slc#46.itm(1)} -attr vt d
+load net {ACC1:slc#46.itm(2)} -attr vt d
+load netBundle {ACC1:slc#46.itm} 3 {ACC1:slc#46.itm(0)} {ACC1:slc#46.itm(1)} {ACC1:slc#46.itm(2)} -attr xrf 18307 -attr oid 453 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#46.itm}
+load net {ACC1:acc#198.itm(0)} -attr vt d
+load net {ACC1:acc#198.itm(1)} -attr vt d
+load net {ACC1:acc#198.itm(2)} -attr vt d
+load net {ACC1:acc#198.itm(3)} -attr vt d
+load netBundle {ACC1:acc#198.itm} 4 {ACC1:acc#198.itm(0)} {ACC1:acc#198.itm(1)} {ACC1:acc#198.itm(2)} {ACC1:acc#198.itm(3)} -attr xrf 18308 -attr oid 454 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {conc#370.itm(0)} -attr vt d
+load net {conc#370.itm(1)} -attr vt d
+load net {conc#370.itm(2)} -attr vt d
+load netBundle {conc#370.itm} 3 {conc#370.itm(0)} {conc#370.itm(1)} {conc#370.itm(2)} -attr xrf 18309 -attr oid 455 -attr vt d -attr @path {/sobel/sobel:core/conc#370.itm}
+load net {ACC1:slc#43.itm(0)} -attr vt d
+load net {ACC1:slc#43.itm(1)} -attr vt d
+load netBundle {ACC1:slc#43.itm} 2 {ACC1:slc#43.itm(0)} {ACC1:slc#43.itm(1)} -attr xrf 18310 -attr oid 456 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#43.itm}
+load net {ACC1:acc#195.itm(0)} -attr vt d
+load net {ACC1:acc#195.itm(1)} -attr vt d
+load net {ACC1:acc#195.itm(2)} -attr vt d
+load netBundle {ACC1:acc#195.itm} 3 {ACC1:acc#195.itm(0)} {ACC1:acc#195.itm(1)} {ACC1:acc#195.itm(2)} -attr xrf 18311 -attr oid 457 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load net {conc#371.itm(0)} -attr vt d
+load net {conc#371.itm(1)} -attr vt d
+load netBundle {conc#371.itm} 2 {conc#371.itm(0)} {conc#371.itm(1)} -attr xrf 18312 -attr oid 458 -attr vt d -attr @path {/sobel/sobel:core/conc#371.itm}
+load net {ACC1:conc#373.itm(0)} -attr vt d
+load net {ACC1:conc#373.itm(1)} -attr vt d
+load netBundle {ACC1:conc#373.itm} 2 {ACC1:conc#373.itm(0)} {ACC1:conc#373.itm(1)} -attr xrf 18313 -attr oid 459 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#373.itm}
+load net {ACC1:conc#379.itm(0)} -attr vt d
+load net {ACC1:conc#379.itm(1)} -attr vt d
+load net {ACC1:conc#379.itm(2)} -attr vt d
+load netBundle {ACC1:conc#379.itm} 3 {ACC1:conc#379.itm(0)} {ACC1:conc#379.itm(1)} {ACC1:conc#379.itm(2)} -attr xrf 18314 -attr oid 460 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#379.itm}
+load net {ACC1:slc#42.itm(0)} -attr vt d
+load net {ACC1:slc#42.itm(1)} -attr vt d
+load netBundle {ACC1:slc#42.itm} 2 {ACC1:slc#42.itm(0)} {ACC1:slc#42.itm(1)} -attr xrf 18315 -attr oid 461 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#42.itm}
+load net {ACC1:acc#194.itm(0)} -attr vt d
+load net {ACC1:acc#194.itm(1)} -attr vt d
+load net {ACC1:acc#194.itm(2)} -attr vt d
+load netBundle {ACC1:acc#194.itm} 3 {ACC1:acc#194.itm(0)} {ACC1:acc#194.itm(1)} {ACC1:acc#194.itm(2)} -attr xrf 18316 -attr oid 462 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load net {conc#372.itm(0)} -attr vt d
+load net {conc#372.itm(1)} -attr vt d
+load netBundle {conc#372.itm} 2 {conc#372.itm(0)} {conc#372.itm(1)} -attr xrf 18317 -attr oid 463 -attr vt d -attr @path {/sobel/sobel:core/conc#372.itm}
+load net {ACC1:conc#371.itm(0)} -attr vt d
+load net {ACC1:conc#371.itm(1)} -attr vt d
+load netBundle {ACC1:conc#371.itm} 2 {ACC1:conc#371.itm(0)} {ACC1:conc#371.itm(1)} -attr xrf 18318 -attr oid 464 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#371.itm}
+load net {conc#373.itm(0)} -attr vt d
+load net {conc#373.itm(1)} -attr vt d
+load net {conc#373.itm(2)} -attr vt d
+load net {conc#373.itm(3)} -attr vt d
+load net {conc#373.itm(4)} -attr vt d
+load net {conc#373.itm(5)} -attr vt d
+load netBundle {conc#373.itm} 6 {conc#373.itm(0)} {conc#373.itm(1)} {conc#373.itm(2)} {conc#373.itm(3)} {conc#373.itm(4)} {conc#373.itm(5)} -attr xrf 18319 -attr oid 465 -attr vt d -attr @path {/sobel/sobel:core/conc#373.itm}
+load net {ACC1:acc#174.itm(0)} -attr vt d
+load net {ACC1:acc#174.itm(1)} -attr vt d
+load net {ACC1:acc#174.itm(2)} -attr vt d
+load net {ACC1:acc#174.itm(3)} -attr vt d
+load net {ACC1:acc#174.itm(4)} -attr vt d
+load net {ACC1:acc#174.itm(5)} -attr vt d
+load netBundle {ACC1:acc#174.itm} 6 {ACC1:acc#174.itm(0)} {ACC1:acc#174.itm(1)} {ACC1:acc#174.itm(2)} {ACC1:acc#174.itm(3)} {ACC1:acc#174.itm(4)} {ACC1:acc#174.itm(5)} -attr xrf 18320 -attr oid 466 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {conc#374.itm(0)} -attr vt d
+load net {conc#374.itm(1)} -attr vt d
+load net {conc#374.itm(2)} -attr vt d
+load net {conc#374.itm(3)} -attr vt d
+load net {conc#374.itm(4)} -attr vt d
+load net {conc#374.itm(5)} -attr vt d
+load netBundle {conc#374.itm} 6 {conc#374.itm(0)} {conc#374.itm(1)} {conc#374.itm(2)} {conc#374.itm(3)} {conc#374.itm(4)} {conc#374.itm(5)} -attr xrf 18321 -attr oid 467 -attr vt d -attr @path {/sobel/sobel:core/conc#374.itm}
+load net {ACC1:slc#23.itm(0)} -attr vt d
+load net {ACC1:slc#23.itm(1)} -attr vt d
+load net {ACC1:slc#23.itm(2)} -attr vt d
+load net {ACC1:slc#23.itm(3)} -attr vt d
+load net {ACC1:slc#23.itm(4)} -attr vt d
+load netBundle {ACC1:slc#23.itm} 5 {ACC1:slc#23.itm(0)} {ACC1:slc#23.itm(1)} {ACC1:slc#23.itm(2)} {ACC1:slc#23.itm(3)} {ACC1:slc#23.itm(4)} -attr xrf 18322 -attr oid 468 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#23.itm}
+load net {ACC1:acc#173.itm(0)} -attr vt d
+load net {ACC1:acc#173.itm(1)} -attr vt d
+load net {ACC1:acc#173.itm(2)} -attr vt d
+load net {ACC1:acc#173.itm(3)} -attr vt d
+load net {ACC1:acc#173.itm(4)} -attr vt d
+load net {ACC1:acc#173.itm(5)} -attr vt d
+load netBundle {ACC1:acc#173.itm} 6 {ACC1:acc#173.itm(0)} {ACC1:acc#173.itm(1)} {ACC1:acc#173.itm(2)} {ACC1:acc#173.itm(3)} {ACC1:acc#173.itm(4)} {ACC1:acc#173.itm(5)} -attr xrf 18323 -attr oid 469 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load net {conc#375.itm(0)} -attr vt d
+load net {conc#375.itm(1)} -attr vt d
+load net {conc#375.itm(2)} -attr vt d
+load net {conc#375.itm(3)} -attr vt d
+load net {conc#375.itm(4)} -attr vt d
+load netBundle {conc#375.itm} 5 {conc#375.itm(0)} {conc#375.itm(1)} {conc#375.itm(2)} {conc#375.itm(3)} {conc#375.itm(4)} -attr xrf 18324 -attr oid 470 -attr vt d -attr @path {/sobel/sobel:core/conc#375.itm}
+load net {ACC1:slc#22.itm(0)} -attr vt d
+load net {ACC1:slc#22.itm(1)} -attr vt d
+load net {ACC1:slc#22.itm(2)} -attr vt d
+load net {ACC1:slc#22.itm(3)} -attr vt d
+load netBundle {ACC1:slc#22.itm} 4 {ACC1:slc#22.itm(0)} {ACC1:slc#22.itm(1)} {ACC1:slc#22.itm(2)} {ACC1:slc#22.itm(3)} -attr xrf 18325 -attr oid 471 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#22.itm}
+load net {ACC1:acc#172.itm(0)} -attr vt d
+load net {ACC1:acc#172.itm(1)} -attr vt d
+load net {ACC1:acc#172.itm(2)} -attr vt d
+load net {ACC1:acc#172.itm(3)} -attr vt d
+load net {ACC1:acc#172.itm(4)} -attr vt d
+load netBundle {ACC1:acc#172.itm} 5 {ACC1:acc#172.itm(0)} {ACC1:acc#172.itm(1)} {ACC1:acc#172.itm(2)} {ACC1:acc#172.itm(3)} {ACC1:acc#172.itm(4)} -attr xrf 18326 -attr oid 472 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load net {conc#376.itm(0)} -attr vt d
+load net {conc#376.itm(1)} -attr vt d
+load net {conc#376.itm(2)} -attr vt d
+load net {conc#376.itm(3)} -attr vt d
+load netBundle {conc#376.itm} 4 {conc#376.itm(0)} {conc#376.itm(1)} {conc#376.itm(2)} {conc#376.itm(3)} -attr xrf 18327 -attr oid 473 -attr vt d -attr @path {/sobel/sobel:core/conc#376.itm}
+load net {ACC1:slc#20.itm(0)} -attr vt d
+load net {ACC1:slc#20.itm(1)} -attr vt d
+load net {ACC1:slc#20.itm(2)} -attr vt d
+load netBundle {ACC1:slc#20.itm} 3 {ACC1:slc#20.itm(0)} {ACC1:slc#20.itm(1)} {ACC1:slc#20.itm(2)} -attr xrf 18328 -attr oid 474 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#20.itm}
+load net {ACC1:acc#170.itm(0)} -attr vt d
+load net {ACC1:acc#170.itm(1)} -attr vt d
+load net {ACC1:acc#170.itm(2)} -attr vt d
+load net {ACC1:acc#170.itm(3)} -attr vt d
+load netBundle {ACC1:acc#170.itm} 4 {ACC1:acc#170.itm(0)} {ACC1:acc#170.itm(1)} {ACC1:acc#170.itm(2)} {ACC1:acc#170.itm(3)} -attr xrf 18329 -attr oid 475 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170.itm}
+load net {conc#377.itm(0)} -attr vt d
+load net {conc#377.itm(1)} -attr vt d
+load net {conc#377.itm(2)} -attr vt d
+load netBundle {conc#377.itm} 3 {conc#377.itm(0)} {conc#377.itm(1)} {conc#377.itm(2)} -attr xrf 18330 -attr oid 476 -attr vt d -attr @path {/sobel/sobel:core/conc#377.itm}
+load net {ACC1:slc#16.itm(0)} -attr vt d
+load net {ACC1:slc#16.itm(1)} -attr vt d
+load netBundle {ACC1:slc#16.itm} 2 {ACC1:slc#16.itm(0)} {ACC1:slc#16.itm(1)} -attr xrf 18331 -attr oid 477 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#16.itm}
+load net {ACC1:acc#166.itm(0)} -attr vt d
+load net {ACC1:acc#166.itm(1)} -attr vt d
+load net {ACC1:acc#166.itm(2)} -attr vt d
+load netBundle {ACC1:acc#166.itm} 3 {ACC1:acc#166.itm(0)} {ACC1:acc#166.itm(1)} {ACC1:acc#166.itm(2)} -attr xrf 18332 -attr oid 478 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load net {conc#378.itm(0)} -attr vt d
+load net {conc#378.itm(1)} -attr vt d
+load netBundle {conc#378.itm} 2 {conc#378.itm(0)} {conc#378.itm(1)} -attr xrf 18333 -attr oid 479 -attr vt d -attr @path {/sobel/sobel:core/conc#378.itm}
+load net {conc#379.itm(0)} -attr vt d
+load net {conc#379.itm(1)} -attr vt d
+load netBundle {conc#379.itm} 2 {conc#379.itm(0)} {conc#379.itm(1)} -attr xrf 18334 -attr oid 480 -attr vt d -attr @path {/sobel/sobel:core/conc#379.itm}
+load net {ACC1:conc#323.itm(0)} -attr vt d
+load net {ACC1:conc#323.itm(1)} -attr vt d
+load netBundle {ACC1:conc#323.itm} 2 {ACC1:conc#323.itm(0)} {ACC1:conc#323.itm(1)} -attr xrf 18335 -attr oid 481 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#323.itm}
+load net {ACC1:conc#327.itm(0)} -attr vt d
+load net {ACC1:conc#327.itm(1)} -attr vt d
+load net {ACC1:conc#327.itm(2)} -attr vt d
+load netBundle {ACC1:conc#327.itm} 3 {ACC1:conc#327.itm(0)} {ACC1:conc#327.itm(1)} {ACC1:conc#327.itm(2)} -attr xrf 18336 -attr oid 482 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#327.itm}
+load net {ACC1:slc#19.itm(0)} -attr vt d
+load net {ACC1:slc#19.itm(1)} -attr vt d
+load netBundle {ACC1:slc#19.itm} 2 {ACC1:slc#19.itm(0)} {ACC1:slc#19.itm(1)} -attr xrf 18337 -attr oid 483 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#19.itm}
+load net {ACC1:acc#169.itm(0)} -attr vt d
+load net {ACC1:acc#169.itm(1)} -attr vt d
+load net {ACC1:acc#169.itm(2)} -attr vt d
+load netBundle {ACC1:acc#169.itm} 3 {ACC1:acc#169.itm(0)} {ACC1:acc#169.itm(1)} {ACC1:acc#169.itm(2)} -attr xrf 18338 -attr oid 484 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load net {conc#380.itm(0)} -attr vt d
+load net {conc#380.itm(1)} -attr vt d
+load netBundle {conc#380.itm} 2 {conc#380.itm(0)} {conc#380.itm(1)} -attr xrf 18339 -attr oid 485 -attr vt d -attr @path {/sobel/sobel:core/conc#380.itm}
+load net {ACC1:conc#321.itm(0)} -attr vt d
+load net {ACC1:conc#321.itm(1)} -attr vt d
+load netBundle {ACC1:conc#321.itm} 2 {ACC1:conc#321.itm(0)} {ACC1:conc#321.itm(1)} -attr xrf 18340 -attr oid 486 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#321.itm}
+load net {ACC1:conc#329.itm(0)} -attr vt d
+load net {ACC1:conc#329.itm(1)} -attr vt d
+load net {ACC1:conc#329.itm(2)} -attr vt d
+load net {ACC1:conc#329.itm(3)} -attr vt d
+load netBundle {ACC1:conc#329.itm} 4 {ACC1:conc#329.itm(0)} {ACC1:conc#329.itm(1)} {ACC1:conc#329.itm(2)} {ACC1:conc#329.itm(3)} -attr xrf 18341 -attr oid 487 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#329.itm}
+load net {ACC1:slc#21.itm(0)} -attr vt d
+load net {ACC1:slc#21.itm(1)} -attr vt d
+load net {ACC1:slc#21.itm(2)} -attr vt d
+load netBundle {ACC1:slc#21.itm} 3 {ACC1:slc#21.itm(0)} {ACC1:slc#21.itm(1)} {ACC1:slc#21.itm(2)} -attr xrf 18342 -attr oid 488 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#21.itm}
+load net {ACC1:acc#171.itm(0)} -attr vt d
+load net {ACC1:acc#171.itm(1)} -attr vt d
+load net {ACC1:acc#171.itm(2)} -attr vt d
+load net {ACC1:acc#171.itm(3)} -attr vt d
+load netBundle {ACC1:acc#171.itm} 4 {ACC1:acc#171.itm(0)} {ACC1:acc#171.itm(1)} {ACC1:acc#171.itm(2)} {ACC1:acc#171.itm(3)} -attr xrf 18343 -attr oid 489 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {conc#381.itm(0)} -attr vt d
+load net {conc#381.itm(1)} -attr vt d
+load net {conc#381.itm(2)} -attr vt d
+load netBundle {conc#381.itm} 3 {conc#381.itm(0)} {conc#381.itm(1)} {conc#381.itm(2)} -attr xrf 18344 -attr oid 490 -attr vt d -attr @path {/sobel/sobel:core/conc#381.itm}
+load net {ACC1:slc#18.itm(0)} -attr vt d
+load net {ACC1:slc#18.itm(1)} -attr vt d
+load netBundle {ACC1:slc#18.itm} 2 {ACC1:slc#18.itm(0)} {ACC1:slc#18.itm(1)} -attr xrf 18345 -attr oid 491 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#18.itm}
+load net {ACC1:acc#168.itm(0)} -attr vt d
+load net {ACC1:acc#168.itm(1)} -attr vt d
+load net {ACC1:acc#168.itm(2)} -attr vt d
+load netBundle {ACC1:acc#168.itm} 3 {ACC1:acc#168.itm(0)} {ACC1:acc#168.itm(1)} {ACC1:acc#168.itm(2)} -attr xrf 18346 -attr oid 492 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168.itm}
+load net {conc#382.itm(0)} -attr vt d
+load net {conc#382.itm(1)} -attr vt d
+load netBundle {conc#382.itm} 2 {conc#382.itm(0)} {conc#382.itm(1)} -attr xrf 18347 -attr oid 493 -attr vt d -attr @path {/sobel/sobel:core/conc#382.itm}
+load net {ACC1:conc#319.itm(0)} -attr vt d
+load net {ACC1:conc#319.itm(1)} -attr vt d
+load netBundle {ACC1:conc#319.itm} 2 {ACC1:conc#319.itm(0)} {ACC1:conc#319.itm(1)} -attr xrf 18348 -attr oid 494 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#319.itm}
+load net {ACC1:conc#325.itm(0)} -attr vt d
+load net {ACC1:conc#325.itm(1)} -attr vt d
+load net {ACC1:conc#325.itm(2)} -attr vt d
+load netBundle {ACC1:conc#325.itm} 3 {ACC1:conc#325.itm(0)} {ACC1:conc#325.itm(1)} {ACC1:conc#325.itm(2)} -attr xrf 18349 -attr oid 495 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#325.itm}
+load net {ACC1:slc#17.itm(0)} -attr vt d
+load net {ACC1:slc#17.itm(1)} -attr vt d
+load netBundle {ACC1:slc#17.itm} 2 {ACC1:slc#17.itm(0)} {ACC1:slc#17.itm(1)} -attr xrf 18350 -attr oid 496 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#17.itm}
+load net {ACC1:acc#167.itm(0)} -attr vt d
+load net {ACC1:acc#167.itm(1)} -attr vt d
+load net {ACC1:acc#167.itm(2)} -attr vt d
+load netBundle {ACC1:acc#167.itm} 3 {ACC1:acc#167.itm(0)} {ACC1:acc#167.itm(1)} {ACC1:acc#167.itm(2)} -attr xrf 18351 -attr oid 497 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load net {conc#383.itm(0)} -attr vt d
+load net {conc#383.itm(1)} -attr vt d
+load netBundle {conc#383.itm} 2 {conc#383.itm(0)} {conc#383.itm(1)} -attr xrf 18352 -attr oid 498 -attr vt d -attr @path {/sobel/sobel:core/conc#383.itm}
+load net {ACC1:conc#317.itm(0)} -attr vt d
+load net {ACC1:conc#317.itm(1)} -attr vt d
+load netBundle {ACC1:conc#317.itm} 2 {ACC1:conc#317.itm(0)} {ACC1:conc#317.itm(1)} -attr xrf 18353 -attr oid 499 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#317.itm}
+load net {conc#384.itm(0)} -attr vt d
+load net {conc#384.itm(1)} -attr vt d
+load net {conc#384.itm(2)} -attr vt d
+load net {conc#384.itm(3)} -attr vt d
+load net {conc#384.itm(4)} -attr vt d
+load net {conc#384.itm(5)} -attr vt d
+load netBundle {conc#384.itm} 6 {conc#384.itm(0)} {conc#384.itm(1)} {conc#384.itm(2)} {conc#384.itm(3)} {conc#384.itm(4)} {conc#384.itm(5)} -attr xrf 18354 -attr oid 500 -attr vt d -attr @path {/sobel/sobel:core/conc#384.itm}
+load net {ACC1:slc#51.itm(0)} -attr vt d
+load net {ACC1:slc#51.itm(1)} -attr vt d
+load net {ACC1:slc#51.itm(2)} -attr vt d
+load netBundle {ACC1:slc#51.itm} 3 {ACC1:slc#51.itm(0)} {ACC1:slc#51.itm(1)} {ACC1:slc#51.itm(2)} -attr xrf 18355 -attr oid 501 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#51.itm}
+load net {ACC1:acc#203.itm(0)} -attr vt d
+load net {ACC1:acc#203.itm(1)} -attr vt d
+load net {ACC1:acc#203.itm(2)} -attr vt d
+load net {ACC1:acc#203.itm(3)} -attr vt d
+load netBundle {ACC1:acc#203.itm} 4 {ACC1:acc#203.itm(0)} {ACC1:acc#203.itm(1)} {ACC1:acc#203.itm(2)} {ACC1:acc#203.itm(3)} -attr xrf 18356 -attr oid 502 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {conc#385.itm(0)} -attr vt d
+load net {conc#385.itm(1)} -attr vt d
+load net {conc#385.itm(2)} -attr vt d
+load netBundle {conc#385.itm} 3 {conc#385.itm(0)} {conc#385.itm(1)} {conc#385.itm(2)} -attr xrf 18357 -attr oid 503 -attr vt d -attr @path {/sobel/sobel:core/conc#385.itm}
+load net {ACC1:slc#50.itm(0)} -attr vt d
+load net {ACC1:slc#50.itm(1)} -attr vt d
+load netBundle {ACC1:slc#50.itm} 2 {ACC1:slc#50.itm(0)} {ACC1:slc#50.itm(1)} -attr xrf 18358 -attr oid 504 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#202.itm(0)} -attr vt d
+load net {ACC1:acc#202.itm(1)} -attr vt d
+load net {ACC1:acc#202.itm(2)} -attr vt d
+load netBundle {ACC1:acc#202.itm} 3 {ACC1:acc#202.itm(0)} {ACC1:acc#202.itm(1)} {ACC1:acc#202.itm(2)} -attr xrf 18359 -attr oid 505 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {conc#386.itm(0)} -attr vt d
+load net {conc#386.itm(1)} -attr vt d
+load netBundle {conc#386.itm} 2 {conc#386.itm(0)} {conc#386.itm(1)} -attr xrf 18360 -attr oid 506 -attr vt d -attr @path {/sobel/sobel:core/conc#386.itm}
+load net {conc#387.itm(0)} -attr vt d
+load net {conc#387.itm(1)} -attr vt d
+load netBundle {conc#387.itm} 2 {conc#387.itm(0)} {conc#387.itm(1)} -attr xrf 18361 -attr oid 507 -attr vt d -attr @path {/sobel/sobel:core/conc#387.itm}
+load net {ACC1:conc#390.itm(0)} -attr vt d
+load net {ACC1:conc#390.itm(1)} -attr vt d
+load netBundle {ACC1:conc#390.itm} 2 {ACC1:conc#390.itm(0)} {ACC1:conc#390.itm(1)} -attr xrf 18362 -attr oid 508 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#390.itm}
+load net {conc#388.itm(0)} -attr vt d
+load net {conc#388.itm(1)} -attr vt d
+load net {conc#388.itm(2)} -attr vt d
+load netBundle {conc#388.itm} 3 {conc#388.itm(0)} {conc#388.itm(1)} {conc#388.itm(2)} -attr xrf 18363 -attr oid 509 -attr vt d -attr @path {/sobel/sobel:core/conc#388.itm}
+load net {ACC1:acc#205.itm(0)} -attr vt d
+load net {ACC1:acc#205.itm(1)} -attr vt d
+load net {ACC1:acc#205.itm(2)} -attr vt d
+load netBundle {ACC1:acc#205.itm} 3 {ACC1:acc#205.itm(0)} {ACC1:acc#205.itm(1)} {ACC1:acc#205.itm(2)} -attr xrf 18364 -attr oid 510 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:conc#270.itm(0)} -attr vt d
+load net {ACC1:conc#270.itm(1)} -attr vt d
+load netBundle {ACC1:conc#270.itm} 2 {ACC1:conc#270.itm(0)} {ACC1:conc#270.itm(1)} -attr xrf 18365 -attr oid 511 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#270.itm}
+load net {conc#389.itm(0)} -attr vt d
+load net {conc#389.itm(1)} -attr vt d
+load netBundle {conc#389.itm} 2 {conc#389.itm(0)} {conc#389.itm(1)} -attr xrf 18366 -attr oid 512 -attr vt d -attr @path {/sobel/sobel:core/conc#389.itm}
+load net {ACC1:acc#204.itm(0)} -attr vt d
+load net {ACC1:acc#204.itm(1)} -attr vt d
+load net {ACC1:acc#204.itm(2)} -attr vt d
+load netBundle {ACC1:acc#204.itm} 3 {ACC1:acc#204.itm(0)} {ACC1:acc#204.itm(1)} {ACC1:acc#204.itm(2)} -attr xrf 18367 -attr oid 513 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:conc#272.itm(0)} -attr vt d
+load net {ACC1:conc#272.itm(1)} -attr vt d
+load netBundle {ACC1:conc#272.itm} 2 {ACC1:conc#272.itm(0)} {ACC1:conc#272.itm(1)} -attr xrf 18368 -attr oid 514 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#272.itm}
+load net {ACC1:conc#273.itm(0)} -attr vt d
+load net {ACC1:conc#273.itm(1)} -attr vt d
+load netBundle {ACC1:conc#273.itm} 2 {ACC1:conc#273.itm(0)} {ACC1:conc#273.itm(1)} -attr xrf 18369 -attr oid 515 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#273.itm}
+load net {conc#390.itm(0)} -attr vt d
+load net {conc#390.itm(1)} -attr vt d
+load net {conc#390.itm(2)} -attr vt d
+load netBundle {conc#390.itm} 3 {conc#390.itm(0)} {conc#390.itm(1)} {conc#390.itm(2)} -attr xrf 18370 -attr oid 516 -attr vt d -attr @path {/sobel/sobel:core/conc#390.itm}
+load net {ACC1:conc#397.itm(0)} -attr vt d
+load net {ACC1:conc#397.itm(1)} -attr vt d
+load netBundle {ACC1:conc#397.itm} 2 {ACC1:conc#397.itm(0)} {ACC1:conc#397.itm(1)} -attr xrf 18371 -attr oid 517 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#397.itm}
+load net {conc#391.itm(0)} -attr vt d
+load net {conc#391.itm(1)} -attr vt d
+load net {conc#391.itm(2)} -attr vt d
+load netBundle {conc#391.itm} 3 {conc#391.itm(0)} {conc#391.itm(1)} {conc#391.itm(2)} -attr xrf 18372 -attr oid 518 -attr vt d -attr @path {/sobel/sobel:core/conc#391.itm}
+load net {ACC1:conc#400.itm(0)} -attr vt d
+load net {ACC1:conc#400.itm(1)} -attr vt d
+load netBundle {ACC1:conc#400.itm} 2 {ACC1:conc#400.itm(0)} {ACC1:conc#400.itm(1)} -attr xrf 18373 -attr oid 519 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#400.itm}
+load net {ACC1:slc#40.itm(0)} -attr vt d
+load net {ACC1:slc#40.itm(1)} -attr vt d
+load net {ACC1:slc#40.itm(2)} -attr vt d
+load netBundle {ACC1:slc#40.itm} 3 {ACC1:slc#40.itm(0)} {ACC1:slc#40.itm(1)} {ACC1:slc#40.itm(2)} -attr xrf 18374 -attr oid 520 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1:acc#191.itm(0)} -attr vt d
+load net {ACC1:acc#191.itm(1)} -attr vt d
+load net {ACC1:acc#191.itm(2)} -attr vt d
+load net {ACC1:acc#191.itm(3)} -attr vt d
+load netBundle {ACC1:acc#191.itm} 4 {ACC1:acc#191.itm(0)} {ACC1:acc#191.itm(1)} {ACC1:acc#191.itm(2)} {ACC1:acc#191.itm(3)} -attr xrf 18375 -attr oid 521 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load net {conc#392.itm(0)} -attr vt d
+load net {conc#392.itm(1)} -attr vt d
+load net {conc#392.itm(2)} -attr vt d
+load netBundle {conc#392.itm} 3 {conc#392.itm(0)} {conc#392.itm(1)} {conc#392.itm(2)} -attr xrf 18376 -attr oid 522 -attr vt d -attr @path {/sobel/sobel:core/conc#392.itm}
+load net {ACC1:slc#39.itm(0)} -attr vt d
+load net {ACC1:slc#39.itm(1)} -attr vt d
+load netBundle {ACC1:slc#39.itm} 2 {ACC1:slc#39.itm(0)} {ACC1:slc#39.itm(1)} -attr xrf 18377 -attr oid 523 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#39.itm}
+load net {ACC1:acc#190.itm(0)} -attr vt d
+load net {ACC1:acc#190.itm(1)} -attr vt d
+load net {ACC1:acc#190.itm(2)} -attr vt d
+load netBundle {ACC1:acc#190.itm} 3 {ACC1:acc#190.itm(0)} {ACC1:acc#190.itm(1)} {ACC1:acc#190.itm(2)} -attr xrf 18378 -attr oid 524 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load net {conc#393.itm(0)} -attr vt d
+load net {conc#393.itm(1)} -attr vt d
+load netBundle {conc#393.itm} 2 {conc#393.itm(0)} {conc#393.itm(1)} -attr xrf 18379 -attr oid 525 -attr vt d -attr @path {/sobel/sobel:core/conc#393.itm}
+load net {conc#394.itm(0)} -attr vt d
+load net {conc#394.itm(1)} -attr vt d
+load netBundle {conc#394.itm} 2 {conc#394.itm(0)} {conc#394.itm(1)} -attr xrf 18380 -attr oid 526 -attr vt d -attr @path {/sobel/sobel:core/conc#394.itm}
+load net {ACC1:conc#366.itm(0)} -attr vt d
+load net {ACC1:conc#366.itm(1)} -attr vt d
+load netBundle {ACC1:conc#366.itm} 2 {ACC1:conc#366.itm(0)} {ACC1:conc#366.itm(1)} -attr xrf 18381 -attr oid 527 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#366.itm}
+load net {conc#395.itm(0)} -attr vt d
+load net {conc#395.itm(1)} -attr vt d
+load net {conc#395.itm(2)} -attr vt d
+load netBundle {conc#395.itm} 3 {conc#395.itm(0)} {conc#395.itm(1)} {conc#395.itm(2)} -attr xrf 18382 -attr oid 528 -attr vt d -attr @path {/sobel/sobel:core/conc#395.itm}
+load net {ACC1:slc#26.itm(0)} -attr vt d
+load net {ACC1:slc#26.itm(1)} -attr vt d
+load net {ACC1:slc#26.itm(2)} -attr vt d
+load netBundle {ACC1:slc#26.itm} 3 {ACC1:slc#26.itm(0)} {ACC1:slc#26.itm(1)} {ACC1:slc#26.itm(2)} -attr xrf 18383 -attr oid 529 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#176.itm(0)} -attr vt d
+load net {ACC1:acc#176.itm(1)} -attr vt d
+load net {ACC1:acc#176.itm(2)} -attr vt d
+load net {ACC1:acc#176.itm(3)} -attr vt d
+load netBundle {ACC1:acc#176.itm} 4 {ACC1:acc#176.itm(0)} {ACC1:acc#176.itm(1)} {ACC1:acc#176.itm(2)} {ACC1:acc#176.itm(3)} -attr xrf 18384 -attr oid 530 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {conc#396.itm(0)} -attr vt d
+load net {conc#396.itm(1)} -attr vt d
+load net {conc#396.itm(2)} -attr vt d
+load netBundle {conc#396.itm} 3 {conc#396.itm(0)} {conc#396.itm(1)} {conc#396.itm(2)} -attr xrf 18385 -attr oid 531 -attr vt d -attr @path {/sobel/sobel:core/conc#396.itm}
+load net {ACC1:slc#25.itm(0)} -attr vt d
+load net {ACC1:slc#25.itm(1)} -attr vt d
+load netBundle {ACC1:slc#25.itm} 2 {ACC1:slc#25.itm(0)} {ACC1:slc#25.itm(1)} -attr xrf 18386 -attr oid 532 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#25.itm}
+load net {ACC1:acc#175.itm(0)} -attr vt d
+load net {ACC1:acc#175.itm(1)} -attr vt d
+load net {ACC1:acc#175.itm(2)} -attr vt d
+load netBundle {ACC1:acc#175.itm} 3 {ACC1:acc#175.itm(0)} {ACC1:acc#175.itm(1)} {ACC1:acc#175.itm(2)} -attr xrf 18387 -attr oid 533 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load net {conc#397.itm(0)} -attr vt d
+load net {conc#397.itm(1)} -attr vt d
+load netBundle {conc#397.itm} 2 {conc#397.itm(0)} {conc#397.itm(1)} -attr xrf 18388 -attr oid 534 -attr vt d -attr @path {/sobel/sobel:core/conc#397.itm}
+load net {conc#398.itm(0)} -attr vt d
+load net {conc#398.itm(1)} -attr vt d
+load netBundle {conc#398.itm} 2 {conc#398.itm(0)} {conc#398.itm(1)} -attr xrf 18389 -attr oid 535 -attr vt d -attr @path {/sobel/sobel:core/conc#398.itm}
+load net {ACC1:conc#336.itm(0)} -attr vt d
+load net {ACC1:conc#336.itm(1)} -attr vt d
+load netBundle {ACC1:conc#336.itm} 2 {ACC1:conc#336.itm(0)} {ACC1:conc#336.itm(1)} -attr xrf 18390 -attr oid 536 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#336.itm}
+load net {conc#399.itm(0)} -attr vt d
+load net {conc#399.itm(1)} -attr vt d
+load net {conc#399.itm(2)} -attr vt d
+load netBundle {conc#399.itm} 3 {conc#399.itm(0)} {conc#399.itm(1)} {conc#399.itm(2)} -attr xrf 18391 -attr oid 537 -attr vt d -attr @path {/sobel/sobel:core/conc#399.itm}
+load net {clk} -attr xrf 18392 -attr oid 538
+load net {clk} -port {clk} -attr xrf 18393 -attr oid 539
+load net {en} -attr xrf 18394 -attr oid 540
+load net {en} -port {en} -attr xrf 18395 -attr oid 541
+load net {arst_n} -attr xrf 18396 -attr oid 542
+load net {arst_n} -port {arst_n} -attr xrf 18397 -attr oid 543
+load net {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 18398 -attr oid 544 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(0)} -port {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -port {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -port {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -port {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -port {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -port {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -port {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -port {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -port {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -port {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -port {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -port {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -port {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -port {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -port {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -port {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -port {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -port {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -port {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -port {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -port {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -port {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -port {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -port {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -port {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -port {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -port {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -port {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -port {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -port {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -port {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -port {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -port {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -port {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -port {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -port {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -port {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -port {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -port {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -port {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -port {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -port {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -port {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -port {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -port {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -port {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -port {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -port {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -port {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -port {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -port {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -port {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -port {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -port {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -port {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -port {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -port {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -port {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -port {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -port {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -port {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -port {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -port {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -port {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -port {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -port {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -port {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -port {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -port {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -port {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -port {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -port {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -port {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -port {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -port {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -port {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -port {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -port {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -port {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -port {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -port {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -port {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -port {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -port {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -port {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -port {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -port {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -port {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -port {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -port {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 18399 -attr oid 545 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d} 30 {vout:rsc:mgc_out_stdreg.d(0)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(29)} -attr xrf 18400 -attr oid 546 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -port {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -port {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -port {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -port {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -port {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -port {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -port {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -port {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -port {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -port {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -port {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -port {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -port {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -port {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -port {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -port {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -port {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -port {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -port {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -port {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -port {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -port {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -port {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -port {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -port {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -port {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -port {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -port {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -port {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -port {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:or" "or(2,10)" "INTERFACE" -attr xrf 18401 -attr oid 547 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or} -attr area 7.298324 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2)"
+load net {FRAME:acc#5.psp.sva(0)} -pin  "FRAME:or" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm}
+load net {FRAME:acc#5.psp.sva(1)} -pin  "FRAME:or" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm}
+load net {FRAME:acc#5.psp.sva(2)} -pin  "FRAME:or" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm}
+load net {FRAME:acc#5.psp.sva(3)} -pin  "FRAME:or" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm}
+load net {FRAME:acc#5.psp.sva(4)} -pin  "FRAME:or" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm}
+load net {FRAME:acc#5.psp.sva(5)} -pin  "FRAME:or" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm}
+load net {FRAME:acc#5.psp.sva(6)} -pin  "FRAME:or" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm}
+load net {FRAME:acc#5.psp.sva(7)} -pin  "FRAME:or" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm}
+load net {FRAME:acc#5.psp.sva(8)} -pin  "FRAME:or" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm}
+load net {FRAME:acc#5.psp.sva(9)} -pin  "FRAME:or" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#4.itm}
+load net {FRAME:acc#5.psp.sva(10)} -pin  "FRAME:or" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#309.itm}
+load net {FRAME:acc#5.psp.sva(11)} -pin  "FRAME:or" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#309.itm}
+load net {GND} -pin  "FRAME:or" {A1(2)} -attr @path {/sobel/sobel:core/conc#309.itm}
+load net {GND} -pin  "FRAME:or" {A1(3)} -attr @path {/sobel/sobel:core/conc#309.itm}
+load net {GND} -pin  "FRAME:or" {A1(4)} -attr @path {/sobel/sobel:core/conc#309.itm}
+load net {GND} -pin  "FRAME:or" {A1(5)} -attr @path {/sobel/sobel:core/conc#309.itm}
+load net {GND} -pin  "FRAME:or" {A1(6)} -attr @path {/sobel/sobel:core/conc#309.itm}
+load net {GND} -pin  "FRAME:or" {A1(7)} -attr @path {/sobel/sobel:core/conc#309.itm}
+load net {GND} -pin  "FRAME:or" {A1(8)} -attr @path {/sobel/sobel:core/conc#309.itm}
+load net {GND} -pin  "FRAME:or" {A1(9)} -attr @path {/sobel/sobel:core/conc#309.itm}
+load net {FRAME:or.itm(0)} -pin  "FRAME:or" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(1)} -pin  "FRAME:or" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(2)} -pin  "FRAME:or" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(3)} -pin  "FRAME:or" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(4)} -pin  "FRAME:or" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(5)} -pin  "FRAME:or" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(6)} -pin  "FRAME:or" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(7)} -pin  "FRAME:or" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(8)} -pin  "FRAME:or" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(9)} -pin  "FRAME:or" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load inst "FRAME:or#3" "or(2,6)" "INTERFACE" -attr xrf 18402 -attr oid 548 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3} -attr area 4.378994 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2)"
+load net {FRAME:acc#5.psp.sva(0)} -pin  "FRAME:or#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(1)} -pin  "FRAME:or#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(2)} -pin  "FRAME:or#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(3)} -pin  "FRAME:or#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(4)} -pin  "FRAME:or#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(5)} -pin  "FRAME:or#3" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#5.psp.sva)#3.itm}
+load net {FRAME:acc#5.psp.sva(10)} -pin  "FRAME:or#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#310.itm}
+load net {FRAME:acc#5.psp.sva(11)} -pin  "FRAME:or#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#310.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(2)} -attr @path {/sobel/sobel:core/conc#310.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(3)} -attr @path {/sobel/sobel:core/conc#310.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(4)} -attr @path {/sobel/sobel:core/conc#310.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(5)} -attr @path {/sobel/sobel:core/conc#310.itm}
+load net {FRAME:or#3.itm(0)} -pin  "FRAME:or#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(1)} -pin  "FRAME:or#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(2)} -pin  "FRAME:or#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(3)} -pin  "FRAME:or#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(4)} -pin  "FRAME:or#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(5)} -pin  "FRAME:or#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load inst "mux" "mux(2,30)" "INTERFACE" -attr xrf 18403 -attr oid 549 -attr vt d -attr @path {/sobel/sobel:core/mux} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {FRAME:acc#5.psp.sva(0)} -pin  "mux" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:acc#5.psp.sva(1)} -pin  "mux" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:acc#5.psp.sva(2)} -pin  "mux" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:acc#5.psp.sva(3)} -pin  "mux" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:acc#5.psp.sva(4)} -pin  "mux" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:acc#5.psp.sva(5)} -pin  "mux" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:acc#5.psp.sva(6)} -pin  "mux" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:acc#5.psp.sva(7)} -pin  "mux" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:acc#5.psp.sva(8)} -pin  "mux" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:acc#5.psp.sva(9)} -pin  "mux" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or#3.itm(0)} -pin  "mux" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or#3.itm(1)} -pin  "mux" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or#3.itm(2)} -pin  "mux" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or#3.itm(3)} -pin  "mux" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or#3.itm(4)} -pin  "mux" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or#3.itm(5)} -pin  "mux" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:acc#5.psp.sva(6)} -pin  "mux" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:acc#5.psp.sva(7)} -pin  "mux" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:acc#5.psp.sva(8)} -pin  "mux" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:acc#5.psp.sva(9)} -pin  "mux" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or.itm(0)} -pin  "mux" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or.itm(1)} -pin  "mux" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or.itm(2)} -pin  "mux" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or.itm(3)} -pin  "mux" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or.itm(4)} -pin  "mux" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or.itm(5)} -pin  "mux" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or.itm(6)} -pin  "mux" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or.itm(7)} -pin  "mux" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or.itm(8)} -pin  "mux" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {FRAME:or.itm(9)} -pin  "mux" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#22.itm}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "mux" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "mux" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "mux" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "mux" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "mux" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "mux" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "mux" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "mux" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "mux" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "mux" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "mux" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "mux" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "mux" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "mux" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "mux" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "mux" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "mux" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "mux" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "mux" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "mux" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {main.stage_0#3} -pin  "mux" {S(0)} -attr @path {/sobel/sobel:core/main.stage_0#3}
+load net {mux.itm(0)} -pin  "mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "mux" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "mux" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "mux" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "mux" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "mux" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "mux" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "mux" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "mux" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "mux" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "mux" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "mux" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "mux" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "mux" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "mux" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "mux" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "mux" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "mux" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "mux" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "mux" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "mux" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 18404 -attr oid 550 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)}
+load net {mux.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#7}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 18405 -attr oid 551 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "reg(intensity:slc(intensity#2.sg1)#9.itm#1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 18406 -attr oid 552 -attr vt d -attr @path {/sobel/sobel:core/reg(intensity:slc(intensity#2.sg1)#9.itm#1)}
+load net {ACC1:acc.itm(13)} -pin  "reg(intensity:slc(intensity#2.sg1)#9.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#4.itm}
+load net {ACC1:acc.itm(14)} -pin  "reg(intensity:slc(intensity#2.sg1)#9.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#4.itm}
+load net {GND} -pin  "reg(intensity:slc(intensity#2.sg1)#9.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(intensity:slc(intensity#2.sg1)#9.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(intensity:slc(intensity#2.sg1)#9.itm#1)" {clk} -attr xrf 18407 -attr oid 553 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(intensity:slc(intensity#2.sg1)#9.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(intensity:slc(intensity#2.sg1)#9.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {intensity:slc(intensity#2.sg1)#9.itm#1(0)} -pin  "reg(intensity:slc(intensity#2.sg1)#9.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1)#9.itm#1}
+load net {intensity:slc(intensity#2.sg1)#9.itm#1(1)} -pin  "reg(intensity:slc(intensity#2.sg1)#9.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1)#9.itm#1}
+load inst "reg(intensity:slc(intensity#2.sg1)#11.itm#1)" "reg(3,1,1,-1,0)" "INTERFACE" -attr xrf 18408 -attr oid 554 -attr vt d -attr @path {/sobel/sobel:core/reg(intensity:slc(intensity#2.sg1)#11.itm#1)}
+load net {ACC1:acc.itm(10)} -pin  "reg(intensity:slc(intensity#2.sg1)#11.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#3.itm}
+load net {ACC1:acc.itm(11)} -pin  "reg(intensity:slc(intensity#2.sg1)#11.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#3.itm}
+load net {ACC1:acc.itm(12)} -pin  "reg(intensity:slc(intensity#2.sg1)#11.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#3.itm}
+load net {GND} -pin  "reg(intensity:slc(intensity#2.sg1)#11.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {GND} -pin  "reg(intensity:slc(intensity#2.sg1)#11.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {GND} -pin  "reg(intensity:slc(intensity#2.sg1)#11.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {clk} -pin  "reg(intensity:slc(intensity#2.sg1)#11.itm#1)" {clk} -attr xrf 18409 -attr oid 555 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(intensity:slc(intensity#2.sg1)#11.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(intensity:slc(intensity#2.sg1)#11.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {intensity:slc(intensity#2.sg1)#11.itm#1(0)} -pin  "reg(intensity:slc(intensity#2.sg1)#11.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1)#11.itm#1}
+load net {intensity:slc(intensity#2.sg1)#11.itm#1(1)} -pin  "reg(intensity:slc(intensity#2.sg1)#11.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1)#11.itm#1}
+load net {intensity:slc(intensity#2.sg1)#11.itm#1(2)} -pin  "reg(intensity:slc(intensity#2.sg1)#11.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1)#11.itm#1}
+load inst "reg(intensity:slc(intensity#2.sg1).itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 18410 -attr oid 556 -attr vt d -attr @path {/sobel/sobel:core/reg(intensity:slc(intensity#2.sg1).itm#1)}
+load net {ACC1:acc.itm(4)} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(5)} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(6)} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(7)} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(8)} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(9)} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {GND} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {clk} -attr xrf 18411 -attr oid 557 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {intensity:slc(intensity#2.sg1).itm#1(0)} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1).itm#1}
+load net {intensity:slc(intensity#2.sg1).itm#1(1)} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1).itm#1}
+load net {intensity:slc(intensity#2.sg1).itm#1(2)} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1).itm#1}
+load net {intensity:slc(intensity#2.sg1).itm#1(3)} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1).itm#1}
+load net {intensity:slc(intensity#2.sg1).itm#1(4)} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1).itm#1}
+load net {intensity:slc(intensity#2.sg1).itm#1(5)} -pin  "reg(intensity:slc(intensity#2.sg1).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1).itm#1}
+load inst "reg(intensity:slc(intensity#2.sg1)#12.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 18412 -attr oid 558 -attr @path {/sobel/sobel:core/reg(intensity:slc(intensity#2.sg1)#12.itm#1)}
+load net {ACC1:acc.itm(15)} -pin  "reg(intensity:slc(intensity#2.sg1)#12.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva).itm}
+load net {GND} -pin  "reg(intensity:slc(intensity#2.sg1)#12.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(intensity:slc(intensity#2.sg1)#12.itm#1)" {clk} -attr xrf 18413 -attr oid 559 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(intensity:slc(intensity#2.sg1)#12.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(intensity:slc(intensity#2.sg1)#12.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {intensity:slc(intensity#2.sg1)#12.itm#1} -pin  "reg(intensity:slc(intensity#2.sg1)#12.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1)#12.itm#1}
+load inst "FRAME:not#26" "not(3)" "INTERFACE" -attr xrf 18414 -attr oid 560 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#26} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(10)} -pin  "FRAME:not#26" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#9.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:not#26" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#9.itm}
+load net {ACC1:acc.itm(12)} -pin  "FRAME:not#26" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#9.itm}
+load net {FRAME:not#26.itm(0)} -pin  "FRAME:not#26" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#26.itm}
+load net {FRAME:not#26.itm(1)} -pin  "FRAME:not#26" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#26.itm}
+load net {FRAME:not#26.itm(2)} -pin  "FRAME:not#26" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#26.itm}
+load inst "FRAME:acc#9" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18415 -attr oid 561 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#9} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc.itm(7)} -pin  "FRAME:acc#9" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#8.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:acc#9" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#8.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:acc#9" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#8.itm}
+load net {FRAME:not#26.itm(0)} -pin  "FRAME:acc#9" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#26.itm}
+load net {FRAME:not#26.itm(1)} -pin  "FRAME:acc#9" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#26.itm}
+load net {FRAME:not#26.itm(2)} -pin  "FRAME:acc#9" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#26.itm}
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#9" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#9" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#9" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#9" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load inst "FRAME:not#36" "not(1)" "INTERFACE" -attr xrf 18416 -attr oid 562 -attr @path {/sobel/sobel:core/FRAME:not#36} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc.itm(15)} -pin  "FRAME:not#36" {A(0)} -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#12.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:not#36" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#36.itm}
+load inst "FRAME:not#38" "not(1)" "INTERFACE" -attr xrf 18417 -attr oid 563 -attr @path {/sobel/sobel:core/FRAME:not#38} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc.itm(15)} -pin  "FRAME:not#38" {A(0)} -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#7.itm}
+load net {FRAME:not#38.itm} -pin  "FRAME:not#38" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#38.itm}
+load inst "FRAME:acc#8" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 18418 -attr oid 564 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#38.itm} -pin  "FRAME:acc#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#311.itm}
+load net {PWR} -pin  "FRAME:acc#8" {A(1)} -attr @path {/sobel/sobel:core/conc#311.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:acc#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#311.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#10.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#10.itm}
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load inst "FRAME:acc#11" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 18419 -attr oid 565 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#11" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#11" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#11" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#11" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#11" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#11" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#11" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#11" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#11" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#11" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#11" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#11" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "FRAME:acc#11" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load inst "FRAME:not#25" "not(3)" "INTERFACE" -attr xrf 18420 -attr oid 566 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(4)} -pin  "FRAME:not#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#6.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:not#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#6.itm}
+load net {ACC1:acc.itm(6)} -pin  "FRAME:not#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#6.itm}
+load net {FRAME:not#25.itm(0)} -pin  "FRAME:not#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:not#25.itm(1)} -pin  "FRAME:not#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:not#25.itm(2)} -pin  "FRAME:not#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load inst "FRAME:acc#10" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18421 -attr oid 567 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc.itm(1)} -pin  "FRAME:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#5.itm}
+load net {ACC1:acc.itm(2)} -pin  "FRAME:acc#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#5.itm}
+load net {ACC1:acc.itm(3)} -pin  "FRAME:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#5.itm}
+load net {FRAME:not#25.itm(0)} -pin  "FRAME:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:not#25.itm(1)} -pin  "FRAME:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:not#25.itm(2)} -pin  "FRAME:acc#10" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#25.itm}
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load inst "FRAME:acc#12" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 18422 -attr oid 568 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#12} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#12" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#12" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#12" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#12" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "FRAME:acc#12" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#12" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#12" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#12" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#12" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#12" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#12" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(4)} -pin  "FRAME:acc#12" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(5)} -pin  "FRAME:acc#12" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load inst "reg(FRAME:acc#12.itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 18423 -attr oid 569 -attr vt dc -attr @path {/sobel/sobel:core/reg(FRAME:acc#12.itm#1)}
+load net {FRAME:acc#12.itm(0)} -pin  "reg(FRAME:acc#12.itm#1)" {D(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "reg(FRAME:acc#12.itm#1)" {D(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "reg(FRAME:acc#12.itm#1)" {D(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "reg(FRAME:acc#12.itm#1)" {D(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(4)} -pin  "reg(FRAME:acc#12.itm#1)" {D(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(5)} -pin  "reg(FRAME:acc#12.itm#1)" {D(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {GND} -pin  "reg(FRAME:acc#12.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#12.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#12.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#12.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#12.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#12.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(FRAME:acc#12.itm#1)" {clk} -attr xrf 18424 -attr oid 570 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#12.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#12.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#12.itm#1(0)} -pin  "reg(FRAME:acc#12.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm#1}
+load net {FRAME:acc#12.itm#1(1)} -pin  "reg(FRAME:acc#12.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm#1}
+load net {FRAME:acc#12.itm#1(2)} -pin  "reg(FRAME:acc#12.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm#1}
+load net {FRAME:acc#12.itm#1(3)} -pin  "reg(FRAME:acc#12.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm#1}
+load net {FRAME:acc#12.itm#1(4)} -pin  "reg(FRAME:acc#12.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm#1}
+load net {FRAME:acc#12.itm#1(5)} -pin  "reg(FRAME:acc#12.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm#1}
+load inst "reg(main.stage_0#2)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 18425 -attr oid 571 -attr @path {/sobel/sobel:core/reg(main.stage_0#2)}
+load net {PWR} -pin  "reg(main.stage_0#2)" {D(0)} -attr @path {/sobel/sobel:core/C1365_11#67}
+load net {GND} -pin  "reg(main.stage_0#2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(main.stage_0#2)" {clk} -attr xrf 18426 -attr oid 572 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(main.stage_0#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(main.stage_0#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {main.stage_0#2} -pin  "reg(main.stage_0#2)" {Z(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load inst "reg(main.stage_0#3)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 18427 -attr oid 573 -attr @path {/sobel/sobel:core/reg(main.stage_0#3)}
+load net {main.stage_0#2} -pin  "reg(main.stage_0#3)" {D(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {GND} -pin  "reg(main.stage_0#3)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(main.stage_0#3)" {clk} -attr xrf 18428 -attr oid 574 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(main.stage_0#3)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(main.stage_0#3)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {main.stage_0#3} -pin  "reg(main.stage_0#3)" {Z(0)} -attr @path {/sobel/sobel:core/main.stage_0#3}
+load inst "ACC1:acc#144" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18429 -attr oid 575 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv.sva(15)} -pin  "ACC1:acc#144" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#9.itm}
+load net {acc.idiv#2.sva(15)} -pin  "ACC1:acc#144" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#37.itm}
+load net {ACC1:acc#144.itm(0)} -pin  "ACC1:acc#144" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144.itm}
+load net {ACC1:acc#144.itm(1)} -pin  "ACC1:acc#144" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144.itm}
+load inst "ACC1:mul#101" "mul(2,0,11,0,12)" "INTERFACE" -attr xrf 18430 -attr oid 576 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,11,0,12)"
+load net {ACC1:acc#144.itm(0)} -pin  "ACC1:mul#101" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144.itm}
+load net {ACC1:acc#144.itm(1)} -pin  "ACC1:mul#101" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144.itm}
+load net {PWR} -pin  "ACC1:mul#101" {B(0)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#101" {B(1)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#101" {B(2)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#101" {B(3)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#101" {B(4)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#101" {B(5)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#101" {B(6)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#101" {B(7)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#101" {B(8)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#101" {B(9)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#101" {B(10)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {ACC1:mul#101.itm(0)} -pin  "ACC1:mul#101" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101.itm}
+load net {ACC1:mul#101.itm(1)} -pin  "ACC1:mul#101" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101.itm}
+load net {ACC1:mul#101.itm(2)} -pin  "ACC1:mul#101" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101.itm}
+load net {ACC1:mul#101.itm(3)} -pin  "ACC1:mul#101" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101.itm}
+load net {ACC1:mul#101.itm(4)} -pin  "ACC1:mul#101" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101.itm}
+load net {ACC1:mul#101.itm(5)} -pin  "ACC1:mul#101" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101.itm}
+load net {ACC1:mul#101.itm(6)} -pin  "ACC1:mul#101" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101.itm}
+load net {ACC1:mul#101.itm(7)} -pin  "ACC1:mul#101" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101.itm}
+load net {ACC1:mul#101.itm(8)} -pin  "ACC1:mul#101" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101.itm}
+load net {ACC1:mul#101.itm(9)} -pin  "ACC1:mul#101" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101.itm}
+load net {ACC1:mul#101.itm(10)} -pin  "ACC1:mul#101" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101.itm}
+load net {ACC1:mul#101.itm(11)} -pin  "ACC1:mul#101" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#101.itm}
+load inst "ACC1:acc#138" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18431 -attr oid 577 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv#3.sva(12)} -pin  "ACC1:acc#138" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#33.itm}
+load net {acc.idiv#7.sva(12)} -pin  "ACC1:acc#138" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#25.itm}
+load net {ACC1:acc#138.itm(0)} -pin  "ACC1:acc#138" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {ACC1:acc#138.itm(1)} -pin  "ACC1:acc#138" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load inst "ACC1:mul#95" "mul(2,0,11,0,12)" "INTERFACE" -attr xrf 18432 -attr oid 578 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,11,0,12)"
+load net {ACC1:acc#138.itm(0)} -pin  "ACC1:mul#95" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {ACC1:acc#138.itm(1)} -pin  "ACC1:mul#95" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {PWR} -pin  "ACC1:mul#95" {B(0)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#95" {B(1)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#95" {B(2)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#95" {B(3)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#95" {B(4)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#95" {B(5)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#95" {B(6)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#95" {B(7)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#95" {B(8)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#95" {B(9)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#95" {B(10)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {ACC1:mul#95.itm(0)} -pin  "ACC1:mul#95" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95.itm}
+load net {ACC1:mul#95.itm(1)} -pin  "ACC1:mul#95" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95.itm}
+load net {ACC1:mul#95.itm(2)} -pin  "ACC1:mul#95" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95.itm}
+load net {ACC1:mul#95.itm(3)} -pin  "ACC1:mul#95" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95.itm}
+load net {ACC1:mul#95.itm(4)} -pin  "ACC1:mul#95" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95.itm}
+load net {ACC1:mul#95.itm(5)} -pin  "ACC1:mul#95" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95.itm}
+load net {ACC1:mul#95.itm(6)} -pin  "ACC1:mul#95" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95.itm}
+load net {ACC1:mul#95.itm(7)} -pin  "ACC1:mul#95" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95.itm}
+load net {ACC1:mul#95.itm(8)} -pin  "ACC1:mul#95" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95.itm}
+load net {ACC1:mul#95.itm(9)} -pin  "ACC1:mul#95" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95.itm}
+load net {ACC1:mul#95.itm(10)} -pin  "ACC1:mul#95" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95.itm}
+load net {ACC1:mul#95.itm(11)} -pin  "ACC1:mul#95" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#95.itm}
+load inst "ACC1:acc#143" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18433 -attr oid 579 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv.sva(13)} -pin  "ACC1:acc#143" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#8.itm}
+load net {acc.idiv#2.sva(13)} -pin  "ACC1:acc#143" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#21.itm}
+load net {ACC1:acc#143.itm(0)} -pin  "ACC1:acc#143" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(1)} -pin  "ACC1:acc#143" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load inst "ACC1:mul#100" "mul(2,0,9,0,10)" "INTERFACE" -attr xrf 18434 -attr oid 580 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#100} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC1:acc#143.itm(0)} -pin  "ACC1:mul#100" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(1)} -pin  "ACC1:mul#100" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {PWR} -pin  "ACC1:mul#100" {B(0)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#100" {B(1)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#100" {B(2)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#100" {B(3)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#100" {B(4)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#100" {B(5)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#100" {B(6)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#100" {B(7)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#100" {B(8)} -attr @path {/sobel/sobel:core/C341_9}
+load net {ACC1:mul#100.itm(0)} -pin  "ACC1:mul#100" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#100.itm}
+load net {ACC1:mul#100.itm(1)} -pin  "ACC1:mul#100" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#100.itm}
+load net {ACC1:mul#100.itm(2)} -pin  "ACC1:mul#100" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#100.itm}
+load net {ACC1:mul#100.itm(3)} -pin  "ACC1:mul#100" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#100.itm}
+load net {ACC1:mul#100.itm(4)} -pin  "ACC1:mul#100" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#100.itm}
+load net {ACC1:mul#100.itm(5)} -pin  "ACC1:mul#100" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#100.itm}
+load net {ACC1:mul#100.itm(6)} -pin  "ACC1:mul#100" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#100.itm}
+load net {ACC1:mul#100.itm(7)} -pin  "ACC1:mul#100" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#100.itm}
+load net {ACC1:mul#100.itm(8)} -pin  "ACC1:mul#100" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#100.itm}
+load net {ACC1:mul#100.itm(9)} -pin  "ACC1:mul#100" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#100.itm}
+load inst "ACC1:acc#272" "add(13,0,13,0,14)" "INTERFACE" -attr xrf 18435 -attr oid 581 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272} -attr area 14.215154 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,0,13,0,14)"
+load net {ACC1:acc#189.itm(3)} -pin  "ACC1:acc#272" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {ACC1:mul#95.itm(0)} -pin  "ACC1:acc#272" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {ACC1:mul#95.itm(1)} -pin  "ACC1:acc#272" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {ACC1:mul#95.itm(2)} -pin  "ACC1:acc#272" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {ACC1:mul#95.itm(3)} -pin  "ACC1:acc#272" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {ACC1:mul#95.itm(4)} -pin  "ACC1:acc#272" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {ACC1:mul#95.itm(5)} -pin  "ACC1:acc#272" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {ACC1:mul#95.itm(6)} -pin  "ACC1:acc#272" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {ACC1:mul#95.itm(7)} -pin  "ACC1:acc#272" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {ACC1:mul#95.itm(8)} -pin  "ACC1:acc#272" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {ACC1:mul#95.itm(9)} -pin  "ACC1:acc#272" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {ACC1:mul#95.itm(10)} -pin  "ACC1:acc#272" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {ACC1:mul#95.itm(11)} -pin  "ACC1:acc#272" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#253.itm}
+load net {acc.idiv#3.sva(5)} -pin  "ACC1:acc#272" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {acc.idiv#3.sva(5)} -pin  "ACC1:acc#272" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {acc.idiv#7.sva(3)} -pin  "ACC1:acc#272" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {ACC1:mul#100.itm(0)} -pin  "ACC1:acc#272" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {ACC1:mul#100.itm(1)} -pin  "ACC1:acc#272" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {ACC1:mul#100.itm(2)} -pin  "ACC1:acc#272" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {ACC1:mul#100.itm(3)} -pin  "ACC1:acc#272" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {ACC1:mul#100.itm(4)} -pin  "ACC1:acc#272" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {ACC1:mul#100.itm(5)} -pin  "ACC1:acc#272" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {ACC1:mul#100.itm(6)} -pin  "ACC1:acc#272" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {ACC1:mul#100.itm(7)} -pin  "ACC1:acc#272" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {ACC1:mul#100.itm(8)} -pin  "ACC1:acc#272" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {ACC1:mul#100.itm(9)} -pin  "ACC1:acc#272" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#276.itm}
+load net {ACC1:acc#272.itm(0)} -pin  "ACC1:acc#272" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(1)} -pin  "ACC1:acc#272" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(2)} -pin  "ACC1:acc#272" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(3)} -pin  "ACC1:acc#272" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(4)} -pin  "ACC1:acc#272" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(5)} -pin  "ACC1:acc#272" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(6)} -pin  "ACC1:acc#272" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(7)} -pin  "ACC1:acc#272" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(8)} -pin  "ACC1:acc#272" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(9)} -pin  "ACC1:acc#272" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(10)} -pin  "ACC1:acc#272" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(11)} -pin  "ACC1:acc#272" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(12)} -pin  "ACC1:acc#272" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(13)} -pin  "ACC1:acc#272" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load inst "ACC1:acc#275" "add(15,0,14,0,16)" "INTERFACE" -attr xrf 18436 -attr oid 582 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275} -attr area 16.197770 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,15,0,16)"
+load net {acc.idiv.sva(17)} -pin  "ACC1:acc#275" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {acc.idiv.sva(17)} -pin  "ACC1:acc#275" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:acc#174.itm(4)} -pin  "ACC1:acc#275" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:mul#101.itm(0)} -pin  "ACC1:acc#275" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:mul#101.itm(1)} -pin  "ACC1:acc#275" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:mul#101.itm(2)} -pin  "ACC1:acc#275" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:mul#101.itm(3)} -pin  "ACC1:acc#275" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:mul#101.itm(4)} -pin  "ACC1:acc#275" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:mul#101.itm(5)} -pin  "ACC1:acc#275" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:mul#101.itm(6)} -pin  "ACC1:acc#275" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:mul#101.itm(7)} -pin  "ACC1:acc#275" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:mul#101.itm(8)} -pin  "ACC1:acc#275" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:mul#101.itm(9)} -pin  "ACC1:acc#275" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:mul#101.itm(10)} -pin  "ACC1:acc#275" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:mul#101.itm(11)} -pin  "ACC1:acc#275" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#277.itm}
+load net {ACC1:acc#272.itm(0)} -pin  "ACC1:acc#275" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(1)} -pin  "ACC1:acc#275" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(2)} -pin  "ACC1:acc#275" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(3)} -pin  "ACC1:acc#275" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(4)} -pin  "ACC1:acc#275" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(5)} -pin  "ACC1:acc#275" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(6)} -pin  "ACC1:acc#275" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(7)} -pin  "ACC1:acc#275" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(8)} -pin  "ACC1:acc#275" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(9)} -pin  "ACC1:acc#275" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(10)} -pin  "ACC1:acc#275" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(11)} -pin  "ACC1:acc#275" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(12)} -pin  "ACC1:acc#275" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(13)} -pin  "ACC1:acc#275" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#275.itm(0)} -pin  "ACC1:acc#275" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(1)} -pin  "ACC1:acc#275" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(2)} -pin  "ACC1:acc#275" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(3)} -pin  "ACC1:acc#275" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(4)} -pin  "ACC1:acc#275" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(5)} -pin  "ACC1:acc#275" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(6)} -pin  "ACC1:acc#275" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(7)} -pin  "ACC1:acc#275" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(8)} -pin  "ACC1:acc#275" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(9)} -pin  "ACC1:acc#275" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(10)} -pin  "ACC1:acc#275" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(11)} -pin  "ACC1:acc#275" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(12)} -pin  "ACC1:acc#275" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(13)} -pin  "ACC1:acc#275" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(14)} -pin  "ACC1:acc#275" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(15)} -pin  "ACC1:acc#275" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load inst "ACC1:acc#140" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18437 -attr oid 583 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv#3.sva(16)} -pin  "ACC1:acc#140" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#38.itm}
+load net {acc.idiv#7.sva(16)} -pin  "ACC1:acc#140" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#32.itm}
+load net {ACC1:acc#140.itm(0)} -pin  "ACC1:acc#140" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load net {ACC1:acc#140.itm(1)} -pin  "ACC1:acc#140" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load inst "ACC1:mul#97" "mul(2,0,15,-1,15)" "INTERFACE" -attr xrf 18438 -attr oid 584 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,15,0,16)"
+load net {ACC1:acc#140.itm(0)} -pin  "ACC1:mul#97" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load net {ACC1:acc#140.itm(1)} -pin  "ACC1:mul#97" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load net {PWR} -pin  "ACC1:mul#97" {B(0)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {GND} -pin  "ACC1:mul#97" {B(1)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {PWR} -pin  "ACC1:mul#97" {B(2)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {GND} -pin  "ACC1:mul#97" {B(3)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {PWR} -pin  "ACC1:mul#97" {B(4)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {GND} -pin  "ACC1:mul#97" {B(5)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {PWR} -pin  "ACC1:mul#97" {B(6)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {GND} -pin  "ACC1:mul#97" {B(7)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {PWR} -pin  "ACC1:mul#97" {B(8)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {GND} -pin  "ACC1:mul#97" {B(9)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {PWR} -pin  "ACC1:mul#97" {B(10)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {GND} -pin  "ACC1:mul#97" {B(11)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {PWR} -pin  "ACC1:mul#97" {B(12)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {GND} -pin  "ACC1:mul#97" {B(13)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {PWR} -pin  "ACC1:mul#97" {B(14)} -attr @path {/sobel/sobel:core/Cn10923_15}
+load net {ACC1:mul#97.itm(0)} -pin  "ACC1:mul#97" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(1)} -pin  "ACC1:mul#97" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(2)} -pin  "ACC1:mul#97" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(3)} -pin  "ACC1:mul#97" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(4)} -pin  "ACC1:mul#97" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(5)} -pin  "ACC1:mul#97" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(6)} -pin  "ACC1:mul#97" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(7)} -pin  "ACC1:mul#97" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(8)} -pin  "ACC1:mul#97" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(9)} -pin  "ACC1:mul#97" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(10)} -pin  "ACC1:mul#97" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(11)} -pin  "ACC1:mul#97" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(12)} -pin  "ACC1:mul#97" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(13)} -pin  "ACC1:mul#97" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load net {ACC1:mul#97.itm(14)} -pin  "ACC1:mul#97" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#97.itm}
+load inst "ACC1:acc#279" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 18439 -attr oid 585 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,17)"
+load net {ACC1:acc#275.itm(0)} -pin  "ACC1:acc#279" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(1)} -pin  "ACC1:acc#279" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(2)} -pin  "ACC1:acc#279" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(3)} -pin  "ACC1:acc#279" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(4)} -pin  "ACC1:acc#279" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(5)} -pin  "ACC1:acc#279" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(6)} -pin  "ACC1:acc#279" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(7)} -pin  "ACC1:acc#279" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(8)} -pin  "ACC1:acc#279" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(9)} -pin  "ACC1:acc#279" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(10)} -pin  "ACC1:acc#279" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(11)} -pin  "ACC1:acc#279" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(12)} -pin  "ACC1:acc#279" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(13)} -pin  "ACC1:acc#279" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(14)} -pin  "ACC1:acc#279" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(15)} -pin  "ACC1:acc#279" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {acc.imod#1.sva(1)} -pin  "ACC1:acc#279" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(0)} -pin  "ACC1:acc#279" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(1)} -pin  "ACC1:acc#279" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(2)} -pin  "ACC1:acc#279" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(3)} -pin  "ACC1:acc#279" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(4)} -pin  "ACC1:acc#279" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(5)} -pin  "ACC1:acc#279" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(6)} -pin  "ACC1:acc#279" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(7)} -pin  "ACC1:acc#279" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(8)} -pin  "ACC1:acc#279" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(9)} -pin  "ACC1:acc#279" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(10)} -pin  "ACC1:acc#279" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(11)} -pin  "ACC1:acc#279" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(12)} -pin  "ACC1:acc#279" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(13)} -pin  "ACC1:acc#279" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:mul#97.itm(14)} -pin  "ACC1:acc#279" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#255.itm}
+load net {ACC1:acc#279.itm(0)} -pin  "ACC1:acc#279" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(1)} -pin  "ACC1:acc#279" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(2)} -pin  "ACC1:acc#279" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(3)} -pin  "ACC1:acc#279" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(4)} -pin  "ACC1:acc#279" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(5)} -pin  "ACC1:acc#279" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(6)} -pin  "ACC1:acc#279" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(7)} -pin  "ACC1:acc#279" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(8)} -pin  "ACC1:acc#279" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(9)} -pin  "ACC1:acc#279" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(10)} -pin  "ACC1:acc#279" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(11)} -pin  "ACC1:acc#279" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(12)} -pin  "ACC1:acc#279" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(13)} -pin  "ACC1:acc#279" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(14)} -pin  "ACC1:acc#279" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(15)} -pin  "ACC1:acc#279" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load inst "ACC1:acc#150" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18440 -attr oid 586 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv#3.sva(15)} -pin  "ACC1:acc#150" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#8.itm}
+load net {acc.idiv#7.sva(15)} -pin  "ACC1:acc#150" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#23.itm}
+load net {ACC1:acc#150.itm(0)} -pin  "ACC1:acc#150" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load net {ACC1:acc#150.itm(1)} -pin  "ACC1:acc#150" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load inst "ACC1:acc#149" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 18441 -attr oid 587 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#150.itm(0)} -pin  "ACC1:acc#149" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load net {ACC1:acc#150.itm(1)} -pin  "ACC1:acc#149" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load net {acc.idiv#7.sva(17)} -pin  "ACC1:acc#149" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#44.itm}
+load net {ACC1:acc#149.itm(0)} -pin  "ACC1:acc#149" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149.itm}
+load net {ACC1:acc#149.itm(1)} -pin  "ACC1:acc#149" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149.itm}
+load inst "ACC1:acc#148" "add(2,0,1,0,3)" "INTERFACE" -attr xrf 18442 -attr oid 588 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#149.itm(0)} -pin  "ACC1:acc#148" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149.itm}
+load net {ACC1:acc#149.itm(1)} -pin  "ACC1:acc#148" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149.itm}
+load net {acc.idiv#3.sva(17)} -pin  "ACC1:acc#148" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#6.itm}
+load net {ACC1:acc#148.itm(0)} -pin  "ACC1:acc#148" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {ACC1:acc#148.itm(1)} -pin  "ACC1:acc#148" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {ACC1:acc#148.itm(2)} -pin  "ACC1:acc#148" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load inst "ACC1:mul#105" "mul(3,0,11,0,12)" "INTERFACE" -attr xrf 18443 -attr oid 589 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,11,0,12)"
+load net {ACC1:acc#148.itm(0)} -pin  "ACC1:mul#105" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {ACC1:acc#148.itm(1)} -pin  "ACC1:mul#105" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {ACC1:acc#148.itm(2)} -pin  "ACC1:mul#105" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {PWR} -pin  "ACC1:mul#105" {B(0)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#105" {B(1)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#105" {B(2)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#105" {B(3)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#105" {B(4)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#105" {B(5)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#105" {B(6)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#105" {B(7)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#105" {B(8)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#105" {B(9)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#105" {B(10)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {ACC1:mul#105.itm(0)} -pin  "ACC1:mul#105" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105.itm}
+load net {ACC1:mul#105.itm(1)} -pin  "ACC1:mul#105" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105.itm}
+load net {ACC1:mul#105.itm(2)} -pin  "ACC1:mul#105" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105.itm}
+load net {ACC1:mul#105.itm(3)} -pin  "ACC1:mul#105" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105.itm}
+load net {ACC1:mul#105.itm(4)} -pin  "ACC1:mul#105" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105.itm}
+load net {ACC1:mul#105.itm(5)} -pin  "ACC1:mul#105" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105.itm}
+load net {ACC1:mul#105.itm(6)} -pin  "ACC1:mul#105" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105.itm}
+load net {ACC1:mul#105.itm(7)} -pin  "ACC1:mul#105" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105.itm}
+load net {ACC1:mul#105.itm(8)} -pin  "ACC1:mul#105" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105.itm}
+load net {ACC1:mul#105.itm(9)} -pin  "ACC1:mul#105" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105.itm}
+load net {ACC1:mul#105.itm(10)} -pin  "ACC1:mul#105" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105.itm}
+load net {ACC1:mul#105.itm(11)} -pin  "ACC1:mul#105" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#105.itm}
+load inst "ACC1:acc#151" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18444 -attr oid 590 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv.sva(16)} -pin  "ACC1:acc#151" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#25.itm}
+load net {acc.idiv#2.sva(16)} -pin  "ACC1:acc#151" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#22.itm}
+load net {ACC1:acc#151.itm(0)} -pin  "ACC1:acc#151" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151.itm}
+load net {ACC1:acc#151.itm(1)} -pin  "ACC1:acc#151" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151.itm}
+load inst "mul" "mul(2,0,15,0,16)" "INTERFACE" -attr xrf 18445 -attr oid 591 -attr vt d -attr @path {/sobel/sobel:core/mul} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,15,0,16)"
+load net {ACC1:acc#151.itm(0)} -pin  "mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151.itm}
+load net {ACC1:acc#151.itm(1)} -pin  "mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151.itm}
+load net {PWR} -pin  "mul" {B(0)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {GND} -pin  "mul" {B(1)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {PWR} -pin  "mul" {B(2)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {GND} -pin  "mul" {B(3)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {PWR} -pin  "mul" {B(4)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {GND} -pin  "mul" {B(5)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {PWR} -pin  "mul" {B(6)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {GND} -pin  "mul" {B(7)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {PWR} -pin  "mul" {B(8)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {GND} -pin  "mul" {B(9)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {PWR} -pin  "mul" {B(10)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {GND} -pin  "mul" {B(11)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {PWR} -pin  "mul" {B(12)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {GND} -pin  "mul" {B(13)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {PWR} -pin  "mul" {B(14)} -attr @path {/sobel/sobel:core/C21845_15}
+load net {mul.itm(0)} -pin  "mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(1)} -pin  "mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(2)} -pin  "mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(3)} -pin  "mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(4)} -pin  "mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(5)} -pin  "mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(6)} -pin  "mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(7)} -pin  "mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(8)} -pin  "mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(9)} -pin  "mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(10)} -pin  "mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(11)} -pin  "mul" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(12)} -pin  "mul" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(13)} -pin  "mul" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(14)} -pin  "mul" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(15)} -pin  "mul" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load inst "ACC1:acc#278" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 18446 -attr oid 592 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,17)"
+load net {acc.idiv#3.sva(7)} -pin  "ACC1:acc#278" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {acc.idiv#3.sva(7)} -pin  "ACC1:acc#278" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {GND} -pin  "ACC1:acc#278" {A(2)} -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {acc.idiv#2.sva(7)} -pin  "ACC1:acc#278" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {ACC1:mul#105.itm(0)} -pin  "ACC1:acc#278" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {ACC1:mul#105.itm(1)} -pin  "ACC1:acc#278" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {ACC1:mul#105.itm(2)} -pin  "ACC1:acc#278" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {ACC1:mul#105.itm(3)} -pin  "ACC1:acc#278" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {ACC1:mul#105.itm(4)} -pin  "ACC1:acc#278" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {ACC1:mul#105.itm(5)} -pin  "ACC1:acc#278" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {ACC1:mul#105.itm(6)} -pin  "ACC1:acc#278" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {ACC1:mul#105.itm(7)} -pin  "ACC1:acc#278" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {ACC1:mul#105.itm(8)} -pin  "ACC1:acc#278" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {ACC1:mul#105.itm(9)} -pin  "ACC1:acc#278" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {ACC1:mul#105.itm(10)} -pin  "ACC1:acc#278" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {ACC1:mul#105.itm(11)} -pin  "ACC1:acc#278" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/conc#312.itm}
+load net {mul.itm(0)} -pin  "ACC1:acc#278" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(1)} -pin  "ACC1:acc#278" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(2)} -pin  "ACC1:acc#278" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(3)} -pin  "ACC1:acc#278" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(4)} -pin  "ACC1:acc#278" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(5)} -pin  "ACC1:acc#278" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(6)} -pin  "ACC1:acc#278" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(7)} -pin  "ACC1:acc#278" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(8)} -pin  "ACC1:acc#278" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(9)} -pin  "ACC1:acc#278" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(10)} -pin  "ACC1:acc#278" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(11)} -pin  "ACC1:acc#278" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(12)} -pin  "ACC1:acc#278" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(13)} -pin  "ACC1:acc#278" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(14)} -pin  "ACC1:acc#278" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {mul.itm(15)} -pin  "ACC1:acc#278" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/mul.itm}
+load net {ACC1:acc#278.itm(0)} -pin  "ACC1:acc#278" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(1)} -pin  "ACC1:acc#278" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(2)} -pin  "ACC1:acc#278" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(3)} -pin  "ACC1:acc#278" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(4)} -pin  "ACC1:acc#278" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(5)} -pin  "ACC1:acc#278" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(6)} -pin  "ACC1:acc#278" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(7)} -pin  "ACC1:acc#278" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(8)} -pin  "ACC1:acc#278" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(9)} -pin  "ACC1:acc#278" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(10)} -pin  "ACC1:acc#278" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(11)} -pin  "ACC1:acc#278" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(12)} -pin  "ACC1:acc#278" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(13)} -pin  "ACC1:acc#278" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(14)} -pin  "ACC1:acc#278" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(15)} -pin  "ACC1:acc#278" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load inst "ACC1:acc#281" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 18447 -attr oid 593 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,17)"
+load net {ACC1:acc#279.itm(0)} -pin  "ACC1:acc#281" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(1)} -pin  "ACC1:acc#281" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(2)} -pin  "ACC1:acc#281" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(3)} -pin  "ACC1:acc#281" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(4)} -pin  "ACC1:acc#281" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(5)} -pin  "ACC1:acc#281" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(6)} -pin  "ACC1:acc#281" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(7)} -pin  "ACC1:acc#281" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(8)} -pin  "ACC1:acc#281" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(9)} -pin  "ACC1:acc#281" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(10)} -pin  "ACC1:acc#281" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(11)} -pin  "ACC1:acc#281" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(12)} -pin  "ACC1:acc#281" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(13)} -pin  "ACC1:acc#281" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(14)} -pin  "ACC1:acc#281" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(15)} -pin  "ACC1:acc#281" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#278.itm(0)} -pin  "ACC1:acc#281" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(1)} -pin  "ACC1:acc#281" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(2)} -pin  "ACC1:acc#281" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(3)} -pin  "ACC1:acc#281" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(4)} -pin  "ACC1:acc#281" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(5)} -pin  "ACC1:acc#281" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(6)} -pin  "ACC1:acc#281" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(7)} -pin  "ACC1:acc#281" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(8)} -pin  "ACC1:acc#281" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(9)} -pin  "ACC1:acc#281" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(10)} -pin  "ACC1:acc#281" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(11)} -pin  "ACC1:acc#281" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(12)} -pin  "ACC1:acc#281" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(13)} -pin  "ACC1:acc#281" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(14)} -pin  "ACC1:acc#281" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(15)} -pin  "ACC1:acc#281" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#281.itm(0)} -pin  "ACC1:acc#281" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(1)} -pin  "ACC1:acc#281" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(2)} -pin  "ACC1:acc#281" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(3)} -pin  "ACC1:acc#281" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(4)} -pin  "ACC1:acc#281" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(5)} -pin  "ACC1:acc#281" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(6)} -pin  "ACC1:acc#281" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(7)} -pin  "ACC1:acc#281" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(8)} -pin  "ACC1:acc#281" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(9)} -pin  "ACC1:acc#281" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(10)} -pin  "ACC1:acc#281" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(11)} -pin  "ACC1:acc#281" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(12)} -pin  "ACC1:acc#281" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(13)} -pin  "ACC1:acc#281" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(14)} -pin  "ACC1:acc#281" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(15)} -pin  "ACC1:acc#281" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load inst "reg(ACC1:acc#281.itm#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 18448 -attr oid 594 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#281.itm#1)}
+load net {ACC1:acc#281.itm(0)} -pin  "reg(ACC1:acc#281.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(1)} -pin  "reg(ACC1:acc#281.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(2)} -pin  "reg(ACC1:acc#281.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(3)} -pin  "reg(ACC1:acc#281.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(4)} -pin  "reg(ACC1:acc#281.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(5)} -pin  "reg(ACC1:acc#281.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(6)} -pin  "reg(ACC1:acc#281.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(7)} -pin  "reg(ACC1:acc#281.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(8)} -pin  "reg(ACC1:acc#281.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(9)} -pin  "reg(ACC1:acc#281.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(10)} -pin  "reg(ACC1:acc#281.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(11)} -pin  "reg(ACC1:acc#281.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(12)} -pin  "reg(ACC1:acc#281.itm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(13)} -pin  "reg(ACC1:acc#281.itm#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(14)} -pin  "reg(ACC1:acc#281.itm#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(15)} -pin  "reg(ACC1:acc#281.itm#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(ACC1:acc#281.itm#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(ACC1:acc#281.itm#1)" {clk} -attr xrf 18449 -attr oid 595 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#281.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#281.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#281.itm#1(0)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(1)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(2)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(3)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(4)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(5)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(6)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(7)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(8)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(9)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(10)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(11)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(12)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(13)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(14)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(15)} -pin  "reg(ACC1:acc#281.itm#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load inst "ACC1:acc#152" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18450 -attr oid 596 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv.sva(17)} -pin  "ACC1:acc#152" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#33.itm}
+load net {acc.idiv#2.sva(17)} -pin  "ACC1:acc#152" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#29.itm}
+load net {ACC1:acc#152.itm(0)} -pin  "ACC1:acc#152" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(1)} -pin  "ACC1:acc#152" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load inst "mul#1" "mul(2,0,13,-1,13)" "INTERFACE" -attr xrf 18451 -attr oid 597 -attr vt d -attr @path {/sobel/sobel:core/mul#1} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,13,0,14)"
+load net {ACC1:acc#152.itm(0)} -pin  "mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(1)} -pin  "mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {PWR} -pin  "mul#1" {B(0)} -attr @path {/sobel/sobel:core/Cn2731_13}
+load net {GND} -pin  "mul#1" {B(1)} -attr @path {/sobel/sobel:core/Cn2731_13}
+load net {PWR} -pin  "mul#1" {B(2)} -attr @path {/sobel/sobel:core/Cn2731_13}
+load net {GND} -pin  "mul#1" {B(3)} -attr @path {/sobel/sobel:core/Cn2731_13}
+load net {PWR} -pin  "mul#1" {B(4)} -attr @path {/sobel/sobel:core/Cn2731_13}
+load net {GND} -pin  "mul#1" {B(5)} -attr @path {/sobel/sobel:core/Cn2731_13}
+load net {PWR} -pin  "mul#1" {B(6)} -attr @path {/sobel/sobel:core/Cn2731_13}
+load net {GND} -pin  "mul#1" {B(7)} -attr @path {/sobel/sobel:core/Cn2731_13}
+load net {PWR} -pin  "mul#1" {B(8)} -attr @path {/sobel/sobel:core/Cn2731_13}
+load net {GND} -pin  "mul#1" {B(9)} -attr @path {/sobel/sobel:core/Cn2731_13}
+load net {PWR} -pin  "mul#1" {B(10)} -attr @path {/sobel/sobel:core/Cn2731_13}
+load net {GND} -pin  "mul#1" {B(11)} -attr @path {/sobel/sobel:core/Cn2731_13}
+load net {PWR} -pin  "mul#1" {B(12)} -attr @path {/sobel/sobel:core/Cn2731_13}
+load net {mul#1.itm(0)} -pin  "mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(1)} -pin  "mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(2)} -pin  "mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(3)} -pin  "mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(4)} -pin  "mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(5)} -pin  "mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(6)} -pin  "mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(7)} -pin  "mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(8)} -pin  "mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(9)} -pin  "mul#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(10)} -pin  "mul#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(11)} -pin  "mul#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(12)} -pin  "mul#1" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load inst "reg(mul#1.itm#1)" "reg(13,1,1,-1,0)" "INTERFACE" -attr xrf 18452 -attr oid 598 -attr vt d -attr @path {/sobel/sobel:core/reg(mul#1.itm#1)}
+load net {mul#1.itm(0)} -pin  "reg(mul#1.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(1)} -pin  "reg(mul#1.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(2)} -pin  "reg(mul#1.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(3)} -pin  "reg(mul#1.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(4)} -pin  "reg(mul#1.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(5)} -pin  "reg(mul#1.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(6)} -pin  "reg(mul#1.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(7)} -pin  "reg(mul#1.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(8)} -pin  "reg(mul#1.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(9)} -pin  "reg(mul#1.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(10)} -pin  "reg(mul#1.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(11)} -pin  "reg(mul#1.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {mul#1.itm(12)} -pin  "reg(mul#1.itm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm}
+load net {GND} -pin  "reg(mul#1.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(mul#1.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(mul#1.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(mul#1.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(mul#1.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(mul#1.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(mul#1.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(mul#1.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(mul#1.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(mul#1.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(mul#1.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(mul#1.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(mul#1.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_13}
+load net {clk} -pin  "reg(mul#1.itm#1)" {clk} -attr xrf 18453 -attr oid 599 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(mul#1.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(mul#1.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {mul#1.itm#1(0)} -pin  "reg(mul#1.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load net {mul#1.itm#1(1)} -pin  "reg(mul#1.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load net {mul#1.itm#1(2)} -pin  "reg(mul#1.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load net {mul#1.itm#1(3)} -pin  "reg(mul#1.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load net {mul#1.itm#1(4)} -pin  "reg(mul#1.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load net {mul#1.itm#1(5)} -pin  "reg(mul#1.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load net {mul#1.itm#1(6)} -pin  "reg(mul#1.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load net {mul#1.itm#1(7)} -pin  "reg(mul#1.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load net {mul#1.itm#1(8)} -pin  "reg(mul#1.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load net {mul#1.itm#1(9)} -pin  "reg(mul#1.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load net {mul#1.itm#1(10)} -pin  "reg(mul#1.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load net {mul#1.itm#1(11)} -pin  "reg(mul#1.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load net {mul#1.itm#1(12)} -pin  "reg(mul#1.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mul#1.itm#1}
+load inst "reg(ACC1-2:slc(acc.idiv)#131.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 18454 -attr oid 600 -attr @path {/sobel/sobel:core/reg(ACC1-2:slc(acc.idiv)#131.itm#1)}
+load net {acc.idiv#3.sva(13)} -pin  "reg(ACC1-2:slc(acc.idiv)#131.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#27.itm}
+load net {GND} -pin  "reg(ACC1-2:slc(acc.idiv)#131.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(ACC1-2:slc(acc.idiv)#131.itm#1)" {clk} -attr xrf 18455 -attr oid 601 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1-2:slc(acc.idiv)#131.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1-2:slc(acc.idiv)#131.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1-2:slc(acc.idiv)#131.itm#1} -pin  "reg(ACC1-2:slc(acc.idiv)#131.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:slc(acc.idiv)#131.itm#1}
+load inst "ACC1:acc#142" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18456 -attr oid 602 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv.sva(11)} -pin  "ACC1:acc#142" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#31.itm}
+load net {acc.idiv#2.sva(11)} -pin  "ACC1:acc#142" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#26.itm}
+load net {ACC1:acc#142.itm(0)} -pin  "ACC1:acc#142" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(1)} -pin  "ACC1:acc#142" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load inst "ACC1:mul#99" "mul(2,0,7,0,8)" "INTERFACE" -attr xrf 18457 -attr oid 603 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,7,0,8)"
+load net {ACC1:acc#142.itm(0)} -pin  "ACC1:mul#99" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(1)} -pin  "ACC1:mul#99" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {PWR} -pin  "ACC1:mul#99" {B(0)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#99" {B(1)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#99" {B(2)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#99" {B(3)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#99" {B(4)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#99" {B(5)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#99" {B(6)} -attr @path {/sobel/sobel:core/C85_7}
+load net {ACC1:mul#99.itm(0)} -pin  "ACC1:mul#99" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(1)} -pin  "ACC1:mul#99" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(2)} -pin  "ACC1:mul#99" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(3)} -pin  "ACC1:mul#99" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(4)} -pin  "ACC1:mul#99" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(5)} -pin  "ACC1:mul#99" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(6)} -pin  "ACC1:mul#99" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(7)} -pin  "ACC1:mul#99" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load inst "reg(ACC1:mul#99.itm#1)" "reg(8,1,1,-1,0)" "INTERFACE" -attr xrf 18458 -attr oid 604 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:mul#99.itm#1)}
+load net {ACC1:mul#99.itm(0)} -pin  "reg(ACC1:mul#99.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(1)} -pin  "reg(ACC1:mul#99.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(2)} -pin  "reg(ACC1:mul#99.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(3)} -pin  "reg(ACC1:mul#99.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(4)} -pin  "reg(ACC1:mul#99.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(5)} -pin  "reg(ACC1:mul#99.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(6)} -pin  "reg(ACC1:mul#99.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {ACC1:mul#99.itm(7)} -pin  "reg(ACC1:mul#99.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm}
+load net {GND} -pin  "reg(ACC1:mul#99.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#99.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#99.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#99.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#99.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#99.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#99.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#99.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_8}
+load net {clk} -pin  "reg(ACC1:mul#99.itm#1)" {clk} -attr xrf 18459 -attr oid 605 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:mul#99.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:mul#99.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:mul#99.itm#1(0)} -pin  "reg(ACC1:mul#99.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm#1}
+load net {ACC1:mul#99.itm#1(1)} -pin  "reg(ACC1:mul#99.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm#1}
+load net {ACC1:mul#99.itm#1(2)} -pin  "reg(ACC1:mul#99.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm#1}
+load net {ACC1:mul#99.itm#1(3)} -pin  "reg(ACC1:mul#99.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm#1}
+load net {ACC1:mul#99.itm#1(4)} -pin  "reg(ACC1:mul#99.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm#1}
+load net {ACC1:mul#99.itm#1(5)} -pin  "reg(ACC1:mul#99.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm#1}
+load net {ACC1:mul#99.itm#1(6)} -pin  "reg(ACC1:mul#99.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm#1}
+load net {ACC1:mul#99.itm#1(7)} -pin  "reg(ACC1:mul#99.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#99.itm#1}
+load inst "reg(ACC1:slc(acc.imod#17)#8.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 18460 -attr oid 606 -attr @path {/sobel/sobel:core/reg(ACC1:slc(acc.imod#17)#8.itm#1)}
+load net {ACC1:acc#162.itm(4)} -pin  "reg(ACC1:slc(acc.imod#17)#8.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#17.sva)#2.itm}
+load net {GND} -pin  "reg(ACC1:slc(acc.imod#17)#8.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(ACC1:slc(acc.imod#17)#8.itm#1)" {clk} -attr xrf 18461 -attr oid 607 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(acc.imod#17)#8.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(acc.imod#17)#8.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(acc.imod#17)#8.itm#1} -pin  "reg(ACC1:slc(acc.imod#17)#8.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:slc(acc.imod#17)#8.itm#1}
+load inst "reg(ACC1-2:slc(acc.idiv)#106.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 18462 -attr oid 608 -attr @path {/sobel/sobel:core/reg(ACC1-2:slc(acc.idiv)#106.itm#1)}
+load net {acc.idiv#3.sva(17)} -pin  "reg(ACC1-2:slc(acc.idiv)#106.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#19.itm}
+load net {GND} -pin  "reg(ACC1-2:slc(acc.idiv)#106.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(ACC1-2:slc(acc.idiv)#106.itm#1)" {clk} -attr xrf 18463 -attr oid 609 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1-2:slc(acc.idiv)#106.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1-2:slc(acc.idiv)#106.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1-2:slc(acc.idiv)#106.itm#1} -pin  "reg(ACC1-2:slc(acc.idiv)#106.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:slc(acc.idiv)#106.itm#1}
+load inst "ACC1:acc#135" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18464 -attr oid 610 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv#3.sva(6)} -pin  "ACC1:acc#135" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#37.itm}
+load net {acc.idiv#7.sva(6)} -pin  "ACC1:acc#135" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#29.itm}
+load net {ACC1:acc#135.itm(0)} -pin  "ACC1:acc#135" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135.itm}
+load net {ACC1:acc#135.itm(1)} -pin  "ACC1:acc#135" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135.itm}
+load inst "ACC1:mul#92" "mul(2,0,5,0,6)" "INTERFACE" -attr xrf 18465 -attr oid 611 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#92} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc#135.itm(0)} -pin  "ACC1:mul#92" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135.itm}
+load net {ACC1:acc#135.itm(1)} -pin  "ACC1:mul#92" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135.itm}
+load net {PWR} -pin  "ACC1:mul#92" {B(0)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#92" {B(1)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#92" {B(2)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#92" {B(3)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#92" {B(4)} -attr @path {/sobel/sobel:core/C21_5}
+load net {ACC1:mul#92.itm(0)} -pin  "ACC1:mul#92" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#92.itm}
+load net {ACC1:mul#92.itm(1)} -pin  "ACC1:mul#92" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#92.itm}
+load net {ACC1:mul#92.itm(2)} -pin  "ACC1:mul#92" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#92.itm}
+load net {ACC1:mul#92.itm(3)} -pin  "ACC1:mul#92" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#92.itm}
+load net {ACC1:mul#92.itm(4)} -pin  "ACC1:mul#92" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#92.itm}
+load net {ACC1:mul#92.itm(5)} -pin  "ACC1:mul#92" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#92.itm}
+load inst "ACC1:acc#259" "add(7,-1,7,-1,7)" "INTERFACE" -attr xrf 18466 -attr oid 612 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {acc.idiv.sva(9)} -pin  "ACC1:acc#259" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#313.itm}
+load net {acc.idiv.sva(9)} -pin  "ACC1:acc#259" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#313.itm}
+load net {PWR} -pin  "ACC1:acc#259" {A(2)} -attr @path {/sobel/sobel:core/conc#313.itm}
+load net {GND} -pin  "ACC1:acc#259" {A(3)} -attr @path {/sobel/sobel:core/conc#313.itm}
+load net {PWR} -pin  "ACC1:acc#259" {A(4)} -attr @path {/sobel/sobel:core/conc#313.itm}
+load net {GND} -pin  "ACC1:acc#259" {A(5)} -attr @path {/sobel/sobel:core/conc#313.itm}
+load net {PWR} -pin  "ACC1:acc#259" {A(6)} -attr @path {/sobel/sobel:core/conc#313.itm}
+load net {acc.idiv#2.sva(3)} -pin  "ACC1:acc#259" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#250.itm}
+load net {ACC1:mul#92.itm(0)} -pin  "ACC1:acc#259" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#250.itm}
+load net {ACC1:mul#92.itm(1)} -pin  "ACC1:acc#259" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#250.itm}
+load net {ACC1:mul#92.itm(2)} -pin  "ACC1:acc#259" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#250.itm}
+load net {ACC1:mul#92.itm(3)} -pin  "ACC1:acc#259" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#250.itm}
+load net {ACC1:mul#92.itm(4)} -pin  "ACC1:acc#259" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#250.itm}
+load net {ACC1:mul#92.itm(5)} -pin  "ACC1:acc#259" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#250.itm}
+load net {ACC1:acc#259.itm(0)} -pin  "ACC1:acc#259" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(1)} -pin  "ACC1:acc#259" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(2)} -pin  "ACC1:acc#259" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(3)} -pin  "ACC1:acc#259" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(4)} -pin  "ACC1:acc#259" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(5)} -pin  "ACC1:acc#259" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(6)} -pin  "ACC1:acc#259" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load inst "ACC1:acc#227" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18467 -attr oid 613 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#3.sva(11)} -pin  "ACC1:acc#227" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#3.itm}
+load net {acc.idiv#3.sva(11)} -pin  "ACC1:acc#227" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#3.itm}
+load net {acc.idiv#3.sva(13)} -pin  "ACC1:acc#227" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#4.itm}
+load net {acc.idiv#3.sva(13)} -pin  "ACC1:acc#227" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#4.itm}
+load net {ACC1:acc#227.itm(0)} -pin  "ACC1:acc#227" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(1)} -pin  "ACC1:acc#227" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(2)} -pin  "ACC1:acc#227" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load inst "ACC1:acc#226" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18468 -attr oid 614 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#3.sva(15)} -pin  "ACC1:acc#226" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#5.itm}
+load net {acc.idiv#3.sva(15)} -pin  "ACC1:acc#226" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#5.itm}
+load net {acc.idiv#7.sva(17)} -pin  "ACC1:acc#226" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#40.itm}
+load net {acc.idiv#7.sva(17)} -pin  "ACC1:acc#226" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#40.itm}
+load net {ACC1:acc#226.itm(0)} -pin  "ACC1:acc#226" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(1)} -pin  "ACC1:acc#226" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(2)} -pin  "ACC1:acc#226" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load inst "ACC1:acc#241" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18469 -attr oid 615 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#227.itm(0)} -pin  "ACC1:acc#241" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(1)} -pin  "ACC1:acc#241" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(2)} -pin  "ACC1:acc#241" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#226.itm(0)} -pin  "ACC1:acc#241" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(1)} -pin  "ACC1:acc#241" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(2)} -pin  "ACC1:acc#241" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#241.itm(0)} -pin  "ACC1:acc#241" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(1)} -pin  "ACC1:acc#241" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(2)} -pin  "ACC1:acc#241" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(3)} -pin  "ACC1:acc#241" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load inst "ACC1:acc#225" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18470 -attr oid 616 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#7.sva(5)} -pin  "ACC1:acc#225" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#35.itm}
+load net {acc.idiv#7.sva(5)} -pin  "ACC1:acc#225" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#35.itm}
+load net {acc.idiv#7.sva(7)} -pin  "ACC1:acc#225" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#39.itm}
+load net {acc.idiv#7.sva(7)} -pin  "ACC1:acc#225" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#39.itm}
+load net {ACC1:acc#225.itm(0)} -pin  "ACC1:acc#225" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#225.itm(1)} -pin  "ACC1:acc#225" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#225.itm(2)} -pin  "ACC1:acc#225" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load inst "ACC1:acc#224" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18471 -attr oid 617 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#7.sva(9)} -pin  "ACC1:acc#224" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#37.itm}
+load net {acc.idiv#7.sva(9)} -pin  "ACC1:acc#224" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#37.itm}
+load net {acc.idiv#7.sva(11)} -pin  "ACC1:acc#224" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#41.itm}
+load net {acc.idiv#7.sva(11)} -pin  "ACC1:acc#224" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#41.itm}
+load net {ACC1:acc#224.itm(0)} -pin  "ACC1:acc#224" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.itm}
+load net {ACC1:acc#224.itm(1)} -pin  "ACC1:acc#224" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.itm}
+load net {ACC1:acc#224.itm(2)} -pin  "ACC1:acc#224" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.itm}
+load inst "ACC1:acc#240" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18472 -attr oid 618 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#240} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#225.itm(0)} -pin  "ACC1:acc#240" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#225.itm(1)} -pin  "ACC1:acc#240" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#225.itm(2)} -pin  "ACC1:acc#240" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#224.itm(0)} -pin  "ACC1:acc#240" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.itm}
+load net {ACC1:acc#224.itm(1)} -pin  "ACC1:acc#240" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.itm}
+load net {ACC1:acc#224.itm(2)} -pin  "ACC1:acc#240" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.itm}
+load net {ACC1:acc#240.itm(0)} -pin  "ACC1:acc#240" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#240.itm}
+load net {ACC1:acc#240.itm(1)} -pin  "ACC1:acc#240" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#240.itm}
+load net {ACC1:acc#240.itm(2)} -pin  "ACC1:acc#240" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#240.itm}
+load net {ACC1:acc#240.itm(3)} -pin  "ACC1:acc#240" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#240.itm}
+load inst "ACC1:acc#249" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 18473 -attr oid 619 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#249} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#241.itm(0)} -pin  "ACC1:acc#249" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(1)} -pin  "ACC1:acc#249" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(2)} -pin  "ACC1:acc#249" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(3)} -pin  "ACC1:acc#249" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#240.itm(0)} -pin  "ACC1:acc#249" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#240.itm}
+load net {ACC1:acc#240.itm(1)} -pin  "ACC1:acc#249" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#240.itm}
+load net {ACC1:acc#240.itm(2)} -pin  "ACC1:acc#249" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#240.itm}
+load net {ACC1:acc#240.itm(3)} -pin  "ACC1:acc#249" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#240.itm}
+load net {ACC1:acc#249.itm(0)} -pin  "ACC1:acc#249" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#249.itm}
+load net {ACC1:acc#249.itm(1)} -pin  "ACC1:acc#249" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#249.itm}
+load net {ACC1:acc#249.itm(2)} -pin  "ACC1:acc#249" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#249.itm}
+load net {ACC1:acc#249.itm(3)} -pin  "ACC1:acc#249" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#249.itm}
+load net {ACC1:acc#249.itm(4)} -pin  "ACC1:acc#249" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#249.itm}
+load inst "ACC1:acc#223" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18474 -attr oid 620 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#7.sva(13)} -pin  "ACC1:acc#223" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#38.itm}
+load net {acc.idiv#7.sva(13)} -pin  "ACC1:acc#223" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#38.itm}
+load net {acc.idiv#7.sva(15)} -pin  "ACC1:acc#223" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#36.itm}
+load net {acc.idiv#7.sva(15)} -pin  "ACC1:acc#223" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#36.itm}
+load net {ACC1:acc#223.itm(0)} -pin  "ACC1:acc#223" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.itm}
+load net {ACC1:acc#223.itm(1)} -pin  "ACC1:acc#223" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.itm}
+load net {ACC1:acc#223.itm(2)} -pin  "ACC1:acc#223" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.itm}
+load inst "ACC1:acc#222" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18475 -attr oid 621 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#2.sva(5)} -pin  "ACC1:acc#222" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#14.itm}
+load net {acc.idiv#2.sva(5)} -pin  "ACC1:acc#222" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#14.itm}
+load net {acc.idiv#2.sva(7)} -pin  "ACC1:acc#222" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#15.itm}
+load net {acc.idiv#2.sva(7)} -pin  "ACC1:acc#222" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#15.itm}
+load net {ACC1:acc#222.itm(0)} -pin  "ACC1:acc#222" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {ACC1:acc#222.itm(1)} -pin  "ACC1:acc#222" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {ACC1:acc#222.itm(2)} -pin  "ACC1:acc#222" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load inst "ACC1:acc#239" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18476 -attr oid 622 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#223.itm(0)} -pin  "ACC1:acc#239" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.itm}
+load net {ACC1:acc#223.itm(1)} -pin  "ACC1:acc#239" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.itm}
+load net {ACC1:acc#223.itm(2)} -pin  "ACC1:acc#239" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#223.itm}
+load net {ACC1:acc#222.itm(0)} -pin  "ACC1:acc#239" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {ACC1:acc#222.itm(1)} -pin  "ACC1:acc#239" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {ACC1:acc#222.itm(2)} -pin  "ACC1:acc#239" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {ACC1:acc#239.itm(0)} -pin  "ACC1:acc#239" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(1)} -pin  "ACC1:acc#239" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(2)} -pin  "ACC1:acc#239" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(3)} -pin  "ACC1:acc#239" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load inst "ACC1:acc#221" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18477 -attr oid 623 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#2.sva(9)} -pin  "ACC1:acc#221" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#16.itm}
+load net {acc.idiv#2.sva(9)} -pin  "ACC1:acc#221" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#16.itm}
+load net {acc.idiv#2.sva(11)} -pin  "ACC1:acc#221" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#17.itm}
+load net {acc.idiv#2.sva(11)} -pin  "ACC1:acc#221" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#17.itm}
+load net {ACC1:acc#221.itm(0)} -pin  "ACC1:acc#221" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {ACC1:acc#221.itm(1)} -pin  "ACC1:acc#221" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {ACC1:acc#221.itm(2)} -pin  "ACC1:acc#221" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load inst "ACC1:acc#220" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18478 -attr oid 624 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#2.sva(13)} -pin  "ACC1:acc#220" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#18.itm}
+load net {acc.idiv#2.sva(13)} -pin  "ACC1:acc#220" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#18.itm}
+load net {acc.idiv#2.sva(15)} -pin  "ACC1:acc#220" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#19.itm}
+load net {acc.idiv#2.sva(15)} -pin  "ACC1:acc#220" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#19.itm}
+load net {ACC1:acc#220.itm(0)} -pin  "ACC1:acc#220" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {ACC1:acc#220.itm(1)} -pin  "ACC1:acc#220" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {ACC1:acc#220.itm(2)} -pin  "ACC1:acc#220" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load inst "ACC1:acc#238" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18479 -attr oid 625 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#221.itm(0)} -pin  "ACC1:acc#238" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {ACC1:acc#221.itm(1)} -pin  "ACC1:acc#238" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {ACC1:acc#221.itm(2)} -pin  "ACC1:acc#238" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {ACC1:acc#220.itm(0)} -pin  "ACC1:acc#238" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {ACC1:acc#220.itm(1)} -pin  "ACC1:acc#238" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {ACC1:acc#220.itm(2)} -pin  "ACC1:acc#238" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {ACC1:acc#238.itm(0)} -pin  "ACC1:acc#238" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(1)} -pin  "ACC1:acc#238" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(2)} -pin  "ACC1:acc#238" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(3)} -pin  "ACC1:acc#238" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load inst "ACC1:acc#248" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 18480 -attr oid 626 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#239.itm(0)} -pin  "ACC1:acc#248" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(1)} -pin  "ACC1:acc#248" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(2)} -pin  "ACC1:acc#248" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(3)} -pin  "ACC1:acc#248" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#238.itm(0)} -pin  "ACC1:acc#248" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(1)} -pin  "ACC1:acc#248" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(2)} -pin  "ACC1:acc#248" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(3)} -pin  "ACC1:acc#248" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#248.itm(0)} -pin  "ACC1:acc#248" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(1)} -pin  "ACC1:acc#248" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(2)} -pin  "ACC1:acc#248" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(3)} -pin  "ACC1:acc#248" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(4)} -pin  "ACC1:acc#248" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load inst "ACC1:acc#254" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 18481 -attr oid 627 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#249.itm(0)} -pin  "ACC1:acc#254" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#249.itm}
+load net {ACC1:acc#249.itm(1)} -pin  "ACC1:acc#254" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#249.itm}
+load net {ACC1:acc#249.itm(2)} -pin  "ACC1:acc#254" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#249.itm}
+load net {ACC1:acc#249.itm(3)} -pin  "ACC1:acc#254" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#249.itm}
+load net {ACC1:acc#249.itm(4)} -pin  "ACC1:acc#254" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#249.itm}
+load net {ACC1:acc#248.itm(0)} -pin  "ACC1:acc#254" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(1)} -pin  "ACC1:acc#254" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(2)} -pin  "ACC1:acc#254" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(3)} -pin  "ACC1:acc#254" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(4)} -pin  "ACC1:acc#254" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#254.itm(0)} -pin  "ACC1:acc#254" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(1)} -pin  "ACC1:acc#254" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(2)} -pin  "ACC1:acc#254" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(3)} -pin  "ACC1:acc#254" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(4)} -pin  "ACC1:acc#254" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(5)} -pin  "ACC1:acc#254" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load inst "ACC1:acc#219" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18482 -attr oid 628 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#7.sva(7)} -pin  "ACC1:acc#219" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#29.itm}
+load net {acc.idiv#7.sva(7)} -pin  "ACC1:acc#219" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#29.itm}
+load net {acc.idiv#7.sva(9)} -pin  "ACC1:acc#219" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#25.itm}
+load net {acc.idiv#7.sva(9)} -pin  "ACC1:acc#219" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#25.itm}
+load net {ACC1:acc#219.itm(0)} -pin  "ACC1:acc#219" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {ACC1:acc#219.itm(1)} -pin  "ACC1:acc#219" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {ACC1:acc#219.itm(2)} -pin  "ACC1:acc#219" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load inst "ACC1:acc#218" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18483 -attr oid 629 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#7.sva(11)} -pin  "ACC1:acc#218" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#33.itm}
+load net {acc.idiv#7.sva(11)} -pin  "ACC1:acc#218" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#33.itm}
+load net {acc.idiv#7.sva(13)} -pin  "ACC1:acc#218" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#27.itm}
+load net {acc.idiv#7.sva(13)} -pin  "ACC1:acc#218" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#27.itm}
+load net {ACC1:acc#218.itm(0)} -pin  "ACC1:acc#218" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {ACC1:acc#218.itm(1)} -pin  "ACC1:acc#218" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {ACC1:acc#218.itm(2)} -pin  "ACC1:acc#218" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load inst "ACC1:acc#237" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18484 -attr oid 630 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#219.itm(0)} -pin  "ACC1:acc#237" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {ACC1:acc#219.itm(1)} -pin  "ACC1:acc#237" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {ACC1:acc#219.itm(2)} -pin  "ACC1:acc#237" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {ACC1:acc#218.itm(0)} -pin  "ACC1:acc#237" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {ACC1:acc#218.itm(1)} -pin  "ACC1:acc#237" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {ACC1:acc#218.itm(2)} -pin  "ACC1:acc#237" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {ACC1:acc#237.itm(0)} -pin  "ACC1:acc#237" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(1)} -pin  "ACC1:acc#237" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(2)} -pin  "ACC1:acc#237" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(3)} -pin  "ACC1:acc#237" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load inst "ACC1:acc#217" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18485 -attr oid 631 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#7.sva(15)} -pin  "ACC1:acc#217" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#23.itm}
+load net {acc.idiv#7.sva(15)} -pin  "ACC1:acc#217" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#23.itm}
+load net {acc.idiv#7.sva(17)} -pin  "ACC1:acc#217" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#31.itm}
+load net {acc.idiv#7.sva(17)} -pin  "ACC1:acc#217" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#31.itm}
+load net {ACC1:acc#217.itm(0)} -pin  "ACC1:acc#217" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1:acc#217.itm(1)} -pin  "ACC1:acc#217" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1:acc#217.itm(2)} -pin  "ACC1:acc#217" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load inst "ACC1:acc#216" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18486 -attr oid 632 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#7.sva(5)} -pin  "ACC1:acc#216" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#21.itm}
+load net {acc.idiv#7.sva(5)} -pin  "ACC1:acc#216" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#21.itm}
+load net {acc.idiv#2.sva(17)} -pin  "ACC1:acc#216" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#20.itm}
+load net {acc.idiv#2.sva(17)} -pin  "ACC1:acc#216" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#20.itm}
+load net {ACC1:acc#216.itm(0)} -pin  "ACC1:acc#216" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {ACC1:acc#216.itm(1)} -pin  "ACC1:acc#216" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {ACC1:acc#216.itm(2)} -pin  "ACC1:acc#216" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load inst "ACC1:acc#236" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18487 -attr oid 633 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#217.itm(0)} -pin  "ACC1:acc#236" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1:acc#217.itm(1)} -pin  "ACC1:acc#236" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1:acc#217.itm(2)} -pin  "ACC1:acc#236" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1:acc#216.itm(0)} -pin  "ACC1:acc#236" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {ACC1:acc#216.itm(1)} -pin  "ACC1:acc#236" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {ACC1:acc#216.itm(2)} -pin  "ACC1:acc#236" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {ACC1:acc#236.itm(0)} -pin  "ACC1:acc#236" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(1)} -pin  "ACC1:acc#236" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(2)} -pin  "ACC1:acc#236" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(3)} -pin  "ACC1:acc#236" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load inst "ACC1:acc#247" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 18488 -attr oid 634 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#237.itm(0)} -pin  "ACC1:acc#247" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(1)} -pin  "ACC1:acc#247" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(2)} -pin  "ACC1:acc#247" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(3)} -pin  "ACC1:acc#247" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#236.itm(0)} -pin  "ACC1:acc#247" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(1)} -pin  "ACC1:acc#247" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(2)} -pin  "ACC1:acc#247" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(3)} -pin  "ACC1:acc#247" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#247.itm(0)} -pin  "ACC1:acc#247" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(1)} -pin  "ACC1:acc#247" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(2)} -pin  "ACC1:acc#247" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(3)} -pin  "ACC1:acc#247" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(4)} -pin  "ACC1:acc#247" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load inst "ACC1:acc#215" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18489 -attr oid 635 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv.sva(1)} -pin  "ACC1:acc#215" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {acc.idiv.sva(3)} -pin  "ACC1:acc#215" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {acc.idiv.sva(2)} -pin  "ACC1:acc#215" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#245.itm}
+load net {acc.idiv#2.sva(3)} -pin  "ACC1:acc#215" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#245.itm}
+load net {ACC1:acc#215.itm(0)} -pin  "ACC1:acc#215" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(1)} -pin  "ACC1:acc#215" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(2)} -pin  "ACC1:acc#215" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load inst "ACC1:acc#214" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18490 -attr oid 636 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv.sva(3)} -pin  "ACC1:acc#214" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#246.itm}
+load net {acc.idiv#3.sva(1)} -pin  "ACC1:acc#214" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#246.itm}
+load net {acc.idiv.sva(4)} -pin  "ACC1:acc#214" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#247.itm}
+load net {acc.idiv#3.sva(2)} -pin  "ACC1:acc#214" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#247.itm}
+load net {ACC1:acc#214.itm(0)} -pin  "ACC1:acc#214" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(1)} -pin  "ACC1:acc#214" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(2)} -pin  "ACC1:acc#214" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load inst "ACC1:acc#235" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18491 -attr oid 637 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#215.itm(0)} -pin  "ACC1:acc#235" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(1)} -pin  "ACC1:acc#235" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(2)} -pin  "ACC1:acc#235" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#214.itm(0)} -pin  "ACC1:acc#235" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(1)} -pin  "ACC1:acc#235" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(2)} -pin  "ACC1:acc#235" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#235.itm(0)} -pin  "ACC1:acc#235" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(1)} -pin  "ACC1:acc#235" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(2)} -pin  "ACC1:acc#235" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(3)} -pin  "ACC1:acc#235" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load inst "ACC1:acc#213" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18492 -attr oid 638 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#2.sva(1)} -pin  "ACC1:acc#213" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#248.itm}
+load net {acc.idiv#3.sva(3)} -pin  "ACC1:acc#213" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#248.itm}
+load net {acc.idiv#2.sva(2)} -pin  "ACC1:acc#213" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#249.itm}
+load net {acc.idiv#3.sva(4)} -pin  "ACC1:acc#213" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#249.itm}
+load net {ACC1:acc#213.itm(0)} -pin  "ACC1:acc#213" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(1)} -pin  "ACC1:acc#213" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(2)} -pin  "ACC1:acc#213" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load inst "ACC1:acc#212" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18493 -attr oid 639 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#201.itm(2)} -pin  "ACC1:acc#212" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#256.itm}
+load net {ACC1:acc#189.itm(4)} -pin  "ACC1:acc#212" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#256.itm}
+load net {ACC1:acc#201.itm(3)} -pin  "ACC1:acc#212" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#257.itm}
+load net {ACC1:acc#162.itm(2)} -pin  "ACC1:acc#212" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#257.itm}
+load net {ACC1:acc#212.itm(0)} -pin  "ACC1:acc#212" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(1)} -pin  "ACC1:acc#212" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(2)} -pin  "ACC1:acc#212" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load inst "ACC1:acc#234" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18494 -attr oid 640 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#213.itm(0)} -pin  "ACC1:acc#234" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(1)} -pin  "ACC1:acc#234" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(2)} -pin  "ACC1:acc#234" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#212.itm(0)} -pin  "ACC1:acc#234" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(1)} -pin  "ACC1:acc#234" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(2)} -pin  "ACC1:acc#234" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#234.itm(0)} -pin  "ACC1:acc#234" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(1)} -pin  "ACC1:acc#234" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(2)} -pin  "ACC1:acc#234" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(3)} -pin  "ACC1:acc#234" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load inst "ACC1:acc#246" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 18495 -attr oid 641 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#235.itm(0)} -pin  "ACC1:acc#246" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(1)} -pin  "ACC1:acc#246" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(2)} -pin  "ACC1:acc#246" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(3)} -pin  "ACC1:acc#246" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#234.itm(0)} -pin  "ACC1:acc#246" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(1)} -pin  "ACC1:acc#246" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(2)} -pin  "ACC1:acc#246" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(3)} -pin  "ACC1:acc#246" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#246.itm(0)} -pin  "ACC1:acc#246" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(1)} -pin  "ACC1:acc#246" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(2)} -pin  "ACC1:acc#246" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(3)} -pin  "ACC1:acc#246" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(4)} -pin  "ACC1:acc#246" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load inst "ACC1:acc#253" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 18496 -attr oid 642 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#247.itm(0)} -pin  "ACC1:acc#253" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(1)} -pin  "ACC1:acc#253" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(2)} -pin  "ACC1:acc#253" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(3)} -pin  "ACC1:acc#253" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(4)} -pin  "ACC1:acc#253" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#246.itm(0)} -pin  "ACC1:acc#253" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(1)} -pin  "ACC1:acc#253" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(2)} -pin  "ACC1:acc#253" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(3)} -pin  "ACC1:acc#253" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(4)} -pin  "ACC1:acc#253" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#253.itm(0)} -pin  "ACC1:acc#253" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(1)} -pin  "ACC1:acc#253" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(2)} -pin  "ACC1:acc#253" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(3)} -pin  "ACC1:acc#253" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(4)} -pin  "ACC1:acc#253" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(5)} -pin  "ACC1:acc#253" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load inst "ACC1:acc#257" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 18497 -attr oid 643 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#254.itm(0)} -pin  "ACC1:acc#257" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(1)} -pin  "ACC1:acc#257" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(2)} -pin  "ACC1:acc#257" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(3)} -pin  "ACC1:acc#257" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(4)} -pin  "ACC1:acc#257" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(5)} -pin  "ACC1:acc#257" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#253.itm(0)} -pin  "ACC1:acc#257" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(1)} -pin  "ACC1:acc#257" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(2)} -pin  "ACC1:acc#257" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(3)} -pin  "ACC1:acc#257" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(4)} -pin  "ACC1:acc#257" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(5)} -pin  "ACC1:acc#257" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#257.itm(0)} -pin  "ACC1:acc#257" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(1)} -pin  "ACC1:acc#257" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(2)} -pin  "ACC1:acc#257" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(3)} -pin  "ACC1:acc#257" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(4)} -pin  "ACC1:acc#257" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(5)} -pin  "ACC1:acc#257" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(6)} -pin  "ACC1:acc#257" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load inst "ACC1:acc#261" "add(7,1,7,0,9)" "INTERFACE" -attr xrf 18498 -attr oid 644 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#259.itm(0)} -pin  "ACC1:acc#261" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(1)} -pin  "ACC1:acc#261" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(2)} -pin  "ACC1:acc#261" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(3)} -pin  "ACC1:acc#261" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(4)} -pin  "ACC1:acc#261" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(5)} -pin  "ACC1:acc#261" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(6)} -pin  "ACC1:acc#261" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#257.itm(0)} -pin  "ACC1:acc#261" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(1)} -pin  "ACC1:acc#261" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(2)} -pin  "ACC1:acc#261" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(3)} -pin  "ACC1:acc#261" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(4)} -pin  "ACC1:acc#261" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(5)} -pin  "ACC1:acc#261" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(6)} -pin  "ACC1:acc#261" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#261.itm(0)} -pin  "ACC1:acc#261" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(1)} -pin  "ACC1:acc#261" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(2)} -pin  "ACC1:acc#261" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(3)} -pin  "ACC1:acc#261" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(4)} -pin  "ACC1:acc#261" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(5)} -pin  "ACC1:acc#261" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(6)} -pin  "ACC1:acc#261" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(7)} -pin  "ACC1:acc#261" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(8)} -pin  "ACC1:acc#261" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load inst "ACC1:acc#136" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18499 -attr oid 645 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv#3.sva(8)} -pin  "ACC1:acc#136" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#51.itm}
+load net {acc.idiv#7.sva(8)} -pin  "ACC1:acc#136" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#51.itm}
+load net {ACC1:acc#136.itm(0)} -pin  "ACC1:acc#136" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load net {ACC1:acc#136.itm(1)} -pin  "ACC1:acc#136" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load inst "ACC1:mul#93" "mul(2,0,7,0,8)" "INTERFACE" -attr xrf 18500 -attr oid 646 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#93} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,7,0,8)"
+load net {ACC1:acc#136.itm(0)} -pin  "ACC1:mul#93" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load net {ACC1:acc#136.itm(1)} -pin  "ACC1:mul#93" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load net {PWR} -pin  "ACC1:mul#93" {B(0)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#93" {B(1)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#93" {B(2)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#93" {B(3)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#93" {B(4)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#93" {B(5)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#93" {B(6)} -attr @path {/sobel/sobel:core/C85_7}
+load net {ACC1:mul#93.itm(0)} -pin  "ACC1:mul#93" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#93.itm}
+load net {ACC1:mul#93.itm(1)} -pin  "ACC1:mul#93" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#93.itm}
+load net {ACC1:mul#93.itm(2)} -pin  "ACC1:mul#93" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#93.itm}
+load net {ACC1:mul#93.itm(3)} -pin  "ACC1:mul#93" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#93.itm}
+load net {ACC1:mul#93.itm(4)} -pin  "ACC1:mul#93" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#93.itm}
+load net {ACC1:mul#93.itm(5)} -pin  "ACC1:mul#93" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#93.itm}
+load net {ACC1:mul#93.itm(6)} -pin  "ACC1:mul#93" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#93.itm}
+load net {ACC1:mul#93.itm(7)} -pin  "ACC1:mul#93" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#93.itm}
+load inst "ACC1:acc#264" "add(9,1,9,0,10)" "INTERFACE" -attr xrf 18501 -attr oid 647 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,10)"
+load net {ACC1:acc#261.itm(0)} -pin  "ACC1:acc#264" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(1)} -pin  "ACC1:acc#264" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(2)} -pin  "ACC1:acc#264" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(3)} -pin  "ACC1:acc#264" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(4)} -pin  "ACC1:acc#264" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(5)} -pin  "ACC1:acc#264" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(6)} -pin  "ACC1:acc#264" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(7)} -pin  "ACC1:acc#264" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(8)} -pin  "ACC1:acc#264" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {acc.idiv#2.sva(4)} -pin  "ACC1:acc#264" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#251.itm}
+load net {ACC1:mul#93.itm(0)} -pin  "ACC1:acc#264" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#251.itm}
+load net {ACC1:mul#93.itm(1)} -pin  "ACC1:acc#264" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#251.itm}
+load net {ACC1:mul#93.itm(2)} -pin  "ACC1:acc#264" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#251.itm}
+load net {ACC1:mul#93.itm(3)} -pin  "ACC1:acc#264" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#251.itm}
+load net {ACC1:mul#93.itm(4)} -pin  "ACC1:acc#264" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#251.itm}
+load net {ACC1:mul#93.itm(5)} -pin  "ACC1:acc#264" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#251.itm}
+load net {ACC1:mul#93.itm(6)} -pin  "ACC1:acc#264" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#251.itm}
+load net {ACC1:mul#93.itm(7)} -pin  "ACC1:acc#264" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#251.itm}
+load net {ACC1:acc#264.itm(0)} -pin  "ACC1:acc#264" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(1)} -pin  "ACC1:acc#264" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(2)} -pin  "ACC1:acc#264" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(3)} -pin  "ACC1:acc#264" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(4)} -pin  "ACC1:acc#264" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(5)} -pin  "ACC1:acc#264" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(6)} -pin  "ACC1:acc#264" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(7)} -pin  "ACC1:acc#264" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(8)} -pin  "ACC1:acc#264" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(9)} -pin  "ACC1:acc#264" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load inst "reg(ACC1:acc#264.itm#1)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 18502 -attr oid 648 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#264.itm#1)}
+load net {ACC1:acc#264.itm(0)} -pin  "reg(ACC1:acc#264.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(1)} -pin  "reg(ACC1:acc#264.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(2)} -pin  "reg(ACC1:acc#264.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(3)} -pin  "reg(ACC1:acc#264.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(4)} -pin  "reg(ACC1:acc#264.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(5)} -pin  "reg(ACC1:acc#264.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(6)} -pin  "reg(ACC1:acc#264.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(7)} -pin  "reg(ACC1:acc#264.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(8)} -pin  "reg(ACC1:acc#264.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(9)} -pin  "reg(ACC1:acc#264.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {GND} -pin  "reg(ACC1:acc#264.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:acc#264.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:acc#264.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:acc#264.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:acc#264.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:acc#264.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:acc#264.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:acc#264.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:acc#264.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:acc#264.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10}
+load net {clk} -pin  "reg(ACC1:acc#264.itm#1)" {clk} -attr xrf 18503 -attr oid 649 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#264.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#264.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#264.itm#1(0)} -pin  "reg(ACC1:acc#264.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(1)} -pin  "reg(ACC1:acc#264.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(2)} -pin  "reg(ACC1:acc#264.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(3)} -pin  "reg(ACC1:acc#264.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(4)} -pin  "reg(ACC1:acc#264.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(5)} -pin  "reg(ACC1:acc#264.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(6)} -pin  "reg(ACC1:acc#264.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(7)} -pin  "reg(ACC1:acc#264.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(8)} -pin  "reg(ACC1:acc#264.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(9)} -pin  "reg(ACC1:acc#264.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load inst "ACC1:acc#133" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18504 -attr oid 650 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv.sva(12)} -pin  "ACC1:acc#133" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#40.itm}
+load net {acc.idiv#2.sva(12)} -pin  "ACC1:acc#133" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#35.itm}
+load net {ACC1:acc#133.itm(0)} -pin  "ACC1:acc#133" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(1)} -pin  "ACC1:acc#133" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load inst "ACC1:mul#90" "mul(2,0,11,0,12)" "INTERFACE" -attr xrf 18505 -attr oid 651 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,11,0,12)"
+load net {ACC1:acc#133.itm(0)} -pin  "ACC1:mul#90" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(1)} -pin  "ACC1:mul#90" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {PWR} -pin  "ACC1:mul#90" {B(0)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#90" {B(1)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#90" {B(2)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#90" {B(3)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#90" {B(4)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#90" {B(5)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#90" {B(6)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#90" {B(7)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#90" {B(8)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {GND} -pin  "ACC1:mul#90" {B(9)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {PWR} -pin  "ACC1:mul#90" {B(10)} -attr @path {/sobel/sobel:core/C1365_11}
+load net {ACC1:mul#90.itm(0)} -pin  "ACC1:mul#90" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(1)} -pin  "ACC1:mul#90" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(2)} -pin  "ACC1:mul#90" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(3)} -pin  "ACC1:mul#90" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(4)} -pin  "ACC1:mul#90" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(5)} -pin  "ACC1:mul#90" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(6)} -pin  "ACC1:mul#90" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(7)} -pin  "ACC1:mul#90" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(8)} -pin  "ACC1:mul#90" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(9)} -pin  "ACC1:mul#90" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(10)} -pin  "ACC1:mul#90" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(11)} -pin  "ACC1:mul#90" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load inst "reg(ACC1:mul#90.itm#1)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 18506 -attr oid 652 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:mul#90.itm#1)}
+load net {ACC1:mul#90.itm(0)} -pin  "reg(ACC1:mul#90.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(1)} -pin  "reg(ACC1:mul#90.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(2)} -pin  "reg(ACC1:mul#90.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(3)} -pin  "reg(ACC1:mul#90.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(4)} -pin  "reg(ACC1:mul#90.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(5)} -pin  "reg(ACC1:mul#90.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(6)} -pin  "reg(ACC1:mul#90.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(7)} -pin  "reg(ACC1:mul#90.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(8)} -pin  "reg(ACC1:mul#90.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(9)} -pin  "reg(ACC1:mul#90.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(10)} -pin  "reg(ACC1:mul#90.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {ACC1:mul#90.itm(11)} -pin  "reg(ACC1:mul#90.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm}
+load net {GND} -pin  "reg(ACC1:mul#90.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:mul#90.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:mul#90.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:mul#90.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:mul#90.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:mul#90.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:mul#90.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:mul#90.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:mul#90.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:mul#90.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:mul#90.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:mul#90.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(ACC1:mul#90.itm#1)" {clk} -attr xrf 18507 -attr oid 653 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:mul#90.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:mul#90.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:mul#90.itm#1(0)} -pin  "reg(ACC1:mul#90.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(1)} -pin  "reg(ACC1:mul#90.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(2)} -pin  "reg(ACC1:mul#90.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(3)} -pin  "reg(ACC1:mul#90.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(4)} -pin  "reg(ACC1:mul#90.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(5)} -pin  "reg(ACC1:mul#90.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(6)} -pin  "reg(ACC1:mul#90.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(7)} -pin  "reg(ACC1:mul#90.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(8)} -pin  "reg(ACC1:mul#90.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(9)} -pin  "reg(ACC1:mul#90.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(10)} -pin  "reg(ACC1:mul#90.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(11)} -pin  "reg(ACC1:mul#90.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load inst "ACC1:acc#134" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18508 -attr oid 654 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv.sva(14)} -pin  "ACC1:acc#134" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#32.itm}
+load net {acc.idiv#2.sva(14)} -pin  "ACC1:acc#134" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#27.itm}
+load net {ACC1:acc#134.itm(0)} -pin  "ACC1:acc#134" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134.itm}
+load net {ACC1:acc#134.itm(1)} -pin  "ACC1:acc#134" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134.itm}
+load inst "ACC1:mul#91" "mul(2,0,13,0,14)" "INTERFACE" -attr xrf 18509 -attr oid 655 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,13,0,14)"
+load net {ACC1:acc#134.itm(0)} -pin  "ACC1:mul#91" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134.itm}
+load net {ACC1:acc#134.itm(1)} -pin  "ACC1:mul#91" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134.itm}
+load net {PWR} -pin  "ACC1:mul#91" {B(0)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {GND} -pin  "ACC1:mul#91" {B(1)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {PWR} -pin  "ACC1:mul#91" {B(2)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {GND} -pin  "ACC1:mul#91" {B(3)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {PWR} -pin  "ACC1:mul#91" {B(4)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {GND} -pin  "ACC1:mul#91" {B(5)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {PWR} -pin  "ACC1:mul#91" {B(6)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {GND} -pin  "ACC1:mul#91" {B(7)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {PWR} -pin  "ACC1:mul#91" {B(8)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {GND} -pin  "ACC1:mul#91" {B(9)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {PWR} -pin  "ACC1:mul#91" {B(10)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {GND} -pin  "ACC1:mul#91" {B(11)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {PWR} -pin  "ACC1:mul#91" {B(12)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {ACC1:mul#91.itm(0)} -pin  "ACC1:mul#91" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(1)} -pin  "ACC1:mul#91" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(2)} -pin  "ACC1:mul#91" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(3)} -pin  "ACC1:mul#91" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(4)} -pin  "ACC1:mul#91" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(5)} -pin  "ACC1:mul#91" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(6)} -pin  "ACC1:mul#91" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(7)} -pin  "ACC1:mul#91" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(8)} -pin  "ACC1:mul#91" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(9)} -pin  "ACC1:mul#91" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(10)} -pin  "ACC1:mul#91" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(11)} -pin  "ACC1:mul#91" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(12)} -pin  "ACC1:mul#91" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(13)} -pin  "ACC1:mul#91" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load inst "reg(ACC1:mul#91.itm#1)" "reg(14,1,1,-1,0)" "INTERFACE" -attr xrf 18510 -attr oid 656 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:mul#91.itm#1)}
+load net {ACC1:mul#91.itm(0)} -pin  "reg(ACC1:mul#91.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(1)} -pin  "reg(ACC1:mul#91.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(2)} -pin  "reg(ACC1:mul#91.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(3)} -pin  "reg(ACC1:mul#91.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(4)} -pin  "reg(ACC1:mul#91.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(5)} -pin  "reg(ACC1:mul#91.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(6)} -pin  "reg(ACC1:mul#91.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(7)} -pin  "reg(ACC1:mul#91.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(8)} -pin  "reg(ACC1:mul#91.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(9)} -pin  "reg(ACC1:mul#91.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(10)} -pin  "reg(ACC1:mul#91.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(11)} -pin  "reg(ACC1:mul#91.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(12)} -pin  "reg(ACC1:mul#91.itm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {ACC1:mul#91.itm(13)} -pin  "reg(ACC1:mul#91.itm#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#91.itm#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_14}
+load net {clk} -pin  "reg(ACC1:mul#91.itm#1)" {clk} -attr xrf 18511 -attr oid 657 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:mul#91.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:mul#91.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:mul#91.itm#1(0)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(1)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(2)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(3)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(4)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(5)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(6)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(7)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(8)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(9)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(10)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(11)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(12)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(13)} -pin  "reg(ACC1:mul#91.itm#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load inst "ACC1:acc#147" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18512 -attr oid 658 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv#3.sva(13)} -pin  "ACC1:acc#147" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#28.itm}
+load net {acc.idiv#7.sva(13)} -pin  "ACC1:acc#147" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#33.itm}
+load net {ACC1:acc#147.itm(0)} -pin  "ACC1:acc#147" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load net {ACC1:acc#147.itm(1)} -pin  "ACC1:acc#147" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load inst "ACC1:mul#104" "mul(2,0,9,0,10)" "INTERFACE" -attr xrf 18513 -attr oid 659 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC1:acc#147.itm(0)} -pin  "ACC1:mul#104" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load net {ACC1:acc#147.itm(1)} -pin  "ACC1:mul#104" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load net {PWR} -pin  "ACC1:mul#104" {B(0)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#104" {B(1)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#104" {B(2)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#104" {B(3)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#104" {B(4)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#104" {B(5)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#104" {B(6)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#104" {B(7)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#104" {B(8)} -attr @path {/sobel/sobel:core/C341_9}
+load net {ACC1:mul#104.itm(0)} -pin  "ACC1:mul#104" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(1)} -pin  "ACC1:mul#104" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(2)} -pin  "ACC1:mul#104" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(3)} -pin  "ACC1:mul#104" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(4)} -pin  "ACC1:mul#104" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(5)} -pin  "ACC1:mul#104" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(6)} -pin  "ACC1:mul#104" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(7)} -pin  "ACC1:mul#104" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(8)} -pin  "ACC1:mul#104" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(9)} -pin  "ACC1:mul#104" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load inst "reg(ACC1:mul#104.itm#1)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 18514 -attr oid 660 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:mul#104.itm#1)}
+load net {ACC1:mul#104.itm(0)} -pin  "reg(ACC1:mul#104.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(1)} -pin  "reg(ACC1:mul#104.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(2)} -pin  "reg(ACC1:mul#104.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(3)} -pin  "reg(ACC1:mul#104.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(4)} -pin  "reg(ACC1:mul#104.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(5)} -pin  "reg(ACC1:mul#104.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(6)} -pin  "reg(ACC1:mul#104.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(7)} -pin  "reg(ACC1:mul#104.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(8)} -pin  "reg(ACC1:mul#104.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {ACC1:mul#104.itm(9)} -pin  "reg(ACC1:mul#104.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm}
+load net {GND} -pin  "reg(ACC1:mul#104.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#104.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#104.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#104.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#104.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#104.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#104.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#104.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#104.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#104.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10}
+load net {clk} -pin  "reg(ACC1:mul#104.itm#1)" {clk} -attr xrf 18515 -attr oid 661 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:mul#104.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:mul#104.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:mul#104.itm#1(0)} -pin  "reg(ACC1:mul#104.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm#1}
+load net {ACC1:mul#104.itm#1(1)} -pin  "reg(ACC1:mul#104.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm#1}
+load net {ACC1:mul#104.itm#1(2)} -pin  "reg(ACC1:mul#104.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm#1}
+load net {ACC1:mul#104.itm#1(3)} -pin  "reg(ACC1:mul#104.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm#1}
+load net {ACC1:mul#104.itm#1(4)} -pin  "reg(ACC1:mul#104.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm#1}
+load net {ACC1:mul#104.itm#1(5)} -pin  "reg(ACC1:mul#104.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm#1}
+load net {ACC1:mul#104.itm#1(6)} -pin  "reg(ACC1:mul#104.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm#1}
+load net {ACC1:mul#104.itm#1(7)} -pin  "reg(ACC1:mul#104.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm#1}
+load net {ACC1:mul#104.itm#1(8)} -pin  "reg(ACC1:mul#104.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm#1}
+load net {ACC1:mul#104.itm#1(9)} -pin  "reg(ACC1:mul#104.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#104.itm#1}
+load inst "reg(ACC1:slc(acc.idiv#2)#90.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 18516 -attr oid 662 -attr @path {/sobel/sobel:core/reg(ACC1:slc(acc.idiv#2)#90.itm#1)}
+load net {acc.idiv#2.sva(5)} -pin  "reg(ACC1:slc(acc.idiv#2)#90.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#19.itm}
+load net {GND} -pin  "reg(ACC1:slc(acc.idiv#2)#90.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(ACC1:slc(acc.idiv#2)#90.itm#1)" {clk} -attr xrf 18517 -attr oid 663 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(acc.idiv#2)#90.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(acc.idiv#2)#90.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(acc.idiv#2)#90.itm#1} -pin  "reg(ACC1:slc(acc.idiv#2)#90.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:slc(acc.idiv#2)#90.itm#1}
+load inst "reg(ACC1-3:slc(acc.idiv)#132.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 18518 -attr oid 664 -attr @path {/sobel/sobel:core/reg(ACC1-3:slc(acc.idiv)#132.itm#1)}
+load net {acc.idiv.sva(15)} -pin  "reg(ACC1-3:slc(acc.idiv)#132.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#24.itm}
+load net {GND} -pin  "reg(ACC1-3:slc(acc.idiv)#132.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(ACC1-3:slc(acc.idiv)#132.itm#1)" {clk} -attr xrf 18519 -attr oid 665 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1-3:slc(acc.idiv)#132.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1-3:slc(acc.idiv)#132.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1-3:slc(acc.idiv)#132.itm#1} -pin  "reg(ACC1-3:slc(acc.idiv)#132.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:slc(acc.idiv)#132.itm#1}
+load inst "ACC1:acc#146" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18520 -attr oid 666 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv#3.sva(11)} -pin  "ACC1:acc#146" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#49.itm}
+load net {acc.idiv#7.sva(11)} -pin  "ACC1:acc#146" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#48.itm}
+load net {ACC1:acc#146.itm(0)} -pin  "ACC1:acc#146" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {ACC1:acc#146.itm(1)} -pin  "ACC1:acc#146" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load inst "ACC1:mul#103" "mul(2,0,7,0,8)" "INTERFACE" -attr xrf 18521 -attr oid 667 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,7,0,8)"
+load net {ACC1:acc#146.itm(0)} -pin  "ACC1:mul#103" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {ACC1:acc#146.itm(1)} -pin  "ACC1:mul#103" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {PWR} -pin  "ACC1:mul#103" {B(0)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#103" {B(1)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#103" {B(2)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#103" {B(3)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#103" {B(4)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#103" {B(5)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#103" {B(6)} -attr @path {/sobel/sobel:core/C85_7}
+load net {ACC1:mul#103.itm(0)} -pin  "ACC1:mul#103" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(1)} -pin  "ACC1:mul#103" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(2)} -pin  "ACC1:mul#103" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(3)} -pin  "ACC1:mul#103" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(4)} -pin  "ACC1:mul#103" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(5)} -pin  "ACC1:mul#103" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(6)} -pin  "ACC1:mul#103" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(7)} -pin  "ACC1:mul#103" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load inst "reg(ACC1:mul#103.itm#1)" "reg(8,1,1,-1,0)" "INTERFACE" -attr xrf 18522 -attr oid 668 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:mul#103.itm#1)}
+load net {ACC1:mul#103.itm(0)} -pin  "reg(ACC1:mul#103.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(1)} -pin  "reg(ACC1:mul#103.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(2)} -pin  "reg(ACC1:mul#103.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(3)} -pin  "reg(ACC1:mul#103.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(4)} -pin  "reg(ACC1:mul#103.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(5)} -pin  "reg(ACC1:mul#103.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(6)} -pin  "reg(ACC1:mul#103.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {ACC1:mul#103.itm(7)} -pin  "reg(ACC1:mul#103.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm}
+load net {GND} -pin  "reg(ACC1:mul#103.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#103.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#103.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#103.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#103.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#103.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#103.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_8}
+load net {GND} -pin  "reg(ACC1:mul#103.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_8}
+load net {clk} -pin  "reg(ACC1:mul#103.itm#1)" {clk} -attr xrf 18523 -attr oid 669 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:mul#103.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:mul#103.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:mul#103.itm#1(0)} -pin  "reg(ACC1:mul#103.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm#1}
+load net {ACC1:mul#103.itm#1(1)} -pin  "reg(ACC1:mul#103.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm#1}
+load net {ACC1:mul#103.itm#1(2)} -pin  "reg(ACC1:mul#103.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm#1}
+load net {ACC1:mul#103.itm#1(3)} -pin  "reg(ACC1:mul#103.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm#1}
+load net {ACC1:mul#103.itm#1(4)} -pin  "reg(ACC1:mul#103.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm#1}
+load net {ACC1:mul#103.itm#1(5)} -pin  "reg(ACC1:mul#103.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm#1}
+load net {ACC1:mul#103.itm#1(6)} -pin  "reg(ACC1:mul#103.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm#1}
+load net {ACC1:mul#103.itm#1(7)} -pin  "reg(ACC1:mul#103.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#103.itm#1}
+load inst "reg(ACC1:slc(acc.idiv)#91.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 18524 -attr oid 670 -attr @path {/sobel/sobel:core/reg(ACC1:slc(acc.idiv)#91.itm#1)}
+load net {acc.idiv.sva(7)} -pin  "reg(ACC1:slc(acc.idiv)#91.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#19.itm}
+load net {GND} -pin  "reg(ACC1:slc(acc.idiv)#91.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(ACC1:slc(acc.idiv)#91.itm#1)" {clk} -attr xrf 18525 -attr oid 671 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(acc.idiv)#91.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(acc.idiv)#91.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(acc.idiv)#91.itm#1} -pin  "reg(ACC1:slc(acc.idiv)#91.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:slc(acc.idiv)#91.itm#1}
+load inst "reg(ACC1-3:slc(acc.idiv)#131.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 18526 -attr oid 672 -attr @path {/sobel/sobel:core/reg(ACC1-3:slc(acc.idiv)#131.itm#1)}
+load net {acc.idiv.sva(13)} -pin  "reg(ACC1-3:slc(acc.idiv)#131.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#22.itm}
+load net {GND} -pin  "reg(ACC1-3:slc(acc.idiv)#131.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(ACC1-3:slc(acc.idiv)#131.itm#1)" {clk} -attr xrf 18527 -attr oid 673 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1-3:slc(acc.idiv)#131.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1-3:slc(acc.idiv)#131.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1-3:slc(acc.idiv)#131.itm#1} -pin  "reg(ACC1-3:slc(acc.idiv)#131.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:slc(acc.idiv)#131.itm#1}
+load inst "ACC1:acc#141" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18528 -attr oid 674 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv.sva(9)} -pin  "ACC1:acc#141" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#38.itm}
+load net {acc.idiv#2.sva(9)} -pin  "ACC1:acc#141" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#33.itm}
+load net {ACC1:acc#141.itm(0)} -pin  "ACC1:acc#141" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141.itm}
+load net {ACC1:acc#141.itm(1)} -pin  "ACC1:acc#141" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141.itm}
+load inst "ACC1:mul#98" "mul(2,0,5,0,6)" "INTERFACE" -attr xrf 18529 -attr oid 675 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc#141.itm(0)} -pin  "ACC1:mul#98" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141.itm}
+load net {ACC1:acc#141.itm(1)} -pin  "ACC1:mul#98" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141.itm}
+load net {PWR} -pin  "ACC1:mul#98" {B(0)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#98" {B(1)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#98" {B(2)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#98" {B(3)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#98" {B(4)} -attr @path {/sobel/sobel:core/C21_5}
+load net {ACC1:mul#98.itm(0)} -pin  "ACC1:mul#98" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm}
+load net {ACC1:mul#98.itm(1)} -pin  "ACC1:mul#98" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm}
+load net {ACC1:mul#98.itm(2)} -pin  "ACC1:mul#98" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm}
+load net {ACC1:mul#98.itm(3)} -pin  "ACC1:mul#98" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm}
+load net {ACC1:mul#98.itm(4)} -pin  "ACC1:mul#98" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm}
+load net {ACC1:mul#98.itm(5)} -pin  "ACC1:mul#98" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm}
+load inst "reg(ACC1:mul#98.itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 18530 -attr oid 676 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:mul#98.itm#1)}
+load net {ACC1:mul#98.itm(0)} -pin  "reg(ACC1:mul#98.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm}
+load net {ACC1:mul#98.itm(1)} -pin  "reg(ACC1:mul#98.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm}
+load net {ACC1:mul#98.itm(2)} -pin  "reg(ACC1:mul#98.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm}
+load net {ACC1:mul#98.itm(3)} -pin  "reg(ACC1:mul#98.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm}
+load net {ACC1:mul#98.itm(4)} -pin  "reg(ACC1:mul#98.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm}
+load net {ACC1:mul#98.itm(5)} -pin  "reg(ACC1:mul#98.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm}
+load net {GND} -pin  "reg(ACC1:mul#98.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:mul#98.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:mul#98.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:mul#98.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:mul#98.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:mul#98.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(ACC1:mul#98.itm#1)" {clk} -attr xrf 18531 -attr oid 677 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:mul#98.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:mul#98.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:mul#98.itm#1(0)} -pin  "reg(ACC1:mul#98.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm#1}
+load net {ACC1:mul#98.itm#1(1)} -pin  "reg(ACC1:mul#98.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm#1}
+load net {ACC1:mul#98.itm#1(2)} -pin  "reg(ACC1:mul#98.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm#1}
+load net {ACC1:mul#98.itm#1(3)} -pin  "reg(ACC1:mul#98.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm#1}
+load net {ACC1:mul#98.itm#1(4)} -pin  "reg(ACC1:mul#98.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm#1}
+load net {ACC1:mul#98.itm#1(5)} -pin  "reg(ACC1:mul#98.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#98.itm#1}
+load inst "reg(ACC1:slc(acc.idiv#3)#36.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 18532 -attr oid 678 -attr @path {/sobel/sobel:core/reg(ACC1:slc(acc.idiv#3)#36.itm#1)}
+load net {acc.idiv#3.sva(3)} -pin  "reg(ACC1:slc(acc.idiv#3)#36.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#25.itm}
+load net {GND} -pin  "reg(ACC1:slc(acc.idiv#3)#36.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(ACC1:slc(acc.idiv#3)#36.itm#1)" {clk} -attr xrf 18533 -attr oid 679 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(acc.idiv#3)#36.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(acc.idiv#3)#36.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(acc.idiv#3)#36.itm#1} -pin  "reg(ACC1:slc(acc.idiv#3)#36.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:slc(acc.idiv#3)#36.itm#1}
+load inst "reg(ACC1-2:slc(acc.idiv)#132.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 18534 -attr oid 680 -attr @path {/sobel/sobel:core/reg(ACC1-2:slc(acc.idiv)#132.itm#1)}
+load net {acc.idiv#3.sva(15)} -pin  "reg(ACC1-2:slc(acc.idiv)#132.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#22.itm}
+load net {GND} -pin  "reg(ACC1-2:slc(acc.idiv)#132.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(ACC1-2:slc(acc.idiv)#132.itm#1)" {clk} -attr xrf 18535 -attr oid 681 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1-2:slc(acc.idiv)#132.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1-2:slc(acc.idiv)#132.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1-2:slc(acc.idiv)#132.itm#1} -pin  "reg(ACC1-2:slc(acc.idiv)#132.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:slc(acc.idiv)#132.itm#1}
+load inst "ACC1:acc#211" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18536 -attr oid 682 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#201.itm(4)} -pin  "ACC1:acc#211" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#258.itm}
+load net {ACC1:acc#162.itm(3)} -pin  "ACC1:acc#211" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#258.itm}
+load net {acc.imod#7.sva(1)} -pin  "ACC1:acc#211" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#259.itm}
+load net {ACC1:acc#162.itm(4)} -pin  "ACC1:acc#211" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#259.itm}
+load net {ACC1:acc#211.itm(0)} -pin  "ACC1:acc#211" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(1)} -pin  "ACC1:acc#211" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(2)} -pin  "ACC1:acc#211" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load inst "ACC1:not" "not(1)" "INTERFACE" -attr xrf 18537 -attr oid 683 -attr @path {/sobel/sobel:core/ACC1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#19.sva(2)} -pin  "ACC1:not" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#19.sva)#4.itm}
+load net {ACC1:not.itm} -pin  "ACC1:not" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load inst "ACC1:acc#286" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18538 -attr oid 684 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286} -attr area 2.320458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.imod#19.sva(1)} -pin  "ACC1:acc#286" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#19.sva)#3.itm}
+load net {ACC1:not.itm} -pin  "ACC1:acc#286" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:acc#286.itm(0)} -pin  "ACC1:acc#286" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(1)} -pin  "ACC1:acc#286" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load inst "ACC1-3:not#49" "not(1)" "INTERFACE" -attr xrf 18539 -attr oid 685 -attr @path {/sobel/sobel:core/ACC1-3:not#49} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#7.sva(1)} -pin  "ACC1-3:not#49" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#3.itm}
+load net {ACC1-3:not#49.itm} -pin  "ACC1-3:not#49" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#49.itm}
+load inst "ACC1-3:not#50" "not(1)" "INTERFACE" -attr xrf 18540 -attr oid 686 -attr @path {/sobel/sobel:core/ACC1-3:not#50} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#7.sva(2)} -pin  "ACC1-3:not#50" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#4.itm}
+load net {ACC1-3:not#50.itm} -pin  "ACC1-3:not#50" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#50.itm}
+load inst "ACC1:acc#282" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 18541 -attr oid 687 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#282" {A(0)} -attr @path {/sobel/sobel:core/conc#314.itm}
+load net {acc.imod#7.sva(0)} -pin  "ACC1:acc#282" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#314.itm}
+load net {PWR} -pin  "ACC1:acc#282" {A(2)} -attr @path {/sobel/sobel:core/conc#314.itm}
+load net {ACC1-3:not#50.itm} -pin  "ACC1:acc#282" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#394.itm}
+load net {ACC1-3:not#49.itm} -pin  "ACC1:acc#282" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#394.itm}
+load net {ACC1:acc#282.itm(0)} -pin  "ACC1:acc#282" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(1)} -pin  "ACC1:acc#282" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(2)} -pin  "ACC1:acc#282" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load inst "ACC1:not#120" "not(1)" "INTERFACE" -attr xrf 18542 -attr oid 688 -attr @path {/sobel/sobel:core/ACC1:not#120} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#282.itm(2)} -pin  "ACC1:not#120" {A(0)} -attr @path {/sobel/sobel:core/ACC1:slc#52.itm}
+load net {ACC1:not#120.itm} -pin  "ACC1:not#120" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#120.itm}
+load inst "ACC1:acc#233" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18543 -attr oid 689 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#211.itm(0)} -pin  "ACC1:acc#233" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(1)} -pin  "ACC1:acc#233" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(2)} -pin  "ACC1:acc#233" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:not#120.itm} -pin  "ACC1:acc#233" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#404.itm}
+load net {ACC1:acc#286.itm(0)} -pin  "ACC1:acc#233" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#404.itm}
+load net {ACC1:acc#286.itm(1)} -pin  "ACC1:acc#233" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#404.itm}
+load net {ACC1:acc#233.itm(0)} -pin  "ACC1:acc#233" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(1)} -pin  "ACC1:acc#233" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(2)} -pin  "ACC1:acc#233" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(3)} -pin  "ACC1:acc#233" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load inst "acc" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18544 -attr oid 690 -attr vt d -attr @path {/sobel/sobel:core/acc} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "acc" {A(0)} -attr @path {/sobel/sobel:core/conc#316.itm}
+load net {acc.idiv#7.sva(2)} -pin  "acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#316.itm}
+load net {acc.idiv#7.sva(4)} -pin  "acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#304.itm}
+load net {acc.idiv#7.sva(3)} -pin  "acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#304.itm}
+load net {acc.itm(0)} -pin  "acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(1)} -pin  "acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load net {acc.itm(2)} -pin  "acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.itm}
+load inst "ACC1:acc#294" "add(2,0,1,0,3)" "INTERFACE" -attr xrf 18545 -attr oid 691 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#294} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,3)"
+load net {acc.itm(1)} -pin  "ACC1:acc#294" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.itm(2)} -pin  "ACC1:acc#294" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc.itm}
+load net {acc.idiv#7.sva(1)} -pin  "ACC1:acc#294" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#47.itm}
+load net {ACC1:acc#294.itm(0)} -pin  "ACC1:acc#294" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(1)} -pin  "ACC1:acc#294" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(2)} -pin  "ACC1:acc#294" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load inst "ACC1:acc#245" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 18546 -attr oid 692 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#233.itm(0)} -pin  "ACC1:acc#245" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(1)} -pin  "ACC1:acc#245" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(2)} -pin  "ACC1:acc#245" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(3)} -pin  "ACC1:acc#245" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {PWR} -pin  "ACC1:acc#245" {B(0)} -attr @path {/sobel/sobel:core/conc#315.itm}
+load net {ACC1:acc#294.itm(0)} -pin  "ACC1:acc#245" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#315.itm}
+load net {ACC1:acc#294.itm(1)} -pin  "ACC1:acc#245" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#315.itm}
+load net {ACC1:acc#294.itm(2)} -pin  "ACC1:acc#245" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#315.itm}
+load net {ACC1:acc#245.itm(0)} -pin  "ACC1:acc#245" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(1)} -pin  "ACC1:acc#245" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(2)} -pin  "ACC1:acc#245" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(3)} -pin  "ACC1:acc#245" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(4)} -pin  "ACC1:acc#245" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load inst "acc#19" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18547 -attr oid 693 -attr vt d -attr @path {/sobel/sobel:core/acc#19} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "acc#19" {A(0)} -attr @path {/sobel/sobel:core/conc#318.itm}
+load net {ACC1:acc#201.itm(4)} -pin  "acc#19" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#318.itm}
+load net {ACC1:acc#174.itm(3)} -pin  "acc#19" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#306.itm}
+load net {ACC1:acc#174.itm(2)} -pin  "acc#19" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#306.itm}
+load net {acc#19.itm(0)} -pin  "acc#19" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#19.itm}
+load net {acc#19.itm(1)} -pin  "acc#19" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#19.itm}
+load net {acc#19.itm(2)} -pin  "acc#19" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#19.itm}
+load inst "acc#20" "add(3,0,4,0,5)" "INTERFACE" -attr xrf 18548 -attr oid 694 -attr vt d -attr @path {/sobel/sobel:core/acc#20} -attr area 5.298136 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,5)"
+load net {PWR} -pin  "acc#20" {A(0)} -attr @path {/sobel/sobel:core/conc#317.itm}
+load net {acc#19.itm(1)} -pin  "acc#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#317.itm}
+load net {acc#19.itm(2)} -pin  "acc#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#317.itm}
+load net {ACC1:acc#174.itm(4)} -pin  "acc#20" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#308.itm}
+load net {ACC1:acc#230.sdt(1)} -pin  "acc#20" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#308.itm}
+load net {ACC1:acc#230.sdt(2)} -pin  "acc#20" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#308.itm}
+load net {ACC1:acc#230.sdt(3)} -pin  "acc#20" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#308.itm}
+load net {acc#20.itm(0)} -pin  "acc#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.itm}
+load net {acc#20.itm(1)} -pin  "acc#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.itm}
+load net {acc#20.itm(2)} -pin  "acc#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.itm}
+load net {acc#20.itm(3)} -pin  "acc#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.itm}
+load net {acc#20.itm(4)} -pin  "acc#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#20.itm}
+load inst "ACC1:acc#252" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 18549 -attr oid 695 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#245.itm(0)} -pin  "ACC1:acc#252" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(1)} -pin  "ACC1:acc#252" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(2)} -pin  "ACC1:acc#252" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(3)} -pin  "ACC1:acc#252" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(4)} -pin  "ACC1:acc#252" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#230.sdt(0)} -pin  "ACC1:acc#252" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#411.itm}
+load net {acc#20.itm(1)} -pin  "ACC1:acc#252" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#411.itm}
+load net {acc#20.itm(2)} -pin  "ACC1:acc#252" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#411.itm}
+load net {acc#20.itm(3)} -pin  "ACC1:acc#252" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#411.itm}
+load net {acc#20.itm(4)} -pin  "ACC1:acc#252" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#411.itm}
+load net {ACC1:acc#252.itm(0)} -pin  "ACC1:acc#252" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(1)} -pin  "ACC1:acc#252" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(2)} -pin  "ACC1:acc#252" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(3)} -pin  "ACC1:acc#252" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(4)} -pin  "ACC1:acc#252" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(5)} -pin  "ACC1:acc#252" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load inst "reg(ACC1:acc#252.itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 18550 -attr oid 696 -attr vt dc -attr @path {/sobel/sobel:core/reg(ACC1:acc#252.itm#1)}
+load net {ACC1:acc#252.itm(0)} -pin  "reg(ACC1:acc#252.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(1)} -pin  "reg(ACC1:acc#252.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(2)} -pin  "reg(ACC1:acc#252.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(3)} -pin  "reg(ACC1:acc#252.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(4)} -pin  "reg(ACC1:acc#252.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(5)} -pin  "reg(ACC1:acc#252.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {GND} -pin  "reg(ACC1:acc#252.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:acc#252.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:acc#252.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:acc#252.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:acc#252.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:acc#252.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(ACC1:acc#252.itm#1)" {clk} -attr xrf 18551 -attr oid 697 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#252.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#252.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#252.itm#1(0)} -pin  "reg(ACC1:acc#252.itm#1)" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#252.itm#1}
+load net {ACC1:acc#252.itm#1(1)} -pin  "reg(ACC1:acc#252.itm#1)" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#252.itm#1}
+load net {ACC1:acc#252.itm#1(2)} -pin  "reg(ACC1:acc#252.itm#1)" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#252.itm#1}
+load net {ACC1:acc#252.itm#1(3)} -pin  "reg(ACC1:acc#252.itm#1)" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#252.itm#1}
+load net {ACC1:acc#252.itm#1(4)} -pin  "reg(ACC1:acc#252.itm#1)" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#252.itm#1}
+load net {ACC1:acc#252.itm#1(5)} -pin  "reg(ACC1:acc#252.itm#1)" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#252.itm#1}
+load inst "ACC1:not#144" "not(1)" "INTERFACE" -attr xrf 18552 -attr oid 698 -attr @path {/sobel/sobel:core/ACC1:not#144} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#162.itm(5)} -pin  "ACC1:not#144" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#17.sva)#9.itm}
+load net {ACC1:not#144.itm} -pin  "ACC1:not#144" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#144.itm}
+load inst "ACC1:not#143" "not(1)" "INTERFACE" -attr xrf 18553 -attr oid 699 -attr @path {/sobel/sobel:core/ACC1:not#143} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#189.itm(5)} -pin  "ACC1:not#143" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#9.itm}
+load net {ACC1:not#143.itm} -pin  "ACC1:not#143" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#143.itm}
+load inst "ACC1-2:not#13" "not(1)" "INTERFACE" -attr xrf 18554 -attr oid 700 -attr @path {/sobel/sobel:core/ACC1-2:not#13} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#19.sva(1)} -pin  "ACC1-2:not#13" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#19.sva)#1.itm}
+load net {ACC1-2:not#13.itm} -pin  "ACC1-2:not#13" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#13.itm}
+load inst "ACC1-2:not#14" "not(1)" "INTERFACE" -attr xrf 18555 -attr oid 701 -attr @path {/sobel/sobel:core/ACC1-2:not#14} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#19.sva(2)} -pin  "ACC1-2:not#14" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#19.sva)#2.itm}
+load net {ACC1-2:not#14.itm} -pin  "ACC1-2:not#14" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-2:not#14.itm}
+load inst "ACC1:acc#285" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 18556 -attr oid 702 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#285" {A(0)} -attr @path {/sobel/sobel:core/conc#319.itm}
+load net {acc.imod#19.sva(0)} -pin  "ACC1:acc#285" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#319.itm}
+load net {PWR} -pin  "ACC1:acc#285" {A(2)} -attr @path {/sobel/sobel:core/conc#319.itm}
+load net {ACC1-2:not#14.itm} -pin  "ACC1:acc#285" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#403.itm}
+load net {ACC1-2:not#13.itm} -pin  "ACC1:acc#285" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#403.itm}
+load net {ACC1:acc#285.itm(0)} -pin  "ACC1:acc#285" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(1)} -pin  "ACC1:acc#285" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(2)} -pin  "ACC1:acc#285" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load inst "ACC1:not#129" "not(1)" "INTERFACE" -attr xrf 18557 -attr oid 703 -attr @path {/sobel/sobel:core/ACC1:not#129} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#285.itm(2)} -pin  "ACC1:not#129" {A(0)} -attr @path {/sobel/sobel:core/ACC1:slc#55.itm}
+load net {ACC1:not#129.itm} -pin  "ACC1:not#129" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#129.itm}
+load inst "ACC1:not#145" "not(1)" "INTERFACE" -attr xrf 18558 -attr oid 704 -attr @path {/sobel/sobel:core/ACC1:not#145} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#201.itm(5)} -pin  "ACC1:not#145" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#8.itm}
+load net {ACC1:not#145.itm} -pin  "ACC1:not#145" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#145.itm}
+load inst "ACC1:not#146" "not(1)" "INTERFACE" -attr xrf 18559 -attr oid 705 -attr @path {/sobel/sobel:core/ACC1:not#146} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#174.itm(5)} -pin  "ACC1:not#146" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#25.sva)#8.itm}
+load net {ACC1:not#146.itm} -pin  "ACC1:not#146" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#146.itm}
+load inst "ACC1:not#139" "not(1)" "INTERFACE" -attr xrf 18560 -attr oid 706 -attr @path {/sobel/sobel:core/ACC1:not#139} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#201.itm(5)} -pin  "ACC1:not#139" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva).itm}
+load net {ACC1:not#139.itm} -pin  "ACC1:not#139" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#139.itm}
+load inst "ACC1:not#137" "not(1)" "INTERFACE" -attr xrf 18561 -attr oid 707 -attr @path {/sobel/sobel:core/ACC1:not#137} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#162.itm(5)} -pin  "ACC1:not#137" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#17.sva).itm}
+load net {ACC1:not#137.itm} -pin  "ACC1:not#137" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#137.itm}
+load inst "ACC1:not#134" "not(1)" "INTERFACE" -attr xrf 18562 -attr oid 708 -attr @path {/sobel/sobel:core/ACC1:not#134} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#7.sva(2)} -pin  "ACC1:not#134" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva).itm}
+load net {ACC1:not#134.itm} -pin  "ACC1:not#134" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#134.itm}
+load inst "ACC1:acc#243" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 18563 -attr oid 709 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:not#145.itm} -pin  "ACC1:acc#243" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#278.itm}
+load net {ACC1:not#129.itm} -pin  "ACC1:acc#243" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#278.itm}
+load net {ACC1:not#143.itm} -pin  "ACC1:acc#243" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#278.itm}
+load net {ACC1:not#144.itm} -pin  "ACC1:acc#243" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#278.itm}
+load net {ACC1:not#134.itm} -pin  "ACC1:acc#243" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#279.itm}
+load net {ACC1:not#137.itm} -pin  "ACC1:acc#243" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#279.itm}
+load net {ACC1:not#139.itm} -pin  "ACC1:acc#243" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#279.itm}
+load net {ACC1:not#146.itm} -pin  "ACC1:acc#243" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#279.itm}
+load net {ACC1:acc#243.itm(0)} -pin  "ACC1:acc#243" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(1)} -pin  "ACC1:acc#243" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(2)} -pin  "ACC1:acc#243" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(3)} -pin  "ACC1:acc#243" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(4)} -pin  "ACC1:acc#243" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load inst "ACC1:acc#251" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 18564 -attr oid 710 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#243.itm(0)} -pin  "ACC1:acc#251" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(1)} -pin  "ACC1:acc#251" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(2)} -pin  "ACC1:acc#251" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(3)} -pin  "ACC1:acc#251" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(4)} -pin  "ACC1:acc#251" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {acc.idiv#3.sva(9)} -pin  "ACC1:acc#251" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#320.itm}
+load net {acc.idiv#3.sva(9)} -pin  "ACC1:acc#251" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#320.itm}
+load net {GND} -pin  "ACC1:acc#251" {B(2)} -attr @path {/sobel/sobel:core/conc#320.itm}
+load net {acc.idiv#3.sva(4)} -pin  "ACC1:acc#251" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#320.itm}
+load net {acc.idiv#7.sva(5)} -pin  "ACC1:acc#251" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#320.itm}
+load net {ACC1:acc#251.itm(0)} -pin  "ACC1:acc#251" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(1)} -pin  "ACC1:acc#251" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(2)} -pin  "ACC1:acc#251" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(3)} -pin  "ACC1:acc#251" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(4)} -pin  "ACC1:acc#251" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(5)} -pin  "ACC1:acc#251" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load inst "reg(ACC1:acc#251.itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 18565 -attr oid 711 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#251.itm#1)}
+load net {ACC1:acc#251.itm(0)} -pin  "reg(ACC1:acc#251.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(1)} -pin  "reg(ACC1:acc#251.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(2)} -pin  "reg(ACC1:acc#251.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(3)} -pin  "reg(ACC1:acc#251.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(4)} -pin  "reg(ACC1:acc#251.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(5)} -pin  "reg(ACC1:acc#251.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {GND} -pin  "reg(ACC1:acc#251.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:acc#251.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:acc#251.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:acc#251.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:acc#251.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(ACC1:acc#251.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(ACC1:acc#251.itm#1)" {clk} -attr xrf 18566 -attr oid 712 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#251.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#251.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#251.itm#1(0)} -pin  "reg(ACC1:acc#251.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm#1}
+load net {ACC1:acc#251.itm#1(1)} -pin  "reg(ACC1:acc#251.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm#1}
+load net {ACC1:acc#251.itm#1(2)} -pin  "reg(ACC1:acc#251.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm#1}
+load net {ACC1:acc#251.itm#1(3)} -pin  "reg(ACC1:acc#251.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm#1}
+load net {ACC1:acc#251.itm#1(4)} -pin  "reg(ACC1:acc#251.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm#1}
+load net {ACC1:acc#251.itm#1(5)} -pin  "reg(ACC1:acc#251.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm#1}
+load inst "ACC1:acc#229" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18567 -attr oid 713 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#3.sva(17)} -pin  "ACC1:acc#229" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#6.itm}
+load net {acc.idiv#3.sva(17)} -pin  "ACC1:acc#229" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#6.itm}
+load net {acc.idiv#3.sva(5)} -pin  "ACC1:acc#229" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs.itm}
+load net {acc.idiv#3.sva(5)} -pin  "ACC1:acc#229" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs.itm}
+load net {ACC1:acc#229.itm(0)} -pin  "ACC1:acc#229" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(1)} -pin  "ACC1:acc#229" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(2)} -pin  "ACC1:acc#229" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load inst "ACC1:acc#228" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18568 -attr oid 714 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.idiv#3.sva(7)} -pin  "ACC1:acc#228" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1.itm}
+load net {acc.idiv#3.sva(7)} -pin  "ACC1:acc#228" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#1.itm}
+load net {acc.idiv#3.sva(9)} -pin  "ACC1:acc#228" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#2.itm}
+load net {acc.idiv#3.sva(9)} -pin  "ACC1:acc#228" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#2.itm}
+load net {ACC1:acc#228.itm(0)} -pin  "ACC1:acc#228" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(1)} -pin  "ACC1:acc#228" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(2)} -pin  "ACC1:acc#228" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load inst "ACC1:acc#242" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18569 -attr oid 715 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#229.itm(0)} -pin  "ACC1:acc#242" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(1)} -pin  "ACC1:acc#242" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(2)} -pin  "ACC1:acc#242" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#228.itm(0)} -pin  "ACC1:acc#242" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(1)} -pin  "ACC1:acc#242" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(2)} -pin  "ACC1:acc#242" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#242.itm(0)} -pin  "ACC1:acc#242" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#242.itm(1)} -pin  "ACC1:acc#242" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#242.itm(2)} -pin  "ACC1:acc#242" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#242.itm(3)} -pin  "ACC1:acc#242" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load inst "ACC1:acc#250" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 18570 -attr oid 716 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {acc.idiv#3.sva(11)} -pin  "ACC1:acc#250" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#321.itm}
+load net {acc.idiv#3.sva(11)} -pin  "ACC1:acc#250" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#321.itm}
+load net {GND} -pin  "ACC1:acc#250" {A(2)} -attr @path {/sobel/sobel:core/conc#321.itm}
+load net {acc.idiv#7.sva(4)} -pin  "ACC1:acc#250" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#321.itm}
+load net {acc.idiv#7.sva(7)} -pin  "ACC1:acc#250" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#321.itm}
+load net {ACC1:acc#242.itm(0)} -pin  "ACC1:acc#250" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#242.itm(1)} -pin  "ACC1:acc#250" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#242.itm(2)} -pin  "ACC1:acc#250" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#242.itm(3)} -pin  "ACC1:acc#250" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#250.itm(0)} -pin  "ACC1:acc#250" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.itm}
+load net {ACC1:acc#250.itm(1)} -pin  "ACC1:acc#250" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.itm}
+load net {ACC1:acc#250.itm(2)} -pin  "ACC1:acc#250" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.itm}
+load net {ACC1:acc#250.itm(3)} -pin  "ACC1:acc#250" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.itm}
+load net {ACC1:acc#250.itm(4)} -pin  "ACC1:acc#250" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.itm}
+load net {ACC1:acc#250.itm(5)} -pin  "ACC1:acc#250" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.itm}
+load inst "ACC1:acc#130" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18571 -attr oid 717 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#130} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv.sva(6)} -pin  "ACC1:acc#130" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#37.itm}
+load net {acc.idiv#2.sva(6)} -pin  "ACC1:acc#130" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#32.itm}
+load net {ACC1:acc#130.itm(0)} -pin  "ACC1:acc#130" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#130.itm}
+load net {ACC1:acc#130.itm(1)} -pin  "ACC1:acc#130" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#130.itm}
+load inst "ACC1:mul" "mul(2,0,5,0,6)" "INTERFACE" -attr xrf 18572 -attr oid 718 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc#130.itm(0)} -pin  "ACC1:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#130.itm}
+load net {ACC1:acc#130.itm(1)} -pin  "ACC1:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#130.itm}
+load net {PWR} -pin  "ACC1:mul" {B(0)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul" {B(1)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul" {B(2)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul" {B(3)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul" {B(4)} -attr @path {/sobel/sobel:core/C21_5}
+load net {ACC1:mul.itm(0)} -pin  "ACC1:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(1)} -pin  "ACC1:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(2)} -pin  "ACC1:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(3)} -pin  "ACC1:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(4)} -pin  "ACC1:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(5)} -pin  "ACC1:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load inst "ACC1:acc#255" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 18573 -attr oid 719 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#250.itm(0)} -pin  "ACC1:acc#255" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.itm}
+load net {ACC1:acc#250.itm(1)} -pin  "ACC1:acc#255" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.itm}
+load net {ACC1:acc#250.itm(2)} -pin  "ACC1:acc#255" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.itm}
+load net {ACC1:acc#250.itm(3)} -pin  "ACC1:acc#255" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.itm}
+load net {ACC1:acc#250.itm(4)} -pin  "ACC1:acc#255" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.itm}
+load net {ACC1:acc#250.itm(5)} -pin  "ACC1:acc#255" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.itm}
+load net {ACC1:mul.itm(0)} -pin  "ACC1:acc#255" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(1)} -pin  "ACC1:acc#255" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(2)} -pin  "ACC1:acc#255" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(3)} -pin  "ACC1:acc#255" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(4)} -pin  "ACC1:acc#255" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(5)} -pin  "ACC1:acc#255" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:acc#255.itm(0)} -pin  "ACC1:acc#255" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(1)} -pin  "ACC1:acc#255" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(2)} -pin  "ACC1:acc#255" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(3)} -pin  "ACC1:acc#255" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(4)} -pin  "ACC1:acc#255" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(5)} -pin  "ACC1:acc#255" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(6)} -pin  "ACC1:acc#255" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load inst "reg(ACC1:acc#255.itm#1)" "reg(7,1,1,-1,0)" "INTERFACE" -attr xrf 18574 -attr oid 720 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#255.itm#1)}
+load net {ACC1:acc#255.itm(0)} -pin  "reg(ACC1:acc#255.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(1)} -pin  "reg(ACC1:acc#255.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(2)} -pin  "reg(ACC1:acc#255.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(3)} -pin  "reg(ACC1:acc#255.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(4)} -pin  "reg(ACC1:acc#255.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(5)} -pin  "reg(ACC1:acc#255.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(6)} -pin  "reg(ACC1:acc#255.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {GND} -pin  "reg(ACC1:acc#255.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_7}
+load net {GND} -pin  "reg(ACC1:acc#255.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_7}
+load net {GND} -pin  "reg(ACC1:acc#255.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_7}
+load net {GND} -pin  "reg(ACC1:acc#255.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_7}
+load net {GND} -pin  "reg(ACC1:acc#255.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_7}
+load net {GND} -pin  "reg(ACC1:acc#255.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_7}
+load net {GND} -pin  "reg(ACC1:acc#255.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_7}
+load net {clk} -pin  "reg(ACC1:acc#255.itm#1)" {clk} -attr xrf 18575 -attr oid 721 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#255.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#255.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#255.itm#1(0)} -pin  "reg(ACC1:acc#255.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:acc#255.itm#1(1)} -pin  "reg(ACC1:acc#255.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:acc#255.itm#1(2)} -pin  "reg(ACC1:acc#255.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:acc#255.itm#1(3)} -pin  "reg(ACC1:acc#255.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:acc#255.itm#1(4)} -pin  "reg(ACC1:acc#255.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:acc#255.itm#1(5)} -pin  "reg(ACC1:acc#255.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:acc#255.itm#1(6)} -pin  "reg(ACC1:acc#255.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load inst "ACC1:acc#132" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18576 -attr oid 722 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv.sva(10)} -pin  "ACC1:acc#132" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#44.itm}
+load net {acc.idiv#2.sva(10)} -pin  "ACC1:acc#132" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#44.itm}
+load net {ACC1:acc#132.itm(0)} -pin  "ACC1:acc#132" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(1)} -pin  "ACC1:acc#132" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load inst "ACC1:mul#89" "mul(2,0,9,0,10)" "INTERFACE" -attr xrf 18577 -attr oid 723 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC1:acc#132.itm(0)} -pin  "ACC1:mul#89" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(1)} -pin  "ACC1:mul#89" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {PWR} -pin  "ACC1:mul#89" {B(0)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#89" {B(1)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#89" {B(2)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#89" {B(3)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#89" {B(4)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#89" {B(5)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#89" {B(6)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#89" {B(7)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#89" {B(8)} -attr @path {/sobel/sobel:core/C341_9}
+load net {ACC1:mul#89.itm(0)} -pin  "ACC1:mul#89" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(1)} -pin  "ACC1:mul#89" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(2)} -pin  "ACC1:mul#89" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(3)} -pin  "ACC1:mul#89" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(4)} -pin  "ACC1:mul#89" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(5)} -pin  "ACC1:mul#89" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(6)} -pin  "ACC1:mul#89" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(7)} -pin  "ACC1:mul#89" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(8)} -pin  "ACC1:mul#89" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(9)} -pin  "ACC1:mul#89" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load inst "reg(ACC1:mul#89.itm#1)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 18578 -attr oid 724 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:mul#89.itm#1)}
+load net {ACC1:mul#89.itm(0)} -pin  "reg(ACC1:mul#89.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(1)} -pin  "reg(ACC1:mul#89.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(2)} -pin  "reg(ACC1:mul#89.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(3)} -pin  "reg(ACC1:mul#89.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(4)} -pin  "reg(ACC1:mul#89.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(5)} -pin  "reg(ACC1:mul#89.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(6)} -pin  "reg(ACC1:mul#89.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(7)} -pin  "reg(ACC1:mul#89.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(8)} -pin  "reg(ACC1:mul#89.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {ACC1:mul#89.itm(9)} -pin  "reg(ACC1:mul#89.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm}
+load net {GND} -pin  "reg(ACC1:mul#89.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#89.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#89.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#89.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#89.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#89.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#89.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#89.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#89.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10}
+load net {GND} -pin  "reg(ACC1:mul#89.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10}
+load net {clk} -pin  "reg(ACC1:mul#89.itm#1)" {clk} -attr xrf 18579 -attr oid 725 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:mul#89.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:mul#89.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:mul#89.itm#1(0)} -pin  "reg(ACC1:mul#89.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(1)} -pin  "reg(ACC1:mul#89.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(2)} -pin  "reg(ACC1:mul#89.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(3)} -pin  "reg(ACC1:mul#89.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(4)} -pin  "reg(ACC1:mul#89.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(5)} -pin  "reg(ACC1:mul#89.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(6)} -pin  "reg(ACC1:mul#89.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(7)} -pin  "reg(ACC1:mul#89.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(8)} -pin  "reg(ACC1:mul#89.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(9)} -pin  "reg(ACC1:mul#89.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load inst "ACC1:acc#145" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18580 -attr oid 726 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv#3.sva(9)} -pin  "ACC1:acc#145" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#34.itm}
+load net {acc.idiv#7.sva(9)} -pin  "ACC1:acc#145" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#26.itm}
+load net {ACC1:acc#145.itm(0)} -pin  "ACC1:acc#145" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145.itm}
+load net {ACC1:acc#145.itm(1)} -pin  "ACC1:acc#145" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145.itm}
+load inst "ACC1:mul#102" "mul(2,0,5,0,6)" "INTERFACE" -attr xrf 18581 -attr oid 727 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#102} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc#145.itm(0)} -pin  "ACC1:mul#102" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145.itm}
+load net {ACC1:acc#145.itm(1)} -pin  "ACC1:mul#102" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145.itm}
+load net {PWR} -pin  "ACC1:mul#102" {B(0)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#102" {B(1)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#102" {B(2)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#102" {B(3)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#102" {B(4)} -attr @path {/sobel/sobel:core/C21_5}
+load net {ACC1:mul#102.itm(0)} -pin  "ACC1:mul#102" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#102.itm}
+load net {ACC1:mul#102.itm(1)} -pin  "ACC1:mul#102" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#102.itm}
+load net {ACC1:mul#102.itm(2)} -pin  "ACC1:mul#102" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#102.itm}
+load net {ACC1:mul#102.itm(3)} -pin  "ACC1:mul#102" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#102.itm}
+load net {ACC1:mul#102.itm(4)} -pin  "ACC1:mul#102" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#102.itm}
+load net {ACC1:mul#102.itm(5)} -pin  "ACC1:mul#102" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#102.itm}
+load inst "ACC1:acc#296" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18582 -attr oid 728 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296} -attr area 4.303074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {acc.idiv#3.sva(5)} -pin  "ACC1:acc#296" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#286.itm}
+load net {acc.idiv.sva(7)} -pin  "ACC1:acc#296" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#286.itm}
+load net {acc.idiv#3.sva(7)} -pin  "ACC1:acc#296" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#286.itm}
+load net {acc.idiv#3.sva(7)} -pin  "ACC1:acc#296" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#287.itm}
+load net {acc.idiv#2.sva(7)} -pin  "ACC1:acc#296" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#287.itm}
+load net {acc.idiv#7.sva(7)} -pin  "ACC1:acc#296" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#287.itm}
+load net {ACC1:acc#296.itm(0)} -pin  "ACC1:acc#296" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(1)} -pin  "ACC1:acc#296" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(2)} -pin  "ACC1:acc#296" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(3)} -pin  "ACC1:acc#296" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load inst "ACC1:acc#297" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18583 -attr oid 729 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297} -attr area 4.303074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {acc.idiv.sva(5)} -pin  "ACC1:acc#297" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#413.itm}
+load net {acc.idiv.sva(5)} -pin  "ACC1:acc#297" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#413.itm}
+load net {acc.idiv.sva(4)} -pin  "ACC1:acc#297" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#413.itm}
+load net {acc.idiv.sva(7)} -pin  "ACC1:acc#297" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#414.itm}
+load net {acc.idiv.sva(7)} -pin  "ACC1:acc#297" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#414.itm}
+load net {acc.idiv#2.sva(4)} -pin  "ACC1:acc#297" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#414.itm}
+load net {ACC1:acc#297.itm(0)} -pin  "ACC1:acc#297" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(1)} -pin  "ACC1:acc#297" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(2)} -pin  "ACC1:acc#297" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(3)} -pin  "ACC1:acc#297" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load inst "ACC1:acc#131" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18584 -attr oid 730 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#131} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv.sva(8)} -pin  "ACC1:acc#131" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#29.itm}
+load net {acc.idiv#2.sva(8)} -pin  "ACC1:acc#131" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#24.itm}
+load net {ACC1:acc#131.itm(0)} -pin  "ACC1:acc#131" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#131.itm}
+load net {ACC1:acc#131.itm(1)} -pin  "ACC1:acc#131" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#131.itm}
+load inst "ACC1:mul#88" "mul(2,0,7,0,8)" "INTERFACE" -attr xrf 18585 -attr oid 731 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,7,0,8)"
+load net {ACC1:acc#131.itm(0)} -pin  "ACC1:mul#88" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#131.itm}
+load net {ACC1:acc#131.itm(1)} -pin  "ACC1:mul#88" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#131.itm}
+load net {PWR} -pin  "ACC1:mul#88" {B(0)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#88" {B(1)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#88" {B(2)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#88" {B(3)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#88" {B(4)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#88" {B(5)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#88" {B(6)} -attr @path {/sobel/sobel:core/C85_7}
+load net {ACC1:mul#88.itm(0)} -pin  "ACC1:mul#88" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(1)} -pin  "ACC1:mul#88" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(2)} -pin  "ACC1:mul#88" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(3)} -pin  "ACC1:mul#88" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(4)} -pin  "ACC1:mul#88" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(5)} -pin  "ACC1:mul#88" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(6)} -pin  "ACC1:mul#88" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(7)} -pin  "ACC1:mul#88" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load inst "ACC1:acc#262" "add(8,0,8,0,9)" "INTERFACE" -attr xrf 18586 -attr oid 732 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,9)"
+load net {ACC1:acc#297.itm(0)} -pin  "ACC1:acc#262" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#412.itm}
+load net {ACC1:acc#297.itm(1)} -pin  "ACC1:acc#262" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#412.itm}
+load net {ACC1:acc#297.itm(2)} -pin  "ACC1:acc#262" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#412.itm}
+load net {ACC1:acc#297.itm(3)} -pin  "ACC1:acc#262" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#412.itm}
+load net {ACC1:acc#296.itm(0)} -pin  "ACC1:acc#262" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#412.itm}
+load net {ACC1:acc#296.itm(1)} -pin  "ACC1:acc#262" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#412.itm}
+load net {ACC1:acc#296.itm(2)} -pin  "ACC1:acc#262" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#412.itm}
+load net {ACC1:acc#296.itm(3)} -pin  "ACC1:acc#262" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#412.itm}
+load net {ACC1:mul#88.itm(0)} -pin  "ACC1:acc#262" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(1)} -pin  "ACC1:acc#262" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(2)} -pin  "ACC1:acc#262" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(3)} -pin  "ACC1:acc#262" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(4)} -pin  "ACC1:acc#262" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(5)} -pin  "ACC1:acc#262" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(6)} -pin  "ACC1:acc#262" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:mul#88.itm(7)} -pin  "ACC1:acc#262" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#88.itm}
+load net {ACC1:acc#262.itm(0)} -pin  "ACC1:acc#262" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(1)} -pin  "ACC1:acc#262" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(2)} -pin  "ACC1:acc#262" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(3)} -pin  "ACC1:acc#262" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(4)} -pin  "ACC1:acc#262" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(5)} -pin  "ACC1:acc#262" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(6)} -pin  "ACC1:acc#262" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(7)} -pin  "ACC1:acc#262" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(8)} -pin  "ACC1:acc#262" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load inst "ACC1:acc#265" "add(10,0,9,0,11)" "INTERFACE" -attr xrf 18587 -attr oid 733 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265} -attr area 11.241230 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,11)"
+load net {acc.idiv.sva(11)} -pin  "ACC1:acc#265" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#322.itm}
+load net {acc.idiv.sva(11)} -pin  "ACC1:acc#265" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#322.itm}
+load net {GND} -pin  "ACC1:acc#265" {A(2)} -attr @path {/sobel/sobel:core/conc#322.itm}
+load net {acc.idiv.sva(5)} -pin  "ACC1:acc#265" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#322.itm}
+load net {ACC1:mul#102.itm(0)} -pin  "ACC1:acc#265" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#322.itm}
+load net {ACC1:mul#102.itm(1)} -pin  "ACC1:acc#265" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#322.itm}
+load net {ACC1:mul#102.itm(2)} -pin  "ACC1:acc#265" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#322.itm}
+load net {ACC1:mul#102.itm(3)} -pin  "ACC1:acc#265" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#322.itm}
+load net {ACC1:mul#102.itm(4)} -pin  "ACC1:acc#265" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#322.itm}
+load net {ACC1:mul#102.itm(5)} -pin  "ACC1:acc#265" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#322.itm}
+load net {ACC1:acc#262.itm(0)} -pin  "ACC1:acc#265" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(1)} -pin  "ACC1:acc#265" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(2)} -pin  "ACC1:acc#265" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(3)} -pin  "ACC1:acc#265" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(4)} -pin  "ACC1:acc#265" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(5)} -pin  "ACC1:acc#265" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(6)} -pin  "ACC1:acc#265" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(7)} -pin  "ACC1:acc#265" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(8)} -pin  "ACC1:acc#265" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#265.itm(0)} -pin  "ACC1:acc#265" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(1)} -pin  "ACC1:acc#265" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(2)} -pin  "ACC1:acc#265" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(3)} -pin  "ACC1:acc#265" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(4)} -pin  "ACC1:acc#265" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(5)} -pin  "ACC1:acc#265" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(6)} -pin  "ACC1:acc#265" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(7)} -pin  "ACC1:acc#265" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(8)} -pin  "ACC1:acc#265" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(9)} -pin  "ACC1:acc#265" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(10)} -pin  "ACC1:acc#265" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load inst "ACC1:acc#137" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18588 -attr oid 734 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv#3.sva(10)} -pin  "ACC1:acc#137" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#39.itm}
+load net {acc.idiv#7.sva(10)} -pin  "ACC1:acc#137" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#36.itm}
+load net {ACC1:acc#137.itm(0)} -pin  "ACC1:acc#137" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load net {ACC1:acc#137.itm(1)} -pin  "ACC1:acc#137" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load inst "ACC1:mul#94" "mul(2,0,9,0,10)" "INTERFACE" -attr xrf 18589 -attr oid 735 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#94} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC1:acc#137.itm(0)} -pin  "ACC1:mul#94" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load net {ACC1:acc#137.itm(1)} -pin  "ACC1:mul#94" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load net {PWR} -pin  "ACC1:mul#94" {B(0)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#94" {B(1)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#94" {B(2)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#94" {B(3)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#94" {B(4)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#94" {B(5)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#94" {B(6)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#94" {B(7)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#94" {B(8)} -attr @path {/sobel/sobel:core/C341_9}
+load net {ACC1:mul#94.itm(0)} -pin  "ACC1:mul#94" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#94.itm}
+load net {ACC1:mul#94.itm(1)} -pin  "ACC1:mul#94" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#94.itm}
+load net {ACC1:mul#94.itm(2)} -pin  "ACC1:mul#94" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#94.itm}
+load net {ACC1:mul#94.itm(3)} -pin  "ACC1:mul#94" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#94.itm}
+load net {ACC1:mul#94.itm(4)} -pin  "ACC1:mul#94" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#94.itm}
+load net {ACC1:mul#94.itm(5)} -pin  "ACC1:mul#94" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#94.itm}
+load net {ACC1:mul#94.itm(6)} -pin  "ACC1:mul#94" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#94.itm}
+load net {ACC1:mul#94.itm(7)} -pin  "ACC1:mul#94" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#94.itm}
+load net {ACC1:mul#94.itm(8)} -pin  "ACC1:mul#94" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#94.itm}
+load net {ACC1:mul#94.itm(9)} -pin  "ACC1:mul#94" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#94.itm}
+load inst "ACC1:acc#268" "add(11,0,11,0,12)" "INTERFACE" -attr xrf 18590 -attr oid 736 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268} -attr area 12.232538 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,0,12)"
+load net {ACC1:acc#265.itm(0)} -pin  "ACC1:acc#268" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(1)} -pin  "ACC1:acc#268" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(2)} -pin  "ACC1:acc#268" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(3)} -pin  "ACC1:acc#268" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(4)} -pin  "ACC1:acc#268" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(5)} -pin  "ACC1:acc#268" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(6)} -pin  "ACC1:acc#268" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(7)} -pin  "ACC1:acc#268" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(8)} -pin  "ACC1:acc#268" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(9)} -pin  "ACC1:acc#268" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(10)} -pin  "ACC1:acc#268" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#189.itm(2)} -pin  "ACC1:acc#268" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#252.itm}
+load net {ACC1:mul#94.itm(0)} -pin  "ACC1:acc#268" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#252.itm}
+load net {ACC1:mul#94.itm(1)} -pin  "ACC1:acc#268" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#252.itm}
+load net {ACC1:mul#94.itm(2)} -pin  "ACC1:acc#268" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#252.itm}
+load net {ACC1:mul#94.itm(3)} -pin  "ACC1:acc#268" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#252.itm}
+load net {ACC1:mul#94.itm(4)} -pin  "ACC1:acc#268" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#252.itm}
+load net {ACC1:mul#94.itm(5)} -pin  "ACC1:acc#268" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#252.itm}
+load net {ACC1:mul#94.itm(6)} -pin  "ACC1:acc#268" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#252.itm}
+load net {ACC1:mul#94.itm(7)} -pin  "ACC1:acc#268" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#252.itm}
+load net {ACC1:mul#94.itm(8)} -pin  "ACC1:acc#268" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#252.itm}
+load net {ACC1:mul#94.itm(9)} -pin  "ACC1:acc#268" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#252.itm}
+load net {ACC1:acc#268.itm(0)} -pin  "ACC1:acc#268" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(1)} -pin  "ACC1:acc#268" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(2)} -pin  "ACC1:acc#268" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(3)} -pin  "ACC1:acc#268" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(4)} -pin  "ACC1:acc#268" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(5)} -pin  "ACC1:acc#268" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(6)} -pin  "ACC1:acc#268" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(7)} -pin  "ACC1:acc#268" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(8)} -pin  "ACC1:acc#268" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(9)} -pin  "ACC1:acc#268" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(10)} -pin  "ACC1:acc#268" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(11)} -pin  "ACC1:acc#268" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load inst "reg(ACC1:acc#268.itm#1)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 18591 -attr oid 737 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#268.itm#1)}
+load net {ACC1:acc#268.itm(0)} -pin  "reg(ACC1:acc#268.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(1)} -pin  "reg(ACC1:acc#268.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(2)} -pin  "reg(ACC1:acc#268.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(3)} -pin  "reg(ACC1:acc#268.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(4)} -pin  "reg(ACC1:acc#268.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(5)} -pin  "reg(ACC1:acc#268.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(6)} -pin  "reg(ACC1:acc#268.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(7)} -pin  "reg(ACC1:acc#268.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(8)} -pin  "reg(ACC1:acc#268.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(9)} -pin  "reg(ACC1:acc#268.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(10)} -pin  "reg(ACC1:acc#268.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(11)} -pin  "reg(ACC1:acc#268.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {GND} -pin  "reg(ACC1:acc#268.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#268.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#268.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#268.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#268.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#268.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#268.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#268.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#268.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#268.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#268.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#268.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(ACC1:acc#268.itm#1)" {clk} -attr xrf 18592 -attr oid 738 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#268.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#268.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#268.itm#1(0)} -pin  "reg(ACC1:acc#268.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(1)} -pin  "reg(ACC1:acc#268.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(2)} -pin  "reg(ACC1:acc#268.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(3)} -pin  "reg(ACC1:acc#268.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(4)} -pin  "reg(ACC1:acc#268.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(5)} -pin  "reg(ACC1:acc#268.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(6)} -pin  "reg(ACC1:acc#268.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(7)} -pin  "reg(ACC1:acc#268.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(8)} -pin  "reg(ACC1:acc#268.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(9)} -pin  "reg(ACC1:acc#268.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(10)} -pin  "reg(ACC1:acc#268.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(11)} -pin  "reg(ACC1:acc#268.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load inst "ACC1:acc#139" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 18593 -attr oid 739 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {acc.idiv#3.sva(14)} -pin  "ACC1:acc#139" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#46.itm}
+load net {acc.idiv#7.sva(14)} -pin  "ACC1:acc#139" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#46.itm}
+load net {ACC1:acc#139.itm(0)} -pin  "ACC1:acc#139" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139.itm}
+load net {ACC1:acc#139.itm(1)} -pin  "ACC1:acc#139" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139.itm}
+load inst "ACC1:mul#96" "mul(2,0,13,0,14)" "INTERFACE" -attr xrf 18594 -attr oid 740 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,13,0,14)"
+load net {ACC1:acc#139.itm(0)} -pin  "ACC1:mul#96" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139.itm}
+load net {ACC1:acc#139.itm(1)} -pin  "ACC1:mul#96" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139.itm}
+load net {PWR} -pin  "ACC1:mul#96" {B(0)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {GND} -pin  "ACC1:mul#96" {B(1)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {PWR} -pin  "ACC1:mul#96" {B(2)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {GND} -pin  "ACC1:mul#96" {B(3)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {PWR} -pin  "ACC1:mul#96" {B(4)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {GND} -pin  "ACC1:mul#96" {B(5)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {PWR} -pin  "ACC1:mul#96" {B(6)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {GND} -pin  "ACC1:mul#96" {B(7)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {PWR} -pin  "ACC1:mul#96" {B(8)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {GND} -pin  "ACC1:mul#96" {B(9)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {PWR} -pin  "ACC1:mul#96" {B(10)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {GND} -pin  "ACC1:mul#96" {B(11)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {PWR} -pin  "ACC1:mul#96" {B(12)} -attr @path {/sobel/sobel:core/C5461_13}
+load net {ACC1:mul#96.itm(0)} -pin  "ACC1:mul#96" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(1)} -pin  "ACC1:mul#96" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(2)} -pin  "ACC1:mul#96" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(3)} -pin  "ACC1:mul#96" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(4)} -pin  "ACC1:mul#96" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(5)} -pin  "ACC1:mul#96" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(6)} -pin  "ACC1:mul#96" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(7)} -pin  "ACC1:mul#96" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(8)} -pin  "ACC1:mul#96" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(9)} -pin  "ACC1:mul#96" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(10)} -pin  "ACC1:mul#96" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(11)} -pin  "ACC1:mul#96" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(12)} -pin  "ACC1:mul#96" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(13)} -pin  "ACC1:mul#96" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load inst "reg(ACC1:mul#96.itm#1)" "reg(14,1,1,-1,0)" "INTERFACE" -attr xrf 18595 -attr oid 741 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:mul#96.itm#1)}
+load net {ACC1:mul#96.itm(0)} -pin  "reg(ACC1:mul#96.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(1)} -pin  "reg(ACC1:mul#96.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(2)} -pin  "reg(ACC1:mul#96.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(3)} -pin  "reg(ACC1:mul#96.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(4)} -pin  "reg(ACC1:mul#96.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(5)} -pin  "reg(ACC1:mul#96.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(6)} -pin  "reg(ACC1:mul#96.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(7)} -pin  "reg(ACC1:mul#96.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(8)} -pin  "reg(ACC1:mul#96.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(9)} -pin  "reg(ACC1:mul#96.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(10)} -pin  "reg(ACC1:mul#96.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(11)} -pin  "reg(ACC1:mul#96.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(12)} -pin  "reg(ACC1:mul#96.itm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {ACC1:mul#96.itm(13)} -pin  "reg(ACC1:mul#96.itm#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_14}
+load net {GND} -pin  "reg(ACC1:mul#96.itm#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_14}
+load net {clk} -pin  "reg(ACC1:mul#96.itm#1)" {clk} -attr xrf 18596 -attr oid 742 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:mul#96.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:mul#96.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:mul#96.itm#1(0)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {ACC1:mul#96.itm#1(1)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {ACC1:mul#96.itm#1(2)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {ACC1:mul#96.itm#1(3)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {ACC1:mul#96.itm#1(4)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {ACC1:mul#96.itm#1(5)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {ACC1:mul#96.itm#1(6)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {ACC1:mul#96.itm#1(7)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {ACC1:mul#96.itm#1(8)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {ACC1:mul#96.itm#1(9)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {ACC1:mul#96.itm#1(10)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {ACC1:mul#96.itm#1(11)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {ACC1:mul#96.itm#1(12)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load net {ACC1:mul#96.itm#1(13)} -pin  "reg(ACC1:mul#96.itm#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#96.itm#1}
+load inst "reg(ACC1:slc(acc.imod)#28.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 18597 -attr oid 743 -attr @path {/sobel/sobel:core/reg(ACC1:slc(acc.imod)#28.itm#1)}
+load net {ACC1:acc#189.itm(4)} -pin  "reg(ACC1:slc(acc.imod)#28.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod.sva).itm}
+load net {GND} -pin  "reg(ACC1:slc(acc.imod)#28.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(ACC1:slc(acc.imod)#28.itm#1)" {clk} -attr xrf 18598 -attr oid 744 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:slc(acc.imod)#28.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:slc(acc.imod)#28.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:slc(acc.imod)#28.itm#1} -pin  "reg(ACC1:slc(acc.imod)#28.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:slc(acc.imod)#28.itm#1}
+load inst "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 18599 -attr oid 745 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)}
+load net {regs.regs(1).sg2.sva(10)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(11)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(12)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(13)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(14)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(15)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(16)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(17)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(18)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {regs.regs(1).sg2.sva(19)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#2.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {clk} -attr xrf 18600 -attr oid 746 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#1.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load inst "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 18601 -attr oid 747 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)}
+load net {regs.regs(1).sg2.sva(0)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(1)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(2)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(3)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(4)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(5)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(6)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(7)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(8)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {regs.regs(1).sg2.sva(9)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva)#1.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {clk} -attr xrf 18602 -attr oid 748 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2)#2.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load inst "reg(regs.regs:slc(regs.regs(2).sg2).itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 18603 -attr oid 749 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2).sg2).itm)}
+load net {regs.regs(1).sg2.sva(20)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(21)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(22)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(23)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(24)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(25)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(26)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(27)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(28)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {regs.regs(1).sg2.sva(29)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sg2.sva).itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {clk} -attr xrf 18604 -attr oid 750 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2).sg2).itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#6.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 18605 -attr oid 751 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#6.itm)}
+load net {regs.regs(1)#1.sva(10)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(11)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(12)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(13)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(14)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(15)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(16)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(17)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(18)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {regs.regs(1)#1.sva(19)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#2.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {clk} -attr xrf 18606 -attr oid 752 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#6.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#6.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load inst "reg(regs.regs:slc(regs.regs(2))#7.itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 18607 -attr oid 753 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2))#7.itm)}
+load net {regs.regs(1)#1.sva(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {regs.regs(1)#1.sva(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva)#1.itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {clk} -attr xrf 18608 -attr oid 754 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2))#7.itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2))#7.itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load inst "reg(regs.regs:slc(regs.regs(2)).itm)" "reg(10,1,1,-1,0)" "INTERFACE" -attr xrf 18609 -attr oid 755 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs:slc(regs.regs(2)).itm)}
+load net {regs.regs(1)#1.sva(20)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(21)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(22)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(23)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(24)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(25)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(26)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(27)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(28)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {regs.regs(1)#1.sva(29)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1)#1.sva).itm}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {GND} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_10#1}
+load net {clk} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {clk} -attr xrf 18610 -attr oid 756 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs:slc(regs.regs(2)).itm(0)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(1)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(2)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(3)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(4)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(5)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(6)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(7)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(8)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(9)} -pin  "reg(regs.regs:slc(regs.regs(2)).itm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load inst "reg(regs.regs(1).sg2.sva)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 18611 -attr oid 757 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(1).sg2.sva)}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "reg(regs.regs(1).sg2.sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "reg(regs.regs(1).sg2.sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "reg(regs.regs(1).sg2.sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "reg(regs.regs(1).sg2.sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "reg(regs.regs(1).sg2.sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "reg(regs.regs(1).sg2.sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "reg(regs.regs(1).sg2.sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "reg(regs.regs(1).sg2.sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "reg(regs.regs(1).sg2.sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "reg(regs.regs(1).sg2.sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "reg(regs.regs(1).sg2.sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "reg(regs.regs(1).sg2.sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "reg(regs.regs(1).sg2.sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "reg(regs.regs(1).sg2.sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "reg(regs.regs(1).sg2.sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "reg(regs.regs(1).sg2.sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "reg(regs.regs(1).sg2.sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "reg(regs.regs(1).sg2.sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "reg(regs.regs(1).sg2.sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "reg(regs.regs(1).sg2.sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "reg(regs.regs(1).sg2.sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "reg(regs.regs(1).sg2.sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "reg(regs.regs(1).sg2.sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "reg(regs.regs(1).sg2.sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "reg(regs.regs(1).sg2.sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "reg(regs.regs(1).sg2.sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "reg(regs.regs(1).sg2.sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "reg(regs.regs(1).sg2.sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "reg(regs.regs(1).sg2.sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "reg(regs.regs(1).sg2.sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1).sg2.sva)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(regs.regs(1).sg2.sva)" {clk} -attr xrf 18612 -attr oid 758 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(1).sg2.sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(1).sg2.sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(1).sg2.sva(0)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(1)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(2)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(3)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(4)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(5)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(6)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(7)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(8)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(9)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(10)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(11)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(12)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(13)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(14)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(15)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(16)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(17)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(18)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(19)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(20)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(21)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(22)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(23)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(24)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(25)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(26)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(27)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(28)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load net {regs.regs(1).sg2.sva(29)} -pin  "reg(regs.regs(1).sg2.sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sg2.sva}
+load inst "reg(regs.regs(1)#1.sva)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 18613 -attr oid 759 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(1)#1.sva)}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "reg(regs.regs(1)#1.sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "reg(regs.regs(1)#1.sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "reg(regs.regs(1)#1.sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "reg(regs.regs(1)#1.sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "reg(regs.regs(1)#1.sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "reg(regs.regs(1)#1.sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "reg(regs.regs(1)#1.sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "reg(regs.regs(1)#1.sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "reg(regs.regs(1)#1.sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "reg(regs.regs(1)#1.sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "reg(regs.regs(1)#1.sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "reg(regs.regs(1)#1.sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "reg(regs.regs(1)#1.sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "reg(regs.regs(1)#1.sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "reg(regs.regs(1)#1.sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "reg(regs.regs(1)#1.sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "reg(regs.regs(1)#1.sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "reg(regs.regs(1)#1.sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "reg(regs.regs(1)#1.sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "reg(regs.regs(1)#1.sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "reg(regs.regs(1)#1.sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "reg(regs.regs(1)#1.sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "reg(regs.regs(1)#1.sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "reg(regs.regs(1)#1.sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "reg(regs.regs(1)#1.sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "reg(regs.regs(1)#1.sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "reg(regs.regs(1)#1.sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "reg(regs.regs(1)#1.sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "reg(regs.regs(1)#1.sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "reg(regs.regs(1)#1.sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(1)#1.sva)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(regs.regs(1)#1.sva)" {clk} -attr xrf 18614 -attr oid 760 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(1)#1.sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(1)#1.sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(1)#1.sva(0)} -pin  "reg(regs.regs(1)#1.sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(1)} -pin  "reg(regs.regs(1)#1.sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(2)} -pin  "reg(regs.regs(1)#1.sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(3)} -pin  "reg(regs.regs(1)#1.sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(4)} -pin  "reg(regs.regs(1)#1.sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(5)} -pin  "reg(regs.regs(1)#1.sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(6)} -pin  "reg(regs.regs(1)#1.sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(7)} -pin  "reg(regs.regs(1)#1.sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(8)} -pin  "reg(regs.regs(1)#1.sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(9)} -pin  "reg(regs.regs(1)#1.sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(10)} -pin  "reg(regs.regs(1)#1.sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(11)} -pin  "reg(regs.regs(1)#1.sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(12)} -pin  "reg(regs.regs(1)#1.sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(13)} -pin  "reg(regs.regs(1)#1.sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(14)} -pin  "reg(regs.regs(1)#1.sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(15)} -pin  "reg(regs.regs(1)#1.sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(16)} -pin  "reg(regs.regs(1)#1.sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(17)} -pin  "reg(regs.regs(1)#1.sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(18)} -pin  "reg(regs.regs(1)#1.sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(19)} -pin  "reg(regs.regs(1)#1.sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(20)} -pin  "reg(regs.regs(1)#1.sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(21)} -pin  "reg(regs.regs(1)#1.sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(22)} -pin  "reg(regs.regs(1)#1.sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(23)} -pin  "reg(regs.regs(1)#1.sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(24)} -pin  "reg(regs.regs(1)#1.sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(25)} -pin  "reg(regs.regs(1)#1.sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(26)} -pin  "reg(regs.regs(1)#1.sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(27)} -pin  "reg(regs.regs(1)#1.sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(28)} -pin  "reg(regs.regs(1)#1.sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load net {regs.regs(1)#1.sva(29)} -pin  "reg(regs.regs(1)#1.sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1)#1.sva}
+load inst "FRAME:mul#6" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 18615 -attr oid 761 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {intensity:slc(intensity#2.sg1)#9.itm#1(0)} -pin  "FRAME:mul#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1)#9.itm#1}
+load net {intensity:slc(intensity#2.sg1)#9.itm#1(1)} -pin  "FRAME:mul#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1)#9.itm#1}
+load net {PWR} -pin  "FRAME:mul#6" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#6" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#6" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#6" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#6" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#6" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#6" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#6" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#6" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#6.itm(0)} -pin  "FRAME:mul#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(1)} -pin  "FRAME:mul#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(2)} -pin  "FRAME:mul#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(3)} -pin  "FRAME:mul#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(4)} -pin  "FRAME:mul#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(5)} -pin  "FRAME:mul#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(6)} -pin  "FRAME:mul#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(7)} -pin  "FRAME:mul#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(8)} -pin  "FRAME:mul#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(9)} -pin  "FRAME:mul#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(10)} -pin  "FRAME:mul#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load inst "FRAME:mul#7" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 18616 -attr oid 762 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {intensity:slc(intensity#2.sg1)#11.itm#1(0)} -pin  "FRAME:mul#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1)#11.itm#1}
+load net {intensity:slc(intensity#2.sg1)#11.itm#1(1)} -pin  "FRAME:mul#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1)#11.itm#1}
+load net {intensity:slc(intensity#2.sg1)#11.itm#1(2)} -pin  "FRAME:mul#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1)#11.itm#1}
+load net {PWR} -pin  "FRAME:mul#7" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#7" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#7" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#7" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#7" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#7" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#7.itm(0)} -pin  "FRAME:mul#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(1)} -pin  "FRAME:mul#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(2)} -pin  "FRAME:mul#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(3)} -pin  "FRAME:mul#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(4)} -pin  "FRAME:mul#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(5)} -pin  "FRAME:mul#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(6)} -pin  "FRAME:mul#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(7)} -pin  "FRAME:mul#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(8)} -pin  "FRAME:mul#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load inst "FRAME:not#31" "not(1)" "INTERFACE" -attr xrf 18617 -attr oid 763 -attr @path {/sobel/sobel:core/FRAME:not#31} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#15.sva(5)} -pin  "FRAME:not#31" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#15.sva)#6.itm}
+load net {FRAME:not#31.itm} -pin  "FRAME:not#31" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#31.itm}
+load inst "FRAME:not#29" "not(3)" "INTERFACE" -attr xrf 18618 -attr oid 764 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#29} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#15.sva(3)} -pin  "FRAME:not#29" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#15.sva)#2.itm}
+load net {acc.imod#15.sva(4)} -pin  "FRAME:not#29" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#15.sva)#2.itm}
+load net {acc.imod#15.sva(5)} -pin  "FRAME:not#29" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#15.sva)#2.itm}
+load net {FRAME:not#29.itm(0)} -pin  "FRAME:not#29" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#29.itm}
+load net {FRAME:not#29.itm(1)} -pin  "FRAME:not#29" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#29.itm}
+load net {FRAME:not#29.itm(2)} -pin  "FRAME:not#29" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#29.itm}
+load inst "FRAME:not#28" "not(1)" "INTERFACE" -attr xrf 18619 -attr oid 765 -attr @path {/sobel/sobel:core/FRAME:not#28} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#15.sva(5)} -pin  "FRAME:not#28" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#15.sva)#3.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:not#28" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#28.itm}
+load inst "FRAME:acc#19" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 18620 -attr oid 766 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {PWR} -pin  "FRAME:acc#19" {A(0)} -attr @path {/sobel/sobel:core/conc#324.itm}
+load net {acc.imod#15.sva(0)} -pin  "FRAME:acc#19" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#324.itm}
+load net {acc.imod#15.sva(1)} -pin  "FRAME:acc#19" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#324.itm}
+load net {acc.imod#15.sva(2)} -pin  "FRAME:acc#19" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#324.itm}
+load net {PWR} -pin  "FRAME:acc#19" {A(4)} -attr @path {/sobel/sobel:core/conc#324.itm}
+load net {FRAME:not#28.itm} -pin  "FRAME:acc#19" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#26.itm}
+load net {FRAME:not#29.itm(0)} -pin  "FRAME:acc#19" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#26.itm}
+load net {FRAME:not#29.itm(1)} -pin  "FRAME:acc#19" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#26.itm}
+load net {FRAME:not#29.itm(2)} -pin  "FRAME:acc#19" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#26.itm}
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#19" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#19" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#19" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(3)} -pin  "FRAME:acc#19" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(4)} -pin  "FRAME:acc#19" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load inst "FRAME:not#40" "not(1)" "INTERFACE" -attr xrf 18621 -attr oid 767 -attr @path {/sobel/sobel:core/FRAME:not#40} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#19.itm(4)} -pin  "FRAME:not#40" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#3.itm}
+load net {FRAME:not#40.itm} -pin  "FRAME:not#40" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#40.itm}
+load inst "FRAME:acc#13" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 18622 -attr oid 768 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#40.itm} -pin  "FRAME:acc#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#323.itm}
+load net {PWR} -pin  "FRAME:acc#13" {A(1)} -attr @path {/sobel/sobel:core/conc#323.itm}
+load net {FRAME:not#31.itm} -pin  "FRAME:acc#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#323.itm}
+load net {acc.imod#15.sva(3)} -pin  "FRAME:acc#13" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#15.sva)#4.itm}
+load net {acc.imod#15.sva(4)} -pin  "FRAME:acc#13" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#15.sva)#4.itm}
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load inst "FRAME:not#30" "not(3)" "INTERFACE" -attr xrf 18623 -attr oid 769 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#30} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {intensity:slc(intensity#2.sg1).itm#1(3)} -pin  "FRAME:not#30" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity:slc(intensity#2.sg1).itm#1).itm}
+load net {intensity:slc(intensity#2.sg1).itm#1(4)} -pin  "FRAME:not#30" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity:slc(intensity#2.sg1).itm#1).itm}
+load net {intensity:slc(intensity#2.sg1).itm#1(5)} -pin  "FRAME:not#30" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity:slc(intensity#2.sg1).itm#1).itm}
+load net {FRAME:not#30.itm(0)} -pin  "FRAME:not#30" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#30.itm}
+load net {FRAME:not#30.itm(1)} -pin  "FRAME:not#30" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#30.itm}
+load net {FRAME:not#30.itm(2)} -pin  "FRAME:not#30" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#30.itm}
+load inst "FRAME:acc#14" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 18624 -attr oid 770 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:not#30.itm(0)} -pin  "FRAME:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#30.itm}
+load net {FRAME:not#30.itm(1)} -pin  "FRAME:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#30.itm}
+load net {FRAME:not#30.itm(2)} -pin  "FRAME:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#30.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(4)} -pin  "FRAME:acc#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load inst "FRAME:acc#15" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 18625 -attr oid 771 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#15" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(4)} -pin  "FRAME:acc#15" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {acc.imod#15.sva(5)} -pin  "FRAME:acc#15" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#325.itm}
+load net {PWR} -pin  "FRAME:acc#15" {B(1)} -attr @path {/sobel/sobel:core/conc#325.itm}
+load net {GND} -pin  "FRAME:acc#15" {B(2)} -attr @path {/sobel/sobel:core/conc#325.itm}
+load net {GND} -pin  "FRAME:acc#15" {B(3)} -attr @path {/sobel/sobel:core/conc#325.itm}
+load net {PWR} -pin  "FRAME:acc#15" {B(4)} -attr @path {/sobel/sobel:core/conc#325.itm}
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load inst "FRAME:acc#16" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 18626 -attr oid 772 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {intensity:slc(intensity#2.sg1).itm#1(0)} -pin  "FRAME:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1).itm#1}
+load net {intensity:slc(intensity#2.sg1).itm#1(1)} -pin  "FRAME:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1).itm#1}
+load net {intensity:slc(intensity#2.sg1).itm#1(2)} -pin  "FRAME:acc#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1).itm#1}
+load net {intensity:slc(intensity#2.sg1).itm#1(3)} -pin  "FRAME:acc#16" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1).itm#1}
+load net {intensity:slc(intensity#2.sg1).itm#1(4)} -pin  "FRAME:acc#16" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1).itm#1}
+load net {intensity:slc(intensity#2.sg1).itm#1(5)} -pin  "FRAME:acc#16" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/intensity:slc(intensity#2.sg1).itm#1}
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#16" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#16" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#16" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#16" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#16" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#16.itm(0)} -pin  "FRAME:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "FRAME:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "FRAME:acc#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "FRAME:acc#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:acc#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(5)} -pin  "FRAME:acc#16" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(6)} -pin  "FRAME:acc#16" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(7)} -pin  "FRAME:acc#16" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load inst "FRAME:acc#17" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 18627 -attr oid 773 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,10)"
+load net {FRAME:mul#7.itm(0)} -pin  "FRAME:acc#17" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(1)} -pin  "FRAME:acc#17" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(2)} -pin  "FRAME:acc#17" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(3)} -pin  "FRAME:acc#17" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(4)} -pin  "FRAME:acc#17" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(5)} -pin  "FRAME:acc#17" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(6)} -pin  "FRAME:acc#17" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(7)} -pin  "FRAME:acc#17" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:mul#7.itm(8)} -pin  "FRAME:acc#17" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#7.itm}
+load net {FRAME:acc#16.itm(0)} -pin  "FRAME:acc#17" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "FRAME:acc#17" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "FRAME:acc#17" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "FRAME:acc#17" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:acc#17" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(5)} -pin  "FRAME:acc#17" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(6)} -pin  "FRAME:acc#17" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(7)} -pin  "FRAME:acc#17" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:acc#17" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:acc#17" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(4)} -pin  "FRAME:acc#17" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(5)} -pin  "FRAME:acc#17" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(6)} -pin  "FRAME:acc#17" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(7)} -pin  "FRAME:acc#17" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(8)} -pin  "FRAME:acc#17" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(9)} -pin  "FRAME:acc#17" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load inst "FRAME:acc#18" "add(11,0,10,1,12)" "INTERFACE" -attr xrf 18628 -attr oid 774 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12)"
+load net {FRAME:mul#6.itm(0)} -pin  "FRAME:acc#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(1)} -pin  "FRAME:acc#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(2)} -pin  "FRAME:acc#18" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(3)} -pin  "FRAME:acc#18" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(4)} -pin  "FRAME:acc#18" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(5)} -pin  "FRAME:acc#18" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(6)} -pin  "FRAME:acc#18" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(7)} -pin  "FRAME:acc#18" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(8)} -pin  "FRAME:acc#18" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(9)} -pin  "FRAME:acc#18" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:mul#6.itm(10)} -pin  "FRAME:acc#18" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#6.itm}
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#18" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#18" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:acc#18" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:acc#18" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(4)} -pin  "FRAME:acc#18" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(5)} -pin  "FRAME:acc#18" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(6)} -pin  "FRAME:acc#18" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(7)} -pin  "FRAME:acc#18" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(8)} -pin  "FRAME:acc#18" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(9)} -pin  "FRAME:acc#18" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#18.itm(0)} -pin  "FRAME:acc#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(1)} -pin  "FRAME:acc#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(2)} -pin  "FRAME:acc#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(3)} -pin  "FRAME:acc#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(4)} -pin  "FRAME:acc#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
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+load net {FRAME:acc#18.itm(6)} -pin  "FRAME:acc#18" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(7)} -pin  "FRAME:acc#18" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(8)} -pin  "FRAME:acc#18" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(9)} -pin  "FRAME:acc#18" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(10)} -pin  "FRAME:acc#18" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(11)} -pin  "FRAME:acc#18" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load inst "FRAME:acc#5" "add(12,-1,11,0,12)" "INTERFACE" -attr xrf 18629 -attr oid 775 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,12,1,14)"
+load net {FRAME:acc#18.itm(0)} -pin  "FRAME:acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(1)} -pin  "FRAME:acc#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(2)} -pin  "FRAME:acc#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(3)} -pin  "FRAME:acc#5" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(4)} -pin  "FRAME:acc#5" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(5)} -pin  "FRAME:acc#5" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(6)} -pin  "FRAME:acc#5" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(7)} -pin  "FRAME:acc#5" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(8)} -pin  "FRAME:acc#5" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(9)} -pin  "FRAME:acc#5" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(10)} -pin  "FRAME:acc#5" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(11)} -pin  "FRAME:acc#5" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {intensity:slc(intensity#2.sg1)#12.itm#1} -pin  "FRAME:acc#5" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {GND} -pin  "FRAME:acc#5" {B(1)} -attr @path {/sobel/sobel:core/exs.itm}
+load net {intensity:slc(intensity#2.sg1)#12.itm#1} -pin  "FRAME:acc#5" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {intensity:slc(intensity#2.sg1)#12.itm#1} -pin  "FRAME:acc#5" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {intensity:slc(intensity#2.sg1)#12.itm#1} -pin  "FRAME:acc#5" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {GND} -pin  "FRAME:acc#5" {B(5)} -attr @path {/sobel/sobel:core/exs.itm}
+load net {GND} -pin  "FRAME:acc#5" {B(6)} -attr @path {/sobel/sobel:core/exs.itm}
+load net {GND} -pin  "FRAME:acc#5" {B(7)} -attr @path {/sobel/sobel:core/exs.itm}
+load net {intensity:slc(intensity#2.sg1)#12.itm#1} -pin  "FRAME:acc#5" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {intensity:slc(intensity#2.sg1)#12.itm#1} -pin  "FRAME:acc#5" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {intensity:slc(intensity#2.sg1)#12.itm#1} -pin  "FRAME:acc#5" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:acc#5.psp.sva(0)} -pin  "FRAME:acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(1)} -pin  "FRAME:acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(2)} -pin  "FRAME:acc#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(3)} -pin  "FRAME:acc#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(4)} -pin  "FRAME:acc#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(5)} -pin  "FRAME:acc#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(6)} -pin  "FRAME:acc#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(7)} -pin  "FRAME:acc#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(8)} -pin  "FRAME:acc#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(9)} -pin  "FRAME:acc#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(10)} -pin  "FRAME:acc#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load net {FRAME:acc#5.psp.sva(11)} -pin  "FRAME:acc#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.psp.sva}
+load inst "acc#18" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 18630 -attr oid 776 -attr vt d -attr @path {/sobel/sobel:core/acc#18} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {FRAME:acc#12.itm#1(0)} -pin  "acc#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm#1}
+load net {FRAME:acc#12.itm#1(1)} -pin  "acc#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm#1}
+load net {FRAME:acc#12.itm#1(2)} -pin  "acc#18" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm#1}
+load net {FRAME:acc#12.itm#1(3)} -pin  "acc#18" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm#1}
+load net {FRAME:acc#12.itm#1(4)} -pin  "acc#18" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm#1}
+load net {FRAME:acc#12.itm#1(5)} -pin  "acc#18" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm#1}
+load net {PWR} -pin  "acc#18" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#18" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#18" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#18" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#18" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#18" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#15.sva(0)} -pin  "acc#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#15.sva}
+load net {acc.imod#15.sva(1)} -pin  "acc#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#15.sva}
+load net {acc.imod#15.sva(2)} -pin  "acc#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#15.sva}
+load net {acc.imod#15.sva(3)} -pin  "acc#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#15.sva}
+load net {acc.imod#15.sva(4)} -pin  "acc#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#15.sva}
+load net {acc.imod#15.sva(5)} -pin  "acc#18" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#15.sva}
+load inst "ACC1:acc#267" "add(11,0,10,1,12)" "INTERFACE" -attr xrf 18631 -attr oid 777 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12)"
+load net {ACC1-2:slc(acc.idiv)#106.itm#1} -pin  "ACC1:acc#267" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#275.itm}
+load net {ACC1-2:slc(acc.idiv)#106.itm#1} -pin  "ACC1:acc#267" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#275.itm}
+load net {ACC1:slc(acc.imod#17)#8.itm#1} -pin  "ACC1:acc#267" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#275.itm}
+load net {ACC1:mul#99.itm#1(0)} -pin  "ACC1:acc#267" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#275.itm}
+load net {ACC1:mul#99.itm#1(1)} -pin  "ACC1:acc#267" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#275.itm}
+load net {ACC1:mul#99.itm#1(2)} -pin  "ACC1:acc#267" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#275.itm}
+load net {ACC1:mul#99.itm#1(3)} -pin  "ACC1:acc#267" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#275.itm}
+load net {ACC1:mul#99.itm#1(4)} -pin  "ACC1:acc#267" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#275.itm}
+load net {ACC1:mul#99.itm#1(5)} -pin  "ACC1:acc#267" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#275.itm}
+load net {ACC1:mul#99.itm#1(6)} -pin  "ACC1:acc#267" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#275.itm}
+load net {ACC1:mul#99.itm#1(7)} -pin  "ACC1:acc#267" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#275.itm}
+load net {ACC1:acc#264.itm#1(0)} -pin  "ACC1:acc#267" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(1)} -pin  "ACC1:acc#267" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(2)} -pin  "ACC1:acc#267" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(3)} -pin  "ACC1:acc#267" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(4)} -pin  "ACC1:acc#267" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(5)} -pin  "ACC1:acc#267" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(6)} -pin  "ACC1:acc#267" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(7)} -pin  "ACC1:acc#267" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(8)} -pin  "ACC1:acc#267" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#264.itm#1(9)} -pin  "ACC1:acc#267" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm#1}
+load net {ACC1:acc#267.itm(0)} -pin  "ACC1:acc#267" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(1)} -pin  "ACC1:acc#267" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(2)} -pin  "ACC1:acc#267" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(3)} -pin  "ACC1:acc#267" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(4)} -pin  "ACC1:acc#267" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(5)} -pin  "ACC1:acc#267" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(6)} -pin  "ACC1:acc#267" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(7)} -pin  "ACC1:acc#267" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(8)} -pin  "ACC1:acc#267" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(9)} -pin  "ACC1:acc#267" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(10)} -pin  "ACC1:acc#267" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(11)} -pin  "ACC1:acc#267" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load inst "ACC1:acc#270" "add(12,1,12,0,14)" "INTERFACE" -attr xrf 18632 -attr oid 778 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,12,1,14)"
+load net {ACC1:acc#267.itm(0)} -pin  "ACC1:acc#270" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(1)} -pin  "ACC1:acc#270" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(2)} -pin  "ACC1:acc#270" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(3)} -pin  "ACC1:acc#270" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(4)} -pin  "ACC1:acc#270" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(5)} -pin  "ACC1:acc#270" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(6)} -pin  "ACC1:acc#270" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(7)} -pin  "ACC1:acc#270" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(8)} -pin  "ACC1:acc#270" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(9)} -pin  "ACC1:acc#270" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(10)} -pin  "ACC1:acc#270" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(11)} -pin  "ACC1:acc#270" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:mul#90.itm#1(0)} -pin  "ACC1:acc#270" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(1)} -pin  "ACC1:acc#270" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(2)} -pin  "ACC1:acc#270" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(3)} -pin  "ACC1:acc#270" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(4)} -pin  "ACC1:acc#270" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(5)} -pin  "ACC1:acc#270" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(6)} -pin  "ACC1:acc#270" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(7)} -pin  "ACC1:acc#270" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(8)} -pin  "ACC1:acc#270" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(9)} -pin  "ACC1:acc#270" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(10)} -pin  "ACC1:acc#270" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:mul#90.itm#1(11)} -pin  "ACC1:acc#270" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#90.itm#1}
+load net {ACC1:acc#270.itm(0)} -pin  "ACC1:acc#270" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(1)} -pin  "ACC1:acc#270" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(2)} -pin  "ACC1:acc#270" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(3)} -pin  "ACC1:acc#270" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(4)} -pin  "ACC1:acc#270" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(5)} -pin  "ACC1:acc#270" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(6)} -pin  "ACC1:acc#270" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(7)} -pin  "ACC1:acc#270" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(8)} -pin  "ACC1:acc#270" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(9)} -pin  "ACC1:acc#270" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(10)} -pin  "ACC1:acc#270" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(11)} -pin  "ACC1:acc#270" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(12)} -pin  "ACC1:acc#270" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(13)} -pin  "ACC1:acc#270" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load inst "ACC1:acc#274" "add(14,1,14,0,15)" "INTERFACE" -attr xrf 18633 -attr oid 779 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274} -attr area 15.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(14,0,14,1,15)"
+load net {ACC1:acc#270.itm(0)} -pin  "ACC1:acc#274" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(1)} -pin  "ACC1:acc#274" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(2)} -pin  "ACC1:acc#274" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(3)} -pin  "ACC1:acc#274" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(4)} -pin  "ACC1:acc#274" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(5)} -pin  "ACC1:acc#274" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(6)} -pin  "ACC1:acc#274" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(7)} -pin  "ACC1:acc#274" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(8)} -pin  "ACC1:acc#274" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(9)} -pin  "ACC1:acc#274" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(10)} -pin  "ACC1:acc#274" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(11)} -pin  "ACC1:acc#274" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(12)} -pin  "ACC1:acc#274" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(13)} -pin  "ACC1:acc#274" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:mul#91.itm#1(0)} -pin  "ACC1:acc#274" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(1)} -pin  "ACC1:acc#274" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(2)} -pin  "ACC1:acc#274" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(3)} -pin  "ACC1:acc#274" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(4)} -pin  "ACC1:acc#274" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(5)} -pin  "ACC1:acc#274" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(6)} -pin  "ACC1:acc#274" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(7)} -pin  "ACC1:acc#274" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(8)} -pin  "ACC1:acc#274" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(9)} -pin  "ACC1:acc#274" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(10)} -pin  "ACC1:acc#274" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(11)} -pin  "ACC1:acc#274" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(12)} -pin  "ACC1:acc#274" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:mul#91.itm#1(13)} -pin  "ACC1:acc#274" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#91.itm#1}
+load net {ACC1:acc#274.itm(0)} -pin  "ACC1:acc#274" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(1)} -pin  "ACC1:acc#274" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(2)} -pin  "ACC1:acc#274" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(3)} -pin  "ACC1:acc#274" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(4)} -pin  "ACC1:acc#274" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(5)} -pin  "ACC1:acc#274" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(6)} -pin  "ACC1:acc#274" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(7)} -pin  "ACC1:acc#274" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(8)} -pin  "ACC1:acc#274" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(9)} -pin  "ACC1:acc#274" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(10)} -pin  "ACC1:acc#274" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(11)} -pin  "ACC1:acc#274" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(12)} -pin  "ACC1:acc#274" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(13)} -pin  "ACC1:acc#274" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(14)} -pin  "ACC1:acc#274" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load inst "ACC1:acc#277" "add(16,-1,15,1,16)" "INTERFACE" -attr xrf 18634 -attr oid 780 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,15,1,16)"
+load net {ACC1-2:slc(acc.idiv)#131.itm#1} -pin  "ACC1:acc#277" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {ACC1-2:slc(acc.idiv)#131.itm#1} -pin  "ACC1:acc#277" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {GND} -pin  "ACC1:acc#277" {A(2)} -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {mul#1.itm#1(0)} -pin  "ACC1:acc#277" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {mul#1.itm#1(1)} -pin  "ACC1:acc#277" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {mul#1.itm#1(2)} -pin  "ACC1:acc#277" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {mul#1.itm#1(3)} -pin  "ACC1:acc#277" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {mul#1.itm#1(4)} -pin  "ACC1:acc#277" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {mul#1.itm#1(5)} -pin  "ACC1:acc#277" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {mul#1.itm#1(6)} -pin  "ACC1:acc#277" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {mul#1.itm#1(7)} -pin  "ACC1:acc#277" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {mul#1.itm#1(8)} -pin  "ACC1:acc#277" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {mul#1.itm#1(9)} -pin  "ACC1:acc#277" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {mul#1.itm#1(10)} -pin  "ACC1:acc#277" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {mul#1.itm#1(11)} -pin  "ACC1:acc#277" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {mul#1.itm#1(12)} -pin  "ACC1:acc#277" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/conc#328.itm}
+load net {ACC1:acc#274.itm(0)} -pin  "ACC1:acc#277" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(1)} -pin  "ACC1:acc#277" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(2)} -pin  "ACC1:acc#277" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(3)} -pin  "ACC1:acc#277" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(4)} -pin  "ACC1:acc#277" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(5)} -pin  "ACC1:acc#277" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(6)} -pin  "ACC1:acc#277" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(7)} -pin  "ACC1:acc#277" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(8)} -pin  "ACC1:acc#277" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(9)} -pin  "ACC1:acc#277" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(10)} -pin  "ACC1:acc#277" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(11)} -pin  "ACC1:acc#277" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(12)} -pin  "ACC1:acc#277" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(13)} -pin  "ACC1:acc#277" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(14)} -pin  "ACC1:acc#277" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#277.itm(0)} -pin  "ACC1:acc#277" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(1)} -pin  "ACC1:acc#277" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(2)} -pin  "ACC1:acc#277" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(3)} -pin  "ACC1:acc#277" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(4)} -pin  "ACC1:acc#277" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(5)} -pin  "ACC1:acc#277" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(6)} -pin  "ACC1:acc#277" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(7)} -pin  "ACC1:acc#277" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(8)} -pin  "ACC1:acc#277" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(9)} -pin  "ACC1:acc#277" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(10)} -pin  "ACC1:acc#277" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(11)} -pin  "ACC1:acc#277" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(12)} -pin  "ACC1:acc#277" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(13)} -pin  "ACC1:acc#277" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(14)} -pin  "ACC1:acc#277" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(15)} -pin  "ACC1:acc#277" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load inst "ACC1:acc#256" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 18635 -attr oid 781 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:acc#252.itm#1(0)} -pin  "ACC1:acc#256" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#252.itm#1}
+load net {ACC1:acc#252.itm#1(1)} -pin  "ACC1:acc#256" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#252.itm#1}
+load net {ACC1:acc#252.itm#1(2)} -pin  "ACC1:acc#256" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#252.itm#1}
+load net {ACC1:acc#252.itm#1(3)} -pin  "ACC1:acc#256" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#252.itm#1}
+load net {ACC1:acc#252.itm#1(4)} -pin  "ACC1:acc#256" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#252.itm#1}
+load net {ACC1:acc#252.itm#1(5)} -pin  "ACC1:acc#256" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#252.itm#1}
+load net {ACC1:acc#251.itm#1(0)} -pin  "ACC1:acc#256" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm#1}
+load net {ACC1:acc#251.itm#1(1)} -pin  "ACC1:acc#256" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm#1}
+load net {ACC1:acc#251.itm#1(2)} -pin  "ACC1:acc#256" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm#1}
+load net {ACC1:acc#251.itm#1(3)} -pin  "ACC1:acc#256" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm#1}
+load net {ACC1:acc#251.itm#1(4)} -pin  "ACC1:acc#256" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm#1}
+load net {ACC1:acc#251.itm#1(5)} -pin  "ACC1:acc#256" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm#1}
+load net {ACC1:acc#256.itm(0)} -pin  "ACC1:acc#256" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(1)} -pin  "ACC1:acc#256" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(2)} -pin  "ACC1:acc#256" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(3)} -pin  "ACC1:acc#256" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(4)} -pin  "ACC1:acc#256" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(5)} -pin  "ACC1:acc#256" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(6)} -pin  "ACC1:acc#256" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load inst "ACC1:acc#260" "add(7,0,7,0,8)" "INTERFACE" -attr xrf 18636 -attr oid 782 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260} -attr area 8.267306 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,0,8)"
+load net {ACC1:acc#256.itm(0)} -pin  "ACC1:acc#260" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(1)} -pin  "ACC1:acc#260" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(2)} -pin  "ACC1:acc#260" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(3)} -pin  "ACC1:acc#260" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(4)} -pin  "ACC1:acc#260" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(5)} -pin  "ACC1:acc#260" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(6)} -pin  "ACC1:acc#260" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#255.itm#1(0)} -pin  "ACC1:acc#260" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:acc#255.itm#1(1)} -pin  "ACC1:acc#260" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:acc#255.itm#1(2)} -pin  "ACC1:acc#260" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:acc#255.itm#1(3)} -pin  "ACC1:acc#260" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:acc#255.itm#1(4)} -pin  "ACC1:acc#260" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:acc#255.itm#1(5)} -pin  "ACC1:acc#260" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:acc#255.itm#1(6)} -pin  "ACC1:acc#260" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm#1}
+load net {ACC1:acc#260.itm(0)} -pin  "ACC1:acc#260" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(1)} -pin  "ACC1:acc#260" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(2)} -pin  "ACC1:acc#260" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(3)} -pin  "ACC1:acc#260" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(4)} -pin  "ACC1:acc#260" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(5)} -pin  "ACC1:acc#260" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(6)} -pin  "ACC1:acc#260" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(7)} -pin  "ACC1:acc#260" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load inst "ACC1:acc#263" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 18637 -attr oid 783 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,9,1,10)"
+load net {ACC1-2:slc(acc.idiv)#132.itm#1} -pin  "ACC1:acc#263" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#274.itm}
+load net {ACC1-2:slc(acc.idiv)#132.itm#1} -pin  "ACC1:acc#263" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#274.itm}
+load net {ACC1:slc(acc.idiv#3)#36.itm#1} -pin  "ACC1:acc#263" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#274.itm}
+load net {ACC1:mul#98.itm#1(0)} -pin  "ACC1:acc#263" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#274.itm}
+load net {ACC1:mul#98.itm#1(1)} -pin  "ACC1:acc#263" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#274.itm}
+load net {ACC1:mul#98.itm#1(2)} -pin  "ACC1:acc#263" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#274.itm}
+load net {ACC1:mul#98.itm#1(3)} -pin  "ACC1:acc#263" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#274.itm}
+load net {ACC1:mul#98.itm#1(4)} -pin  "ACC1:acc#263" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#274.itm}
+load net {ACC1:mul#98.itm#1(5)} -pin  "ACC1:acc#263" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#274.itm}
+load net {ACC1:acc#260.itm(0)} -pin  "ACC1:acc#263" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(1)} -pin  "ACC1:acc#263" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(2)} -pin  "ACC1:acc#263" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(3)} -pin  "ACC1:acc#263" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(4)} -pin  "ACC1:acc#263" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(5)} -pin  "ACC1:acc#263" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(6)} -pin  "ACC1:acc#263" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(7)} -pin  "ACC1:acc#263" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#263.itm(0)} -pin  "ACC1:acc#263" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(1)} -pin  "ACC1:acc#263" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(2)} -pin  "ACC1:acc#263" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(3)} -pin  "ACC1:acc#263" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(4)} -pin  "ACC1:acc#263" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(5)} -pin  "ACC1:acc#263" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(6)} -pin  "ACC1:acc#263" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(7)} -pin  "ACC1:acc#263" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(8)} -pin  "ACC1:acc#263" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(9)} -pin  "ACC1:acc#263" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load inst "ACC1:acc#266" "add(10,0,10,0,11)" "INTERFACE" -attr xrf 18638 -attr oid 784 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266} -attr area 11.241230 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,11)"
+load net {ACC1:acc#263.itm(0)} -pin  "ACC1:acc#266" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(1)} -pin  "ACC1:acc#266" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(2)} -pin  "ACC1:acc#266" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(3)} -pin  "ACC1:acc#266" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(4)} -pin  "ACC1:acc#266" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(5)} -pin  "ACC1:acc#266" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(6)} -pin  "ACC1:acc#266" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(7)} -pin  "ACC1:acc#266" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(8)} -pin  "ACC1:acc#266" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(9)} -pin  "ACC1:acc#266" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:mul#89.itm#1(0)} -pin  "ACC1:acc#266" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(1)} -pin  "ACC1:acc#266" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(2)} -pin  "ACC1:acc#266" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(3)} -pin  "ACC1:acc#266" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(4)} -pin  "ACC1:acc#266" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(5)} -pin  "ACC1:acc#266" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(6)} -pin  "ACC1:acc#266" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(7)} -pin  "ACC1:acc#266" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(8)} -pin  "ACC1:acc#266" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:mul#89.itm#1(9)} -pin  "ACC1:acc#266" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#89.itm#1}
+load net {ACC1:acc#266.itm(0)} -pin  "ACC1:acc#266" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(1)} -pin  "ACC1:acc#266" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(2)} -pin  "ACC1:acc#266" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(3)} -pin  "ACC1:acc#266" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(4)} -pin  "ACC1:acc#266" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(5)} -pin  "ACC1:acc#266" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(6)} -pin  "ACC1:acc#266" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(7)} -pin  "ACC1:acc#266" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(8)} -pin  "ACC1:acc#266" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(9)} -pin  "ACC1:acc#266" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(10)} -pin  "ACC1:acc#266" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load inst "ACC1:acc#269" "add(12,-1,11,0,12)" "INTERFACE" -attr xrf 18639 -attr oid 785 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,12,1,14)"
+load net {ACC1-3:slc(acc.idiv)#131.itm#1} -pin  "ACC1:acc#269" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#330.itm}
+load net {ACC1-3:slc(acc.idiv)#131.itm#1} -pin  "ACC1:acc#269" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#330.itm}
+load net {GND} -pin  "ACC1:acc#269" {A(2)} -attr @path {/sobel/sobel:core/conc#330.itm}
+load net {ACC1:slc(acc.idiv)#91.itm#1} -pin  "ACC1:acc#269" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#330.itm}
+load net {ACC1:mul#103.itm#1(0)} -pin  "ACC1:acc#269" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#330.itm}
+load net {ACC1:mul#103.itm#1(1)} -pin  "ACC1:acc#269" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#330.itm}
+load net {ACC1:mul#103.itm#1(2)} -pin  "ACC1:acc#269" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#330.itm}
+load net {ACC1:mul#103.itm#1(3)} -pin  "ACC1:acc#269" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#330.itm}
+load net {ACC1:mul#103.itm#1(4)} -pin  "ACC1:acc#269" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#330.itm}
+load net {ACC1:mul#103.itm#1(5)} -pin  "ACC1:acc#269" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#330.itm}
+load net {ACC1:mul#103.itm#1(6)} -pin  "ACC1:acc#269" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#330.itm}
+load net {ACC1:mul#103.itm#1(7)} -pin  "ACC1:acc#269" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#330.itm}
+load net {ACC1:acc#266.itm(0)} -pin  "ACC1:acc#269" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(1)} -pin  "ACC1:acc#269" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(2)} -pin  "ACC1:acc#269" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(3)} -pin  "ACC1:acc#269" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(4)} -pin  "ACC1:acc#269" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(5)} -pin  "ACC1:acc#269" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(6)} -pin  "ACC1:acc#269" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(7)} -pin  "ACC1:acc#269" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(8)} -pin  "ACC1:acc#269" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(9)} -pin  "ACC1:acc#269" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(10)} -pin  "ACC1:acc#269" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#269.itm(0)} -pin  "ACC1:acc#269" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(1)} -pin  "ACC1:acc#269" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(2)} -pin  "ACC1:acc#269" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(3)} -pin  "ACC1:acc#269" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(4)} -pin  "ACC1:acc#269" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(5)} -pin  "ACC1:acc#269" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(6)} -pin  "ACC1:acc#269" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(7)} -pin  "ACC1:acc#269" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(8)} -pin  "ACC1:acc#269" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(9)} -pin  "ACC1:acc#269" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(10)} -pin  "ACC1:acc#269" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(11)} -pin  "ACC1:acc#269" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load inst "ACC1:acc#271" "add(12,0,12,0,13)" "INTERFACE" -attr xrf 18640 -attr oid 786 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271} -attr area 13.223846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,12,0,13)"
+load net {ACC1:acc#269.itm(0)} -pin  "ACC1:acc#271" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(1)} -pin  "ACC1:acc#271" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(2)} -pin  "ACC1:acc#271" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(3)} -pin  "ACC1:acc#271" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(4)} -pin  "ACC1:acc#271" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(5)} -pin  "ACC1:acc#271" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(6)} -pin  "ACC1:acc#271" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(7)} -pin  "ACC1:acc#271" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(8)} -pin  "ACC1:acc#271" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(9)} -pin  "ACC1:acc#271" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(10)} -pin  "ACC1:acc#271" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(11)} -pin  "ACC1:acc#271" {A(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#268.itm#1(0)} -pin  "ACC1:acc#271" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(1)} -pin  "ACC1:acc#271" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(2)} -pin  "ACC1:acc#271" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(3)} -pin  "ACC1:acc#271" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(4)} -pin  "ACC1:acc#271" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(5)} -pin  "ACC1:acc#271" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(6)} -pin  "ACC1:acc#271" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(7)} -pin  "ACC1:acc#271" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(8)} -pin  "ACC1:acc#271" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(9)} -pin  "ACC1:acc#271" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(10)} -pin  "ACC1:acc#271" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#268.itm#1(11)} -pin  "ACC1:acc#271" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm#1}
+load net {ACC1:acc#271.itm(0)} -pin  "ACC1:acc#271" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(1)} -pin  "ACC1:acc#271" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(2)} -pin  "ACC1:acc#271" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(3)} -pin  "ACC1:acc#271" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(4)} -pin  "ACC1:acc#271" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(5)} -pin  "ACC1:acc#271" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(6)} -pin  "ACC1:acc#271" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(7)} -pin  "ACC1:acc#271" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(8)} -pin  "ACC1:acc#271" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(9)} -pin  "ACC1:acc#271" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(10)} -pin  "ACC1:acc#271" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(11)} -pin  "ACC1:acc#271" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(12)} -pin  "ACC1:acc#271" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load inst "ACC1:acc#273" "add(14,0,13,0,15)" "INTERFACE" -attr xrf 18641 -attr oid 787 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273} -attr area 15.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(14,0,14,1,15)"
+load net {ACC1-3:slc(acc.idiv)#132.itm#1} -pin  "ACC1:acc#273" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1-3:slc(acc.idiv)#132.itm#1} -pin  "ACC1:acc#273" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {GND} -pin  "ACC1:acc#273" {A(2)} -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1:slc(acc.idiv#2)#90.itm#1} -pin  "ACC1:acc#273" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1:mul#104.itm#1(0)} -pin  "ACC1:acc#273" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1:mul#104.itm#1(1)} -pin  "ACC1:acc#273" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1:mul#104.itm#1(2)} -pin  "ACC1:acc#273" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1:mul#104.itm#1(3)} -pin  "ACC1:acc#273" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1:mul#104.itm#1(4)} -pin  "ACC1:acc#273" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1:mul#104.itm#1(5)} -pin  "ACC1:acc#273" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1:mul#104.itm#1(6)} -pin  "ACC1:acc#273" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1:mul#104.itm#1(7)} -pin  "ACC1:acc#273" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1:mul#104.itm#1(8)} -pin  "ACC1:acc#273" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1:mul#104.itm#1(9)} -pin  "ACC1:acc#273" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/conc#329.itm}
+load net {ACC1:acc#271.itm(0)} -pin  "ACC1:acc#273" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(1)} -pin  "ACC1:acc#273" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(2)} -pin  "ACC1:acc#273" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(3)} -pin  "ACC1:acc#273" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(4)} -pin  "ACC1:acc#273" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(5)} -pin  "ACC1:acc#273" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(6)} -pin  "ACC1:acc#273" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(7)} -pin  "ACC1:acc#273" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(8)} -pin  "ACC1:acc#273" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(9)} -pin  "ACC1:acc#273" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(10)} -pin  "ACC1:acc#273" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(11)} -pin  "ACC1:acc#273" {B(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(12)} -pin  "ACC1:acc#273" {B(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#273.itm(0)} -pin  "ACC1:acc#273" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(1)} -pin  "ACC1:acc#273" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(2)} -pin  "ACC1:acc#273" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(3)} -pin  "ACC1:acc#273" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(4)} -pin  "ACC1:acc#273" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(5)} -pin  "ACC1:acc#273" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(6)} -pin  "ACC1:acc#273" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(7)} -pin  "ACC1:acc#273" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(8)} -pin  "ACC1:acc#273" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(9)} -pin  "ACC1:acc#273" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(10)} -pin  "ACC1:acc#273" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(11)} -pin  "ACC1:acc#273" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(12)} -pin  "ACC1:acc#273" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(13)} -pin  "ACC1:acc#273" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(14)} -pin  "ACC1:acc#273" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load inst "ACC1:acc#276" "add(15,0,15,0,16)" "INTERFACE" -attr xrf 18642 -attr oid 788 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276} -attr area 16.197770 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,15,0,16)"
+load net {ACC1:acc#273.itm(0)} -pin  "ACC1:acc#276" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(1)} -pin  "ACC1:acc#276" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(2)} -pin  "ACC1:acc#276" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(3)} -pin  "ACC1:acc#276" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(4)} -pin  "ACC1:acc#276" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(5)} -pin  "ACC1:acc#276" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(6)} -pin  "ACC1:acc#276" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(7)} -pin  "ACC1:acc#276" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(8)} -pin  "ACC1:acc#276" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(9)} -pin  "ACC1:acc#276" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(10)} -pin  "ACC1:acc#276" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(11)} -pin  "ACC1:acc#276" {A(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(12)} -pin  "ACC1:acc#276" {A(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(13)} -pin  "ACC1:acc#276" {A(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(14)} -pin  "ACC1:acc#276" {A(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:slc(acc.imod)#28.itm#1} -pin  "ACC1:acc#276" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(0)} -pin  "ACC1:acc#276" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(1)} -pin  "ACC1:acc#276" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(2)} -pin  "ACC1:acc#276" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(3)} -pin  "ACC1:acc#276" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(4)} -pin  "ACC1:acc#276" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(5)} -pin  "ACC1:acc#276" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(6)} -pin  "ACC1:acc#276" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(7)} -pin  "ACC1:acc#276" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(8)} -pin  "ACC1:acc#276" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(9)} -pin  "ACC1:acc#276" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(10)} -pin  "ACC1:acc#276" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(11)} -pin  "ACC1:acc#276" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(12)} -pin  "ACC1:acc#276" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:mul#96.itm#1(13)} -pin  "ACC1:acc#276" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#254.itm}
+load net {ACC1:acc#276.itm(0)} -pin  "ACC1:acc#276" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(1)} -pin  "ACC1:acc#276" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(2)} -pin  "ACC1:acc#276" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(3)} -pin  "ACC1:acc#276" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(4)} -pin  "ACC1:acc#276" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(5)} -pin  "ACC1:acc#276" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(6)} -pin  "ACC1:acc#276" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(7)} -pin  "ACC1:acc#276" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(8)} -pin  "ACC1:acc#276" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(9)} -pin  "ACC1:acc#276" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(10)} -pin  "ACC1:acc#276" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(11)} -pin  "ACC1:acc#276" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(12)} -pin  "ACC1:acc#276" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(13)} -pin  "ACC1:acc#276" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(14)} -pin  "ACC1:acc#276" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(15)} -pin  "ACC1:acc#276" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load inst "ACC1:acc#280" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 18643 -attr oid 789 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,17)"
+load net {ACC1:acc#277.itm(0)} -pin  "ACC1:acc#280" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(1)} -pin  "ACC1:acc#280" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(2)} -pin  "ACC1:acc#280" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(3)} -pin  "ACC1:acc#280" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(4)} -pin  "ACC1:acc#280" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(5)} -pin  "ACC1:acc#280" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(6)} -pin  "ACC1:acc#280" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(7)} -pin  "ACC1:acc#280" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(8)} -pin  "ACC1:acc#280" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(9)} -pin  "ACC1:acc#280" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(10)} -pin  "ACC1:acc#280" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(11)} -pin  "ACC1:acc#280" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(12)} -pin  "ACC1:acc#280" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(13)} -pin  "ACC1:acc#280" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(14)} -pin  "ACC1:acc#280" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#277.itm(15)} -pin  "ACC1:acc#280" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.itm}
+load net {ACC1:acc#276.itm(0)} -pin  "ACC1:acc#280" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(1)} -pin  "ACC1:acc#280" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(2)} -pin  "ACC1:acc#280" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(3)} -pin  "ACC1:acc#280" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(4)} -pin  "ACC1:acc#280" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(5)} -pin  "ACC1:acc#280" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(6)} -pin  "ACC1:acc#280" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(7)} -pin  "ACC1:acc#280" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(8)} -pin  "ACC1:acc#280" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(9)} -pin  "ACC1:acc#280" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(10)} -pin  "ACC1:acc#280" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(11)} -pin  "ACC1:acc#280" {B(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(12)} -pin  "ACC1:acc#280" {B(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(13)} -pin  "ACC1:acc#280" {B(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(14)} -pin  "ACC1:acc#280" {B(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#276.itm(15)} -pin  "ACC1:acc#280" {B(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#276.itm}
+load net {ACC1:acc#280.itm(0)} -pin  "ACC1:acc#280" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(1)} -pin  "ACC1:acc#280" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(2)} -pin  "ACC1:acc#280" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(3)} -pin  "ACC1:acc#280" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(4)} -pin  "ACC1:acc#280" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(5)} -pin  "ACC1:acc#280" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(6)} -pin  "ACC1:acc#280" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(7)} -pin  "ACC1:acc#280" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(8)} -pin  "ACC1:acc#280" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(9)} -pin  "ACC1:acc#280" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(10)} -pin  "ACC1:acc#280" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(11)} -pin  "ACC1:acc#280" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(12)} -pin  "ACC1:acc#280" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(13)} -pin  "ACC1:acc#280" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(14)} -pin  "ACC1:acc#280" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(15)} -pin  "ACC1:acc#280" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load inst "ACC1:acc" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 18644 -attr oid 790 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,17)"
+load net {ACC1:acc#281.itm#1(0)} -pin  "ACC1:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(1)} -pin  "ACC1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(2)} -pin  "ACC1:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(3)} -pin  "ACC1:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(4)} -pin  "ACC1:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(5)} -pin  "ACC1:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(6)} -pin  "ACC1:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(7)} -pin  "ACC1:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(8)} -pin  "ACC1:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(9)} -pin  "ACC1:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(10)} -pin  "ACC1:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(11)} -pin  "ACC1:acc" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(12)} -pin  "ACC1:acc" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(13)} -pin  "ACC1:acc" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(14)} -pin  "ACC1:acc" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#281.itm#1(15)} -pin  "ACC1:acc" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm#1}
+load net {ACC1:acc#280.itm(0)} -pin  "ACC1:acc" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(1)} -pin  "ACC1:acc" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(2)} -pin  "ACC1:acc" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(3)} -pin  "ACC1:acc" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(4)} -pin  "ACC1:acc" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(5)} -pin  "ACC1:acc" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(6)} -pin  "ACC1:acc" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(7)} -pin  "ACC1:acc" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(8)} -pin  "ACC1:acc" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(9)} -pin  "ACC1:acc" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(10)} -pin  "ACC1:acc" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(11)} -pin  "ACC1:acc" {B(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(12)} -pin  "ACC1:acc" {B(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(13)} -pin  "ACC1:acc" {B(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(14)} -pin  "ACC1:acc" {B(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(15)} -pin  "ACC1:acc" {B(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc.itm(0)} -pin  "ACC1:acc" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(1)} -pin  "ACC1:acc" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(2)} -pin  "ACC1:acc" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(3)} -pin  "ACC1:acc" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(4)} -pin  "ACC1:acc" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(5)} -pin  "ACC1:acc" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(6)} -pin  "ACC1:acc" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(7)} -pin  "ACC1:acc" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(8)} -pin  "ACC1:acc" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(9)} -pin  "ACC1:acc" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(10)} -pin  "ACC1:acc" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(11)} -pin  "ACC1:acc" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(12)} -pin  "ACC1:acc" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(13)} -pin  "ACC1:acc" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(14)} -pin  "ACC1:acc" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(15)} -pin  "ACC1:acc" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load inst "ACC1-3:not#5" "not(1)" "INTERFACE" -attr xrf 18645 -attr oid 791 -attr @path {/sobel/sobel:core/ACC1-3:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv.sva(9)} -pin  "ACC1-3:not#5" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#7.itm}
+load net {ACC1-3:not#5.itm} -pin  "ACC1-3:not#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#5.itm}
+load inst "ACC1:acc#181" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18646 -attr oid 792 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#181" {A(0)} -attr @path {/sobel/sobel:core/conc#335.itm}
+load net {acc.idiv.sva(8)} -pin  "ACC1:acc#181" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#335.itm}
+load net {PWR} -pin  "ACC1:acc#181" {B(0)} -attr @path {/sobel/sobel:core/conc#336.itm}
+load net {ACC1-3:not#5.itm} -pin  "ACC1:acc#181" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#336.itm}
+load net {ACC1:acc#181.itm(0)} -pin  "ACC1:acc#181" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181.itm}
+load net {ACC1:acc#181.itm(1)} -pin  "ACC1:acc#181" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181.itm}
+load net {ACC1:acc#181.itm(2)} -pin  "ACC1:acc#181" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181.itm}
+load inst "ACC1-3:not#1" "not(1)" "INTERFACE" -attr xrf 18647 -attr oid 793 -attr @path {/sobel/sobel:core/ACC1-3:not#1} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv.sva(1)} -pin  "ACC1-3:not#1" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#13.itm}
+load net {ACC1-3:not#1.itm} -pin  "ACC1-3:not#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#1.itm}
+load inst "ACC1-3:not#7" "not(1)" "INTERFACE" -attr xrf 18648 -attr oid 794 -attr @path {/sobel/sobel:core/ACC1-3:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv.sva(13)} -pin  "ACC1-3:not#7" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#21.itm}
+load net {ACC1-3:not#7.itm} -pin  "ACC1-3:not#7" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#7.itm}
+load inst "ACC1:acc#185" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 18649 -attr oid 795 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#185" {A(0)} -attr @path {/sobel/sobel:core/conc#334.itm}
+load net {ACC1:acc#181.itm(1)} -pin  "ACC1:acc#185" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#334.itm}
+load net {ACC1:acc#181.itm(2)} -pin  "ACC1:acc#185" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#334.itm}
+load net {ACC1-3:not#7.itm} -pin  "ACC1:acc#185" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#353.itm}
+load net {ACC1-3:not#1.itm} -pin  "ACC1:acc#185" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#353.itm}
+load net {ACC1:acc#185.itm(0)} -pin  "ACC1:acc#185" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {ACC1:acc#185.itm(1)} -pin  "ACC1:acc#185" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {ACC1:acc#185.itm(2)} -pin  "ACC1:acc#185" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {ACC1:acc#185.itm(3)} -pin  "ACC1:acc#185" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load inst "ACC1-3:not#2" "not(1)" "INTERFACE" -attr xrf 18650 -attr oid 796 -attr @path {/sobel/sobel:core/ACC1-3:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv.sva(3)} -pin  "ACC1-3:not#2" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#12.itm}
+load net {ACC1-3:not#2.itm} -pin  "ACC1-3:not#2" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#2.itm}
+load inst "ACC1:acc#184" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18651 -attr oid 797 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#184" {A(0)} -attr @path {/sobel/sobel:core/conc#337.itm}
+load net {acc.idiv.sva(2)} -pin  "ACC1:acc#184" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#337.itm}
+load net {acc.idiv.sva(12)} -pin  "ACC1:acc#184" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#351.itm}
+load net {ACC1-3:not#2.itm} -pin  "ACC1:acc#184" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#351.itm}
+load net {ACC1:acc#184.itm(0)} -pin  "ACC1:acc#184" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load net {ACC1:acc#184.itm(1)} -pin  "ACC1:acc#184" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load net {ACC1:acc#184.itm(2)} -pin  "ACC1:acc#184" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load inst "ACC1-3:not#8" "not(1)" "INTERFACE" -attr xrf 18652 -attr oid 798 -attr @path {/sobel/sobel:core/ACC1-3:not#8} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv.sva(15)} -pin  "ACC1-3:not#8" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#23.itm}
+load net {ACC1-3:not#8.itm} -pin  "ACC1-3:not#8" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#8.itm}
+load inst "ACC1:acc#187" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 18653 -attr oid 799 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {PWR} -pin  "ACC1:acc#187" {A(0)} -attr @path {/sobel/sobel:core/conc#333.itm}
+load net {ACC1:acc#185.itm(1)} -pin  "ACC1:acc#187" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#333.itm}
+load net {ACC1:acc#185.itm(2)} -pin  "ACC1:acc#187" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#333.itm}
+load net {ACC1:acc#185.itm(3)} -pin  "ACC1:acc#187" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#333.itm}
+load net {ACC1-3:not#8.itm} -pin  "ACC1:acc#187" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#357.itm}
+load net {ACC1:acc#184.itm(1)} -pin  "ACC1:acc#187" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#357.itm}
+load net {ACC1:acc#184.itm(2)} -pin  "ACC1:acc#187" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#357.itm}
+load net {ACC1:acc#187.itm(0)} -pin  "ACC1:acc#187" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load net {ACC1:acc#187.itm(1)} -pin  "ACC1:acc#187" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load net {ACC1:acc#187.itm(2)} -pin  "ACC1:acc#187" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load net {ACC1:acc#187.itm(3)} -pin  "ACC1:acc#187" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load net {ACC1:acc#187.itm(4)} -pin  "ACC1:acc#187" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load inst "ACC1-3:not#3" "not(1)" "INTERFACE" -attr xrf 18654 -attr oid 800 -attr @path {/sobel/sobel:core/ACC1-3:not#3} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv.sva(5)} -pin  "ACC1-3:not#3" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv.sva).itm}
+load net {ACC1-3:not#3.itm} -pin  "ACC1-3:not#3" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#3.itm}
+load inst "ACC1-3:not#6" "not(1)" "INTERFACE" -attr xrf 18655 -attr oid 801 -attr @path {/sobel/sobel:core/ACC1-3:not#6} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv.sva(11)} -pin  "ACC1-3:not#6" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#1.itm}
+load net {ACC1-3:not#6.itm} -pin  "ACC1-3:not#6" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#6.itm}
+load inst "ACC1:acc#183" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18656 -attr oid 802 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#183" {A(0)} -attr @path {/sobel/sobel:core/conc#339.itm}
+load net {acc.idiv.sva(4)} -pin  "ACC1:acc#183" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#339.itm}
+load net {ACC1-3:not#6.itm} -pin  "ACC1:acc#183" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#349.itm}
+load net {ACC1-3:not#3.itm} -pin  "ACC1:acc#183" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#349.itm}
+load net {ACC1:acc#183.itm(0)} -pin  "ACC1:acc#183" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load net {ACC1:acc#183.itm(1)} -pin  "ACC1:acc#183" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load net {ACC1:acc#183.itm(2)} -pin  "ACC1:acc#183" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load inst "ACC1-3:not#4" "not(1)" "INTERFACE" -attr xrf 18657 -attr oid 803 -attr @path {/sobel/sobel:core/ACC1-3:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv.sva(7)} -pin  "ACC1-3:not#4" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#18.itm}
+load net {ACC1-3:not#4.itm} -pin  "ACC1-3:not#4" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#4.itm}
+load inst "ACC1:acc#182" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18658 -attr oid 804 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#182" {A(0)} -attr @path {/sobel/sobel:core/conc#340.itm}
+load net {acc.idiv.sva(6)} -pin  "ACC1:acc#182" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#340.itm}
+load net {acc.idiv.sva(10)} -pin  "ACC1:acc#182" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#347.itm}
+load net {ACC1-3:not#4.itm} -pin  "ACC1:acc#182" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#347.itm}
+load net {ACC1:acc#182.itm(0)} -pin  "ACC1:acc#182" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182.itm}
+load net {ACC1:acc#182.itm(1)} -pin  "ACC1:acc#182" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182.itm}
+load net {ACC1:acc#182.itm(2)} -pin  "ACC1:acc#182" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182.itm}
+load inst "ACC1:acc#186" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18659 -attr oid 805 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#186" {A(0)} -attr @path {/sobel/sobel:core/conc#338.itm}
+load net {ACC1:acc#183.itm(1)} -pin  "ACC1:acc#186" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#338.itm}
+load net {ACC1:acc#183.itm(2)} -pin  "ACC1:acc#186" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#338.itm}
+load net {acc.idiv.sva(14)} -pin  "ACC1:acc#186" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#355.itm}
+load net {ACC1:acc#182.itm(1)} -pin  "ACC1:acc#186" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#355.itm}
+load net {ACC1:acc#182.itm(2)} -pin  "ACC1:acc#186" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#355.itm}
+load net {ACC1:acc#186.itm(0)} -pin  "ACC1:acc#186" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186.itm}
+load net {ACC1:acc#186.itm(1)} -pin  "ACC1:acc#186" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186.itm}
+load net {ACC1:acc#186.itm(2)} -pin  "ACC1:acc#186" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186.itm}
+load net {ACC1:acc#186.itm(3)} -pin  "ACC1:acc#186" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186.itm}
+load inst "ACC1:acc#188" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 18660 -attr oid 806 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {PWR} -pin  "ACC1:acc#188" {A(0)} -attr @path {/sobel/sobel:core/conc#332.itm}
+load net {ACC1:acc#187.itm(1)} -pin  "ACC1:acc#188" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#332.itm}
+load net {ACC1:acc#187.itm(2)} -pin  "ACC1:acc#188" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#332.itm}
+load net {ACC1:acc#187.itm(3)} -pin  "ACC1:acc#188" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#332.itm}
+load net {ACC1:acc#187.itm(4)} -pin  "ACC1:acc#188" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#332.itm}
+load net {acc.idiv.sva(16)} -pin  "ACC1:acc#188" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#359.itm}
+load net {ACC1:acc#186.itm(1)} -pin  "ACC1:acc#188" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#359.itm}
+load net {ACC1:acc#186.itm(2)} -pin  "ACC1:acc#188" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#359.itm}
+load net {ACC1:acc#186.itm(3)} -pin  "ACC1:acc#188" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#359.itm}
+load net {ACC1:acc#188.itm(0)} -pin  "ACC1:acc#188" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load net {ACC1:acc#188.itm(1)} -pin  "ACC1:acc#188" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load net {ACC1:acc#188.itm(2)} -pin  "ACC1:acc#188" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load net {ACC1:acc#188.itm(3)} -pin  "ACC1:acc#188" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load net {ACC1:acc#188.itm(4)} -pin  "ACC1:acc#188" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load net {ACC1:acc#188.itm(5)} -pin  "ACC1:acc#188" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load inst "ACC1-3:not#9" "not(1)" "INTERFACE" -attr xrf 18661 -attr oid 807 -attr @path {/sobel/sobel:core/ACC1-3:not#9} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv.sva(17)} -pin  "ACC1-3:not#9" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv.sva)#15.itm}
+load net {ACC1-3:not#9.itm} -pin  "ACC1-3:not#9" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#9.itm}
+load inst "ACC1:acc#189" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 18662 -attr oid 808 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {PWR} -pin  "ACC1:acc#189" {A(0)} -attr @path {/sobel/sobel:core/conc#331.itm}
+load net {ACC1:acc#188.itm(1)} -pin  "ACC1:acc#189" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#331.itm}
+load net {ACC1:acc#188.itm(2)} -pin  "ACC1:acc#189" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#331.itm}
+load net {ACC1:acc#188.itm(3)} -pin  "ACC1:acc#189" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#331.itm}
+load net {ACC1:acc#188.itm(4)} -pin  "ACC1:acc#189" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#331.itm}
+load net {ACC1:acc#188.itm(5)} -pin  "ACC1:acc#189" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#331.itm}
+load net {ACC1-3:not#9.itm} -pin  "ACC1:acc#189" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#341.itm}
+load net {acc.idiv.sva(0)} -pin  "ACC1:acc#189" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#341.itm}
+load net {PWR} -pin  "ACC1:acc#189" {B(2)} -attr @path {/sobel/sobel:core/conc#341.itm}
+load net {PWR} -pin  "ACC1:acc#189" {B(3)} -attr @path {/sobel/sobel:core/conc#341.itm}
+load net {GND} -pin  "ACC1:acc#189" {B(4)} -attr @path {/sobel/sobel:core/conc#341.itm}
+load net {PWR} -pin  "ACC1:acc#189" {B(5)} -attr @path {/sobel/sobel:core/conc#341.itm}
+load net {ACC1:acc#189.itm(0)} -pin  "ACC1:acc#189" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {ACC1:acc#189.itm(1)} -pin  "ACC1:acc#189" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {ACC1:acc#189.itm(2)} -pin  "ACC1:acc#189" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {ACC1:acc#189.itm(3)} -pin  "ACC1:acc#189" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {ACC1:acc#189.itm(4)} -pin  "ACC1:acc#189" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {ACC1:acc#189.itm(5)} -pin  "ACC1:acc#189" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load inst "ACC1:acc#153" "add(16,0,16,0,17)" "INTERFACE" -attr xrf 18663 -attr oid 809 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,17)"
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "ACC1:acc#153" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "ACC1:acc#153" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "ACC1:acc#153" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "ACC1:acc#153" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "ACC1:acc#153" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "ACC1:acc#153" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "ACC1:acc#153" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "ACC1:acc#153" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "ACC1:acc#153" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:acc#153" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:acc#153" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:acc#153" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:acc#153" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:acc#153" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:acc#153" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:acc#153" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#56.itm}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "ACC1:acc#153" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "ACC1:acc#153" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "ACC1:acc#153" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "ACC1:acc#153" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "ACC1:acc#153" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "ACC1:acc#153" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "ACC1:acc#153" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "ACC1:acc#153" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "ACC1:acc#153" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:acc#153" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:acc#153" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:acc#153" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:acc#153" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:acc#153" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:acc#153" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:acc#153" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#57.itm}
+load net {ACC1:acc#153.itm(0)} -pin  "ACC1:acc#153" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(1)} -pin  "ACC1:acc#153" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(2)} -pin  "ACC1:acc#153" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(3)} -pin  "ACC1:acc#153" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(4)} -pin  "ACC1:acc#153" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(5)} -pin  "ACC1:acc#153" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(6)} -pin  "ACC1:acc#153" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(7)} -pin  "ACC1:acc#153" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(8)} -pin  "ACC1:acc#153" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(9)} -pin  "ACC1:acc#153" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(10)} -pin  "ACC1:acc#153" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(11)} -pin  "ACC1:acc#153" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(12)} -pin  "ACC1:acc#153" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(13)} -pin  "ACC1:acc#153" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(14)} -pin  "ACC1:acc#153" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(15)} -pin  "ACC1:acc#153" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(16)} -pin  "ACC1:acc#153" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load inst "ACC1-1:acc" "add(17,0,16,0,18)" "INTERFACE" -attr xrf 18664 -attr oid 810 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc} -attr area 18.184140 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(17,0,16,0,18)"
+load net {ACC1:acc#153.itm(0)} -pin  "ACC1-1:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(1)} -pin  "ACC1-1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(2)} -pin  "ACC1-1:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(3)} -pin  "ACC1-1:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(4)} -pin  "ACC1-1:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(5)} -pin  "ACC1-1:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(6)} -pin  "ACC1-1:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(7)} -pin  "ACC1-1:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(8)} -pin  "ACC1-1:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(9)} -pin  "ACC1-1:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(10)} -pin  "ACC1-1:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(11)} -pin  "ACC1-1:acc" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(12)} -pin  "ACC1-1:acc" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(13)} -pin  "ACC1-1:acc" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(14)} -pin  "ACC1-1:acc" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(15)} -pin  "ACC1-1:acc" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(16)} -pin  "ACC1-1:acc" {A(16)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "ACC1-1:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "ACC1-1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "ACC1-1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "ACC1-1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "ACC1-1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "ACC1-1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "ACC1-1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "ACC1-1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "ACC1-1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1-1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1-1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1-1:acc" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1-1:acc" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1-1:acc" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1-1:acc" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1-1:acc" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs.itm}
+load net {acc.idiv#3.sva(0)} -pin  "ACC1-1:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(1)} -pin  "ACC1-1:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(2)} -pin  "ACC1-1:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(3)} -pin  "ACC1-1:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(4)} -pin  "ACC1-1:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(5)} -pin  "ACC1-1:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(6)} -pin  "ACC1-1:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(7)} -pin  "ACC1-1:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(8)} -pin  "ACC1-1:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(9)} -pin  "ACC1-1:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(10)} -pin  "ACC1-1:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(11)} -pin  "ACC1-1:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(12)} -pin  "ACC1-1:acc" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(13)} -pin  "ACC1-1:acc" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(14)} -pin  "ACC1-1:acc" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(15)} -pin  "ACC1-1:acc" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(16)} -pin  "ACC1-1:acc" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load net {acc.idiv#3.sva(17)} -pin  "ACC1-1:acc" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#3.sva}
+load inst "ACC1:acc#165" "add(16,0,16,0,17)" "INTERFACE" -attr xrf 18665 -attr oid 811 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,17)"
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "ACC1:acc#165" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "ACC1:acc#165" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "ACC1:acc#165" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "ACC1:acc#165" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "ACC1:acc#165" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "ACC1:acc#165" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "ACC1:acc#165" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "ACC1:acc#165" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "ACC1:acc#165" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:acc#165" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:acc#165" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:acc#165" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:acc#165" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:acc#165" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:acc#165" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:acc#165" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#68.itm}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "ACC1:acc#165" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "ACC1:acc#165" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "ACC1:acc#165" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "ACC1:acc#165" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "ACC1:acc#165" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "ACC1:acc#165" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "ACC1:acc#165" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "ACC1:acc#165" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "ACC1:acc#165" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:acc#165" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:acc#165" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:acc#165" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:acc#165" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:acc#165" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:acc#165" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:acc#165" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#69.itm}
+load net {ACC1:acc#165.itm(0)} -pin  "ACC1:acc#165" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(1)} -pin  "ACC1:acc#165" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(2)} -pin  "ACC1:acc#165" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(3)} -pin  "ACC1:acc#165" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(4)} -pin  "ACC1:acc#165" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(5)} -pin  "ACC1:acc#165" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(6)} -pin  "ACC1:acc#165" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(7)} -pin  "ACC1:acc#165" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(8)} -pin  "ACC1:acc#165" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(9)} -pin  "ACC1:acc#165" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(10)} -pin  "ACC1:acc#165" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(11)} -pin  "ACC1:acc#165" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(12)} -pin  "ACC1:acc#165" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(13)} -pin  "ACC1:acc#165" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(14)} -pin  "ACC1:acc#165" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(15)} -pin  "ACC1:acc#165" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(16)} -pin  "ACC1:acc#165" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load inst "ACC1-1:acc#26" "add(17,0,16,0,18)" "INTERFACE" -attr xrf 18666 -attr oid 812 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#26} -attr area 18.184140 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(17,0,16,0,18)"
+load net {ACC1:acc#165.itm(0)} -pin  "ACC1-1:acc#26" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(1)} -pin  "ACC1-1:acc#26" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(2)} -pin  "ACC1-1:acc#26" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(3)} -pin  "ACC1-1:acc#26" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(4)} -pin  "ACC1-1:acc#26" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(5)} -pin  "ACC1-1:acc#26" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(6)} -pin  "ACC1-1:acc#26" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(7)} -pin  "ACC1-1:acc#26" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(8)} -pin  "ACC1-1:acc#26" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(9)} -pin  "ACC1-1:acc#26" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(10)} -pin  "ACC1-1:acc#26" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(11)} -pin  "ACC1-1:acc#26" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(12)} -pin  "ACC1-1:acc#26" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(13)} -pin  "ACC1-1:acc#26" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(14)} -pin  "ACC1-1:acc#26" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(15)} -pin  "ACC1-1:acc#26" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(16)} -pin  "ACC1-1:acc#26" {A(16)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "ACC1-1:acc#26" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "ACC1-1:acc#26" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "ACC1-1:acc#26" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "ACC1-1:acc#26" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "ACC1-1:acc#26" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "ACC1-1:acc#26" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "ACC1-1:acc#26" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "ACC1-1:acc#26" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "ACC1-1:acc#26" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1-1:acc#26" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1-1:acc#26" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1-1:acc#26" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1-1:acc#26" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1-1:acc#26" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1-1:acc#26" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1-1:acc#26" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#67.itm}
+load net {acc.idiv#7.sva(0)} -pin  "ACC1-1:acc#26" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(1)} -pin  "ACC1-1:acc#26" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(2)} -pin  "ACC1-1:acc#26" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(3)} -pin  "ACC1-1:acc#26" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(4)} -pin  "ACC1-1:acc#26" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(5)} -pin  "ACC1-1:acc#26" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(6)} -pin  "ACC1-1:acc#26" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(7)} -pin  "ACC1-1:acc#26" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(8)} -pin  "ACC1-1:acc#26" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(9)} -pin  "ACC1-1:acc#26" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(10)} -pin  "ACC1-1:acc#26" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(11)} -pin  "ACC1-1:acc#26" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(12)} -pin  "ACC1-1:acc#26" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(13)} -pin  "ACC1-1:acc#26" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(14)} -pin  "ACC1-1:acc#26" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(15)} -pin  "ACC1-1:acc#26" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(16)} -pin  "ACC1-1:acc#26" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load net {acc.idiv#7.sva(17)} -pin  "ACC1-1:acc#26" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#7.sva}
+load inst "ACC1:not#73" "not(10)" "INTERFACE" -attr xrf 18667 -attr oid 813 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#73} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs:slc(regs.regs(2))#6.itm(0)} -pin  "ACC1:not#73" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(1)} -pin  "ACC1:not#73" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(2)} -pin  "ACC1:not#73" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(3)} -pin  "ACC1:not#73" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(4)} -pin  "ACC1:not#73" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(5)} -pin  "ACC1:not#73" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(6)} -pin  "ACC1:not#73" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(7)} -pin  "ACC1:not#73" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(8)} -pin  "ACC1:not#73" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {regs.regs:slc(regs.regs(2))#6.itm(9)} -pin  "ACC1:not#73" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#6.itm}
+load net {ACC1:not#73.itm(0)} -pin  "ACC1:not#73" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#73.itm}
+load net {ACC1:not#73.itm(1)} -pin  "ACC1:not#73" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#73.itm}
+load net {ACC1:not#73.itm(2)} -pin  "ACC1:not#73" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#73.itm}
+load net {ACC1:not#73.itm(3)} -pin  "ACC1:not#73" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#73.itm}
+load net {ACC1:not#73.itm(4)} -pin  "ACC1:not#73" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#73.itm}
+load net {ACC1:not#73.itm(5)} -pin  "ACC1:not#73" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#73.itm}
+load net {ACC1:not#73.itm(6)} -pin  "ACC1:not#73" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#73.itm}
+load net {ACC1:not#73.itm(7)} -pin  "ACC1:not#73" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#73.itm}
+load net {ACC1:not#73.itm(8)} -pin  "ACC1:not#73" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#73.itm}
+load net {ACC1:not#73.itm(9)} -pin  "ACC1:not#73" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#73.itm}
+load inst "ACC1:acc#178" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 18668 -attr oid 814 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#178" {A(0)} -attr @path {/sobel/sobel:core/conc#342.itm}
+load net {ACC1:not#73.itm(0)} -pin  "ACC1:acc#178" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#342.itm}
+load net {ACC1:not#73.itm(1)} -pin  "ACC1:acc#178" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#342.itm}
+load net {ACC1:not#73.itm(2)} -pin  "ACC1:acc#178" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#342.itm}
+load net {ACC1:not#73.itm(3)} -pin  "ACC1:acc#178" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#342.itm}
+load net {ACC1:not#73.itm(4)} -pin  "ACC1:acc#178" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#342.itm}
+load net {ACC1:not#73.itm(5)} -pin  "ACC1:acc#178" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#342.itm}
+load net {ACC1:not#73.itm(6)} -pin  "ACC1:acc#178" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#342.itm}
+load net {ACC1:not#73.itm(7)} -pin  "ACC1:acc#178" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#342.itm}
+load net {ACC1:not#73.itm(8)} -pin  "ACC1:acc#178" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#342.itm}
+load net {ACC1:not#73.itm(9)} -pin  "ACC1:acc#178" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#342.itm}
+load net {PWR} -pin  "ACC1:acc#178" {B(0)} -attr @path {/sobel/sobel:core/conc#343.itm}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "ACC1:acc#178" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#343.itm}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "ACC1:acc#178" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#343.itm}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "ACC1:acc#178" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#343.itm}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "ACC1:acc#178" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#343.itm}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "ACC1:acc#178" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#343.itm}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "ACC1:acc#178" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#343.itm}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "ACC1:acc#178" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#343.itm}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "ACC1:acc#178" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#343.itm}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "ACC1:acc#178" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#343.itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:acc#178" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#343.itm}
+load net {ACC1:acc#178.itm(0)} -pin  "ACC1:acc#178" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(1)} -pin  "ACC1:acc#178" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(2)} -pin  "ACC1:acc#178" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(3)} -pin  "ACC1:acc#178" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(4)} -pin  "ACC1:acc#178" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(5)} -pin  "ACC1:acc#178" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(6)} -pin  "ACC1:acc#178" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(7)} -pin  "ACC1:acc#178" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(8)} -pin  "ACC1:acc#178" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(9)} -pin  "ACC1:acc#178" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(10)} -pin  "ACC1:acc#178" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(11)} -pin  "ACC1:acc#178" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load inst "ACC1:not#74" "not(10)" "INTERFACE" -attr xrf 18669 -attr oid 815 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#74} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs:slc(regs.regs(2))#7.itm(0)} -pin  "ACC1:not#74" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(1)} -pin  "ACC1:not#74" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(2)} -pin  "ACC1:not#74" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(3)} -pin  "ACC1:not#74" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(4)} -pin  "ACC1:not#74" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(5)} -pin  "ACC1:not#74" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(6)} -pin  "ACC1:not#74" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(7)} -pin  "ACC1:not#74" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(8)} -pin  "ACC1:not#74" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {regs.regs:slc(regs.regs(2))#7.itm(9)} -pin  "ACC1:not#74" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2))#7.itm}
+load net {ACC1:not#74.itm(0)} -pin  "ACC1:not#74" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#74.itm}
+load net {ACC1:not#74.itm(1)} -pin  "ACC1:not#74" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#74.itm}
+load net {ACC1:not#74.itm(2)} -pin  "ACC1:not#74" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#74.itm}
+load net {ACC1:not#74.itm(3)} -pin  "ACC1:not#74" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#74.itm}
+load net {ACC1:not#74.itm(4)} -pin  "ACC1:not#74" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#74.itm}
+load net {ACC1:not#74.itm(5)} -pin  "ACC1:not#74" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#74.itm}
+load net {ACC1:not#74.itm(6)} -pin  "ACC1:not#74" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#74.itm}
+load net {ACC1:not#74.itm(7)} -pin  "ACC1:not#74" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#74.itm}
+load net {ACC1:not#74.itm(8)} -pin  "ACC1:not#74" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#74.itm}
+load net {ACC1:not#74.itm(9)} -pin  "ACC1:not#74" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#74.itm}
+load inst "ACC1:acc#179" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 18670 -attr oid 816 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#179" {A(0)} -attr @path {/sobel/sobel:core/conc#344.itm}
+load net {ACC1:not#74.itm(0)} -pin  "ACC1:acc#179" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#344.itm}
+load net {ACC1:not#74.itm(1)} -pin  "ACC1:acc#179" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#344.itm}
+load net {ACC1:not#74.itm(2)} -pin  "ACC1:acc#179" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#344.itm}
+load net {ACC1:not#74.itm(3)} -pin  "ACC1:acc#179" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#344.itm}
+load net {ACC1:not#74.itm(4)} -pin  "ACC1:acc#179" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#344.itm}
+load net {ACC1:not#74.itm(5)} -pin  "ACC1:acc#179" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#344.itm}
+load net {ACC1:not#74.itm(6)} -pin  "ACC1:acc#179" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#344.itm}
+load net {ACC1:not#74.itm(7)} -pin  "ACC1:acc#179" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#344.itm}
+load net {ACC1:not#74.itm(8)} -pin  "ACC1:acc#179" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#344.itm}
+load net {ACC1:not#74.itm(9)} -pin  "ACC1:acc#179" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#344.itm}
+load net {PWR} -pin  "ACC1:acc#179" {B(0)} -attr @path {/sobel/sobel:core/conc#345.itm}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "ACC1:acc#179" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#345.itm}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "ACC1:acc#179" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#345.itm}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "ACC1:acc#179" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#345.itm}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "ACC1:acc#179" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#345.itm}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "ACC1:acc#179" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#345.itm}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "ACC1:acc#179" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#345.itm}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "ACC1:acc#179" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#345.itm}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "ACC1:acc#179" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#345.itm}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "ACC1:acc#179" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#345.itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:acc#179" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#345.itm}
+load net {ACC1:acc#179.itm(0)} -pin  "ACC1:acc#179" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(1)} -pin  "ACC1:acc#179" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(2)} -pin  "ACC1:acc#179" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(3)} -pin  "ACC1:acc#179" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(4)} -pin  "ACC1:acc#179" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(5)} -pin  "ACC1:acc#179" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(6)} -pin  "ACC1:acc#179" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(7)} -pin  "ACC1:acc#179" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(8)} -pin  "ACC1:acc#179" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(9)} -pin  "ACC1:acc#179" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(10)} -pin  "ACC1:acc#179" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(11)} -pin  "ACC1:acc#179" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load inst "ACC1:acc#177" "add(16,0,16,0,17)" "INTERFACE" -attr xrf 18671 -attr oid 817 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,17)"
+load net {ACC1:acc#178.itm(1)} -pin  "ACC1:acc#177" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(2)} -pin  "ACC1:acc#177" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(3)} -pin  "ACC1:acc#177" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(4)} -pin  "ACC1:acc#177" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(5)} -pin  "ACC1:acc#177" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(6)} -pin  "ACC1:acc#177" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(7)} -pin  "ACC1:acc#177" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(8)} -pin  "ACC1:acc#177" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(9)} -pin  "ACC1:acc#177" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(10)} -pin  "ACC1:acc#177" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(11)} -pin  "ACC1:acc#177" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(11)} -pin  "ACC1:acc#177" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(11)} -pin  "ACC1:acc#177" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(11)} -pin  "ACC1:acc#177" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(11)} -pin  "ACC1:acc#177" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#178.itm(11)} -pin  "ACC1:acc#177" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#95.itm}
+load net {ACC1:acc#179.itm(1)} -pin  "ACC1:acc#177" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(2)} -pin  "ACC1:acc#177" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(3)} -pin  "ACC1:acc#177" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(4)} -pin  "ACC1:acc#177" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(5)} -pin  "ACC1:acc#177" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(6)} -pin  "ACC1:acc#177" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(7)} -pin  "ACC1:acc#177" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(8)} -pin  "ACC1:acc#177" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(9)} -pin  "ACC1:acc#177" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(10)} -pin  "ACC1:acc#177" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(11)} -pin  "ACC1:acc#177" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(11)} -pin  "ACC1:acc#177" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(11)} -pin  "ACC1:acc#177" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(11)} -pin  "ACC1:acc#177" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(11)} -pin  "ACC1:acc#177" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#179.itm(11)} -pin  "ACC1:acc#177" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#96.itm}
+load net {ACC1:acc#177.itm(0)} -pin  "ACC1:acc#177" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(1)} -pin  "ACC1:acc#177" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(2)} -pin  "ACC1:acc#177" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(3)} -pin  "ACC1:acc#177" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(4)} -pin  "ACC1:acc#177" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(5)} -pin  "ACC1:acc#177" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(6)} -pin  "ACC1:acc#177" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(7)} -pin  "ACC1:acc#177" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(8)} -pin  "ACC1:acc#177" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(9)} -pin  "ACC1:acc#177" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(10)} -pin  "ACC1:acc#177" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(11)} -pin  "ACC1:acc#177" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(12)} -pin  "ACC1:acc#177" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(13)} -pin  "ACC1:acc#177" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(14)} -pin  "ACC1:acc#177" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(15)} -pin  "ACC1:acc#177" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(16)} -pin  "ACC1:acc#177" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load inst "ACC1:not#72" "not(10)" "INTERFACE" -attr xrf 18672 -attr oid 818 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#72} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {regs.regs:slc(regs.regs(2)).itm(0)} -pin  "ACC1:not#72" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(1)} -pin  "ACC1:not#72" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(2)} -pin  "ACC1:not#72" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(3)} -pin  "ACC1:not#72" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(4)} -pin  "ACC1:not#72" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(5)} -pin  "ACC1:not#72" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(6)} -pin  "ACC1:not#72" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(7)} -pin  "ACC1:not#72" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(8)} -pin  "ACC1:not#72" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {regs.regs:slc(regs.regs(2)).itm(9)} -pin  "ACC1:not#72" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2)).itm}
+load net {ACC1:not#72.itm(0)} -pin  "ACC1:not#72" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#72.itm}
+load net {ACC1:not#72.itm(1)} -pin  "ACC1:not#72" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#72.itm}
+load net {ACC1:not#72.itm(2)} -pin  "ACC1:not#72" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#72.itm}
+load net {ACC1:not#72.itm(3)} -pin  "ACC1:not#72" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#72.itm}
+load net {ACC1:not#72.itm(4)} -pin  "ACC1:not#72" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#72.itm}
+load net {ACC1:not#72.itm(5)} -pin  "ACC1:not#72" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#72.itm}
+load net {ACC1:not#72.itm(6)} -pin  "ACC1:not#72" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#72.itm}
+load net {ACC1:not#72.itm(7)} -pin  "ACC1:not#72" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#72.itm}
+load net {ACC1:not#72.itm(8)} -pin  "ACC1:not#72" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#72.itm}
+load net {ACC1:not#72.itm(9)} -pin  "ACC1:not#72" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#72.itm}
+load inst "ACC1:acc#180" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 18673 -attr oid 819 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {PWR} -pin  "ACC1:acc#180" {A(0)} -attr @path {/sobel/sobel:core/conc#346.itm}
+load net {ACC1:not#72.itm(0)} -pin  "ACC1:acc#180" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#346.itm}
+load net {ACC1:not#72.itm(1)} -pin  "ACC1:acc#180" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#346.itm}
+load net {ACC1:not#72.itm(2)} -pin  "ACC1:acc#180" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#346.itm}
+load net {ACC1:not#72.itm(3)} -pin  "ACC1:acc#180" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#346.itm}
+load net {ACC1:not#72.itm(4)} -pin  "ACC1:acc#180" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#346.itm}
+load net {ACC1:not#72.itm(5)} -pin  "ACC1:acc#180" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#346.itm}
+load net {ACC1:not#72.itm(6)} -pin  "ACC1:acc#180" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#346.itm}
+load net {ACC1:not#72.itm(7)} -pin  "ACC1:acc#180" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#346.itm}
+load net {ACC1:not#72.itm(8)} -pin  "ACC1:acc#180" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#346.itm}
+load net {ACC1:not#72.itm(9)} -pin  "ACC1:acc#180" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#346.itm}
+load net {PWR} -pin  "ACC1:acc#180" {B(0)} -attr @path {/sobel/sobel:core/conc#347.itm}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "ACC1:acc#180" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#347.itm}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "ACC1:acc#180" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#347.itm}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "ACC1:acc#180" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#347.itm}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "ACC1:acc#180" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#347.itm}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "ACC1:acc#180" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#347.itm}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "ACC1:acc#180" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#347.itm}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "ACC1:acc#180" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#347.itm}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "ACC1:acc#180" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#347.itm}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "ACC1:acc#180" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#347.itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1:acc#180" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#347.itm}
+load net {ACC1:acc#180.itm(0)} -pin  "ACC1:acc#180" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(1)} -pin  "ACC1:acc#180" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(2)} -pin  "ACC1:acc#180" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(3)} -pin  "ACC1:acc#180" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(4)} -pin  "ACC1:acc#180" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(5)} -pin  "ACC1:acc#180" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(6)} -pin  "ACC1:acc#180" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(7)} -pin  "ACC1:acc#180" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(8)} -pin  "ACC1:acc#180" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(9)} -pin  "ACC1:acc#180" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(10)} -pin  "ACC1:acc#180" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(11)} -pin  "ACC1:acc#180" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load inst "ACC1-3:acc" "add(17,0,16,0,18)" "INTERFACE" -attr xrf 18674 -attr oid 820 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc} -attr area 18.184140 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(17,0,16,0,18)"
+load net {ACC1:acc#177.itm(0)} -pin  "ACC1-3:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(1)} -pin  "ACC1-3:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(2)} -pin  "ACC1-3:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(3)} -pin  "ACC1-3:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(4)} -pin  "ACC1-3:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(5)} -pin  "ACC1-3:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(6)} -pin  "ACC1-3:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(7)} -pin  "ACC1-3:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(8)} -pin  "ACC1-3:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(9)} -pin  "ACC1-3:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(10)} -pin  "ACC1-3:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(11)} -pin  "ACC1-3:acc" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(12)} -pin  "ACC1-3:acc" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(13)} -pin  "ACC1-3:acc" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(14)} -pin  "ACC1-3:acc" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(15)} -pin  "ACC1-3:acc" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(16)} -pin  "ACC1-3:acc" {A(16)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#180.itm(1)} -pin  "ACC1-3:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(2)} -pin  "ACC1-3:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(3)} -pin  "ACC1-3:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(4)} -pin  "ACC1-3:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(5)} -pin  "ACC1-3:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(6)} -pin  "ACC1-3:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(7)} -pin  "ACC1-3:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(8)} -pin  "ACC1-3:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(9)} -pin  "ACC1-3:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(10)} -pin  "ACC1-3:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(11)} -pin  "ACC1-3:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(11)} -pin  "ACC1-3:acc" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(11)} -pin  "ACC1-3:acc" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(11)} -pin  "ACC1-3:acc" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(11)} -pin  "ACC1-3:acc" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {ACC1:acc#180.itm(11)} -pin  "ACC1-3:acc" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#94.itm}
+load net {acc.idiv.sva(0)} -pin  "ACC1-3:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(1)} -pin  "ACC1-3:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(2)} -pin  "ACC1-3:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(3)} -pin  "ACC1-3:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(4)} -pin  "ACC1-3:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(5)} -pin  "ACC1-3:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(6)} -pin  "ACC1-3:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(7)} -pin  "ACC1-3:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(8)} -pin  "ACC1-3:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(9)} -pin  "ACC1-3:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(10)} -pin  "ACC1-3:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(11)} -pin  "ACC1-3:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(12)} -pin  "ACC1-3:acc" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(13)} -pin  "ACC1-3:acc" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(14)} -pin  "ACC1-3:acc" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(15)} -pin  "ACC1-3:acc" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(16)} -pin  "ACC1-3:acc" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load net {acc.idiv.sva(17)} -pin  "ACC1-3:acc" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv.sva}
+load inst "ACC1-3:acc#22" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 18675 -attr oid 821 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#22} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "ACC1-3:acc#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "ACC1-3:acc#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "ACC1-3:acc#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "ACC1-3:acc#22" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "ACC1-3:acc#22" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "ACC1-3:acc#22" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "ACC1-3:acc#22" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "ACC1-3:acc#22" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "ACC1-3:acc#22" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1-3:acc#22" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(0)} -pin  "ACC1-3:acc#22" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(1)} -pin  "ACC1-3:acc#22" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(2)} -pin  "ACC1-3:acc#22" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(3)} -pin  "ACC1-3:acc#22" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(4)} -pin  "ACC1-3:acc#22" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(5)} -pin  "ACC1-3:acc#22" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(6)} -pin  "ACC1-3:acc#22" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(7)} -pin  "ACC1-3:acc#22" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(8)} -pin  "ACC1-3:acc#22" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#1.itm(9)} -pin  "ACC1-3:acc#22" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#1.itm}
+load net {ACC1-3:acc#22.itm(0)} -pin  "ACC1-3:acc#22" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#22.itm}
+load net {ACC1-3:acc#22.itm(1)} -pin  "ACC1-3:acc#22" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#22.itm}
+load net {ACC1-3:acc#22.itm(2)} -pin  "ACC1-3:acc#22" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#22.itm}
+load net {ACC1-3:acc#22.itm(3)} -pin  "ACC1-3:acc#22" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#22.itm}
+load net {ACC1-3:acc#22.itm(4)} -pin  "ACC1-3:acc#22" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#22.itm}
+load net {ACC1-3:acc#22.itm(5)} -pin  "ACC1-3:acc#22" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#22.itm}
+load net {ACC1-3:acc#22.itm(6)} -pin  "ACC1-3:acc#22" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#22.itm}
+load net {ACC1-3:acc#22.itm(7)} -pin  "ACC1-3:acc#22" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#22.itm}
+load net {ACC1-3:acc#22.itm(8)} -pin  "ACC1-3:acc#22" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#22.itm}
+load net {ACC1-3:acc#22.itm(9)} -pin  "ACC1-3:acc#22" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#22.itm}
+load net {ACC1-3:acc#22.itm(10)} -pin  "ACC1-3:acc#22" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#22.itm}
+load inst "ACC1-3:acc#25" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 18676 -attr oid 822 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#25} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "ACC1-3:acc#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "ACC1-3:acc#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "ACC1-3:acc#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "ACC1-3:acc#25" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "ACC1-3:acc#25" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "ACC1-3:acc#25" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "ACC1-3:acc#25" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "ACC1-3:acc#25" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "ACC1-3:acc#25" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1-3:acc#25" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(0)} -pin  "ACC1-3:acc#25" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(1)} -pin  "ACC1-3:acc#25" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(2)} -pin  "ACC1-3:acc#25" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(3)} -pin  "ACC1-3:acc#25" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(4)} -pin  "ACC1-3:acc#25" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(5)} -pin  "ACC1-3:acc#25" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(6)} -pin  "ACC1-3:acc#25" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(7)} -pin  "ACC1-3:acc#25" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(8)} -pin  "ACC1-3:acc#25" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {regs.regs:slc(regs.regs(2).sg2)#2.itm(9)} -pin  "ACC1-3:acc#25" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2)#2.itm}
+load net {ACC1-3:acc#25.itm(0)} -pin  "ACC1-3:acc#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#25.itm}
+load net {ACC1-3:acc#25.itm(1)} -pin  "ACC1-3:acc#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#25.itm}
+load net {ACC1-3:acc#25.itm(2)} -pin  "ACC1-3:acc#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#25.itm}
+load net {ACC1-3:acc#25.itm(3)} -pin  "ACC1-3:acc#25" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#25.itm}
+load net {ACC1-3:acc#25.itm(4)} -pin  "ACC1-3:acc#25" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#25.itm}
+load net {ACC1-3:acc#25.itm(5)} -pin  "ACC1-3:acc#25" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#25.itm}
+load net {ACC1-3:acc#25.itm(6)} -pin  "ACC1-3:acc#25" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#25.itm}
+load net {ACC1-3:acc#25.itm(7)} -pin  "ACC1-3:acc#25" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#25.itm}
+load net {ACC1-3:acc#25.itm(8)} -pin  "ACC1-3:acc#25" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#25.itm}
+load net {ACC1-3:acc#25.itm(9)} -pin  "ACC1-3:acc#25" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#25.itm}
+load net {ACC1-3:acc#25.itm(10)} -pin  "ACC1-3:acc#25" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#25.itm}
+load inst "ACC1:acc#192" "add(16,0,16,0,17)" "INTERFACE" -attr xrf 18677 -attr oid 823 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,17)"
+load net {ACC1-3:acc#22.itm(0)} -pin  "ACC1:acc#192" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(1)} -pin  "ACC1:acc#192" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(2)} -pin  "ACC1:acc#192" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(3)} -pin  "ACC1:acc#192" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(4)} -pin  "ACC1:acc#192" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(5)} -pin  "ACC1:acc#192" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(6)} -pin  "ACC1:acc#192" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(7)} -pin  "ACC1:acc#192" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(8)} -pin  "ACC1:acc#192" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(9)} -pin  "ACC1:acc#192" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(10)} -pin  "ACC1:acc#192" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(10)} -pin  "ACC1:acc#192" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(10)} -pin  "ACC1:acc#192" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(10)} -pin  "ACC1:acc#192" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(10)} -pin  "ACC1:acc#192" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#22.itm(10)} -pin  "ACC1:acc#192" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#74.itm}
+load net {ACC1-3:acc#25.itm(0)} -pin  "ACC1:acc#192" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(1)} -pin  "ACC1:acc#192" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(2)} -pin  "ACC1:acc#192" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(3)} -pin  "ACC1:acc#192" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(4)} -pin  "ACC1:acc#192" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(5)} -pin  "ACC1:acc#192" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(6)} -pin  "ACC1:acc#192" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(7)} -pin  "ACC1:acc#192" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(8)} -pin  "ACC1:acc#192" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(9)} -pin  "ACC1:acc#192" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(10)} -pin  "ACC1:acc#192" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(10)} -pin  "ACC1:acc#192" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(10)} -pin  "ACC1:acc#192" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(10)} -pin  "ACC1:acc#192" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(10)} -pin  "ACC1:acc#192" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1-3:acc#25.itm(10)} -pin  "ACC1:acc#192" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#75.itm}
+load net {ACC1:acc#192.itm(0)} -pin  "ACC1:acc#192" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(1)} -pin  "ACC1:acc#192" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(2)} -pin  "ACC1:acc#192" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(3)} -pin  "ACC1:acc#192" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(4)} -pin  "ACC1:acc#192" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(5)} -pin  "ACC1:acc#192" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(6)} -pin  "ACC1:acc#192" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(7)} -pin  "ACC1:acc#192" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(8)} -pin  "ACC1:acc#192" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(9)} -pin  "ACC1:acc#192" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(10)} -pin  "ACC1:acc#192" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(11)} -pin  "ACC1:acc#192" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(12)} -pin  "ACC1:acc#192" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(13)} -pin  "ACC1:acc#192" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(14)} -pin  "ACC1:acc#192" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(15)} -pin  "ACC1:acc#192" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(16)} -pin  "ACC1:acc#192" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load inst "ACC1-3:acc#19" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 18678 -attr oid 824 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#19} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "ACC1-3:acc#19" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "ACC1-3:acc#19" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "ACC1-3:acc#19" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "ACC1-3:acc#19" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "ACC1-3:acc#19" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "ACC1-3:acc#19" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "ACC1-3:acc#19" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "ACC1-3:acc#19" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "ACC1-3:acc#19" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1-3:acc#19" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3)#1.itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(0)} -pin  "ACC1-3:acc#19" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(1)} -pin  "ACC1-3:acc#19" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(2)} -pin  "ACC1-3:acc#19" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(3)} -pin  "ACC1-3:acc#19" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(4)} -pin  "ACC1-3:acc#19" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(5)} -pin  "ACC1-3:acc#19" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(6)} -pin  "ACC1-3:acc#19" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(7)} -pin  "ACC1-3:acc#19" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(8)} -pin  "ACC1-3:acc#19" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {regs.regs:slc(regs.regs(2).sg2).itm(9)} -pin  "ACC1-3:acc#19" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs:slc(regs.regs(2).sg2).itm}
+load net {ACC1-3:acc#19.itm(0)} -pin  "ACC1-3:acc#19" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#19.itm}
+load net {ACC1-3:acc#19.itm(1)} -pin  "ACC1-3:acc#19" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#19.itm}
+load net {ACC1-3:acc#19.itm(2)} -pin  "ACC1-3:acc#19" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#19.itm}
+load net {ACC1-3:acc#19.itm(3)} -pin  "ACC1-3:acc#19" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#19.itm}
+load net {ACC1-3:acc#19.itm(4)} -pin  "ACC1-3:acc#19" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#19.itm}
+load net {ACC1-3:acc#19.itm(5)} -pin  "ACC1-3:acc#19" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#19.itm}
+load net {ACC1-3:acc#19.itm(6)} -pin  "ACC1-3:acc#19" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#19.itm}
+load net {ACC1-3:acc#19.itm(7)} -pin  "ACC1-3:acc#19" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#19.itm}
+load net {ACC1-3:acc#19.itm(8)} -pin  "ACC1-3:acc#19" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#19.itm}
+load net {ACC1-3:acc#19.itm(9)} -pin  "ACC1-3:acc#19" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#19.itm}
+load net {ACC1-3:acc#19.itm(10)} -pin  "ACC1-3:acc#19" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#19.itm}
+load inst "ACC1-3:acc#26" "add(17,0,16,0,18)" "INTERFACE" -attr xrf 18679 -attr oid 825 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#26} -attr area 18.184140 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(17,0,16,0,18)"
+load net {ACC1:acc#192.itm(0)} -pin  "ACC1-3:acc#26" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(1)} -pin  "ACC1-3:acc#26" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(2)} -pin  "ACC1-3:acc#26" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(3)} -pin  "ACC1-3:acc#26" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(4)} -pin  "ACC1-3:acc#26" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(5)} -pin  "ACC1-3:acc#26" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(6)} -pin  "ACC1-3:acc#26" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(7)} -pin  "ACC1-3:acc#26" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(8)} -pin  "ACC1-3:acc#26" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(9)} -pin  "ACC1-3:acc#26" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(10)} -pin  "ACC1-3:acc#26" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(11)} -pin  "ACC1-3:acc#26" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(12)} -pin  "ACC1-3:acc#26" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(13)} -pin  "ACC1-3:acc#26" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(14)} -pin  "ACC1-3:acc#26" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(15)} -pin  "ACC1-3:acc#26" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(16)} -pin  "ACC1-3:acc#26" {A(16)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1-3:acc#19.itm(0)} -pin  "ACC1-3:acc#26" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(1)} -pin  "ACC1-3:acc#26" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(2)} -pin  "ACC1-3:acc#26" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(3)} -pin  "ACC1-3:acc#26" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(4)} -pin  "ACC1-3:acc#26" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(5)} -pin  "ACC1-3:acc#26" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(6)} -pin  "ACC1-3:acc#26" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(7)} -pin  "ACC1-3:acc#26" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(8)} -pin  "ACC1-3:acc#26" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(9)} -pin  "ACC1-3:acc#26" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(10)} -pin  "ACC1-3:acc#26" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(10)} -pin  "ACC1-3:acc#26" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(10)} -pin  "ACC1-3:acc#26" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(10)} -pin  "ACC1-3:acc#26" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(10)} -pin  "ACC1-3:acc#26" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {ACC1-3:acc#19.itm(10)} -pin  "ACC1-3:acc#26" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#73.itm}
+load net {acc.idiv#2.sva(0)} -pin  "ACC1-3:acc#26" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(1)} -pin  "ACC1-3:acc#26" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(2)} -pin  "ACC1-3:acc#26" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(3)} -pin  "ACC1-3:acc#26" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(4)} -pin  "ACC1-3:acc#26" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(5)} -pin  "ACC1-3:acc#26" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(6)} -pin  "ACC1-3:acc#26" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(7)} -pin  "ACC1-3:acc#26" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(8)} -pin  "ACC1-3:acc#26" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(9)} -pin  "ACC1-3:acc#26" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(10)} -pin  "ACC1-3:acc#26" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(11)} -pin  "ACC1-3:acc#26" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(12)} -pin  "ACC1-3:acc#26" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(13)} -pin  "ACC1-3:acc#26" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(14)} -pin  "ACC1-3:acc#26" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(15)} -pin  "ACC1-3:acc#26" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(16)} -pin  "ACC1-3:acc#26" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load net {acc.idiv#2.sva(17)} -pin  "ACC1-3:acc#26" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/acc.idiv#2.sva}
+load inst "ACC1-1:not#5" "not(1)" "INTERFACE" -attr xrf 18680 -attr oid 826 -attr @path {/sobel/sobel:core/ACC1-1:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#3.sva(9)} -pin  "ACC1-1:not#5" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#1.itm}
+load net {ACC1-1:not#5.itm} -pin  "ACC1-1:not#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#5.itm}
+load inst "ACC1:acc#154" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18681 -attr oid 827 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#154" {A(0)} -attr @path {/sobel/sobel:core/conc#352.itm}
+load net {acc.idiv#3.sva(8)} -pin  "ACC1:acc#154" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#352.itm}
+load net {PWR} -pin  "ACC1:acc#154" {B(0)} -attr @path {/sobel/sobel:core/conc#353.itm}
+load net {ACC1-1:not#5.itm} -pin  "ACC1:acc#154" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#353.itm}
+load net {ACC1:acc#154.itm(0)} -pin  "ACC1:acc#154" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154.itm}
+load net {ACC1:acc#154.itm(1)} -pin  "ACC1:acc#154" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154.itm}
+load net {ACC1:acc#154.itm(2)} -pin  "ACC1:acc#154" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154.itm}
+load inst "ACC1-1:not#1" "not(1)" "INTERFACE" -attr xrf 18682 -attr oid 828 -attr @path {/sobel/sobel:core/ACC1-1:not#1} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#3.sva(1)} -pin  "ACC1-1:not#1" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#12.itm}
+load net {ACC1-1:not#1.itm} -pin  "ACC1-1:not#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#1.itm}
+load inst "ACC1-1:not#7" "not(1)" "INTERFACE" -attr xrf 18683 -attr oid 829 -attr @path {/sobel/sobel:core/ACC1-1:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#3.sva(13)} -pin  "ACC1-1:not#7" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#26.itm}
+load net {ACC1-1:not#7.itm} -pin  "ACC1-1:not#7" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#7.itm}
+load inst "ACC1:acc#158" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 18684 -attr oid 830 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#158" {A(0)} -attr @path {/sobel/sobel:core/conc#351.itm}
+load net {ACC1:acc#154.itm(1)} -pin  "ACC1:acc#158" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#351.itm}
+load net {ACC1:acc#154.itm(2)} -pin  "ACC1:acc#158" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#351.itm}
+load net {ACC1-1:not#7.itm} -pin  "ACC1:acc#158" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#299.itm}
+load net {ACC1-1:not#1.itm} -pin  "ACC1:acc#158" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#299.itm}
+load net {ACC1:acc#158.itm(0)} -pin  "ACC1:acc#158" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {ACC1:acc#158.itm(1)} -pin  "ACC1:acc#158" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {ACC1:acc#158.itm(2)} -pin  "ACC1:acc#158" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {ACC1:acc#158.itm(3)} -pin  "ACC1:acc#158" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load inst "ACC1-1:not#2" "not(1)" "INTERFACE" -attr xrf 18685 -attr oid 831 -attr @path {/sobel/sobel:core/ACC1-1:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#3.sva(3)} -pin  "ACC1-1:not#2" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#24.itm}
+load net {ACC1-1:not#2.itm} -pin  "ACC1-1:not#2" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#2.itm}
+load inst "ACC1:acc#157" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18686 -attr oid 832 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#157} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#157" {A(0)} -attr @path {/sobel/sobel:core/conc#354.itm}
+load net {acc.idiv#3.sva(2)} -pin  "ACC1:acc#157" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#354.itm}
+load net {acc.idiv#3.sva(12)} -pin  "ACC1:acc#157" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#297.itm}
+load net {ACC1-1:not#2.itm} -pin  "ACC1:acc#157" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#297.itm}
+load net {ACC1:acc#157.itm(0)} -pin  "ACC1:acc#157" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load net {ACC1:acc#157.itm(1)} -pin  "ACC1:acc#157" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load net {ACC1:acc#157.itm(2)} -pin  "ACC1:acc#157" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load inst "ACC1-1:not#8" "not(1)" "INTERFACE" -attr xrf 18687 -attr oid 833 -attr @path {/sobel/sobel:core/ACC1-1:not#8} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#3.sva(15)} -pin  "ACC1-1:not#8" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#21.itm}
+load net {ACC1-1:not#8.itm} -pin  "ACC1-1:not#8" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#8.itm}
+load inst "ACC1:acc#160" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 18688 -attr oid 834 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#160} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {PWR} -pin  "ACC1:acc#160" {A(0)} -attr @path {/sobel/sobel:core/conc#350.itm}
+load net {ACC1:acc#158.itm(1)} -pin  "ACC1:acc#160" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#350.itm}
+load net {ACC1:acc#158.itm(2)} -pin  "ACC1:acc#160" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#350.itm}
+load net {ACC1:acc#158.itm(3)} -pin  "ACC1:acc#160" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#350.itm}
+load net {ACC1-1:not#8.itm} -pin  "ACC1:acc#160" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#303.itm}
+load net {ACC1:acc#157.itm(1)} -pin  "ACC1:acc#160" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#303.itm}
+load net {ACC1:acc#157.itm(2)} -pin  "ACC1:acc#160" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#303.itm}
+load net {ACC1:acc#160.itm(0)} -pin  "ACC1:acc#160" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load net {ACC1:acc#160.itm(1)} -pin  "ACC1:acc#160" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load net {ACC1:acc#160.itm(2)} -pin  "ACC1:acc#160" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load net {ACC1:acc#160.itm(3)} -pin  "ACC1:acc#160" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load net {ACC1:acc#160.itm(4)} -pin  "ACC1:acc#160" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load inst "ACC1-1:not#3" "not(1)" "INTERFACE" -attr xrf 18689 -attr oid 835 -attr @path {/sobel/sobel:core/ACC1-1:not#3} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#3.sva(5)} -pin  "ACC1-1:not#3" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#3.itm}
+load net {ACC1-1:not#3.itm} -pin  "ACC1-1:not#3" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#3.itm}
+load inst "ACC1-1:not#6" "not(1)" "INTERFACE" -attr xrf 18690 -attr oid 836 -attr @path {/sobel/sobel:core/ACC1-1:not#6} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#3.sva(11)} -pin  "ACC1-1:not#6" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#5.itm}
+load net {ACC1-1:not#6.itm} -pin  "ACC1-1:not#6" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#6.itm}
+load inst "ACC1:acc#156" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18691 -attr oid 837 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#156" {A(0)} -attr @path {/sobel/sobel:core/conc#356.itm}
+load net {acc.idiv#3.sva(4)} -pin  "ACC1:acc#156" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#356.itm}
+load net {ACC1-1:not#6.itm} -pin  "ACC1:acc#156" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#295.itm}
+load net {ACC1-1:not#3.itm} -pin  "ACC1:acc#156" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#295.itm}
+load net {ACC1:acc#156.itm(0)} -pin  "ACC1:acc#156" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load net {ACC1:acc#156.itm(1)} -pin  "ACC1:acc#156" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load net {ACC1:acc#156.itm(2)} -pin  "ACC1:acc#156" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load inst "ACC1-1:not#4" "not(1)" "INTERFACE" -attr xrf 18692 -attr oid 838 -attr @path {/sobel/sobel:core/ACC1-1:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#3.sva(7)} -pin  "ACC1-1:not#4" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#2.itm}
+load net {ACC1-1:not#4.itm} -pin  "ACC1-1:not#4" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#4.itm}
+load inst "ACC1:acc#155" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18693 -attr oid 839 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#155} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#155" {A(0)} -attr @path {/sobel/sobel:core/conc#357.itm}
+load net {acc.idiv#3.sva(6)} -pin  "ACC1:acc#155" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#357.itm}
+load net {acc.idiv#3.sva(10)} -pin  "ACC1:acc#155" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#293.itm}
+load net {ACC1-1:not#4.itm} -pin  "ACC1:acc#155" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#293.itm}
+load net {ACC1:acc#155.itm(0)} -pin  "ACC1:acc#155" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#155.itm}
+load net {ACC1:acc#155.itm(1)} -pin  "ACC1:acc#155" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#155.itm}
+load net {ACC1:acc#155.itm(2)} -pin  "ACC1:acc#155" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#155.itm}
+load inst "ACC1:acc#159" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18694 -attr oid 840 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#159} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#159" {A(0)} -attr @path {/sobel/sobel:core/conc#355.itm}
+load net {ACC1:acc#156.itm(1)} -pin  "ACC1:acc#159" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#355.itm}
+load net {ACC1:acc#156.itm(2)} -pin  "ACC1:acc#159" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#355.itm}
+load net {acc.idiv#3.sva(14)} -pin  "ACC1:acc#159" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#301.itm}
+load net {ACC1:acc#155.itm(1)} -pin  "ACC1:acc#159" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#301.itm}
+load net {ACC1:acc#155.itm(2)} -pin  "ACC1:acc#159" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#301.itm}
+load net {ACC1:acc#159.itm(0)} -pin  "ACC1:acc#159" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#159.itm}
+load net {ACC1:acc#159.itm(1)} -pin  "ACC1:acc#159" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#159.itm}
+load net {ACC1:acc#159.itm(2)} -pin  "ACC1:acc#159" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#159.itm}
+load net {ACC1:acc#159.itm(3)} -pin  "ACC1:acc#159" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#159.itm}
+load inst "ACC1:acc#161" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 18695 -attr oid 841 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#161} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {PWR} -pin  "ACC1:acc#161" {A(0)} -attr @path {/sobel/sobel:core/conc#349.itm}
+load net {ACC1:acc#160.itm(1)} -pin  "ACC1:acc#161" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#349.itm}
+load net {ACC1:acc#160.itm(2)} -pin  "ACC1:acc#161" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#349.itm}
+load net {ACC1:acc#160.itm(3)} -pin  "ACC1:acc#161" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#349.itm}
+load net {ACC1:acc#160.itm(4)} -pin  "ACC1:acc#161" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#349.itm}
+load net {acc.idiv#3.sva(16)} -pin  "ACC1:acc#161" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#305.itm}
+load net {ACC1:acc#159.itm(1)} -pin  "ACC1:acc#161" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#305.itm}
+load net {ACC1:acc#159.itm(2)} -pin  "ACC1:acc#161" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#305.itm}
+load net {ACC1:acc#159.itm(3)} -pin  "ACC1:acc#161" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#305.itm}
+load net {ACC1:acc#161.itm(0)} -pin  "ACC1:acc#161" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load net {ACC1:acc#161.itm(1)} -pin  "ACC1:acc#161" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load net {ACC1:acc#161.itm(2)} -pin  "ACC1:acc#161" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load net {ACC1:acc#161.itm(3)} -pin  "ACC1:acc#161" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load net {ACC1:acc#161.itm(4)} -pin  "ACC1:acc#161" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load net {ACC1:acc#161.itm(5)} -pin  "ACC1:acc#161" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load inst "ACC1-1:not#9" "not(1)" "INTERFACE" -attr xrf 18696 -attr oid 842 -attr @path {/sobel/sobel:core/ACC1-1:not#9} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#3.sva(17)} -pin  "ACC1-1:not#9" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#3.sva)#18.itm}
+load net {ACC1-1:not#9.itm} -pin  "ACC1-1:not#9" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#9.itm}
+load inst "ACC1:acc#162" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 18697 -attr oid 843 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {PWR} -pin  "ACC1:acc#162" {A(0)} -attr @path {/sobel/sobel:core/conc#348.itm}
+load net {ACC1:acc#161.itm(1)} -pin  "ACC1:acc#162" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#348.itm}
+load net {ACC1:acc#161.itm(2)} -pin  "ACC1:acc#162" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#348.itm}
+load net {ACC1:acc#161.itm(3)} -pin  "ACC1:acc#162" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#348.itm}
+load net {ACC1:acc#161.itm(4)} -pin  "ACC1:acc#162" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#348.itm}
+load net {ACC1:acc#161.itm(5)} -pin  "ACC1:acc#162" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#348.itm}
+load net {ACC1-1:not#9.itm} -pin  "ACC1:acc#162" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#358.itm}
+load net {acc.idiv#3.sva(0)} -pin  "ACC1:acc#162" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#358.itm}
+load net {PWR} -pin  "ACC1:acc#162" {B(2)} -attr @path {/sobel/sobel:core/conc#358.itm}
+load net {PWR} -pin  "ACC1:acc#162" {B(3)} -attr @path {/sobel/sobel:core/conc#358.itm}
+load net {GND} -pin  "ACC1:acc#162" {B(4)} -attr @path {/sobel/sobel:core/conc#358.itm}
+load net {PWR} -pin  "ACC1:acc#162" {B(5)} -attr @path {/sobel/sobel:core/conc#358.itm}
+load net {ACC1:acc#162.itm(0)} -pin  "ACC1:acc#162" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(1)} -pin  "ACC1:acc#162" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(2)} -pin  "ACC1:acc#162" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(3)} -pin  "ACC1:acc#162" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(4)} -pin  "ACC1:acc#162" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(5)} -pin  "ACC1:acc#162" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load inst "ACC1-1:not#11" "not(1)" "INTERFACE" -attr xrf 18698 -attr oid 844 -attr @path {/sobel/sobel:core/ACC1-1:not#11} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#162.itm(4)} -pin  "ACC1-1:not#11" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#17.sva)#4.itm}
+load net {ACC1-1:not#11.itm} -pin  "ACC1-1:not#11" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#11.itm}
+load inst "ACC1:acc#163" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18699 -attr oid 845 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#163" {A(0)} -attr @path {/sobel/sobel:core/conc#360.itm}
+load net {ACC1:acc#162.itm(3)} -pin  "ACC1:acc#163" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#360.itm}
+load net {PWR} -pin  "ACC1:acc#163" {B(0)} -attr @path {/sobel/sobel:core/conc#361.itm}
+load net {ACC1-1:not#11.itm} -pin  "ACC1:acc#163" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#361.itm}
+load net {ACC1:acc#163.itm(0)} -pin  "ACC1:acc#163" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163.itm}
+load net {ACC1:acc#163.itm(1)} -pin  "ACC1:acc#163" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163.itm}
+load net {ACC1:acc#163.itm(2)} -pin  "ACC1:acc#163" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163.itm}
+load inst "ACC1-1:not#10" "not(1)" "INTERFACE" -attr xrf 18700 -attr oid 846 -attr @path {/sobel/sobel:core/ACC1-1:not#10} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#162.itm(2)} -pin  "ACC1-1:not#10" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#17.sva)#5.itm}
+load net {ACC1-1:not#10.itm} -pin  "ACC1-1:not#10" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#10.itm}
+load inst "ACC1-1:not#12" "not(1)" "INTERFACE" -attr xrf 18701 -attr oid 847 -attr @path {/sobel/sobel:core/ACC1-1:not#12} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#162.itm(5)} -pin  "ACC1-1:not#12" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#17.sva)#6.itm}
+load net {ACC1-1:not#12.itm} -pin  "ACC1-1:not#12" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#12.itm}
+load inst "ACC1:acc#164" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 18702 -attr oid 848 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#164" {A(0)} -attr @path {/sobel/sobel:core/conc#359.itm}
+load net {ACC1:acc#163.itm(1)} -pin  "ACC1:acc#164" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#359.itm}
+load net {ACC1:acc#163.itm(2)} -pin  "ACC1:acc#164" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#359.itm}
+load net {ACC1-1:not#12.itm} -pin  "ACC1:acc#164" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#312.itm}
+load net {ACC1-1:not#10.itm} -pin  "ACC1:acc#164" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#312.itm}
+load net {ACC1:acc#164.itm(0)} -pin  "ACC1:acc#164" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164.itm}
+load net {ACC1:acc#164.itm(1)} -pin  "ACC1:acc#164" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164.itm}
+load net {ACC1:acc#164.itm(2)} -pin  "ACC1:acc#164" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164.itm}
+load net {ACC1:acc#164.itm(3)} -pin  "ACC1:acc#164" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164.itm}
+load inst "ACC1-1:acc#5" "add(3,-1,3,-1,3)" "INTERFACE" -attr xrf 18703 -attr oid 849 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#5} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#164.itm(1)} -pin  "ACC1-1:acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#15.itm}
+load net {ACC1:acc#164.itm(2)} -pin  "ACC1-1:acc#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#15.itm}
+load net {ACC1:acc#164.itm(3)} -pin  "ACC1-1:acc#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#15.itm}
+load net {ACC1:acc#162.itm(1)} -pin  "ACC1-1:acc#5" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#362.itm}
+load net {GND} -pin  "ACC1-1:acc#5" {B(1)} -attr @path {/sobel/sobel:core/conc#362.itm}
+load net {PWR} -pin  "ACC1-1:acc#5" {B(2)} -attr @path {/sobel/sobel:core/conc#362.itm}
+load net {acc.imod#19.sva(0)} -pin  "ACC1-1:acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#19.sva}
+load net {acc.imod#19.sva(1)} -pin  "ACC1-1:acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#19.sva}
+load net {acc.imod#19.sva(2)} -pin  "ACC1-1:acc#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#19.sva}
+load inst "ACC1-3:not#41" "not(1)" "INTERFACE" -attr xrf 18704 -attr oid 850 -attr @path {/sobel/sobel:core/ACC1-3:not#41} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#2.sva(9)} -pin  "ACC1-3:not#41" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#5.itm}
+load net {ACC1-3:not#41.itm} -pin  "ACC1-3:not#41" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#41.itm}
+load inst "ACC1:acc#193" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18705 -attr oid 851 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#193" {A(0)} -attr @path {/sobel/sobel:core/conc#367.itm}
+load net {acc.idiv#2.sva(8)} -pin  "ACC1:acc#193" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#367.itm}
+load net {PWR} -pin  "ACC1:acc#193" {B(0)} -attr @path {/sobel/sobel:core/conc#368.itm}
+load net {ACC1-3:not#41.itm} -pin  "ACC1:acc#193" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#368.itm}
+load net {ACC1:acc#193.itm(0)} -pin  "ACC1:acc#193" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load net {ACC1:acc#193.itm(1)} -pin  "ACC1:acc#193" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load net {ACC1:acc#193.itm(2)} -pin  "ACC1:acc#193" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load inst "ACC1-3:not#37" "not(1)" "INTERFACE" -attr xrf 18706 -attr oid 852 -attr @path {/sobel/sobel:core/ACC1-3:not#37} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#2.sva(1)} -pin  "ACC1-3:not#37" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#14.itm}
+load net {ACC1-3:not#37.itm} -pin  "ACC1-3:not#37" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#37.itm}
+load inst "ACC1-3:not#43" "not(1)" "INTERFACE" -attr xrf 18707 -attr oid 853 -attr @path {/sobel/sobel:core/ACC1-3:not#43} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#2.sva(13)} -pin  "ACC1-3:not#43" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#11.itm}
+load net {ACC1-3:not#43.itm} -pin  "ACC1-3:not#43" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#43.itm}
+load inst "ACC1:acc#197" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 18708 -attr oid 854 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#197" {A(0)} -attr @path {/sobel/sobel:core/conc#366.itm}
+load net {ACC1:acc#193.itm(1)} -pin  "ACC1:acc#197" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#366.itm}
+load net {ACC1:acc#193.itm(2)} -pin  "ACC1:acc#197" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#366.itm}
+load net {ACC1-3:not#43.itm} -pin  "ACC1:acc#197" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#377.itm}
+load net {ACC1-3:not#37.itm} -pin  "ACC1:acc#197" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#377.itm}
+load net {ACC1:acc#197.itm(0)} -pin  "ACC1:acc#197" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.itm}
+load net {ACC1:acc#197.itm(1)} -pin  "ACC1:acc#197" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.itm}
+load net {ACC1:acc#197.itm(2)} -pin  "ACC1:acc#197" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.itm}
+load net {ACC1:acc#197.itm(3)} -pin  "ACC1:acc#197" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.itm}
+load inst "ACC1-3:not#38" "not(1)" "INTERFACE" -attr xrf 18709 -attr oid 855 -attr @path {/sobel/sobel:core/ACC1-3:not#38} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#2.sva(3)} -pin  "ACC1-3:not#38" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#9.itm}
+load net {ACC1-3:not#38.itm} -pin  "ACC1-3:not#38" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#38.itm}
+load inst "ACC1:acc#196" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18710 -attr oid 856 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#196} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#196" {A(0)} -attr @path {/sobel/sobel:core/conc#369.itm}
+load net {acc.idiv#2.sva(2)} -pin  "ACC1:acc#196" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#369.itm}
+load net {acc.idiv#2.sva(12)} -pin  "ACC1:acc#196" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#375.itm}
+load net {ACC1-3:not#38.itm} -pin  "ACC1:acc#196" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#375.itm}
+load net {ACC1:acc#196.itm(0)} -pin  "ACC1:acc#196" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#196.itm}
+load net {ACC1:acc#196.itm(1)} -pin  "ACC1:acc#196" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#196.itm}
+load net {ACC1:acc#196.itm(2)} -pin  "ACC1:acc#196" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#196.itm}
+load inst "ACC1-3:not#44" "not(1)" "INTERFACE" -attr xrf 18711 -attr oid 857 -attr @path {/sobel/sobel:core/ACC1-3:not#44} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#2.sva(15)} -pin  "ACC1-3:not#44" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#12.itm}
+load net {ACC1-3:not#44.itm} -pin  "ACC1-3:not#44" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#44.itm}
+load inst "ACC1:acc#199" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 18712 -attr oid 858 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {PWR} -pin  "ACC1:acc#199" {A(0)} -attr @path {/sobel/sobel:core/conc#365.itm}
+load net {ACC1:acc#197.itm(1)} -pin  "ACC1:acc#199" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#365.itm}
+load net {ACC1:acc#197.itm(2)} -pin  "ACC1:acc#199" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#365.itm}
+load net {ACC1:acc#197.itm(3)} -pin  "ACC1:acc#199" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#365.itm}
+load net {ACC1-3:not#44.itm} -pin  "ACC1:acc#199" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#381.itm}
+load net {ACC1:acc#196.itm(1)} -pin  "ACC1:acc#199" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#381.itm}
+load net {ACC1:acc#196.itm(2)} -pin  "ACC1:acc#199" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#381.itm}
+load net {ACC1:acc#199.itm(0)} -pin  "ACC1:acc#199" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(1)} -pin  "ACC1:acc#199" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(2)} -pin  "ACC1:acc#199" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(3)} -pin  "ACC1:acc#199" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(4)} -pin  "ACC1:acc#199" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load inst "ACC1-3:not#39" "not(1)" "INTERFACE" -attr xrf 18713 -attr oid 859 -attr @path {/sobel/sobel:core/ACC1-3:not#39} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#2.sva(5)} -pin  "ACC1-3:not#39" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#18.itm}
+load net {ACC1-3:not#39.itm} -pin  "ACC1-3:not#39" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#39.itm}
+load inst "ACC1-3:not#42" "not(1)" "INTERFACE" -attr xrf 18714 -attr oid 860 -attr @path {/sobel/sobel:core/ACC1-3:not#42} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#2.sva(11)} -pin  "ACC1-3:not#42" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#10.itm}
+load net {ACC1-3:not#42.itm} -pin  "ACC1-3:not#42" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#42.itm}
+load inst "ACC1:acc#195" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18715 -attr oid 861 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#195" {A(0)} -attr @path {/sobel/sobel:core/conc#371.itm}
+load net {acc.idiv#2.sva(4)} -pin  "ACC1:acc#195" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#371.itm}
+load net {ACC1-3:not#42.itm} -pin  "ACC1:acc#195" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#373.itm}
+load net {ACC1-3:not#39.itm} -pin  "ACC1:acc#195" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#373.itm}
+load net {ACC1:acc#195.itm(0)} -pin  "ACC1:acc#195" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load net {ACC1:acc#195.itm(1)} -pin  "ACC1:acc#195" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load net {ACC1:acc#195.itm(2)} -pin  "ACC1:acc#195" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load inst "ACC1-3:not#40" "not(1)" "INTERFACE" -attr xrf 18716 -attr oid 862 -attr @path {/sobel/sobel:core/ACC1-3:not#40} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#2.sva(7)} -pin  "ACC1-3:not#40" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva).itm}
+load net {ACC1-3:not#40.itm} -pin  "ACC1-3:not#40" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#40.itm}
+load inst "ACC1:acc#194" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18717 -attr oid 863 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#194" {A(0)} -attr @path {/sobel/sobel:core/conc#372.itm}
+load net {acc.idiv#2.sva(6)} -pin  "ACC1:acc#194" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#372.itm}
+load net {acc.idiv#2.sva(10)} -pin  "ACC1:acc#194" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#371.itm}
+load net {ACC1-3:not#40.itm} -pin  "ACC1:acc#194" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#371.itm}
+load net {ACC1:acc#194.itm(0)} -pin  "ACC1:acc#194" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load net {ACC1:acc#194.itm(1)} -pin  "ACC1:acc#194" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load net {ACC1:acc#194.itm(2)} -pin  "ACC1:acc#194" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load inst "ACC1:acc#198" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18718 -attr oid 864 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#198" {A(0)} -attr @path {/sobel/sobel:core/conc#370.itm}
+load net {ACC1:acc#195.itm(1)} -pin  "ACC1:acc#198" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#370.itm}
+load net {ACC1:acc#195.itm(2)} -pin  "ACC1:acc#198" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#370.itm}
+load net {acc.idiv#2.sva(14)} -pin  "ACC1:acc#198" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#379.itm}
+load net {ACC1:acc#194.itm(1)} -pin  "ACC1:acc#198" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#379.itm}
+load net {ACC1:acc#194.itm(2)} -pin  "ACC1:acc#198" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#379.itm}
+load net {ACC1:acc#198.itm(0)} -pin  "ACC1:acc#198" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:acc#198.itm(1)} -pin  "ACC1:acc#198" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:acc#198.itm(2)} -pin  "ACC1:acc#198" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:acc#198.itm(3)} -pin  "ACC1:acc#198" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load inst "ACC1:acc#200" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 18719 -attr oid 865 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {PWR} -pin  "ACC1:acc#200" {A(0)} -attr @path {/sobel/sobel:core/conc#364.itm}
+load net {ACC1:acc#199.itm(1)} -pin  "ACC1:acc#200" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#364.itm}
+load net {ACC1:acc#199.itm(2)} -pin  "ACC1:acc#200" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#364.itm}
+load net {ACC1:acc#199.itm(3)} -pin  "ACC1:acc#200" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#364.itm}
+load net {ACC1:acc#199.itm(4)} -pin  "ACC1:acc#200" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#364.itm}
+load net {acc.idiv#2.sva(16)} -pin  "ACC1:acc#200" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#383.itm}
+load net {ACC1:acc#198.itm(1)} -pin  "ACC1:acc#200" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#383.itm}
+load net {ACC1:acc#198.itm(2)} -pin  "ACC1:acc#200" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#383.itm}
+load net {ACC1:acc#198.itm(3)} -pin  "ACC1:acc#200" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#383.itm}
+load net {ACC1:acc#200.itm(0)} -pin  "ACC1:acc#200" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(1)} -pin  "ACC1:acc#200" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(2)} -pin  "ACC1:acc#200" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(3)} -pin  "ACC1:acc#200" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(4)} -pin  "ACC1:acc#200" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(5)} -pin  "ACC1:acc#200" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load inst "ACC1-3:not#45" "not(1)" "INTERFACE" -attr xrf 18720 -attr oid 866 -attr @path {/sobel/sobel:core/ACC1-3:not#45} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#2.sva(17)} -pin  "ACC1-3:not#45" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#2.sva)#13.itm}
+load net {ACC1-3:not#45.itm} -pin  "ACC1-3:not#45" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#45.itm}
+load inst "ACC1:acc#201" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 18721 -attr oid 867 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {PWR} -pin  "ACC1:acc#201" {A(0)} -attr @path {/sobel/sobel:core/conc#363.itm}
+load net {ACC1:acc#200.itm(1)} -pin  "ACC1:acc#201" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#363.itm}
+load net {ACC1:acc#200.itm(2)} -pin  "ACC1:acc#201" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#363.itm}
+load net {ACC1:acc#200.itm(3)} -pin  "ACC1:acc#201" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#363.itm}
+load net {ACC1:acc#200.itm(4)} -pin  "ACC1:acc#201" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#363.itm}
+load net {ACC1:acc#200.itm(5)} -pin  "ACC1:acc#201" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#363.itm}
+load net {ACC1-3:not#45.itm} -pin  "ACC1:acc#201" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#373.itm}
+load net {acc.idiv#2.sva(0)} -pin  "ACC1:acc#201" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#373.itm}
+load net {PWR} -pin  "ACC1:acc#201" {B(2)} -attr @path {/sobel/sobel:core/conc#373.itm}
+load net {PWR} -pin  "ACC1:acc#201" {B(3)} -attr @path {/sobel/sobel:core/conc#373.itm}
+load net {GND} -pin  "ACC1:acc#201" {B(4)} -attr @path {/sobel/sobel:core/conc#373.itm}
+load net {PWR} -pin  "ACC1:acc#201" {B(5)} -attr @path {/sobel/sobel:core/conc#373.itm}
+load net {ACC1:acc#201.itm(0)} -pin  "ACC1:acc#201" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(1)} -pin  "ACC1:acc#201" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(2)} -pin  "ACC1:acc#201" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(3)} -pin  "ACC1:acc#201" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(4)} -pin  "ACC1:acc#201" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(5)} -pin  "ACC1:acc#201" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load inst "ACC1-1:not#41" "not(1)" "INTERFACE" -attr xrf 18722 -attr oid 868 -attr @path {/sobel/sobel:core/ACC1-1:not#41} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#7.sva(9)} -pin  "ACC1-1:not#41" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#1.itm}
+load net {ACC1-1:not#41.itm} -pin  "ACC1-1:not#41" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#41.itm}
+load inst "ACC1:acc#166" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18723 -attr oid 869 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#166" {A(0)} -attr @path {/sobel/sobel:core/conc#378.itm}
+load net {acc.idiv#7.sva(8)} -pin  "ACC1:acc#166" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#378.itm}
+load net {PWR} -pin  "ACC1:acc#166" {B(0)} -attr @path {/sobel/sobel:core/conc#379.itm}
+load net {ACC1-1:not#41.itm} -pin  "ACC1:acc#166" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#379.itm}
+load net {ACC1:acc#166.itm(0)} -pin  "ACC1:acc#166" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load net {ACC1:acc#166.itm(1)} -pin  "ACC1:acc#166" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load net {ACC1:acc#166.itm(2)} -pin  "ACC1:acc#166" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load inst "ACC1-1:not#37" "not(1)" "INTERFACE" -attr xrf 18724 -attr oid 870 -attr @path {/sobel/sobel:core/ACC1-1:not#37} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#7.sva(1)} -pin  "ACC1-1:not#37" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#6.itm}
+load net {ACC1-1:not#37.itm} -pin  "ACC1-1:not#37" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#37.itm}
+load inst "ACC1-1:not#43" "not(1)" "INTERFACE" -attr xrf 18725 -attr oid 871 -attr @path {/sobel/sobel:core/ACC1-1:not#43} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#7.sva(13)} -pin  "ACC1-1:not#43" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#10.itm}
+load net {ACC1-1:not#43.itm} -pin  "ACC1-1:not#43" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#43.itm}
+load inst "ACC1:acc#170" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 18726 -attr oid 872 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#170" {A(0)} -attr @path {/sobel/sobel:core/conc#377.itm}
+load net {ACC1:acc#166.itm(1)} -pin  "ACC1:acc#170" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#377.itm}
+load net {ACC1:acc#166.itm(2)} -pin  "ACC1:acc#170" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#377.itm}
+load net {ACC1-1:not#43.itm} -pin  "ACC1:acc#170" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#323.itm}
+load net {ACC1-1:not#37.itm} -pin  "ACC1:acc#170" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#323.itm}
+load net {ACC1:acc#170.itm(0)} -pin  "ACC1:acc#170" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170.itm}
+load net {ACC1:acc#170.itm(1)} -pin  "ACC1:acc#170" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170.itm}
+load net {ACC1:acc#170.itm(2)} -pin  "ACC1:acc#170" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170.itm}
+load net {ACC1:acc#170.itm(3)} -pin  "ACC1:acc#170" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170.itm}
+load inst "ACC1-1:not#38" "not(1)" "INTERFACE" -attr xrf 18727 -attr oid 873 -attr @path {/sobel/sobel:core/ACC1-1:not#38} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#7.sva(3)} -pin  "ACC1-1:not#38" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#8.itm}
+load net {ACC1-1:not#38.itm} -pin  "ACC1-1:not#38" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#38.itm}
+load inst "ACC1:acc#169" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18728 -attr oid 874 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#169" {A(0)} -attr @path {/sobel/sobel:core/conc#380.itm}
+load net {acc.idiv#7.sva(2)} -pin  "ACC1:acc#169" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#380.itm}
+load net {acc.idiv#7.sva(12)} -pin  "ACC1:acc#169" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#321.itm}
+load net {ACC1-1:not#38.itm} -pin  "ACC1:acc#169" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#321.itm}
+load net {ACC1:acc#169.itm(0)} -pin  "ACC1:acc#169" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load net {ACC1:acc#169.itm(1)} -pin  "ACC1:acc#169" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load net {ACC1:acc#169.itm(2)} -pin  "ACC1:acc#169" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load inst "ACC1-1:not#44" "not(1)" "INTERFACE" -attr xrf 18729 -attr oid 875 -attr @path {/sobel/sobel:core/ACC1-1:not#44} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#7.sva(15)} -pin  "ACC1-1:not#44" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#13.itm}
+load net {ACC1-1:not#44.itm} -pin  "ACC1-1:not#44" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#44.itm}
+load inst "ACC1:acc#172" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 18730 -attr oid 876 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {PWR} -pin  "ACC1:acc#172" {A(0)} -attr @path {/sobel/sobel:core/conc#376.itm}
+load net {ACC1:acc#170.itm(1)} -pin  "ACC1:acc#172" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#376.itm}
+load net {ACC1:acc#170.itm(2)} -pin  "ACC1:acc#172" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#376.itm}
+load net {ACC1:acc#170.itm(3)} -pin  "ACC1:acc#172" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#376.itm}
+load net {ACC1-1:not#44.itm} -pin  "ACC1:acc#172" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#327.itm}
+load net {ACC1:acc#169.itm(1)} -pin  "ACC1:acc#172" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#327.itm}
+load net {ACC1:acc#169.itm(2)} -pin  "ACC1:acc#172" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#327.itm}
+load net {ACC1:acc#172.itm(0)} -pin  "ACC1:acc#172" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load net {ACC1:acc#172.itm(1)} -pin  "ACC1:acc#172" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load net {ACC1:acc#172.itm(2)} -pin  "ACC1:acc#172" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load net {ACC1:acc#172.itm(3)} -pin  "ACC1:acc#172" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load net {ACC1:acc#172.itm(4)} -pin  "ACC1:acc#172" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load inst "ACC1-1:not#39" "not(1)" "INTERFACE" -attr xrf 18731 -attr oid 877 -attr @path {/sobel/sobel:core/ACC1-1:not#39} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#7.sva(5)} -pin  "ACC1-1:not#39" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#5.itm}
+load net {ACC1-1:not#39.itm} -pin  "ACC1-1:not#39" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#39.itm}
+load inst "ACC1-1:not#42" "not(1)" "INTERFACE" -attr xrf 18732 -attr oid 878 -attr @path {/sobel/sobel:core/ACC1-1:not#42} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#7.sva(11)} -pin  "ACC1-1:not#42" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#9.itm}
+load net {ACC1-1:not#42.itm} -pin  "ACC1-1:not#42" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#42.itm}
+load inst "ACC1:acc#168" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18733 -attr oid 879 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#168" {A(0)} -attr @path {/sobel/sobel:core/conc#382.itm}
+load net {acc.idiv#7.sva(4)} -pin  "ACC1:acc#168" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#382.itm}
+load net {ACC1-1:not#42.itm} -pin  "ACC1:acc#168" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#319.itm}
+load net {ACC1-1:not#39.itm} -pin  "ACC1:acc#168" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#319.itm}
+load net {ACC1:acc#168.itm(0)} -pin  "ACC1:acc#168" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168.itm}
+load net {ACC1:acc#168.itm(1)} -pin  "ACC1:acc#168" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168.itm}
+load net {ACC1:acc#168.itm(2)} -pin  "ACC1:acc#168" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168.itm}
+load inst "ACC1-1:not#40" "not(1)" "INTERFACE" -attr xrf 18734 -attr oid 880 -attr @path {/sobel/sobel:core/ACC1-1:not#40} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#7.sva(7)} -pin  "ACC1-1:not#40" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#2.itm}
+load net {ACC1-1:not#40.itm} -pin  "ACC1-1:not#40" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#40.itm}
+load inst "ACC1:acc#167" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18735 -attr oid 881 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#167" {A(0)} -attr @path {/sobel/sobel:core/conc#383.itm}
+load net {acc.idiv#7.sva(6)} -pin  "ACC1:acc#167" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#383.itm}
+load net {acc.idiv#7.sva(10)} -pin  "ACC1:acc#167" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#317.itm}
+load net {ACC1-1:not#40.itm} -pin  "ACC1:acc#167" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#317.itm}
+load net {ACC1:acc#167.itm(0)} -pin  "ACC1:acc#167" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load net {ACC1:acc#167.itm(1)} -pin  "ACC1:acc#167" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load net {ACC1:acc#167.itm(2)} -pin  "ACC1:acc#167" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load inst "ACC1:acc#171" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18736 -attr oid 882 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#171" {A(0)} -attr @path {/sobel/sobel:core/conc#381.itm}
+load net {ACC1:acc#168.itm(1)} -pin  "ACC1:acc#171" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#381.itm}
+load net {ACC1:acc#168.itm(2)} -pin  "ACC1:acc#171" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#381.itm}
+load net {acc.idiv#7.sva(14)} -pin  "ACC1:acc#171" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#325.itm}
+load net {ACC1:acc#167.itm(1)} -pin  "ACC1:acc#171" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#325.itm}
+load net {ACC1:acc#167.itm(2)} -pin  "ACC1:acc#171" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#325.itm}
+load net {ACC1:acc#171.itm(0)} -pin  "ACC1:acc#171" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(1)} -pin  "ACC1:acc#171" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(2)} -pin  "ACC1:acc#171" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(3)} -pin  "ACC1:acc#171" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load inst "ACC1:acc#173" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 18737 -attr oid 883 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {PWR} -pin  "ACC1:acc#173" {A(0)} -attr @path {/sobel/sobel:core/conc#375.itm}
+load net {ACC1:acc#172.itm(1)} -pin  "ACC1:acc#173" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#375.itm}
+load net {ACC1:acc#172.itm(2)} -pin  "ACC1:acc#173" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#375.itm}
+load net {ACC1:acc#172.itm(3)} -pin  "ACC1:acc#173" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#375.itm}
+load net {ACC1:acc#172.itm(4)} -pin  "ACC1:acc#173" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#375.itm}
+load net {acc.idiv#7.sva(16)} -pin  "ACC1:acc#173" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#329.itm}
+load net {ACC1:acc#171.itm(1)} -pin  "ACC1:acc#173" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#329.itm}
+load net {ACC1:acc#171.itm(2)} -pin  "ACC1:acc#173" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#329.itm}
+load net {ACC1:acc#171.itm(3)} -pin  "ACC1:acc#173" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#329.itm}
+load net {ACC1:acc#173.itm(0)} -pin  "ACC1:acc#173" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load net {ACC1:acc#173.itm(1)} -pin  "ACC1:acc#173" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load net {ACC1:acc#173.itm(2)} -pin  "ACC1:acc#173" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load net {ACC1:acc#173.itm(3)} -pin  "ACC1:acc#173" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load net {ACC1:acc#173.itm(4)} -pin  "ACC1:acc#173" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load net {ACC1:acc#173.itm(5)} -pin  "ACC1:acc#173" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load inst "ACC1-1:not#45" "not(1)" "INTERFACE" -attr xrf 18738 -attr oid 884 -attr @path {/sobel/sobel:core/ACC1-1:not#45} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.idiv#7.sva(17)} -pin  "ACC1-1:not#45" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.idiv#7.sva)#12.itm}
+load net {ACC1-1:not#45.itm} -pin  "ACC1-1:not#45" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#45.itm}
+load inst "ACC1:acc#174" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 18739 -attr oid 885 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {PWR} -pin  "ACC1:acc#174" {A(0)} -attr @path {/sobel/sobel:core/conc#374.itm}
+load net {ACC1:acc#173.itm(1)} -pin  "ACC1:acc#174" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#374.itm}
+load net {ACC1:acc#173.itm(2)} -pin  "ACC1:acc#174" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#374.itm}
+load net {ACC1:acc#173.itm(3)} -pin  "ACC1:acc#174" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#374.itm}
+load net {ACC1:acc#173.itm(4)} -pin  "ACC1:acc#174" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#374.itm}
+load net {ACC1:acc#173.itm(5)} -pin  "ACC1:acc#174" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#374.itm}
+load net {ACC1-1:not#45.itm} -pin  "ACC1:acc#174" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#384.itm}
+load net {acc.idiv#7.sva(0)} -pin  "ACC1:acc#174" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#384.itm}
+load net {PWR} -pin  "ACC1:acc#174" {B(2)} -attr @path {/sobel/sobel:core/conc#384.itm}
+load net {PWR} -pin  "ACC1:acc#174" {B(3)} -attr @path {/sobel/sobel:core/conc#384.itm}
+load net {GND} -pin  "ACC1:acc#174" {B(4)} -attr @path {/sobel/sobel:core/conc#384.itm}
+load net {PWR} -pin  "ACC1:acc#174" {B(5)} -attr @path {/sobel/sobel:core/conc#384.itm}
+load net {ACC1:acc#174.itm(0)} -pin  "ACC1:acc#174" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {ACC1:acc#174.itm(1)} -pin  "ACC1:acc#174" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {ACC1:acc#174.itm(2)} -pin  "ACC1:acc#174" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {ACC1:acc#174.itm(3)} -pin  "ACC1:acc#174" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {ACC1:acc#174.itm(4)} -pin  "ACC1:acc#174" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {ACC1:acc#174.itm(5)} -pin  "ACC1:acc#174" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load inst "ACC1-3:not#47" "not(1)" "INTERFACE" -attr xrf 18740 -attr oid 886 -attr @path {/sobel/sobel:core/ACC1-3:not#47} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#201.itm(4)} -pin  "ACC1-3:not#47" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#4.itm}
+load net {ACC1-3:not#47.itm} -pin  "ACC1-3:not#47" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#47.itm}
+load inst "ACC1:acc#202" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18741 -attr oid 887 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#202" {A(0)} -attr @path {/sobel/sobel:core/conc#386.itm}
+load net {ACC1:acc#201.itm(3)} -pin  "ACC1:acc#202" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#386.itm}
+load net {PWR} -pin  "ACC1:acc#202" {B(0)} -attr @path {/sobel/sobel:core/conc#387.itm}
+load net {ACC1-3:not#47.itm} -pin  "ACC1:acc#202" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#387.itm}
+load net {ACC1:acc#202.itm(0)} -pin  "ACC1:acc#202" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(1)} -pin  "ACC1:acc#202" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(2)} -pin  "ACC1:acc#202" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load inst "ACC1-3:not#46" "not(1)" "INTERFACE" -attr xrf 18742 -attr oid 888 -attr @path {/sobel/sobel:core/ACC1-3:not#46} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#201.itm(2)} -pin  "ACC1-3:not#46" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#5.itm}
+load net {ACC1-3:not#46.itm} -pin  "ACC1-3:not#46" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#46.itm}
+load inst "ACC1-3:not#48" "not(1)" "INTERFACE" -attr xrf 18743 -attr oid 889 -attr @path {/sobel/sobel:core/ACC1-3:not#48} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#201.itm(5)} -pin  "ACC1-3:not#48" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#6.itm}
+load net {ACC1-3:not#48.itm} -pin  "ACC1-3:not#48" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#48.itm}
+load inst "ACC1:acc#203" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 18744 -attr oid 890 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#203" {A(0)} -attr @path {/sobel/sobel:core/conc#385.itm}
+load net {ACC1:acc#202.itm(1)} -pin  "ACC1:acc#203" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#385.itm}
+load net {ACC1:acc#202.itm(2)} -pin  "ACC1:acc#203" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#385.itm}
+load net {ACC1-3:not#48.itm} -pin  "ACC1:acc#203" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#390.itm}
+load net {ACC1-3:not#46.itm} -pin  "ACC1:acc#203" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#390.itm}
+load net {ACC1:acc#203.itm(0)} -pin  "ACC1:acc#203" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(1)} -pin  "ACC1:acc#203" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(2)} -pin  "ACC1:acc#203" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(3)} -pin  "ACC1:acc#203" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load inst "ACC1-3:acc#28" "add(3,-1,3,-1,3)" "INTERFACE" -attr xrf 18745 -attr oid 891 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#28} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#203.itm(1)} -pin  "ACC1-3:acc#28" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#51.itm}
+load net {ACC1:acc#203.itm(2)} -pin  "ACC1-3:acc#28" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#51.itm}
+load net {ACC1:acc#203.itm(3)} -pin  "ACC1-3:acc#28" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#51.itm}
+load net {ACC1:acc#201.itm(1)} -pin  "ACC1-3:acc#28" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#388.itm}
+load net {GND} -pin  "ACC1-3:acc#28" {B(1)} -attr @path {/sobel/sobel:core/conc#388.itm}
+load net {PWR} -pin  "ACC1-3:acc#28" {B(2)} -attr @path {/sobel/sobel:core/conc#388.itm}
+load net {acc.imod#7.sva(0)} -pin  "ACC1-3:acc#28" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.sva}
+load net {acc.imod#7.sva(1)} -pin  "ACC1-3:acc#28" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.sva}
+load net {acc.imod#7.sva(2)} -pin  "ACC1-3:acc#28" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.sva}
+load inst "ACC1:not#141" "not(1)" "INTERFACE" -attr xrf 18746 -attr oid 892 -attr @path {/sobel/sobel:core/ACC1:not#141} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#174.itm(5)} -pin  "ACC1:not#141" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#25.sva).itm}
+load net {ACC1:not#141.itm} -pin  "ACC1:not#141" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#141.itm}
+load inst "ACC1:not#135" "not(1)" "INTERFACE" -attr xrf 18747 -attr oid 893 -attr @path {/sobel/sobel:core/ACC1:not#135} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#189.itm(5)} -pin  "ACC1:not#135" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#2.itm}
+load net {ACC1:not#135.itm} -pin  "ACC1:not#135" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#135.itm}
+load inst "ACC1:acc#205" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18748 -attr oid 894 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:not#135.itm} -pin  "ACC1:acc#205" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#270.itm}
+load net {ACC1:not#141.itm} -pin  "ACC1:acc#205" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#270.itm}
+load net {PWR} -pin  "ACC1:acc#205" {B(0)} -attr @path {/sobel/sobel:core/conc#389.itm}
+load net {acc.imod#27.sva(1)} -pin  "ACC1:acc#205" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#389.itm}
+load net {ACC1:acc#205.itm(0)} -pin  "ACC1:acc#205" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(1)} -pin  "ACC1:acc#205" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(2)} -pin  "ACC1:acc#205" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load inst "ACC1:not#123" "not(1)" "INTERFACE" -attr xrf 18749 -attr oid 895 -attr @path {/sobel/sobel:core/ACC1:not#123} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#27.sva(2)} -pin  "ACC1:not#123" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#27.sva)#1.itm}
+load net {ACC1:not#123.itm} -pin  "ACC1:not#123" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#123.itm}
+load inst "ACC1:not#124" "not(1)" "INTERFACE" -attr xrf 18750 -attr oid 896 -attr @path {/sobel/sobel:core/ACC1:not#124} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#1.sva(2)} -pin  "ACC1:not#124" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#1.sva)#1.itm}
+load net {ACC1:not#124.itm} -pin  "ACC1:not#124" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#124.itm}
+load inst "ACC1-1:not#49" "not(1)" "INTERFACE" -attr xrf 18751 -attr oid 897 -attr @path {/sobel/sobel:core/ACC1-1:not#49} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#27.sva(1)} -pin  "ACC1-1:not#49" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#27.sva).itm}
+load net {ACC1-1:not#49.itm} -pin  "ACC1-1:not#49" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#49.itm}
+load inst "ACC1-1:not#50" "not(1)" "INTERFACE" -attr xrf 18752 -attr oid 898 -attr @path {/sobel/sobel:core/ACC1-1:not#50} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#27.sva(2)} -pin  "ACC1-1:not#50" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#27.sva)#3.itm}
+load net {ACC1-1:not#50.itm} -pin  "ACC1-1:not#50" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#50.itm}
+load inst "ACC1:acc#283" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 18753 -attr oid 899 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#283" {A(0)} -attr @path {/sobel/sobel:core/conc#390.itm}
+load net {acc.imod#27.sva(0)} -pin  "ACC1:acc#283" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#390.itm}
+load net {PWR} -pin  "ACC1:acc#283" {A(2)} -attr @path {/sobel/sobel:core/conc#390.itm}
+load net {ACC1-1:not#50.itm} -pin  "ACC1:acc#283" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#397.itm}
+load net {ACC1-1:not#49.itm} -pin  "ACC1:acc#283" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#397.itm}
+load net {ACC1:acc#283.itm(0)} -pin  "ACC1:acc#283" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(1)} -pin  "ACC1:acc#283" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(2)} -pin  "ACC1:acc#283" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load inst "ACC1:not#125" "not(1)" "INTERFACE" -attr xrf 18754 -attr oid 900 -attr @path {/sobel/sobel:core/ACC1:not#125} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#283.itm(2)} -pin  "ACC1:not#125" {A(0)} -attr @path {/sobel/sobel:core/ACC1:slc#53.itm}
+load net {ACC1:not#125.itm} -pin  "ACC1:not#125" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#125.itm}
+load inst "ACC1-3:not#13" "not(1)" "INTERFACE" -attr xrf 18755 -attr oid 901 -attr @path {/sobel/sobel:core/ACC1-3:not#13} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#1.sva(1)} -pin  "ACC1-3:not#13" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#1.sva)#3.itm}
+load net {ACC1-3:not#13.itm} -pin  "ACC1-3:not#13" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#13.itm}
+load inst "ACC1-3:not#14" "not(1)" "INTERFACE" -attr xrf 18756 -attr oid 902 -attr @path {/sobel/sobel:core/ACC1-3:not#14} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#1.sva(2)} -pin  "ACC1-3:not#14" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#1.sva)#4.itm}
+load net {ACC1-3:not#14.itm} -pin  "ACC1-3:not#14" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#14.itm}
+load inst "ACC1:acc#284" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 18757 -attr oid 903 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#284} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#284" {A(0)} -attr @path {/sobel/sobel:core/conc#391.itm}
+load net {acc.imod#1.sva(0)} -pin  "ACC1:acc#284" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#391.itm}
+load net {PWR} -pin  "ACC1:acc#284" {A(2)} -attr @path {/sobel/sobel:core/conc#391.itm}
+load net {ACC1-3:not#14.itm} -pin  "ACC1:acc#284" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#400.itm}
+load net {ACC1-3:not#13.itm} -pin  "ACC1:acc#284" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#400.itm}
+load net {ACC1:acc#284.itm(0)} -pin  "ACC1:acc#284" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(1)} -pin  "ACC1:acc#284" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(2)} -pin  "ACC1:acc#284" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load inst "ACC1:not#126" "not(1)" "INTERFACE" -attr xrf 18758 -attr oid 904 -attr @path {/sobel/sobel:core/ACC1:not#126} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#284.itm(2)} -pin  "ACC1:not#126" {A(0)} -attr @path {/sobel/sobel:core/ACC1:slc#54.itm}
+load net {ACC1:not#126.itm} -pin  "ACC1:not#126" {Z(0)} -attr @path {/sobel/sobel:core/ACC1:not#126.itm}
+load inst "ACC1:acc#204" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18759 -attr oid 905 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:not#124.itm} -pin  "ACC1:acc#204" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#272.itm}
+load net {ACC1:not#123.itm} -pin  "ACC1:acc#204" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#272.itm}
+load net {ACC1:not#126.itm} -pin  "ACC1:acc#204" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#273.itm}
+load net {ACC1:not#125.itm} -pin  "ACC1:acc#204" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#273.itm}
+load net {ACC1:acc#204.itm(0)} -pin  "ACC1:acc#204" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(1)} -pin  "ACC1:acc#204" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(2)} -pin  "ACC1:acc#204" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load inst "ACC1:acc#230" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 18760 -attr oid 906 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#205.itm(0)} -pin  "ACC1:acc#230" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(1)} -pin  "ACC1:acc#230" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(2)} -pin  "ACC1:acc#230" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#204.itm(0)} -pin  "ACC1:acc#230" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(1)} -pin  "ACC1:acc#230" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(2)} -pin  "ACC1:acc#230" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#230.sdt(0)} -pin  "ACC1:acc#230" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.sdt}
+load net {ACC1:acc#230.sdt(1)} -pin  "ACC1:acc#230" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.sdt}
+load net {ACC1:acc#230.sdt(2)} -pin  "ACC1:acc#230" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.sdt}
+load net {ACC1:acc#230.sdt(3)} -pin  "ACC1:acc#230" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.sdt}
+load inst "ACC1-3:not#11" "not(1)" "INTERFACE" -attr xrf 18761 -attr oid 907 -attr @path {/sobel/sobel:core/ACC1-3:not#11} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#189.itm(4)} -pin  "ACC1-3:not#11" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#4.itm}
+load net {ACC1-3:not#11.itm} -pin  "ACC1-3:not#11" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#11.itm}
+load inst "ACC1:acc#190" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18762 -attr oid 908 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#190" {A(0)} -attr @path {/sobel/sobel:core/conc#393.itm}
+load net {ACC1:acc#189.itm(3)} -pin  "ACC1:acc#190" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#393.itm}
+load net {PWR} -pin  "ACC1:acc#190" {B(0)} -attr @path {/sobel/sobel:core/conc#394.itm}
+load net {ACC1-3:not#11.itm} -pin  "ACC1:acc#190" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#394.itm}
+load net {ACC1:acc#190.itm(0)} -pin  "ACC1:acc#190" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load net {ACC1:acc#190.itm(1)} -pin  "ACC1:acc#190" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load net {ACC1:acc#190.itm(2)} -pin  "ACC1:acc#190" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load inst "ACC1-3:not#10" "not(1)" "INTERFACE" -attr xrf 18763 -attr oid 909 -attr @path {/sobel/sobel:core/ACC1-3:not#10} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#189.itm(2)} -pin  "ACC1-3:not#10" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#5.itm}
+load net {ACC1-3:not#10.itm} -pin  "ACC1-3:not#10" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#10.itm}
+load inst "ACC1-3:not#12" "not(1)" "INTERFACE" -attr xrf 18764 -attr oid 910 -attr @path {/sobel/sobel:core/ACC1-3:not#12} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#189.itm(5)} -pin  "ACC1-3:not#12" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod.sva)#6.itm}
+load net {ACC1-3:not#12.itm} -pin  "ACC1-3:not#12" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#12.itm}
+load inst "ACC1:acc#191" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 18765 -attr oid 911 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#191" {A(0)} -attr @path {/sobel/sobel:core/conc#392.itm}
+load net {ACC1:acc#190.itm(1)} -pin  "ACC1:acc#191" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#392.itm}
+load net {ACC1:acc#190.itm(2)} -pin  "ACC1:acc#191" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#392.itm}
+load net {ACC1-3:not#12.itm} -pin  "ACC1:acc#191" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#366.itm}
+load net {ACC1-3:not#10.itm} -pin  "ACC1:acc#191" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#366.itm}
+load net {ACC1:acc#191.itm(0)} -pin  "ACC1:acc#191" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load net {ACC1:acc#191.itm(1)} -pin  "ACC1:acc#191" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load net {ACC1:acc#191.itm(2)} -pin  "ACC1:acc#191" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load net {ACC1:acc#191.itm(3)} -pin  "ACC1:acc#191" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load inst "ACC1-3:acc#5" "add(3,-1,3,-1,3)" "INTERFACE" -attr xrf 18766 -attr oid 912 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#5} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#191.itm(1)} -pin  "ACC1-3:acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1:acc#191.itm(2)} -pin  "ACC1-3:acc#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1:acc#191.itm(3)} -pin  "ACC1-3:acc#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1:acc#189.itm(1)} -pin  "ACC1-3:acc#5" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#395.itm}
+load net {GND} -pin  "ACC1-3:acc#5" {B(1)} -attr @path {/sobel/sobel:core/conc#395.itm}
+load net {PWR} -pin  "ACC1-3:acc#5" {B(2)} -attr @path {/sobel/sobel:core/conc#395.itm}
+load net {acc.imod#1.sva(0)} -pin  "ACC1-3:acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#1.sva}
+load net {acc.imod#1.sva(1)} -pin  "ACC1-3:acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#1.sva}
+load net {acc.imod#1.sva(2)} -pin  "ACC1-3:acc#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#1.sva}
+load inst "ACC1-1:not#47" "not(1)" "INTERFACE" -attr xrf 18767 -attr oid 913 -attr @path {/sobel/sobel:core/ACC1-1:not#47} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#174.itm(4)} -pin  "ACC1-1:not#47" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#25.sva)#4.itm}
+load net {ACC1-1:not#47.itm} -pin  "ACC1-1:not#47" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#47.itm}
+load inst "ACC1:acc#175" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 18768 -attr oid 914 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#175" {A(0)} -attr @path {/sobel/sobel:core/conc#397.itm}
+load net {ACC1:acc#174.itm(3)} -pin  "ACC1:acc#175" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#397.itm}
+load net {PWR} -pin  "ACC1:acc#175" {B(0)} -attr @path {/sobel/sobel:core/conc#398.itm}
+load net {ACC1-1:not#47.itm} -pin  "ACC1:acc#175" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#398.itm}
+load net {ACC1:acc#175.itm(0)} -pin  "ACC1:acc#175" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load net {ACC1:acc#175.itm(1)} -pin  "ACC1:acc#175" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load net {ACC1:acc#175.itm(2)} -pin  "ACC1:acc#175" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load inst "ACC1-1:not#46" "not(1)" "INTERFACE" -attr xrf 18769 -attr oid 915 -attr @path {/sobel/sobel:core/ACC1-1:not#46} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#174.itm(2)} -pin  "ACC1-1:not#46" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#25.sva)#5.itm}
+load net {ACC1-1:not#46.itm} -pin  "ACC1-1:not#46" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#46.itm}
+load inst "ACC1-1:not#48" "not(1)" "INTERFACE" -attr xrf 18770 -attr oid 916 -attr @path {/sobel/sobel:core/ACC1-1:not#48} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#174.itm(5)} -pin  "ACC1-1:not#48" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#25.sva)#6.itm}
+load net {ACC1-1:not#48.itm} -pin  "ACC1-1:not#48" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#48.itm}
+load inst "ACC1:acc#176" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 18771 -attr oid 917 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#176" {A(0)} -attr @path {/sobel/sobel:core/conc#396.itm}
+load net {ACC1:acc#175.itm(1)} -pin  "ACC1:acc#176" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#396.itm}
+load net {ACC1:acc#175.itm(2)} -pin  "ACC1:acc#176" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#396.itm}
+load net {ACC1-1:not#48.itm} -pin  "ACC1:acc#176" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#336.itm}
+load net {ACC1-1:not#46.itm} -pin  "ACC1:acc#176" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#336.itm}
+load net {ACC1:acc#176.itm(0)} -pin  "ACC1:acc#176" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {ACC1:acc#176.itm(1)} -pin  "ACC1:acc#176" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {ACC1:acc#176.itm(2)} -pin  "ACC1:acc#176" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {ACC1:acc#176.itm(3)} -pin  "ACC1:acc#176" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load inst "ACC1-1:acc#28" "add(3,-1,3,-1,3)" "INTERFACE" -attr xrf 18772 -attr oid 918 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#28} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#176.itm(1)} -pin  "ACC1-1:acc#28" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#176.itm(2)} -pin  "ACC1-1:acc#28" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#176.itm(3)} -pin  "ACC1-1:acc#28" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#174.itm(1)} -pin  "ACC1-1:acc#28" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#399.itm}
+load net {GND} -pin  "ACC1-1:acc#28" {B(1)} -attr @path {/sobel/sobel:core/conc#399.itm}
+load net {PWR} -pin  "ACC1-1:acc#28" {B(2)} -attr @path {/sobel/sobel:core/conc#399.itm}
+load net {acc.imod#27.sva(0)} -pin  "ACC1-1:acc#28" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#27.sva}
+load net {acc.imod#27.sva(1)} -pin  "ACC1-1:acc#28" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#27.sva}
+load net {acc.imod#27.sva(2)} -pin  "ACC1-1:acc#28" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#27.sva}
+### END MODULE 
+
+module new "sobel" "orig"
+load portBus {vin:rsc.z(89:0)} input 90 {vin:rsc.z(89)} {vin:rsc.z(88)} {vin:rsc.z(87)} {vin:rsc.z(86)} {vin:rsc.z(85)} {vin:rsc.z(84)} {vin:rsc.z(83)} {vin:rsc.z(82)} {vin:rsc.z(81)} {vin:rsc.z(80)} {vin:rsc.z(79)} {vin:rsc.z(78)} {vin:rsc.z(77)} {vin:rsc.z(76)} {vin:rsc.z(75)} {vin:rsc.z(74)} {vin:rsc.z(73)} {vin:rsc.z(72)} {vin:rsc.z(71)} {vin:rsc.z(70)} {vin:rsc.z(69)} {vin:rsc.z(68)} {vin:rsc.z(67)} {vin:rsc.z(66)} {vin:rsc.z(65)} {vin:rsc.z(64)} {vin:rsc.z(63)} {vin:rsc.z(62)} {vin:rsc.z(61)} {vin:rsc.z(60)} {vin:rsc.z(59)} {vin:rsc.z(58)} {vin:rsc.z(57)} {vin:rsc.z(56)} {vin:rsc.z(55)} {vin:rsc.z(54)} {vin:rsc.z(53)} {vin:rsc.z(52)} {vin:rsc.z(51)} {vin:rsc.z(50)} {vin:rsc.z(49)} {vin:rsc.z(48)} {vin:rsc.z(47)} {vin:rsc.z(46)} {vin:rsc.z(45)} {vin:rsc.z(44)} {vin:rsc.z(43)} {vin:rsc.z(42)} {vin:rsc.z(41)} {vin:rsc.z(40)} {vin:rsc.z(39)} {vin:rsc.z(38)} {vin:rsc.z(37)} {vin:rsc.z(36)} {vin:rsc.z(35)} {vin:rsc.z(34)} {vin:rsc.z(33)} {vin:rsc.z(32)} {vin:rsc.z(31)} {vin:rsc.z(30)} {vin:rsc.z(29)} {vin:rsc.z(28)} {vin:rsc.z(27)} {vin:rsc.z(26)} {vin:rsc.z(25)} {vin:rsc.z(24)} {vin:rsc.z(23)} {vin:rsc.z(22)} {vin:rsc.z(21)} {vin:rsc.z(20)} {vin:rsc.z(19)} {vin:rsc.z(18)} {vin:rsc.z(17)} {vin:rsc.z(16)} {vin:rsc.z(15)} {vin:rsc.z(14)} {vin:rsc.z(13)} {vin:rsc.z(12)} {vin:rsc.z(11)} {vin:rsc.z(10)} {vin:rsc.z(9)} {vin:rsc.z(8)} {vin:rsc.z(7)} {vin:rsc.z(6)} {vin:rsc.z(5)} {vin:rsc.z(4)} {vin:rsc.z(3)} {vin:rsc.z(2)} {vin:rsc.z(1)} {vin:rsc.z(0)} -attr xrf 18773 -attr oid 919 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load portBus {vout:rsc.z(29:0)} output 30 {vout:rsc.z(29)} {vout:rsc.z(28)} {vout:rsc.z(27)} {vout:rsc.z(26)} {vout:rsc.z(25)} {vout:rsc.z(24)} {vout:rsc.z(23)} {vout:rsc.z(22)} {vout:rsc.z(21)} {vout:rsc.z(20)} {vout:rsc.z(19)} {vout:rsc.z(18)} {vout:rsc.z(17)} {vout:rsc.z(16)} {vout:rsc.z(15)} {vout:rsc.z(14)} {vout:rsc.z(13)} {vout:rsc.z(12)} {vout:rsc.z(11)} {vout:rsc.z(10)} {vout:rsc.z(9)} {vout:rsc.z(8)} {vout:rsc.z(7)} {vout:rsc.z(6)} {vout:rsc.z(5)} {vout:rsc.z(4)} {vout:rsc.z(3)} {vout:rsc.z(2)} {vout:rsc.z(1)} {vout:rsc.z(0)} -attr xrf 18774 -attr oid 920 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load port {clk} input -attr xrf 18775 -attr oid 921 -attr vt d -attr @path {/sobel/clk}
+load port {en} input -attr xrf 18776 -attr oid 922 -attr vt d -attr @path {/sobel/en}
+load port {arst_n} input -attr xrf 18777 -attr oid 923 -attr vt d -attr @path {/sobel/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(89:0)} output 90 {d(89)} {d(88)} {d(87)} {d(86)} {d(85)} {d(84)} {d(83)} {d(82)} {d(81)} {d(80)} {d(79)} {d(78)} {d(77)} {d(76)} {d(75)} {d(74)} {d(73)} {d(72)} {d(71)} {d(70)} {d(69)} {d(68)} {d(67)} {d(66)} {d(65)} {d(64)} {d(63)} {d(62)} {d(61)} {d(60)} {d(59)} {d(58)} {d(57)} {d(56)} {d(55)} {d(54)} {d(53)} {d(52)} {d(51)} {d(50)} {d(49)} {d(48)} {d(47)} {d(46)} {d(45)} {d(44)} {d(43)} {d(42)} {d(41)} {d(40)} {d(39)} {d(38)} {d(37)} {d(36)} {d(35)} {d(34)} {d(33)} {d(32)} {d(31)} {d(30)} {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(89:0)} input 90 {z(89)} {z(88)} {z(87)} {z(86)} {z(85)} {z(84)} {z(83)} {z(82)} {z(81)} {z(80)} {z(79)} {z(78)} {z(77)} {z(76)} {z(75)} {z(74)} {z(73)} {z(72)} {z(71)} {z(70)} {z(69)} {z(68)} {z(67)} {z(66)} {z(65)} {z(64)} {z(63)} {z(62)} {z(61)} {z(60)} {z(59)} {z(58)} {z(57)} {z(56)} {z(55)} {z(54)} {z(53)} {z(52)} {z(51)} {z(50)} {z(49)} {z(48)} {z(47)} {z(46)} {z(45)} {z(44)} {z(43)} {z(42)} {z(41)} {z(40)} {z(39)} {z(38)} {z(37)} {z(36)} {z(35)} {z(34)} {z(33)} {z(32)} {z(31)} {z(30)} {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(29:0)} input 30 {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(29:0)} output 30 {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "sobel:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} \
+     portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} \
+
+load net {vin:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d#1} 90 {vin:rsc:mgc_in_wire.d#1(0)} {vin:rsc:mgc_in_wire.d#1(1)} {vin:rsc:mgc_in_wire.d#1(2)} {vin:rsc:mgc_in_wire.d#1(3)} {vin:rsc:mgc_in_wire.d#1(4)} {vin:rsc:mgc_in_wire.d#1(5)} {vin:rsc:mgc_in_wire.d#1(6)} {vin:rsc:mgc_in_wire.d#1(7)} {vin:rsc:mgc_in_wire.d#1(8)} {vin:rsc:mgc_in_wire.d#1(9)} {vin:rsc:mgc_in_wire.d#1(10)} {vin:rsc:mgc_in_wire.d#1(11)} {vin:rsc:mgc_in_wire.d#1(12)} {vin:rsc:mgc_in_wire.d#1(13)} {vin:rsc:mgc_in_wire.d#1(14)} {vin:rsc:mgc_in_wire.d#1(15)} {vin:rsc:mgc_in_wire.d#1(16)} {vin:rsc:mgc_in_wire.d#1(17)} {vin:rsc:mgc_in_wire.d#1(18)} {vin:rsc:mgc_in_wire.d#1(19)} {vin:rsc:mgc_in_wire.d#1(20)} {vin:rsc:mgc_in_wire.d#1(21)} {vin:rsc:mgc_in_wire.d#1(22)} {vin:rsc:mgc_in_wire.d#1(23)} {vin:rsc:mgc_in_wire.d#1(24)} {vin:rsc:mgc_in_wire.d#1(25)} {vin:rsc:mgc_in_wire.d#1(26)} {vin:rsc:mgc_in_wire.d#1(27)} {vin:rsc:mgc_in_wire.d#1(28)} {vin:rsc:mgc_in_wire.d#1(29)} {vin:rsc:mgc_in_wire.d#1(30)} {vin:rsc:mgc_in_wire.d#1(31)} {vin:rsc:mgc_in_wire.d#1(32)} {vin:rsc:mgc_in_wire.d#1(33)} {vin:rsc:mgc_in_wire.d#1(34)} {vin:rsc:mgc_in_wire.d#1(35)} {vin:rsc:mgc_in_wire.d#1(36)} {vin:rsc:mgc_in_wire.d#1(37)} {vin:rsc:mgc_in_wire.d#1(38)} {vin:rsc:mgc_in_wire.d#1(39)} {vin:rsc:mgc_in_wire.d#1(40)} {vin:rsc:mgc_in_wire.d#1(41)} {vin:rsc:mgc_in_wire.d#1(42)} {vin:rsc:mgc_in_wire.d#1(43)} {vin:rsc:mgc_in_wire.d#1(44)} {vin:rsc:mgc_in_wire.d#1(45)} {vin:rsc:mgc_in_wire.d#1(46)} {vin:rsc:mgc_in_wire.d#1(47)} {vin:rsc:mgc_in_wire.d#1(48)} {vin:rsc:mgc_in_wire.d#1(49)} {vin:rsc:mgc_in_wire.d#1(50)} {vin:rsc:mgc_in_wire.d#1(51)} {vin:rsc:mgc_in_wire.d#1(52)} {vin:rsc:mgc_in_wire.d#1(53)} {vin:rsc:mgc_in_wire.d#1(54)} {vin:rsc:mgc_in_wire.d#1(55)} {vin:rsc:mgc_in_wire.d#1(56)} {vin:rsc:mgc_in_wire.d#1(57)} {vin:rsc:mgc_in_wire.d#1(58)} {vin:rsc:mgc_in_wire.d#1(59)} {vin:rsc:mgc_in_wire.d#1(60)} {vin:rsc:mgc_in_wire.d#1(61)} {vin:rsc:mgc_in_wire.d#1(62)} {vin:rsc:mgc_in_wire.d#1(63)} {vin:rsc:mgc_in_wire.d#1(64)} {vin:rsc:mgc_in_wire.d#1(65)} {vin:rsc:mgc_in_wire.d#1(66)} {vin:rsc:mgc_in_wire.d#1(67)} {vin:rsc:mgc_in_wire.d#1(68)} {vin:rsc:mgc_in_wire.d#1(69)} {vin:rsc:mgc_in_wire.d#1(70)} {vin:rsc:mgc_in_wire.d#1(71)} {vin:rsc:mgc_in_wire.d#1(72)} {vin:rsc:mgc_in_wire.d#1(73)} {vin:rsc:mgc_in_wire.d#1(74)} {vin:rsc:mgc_in_wire.d#1(75)} {vin:rsc:mgc_in_wire.d#1(76)} {vin:rsc:mgc_in_wire.d#1(77)} {vin:rsc:mgc_in_wire.d#1(78)} {vin:rsc:mgc_in_wire.d#1(79)} {vin:rsc:mgc_in_wire.d#1(80)} {vin:rsc:mgc_in_wire.d#1(81)} {vin:rsc:mgc_in_wire.d#1(82)} {vin:rsc:mgc_in_wire.d#1(83)} {vin:rsc:mgc_in_wire.d#1(84)} {vin:rsc:mgc_in_wire.d#1(85)} {vin:rsc:mgc_in_wire.d#1(86)} {vin:rsc:mgc_in_wire.d#1(87)} {vin:rsc:mgc_in_wire.d#1(88)} {vin:rsc:mgc_in_wire.d#1(89)} -attr xrf 18778 -attr oid 924 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d#1} 30 {vout:rsc:mgc_out_stdreg.d#1(0)} {vout:rsc:mgc_out_stdreg.d#1(1)} {vout:rsc:mgc_out_stdreg.d#1(2)} {vout:rsc:mgc_out_stdreg.d#1(3)} {vout:rsc:mgc_out_stdreg.d#1(4)} {vout:rsc:mgc_out_stdreg.d#1(5)} {vout:rsc:mgc_out_stdreg.d#1(6)} {vout:rsc:mgc_out_stdreg.d#1(7)} {vout:rsc:mgc_out_stdreg.d#1(8)} {vout:rsc:mgc_out_stdreg.d#1(9)} {vout:rsc:mgc_out_stdreg.d#1(10)} {vout:rsc:mgc_out_stdreg.d#1(11)} {vout:rsc:mgc_out_stdreg.d#1(12)} {vout:rsc:mgc_out_stdreg.d#1(13)} {vout:rsc:mgc_out_stdreg.d#1(14)} {vout:rsc:mgc_out_stdreg.d#1(15)} {vout:rsc:mgc_out_stdreg.d#1(16)} {vout:rsc:mgc_out_stdreg.d#1(17)} {vout:rsc:mgc_out_stdreg.d#1(18)} {vout:rsc:mgc_out_stdreg.d#1(19)} {vout:rsc:mgc_out_stdreg.d#1(20)} {vout:rsc:mgc_out_stdreg.d#1(21)} {vout:rsc:mgc_out_stdreg.d#1(22)} {vout:rsc:mgc_out_stdreg.d#1(23)} {vout:rsc:mgc_out_stdreg.d#1(24)} {vout:rsc:mgc_out_stdreg.d#1(25)} {vout:rsc:mgc_out_stdreg.d#1(26)} {vout:rsc:mgc_out_stdreg.d#1(27)} {vout:rsc:mgc_out_stdreg.d#1(28)} {vout:rsc:mgc_out_stdreg.d#1(29)} -attr xrf 18779 -attr oid 925 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -attr vt d
+load net {vin:rsc.z(13)} -attr vt d
+load net {vin:rsc.z(14)} -attr vt d
+load net {vin:rsc.z(15)} -attr vt d
+load net {vin:rsc.z(16)} -attr vt d
+load net {vin:rsc.z(17)} -attr vt d
+load net {vin:rsc.z(18)} -attr vt d
+load net {vin:rsc.z(19)} -attr vt d
+load net {vin:rsc.z(20)} -attr vt d
+load net {vin:rsc.z(21)} -attr vt d
+load net {vin:rsc.z(22)} -attr vt d
+load net {vin:rsc.z(23)} -attr vt d
+load net {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -attr vt d
+load net {vin:rsc.z(28)} -attr vt d
+load net {vin:rsc.z(29)} -attr vt d
+load net {vin:rsc.z(30)} -attr vt d
+load net {vin:rsc.z(31)} -attr vt d
+load net {vin:rsc.z(32)} -attr vt d
+load net {vin:rsc.z(33)} -attr vt d
+load net {vin:rsc.z(34)} -attr vt d
+load net {vin:rsc.z(35)} -attr vt d
+load net {vin:rsc.z(36)} -attr vt d
+load net {vin:rsc.z(37)} -attr vt d
+load net {vin:rsc.z(38)} -attr vt d
+load net {vin:rsc.z(39)} -attr vt d
+load net {vin:rsc.z(40)} -attr vt d
+load net {vin:rsc.z(41)} -attr vt d
+load net {vin:rsc.z(42)} -attr vt d
+load net {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -attr vt d
+load net {vin:rsc.z(45)} -attr vt d
+load net {vin:rsc.z(46)} -attr vt d
+load net {vin:rsc.z(47)} -attr vt d
+load net {vin:rsc.z(48)} -attr vt d
+load net {vin:rsc.z(49)} -attr vt d
+load net {vin:rsc.z(50)} -attr vt d
+load net {vin:rsc.z(51)} -attr vt d
+load net {vin:rsc.z(52)} -attr vt d
+load net {vin:rsc.z(53)} -attr vt d
+load net {vin:rsc.z(54)} -attr vt d
+load net {vin:rsc.z(55)} -attr vt d
+load net {vin:rsc.z(56)} -attr vt d
+load net {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -attr vt d
+load net {vin:rsc.z(63)} -attr vt d
+load net {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -attr vt d
+load net {vin:rsc.z(68)} -attr vt d
+load net {vin:rsc.z(69)} -attr vt d
+load net {vin:rsc.z(70)} -attr vt d
+load net {vin:rsc.z(71)} -attr vt d
+load net {vin:rsc.z(72)} -attr vt d
+load net {vin:rsc.z(73)} -attr vt d
+load net {vin:rsc.z(74)} -attr vt d
+load net {vin:rsc.z(75)} -attr vt d
+load net {vin:rsc.z(76)} -attr vt d
+load net {vin:rsc.z(77)} -attr vt d
+load net {vin:rsc.z(78)} -attr vt d
+load net {vin:rsc.z(79)} -attr vt d
+load net {vin:rsc.z(80)} -attr vt d
+load net {vin:rsc.z(81)} -attr vt d
+load net {vin:rsc.z(82)} -attr vt d
+load net {vin:rsc.z(83)} -attr vt d
+load net {vin:rsc.z(84)} -attr vt d
+load net {vin:rsc.z(85)} -attr vt d
+load net {vin:rsc.z(86)} -attr vt d
+load net {vin:rsc.z(87)} -attr vt d
+load net {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 18780 -attr oid 926 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(0)} -port {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -port {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -port {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -port {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -port {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -port {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -port {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -port {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -port {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -port {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -port {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -port {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -port {vin:rsc.z(12)} -attr vt d
+load net {vin:rsc.z(13)} -port {vin:rsc.z(13)} -attr vt d
+load net {vin:rsc.z(14)} -port {vin:rsc.z(14)} -attr vt d
+load net {vin:rsc.z(15)} -port {vin:rsc.z(15)} -attr vt d
+load net {vin:rsc.z(16)} -port {vin:rsc.z(16)} -attr vt d
+load net {vin:rsc.z(17)} -port {vin:rsc.z(17)} -attr vt d
+load net {vin:rsc.z(18)} -port {vin:rsc.z(18)} -attr vt d
+load net {vin:rsc.z(19)} -port {vin:rsc.z(19)} -attr vt d
+load net {vin:rsc.z(20)} -port {vin:rsc.z(20)} -attr vt d
+load net {vin:rsc.z(21)} -port {vin:rsc.z(21)} -attr vt d
+load net {vin:rsc.z(22)} -port {vin:rsc.z(22)} -attr vt d
+load net {vin:rsc.z(23)} -port {vin:rsc.z(23)} -attr vt d
+load net {vin:rsc.z(24)} -port {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -port {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -port {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -port {vin:rsc.z(27)} -attr vt d
+load net {vin:rsc.z(28)} -port {vin:rsc.z(28)} -attr vt d
+load net {vin:rsc.z(29)} -port {vin:rsc.z(29)} -attr vt d
+load net {vin:rsc.z(30)} -port {vin:rsc.z(30)} -attr vt d
+load net {vin:rsc.z(31)} -port {vin:rsc.z(31)} -attr vt d
+load net {vin:rsc.z(32)} -port {vin:rsc.z(32)} -attr vt d
+load net {vin:rsc.z(33)} -port {vin:rsc.z(33)} -attr vt d
+load net {vin:rsc.z(34)} -port {vin:rsc.z(34)} -attr vt d
+load net {vin:rsc.z(35)} -port {vin:rsc.z(35)} -attr vt d
+load net {vin:rsc.z(36)} -port {vin:rsc.z(36)} -attr vt d
+load net {vin:rsc.z(37)} -port {vin:rsc.z(37)} -attr vt d
+load net {vin:rsc.z(38)} -port {vin:rsc.z(38)} -attr vt d
+load net {vin:rsc.z(39)} -port {vin:rsc.z(39)} -attr vt d
+load net {vin:rsc.z(40)} -port {vin:rsc.z(40)} -attr vt d
+load net {vin:rsc.z(41)} -port {vin:rsc.z(41)} -attr vt d
+load net {vin:rsc.z(42)} -port {vin:rsc.z(42)} -attr vt d
+load net {vin:rsc.z(43)} -port {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -port {vin:rsc.z(44)} -attr vt d
+load net {vin:rsc.z(45)} -port {vin:rsc.z(45)} -attr vt d
+load net {vin:rsc.z(46)} -port {vin:rsc.z(46)} -attr vt d
+load net {vin:rsc.z(47)} -port {vin:rsc.z(47)} -attr vt d
+load net {vin:rsc.z(48)} -port {vin:rsc.z(48)} -attr vt d
+load net {vin:rsc.z(49)} -port {vin:rsc.z(49)} -attr vt d
+load net {vin:rsc.z(50)} -port {vin:rsc.z(50)} -attr vt d
+load net {vin:rsc.z(51)} -port {vin:rsc.z(51)} -attr vt d
+load net {vin:rsc.z(52)} -port {vin:rsc.z(52)} -attr vt d
+load net {vin:rsc.z(53)} -port {vin:rsc.z(53)} -attr vt d
+load net {vin:rsc.z(54)} -port {vin:rsc.z(54)} -attr vt d
+load net {vin:rsc.z(55)} -port {vin:rsc.z(55)} -attr vt d
+load net {vin:rsc.z(56)} -port {vin:rsc.z(56)} -attr vt d
+load net {vin:rsc.z(57)} -port {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -port {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -port {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -port {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -port {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -port {vin:rsc.z(62)} -attr vt d
+load net {vin:rsc.z(63)} -port {vin:rsc.z(63)} -attr vt d
+load net {vin:rsc.z(64)} -port {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -port {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -port {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -port {vin:rsc.z(67)} -attr vt d
+load net {vin:rsc.z(68)} -port {vin:rsc.z(68)} -attr vt d
+load net {vin:rsc.z(69)} -port {vin:rsc.z(69)} -attr vt d
+load net {vin:rsc.z(70)} -port {vin:rsc.z(70)} -attr vt d
+load net {vin:rsc.z(71)} -port {vin:rsc.z(71)} -attr vt d
+load net {vin:rsc.z(72)} -port {vin:rsc.z(72)} -attr vt d
+load net {vin:rsc.z(73)} -port {vin:rsc.z(73)} -attr vt d
+load net {vin:rsc.z(74)} -port {vin:rsc.z(74)} -attr vt d
+load net {vin:rsc.z(75)} -port {vin:rsc.z(75)} -attr vt d
+load net {vin:rsc.z(76)} -port {vin:rsc.z(76)} -attr vt d
+load net {vin:rsc.z(77)} -port {vin:rsc.z(77)} -attr vt d
+load net {vin:rsc.z(78)} -port {vin:rsc.z(78)} -attr vt d
+load net {vin:rsc.z(79)} -port {vin:rsc.z(79)} -attr vt d
+load net {vin:rsc.z(80)} -port {vin:rsc.z(80)} -attr vt d
+load net {vin:rsc.z(81)} -port {vin:rsc.z(81)} -attr vt d
+load net {vin:rsc.z(82)} -port {vin:rsc.z(82)} -attr vt d
+load net {vin:rsc.z(83)} -port {vin:rsc.z(83)} -attr vt d
+load net {vin:rsc.z(84)} -port {vin:rsc.z(84)} -attr vt d
+load net {vin:rsc.z(85)} -port {vin:rsc.z(85)} -attr vt d
+load net {vin:rsc.z(86)} -port {vin:rsc.z(86)} -attr vt d
+load net {vin:rsc.z(87)} -port {vin:rsc.z(87)} -attr vt d
+load net {vin:rsc.z(88)} -port {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -port {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 18781 -attr oid 927 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vout:rsc.z(0)} -attr vt d
+load net {vout:rsc.z(1)} -attr vt d
+load net {vout:rsc.z(2)} -attr vt d
+load net {vout:rsc.z(3)} -attr vt d
+load net {vout:rsc.z(4)} -attr vt d
+load net {vout:rsc.z(5)} -attr vt d
+load net {vout:rsc.z(6)} -attr vt d
+load net {vout:rsc.z(7)} -attr vt d
+load net {vout:rsc.z(8)} -attr vt d
+load net {vout:rsc.z(9)} -attr vt d
+load net {vout:rsc.z(10)} -attr vt d
+load net {vout:rsc.z(11)} -attr vt d
+load net {vout:rsc.z(12)} -attr vt d
+load net {vout:rsc.z(13)} -attr vt d
+load net {vout:rsc.z(14)} -attr vt d
+load net {vout:rsc.z(15)} -attr vt d
+load net {vout:rsc.z(16)} -attr vt d
+load net {vout:rsc.z(17)} -attr vt d
+load net {vout:rsc.z(18)} -attr vt d
+load net {vout:rsc.z(19)} -attr vt d
+load net {vout:rsc.z(20)} -attr vt d
+load net {vout:rsc.z(21)} -attr vt d
+load net {vout:rsc.z(22)} -attr vt d
+load net {vout:rsc.z(23)} -attr vt d
+load net {vout:rsc.z(24)} -attr vt d
+load net {vout:rsc.z(25)} -attr vt d
+load net {vout:rsc.z(26)} -attr vt d
+load net {vout:rsc.z(27)} -attr vt d
+load net {vout:rsc.z(28)} -attr vt d
+load net {vout:rsc.z(29)} -attr vt d
+load netBundle {vout:rsc.z} 30 {vout:rsc.z(0)} {vout:rsc.z(1)} {vout:rsc.z(2)} {vout:rsc.z(3)} {vout:rsc.z(4)} {vout:rsc.z(5)} {vout:rsc.z(6)} {vout:rsc.z(7)} {vout:rsc.z(8)} {vout:rsc.z(9)} {vout:rsc.z(10)} {vout:rsc.z(11)} {vout:rsc.z(12)} {vout:rsc.z(13)} {vout:rsc.z(14)} {vout:rsc.z(15)} {vout:rsc.z(16)} {vout:rsc.z(17)} {vout:rsc.z(18)} {vout:rsc.z(19)} {vout:rsc.z(20)} {vout:rsc.z(21)} {vout:rsc.z(22)} {vout:rsc.z(23)} {vout:rsc.z(24)} {vout:rsc.z(25)} {vout:rsc.z(26)} {vout:rsc.z(27)} {vout:rsc.z(28)} {vout:rsc.z(29)} -attr xrf 18782 -attr oid 928 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(0)} -port {vout:rsc.z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -port {vout:rsc.z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -port {vout:rsc.z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -port {vout:rsc.z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -port {vout:rsc.z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -port {vout:rsc.z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -port {vout:rsc.z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -port {vout:rsc.z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -port {vout:rsc.z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -port {vout:rsc.z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -port {vout:rsc.z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -port {vout:rsc.z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -port {vout:rsc.z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -port {vout:rsc.z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -port {vout:rsc.z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -port {vout:rsc.z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -port {vout:rsc.z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -port {vout:rsc.z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -port {vout:rsc.z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -port {vout:rsc.z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -port {vout:rsc.z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -port {vout:rsc.z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -port {vout:rsc.z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -port {vout:rsc.z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -port {vout:rsc.z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -port {vout:rsc.z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -port {vout:rsc.z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -port {vout:rsc.z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -port {vout:rsc.z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -port {vout:rsc.z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {clk} -attr xrf 18783 -attr oid 929
+load net {clk} -port {clk} -attr xrf 18784 -attr oid 930
+load net {en} -attr xrf 18785 -attr oid 931
+load net {en} -port {en} -attr xrf 18786 -attr oid 932
+load net {arst_n} -attr xrf 18787 -attr oid 933
+load net {arst_n} -port {arst_n} -attr xrf 18788 -attr oid 934
+load inst "sobel:core:inst" "sobel:core" "orig" -attr xrf 18789 -attr oid 935 -attr vt dc -attr @path {/sobel/sobel:core:inst} -attr area 8771.559725 -attr delay 15.982252 -attr hier "/sobel/sobel:core" -pg 1 -lvl 3
+load net {clk} -pin  "sobel:core:inst" {clk#1} -attr xrf 18790 -attr oid 936 -attr @path {/sobel/clk}
+load net {en} -pin  "sobel:core:inst" {en#1} -attr xrf 18791 -attr oid 937 -attr @path {/sobel/en}
+load net {arst_n} -pin  "sobel:core:inst" {arst_n#1} -attr xrf 18792 -attr oid 938 -attr @path {/sobel/arst_n}
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(8)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(9)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(10)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(11)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(12)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(13)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(14)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(15)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(16)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(17)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(18)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(19)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(20)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(21)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(22)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(23)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(24)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(25)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(26)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(27)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(28)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(29)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(30)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(31)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(32)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(33)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(34)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(35)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(36)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(37)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(38)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(39)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(40)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(41)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(42)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(43)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(44)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(45)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(46)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(47)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(48)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(49)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(50)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(51)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(52)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(53)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(54)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(55)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(56)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(57)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(58)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(59)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(60)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(61)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(62)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(63)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(64)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(65)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(66)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(67)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(68)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(69)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(70)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(71)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(72)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(73)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(74)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(75)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(76)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(77)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(78)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(79)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(80)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(81)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(82)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(83)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(84)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(85)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(86)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(87)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(88)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(89)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(8)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(9)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(10)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(11)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(12)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(13)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(14)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(15)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(16)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(17)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(18)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(19)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(20)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(21)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(22)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(23)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(24)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(25)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(26)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(27)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(28)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(29)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load inst "vin:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" -attr xrf 18793 -attr oid 939 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,90)" -pg 1 -lvl 1
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "vin:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "vin:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "vin:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "vin:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "vin:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "vin:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "vin:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "vin:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "vin:rsc:mgc_in_wire" {d(8)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "vin:rsc:mgc_in_wire" {d(9)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "vin:rsc:mgc_in_wire" {d(10)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "vin:rsc:mgc_in_wire" {d(11)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "vin:rsc:mgc_in_wire" {d(12)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "vin:rsc:mgc_in_wire" {d(13)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "vin:rsc:mgc_in_wire" {d(14)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "vin:rsc:mgc_in_wire" {d(15)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "vin:rsc:mgc_in_wire" {d(16)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "vin:rsc:mgc_in_wire" {d(17)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "vin:rsc:mgc_in_wire" {d(18)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "vin:rsc:mgc_in_wire" {d(19)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "vin:rsc:mgc_in_wire" {d(20)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "vin:rsc:mgc_in_wire" {d(21)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "vin:rsc:mgc_in_wire" {d(22)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "vin:rsc:mgc_in_wire" {d(23)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "vin:rsc:mgc_in_wire" {d(24)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "vin:rsc:mgc_in_wire" {d(25)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "vin:rsc:mgc_in_wire" {d(26)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "vin:rsc:mgc_in_wire" {d(27)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "vin:rsc:mgc_in_wire" {d(28)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "vin:rsc:mgc_in_wire" {d(29)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "vin:rsc:mgc_in_wire" {d(30)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "vin:rsc:mgc_in_wire" {d(31)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "vin:rsc:mgc_in_wire" {d(32)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "vin:rsc:mgc_in_wire" {d(33)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "vin:rsc:mgc_in_wire" {d(34)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "vin:rsc:mgc_in_wire" {d(35)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "vin:rsc:mgc_in_wire" {d(36)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "vin:rsc:mgc_in_wire" {d(37)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "vin:rsc:mgc_in_wire" {d(38)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "vin:rsc:mgc_in_wire" {d(39)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "vin:rsc:mgc_in_wire" {d(40)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "vin:rsc:mgc_in_wire" {d(41)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "vin:rsc:mgc_in_wire" {d(42)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "vin:rsc:mgc_in_wire" {d(43)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "vin:rsc:mgc_in_wire" {d(44)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "vin:rsc:mgc_in_wire" {d(45)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "vin:rsc:mgc_in_wire" {d(46)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "vin:rsc:mgc_in_wire" {d(47)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "vin:rsc:mgc_in_wire" {d(48)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "vin:rsc:mgc_in_wire" {d(49)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "vin:rsc:mgc_in_wire" {d(50)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "vin:rsc:mgc_in_wire" {d(51)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "vin:rsc:mgc_in_wire" {d(52)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "vin:rsc:mgc_in_wire" {d(53)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "vin:rsc:mgc_in_wire" {d(54)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "vin:rsc:mgc_in_wire" {d(55)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "vin:rsc:mgc_in_wire" {d(56)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "vin:rsc:mgc_in_wire" {d(57)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "vin:rsc:mgc_in_wire" {d(58)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "vin:rsc:mgc_in_wire" {d(59)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "vin:rsc:mgc_in_wire" {d(60)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "vin:rsc:mgc_in_wire" {d(61)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "vin:rsc:mgc_in_wire" {d(62)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "vin:rsc:mgc_in_wire" {d(63)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "vin:rsc:mgc_in_wire" {d(64)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "vin:rsc:mgc_in_wire" {d(65)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "vin:rsc:mgc_in_wire" {d(66)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "vin:rsc:mgc_in_wire" {d(67)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "vin:rsc:mgc_in_wire" {d(68)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "vin:rsc:mgc_in_wire" {d(69)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "vin:rsc:mgc_in_wire" {d(70)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "vin:rsc:mgc_in_wire" {d(71)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "vin:rsc:mgc_in_wire" {d(72)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "vin:rsc:mgc_in_wire" {d(73)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "vin:rsc:mgc_in_wire" {d(74)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "vin:rsc:mgc_in_wire" {d(75)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "vin:rsc:mgc_in_wire" {d(76)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "vin:rsc:mgc_in_wire" {d(77)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "vin:rsc:mgc_in_wire" {d(78)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "vin:rsc:mgc_in_wire" {d(79)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "vin:rsc:mgc_in_wire" {d(80)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "vin:rsc:mgc_in_wire" {d(81)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "vin:rsc:mgc_in_wire" {d(82)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "vin:rsc:mgc_in_wire" {d(83)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "vin:rsc:mgc_in_wire" {d(84)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "vin:rsc:mgc_in_wire" {d(85)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "vin:rsc:mgc_in_wire" {d(86)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "vin:rsc:mgc_in_wire" {d(87)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "vin:rsc:mgc_in_wire" {d(88)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "vin:rsc:mgc_in_wire" {d(89)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc.z(0)} -pin  "vin:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(1)} -pin  "vin:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(2)} -pin  "vin:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(3)} -pin  "vin:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(4)} -pin  "vin:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(5)} -pin  "vin:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(6)} -pin  "vin:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(7)} -pin  "vin:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(8)} -pin  "vin:rsc:mgc_in_wire" {z(8)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(9)} -pin  "vin:rsc:mgc_in_wire" {z(9)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(10)} -pin  "vin:rsc:mgc_in_wire" {z(10)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(11)} -pin  "vin:rsc:mgc_in_wire" {z(11)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(12)} -pin  "vin:rsc:mgc_in_wire" {z(12)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(13)} -pin  "vin:rsc:mgc_in_wire" {z(13)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(14)} -pin  "vin:rsc:mgc_in_wire" {z(14)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(15)} -pin  "vin:rsc:mgc_in_wire" {z(15)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(16)} -pin  "vin:rsc:mgc_in_wire" {z(16)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(17)} -pin  "vin:rsc:mgc_in_wire" {z(17)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(18)} -pin  "vin:rsc:mgc_in_wire" {z(18)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(19)} -pin  "vin:rsc:mgc_in_wire" {z(19)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(20)} -pin  "vin:rsc:mgc_in_wire" {z(20)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(21)} -pin  "vin:rsc:mgc_in_wire" {z(21)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(22)} -pin  "vin:rsc:mgc_in_wire" {z(22)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(23)} -pin  "vin:rsc:mgc_in_wire" {z(23)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(24)} -pin  "vin:rsc:mgc_in_wire" {z(24)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(25)} -pin  "vin:rsc:mgc_in_wire" {z(25)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(26)} -pin  "vin:rsc:mgc_in_wire" {z(26)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(27)} -pin  "vin:rsc:mgc_in_wire" {z(27)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(28)} -pin  "vin:rsc:mgc_in_wire" {z(28)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(29)} -pin  "vin:rsc:mgc_in_wire" {z(29)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(30)} -pin  "vin:rsc:mgc_in_wire" {z(30)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(31)} -pin  "vin:rsc:mgc_in_wire" {z(31)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(32)} -pin  "vin:rsc:mgc_in_wire" {z(32)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(33)} -pin  "vin:rsc:mgc_in_wire" {z(33)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(34)} -pin  "vin:rsc:mgc_in_wire" {z(34)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(35)} -pin  "vin:rsc:mgc_in_wire" {z(35)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(36)} -pin  "vin:rsc:mgc_in_wire" {z(36)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(37)} -pin  "vin:rsc:mgc_in_wire" {z(37)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(38)} -pin  "vin:rsc:mgc_in_wire" {z(38)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(39)} -pin  "vin:rsc:mgc_in_wire" {z(39)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(40)} -pin  "vin:rsc:mgc_in_wire" {z(40)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(41)} -pin  "vin:rsc:mgc_in_wire" {z(41)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(42)} -pin  "vin:rsc:mgc_in_wire" {z(42)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(43)} -pin  "vin:rsc:mgc_in_wire" {z(43)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(44)} -pin  "vin:rsc:mgc_in_wire" {z(44)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(45)} -pin  "vin:rsc:mgc_in_wire" {z(45)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(46)} -pin  "vin:rsc:mgc_in_wire" {z(46)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(47)} -pin  "vin:rsc:mgc_in_wire" {z(47)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(48)} -pin  "vin:rsc:mgc_in_wire" {z(48)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(49)} -pin  "vin:rsc:mgc_in_wire" {z(49)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(50)} -pin  "vin:rsc:mgc_in_wire" {z(50)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(51)} -pin  "vin:rsc:mgc_in_wire" {z(51)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(52)} -pin  "vin:rsc:mgc_in_wire" {z(52)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(53)} -pin  "vin:rsc:mgc_in_wire" {z(53)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(54)} -pin  "vin:rsc:mgc_in_wire" {z(54)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(55)} -pin  "vin:rsc:mgc_in_wire" {z(55)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(56)} -pin  "vin:rsc:mgc_in_wire" {z(56)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(57)} -pin  "vin:rsc:mgc_in_wire" {z(57)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(58)} -pin  "vin:rsc:mgc_in_wire" {z(58)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(59)} -pin  "vin:rsc:mgc_in_wire" {z(59)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(60)} -pin  "vin:rsc:mgc_in_wire" {z(60)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(61)} -pin  "vin:rsc:mgc_in_wire" {z(61)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(62)} -pin  "vin:rsc:mgc_in_wire" {z(62)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(63)} -pin  "vin:rsc:mgc_in_wire" {z(63)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(64)} -pin  "vin:rsc:mgc_in_wire" {z(64)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(65)} -pin  "vin:rsc:mgc_in_wire" {z(65)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(66)} -pin  "vin:rsc:mgc_in_wire" {z(66)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(67)} -pin  "vin:rsc:mgc_in_wire" {z(67)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(68)} -pin  "vin:rsc:mgc_in_wire" {z(68)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(69)} -pin  "vin:rsc:mgc_in_wire" {z(69)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(70)} -pin  "vin:rsc:mgc_in_wire" {z(70)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(71)} -pin  "vin:rsc:mgc_in_wire" {z(71)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(72)} -pin  "vin:rsc:mgc_in_wire" {z(72)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(73)} -pin  "vin:rsc:mgc_in_wire" {z(73)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(74)} -pin  "vin:rsc:mgc_in_wire" {z(74)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(75)} -pin  "vin:rsc:mgc_in_wire" {z(75)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(76)} -pin  "vin:rsc:mgc_in_wire" {z(76)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(77)} -pin  "vin:rsc:mgc_in_wire" {z(77)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(78)} -pin  "vin:rsc:mgc_in_wire" {z(78)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(79)} -pin  "vin:rsc:mgc_in_wire" {z(79)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(80)} -pin  "vin:rsc:mgc_in_wire" {z(80)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(81)} -pin  "vin:rsc:mgc_in_wire" {z(81)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(82)} -pin  "vin:rsc:mgc_in_wire" {z(82)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(83)} -pin  "vin:rsc:mgc_in_wire" {z(83)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(84)} -pin  "vin:rsc:mgc_in_wire" {z(84)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(85)} -pin  "vin:rsc:mgc_in_wire" {z(85)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(86)} -pin  "vin:rsc:mgc_in_wire" {z(86)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(87)} -pin  "vin:rsc:mgc_in_wire" {z(87)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(88)} -pin  "vin:rsc:mgc_in_wire" {z(88)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(89)} -pin  "vin:rsc:mgc_in_wire" {z(89)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load inst "vout:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" -attr xrf 18794 -attr oid 940 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(2,30)" -pg 1 -lvl 1002
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "vout:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "vout:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "vout:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "vout:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "vout:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "vout:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "vout:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "vout:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "vout:rsc:mgc_out_stdreg" {d(8)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "vout:rsc:mgc_out_stdreg" {d(9)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "vout:rsc:mgc_out_stdreg" {d(10)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "vout:rsc:mgc_out_stdreg" {d(11)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "vout:rsc:mgc_out_stdreg" {d(12)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "vout:rsc:mgc_out_stdreg" {d(13)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "vout:rsc:mgc_out_stdreg" {d(14)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "vout:rsc:mgc_out_stdreg" {d(15)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "vout:rsc:mgc_out_stdreg" {d(16)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "vout:rsc:mgc_out_stdreg" {d(17)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "vout:rsc:mgc_out_stdreg" {d(18)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "vout:rsc:mgc_out_stdreg" {d(19)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "vout:rsc:mgc_out_stdreg" {d(20)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "vout:rsc:mgc_out_stdreg" {d(21)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "vout:rsc:mgc_out_stdreg" {d(22)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "vout:rsc:mgc_out_stdreg" {d(23)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "vout:rsc:mgc_out_stdreg" {d(24)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "vout:rsc:mgc_out_stdreg" {d(25)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "vout:rsc:mgc_out_stdreg" {d(26)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "vout:rsc:mgc_out_stdreg" {d(27)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "vout:rsc:mgc_out_stdreg" {d(28)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "vout:rsc:mgc_out_stdreg" {d(29)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc.z(0)} -pin  "vout:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -pin  "vout:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -pin  "vout:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -pin  "vout:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -pin  "vout:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -pin  "vout:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -pin  "vout:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -pin  "vout:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -pin  "vout:rsc:mgc_out_stdreg" {z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -pin  "vout:rsc:mgc_out_stdreg" {z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -pin  "vout:rsc:mgc_out_stdreg" {z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -pin  "vout:rsc:mgc_out_stdreg" {z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -pin  "vout:rsc:mgc_out_stdreg" {z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -pin  "vout:rsc:mgc_out_stdreg" {z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -pin  "vout:rsc:mgc_out_stdreg" {z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -pin  "vout:rsc:mgc_out_stdreg" {z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -pin  "vout:rsc:mgc_out_stdreg" {z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -pin  "vout:rsc:mgc_out_stdreg" {z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -pin  "vout:rsc:mgc_out_stdreg" {z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -pin  "vout:rsc:mgc_out_stdreg" {z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -pin  "vout:rsc:mgc_out_stdreg" {z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -pin  "vout:rsc:mgc_out_stdreg" {z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -pin  "vout:rsc:mgc_out_stdreg" {z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -pin  "vout:rsc:mgc_out_stdreg" {z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -pin  "vout:rsc:mgc_out_stdreg" {z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -pin  "vout:rsc:mgc_out_stdreg" {z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -pin  "vout:rsc:mgc_out_stdreg" {z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -pin  "vout:rsc:mgc_out_stdreg" {z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -pin  "vout:rsc:mgc_out_stdreg" {z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -pin  "vout:rsc:mgc_out_stdreg" {z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+### END MODULE 
+
diff --git a/Sobel/sobel.v7/concat_rtl.v b/Sobel/sobel.v7/concat_rtl.v
new file mode 100644
index 0000000..473d910
--- /dev/null
+++ b/Sobel/sobel.v7/concat_rtl.v
@@ -0,0 +1,2805 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 15:20:14 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [1:0] acc_imod_7_lpi_1_dfm;
+  reg [11:0] ACC1_acc_125_psp_lpi_1_dfm;
+  reg [1:0] acc_imod_20_lpi_1_dfm;
+  reg [11:0] ACC1_acc_125_psp_1_lpi_1_dfm;
+  reg [15:0] in_0_sva_1;
+  reg [15:0] in_2_sva_1;
+  reg [1:0] i_6_sva_1;
+  reg exit_FRAME_lpi_1_dfm_1;
+  reg exit_FRAME_for_lpi_1_dfm_3;
+  reg [12:0] FRAME_for_acc_24_itm_1;
+  wire [14:0] nl_FRAME_for_acc_24_itm_1;
+  reg [11:0] FRAME_for_slc_in_0_sva_itm_1;
+  wire [14:0] nl_FRAME_for_slc_in_0_sva_itm_1;
+  reg [11:0] FRAME_for_acc_26_itm_1;
+  wire [13:0] nl_FRAME_for_acc_26_itm_1;
+  reg [11:0] FRAME_for_slc_in_2_sva_itm_1;
+  wire [14:0] nl_FRAME_for_slc_in_2_sva_itm_1;
+  reg [12:0] ACC1_acc_341_itm_1;
+  wire [14:0] nl_ACC1_acc_341_itm_1;
+  reg exit_FRAME_for_sva_1_st_1;
+  reg main_stage_0_2;
+  reg [1:0] acc_imod_6_lpi_1_dfm_sg1;
+  reg [29:0] regs_regs_2_lpi_1_dfm_sg2;
+  reg [29:0] regs_regs_2_lpi_1_dfm_1;
+  reg [1:0] ACC1_acc_118_psp_lpi_1_dfm_sg1;
+  reg [2:0] ACC1_acc_110_psp_1_lpi_1_dfm_sg1;
+  reg [1:0] acc_imod_18_lpi_1_dfm_sg1;
+  reg [1:0] ACC1_acc_118_psp_1_lpi_1_dfm_sg1;
+  reg [2:0] ACC1_acc_110_psp_2_lpi_1_dfm_sg1;
+  wire and_cse;
+  wire exit_FRAME_for_lpi_1_dfm_4;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+  wire [11:0] FRAME_acc_2_psp_sva;
+  wire [13:0] nl_FRAME_acc_2_psp_sva;
+  wire [5:0] acc_imod_12_sva;
+  wire [7:0] nl_acc_imod_12_sva;
+  wire [15:0] in_2_sva_3;
+  wire [16:0] nl_in_2_sva_3;
+  wire [15:0] in_0_sva_3;
+  wire [16:0] nl_in_0_sva_3;
+  wire [1:0] i_6_sva_2;
+  wire [2:0] nl_i_6_sva_2;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire [2:0] ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0;
+  wire [11:0] ACC1_acc_125_psp_lpi_1_dfm_mx0;
+  wire [1:0] ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0;
+  wire [29:0] regs_regs_2_lpi_1_dfm_sg2_mx0;
+  wire [29:0] regs_regs_2_lpi_1_dfm_1_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire [1:0] acc_imod_7_lpi_1_dfm_mx0;
+  wire [1:0] acc_imod_6_lpi_1_dfm_sg1_mx0;
+  wire [2:0] ACC1_acc_118_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_118_psp_1_sva;
+  wire [11:0] ACC1_acc_125_psp_1_sva;
+  wire [12:0] nl_ACC1_acc_125_psp_1_sva;
+  wire [11:0] ACC1_acc_125_psp_sva;
+  wire [12:0] nl_ACC1_acc_125_psp_sva;
+  wire [2:0] ACC1_acc_118_psp_sva;
+  wire [3:0] nl_ACC1_acc_118_psp_sva;
+  wire [11:0] acc_10_psp_1_sva;
+  wire [12:0] nl_acc_10_psp_1_sva;
+  wire [3:0] ACC1_acc_113_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_113_psp_1_sva;
+  wire [2:0] ACC1_acc_120_psp_sva;
+  wire [3:0] nl_ACC1_acc_120_psp_sva;
+  wire [2:0] ACC1_acc_250_cse;
+  wire [3:0] nl_ACC1_acc_250_cse;
+  wire [11:0] acc_10_psp_2_sva;
+  wire [12:0] nl_acc_10_psp_2_sva;
+  wire [3:0] ACC1_acc_113_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_113_psp_2_sva;
+  wire [2:0] ACC1_acc_120_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_120_psp_1_sva;
+  wire [2:0] ACC1_acc_277_cse;
+  wire [3:0] nl_ACC1_acc_277_cse;
+  wire [11:0] acc_psp_1_sva;
+  wire [12:0] nl_acc_psp_1_sva;
+  wire [3:0] ACC1_acc_107_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_107_psp_1_sva;
+  wire [2:0] ACC1_acc_116_psp_sva;
+  wire [3:0] nl_ACC1_acc_116_psp_sva;
+  wire [2:0] ACC1_acc_197_cse;
+  wire [3:0] nl_ACC1_acc_197_cse;
+  wire [11:0] acc_psp_2_sva;
+  wire [12:0] nl_acc_psp_2_sva;
+  wire [3:0] ACC1_acc_107_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_107_psp_2_sva;
+  wire [2:0] ACC1_acc_116_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_116_psp_1_sva;
+  wire [2:0] ACC1_acc_224_cse;
+  wire [3:0] nl_ACC1_acc_224_cse;
+  wire exit_FRAME_lpi_1_dfm_1_mx0;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [11:0] ACC1_acc_125_psp_1_lpi_1_dfm_mx0;
+  wire [1:0] acc_imod_18_lpi_1_dfm_sg1_mx0;
+  wire [2:0] ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0;
+  wire [1:0] acc_imod_20_lpi_1_dfm_mx0;
+  wire [1:0] ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0;
+  wire FRAME_for_nor_cse;
+  wire [15:0] ACC1_acc_itm;
+  wire [17:0] nl_ACC1_acc_itm;
+  wire [3:0] ACC1_acc_150_itm;
+  wire [4:0] nl_ACC1_acc_150_itm;
+  wire [4:0] ACC1_acc_148_itm;
+  wire [5:0] nl_ACC1_acc_148_itm;
+  wire [4:0] ACC1_acc_176_itm;
+  wire [5:0] nl_ACC1_acc_176_itm;
+  wire [3:0] ACC1_acc_178_itm;
+  wire [4:0] nl_ACC1_acc_178_itm;
+  wire [2:0] ACC1_acc_188_itm;
+  wire [3:0] nl_ACC1_acc_188_itm;
+  wire [2:0] ACC1_acc_161_itm;
+  wire [3:0] nl_ACC1_acc_161_itm;
+  wire [3:0] ACC1_acc_160_itm;
+  wire [4:0] nl_ACC1_acc_160_itm;
+  wire [3:0] ACC1_acc_187_itm;
+  wire [4:0] nl_ACC1_acc_187_itm;
+  wire [2:0] ACC1_acc_170_itm;
+  wire [3:0] nl_ACC1_acc_170_itm;
+  wire [2:0] ACC1_acc_141_itm;
+  wire [3:0] nl_ACC1_acc_141_itm;
+  wire [3:0] ACC1_acc_140_itm;
+  wire [4:0] nl_ACC1_acc_140_itm;
+  wire [3:0] ACC1_acc_169_itm;
+  wire [4:0] nl_ACC1_acc_169_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_3_itm;
+
+  wire[15:0] FRAME_for_mux_12_nl;
+  wire[15:0] FRAME_for_mux_11_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_2_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(ACC1_acc_itm[14:13])
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_itm[12:10])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_itm[9:4]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_12_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_12_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_12_sva[5:3])) , (~ (acc_imod_12_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_12_sva[4:3])) + conv_u2u_3_5(~ (ACC1_acc_itm[9:7])))
+      + ({4'b1001 , (acc_imod_12_sva[5])}))))) + conv_u2u_11_12(signext_11_9({(ACC1_acc_itm[15])
+      , 3'b0 , (signext_3_1(ACC1_acc_itm[15])) , 1'b0 , (ACC1_acc_itm[15])}));
+  assign FRAME_acc_2_psp_sva = nl_FRAME_acc_2_psp_sva[11:0];
+  assign nl_ACC1_acc_itm = (in_2_sva_3 + conv_s2s_13_16(ACC1_acc_341_itm_1)) + in_0_sva_3;
+  assign ACC1_acc_itm = nl_ACC1_acc_itm[15:0];
+  assign nl_acc_imod_12_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~ (ACC1_acc_itm[15]))
+      , 1'b1 , (~ (ACC1_acc_itm[15]))}) + conv_u2u_2_4(ACC1_acc_itm[14:13]))) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_itm[3:1])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[6:4])))) + 6'b101011;
+  assign acc_imod_12_sva = nl_acc_imod_12_sva[5:0];
+  assign FRAME_for_mux_12_nl = MUX_v_16_2_2({in_2_sva_1 , ({{4{FRAME_for_slc_in_2_sva_itm_1[11]}},
+      FRAME_for_slc_in_2_sva_itm_1})}, exit_FRAME_for_lpi_1_dfm_3);
+  assign nl_in_2_sva_3 = conv_s2u_12_16(FRAME_for_acc_26_itm_1) + (FRAME_for_mux_12_nl);
+  assign in_2_sva_3 = nl_in_2_sva_3[15:0];
+  assign FRAME_for_mux_11_nl = MUX_v_16_2_2({in_0_sva_1 , ({{4{FRAME_for_slc_in_0_sva_itm_1[11]}},
+      FRAME_for_slc_in_0_sva_itm_1})}, exit_FRAME_for_lpi_1_dfm_3);
+  assign nl_in_0_sva_3 = conv_s2u_13_16(FRAME_for_acc_24_itm_1) + (FRAME_for_mux_11_nl);
+  assign in_0_sva_3 = nl_in_0_sva_3[15:0];
+  assign nl_FRAME_for_acc_itm = i_6_sva_2 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  assign exit_FRAME_for_lpi_1_dfm_4 = exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva;
+  assign nl_i_6_sva_2 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_2 = nl_i_6_sva_2[1:0];
+  assign i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm_4));
+  assign ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0 = MUX_v_3_2_2({(ACC1_acc_176_itm[4:2])
+      , ACC1_acc_110_psp_1_lpi_1_dfm_sg1}, and_cse);
+  assign ACC1_acc_125_psp_lpi_1_dfm_mx0 = MUX_v_12_2_2({ACC1_acc_125_psp_sva , ACC1_acc_125_psp_lpi_1_dfm},
+      and_cse);
+  assign ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_118_psp_sva[2:1])
+      , ACC1_acc_118_psp_lpi_1_dfm_sg1}, and_cse);
+  assign regs_regs_2_lpi_1_dfm_sg2_mx0 = MUX_v_30_2_2({(regs_regs_1_sva[89:60]) ,
+      regs_regs_2_lpi_1_dfm_sg2}, and_cse);
+  assign regs_regs_2_lpi_1_dfm_1_mx0 = MUX_v_30_2_2({(regs_regs_1_sva[29:0]) , regs_regs_2_lpi_1_dfm_1},
+      and_cse);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_cse);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_cse);
+  assign acc_imod_7_lpi_1_dfm_mx0 = MUX_v_2_2_2({(readslicef_3_2_1((({1'b1 , (ACC1_acc_178_itm[1])
+      , 1'b1}) + conv_u2s_2_3({(~ (ACC1_acc_178_itm[2])) , (~ (ACC1_acc_178_itm[3]))}))))
+      , acc_imod_7_lpi_1_dfm}, and_cse);
+  assign acc_imod_6_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_178_itm[3:2]) , acc_imod_6_lpi_1_dfm_sg1},
+      and_cse);
+  assign nl_ACC1_acc_150_itm = conv_s2s_3_4({(~ (ACC1_acc_118_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_118_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_150_itm = nl_ACC1_acc_150_itm[3:0];
+  assign nl_ACC1_acc_118_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_148_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_148_itm[2])) , (ACC1_acc_148_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_148_itm[4]));
+  assign ACC1_acc_118_psp_1_sva = nl_ACC1_acc_118_psp_1_sva[2:0];
+  assign nl_ACC1_acc_148_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_125_psp_1_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_1_sva[2])) , (~ (ACC1_acc_125_psp_1_sva[6]))}))))
+      , (~ (ACC1_acc_125_psp_1_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_1_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_1_sva[4])) , (ACC1_acc_125_psp_1_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_125_psp_1_sva[11:10])) , (ACC1_acc_125_psp_1_sva[7])}))))
+      , (ACC1_acc_125_psp_1_sva[9])});
+  assign ACC1_acc_148_itm = nl_ACC1_acc_148_itm[4:0];
+  assign nl_ACC1_acc_125_psp_1_sva = conv_s2u_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[39:30]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[49:40]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[59:50])) + 11'b11);
+  assign ACC1_acc_125_psp_1_sva = nl_ACC1_acc_125_psp_1_sva[11:0];
+  assign nl_ACC1_acc_176_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_125_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_sva[2])) , (~ (ACC1_acc_125_psp_sva[6]))}))))
+      , (~ (ACC1_acc_125_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_sva[4])) , (ACC1_acc_125_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_125_psp_sva[11:10])) , (ACC1_acc_125_psp_sva[7])}))))
+      , (ACC1_acc_125_psp_sva[9])});
+  assign ACC1_acc_176_itm = nl_ACC1_acc_176_itm[4:0];
+  assign nl_ACC1_acc_125_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_1_sva[49:40])
+      + conv_s2s_10_11(regs_regs_1_sva[39:30])) + conv_s2u_10_12(regs_regs_1_sva[59:50]);
+  assign ACC1_acc_125_psp_sva = nl_ACC1_acc_125_psp_sva[11:0];
+  assign nl_ACC1_acc_118_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_176_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_176_itm[2])) , (ACC1_acc_176_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_176_itm[4]));
+  assign ACC1_acc_118_psp_sva = nl_ACC1_acc_118_psp_sva[2:0];
+  assign nl_ACC1_acc_178_itm = conv_s2s_3_4({(~ (ACC1_acc_118_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_118_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_178_itm = nl_ACC1_acc_178_itm[3:0];
+  assign nl_acc_10_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_1_sva[79:70])
+      + conv_s2s_10_11(regs_regs_1_sva[69:60])) + conv_s2s_10_12(regs_regs_1_sva[89:80]);
+  assign acc_10_psp_1_sva = nl_acc_10_psp_1_sva[11:0];
+  assign nl_ACC1_acc_113_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_10_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_10_psp_1_sva[1]))
+      , (acc_10_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_10_psp_1_sva[0])
+      , (acc_10_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_1_sva[3])) , (~ (acc_10_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_1_sva[5])) , (acc_10_psp_1_sva[6])}))))
+      , (~ (acc_10_psp_1_sva[9]))}))));
+  assign ACC1_acc_113_psp_1_sva = nl_ACC1_acc_113_psp_1_sva[3:0];
+  assign nl_ACC1_acc_120_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_113_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_113_psp_1_sva[1])) , (ACC1_acc_113_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_113_psp_1_sva[3]));
+  assign ACC1_acc_120_psp_sva = nl_ACC1_acc_120_psp_sva[2:0];
+  assign nl_ACC1_acc_250_cse = conv_u2u_2_3(signext_2_1(acc_10_psp_1_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_10_psp_1_sva[11]));
+  assign ACC1_acc_250_cse = nl_ACC1_acc_250_cse[2:0];
+  assign nl_ACC1_acc_188_itm = ({1'b1 , (ACC1_acc_187_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_187_itm[2])) , (~ (ACC1_acc_187_itm[3]))});
+  assign ACC1_acc_188_itm = nl_ACC1_acc_188_itm[2:0];
+  assign nl_acc_10_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[69:60]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[79:70]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[89:80])) + 11'b11);
+  assign acc_10_psp_2_sva = nl_acc_10_psp_2_sva[11:0];
+  assign nl_ACC1_acc_161_itm = ({1'b1 , (ACC1_acc_160_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_160_itm[2])) , (~ (ACC1_acc_160_itm[3]))});
+  assign ACC1_acc_161_itm = nl_ACC1_acc_161_itm[2:0];
+  assign nl_ACC1_acc_160_itm = conv_s2s_3_4({(~ (ACC1_acc_120_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_120_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_160_itm = nl_ACC1_acc_160_itm[3:0];
+  assign nl_ACC1_acc_113_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_10_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_10_psp_2_sva[1]))
+      , (acc_10_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_10_psp_2_sva[0])
+      , (acc_10_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_2_sva[3])) , (~ (acc_10_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_2_sva[5])) , (acc_10_psp_2_sva[6])}))))
+      , (~ (acc_10_psp_2_sva[9]))}))));
+  assign ACC1_acc_113_psp_2_sva = nl_ACC1_acc_113_psp_2_sva[3:0];
+  assign nl_ACC1_acc_120_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_113_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_113_psp_2_sva[1])) , (ACC1_acc_113_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_113_psp_2_sva[3]));
+  assign ACC1_acc_120_psp_1_sva = nl_ACC1_acc_120_psp_1_sva[2:0];
+  assign nl_ACC1_acc_277_cse = conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11]));
+  assign ACC1_acc_277_cse = nl_ACC1_acc_277_cse[2:0];
+  assign nl_ACC1_acc_187_itm = conv_s2s_3_4({(~ (ACC1_acc_120_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_120_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_187_itm = nl_ACC1_acc_187_itm[3:0];
+  assign nl_acc_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_1_sva[19:10])
+      + conv_s2s_10_11(regs_regs_1_sva[9:0])) + conv_s2s_10_12(regs_regs_1_sva[29:20]);
+  assign acc_psp_1_sva = nl_acc_psp_1_sva[11:0];
+  assign nl_ACC1_acc_107_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_1_sva[1])) , (acc_psp_1_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_1_sva[0]) , (acc_psp_1_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[3])) , (~ (acc_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[5])) , (acc_psp_1_sva[6])})))) ,
+      (~ (acc_psp_1_sva[9]))}))));
+  assign ACC1_acc_107_psp_1_sva = nl_ACC1_acc_107_psp_1_sva[3:0];
+  assign nl_ACC1_acc_116_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_107_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_107_psp_1_sva[1])) , (ACC1_acc_107_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_107_psp_1_sva[3]));
+  assign ACC1_acc_116_psp_sva = nl_ACC1_acc_116_psp_sva[2:0];
+  assign nl_ACC1_acc_197_cse = conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]));
+  assign ACC1_acc_197_cse = nl_ACC1_acc_197_cse[2:0];
+  assign nl_ACC1_acc_170_itm = ({1'b1 , (ACC1_acc_169_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_169_itm[2])) , (~ (ACC1_acc_169_itm[3]))});
+  assign ACC1_acc_170_itm = nl_ACC1_acc_170_itm[2:0];
+  assign nl_acc_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[9:0]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[19:10]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[29:20])) + 11'b11);
+  assign acc_psp_2_sva = nl_acc_psp_2_sva[11:0];
+  assign nl_ACC1_acc_141_itm = ({1'b1 , (ACC1_acc_140_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_140_itm[2])) , (~ (ACC1_acc_140_itm[3]))});
+  assign ACC1_acc_141_itm = nl_ACC1_acc_141_itm[2:0];
+  assign nl_ACC1_acc_140_itm = conv_s2s_3_4({(~ (ACC1_acc_116_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_116_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_140_itm = nl_ACC1_acc_140_itm[3:0];
+  assign nl_ACC1_acc_107_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_2_sva[1])) , (acc_psp_2_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_2_sva[0]) , (acc_psp_2_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[3])) , (~ (acc_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[5])) , (acc_psp_2_sva[6])})))) ,
+      (~ (acc_psp_2_sva[9]))}))));
+  assign ACC1_acc_107_psp_2_sva = nl_ACC1_acc_107_psp_2_sva[3:0];
+  assign nl_ACC1_acc_116_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_107_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_107_psp_2_sva[1])) , (ACC1_acc_107_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_107_psp_2_sva[3]));
+  assign ACC1_acc_116_psp_1_sva = nl_ACC1_acc_116_psp_1_sva[2:0];
+  assign nl_ACC1_acc_224_cse = conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11]));
+  assign ACC1_acc_224_cse = nl_ACC1_acc_224_cse[2:0];
+  assign nl_ACC1_acc_169_itm = conv_s2s_3_4({(~ (ACC1_acc_116_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_116_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_169_itm = nl_ACC1_acc_169_itm[3:0];
+  assign exit_FRAME_lpi_1_dfm_1_mx0 = MUX_s_1_2_2({(~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+      + 8'b10110101)))) , (exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm_4))},
+      FRAME_for_acc_itm[1]);
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign ACC1_acc_125_psp_1_lpi_1_dfm_mx0 = MUX_v_12_2_2({ACC1_acc_125_psp_1_sva
+      , ACC1_acc_125_psp_1_lpi_1_dfm}, and_cse);
+  assign acc_imod_18_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_150_itm[3:2]) , acc_imod_18_lpi_1_dfm_sg1},
+      and_cse);
+  assign ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0 = MUX_v_3_2_2({(ACC1_acc_148_itm[4:2])
+      , ACC1_acc_110_psp_2_lpi_1_dfm_sg1}, and_cse);
+  assign acc_imod_20_lpi_1_dfm_mx0 = MUX_v_2_2_2({(readslicef_3_2_1((({1'b1 , (ACC1_acc_150_itm[1])
+      , 1'b1}) + conv_u2s_2_3({(~ (ACC1_acc_150_itm[2])) , (~ (ACC1_acc_150_itm[3]))}))))
+      , acc_imod_20_lpi_1_dfm}, and_cse);
+  assign ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_118_psp_1_sva[2:1])
+      , ACC1_acc_118_psp_1_lpi_1_dfm_sg1}, and_cse);
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_3_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) |
+      FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+  assign and_cse = ~(exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva);
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      in_2_sva_1 <= 16'b0;
+      ACC1_acc_341_itm_1 <= 13'b0;
+      in_0_sva_1 <= 16'b0;
+      exit_FRAME_for_sva_1_st_1 <= 1'b0;
+      FRAME_for_acc_26_itm_1 <= 12'b0;
+      FRAME_for_slc_in_2_sva_itm_1 <= 12'b0;
+      exit_FRAME_for_lpi_1_dfm_3 <= 1'b0;
+      FRAME_for_acc_24_itm_1 <= 13'b0;
+      FRAME_for_slc_in_0_sva_itm_1 <= 12'b0;
+      i_6_sva_1 <= 2'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      ACC1_acc_110_psp_1_lpi_1_dfm_sg1 <= 3'b0;
+      ACC1_acc_125_psp_lpi_1_dfm <= 12'b0;
+      ACC1_acc_118_psp_lpi_1_dfm_sg1 <= 2'b0;
+      regs_regs_2_lpi_1_dfm_sg2 <= 30'b0;
+      regs_regs_2_lpi_1_dfm_1 <= 30'b0;
+      acc_imod_7_lpi_1_dfm <= 2'b0;
+      acc_imod_6_lpi_1_dfm_sg1 <= 2'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_1 <= 1'b0;
+      ACC1_acc_125_psp_1_lpi_1_dfm <= 12'b0;
+      acc_imod_18_lpi_1_dfm_sg1 <= 2'b0;
+      ACC1_acc_110_psp_2_lpi_1_dfm_sg1 <= 3'b0;
+      acc_imod_20_lpi_1_dfm <= 2'b0;
+      ACC1_acc_118_psp_1_lpi_1_dfm_sg1 <= 2'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({({((FRAME_acc_2_psp_sva[9:0])
+            | ({8'b0 , (FRAME_acc_2_psp_sva[11:10])})) , (FRAME_acc_2_psp_sva[9:6])
+            , ((FRAME_acc_2_psp_sva[5:0]) | ({4'b0 , (FRAME_acc_2_psp_sva[11:10])}))
+            , (FRAME_acc_2_psp_sva[9:0])}) , vout_rsc_mgc_out_stdreg_d}, ~(exit_FRAME_for_sva_1_st_1
+            & main_stage_0_2));
+        in_2_sva_1 <= MUX_v_16_2_2({in_2_sva_1 , in_2_sva_3}, main_stage_0_2);
+        ACC1_acc_341_itm_1 <= nl_ACC1_acc_341_itm_1[12:0];
+        in_0_sva_1 <= MUX_v_16_2_2({in_0_sva_1 , in_0_sva_3}, main_stage_0_2);
+        exit_FRAME_for_sva_1_st_1 <= ~ (FRAME_for_acc_itm[1]);
+        FRAME_for_acc_26_itm_1 <= nl_FRAME_for_acc_26_itm_1[11:0];
+        FRAME_for_slc_in_2_sva_itm_1 <= nl_FRAME_for_slc_in_2_sva_itm_1[11:0];
+        exit_FRAME_for_lpi_1_dfm_3 <= exit_FRAME_for_lpi_1_dfm_4;
+        FRAME_for_acc_24_itm_1 <= nl_FRAME_for_acc_24_itm_1[12:0];
+        FRAME_for_slc_in_0_sva_itm_1 <= nl_FRAME_for_slc_in_0_sva_itm_1[11:0];
+        i_6_sva_1 <= i_6_sva_2;
+        exit_FRAME_1_sva <= (~ (FRAME_for_acc_itm[1])) & exit_FRAME_lpi_1_dfm_1_mx0;
+        main_stage_0_2 <= 1'b1;
+        ACC1_acc_110_psp_1_lpi_1_dfm_sg1 <= ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0;
+        ACC1_acc_125_psp_lpi_1_dfm <= ACC1_acc_125_psp_lpi_1_dfm_mx0;
+        ACC1_acc_118_psp_lpi_1_dfm_sg1 <= ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0;
+        regs_regs_2_lpi_1_dfm_sg2 <= regs_regs_2_lpi_1_dfm_sg2_mx0;
+        regs_regs_2_lpi_1_dfm_1 <= regs_regs_2_lpi_1_dfm_1_mx0;
+        acc_imod_7_lpi_1_dfm <= acc_imod_7_lpi_1_dfm_mx0;
+        acc_imod_6_lpi_1_dfm_sg1 <= acc_imod_6_lpi_1_dfm_sg1_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_1 <= exit_FRAME_lpi_1_dfm_1_mx0;
+        ACC1_acc_125_psp_1_lpi_1_dfm <= ACC1_acc_125_psp_1_lpi_1_dfm_mx0;
+        acc_imod_18_lpi_1_dfm_sg1 <= acc_imod_18_lpi_1_dfm_sg1_mx0;
+        ACC1_acc_110_psp_2_lpi_1_dfm_sg1 <= ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0;
+        acc_imod_20_lpi_1_dfm <= acc_imod_20_lpi_1_dfm_mx0;
+        ACC1_acc_118_psp_1_lpi_1_dfm_sg1 <= ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0;
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_sva_1 , FRAME_p_1_lpi_1_dfm},
+            FRAME_for_acc_itm[1]);
+      end
+    end
+  end
+  assign nl_ACC1_acc_341_itm_1  = (conv_s2s_26_13(conv_u2s_2_13(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])) * 13'b1101000000001)
+      + conv_u2s_10_13((conv_u2u_9_10({conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[8])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[8])) * 6'b10101) , (ACC1_acc_125_psp_lpi_1_dfm_mx0[3])
+      , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}) + conv_u2u_8_10(conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[7])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[7])) * 8'b1010101) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[5])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[5])) * 6'b10101)) + conv_u2u_6_7({(ACC1_acc_125_psp_lpi_1_dfm_mx0[6])
+      , 1'b0 , (ACC1_acc_125_psp_lpi_1_dfm_mx0[4]) , 1'b0 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}))))
+      + conv_u2u_8_10((conv_u2u_7_8(signext_7_3({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (signext_2_1(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11]))})) + conv_u2u_6_8(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (acc_imod_18_lpi_1_dfm_sg1_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[4])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[2])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , ((ACC1_acc_125_psp_lpi_1_dfm_mx0[11]) & (~ (acc_imod_7_lpi_1_dfm_mx0[1]))
+      & (acc_imod_7_lpi_1_dfm_mx0[0]))}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[6])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[8])
+      , (~((acc_imod_7_lpi_1_dfm_mx0[1]) & (~ (ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))))})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[10])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (acc_imod_6_lpi_1_dfm_sg1_mx0[0])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[1])}))))))))) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[4:3]))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[6])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[8]) ,
+      (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[1])}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_125_psp_lpi_1_dfm_mx0[3])})))))) + conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_125_psp_lpi_1_dfm_mx0[2])
+      , (ACC1_acc_125_psp_lpi_1_dfm_mx0[0]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[2])
+      , (ACC1_acc_125_psp_lpi_1_dfm_mx0[1]) , (ACC1_acc_125_psp_lpi_1_dfm_mx0[2])}))))
+      , 1'b1}) + conv_u2u_4_5({(~ (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[2])) , 1'b1
+      , (~ (acc_imod_6_lpi_1_dfm_sg1_mx0[1])) , ((ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      & (~ (acc_imod_20_lpi_1_dfm_mx0[1])) & (acc_imod_20_lpi_1_dfm_mx0[0]))}))))))
+      + conv_u2u_4_7((readslicef_5_4_1((conv_u2u_4_5({(~ (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[2]))
+      , 1'b1 , (~ (acc_imod_18_lpi_1_dfm_sg1_mx0[1])) , 1'b1}) + conv_s2u_3_5({ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0
+      , (~((acc_imod_20_lpi_1_dfm_mx0[1]) & (~ (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11]))))}))))
+      + (readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_s2s_3_5({ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0 , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[1])})))))))))
+      + (conv_s2s_11_13(conv_u2s_10_12(conv_u2s_20_11(conv_u2u_2_10(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[9])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[9])) * 10'b101010101)) + conv_s2s_9_11(conv_s2s_7_9(conv_u2s_6_7({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[6])
+      , 1'b0 , (ACC1_acc_125_psp_lpi_1_dfm_mx0[6]) , 1'b0 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))})
+      + conv_s2s_5_7(({(conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[4]) + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[6]))
+      , (conv_u2u_2_3(signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[10])) + conv_u2u_2_3(signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])))})
+      + ({3'b100 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}))) + conv_u2s_7_9(signext_7_3({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))})))) + conv_u2s_11_13({conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[10])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[10])) * 8'b1010101) , (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[3])
+      , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}));
+  assign nl_FRAME_for_acc_26_itm_1  = (conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+      , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_sg2_mx0[19:10])
+      , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})))
+      + conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+      , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_sg2_mx0[9:0]) ,
+      10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))
+      + conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+      , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_sg2_mx0[29:20])
+      , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign nl_FRAME_for_slc_in_2_sva_itm_1  = conv_s2s_11_12(conv_u2s_10_11({(acc_10_psp_1_sva[11])
+      , 8'b0 , (acc_10_psp_1_sva[11])}) + (conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_10_psp_1_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_113_psp_1_sva[3])
+      , (acc_10_psp_1_sva[4])})))) + conv_s2s_2_3(ACC1_acc_120_psp_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_10_psp_1_sva[3])
+      , (acc_10_psp_1_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_113_psp_1_sva[3])
+      , (acc_10_psp_1_sva[2]) , (ACC1_acc_113_psp_1_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_10_psp_1_sva[7])
+      , (acc_10_psp_1_sva[4]) , (signext_2_1(acc_10_psp_1_sva[11]))}) + conv_u2u_3_5(ACC1_acc_250_cse)))
+      + conv_u2s_7_8({(acc_10_psp_1_sva[8]) , 1'b0 , (acc_10_psp_1_sva[8]) , 1'b0
+      , (acc_10_psp_1_sva[8]) , 1'b0 , (acc_10_psp_1_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_10_psp_1_sva[11])
+      , (signext_2_1(acc_10_psp_1_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_10_psp_1_sva[6])
+      , 1'b0 , (acc_10_psp_1_sva[6]) , 1'b0 , (acc_10_psp_1_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_250_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[9]) , ((acc_10_psp_1_sva[11])
+      & (~ (ACC1_acc_188_itm[2])) & (ACC1_acc_188_itm[1]))}))))))))) + conv_u2s_10_11({(acc_10_psp_1_sva[11])
+      , 1'b0 , (acc_10_psp_1_sva[11]) , 1'b0 , (acc_10_psp_1_sva[11]) , 1'b0 , (acc_10_psp_1_sva[11])
+      , 1'b0 , (signext_2_1(acc_10_psp_1_sva[11]))}))) + (conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_10_psp_2_sva[10])
+      , 1'b0 , (acc_10_psp_2_sva[10]) , 1'b0 , (acc_10_psp_2_sva[10]) , 1'b0 , (acc_10_psp_2_sva[10])
+      , 1'b0 , (acc_10_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_10_psp_2_sva[9]) ,
+      1'b0 , (acc_10_psp_2_sva[9]) , 1'b0 , (acc_10_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_10_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_10_psp_2_sva[7]) , 1'b0 , (acc_10_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_10_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (~((ACC1_acc_161_itm[2])
+      & (~ (acc_10_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (~ (ACC1_acc_160_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (ACC1_acc_160_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (ACC1_acc_113_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_10_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_113_psp_2_sva[3])
+      , (acc_10_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_120_psp_1_sva[2:1])) +
+      (readslicef_5_4_1((conv_u2s_3_5({(acc_10_psp_2_sva[3]) , (acc_10_psp_2_sva[1])
+      , 1'b1}) + conv_s2s_3_5({(ACC1_acc_113_psp_2_sva[3]) , (acc_10_psp_2_sva[2])
+      , (ACC1_acc_113_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_10_psp_2_sva[7])
+      , (acc_10_psp_2_sva[4]) , (signext_2_1(acc_10_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_277_cse)))
+      + conv_u2s_7_8({(acc_10_psp_2_sva[8]) , 1'b0 , (acc_10_psp_2_sva[8]) , 1'b0
+      , (acc_10_psp_2_sva[8]) , 1'b0 , (acc_10_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_10_psp_2_sva[11])
+      , (signext_2_1(acc_10_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_10_psp_2_sva[6])
+      , 1'b0 , (acc_10_psp_2_sva[6]) , 1'b0 , (acc_10_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_277_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[9]) , ((acc_10_psp_2_sva[11])
+      & (~ (ACC1_acc_161_itm[2])) & (ACC1_acc_161_itm[1]))})))))))))) + ({(acc_10_psp_2_sva[11])
+      , 2'b0 , (acc_10_psp_2_sva[11]) , 1'b0 , (acc_10_psp_2_sva[11]) , 1'b0 , (acc_10_psp_2_sva[11])
+      , (conv_u2u_1_3(acc_10_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11])))}))
+      + conv_u2s_10_12(conv_u2u_9_10({(acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10])
+      , 1'b0 , (acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10])})
+      + conv_u2u_8_10(({(acc_10_psp_1_sva[9]) , 1'b0 , (acc_10_psp_1_sva[9]) , 1'b0
+      , (acc_10_psp_1_sva[9]) , 1'b0 , (signext_2_1(acc_10_psp_1_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_10_psp_1_sva[7])
+      , 1'b0 , (acc_10_psp_1_sva[5]) , 1'b0 , (signext_2_1(acc_10_psp_1_sva[11]))})
+      + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (~((ACC1_acc_188_itm[2])
+      & (~ (acc_10_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (~ (ACC1_acc_187_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (ACC1_acc_187_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (ACC1_acc_113_psp_1_sva[2])})))))))))));
+  assign nl_FRAME_for_acc_24_itm_1  = (conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+      , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_1_mx0[19:10]) ,
+      10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm}))) + conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0])
+      , (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_1_mx0[9:0]) , 10'b0},
+      i_6_lpi_1_dfm)) * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})))) + conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+      , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_1_mx0[29:20]) ,
+      10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign nl_FRAME_for_slc_in_0_sva_itm_1  = conv_s2s_11_12(conv_u2s_10_11({(acc_psp_1_sva[11])
+      , 8'b0 , (acc_psp_1_sva[11])}) + (conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_psp_1_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_107_psp_1_sva[3]) ,
+      (acc_psp_1_sva[4])})))) + conv_s2s_2_3(ACC1_acc_116_psp_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_1_sva[3])
+      , (acc_psp_1_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_107_psp_1_sva[3]) ,
+      (acc_psp_1_sva[2]) , (ACC1_acc_107_psp_1_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_1_sva[7])
+      , (acc_psp_1_sva[4]) , (signext_2_1(acc_psp_1_sva[11]))}) + conv_u2u_3_5(ACC1_acc_197_cse)))
+      + conv_u2s_7_8({(acc_psp_1_sva[8]) , 1'b0 , (acc_psp_1_sva[8]) , 1'b0 , (acc_psp_1_sva[8])
+      , 1'b0 , (acc_psp_1_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_1_sva[11])
+      , (signext_2_1(acc_psp_1_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_1_sva[6])
+      , 1'b0 , (acc_psp_1_sva[6]) , 1'b0 , (acc_psp_1_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_197_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[9]) , ((acc_psp_1_sva[11])
+      & (~ (ACC1_acc_170_itm[2])) & (ACC1_acc_170_itm[1]))}))))))))) + conv_u2s_10_11({(acc_psp_1_sva[11])
+      , 1'b0 , (acc_psp_1_sva[11]) , 1'b0 , (acc_psp_1_sva[11]) , 1'b0 , (acc_psp_1_sva[11])
+      , 1'b0 , (signext_2_1(acc_psp_1_sva[11]))}))) + (conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_psp_2_sva[9]) , 1'b0
+      , (acc_psp_2_sva[9]) , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_2_sva[7]) , 1'b0 , (acc_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~((ACC1_acc_141_itm[2])
+      & (~ (acc_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~ (ACC1_acc_140_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_140_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_107_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_107_psp_2_sva[3]) ,
+      (acc_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_116_psp_1_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_2_sva[3])
+      , (acc_psp_2_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_107_psp_2_sva[3]) ,
+      (acc_psp_2_sva[2]) , (ACC1_acc_107_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_2_sva[7])
+      , (acc_psp_2_sva[4]) , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_224_cse)))
+      + conv_u2s_7_8({(acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])
+      , 1'b0 , (acc_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_2_sva[6])
+      , 1'b0 , (acc_psp_2_sva[6]) , 1'b0 , (acc_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_224_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , ((acc_psp_2_sva[11])
+      & (~ (ACC1_acc_141_itm[2])) & (ACC1_acc_141_itm[1]))})))))))))) + ({(acc_psp_2_sva[11])
+      , 2'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11])
+      , (conv_u2u_1_3(acc_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])))}))
+      + conv_u2s_10_12(conv_u2u_9_10({(acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10])
+      , 1'b0 , (acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10])})
+      + conv_u2u_8_10(({(acc_psp_1_sva[9]) , 1'b0 , (acc_psp_1_sva[9]) , 1'b0 , (acc_psp_1_sva[9])
+      , 1'b0 , (signext_2_1(acc_psp_1_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_1_sva[7])
+      , 1'b0 , (acc_psp_1_sva[5]) , 1'b0 , (signext_2_1(acc_psp_1_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (~((ACC1_acc_170_itm[2])
+      & (~ (acc_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (~ (ACC1_acc_169_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_169_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_107_psp_1_sva[2])})))))))))));
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] MUX_v_3_2_2;
+    input [5:0] inputs;
+    input [0:0] sel;
+    reg [2:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[5:3];
+      end
+      1'b1 : begin
+        result = inputs[2:0];
+      end
+      default : begin
+        result = inputs[5:3];
+      end
+    endcase
+    MUX_v_3_2_2 = result;
+  end
+  endfunction
+
+
+  function [11:0] MUX_v_12_2_2;
+    input [23:0] inputs;
+    input [0:0] sel;
+    reg [11:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[23:12];
+      end
+      1'b1 : begin
+        result = inputs[11:0];
+      end
+      default : begin
+        result = inputs[23:12];
+      end
+    endcase
+    MUX_v_12_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] MUX_v_2_2_2;
+    input [3:0] inputs;
+    input [0:0] sel;
+    reg [1:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[3:2];
+      end
+      1'b1 : begin
+        result = inputs[1:0];
+      end
+      default : begin
+        result = inputs[3:2];
+      end
+    endcase
+    MUX_v_2_2_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [6:0] signext_7_3;
+    input [2:0] vector;
+  begin
+    signext_7_3= {{4{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_2;
+    input [1:0] vector;
+  begin
+    signext_3_2= {{1{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_13_16 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_16 = {{3{vector[12]}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_13_16 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2u_13_16 = {{3{vector[12]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_26_13 ;
+    input signed [25:0]  vector ;
+  begin
+    conv_s2s_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_12_6 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_6 = vector[5:0];
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_2_6 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_6 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_2_8 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_8 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_4_7 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_7 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_s2u_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2u_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_11_13 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_13 = {{2{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_9_11 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_11 = {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2s_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_6_8 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_8 = {{2{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2s_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v7/cycle.rpt b/Sobel/sobel.v7/cycle.rpt
new file mode 100644
index 0000000..b5dda20
--- /dev/null
+++ b/Sobel/sobel.v7/cycle.rpt
@@ -0,0 +1,85 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 15:19:30 +0000 2016                      
+
+Solution Settings: sobel.v7
+  Current state: schedule
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       444  921601     921600            0  1          
+    Design Total:                     444  921601     921600            0  0          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /sobel/core              
+    
+  I/O Data Ranges
+    Port       Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ---------- ---- -------- --------- --------- ------- -------- --------
+    vin:rsc.z  IN   Unsigned        90                                     
+    clk        IN   Unsigned         1                                     
+    en         IN   Unsigned         1                                     
+    arst_n     IN   Unsigned         1                                     
+    vout:rsc.z OUT  Unsigned        30                                     
+    
+  Memory Resources
+    Resource Name: /sobel/vin:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 90
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable   Indices Phys Memory Address     
+      ---------- ------- -----------------------
+      /sobel/vin    0:89 00000000-00000000 (0-0) 
+      
+    Resource Name: /sobel/vout:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 30
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable    Indices Phys Memory Address     
+      ----------- ------- -----------------------
+      /sobel/vout    0:29 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process     Loop             Iterations C-Steps Total Cycles  Duration  Unroll Init Comments 
+    ----------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
+    /sobel/core core:rlp           Infinite       0       921602  18.43 ms                       
+    /sobel/core   main             Infinite       3       921602  18.43 ms            1          
+    
+  Loop Execution Profile
+    Process     Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------- ---------------- ------------ -------------------------- ----------------- --------
+    /sobel/core core:rlp                   0                        0.00           921600           
+    /sobel/core   main                921602                      100.00           921600           
+    
+  End of Report
diff --git a/Sobel/sobel.v7/cycle.v b/Sobel/sobel.v7/cycle.v
new file mode 100644
index 0000000..618b4d9
--- /dev/null
+++ b/Sobel/sobel.v7/cycle.v
@@ -0,0 +1,1529 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 15:19:31 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg [18:0] FRAME_p_1_lpi_1;
+    reg [89:0] regs_regs_1_sva;
+    reg [89:0] regs_regs_0_sva;
+    reg exit_FRAME_1_sva;
+    reg [18:0] FRAME_p_1_lpi_1_dfm;
+    reg exit_FRAME_for_lpi_1_dfm;
+    reg [89:0] regs_regs_0_sva_1;
+    reg [11:0] acc_psp_2_sva;
+    reg [3:0] ACC1_acc_107_psp_2_sva;
+    reg [2:0] ACC1_acc_116_psp_1_sva;
+    reg [2:0] acc_imod_14_sva;
+    reg [1:0] acc_imod_16_sva;
+    reg [11:0] ACC1_acc_125_psp_1_sva;
+    reg [3:0] ACC1_acc_110_psp_2_sva;
+    reg [2:0] ACC1_acc_118_psp_1_sva;
+    reg [2:0] acc_imod_18_sva;
+    reg [1:0] acc_imod_20_sva;
+    reg [11:0] acc_10_psp_2_sva;
+    reg [3:0] ACC1_acc_113_psp_2_sva;
+    reg [2:0] ACC1_acc_120_psp_1_sva;
+    reg [2:0] acc_imod_22_sva;
+    reg [1:0] acc_imod_24_sva;
+    reg [11:0] acc_psp_1_sva;
+    reg [3:0] ACC1_acc_107_psp_1_sva;
+    reg [2:0] ACC1_acc_116_psp_sva;
+    reg [2:0] acc_imod_2_sva;
+    reg [1:0] acc_imod_3_sva;
+    reg [11:0] ACC1_acc_125_psp_sva;
+    reg [3:0] ACC1_acc_110_psp_1_sva;
+    reg [2:0] ACC1_acc_118_psp_sva;
+    reg [2:0] acc_imod_6_sva;
+    reg [11:0] acc_10_psp_1_sva;
+    reg [3:0] ACC1_acc_113_psp_1_sva;
+    reg [2:0] ACC1_acc_120_psp_sva;
+    reg [2:0] acc_imod_10_sva;
+    reg [1:0] acc_imod_11_sva;
+    reg [1:0] acc_imod_7_lpi_1_dfm;
+    reg [89:0] regs_regs_0_sva_dfm;
+    reg [89:0] regs_regs_1_sva_dfm;
+    reg [11:0] ACC1_acc_125_psp_lpi_1_dfm;
+    reg [1:0] i_6_lpi_1_dfm;
+    reg [1:0] acc_imod_20_lpi_1_dfm;
+    reg [11:0] ACC1_acc_125_psp_1_lpi_1_dfm;
+    reg FRAME_for_slc_YMATRIX_rom_11_psp_sva;
+    reg [15:0] in_0_sva_1;
+    reg [15:0] in_2_sva_1;
+    reg [1:0] i_6_sva_1;
+    reg exit_FRAME_for_sva_1;
+    reg [14:0] intensity_2_sg1_sva;
+    reg [5:0] acc_imod_12_sva;
+    reg [11:0] FRAME_acc_2_psp_sva;
+    reg [18:0] FRAME_p_1_sva_1;
+    reg exit_FRAME_lpi_1_dfm_1;
+    reg exit_FRAME_for_lpi_1_dfm_2;
+    reg exit_FRAME_for_lpi_1_dfm_3;
+    reg [12:0] FRAME_for_acc_24_itm_1;
+    reg [11:0] FRAME_for_slc_in_0_sva_itm_1;
+    reg [11:0] FRAME_for_acc_26_itm_1;
+    reg [11:0] FRAME_for_slc_in_2_sva_itm_1;
+    reg [12:0] ACC1_acc_341_itm;
+    reg [12:0] ACC1_acc_341_itm_1;
+    reg exit_FRAME_for_sva_1_st_1;
+    reg main_stage_0_2;
+    reg [11:0] in_0_sva_2;
+    reg [11:0] in_2_sva_2;
+    reg [1:0] acc_imod_6_lpi_1_dfm_sg1;
+    reg [29:0] regs_regs_2_lpi_1_dfm_sg2;
+    reg [29:0] regs_regs_2_lpi_1_dfm_1;
+    reg [1:0] ACC1_acc_118_psp_lpi_1_dfm_sg1;
+    reg [2:0] ACC1_acc_110_psp_1_lpi_1_dfm_sg1;
+    reg [1:0] acc_imod_18_lpi_1_dfm_sg1;
+    reg [1:0] ACC1_acc_118_psp_1_lpi_1_dfm_sg1;
+    reg [2:0] ACC1_acc_110_psp_2_lpi_1_dfm_sg1;
+    reg [2:0] ACC1_acc_197_cse;
+    reg [2:0] ACC1_acc_224_cse;
+    reg [2:0] ACC1_acc_250_cse;
+    reg [2:0] ACC1_acc_277_cse;
+    reg FRAME_for_nor_cse;
+    reg FRAME_for_slc_XMATRIX_rom_10_psp_sva_1;
+
+    reg[15:0] FRAME_for_mux_11_nl;
+    reg[15:0] FRAME_for_mux_12_nl;
+    reg[9:0] regs_operator_10_mux_nl;
+    reg[9:0] regs_operator_11_mux_nl;
+    reg[9:0] regs_operator_9_mux_nl;
+    reg[9:0] regs_operator_16_mux_nl;
+    reg[9:0] regs_operator_17_mux_nl;
+    reg[9:0] regs_operator_15_mux_nl;
+    begin : core_rlpExit
+      forever begin : core_rlp
+        // C-Step 0 of Loop 'core_rlp'
+        FRAME_p_1_lpi_1 = 19'b0;
+        regs_regs_1_sva = 90'b0;
+        regs_regs_0_sva = 90'b0;
+        exit_FRAME_1_sva = 1'b1;
+        main_stage_0_2 = 1'b0;
+        begin : mainExit
+          forever begin : main
+            // C-Step 0 of Loop 'main'
+            begin : waitLoop0Exit
+              forever begin : waitLoop0
+                @(posedge clk or negedge ( arst_n ));
+                if ( ~ arst_n )
+                  disable core_rlpExit;
+                if ( en )
+                  disable waitLoop0Exit;
+              end
+            end
+            // C-Step 1 of Loop 'main'
+            if ( main_stage_0_2 ) begin
+              FRAME_for_mux_11_nl = MUX_v_16_2_2({in_0_sva_1 , ({{4{FRAME_for_slc_in_0_sva_itm_1[11]}},
+                  FRAME_for_slc_in_0_sva_itm_1})}, exit_FRAME_for_lpi_1_dfm_3);
+              in_0_sva_1 = conv_s2u_13_16(FRAME_for_acc_24_itm_1) + (FRAME_for_mux_11_nl);
+              FRAME_for_mux_12_nl = MUX_v_16_2_2({in_2_sva_1 , ({{4{FRAME_for_slc_in_2_sva_itm_1[11]}},
+                  FRAME_for_slc_in_2_sva_itm_1})}, exit_FRAME_for_lpi_1_dfm_3);
+              in_2_sva_1 = conv_s2u_12_16(FRAME_for_acc_26_itm_1) + (FRAME_for_mux_12_nl);
+              if ( exit_FRAME_for_sva_1_st_1 ) begin
+                intensity_2_sg1_sva = readslicef_16_15_1(((in_2_sva_1 + conv_s2s_13_16(ACC1_acc_341_itm_1))
+                    + in_0_sva_1));
+                acc_imod_12_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(intensity_2_sg1_sva[8:6])
+                    + conv_u2u_3_4(~ (intensity_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                    (intensity_2_sg1_sva[14])) , 1'b1 , (~ (intensity_2_sg1_sva[14]))})
+                    + conv_u2u_2_4(intensity_2_sg1_sva[13:12]))) + conv_u2u_4_6(conv_u2u_3_4(intensity_2_sg1_sva[2:0])
+                    + conv_u2u_3_4(~ (intensity_2_sg1_sva[5:3])))) + 6'b101011;
+                FRAME_acc_2_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(intensity_2_sg1_sva[13:12])
+                    * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(intensity_2_sg1_sva[11:9])
+                    * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(intensity_2_sg1_sva[8:3])
+                    + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_12_sva[5]))
+                    , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_12_sva[2:0])
+                    , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_12_sva[5:3])) , (~ (acc_imod_12_sva[5]))})))))})
+                    + conv_u2u_2_4(acc_imod_12_sva[4:3])) + conv_u2u_3_5(~ (intensity_2_sg1_sva[8:6])))
+                    + ({4'b1001 , (acc_imod_12_sva[5])}))))) + conv_u2u_11_12(signext_11_9({(intensity_2_sg1_sva[14])
+                    , 3'b0 , (signext_3_1(intensity_2_sg1_sva[14])) , 1'b0 , (intensity_2_sg1_sva[14])}));
+                vout_rsc_mgc_out_stdreg_d <= {((FRAME_acc_2_psp_sva[9:0]) | ({8'b0,
+                    FRAME_acc_2_psp_sva[11:10]})) , (FRAME_acc_2_psp_sva[9:6]) ,
+                    ((FRAME_acc_2_psp_sva[5:0]) | ({4'b0, FRAME_acc_2_psp_sva[11:10]}))
+                    , (FRAME_acc_2_psp_sva[9:0])};
+              end
+            end
+            FRAME_p_1_sva_1 = 19'b0;
+            in_2_sva_2 = 12'b0;
+            in_0_sva_2 = 12'b0;
+            acc_imod_20_sva = 2'b0;
+            acc_imod_18_sva = 3'b0;
+            ACC1_acc_118_psp_1_sva = 3'b0;
+            ACC1_acc_110_psp_2_sva = 4'b0;
+            ACC1_acc_125_psp_1_sva = 12'b0;
+            FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+            exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_lpi_1_dfm_2 | exit_FRAME_1_sva;
+            if ( exit_FRAME_for_lpi_1_dfm ) begin
+              regs_regs_0_sva_1 = vin_rsc_mgc_in_wire_d;
+              acc_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (regs_regs_0_sva_1[9:0]))
+                  + conv_s2s_10_11(~ (regs_regs_0_sva_1[19:10]))) + conv_s2s_11_12(conv_s2s_10_11(~
+                  (regs_regs_0_sva_1[29:20])) + 11'b11);
+              ACC1_acc_107_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                  (acc_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_2_sva[1]))
+                  , (acc_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_2_sva[0])
+                  , (acc_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[2])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[3])) , (~ (acc_psp_2_sva[7]))}))))
+                  , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[4])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[5])) , (acc_psp_2_sva[6])}))))
+                  , (~ (acc_psp_2_sva[9]))}))));
+              ACC1_acc_116_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_107_psp_2_sva[0])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_107_psp_2_sva[1])) , (ACC1_acc_107_psp_2_sva[2])}))))
+                  + conv_s2s_1_3(~ (ACC1_acc_107_psp_2_sva[3]));
+              acc_imod_14_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_116_psp_1_sva[2:1]))
+                  , 1'b1}) + conv_u2s_2_4({(ACC1_acc_116_psp_1_sva[0]) , 1'b1})));
+              acc_imod_16_sva = readslicef_3_2_1((({1'b1 , (acc_imod_14_sva[0]) ,
+                  1'b1}) + conv_u2s_2_3({(~ (acc_imod_14_sva[1])) , (~ (acc_imod_14_sva[2]))})));
+              ACC1_acc_125_psp_1_sva = conv_s2u_11_12(conv_s2s_10_11(~ (regs_regs_0_sva_1[39:30]))
+                  + conv_s2s_10_11(~ (regs_regs_0_sva_1[49:40]))) + conv_s2u_11_12(conv_s2s_10_11(~
+                  (regs_regs_0_sva_1[59:50])) + 11'b11);
+              ACC1_acc_110_psp_2_sva = readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((({2'b10
+                  , (~ (ACC1_acc_125_psp_1_sva[0])) , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_1_sva[1])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_1_sva[2])) , (~ (ACC1_acc_125_psp_1_sva[6]))}))))
+                  , (~ (ACC1_acc_125_psp_1_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_1_sva[3])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_1_sva[4])) , (ACC1_acc_125_psp_1_sva[5])}))))
+                  , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_125_psp_1_sva[11:10])) ,
+                  (ACC1_acc_125_psp_1_sva[7])})))) , (ACC1_acc_125_psp_1_sva[9])})));
+              ACC1_acc_118_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_110_psp_2_sva[0])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_110_psp_2_sva[1])) , (ACC1_acc_110_psp_2_sva[2])}))))
+                  + conv_s2s_1_3(~ (ACC1_acc_110_psp_2_sva[3]));
+              acc_imod_18_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_118_psp_1_sva[2:1]))
+                  , 1'b1}) + conv_u2s_2_4({(ACC1_acc_118_psp_1_sva[0]) , 1'b1})));
+              acc_imod_20_sva = readslicef_3_2_1((({1'b1 , (acc_imod_18_sva[0]) ,
+                  1'b1}) + conv_u2s_2_3({(~ (acc_imod_18_sva[1])) , (~ (acc_imod_18_sva[2]))})));
+              acc_10_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (regs_regs_0_sva_1[69:60]))
+                  + conv_s2s_10_11(~ (regs_regs_0_sva_1[79:70]))) + conv_s2s_11_12(conv_s2s_10_11(~
+                  (regs_regs_0_sva_1[89:80])) + 11'b11);
+              ACC1_acc_113_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                  (acc_10_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_10_psp_2_sva[1]))
+                  , (acc_10_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_10_psp_2_sva[0])
+                  , (acc_10_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_2_sva[2])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_2_sva[3])) , (~ (acc_10_psp_2_sva[7]))}))))
+                  , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_2_sva[4])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_2_sva[5])) , (acc_10_psp_2_sva[6])}))))
+                  , (~ (acc_10_psp_2_sva[9]))}))));
+              ACC1_acc_120_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_113_psp_2_sva[0])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_113_psp_2_sva[1])) , (ACC1_acc_113_psp_2_sva[2])}))))
+                  + conv_s2s_1_3(~ (ACC1_acc_113_psp_2_sva[3]));
+              acc_imod_22_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_120_psp_1_sva[2:1]))
+                  , 1'b1}) + conv_u2s_2_4({(ACC1_acc_120_psp_1_sva[0]) , 1'b1})));
+              acc_imod_24_sva = readslicef_3_2_1((({1'b1 , (acc_imod_22_sva[0]) ,
+                  1'b1}) + conv_u2s_2_3({(~ (acc_imod_22_sva[1])) , (~ (acc_imod_22_sva[2]))})));
+              acc_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_1_sva[19:10])
+                  + conv_s2s_10_11(regs_regs_1_sva[9:0])) + conv_s2s_10_12(regs_regs_1_sva[29:20]);
+              ACC1_acc_107_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                  (acc_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_1_sva[1]))
+                  , (acc_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_1_sva[0])
+                  , (acc_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[2])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[3])) , (~ (acc_psp_1_sva[7]))}))))
+                  , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[4])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[5])) , (acc_psp_1_sva[6])}))))
+                  , (~ (acc_psp_1_sva[9]))}))));
+              ACC1_acc_116_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_107_psp_1_sva[0])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_107_psp_1_sva[1])) , (ACC1_acc_107_psp_1_sva[2])}))))
+                  + conv_s2s_1_3(~ (ACC1_acc_107_psp_1_sva[3]));
+              acc_imod_2_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_116_psp_sva[2:1]))
+                  , 1'b1}) + conv_u2s_2_4({(ACC1_acc_116_psp_sva[0]) , 1'b1})));
+              acc_imod_3_sva = readslicef_3_2_1((({1'b1 , (acc_imod_2_sva[0]) , 1'b1})
+                  + conv_u2s_2_3({(~ (acc_imod_2_sva[1])) , (~ (acc_imod_2_sva[2]))})));
+              ACC1_acc_125_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_1_sva[49:40])
+                  + conv_s2s_10_11(regs_regs_1_sva[39:30])) + conv_s2u_10_12(regs_regs_1_sva[59:50]);
+              ACC1_acc_110_psp_1_sva = readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((({2'b10
+                  , (~ (ACC1_acc_125_psp_sva[0])) , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_sva[1])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_sva[2])) , (~ (ACC1_acc_125_psp_sva[6]))}))))
+                  , (~ (ACC1_acc_125_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_sva[3])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_sva[4])) , (ACC1_acc_125_psp_sva[5])}))))
+                  , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_125_psp_sva[11:10])) , (ACC1_acc_125_psp_sva[7])}))))
+                  , (ACC1_acc_125_psp_sva[9])})));
+              ACC1_acc_118_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_110_psp_1_sva[0])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_110_psp_1_sva[1])) , (ACC1_acc_110_psp_1_sva[2])}))))
+                  + conv_s2s_1_3(~ (ACC1_acc_110_psp_1_sva[3]));
+              acc_imod_6_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_118_psp_sva[2:1]))
+                  , 1'b1}) + conv_u2s_2_4({(ACC1_acc_118_psp_sva[0]) , 1'b1})));
+              acc_10_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_1_sva[79:70])
+                  + conv_s2s_10_11(regs_regs_1_sva[69:60])) + conv_s2s_10_12(regs_regs_1_sva[89:80]);
+              ACC1_acc_113_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                  (acc_10_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_10_psp_1_sva[1]))
+                  , (acc_10_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_10_psp_1_sva[0])
+                  , (acc_10_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_1_sva[2])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_1_sva[3])) , (~ (acc_10_psp_1_sva[7]))}))))
+                  , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_1_sva[4])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_1_sva[5])) , (acc_10_psp_1_sva[6])}))))
+                  , (~ (acc_10_psp_1_sva[9]))}))));
+              ACC1_acc_120_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_113_psp_1_sva[0])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_113_psp_1_sva[1])) , (ACC1_acc_113_psp_1_sva[2])}))))
+                  + conv_s2s_1_3(~ (ACC1_acc_113_psp_1_sva[3]));
+              acc_imod_10_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_120_psp_sva[2:1]))
+                  , 1'b1}) + conv_u2s_2_4({(ACC1_acc_120_psp_sva[0]) , 1'b1})));
+              acc_imod_11_sva = readslicef_3_2_1((({1'b1 , (acc_imod_10_sva[0]) ,
+                  1'b1}) + conv_u2s_2_3({(~ (acc_imod_10_sva[1])) , (~ (acc_imod_10_sva[2]))})));
+              ACC1_acc_197_cse = conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]));
+              ACC1_acc_224_cse = conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11]));
+              in_0_sva_2 = conv_s2s_11_12(conv_u2s_10_11({(acc_psp_1_sva[11]) , 8'b0
+                  , (acc_psp_1_sva[11])}) + (conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+                  , (acc_psp_1_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_107_psp_1_sva[3])
+                  , (acc_psp_1_sva[4])})))) + conv_s2s_2_3(ACC1_acc_116_psp_sva[2:1]))
+                  + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_1_sva[3]) , (acc_psp_1_sva[1])
+                  , 1'b1}) + conv_s2s_3_5({(ACC1_acc_107_psp_1_sva[3]) , (acc_psp_1_sva[2])
+                  , (ACC1_acc_107_psp_1_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_1_sva[7])
+                  , (acc_psp_1_sva[4]) , (signext_2_1(acc_psp_1_sva[11]))}) + conv_u2u_3_5(ACC1_acc_197_cse)))
+                  + conv_u2s_7_8({(acc_psp_1_sva[8]) , 1'b0 , (acc_psp_1_sva[8])
+                  , 1'b0 , (acc_psp_1_sva[8]) , 1'b0 , (acc_psp_1_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_1_sva[11])
+                  , (signext_2_1(acc_psp_1_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_1_sva[6])
+                  , 1'b0 , (acc_psp_1_sva[6]) , 1'b0 , (acc_psp_1_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_197_cse)
+                  + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[7])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[9]) , ((acc_psp_1_sva[11])
+                  & (~ (acc_imod_3_sva[1])) & (acc_imod_3_sva[0]))}))))))))) + conv_u2s_10_11({(acc_psp_1_sva[11])
+                  , 1'b0 , (acc_psp_1_sva[11]) , 1'b0 , (acc_psp_1_sva[11]) , 1'b0
+                  , (acc_psp_1_sva[11]) , 1'b0 , (signext_2_1(acc_psp_1_sva[11]))})))
+                  + (conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_psp_2_sva[10])
+                  , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10]) , 1'b0
+                  , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_psp_2_sva[9])
+                  , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 , (acc_psp_2_sva[9]) , 1'b0
+                  , (signext_2_1(acc_psp_2_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_2_sva[7])
+                  , 1'b0 , (acc_psp_2_sva[5]) , 1'b0 , (signext_2_1(acc_psp_2_sva[11]))})
+                  + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~((acc_imod_16_sva[1])
+                  & (~ (acc_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~
+                  (acc_imod_14_sva[2]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (acc_imod_14_sva[1])})))))
+                  + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_107_psp_2_sva[2])}))))))))))
+                  + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+                  , (acc_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_107_psp_2_sva[3])
+                  , (acc_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_116_psp_1_sva[2:1]))
+                  + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_2_sva[3]) , (acc_psp_2_sva[1])
+                  , 1'b1}) + conv_s2s_3_5({(ACC1_acc_107_psp_2_sva[3]) , (acc_psp_2_sva[2])
+                  , (ACC1_acc_107_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_2_sva[7])
+                  , (acc_psp_2_sva[4]) , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_224_cse)))
+                  + conv_u2s_7_8({(acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])
+                  , 1'b0 , (acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+                  , (signext_2_1(acc_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_2_sva[6])
+                  , 1'b0 , (acc_psp_2_sva[6]) , 1'b0 , (acc_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_224_cse)
+                  + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , ((acc_psp_2_sva[11])
+                  & (~ (acc_imod_16_sva[1])) & (acc_imod_16_sva[0]))})))))))))) +
+                  ({(acc_psp_2_sva[11]) , 2'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11])
+                  , 1'b0 , (acc_psp_2_sva[11]) , (conv_u2u_1_3(acc_psp_2_sva[11])
+                  + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])))})) + conv_u2s_10_12(conv_u2u_9_10({(acc_psp_1_sva[10])
+                  , 1'b0 , (acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10]) , 1'b0
+                  , (acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10])}) + conv_u2u_8_10(({(acc_psp_1_sva[9])
+                  , 1'b0 , (acc_psp_1_sva[9]) , 1'b0 , (acc_psp_1_sva[9]) , 1'b0
+                  , (signext_2_1(acc_psp_1_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_1_sva[7])
+                  , 1'b0 , (acc_psp_1_sva[5]) , 1'b0 , (signext_2_1(acc_psp_1_sva[11]))})
+                  + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (~((acc_imod_3_sva[1])
+                  & (~ (acc_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (~
+                  (acc_imod_2_sva[2]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (acc_imod_2_sva[1])})))))
+                  + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_107_psp_1_sva[2])})))))))))));
+              ACC1_acc_250_cse = conv_u2u_2_3(signext_2_1(acc_10_psp_1_sva[11]))
+                  + conv_u2u_2_3(signext_2_1(acc_10_psp_1_sva[11]));
+              ACC1_acc_277_cse = conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11]))
+                  + conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11]));
+              in_2_sva_2 = conv_s2s_11_12(conv_u2s_10_11({(acc_10_psp_1_sva[11])
+                  , 8'b0 , (acc_10_psp_1_sva[11])}) + (conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+                  , (acc_10_psp_1_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_113_psp_1_sva[3])
+                  , (acc_10_psp_1_sva[4])})))) + conv_s2s_2_3(ACC1_acc_120_psp_sva[2:1]))
+                  + (readslicef_5_4_1((conv_u2s_3_5({(acc_10_psp_1_sva[3]) , (acc_10_psp_1_sva[1])
+                  , 1'b1}) + conv_s2s_3_5({(ACC1_acc_113_psp_1_sva[3]) , (acc_10_psp_1_sva[2])
+                  , (ACC1_acc_113_psp_1_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_10_psp_1_sva[7])
+                  , (acc_10_psp_1_sva[4]) , (signext_2_1(acc_10_psp_1_sva[11]))})
+                  + conv_u2u_3_5(ACC1_acc_250_cse))) + conv_u2s_7_8({(acc_10_psp_1_sva[8])
+                  , 1'b0 , (acc_10_psp_1_sva[8]) , 1'b0 , (acc_10_psp_1_sva[8]) ,
+                  1'b0 , (acc_10_psp_1_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_10_psp_1_sva[11])
+                  , (signext_2_1(acc_10_psp_1_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_10_psp_1_sva[6])
+                  , 1'b0 , (acc_10_psp_1_sva[6]) , 1'b0 , (acc_10_psp_1_sva[6])})
+                  + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_250_cse) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[7])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[9]) , ((acc_10_psp_1_sva[11])
+                  & (~ (acc_imod_11_sva[1])) & (acc_imod_11_sva[0]))}))))))))) +
+                  conv_u2s_10_11({(acc_10_psp_1_sva[11]) , 1'b0 , (acc_10_psp_1_sva[11])
+                  , 1'b0 , (acc_10_psp_1_sva[11]) , 1'b0 , (acc_10_psp_1_sva[11])
+                  , 1'b0 , (signext_2_1(acc_10_psp_1_sva[11]))}))) + (conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_10_psp_2_sva[10])
+                  , 1'b0 , (acc_10_psp_2_sva[10]) , 1'b0 , (acc_10_psp_2_sva[10])
+                  , 1'b0 , (acc_10_psp_2_sva[10]) , 1'b0 , (acc_10_psp_2_sva[10])})
+                  + conv_u2u_8_10(({(acc_10_psp_2_sva[9]) , 1'b0 , (acc_10_psp_2_sva[9])
+                  , 1'b0 , (acc_10_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_10_psp_2_sva[5]))})
+                  + conv_u2u_7_8(conv_u2u_6_7({(acc_10_psp_2_sva[7]) , 1'b0 , (acc_10_psp_2_sva[5])
+                  , 1'b0 , (signext_2_1(acc_10_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) ,
+                  (~((acc_imod_24_sva[1]) & (~ (acc_10_psp_2_sva[11]))))}))))) +
+                  conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) ,
+                  (~ (acc_imod_22_sva[2]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) ,
+                  (acc_imod_22_sva[1])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) ,
+                  (ACC1_acc_113_psp_2_sva[2])})))))))))) + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+                  , (acc_10_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_113_psp_2_sva[3])
+                  , (acc_10_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_120_psp_1_sva[2:1]))
+                  + (readslicef_5_4_1((conv_u2s_3_5({(acc_10_psp_2_sva[3]) , (acc_10_psp_2_sva[1])
+                  , 1'b1}) + conv_s2s_3_5({(ACC1_acc_113_psp_2_sva[3]) , (acc_10_psp_2_sva[2])
+                  , (ACC1_acc_113_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_10_psp_2_sva[7])
+                  , (acc_10_psp_2_sva[4]) , (signext_2_1(acc_10_psp_2_sva[11]))})
+                  + conv_u2u_3_5(ACC1_acc_277_cse))) + conv_u2s_7_8({(acc_10_psp_2_sva[8])
+                  , 1'b0 , (acc_10_psp_2_sva[8]) , 1'b0 , (acc_10_psp_2_sva[8]) ,
+                  1'b0 , (acc_10_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_10_psp_2_sva[11])
+                  , (signext_2_1(acc_10_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_10_psp_2_sva[6])
+                  , 1'b0 , (acc_10_psp_2_sva[6]) , 1'b0 , (acc_10_psp_2_sva[6])})
+                  + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_277_cse) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[7])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[9]) , ((acc_10_psp_2_sva[11])
+                  & (~ (acc_imod_24_sva[1])) & (acc_imod_24_sva[0]))})))))))))) +
+                  ({(acc_10_psp_2_sva[11]) , 2'b0 , (acc_10_psp_2_sva[11]) , 1'b0
+                  , (acc_10_psp_2_sva[11]) , 1'b0 , (acc_10_psp_2_sva[11]) , (conv_u2u_1_3(acc_10_psp_2_sva[11])
+                  + conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11])))})) + conv_u2s_10_12(conv_u2u_9_10({(acc_10_psp_1_sva[10])
+                  , 1'b0 , (acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10])
+                  , 1'b0 , (acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10])})
+                  + conv_u2u_8_10(({(acc_10_psp_1_sva[9]) , 1'b0 , (acc_10_psp_1_sva[9])
+                  , 1'b0 , (acc_10_psp_1_sva[9]) , 1'b0 , (signext_2_1(acc_10_psp_1_sva[5]))})
+                  + conv_u2u_7_8(conv_u2u_6_7({(acc_10_psp_1_sva[7]) , 1'b0 , (acc_10_psp_1_sva[5])
+                  , 1'b0 , (signext_2_1(acc_10_psp_1_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) ,
+                  (~((acc_imod_11_sva[1]) & (~ (acc_10_psp_1_sva[11]))))}))))) +
+                  conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) ,
+                  (~ (acc_imod_10_sva[2]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) ,
+                  (acc_imod_10_sva[1])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) ,
+                  (ACC1_acc_113_psp_1_sva[2])})))))))))));
+              acc_imod_6_lpi_1_dfm_sg1 = acc_imod_6_sva[2:1];
+              acc_imod_7_lpi_1_dfm = readslicef_3_2_1((({1'b1 , (acc_imod_6_sva[0])
+                  , 1'b1}) + conv_u2s_2_3({(~ (acc_imod_6_sva[1])) , (~ (acc_imod_6_sva[2]))})));
+              regs_regs_0_sva_dfm = regs_regs_0_sva_1;
+              regs_regs_1_sva_dfm = regs_regs_0_sva;
+              regs_regs_2_lpi_1_dfm_1 = regs_regs_1_sva[29:0];
+              regs_regs_2_lpi_1_dfm_sg2 = regs_regs_1_sva[89:60];
+              ACC1_acc_118_psp_lpi_1_dfm_sg1 = ACC1_acc_118_psp_sva[2:1];
+              ACC1_acc_125_psp_lpi_1_dfm = ACC1_acc_125_psp_sva;
+              ACC1_acc_110_psp_1_lpi_1_dfm_sg1 = ACC1_acc_110_psp_1_sva[3:1];
+            end
+            else begin
+              regs_regs_0_sva_dfm = regs_regs_0_sva;
+              regs_regs_1_sva_dfm = regs_regs_1_sva;
+            end
+            i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm));
+            acc_imod_18_lpi_1_dfm_sg1 = MUX_v_2_2_2({acc_imod_18_lpi_1_dfm_sg1 ,
+                (acc_imod_18_sva[2:1])}, exit_FRAME_for_lpi_1_dfm);
+            acc_imod_20_lpi_1_dfm = MUX_v_2_2_2({acc_imod_20_lpi_1_dfm , acc_imod_20_sva},
+                exit_FRAME_for_lpi_1_dfm);
+            ACC1_acc_118_psp_1_lpi_1_dfm_sg1 = MUX_v_2_2_2({ACC1_acc_118_psp_1_lpi_1_dfm_sg1
+                , (ACC1_acc_118_psp_1_sva[2:1])}, exit_FRAME_for_lpi_1_dfm);
+            ACC1_acc_125_psp_1_lpi_1_dfm = MUX_v_12_2_2({ACC1_acc_125_psp_1_lpi_1_dfm
+                , ACC1_acc_125_psp_1_sva}, exit_FRAME_for_lpi_1_dfm);
+            ACC1_acc_110_psp_2_lpi_1_dfm_sg1 = MUX_v_3_2_2({ACC1_acc_110_psp_2_lpi_1_dfm_sg1
+                , (ACC1_acc_110_psp_2_sva[3:1])}, exit_FRAME_for_lpi_1_dfm);
+            FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+            FRAME_for_slc_YMATRIX_rom_11_psp_sva = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1]))))
+                | FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+            FRAME_for_slc_XMATRIX_rom_10_psp_sva_1 = (~((~ (i_6_lpi_1_dfm[1])) &
+                (i_6_lpi_1_dfm[0]))) | FRAME_for_nor_cse;
+            i_6_sva_1 = i_6_lpi_1_dfm + 2'b1;
+            exit_FRAME_for_sva_1 = ~ (readslicef_3_1_2((({1'b1 , i_6_sva_1}) + 3'b1)));
+            if ( exit_FRAME_for_sva_1 ) begin
+              ACC1_acc_341_itm = (conv_s2s_26_13(conv_u2s_2_13(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[11])) * 13'b1101000000001)
+                  + conv_u2s_10_13((conv_u2u_9_10({conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm[8])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[8])) * 6'b10101) ,
+                  (ACC1_acc_125_psp_lpi_1_dfm[3]) , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11]))})
+                  + conv_u2u_8_10(conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm[7])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[7])) * 8'b1010101)
+                  + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm[5])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[5])) * 6'b10101)) +
+                  conv_u2u_6_7({(ACC1_acc_125_psp_lpi_1_dfm[6]) , 1'b0 , (ACC1_acc_125_psp_lpi_1_dfm[4])
+                  , 1'b0 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11]))})))) + conv_u2u_8_10((conv_u2u_7_8(signext_7_3({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (signext_2_1(ACC1_acc_125_psp_1_lpi_1_dfm[11]))})) + conv_u2u_6_8(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , (acc_imod_18_lpi_1_dfm_sg1[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[4])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1[2])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , ((ACC1_acc_125_psp_lpi_1_dfm[11]) & (~ (acc_imod_7_lpi_1_dfm[1]))
+                  & (acc_imod_7_lpi_1_dfm[0]))}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[6])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[8])
+                  , (~((acc_imod_7_lpi_1_dfm[1]) & (~ (ACC1_acc_125_psp_lpi_1_dfm[11]))))})))))
+                  + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[10])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (acc_imod_6_lpi_1_dfm_sg1[0])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1[1])}))))))))) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2(ACC1_acc_125_psp_1_lpi_1_dfm[4:3]))))))
+                  + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (ACC1_acc_125_psp_1_lpi_1_dfm[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[6])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[8])
+                  , (ACC1_acc_125_psp_1_lpi_1_dfm[1])}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , (ACC1_acc_125_psp_1_lpi_1_dfm[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , (ACC1_acc_125_psp_lpi_1_dfm[3])})))))) + conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_125_psp_lpi_1_dfm[2])
+                  , (ACC1_acc_125_psp_lpi_1_dfm[0]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_125_psp_1_lpi_1_dfm[2])
+                  , (ACC1_acc_125_psp_lpi_1_dfm[1]) , (ACC1_acc_125_psp_lpi_1_dfm[2])}))))
+                  , 1'b1}) + conv_u2u_4_5({(~ (ACC1_acc_110_psp_1_lpi_1_dfm_sg1[2]))
+                  , 1'b1 , (~ (acc_imod_6_lpi_1_dfm_sg1[1])) , ((ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  & (~ (acc_imod_20_lpi_1_dfm[1])) & (acc_imod_20_lpi_1_dfm[0]))}))))))
+                  + conv_u2u_4_7((readslicef_5_4_1((conv_u2u_4_5({(~ (ACC1_acc_110_psp_2_lpi_1_dfm_sg1[2]))
+                  , 1'b1 , (~ (acc_imod_18_lpi_1_dfm_sg1[1])) , 1'b1}) + conv_s2u_3_5({ACC1_acc_118_psp_lpi_1_dfm_sg1
+                  , (~((acc_imod_20_lpi_1_dfm[1]) & (~ (ACC1_acc_125_psp_1_lpi_1_dfm[11]))))}))))
+                  + (readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , 1'b1})) + conv_s2s_3_5({ACC1_acc_118_psp_1_lpi_1_dfm_sg1 , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1[1])})))))))))
+                  + (conv_s2s_11_13(conv_u2s_10_12(conv_u2s_20_11(conv_u2u_2_10(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm[9])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[9])) * 10'b101010101))
+                  + conv_s2s_9_11(conv_s2s_7_9(conv_u2s_6_7({(ACC1_acc_125_psp_1_lpi_1_dfm[6])
+                  , 1'b0 , (ACC1_acc_125_psp_lpi_1_dfm[6]) , 1'b0 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11]))})
+                  + conv_s2s_5_7(({(conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[4])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[6])) , (conv_u2u_2_3(signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[10]))
+                  + conv_u2u_2_3(signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11])))})
+                  + ({3'b100 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11]))})))
+                  + conv_u2s_7_9(signext_7_3({(ACC1_acc_125_psp_lpi_1_dfm[11]) ,
+                  (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11]))})))) + conv_u2s_11_13({conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm[10])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[10])) * 8'b1010101)
+                  , (ACC1_acc_125_psp_1_lpi_1_dfm[3]) , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11]))}));
+              FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+              exit_FRAME_lpi_1_dfm_1 = ~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+                  + 8'b10110101)));
+            end
+            else begin
+              exit_FRAME_lpi_1_dfm_1 = exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm);
+            end
+            exit_FRAME_for_lpi_1_dfm_2 = exit_FRAME_for_sva_1;
+            regs_regs_0_sva = regs_regs_0_sva_dfm;
+            regs_regs_1_sva = regs_regs_1_sva_dfm;
+            FRAME_p_1_lpi_1 = MUX_v_19_2_2({FRAME_p_1_lpi_1_dfm , FRAME_p_1_sva_1},
+                exit_FRAME_for_sva_1);
+            exit_FRAME_1_sva = exit_FRAME_for_sva_1 & exit_FRAME_lpi_1_dfm_1;
+            exit_FRAME_for_lpi_1_dfm_3 = exit_FRAME_for_lpi_1_dfm;
+            regs_operator_10_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[19:10])
+                , (regs_regs_1_sva_dfm[19:10]) , (regs_regs_2_lpi_1_dfm_1[19:10])
+                , 10'b0}, i_6_lpi_1_dfm);
+            regs_operator_11_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[9:0]) ,
+                (regs_regs_1_sva_dfm[9:0]) , (regs_regs_2_lpi_1_dfm_1[9:0]) , 10'b0},
+                i_6_lpi_1_dfm);
+            regs_operator_9_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[29:20]) ,
+                (regs_regs_1_sva_dfm[29:20]) , (regs_regs_2_lpi_1_dfm_1[29:20]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            FRAME_for_acc_24_itm_1 = (conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(regs_operator_10_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva})))
+                + conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(regs_operator_11_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva}))))
+                + conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(regs_operator_9_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva})));
+            FRAME_for_slc_in_0_sva_itm_1 = in_0_sva_2;
+            regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[79:70])
+                , (regs_regs_1_sva_dfm[79:70]) , (regs_regs_2_lpi_1_dfm_sg2[19:10])
+                , 10'b0}, i_6_lpi_1_dfm);
+            regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[69:60])
+                , (regs_regs_1_sva_dfm[69:60]) , (regs_regs_2_lpi_1_dfm_sg2[9:0])
+                , 10'b0}, i_6_lpi_1_dfm);
+            regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[89:80])
+                , (regs_regs_1_sva_dfm[89:80]) , (regs_regs_2_lpi_1_dfm_sg2[29:20])
+                , 10'b0}, i_6_lpi_1_dfm);
+            FRAME_for_acc_26_itm_1 = (conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(regs_operator_16_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_10_psp_sva_1})))
+                + conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(regs_operator_17_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_10_psp_sva_1}))))
+                + conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(regs_operator_15_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_10_psp_sva_1})));
+            FRAME_for_slc_in_2_sva_itm_1 = in_2_sva_2;
+            ACC1_acc_341_itm_1 = ACC1_acc_341_itm;
+            exit_FRAME_for_sva_1_st_1 = exit_FRAME_for_sva_1;
+            main_stage_0_2 = 1'b1;
+          end
+        end
+      end
+    end
+    FRAME_for_slc_XMATRIX_rom_10_psp_sva_1 = 1'b0;
+    FRAME_for_nor_cse = 1'b0;
+    ACC1_acc_277_cse = 3'b0;
+    ACC1_acc_250_cse = 3'b0;
+    ACC1_acc_224_cse = 3'b0;
+    ACC1_acc_197_cse = 3'b0;
+    ACC1_acc_110_psp_2_lpi_1_dfm_sg1 = 3'b0;
+    ACC1_acc_118_psp_1_lpi_1_dfm_sg1 = 2'b0;
+    acc_imod_18_lpi_1_dfm_sg1 = 2'b0;
+    ACC1_acc_110_psp_1_lpi_1_dfm_sg1 = 3'b0;
+    ACC1_acc_118_psp_lpi_1_dfm_sg1 = 2'b0;
+    regs_regs_2_lpi_1_dfm_1 = 30'b0;
+    regs_regs_2_lpi_1_dfm_sg2 = 30'b0;
+    acc_imod_6_lpi_1_dfm_sg1 = 2'b0;
+    in_2_sva_2 = 12'b0;
+    in_0_sva_2 = 12'b0;
+    main_stage_0_2 = 1'b0;
+    exit_FRAME_for_sva_1_st_1 = 1'b0;
+    ACC1_acc_341_itm_1 = 13'b0;
+    ACC1_acc_341_itm = 13'b0;
+    FRAME_for_slc_in_2_sva_itm_1 = 12'b0;
+    FRAME_for_acc_26_itm_1 = 12'b0;
+    FRAME_for_slc_in_0_sva_itm_1 = 12'b0;
+    FRAME_for_acc_24_itm_1 = 13'b0;
+    exit_FRAME_for_lpi_1_dfm_3 = 1'b0;
+    exit_FRAME_for_lpi_1_dfm_2 = 1'b0;
+    exit_FRAME_lpi_1_dfm_1 = 1'b0;
+    FRAME_p_1_sva_1 = 19'b0;
+    FRAME_acc_2_psp_sva = 12'b0;
+    acc_imod_12_sva = 6'b0;
+    intensity_2_sg1_sva = 15'b0;
+    exit_FRAME_for_sva_1 = 1'b0;
+    i_6_sva_1 = 2'b0;
+    in_2_sva_1 = 16'b0;
+    in_0_sva_1 = 16'b0;
+    FRAME_for_slc_YMATRIX_rom_11_psp_sva = 1'b0;
+    ACC1_acc_125_psp_1_lpi_1_dfm = 12'b0;
+    acc_imod_20_lpi_1_dfm = 2'b0;
+    i_6_lpi_1_dfm = 2'b0;
+    ACC1_acc_125_psp_lpi_1_dfm = 12'b0;
+    regs_regs_1_sva_dfm = 90'b0;
+    regs_regs_0_sva_dfm = 90'b0;
+    acc_imod_7_lpi_1_dfm = 2'b0;
+    acc_imod_11_sva = 2'b0;
+    acc_imod_10_sva = 3'b0;
+    ACC1_acc_120_psp_sva = 3'b0;
+    ACC1_acc_113_psp_1_sva = 4'b0;
+    acc_10_psp_1_sva = 12'b0;
+    acc_imod_6_sva = 3'b0;
+    ACC1_acc_118_psp_sva = 3'b0;
+    ACC1_acc_110_psp_1_sva = 4'b0;
+    ACC1_acc_125_psp_sva = 12'b0;
+    acc_imod_3_sva = 2'b0;
+    acc_imod_2_sva = 3'b0;
+    ACC1_acc_116_psp_sva = 3'b0;
+    ACC1_acc_107_psp_1_sva = 4'b0;
+    acc_psp_1_sva = 12'b0;
+    acc_imod_24_sva = 2'b0;
+    acc_imod_22_sva = 3'b0;
+    ACC1_acc_120_psp_1_sva = 3'b0;
+    ACC1_acc_113_psp_2_sva = 4'b0;
+    acc_10_psp_2_sva = 12'b0;
+    acc_imod_20_sva = 2'b0;
+    acc_imod_18_sva = 3'b0;
+    ACC1_acc_118_psp_1_sva = 3'b0;
+    ACC1_acc_110_psp_2_sva = 4'b0;
+    ACC1_acc_125_psp_1_sva = 12'b0;
+    acc_imod_16_sva = 2'b0;
+    acc_imod_14_sva = 3'b0;
+    ACC1_acc_116_psp_1_sva = 3'b0;
+    ACC1_acc_107_psp_2_sva = 4'b0;
+    acc_psp_2_sva = 12'b0;
+    regs_regs_0_sva_1 = 90'b0;
+    exit_FRAME_for_lpi_1_dfm = 1'b0;
+    FRAME_p_1_lpi_1_dfm = 19'b0;
+    exit_FRAME_1_sva = 1'b0;
+    regs_regs_0_sva = 90'b0;
+    regs_regs_1_sva = 90'b0;
+    FRAME_p_1_lpi_1 = 19'b0;
+    vout_rsc_mgc_out_stdreg_d <= 30'b0;
+  end
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [14:0] readslicef_16_15_1;
+    input [15:0] vector;
+    reg [15:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_16_15_1 = tmp[14:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_3;
+    input [2:0] vector;
+  begin
+    signext_7_3= {{4{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_2;
+    input [1:0] vector;
+  begin
+    signext_3_2= {{1{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] MUX_v_2_2_2;
+    input [3:0] inputs;
+    input [0:0] sel;
+    reg [1:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[3:2];
+      end
+      1'b1 : begin
+        result = inputs[1:0];
+      end
+      default : begin
+        result = inputs[3:2];
+      end
+    endcase
+    MUX_v_2_2_2 = result;
+  end
+  endfunction
+
+
+  function [11:0] MUX_v_12_2_2;
+    input [23:0] inputs;
+    input [0:0] sel;
+    reg [11:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[23:12];
+      end
+      1'b1 : begin
+        result = inputs[11:0];
+      end
+      default : begin
+        result = inputs[23:12];
+      end
+    endcase
+    MUX_v_12_2_2 = result;
+  end
+  endfunction
+
+
+  function [2:0] MUX_v_3_2_2;
+    input [5:0] inputs;
+    input [0:0] sel;
+    reg [2:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[5:3];
+      end
+      1'b1 : begin
+        result = inputs[2:0];
+      end
+      default : begin
+        result = inputs[5:3];
+      end
+    endcase
+    MUX_v_3_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_3_1_2;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 2;
+    readslicef_3_1_2 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_13_16 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2u_13_16 = {{3{vector[12]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_13_16 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_16 = {{3{vector[12]}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_6_8 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_8 = {{2{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_26_13 ;
+    input signed [25:0]  vector ;
+  begin
+    conv_s2s_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_12_6 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_6 = vector[5:0];
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_2_6 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_6 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_2_8 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_8 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_4_7 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_7 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_s2u_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2u_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_11_13 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_13 = {{2{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_9_11 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_11 = {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2s_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2s_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v7/cycle_mgc_ioport.v b/Sobel/sobel.v7/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v7/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v7/cycle_mgc_ioport_v2001.v b/Sobel/sobel.v7/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v7/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v7/cycle_set.tcl b/Sobel/sobel.v7/cycle_set.tcl
new file mode 100644
index 0000000..1b75cc6
--- /dev/null
+++ b/Sobel/sobel.v7/cycle_set.tcl
@@ -0,0 +1,316 @@
+
+# Loop constraints
+directive set /sobel/core/core:rlp CSTEPS_FROM {{. == 0}}
+directive set /sobel/core/core:rlp/main CSTEPS_FROM {{. == 3} {.. == 0}}
+
+# IO operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:io_read(vin:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:io_write(vout:rsc.d) CSTEPS_FROM {{.. == 2}}
+
+# Real operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:for:and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#133 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#132 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#136 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#138 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#135 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#134 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#137 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#107 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#139 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#116 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#140 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#141 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#143 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#142 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#125 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#145 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#147 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#144 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#146 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#148 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#149 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#118 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#150 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#151 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#153 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#152 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#156 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#158 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#155 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#154 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#157 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#113 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#159 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#120 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#160 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#161 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#162 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#165 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#167 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#164 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#163 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#166 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#107 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#168 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#116 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#169 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#170 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#171 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#125 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#173 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#175 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#172 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#174 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#176 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#177 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#118 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#178 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#179 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#180 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#183 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#185 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#182 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#181 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#184 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#113 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#186 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#120 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#187 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#188 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#189 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#198 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#190 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#203 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#197 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#202 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#206 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#209 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#196 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#195 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#201 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#205 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#208 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#211 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#213 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#215 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#221 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#220 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#227 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#219 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#218 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#226 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#231 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#234 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#237 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#239 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#216 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#225 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#217 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#230 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#224 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#229 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#233 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#236 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#223 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#222 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#228 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#232 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#235 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#238 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#241 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#240 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#122 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#194 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#193 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#200 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#192 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#191 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#199 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#204 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#207 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#210 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#212 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#214 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#122 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#242 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#251 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#243 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#256 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#250 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#255 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#259 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#262 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#249 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#248 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#254 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#258 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#261 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#264 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#266 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#268 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#274 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#273 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#280 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#272 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#271 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#279 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#284 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#287 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#290 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#292 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#269 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#278 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#270 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#283 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#277 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#282 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#286 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#289 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#276 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#275 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#281 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#285 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#288 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#291 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#294 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#293 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#124 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#247 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#246 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#253 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#245 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#244 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#252 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#257 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#260 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#263 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#265 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#267 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-3:acc#124 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#9 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#10 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#17 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#20 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#26 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#30 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#33 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#36 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#10:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#1 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#11:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#23 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#9:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#24 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#11 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#20 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:or#4 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#16:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#7 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#17:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#25 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#15:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#26 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#12 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#22 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#20 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#21 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#18 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#330 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#334 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#336 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#310 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#309 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#319 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#307 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#306 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#318 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#325 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#305 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#304 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#317 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#303 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#302 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#316 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#324 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#328 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#332 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#301 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#300 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#315 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#299 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#298 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#314 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#323 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#297 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#296 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#313 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#295 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#312 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#322 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#327 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#311 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#308 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#321 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#331 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#335 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#338 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#340 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#19 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#320 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#326 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#329 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#333 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#337 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#22 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#339 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#341 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#342 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#6 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#5 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#8 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#7 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#9 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/acc#15 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#1 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#16 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#10 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#11 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#12 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#13 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#14 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#15 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#2 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#44 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#45 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#42 CSTEPS_FROM {{.. == 1}}
diff --git a/Sobel/sobel.v7/directives.tcl b/Sobel/sobel.v7/directives.tcl
new file mode 100644
index 0000000..504c4bb
--- /dev/null
+++ b/Sobel/sobel.v7/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
+go extract
diff --git a/Sobel/sobel.v7/messages.txt b/Sobel/sobel.v7/messages.txt
new file mode 100644
index 0000000..00a0802
--- /dev/null
+++ b/Sobel/sobel.v7/messages.txt
@@ -0,0 +1,252 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.23 seconds, memory usage 269072kB, peak memory usage 388764kB (SOL-9)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.cpp(128): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+
+# Messages from "go compile"
+
+Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'sobel' specified by directive (CIN-52)
+Synthesizing routine 'sobel' (CIN-13)
+Inlining routine 'sobel' (CIN-14)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Optimizing block '/sobel' ... (CIN-4)
+Inout port 'vin' is only used as an input. (OPT-10)
+Inout port 'vout' is only used as an output. (OPT-11)
+Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+Detected constant initialization of array 'in', optimizing loop 'RESET' (LOOP-12)
+Design 'sobel' was read (SOL-1)
+Optimizing partition '/sobel': (Total ops = 1035, Real ops = 214, Vars = 224) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1035, Real ops = 214, Vars = 222) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 993, Real ops = 206, Vars = 228) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 993, Real ops = 206, Vars = 230) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 993, Real ops = 206, Vars = 230) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 993, Real ops = 206, Vars = 228) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 937, Real ops = 205, Vars = 215) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 912, Real ops = 205, Vars = 214) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 912, Real ops = 205, Vars = 214) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 912, Real ops = 205, Vars = 216) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 912, Real ops = 205, Vars = 216) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 890, Real ops = 203, Vars = 258) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 39) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 670, Real ops = 125, Vars = 32) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 595, Real ops = 117, Vars = 31) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 592, Real ops = 117, Vars = 31) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 592, Real ops = 117, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 587, Real ops = 117, Vars = 36) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 584, Real ops = 117, Vars = 31) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 584, Real ops = 117, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 584, Real ops = 117, Vars = 31) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 584, Real ops = 117, Vars = 33) (SOL-10)
+Completed transformation 'compile' on solution 'sobel.v7': elapsed time 4.54 seconds, memory usage 276108kB, peak memory usage 388764kB (SOL-9)
+Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'sobel.v7' (SOL-8)
+Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+Loop '/sobel/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/sobel/core': (Total ops = 1539, Real ops = 290, Vars = 31) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 971, Real ops = 174, Vars = 40) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 970, Real ops = 174, Vars = 39) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 970, Real ops = 174, Vars = 39) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 973, Real ops = 174, Vars = 41) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 968, Real ops = 174, Vars = 41) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 939, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 939, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 939, Real ops = 187, Vars = 45) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 940, Real ops = 187, Vars = 41) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 940, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 940, Real ops = 187, Vars = 45) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 940, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 940, Real ops = 187, Vars = 45) (SOL-10)
+I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 48) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 43) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 45) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 45) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 45) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 932, Real ops = 187, Vars = 49) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 932, Real ops = 187, Vars = 44) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 913, Real ops = 192, Vars = 42) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 913, Real ops = 192, Vars = 47) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 913, Real ops = 192, Vars = 42) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 913, Real ops = 192, Vars = 47) (SOL-10)
+Design 'sobel' contains '439' real operations. (SOL-11)
+Optimizing partition '/sobel/core': (Total ops = 920, Real ops = 193, Vars = 45) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 919, Real ops = 193, Vars = 45) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1354, Real ops = 245, Vars = 293) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 987, Real ops = 216, Vars = 83) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 986, Real ops = 216, Vars = 82) (SOL-10)
+Completed transformation 'architect' on solution 'sobel.v7': elapsed time 10.84 seconds, memory usage 276144kB, peak memory usage 388764kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'sobel.v7' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 6857.74, 0.00, 6857.74 (CRAAS-11)
+Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 6767.91, 0.00, 6767.91 (CRAAS-10)
+Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 6764.18, 0.00, 6764.18 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 6764.18, 0.00, 6764.18 (CRAAS-12)
+Completed transformation 'allocate' on solution 'sobel.v7': elapsed time 4.90 seconds, memory usage 276616kB, peak memory usage 388764kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'sobel.v7' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 1561, Real ops = 440, Vars = 122) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1551, Real ops = 439, Vars = 114) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 1542, Real ops = 440, Vars = 129) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 1433, Real ops = 426, Vars = 82) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 1422, Real ops = 425, Vars = 79) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1436, Real ops = 425, Vars = 91) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1427, Real ops = 425, Vars = 84) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 1424, Real ops = 425, Vars = 81) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 1423, Real ops = 425, Vars = 79) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1437, Real ops = 425, Vars = 91) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1428, Real ops = 425, Vars = 84) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 1423, Real ops = 425, Vars = 79) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1437, Real ops = 425, Vars = 91) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1428, Real ops = 425, Vars = 84) (SOL-10)
+Completed transformation 'schedule' on solution 'sobel.v7': elapsed time 6.12 seconds, memory usage 285508kB, peak memory usage 388764kB (SOL-9)
+Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'sobel.v7' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 1830, Real ops = 467, Vars = 1152) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1821, Real ops = 467, Vars = 1145) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2601, Real ops = 461, Vars = 103) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2592, Real ops = 461, Vars = 96) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+Completed transformation 'dpfsm' on solution 'sobel.v7': elapsed time 1.70 seconds, memory usage 285896kB, peak memory usage 388764kB (SOL-9)
+
+# Messages from "go extract"
+
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'sobel.v7' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 1495, Real ops = 470, Vars = 1492) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1486, Real ops = 470, Vars = 1485) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1480, Real ops = 469, Vars = 1477) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1471, Real ops = 469, Vars = 1470) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1480, Real ops = 469, Vars = 1477) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1471, Real ops = 469, Vars = 1470) (SOL-10)
+Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+Reassigned operation ACC1:acc#268:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,0,11) (ASG-1)
+Reassigned operation ACC1:acc#215:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,0,11) (ASG-1)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/sobel': (Total ops = 1480, Real ops = 469, Vars = 1477) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1471, Real ops = 469, Vars = 1470) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1402, Real ops = 457, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1393, Real ops = 457, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1402, Real ops = 457, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1393, Real ops = 457, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1402, Real ops = 457, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1393, Real ops = 457, Vars = 95) (SOL-10)
+Completed transformation 'extract' on solution 'sobel.v7': elapsed time 11.58 seconds, memory usage 287424kB, peak memory usage 388764kB (SOL-9)
diff --git a/Sobel/sobel.v7/reg_sharing.tcl b/Sobel/sobel.v7/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v7/reg_sharing.tcl
diff --git a/Sobel/sobel.v7/res_sharing.tcl b/Sobel/sobel.v7/res_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v7/res_sharing.tcl
diff --git a/Sobel/sobel.v7/rtl.rpt b/Sobel/sobel.v7/rtl.rpt
new file mode 100644
index 0000000..460f40a
--- /dev/null
+++ b/Sobel/sobel.v7/rtl.rpt
@@ -0,0 +1,1184 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 15:20:14 +0000 2016                      
+
+Solution Settings: sobel.v7
+  Current state: extract
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       444  921601     921600            0  1          
+    Design Total:                     444  921601     921600            0  0          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(1,0,1,0,2)                           2.319                       0.000      2.319 0.506          6           7 
+    mgc_add(10,0,10,0,11)                       11.241                       0.000     11.241 1.301          2           0 
+    mgc_add(10,0,10,1,11)                       11.000                       0.000     11.000 1.139          6           6 
+    mgc_add(10,1,10,1,11)                       11.000                       0.000     11.000 1.139          9           9 
+    mgc_add(11,0,10,0,11)                       12.236                       0.000     12.236 1.370          0           2 
+    mgc_add(11,0,11,1,13)                       12.000                       0.000     12.000 1.043          6           6 
+    mgc_add(11,1,11,1,12)                       12.000                       0.000     12.000 1.206          7           7 
+    mgc_add(12,1,12,1,13)                       13.000                       0.000     13.000 1.272          7           5 
+    mgc_add(13,0,12,1,13)                       14.000                       0.000     14.000 1.501          2           2 
+    mgc_add(13,0,13,0,13)                       14.215                       0.000     14.215 1.499          1           1 
+    mgc_add(16,0,13,1,16)                       17.000                       0.000     17.000 1.694          3           3 
+    mgc_add(16,0,16,0,16)                       17.189                       0.000     17.189 1.690          1           1 
+    mgc_add(19,0,2,1,19)                        20.000                       0.000     20.000 1.908          1           1 
+    mgc_add(2,0,1,0,2)                           3.315                       0.000      3.315 0.658          0           1 
+    mgc_add(2,0,1,0,3)                           3.315                       0.000      3.315 0.658          0           2 
+    mgc_add(2,0,2,0,3)                           3.311                       0.000      3.311 0.653         26          23 
+    mgc_add(2,0,2,1,4)                           3.000                       0.000      3.000 0.328         11          11 
+    mgc_add(3,0,3,0,4)                           4.302                       0.000      4.302 0.761         60          60 
+    mgc_add(3,0,3,1,5)                           4.000                       0.000      4.000 0.436         22          21 
+    mgc_add(3,1,2,1,4)                           4.000                       0.000      4.000 0.602          8           8 
+    mgc_add(4,0,4,0,5)                           5.293                       0.000      5.293 0.854         11          10 
+    mgc_add(4,0,4,1,6)                           5.000                       0.000      5.000 0.529         13          13 
+    mgc_add(4,1,4,1,5)                           5.000                       0.000      5.000 0.691          8           8 
+    mgc_add(5,0,5,0,6)                           6.285                       0.000      6.285 0.938          2           2 
+    mgc_add(5,0,5,1,7)                           6.000                       0.000      6.000 0.613         14          14 
+    mgc_add(6,0,6,0,7)                           7.276                       0.000      7.276 1.016          1           1 
+    mgc_add(6,0,6,1,8)                           7.000                       0.000      7.000 0.691          8           8 
+    mgc_add(7,0,7,1,9)                           8.000                       0.000      8.000 0.766         10          10 
+    mgc_add(8,0,8,1,10)                          9.000                       0.000      9.000 0.838         11          11 
+    mgc_add(9,0,8,0,10)                         10.254                       0.000     10.254 1.235          5           5 
+    mgc_add(9,0,8,1,10)                         10.000                       0.000     10.000 1.072          1           1 
+    mgc_and(1,2)                                 0.730                       0.000      0.730 0.263          0           3 
+    mgc_and(1,3)                                 1.054                       0.000      1.054 0.416          0           6 
+    mgc_and(19,2)                               13.867                       0.000     13.867 0.263          1           1 
+    mgc_and(2,2)                                 1.460                       0.000      1.460 0.263          2           1 
+    mgc_mul(2,0,12,1,13)                       330.000                       2.000     10.000 3.224          7           7 
+    mgc_mul(2,1,10,1,12)                       330.000                       2.000     10.000 3.087          6           6 
+    mgc_mul(3,0,6,0,9)                         330.250                       2.000     10.250 2.846          1           1 
+    mgc_mux(1,1,2)                               0.919                       0.000      0.919 0.369          2           1 
+    mgc_mux(10,2,4)                             22.259                       0.000     22.259 0.936          6           6 
+    mgc_mux(12,1,2)                             11.033                       0.000     11.033 0.369          2           2 
+    mgc_mux(16,1,2)                             14.711                       0.000     14.711 0.369          2           4 
+    mgc_mux(19,1,2)                             17.469                       0.000     17.469 0.369          1           1 
+    mgc_mux(2,1,2)                               1.839                       0.000      1.839 0.369          2           6 
+    mgc_mux(3,1,2)                               2.758                       0.000      2.758 0.369          4           2 
+    mgc_mux(30,1,2)                             27.583                       0.000     27.583 0.369          0           3 
+    mgc_mux(4,1,2)                               3.678                       0.000      3.678 0.369          2           0 
+    mgc_mux(90,1,2)                             82.748                       0.000     82.748 0.369          3           2 
+    mgc_nand(1,2)                                0.730                       0.000      0.730 0.268          0           9 
+    mgc_nor(1,2)                                 0.730                       0.000      0.730 0.263          0           2 
+    mgc_not(1)                                   0.000                       0.000      0.000 0.000          0          92 
+    mgc_not(10)                                  0.000                       0.000      0.000 0.000          0           9 
+    mgc_not(2)                                   0.000                       0.000      0.000 0.000          0           8 
+    mgc_not(3)                                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_or(1,2)                                  0.730                       0.000      0.730 0.268          0           2 
+    mgc_or(1,3)                                  1.054                       0.000      1.054 0.425          0           1 
+    mgc_or(10,2)                                 7.298                       0.000      7.298 0.268          1           1 
+    mgc_or(2,2)                                  1.460                       0.000      1.460 0.268          1           0 
+    mgc_or(6,2)                                  4.379                       0.000      4.379 0.268          1           1 
+    mgc_reg_pos(1,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           5 
+    mgc_reg_pos(12,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           5 
+    mgc_reg_pos(13,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(16,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(19,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(2,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           7 
+    mgc_reg_pos(3,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(30,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(90,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,90)                            0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(2,30)                         0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):            6772.333                      28.000   2292.000                              
+    
+  Area Scores
+                      Post-Scheduling   Post-DP & FSM Post-Assignment 
+    ----------------- --------------- --------------- ---------------
+    Total Area Score:   6764.2          6930.2          6772.3        
+    Total Reg:             0.0             0.0             0.0        
+                                                                      
+    DataPath:           6764.2 (100%)   6930.2 (100%)   6772.3 (100%) 
+      MUX:               474.7   (7%)    653.3   (9%)    497.6   (7%) 
+      FUNC:             6259.6  (93%)   6230.8  (90%)   6228.6  (92%) 
+      LOGIC:              29.9   (0%)     46.1   (1%)     46.1   (1%) 
+      BUFFER:              0.0             0.0             0.0        
+      MEM:                 0.0             0.0             0.0        
+      ROM:                 0.0             0.0             0.0        
+      REG:                 0.0             0.0             0.0        
+                                                                      
+    
+    FSM:                   0.0             0.0             0.0        
+      FSM-REG:             0.0             0.0             0.0        
+      FSM-COMB:            0.0             0.0             0.0        
+                                                                      
+    
+  Register-to-Variable Mappings
+    Register                         Size(bits) Gated Register CG Opt Done Variables                                             
+    -------------------------------- ---------- -------------- ----------- -----------------------------------------------------
+    regs.regs(0).sva                         90         Y                  regs.regs(0).sva                                      
+    regs.regs(1).sva                         90         Y                  regs.regs(1).sva                                      
+    regs.regs(2).lpi#1.dfm#1                 30         Y                  regs.regs(2).lpi#1.dfm#1                              
+    regs.regs(2).lpi#1.dfm.sg2               30         Y                  regs.regs(2).lpi#1.dfm.sg2                            
+    vout:rsc:mgc_out_stdreg.d                30         Y                  vout:rsc:mgc_out_stdreg.d                             
+    FRAME:p#1.lpi#1                          19         Y                  FRAME:p#1.lpi#1                                       
+    in(0).sva#1                              16         Y                  in(0).sva#1                                           
+    in(2).sva#1                              16         Y                  in(2).sva#1                                           
+    ACC1:acc#341.itm#1                       13         Y                  ACC1:acc#341.itm#1                                    
+    FRAME:for:acc#24.itm#1                   13         Y                  FRAME:for:acc#24.itm#1                                
+    ACC1:acc#125.psp#1.lpi#1.dfm             12         Y                  ACC1:acc#125.psp#1.lpi#1.dfm                          
+    ACC1:acc#125.psp.lpi#1.dfm               12         Y                  ACC1:acc#125.psp.lpi#1.dfm                            
+    FRAME:for:acc#26.itm#1                   12         Y                  FRAME:for:acc#26.itm#1                                
+    FRAME:for:slc(in(0).sva).itm#1           12         Y                  FRAME:for:slc(in(0).sva).itm#1                        
+    FRAME:for:slc(in(2).sva).itm#1           12         Y                  FRAME:for:slc(in(2).sva).itm#1                        
+    ACC1:acc#110.psp#1.lpi#1.dfm.sg1          3         Y                  ACC1:acc#110.psp#1.lpi#1.dfm.sg1                      
+    ACC1:acc#110.psp#2.lpi#1.dfm.sg1          3         Y                  ACC1:acc#110.psp#2.lpi#1.dfm.sg1                      
+    ACC1:acc#118.psp#1.lpi#1.dfm.sg1          2         Y                  ACC1:acc#118.psp#1.lpi#1.dfm.sg1                      
+    ACC1:acc#118.psp.lpi#1.dfm.sg1            2         Y                  ACC1:acc#118.psp.lpi#1.dfm.sg1                        
+    acc.imod#18.lpi#1.dfm.sg1                 2         Y                  acc.imod#18.lpi#1.dfm.sg1                             
+    acc.imod#20.lpi#1.dfm                     2         Y                  acc.imod#20.lpi#1.dfm                                 
+    acc.imod#6.lpi#1.dfm.sg1                  2         Y                  acc.imod#6.lpi#1.dfm.sg1                              
+    acc.imod#7.lpi#1.dfm                      2         Y                  acc.imod#7.lpi#1.dfm                                  
+    i#6.sva#1                                 2         Y                  i#6.sva#1                                             
+    exit:FRAME#1.sva                          1         Y                  exit:FRAME#1.sva                                      
+    exit:FRAME.lpi#1.dfm#1                    1         Y                  exit:FRAME.lpi#1.dfm#1                                
+    exit:FRAME:for.lpi#1.dfm#3                1         Y                  exit:FRAME:for.lpi#1.dfm#3                            
+    exit:FRAME:for.sva#1.st#1                 1         Y                  exit:FRAME:for.sva#1.st#1                             
+    main.stage_0#2                            1         Y                  main.stage_0#2                                        
+                                                                                                                                 
+    Total:                                  432            432           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  16.044071
+      Slack:      3.955929000000001
+      
+      Path                                             Startpoint                       Endpoint                                       Delay   Slack   
+      ------------------------------------------------ -------------------------------- ---------------------------------------------- ------- -------
+      1                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#1)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#1).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not#161                        mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not#161.itm                                                                                                    0.0000  0.0000  
+        sobel:core/ACC1:acc#153                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#153.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc#10                       mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc#10.psp#2.sva                                                                                                    0.0000  2.3449  
+        sobel:core/slc(acc#10.psp#2.sva)#17                                                                                            0.0000  2.3449  
+        sobel:core/slc(acc#10.psp#2.sva)#17.itm                                                                                        0.0000  2.3449  
+        sobel:core/conc#715                                                                                                            0.0000  2.3449  
+        sobel:core/conc#715.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#155                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#155.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#23                                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:slc#23.itm                                                                                                     0.0000  2.9974  
+        sobel:core/conc#714                                                                                                            0.0000  2.9974  
+        sobel:core/conc#714.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#157                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#157.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc#25                                                                                                         0.0000  3.7583  
+        sobel:core/ACC1:slc#25.itm                                                                                                     0.0000  3.7583  
+        sobel:core/ACC1-1:acc#113                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#113.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#113.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#113.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#717                                                                                                            0.0000  4.2869  
+        sobel:core/conc#717.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#159                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#159.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#27                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#27.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#120                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#120.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#120.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#120.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#149                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#149.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#709                                                                                                            0.0000  5.2670  
+        sobel:core/conc#709.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#160                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#160.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#28                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#22.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#22.sva)#2                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#22.sva)#2.itm                                                                                          0.0000  5.7029  
+        sobel:core/conc#708                                                                                                            0.0000  5.7029  
+        sobel:core/conc#708.itm                                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:acc#161                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#161.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#29                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#24.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#24.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#24.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand#2                       mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand#2.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:conc#607                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#607.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#774                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#774.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#274                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#274.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#80                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#80.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#280                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#280.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#284                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#284.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#287                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#287.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#290                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#290.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#292                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#292.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#294                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#294.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#124                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#124.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#267                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#267.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#124                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#124.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      2                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#17                                                                                               0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#17.itm                                                                                           0.0000  2.3449  
+        sobel:core/conc#735                                                                                                            0.0000  2.3449  
+        sobel:core/conc#735.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#135                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#135.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#7                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#7.itm                                                                                                      0.0000  2.9974  
+        sobel:core/conc#734                                                                                                            0.0000  2.9974  
+        sobel:core/conc#734.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#737                                                                                                            0.0000  4.2869  
+        sobel:core/conc#737.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#2                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#2.itm                                                                                          0.0000  5.7029  
+        sobel:core/conc#728                                                                                                            0.0000  5.7029  
+        sobel:core/conc#728.itm                                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      3                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#2)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#2).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not#162                        mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not#162.itm                                                                                                    0.0000  0.0000  
+        sobel:core/ACC1:acc#153                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#153.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc#10                       mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc#10.psp#2.sva                                                                                                    0.0000  2.3449  
+        sobel:core/slc(acc#10.psp#2.sva)#17                                                                                            0.0000  2.3449  
+        sobel:core/slc(acc#10.psp#2.sva)#17.itm                                                                                        0.0000  2.3449  
+        sobel:core/conc#715                                                                                                            0.0000  2.3449  
+        sobel:core/conc#715.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#155                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#155.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#23                                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:slc#23.itm                                                                                                     0.0000  2.9974  
+        sobel:core/conc#714                                                                                                            0.0000  2.9974  
+        sobel:core/conc#714.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#157                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#157.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc#25                                                                                                         0.0000  3.7583  
+        sobel:core/ACC1:slc#25.itm                                                                                                     0.0000  3.7583  
+        sobel:core/ACC1-1:acc#113                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#113.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#113.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#113.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#717                                                                                                            0.0000  4.2869  
+        sobel:core/conc#717.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#159                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#159.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#27                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#27.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#120                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#120.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#120.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#120.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#149                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#149.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#709                                                                                                            0.0000  5.2670  
+        sobel:core/conc#709.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#160                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#160.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#28                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#22.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#22.sva)#2                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#22.sva)#2.itm                                                                                          0.0000  5.7029  
+        sobel:core/conc#708                                                                                                            0.0000  5.7029  
+        sobel:core/conc#708.itm                                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:acc#161                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#161.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#29                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#24.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#24.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#24.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand#2                       mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand#2.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:conc#607                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#607.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#774                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#774.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#274                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#274.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#80                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#80.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#280                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#280.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#284                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#284.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#287                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#287.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#290                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#290.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#292                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#292.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#294                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#294.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#124                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#124.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#267                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#267.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#124                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#124.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      4                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#17                                                                                               0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#17.itm                                                                                           0.0000  2.3449  
+        sobel:core/conc#735                                                                                                            0.0000  2.3449  
+        sobel:core/conc#735.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#135                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#135.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#7                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#7.itm                                                                                                      0.0000  2.9974  
+        sobel:core/conc#734                                                                                                            0.0000  2.9974  
+        sobel:core/conc#734.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#737                                                                                                            0.0000  4.2869  
+        sobel:core/conc#737.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3.itm                                                                                          0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                       mgc_not_1                                                                       0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:conc#459                                                                                                       0.0000  5.7029  
+        sobel:core/ACC1:conc#459.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      5                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#7                                                                                                0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#7.itm                                                                                            0.0000  2.3449  
+        sobel:core/ACC1-1:not#107                      mgc_not_1                                                                       0.0000  2.3449  
+        sobel:core/ACC1-1:not#107.itm                                                                                                  0.0000  2.3449  
+        sobel:core/ACC1:conc#446                                                                                                       0.0000  2.3449  
+        sobel:core/ACC1:conc#446.itm                                                                                                   0.0000  2.3449  
+        sobel:core/ACC1:acc#135                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#135.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#7                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#7.itm                                                                                                      0.0000  2.9974  
+        sobel:core/conc#734                                                                                                            0.0000  2.9974  
+        sobel:core/conc#734.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#737                                                                                                            0.0000  4.2869  
+        sobel:core/conc#737.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3.itm                                                                                          0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                       mgc_not_1                                                                       0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:conc#459                                                                                                       0.0000  5.7029  
+        sobel:core/ACC1:conc#459.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      6                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#6                                                                                                0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#6.itm                                                                                            0.0000  2.3449  
+        sobel:core/conc#736                                                                                                            0.0000  2.3449  
+        sobel:core/conc#736.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#134                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#134.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#9                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#9.itm                                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:conc#450                                                                                                       0.0000  2.9974  
+        sobel:core/ACC1:conc#450.itm                                                                                                   0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#737                                                                                                            0.0000  4.2869  
+        sobel:core/conc#737.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3.itm                                                                                          0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                       mgc_not_1                                                                       0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:conc#459                                                                                                       0.0000  5.7029  
+        sobel:core/ACC1:conc#459.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      7                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#17                                                                                               0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#17.itm                                                                                           0.0000  2.3449  
+        sobel:core/conc#735                                                                                                            0.0000  2.3449  
+        sobel:core/conc#735.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#135                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#135.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#7                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#7.itm                                                                                                      0.0000  2.9974  
+        sobel:core/conc#734                                                                                                            0.0000  2.9974  
+        sobel:core/conc#734.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#4                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#4.itm                                                                                   0.0000  4.2869  
+        sobel:core/ACC1-1:not#133                      mgc_not_1                                                                       0.0000  4.2869  
+        sobel:core/ACC1-1:not#133.itm                                                                                                  0.0000  4.2869  
+        sobel:core/ACC1:conc#454                                                                                                       0.0000  4.2869  
+        sobel:core/ACC1:conc#454.itm                                                                                                   0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3.itm                                                                                          0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                       mgc_not_1                                                                       0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:conc#459                                                                                                       0.0000  5.7029  
+        sobel:core/ACC1:conc#459.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      8                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#6                                                                                                0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#6.itm                                                                                            0.0000  2.3449  
+        sobel:core/conc#736                                                                                                            0.0000  2.3449  
+        sobel:core/conc#736.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#134                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#134.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#9                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#9.itm                                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:conc#450                                                                                                       0.0000  2.9974  
+        sobel:core/ACC1:conc#450.itm                                                                                                   0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#4                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#4.itm                                                                                   0.0000  4.2869  
+        sobel:core/ACC1-1:not#133                      mgc_not_1                                                                       0.0000  4.2869  
+        sobel:core/ACC1-1:not#133.itm                                                                                                  0.0000  4.2869  
+        sobel:core/ACC1:conc#454                                                                                                       0.0000  4.2869  
+        sobel:core/ACC1:conc#454.itm                                                                                                   0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3.itm                                                                                          0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                       mgc_not_1                                                                       0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:conc#459                                                                                                       0.0000  5.7029  
+        sobel:core/ACC1:conc#459.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      9                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#7                                                                                                0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#7.itm                                                                                            0.0000  2.3449  
+        sobel:core/ACC1-1:not#107                      mgc_not_1                                                                       0.0000  2.3449  
+        sobel:core/ACC1-1:not#107.itm                                                                                                  0.0000  2.3449  
+        sobel:core/ACC1:conc#446                                                                                                       0.0000  2.3449  
+        sobel:core/ACC1:conc#446.itm                                                                                                   0.0000  2.3449  
+        sobel:core/ACC1:acc#135                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#135.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#7                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#7.itm                                                                                                      0.0000  2.9974  
+        sobel:core/conc#734                                                                                                            0.0000  2.9974  
+        sobel:core/conc#734.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#4                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#4.itm                                                                                   0.0000  4.2869  
+        sobel:core/ACC1-1:not#133                      mgc_not_1                                                                       0.0000  4.2869  
+        sobel:core/ACC1-1:not#133.itm                                                                                                  0.0000  4.2869  
+        sobel:core/ACC1:conc#454                                                                                                       0.0000  4.2869  
+        sobel:core/ACC1:conc#454.itm                                                                                                   0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3.itm                                                                                          0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                       mgc_not_1                                                                       0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:conc#459                                                                                                       0.0000  5.7029  
+        sobel:core/ACC1:conc#459.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      10                                               sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not#163                        mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not#163.itm                                                                                                    0.0000  0.0000  
+        sobel:core/ACC1:acc#152                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#152.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc#10                       mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc#10.psp#2.sva                                                                                                    0.0000  2.3449  
+        sobel:core/slc(acc#10.psp#2.sva)#17                                                                                            0.0000  2.3449  
+        sobel:core/slc(acc#10.psp#2.sva)#17.itm                                                                                        0.0000  2.3449  
+        sobel:core/conc#715                                                                                                            0.0000  2.3449  
+        sobel:core/conc#715.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#155                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#155.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#23                                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:slc#23.itm                                                                                                     0.0000  2.9974  
+        sobel:core/conc#714                                                                                                            0.0000  2.9974  
+        sobel:core/conc#714.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#157                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#157.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc#25                                                                                                         0.0000  3.7583  
+        sobel:core/ACC1:slc#25.itm                                                                                                     0.0000  3.7583  
+        sobel:core/ACC1-1:acc#113                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#113.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#113.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#113.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#717                                                                                                            0.0000  4.2869  
+        sobel:core/conc#717.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#159                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#159.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#27                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#27.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#120                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#120.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#120.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#120.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#149                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#149.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#709                                                                                                            0.0000  5.2670  
+        sobel:core/conc#709.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#160                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#160.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#28                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#22.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#22.sva)#2                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#22.sva)#2.itm                                                                                          0.0000  5.7029  
+        sobel:core/conc#708                                                                                                            0.0000  5.7029  
+        sobel:core/conc#708.itm                                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:acc#161                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#161.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#29                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#24.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#24.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#24.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand#2                       mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand#2.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:conc#607                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#607.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#774                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#774.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#274                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#274.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#80                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#80.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#280                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#280.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#284                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#284.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#287                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#287.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#290                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#290.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#292                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#292.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#294                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#294.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#124                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#124.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#267                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#267.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#124                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#124.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                         Port                                   Slack (Delay) Messages 
+      ------------------------------------------------ ------------------------------------ ------- ------- --------
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)        mux.itm                               4.7285 15.2715          
+      sobel:core/reg(in(2).sva#1)                      mux#1.itm                            17.5676  2.4324          
+      sobel:core/reg(ACC1:acc#341.itm#1)               ACC1:acc#341.itm                      4.1682 15.8318          
+      sobel:core/reg(in(0).sva#1)                      mux#2.itm                            17.5676  2.4324          
+      sobel:core/reg(exit:FRAME:for.sva#1.st#1)        FRAME:for:not#7.itm                  18.4843  1.5157          
+      sobel:core/reg(FRAME:for:acc#26.itm#1)           FRAME:for:acc#26.itm                 12.8675  7.1325          
+      sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1)   ACC1-3:acc#124.itm                    3.9559 16.0441          
+      sobel:core/reg(exit:FRAME:for.lpi#1.dfm#3)       exit:FRAME:for.lpi#1.dfm#4           12.6737  7.3263          
+      sobel:core/reg(FRAME:for:acc#24.itm#1)           FRAME:for:acc#24.itm                 12.5726  7.4274          
+      sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1)   ACC1-3:acc#122.itm                    3.9559 16.0441          
+      sobel:core/reg(i#6.sva#1)                        i#6.sva#2                            17.8528  2.1472          
+      sobel:core/reg(exit:FRAME#1.sva)                 FRAME:and.itm                        16.3597  3.6403          
+      sobel:core/reg(main.stage_0#2)                   Cn1_1#2                              20.0000  0.0000          
+      sobel:core/reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1) ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0  6.4362 13.5638          
+      sobel:core/reg(ACC1:acc#125.psp.lpi#1.dfm)       ACC1:acc#125.psp.lpi#1.dfm:mx0        6.3282 13.6718          
+      sobel:core/reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)   ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0    7.7867 12.2133          
+      sobel:core/reg(regs.regs(2).lpi#1.dfm.sg2)       regs.regs(2).lpi#1.dfm.sg2:mx0       12.8675  7.1325          
+      sobel:core/reg(regs.regs(2).lpi#1.dfm#1)         regs.regs(2).lpi#1.dfm#1:mx0         12.5726  7.4274          
+      sobel:core/reg(acc.imod#7.lpi#1.dfm)             acc.imod#7.lpi#1.dfm:mx0              4.1682 15.8318          
+      sobel:core/reg(acc.imod#6.lpi#1.dfm.sg1)         acc.imod#6.lpi#1.dfm.sg1:mx0          5.0202 14.9798          
+      sobel:core/reg(regs.regs(1).sva)                 regs.regs(1).sva.dfm:mx0             12.5726  7.4274          
+      sobel:core/reg(regs.regs(0).sva)                 regs.regs(0).sva.dfm:mx0             12.5726  7.4274          
+      sobel:core/reg(exit:FRAME.lpi#1.dfm#1)           exit:FRAME.lpi#1.dfm#1:mx0           16.3597  3.6403          
+      sobel:core/reg(ACC1:acc#125.psp#1.lpi#1.dfm)     ACC1:acc#125.psp#1.lpi#1.dfm:mx0      6.3282 13.6718          
+      sobel:core/reg(acc.imod#18.lpi#1.dfm.sg1)        acc.imod#18.lpi#1.dfm.sg1:mx0         5.0202 14.9798          
+      sobel:core/reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1) ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0  6.4362 13.5638          
+      sobel:core/reg(acc.imod#20.lpi#1.dfm)            acc.imod#20.lpi#1.dfm:mx0             4.9112 15.0888          
+      sobel:core/reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1) ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0  7.8794 12.1206          
+      sobel:core/reg(FRAME:p#1.lpi#1)                  mux#18.itm                           17.4604  2.5396          
+      sobel                                            vout:rsc.z                           20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                   19     1 
+    -                   16     4 
+    -                   13    14 
+    -                   12     7 
+    -                   11    17 
+    -                   10    17 
+    -                    9    10 
+    -                    8     8 
+    -                    7    15 
+    -                    6    15 
+    -                    5    39 
+    -                    4    79 
+    -                    3    25 
+    -                    2     8 
+    and                          
+    -                    3     6 
+    -                    2     5 
+    mul                          
+    -                   13     7 
+    -                   12     6 
+    -                    9     1 
+    mux                          
+    -                    2     6 
+    -                    1    21 
+    nand                         
+    -                    2     9 
+    nor                          
+    -                    2     2 
+    not                          
+    -                   10     9 
+    -                    3     4 
+    -                    2     8 
+    -                    1    92 
+    or                           
+    -                    3     1 
+    -                    2     4 
+    read_port                    
+    -                   90     1 
+    reg                          
+    -                   90     2 
+    -                   30     3 
+    -                   19     1 
+    -                   16     2 
+    -                   13     2 
+    -                   12     5 
+    -                    3     2 
+    -                    2     7 
+    -                    1     5 
+    write_port                   
+    -                   30     1 
+    
+  End of Report
diff --git a/Sobel/sobel.v7/rtl.v b/Sobel/sobel.v7/rtl.v
new file mode 100644
index 0000000..e50da8f
--- /dev/null
+++ b/Sobel/sobel.v7/rtl.v
@@ -0,0 +1,1557 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 15:20:14 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [1:0] acc_imod_7_lpi_1_dfm;
+  reg [11:0] ACC1_acc_125_psp_lpi_1_dfm;
+  reg [1:0] acc_imod_20_lpi_1_dfm;
+  reg [11:0] ACC1_acc_125_psp_1_lpi_1_dfm;
+  reg [15:0] in_0_sva_1;
+  reg [15:0] in_2_sva_1;
+  reg [1:0] i_6_sva_1;
+  reg exit_FRAME_lpi_1_dfm_1;
+  reg exit_FRAME_for_lpi_1_dfm_3;
+  reg [12:0] FRAME_for_acc_24_itm_1;
+  wire [14:0] nl_FRAME_for_acc_24_itm_1;
+  reg [11:0] FRAME_for_slc_in_0_sva_itm_1;
+  wire [14:0] nl_FRAME_for_slc_in_0_sva_itm_1;
+  reg [11:0] FRAME_for_acc_26_itm_1;
+  wire [13:0] nl_FRAME_for_acc_26_itm_1;
+  reg [11:0] FRAME_for_slc_in_2_sva_itm_1;
+  wire [14:0] nl_FRAME_for_slc_in_2_sva_itm_1;
+  reg [12:0] ACC1_acc_341_itm_1;
+  wire [14:0] nl_ACC1_acc_341_itm_1;
+  reg exit_FRAME_for_sva_1_st_1;
+  reg main_stage_0_2;
+  reg [1:0] acc_imod_6_lpi_1_dfm_sg1;
+  reg [29:0] regs_regs_2_lpi_1_dfm_sg2;
+  reg [29:0] regs_regs_2_lpi_1_dfm_1;
+  reg [1:0] ACC1_acc_118_psp_lpi_1_dfm_sg1;
+  reg [2:0] ACC1_acc_110_psp_1_lpi_1_dfm_sg1;
+  reg [1:0] acc_imod_18_lpi_1_dfm_sg1;
+  reg [1:0] ACC1_acc_118_psp_1_lpi_1_dfm_sg1;
+  reg [2:0] ACC1_acc_110_psp_2_lpi_1_dfm_sg1;
+  wire and_cse;
+  wire exit_FRAME_for_lpi_1_dfm_4;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+  wire [11:0] FRAME_acc_2_psp_sva;
+  wire [13:0] nl_FRAME_acc_2_psp_sva;
+  wire [5:0] acc_imod_12_sva;
+  wire [7:0] nl_acc_imod_12_sva;
+  wire [15:0] in_2_sva_3;
+  wire [16:0] nl_in_2_sva_3;
+  wire [15:0] in_0_sva_3;
+  wire [16:0] nl_in_0_sva_3;
+  wire [1:0] i_6_sva_2;
+  wire [2:0] nl_i_6_sva_2;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire [2:0] ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0;
+  wire [11:0] ACC1_acc_125_psp_lpi_1_dfm_mx0;
+  wire [1:0] ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0;
+  wire [29:0] regs_regs_2_lpi_1_dfm_sg2_mx0;
+  wire [29:0] regs_regs_2_lpi_1_dfm_1_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire [1:0] acc_imod_7_lpi_1_dfm_mx0;
+  wire [1:0] acc_imod_6_lpi_1_dfm_sg1_mx0;
+  wire [2:0] ACC1_acc_118_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_118_psp_1_sva;
+  wire [11:0] ACC1_acc_125_psp_1_sva;
+  wire [12:0] nl_ACC1_acc_125_psp_1_sva;
+  wire [11:0] ACC1_acc_125_psp_sva;
+  wire [12:0] nl_ACC1_acc_125_psp_sva;
+  wire [2:0] ACC1_acc_118_psp_sva;
+  wire [3:0] nl_ACC1_acc_118_psp_sva;
+  wire [11:0] acc_10_psp_1_sva;
+  wire [12:0] nl_acc_10_psp_1_sva;
+  wire [3:0] ACC1_acc_113_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_113_psp_1_sva;
+  wire [2:0] ACC1_acc_120_psp_sva;
+  wire [3:0] nl_ACC1_acc_120_psp_sva;
+  wire [2:0] ACC1_acc_250_cse;
+  wire [3:0] nl_ACC1_acc_250_cse;
+  wire [11:0] acc_10_psp_2_sva;
+  wire [12:0] nl_acc_10_psp_2_sva;
+  wire [3:0] ACC1_acc_113_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_113_psp_2_sva;
+  wire [2:0] ACC1_acc_120_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_120_psp_1_sva;
+  wire [2:0] ACC1_acc_277_cse;
+  wire [3:0] nl_ACC1_acc_277_cse;
+  wire [11:0] acc_psp_1_sva;
+  wire [12:0] nl_acc_psp_1_sva;
+  wire [3:0] ACC1_acc_107_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_107_psp_1_sva;
+  wire [2:0] ACC1_acc_116_psp_sva;
+  wire [3:0] nl_ACC1_acc_116_psp_sva;
+  wire [2:0] ACC1_acc_197_cse;
+  wire [3:0] nl_ACC1_acc_197_cse;
+  wire [11:0] acc_psp_2_sva;
+  wire [12:0] nl_acc_psp_2_sva;
+  wire [3:0] ACC1_acc_107_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_107_psp_2_sva;
+  wire [2:0] ACC1_acc_116_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_116_psp_1_sva;
+  wire [2:0] ACC1_acc_224_cse;
+  wire [3:0] nl_ACC1_acc_224_cse;
+  wire exit_FRAME_lpi_1_dfm_1_mx0;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [11:0] ACC1_acc_125_psp_1_lpi_1_dfm_mx0;
+  wire [1:0] acc_imod_18_lpi_1_dfm_sg1_mx0;
+  wire [2:0] ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0;
+  wire [1:0] acc_imod_20_lpi_1_dfm_mx0;
+  wire [1:0] ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0;
+  wire FRAME_for_nor_cse;
+  wire [15:0] ACC1_acc_itm;
+  wire [17:0] nl_ACC1_acc_itm;
+  wire [3:0] ACC1_acc_150_itm;
+  wire [4:0] nl_ACC1_acc_150_itm;
+  wire [4:0] ACC1_acc_148_itm;
+  wire [5:0] nl_ACC1_acc_148_itm;
+  wire [4:0] ACC1_acc_176_itm;
+  wire [5:0] nl_ACC1_acc_176_itm;
+  wire [3:0] ACC1_acc_178_itm;
+  wire [4:0] nl_ACC1_acc_178_itm;
+  wire [2:0] ACC1_acc_188_itm;
+  wire [3:0] nl_ACC1_acc_188_itm;
+  wire [2:0] ACC1_acc_161_itm;
+  wire [3:0] nl_ACC1_acc_161_itm;
+  wire [3:0] ACC1_acc_160_itm;
+  wire [4:0] nl_ACC1_acc_160_itm;
+  wire [3:0] ACC1_acc_187_itm;
+  wire [4:0] nl_ACC1_acc_187_itm;
+  wire [2:0] ACC1_acc_170_itm;
+  wire [3:0] nl_ACC1_acc_170_itm;
+  wire [2:0] ACC1_acc_141_itm;
+  wire [3:0] nl_ACC1_acc_141_itm;
+  wire [3:0] ACC1_acc_140_itm;
+  wire [4:0] nl_ACC1_acc_140_itm;
+  wire [3:0] ACC1_acc_169_itm;
+  wire [4:0] nl_ACC1_acc_169_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_3_itm;
+
+  wire[15:0] FRAME_for_mux_12_nl;
+  wire[15:0] FRAME_for_mux_11_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_2_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(ACC1_acc_itm[14:13])
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_itm[12:10])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_itm[9:4]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_12_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_12_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_12_sva[5:3])) , (~ (acc_imod_12_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_12_sva[4:3])) + conv_u2u_3_5(~ (ACC1_acc_itm[9:7])))
+      + ({4'b1001 , (acc_imod_12_sva[5])}))))) + conv_u2u_11_12(signext_11_9({(ACC1_acc_itm[15])
+      , 3'b0 , (signext_3_1(ACC1_acc_itm[15])) , 1'b0 , (ACC1_acc_itm[15])}));
+  assign FRAME_acc_2_psp_sva = nl_FRAME_acc_2_psp_sva[11:0];
+  assign nl_ACC1_acc_itm = (in_2_sva_3 + conv_s2s_13_16(ACC1_acc_341_itm_1)) + in_0_sva_3;
+  assign ACC1_acc_itm = nl_ACC1_acc_itm[15:0];
+  assign nl_acc_imod_12_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~ (ACC1_acc_itm[15]))
+      , 1'b1 , (~ (ACC1_acc_itm[15]))}) + conv_u2u_2_4(ACC1_acc_itm[14:13]))) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_itm[3:1])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[6:4])))) + 6'b101011;
+  assign acc_imod_12_sva = nl_acc_imod_12_sva[5:0];
+  assign FRAME_for_mux_12_nl = MUX_v_16_2_2({in_2_sva_1 , ({{4{FRAME_for_slc_in_2_sva_itm_1[11]}},
+      FRAME_for_slc_in_2_sva_itm_1})}, exit_FRAME_for_lpi_1_dfm_3);
+  assign nl_in_2_sva_3 = conv_s2u_12_16(FRAME_for_acc_26_itm_1) + (FRAME_for_mux_12_nl);
+  assign in_2_sva_3 = nl_in_2_sva_3[15:0];
+  assign FRAME_for_mux_11_nl = MUX_v_16_2_2({in_0_sva_1 , ({{4{FRAME_for_slc_in_0_sva_itm_1[11]}},
+      FRAME_for_slc_in_0_sva_itm_1})}, exit_FRAME_for_lpi_1_dfm_3);
+  assign nl_in_0_sva_3 = conv_s2u_13_16(FRAME_for_acc_24_itm_1) + (FRAME_for_mux_11_nl);
+  assign in_0_sva_3 = nl_in_0_sva_3[15:0];
+  assign nl_FRAME_for_acc_itm = i_6_sva_2 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  assign exit_FRAME_for_lpi_1_dfm_4 = exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva;
+  assign nl_i_6_sva_2 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_2 = nl_i_6_sva_2[1:0];
+  assign i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm_4));
+  assign ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0 = MUX_v_3_2_2({(ACC1_acc_176_itm[4:2])
+      , ACC1_acc_110_psp_1_lpi_1_dfm_sg1}, and_cse);
+  assign ACC1_acc_125_psp_lpi_1_dfm_mx0 = MUX_v_12_2_2({ACC1_acc_125_psp_sva , ACC1_acc_125_psp_lpi_1_dfm},
+      and_cse);
+  assign ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_118_psp_sva[2:1])
+      , ACC1_acc_118_psp_lpi_1_dfm_sg1}, and_cse);
+  assign regs_regs_2_lpi_1_dfm_sg2_mx0 = MUX_v_30_2_2({(regs_regs_1_sva[89:60]) ,
+      regs_regs_2_lpi_1_dfm_sg2}, and_cse);
+  assign regs_regs_2_lpi_1_dfm_1_mx0 = MUX_v_30_2_2({(regs_regs_1_sva[29:0]) , regs_regs_2_lpi_1_dfm_1},
+      and_cse);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_cse);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_cse);
+  assign acc_imod_7_lpi_1_dfm_mx0 = MUX_v_2_2_2({(readslicef_3_2_1((({1'b1 , (ACC1_acc_178_itm[1])
+      , 1'b1}) + conv_u2s_2_3({(~ (ACC1_acc_178_itm[2])) , (~ (ACC1_acc_178_itm[3]))}))))
+      , acc_imod_7_lpi_1_dfm}, and_cse);
+  assign acc_imod_6_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_178_itm[3:2]) , acc_imod_6_lpi_1_dfm_sg1},
+      and_cse);
+  assign nl_ACC1_acc_150_itm = conv_s2s_3_4({(~ (ACC1_acc_118_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_118_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_150_itm = nl_ACC1_acc_150_itm[3:0];
+  assign nl_ACC1_acc_118_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_148_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_148_itm[2])) , (ACC1_acc_148_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_148_itm[4]));
+  assign ACC1_acc_118_psp_1_sva = nl_ACC1_acc_118_psp_1_sva[2:0];
+  assign nl_ACC1_acc_148_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_125_psp_1_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_1_sva[2])) , (~ (ACC1_acc_125_psp_1_sva[6]))}))))
+      , (~ (ACC1_acc_125_psp_1_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_1_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_1_sva[4])) , (ACC1_acc_125_psp_1_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_125_psp_1_sva[11:10])) , (ACC1_acc_125_psp_1_sva[7])}))))
+      , (ACC1_acc_125_psp_1_sva[9])});
+  assign ACC1_acc_148_itm = nl_ACC1_acc_148_itm[4:0];
+  assign nl_ACC1_acc_125_psp_1_sva = conv_s2u_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[39:30]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[49:40]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[59:50])) + 11'b11);
+  assign ACC1_acc_125_psp_1_sva = nl_ACC1_acc_125_psp_1_sva[11:0];
+  assign nl_ACC1_acc_176_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_125_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_sva[2])) , (~ (ACC1_acc_125_psp_sva[6]))}))))
+      , (~ (ACC1_acc_125_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_sva[4])) , (ACC1_acc_125_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_125_psp_sva[11:10])) , (ACC1_acc_125_psp_sva[7])}))))
+      , (ACC1_acc_125_psp_sva[9])});
+  assign ACC1_acc_176_itm = nl_ACC1_acc_176_itm[4:0];
+  assign nl_ACC1_acc_125_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_1_sva[49:40])
+      + conv_s2s_10_11(regs_regs_1_sva[39:30])) + conv_s2u_10_12(regs_regs_1_sva[59:50]);
+  assign ACC1_acc_125_psp_sva = nl_ACC1_acc_125_psp_sva[11:0];
+  assign nl_ACC1_acc_118_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_176_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_176_itm[2])) , (ACC1_acc_176_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_176_itm[4]));
+  assign ACC1_acc_118_psp_sva = nl_ACC1_acc_118_psp_sva[2:0];
+  assign nl_ACC1_acc_178_itm = conv_s2s_3_4({(~ (ACC1_acc_118_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_118_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_178_itm = nl_ACC1_acc_178_itm[3:0];
+  assign nl_acc_10_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_1_sva[79:70])
+      + conv_s2s_10_11(regs_regs_1_sva[69:60])) + conv_s2s_10_12(regs_regs_1_sva[89:80]);
+  assign acc_10_psp_1_sva = nl_acc_10_psp_1_sva[11:0];
+  assign nl_ACC1_acc_113_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_10_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_10_psp_1_sva[1]))
+      , (acc_10_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_10_psp_1_sva[0])
+      , (acc_10_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_1_sva[3])) , (~ (acc_10_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_1_sva[5])) , (acc_10_psp_1_sva[6])}))))
+      , (~ (acc_10_psp_1_sva[9]))}))));
+  assign ACC1_acc_113_psp_1_sva = nl_ACC1_acc_113_psp_1_sva[3:0];
+  assign nl_ACC1_acc_120_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_113_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_113_psp_1_sva[1])) , (ACC1_acc_113_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_113_psp_1_sva[3]));
+  assign ACC1_acc_120_psp_sva = nl_ACC1_acc_120_psp_sva[2:0];
+  assign nl_ACC1_acc_250_cse = conv_u2u_2_3(signext_2_1(acc_10_psp_1_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_10_psp_1_sva[11]));
+  assign ACC1_acc_250_cse = nl_ACC1_acc_250_cse[2:0];
+  assign nl_ACC1_acc_188_itm = ({1'b1 , (ACC1_acc_187_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_187_itm[2])) , (~ (ACC1_acc_187_itm[3]))});
+  assign ACC1_acc_188_itm = nl_ACC1_acc_188_itm[2:0];
+  assign nl_acc_10_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[69:60]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[79:70]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[89:80])) + 11'b11);
+  assign acc_10_psp_2_sva = nl_acc_10_psp_2_sva[11:0];
+  assign nl_ACC1_acc_161_itm = ({1'b1 , (ACC1_acc_160_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_160_itm[2])) , (~ (ACC1_acc_160_itm[3]))});
+  assign ACC1_acc_161_itm = nl_ACC1_acc_161_itm[2:0];
+  assign nl_ACC1_acc_160_itm = conv_s2s_3_4({(~ (ACC1_acc_120_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_120_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_160_itm = nl_ACC1_acc_160_itm[3:0];
+  assign nl_ACC1_acc_113_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_10_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_10_psp_2_sva[1]))
+      , (acc_10_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_10_psp_2_sva[0])
+      , (acc_10_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_2_sva[3])) , (~ (acc_10_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_2_sva[5])) , (acc_10_psp_2_sva[6])}))))
+      , (~ (acc_10_psp_2_sva[9]))}))));
+  assign ACC1_acc_113_psp_2_sva = nl_ACC1_acc_113_psp_2_sva[3:0];
+  assign nl_ACC1_acc_120_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_113_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_113_psp_2_sva[1])) , (ACC1_acc_113_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_113_psp_2_sva[3]));
+  assign ACC1_acc_120_psp_1_sva = nl_ACC1_acc_120_psp_1_sva[2:0];
+  assign nl_ACC1_acc_277_cse = conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11]));
+  assign ACC1_acc_277_cse = nl_ACC1_acc_277_cse[2:0];
+  assign nl_ACC1_acc_187_itm = conv_s2s_3_4({(~ (ACC1_acc_120_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_120_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_187_itm = nl_ACC1_acc_187_itm[3:0];
+  assign nl_acc_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_1_sva[19:10])
+      + conv_s2s_10_11(regs_regs_1_sva[9:0])) + conv_s2s_10_12(regs_regs_1_sva[29:20]);
+  assign acc_psp_1_sva = nl_acc_psp_1_sva[11:0];
+  assign nl_ACC1_acc_107_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_1_sva[1])) , (acc_psp_1_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_1_sva[0]) , (acc_psp_1_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[3])) , (~ (acc_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[5])) , (acc_psp_1_sva[6])})))) ,
+      (~ (acc_psp_1_sva[9]))}))));
+  assign ACC1_acc_107_psp_1_sva = nl_ACC1_acc_107_psp_1_sva[3:0];
+  assign nl_ACC1_acc_116_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_107_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_107_psp_1_sva[1])) , (ACC1_acc_107_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_107_psp_1_sva[3]));
+  assign ACC1_acc_116_psp_sva = nl_ACC1_acc_116_psp_sva[2:0];
+  assign nl_ACC1_acc_197_cse = conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]));
+  assign ACC1_acc_197_cse = nl_ACC1_acc_197_cse[2:0];
+  assign nl_ACC1_acc_170_itm = ({1'b1 , (ACC1_acc_169_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_169_itm[2])) , (~ (ACC1_acc_169_itm[3]))});
+  assign ACC1_acc_170_itm = nl_ACC1_acc_170_itm[2:0];
+  assign nl_acc_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[9:0]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[19:10]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[29:20])) + 11'b11);
+  assign acc_psp_2_sva = nl_acc_psp_2_sva[11:0];
+  assign nl_ACC1_acc_141_itm = ({1'b1 , (ACC1_acc_140_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_140_itm[2])) , (~ (ACC1_acc_140_itm[3]))});
+  assign ACC1_acc_141_itm = nl_ACC1_acc_141_itm[2:0];
+  assign nl_ACC1_acc_140_itm = conv_s2s_3_4({(~ (ACC1_acc_116_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_116_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_140_itm = nl_ACC1_acc_140_itm[3:0];
+  assign nl_ACC1_acc_107_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_2_sva[1])) , (acc_psp_2_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_2_sva[0]) , (acc_psp_2_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[3])) , (~ (acc_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[5])) , (acc_psp_2_sva[6])})))) ,
+      (~ (acc_psp_2_sva[9]))}))));
+  assign ACC1_acc_107_psp_2_sva = nl_ACC1_acc_107_psp_2_sva[3:0];
+  assign nl_ACC1_acc_116_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_107_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_107_psp_2_sva[1])) , (ACC1_acc_107_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_107_psp_2_sva[3]));
+  assign ACC1_acc_116_psp_1_sva = nl_ACC1_acc_116_psp_1_sva[2:0];
+  assign nl_ACC1_acc_224_cse = conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11]));
+  assign ACC1_acc_224_cse = nl_ACC1_acc_224_cse[2:0];
+  assign nl_ACC1_acc_169_itm = conv_s2s_3_4({(~ (ACC1_acc_116_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_116_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_169_itm = nl_ACC1_acc_169_itm[3:0];
+  assign exit_FRAME_lpi_1_dfm_1_mx0 = MUX_s_1_2_2({(~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+      + 8'b10110101)))) , (exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm_4))},
+      FRAME_for_acc_itm[1]);
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign ACC1_acc_125_psp_1_lpi_1_dfm_mx0 = MUX_v_12_2_2({ACC1_acc_125_psp_1_sva
+      , ACC1_acc_125_psp_1_lpi_1_dfm}, and_cse);
+  assign acc_imod_18_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_150_itm[3:2]) , acc_imod_18_lpi_1_dfm_sg1},
+      and_cse);
+  assign ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0 = MUX_v_3_2_2({(ACC1_acc_148_itm[4:2])
+      , ACC1_acc_110_psp_2_lpi_1_dfm_sg1}, and_cse);
+  assign acc_imod_20_lpi_1_dfm_mx0 = MUX_v_2_2_2({(readslicef_3_2_1((({1'b1 , (ACC1_acc_150_itm[1])
+      , 1'b1}) + conv_u2s_2_3({(~ (ACC1_acc_150_itm[2])) , (~ (ACC1_acc_150_itm[3]))}))))
+      , acc_imod_20_lpi_1_dfm}, and_cse);
+  assign ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_118_psp_1_sva[2:1])
+      , ACC1_acc_118_psp_1_lpi_1_dfm_sg1}, and_cse);
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_3_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) |
+      FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+  assign and_cse = ~(exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva);
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      in_2_sva_1 <= 16'b0;
+      ACC1_acc_341_itm_1 <= 13'b0;
+      in_0_sva_1 <= 16'b0;
+      exit_FRAME_for_sva_1_st_1 <= 1'b0;
+      FRAME_for_acc_26_itm_1 <= 12'b0;
+      FRAME_for_slc_in_2_sva_itm_1 <= 12'b0;
+      exit_FRAME_for_lpi_1_dfm_3 <= 1'b0;
+      FRAME_for_acc_24_itm_1 <= 13'b0;
+      FRAME_for_slc_in_0_sva_itm_1 <= 12'b0;
+      i_6_sva_1 <= 2'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      ACC1_acc_110_psp_1_lpi_1_dfm_sg1 <= 3'b0;
+      ACC1_acc_125_psp_lpi_1_dfm <= 12'b0;
+      ACC1_acc_118_psp_lpi_1_dfm_sg1 <= 2'b0;
+      regs_regs_2_lpi_1_dfm_sg2 <= 30'b0;
+      regs_regs_2_lpi_1_dfm_1 <= 30'b0;
+      acc_imod_7_lpi_1_dfm <= 2'b0;
+      acc_imod_6_lpi_1_dfm_sg1 <= 2'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_1 <= 1'b0;
+      ACC1_acc_125_psp_1_lpi_1_dfm <= 12'b0;
+      acc_imod_18_lpi_1_dfm_sg1 <= 2'b0;
+      ACC1_acc_110_psp_2_lpi_1_dfm_sg1 <= 3'b0;
+      acc_imod_20_lpi_1_dfm <= 2'b0;
+      ACC1_acc_118_psp_1_lpi_1_dfm_sg1 <= 2'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({({((FRAME_acc_2_psp_sva[9:0])
+            | ({8'b0 , (FRAME_acc_2_psp_sva[11:10])})) , (FRAME_acc_2_psp_sva[9:6])
+            , ((FRAME_acc_2_psp_sva[5:0]) | ({4'b0 , (FRAME_acc_2_psp_sva[11:10])}))
+            , (FRAME_acc_2_psp_sva[9:0])}) , vout_rsc_mgc_out_stdreg_d}, ~(exit_FRAME_for_sva_1_st_1
+            & main_stage_0_2));
+        in_2_sva_1 <= MUX_v_16_2_2({in_2_sva_1 , in_2_sva_3}, main_stage_0_2);
+        ACC1_acc_341_itm_1 <= nl_ACC1_acc_341_itm_1[12:0];
+        in_0_sva_1 <= MUX_v_16_2_2({in_0_sva_1 , in_0_sva_3}, main_stage_0_2);
+        exit_FRAME_for_sva_1_st_1 <= ~ (FRAME_for_acc_itm[1]);
+        FRAME_for_acc_26_itm_1 <= nl_FRAME_for_acc_26_itm_1[11:0];
+        FRAME_for_slc_in_2_sva_itm_1 <= nl_FRAME_for_slc_in_2_sva_itm_1[11:0];
+        exit_FRAME_for_lpi_1_dfm_3 <= exit_FRAME_for_lpi_1_dfm_4;
+        FRAME_for_acc_24_itm_1 <= nl_FRAME_for_acc_24_itm_1[12:0];
+        FRAME_for_slc_in_0_sva_itm_1 <= nl_FRAME_for_slc_in_0_sva_itm_1[11:0];
+        i_6_sva_1 <= i_6_sva_2;
+        exit_FRAME_1_sva <= (~ (FRAME_for_acc_itm[1])) & exit_FRAME_lpi_1_dfm_1_mx0;
+        main_stage_0_2 <= 1'b1;
+        ACC1_acc_110_psp_1_lpi_1_dfm_sg1 <= ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0;
+        ACC1_acc_125_psp_lpi_1_dfm <= ACC1_acc_125_psp_lpi_1_dfm_mx0;
+        ACC1_acc_118_psp_lpi_1_dfm_sg1 <= ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0;
+        regs_regs_2_lpi_1_dfm_sg2 <= regs_regs_2_lpi_1_dfm_sg2_mx0;
+        regs_regs_2_lpi_1_dfm_1 <= regs_regs_2_lpi_1_dfm_1_mx0;
+        acc_imod_7_lpi_1_dfm <= acc_imod_7_lpi_1_dfm_mx0;
+        acc_imod_6_lpi_1_dfm_sg1 <= acc_imod_6_lpi_1_dfm_sg1_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_1 <= exit_FRAME_lpi_1_dfm_1_mx0;
+        ACC1_acc_125_psp_1_lpi_1_dfm <= ACC1_acc_125_psp_1_lpi_1_dfm_mx0;
+        acc_imod_18_lpi_1_dfm_sg1 <= acc_imod_18_lpi_1_dfm_sg1_mx0;
+        ACC1_acc_110_psp_2_lpi_1_dfm_sg1 <= ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0;
+        acc_imod_20_lpi_1_dfm <= acc_imod_20_lpi_1_dfm_mx0;
+        ACC1_acc_118_psp_1_lpi_1_dfm_sg1 <= ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0;
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_sva_1 , FRAME_p_1_lpi_1_dfm},
+            FRAME_for_acc_itm[1]);
+      end
+    end
+  end
+  assign nl_ACC1_acc_341_itm_1  = (conv_s2s_26_13(conv_u2s_2_13(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])) * 13'b1101000000001)
+      + conv_u2s_10_13((conv_u2u_9_10({conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[8])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[8])) * 6'b10101) , (ACC1_acc_125_psp_lpi_1_dfm_mx0[3])
+      , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}) + conv_u2u_8_10(conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[7])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[7])) * 8'b1010101) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[5])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[5])) * 6'b10101)) + conv_u2u_6_7({(ACC1_acc_125_psp_lpi_1_dfm_mx0[6])
+      , 1'b0 , (ACC1_acc_125_psp_lpi_1_dfm_mx0[4]) , 1'b0 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}))))
+      + conv_u2u_8_10((conv_u2u_7_8(signext_7_3({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (signext_2_1(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11]))})) + conv_u2u_6_8(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (acc_imod_18_lpi_1_dfm_sg1_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[4])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[2])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , ((ACC1_acc_125_psp_lpi_1_dfm_mx0[11]) & (~ (acc_imod_7_lpi_1_dfm_mx0[1]))
+      & (acc_imod_7_lpi_1_dfm_mx0[0]))}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[6])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[8])
+      , (~((acc_imod_7_lpi_1_dfm_mx0[1]) & (~ (ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))))})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[10])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (acc_imod_6_lpi_1_dfm_sg1_mx0[0])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[1])}))))))))) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[4:3]))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[6])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[8]) ,
+      (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[1])}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_125_psp_lpi_1_dfm_mx0[3])})))))) + conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_125_psp_lpi_1_dfm_mx0[2])
+      , (ACC1_acc_125_psp_lpi_1_dfm_mx0[0]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[2])
+      , (ACC1_acc_125_psp_lpi_1_dfm_mx0[1]) , (ACC1_acc_125_psp_lpi_1_dfm_mx0[2])}))))
+      , 1'b1}) + conv_u2u_4_5({(~ (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[2])) , 1'b1
+      , (~ (acc_imod_6_lpi_1_dfm_sg1_mx0[1])) , ((ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      & (~ (acc_imod_20_lpi_1_dfm_mx0[1])) & (acc_imod_20_lpi_1_dfm_mx0[0]))}))))))
+      + conv_u2u_4_7((readslicef_5_4_1((conv_u2u_4_5({(~ (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[2]))
+      , 1'b1 , (~ (acc_imod_18_lpi_1_dfm_sg1_mx0[1])) , 1'b1}) + conv_s2u_3_5({ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0
+      , (~((acc_imod_20_lpi_1_dfm_mx0[1]) & (~ (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11]))))}))))
+      + (readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_s2s_3_5({ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0 , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[1])})))))))))
+      + (conv_s2s_11_13(conv_u2s_10_12(conv_u2s_20_11(conv_u2u_2_10(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[9])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[9])) * 10'b101010101)) + conv_s2s_9_11(conv_s2s_7_9(conv_u2s_6_7({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[6])
+      , 1'b0 , (ACC1_acc_125_psp_lpi_1_dfm_mx0[6]) , 1'b0 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))})
+      + conv_s2s_5_7(({(conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[4]) + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[6]))
+      , (conv_u2u_2_3(signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[10])) + conv_u2u_2_3(signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])))})
+      + ({3'b100 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}))) + conv_u2s_7_9(signext_7_3({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))})))) + conv_u2s_11_13({conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[10])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[10])) * 8'b1010101) , (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[3])
+      , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}));
+  assign nl_FRAME_for_acc_26_itm_1  = (conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+      , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_sg2_mx0[19:10])
+      , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})))
+      + conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+      , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_sg2_mx0[9:0]) ,
+      10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))
+      + conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+      , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_sg2_mx0[29:20])
+      , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign nl_FRAME_for_slc_in_2_sva_itm_1  = conv_s2s_11_12(conv_u2s_10_11({(acc_10_psp_1_sva[11])
+      , 8'b0 , (acc_10_psp_1_sva[11])}) + (conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_10_psp_1_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_113_psp_1_sva[3])
+      , (acc_10_psp_1_sva[4])})))) + conv_s2s_2_3(ACC1_acc_120_psp_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_10_psp_1_sva[3])
+      , (acc_10_psp_1_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_113_psp_1_sva[3])
+      , (acc_10_psp_1_sva[2]) , (ACC1_acc_113_psp_1_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_10_psp_1_sva[7])
+      , (acc_10_psp_1_sva[4]) , (signext_2_1(acc_10_psp_1_sva[11]))}) + conv_u2u_3_5(ACC1_acc_250_cse)))
+      + conv_u2s_7_8({(acc_10_psp_1_sva[8]) , 1'b0 , (acc_10_psp_1_sva[8]) , 1'b0
+      , (acc_10_psp_1_sva[8]) , 1'b0 , (acc_10_psp_1_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_10_psp_1_sva[11])
+      , (signext_2_1(acc_10_psp_1_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_10_psp_1_sva[6])
+      , 1'b0 , (acc_10_psp_1_sva[6]) , 1'b0 , (acc_10_psp_1_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_250_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[9]) , ((acc_10_psp_1_sva[11])
+      & (~ (ACC1_acc_188_itm[2])) & (ACC1_acc_188_itm[1]))}))))))))) + conv_u2s_10_11({(acc_10_psp_1_sva[11])
+      , 1'b0 , (acc_10_psp_1_sva[11]) , 1'b0 , (acc_10_psp_1_sva[11]) , 1'b0 , (acc_10_psp_1_sva[11])
+      , 1'b0 , (signext_2_1(acc_10_psp_1_sva[11]))}))) + (conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_10_psp_2_sva[10])
+      , 1'b0 , (acc_10_psp_2_sva[10]) , 1'b0 , (acc_10_psp_2_sva[10]) , 1'b0 , (acc_10_psp_2_sva[10])
+      , 1'b0 , (acc_10_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_10_psp_2_sva[9]) ,
+      1'b0 , (acc_10_psp_2_sva[9]) , 1'b0 , (acc_10_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_10_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_10_psp_2_sva[7]) , 1'b0 , (acc_10_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_10_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (~((ACC1_acc_161_itm[2])
+      & (~ (acc_10_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (~ (ACC1_acc_160_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (ACC1_acc_160_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (ACC1_acc_113_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_10_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_113_psp_2_sva[3])
+      , (acc_10_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_120_psp_1_sva[2:1])) +
+      (readslicef_5_4_1((conv_u2s_3_5({(acc_10_psp_2_sva[3]) , (acc_10_psp_2_sva[1])
+      , 1'b1}) + conv_s2s_3_5({(ACC1_acc_113_psp_2_sva[3]) , (acc_10_psp_2_sva[2])
+      , (ACC1_acc_113_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_10_psp_2_sva[7])
+      , (acc_10_psp_2_sva[4]) , (signext_2_1(acc_10_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_277_cse)))
+      + conv_u2s_7_8({(acc_10_psp_2_sva[8]) , 1'b0 , (acc_10_psp_2_sva[8]) , 1'b0
+      , (acc_10_psp_2_sva[8]) , 1'b0 , (acc_10_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_10_psp_2_sva[11])
+      , (signext_2_1(acc_10_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_10_psp_2_sva[6])
+      , 1'b0 , (acc_10_psp_2_sva[6]) , 1'b0 , (acc_10_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_277_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[9]) , ((acc_10_psp_2_sva[11])
+      & (~ (ACC1_acc_161_itm[2])) & (ACC1_acc_161_itm[1]))})))))))))) + ({(acc_10_psp_2_sva[11])
+      , 2'b0 , (acc_10_psp_2_sva[11]) , 1'b0 , (acc_10_psp_2_sva[11]) , 1'b0 , (acc_10_psp_2_sva[11])
+      , (conv_u2u_1_3(acc_10_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11])))}))
+      + conv_u2s_10_12(conv_u2u_9_10({(acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10])
+      , 1'b0 , (acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10])})
+      + conv_u2u_8_10(({(acc_10_psp_1_sva[9]) , 1'b0 , (acc_10_psp_1_sva[9]) , 1'b0
+      , (acc_10_psp_1_sva[9]) , 1'b0 , (signext_2_1(acc_10_psp_1_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_10_psp_1_sva[7])
+      , 1'b0 , (acc_10_psp_1_sva[5]) , 1'b0 , (signext_2_1(acc_10_psp_1_sva[11]))})
+      + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (~((ACC1_acc_188_itm[2])
+      & (~ (acc_10_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (~ (ACC1_acc_187_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (ACC1_acc_187_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (ACC1_acc_113_psp_1_sva[2])})))))))))));
+  assign nl_FRAME_for_acc_24_itm_1  = (conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+      , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_1_mx0[19:10]) ,
+      10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm}))) + conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0])
+      , (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_1_mx0[9:0]) , 10'b0},
+      i_6_lpi_1_dfm)) * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})))) + conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+      , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_1_mx0[29:20]) ,
+      10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign nl_FRAME_for_slc_in_0_sva_itm_1  = conv_s2s_11_12(conv_u2s_10_11({(acc_psp_1_sva[11])
+      , 8'b0 , (acc_psp_1_sva[11])}) + (conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_psp_1_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_107_psp_1_sva[3]) ,
+      (acc_psp_1_sva[4])})))) + conv_s2s_2_3(ACC1_acc_116_psp_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_1_sva[3])
+      , (acc_psp_1_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_107_psp_1_sva[3]) ,
+      (acc_psp_1_sva[2]) , (ACC1_acc_107_psp_1_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_1_sva[7])
+      , (acc_psp_1_sva[4]) , (signext_2_1(acc_psp_1_sva[11]))}) + conv_u2u_3_5(ACC1_acc_197_cse)))
+      + conv_u2s_7_8({(acc_psp_1_sva[8]) , 1'b0 , (acc_psp_1_sva[8]) , 1'b0 , (acc_psp_1_sva[8])
+      , 1'b0 , (acc_psp_1_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_1_sva[11])
+      , (signext_2_1(acc_psp_1_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_1_sva[6])
+      , 1'b0 , (acc_psp_1_sva[6]) , 1'b0 , (acc_psp_1_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_197_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[9]) , ((acc_psp_1_sva[11])
+      & (~ (ACC1_acc_170_itm[2])) & (ACC1_acc_170_itm[1]))}))))))))) + conv_u2s_10_11({(acc_psp_1_sva[11])
+      , 1'b0 , (acc_psp_1_sva[11]) , 1'b0 , (acc_psp_1_sva[11]) , 1'b0 , (acc_psp_1_sva[11])
+      , 1'b0 , (signext_2_1(acc_psp_1_sva[11]))}))) + (conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_psp_2_sva[9]) , 1'b0
+      , (acc_psp_2_sva[9]) , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_2_sva[7]) , 1'b0 , (acc_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~((ACC1_acc_141_itm[2])
+      & (~ (acc_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~ (ACC1_acc_140_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_140_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_107_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_107_psp_2_sva[3]) ,
+      (acc_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_116_psp_1_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_2_sva[3])
+      , (acc_psp_2_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_107_psp_2_sva[3]) ,
+      (acc_psp_2_sva[2]) , (ACC1_acc_107_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_2_sva[7])
+      , (acc_psp_2_sva[4]) , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_224_cse)))
+      + conv_u2s_7_8({(acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])
+      , 1'b0 , (acc_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_2_sva[6])
+      , 1'b0 , (acc_psp_2_sva[6]) , 1'b0 , (acc_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_224_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , ((acc_psp_2_sva[11])
+      & (~ (ACC1_acc_141_itm[2])) & (ACC1_acc_141_itm[1]))})))))))))) + ({(acc_psp_2_sva[11])
+      , 2'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11])
+      , (conv_u2u_1_3(acc_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])))}))
+      + conv_u2s_10_12(conv_u2u_9_10({(acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10])
+      , 1'b0 , (acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10])})
+      + conv_u2u_8_10(({(acc_psp_1_sva[9]) , 1'b0 , (acc_psp_1_sva[9]) , 1'b0 , (acc_psp_1_sva[9])
+      , 1'b0 , (signext_2_1(acc_psp_1_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_1_sva[7])
+      , 1'b0 , (acc_psp_1_sva[5]) , 1'b0 , (signext_2_1(acc_psp_1_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (~((ACC1_acc_170_itm[2])
+      & (~ (acc_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (~ (ACC1_acc_169_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_169_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_107_psp_1_sva[2])})))))))))));
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] MUX_v_3_2_2;
+    input [5:0] inputs;
+    input [0:0] sel;
+    reg [2:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[5:3];
+      end
+      1'b1 : begin
+        result = inputs[2:0];
+      end
+      default : begin
+        result = inputs[5:3];
+      end
+    endcase
+    MUX_v_3_2_2 = result;
+  end
+  endfunction
+
+
+  function [11:0] MUX_v_12_2_2;
+    input [23:0] inputs;
+    input [0:0] sel;
+    reg [11:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[23:12];
+      end
+      1'b1 : begin
+        result = inputs[11:0];
+      end
+      default : begin
+        result = inputs[23:12];
+      end
+    endcase
+    MUX_v_12_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] MUX_v_2_2_2;
+    input [3:0] inputs;
+    input [0:0] sel;
+    reg [1:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[3:2];
+      end
+      1'b1 : begin
+        result = inputs[1:0];
+      end
+      default : begin
+        result = inputs[3:2];
+      end
+    endcase
+    MUX_v_2_2_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [6:0] signext_7_3;
+    input [2:0] vector;
+  begin
+    signext_7_3= {{4{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_2;
+    input [1:0] vector;
+  begin
+    signext_3_2= {{1{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_13_16 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_16 = {{3{vector[12]}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_13_16 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2u_13_16 = {{3{vector[12]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_26_13 ;
+    input signed [25:0]  vector ;
+  begin
+    conv_s2s_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_12_6 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_6 = vector[5:0];
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_2_6 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_6 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_2_8 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_8 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_4_7 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_7 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_s2u_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2u_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_11_13 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_13 = {{2{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_9_11 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_11 = {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2s_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_6_8 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_8 = {{2{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2s_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v7/rtl.v.psr b/Sobel/sobel.v7/rtl.v.psr
new file mode 100644
index 0000000..47be6d0
--- /dev/null
+++ b/Sobel/sobel.v7/rtl.v.psr
@@ -0,0 +1,289 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v7/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v7/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v7/rtl.v}} -format verilog
+   setup_design -design=sobel
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'sobel': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'sobel': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'sobel'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'sobel'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to vout_rsc_z(29:0)
+   report_timing -from en -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from vin_rsc_z(89:0) -to vout_rsc_z(29:0)
+   report_timing -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock clk] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock en] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'sobel'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'sobel'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v7 mapped.v]
+          puts "-- Writing mapped netlist for 'sobel' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v7 gate.v]
+          set gate_sdf [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v7 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/Sobel/sobel.v7/rtl.v.psr_timing b/Sobel/sobel.v7/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/Sobel/sobel.v7/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/Sobel/sobel.v7/rtl.v_order.txt b/Sobel/sobel.v7/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/Sobel/sobel.v7/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/Sobel/sobel.v7/rtl_mgc_ioport.v b/Sobel/sobel.v7/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v7/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v7/rtl_mgc_ioport_v2001.v b/Sobel/sobel.v7/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v7/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v7/schedule.gnt b/Sobel/sobel.v7/schedule.gnt
new file mode 100644
index 0000000..c9d2735
--- /dev/null
+++ b/Sobel/sobel.v7/schedule.gnt
@@ -0,0 +1,1570 @@
+set a(0-2827) {NAME i:asn(i#6.lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21006 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2828) {NAME in:asn(in(2).lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21007 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2829) {NAME in:asn(in(0).lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21008 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2830) {NAME ACC1:asn(acc.imod#7.lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21009 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2831) {NAME ACC1:asn(acc.imod#6.lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21010 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2832) {NAME ACC1:asn(ACC1:acc#118.psp.lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21011 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2833) {NAME ACC1:asn(ACC1:acc#110.psp#1.lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21012 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2834) {NAME ACC1:asn(ACC1:acc#125.psp.lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21013 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2835) {NAME ACC1:asn(acc.imod#20.lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21014 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2836) {NAME ACC1:asn(acc.imod#18.lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21015 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2837) {NAME ACC1:asn(ACC1:acc#118.psp#1.lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21016 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2838) {NAME ACC1:asn(ACC1:acc#110.psp#2.lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21017 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2839) {NAME ACC1:asn(ACC1:acc#125.psp#1.lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21018 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2840) {NAME regs.regs:asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21019 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2841) {NAME FRAME:asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21020 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2842) {NAME FRAME:for:asn(exit:FRAME:for.lpi#1)#1 TYPE ASSIGN PAR 0-2826 XREFS 21021 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2843) {NAME FRAME:p:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-2826 XREFS 21022 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2844) {NAME asn(regs.regs(1))#1 TYPE ASSIGN PAR 0-2826 XREFS 21023 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2845) {NAME asn(regs.regs(0))#1 TYPE ASSIGN PAR 0-2826 XREFS 21024 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{258 0 0-2847 {}}} CYCLES {}}
+set a(0-2846) {NAME FRAME:for:asn(exit:FRAME#1) TYPE ASSIGN PAR 0-2826 XREFS 21025 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-2847 {}}} SUCCS {{259 0 0-2847 {}}} CYCLES {}}
+set a(0-2848) {NAME FRAME:asn(exit:FRAME.sva#1) TYPE ASSIGN PAR 0-2847 XREFS 21026 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 1 0.9769393999999999} PREDS {} SUCCS {{258 0 0-4365 {}} {258 0 0-4366 {}}} CYCLES {}}
+set a(0-2849) {NAME FRAME:p:asn(FRAME:p#1.sva#1) TYPE ASSIGN PAR 0-2847 XREFS 21027 LOC {0 1.0 1 0.9245549 1 0.9245549 2 0.7658281499999999} PREDS {} SUCCS {{258 0 0-4379 {}}} CYCLES {}}
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+set a(0-2851) {NAME in:asn(in(0).sva) TYPE ASSIGN PAR 0-2847 XREFS 21029 LOC {0 1.0 1 1.0 1 1.0 2 0.17449594999999998} PREDS {} SUCCS {{258 0 0-3967 {}}} CYCLES {}}
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+set a(0-2853) {NAME ACC1:asn(acc.imod#6.sva) TYPE ASSIGN PAR 0-2847 XREFS 21031 LOC {0 1.0 1 0.38368015 1 0.38368015 1 0.59843245} PREDS {} SUCCS {{258 0 0-3914 {}}} CYCLES {}}
+set a(0-2854) {NAME ACC1:asn(ACC1:acc#118.psp.sva) TYPE ASSIGN PAR 0-2847 XREFS 21032 LOC {0 1.0 1 0.356434225 1 0.356434225 1 0.744095325} PREDS {} SUCCS {{258 0 0-3923 {}}} CYCLES {}}
+set a(0-2855) {NAME ACC1:asn(ACC1:acc#110.psp#1.sva) TYPE ASSIGN PAR 0-2847 XREFS 21033 LOC {0 1.0 1 0.295178375 1 0.295178375 1 0.59843245} PREDS {} SUCCS {{258 0 0-3925 {}}} CYCLES {}}
+set a(0-2856) {NAME ACC1:asn(ACC1:acc#125.psp.sva) TYPE ASSIGN PAR 0-2847 XREFS 21034 LOC {0 1.0 1 0.18306899999999998 1 0.18306899999999998 1 0.47957327499999997} PREDS {} SUCCS {{258 0 0-3924 {}}} CYCLES {}}
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+set a(0-2859) {NAME ACC1:asn(ACC1:acc#118.psp#1.sva) TYPE ASSIGN PAR 0-2847 XREFS 21037 LOC {0 1.0 1 0.38368015 1 0.38368015 1 0.749886225} PREDS {} SUCCS {{258 0 0-3931 {}}} CYCLES {}}
+set a(0-2860) {NAME ACC1:asn(ACC1:acc#110.psp#2.sva) TYPE ASSIGN PAR 0-2847 XREFS 21038 LOC {0 1.0 1 0.3224243 1 0.3224243 1 0.59843245} PREDS {} SUCCS {{258 0 0-3933 {}}} CYCLES {}}
+set a(0-2861) {NAME ACC1:asn(ACC1:acc#125.psp#1.sva) TYPE ASSIGN PAR 0-2847 XREFS 21039 LOC {0 1.0 1 0.21031492499999999 1 0.21031492499999999 1 0.47957327499999997} PREDS {} SUCCS {{258 0 0-3932 {}}} CYCLES {}}
+set a(0-2862) {NAME regs.regs:asn(regs.regs(0).sva#1) TYPE ASSIGN PAR 0-2847 XREFS 21040 LOC {0 1.0 1 0.013988325 1 0.013988325 1 0.6501168749999999} PREDS {} SUCCS {{258 0 0-3917 {}}} CYCLES {}}
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{146 0 0-3862 {}} {146 0 0-3863 {}} {146 0 0-3864 {}} {146 0 0-3865 {}} {146 0 0-3866 {}} {146 0 0-3867 {}} {146 0 0-3868 {}} {146 0 0-3869 {}} {146 0 0-3870 {}} {146 0 0-3871 {}} {146 0 0-3872 {}} {146 0 0-3873 {}} {146 0 0-3874 {}} {146 0 0-3875 {}} {146 0 0-3876 {}} {146 0 0-3877 {}} {146 0 0-3878 {}} {146 0 0-3879 {}} {146 0 0-3880 {}} {146 0 0-3881 {}} {146 0 0-3882 {}} {146 0 0-3883 {}} {146 0 0-3884 {}} {146 0 0-3885 {}} {146 0 0-3886 {}} {146 0 0-3887 {}} {146 0 0-3888 {}} {146 0 0-3889 {}} {146 0 0-3890 {}} {146 0 0-3891 {}} {146 0 0-3892 {}} {146 0 0-3893 {}} {146 0 0-3894 {}} {146 0 0-3895 {}} {146 0 0-3896 {}} {146 0 0-3897 {}} {146 0 0-3898 {}} {146 0 0-3899 {}} {146 0 0-3900 {}} {146 0 0-3901 {}} {146 0 0-3902 {}} {146 0 0-3903 {}} {146 0 0-3904 {}} {146 0 0-3905 {}} {146 0 0-3906 {}} {146 0 0-3907 {}} {146 0 0-3908 {}} {146 0 0-3909 {}} {146 0 0-3910 {}} {146 0 0-3911 {}} {146 0 0-3912 {}} {146 0 0-3913 {}}} CYCLES {}}
+set a(0-2872) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,90) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_read(vin:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-2847 XREFS 21050 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-2871 {}}} SUCCS {{259 0 0-2873 {}} {258 0 0-2875 {}} {258 0 0-2878 {}} {258 0 0-2949 {}} {258 0 0-2951 {}} {258 0 0-2954 {}} {258 0 0-3022 {}} {258 0 0-3024 {}} {258 0 0-3027 {}} {258 0 0-3917 {}}} CYCLES {}}
+set a(0-2873) {NAME regs.regs:slc(regs.regs(0)) TYPE READSLICE PAR 0-2847 XREFS 21051 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15869224999999998} PREDS {{146 0 0-2871 {}} {259 0 0-2872 {}}} SUCCS {{259 0 0-2874 {}}} CYCLES {}}
+set a(0-2874) {NAME ACC1:not TYPE NOT PAR 0-2847 XREFS 21052 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15869224999999998} PREDS {{146 0 0-2871 {}} {259 0 0-2873 {}}} SUCCS {{258 0 0-2877 {}}} CYCLES {}}
+set a(0-2875) {NAME regs.regs:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-2847 XREFS 21053 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15869224999999998} PREDS {{146 0 0-2871 {}} {258 0 0-2872 {}}} SUCCS {{259 0 0-2876 {}}} CYCLES {}}
+set a(0-2876) {NAME ACC1:not#156 TYPE NOT PAR 0-2847 XREFS 21054 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15869224999999998} PREDS {{146 0 0-2871 {}} {259 0 0-2875 {}}} SUCCS {{259 0 0-2877 {}}} CYCLES {}}
+set a(0-2877) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#133 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 21055 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.08517242833641131 1 0.2298763533364113} PREDS {{146 0 0-2871 {}} {258 0 0-2874 {}} {259 0 0-2876 {}}} SUCCS {{258 0 0-2881 {}}} CYCLES {}}
+set a(0-2878) {NAME regs.regs:slc(regs.regs(0))#2 TYPE READSLICE PAR 0-2847 XREFS 21056 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15869224999999998} PREDS {{146 0 0-2871 {}} {258 0 0-2872 {}}} SUCCS {{259 0 0-2879 {}}} CYCLES {}}
+set a(0-2879) {NAME ACC1:not#157 TYPE NOT PAR 0-2847 XREFS 21057 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15869224999999998} PREDS {{146 0 0-2871 {}} {259 0 0-2878 {}}} SUCCS {{259 0 0-2880 {}}} CYCLES {}}
+set a(0-2880) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#132 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 21058 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.08517242833641131 1 0.2298763533364113} PREDS {{146 0 0-2871 {}} {259 0 0-2879 {}}} SUCCS {{259 0 0-2881 {}}} CYCLES {}}
+set a(0-2881) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME ACC1-1:acc TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-2847 XREFS 21059 LOC {1 0.07118415 1 0.085172475 1 0.085172475 1 0.16054323137342835 1 0.30524715637342836} PREDS {{146 0 0-2871 {}} {258 0 0-2877 {}} {259 0 0-2880 {}}} SUCCS {{259 0 0-2882 {}} {258 0 0-2885 {}} {258 0 0-2887 {}} {258 0 0-2892 {}} {258 0 0-2894 {}} {258 0 0-2898 {}} {258 0 0-2900 {}} {258 0 0-2902 {}} {258 0 0-2908 {}} {258 0 0-2910 {}} {258 0 0-2912 {}} {258 0 0-2916 {}} {258 0 0-3404 {}} {258 0 0-3405 {}} {258 0 0-3406 {}} {258 0 0-3407 {}} {258 0 0-3408 {}} {258 0 0-3410 {}} {258 0 0-3411 {}} {258 0 0-3412 {}} {258 0 0-3413 {}} {258 0 0-3416 {}} {258 0 0-3417 {}} {258 0 0-3418 {}} {258 0 0-3421 {}} {258 0 0-3424 {}} {258 0 0-3427 {}} {258 0 0-3433 {}} {258 0 0-3436 {}} {258 0 0-3444 {}} {258 0 0-3447 {}} {258 0 0-3453 {}} {258 0 0-3456 {}} {258 0 0-3467 {}} {258 0 0-3471 {}} {258 0 0-3477 {}} {258 0 0-3478 {}} {258 0 0-3482 {}} {258 0 0-3489 {}} {258 0 0-3490 {}} {258 0 0-3491 {}} {258 0 0-3494 {}} {258 0 0-3496 {}} {258 0 0-3501 {}} {258 0 0-3502 {}} {258 0 0-3503 {}} {258 0 0-3504 {}} {258 0 0-3507 {}} {258 0 0-3508 {}} {258 0 0-3512 {}} {258 0 0-3513 {}} {258 0 0-3514 {}} {258 0 0-3516 {}} {258 0 0-3518 {}} {258 0 0-3521 {}} {258 0 0-3524 {}} {258 0 0-3526 {}} {258 0 0-3539 {}} {258 0 0-3540 {}} {258 0 0-3542 {}} {258 0 0-3543 {}} {258 0 0-3544 {}} {258 0 0-3545 {}} {258 0 0-3546 {}}} CYCLES {}}
+set a(0-2882) {NAME ACC1-1:slc(acc.psp)#11 TYPE READSLICE PAR 0-2847 XREFS 21060 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.32992167499999997} PREDS {{146 0 0-2871 {}} {259 0 0-2881 {}}} SUCCS {{259 0 0-2883 {}}} CYCLES {}}
+set a(0-2883) {NAME ACC1-1:not#151 TYPE NOT PAR 0-2847 XREFS 21061 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.32992167499999997} PREDS {{146 0 0-2871 {}} {259 0 0-2882 {}}} SUCCS {{259 0 0-2884 {}}} CYCLES {}}
+set a(0-2884) {NAME ACC1:conc#447 TYPE CONCATENATE PAR 0-2847 XREFS 21062 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.32992167499999997} PREDS {{146 0 0-2871 {}} {259 0 0-2883 {}}} SUCCS {{258 0 0-2889 {}}} CYCLES {}}
+set a(0-2885) {NAME ACC1-1:slc(acc.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21063 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.32992167499999997} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-2886 {}}} CYCLES {}}
+set a(0-2886) {NAME ACC1-1:not#106 TYPE NOT PAR 0-2847 XREFS 21064 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.32992167499999997} PREDS {{146 0 0-2871 {}} {259 0 0-2885 {}}} SUCCS {{258 0 0-2888 {}}} CYCLES {}}
+set a(0-2887) {NAME ACC1-1:slc(acc.psp)#8 TYPE READSLICE PAR 0-2847 XREFS 21065 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.32992167499999997} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-2888 {}}} CYCLES {}}
+set a(0-2888) {NAME ACC1:conc#448 TYPE CONCATENATE PAR 0-2847 XREFS 21066 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.32992167499999997} PREDS {{146 0 0-2871 {}} {258 0 0-2886 {}} {259 0 0-2887 {}}} SUCCS {{259 0 0-2889 {}}} CYCLES {}}
+set a(0-2889) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1:acc#136 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-2847 XREFS 21067 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.20569051008947523 1 0.3503944350894752} PREDS {{146 0 0-2871 {}} {258 0 0-2884 {}} {259 0 0-2888 {}}} SUCCS {{259 0 0-2890 {}}} CYCLES {}}
+set a(0-2890) {NAME ACC1:slc#8 TYPE READSLICE PAR 0-2847 XREFS 21068 LOC {1 0.16702775 1 0.20569055 1 0.20569055 1 0.350394475} PREDS {{146 0 0-2871 {}} {259 0 0-2889 {}}} SUCCS {{259 0 0-2891 {}}} CYCLES {}}
+set a(0-2891) {NAME ACC1:conc#451 TYPE CONCATENATE PAR 0-2847 XREFS 21069 LOC {1 0.16702775 1 0.20569055 1 0.20569055 1 0.350394475} PREDS {{146 0 0-2871 {}} {259 0 0-2890 {}}} SUCCS {{258 0 0-2896 {}}} CYCLES {}}
+set a(0-2892) {NAME ACC1-1:slc(acc.psp) TYPE READSLICE PAR 0-2847 XREFS 21070 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.350394475} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-2893 {}}} CYCLES {}}
+set a(0-2893) {NAME ACC1:conc#442 TYPE CONCATENATE PAR 0-2847 XREFS 21071 LOC {1 0.14655495 1 0.20569055 1 0.20569055 1 0.350394475} PREDS {{146 0 0-2871 {}} {259 0 0-2892 {}}} SUCCS {{258 0 0-2895 {}}} CYCLES {}}
+set a(0-2894) {NAME ACC1-1:slc(acc.psp)#10 TYPE READSLICE PAR 0-2847 XREFS 21072 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.350394475} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-2895 {}}} CYCLES {}}
+set a(0-2895) {NAME ACC1:conc#452 TYPE CONCATENATE PAR 0-2847 XREFS 21073 LOC {1 0.14655495 1 0.20569055 1 0.20569055 1 0.350394475} PREDS {{146 0 0-2871 {}} {258 0 0-2893 {}} {259 0 0-2894 {}}} SUCCS {{259 0 0-2896 {}}} CYCLES {}}
+set a(0-2896) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#138 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 21074 LOC {1 0.16702775 1 0.20569055 1 0.20569055 1 0.24888244517895047 1 0.3935863701789505} PREDS {{146 0 0-2871 {}} {258 0 0-2891 {}} {259 0 0-2895 {}}} SUCCS {{259 0 0-2897 {}}} CYCLES {}}
+set a(0-2897) {NAME ACC1:slc#10 TYPE READSLICE PAR 0-2847 XREFS 21075 LOC {1 0.21021969999999998 1 0.24888249999999998 1 0.24888249999999998 1 0.39358642499999996} PREDS {{146 0 0-2871 {}} {259 0 0-2896 {}}} SUCCS {{258 0 0-2921 {}}} CYCLES {}}
+set a(0-2898) {NAME ACC1-1:slc(acc.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21076 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-2899 {}}} CYCLES {}}
+set a(0-2899) {NAME ACC1:conc#445 TYPE CONCATENATE PAR 0-2847 XREFS 21077 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-2871 {}} {259 0 0-2898 {}}} SUCCS {{258 0 0-2905 {}}} CYCLES {}}
+set a(0-2900) {NAME ACC1-1:slc(acc.psp)#3 TYPE READSLICE PAR 0-2847 XREFS 21078 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-2901 {}}} CYCLES {}}
+set a(0-2901) {NAME ACC1-1:not#107 TYPE NOT PAR 0-2847 XREFS 21079 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-2871 {}} {259 0 0-2900 {}}} SUCCS {{258 0 0-2904 {}}} CYCLES {}}
+set a(0-2902) {NAME ACC1-1:slc(acc.psp)#7 TYPE READSLICE PAR 0-2847 XREFS 21080 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-2903 {}}} CYCLES {}}
+set a(0-2903) {NAME ACC1-1:not#109 TYPE NOT PAR 0-2847 XREFS 21081 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-2871 {}} {259 0 0-2902 {}}} SUCCS {{259 0 0-2904 {}}} CYCLES {}}
+set a(0-2904) {NAME ACC1:conc#446 TYPE CONCATENATE PAR 0-2847 XREFS 21082 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-2871 {}} {258 0 0-2901 {}} {259 0 0-2903 {}}} SUCCS {{259 0 0-2905 {}}} CYCLES {}}
+set a(0-2905) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#135 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21083 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.20132628508947523 1 0.3460302100894752} PREDS {{146 0 0-2871 {}} {258 0 0-2899 {}} {259 0 0-2904 {}}} SUCCS {{259 0 0-2906 {}}} CYCLES {}}
+set a(0-2906) {NAME ACC1:slc#7 TYPE READSLICE PAR 0-2847 XREFS 21084 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.34603025} PREDS {{146 0 0-2871 {}} {259 0 0-2905 {}}} SUCCS {{259 0 0-2907 {}}} CYCLES {}}
+set a(0-2907) {NAME ACC1:conc#449 TYPE CONCATENATE PAR 0-2847 XREFS 21085 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.34603025} PREDS {{146 0 0-2871 {}} {259 0 0-2906 {}}} SUCCS {{258 0 0-2919 {}}} CYCLES {}}
+set a(0-2908) {NAME ACC1-1:slc(acc.psp)#4 TYPE READSLICE PAR 0-2847 XREFS 21086 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-2909 {}}} CYCLES {}}
+set a(0-2909) {NAME ACC1:conc#443 TYPE CONCATENATE PAR 0-2847 XREFS 21087 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-2871 {}} {259 0 0-2908 {}}} SUCCS {{258 0 0-2914 {}}} CYCLES {}}
+set a(0-2910) {NAME ACC1-1:slc(acc.psp)#5 TYPE READSLICE PAR 0-2847 XREFS 21088 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-2911 {}}} CYCLES {}}
+set a(0-2911) {NAME ACC1-1:not#108 TYPE NOT PAR 0-2847 XREFS 21089 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-2871 {}} {259 0 0-2910 {}}} SUCCS {{258 0 0-2913 {}}} CYCLES {}}
+set a(0-2912) {NAME ACC1-1:slc(acc.psp)#6 TYPE READSLICE PAR 0-2847 XREFS 21090 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-2913 {}}} CYCLES {}}
+set a(0-2913) {NAME ACC1:conc#444 TYPE CONCATENATE PAR 0-2847 XREFS 21091 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-2871 {}} {258 0 0-2911 {}} {259 0 0-2912 {}}} SUCCS {{259 0 0-2914 {}}} CYCLES {}}
+set a(0-2914) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#134 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21092 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.20132628508947523 1 0.3460302100894752} PREDS {{146 0 0-2871 {}} {258 0 0-2909 {}} {259 0 0-2913 {}}} SUCCS {{259 0 0-2915 {}}} CYCLES {}}
+set a(0-2915) {NAME ACC1:slc#9 TYPE READSLICE PAR 0-2847 XREFS 21093 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.34603025} PREDS {{146 0 0-2871 {}} {259 0 0-2914 {}}} SUCCS {{258 0 0-2918 {}}} CYCLES {}}
+set a(0-2916) {NAME ACC1-1:slc(acc.psp)#9 TYPE READSLICE PAR 0-2847 XREFS 21094 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.34603025} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-2917 {}}} CYCLES {}}
+set a(0-2917) {NAME ACC1-1:not#110 TYPE NOT PAR 0-2847 XREFS 21095 LOC {1 0.14655495 1 0.201326325 1 0.201326325 1 0.34603025} PREDS {{146 0 0-2871 {}} {259 0 0-2916 {}}} SUCCS {{259 0 0-2918 {}}} CYCLES {}}
+set a(0-2918) {NAME ACC1:conc#450 TYPE CONCATENATE PAR 0-2847 XREFS 21096 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.34603025} PREDS {{146 0 0-2871 {}} {258 0 0-2915 {}} {259 0 0-2917 {}}} SUCCS {{259 0 0-2919 {}}} CYCLES {}}
+set a(0-2919) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#137 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21097 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.24888245207082718 1 0.39358637707082716} PREDS {{146 0 0-2871 {}} {258 0 0-2907 {}} {259 0 0-2918 {}}} SUCCS {{259 0 0-2920 {}}} CYCLES {}}
+set a(0-2920) {NAME ACC1:slc TYPE READSLICE PAR 0-2847 XREFS 21098 LOC {1 0.23489417499999998 1 0.24888249999999998 1 0.24888249999999998 1 0.39358642499999996} PREDS {{146 0 0-2871 {}} {259 0 0-2919 {}}} SUCCS {{259 0 0-2921 {}}} CYCLES {}}
+set a(0-2921) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1-1:acc#107 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-2847 XREFS 21099 LOC {1 0.23489417499999998 1 0.24888249999999998 1 0.24888249999999998 1 0.28191927017895047 1 0.4266231951789505} PREDS {{146 0 0-2871 {}} {258 0 0-2897 {}} {259 0 0-2920 {}}} SUCCS {{259 0 0-2922 {}} {258 0 0-2924 {}} {258 0 0-2926 {}} {258 0 0-2930 {}} {258 0 0-3458 {}} {258 0 0-3470 {}} {258 0 0-3481 {}} {258 0 0-3484 {}}} CYCLES {}}
+set a(0-2922) {NAME ACC1-1:slc(ACC1:acc#107.psp) TYPE READSLICE PAR 0-2847 XREFS 21100 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.42662324999999995} PREDS {{146 0 0-2871 {}} {259 0 0-2921 {}}} SUCCS {{259 0 0-2923 {}}} CYCLES {}}
+set a(0-2923) {NAME ACC1:conc#453 TYPE CONCATENATE PAR 0-2847 XREFS 21101 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.42662324999999995} PREDS {{146 0 0-2871 {}} {259 0 0-2922 {}}} SUCCS {{258 0 0-2928 {}}} CYCLES {}}
+set a(0-2924) {NAME ACC1-1:slc(ACC1:acc#107.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21102 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.42662324999999995} PREDS {{146 0 0-2871 {}} {258 0 0-2921 {}}} SUCCS {{259 0 0-2925 {}}} CYCLES {}}
+set a(0-2925) {NAME ACC1-1:not#133 TYPE NOT PAR 0-2847 XREFS 21103 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.42662324999999995} PREDS {{146 0 0-2871 {}} {259 0 0-2924 {}}} SUCCS {{258 0 0-2927 {}}} CYCLES {}}
+set a(0-2926) {NAME ACC1-1:slc(ACC1:acc#107.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21104 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.42662324999999995} PREDS {{146 0 0-2871 {}} {258 0 0-2921 {}}} SUCCS {{259 0 0-2927 {}}} CYCLES {}}
+set a(0-2927) {NAME ACC1:conc#454 TYPE CONCATENATE PAR 0-2847 XREFS 21105 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.42662324999999995} PREDS {{146 0 0-2871 {}} {258 0 0-2925 {}} {259 0 0-2926 {}}} SUCCS {{259 0 0-2928 {}}} CYCLES {}}
+set a(0-2928) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#139 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21106 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.3227023350894752 1 0.46740626008947517} PREDS {{146 0 0-2871 {}} {258 0 0-2923 {}} {259 0 0-2927 {}}} SUCCS {{259 0 0-2929 {}}} CYCLES {}}
+set a(0-2929) {NAME ACC1:slc#11 TYPE READSLICE PAR 0-2847 XREFS 21107 LOC {1 0.30871404999999996 1 0.322702375 1 0.322702375 1 0.4674063} PREDS {{146 0 0-2871 {}} {259 0 0-2928 {}}} SUCCS {{258 0 0-2932 {}}} CYCLES {}}
+set a(0-2930) {NAME ACC1-1:slc(ACC1:acc#107.psp)#3 TYPE READSLICE PAR 0-2847 XREFS 21108 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.4674063} PREDS {{146 0 0-2871 {}} {258 0 0-2921 {}}} SUCCS {{259 0 0-2931 {}}} CYCLES {}}
+set a(0-2931) {NAME ACC1-1:not#153 TYPE NOT PAR 0-2847 XREFS 21109 LOC {1 0.267931 1 0.322702375 1 0.322702375 1 0.4674063} PREDS {{146 0 0-2871 {}} {259 0 0-2930 {}}} SUCCS {{259 0 0-2932 {}}} CYCLES {}}
+set a(0-2932) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1-1:acc#116 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-2847 XREFS 21110 LOC {1 0.30871404999999996 1 0.322702375 1 0.322702375 1 0.3431751350894752 1 0.48787906008947524} PREDS {{146 0 0-2871 {}} {258 0 0-2929 {}} {259 0 0-2931 {}}} SUCCS {{259 0 0-2933 {}} {258 0 0-2936 {}} {258 0 0-3475 {}}} CYCLES {}}
+set a(0-2933) {NAME ACC1-1:slc(ACC1:acc#116.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21111 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.48787909999999995} PREDS {{146 0 0-2871 {}} {259 0 0-2932 {}}} SUCCS {{259 0 0-2934 {}}} CYCLES {}}
+set a(0-2934) {NAME ACC1-1:not#145 TYPE NOT PAR 0-2847 XREFS 21112 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.48787909999999995} PREDS {{146 0 0-2871 {}} {259 0 0-2933 {}}} SUCCS {{259 0 0-2935 {}}} CYCLES {}}
+set a(0-2935) {NAME ACC1:conc#455 TYPE CONCATENATE PAR 0-2847 XREFS 21113 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.48787909999999995} PREDS {{146 0 0-2871 {}} {259 0 0-2934 {}}} SUCCS {{258 0 0-2938 {}}} CYCLES {}}
+set a(0-2936) {NAME ACC1-1:slc(ACC1:acc#116.psp) TYPE READSLICE PAR 0-2847 XREFS 21114 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.48787909999999995} PREDS {{146 0 0-2871 {}} {258 0 0-2932 {}}} SUCCS {{259 0 0-2937 {}}} CYCLES {}}
+set a(0-2937) {NAME ACC1:conc#456 TYPE CONCATENATE PAR 0-2847 XREFS 21115 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.48787909999999995} PREDS {{146 0 0-2871 {}} {259 0 0-2936 {}}} SUCCS {{259 0 0-2938 {}}} CYCLES {}}
+set a(0-2938) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#140 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21116 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.3704210520708272 1 0.5151249770708272} PREDS {{146 0 0-2871 {}} {258 0 0-2935 {}} {259 0 0-2937 {}}} SUCCS {{259 0 0-2939 {}}} CYCLES {}}
+set a(0-2939) {NAME ACC1:slc#12 TYPE READSLICE PAR 0-2847 XREFS 21117 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-2871 {}} {259 0 0-2938 {}}} SUCCS {{259 0 0-2940 {}} {258 0 0-2942 {}} {258 0 0-2944 {}} {258 0 0-3438 {}} {258 0 0-3449 {}}} CYCLES {}}
+set a(0-2940) {NAME ACC1-1:slc(acc.imod#2) TYPE READSLICE PAR 0-2847 XREFS 21118 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-2871 {}} {259 0 0-2939 {}}} SUCCS {{259 0 0-2941 {}}} CYCLES {}}
+set a(0-2941) {NAME ACC1:conc#458 TYPE CONCATENATE PAR 0-2847 XREFS 21119 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-2871 {}} {259 0 0-2940 {}}} SUCCS {{258 0 0-2947 {}}} CYCLES {}}
+set a(0-2942) {NAME ACC1-1:slc(acc.imod#2)#1 TYPE READSLICE PAR 0-2847 XREFS 21120 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-2871 {}} {258 0 0-2939 {}}} SUCCS {{259 0 0-2943 {}}} CYCLES {}}
+set a(0-2943) {NAME ACC1-1:not#25 TYPE NOT PAR 0-2847 XREFS 21121 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-2871 {}} {259 0 0-2942 {}}} SUCCS {{258 0 0-2946 {}}} CYCLES {}}
+set a(0-2944) {NAME ACC1-1:slc(acc.imod#2)#2 TYPE READSLICE PAR 0-2847 XREFS 21122 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-2871 {}} {258 0 0-2939 {}}} SUCCS {{259 0 0-2945 {}}} CYCLES {}}
+set a(0-2945) {NAME ACC1-1:not#26 TYPE NOT PAR 0-2847 XREFS 21123 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-2871 {}} {259 0 0-2944 {}}} SUCCS {{259 0 0-2946 {}}} CYCLES {}}
+set a(0-2946) {NAME ACC1:conc#459 TYPE CONCATENATE PAR 0-2847 XREFS 21124 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-2871 {}} {258 0 0-2943 {}} {259 0 0-2945 {}}} SUCCS {{259 0 0-2947 {}}} CYCLES {}}
+set a(0-2947) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#141 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21125 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3976669770708272 1 0.5423709020708272} PREDS {{146 0 0-2871 {}} {258 0 0-2941 {}} {259 0 0-2946 {}}} SUCCS {{259 0 0-2948 {}}} CYCLES {}}
+set a(0-2948) {NAME ACC1:slc#13 TYPE READSLICE PAR 0-2847 XREFS 21126 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-2947 {}}} SUCCS {{258 0 0-3426 {}} {258 0 0-3527 {}} {258 0 0-3529 {}}} CYCLES {}}
+set a(0-2949) {NAME regs.regs:slc(regs.regs(0))#3 TYPE READSLICE PAR 0-2847 XREFS 21127 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.25126634999999997} PREDS {{146 0 0-2871 {}} {258 0 0-2872 {}}} SUCCS {{259 0 0-2950 {}}} CYCLES {}}
+set a(0-2950) {NAME ACC1:not#158 TYPE NOT PAR 0-2847 XREFS 21128 LOC {1 0.0 1 0.063759975 1 0.063759975 1 0.25126634999999997} PREDS {{146 0 0-2871 {}} {259 0 0-2949 {}}} SUCCS {{258 0 0-2953 {}}} CYCLES {}}
+set a(0-2951) {NAME regs.regs:slc(regs.regs(0))#4 TYPE READSLICE PAR 0-2847 XREFS 21129 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.25126634999999997} PREDS {{146 0 0-2871 {}} {258 0 0-2872 {}}} SUCCS {{259 0 0-2952 {}}} CYCLES {}}
+set a(0-2952) {NAME ACC1:not#159 TYPE NOT PAR 0-2847 XREFS 21130 LOC {1 0.0 1 0.063759975 1 0.063759975 1 0.25126634999999997} PREDS {{146 0 0-2871 {}} {259 0 0-2951 {}}} SUCCS {{259 0 0-2953 {}}} CYCLES {}}
+set a(0-2953) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#143 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 21131 LOC {1 0.0 1 0.063759975 1 0.063759975 1 0.1349440783364113 1 0.3224504533364113} PREDS {{146 0 0-2871 {}} {258 0 0-2950 {}} {259 0 0-2952 {}}} SUCCS {{258 0 0-2957 {}}} CYCLES {}}
+set a(0-2954) {NAME regs.regs:slc(regs.regs(0))#5 TYPE READSLICE PAR 0-2847 XREFS 21132 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.25126634999999997} PREDS {{146 0 0-2871 {}} {258 0 0-2872 {}}} SUCCS {{259 0 0-2955 {}}} CYCLES {}}
+set a(0-2955) {NAME ACC1:not#160 TYPE NOT PAR 0-2847 XREFS 21133 LOC {1 0.0 1 0.063759975 1 0.063759975 1 0.25126634999999997} PREDS {{146 0 0-2871 {}} {259 0 0-2954 {}}} SUCCS {{259 0 0-2956 {}}} CYCLES {}}
+set a(0-2956) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#142 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 21134 LOC {1 0.0 1 0.063759975 1 0.063759975 1 0.1349440783364113 1 0.3224504533364113} PREDS {{146 0 0-2871 {}} {259 0 0-2955 {}}} SUCCS {{259 0 0-2957 {}}} CYCLES {}}
+set a(0-2957) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME ACC1-1:acc#125 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-2847 XREFS 21135 LOC {1 0.07118415 1 0.134944125 1 0.134944125 1 0.21031488137342835 1 0.39782125637342836} PREDS {{146 0 0-2871 {}} {258 0 0-2953 {}} {259 0 0-2956 {}}} SUCCS {{259 0 0-2958 {}} {258 0 0-2961 {}} {258 0 0-2963 {}} {258 0 0-2965 {}} {258 0 0-2970 {}} {258 0 0-2976 {}} {258 0 0-2978 {}} {258 0 0-2980 {}} {258 0 0-2985 {}} {258 0 0-2987 {}} {258 0 0-2991 {}} {258 0 0-3932 {}}} CYCLES {}}
+set a(0-2958) {NAME ACC1-1:slc(acc#5.psp)#39 TYPE READSLICE PAR 0-2847 XREFS 21136 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.43860435} PREDS {{146 0 0-2871 {}} {259 0 0-2957 {}}} SUCCS {{259 0 0-2959 {}}} CYCLES {}}
+set a(0-2959) {NAME ACC1-1:not#115 TYPE NOT PAR 0-2847 XREFS 21137 LOC {1 0.14655495 1 0.251097975 1 0.251097975 1 0.43860435} PREDS {{146 0 0-2871 {}} {259 0 0-2958 {}}} SUCCS {{259 0 0-2960 {}}} CYCLES {}}
+set a(0-2960) {NAME ACC1:conc#467 TYPE CONCATENATE PAR 0-2847 XREFS 21138 LOC {1 0.14655495 1 0.251097975 1 0.251097975 1 0.43860435} PREDS {{146 0 0-2871 {}} {259 0 0-2959 {}}} SUCCS {{258 0 0-2973 {}}} CYCLES {}}
+set a(0-2961) {NAME ACC1-1:slc(acc#5.psp)#40 TYPE READSLICE PAR 0-2847 XREFS 21139 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-2871 {}} {258 0 0-2957 {}}} SUCCS {{259 0 0-2962 {}}} CYCLES {}}
+set a(0-2962) {NAME ACC1:conc#463 TYPE CONCATENATE PAR 0-2847 XREFS 21140 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-2871 {}} {259 0 0-2961 {}}} SUCCS {{258 0 0-2968 {}}} CYCLES {}}
+set a(0-2963) {NAME ACC1-1:slc(acc#5.psp)#41 TYPE READSLICE PAR 0-2847 XREFS 21141 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-2871 {}} {258 0 0-2957 {}}} SUCCS {{259 0 0-2964 {}}} CYCLES {}}
+set a(0-2964) {NAME ACC1-1:not#116 TYPE NOT PAR 0-2847 XREFS 21142 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-2871 {}} {259 0 0-2963 {}}} SUCCS {{258 0 0-2967 {}}} CYCLES {}}
+set a(0-2965) {NAME ACC1-1:slc(acc#5.psp)#45 TYPE READSLICE PAR 0-2847 XREFS 21143 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-2871 {}} {258 0 0-2957 {}}} SUCCS {{259 0 0-2966 {}}} CYCLES {}}
+set a(0-2966) {NAME ACC1-1:not#118 TYPE NOT PAR 0-2847 XREFS 21144 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-2871 {}} {259 0 0-2965 {}}} SUCCS {{259 0 0-2967 {}}} CYCLES {}}
+set a(0-2967) {NAME ACC1:conc#464 TYPE CONCATENATE PAR 0-2847 XREFS 21145 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-2871 {}} {258 0 0-2964 {}} {259 0 0-2966 {}}} SUCCS {{259 0 0-2968 {}}} CYCLES {}}
+set a(0-2968) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#145 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21146 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.2510979350894752 1 0.4386043100894752} PREDS {{146 0 0-2871 {}} {258 0 0-2962 {}} {259 0 0-2967 {}}} SUCCS {{259 0 0-2969 {}}} CYCLES {}}
+set a(0-2969) {NAME ACC1:slc#15 TYPE READSLICE PAR 0-2847 XREFS 21147 LOC {1 0.187338 1 0.251097975 1 0.251097975 1 0.43860435} PREDS {{146 0 0-2871 {}} {259 0 0-2968 {}}} SUCCS {{258 0 0-2972 {}}} CYCLES {}}
+set a(0-2970) {NAME ACC1-1:slc(acc#5.psp)#47 TYPE READSLICE PAR 0-2847 XREFS 21148 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.43860435} PREDS {{146 0 0-2871 {}} {258 0 0-2957 {}}} SUCCS {{259 0 0-2971 {}}} CYCLES {}}
+set a(0-2971) {NAME ACC1-1:not#119 TYPE NOT PAR 0-2847 XREFS 21149 LOC {1 0.14655495 1 0.251097975 1 0.251097975 1 0.43860435} PREDS {{146 0 0-2871 {}} {259 0 0-2970 {}}} SUCCS {{259 0 0-2972 {}}} CYCLES {}}
+set a(0-2972) {NAME ACC1:conc#468 TYPE CONCATENATE PAR 0-2847 XREFS 21150 LOC {1 0.187338 1 0.251097975 1 0.251097975 1 0.43860435} PREDS {{146 0 0-2871 {}} {258 0 0-2969 {}} {259 0 0-2971 {}}} SUCCS {{259 0 0-2973 {}}} CYCLES {}}
+set a(0-2973) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#147 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-2847 XREFS 21151 LOC {1 0.187338 1 0.251097975 1 0.251097975 1 0.2841347451789505 1 0.4716411201789505} PREDS {{146 0 0-2871 {}} {258 0 0-2960 {}} {259 0 0-2972 {}}} SUCCS {{259 0 0-2974 {}}} CYCLES {}}
+set a(0-2974) {NAME ACC1:slc#17 TYPE READSLICE PAR 0-2847 XREFS 21152 LOC {1 0.220374825 1 0.28413479999999997 1 0.28413479999999997 1 0.47164117499999997} PREDS {{146 0 0-2871 {}} {259 0 0-2973 {}}} SUCCS {{259 0 0-2975 {}}} CYCLES {}}
+set a(0-2975) {NAME ACC1:conc#469 TYPE CONCATENATE PAR 0-2847 XREFS 21153 LOC {1 0.220374825 1 0.28413479999999997 1 0.28413479999999997 1 0.47164117499999997} PREDS {{146 0 0-2871 {}} {259 0 0-2974 {}}} SUCCS {{258 0 0-2993 {}}} CYCLES {}}
+set a(0-2976) {NAME ACC1-1:slc(acc#5.psp)#42 TYPE READSLICE PAR 0-2847 XREFS 21154 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.4036122} PREDS {{146 0 0-2871 {}} {258 0 0-2957 {}}} SUCCS {{259 0 0-2977 {}}} CYCLES {}}
+set a(0-2977) {NAME ACC1:conc#461 TYPE CONCATENATE PAR 0-2847 XREFS 21155 LOC {1 0.14655495 1 0.216105825 1 0.216105825 1 0.4036122} PREDS {{146 0 0-2871 {}} {259 0 0-2976 {}}} SUCCS {{258 0 0-2982 {}}} CYCLES {}}
+set a(0-2978) {NAME ACC1-1:slc(acc#5.psp)#43 TYPE READSLICE PAR 0-2847 XREFS 21156 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.4036122} PREDS {{146 0 0-2871 {}} {258 0 0-2957 {}}} SUCCS {{259 0 0-2979 {}}} CYCLES {}}
+set a(0-2979) {NAME ACC1-1:not#117 TYPE NOT PAR 0-2847 XREFS 21157 LOC {1 0.14655495 1 0.216105825 1 0.216105825 1 0.4036122} PREDS {{146 0 0-2871 {}} {259 0 0-2978 {}}} SUCCS {{258 0 0-2981 {}}} CYCLES {}}
+set a(0-2980) {NAME ACC1-1:slc(acc#5.psp)#44 TYPE READSLICE PAR 0-2847 XREFS 21158 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.4036122} PREDS {{146 0 0-2871 {}} {258 0 0-2957 {}}} SUCCS {{259 0 0-2981 {}}} CYCLES {}}
+set a(0-2981) {NAME ACC1:conc#462 TYPE CONCATENATE PAR 0-2847 XREFS 21159 LOC {1 0.14655495 1 0.216105825 1 0.216105825 1 0.4036122} PREDS {{146 0 0-2871 {}} {258 0 0-2979 {}} {259 0 0-2980 {}}} SUCCS {{259 0 0-2982 {}}} CYCLES {}}
+set a(0-2982) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#144 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21160 LOC {1 0.14655495 1 0.216105825 1 0.216105825 1 0.25688883508947524 1 0.44439521008947525} PREDS {{146 0 0-2871 {}} {258 0 0-2977 {}} {259 0 0-2981 {}}} SUCCS {{259 0 0-2983 {}}} CYCLES {}}
+set a(0-2983) {NAME ACC1:slc#14 TYPE READSLICE PAR 0-2847 XREFS 21161 LOC {1 0.187338 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-2871 {}} {259 0 0-2982 {}}} SUCCS {{259 0 0-2984 {}}} CYCLES {}}
+set a(0-2984) {NAME ACC1:conc#465 TYPE CONCATENATE PAR 0-2847 XREFS 21162 LOC {1 0.187338 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-2871 {}} {259 0 0-2983 {}}} SUCCS {{258 0 0-2989 {}}} CYCLES {}}
+set a(0-2985) {NAME ACC1-1:slc(acc#5.psp)#49 TYPE READSLICE PAR 0-2847 XREFS 21163 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.44439524999999996} PREDS {{146 0 0-2871 {}} {258 0 0-2957 {}}} SUCCS {{259 0 0-2986 {}}} CYCLES {}}
+set a(0-2986) {NAME ACC1-1:not#120 TYPE NOT PAR 0-2847 XREFS 21164 LOC {1 0.14655495 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-2871 {}} {259 0 0-2985 {}}} SUCCS {{258 0 0-2988 {}}} CYCLES {}}
+set a(0-2987) {NAME ACC1-1:slc(acc#5.psp)#46 TYPE READSLICE PAR 0-2847 XREFS 21165 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.44439524999999996} PREDS {{146 0 0-2871 {}} {258 0 0-2957 {}}} SUCCS {{259 0 0-2988 {}}} CYCLES {}}
+set a(0-2988) {NAME ACC1:conc#466 TYPE CONCATENATE PAR 0-2847 XREFS 21166 LOC {1 0.14655495 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-2871 {}} {258 0 0-2986 {}} {259 0 0-2987 {}}} SUCCS {{259 0 0-2989 {}}} CYCLES {}}
+set a(0-2989) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#146 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21167 LOC {1 0.187338 1 0.25688887499999996 1 0.25688887499999996 1 0.28413475207082717 1 0.47164112707082717} PREDS {{146 0 0-2871 {}} {258 0 0-2984 {}} {259 0 0-2988 {}}} SUCCS {{259 0 0-2990 {}}} CYCLES {}}
+set a(0-2990) {NAME ACC1:slc#16 TYPE READSLICE PAR 0-2847 XREFS 21168 LOC {1 0.21458392499999998 1 0.28413479999999997 1 0.28413479999999997 1 0.47164117499999997} PREDS {{146 0 0-2871 {}} {259 0 0-2989 {}}} SUCCS {{258 0 0-2992 {}}} CYCLES {}}
+set a(0-2991) {NAME ACC1-1:slc(acc#5.psp)#48 TYPE READSLICE PAR 0-2847 XREFS 21169 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.47164117499999997} PREDS {{146 0 0-2871 {}} {258 0 0-2957 {}}} SUCCS {{259 0 0-2992 {}}} CYCLES {}}
+set a(0-2992) {NAME ACC1:conc#470 TYPE CONCATENATE PAR 0-2847 XREFS 21170 LOC {1 0.21458392499999998 1 0.28413479999999997 1 0.28413479999999997 1 0.47164117499999997} PREDS {{146 0 0-2871 {}} {258 0 0-2990 {}} {259 0 0-2991 {}}} SUCCS {{259 0 0-2993 {}}} CYCLES {}}
+set a(0-2993) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#148 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 21171 LOC {1 0.220374825 1 0.28413479999999997 1 0.28413479999999997 1 0.32242425949693604 1 0.509930634496936} PREDS {{146 0 0-2871 {}} {258 0 0-2975 {}} {259 0 0-2992 {}}} SUCCS {{259 0 0-2994 {}}} CYCLES {}}
+set a(0-2994) {NAME ACC1:slc#18 TYPE READSLICE PAR 0-2847 XREFS 21172 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-2871 {}} {259 0 0-2993 {}}} SUCCS {{259 0 0-2995 {}} {258 0 0-2997 {}} {258 0 0-2999 {}} {258 0 0-3003 {}} {258 0 0-3933 {}}} CYCLES {}}
+set a(0-2995) {NAME ACC1-1:slc(ACC1:acc#110.psp) TYPE READSLICE PAR 0-2847 XREFS 21173 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-2871 {}} {259 0 0-2994 {}}} SUCCS {{259 0 0-2996 {}}} CYCLES {}}
+set a(0-2996) {NAME ACC1:conc#471 TYPE CONCATENATE PAR 0-2847 XREFS 21174 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-2871 {}} {259 0 0-2995 {}}} SUCCS {{258 0 0-3001 {}}} CYCLES {}}
+set a(0-2997) {NAME ACC1-1:slc(ACC1:acc#110.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21175 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-2871 {}} {258 0 0-2994 {}}} SUCCS {{259 0 0-2998 {}}} CYCLES {}}
+set a(0-2998) {NAME ACC1-1:not#137 TYPE NOT PAR 0-2847 XREFS 21176 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-2871 {}} {259 0 0-2997 {}}} SUCCS {{258 0 0-3000 {}}} CYCLES {}}
+set a(0-2999) {NAME ACC1-1:slc(ACC1:acc#110.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21177 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-2871 {}} {258 0 0-2994 {}}} SUCCS {{259 0 0-3000 {}}} CYCLES {}}
+set a(0-3000) {NAME ACC1:conc#472 TYPE CONCATENATE PAR 0-2847 XREFS 21178 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-2871 {}} {258 0 0-2998 {}} {259 0 0-2999 {}}} SUCCS {{259 0 0-3001 {}}} CYCLES {}}
+set a(0-3001) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#149 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21179 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.36320731008947527 1 0.5507136850894753} PREDS {{146 0 0-2871 {}} {258 0 0-2996 {}} {259 0 0-3000 {}}} SUCCS {{259 0 0-3002 {}}} CYCLES {}}
+set a(0-3002) {NAME ACC1:slc#19 TYPE READSLICE PAR 0-2847 XREFS 21180 LOC {1 0.29944737499999996 1 0.36320735 1 0.36320735 1 0.5507137249999999} PREDS {{146 0 0-2871 {}} {259 0 0-3001 {}}} SUCCS {{258 0 0-3005 {}}} CYCLES {}}
+set a(0-3003) {NAME ACC1-1:slc(ACC1:acc#110.psp)#3 TYPE READSLICE PAR 0-2847 XREFS 21181 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.5507137249999999} PREDS {{146 0 0-2871 {}} {258 0 0-2994 {}}} SUCCS {{259 0 0-3004 {}}} CYCLES {}}
+set a(0-3004) {NAME ACC1-1:not#154 TYPE NOT PAR 0-2847 XREFS 21182 LOC {1 0.258664325 1 0.36320735 1 0.36320735 1 0.5507137249999999} PREDS {{146 0 0-2871 {}} {259 0 0-3003 {}}} SUCCS {{259 0 0-3005 {}}} CYCLES {}}
+set a(0-3005) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1-1:acc#118 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-2847 XREFS 21183 LOC {1 0.29944737499999996 1 0.36320735 1 0.36320735 1 0.3836801100894752 1 0.5711864850894752} PREDS {{146 0 0-2871 {}} {258 0 0-3002 {}} {259 0 0-3004 {}}} SUCCS {{259 0 0-3006 {}} {258 0 0-3009 {}} {258 0 0-3931 {}}} CYCLES {}}
+set a(0-3006) {NAME ACC1-1:slc(ACC1:acc#118.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21184 LOC {1 0.319920175 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-2871 {}} {259 0 0-3005 {}}} SUCCS {{259 0 0-3007 {}}} CYCLES {}}
+set a(0-3007) {NAME ACC1-1:not#147 TYPE NOT PAR 0-2847 XREFS 21185 LOC {1 0.319920175 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-2871 {}} {259 0 0-3006 {}}} SUCCS {{259 0 0-3008 {}}} CYCLES {}}
+set a(0-3008) {NAME ACC1:conc#473 TYPE CONCATENATE PAR 0-2847 XREFS 21186 LOC {1 0.319920175 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-2871 {}} {259 0 0-3007 {}}} SUCCS {{258 0 0-3011 {}}} CYCLES {}}
+set a(0-3009) {NAME ACC1-1:slc(ACC1:acc#118.psp) TYPE READSLICE PAR 0-2847 XREFS 21187 LOC {1 0.319920175 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-2871 {}} {258 0 0-3005 {}}} SUCCS {{259 0 0-3010 {}}} CYCLES {}}
+set a(0-3010) {NAME ACC1:conc#474 TYPE CONCATENATE PAR 0-2847 XREFS 21188 LOC {1 0.319920175 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-2871 {}} {259 0 0-3009 {}}} SUCCS {{259 0 0-3011 {}}} CYCLES {}}
+set a(0-3011) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#150 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21189 LOC {1 0.319920175 1 0.38368015 1 0.38368015 1 0.41092602707082715 1 0.5984324020708272} PREDS {{146 0 0-2871 {}} {258 0 0-3008 {}} {259 0 0-3010 {}}} SUCCS {{259 0 0-3012 {}}} CYCLES {}}
+set a(0-3012) {NAME ACC1:slc#20 TYPE READSLICE PAR 0-2847 XREFS 21190 LOC {1 0.3471661 1 0.410926075 1 0.410926075 1 0.59843245} PREDS {{146 0 0-2871 {}} {259 0 0-3011 {}}} SUCCS {{259 0 0-3013 {}} {258 0 0-3015 {}} {258 0 0-3017 {}} {258 0 0-3929 {}}} CYCLES {}}
+set a(0-3013) {NAME ACC1-1:slc(acc.imod#6) TYPE READSLICE PAR 0-2847 XREFS 21191 LOC {1 0.3471661 1 0.410926075 1 0.410926075 1 0.61762915} PREDS {{146 0 0-2871 {}} {259 0 0-3012 {}}} SUCCS {{259 0 0-3014 {}}} CYCLES {}}
+set a(0-3014) {NAME ACC1:conc#476 TYPE CONCATENATE PAR 0-2847 XREFS 21192 LOC {1 0.3471661 1 0.43012277499999996 1 0.43012277499999996 1 0.61762915} PREDS {{146 0 0-2871 {}} {259 0 0-3013 {}}} SUCCS {{258 0 0-3020 {}}} CYCLES {}}
+set a(0-3015) {NAME ACC1-1:slc(acc.imod#6)#1 TYPE READSLICE PAR 0-2847 XREFS 21193 LOC {1 0.3471661 1 0.410926075 1 0.410926075 1 0.61762915} PREDS {{146 0 0-2871 {}} {258 0 0-3012 {}}} SUCCS {{259 0 0-3016 {}}} CYCLES {}}
+set a(0-3016) {NAME ACC1-1:not#57 TYPE NOT PAR 0-2847 XREFS 21194 LOC {1 0.3471661 1 0.43012277499999996 1 0.43012277499999996 1 0.61762915} PREDS {{146 0 0-2871 {}} {259 0 0-3015 {}}} SUCCS {{258 0 0-3019 {}}} CYCLES {}}
+set a(0-3017) {NAME ACC1-1:slc(acc.imod#6)#2 TYPE READSLICE PAR 0-2847 XREFS 21195 LOC {1 0.3471661 1 0.410926075 1 0.410926075 1 0.61762915} PREDS {{146 0 0-2871 {}} {258 0 0-3012 {}}} SUCCS {{259 0 0-3018 {}}} CYCLES {}}
+set a(0-3018) {NAME ACC1-1:not#58 TYPE NOT PAR 0-2847 XREFS 21196 LOC {1 0.3471661 1 0.43012277499999996 1 0.43012277499999996 1 0.61762915} PREDS {{146 0 0-2871 {}} {259 0 0-3017 {}}} SUCCS {{259 0 0-3019 {}}} CYCLES {}}
+set a(0-3019) {NAME ACC1:conc#477 TYPE CONCATENATE PAR 0-2847 XREFS 21197 LOC {1 0.3471661 1 0.43012277499999996 1 0.43012277499999996 1 0.61762915} PREDS {{146 0 0-2871 {}} {258 0 0-3016 {}} {259 0 0-3018 {}}} SUCCS {{259 0 0-3020 {}}} CYCLES {}}
+set a(0-3020) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#151 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21198 LOC {1 0.3471661 1 0.43012277499999996 1 0.43012277499999996 1 0.4573686520708271 1 0.6448750270708271} PREDS {{146 0 0-2871 {}} {258 0 0-3014 {}} {259 0 0-3019 {}}} SUCCS {{259 0 0-3021 {}}} CYCLES {}}
+set a(0-3021) {NAME ACC1:slc#21 TYPE READSLICE PAR 0-2847 XREFS 21199 LOC {1 0.374412025 1 0.45736869999999996 1 0.45736869999999996 1 0.644875075} PREDS {{146 0 0-2871 {}} {259 0 0-3020 {}}} SUCCS {{258 0 0-3930 {}}} CYCLES {}}
+set a(0-3022) {NAME regs.regs:slc(regs.regs(0))#6 TYPE READSLICE PAR 0-2847 XREFS 21200 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-2871 {}} {258 0 0-2872 {}}} SUCCS {{259 0 0-3023 {}}} CYCLES {}}
+set a(0-3023) {NAME ACC1:not#161 TYPE NOT PAR 0-2847 XREFS 21201 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-2871 {}} {259 0 0-3022 {}}} SUCCS {{258 0 0-3026 {}}} CYCLES {}}
+set a(0-3024) {NAME regs.regs:slc(regs.regs(0))#7 TYPE READSLICE PAR 0-2847 XREFS 21202 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-2871 {}} {258 0 0-2872 {}}} SUCCS {{259 0 0-3025 {}}} CYCLES {}}
+set a(0-3025) {NAME ACC1:not#162 TYPE NOT PAR 0-2847 XREFS 21203 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-2871 {}} {259 0 0-3024 {}}} SUCCS {{259 0 0-3026 {}}} CYCLES {}}
+set a(0-3026) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#153 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 21204 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.08517242833641131 1 0.08517242833641131} PREDS {{146 0 0-2871 {}} {258 0 0-3023 {}} {259 0 0-3025 {}}} SUCCS {{258 0 0-3030 {}}} CYCLES {}}
+set a(0-3027) {NAME regs.regs:slc(regs.regs(0))#8 TYPE READSLICE PAR 0-2847 XREFS 21205 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-2871 {}} {258 0 0-2872 {}}} SUCCS {{259 0 0-3028 {}}} CYCLES {}}
+set a(0-3028) {NAME ACC1:not#163 TYPE NOT PAR 0-2847 XREFS 21206 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-2871 {}} {259 0 0-3027 {}}} SUCCS {{259 0 0-3029 {}}} CYCLES {}}
+set a(0-3029) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#152 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 21207 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.08517242833641131 1 0.08517242833641131} PREDS {{146 0 0-2871 {}} {259 0 0-3028 {}}} SUCCS {{259 0 0-3030 {}}} CYCLES {}}
+set a(0-3030) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME ACC1-1:acc#10 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-2847 XREFS 21208 LOC {1 0.07118415 1 0.085172475 1 0.085172475 1 0.16054323137342835 1 0.16054323137342835} PREDS {{146 0 0-2871 {}} {258 0 0-3026 {}} {259 0 0-3029 {}}} SUCCS {{259 0 0-3031 {}} {258 0 0-3034 {}} {258 0 0-3036 {}} {258 0 0-3041 {}} {258 0 0-3043 {}} {258 0 0-3047 {}} {258 0 0-3049 {}} {258 0 0-3051 {}} {258 0 0-3057 {}} {258 0 0-3059 {}} {258 0 0-3061 {}} {258 0 0-3065 {}} {258 0 0-3701 {}} {258 0 0-3702 {}} {258 0 0-3703 {}} {258 0 0-3704 {}} {258 0 0-3705 {}} {258 0 0-3707 {}} {258 0 0-3708 {}} {258 0 0-3709 {}} {258 0 0-3710 {}} {258 0 0-3713 {}} {258 0 0-3714 {}} {258 0 0-3715 {}} {258 0 0-3718 {}} {258 0 0-3721 {}} {258 0 0-3724 {}} {258 0 0-3730 {}} {258 0 0-3733 {}} {258 0 0-3741 {}} {258 0 0-3744 {}} {258 0 0-3750 {}} {258 0 0-3753 {}} {258 0 0-3764 {}} {258 0 0-3768 {}} {258 0 0-3774 {}} {258 0 0-3775 {}} {258 0 0-3779 {}} {258 0 0-3786 {}} {258 0 0-3787 {}} {258 0 0-3788 {}} {258 0 0-3791 {}} {258 0 0-3793 {}} {258 0 0-3798 {}} {258 0 0-3799 {}} {258 0 0-3800 {}} {258 0 0-3801 {}} {258 0 0-3804 {}} {258 0 0-3805 {}} {258 0 0-3809 {}} {258 0 0-3810 {}} {258 0 0-3811 {}} {258 0 0-3813 {}} {258 0 0-3815 {}} {258 0 0-3818 {}} {258 0 0-3821 {}} {258 0 0-3823 {}} {258 0 0-3836 {}} {258 0 0-3837 {}} {258 0 0-3839 {}} {258 0 0-3840 {}} {258 0 0-3841 {}} {258 0 0-3842 {}} {258 0 0-3843 {}}} CYCLES {}}
+set a(0-3031) {NAME ACC1-1:slc(acc#10.psp)#11 TYPE READSLICE PAR 0-2847 XREFS 21209 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.18521775} PREDS {{146 0 0-2871 {}} {259 0 0-3030 {}}} SUCCS {{259 0 0-3032 {}}} CYCLES {}}
+set a(0-3032) {NAME ACC1-1:not#152 TYPE NOT PAR 0-2847 XREFS 21210 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.18521775} PREDS {{146 0 0-2871 {}} {259 0 0-3031 {}}} SUCCS {{259 0 0-3033 {}}} CYCLES {}}
+set a(0-3033) {NAME ACC1:conc#483 TYPE CONCATENATE PAR 0-2847 XREFS 21211 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.18521775} PREDS {{146 0 0-2871 {}} {259 0 0-3032 {}}} SUCCS {{258 0 0-3038 {}}} CYCLES {}}
+set a(0-3034) {NAME ACC1-1:slc(acc#10.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21212 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.18521775} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3035 {}}} CYCLES {}}
+set a(0-3035) {NAME ACC1-1:not#124 TYPE NOT PAR 0-2847 XREFS 21213 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.18521775} PREDS {{146 0 0-2871 {}} {259 0 0-3034 {}}} SUCCS {{258 0 0-3037 {}}} CYCLES {}}
+set a(0-3036) {NAME ACC1-1:slc(acc#10.psp)#8 TYPE READSLICE PAR 0-2847 XREFS 21214 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.18521775} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3037 {}}} CYCLES {}}
+set a(0-3037) {NAME ACC1:conc#484 TYPE CONCATENATE PAR 0-2847 XREFS 21215 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.18521775} PREDS {{146 0 0-2871 {}} {258 0 0-3035 {}} {259 0 0-3036 {}}} SUCCS {{259 0 0-3038 {}}} CYCLES {}}
+set a(0-3038) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1:acc#156 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-2847 XREFS 21216 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.20569051008947523 1 0.20569051008947523} PREDS {{146 0 0-2871 {}} {258 0 0-3033 {}} {259 0 0-3037 {}}} SUCCS {{259 0 0-3039 {}}} CYCLES {}}
+set a(0-3039) {NAME ACC1:slc#24 TYPE READSLICE PAR 0-2847 XREFS 21217 LOC {1 0.16702775 1 0.20569055 1 0.20569055 1 0.20569055} PREDS {{146 0 0-2871 {}} {259 0 0-3038 {}}} SUCCS {{259 0 0-3040 {}}} CYCLES {}}
+set a(0-3040) {NAME ACC1:conc#487 TYPE CONCATENATE PAR 0-2847 XREFS 21218 LOC {1 0.16702775 1 0.20569055 1 0.20569055 1 0.20569055} PREDS {{146 0 0-2871 {}} {259 0 0-3039 {}}} SUCCS {{258 0 0-3045 {}}} CYCLES {}}
+set a(0-3041) {NAME ACC1-1:slc(acc#10.psp) TYPE READSLICE PAR 0-2847 XREFS 21219 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.20569055} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3042 {}}} CYCLES {}}
+set a(0-3042) {NAME ACC1:conc#478 TYPE CONCATENATE PAR 0-2847 XREFS 21220 LOC {1 0.14655495 1 0.20569055 1 0.20569055 1 0.20569055} PREDS {{146 0 0-2871 {}} {259 0 0-3041 {}}} SUCCS {{258 0 0-3044 {}}} CYCLES {}}
+set a(0-3043) {NAME ACC1-1:slc(acc#10.psp)#10 TYPE READSLICE PAR 0-2847 XREFS 21221 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.20569055} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3044 {}}} CYCLES {}}
+set a(0-3044) {NAME ACC1:conc#488 TYPE CONCATENATE PAR 0-2847 XREFS 21222 LOC {1 0.14655495 1 0.20569055 1 0.20569055 1 0.20569055} PREDS {{146 0 0-2871 {}} {258 0 0-3042 {}} {259 0 0-3043 {}}} SUCCS {{259 0 0-3045 {}}} CYCLES {}}
+set a(0-3045) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#158 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 21223 LOC {1 0.16702775 1 0.20569055 1 0.20569055 1 0.24888244517895047 1 0.24888244517895047} PREDS {{146 0 0-2871 {}} {258 0 0-3040 {}} {259 0 0-3044 {}}} SUCCS {{259 0 0-3046 {}}} CYCLES {}}
+set a(0-3046) {NAME ACC1:slc#26 TYPE READSLICE PAR 0-2847 XREFS 21224 LOC {1 0.21021969999999998 1 0.24888249999999998 1 0.24888249999999998 1 0.24888249999999998} PREDS {{146 0 0-2871 {}} {259 0 0-3045 {}}} SUCCS {{258 0 0-3070 {}}} CYCLES {}}
+set a(0-3047) {NAME ACC1-1:slc(acc#10.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21225 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3048 {}}} CYCLES {}}
+set a(0-3048) {NAME ACC1:conc#481 TYPE CONCATENATE PAR 0-2847 XREFS 21226 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3047 {}}} SUCCS {{258 0 0-3054 {}}} CYCLES {}}
+set a(0-3049) {NAME ACC1-1:slc(acc#10.psp)#3 TYPE READSLICE PAR 0-2847 XREFS 21227 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3050 {}}} CYCLES {}}
+set a(0-3050) {NAME ACC1-1:not#125 TYPE NOT PAR 0-2847 XREFS 21228 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3049 {}}} SUCCS {{258 0 0-3053 {}}} CYCLES {}}
+set a(0-3051) {NAME ACC1-1:slc(acc#10.psp)#7 TYPE READSLICE PAR 0-2847 XREFS 21229 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3052 {}}} CYCLES {}}
+set a(0-3052) {NAME ACC1-1:not#127 TYPE NOT PAR 0-2847 XREFS 21230 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3051 {}}} SUCCS {{259 0 0-3053 {}}} CYCLES {}}
+set a(0-3053) {NAME ACC1:conc#482 TYPE CONCATENATE PAR 0-2847 XREFS 21231 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3050 {}} {259 0 0-3052 {}}} SUCCS {{259 0 0-3054 {}}} CYCLES {}}
+set a(0-3054) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#155 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21232 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.20132628508947523 1 0.20132628508947523} PREDS {{146 0 0-2871 {}} {258 0 0-3048 {}} {259 0 0-3053 {}}} SUCCS {{259 0 0-3055 {}}} CYCLES {}}
+set a(0-3055) {NAME ACC1:slc#23 TYPE READSLICE PAR 0-2847 XREFS 21233 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.201326325} PREDS {{146 0 0-2871 {}} {259 0 0-3054 {}}} SUCCS {{259 0 0-3056 {}}} CYCLES {}}
+set a(0-3056) {NAME ACC1:conc#485 TYPE CONCATENATE PAR 0-2847 XREFS 21234 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.201326325} PREDS {{146 0 0-2871 {}} {259 0 0-3055 {}}} SUCCS {{258 0 0-3068 {}}} CYCLES {}}
+set a(0-3057) {NAME ACC1-1:slc(acc#10.psp)#4 TYPE READSLICE PAR 0-2847 XREFS 21235 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3058 {}}} CYCLES {}}
+set a(0-3058) {NAME ACC1:conc#479 TYPE CONCATENATE PAR 0-2847 XREFS 21236 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3057 {}}} SUCCS {{258 0 0-3063 {}}} CYCLES {}}
+set a(0-3059) {NAME ACC1-1:slc(acc#10.psp)#5 TYPE READSLICE PAR 0-2847 XREFS 21237 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3060 {}}} CYCLES {}}
+set a(0-3060) {NAME ACC1-1:not#126 TYPE NOT PAR 0-2847 XREFS 21238 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3059 {}}} SUCCS {{258 0 0-3062 {}}} CYCLES {}}
+set a(0-3061) {NAME ACC1-1:slc(acc#10.psp)#6 TYPE READSLICE PAR 0-2847 XREFS 21239 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3062 {}}} CYCLES {}}
+set a(0-3062) {NAME ACC1:conc#480 TYPE CONCATENATE PAR 0-2847 XREFS 21240 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3060 {}} {259 0 0-3061 {}}} SUCCS {{259 0 0-3063 {}}} CYCLES {}}
+set a(0-3063) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#154 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21241 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.20132628508947523 1 0.20132628508947523} PREDS {{146 0 0-2871 {}} {258 0 0-3058 {}} {259 0 0-3062 {}}} SUCCS {{259 0 0-3064 {}}} CYCLES {}}
+set a(0-3064) {NAME ACC1:slc#22 TYPE READSLICE PAR 0-2847 XREFS 21242 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.201326325} PREDS {{146 0 0-2871 {}} {259 0 0-3063 {}}} SUCCS {{258 0 0-3067 {}}} CYCLES {}}
+set a(0-3065) {NAME ACC1-1:slc(acc#10.psp)#9 TYPE READSLICE PAR 0-2847 XREFS 21243 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.201326325} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3066 {}}} CYCLES {}}
+set a(0-3066) {NAME ACC1-1:not#128 TYPE NOT PAR 0-2847 XREFS 21244 LOC {1 0.14655495 1 0.201326325 1 0.201326325 1 0.201326325} PREDS {{146 0 0-2871 {}} {259 0 0-3065 {}}} SUCCS {{259 0 0-3067 {}}} CYCLES {}}
+set a(0-3067) {NAME ACC1:conc#486 TYPE CONCATENATE PAR 0-2847 XREFS 21245 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.201326325} PREDS {{146 0 0-2871 {}} {258 0 0-3064 {}} {259 0 0-3066 {}}} SUCCS {{259 0 0-3068 {}}} CYCLES {}}
+set a(0-3068) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#157 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21246 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.24888245207082718 1 0.24888245207082718} PREDS {{146 0 0-2871 {}} {258 0 0-3056 {}} {259 0 0-3067 {}}} SUCCS {{259 0 0-3069 {}}} CYCLES {}}
+set a(0-3069) {NAME ACC1:slc#25 TYPE READSLICE PAR 0-2847 XREFS 21247 LOC {1 0.23489417499999998 1 0.24888249999999998 1 0.24888249999999998 1 0.24888249999999998} PREDS {{146 0 0-2871 {}} {259 0 0-3068 {}}} SUCCS {{259 0 0-3070 {}}} CYCLES {}}
+set a(0-3070) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1-1:acc#113 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-2847 XREFS 21248 LOC {1 0.23489417499999998 1 0.24888249999999998 1 0.24888249999999998 1 0.28191927017895047 1 0.28191927017895047} PREDS {{146 0 0-2871 {}} {258 0 0-3046 {}} {259 0 0-3069 {}}} SUCCS {{259 0 0-3071 {}} {258 0 0-3073 {}} {258 0 0-3075 {}} {258 0 0-3079 {}} {258 0 0-3755 {}} {258 0 0-3767 {}} {258 0 0-3778 {}} {258 0 0-3781 {}}} CYCLES {}}
+set a(0-3071) {NAME ACC1-1:slc(ACC1:acc#113.psp) TYPE READSLICE PAR 0-2847 XREFS 21249 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.281919325} PREDS {{146 0 0-2871 {}} {259 0 0-3070 {}}} SUCCS {{259 0 0-3072 {}}} CYCLES {}}
+set a(0-3072) {NAME ACC1:conc#489 TYPE CONCATENATE PAR 0-2847 XREFS 21250 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.281919325} PREDS {{146 0 0-2871 {}} {259 0 0-3071 {}}} SUCCS {{258 0 0-3077 {}}} CYCLES {}}
+set a(0-3073) {NAME ACC1-1:slc(ACC1:acc#113.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21251 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.281919325} PREDS {{146 0 0-2871 {}} {258 0 0-3070 {}}} SUCCS {{259 0 0-3074 {}}} CYCLES {}}
+set a(0-3074) {NAME ACC1-1:not#141 TYPE NOT PAR 0-2847 XREFS 21252 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.281919325} PREDS {{146 0 0-2871 {}} {259 0 0-3073 {}}} SUCCS {{258 0 0-3076 {}}} CYCLES {}}
+set a(0-3075) {NAME ACC1-1:slc(ACC1:acc#113.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21253 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.281919325} PREDS {{146 0 0-2871 {}} {258 0 0-3070 {}}} SUCCS {{259 0 0-3076 {}}} CYCLES {}}
+set a(0-3076) {NAME ACC1:conc#490 TYPE CONCATENATE PAR 0-2847 XREFS 21254 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.281919325} PREDS {{146 0 0-2871 {}} {258 0 0-3074 {}} {259 0 0-3075 {}}} SUCCS {{259 0 0-3077 {}}} CYCLES {}}
+set a(0-3077) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#159 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21255 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.3227023350894752 1 0.3227023350894752} PREDS {{146 0 0-2871 {}} {258 0 0-3072 {}} {259 0 0-3076 {}}} SUCCS {{259 0 0-3078 {}}} CYCLES {}}
+set a(0-3078) {NAME ACC1:slc#27 TYPE READSLICE PAR 0-2847 XREFS 21256 LOC {1 0.30871404999999996 1 0.322702375 1 0.322702375 1 0.322702375} PREDS {{146 0 0-2871 {}} {259 0 0-3077 {}}} SUCCS {{258 0 0-3081 {}}} CYCLES {}}
+set a(0-3079) {NAME ACC1-1:slc(ACC1:acc#113.psp)#3 TYPE READSLICE PAR 0-2847 XREFS 21257 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.322702375} PREDS {{146 0 0-2871 {}} {258 0 0-3070 {}}} SUCCS {{259 0 0-3080 {}}} CYCLES {}}
+set a(0-3080) {NAME ACC1-1:not#155 TYPE NOT PAR 0-2847 XREFS 21258 LOC {1 0.267931 1 0.322702375 1 0.322702375 1 0.322702375} PREDS {{146 0 0-2871 {}} {259 0 0-3079 {}}} SUCCS {{259 0 0-3081 {}}} CYCLES {}}
+set a(0-3081) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1-1:acc#120 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-2847 XREFS 21259 LOC {1 0.30871404999999996 1 0.322702375 1 0.322702375 1 0.3431751350894752 1 0.3431751350894752} PREDS {{146 0 0-2871 {}} {258 0 0-3078 {}} {259 0 0-3080 {}}} SUCCS {{259 0 0-3082 {}} {258 0 0-3085 {}} {258 0 0-3772 {}}} CYCLES {}}
+set a(0-3082) {NAME ACC1-1:slc(ACC1:acc#120.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21260 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.343175175} PREDS {{146 0 0-2871 {}} {259 0 0-3081 {}}} SUCCS {{259 0 0-3083 {}}} CYCLES {}}
+set a(0-3083) {NAME ACC1-1:not#149 TYPE NOT PAR 0-2847 XREFS 21261 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.343175175} PREDS {{146 0 0-2871 {}} {259 0 0-3082 {}}} SUCCS {{259 0 0-3084 {}}} CYCLES {}}
+set a(0-3084) {NAME ACC1:conc#491 TYPE CONCATENATE PAR 0-2847 XREFS 21262 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.343175175} PREDS {{146 0 0-2871 {}} {259 0 0-3083 {}}} SUCCS {{258 0 0-3087 {}}} CYCLES {}}
+set a(0-3085) {NAME ACC1-1:slc(ACC1:acc#120.psp) TYPE READSLICE PAR 0-2847 XREFS 21263 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.343175175} PREDS {{146 0 0-2871 {}} {258 0 0-3081 {}}} SUCCS {{259 0 0-3086 {}}} CYCLES {}}
+set a(0-3086) {NAME ACC1:conc#492 TYPE CONCATENATE PAR 0-2847 XREFS 21264 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.343175175} PREDS {{146 0 0-2871 {}} {259 0 0-3085 {}}} SUCCS {{259 0 0-3087 {}}} CYCLES {}}
+set a(0-3087) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#160 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21265 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.3704210520708272 1 0.3704210520708272} PREDS {{146 0 0-2871 {}} {258 0 0-3084 {}} {259 0 0-3086 {}}} SUCCS {{259 0 0-3088 {}}} CYCLES {}}
+set a(0-3088) {NAME ACC1:slc#28 TYPE READSLICE PAR 0-2847 XREFS 21266 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-2871 {}} {259 0 0-3087 {}}} SUCCS {{259 0 0-3089 {}} {258 0 0-3091 {}} {258 0 0-3093 {}} {258 0 0-3735 {}} {258 0 0-3746 {}}} CYCLES {}}
+set a(0-3089) {NAME ACC1-1:slc(acc.imod#10) TYPE READSLICE PAR 0-2847 XREFS 21267 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-2871 {}} {259 0 0-3088 {}}} SUCCS {{259 0 0-3090 {}}} CYCLES {}}
+set a(0-3090) {NAME ACC1:conc#494 TYPE CONCATENATE PAR 0-2847 XREFS 21268 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-2871 {}} {259 0 0-3089 {}}} SUCCS {{258 0 0-3096 {}}} CYCLES {}}
+set a(0-3091) {NAME ACC1-1:slc(acc.imod#10)#1 TYPE READSLICE PAR 0-2847 XREFS 21269 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-2871 {}} {258 0 0-3088 {}}} SUCCS {{259 0 0-3092 {}}} CYCLES {}}
+set a(0-3092) {NAME ACC1-1:not#89 TYPE NOT PAR 0-2847 XREFS 21270 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-2871 {}} {259 0 0-3091 {}}} SUCCS {{258 0 0-3095 {}}} CYCLES {}}
+set a(0-3093) {NAME ACC1-1:slc(acc.imod#10)#2 TYPE READSLICE PAR 0-2847 XREFS 21271 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-2871 {}} {258 0 0-3088 {}}} SUCCS {{259 0 0-3094 {}}} CYCLES {}}
+set a(0-3094) {NAME ACC1-1:not#90 TYPE NOT PAR 0-2847 XREFS 21272 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-2871 {}} {259 0 0-3093 {}}} SUCCS {{259 0 0-3095 {}}} CYCLES {}}
+set a(0-3095) {NAME ACC1:conc#495 TYPE CONCATENATE PAR 0-2847 XREFS 21273 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-2871 {}} {258 0 0-3092 {}} {259 0 0-3094 {}}} SUCCS {{259 0 0-3096 {}}} CYCLES {}}
+set a(0-3096) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#161 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21274 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3976669770708272 1 0.3976669770708272} PREDS {{146 0 0-2871 {}} {258 0 0-3090 {}} {259 0 0-3095 {}}} SUCCS {{259 0 0-3097 {}}} CYCLES {}}
+set a(0-3097) {NAME ACC1:slc#29 TYPE READSLICE PAR 0-2847 XREFS 21275 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3096 {}}} SUCCS {{258 0 0-3723 {}} {258 0 0-3824 {}} {258 0 0-3826 {}}} CYCLES {}}
+set a(0-3098) {NAME regs.regs:asn TYPE ASSIGN PAR 0-2847 XREFS 21276 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.295092075} PREDS {{146 0 0-2871 {}} {262 0 0-4372 {}}} SUCCS {{259 0 0-3099 {}} {256 0 0-4372 {}}} CYCLES {}}
+set a(0-3099) {NAME regs.regs:slc(regs.regs(2))#1 TYPE READSLICE PAR 0-2847 XREFS 21277 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.295092075} PREDS {{146 0 0-2871 {}} {259 0 0-3098 {}}} SUCCS {{258 0 0-3102 {}}} CYCLES {}}
+set a(0-3100) {NAME regs.regs:asn#1 TYPE ASSIGN PAR 0-2847 XREFS 21278 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.295092075} PREDS {{146 0 0-2871 {}} {262 0 0-4372 {}}} SUCCS {{259 0 0-3101 {}} {256 0 0-4372 {}}} CYCLES {}}
+set a(0-3101) {NAME regs.regs:slc(regs.regs(2))#2 TYPE READSLICE PAR 0-2847 XREFS 21279 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.295092075} PREDS {{146 0 0-2871 {}} {259 0 0-3100 {}}} SUCCS {{259 0 0-3102 {}}} CYCLES {}}
+set a(0-3102) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#162 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 21280 LOC {1 0.0 1 0.15038815 1 0.15038815 1 0.2215722533364113 1 0.36627617833641135} PREDS {{146 0 0-2871 {}} {258 0 0-3099 {}} {259 0 0-3101 {}}} SUCCS {{258 0 0-3105 {}}} CYCLES {}}
+set a(0-3103) {NAME regs.regs:asn#2 TYPE ASSIGN PAR 0-2847 XREFS 21281 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.366276225} PREDS {{146 0 0-2871 {}} {262 0 0-4372 {}}} SUCCS {{259 0 0-3104 {}} {256 0 0-4372 {}}} CYCLES {}}
+set a(0-3104) {NAME regs.regs:slc(regs.regs(2)) TYPE READSLICE PAR 0-2847 XREFS 21282 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.366276225} PREDS {{146 0 0-2871 {}} {259 0 0-3103 {}}} SUCCS {{259 0 0-3105 {}}} CYCLES {}}
+set a(0-3105) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME ACC1-3:acc TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-2847 XREFS 21283 LOC {1 0.07118415 1 0.2215723 1 0.2215723 1 0.2969430563734284 1 0.4416469813734284} PREDS {{146 0 0-2871 {}} {258 0 0-3102 {}} {259 0 0-3104 {}}} SUCCS {{259 0 0-3106 {}} {258 0 0-3109 {}} {258 0 0-3111 {}} {258 0 0-3116 {}} {258 0 0-3118 {}} {258 0 0-3122 {}} {258 0 0-3124 {}} {258 0 0-3126 {}} {258 0 0-3132 {}} {258 0 0-3134 {}} {258 0 0-3136 {}} {258 0 0-3140 {}} {258 0 0-3320 {}} {258 0 0-3321 {}} {258 0 0-3322 {}} {258 0 0-3324 {}} {258 0 0-3328 {}} {258 0 0-3334 {}} {258 0 0-3335 {}} {258 0 0-3339 {}} {258 0 0-3346 {}} {258 0 0-3347 {}} {258 0 0-3348 {}} {258 0 0-3351 {}} {258 0 0-3353 {}} {258 0 0-3358 {}} {258 0 0-3359 {}} {258 0 0-3360 {}} {258 0 0-3361 {}} {258 0 0-3364 {}} {258 0 0-3365 {}} {258 0 0-3369 {}} {258 0 0-3370 {}} {258 0 0-3371 {}} {258 0 0-3373 {}} {258 0 0-3375 {}} {258 0 0-3378 {}} {258 0 0-3381 {}} {258 0 0-3383 {}} {258 0 0-3395 {}} {258 0 0-3396 {}} {258 0 0-3397 {}} {258 0 0-3398 {}} {258 0 0-3399 {}} {258 0 0-3551 {}} {258 0 0-3552 {}} {258 0 0-3553 {}} {258 0 0-3554 {}} {258 0 0-3555 {}} {258 0 0-3557 {}} {258 0 0-3558 {}} {258 0 0-3559 {}} {258 0 0-3560 {}} {258 0 0-3563 {}} {258 0 0-3564 {}} {258 0 0-3565 {}} {258 0 0-3568 {}} {258 0 0-3571 {}} {258 0 0-3574 {}} {258 0 0-3580 {}} {258 0 0-3583 {}} {258 0 0-3591 {}} {258 0 0-3594 {}} {258 0 0-3600 {}} {258 0 0-3603 {}}} CYCLES {}}
+set a(0-3106) {NAME ACC1-3:slc(acc.psp)#11 TYPE READSLICE PAR 0-2847 XREFS 21284 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.4663215} PREDS {{146 0 0-2871 {}} {259 0 0-3105 {}}} SUCCS {{259 0 0-3107 {}}} CYCLES {}}
+set a(0-3107) {NAME ACC1-3:not#151 TYPE NOT PAR 0-2847 XREFS 21285 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.4663215} PREDS {{146 0 0-2871 {}} {259 0 0-3106 {}}} SUCCS {{259 0 0-3108 {}}} CYCLES {}}
+set a(0-3108) {NAME ACC1:conc#501 TYPE CONCATENATE PAR 0-2847 XREFS 21286 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.4663215} PREDS {{146 0 0-2871 {}} {259 0 0-3107 {}}} SUCCS {{258 0 0-3113 {}}} CYCLES {}}
+set a(0-3109) {NAME ACC1-3:slc(acc.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21287 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.4663215} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3110 {}}} CYCLES {}}
+set a(0-3110) {NAME ACC1-3:not#106 TYPE NOT PAR 0-2847 XREFS 21288 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.4663215} PREDS {{146 0 0-2871 {}} {259 0 0-3109 {}}} SUCCS {{258 0 0-3112 {}}} CYCLES {}}
+set a(0-3111) {NAME ACC1-3:slc(acc.psp)#8 TYPE READSLICE PAR 0-2847 XREFS 21289 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.4663215} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3112 {}}} CYCLES {}}
+set a(0-3112) {NAME ACC1:conc#502 TYPE CONCATENATE PAR 0-2847 XREFS 21290 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.4663215} PREDS {{146 0 0-2871 {}} {258 0 0-3110 {}} {259 0 0-3111 {}}} SUCCS {{259 0 0-3113 {}}} CYCLES {}}
+set a(0-3113) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1:acc#165 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-2847 XREFS 21291 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.34209033508947523 1 0.48679426008947524} PREDS {{146 0 0-2871 {}} {258 0 0-3108 {}} {259 0 0-3112 {}}} SUCCS {{259 0 0-3114 {}}} CYCLES {}}
+set a(0-3114) {NAME ACC1:slc#32 TYPE READSLICE PAR 0-2847 XREFS 21292 LOC {1 0.16702775 1 0.342090375 1 0.342090375 1 0.48679429999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3113 {}}} SUCCS {{259 0 0-3115 {}}} CYCLES {}}
+set a(0-3115) {NAME ACC1:conc#505 TYPE CONCATENATE PAR 0-2847 XREFS 21293 LOC {1 0.16702775 1 0.342090375 1 0.342090375 1 0.48679429999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3114 {}}} SUCCS {{258 0 0-3120 {}}} CYCLES {}}
+set a(0-3116) {NAME ACC1-3:slc(acc.psp) TYPE READSLICE PAR 0-2847 XREFS 21294 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.48679429999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3117 {}}} CYCLES {}}
+set a(0-3117) {NAME ACC1:conc#496 TYPE CONCATENATE PAR 0-2847 XREFS 21295 LOC {1 0.14655495 1 0.342090375 1 0.342090375 1 0.48679429999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3116 {}}} SUCCS {{258 0 0-3119 {}}} CYCLES {}}
+set a(0-3118) {NAME ACC1-3:slc(acc.psp)#10 TYPE READSLICE PAR 0-2847 XREFS 21296 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.48679429999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3119 {}}} CYCLES {}}
+set a(0-3119) {NAME ACC1:conc#506 TYPE CONCATENATE PAR 0-2847 XREFS 21297 LOC {1 0.14655495 1 0.342090375 1 0.342090375 1 0.48679429999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3117 {}} {259 0 0-3118 {}}} SUCCS {{259 0 0-3120 {}}} CYCLES {}}
+set a(0-3120) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#167 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 21298 LOC {1 0.16702775 1 0.342090375 1 0.342090375 1 0.3852822701789505 1 0.5299861951789504} PREDS {{146 0 0-2871 {}} {258 0 0-3115 {}} {259 0 0-3119 {}}} SUCCS {{259 0 0-3121 {}}} CYCLES {}}
+set a(0-3121) {NAME ACC1:slc#34 TYPE READSLICE PAR 0-2847 XREFS 21299 LOC {1 0.21021969999999998 1 0.385282325 1 0.385282325 1 0.52998625} PREDS {{146 0 0-2871 {}} {259 0 0-3120 {}}} SUCCS {{258 0 0-3145 {}}} CYCLES {}}
+set a(0-3122) {NAME ACC1-3:slc(acc.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21300 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3123 {}}} CYCLES {}}
+set a(0-3123) {NAME ACC1:conc#499 TYPE CONCATENATE PAR 0-2847 XREFS 21301 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-2871 {}} {259 0 0-3122 {}}} SUCCS {{258 0 0-3129 {}}} CYCLES {}}
+set a(0-3124) {NAME ACC1-3:slc(acc.psp)#3 TYPE READSLICE PAR 0-2847 XREFS 21302 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3125 {}}} CYCLES {}}
+set a(0-3125) {NAME ACC1-3:not#107 TYPE NOT PAR 0-2847 XREFS 21303 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-2871 {}} {259 0 0-3124 {}}} SUCCS {{258 0 0-3128 {}}} CYCLES {}}
+set a(0-3126) {NAME ACC1-3:slc(acc.psp)#7 TYPE READSLICE PAR 0-2847 XREFS 21304 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3127 {}}} CYCLES {}}
+set a(0-3127) {NAME ACC1-3:not#109 TYPE NOT PAR 0-2847 XREFS 21305 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-2871 {}} {259 0 0-3126 {}}} SUCCS {{259 0 0-3128 {}}} CYCLES {}}
+set a(0-3128) {NAME ACC1:conc#500 TYPE CONCATENATE PAR 0-2847 XREFS 21306 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-2871 {}} {258 0 0-3125 {}} {259 0 0-3127 {}}} SUCCS {{259 0 0-3129 {}}} CYCLES {}}
+set a(0-3129) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#164 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21307 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.3377261100894752 1 0.48243003508947524} PREDS {{146 0 0-2871 {}} {258 0 0-3123 {}} {259 0 0-3128 {}}} SUCCS {{259 0 0-3130 {}}} CYCLES {}}
+set a(0-3130) {NAME ACC1:slc#31 TYPE READSLICE PAR 0-2847 XREFS 21308 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.48243007499999996} PREDS {{146 0 0-2871 {}} {259 0 0-3129 {}}} SUCCS {{259 0 0-3131 {}}} CYCLES {}}
+set a(0-3131) {NAME ACC1:conc#503 TYPE CONCATENATE PAR 0-2847 XREFS 21309 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.48243007499999996} PREDS {{146 0 0-2871 {}} {259 0 0-3130 {}}} SUCCS {{258 0 0-3143 {}}} CYCLES {}}
+set a(0-3132) {NAME ACC1-3:slc(acc.psp)#4 TYPE READSLICE PAR 0-2847 XREFS 21310 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3133 {}}} CYCLES {}}
+set a(0-3133) {NAME ACC1:conc#497 TYPE CONCATENATE PAR 0-2847 XREFS 21311 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-2871 {}} {259 0 0-3132 {}}} SUCCS {{258 0 0-3138 {}}} CYCLES {}}
+set a(0-3134) {NAME ACC1-3:slc(acc.psp)#5 TYPE READSLICE PAR 0-2847 XREFS 21312 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3135 {}}} CYCLES {}}
+set a(0-3135) {NAME ACC1-3:not#108 TYPE NOT PAR 0-2847 XREFS 21313 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-2871 {}} {259 0 0-3134 {}}} SUCCS {{258 0 0-3137 {}}} CYCLES {}}
+set a(0-3136) {NAME ACC1-3:slc(acc.psp)#6 TYPE READSLICE PAR 0-2847 XREFS 21314 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3137 {}}} CYCLES {}}
+set a(0-3137) {NAME ACC1:conc#498 TYPE CONCATENATE PAR 0-2847 XREFS 21315 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-2871 {}} {258 0 0-3135 {}} {259 0 0-3136 {}}} SUCCS {{259 0 0-3138 {}}} CYCLES {}}
+set a(0-3138) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#163 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21316 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.3377261100894752 1 0.48243003508947524} PREDS {{146 0 0-2871 {}} {258 0 0-3133 {}} {259 0 0-3137 {}}} SUCCS {{259 0 0-3139 {}}} CYCLES {}}
+set a(0-3139) {NAME ACC1:slc#30 TYPE READSLICE PAR 0-2847 XREFS 21317 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.48243007499999996} PREDS {{146 0 0-2871 {}} {259 0 0-3138 {}}} SUCCS {{258 0 0-3142 {}}} CYCLES {}}
+set a(0-3140) {NAME ACC1-3:slc(acc.psp)#9 TYPE READSLICE PAR 0-2847 XREFS 21318 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.48243007499999996} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3141 {}}} CYCLES {}}
+set a(0-3141) {NAME ACC1-3:not#110 TYPE NOT PAR 0-2847 XREFS 21319 LOC {1 0.14655495 1 0.33772615 1 0.33772615 1 0.48243007499999996} PREDS {{146 0 0-2871 {}} {259 0 0-3140 {}}} SUCCS {{259 0 0-3142 {}}} CYCLES {}}
+set a(0-3142) {NAME ACC1:conc#504 TYPE CONCATENATE PAR 0-2847 XREFS 21320 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.48243007499999996} PREDS {{146 0 0-2871 {}} {258 0 0-3139 {}} {259 0 0-3141 {}}} SUCCS {{259 0 0-3143 {}}} CYCLES {}}
+set a(0-3143) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#166 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21321 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.3852822770708272 1 0.5299862020708271} PREDS {{146 0 0-2871 {}} {258 0 0-3131 {}} {259 0 0-3142 {}}} SUCCS {{259 0 0-3144 {}}} CYCLES {}}
+set a(0-3144) {NAME ACC1:slc#33 TYPE READSLICE PAR 0-2847 XREFS 21322 LOC {1 0.23489417499999998 1 0.385282325 1 0.385282325 1 0.52998625} PREDS {{146 0 0-2871 {}} {259 0 0-3143 {}}} SUCCS {{259 0 0-3145 {}}} CYCLES {}}
+set a(0-3145) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1-3:acc#107 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-2847 XREFS 21323 LOC {1 0.23489417499999998 1 0.385282325 1 0.385282325 1 0.4183190951789505 1 0.5630230201789505} PREDS {{146 0 0-2871 {}} {258 0 0-3121 {}} {259 0 0-3144 {}}} SUCCS {{259 0 0-3146 {}} {258 0 0-3148 {}} {258 0 0-3150 {}} {258 0 0-3154 {}} {258 0 0-3327 {}} {258 0 0-3338 {}} {258 0 0-3341 {}} {258 0 0-3605 {}}} CYCLES {}}
+set a(0-3146) {NAME ACC1-3:slc(ACC1:acc#107.psp) TYPE READSLICE PAR 0-2847 XREFS 21324 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.5630230749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3145 {}}} SUCCS {{259 0 0-3147 {}}} CYCLES {}}
+set a(0-3147) {NAME ACC1:conc#507 TYPE CONCATENATE PAR 0-2847 XREFS 21325 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.5630230749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3146 {}}} SUCCS {{258 0 0-3152 {}}} CYCLES {}}
+set a(0-3148) {NAME ACC1-3:slc(ACC1:acc#107.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21326 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.5630230749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3145 {}}} SUCCS {{259 0 0-3149 {}}} CYCLES {}}
+set a(0-3149) {NAME ACC1-3:not#133 TYPE NOT PAR 0-2847 XREFS 21327 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.5630230749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3148 {}}} SUCCS {{258 0 0-3151 {}}} CYCLES {}}
+set a(0-3150) {NAME ACC1-3:slc(ACC1:acc#107.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21328 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.5630230749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3145 {}}} SUCCS {{259 0 0-3151 {}}} CYCLES {}}
+set a(0-3151) {NAME ACC1:conc#508 TYPE CONCATENATE PAR 0-2847 XREFS 21329 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.5630230749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3149 {}} {259 0 0-3150 {}}} SUCCS {{259 0 0-3152 {}}} CYCLES {}}
+set a(0-3152) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#168 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21330 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.45910216008947524 1 0.6038060850894752} PREDS {{146 0 0-2871 {}} {258 0 0-3147 {}} {259 0 0-3151 {}}} SUCCS {{259 0 0-3153 {}}} CYCLES {}}
+set a(0-3153) {NAME ACC1:slc#35 TYPE READSLICE PAR 0-2847 XREFS 21331 LOC {1 0.30871404999999996 1 0.45910219999999996 1 0.45910219999999996 1 0.603806125} PREDS {{146 0 0-2871 {}} {259 0 0-3152 {}}} SUCCS {{258 0 0-3156 {}}} CYCLES {}}
+set a(0-3154) {NAME ACC1-3:slc(ACC1:acc#107.psp)#3 TYPE READSLICE PAR 0-2847 XREFS 21332 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.603806125} PREDS {{146 0 0-2871 {}} {258 0 0-3145 {}}} SUCCS {{259 0 0-3155 {}}} CYCLES {}}
+set a(0-3155) {NAME ACC1-3:not#153 TYPE NOT PAR 0-2847 XREFS 21333 LOC {1 0.267931 1 0.45910219999999996 1 0.45910219999999996 1 0.603806125} PREDS {{146 0 0-2871 {}} {259 0 0-3154 {}}} SUCCS {{259 0 0-3156 {}}} CYCLES {}}
+set a(0-3156) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1-3:acc#116 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-2847 XREFS 21334 LOC {1 0.30871404999999996 1 0.45910219999999996 1 0.45910219999999996 1 0.4795749600894752 1 0.6242788850894753} PREDS {{146 0 0-2871 {}} {258 0 0-3153 {}} {259 0 0-3155 {}}} SUCCS {{259 0 0-3157 {}} {258 0 0-3160 {}} {258 0 0-3332 {}}} CYCLES {}}
+set a(0-3157) {NAME ACC1-3:slc(ACC1:acc#116.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21335 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.6242789249999999} PREDS {{146 0 0-2871 {}} {259 0 0-3156 {}}} SUCCS {{259 0 0-3158 {}}} CYCLES {}}
+set a(0-3158) {NAME ACC1-3:not#145 TYPE NOT PAR 0-2847 XREFS 21336 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.6242789249999999} PREDS {{146 0 0-2871 {}} {259 0 0-3157 {}}} SUCCS {{259 0 0-3159 {}}} CYCLES {}}
+set a(0-3159) {NAME ACC1:conc#509 TYPE CONCATENATE PAR 0-2847 XREFS 21337 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.6242789249999999} PREDS {{146 0 0-2871 {}} {259 0 0-3158 {}}} SUCCS {{258 0 0-3162 {}}} CYCLES {}}
+set a(0-3160) {NAME ACC1-3:slc(ACC1:acc#116.psp) TYPE READSLICE PAR 0-2847 XREFS 21338 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.6242789249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3156 {}}} SUCCS {{259 0 0-3161 {}}} CYCLES {}}
+set a(0-3161) {NAME ACC1:conc#510 TYPE CONCATENATE PAR 0-2847 XREFS 21339 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.6242789249999999} PREDS {{146 0 0-2871 {}} {259 0 0-3160 {}}} SUCCS {{259 0 0-3162 {}}} CYCLES {}}
+set a(0-3162) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#169 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21340 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.5068208770708271 1 0.6515248020708271} PREDS {{146 0 0-2871 {}} {258 0 0-3159 {}} {259 0 0-3161 {}}} SUCCS {{259 0 0-3163 {}}} CYCLES {}}
+set a(0-3163) {NAME ACC1:slc#36 TYPE READSLICE PAR 0-2847 XREFS 21341 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3162 {}}} SUCCS {{259 0 0-3164 {}} {258 0 0-3166 {}} {258 0 0-3168 {}} {258 0 0-3585 {}} {258 0 0-3596 {}}} CYCLES {}}
+set a(0-3164) {NAME ACC1-3:slc(acc.imod#2) TYPE READSLICE PAR 0-2847 XREFS 21342 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3163 {}}} SUCCS {{259 0 0-3165 {}}} CYCLES {}}
+set a(0-3165) {NAME ACC1:conc#512 TYPE CONCATENATE PAR 0-2847 XREFS 21343 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3164 {}}} SUCCS {{258 0 0-3171 {}}} CYCLES {}}
+set a(0-3166) {NAME ACC1-3:slc(acc.imod#2)#1 TYPE READSLICE PAR 0-2847 XREFS 21344 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3163 {}}} SUCCS {{259 0 0-3167 {}}} CYCLES {}}
+set a(0-3167) {NAME ACC1-3:not#25 TYPE NOT PAR 0-2847 XREFS 21345 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3166 {}}} SUCCS {{258 0 0-3170 {}}} CYCLES {}}
+set a(0-3168) {NAME ACC1-3:slc(acc.imod#2)#2 TYPE READSLICE PAR 0-2847 XREFS 21346 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3163 {}}} SUCCS {{259 0 0-3169 {}}} CYCLES {}}
+set a(0-3169) {NAME ACC1-3:not#26 TYPE NOT PAR 0-2847 XREFS 21347 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3168 {}}} SUCCS {{259 0 0-3170 {}}} CYCLES {}}
+set a(0-3170) {NAME ACC1:conc#513 TYPE CONCATENATE PAR 0-2847 XREFS 21348 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3167 {}} {259 0 0-3169 {}}} SUCCS {{259 0 0-3171 {}}} CYCLES {}}
+set a(0-3171) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#170 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21349 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.5340668020708271 1 0.6787707270708271} PREDS {{146 0 0-2871 {}} {258 0 0-3165 {}} {259 0 0-3170 {}}} SUCCS {{259 0 0-3172 {}}} CYCLES {}}
+set a(0-3172) {NAME ACC1:slc#37 TYPE READSLICE PAR 0-2847 XREFS 21350 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3171 {}}} SUCCS {{258 0 0-3384 {}} {258 0 0-3386 {}} {258 0 0-3573 {}}} CYCLES {}}
+set a(0-3173) {NAME regs.regs:asn#3 TYPE ASSIGN PAR 0-2847 XREFS 21351 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.224020425} PREDS {{146 0 0-2871 {}} {262 0 0-4372 {}}} SUCCS {{259 0 0-3174 {}} {256 0 0-4372 {}}} CYCLES {}}
+set a(0-3174) {NAME regs.regs:slc(regs.regs(2))#4 TYPE READSLICE PAR 0-2847 XREFS 21352 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.224020425} PREDS {{146 0 0-2871 {}} {259 0 0-3173 {}}} SUCCS {{258 0 0-3177 {}}} CYCLES {}}
+set a(0-3175) {NAME regs.regs:asn#4 TYPE ASSIGN PAR 0-2847 XREFS 21353 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.224020425} PREDS {{146 0 0-2871 {}} {262 0 0-4372 {}}} SUCCS {{259 0 0-3176 {}} {256 0 0-4372 {}}} CYCLES {}}
+set a(0-3176) {NAME regs.regs:slc(regs.regs(2))#5 TYPE READSLICE PAR 0-2847 XREFS 21354 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.224020425} PREDS {{146 0 0-2871 {}} {259 0 0-3175 {}}} SUCCS {{259 0 0-3177 {}}} CYCLES {}}
+set a(0-3177) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#171 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 21355 LOC {1 0.0 1 0.03651405 1 0.03651405 1 0.1076981533364113 1 0.2952045283364113} PREDS {{146 0 0-2871 {}} {258 0 0-3174 {}} {259 0 0-3176 {}}} SUCCS {{258 0 0-3180 {}}} CYCLES {}}
+set a(0-3178) {NAME regs.regs:asn#5 TYPE ASSIGN PAR 0-2847 XREFS 21356 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.29520457499999997} PREDS {{146 0 0-2871 {}} {262 0 0-4372 {}}} SUCCS {{259 0 0-3179 {}} {256 0 0-4372 {}}} CYCLES {}}
+set a(0-3179) {NAME regs.regs:slc(regs.regs(2))#3 TYPE READSLICE PAR 0-2847 XREFS 21357 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.29520457499999997} PREDS {{146 0 0-2871 {}} {259 0 0-3178 {}}} SUCCS {{259 0 0-3180 {}}} CYCLES {}}
+set a(0-3180) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME ACC1-3:acc#125 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-2847 XREFS 21358 LOC {1 0.07118415 1 0.1076982 1 0.1076982 1 0.18306895637342835 1 0.37057533137342835} PREDS {{146 0 0-2871 {}} {258 0 0-3177 {}} {259 0 0-3179 {}}} SUCCS {{259 0 0-3181 {}} {258 0 0-3184 {}} {258 0 0-3186 {}} {258 0 0-3188 {}} {258 0 0-3193 {}} {258 0 0-3199 {}} {258 0 0-3201 {}} {258 0 0-3203 {}} {258 0 0-3208 {}} {258 0 0-3210 {}} {258 0 0-3214 {}} {258 0 0-3924 {}}} CYCLES {}}
+set a(0-3181) {NAME ACC1-3:slc(acc#5.psp)#39 TYPE READSLICE PAR 0-2847 XREFS 21359 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.41135842499999997} PREDS {{146 0 0-2871 {}} {259 0 0-3180 {}}} SUCCS {{259 0 0-3182 {}}} CYCLES {}}
+set a(0-3182) {NAME ACC1-3:not#115 TYPE NOT PAR 0-2847 XREFS 21360 LOC {1 0.14655495 1 0.22385205 1 0.22385205 1 0.41135842499999997} PREDS {{146 0 0-2871 {}} {259 0 0-3181 {}}} SUCCS {{259 0 0-3183 {}}} CYCLES {}}
+set a(0-3183) {NAME ACC1:conc#521 TYPE CONCATENATE PAR 0-2847 XREFS 21361 LOC {1 0.14655495 1 0.22385205 1 0.22385205 1 0.41135842499999997} PREDS {{146 0 0-2871 {}} {259 0 0-3182 {}}} SUCCS {{258 0 0-3196 {}}} CYCLES {}}
+set a(0-3184) {NAME ACC1-3:slc(acc#5.psp)#40 TYPE READSLICE PAR 0-2847 XREFS 21362 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-2871 {}} {258 0 0-3180 {}}} SUCCS {{259 0 0-3185 {}}} CYCLES {}}
+set a(0-3185) {NAME ACC1:conc#517 TYPE CONCATENATE PAR 0-2847 XREFS 21363 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-2871 {}} {259 0 0-3184 {}}} SUCCS {{258 0 0-3191 {}}} CYCLES {}}
+set a(0-3186) {NAME ACC1-3:slc(acc#5.psp)#41 TYPE READSLICE PAR 0-2847 XREFS 21364 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-2871 {}} {258 0 0-3180 {}}} SUCCS {{259 0 0-3187 {}}} CYCLES {}}
+set a(0-3187) {NAME ACC1-3:not#116 TYPE NOT PAR 0-2847 XREFS 21365 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-2871 {}} {259 0 0-3186 {}}} SUCCS {{258 0 0-3190 {}}} CYCLES {}}
+set a(0-3188) {NAME ACC1-3:slc(acc#5.psp)#45 TYPE READSLICE PAR 0-2847 XREFS 21366 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-2871 {}} {258 0 0-3180 {}}} SUCCS {{259 0 0-3189 {}}} CYCLES {}}
+set a(0-3189) {NAME ACC1-3:not#118 TYPE NOT PAR 0-2847 XREFS 21367 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-2871 {}} {259 0 0-3188 {}}} SUCCS {{259 0 0-3190 {}}} CYCLES {}}
+set a(0-3190) {NAME ACC1:conc#518 TYPE CONCATENATE PAR 0-2847 XREFS 21368 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-2871 {}} {258 0 0-3187 {}} {259 0 0-3189 {}}} SUCCS {{259 0 0-3191 {}}} CYCLES {}}
+set a(0-3191) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#173 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21369 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.22385201008947522 1 0.4113583850894752} PREDS {{146 0 0-2871 {}} {258 0 0-3185 {}} {259 0 0-3190 {}}} SUCCS {{259 0 0-3192 {}}} CYCLES {}}
+set a(0-3192) {NAME ACC1:slc#39 TYPE READSLICE PAR 0-2847 XREFS 21370 LOC {1 0.187338 1 0.22385205 1 0.22385205 1 0.41135842499999997} PREDS {{146 0 0-2871 {}} {259 0 0-3191 {}}} SUCCS {{258 0 0-3195 {}}} CYCLES {}}
+set a(0-3193) {NAME ACC1-3:slc(acc#5.psp)#47 TYPE READSLICE PAR 0-2847 XREFS 21371 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.41135842499999997} PREDS {{146 0 0-2871 {}} {258 0 0-3180 {}}} SUCCS {{259 0 0-3194 {}}} CYCLES {}}
+set a(0-3194) {NAME ACC1-3:not#119 TYPE NOT PAR 0-2847 XREFS 21372 LOC {1 0.14655495 1 0.22385205 1 0.22385205 1 0.41135842499999997} PREDS {{146 0 0-2871 {}} {259 0 0-3193 {}}} SUCCS {{259 0 0-3195 {}}} CYCLES {}}
+set a(0-3195) {NAME ACC1:conc#522 TYPE CONCATENATE PAR 0-2847 XREFS 21373 LOC {1 0.187338 1 0.22385205 1 0.22385205 1 0.41135842499999997} PREDS {{146 0 0-2871 {}} {258 0 0-3192 {}} {259 0 0-3194 {}}} SUCCS {{259 0 0-3196 {}}} CYCLES {}}
+set a(0-3196) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#175 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-2847 XREFS 21374 LOC {1 0.187338 1 0.22385205 1 0.22385205 1 0.2568888201789505 1 0.4443951951789505} PREDS {{146 0 0-2871 {}} {258 0 0-3183 {}} {259 0 0-3195 {}}} SUCCS {{259 0 0-3197 {}}} CYCLES {}}
+set a(0-3197) {NAME ACC1:slc#41 TYPE READSLICE PAR 0-2847 XREFS 21375 LOC {1 0.220374825 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3196 {}}} SUCCS {{259 0 0-3198 {}}} CYCLES {}}
+set a(0-3198) {NAME ACC1:conc#523 TYPE CONCATENATE PAR 0-2847 XREFS 21376 LOC {1 0.220374825 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3197 {}}} SUCCS {{258 0 0-3216 {}}} CYCLES {}}
+set a(0-3199) {NAME ACC1-3:slc(acc#5.psp)#42 TYPE READSLICE PAR 0-2847 XREFS 21377 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.376366275} PREDS {{146 0 0-2871 {}} {258 0 0-3180 {}}} SUCCS {{259 0 0-3200 {}}} CYCLES {}}
+set a(0-3200) {NAME ACC1:conc#515 TYPE CONCATENATE PAR 0-2847 XREFS 21378 LOC {1 0.14655495 1 0.1888599 1 0.1888599 1 0.376366275} PREDS {{146 0 0-2871 {}} {259 0 0-3199 {}}} SUCCS {{258 0 0-3205 {}}} CYCLES {}}
+set a(0-3201) {NAME ACC1-3:slc(acc#5.psp)#43 TYPE READSLICE PAR 0-2847 XREFS 21379 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.376366275} PREDS {{146 0 0-2871 {}} {258 0 0-3180 {}}} SUCCS {{259 0 0-3202 {}}} CYCLES {}}
+set a(0-3202) {NAME ACC1-3:not#117 TYPE NOT PAR 0-2847 XREFS 21380 LOC {1 0.14655495 1 0.1888599 1 0.1888599 1 0.376366275} PREDS {{146 0 0-2871 {}} {259 0 0-3201 {}}} SUCCS {{258 0 0-3204 {}}} CYCLES {}}
+set a(0-3203) {NAME ACC1-3:slc(acc#5.psp)#44 TYPE READSLICE PAR 0-2847 XREFS 21381 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.376366275} PREDS {{146 0 0-2871 {}} {258 0 0-3180 {}}} SUCCS {{259 0 0-3204 {}}} CYCLES {}}
+set a(0-3204) {NAME ACC1:conc#516 TYPE CONCATENATE PAR 0-2847 XREFS 21382 LOC {1 0.14655495 1 0.1888599 1 0.1888599 1 0.376366275} PREDS {{146 0 0-2871 {}} {258 0 0-3202 {}} {259 0 0-3203 {}}} SUCCS {{259 0 0-3205 {}}} CYCLES {}}
+set a(0-3205) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#172 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21383 LOC {1 0.14655495 1 0.1888599 1 0.1888599 1 0.22964291008947524 1 0.41714928508947524} PREDS {{146 0 0-2871 {}} {258 0 0-3200 {}} {259 0 0-3204 {}}} SUCCS {{259 0 0-3206 {}}} CYCLES {}}
+set a(0-3206) {NAME ACC1:slc#38 TYPE READSLICE PAR 0-2847 XREFS 21384 LOC {1 0.187338 1 0.22964294999999998 1 0.22964294999999998 1 0.41714932499999996} PREDS {{146 0 0-2871 {}} {259 0 0-3205 {}}} SUCCS {{259 0 0-3207 {}}} CYCLES {}}
+set a(0-3207) {NAME ACC1:conc#519 TYPE CONCATENATE PAR 0-2847 XREFS 21385 LOC {1 0.187338 1 0.22964294999999998 1 0.22964294999999998 1 0.41714932499999996} PREDS {{146 0 0-2871 {}} {259 0 0-3206 {}}} SUCCS {{258 0 0-3212 {}}} CYCLES {}}
+set a(0-3208) {NAME ACC1-3:slc(acc#5.psp)#49 TYPE READSLICE PAR 0-2847 XREFS 21386 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.41714932499999996} PREDS {{146 0 0-2871 {}} {258 0 0-3180 {}}} SUCCS {{259 0 0-3209 {}}} CYCLES {}}
+set a(0-3209) {NAME ACC1-3:not#120 TYPE NOT PAR 0-2847 XREFS 21387 LOC {1 0.14655495 1 0.22964294999999998 1 0.22964294999999998 1 0.41714932499999996} PREDS {{146 0 0-2871 {}} {259 0 0-3208 {}}} SUCCS {{258 0 0-3211 {}}} CYCLES {}}
+set a(0-3210) {NAME ACC1-3:slc(acc#5.psp)#46 TYPE READSLICE PAR 0-2847 XREFS 21388 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.41714932499999996} PREDS {{146 0 0-2871 {}} {258 0 0-3180 {}}} SUCCS {{259 0 0-3211 {}}} CYCLES {}}
+set a(0-3211) {NAME ACC1:conc#520 TYPE CONCATENATE PAR 0-2847 XREFS 21389 LOC {1 0.14655495 1 0.22964294999999998 1 0.22964294999999998 1 0.41714932499999996} PREDS {{146 0 0-2871 {}} {258 0 0-3209 {}} {259 0 0-3210 {}}} SUCCS {{259 0 0-3212 {}}} CYCLES {}}
+set a(0-3212) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#174 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21390 LOC {1 0.187338 1 0.22964294999999998 1 0.22964294999999998 1 0.25688882707082716 1 0.44439520207082717} PREDS {{146 0 0-2871 {}} {258 0 0-3207 {}} {259 0 0-3211 {}}} SUCCS {{259 0 0-3213 {}}} CYCLES {}}
+set a(0-3213) {NAME ACC1:slc#40 TYPE READSLICE PAR 0-2847 XREFS 21391 LOC {1 0.21458392499999998 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3212 {}}} SUCCS {{258 0 0-3215 {}}} CYCLES {}}
+set a(0-3214) {NAME ACC1-3:slc(acc#5.psp)#48 TYPE READSLICE PAR 0-2847 XREFS 21392 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.44439524999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3180 {}}} SUCCS {{259 0 0-3215 {}}} CYCLES {}}
+set a(0-3215) {NAME ACC1:conc#524 TYPE CONCATENATE PAR 0-2847 XREFS 21393 LOC {1 0.21458392499999998 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3213 {}} {259 0 0-3214 {}}} SUCCS {{259 0 0-3216 {}}} CYCLES {}}
+set a(0-3216) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#176 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 21394 LOC {1 0.220374825 1 0.25688887499999996 1 0.25688887499999996 1 0.29517833449693603 1 0.48268470949693604} PREDS {{146 0 0-2871 {}} {258 0 0-3198 {}} {259 0 0-3215 {}}} SUCCS {{259 0 0-3217 {}}} CYCLES {}}
+set a(0-3217) {NAME ACC1:slc#42 TYPE READSLICE PAR 0-2847 XREFS 21395 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-2871 {}} {259 0 0-3216 {}}} SUCCS {{259 0 0-3218 {}} {258 0 0-3220 {}} {258 0 0-3222 {}} {258 0 0-3226 {}} {258 0 0-3925 {}}} CYCLES {}}
+set a(0-3218) {NAME ACC1-3:slc(ACC1:acc#110.psp) TYPE READSLICE PAR 0-2847 XREFS 21396 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-2871 {}} {259 0 0-3217 {}}} SUCCS {{259 0 0-3219 {}}} CYCLES {}}
+set a(0-3219) {NAME ACC1:conc#525 TYPE CONCATENATE PAR 0-2847 XREFS 21397 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-2871 {}} {259 0 0-3218 {}}} SUCCS {{258 0 0-3224 {}}} CYCLES {}}
+set a(0-3220) {NAME ACC1-3:slc(ACC1:acc#110.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21398 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-2871 {}} {258 0 0-3217 {}}} SUCCS {{259 0 0-3221 {}}} CYCLES {}}
+set a(0-3221) {NAME ACC1-3:not#137 TYPE NOT PAR 0-2847 XREFS 21399 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-2871 {}} {259 0 0-3220 {}}} SUCCS {{258 0 0-3223 {}}} CYCLES {}}
+set a(0-3222) {NAME ACC1-3:slc(ACC1:acc#110.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21400 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-2871 {}} {258 0 0-3217 {}}} SUCCS {{259 0 0-3223 {}}} CYCLES {}}
+set a(0-3223) {NAME ACC1:conc#526 TYPE CONCATENATE PAR 0-2847 XREFS 21401 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-2871 {}} {258 0 0-3221 {}} {259 0 0-3222 {}}} SUCCS {{259 0 0-3224 {}}} CYCLES {}}
+set a(0-3224) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#177 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21402 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.33596138508947526 1 0.5234677600894753} PREDS {{146 0 0-2871 {}} {258 0 0-3219 {}} {259 0 0-3223 {}}} SUCCS {{259 0 0-3225 {}}} CYCLES {}}
+set a(0-3225) {NAME ACC1:slc#43 TYPE READSLICE PAR 0-2847 XREFS 21403 LOC {1 0.29944737499999996 1 0.335961425 1 0.335961425 1 0.5234677999999999} PREDS {{146 0 0-2871 {}} {259 0 0-3224 {}}} SUCCS {{258 0 0-3228 {}}} CYCLES {}}
+set a(0-3226) {NAME ACC1-3:slc(ACC1:acc#110.psp)#3 TYPE READSLICE PAR 0-2847 XREFS 21404 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.5234677999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3217 {}}} SUCCS {{259 0 0-3227 {}}} CYCLES {}}
+set a(0-3227) {NAME ACC1-3:not#154 TYPE NOT PAR 0-2847 XREFS 21405 LOC {1 0.258664325 1 0.335961425 1 0.335961425 1 0.5234677999999999} PREDS {{146 0 0-2871 {}} {259 0 0-3226 {}}} SUCCS {{259 0 0-3228 {}}} CYCLES {}}
+set a(0-3228) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1-3:acc#118 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-2847 XREFS 21406 LOC {1 0.29944737499999996 1 0.335961425 1 0.335961425 1 0.3564341850894752 1 0.5439405600894752} PREDS {{146 0 0-2871 {}} {258 0 0-3225 {}} {259 0 0-3227 {}}} SUCCS {{259 0 0-3229 {}} {258 0 0-3232 {}} {258 0 0-3923 {}}} CYCLES {}}
+set a(0-3229) {NAME ACC1-3:slc(ACC1:acc#118.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21407 LOC {1 0.319920175 1 0.356434225 1 0.356434225 1 0.5439406} PREDS {{146 0 0-2871 {}} {259 0 0-3228 {}}} SUCCS {{259 0 0-3230 {}}} CYCLES {}}
+set a(0-3230) {NAME ACC1-3:not#147 TYPE NOT PAR 0-2847 XREFS 21408 LOC {1 0.319920175 1 0.356434225 1 0.356434225 1 0.5439406} PREDS {{146 0 0-2871 {}} {259 0 0-3229 {}}} SUCCS {{259 0 0-3231 {}}} CYCLES {}}
+set a(0-3231) {NAME ACC1:conc#527 TYPE CONCATENATE PAR 0-2847 XREFS 21409 LOC {1 0.319920175 1 0.356434225 1 0.356434225 1 0.5439406} PREDS {{146 0 0-2871 {}} {259 0 0-3230 {}}} SUCCS {{258 0 0-3234 {}}} CYCLES {}}
+set a(0-3232) {NAME ACC1-3:slc(ACC1:acc#118.psp) TYPE READSLICE PAR 0-2847 XREFS 21410 LOC {1 0.319920175 1 0.356434225 1 0.356434225 1 0.5439406} PREDS {{146 0 0-2871 {}} {258 0 0-3228 {}}} SUCCS {{259 0 0-3233 {}}} CYCLES {}}
+set a(0-3233) {NAME ACC1:conc#528 TYPE CONCATENATE PAR 0-2847 XREFS 21411 LOC {1 0.319920175 1 0.356434225 1 0.356434225 1 0.5439406} PREDS {{146 0 0-2871 {}} {259 0 0-3232 {}}} SUCCS {{259 0 0-3234 {}}} CYCLES {}}
+set a(0-3234) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#178 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21412 LOC {1 0.319920175 1 0.356434225 1 0.356434225 1 0.38368010207082714 1 0.5711864770708271} PREDS {{146 0 0-2871 {}} {258 0 0-3231 {}} {259 0 0-3233 {}}} SUCCS {{259 0 0-3235 {}}} CYCLES {}}
+set a(0-3235) {NAME ACC1:slc#44 TYPE READSLICE PAR 0-2847 XREFS 21413 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-2871 {}} {259 0 0-3234 {}}} SUCCS {{259 0 0-3236 {}} {258 0 0-3238 {}} {258 0 0-3240 {}} {258 0 0-3914 {}}} CYCLES {}}
+set a(0-3236) {NAME ACC1-3:slc(acc.imod#6) TYPE READSLICE PAR 0-2847 XREFS 21414 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-2871 {}} {259 0 0-3235 {}}} SUCCS {{259 0 0-3237 {}}} CYCLES {}}
+set a(0-3237) {NAME ACC1:conc#530 TYPE CONCATENATE PAR 0-2847 XREFS 21415 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-2871 {}} {259 0 0-3236 {}}} SUCCS {{258 0 0-3243 {}}} CYCLES {}}
+set a(0-3238) {NAME ACC1-3:slc(acc.imod#6)#1 TYPE READSLICE PAR 0-2847 XREFS 21416 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-2871 {}} {258 0 0-3235 {}}} SUCCS {{259 0 0-3239 {}}} CYCLES {}}
+set a(0-3239) {NAME ACC1-3:not#57 TYPE NOT PAR 0-2847 XREFS 21417 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-2871 {}} {259 0 0-3238 {}}} SUCCS {{258 0 0-3242 {}}} CYCLES {}}
+set a(0-3240) {NAME ACC1-3:slc(acc.imod#6)#2 TYPE READSLICE PAR 0-2847 XREFS 21418 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-2871 {}} {258 0 0-3235 {}}} SUCCS {{259 0 0-3241 {}}} CYCLES {}}
+set a(0-3241) {NAME ACC1-3:not#58 TYPE NOT PAR 0-2847 XREFS 21419 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-2871 {}} {259 0 0-3240 {}}} SUCCS {{259 0 0-3242 {}}} CYCLES {}}
+set a(0-3242) {NAME ACC1:conc#531 TYPE CONCATENATE PAR 0-2847 XREFS 21420 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-2871 {}} {258 0 0-3239 {}} {259 0 0-3241 {}}} SUCCS {{259 0 0-3243 {}}} CYCLES {}}
+set a(0-3243) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#179 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21421 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.41092602707082715 1 0.5984324020708272} PREDS {{146 0 0-2871 {}} {258 0 0-3237 {}} {259 0 0-3242 {}}} SUCCS {{259 0 0-3244 {}}} CYCLES {}}
+set a(0-3244) {NAME ACC1:slc#45 TYPE READSLICE PAR 0-2847 XREFS 21422 LOC {1 0.374412025 1 0.410926075 1 0.410926075 1 0.59843245} PREDS {{146 0 0-2871 {}} {259 0 0-3243 {}}} SUCCS {{258 0 0-3915 {}}} CYCLES {}}
+set a(0-3245) {NAME regs.regs:asn#6 TYPE ASSIGN PAR 0-2847 XREFS 21423 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15038815} PREDS {{146 0 0-2871 {}} {262 0 0-4372 {}}} SUCCS {{259 0 0-3246 {}} {256 0 0-4372 {}}} CYCLES {}}
+set a(0-3246) {NAME regs.regs:slc(regs.regs(2))#7 TYPE READSLICE PAR 0-2847 XREFS 21424 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15038815} PREDS {{146 0 0-2871 {}} {259 0 0-3245 {}}} SUCCS {{258 0 0-3249 {}}} CYCLES {}}
+set a(0-3247) {NAME regs.regs:asn#7 TYPE ASSIGN PAR 0-2847 XREFS 21425 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15038815} PREDS {{146 0 0-2871 {}} {262 0 0-4372 {}}} SUCCS {{259 0 0-3248 {}} {256 0 0-4372 {}}} CYCLES {}}
+set a(0-3248) {NAME regs.regs:slc(regs.regs(2))#8 TYPE READSLICE PAR 0-2847 XREFS 21426 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15038815} PREDS {{146 0 0-2871 {}} {259 0 0-3247 {}}} SUCCS {{259 0 0-3249 {}}} CYCLES {}}
+set a(0-3249) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#180 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 21427 LOC {1 0.0 1 0.15038815 1 0.15038815 1 0.2215722533364113 1 0.2215722533364113} PREDS {{146 0 0-2871 {}} {258 0 0-3246 {}} {259 0 0-3248 {}}} SUCCS {{258 0 0-3252 {}}} CYCLES {}}
+set a(0-3250) {NAME regs.regs:asn#8 TYPE ASSIGN PAR 0-2847 XREFS 21428 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.2215723} PREDS {{146 0 0-2871 {}} {262 0 0-4372 {}}} SUCCS {{259 0 0-3251 {}} {256 0 0-4372 {}}} CYCLES {}}
+set a(0-3251) {NAME regs.regs:slc(regs.regs(2))#6 TYPE READSLICE PAR 0-2847 XREFS 21429 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.2215723} PREDS {{146 0 0-2871 {}} {259 0 0-3250 {}}} SUCCS {{259 0 0-3252 {}}} CYCLES {}}
+set a(0-3252) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME ACC1-3:acc#10 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-2847 XREFS 21430 LOC {1 0.07118415 1 0.2215723 1 0.2215723 1 0.2969430563734284 1 0.2969430563734284} PREDS {{146 0 0-2871 {}} {258 0 0-3249 {}} {259 0 0-3251 {}}} SUCCS {{259 0 0-3253 {}} {258 0 0-3256 {}} {258 0 0-3258 {}} {258 0 0-3263 {}} {258 0 0-3265 {}} {258 0 0-3269 {}} {258 0 0-3271 {}} {258 0 0-3273 {}} {258 0 0-3279 {}} {258 0 0-3281 {}} {258 0 0-3283 {}} {258 0 0-3287 {}} {258 0 0-3617 {}} {258 0 0-3618 {}} {258 0 0-3619 {}} {258 0 0-3621 {}} {258 0 0-3625 {}} {258 0 0-3631 {}} {258 0 0-3632 {}} {258 0 0-3636 {}} {258 0 0-3643 {}} {258 0 0-3644 {}} {258 0 0-3645 {}} {258 0 0-3648 {}} {258 0 0-3650 {}} {258 0 0-3655 {}} {258 0 0-3656 {}} {258 0 0-3657 {}} {258 0 0-3658 {}} {258 0 0-3661 {}} {258 0 0-3662 {}} {258 0 0-3666 {}} {258 0 0-3667 {}} {258 0 0-3668 {}} {258 0 0-3670 {}} {258 0 0-3672 {}} {258 0 0-3675 {}} {258 0 0-3678 {}} {258 0 0-3680 {}} {258 0 0-3692 {}} {258 0 0-3693 {}} {258 0 0-3694 {}} {258 0 0-3695 {}} {258 0 0-3696 {}} {258 0 0-3848 {}} {258 0 0-3849 {}} {258 0 0-3850 {}} {258 0 0-3851 {}} {258 0 0-3852 {}} {258 0 0-3854 {}} {258 0 0-3855 {}} {258 0 0-3856 {}} {258 0 0-3857 {}} {258 0 0-3860 {}} {258 0 0-3861 {}} {258 0 0-3862 {}} {258 0 0-3865 {}} {258 0 0-3868 {}} {258 0 0-3871 {}} {258 0 0-3877 {}} {258 0 0-3880 {}} {258 0 0-3888 {}} {258 0 0-3891 {}} {258 0 0-3897 {}} {258 0 0-3900 {}}} CYCLES {}}
+set a(0-3253) {NAME ACC1-3:slc(acc#10.psp)#11 TYPE READSLICE PAR 0-2847 XREFS 21431 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.321617575} PREDS {{146 0 0-2871 {}} {259 0 0-3252 {}}} SUCCS {{259 0 0-3254 {}}} CYCLES {}}
+set a(0-3254) {NAME ACC1-3:not#152 TYPE NOT PAR 0-2847 XREFS 21432 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.321617575} PREDS {{146 0 0-2871 {}} {259 0 0-3253 {}}} SUCCS {{259 0 0-3255 {}}} CYCLES {}}
+set a(0-3255) {NAME ACC1:conc#537 TYPE CONCATENATE PAR 0-2847 XREFS 21433 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.321617575} PREDS {{146 0 0-2871 {}} {259 0 0-3254 {}}} SUCCS {{258 0 0-3260 {}}} CYCLES {}}
+set a(0-3256) {NAME ACC1-3:slc(acc#10.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21434 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.321617575} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3257 {}}} CYCLES {}}
+set a(0-3257) {NAME ACC1-3:not#124 TYPE NOT PAR 0-2847 XREFS 21435 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.321617575} PREDS {{146 0 0-2871 {}} {259 0 0-3256 {}}} SUCCS {{258 0 0-3259 {}}} CYCLES {}}
+set a(0-3258) {NAME ACC1-3:slc(acc#10.psp)#8 TYPE READSLICE PAR 0-2847 XREFS 21436 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.321617575} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3259 {}}} CYCLES {}}
+set a(0-3259) {NAME ACC1:conc#538 TYPE CONCATENATE PAR 0-2847 XREFS 21437 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.321617575} PREDS {{146 0 0-2871 {}} {258 0 0-3257 {}} {259 0 0-3258 {}}} SUCCS {{259 0 0-3260 {}}} CYCLES {}}
+set a(0-3260) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1:acc#183 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-2847 XREFS 21438 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.34209033508947523 1 0.34209033508947523} PREDS {{146 0 0-2871 {}} {258 0 0-3255 {}} {259 0 0-3259 {}}} SUCCS {{259 0 0-3261 {}}} CYCLES {}}
+set a(0-3261) {NAME ACC1:slc#48 TYPE READSLICE PAR 0-2847 XREFS 21439 LOC {1 0.16702775 1 0.342090375 1 0.342090375 1 0.342090375} PREDS {{146 0 0-2871 {}} {259 0 0-3260 {}}} SUCCS {{259 0 0-3262 {}}} CYCLES {}}
+set a(0-3262) {NAME ACC1:conc#541 TYPE CONCATENATE PAR 0-2847 XREFS 21440 LOC {1 0.16702775 1 0.342090375 1 0.342090375 1 0.342090375} PREDS {{146 0 0-2871 {}} {259 0 0-3261 {}}} SUCCS {{258 0 0-3267 {}}} CYCLES {}}
+set a(0-3263) {NAME ACC1-3:slc(acc#10.psp) TYPE READSLICE PAR 0-2847 XREFS 21441 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.342090375} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3264 {}}} CYCLES {}}
+set a(0-3264) {NAME ACC1:conc#532 TYPE CONCATENATE PAR 0-2847 XREFS 21442 LOC {1 0.14655495 1 0.342090375 1 0.342090375 1 0.342090375} PREDS {{146 0 0-2871 {}} {259 0 0-3263 {}}} SUCCS {{258 0 0-3266 {}}} CYCLES {}}
+set a(0-3265) {NAME ACC1-3:slc(acc#10.psp)#10 TYPE READSLICE PAR 0-2847 XREFS 21443 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.342090375} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3266 {}}} CYCLES {}}
+set a(0-3266) {NAME ACC1:conc#542 TYPE CONCATENATE PAR 0-2847 XREFS 21444 LOC {1 0.14655495 1 0.342090375 1 0.342090375 1 0.342090375} PREDS {{146 0 0-2871 {}} {258 0 0-3264 {}} {259 0 0-3265 {}}} SUCCS {{259 0 0-3267 {}}} CYCLES {}}
+set a(0-3267) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#185 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 21445 LOC {1 0.16702775 1 0.342090375 1 0.342090375 1 0.3852822701789505 1 0.3852822701789505} PREDS {{146 0 0-2871 {}} {258 0 0-3262 {}} {259 0 0-3266 {}}} SUCCS {{259 0 0-3268 {}}} CYCLES {}}
+set a(0-3268) {NAME ACC1:slc#50 TYPE READSLICE PAR 0-2847 XREFS 21446 LOC {1 0.21021969999999998 1 0.385282325 1 0.385282325 1 0.385282325} PREDS {{146 0 0-2871 {}} {259 0 0-3267 {}}} SUCCS {{258 0 0-3292 {}}} CYCLES {}}
+set a(0-3269) {NAME ACC1-3:slc(acc#10.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21447 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3270 {}}} CYCLES {}}
+set a(0-3270) {NAME ACC1:conc#535 TYPE CONCATENATE PAR 0-2847 XREFS 21448 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3269 {}}} SUCCS {{258 0 0-3276 {}}} CYCLES {}}
+set a(0-3271) {NAME ACC1-3:slc(acc#10.psp)#3 TYPE READSLICE PAR 0-2847 XREFS 21449 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3272 {}}} CYCLES {}}
+set a(0-3272) {NAME ACC1-3:not#125 TYPE NOT PAR 0-2847 XREFS 21450 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3271 {}}} SUCCS {{258 0 0-3275 {}}} CYCLES {}}
+set a(0-3273) {NAME ACC1-3:slc(acc#10.psp)#7 TYPE READSLICE PAR 0-2847 XREFS 21451 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3274 {}}} CYCLES {}}
+set a(0-3274) {NAME ACC1-3:not#127 TYPE NOT PAR 0-2847 XREFS 21452 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3273 {}}} SUCCS {{259 0 0-3275 {}}} CYCLES {}}
+set a(0-3275) {NAME ACC1:conc#536 TYPE CONCATENATE PAR 0-2847 XREFS 21453 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3272 {}} {259 0 0-3274 {}}} SUCCS {{259 0 0-3276 {}}} CYCLES {}}
+set a(0-3276) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#182 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21454 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.3377261100894752 1 0.3377261100894752} PREDS {{146 0 0-2871 {}} {258 0 0-3270 {}} {259 0 0-3275 {}}} SUCCS {{259 0 0-3277 {}}} CYCLES {}}
+set a(0-3277) {NAME ACC1:slc#47 TYPE READSLICE PAR 0-2847 XREFS 21455 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.33772615} PREDS {{146 0 0-2871 {}} {259 0 0-3276 {}}} SUCCS {{259 0 0-3278 {}}} CYCLES {}}
+set a(0-3278) {NAME ACC1:conc#539 TYPE CONCATENATE PAR 0-2847 XREFS 21456 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.33772615} PREDS {{146 0 0-2871 {}} {259 0 0-3277 {}}} SUCCS {{258 0 0-3290 {}}} CYCLES {}}
+set a(0-3279) {NAME ACC1-3:slc(acc#10.psp)#4 TYPE READSLICE PAR 0-2847 XREFS 21457 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3280 {}}} CYCLES {}}
+set a(0-3280) {NAME ACC1:conc#533 TYPE CONCATENATE PAR 0-2847 XREFS 21458 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3279 {}}} SUCCS {{258 0 0-3285 {}}} CYCLES {}}
+set a(0-3281) {NAME ACC1-3:slc(acc#10.psp)#5 TYPE READSLICE PAR 0-2847 XREFS 21459 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3282 {}}} CYCLES {}}
+set a(0-3282) {NAME ACC1-3:not#126 TYPE NOT PAR 0-2847 XREFS 21460 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3281 {}}} SUCCS {{258 0 0-3284 {}}} CYCLES {}}
+set a(0-3283) {NAME ACC1-3:slc(acc#10.psp)#6 TYPE READSLICE PAR 0-2847 XREFS 21461 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3284 {}}} CYCLES {}}
+set a(0-3284) {NAME ACC1:conc#534 TYPE CONCATENATE PAR 0-2847 XREFS 21462 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3282 {}} {259 0 0-3283 {}}} SUCCS {{259 0 0-3285 {}}} CYCLES {}}
+set a(0-3285) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#181 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21463 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.3377261100894752 1 0.3377261100894752} PREDS {{146 0 0-2871 {}} {258 0 0-3280 {}} {259 0 0-3284 {}}} SUCCS {{259 0 0-3286 {}}} CYCLES {}}
+set a(0-3286) {NAME ACC1:slc#46 TYPE READSLICE PAR 0-2847 XREFS 21464 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.33772615} PREDS {{146 0 0-2871 {}} {259 0 0-3285 {}}} SUCCS {{258 0 0-3289 {}}} CYCLES {}}
+set a(0-3287) {NAME ACC1-3:slc(acc#10.psp)#9 TYPE READSLICE PAR 0-2847 XREFS 21465 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.33772615} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3288 {}}} CYCLES {}}
+set a(0-3288) {NAME ACC1-3:not#128 TYPE NOT PAR 0-2847 XREFS 21466 LOC {1 0.14655495 1 0.33772615 1 0.33772615 1 0.33772615} PREDS {{146 0 0-2871 {}} {259 0 0-3287 {}}} SUCCS {{259 0 0-3289 {}}} CYCLES {}}
+set a(0-3289) {NAME ACC1:conc#540 TYPE CONCATENATE PAR 0-2847 XREFS 21467 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.33772615} PREDS {{146 0 0-2871 {}} {258 0 0-3286 {}} {259 0 0-3288 {}}} SUCCS {{259 0 0-3290 {}}} CYCLES {}}
+set a(0-3290) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#184 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21468 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.3852822770708272 1 0.3852822770708272} PREDS {{146 0 0-2871 {}} {258 0 0-3278 {}} {259 0 0-3289 {}}} SUCCS {{259 0 0-3291 {}}} CYCLES {}}
+set a(0-3291) {NAME ACC1:slc#49 TYPE READSLICE PAR 0-2847 XREFS 21469 LOC {1 0.23489417499999998 1 0.385282325 1 0.385282325 1 0.385282325} PREDS {{146 0 0-2871 {}} {259 0 0-3290 {}}} SUCCS {{259 0 0-3292 {}}} CYCLES {}}
+set a(0-3292) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1-3:acc#113 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-2847 XREFS 21470 LOC {1 0.23489417499999998 1 0.385282325 1 0.385282325 1 0.4183190951789505 1 0.4183190951789505} PREDS {{146 0 0-2871 {}} {258 0 0-3268 {}} {259 0 0-3291 {}}} SUCCS {{259 0 0-3293 {}} {258 0 0-3295 {}} {258 0 0-3297 {}} {258 0 0-3301 {}} {258 0 0-3624 {}} {258 0 0-3635 {}} {258 0 0-3638 {}} {258 0 0-3902 {}}} CYCLES {}}
+set a(0-3293) {NAME ACC1-3:slc(ACC1:acc#113.psp) TYPE READSLICE PAR 0-2847 XREFS 21471 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.41831915} PREDS {{146 0 0-2871 {}} {259 0 0-3292 {}}} SUCCS {{259 0 0-3294 {}}} CYCLES {}}
+set a(0-3294) {NAME ACC1:conc#543 TYPE CONCATENATE PAR 0-2847 XREFS 21472 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.41831915} PREDS {{146 0 0-2871 {}} {259 0 0-3293 {}}} SUCCS {{258 0 0-3299 {}}} CYCLES {}}
+set a(0-3295) {NAME ACC1-3:slc(ACC1:acc#113.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21473 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.41831915} PREDS {{146 0 0-2871 {}} {258 0 0-3292 {}}} SUCCS {{259 0 0-3296 {}}} CYCLES {}}
+set a(0-3296) {NAME ACC1-3:not#141 TYPE NOT PAR 0-2847 XREFS 21474 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.41831915} PREDS {{146 0 0-2871 {}} {259 0 0-3295 {}}} SUCCS {{258 0 0-3298 {}}} CYCLES {}}
+set a(0-3297) {NAME ACC1-3:slc(ACC1:acc#113.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21475 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.41831915} PREDS {{146 0 0-2871 {}} {258 0 0-3292 {}}} SUCCS {{259 0 0-3298 {}}} CYCLES {}}
+set a(0-3298) {NAME ACC1:conc#544 TYPE CONCATENATE PAR 0-2847 XREFS 21476 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.41831915} PREDS {{146 0 0-2871 {}} {258 0 0-3296 {}} {259 0 0-3297 {}}} SUCCS {{259 0 0-3299 {}}} CYCLES {}}
+set a(0-3299) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#186 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21477 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.45910216008947524 1 0.45910216008947524} PREDS {{146 0 0-2871 {}} {258 0 0-3294 {}} {259 0 0-3298 {}}} SUCCS {{259 0 0-3300 {}}} CYCLES {}}
+set a(0-3300) {NAME ACC1:slc#51 TYPE READSLICE PAR 0-2847 XREFS 21478 LOC {1 0.30871404999999996 1 0.45910219999999996 1 0.45910219999999996 1 0.45910219999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3299 {}}} SUCCS {{258 0 0-3303 {}}} CYCLES {}}
+set a(0-3301) {NAME ACC1-3:slc(ACC1:acc#113.psp)#3 TYPE READSLICE PAR 0-2847 XREFS 21479 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.45910219999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3292 {}}} SUCCS {{259 0 0-3302 {}}} CYCLES {}}
+set a(0-3302) {NAME ACC1-3:not#155 TYPE NOT PAR 0-2847 XREFS 21480 LOC {1 0.267931 1 0.45910219999999996 1 0.45910219999999996 1 0.45910219999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3301 {}}} SUCCS {{259 0 0-3303 {}}} CYCLES {}}
+set a(0-3303) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1-3:acc#120 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-2847 XREFS 21481 LOC {1 0.30871404999999996 1 0.45910219999999996 1 0.45910219999999996 1 0.4795749600894752 1 0.4795749600894752} PREDS {{146 0 0-2871 {}} {258 0 0-3300 {}} {259 0 0-3302 {}}} SUCCS {{259 0 0-3304 {}} {258 0 0-3307 {}} {258 0 0-3629 {}}} CYCLES {}}
+set a(0-3304) {NAME ACC1-3:slc(ACC1:acc#120.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 21482 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.479575} PREDS {{146 0 0-2871 {}} {259 0 0-3303 {}}} SUCCS {{259 0 0-3305 {}}} CYCLES {}}
+set a(0-3305) {NAME ACC1-3:not#149 TYPE NOT PAR 0-2847 XREFS 21483 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.479575} PREDS {{146 0 0-2871 {}} {259 0 0-3304 {}}} SUCCS {{259 0 0-3306 {}}} CYCLES {}}
+set a(0-3306) {NAME ACC1:conc#545 TYPE CONCATENATE PAR 0-2847 XREFS 21484 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.479575} PREDS {{146 0 0-2871 {}} {259 0 0-3305 {}}} SUCCS {{258 0 0-3309 {}}} CYCLES {}}
+set a(0-3307) {NAME ACC1-3:slc(ACC1:acc#120.psp) TYPE READSLICE PAR 0-2847 XREFS 21485 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.479575} PREDS {{146 0 0-2871 {}} {258 0 0-3303 {}}} SUCCS {{259 0 0-3308 {}}} CYCLES {}}
+set a(0-3308) {NAME ACC1:conc#546 TYPE CONCATENATE PAR 0-2847 XREFS 21486 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.479575} PREDS {{146 0 0-2871 {}} {259 0 0-3307 {}}} SUCCS {{259 0 0-3309 {}}} CYCLES {}}
+set a(0-3309) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#187 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21487 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.5068208770708271 1 0.5068208770708271} PREDS {{146 0 0-2871 {}} {258 0 0-3306 {}} {259 0 0-3308 {}}} SUCCS {{259 0 0-3310 {}}} CYCLES {}}
+set a(0-3310) {NAME ACC1:slc#52 TYPE READSLICE PAR 0-2847 XREFS 21488 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-2871 {}} {259 0 0-3309 {}}} SUCCS {{259 0 0-3311 {}} {258 0 0-3313 {}} {258 0 0-3315 {}} {258 0 0-3882 {}} {258 0 0-3893 {}}} CYCLES {}}
+set a(0-3311) {NAME ACC1-3:slc(acc.imod#10) TYPE READSLICE PAR 0-2847 XREFS 21489 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-2871 {}} {259 0 0-3310 {}}} SUCCS {{259 0 0-3312 {}}} CYCLES {}}
+set a(0-3312) {NAME ACC1:conc#548 TYPE CONCATENATE PAR 0-2847 XREFS 21490 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-2871 {}} {259 0 0-3311 {}}} SUCCS {{258 0 0-3318 {}}} CYCLES {}}
+set a(0-3313) {NAME ACC1-3:slc(acc.imod#10)#1 TYPE READSLICE PAR 0-2847 XREFS 21491 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-2871 {}} {258 0 0-3310 {}}} SUCCS {{259 0 0-3314 {}}} CYCLES {}}
+set a(0-3314) {NAME ACC1-3:not#89 TYPE NOT PAR 0-2847 XREFS 21492 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-2871 {}} {259 0 0-3313 {}}} SUCCS {{258 0 0-3317 {}}} CYCLES {}}
+set a(0-3315) {NAME ACC1-3:slc(acc.imod#10)#2 TYPE READSLICE PAR 0-2847 XREFS 21493 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-2871 {}} {258 0 0-3310 {}}} SUCCS {{259 0 0-3316 {}}} CYCLES {}}
+set a(0-3316) {NAME ACC1-3:not#90 TYPE NOT PAR 0-2847 XREFS 21494 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-2871 {}} {259 0 0-3315 {}}} SUCCS {{259 0 0-3317 {}}} CYCLES {}}
+set a(0-3317) {NAME ACC1:conc#549 TYPE CONCATENATE PAR 0-2847 XREFS 21495 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-2871 {}} {258 0 0-3314 {}} {259 0 0-3316 {}}} SUCCS {{259 0 0-3318 {}}} CYCLES {}}
+set a(0-3318) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#188 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21496 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.5340668020708271 1 0.5340668020708271} PREDS {{146 0 0-2871 {}} {258 0 0-3312 {}} {259 0 0-3317 {}}} SUCCS {{259 0 0-3319 {}}} CYCLES {}}
+set a(0-3319) {NAME ACC1:slc#53 TYPE READSLICE PAR 0-2847 XREFS 21497 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3318 {}}} SUCCS {{258 0 0-3681 {}} {258 0 0-3683 {}} {258 0 0-3870 {}}} CYCLES {}}
+set a(0-3320) {NAME ACC1-3:slc(acc.psp)#61 TYPE READSLICE PAR 0-2847 XREFS 21498 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 2 0.015519449999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3323 {}}} CYCLES {}}
+set a(0-3321) {NAME ACC1-3:slc(acc.psp)#62 TYPE READSLICE PAR 0-2847 XREFS 21499 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 2 0.015519449999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3323 {}}} CYCLES {}}
+set a(0-3322) {NAME ACC1-3:slc(acc.psp)#49 TYPE READSLICE PAR 0-2847 XREFS 21500 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 2 0.015519449999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3323 {}}} CYCLES {}}
+set a(0-3323) {NAME ACC1-3:conc#257 TYPE CONCATENATE PAR 0-2847 XREFS 21501 LOC {1 0.14655495 1 0.8410234999999999 1 0.8410234999999999 2 0.015519449999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3321 {}} {258 0 0-3320 {}} {259 0 0-3322 {}}} SUCCS {{258 0 0-3403 {}}} CYCLES {}}
+set a(0-3324) {NAME ACC1-3:slc(acc.psp)#29 TYPE READSLICE PAR 0-2847 XREFS 21502 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6718295249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3325 {}}} CYCLES {}}
+set a(0-3325) {NAME ACC1:conc#550 TYPE CONCATENATE PAR 0-2847 XREFS 21503 LOC {1 0.14655495 1 0.512853025 1 0.512853025 1 0.6718295249999999} PREDS {{146 0 0-2871 {}} {259 0 0-3324 {}}} SUCCS {{259 0 0-3326 {}}} CYCLES {}}
+set a(0-3326) {NAME ACC1:conc#551 TYPE CONCATENATE PAR 0-2847 XREFS 21504 LOC {1 0.14655495 1 0.512853025 1 0.512853025 1 0.6718295249999999} PREDS {{146 0 0-2871 {}} {259 0 0-3325 {}}} SUCCS {{258 0 0-3330 {}}} CYCLES {}}
+set a(0-3327) {NAME ACC1-3:slc(ACC1:acc#107.psp)#10 TYPE READSLICE PAR 0-2847 XREFS 21505 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.6718295249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3145 {}}} SUCCS {{258 0 0-3329 {}}} CYCLES {}}
+set a(0-3328) {NAME ACC1-3:slc(acc.psp)#30 TYPE READSLICE PAR 0-2847 XREFS 21506 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6718295249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3329 {}}} CYCLES {}}
+set a(0-3329) {NAME ACC1:conc#552 TYPE CONCATENATE PAR 0-2847 XREFS 21507 LOC {1 0.267931 1 0.512853025 1 0.512853025 1 0.6718295249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3327 {}} {259 0 0-3328 {}}} SUCCS {{259 0 0-3330 {}}} CYCLES {}}
+set a(0-3330) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#189 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-2847 XREFS 21508 LOC {1 0.267931 1 0.512853025 1 0.512853025 1 0.5504736020241716 1 0.7094501020241716} PREDS {{146 0 0-2871 {}} {258 0 0-3326 {}} {259 0 0-3329 {}}} SUCCS {{259 0 0-3331 {}}} CYCLES {}}
+set a(0-3331) {NAME ACC1:slc#54 TYPE READSLICE PAR 0-2847 XREFS 21509 LOC {1 0.305551625 1 0.5504736499999999 1 0.5504736499999999 1 0.70945015} PREDS {{146 0 0-2871 {}} {259 0 0-3330 {}}} SUCCS {{258 0 0-3333 {}}} CYCLES {}}
+set a(0-3332) {NAME ACC1-3:slc(ACC1:acc#116.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21510 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.70945015} PREDS {{146 0 0-2871 {}} {258 0 0-3156 {}}} SUCCS {{259 0 0-3333 {}}} CYCLES {}}
+set a(0-3333) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#198 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-2847 XREFS 21511 LOC {1 0.32918685 1 0.5504736499999999 1 0.5504736499999999 1 0.5880942270241716 1 0.7470707270241717} PREDS {{146 0 0-2871 {}} {258 0 0-3331 {}} {259 0 0-3332 {}}} SUCCS {{258 0 0-3345 {}}} CYCLES {}}
+set a(0-3334) {NAME ACC1-3:slc(acc.psp)#31 TYPE READSLICE PAR 0-2847 XREFS 21512 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.71982485} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3336 {}}} CYCLES {}}
+set a(0-3335) {NAME ACC1-3:slc(acc.psp)#32 TYPE READSLICE PAR 0-2847 XREFS 21513 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.71982485} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3336 {}}} CYCLES {}}
+set a(0-3336) {NAME ACC1-3:conc#258 TYPE CONCATENATE PAR 0-2847 XREFS 21514 LOC {1 0.14655495 1 0.56084835 1 0.56084835 1 0.71982485} PREDS {{146 0 0-2871 {}} {258 0 0-3334 {}} {259 0 0-3335 {}}} SUCCS {{259 0 0-3337 {}}} CYCLES {}}
+set a(0-3337) {NAME ACC1:conc#553 TYPE CONCATENATE PAR 0-2847 XREFS 21515 LOC {1 0.14655495 1 0.56084835 1 0.56084835 1 0.71982485} PREDS {{146 0 0-2871 {}} {259 0 0-3336 {}}} SUCCS {{258 0 0-3343 {}}} CYCLES {}}
+set a(0-3338) {NAME ACC1-3:slc(ACC1:acc#107.psp)#11 TYPE READSLICE PAR 0-2847 XREFS 21516 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.71982485} PREDS {{146 0 0-2871 {}} {258 0 0-3145 {}}} SUCCS {{258 0 0-3340 {}}} CYCLES {}}
+set a(0-3339) {NAME ACC1-3:slc(acc.psp)#33 TYPE READSLICE PAR 0-2847 XREFS 21517 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.71982485} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3340 {}}} CYCLES {}}
+set a(0-3340) {NAME ACC1-3:conc#259 TYPE CONCATENATE PAR 0-2847 XREFS 21518 LOC {1 0.267931 1 0.56084835 1 0.56084835 1 0.71982485} PREDS {{146 0 0-2871 {}} {258 0 0-3338 {}} {259 0 0-3339 {}}} SUCCS {{258 0 0-3342 {}}} CYCLES {}}
+set a(0-3341) {NAME ACC1-3:slc(ACC1:acc#107.psp)#8 TYPE READSLICE PAR 0-2847 XREFS 21519 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.71982485} PREDS {{146 0 0-2871 {}} {258 0 0-3145 {}}} SUCCS {{259 0 0-3342 {}}} CYCLES {}}
+set a(0-3342) {NAME ACC1:conc#554 TYPE CONCATENATE PAR 0-2847 XREFS 21520 LOC {1 0.267931 1 0.56084835 1 0.56084835 1 0.71982485} PREDS {{146 0 0-2871 {}} {258 0 0-3340 {}} {259 0 0-3341 {}}} SUCCS {{259 0 0-3343 {}}} CYCLES {}}
+set a(0-3343) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#190 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21521 LOC {1 0.267931 1 0.56084835 1 0.56084835 1 0.5880942270708271 1 0.7470707270708271} PREDS {{146 0 0-2871 {}} {258 0 0-3337 {}} {259 0 0-3342 {}}} SUCCS {{259 0 0-3344 {}}} CYCLES {}}
+set a(0-3344) {NAME ACC1:slc#55 TYPE READSLICE PAR 0-2847 XREFS 21522 LOC {1 0.295176925 1 0.588094275 1 0.588094275 1 0.747070775} PREDS {{146 0 0-2871 {}} {259 0 0-3343 {}}} SUCCS {{259 0 0-3345 {}}} CYCLES {}}
+set a(0-3345) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#203 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 21523 LOC {1 0.366807475 1 0.588094275 1 0.588094275 1 0.6312861701789505 1 0.7902626701789505} PREDS {{146 0 0-2871 {}} {258 0 0-3333 {}} {259 0 0-3344 {}}} SUCCS {{258 0 0-3357 {}}} CYCLES {}}
+set a(0-3346) {NAME ACC1-3:slc(acc.psp)#34 TYPE READSLICE PAR 0-2847 XREFS 21524 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7572259} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3350 {}}} CYCLES {}}
+set a(0-3347) {NAME ACC1-3:slc(acc.psp)#35 TYPE READSLICE PAR 0-2847 XREFS 21525 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7572259} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3350 {}}} CYCLES {}}
+set a(0-3348) {NAME ACC1-3:slc(acc.idiv)#31 TYPE READSLICE PAR 0-2847 XREFS 21526 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7572259} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3349 {}}} CYCLES {}}
+set a(0-3349) {NAME ACC1-3:exs#15 TYPE SIGNEXTEND PAR 0-2847 XREFS 21527 LOC {1 0.14655495 1 0.5982493999999999 1 0.5982493999999999 1 0.7572259} PREDS {{146 0 0-2871 {}} {259 0 0-3348 {}}} SUCCS {{259 0 0-3350 {}}} CYCLES {}}
+set a(0-3350) {NAME ACC1-3:conc#260 TYPE CONCATENATE PAR 0-2847 XREFS 21528 LOC {1 0.14655495 1 0.5982493999999999 1 0.5982493999999999 1 0.7572259} PREDS {{146 0 0-2871 {}} {258 0 0-3347 {}} {258 0 0-3346 {}} {259 0 0-3349 {}}} SUCCS {{258 0 0-3356 {}}} CYCLES {}}
+set a(0-3351) {NAME ACC1-3:slc(acc.idiv)#33 TYPE READSLICE PAR 0-2847 XREFS 21529 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.71644285} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3352 {}}} CYCLES {}}
+set a(0-3352) {NAME ACC1-3:exs#16 TYPE SIGNEXTEND PAR 0-2847 XREFS 21530 LOC {1 0.14655495 1 0.55746635 1 0.55746635 1 0.71644285} PREDS {{146 0 0-2871 {}} {259 0 0-3351 {}}} SUCCS {{258 0 0-3355 {}}} CYCLES {}}
+set a(0-3353) {NAME ACC1-3:slc(acc.idiv)#35 TYPE READSLICE PAR 0-2847 XREFS 21531 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.71644285} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3354 {}}} CYCLES {}}
+set a(0-3354) {NAME ACC1-3:exs#17 TYPE SIGNEXTEND PAR 0-2847 XREFS 21532 LOC {1 0.14655495 1 0.55746635 1 0.55746635 1 0.71644285} PREDS {{146 0 0-2871 {}} {259 0 0-3353 {}}} SUCCS {{259 0 0-3355 {}}} CYCLES {}}
+set a(0-3355) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#197 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21533 LOC {1 0.14655495 1 0.55746635 1 0.55746635 1 0.5982493600894753 1 0.7572258600894752} PREDS {{146 0 0-2871 {}} {258 0 0-3352 {}} {259 0 0-3354 {}}} SUCCS {{259 0 0-3356 {}}} CYCLES {}}
+set a(0-3356) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#202 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-2847 XREFS 21534 LOC {1 0.187338 1 0.5982493999999999 1 0.5982493999999999 1 0.6312861701789504 1 0.7902626701789505} PREDS {{146 0 0-2871 {}} {258 0 0-3350 {}} {259 0 0-3355 {}}} SUCCS {{259 0 0-3357 {}}} CYCLES {}}
+set a(0-3357) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#206 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 21535 LOC {1 0.409999425 1 0.631286225 1 0.631286225 1 0.669575684496936 1 0.828552184496936} PREDS {{146 0 0-2871 {}} {258 0 0-3345 {}} {259 0 0-3356 {}}} SUCCS {{258 0 0-3363 {}}} CYCLES {}}
+set a(0-3358) {NAME ACC1-3:slc(acc.psp)#54 TYPE READSLICE PAR 0-2847 XREFS 21536 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8285522249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3362 {}}} CYCLES {}}
+set a(0-3359) {NAME ACC1-3:slc(acc.psp)#55 TYPE READSLICE PAR 0-2847 XREFS 21537 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8285522249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3362 {}}} CYCLES {}}
+set a(0-3360) {NAME ACC1-3:slc(acc.psp)#56 TYPE READSLICE PAR 0-2847 XREFS 21538 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8285522249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3362 {}}} CYCLES {}}
+set a(0-3361) {NAME ACC1-3:slc(acc.psp)#47 TYPE READSLICE PAR 0-2847 XREFS 21539 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8285522249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3362 {}}} CYCLES {}}
+set a(0-3362) {NAME ACC1-3:conc#255 TYPE CONCATENATE PAR 0-2847 XREFS 21540 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.8285522249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3360 {}} {258 0 0-3359 {}} {258 0 0-3358 {}} {259 0 0-3361 {}}} SUCCS {{259 0 0-3363 {}}} CYCLES {}}
+set a(0-3363) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#209 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-2847 XREFS 21541 LOC {1 0.448288925 1 0.669575725 1 0.669575725 1 0.7174547879329679 1 0.8764312879329679} PREDS {{146 0 0-2871 {}} {258 0 0-3357 {}} {259 0 0-3362 {}}} SUCCS {{258 0 0-3394 {}}} CYCLES {}}
+set a(0-3364) {NAME ACC1-3:slc(acc.psp)#17 TYPE READSLICE PAR 0-2847 XREFS 21542 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8285522249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3367 {}}} CYCLES {}}
+set a(0-3365) {NAME ACC1-3:slc(acc.idiv)#25 TYPE READSLICE PAR 0-2847 XREFS 21543 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8285522249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3366 {}}} CYCLES {}}
+set a(0-3366) {NAME ACC1-3:exs#12 TYPE SIGNEXTEND PAR 0-2847 XREFS 21544 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.8285522249999999} PREDS {{146 0 0-2871 {}} {259 0 0-3365 {}}} SUCCS {{259 0 0-3367 {}}} CYCLES {}}
+set a(0-3367) {NAME ACC1-3:conc#226 TYPE CONCATENATE PAR 0-2847 XREFS 21545 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.8285522249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3364 {}} {259 0 0-3366 {}}} SUCCS {{259 0 0-3368 {}}} CYCLES {}}
+set a(0-3368) {NAME ACC1-3:exs#538 TYPE SIGNEXTEND PAR 0-2847 XREFS 21546 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.8285522249999999} PREDS {{146 0 0-2871 {}} {259 0 0-3367 {}}} SUCCS {{258 0 0-3393 {}}} CYCLES {}}
+set a(0-3369) {NAME ACC1-3:slc(acc.psp)#52 TYPE READSLICE PAR 0-2847 XREFS 21547 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7902627249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3372 {}}} CYCLES {}}
+set a(0-3370) {NAME ACC1-3:slc(acc.psp)#53 TYPE READSLICE PAR 0-2847 XREFS 21548 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7902627249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3372 {}}} CYCLES {}}
+set a(0-3371) {NAME ACC1-3:slc(acc.psp)#46 TYPE READSLICE PAR 0-2847 XREFS 21549 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7902627249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3372 {}}} CYCLES {}}
+set a(0-3372) {NAME ACC1-3:conc TYPE CONCATENATE PAR 0-2847 XREFS 21550 LOC {1 0.14655495 1 0.631286225 1 0.631286225 1 0.7902627249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3370 {}} {258 0 0-3369 {}} {259 0 0-3371 {}}} SUCCS {{258 0 0-3392 {}}} CYCLES {}}
+set a(0-3373) {NAME ACC1-3:slc(acc.idiv)#9 TYPE READSLICE PAR 0-2847 XREFS 21551 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7019234999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3374 {}}} CYCLES {}}
+set a(0-3374) {NAME ACC1-3:exs#4 TYPE SIGNEXTEND PAR 0-2847 XREFS 21552 LOC {1 0.14655495 1 0.542947 1 0.542947 1 0.7019234999999999} PREDS {{146 0 0-2871 {}} {259 0 0-3373 {}}} SUCCS {{258 0 0-3377 {}}} CYCLES {}}
+set a(0-3375) {NAME ACC1-3:slc(acc.idiv)#11 TYPE READSLICE PAR 0-2847 XREFS 21553 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7019234999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3376 {}}} CYCLES {}}
+set a(0-3376) {NAME ACC1-3:exs#5 TYPE SIGNEXTEND PAR 0-2847 XREFS 21554 LOC {1 0.14655495 1 0.542947 1 0.542947 1 0.7019234999999999} PREDS {{146 0 0-2871 {}} {259 0 0-3375 {}}} SUCCS {{259 0 0-3377 {}}} CYCLES {}}
+set a(0-3377) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#196 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21555 LOC {1 0.14655495 1 0.542947 1 0.542947 1 0.5837300100894752 1 0.7427065100894752} PREDS {{146 0 0-2871 {}} {258 0 0-3374 {}} {259 0 0-3376 {}}} SUCCS {{258 0 0-3391 {}}} CYCLES {}}
+set a(0-3378) {NAME ACC1-3:slc(acc.idiv)#1 TYPE READSLICE PAR 0-2847 XREFS 21556 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.695150375} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3379 {}}} CYCLES {}}
+set a(0-3379) {NAME ACC1-3:exs#496 TYPE SIGNEXTEND PAR 0-2847 XREFS 21557 LOC {1 0.14655495 1 0.536173875 1 0.536173875 1 0.695150375} PREDS {{146 0 0-2871 {}} {259 0 0-3378 {}}} SUCCS {{259 0 0-3380 {}}} CYCLES {}}
+set a(0-3380) {NAME ACC1:conc#563 TYPE CONCATENATE PAR 0-2847 XREFS 21558 LOC {1 0.14655495 1 0.536173875 1 0.536173875 1 0.695150375} PREDS {{146 0 0-2871 {}} {259 0 0-3379 {}}} SUCCS {{258 0 0-3389 {}}} CYCLES {}}
+set a(0-3381) {NAME ACC1-3:slc(acc.idiv)#3 TYPE READSLICE PAR 0-2847 XREFS 21559 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.695150375} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3382 {}}} CYCLES {}}
+set a(0-3382) {NAME ACC1-3:exs#1 TYPE SIGNEXTEND PAR 0-2847 XREFS 21560 LOC {1 0.14655495 1 0.536173875 1 0.536173875 1 0.695150375} PREDS {{146 0 0-2871 {}} {259 0 0-3381 {}}} SUCCS {{258 0 0-3388 {}}} CYCLES {}}
+set a(0-3383) {NAME ACC1-3:slc(acc.idiv)#45 TYPE READSLICE PAR 0-2847 XREFS 21561 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.695150375} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3387 {}}} CYCLES {}}
+set a(0-3384) {NAME ACC1-3:slc(acc.imod#3)#1 TYPE READSLICE PAR 0-2847 XREFS 21562 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.695150375} PREDS {{146 0 0-2871 {}} {258 0 0-3172 {}}} SUCCS {{259 0 0-3385 {}}} CYCLES {}}
+set a(0-3385) {NAME ACC1-3:not#28 TYPE NOT PAR 0-2847 XREFS 21563 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.695150375} PREDS {{146 0 0-2871 {}} {259 0 0-3384 {}}} SUCCS {{258 0 0-3387 {}}} CYCLES {}}
+set a(0-3386) {NAME ACC1-3:slc(acc.imod#3)#2 TYPE READSLICE PAR 0-2847 XREFS 21564 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.695150375} PREDS {{146 0 0-2871 {}} {258 0 0-3172 {}}} SUCCS {{259 0 0-3387 {}}} CYCLES {}}
+set a(0-3387) {NAME ACC1-3:and#1 TYPE AND PAR 0-2847 XREFS 21565 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.695150375} PREDS {{146 0 0-2871 {}} {258 0 0-3385 {}} {258 0 0-3383 {}} {259 0 0-3386 {}}} SUCCS {{259 0 0-3388 {}}} CYCLES {}}
+set a(0-3388) {NAME ACC1:conc#564 TYPE CONCATENATE PAR 0-2847 XREFS 21566 LOC {1 0.3836787 1 0.536173875 1 0.536173875 1 0.695150375} PREDS {{146 0 0-2871 {}} {258 0 0-3382 {}} {259 0 0-3387 {}}} SUCCS {{259 0 0-3389 {}}} CYCLES {}}
+set a(0-3389) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#195 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21567 LOC {1 0.3836787 1 0.536173875 1 0.536173875 1 0.5837300020708271 1 0.7427065020708271} PREDS {{146 0 0-2871 {}} {258 0 0-3380 {}} {259 0 0-3388 {}}} SUCCS {{259 0 0-3390 {}}} CYCLES {}}
+set a(0-3390) {NAME ACC1:slc#60 TYPE READSLICE PAR 0-2847 XREFS 21568 LOC {1 0.43123487499999996 1 0.58373005 1 0.58373005 1 0.74270655} PREDS {{146 0 0-2871 {}} {259 0 0-3389 {}}} SUCCS {{259 0 0-3391 {}}} CYCLES {}}
+set a(0-3391) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#201 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21569 LOC {1 0.43123487499999996 1 0.58373005 1 0.58373005 1 0.6312861770708271 1 0.7902626770708271} PREDS {{146 0 0-2871 {}} {258 0 0-3377 {}} {259 0 0-3390 {}}} SUCCS {{259 0 0-3392 {}}} CYCLES {}}
+set a(0-3392) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#205 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 21570 LOC {1 0.47879105 1 0.631286225 1 0.631286225 1 0.669575684496936 1 0.828552184496936} PREDS {{146 0 0-2871 {}} {258 0 0-3372 {}} {259 0 0-3391 {}}} SUCCS {{259 0 0-3393 {}}} CYCLES {}}
+set a(0-3393) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#208 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-2847 XREFS 21571 LOC {1 0.51708055 1 0.669575725 1 0.669575725 1 0.7174547879329679 1 0.8764312879329679} PREDS {{146 0 0-2871 {}} {258 0 0-3368 {}} {259 0 0-3392 {}}} SUCCS {{259 0 0-3394 {}}} CYCLES {}}
+set a(0-3394) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#211 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-2847 XREFS 21572 LOC {1 0.564959675 1 0.71745485 1 0.71745485 1 0.7698393027684257 1 0.9288158027684257} PREDS {{146 0 0-2871 {}} {258 0 0-3363 {}} {259 0 0-3393 {}}} SUCCS {{258 0 0-3402 {}}} CYCLES {}}
+set a(0-3395) {NAME ACC1-3:slc(acc.psp)#66 TYPE READSLICE PAR 0-2847 XREFS 21573 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.92881585} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3401 {}}} CYCLES {}}
+set a(0-3396) {NAME ACC1-3:slc(acc.psp)#67 TYPE READSLICE PAR 0-2847 XREFS 21574 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.92881585} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3401 {}}} CYCLES {}}
+set a(0-3397) {NAME ACC1-3:slc(acc.psp)#68 TYPE READSLICE PAR 0-2847 XREFS 21575 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.92881585} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3401 {}}} CYCLES {}}
+set a(0-3398) {NAME ACC1-3:slc(acc.psp)#51 TYPE READSLICE PAR 0-2847 XREFS 21576 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.92881585} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3401 {}}} CYCLES {}}
+set a(0-3399) {NAME ACC1-3:slc(acc.idiv)#27 TYPE READSLICE PAR 0-2847 XREFS 21577 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.92881585} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3400 {}}} CYCLES {}}
+set a(0-3400) {NAME ACC1-3:exs#13 TYPE SIGNEXTEND PAR 0-2847 XREFS 21578 LOC {1 0.14655495 1 0.7698393499999999 1 0.7698393499999999 1 0.92881585} PREDS {{146 0 0-2871 {}} {259 0 0-3399 {}}} SUCCS {{259 0 0-3401 {}}} CYCLES {}}
+set a(0-3401) {NAME ACC1-3:conc#263 TYPE CONCATENATE PAR 0-2847 XREFS 21579 LOC {1 0.14655495 1 0.7698393499999999 1 0.7698393499999999 1 0.92881585} PREDS {{146 0 0-2871 {}} {258 0 0-3398 {}} {258 0 0-3397 {}} {258 0 0-3396 {}} {258 0 0-3395 {}} {259 0 0-3400 {}}} SUCCS {{259 0 0-3402 {}}} CYCLES {}}
+set a(0-3402) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#213 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 21580 LOC {1 0.6173441749999999 1 0.7698393499999999 1 0.7698393499999999 1 0.8410234533364113 1 0.9999999533364113} PREDS {{146 0 0-2871 {}} {258 0 0-3394 {}} {259 0 0-3401 {}}} SUCCS {{259 0 0-3403 {}}} CYCLES {}}
+set a(0-3403) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME ACC1:acc#215 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-2847 XREFS 21581 LOC {1 0.6885283249999999 1 0.8410234999999999 1 0.8410234999999999 1 0.9205117034997776 2 0.09500765349977768} PREDS {{146 0 0-2871 {}} {258 0 0-3323 {}} {259 0 0-3402 {}}} SUCCS {{258 0 0-3615 {}}} CYCLES {}}
+set a(0-3404) {NAME ACC1-1:slc(acc.psp)#57 TYPE READSLICE PAR 0-2847 XREFS 21582 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7864166499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3409 {}}} CYCLES {}}
+set a(0-3405) {NAME ACC1-1:slc(acc.psp)#58 TYPE READSLICE PAR 0-2847 XREFS 21583 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7864166499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3409 {}}} CYCLES {}}
+set a(0-3406) {NAME ACC1-1:slc(acc.psp)#59 TYPE READSLICE PAR 0-2847 XREFS 21584 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7864166499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3409 {}}} CYCLES {}}
+set a(0-3407) {NAME ACC1-1:slc(acc.psp)#60 TYPE READSLICE PAR 0-2847 XREFS 21585 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7864166499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3409 {}}} CYCLES {}}
+set a(0-3408) {NAME ACC1-1:slc(acc.psp)#48 TYPE READSLICE PAR 0-2847 XREFS 21586 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7864166499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3409 {}}} CYCLES {}}
+set a(0-3409) {NAME ACC1-1:conc#256 TYPE CONCATENATE PAR 0-2847 XREFS 21587 LOC {1 0.14655495 1 0.641712725 1 0.641712725 1 0.7864166499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3407 {}} {258 0 0-3406 {}} {258 0 0-3405 {}} {258 0 0-3404 {}} {259 0 0-3408 {}}} SUCCS {{258 0 0-3466 {}}} CYCLES {}}
+set a(0-3410) {NAME ACC1-1:slc(acc.psp)#63 TYPE READSLICE PAR 0-2847 XREFS 21588 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.73403215} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3415 {}}} CYCLES {}}
+set a(0-3411) {NAME ACC1-1:slc(acc.psp)#64 TYPE READSLICE PAR 0-2847 XREFS 21589 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.73403215} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3415 {}}} CYCLES {}}
+set a(0-3412) {NAME ACC1-1:slc(acc.psp)#50 TYPE READSLICE PAR 0-2847 XREFS 21590 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.73403215} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3415 {}}} CYCLES {}}
+set a(0-3413) {NAME ACC1-1:slc(acc.psp)#65 TYPE READSLICE PAR 0-2847 XREFS 21591 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.73403215} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3414 {}}} CYCLES {}}
+set a(0-3414) {NAME ACC1-1:exs TYPE SIGNEXTEND PAR 0-2847 XREFS 21592 LOC {1 0.14655495 1 0.5893282249999999 1 0.5893282249999999 1 0.73403215} PREDS {{146 0 0-2871 {}} {259 0 0-3413 {}}} SUCCS {{259 0 0-3415 {}}} CYCLES {}}
+set a(0-3415) {NAME ACC1-1:conc#261 TYPE CONCATENATE PAR 0-2847 XREFS 21593 LOC {1 0.14655495 1 0.5893282249999999 1 0.5893282249999999 1 0.73403215} PREDS {{146 0 0-2871 {}} {258 0 0-3412 {}} {258 0 0-3411 {}} {258 0 0-3410 {}} {259 0 0-3414 {}}} SUCCS {{258 0 0-3465 {}}} CYCLES {}}
+set a(0-3416) {NAME ACC1-1:slc(acc.psp)#36 TYPE READSLICE PAR 0-2847 XREFS 21594 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.690830375} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3420 {}}} CYCLES {}}
+set a(0-3417) {NAME ACC1-1:slc(acc.psp)#37 TYPE READSLICE PAR 0-2847 XREFS 21595 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.690830375} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3420 {}}} CYCLES {}}
+set a(0-3418) {NAME ACC1-1:slc(acc.idiv)#29 TYPE READSLICE PAR 0-2847 XREFS 21596 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.690830375} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3419 {}}} CYCLES {}}
+set a(0-3419) {NAME ACC1-1:exs#14 TYPE SIGNEXTEND PAR 0-2847 XREFS 21597 LOC {1 0.14655495 1 0.5461264499999999 1 0.5461264499999999 1 0.690830375} PREDS {{146 0 0-2871 {}} {259 0 0-3418 {}}} SUCCS {{259 0 0-3420 {}}} CYCLES {}}
+set a(0-3420) {NAME ACC1-1:conc#265 TYPE CONCATENATE PAR 0-2847 XREFS 21598 LOC {1 0.14655495 1 0.5461264499999999 1 0.5461264499999999 1 0.690830375} PREDS {{146 0 0-2871 {}} {258 0 0-3417 {}} {258 0 0-3416 {}} {259 0 0-3419 {}}} SUCCS {{258 0 0-3464 {}}} CYCLES {}}
+set a(0-3421) {NAME ACC1-1:slc(acc.idiv)#5 TYPE READSLICE PAR 0-2847 XREFS 21599 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3422 {}}} CYCLES {}}
+set a(0-3422) {NAME ACC1-1:exs#2 TYPE SIGNEXTEND PAR 0-2847 XREFS 21600 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3421 {}}} SUCCS {{259 0 0-3423 {}}} CYCLES {}}
+set a(0-3423) {NAME ACC1:conc#576 TYPE CONCATENATE PAR 0-2847 XREFS 21601 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3422 {}}} SUCCS {{258 0 0-3431 {}}} CYCLES {}}
+set a(0-3424) {NAME ACC1-1:slc(acc.idiv)#7 TYPE READSLICE PAR 0-2847 XREFS 21602 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3425 {}}} CYCLES {}}
+set a(0-3425) {NAME ACC1-1:exs#3 TYPE SIGNEXTEND PAR 0-2847 XREFS 21603 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3424 {}}} SUCCS {{258 0 0-3430 {}}} CYCLES {}}
+set a(0-3426) {NAME ACC1-1:slc(acc.imod#3) TYPE READSLICE PAR 0-2847 XREFS 21604 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-2948 {}}} SUCCS {{258 0 0-3429 {}}} CYCLES {}}
+set a(0-3427) {NAME ACC1-1:slc(acc.idiv)#44 TYPE READSLICE PAR 0-2847 XREFS 21605 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3428 {}}} CYCLES {}}
+set a(0-3428) {NAME ACC1-1:not#27 TYPE NOT PAR 0-2847 XREFS 21606 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3427 {}}} SUCCS {{259 0 0-3429 {}}} CYCLES {}}
+set a(0-3429) {NAME ACC1-1:nand TYPE NAND PAR 0-2847 XREFS 21607 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-3426 {}} {259 0 0-3428 {}}} SUCCS {{259 0 0-3430 {}}} CYCLES {}}
+set a(0-3430) {NAME ACC1:conc#577 TYPE CONCATENATE PAR 0-2847 XREFS 21608 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-3425 {}} {259 0 0-3429 {}}} SUCCS {{259 0 0-3431 {}}} CYCLES {}}
+set a(0-3431) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#221 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21609 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.5899270770708271} PREDS {{146 0 0-2871 {}} {258 0 0-3423 {}} {259 0 0-3430 {}}} SUCCS {{259 0 0-3432 {}}} CYCLES {}}
+set a(0-3432) {NAME ACC1:slc#66 TYPE READSLICE PAR 0-2847 XREFS 21610 LOC {1 0.43123487499999996 1 0.4452232 1 0.4452232 1 0.589927125} PREDS {{146 0 0-2871 {}} {259 0 0-3431 {}}} SUCCS {{258 0 0-3443 {}}} CYCLES {}}
+set a(0-3433) {NAME ACC1-1:slc(acc.idiv)#15 TYPE READSLICE PAR 0-2847 XREFS 21611 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3434 {}}} CYCLES {}}
+set a(0-3434) {NAME ACC1-1:exs#7 TYPE SIGNEXTEND PAR 0-2847 XREFS 21612 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3433 {}}} SUCCS {{259 0 0-3435 {}}} CYCLES {}}
+set a(0-3435) {NAME ACC1:conc#574 TYPE CONCATENATE PAR 0-2847 XREFS 21613 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3434 {}}} SUCCS {{258 0 0-3441 {}}} CYCLES {}}
+set a(0-3436) {NAME ACC1-1:slc(acc.idiv)#17 TYPE READSLICE PAR 0-2847 XREFS 21614 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3437 {}}} CYCLES {}}
+set a(0-3437) {NAME ACC1-1:exs#8 TYPE SIGNEXTEND PAR 0-2847 XREFS 21615 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3436 {}}} SUCCS {{258 0 0-3440 {}}} CYCLES {}}
+set a(0-3438) {NAME ACC1-1:slc(acc.imod#2)#12 TYPE READSLICE PAR 0-2847 XREFS 21616 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-2939 {}}} SUCCS {{259 0 0-3439 {}}} CYCLES {}}
+set a(0-3439) {NAME ACC1-1:not#146 TYPE NOT PAR 0-2847 XREFS 21617 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3438 {}}} SUCCS {{259 0 0-3440 {}}} CYCLES {}}
+set a(0-3440) {NAME ACC1:conc#575 TYPE CONCATENATE PAR 0-2847 XREFS 21618 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-3437 {}} {259 0 0-3439 {}}} SUCCS {{259 0 0-3441 {}}} CYCLES {}}
+set a(0-3441) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#220 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21619 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.5899270770708271} PREDS {{146 0 0-2871 {}} {258 0 0-3435 {}} {259 0 0-3440 {}}} SUCCS {{259 0 0-3442 {}}} CYCLES {}}
+set a(0-3442) {NAME ACC1:slc#65 TYPE READSLICE PAR 0-2847 XREFS 21620 LOC {1 0.40398894999999996 1 0.4452232 1 0.4452232 1 0.589927125} PREDS {{146 0 0-2871 {}} {259 0 0-3441 {}}} SUCCS {{259 0 0-3443 {}}} CYCLES {}}
+set a(0-3443) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#227 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21621 LOC {1 0.43123487499999996 1 0.4452232 1 0.4452232 1 0.49277932707082717 1 0.6374832520708271} PREDS {{146 0 0-2871 {}} {258 0 0-3432 {}} {259 0 0-3442 {}}} SUCCS {{258 0 0-3463 {}}} CYCLES {}}
+set a(0-3444) {NAME ACC1-1:slc(acc.idiv)#13 TYPE READSLICE PAR 0-2847 XREFS 21622 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3445 {}}} CYCLES {}}
+set a(0-3445) {NAME ACC1-1:exs#6 TYPE SIGNEXTEND PAR 0-2847 XREFS 21623 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3444 {}}} SUCCS {{259 0 0-3446 {}}} CYCLES {}}
+set a(0-3446) {NAME ACC1:conc#572 TYPE CONCATENATE PAR 0-2847 XREFS 21624 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3445 {}}} SUCCS {{258 0 0-3451 {}}} CYCLES {}}
+set a(0-3447) {NAME ACC1-1:slc(acc.idiv)#23 TYPE READSLICE PAR 0-2847 XREFS 21625 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3448 {}}} CYCLES {}}
+set a(0-3448) {NAME ACC1-1:exs#11 TYPE SIGNEXTEND PAR 0-2847 XREFS 21626 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3447 {}}} SUCCS {{258 0 0-3450 {}}} CYCLES {}}
+set a(0-3449) {NAME ACC1-1:slc(acc.imod#2)#11 TYPE READSLICE PAR 0-2847 XREFS 21627 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-2939 {}}} SUCCS {{259 0 0-3450 {}}} CYCLES {}}
+set a(0-3450) {NAME ACC1:conc#573 TYPE CONCATENATE PAR 0-2847 XREFS 21628 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-3448 {}} {259 0 0-3449 {}}} SUCCS {{259 0 0-3451 {}}} CYCLES {}}
+set a(0-3451) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#219 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21629 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.5899270770708271} PREDS {{146 0 0-2871 {}} {258 0 0-3446 {}} {259 0 0-3450 {}}} SUCCS {{259 0 0-3452 {}}} CYCLES {}}
+set a(0-3452) {NAME ACC1:slc#64 TYPE READSLICE PAR 0-2847 XREFS 21630 LOC {1 0.40398894999999996 1 0.4452232 1 0.4452232 1 0.589927125} PREDS {{146 0 0-2871 {}} {259 0 0-3451 {}}} SUCCS {{258 0 0-3462 {}}} CYCLES {}}
+set a(0-3453) {NAME ACC1-1:slc(acc.idiv)#19 TYPE READSLICE PAR 0-2847 XREFS 21631 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3454 {}}} CYCLES {}}
+set a(0-3454) {NAME ACC1-1:exs#9 TYPE SIGNEXTEND PAR 0-2847 XREFS 21632 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3453 {}}} SUCCS {{259 0 0-3455 {}}} CYCLES {}}
+set a(0-3455) {NAME ACC1:conc#570 TYPE CONCATENATE PAR 0-2847 XREFS 21633 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3454 {}}} SUCCS {{258 0 0-3460 {}}} CYCLES {}}
+set a(0-3456) {NAME ACC1-1:slc(acc.idiv)#21 TYPE READSLICE PAR 0-2847 XREFS 21634 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3457 {}}} CYCLES {}}
+set a(0-3457) {NAME ACC1-1:exs#10 TYPE SIGNEXTEND PAR 0-2847 XREFS 21635 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {259 0 0-3456 {}}} SUCCS {{258 0 0-3459 {}}} CYCLES {}}
+set a(0-3458) {NAME ACC1-1:slc(ACC1:acc#107.psp)#9 TYPE READSLICE PAR 0-2847 XREFS 21636 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-2921 {}}} SUCCS {{259 0 0-3459 {}}} CYCLES {}}
+set a(0-3459) {NAME ACC1:conc#571 TYPE CONCATENATE PAR 0-2847 XREFS 21637 LOC {1 0.267931 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-2871 {}} {258 0 0-3457 {}} {259 0 0-3458 {}}} SUCCS {{259 0 0-3460 {}}} CYCLES {}}
+set a(0-3460) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#218 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21638 LOC {1 0.267931 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.5899270770708271} PREDS {{146 0 0-2871 {}} {258 0 0-3455 {}} {259 0 0-3459 {}}} SUCCS {{259 0 0-3461 {}}} CYCLES {}}
+set a(0-3461) {NAME ACC1:slc#63 TYPE READSLICE PAR 0-2847 XREFS 21639 LOC {1 0.315487175 1 0.4452232 1 0.4452232 1 0.589927125} PREDS {{146 0 0-2871 {}} {259 0 0-3460 {}}} SUCCS {{259 0 0-3462 {}}} CYCLES {}}
+set a(0-3462) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#226 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21640 LOC {1 0.40398894999999996 1 0.4452232 1 0.4452232 1 0.49277932707082717 1 0.6374832520708271} PREDS {{146 0 0-2871 {}} {258 0 0-3452 {}} {259 0 0-3461 {}}} SUCCS {{259 0 0-3463 {}}} CYCLES {}}
+set a(0-3463) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#231 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-2847 XREFS 21641 LOC {1 0.47879105 1 0.49277937499999996 1 0.49277937499999996 1 0.5461263951789505 1 0.6908303201789505} PREDS {{146 0 0-2871 {}} {258 0 0-3443 {}} {259 0 0-3462 {}}} SUCCS {{259 0 0-3464 {}}} CYCLES {}}
+set a(0-3464) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME ACC1:acc#234 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 21642 LOC {1 0.532138125 1 0.5461264499999999 1 0.5461264499999999 1 0.5893281734103023 1 0.7340320984103024} PREDS {{146 0 0-2871 {}} {258 0 0-3420 {}} {259 0 0-3463 {}}} SUCCS {{259 0 0-3465 {}}} CYCLES {}}
+set a(0-3465) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#237 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-2847 XREFS 21643 LOC {1 0.5753399 1 0.5893282249999999 1 0.5893282249999999 1 0.6417126777684257 1 0.7864166027684257} PREDS {{146 0 0-2871 {}} {258 0 0-3415 {}} {259 0 0-3464 {}}} SUCCS {{259 0 0-3466 {}}} CYCLES {}}
+set a(0-3466) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,0,10) AREA_SCORE 10.25 QUANTITY 5 NAME ACC1:acc#239 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-2847 XREFS 21644 LOC {1 0.6277244 1 0.641712725 1 0.641712725 1 0.71889620686502 1 0.8636001318650199} PREDS {{146 0 0-2871 {}} {258 0 0-3409 {}} {259 0 0-3465 {}}} SUCCS {{258 0 0-3538 {}}} CYCLES {}}
+set a(0-3467) {NAME ACC1-1:slc(acc.psp)#29 TYPE READSLICE PAR 0-2847 XREFS 21645 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.60661385} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3468 {}}} CYCLES {}}
+set a(0-3468) {NAME ACC1:conc#565 TYPE CONCATENATE PAR 0-2847 XREFS 21646 LOC {1 0.14655495 1 0.461909925 1 0.461909925 1 0.60661385} PREDS {{146 0 0-2871 {}} {259 0 0-3467 {}}} SUCCS {{259 0 0-3469 {}}} CYCLES {}}
+set a(0-3469) {NAME ACC1:conc#566 TYPE CONCATENATE PAR 0-2847 XREFS 21647 LOC {1 0.14655495 1 0.461909925 1 0.461909925 1 0.60661385} PREDS {{146 0 0-2871 {}} {259 0 0-3468 {}}} SUCCS {{258 0 0-3473 {}}} CYCLES {}}
+set a(0-3470) {NAME ACC1-1:slc(ACC1:acc#107.psp)#10 TYPE READSLICE PAR 0-2847 XREFS 21648 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.60661385} PREDS {{146 0 0-2871 {}} {258 0 0-2921 {}}} SUCCS {{258 0 0-3472 {}}} CYCLES {}}
+set a(0-3471) {NAME ACC1-1:slc(acc.psp)#30 TYPE READSLICE PAR 0-2847 XREFS 21649 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.60661385} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3472 {}}} CYCLES {}}
+set a(0-3472) {NAME ACC1:conc#567 TYPE CONCATENATE PAR 0-2847 XREFS 21650 LOC {1 0.267931 1 0.461909925 1 0.461909925 1 0.60661385} PREDS {{146 0 0-2871 {}} {258 0 0-3470 {}} {259 0 0-3471 {}}} SUCCS {{259 0 0-3473 {}}} CYCLES {}}
+set a(0-3473) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#216 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-2847 XREFS 21651 LOC {1 0.267931 1 0.461909925 1 0.461909925 1 0.49953050202417165 1 0.6442344270241717} PREDS {{146 0 0-2871 {}} {258 0 0-3469 {}} {259 0 0-3472 {}}} SUCCS {{259 0 0-3474 {}}} CYCLES {}}
+set a(0-3474) {NAME ACC1:slc#61 TYPE READSLICE PAR 0-2847 XREFS 21652 LOC {1 0.305551625 1 0.49953054999999996 1 0.49953054999999996 1 0.644234475} PREDS {{146 0 0-2871 {}} {259 0 0-3473 {}}} SUCCS {{258 0 0-3476 {}}} CYCLES {}}
+set a(0-3475) {NAME ACC1-1:slc(ACC1:acc#116.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21653 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.644234475} PREDS {{146 0 0-2871 {}} {258 0 0-2932 {}}} SUCCS {{259 0 0-3476 {}}} CYCLES {}}
+set a(0-3476) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#225 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-2847 XREFS 21654 LOC {1 0.32918685 1 0.49953054999999996 1 0.49953054999999996 1 0.5371511270241717 1 0.6818550520241716} PREDS {{146 0 0-2871 {}} {258 0 0-3474 {}} {259 0 0-3475 {}}} SUCCS {{258 0 0-3488 {}}} CYCLES {}}
+set a(0-3477) {NAME ACC1-1:slc(acc.psp)#31 TYPE READSLICE PAR 0-2847 XREFS 21655 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6546091749999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3479 {}}} CYCLES {}}
+set a(0-3478) {NAME ACC1-1:slc(acc.psp)#32 TYPE READSLICE PAR 0-2847 XREFS 21656 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6546091749999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3479 {}}} CYCLES {}}
+set a(0-3479) {NAME ACC1-1:conc#258 TYPE CONCATENATE PAR 0-2847 XREFS 21657 LOC {1 0.14655495 1 0.50990525 1 0.50990525 1 0.6546091749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3477 {}} {259 0 0-3478 {}}} SUCCS {{259 0 0-3480 {}}} CYCLES {}}
+set a(0-3480) {NAME ACC1:conc#568 TYPE CONCATENATE PAR 0-2847 XREFS 21658 LOC {1 0.14655495 1 0.50990525 1 0.50990525 1 0.6546091749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3479 {}}} SUCCS {{258 0 0-3486 {}}} CYCLES {}}
+set a(0-3481) {NAME ACC1-1:slc(ACC1:acc#107.psp)#11 TYPE READSLICE PAR 0-2847 XREFS 21659 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.6546091749999999} PREDS {{146 0 0-2871 {}} {258 0 0-2921 {}}} SUCCS {{258 0 0-3483 {}}} CYCLES {}}
+set a(0-3482) {NAME ACC1-1:slc(acc.psp)#33 TYPE READSLICE PAR 0-2847 XREFS 21660 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6546091749999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3483 {}}} CYCLES {}}
+set a(0-3483) {NAME ACC1-1:conc#259 TYPE CONCATENATE PAR 0-2847 XREFS 21661 LOC {1 0.267931 1 0.50990525 1 0.50990525 1 0.6546091749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3481 {}} {259 0 0-3482 {}}} SUCCS {{258 0 0-3485 {}}} CYCLES {}}
+set a(0-3484) {NAME ACC1-1:slc(ACC1:acc#107.psp)#8 TYPE READSLICE PAR 0-2847 XREFS 21662 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.6546091749999999} PREDS {{146 0 0-2871 {}} {258 0 0-2921 {}}} SUCCS {{259 0 0-3485 {}}} CYCLES {}}
+set a(0-3485) {NAME ACC1:conc#569 TYPE CONCATENATE PAR 0-2847 XREFS 21663 LOC {1 0.267931 1 0.50990525 1 0.50990525 1 0.6546091749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3483 {}} {259 0 0-3484 {}}} SUCCS {{259 0 0-3486 {}}} CYCLES {}}
+set a(0-3486) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#217 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21664 LOC {1 0.267931 1 0.50990525 1 0.50990525 1 0.5371511270708271 1 0.6818550520708271} PREDS {{146 0 0-2871 {}} {258 0 0-3480 {}} {259 0 0-3485 {}}} SUCCS {{259 0 0-3487 {}}} CYCLES {}}
+set a(0-3487) {NAME ACC1:slc#62 TYPE READSLICE PAR 0-2847 XREFS 21665 LOC {1 0.295176925 1 0.537151175 1 0.537151175 1 0.6818550999999999} PREDS {{146 0 0-2871 {}} {259 0 0-3486 {}}} SUCCS {{259 0 0-3488 {}}} CYCLES {}}
+set a(0-3488) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#230 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 21666 LOC {1 0.366807475 1 0.537151175 1 0.537151175 1 0.5803430701789505 1 0.7250469951789504} PREDS {{146 0 0-2871 {}} {258 0 0-3476 {}} {259 0 0-3487 {}}} SUCCS {{258 0 0-3500 {}}} CYCLES {}}
+set a(0-3489) {NAME ACC1-1:slc(acc.psp)#34 TYPE READSLICE PAR 0-2847 XREFS 21667 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.692010225} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3493 {}}} CYCLES {}}
+set a(0-3490) {NAME ACC1-1:slc(acc.psp)#35 TYPE READSLICE PAR 0-2847 XREFS 21668 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.692010225} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3493 {}}} CYCLES {}}
+set a(0-3491) {NAME ACC1-1:slc(acc.idiv)#31 TYPE READSLICE PAR 0-2847 XREFS 21669 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.692010225} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3492 {}}} CYCLES {}}
+set a(0-3492) {NAME ACC1-1:exs#15 TYPE SIGNEXTEND PAR 0-2847 XREFS 21670 LOC {1 0.14655495 1 0.5473063 1 0.5473063 1 0.692010225} PREDS {{146 0 0-2871 {}} {259 0 0-3491 {}}} SUCCS {{259 0 0-3493 {}}} CYCLES {}}
+set a(0-3493) {NAME ACC1-1:conc#260 TYPE CONCATENATE PAR 0-2847 XREFS 21671 LOC {1 0.14655495 1 0.5473063 1 0.5473063 1 0.692010225} PREDS {{146 0 0-2871 {}} {258 0 0-3490 {}} {258 0 0-3489 {}} {259 0 0-3492 {}}} SUCCS {{258 0 0-3499 {}}} CYCLES {}}
+set a(0-3494) {NAME ACC1-1:slc(acc.idiv)#33 TYPE READSLICE PAR 0-2847 XREFS 21672 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6512271749999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3495 {}}} CYCLES {}}
+set a(0-3495) {NAME ACC1-1:exs#16 TYPE SIGNEXTEND PAR 0-2847 XREFS 21673 LOC {1 0.14655495 1 0.50652325 1 0.50652325 1 0.6512271749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3494 {}}} SUCCS {{258 0 0-3498 {}}} CYCLES {}}
+set a(0-3496) {NAME ACC1-1:slc(acc.idiv)#35 TYPE READSLICE PAR 0-2847 XREFS 21674 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6512271749999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3497 {}}} CYCLES {}}
+set a(0-3497) {NAME ACC1-1:exs#17 TYPE SIGNEXTEND PAR 0-2847 XREFS 21675 LOC {1 0.14655495 1 0.50652325 1 0.50652325 1 0.6512271749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3496 {}}} SUCCS {{259 0 0-3498 {}}} CYCLES {}}
+set a(0-3498) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#224 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21676 LOC {1 0.14655495 1 0.50652325 1 0.50652325 1 0.5473062600894752 1 0.6920101850894752} PREDS {{146 0 0-2871 {}} {258 0 0-3495 {}} {259 0 0-3497 {}}} SUCCS {{259 0 0-3499 {}}} CYCLES {}}
+set a(0-3499) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#229 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-2847 XREFS 21677 LOC {1 0.187338 1 0.5473063 1 0.5473063 1 0.5803430701789505 1 0.7250469951789504} PREDS {{146 0 0-2871 {}} {258 0 0-3493 {}} {259 0 0-3498 {}}} SUCCS {{259 0 0-3500 {}}} CYCLES {}}
+set a(0-3500) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#233 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 21678 LOC {1 0.409999425 1 0.580343125 1 0.580343125 1 0.618632584496936 1 0.763336509496936} PREDS {{146 0 0-2871 {}} {258 0 0-3488 {}} {259 0 0-3499 {}}} SUCCS {{258 0 0-3506 {}}} CYCLES {}}
+set a(0-3501) {NAME ACC1-1:slc(acc.psp)#54 TYPE READSLICE PAR 0-2847 XREFS 21679 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.76333655} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3505 {}}} CYCLES {}}
+set a(0-3502) {NAME ACC1-1:slc(acc.psp)#55 TYPE READSLICE PAR 0-2847 XREFS 21680 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.76333655} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3505 {}}} CYCLES {}}
+set a(0-3503) {NAME ACC1-1:slc(acc.psp)#56 TYPE READSLICE PAR 0-2847 XREFS 21681 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.76333655} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3505 {}}} CYCLES {}}
+set a(0-3504) {NAME ACC1-1:slc(acc.psp)#47 TYPE READSLICE PAR 0-2847 XREFS 21682 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.76333655} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3505 {}}} CYCLES {}}
+set a(0-3505) {NAME ACC1-1:conc#255 TYPE CONCATENATE PAR 0-2847 XREFS 21683 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.76333655} PREDS {{146 0 0-2871 {}} {258 0 0-3503 {}} {258 0 0-3502 {}} {258 0 0-3501 {}} {259 0 0-3504 {}}} SUCCS {{259 0 0-3506 {}}} CYCLES {}}
+set a(0-3506) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#236 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-2847 XREFS 21684 LOC {1 0.448288925 1 0.6186326249999999 1 0.6186326249999999 1 0.6665116879329679 1 0.811215612932968} PREDS {{146 0 0-2871 {}} {258 0 0-3500 {}} {259 0 0-3505 {}}} SUCCS {{258 0 0-3537 {}}} CYCLES {}}
+set a(0-3507) {NAME ACC1-1:slc(acc.psp)#17 TYPE READSLICE PAR 0-2847 XREFS 21685 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.76333655} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3510 {}}} CYCLES {}}
+set a(0-3508) {NAME ACC1-1:slc(acc.idiv)#25 TYPE READSLICE PAR 0-2847 XREFS 21686 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.76333655} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3509 {}}} CYCLES {}}
+set a(0-3509) {NAME ACC1-1:exs#12 TYPE SIGNEXTEND PAR 0-2847 XREFS 21687 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.76333655} PREDS {{146 0 0-2871 {}} {259 0 0-3508 {}}} SUCCS {{259 0 0-3510 {}}} CYCLES {}}
+set a(0-3510) {NAME ACC1-1:conc#226 TYPE CONCATENATE PAR 0-2847 XREFS 21688 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.76333655} PREDS {{146 0 0-2871 {}} {258 0 0-3507 {}} {259 0 0-3509 {}}} SUCCS {{259 0 0-3511 {}}} CYCLES {}}
+set a(0-3511) {NAME ACC1-1:exs#538 TYPE SIGNEXTEND PAR 0-2847 XREFS 21689 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.76333655} PREDS {{146 0 0-2871 {}} {259 0 0-3510 {}}} SUCCS {{258 0 0-3536 {}}} CYCLES {}}
+set a(0-3512) {NAME ACC1-1:slc(acc.psp)#52 TYPE READSLICE PAR 0-2847 XREFS 21690 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7250470499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3515 {}}} CYCLES {}}
+set a(0-3513) {NAME ACC1-1:slc(acc.psp)#53 TYPE READSLICE PAR 0-2847 XREFS 21691 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7250470499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3515 {}}} CYCLES {}}
+set a(0-3514) {NAME ACC1-1:slc(acc.psp)#46 TYPE READSLICE PAR 0-2847 XREFS 21692 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7250470499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3515 {}}} CYCLES {}}
+set a(0-3515) {NAME ACC1-1:conc TYPE CONCATENATE PAR 0-2847 XREFS 21693 LOC {1 0.14655495 1 0.580343125 1 0.580343125 1 0.7250470499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3513 {}} {258 0 0-3512 {}} {259 0 0-3514 {}}} SUCCS {{258 0 0-3535 {}}} CYCLES {}}
+set a(0-3516) {NAME ACC1-1:slc(acc.idiv)#9 TYPE READSLICE PAR 0-2847 XREFS 21694 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.636707825} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3517 {}}} CYCLES {}}
+set a(0-3517) {NAME ACC1-1:exs#4 TYPE SIGNEXTEND PAR 0-2847 XREFS 21695 LOC {1 0.14655495 1 0.4920039 1 0.4920039 1 0.636707825} PREDS {{146 0 0-2871 {}} {259 0 0-3516 {}}} SUCCS {{258 0 0-3520 {}}} CYCLES {}}
+set a(0-3518) {NAME ACC1-1:slc(acc.idiv)#11 TYPE READSLICE PAR 0-2847 XREFS 21696 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.636707825} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3519 {}}} CYCLES {}}
+set a(0-3519) {NAME ACC1-1:exs#5 TYPE SIGNEXTEND PAR 0-2847 XREFS 21697 LOC {1 0.14655495 1 0.4920039 1 0.4920039 1 0.636707825} PREDS {{146 0 0-2871 {}} {259 0 0-3518 {}}} SUCCS {{259 0 0-3520 {}}} CYCLES {}}
+set a(0-3520) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#223 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21698 LOC {1 0.14655495 1 0.4920039 1 0.4920039 1 0.5327869100894752 1 0.6774908350894753} PREDS {{146 0 0-2871 {}} {258 0 0-3517 {}} {259 0 0-3519 {}}} SUCCS {{258 0 0-3534 {}}} CYCLES {}}
+set a(0-3521) {NAME ACC1-1:slc(acc.idiv)#1 TYPE READSLICE PAR 0-2847 XREFS 21699 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6299347} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3522 {}}} CYCLES {}}
+set a(0-3522) {NAME ACC1-1:exs#496 TYPE SIGNEXTEND PAR 0-2847 XREFS 21700 LOC {1 0.14655495 1 0.485230775 1 0.485230775 1 0.6299347} PREDS {{146 0 0-2871 {}} {259 0 0-3521 {}}} SUCCS {{259 0 0-3523 {}}} CYCLES {}}
+set a(0-3523) {NAME ACC1:conc#578 TYPE CONCATENATE PAR 0-2847 XREFS 21701 LOC {1 0.14655495 1 0.485230775 1 0.485230775 1 0.6299347} PREDS {{146 0 0-2871 {}} {259 0 0-3522 {}}} SUCCS {{258 0 0-3532 {}}} CYCLES {}}
+set a(0-3524) {NAME ACC1-1:slc(acc.idiv)#3 TYPE READSLICE PAR 0-2847 XREFS 21702 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6299347} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3525 {}}} CYCLES {}}
+set a(0-3525) {NAME ACC1-1:exs#1 TYPE SIGNEXTEND PAR 0-2847 XREFS 21703 LOC {1 0.14655495 1 0.485230775 1 0.485230775 1 0.6299347} PREDS {{146 0 0-2871 {}} {259 0 0-3524 {}}} SUCCS {{258 0 0-3531 {}}} CYCLES {}}
+set a(0-3526) {NAME ACC1-1:slc(acc.idiv)#45 TYPE READSLICE PAR 0-2847 XREFS 21704 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6299347} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3530 {}}} CYCLES {}}
+set a(0-3527) {NAME ACC1-1:slc(acc.imod#3)#1 TYPE READSLICE PAR 0-2847 XREFS 21705 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.6299347} PREDS {{146 0 0-2871 {}} {258 0 0-2948 {}}} SUCCS {{259 0 0-3528 {}}} CYCLES {}}
+set a(0-3528) {NAME ACC1-1:not#28 TYPE NOT PAR 0-2847 XREFS 21706 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.6299347} PREDS {{146 0 0-2871 {}} {259 0 0-3527 {}}} SUCCS {{258 0 0-3530 {}}} CYCLES {}}
+set a(0-3529) {NAME ACC1-1:slc(acc.imod#3)#2 TYPE READSLICE PAR 0-2847 XREFS 21707 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.6299347} PREDS {{146 0 0-2871 {}} {258 0 0-2948 {}}} SUCCS {{259 0 0-3530 {}}} CYCLES {}}
+set a(0-3530) {NAME ACC1-1:and#1 TYPE AND PAR 0-2847 XREFS 21708 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.6299347} PREDS {{146 0 0-2871 {}} {258 0 0-3528 {}} {258 0 0-3526 {}} {259 0 0-3529 {}}} SUCCS {{259 0 0-3531 {}}} CYCLES {}}
+set a(0-3531) {NAME ACC1:conc#579 TYPE CONCATENATE PAR 0-2847 XREFS 21709 LOC {1 0.3836787 1 0.485230775 1 0.485230775 1 0.6299347} PREDS {{146 0 0-2871 {}} {258 0 0-3525 {}} {259 0 0-3530 {}}} SUCCS {{259 0 0-3532 {}}} CYCLES {}}
+set a(0-3532) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#222 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21710 LOC {1 0.3836787 1 0.485230775 1 0.485230775 1 0.5327869020708271 1 0.6774908270708271} PREDS {{146 0 0-2871 {}} {258 0 0-3523 {}} {259 0 0-3531 {}}} SUCCS {{259 0 0-3533 {}}} CYCLES {}}
+set a(0-3533) {NAME ACC1:slc#67 TYPE READSLICE PAR 0-2847 XREFS 21711 LOC {1 0.43123487499999996 1 0.53278695 1 0.53278695 1 0.6774908749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3532 {}}} SUCCS {{259 0 0-3534 {}}} CYCLES {}}
+set a(0-3534) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#228 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21712 LOC {1 0.43123487499999996 1 0.53278695 1 0.53278695 1 0.5803430770708271 1 0.7250470020708271} PREDS {{146 0 0-2871 {}} {258 0 0-3520 {}} {259 0 0-3533 {}}} SUCCS {{259 0 0-3535 {}}} CYCLES {}}
+set a(0-3535) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#232 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 21713 LOC {1 0.47879105 1 0.580343125 1 0.580343125 1 0.618632584496936 1 0.763336509496936} PREDS {{146 0 0-2871 {}} {258 0 0-3515 {}} {259 0 0-3534 {}}} SUCCS {{259 0 0-3536 {}}} CYCLES {}}
+set a(0-3536) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#235 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-2847 XREFS 21714 LOC {1 0.51708055 1 0.6186326249999999 1 0.6186326249999999 1 0.6665116879329679 1 0.811215612932968} PREDS {{146 0 0-2871 {}} {258 0 0-3511 {}} {259 0 0-3535 {}}} SUCCS {{259 0 0-3537 {}}} CYCLES {}}
+set a(0-3537) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#238 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-2847 XREFS 21715 LOC {1 0.564959675 1 0.66651175 1 0.66651175 1 0.7188962027684257 1 0.8636001277684257} PREDS {{146 0 0-2871 {}} {258 0 0-3506 {}} {259 0 0-3536 {}}} SUCCS {{259 0 0-3538 {}}} CYCLES {}}
+set a(0-3538) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#241 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 21716 LOC {1 0.704907925 1 0.71889625 1 0.71889625 1 0.7900803533364114 1 0.9347842783364113} PREDS {{146 0 0-2871 {}} {258 0 0-3466 {}} {259 0 0-3537 {}}} SUCCS {{258 0 0-3550 {}}} CYCLES {}}
+set a(0-3539) {NAME ACC1-1:slc(acc.psp)#62 TYPE READSLICE PAR 0-2847 XREFS 21717 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3541 {}}} CYCLES {}}
+set a(0-3540) {NAME ACC1-1:slc(acc.psp)#49 TYPE READSLICE PAR 0-2847 XREFS 21718 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3541 {}}} CYCLES {}}
+set a(0-3541) {NAME ACC1-1:conc#257 TYPE CONCATENATE PAR 0-2847 XREFS 21719 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.8534450499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3539 {}} {259 0 0-3540 {}}} SUCCS {{258 0 0-3549 {}}} CYCLES {}}
+set a(0-3542) {NAME ACC1-1:slc(acc.psp)#66 TYPE READSLICE PAR 0-2847 XREFS 21720 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3548 {}}} CYCLES {}}
+set a(0-3543) {NAME ACC1-1:slc(acc.psp)#67 TYPE READSLICE PAR 0-2847 XREFS 21721 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3548 {}}} CYCLES {}}
+set a(0-3544) {NAME ACC1-1:slc(acc.psp)#68 TYPE READSLICE PAR 0-2847 XREFS 21722 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3548 {}}} CYCLES {}}
+set a(0-3545) {NAME ACC1-1:slc(acc.psp)#51 TYPE READSLICE PAR 0-2847 XREFS 21723 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{258 0 0-3548 {}}} CYCLES {}}
+set a(0-3546) {NAME ACC1-1:slc(acc.idiv)#27 TYPE READSLICE PAR 0-2847 XREFS 21724 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-2871 {}} {258 0 0-2881 {}}} SUCCS {{259 0 0-3547 {}}} CYCLES {}}
+set a(0-3547) {NAME ACC1-1:exs#13 TYPE SIGNEXTEND PAR 0-2847 XREFS 21725 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.8534450499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3546 {}}} SUCCS {{259 0 0-3548 {}}} CYCLES {}}
+set a(0-3548) {NAME ACC1-1:conc#263 TYPE CONCATENATE PAR 0-2847 XREFS 21726 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.8534450499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3545 {}} {258 0 0-3544 {}} {258 0 0-3543 {}} {258 0 0-3542 {}} {259 0 0-3547 {}}} SUCCS {{259 0 0-3549 {}}} CYCLES {}}
+set a(0-3549) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,11) AREA_SCORE 11.24 QUANTITY 2 NAME ACC1:acc#240 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-2847 XREFS 21727 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.7900803533364112 1 0.9347842783364112} PREDS {{146 0 0-2871 {}} {258 0 0-3541 {}} {259 0 0-3548 {}}} SUCCS {{259 0 0-3550 {}}} CYCLES {}}
+set a(0-3550) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,13) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1-1:acc#122 TYPE ACCU DELAY {1.04 ns} LIBRARY_DELAY {1.04 ns} PAR 0-2847 XREFS 21728 LOC {1 0.776092075 1 0.7900804 1 0.7900804 1 0.8552960313734284 1 0.9999999563734283} PREDS {{146 0 0-2871 {}} {258 0 0-3538 {}} {259 0 0-3549 {}}} SUCCS {{258 0 0-3614 {}}} CYCLES {}}
+set a(0-3551) {NAME ACC1-3:slc(acc.psp)#57 TYPE READSLICE PAR 0-2847 XREFS 21729 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.922816475} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3556 {}}} CYCLES {}}
+set a(0-3552) {NAME ACC1-3:slc(acc.psp)#58 TYPE READSLICE PAR 0-2847 XREFS 21730 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.922816475} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3556 {}}} CYCLES {}}
+set a(0-3553) {NAME ACC1-3:slc(acc.psp)#59 TYPE READSLICE PAR 0-2847 XREFS 21731 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.922816475} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3556 {}}} CYCLES {}}
+set a(0-3554) {NAME ACC1-3:slc(acc.psp)#60 TYPE READSLICE PAR 0-2847 XREFS 21732 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.922816475} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3556 {}}} CYCLES {}}
+set a(0-3555) {NAME ACC1-3:slc(acc.psp)#48 TYPE READSLICE PAR 0-2847 XREFS 21733 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.922816475} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3556 {}}} CYCLES {}}
+set a(0-3556) {NAME ACC1-3:conc#256 TYPE CONCATENATE PAR 0-2847 XREFS 21734 LOC {1 0.14655495 1 0.77811255 1 0.77811255 1 0.922816475} PREDS {{146 0 0-2871 {}} {258 0 0-3554 {}} {258 0 0-3553 {}} {258 0 0-3552 {}} {258 0 0-3551 {}} {259 0 0-3555 {}}} SUCCS {{258 0 0-3613 {}}} CYCLES {}}
+set a(0-3557) {NAME ACC1-3:slc(acc.psp)#63 TYPE READSLICE PAR 0-2847 XREFS 21735 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8704319749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3562 {}}} CYCLES {}}
+set a(0-3558) {NAME ACC1-3:slc(acc.psp)#64 TYPE READSLICE PAR 0-2847 XREFS 21736 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8704319749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3562 {}}} CYCLES {}}
+set a(0-3559) {NAME ACC1-3:slc(acc.psp)#50 TYPE READSLICE PAR 0-2847 XREFS 21737 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8704319749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3562 {}}} CYCLES {}}
+set a(0-3560) {NAME ACC1-3:slc(acc.psp)#65 TYPE READSLICE PAR 0-2847 XREFS 21738 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8704319749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3561 {}}} CYCLES {}}
+set a(0-3561) {NAME ACC1-3:exs TYPE SIGNEXTEND PAR 0-2847 XREFS 21739 LOC {1 0.14655495 1 0.72572805 1 0.72572805 1 0.8704319749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3560 {}}} SUCCS {{259 0 0-3562 {}}} CYCLES {}}
+set a(0-3562) {NAME ACC1-3:conc#261 TYPE CONCATENATE PAR 0-2847 XREFS 21740 LOC {1 0.14655495 1 0.72572805 1 0.72572805 1 0.8704319749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3559 {}} {258 0 0-3558 {}} {258 0 0-3557 {}} {259 0 0-3561 {}}} SUCCS {{258 0 0-3612 {}}} CYCLES {}}
+set a(0-3563) {NAME ACC1-3:slc(acc.psp)#36 TYPE READSLICE PAR 0-2847 XREFS 21741 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8272301999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3567 {}}} CYCLES {}}
+set a(0-3564) {NAME ACC1-3:slc(acc.psp)#37 TYPE READSLICE PAR 0-2847 XREFS 21742 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8272301999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{258 0 0-3567 {}}} CYCLES {}}
+set a(0-3565) {NAME ACC1-3:slc(acc.idiv)#29 TYPE READSLICE PAR 0-2847 XREFS 21743 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8272301999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3566 {}}} CYCLES {}}
+set a(0-3566) {NAME ACC1-3:exs#14 TYPE SIGNEXTEND PAR 0-2847 XREFS 21744 LOC {1 0.14655495 1 0.682526275 1 0.682526275 1 0.8272301999999999} PREDS {{146 0 0-2871 {}} {259 0 0-3565 {}}} SUCCS {{259 0 0-3567 {}}} CYCLES {}}
+set a(0-3567) {NAME ACC1-3:conc#265 TYPE CONCATENATE PAR 0-2847 XREFS 21745 LOC {1 0.14655495 1 0.682526275 1 0.682526275 1 0.8272301999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3564 {}} {258 0 0-3563 {}} {259 0 0-3566 {}}} SUCCS {{258 0 0-3611 {}}} CYCLES {}}
+set a(0-3568) {NAME ACC1-3:slc(acc.idiv)#5 TYPE READSLICE PAR 0-2847 XREFS 21746 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3569 {}}} CYCLES {}}
+set a(0-3569) {NAME ACC1-3:exs#2 TYPE SIGNEXTEND PAR 0-2847 XREFS 21747 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3568 {}}} SUCCS {{259 0 0-3570 {}}} CYCLES {}}
+set a(0-3570) {NAME ACC1:conc#561 TYPE CONCATENATE PAR 0-2847 XREFS 21748 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3569 {}}} SUCCS {{258 0 0-3578 {}}} CYCLES {}}
+set a(0-3571) {NAME ACC1-3:slc(acc.idiv)#7 TYPE READSLICE PAR 0-2847 XREFS 21749 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3572 {}}} CYCLES {}}
+set a(0-3572) {NAME ACC1-3:exs#3 TYPE SIGNEXTEND PAR 0-2847 XREFS 21750 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3571 {}}} SUCCS {{258 0 0-3577 {}}} CYCLES {}}
+set a(0-3573) {NAME ACC1-3:slc(acc.imod#3) TYPE READSLICE PAR 0-2847 XREFS 21751 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3172 {}}} SUCCS {{258 0 0-3576 {}}} CYCLES {}}
+set a(0-3574) {NAME ACC1-3:slc(acc.idiv)#44 TYPE READSLICE PAR 0-2847 XREFS 21752 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3575 {}}} CYCLES {}}
+set a(0-3575) {NAME ACC1-3:not#27 TYPE NOT PAR 0-2847 XREFS 21753 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3574 {}}} SUCCS {{259 0 0-3576 {}}} CYCLES {}}
+set a(0-3576) {NAME ACC1-3:nand TYPE NAND PAR 0-2847 XREFS 21754 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3573 {}} {259 0 0-3575 {}}} SUCCS {{259 0 0-3577 {}}} CYCLES {}}
+set a(0-3577) {NAME ACC1:conc#562 TYPE CONCATENATE PAR 0-2847 XREFS 21755 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3572 {}} {259 0 0-3576 {}}} SUCCS {{259 0 0-3578 {}}} CYCLES {}}
+set a(0-3578) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#194 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21756 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.7263269020708271} PREDS {{146 0 0-2871 {}} {258 0 0-3570 {}} {259 0 0-3577 {}}} SUCCS {{259 0 0-3579 {}}} CYCLES {}}
+set a(0-3579) {NAME ACC1:slc#59 TYPE READSLICE PAR 0-2847 XREFS 21757 LOC {1 0.43123487499999996 1 0.581623025 1 0.581623025 1 0.7263269499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3578 {}}} SUCCS {{258 0 0-3590 {}}} CYCLES {}}
+set a(0-3580) {NAME ACC1-3:slc(acc.idiv)#15 TYPE READSLICE PAR 0-2847 XREFS 21758 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3581 {}}} CYCLES {}}
+set a(0-3581) {NAME ACC1-3:exs#7 TYPE SIGNEXTEND PAR 0-2847 XREFS 21759 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3580 {}}} SUCCS {{259 0 0-3582 {}}} CYCLES {}}
+set a(0-3582) {NAME ACC1:conc#559 TYPE CONCATENATE PAR 0-2847 XREFS 21760 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3581 {}}} SUCCS {{258 0 0-3588 {}}} CYCLES {}}
+set a(0-3583) {NAME ACC1-3:slc(acc.idiv)#17 TYPE READSLICE PAR 0-2847 XREFS 21761 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3584 {}}} CYCLES {}}
+set a(0-3584) {NAME ACC1-3:exs#8 TYPE SIGNEXTEND PAR 0-2847 XREFS 21762 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3583 {}}} SUCCS {{258 0 0-3587 {}}} CYCLES {}}
+set a(0-3585) {NAME ACC1-3:slc(acc.imod#2)#12 TYPE READSLICE PAR 0-2847 XREFS 21763 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3163 {}}} SUCCS {{259 0 0-3586 {}}} CYCLES {}}
+set a(0-3586) {NAME ACC1-3:not#146 TYPE NOT PAR 0-2847 XREFS 21764 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3585 {}}} SUCCS {{259 0 0-3587 {}}} CYCLES {}}
+set a(0-3587) {NAME ACC1:conc#560 TYPE CONCATENATE PAR 0-2847 XREFS 21765 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3584 {}} {259 0 0-3586 {}}} SUCCS {{259 0 0-3588 {}}} CYCLES {}}
+set a(0-3588) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#193 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21766 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.7263269020708271} PREDS {{146 0 0-2871 {}} {258 0 0-3582 {}} {259 0 0-3587 {}}} SUCCS {{259 0 0-3589 {}}} CYCLES {}}
+set a(0-3589) {NAME ACC1:slc#58 TYPE READSLICE PAR 0-2847 XREFS 21767 LOC {1 0.40398894999999996 1 0.581623025 1 0.581623025 1 0.7263269499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3588 {}}} SUCCS {{259 0 0-3590 {}}} CYCLES {}}
+set a(0-3590) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#200 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21768 LOC {1 0.43123487499999996 1 0.581623025 1 0.581623025 1 0.6291791520708271 1 0.773883077070827} PREDS {{146 0 0-2871 {}} {258 0 0-3579 {}} {259 0 0-3589 {}}} SUCCS {{258 0 0-3610 {}}} CYCLES {}}
+set a(0-3591) {NAME ACC1-3:slc(acc.idiv)#13 TYPE READSLICE PAR 0-2847 XREFS 21769 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3592 {}}} CYCLES {}}
+set a(0-3592) {NAME ACC1-3:exs#6 TYPE SIGNEXTEND PAR 0-2847 XREFS 21770 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3591 {}}} SUCCS {{259 0 0-3593 {}}} CYCLES {}}
+set a(0-3593) {NAME ACC1:conc#557 TYPE CONCATENATE PAR 0-2847 XREFS 21771 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3592 {}}} SUCCS {{258 0 0-3598 {}}} CYCLES {}}
+set a(0-3594) {NAME ACC1-3:slc(acc.idiv)#23 TYPE READSLICE PAR 0-2847 XREFS 21772 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3595 {}}} CYCLES {}}
+set a(0-3595) {NAME ACC1-3:exs#11 TYPE SIGNEXTEND PAR 0-2847 XREFS 21773 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3594 {}}} SUCCS {{258 0 0-3597 {}}} CYCLES {}}
+set a(0-3596) {NAME ACC1-3:slc(acc.imod#2)#11 TYPE READSLICE PAR 0-2847 XREFS 21774 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3163 {}}} SUCCS {{259 0 0-3597 {}}} CYCLES {}}
+set a(0-3597) {NAME ACC1:conc#558 TYPE CONCATENATE PAR 0-2847 XREFS 21775 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3595 {}} {259 0 0-3596 {}}} SUCCS {{259 0 0-3598 {}}} CYCLES {}}
+set a(0-3598) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#192 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21776 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.7263269020708271} PREDS {{146 0 0-2871 {}} {258 0 0-3593 {}} {259 0 0-3597 {}}} SUCCS {{259 0 0-3599 {}}} CYCLES {}}
+set a(0-3599) {NAME ACC1:slc#57 TYPE READSLICE PAR 0-2847 XREFS 21777 LOC {1 0.40398894999999996 1 0.581623025 1 0.581623025 1 0.7263269499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3598 {}}} SUCCS {{258 0 0-3609 {}}} CYCLES {}}
+set a(0-3600) {NAME ACC1-3:slc(acc.idiv)#19 TYPE READSLICE PAR 0-2847 XREFS 21778 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3601 {}}} CYCLES {}}
+set a(0-3601) {NAME ACC1-3:exs#9 TYPE SIGNEXTEND PAR 0-2847 XREFS 21779 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3600 {}}} SUCCS {{259 0 0-3602 {}}} CYCLES {}}
+set a(0-3602) {NAME ACC1:conc#555 TYPE CONCATENATE PAR 0-2847 XREFS 21780 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3601 {}}} SUCCS {{258 0 0-3607 {}}} CYCLES {}}
+set a(0-3603) {NAME ACC1-3:slc(acc.idiv)#21 TYPE READSLICE PAR 0-2847 XREFS 21781 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3105 {}}} SUCCS {{259 0 0-3604 {}}} CYCLES {}}
+set a(0-3604) {NAME ACC1-3:exs#10 TYPE SIGNEXTEND PAR 0-2847 XREFS 21782 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {259 0 0-3603 {}}} SUCCS {{258 0 0-3606 {}}} CYCLES {}}
+set a(0-3605) {NAME ACC1-3:slc(ACC1:acc#107.psp)#9 TYPE READSLICE PAR 0-2847 XREFS 21783 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3145 {}}} SUCCS {{259 0 0-3606 {}}} CYCLES {}}
+set a(0-3606) {NAME ACC1:conc#556 TYPE CONCATENATE PAR 0-2847 XREFS 21784 LOC {1 0.267931 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-2871 {}} {258 0 0-3604 {}} {259 0 0-3605 {}}} SUCCS {{259 0 0-3607 {}}} CYCLES {}}
+set a(0-3607) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#191 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21785 LOC {1 0.267931 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.7263269020708271} PREDS {{146 0 0-2871 {}} {258 0 0-3602 {}} {259 0 0-3606 {}}} SUCCS {{259 0 0-3608 {}}} CYCLES {}}
+set a(0-3608) {NAME ACC1:slc#56 TYPE READSLICE PAR 0-2847 XREFS 21786 LOC {1 0.315487175 1 0.581623025 1 0.581623025 1 0.7263269499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3607 {}}} SUCCS {{259 0 0-3609 {}}} CYCLES {}}
+set a(0-3609) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#199 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21787 LOC {1 0.40398894999999996 1 0.581623025 1 0.581623025 1 0.6291791520708271 1 0.773883077070827} PREDS {{146 0 0-2871 {}} {258 0 0-3599 {}} {259 0 0-3608 {}}} SUCCS {{259 0 0-3610 {}}} CYCLES {}}
+set a(0-3610) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#204 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-2847 XREFS 21788 LOC {1 0.47879105 1 0.6291791999999999 1 0.6291791999999999 1 0.6825262201789504 1 0.8272301451789505} PREDS {{146 0 0-2871 {}} {258 0 0-3590 {}} {259 0 0-3609 {}}} SUCCS {{259 0 0-3611 {}}} CYCLES {}}
+set a(0-3611) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME ACC1:acc#207 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 21789 LOC {1 0.532138125 1 0.682526275 1 0.682526275 1 0.7257279984103023 1 0.8704319234103023} PREDS {{146 0 0-2871 {}} {258 0 0-3567 {}} {259 0 0-3610 {}}} SUCCS {{259 0 0-3612 {}}} CYCLES {}}
+set a(0-3612) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#210 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-2847 XREFS 21790 LOC {1 0.5753399 1 0.72572805 1 0.72572805 1 0.7781125027684257 1 0.9228164277684257} PREDS {{146 0 0-2871 {}} {258 0 0-3562 {}} {259 0 0-3611 {}}} SUCCS {{259 0 0-3613 {}}} CYCLES {}}
+set a(0-3613) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,0,10) AREA_SCORE 10.25 QUANTITY 5 NAME ACC1:acc#212 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-2847 XREFS 21791 LOC {1 0.6277244 1 0.77811255 1 0.77811255 1 0.85529603186502 1 0.99999995686502} PREDS {{146 0 0-2871 {}} {258 0 0-3556 {}} {259 0 0-3612 {}}} SUCCS {{259 0 0-3614 {}}} CYCLES {}}
+set a(0-3614) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,13) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#214 TYPE ACCU DELAY {1.04 ns} LIBRARY_DELAY {1.04 ns} PAR 0-2847 XREFS 21792 LOC {1 0.8413077499999999 1 0.8552960749999999 1 0.8552960749999999 1 0.9205117063734283 2 0.09500765637342837} PREDS {{146 0 0-2871 {}} {258 0 0-3550 {}} {259 0 0-3613 {}}} SUCCS {{259 0 0-3615 {}}} CYCLES {}}
+set a(0-3615) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME ACC1-3:acc#122 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-2847 XREFS 21793 LOC {1 0.9065234249999999 1 0.92051175 1 0.92051175 1 0.9999999534997777 2 0.17449590349977767} PREDS {{146 0 0-2871 {}} {258 0 0-3403 {}} {259 0 0-3614 {}}} SUCCS {{259 0 0-3616 {}}} CYCLES {}}
+set a(0-3616) {NAME ACC1:exs#749 TYPE SIGNEXTEND PAR 0-2847 XREFS 21794 LOC {1 0.986011675 1 1.0 1 1.0 2 0.17449594999999998} PREDS {{146 0 0-2871 {}} {259 0 0-3615 {}}} SUCCS {{258 0 0-3967 {}}} CYCLES {}}
+set a(0-3617) {NAME ACC1-3:slc(acc#10.psp)#61 TYPE READSLICE PAR 0-2847 XREFS 21795 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8410234999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3620 {}}} CYCLES {}}
+set a(0-3618) {NAME ACC1-3:slc(acc#10.psp)#62 TYPE READSLICE PAR 0-2847 XREFS 21796 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8410234999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3620 {}}} CYCLES {}}
+set a(0-3619) {NAME ACC1-3:slc(acc#10.psp)#49 TYPE READSLICE PAR 0-2847 XREFS 21797 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8410234999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3620 {}}} CYCLES {}}
+set a(0-3620) {NAME ACC1-3:conc#281 TYPE CONCATENATE PAR 0-2847 XREFS 21798 LOC {1 0.14655495 1 0.8410234999999999 1 0.8410234999999999 1 0.8410234999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3618 {}} {258 0 0-3617 {}} {259 0 0-3619 {}}} SUCCS {{258 0 0-3700 {}}} CYCLES {}}
+set a(0-3621) {NAME ACC1-3:slc(acc#10.psp)#29 TYPE READSLICE PAR 0-2847 XREFS 21799 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.512853025} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3622 {}}} CYCLES {}}
+set a(0-3622) {NAME ACC1:conc#580 TYPE CONCATENATE PAR 0-2847 XREFS 21800 LOC {1 0.14655495 1 0.512853025 1 0.512853025 1 0.512853025} PREDS {{146 0 0-2871 {}} {259 0 0-3621 {}}} SUCCS {{259 0 0-3623 {}}} CYCLES {}}
+set a(0-3623) {NAME ACC1:conc#581 TYPE CONCATENATE PAR 0-2847 XREFS 21801 LOC {1 0.14655495 1 0.512853025 1 0.512853025 1 0.512853025} PREDS {{146 0 0-2871 {}} {259 0 0-3622 {}}} SUCCS {{258 0 0-3627 {}}} CYCLES {}}
+set a(0-3624) {NAME ACC1-3:slc(ACC1:acc#113.psp)#10 TYPE READSLICE PAR 0-2847 XREFS 21802 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.512853025} PREDS {{146 0 0-2871 {}} {258 0 0-3292 {}}} SUCCS {{258 0 0-3626 {}}} CYCLES {}}
+set a(0-3625) {NAME ACC1-3:slc(acc#10.psp)#30 TYPE READSLICE PAR 0-2847 XREFS 21803 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.512853025} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3626 {}}} CYCLES {}}
+set a(0-3626) {NAME ACC1:conc#582 TYPE CONCATENATE PAR 0-2847 XREFS 21804 LOC {1 0.267931 1 0.512853025 1 0.512853025 1 0.512853025} PREDS {{146 0 0-2871 {}} {258 0 0-3624 {}} {259 0 0-3625 {}}} SUCCS {{259 0 0-3627 {}}} CYCLES {}}
+set a(0-3627) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#242 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-2847 XREFS 21805 LOC {1 0.267931 1 0.512853025 1 0.512853025 1 0.5504736020241716 1 0.5504736020241716} PREDS {{146 0 0-2871 {}} {258 0 0-3623 {}} {259 0 0-3626 {}}} SUCCS {{259 0 0-3628 {}}} CYCLES {}}
+set a(0-3628) {NAME ACC1:slc#68 TYPE READSLICE PAR 0-2847 XREFS 21806 LOC {1 0.305551625 1 0.5504736499999999 1 0.5504736499999999 1 0.5504736499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3627 {}}} SUCCS {{258 0 0-3630 {}}} CYCLES {}}
+set a(0-3629) {NAME ACC1-3:slc(ACC1:acc#120.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21807 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.5504736499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3303 {}}} SUCCS {{259 0 0-3630 {}}} CYCLES {}}
+set a(0-3630) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#251 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-2847 XREFS 21808 LOC {1 0.32918685 1 0.5504736499999999 1 0.5504736499999999 1 0.5880942270241716 1 0.5880942270241716} PREDS {{146 0 0-2871 {}} {258 0 0-3628 {}} {259 0 0-3629 {}}} SUCCS {{258 0 0-3642 {}}} CYCLES {}}
+set a(0-3631) {NAME ACC1-3:slc(acc#10.psp)#31 TYPE READSLICE PAR 0-2847 XREFS 21809 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.56084835} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3633 {}}} CYCLES {}}
+set a(0-3632) {NAME ACC1-3:slc(acc#10.psp)#32 TYPE READSLICE PAR 0-2847 XREFS 21810 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.56084835} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3633 {}}} CYCLES {}}
+set a(0-3633) {NAME ACC1-3:conc#282 TYPE CONCATENATE PAR 0-2847 XREFS 21811 LOC {1 0.14655495 1 0.56084835 1 0.56084835 1 0.56084835} PREDS {{146 0 0-2871 {}} {258 0 0-3631 {}} {259 0 0-3632 {}}} SUCCS {{259 0 0-3634 {}}} CYCLES {}}
+set a(0-3634) {NAME ACC1:conc#583 TYPE CONCATENATE PAR 0-2847 XREFS 21812 LOC {1 0.14655495 1 0.56084835 1 0.56084835 1 0.56084835} PREDS {{146 0 0-2871 {}} {259 0 0-3633 {}}} SUCCS {{258 0 0-3640 {}}} CYCLES {}}
+set a(0-3635) {NAME ACC1-3:slc(ACC1:acc#113.psp)#11 TYPE READSLICE PAR 0-2847 XREFS 21813 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.56084835} PREDS {{146 0 0-2871 {}} {258 0 0-3292 {}}} SUCCS {{258 0 0-3637 {}}} CYCLES {}}
+set a(0-3636) {NAME ACC1-3:slc(acc#10.psp)#33 TYPE READSLICE PAR 0-2847 XREFS 21814 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.56084835} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3637 {}}} CYCLES {}}
+set a(0-3637) {NAME ACC1-3:conc#283 TYPE CONCATENATE PAR 0-2847 XREFS 21815 LOC {1 0.267931 1 0.56084835 1 0.56084835 1 0.56084835} PREDS {{146 0 0-2871 {}} {258 0 0-3635 {}} {259 0 0-3636 {}}} SUCCS {{258 0 0-3639 {}}} CYCLES {}}
+set a(0-3638) {NAME ACC1-3:slc(ACC1:acc#113.psp)#8 TYPE READSLICE PAR 0-2847 XREFS 21816 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.56084835} PREDS {{146 0 0-2871 {}} {258 0 0-3292 {}}} SUCCS {{259 0 0-3639 {}}} CYCLES {}}
+set a(0-3639) {NAME ACC1:conc#584 TYPE CONCATENATE PAR 0-2847 XREFS 21817 LOC {1 0.267931 1 0.56084835 1 0.56084835 1 0.56084835} PREDS {{146 0 0-2871 {}} {258 0 0-3637 {}} {259 0 0-3638 {}}} SUCCS {{259 0 0-3640 {}}} CYCLES {}}
+set a(0-3640) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#243 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21818 LOC {1 0.267931 1 0.56084835 1 0.56084835 1 0.5880942270708271 1 0.5880942270708271} PREDS {{146 0 0-2871 {}} {258 0 0-3634 {}} {259 0 0-3639 {}}} SUCCS {{259 0 0-3641 {}}} CYCLES {}}
+set a(0-3641) {NAME ACC1:slc#69 TYPE READSLICE PAR 0-2847 XREFS 21819 LOC {1 0.295176925 1 0.588094275 1 0.588094275 1 0.588094275} PREDS {{146 0 0-2871 {}} {259 0 0-3640 {}}} SUCCS {{259 0 0-3642 {}}} CYCLES {}}
+set a(0-3642) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#256 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 21820 LOC {1 0.366807475 1 0.588094275 1 0.588094275 1 0.6312861701789505 1 0.6312861701789505} PREDS {{146 0 0-2871 {}} {258 0 0-3630 {}} {259 0 0-3641 {}}} SUCCS {{258 0 0-3654 {}}} CYCLES {}}
+set a(0-3643) {NAME ACC1-3:slc(acc#10.psp)#34 TYPE READSLICE PAR 0-2847 XREFS 21821 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.5982493999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3647 {}}} CYCLES {}}
+set a(0-3644) {NAME ACC1-3:slc(acc#10.psp)#35 TYPE READSLICE PAR 0-2847 XREFS 21822 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.5982493999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3647 {}}} CYCLES {}}
+set a(0-3645) {NAME ACC1-3:slc(acc.idiv#2)#31 TYPE READSLICE PAR 0-2847 XREFS 21823 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.5982493999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3646 {}}} CYCLES {}}
+set a(0-3646) {NAME ACC1-3:exs#51 TYPE SIGNEXTEND PAR 0-2847 XREFS 21824 LOC {1 0.14655495 1 0.5982493999999999 1 0.5982493999999999 1 0.5982493999999999} PREDS {{146 0 0-2871 {}} {259 0 0-3645 {}}} SUCCS {{259 0 0-3647 {}}} CYCLES {}}
+set a(0-3647) {NAME ACC1-3:conc#284 TYPE CONCATENATE PAR 0-2847 XREFS 21825 LOC {1 0.14655495 1 0.5982493999999999 1 0.5982493999999999 1 0.5982493999999999} PREDS {{146 0 0-2871 {}} {258 0 0-3644 {}} {258 0 0-3643 {}} {259 0 0-3646 {}}} SUCCS {{258 0 0-3653 {}}} CYCLES {}}
+set a(0-3648) {NAME ACC1-3:slc(acc.idiv#2)#33 TYPE READSLICE PAR 0-2847 XREFS 21826 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.55746635} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3649 {}}} CYCLES {}}
+set a(0-3649) {NAME ACC1-3:exs#52 TYPE SIGNEXTEND PAR 0-2847 XREFS 21827 LOC {1 0.14655495 1 0.55746635 1 0.55746635 1 0.55746635} PREDS {{146 0 0-2871 {}} {259 0 0-3648 {}}} SUCCS {{258 0 0-3652 {}}} CYCLES {}}
+set a(0-3650) {NAME ACC1-3:slc(acc.idiv#2)#35 TYPE READSLICE PAR 0-2847 XREFS 21828 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.55746635} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3651 {}}} CYCLES {}}
+set a(0-3651) {NAME ACC1-3:exs#53 TYPE SIGNEXTEND PAR 0-2847 XREFS 21829 LOC {1 0.14655495 1 0.55746635 1 0.55746635 1 0.55746635} PREDS {{146 0 0-2871 {}} {259 0 0-3650 {}}} SUCCS {{259 0 0-3652 {}}} CYCLES {}}
+set a(0-3652) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#250 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21830 LOC {1 0.14655495 1 0.55746635 1 0.55746635 1 0.5982493600894753 1 0.5982493600894753} PREDS {{146 0 0-2871 {}} {258 0 0-3649 {}} {259 0 0-3651 {}}} SUCCS {{259 0 0-3653 {}}} CYCLES {}}
+set a(0-3653) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#255 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-2847 XREFS 21831 LOC {1 0.187338 1 0.5982493999999999 1 0.5982493999999999 1 0.6312861701789504 1 0.6312861701789504} PREDS {{146 0 0-2871 {}} {258 0 0-3647 {}} {259 0 0-3652 {}}} SUCCS {{259 0 0-3654 {}}} CYCLES {}}
+set a(0-3654) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#259 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 21832 LOC {1 0.409999425 1 0.631286225 1 0.631286225 1 0.669575684496936 1 0.669575684496936} PREDS {{146 0 0-2871 {}} {258 0 0-3642 {}} {259 0 0-3653 {}}} SUCCS {{258 0 0-3660 {}}} CYCLES {}}
+set a(0-3655) {NAME ACC1-3:slc(acc#10.psp)#54 TYPE READSLICE PAR 0-2847 XREFS 21833 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.669575725} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3659 {}}} CYCLES {}}
+set a(0-3656) {NAME ACC1-3:slc(acc#10.psp)#55 TYPE READSLICE PAR 0-2847 XREFS 21834 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.669575725} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3659 {}}} CYCLES {}}
+set a(0-3657) {NAME ACC1-3:slc(acc#10.psp)#56 TYPE READSLICE PAR 0-2847 XREFS 21835 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.669575725} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3659 {}}} CYCLES {}}
+set a(0-3658) {NAME ACC1-3:slc(acc#10.psp)#47 TYPE READSLICE PAR 0-2847 XREFS 21836 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.669575725} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3659 {}}} CYCLES {}}
+set a(0-3659) {NAME ACC1-3:conc#279 TYPE CONCATENATE PAR 0-2847 XREFS 21837 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.669575725} PREDS {{146 0 0-2871 {}} {258 0 0-3657 {}} {258 0 0-3656 {}} {258 0 0-3655 {}} {259 0 0-3658 {}}} SUCCS {{259 0 0-3660 {}}} CYCLES {}}
+set a(0-3660) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#262 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-2847 XREFS 21838 LOC {1 0.448288925 1 0.669575725 1 0.669575725 1 0.7174547879329679 1 0.7174547879329679} PREDS {{146 0 0-2871 {}} {258 0 0-3654 {}} {259 0 0-3659 {}}} SUCCS {{258 0 0-3691 {}}} CYCLES {}}
+set a(0-3661) {NAME ACC1-3:slc(acc#10.psp)#17 TYPE READSLICE PAR 0-2847 XREFS 21839 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.669575725} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3664 {}}} CYCLES {}}
+set a(0-3662) {NAME ACC1-3:slc(acc.idiv#2)#25 TYPE READSLICE PAR 0-2847 XREFS 21840 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.669575725} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3663 {}}} CYCLES {}}
+set a(0-3663) {NAME ACC1-3:exs#48 TYPE SIGNEXTEND PAR 0-2847 XREFS 21841 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.669575725} PREDS {{146 0 0-2871 {}} {259 0 0-3662 {}}} SUCCS {{259 0 0-3664 {}}} CYCLES {}}
+set a(0-3664) {NAME ACC1-3:conc#254 TYPE CONCATENATE PAR 0-2847 XREFS 21842 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.669575725} PREDS {{146 0 0-2871 {}} {258 0 0-3661 {}} {259 0 0-3663 {}}} SUCCS {{259 0 0-3665 {}}} CYCLES {}}
+set a(0-3665) {NAME ACC1-3:exs#544 TYPE SIGNEXTEND PAR 0-2847 XREFS 21843 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.669575725} PREDS {{146 0 0-2871 {}} {259 0 0-3664 {}}} SUCCS {{258 0 0-3690 {}}} CYCLES {}}
+set a(0-3666) {NAME ACC1-3:slc(acc#10.psp)#52 TYPE READSLICE PAR 0-2847 XREFS 21844 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.631286225} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3669 {}}} CYCLES {}}
+set a(0-3667) {NAME ACC1-3:slc(acc#10.psp)#53 TYPE READSLICE PAR 0-2847 XREFS 21845 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.631286225} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3669 {}}} CYCLES {}}
+set a(0-3668) {NAME ACC1-3:slc(acc#10.psp)#46 TYPE READSLICE PAR 0-2847 XREFS 21846 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.631286225} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3669 {}}} CYCLES {}}
+set a(0-3669) {NAME ACC1-3:conc#278 TYPE CONCATENATE PAR 0-2847 XREFS 21847 LOC {1 0.14655495 1 0.631286225 1 0.631286225 1 0.631286225} PREDS {{146 0 0-2871 {}} {258 0 0-3667 {}} {258 0 0-3666 {}} {259 0 0-3668 {}}} SUCCS {{258 0 0-3689 {}}} CYCLES {}}
+set a(0-3670) {NAME ACC1-3:slc(acc.idiv#2)#9 TYPE READSLICE PAR 0-2847 XREFS 21848 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.542947} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3671 {}}} CYCLES {}}
+set a(0-3671) {NAME ACC1-3:exs#40 TYPE SIGNEXTEND PAR 0-2847 XREFS 21849 LOC {1 0.14655495 1 0.542947 1 0.542947 1 0.542947} PREDS {{146 0 0-2871 {}} {259 0 0-3670 {}}} SUCCS {{258 0 0-3674 {}}} CYCLES {}}
+set a(0-3672) {NAME ACC1-3:slc(acc.idiv#2)#11 TYPE READSLICE PAR 0-2847 XREFS 21850 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.542947} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3673 {}}} CYCLES {}}
+set a(0-3673) {NAME ACC1-3:exs#41 TYPE SIGNEXTEND PAR 0-2847 XREFS 21851 LOC {1 0.14655495 1 0.542947 1 0.542947 1 0.542947} PREDS {{146 0 0-2871 {}} {259 0 0-3672 {}}} SUCCS {{259 0 0-3674 {}}} CYCLES {}}
+set a(0-3674) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#249 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21852 LOC {1 0.14655495 1 0.542947 1 0.542947 1 0.5837300100894752 1 0.5837300100894752} PREDS {{146 0 0-2871 {}} {258 0 0-3671 {}} {259 0 0-3673 {}}} SUCCS {{258 0 0-3688 {}}} CYCLES {}}
+set a(0-3675) {NAME ACC1-3:slc(acc.idiv#2)#1 TYPE READSLICE PAR 0-2847 XREFS 21853 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.536173875} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3676 {}}} CYCLES {}}
+set a(0-3676) {NAME ACC1-3:exs#36 TYPE SIGNEXTEND PAR 0-2847 XREFS 21854 LOC {1 0.14655495 1 0.536173875 1 0.536173875 1 0.536173875} PREDS {{146 0 0-2871 {}} {259 0 0-3675 {}}} SUCCS {{259 0 0-3677 {}}} CYCLES {}}
+set a(0-3677) {NAME ACC1:conc#593 TYPE CONCATENATE PAR 0-2847 XREFS 21855 LOC {1 0.14655495 1 0.536173875 1 0.536173875 1 0.536173875} PREDS {{146 0 0-2871 {}} {259 0 0-3676 {}}} SUCCS {{258 0 0-3686 {}}} CYCLES {}}
+set a(0-3678) {NAME ACC1-3:slc(acc.idiv#2)#3 TYPE READSLICE PAR 0-2847 XREFS 21856 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.536173875} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3679 {}}} CYCLES {}}
+set a(0-3679) {NAME ACC1-3:exs#37 TYPE SIGNEXTEND PAR 0-2847 XREFS 21857 LOC {1 0.14655495 1 0.536173875 1 0.536173875 1 0.536173875} PREDS {{146 0 0-2871 {}} {259 0 0-3678 {}}} SUCCS {{258 0 0-3685 {}}} CYCLES {}}
+set a(0-3680) {NAME ACC1-3:slc(acc.idiv#2)#45 TYPE READSLICE PAR 0-2847 XREFS 21858 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.536173875} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3684 {}}} CYCLES {}}
+set a(0-3681) {NAME ACC1-3:slc(acc.imod#11)#1 TYPE READSLICE PAR 0-2847 XREFS 21859 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.536173875} PREDS {{146 0 0-2871 {}} {258 0 0-3319 {}}} SUCCS {{259 0 0-3682 {}}} CYCLES {}}
+set a(0-3682) {NAME ACC1-3:not#92 TYPE NOT PAR 0-2847 XREFS 21860 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.536173875} PREDS {{146 0 0-2871 {}} {259 0 0-3681 {}}} SUCCS {{258 0 0-3684 {}}} CYCLES {}}
+set a(0-3683) {NAME ACC1-3:slc(acc.imod#11)#2 TYPE READSLICE PAR 0-2847 XREFS 21861 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.536173875} PREDS {{146 0 0-2871 {}} {258 0 0-3319 {}}} SUCCS {{259 0 0-3684 {}}} CYCLES {}}
+set a(0-3684) {NAME ACC1-3:and#5 TYPE AND PAR 0-2847 XREFS 21862 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.536173875} PREDS {{146 0 0-2871 {}} {258 0 0-3682 {}} {258 0 0-3680 {}} {259 0 0-3683 {}}} SUCCS {{259 0 0-3685 {}}} CYCLES {}}
+set a(0-3685) {NAME ACC1:conc#594 TYPE CONCATENATE PAR 0-2847 XREFS 21863 LOC {1 0.3836787 1 0.536173875 1 0.536173875 1 0.536173875} PREDS {{146 0 0-2871 {}} {258 0 0-3679 {}} {259 0 0-3684 {}}} SUCCS {{259 0 0-3686 {}}} CYCLES {}}
+set a(0-3686) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#248 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21864 LOC {1 0.3836787 1 0.536173875 1 0.536173875 1 0.5837300020708271 1 0.5837300020708271} PREDS {{146 0 0-2871 {}} {258 0 0-3677 {}} {259 0 0-3685 {}}} SUCCS {{259 0 0-3687 {}}} CYCLES {}}
+set a(0-3687) {NAME ACC1:slc#74 TYPE READSLICE PAR 0-2847 XREFS 21865 LOC {1 0.43123487499999996 1 0.58373005 1 0.58373005 1 0.58373005} PREDS {{146 0 0-2871 {}} {259 0 0-3686 {}}} SUCCS {{259 0 0-3688 {}}} CYCLES {}}
+set a(0-3688) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#254 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21866 LOC {1 0.43123487499999996 1 0.58373005 1 0.58373005 1 0.6312861770708271 1 0.6312861770708271} PREDS {{146 0 0-2871 {}} {258 0 0-3674 {}} {259 0 0-3687 {}}} SUCCS {{259 0 0-3689 {}}} CYCLES {}}
+set a(0-3689) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#258 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 21867 LOC {1 0.47879105 1 0.631286225 1 0.631286225 1 0.669575684496936 1 0.669575684496936} PREDS {{146 0 0-2871 {}} {258 0 0-3669 {}} {259 0 0-3688 {}}} SUCCS {{259 0 0-3690 {}}} CYCLES {}}
+set a(0-3690) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#261 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-2847 XREFS 21868 LOC {1 0.51708055 1 0.669575725 1 0.669575725 1 0.7174547879329679 1 0.7174547879329679} PREDS {{146 0 0-2871 {}} {258 0 0-3665 {}} {259 0 0-3689 {}}} SUCCS {{259 0 0-3691 {}}} CYCLES {}}
+set a(0-3691) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#264 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-2847 XREFS 21869 LOC {1 0.564959675 1 0.71745485 1 0.71745485 1 0.7698393027684257 1 0.7698393027684257} PREDS {{146 0 0-2871 {}} {258 0 0-3660 {}} {259 0 0-3690 {}}} SUCCS {{258 0 0-3699 {}}} CYCLES {}}
+set a(0-3692) {NAME ACC1-3:slc(acc#10.psp)#66 TYPE READSLICE PAR 0-2847 XREFS 21870 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7698393499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3698 {}}} CYCLES {}}
+set a(0-3693) {NAME ACC1-3:slc(acc#10.psp)#67 TYPE READSLICE PAR 0-2847 XREFS 21871 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7698393499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3698 {}}} CYCLES {}}
+set a(0-3694) {NAME ACC1-3:slc(acc#10.psp)#68 TYPE READSLICE PAR 0-2847 XREFS 21872 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7698393499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3698 {}}} CYCLES {}}
+set a(0-3695) {NAME ACC1-3:slc(acc#10.psp)#51 TYPE READSLICE PAR 0-2847 XREFS 21873 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7698393499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3698 {}}} CYCLES {}}
+set a(0-3696) {NAME ACC1-3:slc(acc.idiv#2)#27 TYPE READSLICE PAR 0-2847 XREFS 21874 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7698393499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3697 {}}} CYCLES {}}
+set a(0-3697) {NAME ACC1-3:exs#49 TYPE SIGNEXTEND PAR 0-2847 XREFS 21875 LOC {1 0.14655495 1 0.7698393499999999 1 0.7698393499999999 1 0.7698393499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3696 {}}} SUCCS {{259 0 0-3698 {}}} CYCLES {}}
+set a(0-3698) {NAME ACC1-3:conc#287 TYPE CONCATENATE PAR 0-2847 XREFS 21876 LOC {1 0.14655495 1 0.7698393499999999 1 0.7698393499999999 1 0.7698393499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3695 {}} {258 0 0-3694 {}} {258 0 0-3693 {}} {258 0 0-3692 {}} {259 0 0-3697 {}}} SUCCS {{259 0 0-3699 {}}} CYCLES {}}
+set a(0-3699) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#266 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 21877 LOC {1 0.6173441749999999 1 0.7698393499999999 1 0.7698393499999999 1 0.8410234533364113 1 0.8410234533364113} PREDS {{146 0 0-2871 {}} {258 0 0-3691 {}} {259 0 0-3698 {}}} SUCCS {{259 0 0-3700 {}}} CYCLES {}}
+set a(0-3700) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME ACC1:acc#268 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-2847 XREFS 21878 LOC {1 0.6885283249999999 1 0.8410234999999999 1 0.8410234999999999 1 0.9205117034997776 1 0.9205117034997776} PREDS {{146 0 0-2871 {}} {258 0 0-3620 {}} {259 0 0-3699 {}}} SUCCS {{258 0 0-3912 {}}} CYCLES {}}
+set a(0-3701) {NAME ACC1-1:slc(acc#10.psp)#57 TYPE READSLICE PAR 0-2847 XREFS 21879 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.641712725} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3706 {}}} CYCLES {}}
+set a(0-3702) {NAME ACC1-1:slc(acc#10.psp)#58 TYPE READSLICE PAR 0-2847 XREFS 21880 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.641712725} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3706 {}}} CYCLES {}}
+set a(0-3703) {NAME ACC1-1:slc(acc#10.psp)#59 TYPE READSLICE PAR 0-2847 XREFS 21881 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.641712725} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3706 {}}} CYCLES {}}
+set a(0-3704) {NAME ACC1-1:slc(acc#10.psp)#60 TYPE READSLICE PAR 0-2847 XREFS 21882 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.641712725} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3706 {}}} CYCLES {}}
+set a(0-3705) {NAME ACC1-1:slc(acc#10.psp)#48 TYPE READSLICE PAR 0-2847 XREFS 21883 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.641712725} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3706 {}}} CYCLES {}}
+set a(0-3706) {NAME ACC1-1:conc#280 TYPE CONCATENATE PAR 0-2847 XREFS 21884 LOC {1 0.14655495 1 0.641712725 1 0.641712725 1 0.641712725} PREDS {{146 0 0-2871 {}} {258 0 0-3704 {}} {258 0 0-3703 {}} {258 0 0-3702 {}} {258 0 0-3701 {}} {259 0 0-3705 {}}} SUCCS {{258 0 0-3763 {}}} CYCLES {}}
+set a(0-3707) {NAME ACC1-1:slc(acc#10.psp)#63 TYPE READSLICE PAR 0-2847 XREFS 21885 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5893282249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3712 {}}} CYCLES {}}
+set a(0-3708) {NAME ACC1-1:slc(acc#10.psp)#64 TYPE READSLICE PAR 0-2847 XREFS 21886 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5893282249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3712 {}}} CYCLES {}}
+set a(0-3709) {NAME ACC1-1:slc(acc#10.psp)#50 TYPE READSLICE PAR 0-2847 XREFS 21887 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5893282249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3712 {}}} CYCLES {}}
+set a(0-3710) {NAME ACC1-1:slc(acc#10.psp)#65 TYPE READSLICE PAR 0-2847 XREFS 21888 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5893282249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3711 {}}} CYCLES {}}
+set a(0-3711) {NAME ACC1-1:exs#543 TYPE SIGNEXTEND PAR 0-2847 XREFS 21889 LOC {1 0.14655495 1 0.5893282249999999 1 0.5893282249999999 1 0.5893282249999999} PREDS {{146 0 0-2871 {}} {259 0 0-3710 {}}} SUCCS {{259 0 0-3712 {}}} CYCLES {}}
+set a(0-3712) {NAME ACC1-1:conc#285 TYPE CONCATENATE PAR 0-2847 XREFS 21890 LOC {1 0.14655495 1 0.5893282249999999 1 0.5893282249999999 1 0.5893282249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3709 {}} {258 0 0-3708 {}} {258 0 0-3707 {}} {259 0 0-3711 {}}} SUCCS {{258 0 0-3762 {}}} CYCLES {}}
+set a(0-3713) {NAME ACC1-1:slc(acc#10.psp)#36 TYPE READSLICE PAR 0-2847 XREFS 21891 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5461264499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3717 {}}} CYCLES {}}
+set a(0-3714) {NAME ACC1-1:slc(acc#10.psp)#37 TYPE READSLICE PAR 0-2847 XREFS 21892 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5461264499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3717 {}}} CYCLES {}}
+set a(0-3715) {NAME ACC1-1:slc(acc.idiv#2)#29 TYPE READSLICE PAR 0-2847 XREFS 21893 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5461264499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3716 {}}} CYCLES {}}
+set a(0-3716) {NAME ACC1-1:exs#50 TYPE SIGNEXTEND PAR 0-2847 XREFS 21894 LOC {1 0.14655495 1 0.5461264499999999 1 0.5461264499999999 1 0.5461264499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3715 {}}} SUCCS {{259 0 0-3717 {}}} CYCLES {}}
+set a(0-3717) {NAME ACC1-1:conc#289 TYPE CONCATENATE PAR 0-2847 XREFS 21895 LOC {1 0.14655495 1 0.5461264499999999 1 0.5461264499999999 1 0.5461264499999999} PREDS {{146 0 0-2871 {}} {258 0 0-3714 {}} {258 0 0-3713 {}} {259 0 0-3716 {}}} SUCCS {{258 0 0-3761 {}}} CYCLES {}}
+set a(0-3718) {NAME ACC1-1:slc(acc.idiv#2)#5 TYPE READSLICE PAR 0-2847 XREFS 21896 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3719 {}}} CYCLES {}}
+set a(0-3719) {NAME ACC1-1:exs#38 TYPE SIGNEXTEND PAR 0-2847 XREFS 21897 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3718 {}}} SUCCS {{259 0 0-3720 {}}} CYCLES {}}
+set a(0-3720) {NAME ACC1:conc#606 TYPE CONCATENATE PAR 0-2847 XREFS 21898 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3719 {}}} SUCCS {{258 0 0-3728 {}}} CYCLES {}}
+set a(0-3721) {NAME ACC1-1:slc(acc.idiv#2)#7 TYPE READSLICE PAR 0-2847 XREFS 21899 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3722 {}}} CYCLES {}}
+set a(0-3722) {NAME ACC1-1:exs#39 TYPE SIGNEXTEND PAR 0-2847 XREFS 21900 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3721 {}}} SUCCS {{258 0 0-3727 {}}} CYCLES {}}
+set a(0-3723) {NAME ACC1-1:slc(acc.imod#11) TYPE READSLICE PAR 0-2847 XREFS 21901 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3097 {}}} SUCCS {{258 0 0-3726 {}}} CYCLES {}}
+set a(0-3724) {NAME ACC1-1:slc(acc.idiv#2)#44 TYPE READSLICE PAR 0-2847 XREFS 21902 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3725 {}}} CYCLES {}}
+set a(0-3725) {NAME ACC1-1:not#91 TYPE NOT PAR 0-2847 XREFS 21903 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3724 {}}} SUCCS {{259 0 0-3726 {}}} CYCLES {}}
+set a(0-3726) {NAME ACC1-1:nand#2 TYPE NAND PAR 0-2847 XREFS 21904 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3723 {}} {259 0 0-3725 {}}} SUCCS {{259 0 0-3727 {}}} CYCLES {}}
+set a(0-3727) {NAME ACC1:conc#607 TYPE CONCATENATE PAR 0-2847 XREFS 21905 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3722 {}} {259 0 0-3726 {}}} SUCCS {{259 0 0-3728 {}}} CYCLES {}}
+set a(0-3728) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#274 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21906 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.4452231520708272} PREDS {{146 0 0-2871 {}} {258 0 0-3720 {}} {259 0 0-3727 {}}} SUCCS {{259 0 0-3729 {}}} CYCLES {}}
+set a(0-3729) {NAME ACC1:slc#80 TYPE READSLICE PAR 0-2847 XREFS 21907 LOC {1 0.43123487499999996 1 0.4452232 1 0.4452232 1 0.4452232} PREDS {{146 0 0-2871 {}} {259 0 0-3728 {}}} SUCCS {{258 0 0-3740 {}}} CYCLES {}}
+set a(0-3730) {NAME ACC1-1:slc(acc.idiv#2)#15 TYPE READSLICE PAR 0-2847 XREFS 21908 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3731 {}}} CYCLES {}}
+set a(0-3731) {NAME ACC1-1:exs#43 TYPE SIGNEXTEND PAR 0-2847 XREFS 21909 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3730 {}}} SUCCS {{259 0 0-3732 {}}} CYCLES {}}
+set a(0-3732) {NAME ACC1:conc#604 TYPE CONCATENATE PAR 0-2847 XREFS 21910 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3731 {}}} SUCCS {{258 0 0-3738 {}}} CYCLES {}}
+set a(0-3733) {NAME ACC1-1:slc(acc.idiv#2)#17 TYPE READSLICE PAR 0-2847 XREFS 21911 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3734 {}}} CYCLES {}}
+set a(0-3734) {NAME ACC1-1:exs#44 TYPE SIGNEXTEND PAR 0-2847 XREFS 21912 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3733 {}}} SUCCS {{258 0 0-3737 {}}} CYCLES {}}
+set a(0-3735) {NAME ACC1-1:slc(acc.imod#10)#12 TYPE READSLICE PAR 0-2847 XREFS 21913 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3088 {}}} SUCCS {{259 0 0-3736 {}}} CYCLES {}}
+set a(0-3736) {NAME ACC1-1:not#150 TYPE NOT PAR 0-2847 XREFS 21914 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3735 {}}} SUCCS {{259 0 0-3737 {}}} CYCLES {}}
+set a(0-3737) {NAME ACC1:conc#605 TYPE CONCATENATE PAR 0-2847 XREFS 21915 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3734 {}} {259 0 0-3736 {}}} SUCCS {{259 0 0-3738 {}}} CYCLES {}}
+set a(0-3738) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#273 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21916 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.4452231520708272} PREDS {{146 0 0-2871 {}} {258 0 0-3732 {}} {259 0 0-3737 {}}} SUCCS {{259 0 0-3739 {}}} CYCLES {}}
+set a(0-3739) {NAME ACC1:slc#79 TYPE READSLICE PAR 0-2847 XREFS 21917 LOC {1 0.40398894999999996 1 0.4452232 1 0.4452232 1 0.4452232} PREDS {{146 0 0-2871 {}} {259 0 0-3738 {}}} SUCCS {{259 0 0-3740 {}}} CYCLES {}}
+set a(0-3740) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#280 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21918 LOC {1 0.43123487499999996 1 0.4452232 1 0.4452232 1 0.49277932707082717 1 0.49277932707082717} PREDS {{146 0 0-2871 {}} {258 0 0-3729 {}} {259 0 0-3739 {}}} SUCCS {{258 0 0-3760 {}}} CYCLES {}}
+set a(0-3741) {NAME ACC1-1:slc(acc.idiv#2)#13 TYPE READSLICE PAR 0-2847 XREFS 21919 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3742 {}}} CYCLES {}}
+set a(0-3742) {NAME ACC1-1:exs#42 TYPE SIGNEXTEND PAR 0-2847 XREFS 21920 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3741 {}}} SUCCS {{259 0 0-3743 {}}} CYCLES {}}
+set a(0-3743) {NAME ACC1:conc#602 TYPE CONCATENATE PAR 0-2847 XREFS 21921 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3742 {}}} SUCCS {{258 0 0-3748 {}}} CYCLES {}}
+set a(0-3744) {NAME ACC1-1:slc(acc.idiv#2)#23 TYPE READSLICE PAR 0-2847 XREFS 21922 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3745 {}}} CYCLES {}}
+set a(0-3745) {NAME ACC1-1:exs#47 TYPE SIGNEXTEND PAR 0-2847 XREFS 21923 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3744 {}}} SUCCS {{258 0 0-3747 {}}} CYCLES {}}
+set a(0-3746) {NAME ACC1-1:slc(acc.imod#10)#11 TYPE READSLICE PAR 0-2847 XREFS 21924 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3088 {}}} SUCCS {{259 0 0-3747 {}}} CYCLES {}}
+set a(0-3747) {NAME ACC1:conc#603 TYPE CONCATENATE PAR 0-2847 XREFS 21925 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3745 {}} {259 0 0-3746 {}}} SUCCS {{259 0 0-3748 {}}} CYCLES {}}
+set a(0-3748) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#272 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21926 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.4452231520708272} PREDS {{146 0 0-2871 {}} {258 0 0-3743 {}} {259 0 0-3747 {}}} SUCCS {{259 0 0-3749 {}}} CYCLES {}}
+set a(0-3749) {NAME ACC1:slc#78 TYPE READSLICE PAR 0-2847 XREFS 21927 LOC {1 0.40398894999999996 1 0.4452232 1 0.4452232 1 0.4452232} PREDS {{146 0 0-2871 {}} {259 0 0-3748 {}}} SUCCS {{258 0 0-3759 {}}} CYCLES {}}
+set a(0-3750) {NAME ACC1-1:slc(acc.idiv#2)#19 TYPE READSLICE PAR 0-2847 XREFS 21928 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3751 {}}} CYCLES {}}
+set a(0-3751) {NAME ACC1-1:exs#45 TYPE SIGNEXTEND PAR 0-2847 XREFS 21929 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3750 {}}} SUCCS {{259 0 0-3752 {}}} CYCLES {}}
+set a(0-3752) {NAME ACC1:conc#600 TYPE CONCATENATE PAR 0-2847 XREFS 21930 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3751 {}}} SUCCS {{258 0 0-3757 {}}} CYCLES {}}
+set a(0-3753) {NAME ACC1-1:slc(acc.idiv#2)#21 TYPE READSLICE PAR 0-2847 XREFS 21931 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3754 {}}} CYCLES {}}
+set a(0-3754) {NAME ACC1-1:exs#46 TYPE SIGNEXTEND PAR 0-2847 XREFS 21932 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {259 0 0-3753 {}}} SUCCS {{258 0 0-3756 {}}} CYCLES {}}
+set a(0-3755) {NAME ACC1-1:slc(ACC1:acc#113.psp)#9 TYPE READSLICE PAR 0-2847 XREFS 21933 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3070 {}}} SUCCS {{259 0 0-3756 {}}} CYCLES {}}
+set a(0-3756) {NAME ACC1:conc#601 TYPE CONCATENATE PAR 0-2847 XREFS 21934 LOC {1 0.267931 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-2871 {}} {258 0 0-3754 {}} {259 0 0-3755 {}}} SUCCS {{259 0 0-3757 {}}} CYCLES {}}
+set a(0-3757) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#271 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21935 LOC {1 0.267931 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.4452231520708272} PREDS {{146 0 0-2871 {}} {258 0 0-3752 {}} {259 0 0-3756 {}}} SUCCS {{259 0 0-3758 {}}} CYCLES {}}
+set a(0-3758) {NAME ACC1:slc#77 TYPE READSLICE PAR 0-2847 XREFS 21936 LOC {1 0.315487175 1 0.4452232 1 0.4452232 1 0.4452232} PREDS {{146 0 0-2871 {}} {259 0 0-3757 {}}} SUCCS {{259 0 0-3759 {}}} CYCLES {}}
+set a(0-3759) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#279 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 21937 LOC {1 0.40398894999999996 1 0.4452232 1 0.4452232 1 0.49277932707082717 1 0.49277932707082717} PREDS {{146 0 0-2871 {}} {258 0 0-3749 {}} {259 0 0-3758 {}}} SUCCS {{259 0 0-3760 {}}} CYCLES {}}
+set a(0-3760) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#284 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-2847 XREFS 21938 LOC {1 0.47879105 1 0.49277937499999996 1 0.49277937499999996 1 0.5461263951789505 1 0.5461263951789505} PREDS {{146 0 0-2871 {}} {258 0 0-3740 {}} {259 0 0-3759 {}}} SUCCS {{259 0 0-3761 {}}} CYCLES {}}
+set a(0-3761) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME ACC1:acc#287 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 21939 LOC {1 0.532138125 1 0.5461264499999999 1 0.5461264499999999 1 0.5893281734103023 1 0.5893281734103023} PREDS {{146 0 0-2871 {}} {258 0 0-3717 {}} {259 0 0-3760 {}}} SUCCS {{259 0 0-3762 {}}} CYCLES {}}
+set a(0-3762) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#290 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-2847 XREFS 21940 LOC {1 0.5753399 1 0.5893282249999999 1 0.5893282249999999 1 0.6417126777684257 1 0.6417126777684257} PREDS {{146 0 0-2871 {}} {258 0 0-3712 {}} {259 0 0-3761 {}}} SUCCS {{259 0 0-3763 {}}} CYCLES {}}
+set a(0-3763) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,0,10) AREA_SCORE 10.25 QUANTITY 5 NAME ACC1:acc#292 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-2847 XREFS 21941 LOC {1 0.6277244 1 0.641712725 1 0.641712725 1 0.71889620686502 1 0.71889620686502} PREDS {{146 0 0-2871 {}} {258 0 0-3706 {}} {259 0 0-3762 {}}} SUCCS {{258 0 0-3835 {}}} CYCLES {}}
+set a(0-3764) {NAME ACC1-1:slc(acc#10.psp)#29 TYPE READSLICE PAR 0-2847 XREFS 21942 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.461909925} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3765 {}}} CYCLES {}}
+set a(0-3765) {NAME ACC1:conc#595 TYPE CONCATENATE PAR 0-2847 XREFS 21943 LOC {1 0.14655495 1 0.461909925 1 0.461909925 1 0.461909925} PREDS {{146 0 0-2871 {}} {259 0 0-3764 {}}} SUCCS {{259 0 0-3766 {}}} CYCLES {}}
+set a(0-3766) {NAME ACC1:conc#596 TYPE CONCATENATE PAR 0-2847 XREFS 21944 LOC {1 0.14655495 1 0.461909925 1 0.461909925 1 0.461909925} PREDS {{146 0 0-2871 {}} {259 0 0-3765 {}}} SUCCS {{258 0 0-3770 {}}} CYCLES {}}
+set a(0-3767) {NAME ACC1-1:slc(ACC1:acc#113.psp)#10 TYPE READSLICE PAR 0-2847 XREFS 21945 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.461909925} PREDS {{146 0 0-2871 {}} {258 0 0-3070 {}}} SUCCS {{258 0 0-3769 {}}} CYCLES {}}
+set a(0-3768) {NAME ACC1-1:slc(acc#10.psp)#30 TYPE READSLICE PAR 0-2847 XREFS 21946 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.461909925} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3769 {}}} CYCLES {}}
+set a(0-3769) {NAME ACC1:conc#597 TYPE CONCATENATE PAR 0-2847 XREFS 21947 LOC {1 0.267931 1 0.461909925 1 0.461909925 1 0.461909925} PREDS {{146 0 0-2871 {}} {258 0 0-3767 {}} {259 0 0-3768 {}}} SUCCS {{259 0 0-3770 {}}} CYCLES {}}
+set a(0-3770) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#269 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-2847 XREFS 21948 LOC {1 0.267931 1 0.461909925 1 0.461909925 1 0.49953050202417165 1 0.49953050202417165} PREDS {{146 0 0-2871 {}} {258 0 0-3766 {}} {259 0 0-3769 {}}} SUCCS {{259 0 0-3771 {}}} CYCLES {}}
+set a(0-3771) {NAME ACC1:slc#75 TYPE READSLICE PAR 0-2847 XREFS 21949 LOC {1 0.305551625 1 0.49953054999999996 1 0.49953054999999996 1 0.49953054999999996} PREDS {{146 0 0-2871 {}} {259 0 0-3770 {}}} SUCCS {{258 0 0-3773 {}}} CYCLES {}}
+set a(0-3772) {NAME ACC1-1:slc(ACC1:acc#120.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 21950 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.49953054999999996} PREDS {{146 0 0-2871 {}} {258 0 0-3081 {}}} SUCCS {{259 0 0-3773 {}}} CYCLES {}}
+set a(0-3773) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#278 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-2847 XREFS 21951 LOC {1 0.32918685 1 0.49953054999999996 1 0.49953054999999996 1 0.5371511270241717 1 0.5371511270241717} PREDS {{146 0 0-2871 {}} {258 0 0-3771 {}} {259 0 0-3772 {}}} SUCCS {{258 0 0-3785 {}}} CYCLES {}}
+set a(0-3774) {NAME ACC1-1:slc(acc#10.psp)#31 TYPE READSLICE PAR 0-2847 XREFS 21952 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.50990525} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3776 {}}} CYCLES {}}
+set a(0-3775) {NAME ACC1-1:slc(acc#10.psp)#32 TYPE READSLICE PAR 0-2847 XREFS 21953 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.50990525} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3776 {}}} CYCLES {}}
+set a(0-3776) {NAME ACC1-1:conc#282 TYPE CONCATENATE PAR 0-2847 XREFS 21954 LOC {1 0.14655495 1 0.50990525 1 0.50990525 1 0.50990525} PREDS {{146 0 0-2871 {}} {258 0 0-3774 {}} {259 0 0-3775 {}}} SUCCS {{259 0 0-3777 {}}} CYCLES {}}
+set a(0-3777) {NAME ACC1:conc#598 TYPE CONCATENATE PAR 0-2847 XREFS 21955 LOC {1 0.14655495 1 0.50990525 1 0.50990525 1 0.50990525} PREDS {{146 0 0-2871 {}} {259 0 0-3776 {}}} SUCCS {{258 0 0-3783 {}}} CYCLES {}}
+set a(0-3778) {NAME ACC1-1:slc(ACC1:acc#113.psp)#11 TYPE READSLICE PAR 0-2847 XREFS 21956 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.50990525} PREDS {{146 0 0-2871 {}} {258 0 0-3070 {}}} SUCCS {{258 0 0-3780 {}}} CYCLES {}}
+set a(0-3779) {NAME ACC1-1:slc(acc#10.psp)#33 TYPE READSLICE PAR 0-2847 XREFS 21957 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.50990525} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3780 {}}} CYCLES {}}
+set a(0-3780) {NAME ACC1-1:conc#283 TYPE CONCATENATE PAR 0-2847 XREFS 21958 LOC {1 0.267931 1 0.50990525 1 0.50990525 1 0.50990525} PREDS {{146 0 0-2871 {}} {258 0 0-3778 {}} {259 0 0-3779 {}}} SUCCS {{258 0 0-3782 {}}} CYCLES {}}
+set a(0-3781) {NAME ACC1-1:slc(ACC1:acc#113.psp)#8 TYPE READSLICE PAR 0-2847 XREFS 21959 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.50990525} PREDS {{146 0 0-2871 {}} {258 0 0-3070 {}}} SUCCS {{259 0 0-3782 {}}} CYCLES {}}
+set a(0-3782) {NAME ACC1:conc#599 TYPE CONCATENATE PAR 0-2847 XREFS 21960 LOC {1 0.267931 1 0.50990525 1 0.50990525 1 0.50990525} PREDS {{146 0 0-2871 {}} {258 0 0-3780 {}} {259 0 0-3781 {}}} SUCCS {{259 0 0-3783 {}}} CYCLES {}}
+set a(0-3783) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#270 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 21961 LOC {1 0.267931 1 0.50990525 1 0.50990525 1 0.5371511270708271 1 0.5371511270708271} PREDS {{146 0 0-2871 {}} {258 0 0-3777 {}} {259 0 0-3782 {}}} SUCCS {{259 0 0-3784 {}}} CYCLES {}}
+set a(0-3784) {NAME ACC1:slc#76 TYPE READSLICE PAR 0-2847 XREFS 21962 LOC {1 0.295176925 1 0.537151175 1 0.537151175 1 0.537151175} PREDS {{146 0 0-2871 {}} {259 0 0-3783 {}}} SUCCS {{259 0 0-3785 {}}} CYCLES {}}
+set a(0-3785) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#283 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 21963 LOC {1 0.366807475 1 0.537151175 1 0.537151175 1 0.5803430701789505 1 0.5803430701789505} PREDS {{146 0 0-2871 {}} {258 0 0-3773 {}} {259 0 0-3784 {}}} SUCCS {{258 0 0-3797 {}}} CYCLES {}}
+set a(0-3786) {NAME ACC1-1:slc(acc#10.psp)#34 TYPE READSLICE PAR 0-2847 XREFS 21964 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5473063} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3790 {}}} CYCLES {}}
+set a(0-3787) {NAME ACC1-1:slc(acc#10.psp)#35 TYPE READSLICE PAR 0-2847 XREFS 21965 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5473063} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3790 {}}} CYCLES {}}
+set a(0-3788) {NAME ACC1-1:slc(acc.idiv#2)#31 TYPE READSLICE PAR 0-2847 XREFS 21966 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5473063} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3789 {}}} CYCLES {}}
+set a(0-3789) {NAME ACC1-1:exs#51 TYPE SIGNEXTEND PAR 0-2847 XREFS 21967 LOC {1 0.14655495 1 0.5473063 1 0.5473063 1 0.5473063} PREDS {{146 0 0-2871 {}} {259 0 0-3788 {}}} SUCCS {{259 0 0-3790 {}}} CYCLES {}}
+set a(0-3790) {NAME ACC1-1:conc#284 TYPE CONCATENATE PAR 0-2847 XREFS 21968 LOC {1 0.14655495 1 0.5473063 1 0.5473063 1 0.5473063} PREDS {{146 0 0-2871 {}} {258 0 0-3787 {}} {258 0 0-3786 {}} {259 0 0-3789 {}}} SUCCS {{258 0 0-3796 {}}} CYCLES {}}
+set a(0-3791) {NAME ACC1-1:slc(acc.idiv#2)#33 TYPE READSLICE PAR 0-2847 XREFS 21969 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.50652325} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3792 {}}} CYCLES {}}
+set a(0-3792) {NAME ACC1-1:exs#52 TYPE SIGNEXTEND PAR 0-2847 XREFS 21970 LOC {1 0.14655495 1 0.50652325 1 0.50652325 1 0.50652325} PREDS {{146 0 0-2871 {}} {259 0 0-3791 {}}} SUCCS {{258 0 0-3795 {}}} CYCLES {}}
+set a(0-3793) {NAME ACC1-1:slc(acc.idiv#2)#35 TYPE READSLICE PAR 0-2847 XREFS 21971 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.50652325} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3794 {}}} CYCLES {}}
+set a(0-3794) {NAME ACC1-1:exs#53 TYPE SIGNEXTEND PAR 0-2847 XREFS 21972 LOC {1 0.14655495 1 0.50652325 1 0.50652325 1 0.50652325} PREDS {{146 0 0-2871 {}} {259 0 0-3793 {}}} SUCCS {{259 0 0-3795 {}}} CYCLES {}}
+set a(0-3795) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#277 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21973 LOC {1 0.14655495 1 0.50652325 1 0.50652325 1 0.5473062600894752 1 0.5473062600894752} PREDS {{146 0 0-2871 {}} {258 0 0-3792 {}} {259 0 0-3794 {}}} SUCCS {{259 0 0-3796 {}}} CYCLES {}}
+set a(0-3796) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#282 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-2847 XREFS 21974 LOC {1 0.187338 1 0.5473063 1 0.5473063 1 0.5803430701789505 1 0.5803430701789505} PREDS {{146 0 0-2871 {}} {258 0 0-3790 {}} {259 0 0-3795 {}}} SUCCS {{259 0 0-3797 {}}} CYCLES {}}
+set a(0-3797) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#286 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 21975 LOC {1 0.409999425 1 0.580343125 1 0.580343125 1 0.618632584496936 1 0.618632584496936} PREDS {{146 0 0-2871 {}} {258 0 0-3785 {}} {259 0 0-3796 {}}} SUCCS {{258 0 0-3803 {}}} CYCLES {}}
+set a(0-3798) {NAME ACC1-1:slc(acc#10.psp)#54 TYPE READSLICE PAR 0-2847 XREFS 21976 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6186326249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3802 {}}} CYCLES {}}
+set a(0-3799) {NAME ACC1-1:slc(acc#10.psp)#55 TYPE READSLICE PAR 0-2847 XREFS 21977 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6186326249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3802 {}}} CYCLES {}}
+set a(0-3800) {NAME ACC1-1:slc(acc#10.psp)#56 TYPE READSLICE PAR 0-2847 XREFS 21978 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6186326249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3802 {}}} CYCLES {}}
+set a(0-3801) {NAME ACC1-1:slc(acc#10.psp)#47 TYPE READSLICE PAR 0-2847 XREFS 21979 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6186326249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3802 {}}} CYCLES {}}
+set a(0-3802) {NAME ACC1-1:conc#279 TYPE CONCATENATE PAR 0-2847 XREFS 21980 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.6186326249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3800 {}} {258 0 0-3799 {}} {258 0 0-3798 {}} {259 0 0-3801 {}}} SUCCS {{259 0 0-3803 {}}} CYCLES {}}
+set a(0-3803) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#289 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-2847 XREFS 21981 LOC {1 0.448288925 1 0.6186326249999999 1 0.6186326249999999 1 0.6665116879329679 1 0.6665116879329679} PREDS {{146 0 0-2871 {}} {258 0 0-3797 {}} {259 0 0-3802 {}}} SUCCS {{258 0 0-3834 {}}} CYCLES {}}
+set a(0-3804) {NAME ACC1-1:slc(acc#10.psp)#17 TYPE READSLICE PAR 0-2847 XREFS 21982 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6186326249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3807 {}}} CYCLES {}}
+set a(0-3805) {NAME ACC1-1:slc(acc.idiv#2)#25 TYPE READSLICE PAR 0-2847 XREFS 21983 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6186326249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3806 {}}} CYCLES {}}
+set a(0-3806) {NAME ACC1-1:exs#48 TYPE SIGNEXTEND PAR 0-2847 XREFS 21984 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.6186326249999999} PREDS {{146 0 0-2871 {}} {259 0 0-3805 {}}} SUCCS {{259 0 0-3807 {}}} CYCLES {}}
+set a(0-3807) {NAME ACC1-1:conc#254 TYPE CONCATENATE PAR 0-2847 XREFS 21985 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.6186326249999999} PREDS {{146 0 0-2871 {}} {258 0 0-3804 {}} {259 0 0-3806 {}}} SUCCS {{259 0 0-3808 {}}} CYCLES {}}
+set a(0-3808) {NAME ACC1-1:exs#544 TYPE SIGNEXTEND PAR 0-2847 XREFS 21986 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.6186326249999999} PREDS {{146 0 0-2871 {}} {259 0 0-3807 {}}} SUCCS {{258 0 0-3833 {}}} CYCLES {}}
+set a(0-3809) {NAME ACC1-1:slc(acc#10.psp)#52 TYPE READSLICE PAR 0-2847 XREFS 21987 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.580343125} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3812 {}}} CYCLES {}}
+set a(0-3810) {NAME ACC1-1:slc(acc#10.psp)#53 TYPE READSLICE PAR 0-2847 XREFS 21988 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.580343125} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3812 {}}} CYCLES {}}
+set a(0-3811) {NAME ACC1-1:slc(acc#10.psp)#46 TYPE READSLICE PAR 0-2847 XREFS 21989 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.580343125} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3812 {}}} CYCLES {}}
+set a(0-3812) {NAME ACC1-1:conc#278 TYPE CONCATENATE PAR 0-2847 XREFS 21990 LOC {1 0.14655495 1 0.580343125 1 0.580343125 1 0.580343125} PREDS {{146 0 0-2871 {}} {258 0 0-3810 {}} {258 0 0-3809 {}} {259 0 0-3811 {}}} SUCCS {{258 0 0-3832 {}}} CYCLES {}}
+set a(0-3813) {NAME ACC1-1:slc(acc.idiv#2)#9 TYPE READSLICE PAR 0-2847 XREFS 21991 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.4920039} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3814 {}}} CYCLES {}}
+set a(0-3814) {NAME ACC1-1:exs#40 TYPE SIGNEXTEND PAR 0-2847 XREFS 21992 LOC {1 0.14655495 1 0.4920039 1 0.4920039 1 0.4920039} PREDS {{146 0 0-2871 {}} {259 0 0-3813 {}}} SUCCS {{258 0 0-3817 {}}} CYCLES {}}
+set a(0-3815) {NAME ACC1-1:slc(acc.idiv#2)#11 TYPE READSLICE PAR 0-2847 XREFS 21993 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.4920039} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3816 {}}} CYCLES {}}
+set a(0-3816) {NAME ACC1-1:exs#41 TYPE SIGNEXTEND PAR 0-2847 XREFS 21994 LOC {1 0.14655495 1 0.4920039 1 0.4920039 1 0.4920039} PREDS {{146 0 0-2871 {}} {259 0 0-3815 {}}} SUCCS {{259 0 0-3817 {}}} CYCLES {}}
+set a(0-3817) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#276 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-2847 XREFS 21995 LOC {1 0.14655495 1 0.4920039 1 0.4920039 1 0.5327869100894752 1 0.5327869100894752} PREDS {{146 0 0-2871 {}} {258 0 0-3814 {}} {259 0 0-3816 {}}} SUCCS {{258 0 0-3831 {}}} CYCLES {}}
+set a(0-3818) {NAME ACC1-1:slc(acc.idiv#2)#1 TYPE READSLICE PAR 0-2847 XREFS 21996 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.485230775} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3819 {}}} CYCLES {}}
+set a(0-3819) {NAME ACC1-1:exs#36 TYPE SIGNEXTEND PAR 0-2847 XREFS 21997 LOC {1 0.14655495 1 0.485230775 1 0.485230775 1 0.485230775} PREDS {{146 0 0-2871 {}} {259 0 0-3818 {}}} SUCCS {{259 0 0-3820 {}}} CYCLES {}}
+set a(0-3820) {NAME ACC1:conc#608 TYPE CONCATENATE PAR 0-2847 XREFS 21998 LOC {1 0.14655495 1 0.485230775 1 0.485230775 1 0.485230775} PREDS {{146 0 0-2871 {}} {259 0 0-3819 {}}} SUCCS {{258 0 0-3829 {}}} CYCLES {}}
+set a(0-3821) {NAME ACC1-1:slc(acc.idiv#2)#3 TYPE READSLICE PAR 0-2847 XREFS 21999 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.485230775} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3822 {}}} CYCLES {}}
+set a(0-3822) {NAME ACC1-1:exs#37 TYPE SIGNEXTEND PAR 0-2847 XREFS 22000 LOC {1 0.14655495 1 0.485230775 1 0.485230775 1 0.485230775} PREDS {{146 0 0-2871 {}} {259 0 0-3821 {}}} SUCCS {{258 0 0-3828 {}}} CYCLES {}}
+set a(0-3823) {NAME ACC1-1:slc(acc.idiv#2)#45 TYPE READSLICE PAR 0-2847 XREFS 22001 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.485230775} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3827 {}}} CYCLES {}}
+set a(0-3824) {NAME ACC1-1:slc(acc.imod#11)#1 TYPE READSLICE PAR 0-2847 XREFS 22002 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.485230775} PREDS {{146 0 0-2871 {}} {258 0 0-3097 {}}} SUCCS {{259 0 0-3825 {}}} CYCLES {}}
+set a(0-3825) {NAME ACC1-1:not#92 TYPE NOT PAR 0-2847 XREFS 22003 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.485230775} PREDS {{146 0 0-2871 {}} {259 0 0-3824 {}}} SUCCS {{258 0 0-3827 {}}} CYCLES {}}
+set a(0-3826) {NAME ACC1-1:slc(acc.imod#11)#2 TYPE READSLICE PAR 0-2847 XREFS 22004 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.485230775} PREDS {{146 0 0-2871 {}} {258 0 0-3097 {}}} SUCCS {{259 0 0-3827 {}}} CYCLES {}}
+set a(0-3827) {NAME ACC1-1:and#5 TYPE AND PAR 0-2847 XREFS 22005 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.485230775} PREDS {{146 0 0-2871 {}} {258 0 0-3825 {}} {258 0 0-3823 {}} {259 0 0-3826 {}}} SUCCS {{259 0 0-3828 {}}} CYCLES {}}
+set a(0-3828) {NAME ACC1:conc#609 TYPE CONCATENATE PAR 0-2847 XREFS 22006 LOC {1 0.3836787 1 0.485230775 1 0.485230775 1 0.485230775} PREDS {{146 0 0-2871 {}} {258 0 0-3822 {}} {259 0 0-3827 {}}} SUCCS {{259 0 0-3829 {}}} CYCLES {}}
+set a(0-3829) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#275 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22007 LOC {1 0.3836787 1 0.485230775 1 0.485230775 1 0.5327869020708271 1 0.5327869020708271} PREDS {{146 0 0-2871 {}} {258 0 0-3820 {}} {259 0 0-3828 {}}} SUCCS {{259 0 0-3830 {}}} CYCLES {}}
+set a(0-3830) {NAME ACC1:slc#81 TYPE READSLICE PAR 0-2847 XREFS 22008 LOC {1 0.43123487499999996 1 0.53278695 1 0.53278695 1 0.53278695} PREDS {{146 0 0-2871 {}} {259 0 0-3829 {}}} SUCCS {{259 0 0-3831 {}}} CYCLES {}}
+set a(0-3831) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#281 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22009 LOC {1 0.43123487499999996 1 0.53278695 1 0.53278695 1 0.5803430770708271 1 0.5803430770708271} PREDS {{146 0 0-2871 {}} {258 0 0-3817 {}} {259 0 0-3830 {}}} SUCCS {{259 0 0-3832 {}}} CYCLES {}}
+set a(0-3832) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#285 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 22010 LOC {1 0.47879105 1 0.580343125 1 0.580343125 1 0.618632584496936 1 0.618632584496936} PREDS {{146 0 0-2871 {}} {258 0 0-3812 {}} {259 0 0-3831 {}}} SUCCS {{259 0 0-3833 {}}} CYCLES {}}
+set a(0-3833) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#288 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-2847 XREFS 22011 LOC {1 0.51708055 1 0.6186326249999999 1 0.6186326249999999 1 0.6665116879329679 1 0.6665116879329679} PREDS {{146 0 0-2871 {}} {258 0 0-3808 {}} {259 0 0-3832 {}}} SUCCS {{259 0 0-3834 {}}} CYCLES {}}
+set a(0-3834) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#291 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-2847 XREFS 22012 LOC {1 0.564959675 1 0.66651175 1 0.66651175 1 0.7188962027684257 1 0.7188962027684257} PREDS {{146 0 0-2871 {}} {258 0 0-3803 {}} {259 0 0-3833 {}}} SUCCS {{259 0 0-3835 {}}} CYCLES {}}
+set a(0-3835) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#294 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 22013 LOC {1 0.704907925 1 0.71889625 1 0.71889625 1 0.7900803533364114 1 0.7900803533364114} PREDS {{146 0 0-2871 {}} {258 0 0-3763 {}} {259 0 0-3834 {}}} SUCCS {{258 0 0-3847 {}}} CYCLES {}}
+set a(0-3836) {NAME ACC1-1:slc(acc#10.psp)#62 TYPE READSLICE PAR 0-2847 XREFS 22014 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3838 {}}} CYCLES {}}
+set a(0-3837) {NAME ACC1-1:slc(acc#10.psp)#49 TYPE READSLICE PAR 0-2847 XREFS 22015 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3838 {}}} CYCLES {}}
+set a(0-3838) {NAME ACC1-1:conc#281 TYPE CONCATENATE PAR 0-2847 XREFS 22016 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.708741125} PREDS {{146 0 0-2871 {}} {258 0 0-3836 {}} {259 0 0-3837 {}}} SUCCS {{258 0 0-3846 {}}} CYCLES {}}
+set a(0-3839) {NAME ACC1-1:slc(acc#10.psp)#66 TYPE READSLICE PAR 0-2847 XREFS 22017 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3845 {}}} CYCLES {}}
+set a(0-3840) {NAME ACC1-1:slc(acc#10.psp)#67 TYPE READSLICE PAR 0-2847 XREFS 22018 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3845 {}}} CYCLES {}}
+set a(0-3841) {NAME ACC1-1:slc(acc#10.psp)#68 TYPE READSLICE PAR 0-2847 XREFS 22019 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3845 {}}} CYCLES {}}
+set a(0-3842) {NAME ACC1-1:slc(acc#10.psp)#51 TYPE READSLICE PAR 0-2847 XREFS 22020 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{258 0 0-3845 {}}} CYCLES {}}
+set a(0-3843) {NAME ACC1-1:slc(acc.idiv#2)#27 TYPE READSLICE PAR 0-2847 XREFS 22021 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-2871 {}} {258 0 0-3030 {}}} SUCCS {{259 0 0-3844 {}}} CYCLES {}}
+set a(0-3844) {NAME ACC1-1:exs#49 TYPE SIGNEXTEND PAR 0-2847 XREFS 22022 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.708741125} PREDS {{146 0 0-2871 {}} {259 0 0-3843 {}}} SUCCS {{259 0 0-3845 {}}} CYCLES {}}
+set a(0-3845) {NAME ACC1-1:conc#287 TYPE CONCATENATE PAR 0-2847 XREFS 22023 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.708741125} PREDS {{146 0 0-2871 {}} {258 0 0-3842 {}} {258 0 0-3841 {}} {258 0 0-3840 {}} {258 0 0-3839 {}} {259 0 0-3844 {}}} SUCCS {{259 0 0-3846 {}}} CYCLES {}}
+set a(0-3846) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,11) AREA_SCORE 11.24 QUANTITY 2 NAME ACC1:acc#293 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-2847 XREFS 22024 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.7900803533364112 1 0.7900803533364112} PREDS {{146 0 0-2871 {}} {258 0 0-3838 {}} {259 0 0-3845 {}}} SUCCS {{259 0 0-3847 {}}} CYCLES {}}
+set a(0-3847) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,13) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1-1:acc#124 TYPE ACCU DELAY {1.04 ns} LIBRARY_DELAY {1.04 ns} PAR 0-2847 XREFS 22025 LOC {1 0.776092075 1 0.7900804 1 0.7900804 1 0.8552960313734284 1 0.8552960313734284} PREDS {{146 0 0-2871 {}} {258 0 0-3835 {}} {259 0 0-3846 {}}} SUCCS {{258 0 0-3911 {}}} CYCLES {}}
+set a(0-3848) {NAME ACC1-3:slc(acc#10.psp)#57 TYPE READSLICE PAR 0-2847 XREFS 22026 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.77811255} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3853 {}}} CYCLES {}}
+set a(0-3849) {NAME ACC1-3:slc(acc#10.psp)#58 TYPE READSLICE PAR 0-2847 XREFS 22027 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.77811255} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3853 {}}} CYCLES {}}
+set a(0-3850) {NAME ACC1-3:slc(acc#10.psp)#59 TYPE READSLICE PAR 0-2847 XREFS 22028 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.77811255} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3853 {}}} CYCLES {}}
+set a(0-3851) {NAME ACC1-3:slc(acc#10.psp)#60 TYPE READSLICE PAR 0-2847 XREFS 22029 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.77811255} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3853 {}}} CYCLES {}}
+set a(0-3852) {NAME ACC1-3:slc(acc#10.psp)#48 TYPE READSLICE PAR 0-2847 XREFS 22030 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.77811255} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3853 {}}} CYCLES {}}
+set a(0-3853) {NAME ACC1-3:conc#280 TYPE CONCATENATE PAR 0-2847 XREFS 22031 LOC {1 0.14655495 1 0.77811255 1 0.77811255 1 0.77811255} PREDS {{146 0 0-2871 {}} {258 0 0-3851 {}} {258 0 0-3850 {}} {258 0 0-3849 {}} {258 0 0-3848 {}} {259 0 0-3852 {}}} SUCCS {{258 0 0-3910 {}}} CYCLES {}}
+set a(0-3854) {NAME ACC1-3:slc(acc#10.psp)#63 TYPE READSLICE PAR 0-2847 XREFS 22032 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.72572805} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3859 {}}} CYCLES {}}
+set a(0-3855) {NAME ACC1-3:slc(acc#10.psp)#64 TYPE READSLICE PAR 0-2847 XREFS 22033 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.72572805} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3859 {}}} CYCLES {}}
+set a(0-3856) {NAME ACC1-3:slc(acc#10.psp)#50 TYPE READSLICE PAR 0-2847 XREFS 22034 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.72572805} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3859 {}}} CYCLES {}}
+set a(0-3857) {NAME ACC1-3:slc(acc#10.psp)#65 TYPE READSLICE PAR 0-2847 XREFS 22035 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.72572805} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3858 {}}} CYCLES {}}
+set a(0-3858) {NAME ACC1-3:exs#543 TYPE SIGNEXTEND PAR 0-2847 XREFS 22036 LOC {1 0.14655495 1 0.72572805 1 0.72572805 1 0.72572805} PREDS {{146 0 0-2871 {}} {259 0 0-3857 {}}} SUCCS {{259 0 0-3859 {}}} CYCLES {}}
+set a(0-3859) {NAME ACC1-3:conc#285 TYPE CONCATENATE PAR 0-2847 XREFS 22037 LOC {1 0.14655495 1 0.72572805 1 0.72572805 1 0.72572805} PREDS {{146 0 0-2871 {}} {258 0 0-3856 {}} {258 0 0-3855 {}} {258 0 0-3854 {}} {259 0 0-3858 {}}} SUCCS {{258 0 0-3909 {}}} CYCLES {}}
+set a(0-3860) {NAME ACC1-3:slc(acc#10.psp)#36 TYPE READSLICE PAR 0-2847 XREFS 22038 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.682526275} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3864 {}}} CYCLES {}}
+set a(0-3861) {NAME ACC1-3:slc(acc#10.psp)#37 TYPE READSLICE PAR 0-2847 XREFS 22039 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.682526275} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{258 0 0-3864 {}}} CYCLES {}}
+set a(0-3862) {NAME ACC1-3:slc(acc.idiv#2)#29 TYPE READSLICE PAR 0-2847 XREFS 22040 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.682526275} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3863 {}}} CYCLES {}}
+set a(0-3863) {NAME ACC1-3:exs#50 TYPE SIGNEXTEND PAR 0-2847 XREFS 22041 LOC {1 0.14655495 1 0.682526275 1 0.682526275 1 0.682526275} PREDS {{146 0 0-2871 {}} {259 0 0-3862 {}}} SUCCS {{259 0 0-3864 {}}} CYCLES {}}
+set a(0-3864) {NAME ACC1-3:conc#289 TYPE CONCATENATE PAR 0-2847 XREFS 22042 LOC {1 0.14655495 1 0.682526275 1 0.682526275 1 0.682526275} PREDS {{146 0 0-2871 {}} {258 0 0-3861 {}} {258 0 0-3860 {}} {259 0 0-3863 {}}} SUCCS {{258 0 0-3908 {}}} CYCLES {}}
+set a(0-3865) {NAME ACC1-3:slc(acc.idiv#2)#5 TYPE READSLICE PAR 0-2847 XREFS 22043 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3866 {}}} CYCLES {}}
+set a(0-3866) {NAME ACC1-3:exs#38 TYPE SIGNEXTEND PAR 0-2847 XREFS 22044 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3865 {}}} SUCCS {{259 0 0-3867 {}}} CYCLES {}}
+set a(0-3867) {NAME ACC1:conc#591 TYPE CONCATENATE PAR 0-2847 XREFS 22045 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3866 {}}} SUCCS {{258 0 0-3875 {}}} CYCLES {}}
+set a(0-3868) {NAME ACC1-3:slc(acc.idiv#2)#7 TYPE READSLICE PAR 0-2847 XREFS 22046 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3869 {}}} CYCLES {}}
+set a(0-3869) {NAME ACC1-3:exs#39 TYPE SIGNEXTEND PAR 0-2847 XREFS 22047 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3868 {}}} SUCCS {{258 0 0-3874 {}}} CYCLES {}}
+set a(0-3870) {NAME ACC1-3:slc(acc.imod#11) TYPE READSLICE PAR 0-2847 XREFS 22048 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3319 {}}} SUCCS {{258 0 0-3873 {}}} CYCLES {}}
+set a(0-3871) {NAME ACC1-3:slc(acc.idiv#2)#44 TYPE READSLICE PAR 0-2847 XREFS 22049 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3872 {}}} CYCLES {}}
+set a(0-3872) {NAME ACC1-3:not#91 TYPE NOT PAR 0-2847 XREFS 22050 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3871 {}}} SUCCS {{259 0 0-3873 {}}} CYCLES {}}
+set a(0-3873) {NAME ACC1-3:nand#2 TYPE NAND PAR 0-2847 XREFS 22051 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3870 {}} {259 0 0-3872 {}}} SUCCS {{259 0 0-3874 {}}} CYCLES {}}
+set a(0-3874) {NAME ACC1:conc#592 TYPE CONCATENATE PAR 0-2847 XREFS 22052 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3869 {}} {259 0 0-3873 {}}} SUCCS {{259 0 0-3875 {}}} CYCLES {}}
+set a(0-3875) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#247 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22053 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.5816229770708271} PREDS {{146 0 0-2871 {}} {258 0 0-3867 {}} {259 0 0-3874 {}}} SUCCS {{259 0 0-3876 {}}} CYCLES {}}
+set a(0-3876) {NAME ACC1:slc#73 TYPE READSLICE PAR 0-2847 XREFS 22054 LOC {1 0.43123487499999996 1 0.581623025 1 0.581623025 1 0.581623025} PREDS {{146 0 0-2871 {}} {259 0 0-3875 {}}} SUCCS {{258 0 0-3887 {}}} CYCLES {}}
+set a(0-3877) {NAME ACC1-3:slc(acc.idiv#2)#15 TYPE READSLICE PAR 0-2847 XREFS 22055 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3878 {}}} CYCLES {}}
+set a(0-3878) {NAME ACC1-3:exs#43 TYPE SIGNEXTEND PAR 0-2847 XREFS 22056 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3877 {}}} SUCCS {{259 0 0-3879 {}}} CYCLES {}}
+set a(0-3879) {NAME ACC1:conc#589 TYPE CONCATENATE PAR 0-2847 XREFS 22057 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3878 {}}} SUCCS {{258 0 0-3885 {}}} CYCLES {}}
+set a(0-3880) {NAME ACC1-3:slc(acc.idiv#2)#17 TYPE READSLICE PAR 0-2847 XREFS 22058 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3881 {}}} CYCLES {}}
+set a(0-3881) {NAME ACC1-3:exs#44 TYPE SIGNEXTEND PAR 0-2847 XREFS 22059 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3880 {}}} SUCCS {{258 0 0-3884 {}}} CYCLES {}}
+set a(0-3882) {NAME ACC1-3:slc(acc.imod#10)#12 TYPE READSLICE PAR 0-2847 XREFS 22060 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3310 {}}} SUCCS {{259 0 0-3883 {}}} CYCLES {}}
+set a(0-3883) {NAME ACC1-3:not#150 TYPE NOT PAR 0-2847 XREFS 22061 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3882 {}}} SUCCS {{259 0 0-3884 {}}} CYCLES {}}
+set a(0-3884) {NAME ACC1:conc#590 TYPE CONCATENATE PAR 0-2847 XREFS 22062 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3881 {}} {259 0 0-3883 {}}} SUCCS {{259 0 0-3885 {}}} CYCLES {}}
+set a(0-3885) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#246 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22063 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.5816229770708271} PREDS {{146 0 0-2871 {}} {258 0 0-3879 {}} {259 0 0-3884 {}}} SUCCS {{259 0 0-3886 {}}} CYCLES {}}
+set a(0-3886) {NAME ACC1:slc#72 TYPE READSLICE PAR 0-2847 XREFS 22064 LOC {1 0.40398894999999996 1 0.581623025 1 0.581623025 1 0.581623025} PREDS {{146 0 0-2871 {}} {259 0 0-3885 {}}} SUCCS {{259 0 0-3887 {}}} CYCLES {}}
+set a(0-3887) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#253 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22065 LOC {1 0.43123487499999996 1 0.581623025 1 0.581623025 1 0.6291791520708271 1 0.6291791520708271} PREDS {{146 0 0-2871 {}} {258 0 0-3876 {}} {259 0 0-3886 {}}} SUCCS {{258 0 0-3907 {}}} CYCLES {}}
+set a(0-3888) {NAME ACC1-3:slc(acc.idiv#2)#13 TYPE READSLICE PAR 0-2847 XREFS 22066 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3889 {}}} CYCLES {}}
+set a(0-3889) {NAME ACC1-3:exs#42 TYPE SIGNEXTEND PAR 0-2847 XREFS 22067 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3888 {}}} SUCCS {{259 0 0-3890 {}}} CYCLES {}}
+set a(0-3890) {NAME ACC1:conc#587 TYPE CONCATENATE PAR 0-2847 XREFS 22068 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3889 {}}} SUCCS {{258 0 0-3895 {}}} CYCLES {}}
+set a(0-3891) {NAME ACC1-3:slc(acc.idiv#2)#23 TYPE READSLICE PAR 0-2847 XREFS 22069 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3892 {}}} CYCLES {}}
+set a(0-3892) {NAME ACC1-3:exs#47 TYPE SIGNEXTEND PAR 0-2847 XREFS 22070 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3891 {}}} SUCCS {{258 0 0-3894 {}}} CYCLES {}}
+set a(0-3893) {NAME ACC1-3:slc(acc.imod#10)#11 TYPE READSLICE PAR 0-2847 XREFS 22071 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3310 {}}} SUCCS {{259 0 0-3894 {}}} CYCLES {}}
+set a(0-3894) {NAME ACC1:conc#588 TYPE CONCATENATE PAR 0-2847 XREFS 22072 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3892 {}} {259 0 0-3893 {}}} SUCCS {{259 0 0-3895 {}}} CYCLES {}}
+set a(0-3895) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#245 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22073 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.5816229770708271} PREDS {{146 0 0-2871 {}} {258 0 0-3890 {}} {259 0 0-3894 {}}} SUCCS {{259 0 0-3896 {}}} CYCLES {}}
+set a(0-3896) {NAME ACC1:slc#71 TYPE READSLICE PAR 0-2847 XREFS 22074 LOC {1 0.40398894999999996 1 0.581623025 1 0.581623025 1 0.581623025} PREDS {{146 0 0-2871 {}} {259 0 0-3895 {}}} SUCCS {{258 0 0-3906 {}}} CYCLES {}}
+set a(0-3897) {NAME ACC1-3:slc(acc.idiv#2)#19 TYPE READSLICE PAR 0-2847 XREFS 22075 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3898 {}}} CYCLES {}}
+set a(0-3898) {NAME ACC1-3:exs#45 TYPE SIGNEXTEND PAR 0-2847 XREFS 22076 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3897 {}}} SUCCS {{259 0 0-3899 {}}} CYCLES {}}
+set a(0-3899) {NAME ACC1:conc#585 TYPE CONCATENATE PAR 0-2847 XREFS 22077 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3898 {}}} SUCCS {{258 0 0-3904 {}}} CYCLES {}}
+set a(0-3900) {NAME ACC1-3:slc(acc.idiv#2)#21 TYPE READSLICE PAR 0-2847 XREFS 22078 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3252 {}}} SUCCS {{259 0 0-3901 {}}} CYCLES {}}
+set a(0-3901) {NAME ACC1-3:exs#46 TYPE SIGNEXTEND PAR 0-2847 XREFS 22079 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {259 0 0-3900 {}}} SUCCS {{258 0 0-3903 {}}} CYCLES {}}
+set a(0-3902) {NAME ACC1-3:slc(ACC1:acc#113.psp)#9 TYPE READSLICE PAR 0-2847 XREFS 22080 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3292 {}}} SUCCS {{259 0 0-3903 {}}} CYCLES {}}
+set a(0-3903) {NAME ACC1:conc#586 TYPE CONCATENATE PAR 0-2847 XREFS 22081 LOC {1 0.267931 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-2871 {}} {258 0 0-3901 {}} {259 0 0-3902 {}}} SUCCS {{259 0 0-3904 {}}} CYCLES {}}
+set a(0-3904) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#244 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22082 LOC {1 0.267931 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.5816229770708271} PREDS {{146 0 0-2871 {}} {258 0 0-3899 {}} {259 0 0-3903 {}}} SUCCS {{259 0 0-3905 {}}} CYCLES {}}
+set a(0-3905) {NAME ACC1:slc#70 TYPE READSLICE PAR 0-2847 XREFS 22083 LOC {1 0.315487175 1 0.581623025 1 0.581623025 1 0.581623025} PREDS {{146 0 0-2871 {}} {259 0 0-3904 {}}} SUCCS {{259 0 0-3906 {}}} CYCLES {}}
+set a(0-3906) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#252 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22084 LOC {1 0.40398894999999996 1 0.581623025 1 0.581623025 1 0.6291791520708271 1 0.6291791520708271} PREDS {{146 0 0-2871 {}} {258 0 0-3896 {}} {259 0 0-3905 {}}} SUCCS {{259 0 0-3907 {}}} CYCLES {}}
+set a(0-3907) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#257 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-2847 XREFS 22085 LOC {1 0.47879105 1 0.6291791999999999 1 0.6291791999999999 1 0.6825262201789504 1 0.6825262201789504} PREDS {{146 0 0-2871 {}} {258 0 0-3887 {}} {259 0 0-3906 {}}} SUCCS {{259 0 0-3908 {}}} CYCLES {}}
+set a(0-3908) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME ACC1:acc#260 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 22086 LOC {1 0.532138125 1 0.682526275 1 0.682526275 1 0.7257279984103023 1 0.7257279984103023} PREDS {{146 0 0-2871 {}} {258 0 0-3864 {}} {259 0 0-3907 {}}} SUCCS {{259 0 0-3909 {}}} CYCLES {}}
+set a(0-3909) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#263 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-2847 XREFS 22087 LOC {1 0.5753399 1 0.72572805 1 0.72572805 1 0.7781125027684257 1 0.7781125027684257} PREDS {{146 0 0-2871 {}} {258 0 0-3859 {}} {259 0 0-3908 {}}} SUCCS {{259 0 0-3910 {}}} CYCLES {}}
+set a(0-3910) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,0,10) AREA_SCORE 10.25 QUANTITY 5 NAME ACC1:acc#265 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-2847 XREFS 22088 LOC {1 0.6277244 1 0.77811255 1 0.77811255 1 0.85529603186502 1 0.85529603186502} PREDS {{146 0 0-2871 {}} {258 0 0-3853 {}} {259 0 0-3909 {}}} SUCCS {{259 0 0-3911 {}}} CYCLES {}}
+set a(0-3911) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,13) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#267 TYPE ACCU DELAY {1.04 ns} LIBRARY_DELAY {1.04 ns} PAR 0-2847 XREFS 22089 LOC {1 0.8413077499999999 1 0.8552960749999999 1 0.8552960749999999 1 0.9205117063734283 1 0.9205117063734283} PREDS {{146 0 0-2871 {}} {258 0 0-3847 {}} {259 0 0-3910 {}}} SUCCS {{259 0 0-3912 {}}} CYCLES {}}
+set a(0-3912) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME ACC1-3:acc#124 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-2847 XREFS 22090 LOC {1 0.9065234249999999 1 0.92051175 1 0.92051175 1 0.9999999534997777 1 0.9999999534997777} PREDS {{146 0 0-2871 {}} {258 0 0-3700 {}} {259 0 0-3911 {}}} SUCCS {{259 0 0-3913 {}}} CYCLES {}}
+set a(0-3913) {NAME ACC1:exs#750 TYPE SIGNEXTEND PAR 0-2847 XREFS 22091 LOC {1 0.986011675 1 1.0 1 1.0 2 0.06859512499999999} PREDS {{146 0 0-2871 {}} {259 0 0-3912 {}}} SUCCS {{258 0 0-4005 {}}} CYCLES {}}
+set a(0-3914) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(3,1,2) AREA_SCORE 2.76 QUANTITY 4 NAME FRAME:for:mux#4 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22092 LOC {1 0.3471661 1 0.410926075 1 0.410926075 1 0.4339866375 1 0.6214930125} PREDS {{258 0 0-2870 {}} {262 0 0-4369 {}} {258 0 0-3235 {}} {258 0 0-2853 {}}} SUCCS {{258 0 0-4109 {}} {258 0 0-4208 {}} {258 0 0-4369 {}}} CYCLES {}}
+set a(0-3915) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(2,1,2) AREA_SCORE 1.84 QUANTITY 2 NAME FRAME:for:mux#5 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22093 LOC {1 0.374412025 1 0.410926075 1 0.410926075 1 0.4339866375 1 0.6214930125} PREDS {{258 0 0-2870 {}} {262 0 0-4370 {}} {258 0 0-3244 {}} {258 0 0-2852 {}}} SUCCS {{258 0 0-4083 {}} {258 0 0-4085 {}} {258 0 0-4097 {}} {258 0 0-4370 {}}} CYCLES {}}
+set a(0-3916) {NAME FRAME:for:asn#4 TYPE ASSIGN PAR 0-2847 XREFS 22094 LOC {0 1.0 1 0.55219575 1 0.55219575 1 0.6501168749999999} PREDS {{262 0 0-4371 {}}} SUCCS {{259 0 0-3917 {}} {256 0 0-4371 {}}} CYCLES {}}
+set a(0-3917) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#8 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22095 LOC {1 0.0 1 0.55219575 1 0.55219575 1 0.5752563125 1 0.6731774374999999} PREDS {{258 0 0-2870 {}} {258 0 0-2872 {}} {258 0 0-2862 {}} {259 0 0-3916 {}}} SUCCS {{258 0 0-3949 {}} {258 0 0-3955 {}} {258 0 0-3962 {}} {258 0 0-3990 {}} {258 0 0-3995 {}} {258 0 0-4001 {}} {258 0 0-4371 {}}} CYCLES {}}
+set a(0-3918) {NAME FRAME:for:asn#5 TYPE ASSIGN PAR 0-2847 XREFS 22096 LOC {0 1.0 1 0.55219575 1 0.55219575 1 0.6501168749999999} PREDS {{262 0 0-4371 {}}} SUCCS {{258 0 0-3920 {}} {256 0 0-4371 {}}} CYCLES {}}
+set a(0-3919) {NAME FRAME:for:asn#6 TYPE ASSIGN PAR 0-2847 XREFS 22097 LOC {0 1.0 1 0.55219575 1 0.55219575 1 0.6501168749999999} PREDS {{262 0 0-4372 {}}} SUCCS {{259 0 0-3920 {}} {256 0 0-4372 {}}} CYCLES {}}
+set a(0-3920) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#9 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22098 LOC {1 0.0 1 0.55219575 1 0.55219575 1 0.5752563125 1 0.6731774374999999} PREDS {{258 0 0-2870 {}} {258 0 0-3918 {}} {259 0 0-3919 {}}} SUCCS {{258 0 0-3948 {}} {258 0 0-3954 {}} {258 0 0-3961 {}} {258 0 0-3989 {}} {258 0 0-3994 {}} {258 0 0-4000 {}} {258 0 0-4372 {}}} CYCLES {}}
+set a(0-3921) {NAME FRAME:for:asn#7 TYPE ASSIGN PAR 0-2847 XREFS 22099 LOC {0 1.0 1 0.55219575 1 0.55219575 1 0.6501168749999999} PREDS {{262 0 0-4372 {}}} SUCCS {{259 0 0-3922 {}} {256 0 0-4372 {}}} CYCLES {}}
+set a(0-3922) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#10 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22100 LOC {1 0.0 1 0.55219575 1 0.55219575 1 0.5752563125 1 0.6731774374999999} PREDS {{258 0 0-2870 {}} {262 0 0-4373 {}} {259 0 0-3921 {}}} SUCCS {{258 0 0-3947 {}} {258 0 0-3953 {}} {258 0 0-3960 {}} {258 0 0-3988 {}} {258 0 0-3993 {}} {258 0 0-3999 {}} {258 0 0-4373 {}}} CYCLES {}}
+set a(0-3923) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(3,1,2) AREA_SCORE 2.76 QUANTITY 4 NAME FRAME:for:mux#14 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22101 LOC {1 0.319920175 1 0.55658895 1 0.55658895 1 0.5796495125 1 0.7671558875} PREDS {{258 0 0-2870 {}} {262 0 0-4376 {}} {258 0 0-3228 {}} {258 0 0-2854 {}}} SUCCS {{258 0 0-4227 {}} {258 0 0-4376 {}}} CYCLES {}}
+set a(0-3924) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(12,1,2) AREA_SCORE 11.03 QUANTITY 2 NAME FRAME:for:mux#17 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22102 LOC {1 0.14655495 1 0.29206689999999996 1 0.29206689999999996 1 0.31512746249999996 1 0.5026338375} PREDS {{258 0 0-2870 {}} {262 0 0-4377 {}} {258 0 0-3180 {}} {258 0 0-2856 {}}} SUCCS {{258 0 0-4016 {}} {258 0 0-4020 {}} {258 0 0-4024 {}} {258 0 0-4025 {}} {258 0 0-4028 {}} {258 0 0-4032 {}} {258 0 0-4036 {}} {258 0 0-4037 {}} {258 0 0-4038 {}} {258 0 0-4049 {}} {258 0 0-4052 {}} {258 0 0-4058 {}} {258 0 0-4061 {}} {258 0 0-4082 {}} {258 0 0-4098 {}} {258 0 0-4164 {}} {258 0 0-4167 {}} {258 0 0-4175 {}} {258 0 0-4178 {}} {258 0 0-4184 {}} {258 0 0-4187 {}} {258 0 0-4189 {}} {258 0 0-4194 {}} {258 0 0-4195 {}} {258 0 0-4199 {}} {258 0 0-4201 {}} {258 0 0-4235 {}} {258 0 0-4248 {}} {258 0 0-4253 {}} {258 0 0-4254 {}} {258 0 0-4258 {}} {258 0 0-4262 {}} {258 0 0-4266 {}} {258 0 0-4271 {}} {258 0 0-4272 {}} {258 0 0-4278 {}} {258 0 0-4283 {}} {258 0 0-4377 {}}} CYCLES {}}
+set a(0-3925) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(4,1,2) AREA_SCORE 3.68 QUANTITY 2 NAME FRAME:for:mux#20 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22103 LOC {1 0.258664325 1 0.410926075 1 0.410926075 1 0.4339866375 1 0.6214930125} PREDS {{258 0 0-2870 {}} {262 0 0-4378 {}} {258 0 0-3217 {}} {258 0 0-2855 {}}} SUCCS {{258 0 0-4119 {}} {258 0 0-4128 {}} {258 0 0-4141 {}} {258 0 0-4206 {}} {258 0 0-4378 {}}} CYCLES {}}
+set a(0-3926) {NAME not#16 TYPE NOT PAR 0-2847 XREFS 22104 LOC {1 0.0 1 0.251002 1 0.251002 1 0.438508375} PREDS {{258 0 0-2870 {}}} SUCCS {{259 0 0-3927 {}}} CYCLES {}}
+set a(0-3927) {NAME FRAME:for:exs#19 TYPE SIGNEXTEND PAR 0-2847 XREFS 22105 LOC {1 0.0 1 0.251002 1 0.251002 1 0.438508375} PREDS {{259 0 0-3926 {}}} SUCCS {{259 0 0-3928 {}}} CYCLES {}}
+set a(0-3928) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 2 NAME FRAME:for:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-2847 XREFS 22106 LOC {1 0.0 1 0.251002 1 0.251002 1 0.2674087312638539 1 0.4549151062638539} PREDS {{262 0 0-4380 {}} {259 0 0-3927 {}}} SUCCS {{258 0 0-3934 {}} {258 0 0-3935 {}} {258 0 0-3936 {}} {258 0 0-3937 {}} {258 0 0-3938 {}} {258 0 0-3941 {}} {258 0 0-3943 {}} {258 0 0-3950 {}} {258 0 0-3956 {}} {258 0 0-3963 {}} {258 0 0-3971 {}} {258 0 0-3973 {}} {258 0 0-3991 {}} {258 0 0-3996 {}} {258 0 0-4002 {}} {258 0 0-4009 {}} {256 0 0-4380 {}}} CYCLES {}}
+set a(0-3929) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(3,1,2) AREA_SCORE 2.76 QUANTITY 4 NAME FRAME:for:mux#25 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22107 LOC {1 0.3471661 1 0.410926075 1 0.410926075 1 0.4339866375 1 0.6214930125} PREDS {{258 0 0-2870 {}} {262 0 0-4381 {}} {258 0 0-3012 {}} {258 0 0-2858 {}}} SUCCS {{258 0 0-4054 {}} {258 0 0-4223 {}} {258 0 0-4381 {}}} CYCLES {}}
+set a(0-3930) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(2,1,2) AREA_SCORE 1.84 QUANTITY 2 NAME FRAME:for:mux#26 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22108 LOC {1 0.374412025 1 0.45736869999999996 1 0.45736869999999996 1 0.48042926249999995 1 0.6679356375} PREDS {{258 0 0-2870 {}} {262 0 0-4382 {}} {258 0 0-3021 {}} {258 0 0-2857 {}}} SUCCS {{258 0 0-4212 {}} {258 0 0-4214 {}} {258 0 0-4228 {}} {258 0 0-4382 {}}} CYCLES {}}
+set a(0-3931) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(3,1,2) AREA_SCORE 2.76 QUANTITY 4 NAME FRAME:for:mux#30 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22109 LOC {1 0.319920175 1 0.56237985 1 0.56237985 1 0.5854404125 1 0.7729467875} PREDS {{258 0 0-2870 {}} {262 0 0-4383 {}} {258 0 0-3005 {}} {258 0 0-2859 {}}} SUCCS {{258 0 0-4238 {}} {258 0 0-4383 {}}} CYCLES {}}
+set a(0-3932) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(12,1,2) AREA_SCORE 11.03 QUANTITY 2 NAME FRAME:for:mux#33 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22110 LOC {1 0.14655495 1 0.29206689999999996 1 0.29206689999999996 1 0.31512746249999996 1 0.5026338375} PREDS {{258 0 0-2870 {}} {262 0 0-4384 {}} {258 0 0-2957 {}} {258 0 0-2861 {}}} SUCCS {{258 0 0-4017 {}} {258 0 0-4021 {}} {258 0 0-4029 {}} {258 0 0-4033 {}} {258 0 0-4044 {}} {258 0 0-4045 {}} {258 0 0-4068 {}} {258 0 0-4071 {}} {258 0 0-4077 {}} {258 0 0-4080 {}} {258 0 0-4092 {}} {258 0 0-4095 {}} {258 0 0-4104 {}} {258 0 0-4107 {}} {258 0 0-4114 {}} {258 0 0-4117 {}} {258 0 0-4123 {}} {258 0 0-4126 {}} {258 0 0-4136 {}} {258 0 0-4139 {}} {258 0 0-4145 {}} {258 0 0-4148 {}} {258 0 0-4150 {}} {258 0 0-4155 {}} {258 0 0-4158 {}} {258 0 0-4160 {}} {258 0 0-4169 {}} {258 0 0-4180 {}} {258 0 0-4198 {}} {258 0 0-4211 {}} {258 0 0-4229 {}} {258 0 0-4249 {}} {258 0 0-4252 {}} {258 0 0-4257 {}} {258 0 0-4261 {}} {258 0 0-4279 {}} {258 0 0-4282 {}} {258 0 0-4384 {}}} CYCLES {}}
+set a(0-3933) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(4,1,2) AREA_SCORE 3.68 QUANTITY 2 NAME FRAME:for:mux#36 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22111 LOC {1 0.258664325 1 0.410926075 1 0.410926075 1 0.4339866375 1 0.6214930125} PREDS {{258 0 0-2870 {}} {262 0 0-4385 {}} {258 0 0-2994 {}} {258 0 0-2860 {}}} SUCCS {{258 0 0-4063 {}} {258 0 0-4073 {}} {258 0 0-4221 {}} {258 0 0-4239 {}} {258 0 0-4385 {}}} CYCLES {}}
+set a(0-3934) {NAME slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-2847 XREFS 22112 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-3928 {}}} SUCCS {{258 0 0-3942 {}}} CYCLES {}}
+set a(0-3935) {NAME slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-2847 XREFS 22113 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-3928 {}}} SUCCS {{258 0 0-3939 {}}} CYCLES {}}
+set a(0-3936) {NAME slc(i#6.lpi#1.dfm)#2 TYPE READSLICE PAR 0-2847 XREFS 22114 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-3928 {}}} SUCCS {{258 0 0-3945 {}}} CYCLES {}}
+set a(0-3937) {NAME slc(i#6.lpi#1.dfm)#3 TYPE READSLICE PAR 0-2847 XREFS 22115 LOC {1 0.016406775 1 0.267408775 1 0.267408775 3 1.0} PREDS {{258 0 0-3928 {}}} SUCCS {} CYCLES {}}
+set a(0-3938) {NAME FRAME:for:slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-2847 XREFS 22116 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-3928 {}}} SUCCS {{258 0 0-3940 {}}} CYCLES {}}
+set a(0-3939) {NAME FRAME:for:not#1 TYPE NOT PAR 0-2847 XREFS 22117 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-3935 {}}} SUCCS {{259 0 0-3940 {}}} CYCLES {}}
+set a(0-3940) {NAME FRAME:for:nand TYPE NAND PAR 0-2847 XREFS 22118 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-3938 {}} {259 0 0-3939 {}}} SUCCS {{258 0 0-3946 {}}} CYCLES {}}
+set a(0-3941) {NAME FRAME:for:slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-2847 XREFS 22119 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-3928 {}}} SUCCS {{259 0 0-3942 {}}} CYCLES {}}
+set a(0-3942) {NAME FRAME:for:nor TYPE NOR PAR 0-2847 XREFS 22120 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-3934 {}} {259 0 0-3941 {}}} SUCCS {{258 0 0-3946 {}}} CYCLES {}}
+set a(0-3943) {NAME FRAME:for:slc(i#6.lpi#1.dfm)#2 TYPE READSLICE PAR 0-2847 XREFS 22121 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-3928 {}}} SUCCS {{259 0 0-3944 {}}} CYCLES {}}
+set a(0-3944) {NAME FRAME:for:not#2 TYPE NOT PAR 0-2847 XREFS 22122 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{259 0 0-3943 {}}} SUCCS {{259 0 0-3945 {}}} CYCLES {}}
+set a(0-3945) {NAME FRAME:for:and#3 TYPE AND PAR 0-2847 XREFS 22123 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-3936 {}} {259 0 0-3944 {}}} SUCCS {{259 0 0-3946 {}}} CYCLES {}}
+set a(0-3946) {NAME FRAME:for:or#3 TYPE OR PAR 0-2847 XREFS 22124 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-3942 {}} {258 0 0-3940 {}} {259 0 0-3945 {}}} SUCCS {{258 0 0-3951 {}} {258 0 0-3957 {}} {258 0 0-3964 {}}} CYCLES {}}
+set a(0-3947) {NAME {regs.operator[]#10:slc(regs.regs(2))} TYPE READSLICE PAR 0-2847 XREFS 22125 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-3922 {}}} SUCCS {{258 0 0-3950 {}}} CYCLES {}}
+set a(0-3948) {NAME {regs.operator[]#10:slc(regs.regs(1))} TYPE READSLICE PAR 0-2847 XREFS 22126 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-3920 {}}} SUCCS {{258 0 0-3950 {}}} CYCLES {}}
+set a(0-3949) {NAME {regs.operator[]#10:slc(regs.regs(0))} TYPE READSLICE PAR 0-2847 XREFS 22127 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-3917 {}}} SUCCS {{259 0 0-3950 {}}} CYCLES {}}
+set a(0-3950) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#10:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-2847 XREFS 22128 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6337841 1 0.807076025} PREDS {{258 0 0-3928 {}} {258 0 0-3948 {}} {258 0 0-3947 {}} {259 0 0-3949 {}}} SUCCS {{258 0 0-3952 {}}} CYCLES {}}
+set a(0-3951) {NAME FRAME:for:conc#6 TYPE CONCATENATE PAR 0-2847 XREFS 22129 LOC {1 0.016406775 1 0.63378415 1 0.63378415 1 0.807076075} PREDS {{258 0 0-3946 {}}} SUCCS {{259 0 0-3952 {}}} CYCLES {}}
+set a(0-3952) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#1 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-2847 XREFS 22130 LOC {1 0.08158839999999999 1 0.63378415 1 0.63378415 1 0.8267080124999999 1 0.9999999374999999} PREDS {{258 0 0-3950 {}} {259 0 0-3951 {}}} SUCCS {{258 0 0-3959 {}}} CYCLES {}}
+set a(0-3953) {NAME {regs.operator[]#11:slc(regs.regs(2))} TYPE READSLICE PAR 0-2847 XREFS 22131 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-3922 {}}} SUCCS {{258 0 0-3956 {}}} CYCLES {}}
+set a(0-3954) {NAME {regs.operator[]#11:slc(regs.regs(1))} TYPE READSLICE PAR 0-2847 XREFS 22132 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-3920 {}}} SUCCS {{258 0 0-3956 {}}} CYCLES {}}
+set a(0-3955) {NAME {regs.operator[]#11:slc(regs.regs(0))} TYPE READSLICE PAR 0-2847 XREFS 22133 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-3917 {}}} SUCCS {{259 0 0-3956 {}}} CYCLES {}}
+set a(0-3956) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#11:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-2847 XREFS 22134 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6337841 1 0.807076025} PREDS {{258 0 0-3928 {}} {258 0 0-3954 {}} {258 0 0-3953 {}} {259 0 0-3955 {}}} SUCCS {{258 0 0-3958 {}}} CYCLES {}}
+set a(0-3957) {NAME FRAME:for:conc#7 TYPE CONCATENATE PAR 0-2847 XREFS 22135 LOC {1 0.016406775 1 0.63378415 1 0.63378415 1 0.807076075} PREDS {{258 0 0-3946 {}}} SUCCS {{259 0 0-3958 {}}} CYCLES {}}
+set a(0-3958) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#2 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-2847 XREFS 22136 LOC {1 0.08158839999999999 1 0.63378415 1 0.63378415 1 0.8267080124999999 1 0.9999999374999999} PREDS {{258 0 0-3956 {}} {259 0 0-3957 {}}} SUCCS {{259 0 0-3959 {}}} CYCLES {}}
+set a(0-3959) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME FRAME:for:acc#23 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-2847 XREFS 22137 LOC {1 0.274512325 1 0.826708075 1 0.826708075 1 0.9061962784997777 2 0.10375282849977767} PREDS {{258 0 0-3952 {}} {259 0 0-3958 {}}} SUCCS {{258 0 0-3966 {}}} CYCLES {}}
+set a(0-3960) {NAME {regs.operator[]#9:slc(regs.regs(2))} TYPE READSLICE PAR 0-2847 XREFS 22138 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-3922 {}}} SUCCS {{258 0 0-3963 {}}} CYCLES {}}
+set a(0-3961) {NAME {regs.operator[]#9:slc(regs.regs(1))} TYPE READSLICE PAR 0-2847 XREFS 22139 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-3920 {}}} SUCCS {{258 0 0-3963 {}}} CYCLES {}}
+set a(0-3962) {NAME {regs.operator[]#9:slc(regs.regs(0))} TYPE READSLICE PAR 0-2847 XREFS 22140 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-3917 {}}} SUCCS {{259 0 0-3963 {}}} CYCLES {}}
+set a(0-3963) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#9:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-2847 XREFS 22141 LOC {1 0.0230606 1 0.6547446 1 0.6547446 1 0.71327235 1 0.807076025} PREDS {{258 0 0-3928 {}} {258 0 0-3961 {}} {258 0 0-3960 {}} {259 0 0-3962 {}}} SUCCS {{258 0 0-3965 {}}} CYCLES {}}
+set a(0-3964) {NAME FRAME:for:conc#5 TYPE CONCATENATE PAR 0-2847 XREFS 22142 LOC {1 0.016406775 1 0.7132723999999999 1 0.7132723999999999 1 0.807076075} PREDS {{258 0 0-3946 {}}} SUCCS {{259 0 0-3965 {}}} CYCLES {}}
+set a(0-3965) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-2847 XREFS 22143 LOC {1 0.08158839999999999 1 0.7132723999999999 1 0.7132723999999999 1 0.9061962625 1 0.9999999374999999} PREDS {{258 0 0-3963 {}} {259 0 0-3964 {}}} SUCCS {{259 0 0-3966 {}}} CYCLES {}}
+set a(0-3966) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,0,12,1,13) AREA_SCORE 14.00 QUANTITY 2 NAME FRAME:for:acc#24 TYPE ACCU DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-2847 XREFS 22144 LOC {1 0.354000575 1 0.9061963249999999 1 0.9061963249999999 1 0.9999999502166911 2 0.1975565002166912} PREDS {{258 0 0-3959 {}} {259 0 0-3965 {}}} SUCCS {{258 0 0-3970 {}}} CYCLES {}}
+set a(0-3967) {NAME FRAME:for:slc(in(0).sva) TYPE READSLICE PAR 0-2847 XREFS 22145 LOC {1 0.986011675 1 1.0 1 1.0 2 0.17449594999999998} PREDS {{258 0 0-3616 {}} {258 0 0-2851 {}}} SUCCS {{259 0 0-3968 {}}} CYCLES {}}
+set a(0-3968) {NAME FRAME:for:exs#20 TYPE SIGNEXTEND PAR 0-2847 XREFS 22146 LOC {1 0.986011675 2 0.17449594999999998 2 0.17449594999999998 2 0.17449594999999998} PREDS {{259 0 0-3967 {}}} SUCCS {{259 0 0-3969 {}}} CYCLES {}}
+set a(0-3969) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 2 NAME FRAME:for:mux#11 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22147 LOC {2 0.0 2 0.17449594999999998 2 0.17449594999999998 2 0.19755651249999998 2 0.19755651249999998} PREDS {{258 0 0-2870 {}} {262 0 0-4374 {}} {259 0 0-3968 {}}} SUCCS {{259 0 0-3970 {}} {256 0 0-4374 {}}} CYCLES {}}
+set a(0-3970) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,13,1,16) AREA_SCORE 17.00 QUANTITY 3 NAME FRAME:for:acc#20 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-2847 XREFS 22148 LOC {2 0.0230606 2 0.19755655 2 0.19755655 2 0.3034573281715468 2 0.3034573281715468} PREDS {{258 0 0-3966 {}} {259 0 0-3969 {}}} SUCCS {{258 0 0-4289 {}} {258 0 0-4374 {}}} CYCLES {}}
+set a(0-3971) {NAME i:slc(i#3)#1 TYPE READSLICE PAR 0-2847 XREFS 22149 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{258 0 0-3928 {}}} SUCCS {{259 0 0-3972 {}}} CYCLES {}}
+set a(0-3972) {NAME FRAME:for:not#4 TYPE NOT PAR 0-2847 XREFS 22150 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{259 0 0-3971 {}}} SUCCS {{258 0 0-3974 {}}} CYCLES {}}
+set a(0-3973) {NAME i:slc(i#3)#2 TYPE READSLICE PAR 0-2847 XREFS 22151 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{258 0 0-3928 {}}} SUCCS {{259 0 0-3974 {}}} CYCLES {}}
+set a(0-3974) {NAME FRAME:for:conc TYPE CONCATENATE PAR 0-2847 XREFS 22152 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{258 0 0-3972 {}} {259 0 0-3973 {}}} SUCCS {{259 0 0-3975 {}} {258 0 0-3976 {}} {258 0 0-3977 {}} {258 0 0-3978 {}} {258 0 0-3979 {}} {258 0 0-3983 {}}} CYCLES {}}
+set a(0-3975) {NAME slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-2847 XREFS 22153 LOC {1 0.016406775 1 0.267408775 1 0.267408775 3 1.0} PREDS {{259 0 0-3974 {}}} SUCCS {} CYCLES {}}
+set a(0-3976) {NAME slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-2847 XREFS 22154 LOC {1 0.016406775 1 0.267408775 1 0.267408775 3 1.0} PREDS {{258 0 0-3974 {}}} SUCCS {} CYCLES {}}
+set a(0-3977) {NAME slc(FRAME:for:conc.tmp)#2 TYPE READSLICE PAR 0-2847 XREFS 22155 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.7149628} PREDS {{258 0 0-3974 {}}} SUCCS {{258 0 0-3985 {}}} CYCLES {}}
+set a(0-3978) {NAME slc(FRAME:for:conc.tmp)#3 TYPE READSLICE PAR 0-2847 XREFS 22156 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{258 0 0-3974 {}}} SUCCS {{258 0 0-3980 {}}} CYCLES {}}
+set a(0-3979) {NAME FRAME:for:slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-2847 XREFS 22157 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{258 0 0-3974 {}}} SUCCS {{259 0 0-3980 {}}} CYCLES {}}
+set a(0-3980) {NAME FRAME:for:nand#1 TYPE NAND PAR 0-2847 XREFS 22158 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{258 0 0-3978 {}} {259 0 0-3979 {}}} SUCCS {{259 0 0-3981 {}}} CYCLES {}}
+set a(0-3981) {NAME FRAME:for:exs#22 TYPE SIGNEXTEND PAR 0-2847 XREFS 22159 LOC {1 0.016406775 1 0.619067775 1 0.619067775 1 0.6985560249999999} PREDS {{259 0 0-3980 {}}} SUCCS {{259 0 0-3982 {}}} CYCLES {}}
+set a(0-3982) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 2 NAME FRAME:for:and#4 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-2847 XREFS 22160 LOC {1 0.016406775 1 0.619067775 1 0.619067775 1 0.6354745062638539 1 0.7149627562638539} PREDS {{259 0 0-3981 {}}} SUCCS {{258 0 0-3987 {}}} CYCLES {}}
+set a(0-3983) {NAME FRAME:for:slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-2847 XREFS 22161 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.7149628} PREDS {{258 0 0-3974 {}}} SUCCS {{259 0 0-3984 {}}} CYCLES {}}
+set a(0-3984) {NAME FRAME:for:not#3 TYPE NOT PAR 0-2847 XREFS 22162 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.7149628} PREDS {{259 0 0-3983 {}}} SUCCS {{259 0 0-3985 {}}} CYCLES {}}
+set a(0-3985) {NAME FRAME:for:and#5 TYPE AND PAR 0-2847 XREFS 22163 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.7149628} PREDS {{258 0 0-3977 {}} {259 0 0-3984 {}}} SUCCS {{259 0 0-3986 {}}} CYCLES {}}
+set a(0-3986) {NAME FRAME:for:exs#23 TYPE SIGNEXTEND PAR 0-2847 XREFS 22164 LOC {1 0.016406775 1 0.63547455 1 0.63547455 1 0.7149628} PREDS {{259 0 0-3985 {}}} SUCCS {{259 0 0-3987 {}}} CYCLES {}}
+set a(0-3987) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(2,2) AREA_SCORE 1.46 QUANTITY 1 NAME FRAME:for:or#4 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-2847 XREFS 22165 LOC {1 0.03281355 1 0.63547455 1 0.63547455 1 0.6522169811077388 1 0.7317052311077389} PREDS {{258 0 0-3982 {}} {259 0 0-3986 {}}} SUCCS {{258 0 0-3992 {}} {258 0 0-3997 {}} {258 0 0-4003 {}}} CYCLES {}}
+set a(0-3988) {NAME {regs.operator[]#16:slc(regs.regs(2))} TYPE READSLICE PAR 0-2847 XREFS 22166 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6731774749999999} PREDS {{258 0 0-3922 {}}} SUCCS {{258 0 0-3991 {}}} CYCLES {}}
+set a(0-3989) {NAME {regs.operator[]#16:slc(regs.regs(1))} TYPE READSLICE PAR 0-2847 XREFS 22167 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6731774749999999} PREDS {{258 0 0-3920 {}}} SUCCS {{258 0 0-3991 {}}} CYCLES {}}
+set a(0-3990) {NAME {regs.operator[]#16:slc(regs.regs(0))} TYPE READSLICE PAR 0-2847 XREFS 22168 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6731774749999999} PREDS {{258 0 0-3917 {}}} SUCCS {{259 0 0-3991 {}}} CYCLES {}}
+set a(0-3991) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#16:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-2847 XREFS 22169 LOC {1 0.0230606 1 0.593689225 1 0.593689225 1 0.652216975 1 0.7317052249999999} PREDS {{258 0 0-3928 {}} {258 0 0-3989 {}} {258 0 0-3988 {}} {259 0 0-3990 {}}} SUCCS {{259 0 0-3992 {}}} CYCLES {}}
+set a(0-3992) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#7 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-2847 XREFS 22170 LOC {1 0.08158839999999999 1 0.652217025 1 0.652217025 1 0.8451408874999999 1 0.9246291375} PREDS {{258 0 0-3987 {}} {259 0 0-3991 {}}} SUCCS {{258 0 0-3998 {}}} CYCLES {}}
+set a(0-3993) {NAME {regs.operator[]#17:slc(regs.regs(2))} TYPE READSLICE PAR 0-2847 XREFS 22171 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6731774749999999} PREDS {{258 0 0-3922 {}}} SUCCS {{258 0 0-3996 {}}} CYCLES {}}
+set a(0-3994) {NAME {regs.operator[]#17:slc(regs.regs(1))} TYPE READSLICE PAR 0-2847 XREFS 22172 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6731774749999999} PREDS {{258 0 0-3920 {}}} SUCCS {{258 0 0-3996 {}}} CYCLES {}}
+set a(0-3995) {NAME {regs.operator[]#17:slc(regs.regs(0))} TYPE READSLICE PAR 0-2847 XREFS 22173 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6731774749999999} PREDS {{258 0 0-3917 {}}} SUCCS {{259 0 0-3996 {}}} CYCLES {}}
+set a(0-3996) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#17:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-2847 XREFS 22174 LOC {1 0.0230606 1 0.593689225 1 0.593689225 1 0.652216975 1 0.7317052249999999} PREDS {{258 0 0-3928 {}} {258 0 0-3994 {}} {258 0 0-3993 {}} {259 0 0-3995 {}}} SUCCS {{259 0 0-3997 {}}} CYCLES {}}
+set a(0-3997) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#8 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-2847 XREFS 22175 LOC {1 0.08158839999999999 1 0.652217025 1 0.652217025 1 0.8451408874999999 1 0.9246291375} PREDS {{258 0 0-3987 {}} {259 0 0-3996 {}}} SUCCS {{259 0 0-3998 {}}} CYCLES {}}
+set a(0-3998) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME FRAME:for:acc#25 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-2847 XREFS 22176 LOC {1 0.274512325 1 0.84514095 1 0.84514095 1 0.9205117063734284 1 0.9999999563734283} PREDS {{258 0 0-3992 {}} {259 0 0-3997 {}}} SUCCS {{258 0 0-4004 {}}} CYCLES {}}
+set a(0-3999) {NAME {regs.operator[]#15:slc(regs.regs(2))} TYPE READSLICE PAR 0-2847 XREFS 22177 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-3922 {}}} SUCCS {{258 0 0-4002 {}}} CYCLES {}}
+set a(0-4000) {NAME {regs.operator[]#15:slc(regs.regs(1))} TYPE READSLICE PAR 0-2847 XREFS 22178 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-3920 {}}} SUCCS {{258 0 0-4002 {}}} CYCLES {}}
+set a(0-4001) {NAME {regs.operator[]#15:slc(regs.regs(0))} TYPE READSLICE PAR 0-2847 XREFS 22179 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-3917 {}}} SUCCS {{259 0 0-4002 {}}} CYCLES {}}
+set a(0-4002) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#15:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-2847 XREFS 22180 LOC {1 0.0230606 1 0.669060025 1 0.669060025 1 0.7275877749999999 1 0.807076025} PREDS {{258 0 0-3928 {}} {258 0 0-4000 {}} {258 0 0-3999 {}} {259 0 0-4001 {}}} SUCCS {{259 0 0-4003 {}}} CYCLES {}}
+set a(0-4003) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#6 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-2847 XREFS 22181 LOC {1 0.08158839999999999 1 0.727587825 1 0.727587825 1 0.9205116874999999 1 0.9999999374999999} PREDS {{258 0 0-3987 {}} {259 0 0-4002 {}}} SUCCS {{259 0 0-4004 {}}} CYCLES {}}
+set a(0-4004) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME FRAME:for:acc#26 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-2847 XREFS 22182 LOC {1 0.34988312499999996 1 0.92051175 1 0.92051175 1 0.9999999534997777 2 0.09165567849977767} PREDS {{258 0 0-3998 {}} {259 0 0-4003 {}}} SUCCS {{258 0 0-4008 {}}} CYCLES {}}
+set a(0-4005) {NAME FRAME:for:slc(in(2).sva) TYPE READSLICE PAR 0-2847 XREFS 22183 LOC {1 0.986011675 1 1.0 1 1.0 2 0.06859512499999999} PREDS {{258 0 0-3913 {}} {258 0 0-2850 {}}} SUCCS {{259 0 0-4006 {}}} CYCLES {}}
+set a(0-4006) {NAME FRAME:for:exs#21 TYPE SIGNEXTEND PAR 0-2847 XREFS 22184 LOC {1 0.986011675 2 0.06859512499999999 2 0.06859512499999999 2 0.06859512499999999} PREDS {{259 0 0-4005 {}}} SUCCS {{259 0 0-4007 {}}} CYCLES {}}
+set a(0-4007) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 2 NAME FRAME:for:mux#12 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22185 LOC {2 0.0 2 0.06859512499999999 2 0.06859512499999999 2 0.0916556875 2 0.0916556875} PREDS {{258 0 0-2870 {}} {262 0 0-4375 {}} {259 0 0-4006 {}}} SUCCS {{259 0 0-4008 {}} {256 0 0-4375 {}}} CYCLES {}}
+set a(0-4008) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,13,1,16) AREA_SCORE 17.00 QUANTITY 3 NAME FRAME:for:acc#22 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-2847 XREFS 22186 LOC {2 0.0230606 2 0.091655725 2 0.091655725 2 0.19755650317154677 2 0.19755650317154677} PREDS {{258 0 0-4004 {}} {259 0 0-4007 {}}} SUCCS {{258 0 0-4288 {}} {258 0 0-4375 {}}} CYCLES {}}
+set a(0-4009) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME FRAME:for:acc#16 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-2847 XREFS 22187 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.2878815350894752 1 0.47538791008947523} PREDS {{258 0 0-3928 {}}} SUCCS {{259 0 0-4010 {}} {258 0 0-4380 {}}} CYCLES {}}
+set a(0-4010) {NAME FRAME:for:asn#2 TYPE ASSIGN PAR 0-2847 XREFS 22188 LOC {1 0.036879575 1 0.287881575 1 0.287881575 1 0.47538795} PREDS {{259 0 0-4009 {}}} SUCCS {{259 0 0-4011 {}}} CYCLES {}}
+set a(0-4011) {NAME FRAME:for:conc#11 TYPE CONCATENATE PAR 0-2847 XREFS 22189 LOC {1 0.036879575 1 0.287881575 1 0.287881575 1 0.47538795} PREDS {{259 0 0-4010 {}}} SUCCS {{259 0 0-4012 {}}} CYCLES {}}
+set a(0-4012) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME FRAME:for:acc TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 22190 LOC {1 0.036879575 1 0.287881575 1 0.287881575 1 0.31512745207082715 1 0.5026338270708272} PREDS {{259 0 0-4011 {}}} SUCCS {{259 0 0-4013 {}}} CYCLES {}}
+set a(0-4013) {NAME FRAME:for:slc TYPE READSLICE PAR 0-2847 XREFS 22191 LOC {1 0.0641255 1 0.3151275 1 0.3151275 1 0.502633875} PREDS {{259 0 0-4012 {}}} SUCCS {{259 0 0-4014 {}}} CYCLES {}}
+set a(0-4014) {NAME FRAME:for:not TYPE NOT PAR 0-2847 XREFS 22192 LOC {1 0.0641255 1 0.3151275 1 0.3151275 1 0.502633875} PREDS {{259 0 0-4013 {}}} SUCCS {{259 0 0-4015 {}} {258 0 0-4365 {}} {258 0 0-4367 {}} {258 0 0-4368 {}} {258 0 0-4379 {}}} CYCLES {}}
+set a(0-4015) {NAME FRAME:for:select#2 TYPE SELECT PAR 0-2847 XREFS 22193 LOC {1 0.0641255 1 0.3151275 1 0.3151275 1 0.502633875} PREDS {{259 0 0-4014 {}}} SUCCS {{146 0 0-4016 {}} {146 0 0-4017 {}} {146 0 0-4018 {}} {146 0 0-4019 {}} {146 0 0-4020 {}} {146 0 0-4021 {}} {146 0 0-4022 {}} {146 0 0-4023 {}} {146 0 0-4024 {}} {146 0 0-4025 {}} {146 0 0-4026 {}} {146 0 0-4027 {}} {146 0 0-4028 {}} {146 0 0-4029 {}} {146 0 0-4030 {}} {146 0 0-4031 {}} {146 0 0-4032 {}} {146 0 0-4033 {}} {146 0 0-4034 {}} {146 0 0-4035 {}} {146 0 0-4036 {}} {146 0 0-4037 {}} {146 0 0-4038 {}} {146 0 0-4039 {}} {146 0 0-4040 {}} {146 0 0-4041 {}} {146 0 0-4042 {}} {146 0 0-4043 {}} {146 0 0-4044 {}} {146 0 0-4045 {}} {146 0 0-4046 {}} {146 0 0-4047 {}} {146 0 0-4048 {}} {146 0 0-4049 {}} {146 0 0-4050 {}} {146 0 0-4051 {}} {146 0 0-4052 {}} {146 0 0-4053 {}} {146 0 0-4054 {}} {146 0 0-4055 {}} {146 0 0-4056 {}} {146 0 0-4057 {}} {146 0 0-4058 {}} {146 0 0-4059 {}} {146 0 0-4060 {}} {146 0 0-4061 {}} {146 0 0-4062 {}} {146 0 0-4063 {}} {146 0 0-4064 {}} {146 0 0-4065 {}} {146 0 0-4066 {}} {146 0 0-4067 {}} {146 0 0-4068 {}} {146 0 0-4069 {}} {146 0 0-4070 {}} {146 0 0-4071 {}} {146 0 0-4072 {}} {146 0 0-4073 {}} {146 0 0-4074 {}} {146 0 0-4075 {}} {146 0 0-4076 {}} {146 0 0-4077 {}} {146 0 0-4078 {}} {146 0 0-4079 {}} {146 0 0-4080 {}} {146 0 0-4081 {}} {146 0 0-4082 {}} {146 0 0-4083 {}} {146 0 0-4084 {}} {146 0 0-4085 {}} {146 0 0-4086 {}} {146 0 0-4087 {}} {146 0 0-4088 {}} {146 0 0-4089 {}} {146 0 0-4090 {}} {146 0 0-4091 {}} {146 0 0-4092 {}} {146 0 0-4093 {}} {146 0 0-4094 {}} {146 0 0-4095 {}} {146 0 0-4096 {}} {146 0 0-4097 {}} {146 0 0-4098 {}} {146 0 0-4099 {}} {146 0 0-4100 {}} {146 0 0-4101 {}} {146 0 0-4102 {}} {146 0 0-4103 {}} {146 0 0-4104 {}} {146 0 0-4105 {}} {146 0 0-4106 {}} {146 0 0-4107 {}} {146 0 0-4108 {}} {146 0 0-4109 {}} {146 0 0-4110 {}} {146 0 0-4111 {}} {146 0 0-4112 {}} {146 0 0-4113 {}} {146 0 0-4114 {}} {146 0 0-4115 {}} {146 0 0-4116 {}} {146 0 0-4117 {}} {146 0 0-4118 {}} {146 0 0-4119 {}} {146 0 0-4120 {}} {146 0 0-4121 {}} {146 0 0-4122 {}} {146 0 0-4123 {}} {146 0 0-4124 {}} {146 0 0-4125 {}} {146 0 0-4126 {}} {146 0 0-4127 {}} {146 0 0-4128 {}} {146 0 0-4129 {}} {146 0 0-4130 {}} {146 0 0-4131 {}} {146 0 0-4132 {}} {146 0 0-4133 {}} {146 0 0-4134 {}} {146 0 0-4135 {}} {146 0 0-4136 {}} {146 0 0-4137 {}} {146 0 0-4138 {}} {146 0 0-4139 {}} {146 0 0-4140 {}} {146 0 0-4141 {}} {146 0 0-4142 {}} {146 0 0-4143 {}} {146 0 0-4144 {}} {146 0 0-4145 {}} {146 0 0-4146 {}} {146 0 0-4147 {}} {146 0 0-4148 {}} {146 0 0-4149 {}} {146 0 0-4150 {}} {146 0 0-4151 {}} {146 0 0-4152 {}} {146 0 0-4153 {}} {146 0 0-4154 {}} {146 0 0-4155 {}} {146 0 0-4156 {}} {146 0 0-4157 {}} {146 0 0-4158 {}} {146 0 0-4159 {}} {146 0 0-4160 {}} {146 0 0-4161 {}} {146 0 0-4162 {}} {146 0 0-4163 {}} {146 0 0-4164 {}} {146 0 0-4165 {}} {146 0 0-4166 {}} {146 0 0-4167 {}} {146 0 0-4168 {}} {146 0 0-4169 {}} {146 0 0-4170 {}} {146 0 0-4171 {}} {146 0 0-4172 {}} {146 0 0-4173 {}} {146 0 0-4174 {}} {146 0 0-4175 {}} {146 0 0-4176 {}} {146 0 0-4177 {}} {146 0 0-4178 {}} {146 0 0-4179 {}} {146 0 0-4180 {}} {146 0 0-4181 {}} {146 0 0-4182 {}} {146 0 0-4183 {}} {146 0 0-4184 {}} {146 0 0-4185 {}} {146 0 0-4186 {}} {146 0 0-4187 {}} {146 0 0-4188 {}} {146 0 0-4189 {}} {146 0 0-4190 {}} {146 0 0-4191 {}} {146 0 0-4192 {}} {146 0 0-4193 {}} {146 0 0-4194 {}} {146 0 0-4195 {}} {146 0 0-4196 {}} {146 0 0-4197 {}} {146 0 0-4198 {}} {146 0 0-4199 {}} {146 0 0-4200 {}} {146 0 0-4201 {}} {146 0 0-4202 {}} {146 0 0-4203 {}} {146 0 0-4204 {}} {146 0 0-4205 {}} {146 0 0-4206 {}} {146 0 0-4207 {}} {146 0 0-4208 {}} {146 0 0-4209 {}} {146 0 0-4210 {}} {146 0 0-4211 {}} {146 0 0-4212 {}} {146 0 0-4213 {}} {146 0 0-4214 {}} {146 0 0-4215 {}} {146 0 0-4216 {}} {146 0 0-4217 {}} {146 0 0-4218 {}} {146 0 0-4219 {}} {146 0 0-4220 {}} {146 0 0-4221 {}} {146 0 0-4222 {}} {146 0 0-4223 {}} {146 0 0-4224 {}} {146 0 0-4225 {}} {146 0 0-4226 {}} {146 0 0-4227 {}} {146 0 0-4228 {}} {146 0 0-4229 {}} {146 0 0-4230 {}} {146 0 0-4231 {}} {146 0 0-4232 {}} {146 0 0-4233 {}} {146 0 0-4234 {}} {146 0 0-4235 {}} {146 0 0-4236 {}} {146 0 0-4237 {}} {146 0 0-4238 {}} {146 0 0-4239 {}} {146 0 0-4240 {}} {146 0 0-4241 {}} {146 0 0-4242 {}} {146 0 0-4243 {}} {146 0 0-4244 {}} {146 0 0-4245 {}} {146 0 0-4246 {}} {146 0 0-4247 {}} {146 0 0-4248 {}} {146 0 0-4249 {}} {146 0 0-4250 {}} {146 0 0-4251 {}} {146 0 0-4252 {}} {146 0 0-4253 {}} {146 0 0-4254 {}} {146 0 0-4255 {}} {146 0 0-4256 {}} {146 0 0-4257 {}} {146 0 0-4258 {}} {146 0 0-4259 {}} {146 0 0-4260 {}} {146 0 0-4261 {}} {146 0 0-4262 {}} {146 0 0-4263 {}} {146 0 0-4264 {}} {146 0 0-4265 {}} {146 0 0-4266 {}} {146 0 0-4267 {}} {146 0 0-4268 {}} {146 0 0-4269 {}} {146 0 0-4270 {}} {146 0 0-4271 {}} {146 0 0-4272 {}} {146 0 0-4273 {}} {146 0 0-4274 {}} {146 0 0-4275 {}} {146 0 0-4276 {}} {146 0 0-4277 {}} {146 0 0-4278 {}} {146 0 0-4279 {}} {146 0 0-4280 {}} {146 0 0-4281 {}} {146 0 0-4282 {}} {146 0 0-4283 {}} {146 0 0-4284 {}} {146 0 0-4285 {}} {146 0 0-4286 {}} {146 0 0-4287 {}} {146 0 0-4288 {}} {146 0 0-4289 {}} {146 0 0-4290 {}} {146 0 0-4291 {}} {146 0 0-4292 {}} {146 0 0-4293 {}} {146 0 0-4294 {}} {146 0 0-4295 {}} {146 0 0-4296 {}} {146 0 0-4297 {}} {146 0 0-4298 {}} {146 0 0-4299 {}} {146 0 0-4300 {}} {146 0 0-4301 {}} {146 0 0-4302 {}} {146 0 0-4303 {}} {146 0 0-4304 {}} {146 0 0-4305 {}} {146 0 0-4306 {}} {146 0 0-4307 {}} {146 0 0-4308 {}} {146 0 0-4309 {}} {146 0 0-4310 {}} {146 0 0-4311 {}} {146 0 0-4312 {}} {146 0 0-4313 {}} {146 0 0-4314 {}} {146 0 0-4315 {}} {146 0 0-4316 {}} {146 0 0-4317 {}} {146 0 0-4318 {}} {146 0 0-4319 {}} {146 0 0-4320 {}} {146 0 0-4321 {}} {146 0 0-4322 {}} {146 0 0-4323 {}} {146 0 0-4324 {}} {146 0 0-4325 {}} {146 0 0-4326 {}} {146 0 0-4327 {}} {146 0 0-4328 {}} {146 0 0-4329 {}} {146 0 0-4330 {}} {146 0 0-4331 {}} {146 0 0-4332 {}} {146 0 0-4333 {}} {146 0 0-4334 {}} {146 0 0-4335 {}} {146 0 0-4336 {}} {146 0 0-4337 {}} {146 0 0-4338 {}} {146 0 0-4339 {}} {146 0 0-4340 {}} {146 0 0-4341 {}} {146 0 0-4342 {}} {146 0 0-4343 {}} {146 0 0-4344 {}} {146 0 0-4345 {}} {146 0 0-4346 {}} {146 0 0-4347 {}} {146 0 0-4348 {}} {146 0 0-4349 {}} {146 0 0-4350 {}} {146 0 0-4351 {}} {146 0 0-4352 {}} {146 0 0-4353 {}} {146 0 0-4354 {}} {146 0 0-4355 {}} {146 0 0-4356 {}} {130 0 0-4357 {}} {146 0 0-4358 {}} {146 0 0-4359 {}} {146 0 0-4360 {}} {146 0 0-4361 {}} {146 0 0-4362 {}}} CYCLES {}}
+set a(0-4016) {NAME ACC2:slc(ACC1:acc#125.psp)#5 TYPE READSLICE PAR 0-2847 XREFS 22194 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.766898075} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{258 0 0-4018 {}}} CYCLES {}}
+set a(0-4017) {NAME ACC2:slc(ACC1:acc#125.psp#1)#3 TYPE READSLICE PAR 0-2847 XREFS 22195 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.766898075} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4018 {}}} CYCLES {}}
+set a(0-4018) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 6 NAME ACC2:acc#5 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-2847 XREFS 22196 LOC {1 0.16961555 1 0.5793917 1 0.5793917 1 0.61100253625 1 0.7985089112499999} PREDS {{146 0 0-4015 {}} {258 0 0-4016 {}} {259 0 0-4017 {}}} SUCCS {{259 0 0-4019 {}}} CYCLES {}}
+set a(0-4019) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME ACC1:mul#20 TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-2847 XREFS 22197 LOC {1 0.201226425 1 0.611002575 1 0.611002575 1 0.8124935812499999 1 0.9999999562499999} PREDS {{146 0 0-4015 {}} {259 0 0-4018 {}}} SUCCS {{258 0 0-4247 {}}} CYCLES {}}
+set a(0-4020) {NAME ACC2:slc(ACC1:acc#125.psp)#9 TYPE READSLICE PAR 0-2847 XREFS 22198 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6185303999999999} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{258 0 0-4022 {}}} CYCLES {}}
+set a(0-4021) {NAME ACC2:slc(ACC1:acc#125.psp#1)#9 TYPE READSLICE PAR 0-2847 XREFS 22199 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6185303999999999} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4022 {}}} CYCLES {}}
+set a(0-4022) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 6 NAME ACC2:acc#6 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-2847 XREFS 22200 LOC {1 0.16961555 1 0.431024025 1 0.431024025 1 0.46263486125 1 0.6501412362499999} PREDS {{146 0 0-4015 {}} {258 0 0-4020 {}} {259 0 0-4021 {}}} SUCCS {{259 0 0-4023 {}}} CYCLES {}}
+set a(0-4023) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME ACC1:mul#21 TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-2847 XREFS 22201 LOC {1 0.201226425 1 0.46263489999999996 1 0.46263489999999996 1 0.6641259062499999 1 0.8516322812499999} PREDS {{146 0 0-4015 {}} {259 0 0-4022 {}}} SUCCS {{258 0 0-4027 {}}} CYCLES {}}
+set a(0-4024) {NAME ACC2:slc(ACC1:acc#125.psp)#10 TYPE READSLICE PAR 0-2847 XREFS 22202 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.851632325} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{258 0 0-4027 {}}} CYCLES {}}
+set a(0-4025) {NAME ACC1-3:slc(acc#5.psp)#57 TYPE READSLICE PAR 0-2847 XREFS 22203 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.851632325} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4026 {}}} CYCLES {}}
+set a(0-4026) {NAME ACC1-3:exs#24 TYPE SIGNEXTEND PAR 0-2847 XREFS 22204 LOC {1 0.16961555 1 0.66412595 1 0.66412595 1 0.851632325} PREDS {{146 0 0-4015 {}} {259 0 0-4025 {}}} SUCCS {{259 0 0-4027 {}}} CYCLES {}}
+set a(0-4027) {NAME ACC1:conc TYPE CONCATENATE PAR 0-2847 XREFS 22205 LOC {1 0.402717475 1 0.66412595 1 0.66412595 1 0.851632325} PREDS {{146 0 0-4015 {}} {258 0 0-4024 {}} {258 0 0-4023 {}} {259 0 0-4026 {}}} SUCCS {{258 0 0-4043 {}}} CYCLES {}}
+set a(0-4028) {NAME ACC2:slc(ACC1:acc#125.psp)#3 TYPE READSLICE PAR 0-2847 XREFS 22206 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.5661459} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{258 0 0-4030 {}}} CYCLES {}}
+set a(0-4029) {NAME ACC2:slc(ACC1:acc#125.psp#1)#1 TYPE READSLICE PAR 0-2847 XREFS 22207 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.5661459} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4030 {}}} CYCLES {}}
+set a(0-4030) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 6 NAME ACC2:acc#3 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-2847 XREFS 22208 LOC {1 0.16961555 1 0.378639525 1 0.378639525 1 0.41025036125 1 0.59775673625} PREDS {{146 0 0-4015 {}} {258 0 0-4028 {}} {259 0 0-4029 {}}} SUCCS {{259 0 0-4031 {}}} CYCLES {}}
+set a(0-4031) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME ACC1:mul#18 TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-2847 XREFS 22209 LOC {1 0.201226425 1 0.41025039999999996 1 0.41025039999999996 1 0.61174140625 1 0.79924778125} PREDS {{146 0 0-4015 {}} {259 0 0-4030 {}}} SUCCS {{258 0 0-4042 {}}} CYCLES {}}
+set a(0-4032) {NAME ACC2:slc(ACC1:acc#125.psp)#2 TYPE READSLICE PAR 0-2847 XREFS 22210 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.502633875} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{258 0 0-4034 {}}} CYCLES {}}
+set a(0-4033) {NAME ACC2:slc(ACC1:acc#125.psp#1) TYPE READSLICE PAR 0-2847 XREFS 22211 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.502633875} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4034 {}}} CYCLES {}}
+set a(0-4034) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 6 NAME ACC2:acc TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-2847 XREFS 22212 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.34673833625 1 0.53424471125} PREDS {{146 0 0-4015 {}} {258 0 0-4032 {}} {259 0 0-4033 {}}} SUCCS {{259 0 0-4035 {}}} CYCLES {}}
+set a(0-4035) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME ACC1:mul TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-2847 XREFS 22213 LOC {1 0.201226425 1 0.346738375 1 0.346738375 1 0.54822938125 1 0.7357357562499999} PREDS {{146 0 0-4015 {}} {259 0 0-4034 {}}} SUCCS {{258 0 0-4041 {}}} CYCLES {}}
+set a(0-4036) {NAME ACC2:slc(ACC1:acc#125.psp)#12 TYPE READSLICE PAR 0-2847 XREFS 22214 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.7357357999999999} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{258 0 0-4040 {}}} CYCLES {}}
+set a(0-4037) {NAME ACC2:slc(ACC1:acc#125.psp)#13 TYPE READSLICE PAR 0-2847 XREFS 22215 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.7357357999999999} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{258 0 0-4040 {}}} CYCLES {}}
+set a(0-4038) {NAME ACC1-3:slc(acc#5.psp)#59 TYPE READSLICE PAR 0-2847 XREFS 22216 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.7357357999999999} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4039 {}}} CYCLES {}}
+set a(0-4039) {NAME ACC1-3:exs#25 TYPE SIGNEXTEND PAR 0-2847 XREFS 22217 LOC {1 0.16961555 1 0.5482294249999999 1 0.5482294249999999 1 0.7357357999999999} PREDS {{146 0 0-4015 {}} {259 0 0-4038 {}}} SUCCS {{259 0 0-4040 {}}} CYCLES {}}
+set a(0-4040) {NAME ACC2:conc#6 TYPE CONCATENATE PAR 0-2847 XREFS 22218 LOC {1 0.16961555 1 0.5482294249999999 1 0.5482294249999999 1 0.7357357999999999} PREDS {{146 0 0-4015 {}} {258 0 0-4037 {}} {258 0 0-4036 {}} {259 0 0-4039 {}}} SUCCS {{259 0 0-4041 {}}} CYCLES {}}
+set a(0-4041) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 1 NAME ACC1:acc#330 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-2847 XREFS 22219 LOC {1 0.402717475 1 0.5482294249999999 1 0.5482294249999999 1 0.6117413984103024 1 0.7992477734103024} PREDS {{146 0 0-4015 {}} {258 0 0-4035 {}} {259 0 0-4040 {}}} SUCCS {{259 0 0-4042 {}}} CYCLES {}}
+set a(0-4042) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#334 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-2847 XREFS 22220 LOC {1 0.46622949999999996 1 0.61174145 1 0.61174145 1 0.6641259027684258 1 0.8516322777684256} PREDS {{146 0 0-4015 {}} {258 0 0-4031 {}} {259 0 0-4041 {}}} SUCCS {{259 0 0-4043 {}}} CYCLES {}}
+set a(0-4043) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,0,10) AREA_SCORE 10.25 QUANTITY 5 NAME ACC1:acc#336 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-2847 XREFS 22221 LOC {1 0.518614 1 0.66412595 1 0.66412595 1 0.74130943186502 1 0.92881580686502} PREDS {{146 0 0-4015 {}} {258 0 0-4027 {}} {259 0 0-4042 {}}} SUCCS {{258 0 0-4246 {}}} CYCLES {}}
+set a(0-4044) {NAME ACC1-1:slc(acc#5.psp)#52 TYPE READSLICE PAR 0-2847 XREFS 22222 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.8285522249999999} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{258 0 0-4047 {}}} CYCLES {}}
+set a(0-4045) {NAME ACC1-1:slc(acc#5.psp)#53 TYPE READSLICE PAR 0-2847 XREFS 22223 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.8285522249999999} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4046 {}}} CYCLES {}}
+set a(0-4046) {NAME ACC1-1:exs#30 TYPE SIGNEXTEND PAR 0-2847 XREFS 22224 LOC {1 0.16961555 1 0.6410458499999999 1 0.6410458499999999 1 0.8285522249999999} PREDS {{146 0 0-4015 {}} {259 0 0-4045 {}}} SUCCS {{259 0 0-4047 {}}} CYCLES {}}
+set a(0-4047) {NAME ACC1-1:conc#240 TYPE CONCATENATE PAR 0-2847 XREFS 22225 LOC {1 0.16961555 1 0.6410458499999999 1 0.6410458499999999 1 0.8285522249999999} PREDS {{146 0 0-4015 {}} {258 0 0-4044 {}} {259 0 0-4046 {}}} SUCCS {{259 0 0-4048 {}}} CYCLES {}}
+set a(0-4048) {NAME ACC1-1:exs#541 TYPE SIGNEXTEND PAR 0-2847 XREFS 22226 LOC {1 0.16961555 1 0.6410458499999999 1 0.6410458499999999 1 0.8285522249999999} PREDS {{146 0 0-4015 {}} {259 0 0-4047 {}}} SUCCS {{258 0 0-4135 {}}} CYCLES {}}
+set a(0-4049) {NAME ACC1-3:slc(acc#5.psp)#54 TYPE READSLICE PAR 0-2847 XREFS 22227 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4050 {}}} CYCLES {}}
+set a(0-4050) {NAME ACC1-3:exs#28 TYPE SIGNEXTEND PAR 0-2847 XREFS 22228 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4049 {}}} SUCCS {{259 0 0-4051 {}}} CYCLES {}}
+set a(0-4051) {NAME ACC1:conc#641 TYPE CONCATENATE PAR 0-2847 XREFS 22229 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4050 {}}} SUCCS {{258 0 0-4056 {}}} CYCLES {}}
+set a(0-4052) {NAME ACC1-3:slc(acc#5.psp)#68 TYPE READSLICE PAR 0-2847 XREFS 22230 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4053 {}}} CYCLES {}}
+set a(0-4053) {NAME ACC1-3:exs#33 TYPE SIGNEXTEND PAR 0-2847 XREFS 22231 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4052 {}}} SUCCS {{258 0 0-4055 {}}} CYCLES {}}
+set a(0-4054) {NAME ACC2:slc(acc.imod#18) TYPE READSLICE PAR 0-2847 XREFS 22232 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3929 {}}} SUCCS {{259 0 0-4055 {}}} CYCLES {}}
+set a(0-4055) {NAME ACC1:conc#642 TYPE CONCATENATE PAR 0-2847 XREFS 22233 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-4053 {}} {259 0 0-4054 {}}} SUCCS {{259 0 0-4056 {}}} CYCLES {}}
+set a(0-4056) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#310 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22234 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-4015 {}} {258 0 0-4051 {}} {259 0 0-4055 {}}} SUCCS {{259 0 0-4057 {}}} CYCLES {}}
+set a(0-4057) {NAME ACC1:slc#97 TYPE READSLICE PAR 0-2847 XREFS 22235 LOC {1 0.417782875 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-4015 {}} {259 0 0-4056 {}}} SUCCS {{258 0 0-4067 {}}} CYCLES {}}
+set a(0-4058) {NAME ACC1-3:slc(acc#5.psp)#71 TYPE READSLICE PAR 0-2847 XREFS 22236 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4059 {}}} CYCLES {}}
+set a(0-4059) {NAME ACC1-3:exs#540 TYPE SIGNEXTEND PAR 0-2847 XREFS 22237 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4058 {}}} SUCCS {{259 0 0-4060 {}}} CYCLES {}}
+set a(0-4060) {NAME ACC1:conc#639 TYPE CONCATENATE PAR 0-2847 XREFS 22238 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4059 {}}} SUCCS {{258 0 0-4065 {}}} CYCLES {}}
+set a(0-4061) {NAME ACC1-3:slc(acc#5.psp)#70 TYPE READSLICE PAR 0-2847 XREFS 22239 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4062 {}}} CYCLES {}}
+set a(0-4062) {NAME ACC1-3:exs#31 TYPE SIGNEXTEND PAR 0-2847 XREFS 22240 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4061 {}}} SUCCS {{258 0 0-4064 {}}} CYCLES {}}
+set a(0-4063) {NAME ACC2:slc(ACC1:acc#110.psp#2)#2 TYPE READSLICE PAR 0-2847 XREFS 22241 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3933 {}}} SUCCS {{259 0 0-4064 {}}} CYCLES {}}
+set a(0-4064) {NAME ACC1:conc#640 TYPE CONCATENATE PAR 0-2847 XREFS 22242 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-4062 {}} {259 0 0-4063 {}}} SUCCS {{259 0 0-4065 {}}} CYCLES {}}
+set a(0-4065) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#309 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22243 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-4015 {}} {258 0 0-4060 {}} {259 0 0-4064 {}}} SUCCS {{259 0 0-4066 {}}} CYCLES {}}
+set a(0-4066) {NAME ACC1:slc#96 TYPE READSLICE PAR 0-2847 XREFS 22244 LOC {1 0.3292811 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-4015 {}} {259 0 0-4065 {}}} SUCCS {{259 0 0-4067 {}}} CYCLES {}}
+set a(0-4067) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#319 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22245 LOC {1 0.417782875 1 0.48154284999999997 1 0.48154284999999997 1 0.5290989770708271 1 0.7166053520708271} PREDS {{146 0 0-4015 {}} {258 0 0-4057 {}} {259 0 0-4066 {}}} SUCCS {{258 0 0-4091 {}}} CYCLES {}}
+set a(0-4068) {NAME ACC1-1:slc(acc#5.psp)#67 TYPE READSLICE PAR 0-2847 XREFS 22246 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4069 {}}} CYCLES {}}
+set a(0-4069) {NAME ACC1-1:exs#34 TYPE SIGNEXTEND PAR 0-2847 XREFS 22247 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4068 {}}} SUCCS {{259 0 0-4070 {}}} CYCLES {}}
+set a(0-4070) {NAME ACC1:conc#635 TYPE CONCATENATE PAR 0-2847 XREFS 22248 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4069 {}}} SUCCS {{258 0 0-4075 {}}} CYCLES {}}
+set a(0-4071) {NAME ACC1-1:slc(acc#5.psp)#66 TYPE READSLICE PAR 0-2847 XREFS 22249 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4072 {}}} CYCLES {}}
+set a(0-4072) {NAME ACC1-1:exs#35 TYPE SIGNEXTEND PAR 0-2847 XREFS 22250 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4071 {}}} SUCCS {{258 0 0-4074 {}}} CYCLES {}}
+set a(0-4073) {NAME ACC2:slc(ACC1:acc#110.psp#2) TYPE READSLICE PAR 0-2847 XREFS 22251 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3933 {}}} SUCCS {{259 0 0-4074 {}}} CYCLES {}}
+set a(0-4074) {NAME ACC1:conc#636 TYPE CONCATENATE PAR 0-2847 XREFS 22252 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-4072 {}} {259 0 0-4073 {}}} SUCCS {{259 0 0-4075 {}}} CYCLES {}}
+set a(0-4075) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#307 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22253 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-4015 {}} {258 0 0-4070 {}} {259 0 0-4074 {}}} SUCCS {{259 0 0-4076 {}}} CYCLES {}}
+set a(0-4076) {NAME ACC1:slc#94 TYPE READSLICE PAR 0-2847 XREFS 22254 LOC {1 0.3292811 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-4015 {}} {259 0 0-4075 {}}} SUCCS {{258 0 0-4090 {}}} CYCLES {}}
+set a(0-4077) {NAME ACC1-1:slc(acc#5.psp)#65 TYPE READSLICE PAR 0-2847 XREFS 22255 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4078 {}}} CYCLES {}}
+set a(0-4078) {NAME ACC1-1:exs#22 TYPE SIGNEXTEND PAR 0-2847 XREFS 22256 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4077 {}}} SUCCS {{259 0 0-4079 {}}} CYCLES {}}
+set a(0-4079) {NAME ACC1:conc#633 TYPE CONCATENATE PAR 0-2847 XREFS 22257 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4078 {}}} SUCCS {{258 0 0-4088 {}}} CYCLES {}}
+set a(0-4080) {NAME ACC1-1:slc(acc#5.psp)#64 TYPE READSLICE PAR 0-2847 XREFS 22258 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4081 {}}} CYCLES {}}
+set a(0-4081) {NAME ACC1-1:exs#23 TYPE SIGNEXTEND PAR 0-2847 XREFS 22259 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4080 {}}} SUCCS {{258 0 0-4087 {}}} CYCLES {}}
+set a(0-4082) {NAME ACC1-3:slc(acc#5.psp)#51 TYPE READSLICE PAR 0-2847 XREFS 22260 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{258 0 0-4086 {}}} CYCLES {}}
+set a(0-4083) {NAME ACC1-3:slc(acc.imod#7)#1 TYPE READSLICE PAR 0-2847 XREFS 22261 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3915 {}}} SUCCS {{259 0 0-4084 {}}} CYCLES {}}
+set a(0-4084) {NAME ACC1-3:not#60 TYPE NOT PAR 0-2847 XREFS 22262 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4083 {}}} SUCCS {{258 0 0-4086 {}}} CYCLES {}}
+set a(0-4085) {NAME ACC1-3:slc(acc.imod#7)#2 TYPE READSLICE PAR 0-2847 XREFS 22263 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3915 {}}} SUCCS {{259 0 0-4086 {}}} CYCLES {}}
+set a(0-4086) {NAME ACC1-3:and#3 TYPE AND PAR 0-2847 XREFS 22264 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-4084 {}} {258 0 0-4082 {}} {259 0 0-4085 {}}} SUCCS {{259 0 0-4087 {}}} CYCLES {}}
+set a(0-4087) {NAME ACC1:conc#634 TYPE CONCATENATE PAR 0-2847 XREFS 22265 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-4081 {}} {259 0 0-4086 {}}} SUCCS {{259 0 0-4088 {}}} CYCLES {}}
+set a(0-4088) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#306 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22266 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-4015 {}} {258 0 0-4079 {}} {259 0 0-4087 {}}} SUCCS {{259 0 0-4089 {}}} CYCLES {}}
+set a(0-4089) {NAME ACC1:slc#93 TYPE READSLICE PAR 0-2847 XREFS 22267 LOC {1 0.4450288 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-4015 {}} {259 0 0-4088 {}}} SUCCS {{259 0 0-4090 {}}} CYCLES {}}
+set a(0-4090) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#318 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22268 LOC {1 0.4450288 1 0.48154284999999997 1 0.48154284999999997 1 0.5290989770708271 1 0.7166053520708271} PREDS {{146 0 0-4015 {}} {258 0 0-4076 {}} {259 0 0-4089 {}}} SUCCS {{259 0 0-4091 {}}} CYCLES {}}
+set a(0-4091) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#325 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-2847 XREFS 22269 LOC {1 0.492584975 1 0.529099025 1 0.529099025 1 0.5824460451789504 1 0.7699524201789505} PREDS {{146 0 0-4015 {}} {258 0 0-4067 {}} {259 0 0-4090 {}}} SUCCS {{258 0 0-4134 {}}} CYCLES {}}
+set a(0-4092) {NAME ACC1-1:slc(acc#5.psp)#63 TYPE READSLICE PAR 0-2847 XREFS 22270 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4093 {}}} CYCLES {}}
+set a(0-4093) {NAME ACC1-1:exs#18 TYPE SIGNEXTEND PAR 0-2847 XREFS 22271 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4092 {}}} SUCCS {{259 0 0-4094 {}}} CYCLES {}}
+set a(0-4094) {NAME ACC1:conc#631 TYPE CONCATENATE PAR 0-2847 XREFS 22272 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4093 {}}} SUCCS {{258 0 0-4102 {}}} CYCLES {}}
+set a(0-4095) {NAME ACC1-1:slc(acc#5.psp)#62 TYPE READSLICE PAR 0-2847 XREFS 22273 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4096 {}}} CYCLES {}}
+set a(0-4096) {NAME ACC1-1:exs#19 TYPE SIGNEXTEND PAR 0-2847 XREFS 22274 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4095 {}}} SUCCS {{258 0 0-4101 {}}} CYCLES {}}
+set a(0-4097) {NAME ACC1-3:slc(acc.imod#7) TYPE READSLICE PAR 0-2847 XREFS 22275 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3915 {}}} SUCCS {{258 0 0-4100 {}}} CYCLES {}}
+set a(0-4098) {NAME ACC1-3:slc(acc#5.psp)#50 TYPE READSLICE PAR 0-2847 XREFS 22276 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4099 {}}} CYCLES {}}
+set a(0-4099) {NAME ACC1-3:not#59 TYPE NOT PAR 0-2847 XREFS 22277 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4098 {}}} SUCCS {{259 0 0-4100 {}}} CYCLES {}}
+set a(0-4100) {NAME ACC1-3:nand#1 TYPE NAND PAR 0-2847 XREFS 22278 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-4097 {}} {259 0 0-4099 {}}} SUCCS {{259 0 0-4101 {}}} CYCLES {}}
+set a(0-4101) {NAME ACC1:conc#632 TYPE CONCATENATE PAR 0-2847 XREFS 22279 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-4096 {}} {259 0 0-4100 {}}} SUCCS {{259 0 0-4102 {}}} CYCLES {}}
+set a(0-4102) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#305 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22280 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-4015 {}} {258 0 0-4094 {}} {259 0 0-4101 {}}} SUCCS {{259 0 0-4103 {}}} CYCLES {}}
+set a(0-4103) {NAME ACC1:slc#92 TYPE READSLICE PAR 0-2847 XREFS 22281 LOC {1 0.4450288 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-4015 {}} {259 0 0-4102 {}}} SUCCS {{258 0 0-4113 {}}} CYCLES {}}
+set a(0-4104) {NAME ACC1-1:slc(acc#5.psp)#61 TYPE READSLICE PAR 0-2847 XREFS 22282 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4105 {}}} CYCLES {}}
+set a(0-4105) {NAME ACC1-1:exs#20 TYPE SIGNEXTEND PAR 0-2847 XREFS 22283 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4104 {}}} SUCCS {{259 0 0-4106 {}}} CYCLES {}}
+set a(0-4106) {NAME ACC1:conc#629 TYPE CONCATENATE PAR 0-2847 XREFS 22284 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4105 {}}} SUCCS {{258 0 0-4111 {}}} CYCLES {}}
+set a(0-4107) {NAME ACC1-1:slc(acc#5.psp)#60 TYPE READSLICE PAR 0-2847 XREFS 22285 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4108 {}}} CYCLES {}}
+set a(0-4108) {NAME ACC1-1:exs#21 TYPE SIGNEXTEND PAR 0-2847 XREFS 22286 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4107 {}}} SUCCS {{258 0 0-4110 {}}} CYCLES {}}
+set a(0-4109) {NAME ACC2:slc(acc.imod#6) TYPE READSLICE PAR 0-2847 XREFS 22287 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3914 {}}} SUCCS {{259 0 0-4110 {}}} CYCLES {}}
+set a(0-4110) {NAME ACC1:conc#630 TYPE CONCATENATE PAR 0-2847 XREFS 22288 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-4108 {}} {259 0 0-4109 {}}} SUCCS {{259 0 0-4111 {}}} CYCLES {}}
+set a(0-4111) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#304 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22289 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-4015 {}} {258 0 0-4106 {}} {259 0 0-4110 {}}} SUCCS {{259 0 0-4112 {}}} CYCLES {}}
+set a(0-4112) {NAME ACC1:slc#91 TYPE READSLICE PAR 0-2847 XREFS 22290 LOC {1 0.417782875 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-4015 {}} {259 0 0-4111 {}}} SUCCS {{259 0 0-4113 {}}} CYCLES {}}
+set a(0-4113) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#317 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22291 LOC {1 0.4450288 1 0.48154284999999997 1 0.48154284999999997 1 0.5290989770708271 1 0.7166053520708271} PREDS {{146 0 0-4015 {}} {258 0 0-4103 {}} {259 0 0-4112 {}}} SUCCS {{258 0 0-4133 {}}} CYCLES {}}
+set a(0-4114) {NAME ACC1-1:slc(acc#5.psp)#59 TYPE READSLICE PAR 0-2847 XREFS 22292 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4115 {}}} CYCLES {}}
+set a(0-4115) {NAME ACC1-1:exs#25 TYPE SIGNEXTEND PAR 0-2847 XREFS 22293 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4114 {}}} SUCCS {{259 0 0-4116 {}}} CYCLES {}}
+set a(0-4116) {NAME ACC1:conc#627 TYPE CONCATENATE PAR 0-2847 XREFS 22294 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4115 {}}} SUCCS {{258 0 0-4121 {}}} CYCLES {}}
+set a(0-4117) {NAME ACC1-1:slc(acc#5.psp)#58 TYPE READSLICE PAR 0-2847 XREFS 22295 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4118 {}}} CYCLES {}}
+set a(0-4118) {NAME ACC1-1:exs#26 TYPE SIGNEXTEND PAR 0-2847 XREFS 22296 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4117 {}}} SUCCS {{258 0 0-4120 {}}} CYCLES {}}
+set a(0-4119) {NAME ACC2:slc(ACC1:acc#110.psp#1)#2 TYPE READSLICE PAR 0-2847 XREFS 22297 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3925 {}}} SUCCS {{259 0 0-4120 {}}} CYCLES {}}
+set a(0-4120) {NAME ACC1:conc#628 TYPE CONCATENATE PAR 0-2847 XREFS 22298 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-4118 {}} {259 0 0-4119 {}}} SUCCS {{259 0 0-4121 {}}} CYCLES {}}
+set a(0-4121) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#303 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22299 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-4015 {}} {258 0 0-4116 {}} {259 0 0-4120 {}}} SUCCS {{259 0 0-4122 {}}} CYCLES {}}
+set a(0-4122) {NAME ACC1:slc#90 TYPE READSLICE PAR 0-2847 XREFS 22300 LOC {1 0.3292811 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-4015 {}} {259 0 0-4121 {}}} SUCCS {{258 0 0-4132 {}}} CYCLES {}}
+set a(0-4123) {NAME ACC1-1:slc(acc#5.psp)#57 TYPE READSLICE PAR 0-2847 XREFS 22301 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4124 {}}} CYCLES {}}
+set a(0-4124) {NAME ACC1-1:exs#24 TYPE SIGNEXTEND PAR 0-2847 XREFS 22302 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4123 {}}} SUCCS {{259 0 0-4125 {}}} CYCLES {}}
+set a(0-4125) {NAME ACC1:conc#625 TYPE CONCATENATE PAR 0-2847 XREFS 22303 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4124 {}}} SUCCS {{258 0 0-4130 {}}} CYCLES {}}
+set a(0-4126) {NAME ACC1-1:slc(acc#5.psp)#56 TYPE READSLICE PAR 0-2847 XREFS 22304 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4127 {}}} CYCLES {}}
+set a(0-4127) {NAME ACC1-1:exs#29 TYPE SIGNEXTEND PAR 0-2847 XREFS 22305 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {259 0 0-4126 {}}} SUCCS {{258 0 0-4129 {}}} CYCLES {}}
+set a(0-4128) {NAME ACC2:slc(ACC1:acc#110.psp#1)#1 TYPE READSLICE PAR 0-2847 XREFS 22306 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-3925 {}}} SUCCS {{259 0 0-4129 {}}} CYCLES {}}
+set a(0-4129) {NAME ACC1:conc#626 TYPE CONCATENATE PAR 0-2847 XREFS 22307 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-4015 {}} {258 0 0-4127 {}} {259 0 0-4128 {}}} SUCCS {{259 0 0-4130 {}}} CYCLES {}}
+set a(0-4130) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#302 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22308 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-4015 {}} {258 0 0-4125 {}} {259 0 0-4129 {}}} SUCCS {{259 0 0-4131 {}}} CYCLES {}}
+set a(0-4131) {NAME ACC1:slc#89 TYPE READSLICE PAR 0-2847 XREFS 22309 LOC {1 0.3292811 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-4015 {}} {259 0 0-4130 {}}} SUCCS {{259 0 0-4132 {}}} CYCLES {}}
+set a(0-4132) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#316 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22310 LOC {1 0.3292811 1 0.48154284999999997 1 0.48154284999999997 1 0.5290989770708271 1 0.7166053520708271} PREDS {{146 0 0-4015 {}} {258 0 0-4122 {}} {259 0 0-4131 {}}} SUCCS {{259 0 0-4133 {}}} CYCLES {}}
+set a(0-4133) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#324 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-2847 XREFS 22311 LOC {1 0.492584975 1 0.529099025 1 0.529099025 1 0.5824460451789504 1 0.7699524201789505} PREDS {{146 0 0-4015 {}} {258 0 0-4113 {}} {259 0 0-4132 {}}} SUCCS {{259 0 0-4134 {}}} CYCLES {}}
+set a(0-4134) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 2 NAME ACC1:acc#328 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-2847 XREFS 22312 LOC {1 0.54593205 1 0.5824461 1 0.5824461 1 0.641045809496936 1 0.828552184496936} PREDS {{146 0 0-4015 {}} {258 0 0-4091 {}} {259 0 0-4133 {}}} SUCCS {{259 0 0-4135 {}}} CYCLES {}}
+set a(0-4135) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#332 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-2847 XREFS 22313 LOC {1 0.6045318 1 0.6410458499999999 1 0.6410458499999999 1 0.6889249129329679 1 0.8764312879329679} PREDS {{146 0 0-4015 {}} {258 0 0-4048 {}} {259 0 0-4134 {}}} SUCCS {{258 0 0-4245 {}}} CYCLES {}}
+set a(0-4136) {NAME ACC1-1:slc(acc#5.psp)#55 TYPE READSLICE PAR 0-2847 XREFS 22314 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4137 {}}} CYCLES {}}
+set a(0-4137) {NAME ACC1-1:exs#27 TYPE SIGNEXTEND PAR 0-2847 XREFS 22315 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4136 {}}} SUCCS {{259 0 0-4138 {}}} CYCLES {}}
+set a(0-4138) {NAME ACC1:conc#623 TYPE CONCATENATE PAR 0-2847 XREFS 22316 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4137 {}}} SUCCS {{258 0 0-4143 {}}} CYCLES {}}
+set a(0-4139) {NAME ACC1-1:slc(acc#5.psp)#54 TYPE READSLICE PAR 0-2847 XREFS 22317 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4140 {}}} CYCLES {}}
+set a(0-4140) {NAME ACC1-1:exs#28 TYPE SIGNEXTEND PAR 0-2847 XREFS 22318 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4139 {}}} SUCCS {{258 0 0-4142 {}}} CYCLES {}}
+set a(0-4141) {NAME ACC2:slc(ACC1:acc#110.psp#1) TYPE READSLICE PAR 0-2847 XREFS 22319 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3925 {}}} SUCCS {{259 0 0-4142 {}}} CYCLES {}}
+set a(0-4142) {NAME ACC1:conc#624 TYPE CONCATENATE PAR 0-2847 XREFS 22320 LOC {1 0.281724925 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-4140 {}} {259 0 0-4141 {}}} SUCCS {{259 0 0-4143 {}}} CYCLES {}}
+set a(0-4143) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#301 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22321 LOC {1 0.281724925 1 0.43866402499999996 1 0.43866402499999996 1 0.48622015207082714 1 0.6737265270708271} PREDS {{146 0 0-4015 {}} {258 0 0-4138 {}} {259 0 0-4142 {}}} SUCCS {{259 0 0-4144 {}}} CYCLES {}}
+set a(0-4144) {NAME ACC1:slc#88 TYPE READSLICE PAR 0-2847 XREFS 22322 LOC {1 0.3292811 1 0.4862202 1 0.4862202 1 0.673726575} PREDS {{146 0 0-4015 {}} {259 0 0-4143 {}}} SUCCS {{258 0 0-4154 {}}} CYCLES {}}
+set a(0-4145) {NAME ACC1-1:slc(acc#5.psp)#68 TYPE READSLICE PAR 0-2847 XREFS 22323 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4146 {}}} CYCLES {}}
+set a(0-4146) {NAME ACC1-1:exs#33 TYPE SIGNEXTEND PAR 0-2847 XREFS 22324 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4145 {}}} SUCCS {{259 0 0-4147 {}}} CYCLES {}}
+set a(0-4147) {NAME ACC1:conc#621 TYPE CONCATENATE PAR 0-2847 XREFS 22325 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4146 {}}} SUCCS {{258 0 0-4152 {}}} CYCLES {}}
+set a(0-4148) {NAME ACC1-1:slc(acc#5.psp)#71 TYPE READSLICE PAR 0-2847 XREFS 22326 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4149 {}}} CYCLES {}}
+set a(0-4149) {NAME ACC1-1:exs#540 TYPE SIGNEXTEND PAR 0-2847 XREFS 22327 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4148 {}}} SUCCS {{258 0 0-4151 {}}} CYCLES {}}
+set a(0-4150) {NAME ACC2:slc(ACC1:acc#125.psp#1)#7 TYPE READSLICE PAR 0-2847 XREFS 22328 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4151 {}}} CYCLES {}}
+set a(0-4151) {NAME ACC1:conc#622 TYPE CONCATENATE PAR 0-2847 XREFS 22329 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-4149 {}} {259 0 0-4150 {}}} SUCCS {{259 0 0-4152 {}}} CYCLES {}}
+set a(0-4152) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#300 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22330 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.48622015207082714 1 0.6737265270708271} PREDS {{146 0 0-4015 {}} {258 0 0-4147 {}} {259 0 0-4151 {}}} SUCCS {{259 0 0-4153 {}}} CYCLES {}}
+set a(0-4153) {NAME ACC1:slc#87 TYPE READSLICE PAR 0-2847 XREFS 22331 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.673726575} PREDS {{146 0 0-4015 {}} {259 0 0-4152 {}}} SUCCS {{259 0 0-4154 {}}} CYCLES {}}
+set a(0-4154) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#315 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22332 LOC {1 0.3292811 1 0.4862202 1 0.4862202 1 0.5337763270708271 1 0.7212827020708271} PREDS {{146 0 0-4015 {}} {258 0 0-4144 {}} {259 0 0-4153 {}}} SUCCS {{258 0 0-4174 {}}} CYCLES {}}
+set a(0-4155) {NAME ACC1-1:slc(acc#5.psp)#70 TYPE READSLICE PAR 0-2847 XREFS 22333 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4156 {}}} CYCLES {}}
+set a(0-4156) {NAME ACC1-1:exs#31 TYPE SIGNEXTEND PAR 0-2847 XREFS 22334 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4155 {}}} SUCCS {{259 0 0-4157 {}}} CYCLES {}}
+set a(0-4157) {NAME ACC1:conc#619 TYPE CONCATENATE PAR 0-2847 XREFS 22335 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4156 {}}} SUCCS {{258 0 0-4162 {}}} CYCLES {}}
+set a(0-4158) {NAME ACC1-1:slc(acc#5.psp)#69 TYPE READSLICE PAR 0-2847 XREFS 22336 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4159 {}}} CYCLES {}}
+set a(0-4159) {NAME ACC1-1:exs#32 TYPE SIGNEXTEND PAR 0-2847 XREFS 22337 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4158 {}}} SUCCS {{258 0 0-4161 {}}} CYCLES {}}
+set a(0-4160) {NAME ACC2:slc(ACC1:acc#125.psp#1)#6 TYPE READSLICE PAR 0-2847 XREFS 22338 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4161 {}}} CYCLES {}}
+set a(0-4161) {NAME ACC1:conc#620 TYPE CONCATENATE PAR 0-2847 XREFS 22339 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-4159 {}} {259 0 0-4160 {}}} SUCCS {{259 0 0-4162 {}}} CYCLES {}}
+set a(0-4162) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#299 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22340 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.48622015207082714 1 0.6737265270708271} PREDS {{146 0 0-4015 {}} {258 0 0-4157 {}} {259 0 0-4161 {}}} SUCCS {{259 0 0-4163 {}}} CYCLES {}}
+set a(0-4163) {NAME ACC1:slc#86 TYPE READSLICE PAR 0-2847 XREFS 22341 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.673726575} PREDS {{146 0 0-4015 {}} {259 0 0-4162 {}}} SUCCS {{258 0 0-4173 {}}} CYCLES {}}
+set a(0-4164) {NAME ACC1-3:slc(acc#5.psp)#63 TYPE READSLICE PAR 0-2847 XREFS 22342 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4165 {}}} CYCLES {}}
+set a(0-4165) {NAME ACC1-3:exs#18 TYPE SIGNEXTEND PAR 0-2847 XREFS 22343 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4164 {}}} SUCCS {{259 0 0-4166 {}}} CYCLES {}}
+set a(0-4166) {NAME ACC1:conc#617 TYPE CONCATENATE PAR 0-2847 XREFS 22344 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4165 {}}} SUCCS {{258 0 0-4171 {}}} CYCLES {}}
+set a(0-4167) {NAME ACC1-3:slc(acc#5.psp)#62 TYPE READSLICE PAR 0-2847 XREFS 22345 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4168 {}}} CYCLES {}}
+set a(0-4168) {NAME ACC1-3:exs#19 TYPE SIGNEXTEND PAR 0-2847 XREFS 22346 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4167 {}}} SUCCS {{258 0 0-4170 {}}} CYCLES {}}
+set a(0-4169) {NAME ACC2:slc(ACC1:acc#125.psp#1)#5 TYPE READSLICE PAR 0-2847 XREFS 22347 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4170 {}}} CYCLES {}}
+set a(0-4170) {NAME ACC1:conc#618 TYPE CONCATENATE PAR 0-2847 XREFS 22348 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-4168 {}} {259 0 0-4169 {}}} SUCCS {{259 0 0-4171 {}}} CYCLES {}}
+set a(0-4171) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#298 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22349 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.48622015207082714 1 0.6737265270708271} PREDS {{146 0 0-4015 {}} {258 0 0-4166 {}} {259 0 0-4170 {}}} SUCCS {{259 0 0-4172 {}}} CYCLES {}}
+set a(0-4172) {NAME ACC1:slc#85 TYPE READSLICE PAR 0-2847 XREFS 22350 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.673726575} PREDS {{146 0 0-4015 {}} {259 0 0-4171 {}}} SUCCS {{259 0 0-4173 {}}} CYCLES {}}
+set a(0-4173) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#314 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22351 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.5337763270708271 1 0.7212827020708271} PREDS {{146 0 0-4015 {}} {258 0 0-4163 {}} {259 0 0-4172 {}}} SUCCS {{259 0 0-4174 {}}} CYCLES {}}
+set a(0-4174) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#323 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-2847 XREFS 22352 LOC {1 0.37683727499999997 1 0.533776375 1 0.533776375 1 0.5871233951789505 1 0.7746297701789504} PREDS {{146 0 0-4015 {}} {258 0 0-4154 {}} {259 0 0-4173 {}}} SUCCS {{258 0 0-4220 {}}} CYCLES {}}
+set a(0-4175) {NAME ACC1-3:slc(acc#5.psp)#67 TYPE READSLICE PAR 0-2847 XREFS 22353 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4176 {}}} CYCLES {}}
+set a(0-4176) {NAME ACC1-3:exs#34 TYPE SIGNEXTEND PAR 0-2847 XREFS 22354 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4175 {}}} SUCCS {{259 0 0-4177 {}}} CYCLES {}}
+set a(0-4177) {NAME ACC1:conc#615 TYPE CONCATENATE PAR 0-2847 XREFS 22355 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4176 {}}} SUCCS {{258 0 0-4182 {}}} CYCLES {}}
+set a(0-4178) {NAME ACC1-3:slc(acc#5.psp)#66 TYPE READSLICE PAR 0-2847 XREFS 22356 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4179 {}}} CYCLES {}}
+set a(0-4179) {NAME ACC1-3:exs#35 TYPE SIGNEXTEND PAR 0-2847 XREFS 22357 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4178 {}}} SUCCS {{258 0 0-4181 {}}} CYCLES {}}
+set a(0-4180) {NAME ACC2:slc(ACC1:acc#125.psp#1)#4 TYPE READSLICE PAR 0-2847 XREFS 22358 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4181 {}}} CYCLES {}}
+set a(0-4181) {NAME ACC1:conc#616 TYPE CONCATENATE PAR 0-2847 XREFS 22359 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-4179 {}} {259 0 0-4180 {}}} SUCCS {{259 0 0-4182 {}}} CYCLES {}}
+set a(0-4182) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#297 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22360 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.48622015207082714 1 0.6737265270708271} PREDS {{146 0 0-4015 {}} {258 0 0-4177 {}} {259 0 0-4181 {}}} SUCCS {{259 0 0-4183 {}}} CYCLES {}}
+set a(0-4183) {NAME ACC1:slc#84 TYPE READSLICE PAR 0-2847 XREFS 22361 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.673726575} PREDS {{146 0 0-4015 {}} {259 0 0-4182 {}}} SUCCS {{258 0 0-4193 {}}} CYCLES {}}
+set a(0-4184) {NAME ACC1-3:slc(acc#5.psp)#65 TYPE READSLICE PAR 0-2847 XREFS 22362 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4185 {}}} CYCLES {}}
+set a(0-4185) {NAME ACC1-3:exs#22 TYPE SIGNEXTEND PAR 0-2847 XREFS 22363 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4184 {}}} SUCCS {{259 0 0-4186 {}}} CYCLES {}}
+set a(0-4186) {NAME ACC1:conc#613 TYPE CONCATENATE PAR 0-2847 XREFS 22364 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4185 {}}} SUCCS {{258 0 0-4191 {}}} CYCLES {}}
+set a(0-4187) {NAME ACC1-3:slc(acc#5.psp)#64 TYPE READSLICE PAR 0-2847 XREFS 22365 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4188 {}}} CYCLES {}}
+set a(0-4188) {NAME ACC1-3:exs#23 TYPE SIGNEXTEND PAR 0-2847 XREFS 22366 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {259 0 0-4187 {}}} SUCCS {{258 0 0-4190 {}}} CYCLES {}}
+set a(0-4189) {NAME ACC2:slc(ACC1:acc#125.psp)#1 TYPE READSLICE PAR 0-2847 XREFS 22367 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4190 {}}} CYCLES {}}
+set a(0-4190) {NAME ACC1:conc#614 TYPE CONCATENATE PAR 0-2847 XREFS 22368 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-4015 {}} {258 0 0-4188 {}} {259 0 0-4189 {}}} SUCCS {{259 0 0-4191 {}}} CYCLES {}}
+set a(0-4191) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#296 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22369 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.48622015207082714 1 0.6737265270708271} PREDS {{146 0 0-4015 {}} {258 0 0-4186 {}} {259 0 0-4190 {}}} SUCCS {{259 0 0-4192 {}}} CYCLES {}}
+set a(0-4192) {NAME ACC1:slc#83 TYPE READSLICE PAR 0-2847 XREFS 22370 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.673726575} PREDS {{146 0 0-4015 {}} {259 0 0-4191 {}}} SUCCS {{259 0 0-4193 {}}} CYCLES {}}
+set a(0-4193) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#313 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22371 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.5337763270708271 1 0.7212827020708271} PREDS {{146 0 0-4015 {}} {258 0 0-4183 {}} {259 0 0-4192 {}}} SUCCS {{258 0 0-4219 {}}} CYCLES {}}
+set a(0-4194) {NAME ACC2:slc(ACC1:acc#125.psp)#6 TYPE READSLICE PAR 0-2847 XREFS 22372 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6203795} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{258 0 0-4196 {}}} CYCLES {}}
+set a(0-4195) {NAME ACC2:slc(ACC1:acc#125.psp)#7 TYPE READSLICE PAR 0-2847 XREFS 22373 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6203795} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4196 {}}} CYCLES {}}
+set a(0-4196) {NAME ACC2:conc TYPE CONCATENATE PAR 0-2847 XREFS 22374 LOC {1 0.16961555 1 0.43287312499999997 1 0.43287312499999997 1 0.6203795} PREDS {{146 0 0-4015 {}} {258 0 0-4194 {}} {259 0 0-4195 {}}} SUCCS {{259 0 0-4197 {}}} CYCLES {}}
+set a(0-4197) {NAME ACC1:conc#611 TYPE CONCATENATE PAR 0-2847 XREFS 22375 LOC {1 0.16961555 1 0.43287312499999997 1 0.43287312499999997 1 0.6203795} PREDS {{146 0 0-4015 {}} {259 0 0-4196 {}}} SUCCS {{258 0 0-4203 {}}} CYCLES {}}
+set a(0-4198) {NAME ACC2:slc(ACC1:acc#125.psp#1)#8 TYPE READSLICE PAR 0-2847 XREFS 22376 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6203795} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{258 0 0-4200 {}}} CYCLES {}}
+set a(0-4199) {NAME ACC2:slc(ACC1:acc#125.psp)#8 TYPE READSLICE PAR 0-2847 XREFS 22377 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6203795} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4200 {}}} CYCLES {}}
+set a(0-4200) {NAME ACC2:conc#1 TYPE CONCATENATE PAR 0-2847 XREFS 22378 LOC {1 0.16961555 1 0.43287312499999997 1 0.43287312499999997 1 0.6203795} PREDS {{146 0 0-4015 {}} {258 0 0-4198 {}} {259 0 0-4199 {}}} SUCCS {{258 0 0-4202 {}}} CYCLES {}}
+set a(0-4201) {NAME ACC2:slc(ACC1:acc#125.psp) TYPE READSLICE PAR 0-2847 XREFS 22379 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6203795} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4202 {}}} CYCLES {}}
+set a(0-4202) {NAME ACC1:conc#612 TYPE CONCATENATE PAR 0-2847 XREFS 22380 LOC {1 0.16961555 1 0.43287312499999997 1 0.43287312499999997 1 0.6203795} PREDS {{146 0 0-4015 {}} {258 0 0-4200 {}} {259 0 0-4201 {}}} SUCCS {{259 0 0-4203 {}}} CYCLES {}}
+set a(0-4203) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#295 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22381 LOC {1 0.16961555 1 0.43287312499999997 1 0.43287312499999997 1 0.48042925207082715 1 0.6679356270708271} PREDS {{146 0 0-4015 {}} {258 0 0-4197 {}} {259 0 0-4202 {}}} SUCCS {{259 0 0-4204 {}}} CYCLES {}}
+set a(0-4204) {NAME ACC1:slc#82 TYPE READSLICE PAR 0-2847 XREFS 22382 LOC {1 0.21717172499999998 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-4015 {}} {259 0 0-4203 {}}} SUCCS {{259 0 0-4205 {}}} CYCLES {}}
+set a(0-4205) {NAME ACC1:conc#645 TYPE CONCATENATE PAR 0-2847 XREFS 22383 LOC {1 0.21717172499999998 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-4015 {}} {259 0 0-4204 {}}} SUCCS {{258 0 0-4217 {}}} CYCLES {}}
+set a(0-4206) {NAME ACC2:slc(ACC1:acc#110.psp#1)#3 TYPE READSLICE PAR 0-2847 XREFS 22384 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.667935675} PREDS {{146 0 0-4015 {}} {258 0 0-3925 {}}} SUCCS {{259 0 0-4207 {}}} CYCLES {}}
+set a(0-4207) {NAME ACC2:not TYPE NOT PAR 0-2847 XREFS 22385 LOC {1 0.281724925 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-4015 {}} {259 0 0-4206 {}}} SUCCS {{258 0 0-4210 {}}} CYCLES {}}
+set a(0-4208) {NAME ACC2:slc(acc.imod#6)#1 TYPE READSLICE PAR 0-2847 XREFS 22386 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.667935675} PREDS {{146 0 0-4015 {}} {258 0 0-3914 {}}} SUCCS {{259 0 0-4209 {}}} CYCLES {}}
+set a(0-4209) {NAME ACC2:not#1 TYPE NOT PAR 0-2847 XREFS 22387 LOC {1 0.37022669999999996 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-4015 {}} {259 0 0-4208 {}}} SUCCS {{259 0 0-4210 {}}} CYCLES {}}
+set a(0-4210) {NAME ACC2:conc#2 TYPE CONCATENATE PAR 0-2847 XREFS 22388 LOC {1 0.37022669999999996 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-4015 {}} {258 0 0-4207 {}} {259 0 0-4209 {}}} SUCCS {{258 0 0-4216 {}}} CYCLES {}}
+set a(0-4211) {NAME ACC1-1:slc(acc#5.psp)#51 TYPE READSLICE PAR 0-2847 XREFS 22389 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.667935675} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{258 0 0-4215 {}}} CYCLES {}}
+set a(0-4212) {NAME ACC1-1:slc(acc.imod#7)#1 TYPE READSLICE PAR 0-2847 XREFS 22390 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-4015 {}} {258 0 0-3930 {}}} SUCCS {{259 0 0-4213 {}}} CYCLES {}}
+set a(0-4213) {NAME ACC1-1:not#60 TYPE NOT PAR 0-2847 XREFS 22391 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-4015 {}} {259 0 0-4212 {}}} SUCCS {{258 0 0-4215 {}}} CYCLES {}}
+set a(0-4214) {NAME ACC1-1:slc(acc.imod#7)#2 TYPE READSLICE PAR 0-2847 XREFS 22392 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-4015 {}} {258 0 0-3930 {}}} SUCCS {{259 0 0-4215 {}}} CYCLES {}}
+set a(0-4215) {NAME ACC1-1:and#3 TYPE AND PAR 0-2847 XREFS 22393 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-4015 {}} {258 0 0-4213 {}} {258 0 0-4211 {}} {259 0 0-4214 {}}} SUCCS {{259 0 0-4216 {}}} CYCLES {}}
+set a(0-4216) {NAME ACC1:conc#646 TYPE CONCATENATE PAR 0-2847 XREFS 22394 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-4015 {}} {258 0 0-4210 {}} {259 0 0-4215 {}}} SUCCS {{259 0 0-4217 {}}} CYCLES {}}
+set a(0-4217) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#312 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-2847 XREFS 22395 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.5337763201789505 1 0.7212826951789504} PREDS {{146 0 0-4015 {}} {258 0 0-4205 {}} {259 0 0-4216 {}}} SUCCS {{259 0 0-4218 {}}} CYCLES {}}
+set a(0-4218) {NAME ACC1:slc#99 TYPE READSLICE PAR 0-2847 XREFS 22396 LOC {1 0.4508197 1 0.533776375 1 0.533776375 1 0.72128275} PREDS {{146 0 0-4015 {}} {259 0 0-4217 {}}} SUCCS {{259 0 0-4219 {}}} CYCLES {}}
+set a(0-4219) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#322 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-2847 XREFS 22397 LOC {1 0.4508197 1 0.533776375 1 0.533776375 1 0.5871233951789505 1 0.7746297701789504} PREDS {{146 0 0-4015 {}} {258 0 0-4193 {}} {259 0 0-4218 {}}} SUCCS {{259 0 0-4220 {}}} CYCLES {}}
+set a(0-4220) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 2 NAME ACC1:acc#327 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-2847 XREFS 22398 LOC {1 0.504166775 1 0.58712345 1 0.58712345 1 0.645723159496936 1 0.833229534496936} PREDS {{146 0 0-4015 {}} {258 0 0-4174 {}} {259 0 0-4219 {}}} SUCCS {{258 0 0-4244 {}}} CYCLES {}}
+set a(0-4221) {NAME ACC2:slc(ACC1:acc#110.psp#2)#3 TYPE READSLICE PAR 0-2847 XREFS 22399 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.767155925} PREDS {{146 0 0-4015 {}} {258 0 0-3933 {}}} SUCCS {{259 0 0-4222 {}}} CYCLES {}}
+set a(0-4222) {NAME ACC2:not#2 TYPE NOT PAR 0-2847 XREFS 22400 LOC {1 0.281724925 1 0.57964955 1 0.57964955 1 0.767155925} PREDS {{146 0 0-4015 {}} {259 0 0-4221 {}}} SUCCS {{258 0 0-4225 {}}} CYCLES {}}
+set a(0-4223) {NAME ACC2:slc(acc.imod#18)#1 TYPE READSLICE PAR 0-2847 XREFS 22401 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.767155925} PREDS {{146 0 0-4015 {}} {258 0 0-3929 {}}} SUCCS {{259 0 0-4224 {}}} CYCLES {}}
+set a(0-4224) {NAME ACC2:not#3 TYPE NOT PAR 0-2847 XREFS 22402 LOC {1 0.37022669999999996 1 0.57964955 1 0.57964955 1 0.767155925} PREDS {{146 0 0-4015 {}} {259 0 0-4223 {}}} SUCCS {{259 0 0-4225 {}}} CYCLES {}}
+set a(0-4225) {NAME ACC2:conc#3 TYPE CONCATENATE PAR 0-2847 XREFS 22403 LOC {1 0.37022669999999996 1 0.57964955 1 0.57964955 1 0.767155925} PREDS {{146 0 0-4015 {}} {258 0 0-4222 {}} {259 0 0-4224 {}}} SUCCS {{259 0 0-4226 {}}} CYCLES {}}
+set a(0-4226) {NAME ACC1:conc#643 TYPE CONCATENATE PAR 0-2847 XREFS 22404 LOC {1 0.37022669999999996 1 0.57964955 1 0.57964955 1 0.767155925} PREDS {{146 0 0-4015 {}} {259 0 0-4225 {}}} SUCCS {{258 0 0-4233 {}}} CYCLES {}}
+set a(0-4227) {NAME ACC2:slc(ACC1:acc#118.psp) TYPE READSLICE PAR 0-2847 XREFS 22405 LOC {1 0.34298077499999996 1 0.57964955 1 0.57964955 1 0.767155925} PREDS {{146 0 0-4015 {}} {258 0 0-3923 {}}} SUCCS {{258 0 0-4232 {}}} CYCLES {}}
+set a(0-4228) {NAME ACC1-1:slc(acc.imod#7) TYPE READSLICE PAR 0-2847 XREFS 22406 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.767155925} PREDS {{146 0 0-4015 {}} {258 0 0-3930 {}}} SUCCS {{258 0 0-4231 {}}} CYCLES {}}
+set a(0-4229) {NAME ACC1-1:slc(acc#5.psp)#50 TYPE READSLICE PAR 0-2847 XREFS 22407 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.767155925} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4230 {}}} CYCLES {}}
+set a(0-4230) {NAME ACC1-1:not#59 TYPE NOT PAR 0-2847 XREFS 22408 LOC {1 0.16961555 1 0.4804293 1 0.4804293 1 0.767155925} PREDS {{146 0 0-4015 {}} {259 0 0-4229 {}}} SUCCS {{259 0 0-4231 {}}} CYCLES {}}
+set a(0-4231) {NAME ACC1-1:nand#1 TYPE NAND PAR 0-2847 XREFS 22409 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.767155925} PREDS {{146 0 0-4015 {}} {258 0 0-4228 {}} {259 0 0-4230 {}}} SUCCS {{259 0 0-4232 {}}} CYCLES {}}
+set a(0-4232) {NAME ACC1:conc#644 TYPE CONCATENATE PAR 0-2847 XREFS 22410 LOC {1 0.39747262499999997 1 0.57964955 1 0.57964955 1 0.767155925} PREDS {{146 0 0-4015 {}} {258 0 0-4227 {}} {259 0 0-4231 {}}} SUCCS {{259 0 0-4233 {}}} CYCLES {}}
+set a(0-4233) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#311 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-2847 XREFS 22411 LOC {1 0.39747262499999997 1 0.57964955 1 0.57964955 1 0.6126863201789504 1 0.8001926951789504} PREDS {{146 0 0-4015 {}} {258 0 0-4226 {}} {259 0 0-4232 {}}} SUCCS {{259 0 0-4234 {}}} CYCLES {}}
+set a(0-4234) {NAME ACC1:slc#98 TYPE READSLICE PAR 0-2847 XREFS 22412 LOC {1 0.43050944999999996 1 0.612686375 1 0.612686375 1 0.80019275} PREDS {{146 0 0-4015 {}} {259 0 0-4233 {}}} SUCCS {{258 0 0-4243 {}}} CYCLES {}}
+set a(0-4235) {NAME ACC1-3:slc(acc#5.psp)#69 TYPE READSLICE PAR 0-2847 XREFS 22413 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.772946825} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4236 {}}} CYCLES {}}
+set a(0-4236) {NAME ACC1-3:exs#32 TYPE SIGNEXTEND PAR 0-2847 XREFS 22414 LOC {1 0.16961555 1 0.58544045 1 0.58544045 1 0.772946825} PREDS {{146 0 0-4015 {}} {259 0 0-4235 {}}} SUCCS {{259 0 0-4237 {}}} CYCLES {}}
+set a(0-4237) {NAME ACC1:conc#637 TYPE CONCATENATE PAR 0-2847 XREFS 22415 LOC {1 0.16961555 1 0.58544045 1 0.58544045 1 0.772946825} PREDS {{146 0 0-4015 {}} {259 0 0-4236 {}}} SUCCS {{258 0 0-4241 {}}} CYCLES {}}
+set a(0-4238) {NAME ACC2:slc(ACC1:acc#118.psp#1) TYPE READSLICE PAR 0-2847 XREFS 22416 LOC {1 0.34298077499999996 1 0.58544045 1 0.58544045 1 0.772946825} PREDS {{146 0 0-4015 {}} {258 0 0-3931 {}}} SUCCS {{258 0 0-4240 {}}} CYCLES {}}
+set a(0-4239) {NAME ACC2:slc(ACC1:acc#110.psp#2)#1 TYPE READSLICE PAR 0-2847 XREFS 22417 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.772946825} PREDS {{146 0 0-4015 {}} {258 0 0-3933 {}}} SUCCS {{259 0 0-4240 {}}} CYCLES {}}
+set a(0-4240) {NAME ACC1:conc#638 TYPE CONCATENATE PAR 0-2847 XREFS 22418 LOC {1 0.34298077499999996 1 0.58544045 1 0.58544045 1 0.772946825} PREDS {{146 0 0-4015 {}} {258 0 0-4238 {}} {259 0 0-4239 {}}} SUCCS {{259 0 0-4241 {}}} CYCLES {}}
+set a(0-4241) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#308 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 22419 LOC {1 0.34298077499999996 1 0.58544045 1 0.58544045 1 0.6126863270708272 1 0.8001927020708272} PREDS {{146 0 0-4015 {}} {258 0 0-4237 {}} {259 0 0-4240 {}}} SUCCS {{259 0 0-4242 {}}} CYCLES {}}
+set a(0-4242) {NAME ACC1:slc#95 TYPE READSLICE PAR 0-2847 XREFS 22420 LOC {1 0.37022669999999996 1 0.612686375 1 0.612686375 1 0.80019275} PREDS {{146 0 0-4015 {}} {259 0 0-4241 {}}} SUCCS {{259 0 0-4243 {}}} CYCLES {}}
+set a(0-4243) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#321 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-2847 XREFS 22421 LOC {1 0.43050944999999996 1 0.612686375 1 0.612686375 1 0.6457231451789505 1 0.8332295201789505} PREDS {{146 0 0-4015 {}} {258 0 0-4234 {}} {259 0 0-4242 {}}} SUCCS {{259 0 0-4244 {}}} CYCLES {}}
+set a(0-4244) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME ACC1:acc#331 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 22422 LOC {1 0.562766525 1 0.6457231999999999 1 0.6457231999999999 1 0.6889249234103023 1 0.8764312984103023} PREDS {{146 0 0-4015 {}} {258 0 0-4220 {}} {259 0 0-4243 {}}} SUCCS {{259 0 0-4245 {}}} CYCLES {}}
+set a(0-4245) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#335 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-2847 XREFS 22423 LOC {1 0.652410925 1 0.6889249749999999 1 0.6889249749999999 1 0.7413094277684257 1 0.9288158027684257} PREDS {{146 0 0-4015 {}} {258 0 0-4135 {}} {259 0 0-4244 {}}} SUCCS {{259 0 0-4246 {}}} CYCLES {}}
+set a(0-4246) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#338 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 22424 LOC {1 0.7047954249999999 1 0.741309475 1 0.741309475 1 0.8124935783364113 1 0.9999999533364113} PREDS {{146 0 0-4015 {}} {258 0 0-4043 {}} {259 0 0-4245 {}}} SUCCS {{259 0 0-4247 {}}} CYCLES {}}
+set a(0-4247) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,0,12,1,13) AREA_SCORE 14.00 QUANTITY 2 NAME ACC1:acc#340 TYPE ACCU DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-2847 XREFS 22425 LOC {1 0.7759795749999999 1 0.812493625 1 0.812493625 1 0.9062972502166912 2 0.1038538002166912} PREDS {{146 0 0-4015 {}} {258 0 0-4019 {}} {259 0 0-4246 {}}} SUCCS {{258 0 0-4287 {}}} CYCLES {}}
+set a(0-4248) {NAME ACC2:slc(ACC1:acc#125.psp)#4 TYPE READSLICE PAR 0-2847 XREFS 22426 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.695713925} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{258 0 0-4250 {}}} CYCLES {}}
+set a(0-4249) {NAME ACC2:slc(ACC1:acc#125.psp#1)#2 TYPE READSLICE PAR 0-2847 XREFS 22427 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.695713925} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4250 {}}} CYCLES {}}
+set a(0-4250) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 6 NAME ACC2:acc#4 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-2847 XREFS 22428 LOC {1 0.16961555 1 0.53679555 1 0.53679555 1 0.56840638625 1 0.72732476125} PREDS {{146 0 0-4015 {}} {258 0 0-4248 {}} {259 0 0-4249 {}}} SUCCS {{259 0 0-4251 {}}} CYCLES {}}
+set a(0-4251) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME ACC1:mul#19 TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-2847 XREFS 22429 LOC {1 0.201226425 1 0.5684064249999999 1 0.5684064249999999 1 0.7698974312499999 1 0.9288158062499999} PREDS {{146 0 0-4015 {}} {259 0 0-4250 {}}} SUCCS {{258 0 0-4277 {}}} CYCLES {}}
+set a(0-4252) {NAME ACC2:slc(ACC1:acc#125.psp#1)#14 TYPE READSLICE PAR 0-2847 XREFS 22430 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.83773495} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{258 0 0-4256 {}}} CYCLES {}}
+set a(0-4253) {NAME ACC2:slc(ACC1:acc#125.psp)#14 TYPE READSLICE PAR 0-2847 XREFS 22431 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.83773495} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{258 0 0-4256 {}}} CYCLES {}}
+set a(0-4254) {NAME ACC1-3:slc(acc#5.psp)#58 TYPE READSLICE PAR 0-2847 XREFS 22432 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.83773495} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4255 {}}} CYCLES {}}
+set a(0-4255) {NAME ACC1-3:exs#26 TYPE SIGNEXTEND PAR 0-2847 XREFS 22433 LOC {1 0.16961555 1 0.6788165749999999 1 0.6788165749999999 1 0.83773495} PREDS {{146 0 0-4015 {}} {259 0 0-4254 {}}} SUCCS {{259 0 0-4256 {}}} CYCLES {}}
+set a(0-4256) {NAME ACC2:conc#7 TYPE CONCATENATE PAR 0-2847 XREFS 22434 LOC {1 0.16961555 1 0.6788165749999999 1 0.6788165749999999 1 0.83773495} PREDS {{146 0 0-4015 {}} {258 0 0-4253 {}} {258 0 0-4252 {}} {259 0 0-4255 {}}} SUCCS {{258 0 0-4270 {}}} CYCLES {}}
+set a(0-4257) {NAME ACC2:slc(ACC1:acc#125.psp#1)#12 TYPE READSLICE PAR 0-2847 XREFS 22435 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.746098375} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{258 0 0-4260 {}}} CYCLES {}}
+set a(0-4258) {NAME ACC1-3:slc(acc#5.psp)#61 TYPE READSLICE PAR 0-2847 XREFS 22436 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.746098375} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4259 {}}} CYCLES {}}
+set a(0-4259) {NAME ACC1-3:exs#20 TYPE SIGNEXTEND PAR 0-2847 XREFS 22437 LOC {1 0.16961555 1 0.5871799999999999 1 0.5871799999999999 1 0.746098375} PREDS {{146 0 0-4015 {}} {259 0 0-4258 {}}} SUCCS {{259 0 0-4260 {}}} CYCLES {}}
+set a(0-4260) {NAME ACC2:conc#4 TYPE CONCATENATE PAR 0-2847 XREFS 22438 LOC {1 0.16961555 1 0.5871799999999999 1 0.5871799999999999 1 0.746098375} PREDS {{146 0 0-4015 {}} {258 0 0-4257 {}} {259 0 0-4259 {}}} SUCCS {{258 0 0-4265 {}}} CYCLES {}}
+set a(0-4261) {NAME ACC2:slc(ACC1:acc#125.psp#1)#13 TYPE READSLICE PAR 0-2847 XREFS 22439 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.746098375} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{258 0 0-4264 {}}} CYCLES {}}
+set a(0-4262) {NAME ACC1-3:slc(acc#5.psp)#60 TYPE READSLICE PAR 0-2847 XREFS 22440 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.746098375} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4263 {}}} CYCLES {}}
+set a(0-4263) {NAME ACC1-3:exs#21 TYPE SIGNEXTEND PAR 0-2847 XREFS 22441 LOC {1 0.16961555 1 0.5871799999999999 1 0.5871799999999999 1 0.746098375} PREDS {{146 0 0-4015 {}} {259 0 0-4262 {}}} SUCCS {{259 0 0-4264 {}}} CYCLES {}}
+set a(0-4264) {NAME ACC2:conc#5 TYPE CONCATENATE PAR 0-2847 XREFS 22442 LOC {1 0.16961555 1 0.5871799999999999 1 0.5871799999999999 1 0.746098375} PREDS {{146 0 0-4015 {}} {258 0 0-4261 {}} {259 0 0-4263 {}}} SUCCS {{259 0 0-4265 {}}} CYCLES {}}
+set a(0-4265) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#320 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-2847 XREFS 22443 LOC {1 0.16961555 1 0.5871799999999999 1 0.5871799999999999 1 0.6405270201789504 1 0.7994453951789504} PREDS {{146 0 0-4015 {}} {258 0 0-4260 {}} {259 0 0-4264 {}}} SUCCS {{258 0 0-4269 {}}} CYCLES {}}
+set a(0-4266) {NAME ACC1-3:slc(acc#5.psp)#55 TYPE READSLICE PAR 0-2847 XREFS 22444 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.79944545} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4267 {}}} CYCLES {}}
+set a(0-4267) {NAME ACC1-3:exs#27 TYPE SIGNEXTEND PAR 0-2847 XREFS 22445 LOC {1 0.16961555 1 0.640527075 1 0.640527075 1 0.79944545} PREDS {{146 0 0-4015 {}} {259 0 0-4266 {}}} SUCCS {{259 0 0-4268 {}}} CYCLES {}}
+set a(0-4268) {NAME ACC1:conc#610 TYPE CONCATENATE PAR 0-2847 XREFS 22446 LOC {1 0.16961555 1 0.640527075 1 0.640527075 1 0.79944545} PREDS {{146 0 0-4015 {}} {259 0 0-4267 {}}} SUCCS {{259 0 0-4269 {}}} CYCLES {}}
+set a(0-4269) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#326 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 22447 LOC {1 0.222962625 1 0.640527075 1 0.640527075 1 0.678816534496936 1 0.8377349094969361} PREDS {{146 0 0-4015 {}} {258 0 0-4265 {}} {259 0 0-4268 {}}} SUCCS {{259 0 0-4270 {}}} CYCLES {}}
+set a(0-4270) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME ACC1:acc#329 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 22448 LOC {1 0.261252125 1 0.6788165749999999 1 0.6788165749999999 1 0.7220182984103023 1 0.8809366734103024} PREDS {{146 0 0-4015 {}} {258 0 0-4256 {}} {259 0 0-4269 {}}} SUCCS {{258 0 0-4276 {}}} CYCLES {}}
+set a(0-4271) {NAME ACC1-3:slc(acc#5.psp)#52 TYPE READSLICE PAR 0-2847 XREFS 22449 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.880936725} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{258 0 0-4274 {}}} CYCLES {}}
+set a(0-4272) {NAME ACC1-3:slc(acc#5.psp)#53 TYPE READSLICE PAR 0-2847 XREFS 22450 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.880936725} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4273 {}}} CYCLES {}}
+set a(0-4273) {NAME ACC1-3:exs#30 TYPE SIGNEXTEND PAR 0-2847 XREFS 22451 LOC {1 0.16961555 1 0.7220183499999999 1 0.7220183499999999 1 0.880936725} PREDS {{146 0 0-4015 {}} {259 0 0-4272 {}}} SUCCS {{259 0 0-4274 {}}} CYCLES {}}
+set a(0-4274) {NAME ACC1-3:conc#240 TYPE CONCATENATE PAR 0-2847 XREFS 22452 LOC {1 0.16961555 1 0.7220183499999999 1 0.7220183499999999 1 0.880936725} PREDS {{146 0 0-4015 {}} {258 0 0-4271 {}} {259 0 0-4273 {}}} SUCCS {{259 0 0-4275 {}}} CYCLES {}}
+set a(0-4275) {NAME ACC1-3:exs#541 TYPE SIGNEXTEND PAR 0-2847 XREFS 22453 LOC {1 0.16961555 1 0.7220183499999999 1 0.7220183499999999 1 0.880936725} PREDS {{146 0 0-4015 {}} {259 0 0-4274 {}}} SUCCS {{259 0 0-4276 {}}} CYCLES {}}
+set a(0-4276) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#333 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-2847 XREFS 22454 LOC {1 0.3044539 1 0.7220183499999999 1 0.7220183499999999 1 0.7698974129329679 1 0.9288157879329679} PREDS {{146 0 0-4015 {}} {258 0 0-4270 {}} {259 0 0-4275 {}}} SUCCS {{259 0 0-4277 {}}} CYCLES {}}
+set a(0-4277) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#337 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-2847 XREFS 22455 LOC {1 0.402717475 1 0.7698974749999999 1 0.7698974749999999 1 0.8410815783364113 1 0.9999999533364113} PREDS {{146 0 0-4015 {}} {258 0 0-4251 {}} {259 0 0-4276 {}}} SUCCS {{258 0 0-4286 {}}} CYCLES {}}
+set a(0-4278) {NAME ACC2:slc(ACC1:acc#125.psp)#11 TYPE READSLICE PAR 0-2847 XREFS 22456 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.766898075} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{258 0 0-4280 {}}} CYCLES {}}
+set a(0-4279) {NAME ACC2:slc(ACC1:acc#125.psp#1)#10 TYPE READSLICE PAR 0-2847 XREFS 22457 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.766898075} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{259 0 0-4280 {}}} CYCLES {}}
+set a(0-4280) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 6 NAME ACC2:acc#7 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-2847 XREFS 22458 LOC {1 0.16961555 1 0.6079797 1 0.6079797 1 0.6395905362500001 1 0.7985089112499999} PREDS {{146 0 0-4015 {}} {258 0 0-4278 {}} {259 0 0-4279 {}}} SUCCS {{259 0 0-4281 {}}} CYCLES {}}
+set a(0-4281) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME ACC1:mul#22 TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-2847 XREFS 22459 LOC {1 0.201226425 1 0.6395905749999999 1 0.6395905749999999 1 0.8410815812499999 1 0.9999999562499999} PREDS {{146 0 0-4015 {}} {259 0 0-4280 {}}} SUCCS {{258 0 0-4285 {}}} CYCLES {}}
+set a(0-4282) {NAME ACC2:slc(ACC1:acc#125.psp#1)#11 TYPE READSLICE PAR 0-2847 XREFS 22460 LOC {1 0.16961555 1 0.3151275 1 0.3151275 2 0.038638175} PREDS {{146 0 0-4015 {}} {258 0 0-3932 {}}} SUCCS {{258 0 0-4285 {}}} CYCLES {}}
+set a(0-4283) {NAME ACC1-3:slc(acc#5.psp)#56 TYPE READSLICE PAR 0-2847 XREFS 22461 LOC {1 0.16961555 1 0.3151275 1 0.3151275 2 0.038638175} PREDS {{146 0 0-4015 {}} {258 0 0-3924 {}}} SUCCS {{259 0 0-4284 {}}} CYCLES {}}
+set a(0-4284) {NAME ACC1-3:exs#29 TYPE SIGNEXTEND PAR 0-2847 XREFS 22462 LOC {1 0.16961555 1 0.8410816249999999 1 0.8410816249999999 2 0.038638175} PREDS {{146 0 0-4015 {}} {259 0 0-4283 {}}} SUCCS {{259 0 0-4285 {}}} CYCLES {}}
+set a(0-4285) {NAME ACC1:conc#441 TYPE CONCATENATE PAR 0-2847 XREFS 22463 LOC {1 0.402717475 1 0.8410816249999999 1 0.8410816249999999 2 0.038638175} PREDS {{146 0 0-4015 {}} {258 0 0-4282 {}} {258 0 0-4281 {}} {259 0 0-4284 {}}} SUCCS {{259 0 0-4286 {}}} CYCLES {}}
+set a(0-4286) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,13) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#339 TYPE ACCU DELAY {1.04 ns} LIBRARY_DELAY {1.04 ns} PAR 0-2847 XREFS 22464 LOC {1 0.473901625 1 0.8410816249999999 1 0.8410816249999999 1 0.9062972563734283 2 0.10385380637342836} PREDS {{146 0 0-4015 {}} {258 0 0-4277 {}} {259 0 0-4285 {}}} SUCCS {{259 0 0-4287 {}}} CYCLES {}}
+set a(0-4287) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,0,13,0,13) AREA_SCORE 14.22 QUANTITY 1 NAME ACC1:acc#341 TYPE ACCU DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-2847 XREFS 22465 LOC {1 0.86978325 1 0.9062973 1 0.9062973 1 0.9999999620503581 2 0.19755651205035812} PREDS {{146 0 0-4015 {}} {258 0 0-4247 {}} {259 0 0-4286 {}}} SUCCS {{259 0 0-4288 {}}} CYCLES {}}
+set a(0-4288) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,13,1,16) AREA_SCORE 17.00 QUANTITY 3 NAME ACC1:acc#342 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-2847 XREFS 22466 LOC {2 0.128961425 2 0.19755655 2 0.19755655 2 0.3034573281715468 2 0.3034573281715468} PREDS {{146 0 0-4015 {}} {258 0 0-4008 {}} {259 0 0-4287 {}}} SUCCS {{259 0 0-4289 {}}} CYCLES {}}
+set a(0-4289) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 1 NAME ACC1:acc TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-2847 XREFS 22467 LOC {2 0.23486225 2 0.303457375 2 0.303457375 2 0.409067105357901 2 0.409067105357901} PREDS {{146 0 0-4015 {}} {258 0 0-3970 {}} {259 0 0-4288 {}}} SUCCS {{259 0 0-4290 {}}} CYCLES {}}
+set a(0-4290) {NAME ACC2:slc TYPE READSLICE PAR 0-2847 XREFS 22468 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.40906715} PREDS {{146 0 0-4015 {}} {259 0 0-4289 {}}} SUCCS {{259 0 0-4291 {}} {258 0 0-4292 {}} {258 0 0-4295 {}} {258 0 0-4297 {}} {258 0 0-4300 {}} {258 0 0-4303 {}} {258 0 0-4304 {}} {258 0 0-4309 {}} {258 0 0-4311 {}} {258 0 0-4313 {}} {258 0 0-4330 {}} {258 0 0-4339 {}} {258 0 0-4340 {}} {258 0 0-4342 {}}} CYCLES {}}
+set a(0-4291) {NAME intensity:slc(intensity#2.sg1)#4 TYPE READSLICE PAR 0-2847 XREFS 22469 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.40906715} PREDS {{146 0 0-4015 {}} {259 0 0-4290 {}}} SUCCS {{258 0 0-4294 {}}} CYCLES {}}
+set a(0-4292) {NAME intensity:slc(intensity#2.sg1)#5 TYPE READSLICE PAR 0-2847 XREFS 22470 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.40906715} PREDS {{146 0 0-4015 {}} {258 0 0-4290 {}}} SUCCS {{259 0 0-4293 {}}} CYCLES {}}
+set a(0-4293) {NAME FRAME:not#2 TYPE NOT PAR 0-2847 XREFS 22471 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.40906715} PREDS {{146 0 0-4015 {}} {259 0 0-4292 {}}} SUCCS {{259 0 0-4294 {}}} CYCLES {}}
+set a(0-4294) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME FRAME:acc#6 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22472 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.45662327707082717 2 0.45662327707082717} PREDS {{146 0 0-4015 {}} {258 0 0-4291 {}} {259 0 0-4293 {}}} SUCCS {{258 0 0-4302 {}}} CYCLES {}}
+set a(0-4295) {NAME intensity:slc(intensity#2.sg1)#6 TYPE READSLICE PAR 0-2847 XREFS 22473 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.42937739999999996} PREDS {{146 0 0-4015 {}} {258 0 0-4290 {}}} SUCCS {{259 0 0-4296 {}}} CYCLES {}}
+set a(0-4296) {NAME FRAME:not#3 TYPE NOT PAR 0-2847 XREFS 22474 LOC {2 0.340472025 2 0.42937739999999996 2 0.42937739999999996 2 0.42937739999999996} PREDS {{146 0 0-4015 {}} {259 0 0-4295 {}}} SUCCS {{258 0 0-4299 {}}} CYCLES {}}
+set a(0-4297) {NAME intensity:slc(intensity#2.sg1)#7 TYPE READSLICE PAR 0-2847 XREFS 22475 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.42937739999999996} PREDS {{146 0 0-4015 {}} {258 0 0-4290 {}}} SUCCS {{259 0 0-4298 {}}} CYCLES {}}
+set a(0-4298) {NAME FRAME:not#9 TYPE NOT PAR 0-2847 XREFS 22476 LOC {2 0.340472025 2 0.42937739999999996 2 0.42937739999999996 2 0.42937739999999996} PREDS {{146 0 0-4015 {}} {259 0 0-4297 {}}} SUCCS {{259 0 0-4299 {}}} CYCLES {}}
+set a(0-4299) {NAME FRAME:conc TYPE CONCATENATE PAR 0-2847 XREFS 22477 LOC {2 0.340472025 2 0.42937739999999996 2 0.42937739999999996 2 0.42937739999999996} PREDS {{146 0 0-4015 {}} {258 0 0-4296 {}} {259 0 0-4298 {}}} SUCCS {{258 0 0-4301 {}}} CYCLES {}}
+set a(0-4300) {NAME intensity:slc(intensity#2.sg1)#1 TYPE READSLICE PAR 0-2847 XREFS 22478 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.42937739999999996} PREDS {{146 0 0-4015 {}} {258 0 0-4290 {}}} SUCCS {{259 0 0-4301 {}}} CYCLES {}}
+set a(0-4301) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME FRAME:acc#5 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 22479 LOC {2 0.340472025 2 0.42937739999999996 2 0.42937739999999996 2 0.45662327707082717 2 0.45662327707082717} PREDS {{146 0 0-4015 {}} {258 0 0-4299 {}} {259 0 0-4300 {}}} SUCCS {{259 0 0-4302 {}}} CYCLES {}}
+set a(0-4302) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME FRAME:acc#8 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-2847 XREFS 22480 LOC {2 0.3880282 2 0.45662332499999997 2 0.45662332499999997 2 0.5099703451789505 2 0.5099703451789505} PREDS {{146 0 0-4015 {}} {258 0 0-4294 {}} {259 0 0-4301 {}}} SUCCS {{258 0 0-4307 {}}} CYCLES {}}
+set a(0-4303) {NAME intensity:slc(intensity#2.sg1)#2 TYPE READSLICE PAR 0-2847 XREFS 22481 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.46241422499999996} PREDS {{146 0 0-4015 {}} {258 0 0-4290 {}}} SUCCS {{258 0 0-4306 {}}} CYCLES {}}
+set a(0-4304) {NAME intensity:slc(intensity#2.sg1)#3 TYPE READSLICE PAR 0-2847 XREFS 22482 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.46241422499999996} PREDS {{146 0 0-4015 {}} {258 0 0-4290 {}}} SUCCS {{259 0 0-4305 {}}} CYCLES {}}
+set a(0-4305) {NAME FRAME:not#1 TYPE NOT PAR 0-2847 XREFS 22483 LOC {2 0.340472025 2 0.46241422499999996 2 0.46241422499999996 2 0.46241422499999996} PREDS {{146 0 0-4015 {}} {259 0 0-4304 {}}} SUCCS {{259 0 0-4306 {}}} CYCLES {}}
+set a(0-4306) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME FRAME:acc#7 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-2847 XREFS 22484 LOC {2 0.340472025 2 0.46241422499999996 2 0.46241422499999996 2 0.5099703520708271 2 0.5099703520708271} PREDS {{146 0 0-4015 {}} {258 0 0-4303 {}} {259 0 0-4305 {}}} SUCCS {{259 0 0-4307 {}}} CYCLES {}}
+set a(0-4307) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME FRAME:acc#9 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 22485 LOC {2 0.44137527499999996 2 0.5099703999999999 2 0.5099703999999999 2 0.548259859496936 2 0.548259859496936} PREDS {{146 0 0-4015 {}} {258 0 0-4302 {}} {259 0 0-4306 {}}} SUCCS {{259 0 0-4308 {}}} CYCLES {}}
+set a(0-4308) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME acc#15 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 22486 LOC {2 0.479664775 2 0.5482599 2 0.5482599 2 0.5914616234103024 2 0.5914616234103024} PREDS {{146 0 0-4015 {}} {259 0 0-4307 {}}} SUCCS {{258 0 0-4314 {}} {258 0 0-4316 {}} {258 0 0-4318 {}} {258 0 0-4320 {}} {258 0 0-4328 {}} {258 0 0-4333 {}}} CYCLES {}}
+set a(0-4309) {NAME intensity:slc(intensity#2.sg1)#9 TYPE READSLICE PAR 0-2847 XREFS 22487 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.63706255} PREDS {{146 0 0-4015 {}} {258 0 0-4290 {}}} SUCCS {{259 0 0-4310 {}}} CYCLES {}}
+set a(0-4310) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME FRAME:mul TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-2847 XREFS 22488 LOC {2 0.340472025 2 0.63706255 2 0.63706255 2 0.8385535562499999 2 0.8385535562499999} PREDS {{146 0 0-4015 {}} {259 0 0-4309 {}}} SUCCS {{258 0 0-4338 {}}} CYCLES {}}
+set a(0-4311) {NAME intensity:slc(intensity#2.sg1)#11 TYPE READSLICE PAR 0-2847 XREFS 22489 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.59364335} PREDS {{146 0 0-4015 {}} {258 0 0-4290 {}}} SUCCS {{259 0 0-4312 {}}} CYCLES {}}
+set a(0-4312) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 1 NAME FRAME:mul#1 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-2847 XREFS 22490 LOC {2 0.340472025 2 0.59364335 2 0.59364335 2 0.7715251421744312 2 0.7715251421744312} PREDS {{146 0 0-4015 {}} {259 0 0-4311 {}}} SUCCS {{258 0 0-4337 {}}} CYCLES {}}
+set a(0-4313) {NAME intensity:slc(intensity#2.sg1) TYPE READSLICE PAR 0-2847 XREFS 22491 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.7283234249999999} PREDS {{146 0 0-4015 {}} {258 0 0-4290 {}}} SUCCS {{258 0 0-4336 {}}} CYCLES {}}
+set a(0-4314) {NAME FRAME:slc(acc.imod#12)#6 TYPE READSLICE PAR 0-2847 XREFS 22492 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.629751175} PREDS {{146 0 0-4015 {}} {258 0 0-4308 {}}} SUCCS {{259 0 0-4315 {}}} CYCLES {}}
+set a(0-4315) {NAME FRAME:not#7 TYPE NOT PAR 0-2847 XREFS 22493 LOC {2 0.5228665499999999 2 0.629751175 2 0.629751175 2 0.629751175} PREDS {{146 0 0-4015 {}} {259 0 0-4314 {}}} SUCCS {{258 0 0-4327 {}}} CYCLES {}}
+set a(0-4316) {NAME FRAME:slc(acc.imod#12)#1 TYPE READSLICE PAR 0-2847 XREFS 22494 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-4015 {}} {258 0 0-4308 {}}} SUCCS {{259 0 0-4317 {}}} CYCLES {}}
+set a(0-4317) {NAME FRAME:conc#14 TYPE CONCATENATE PAR 0-2847 XREFS 22495 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-4015 {}} {259 0 0-4316 {}}} SUCCS {{258 0 0-4323 {}}} CYCLES {}}
+set a(0-4318) {NAME FRAME:slc(acc.imod#12)#2 TYPE READSLICE PAR 0-2847 XREFS 22496 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-4015 {}} {258 0 0-4308 {}}} SUCCS {{259 0 0-4319 {}}} CYCLES {}}
+set a(0-4319) {NAME FRAME:not#5 TYPE NOT PAR 0-2847 XREFS 22497 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-4015 {}} {259 0 0-4318 {}}} SUCCS {{258 0 0-4322 {}}} CYCLES {}}
+set a(0-4320) {NAME FRAME:slc(acc.imod#12) TYPE READSLICE PAR 0-2847 XREFS 22498 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-4015 {}} {258 0 0-4308 {}}} SUCCS {{259 0 0-4321 {}}} CYCLES {}}
+set a(0-4321) {NAME FRAME:not#4 TYPE NOT PAR 0-2847 XREFS 22499 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-4015 {}} {259 0 0-4320 {}}} SUCCS {{259 0 0-4322 {}}} CYCLES {}}
+set a(0-4322) {NAME FRAME:conc#15 TYPE CONCATENATE PAR 0-2847 XREFS 22500 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-4015 {}} {258 0 0-4319 {}} {259 0 0-4321 {}}} SUCCS {{259 0 0-4323 {}}} CYCLES {}}
+set a(0-4323) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME FRAME:acc#16 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 22501 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.6297511344969361 2 0.6297511344969361} PREDS {{146 0 0-4015 {}} {258 0 0-4317 {}} {259 0 0-4322 {}}} SUCCS {{259 0 0-4324 {}}} CYCLES {}}
+set a(0-4324) {NAME FRAME:slc#3 TYPE READSLICE PAR 0-2847 XREFS 22502 LOC {2 0.56115605 2 0.629751175 2 0.629751175 2 0.629751175} PREDS {{146 0 0-4015 {}} {259 0 0-4323 {}}} SUCCS {{259 0 0-4325 {}}} CYCLES {}}
+set a(0-4325) {NAME FRAME:slc#2 TYPE READSLICE PAR 0-2847 XREFS 22503 LOC {2 0.56115605 2 0.629751175 2 0.629751175 2 0.629751175} PREDS {{146 0 0-4015 {}} {259 0 0-4324 {}}} SUCCS {{259 0 0-4326 {}}} CYCLES {}}
+set a(0-4326) {NAME FRAME:not#8 TYPE NOT PAR 0-2847 XREFS 22504 LOC {2 0.56115605 2 0.629751175 2 0.629751175 2 0.629751175} PREDS {{146 0 0-4015 {}} {259 0 0-4325 {}}} SUCCS {{259 0 0-4327 {}}} CYCLES {}}
+set a(0-4327) {NAME FRAME:conc#3 TYPE CONCATENATE PAR 0-2847 XREFS 22505 LOC {2 0.56115605 2 0.629751175 2 0.629751175 2 0.629751175} PREDS {{146 0 0-4015 {}} {258 0 0-4315 {}} {259 0 0-4326 {}}} SUCCS {{258 0 0-4329 {}}} CYCLES {}}
+set a(0-4328) {NAME FRAME:slc(acc.imod#12)#5 TYPE READSLICE PAR 0-2847 XREFS 22506 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.629751175} PREDS {{146 0 0-4015 {}} {258 0 0-4308 {}}} SUCCS {{259 0 0-4329 {}}} CYCLES {}}
+set a(0-4329) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME FRAME:acc#10 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-2847 XREFS 22507 LOC {2 0.56115605 2 0.629751175 2 0.629751175 2 0.6569970520708271 2 0.6569970520708271} PREDS {{146 0 0-4015 {}} {258 0 0-4327 {}} {259 0 0-4328 {}}} SUCCS {{258 0 0-4332 {}}} CYCLES {}}
+set a(0-4330) {NAME intensity:slc(intensity#2.sg1)#10 TYPE READSLICE PAR 0-2847 XREFS 22508 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.6569971} PREDS {{146 0 0-4015 {}} {258 0 0-4290 {}}} SUCCS {{259 0 0-4331 {}}} CYCLES {}}
+set a(0-4331) {NAME FRAME:not#6 TYPE NOT PAR 0-2847 XREFS 22509 LOC {2 0.340472025 2 0.6569971 2 0.6569971 2 0.6569971} PREDS {{146 0 0-4015 {}} {259 0 0-4330 {}}} SUCCS {{259 0 0-4332 {}}} CYCLES {}}
+set a(0-4332) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME FRAME:acc#11 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-2847 XREFS 22510 LOC {2 0.588401975 2 0.6569971 2 0.6569971 2 0.6900338701789505 2 0.6900338701789505} PREDS {{146 0 0-4015 {}} {258 0 0-4329 {}} {259 0 0-4331 {}}} SUCCS {{258 0 0-4335 {}}} CYCLES {}}
+set a(0-4333) {NAME FRAME:slc(acc.imod#12)#4 TYPE READSLICE PAR 0-2847 XREFS 22511 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.6900339249999999} PREDS {{146 0 0-4015 {}} {258 0 0-4308 {}}} SUCCS {{259 0 0-4334 {}}} CYCLES {}}
+set a(0-4334) {NAME FRAME:conc#12 TYPE CONCATENATE PAR 0-2847 XREFS 22512 LOC {2 0.5228665499999999 2 0.6900339249999999 2 0.6900339249999999 2 0.6900339249999999} PREDS {{146 0 0-4015 {}} {259 0 0-4333 {}}} SUCCS {{259 0 0-4335 {}}} CYCLES {}}
+set a(0-4335) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME FRAME:acc#12 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-2847 XREFS 22513 LOC {2 0.6214388 2 0.6900339249999999 2 0.6900339249999999 2 0.728323384496936 2 0.728323384496936} PREDS {{146 0 0-4015 {}} {258 0 0-4332 {}} {259 0 0-4334 {}}} SUCCS {{259 0 0-4336 {}}} CYCLES {}}
+set a(0-4336) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME FRAME:acc#13 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-2847 XREFS 22514 LOC {2 0.6597282999999999 2 0.7283234249999999 2 0.7283234249999999 2 0.7715251484103023 2 0.7715251484103023} PREDS {{146 0 0-4015 {}} {258 0 0-4313 {}} {259 0 0-4335 {}}} SUCCS {{259 0 0-4337 {}}} CYCLES {}}
+set a(0-4337) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 1 NAME FRAME:acc#14 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-2847 XREFS 22515 LOC {2 0.7029300749999999 2 0.7715251999999999 2 0.7715251999999999 2 0.8385535568650199 2 0.8385535568650199} PREDS {{146 0 0-4015 {}} {258 0 0-4312 {}} {259 0 0-4336 {}}} SUCCS {{259 0 0-4338 {}}} CYCLES {}}
+set a(0-4338) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,13) AREA_SCORE 12.00 QUANTITY 6 NAME FRAME:acc#15 TYPE ACCU DELAY {1.04 ns} LIBRARY_DELAY {1.04 ns} PAR 0-2847 XREFS 22516 LOC {2 0.7699584749999999 2 0.8385536 2 0.8385536 2 0.9037692313734284 2 0.9037692313734284} PREDS {{146 0 0-4015 {}} {258 0 0-4310 {}} {259 0 0-4337 {}}} SUCCS {{258 0 0-4345 {}}} CYCLES {}}
+set a(0-4339) {NAME intensity:slc(intensity#2.sg1)#12 TYPE READSLICE PAR 0-2847 XREFS 22517 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.9037692749999999} PREDS {{146 0 0-4015 {}} {258 0 0-4290 {}}} SUCCS {{258 0 0-4343 {}}} CYCLES {}}
+set a(0-4340) {NAME intensity:slc(intensity#2.sg1)#13 TYPE READSLICE PAR 0-2847 XREFS 22518 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.9037692749999999} PREDS {{146 0 0-4015 {}} {258 0 0-4290 {}}} SUCCS {{259 0 0-4341 {}}} CYCLES {}}
+set a(0-4341) {NAME FRAME:exs#1 TYPE SIGNEXTEND PAR 0-2847 XREFS 22519 LOC {2 0.340472025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-4015 {}} {259 0 0-4340 {}}} SUCCS {{258 0 0-4343 {}}} CYCLES {}}
+set a(0-4342) {NAME intensity:slc(intensity#2.sg1)#8 TYPE READSLICE PAR 0-2847 XREFS 22520 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.9037692749999999} PREDS {{146 0 0-4015 {}} {258 0 0-4290 {}}} SUCCS {{259 0 0-4343 {}}} CYCLES {}}
+set a(0-4343) {NAME FRAME:conc#2 TYPE CONCATENATE PAR 0-2847 XREFS 22521 LOC {2 0.340472025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-4015 {}} {258 0 0-4341 {}} {258 0 0-4339 {}} {259 0 0-4342 {}}} SUCCS {{259 0 0-4344 {}}} CYCLES {}}
+set a(0-4344) {NAME FRAME:exs TYPE SIGNEXTEND PAR 0-2847 XREFS 22522 LOC {2 0.340472025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-4015 {}} {259 0 0-4343 {}}} SUCCS {{259 0 0-4345 {}}} CYCLES {}}
+set a(0-4345) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME FRAME:acc#2 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-2847 XREFS 22523 LOC {2 0.83517415 2 0.9037692749999999 2 0.9037692749999999 2 0.9832574784997776 2 0.9832574784997776} PREDS {{146 0 0-4015 {}} {258 0 0-4338 {}} {259 0 0-4344 {}}} SUCCS {{259 0 0-4346 {}} {258 0 0-4347 {}} {258 0 0-4350 {}} {258 0 0-4351 {}} {258 0 0-4352 {}} {258 0 0-4355 {}}} CYCLES {}}
+set a(0-4346) {NAME intensity:slc(intensity) TYPE READSLICE PAR 0-2847 XREFS 22524 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-4015 {}} {259 0 0-4345 {}}} SUCCS {{258 0 0-4349 {}}} CYCLES {}}
+set a(0-4347) {NAME intensity:slc(intensity)#1 TYPE READSLICE PAR 0-2847 XREFS 22525 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-4015 {}} {258 0 0-4345 {}}} SUCCS {{259 0 0-4348 {}}} CYCLES {}}
+set a(0-4348) {NAME FRAME:exu TYPE PADZEROES PAR 0-2847 XREFS 22526 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-4015 {}} {259 0 0-4347 {}}} SUCCS {{259 0 0-4349 {}}} CYCLES {}}
+set a(0-4349) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(10,2) AREA_SCORE 7.30 QUANTITY 1 NAME FRAME:or TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-2847 XREFS 22527 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{146 0 0-4015 {}} {258 0 0-4346 {}} {259 0 0-4348 {}}} SUCCS {{258 0 0-4356 {}}} CYCLES {}}
+set a(0-4350) {NAME intensity:slc(intensity)#2 TYPE READSLICE PAR 0-2847 XREFS 22528 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 1.0} PREDS {{146 0 0-4015 {}} {258 0 0-4345 {}}} SUCCS {{258 0 0-4356 {}}} CYCLES {}}
+set a(0-4351) {NAME intensity:slc(intensity)#3 TYPE READSLICE PAR 0-2847 XREFS 22529 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-4015 {}} {258 0 0-4345 {}}} SUCCS {{258 0 0-4354 {}}} CYCLES {}}
+set a(0-4352) {NAME intensity:slc(intensity)#4 TYPE READSLICE PAR 0-2847 XREFS 22530 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-4015 {}} {258 0 0-4345 {}}} SUCCS {{259 0 0-4353 {}}} CYCLES {}}
+set a(0-4353) {NAME FRAME:exu#6 TYPE PADZEROES PAR 0-2847 XREFS 22531 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-4015 {}} {259 0 0-4352 {}}} SUCCS {{259 0 0-4354 {}}} CYCLES {}}
+set a(0-4354) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(6,2) AREA_SCORE 4.38 QUANTITY 1 NAME FRAME:or#3 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-2847 XREFS 22532 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{146 0 0-4015 {}} {258 0 0-4351 {}} {259 0 0-4353 {}}} SUCCS {{258 0 0-4356 {}}} CYCLES {}}
+set a(0-4355) {NAME intensity:slc(intensity)#5 TYPE READSLICE PAR 0-2847 XREFS 22533 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 1.0} PREDS {{146 0 0-4015 {}} {258 0 0-4345 {}}} SUCCS {{259 0 0-4356 {}}} CYCLES {}}
+set a(0-4356) {NAME FRAME:conc#11 TYPE CONCATENATE PAR 0-2847 XREFS 22534 LOC {2 0.9314048749999999 2 1.0 2 1.0 2 1.0} PREDS {{146 0 0-4015 {}} {258 0 0-4354 {}} {258 0 0-4350 {}} {258 0 0-4349 {}} {259 0 0-4355 {}}} SUCCS {{259 0 0-4357 {}}} CYCLES {}}
+set a(0-4357) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(2,30) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_write(vout:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-2847 XREFS 22535 LOC {2 1.0 2 1.0 2 1.0 3 0.0 2 0.9999} PREDS {{130 0 0-4015 {}} {260 0 0-4357 {}} {259 0 0-4356 {}}} SUCCS {{260 0 0-4357 {}}} CYCLES {}}
+set a(0-4358) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(19,0,2,1,19) AREA_SCORE 20.00 QUANTITY 1 NAME FRAME:acc#4 TYPE ACCU DELAY {1.91 ns} LIBRARY_DELAY {1.91 ns} PAR 0-2847 XREFS 22536 LOC {1 0.0641255 1 0.805295525 1 0.805295525 1 0.9245548410815966 1 0.9245548410815966} PREDS {{146 0 0-4015 {}} {258 0 0-2868 {}}} SUCCS {{259 0 0-4359 {}} {258 0 0-4379 {}}} CYCLES {}}
+set a(0-4359) {NAME FRAME:p:slc(FRAME:p)#1 TYPE READSLICE PAR 0-2847 XREFS 22537 LOC {1 0.183384875 1 0.9245549 1 0.9245549 1 0.9245549} PREDS {{146 0 0-4015 {}} {259 0 0-4358 {}}} SUCCS {{259 0 0-4360 {}}} CYCLES {}}
+set a(0-4360) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME FRAME:acc TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-2847 XREFS 22538 LOC {1 0.183384875 1 0.9245549 1 0.9245549 1 0.9769393527684257 1 0.9769393527684257} PREDS {{146 0 0-4015 {}} {259 0 0-4359 {}}} SUCCS {{259 0 0-4361 {}}} CYCLES {}}
+set a(0-4361) {NAME FRAME:slc TYPE READSLICE PAR 0-2847 XREFS 22539 LOC {1 0.23576937499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9769393999999999} PREDS {{146 0 0-4015 {}} {259 0 0-4360 {}}} SUCCS {{259 0 0-4362 {}}} CYCLES {}}
+set a(0-4362) {NAME FRAME:not TYPE NOT PAR 0-2847 XREFS 22540 LOC {1 0.23576937499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9769393999999999} PREDS {{146 0 0-4015 {}} {259 0 0-4361 {}}} SUCCS {{258 0 0-4365 {}} {258 0 0-4366 {}}} CYCLES {}}
+set a(0-4363) {NAME not#1 TYPE NOT PAR 0-2847 XREFS 22541 LOC {1 0.0 1 0.0 1 0.0 1 0.9769393999999999} PREDS {{258 0 0-2870 {}}} SUCCS {{259 0 0-4364 {}}} CYCLES {}}
+set a(0-4364) {NAME FRAME:for:and#2 TYPE AND PAR 0-2847 XREFS 22542 LOC {1 0.0 1 0.0 1 0.0 1 0.9769393999999999} PREDS {{262 0 0-4386 {}} {259 0 0-4363 {}}} SUCCS {{259 0 0-4365 {}} {256 0 0-4386 {}}} CYCLES {}}
+set a(0-4365) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 2 NAME FRAME:for:mux#44 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22543 LOC {1 0.23576937499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 1 0.9999999624999999} PREDS {{258 0 0-4014 {}} {258 0 0-4362 {}} {258 0 0-2848 {}} {259 0 0-4364 {}}} SUCCS {{258 0 0-4386 {}} {258 0 0-4388 {}}} CYCLES {}}
+set a(0-4366) {NAME not#2 TYPE NOT PAR 0-2847 XREFS 22544 LOC {1 0.23576937499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9769393999999999} PREDS {{258 0 0-4362 {}} {258 0 0-2848 {}}} SUCCS {{259 0 0-4367 {}}} CYCLES {}}
+set a(0-4367) {NAME FRAME:for:or#1 TYPE OR PAR 0-2847 XREFS 22545 LOC {1 0.23576937499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9769393999999999} PREDS {{258 0 0-4014 {}} {259 0 0-4366 {}}} SUCCS {{259 0 0-4368 {}}} CYCLES {}}
+set a(0-4368) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 2 NAME FRAME:for:mux#45 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22546 LOC {1 0.23576937499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 1 0.9999999624999999} PREDS {{258 0 0-4014 {}} {259 0 0-4367 {}}} SUCCS {{258 0 0-4387 {}} {258 0 0-4388 {}}} CYCLES {}}
+set a(0-4369) {NAME FRAME:for:asn(acc.imod#6.lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22547 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 2 0.59843245} PREDS {{260 0 0-4369 {}} {258 0 0-3914 {}}} SUCCS {{262 0 0-3914 {}} {260 0 0-4369 {}}} CYCLES {}}
+set a(0-4370) {NAME FRAME:for:asn(acc.imod#7.lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22548 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 2 0.59843245} PREDS {{260 0 0-4370 {}} {258 0 0-3915 {}}} SUCCS {{262 0 0-3915 {}} {260 0 0-4370 {}}} CYCLES {}}
+set a(0-4371) {NAME FRAME:for:asn(regs.regs(0).sva) TYPE ASSIGN PAR 0-2847 XREFS 22549 LOC {1 0.0230606 1 0.57525635 1 0.57525635 2 0.6501168749999999} PREDS {{260 0 0-4371 {}} {256 0 0-3916 {}} {256 0 0-3918 {}} {258 0 0-3917 {}}} SUCCS {{262 0 0-3916 {}} {262 0 0-3918 {}} {260 0 0-4371 {}}} CYCLES {}}
+set a(0-4372) {NAME FRAME:for:asn(regs.regs(1).sva) TYPE ASSIGN PAR 0-2847 XREFS 22550 LOC {1 0.0230606 1 0.57525635 1 0.57525635 2 0.15038815} PREDS {{260 0 0-4372 {}} {256 0 0-3098 {}} {256 0 0-3100 {}} {256 0 0-3103 {}} {256 0 0-3173 {}} {256 0 0-3175 {}} {256 0 0-3178 {}} {256 0 0-3245 {}} {256 0 0-3247 {}} {256 0 0-3250 {}} {256 0 0-3919 {}} {256 0 0-3921 {}} {258 0 0-3920 {}}} SUCCS {{262 0 0-3098 {}} {262 0 0-3100 {}} {262 0 0-3103 {}} {262 0 0-3173 {}} {262 0 0-3175 {}} {262 0 0-3178 {}} {262 0 0-3245 {}} {262 0 0-3247 {}} {262 0 0-3250 {}} {262 0 0-3919 {}} {262 0 0-3921 {}} {260 0 0-4372 {}}} CYCLES {}}
+set a(0-4373) {NAME FRAME:for:asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22551 LOC {1 0.0230606 1 0.57525635 1 0.57525635 2 0.6501168749999999} PREDS {{260 0 0-4373 {}} {258 0 0-3922 {}}} SUCCS {{262 0 0-3922 {}} {260 0 0-4373 {}}} CYCLES {}}
+set a(0-4374) {NAME FRAME:for:asn(in(0).lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22552 LOC {2 0.128961425 2 0.303457375 2 0.303457375 3 0.17449594999999998} PREDS {{260 0 0-4374 {}} {256 0 0-3969 {}} {258 0 0-3970 {}}} SUCCS {{262 0 0-3969 {}} {260 0 0-4374 {}}} CYCLES {}}
+set a(0-4375) {NAME FRAME:for:asn(in(2).lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22553 LOC {2 0.128961425 2 0.19755655 2 0.19755655 3 0.06859512499999999} PREDS {{260 0 0-4375 {}} {256 0 0-4007 {}} {258 0 0-4008 {}}} SUCCS {{262 0 0-4007 {}} {260 0 0-4375 {}}} CYCLES {}}
+set a(0-4376) {NAME FRAME:for:asn(ACC1:acc#118.psp.lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22554 LOC {1 0.34298077499999996 1 0.57964955 1 0.57964955 2 0.744095325} PREDS {{260 0 0-4376 {}} {258 0 0-3923 {}}} SUCCS {{262 0 0-3923 {}} {260 0 0-4376 {}}} CYCLES {}}
+set a(0-4377) {NAME FRAME:for:asn(ACC1:acc#125.psp.lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22555 LOC {1 0.16961555 1 0.3151275 1 0.3151275 2 0.47957327499999997} PREDS {{260 0 0-4377 {}} {258 0 0-3924 {}}} SUCCS {{262 0 0-3924 {}} {260 0 0-4377 {}}} CYCLES {}}
+set a(0-4378) {NAME FRAME:for:asn(ACC1:acc#110.psp#1.lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22556 LOC {1 0.281724925 1 0.433986675 1 0.433986675 2 0.59843245} PREDS {{260 0 0-4378 {}} {258 0 0-3925 {}}} SUCCS {{262 0 0-3925 {}} {260 0 0-4378 {}}} CYCLES {}}
+set a(0-4379) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(19,1,2) AREA_SCORE 17.47 QUANTITY 1 NAME FRAME:for:mux#42 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-2847 XREFS 22557 LOC {1 0.183384875 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.7888887124999999} PREDS {{260 0 0-4379 {}} {258 0 0-4014 {}} {258 0 0-2868 {}} {258 0 0-4358 {}} {258 0 0-2849 {}}} SUCCS {{262 0 0-2868 {}} {260 0 0-4379 {}}} CYCLES {}}
+set a(0-4380) {NAME FRAME:for:asn(i#6.lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22558 LOC {1 0.036879575 1 0.287881575 1 0.287881575 2 0.438508375} PREDS {{260 0 0-4380 {}} {256 0 0-3928 {}} {258 0 0-4009 {}}} SUCCS {{262 0 0-3928 {}} {260 0 0-4380 {}}} CYCLES {}}
+set a(0-4381) {NAME FRAME:for:asn(acc.imod#18.lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22559 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 2 0.59843245} PREDS {{260 0 0-4381 {}} {258 0 0-3929 {}}} SUCCS {{262 0 0-3929 {}} {260 0 0-4381 {}}} CYCLES {}}
+set a(0-4382) {NAME FRAME:for:asn(acc.imod#20.lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22560 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 2 0.644875075} PREDS {{260 0 0-4382 {}} {258 0 0-3930 {}}} SUCCS {{262 0 0-3930 {}} {260 0 0-4382 {}}} CYCLES {}}
+set a(0-4383) {NAME FRAME:for:asn(ACC1:acc#118.psp#1.lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22561 LOC {1 0.34298077499999996 1 0.58544045 1 0.58544045 2 0.749886225} PREDS {{260 0 0-4383 {}} {258 0 0-3931 {}}} SUCCS {{262 0 0-3931 {}} {260 0 0-4383 {}}} CYCLES {}}
+set a(0-4384) {NAME FRAME:for:asn(ACC1:acc#125.psp#1.lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22562 LOC {1 0.16961555 1 0.3151275 1 0.3151275 2 0.47957327499999997} PREDS {{260 0 0-4384 {}} {258 0 0-3932 {}}} SUCCS {{262 0 0-3932 {}} {260 0 0-4384 {}}} CYCLES {}}
+set a(0-4385) {NAME FRAME:for:asn(ACC1:acc#110.psp#2.lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22563 LOC {1 0.281724925 1 0.433986675 1 0.433986675 2 0.59843245} PREDS {{260 0 0-4385 {}} {258 0 0-3933 {}}} SUCCS {{262 0 0-3933 {}} {260 0 0-4385 {}}} CYCLES {}}
+set a(0-4386) {NAME FRAME:for:asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22564 LOC {1 0.258829975 1 1.0 1 1.0 2 0.9769393999999999} PREDS {{260 0 0-4386 {}} {256 0 0-4364 {}} {258 0 0-4365 {}}} SUCCS {{262 0 0-4364 {}} {260 0 0-4386 {}}} CYCLES {}}
+set a(0-4387) {NAME FRAME:for:asn(exit:FRAME:for.lpi#1) TYPE ASSIGN PAR 0-2847 XREFS 22565 LOC {1 0.258829975 1 1.0 1 1.0 2 0.013988325} PREDS {{260 0 0-4387 {}} {256 0 0-2870 {}} {258 0 0-4368 {}}} SUCCS {{262 0 0-2870 {}} {260 0 0-4387 {}}} CYCLES {}}
+set a(0-4388) {NAME FRAME:and TYPE AND PAR 0-2847 XREFS 22566 LOC {1 0.258829975 1 1.0 1 1.0 2 0.013988325} PREDS {{258 0 0-4365 {}} {258 0 0-4368 {}}} SUCCS {{259 0 0-4389 {}}} CYCLES {}}
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3.0 CYCLES_IN 921602 TOTAL_CYCLES_IN 921602 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 921602 NAME main TYPE LOOP DELAY {18432060.00 ns} PAR 0-2826 XREFS 22568 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{258 0 0-2841 {}} {258 0 0-2828 {}} {258 0 0-2829 {}} {258 0 0-2838 {}} {258 0 0-2839 {}} {258 0 0-2837 {}} {258 0 0-2835 {}} {258 0 0-2836 {}} {258 0 0-2827 {}} {258 0 0-2833 {}} {258 0 0-2834 {}} {258 0 0-2832 {}} {258 0 0-2840 {}} {258 0 0-2845 {}} {258 0 0-2830 {}} {258 0 0-2831 {}} {258 0 0-2844 {}} {258 0 0-2842 {}} {258 0 0-2843 {}} {259 0 0-2846 {}}} SUCCS {{772 0 0-2827 {}} {772 0 0-2828 {}} {772 0 0-2829 {}} {772 0 0-2830 {}} {772 0 0-2831 {}} {772 0 0-2832 {}} {772 0 0-2833 {}} {772 0 0-2834 {}} {772 0 0-2835 {}} {772 0 0-2836 {}} {772 0 0-2837 {}} {772 0 0-2838 {}} {772 0 0-2839 {}} {772 0 0-2840 {}} {772 0 0-2841 {}} {772 0 0-2842 {}} {772 0 0-2843 {}} {772 0 0-2844 {}} {772 0 0-2845 {}} {772 0 0-2846 {}}} CYCLES {}}
+set a(0-2826) {CHI {0-2827 0-2828 0-2829 0-2830 0-2831 0-2832 0-2833 0-2834 0-2835 0-2836 0-2837 0-2838 0-2839 0-2840 0-2841 0-2842 0-2843 0-2844 0-2845 0-2846 0-2847} ITERATIONS Infinite LATENCY 921601 RESET_LATENCY 0 CSTEPS 0 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 921600 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 0 TOTAL_CYCLES_IN 0 TOTAL_CYCLES_UNDER 921602 TOTAL_CYCLES 921602 NAME core:rlp TYPE LOOP DELAY {18432060.00 ns} PAR {} XREFS 22569 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-2826-TOTALCYCLES) {921602}
+set a(0-2826-QMOD) {mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2) 0-2868 mgc_ioport.mgc_in_wire(1,90) 0-2872 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11) {0-2877 0-2880 0-2953 0-2956 0-3026 0-3029 0-3102 0-3177 0-3249} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12) {0-2881 0-2957 0-3030 0-3105 0-3180 0-3252 0-3998} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4) {0-2889 0-2932 0-3005 0-3038 0-3081 0-3113 0-3156 0-3228 0-3260 0-3303 0-4009} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5) {0-2896 0-3045 0-3120 0-3267 0-3345 0-3488 0-3642 0-3785} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3) {0-2905 0-2914 0-2928 0-2968 0-2982 0-3001 0-3054 0-3063 0-3077 0-3129 0-3138 0-3152 0-3191 0-3205 0-3224 0-3276 0-3285 0-3299 0-3355 0-3377 0-3498 0-3520 0-3652 0-3674 0-3795 0-3817} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4) {0-2919 0-3068 0-3143 0-3290 0-3389 0-3391 0-3431 0-3441 0-3443 0-3451 0-3460 0-3462 0-3532 0-3534 0-3578 0-3588 0-3590 0-3598 0-3607 0-3609 0-3686 0-3688 0-3728 0-3738 0-3740 0-3748 0-3757 0-3759 0-3829 0-3831 0-3875 0-3885 0-3887 0-3895 0-3904 0-3906 0-4056 0-4065 0-4067 0-4075 0-4088 0-4090 0-4102 0-4111 0-4113 0-4121 0-4130 0-4132 0-4143 0-4152 0-4154 0-4162 0-4171 0-4173 0-4182 0-4191 0-4193 0-4203 0-4294 0-4306} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6) {0-2921 0-2973 0-3070 0-3145 0-3196 0-3292 0-3356 0-3499 0-3653 0-3796 0-4233 0-4243 0-4332} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5) {0-2938 0-2947 0-2989 0-3011 0-3020 0-3087 0-3096 0-3162 0-3171 0-3212 0-3234 0-3243 0-3309 0-3318 0-3343 0-3486 0-3640 0-3783 0-4012 0-4241 0-4301 0-4329} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7) {0-2993 0-3216 0-3357 0-3392 0-3500 0-3535 0-3654 0-3689 0-3797 0-3832 0-4269 0-4307 0-4323 0-4335} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4) {0-3330 0-3333 0-3473 0-3476 0-3627 0-3630 0-3770 0-3773} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9) {0-3363 0-3393 0-3506 0-3536 0-3660 0-3690 0-3803 0-3833 0-4135 0-4276} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10) {0-3394 0-3465 0-3537 0-3612 0-3691 0-3762 0-3834 0-3909 0-4042 0-4245 0-4360} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11) {0-3402 0-3538 0-3699 0-3835 0-4246 0-4277} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) {0-3403 0-3615 0-3700 0-3912 0-3959 0-4004 0-4345} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5) {0-3463 0-3610 0-3760 0-3907 0-4091 0-4133 0-4174 0-4217 0-4219 0-4265 0-4302} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8) {0-3464 0-3611 0-3761 0-3908 0-4244 0-4270 0-4308 0-4336} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,0,10) {0-3466 0-3613 0-3763 0-3910 0-4043} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,11) {0-3549 0-3846} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13) {0-3550 0-3614 0-3847 0-3911 0-4286 0-4338} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(3,1,2) {0-3914 0-3923 0-3929 0-3931} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2) {0-3915 0-3930} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2) {0-3917 0-3920 0-3922} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(12,1,2) {0-3924 0-3932} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(4,1,2) {0-3925 0-3933} mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2) {0-3928 0-3982} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4) {0-3950 0-3956 0-3963 0-3991 0-3996 0-4002} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12) {0-3952 0-3958 0-3965 0-3992 0-3997 0-4003} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,0,12,1,13) {0-3966 0-4247} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2) {0-3969 0-4007} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,13,1,16) {0-3970 0-4008 0-4288} mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(2,2) 0-3987 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2) {0-4018 0-4022 0-4030 0-4034 0-4250 0-4280} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13) {0-4019 0-4023 0-4031 0-4035 0-4251 0-4281 0-4310} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7) 0-4041 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6) {0-4134 0-4220} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,0,13,0,13) 0-4287 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16) 0-4289 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9) 0-4312 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10) 0-4337 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2) 0-4349 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2) 0-4354 mgc_ioport.mgc_out_stdreg(2,30) 0-4357 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19) 0-4358 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2) {0-4365 0-4368} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2) 0-4379}
+set a(0-2826-PROC_NAME) {core}
+set a(0-2826-HIER_NAME) {/sobel/core}
+set a(TOP) {0-2826}
+
diff --git a/Sobel/sobel.v7/schematic.nlv b/Sobel/sobel.v7/schematic.nlv
new file mode 100644
index 0000000..331d7dd
--- /dev/null
+++ b/Sobel/sobel.v7/schematic.nlv
@@ -0,0 +1,15334 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "sobel:core" "orig"
+load port {clk} input -attr xrf 24705 -attr oid 1 -attr vt d -attr @path {/sobel/sobel:core/clk}
+load port {en} input -attr xrf 24706 -attr oid 2 -attr vt d -attr @path {/sobel/sobel:core/en}
+load port {arst_n} input -attr xrf 24707 -attr oid 3 -attr vt d -attr @path {/sobel/sobel:core/arst_n}
+load portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} -attr xrf 24708 -attr oid 4 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} -attr xrf 24709 -attr oid 5 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load symbol "or(2,10)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,6)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(5:0)} input 6 {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(5:0)} input 6 {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nand(2,1)" "INTERFACE" NAND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,30)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(29:0)} input 30 {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(29:0)} input 30 {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(30,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(29:0)} input 30 {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(29:0)} input 30 {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,16)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(15:0)} input 16 {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(15:0)} input 16 {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(16,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(15:0)} input 16 {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(15:0)} input 16 {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(1,0,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,12,1,13)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,5,0,6)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,7,0,8)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,6,0,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,-1,7,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "and(3,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(4,0,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,6,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,-1,4,-1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,4,0,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,-1,8,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(13,-1,10,0,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(12:0)} input 13 {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,10)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,1,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,1,7,0,9)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,9,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,11,0,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(13,-1,13,-1,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(12:0)} input 13 {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(12:0)} input 13 {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(13,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(12:0)} input 13 {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(12:0)} input 13 {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(1,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(0:0)} input 1 {D(0)} \
+     portBus {DRa(0:0)} input 1 {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(4,10)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {A2(9:0)} input 10 {A2(9)} {A2(8)} {A2(7)} {A2(6)} {A2(5)} {A2(4)} {A2(3)} {A2(2)} {A2(1)} {A2(0)} \
+     portBus {A3(9:0)} input 10 {A3(9)} {A3(8)} {A3(7)} {A3(6)} {A3(5)} {A3(4)} {A3(3)} {A3(2)} {A3(1)} {A3(0)} \
+     portBus {S(1:0)} input.top 2 {S(1)} {S(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,11,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,-1,11,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(12,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(11:0)} input 12 {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(11:0)} input 12 {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,2,1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,2,1,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,4,-1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,1,7,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,1,8,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,10,0,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,11,-1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,0,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,10,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(1,0,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,-1,11,-1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,10,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,12,-1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,12)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,1,12,1,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(13,-1,12,1,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(12:0)} input 13 {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(2,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(1:0)} input 2 {D(1)} {D(0)} \
+     portBus {DRa(1:0)} input 2 {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "and(2,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "reg(3,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(2:0)} input 3 {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(2:0)} input 3 {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(90,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(89:0)} input 90 {D(89)} {D(88)} {D(87)} {D(86)} {D(85)} {D(84)} {D(83)} {D(82)} {D(81)} {D(80)} {D(79)} {D(78)} {D(77)} {D(76)} {D(75)} {D(74)} {D(73)} {D(72)} {D(71)} {D(70)} {D(69)} {D(68)} {D(67)} {D(66)} {D(65)} {D(64)} {D(63)} {D(62)} {D(61)} {D(60)} {D(59)} {D(58)} {D(57)} {D(56)} {D(55)} {D(54)} {D(53)} {D(52)} {D(51)} {D(50)} {D(49)} {D(48)} {D(47)} {D(46)} {D(45)} {D(44)} {D(43)} {D(42)} {D(41)} {D(40)} {D(39)} {D(38)} {D(37)} {D(36)} {D(35)} {D(34)} {D(33)} {D(32)} {D(31)} {D(30)} {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(89:0)} input 90 {DRa(89)} {DRa(88)} {DRa(87)} {DRa(86)} {DRa(85)} {DRa(84)} {DRa(83)} {DRa(82)} {DRa(81)} {DRa(80)} {DRa(79)} {DRa(78)} {DRa(77)} {DRa(76)} {DRa(75)} {DRa(74)} {DRa(73)} {DRa(72)} {DRa(71)} {DRa(70)} {DRa(69)} {DRa(68)} {DRa(67)} {DRa(66)} {DRa(65)} {DRa(64)} {DRa(63)} {DRa(62)} {DRa(61)} {DRa(60)} {DRa(59)} {DRa(58)} {DRa(57)} {DRa(56)} {DRa(55)} {DRa(54)} {DRa(53)} {DRa(52)} {DRa(51)} {DRa(50)} {DRa(49)} {DRa(48)} {DRa(47)} {DRa(46)} {DRa(45)} {DRa(44)} {DRa(43)} {DRa(42)} {DRa(41)} {DRa(40)} {DRa(39)} {DRa(38)} {DRa(37)} {DRa(36)} {DRa(35)} {DRa(34)} {DRa(33)} {DRa(32)} {DRa(31)} {DRa(30)} {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,19)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(19,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(18:0)} input 19 {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(18:0)} input 19 {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,6,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(3)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,0,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,-1,11,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,13,1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(12:0)} input 13 {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,16,-1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,-1,6,-1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,1,16,-1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(13,1,16,-1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(12:0)} input 13 {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "or(2,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "and(2,2)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(1:0)} input 2 {A0(1)} {A0(0)} \
+     portBus {A1(1:0)} input 2 {A1(1)} {A1(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "mux(2,3)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(2:0)} input 3 {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(2:0)} input 3 {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,12)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(11:0)} input 12 {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(11:0)} input 12 {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,2)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(1:0)} input 2 {A0(1)} {A0(0)} \
+     portBus {A1(1:0)} input 2 {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "mux(2,90)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(89:0)} input 90 {A0(89)} {A0(88)} {A0(87)} {A0(86)} {A0(85)} {A0(84)} {A0(83)} {A0(82)} {A0(81)} {A0(80)} {A0(79)} {A0(78)} {A0(77)} {A0(76)} {A0(75)} {A0(74)} {A0(73)} {A0(72)} {A0(71)} {A0(70)} {A0(69)} {A0(68)} {A0(67)} {A0(66)} {A0(65)} {A0(64)} {A0(63)} {A0(62)} {A0(61)} {A0(60)} {A0(59)} {A0(58)} {A0(57)} {A0(56)} {A0(55)} {A0(54)} {A0(53)} {A0(52)} {A0(51)} {A0(50)} {A0(49)} {A0(48)} {A0(47)} {A0(46)} {A0(45)} {A0(44)} {A0(43)} {A0(42)} {A0(41)} {A0(40)} {A0(39)} {A0(38)} {A0(37)} {A0(36)} {A0(35)} {A0(34)} {A0(33)} {A0(32)} {A0(31)} {A0(30)} {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(89:0)} input 90 {A1(89)} {A1(88)} {A1(87)} {A1(86)} {A1(85)} {A1(84)} {A1(83)} {A1(82)} {A1(81)} {A1(80)} {A1(79)} {A1(78)} {A1(77)} {A1(76)} {A1(75)} {A1(74)} {A1(73)} {A1(72)} {A1(71)} {A1(70)} {A1(69)} {A1(68)} {A1(67)} {A1(66)} {A1(65)} {A1(64)} {A1(63)} {A1(62)} {A1(61)} {A1(60)} {A1(59)} {A1(58)} {A1(57)} {A1(56)} {A1(55)} {A1(54)} {A1(53)} {A1(52)} {A1(51)} {A1(50)} {A1(49)} {A1(48)} {A1(47)} {A1(46)} {A1(45)} {A1(44)} {A1(43)} {A1(42)} {A1(41)} {A1(40)} {A1(39)} {A1(38)} {A1(37)} {A1(36)} {A1(35)} {A1(34)} {A1(33)} {A1(32)} {A1(31)} {A1(30)} {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(2)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,1,1,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,-1,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(10)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,10,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,2,0,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,1,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,4,1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,8,-1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,1)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(19,-1,1,0,19)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(18:0)} input 19 {A(18)} {A(17)} {A(16)} {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,19)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nor(2,1)" "INTERFACE" NOR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "or(3,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load net {FRAME:p#1.lpi#1(0)} -attr vt d
+load net {FRAME:p#1.lpi#1(1)} -attr vt d
+load net {FRAME:p#1.lpi#1(2)} -attr vt d
+load net {FRAME:p#1.lpi#1(3)} -attr vt d
+load net {FRAME:p#1.lpi#1(4)} -attr vt d
+load net {FRAME:p#1.lpi#1(5)} -attr vt d
+load net {FRAME:p#1.lpi#1(6)} -attr vt d
+load net {FRAME:p#1.lpi#1(7)} -attr vt d
+load net {FRAME:p#1.lpi#1(8)} -attr vt d
+load net {FRAME:p#1.lpi#1(9)} -attr vt d
+load net {FRAME:p#1.lpi#1(10)} -attr vt d
+load net {FRAME:p#1.lpi#1(11)} -attr vt d
+load net {FRAME:p#1.lpi#1(12)} -attr vt d
+load net {FRAME:p#1.lpi#1(13)} -attr vt d
+load net {FRAME:p#1.lpi#1(14)} -attr vt d
+load net {FRAME:p#1.lpi#1(15)} -attr vt d
+load net {FRAME:p#1.lpi#1(16)} -attr vt d
+load net {FRAME:p#1.lpi#1(17)} -attr vt d
+load net {FRAME:p#1.lpi#1(18)} -attr vt d
+load netBundle {FRAME:p#1.lpi#1} 19 {FRAME:p#1.lpi#1(0)} {FRAME:p#1.lpi#1(1)} {FRAME:p#1.lpi#1(2)} {FRAME:p#1.lpi#1(3)} {FRAME:p#1.lpi#1(4)} {FRAME:p#1.lpi#1(5)} {FRAME:p#1.lpi#1(6)} {FRAME:p#1.lpi#1(7)} {FRAME:p#1.lpi#1(8)} {FRAME:p#1.lpi#1(9)} {FRAME:p#1.lpi#1(10)} {FRAME:p#1.lpi#1(11)} {FRAME:p#1.lpi#1(12)} {FRAME:p#1.lpi#1(13)} {FRAME:p#1.lpi#1(14)} {FRAME:p#1.lpi#1(15)} {FRAME:p#1.lpi#1(16)} {FRAME:p#1.lpi#1(17)} {FRAME:p#1.lpi#1(18)} -attr xrf 24710 -attr oid 6 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {regs.regs(1).sva(0)} -attr vt d
+load net {regs.regs(1).sva(1)} -attr vt d
+load net {regs.regs(1).sva(2)} -attr vt d
+load net {regs.regs(1).sva(3)} -attr vt d
+load net {regs.regs(1).sva(4)} -attr vt d
+load net {regs.regs(1).sva(5)} -attr vt d
+load net {regs.regs(1).sva(6)} -attr vt d
+load net {regs.regs(1).sva(7)} -attr vt d
+load net {regs.regs(1).sva(8)} -attr vt d
+load net {regs.regs(1).sva(9)} -attr vt d
+load net {regs.regs(1).sva(10)} -attr vt d
+load net {regs.regs(1).sva(11)} -attr vt d
+load net {regs.regs(1).sva(12)} -attr vt d
+load net {regs.regs(1).sva(13)} -attr vt d
+load net {regs.regs(1).sva(14)} -attr vt d
+load net {regs.regs(1).sva(15)} -attr vt d
+load net {regs.regs(1).sva(16)} -attr vt d
+load net {regs.regs(1).sva(17)} -attr vt d
+load net {regs.regs(1).sva(18)} -attr vt d
+load net {regs.regs(1).sva(19)} -attr vt d
+load net {regs.regs(1).sva(20)} -attr vt d
+load net {regs.regs(1).sva(21)} -attr vt d
+load net {regs.regs(1).sva(22)} -attr vt d
+load net {regs.regs(1).sva(23)} -attr vt d
+load net {regs.regs(1).sva(24)} -attr vt d
+load net {regs.regs(1).sva(25)} -attr vt d
+load net {regs.regs(1).sva(26)} -attr vt d
+load net {regs.regs(1).sva(27)} -attr vt d
+load net {regs.regs(1).sva(28)} -attr vt d
+load net {regs.regs(1).sva(29)} -attr vt d
+load net {regs.regs(1).sva(30)} -attr vt d
+load net {regs.regs(1).sva(31)} -attr vt d
+load net {regs.regs(1).sva(32)} -attr vt d
+load net {regs.regs(1).sva(33)} -attr vt d
+load net {regs.regs(1).sva(34)} -attr vt d
+load net {regs.regs(1).sva(35)} -attr vt d
+load net {regs.regs(1).sva(36)} -attr vt d
+load net {regs.regs(1).sva(37)} -attr vt d
+load net {regs.regs(1).sva(38)} -attr vt d
+load net {regs.regs(1).sva(39)} -attr vt d
+load net {regs.regs(1).sva(40)} -attr vt d
+load net {regs.regs(1).sva(41)} -attr vt d
+load net {regs.regs(1).sva(42)} -attr vt d
+load net {regs.regs(1).sva(43)} -attr vt d
+load net {regs.regs(1).sva(44)} -attr vt d
+load net {regs.regs(1).sva(45)} -attr vt d
+load net {regs.regs(1).sva(46)} -attr vt d
+load net {regs.regs(1).sva(47)} -attr vt d
+load net {regs.regs(1).sva(48)} -attr vt d
+load net {regs.regs(1).sva(49)} -attr vt d
+load net {regs.regs(1).sva(50)} -attr vt d
+load net {regs.regs(1).sva(51)} -attr vt d
+load net {regs.regs(1).sva(52)} -attr vt d
+load net {regs.regs(1).sva(53)} -attr vt d
+load net {regs.regs(1).sva(54)} -attr vt d
+load net {regs.regs(1).sva(55)} -attr vt d
+load net {regs.regs(1).sva(56)} -attr vt d
+load net {regs.regs(1).sva(57)} -attr vt d
+load net {regs.regs(1).sva(58)} -attr vt d
+load net {regs.regs(1).sva(59)} -attr vt d
+load net {regs.regs(1).sva(60)} -attr vt d
+load net {regs.regs(1).sva(61)} -attr vt d
+load net {regs.regs(1).sva(62)} -attr vt d
+load net {regs.regs(1).sva(63)} -attr vt d
+load net {regs.regs(1).sva(64)} -attr vt d
+load net {regs.regs(1).sva(65)} -attr vt d
+load net {regs.regs(1).sva(66)} -attr vt d
+load net {regs.regs(1).sva(67)} -attr vt d
+load net {regs.regs(1).sva(68)} -attr vt d
+load net {regs.regs(1).sva(69)} -attr vt d
+load net {regs.regs(1).sva(70)} -attr vt d
+load net {regs.regs(1).sva(71)} -attr vt d
+load net {regs.regs(1).sva(72)} -attr vt d
+load net {regs.regs(1).sva(73)} -attr vt d
+load net {regs.regs(1).sva(74)} -attr vt d
+load net {regs.regs(1).sva(75)} -attr vt d
+load net {regs.regs(1).sva(76)} -attr vt d
+load net {regs.regs(1).sva(77)} -attr vt d
+load net {regs.regs(1).sva(78)} -attr vt d
+load net {regs.regs(1).sva(79)} -attr vt d
+load net {regs.regs(1).sva(80)} -attr vt d
+load net {regs.regs(1).sva(81)} -attr vt d
+load net {regs.regs(1).sva(82)} -attr vt d
+load net {regs.regs(1).sva(83)} -attr vt d
+load net {regs.regs(1).sva(84)} -attr vt d
+load net {regs.regs(1).sva(85)} -attr vt d
+load net {regs.regs(1).sva(86)} -attr vt d
+load net {regs.regs(1).sva(87)} -attr vt d
+load net {regs.regs(1).sva(88)} -attr vt d
+load net {regs.regs(1).sva(89)} -attr vt d
+load netBundle {regs.regs(1).sva} 90 {regs.regs(1).sva(0)} {regs.regs(1).sva(1)} {regs.regs(1).sva(2)} {regs.regs(1).sva(3)} {regs.regs(1).sva(4)} {regs.regs(1).sva(5)} {regs.regs(1).sva(6)} {regs.regs(1).sva(7)} {regs.regs(1).sva(8)} {regs.regs(1).sva(9)} {regs.regs(1).sva(10)} {regs.regs(1).sva(11)} {regs.regs(1).sva(12)} {regs.regs(1).sva(13)} {regs.regs(1).sva(14)} {regs.regs(1).sva(15)} {regs.regs(1).sva(16)} {regs.regs(1).sva(17)} {regs.regs(1).sva(18)} {regs.regs(1).sva(19)} {regs.regs(1).sva(20)} {regs.regs(1).sva(21)} {regs.regs(1).sva(22)} {regs.regs(1).sva(23)} {regs.regs(1).sva(24)} {regs.regs(1).sva(25)} {regs.regs(1).sva(26)} {regs.regs(1).sva(27)} {regs.regs(1).sva(28)} {regs.regs(1).sva(29)} {regs.regs(1).sva(30)} {regs.regs(1).sva(31)} {regs.regs(1).sva(32)} {regs.regs(1).sva(33)} {regs.regs(1).sva(34)} {regs.regs(1).sva(35)} {regs.regs(1).sva(36)} {regs.regs(1).sva(37)} {regs.regs(1).sva(38)} {regs.regs(1).sva(39)} {regs.regs(1).sva(40)} {regs.regs(1).sva(41)} {regs.regs(1).sva(42)} {regs.regs(1).sva(43)} {regs.regs(1).sva(44)} {regs.regs(1).sva(45)} {regs.regs(1).sva(46)} {regs.regs(1).sva(47)} {regs.regs(1).sva(48)} {regs.regs(1).sva(49)} {regs.regs(1).sva(50)} {regs.regs(1).sva(51)} {regs.regs(1).sva(52)} {regs.regs(1).sva(53)} {regs.regs(1).sva(54)} {regs.regs(1).sva(55)} {regs.regs(1).sva(56)} {regs.regs(1).sva(57)} {regs.regs(1).sva(58)} {regs.regs(1).sva(59)} {regs.regs(1).sva(60)} {regs.regs(1).sva(61)} {regs.regs(1).sva(62)} {regs.regs(1).sva(63)} {regs.regs(1).sva(64)} {regs.regs(1).sva(65)} {regs.regs(1).sva(66)} {regs.regs(1).sva(67)} {regs.regs(1).sva(68)} {regs.regs(1).sva(69)} {regs.regs(1).sva(70)} {regs.regs(1).sva(71)} {regs.regs(1).sva(72)} {regs.regs(1).sva(73)} {regs.regs(1).sva(74)} {regs.regs(1).sva(75)} {regs.regs(1).sva(76)} {regs.regs(1).sva(77)} {regs.regs(1).sva(78)} {regs.regs(1).sva(79)} {regs.regs(1).sva(80)} {regs.regs(1).sva(81)} {regs.regs(1).sva(82)} {regs.regs(1).sva(83)} {regs.regs(1).sva(84)} {regs.regs(1).sva(85)} {regs.regs(1).sva(86)} {regs.regs(1).sva(87)} {regs.regs(1).sva(88)} {regs.regs(1).sva(89)} -attr xrf 24711 -attr oid 7 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -attr vt d
+load net {regs.regs(0).sva(1)} -attr vt d
+load net {regs.regs(0).sva(2)} -attr vt d
+load net {regs.regs(0).sva(3)} -attr vt d
+load net {regs.regs(0).sva(4)} -attr vt d
+load net {regs.regs(0).sva(5)} -attr vt d
+load net {regs.regs(0).sva(6)} -attr vt d
+load net {regs.regs(0).sva(7)} -attr vt d
+load net {regs.regs(0).sva(8)} -attr vt d
+load net {regs.regs(0).sva(9)} -attr vt d
+load net {regs.regs(0).sva(10)} -attr vt d
+load net {regs.regs(0).sva(11)} -attr vt d
+load net {regs.regs(0).sva(12)} -attr vt d
+load net {regs.regs(0).sva(13)} -attr vt d
+load net {regs.regs(0).sva(14)} -attr vt d
+load net {regs.regs(0).sva(15)} -attr vt d
+load net {regs.regs(0).sva(16)} -attr vt d
+load net {regs.regs(0).sva(17)} -attr vt d
+load net {regs.regs(0).sva(18)} -attr vt d
+load net {regs.regs(0).sva(19)} -attr vt d
+load net {regs.regs(0).sva(20)} -attr vt d
+load net {regs.regs(0).sva(21)} -attr vt d
+load net {regs.regs(0).sva(22)} -attr vt d
+load net {regs.regs(0).sva(23)} -attr vt d
+load net {regs.regs(0).sva(24)} -attr vt d
+load net {regs.regs(0).sva(25)} -attr vt d
+load net {regs.regs(0).sva(26)} -attr vt d
+load net {regs.regs(0).sva(27)} -attr vt d
+load net {regs.regs(0).sva(28)} -attr vt d
+load net {regs.regs(0).sva(29)} -attr vt d
+load net {regs.regs(0).sva(30)} -attr vt d
+load net {regs.regs(0).sva(31)} -attr vt d
+load net {regs.regs(0).sva(32)} -attr vt d
+load net {regs.regs(0).sva(33)} -attr vt d
+load net {regs.regs(0).sva(34)} -attr vt d
+load net {regs.regs(0).sva(35)} -attr vt d
+load net {regs.regs(0).sva(36)} -attr vt d
+load net {regs.regs(0).sva(37)} -attr vt d
+load net {regs.regs(0).sva(38)} -attr vt d
+load net {regs.regs(0).sva(39)} -attr vt d
+load net {regs.regs(0).sva(40)} -attr vt d
+load net {regs.regs(0).sva(41)} -attr vt d
+load net {regs.regs(0).sva(42)} -attr vt d
+load net {regs.regs(0).sva(43)} -attr vt d
+load net {regs.regs(0).sva(44)} -attr vt d
+load net {regs.regs(0).sva(45)} -attr vt d
+load net {regs.regs(0).sva(46)} -attr vt d
+load net {regs.regs(0).sva(47)} -attr vt d
+load net {regs.regs(0).sva(48)} -attr vt d
+load net {regs.regs(0).sva(49)} -attr vt d
+load net {regs.regs(0).sva(50)} -attr vt d
+load net {regs.regs(0).sva(51)} -attr vt d
+load net {regs.regs(0).sva(52)} -attr vt d
+load net {regs.regs(0).sva(53)} -attr vt d
+load net {regs.regs(0).sva(54)} -attr vt d
+load net {regs.regs(0).sva(55)} -attr vt d
+load net {regs.regs(0).sva(56)} -attr vt d
+load net {regs.regs(0).sva(57)} -attr vt d
+load net {regs.regs(0).sva(58)} -attr vt d
+load net {regs.regs(0).sva(59)} -attr vt d
+load net {regs.regs(0).sva(60)} -attr vt d
+load net {regs.regs(0).sva(61)} -attr vt d
+load net {regs.regs(0).sva(62)} -attr vt d
+load net {regs.regs(0).sva(63)} -attr vt d
+load net {regs.regs(0).sva(64)} -attr vt d
+load net {regs.regs(0).sva(65)} -attr vt d
+load net {regs.regs(0).sva(66)} -attr vt d
+load net {regs.regs(0).sva(67)} -attr vt d
+load net {regs.regs(0).sva(68)} -attr vt d
+load net {regs.regs(0).sva(69)} -attr vt d
+load net {regs.regs(0).sva(70)} -attr vt d
+load net {regs.regs(0).sva(71)} -attr vt d
+load net {regs.regs(0).sva(72)} -attr vt d
+load net {regs.regs(0).sva(73)} -attr vt d
+load net {regs.regs(0).sva(74)} -attr vt d
+load net {regs.regs(0).sva(75)} -attr vt d
+load net {regs.regs(0).sva(76)} -attr vt d
+load net {regs.regs(0).sva(77)} -attr vt d
+load net {regs.regs(0).sva(78)} -attr vt d
+load net {regs.regs(0).sva(79)} -attr vt d
+load net {regs.regs(0).sva(80)} -attr vt d
+load net {regs.regs(0).sva(81)} -attr vt d
+load net {regs.regs(0).sva(82)} -attr vt d
+load net {regs.regs(0).sva(83)} -attr vt d
+load net {regs.regs(0).sva(84)} -attr vt d
+load net {regs.regs(0).sva(85)} -attr vt d
+load net {regs.regs(0).sva(86)} -attr vt d
+load net {regs.regs(0).sva(87)} -attr vt d
+load net {regs.regs(0).sva(88)} -attr vt d
+load net {regs.regs(0).sva(89)} -attr vt d
+load netBundle {regs.regs(0).sva} 90 {regs.regs(0).sva(0)} {regs.regs(0).sva(1)} {regs.regs(0).sva(2)} {regs.regs(0).sva(3)} {regs.regs(0).sva(4)} {regs.regs(0).sva(5)} {regs.regs(0).sva(6)} {regs.regs(0).sva(7)} {regs.regs(0).sva(8)} {regs.regs(0).sva(9)} {regs.regs(0).sva(10)} {regs.regs(0).sva(11)} {regs.regs(0).sva(12)} {regs.regs(0).sva(13)} {regs.regs(0).sva(14)} {regs.regs(0).sva(15)} {regs.regs(0).sva(16)} {regs.regs(0).sva(17)} {regs.regs(0).sva(18)} {regs.regs(0).sva(19)} {regs.regs(0).sva(20)} {regs.regs(0).sva(21)} {regs.regs(0).sva(22)} {regs.regs(0).sva(23)} {regs.regs(0).sva(24)} {regs.regs(0).sva(25)} {regs.regs(0).sva(26)} {regs.regs(0).sva(27)} {regs.regs(0).sva(28)} {regs.regs(0).sva(29)} {regs.regs(0).sva(30)} {regs.regs(0).sva(31)} {regs.regs(0).sva(32)} {regs.regs(0).sva(33)} {regs.regs(0).sva(34)} {regs.regs(0).sva(35)} {regs.regs(0).sva(36)} {regs.regs(0).sva(37)} {regs.regs(0).sva(38)} {regs.regs(0).sva(39)} {regs.regs(0).sva(40)} {regs.regs(0).sva(41)} {regs.regs(0).sva(42)} {regs.regs(0).sva(43)} {regs.regs(0).sva(44)} {regs.regs(0).sva(45)} {regs.regs(0).sva(46)} {regs.regs(0).sva(47)} {regs.regs(0).sva(48)} {regs.regs(0).sva(49)} {regs.regs(0).sva(50)} {regs.regs(0).sva(51)} {regs.regs(0).sva(52)} {regs.regs(0).sva(53)} {regs.regs(0).sva(54)} {regs.regs(0).sva(55)} {regs.regs(0).sva(56)} {regs.regs(0).sva(57)} {regs.regs(0).sva(58)} {regs.regs(0).sva(59)} {regs.regs(0).sva(60)} {regs.regs(0).sva(61)} {regs.regs(0).sva(62)} {regs.regs(0).sva(63)} {regs.regs(0).sva(64)} {regs.regs(0).sva(65)} {regs.regs(0).sva(66)} {regs.regs(0).sva(67)} {regs.regs(0).sva(68)} {regs.regs(0).sva(69)} {regs.regs(0).sva(70)} {regs.regs(0).sva(71)} {regs.regs(0).sva(72)} {regs.regs(0).sva(73)} {regs.regs(0).sva(74)} {regs.regs(0).sva(75)} {regs.regs(0).sva(76)} {regs.regs(0).sva(77)} {regs.regs(0).sva(78)} {regs.regs(0).sva(79)} {regs.regs(0).sva(80)} {regs.regs(0).sva(81)} {regs.regs(0).sva(82)} {regs.regs(0).sva(83)} {regs.regs(0).sva(84)} {regs.regs(0).sva(85)} {regs.regs(0).sva(86)} {regs.regs(0).sva(87)} {regs.regs(0).sva(88)} {regs.regs(0).sva(89)} -attr xrf 24712 -attr oid 8 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {acc.imod#7.lpi#1.dfm(0)} -attr vt d
+load net {acc.imod#7.lpi#1.dfm(1)} -attr vt d
+load netBundle {acc.imod#7.lpi#1.dfm} 2 {acc.imod#7.lpi#1.dfm(0)} {acc.imod#7.lpi#1.dfm(1)} -attr xrf 24713 -attr oid 9 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(0)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(1)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(2)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(3)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(4)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(5)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(6)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(7)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(8)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(9)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(10)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(11)} -attr vt d
+load netBundle {ACC1:acc#125.psp.lpi#1.dfm} 12 {ACC1:acc#125.psp.lpi#1.dfm(0)} {ACC1:acc#125.psp.lpi#1.dfm(1)} {ACC1:acc#125.psp.lpi#1.dfm(2)} {ACC1:acc#125.psp.lpi#1.dfm(3)} {ACC1:acc#125.psp.lpi#1.dfm(4)} {ACC1:acc#125.psp.lpi#1.dfm(5)} {ACC1:acc#125.psp.lpi#1.dfm(6)} {ACC1:acc#125.psp.lpi#1.dfm(7)} {ACC1:acc#125.psp.lpi#1.dfm(8)} {ACC1:acc#125.psp.lpi#1.dfm(9)} {ACC1:acc#125.psp.lpi#1.dfm(10)} {ACC1:acc#125.psp.lpi#1.dfm(11)} -attr xrf 24714 -attr oid 10 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {acc.imod#20.lpi#1.dfm(0)} -attr vt d
+load net {acc.imod#20.lpi#1.dfm(1)} -attr vt d
+load netBundle {acc.imod#20.lpi#1.dfm} 2 {acc.imod#20.lpi#1.dfm(0)} {acc.imod#20.lpi#1.dfm(1)} -attr xrf 24715 -attr oid 11 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(0)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(1)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(2)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(3)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(4)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(5)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(6)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(7)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(8)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(9)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(10)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(11)} -attr vt d
+load netBundle {ACC1:acc#125.psp#1.lpi#1.dfm} 12 {ACC1:acc#125.psp#1.lpi#1.dfm(0)} {ACC1:acc#125.psp#1.lpi#1.dfm(1)} {ACC1:acc#125.psp#1.lpi#1.dfm(2)} {ACC1:acc#125.psp#1.lpi#1.dfm(3)} {ACC1:acc#125.psp#1.lpi#1.dfm(4)} {ACC1:acc#125.psp#1.lpi#1.dfm(5)} {ACC1:acc#125.psp#1.lpi#1.dfm(6)} {ACC1:acc#125.psp#1.lpi#1.dfm(7)} {ACC1:acc#125.psp#1.lpi#1.dfm(8)} {ACC1:acc#125.psp#1.lpi#1.dfm(9)} {ACC1:acc#125.psp#1.lpi#1.dfm(10)} {ACC1:acc#125.psp#1.lpi#1.dfm(11)} -attr xrf 24716 -attr oid 12 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {in(0).sva#1(0)} -attr vt d
+load net {in(0).sva#1(1)} -attr vt d
+load net {in(0).sva#1(2)} -attr vt d
+load net {in(0).sva#1(3)} -attr vt d
+load net {in(0).sva#1(4)} -attr vt d
+load net {in(0).sva#1(5)} -attr vt d
+load net {in(0).sva#1(6)} -attr vt d
+load net {in(0).sva#1(7)} -attr vt d
+load net {in(0).sva#1(8)} -attr vt d
+load net {in(0).sva#1(9)} -attr vt d
+load net {in(0).sva#1(10)} -attr vt d
+load net {in(0).sva#1(11)} -attr vt d
+load net {in(0).sva#1(12)} -attr vt d
+load net {in(0).sva#1(13)} -attr vt d
+load net {in(0).sva#1(14)} -attr vt d
+load net {in(0).sva#1(15)} -attr vt d
+load netBundle {in(0).sva#1} 16 {in(0).sva#1(0)} {in(0).sva#1(1)} {in(0).sva#1(2)} {in(0).sva#1(3)} {in(0).sva#1(4)} {in(0).sva#1(5)} {in(0).sva#1(6)} {in(0).sva#1(7)} {in(0).sva#1(8)} {in(0).sva#1(9)} {in(0).sva#1(10)} {in(0).sva#1(11)} {in(0).sva#1(12)} {in(0).sva#1(13)} {in(0).sva#1(14)} {in(0).sva#1(15)} -attr xrf 24717 -attr oid 13 -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(2).sva#1(0)} -attr vt d
+load net {in(2).sva#1(1)} -attr vt d
+load net {in(2).sva#1(2)} -attr vt d
+load net {in(2).sva#1(3)} -attr vt d
+load net {in(2).sva#1(4)} -attr vt d
+load net {in(2).sva#1(5)} -attr vt d
+load net {in(2).sva#1(6)} -attr vt d
+load net {in(2).sva#1(7)} -attr vt d
+load net {in(2).sva#1(8)} -attr vt d
+load net {in(2).sva#1(9)} -attr vt d
+load net {in(2).sva#1(10)} -attr vt d
+load net {in(2).sva#1(11)} -attr vt d
+load net {in(2).sva#1(12)} -attr vt d
+load net {in(2).sva#1(13)} -attr vt d
+load net {in(2).sva#1(14)} -attr vt d
+load net {in(2).sva#1(15)} -attr vt d
+load netBundle {in(2).sva#1} 16 {in(2).sva#1(0)} {in(2).sva#1(1)} {in(2).sva#1(2)} {in(2).sva#1(3)} {in(2).sva#1(4)} {in(2).sva#1(5)} {in(2).sva#1(6)} {in(2).sva#1(7)} {in(2).sva#1(8)} {in(2).sva#1(9)} {in(2).sva#1(10)} {in(2).sva#1(11)} {in(2).sva#1(12)} {in(2).sva#1(13)} {in(2).sva#1(14)} {in(2).sva#1(15)} -attr xrf 24718 -attr oid 14 -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {i#6.sva#1(0)} -attr vt d
+load net {i#6.sva#1(1)} -attr vt d
+load netBundle {i#6.sva#1} 2 {i#6.sva#1(0)} {i#6.sva#1(1)} -attr xrf 24719 -attr oid 15 -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {FRAME:for:acc#24.itm#1(0)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(1)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(2)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(3)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(4)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(5)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(6)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(7)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(8)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(9)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(10)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(11)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(12)} -attr vt d
+load netBundle {FRAME:for:acc#24.itm#1} 13 {FRAME:for:acc#24.itm#1(0)} {FRAME:for:acc#24.itm#1(1)} {FRAME:for:acc#24.itm#1(2)} {FRAME:for:acc#24.itm#1(3)} {FRAME:for:acc#24.itm#1(4)} {FRAME:for:acc#24.itm#1(5)} {FRAME:for:acc#24.itm#1(6)} {FRAME:for:acc#24.itm#1(7)} {FRAME:for:acc#24.itm#1(8)} {FRAME:for:acc#24.itm#1(9)} {FRAME:for:acc#24.itm#1(10)} {FRAME:for:acc#24.itm#1(11)} {FRAME:for:acc#24.itm#1(12)} -attr xrf 24720 -attr oid 16 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(0)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(1)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(2)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(3)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(4)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(5)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(6)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(7)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(8)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(9)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(10)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -attr vt d
+load netBundle {FRAME:for:slc(in(0).sva).itm#1} 12 {FRAME:for:slc(in(0).sva).itm#1(0)} {FRAME:for:slc(in(0).sva).itm#1(1)} {FRAME:for:slc(in(0).sva).itm#1(2)} {FRAME:for:slc(in(0).sva).itm#1(3)} {FRAME:for:slc(in(0).sva).itm#1(4)} {FRAME:for:slc(in(0).sva).itm#1(5)} {FRAME:for:slc(in(0).sva).itm#1(6)} {FRAME:for:slc(in(0).sva).itm#1(7)} {FRAME:for:slc(in(0).sva).itm#1(8)} {FRAME:for:slc(in(0).sva).itm#1(9)} {FRAME:for:slc(in(0).sva).itm#1(10)} {FRAME:for:slc(in(0).sva).itm#1(11)} -attr xrf 24721 -attr oid 17 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:acc#26.itm#1(0)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(1)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(2)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(3)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(4)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(5)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(6)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(7)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(8)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(9)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(10)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(11)} -attr vt d
+load netBundle {FRAME:for:acc#26.itm#1} 12 {FRAME:for:acc#26.itm#1(0)} {FRAME:for:acc#26.itm#1(1)} {FRAME:for:acc#26.itm#1(2)} {FRAME:for:acc#26.itm#1(3)} {FRAME:for:acc#26.itm#1(4)} {FRAME:for:acc#26.itm#1(5)} {FRAME:for:acc#26.itm#1(6)} {FRAME:for:acc#26.itm#1(7)} {FRAME:for:acc#26.itm#1(8)} {FRAME:for:acc#26.itm#1(9)} {FRAME:for:acc#26.itm#1(10)} {FRAME:for:acc#26.itm#1(11)} -attr xrf 24722 -attr oid 18 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(0)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(1)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(2)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(3)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(4)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(5)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(6)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(7)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(8)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(9)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(10)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -attr vt d
+load netBundle {FRAME:for:slc(in(2).sva).itm#1} 12 {FRAME:for:slc(in(2).sva).itm#1(0)} {FRAME:for:slc(in(2).sva).itm#1(1)} {FRAME:for:slc(in(2).sva).itm#1(2)} {FRAME:for:slc(in(2).sva).itm#1(3)} {FRAME:for:slc(in(2).sva).itm#1(4)} {FRAME:for:slc(in(2).sva).itm#1(5)} {FRAME:for:slc(in(2).sva).itm#1(6)} {FRAME:for:slc(in(2).sva).itm#1(7)} {FRAME:for:slc(in(2).sva).itm#1(8)} {FRAME:for:slc(in(2).sva).itm#1(9)} {FRAME:for:slc(in(2).sva).itm#1(10)} {FRAME:for:slc(in(2).sva).itm#1(11)} -attr xrf 24723 -attr oid 19 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {ACC1:acc#341.itm#1(0)} -attr vt d
+load net {ACC1:acc#341.itm#1(1)} -attr vt d
+load net {ACC1:acc#341.itm#1(2)} -attr vt d
+load net {ACC1:acc#341.itm#1(3)} -attr vt d
+load net {ACC1:acc#341.itm#1(4)} -attr vt d
+load net {ACC1:acc#341.itm#1(5)} -attr vt d
+load net {ACC1:acc#341.itm#1(6)} -attr vt d
+load net {ACC1:acc#341.itm#1(7)} -attr vt d
+load net {ACC1:acc#341.itm#1(8)} -attr vt d
+load net {ACC1:acc#341.itm#1(9)} -attr vt d
+load net {ACC1:acc#341.itm#1(10)} -attr vt d
+load net {ACC1:acc#341.itm#1(11)} -attr vt d
+load net {ACC1:acc#341.itm#1(12)} -attr vt d
+load netBundle {ACC1:acc#341.itm#1} 13 {ACC1:acc#341.itm#1(0)} {ACC1:acc#341.itm#1(1)} {ACC1:acc#341.itm#1(2)} {ACC1:acc#341.itm#1(3)} {ACC1:acc#341.itm#1(4)} {ACC1:acc#341.itm#1(5)} {ACC1:acc#341.itm#1(6)} {ACC1:acc#341.itm#1(7)} {ACC1:acc#341.itm#1(8)} {ACC1:acc#341.itm#1(9)} {ACC1:acc#341.itm#1(10)} {ACC1:acc#341.itm#1(11)} {ACC1:acc#341.itm#1(12)} -attr xrf 24724 -attr oid 20 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {acc.imod#6.lpi#1.dfm.sg1(0)} -attr vt d
+load net {acc.imod#6.lpi#1.dfm.sg1(1)} -attr vt d
+load netBundle {acc.imod#6.lpi#1.dfm.sg1} 2 {acc.imod#6.lpi#1.dfm.sg1(0)} {acc.imod#6.lpi#1.dfm.sg1(1)} -attr xrf 24725 -attr oid 21 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1}
+load net {regs.regs(2).lpi#1.dfm.sg2(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(29)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm.sg2} 30 {regs.regs(2).lpi#1.dfm.sg2(0)} {regs.regs(2).lpi#1.dfm.sg2(1)} {regs.regs(2).lpi#1.dfm.sg2(2)} {regs.regs(2).lpi#1.dfm.sg2(3)} {regs.regs(2).lpi#1.dfm.sg2(4)} {regs.regs(2).lpi#1.dfm.sg2(5)} {regs.regs(2).lpi#1.dfm.sg2(6)} {regs.regs(2).lpi#1.dfm.sg2(7)} {regs.regs(2).lpi#1.dfm.sg2(8)} {regs.regs(2).lpi#1.dfm.sg2(9)} {regs.regs(2).lpi#1.dfm.sg2(10)} {regs.regs(2).lpi#1.dfm.sg2(11)} {regs.regs(2).lpi#1.dfm.sg2(12)} {regs.regs(2).lpi#1.dfm.sg2(13)} {regs.regs(2).lpi#1.dfm.sg2(14)} {regs.regs(2).lpi#1.dfm.sg2(15)} {regs.regs(2).lpi#1.dfm.sg2(16)} {regs.regs(2).lpi#1.dfm.sg2(17)} {regs.regs(2).lpi#1.dfm.sg2(18)} {regs.regs(2).lpi#1.dfm.sg2(19)} {regs.regs(2).lpi#1.dfm.sg2(20)} {regs.regs(2).lpi#1.dfm.sg2(21)} {regs.regs(2).lpi#1.dfm.sg2(22)} {regs.regs(2).lpi#1.dfm.sg2(23)} {regs.regs(2).lpi#1.dfm.sg2(24)} {regs.regs(2).lpi#1.dfm.sg2(25)} {regs.regs(2).lpi#1.dfm.sg2(26)} {regs.regs(2).lpi#1.dfm.sg2(27)} {regs.regs(2).lpi#1.dfm.sg2(28)} {regs.regs(2).lpi#1.dfm.sg2(29)} -attr xrf 24726 -attr oid 22 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm#1(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(29)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm#1} 30 {regs.regs(2).lpi#1.dfm#1(0)} {regs.regs(2).lpi#1.dfm#1(1)} {regs.regs(2).lpi#1.dfm#1(2)} {regs.regs(2).lpi#1.dfm#1(3)} {regs.regs(2).lpi#1.dfm#1(4)} {regs.regs(2).lpi#1.dfm#1(5)} {regs.regs(2).lpi#1.dfm#1(6)} {regs.regs(2).lpi#1.dfm#1(7)} {regs.regs(2).lpi#1.dfm#1(8)} {regs.regs(2).lpi#1.dfm#1(9)} {regs.regs(2).lpi#1.dfm#1(10)} {regs.regs(2).lpi#1.dfm#1(11)} {regs.regs(2).lpi#1.dfm#1(12)} {regs.regs(2).lpi#1.dfm#1(13)} {regs.regs(2).lpi#1.dfm#1(14)} {regs.regs(2).lpi#1.dfm#1(15)} {regs.regs(2).lpi#1.dfm#1(16)} {regs.regs(2).lpi#1.dfm#1(17)} {regs.regs(2).lpi#1.dfm#1(18)} {regs.regs(2).lpi#1.dfm#1(19)} {regs.regs(2).lpi#1.dfm#1(20)} {regs.regs(2).lpi#1.dfm#1(21)} {regs.regs(2).lpi#1.dfm#1(22)} {regs.regs(2).lpi#1.dfm#1(23)} {regs.regs(2).lpi#1.dfm#1(24)} {regs.regs(2).lpi#1.dfm#1(25)} {regs.regs(2).lpi#1.dfm#1(26)} {regs.regs(2).lpi#1.dfm#1(27)} {regs.regs(2).lpi#1.dfm#1(28)} {regs.regs(2).lpi#1.dfm#1(29)} -attr xrf 24727 -attr oid 23 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1(0)} -attr vt d
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1(1)} -attr vt d
+load netBundle {ACC1:acc#118.psp.lpi#1.dfm.sg1} 2 {ACC1:acc#118.psp.lpi#1.dfm.sg1(0)} {ACC1:acc#118.psp.lpi#1.dfm.sg1(1)} -attr xrf 24728 -attr oid 24 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(0)} -attr vt d
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(1)} -attr vt d
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(2)} -attr vt d
+load netBundle {ACC1:acc#110.psp#1.lpi#1.dfm.sg1} 3 {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(0)} {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(1)} {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(2)} -attr xrf 24729 -attr oid 25 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load net {acc.imod#18.lpi#1.dfm.sg1(0)} -attr vt d
+load net {acc.imod#18.lpi#1.dfm.sg1(1)} -attr vt d
+load netBundle {acc.imod#18.lpi#1.dfm.sg1} 2 {acc.imod#18.lpi#1.dfm.sg1(0)} {acc.imod#18.lpi#1.dfm.sg1(1)} -attr xrf 24730 -attr oid 26 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(0)} -attr vt d
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(1)} -attr vt d
+load netBundle {ACC1:acc#118.psp#1.lpi#1.dfm.sg1} 2 {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(0)} {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(1)} -attr xrf 24731 -attr oid 27 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(0)} -attr vt d
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(1)} -attr vt d
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(2)} -attr vt d
+load netBundle {ACC1:acc#110.psp#2.lpi#1.dfm.sg1} 3 {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(0)} {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(1)} {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(2)} -attr xrf 24732 -attr oid 28 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load net {FRAME:p#1.sva#1(0)} -attr vt d
+load net {FRAME:p#1.sva#1(1)} -attr vt d
+load net {FRAME:p#1.sva#1(2)} -attr vt d
+load net {FRAME:p#1.sva#1(3)} -attr vt d
+load net {FRAME:p#1.sva#1(4)} -attr vt d
+load net {FRAME:p#1.sva#1(5)} -attr vt d
+load net {FRAME:p#1.sva#1(6)} -attr vt d
+load net {FRAME:p#1.sva#1(7)} -attr vt d
+load net {FRAME:p#1.sva#1(8)} -attr vt d
+load net {FRAME:p#1.sva#1(9)} -attr vt d
+load net {FRAME:p#1.sva#1(10)} -attr vt d
+load net {FRAME:p#1.sva#1(11)} -attr vt d
+load net {FRAME:p#1.sva#1(12)} -attr vt d
+load net {FRAME:p#1.sva#1(13)} -attr vt d
+load net {FRAME:p#1.sva#1(14)} -attr vt d
+load net {FRAME:p#1.sva#1(15)} -attr vt d
+load net {FRAME:p#1.sva#1(16)} -attr vt d
+load net {FRAME:p#1.sva#1(17)} -attr vt d
+load net {FRAME:p#1.sva#1(18)} -attr vt d
+load netBundle {FRAME:p#1.sva#1} 19 {FRAME:p#1.sva#1(0)} {FRAME:p#1.sva#1(1)} {FRAME:p#1.sva#1(2)} {FRAME:p#1.sva#1(3)} {FRAME:p#1.sva#1(4)} {FRAME:p#1.sva#1(5)} {FRAME:p#1.sva#1(6)} {FRAME:p#1.sva#1(7)} {FRAME:p#1.sva#1(8)} {FRAME:p#1.sva#1(9)} {FRAME:p#1.sva#1(10)} {FRAME:p#1.sva#1(11)} {FRAME:p#1.sva#1(12)} {FRAME:p#1.sva#1(13)} {FRAME:p#1.sva#1(14)} {FRAME:p#1.sva#1(15)} {FRAME:p#1.sva#1(16)} {FRAME:p#1.sva#1(17)} {FRAME:p#1.sva#1(18)} -attr xrf 24733 -attr oid 29 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:acc#2.psp.sva(0)} -attr vt d
+load net {FRAME:acc#2.psp.sva(1)} -attr vt d
+load net {FRAME:acc#2.psp.sva(2)} -attr vt d
+load net {FRAME:acc#2.psp.sva(3)} -attr vt d
+load net {FRAME:acc#2.psp.sva(4)} -attr vt d
+load net {FRAME:acc#2.psp.sva(5)} -attr vt d
+load net {FRAME:acc#2.psp.sva(6)} -attr vt d
+load net {FRAME:acc#2.psp.sva(7)} -attr vt d
+load net {FRAME:acc#2.psp.sva(8)} -attr vt d
+load net {FRAME:acc#2.psp.sva(9)} -attr vt d
+load net {FRAME:acc#2.psp.sva(10)} -attr vt d
+load net {FRAME:acc#2.psp.sva(11)} -attr vt d
+load netBundle {FRAME:acc#2.psp.sva} 12 {FRAME:acc#2.psp.sva(0)} {FRAME:acc#2.psp.sva(1)} {FRAME:acc#2.psp.sva(2)} {FRAME:acc#2.psp.sva(3)} {FRAME:acc#2.psp.sva(4)} {FRAME:acc#2.psp.sva(5)} {FRAME:acc#2.psp.sva(6)} {FRAME:acc#2.psp.sva(7)} {FRAME:acc#2.psp.sva(8)} {FRAME:acc#2.psp.sva(9)} {FRAME:acc#2.psp.sva(10)} {FRAME:acc#2.psp.sva(11)} -attr xrf 24734 -attr oid 30 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {intensity#2.sg1.sva(0)} -attr vt d
+load net {intensity#2.sg1.sva(1)} -attr vt d
+load net {intensity#2.sg1.sva(2)} -attr vt d
+load net {intensity#2.sg1.sva(3)} -attr vt d
+load net {intensity#2.sg1.sva(4)} -attr vt d
+load net {intensity#2.sg1.sva(5)} -attr vt d
+load net {intensity#2.sg1.sva(6)} -attr vt d
+load net {intensity#2.sg1.sva(7)} -attr vt d
+load net {intensity#2.sg1.sva(8)} -attr vt d
+load net {intensity#2.sg1.sva(9)} -attr vt d
+load net {intensity#2.sg1.sva(10)} -attr vt d
+load net {intensity#2.sg1.sva(11)} -attr vt d
+load net {intensity#2.sg1.sva(12)} -attr vt d
+load net {intensity#2.sg1.sva(13)} -attr vt d
+load net {intensity#2.sg1.sva(14)} -attr vt d
+load netBundle {intensity#2.sg1.sva} 15 {intensity#2.sg1.sva(0)} {intensity#2.sg1.sva(1)} {intensity#2.sg1.sva(2)} {intensity#2.sg1.sva(3)} {intensity#2.sg1.sva(4)} {intensity#2.sg1.sva(5)} {intensity#2.sg1.sva(6)} {intensity#2.sg1.sva(7)} {intensity#2.sg1.sva(8)} {intensity#2.sg1.sva(9)} {intensity#2.sg1.sva(10)} {intensity#2.sg1.sva(11)} {intensity#2.sg1.sva(12)} {intensity#2.sg1.sva(13)} {intensity#2.sg1.sva(14)} -attr xrf 24735 -attr oid 31 -attr vt d -attr @path {/sobel/sobel:core/intensity#2.sg1.sva}
+load net {acc.imod#12.sva(0)} -attr vt d
+load net {acc.imod#12.sva(1)} -attr vt d
+load net {acc.imod#12.sva(2)} -attr vt d
+load net {acc.imod#12.sva(3)} -attr vt d
+load net {acc.imod#12.sva(4)} -attr vt d
+load net {acc.imod#12.sva(5)} -attr vt d
+load netBundle {acc.imod#12.sva} 6 {acc.imod#12.sva(0)} {acc.imod#12.sva(1)} {acc.imod#12.sva(2)} {acc.imod#12.sva(3)} {acc.imod#12.sva(4)} {acc.imod#12.sva(5)} -attr xrf 24736 -attr oid 32 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load net {in(2).sva#3(0)} -attr vt d
+load net {in(2).sva#3(1)} -attr vt d
+load net {in(2).sva#3(2)} -attr vt d
+load net {in(2).sva#3(3)} -attr vt d
+load net {in(2).sva#3(4)} -attr vt d
+load net {in(2).sva#3(5)} -attr vt d
+load net {in(2).sva#3(6)} -attr vt d
+load net {in(2).sva#3(7)} -attr vt d
+load net {in(2).sva#3(8)} -attr vt d
+load net {in(2).sva#3(9)} -attr vt d
+load net {in(2).sva#3(10)} -attr vt d
+load net {in(2).sva#3(11)} -attr vt d
+load net {in(2).sva#3(12)} -attr vt d
+load net {in(2).sva#3(13)} -attr vt d
+load net {in(2).sva#3(14)} -attr vt d
+load net {in(2).sva#3(15)} -attr vt d
+load netBundle {in(2).sva#3} 16 {in(2).sva#3(0)} {in(2).sva#3(1)} {in(2).sva#3(2)} {in(2).sva#3(3)} {in(2).sva#3(4)} {in(2).sva#3(5)} {in(2).sva#3(6)} {in(2).sva#3(7)} {in(2).sva#3(8)} {in(2).sva#3(9)} {in(2).sva#3(10)} {in(2).sva#3(11)} {in(2).sva#3(12)} {in(2).sva#3(13)} {in(2).sva#3(14)} {in(2).sva#3(15)} -attr xrf 24737 -attr oid 33 -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(0).sva#3(0)} -attr vt d
+load net {in(0).sva#3(1)} -attr vt d
+load net {in(0).sva#3(2)} -attr vt d
+load net {in(0).sva#3(3)} -attr vt d
+load net {in(0).sva#3(4)} -attr vt d
+load net {in(0).sva#3(5)} -attr vt d
+load net {in(0).sva#3(6)} -attr vt d
+load net {in(0).sva#3(7)} -attr vt d
+load net {in(0).sva#3(8)} -attr vt d
+load net {in(0).sva#3(9)} -attr vt d
+load net {in(0).sva#3(10)} -attr vt d
+load net {in(0).sva#3(11)} -attr vt d
+load net {in(0).sva#3(12)} -attr vt d
+load net {in(0).sva#3(13)} -attr vt d
+load net {in(0).sva#3(14)} -attr vt d
+load net {in(0).sva#3(15)} -attr vt d
+load netBundle {in(0).sva#3} 16 {in(0).sva#3(0)} {in(0).sva#3(1)} {in(0).sva#3(2)} {in(0).sva#3(3)} {in(0).sva#3(4)} {in(0).sva#3(5)} {in(0).sva#3(6)} {in(0).sva#3(7)} {in(0).sva#3(8)} {in(0).sva#3(9)} {in(0).sva#3(10)} {in(0).sva#3(11)} {in(0).sva#3(12)} {in(0).sva#3(13)} {in(0).sva#3(14)} {in(0).sva#3(15)} -attr xrf 24738 -attr oid 34 -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {i#6.sva#2(0)} -attr vt d
+load net {i#6.sva#2(1)} -attr vt d
+load netBundle {i#6.sva#2} 2 {i#6.sva#2(0)} {i#6.sva#2(1)} -attr xrf 24739 -attr oid 35 -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.lpi#1.dfm(0)} -attr vt d
+load net {i#6.lpi#1.dfm(1)} -attr vt d
+load netBundle {i#6.lpi#1.dfm} 2 {i#6.lpi#1.dfm(0)} {i#6.lpi#1.dfm(1)} -attr xrf 24740 -attr oid 36 -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(0)} -attr vt d
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(1)} -attr vt d
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(2)} -attr vt d
+load netBundle {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0} 3 {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(0)} {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(1)} {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(2)} -attr xrf 24741 -attr oid 37 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(0)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(1)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(2)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(3)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(5)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(7)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(9)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -attr vt d
+load netBundle {ACC1:acc#125.psp.lpi#1.dfm:mx0} 12 {ACC1:acc#125.psp.lpi#1.dfm:mx0(0)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(1)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(2)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(3)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(5)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(7)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(9)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -attr xrf 24742 -attr oid 38 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(0)} -attr vt d
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(1)} -attr vt d
+load netBundle {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0} 2 {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(0)} {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(1)} -attr xrf 24743 -attr oid 39 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(29)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm.sg2:mx0} 30 {regs.regs(2).lpi#1.dfm.sg2:mx0(0)} {regs.regs(2).lpi#1.dfm.sg2:mx0(1)} {regs.regs(2).lpi#1.dfm.sg2:mx0(2)} {regs.regs(2).lpi#1.dfm.sg2:mx0(3)} {regs.regs(2).lpi#1.dfm.sg2:mx0(4)} {regs.regs(2).lpi#1.dfm.sg2:mx0(5)} {regs.regs(2).lpi#1.dfm.sg2:mx0(6)} {regs.regs(2).lpi#1.dfm.sg2:mx0(7)} {regs.regs(2).lpi#1.dfm.sg2:mx0(8)} {regs.regs(2).lpi#1.dfm.sg2:mx0(9)} {regs.regs(2).lpi#1.dfm.sg2:mx0(10)} {regs.regs(2).lpi#1.dfm.sg2:mx0(11)} {regs.regs(2).lpi#1.dfm.sg2:mx0(12)} {regs.regs(2).lpi#1.dfm.sg2:mx0(13)} {regs.regs(2).lpi#1.dfm.sg2:mx0(14)} {regs.regs(2).lpi#1.dfm.sg2:mx0(15)} {regs.regs(2).lpi#1.dfm.sg2:mx0(16)} {regs.regs(2).lpi#1.dfm.sg2:mx0(17)} {regs.regs(2).lpi#1.dfm.sg2:mx0(18)} {regs.regs(2).lpi#1.dfm.sg2:mx0(19)} {regs.regs(2).lpi#1.dfm.sg2:mx0(20)} {regs.regs(2).lpi#1.dfm.sg2:mx0(21)} {regs.regs(2).lpi#1.dfm.sg2:mx0(22)} {regs.regs(2).lpi#1.dfm.sg2:mx0(23)} {regs.regs(2).lpi#1.dfm.sg2:mx0(24)} {regs.regs(2).lpi#1.dfm.sg2:mx0(25)} {regs.regs(2).lpi#1.dfm.sg2:mx0(26)} {regs.regs(2).lpi#1.dfm.sg2:mx0(27)} {regs.regs(2).lpi#1.dfm.sg2:mx0(28)} {regs.regs(2).lpi#1.dfm.sg2:mx0(29)} -attr xrf 24744 -attr oid 40 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(29)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm#1:mx0} 30 {regs.regs(2).lpi#1.dfm#1:mx0(0)} {regs.regs(2).lpi#1.dfm#1:mx0(1)} {regs.regs(2).lpi#1.dfm#1:mx0(2)} {regs.regs(2).lpi#1.dfm#1:mx0(3)} {regs.regs(2).lpi#1.dfm#1:mx0(4)} {regs.regs(2).lpi#1.dfm#1:mx0(5)} {regs.regs(2).lpi#1.dfm#1:mx0(6)} {regs.regs(2).lpi#1.dfm#1:mx0(7)} {regs.regs(2).lpi#1.dfm#1:mx0(8)} {regs.regs(2).lpi#1.dfm#1:mx0(9)} {regs.regs(2).lpi#1.dfm#1:mx0(10)} {regs.regs(2).lpi#1.dfm#1:mx0(11)} {regs.regs(2).lpi#1.dfm#1:mx0(12)} {regs.regs(2).lpi#1.dfm#1:mx0(13)} {regs.regs(2).lpi#1.dfm#1:mx0(14)} {regs.regs(2).lpi#1.dfm#1:mx0(15)} {regs.regs(2).lpi#1.dfm#1:mx0(16)} {regs.regs(2).lpi#1.dfm#1:mx0(17)} {regs.regs(2).lpi#1.dfm#1:mx0(18)} {regs.regs(2).lpi#1.dfm#1:mx0(19)} {regs.regs(2).lpi#1.dfm#1:mx0(20)} {regs.regs(2).lpi#1.dfm#1:mx0(21)} {regs.regs(2).lpi#1.dfm#1:mx0(22)} {regs.regs(2).lpi#1.dfm#1:mx0(23)} {regs.regs(2).lpi#1.dfm#1:mx0(24)} {regs.regs(2).lpi#1.dfm#1:mx0(25)} {regs.regs(2).lpi#1.dfm#1:mx0(26)} {regs.regs(2).lpi#1.dfm#1:mx0(27)} {regs.regs(2).lpi#1.dfm#1:mx0(28)} {regs.regs(2).lpi#1.dfm#1:mx0(29)} -attr xrf 24745 -attr oid 41 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(1).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(1).sva.dfm:mx0} 90 {regs.regs(1).sva.dfm:mx0(0)} {regs.regs(1).sva.dfm:mx0(1)} {regs.regs(1).sva.dfm:mx0(2)} {regs.regs(1).sva.dfm:mx0(3)} {regs.regs(1).sva.dfm:mx0(4)} {regs.regs(1).sva.dfm:mx0(5)} {regs.regs(1).sva.dfm:mx0(6)} {regs.regs(1).sva.dfm:mx0(7)} {regs.regs(1).sva.dfm:mx0(8)} {regs.regs(1).sva.dfm:mx0(9)} {regs.regs(1).sva.dfm:mx0(10)} {regs.regs(1).sva.dfm:mx0(11)} {regs.regs(1).sva.dfm:mx0(12)} {regs.regs(1).sva.dfm:mx0(13)} {regs.regs(1).sva.dfm:mx0(14)} {regs.regs(1).sva.dfm:mx0(15)} {regs.regs(1).sva.dfm:mx0(16)} {regs.regs(1).sva.dfm:mx0(17)} {regs.regs(1).sva.dfm:mx0(18)} {regs.regs(1).sva.dfm:mx0(19)} {regs.regs(1).sva.dfm:mx0(20)} {regs.regs(1).sva.dfm:mx0(21)} {regs.regs(1).sva.dfm:mx0(22)} {regs.regs(1).sva.dfm:mx0(23)} {regs.regs(1).sva.dfm:mx0(24)} {regs.regs(1).sva.dfm:mx0(25)} {regs.regs(1).sva.dfm:mx0(26)} {regs.regs(1).sva.dfm:mx0(27)} {regs.regs(1).sva.dfm:mx0(28)} {regs.regs(1).sva.dfm:mx0(29)} {regs.regs(1).sva.dfm:mx0(30)} {regs.regs(1).sva.dfm:mx0(31)} {regs.regs(1).sva.dfm:mx0(32)} {regs.regs(1).sva.dfm:mx0(33)} {regs.regs(1).sva.dfm:mx0(34)} {regs.regs(1).sva.dfm:mx0(35)} {regs.regs(1).sva.dfm:mx0(36)} {regs.regs(1).sva.dfm:mx0(37)} {regs.regs(1).sva.dfm:mx0(38)} {regs.regs(1).sva.dfm:mx0(39)} {regs.regs(1).sva.dfm:mx0(40)} {regs.regs(1).sva.dfm:mx0(41)} {regs.regs(1).sva.dfm:mx0(42)} {regs.regs(1).sva.dfm:mx0(43)} {regs.regs(1).sva.dfm:mx0(44)} {regs.regs(1).sva.dfm:mx0(45)} {regs.regs(1).sva.dfm:mx0(46)} {regs.regs(1).sva.dfm:mx0(47)} {regs.regs(1).sva.dfm:mx0(48)} {regs.regs(1).sva.dfm:mx0(49)} {regs.regs(1).sva.dfm:mx0(50)} {regs.regs(1).sva.dfm:mx0(51)} {regs.regs(1).sva.dfm:mx0(52)} {regs.regs(1).sva.dfm:mx0(53)} {regs.regs(1).sva.dfm:mx0(54)} {regs.regs(1).sva.dfm:mx0(55)} {regs.regs(1).sva.dfm:mx0(56)} {regs.regs(1).sva.dfm:mx0(57)} {regs.regs(1).sva.dfm:mx0(58)} {regs.regs(1).sva.dfm:mx0(59)} {regs.regs(1).sva.dfm:mx0(60)} {regs.regs(1).sva.dfm:mx0(61)} {regs.regs(1).sva.dfm:mx0(62)} {regs.regs(1).sva.dfm:mx0(63)} {regs.regs(1).sva.dfm:mx0(64)} {regs.regs(1).sva.dfm:mx0(65)} {regs.regs(1).sva.dfm:mx0(66)} {regs.regs(1).sva.dfm:mx0(67)} {regs.regs(1).sva.dfm:mx0(68)} {regs.regs(1).sva.dfm:mx0(69)} {regs.regs(1).sva.dfm:mx0(70)} {regs.regs(1).sva.dfm:mx0(71)} {regs.regs(1).sva.dfm:mx0(72)} {regs.regs(1).sva.dfm:mx0(73)} {regs.regs(1).sva.dfm:mx0(74)} {regs.regs(1).sva.dfm:mx0(75)} {regs.regs(1).sva.dfm:mx0(76)} {regs.regs(1).sva.dfm:mx0(77)} {regs.regs(1).sva.dfm:mx0(78)} {regs.regs(1).sva.dfm:mx0(79)} {regs.regs(1).sva.dfm:mx0(80)} {regs.regs(1).sva.dfm:mx0(81)} {regs.regs(1).sva.dfm:mx0(82)} {regs.regs(1).sva.dfm:mx0(83)} {regs.regs(1).sva.dfm:mx0(84)} {regs.regs(1).sva.dfm:mx0(85)} {regs.regs(1).sva.dfm:mx0(86)} {regs.regs(1).sva.dfm:mx0(87)} {regs.regs(1).sva.dfm:mx0(88)} {regs.regs(1).sva.dfm:mx0(89)} -attr xrf 24746 -attr oid 42 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(0).sva.dfm:mx0} 90 {regs.regs(0).sva.dfm:mx0(0)} {regs.regs(0).sva.dfm:mx0(1)} {regs.regs(0).sva.dfm:mx0(2)} {regs.regs(0).sva.dfm:mx0(3)} {regs.regs(0).sva.dfm:mx0(4)} {regs.regs(0).sva.dfm:mx0(5)} {regs.regs(0).sva.dfm:mx0(6)} {regs.regs(0).sva.dfm:mx0(7)} {regs.regs(0).sva.dfm:mx0(8)} {regs.regs(0).sva.dfm:mx0(9)} {regs.regs(0).sva.dfm:mx0(10)} {regs.regs(0).sva.dfm:mx0(11)} {regs.regs(0).sva.dfm:mx0(12)} {regs.regs(0).sva.dfm:mx0(13)} {regs.regs(0).sva.dfm:mx0(14)} {regs.regs(0).sva.dfm:mx0(15)} {regs.regs(0).sva.dfm:mx0(16)} {regs.regs(0).sva.dfm:mx0(17)} {regs.regs(0).sva.dfm:mx0(18)} {regs.regs(0).sva.dfm:mx0(19)} {regs.regs(0).sva.dfm:mx0(20)} {regs.regs(0).sva.dfm:mx0(21)} {regs.regs(0).sva.dfm:mx0(22)} {regs.regs(0).sva.dfm:mx0(23)} {regs.regs(0).sva.dfm:mx0(24)} {regs.regs(0).sva.dfm:mx0(25)} {regs.regs(0).sva.dfm:mx0(26)} {regs.regs(0).sva.dfm:mx0(27)} {regs.regs(0).sva.dfm:mx0(28)} {regs.regs(0).sva.dfm:mx0(29)} {regs.regs(0).sva.dfm:mx0(30)} {regs.regs(0).sva.dfm:mx0(31)} {regs.regs(0).sva.dfm:mx0(32)} {regs.regs(0).sva.dfm:mx0(33)} {regs.regs(0).sva.dfm:mx0(34)} {regs.regs(0).sva.dfm:mx0(35)} {regs.regs(0).sva.dfm:mx0(36)} {regs.regs(0).sva.dfm:mx0(37)} {regs.regs(0).sva.dfm:mx0(38)} {regs.regs(0).sva.dfm:mx0(39)} {regs.regs(0).sva.dfm:mx0(40)} {regs.regs(0).sva.dfm:mx0(41)} {regs.regs(0).sva.dfm:mx0(42)} {regs.regs(0).sva.dfm:mx0(43)} {regs.regs(0).sva.dfm:mx0(44)} {regs.regs(0).sva.dfm:mx0(45)} {regs.regs(0).sva.dfm:mx0(46)} {regs.regs(0).sva.dfm:mx0(47)} {regs.regs(0).sva.dfm:mx0(48)} {regs.regs(0).sva.dfm:mx0(49)} {regs.regs(0).sva.dfm:mx0(50)} {regs.regs(0).sva.dfm:mx0(51)} {regs.regs(0).sva.dfm:mx0(52)} {regs.regs(0).sva.dfm:mx0(53)} {regs.regs(0).sva.dfm:mx0(54)} {regs.regs(0).sva.dfm:mx0(55)} {regs.regs(0).sva.dfm:mx0(56)} {regs.regs(0).sva.dfm:mx0(57)} {regs.regs(0).sva.dfm:mx0(58)} {regs.regs(0).sva.dfm:mx0(59)} {regs.regs(0).sva.dfm:mx0(60)} {regs.regs(0).sva.dfm:mx0(61)} {regs.regs(0).sva.dfm:mx0(62)} {regs.regs(0).sva.dfm:mx0(63)} {regs.regs(0).sva.dfm:mx0(64)} {regs.regs(0).sva.dfm:mx0(65)} {regs.regs(0).sva.dfm:mx0(66)} {regs.regs(0).sva.dfm:mx0(67)} {regs.regs(0).sva.dfm:mx0(68)} {regs.regs(0).sva.dfm:mx0(69)} {regs.regs(0).sva.dfm:mx0(70)} {regs.regs(0).sva.dfm:mx0(71)} {regs.regs(0).sva.dfm:mx0(72)} {regs.regs(0).sva.dfm:mx0(73)} {regs.regs(0).sva.dfm:mx0(74)} {regs.regs(0).sva.dfm:mx0(75)} {regs.regs(0).sva.dfm:mx0(76)} {regs.regs(0).sva.dfm:mx0(77)} {regs.regs(0).sva.dfm:mx0(78)} {regs.regs(0).sva.dfm:mx0(79)} {regs.regs(0).sva.dfm:mx0(80)} {regs.regs(0).sva.dfm:mx0(81)} {regs.regs(0).sva.dfm:mx0(82)} {regs.regs(0).sva.dfm:mx0(83)} {regs.regs(0).sva.dfm:mx0(84)} {regs.regs(0).sva.dfm:mx0(85)} {regs.regs(0).sva.dfm:mx0(86)} {regs.regs(0).sva.dfm:mx0(87)} {regs.regs(0).sva.dfm:mx0(88)} {regs.regs(0).sva.dfm:mx0(89)} -attr xrf 24747 -attr oid 43 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {acc.imod#7.lpi#1.dfm:mx0(0)} -attr vt d
+load net {acc.imod#7.lpi#1.dfm:mx0(1)} -attr vt d
+load netBundle {acc.imod#7.lpi#1.dfm:mx0} 2 {acc.imod#7.lpi#1.dfm:mx0(0)} {acc.imod#7.lpi#1.dfm:mx0(1)} -attr xrf 24748 -attr oid 44 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm:mx0}
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(0)} -attr vt d
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(1)} -attr vt d
+load netBundle {acc.imod#6.lpi#1.dfm.sg1:mx0} 2 {acc.imod#6.lpi#1.dfm.sg1:mx0(0)} {acc.imod#6.lpi#1.dfm.sg1:mx0(1)} -attr xrf 24749 -attr oid 45 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1:mx0}
+load net {acc.imod#18.sva(0)} -attr vt d
+load net {acc.imod#18.sva(1)} -attr vt d
+load net {acc.imod#18.sva(2)} -attr vt d
+load netBundle {acc.imod#18.sva} 3 {acc.imod#18.sva(0)} {acc.imod#18.sva(1)} {acc.imod#18.sva(2)} -attr xrf 24750 -attr oid 46 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.sva}
+load net {ACC1:acc#118.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#118.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#118.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#118.psp#1.sva} 3 {ACC1:acc#118.psp#1.sva(0)} {ACC1:acc#118.psp#1.sva(1)} {ACC1:acc#118.psp#1.sva(2)} -attr xrf 24751 -attr oid 47 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.sva}
+load net {ACC1:acc#110.psp#2.sva(0)} -attr vt d
+load net {ACC1:acc#110.psp#2.sva(1)} -attr vt d
+load net {ACC1:acc#110.psp#2.sva(2)} -attr vt d
+load net {ACC1:acc#110.psp#2.sva(3)} -attr vt d
+load netBundle {ACC1:acc#110.psp#2.sva} 4 {ACC1:acc#110.psp#2.sva(0)} {ACC1:acc#110.psp#2.sva(1)} {ACC1:acc#110.psp#2.sva(2)} {ACC1:acc#110.psp#2.sva(3)} -attr xrf 24752 -attr oid 48 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.sva}
+load net {ACC1:acc#125.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(2)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(3)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(4)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(5)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(6)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(7)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(8)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(9)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(10)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(11)} -attr vt d
+load netBundle {ACC1:acc#125.psp#1.sva} 12 {ACC1:acc#125.psp#1.sva(0)} {ACC1:acc#125.psp#1.sva(1)} {ACC1:acc#125.psp#1.sva(2)} {ACC1:acc#125.psp#1.sva(3)} {ACC1:acc#125.psp#1.sva(4)} {ACC1:acc#125.psp#1.sva(5)} {ACC1:acc#125.psp#1.sva(6)} {ACC1:acc#125.psp#1.sva(7)} {ACC1:acc#125.psp#1.sva(8)} {ACC1:acc#125.psp#1.sva(9)} {ACC1:acc#125.psp#1.sva(10)} {ACC1:acc#125.psp#1.sva(11)} -attr xrf 24753 -attr oid 49 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#110.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#110.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#110.psp#1.sva(2)} -attr vt d
+load net {ACC1:acc#110.psp#1.sva(3)} -attr vt d
+load netBundle {ACC1:acc#110.psp#1.sva} 4 {ACC1:acc#110.psp#1.sva(0)} {ACC1:acc#110.psp#1.sva(1)} {ACC1:acc#110.psp#1.sva(2)} {ACC1:acc#110.psp#1.sva(3)} -attr xrf 24754 -attr oid 50 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.sva}
+load net {ACC1:acc#125.psp.sva(0)} -attr vt d
+load net {ACC1:acc#125.psp.sva(1)} -attr vt d
+load net {ACC1:acc#125.psp.sva(2)} -attr vt d
+load net {ACC1:acc#125.psp.sva(3)} -attr vt d
+load net {ACC1:acc#125.psp.sva(4)} -attr vt d
+load net {ACC1:acc#125.psp.sva(5)} -attr vt d
+load net {ACC1:acc#125.psp.sva(6)} -attr vt d
+load net {ACC1:acc#125.psp.sva(7)} -attr vt d
+load net {ACC1:acc#125.psp.sva(8)} -attr vt d
+load net {ACC1:acc#125.psp.sva(9)} -attr vt d
+load net {ACC1:acc#125.psp.sva(10)} -attr vt d
+load net {ACC1:acc#125.psp.sva(11)} -attr vt d
+load netBundle {ACC1:acc#125.psp.sva} 12 {ACC1:acc#125.psp.sva(0)} {ACC1:acc#125.psp.sva(1)} {ACC1:acc#125.psp.sva(2)} {ACC1:acc#125.psp.sva(3)} {ACC1:acc#125.psp.sva(4)} {ACC1:acc#125.psp.sva(5)} {ACC1:acc#125.psp.sva(6)} {ACC1:acc#125.psp.sva(7)} {ACC1:acc#125.psp.sva(8)} {ACC1:acc#125.psp.sva(9)} {ACC1:acc#125.psp.sva(10)} {ACC1:acc#125.psp.sva(11)} -attr xrf 24755 -attr oid 51 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#118.psp.sva(0)} -attr vt d
+load net {ACC1:acc#118.psp.sva(1)} -attr vt d
+load net {ACC1:acc#118.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#118.psp.sva} 3 {ACC1:acc#118.psp.sva(0)} {ACC1:acc#118.psp.sva(1)} {ACC1:acc#118.psp.sva(2)} -attr xrf 24756 -attr oid 52 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.sva}
+load net {acc.imod#6.sva(0)} -attr vt d
+load net {acc.imod#6.sva(1)} -attr vt d
+load net {acc.imod#6.sva(2)} -attr vt d
+load netBundle {acc.imod#6.sva} 3 {acc.imod#6.sva(0)} {acc.imod#6.sva(1)} {acc.imod#6.sva(2)} -attr xrf 24757 -attr oid 53 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.sva}
+load net {ACC1:acc#120.psp.sva(0)} -attr vt d
+load net {ACC1:acc#120.psp.sva(1)} -attr vt d
+load net {ACC1:acc#120.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#120.psp.sva} 3 {ACC1:acc#120.psp.sva(0)} {ACC1:acc#120.psp.sva(1)} {ACC1:acc#120.psp.sva(2)} -attr xrf 24758 -attr oid 54 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#120.psp.sva}
+load net {ACC1:acc#250.cse(0)} -attr vt d
+load net {ACC1:acc#250.cse(1)} -attr vt d
+load net {ACC1:acc#250.cse(2)} -attr vt d
+load netBundle {ACC1:acc#250.cse} 3 {ACC1:acc#250.cse(0)} {ACC1:acc#250.cse(1)} {ACC1:acc#250.cse(2)} -attr xrf 24759 -attr oid 55 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#120.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#120.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#120.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#120.psp#1.sva} 3 {ACC1:acc#120.psp#1.sva(0)} {ACC1:acc#120.psp#1.sva(1)} {ACC1:acc#120.psp#1.sva(2)} -attr xrf 24760 -attr oid 56 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#120.psp#1.sva}
+load net {ACC1:acc#277.cse(0)} -attr vt d
+load net {ACC1:acc#277.cse(1)} -attr vt d
+load net {ACC1:acc#277.cse(2)} -attr vt d
+load netBundle {ACC1:acc#277.cse} 3 {ACC1:acc#277.cse(0)} {ACC1:acc#277.cse(1)} {ACC1:acc#277.cse(2)} -attr xrf 24761 -attr oid 57 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#116.psp.sva(0)} -attr vt d
+load net {ACC1:acc#116.psp.sva(1)} -attr vt d
+load net {ACC1:acc#116.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#116.psp.sva} 3 {ACC1:acc#116.psp.sva(0)} {ACC1:acc#116.psp.sva(1)} {ACC1:acc#116.psp.sva(2)} -attr xrf 24762 -attr oid 58 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp.sva}
+load net {ACC1:acc#197.cse(0)} -attr vt d
+load net {ACC1:acc#197.cse(1)} -attr vt d
+load net {ACC1:acc#197.cse(2)} -attr vt d
+load netBundle {ACC1:acc#197.cse} 3 {ACC1:acc#197.cse(0)} {ACC1:acc#197.cse(1)} {ACC1:acc#197.cse(2)} -attr xrf 24763 -attr oid 59 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#116.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#116.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#116.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#116.psp#1.sva} 3 {ACC1:acc#116.psp#1.sva(0)} {ACC1:acc#116.psp#1.sva(1)} {ACC1:acc#116.psp#1.sva(2)} -attr xrf 24764 -attr oid 60 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp#1.sva}
+load net {ACC1:acc#224.cse(0)} -attr vt d
+load net {ACC1:acc#224.cse(1)} -attr vt d
+load net {ACC1:acc#224.cse(2)} -attr vt d
+load netBundle {ACC1:acc#224.cse} 3 {ACC1:acc#224.cse(0)} {ACC1:acc#224.cse(1)} {ACC1:acc#224.cse(2)} -attr xrf 24765 -attr oid 61 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {FRAME:p#1.lpi#1.dfm(0)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(1)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(2)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(3)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(4)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(5)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(6)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(7)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(8)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(9)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(10)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(11)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(12)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(13)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(14)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(15)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(16)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(17)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(18)} -attr vt d
+load netBundle {FRAME:p#1.lpi#1.dfm} 19 {FRAME:p#1.lpi#1.dfm(0)} {FRAME:p#1.lpi#1.dfm(1)} {FRAME:p#1.lpi#1.dfm(2)} {FRAME:p#1.lpi#1.dfm(3)} {FRAME:p#1.lpi#1.dfm(4)} {FRAME:p#1.lpi#1.dfm(5)} {FRAME:p#1.lpi#1.dfm(6)} {FRAME:p#1.lpi#1.dfm(7)} {FRAME:p#1.lpi#1.dfm(8)} {FRAME:p#1.lpi#1.dfm(9)} {FRAME:p#1.lpi#1.dfm(10)} {FRAME:p#1.lpi#1.dfm(11)} {FRAME:p#1.lpi#1.dfm(12)} {FRAME:p#1.lpi#1.dfm(13)} {FRAME:p#1.lpi#1.dfm(14)} {FRAME:p#1.lpi#1.dfm(15)} {FRAME:p#1.lpi#1.dfm(16)} {FRAME:p#1.lpi#1.dfm(17)} {FRAME:p#1.lpi#1.dfm(18)} -attr xrf 24766 -attr oid 62 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(0)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(1)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(2)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(3)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(5)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(7)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(9)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -attr vt d
+load netBundle {ACC1:acc#125.psp#1.lpi#1.dfm:mx0} 12 {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(0)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(1)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(2)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(3)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(5)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(7)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(9)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -attr xrf 24767 -attr oid 63 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(0)} -attr vt d
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(1)} -attr vt d
+load netBundle {acc.imod#18.lpi#1.dfm.sg1:mx0} 2 {acc.imod#18.lpi#1.dfm.sg1:mx0(0)} {acc.imod#18.lpi#1.dfm.sg1:mx0(1)} -attr xrf 24768 -attr oid 64 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(0)} -attr vt d
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(1)} -attr vt d
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(2)} -attr vt d
+load netBundle {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0} 3 {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(0)} {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(1)} {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(2)} -attr xrf 24769 -attr oid 65 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load net {acc.imod#20.lpi#1.dfm:mx0(0)} -attr vt d
+load net {acc.imod#20.lpi#1.dfm:mx0(1)} -attr vt d
+load netBundle {acc.imod#20.lpi#1.dfm:mx0} 2 {acc.imod#20.lpi#1.dfm:mx0(0)} {acc.imod#20.lpi#1.dfm:mx0(1)} -attr xrf 24770 -attr oid 66 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm:mx0}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(0)} -attr vt d
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(1)} -attr vt d
+load netBundle {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0} 2 {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(0)} {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(1)} -attr xrf 24771 -attr oid 67 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0}
+load net {FRAME:for:conc#16(0)} -attr vt d
+load net {FRAME:for:conc#16(1)} -attr vt d
+load netBundle {FRAME:for:conc#16} 2 {FRAME:for:conc#16(0)} {FRAME:for:conc#16(1)} -attr xrf 24772 -attr oid 68 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {mux.itm(0)} -attr vt d
+load net {mux.itm(1)} -attr vt d
+load net {mux.itm(2)} -attr vt d
+load net {mux.itm(3)} -attr vt d
+load net {mux.itm(4)} -attr vt d
+load net {mux.itm(5)} -attr vt d
+load net {mux.itm(6)} -attr vt d
+load net {mux.itm(7)} -attr vt d
+load net {mux.itm(8)} -attr vt d
+load net {mux.itm(9)} -attr vt d
+load net {mux.itm(10)} -attr vt d
+load net {mux.itm(11)} -attr vt d
+load net {mux.itm(12)} -attr vt d
+load net {mux.itm(13)} -attr vt d
+load net {mux.itm(14)} -attr vt d
+load net {mux.itm(15)} -attr vt d
+load net {mux.itm(16)} -attr vt d
+load net {mux.itm(17)} -attr vt d
+load net {mux.itm(18)} -attr vt d
+load net {mux.itm(19)} -attr vt d
+load net {mux.itm(20)} -attr vt d
+load net {mux.itm(21)} -attr vt d
+load net {mux.itm(22)} -attr vt d
+load net {mux.itm(23)} -attr vt d
+load net {mux.itm(24)} -attr vt d
+load net {mux.itm(25)} -attr vt d
+load net {mux.itm(26)} -attr vt d
+load net {mux.itm(27)} -attr vt d
+load net {mux.itm(28)} -attr vt d
+load net {mux.itm(29)} -attr vt d
+load netBundle {mux.itm} 30 {mux.itm(0)} {mux.itm(1)} {mux.itm(2)} {mux.itm(3)} {mux.itm(4)} {mux.itm(5)} {mux.itm(6)} {mux.itm(7)} {mux.itm(8)} {mux.itm(9)} {mux.itm(10)} {mux.itm(11)} {mux.itm(12)} {mux.itm(13)} {mux.itm(14)} {mux.itm(15)} {mux.itm(16)} {mux.itm(17)} {mux.itm(18)} {mux.itm(19)} {mux.itm(20)} {mux.itm(21)} {mux.itm(22)} {mux.itm(23)} {mux.itm(24)} {mux.itm(25)} {mux.itm(26)} {mux.itm(27)} {mux.itm(28)} {mux.itm(29)} -attr xrf 24773 -attr oid 69 -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {FRAME:conc#11.itm(0)} -attr vt d
+load net {FRAME:conc#11.itm(1)} -attr vt d
+load net {FRAME:conc#11.itm(2)} -attr vt d
+load net {FRAME:conc#11.itm(3)} -attr vt d
+load net {FRAME:conc#11.itm(4)} -attr vt d
+load net {FRAME:conc#11.itm(5)} -attr vt d
+load net {FRAME:conc#11.itm(6)} -attr vt d
+load net {FRAME:conc#11.itm(7)} -attr vt d
+load net {FRAME:conc#11.itm(8)} -attr vt d
+load net {FRAME:conc#11.itm(9)} -attr vt d
+load net {FRAME:conc#11.itm(10)} -attr vt d
+load net {FRAME:conc#11.itm(11)} -attr vt d
+load net {FRAME:conc#11.itm(12)} -attr vt d
+load net {FRAME:conc#11.itm(13)} -attr vt d
+load net {FRAME:conc#11.itm(14)} -attr vt d
+load net {FRAME:conc#11.itm(15)} -attr vt d
+load net {FRAME:conc#11.itm(16)} -attr vt d
+load net {FRAME:conc#11.itm(17)} -attr vt d
+load net {FRAME:conc#11.itm(18)} -attr vt d
+load net {FRAME:conc#11.itm(19)} -attr vt d
+load net {FRAME:conc#11.itm(20)} -attr vt d
+load net {FRAME:conc#11.itm(21)} -attr vt d
+load net {FRAME:conc#11.itm(22)} -attr vt d
+load net {FRAME:conc#11.itm(23)} -attr vt d
+load net {FRAME:conc#11.itm(24)} -attr vt d
+load net {FRAME:conc#11.itm(25)} -attr vt d
+load net {FRAME:conc#11.itm(26)} -attr vt d
+load net {FRAME:conc#11.itm(27)} -attr vt d
+load net {FRAME:conc#11.itm(28)} -attr vt d
+load net {FRAME:conc#11.itm(29)} -attr vt d
+load netBundle {FRAME:conc#11.itm} 30 {FRAME:conc#11.itm(0)} {FRAME:conc#11.itm(1)} {FRAME:conc#11.itm(2)} {FRAME:conc#11.itm(3)} {FRAME:conc#11.itm(4)} {FRAME:conc#11.itm(5)} {FRAME:conc#11.itm(6)} {FRAME:conc#11.itm(7)} {FRAME:conc#11.itm(8)} {FRAME:conc#11.itm(9)} {FRAME:conc#11.itm(10)} {FRAME:conc#11.itm(11)} {FRAME:conc#11.itm(12)} {FRAME:conc#11.itm(13)} {FRAME:conc#11.itm(14)} {FRAME:conc#11.itm(15)} {FRAME:conc#11.itm(16)} {FRAME:conc#11.itm(17)} {FRAME:conc#11.itm(18)} {FRAME:conc#11.itm(19)} {FRAME:conc#11.itm(20)} {FRAME:conc#11.itm(21)} {FRAME:conc#11.itm(22)} {FRAME:conc#11.itm(23)} {FRAME:conc#11.itm(24)} {FRAME:conc#11.itm(25)} {FRAME:conc#11.itm(26)} {FRAME:conc#11.itm(27)} {FRAME:conc#11.itm(28)} {FRAME:conc#11.itm(29)} -attr xrf 24774 -attr oid 70 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(0)} -attr vt d
+load net {FRAME:or.itm(1)} -attr vt d
+load net {FRAME:or.itm(2)} -attr vt d
+load net {FRAME:or.itm(3)} -attr vt d
+load net {FRAME:or.itm(4)} -attr vt d
+load net {FRAME:or.itm(5)} -attr vt d
+load net {FRAME:or.itm(6)} -attr vt d
+load net {FRAME:or.itm(7)} -attr vt d
+load net {FRAME:or.itm(8)} -attr vt d
+load net {FRAME:or.itm(9)} -attr vt d
+load netBundle {FRAME:or.itm} 10 {FRAME:or.itm(0)} {FRAME:or.itm(1)} {FRAME:or.itm(2)} {FRAME:or.itm(3)} {FRAME:or.itm(4)} {FRAME:or.itm(5)} {FRAME:or.itm(6)} {FRAME:or.itm(7)} {FRAME:or.itm(8)} {FRAME:or.itm(9)} -attr xrf 24775 -attr oid 71 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(3)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(4)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(5)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(6)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(7)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(8)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(9)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#4.itm} 10 {slc(FRAME:acc#2.psp.sva)#4.itm(0)} {slc(FRAME:acc#2.psp.sva)#4.itm(1)} {slc(FRAME:acc#2.psp.sva)#4.itm(2)} {slc(FRAME:acc#2.psp.sva)#4.itm(3)} {slc(FRAME:acc#2.psp.sva)#4.itm(4)} {slc(FRAME:acc#2.psp.sva)#4.itm(5)} {slc(FRAME:acc#2.psp.sva)#4.itm(6)} {slc(FRAME:acc#2.psp.sva)#4.itm(7)} {slc(FRAME:acc#2.psp.sva)#4.itm(8)} {slc(FRAME:acc#2.psp.sva)#4.itm(9)} -attr xrf 24776 -attr oid 72 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {conc.itm(0)} -attr vt d
+load net {conc.itm(1)} -attr vt d
+load net {conc.itm(2)} -attr vt d
+load net {conc.itm(3)} -attr vt d
+load net {conc.itm(4)} -attr vt d
+load net {conc.itm(5)} -attr vt d
+load net {conc.itm(6)} -attr vt d
+load net {conc.itm(7)} -attr vt d
+load net {conc.itm(8)} -attr vt d
+load net {conc.itm(9)} -attr vt d
+load netBundle {conc.itm} 10 {conc.itm(0)} {conc.itm(1)} {conc.itm(2)} {conc.itm(3)} {conc.itm(4)} {conc.itm(5)} {conc.itm(6)} {conc.itm(7)} {conc.itm(8)} {conc.itm(9)} -attr xrf 24777 -attr oid 73 -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {slc(FRAME:acc#2.psp.sva)#5.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#5.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#5.itm} 2 {slc(FRAME:acc#2.psp.sva)#5.itm(0)} {slc(FRAME:acc#2.psp.sva)#5.itm(1)} -attr xrf 24778 -attr oid 74 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#5.itm}
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(3)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#2.itm} 4 {slc(FRAME:acc#2.psp.sva)#2.itm(0)} {slc(FRAME:acc#2.psp.sva)#2.itm(1)} {slc(FRAME:acc#2.psp.sva)#2.itm(2)} {slc(FRAME:acc#2.psp.sva)#2.itm(3)} -attr xrf 24779 -attr oid 75 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#2.itm}
+load net {FRAME:or#3.itm(0)} -attr vt d
+load net {FRAME:or#3.itm(1)} -attr vt d
+load net {FRAME:or#3.itm(2)} -attr vt d
+load net {FRAME:or#3.itm(3)} -attr vt d
+load net {FRAME:or#3.itm(4)} -attr vt d
+load net {FRAME:or#3.itm(5)} -attr vt d
+load netBundle {FRAME:or#3.itm} 6 {FRAME:or#3.itm(0)} {FRAME:or#3.itm(1)} {FRAME:or#3.itm(2)} {FRAME:or#3.itm(3)} {FRAME:or#3.itm(4)} {FRAME:or#3.itm(5)} -attr xrf 24780 -attr oid 76 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(3)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(4)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(5)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#3.itm} 6 {slc(FRAME:acc#2.psp.sva)#3.itm(0)} {slc(FRAME:acc#2.psp.sva)#3.itm(1)} {slc(FRAME:acc#2.psp.sva)#3.itm(2)} {slc(FRAME:acc#2.psp.sva)#3.itm(3)} {slc(FRAME:acc#2.psp.sva)#3.itm(4)} {slc(FRAME:acc#2.psp.sva)#3.itm(5)} -attr xrf 24781 -attr oid 77 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {conc#589.itm(0)} -attr vt d
+load net {conc#589.itm(1)} -attr vt d
+load net {conc#589.itm(2)} -attr vt d
+load net {conc#589.itm(3)} -attr vt d
+load net {conc#589.itm(4)} -attr vt d
+load net {conc#589.itm(5)} -attr vt d
+load netBundle {conc#589.itm} 6 {conc#589.itm(0)} {conc#589.itm(1)} {conc#589.itm(2)} {conc#589.itm(3)} {conc#589.itm(4)} {conc#589.itm(5)} -attr xrf 24782 -attr oid 78 -attr vt d -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {slc(FRAME:acc#2.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#1.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#1.itm} 2 {slc(FRAME:acc#2.psp.sva)#1.itm(0)} {slc(FRAME:acc#2.psp.sva)#1.itm(1)} -attr xrf 24783 -attr oid 79 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#1.itm}
+load net {slc(FRAME:acc#2.psp.sva).itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(3)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(4)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(5)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(6)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(7)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(8)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(9)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva).itm} 10 {slc(FRAME:acc#2.psp.sva).itm(0)} {slc(FRAME:acc#2.psp.sva).itm(1)} {slc(FRAME:acc#2.psp.sva).itm(2)} {slc(FRAME:acc#2.psp.sva).itm(3)} {slc(FRAME:acc#2.psp.sva).itm(4)} {slc(FRAME:acc#2.psp.sva).itm(5)} {slc(FRAME:acc#2.psp.sva).itm(6)} {slc(FRAME:acc#2.psp.sva).itm(7)} {slc(FRAME:acc#2.psp.sva).itm(8)} {slc(FRAME:acc#2.psp.sva).itm(9)} -attr xrf 24784 -attr oid 80 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva).itm}
+load net {mux#1.itm(0)} -attr vt d
+load net {mux#1.itm(1)} -attr vt d
+load net {mux#1.itm(2)} -attr vt d
+load net {mux#1.itm(3)} -attr vt d
+load net {mux#1.itm(4)} -attr vt d
+load net {mux#1.itm(5)} -attr vt d
+load net {mux#1.itm(6)} -attr vt d
+load net {mux#1.itm(7)} -attr vt d
+load net {mux#1.itm(8)} -attr vt d
+load net {mux#1.itm(9)} -attr vt d
+load net {mux#1.itm(10)} -attr vt d
+load net {mux#1.itm(11)} -attr vt d
+load net {mux#1.itm(12)} -attr vt d
+load net {mux#1.itm(13)} -attr vt d
+load net {mux#1.itm(14)} -attr vt d
+load net {mux#1.itm(15)} -attr vt d
+load netBundle {mux#1.itm} 16 {mux#1.itm(0)} {mux#1.itm(1)} {mux#1.itm(2)} {mux#1.itm(3)} {mux#1.itm(4)} {mux#1.itm(5)} {mux#1.itm(6)} {mux#1.itm(7)} {mux#1.itm(8)} {mux#1.itm(9)} {mux#1.itm(10)} {mux#1.itm(11)} {mux#1.itm(12)} {mux#1.itm(13)} {mux#1.itm(14)} {mux#1.itm(15)} -attr xrf 24785 -attr oid 81 -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {ACC1:acc#341.itm(0)} -attr vt d
+load net {ACC1:acc#341.itm(1)} -attr vt d
+load net {ACC1:acc#341.itm(2)} -attr vt d
+load net {ACC1:acc#341.itm(3)} -attr vt d
+load net {ACC1:acc#341.itm(4)} -attr vt d
+load net {ACC1:acc#341.itm(5)} -attr vt d
+load net {ACC1:acc#341.itm(6)} -attr vt d
+load net {ACC1:acc#341.itm(7)} -attr vt d
+load net {ACC1:acc#341.itm(8)} -attr vt d
+load net {ACC1:acc#341.itm(9)} -attr vt d
+load net {ACC1:acc#341.itm(10)} -attr vt d
+load net {ACC1:acc#341.itm(11)} -attr vt d
+load net {ACC1:acc#341.itm(12)} -attr vt d
+load netBundle {ACC1:acc#341.itm} 13 {ACC1:acc#341.itm(0)} {ACC1:acc#341.itm(1)} {ACC1:acc#341.itm(2)} {ACC1:acc#341.itm(3)} {ACC1:acc#341.itm(4)} {ACC1:acc#341.itm(5)} {ACC1:acc#341.itm(6)} {ACC1:acc#341.itm(7)} {ACC1:acc#341.itm(8)} {ACC1:acc#341.itm(9)} {ACC1:acc#341.itm(10)} {ACC1:acc#341.itm(11)} {ACC1:acc#341.itm(12)} -attr xrf 24786 -attr oid 82 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#340.itm(0)} -attr vt d
+load net {ACC1:acc#340.itm(1)} -attr vt d
+load net {ACC1:acc#340.itm(2)} -attr vt d
+load net {ACC1:acc#340.itm(3)} -attr vt d
+load net {ACC1:acc#340.itm(4)} -attr vt d
+load net {ACC1:acc#340.itm(5)} -attr vt d
+load net {ACC1:acc#340.itm(6)} -attr vt d
+load net {ACC1:acc#340.itm(7)} -attr vt d
+load net {ACC1:acc#340.itm(8)} -attr vt d
+load net {ACC1:acc#340.itm(9)} -attr vt d
+load net {ACC1:acc#340.itm(10)} -attr vt d
+load net {ACC1:acc#340.itm(11)} -attr vt d
+load net {ACC1:acc#340.itm(12)} -attr vt d
+load netBundle {ACC1:acc#340.itm} 13 {ACC1:acc#340.itm(0)} {ACC1:acc#340.itm(1)} {ACC1:acc#340.itm(2)} {ACC1:acc#340.itm(3)} {ACC1:acc#340.itm(4)} {ACC1:acc#340.itm(5)} {ACC1:acc#340.itm(6)} {ACC1:acc#340.itm(7)} {ACC1:acc#340.itm(8)} {ACC1:acc#340.itm(9)} {ACC1:acc#340.itm(10)} {ACC1:acc#340.itm(11)} {ACC1:acc#340.itm(12)} -attr xrf 24787 -attr oid 83 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:mul#20.itm(0)} -attr vt d
+load net {ACC1:mul#20.itm(1)} -attr vt d
+load net {ACC1:mul#20.itm(2)} -attr vt d
+load net {ACC1:mul#20.itm(3)} -attr vt d
+load net {ACC1:mul#20.itm(4)} -attr vt d
+load net {ACC1:mul#20.itm(5)} -attr vt d
+load net {ACC1:mul#20.itm(6)} -attr vt d
+load net {ACC1:mul#20.itm(7)} -attr vt d
+load net {ACC1:mul#20.itm(8)} -attr vt d
+load net {ACC1:mul#20.itm(9)} -attr vt d
+load net {ACC1:mul#20.itm(10)} -attr vt d
+load net {ACC1:mul#20.itm(11)} -attr vt d
+load net {ACC1:mul#20.itm(12)} -attr vt d
+load netBundle {ACC1:mul#20.itm} 13 {ACC1:mul#20.itm(0)} {ACC1:mul#20.itm(1)} {ACC1:mul#20.itm(2)} {ACC1:mul#20.itm(3)} {ACC1:mul#20.itm(4)} {ACC1:mul#20.itm(5)} {ACC1:mul#20.itm(6)} {ACC1:mul#20.itm(7)} {ACC1:mul#20.itm(8)} {ACC1:mul#20.itm(9)} {ACC1:mul#20.itm(10)} {ACC1:mul#20.itm(11)} {ACC1:mul#20.itm(12)} -attr xrf 24788 -attr oid 84 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC2:acc#5.itm(0)} -attr vt d
+load net {ACC2:acc#5.itm(1)} -attr vt d
+load netBundle {ACC2:acc#5.itm} 2 {ACC2:acc#5.itm(0)} {ACC2:acc#5.itm(1)} -attr xrf 24789 -attr oid 85 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#5.itm}
+load net {ACC1:acc#338.itm(0)} -attr vt d
+load net {ACC1:acc#338.itm(1)} -attr vt d
+load net {ACC1:acc#338.itm(2)} -attr vt d
+load net {ACC1:acc#338.itm(3)} -attr vt d
+load net {ACC1:acc#338.itm(4)} -attr vt d
+load net {ACC1:acc#338.itm(5)} -attr vt d
+load net {ACC1:acc#338.itm(6)} -attr vt d
+load net {ACC1:acc#338.itm(7)} -attr vt d
+load net {ACC1:acc#338.itm(8)} -attr vt d
+load net {ACC1:acc#338.itm(9)} -attr vt d
+load netBundle {ACC1:acc#338.itm} 10 {ACC1:acc#338.itm(0)} {ACC1:acc#338.itm(1)} {ACC1:acc#338.itm(2)} {ACC1:acc#338.itm(3)} {ACC1:acc#338.itm(4)} {ACC1:acc#338.itm(5)} {ACC1:acc#338.itm(6)} {ACC1:acc#338.itm(7)} {ACC1:acc#338.itm(8)} {ACC1:acc#338.itm(9)} -attr xrf 24790 -attr oid 86 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#336.itm(0)} -attr vt d
+load net {ACC1:acc#336.itm(1)} -attr vt d
+load net {ACC1:acc#336.itm(2)} -attr vt d
+load net {ACC1:acc#336.itm(3)} -attr vt d
+load net {ACC1:acc#336.itm(4)} -attr vt d
+load net {ACC1:acc#336.itm(5)} -attr vt d
+load net {ACC1:acc#336.itm(6)} -attr vt d
+load net {ACC1:acc#336.itm(7)} -attr vt d
+load net {ACC1:acc#336.itm(8)} -attr vt d
+load net {ACC1:acc#336.itm(9)} -attr vt d
+load netBundle {ACC1:acc#336.itm} 10 {ACC1:acc#336.itm(0)} {ACC1:acc#336.itm(1)} {ACC1:acc#336.itm(2)} {ACC1:acc#336.itm(3)} {ACC1:acc#336.itm(4)} {ACC1:acc#336.itm(5)} {ACC1:acc#336.itm(6)} {ACC1:acc#336.itm(7)} {ACC1:acc#336.itm(8)} {ACC1:acc#336.itm(9)} -attr xrf 24791 -attr oid 87 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:conc.itm(0)} -attr vt d
+load net {ACC1:conc.itm(1)} -attr vt d
+load net {ACC1:conc.itm(2)} -attr vt d
+load net {ACC1:conc.itm(3)} -attr vt d
+load net {ACC1:conc.itm(4)} -attr vt d
+load net {ACC1:conc.itm(5)} -attr vt d
+load net {ACC1:conc.itm(6)} -attr vt d
+load net {ACC1:conc.itm(7)} -attr vt d
+load net {ACC1:conc.itm(8)} -attr vt d
+load netBundle {ACC1:conc.itm} 9 {ACC1:conc.itm(0)} {ACC1:conc.itm(1)} {ACC1:conc.itm(2)} {ACC1:conc.itm(3)} {ACC1:conc.itm(4)} {ACC1:conc.itm(5)} {ACC1:conc.itm(6)} {ACC1:conc.itm(7)} {ACC1:conc.itm(8)} -attr xrf 24792 -attr oid 88 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(0)} -attr vt d
+load net {ACC1:mul#21.itm(1)} -attr vt d
+load net {ACC1:mul#21.itm(2)} -attr vt d
+load net {ACC1:mul#21.itm(3)} -attr vt d
+load net {ACC1:mul#21.itm(4)} -attr vt d
+load net {ACC1:mul#21.itm(5)} -attr vt d
+load netBundle {ACC1:mul#21.itm} 6 {ACC1:mul#21.itm(0)} {ACC1:mul#21.itm(1)} {ACC1:mul#21.itm(2)} {ACC1:mul#21.itm(3)} {ACC1:mul#21.itm(4)} {ACC1:mul#21.itm(5)} -attr xrf 24793 -attr oid 89 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load net {ACC2:acc#6.itm(0)} -attr vt d
+load net {ACC2:acc#6.itm(1)} -attr vt d
+load netBundle {ACC2:acc#6.itm} 2 {ACC2:acc#6.itm(0)} {ACC2:acc#6.itm(1)} -attr xrf 24794 -attr oid 90 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#6.itm}
+load net {ACC1-3:exs#563.itm(0)} -attr vt d
+load net {ACC1-3:exs#563.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#563.itm} 2 {ACC1-3:exs#563.itm(0)} {ACC1-3:exs#563.itm(1)} -attr xrf 24795 -attr oid 91 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#563.itm}
+load net {ACC1:acc#334.itm(0)} -attr vt d
+load net {ACC1:acc#334.itm(1)} -attr vt d
+load net {ACC1:acc#334.itm(2)} -attr vt d
+load net {ACC1:acc#334.itm(3)} -attr vt d
+load net {ACC1:acc#334.itm(4)} -attr vt d
+load net {ACC1:acc#334.itm(5)} -attr vt d
+load net {ACC1:acc#334.itm(6)} -attr vt d
+load net {ACC1:acc#334.itm(7)} -attr vt d
+load netBundle {ACC1:acc#334.itm} 8 {ACC1:acc#334.itm(0)} {ACC1:acc#334.itm(1)} {ACC1:acc#334.itm(2)} {ACC1:acc#334.itm(3)} {ACC1:acc#334.itm(4)} {ACC1:acc#334.itm(5)} {ACC1:acc#334.itm(6)} {ACC1:acc#334.itm(7)} -attr xrf 24796 -attr oid 92 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:mul#18.itm(0)} -attr vt d
+load net {ACC1:mul#18.itm(1)} -attr vt d
+load net {ACC1:mul#18.itm(2)} -attr vt d
+load net {ACC1:mul#18.itm(3)} -attr vt d
+load net {ACC1:mul#18.itm(4)} -attr vt d
+load net {ACC1:mul#18.itm(5)} -attr vt d
+load net {ACC1:mul#18.itm(6)} -attr vt d
+load net {ACC1:mul#18.itm(7)} -attr vt d
+load netBundle {ACC1:mul#18.itm} 8 {ACC1:mul#18.itm(0)} {ACC1:mul#18.itm(1)} {ACC1:mul#18.itm(2)} {ACC1:mul#18.itm(3)} {ACC1:mul#18.itm(4)} {ACC1:mul#18.itm(5)} {ACC1:mul#18.itm(6)} {ACC1:mul#18.itm(7)} -attr xrf 24797 -attr oid 93 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC2:acc#3.itm(0)} -attr vt d
+load net {ACC2:acc#3.itm(1)} -attr vt d
+load netBundle {ACC2:acc#3.itm} 2 {ACC2:acc#3.itm(0)} {ACC2:acc#3.itm(1)} -attr xrf 24798 -attr oid 94 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#3.itm}
+load net {ACC1:acc#330.itm(0)} -attr vt d
+load net {ACC1:acc#330.itm(1)} -attr vt d
+load net {ACC1:acc#330.itm(2)} -attr vt d
+load net {ACC1:acc#330.itm(3)} -attr vt d
+load net {ACC1:acc#330.itm(4)} -attr vt d
+load net {ACC1:acc#330.itm(5)} -attr vt d
+load net {ACC1:acc#330.itm(6)} -attr vt d
+load netBundle {ACC1:acc#330.itm} 7 {ACC1:acc#330.itm(0)} {ACC1:acc#330.itm(1)} {ACC1:acc#330.itm(2)} {ACC1:acc#330.itm(3)} {ACC1:acc#330.itm(4)} {ACC1:acc#330.itm(5)} {ACC1:acc#330.itm(6)} -attr xrf 24799 -attr oid 95 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:mul.itm(0)} -attr vt d
+load net {ACC1:mul.itm(1)} -attr vt d
+load net {ACC1:mul.itm(2)} -attr vt d
+load net {ACC1:mul.itm(3)} -attr vt d
+load net {ACC1:mul.itm(4)} -attr vt d
+load net {ACC1:mul.itm(5)} -attr vt d
+load netBundle {ACC1:mul.itm} 6 {ACC1:mul.itm(0)} {ACC1:mul.itm(1)} {ACC1:mul.itm(2)} {ACC1:mul.itm(3)} {ACC1:mul.itm(4)} {ACC1:mul.itm(5)} -attr xrf 24800 -attr oid 96 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC2:acc.itm(0)} -attr vt d
+load net {ACC2:acc.itm(1)} -attr vt d
+load netBundle {ACC2:acc.itm} 2 {ACC2:acc.itm(0)} {ACC2:acc.itm(1)} -attr xrf 24801 -attr oid 97 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {conc#590.itm(0)} -attr vt d
+load net {conc#590.itm(1)} -attr vt d
+load net {conc#590.itm(2)} -attr vt d
+load net {conc#590.itm(3)} -attr vt d
+load net {conc#590.itm(4)} -attr vt d
+load net {conc#590.itm(5)} -attr vt d
+load netBundle {conc#590.itm} 6 {conc#590.itm(0)} {conc#590.itm(1)} {conc#590.itm(2)} {conc#590.itm(3)} {conc#590.itm(4)} {conc#590.itm(5)} -attr xrf 24802 -attr oid 98 -attr vt d -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {ACC1-3:exs#568.itm(0)} -attr vt d
+load net {ACC1-3:exs#568.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#568.itm} 2 {ACC1-3:exs#568.itm(0)} {ACC1-3:exs#568.itm(1)} -attr xrf 24803 -attr oid 99 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#568.itm}
+load net {ACC1:acc#335.itm(0)} -attr vt d
+load net {ACC1:acc#335.itm(1)} -attr vt d
+load net {ACC1:acc#335.itm(2)} -attr vt d
+load net {ACC1:acc#335.itm(3)} -attr vt d
+load net {ACC1:acc#335.itm(4)} -attr vt d
+load net {ACC1:acc#335.itm(5)} -attr vt d
+load net {ACC1:acc#335.itm(6)} -attr vt d
+load net {ACC1:acc#335.itm(7)} -attr vt d
+load netBundle {ACC1:acc#335.itm} 8 {ACC1:acc#335.itm(0)} {ACC1:acc#335.itm(1)} {ACC1:acc#335.itm(2)} {ACC1:acc#335.itm(3)} {ACC1:acc#335.itm(4)} {ACC1:acc#335.itm(5)} {ACC1:acc#335.itm(6)} {ACC1:acc#335.itm(7)} -attr xrf 24804 -attr oid 100 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#332.itm(0)} -attr vt d
+load net {ACC1:acc#332.itm(1)} -attr vt d
+load net {ACC1:acc#332.itm(2)} -attr vt d
+load net {ACC1:acc#332.itm(3)} -attr vt d
+load net {ACC1:acc#332.itm(4)} -attr vt d
+load net {ACC1:acc#332.itm(5)} -attr vt d
+load net {ACC1:acc#332.itm(6)} -attr vt d
+load net {ACC1:acc#332.itm(7)} -attr vt d
+load netBundle {ACC1:acc#332.itm} 8 {ACC1:acc#332.itm(0)} {ACC1:acc#332.itm(1)} {ACC1:acc#332.itm(2)} {ACC1:acc#332.itm(3)} {ACC1:acc#332.itm(4)} {ACC1:acc#332.itm(5)} {ACC1:acc#332.itm(6)} {ACC1:acc#332.itm(7)} -attr xrf 24805 -attr oid 101 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1-1:exs#541.itm(0)} -attr vt d
+load net {ACC1-1:exs#541.itm(1)} -attr vt d
+load net {ACC1-1:exs#541.itm(2)} -attr vt d
+load net {ACC1-1:exs#541.itm(3)} -attr vt d
+load net {ACC1-1:exs#541.itm(4)} -attr vt d
+load net {ACC1-1:exs#541.itm(5)} -attr vt d
+load net {ACC1-1:exs#541.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#541.itm} 7 {ACC1-1:exs#541.itm(0)} {ACC1-1:exs#541.itm(1)} {ACC1-1:exs#541.itm(2)} {ACC1-1:exs#541.itm(3)} {ACC1-1:exs#541.itm(4)} {ACC1-1:exs#541.itm(5)} {ACC1-1:exs#541.itm(6)} -attr xrf 24806 -attr oid 102 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1-1:conc#240.itm(0)} -attr vt d
+load net {ACC1-1:conc#240.itm(1)} -attr vt d
+load net {ACC1-1:conc#240.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#240.itm} 3 {ACC1-1:conc#240.itm(0)} {ACC1-1:conc#240.itm(1)} {ACC1-1:conc#240.itm(2)} -attr xrf 24807 -attr oid 103 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#240.itm}
+load net {ACC1-1:exs#30.itm(0)} -attr vt d
+load net {ACC1-1:exs#30.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#30.itm} 2 {ACC1-1:exs#30.itm(0)} {ACC1-1:exs#30.itm(1)} -attr xrf 24808 -attr oid 104 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#30.itm}
+load net {ACC1:acc#328.itm(0)} -attr vt d
+load net {ACC1:acc#328.itm(1)} -attr vt d
+load net {ACC1:acc#328.itm(2)} -attr vt d
+load net {ACC1:acc#328.itm(3)} -attr vt d
+load net {ACC1:acc#328.itm(4)} -attr vt d
+load net {ACC1:acc#328.itm(5)} -attr vt d
+load netBundle {ACC1:acc#328.itm} 6 {ACC1:acc#328.itm(0)} {ACC1:acc#328.itm(1)} {ACC1:acc#328.itm(2)} {ACC1:acc#328.itm(3)} {ACC1:acc#328.itm(4)} {ACC1:acc#328.itm(5)} -attr xrf 24809 -attr oid 105 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#325.itm(0)} -attr vt d
+load net {ACC1:acc#325.itm(1)} -attr vt d
+load net {ACC1:acc#325.itm(2)} -attr vt d
+load net {ACC1:acc#325.itm(3)} -attr vt d
+load net {ACC1:acc#325.itm(4)} -attr vt d
+load netBundle {ACC1:acc#325.itm} 5 {ACC1:acc#325.itm(0)} {ACC1:acc#325.itm(1)} {ACC1:acc#325.itm(2)} {ACC1:acc#325.itm(3)} {ACC1:acc#325.itm(4)} -attr xrf 24810 -attr oid 106 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#319.itm(0)} -attr vt d
+load net {ACC1:acc#319.itm(1)} -attr vt d
+load net {ACC1:acc#319.itm(2)} -attr vt d
+load net {ACC1:acc#319.itm(3)} -attr vt d
+load netBundle {ACC1:acc#319.itm} 4 {ACC1:acc#319.itm(0)} {ACC1:acc#319.itm(1)} {ACC1:acc#319.itm(2)} {ACC1:acc#319.itm(3)} -attr xrf 24811 -attr oid 107 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:slc#97.itm(0)} -attr vt d
+load net {ACC1:slc#97.itm(1)} -attr vt d
+load net {ACC1:slc#97.itm(2)} -attr vt d
+load netBundle {ACC1:slc#97.itm} 3 {ACC1:slc#97.itm(0)} {ACC1:slc#97.itm(1)} {ACC1:slc#97.itm(2)} -attr xrf 24812 -attr oid 108 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#310.itm(0)} -attr vt d
+load net {ACC1:acc#310.itm(1)} -attr vt d
+load net {ACC1:acc#310.itm(2)} -attr vt d
+load net {ACC1:acc#310.itm(3)} -attr vt d
+load netBundle {ACC1:acc#310.itm} 4 {ACC1:acc#310.itm(0)} {ACC1:acc#310.itm(1)} {ACC1:acc#310.itm(2)} {ACC1:acc#310.itm(3)} -attr xrf 24813 -attr oid 109 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {exs.itm(0)} -attr vt d
+load net {exs.itm(1)} -attr vt d
+load net {exs.itm(2)} -attr vt d
+load netBundle {exs.itm} 3 {exs.itm(0)} {exs.itm(1)} {exs.itm(2)} -attr xrf 24814 -attr oid 110 -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {conc#591.itm(0)} -attr vt d
+load net {conc#591.itm(1)} -attr vt d
+load netBundle {conc#591.itm} 2 {conc#591.itm(0)} {conc#591.itm(1)} -attr xrf 24815 -attr oid 111 -attr vt d -attr @path {/sobel/sobel:core/conc#591.itm}
+load net {ACC1:exs#793.itm(0)} -attr vt d
+load net {ACC1:exs#793.itm(1)} -attr vt d
+load net {ACC1:exs#793.itm(2)} -attr vt d
+load netBundle {ACC1:exs#793.itm} 3 {ACC1:exs#793.itm(0)} {ACC1:exs#793.itm(1)} {ACC1:exs#793.itm(2)} -attr xrf 24816 -attr oid 112 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#793.itm}
+load net {ACC1:conc#642.itm(0)} -attr vt d
+load net {ACC1:conc#642.itm(1)} -attr vt d
+load netBundle {ACC1:conc#642.itm} 2 {ACC1:conc#642.itm(0)} {ACC1:conc#642.itm(1)} -attr xrf 24817 -attr oid 113 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#642.itm}
+load net {ACC1:slc#96.itm(0)} -attr vt d
+load net {ACC1:slc#96.itm(1)} -attr vt d
+load net {ACC1:slc#96.itm(2)} -attr vt d
+load netBundle {ACC1:slc#96.itm} 3 {ACC1:slc#96.itm(0)} {ACC1:slc#96.itm(1)} {ACC1:slc#96.itm(2)} -attr xrf 24818 -attr oid 114 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#309.itm(0)} -attr vt d
+load net {ACC1:acc#309.itm(1)} -attr vt d
+load net {ACC1:acc#309.itm(2)} -attr vt d
+load net {ACC1:acc#309.itm(3)} -attr vt d
+load netBundle {ACC1:acc#309.itm} 4 {ACC1:acc#309.itm(0)} {ACC1:acc#309.itm(1)} {ACC1:acc#309.itm(2)} {ACC1:acc#309.itm(3)} -attr xrf 24819 -attr oid 115 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {exs#54.itm(0)} -attr vt d
+load net {exs#54.itm(1)} -attr vt d
+load net {exs#54.itm(2)} -attr vt d
+load netBundle {exs#54.itm} 3 {exs#54.itm(0)} {exs#54.itm(1)} {exs#54.itm(2)} -attr xrf 24820 -attr oid 116 -attr vt d -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {conc#592.itm(0)} -attr vt d
+load net {conc#592.itm(1)} -attr vt d
+load netBundle {conc#592.itm} 2 {conc#592.itm(0)} {conc#592.itm(1)} -attr xrf 24821 -attr oid 117 -attr vt d -attr @path {/sobel/sobel:core/conc#592.itm}
+load net {ACC1:exs#795.itm(0)} -attr vt d
+load net {ACC1:exs#795.itm(1)} -attr vt d
+load net {ACC1:exs#795.itm(2)} -attr vt d
+load netBundle {ACC1:exs#795.itm} 3 {ACC1:exs#795.itm(0)} {ACC1:exs#795.itm(1)} {ACC1:exs#795.itm(2)} -attr xrf 24822 -attr oid 118 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#795.itm}
+load net {ACC1:conc#640.itm(0)} -attr vt d
+load net {ACC1:conc#640.itm(1)} -attr vt d
+load netBundle {ACC1:conc#640.itm} 2 {ACC1:conc#640.itm(0)} {ACC1:conc#640.itm(1)} -attr xrf 24823 -attr oid 119 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#640.itm}
+load net {ACC1:acc#318.itm(0)} -attr vt d
+load net {ACC1:acc#318.itm(1)} -attr vt d
+load net {ACC1:acc#318.itm(2)} -attr vt d
+load net {ACC1:acc#318.itm(3)} -attr vt d
+load netBundle {ACC1:acc#318.itm} 4 {ACC1:acc#318.itm(0)} {ACC1:acc#318.itm(1)} {ACC1:acc#318.itm(2)} {ACC1:acc#318.itm(3)} -attr xrf 24824 -attr oid 120 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:slc#94.itm(0)} -attr vt d
+load net {ACC1:slc#94.itm(1)} -attr vt d
+load net {ACC1:slc#94.itm(2)} -attr vt d
+load netBundle {ACC1:slc#94.itm} 3 {ACC1:slc#94.itm(0)} {ACC1:slc#94.itm(1)} {ACC1:slc#94.itm(2)} -attr xrf 24825 -attr oid 121 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#307.itm(0)} -attr vt d
+load net {ACC1:acc#307.itm(1)} -attr vt d
+load net {ACC1:acc#307.itm(2)} -attr vt d
+load net {ACC1:acc#307.itm(3)} -attr vt d
+load netBundle {ACC1:acc#307.itm} 4 {ACC1:acc#307.itm(0)} {ACC1:acc#307.itm(1)} {ACC1:acc#307.itm(2)} {ACC1:acc#307.itm(3)} -attr xrf 24826 -attr oid 122 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {exs#28.itm(0)} -attr vt d
+load net {exs#28.itm(1)} -attr vt d
+load net {exs#28.itm(2)} -attr vt d
+load netBundle {exs#28.itm} 3 {exs#28.itm(0)} {exs#28.itm(1)} {exs#28.itm(2)} -attr xrf 24827 -attr oid 123 -attr vt d -attr @path {/sobel/sobel:core/exs#28.itm}
+load net {conc#594.itm(0)} -attr vt d
+load net {conc#594.itm(1)} -attr vt d
+load netBundle {conc#594.itm} 2 {conc#594.itm(0)} {conc#594.itm(1)} -attr xrf 24828 -attr oid 124 -attr vt d -attr @path {/sobel/sobel:core/conc#594.itm}
+load net {ACC1:exs#797.itm(0)} -attr vt d
+load net {ACC1:exs#797.itm(1)} -attr vt d
+load net {ACC1:exs#797.itm(2)} -attr vt d
+load netBundle {ACC1:exs#797.itm} 3 {ACC1:exs#797.itm(0)} {ACC1:exs#797.itm(1)} {ACC1:exs#797.itm(2)} -attr xrf 24829 -attr oid 125 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#797.itm}
+load net {ACC1:conc#636.itm(0)} -attr vt d
+load net {ACC1:conc#636.itm(1)} -attr vt d
+load netBundle {ACC1:conc#636.itm} 2 {ACC1:conc#636.itm(0)} {ACC1:conc#636.itm(1)} -attr xrf 24830 -attr oid 126 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#636.itm}
+load net {ACC1:slc#93.itm(0)} -attr vt d
+load net {ACC1:slc#93.itm(1)} -attr vt d
+load net {ACC1:slc#93.itm(2)} -attr vt d
+load netBundle {ACC1:slc#93.itm} 3 {ACC1:slc#93.itm(0)} {ACC1:slc#93.itm(1)} {ACC1:slc#93.itm(2)} -attr xrf 24831 -attr oid 127 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#306.itm(0)} -attr vt d
+load net {ACC1:acc#306.itm(1)} -attr vt d
+load net {ACC1:acc#306.itm(2)} -attr vt d
+load net {ACC1:acc#306.itm(3)} -attr vt d
+load netBundle {ACC1:acc#306.itm} 4 {ACC1:acc#306.itm(0)} {ACC1:acc#306.itm(1)} {ACC1:acc#306.itm(2)} {ACC1:acc#306.itm(3)} -attr xrf 24832 -attr oid 128 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {exs#29.itm(0)} -attr vt d
+load net {exs#29.itm(1)} -attr vt d
+load net {exs#29.itm(2)} -attr vt d
+load netBundle {exs#29.itm} 3 {exs#29.itm(0)} {exs#29.itm(1)} {exs#29.itm(2)} -attr xrf 24833 -attr oid 129 -attr vt d -attr @path {/sobel/sobel:core/exs#29.itm}
+load net {conc#595.itm(0)} -attr vt d
+load net {conc#595.itm(1)} -attr vt d
+load netBundle {conc#595.itm} 2 {conc#595.itm(0)} {conc#595.itm(1)} -attr xrf 24834 -attr oid 130 -attr vt d -attr @path {/sobel/sobel:core/conc#595.itm}
+load net {ACC1:exs#799.itm(0)} -attr vt d
+load net {ACC1:exs#799.itm(1)} -attr vt d
+load net {ACC1:exs#799.itm(2)} -attr vt d
+load netBundle {ACC1:exs#799.itm} 3 {ACC1:exs#799.itm(0)} {ACC1:exs#799.itm(1)} {ACC1:exs#799.itm(2)} -attr xrf 24835 -attr oid 131 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#799.itm}
+load net {ACC1:conc#634.itm(0)} -attr vt d
+load net {ACC1:conc#634.itm(1)} -attr vt d
+load netBundle {ACC1:conc#634.itm} 2 {ACC1:conc#634.itm(0)} {ACC1:conc#634.itm(1)} -attr xrf 24836 -attr oid 132 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#634.itm}
+load net {ACC1:acc#324.itm(0)} -attr vt d
+load net {ACC1:acc#324.itm(1)} -attr vt d
+load net {ACC1:acc#324.itm(2)} -attr vt d
+load net {ACC1:acc#324.itm(3)} -attr vt d
+load net {ACC1:acc#324.itm(4)} -attr vt d
+load netBundle {ACC1:acc#324.itm} 5 {ACC1:acc#324.itm(0)} {ACC1:acc#324.itm(1)} {ACC1:acc#324.itm(2)} {ACC1:acc#324.itm(3)} {ACC1:acc#324.itm(4)} -attr xrf 24837 -attr oid 133 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#317.itm(0)} -attr vt d
+load net {ACC1:acc#317.itm(1)} -attr vt d
+load net {ACC1:acc#317.itm(2)} -attr vt d
+load net {ACC1:acc#317.itm(3)} -attr vt d
+load netBundle {ACC1:acc#317.itm} 4 {ACC1:acc#317.itm(0)} {ACC1:acc#317.itm(1)} {ACC1:acc#317.itm(2)} {ACC1:acc#317.itm(3)} -attr xrf 24838 -attr oid 134 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:slc#92.itm(0)} -attr vt d
+load net {ACC1:slc#92.itm(1)} -attr vt d
+load net {ACC1:slc#92.itm(2)} -attr vt d
+load netBundle {ACC1:slc#92.itm} 3 {ACC1:slc#92.itm(0)} {ACC1:slc#92.itm(1)} {ACC1:slc#92.itm(2)} -attr xrf 24839 -attr oid 135 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#92.itm}
+load net {ACC1:acc#305.itm(0)} -attr vt d
+load net {ACC1:acc#305.itm(1)} -attr vt d
+load net {ACC1:acc#305.itm(2)} -attr vt d
+load net {ACC1:acc#305.itm(3)} -attr vt d
+load netBundle {ACC1:acc#305.itm} 4 {ACC1:acc#305.itm(0)} {ACC1:acc#305.itm(1)} {ACC1:acc#305.itm(2)} {ACC1:acc#305.itm(3)} -attr xrf 24840 -attr oid 136 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {exs#55.itm(0)} -attr vt d
+load net {exs#55.itm(1)} -attr vt d
+load net {exs#55.itm(2)} -attr vt d
+load netBundle {exs#55.itm} 3 {exs#55.itm(0)} {exs#55.itm(1)} {exs#55.itm(2)} -attr xrf 24841 -attr oid 137 -attr vt d -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {conc#596.itm(0)} -attr vt d
+load net {conc#596.itm(1)} -attr vt d
+load netBundle {conc#596.itm} 2 {conc#596.itm(0)} {conc#596.itm(1)} -attr xrf 24842 -attr oid 138 -attr vt d -attr @path {/sobel/sobel:core/conc#596.itm}
+load net {ACC1:exs#801.itm(0)} -attr vt d
+load net {ACC1:exs#801.itm(1)} -attr vt d
+load net {ACC1:exs#801.itm(2)} -attr vt d
+load netBundle {ACC1:exs#801.itm} 3 {ACC1:exs#801.itm(0)} {ACC1:exs#801.itm(1)} {ACC1:exs#801.itm(2)} -attr xrf 24843 -attr oid 139 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#801.itm}
+load net {ACC1:conc#632.itm(0)} -attr vt d
+load net {ACC1:conc#632.itm(1)} -attr vt d
+load netBundle {ACC1:conc#632.itm} 2 {ACC1:conc#632.itm(0)} {ACC1:conc#632.itm(1)} -attr xrf 24844 -attr oid 140 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#632.itm}
+load net {ACC1:slc#91.itm(0)} -attr vt d
+load net {ACC1:slc#91.itm(1)} -attr vt d
+load net {ACC1:slc#91.itm(2)} -attr vt d
+load netBundle {ACC1:slc#91.itm} 3 {ACC1:slc#91.itm(0)} {ACC1:slc#91.itm(1)} {ACC1:slc#91.itm(2)} -attr xrf 24845 -attr oid 141 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#91.itm}
+load net {ACC1:acc#304.itm(0)} -attr vt d
+load net {ACC1:acc#304.itm(1)} -attr vt d
+load net {ACC1:acc#304.itm(2)} -attr vt d
+load net {ACC1:acc#304.itm(3)} -attr vt d
+load netBundle {ACC1:acc#304.itm} 4 {ACC1:acc#304.itm(0)} {ACC1:acc#304.itm(1)} {ACC1:acc#304.itm(2)} {ACC1:acc#304.itm(3)} -attr xrf 24846 -attr oid 142 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {exs#56.itm(0)} -attr vt d
+load net {exs#56.itm(1)} -attr vt d
+load net {exs#56.itm(2)} -attr vt d
+load netBundle {exs#56.itm} 3 {exs#56.itm(0)} {exs#56.itm(1)} {exs#56.itm(2)} -attr xrf 24847 -attr oid 143 -attr vt d -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {conc#598.itm(0)} -attr vt d
+load net {conc#598.itm(1)} -attr vt d
+load netBundle {conc#598.itm} 2 {conc#598.itm(0)} {conc#598.itm(1)} -attr xrf 24848 -attr oid 144 -attr vt d -attr @path {/sobel/sobel:core/conc#598.itm}
+load net {ACC1:exs#803.itm(0)} -attr vt d
+load net {ACC1:exs#803.itm(1)} -attr vt d
+load net {ACC1:exs#803.itm(2)} -attr vt d
+load netBundle {ACC1:exs#803.itm} 3 {ACC1:exs#803.itm(0)} {ACC1:exs#803.itm(1)} {ACC1:exs#803.itm(2)} -attr xrf 24849 -attr oid 145 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#803.itm}
+load net {ACC1:conc#630.itm(0)} -attr vt d
+load net {ACC1:conc#630.itm(1)} -attr vt d
+load netBundle {ACC1:conc#630.itm} 2 {ACC1:conc#630.itm(0)} {ACC1:conc#630.itm(1)} -attr xrf 24850 -attr oid 146 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#630.itm}
+load net {ACC1:acc#316.itm(0)} -attr vt d
+load net {ACC1:acc#316.itm(1)} -attr vt d
+load net {ACC1:acc#316.itm(2)} -attr vt d
+load net {ACC1:acc#316.itm(3)} -attr vt d
+load netBundle {ACC1:acc#316.itm} 4 {ACC1:acc#316.itm(0)} {ACC1:acc#316.itm(1)} {ACC1:acc#316.itm(2)} {ACC1:acc#316.itm(3)} -attr xrf 24851 -attr oid 147 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:slc#90.itm(0)} -attr vt d
+load net {ACC1:slc#90.itm(1)} -attr vt d
+load net {ACC1:slc#90.itm(2)} -attr vt d
+load netBundle {ACC1:slc#90.itm} 3 {ACC1:slc#90.itm(0)} {ACC1:slc#90.itm(1)} {ACC1:slc#90.itm(2)} -attr xrf 24852 -attr oid 148 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1:acc#303.itm(0)} -attr vt d
+load net {ACC1:acc#303.itm(1)} -attr vt d
+load net {ACC1:acc#303.itm(2)} -attr vt d
+load net {ACC1:acc#303.itm(3)} -attr vt d
+load netBundle {ACC1:acc#303.itm} 4 {ACC1:acc#303.itm(0)} {ACC1:acc#303.itm(1)} {ACC1:acc#303.itm(2)} {ACC1:acc#303.itm(3)} -attr xrf 24853 -attr oid 149 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {exs#30.itm(0)} -attr vt d
+load net {exs#30.itm(1)} -attr vt d
+load net {exs#30.itm(2)} -attr vt d
+load netBundle {exs#30.itm} 3 {exs#30.itm(0)} {exs#30.itm(1)} {exs#30.itm(2)} -attr xrf 24854 -attr oid 150 -attr vt d -attr @path {/sobel/sobel:core/exs#30.itm}
+load net {conc#600.itm(0)} -attr vt d
+load net {conc#600.itm(1)} -attr vt d
+load netBundle {conc#600.itm} 2 {conc#600.itm(0)} {conc#600.itm(1)} -attr xrf 24855 -attr oid 151 -attr vt d -attr @path {/sobel/sobel:core/conc#600.itm}
+load net {ACC1:exs#805.itm(0)} -attr vt d
+load net {ACC1:exs#805.itm(1)} -attr vt d
+load net {ACC1:exs#805.itm(2)} -attr vt d
+load netBundle {ACC1:exs#805.itm} 3 {ACC1:exs#805.itm(0)} {ACC1:exs#805.itm(1)} {ACC1:exs#805.itm(2)} -attr xrf 24856 -attr oid 152 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#805.itm}
+load net {ACC1:conc#628.itm(0)} -attr vt d
+load net {ACC1:conc#628.itm(1)} -attr vt d
+load netBundle {ACC1:conc#628.itm} 2 {ACC1:conc#628.itm(0)} {ACC1:conc#628.itm(1)} -attr xrf 24857 -attr oid 153 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#628.itm}
+load net {ACC1:slc#89.itm(0)} -attr vt d
+load net {ACC1:slc#89.itm(1)} -attr vt d
+load net {ACC1:slc#89.itm(2)} -attr vt d
+load netBundle {ACC1:slc#89.itm} 3 {ACC1:slc#89.itm(0)} {ACC1:slc#89.itm(1)} {ACC1:slc#89.itm(2)} -attr xrf 24858 -attr oid 154 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#302.itm(0)} -attr vt d
+load net {ACC1:acc#302.itm(1)} -attr vt d
+load net {ACC1:acc#302.itm(2)} -attr vt d
+load net {ACC1:acc#302.itm(3)} -attr vt d
+load netBundle {ACC1:acc#302.itm} 4 {ACC1:acc#302.itm(0)} {ACC1:acc#302.itm(1)} {ACC1:acc#302.itm(2)} {ACC1:acc#302.itm(3)} -attr xrf 24859 -attr oid 155 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {exs#31.itm(0)} -attr vt d
+load net {exs#31.itm(1)} -attr vt d
+load net {exs#31.itm(2)} -attr vt d
+load netBundle {exs#31.itm} 3 {exs#31.itm(0)} {exs#31.itm(1)} {exs#31.itm(2)} -attr xrf 24860 -attr oid 156 -attr vt d -attr @path {/sobel/sobel:core/exs#31.itm}
+load net {conc#601.itm(0)} -attr vt d
+load net {conc#601.itm(1)} -attr vt d
+load netBundle {conc#601.itm} 2 {conc#601.itm(0)} {conc#601.itm(1)} -attr xrf 24861 -attr oid 157 -attr vt d -attr @path {/sobel/sobel:core/conc#601.itm}
+load net {ACC1:exs#807.itm(0)} -attr vt d
+load net {ACC1:exs#807.itm(1)} -attr vt d
+load net {ACC1:exs#807.itm(2)} -attr vt d
+load netBundle {ACC1:exs#807.itm} 3 {ACC1:exs#807.itm(0)} {ACC1:exs#807.itm(1)} {ACC1:exs#807.itm(2)} -attr xrf 24862 -attr oid 158 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#807.itm}
+load net {ACC1:conc#626.itm(0)} -attr vt d
+load net {ACC1:conc#626.itm(1)} -attr vt d
+load netBundle {ACC1:conc#626.itm} 2 {ACC1:conc#626.itm(0)} {ACC1:conc#626.itm(1)} -attr xrf 24863 -attr oid 159 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#626.itm}
+load net {ACC1:acc#331.itm(0)} -attr vt d
+load net {ACC1:acc#331.itm(1)} -attr vt d
+load net {ACC1:acc#331.itm(2)} -attr vt d
+load net {ACC1:acc#331.itm(3)} -attr vt d
+load net {ACC1:acc#331.itm(4)} -attr vt d
+load net {ACC1:acc#331.itm(5)} -attr vt d
+load net {ACC1:acc#331.itm(6)} -attr vt d
+load netBundle {ACC1:acc#331.itm} 7 {ACC1:acc#331.itm(0)} {ACC1:acc#331.itm(1)} {ACC1:acc#331.itm(2)} {ACC1:acc#331.itm(3)} {ACC1:acc#331.itm(4)} {ACC1:acc#331.itm(5)} {ACC1:acc#331.itm(6)} -attr xrf 24864 -attr oid 160 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#327.itm(0)} -attr vt d
+load net {ACC1:acc#327.itm(1)} -attr vt d
+load net {ACC1:acc#327.itm(2)} -attr vt d
+load net {ACC1:acc#327.itm(3)} -attr vt d
+load net {ACC1:acc#327.itm(4)} -attr vt d
+load net {ACC1:acc#327.itm(5)} -attr vt d
+load netBundle {ACC1:acc#327.itm} 6 {ACC1:acc#327.itm(0)} {ACC1:acc#327.itm(1)} {ACC1:acc#327.itm(2)} {ACC1:acc#327.itm(3)} {ACC1:acc#327.itm(4)} {ACC1:acc#327.itm(5)} -attr xrf 24865 -attr oid 161 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#323.itm(0)} -attr vt d
+load net {ACC1:acc#323.itm(1)} -attr vt d
+load net {ACC1:acc#323.itm(2)} -attr vt d
+load net {ACC1:acc#323.itm(3)} -attr vt d
+load net {ACC1:acc#323.itm(4)} -attr vt d
+load netBundle {ACC1:acc#323.itm} 5 {ACC1:acc#323.itm(0)} {ACC1:acc#323.itm(1)} {ACC1:acc#323.itm(2)} {ACC1:acc#323.itm(3)} {ACC1:acc#323.itm(4)} -attr xrf 24866 -attr oid 162 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#315.itm(0)} -attr vt d
+load net {ACC1:acc#315.itm(1)} -attr vt d
+load net {ACC1:acc#315.itm(2)} -attr vt d
+load net {ACC1:acc#315.itm(3)} -attr vt d
+load netBundle {ACC1:acc#315.itm} 4 {ACC1:acc#315.itm(0)} {ACC1:acc#315.itm(1)} {ACC1:acc#315.itm(2)} {ACC1:acc#315.itm(3)} -attr xrf 24867 -attr oid 163 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:slc#88.itm(0)} -attr vt d
+load net {ACC1:slc#88.itm(1)} -attr vt d
+load net {ACC1:slc#88.itm(2)} -attr vt d
+load netBundle {ACC1:slc#88.itm} 3 {ACC1:slc#88.itm(0)} {ACC1:slc#88.itm(1)} {ACC1:slc#88.itm(2)} -attr xrf 24868 -attr oid 164 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#301.itm(0)} -attr vt d
+load net {ACC1:acc#301.itm(1)} -attr vt d
+load net {ACC1:acc#301.itm(2)} -attr vt d
+load net {ACC1:acc#301.itm(3)} -attr vt d
+load netBundle {ACC1:acc#301.itm} 4 {ACC1:acc#301.itm(0)} {ACC1:acc#301.itm(1)} {ACC1:acc#301.itm(2)} {ACC1:acc#301.itm(3)} -attr xrf 24869 -attr oid 165 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {exs#32.itm(0)} -attr vt d
+load net {exs#32.itm(1)} -attr vt d
+load net {exs#32.itm(2)} -attr vt d
+load netBundle {exs#32.itm} 3 {exs#32.itm(0)} {exs#32.itm(1)} {exs#32.itm(2)} -attr xrf 24870 -attr oid 166 -attr vt d -attr @path {/sobel/sobel:core/exs#32.itm}
+load net {conc#602.itm(0)} -attr vt d
+load net {conc#602.itm(1)} -attr vt d
+load netBundle {conc#602.itm} 2 {conc#602.itm(0)} {conc#602.itm(1)} -attr xrf 24871 -attr oid 167 -attr vt d -attr @path {/sobel/sobel:core/conc#602.itm}
+load net {ACC1:exs#809.itm(0)} -attr vt d
+load net {ACC1:exs#809.itm(1)} -attr vt d
+load net {ACC1:exs#809.itm(2)} -attr vt d
+load netBundle {ACC1:exs#809.itm} 3 {ACC1:exs#809.itm(0)} {ACC1:exs#809.itm(1)} {ACC1:exs#809.itm(2)} -attr xrf 24872 -attr oid 168 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#809.itm}
+load net {ACC1:conc#624.itm(0)} -attr vt d
+load net {ACC1:conc#624.itm(1)} -attr vt d
+load netBundle {ACC1:conc#624.itm} 2 {ACC1:conc#624.itm(0)} {ACC1:conc#624.itm(1)} -attr xrf 24873 -attr oid 169 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#624.itm}
+load net {ACC1:slc#87.itm(0)} -attr vt d
+load net {ACC1:slc#87.itm(1)} -attr vt d
+load net {ACC1:slc#87.itm(2)} -attr vt d
+load netBundle {ACC1:slc#87.itm} 3 {ACC1:slc#87.itm(0)} {ACC1:slc#87.itm(1)} {ACC1:slc#87.itm(2)} -attr xrf 24874 -attr oid 170 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#87.itm}
+load net {ACC1:acc#300.itm(0)} -attr vt d
+load net {ACC1:acc#300.itm(1)} -attr vt d
+load net {ACC1:acc#300.itm(2)} -attr vt d
+load net {ACC1:acc#300.itm(3)} -attr vt d
+load netBundle {ACC1:acc#300.itm} 4 {ACC1:acc#300.itm(0)} {ACC1:acc#300.itm(1)} {ACC1:acc#300.itm(2)} {ACC1:acc#300.itm(3)} -attr xrf 24875 -attr oid 171 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {exs#33.itm(0)} -attr vt d
+load net {exs#33.itm(1)} -attr vt d
+load net {exs#33.itm(2)} -attr vt d
+load netBundle {exs#33.itm} 3 {exs#33.itm(0)} {exs#33.itm(1)} {exs#33.itm(2)} -attr xrf 24876 -attr oid 172 -attr vt d -attr @path {/sobel/sobel:core/exs#33.itm}
+load net {conc#603.itm(0)} -attr vt d
+load net {conc#603.itm(1)} -attr vt d
+load netBundle {conc#603.itm} 2 {conc#603.itm(0)} {conc#603.itm(1)} -attr xrf 24877 -attr oid 173 -attr vt d -attr @path {/sobel/sobel:core/conc#603.itm}
+load net {ACC1:exs#811.itm(0)} -attr vt d
+load net {ACC1:exs#811.itm(1)} -attr vt d
+load net {ACC1:exs#811.itm(2)} -attr vt d
+load netBundle {ACC1:exs#811.itm} 3 {ACC1:exs#811.itm(0)} {ACC1:exs#811.itm(1)} {ACC1:exs#811.itm(2)} -attr xrf 24878 -attr oid 174 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#811.itm}
+load net {slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#6.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#6.itm} 2 {slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#6.itm(0)} {slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#6.itm(1)} -attr xrf 24879 -attr oid 175 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#6.itm}
+load net {ACC1:acc#314.itm(0)} -attr vt d
+load net {ACC1:acc#314.itm(1)} -attr vt d
+load net {ACC1:acc#314.itm(2)} -attr vt d
+load net {ACC1:acc#314.itm(3)} -attr vt d
+load netBundle {ACC1:acc#314.itm} 4 {ACC1:acc#314.itm(0)} {ACC1:acc#314.itm(1)} {ACC1:acc#314.itm(2)} {ACC1:acc#314.itm(3)} -attr xrf 24880 -attr oid 176 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:slc#86.itm(0)} -attr vt d
+load net {ACC1:slc#86.itm(1)} -attr vt d
+load net {ACC1:slc#86.itm(2)} -attr vt d
+load netBundle {ACC1:slc#86.itm} 3 {ACC1:slc#86.itm(0)} {ACC1:slc#86.itm(1)} {ACC1:slc#86.itm(2)} -attr xrf 24881 -attr oid 177 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#86.itm}
+load net {ACC1:acc#299.itm(0)} -attr vt d
+load net {ACC1:acc#299.itm(1)} -attr vt d
+load net {ACC1:acc#299.itm(2)} -attr vt d
+load net {ACC1:acc#299.itm(3)} -attr vt d
+load netBundle {ACC1:acc#299.itm} 4 {ACC1:acc#299.itm(0)} {ACC1:acc#299.itm(1)} {ACC1:acc#299.itm(2)} {ACC1:acc#299.itm(3)} -attr xrf 24882 -attr oid 178 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {exs#34.itm(0)} -attr vt d
+load net {exs#34.itm(1)} -attr vt d
+load net {exs#34.itm(2)} -attr vt d
+load netBundle {exs#34.itm} 3 {exs#34.itm(0)} {exs#34.itm(1)} {exs#34.itm(2)} -attr xrf 24883 -attr oid 179 -attr vt d -attr @path {/sobel/sobel:core/exs#34.itm}
+load net {conc#604.itm(0)} -attr vt d
+load net {conc#604.itm(1)} -attr vt d
+load netBundle {conc#604.itm} 2 {conc#604.itm(0)} {conc#604.itm(1)} -attr xrf 24884 -attr oid 180 -attr vt d -attr @path {/sobel/sobel:core/conc#604.itm}
+load net {ACC1:exs#813.itm(0)} -attr vt d
+load net {ACC1:exs#813.itm(1)} -attr vt d
+load net {ACC1:exs#813.itm(2)} -attr vt d
+load netBundle {ACC1:exs#813.itm} 3 {ACC1:exs#813.itm(0)} {ACC1:exs#813.itm(1)} {ACC1:exs#813.itm(2)} -attr xrf 24885 -attr oid 181 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#813.itm}
+load net {ACC1:conc#620.itm(0)} -attr vt d
+load net {ACC1:conc#620.itm(1)} -attr vt d
+load netBundle {ACC1:conc#620.itm} 2 {ACC1:conc#620.itm(0)} {ACC1:conc#620.itm(1)} -attr xrf 24886 -attr oid 182 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#620.itm}
+load net {ACC1:slc#85.itm(0)} -attr vt d
+load net {ACC1:slc#85.itm(1)} -attr vt d
+load net {ACC1:slc#85.itm(2)} -attr vt d
+load netBundle {ACC1:slc#85.itm} 3 {ACC1:slc#85.itm(0)} {ACC1:slc#85.itm(1)} {ACC1:slc#85.itm(2)} -attr xrf 24887 -attr oid 183 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#85.itm}
+load net {ACC1:acc#298.itm(0)} -attr vt d
+load net {ACC1:acc#298.itm(1)} -attr vt d
+load net {ACC1:acc#298.itm(2)} -attr vt d
+load net {ACC1:acc#298.itm(3)} -attr vt d
+load netBundle {ACC1:acc#298.itm} 4 {ACC1:acc#298.itm(0)} {ACC1:acc#298.itm(1)} {ACC1:acc#298.itm(2)} {ACC1:acc#298.itm(3)} -attr xrf 24888 -attr oid 184 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {exs#57.itm(0)} -attr vt d
+load net {exs#57.itm(1)} -attr vt d
+load net {exs#57.itm(2)} -attr vt d
+load netBundle {exs#57.itm} 3 {exs#57.itm(0)} {exs#57.itm(1)} {exs#57.itm(2)} -attr xrf 24889 -attr oid 185 -attr vt d -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {conc#605.itm(0)} -attr vt d
+load net {conc#605.itm(1)} -attr vt d
+load netBundle {conc#605.itm} 2 {conc#605.itm(0)} {conc#605.itm(1)} -attr xrf 24890 -attr oid 186 -attr vt d -attr @path {/sobel/sobel:core/conc#605.itm}
+load net {ACC1:exs#815.itm(0)} -attr vt d
+load net {ACC1:exs#815.itm(1)} -attr vt d
+load net {ACC1:exs#815.itm(2)} -attr vt d
+load netBundle {ACC1:exs#815.itm} 3 {ACC1:exs#815.itm(0)} {ACC1:exs#815.itm(1)} {ACC1:exs#815.itm(2)} -attr xrf 24891 -attr oid 187 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#815.itm}
+load net {ACC1:conc#618.itm(0)} -attr vt d
+load net {ACC1:conc#618.itm(1)} -attr vt d
+load netBundle {ACC1:conc#618.itm} 2 {ACC1:conc#618.itm(0)} {ACC1:conc#618.itm(1)} -attr xrf 24892 -attr oid 188 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#618.itm}
+load net {ACC1:acc#322.itm(0)} -attr vt d
+load net {ACC1:acc#322.itm(1)} -attr vt d
+load net {ACC1:acc#322.itm(2)} -attr vt d
+load net {ACC1:acc#322.itm(3)} -attr vt d
+load net {ACC1:acc#322.itm(4)} -attr vt d
+load netBundle {ACC1:acc#322.itm} 5 {ACC1:acc#322.itm(0)} {ACC1:acc#322.itm(1)} {ACC1:acc#322.itm(2)} {ACC1:acc#322.itm(3)} {ACC1:acc#322.itm(4)} -attr xrf 24893 -attr oid 189 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#313.itm(0)} -attr vt d
+load net {ACC1:acc#313.itm(1)} -attr vt d
+load net {ACC1:acc#313.itm(2)} -attr vt d
+load net {ACC1:acc#313.itm(3)} -attr vt d
+load netBundle {ACC1:acc#313.itm} 4 {ACC1:acc#313.itm(0)} {ACC1:acc#313.itm(1)} {ACC1:acc#313.itm(2)} {ACC1:acc#313.itm(3)} -attr xrf 24894 -attr oid 190 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:slc#84.itm(0)} -attr vt d
+load net {ACC1:slc#84.itm(1)} -attr vt d
+load net {ACC1:slc#84.itm(2)} -attr vt d
+load netBundle {ACC1:slc#84.itm} 3 {ACC1:slc#84.itm(0)} {ACC1:slc#84.itm(1)} {ACC1:slc#84.itm(2)} -attr xrf 24895 -attr oid 191 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#84.itm}
+load net {ACC1:acc#297.itm(0)} -attr vt d
+load net {ACC1:acc#297.itm(1)} -attr vt d
+load net {ACC1:acc#297.itm(2)} -attr vt d
+load net {ACC1:acc#297.itm(3)} -attr vt d
+load netBundle {ACC1:acc#297.itm} 4 {ACC1:acc#297.itm(0)} {ACC1:acc#297.itm(1)} {ACC1:acc#297.itm(2)} {ACC1:acc#297.itm(3)} -attr xrf 24896 -attr oid 192 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {exs#35.itm(0)} -attr vt d
+load net {exs#35.itm(1)} -attr vt d
+load net {exs#35.itm(2)} -attr vt d
+load netBundle {exs#35.itm} 3 {exs#35.itm(0)} {exs#35.itm(1)} {exs#35.itm(2)} -attr xrf 24897 -attr oid 193 -attr vt d -attr @path {/sobel/sobel:core/exs#35.itm}
+load net {conc#607.itm(0)} -attr vt d
+load net {conc#607.itm(1)} -attr vt d
+load netBundle {conc#607.itm} 2 {conc#607.itm(0)} {conc#607.itm(1)} -attr xrf 24898 -attr oid 194 -attr vt d -attr @path {/sobel/sobel:core/conc#607.itm}
+load net {ACC1:exs#817.itm(0)} -attr vt d
+load net {ACC1:exs#817.itm(1)} -attr vt d
+load net {ACC1:exs#817.itm(2)} -attr vt d
+load netBundle {ACC1:exs#817.itm} 3 {ACC1:exs#817.itm(0)} {ACC1:exs#817.itm(1)} {ACC1:exs#817.itm(2)} -attr xrf 24899 -attr oid 195 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#817.itm}
+load net {ACC1:conc#616.itm(0)} -attr vt d
+load net {ACC1:conc#616.itm(1)} -attr vt d
+load netBundle {ACC1:conc#616.itm} 2 {ACC1:conc#616.itm(0)} {ACC1:conc#616.itm(1)} -attr xrf 24900 -attr oid 196 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#616.itm}
+load net {ACC1:slc#83.itm(0)} -attr vt d
+load net {ACC1:slc#83.itm(1)} -attr vt d
+load net {ACC1:slc#83.itm(2)} -attr vt d
+load netBundle {ACC1:slc#83.itm} 3 {ACC1:slc#83.itm(0)} {ACC1:slc#83.itm(1)} {ACC1:slc#83.itm(2)} -attr xrf 24901 -attr oid 197 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#83.itm}
+load net {ACC1:acc#296.itm(0)} -attr vt d
+load net {ACC1:acc#296.itm(1)} -attr vt d
+load net {ACC1:acc#296.itm(2)} -attr vt d
+load net {ACC1:acc#296.itm(3)} -attr vt d
+load netBundle {ACC1:acc#296.itm} 4 {ACC1:acc#296.itm(0)} {ACC1:acc#296.itm(1)} {ACC1:acc#296.itm(2)} {ACC1:acc#296.itm(3)} -attr xrf 24902 -attr oid 198 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {exs#36.itm(0)} -attr vt d
+load net {exs#36.itm(1)} -attr vt d
+load net {exs#36.itm(2)} -attr vt d
+load netBundle {exs#36.itm} 3 {exs#36.itm(0)} {exs#36.itm(1)} {exs#36.itm(2)} -attr xrf 24903 -attr oid 199 -attr vt d -attr @path {/sobel/sobel:core/exs#36.itm}
+load net {conc#608.itm(0)} -attr vt d
+load net {conc#608.itm(1)} -attr vt d
+load netBundle {conc#608.itm} 2 {conc#608.itm(0)} {conc#608.itm(1)} -attr xrf 24904 -attr oid 200 -attr vt d -attr @path {/sobel/sobel:core/conc#608.itm}
+load net {ACC1:exs#819.itm(0)} -attr vt d
+load net {ACC1:exs#819.itm(1)} -attr vt d
+load net {ACC1:exs#819.itm(2)} -attr vt d
+load netBundle {ACC1:exs#819.itm} 3 {ACC1:exs#819.itm(0)} {ACC1:exs#819.itm(1)} {ACC1:exs#819.itm(2)} -attr xrf 24905 -attr oid 201 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#819.itm}
+load net {ACC1:conc#614.itm(0)} -attr vt d
+load net {ACC1:conc#614.itm(1)} -attr vt d
+load netBundle {ACC1:conc#614.itm} 2 {ACC1:conc#614.itm(0)} {ACC1:conc#614.itm(1)} -attr xrf 24906 -attr oid 202 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#614.itm}
+load net {ACC1:slc#99.itm(0)} -attr vt d
+load net {ACC1:slc#99.itm(1)} -attr vt d
+load net {ACC1:slc#99.itm(2)} -attr vt d
+load net {ACC1:slc#99.itm(3)} -attr vt d
+load netBundle {ACC1:slc#99.itm} 4 {ACC1:slc#99.itm(0)} {ACC1:slc#99.itm(1)} {ACC1:slc#99.itm(2)} {ACC1:slc#99.itm(3)} -attr xrf 24907 -attr oid 203 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#312.itm(0)} -attr vt d
+load net {ACC1:acc#312.itm(1)} -attr vt d
+load net {ACC1:acc#312.itm(2)} -attr vt d
+load net {ACC1:acc#312.itm(3)} -attr vt d
+load net {ACC1:acc#312.itm(4)} -attr vt d
+load netBundle {ACC1:acc#312.itm} 5 {ACC1:acc#312.itm(0)} {ACC1:acc#312.itm(1)} {ACC1:acc#312.itm(2)} {ACC1:acc#312.itm(3)} {ACC1:acc#312.itm(4)} -attr xrf 24908 -attr oid 204 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {conc#609.itm(0)} -attr vt d
+load net {conc#609.itm(1)} -attr vt d
+load net {conc#609.itm(2)} -attr vt d
+load net {conc#609.itm(3)} -attr vt d
+load netBundle {conc#609.itm} 4 {conc#609.itm(0)} {conc#609.itm(1)} {conc#609.itm(2)} {conc#609.itm(3)} -attr xrf 24909 -attr oid 205 -attr vt d -attr @path {/sobel/sobel:core/conc#609.itm}
+load net {ACC1:slc#82.itm(0)} -attr vt d
+load net {ACC1:slc#82.itm(1)} -attr vt d
+load net {ACC1:slc#82.itm(2)} -attr vt d
+load netBundle {ACC1:slc#82.itm} 3 {ACC1:slc#82.itm(0)} {ACC1:slc#82.itm(1)} {ACC1:slc#82.itm(2)} -attr xrf 24910 -attr oid 206 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#82.itm}
+load net {ACC1:acc#295.itm(0)} -attr vt d
+load net {ACC1:acc#295.itm(1)} -attr vt d
+load net {ACC1:acc#295.itm(2)} -attr vt d
+load net {ACC1:acc#295.itm(3)} -attr vt d
+load netBundle {ACC1:acc#295.itm} 4 {ACC1:acc#295.itm(0)} {ACC1:acc#295.itm(1)} {ACC1:acc#295.itm(2)} {ACC1:acc#295.itm(3)} -attr xrf 24911 -attr oid 207 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {conc#610.itm(0)} -attr vt d
+load net {conc#610.itm(1)} -attr vt d
+load net {conc#610.itm(2)} -attr vt d
+load netBundle {conc#610.itm} 3 {conc#610.itm(0)} {conc#610.itm(1)} {conc#610.itm(2)} -attr xrf 24912 -attr oid 208 -attr vt d -attr @path {/sobel/sobel:core/conc#610.itm}
+load net {ACC1:conc#612.itm(0)} -attr vt d
+load net {ACC1:conc#612.itm(1)} -attr vt d
+load net {ACC1:conc#612.itm(2)} -attr vt d
+load netBundle {ACC1:conc#612.itm} 3 {ACC1:conc#612.itm(0)} {ACC1:conc#612.itm(1)} {ACC1:conc#612.itm(2)} -attr xrf 24913 -attr oid 209 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#612.itm}
+load net {conc#611.itm(0)} -attr vt d
+load net {conc#611.itm(1)} -attr vt d
+load net {conc#611.itm(2)} -attr vt d
+load net {conc#611.itm(3)} -attr vt d
+load netBundle {conc#611.itm} 4 {conc#611.itm(0)} {conc#611.itm(1)} {conc#611.itm(2)} {conc#611.itm(3)} -attr xrf 24914 -attr oid 210 -attr vt d -attr @path {/sobel/sobel:core/conc#611.itm}
+load net {ACC1:acc#321.itm(0)} -attr vt d
+load net {ACC1:acc#321.itm(1)} -attr vt d
+load net {ACC1:acc#321.itm(2)} -attr vt d
+load net {ACC1:acc#321.itm(3)} -attr vt d
+load netBundle {ACC1:acc#321.itm} 4 {ACC1:acc#321.itm(0)} {ACC1:acc#321.itm(1)} {ACC1:acc#321.itm(2)} {ACC1:acc#321.itm(3)} -attr xrf 24915 -attr oid 211 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:slc#98.itm(0)} -attr vt d
+load net {ACC1:slc#98.itm(1)} -attr vt d
+load net {ACC1:slc#98.itm(2)} -attr vt d
+load net {ACC1:slc#98.itm(3)} -attr vt d
+load netBundle {ACC1:slc#98.itm} 4 {ACC1:slc#98.itm(0)} {ACC1:slc#98.itm(1)} {ACC1:slc#98.itm(2)} {ACC1:slc#98.itm(3)} -attr xrf 24916 -attr oid 212 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#311.itm(0)} -attr vt d
+load net {ACC1:acc#311.itm(1)} -attr vt d
+load net {ACC1:acc#311.itm(2)} -attr vt d
+load net {ACC1:acc#311.itm(3)} -attr vt d
+load net {ACC1:acc#311.itm(4)} -attr vt d
+load netBundle {ACC1:acc#311.itm} 5 {ACC1:acc#311.itm(0)} {ACC1:acc#311.itm(1)} {ACC1:acc#311.itm(2)} {ACC1:acc#311.itm(3)} {ACC1:acc#311.itm(4)} -attr xrf 24917 -attr oid 213 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {conc#612.itm(0)} -attr vt d
+load net {conc#612.itm(1)} -attr vt d
+load net {conc#612.itm(2)} -attr vt d
+load net {conc#612.itm(3)} -attr vt d
+load netBundle {conc#612.itm} 4 {conc#612.itm(0)} {conc#612.itm(1)} {conc#612.itm(2)} {conc#612.itm(3)} -attr xrf 24918 -attr oid 214 -attr vt d -attr @path {/sobel/sobel:core/conc#612.itm}
+load net {ACC1:conc#644.itm(0)} -attr vt d
+load net {ACC1:conc#644.itm(1)} -attr vt d
+load net {ACC1:conc#644.itm(2)} -attr vt d
+load netBundle {ACC1:conc#644.itm} 3 {ACC1:conc#644.itm(0)} {ACC1:conc#644.itm(1)} {ACC1:conc#644.itm(2)} -attr xrf 24919 -attr oid 215 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#644.itm}
+load net {ACC1:slc#95.itm(0)} -attr vt d
+load net {ACC1:slc#95.itm(1)} -attr vt d
+load net {ACC1:slc#95.itm(2)} -attr vt d
+load net {ACC1:slc#95.itm(3)} -attr vt d
+load netBundle {ACC1:slc#95.itm} 4 {ACC1:slc#95.itm(0)} {ACC1:slc#95.itm(1)} {ACC1:slc#95.itm(2)} {ACC1:slc#95.itm(3)} -attr xrf 24920 -attr oid 216 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#308.itm(0)} -attr vt d
+load net {ACC1:acc#308.itm(1)} -attr vt d
+load net {ACC1:acc#308.itm(2)} -attr vt d
+load net {ACC1:acc#308.itm(3)} -attr vt d
+load net {ACC1:acc#308.itm(4)} -attr vt d
+load netBundle {ACC1:acc#308.itm} 5 {ACC1:acc#308.itm(0)} {ACC1:acc#308.itm(1)} {ACC1:acc#308.itm(2)} {ACC1:acc#308.itm(3)} {ACC1:acc#308.itm(4)} -attr xrf 24921 -attr oid 217 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {exs#37.itm(0)} -attr vt d
+load net {exs#37.itm(1)} -attr vt d
+load net {exs#37.itm(2)} -attr vt d
+load netBundle {exs#37.itm} 3 {exs#37.itm(0)} {exs#37.itm(1)} {exs#37.itm(2)} -attr xrf 24922 -attr oid 218 -attr vt d -attr @path {/sobel/sobel:core/exs#37.itm}
+load net {conc#613.itm(0)} -attr vt d
+load net {conc#613.itm(1)} -attr vt d
+load netBundle {conc#613.itm} 2 {conc#613.itm(0)} {conc#613.itm(1)} -attr xrf 24923 -attr oid 219 -attr vt d -attr @path {/sobel/sobel:core/conc#613.itm}
+load net {ACC1:conc#638.itm(0)} -attr vt d
+load net {ACC1:conc#638.itm(1)} -attr vt d
+load net {ACC1:conc#638.itm(2)} -attr vt d
+load netBundle {ACC1:conc#638.itm} 3 {ACC1:conc#638.itm(0)} {ACC1:conc#638.itm(1)} {ACC1:conc#638.itm(2)} -attr xrf 24924 -attr oid 220 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#638.itm}
+load net {ACC1:acc#339.itm(0)} -attr vt d
+load net {ACC1:acc#339.itm(1)} -attr vt d
+load net {ACC1:acc#339.itm(2)} -attr vt d
+load net {ACC1:acc#339.itm(3)} -attr vt d
+load net {ACC1:acc#339.itm(4)} -attr vt d
+load net {ACC1:acc#339.itm(5)} -attr vt d
+load net {ACC1:acc#339.itm(6)} -attr vt d
+load net {ACC1:acc#339.itm(7)} -attr vt d
+load net {ACC1:acc#339.itm(8)} -attr vt d
+load net {ACC1:acc#339.itm(9)} -attr vt d
+load net {ACC1:acc#339.itm(10)} -attr vt d
+load net {ACC1:acc#339.itm(11)} -attr vt d
+load net {ACC1:acc#339.itm(12)} -attr vt d
+load netBundle {ACC1:acc#339.itm} 13 {ACC1:acc#339.itm(0)} {ACC1:acc#339.itm(1)} {ACC1:acc#339.itm(2)} {ACC1:acc#339.itm(3)} {ACC1:acc#339.itm(4)} {ACC1:acc#339.itm(5)} {ACC1:acc#339.itm(6)} {ACC1:acc#339.itm(7)} {ACC1:acc#339.itm(8)} {ACC1:acc#339.itm(9)} {ACC1:acc#339.itm(10)} {ACC1:acc#339.itm(11)} {ACC1:acc#339.itm(12)} -attr xrf 24925 -attr oid 221 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#337.itm(0)} -attr vt d
+load net {ACC1:acc#337.itm(1)} -attr vt d
+load net {ACC1:acc#337.itm(2)} -attr vt d
+load net {ACC1:acc#337.itm(3)} -attr vt d
+load net {ACC1:acc#337.itm(4)} -attr vt d
+load net {ACC1:acc#337.itm(5)} -attr vt d
+load net {ACC1:acc#337.itm(6)} -attr vt d
+load net {ACC1:acc#337.itm(7)} -attr vt d
+load net {ACC1:acc#337.itm(8)} -attr vt d
+load net {ACC1:acc#337.itm(9)} -attr vt d
+load net {ACC1:acc#337.itm(10)} -attr vt d
+load netBundle {ACC1:acc#337.itm} 11 {ACC1:acc#337.itm(0)} {ACC1:acc#337.itm(1)} {ACC1:acc#337.itm(2)} {ACC1:acc#337.itm(3)} {ACC1:acc#337.itm(4)} {ACC1:acc#337.itm(5)} {ACC1:acc#337.itm(6)} {ACC1:acc#337.itm(7)} {ACC1:acc#337.itm(8)} {ACC1:acc#337.itm(9)} {ACC1:acc#337.itm(10)} -attr xrf 24926 -attr oid 222 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:mul#19.itm(0)} -attr vt d
+load net {ACC1:mul#19.itm(1)} -attr vt d
+load net {ACC1:mul#19.itm(2)} -attr vt d
+load net {ACC1:mul#19.itm(3)} -attr vt d
+load net {ACC1:mul#19.itm(4)} -attr vt d
+load net {ACC1:mul#19.itm(5)} -attr vt d
+load net {ACC1:mul#19.itm(6)} -attr vt d
+load net {ACC1:mul#19.itm(7)} -attr vt d
+load net {ACC1:mul#19.itm(8)} -attr vt d
+load net {ACC1:mul#19.itm(9)} -attr vt d
+load netBundle {ACC1:mul#19.itm} 10 {ACC1:mul#19.itm(0)} {ACC1:mul#19.itm(1)} {ACC1:mul#19.itm(2)} {ACC1:mul#19.itm(3)} {ACC1:mul#19.itm(4)} {ACC1:mul#19.itm(5)} {ACC1:mul#19.itm(6)} {ACC1:mul#19.itm(7)} {ACC1:mul#19.itm(8)} {ACC1:mul#19.itm(9)} -attr xrf 24927 -attr oid 223 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC2:acc#4.itm(0)} -attr vt d
+load net {ACC2:acc#4.itm(1)} -attr vt d
+load netBundle {ACC2:acc#4.itm} 2 {ACC2:acc#4.itm(0)} {ACC2:acc#4.itm(1)} -attr xrf 24928 -attr oid 224 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#4.itm}
+load net {ACC1:acc#333.itm(0)} -attr vt d
+load net {ACC1:acc#333.itm(1)} -attr vt d
+load net {ACC1:acc#333.itm(2)} -attr vt d
+load net {ACC1:acc#333.itm(3)} -attr vt d
+load net {ACC1:acc#333.itm(4)} -attr vt d
+load net {ACC1:acc#333.itm(5)} -attr vt d
+load net {ACC1:acc#333.itm(6)} -attr vt d
+load net {ACC1:acc#333.itm(7)} -attr vt d
+load net {ACC1:acc#333.itm(8)} -attr vt d
+load netBundle {ACC1:acc#333.itm} 9 {ACC1:acc#333.itm(0)} {ACC1:acc#333.itm(1)} {ACC1:acc#333.itm(2)} {ACC1:acc#333.itm(3)} {ACC1:acc#333.itm(4)} {ACC1:acc#333.itm(5)} {ACC1:acc#333.itm(6)} {ACC1:acc#333.itm(7)} {ACC1:acc#333.itm(8)} -attr xrf 24929 -attr oid 225 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#329.itm(0)} -attr vt d
+load net {ACC1:acc#329.itm(1)} -attr vt d
+load net {ACC1:acc#329.itm(2)} -attr vt d
+load net {ACC1:acc#329.itm(3)} -attr vt d
+load net {ACC1:acc#329.itm(4)} -attr vt d
+load net {ACC1:acc#329.itm(5)} -attr vt d
+load net {ACC1:acc#329.itm(6)} -attr vt d
+load netBundle {ACC1:acc#329.itm} 7 {ACC1:acc#329.itm(0)} {ACC1:acc#329.itm(1)} {ACC1:acc#329.itm(2)} {ACC1:acc#329.itm(3)} {ACC1:acc#329.itm(4)} {ACC1:acc#329.itm(5)} {ACC1:acc#329.itm(6)} -attr xrf 24930 -attr oid 226 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {conc#614.itm(0)} -attr vt d
+load net {conc#614.itm(1)} -attr vt d
+load net {conc#614.itm(2)} -attr vt d
+load net {conc#614.itm(3)} -attr vt d
+load net {conc#614.itm(4)} -attr vt d
+load net {conc#614.itm(5)} -attr vt d
+load netBundle {conc#614.itm} 6 {conc#614.itm(0)} {conc#614.itm(1)} {conc#614.itm(2)} {conc#614.itm(3)} {conc#614.itm(4)} {conc#614.itm(5)} -attr xrf 24931 -attr oid 227 -attr vt d -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {ACC1-3:exs#570.itm(0)} -attr vt d
+load net {ACC1-3:exs#570.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#570.itm} 2 {ACC1-3:exs#570.itm(0)} {ACC1-3:exs#570.itm(1)} -attr xrf 24932 -attr oid 228 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#570.itm}
+load net {ACC1:acc#326.itm(0)} -attr vt d
+load net {ACC1:acc#326.itm(1)} -attr vt d
+load net {ACC1:acc#326.itm(2)} -attr vt d
+load net {ACC1:acc#326.itm(3)} -attr vt d
+load net {ACC1:acc#326.itm(4)} -attr vt d
+load netBundle {ACC1:acc#326.itm} 5 {ACC1:acc#326.itm(0)} {ACC1:acc#326.itm(1)} {ACC1:acc#326.itm(2)} {ACC1:acc#326.itm(3)} {ACC1:acc#326.itm(4)} -attr xrf 24933 -attr oid 229 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:conc#657.itm(0)} -attr vt d
+load net {ACC1:conc#657.itm(1)} -attr vt d
+load net {ACC1:conc#657.itm(2)} -attr vt d
+load net {ACC1:conc#657.itm(3)} -attr vt d
+load net {ACC1:conc#657.itm(4)} -attr vt d
+load netBundle {ACC1:conc#657.itm} 5 {ACC1:conc#657.itm(0)} {ACC1:conc#657.itm(1)} {ACC1:conc#657.itm(2)} {ACC1:conc#657.itm(3)} {ACC1:conc#657.itm(4)} -attr xrf 24934 -attr oid 230 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#657.itm}
+load net {ACC1:acc#347.itm(0)} -attr vt d
+load net {ACC1:acc#347.itm(1)} -attr vt d
+load netBundle {ACC1:acc#347.itm} 2 {ACC1:acc#347.itm(0)} {ACC1:acc#347.itm(1)} -attr xrf 24935 -attr oid 231 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load net {ACC1:acc#348.itm(0)} -attr vt d
+load net {ACC1:acc#348.itm(1)} -attr vt d
+load net {ACC1:acc#348.itm(2)} -attr vt d
+load netBundle {ACC1:acc#348.itm} 3 {ACC1:acc#348.itm(0)} {ACC1:acc#348.itm(1)} {ACC1:acc#348.itm(2)} -attr xrf 24936 -attr oid 232 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {ACC2:exs.itm(0)} -attr vt d
+load net {ACC2:exs.itm(1)} -attr vt d
+load netBundle {ACC2:exs.itm} 2 {ACC2:exs.itm(0)} {ACC2:exs.itm(1)} -attr xrf 24937 -attr oid 233 -attr vt d -attr @path {/sobel/sobel:core/ACC2:exs.itm}
+load net {ACC2:exs#1.itm(0)} -attr vt d
+load net {ACC2:exs#1.itm(1)} -attr vt d
+load netBundle {ACC2:exs#1.itm} 2 {ACC2:exs#1.itm(0)} {ACC2:exs#1.itm(1)} -attr xrf 24938 -attr oid 234 -attr vt d -attr @path {/sobel/sobel:core/ACC2:exs#1.itm}
+load net {conc#615.itm(0)} -attr vt d
+load net {conc#615.itm(1)} -attr vt d
+load net {conc#615.itm(2)} -attr vt d
+load net {conc#615.itm(3)} -attr vt d
+load net {conc#615.itm(4)} -attr vt d
+load netBundle {conc#615.itm} 5 {conc#615.itm(0)} {conc#615.itm(1)} {conc#615.itm(2)} {conc#615.itm(3)} {conc#615.itm(4)} -attr xrf 24939 -attr oid 235 -attr vt d -attr @path {/sobel/sobel:core/conc#615.itm}
+load net {ACC1-3:exs#566.itm(0)} -attr vt d
+load net {ACC1-3:exs#566.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#566.itm} 2 {ACC1-3:exs#566.itm(0)} {ACC1-3:exs#566.itm(1)} -attr xrf 24940 -attr oid 236 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#566.itm}
+load net {ACC1-3:exs#541.itm(0)} -attr vt d
+load net {ACC1-3:exs#541.itm(1)} -attr vt d
+load net {ACC1-3:exs#541.itm(2)} -attr vt d
+load net {ACC1-3:exs#541.itm(3)} -attr vt d
+load net {ACC1-3:exs#541.itm(4)} -attr vt d
+load net {ACC1-3:exs#541.itm(5)} -attr vt d
+load net {ACC1-3:exs#541.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#541.itm} 7 {ACC1-3:exs#541.itm(0)} {ACC1-3:exs#541.itm(1)} {ACC1-3:exs#541.itm(2)} {ACC1-3:exs#541.itm(3)} {ACC1-3:exs#541.itm(4)} {ACC1-3:exs#541.itm(5)} {ACC1-3:exs#541.itm(6)} -attr xrf 24941 -attr oid 237 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1-3:conc#240.itm(0)} -attr vt d
+load net {ACC1-3:conc#240.itm(1)} -attr vt d
+load net {ACC1-3:conc#240.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#240.itm} 3 {ACC1-3:conc#240.itm(0)} {ACC1-3:conc#240.itm(1)} {ACC1-3:conc#240.itm(2)} -attr xrf 24942 -attr oid 238 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#240.itm}
+load net {ACC1-3:exs#567.itm(0)} -attr vt d
+load net {ACC1-3:exs#567.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#567.itm} 2 {ACC1-3:exs#567.itm(0)} {ACC1-3:exs#567.itm(1)} -attr xrf 24943 -attr oid 239 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#567.itm}
+load net {ACC1:conc#441.itm(0)} -attr vt d
+load net {ACC1:conc#441.itm(1)} -attr vt d
+load net {ACC1:conc#441.itm(2)} -attr vt d
+load net {ACC1:conc#441.itm(3)} -attr vt d
+load net {ACC1:conc#441.itm(4)} -attr vt d
+load net {ACC1:conc#441.itm(5)} -attr vt d
+load net {ACC1:conc#441.itm(6)} -attr vt d
+load net {ACC1:conc#441.itm(7)} -attr vt d
+load net {ACC1:conc#441.itm(8)} -attr vt d
+load net {ACC1:conc#441.itm(9)} -attr vt d
+load net {ACC1:conc#441.itm(10)} -attr vt d
+load netBundle {ACC1:conc#441.itm} 11 {ACC1:conc#441.itm(0)} {ACC1:conc#441.itm(1)} {ACC1:conc#441.itm(2)} {ACC1:conc#441.itm(3)} {ACC1:conc#441.itm(4)} {ACC1:conc#441.itm(5)} {ACC1:conc#441.itm(6)} {ACC1:conc#441.itm(7)} {ACC1:conc#441.itm(8)} {ACC1:conc#441.itm(9)} {ACC1:conc#441.itm(10)} -attr xrf 24944 -attr oid 240 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(0)} -attr vt d
+load net {ACC1:mul#22.itm(1)} -attr vt d
+load net {ACC1:mul#22.itm(2)} -attr vt d
+load net {ACC1:mul#22.itm(3)} -attr vt d
+load net {ACC1:mul#22.itm(4)} -attr vt d
+load net {ACC1:mul#22.itm(5)} -attr vt d
+load net {ACC1:mul#22.itm(6)} -attr vt d
+load net {ACC1:mul#22.itm(7)} -attr vt d
+load netBundle {ACC1:mul#22.itm} 8 {ACC1:mul#22.itm(0)} {ACC1:mul#22.itm(1)} {ACC1:mul#22.itm(2)} {ACC1:mul#22.itm(3)} {ACC1:mul#22.itm(4)} {ACC1:mul#22.itm(5)} {ACC1:mul#22.itm(6)} {ACC1:mul#22.itm(7)} -attr xrf 24945 -attr oid 241 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC2:acc#7.itm(0)} -attr vt d
+load net {ACC2:acc#7.itm(1)} -attr vt d
+load netBundle {ACC2:acc#7.itm} 2 {ACC2:acc#7.itm(0)} {ACC2:acc#7.itm(1)} -attr xrf 24946 -attr oid 242 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC1-3:exs#553.itm(0)} -attr vt d
+load net {ACC1-3:exs#553.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#553.itm} 2 {ACC1-3:exs#553.itm(0)} {ACC1-3:exs#553.itm(1)} -attr xrf 24947 -attr oid 243 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#553.itm}
+load net {mux#2.itm(0)} -attr vt d
+load net {mux#2.itm(1)} -attr vt d
+load net {mux#2.itm(2)} -attr vt d
+load net {mux#2.itm(3)} -attr vt d
+load net {mux#2.itm(4)} -attr vt d
+load net {mux#2.itm(5)} -attr vt d
+load net {mux#2.itm(6)} -attr vt d
+load net {mux#2.itm(7)} -attr vt d
+load net {mux#2.itm(8)} -attr vt d
+load net {mux#2.itm(9)} -attr vt d
+load net {mux#2.itm(10)} -attr vt d
+load net {mux#2.itm(11)} -attr vt d
+load net {mux#2.itm(12)} -attr vt d
+load net {mux#2.itm(13)} -attr vt d
+load net {mux#2.itm(14)} -attr vt d
+load net {mux#2.itm(15)} -attr vt d
+load netBundle {mux#2.itm} 16 {mux#2.itm(0)} {mux#2.itm(1)} {mux#2.itm(2)} {mux#2.itm(3)} {mux#2.itm(4)} {mux#2.itm(5)} {mux#2.itm(6)} {mux#2.itm(7)} {mux#2.itm(8)} {mux#2.itm(9)} {mux#2.itm(10)} {mux#2.itm(11)} {mux#2.itm(12)} {mux#2.itm(13)} {mux#2.itm(14)} {mux#2.itm(15)} -attr xrf 24948 -attr oid 244 -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {FRAME:for:acc#26.itm(0)} -attr vt d
+load net {FRAME:for:acc#26.itm(1)} -attr vt d
+load net {FRAME:for:acc#26.itm(2)} -attr vt d
+load net {FRAME:for:acc#26.itm(3)} -attr vt d
+load net {FRAME:for:acc#26.itm(4)} -attr vt d
+load net {FRAME:for:acc#26.itm(5)} -attr vt d
+load net {FRAME:for:acc#26.itm(6)} -attr vt d
+load net {FRAME:for:acc#26.itm(7)} -attr vt d
+load net {FRAME:for:acc#26.itm(8)} -attr vt d
+load net {FRAME:for:acc#26.itm(9)} -attr vt d
+load net {FRAME:for:acc#26.itm(10)} -attr vt d
+load net {FRAME:for:acc#26.itm(11)} -attr vt d
+load netBundle {FRAME:for:acc#26.itm} 12 {FRAME:for:acc#26.itm(0)} {FRAME:for:acc#26.itm(1)} {FRAME:for:acc#26.itm(2)} {FRAME:for:acc#26.itm(3)} {FRAME:for:acc#26.itm(4)} {FRAME:for:acc#26.itm(5)} {FRAME:for:acc#26.itm(6)} {FRAME:for:acc#26.itm(7)} {FRAME:for:acc#26.itm(8)} {FRAME:for:acc#26.itm(9)} {FRAME:for:acc#26.itm(10)} {FRAME:for:acc#26.itm(11)} -attr xrf 24949 -attr oid 245 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#25.itm(0)} -attr vt d
+load net {FRAME:for:acc#25.itm(1)} -attr vt d
+load net {FRAME:for:acc#25.itm(2)} -attr vt d
+load net {FRAME:for:acc#25.itm(3)} -attr vt d
+load net {FRAME:for:acc#25.itm(4)} -attr vt d
+load net {FRAME:for:acc#25.itm(5)} -attr vt d
+load net {FRAME:for:acc#25.itm(6)} -attr vt d
+load net {FRAME:for:acc#25.itm(7)} -attr vt d
+load net {FRAME:for:acc#25.itm(8)} -attr vt d
+load net {FRAME:for:acc#25.itm(9)} -attr vt d
+load net {FRAME:for:acc#25.itm(10)} -attr vt d
+load net {FRAME:for:acc#25.itm(11)} -attr vt d
+load netBundle {FRAME:for:acc#25.itm} 12 {FRAME:for:acc#25.itm(0)} {FRAME:for:acc#25.itm(1)} {FRAME:for:acc#25.itm(2)} {FRAME:for:acc#25.itm(3)} {FRAME:for:acc#25.itm(4)} {FRAME:for:acc#25.itm(5)} {FRAME:for:acc#25.itm(6)} {FRAME:for:acc#25.itm(7)} {FRAME:for:acc#25.itm(8)} {FRAME:for:acc#25.itm(9)} {FRAME:for:acc#25.itm(10)} {FRAME:for:acc#25.itm(11)} -attr xrf 24950 -attr oid 246 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:mul#7.itm(0)} -attr vt d
+load net {FRAME:for:mul#7.itm(1)} -attr vt d
+load net {FRAME:for:mul#7.itm(2)} -attr vt d
+load net {FRAME:for:mul#7.itm(3)} -attr vt d
+load net {FRAME:for:mul#7.itm(4)} -attr vt d
+load net {FRAME:for:mul#7.itm(5)} -attr vt d
+load net {FRAME:for:mul#7.itm(6)} -attr vt d
+load net {FRAME:for:mul#7.itm(7)} -attr vt d
+load net {FRAME:for:mul#7.itm(8)} -attr vt d
+load net {FRAME:for:mul#7.itm(9)} -attr vt d
+load net {FRAME:for:mul#7.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#7.itm} 11 {FRAME:for:mul#7.itm(0)} {FRAME:for:mul#7.itm(1)} {FRAME:for:mul#7.itm(2)} {FRAME:for:mul#7.itm(3)} {FRAME:for:mul#7.itm(4)} {FRAME:for:mul#7.itm(5)} {FRAME:for:mul#7.itm(6)} {FRAME:for:mul#7.itm(7)} {FRAME:for:mul#7.itm(8)} {FRAME:for:mul#7.itm(9)} {FRAME:for:mul#7.itm(10)} -attr xrf 24951 -attr oid 247 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {regs.operator[]#16:mux.itm(0)} -attr vt d
+load net {regs.operator[]#16:mux.itm(1)} -attr vt d
+load net {regs.operator[]#16:mux.itm(2)} -attr vt d
+load net {regs.operator[]#16:mux.itm(3)} -attr vt d
+load net {regs.operator[]#16:mux.itm(4)} -attr vt d
+load net {regs.operator[]#16:mux.itm(5)} -attr vt d
+load net {regs.operator[]#16:mux.itm(6)} -attr vt d
+load net {regs.operator[]#16:mux.itm(7)} -attr vt d
+load net {regs.operator[]#16:mux.itm(8)} -attr vt d
+load net {regs.operator[]#16:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#16:mux.itm} 10 {regs.operator[]#16:mux.itm(0)} {regs.operator[]#16:mux.itm(1)} {regs.operator[]#16:mux.itm(2)} {regs.operator[]#16:mux.itm(3)} {regs.operator[]#16:mux.itm(4)} {regs.operator[]#16:mux.itm(5)} {regs.operator[]#16:mux.itm(6)} {regs.operator[]#16:mux.itm(7)} {regs.operator[]#16:mux.itm(8)} {regs.operator[]#16:mux.itm(9)} -attr xrf 24952 -attr oid 248 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm} 10 {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(0)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(1)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(2)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(3)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(4)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(5)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(6)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(7)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(8)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(9)} -attr xrf 24953 -attr oid 249 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0).itm} 10 {slc(regs.regs(1).sva.dfm:mx0).itm(0)} {slc(regs.regs(1).sva.dfm:mx0).itm(1)} {slc(regs.regs(1).sva.dfm:mx0).itm(2)} {slc(regs.regs(1).sva.dfm:mx0).itm(3)} {slc(regs.regs(1).sva.dfm:mx0).itm(4)} {slc(regs.regs(1).sva.dfm:mx0).itm(5)} {slc(regs.regs(1).sva.dfm:mx0).itm(6)} {slc(regs.regs(1).sva.dfm:mx0).itm(7)} {slc(regs.regs(1).sva.dfm:mx0).itm(8)} {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr xrf 24954 -attr oid 250 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0).itm} 10 {slc(regs.regs(0).sva.dfm:mx0).itm(0)} {slc(regs.regs(0).sva.dfm:mx0).itm(1)} {slc(regs.regs(0).sva.dfm:mx0).itm(2)} {slc(regs.regs(0).sva.dfm:mx0).itm(3)} {slc(regs.regs(0).sva.dfm:mx0).itm(4)} {slc(regs.regs(0).sva.dfm:mx0).itm(5)} {slc(regs.regs(0).sva.dfm:mx0).itm(6)} {slc(regs.regs(0).sva.dfm:mx0).itm(7)} {slc(regs.regs(0).sva.dfm:mx0).itm(8)} {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr xrf 24955 -attr oid 251 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {FRAME:for:mul#8.itm(0)} -attr vt d
+load net {FRAME:for:mul#8.itm(1)} -attr vt d
+load net {FRAME:for:mul#8.itm(2)} -attr vt d
+load net {FRAME:for:mul#8.itm(3)} -attr vt d
+load net {FRAME:for:mul#8.itm(4)} -attr vt d
+load net {FRAME:for:mul#8.itm(5)} -attr vt d
+load net {FRAME:for:mul#8.itm(6)} -attr vt d
+load net {FRAME:for:mul#8.itm(7)} -attr vt d
+load net {FRAME:for:mul#8.itm(8)} -attr vt d
+load net {FRAME:for:mul#8.itm(9)} -attr vt d
+load net {FRAME:for:mul#8.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#8.itm} 11 {FRAME:for:mul#8.itm(0)} {FRAME:for:mul#8.itm(1)} {FRAME:for:mul#8.itm(2)} {FRAME:for:mul#8.itm(3)} {FRAME:for:mul#8.itm(4)} {FRAME:for:mul#8.itm(5)} {FRAME:for:mul#8.itm(6)} {FRAME:for:mul#8.itm(7)} {FRAME:for:mul#8.itm(8)} {FRAME:for:mul#8.itm(9)} {FRAME:for:mul#8.itm(10)} -attr xrf 24956 -attr oid 252 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {regs.operator[]#17:mux.itm(0)} -attr vt d
+load net {regs.operator[]#17:mux.itm(1)} -attr vt d
+load net {regs.operator[]#17:mux.itm(2)} -attr vt d
+load net {regs.operator[]#17:mux.itm(3)} -attr vt d
+load net {regs.operator[]#17:mux.itm(4)} -attr vt d
+load net {regs.operator[]#17:mux.itm(5)} -attr vt d
+load net {regs.operator[]#17:mux.itm(6)} -attr vt d
+load net {regs.operator[]#17:mux.itm(7)} -attr vt d
+load net {regs.operator[]#17:mux.itm(8)} -attr vt d
+load net {regs.operator[]#17:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#17:mux.itm} 10 {regs.operator[]#17:mux.itm(0)} {regs.operator[]#17:mux.itm(1)} {regs.operator[]#17:mux.itm(2)} {regs.operator[]#17:mux.itm(3)} {regs.operator[]#17:mux.itm(4)} {regs.operator[]#17:mux.itm(5)} {regs.operator[]#17:mux.itm(6)} {regs.operator[]#17:mux.itm(7)} {regs.operator[]#17:mux.itm(8)} {regs.operator[]#17:mux.itm(9)} -attr xrf 24957 -attr oid 253 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm} 10 {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(0)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(1)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(2)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(3)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(4)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(5)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(6)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(7)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(8)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(9)} -attr xrf 24958 -attr oid 254 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr xrf 24959 -attr oid 255 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr xrf 24960 -attr oid 256 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {FRAME:for:mul#6.itm(0)} -attr vt d
+load net {FRAME:for:mul#6.itm(1)} -attr vt d
+load net {FRAME:for:mul#6.itm(2)} -attr vt d
+load net {FRAME:for:mul#6.itm(3)} -attr vt d
+load net {FRAME:for:mul#6.itm(4)} -attr vt d
+load net {FRAME:for:mul#6.itm(5)} -attr vt d
+load net {FRAME:for:mul#6.itm(6)} -attr vt d
+load net {FRAME:for:mul#6.itm(7)} -attr vt d
+load net {FRAME:for:mul#6.itm(8)} -attr vt d
+load net {FRAME:for:mul#6.itm(9)} -attr vt d
+load net {FRAME:for:mul#6.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#6.itm} 11 {FRAME:for:mul#6.itm(0)} {FRAME:for:mul#6.itm(1)} {FRAME:for:mul#6.itm(2)} {FRAME:for:mul#6.itm(3)} {FRAME:for:mul#6.itm(4)} {FRAME:for:mul#6.itm(5)} {FRAME:for:mul#6.itm(6)} {FRAME:for:mul#6.itm(7)} {FRAME:for:mul#6.itm(8)} {FRAME:for:mul#6.itm(9)} {FRAME:for:mul#6.itm(10)} -attr xrf 24961 -attr oid 257 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {regs.operator[]#15:mux.itm(0)} -attr vt d
+load net {regs.operator[]#15:mux.itm(1)} -attr vt d
+load net {regs.operator[]#15:mux.itm(2)} -attr vt d
+load net {regs.operator[]#15:mux.itm(3)} -attr vt d
+load net {regs.operator[]#15:mux.itm(4)} -attr vt d
+load net {regs.operator[]#15:mux.itm(5)} -attr vt d
+load net {regs.operator[]#15:mux.itm(6)} -attr vt d
+load net {regs.operator[]#15:mux.itm(7)} -attr vt d
+load net {regs.operator[]#15:mux.itm(8)} -attr vt d
+load net {regs.operator[]#15:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#15:mux.itm} 10 {regs.operator[]#15:mux.itm(0)} {regs.operator[]#15:mux.itm(1)} {regs.operator[]#15:mux.itm(2)} {regs.operator[]#15:mux.itm(3)} {regs.operator[]#15:mux.itm(4)} {regs.operator[]#15:mux.itm(5)} {regs.operator[]#15:mux.itm(6)} {regs.operator[]#15:mux.itm(7)} {regs.operator[]#15:mux.itm(8)} {regs.operator[]#15:mux.itm(9)} -attr xrf 24962 -attr oid 258 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm} 10 {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(0)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(1)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(2)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(3)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(4)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(5)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(6)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(7)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(8)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(9)} -attr xrf 24963 -attr oid 259 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr xrf 24964 -attr oid 260 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr xrf 24965 -attr oid 261 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {ACC1-3:acc#124.itm(0)} -attr vt d
+load net {ACC1-3:acc#124.itm(1)} -attr vt d
+load net {ACC1-3:acc#124.itm(2)} -attr vt d
+load net {ACC1-3:acc#124.itm(3)} -attr vt d
+load net {ACC1-3:acc#124.itm(4)} -attr vt d
+load net {ACC1-3:acc#124.itm(5)} -attr vt d
+load net {ACC1-3:acc#124.itm(6)} -attr vt d
+load net {ACC1-3:acc#124.itm(7)} -attr vt d
+load net {ACC1-3:acc#124.itm(8)} -attr vt d
+load net {ACC1-3:acc#124.itm(9)} -attr vt d
+load net {ACC1-3:acc#124.itm(10)} -attr vt d
+load net {ACC1-3:acc#124.itm(11)} -attr vt d
+load netBundle {ACC1-3:acc#124.itm} 12 {ACC1-3:acc#124.itm(0)} {ACC1-3:acc#124.itm(1)} {ACC1-3:acc#124.itm(2)} {ACC1-3:acc#124.itm(3)} {ACC1-3:acc#124.itm(4)} {ACC1-3:acc#124.itm(5)} {ACC1-3:acc#124.itm(6)} {ACC1-3:acc#124.itm(7)} {ACC1-3:acc#124.itm(8)} {ACC1-3:acc#124.itm(9)} {ACC1-3:acc#124.itm(10)} {ACC1-3:acc#124.itm(11)} -attr xrf 24966 -attr oid 262 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1:acc#268.itm(0)} -attr vt d
+load net {ACC1:acc#268.itm(1)} -attr vt d
+load net {ACC1:acc#268.itm(2)} -attr vt d
+load net {ACC1:acc#268.itm(3)} -attr vt d
+load net {ACC1:acc#268.itm(4)} -attr vt d
+load net {ACC1:acc#268.itm(5)} -attr vt d
+load net {ACC1:acc#268.itm(6)} -attr vt d
+load net {ACC1:acc#268.itm(7)} -attr vt d
+load net {ACC1:acc#268.itm(8)} -attr vt d
+load net {ACC1:acc#268.itm(9)} -attr vt d
+load net {ACC1:acc#268.itm(10)} -attr vt d
+load netBundle {ACC1:acc#268.itm} 11 {ACC1:acc#268.itm(0)} {ACC1:acc#268.itm(1)} {ACC1:acc#268.itm(2)} {ACC1:acc#268.itm(3)} {ACC1:acc#268.itm(4)} {ACC1:acc#268.itm(5)} {ACC1:acc#268.itm(6)} {ACC1:acc#268.itm(7)} {ACC1:acc#268.itm(8)} {ACC1:acc#268.itm(9)} {ACC1:acc#268.itm(10)} -attr xrf 24967 -attr oid 263 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {conc#616.itm(0)} -attr vt d
+load net {conc#616.itm(1)} -attr vt d
+load net {conc#616.itm(2)} -attr vt d
+load net {conc#616.itm(3)} -attr vt d
+load net {conc#616.itm(4)} -attr vt d
+load net {conc#616.itm(5)} -attr vt d
+load net {conc#616.itm(6)} -attr vt d
+load net {conc#616.itm(7)} -attr vt d
+load net {conc#616.itm(8)} -attr vt d
+load net {conc#616.itm(9)} -attr vt d
+load netBundle {conc#616.itm} 10 {conc#616.itm(0)} {conc#616.itm(1)} {conc#616.itm(2)} {conc#616.itm(3)} {conc#616.itm(4)} {conc#616.itm(5)} {conc#616.itm(6)} {conc#616.itm(7)} {conc#616.itm(8)} {conc#616.itm(9)} -attr xrf 24968 -attr oid 264 -attr vt d -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {ACC1:acc#266.itm(0)} -attr vt d
+load net {ACC1:acc#266.itm(1)} -attr vt d
+load net {ACC1:acc#266.itm(2)} -attr vt d
+load net {ACC1:acc#266.itm(3)} -attr vt d
+load net {ACC1:acc#266.itm(4)} -attr vt d
+load net {ACC1:acc#266.itm(5)} -attr vt d
+load net {ACC1:acc#266.itm(6)} -attr vt d
+load net {ACC1:acc#266.itm(7)} -attr vt d
+load net {ACC1:acc#266.itm(8)} -attr vt d
+load net {ACC1:acc#266.itm(9)} -attr vt d
+load net {ACC1:acc#266.itm(10)} -attr vt d
+load netBundle {ACC1:acc#266.itm} 11 {ACC1:acc#266.itm(0)} {ACC1:acc#266.itm(1)} {ACC1:acc#266.itm(2)} {ACC1:acc#266.itm(3)} {ACC1:acc#266.itm(4)} {ACC1:acc#266.itm(5)} {ACC1:acc#266.itm(6)} {ACC1:acc#266.itm(7)} {ACC1:acc#266.itm(8)} {ACC1:acc#266.itm(9)} {ACC1:acc#266.itm(10)} -attr xrf 24969 -attr oid 265 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#264.itm(0)} -attr vt d
+load net {ACC1:acc#264.itm(1)} -attr vt d
+load net {ACC1:acc#264.itm(2)} -attr vt d
+load net {ACC1:acc#264.itm(3)} -attr vt d
+load net {ACC1:acc#264.itm(4)} -attr vt d
+load net {ACC1:acc#264.itm(5)} -attr vt d
+load net {ACC1:acc#264.itm(6)} -attr vt d
+load net {ACC1:acc#264.itm(7)} -attr vt d
+load net {ACC1:acc#264.itm(8)} -attr vt d
+load net {ACC1:acc#264.itm(9)} -attr vt d
+load netBundle {ACC1:acc#264.itm} 10 {ACC1:acc#264.itm(0)} {ACC1:acc#264.itm(1)} {ACC1:acc#264.itm(2)} {ACC1:acc#264.itm(3)} {ACC1:acc#264.itm(4)} {ACC1:acc#264.itm(5)} {ACC1:acc#264.itm(6)} {ACC1:acc#264.itm(7)} {ACC1:acc#264.itm(8)} {ACC1:acc#264.itm(9)} -attr xrf 24970 -attr oid 266 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#262.itm(0)} -attr vt d
+load net {ACC1:acc#262.itm(1)} -attr vt d
+load net {ACC1:acc#262.itm(2)} -attr vt d
+load net {ACC1:acc#262.itm(3)} -attr vt d
+load net {ACC1:acc#262.itm(4)} -attr vt d
+load net {ACC1:acc#262.itm(5)} -attr vt d
+load net {ACC1:acc#262.itm(6)} -attr vt d
+load net {ACC1:acc#262.itm(7)} -attr vt d
+load netBundle {ACC1:acc#262.itm} 8 {ACC1:acc#262.itm(0)} {ACC1:acc#262.itm(1)} {ACC1:acc#262.itm(2)} {ACC1:acc#262.itm(3)} {ACC1:acc#262.itm(4)} {ACC1:acc#262.itm(5)} {ACC1:acc#262.itm(6)} {ACC1:acc#262.itm(7)} -attr xrf 24971 -attr oid 267 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#259.itm(0)} -attr vt d
+load net {ACC1:acc#259.itm(1)} -attr vt d
+load net {ACC1:acc#259.itm(2)} -attr vt d
+load net {ACC1:acc#259.itm(3)} -attr vt d
+load net {ACC1:acc#259.itm(4)} -attr vt d
+load net {ACC1:acc#259.itm(5)} -attr vt d
+load netBundle {ACC1:acc#259.itm} 6 {ACC1:acc#259.itm(0)} {ACC1:acc#259.itm(1)} {ACC1:acc#259.itm(2)} {ACC1:acc#259.itm(3)} {ACC1:acc#259.itm(4)} {ACC1:acc#259.itm(5)} -attr xrf 24972 -attr oid 268 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#256.itm(0)} -attr vt d
+load net {ACC1:acc#256.itm(1)} -attr vt d
+load net {ACC1:acc#256.itm(2)} -attr vt d
+load net {ACC1:acc#256.itm(3)} -attr vt d
+load netBundle {ACC1:acc#256.itm} 4 {ACC1:acc#256.itm(0)} {ACC1:acc#256.itm(1)} {ACC1:acc#256.itm(2)} {ACC1:acc#256.itm(3)} -attr xrf 24973 -attr oid 269 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#251.itm(0)} -attr vt d
+load net {ACC1:acc#251.itm(1)} -attr vt d
+load net {ACC1:acc#251.itm(2)} -attr vt d
+load netBundle {ACC1:acc#251.itm} 3 {ACC1:acc#251.itm(0)} {ACC1:acc#251.itm(1)} {ACC1:acc#251.itm(2)} -attr xrf 24974 -attr oid 270 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:slc#68.itm(0)} -attr vt d
+load net {ACC1:slc#68.itm(1)} -attr vt d
+load net {ACC1:slc#68.itm(2)} -attr vt d
+load netBundle {ACC1:slc#68.itm} 3 {ACC1:slc#68.itm(0)} {ACC1:slc#68.itm(1)} {ACC1:slc#68.itm(2)} -attr xrf 24975 -attr oid 271 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#68.itm}
+load net {ACC1:acc#242.itm(0)} -attr vt d
+load net {ACC1:acc#242.itm(1)} -attr vt d
+load net {ACC1:acc#242.itm(2)} -attr vt d
+load net {ACC1:acc#242.itm(3)} -attr vt d
+load netBundle {ACC1:acc#242.itm} 4 {ACC1:acc#242.itm(0)} {ACC1:acc#242.itm(1)} {ACC1:acc#242.itm(2)} {ACC1:acc#242.itm(3)} -attr xrf 24976 -attr oid 272 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {conc#617.itm(0)} -attr vt d
+load net {conc#617.itm(1)} -attr vt d
+load net {conc#617.itm(2)} -attr vt d
+load netBundle {conc#617.itm} 3 {conc#617.itm(0)} {conc#617.itm(1)} {conc#617.itm(2)} -attr xrf 24977 -attr oid 273 -attr vt d -attr @path {/sobel/sobel:core/conc#617.itm}
+load net {ACC1:conc#582.itm(0)} -attr vt d
+load net {ACC1:conc#582.itm(1)} -attr vt d
+load netBundle {ACC1:conc#582.itm} 2 {ACC1:conc#582.itm(0)} {ACC1:conc#582.itm(1)} -attr xrf 24978 -attr oid 274 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#582.itm}
+load net {slc(ACC1:acc#120.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#120.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#120.psp.sva)#2.itm} 2 {slc(ACC1:acc#120.psp.sva)#2.itm(0)} {slc(ACC1:acc#120.psp.sva)#2.itm(1)} -attr xrf 24979 -attr oid 275 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp.sva)#2.itm}
+load net {ACC1:slc#69.itm(0)} -attr vt d
+load net {ACC1:slc#69.itm(1)} -attr vt d
+load net {ACC1:slc#69.itm(2)} -attr vt d
+load net {ACC1:slc#69.itm(3)} -attr vt d
+load netBundle {ACC1:slc#69.itm} 4 {ACC1:slc#69.itm(0)} {ACC1:slc#69.itm(1)} {ACC1:slc#69.itm(2)} {ACC1:slc#69.itm(3)} -attr xrf 24980 -attr oid 276 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#69.itm}
+load net {ACC1:acc#243.itm(0)} -attr vt d
+load net {ACC1:acc#243.itm(1)} -attr vt d
+load net {ACC1:acc#243.itm(2)} -attr vt d
+load net {ACC1:acc#243.itm(3)} -attr vt d
+load net {ACC1:acc#243.itm(4)} -attr vt d
+load netBundle {ACC1:acc#243.itm} 5 {ACC1:acc#243.itm(0)} {ACC1:acc#243.itm(1)} {ACC1:acc#243.itm(2)} {ACC1:acc#243.itm(3)} {ACC1:acc#243.itm(4)} -attr xrf 24981 -attr oid 277 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {conc#618.itm(0)} -attr vt d
+load net {conc#618.itm(1)} -attr vt d
+load net {conc#618.itm(2)} -attr vt d
+load netBundle {conc#618.itm} 3 {conc#618.itm(0)} {conc#618.itm(1)} {conc#618.itm(2)} -attr xrf 24982 -attr oid 278 -attr vt d -attr @path {/sobel/sobel:core/conc#618.itm}
+load net {ACC1:conc#584.itm(0)} -attr vt d
+load net {ACC1:conc#584.itm(1)} -attr vt d
+load net {ACC1:conc#584.itm(2)} -attr vt d
+load netBundle {ACC1:conc#584.itm} 3 {ACC1:conc#584.itm(0)} {ACC1:conc#584.itm(1)} {ACC1:conc#584.itm(2)} -attr xrf 24983 -attr oid 279 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#584.itm}
+load net {ACC1:acc#255.itm(0)} -attr vt d
+load net {ACC1:acc#255.itm(1)} -attr vt d
+load net {ACC1:acc#255.itm(2)} -attr vt d
+load net {ACC1:acc#255.itm(3)} -attr vt d
+load net {ACC1:acc#255.itm(4)} -attr vt d
+load netBundle {ACC1:acc#255.itm} 5 {ACC1:acc#255.itm(0)} {ACC1:acc#255.itm(1)} {ACC1:acc#255.itm(2)} {ACC1:acc#255.itm(3)} {ACC1:acc#255.itm(4)} -attr xrf 24984 -attr oid 280 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1-3:conc#284.itm(0)} -attr vt d
+load net {ACC1-3:conc#284.itm(1)} -attr vt d
+load net {ACC1-3:conc#284.itm(2)} -attr vt d
+load net {ACC1-3:conc#284.itm(3)} -attr vt d
+load netBundle {ACC1-3:conc#284.itm} 4 {ACC1-3:conc#284.itm(0)} {ACC1-3:conc#284.itm(1)} {ACC1-3:conc#284.itm(2)} {ACC1-3:conc#284.itm(3)} -attr xrf 24985 -attr oid 281 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#284.itm}
+load net {ACC1-3:exs#555.itm(0)} -attr vt d
+load net {ACC1-3:exs#555.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#555.itm} 2 {ACC1-3:exs#555.itm(0)} {ACC1-3:exs#555.itm(1)} -attr xrf 24986 -attr oid 282 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#555.itm}
+load net {conc#619.itm(0)} -attr vt d
+load net {conc#619.itm(1)} -attr vt d
+load net {conc#619.itm(2)} -attr vt d
+load net {conc#619.itm(3)} -attr vt d
+load net {conc#619.itm(4)} -attr vt d
+load net {conc#619.itm(5)} -attr vt d
+load net {conc#619.itm(6)} -attr vt d
+load netBundle {conc#619.itm} 7 {conc#619.itm(0)} {conc#619.itm(1)} {conc#619.itm(2)} {conc#619.itm(3)} {conc#619.itm(4)} {conc#619.itm(5)} {conc#619.itm(6)} -attr xrf 24987 -attr oid 283 -attr vt d -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {ACC1:acc#261.itm(0)} -attr vt d
+load net {ACC1:acc#261.itm(1)} -attr vt d
+load net {ACC1:acc#261.itm(2)} -attr vt d
+load net {ACC1:acc#261.itm(3)} -attr vt d
+load net {ACC1:acc#261.itm(4)} -attr vt d
+load net {ACC1:acc#261.itm(5)} -attr vt d
+load net {ACC1:acc#261.itm(6)} -attr vt d
+load net {ACC1:acc#261.itm(7)} -attr vt d
+load netBundle {ACC1:acc#261.itm} 8 {ACC1:acc#261.itm(0)} {ACC1:acc#261.itm(1)} {ACC1:acc#261.itm(2)} {ACC1:acc#261.itm(3)} {ACC1:acc#261.itm(4)} {ACC1:acc#261.itm(5)} {ACC1:acc#261.itm(6)} {ACC1:acc#261.itm(7)} -attr xrf 24988 -attr oid 284 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1-3:exs#544.itm(0)} -attr vt d
+load net {ACC1-3:exs#544.itm(1)} -attr vt d
+load net {ACC1-3:exs#544.itm(2)} -attr vt d
+load net {ACC1-3:exs#544.itm(3)} -attr vt d
+load net {ACC1-3:exs#544.itm(4)} -attr vt d
+load net {ACC1-3:exs#544.itm(5)} -attr vt d
+load net {ACC1-3:exs#544.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#544.itm} 7 {ACC1-3:exs#544.itm(0)} {ACC1-3:exs#544.itm(1)} {ACC1-3:exs#544.itm(2)} {ACC1-3:exs#544.itm(3)} {ACC1-3:exs#544.itm(4)} {ACC1-3:exs#544.itm(5)} {ACC1-3:exs#544.itm(6)} -attr xrf 24989 -attr oid 285 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {ACC1-3:conc#254.itm(0)} -attr vt d
+load net {ACC1-3:conc#254.itm(1)} -attr vt d
+load net {ACC1-3:conc#254.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#254.itm} 3 {ACC1-3:conc#254.itm(0)} {ACC1-3:conc#254.itm(1)} {ACC1-3:conc#254.itm(2)} -attr xrf 24990 -attr oid 286 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#254.itm}
+load net {ACC1-3:exs#556.itm(0)} -attr vt d
+load net {ACC1-3:exs#556.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#556.itm} 2 {ACC1-3:exs#556.itm(0)} {ACC1-3:exs#556.itm(1)} -attr xrf 24991 -attr oid 287 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#556.itm}
+load net {ACC1:acc#258.itm(0)} -attr vt d
+load net {ACC1:acc#258.itm(1)} -attr vt d
+load net {ACC1:acc#258.itm(2)} -attr vt d
+load net {ACC1:acc#258.itm(3)} -attr vt d
+load net {ACC1:acc#258.itm(4)} -attr vt d
+load net {ACC1:acc#258.itm(5)} -attr vt d
+load netBundle {ACC1:acc#258.itm} 6 {ACC1:acc#258.itm(0)} {ACC1:acc#258.itm(1)} {ACC1:acc#258.itm(2)} {ACC1:acc#258.itm(3)} {ACC1:acc#258.itm(4)} {ACC1:acc#258.itm(5)} -attr xrf 24992 -attr oid 288 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {conc#620.itm(0)} -attr vt d
+load net {conc#620.itm(1)} -attr vt d
+load net {conc#620.itm(2)} -attr vt d
+load net {conc#620.itm(3)} -attr vt d
+load net {conc#620.itm(4)} -attr vt d
+load netBundle {conc#620.itm} 5 {conc#620.itm(0)} {conc#620.itm(1)} {conc#620.itm(2)} {conc#620.itm(3)} {conc#620.itm(4)} -attr xrf 24993 -attr oid 289 -attr vt d -attr @path {/sobel/sobel:core/conc#620.itm}
+load net {ACC1:acc#254.itm(0)} -attr vt d
+load net {ACC1:acc#254.itm(1)} -attr vt d
+load net {ACC1:acc#254.itm(2)} -attr vt d
+load net {ACC1:acc#254.itm(3)} -attr vt d
+load netBundle {ACC1:acc#254.itm} 4 {ACC1:acc#254.itm(0)} {ACC1:acc#254.itm(1)} {ACC1:acc#254.itm(2)} {ACC1:acc#254.itm(3)} -attr xrf 24994 -attr oid 290 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:slc#74.itm(0)} -attr vt d
+load net {ACC1:slc#74.itm(1)} -attr vt d
+load net {ACC1:slc#74.itm(2)} -attr vt d
+load netBundle {ACC1:slc#74.itm} 3 {ACC1:slc#74.itm(0)} {ACC1:slc#74.itm(1)} {ACC1:slc#74.itm(2)} -attr xrf 24995 -attr oid 291 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:acc#248.itm(0)} -attr vt d
+load net {ACC1:acc#248.itm(1)} -attr vt d
+load net {ACC1:acc#248.itm(2)} -attr vt d
+load net {ACC1:acc#248.itm(3)} -attr vt d
+load netBundle {ACC1:acc#248.itm} 4 {ACC1:acc#248.itm(0)} {ACC1:acc#248.itm(1)} {ACC1:acc#248.itm(2)} {ACC1:acc#248.itm(3)} -attr xrf 24996 -attr oid 292 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {exs#58.itm(0)} -attr vt d
+load net {exs#58.itm(1)} -attr vt d
+load net {exs#58.itm(2)} -attr vt d
+load netBundle {exs#58.itm} 3 {exs#58.itm(0)} {exs#58.itm(1)} {exs#58.itm(2)} -attr xrf 24997 -attr oid 293 -attr vt d -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {conc#621.itm(0)} -attr vt d
+load net {conc#621.itm(1)} -attr vt d
+load netBundle {conc#621.itm} 2 {conc#621.itm(0)} {conc#621.itm(1)} -attr xrf 24998 -attr oid 294 -attr vt d -attr @path {/sobel/sobel:core/conc#621.itm}
+load net {ACC1:exs#772.itm(0)} -attr vt d
+load net {ACC1:exs#772.itm(1)} -attr vt d
+load net {ACC1:exs#772.itm(2)} -attr vt d
+load netBundle {ACC1:exs#772.itm} 3 {ACC1:exs#772.itm(0)} {ACC1:exs#772.itm(1)} {ACC1:exs#772.itm(2)} -attr xrf 24999 -attr oid 295 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#772.itm}
+load net {ACC1:conc#594.itm(0)} -attr vt d
+load net {ACC1:conc#594.itm(1)} -attr vt d
+load netBundle {ACC1:conc#594.itm} 2 {ACC1:conc#594.itm(0)} {ACC1:conc#594.itm(1)} -attr xrf 25000 -attr oid 296 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#594.itm}
+load net {conc#623.itm(0)} -attr vt d
+load net {conc#623.itm(1)} -attr vt d
+load net {conc#623.itm(2)} -attr vt d
+load net {conc#623.itm(3)} -attr vt d
+load net {conc#623.itm(4)} -attr vt d
+load net {conc#623.itm(5)} -attr vt d
+load net {conc#623.itm(6)} -attr vt d
+load net {conc#623.itm(7)} -attr vt d
+load net {conc#623.itm(8)} -attr vt d
+load net {conc#623.itm(9)} -attr vt d
+load netBundle {conc#623.itm} 10 {conc#623.itm(0)} {conc#623.itm(1)} {conc#623.itm(2)} {conc#623.itm(3)} {conc#623.itm(4)} {conc#623.itm(5)} {conc#623.itm(6)} {conc#623.itm(7)} {conc#623.itm(8)} {conc#623.itm(9)} -attr xrf 25001 -attr oid 297 -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {ACC1-3:exs#572.itm(0)} -attr vt d
+load net {ACC1-3:exs#572.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#572.itm} 2 {ACC1-3:exs#572.itm(0)} {ACC1-3:exs#572.itm(1)} -attr xrf 25002 -attr oid 298 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#572.itm}
+load net {ACC1:acc#267.itm(0)} -attr vt d
+load net {ACC1:acc#267.itm(1)} -attr vt d
+load net {ACC1:acc#267.itm(2)} -attr vt d
+load net {ACC1:acc#267.itm(3)} -attr vt d
+load net {ACC1:acc#267.itm(4)} -attr vt d
+load net {ACC1:acc#267.itm(5)} -attr vt d
+load net {ACC1:acc#267.itm(6)} -attr vt d
+load net {ACC1:acc#267.itm(7)} -attr vt d
+load net {ACC1:acc#267.itm(8)} -attr vt d
+load net {ACC1:acc#267.itm(9)} -attr vt d
+load net {ACC1:acc#267.itm(10)} -attr vt d
+load net {ACC1:acc#267.itm(11)} -attr vt d
+load netBundle {ACC1:acc#267.itm} 12 {ACC1:acc#267.itm(0)} {ACC1:acc#267.itm(1)} {ACC1:acc#267.itm(2)} {ACC1:acc#267.itm(3)} {ACC1:acc#267.itm(4)} {ACC1:acc#267.itm(5)} {ACC1:acc#267.itm(6)} {ACC1:acc#267.itm(7)} {ACC1:acc#267.itm(8)} {ACC1:acc#267.itm(9)} {ACC1:acc#267.itm(10)} {ACC1:acc#267.itm(11)} -attr xrf 25003 -attr oid 299 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1-1:acc#124.itm(0)} -attr vt d
+load net {ACC1-1:acc#124.itm(1)} -attr vt d
+load net {ACC1-1:acc#124.itm(2)} -attr vt d
+load net {ACC1-1:acc#124.itm(3)} -attr vt d
+load net {ACC1-1:acc#124.itm(4)} -attr vt d
+load net {ACC1-1:acc#124.itm(5)} -attr vt d
+load net {ACC1-1:acc#124.itm(6)} -attr vt d
+load net {ACC1-1:acc#124.itm(7)} -attr vt d
+load net {ACC1-1:acc#124.itm(8)} -attr vt d
+load net {ACC1-1:acc#124.itm(9)} -attr vt d
+load net {ACC1-1:acc#124.itm(10)} -attr vt d
+load netBundle {ACC1-1:acc#124.itm} 11 {ACC1-1:acc#124.itm(0)} {ACC1-1:acc#124.itm(1)} {ACC1-1:acc#124.itm(2)} {ACC1-1:acc#124.itm(3)} {ACC1-1:acc#124.itm(4)} {ACC1-1:acc#124.itm(5)} {ACC1-1:acc#124.itm(6)} {ACC1-1:acc#124.itm(7)} {ACC1-1:acc#124.itm(8)} {ACC1-1:acc#124.itm(9)} {ACC1-1:acc#124.itm(10)} -attr xrf 25004 -attr oid 300 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1:acc#294.itm(0)} -attr vt d
+load net {ACC1:acc#294.itm(1)} -attr vt d
+load net {ACC1:acc#294.itm(2)} -attr vt d
+load net {ACC1:acc#294.itm(3)} -attr vt d
+load net {ACC1:acc#294.itm(4)} -attr vt d
+load net {ACC1:acc#294.itm(5)} -attr vt d
+load net {ACC1:acc#294.itm(6)} -attr vt d
+load net {ACC1:acc#294.itm(7)} -attr vt d
+load net {ACC1:acc#294.itm(8)} -attr vt d
+load net {ACC1:acc#294.itm(9)} -attr vt d
+load net {ACC1:acc#294.itm(10)} -attr vt d
+load netBundle {ACC1:acc#294.itm} 11 {ACC1:acc#294.itm(0)} {ACC1:acc#294.itm(1)} {ACC1:acc#294.itm(2)} {ACC1:acc#294.itm(3)} {ACC1:acc#294.itm(4)} {ACC1:acc#294.itm(5)} {ACC1:acc#294.itm(6)} {ACC1:acc#294.itm(7)} {ACC1:acc#294.itm(8)} {ACC1:acc#294.itm(9)} {ACC1:acc#294.itm(10)} -attr xrf 25005 -attr oid 301 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#292.itm(0)} -attr vt d
+load net {ACC1:acc#292.itm(1)} -attr vt d
+load net {ACC1:acc#292.itm(2)} -attr vt d
+load net {ACC1:acc#292.itm(3)} -attr vt d
+load net {ACC1:acc#292.itm(4)} -attr vt d
+load net {ACC1:acc#292.itm(5)} -attr vt d
+load net {ACC1:acc#292.itm(6)} -attr vt d
+load net {ACC1:acc#292.itm(7)} -attr vt d
+load net {ACC1:acc#292.itm(8)} -attr vt d
+load net {ACC1:acc#292.itm(9)} -attr vt d
+load netBundle {ACC1:acc#292.itm} 10 {ACC1:acc#292.itm(0)} {ACC1:acc#292.itm(1)} {ACC1:acc#292.itm(2)} {ACC1:acc#292.itm(3)} {ACC1:acc#292.itm(4)} {ACC1:acc#292.itm(5)} {ACC1:acc#292.itm(6)} {ACC1:acc#292.itm(7)} {ACC1:acc#292.itm(8)} {ACC1:acc#292.itm(9)} -attr xrf 25006 -attr oid 302 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {conc#624.itm(0)} -attr vt d
+load net {conc#624.itm(1)} -attr vt d
+load net {conc#624.itm(2)} -attr vt d
+load net {conc#624.itm(3)} -attr vt d
+load net {conc#624.itm(4)} -attr vt d
+load net {conc#624.itm(5)} -attr vt d
+load net {conc#624.itm(6)} -attr vt d
+load net {conc#624.itm(7)} -attr vt d
+load net {conc#624.itm(8)} -attr vt d
+load netBundle {conc#624.itm} 9 {conc#624.itm(0)} {conc#624.itm(1)} {conc#624.itm(2)} {conc#624.itm(3)} {conc#624.itm(4)} {conc#624.itm(5)} {conc#624.itm(6)} {conc#624.itm(7)} {conc#624.itm(8)} -attr xrf 25007 -attr oid 303 -attr vt d -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {ACC1:acc#290.itm(0)} -attr vt d
+load net {ACC1:acc#290.itm(1)} -attr vt d
+load net {ACC1:acc#290.itm(2)} -attr vt d
+load net {ACC1:acc#290.itm(3)} -attr vt d
+load net {ACC1:acc#290.itm(4)} -attr vt d
+load net {ACC1:acc#290.itm(5)} -attr vt d
+load net {ACC1:acc#290.itm(6)} -attr vt d
+load net {ACC1:acc#290.itm(7)} -attr vt d
+load netBundle {ACC1:acc#290.itm} 8 {ACC1:acc#290.itm(0)} {ACC1:acc#290.itm(1)} {ACC1:acc#290.itm(2)} {ACC1:acc#290.itm(3)} {ACC1:acc#290.itm(4)} {ACC1:acc#290.itm(5)} {ACC1:acc#290.itm(6)} {ACC1:acc#290.itm(7)} -attr xrf 25008 -attr oid 304 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {conc#625.itm(0)} -attr vt d
+load net {conc#625.itm(1)} -attr vt d
+load net {conc#625.itm(2)} -attr vt d
+load net {conc#625.itm(3)} -attr vt d
+load net {conc#625.itm(4)} -attr vt d
+load net {conc#625.itm(5)} -attr vt d
+load net {conc#625.itm(6)} -attr vt d
+load net {conc#625.itm(7)} -attr vt d
+load netBundle {conc#625.itm} 8 {conc#625.itm(0)} {conc#625.itm(1)} {conc#625.itm(2)} {conc#625.itm(3)} {conc#625.itm(4)} {conc#625.itm(5)} {conc#625.itm(6)} {conc#625.itm(7)} -attr xrf 25009 -attr oid 305 -attr vt d -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {ACC1-1:exs#553.itm(0)} -attr vt d
+load net {ACC1-1:exs#553.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#553.itm} 2 {ACC1-1:exs#553.itm(0)} {ACC1-1:exs#553.itm(1)} -attr xrf 25010 -attr oid 306 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#553.itm}
+load net {ACC1:acc#287.itm(0)} -attr vt d
+load net {ACC1:acc#287.itm(1)} -attr vt d
+load net {ACC1:acc#287.itm(2)} -attr vt d
+load net {ACC1:acc#287.itm(3)} -attr vt d
+load net {ACC1:acc#287.itm(4)} -attr vt d
+load net {ACC1:acc#287.itm(5)} -attr vt d
+load net {ACC1:acc#287.itm(6)} -attr vt d
+load netBundle {ACC1:acc#287.itm} 7 {ACC1:acc#287.itm(0)} {ACC1:acc#287.itm(1)} {ACC1:acc#287.itm(2)} {ACC1:acc#287.itm(3)} {ACC1:acc#287.itm(4)} {ACC1:acc#287.itm(5)} {ACC1:acc#287.itm(6)} -attr xrf 25011 -attr oid 307 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {conc#626.itm(0)} -attr vt d
+load net {conc#626.itm(1)} -attr vt d
+load net {conc#626.itm(2)} -attr vt d
+load net {conc#626.itm(3)} -attr vt d
+load net {conc#626.itm(4)} -attr vt d
+load net {conc#626.itm(5)} -attr vt d
+load netBundle {conc#626.itm} 6 {conc#626.itm(0)} {conc#626.itm(1)} {conc#626.itm(2)} {conc#626.itm(3)} {conc#626.itm(4)} {conc#626.itm(5)} -attr xrf 25012 -attr oid 308 -attr vt d -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {ACC1-1:exs#556.itm(0)} -attr vt d
+load net {ACC1-1:exs#556.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#556.itm} 2 {ACC1-1:exs#556.itm(0)} {ACC1-1:exs#556.itm(1)} -attr xrf 25013 -attr oid 309 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#556.itm}
+load net {ACC1:acc#284.itm(0)} -attr vt d
+load net {ACC1:acc#284.itm(1)} -attr vt d
+load net {ACC1:acc#284.itm(2)} -attr vt d
+load net {ACC1:acc#284.itm(3)} -attr vt d
+load net {ACC1:acc#284.itm(4)} -attr vt d
+load netBundle {ACC1:acc#284.itm} 5 {ACC1:acc#284.itm(0)} {ACC1:acc#284.itm(1)} {ACC1:acc#284.itm(2)} {ACC1:acc#284.itm(3)} {ACC1:acc#284.itm(4)} -attr xrf 25014 -attr oid 310 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#280.itm(0)} -attr vt d
+load net {ACC1:acc#280.itm(1)} -attr vt d
+load net {ACC1:acc#280.itm(2)} -attr vt d
+load net {ACC1:acc#280.itm(3)} -attr vt d
+load netBundle {ACC1:acc#280.itm} 4 {ACC1:acc#280.itm(0)} {ACC1:acc#280.itm(1)} {ACC1:acc#280.itm(2)} {ACC1:acc#280.itm(3)} -attr xrf 25015 -attr oid 311 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:slc#80.itm(0)} -attr vt d
+load net {ACC1:slc#80.itm(1)} -attr vt d
+load net {ACC1:slc#80.itm(2)} -attr vt d
+load netBundle {ACC1:slc#80.itm} 3 {ACC1:slc#80.itm(0)} {ACC1:slc#80.itm(1)} {ACC1:slc#80.itm(2)} -attr xrf 25016 -attr oid 312 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#80.itm}
+load net {ACC1:acc#274.itm(0)} -attr vt d
+load net {ACC1:acc#274.itm(1)} -attr vt d
+load net {ACC1:acc#274.itm(2)} -attr vt d
+load net {ACC1:acc#274.itm(3)} -attr vt d
+load netBundle {ACC1:acc#274.itm} 4 {ACC1:acc#274.itm(0)} {ACC1:acc#274.itm(1)} {ACC1:acc#274.itm(2)} {ACC1:acc#274.itm(3)} -attr xrf 25017 -attr oid 313 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {exs#38.itm(0)} -attr vt d
+load net {exs#38.itm(1)} -attr vt d
+load net {exs#38.itm(2)} -attr vt d
+load netBundle {exs#38.itm} 3 {exs#38.itm(0)} {exs#38.itm(1)} {exs#38.itm(2)} -attr xrf 25018 -attr oid 314 -attr vt d -attr @path {/sobel/sobel:core/exs#38.itm}
+load net {conc#627.itm(0)} -attr vt d
+load net {conc#627.itm(1)} -attr vt d
+load netBundle {conc#627.itm} 2 {conc#627.itm(0)} {conc#627.itm(1)} -attr xrf 25019 -attr oid 315 -attr vt d -attr @path {/sobel/sobel:core/conc#627.itm}
+load net {ACC1:exs#774.itm(0)} -attr vt d
+load net {ACC1:exs#774.itm(1)} -attr vt d
+load net {ACC1:exs#774.itm(2)} -attr vt d
+load netBundle {ACC1:exs#774.itm} 3 {ACC1:exs#774.itm(0)} {ACC1:exs#774.itm(1)} {ACC1:exs#774.itm(2)} -attr xrf 25020 -attr oid 316 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#774.itm}
+load net {ACC1:conc#607.itm(0)} -attr vt d
+load net {ACC1:conc#607.itm(1)} -attr vt d
+load netBundle {ACC1:conc#607.itm} 2 {ACC1:conc#607.itm(0)} {ACC1:conc#607.itm(1)} -attr xrf 25021 -attr oid 317 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#607.itm}
+load net {ACC1:slc#79.itm(0)} -attr vt d
+load net {ACC1:slc#79.itm(1)} -attr vt d
+load net {ACC1:slc#79.itm(2)} -attr vt d
+load netBundle {ACC1:slc#79.itm} 3 {ACC1:slc#79.itm(0)} {ACC1:slc#79.itm(1)} {ACC1:slc#79.itm(2)} -attr xrf 25022 -attr oid 318 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#79.itm}
+load net {ACC1:acc#273.itm(0)} -attr vt d
+load net {ACC1:acc#273.itm(1)} -attr vt d
+load net {ACC1:acc#273.itm(2)} -attr vt d
+load net {ACC1:acc#273.itm(3)} -attr vt d
+load netBundle {ACC1:acc#273.itm} 4 {ACC1:acc#273.itm(0)} {ACC1:acc#273.itm(1)} {ACC1:acc#273.itm(2)} {ACC1:acc#273.itm(3)} -attr xrf 25023 -attr oid 319 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {exs#39.itm(0)} -attr vt d
+load net {exs#39.itm(1)} -attr vt d
+load net {exs#39.itm(2)} -attr vt d
+load netBundle {exs#39.itm} 3 {exs#39.itm(0)} {exs#39.itm(1)} {exs#39.itm(2)} -attr xrf 25024 -attr oid 320 -attr vt d -attr @path {/sobel/sobel:core/exs#39.itm}
+load net {conc#628.itm(0)} -attr vt d
+load net {conc#628.itm(1)} -attr vt d
+load netBundle {conc#628.itm} 2 {conc#628.itm(0)} {conc#628.itm(1)} -attr xrf 25025 -attr oid 321 -attr vt d -attr @path {/sobel/sobel:core/conc#628.itm}
+load net {ACC1:exs#776.itm(0)} -attr vt d
+load net {ACC1:exs#776.itm(1)} -attr vt d
+load net {ACC1:exs#776.itm(2)} -attr vt d
+load netBundle {ACC1:exs#776.itm} 3 {ACC1:exs#776.itm(0)} {ACC1:exs#776.itm(1)} {ACC1:exs#776.itm(2)} -attr xrf 25026 -attr oid 322 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#776.itm}
+load net {ACC1:conc#605.itm(0)} -attr vt d
+load net {ACC1:conc#605.itm(1)} -attr vt d
+load netBundle {ACC1:conc#605.itm} 2 {ACC1:conc#605.itm(0)} {ACC1:conc#605.itm(1)} -attr xrf 25027 -attr oid 323 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#605.itm}
+load net {ACC1:acc#279.itm(0)} -attr vt d
+load net {ACC1:acc#279.itm(1)} -attr vt d
+load net {ACC1:acc#279.itm(2)} -attr vt d
+load net {ACC1:acc#279.itm(3)} -attr vt d
+load netBundle {ACC1:acc#279.itm} 4 {ACC1:acc#279.itm(0)} {ACC1:acc#279.itm(1)} {ACC1:acc#279.itm(2)} {ACC1:acc#279.itm(3)} -attr xrf 25028 -attr oid 324 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:slc#78.itm(0)} -attr vt d
+load net {ACC1:slc#78.itm(1)} -attr vt d
+load net {ACC1:slc#78.itm(2)} -attr vt d
+load netBundle {ACC1:slc#78.itm} 3 {ACC1:slc#78.itm(0)} {ACC1:slc#78.itm(1)} {ACC1:slc#78.itm(2)} -attr xrf 25029 -attr oid 325 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#78.itm}
+load net {ACC1:acc#272.itm(0)} -attr vt d
+load net {ACC1:acc#272.itm(1)} -attr vt d
+load net {ACC1:acc#272.itm(2)} -attr vt d
+load net {ACC1:acc#272.itm(3)} -attr vt d
+load netBundle {ACC1:acc#272.itm} 4 {ACC1:acc#272.itm(0)} {ACC1:acc#272.itm(1)} {ACC1:acc#272.itm(2)} {ACC1:acc#272.itm(3)} -attr xrf 25030 -attr oid 326 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {exs#40.itm(0)} -attr vt d
+load net {exs#40.itm(1)} -attr vt d
+load net {exs#40.itm(2)} -attr vt d
+load netBundle {exs#40.itm} 3 {exs#40.itm(0)} {exs#40.itm(1)} {exs#40.itm(2)} -attr xrf 25031 -attr oid 327 -attr vt d -attr @path {/sobel/sobel:core/exs#40.itm}
+load net {conc#629.itm(0)} -attr vt d
+load net {conc#629.itm(1)} -attr vt d
+load netBundle {conc#629.itm} 2 {conc#629.itm(0)} {conc#629.itm(1)} -attr xrf 25032 -attr oid 328 -attr vt d -attr @path {/sobel/sobel:core/conc#629.itm}
+load net {ACC1:exs#778.itm(0)} -attr vt d
+load net {ACC1:exs#778.itm(1)} -attr vt d
+load net {ACC1:exs#778.itm(2)} -attr vt d
+load netBundle {ACC1:exs#778.itm} 3 {ACC1:exs#778.itm(0)} {ACC1:exs#778.itm(1)} {ACC1:exs#778.itm(2)} -attr xrf 25033 -attr oid 329 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#778.itm}
+load net {ACC1:conc#603.itm(0)} -attr vt d
+load net {ACC1:conc#603.itm(1)} -attr vt d
+load netBundle {ACC1:conc#603.itm} 2 {ACC1:conc#603.itm(0)} {ACC1:conc#603.itm(1)} -attr xrf 25034 -attr oid 330 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#603.itm}
+load net {ACC1:slc#77.itm(0)} -attr vt d
+load net {ACC1:slc#77.itm(1)} -attr vt d
+load net {ACC1:slc#77.itm(2)} -attr vt d
+load netBundle {ACC1:slc#77.itm} 3 {ACC1:slc#77.itm(0)} {ACC1:slc#77.itm(1)} {ACC1:slc#77.itm(2)} -attr xrf 25035 -attr oid 331 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#77.itm}
+load net {ACC1:acc#271.itm(0)} -attr vt d
+load net {ACC1:acc#271.itm(1)} -attr vt d
+load net {ACC1:acc#271.itm(2)} -attr vt d
+load net {ACC1:acc#271.itm(3)} -attr vt d
+load netBundle {ACC1:acc#271.itm} 4 {ACC1:acc#271.itm(0)} {ACC1:acc#271.itm(1)} {ACC1:acc#271.itm(2)} {ACC1:acc#271.itm(3)} -attr xrf 25036 -attr oid 332 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {exs#41.itm(0)} -attr vt d
+load net {exs#41.itm(1)} -attr vt d
+load net {exs#41.itm(2)} -attr vt d
+load netBundle {exs#41.itm} 3 {exs#41.itm(0)} {exs#41.itm(1)} {exs#41.itm(2)} -attr xrf 25037 -attr oid 333 -attr vt d -attr @path {/sobel/sobel:core/exs#41.itm}
+load net {conc#630.itm(0)} -attr vt d
+load net {conc#630.itm(1)} -attr vt d
+load netBundle {conc#630.itm} 2 {conc#630.itm(0)} {conc#630.itm(1)} -attr xrf 25038 -attr oid 334 -attr vt d -attr @path {/sobel/sobel:core/conc#630.itm}
+load net {ACC1:exs#780.itm(0)} -attr vt d
+load net {ACC1:exs#780.itm(1)} -attr vt d
+load net {ACC1:exs#780.itm(2)} -attr vt d
+load netBundle {ACC1:exs#780.itm} 3 {ACC1:exs#780.itm(0)} {ACC1:exs#780.itm(1)} {ACC1:exs#780.itm(2)} -attr xrf 25039 -attr oid 335 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#780.itm}
+load net {ACC1:conc#601.itm(0)} -attr vt d
+load net {ACC1:conc#601.itm(1)} -attr vt d
+load netBundle {ACC1:conc#601.itm} 2 {ACC1:conc#601.itm(0)} {ACC1:conc#601.itm(1)} -attr xrf 25040 -attr oid 336 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#601.itm}
+load net {ACC1:acc#291.itm(0)} -attr vt d
+load net {ACC1:acc#291.itm(1)} -attr vt d
+load net {ACC1:acc#291.itm(2)} -attr vt d
+load net {ACC1:acc#291.itm(3)} -attr vt d
+load net {ACC1:acc#291.itm(4)} -attr vt d
+load net {ACC1:acc#291.itm(5)} -attr vt d
+load net {ACC1:acc#291.itm(6)} -attr vt d
+load net {ACC1:acc#291.itm(7)} -attr vt d
+load net {ACC1:acc#291.itm(8)} -attr vt d
+load net {ACC1:acc#291.itm(9)} -attr vt d
+load netBundle {ACC1:acc#291.itm} 10 {ACC1:acc#291.itm(0)} {ACC1:acc#291.itm(1)} {ACC1:acc#291.itm(2)} {ACC1:acc#291.itm(3)} {ACC1:acc#291.itm(4)} {ACC1:acc#291.itm(5)} {ACC1:acc#291.itm(6)} {ACC1:acc#291.itm(7)} {ACC1:acc#291.itm(8)} {ACC1:acc#291.itm(9)} -attr xrf 25041 -attr oid 337 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#289.itm(0)} -attr vt d
+load net {ACC1:acc#289.itm(1)} -attr vt d
+load net {ACC1:acc#289.itm(2)} -attr vt d
+load net {ACC1:acc#289.itm(3)} -attr vt d
+load net {ACC1:acc#289.itm(4)} -attr vt d
+load net {ACC1:acc#289.itm(5)} -attr vt d
+load net {ACC1:acc#289.itm(6)} -attr vt d
+load net {ACC1:acc#289.itm(7)} -attr vt d
+load netBundle {ACC1:acc#289.itm} 8 {ACC1:acc#289.itm(0)} {ACC1:acc#289.itm(1)} {ACC1:acc#289.itm(2)} {ACC1:acc#289.itm(3)} {ACC1:acc#289.itm(4)} {ACC1:acc#289.itm(5)} {ACC1:acc#289.itm(6)} {ACC1:acc#289.itm(7)} -attr xrf 25042 -attr oid 338 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#286.itm(0)} -attr vt d
+load net {ACC1:acc#286.itm(1)} -attr vt d
+load net {ACC1:acc#286.itm(2)} -attr vt d
+load net {ACC1:acc#286.itm(3)} -attr vt d
+load net {ACC1:acc#286.itm(4)} -attr vt d
+load net {ACC1:acc#286.itm(5)} -attr vt d
+load netBundle {ACC1:acc#286.itm} 6 {ACC1:acc#286.itm(0)} {ACC1:acc#286.itm(1)} {ACC1:acc#286.itm(2)} {ACC1:acc#286.itm(3)} {ACC1:acc#286.itm(4)} {ACC1:acc#286.itm(5)} -attr xrf 25043 -attr oid 339 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#283.itm(0)} -attr vt d
+load net {ACC1:acc#283.itm(1)} -attr vt d
+load net {ACC1:acc#283.itm(2)} -attr vt d
+load net {ACC1:acc#283.itm(3)} -attr vt d
+load netBundle {ACC1:acc#283.itm} 4 {ACC1:acc#283.itm(0)} {ACC1:acc#283.itm(1)} {ACC1:acc#283.itm(2)} {ACC1:acc#283.itm(3)} -attr xrf 25044 -attr oid 340 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#278.itm(0)} -attr vt d
+load net {ACC1:acc#278.itm(1)} -attr vt d
+load net {ACC1:acc#278.itm(2)} -attr vt d
+load netBundle {ACC1:acc#278.itm} 3 {ACC1:acc#278.itm(0)} {ACC1:acc#278.itm(1)} {ACC1:acc#278.itm(2)} -attr xrf 25045 -attr oid 341 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:slc#75.itm(0)} -attr vt d
+load net {ACC1:slc#75.itm(1)} -attr vt d
+load net {ACC1:slc#75.itm(2)} -attr vt d
+load netBundle {ACC1:slc#75.itm} 3 {ACC1:slc#75.itm(0)} {ACC1:slc#75.itm(1)} {ACC1:slc#75.itm(2)} -attr xrf 25046 -attr oid 342 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#75.itm}
+load net {ACC1:acc#269.itm(0)} -attr vt d
+load net {ACC1:acc#269.itm(1)} -attr vt d
+load net {ACC1:acc#269.itm(2)} -attr vt d
+load net {ACC1:acc#269.itm(3)} -attr vt d
+load netBundle {ACC1:acc#269.itm} 4 {ACC1:acc#269.itm(0)} {ACC1:acc#269.itm(1)} {ACC1:acc#269.itm(2)} {ACC1:acc#269.itm(3)} -attr xrf 25047 -attr oid 343 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {conc#631.itm(0)} -attr vt d
+load net {conc#631.itm(1)} -attr vt d
+load net {conc#631.itm(2)} -attr vt d
+load netBundle {conc#631.itm} 3 {conc#631.itm(0)} {conc#631.itm(1)} {conc#631.itm(2)} -attr xrf 25048 -attr oid 344 -attr vt d -attr @path {/sobel/sobel:core/conc#631.itm}
+load net {ACC1:conc#597.itm(0)} -attr vt d
+load net {ACC1:conc#597.itm(1)} -attr vt d
+load netBundle {ACC1:conc#597.itm} 2 {ACC1:conc#597.itm(0)} {ACC1:conc#597.itm(1)} -attr xrf 25049 -attr oid 345 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#597.itm}
+load net {slc(ACC1:acc#120.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#120.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#120.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#120.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#120.psp#1.sva)#2.itm(1)} -attr xrf 25050 -attr oid 346 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp#1.sva)#2.itm}
+load net {ACC1:slc#76.itm(0)} -attr vt d
+load net {ACC1:slc#76.itm(1)} -attr vt d
+load net {ACC1:slc#76.itm(2)} -attr vt d
+load net {ACC1:slc#76.itm(3)} -attr vt d
+load netBundle {ACC1:slc#76.itm} 4 {ACC1:slc#76.itm(0)} {ACC1:slc#76.itm(1)} {ACC1:slc#76.itm(2)} {ACC1:slc#76.itm(3)} -attr xrf 25051 -attr oid 347 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#76.itm}
+load net {ACC1:acc#270.itm(0)} -attr vt d
+load net {ACC1:acc#270.itm(1)} -attr vt d
+load net {ACC1:acc#270.itm(2)} -attr vt d
+load net {ACC1:acc#270.itm(3)} -attr vt d
+load net {ACC1:acc#270.itm(4)} -attr vt d
+load netBundle {ACC1:acc#270.itm} 5 {ACC1:acc#270.itm(0)} {ACC1:acc#270.itm(1)} {ACC1:acc#270.itm(2)} {ACC1:acc#270.itm(3)} {ACC1:acc#270.itm(4)} -attr xrf 25052 -attr oid 348 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {conc#632.itm(0)} -attr vt d
+load net {conc#632.itm(1)} -attr vt d
+load net {conc#632.itm(2)} -attr vt d
+load netBundle {conc#632.itm} 3 {conc#632.itm(0)} {conc#632.itm(1)} {conc#632.itm(2)} -attr xrf 25053 -attr oid 349 -attr vt d -attr @path {/sobel/sobel:core/conc#632.itm}
+load net {ACC1:conc#599.itm(0)} -attr vt d
+load net {ACC1:conc#599.itm(1)} -attr vt d
+load net {ACC1:conc#599.itm(2)} -attr vt d
+load netBundle {ACC1:conc#599.itm} 3 {ACC1:conc#599.itm(0)} {ACC1:conc#599.itm(1)} {ACC1:conc#599.itm(2)} -attr xrf 25054 -attr oid 350 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#599.itm}
+load net {ACC1:acc#282.itm(0)} -attr vt d
+load net {ACC1:acc#282.itm(1)} -attr vt d
+load net {ACC1:acc#282.itm(2)} -attr vt d
+load net {ACC1:acc#282.itm(3)} -attr vt d
+load net {ACC1:acc#282.itm(4)} -attr vt d
+load netBundle {ACC1:acc#282.itm} 5 {ACC1:acc#282.itm(0)} {ACC1:acc#282.itm(1)} {ACC1:acc#282.itm(2)} {ACC1:acc#282.itm(3)} {ACC1:acc#282.itm(4)} -attr xrf 25055 -attr oid 351 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1-1:conc#284.itm(0)} -attr vt d
+load net {ACC1-1:conc#284.itm(1)} -attr vt d
+load net {ACC1-1:conc#284.itm(2)} -attr vt d
+load net {ACC1-1:conc#284.itm(3)} -attr vt d
+load netBundle {ACC1-1:conc#284.itm} 4 {ACC1-1:conc#284.itm(0)} {ACC1-1:conc#284.itm(1)} {ACC1-1:conc#284.itm(2)} {ACC1-1:conc#284.itm(3)} -attr xrf 25056 -attr oid 352 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#284.itm}
+load net {ACC1-1:exs#550.itm(0)} -attr vt d
+load net {ACC1-1:exs#550.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#550.itm} 2 {ACC1-1:exs#550.itm(0)} {ACC1-1:exs#550.itm(1)} -attr xrf 25057 -attr oid 353 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#550.itm}
+load net {conc#633.itm(0)} -attr vt d
+load net {conc#633.itm(1)} -attr vt d
+load net {conc#633.itm(2)} -attr vt d
+load net {conc#633.itm(3)} -attr vt d
+load net {conc#633.itm(4)} -attr vt d
+load net {conc#633.itm(5)} -attr vt d
+load net {conc#633.itm(6)} -attr vt d
+load netBundle {conc#633.itm} 7 {conc#633.itm(0)} {conc#633.itm(1)} {conc#633.itm(2)} {conc#633.itm(3)} {conc#633.itm(4)} {conc#633.itm(5)} {conc#633.itm(6)} -attr xrf 25058 -attr oid 354 -attr vt d -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {ACC1:acc#288.itm(0)} -attr vt d
+load net {ACC1:acc#288.itm(1)} -attr vt d
+load net {ACC1:acc#288.itm(2)} -attr vt d
+load net {ACC1:acc#288.itm(3)} -attr vt d
+load net {ACC1:acc#288.itm(4)} -attr vt d
+load net {ACC1:acc#288.itm(5)} -attr vt d
+load net {ACC1:acc#288.itm(6)} -attr vt d
+load net {ACC1:acc#288.itm(7)} -attr vt d
+load netBundle {ACC1:acc#288.itm} 8 {ACC1:acc#288.itm(0)} {ACC1:acc#288.itm(1)} {ACC1:acc#288.itm(2)} {ACC1:acc#288.itm(3)} {ACC1:acc#288.itm(4)} {ACC1:acc#288.itm(5)} {ACC1:acc#288.itm(6)} {ACC1:acc#288.itm(7)} -attr xrf 25059 -attr oid 355 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1-1:exs#544.itm(0)} -attr vt d
+load net {ACC1-1:exs#544.itm(1)} -attr vt d
+load net {ACC1-1:exs#544.itm(2)} -attr vt d
+load net {ACC1-1:exs#544.itm(3)} -attr vt d
+load net {ACC1-1:exs#544.itm(4)} -attr vt d
+load net {ACC1-1:exs#544.itm(5)} -attr vt d
+load net {ACC1-1:exs#544.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#544.itm} 7 {ACC1-1:exs#544.itm(0)} {ACC1-1:exs#544.itm(1)} {ACC1-1:exs#544.itm(2)} {ACC1-1:exs#544.itm(3)} {ACC1-1:exs#544.itm(4)} {ACC1-1:exs#544.itm(5)} {ACC1-1:exs#544.itm(6)} -attr xrf 25060 -attr oid 356 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {ACC1-1:conc#254.itm(0)} -attr vt d
+load net {ACC1-1:conc#254.itm(1)} -attr vt d
+load net {ACC1-1:conc#254.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#254.itm} 3 {ACC1-1:conc#254.itm(0)} {ACC1-1:conc#254.itm(1)} {ACC1-1:conc#254.itm(2)} -attr xrf 25061 -attr oid 357 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#254.itm}
+load net {ACC1-1:exs#545.itm(0)} -attr vt d
+load net {ACC1-1:exs#545.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#545.itm} 2 {ACC1-1:exs#545.itm(0)} {ACC1-1:exs#545.itm(1)} -attr xrf 25062 -attr oid 358 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#545.itm}
+load net {ACC1:acc#285.itm(0)} -attr vt d
+load net {ACC1:acc#285.itm(1)} -attr vt d
+load net {ACC1:acc#285.itm(2)} -attr vt d
+load net {ACC1:acc#285.itm(3)} -attr vt d
+load net {ACC1:acc#285.itm(4)} -attr vt d
+load net {ACC1:acc#285.itm(5)} -attr vt d
+load netBundle {ACC1:acc#285.itm} 6 {ACC1:acc#285.itm(0)} {ACC1:acc#285.itm(1)} {ACC1:acc#285.itm(2)} {ACC1:acc#285.itm(3)} {ACC1:acc#285.itm(4)} {ACC1:acc#285.itm(5)} -attr xrf 25063 -attr oid 359 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {conc#634.itm(0)} -attr vt d
+load net {conc#634.itm(1)} -attr vt d
+load net {conc#634.itm(2)} -attr vt d
+load net {conc#634.itm(3)} -attr vt d
+load net {conc#634.itm(4)} -attr vt d
+load netBundle {conc#634.itm} 5 {conc#634.itm(0)} {conc#634.itm(1)} {conc#634.itm(2)} {conc#634.itm(3)} {conc#634.itm(4)} -attr xrf 25064 -attr oid 360 -attr vt d -attr @path {/sobel/sobel:core/conc#634.itm}
+load net {ACC1:acc#281.itm(0)} -attr vt d
+load net {ACC1:acc#281.itm(1)} -attr vt d
+load net {ACC1:acc#281.itm(2)} -attr vt d
+load net {ACC1:acc#281.itm(3)} -attr vt d
+load netBundle {ACC1:acc#281.itm} 4 {ACC1:acc#281.itm(0)} {ACC1:acc#281.itm(1)} {ACC1:acc#281.itm(2)} {ACC1:acc#281.itm(3)} -attr xrf 25065 -attr oid 361 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:slc#81.itm(0)} -attr vt d
+load net {ACC1:slc#81.itm(1)} -attr vt d
+load net {ACC1:slc#81.itm(2)} -attr vt d
+load netBundle {ACC1:slc#81.itm} 3 {ACC1:slc#81.itm(0)} {ACC1:slc#81.itm(1)} {ACC1:slc#81.itm(2)} -attr xrf 25066 -attr oid 362 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#81.itm}
+load net {ACC1:acc#275.itm(0)} -attr vt d
+load net {ACC1:acc#275.itm(1)} -attr vt d
+load net {ACC1:acc#275.itm(2)} -attr vt d
+load net {ACC1:acc#275.itm(3)} -attr vt d
+load netBundle {ACC1:acc#275.itm} 4 {ACC1:acc#275.itm(0)} {ACC1:acc#275.itm(1)} {ACC1:acc#275.itm(2)} {ACC1:acc#275.itm(3)} -attr xrf 25067 -attr oid 363 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {exs#59.itm(0)} -attr vt d
+load net {exs#59.itm(1)} -attr vt d
+load net {exs#59.itm(2)} -attr vt d
+load netBundle {exs#59.itm} 3 {exs#59.itm(0)} {exs#59.itm(1)} {exs#59.itm(2)} -attr xrf 25068 -attr oid 364 -attr vt d -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {conc#635.itm(0)} -attr vt d
+load net {conc#635.itm(1)} -attr vt d
+load netBundle {conc#635.itm} 2 {conc#635.itm(0)} {conc#635.itm(1)} -attr xrf 25069 -attr oid 365 -attr vt d -attr @path {/sobel/sobel:core/conc#635.itm}
+load net {ACC1:exs#782.itm(0)} -attr vt d
+load net {ACC1:exs#782.itm(1)} -attr vt d
+load net {ACC1:exs#782.itm(2)} -attr vt d
+load netBundle {ACC1:exs#782.itm} 3 {ACC1:exs#782.itm(0)} {ACC1:exs#782.itm(1)} {ACC1:exs#782.itm(2)} -attr xrf 25070 -attr oid 366 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#782.itm}
+load net {ACC1:conc#609.itm(0)} -attr vt d
+load net {ACC1:conc#609.itm(1)} -attr vt d
+load netBundle {ACC1:conc#609.itm} 2 {ACC1:conc#609.itm(0)} {ACC1:conc#609.itm(1)} -attr xrf 25071 -attr oid 367 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#609.itm}
+load net {conc#637.itm(0)} -attr vt d
+load net {conc#637.itm(1)} -attr vt d
+load net {conc#637.itm(2)} -attr vt d
+load net {conc#637.itm(3)} -attr vt d
+load net {conc#637.itm(4)} -attr vt d
+load net {conc#637.itm(5)} -attr vt d
+load net {conc#637.itm(6)} -attr vt d
+load net {conc#637.itm(7)} -attr vt d
+load net {conc#637.itm(8)} -attr vt d
+load net {conc#637.itm(9)} -attr vt d
+load net {conc#637.itm(10)} -attr vt d
+load netBundle {conc#637.itm} 11 {conc#637.itm(0)} {conc#637.itm(1)} {conc#637.itm(2)} {conc#637.itm(3)} {conc#637.itm(4)} {conc#637.itm(5)} {conc#637.itm(6)} {conc#637.itm(7)} {conc#637.itm(8)} {conc#637.itm(9)} {conc#637.itm(10)} -attr xrf 25072 -attr oid 368 -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {ACC1:acc#346.itm(0)} -attr vt d
+load net {ACC1:acc#346.itm(1)} -attr vt d
+load net {ACC1:acc#346.itm(2)} -attr vt d
+load netBundle {ACC1:acc#346.itm} 3 {ACC1:acc#346.itm(0)} {ACC1:acc#346.itm(1)} {ACC1:acc#346.itm(2)} -attr xrf 25073 -attr oid 369 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:exs#849.itm(0)} -attr vt d
+load net {ACC1:exs#849.itm(1)} -attr vt d
+load netBundle {ACC1:exs#849.itm} 2 {ACC1:exs#849.itm(0)} {ACC1:exs#849.itm(1)} -attr xrf 25074 -attr oid 370 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#849.itm}
+load net {ACC1:acc#265.itm(0)} -attr vt d
+load net {ACC1:acc#265.itm(1)} -attr vt d
+load net {ACC1:acc#265.itm(2)} -attr vt d
+load net {ACC1:acc#265.itm(3)} -attr vt d
+load net {ACC1:acc#265.itm(4)} -attr vt d
+load net {ACC1:acc#265.itm(5)} -attr vt d
+load net {ACC1:acc#265.itm(6)} -attr vt d
+load net {ACC1:acc#265.itm(7)} -attr vt d
+load net {ACC1:acc#265.itm(8)} -attr vt d
+load net {ACC1:acc#265.itm(9)} -attr vt d
+load netBundle {ACC1:acc#265.itm} 10 {ACC1:acc#265.itm(0)} {ACC1:acc#265.itm(1)} {ACC1:acc#265.itm(2)} {ACC1:acc#265.itm(3)} {ACC1:acc#265.itm(4)} {ACC1:acc#265.itm(5)} {ACC1:acc#265.itm(6)} {ACC1:acc#265.itm(7)} {ACC1:acc#265.itm(8)} {ACC1:acc#265.itm(9)} -attr xrf 25075 -attr oid 371 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {conc#638.itm(0)} -attr vt d
+load net {conc#638.itm(1)} -attr vt d
+load net {conc#638.itm(2)} -attr vt d
+load net {conc#638.itm(3)} -attr vt d
+load net {conc#638.itm(4)} -attr vt d
+load net {conc#638.itm(5)} -attr vt d
+load net {conc#638.itm(6)} -attr vt d
+load net {conc#638.itm(7)} -attr vt d
+load net {conc#638.itm(8)} -attr vt d
+load netBundle {conc#638.itm} 9 {conc#638.itm(0)} {conc#638.itm(1)} {conc#638.itm(2)} {conc#638.itm(3)} {conc#638.itm(4)} {conc#638.itm(5)} {conc#638.itm(6)} {conc#638.itm(7)} {conc#638.itm(8)} -attr xrf 25076 -attr oid 372 -attr vt d -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {ACC1:acc#263.itm(0)} -attr vt d
+load net {ACC1:acc#263.itm(1)} -attr vt d
+load net {ACC1:acc#263.itm(2)} -attr vt d
+load net {ACC1:acc#263.itm(3)} -attr vt d
+load net {ACC1:acc#263.itm(4)} -attr vt d
+load net {ACC1:acc#263.itm(5)} -attr vt d
+load net {ACC1:acc#263.itm(6)} -attr vt d
+load net {ACC1:acc#263.itm(7)} -attr vt d
+load netBundle {ACC1:acc#263.itm} 8 {ACC1:acc#263.itm(0)} {ACC1:acc#263.itm(1)} {ACC1:acc#263.itm(2)} {ACC1:acc#263.itm(3)} {ACC1:acc#263.itm(4)} {ACC1:acc#263.itm(5)} {ACC1:acc#263.itm(6)} {ACC1:acc#263.itm(7)} -attr xrf 25077 -attr oid 373 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {conc#639.itm(0)} -attr vt d
+load net {conc#639.itm(1)} -attr vt d
+load net {conc#639.itm(2)} -attr vt d
+load net {conc#639.itm(3)} -attr vt d
+load net {conc#639.itm(4)} -attr vt d
+load net {conc#639.itm(5)} -attr vt d
+load net {conc#639.itm(6)} -attr vt d
+load net {conc#639.itm(7)} -attr vt d
+load netBundle {conc#639.itm} 8 {conc#639.itm(0)} {conc#639.itm(1)} {conc#639.itm(2)} {conc#639.itm(3)} {conc#639.itm(4)} {conc#639.itm(5)} {conc#639.itm(6)} {conc#639.itm(7)} -attr xrf 25078 -attr oid 374 -attr vt d -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {ACC1-3:exs#576.itm(0)} -attr vt d
+load net {ACC1-3:exs#576.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#576.itm} 2 {ACC1-3:exs#576.itm(0)} {ACC1-3:exs#576.itm(1)} -attr xrf 25079 -attr oid 375 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#576.itm}
+load net {ACC1:acc#260.itm(0)} -attr vt d
+load net {ACC1:acc#260.itm(1)} -attr vt d
+load net {ACC1:acc#260.itm(2)} -attr vt d
+load net {ACC1:acc#260.itm(3)} -attr vt d
+load net {ACC1:acc#260.itm(4)} -attr vt d
+load net {ACC1:acc#260.itm(5)} -attr vt d
+load net {ACC1:acc#260.itm(6)} -attr vt d
+load netBundle {ACC1:acc#260.itm} 7 {ACC1:acc#260.itm(0)} {ACC1:acc#260.itm(1)} {ACC1:acc#260.itm(2)} {ACC1:acc#260.itm(3)} {ACC1:acc#260.itm(4)} {ACC1:acc#260.itm(5)} {ACC1:acc#260.itm(6)} -attr xrf 25080 -attr oid 376 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {conc#640.itm(0)} -attr vt d
+load net {conc#640.itm(1)} -attr vt d
+load net {conc#640.itm(2)} -attr vt d
+load net {conc#640.itm(3)} -attr vt d
+load net {conc#640.itm(4)} -attr vt d
+load net {conc#640.itm(5)} -attr vt d
+load netBundle {conc#640.itm} 6 {conc#640.itm(0)} {conc#640.itm(1)} {conc#640.itm(2)} {conc#640.itm(3)} {conc#640.itm(4)} {conc#640.itm(5)} -attr xrf 25081 -attr oid 377 -attr vt d -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {ACC1-3:exs#579.itm(0)} -attr vt d
+load net {ACC1-3:exs#579.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#579.itm} 2 {ACC1-3:exs#579.itm(0)} {ACC1-3:exs#579.itm(1)} -attr xrf 25082 -attr oid 378 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#579.itm}
+load net {ACC1:acc#257.itm(0)} -attr vt d
+load net {ACC1:acc#257.itm(1)} -attr vt d
+load net {ACC1:acc#257.itm(2)} -attr vt d
+load net {ACC1:acc#257.itm(3)} -attr vt d
+load net {ACC1:acc#257.itm(4)} -attr vt d
+load netBundle {ACC1:acc#257.itm} 5 {ACC1:acc#257.itm(0)} {ACC1:acc#257.itm(1)} {ACC1:acc#257.itm(2)} {ACC1:acc#257.itm(3)} {ACC1:acc#257.itm(4)} -attr xrf 25083 -attr oid 379 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#253.itm(0)} -attr vt d
+load net {ACC1:acc#253.itm(1)} -attr vt d
+load net {ACC1:acc#253.itm(2)} -attr vt d
+load net {ACC1:acc#253.itm(3)} -attr vt d
+load netBundle {ACC1:acc#253.itm} 4 {ACC1:acc#253.itm(0)} {ACC1:acc#253.itm(1)} {ACC1:acc#253.itm(2)} {ACC1:acc#253.itm(3)} -attr xrf 25084 -attr oid 380 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:slc#73.itm(0)} -attr vt d
+load net {ACC1:slc#73.itm(1)} -attr vt d
+load net {ACC1:slc#73.itm(2)} -attr vt d
+load netBundle {ACC1:slc#73.itm} 3 {ACC1:slc#73.itm(0)} {ACC1:slc#73.itm(1)} {ACC1:slc#73.itm(2)} -attr xrf 25085 -attr oid 381 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#247.itm(0)} -attr vt d
+load net {ACC1:acc#247.itm(1)} -attr vt d
+load net {ACC1:acc#247.itm(2)} -attr vt d
+load net {ACC1:acc#247.itm(3)} -attr vt d
+load netBundle {ACC1:acc#247.itm} 4 {ACC1:acc#247.itm(0)} {ACC1:acc#247.itm(1)} {ACC1:acc#247.itm(2)} {ACC1:acc#247.itm(3)} -attr xrf 25086 -attr oid 382 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {exs#42.itm(0)} -attr vt d
+load net {exs#42.itm(1)} -attr vt d
+load net {exs#42.itm(2)} -attr vt d
+load netBundle {exs#42.itm} 3 {exs#42.itm(0)} {exs#42.itm(1)} {exs#42.itm(2)} -attr xrf 25087 -attr oid 383 -attr vt d -attr @path {/sobel/sobel:core/exs#42.itm}
+load net {conc#641.itm(0)} -attr vt d
+load net {conc#641.itm(1)} -attr vt d
+load netBundle {conc#641.itm} 2 {conc#641.itm(0)} {conc#641.itm(1)} -attr xrf 25088 -attr oid 384 -attr vt d -attr @path {/sobel/sobel:core/conc#641.itm}
+load net {ACC1:exs#785.itm(0)} -attr vt d
+load net {ACC1:exs#785.itm(1)} -attr vt d
+load net {ACC1:exs#785.itm(2)} -attr vt d
+load netBundle {ACC1:exs#785.itm} 3 {ACC1:exs#785.itm(0)} {ACC1:exs#785.itm(1)} {ACC1:exs#785.itm(2)} -attr xrf 25089 -attr oid 385 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#785.itm}
+load net {ACC1:conc#592.itm(0)} -attr vt d
+load net {ACC1:conc#592.itm(1)} -attr vt d
+load netBundle {ACC1:conc#592.itm} 2 {ACC1:conc#592.itm(0)} {ACC1:conc#592.itm(1)} -attr xrf 25090 -attr oid 386 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#592.itm}
+load net {ACC1:slc#72.itm(0)} -attr vt d
+load net {ACC1:slc#72.itm(1)} -attr vt d
+load net {ACC1:slc#72.itm(2)} -attr vt d
+load netBundle {ACC1:slc#72.itm} 3 {ACC1:slc#72.itm(0)} {ACC1:slc#72.itm(1)} {ACC1:slc#72.itm(2)} -attr xrf 25091 -attr oid 387 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#246.itm(0)} -attr vt d
+load net {ACC1:acc#246.itm(1)} -attr vt d
+load net {ACC1:acc#246.itm(2)} -attr vt d
+load net {ACC1:acc#246.itm(3)} -attr vt d
+load netBundle {ACC1:acc#246.itm} 4 {ACC1:acc#246.itm(0)} {ACC1:acc#246.itm(1)} {ACC1:acc#246.itm(2)} {ACC1:acc#246.itm(3)} -attr xrf 25092 -attr oid 388 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {exs#43.itm(0)} -attr vt d
+load net {exs#43.itm(1)} -attr vt d
+load net {exs#43.itm(2)} -attr vt d
+load netBundle {exs#43.itm} 3 {exs#43.itm(0)} {exs#43.itm(1)} {exs#43.itm(2)} -attr xrf 25093 -attr oid 389 -attr vt d -attr @path {/sobel/sobel:core/exs#43.itm}
+load net {conc#642.itm(0)} -attr vt d
+load net {conc#642.itm(1)} -attr vt d
+load netBundle {conc#642.itm} 2 {conc#642.itm(0)} {conc#642.itm(1)} -attr xrf 25094 -attr oid 390 -attr vt d -attr @path {/sobel/sobel:core/conc#642.itm}
+load net {ACC1:exs#787.itm(0)} -attr vt d
+load net {ACC1:exs#787.itm(1)} -attr vt d
+load net {ACC1:exs#787.itm(2)} -attr vt d
+load netBundle {ACC1:exs#787.itm} 3 {ACC1:exs#787.itm(0)} {ACC1:exs#787.itm(1)} {ACC1:exs#787.itm(2)} -attr xrf 25095 -attr oid 391 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#787.itm}
+load net {ACC1:conc#590.itm(0)} -attr vt d
+load net {ACC1:conc#590.itm(1)} -attr vt d
+load netBundle {ACC1:conc#590.itm} 2 {ACC1:conc#590.itm(0)} {ACC1:conc#590.itm(1)} -attr xrf 25096 -attr oid 392 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#590.itm}
+load net {ACC1:acc#252.itm(0)} -attr vt d
+load net {ACC1:acc#252.itm(1)} -attr vt d
+load net {ACC1:acc#252.itm(2)} -attr vt d
+load net {ACC1:acc#252.itm(3)} -attr vt d
+load netBundle {ACC1:acc#252.itm} 4 {ACC1:acc#252.itm(0)} {ACC1:acc#252.itm(1)} {ACC1:acc#252.itm(2)} {ACC1:acc#252.itm(3)} -attr xrf 25097 -attr oid 393 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:slc#71.itm(0)} -attr vt d
+load net {ACC1:slc#71.itm(1)} -attr vt d
+load net {ACC1:slc#71.itm(2)} -attr vt d
+load netBundle {ACC1:slc#71.itm} 3 {ACC1:slc#71.itm(0)} {ACC1:slc#71.itm(1)} {ACC1:slc#71.itm(2)} -attr xrf 25098 -attr oid 394 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#71.itm}
+load net {ACC1:acc#245.itm(0)} -attr vt d
+load net {ACC1:acc#245.itm(1)} -attr vt d
+load net {ACC1:acc#245.itm(2)} -attr vt d
+load net {ACC1:acc#245.itm(3)} -attr vt d
+load netBundle {ACC1:acc#245.itm} 4 {ACC1:acc#245.itm(0)} {ACC1:acc#245.itm(1)} {ACC1:acc#245.itm(2)} {ACC1:acc#245.itm(3)} -attr xrf 25099 -attr oid 395 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {exs#44.itm(0)} -attr vt d
+load net {exs#44.itm(1)} -attr vt d
+load net {exs#44.itm(2)} -attr vt d
+load netBundle {exs#44.itm} 3 {exs#44.itm(0)} {exs#44.itm(1)} {exs#44.itm(2)} -attr xrf 25100 -attr oid 396 -attr vt d -attr @path {/sobel/sobel:core/exs#44.itm}
+load net {conc#643.itm(0)} -attr vt d
+load net {conc#643.itm(1)} -attr vt d
+load netBundle {conc#643.itm} 2 {conc#643.itm(0)} {conc#643.itm(1)} -attr xrf 25101 -attr oid 397 -attr vt d -attr @path {/sobel/sobel:core/conc#643.itm}
+load net {ACC1:exs#789.itm(0)} -attr vt d
+load net {ACC1:exs#789.itm(1)} -attr vt d
+load net {ACC1:exs#789.itm(2)} -attr vt d
+load netBundle {ACC1:exs#789.itm} 3 {ACC1:exs#789.itm(0)} {ACC1:exs#789.itm(1)} {ACC1:exs#789.itm(2)} -attr xrf 25102 -attr oid 398 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#789.itm}
+load net {ACC1:conc#588.itm(0)} -attr vt d
+load net {ACC1:conc#588.itm(1)} -attr vt d
+load netBundle {ACC1:conc#588.itm} 2 {ACC1:conc#588.itm(0)} {ACC1:conc#588.itm(1)} -attr xrf 25103 -attr oid 399 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#588.itm}
+load net {ACC1:slc#70.itm(0)} -attr vt d
+load net {ACC1:slc#70.itm(1)} -attr vt d
+load net {ACC1:slc#70.itm(2)} -attr vt d
+load netBundle {ACC1:slc#70.itm} 3 {ACC1:slc#70.itm(0)} {ACC1:slc#70.itm(1)} {ACC1:slc#70.itm(2)} -attr xrf 25104 -attr oid 400 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#70.itm}
+load net {ACC1:acc#244.itm(0)} -attr vt d
+load net {ACC1:acc#244.itm(1)} -attr vt d
+load net {ACC1:acc#244.itm(2)} -attr vt d
+load net {ACC1:acc#244.itm(3)} -attr vt d
+load netBundle {ACC1:acc#244.itm} 4 {ACC1:acc#244.itm(0)} {ACC1:acc#244.itm(1)} {ACC1:acc#244.itm(2)} {ACC1:acc#244.itm(3)} -attr xrf 25105 -attr oid 401 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#244.itm}
+load net {exs#45.itm(0)} -attr vt d
+load net {exs#45.itm(1)} -attr vt d
+load net {exs#45.itm(2)} -attr vt d
+load netBundle {exs#45.itm} 3 {exs#45.itm(0)} {exs#45.itm(1)} {exs#45.itm(2)} -attr xrf 25106 -attr oid 402 -attr vt d -attr @path {/sobel/sobel:core/exs#45.itm}
+load net {conc#644.itm(0)} -attr vt d
+load net {conc#644.itm(1)} -attr vt d
+load netBundle {conc#644.itm} 2 {conc#644.itm(0)} {conc#644.itm(1)} -attr xrf 25107 -attr oid 403 -attr vt d -attr @path {/sobel/sobel:core/conc#644.itm}
+load net {ACC1:exs#791.itm(0)} -attr vt d
+load net {ACC1:exs#791.itm(1)} -attr vt d
+load net {ACC1:exs#791.itm(2)} -attr vt d
+load netBundle {ACC1:exs#791.itm} 3 {ACC1:exs#791.itm(0)} {ACC1:exs#791.itm(1)} {ACC1:exs#791.itm(2)} -attr xrf 25108 -attr oid 404 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#791.itm}
+load net {ACC1:conc#586.itm(0)} -attr vt d
+load net {ACC1:conc#586.itm(1)} -attr vt d
+load netBundle {ACC1:conc#586.itm} 2 {ACC1:conc#586.itm(0)} {ACC1:conc#586.itm(1)} -attr xrf 25109 -attr oid 405 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#586.itm}
+load net {FRAME:for:acc#24.itm(0)} -attr vt d
+load net {FRAME:for:acc#24.itm(1)} -attr vt d
+load net {FRAME:for:acc#24.itm(2)} -attr vt d
+load net {FRAME:for:acc#24.itm(3)} -attr vt d
+load net {FRAME:for:acc#24.itm(4)} -attr vt d
+load net {FRAME:for:acc#24.itm(5)} -attr vt d
+load net {FRAME:for:acc#24.itm(6)} -attr vt d
+load net {FRAME:for:acc#24.itm(7)} -attr vt d
+load net {FRAME:for:acc#24.itm(8)} -attr vt d
+load net {FRAME:for:acc#24.itm(9)} -attr vt d
+load net {FRAME:for:acc#24.itm(10)} -attr vt d
+load net {FRAME:for:acc#24.itm(11)} -attr vt d
+load net {FRAME:for:acc#24.itm(12)} -attr vt d
+load netBundle {FRAME:for:acc#24.itm} 13 {FRAME:for:acc#24.itm(0)} {FRAME:for:acc#24.itm(1)} {FRAME:for:acc#24.itm(2)} {FRAME:for:acc#24.itm(3)} {FRAME:for:acc#24.itm(4)} {FRAME:for:acc#24.itm(5)} {FRAME:for:acc#24.itm(6)} {FRAME:for:acc#24.itm(7)} {FRAME:for:acc#24.itm(8)} {FRAME:for:acc#24.itm(9)} {FRAME:for:acc#24.itm(10)} {FRAME:for:acc#24.itm(11)} {FRAME:for:acc#24.itm(12)} -attr xrf 25110 -attr oid 406 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#23.itm(0)} -attr vt d
+load net {FRAME:for:acc#23.itm(1)} -attr vt d
+load net {FRAME:for:acc#23.itm(2)} -attr vt d
+load net {FRAME:for:acc#23.itm(3)} -attr vt d
+load net {FRAME:for:acc#23.itm(4)} -attr vt d
+load net {FRAME:for:acc#23.itm(5)} -attr vt d
+load net {FRAME:for:acc#23.itm(6)} -attr vt d
+load net {FRAME:for:acc#23.itm(7)} -attr vt d
+load net {FRAME:for:acc#23.itm(8)} -attr vt d
+load net {FRAME:for:acc#23.itm(9)} -attr vt d
+load net {FRAME:for:acc#23.itm(10)} -attr vt d
+load net {FRAME:for:acc#23.itm(11)} -attr vt d
+load net {FRAME:for:acc#23.itm(12)} -attr vt d
+load netBundle {FRAME:for:acc#23.itm} 13 {FRAME:for:acc#23.itm(0)} {FRAME:for:acc#23.itm(1)} {FRAME:for:acc#23.itm(2)} {FRAME:for:acc#23.itm(3)} {FRAME:for:acc#23.itm(4)} {FRAME:for:acc#23.itm(5)} {FRAME:for:acc#23.itm(6)} {FRAME:for:acc#23.itm(7)} {FRAME:for:acc#23.itm(8)} {FRAME:for:acc#23.itm(9)} {FRAME:for:acc#23.itm(10)} {FRAME:for:acc#23.itm(11)} {FRAME:for:acc#23.itm(12)} -attr xrf 25111 -attr oid 407 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:mul#1.itm(0)} -attr vt d
+load net {FRAME:for:mul#1.itm(1)} -attr vt d
+load net {FRAME:for:mul#1.itm(2)} -attr vt d
+load net {FRAME:for:mul#1.itm(3)} -attr vt d
+load net {FRAME:for:mul#1.itm(4)} -attr vt d
+load net {FRAME:for:mul#1.itm(5)} -attr vt d
+load net {FRAME:for:mul#1.itm(6)} -attr vt d
+load net {FRAME:for:mul#1.itm(7)} -attr vt d
+load net {FRAME:for:mul#1.itm(8)} -attr vt d
+load net {FRAME:for:mul#1.itm(9)} -attr vt d
+load net {FRAME:for:mul#1.itm(10)} -attr vt d
+load net {FRAME:for:mul#1.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul#1.itm} 12 {FRAME:for:mul#1.itm(0)} {FRAME:for:mul#1.itm(1)} {FRAME:for:mul#1.itm(2)} {FRAME:for:mul#1.itm(3)} {FRAME:for:mul#1.itm(4)} {FRAME:for:mul#1.itm(5)} {FRAME:for:mul#1.itm(6)} {FRAME:for:mul#1.itm(7)} {FRAME:for:mul#1.itm(8)} {FRAME:for:mul#1.itm(9)} {FRAME:for:mul#1.itm(10)} {FRAME:for:mul#1.itm(11)} -attr xrf 25112 -attr oid 408 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {regs.operator[]#10:mux.itm(0)} -attr vt d
+load net {regs.operator[]#10:mux.itm(1)} -attr vt d
+load net {regs.operator[]#10:mux.itm(2)} -attr vt d
+load net {regs.operator[]#10:mux.itm(3)} -attr vt d
+load net {regs.operator[]#10:mux.itm(4)} -attr vt d
+load net {regs.operator[]#10:mux.itm(5)} -attr vt d
+load net {regs.operator[]#10:mux.itm(6)} -attr vt d
+load net {regs.operator[]#10:mux.itm(7)} -attr vt d
+load net {regs.operator[]#10:mux.itm(8)} -attr vt d
+load net {regs.operator[]#10:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#10:mux.itm} 10 {regs.operator[]#10:mux.itm(0)} {regs.operator[]#10:mux.itm(1)} {regs.operator[]#10:mux.itm(2)} {regs.operator[]#10:mux.itm(3)} {regs.operator[]#10:mux.itm(4)} {regs.operator[]#10:mux.itm(5)} {regs.operator[]#10:mux.itm(6)} {regs.operator[]#10:mux.itm(7)} {regs.operator[]#10:mux.itm(8)} {regs.operator[]#10:mux.itm(9)} -attr xrf 25113 -attr oid 409 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm} 10 {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(0)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(1)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(2)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(3)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(4)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(5)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(6)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(7)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(8)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(9)} -attr xrf 25114 -attr oid 410 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr xrf 25115 -attr oid 411 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr xrf 25116 -attr oid 412 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {conc#645.itm(0)} -attr vt d
+load net {conc#645.itm(1)} -attr vt d
+load netBundle {conc#645.itm} 2 {conc#645.itm(0)} {conc#645.itm(1)} -attr xrf 25117 -attr oid 413 -attr vt d -attr @path {/sobel/sobel:core/conc#645.itm}
+load net {FRAME:for:mul#2.itm(0)} -attr vt d
+load net {FRAME:for:mul#2.itm(1)} -attr vt d
+load net {FRAME:for:mul#2.itm(2)} -attr vt d
+load net {FRAME:for:mul#2.itm(3)} -attr vt d
+load net {FRAME:for:mul#2.itm(4)} -attr vt d
+load net {FRAME:for:mul#2.itm(5)} -attr vt d
+load net {FRAME:for:mul#2.itm(6)} -attr vt d
+load net {FRAME:for:mul#2.itm(7)} -attr vt d
+load net {FRAME:for:mul#2.itm(8)} -attr vt d
+load net {FRAME:for:mul#2.itm(9)} -attr vt d
+load net {FRAME:for:mul#2.itm(10)} -attr vt d
+load net {FRAME:for:mul#2.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul#2.itm} 12 {FRAME:for:mul#2.itm(0)} {FRAME:for:mul#2.itm(1)} {FRAME:for:mul#2.itm(2)} {FRAME:for:mul#2.itm(3)} {FRAME:for:mul#2.itm(4)} {FRAME:for:mul#2.itm(5)} {FRAME:for:mul#2.itm(6)} {FRAME:for:mul#2.itm(7)} {FRAME:for:mul#2.itm(8)} {FRAME:for:mul#2.itm(9)} {FRAME:for:mul#2.itm(10)} {FRAME:for:mul#2.itm(11)} -attr xrf 25118 -attr oid 414 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {regs.operator[]#11:mux.itm(0)} -attr vt d
+load net {regs.operator[]#11:mux.itm(1)} -attr vt d
+load net {regs.operator[]#11:mux.itm(2)} -attr vt d
+load net {regs.operator[]#11:mux.itm(3)} -attr vt d
+load net {regs.operator[]#11:mux.itm(4)} -attr vt d
+load net {regs.operator[]#11:mux.itm(5)} -attr vt d
+load net {regs.operator[]#11:mux.itm(6)} -attr vt d
+load net {regs.operator[]#11:mux.itm(7)} -attr vt d
+load net {regs.operator[]#11:mux.itm(8)} -attr vt d
+load net {regs.operator[]#11:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#11:mux.itm} 10 {regs.operator[]#11:mux.itm(0)} {regs.operator[]#11:mux.itm(1)} {regs.operator[]#11:mux.itm(2)} {regs.operator[]#11:mux.itm(3)} {regs.operator[]#11:mux.itm(4)} {regs.operator[]#11:mux.itm(5)} {regs.operator[]#11:mux.itm(6)} {regs.operator[]#11:mux.itm(7)} {regs.operator[]#11:mux.itm(8)} {regs.operator[]#11:mux.itm(9)} -attr xrf 25119 -attr oid 415 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm} 10 {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(0)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(1)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(2)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(3)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(4)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(5)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(6)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(7)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(8)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(9)} -attr xrf 25120 -attr oid 416 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr xrf 25121 -attr oid 417 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr xrf 25122 -attr oid 418 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {conc#646.itm(0)} -attr vt d
+load net {conc#646.itm(1)} -attr vt d
+load netBundle {conc#646.itm} 2 {conc#646.itm(0)} {conc#646.itm(1)} -attr xrf 25123 -attr oid 419 -attr vt d -attr @path {/sobel/sobel:core/conc#646.itm}
+load net {FRAME:for:mul.itm(0)} -attr vt d
+load net {FRAME:for:mul.itm(1)} -attr vt d
+load net {FRAME:for:mul.itm(2)} -attr vt d
+load net {FRAME:for:mul.itm(3)} -attr vt d
+load net {FRAME:for:mul.itm(4)} -attr vt d
+load net {FRAME:for:mul.itm(5)} -attr vt d
+load net {FRAME:for:mul.itm(6)} -attr vt d
+load net {FRAME:for:mul.itm(7)} -attr vt d
+load net {FRAME:for:mul.itm(8)} -attr vt d
+load net {FRAME:for:mul.itm(9)} -attr vt d
+load net {FRAME:for:mul.itm(10)} -attr vt d
+load net {FRAME:for:mul.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul.itm} 12 {FRAME:for:mul.itm(0)} {FRAME:for:mul.itm(1)} {FRAME:for:mul.itm(2)} {FRAME:for:mul.itm(3)} {FRAME:for:mul.itm(4)} {FRAME:for:mul.itm(5)} {FRAME:for:mul.itm(6)} {FRAME:for:mul.itm(7)} {FRAME:for:mul.itm(8)} {FRAME:for:mul.itm(9)} {FRAME:for:mul.itm(10)} {FRAME:for:mul.itm(11)} -attr xrf 25124 -attr oid 420 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {regs.operator[]#9:mux.itm(0)} -attr vt d
+load net {regs.operator[]#9:mux.itm(1)} -attr vt d
+load net {regs.operator[]#9:mux.itm(2)} -attr vt d
+load net {regs.operator[]#9:mux.itm(3)} -attr vt d
+load net {regs.operator[]#9:mux.itm(4)} -attr vt d
+load net {regs.operator[]#9:mux.itm(5)} -attr vt d
+load net {regs.operator[]#9:mux.itm(6)} -attr vt d
+load net {regs.operator[]#9:mux.itm(7)} -attr vt d
+load net {regs.operator[]#9:mux.itm(8)} -attr vt d
+load net {regs.operator[]#9:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#9:mux.itm} 10 {regs.operator[]#9:mux.itm(0)} {regs.operator[]#9:mux.itm(1)} {regs.operator[]#9:mux.itm(2)} {regs.operator[]#9:mux.itm(3)} {regs.operator[]#9:mux.itm(4)} {regs.operator[]#9:mux.itm(5)} {regs.operator[]#9:mux.itm(6)} {regs.operator[]#9:mux.itm(7)} {regs.operator[]#9:mux.itm(8)} {regs.operator[]#9:mux.itm(9)} -attr xrf 25125 -attr oid 421 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm} 10 {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(0)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(1)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(2)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(3)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(4)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(5)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(6)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(7)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(8)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(9)} -attr xrf 25126 -attr oid 422 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr xrf 25127 -attr oid 423 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr xrf 25128 -attr oid 424 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {conc#647.itm(0)} -attr vt d
+load net {conc#647.itm(1)} -attr vt d
+load netBundle {conc#647.itm} 2 {conc#647.itm(0)} {conc#647.itm(1)} -attr xrf 25129 -attr oid 425 -attr vt d -attr @path {/sobel/sobel:core/conc#647.itm}
+load net {ACC1-3:acc#122.itm(0)} -attr vt d
+load net {ACC1-3:acc#122.itm(1)} -attr vt d
+load net {ACC1-3:acc#122.itm(2)} -attr vt d
+load net {ACC1-3:acc#122.itm(3)} -attr vt d
+load net {ACC1-3:acc#122.itm(4)} -attr vt d
+load net {ACC1-3:acc#122.itm(5)} -attr vt d
+load net {ACC1-3:acc#122.itm(6)} -attr vt d
+load net {ACC1-3:acc#122.itm(7)} -attr vt d
+load net {ACC1-3:acc#122.itm(8)} -attr vt d
+load net {ACC1-3:acc#122.itm(9)} -attr vt d
+load net {ACC1-3:acc#122.itm(10)} -attr vt d
+load net {ACC1-3:acc#122.itm(11)} -attr vt d
+load netBundle {ACC1-3:acc#122.itm} 12 {ACC1-3:acc#122.itm(0)} {ACC1-3:acc#122.itm(1)} {ACC1-3:acc#122.itm(2)} {ACC1-3:acc#122.itm(3)} {ACC1-3:acc#122.itm(4)} {ACC1-3:acc#122.itm(5)} {ACC1-3:acc#122.itm(6)} {ACC1-3:acc#122.itm(7)} {ACC1-3:acc#122.itm(8)} {ACC1-3:acc#122.itm(9)} {ACC1-3:acc#122.itm(10)} {ACC1-3:acc#122.itm(11)} -attr xrf 25130 -attr oid 426 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1:acc#215.itm(0)} -attr vt d
+load net {ACC1:acc#215.itm(1)} -attr vt d
+load net {ACC1:acc#215.itm(2)} -attr vt d
+load net {ACC1:acc#215.itm(3)} -attr vt d
+load net {ACC1:acc#215.itm(4)} -attr vt d
+load net {ACC1:acc#215.itm(5)} -attr vt d
+load net {ACC1:acc#215.itm(6)} -attr vt d
+load net {ACC1:acc#215.itm(7)} -attr vt d
+load net {ACC1:acc#215.itm(8)} -attr vt d
+load net {ACC1:acc#215.itm(9)} -attr vt d
+load net {ACC1:acc#215.itm(10)} -attr vt d
+load netBundle {ACC1:acc#215.itm} 11 {ACC1:acc#215.itm(0)} {ACC1:acc#215.itm(1)} {ACC1:acc#215.itm(2)} {ACC1:acc#215.itm(3)} {ACC1:acc#215.itm(4)} {ACC1:acc#215.itm(5)} {ACC1:acc#215.itm(6)} {ACC1:acc#215.itm(7)} {ACC1:acc#215.itm(8)} {ACC1:acc#215.itm(9)} {ACC1:acc#215.itm(10)} -attr xrf 25131 -attr oid 427 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {conc#648.itm(0)} -attr vt d
+load net {conc#648.itm(1)} -attr vt d
+load net {conc#648.itm(2)} -attr vt d
+load net {conc#648.itm(3)} -attr vt d
+load net {conc#648.itm(4)} -attr vt d
+load net {conc#648.itm(5)} -attr vt d
+load net {conc#648.itm(6)} -attr vt d
+load net {conc#648.itm(7)} -attr vt d
+load net {conc#648.itm(8)} -attr vt d
+load net {conc#648.itm(9)} -attr vt d
+load netBundle {conc#648.itm} 10 {conc#648.itm(0)} {conc#648.itm(1)} {conc#648.itm(2)} {conc#648.itm(3)} {conc#648.itm(4)} {conc#648.itm(5)} {conc#648.itm(6)} {conc#648.itm(7)} {conc#648.itm(8)} {conc#648.itm(9)} -attr xrf 25132 -attr oid 428 -attr vt d -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {ACC1:acc#213.itm(0)} -attr vt d
+load net {ACC1:acc#213.itm(1)} -attr vt d
+load net {ACC1:acc#213.itm(2)} -attr vt d
+load net {ACC1:acc#213.itm(3)} -attr vt d
+load net {ACC1:acc#213.itm(4)} -attr vt d
+load net {ACC1:acc#213.itm(5)} -attr vt d
+load net {ACC1:acc#213.itm(6)} -attr vt d
+load net {ACC1:acc#213.itm(7)} -attr vt d
+load net {ACC1:acc#213.itm(8)} -attr vt d
+load net {ACC1:acc#213.itm(9)} -attr vt d
+load net {ACC1:acc#213.itm(10)} -attr vt d
+load netBundle {ACC1:acc#213.itm} 11 {ACC1:acc#213.itm(0)} {ACC1:acc#213.itm(1)} {ACC1:acc#213.itm(2)} {ACC1:acc#213.itm(3)} {ACC1:acc#213.itm(4)} {ACC1:acc#213.itm(5)} {ACC1:acc#213.itm(6)} {ACC1:acc#213.itm(7)} {ACC1:acc#213.itm(8)} {ACC1:acc#213.itm(9)} {ACC1:acc#213.itm(10)} -attr xrf 25133 -attr oid 429 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#211.itm(0)} -attr vt d
+load net {ACC1:acc#211.itm(1)} -attr vt d
+load net {ACC1:acc#211.itm(2)} -attr vt d
+load net {ACC1:acc#211.itm(3)} -attr vt d
+load net {ACC1:acc#211.itm(4)} -attr vt d
+load net {ACC1:acc#211.itm(5)} -attr vt d
+load net {ACC1:acc#211.itm(6)} -attr vt d
+load net {ACC1:acc#211.itm(7)} -attr vt d
+load net {ACC1:acc#211.itm(8)} -attr vt d
+load net {ACC1:acc#211.itm(9)} -attr vt d
+load netBundle {ACC1:acc#211.itm} 10 {ACC1:acc#211.itm(0)} {ACC1:acc#211.itm(1)} {ACC1:acc#211.itm(2)} {ACC1:acc#211.itm(3)} {ACC1:acc#211.itm(4)} {ACC1:acc#211.itm(5)} {ACC1:acc#211.itm(6)} {ACC1:acc#211.itm(7)} {ACC1:acc#211.itm(8)} {ACC1:acc#211.itm(9)} -attr xrf 25134 -attr oid 430 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#209.itm(0)} -attr vt d
+load net {ACC1:acc#209.itm(1)} -attr vt d
+load net {ACC1:acc#209.itm(2)} -attr vt d
+load net {ACC1:acc#209.itm(3)} -attr vt d
+load net {ACC1:acc#209.itm(4)} -attr vt d
+load net {ACC1:acc#209.itm(5)} -attr vt d
+load net {ACC1:acc#209.itm(6)} -attr vt d
+load net {ACC1:acc#209.itm(7)} -attr vt d
+load netBundle {ACC1:acc#209.itm} 8 {ACC1:acc#209.itm(0)} {ACC1:acc#209.itm(1)} {ACC1:acc#209.itm(2)} {ACC1:acc#209.itm(3)} {ACC1:acc#209.itm(4)} {ACC1:acc#209.itm(5)} {ACC1:acc#209.itm(6)} {ACC1:acc#209.itm(7)} -attr xrf 25135 -attr oid 431 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#206.itm(0)} -attr vt d
+load net {ACC1:acc#206.itm(1)} -attr vt d
+load net {ACC1:acc#206.itm(2)} -attr vt d
+load net {ACC1:acc#206.itm(3)} -attr vt d
+load net {ACC1:acc#206.itm(4)} -attr vt d
+load net {ACC1:acc#206.itm(5)} -attr vt d
+load netBundle {ACC1:acc#206.itm} 6 {ACC1:acc#206.itm(0)} {ACC1:acc#206.itm(1)} {ACC1:acc#206.itm(2)} {ACC1:acc#206.itm(3)} {ACC1:acc#206.itm(4)} {ACC1:acc#206.itm(5)} -attr xrf 25136 -attr oid 432 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#203.itm(0)} -attr vt d
+load net {ACC1:acc#203.itm(1)} -attr vt d
+load net {ACC1:acc#203.itm(2)} -attr vt d
+load net {ACC1:acc#203.itm(3)} -attr vt d
+load netBundle {ACC1:acc#203.itm} 4 {ACC1:acc#203.itm(0)} {ACC1:acc#203.itm(1)} {ACC1:acc#203.itm(2)} {ACC1:acc#203.itm(3)} -attr xrf 25137 -attr oid 433 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#198.itm(0)} -attr vt d
+load net {ACC1:acc#198.itm(1)} -attr vt d
+load net {ACC1:acc#198.itm(2)} -attr vt d
+load netBundle {ACC1:acc#198.itm} 3 {ACC1:acc#198.itm(0)} {ACC1:acc#198.itm(1)} {ACC1:acc#198.itm(2)} -attr xrf 25138 -attr oid 434 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:slc#54.itm(0)} -attr vt d
+load net {ACC1:slc#54.itm(1)} -attr vt d
+load net {ACC1:slc#54.itm(2)} -attr vt d
+load netBundle {ACC1:slc#54.itm} 3 {ACC1:slc#54.itm(0)} {ACC1:slc#54.itm(1)} {ACC1:slc#54.itm(2)} -attr xrf 25139 -attr oid 435 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#54.itm}
+load net {ACC1:acc#189.itm(0)} -attr vt d
+load net {ACC1:acc#189.itm(1)} -attr vt d
+load net {ACC1:acc#189.itm(2)} -attr vt d
+load net {ACC1:acc#189.itm(3)} -attr vt d
+load netBundle {ACC1:acc#189.itm} 4 {ACC1:acc#189.itm(0)} {ACC1:acc#189.itm(1)} {ACC1:acc#189.itm(2)} {ACC1:acc#189.itm(3)} -attr xrf 25140 -attr oid 436 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {conc#649.itm(0)} -attr vt d
+load net {conc#649.itm(1)} -attr vt d
+load net {conc#649.itm(2)} -attr vt d
+load netBundle {conc#649.itm} 3 {conc#649.itm(0)} {conc#649.itm(1)} {conc#649.itm(2)} -attr xrf 25141 -attr oid 437 -attr vt d -attr @path {/sobel/sobel:core/conc#649.itm}
+load net {ACC1:conc#552.itm(0)} -attr vt d
+load net {ACC1:conc#552.itm(1)} -attr vt d
+load netBundle {ACC1:conc#552.itm} 2 {ACC1:conc#552.itm(0)} {ACC1:conc#552.itm(1)} -attr xrf 25142 -attr oid 438 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#552.itm}
+load net {slc(ACC1:acc#116.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#116.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#116.psp.sva)#2.itm} 2 {slc(ACC1:acc#116.psp.sva)#2.itm(0)} {slc(ACC1:acc#116.psp.sva)#2.itm(1)} -attr xrf 25143 -attr oid 439 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp.sva)#2.itm}
+load net {ACC1:slc#55.itm(0)} -attr vt d
+load net {ACC1:slc#55.itm(1)} -attr vt d
+load net {ACC1:slc#55.itm(2)} -attr vt d
+load net {ACC1:slc#55.itm(3)} -attr vt d
+load netBundle {ACC1:slc#55.itm} 4 {ACC1:slc#55.itm(0)} {ACC1:slc#55.itm(1)} {ACC1:slc#55.itm(2)} {ACC1:slc#55.itm(3)} -attr xrf 25144 -attr oid 440 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#55.itm}
+load net {ACC1:acc#190.itm(0)} -attr vt d
+load net {ACC1:acc#190.itm(1)} -attr vt d
+load net {ACC1:acc#190.itm(2)} -attr vt d
+load net {ACC1:acc#190.itm(3)} -attr vt d
+load net {ACC1:acc#190.itm(4)} -attr vt d
+load netBundle {ACC1:acc#190.itm} 5 {ACC1:acc#190.itm(0)} {ACC1:acc#190.itm(1)} {ACC1:acc#190.itm(2)} {ACC1:acc#190.itm(3)} {ACC1:acc#190.itm(4)} -attr xrf 25145 -attr oid 441 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load net {conc#650.itm(0)} -attr vt d
+load net {conc#650.itm(1)} -attr vt d
+load net {conc#650.itm(2)} -attr vt d
+load netBundle {conc#650.itm} 3 {conc#650.itm(0)} {conc#650.itm(1)} {conc#650.itm(2)} -attr xrf 25146 -attr oid 442 -attr vt d -attr @path {/sobel/sobel:core/conc#650.itm}
+load net {ACC1:conc#554.itm(0)} -attr vt d
+load net {ACC1:conc#554.itm(1)} -attr vt d
+load net {ACC1:conc#554.itm(2)} -attr vt d
+load netBundle {ACC1:conc#554.itm} 3 {ACC1:conc#554.itm(0)} {ACC1:conc#554.itm(1)} {ACC1:conc#554.itm(2)} -attr xrf 25147 -attr oid 443 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#554.itm}
+load net {ACC1:acc#202.itm(0)} -attr vt d
+load net {ACC1:acc#202.itm(1)} -attr vt d
+load net {ACC1:acc#202.itm(2)} -attr vt d
+load net {ACC1:acc#202.itm(3)} -attr vt d
+load net {ACC1:acc#202.itm(4)} -attr vt d
+load netBundle {ACC1:acc#202.itm} 5 {ACC1:acc#202.itm(0)} {ACC1:acc#202.itm(1)} {ACC1:acc#202.itm(2)} {ACC1:acc#202.itm(3)} {ACC1:acc#202.itm(4)} -attr xrf 25148 -attr oid 444 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1-3:conc#260.itm(0)} -attr vt d
+load net {ACC1-3:conc#260.itm(1)} -attr vt d
+load net {ACC1-3:conc#260.itm(2)} -attr vt d
+load net {ACC1-3:conc#260.itm(3)} -attr vt d
+load netBundle {ACC1-3:conc#260.itm} 4 {ACC1-3:conc#260.itm(0)} {ACC1-3:conc#260.itm(1)} {ACC1-3:conc#260.itm(2)} {ACC1-3:conc#260.itm(3)} -attr xrf 25149 -attr oid 445 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#260.itm}
+load net {ACC1-3:exs#559.itm(0)} -attr vt d
+load net {ACC1-3:exs#559.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#559.itm} 2 {ACC1-3:exs#559.itm(0)} {ACC1-3:exs#559.itm(1)} -attr xrf 25150 -attr oid 446 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#559.itm}
+load net {conc#651.itm(0)} -attr vt d
+load net {conc#651.itm(1)} -attr vt d
+load net {conc#651.itm(2)} -attr vt d
+load net {conc#651.itm(3)} -attr vt d
+load net {conc#651.itm(4)} -attr vt d
+load net {conc#651.itm(5)} -attr vt d
+load net {conc#651.itm(6)} -attr vt d
+load netBundle {conc#651.itm} 7 {conc#651.itm(0)} {conc#651.itm(1)} {conc#651.itm(2)} {conc#651.itm(3)} {conc#651.itm(4)} {conc#651.itm(5)} {conc#651.itm(6)} -attr xrf 25151 -attr oid 447 -attr vt d -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {ACC1:acc#208.itm(0)} -attr vt d
+load net {ACC1:acc#208.itm(1)} -attr vt d
+load net {ACC1:acc#208.itm(2)} -attr vt d
+load net {ACC1:acc#208.itm(3)} -attr vt d
+load net {ACC1:acc#208.itm(4)} -attr vt d
+load net {ACC1:acc#208.itm(5)} -attr vt d
+load net {ACC1:acc#208.itm(6)} -attr vt d
+load net {ACC1:acc#208.itm(7)} -attr vt d
+load netBundle {ACC1:acc#208.itm} 8 {ACC1:acc#208.itm(0)} {ACC1:acc#208.itm(1)} {ACC1:acc#208.itm(2)} {ACC1:acc#208.itm(3)} {ACC1:acc#208.itm(4)} {ACC1:acc#208.itm(5)} {ACC1:acc#208.itm(6)} {ACC1:acc#208.itm(7)} -attr xrf 25152 -attr oid 448 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1-3:exs#538.itm(0)} -attr vt d
+load net {ACC1-3:exs#538.itm(1)} -attr vt d
+load net {ACC1-3:exs#538.itm(2)} -attr vt d
+load net {ACC1-3:exs#538.itm(3)} -attr vt d
+load net {ACC1-3:exs#538.itm(4)} -attr vt d
+load net {ACC1-3:exs#538.itm(5)} -attr vt d
+load net {ACC1-3:exs#538.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#538.itm} 7 {ACC1-3:exs#538.itm(0)} {ACC1-3:exs#538.itm(1)} {ACC1-3:exs#538.itm(2)} {ACC1-3:exs#538.itm(3)} {ACC1-3:exs#538.itm(4)} {ACC1-3:exs#538.itm(5)} {ACC1-3:exs#538.itm(6)} -attr xrf 25153 -attr oid 449 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {ACC1-3:conc#226.itm(0)} -attr vt d
+load net {ACC1-3:conc#226.itm(1)} -attr vt d
+load net {ACC1-3:conc#226.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#226.itm} 3 {ACC1-3:conc#226.itm(0)} {ACC1-3:conc#226.itm(1)} {ACC1-3:conc#226.itm(2)} -attr xrf 25154 -attr oid 450 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#226.itm}
+load net {ACC1-3:exs#560.itm(0)} -attr vt d
+load net {ACC1-3:exs#560.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#560.itm} 2 {ACC1-3:exs#560.itm(0)} {ACC1-3:exs#560.itm(1)} -attr xrf 25155 -attr oid 451 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#560.itm}
+load net {ACC1:acc#205.itm(0)} -attr vt d
+load net {ACC1:acc#205.itm(1)} -attr vt d
+load net {ACC1:acc#205.itm(2)} -attr vt d
+load net {ACC1:acc#205.itm(3)} -attr vt d
+load net {ACC1:acc#205.itm(4)} -attr vt d
+load net {ACC1:acc#205.itm(5)} -attr vt d
+load netBundle {ACC1:acc#205.itm} 6 {ACC1:acc#205.itm(0)} {ACC1:acc#205.itm(1)} {ACC1:acc#205.itm(2)} {ACC1:acc#205.itm(3)} {ACC1:acc#205.itm(4)} {ACC1:acc#205.itm(5)} -attr xrf 25156 -attr oid 452 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {conc#652.itm(0)} -attr vt d
+load net {conc#652.itm(1)} -attr vt d
+load net {conc#652.itm(2)} -attr vt d
+load net {conc#652.itm(3)} -attr vt d
+load net {conc#652.itm(4)} -attr vt d
+load netBundle {conc#652.itm} 5 {conc#652.itm(0)} {conc#652.itm(1)} {conc#652.itm(2)} {conc#652.itm(3)} {conc#652.itm(4)} -attr xrf 25157 -attr oid 453 -attr vt d -attr @path {/sobel/sobel:core/conc#652.itm}
+load net {ACC1:acc#201.itm(0)} -attr vt d
+load net {ACC1:acc#201.itm(1)} -attr vt d
+load net {ACC1:acc#201.itm(2)} -attr vt d
+load net {ACC1:acc#201.itm(3)} -attr vt d
+load netBundle {ACC1:acc#201.itm} 4 {ACC1:acc#201.itm(0)} {ACC1:acc#201.itm(1)} {ACC1:acc#201.itm(2)} {ACC1:acc#201.itm(3)} -attr xrf 25158 -attr oid 454 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:slc#60.itm(0)} -attr vt d
+load net {ACC1:slc#60.itm(1)} -attr vt d
+load net {ACC1:slc#60.itm(2)} -attr vt d
+load netBundle {ACC1:slc#60.itm} 3 {ACC1:slc#60.itm(0)} {ACC1:slc#60.itm(1)} {ACC1:slc#60.itm(2)} -attr xrf 25159 -attr oid 455 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#60.itm}
+load net {ACC1:acc#195.itm(0)} -attr vt d
+load net {ACC1:acc#195.itm(1)} -attr vt d
+load net {ACC1:acc#195.itm(2)} -attr vt d
+load net {ACC1:acc#195.itm(3)} -attr vt d
+load netBundle {ACC1:acc#195.itm} 4 {ACC1:acc#195.itm(0)} {ACC1:acc#195.itm(1)} {ACC1:acc#195.itm(2)} {ACC1:acc#195.itm(3)} -attr xrf 25160 -attr oid 456 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load net {exs#60.itm(0)} -attr vt d
+load net {exs#60.itm(1)} -attr vt d
+load net {exs#60.itm(2)} -attr vt d
+load netBundle {exs#60.itm} 3 {exs#60.itm(0)} {exs#60.itm(1)} {exs#60.itm(2)} -attr xrf 25161 -attr oid 457 -attr vt d -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {conc#653.itm(0)} -attr vt d
+load net {conc#653.itm(1)} -attr vt d
+load netBundle {conc#653.itm} 2 {conc#653.itm(0)} {conc#653.itm(1)} -attr xrf 25162 -attr oid 458 -attr vt d -attr @path {/sobel/sobel:core/conc#653.itm}
+load net {ACC1:exs#751.itm(0)} -attr vt d
+load net {ACC1:exs#751.itm(1)} -attr vt d
+load net {ACC1:exs#751.itm(2)} -attr vt d
+load netBundle {ACC1:exs#751.itm} 3 {ACC1:exs#751.itm(0)} {ACC1:exs#751.itm(1)} {ACC1:exs#751.itm(2)} -attr xrf 25163 -attr oid 459 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#751.itm}
+load net {ACC1:conc#564.itm(0)} -attr vt d
+load net {ACC1:conc#564.itm(1)} -attr vt d
+load netBundle {ACC1:conc#564.itm} 2 {ACC1:conc#564.itm(0)} {ACC1:conc#564.itm(1)} -attr xrf 25164 -attr oid 460 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#564.itm}
+load net {conc#655.itm(0)} -attr vt d
+load net {conc#655.itm(1)} -attr vt d
+load net {conc#655.itm(2)} -attr vt d
+load net {conc#655.itm(3)} -attr vt d
+load net {conc#655.itm(4)} -attr vt d
+load net {conc#655.itm(5)} -attr vt d
+load net {conc#655.itm(6)} -attr vt d
+load net {conc#655.itm(7)} -attr vt d
+load net {conc#655.itm(8)} -attr vt d
+load net {conc#655.itm(9)} -attr vt d
+load netBundle {conc#655.itm} 10 {conc#655.itm(0)} {conc#655.itm(1)} {conc#655.itm(2)} {conc#655.itm(3)} {conc#655.itm(4)} {conc#655.itm(5)} {conc#655.itm(6)} {conc#655.itm(7)} {conc#655.itm(8)} {conc#655.itm(9)} -attr xrf 25165 -attr oid 461 -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {ACC1-3:exs#581.itm(0)} -attr vt d
+load net {ACC1-3:exs#581.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#581.itm} 2 {ACC1-3:exs#581.itm(0)} {ACC1-3:exs#581.itm(1)} -attr xrf 25166 -attr oid 462 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#581.itm}
+load net {ACC1:acc#214.itm(0)} -attr vt d
+load net {ACC1:acc#214.itm(1)} -attr vt d
+load net {ACC1:acc#214.itm(2)} -attr vt d
+load net {ACC1:acc#214.itm(3)} -attr vt d
+load net {ACC1:acc#214.itm(4)} -attr vt d
+load net {ACC1:acc#214.itm(5)} -attr vt d
+load net {ACC1:acc#214.itm(6)} -attr vt d
+load net {ACC1:acc#214.itm(7)} -attr vt d
+load net {ACC1:acc#214.itm(8)} -attr vt d
+load net {ACC1:acc#214.itm(9)} -attr vt d
+load net {ACC1:acc#214.itm(10)} -attr vt d
+load net {ACC1:acc#214.itm(11)} -attr vt d
+load netBundle {ACC1:acc#214.itm} 12 {ACC1:acc#214.itm(0)} {ACC1:acc#214.itm(1)} {ACC1:acc#214.itm(2)} {ACC1:acc#214.itm(3)} {ACC1:acc#214.itm(4)} {ACC1:acc#214.itm(5)} {ACC1:acc#214.itm(6)} {ACC1:acc#214.itm(7)} {ACC1:acc#214.itm(8)} {ACC1:acc#214.itm(9)} {ACC1:acc#214.itm(10)} {ACC1:acc#214.itm(11)} -attr xrf 25167 -attr oid 463 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1-1:acc#122.itm(0)} -attr vt d
+load net {ACC1-1:acc#122.itm(1)} -attr vt d
+load net {ACC1-1:acc#122.itm(2)} -attr vt d
+load net {ACC1-1:acc#122.itm(3)} -attr vt d
+load net {ACC1-1:acc#122.itm(4)} -attr vt d
+load net {ACC1-1:acc#122.itm(5)} -attr vt d
+load net {ACC1-1:acc#122.itm(6)} -attr vt d
+load net {ACC1-1:acc#122.itm(7)} -attr vt d
+load net {ACC1-1:acc#122.itm(8)} -attr vt d
+load net {ACC1-1:acc#122.itm(9)} -attr vt d
+load net {ACC1-1:acc#122.itm(10)} -attr vt d
+load netBundle {ACC1-1:acc#122.itm} 11 {ACC1-1:acc#122.itm(0)} {ACC1-1:acc#122.itm(1)} {ACC1-1:acc#122.itm(2)} {ACC1-1:acc#122.itm(3)} {ACC1-1:acc#122.itm(4)} {ACC1-1:acc#122.itm(5)} {ACC1-1:acc#122.itm(6)} {ACC1-1:acc#122.itm(7)} {ACC1-1:acc#122.itm(8)} {ACC1-1:acc#122.itm(9)} {ACC1-1:acc#122.itm(10)} -attr xrf 25168 -attr oid 464 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1:acc#241.itm(0)} -attr vt d
+load net {ACC1:acc#241.itm(1)} -attr vt d
+load net {ACC1:acc#241.itm(2)} -attr vt d
+load net {ACC1:acc#241.itm(3)} -attr vt d
+load net {ACC1:acc#241.itm(4)} -attr vt d
+load net {ACC1:acc#241.itm(5)} -attr vt d
+load net {ACC1:acc#241.itm(6)} -attr vt d
+load net {ACC1:acc#241.itm(7)} -attr vt d
+load net {ACC1:acc#241.itm(8)} -attr vt d
+load net {ACC1:acc#241.itm(9)} -attr vt d
+load net {ACC1:acc#241.itm(10)} -attr vt d
+load netBundle {ACC1:acc#241.itm} 11 {ACC1:acc#241.itm(0)} {ACC1:acc#241.itm(1)} {ACC1:acc#241.itm(2)} {ACC1:acc#241.itm(3)} {ACC1:acc#241.itm(4)} {ACC1:acc#241.itm(5)} {ACC1:acc#241.itm(6)} {ACC1:acc#241.itm(7)} {ACC1:acc#241.itm(8)} {ACC1:acc#241.itm(9)} {ACC1:acc#241.itm(10)} -attr xrf 25169 -attr oid 465 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#239.itm(0)} -attr vt d
+load net {ACC1:acc#239.itm(1)} -attr vt d
+load net {ACC1:acc#239.itm(2)} -attr vt d
+load net {ACC1:acc#239.itm(3)} -attr vt d
+load net {ACC1:acc#239.itm(4)} -attr vt d
+load net {ACC1:acc#239.itm(5)} -attr vt d
+load net {ACC1:acc#239.itm(6)} -attr vt d
+load net {ACC1:acc#239.itm(7)} -attr vt d
+load net {ACC1:acc#239.itm(8)} -attr vt d
+load net {ACC1:acc#239.itm(9)} -attr vt d
+load netBundle {ACC1:acc#239.itm} 10 {ACC1:acc#239.itm(0)} {ACC1:acc#239.itm(1)} {ACC1:acc#239.itm(2)} {ACC1:acc#239.itm(3)} {ACC1:acc#239.itm(4)} {ACC1:acc#239.itm(5)} {ACC1:acc#239.itm(6)} {ACC1:acc#239.itm(7)} {ACC1:acc#239.itm(8)} {ACC1:acc#239.itm(9)} -attr xrf 25170 -attr oid 466 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {conc#656.itm(0)} -attr vt d
+load net {conc#656.itm(1)} -attr vt d
+load net {conc#656.itm(2)} -attr vt d
+load net {conc#656.itm(3)} -attr vt d
+load net {conc#656.itm(4)} -attr vt d
+load net {conc#656.itm(5)} -attr vt d
+load net {conc#656.itm(6)} -attr vt d
+load net {conc#656.itm(7)} -attr vt d
+load net {conc#656.itm(8)} -attr vt d
+load netBundle {conc#656.itm} 9 {conc#656.itm(0)} {conc#656.itm(1)} {conc#656.itm(2)} {conc#656.itm(3)} {conc#656.itm(4)} {conc#656.itm(5)} {conc#656.itm(6)} {conc#656.itm(7)} {conc#656.itm(8)} -attr xrf 25171 -attr oid 467 -attr vt d -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {ACC1:acc#237.itm(0)} -attr vt d
+load net {ACC1:acc#237.itm(1)} -attr vt d
+load net {ACC1:acc#237.itm(2)} -attr vt d
+load net {ACC1:acc#237.itm(3)} -attr vt d
+load net {ACC1:acc#237.itm(4)} -attr vt d
+load net {ACC1:acc#237.itm(5)} -attr vt d
+load net {ACC1:acc#237.itm(6)} -attr vt d
+load net {ACC1:acc#237.itm(7)} -attr vt d
+load netBundle {ACC1:acc#237.itm} 8 {ACC1:acc#237.itm(0)} {ACC1:acc#237.itm(1)} {ACC1:acc#237.itm(2)} {ACC1:acc#237.itm(3)} {ACC1:acc#237.itm(4)} {ACC1:acc#237.itm(5)} {ACC1:acc#237.itm(6)} {ACC1:acc#237.itm(7)} -attr xrf 25172 -attr oid 468 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {conc#657.itm(0)} -attr vt d
+load net {conc#657.itm(1)} -attr vt d
+load net {conc#657.itm(2)} -attr vt d
+load net {conc#657.itm(3)} -attr vt d
+load net {conc#657.itm(4)} -attr vt d
+load net {conc#657.itm(5)} -attr vt d
+load net {conc#657.itm(6)} -attr vt d
+load net {conc#657.itm(7)} -attr vt d
+load netBundle {conc#657.itm} 8 {conc#657.itm(0)} {conc#657.itm(1)} {conc#657.itm(2)} {conc#657.itm(3)} {conc#657.itm(4)} {conc#657.itm(5)} {conc#657.itm(6)} {conc#657.itm(7)} -attr xrf 25173 -attr oid 469 -attr vt d -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {ACC1-1:exs#558.itm(0)} -attr vt d
+load net {ACC1-1:exs#558.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#558.itm} 2 {ACC1-1:exs#558.itm(0)} {ACC1-1:exs#558.itm(1)} -attr xrf 25174 -attr oid 470 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#558.itm}
+load net {ACC1:acc#234.itm(0)} -attr vt d
+load net {ACC1:acc#234.itm(1)} -attr vt d
+load net {ACC1:acc#234.itm(2)} -attr vt d
+load net {ACC1:acc#234.itm(3)} -attr vt d
+load net {ACC1:acc#234.itm(4)} -attr vt d
+load net {ACC1:acc#234.itm(5)} -attr vt d
+load net {ACC1:acc#234.itm(6)} -attr vt d
+load netBundle {ACC1:acc#234.itm} 7 {ACC1:acc#234.itm(0)} {ACC1:acc#234.itm(1)} {ACC1:acc#234.itm(2)} {ACC1:acc#234.itm(3)} {ACC1:acc#234.itm(4)} {ACC1:acc#234.itm(5)} {ACC1:acc#234.itm(6)} -attr xrf 25175 -attr oid 471 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {conc#658.itm(0)} -attr vt d
+load net {conc#658.itm(1)} -attr vt d
+load net {conc#658.itm(2)} -attr vt d
+load net {conc#658.itm(3)} -attr vt d
+load net {conc#658.itm(4)} -attr vt d
+load net {conc#658.itm(5)} -attr vt d
+load netBundle {conc#658.itm} 6 {conc#658.itm(0)} {conc#658.itm(1)} {conc#658.itm(2)} {conc#658.itm(3)} {conc#658.itm(4)} {conc#658.itm(5)} -attr xrf 25176 -attr oid 472 -attr vt d -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {ACC1-1:exs#561.itm(0)} -attr vt d
+load net {ACC1-1:exs#561.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#561.itm} 2 {ACC1-1:exs#561.itm(0)} {ACC1-1:exs#561.itm(1)} -attr xrf 25177 -attr oid 473 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#561.itm}
+load net {ACC1:acc#231.itm(0)} -attr vt d
+load net {ACC1:acc#231.itm(1)} -attr vt d
+load net {ACC1:acc#231.itm(2)} -attr vt d
+load net {ACC1:acc#231.itm(3)} -attr vt d
+load net {ACC1:acc#231.itm(4)} -attr vt d
+load netBundle {ACC1:acc#231.itm} 5 {ACC1:acc#231.itm(0)} {ACC1:acc#231.itm(1)} {ACC1:acc#231.itm(2)} {ACC1:acc#231.itm(3)} {ACC1:acc#231.itm(4)} -attr xrf 25178 -attr oid 474 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#227.itm(0)} -attr vt d
+load net {ACC1:acc#227.itm(1)} -attr vt d
+load net {ACC1:acc#227.itm(2)} -attr vt d
+load net {ACC1:acc#227.itm(3)} -attr vt d
+load netBundle {ACC1:acc#227.itm} 4 {ACC1:acc#227.itm(0)} {ACC1:acc#227.itm(1)} {ACC1:acc#227.itm(2)} {ACC1:acc#227.itm(3)} -attr xrf 25179 -attr oid 475 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:slc#66.itm(0)} -attr vt d
+load net {ACC1:slc#66.itm(1)} -attr vt d
+load net {ACC1:slc#66.itm(2)} -attr vt d
+load netBundle {ACC1:slc#66.itm} 3 {ACC1:slc#66.itm(0)} {ACC1:slc#66.itm(1)} {ACC1:slc#66.itm(2)} -attr xrf 25180 -attr oid 476 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1:acc#221.itm(0)} -attr vt d
+load net {ACC1:acc#221.itm(1)} -attr vt d
+load net {ACC1:acc#221.itm(2)} -attr vt d
+load net {ACC1:acc#221.itm(3)} -attr vt d
+load netBundle {ACC1:acc#221.itm} 4 {ACC1:acc#221.itm(0)} {ACC1:acc#221.itm(1)} {ACC1:acc#221.itm(2)} {ACC1:acc#221.itm(3)} -attr xrf 25181 -attr oid 477 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {exs#46.itm(0)} -attr vt d
+load net {exs#46.itm(1)} -attr vt d
+load net {exs#46.itm(2)} -attr vt d
+load netBundle {exs#46.itm} 3 {exs#46.itm(0)} {exs#46.itm(1)} {exs#46.itm(2)} -attr xrf 25182 -attr oid 478 -attr vt d -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {conc#659.itm(0)} -attr vt d
+load net {conc#659.itm(1)} -attr vt d
+load netBundle {conc#659.itm} 2 {conc#659.itm(0)} {conc#659.itm(1)} -attr xrf 25183 -attr oid 479 -attr vt d -attr @path {/sobel/sobel:core/conc#659.itm}
+load net {ACC1:exs#753.itm(0)} -attr vt d
+load net {ACC1:exs#753.itm(1)} -attr vt d
+load net {ACC1:exs#753.itm(2)} -attr vt d
+load netBundle {ACC1:exs#753.itm} 3 {ACC1:exs#753.itm(0)} {ACC1:exs#753.itm(1)} {ACC1:exs#753.itm(2)} -attr xrf 25184 -attr oid 480 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#753.itm}
+load net {ACC1:conc#577.itm(0)} -attr vt d
+load net {ACC1:conc#577.itm(1)} -attr vt d
+load netBundle {ACC1:conc#577.itm} 2 {ACC1:conc#577.itm(0)} {ACC1:conc#577.itm(1)} -attr xrf 25185 -attr oid 481 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#577.itm}
+load net {ACC1:slc#65.itm(0)} -attr vt d
+load net {ACC1:slc#65.itm(1)} -attr vt d
+load net {ACC1:slc#65.itm(2)} -attr vt d
+load netBundle {ACC1:slc#65.itm} 3 {ACC1:slc#65.itm(0)} {ACC1:slc#65.itm(1)} {ACC1:slc#65.itm(2)} -attr xrf 25186 -attr oid 482 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#220.itm(0)} -attr vt d
+load net {ACC1:acc#220.itm(1)} -attr vt d
+load net {ACC1:acc#220.itm(2)} -attr vt d
+load net {ACC1:acc#220.itm(3)} -attr vt d
+load netBundle {ACC1:acc#220.itm} 4 {ACC1:acc#220.itm(0)} {ACC1:acc#220.itm(1)} {ACC1:acc#220.itm(2)} {ACC1:acc#220.itm(3)} -attr xrf 25187 -attr oid 483 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {exs#47.itm(0)} -attr vt d
+load net {exs#47.itm(1)} -attr vt d
+load net {exs#47.itm(2)} -attr vt d
+load netBundle {exs#47.itm} 3 {exs#47.itm(0)} {exs#47.itm(1)} {exs#47.itm(2)} -attr xrf 25188 -attr oid 484 -attr vt d -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {conc#660.itm(0)} -attr vt d
+load net {conc#660.itm(1)} -attr vt d
+load netBundle {conc#660.itm} 2 {conc#660.itm(0)} {conc#660.itm(1)} -attr xrf 25189 -attr oid 485 -attr vt d -attr @path {/sobel/sobel:core/conc#660.itm}
+load net {ACC1:exs#755.itm(0)} -attr vt d
+load net {ACC1:exs#755.itm(1)} -attr vt d
+load net {ACC1:exs#755.itm(2)} -attr vt d
+load netBundle {ACC1:exs#755.itm} 3 {ACC1:exs#755.itm(0)} {ACC1:exs#755.itm(1)} {ACC1:exs#755.itm(2)} -attr xrf 25190 -attr oid 486 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#755.itm}
+load net {ACC1:conc#575.itm(0)} -attr vt d
+load net {ACC1:conc#575.itm(1)} -attr vt d
+load netBundle {ACC1:conc#575.itm} 2 {ACC1:conc#575.itm(0)} {ACC1:conc#575.itm(1)} -attr xrf 25191 -attr oid 487 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#575.itm}
+load net {ACC1:acc#226.itm(0)} -attr vt d
+load net {ACC1:acc#226.itm(1)} -attr vt d
+load net {ACC1:acc#226.itm(2)} -attr vt d
+load net {ACC1:acc#226.itm(3)} -attr vt d
+load netBundle {ACC1:acc#226.itm} 4 {ACC1:acc#226.itm(0)} {ACC1:acc#226.itm(1)} {ACC1:acc#226.itm(2)} {ACC1:acc#226.itm(3)} -attr xrf 25192 -attr oid 488 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:slc#64.itm(0)} -attr vt d
+load net {ACC1:slc#64.itm(1)} -attr vt d
+load net {ACC1:slc#64.itm(2)} -attr vt d
+load netBundle {ACC1:slc#64.itm} 3 {ACC1:slc#64.itm(0)} {ACC1:slc#64.itm(1)} {ACC1:slc#64.itm(2)} -attr xrf 25193 -attr oid 489 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#219.itm(0)} -attr vt d
+load net {ACC1:acc#219.itm(1)} -attr vt d
+load net {ACC1:acc#219.itm(2)} -attr vt d
+load net {ACC1:acc#219.itm(3)} -attr vt d
+load netBundle {ACC1:acc#219.itm} 4 {ACC1:acc#219.itm(0)} {ACC1:acc#219.itm(1)} {ACC1:acc#219.itm(2)} {ACC1:acc#219.itm(3)} -attr xrf 25194 -attr oid 490 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {exs#48.itm(0)} -attr vt d
+load net {exs#48.itm(1)} -attr vt d
+load net {exs#48.itm(2)} -attr vt d
+load netBundle {exs#48.itm} 3 {exs#48.itm(0)} {exs#48.itm(1)} {exs#48.itm(2)} -attr xrf 25195 -attr oid 491 -attr vt d -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {conc#661.itm(0)} -attr vt d
+load net {conc#661.itm(1)} -attr vt d
+load netBundle {conc#661.itm} 2 {conc#661.itm(0)} {conc#661.itm(1)} -attr xrf 25196 -attr oid 492 -attr vt d -attr @path {/sobel/sobel:core/conc#661.itm}
+load net {ACC1:exs#757.itm(0)} -attr vt d
+load net {ACC1:exs#757.itm(1)} -attr vt d
+load net {ACC1:exs#757.itm(2)} -attr vt d
+load netBundle {ACC1:exs#757.itm} 3 {ACC1:exs#757.itm(0)} {ACC1:exs#757.itm(1)} {ACC1:exs#757.itm(2)} -attr xrf 25197 -attr oid 493 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#757.itm}
+load net {ACC1:conc#573.itm(0)} -attr vt d
+load net {ACC1:conc#573.itm(1)} -attr vt d
+load netBundle {ACC1:conc#573.itm} 2 {ACC1:conc#573.itm(0)} {ACC1:conc#573.itm(1)} -attr xrf 25198 -attr oid 494 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#573.itm}
+load net {ACC1:slc#63.itm(0)} -attr vt d
+load net {ACC1:slc#63.itm(1)} -attr vt d
+load net {ACC1:slc#63.itm(2)} -attr vt d
+load netBundle {ACC1:slc#63.itm} 3 {ACC1:slc#63.itm(0)} {ACC1:slc#63.itm(1)} {ACC1:slc#63.itm(2)} -attr xrf 25199 -attr oid 495 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#63.itm}
+load net {ACC1:acc#218.itm(0)} -attr vt d
+load net {ACC1:acc#218.itm(1)} -attr vt d
+load net {ACC1:acc#218.itm(2)} -attr vt d
+load net {ACC1:acc#218.itm(3)} -attr vt d
+load netBundle {ACC1:acc#218.itm} 4 {ACC1:acc#218.itm(0)} {ACC1:acc#218.itm(1)} {ACC1:acc#218.itm(2)} {ACC1:acc#218.itm(3)} -attr xrf 25200 -attr oid 496 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {exs#49.itm(0)} -attr vt d
+load net {exs#49.itm(1)} -attr vt d
+load net {exs#49.itm(2)} -attr vt d
+load netBundle {exs#49.itm} 3 {exs#49.itm(0)} {exs#49.itm(1)} {exs#49.itm(2)} -attr xrf 25201 -attr oid 497 -attr vt d -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {conc#662.itm(0)} -attr vt d
+load net {conc#662.itm(1)} -attr vt d
+load netBundle {conc#662.itm} 2 {conc#662.itm(0)} {conc#662.itm(1)} -attr xrf 25202 -attr oid 498 -attr vt d -attr @path {/sobel/sobel:core/conc#662.itm}
+load net {ACC1:exs#759.itm(0)} -attr vt d
+load net {ACC1:exs#759.itm(1)} -attr vt d
+load net {ACC1:exs#759.itm(2)} -attr vt d
+load netBundle {ACC1:exs#759.itm} 3 {ACC1:exs#759.itm(0)} {ACC1:exs#759.itm(1)} {ACC1:exs#759.itm(2)} -attr xrf 25203 -attr oid 499 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#759.itm}
+load net {ACC1:conc#571.itm(0)} -attr vt d
+load net {ACC1:conc#571.itm(1)} -attr vt d
+load netBundle {ACC1:conc#571.itm} 2 {ACC1:conc#571.itm(0)} {ACC1:conc#571.itm(1)} -attr xrf 25204 -attr oid 500 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#571.itm}
+load net {ACC1:acc#238.itm(0)} -attr vt d
+load net {ACC1:acc#238.itm(1)} -attr vt d
+load net {ACC1:acc#238.itm(2)} -attr vt d
+load net {ACC1:acc#238.itm(3)} -attr vt d
+load net {ACC1:acc#238.itm(4)} -attr vt d
+load net {ACC1:acc#238.itm(5)} -attr vt d
+load net {ACC1:acc#238.itm(6)} -attr vt d
+load net {ACC1:acc#238.itm(7)} -attr vt d
+load net {ACC1:acc#238.itm(8)} -attr vt d
+load net {ACC1:acc#238.itm(9)} -attr vt d
+load netBundle {ACC1:acc#238.itm} 10 {ACC1:acc#238.itm(0)} {ACC1:acc#238.itm(1)} {ACC1:acc#238.itm(2)} {ACC1:acc#238.itm(3)} {ACC1:acc#238.itm(4)} {ACC1:acc#238.itm(5)} {ACC1:acc#238.itm(6)} {ACC1:acc#238.itm(7)} {ACC1:acc#238.itm(8)} {ACC1:acc#238.itm(9)} -attr xrf 25205 -attr oid 501 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#236.itm(0)} -attr vt d
+load net {ACC1:acc#236.itm(1)} -attr vt d
+load net {ACC1:acc#236.itm(2)} -attr vt d
+load net {ACC1:acc#236.itm(3)} -attr vt d
+load net {ACC1:acc#236.itm(4)} -attr vt d
+load net {ACC1:acc#236.itm(5)} -attr vt d
+load net {ACC1:acc#236.itm(6)} -attr vt d
+load net {ACC1:acc#236.itm(7)} -attr vt d
+load netBundle {ACC1:acc#236.itm} 8 {ACC1:acc#236.itm(0)} {ACC1:acc#236.itm(1)} {ACC1:acc#236.itm(2)} {ACC1:acc#236.itm(3)} {ACC1:acc#236.itm(4)} {ACC1:acc#236.itm(5)} {ACC1:acc#236.itm(6)} {ACC1:acc#236.itm(7)} -attr xrf 25206 -attr oid 502 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#233.itm(0)} -attr vt d
+load net {ACC1:acc#233.itm(1)} -attr vt d
+load net {ACC1:acc#233.itm(2)} -attr vt d
+load net {ACC1:acc#233.itm(3)} -attr vt d
+load net {ACC1:acc#233.itm(4)} -attr vt d
+load net {ACC1:acc#233.itm(5)} -attr vt d
+load netBundle {ACC1:acc#233.itm} 6 {ACC1:acc#233.itm(0)} {ACC1:acc#233.itm(1)} {ACC1:acc#233.itm(2)} {ACC1:acc#233.itm(3)} {ACC1:acc#233.itm(4)} {ACC1:acc#233.itm(5)} -attr xrf 25207 -attr oid 503 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#230.itm(0)} -attr vt d
+load net {ACC1:acc#230.itm(1)} -attr vt d
+load net {ACC1:acc#230.itm(2)} -attr vt d
+load net {ACC1:acc#230.itm(3)} -attr vt d
+load netBundle {ACC1:acc#230.itm} 4 {ACC1:acc#230.itm(0)} {ACC1:acc#230.itm(1)} {ACC1:acc#230.itm(2)} {ACC1:acc#230.itm(3)} -attr xrf 25208 -attr oid 504 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#225.itm(0)} -attr vt d
+load net {ACC1:acc#225.itm(1)} -attr vt d
+load net {ACC1:acc#225.itm(2)} -attr vt d
+load netBundle {ACC1:acc#225.itm} 3 {ACC1:acc#225.itm(0)} {ACC1:acc#225.itm(1)} {ACC1:acc#225.itm(2)} -attr xrf 25209 -attr oid 505 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:slc#61.itm(0)} -attr vt d
+load net {ACC1:slc#61.itm(1)} -attr vt d
+load net {ACC1:slc#61.itm(2)} -attr vt d
+load netBundle {ACC1:slc#61.itm} 3 {ACC1:slc#61.itm(0)} {ACC1:slc#61.itm(1)} {ACC1:slc#61.itm(2)} -attr xrf 25210 -attr oid 506 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#61.itm}
+load net {ACC1:acc#216.itm(0)} -attr vt d
+load net {ACC1:acc#216.itm(1)} -attr vt d
+load net {ACC1:acc#216.itm(2)} -attr vt d
+load net {ACC1:acc#216.itm(3)} -attr vt d
+load netBundle {ACC1:acc#216.itm} 4 {ACC1:acc#216.itm(0)} {ACC1:acc#216.itm(1)} {ACC1:acc#216.itm(2)} {ACC1:acc#216.itm(3)} -attr xrf 25211 -attr oid 507 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {conc#663.itm(0)} -attr vt d
+load net {conc#663.itm(1)} -attr vt d
+load net {conc#663.itm(2)} -attr vt d
+load netBundle {conc#663.itm} 3 {conc#663.itm(0)} {conc#663.itm(1)} {conc#663.itm(2)} -attr xrf 25212 -attr oid 508 -attr vt d -attr @path {/sobel/sobel:core/conc#663.itm}
+load net {ACC1:conc#567.itm(0)} -attr vt d
+load net {ACC1:conc#567.itm(1)} -attr vt d
+load netBundle {ACC1:conc#567.itm} 2 {ACC1:conc#567.itm(0)} {ACC1:conc#567.itm(1)} -attr xrf 25213 -attr oid 509 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#567.itm}
+load net {slc(ACC1:acc#116.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#116.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#116.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#116.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#116.psp#1.sva)#2.itm(1)} -attr xrf 25214 -attr oid 510 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp#1.sva)#2.itm}
+load net {ACC1:slc#62.itm(0)} -attr vt d
+load net {ACC1:slc#62.itm(1)} -attr vt d
+load net {ACC1:slc#62.itm(2)} -attr vt d
+load net {ACC1:slc#62.itm(3)} -attr vt d
+load netBundle {ACC1:slc#62.itm} 4 {ACC1:slc#62.itm(0)} {ACC1:slc#62.itm(1)} {ACC1:slc#62.itm(2)} {ACC1:slc#62.itm(3)} -attr xrf 25215 -attr oid 511 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#62.itm}
+load net {ACC1:acc#217.itm(0)} -attr vt d
+load net {ACC1:acc#217.itm(1)} -attr vt d
+load net {ACC1:acc#217.itm(2)} -attr vt d
+load net {ACC1:acc#217.itm(3)} -attr vt d
+load net {ACC1:acc#217.itm(4)} -attr vt d
+load netBundle {ACC1:acc#217.itm} 5 {ACC1:acc#217.itm(0)} {ACC1:acc#217.itm(1)} {ACC1:acc#217.itm(2)} {ACC1:acc#217.itm(3)} {ACC1:acc#217.itm(4)} -attr xrf 25216 -attr oid 512 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {conc#664.itm(0)} -attr vt d
+load net {conc#664.itm(1)} -attr vt d
+load net {conc#664.itm(2)} -attr vt d
+load netBundle {conc#664.itm} 3 {conc#664.itm(0)} {conc#664.itm(1)} {conc#664.itm(2)} -attr xrf 25217 -attr oid 513 -attr vt d -attr @path {/sobel/sobel:core/conc#664.itm}
+load net {ACC1:conc#569.itm(0)} -attr vt d
+load net {ACC1:conc#569.itm(1)} -attr vt d
+load net {ACC1:conc#569.itm(2)} -attr vt d
+load netBundle {ACC1:conc#569.itm} 3 {ACC1:conc#569.itm(0)} {ACC1:conc#569.itm(1)} {ACC1:conc#569.itm(2)} -attr xrf 25218 -attr oid 514 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#569.itm}
+load net {ACC1:acc#229.itm(0)} -attr vt d
+load net {ACC1:acc#229.itm(1)} -attr vt d
+load net {ACC1:acc#229.itm(2)} -attr vt d
+load net {ACC1:acc#229.itm(3)} -attr vt d
+load net {ACC1:acc#229.itm(4)} -attr vt d
+load netBundle {ACC1:acc#229.itm} 5 {ACC1:acc#229.itm(0)} {ACC1:acc#229.itm(1)} {ACC1:acc#229.itm(2)} {ACC1:acc#229.itm(3)} {ACC1:acc#229.itm(4)} -attr xrf 25219 -attr oid 515 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1-1:conc#260.itm(0)} -attr vt d
+load net {ACC1-1:conc#260.itm(1)} -attr vt d
+load net {ACC1-1:conc#260.itm(2)} -attr vt d
+load net {ACC1-1:conc#260.itm(3)} -attr vt d
+load netBundle {ACC1-1:conc#260.itm} 4 {ACC1-1:conc#260.itm(0)} {ACC1-1:conc#260.itm(1)} {ACC1-1:conc#260.itm(2)} {ACC1-1:conc#260.itm(3)} -attr xrf 25220 -attr oid 516 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#260.itm}
+load net {ACC1-1:exs#552.itm(0)} -attr vt d
+load net {ACC1-1:exs#552.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#552.itm} 2 {ACC1-1:exs#552.itm(0)} {ACC1-1:exs#552.itm(1)} -attr xrf 25221 -attr oid 517 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#552.itm}
+load net {conc#665.itm(0)} -attr vt d
+load net {conc#665.itm(1)} -attr vt d
+load net {conc#665.itm(2)} -attr vt d
+load net {conc#665.itm(3)} -attr vt d
+load net {conc#665.itm(4)} -attr vt d
+load net {conc#665.itm(5)} -attr vt d
+load net {conc#665.itm(6)} -attr vt d
+load netBundle {conc#665.itm} 7 {conc#665.itm(0)} {conc#665.itm(1)} {conc#665.itm(2)} {conc#665.itm(3)} {conc#665.itm(4)} {conc#665.itm(5)} {conc#665.itm(6)} -attr xrf 25222 -attr oid 518 -attr vt d -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {ACC1:acc#235.itm(0)} -attr vt d
+load net {ACC1:acc#235.itm(1)} -attr vt d
+load net {ACC1:acc#235.itm(2)} -attr vt d
+load net {ACC1:acc#235.itm(3)} -attr vt d
+load net {ACC1:acc#235.itm(4)} -attr vt d
+load net {ACC1:acc#235.itm(5)} -attr vt d
+load net {ACC1:acc#235.itm(6)} -attr vt d
+load net {ACC1:acc#235.itm(7)} -attr vt d
+load netBundle {ACC1:acc#235.itm} 8 {ACC1:acc#235.itm(0)} {ACC1:acc#235.itm(1)} {ACC1:acc#235.itm(2)} {ACC1:acc#235.itm(3)} {ACC1:acc#235.itm(4)} {ACC1:acc#235.itm(5)} {ACC1:acc#235.itm(6)} {ACC1:acc#235.itm(7)} -attr xrf 25223 -attr oid 519 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1-1:exs#538.itm(0)} -attr vt d
+load net {ACC1-1:exs#538.itm(1)} -attr vt d
+load net {ACC1-1:exs#538.itm(2)} -attr vt d
+load net {ACC1-1:exs#538.itm(3)} -attr vt d
+load net {ACC1-1:exs#538.itm(4)} -attr vt d
+load net {ACC1-1:exs#538.itm(5)} -attr vt d
+load net {ACC1-1:exs#538.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#538.itm} 7 {ACC1-1:exs#538.itm(0)} {ACC1-1:exs#538.itm(1)} {ACC1-1:exs#538.itm(2)} {ACC1-1:exs#538.itm(3)} {ACC1-1:exs#538.itm(4)} {ACC1-1:exs#538.itm(5)} {ACC1-1:exs#538.itm(6)} -attr xrf 25224 -attr oid 520 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {ACC1-1:conc#226.itm(0)} -attr vt d
+load net {ACC1-1:conc#226.itm(1)} -attr vt d
+load net {ACC1-1:conc#226.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#226.itm} 3 {ACC1-1:conc#226.itm(0)} {ACC1-1:conc#226.itm(1)} {ACC1-1:conc#226.itm(2)} -attr xrf 25225 -attr oid 521 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#226.itm}
+load net {ACC1-1:exs#547.itm(0)} -attr vt d
+load net {ACC1-1:exs#547.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#547.itm} 2 {ACC1-1:exs#547.itm(0)} {ACC1-1:exs#547.itm(1)} -attr xrf 25226 -attr oid 522 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#547.itm}
+load net {ACC1:acc#232.itm(0)} -attr vt d
+load net {ACC1:acc#232.itm(1)} -attr vt d
+load net {ACC1:acc#232.itm(2)} -attr vt d
+load net {ACC1:acc#232.itm(3)} -attr vt d
+load net {ACC1:acc#232.itm(4)} -attr vt d
+load net {ACC1:acc#232.itm(5)} -attr vt d
+load netBundle {ACC1:acc#232.itm} 6 {ACC1:acc#232.itm(0)} {ACC1:acc#232.itm(1)} {ACC1:acc#232.itm(2)} {ACC1:acc#232.itm(3)} {ACC1:acc#232.itm(4)} {ACC1:acc#232.itm(5)} -attr xrf 25227 -attr oid 523 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {conc#666.itm(0)} -attr vt d
+load net {conc#666.itm(1)} -attr vt d
+load net {conc#666.itm(2)} -attr vt d
+load net {conc#666.itm(3)} -attr vt d
+load net {conc#666.itm(4)} -attr vt d
+load netBundle {conc#666.itm} 5 {conc#666.itm(0)} {conc#666.itm(1)} {conc#666.itm(2)} {conc#666.itm(3)} {conc#666.itm(4)} -attr xrf 25228 -attr oid 524 -attr vt d -attr @path {/sobel/sobel:core/conc#666.itm}
+load net {ACC1:acc#228.itm(0)} -attr vt d
+load net {ACC1:acc#228.itm(1)} -attr vt d
+load net {ACC1:acc#228.itm(2)} -attr vt d
+load net {ACC1:acc#228.itm(3)} -attr vt d
+load netBundle {ACC1:acc#228.itm} 4 {ACC1:acc#228.itm(0)} {ACC1:acc#228.itm(1)} {ACC1:acc#228.itm(2)} {ACC1:acc#228.itm(3)} -attr xrf 25229 -attr oid 525 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:slc#67.itm(0)} -attr vt d
+load net {ACC1:slc#67.itm(1)} -attr vt d
+load net {ACC1:slc#67.itm(2)} -attr vt d
+load netBundle {ACC1:slc#67.itm} 3 {ACC1:slc#67.itm(0)} {ACC1:slc#67.itm(1)} {ACC1:slc#67.itm(2)} -attr xrf 25230 -attr oid 526 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#67.itm}
+load net {ACC1:acc#222.itm(0)} -attr vt d
+load net {ACC1:acc#222.itm(1)} -attr vt d
+load net {ACC1:acc#222.itm(2)} -attr vt d
+load net {ACC1:acc#222.itm(3)} -attr vt d
+load netBundle {ACC1:acc#222.itm} 4 {ACC1:acc#222.itm(0)} {ACC1:acc#222.itm(1)} {ACC1:acc#222.itm(2)} {ACC1:acc#222.itm(3)} -attr xrf 25231 -attr oid 527 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {exs#61.itm(0)} -attr vt d
+load net {exs#61.itm(1)} -attr vt d
+load net {exs#61.itm(2)} -attr vt d
+load netBundle {exs#61.itm} 3 {exs#61.itm(0)} {exs#61.itm(1)} {exs#61.itm(2)} -attr xrf 25232 -attr oid 528 -attr vt d -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {conc#667.itm(0)} -attr vt d
+load net {conc#667.itm(1)} -attr vt d
+load netBundle {conc#667.itm} 2 {conc#667.itm(0)} {conc#667.itm(1)} -attr xrf 25233 -attr oid 529 -attr vt d -attr @path {/sobel/sobel:core/conc#667.itm}
+load net {ACC1:exs#761.itm(0)} -attr vt d
+load net {ACC1:exs#761.itm(1)} -attr vt d
+load net {ACC1:exs#761.itm(2)} -attr vt d
+load netBundle {ACC1:exs#761.itm} 3 {ACC1:exs#761.itm(0)} {ACC1:exs#761.itm(1)} {ACC1:exs#761.itm(2)} -attr xrf 25234 -attr oid 530 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#761.itm}
+load net {ACC1:conc#579.itm(0)} -attr vt d
+load net {ACC1:conc#579.itm(1)} -attr vt d
+load netBundle {ACC1:conc#579.itm} 2 {ACC1:conc#579.itm(0)} {ACC1:conc#579.itm(1)} -attr xrf 25235 -attr oid 531 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#579.itm}
+load net {conc#669.itm(0)} -attr vt d
+load net {conc#669.itm(1)} -attr vt d
+load net {conc#669.itm(2)} -attr vt d
+load net {conc#669.itm(3)} -attr vt d
+load net {conc#669.itm(4)} -attr vt d
+load net {conc#669.itm(5)} -attr vt d
+load net {conc#669.itm(6)} -attr vt d
+load net {conc#669.itm(7)} -attr vt d
+load net {conc#669.itm(8)} -attr vt d
+load net {conc#669.itm(9)} -attr vt d
+load net {conc#669.itm(10)} -attr vt d
+load netBundle {conc#669.itm} 11 {conc#669.itm(0)} {conc#669.itm(1)} {conc#669.itm(2)} {conc#669.itm(3)} {conc#669.itm(4)} {conc#669.itm(5)} {conc#669.itm(6)} {conc#669.itm(7)} {conc#669.itm(8)} {conc#669.itm(9)} {conc#669.itm(10)} -attr xrf 25236 -attr oid 532 -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {ACC1:acc#344.itm(0)} -attr vt d
+load net {ACC1:acc#344.itm(1)} -attr vt d
+load net {ACC1:acc#344.itm(2)} -attr vt d
+load netBundle {ACC1:acc#344.itm} 3 {ACC1:acc#344.itm(0)} {ACC1:acc#344.itm(1)} {ACC1:acc#344.itm(2)} -attr xrf 25237 -attr oid 533 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:exs#857.itm(0)} -attr vt d
+load net {ACC1:exs#857.itm(1)} -attr vt d
+load netBundle {ACC1:exs#857.itm} 2 {ACC1:exs#857.itm(0)} {ACC1:exs#857.itm(1)} -attr xrf 25238 -attr oid 534 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#857.itm}
+load net {ACC1:acc#212.itm(0)} -attr vt d
+load net {ACC1:acc#212.itm(1)} -attr vt d
+load net {ACC1:acc#212.itm(2)} -attr vt d
+load net {ACC1:acc#212.itm(3)} -attr vt d
+load net {ACC1:acc#212.itm(4)} -attr vt d
+load net {ACC1:acc#212.itm(5)} -attr vt d
+load net {ACC1:acc#212.itm(6)} -attr vt d
+load net {ACC1:acc#212.itm(7)} -attr vt d
+load net {ACC1:acc#212.itm(8)} -attr vt d
+load net {ACC1:acc#212.itm(9)} -attr vt d
+load netBundle {ACC1:acc#212.itm} 10 {ACC1:acc#212.itm(0)} {ACC1:acc#212.itm(1)} {ACC1:acc#212.itm(2)} {ACC1:acc#212.itm(3)} {ACC1:acc#212.itm(4)} {ACC1:acc#212.itm(5)} {ACC1:acc#212.itm(6)} {ACC1:acc#212.itm(7)} {ACC1:acc#212.itm(8)} {ACC1:acc#212.itm(9)} -attr xrf 25239 -attr oid 535 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {conc#670.itm(0)} -attr vt d
+load net {conc#670.itm(1)} -attr vt d
+load net {conc#670.itm(2)} -attr vt d
+load net {conc#670.itm(3)} -attr vt d
+load net {conc#670.itm(4)} -attr vt d
+load net {conc#670.itm(5)} -attr vt d
+load net {conc#670.itm(6)} -attr vt d
+load net {conc#670.itm(7)} -attr vt d
+load net {conc#670.itm(8)} -attr vt d
+load netBundle {conc#670.itm} 9 {conc#670.itm(0)} {conc#670.itm(1)} {conc#670.itm(2)} {conc#670.itm(3)} {conc#670.itm(4)} {conc#670.itm(5)} {conc#670.itm(6)} {conc#670.itm(7)} {conc#670.itm(8)} -attr xrf 25240 -attr oid 536 -attr vt d -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {ACC1:acc#210.itm(0)} -attr vt d
+load net {ACC1:acc#210.itm(1)} -attr vt d
+load net {ACC1:acc#210.itm(2)} -attr vt d
+load net {ACC1:acc#210.itm(3)} -attr vt d
+load net {ACC1:acc#210.itm(4)} -attr vt d
+load net {ACC1:acc#210.itm(5)} -attr vt d
+load net {ACC1:acc#210.itm(6)} -attr vt d
+load net {ACC1:acc#210.itm(7)} -attr vt d
+load netBundle {ACC1:acc#210.itm} 8 {ACC1:acc#210.itm(0)} {ACC1:acc#210.itm(1)} {ACC1:acc#210.itm(2)} {ACC1:acc#210.itm(3)} {ACC1:acc#210.itm(4)} {ACC1:acc#210.itm(5)} {ACC1:acc#210.itm(6)} {ACC1:acc#210.itm(7)} -attr xrf 25241 -attr oid 537 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {conc#671.itm(0)} -attr vt d
+load net {conc#671.itm(1)} -attr vt d
+load net {conc#671.itm(2)} -attr vt d
+load net {conc#671.itm(3)} -attr vt d
+load net {conc#671.itm(4)} -attr vt d
+load net {conc#671.itm(5)} -attr vt d
+load net {conc#671.itm(6)} -attr vt d
+load net {conc#671.itm(7)} -attr vt d
+load netBundle {conc#671.itm} 8 {conc#671.itm(0)} {conc#671.itm(1)} {conc#671.itm(2)} {conc#671.itm(3)} {conc#671.itm(4)} {conc#671.itm(5)} {conc#671.itm(6)} {conc#671.itm(7)} -attr xrf 25242 -attr oid 538 -attr vt d -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {ACC1-3:exs#585.itm(0)} -attr vt d
+load net {ACC1-3:exs#585.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#585.itm} 2 {ACC1-3:exs#585.itm(0)} {ACC1-3:exs#585.itm(1)} -attr xrf 25243 -attr oid 539 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#585.itm}
+load net {ACC1:acc#207.itm(0)} -attr vt d
+load net {ACC1:acc#207.itm(1)} -attr vt d
+load net {ACC1:acc#207.itm(2)} -attr vt d
+load net {ACC1:acc#207.itm(3)} -attr vt d
+load net {ACC1:acc#207.itm(4)} -attr vt d
+load net {ACC1:acc#207.itm(5)} -attr vt d
+load net {ACC1:acc#207.itm(6)} -attr vt d
+load netBundle {ACC1:acc#207.itm} 7 {ACC1:acc#207.itm(0)} {ACC1:acc#207.itm(1)} {ACC1:acc#207.itm(2)} {ACC1:acc#207.itm(3)} {ACC1:acc#207.itm(4)} {ACC1:acc#207.itm(5)} {ACC1:acc#207.itm(6)} -attr xrf 25244 -attr oid 540 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {conc#672.itm(0)} -attr vt d
+load net {conc#672.itm(1)} -attr vt d
+load net {conc#672.itm(2)} -attr vt d
+load net {conc#672.itm(3)} -attr vt d
+load net {conc#672.itm(4)} -attr vt d
+load net {conc#672.itm(5)} -attr vt d
+load netBundle {conc#672.itm} 6 {conc#672.itm(0)} {conc#672.itm(1)} {conc#672.itm(2)} {conc#672.itm(3)} {conc#672.itm(4)} {conc#672.itm(5)} -attr xrf 25245 -attr oid 541 -attr vt d -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {ACC1-3:exs#588.itm(0)} -attr vt d
+load net {ACC1-3:exs#588.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#588.itm} 2 {ACC1-3:exs#588.itm(0)} {ACC1-3:exs#588.itm(1)} -attr xrf 25246 -attr oid 542 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#588.itm}
+load net {ACC1:acc#204.itm(0)} -attr vt d
+load net {ACC1:acc#204.itm(1)} -attr vt d
+load net {ACC1:acc#204.itm(2)} -attr vt d
+load net {ACC1:acc#204.itm(3)} -attr vt d
+load net {ACC1:acc#204.itm(4)} -attr vt d
+load netBundle {ACC1:acc#204.itm} 5 {ACC1:acc#204.itm(0)} {ACC1:acc#204.itm(1)} {ACC1:acc#204.itm(2)} {ACC1:acc#204.itm(3)} {ACC1:acc#204.itm(4)} -attr xrf 25247 -attr oid 543 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#200.itm(0)} -attr vt d
+load net {ACC1:acc#200.itm(1)} -attr vt d
+load net {ACC1:acc#200.itm(2)} -attr vt d
+load net {ACC1:acc#200.itm(3)} -attr vt d
+load netBundle {ACC1:acc#200.itm} 4 {ACC1:acc#200.itm(0)} {ACC1:acc#200.itm(1)} {ACC1:acc#200.itm(2)} {ACC1:acc#200.itm(3)} -attr xrf 25248 -attr oid 544 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:slc#59.itm(0)} -attr vt d
+load net {ACC1:slc#59.itm(1)} -attr vt d
+load net {ACC1:slc#59.itm(2)} -attr vt d
+load netBundle {ACC1:slc#59.itm} 3 {ACC1:slc#59.itm(0)} {ACC1:slc#59.itm(1)} {ACC1:slc#59.itm(2)} -attr xrf 25249 -attr oid 545 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#59.itm}
+load net {ACC1:acc#194.itm(0)} -attr vt d
+load net {ACC1:acc#194.itm(1)} -attr vt d
+load net {ACC1:acc#194.itm(2)} -attr vt d
+load net {ACC1:acc#194.itm(3)} -attr vt d
+load netBundle {ACC1:acc#194.itm} 4 {ACC1:acc#194.itm(0)} {ACC1:acc#194.itm(1)} {ACC1:acc#194.itm(2)} {ACC1:acc#194.itm(3)} -attr xrf 25250 -attr oid 546 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load net {exs#50.itm(0)} -attr vt d
+load net {exs#50.itm(1)} -attr vt d
+load net {exs#50.itm(2)} -attr vt d
+load netBundle {exs#50.itm} 3 {exs#50.itm(0)} {exs#50.itm(1)} {exs#50.itm(2)} -attr xrf 25251 -attr oid 547 -attr vt d -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {conc#673.itm(0)} -attr vt d
+load net {conc#673.itm(1)} -attr vt d
+load netBundle {conc#673.itm} 2 {conc#673.itm(0)} {conc#673.itm(1)} -attr xrf 25252 -attr oid 548 -attr vt d -attr @path {/sobel/sobel:core/conc#673.itm}
+load net {ACC1:exs#764.itm(0)} -attr vt d
+load net {ACC1:exs#764.itm(1)} -attr vt d
+load net {ACC1:exs#764.itm(2)} -attr vt d
+load netBundle {ACC1:exs#764.itm} 3 {ACC1:exs#764.itm(0)} {ACC1:exs#764.itm(1)} {ACC1:exs#764.itm(2)} -attr xrf 25253 -attr oid 549 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#764.itm}
+load net {ACC1:conc#562.itm(0)} -attr vt d
+load net {ACC1:conc#562.itm(1)} -attr vt d
+load netBundle {ACC1:conc#562.itm} 2 {ACC1:conc#562.itm(0)} {ACC1:conc#562.itm(1)} -attr xrf 25254 -attr oid 550 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#562.itm}
+load net {ACC1:slc#58.itm(0)} -attr vt d
+load net {ACC1:slc#58.itm(1)} -attr vt d
+load net {ACC1:slc#58.itm(2)} -attr vt d
+load netBundle {ACC1:slc#58.itm} 3 {ACC1:slc#58.itm(0)} {ACC1:slc#58.itm(1)} {ACC1:slc#58.itm(2)} -attr xrf 25255 -attr oid 551 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:acc#193.itm(0)} -attr vt d
+load net {ACC1:acc#193.itm(1)} -attr vt d
+load net {ACC1:acc#193.itm(2)} -attr vt d
+load net {ACC1:acc#193.itm(3)} -attr vt d
+load netBundle {ACC1:acc#193.itm} 4 {ACC1:acc#193.itm(0)} {ACC1:acc#193.itm(1)} {ACC1:acc#193.itm(2)} {ACC1:acc#193.itm(3)} -attr xrf 25256 -attr oid 552 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load net {exs#51.itm(0)} -attr vt d
+load net {exs#51.itm(1)} -attr vt d
+load net {exs#51.itm(2)} -attr vt d
+load netBundle {exs#51.itm} 3 {exs#51.itm(0)} {exs#51.itm(1)} {exs#51.itm(2)} -attr xrf 25257 -attr oid 553 -attr vt d -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {conc#674.itm(0)} -attr vt d
+load net {conc#674.itm(1)} -attr vt d
+load netBundle {conc#674.itm} 2 {conc#674.itm(0)} {conc#674.itm(1)} -attr xrf 25258 -attr oid 554 -attr vt d -attr @path {/sobel/sobel:core/conc#674.itm}
+load net {ACC1:exs#766.itm(0)} -attr vt d
+load net {ACC1:exs#766.itm(1)} -attr vt d
+load net {ACC1:exs#766.itm(2)} -attr vt d
+load netBundle {ACC1:exs#766.itm} 3 {ACC1:exs#766.itm(0)} {ACC1:exs#766.itm(1)} {ACC1:exs#766.itm(2)} -attr xrf 25259 -attr oid 555 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#766.itm}
+load net {ACC1:conc#560.itm(0)} -attr vt d
+load net {ACC1:conc#560.itm(1)} -attr vt d
+load netBundle {ACC1:conc#560.itm} 2 {ACC1:conc#560.itm(0)} {ACC1:conc#560.itm(1)} -attr xrf 25260 -attr oid 556 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#560.itm}
+load net {ACC1:acc#199.itm(0)} -attr vt d
+load net {ACC1:acc#199.itm(1)} -attr vt d
+load net {ACC1:acc#199.itm(2)} -attr vt d
+load net {ACC1:acc#199.itm(3)} -attr vt d
+load netBundle {ACC1:acc#199.itm} 4 {ACC1:acc#199.itm(0)} {ACC1:acc#199.itm(1)} {ACC1:acc#199.itm(2)} {ACC1:acc#199.itm(3)} -attr xrf 25261 -attr oid 557 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:slc#57.itm(0)} -attr vt d
+load net {ACC1:slc#57.itm(1)} -attr vt d
+load net {ACC1:slc#57.itm(2)} -attr vt d
+load netBundle {ACC1:slc#57.itm} 3 {ACC1:slc#57.itm(0)} {ACC1:slc#57.itm(1)} {ACC1:slc#57.itm(2)} -attr xrf 25262 -attr oid 558 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#57.itm}
+load net {ACC1:acc#192.itm(0)} -attr vt d
+load net {ACC1:acc#192.itm(1)} -attr vt d
+load net {ACC1:acc#192.itm(2)} -attr vt d
+load net {ACC1:acc#192.itm(3)} -attr vt d
+load netBundle {ACC1:acc#192.itm} 4 {ACC1:acc#192.itm(0)} {ACC1:acc#192.itm(1)} {ACC1:acc#192.itm(2)} {ACC1:acc#192.itm(3)} -attr xrf 25263 -attr oid 559 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {exs#52.itm(0)} -attr vt d
+load net {exs#52.itm(1)} -attr vt d
+load net {exs#52.itm(2)} -attr vt d
+load netBundle {exs#52.itm} 3 {exs#52.itm(0)} {exs#52.itm(1)} {exs#52.itm(2)} -attr xrf 25264 -attr oid 560 -attr vt d -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {conc#675.itm(0)} -attr vt d
+load net {conc#675.itm(1)} -attr vt d
+load netBundle {conc#675.itm} 2 {conc#675.itm(0)} {conc#675.itm(1)} -attr xrf 25265 -attr oid 561 -attr vt d -attr @path {/sobel/sobel:core/conc#675.itm}
+load net {ACC1:exs#768.itm(0)} -attr vt d
+load net {ACC1:exs#768.itm(1)} -attr vt d
+load net {ACC1:exs#768.itm(2)} -attr vt d
+load netBundle {ACC1:exs#768.itm} 3 {ACC1:exs#768.itm(0)} {ACC1:exs#768.itm(1)} {ACC1:exs#768.itm(2)} -attr xrf 25266 -attr oid 562 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#768.itm}
+load net {ACC1:conc#558.itm(0)} -attr vt d
+load net {ACC1:conc#558.itm(1)} -attr vt d
+load netBundle {ACC1:conc#558.itm} 2 {ACC1:conc#558.itm(0)} {ACC1:conc#558.itm(1)} -attr xrf 25267 -attr oid 563 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#558.itm}
+load net {ACC1:slc#56.itm(0)} -attr vt d
+load net {ACC1:slc#56.itm(1)} -attr vt d
+load net {ACC1:slc#56.itm(2)} -attr vt d
+load netBundle {ACC1:slc#56.itm} 3 {ACC1:slc#56.itm(0)} {ACC1:slc#56.itm(1)} {ACC1:slc#56.itm(2)} -attr xrf 25268 -attr oid 564 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#56.itm}
+load net {ACC1:acc#191.itm(0)} -attr vt d
+load net {ACC1:acc#191.itm(1)} -attr vt d
+load net {ACC1:acc#191.itm(2)} -attr vt d
+load net {ACC1:acc#191.itm(3)} -attr vt d
+load netBundle {ACC1:acc#191.itm} 4 {ACC1:acc#191.itm(0)} {ACC1:acc#191.itm(1)} {ACC1:acc#191.itm(2)} {ACC1:acc#191.itm(3)} -attr xrf 25269 -attr oid 565 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load net {exs#53.itm(0)} -attr vt d
+load net {exs#53.itm(1)} -attr vt d
+load net {exs#53.itm(2)} -attr vt d
+load netBundle {exs#53.itm} 3 {exs#53.itm(0)} {exs#53.itm(1)} {exs#53.itm(2)} -attr xrf 25270 -attr oid 566 -attr vt d -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {conc#676.itm(0)} -attr vt d
+load net {conc#676.itm(1)} -attr vt d
+load netBundle {conc#676.itm} 2 {conc#676.itm(0)} {conc#676.itm(1)} -attr xrf 25271 -attr oid 567 -attr vt d -attr @path {/sobel/sobel:core/conc#676.itm}
+load net {ACC1:exs#770.itm(0)} -attr vt d
+load net {ACC1:exs#770.itm(1)} -attr vt d
+load net {ACC1:exs#770.itm(2)} -attr vt d
+load netBundle {ACC1:exs#770.itm} 3 {ACC1:exs#770.itm(0)} {ACC1:exs#770.itm(1)} {ACC1:exs#770.itm(2)} -attr xrf 25272 -attr oid 568 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#770.itm}
+load net {ACC1:conc#556.itm(0)} -attr vt d
+load net {ACC1:conc#556.itm(1)} -attr vt d
+load netBundle {ACC1:conc#556.itm} 2 {ACC1:conc#556.itm(0)} {ACC1:conc#556.itm(1)} -attr xrf 25273 -attr oid 569 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#556.itm}
+load net {mux#18.itm(0)} -attr vt d
+load net {mux#18.itm(1)} -attr vt d
+load net {mux#18.itm(2)} -attr vt d
+load net {mux#18.itm(3)} -attr vt d
+load net {mux#18.itm(4)} -attr vt d
+load net {mux#18.itm(5)} -attr vt d
+load net {mux#18.itm(6)} -attr vt d
+load net {mux#18.itm(7)} -attr vt d
+load net {mux#18.itm(8)} -attr vt d
+load net {mux#18.itm(9)} -attr vt d
+load net {mux#18.itm(10)} -attr vt d
+load net {mux#18.itm(11)} -attr vt d
+load net {mux#18.itm(12)} -attr vt d
+load net {mux#18.itm(13)} -attr vt d
+load net {mux#18.itm(14)} -attr vt d
+load net {mux#18.itm(15)} -attr vt d
+load net {mux#18.itm(16)} -attr vt d
+load net {mux#18.itm(17)} -attr vt d
+load net {mux#18.itm(18)} -attr vt d
+load netBundle {mux#18.itm} 19 {mux#18.itm(0)} {mux#18.itm(1)} {mux#18.itm(2)} {mux#18.itm(3)} {mux#18.itm(4)} {mux#18.itm(5)} {mux#18.itm(6)} {mux#18.itm(7)} {mux#18.itm(8)} {mux#18.itm(9)} {mux#18.itm(10)} {mux#18.itm(11)} {mux#18.itm(12)} {mux#18.itm(13)} {mux#18.itm(14)} {mux#18.itm(15)} {mux#18.itm(16)} {mux#18.itm(17)} {mux#18.itm(18)} -attr xrf 25274 -attr oid 570 -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {FRAME:acc#15.itm(0)} -attr vt d
+load net {FRAME:acc#15.itm(1)} -attr vt d
+load net {FRAME:acc#15.itm(2)} -attr vt d
+load net {FRAME:acc#15.itm(3)} -attr vt d
+load net {FRAME:acc#15.itm(4)} -attr vt d
+load net {FRAME:acc#15.itm(5)} -attr vt d
+load net {FRAME:acc#15.itm(6)} -attr vt d
+load net {FRAME:acc#15.itm(7)} -attr vt d
+load net {FRAME:acc#15.itm(8)} -attr vt d
+load net {FRAME:acc#15.itm(9)} -attr vt d
+load net {FRAME:acc#15.itm(10)} -attr vt d
+load net {FRAME:acc#15.itm(11)} -attr vt d
+load netBundle {FRAME:acc#15.itm} 12 {FRAME:acc#15.itm(0)} {FRAME:acc#15.itm(1)} {FRAME:acc#15.itm(2)} {FRAME:acc#15.itm(3)} {FRAME:acc#15.itm(4)} {FRAME:acc#15.itm(5)} {FRAME:acc#15.itm(6)} {FRAME:acc#15.itm(7)} {FRAME:acc#15.itm(8)} {FRAME:acc#15.itm(9)} {FRAME:acc#15.itm(10)} {FRAME:acc#15.itm(11)} -attr xrf 25275 -attr oid 571 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:mul.itm(0)} -attr vt d
+load net {FRAME:mul.itm(1)} -attr vt d
+load net {FRAME:mul.itm(2)} -attr vt d
+load net {FRAME:mul.itm(3)} -attr vt d
+load net {FRAME:mul.itm(4)} -attr vt d
+load net {FRAME:mul.itm(5)} -attr vt d
+load net {FRAME:mul.itm(6)} -attr vt d
+load net {FRAME:mul.itm(7)} -attr vt d
+load net {FRAME:mul.itm(8)} -attr vt d
+load net {FRAME:mul.itm(9)} -attr vt d
+load net {FRAME:mul.itm(10)} -attr vt d
+load netBundle {FRAME:mul.itm} 11 {FRAME:mul.itm(0)} {FRAME:mul.itm(1)} {FRAME:mul.itm(2)} {FRAME:mul.itm(3)} {FRAME:mul.itm(4)} {FRAME:mul.itm(5)} {FRAME:mul.itm(6)} {FRAME:mul.itm(7)} {FRAME:mul.itm(8)} {FRAME:mul.itm(9)} {FRAME:mul.itm(10)} -attr xrf 25276 -attr oid 572 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {slc(intensity#2.sg1.sva)#12.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#12.itm(1)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#12.itm} 2 {slc(intensity#2.sg1.sva)#12.itm(0)} {slc(intensity#2.sg1.sva)#12.itm(1)} -attr xrf 25277 -attr oid 573 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#12.itm}
+load net {FRAME:acc#14.itm(0)} -attr vt d
+load net {FRAME:acc#14.itm(1)} -attr vt d
+load net {FRAME:acc#14.itm(2)} -attr vt d
+load net {FRAME:acc#14.itm(3)} -attr vt d
+load net {FRAME:acc#14.itm(4)} -attr vt d
+load net {FRAME:acc#14.itm(5)} -attr vt d
+load net {FRAME:acc#14.itm(6)} -attr vt d
+load net {FRAME:acc#14.itm(7)} -attr vt d
+load net {FRAME:acc#14.itm(8)} -attr vt d
+load net {FRAME:acc#14.itm(9)} -attr vt d
+load netBundle {FRAME:acc#14.itm} 10 {FRAME:acc#14.itm(0)} {FRAME:acc#14.itm(1)} {FRAME:acc#14.itm(2)} {FRAME:acc#14.itm(3)} {FRAME:acc#14.itm(4)} {FRAME:acc#14.itm(5)} {FRAME:acc#14.itm(6)} {FRAME:acc#14.itm(7)} {FRAME:acc#14.itm(8)} {FRAME:acc#14.itm(9)} -attr xrf 25278 -attr oid 574 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:mul#1.itm(0)} -attr vt d
+load net {FRAME:mul#1.itm(1)} -attr vt d
+load net {FRAME:mul#1.itm(2)} -attr vt d
+load net {FRAME:mul#1.itm(3)} -attr vt d
+load net {FRAME:mul#1.itm(4)} -attr vt d
+load net {FRAME:mul#1.itm(5)} -attr vt d
+load net {FRAME:mul#1.itm(6)} -attr vt d
+load net {FRAME:mul#1.itm(7)} -attr vt d
+load net {FRAME:mul#1.itm(8)} -attr vt d
+load netBundle {FRAME:mul#1.itm} 9 {FRAME:mul#1.itm(0)} {FRAME:mul#1.itm(1)} {FRAME:mul#1.itm(2)} {FRAME:mul#1.itm(3)} {FRAME:mul#1.itm(4)} {FRAME:mul#1.itm(5)} {FRAME:mul#1.itm(6)} {FRAME:mul#1.itm(7)} {FRAME:mul#1.itm(8)} -attr xrf 25279 -attr oid 575 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {slc(intensity#2.sg1.sva)#13.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#13.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#13.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#13.itm} 3 {slc(intensity#2.sg1.sva)#13.itm(0)} {slc(intensity#2.sg1.sva)#13.itm(1)} {slc(intensity#2.sg1.sva)#13.itm(2)} -attr xrf 25280 -attr oid 576 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#13.itm}
+load net {FRAME:acc#13.itm(0)} -attr vt d
+load net {FRAME:acc#13.itm(1)} -attr vt d
+load net {FRAME:acc#13.itm(2)} -attr vt d
+load net {FRAME:acc#13.itm(3)} -attr vt d
+load net {FRAME:acc#13.itm(4)} -attr vt d
+load net {FRAME:acc#13.itm(5)} -attr vt d
+load net {FRAME:acc#13.itm(6)} -attr vt d
+load net {FRAME:acc#13.itm(7)} -attr vt d
+load netBundle {FRAME:acc#13.itm} 8 {FRAME:acc#13.itm(0)} {FRAME:acc#13.itm(1)} {FRAME:acc#13.itm(2)} {FRAME:acc#13.itm(3)} {FRAME:acc#13.itm(4)} {FRAME:acc#13.itm(5)} {FRAME:acc#13.itm(6)} {FRAME:acc#13.itm(7)} -attr xrf 25281 -attr oid 577 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {slc(intensity#2.sg1.sva)#2.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#2.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#2.itm(2)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#2.itm(3)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#2.itm(4)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#2.itm} 6 {slc(intensity#2.sg1.sva)#2.itm(0)} {slc(intensity#2.sg1.sva)#2.itm(1)} {slc(intensity#2.sg1.sva)#2.itm(2)} {slc(intensity#2.sg1.sva)#2.itm(3)} {slc(intensity#2.sg1.sva)#2.itm(4)} {slc(intensity#2.sg1.sva)#2.itm(5)} -attr xrf 25282 -attr oid 578 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {FRAME:acc#12.itm(0)} -attr vt d
+load net {FRAME:acc#12.itm(1)} -attr vt d
+load net {FRAME:acc#12.itm(2)} -attr vt d
+load net {FRAME:acc#12.itm(3)} -attr vt d
+load net {FRAME:acc#12.itm(4)} -attr vt d
+load netBundle {FRAME:acc#12.itm} 5 {FRAME:acc#12.itm(0)} {FRAME:acc#12.itm(1)} {FRAME:acc#12.itm(2)} {FRAME:acc#12.itm(3)} {FRAME:acc#12.itm(4)} -attr xrf 25283 -attr oid 579 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#11.itm(0)} -attr vt d
+load net {FRAME:acc#11.itm(1)} -attr vt d
+load net {FRAME:acc#11.itm(2)} -attr vt d
+load net {FRAME:acc#11.itm(3)} -attr vt d
+load net {FRAME:acc#11.itm(4)} -attr vt d
+load netBundle {FRAME:acc#11.itm} 5 {FRAME:acc#11.itm(0)} {FRAME:acc#11.itm(1)} {FRAME:acc#11.itm(2)} {FRAME:acc#11.itm(3)} {FRAME:acc#11.itm(4)} -attr xrf 25284 -attr oid 580 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#10.itm(0)} -attr vt d
+load net {FRAME:acc#10.itm(1)} -attr vt d
+load net {FRAME:acc#10.itm(2)} -attr vt d
+load net {FRAME:acc#10.itm(3)} -attr vt d
+load netBundle {FRAME:acc#10.itm} 4 {FRAME:acc#10.itm(0)} {FRAME:acc#10.itm(1)} {FRAME:acc#10.itm(2)} {FRAME:acc#10.itm(3)} -attr xrf 25285 -attr oid 581 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {conc#677.itm(0)} -attr vt d
+load net {conc#677.itm(1)} -attr vt d
+load net {conc#677.itm(2)} -attr vt d
+load netBundle {conc#677.itm} 3 {conc#677.itm(0)} {conc#677.itm(1)} {conc#677.itm(2)} -attr xrf 25286 -attr oid 582 -attr vt d -attr @path {/sobel/sobel:core/conc#677.itm}
+load net {conc#678.itm(0)} -attr vt d
+load net {conc#678.itm(1)} -attr vt d
+load net {conc#678.itm(2)} -attr vt d
+load net {conc#678.itm(3)} -attr vt d
+load net {conc#678.itm(4)} -attr vt d
+load netBundle {conc#678.itm} 5 {conc#678.itm(0)} {conc#678.itm(1)} {conc#678.itm(2)} {conc#678.itm(3)} {conc#678.itm(4)} -attr xrf 25287 -attr oid 583 -attr vt d -attr @path {/sobel/sobel:core/conc#678.itm}
+load net {slc(acc.imod#12.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#12.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#12.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#12.sva)#1.itm} 3 {slc(acc.imod#12.sva)#1.itm(0)} {slc(acc.imod#12.sva)#1.itm(1)} {slc(acc.imod#12.sva)#1.itm(2)} -attr xrf 25288 -attr oid 584 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#1.itm}
+load net {FRAME:conc#15.itm(0)} -attr vt d
+load net {FRAME:conc#15.itm(1)} -attr vt d
+load net {FRAME:conc#15.itm(2)} -attr vt d
+load net {FRAME:conc#15.itm(3)} -attr vt d
+load netBundle {FRAME:conc#15.itm} 4 {FRAME:conc#15.itm(0)} {FRAME:conc#15.itm(1)} {FRAME:conc#15.itm(2)} {FRAME:conc#15.itm(3)} -attr xrf 25289 -attr oid 585 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(0)} -attr vt d
+load net {FRAME:not#5.itm(1)} -attr vt d
+load net {FRAME:not#5.itm(2)} -attr vt d
+load netBundle {FRAME:not#5.itm} 3 {FRAME:not#5.itm(0)} {FRAME:not#5.itm(1)} {FRAME:not#5.itm(2)} -attr xrf 25290 -attr oid 586 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {slc(acc.imod#12.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#12.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#12.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#12.sva)#2.itm} 3 {slc(acc.imod#12.sva)#2.itm(0)} {slc(acc.imod#12.sva)#2.itm(1)} {slc(acc.imod#12.sva)#2.itm(2)} -attr xrf 25291 -attr oid 587 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#2.itm}
+load net {slc(acc.imod#12.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#12.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#12.sva)#4.itm} 2 {slc(acc.imod#12.sva)#4.itm(0)} {slc(acc.imod#12.sva)#4.itm(1)} -attr xrf 25292 -attr oid 588 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#4.itm}
+load net {FRAME:not#6.itm(0)} -attr vt d
+load net {FRAME:not#6.itm(1)} -attr vt d
+load net {FRAME:not#6.itm(2)} -attr vt d
+load netBundle {FRAME:not#6.itm} 3 {FRAME:not#6.itm(0)} {FRAME:not#6.itm(1)} {FRAME:not#6.itm(2)} -attr xrf 25293 -attr oid 589 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {slc(intensity#2.sg1.sva)#7.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#7.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#7.itm} 3 {slc(intensity#2.sg1.sva)#7.itm(0)} {slc(intensity#2.sg1.sva)#7.itm(1)} {slc(intensity#2.sg1.sva)#7.itm(2)} -attr xrf 25294 -attr oid 590 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#7.itm}
+load net {conc#679.itm(0)} -attr vt d
+load net {conc#679.itm(1)} -attr vt d
+load net {conc#679.itm(2)} -attr vt d
+load net {conc#679.itm(3)} -attr vt d
+load net {conc#679.itm(4)} -attr vt d
+load netBundle {conc#679.itm} 5 {conc#679.itm(0)} {conc#679.itm(1)} {conc#679.itm(2)} {conc#679.itm(3)} {conc#679.itm(4)} -attr xrf 25295 -attr oid 591 -attr vt d -attr @path {/sobel/sobel:core/conc#679.itm}
+load net {exs#62.itm(0)} -attr vt d
+load net {exs#62.itm(1)} -attr vt d
+load net {exs#62.itm(2)} -attr vt d
+load net {exs#62.itm(3)} -attr vt d
+load net {exs#62.itm(4)} -attr vt d
+load net {exs#62.itm(5)} -attr vt d
+load net {exs#62.itm(6)} -attr vt d
+load net {exs#62.itm(7)} -attr vt d
+load net {exs#62.itm(8)} -attr vt d
+load net {exs#62.itm(9)} -attr vt d
+load net {exs#62.itm(10)} -attr vt d
+load netBundle {exs#62.itm} 11 {exs#62.itm(0)} {exs#62.itm(1)} {exs#62.itm(2)} {exs#62.itm(3)} {exs#62.itm(4)} {exs#62.itm(5)} {exs#62.itm(6)} {exs#62.itm(7)} {exs#62.itm(8)} {exs#62.itm(9)} {exs#62.itm(10)} -attr xrf 25296 -attr oid 592 -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {conc#680.itm(0)} -attr vt d
+load net {conc#680.itm(1)} -attr vt d
+load net {conc#680.itm(2)} -attr vt d
+load net {conc#680.itm(3)} -attr vt d
+load net {conc#680.itm(4)} -attr vt d
+load net {conc#680.itm(5)} -attr vt d
+load net {conc#680.itm(6)} -attr vt d
+load net {conc#680.itm(7)} -attr vt d
+load net {conc#680.itm(8)} -attr vt d
+load netBundle {conc#680.itm} 9 {conc#680.itm(0)} {conc#680.itm(1)} {conc#680.itm(2)} {conc#680.itm(3)} {conc#680.itm(4)} {conc#680.itm(5)} {conc#680.itm(6)} {conc#680.itm(7)} {conc#680.itm(8)} -attr xrf 25297 -attr oid 593 -attr vt d -attr @path {/sobel/sobel:core/conc#680.itm}
+load net {FRAME:exs#5.itm(0)} -attr vt d
+load net {FRAME:exs#5.itm(1)} -attr vt d
+load net {FRAME:exs#5.itm(2)} -attr vt d
+load netBundle {FRAME:exs#5.itm} 3 {FRAME:exs#5.itm(0)} {FRAME:exs#5.itm(1)} {FRAME:exs#5.itm(2)} -attr xrf 25298 -attr oid 594 -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#5.itm}
+load net {ACC1:acc.itm(0)} -attr vt d
+load net {ACC1:acc.itm(1)} -attr vt d
+load net {ACC1:acc.itm(2)} -attr vt d
+load net {ACC1:acc.itm(3)} -attr vt d
+load net {ACC1:acc.itm(4)} -attr vt d
+load net {ACC1:acc.itm(5)} -attr vt d
+load net {ACC1:acc.itm(6)} -attr vt d
+load net {ACC1:acc.itm(7)} -attr vt d
+load net {ACC1:acc.itm(8)} -attr vt d
+load net {ACC1:acc.itm(9)} -attr vt d
+load net {ACC1:acc.itm(10)} -attr vt d
+load net {ACC1:acc.itm(11)} -attr vt d
+load net {ACC1:acc.itm(12)} -attr vt d
+load net {ACC1:acc.itm(13)} -attr vt d
+load net {ACC1:acc.itm(14)} -attr vt d
+load net {ACC1:acc.itm(15)} -attr vt d
+load netBundle {ACC1:acc.itm} 16 {ACC1:acc.itm(0)} {ACC1:acc.itm(1)} {ACC1:acc.itm(2)} {ACC1:acc.itm(3)} {ACC1:acc.itm(4)} {ACC1:acc.itm(5)} {ACC1:acc.itm(6)} {ACC1:acc.itm(7)} {ACC1:acc.itm(8)} {ACC1:acc.itm(9)} {ACC1:acc.itm(10)} {ACC1:acc.itm(11)} {ACC1:acc.itm(12)} {ACC1:acc.itm(13)} {ACC1:acc.itm(14)} {ACC1:acc.itm(15)} -attr xrf 25299 -attr oid 595 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc#342.itm(0)} -attr vt d
+load net {ACC1:acc#342.itm(1)} -attr vt d
+load net {ACC1:acc#342.itm(2)} -attr vt d
+load net {ACC1:acc#342.itm(3)} -attr vt d
+load net {ACC1:acc#342.itm(4)} -attr vt d
+load net {ACC1:acc#342.itm(5)} -attr vt d
+load net {ACC1:acc#342.itm(6)} -attr vt d
+load net {ACC1:acc#342.itm(7)} -attr vt d
+load net {ACC1:acc#342.itm(8)} -attr vt d
+load net {ACC1:acc#342.itm(9)} -attr vt d
+load net {ACC1:acc#342.itm(10)} -attr vt d
+load net {ACC1:acc#342.itm(11)} -attr vt d
+load net {ACC1:acc#342.itm(12)} -attr vt d
+load net {ACC1:acc#342.itm(13)} -attr vt d
+load net {ACC1:acc#342.itm(14)} -attr vt d
+load net {ACC1:acc#342.itm(15)} -attr vt d
+load netBundle {ACC1:acc#342.itm} 16 {ACC1:acc#342.itm(0)} {ACC1:acc#342.itm(1)} {ACC1:acc#342.itm(2)} {ACC1:acc#342.itm(3)} {ACC1:acc#342.itm(4)} {ACC1:acc#342.itm(5)} {ACC1:acc#342.itm(6)} {ACC1:acc#342.itm(7)} {ACC1:acc#342.itm(8)} {ACC1:acc#342.itm(9)} {ACC1:acc#342.itm(10)} {ACC1:acc#342.itm(11)} {ACC1:acc#342.itm(12)} {ACC1:acc#342.itm(13)} {ACC1:acc#342.itm(14)} {ACC1:acc#342.itm(15)} -attr xrf 25300 -attr oid 596 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {FRAME:acc#9.itm(0)} -attr vt d
+load net {FRAME:acc#9.itm(1)} -attr vt d
+load net {FRAME:acc#9.itm(2)} -attr vt d
+load net {FRAME:acc#9.itm(3)} -attr vt d
+load net {FRAME:acc#9.itm(4)} -attr vt d
+load net {FRAME:acc#9.itm(5)} -attr vt d
+load netBundle {FRAME:acc#9.itm} 6 {FRAME:acc#9.itm(0)} {FRAME:acc#9.itm(1)} {FRAME:acc#9.itm(2)} {FRAME:acc#9.itm(3)} {FRAME:acc#9.itm(4)} {FRAME:acc#9.itm(5)} -attr xrf 25301 -attr oid 597 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#8.itm(0)} -attr vt d
+load net {FRAME:acc#8.itm(1)} -attr vt d
+load net {FRAME:acc#8.itm(2)} -attr vt d
+load net {FRAME:acc#8.itm(3)} -attr vt d
+load net {FRAME:acc#8.itm(4)} -attr vt d
+load netBundle {FRAME:acc#8.itm} 5 {FRAME:acc#8.itm(0)} {FRAME:acc#8.itm(1)} {FRAME:acc#8.itm(2)} {FRAME:acc#8.itm(3)} {FRAME:acc#8.itm(4)} -attr xrf 25302 -attr oid 598 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#6.itm(0)} -attr vt d
+load net {FRAME:acc#6.itm(1)} -attr vt d
+load net {FRAME:acc#6.itm(2)} -attr vt d
+load net {FRAME:acc#6.itm(3)} -attr vt d
+load netBundle {FRAME:acc#6.itm} 4 {FRAME:acc#6.itm(0)} {FRAME:acc#6.itm(1)} {FRAME:acc#6.itm(2)} {FRAME:acc#6.itm(3)} -attr xrf 25303 -attr oid 599 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {slc(intensity#2.sg1.sva)#3.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#3.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#3.itm} 3 {slc(intensity#2.sg1.sva)#3.itm(0)} {slc(intensity#2.sg1.sva)#3.itm(1)} {slc(intensity#2.sg1.sva)#3.itm(2)} -attr xrf 25304 -attr oid 600 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#3.itm}
+load net {FRAME:not#2.itm(0)} -attr vt d
+load net {FRAME:not#2.itm(1)} -attr vt d
+load net {FRAME:not#2.itm(2)} -attr vt d
+load netBundle {FRAME:not#2.itm} 3 {FRAME:not#2.itm(0)} {FRAME:not#2.itm(1)} {FRAME:not#2.itm(2)} -attr xrf 25305 -attr oid 601 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {slc(intensity#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#1.itm} 3 {slc(intensity#2.sg1.sva)#1.itm(0)} {slc(intensity#2.sg1.sva)#1.itm(1)} {slc(intensity#2.sg1.sva)#1.itm(2)} -attr xrf 25306 -attr oid 602 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#1.itm}
+load net {FRAME:acc#5.itm(0)} -attr vt d
+load net {FRAME:acc#5.itm(1)} -attr vt d
+load net {FRAME:acc#5.itm(2)} -attr vt d
+load net {FRAME:acc#5.itm(3)} -attr vt d
+load netBundle {FRAME:acc#5.itm} 4 {FRAME:acc#5.itm(0)} {FRAME:acc#5.itm(1)} {FRAME:acc#5.itm(2)} {FRAME:acc#5.itm(3)} -attr xrf 25307 -attr oid 603 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {conc#682.itm(0)} -attr vt d
+load net {conc#682.itm(1)} -attr vt d
+load net {conc#682.itm(2)} -attr vt d
+load netBundle {conc#682.itm} 3 {conc#682.itm(0)} {conc#682.itm(1)} {conc#682.itm(2)} -attr xrf 25308 -attr oid 604 -attr vt d -attr @path {/sobel/sobel:core/conc#682.itm}
+load net {slc(intensity#2.sg1.sva).itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva).itm(1)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva).itm} 2 {slc(intensity#2.sg1.sva).itm(0)} {slc(intensity#2.sg1.sva).itm(1)} -attr xrf 25309 -attr oid 605 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva).itm}
+load net {FRAME:acc#7.itm(0)} -attr vt d
+load net {FRAME:acc#7.itm(1)} -attr vt d
+load net {FRAME:acc#7.itm(2)} -attr vt d
+load net {FRAME:acc#7.itm(3)} -attr vt d
+load netBundle {FRAME:acc#7.itm} 4 {FRAME:acc#7.itm(0)} {FRAME:acc#7.itm(1)} {FRAME:acc#7.itm(2)} {FRAME:acc#7.itm(3)} -attr xrf 25310 -attr oid 606 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {slc(intensity#2.sg1.sva)#5.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#5.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#5.itm} 3 {slc(intensity#2.sg1.sva)#5.itm(0)} {slc(intensity#2.sg1.sva)#5.itm(1)} {slc(intensity#2.sg1.sva)#5.itm(2)} -attr xrf 25311 -attr oid 607 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#5.itm}
+load net {FRAME:not#1.itm(0)} -attr vt d
+load net {FRAME:not#1.itm(1)} -attr vt d
+load net {FRAME:not#1.itm(2)} -attr vt d
+load netBundle {FRAME:not#1.itm} 3 {FRAME:not#1.itm(0)} {FRAME:not#1.itm(1)} {FRAME:not#1.itm(2)} -attr xrf 25312 -attr oid 608 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {slc(intensity#2.sg1.sva)#6.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#6.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#6.itm} 3 {slc(intensity#2.sg1.sva)#6.itm(0)} {slc(intensity#2.sg1.sva)#6.itm(1)} {slc(intensity#2.sg1.sva)#6.itm(2)} -attr xrf 25313 -attr oid 609 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#6.itm}
+load net {FRAME:for:mux#12.itm(0)} -attr vt d
+load net {FRAME:for:mux#12.itm(1)} -attr vt d
+load net {FRAME:for:mux#12.itm(2)} -attr vt d
+load net {FRAME:for:mux#12.itm(3)} -attr vt d
+load net {FRAME:for:mux#12.itm(4)} -attr vt d
+load net {FRAME:for:mux#12.itm(5)} -attr vt d
+load net {FRAME:for:mux#12.itm(6)} -attr vt d
+load net {FRAME:for:mux#12.itm(7)} -attr vt d
+load net {FRAME:for:mux#12.itm(8)} -attr vt d
+load net {FRAME:for:mux#12.itm(9)} -attr vt d
+load net {FRAME:for:mux#12.itm(10)} -attr vt d
+load net {FRAME:for:mux#12.itm(11)} -attr vt d
+load net {FRAME:for:mux#12.itm(12)} -attr vt d
+load net {FRAME:for:mux#12.itm(13)} -attr vt d
+load net {FRAME:for:mux#12.itm(14)} -attr vt d
+load net {FRAME:for:mux#12.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#12.itm} 16 {FRAME:for:mux#12.itm(0)} {FRAME:for:mux#12.itm(1)} {FRAME:for:mux#12.itm(2)} {FRAME:for:mux#12.itm(3)} {FRAME:for:mux#12.itm(4)} {FRAME:for:mux#12.itm(5)} {FRAME:for:mux#12.itm(6)} {FRAME:for:mux#12.itm(7)} {FRAME:for:mux#12.itm(8)} {FRAME:for:mux#12.itm(9)} {FRAME:for:mux#12.itm(10)} {FRAME:for:mux#12.itm(11)} {FRAME:for:mux#12.itm(12)} {FRAME:for:mux#12.itm(13)} {FRAME:for:mux#12.itm(14)} {FRAME:for:mux#12.itm(15)} -attr xrf 25314 -attr oid 610 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:exs#21.itm(0)} -attr vt d
+load net {FRAME:for:exs#21.itm(1)} -attr vt d
+load net {FRAME:for:exs#21.itm(2)} -attr vt d
+load net {FRAME:for:exs#21.itm(3)} -attr vt d
+load net {FRAME:for:exs#21.itm(4)} -attr vt d
+load net {FRAME:for:exs#21.itm(5)} -attr vt d
+load net {FRAME:for:exs#21.itm(6)} -attr vt d
+load net {FRAME:for:exs#21.itm(7)} -attr vt d
+load net {FRAME:for:exs#21.itm(8)} -attr vt d
+load net {FRAME:for:exs#21.itm(9)} -attr vt d
+load net {FRAME:for:exs#21.itm(10)} -attr vt d
+load net {FRAME:for:exs#21.itm(11)} -attr vt d
+load net {FRAME:for:exs#21.itm(12)} -attr vt d
+load net {FRAME:for:exs#21.itm(13)} -attr vt d
+load net {FRAME:for:exs#21.itm(14)} -attr vt d
+load net {FRAME:for:exs#21.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#21.itm} 16 {FRAME:for:exs#21.itm(0)} {FRAME:for:exs#21.itm(1)} {FRAME:for:exs#21.itm(2)} {FRAME:for:exs#21.itm(3)} {FRAME:for:exs#21.itm(4)} {FRAME:for:exs#21.itm(5)} {FRAME:for:exs#21.itm(6)} {FRAME:for:exs#21.itm(7)} {FRAME:for:exs#21.itm(8)} {FRAME:for:exs#21.itm(9)} {FRAME:for:exs#21.itm(10)} {FRAME:for:exs#21.itm(11)} {FRAME:for:exs#21.itm(12)} {FRAME:for:exs#21.itm(13)} {FRAME:for:exs#21.itm(14)} {FRAME:for:exs#21.itm(15)} -attr xrf 25315 -attr oid 611 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:mux#11.itm(0)} -attr vt d
+load net {FRAME:for:mux#11.itm(1)} -attr vt d
+load net {FRAME:for:mux#11.itm(2)} -attr vt d
+load net {FRAME:for:mux#11.itm(3)} -attr vt d
+load net {FRAME:for:mux#11.itm(4)} -attr vt d
+load net {FRAME:for:mux#11.itm(5)} -attr vt d
+load net {FRAME:for:mux#11.itm(6)} -attr vt d
+load net {FRAME:for:mux#11.itm(7)} -attr vt d
+load net {FRAME:for:mux#11.itm(8)} -attr vt d
+load net {FRAME:for:mux#11.itm(9)} -attr vt d
+load net {FRAME:for:mux#11.itm(10)} -attr vt d
+load net {FRAME:for:mux#11.itm(11)} -attr vt d
+load net {FRAME:for:mux#11.itm(12)} -attr vt d
+load net {FRAME:for:mux#11.itm(13)} -attr vt d
+load net {FRAME:for:mux#11.itm(14)} -attr vt d
+load net {FRAME:for:mux#11.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#11.itm} 16 {FRAME:for:mux#11.itm(0)} {FRAME:for:mux#11.itm(1)} {FRAME:for:mux#11.itm(2)} {FRAME:for:mux#11.itm(3)} {FRAME:for:mux#11.itm(4)} {FRAME:for:mux#11.itm(5)} {FRAME:for:mux#11.itm(6)} {FRAME:for:mux#11.itm(7)} {FRAME:for:mux#11.itm(8)} {FRAME:for:mux#11.itm(9)} {FRAME:for:mux#11.itm(10)} {FRAME:for:mux#11.itm(11)} {FRAME:for:mux#11.itm(12)} {FRAME:for:mux#11.itm(13)} {FRAME:for:mux#11.itm(14)} {FRAME:for:mux#11.itm(15)} -attr xrf 25316 -attr oid 612 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:exs#20.itm(0)} -attr vt d
+load net {FRAME:for:exs#20.itm(1)} -attr vt d
+load net {FRAME:for:exs#20.itm(2)} -attr vt d
+load net {FRAME:for:exs#20.itm(3)} -attr vt d
+load net {FRAME:for:exs#20.itm(4)} -attr vt d
+load net {FRAME:for:exs#20.itm(5)} -attr vt d
+load net {FRAME:for:exs#20.itm(6)} -attr vt d
+load net {FRAME:for:exs#20.itm(7)} -attr vt d
+load net {FRAME:for:exs#20.itm(8)} -attr vt d
+load net {FRAME:for:exs#20.itm(9)} -attr vt d
+load net {FRAME:for:exs#20.itm(10)} -attr vt d
+load net {FRAME:for:exs#20.itm(11)} -attr vt d
+load net {FRAME:for:exs#20.itm(12)} -attr vt d
+load net {FRAME:for:exs#20.itm(13)} -attr vt d
+load net {FRAME:for:exs#20.itm(14)} -attr vt d
+load net {FRAME:for:exs#20.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#20.itm} 16 {FRAME:for:exs#20.itm(0)} {FRAME:for:exs#20.itm(1)} {FRAME:for:exs#20.itm(2)} {FRAME:for:exs#20.itm(3)} {FRAME:for:exs#20.itm(4)} {FRAME:for:exs#20.itm(5)} {FRAME:for:exs#20.itm(6)} {FRAME:for:exs#20.itm(7)} {FRAME:for:exs#20.itm(8)} {FRAME:for:exs#20.itm(9)} {FRAME:for:exs#20.itm(10)} {FRAME:for:exs#20.itm(11)} {FRAME:for:exs#20.itm(12)} {FRAME:for:exs#20.itm(13)} {FRAME:for:exs#20.itm(14)} {FRAME:for:exs#20.itm(15)} -attr xrf 25317 -attr oid 613 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:exs#19.itm(0)} -attr vt d
+load net {FRAME:for:exs#19.itm(1)} -attr vt d
+load netBundle {FRAME:for:exs#19.itm} 2 {FRAME:for:exs#19.itm(0)} {FRAME:for:exs#19.itm(1)} -attr xrf 25318 -attr oid 614 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#19.itm}
+load net {slc(ACC1:acc#110.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#110.psp#1.sva).itm(1)} -attr vt d
+load net {slc(ACC1:acc#110.psp#1.sva).itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#110.psp#1.sva).itm} 3 {slc(ACC1:acc#110.psp#1.sva).itm(0)} {slc(ACC1:acc#110.psp#1.sva).itm(1)} {slc(ACC1:acc#110.psp#1.sva).itm(2)} -attr xrf 25319 -attr oid 615 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.sva).itm}
+load net {slc(ACC1:acc#118.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#118.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#118.psp.sva).itm} 2 {slc(ACC1:acc#118.psp.sva).itm(0)} {slc(ACC1:acc#118.psp.sva).itm(1)} -attr xrf 25320 -attr oid 616 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp.sva).itm}
+load net {slc(regs.regs(1).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(9)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(10)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(11)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(12)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(13)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(14)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(15)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(16)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(17)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(18)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(19)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(20)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(21)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(22)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(23)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(24)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(25)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(26)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(27)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(28)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(29)} -attr vt d
+load netBundle {slc(regs.regs(1).sva).itm} 30 {slc(regs.regs(1).sva).itm(0)} {slc(regs.regs(1).sva).itm(1)} {slc(regs.regs(1).sva).itm(2)} {slc(regs.regs(1).sva).itm(3)} {slc(regs.regs(1).sva).itm(4)} {slc(regs.regs(1).sva).itm(5)} {slc(regs.regs(1).sva).itm(6)} {slc(regs.regs(1).sva).itm(7)} {slc(regs.regs(1).sva).itm(8)} {slc(regs.regs(1).sva).itm(9)} {slc(regs.regs(1).sva).itm(10)} {slc(regs.regs(1).sva).itm(11)} {slc(regs.regs(1).sva).itm(12)} {slc(regs.regs(1).sva).itm(13)} {slc(regs.regs(1).sva).itm(14)} {slc(regs.regs(1).sva).itm(15)} {slc(regs.regs(1).sva).itm(16)} {slc(regs.regs(1).sva).itm(17)} {slc(regs.regs(1).sva).itm(18)} {slc(regs.regs(1).sva).itm(19)} {slc(regs.regs(1).sva).itm(20)} {slc(regs.regs(1).sva).itm(21)} {slc(regs.regs(1).sva).itm(22)} {slc(regs.regs(1).sva).itm(23)} {slc(regs.regs(1).sva).itm(24)} {slc(regs.regs(1).sva).itm(25)} {slc(regs.regs(1).sva).itm(26)} {slc(regs.regs(1).sva).itm(27)} {slc(regs.regs(1).sva).itm(28)} {slc(regs.regs(1).sva).itm(29)} -attr xrf 25321 -attr oid 617 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {slc(regs.regs(1).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(9)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(10)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(11)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(12)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(13)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(14)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(15)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(16)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(17)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(18)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(19)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(20)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(21)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(22)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(23)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(24)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(25)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(26)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(27)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(28)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(29)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#1.itm} 30 {slc(regs.regs(1).sva)#1.itm(0)} {slc(regs.regs(1).sva)#1.itm(1)} {slc(regs.regs(1).sva)#1.itm(2)} {slc(regs.regs(1).sva)#1.itm(3)} {slc(regs.regs(1).sva)#1.itm(4)} {slc(regs.regs(1).sva)#1.itm(5)} {slc(regs.regs(1).sva)#1.itm(6)} {slc(regs.regs(1).sva)#1.itm(7)} {slc(regs.regs(1).sva)#1.itm(8)} {slc(regs.regs(1).sva)#1.itm(9)} {slc(regs.regs(1).sva)#1.itm(10)} {slc(regs.regs(1).sva)#1.itm(11)} {slc(regs.regs(1).sva)#1.itm(12)} {slc(regs.regs(1).sva)#1.itm(13)} {slc(regs.regs(1).sva)#1.itm(14)} {slc(regs.regs(1).sva)#1.itm(15)} {slc(regs.regs(1).sva)#1.itm(16)} {slc(regs.regs(1).sva)#1.itm(17)} {slc(regs.regs(1).sva)#1.itm(18)} {slc(regs.regs(1).sva)#1.itm(19)} {slc(regs.regs(1).sva)#1.itm(20)} {slc(regs.regs(1).sva)#1.itm(21)} {slc(regs.regs(1).sva)#1.itm(22)} {slc(regs.regs(1).sva)#1.itm(23)} {slc(regs.regs(1).sva)#1.itm(24)} {slc(regs.regs(1).sva)#1.itm(25)} {slc(regs.regs(1).sva)#1.itm(26)} {slc(regs.regs(1).sva)#1.itm(27)} {slc(regs.regs(1).sva)#1.itm(28)} {slc(regs.regs(1).sva)#1.itm(29)} -attr xrf 25322 -attr oid 618 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {ACC1:slc#45.itm(0)} -attr vt d
+load net {ACC1:slc#45.itm(1)} -attr vt d
+load netBundle {ACC1:slc#45.itm} 2 {ACC1:slc#45.itm(0)} {ACC1:slc#45.itm(1)} -attr xrf 25323 -attr oid 619 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#45.itm}
+load net {ACC1:acc#179.itm(0)} -attr vt d
+load net {ACC1:acc#179.itm(1)} -attr vt d
+load net {ACC1:acc#179.itm(2)} -attr vt d
+load netBundle {ACC1:acc#179.itm} 3 {ACC1:acc#179.itm(0)} {ACC1:acc#179.itm(1)} {ACC1:acc#179.itm(2)} -attr xrf 25324 -attr oid 620 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {conc#683.itm(0)} -attr vt d
+load net {conc#683.itm(1)} -attr vt d
+load net {conc#683.itm(2)} -attr vt d
+load netBundle {conc#683.itm} 3 {conc#683.itm(0)} {conc#683.itm(1)} {conc#683.itm(2)} -attr xrf 25325 -attr oid 621 -attr vt d -attr @path {/sobel/sobel:core/conc#683.itm}
+load net {ACC1:conc#531.itm(0)} -attr vt d
+load net {ACC1:conc#531.itm(1)} -attr vt d
+load netBundle {ACC1:conc#531.itm} 2 {ACC1:conc#531.itm(0)} {ACC1:conc#531.itm(1)} -attr xrf 25326 -attr oid 622 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#531.itm}
+load net {slc(acc.imod#6.sva)#3.itm(0)} -attr vt d
+load net {slc(acc.imod#6.sva)#3.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#6.sva)#3.itm} 2 {slc(acc.imod#6.sva)#3.itm(0)} {slc(acc.imod#6.sva)#3.itm(1)} -attr xrf 25327 -attr oid 623 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#3.itm}
+load net {ACC1:acc#150.itm(0)} -attr vt d
+load net {ACC1:acc#150.itm(1)} -attr vt d
+load net {ACC1:acc#150.itm(2)} -attr vt d
+load net {ACC1:acc#150.itm(3)} -attr vt d
+load netBundle {ACC1:acc#150.itm} 4 {ACC1:acc#150.itm(0)} {ACC1:acc#150.itm(1)} {ACC1:acc#150.itm(2)} {ACC1:acc#150.itm(3)} -attr xrf 25328 -attr oid 624 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load net {conc#684.itm(0)} -attr vt d
+load net {conc#684.itm(1)} -attr vt d
+load net {conc#684.itm(2)} -attr vt d
+load netBundle {conc#684.itm} 3 {conc#684.itm(0)} {conc#684.itm(1)} {conc#684.itm(2)} -attr xrf 25329 -attr oid 625 -attr vt d -attr @path {/sobel/sobel:core/conc#684.itm}
+load net {ACC1-1:not#147.itm(0)} -attr vt d
+load net {ACC1-1:not#147.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#147.itm} 2 {ACC1-1:not#147.itm(0)} {ACC1-1:not#147.itm(1)} -attr xrf 25330 -attr oid 626 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#147.itm}
+load net {slc(ACC1:acc#118.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#118.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#118.psp#1.sva).itm} 2 {slc(ACC1:acc#118.psp#1.sva).itm(0)} {slc(ACC1:acc#118.psp#1.sva).itm(1)} -attr xrf 25331 -attr oid 627 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp#1.sva).itm}
+load net {conc#685.itm(0)} -attr vt d
+load net {conc#685.itm(1)} -attr vt d
+load netBundle {conc#685.itm} 2 {conc#685.itm(0)} {conc#685.itm(1)} -attr xrf 25332 -attr oid 628 -attr vt d -attr @path {/sobel/sobel:core/conc#685.itm}
+load net {ACC1:slc#19.itm(0)} -attr vt d
+load net {ACC1:slc#19.itm(1)} -attr vt d
+load netBundle {ACC1:slc#19.itm} 2 {ACC1:slc#19.itm(0)} {ACC1:slc#19.itm(1)} -attr xrf 25333 -attr oid 629 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#19.itm}
+load net {ACC1:acc#149.itm(0)} -attr vt d
+load net {ACC1:acc#149.itm(1)} -attr vt d
+load net {ACC1:acc#149.itm(2)} -attr vt d
+load netBundle {ACC1:acc#149.itm} 3 {ACC1:acc#149.itm(0)} {ACC1:acc#149.itm(1)} {ACC1:acc#149.itm(2)} -attr xrf 25334 -attr oid 630 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149.itm}
+load net {conc#686.itm(0)} -attr vt d
+load net {conc#686.itm(1)} -attr vt d
+load netBundle {conc#686.itm} 2 {conc#686.itm(0)} {conc#686.itm(1)} -attr xrf 25335 -attr oid 631 -attr vt d -attr @path {/sobel/sobel:core/conc#686.itm}
+load net {ACC1:conc#472.itm(0)} -attr vt d
+load net {ACC1:conc#472.itm(1)} -attr vt d
+load netBundle {ACC1:conc#472.itm} 2 {ACC1:conc#472.itm(0)} {ACC1:conc#472.itm(1)} -attr xrf 25336 -attr oid 632 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#472.itm}
+load net {ACC1:acc#148.itm(0)} -attr vt d
+load net {ACC1:acc#148.itm(1)} -attr vt d
+load net {ACC1:acc#148.itm(2)} -attr vt d
+load net {ACC1:acc#148.itm(3)} -attr vt d
+load net {ACC1:acc#148.itm(4)} -attr vt d
+load netBundle {ACC1:acc#148.itm} 5 {ACC1:acc#148.itm(0)} {ACC1:acc#148.itm(1)} {ACC1:acc#148.itm(2)} {ACC1:acc#148.itm(3)} {ACC1:acc#148.itm(4)} -attr xrf 25337 -attr oid 633 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {conc#687.itm(0)} -attr vt d
+load net {conc#687.itm(1)} -attr vt d
+load net {conc#687.itm(2)} -attr vt d
+load net {conc#687.itm(3)} -attr vt d
+load netBundle {conc#687.itm} 4 {conc#687.itm(0)} {conc#687.itm(1)} {conc#687.itm(2)} {conc#687.itm(3)} -attr xrf 25338 -attr oid 634 -attr vt d -attr @path {/sobel/sobel:core/conc#687.itm}
+load net {ACC1:slc#17.itm(0)} -attr vt d
+load net {ACC1:slc#17.itm(1)} -attr vt d
+load net {ACC1:slc#17.itm(2)} -attr vt d
+load netBundle {ACC1:slc#17.itm} 3 {ACC1:slc#17.itm(0)} {ACC1:slc#17.itm(1)} {ACC1:slc#17.itm(2)} -attr xrf 25339 -attr oid 635 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#17.itm}
+load net {ACC1:acc#147.itm(0)} -attr vt d
+load net {ACC1:acc#147.itm(1)} -attr vt d
+load net {ACC1:acc#147.itm(2)} -attr vt d
+load net {ACC1:acc#147.itm(3)} -attr vt d
+load netBundle {ACC1:acc#147.itm} 4 {ACC1:acc#147.itm(0)} {ACC1:acc#147.itm(1)} {ACC1:acc#147.itm(2)} {ACC1:acc#147.itm(3)} -attr xrf 25340 -attr oid 636 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load net {conc#688.itm(0)} -attr vt d
+load net {conc#688.itm(1)} -attr vt d
+load net {conc#688.itm(2)} -attr vt d
+load net {conc#688.itm(3)} -attr vt d
+load netBundle {conc#688.itm} 4 {conc#688.itm(0)} {conc#688.itm(1)} {conc#688.itm(2)} {conc#688.itm(3)} -attr xrf 25341 -attr oid 637 -attr vt d -attr @path {/sobel/sobel:core/conc#688.itm}
+load net {ACC1:conc#468.itm(0)} -attr vt d
+load net {ACC1:conc#468.itm(1)} -attr vt d
+load net {ACC1:conc#468.itm(2)} -attr vt d
+load netBundle {ACC1:conc#468.itm} 3 {ACC1:conc#468.itm(0)} {ACC1:conc#468.itm(1)} {ACC1:conc#468.itm(2)} -attr xrf 25342 -attr oid 638 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#468.itm}
+load net {ACC1:slc#15.itm(0)} -attr vt d
+load net {ACC1:slc#15.itm(1)} -attr vt d
+load netBundle {ACC1:slc#15.itm} 2 {ACC1:slc#15.itm(0)} {ACC1:slc#15.itm(1)} -attr xrf 25343 -attr oid 639 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#15.itm}
+load net {ACC1:acc#145.itm(0)} -attr vt d
+load net {ACC1:acc#145.itm(1)} -attr vt d
+load net {ACC1:acc#145.itm(2)} -attr vt d
+load netBundle {ACC1:acc#145.itm} 3 {ACC1:acc#145.itm(0)} {ACC1:acc#145.itm(1)} {ACC1:acc#145.itm(2)} -attr xrf 25344 -attr oid 640 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145.itm}
+load net {conc#689.itm(0)} -attr vt d
+load net {conc#689.itm(1)} -attr vt d
+load netBundle {conc#689.itm} 2 {conc#689.itm(0)} {conc#689.itm(1)} -attr xrf 25345 -attr oid 641 -attr vt d -attr @path {/sobel/sobel:core/conc#689.itm}
+load net {ACC1:conc#464.itm(0)} -attr vt d
+load net {ACC1:conc#464.itm(1)} -attr vt d
+load netBundle {ACC1:conc#464.itm} 2 {ACC1:conc#464.itm(0)} {ACC1:conc#464.itm(1)} -attr xrf 25346 -attr oid 642 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#464.itm}
+load net {ACC1:conc#470.itm(0)} -attr vt d
+load net {ACC1:conc#470.itm(1)} -attr vt d
+load net {ACC1:conc#470.itm(2)} -attr vt d
+load net {ACC1:conc#470.itm(3)} -attr vt d
+load net {ACC1:conc#470.itm(4)} -attr vt d
+load netBundle {ACC1:conc#470.itm} 5 {ACC1:conc#470.itm(0)} {ACC1:conc#470.itm(1)} {ACC1:conc#470.itm(2)} {ACC1:conc#470.itm(3)} {ACC1:conc#470.itm(4)} -attr xrf 25347 -attr oid 643 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#470.itm}
+load net {ACC1:slc#16.itm(0)} -attr vt d
+load net {ACC1:slc#16.itm(1)} -attr vt d
+load net {ACC1:slc#16.itm(2)} -attr vt d
+load net {ACC1:slc#16.itm(3)} -attr vt d
+load netBundle {ACC1:slc#16.itm} 4 {ACC1:slc#16.itm(0)} {ACC1:slc#16.itm(1)} {ACC1:slc#16.itm(2)} {ACC1:slc#16.itm(3)} -attr xrf 25348 -attr oid 644 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#16.itm}
+load net {ACC1:acc#146.itm(0)} -attr vt d
+load net {ACC1:acc#146.itm(1)} -attr vt d
+load net {ACC1:acc#146.itm(2)} -attr vt d
+load net {ACC1:acc#146.itm(3)} -attr vt d
+load net {ACC1:acc#146.itm(4)} -attr vt d
+load netBundle {ACC1:acc#146.itm} 5 {ACC1:acc#146.itm(0)} {ACC1:acc#146.itm(1)} {ACC1:acc#146.itm(2)} {ACC1:acc#146.itm(3)} {ACC1:acc#146.itm(4)} -attr xrf 25349 -attr oid 645 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {conc#690.itm(0)} -attr vt d
+load net {conc#690.itm(1)} -attr vt d
+load net {conc#690.itm(2)} -attr vt d
+load netBundle {conc#690.itm} 3 {conc#690.itm(0)} {conc#690.itm(1)} {conc#690.itm(2)} -attr xrf 25350 -attr oid 646 -attr vt d -attr @path {/sobel/sobel:core/conc#690.itm}
+load net {ACC1:slc#14.itm(0)} -attr vt d
+load net {ACC1:slc#14.itm(1)} -attr vt d
+load netBundle {ACC1:slc#14.itm} 2 {ACC1:slc#14.itm(0)} {ACC1:slc#14.itm(1)} -attr xrf 25351 -attr oid 647 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#14.itm}
+load net {ACC1:acc#144.itm(0)} -attr vt d
+load net {ACC1:acc#144.itm(1)} -attr vt d
+load net {ACC1:acc#144.itm(2)} -attr vt d
+load netBundle {ACC1:acc#144.itm} 3 {ACC1:acc#144.itm(0)} {ACC1:acc#144.itm(1)} {ACC1:acc#144.itm(2)} -attr xrf 25352 -attr oid 648 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144.itm}
+load net {conc#691.itm(0)} -attr vt d
+load net {conc#691.itm(1)} -attr vt d
+load netBundle {conc#691.itm} 2 {conc#691.itm(0)} {conc#691.itm(1)} -attr xrf 25353 -attr oid 649 -attr vt d -attr @path {/sobel/sobel:core/conc#691.itm}
+load net {ACC1:conc#462.itm(0)} -attr vt d
+load net {ACC1:conc#462.itm(1)} -attr vt d
+load netBundle {ACC1:conc#462.itm} 2 {ACC1:conc#462.itm(0)} {ACC1:conc#462.itm(1)} -attr xrf 25354 -attr oid 650 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#462.itm}
+load net {ACC1:conc#466.itm(0)} -attr vt d
+load net {ACC1:conc#466.itm(1)} -attr vt d
+load net {ACC1:conc#466.itm(2)} -attr vt d
+load netBundle {ACC1:conc#466.itm} 3 {ACC1:conc#466.itm(0)} {ACC1:conc#466.itm(1)} {ACC1:conc#466.itm(2)} -attr xrf 25355 -attr oid 651 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#466.itm}
+load net {ACC1-1:not#120.itm(0)} -attr vt d
+load net {ACC1-1:not#120.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#120.itm} 2 {ACC1-1:not#120.itm(0)} {ACC1-1:not#120.itm(1)} -attr xrf 25356 -attr oid 652 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#120.itm}
+load net {slc(ACC1:acc#125.psp#1.sva)#8.itm(0)} -attr vt d
+load net {slc(ACC1:acc#125.psp#1.sva)#8.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#125.psp#1.sva)#8.itm} 2 {slc(ACC1:acc#125.psp#1.sva)#8.itm(0)} {slc(ACC1:acc#125.psp#1.sva)#8.itm(1)} -attr xrf 25357 -attr oid 653 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#8.itm}
+load net {ACC1:acc#143.itm(0)} -attr vt d
+load net {ACC1:acc#143.itm(1)} -attr vt d
+load net {ACC1:acc#143.itm(2)} -attr vt d
+load net {ACC1:acc#143.itm(3)} -attr vt d
+load net {ACC1:acc#143.itm(4)} -attr vt d
+load net {ACC1:acc#143.itm(5)} -attr vt d
+load net {ACC1:acc#143.itm(6)} -attr vt d
+load net {ACC1:acc#143.itm(7)} -attr vt d
+load net {ACC1:acc#143.itm(8)} -attr vt d
+load net {ACC1:acc#143.itm(9)} -attr vt d
+load net {ACC1:acc#143.itm(10)} -attr vt d
+load netBundle {ACC1:acc#143.itm} 11 {ACC1:acc#143.itm(0)} {ACC1:acc#143.itm(1)} {ACC1:acc#143.itm(2)} {ACC1:acc#143.itm(3)} {ACC1:acc#143.itm(4)} {ACC1:acc#143.itm(5)} {ACC1:acc#143.itm(6)} {ACC1:acc#143.itm(7)} {ACC1:acc#143.itm(8)} {ACC1:acc#143.itm(9)} {ACC1:acc#143.itm(10)} -attr xrf 25358 -attr oid 654 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:not#158.itm(0)} -attr vt d
+load net {ACC1:not#158.itm(1)} -attr vt d
+load net {ACC1:not#158.itm(2)} -attr vt d
+load net {ACC1:not#158.itm(3)} -attr vt d
+load net {ACC1:not#158.itm(4)} -attr vt d
+load net {ACC1:not#158.itm(5)} -attr vt d
+load net {ACC1:not#158.itm(6)} -attr vt d
+load net {ACC1:not#158.itm(7)} -attr vt d
+load net {ACC1:not#158.itm(8)} -attr vt d
+load net {ACC1:not#158.itm(9)} -attr vt d
+load netBundle {ACC1:not#158.itm} 10 {ACC1:not#158.itm(0)} {ACC1:not#158.itm(1)} {ACC1:not#158.itm(2)} {ACC1:not#158.itm(3)} {ACC1:not#158.itm(4)} {ACC1:not#158.itm(5)} {ACC1:not#158.itm(6)} {ACC1:not#158.itm(7)} {ACC1:not#158.itm(8)} {ACC1:not#158.itm(9)} -attr xrf 25359 -attr oid 655 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {slc(regs.regs(0).sva#4).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#4).itm} 10 {slc(regs.regs(0).sva#4).itm(0)} {slc(regs.regs(0).sva#4).itm(1)} {slc(regs.regs(0).sva#4).itm(2)} {slc(regs.regs(0).sva#4).itm(3)} {slc(regs.regs(0).sva#4).itm(4)} {slc(regs.regs(0).sva#4).itm(5)} {slc(regs.regs(0).sva#4).itm(6)} {slc(regs.regs(0).sva#4).itm(7)} {slc(regs.regs(0).sva#4).itm(8)} {slc(regs.regs(0).sva#4).itm(9)} -attr xrf 25360 -attr oid 656 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:not#159.itm(0)} -attr vt d
+load net {ACC1:not#159.itm(1)} -attr vt d
+load net {ACC1:not#159.itm(2)} -attr vt d
+load net {ACC1:not#159.itm(3)} -attr vt d
+load net {ACC1:not#159.itm(4)} -attr vt d
+load net {ACC1:not#159.itm(5)} -attr vt d
+load net {ACC1:not#159.itm(6)} -attr vt d
+load net {ACC1:not#159.itm(7)} -attr vt d
+load net {ACC1:not#159.itm(8)} -attr vt d
+load net {ACC1:not#159.itm(9)} -attr vt d
+load netBundle {ACC1:not#159.itm} 10 {ACC1:not#159.itm(0)} {ACC1:not#159.itm(1)} {ACC1:not#159.itm(2)} {ACC1:not#159.itm(3)} {ACC1:not#159.itm(4)} {ACC1:not#159.itm(5)} {ACC1:not#159.itm(6)} {ACC1:not#159.itm(7)} {ACC1:not#159.itm(8)} {ACC1:not#159.itm(9)} -attr xrf 25361 -attr oid 657 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {slc(regs.regs(0).sva#5).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#5).itm} 10 {slc(regs.regs(0).sva#5).itm(0)} {slc(regs.regs(0).sva#5).itm(1)} {slc(regs.regs(0).sva#5).itm(2)} {slc(regs.regs(0).sva#5).itm(3)} {slc(regs.regs(0).sva#5).itm(4)} {slc(regs.regs(0).sva#5).itm(5)} {slc(regs.regs(0).sva#5).itm(6)} {slc(regs.regs(0).sva#5).itm(7)} {slc(regs.regs(0).sva#5).itm(8)} {slc(regs.regs(0).sva#5).itm(9)} -attr xrf 25362 -attr oid 658 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {ACC1:acc#142.itm(0)} -attr vt d
+load net {ACC1:acc#142.itm(1)} -attr vt d
+load net {ACC1:acc#142.itm(2)} -attr vt d
+load net {ACC1:acc#142.itm(3)} -attr vt d
+load net {ACC1:acc#142.itm(4)} -attr vt d
+load net {ACC1:acc#142.itm(5)} -attr vt d
+load net {ACC1:acc#142.itm(6)} -attr vt d
+load net {ACC1:acc#142.itm(7)} -attr vt d
+load net {ACC1:acc#142.itm(8)} -attr vt d
+load net {ACC1:acc#142.itm(9)} -attr vt d
+load net {ACC1:acc#142.itm(10)} -attr vt d
+load netBundle {ACC1:acc#142.itm} 11 {ACC1:acc#142.itm(0)} {ACC1:acc#142.itm(1)} {ACC1:acc#142.itm(2)} {ACC1:acc#142.itm(3)} {ACC1:acc#142.itm(4)} {ACC1:acc#142.itm(5)} {ACC1:acc#142.itm(6)} {ACC1:acc#142.itm(7)} {ACC1:acc#142.itm(8)} {ACC1:acc#142.itm(9)} {ACC1:acc#142.itm(10)} -attr xrf 25363 -attr oid 659 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:not#160.itm(0)} -attr vt d
+load net {ACC1:not#160.itm(1)} -attr vt d
+load net {ACC1:not#160.itm(2)} -attr vt d
+load net {ACC1:not#160.itm(3)} -attr vt d
+load net {ACC1:not#160.itm(4)} -attr vt d
+load net {ACC1:not#160.itm(5)} -attr vt d
+load net {ACC1:not#160.itm(6)} -attr vt d
+load net {ACC1:not#160.itm(7)} -attr vt d
+load net {ACC1:not#160.itm(8)} -attr vt d
+load net {ACC1:not#160.itm(9)} -attr vt d
+load netBundle {ACC1:not#160.itm} 10 {ACC1:not#160.itm(0)} {ACC1:not#160.itm(1)} {ACC1:not#160.itm(2)} {ACC1:not#160.itm(3)} {ACC1:not#160.itm(4)} {ACC1:not#160.itm(5)} {ACC1:not#160.itm(6)} {ACC1:not#160.itm(7)} {ACC1:not#160.itm(8)} {ACC1:not#160.itm(9)} -attr xrf 25364 -attr oid 660 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {slc(regs.regs(0).sva#6).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#6).itm} 10 {slc(regs.regs(0).sva#6).itm(0)} {slc(regs.regs(0).sva#6).itm(1)} {slc(regs.regs(0).sva#6).itm(2)} {slc(regs.regs(0).sva#6).itm(3)} {slc(regs.regs(0).sva#6).itm(4)} {slc(regs.regs(0).sva#6).itm(5)} {slc(regs.regs(0).sva#6).itm(6)} {slc(regs.regs(0).sva#6).itm(7)} {slc(regs.regs(0).sva#6).itm(8)} {slc(regs.regs(0).sva#6).itm(9)} -attr xrf 25365 -attr oid 661 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:acc#176.itm(0)} -attr vt d
+load net {ACC1:acc#176.itm(1)} -attr vt d
+load net {ACC1:acc#176.itm(2)} -attr vt d
+load net {ACC1:acc#176.itm(3)} -attr vt d
+load net {ACC1:acc#176.itm(4)} -attr vt d
+load netBundle {ACC1:acc#176.itm} 5 {ACC1:acc#176.itm(0)} {ACC1:acc#176.itm(1)} {ACC1:acc#176.itm(2)} {ACC1:acc#176.itm(3)} {ACC1:acc#176.itm(4)} -attr xrf 25366 -attr oid 662 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {conc#692.itm(0)} -attr vt d
+load net {conc#692.itm(1)} -attr vt d
+load net {conc#692.itm(2)} -attr vt d
+load net {conc#692.itm(3)} -attr vt d
+load netBundle {conc#692.itm} 4 {conc#692.itm(0)} {conc#692.itm(1)} {conc#692.itm(2)} {conc#692.itm(3)} -attr xrf 25367 -attr oid 663 -attr vt d -attr @path {/sobel/sobel:core/conc#692.itm}
+load net {ACC1:slc#41.itm(0)} -attr vt d
+load net {ACC1:slc#41.itm(1)} -attr vt d
+load net {ACC1:slc#41.itm(2)} -attr vt d
+load netBundle {ACC1:slc#41.itm} 3 {ACC1:slc#41.itm(0)} {ACC1:slc#41.itm(1)} {ACC1:slc#41.itm(2)} -attr xrf 25368 -attr oid 664 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#41.itm}
+load net {ACC1:acc#175.itm(0)} -attr vt d
+load net {ACC1:acc#175.itm(1)} -attr vt d
+load net {ACC1:acc#175.itm(2)} -attr vt d
+load net {ACC1:acc#175.itm(3)} -attr vt d
+load netBundle {ACC1:acc#175.itm} 4 {ACC1:acc#175.itm(0)} {ACC1:acc#175.itm(1)} {ACC1:acc#175.itm(2)} {ACC1:acc#175.itm(3)} -attr xrf 25369 -attr oid 665 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load net {conc#693.itm(0)} -attr vt d
+load net {conc#693.itm(1)} -attr vt d
+load net {conc#693.itm(2)} -attr vt d
+load net {conc#693.itm(3)} -attr vt d
+load netBundle {conc#693.itm} 4 {conc#693.itm(0)} {conc#693.itm(1)} {conc#693.itm(2)} {conc#693.itm(3)} -attr xrf 25370 -attr oid 666 -attr vt d -attr @path {/sobel/sobel:core/conc#693.itm}
+load net {ACC1:conc#522.itm(0)} -attr vt d
+load net {ACC1:conc#522.itm(1)} -attr vt d
+load net {ACC1:conc#522.itm(2)} -attr vt d
+load netBundle {ACC1:conc#522.itm} 3 {ACC1:conc#522.itm(0)} {ACC1:conc#522.itm(1)} {ACC1:conc#522.itm(2)} -attr xrf 25371 -attr oid 667 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#522.itm}
+load net {ACC1:slc#39.itm(0)} -attr vt d
+load net {ACC1:slc#39.itm(1)} -attr vt d
+load netBundle {ACC1:slc#39.itm} 2 {ACC1:slc#39.itm(0)} {ACC1:slc#39.itm(1)} -attr xrf 25372 -attr oid 668 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#39.itm}
+load net {ACC1:acc#173.itm(0)} -attr vt d
+load net {ACC1:acc#173.itm(1)} -attr vt d
+load net {ACC1:acc#173.itm(2)} -attr vt d
+load netBundle {ACC1:acc#173.itm} 3 {ACC1:acc#173.itm(0)} {ACC1:acc#173.itm(1)} {ACC1:acc#173.itm(2)} -attr xrf 25373 -attr oid 669 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load net {conc#694.itm(0)} -attr vt d
+load net {conc#694.itm(1)} -attr vt d
+load netBundle {conc#694.itm} 2 {conc#694.itm(0)} {conc#694.itm(1)} -attr xrf 25374 -attr oid 670 -attr vt d -attr @path {/sobel/sobel:core/conc#694.itm}
+load net {ACC1:conc#518.itm(0)} -attr vt d
+load net {ACC1:conc#518.itm(1)} -attr vt d
+load netBundle {ACC1:conc#518.itm} 2 {ACC1:conc#518.itm(0)} {ACC1:conc#518.itm(1)} -attr xrf 25375 -attr oid 671 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#518.itm}
+load net {ACC1:conc#524.itm(0)} -attr vt d
+load net {ACC1:conc#524.itm(1)} -attr vt d
+load net {ACC1:conc#524.itm(2)} -attr vt d
+load net {ACC1:conc#524.itm(3)} -attr vt d
+load net {ACC1:conc#524.itm(4)} -attr vt d
+load netBundle {ACC1:conc#524.itm} 5 {ACC1:conc#524.itm(0)} {ACC1:conc#524.itm(1)} {ACC1:conc#524.itm(2)} {ACC1:conc#524.itm(3)} {ACC1:conc#524.itm(4)} -attr xrf 25376 -attr oid 672 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#524.itm}
+load net {ACC1:slc#40.itm(0)} -attr vt d
+load net {ACC1:slc#40.itm(1)} -attr vt d
+load net {ACC1:slc#40.itm(2)} -attr vt d
+load net {ACC1:slc#40.itm(3)} -attr vt d
+load netBundle {ACC1:slc#40.itm} 4 {ACC1:slc#40.itm(0)} {ACC1:slc#40.itm(1)} {ACC1:slc#40.itm(2)} {ACC1:slc#40.itm(3)} -attr xrf 25377 -attr oid 673 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1:acc#174.itm(0)} -attr vt d
+load net {ACC1:acc#174.itm(1)} -attr vt d
+load net {ACC1:acc#174.itm(2)} -attr vt d
+load net {ACC1:acc#174.itm(3)} -attr vt d
+load net {ACC1:acc#174.itm(4)} -attr vt d
+load netBundle {ACC1:acc#174.itm} 5 {ACC1:acc#174.itm(0)} {ACC1:acc#174.itm(1)} {ACC1:acc#174.itm(2)} {ACC1:acc#174.itm(3)} {ACC1:acc#174.itm(4)} -attr xrf 25378 -attr oid 674 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {conc#695.itm(0)} -attr vt d
+load net {conc#695.itm(1)} -attr vt d
+load net {conc#695.itm(2)} -attr vt d
+load netBundle {conc#695.itm} 3 {conc#695.itm(0)} {conc#695.itm(1)} {conc#695.itm(2)} -attr xrf 25379 -attr oid 675 -attr vt d -attr @path {/sobel/sobel:core/conc#695.itm}
+load net {ACC1:slc#38.itm(0)} -attr vt d
+load net {ACC1:slc#38.itm(1)} -attr vt d
+load netBundle {ACC1:slc#38.itm} 2 {ACC1:slc#38.itm(0)} {ACC1:slc#38.itm(1)} -attr xrf 25380 -attr oid 676 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#38.itm}
+load net {ACC1:acc#172.itm(0)} -attr vt d
+load net {ACC1:acc#172.itm(1)} -attr vt d
+load net {ACC1:acc#172.itm(2)} -attr vt d
+load netBundle {ACC1:acc#172.itm} 3 {ACC1:acc#172.itm(0)} {ACC1:acc#172.itm(1)} {ACC1:acc#172.itm(2)} -attr xrf 25381 -attr oid 677 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load net {conc#696.itm(0)} -attr vt d
+load net {conc#696.itm(1)} -attr vt d
+load netBundle {conc#696.itm} 2 {conc#696.itm(0)} {conc#696.itm(1)} -attr xrf 25382 -attr oid 678 -attr vt d -attr @path {/sobel/sobel:core/conc#696.itm}
+load net {ACC1:conc#516.itm(0)} -attr vt d
+load net {ACC1:conc#516.itm(1)} -attr vt d
+load netBundle {ACC1:conc#516.itm} 2 {ACC1:conc#516.itm(0)} {ACC1:conc#516.itm(1)} -attr xrf 25383 -attr oid 679 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#516.itm}
+load net {ACC1:conc#520.itm(0)} -attr vt d
+load net {ACC1:conc#520.itm(1)} -attr vt d
+load net {ACC1:conc#520.itm(2)} -attr vt d
+load netBundle {ACC1:conc#520.itm} 3 {ACC1:conc#520.itm(0)} {ACC1:conc#520.itm(1)} {ACC1:conc#520.itm(2)} -attr xrf 25384 -attr oid 680 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#520.itm}
+load net {ACC1-3:not#120.itm(0)} -attr vt d
+load net {ACC1-3:not#120.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#120.itm} 2 {ACC1-3:not#120.itm(0)} {ACC1-3:not#120.itm(1)} -attr xrf 25385 -attr oid 681 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#120.itm}
+load net {slc(ACC1:acc#125.psp.sva)#8.itm(0)} -attr vt d
+load net {slc(ACC1:acc#125.psp.sva)#8.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#125.psp.sva)#8.itm} 2 {slc(ACC1:acc#125.psp.sva)#8.itm(0)} {slc(ACC1:acc#125.psp.sva)#8.itm(1)} -attr xrf 25386 -attr oid 682 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#8.itm}
+load net {ACC1:acc#171.itm(0)} -attr vt d
+load net {ACC1:acc#171.itm(1)} -attr vt d
+load net {ACC1:acc#171.itm(2)} -attr vt d
+load net {ACC1:acc#171.itm(3)} -attr vt d
+load net {ACC1:acc#171.itm(4)} -attr vt d
+load net {ACC1:acc#171.itm(5)} -attr vt d
+load net {ACC1:acc#171.itm(6)} -attr vt d
+load net {ACC1:acc#171.itm(7)} -attr vt d
+load net {ACC1:acc#171.itm(8)} -attr vt d
+load net {ACC1:acc#171.itm(9)} -attr vt d
+load net {ACC1:acc#171.itm(10)} -attr vt d
+load netBundle {ACC1:acc#171.itm} 11 {ACC1:acc#171.itm(0)} {ACC1:acc#171.itm(1)} {ACC1:acc#171.itm(2)} {ACC1:acc#171.itm(3)} {ACC1:acc#171.itm(4)} {ACC1:acc#171.itm(5)} {ACC1:acc#171.itm(6)} {ACC1:acc#171.itm(7)} {ACC1:acc#171.itm(8)} {ACC1:acc#171.itm(9)} {ACC1:acc#171.itm(10)} -attr xrf 25387 -attr oid 683 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {slc(regs.regs(1).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#5.itm} 10 {slc(regs.regs(1).sva)#5.itm(0)} {slc(regs.regs(1).sva)#5.itm(1)} {slc(regs.regs(1).sva)#5.itm(2)} {slc(regs.regs(1).sva)#5.itm(3)} {slc(regs.regs(1).sva)#5.itm(4)} {slc(regs.regs(1).sva)#5.itm(5)} {slc(regs.regs(1).sva)#5.itm(6)} {slc(regs.regs(1).sva)#5.itm(7)} {slc(regs.regs(1).sva)#5.itm(8)} {slc(regs.regs(1).sva)#5.itm(9)} -attr xrf 25388 -attr oid 684 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {slc(regs.regs(1).sva)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#6.itm} 10 {slc(regs.regs(1).sva)#6.itm(0)} {slc(regs.regs(1).sva)#6.itm(1)} {slc(regs.regs(1).sva)#6.itm(2)} {slc(regs.regs(1).sva)#6.itm(3)} {slc(regs.regs(1).sva)#6.itm(4)} {slc(regs.regs(1).sva)#6.itm(5)} {slc(regs.regs(1).sva)#6.itm(6)} {slc(regs.regs(1).sva)#6.itm(7)} {slc(regs.regs(1).sva)#6.itm(8)} {slc(regs.regs(1).sva)#6.itm(9)} -attr xrf 25389 -attr oid 685 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {slc(regs.regs(1).sva)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#7.itm} 10 {slc(regs.regs(1).sva)#7.itm(0)} {slc(regs.regs(1).sva)#7.itm(1)} {slc(regs.regs(1).sva)#7.itm(2)} {slc(regs.regs(1).sva)#7.itm(3)} {slc(regs.regs(1).sva)#7.itm(4)} {slc(regs.regs(1).sva)#7.itm(5)} {slc(regs.regs(1).sva)#7.itm(6)} {slc(regs.regs(1).sva)#7.itm(7)} {slc(regs.regs(1).sva)#7.itm(8)} {slc(regs.regs(1).sva)#7.itm(9)} -attr xrf 25390 -attr oid 686 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {ACC1:slc#43.itm(0)} -attr vt d
+load net {ACC1:slc#43.itm(1)} -attr vt d
+load netBundle {ACC1:slc#43.itm} 2 {ACC1:slc#43.itm(0)} {ACC1:slc#43.itm(1)} -attr xrf 25391 -attr oid 687 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#43.itm}
+load net {ACC1:acc#177.itm(0)} -attr vt d
+load net {ACC1:acc#177.itm(1)} -attr vt d
+load net {ACC1:acc#177.itm(2)} -attr vt d
+load netBundle {ACC1:acc#177.itm} 3 {ACC1:acc#177.itm(0)} {ACC1:acc#177.itm(1)} {ACC1:acc#177.itm(2)} -attr xrf 25392 -attr oid 688 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {conc#697.itm(0)} -attr vt d
+load net {conc#697.itm(1)} -attr vt d
+load netBundle {conc#697.itm} 2 {conc#697.itm(0)} {conc#697.itm(1)} -attr xrf 25393 -attr oid 689 -attr vt d -attr @path {/sobel/sobel:core/conc#697.itm}
+load net {ACC1:conc#526.itm(0)} -attr vt d
+load net {ACC1:conc#526.itm(1)} -attr vt d
+load netBundle {ACC1:conc#526.itm} 2 {ACC1:conc#526.itm(0)} {ACC1:conc#526.itm(1)} -attr xrf 25394 -attr oid 690 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#526.itm}
+load net {ACC1:acc#178.itm(0)} -attr vt d
+load net {ACC1:acc#178.itm(1)} -attr vt d
+load net {ACC1:acc#178.itm(2)} -attr vt d
+load net {ACC1:acc#178.itm(3)} -attr vt d
+load netBundle {ACC1:acc#178.itm} 4 {ACC1:acc#178.itm(0)} {ACC1:acc#178.itm(1)} {ACC1:acc#178.itm(2)} {ACC1:acc#178.itm(3)} -attr xrf 25395 -attr oid 691 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {conc#698.itm(0)} -attr vt d
+load net {conc#698.itm(1)} -attr vt d
+load net {conc#698.itm(2)} -attr vt d
+load netBundle {conc#698.itm} 3 {conc#698.itm(0)} {conc#698.itm(1)} {conc#698.itm(2)} -attr xrf 25396 -attr oid 692 -attr vt d -attr @path {/sobel/sobel:core/conc#698.itm}
+load net {ACC1-3:not#147.itm(0)} -attr vt d
+load net {ACC1-3:not#147.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#147.itm} 2 {ACC1-3:not#147.itm(0)} {ACC1-3:not#147.itm(1)} -attr xrf 25397 -attr oid 693 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#147.itm}
+load net {slc(ACC1:acc#118.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#118.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#118.psp.sva)#2.itm} 2 {slc(ACC1:acc#118.psp.sva)#2.itm(0)} {slc(ACC1:acc#118.psp.sva)#2.itm(1)} -attr xrf 25398 -attr oid 694 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp.sva)#2.itm}
+load net {conc#699.itm(0)} -attr vt d
+load net {conc#699.itm(1)} -attr vt d
+load netBundle {conc#699.itm} 2 {conc#699.itm(0)} {conc#699.itm(1)} -attr xrf 25399 -attr oid 695 -attr vt d -attr @path {/sobel/sobel:core/conc#699.itm}
+load net {ACC1:acc#180.itm(0)} -attr vt d
+load net {ACC1:acc#180.itm(1)} -attr vt d
+load net {ACC1:acc#180.itm(2)} -attr vt d
+load net {ACC1:acc#180.itm(3)} -attr vt d
+load net {ACC1:acc#180.itm(4)} -attr vt d
+load net {ACC1:acc#180.itm(5)} -attr vt d
+load net {ACC1:acc#180.itm(6)} -attr vt d
+load net {ACC1:acc#180.itm(7)} -attr vt d
+load net {ACC1:acc#180.itm(8)} -attr vt d
+load net {ACC1:acc#180.itm(9)} -attr vt d
+load net {ACC1:acc#180.itm(10)} -attr vt d
+load netBundle {ACC1:acc#180.itm} 11 {ACC1:acc#180.itm(0)} {ACC1:acc#180.itm(1)} {ACC1:acc#180.itm(2)} {ACC1:acc#180.itm(3)} {ACC1:acc#180.itm(4)} {ACC1:acc#180.itm(5)} {ACC1:acc#180.itm(6)} {ACC1:acc#180.itm(7)} {ACC1:acc#180.itm(8)} {ACC1:acc#180.itm(9)} {ACC1:acc#180.itm(10)} -attr xrf 25400 -attr oid 696 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {slc(regs.regs(1).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#2.itm} 10 {slc(regs.regs(1).sva)#2.itm(0)} {slc(regs.regs(1).sva)#2.itm(1)} {slc(regs.regs(1).sva)#2.itm(2)} {slc(regs.regs(1).sva)#2.itm(3)} {slc(regs.regs(1).sva)#2.itm(4)} {slc(regs.regs(1).sva)#2.itm(5)} {slc(regs.regs(1).sva)#2.itm(6)} {slc(regs.regs(1).sva)#2.itm(7)} {slc(regs.regs(1).sva)#2.itm(8)} {slc(regs.regs(1).sva)#2.itm(9)} -attr xrf 25401 -attr oid 697 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {slc(regs.regs(1).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#3.itm} 10 {slc(regs.regs(1).sva)#3.itm(0)} {slc(regs.regs(1).sva)#3.itm(1)} {slc(regs.regs(1).sva)#3.itm(2)} {slc(regs.regs(1).sva)#3.itm(3)} {slc(regs.regs(1).sva)#3.itm(4)} {slc(regs.regs(1).sva)#3.itm(5)} {slc(regs.regs(1).sva)#3.itm(6)} {slc(regs.regs(1).sva)#3.itm(7)} {slc(regs.regs(1).sva)#3.itm(8)} {slc(regs.regs(1).sva)#3.itm(9)} -attr xrf 25402 -attr oid 698 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {slc(regs.regs(1).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#4.itm} 10 {slc(regs.regs(1).sva)#4.itm(0)} {slc(regs.regs(1).sva)#4.itm(1)} {slc(regs.regs(1).sva)#4.itm(2)} {slc(regs.regs(1).sva)#4.itm(3)} {slc(regs.regs(1).sva)#4.itm(4)} {slc(regs.regs(1).sva)#4.itm(5)} {slc(regs.regs(1).sva)#4.itm(6)} {slc(regs.regs(1).sva)#4.itm(7)} {slc(regs.regs(1).sva)#4.itm(8)} {slc(regs.regs(1).sva)#4.itm(9)} -attr xrf 25403 -attr oid 699 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {ACC1:slc#50.itm(0)} -attr vt d
+load net {ACC1:slc#50.itm(1)} -attr vt d
+load net {ACC1:slc#50.itm(2)} -attr vt d
+load net {ACC1:slc#50.itm(3)} -attr vt d
+load netBundle {ACC1:slc#50.itm} 4 {ACC1:slc#50.itm(0)} {ACC1:slc#50.itm(1)} {ACC1:slc#50.itm(2)} {ACC1:slc#50.itm(3)} -attr xrf 25404 -attr oid 700 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#185.itm(0)} -attr vt d
+load net {ACC1:acc#185.itm(1)} -attr vt d
+load net {ACC1:acc#185.itm(2)} -attr vt d
+load net {ACC1:acc#185.itm(3)} -attr vt d
+load net {ACC1:acc#185.itm(4)} -attr vt d
+load netBundle {ACC1:acc#185.itm} 5 {ACC1:acc#185.itm(0)} {ACC1:acc#185.itm(1)} {ACC1:acc#185.itm(2)} {ACC1:acc#185.itm(3)} {ACC1:acc#185.itm(4)} -attr xrf 25405 -attr oid 701 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {conc#700.itm(0)} -attr vt d
+load net {conc#700.itm(1)} -attr vt d
+load net {conc#700.itm(2)} -attr vt d
+load net {conc#700.itm(3)} -attr vt d
+load netBundle {conc#700.itm} 4 {conc#700.itm(0)} {conc#700.itm(1)} {conc#700.itm(2)} {conc#700.itm(3)} -attr xrf 25406 -attr oid 702 -attr vt d -attr @path {/sobel/sobel:core/conc#700.itm}
+load net {ACC1:slc#48.itm(0)} -attr vt d
+load net {ACC1:slc#48.itm(1)} -attr vt d
+load net {ACC1:slc#48.itm(2)} -attr vt d
+load netBundle {ACC1:slc#48.itm} 3 {ACC1:slc#48.itm(0)} {ACC1:slc#48.itm(1)} {ACC1:slc#48.itm(2)} -attr xrf 25407 -attr oid 703 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#48.itm}
+load net {ACC1:acc#183.itm(0)} -attr vt d
+load net {ACC1:acc#183.itm(1)} -attr vt d
+load net {ACC1:acc#183.itm(2)} -attr vt d
+load net {ACC1:acc#183.itm(3)} -attr vt d
+load netBundle {ACC1:acc#183.itm} 4 {ACC1:acc#183.itm(0)} {ACC1:acc#183.itm(1)} {ACC1:acc#183.itm(2)} {ACC1:acc#183.itm(3)} -attr xrf 25408 -attr oid 704 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load net {conc#701.itm(0)} -attr vt d
+load net {conc#701.itm(1)} -attr vt d
+load netBundle {conc#701.itm} 2 {conc#701.itm(0)} {conc#701.itm(1)} -attr xrf 25409 -attr oid 705 -attr vt d -attr @path {/sobel/sobel:core/conc#701.itm}
+load net {ACC1:conc#538.itm(0)} -attr vt d
+load net {ACC1:conc#538.itm(1)} -attr vt d
+load netBundle {ACC1:conc#538.itm} 2 {ACC1:conc#538.itm(0)} {ACC1:conc#538.itm(1)} -attr xrf 25410 -attr oid 706 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#538.itm}
+load net {conc#702.itm(0)} -attr vt d
+load net {conc#702.itm(1)} -attr vt d
+load net {conc#702.itm(2)} -attr vt d
+load net {conc#702.itm(3)} -attr vt d
+load netBundle {conc#702.itm} 4 {conc#702.itm(0)} {conc#702.itm(1)} {conc#702.itm(2)} {conc#702.itm(3)} -attr xrf 25411 -attr oid 707 -attr vt d -attr @path {/sobel/sobel:core/conc#702.itm}
+load net {ACC1:slc#49.itm(0)} -attr vt d
+load net {ACC1:slc#49.itm(1)} -attr vt d
+load net {ACC1:slc#49.itm(2)} -attr vt d
+load netBundle {ACC1:slc#49.itm} 3 {ACC1:slc#49.itm(0)} {ACC1:slc#49.itm(1)} {ACC1:slc#49.itm(2)} -attr xrf 25412 -attr oid 708 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#49.itm}
+load net {ACC1:acc#184.itm(0)} -attr vt d
+load net {ACC1:acc#184.itm(1)} -attr vt d
+load net {ACC1:acc#184.itm(2)} -attr vt d
+load net {ACC1:acc#184.itm(3)} -attr vt d
+load netBundle {ACC1:acc#184.itm} 4 {ACC1:acc#184.itm(0)} {ACC1:acc#184.itm(1)} {ACC1:acc#184.itm(2)} {ACC1:acc#184.itm(3)} -attr xrf 25413 -attr oid 709 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load net {conc#703.itm(0)} -attr vt d
+load net {conc#703.itm(1)} -attr vt d
+load net {conc#703.itm(2)} -attr vt d
+load netBundle {conc#703.itm} 3 {conc#703.itm(0)} {conc#703.itm(1)} {conc#703.itm(2)} -attr xrf 25414 -attr oid 710 -attr vt d -attr @path {/sobel/sobel:core/conc#703.itm}
+load net {ACC1:slc#47.itm(0)} -attr vt d
+load net {ACC1:slc#47.itm(1)} -attr vt d
+load netBundle {ACC1:slc#47.itm} 2 {ACC1:slc#47.itm(0)} {ACC1:slc#47.itm(1)} -attr xrf 25415 -attr oid 711 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#47.itm}
+load net {ACC1:acc#182.itm(0)} -attr vt d
+load net {ACC1:acc#182.itm(1)} -attr vt d
+load net {ACC1:acc#182.itm(2)} -attr vt d
+load netBundle {ACC1:acc#182.itm} 3 {ACC1:acc#182.itm(0)} {ACC1:acc#182.itm(1)} {ACC1:acc#182.itm(2)} -attr xrf 25416 -attr oid 712 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182.itm}
+load net {conc#704.itm(0)} -attr vt d
+load net {conc#704.itm(1)} -attr vt d
+load netBundle {conc#704.itm} 2 {conc#704.itm(0)} {conc#704.itm(1)} -attr xrf 25417 -attr oid 713 -attr vt d -attr @path {/sobel/sobel:core/conc#704.itm}
+load net {ACC1:conc#536.itm(0)} -attr vt d
+load net {ACC1:conc#536.itm(1)} -attr vt d
+load netBundle {ACC1:conc#536.itm} 2 {ACC1:conc#536.itm(0)} {ACC1:conc#536.itm(1)} -attr xrf 25418 -attr oid 714 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#536.itm}
+load net {ACC1:conc#540.itm(0)} -attr vt d
+load net {ACC1:conc#540.itm(1)} -attr vt d
+load net {ACC1:conc#540.itm(2)} -attr vt d
+load netBundle {ACC1:conc#540.itm} 3 {ACC1:conc#540.itm(0)} {ACC1:conc#540.itm(1)} {ACC1:conc#540.itm(2)} -attr xrf 25419 -attr oid 715 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#540.itm}
+load net {ACC1:slc#46.itm(0)} -attr vt d
+load net {ACC1:slc#46.itm(1)} -attr vt d
+load netBundle {ACC1:slc#46.itm} 2 {ACC1:slc#46.itm(0)} {ACC1:slc#46.itm(1)} -attr xrf 25420 -attr oid 716 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#46.itm}
+load net {ACC1:acc#181.itm(0)} -attr vt d
+load net {ACC1:acc#181.itm(1)} -attr vt d
+load net {ACC1:acc#181.itm(2)} -attr vt d
+load netBundle {ACC1:acc#181.itm} 3 {ACC1:acc#181.itm(0)} {ACC1:acc#181.itm(1)} {ACC1:acc#181.itm(2)} -attr xrf 25421 -attr oid 717 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181.itm}
+load net {conc#705.itm(0)} -attr vt d
+load net {conc#705.itm(1)} -attr vt d
+load netBundle {conc#705.itm} 2 {conc#705.itm(0)} {conc#705.itm(1)} -attr xrf 25422 -attr oid 718 -attr vt d -attr @path {/sobel/sobel:core/conc#705.itm}
+load net {ACC1:conc#534.itm(0)} -attr vt d
+load net {ACC1:conc#534.itm(1)} -attr vt d
+load netBundle {ACC1:conc#534.itm} 2 {ACC1:conc#534.itm(0)} {ACC1:conc#534.itm(1)} -attr xrf 25423 -attr oid 719 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#534.itm}
+load net {ACC1:slc#51.itm(0)} -attr vt d
+load net {ACC1:slc#51.itm(1)} -attr vt d
+load netBundle {ACC1:slc#51.itm} 2 {ACC1:slc#51.itm(0)} {ACC1:slc#51.itm(1)} -attr xrf 25424 -attr oid 720 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#51.itm}
+load net {ACC1:acc#186.itm(0)} -attr vt d
+load net {ACC1:acc#186.itm(1)} -attr vt d
+load net {ACC1:acc#186.itm(2)} -attr vt d
+load netBundle {ACC1:acc#186.itm} 3 {ACC1:acc#186.itm(0)} {ACC1:acc#186.itm(1)} {ACC1:acc#186.itm(2)} -attr xrf 25425 -attr oid 721 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186.itm}
+load net {conc#706.itm(0)} -attr vt d
+load net {conc#706.itm(1)} -attr vt d
+load netBundle {conc#706.itm} 2 {conc#706.itm(0)} {conc#706.itm(1)} -attr xrf 25426 -attr oid 722 -attr vt d -attr @path {/sobel/sobel:core/conc#706.itm}
+load net {ACC1:conc#544.itm(0)} -attr vt d
+load net {ACC1:conc#544.itm(1)} -attr vt d
+load netBundle {ACC1:conc#544.itm} 2 {ACC1:conc#544.itm(0)} {ACC1:conc#544.itm(1)} -attr xrf 25427 -attr oid 723 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#544.itm}
+load net {ACC1-3:exs#558.itm(0)} -attr vt d
+load net {ACC1-3:exs#558.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#558.itm} 2 {ACC1-3:exs#558.itm(0)} {ACC1-3:exs#558.itm(1)} -attr xrf 25428 -attr oid 724 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#558.itm}
+load net {ACC1-3:exs#547.itm(0)} -attr vt d
+load net {ACC1-3:exs#547.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#547.itm} 2 {ACC1-3:exs#547.itm(0)} {ACC1-3:exs#547.itm(1)} -attr xrf 25429 -attr oid 725 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#547.itm}
+load net {ACC1:acc#188.itm(0)} -attr vt d
+load net {ACC1:acc#188.itm(1)} -attr vt d
+load net {ACC1:acc#188.itm(2)} -attr vt d
+load netBundle {ACC1:acc#188.itm} 3 {ACC1:acc#188.itm(0)} {ACC1:acc#188.itm(1)} {ACC1:acc#188.itm(2)} -attr xrf 25430 -attr oid 726 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load net {conc#707.itm(0)} -attr vt d
+load net {conc#707.itm(1)} -attr vt d
+load net {conc#707.itm(2)} -attr vt d
+load netBundle {conc#707.itm} 3 {conc#707.itm(0)} {conc#707.itm(1)} {conc#707.itm(2)} -attr xrf 25431 -attr oid 727 -attr vt d -attr @path {/sobel/sobel:core/conc#707.itm}
+load net {ACC1:conc#549.itm(0)} -attr vt d
+load net {ACC1:conc#549.itm(1)} -attr vt d
+load netBundle {ACC1:conc#549.itm} 2 {ACC1:conc#549.itm(0)} {ACC1:conc#549.itm(1)} -attr xrf 25432 -attr oid 728 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#549.itm}
+load net {ACC1:acc#153.itm(0)} -attr vt d
+load net {ACC1:acc#153.itm(1)} -attr vt d
+load net {ACC1:acc#153.itm(2)} -attr vt d
+load net {ACC1:acc#153.itm(3)} -attr vt d
+load net {ACC1:acc#153.itm(4)} -attr vt d
+load net {ACC1:acc#153.itm(5)} -attr vt d
+load net {ACC1:acc#153.itm(6)} -attr vt d
+load net {ACC1:acc#153.itm(7)} -attr vt d
+load net {ACC1:acc#153.itm(8)} -attr vt d
+load net {ACC1:acc#153.itm(9)} -attr vt d
+load net {ACC1:acc#153.itm(10)} -attr vt d
+load netBundle {ACC1:acc#153.itm} 11 {ACC1:acc#153.itm(0)} {ACC1:acc#153.itm(1)} {ACC1:acc#153.itm(2)} {ACC1:acc#153.itm(3)} {ACC1:acc#153.itm(4)} {ACC1:acc#153.itm(5)} {ACC1:acc#153.itm(6)} {ACC1:acc#153.itm(7)} {ACC1:acc#153.itm(8)} {ACC1:acc#153.itm(9)} {ACC1:acc#153.itm(10)} -attr xrf 25433 -attr oid 729 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:not#161.itm(0)} -attr vt d
+load net {ACC1:not#161.itm(1)} -attr vt d
+load net {ACC1:not#161.itm(2)} -attr vt d
+load net {ACC1:not#161.itm(3)} -attr vt d
+load net {ACC1:not#161.itm(4)} -attr vt d
+load net {ACC1:not#161.itm(5)} -attr vt d
+load net {ACC1:not#161.itm(6)} -attr vt d
+load net {ACC1:not#161.itm(7)} -attr vt d
+load net {ACC1:not#161.itm(8)} -attr vt d
+load net {ACC1:not#161.itm(9)} -attr vt d
+load netBundle {ACC1:not#161.itm} 10 {ACC1:not#161.itm(0)} {ACC1:not#161.itm(1)} {ACC1:not#161.itm(2)} {ACC1:not#161.itm(3)} {ACC1:not#161.itm(4)} {ACC1:not#161.itm(5)} {ACC1:not#161.itm(6)} {ACC1:not#161.itm(7)} {ACC1:not#161.itm(8)} {ACC1:not#161.itm(9)} -attr xrf 25434 -attr oid 730 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {slc(regs.regs(0).sva#1).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#1).itm} 10 {slc(regs.regs(0).sva#1).itm(0)} {slc(regs.regs(0).sva#1).itm(1)} {slc(regs.regs(0).sva#1).itm(2)} {slc(regs.regs(0).sva#1).itm(3)} {slc(regs.regs(0).sva#1).itm(4)} {slc(regs.regs(0).sva#1).itm(5)} {slc(regs.regs(0).sva#1).itm(6)} {slc(regs.regs(0).sva#1).itm(7)} {slc(regs.regs(0).sva#1).itm(8)} {slc(regs.regs(0).sva#1).itm(9)} -attr xrf 25435 -attr oid 731 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {ACC1:not#162.itm(0)} -attr vt d
+load net {ACC1:not#162.itm(1)} -attr vt d
+load net {ACC1:not#162.itm(2)} -attr vt d
+load net {ACC1:not#162.itm(3)} -attr vt d
+load net {ACC1:not#162.itm(4)} -attr vt d
+load net {ACC1:not#162.itm(5)} -attr vt d
+load net {ACC1:not#162.itm(6)} -attr vt d
+load net {ACC1:not#162.itm(7)} -attr vt d
+load net {ACC1:not#162.itm(8)} -attr vt d
+load net {ACC1:not#162.itm(9)} -attr vt d
+load netBundle {ACC1:not#162.itm} 10 {ACC1:not#162.itm(0)} {ACC1:not#162.itm(1)} {ACC1:not#162.itm(2)} {ACC1:not#162.itm(3)} {ACC1:not#162.itm(4)} {ACC1:not#162.itm(5)} {ACC1:not#162.itm(6)} {ACC1:not#162.itm(7)} {ACC1:not#162.itm(8)} {ACC1:not#162.itm(9)} -attr xrf 25436 -attr oid 732 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {slc(regs.regs(0).sva#2).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#2).itm} 10 {slc(regs.regs(0).sva#2).itm(0)} {slc(regs.regs(0).sva#2).itm(1)} {slc(regs.regs(0).sva#2).itm(2)} {slc(regs.regs(0).sva#2).itm(3)} {slc(regs.regs(0).sva#2).itm(4)} {slc(regs.regs(0).sva#2).itm(5)} {slc(regs.regs(0).sva#2).itm(6)} {slc(regs.regs(0).sva#2).itm(7)} {slc(regs.regs(0).sva#2).itm(8)} {slc(regs.regs(0).sva#2).itm(9)} -attr xrf 25437 -attr oid 733 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {ACC1:acc#152.itm(0)} -attr vt d
+load net {ACC1:acc#152.itm(1)} -attr vt d
+load net {ACC1:acc#152.itm(2)} -attr vt d
+load net {ACC1:acc#152.itm(3)} -attr vt d
+load net {ACC1:acc#152.itm(4)} -attr vt d
+load net {ACC1:acc#152.itm(5)} -attr vt d
+load net {ACC1:acc#152.itm(6)} -attr vt d
+load net {ACC1:acc#152.itm(7)} -attr vt d
+load net {ACC1:acc#152.itm(8)} -attr vt d
+load net {ACC1:acc#152.itm(9)} -attr vt d
+load net {ACC1:acc#152.itm(10)} -attr vt d
+load netBundle {ACC1:acc#152.itm} 11 {ACC1:acc#152.itm(0)} {ACC1:acc#152.itm(1)} {ACC1:acc#152.itm(2)} {ACC1:acc#152.itm(3)} {ACC1:acc#152.itm(4)} {ACC1:acc#152.itm(5)} {ACC1:acc#152.itm(6)} {ACC1:acc#152.itm(7)} {ACC1:acc#152.itm(8)} {ACC1:acc#152.itm(9)} {ACC1:acc#152.itm(10)} -attr xrf 25438 -attr oid 734 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:not#163.itm(0)} -attr vt d
+load net {ACC1:not#163.itm(1)} -attr vt d
+load net {ACC1:not#163.itm(2)} -attr vt d
+load net {ACC1:not#163.itm(3)} -attr vt d
+load net {ACC1:not#163.itm(4)} -attr vt d
+load net {ACC1:not#163.itm(5)} -attr vt d
+load net {ACC1:not#163.itm(6)} -attr vt d
+load net {ACC1:not#163.itm(7)} -attr vt d
+load net {ACC1:not#163.itm(8)} -attr vt d
+load net {ACC1:not#163.itm(9)} -attr vt d
+load netBundle {ACC1:not#163.itm} 10 {ACC1:not#163.itm(0)} {ACC1:not#163.itm(1)} {ACC1:not#163.itm(2)} {ACC1:not#163.itm(3)} {ACC1:not#163.itm(4)} {ACC1:not#163.itm(5)} {ACC1:not#163.itm(6)} {ACC1:not#163.itm(7)} {ACC1:not#163.itm(8)} {ACC1:not#163.itm(9)} -attr xrf 25439 -attr oid 735 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {slc(regs.regs(0).sva#3).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#3).itm} 10 {slc(regs.regs(0).sva#3).itm(0)} {slc(regs.regs(0).sva#3).itm(1)} {slc(regs.regs(0).sva#3).itm(2)} {slc(regs.regs(0).sva#3).itm(3)} {slc(regs.regs(0).sva#3).itm(4)} {slc(regs.regs(0).sva#3).itm(5)} {slc(regs.regs(0).sva#3).itm(6)} {slc(regs.regs(0).sva#3).itm(7)} {slc(regs.regs(0).sva#3).itm(8)} {slc(regs.regs(0).sva#3).itm(9)} -attr xrf 25440 -attr oid 736 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {ACC1:acc#161.itm(0)} -attr vt d
+load net {ACC1:acc#161.itm(1)} -attr vt d
+load net {ACC1:acc#161.itm(2)} -attr vt d
+load netBundle {ACC1:acc#161.itm} 3 {ACC1:acc#161.itm(0)} {ACC1:acc#161.itm(1)} {ACC1:acc#161.itm(2)} -attr xrf 25441 -attr oid 737 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load net {conc#708.itm(0)} -attr vt d
+load net {conc#708.itm(1)} -attr vt d
+load net {conc#708.itm(2)} -attr vt d
+load netBundle {conc#708.itm} 3 {conc#708.itm(0)} {conc#708.itm(1)} {conc#708.itm(2)} -attr xrf 25442 -attr oid 738 -attr vt d -attr @path {/sobel/sobel:core/conc#708.itm}
+load net {ACC1:conc#495.itm(0)} -attr vt d
+load net {ACC1:conc#495.itm(1)} -attr vt d
+load netBundle {ACC1:conc#495.itm} 2 {ACC1:conc#495.itm(0)} {ACC1:conc#495.itm(1)} -attr xrf 25443 -attr oid 739 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#495.itm}
+load net {ACC1:acc#160.itm(0)} -attr vt d
+load net {ACC1:acc#160.itm(1)} -attr vt d
+load net {ACC1:acc#160.itm(2)} -attr vt d
+load net {ACC1:acc#160.itm(3)} -attr vt d
+load netBundle {ACC1:acc#160.itm} 4 {ACC1:acc#160.itm(0)} {ACC1:acc#160.itm(1)} {ACC1:acc#160.itm(2)} {ACC1:acc#160.itm(3)} -attr xrf 25444 -attr oid 740 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load net {conc#709.itm(0)} -attr vt d
+load net {conc#709.itm(1)} -attr vt d
+load net {conc#709.itm(2)} -attr vt d
+load netBundle {conc#709.itm} 3 {conc#709.itm(0)} {conc#709.itm(1)} {conc#709.itm(2)} -attr xrf 25445 -attr oid 741 -attr vt d -attr @path {/sobel/sobel:core/conc#709.itm}
+load net {ACC1-1:not#149.itm(0)} -attr vt d
+load net {ACC1-1:not#149.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#149.itm} 2 {ACC1-1:not#149.itm(0)} {ACC1-1:not#149.itm(1)} -attr xrf 25446 -attr oid 742 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#149.itm}
+load net {slc(ACC1:acc#120.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#120.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#120.psp#1.sva).itm} 2 {slc(ACC1:acc#120.psp#1.sva).itm(0)} {slc(ACC1:acc#120.psp#1.sva).itm(1)} -attr xrf 25447 -attr oid 743 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp#1.sva).itm}
+load net {conc#710.itm(0)} -attr vt d
+load net {conc#710.itm(1)} -attr vt d
+load netBundle {conc#710.itm} 2 {conc#710.itm(0)} {conc#710.itm(1)} -attr xrf 25448 -attr oid 744 -attr vt d -attr @path {/sobel/sobel:core/conc#710.itm}
+load net {ACC1:slc#26.itm(0)} -attr vt d
+load net {ACC1:slc#26.itm(1)} -attr vt d
+load net {ACC1:slc#26.itm(2)} -attr vt d
+load net {ACC1:slc#26.itm(3)} -attr vt d
+load netBundle {ACC1:slc#26.itm} 4 {ACC1:slc#26.itm(0)} {ACC1:slc#26.itm(1)} {ACC1:slc#26.itm(2)} {ACC1:slc#26.itm(3)} -attr xrf 25449 -attr oid 745 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#158.itm(0)} -attr vt d
+load net {ACC1:acc#158.itm(1)} -attr vt d
+load net {ACC1:acc#158.itm(2)} -attr vt d
+load net {ACC1:acc#158.itm(3)} -attr vt d
+load net {ACC1:acc#158.itm(4)} -attr vt d
+load netBundle {ACC1:acc#158.itm} 5 {ACC1:acc#158.itm(0)} {ACC1:acc#158.itm(1)} {ACC1:acc#158.itm(2)} {ACC1:acc#158.itm(3)} {ACC1:acc#158.itm(4)} -attr xrf 25450 -attr oid 746 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {conc#711.itm(0)} -attr vt d
+load net {conc#711.itm(1)} -attr vt d
+load net {conc#711.itm(2)} -attr vt d
+load net {conc#711.itm(3)} -attr vt d
+load netBundle {conc#711.itm} 4 {conc#711.itm(0)} {conc#711.itm(1)} {conc#711.itm(2)} {conc#711.itm(3)} -attr xrf 25451 -attr oid 747 -attr vt d -attr @path {/sobel/sobel:core/conc#711.itm}
+load net {ACC1:slc#24.itm(0)} -attr vt d
+load net {ACC1:slc#24.itm(1)} -attr vt d
+load net {ACC1:slc#24.itm(2)} -attr vt d
+load netBundle {ACC1:slc#24.itm} 3 {ACC1:slc#24.itm(0)} {ACC1:slc#24.itm(1)} {ACC1:slc#24.itm(2)} -attr xrf 25452 -attr oid 748 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#24.itm}
+load net {ACC1:acc#156.itm(0)} -attr vt d
+load net {ACC1:acc#156.itm(1)} -attr vt d
+load net {ACC1:acc#156.itm(2)} -attr vt d
+load net {ACC1:acc#156.itm(3)} -attr vt d
+load netBundle {ACC1:acc#156.itm} 4 {ACC1:acc#156.itm(0)} {ACC1:acc#156.itm(1)} {ACC1:acc#156.itm(2)} {ACC1:acc#156.itm(3)} -attr xrf 25453 -attr oid 749 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load net {conc#712.itm(0)} -attr vt d
+load net {conc#712.itm(1)} -attr vt d
+load netBundle {conc#712.itm} 2 {conc#712.itm(0)} {conc#712.itm(1)} -attr xrf 25454 -attr oid 750 -attr vt d -attr @path {/sobel/sobel:core/conc#712.itm}
+load net {ACC1:conc#484.itm(0)} -attr vt d
+load net {ACC1:conc#484.itm(1)} -attr vt d
+load netBundle {ACC1:conc#484.itm} 2 {ACC1:conc#484.itm(0)} {ACC1:conc#484.itm(1)} -attr xrf 25455 -attr oid 751 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#484.itm}
+load net {conc#713.itm(0)} -attr vt d
+load net {conc#713.itm(1)} -attr vt d
+load net {conc#713.itm(2)} -attr vt d
+load net {conc#713.itm(3)} -attr vt d
+load netBundle {conc#713.itm} 4 {conc#713.itm(0)} {conc#713.itm(1)} {conc#713.itm(2)} {conc#713.itm(3)} -attr xrf 25456 -attr oid 752 -attr vt d -attr @path {/sobel/sobel:core/conc#713.itm}
+load net {ACC1:slc#25.itm(0)} -attr vt d
+load net {ACC1:slc#25.itm(1)} -attr vt d
+load net {ACC1:slc#25.itm(2)} -attr vt d
+load netBundle {ACC1:slc#25.itm} 3 {ACC1:slc#25.itm(0)} {ACC1:slc#25.itm(1)} {ACC1:slc#25.itm(2)} -attr xrf 25457 -attr oid 753 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#25.itm}
+load net {ACC1:acc#157.itm(0)} -attr vt d
+load net {ACC1:acc#157.itm(1)} -attr vt d
+load net {ACC1:acc#157.itm(2)} -attr vt d
+load net {ACC1:acc#157.itm(3)} -attr vt d
+load netBundle {ACC1:acc#157.itm} 4 {ACC1:acc#157.itm(0)} {ACC1:acc#157.itm(1)} {ACC1:acc#157.itm(2)} {ACC1:acc#157.itm(3)} -attr xrf 25458 -attr oid 754 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load net {conc#714.itm(0)} -attr vt d
+load net {conc#714.itm(1)} -attr vt d
+load net {conc#714.itm(2)} -attr vt d
+load netBundle {conc#714.itm} 3 {conc#714.itm(0)} {conc#714.itm(1)} {conc#714.itm(2)} -attr xrf 25459 -attr oid 755 -attr vt d -attr @path {/sobel/sobel:core/conc#714.itm}
+load net {ACC1:slc#23.itm(0)} -attr vt d
+load net {ACC1:slc#23.itm(1)} -attr vt d
+load netBundle {ACC1:slc#23.itm} 2 {ACC1:slc#23.itm(0)} {ACC1:slc#23.itm(1)} -attr xrf 25460 -attr oid 756 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#23.itm}
+load net {ACC1:acc#155.itm(0)} -attr vt d
+load net {ACC1:acc#155.itm(1)} -attr vt d
+load net {ACC1:acc#155.itm(2)} -attr vt d
+load netBundle {ACC1:acc#155.itm} 3 {ACC1:acc#155.itm(0)} {ACC1:acc#155.itm(1)} {ACC1:acc#155.itm(2)} -attr xrf 25461 -attr oid 757 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#155.itm}
+load net {conc#715.itm(0)} -attr vt d
+load net {conc#715.itm(1)} -attr vt d
+load netBundle {conc#715.itm} 2 {conc#715.itm(0)} {conc#715.itm(1)} -attr xrf 25462 -attr oid 758 -attr vt d -attr @path {/sobel/sobel:core/conc#715.itm}
+load net {ACC1:conc#482.itm(0)} -attr vt d
+load net {ACC1:conc#482.itm(1)} -attr vt d
+load netBundle {ACC1:conc#482.itm} 2 {ACC1:conc#482.itm(0)} {ACC1:conc#482.itm(1)} -attr xrf 25463 -attr oid 759 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#482.itm}
+load net {ACC1:conc#486.itm(0)} -attr vt d
+load net {ACC1:conc#486.itm(1)} -attr vt d
+load net {ACC1:conc#486.itm(2)} -attr vt d
+load netBundle {ACC1:conc#486.itm} 3 {ACC1:conc#486.itm(0)} {ACC1:conc#486.itm(1)} {ACC1:conc#486.itm(2)} -attr xrf 25464 -attr oid 760 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#486.itm}
+load net {ACC1:slc#22.itm(0)} -attr vt d
+load net {ACC1:slc#22.itm(1)} -attr vt d
+load netBundle {ACC1:slc#22.itm} 2 {ACC1:slc#22.itm(0)} {ACC1:slc#22.itm(1)} -attr xrf 25465 -attr oid 761 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#22.itm}
+load net {ACC1:acc#154.itm(0)} -attr vt d
+load net {ACC1:acc#154.itm(1)} -attr vt d
+load net {ACC1:acc#154.itm(2)} -attr vt d
+load netBundle {ACC1:acc#154.itm} 3 {ACC1:acc#154.itm(0)} {ACC1:acc#154.itm(1)} {ACC1:acc#154.itm(2)} -attr xrf 25466 -attr oid 762 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154.itm}
+load net {conc#716.itm(0)} -attr vt d
+load net {conc#716.itm(1)} -attr vt d
+load netBundle {conc#716.itm} 2 {conc#716.itm(0)} {conc#716.itm(1)} -attr xrf 25467 -attr oid 763 -attr vt d -attr @path {/sobel/sobel:core/conc#716.itm}
+load net {ACC1:conc#480.itm(0)} -attr vt d
+load net {ACC1:conc#480.itm(1)} -attr vt d
+load netBundle {ACC1:conc#480.itm} 2 {ACC1:conc#480.itm(0)} {ACC1:conc#480.itm(1)} -attr xrf 25468 -attr oid 764 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#480.itm}
+load net {ACC1:slc#27.itm(0)} -attr vt d
+load net {ACC1:slc#27.itm(1)} -attr vt d
+load netBundle {ACC1:slc#27.itm} 2 {ACC1:slc#27.itm(0)} {ACC1:slc#27.itm(1)} -attr xrf 25469 -attr oid 765 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#27.itm}
+load net {ACC1:acc#159.itm(0)} -attr vt d
+load net {ACC1:acc#159.itm(1)} -attr vt d
+load net {ACC1:acc#159.itm(2)} -attr vt d
+load netBundle {ACC1:acc#159.itm} 3 {ACC1:acc#159.itm(0)} {ACC1:acc#159.itm(1)} {ACC1:acc#159.itm(2)} -attr xrf 25470 -attr oid 766 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#159.itm}
+load net {conc#717.itm(0)} -attr vt d
+load net {conc#717.itm(1)} -attr vt d
+load netBundle {conc#717.itm} 2 {conc#717.itm(0)} {conc#717.itm(1)} -attr xrf 25471 -attr oid 767 -attr vt d -attr @path {/sobel/sobel:core/conc#717.itm}
+load net {ACC1:conc#490.itm(0)} -attr vt d
+load net {ACC1:conc#490.itm(1)} -attr vt d
+load netBundle {ACC1:conc#490.itm} 2 {ACC1:conc#490.itm(0)} {ACC1:conc#490.itm(1)} -attr xrf 25472 -attr oid 768 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#490.itm}
+load net {ACC1:exs#850.itm(0)} -attr vt d
+load net {ACC1:exs#850.itm(1)} -attr vt d
+load netBundle {ACC1:exs#850.itm} 2 {ACC1:exs#850.itm(0)} {ACC1:exs#850.itm(1)} -attr xrf 25473 -attr oid 769 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#850.itm}
+load net {ACC1:exs#827.itm(0)} -attr vt d
+load net {ACC1:exs#827.itm(1)} -attr vt d
+load netBundle {ACC1:exs#827.itm} 2 {ACC1:exs#827.itm(0)} {ACC1:exs#827.itm(1)} -attr xrf 25474 -attr oid 770 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#827.itm}
+load net {ACC1:acc#187.itm(0)} -attr vt d
+load net {ACC1:acc#187.itm(1)} -attr vt d
+load net {ACC1:acc#187.itm(2)} -attr vt d
+load net {ACC1:acc#187.itm(3)} -attr vt d
+load netBundle {ACC1:acc#187.itm} 4 {ACC1:acc#187.itm(0)} {ACC1:acc#187.itm(1)} {ACC1:acc#187.itm(2)} {ACC1:acc#187.itm(3)} -attr xrf 25475 -attr oid 771 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load net {conc#718.itm(0)} -attr vt d
+load net {conc#718.itm(1)} -attr vt d
+load net {conc#718.itm(2)} -attr vt d
+load netBundle {conc#718.itm} 3 {conc#718.itm(0)} {conc#718.itm(1)} {conc#718.itm(2)} -attr xrf 25476 -attr oid 772 -attr vt d -attr @path {/sobel/sobel:core/conc#718.itm}
+load net {ACC1-3:not#149.itm(0)} -attr vt d
+load net {ACC1-3:not#149.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#149.itm} 2 {ACC1-3:not#149.itm(0)} {ACC1-3:not#149.itm(1)} -attr xrf 25477 -attr oid 773 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#149.itm}
+load net {slc(ACC1:acc#120.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#120.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#120.psp.sva).itm} 2 {slc(ACC1:acc#120.psp.sva).itm(0)} {slc(ACC1:acc#120.psp.sva).itm(1)} -attr xrf 25478 -attr oid 774 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp.sva).itm}
+load net {conc#719.itm(0)} -attr vt d
+load net {conc#719.itm(1)} -attr vt d
+load netBundle {conc#719.itm} 2 {conc#719.itm(0)} {conc#719.itm(1)} -attr xrf 25479 -attr oid 775 -attr vt d -attr @path {/sobel/sobel:core/conc#719.itm}
+load net {ACC1:acc#162.itm(0)} -attr vt d
+load net {ACC1:acc#162.itm(1)} -attr vt d
+load net {ACC1:acc#162.itm(2)} -attr vt d
+load net {ACC1:acc#162.itm(3)} -attr vt d
+load net {ACC1:acc#162.itm(4)} -attr vt d
+load net {ACC1:acc#162.itm(5)} -attr vt d
+load net {ACC1:acc#162.itm(6)} -attr vt d
+load net {ACC1:acc#162.itm(7)} -attr vt d
+load net {ACC1:acc#162.itm(8)} -attr vt d
+load net {ACC1:acc#162.itm(9)} -attr vt d
+load net {ACC1:acc#162.itm(10)} -attr vt d
+load netBundle {ACC1:acc#162.itm} 11 {ACC1:acc#162.itm(0)} {ACC1:acc#162.itm(1)} {ACC1:acc#162.itm(2)} {ACC1:acc#162.itm(3)} {ACC1:acc#162.itm(4)} {ACC1:acc#162.itm(5)} {ACC1:acc#162.itm(6)} {ACC1:acc#162.itm(7)} {ACC1:acc#162.itm(8)} {ACC1:acc#162.itm(9)} {ACC1:acc#162.itm(10)} -attr xrf 25480 -attr oid 776 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {slc(regs.regs(1).sva)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#8.itm} 10 {slc(regs.regs(1).sva)#8.itm(0)} {slc(regs.regs(1).sva)#8.itm(1)} {slc(regs.regs(1).sva)#8.itm(2)} {slc(regs.regs(1).sva)#8.itm(3)} {slc(regs.regs(1).sva)#8.itm(4)} {slc(regs.regs(1).sva)#8.itm(5)} {slc(regs.regs(1).sva)#8.itm(6)} {slc(regs.regs(1).sva)#8.itm(7)} {slc(regs.regs(1).sva)#8.itm(8)} {slc(regs.regs(1).sva)#8.itm(9)} -attr xrf 25481 -attr oid 777 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {slc(regs.regs(1).sva)#9.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#9.itm} 10 {slc(regs.regs(1).sva)#9.itm(0)} {slc(regs.regs(1).sva)#9.itm(1)} {slc(regs.regs(1).sva)#9.itm(2)} {slc(regs.regs(1).sva)#9.itm(3)} {slc(regs.regs(1).sva)#9.itm(4)} {slc(regs.regs(1).sva)#9.itm(5)} {slc(regs.regs(1).sva)#9.itm(6)} {slc(regs.regs(1).sva)#9.itm(7)} {slc(regs.regs(1).sva)#9.itm(8)} {slc(regs.regs(1).sva)#9.itm(9)} -attr xrf 25482 -attr oid 778 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {slc(regs.regs(1).sva)#10.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#10.itm} 10 {slc(regs.regs(1).sva)#10.itm(0)} {slc(regs.regs(1).sva)#10.itm(1)} {slc(regs.regs(1).sva)#10.itm(2)} {slc(regs.regs(1).sva)#10.itm(3)} {slc(regs.regs(1).sva)#10.itm(4)} {slc(regs.regs(1).sva)#10.itm(5)} {slc(regs.regs(1).sva)#10.itm(6)} {slc(regs.regs(1).sva)#10.itm(7)} {slc(regs.regs(1).sva)#10.itm(8)} {slc(regs.regs(1).sva)#10.itm(9)} -attr xrf 25483 -attr oid 779 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {ACC1:slc#34.itm(0)} -attr vt d
+load net {ACC1:slc#34.itm(1)} -attr vt d
+load net {ACC1:slc#34.itm(2)} -attr vt d
+load net {ACC1:slc#34.itm(3)} -attr vt d
+load netBundle {ACC1:slc#34.itm} 4 {ACC1:slc#34.itm(0)} {ACC1:slc#34.itm(1)} {ACC1:slc#34.itm(2)} {ACC1:slc#34.itm(3)} -attr xrf 25484 -attr oid 780 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#167.itm(0)} -attr vt d
+load net {ACC1:acc#167.itm(1)} -attr vt d
+load net {ACC1:acc#167.itm(2)} -attr vt d
+load net {ACC1:acc#167.itm(3)} -attr vt d
+load net {ACC1:acc#167.itm(4)} -attr vt d
+load netBundle {ACC1:acc#167.itm} 5 {ACC1:acc#167.itm(0)} {ACC1:acc#167.itm(1)} {ACC1:acc#167.itm(2)} {ACC1:acc#167.itm(3)} {ACC1:acc#167.itm(4)} -attr xrf 25485 -attr oid 781 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load net {conc#720.itm(0)} -attr vt d
+load net {conc#720.itm(1)} -attr vt d
+load net {conc#720.itm(2)} -attr vt d
+load net {conc#720.itm(3)} -attr vt d
+load netBundle {conc#720.itm} 4 {conc#720.itm(0)} {conc#720.itm(1)} {conc#720.itm(2)} {conc#720.itm(3)} -attr xrf 25486 -attr oid 782 -attr vt d -attr @path {/sobel/sobel:core/conc#720.itm}
+load net {ACC1:slc#32.itm(0)} -attr vt d
+load net {ACC1:slc#32.itm(1)} -attr vt d
+load net {ACC1:slc#32.itm(2)} -attr vt d
+load netBundle {ACC1:slc#32.itm} 3 {ACC1:slc#32.itm(0)} {ACC1:slc#32.itm(1)} {ACC1:slc#32.itm(2)} -attr xrf 25487 -attr oid 783 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#32.itm}
+load net {ACC1:acc#165.itm(0)} -attr vt d
+load net {ACC1:acc#165.itm(1)} -attr vt d
+load net {ACC1:acc#165.itm(2)} -attr vt d
+load net {ACC1:acc#165.itm(3)} -attr vt d
+load netBundle {ACC1:acc#165.itm} 4 {ACC1:acc#165.itm(0)} {ACC1:acc#165.itm(1)} {ACC1:acc#165.itm(2)} {ACC1:acc#165.itm(3)} -attr xrf 25488 -attr oid 784 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {conc#721.itm(0)} -attr vt d
+load net {conc#721.itm(1)} -attr vt d
+load netBundle {conc#721.itm} 2 {conc#721.itm(0)} {conc#721.itm(1)} -attr xrf 25489 -attr oid 785 -attr vt d -attr @path {/sobel/sobel:core/conc#721.itm}
+load net {ACC1:conc#502.itm(0)} -attr vt d
+load net {ACC1:conc#502.itm(1)} -attr vt d
+load netBundle {ACC1:conc#502.itm} 2 {ACC1:conc#502.itm(0)} {ACC1:conc#502.itm(1)} -attr xrf 25490 -attr oid 786 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#502.itm}
+load net {conc#722.itm(0)} -attr vt d
+load net {conc#722.itm(1)} -attr vt d
+load net {conc#722.itm(2)} -attr vt d
+load net {conc#722.itm(3)} -attr vt d
+load netBundle {conc#722.itm} 4 {conc#722.itm(0)} {conc#722.itm(1)} {conc#722.itm(2)} {conc#722.itm(3)} -attr xrf 25491 -attr oid 787 -attr vt d -attr @path {/sobel/sobel:core/conc#722.itm}
+load net {ACC1:slc#33.itm(0)} -attr vt d
+load net {ACC1:slc#33.itm(1)} -attr vt d
+load net {ACC1:slc#33.itm(2)} -attr vt d
+load netBundle {ACC1:slc#33.itm} 3 {ACC1:slc#33.itm(0)} {ACC1:slc#33.itm(1)} {ACC1:slc#33.itm(2)} -attr xrf 25492 -attr oid 788 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#166.itm(0)} -attr vt d
+load net {ACC1:acc#166.itm(1)} -attr vt d
+load net {ACC1:acc#166.itm(2)} -attr vt d
+load net {ACC1:acc#166.itm(3)} -attr vt d
+load netBundle {ACC1:acc#166.itm} 4 {ACC1:acc#166.itm(0)} {ACC1:acc#166.itm(1)} {ACC1:acc#166.itm(2)} {ACC1:acc#166.itm(3)} -attr xrf 25493 -attr oid 789 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load net {conc#723.itm(0)} -attr vt d
+load net {conc#723.itm(1)} -attr vt d
+load net {conc#723.itm(2)} -attr vt d
+load netBundle {conc#723.itm} 3 {conc#723.itm(0)} {conc#723.itm(1)} {conc#723.itm(2)} -attr xrf 25494 -attr oid 790 -attr vt d -attr @path {/sobel/sobel:core/conc#723.itm}
+load net {ACC1:slc#31.itm(0)} -attr vt d
+load net {ACC1:slc#31.itm(1)} -attr vt d
+load netBundle {ACC1:slc#31.itm} 2 {ACC1:slc#31.itm(0)} {ACC1:slc#31.itm(1)} -attr xrf 25495 -attr oid 791 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#31.itm}
+load net {ACC1:acc#164.itm(0)} -attr vt d
+load net {ACC1:acc#164.itm(1)} -attr vt d
+load net {ACC1:acc#164.itm(2)} -attr vt d
+load netBundle {ACC1:acc#164.itm} 3 {ACC1:acc#164.itm(0)} {ACC1:acc#164.itm(1)} {ACC1:acc#164.itm(2)} -attr xrf 25496 -attr oid 792 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164.itm}
+load net {conc#724.itm(0)} -attr vt d
+load net {conc#724.itm(1)} -attr vt d
+load netBundle {conc#724.itm} 2 {conc#724.itm(0)} {conc#724.itm(1)} -attr xrf 25497 -attr oid 793 -attr vt d -attr @path {/sobel/sobel:core/conc#724.itm}
+load net {ACC1:conc#500.itm(0)} -attr vt d
+load net {ACC1:conc#500.itm(1)} -attr vt d
+load netBundle {ACC1:conc#500.itm} 2 {ACC1:conc#500.itm(0)} {ACC1:conc#500.itm(1)} -attr xrf 25498 -attr oid 794 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#500.itm}
+load net {ACC1:conc#504.itm(0)} -attr vt d
+load net {ACC1:conc#504.itm(1)} -attr vt d
+load net {ACC1:conc#504.itm(2)} -attr vt d
+load netBundle {ACC1:conc#504.itm} 3 {ACC1:conc#504.itm(0)} {ACC1:conc#504.itm(1)} {ACC1:conc#504.itm(2)} -attr xrf 25499 -attr oid 795 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#504.itm}
+load net {ACC1:slc#30.itm(0)} -attr vt d
+load net {ACC1:slc#30.itm(1)} -attr vt d
+load netBundle {ACC1:slc#30.itm} 2 {ACC1:slc#30.itm(0)} {ACC1:slc#30.itm(1)} -attr xrf 25500 -attr oid 796 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#30.itm}
+load net {ACC1:acc#163.itm(0)} -attr vt d
+load net {ACC1:acc#163.itm(1)} -attr vt d
+load net {ACC1:acc#163.itm(2)} -attr vt d
+load netBundle {ACC1:acc#163.itm} 3 {ACC1:acc#163.itm(0)} {ACC1:acc#163.itm(1)} {ACC1:acc#163.itm(2)} -attr xrf 25501 -attr oid 797 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163.itm}
+load net {conc#725.itm(0)} -attr vt d
+load net {conc#725.itm(1)} -attr vt d
+load netBundle {conc#725.itm} 2 {conc#725.itm(0)} {conc#725.itm(1)} -attr xrf 25502 -attr oid 798 -attr vt d -attr @path {/sobel/sobel:core/conc#725.itm}
+load net {ACC1:conc#498.itm(0)} -attr vt d
+load net {ACC1:conc#498.itm(1)} -attr vt d
+load netBundle {ACC1:conc#498.itm} 2 {ACC1:conc#498.itm(0)} {ACC1:conc#498.itm(1)} -attr xrf 25503 -attr oid 799 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#498.itm}
+load net {ACC1:slc#35.itm(0)} -attr vt d
+load net {ACC1:slc#35.itm(1)} -attr vt d
+load netBundle {ACC1:slc#35.itm} 2 {ACC1:slc#35.itm(0)} {ACC1:slc#35.itm(1)} -attr xrf 25504 -attr oid 800 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#35.itm}
+load net {ACC1:acc#168.itm(0)} -attr vt d
+load net {ACC1:acc#168.itm(1)} -attr vt d
+load net {ACC1:acc#168.itm(2)} -attr vt d
+load netBundle {ACC1:acc#168.itm} 3 {ACC1:acc#168.itm(0)} {ACC1:acc#168.itm(1)} {ACC1:acc#168.itm(2)} -attr xrf 25505 -attr oid 801 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168.itm}
+load net {conc#726.itm(0)} -attr vt d
+load net {conc#726.itm(1)} -attr vt d
+load netBundle {conc#726.itm} 2 {conc#726.itm(0)} {conc#726.itm(1)} -attr xrf 25506 -attr oid 802 -attr vt d -attr @path {/sobel/sobel:core/conc#726.itm}
+load net {ACC1:conc#508.itm(0)} -attr vt d
+load net {ACC1:conc#508.itm(1)} -attr vt d
+load netBundle {ACC1:conc#508.itm} 2 {ACC1:conc#508.itm(0)} {ACC1:conc#508.itm(1)} -attr xrf 25507 -attr oid 803 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#508.itm}
+load net {ACC1-3:exs#562.itm(0)} -attr vt d
+load net {ACC1-3:exs#562.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#562.itm} 2 {ACC1-3:exs#562.itm(0)} {ACC1-3:exs#562.itm(1)} -attr xrf 25508 -attr oid 804 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#562.itm}
+load net {ACC1-3:exs#551.itm(0)} -attr vt d
+load net {ACC1-3:exs#551.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#551.itm} 2 {ACC1-3:exs#551.itm(0)} {ACC1-3:exs#551.itm(1)} -attr xrf 25509 -attr oid 805 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#551.itm}
+load net {ACC1:acc#170.itm(0)} -attr vt d
+load net {ACC1:acc#170.itm(1)} -attr vt d
+load net {ACC1:acc#170.itm(2)} -attr vt d
+load netBundle {ACC1:acc#170.itm} 3 {ACC1:acc#170.itm(0)} {ACC1:acc#170.itm(1)} {ACC1:acc#170.itm(2)} -attr xrf 25510 -attr oid 806 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170.itm}
+load net {conc#727.itm(0)} -attr vt d
+load net {conc#727.itm(1)} -attr vt d
+load net {conc#727.itm(2)} -attr vt d
+load netBundle {conc#727.itm} 3 {conc#727.itm(0)} {conc#727.itm(1)} {conc#727.itm(2)} -attr xrf 25511 -attr oid 807 -attr vt d -attr @path {/sobel/sobel:core/conc#727.itm}
+load net {ACC1:conc#513.itm(0)} -attr vt d
+load net {ACC1:conc#513.itm(1)} -attr vt d
+load netBundle {ACC1:conc#513.itm} 2 {ACC1:conc#513.itm(0)} {ACC1:conc#513.itm(1)} -attr xrf 25512 -attr oid 808 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#513.itm}
+load net {ACC1:acc#133.itm(0)} -attr vt d
+load net {ACC1:acc#133.itm(1)} -attr vt d
+load net {ACC1:acc#133.itm(2)} -attr vt d
+load net {ACC1:acc#133.itm(3)} -attr vt d
+load net {ACC1:acc#133.itm(4)} -attr vt d
+load net {ACC1:acc#133.itm(5)} -attr vt d
+load net {ACC1:acc#133.itm(6)} -attr vt d
+load net {ACC1:acc#133.itm(7)} -attr vt d
+load net {ACC1:acc#133.itm(8)} -attr vt d
+load net {ACC1:acc#133.itm(9)} -attr vt d
+load net {ACC1:acc#133.itm(10)} -attr vt d
+load netBundle {ACC1:acc#133.itm} 11 {ACC1:acc#133.itm(0)} {ACC1:acc#133.itm(1)} {ACC1:acc#133.itm(2)} {ACC1:acc#133.itm(3)} {ACC1:acc#133.itm(4)} {ACC1:acc#133.itm(5)} {ACC1:acc#133.itm(6)} {ACC1:acc#133.itm(7)} {ACC1:acc#133.itm(8)} {ACC1:acc#133.itm(9)} {ACC1:acc#133.itm(10)} -attr xrf 25513 -attr oid 809 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:not.itm(0)} -attr vt d
+load net {ACC1:not.itm(1)} -attr vt d
+load net {ACC1:not.itm(2)} -attr vt d
+load net {ACC1:not.itm(3)} -attr vt d
+load net {ACC1:not.itm(4)} -attr vt d
+load net {ACC1:not.itm(5)} -attr vt d
+load net {ACC1:not.itm(6)} -attr vt d
+load net {ACC1:not.itm(7)} -attr vt d
+load net {ACC1:not.itm(8)} -attr vt d
+load net {ACC1:not.itm(9)} -attr vt d
+load netBundle {ACC1:not.itm} 10 {ACC1:not.itm(0)} {ACC1:not.itm(1)} {ACC1:not.itm(2)} {ACC1:not.itm(3)} {ACC1:not.itm(4)} {ACC1:not.itm(5)} {ACC1:not.itm(6)} {ACC1:not.itm(7)} {ACC1:not.itm(8)} {ACC1:not.itm(9)} -attr xrf 25514 -attr oid 810 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {slc(regs.regs(0).sva#7).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#7).itm} 10 {slc(regs.regs(0).sva#7).itm(0)} {slc(regs.regs(0).sva#7).itm(1)} {slc(regs.regs(0).sva#7).itm(2)} {slc(regs.regs(0).sva#7).itm(3)} {slc(regs.regs(0).sva#7).itm(4)} {slc(regs.regs(0).sva#7).itm(5)} {slc(regs.regs(0).sva#7).itm(6)} {slc(regs.regs(0).sva#7).itm(7)} {slc(regs.regs(0).sva#7).itm(8)} {slc(regs.regs(0).sva#7).itm(9)} -attr xrf 25515 -attr oid 811 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {ACC1:not#156.itm(0)} -attr vt d
+load net {ACC1:not#156.itm(1)} -attr vt d
+load net {ACC1:not#156.itm(2)} -attr vt d
+load net {ACC1:not#156.itm(3)} -attr vt d
+load net {ACC1:not#156.itm(4)} -attr vt d
+load net {ACC1:not#156.itm(5)} -attr vt d
+load net {ACC1:not#156.itm(6)} -attr vt d
+load net {ACC1:not#156.itm(7)} -attr vt d
+load net {ACC1:not#156.itm(8)} -attr vt d
+load net {ACC1:not#156.itm(9)} -attr vt d
+load netBundle {ACC1:not#156.itm} 10 {ACC1:not#156.itm(0)} {ACC1:not#156.itm(1)} {ACC1:not#156.itm(2)} {ACC1:not#156.itm(3)} {ACC1:not#156.itm(4)} {ACC1:not#156.itm(5)} {ACC1:not#156.itm(6)} {ACC1:not#156.itm(7)} {ACC1:not#156.itm(8)} {ACC1:not#156.itm(9)} -attr xrf 25516 -attr oid 812 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {slc(regs.regs(0).sva#8).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#8).itm} 10 {slc(regs.regs(0).sva#8).itm(0)} {slc(regs.regs(0).sva#8).itm(1)} {slc(regs.regs(0).sva#8).itm(2)} {slc(regs.regs(0).sva#8).itm(3)} {slc(regs.regs(0).sva#8).itm(4)} {slc(regs.regs(0).sva#8).itm(5)} {slc(regs.regs(0).sva#8).itm(6)} {slc(regs.regs(0).sva#8).itm(7)} {slc(regs.regs(0).sva#8).itm(8)} {slc(regs.regs(0).sva#8).itm(9)} -attr xrf 25517 -attr oid 813 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {ACC1:acc#132.itm(0)} -attr vt d
+load net {ACC1:acc#132.itm(1)} -attr vt d
+load net {ACC1:acc#132.itm(2)} -attr vt d
+load net {ACC1:acc#132.itm(3)} -attr vt d
+load net {ACC1:acc#132.itm(4)} -attr vt d
+load net {ACC1:acc#132.itm(5)} -attr vt d
+load net {ACC1:acc#132.itm(6)} -attr vt d
+load net {ACC1:acc#132.itm(7)} -attr vt d
+load net {ACC1:acc#132.itm(8)} -attr vt d
+load net {ACC1:acc#132.itm(9)} -attr vt d
+load net {ACC1:acc#132.itm(10)} -attr vt d
+load netBundle {ACC1:acc#132.itm} 11 {ACC1:acc#132.itm(0)} {ACC1:acc#132.itm(1)} {ACC1:acc#132.itm(2)} {ACC1:acc#132.itm(3)} {ACC1:acc#132.itm(4)} {ACC1:acc#132.itm(5)} {ACC1:acc#132.itm(6)} {ACC1:acc#132.itm(7)} {ACC1:acc#132.itm(8)} {ACC1:acc#132.itm(9)} {ACC1:acc#132.itm(10)} -attr xrf 25518 -attr oid 814 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:not#157.itm(0)} -attr vt d
+load net {ACC1:not#157.itm(1)} -attr vt d
+load net {ACC1:not#157.itm(2)} -attr vt d
+load net {ACC1:not#157.itm(3)} -attr vt d
+load net {ACC1:not#157.itm(4)} -attr vt d
+load net {ACC1:not#157.itm(5)} -attr vt d
+load net {ACC1:not#157.itm(6)} -attr vt d
+load net {ACC1:not#157.itm(7)} -attr vt d
+load net {ACC1:not#157.itm(8)} -attr vt d
+load net {ACC1:not#157.itm(9)} -attr vt d
+load netBundle {ACC1:not#157.itm} 10 {ACC1:not#157.itm(0)} {ACC1:not#157.itm(1)} {ACC1:not#157.itm(2)} {ACC1:not#157.itm(3)} {ACC1:not#157.itm(4)} {ACC1:not#157.itm(5)} {ACC1:not#157.itm(6)} {ACC1:not#157.itm(7)} {ACC1:not#157.itm(8)} {ACC1:not#157.itm(9)} -attr xrf 25519 -attr oid 815 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {slc(regs.regs(0).sva#9).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#9).itm} 10 {slc(regs.regs(0).sva#9).itm(0)} {slc(regs.regs(0).sva#9).itm(1)} {slc(regs.regs(0).sva#9).itm(2)} {slc(regs.regs(0).sva#9).itm(3)} {slc(regs.regs(0).sva#9).itm(4)} {slc(regs.regs(0).sva#9).itm(5)} {slc(regs.regs(0).sva#9).itm(6)} {slc(regs.regs(0).sva#9).itm(7)} {slc(regs.regs(0).sva#9).itm(8)} {slc(regs.regs(0).sva#9).itm(9)} -attr xrf 25520 -attr oid 816 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {ACC1:acc#141.itm(0)} -attr vt d
+load net {ACC1:acc#141.itm(1)} -attr vt d
+load net {ACC1:acc#141.itm(2)} -attr vt d
+load netBundle {ACC1:acc#141.itm} 3 {ACC1:acc#141.itm(0)} {ACC1:acc#141.itm(1)} {ACC1:acc#141.itm(2)} -attr xrf 25521 -attr oid 817 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141.itm}
+load net {conc#728.itm(0)} -attr vt d
+load net {conc#728.itm(1)} -attr vt d
+load net {conc#728.itm(2)} -attr vt d
+load netBundle {conc#728.itm} 3 {conc#728.itm(0)} {conc#728.itm(1)} {conc#728.itm(2)} -attr xrf 25522 -attr oid 818 -attr vt d -attr @path {/sobel/sobel:core/conc#728.itm}
+load net {ACC1:conc#459.itm(0)} -attr vt d
+load net {ACC1:conc#459.itm(1)} -attr vt d
+load netBundle {ACC1:conc#459.itm} 2 {ACC1:conc#459.itm(0)} {ACC1:conc#459.itm(1)} -attr xrf 25523 -attr oid 819 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#459.itm}
+load net {ACC1:acc#140.itm(0)} -attr vt d
+load net {ACC1:acc#140.itm(1)} -attr vt d
+load net {ACC1:acc#140.itm(2)} -attr vt d
+load net {ACC1:acc#140.itm(3)} -attr vt d
+load netBundle {ACC1:acc#140.itm} 4 {ACC1:acc#140.itm(0)} {ACC1:acc#140.itm(1)} {ACC1:acc#140.itm(2)} {ACC1:acc#140.itm(3)} -attr xrf 25524 -attr oid 820 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load net {conc#729.itm(0)} -attr vt d
+load net {conc#729.itm(1)} -attr vt d
+load net {conc#729.itm(2)} -attr vt d
+load netBundle {conc#729.itm} 3 {conc#729.itm(0)} {conc#729.itm(1)} {conc#729.itm(2)} -attr xrf 25525 -attr oid 821 -attr vt d -attr @path {/sobel/sobel:core/conc#729.itm}
+load net {ACC1-1:not#145.itm(0)} -attr vt d
+load net {ACC1-1:not#145.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#145.itm} 2 {ACC1-1:not#145.itm(0)} {ACC1-1:not#145.itm(1)} -attr xrf 25526 -attr oid 822 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#145.itm}
+load net {slc(ACC1:acc#116.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#116.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#116.psp#1.sva).itm} 2 {slc(ACC1:acc#116.psp#1.sva).itm(0)} {slc(ACC1:acc#116.psp#1.sva).itm(1)} -attr xrf 25527 -attr oid 823 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp#1.sva).itm}
+load net {conc#730.itm(0)} -attr vt d
+load net {conc#730.itm(1)} -attr vt d
+load netBundle {conc#730.itm} 2 {conc#730.itm(0)} {conc#730.itm(1)} -attr xrf 25528 -attr oid 824 -attr vt d -attr @path {/sobel/sobel:core/conc#730.itm}
+load net {ACC1:slc#10.itm(0)} -attr vt d
+load net {ACC1:slc#10.itm(1)} -attr vt d
+load net {ACC1:slc#10.itm(2)} -attr vt d
+load net {ACC1:slc#10.itm(3)} -attr vt d
+load netBundle {ACC1:slc#10.itm} 4 {ACC1:slc#10.itm(0)} {ACC1:slc#10.itm(1)} {ACC1:slc#10.itm(2)} {ACC1:slc#10.itm(3)} -attr xrf 25529 -attr oid 825 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#10.itm}
+load net {ACC1:acc#138.itm(0)} -attr vt d
+load net {ACC1:acc#138.itm(1)} -attr vt d
+load net {ACC1:acc#138.itm(2)} -attr vt d
+load net {ACC1:acc#138.itm(3)} -attr vt d
+load net {ACC1:acc#138.itm(4)} -attr vt d
+load netBundle {ACC1:acc#138.itm} 5 {ACC1:acc#138.itm(0)} {ACC1:acc#138.itm(1)} {ACC1:acc#138.itm(2)} {ACC1:acc#138.itm(3)} {ACC1:acc#138.itm(4)} -attr xrf 25530 -attr oid 826 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {conc#731.itm(0)} -attr vt d
+load net {conc#731.itm(1)} -attr vt d
+load net {conc#731.itm(2)} -attr vt d
+load net {conc#731.itm(3)} -attr vt d
+load netBundle {conc#731.itm} 4 {conc#731.itm(0)} {conc#731.itm(1)} {conc#731.itm(2)} {conc#731.itm(3)} -attr xrf 25531 -attr oid 827 -attr vt d -attr @path {/sobel/sobel:core/conc#731.itm}
+load net {ACC1:slc#8.itm(0)} -attr vt d
+load net {ACC1:slc#8.itm(1)} -attr vt d
+load net {ACC1:slc#8.itm(2)} -attr vt d
+load netBundle {ACC1:slc#8.itm} 3 {ACC1:slc#8.itm(0)} {ACC1:slc#8.itm(1)} {ACC1:slc#8.itm(2)} -attr xrf 25532 -attr oid 828 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#8.itm}
+load net {ACC1:acc#136.itm(0)} -attr vt d
+load net {ACC1:acc#136.itm(1)} -attr vt d
+load net {ACC1:acc#136.itm(2)} -attr vt d
+load net {ACC1:acc#136.itm(3)} -attr vt d
+load netBundle {ACC1:acc#136.itm} 4 {ACC1:acc#136.itm(0)} {ACC1:acc#136.itm(1)} {ACC1:acc#136.itm(2)} {ACC1:acc#136.itm(3)} -attr xrf 25533 -attr oid 829 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load net {conc#732.itm(0)} -attr vt d
+load net {conc#732.itm(1)} -attr vt d
+load netBundle {conc#732.itm} 2 {conc#732.itm(0)} {conc#732.itm(1)} -attr xrf 25534 -attr oid 830 -attr vt d -attr @path {/sobel/sobel:core/conc#732.itm}
+load net {ACC1:conc#448.itm(0)} -attr vt d
+load net {ACC1:conc#448.itm(1)} -attr vt d
+load netBundle {ACC1:conc#448.itm} 2 {ACC1:conc#448.itm(0)} {ACC1:conc#448.itm(1)} -attr xrf 25535 -attr oid 831 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#448.itm}
+load net {conc#733.itm(0)} -attr vt d
+load net {conc#733.itm(1)} -attr vt d
+load net {conc#733.itm(2)} -attr vt d
+load net {conc#733.itm(3)} -attr vt d
+load netBundle {conc#733.itm} 4 {conc#733.itm(0)} {conc#733.itm(1)} {conc#733.itm(2)} {conc#733.itm(3)} -attr xrf 25536 -attr oid 832 -attr vt d -attr @path {/sobel/sobel:core/conc#733.itm}
+load net {ACC1:slc.itm(0)} -attr vt d
+load net {ACC1:slc.itm(1)} -attr vt d
+load net {ACC1:slc.itm(2)} -attr vt d
+load netBundle {ACC1:slc.itm} 3 {ACC1:slc.itm(0)} {ACC1:slc.itm(1)} {ACC1:slc.itm(2)} -attr xrf 25537 -attr oid 833 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#137.itm(0)} -attr vt d
+load net {ACC1:acc#137.itm(1)} -attr vt d
+load net {ACC1:acc#137.itm(2)} -attr vt d
+load net {ACC1:acc#137.itm(3)} -attr vt d
+load netBundle {ACC1:acc#137.itm} 4 {ACC1:acc#137.itm(0)} {ACC1:acc#137.itm(1)} {ACC1:acc#137.itm(2)} {ACC1:acc#137.itm(3)} -attr xrf 25538 -attr oid 834 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load net {conc#734.itm(0)} -attr vt d
+load net {conc#734.itm(1)} -attr vt d
+load net {conc#734.itm(2)} -attr vt d
+load netBundle {conc#734.itm} 3 {conc#734.itm(0)} {conc#734.itm(1)} {conc#734.itm(2)} -attr xrf 25539 -attr oid 835 -attr vt d -attr @path {/sobel/sobel:core/conc#734.itm}
+load net {ACC1:slc#7.itm(0)} -attr vt d
+load net {ACC1:slc#7.itm(1)} -attr vt d
+load netBundle {ACC1:slc#7.itm} 2 {ACC1:slc#7.itm(0)} {ACC1:slc#7.itm(1)} -attr xrf 25540 -attr oid 836 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#135.itm(0)} -attr vt d
+load net {ACC1:acc#135.itm(1)} -attr vt d
+load net {ACC1:acc#135.itm(2)} -attr vt d
+load netBundle {ACC1:acc#135.itm} 3 {ACC1:acc#135.itm(0)} {ACC1:acc#135.itm(1)} {ACC1:acc#135.itm(2)} -attr xrf 25541 -attr oid 837 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135.itm}
+load net {conc#735.itm(0)} -attr vt d
+load net {conc#735.itm(1)} -attr vt d
+load netBundle {conc#735.itm} 2 {conc#735.itm(0)} {conc#735.itm(1)} -attr xrf 25542 -attr oid 838 -attr vt d -attr @path {/sobel/sobel:core/conc#735.itm}
+load net {ACC1:conc#446.itm(0)} -attr vt d
+load net {ACC1:conc#446.itm(1)} -attr vt d
+load netBundle {ACC1:conc#446.itm} 2 {ACC1:conc#446.itm(0)} {ACC1:conc#446.itm(1)} -attr xrf 25543 -attr oid 839 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#446.itm}
+load net {ACC1:conc#450.itm(0)} -attr vt d
+load net {ACC1:conc#450.itm(1)} -attr vt d
+load net {ACC1:conc#450.itm(2)} -attr vt d
+load netBundle {ACC1:conc#450.itm} 3 {ACC1:conc#450.itm(0)} {ACC1:conc#450.itm(1)} {ACC1:conc#450.itm(2)} -attr xrf 25544 -attr oid 840 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#450.itm}
+load net {ACC1:slc#9.itm(0)} -attr vt d
+load net {ACC1:slc#9.itm(1)} -attr vt d
+load netBundle {ACC1:slc#9.itm} 2 {ACC1:slc#9.itm(0)} {ACC1:slc#9.itm(1)} -attr xrf 25545 -attr oid 841 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#9.itm}
+load net {ACC1:acc#134.itm(0)} -attr vt d
+load net {ACC1:acc#134.itm(1)} -attr vt d
+load net {ACC1:acc#134.itm(2)} -attr vt d
+load netBundle {ACC1:acc#134.itm} 3 {ACC1:acc#134.itm(0)} {ACC1:acc#134.itm(1)} {ACC1:acc#134.itm(2)} -attr xrf 25546 -attr oid 842 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134.itm}
+load net {conc#736.itm(0)} -attr vt d
+load net {conc#736.itm(1)} -attr vt d
+load netBundle {conc#736.itm} 2 {conc#736.itm(0)} {conc#736.itm(1)} -attr xrf 25547 -attr oid 843 -attr vt d -attr @path {/sobel/sobel:core/conc#736.itm}
+load net {ACC1:conc#444.itm(0)} -attr vt d
+load net {ACC1:conc#444.itm(1)} -attr vt d
+load netBundle {ACC1:conc#444.itm} 2 {ACC1:conc#444.itm(0)} {ACC1:conc#444.itm(1)} -attr xrf 25548 -attr oid 844 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#444.itm}
+load net {ACC1:slc#11.itm(0)} -attr vt d
+load net {ACC1:slc#11.itm(1)} -attr vt d
+load netBundle {ACC1:slc#11.itm} 2 {ACC1:slc#11.itm(0)} {ACC1:slc#11.itm(1)} -attr xrf 25549 -attr oid 845 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#139.itm(0)} -attr vt d
+load net {ACC1:acc#139.itm(1)} -attr vt d
+load net {ACC1:acc#139.itm(2)} -attr vt d
+load netBundle {ACC1:acc#139.itm} 3 {ACC1:acc#139.itm(0)} {ACC1:acc#139.itm(1)} {ACC1:acc#139.itm(2)} -attr xrf 25550 -attr oid 846 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139.itm}
+load net {conc#737.itm(0)} -attr vt d
+load net {conc#737.itm(1)} -attr vt d
+load netBundle {conc#737.itm} 2 {conc#737.itm(0)} {conc#737.itm(1)} -attr xrf 25551 -attr oid 847 -attr vt d -attr @path {/sobel/sobel:core/conc#737.itm}
+load net {ACC1:conc#454.itm(0)} -attr vt d
+load net {ACC1:conc#454.itm(1)} -attr vt d
+load netBundle {ACC1:conc#454.itm} 2 {ACC1:conc#454.itm(0)} {ACC1:conc#454.itm(1)} -attr xrf 25552 -attr oid 848 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#454.itm}
+load net {ACC1:exs#858.itm(0)} -attr vt d
+load net {ACC1:exs#858.itm(1)} -attr vt d
+load netBundle {ACC1:exs#858.itm} 2 {ACC1:exs#858.itm(0)} {ACC1:exs#858.itm(1)} -attr xrf 25553 -attr oid 849 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#858.itm}
+load net {ACC1:exs#833.itm(0)} -attr vt d
+load net {ACC1:exs#833.itm(1)} -attr vt d
+load netBundle {ACC1:exs#833.itm} 2 {ACC1:exs#833.itm(0)} {ACC1:exs#833.itm(1)} -attr xrf 25554 -attr oid 850 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#833.itm}
+load net {ACC1:acc#169.itm(0)} -attr vt d
+load net {ACC1:acc#169.itm(1)} -attr vt d
+load net {ACC1:acc#169.itm(2)} -attr vt d
+load net {ACC1:acc#169.itm(3)} -attr vt d
+load netBundle {ACC1:acc#169.itm} 4 {ACC1:acc#169.itm(0)} {ACC1:acc#169.itm(1)} {ACC1:acc#169.itm(2)} {ACC1:acc#169.itm(3)} -attr xrf 25555 -attr oid 851 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load net {conc#738.itm(0)} -attr vt d
+load net {conc#738.itm(1)} -attr vt d
+load net {conc#738.itm(2)} -attr vt d
+load netBundle {conc#738.itm} 3 {conc#738.itm(0)} {conc#738.itm(1)} {conc#738.itm(2)} -attr xrf 25556 -attr oid 852 -attr vt d -attr @path {/sobel/sobel:core/conc#738.itm}
+load net {ACC1-3:not#145.itm(0)} -attr vt d
+load net {ACC1-3:not#145.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#145.itm} 2 {ACC1-3:not#145.itm(0)} {ACC1-3:not#145.itm(1)} -attr xrf 25557 -attr oid 853 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#145.itm}
+load net {slc(ACC1:acc#116.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#116.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#116.psp.sva).itm} 2 {slc(ACC1:acc#116.psp.sva).itm(0)} {slc(ACC1:acc#116.psp.sva).itm(1)} -attr xrf 25558 -attr oid 854 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp.sva).itm}
+load net {conc#739.itm(0)} -attr vt d
+load net {conc#739.itm(1)} -attr vt d
+load netBundle {conc#739.itm} 2 {conc#739.itm(0)} {conc#739.itm(1)} -attr xrf 25559 -attr oid 855 -attr vt d -attr @path {/sobel/sobel:core/conc#739.itm}
+load net {slc(FRAME:p#1.sva#2).itm(0)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(1)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(2)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(3)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(4)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(5)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(6)} -attr vt d
+load netBundle {slc(FRAME:p#1.sva#2).itm} 7 {slc(FRAME:p#1.sva#2).itm(0)} {slc(FRAME:p#1.sva#2).itm(1)} {slc(FRAME:p#1.sva#2).itm(2)} {slc(FRAME:p#1.sva#2).itm(3)} {slc(FRAME:p#1.sva#2).itm(4)} {slc(FRAME:p#1.sva#2).itm(5)} {slc(FRAME:p#1.sva#2).itm(6)} -attr xrf 25560 -attr oid 856 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:for:exs.itm(0)} -attr vt d
+load net {FRAME:for:exs.itm(1)} -attr vt d
+load net {FRAME:for:exs.itm(2)} -attr vt d
+load net {FRAME:for:exs.itm(3)} -attr vt d
+load net {FRAME:for:exs.itm(4)} -attr vt d
+load net {FRAME:for:exs.itm(5)} -attr vt d
+load net {FRAME:for:exs.itm(6)} -attr vt d
+load net {FRAME:for:exs.itm(7)} -attr vt d
+load net {FRAME:for:exs.itm(8)} -attr vt d
+load net {FRAME:for:exs.itm(9)} -attr vt d
+load net {FRAME:for:exs.itm(10)} -attr vt d
+load net {FRAME:for:exs.itm(11)} -attr vt d
+load net {FRAME:for:exs.itm(12)} -attr vt d
+load net {FRAME:for:exs.itm(13)} -attr vt d
+load net {FRAME:for:exs.itm(14)} -attr vt d
+load net {FRAME:for:exs.itm(15)} -attr vt d
+load net {FRAME:for:exs.itm(16)} -attr vt d
+load net {FRAME:for:exs.itm(17)} -attr vt d
+load net {FRAME:for:exs.itm(18)} -attr vt d
+load netBundle {FRAME:for:exs.itm} 19 {FRAME:for:exs.itm(0)} {FRAME:for:exs.itm(1)} {FRAME:for:exs.itm(2)} {FRAME:for:exs.itm(3)} {FRAME:for:exs.itm(4)} {FRAME:for:exs.itm(5)} {FRAME:for:exs.itm(6)} {FRAME:for:exs.itm(7)} {FRAME:for:exs.itm(8)} {FRAME:for:exs.itm(9)} {FRAME:for:exs.itm(10)} {FRAME:for:exs.itm(11)} {FRAME:for:exs.itm(12)} {FRAME:for:exs.itm(13)} {FRAME:for:exs.itm(14)} {FRAME:for:exs.itm(15)} {FRAME:for:exs.itm(16)} {FRAME:for:exs.itm(17)} {FRAME:for:exs.itm(18)} -attr xrf 25561 -attr oid 857 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {slc(acc.imod#18.sva).itm(0)} -attr vt d
+load net {slc(acc.imod#18.sva).itm(1)} -attr vt d
+load netBundle {slc(acc.imod#18.sva).itm} 2 {slc(acc.imod#18.sva).itm(0)} {slc(acc.imod#18.sva).itm(1)} -attr xrf 25562 -attr oid 858 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva).itm}
+load net {slc(ACC1:acc#110.psp#2.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#110.psp#2.sva).itm(1)} -attr vt d
+load net {slc(ACC1:acc#110.psp#2.sva).itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#110.psp#2.sva).itm} 3 {slc(ACC1:acc#110.psp#2.sva).itm(0)} {slc(ACC1:acc#110.psp#2.sva).itm(1)} {slc(ACC1:acc#110.psp#2.sva).itm(2)} -attr xrf 25563 -attr oid 859 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.sva).itm}
+load net {ACC1:slc#21.itm(0)} -attr vt d
+load net {ACC1:slc#21.itm(1)} -attr vt d
+load netBundle {ACC1:slc#21.itm} 2 {ACC1:slc#21.itm(0)} {ACC1:slc#21.itm(1)} -attr xrf 25564 -attr oid 860 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#21.itm}
+load net {ACC1:acc#151.itm(0)} -attr vt d
+load net {ACC1:acc#151.itm(1)} -attr vt d
+load net {ACC1:acc#151.itm(2)} -attr vt d
+load netBundle {ACC1:acc#151.itm} 3 {ACC1:acc#151.itm(0)} {ACC1:acc#151.itm(1)} {ACC1:acc#151.itm(2)} -attr xrf 25565 -attr oid 861 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151.itm}
+load net {conc#740.itm(0)} -attr vt d
+load net {conc#740.itm(1)} -attr vt d
+load net {conc#740.itm(2)} -attr vt d
+load netBundle {conc#740.itm} 3 {conc#740.itm(0)} {conc#740.itm(1)} {conc#740.itm(2)} -attr xrf 25566 -attr oid 862 -attr vt d -attr @path {/sobel/sobel:core/conc#740.itm}
+load net {ACC1:conc#477.itm(0)} -attr vt d
+load net {ACC1:conc#477.itm(1)} -attr vt d
+load netBundle {ACC1:conc#477.itm} 2 {ACC1:conc#477.itm(0)} {ACC1:conc#477.itm(1)} -attr xrf 25567 -attr oid 863 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#477.itm}
+load net {slc(ACC1:acc#118.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#118.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#118.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#118.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#118.psp#1.sva)#2.itm(1)} -attr xrf 25568 -attr oid 864 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp#1.sva)#2.itm}
+load net {clk} -attr xrf 25569 -attr oid 865
+load net {clk} -port {clk} -attr xrf 25570 -attr oid 866
+load net {en} -attr xrf 25571 -attr oid 867
+load net {en} -port {en} -attr xrf 25572 -attr oid 868
+load net {arst_n} -attr xrf 25573 -attr oid 869
+load net {arst_n} -port {arst_n} -attr xrf 25574 -attr oid 870
+load net {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 25575 -attr oid 871 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(0)} -port {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -port {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -port {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -port {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -port {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -port {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -port {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -port {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -port {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -port {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -port {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -port {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -port {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -port {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -port {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -port {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -port {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -port {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -port {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -port {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -port {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -port {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -port {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -port {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -port {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -port {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -port {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -port {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -port {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -port {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -port {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -port {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -port {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -port {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -port {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -port {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -port {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -port {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -port {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -port {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -port {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -port {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -port {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -port {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -port {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -port {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -port {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -port {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -port {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -port {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -port {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -port {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -port {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -port {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -port {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -port {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -port {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -port {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -port {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -port {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -port {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -port {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -port {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -port {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -port {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -port {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -port {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -port {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -port {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -port {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -port {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -port {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -port {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -port {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -port {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -port {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -port {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -port {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -port {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -port {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -port {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -port {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -port {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -port {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -port {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -port {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -port {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -port {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -port {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -port {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 25576 -attr oid 872 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d} 30 {vout:rsc:mgc_out_stdreg.d(0)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(29)} -attr xrf 25577 -attr oid 873 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -port {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -port {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -port {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -port {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -port {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -port {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -port {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -port {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -port {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -port {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -port {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -port {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -port {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -port {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -port {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -port {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -port {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -port {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -port {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -port {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -port {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -port {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -port {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -port {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -port {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -port {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -port {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -port {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -port {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -port {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:or" "or(2,10)" "INTERFACE" -attr xrf 25578 -attr oid 874 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or} -attr area 7.298324 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2)"
+load net {FRAME:acc#2.psp.sva(0)} -pin  "FRAME:or" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "FRAME:or" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "FRAME:or" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "FRAME:or" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "FRAME:or" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "FRAME:or" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "FRAME:or" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "FRAME:or" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "FRAME:or" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "FRAME:or" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(10)} -pin  "FRAME:or" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {FRAME:acc#2.psp.sva(11)} -pin  "FRAME:or" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(2)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(3)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(4)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(5)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(6)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(7)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(8)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(9)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {FRAME:or.itm(0)} -pin  "FRAME:or" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(1)} -pin  "FRAME:or" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(2)} -pin  "FRAME:or" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(3)} -pin  "FRAME:or" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(4)} -pin  "FRAME:or" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(5)} -pin  "FRAME:or" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(6)} -pin  "FRAME:or" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(7)} -pin  "FRAME:or" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(8)} -pin  "FRAME:or" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(9)} -pin  "FRAME:or" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load inst "FRAME:or#3" "or(2,6)" "INTERFACE" -attr xrf 25579 -attr oid 875 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3} -attr area 4.378994 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2)"
+load net {FRAME:acc#2.psp.sva(0)} -pin  "FRAME:or#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "FRAME:or#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "FRAME:or#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "FRAME:or#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "FRAME:or#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "FRAME:or#3" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(10)} -pin  "FRAME:or#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {FRAME:acc#2.psp.sva(11)} -pin  "FRAME:or#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(2)} -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(3)} -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(4)} -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(5)} -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {FRAME:or#3.itm(0)} -pin  "FRAME:or#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(1)} -pin  "FRAME:or#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(2)} -pin  "FRAME:or#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(3)} -pin  "FRAME:or#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(4)} -pin  "FRAME:or#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(5)} -pin  "FRAME:or#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load inst "nand" "nand(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "nand" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {main.stage_0#2} -pin  "nand" {A1(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {nand.itm} -pin  "nand" {Z(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load inst "mux" "mux(2,30)" "INTERFACE" -attr xrf 25580 -attr oid 876 -attr vt d -attr @path {/sobel/sobel:core/mux} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "mux" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "mux" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "mux" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "mux" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "mux" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "mux" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "mux" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "mux" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "mux" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "mux" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "mux" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "mux" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "mux" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "mux" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "mux" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "mux" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "mux" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "mux" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "mux" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "mux" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "mux" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "mux" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "mux" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "mux" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "mux" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "mux" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "mux" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "mux" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "mux" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "mux" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {FRAME:acc#2.psp.sva(0)} -pin  "mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(0)} -pin  "mux" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(1)} -pin  "mux" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(2)} -pin  "mux" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(3)} -pin  "mux" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(4)} -pin  "mux" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(5)} -pin  "mux" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "mux" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "mux" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "mux" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "mux" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(0)} -pin  "mux" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(1)} -pin  "mux" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(2)} -pin  "mux" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(3)} -pin  "mux" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(4)} -pin  "mux" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(5)} -pin  "mux" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(6)} -pin  "mux" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(7)} -pin  "mux" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(8)} -pin  "mux" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(9)} -pin  "mux" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {nand.itm} -pin  "mux" {S(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load net {mux.itm(0)} -pin  "mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "mux" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "mux" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "mux" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "mux" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "mux" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "mux" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "mux" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "mux" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "mux" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "mux" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "mux" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "mux" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "mux" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "mux" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "mux" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "mux" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "mux" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "mux" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "mux" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "mux" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 25581 -attr oid 877 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)}
+load net {mux.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 25582 -attr oid 878 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "mux#1" "mux(2,16)" "INTERFACE" -attr xrf 25583 -attr oid 879 -attr vt d -attr @path {/sobel/sobel:core/mux#1} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {in(2).sva#3(0)} -pin  "mux#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(1)} -pin  "mux#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(2)} -pin  "mux#1" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(3)} -pin  "mux#1" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(4)} -pin  "mux#1" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(5)} -pin  "mux#1" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(6)} -pin  "mux#1" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(7)} -pin  "mux#1" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(8)} -pin  "mux#1" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(9)} -pin  "mux#1" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(10)} -pin  "mux#1" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(11)} -pin  "mux#1" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(12)} -pin  "mux#1" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(13)} -pin  "mux#1" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(14)} -pin  "mux#1" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(15)} -pin  "mux#1" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#1(0)} -pin  "mux#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(1)} -pin  "mux#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(2)} -pin  "mux#1" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(3)} -pin  "mux#1" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(4)} -pin  "mux#1" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(5)} -pin  "mux#1" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(6)} -pin  "mux#1" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(7)} -pin  "mux#1" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(8)} -pin  "mux#1" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(9)} -pin  "mux#1" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(10)} -pin  "mux#1" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(11)} -pin  "mux#1" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(12)} -pin  "mux#1" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(13)} -pin  "mux#1" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(14)} -pin  "mux#1" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(15)} -pin  "mux#1" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {main.stage_0#2} -pin  "mux#1" {S(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {mux#1.itm(0)} -pin  "mux#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(1)} -pin  "mux#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(2)} -pin  "mux#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(3)} -pin  "mux#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(4)} -pin  "mux#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(5)} -pin  "mux#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(6)} -pin  "mux#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(7)} -pin  "mux#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(8)} -pin  "mux#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(9)} -pin  "mux#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(10)} -pin  "mux#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(11)} -pin  "mux#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(12)} -pin  "mux#1" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(13)} -pin  "mux#1" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(14)} -pin  "mux#1" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(15)} -pin  "mux#1" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load inst "reg(in(2).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 25584 -attr oid 880 -attr vt d -attr @path {/sobel/sobel:core/reg(in(2).sva#1)}
+load net {mux#1.itm(0)} -pin  "reg(in(2).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(1)} -pin  "reg(in(2).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(2)} -pin  "reg(in(2).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(3)} -pin  "reg(in(2).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(4)} -pin  "reg(in(2).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(5)} -pin  "reg(in(2).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(6)} -pin  "reg(in(2).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(7)} -pin  "reg(in(2).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(8)} -pin  "reg(in(2).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(9)} -pin  "reg(in(2).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(10)} -pin  "reg(in(2).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(11)} -pin  "reg(in(2).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(12)} -pin  "reg(in(2).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(13)} -pin  "reg(in(2).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(14)} -pin  "reg(in(2).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(15)} -pin  "reg(in(2).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(in(2).sva#1)" {clk} -attr xrf 25585 -attr oid 881 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(in(2).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(in(2).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {in(2).sva#1(0)} -pin  "reg(in(2).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(1)} -pin  "reg(in(2).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(2)} -pin  "reg(in(2).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(3)} -pin  "reg(in(2).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(4)} -pin  "reg(in(2).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(5)} -pin  "reg(in(2).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(6)} -pin  "reg(in(2).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(7)} -pin  "reg(in(2).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(8)} -pin  "reg(in(2).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(9)} -pin  "reg(in(2).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(10)} -pin  "reg(in(2).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(11)} -pin  "reg(in(2).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(12)} -pin  "reg(in(2).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(13)} -pin  "reg(in(2).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(14)} -pin  "reg(in(2).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(15)} -pin  "reg(in(2).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load inst "ACC2:acc#5" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 25586 -attr oid 882 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#5} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC2:acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#14.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC2:acc#5" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#13.itm}
+load net {ACC2:acc#5.itm(0)} -pin  "ACC2:acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#5.itm}
+load net {ACC2:acc#5.itm(1)} -pin  "ACC2:acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#5.itm}
+load inst "ACC1:mul#20" "mul(2,0,12,1,13)" "INTERFACE" -attr xrf 25587 -attr oid 883 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC2:acc#5.itm(0)} -pin  "ACC1:mul#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#5.itm}
+load net {ACC2:acc#5.itm(1)} -pin  "ACC1:mul#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#5.itm}
+load net {PWR} -pin  "ACC1:mul#20" {B(0)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(1)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(2)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(3)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(4)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(5)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(6)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(7)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(8)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {PWR} -pin  "ACC1:mul#20" {B(9)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(10)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {PWR} -pin  "ACC1:mul#20" {B(11)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {ACC1:mul#20.itm(0)} -pin  "ACC1:mul#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(1)} -pin  "ACC1:mul#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(2)} -pin  "ACC1:mul#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(3)} -pin  "ACC1:mul#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(4)} -pin  "ACC1:mul#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(5)} -pin  "ACC1:mul#20" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(6)} -pin  "ACC1:mul#20" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(7)} -pin  "ACC1:mul#20" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(8)} -pin  "ACC1:mul#20" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(9)} -pin  "ACC1:mul#20" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(10)} -pin  "ACC1:mul#20" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(11)} -pin  "ACC1:mul#20" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(12)} -pin  "ACC1:mul#20" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load inst "ACC2:acc#6" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 25588 -attr oid 884 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#6} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} -pin  "ACC2:acc#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#31.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} -pin  "ACC2:acc#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#31.itm}
+load net {ACC2:acc#6.itm(0)} -pin  "ACC2:acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#6.itm}
+load net {ACC2:acc#6.itm(1)} -pin  "ACC2:acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#6.itm}
+load inst "ACC1:mul#21" "mul(2,0,5,0,6)" "INTERFACE" -attr xrf 25589 -attr oid 885 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC2:acc#6.itm(0)} -pin  "ACC1:mul#21" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#6.itm}
+load net {ACC2:acc#6.itm(1)} -pin  "ACC1:mul#21" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#6.itm}
+load net {PWR} -pin  "ACC1:mul#21" {B(0)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#21" {B(1)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#21" {B(2)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#21" {B(3)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#21" {B(4)} -attr @path {/sobel/sobel:core/C21_5}
+load net {ACC1:mul#21.itm(0)} -pin  "ACC1:mul#21" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load net {ACC1:mul#21.itm(1)} -pin  "ACC1:mul#21" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load net {ACC1:mul#21.itm(2)} -pin  "ACC1:mul#21" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load net {ACC1:mul#21.itm(3)} -pin  "ACC1:mul#21" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load net {ACC1:mul#21.itm(4)} -pin  "ACC1:mul#21" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load net {ACC1:mul#21.itm(5)} -pin  "ACC1:mul#21" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load inst "ACC2:acc#3" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 25590 -attr oid 886 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#3} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(7)} -pin  "ACC2:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#3.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(7)} -pin  "ACC2:acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#2.itm}
+load net {ACC2:acc#3.itm(0)} -pin  "ACC2:acc#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#3.itm}
+load net {ACC2:acc#3.itm(1)} -pin  "ACC2:acc#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#3.itm}
+load inst "ACC1:mul#18" "mul(2,0,7,0,8)" "INTERFACE" -attr xrf 25591 -attr oid 887 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC2:acc#3.itm(0)} -pin  "ACC1:mul#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#3.itm}
+load net {ACC2:acc#3.itm(1)} -pin  "ACC1:mul#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#3.itm}
+load net {PWR} -pin  "ACC1:mul#18" {B(0)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#18" {B(1)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#18" {B(2)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#18" {B(3)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#18" {B(4)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#18" {B(5)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#18" {B(6)} -attr @path {/sobel/sobel:core/C85_7}
+load net {ACC1:mul#18.itm(0)} -pin  "ACC1:mul#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(1)} -pin  "ACC1:mul#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(2)} -pin  "ACC1:mul#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(3)} -pin  "ACC1:mul#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(4)} -pin  "ACC1:mul#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(5)} -pin  "ACC1:mul#18" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(6)} -pin  "ACC1:mul#18" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(7)} -pin  "ACC1:mul#18" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load inst "ACC2:acc" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 25592 -attr oid 888 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(5)} -pin  "ACC2:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#4.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(5)} -pin  "ACC2:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#3.itm}
+load net {ACC2:acc.itm(0)} -pin  "ACC2:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(1)} -pin  "ACC2:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load inst "ACC1:mul" "mul(2,0,5,0,6)" "INTERFACE" -attr xrf 25593 -attr oid 889 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC2:acc.itm(0)} -pin  "ACC1:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(1)} -pin  "ACC1:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {PWR} -pin  "ACC1:mul" {B(0)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul" {B(1)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul" {B(2)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul" {B(3)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul" {B(4)} -attr @path {/sobel/sobel:core/C21_5}
+load net {ACC1:mul.itm(0)} -pin  "ACC1:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(1)} -pin  "ACC1:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(2)} -pin  "ACC1:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(3)} -pin  "ACC1:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(4)} -pin  "ACC1:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(5)} -pin  "ACC1:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load inst "ACC1:acc#330" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 25594 -attr oid 890 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:mul.itm(0)} -pin  "ACC1:acc#330" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(1)} -pin  "ACC1:acc#330" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(2)} -pin  "ACC1:acc#330" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(3)} -pin  "ACC1:acc#330" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(4)} -pin  "ACC1:acc#330" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(5)} -pin  "ACC1:acc#330" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#330" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#330" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {GND} -pin  "ACC1:acc#330" {B(2)} -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} -pin  "ACC1:acc#330" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {GND} -pin  "ACC1:acc#330" {B(4)} -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#330" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {ACC1:acc#330.itm(0)} -pin  "ACC1:acc#330" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(1)} -pin  "ACC1:acc#330" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(2)} -pin  "ACC1:acc#330" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(3)} -pin  "ACC1:acc#330" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(4)} -pin  "ACC1:acc#330" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(5)} -pin  "ACC1:acc#330" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(6)} -pin  "ACC1:acc#330" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load inst "ACC1:acc#334" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 25595 -attr oid 891 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:mul#18.itm(0)} -pin  "ACC1:acc#334" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(1)} -pin  "ACC1:acc#334" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(2)} -pin  "ACC1:acc#334" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(3)} -pin  "ACC1:acc#334" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(4)} -pin  "ACC1:acc#334" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(5)} -pin  "ACC1:acc#334" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(6)} -pin  "ACC1:acc#334" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(7)} -pin  "ACC1:acc#334" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:acc#330.itm(0)} -pin  "ACC1:acc#334" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(1)} -pin  "ACC1:acc#334" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(2)} -pin  "ACC1:acc#334" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(3)} -pin  "ACC1:acc#334" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(4)} -pin  "ACC1:acc#334" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(5)} -pin  "ACC1:acc#334" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(6)} -pin  "ACC1:acc#334" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#334.itm(0)} -pin  "ACC1:acc#334" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(1)} -pin  "ACC1:acc#334" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(2)} -pin  "ACC1:acc#334" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(3)} -pin  "ACC1:acc#334" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(4)} -pin  "ACC1:acc#334" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(5)} -pin  "ACC1:acc#334" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(6)} -pin  "ACC1:acc#334" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(7)} -pin  "ACC1:acc#334" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load inst "ACC1:acc#336" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 25596 -attr oid 892 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336} -attr area 10.253676 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,0,10)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#336" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#336" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(3)} -pin  "ACC1:acc#336" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(0)} -pin  "ACC1:acc#336" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(1)} -pin  "ACC1:acc#336" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(2)} -pin  "ACC1:acc#336" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(3)} -pin  "ACC1:acc#336" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(4)} -pin  "ACC1:acc#336" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(5)} -pin  "ACC1:acc#336" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:acc#334.itm(0)} -pin  "ACC1:acc#336" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(1)} -pin  "ACC1:acc#336" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(2)} -pin  "ACC1:acc#336" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(3)} -pin  "ACC1:acc#336" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(4)} -pin  "ACC1:acc#336" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(5)} -pin  "ACC1:acc#336" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(6)} -pin  "ACC1:acc#336" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(7)} -pin  "ACC1:acc#336" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#336.itm(0)} -pin  "ACC1:acc#336" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(1)} -pin  "ACC1:acc#336" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(2)} -pin  "ACC1:acc#336" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(3)} -pin  "ACC1:acc#336" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(4)} -pin  "ACC1:acc#336" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(5)} -pin  "ACC1:acc#336" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(6)} -pin  "ACC1:acc#336" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(7)} -pin  "ACC1:acc#336" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(8)} -pin  "ACC1:acc#336" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(9)} -pin  "ACC1:acc#336" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load inst "ACC1:acc#310" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25597 -attr oid 893 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#310" {A(0)} -attr @path {/sobel/sobel:core/exs.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#310" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#310" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(0)} -pin  "ACC1:acc#310" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#793.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#310" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#793.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#310" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#793.itm}
+load net {ACC1:acc#310.itm(0)} -pin  "ACC1:acc#310" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(1)} -pin  "ACC1:acc#310" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(2)} -pin  "ACC1:acc#310" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(3)} -pin  "ACC1:acc#310" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load inst "ACC1:acc#309" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25598 -attr oid 894 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#309" {A(0)} -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} -pin  "ACC1:acc#309" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} -pin  "ACC1:acc#309" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(2)} -pin  "ACC1:acc#309" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#795.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#309" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#795.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#309" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#795.itm}
+load net {ACC1:acc#309.itm(0)} -pin  "ACC1:acc#309" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(1)} -pin  "ACC1:acc#309" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(2)} -pin  "ACC1:acc#309" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(3)} -pin  "ACC1:acc#309" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load inst "ACC1:acc#319" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25599 -attr oid 895 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#310.itm(1)} -pin  "ACC1:acc#319" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#310.itm(2)} -pin  "ACC1:acc#319" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#310.itm(3)} -pin  "ACC1:acc#319" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#309.itm(1)} -pin  "ACC1:acc#319" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#309.itm(2)} -pin  "ACC1:acc#319" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#309.itm(3)} -pin  "ACC1:acc#319" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#319.itm(0)} -pin  "ACC1:acc#319" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(1)} -pin  "ACC1:acc#319" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(2)} -pin  "ACC1:acc#319" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(3)} -pin  "ACC1:acc#319" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load inst "ACC1:acc#307" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25600 -attr oid 896 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#307" {A(0)} -attr @path {/sobel/sobel:core/exs#28.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#307" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#28.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#307" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#28.itm}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(0)} -pin  "ACC1:acc#307" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#797.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#307" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#797.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#307" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#797.itm}
+load net {ACC1:acc#307.itm(0)} -pin  "ACC1:acc#307" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#307.itm(1)} -pin  "ACC1:acc#307" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#307.itm(2)} -pin  "ACC1:acc#307" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#307.itm(3)} -pin  "ACC1:acc#307" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load inst "ACC1-3:not#60" "not(1)" "INTERFACE" -attr xrf 25601 -attr oid 897 -attr @path {/sobel/sobel:core/ACC1-3:not#60} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#7.lpi#1.dfm:mx0(1)} -pin  "ACC1-3:not#60" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.lpi#1.dfm:mx0)#2.itm}
+load net {ACC1-3:not#60.itm} -pin  "ACC1-3:not#60" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#60.itm}
+load inst "ACC1-3:and#3" "and(3,1)" "INTERFACE" -attr xrf 25602 -attr oid 898 -attr @path {/sobel/sobel:core/ACC1-3:and#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1-3:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#19.itm}
+load net {ACC1-3:not#60.itm} -pin  "ACC1-3:and#3" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#60.itm}
+load net {acc.imod#7.lpi#1.dfm:mx0(0)} -pin  "ACC1-3:and#3" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.lpi#1.dfm:mx0)#1.itm}
+load net {ACC1-3:and#3.itm} -pin  "ACC1-3:and#3" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#3.itm}
+load inst "ACC1:acc#306" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25603 -attr oid 899 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#306" {A(0)} -attr @path {/sobel/sobel:core/exs#29.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#306" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#29.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#306" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#29.itm}
+load net {ACC1-3:and#3.itm} -pin  "ACC1:acc#306" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#799.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#306" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#799.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#306" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#799.itm}
+load net {ACC1:acc#306.itm(0)} -pin  "ACC1:acc#306" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(1)} -pin  "ACC1:acc#306" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(2)} -pin  "ACC1:acc#306" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(3)} -pin  "ACC1:acc#306" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load inst "ACC1:acc#318" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25604 -attr oid 900 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#307.itm(1)} -pin  "ACC1:acc#318" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#307.itm(2)} -pin  "ACC1:acc#318" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#307.itm(3)} -pin  "ACC1:acc#318" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#306.itm(1)} -pin  "ACC1:acc#318" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#306.itm(2)} -pin  "ACC1:acc#318" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#306.itm(3)} -pin  "ACC1:acc#318" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#318.itm(0)} -pin  "ACC1:acc#318" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(1)} -pin  "ACC1:acc#318" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(2)} -pin  "ACC1:acc#318" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(3)} -pin  "ACC1:acc#318" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load inst "ACC1:acc#325" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 25605 -attr oid 901 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#319.itm(0)} -pin  "ACC1:acc#325" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(1)} -pin  "ACC1:acc#325" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(2)} -pin  "ACC1:acc#325" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(3)} -pin  "ACC1:acc#325" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#318.itm(0)} -pin  "ACC1:acc#325" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(1)} -pin  "ACC1:acc#325" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(2)} -pin  "ACC1:acc#325" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(3)} -pin  "ACC1:acc#325" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#325.itm(0)} -pin  "ACC1:acc#325" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(1)} -pin  "ACC1:acc#325" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(2)} -pin  "ACC1:acc#325" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(3)} -pin  "ACC1:acc#325" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(4)} -pin  "ACC1:acc#325" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load inst "ACC1-3:not#59" "not(1)" "INTERFACE" -attr xrf 25606 -attr oid 902 -attr @path {/sobel/sobel:core/ACC1-3:not#59} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1-3:not#59" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#20.itm}
+load net {ACC1-3:not#59.itm} -pin  "ACC1-3:not#59" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#59.itm}
+load inst "ACC1-3:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 25607 -attr oid 903 -attr @path {/sobel/sobel:core/ACC1-3:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {acc.imod#7.lpi#1.dfm:mx0(1)} -pin  "ACC1-3:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.lpi#1.dfm:mx0).itm}
+load net {ACC1-3:not#59.itm} -pin  "ACC1-3:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#59.itm}
+load net {ACC1-3:nand#1.itm} -pin  "ACC1-3:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand#1.itm}
+load inst "ACC1:acc#305" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25608 -attr oid 904 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#305" {A(0)} -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#305" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#305" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {ACC1-3:nand#1.itm} -pin  "ACC1:acc#305" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#801.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} -pin  "ACC1:acc#305" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#801.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} -pin  "ACC1:acc#305" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#801.itm}
+load net {ACC1:acc#305.itm(0)} -pin  "ACC1:acc#305" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(1)} -pin  "ACC1:acc#305" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(2)} -pin  "ACC1:acc#305" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(3)} -pin  "ACC1:acc#305" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load inst "ACC1:acc#304" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25609 -attr oid 905 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#304" {A(0)} -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} -pin  "ACC1:acc#304" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} -pin  "ACC1:acc#304" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(0)} -pin  "ACC1:acc#304" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#803.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#304" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#803.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#304" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#803.itm}
+load net {ACC1:acc#304.itm(0)} -pin  "ACC1:acc#304" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(1)} -pin  "ACC1:acc#304" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(2)} -pin  "ACC1:acc#304" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(3)} -pin  "ACC1:acc#304" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load inst "ACC1:acc#317" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25610 -attr oid 906 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#305.itm(1)} -pin  "ACC1:acc#317" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#92.itm}
+load net {ACC1:acc#305.itm(2)} -pin  "ACC1:acc#317" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#92.itm}
+load net {ACC1:acc#305.itm(3)} -pin  "ACC1:acc#317" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#92.itm}
+load net {ACC1:acc#304.itm(1)} -pin  "ACC1:acc#317" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#91.itm}
+load net {ACC1:acc#304.itm(2)} -pin  "ACC1:acc#317" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#91.itm}
+load net {ACC1:acc#304.itm(3)} -pin  "ACC1:acc#317" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#91.itm}
+load net {ACC1:acc#317.itm(0)} -pin  "ACC1:acc#317" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(1)} -pin  "ACC1:acc#317" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(2)} -pin  "ACC1:acc#317" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(3)} -pin  "ACC1:acc#317" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load inst "ACC1:acc#303" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25611 -attr oid 907 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#303" {A(0)} -attr @path {/sobel/sobel:core/exs#30.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#303" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#30.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#303" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#30.itm}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(2)} -pin  "ACC1:acc#303" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#805.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#303" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#805.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#303" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#805.itm}
+load net {ACC1:acc#303.itm(0)} -pin  "ACC1:acc#303" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(1)} -pin  "ACC1:acc#303" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(2)} -pin  "ACC1:acc#303" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(3)} -pin  "ACC1:acc#303" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load inst "ACC1:acc#302" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25612 -attr oid 908 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#302" {A(0)} -attr @path {/sobel/sobel:core/exs#31.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#302" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#31.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#302" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#31.itm}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(1)} -pin  "ACC1:acc#302" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#807.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#302" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#807.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#302" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#807.itm}
+load net {ACC1:acc#302.itm(0)} -pin  "ACC1:acc#302" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(1)} -pin  "ACC1:acc#302" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(2)} -pin  "ACC1:acc#302" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(3)} -pin  "ACC1:acc#302" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load inst "ACC1:acc#316" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25613 -attr oid 909 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#303.itm(1)} -pin  "ACC1:acc#316" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1:acc#303.itm(2)} -pin  "ACC1:acc#316" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1:acc#303.itm(3)} -pin  "ACC1:acc#316" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1:acc#302.itm(1)} -pin  "ACC1:acc#316" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#302.itm(2)} -pin  "ACC1:acc#316" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#302.itm(3)} -pin  "ACC1:acc#316" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#316.itm(0)} -pin  "ACC1:acc#316" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(1)} -pin  "ACC1:acc#316" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(2)} -pin  "ACC1:acc#316" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(3)} -pin  "ACC1:acc#316" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load inst "ACC1:acc#324" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 25614 -attr oid 910 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#317.itm(0)} -pin  "ACC1:acc#324" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(1)} -pin  "ACC1:acc#324" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(2)} -pin  "ACC1:acc#324" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(3)} -pin  "ACC1:acc#324" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#316.itm(0)} -pin  "ACC1:acc#324" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(1)} -pin  "ACC1:acc#324" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(2)} -pin  "ACC1:acc#324" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(3)} -pin  "ACC1:acc#324" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#324.itm(0)} -pin  "ACC1:acc#324" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(1)} -pin  "ACC1:acc#324" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(2)} -pin  "ACC1:acc#324" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(3)} -pin  "ACC1:acc#324" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(4)} -pin  "ACC1:acc#324" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load inst "ACC1:acc#328" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 25615 -attr oid 911 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#325.itm(0)} -pin  "ACC1:acc#328" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(1)} -pin  "ACC1:acc#328" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(2)} -pin  "ACC1:acc#328" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(3)} -pin  "ACC1:acc#328" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(4)} -pin  "ACC1:acc#328" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#324.itm(0)} -pin  "ACC1:acc#328" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(1)} -pin  "ACC1:acc#328" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(2)} -pin  "ACC1:acc#328" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(3)} -pin  "ACC1:acc#328" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(4)} -pin  "ACC1:acc#328" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#328.itm(0)} -pin  "ACC1:acc#328" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(1)} -pin  "ACC1:acc#328" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(2)} -pin  "ACC1:acc#328" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(3)} -pin  "ACC1:acc#328" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(4)} -pin  "ACC1:acc#328" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(5)} -pin  "ACC1:acc#328" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load inst "ACC1:acc#332" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 25616 -attr oid 912 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#328.itm(0)} -pin  "ACC1:acc#332" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(1)} -pin  "ACC1:acc#332" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(2)} -pin  "ACC1:acc#332" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(3)} -pin  "ACC1:acc#332" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(4)} -pin  "ACC1:acc#332" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(5)} -pin  "ACC1:acc#332" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#332.itm(0)} -pin  "ACC1:acc#332" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(1)} -pin  "ACC1:acc#332" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(2)} -pin  "ACC1:acc#332" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(3)} -pin  "ACC1:acc#332" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(4)} -pin  "ACC1:acc#332" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(5)} -pin  "ACC1:acc#332" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(6)} -pin  "ACC1:acc#332" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(7)} -pin  "ACC1:acc#332" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load inst "ACC1:acc#301" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25617 -attr oid 913 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#301" {A(0)} -attr @path {/sobel/sobel:core/exs#32.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#301" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#32.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#301" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#32.itm}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(0)} -pin  "ACC1:acc#301" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#809.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#301" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#809.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#301" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#809.itm}
+load net {ACC1:acc#301.itm(0)} -pin  "ACC1:acc#301" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {ACC1:acc#301.itm(1)} -pin  "ACC1:acc#301" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {ACC1:acc#301.itm(2)} -pin  "ACC1:acc#301" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {ACC1:acc#301.itm(3)} -pin  "ACC1:acc#301" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load inst "ACC1:acc#300" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25618 -attr oid 914 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#300" {A(0)} -attr @path {/sobel/sobel:core/exs#33.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#300" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#33.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#300" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#33.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(3)} -pin  "ACC1:acc#300" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#811.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} -pin  "ACC1:acc#300" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#811.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} -pin  "ACC1:acc#300" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#811.itm}
+load net {ACC1:acc#300.itm(0)} -pin  "ACC1:acc#300" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#300.itm(1)} -pin  "ACC1:acc#300" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#300.itm(2)} -pin  "ACC1:acc#300" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#300.itm(3)} -pin  "ACC1:acc#300" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load inst "ACC1:acc#315" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25619 -attr oid 915 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#301.itm(1)} -pin  "ACC1:acc#315" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#301.itm(2)} -pin  "ACC1:acc#315" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#301.itm(3)} -pin  "ACC1:acc#315" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#300.itm(1)} -pin  "ACC1:acc#315" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#87.itm}
+load net {ACC1:acc#300.itm(2)} -pin  "ACC1:acc#315" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#87.itm}
+load net {ACC1:acc#300.itm(3)} -pin  "ACC1:acc#315" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#87.itm}
+load net {ACC1:acc#315.itm(0)} -pin  "ACC1:acc#315" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(1)} -pin  "ACC1:acc#315" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(2)} -pin  "ACC1:acc#315" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(3)} -pin  "ACC1:acc#315" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load inst "ACC1:acc#299" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25620 -attr oid 916 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#299" {A(0)} -attr @path {/sobel/sobel:core/exs#34.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#299" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#34.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#299" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#34.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(2)} -pin  "ACC1:acc#299" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#813.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#299" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#813.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#299" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#813.itm}
+load net {ACC1:acc#299.itm(0)} -pin  "ACC1:acc#299" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(1)} -pin  "ACC1:acc#299" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(2)} -pin  "ACC1:acc#299" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(3)} -pin  "ACC1:acc#299" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load inst "ACC1:acc#298" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25621 -attr oid 917 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#298" {A(0)} -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#298" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#298" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(1)} -pin  "ACC1:acc#298" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#815.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} -pin  "ACC1:acc#298" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#815.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} -pin  "ACC1:acc#298" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#815.itm}
+load net {ACC1:acc#298.itm(0)} -pin  "ACC1:acc#298" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(1)} -pin  "ACC1:acc#298" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(2)} -pin  "ACC1:acc#298" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(3)} -pin  "ACC1:acc#298" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load inst "ACC1:acc#314" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25622 -attr oid 918 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#299.itm(1)} -pin  "ACC1:acc#314" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#86.itm}
+load net {ACC1:acc#299.itm(2)} -pin  "ACC1:acc#314" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#86.itm}
+load net {ACC1:acc#299.itm(3)} -pin  "ACC1:acc#314" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#86.itm}
+load net {ACC1:acc#298.itm(1)} -pin  "ACC1:acc#314" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#85.itm}
+load net {ACC1:acc#298.itm(2)} -pin  "ACC1:acc#314" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#85.itm}
+load net {ACC1:acc#298.itm(3)} -pin  "ACC1:acc#314" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#85.itm}
+load net {ACC1:acc#314.itm(0)} -pin  "ACC1:acc#314" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(1)} -pin  "ACC1:acc#314" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(2)} -pin  "ACC1:acc#314" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(3)} -pin  "ACC1:acc#314" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load inst "ACC1:acc#323" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 25623 -attr oid 919 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#315.itm(0)} -pin  "ACC1:acc#323" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(1)} -pin  "ACC1:acc#323" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(2)} -pin  "ACC1:acc#323" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(3)} -pin  "ACC1:acc#323" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#314.itm(0)} -pin  "ACC1:acc#323" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(1)} -pin  "ACC1:acc#323" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(2)} -pin  "ACC1:acc#323" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(3)} -pin  "ACC1:acc#323" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#323.itm(0)} -pin  "ACC1:acc#323" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(1)} -pin  "ACC1:acc#323" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(2)} -pin  "ACC1:acc#323" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(3)} -pin  "ACC1:acc#323" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(4)} -pin  "ACC1:acc#323" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load inst "ACC1:acc#297" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25624 -attr oid 920 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#297" {A(0)} -attr @path {/sobel/sobel:core/exs#35.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#297" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#35.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#297" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#35.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(0)} -pin  "ACC1:acc#297" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#817.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#297" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#817.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#297" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#817.itm}
+load net {ACC1:acc#297.itm(0)} -pin  "ACC1:acc#297" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(1)} -pin  "ACC1:acc#297" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(2)} -pin  "ACC1:acc#297" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(3)} -pin  "ACC1:acc#297" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load inst "ACC1:acc#296" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25625 -attr oid 921 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#296" {A(0)} -attr @path {/sobel/sobel:core/exs#36.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#296" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#36.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#296" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#36.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(3)} -pin  "ACC1:acc#296" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#819.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#296" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#819.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#296" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#819.itm}
+load net {ACC1:acc#296.itm(0)} -pin  "ACC1:acc#296" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(1)} -pin  "ACC1:acc#296" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(2)} -pin  "ACC1:acc#296" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(3)} -pin  "ACC1:acc#296" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load inst "ACC1:acc#313" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25626 -attr oid 922 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#297.itm(1)} -pin  "ACC1:acc#313" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#84.itm}
+load net {ACC1:acc#297.itm(2)} -pin  "ACC1:acc#313" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#84.itm}
+load net {ACC1:acc#297.itm(3)} -pin  "ACC1:acc#313" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#84.itm}
+load net {ACC1:acc#296.itm(1)} -pin  "ACC1:acc#313" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#83.itm}
+load net {ACC1:acc#296.itm(2)} -pin  "ACC1:acc#313" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#83.itm}
+load net {ACC1:acc#296.itm(3)} -pin  "ACC1:acc#313" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#83.itm}
+load net {ACC1:acc#313.itm(0)} -pin  "ACC1:acc#313" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(1)} -pin  "ACC1:acc#313" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(2)} -pin  "ACC1:acc#313" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(3)} -pin  "ACC1:acc#313" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load inst "ACC1:acc#295" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25627 -attr oid 923 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#295" {A(0)} -attr @path {/sobel/sobel:core/conc#610.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(0)} -pin  "ACC1:acc#295" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#610.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(2)} -pin  "ACC1:acc#295" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#610.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(2)} -pin  "ACC1:acc#295" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#612.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(1)} -pin  "ACC1:acc#295" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#612.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(2)} -pin  "ACC1:acc#295" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#612.itm}
+load net {ACC1:acc#295.itm(0)} -pin  "ACC1:acc#295" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(1)} -pin  "ACC1:acc#295" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(2)} -pin  "ACC1:acc#295" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(3)} -pin  "ACC1:acc#295" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load inst "ACC2:not" "not(1)" "INTERFACE" -attr xrf 25628 -attr oid 924 -attr @path {/sobel/sobel:core/ACC2:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(2)} -pin  "ACC2:not" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0)#4.itm}
+load net {ACC2:not.itm} -pin  "ACC2:not" {Z(0)} -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load inst "ACC2:not#5" "not(1)" "INTERFACE" -attr xrf 25629 -attr oid 925 -attr @path {/sobel/sobel:core/ACC2:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(1)} -pin  "ACC2:not#5" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.lpi#1.dfm.sg1:mx0)#1.itm}
+load net {ACC2:not#5.itm} -pin  "ACC2:not#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC2:not#5.itm}
+load inst "ACC1-1:not#60" "not(1)" "INTERFACE" -attr xrf 25630 -attr oid 926 -attr @path {/sobel/sobel:core/ACC1-1:not#60} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#20.lpi#1.dfm:mx0(1)} -pin  "ACC1-1:not#60" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#20.lpi#1.dfm:mx0)#2.itm}
+load net {ACC1-1:not#60.itm} -pin  "ACC1-1:not#60" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#60.itm}
+load inst "ACC1-1:and#3" "and(3,1)" "INTERFACE" -attr xrf 25631 -attr oid 927 -attr @path {/sobel/sobel:core/ACC1-1:and#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1-1:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#24.itm}
+load net {ACC1-1:not#60.itm} -pin  "ACC1-1:and#3" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#60.itm}
+load net {acc.imod#20.lpi#1.dfm:mx0(0)} -pin  "ACC1-1:and#3" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#20.lpi#1.dfm:mx0)#1.itm}
+load net {ACC1-1:and#3.itm} -pin  "ACC1-1:and#3" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#3.itm}
+load inst "ACC1:acc#312" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 25632 -attr oid 928 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {PWR} -pin  "ACC1:acc#312" {A(0)} -attr @path {/sobel/sobel:core/conc#609.itm}
+load net {ACC1:acc#295.itm(1)} -pin  "ACC1:acc#312" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#609.itm}
+load net {ACC1:acc#295.itm(2)} -pin  "ACC1:acc#312" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#609.itm}
+load net {ACC1:acc#295.itm(3)} -pin  "ACC1:acc#312" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#609.itm}
+load net {ACC1-1:and#3.itm} -pin  "ACC1:acc#312" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#611.itm}
+load net {ACC2:not#5.itm} -pin  "ACC1:acc#312" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#611.itm}
+load net {PWR} -pin  "ACC1:acc#312" {B(2)} -attr @path {/sobel/sobel:core/conc#611.itm}
+load net {ACC2:not.itm} -pin  "ACC1:acc#312" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#611.itm}
+load net {ACC1:acc#312.itm(0)} -pin  "ACC1:acc#312" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(1)} -pin  "ACC1:acc#312" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(2)} -pin  "ACC1:acc#312" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(3)} -pin  "ACC1:acc#312" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(4)} -pin  "ACC1:acc#312" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load inst "ACC1:acc#322" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 25633 -attr oid 929 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#313.itm(0)} -pin  "ACC1:acc#322" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(1)} -pin  "ACC1:acc#322" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(2)} -pin  "ACC1:acc#322" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(3)} -pin  "ACC1:acc#322" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#312.itm(1)} -pin  "ACC1:acc#322" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#312.itm(2)} -pin  "ACC1:acc#322" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#312.itm(3)} -pin  "ACC1:acc#322" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#312.itm(4)} -pin  "ACC1:acc#322" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#322.itm(0)} -pin  "ACC1:acc#322" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(1)} -pin  "ACC1:acc#322" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(2)} -pin  "ACC1:acc#322" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(3)} -pin  "ACC1:acc#322" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(4)} -pin  "ACC1:acc#322" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load inst "ACC1:acc#327" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 25634 -attr oid 930 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#323.itm(0)} -pin  "ACC1:acc#327" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(1)} -pin  "ACC1:acc#327" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(2)} -pin  "ACC1:acc#327" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(3)} -pin  "ACC1:acc#327" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(4)} -pin  "ACC1:acc#327" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#322.itm(0)} -pin  "ACC1:acc#327" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(1)} -pin  "ACC1:acc#327" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(2)} -pin  "ACC1:acc#327" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(3)} -pin  "ACC1:acc#327" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(4)} -pin  "ACC1:acc#327" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#327.itm(0)} -pin  "ACC1:acc#327" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(1)} -pin  "ACC1:acc#327" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(2)} -pin  "ACC1:acc#327" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(3)} -pin  "ACC1:acc#327" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(4)} -pin  "ACC1:acc#327" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(5)} -pin  "ACC1:acc#327" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load inst "ACC2:not#2" "not(1)" "INTERFACE" -attr xrf 25635 -attr oid 931 -attr @path {/sobel/sobel:core/ACC2:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(2)} -pin  "ACC2:not#2" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0)#4.itm}
+load net {ACC2:not#2.itm} -pin  "ACC2:not#2" {Z(0)} -attr @path {/sobel/sobel:core/ACC2:not#2.itm}
+load inst "ACC2:not#7" "not(1)" "INTERFACE" -attr xrf 25636 -attr oid 932 -attr @path {/sobel/sobel:core/ACC2:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(1)} -pin  "ACC2:not#7" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#18.lpi#1.dfm.sg1:mx0)#1.itm}
+load net {ACC2:not#7.itm} -pin  "ACC2:not#7" {Z(0)} -attr @path {/sobel/sobel:core/ACC2:not#7.itm}
+load inst "ACC1-1:not#59" "not(1)" "INTERFACE" -attr xrf 25637 -attr oid 933 -attr @path {/sobel/sobel:core/ACC1-1:not#59} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1-1:not#59" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0).itm}
+load net {ACC1-1:not#59.itm} -pin  "ACC1-1:not#59" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#59.itm}
+load inst "ACC1-1:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 25638 -attr oid 934 -attr @path {/sobel/sobel:core/ACC1-1:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {acc.imod#20.lpi#1.dfm:mx0(1)} -pin  "ACC1-1:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#20.lpi#1.dfm:mx0).itm}
+load net {ACC1-1:not#59.itm} -pin  "ACC1-1:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#59.itm}
+load net {ACC1-1:nand#1.itm} -pin  "ACC1-1:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:nand#1.itm}
+load inst "ACC1:acc#311" "add(4,0,3,1,5)" "INTERFACE" -attr xrf 25639 -attr oid 935 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#311" {A(0)} -attr @path {/sobel/sobel:core/conc#612.itm}
+load net {ACC2:not#7.itm} -pin  "ACC1:acc#311" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#612.itm}
+load net {PWR} -pin  "ACC1:acc#311" {A(2)} -attr @path {/sobel/sobel:core/conc#612.itm}
+load net {ACC2:not#2.itm} -pin  "ACC1:acc#311" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#612.itm}
+load net {ACC1-1:nand#1.itm} -pin  "ACC1:acc#311" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#644.itm}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(0)} -pin  "ACC1:acc#311" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#644.itm}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(1)} -pin  "ACC1:acc#311" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#644.itm}
+load net {ACC1:acc#311.itm(0)} -pin  "ACC1:acc#311" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(1)} -pin  "ACC1:acc#311" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(2)} -pin  "ACC1:acc#311" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(3)} -pin  "ACC1:acc#311" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(4)} -pin  "ACC1:acc#311" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load inst "ACC1:acc#308" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 25640 -attr oid 936 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#308" {A(0)} -attr @path {/sobel/sobel:core/exs#37.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#308" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#37.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#308" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#37.itm}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(1)} -pin  "ACC1:acc#308" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#638.itm}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(0)} -pin  "ACC1:acc#308" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#638.itm}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(1)} -pin  "ACC1:acc#308" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#638.itm}
+load net {ACC1:acc#308.itm(0)} -pin  "ACC1:acc#308" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#308.itm(1)} -pin  "ACC1:acc#308" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#308.itm(2)} -pin  "ACC1:acc#308" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#308.itm(3)} -pin  "ACC1:acc#308" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#308.itm(4)} -pin  "ACC1:acc#308" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load inst "ACC1:acc#321" "add(4,-1,4,-1,4)" "INTERFACE" -attr xrf 25641 -attr oid 937 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#311.itm(1)} -pin  "ACC1:acc#321" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#311.itm(2)} -pin  "ACC1:acc#321" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#311.itm(3)} -pin  "ACC1:acc#321" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#311.itm(4)} -pin  "ACC1:acc#321" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#308.itm(1)} -pin  "ACC1:acc#321" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#308.itm(2)} -pin  "ACC1:acc#321" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#308.itm(3)} -pin  "ACC1:acc#321" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#308.itm(4)} -pin  "ACC1:acc#321" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#321.itm(0)} -pin  "ACC1:acc#321" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(1)} -pin  "ACC1:acc#321" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(2)} -pin  "ACC1:acc#321" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(3)} -pin  "ACC1:acc#321" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load inst "ACC1:acc#331" "add(6,0,4,0,7)" "INTERFACE" -attr xrf 25642 -attr oid 938 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {ACC1:acc#327.itm(0)} -pin  "ACC1:acc#331" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(1)} -pin  "ACC1:acc#331" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(2)} -pin  "ACC1:acc#331" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(3)} -pin  "ACC1:acc#331" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(4)} -pin  "ACC1:acc#331" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(5)} -pin  "ACC1:acc#331" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#321.itm(0)} -pin  "ACC1:acc#331" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(1)} -pin  "ACC1:acc#331" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(2)} -pin  "ACC1:acc#331" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(3)} -pin  "ACC1:acc#331" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#331.itm(0)} -pin  "ACC1:acc#331" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(1)} -pin  "ACC1:acc#331" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(2)} -pin  "ACC1:acc#331" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(3)} -pin  "ACC1:acc#331" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(4)} -pin  "ACC1:acc#331" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(5)} -pin  "ACC1:acc#331" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(6)} -pin  "ACC1:acc#331" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load inst "ACC1:acc#335" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 25643 -attr oid 939 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#332.itm(0)} -pin  "ACC1:acc#335" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(1)} -pin  "ACC1:acc#335" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(2)} -pin  "ACC1:acc#335" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(3)} -pin  "ACC1:acc#335" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(4)} -pin  "ACC1:acc#335" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(5)} -pin  "ACC1:acc#335" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(6)} -pin  "ACC1:acc#335" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(7)} -pin  "ACC1:acc#335" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#331.itm(0)} -pin  "ACC1:acc#335" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(1)} -pin  "ACC1:acc#335" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(2)} -pin  "ACC1:acc#335" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(3)} -pin  "ACC1:acc#335" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(4)} -pin  "ACC1:acc#335" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(5)} -pin  "ACC1:acc#335" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(6)} -pin  "ACC1:acc#335" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#335.itm(0)} -pin  "ACC1:acc#335" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(1)} -pin  "ACC1:acc#335" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(2)} -pin  "ACC1:acc#335" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(3)} -pin  "ACC1:acc#335" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(4)} -pin  "ACC1:acc#335" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(5)} -pin  "ACC1:acc#335" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(6)} -pin  "ACC1:acc#335" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(7)} -pin  "ACC1:acc#335" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load inst "ACC1:acc#338" "add(10,-1,8,0,10)" "INTERFACE" -attr xrf 25644 -attr oid 940 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11)"
+load net {ACC1:acc#336.itm(0)} -pin  "ACC1:acc#338" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(1)} -pin  "ACC1:acc#338" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(2)} -pin  "ACC1:acc#338" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(3)} -pin  "ACC1:acc#338" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(4)} -pin  "ACC1:acc#338" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(5)} -pin  "ACC1:acc#338" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(6)} -pin  "ACC1:acc#338" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(7)} -pin  "ACC1:acc#338" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(8)} -pin  "ACC1:acc#338" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(9)} -pin  "ACC1:acc#338" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#335.itm(0)} -pin  "ACC1:acc#338" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(1)} -pin  "ACC1:acc#338" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(2)} -pin  "ACC1:acc#338" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(3)} -pin  "ACC1:acc#338" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(4)} -pin  "ACC1:acc#338" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(5)} -pin  "ACC1:acc#338" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(6)} -pin  "ACC1:acc#338" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(7)} -pin  "ACC1:acc#338" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#338.itm(0)} -pin  "ACC1:acc#338" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(1)} -pin  "ACC1:acc#338" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(2)} -pin  "ACC1:acc#338" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(3)} -pin  "ACC1:acc#338" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(4)} -pin  "ACC1:acc#338" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(5)} -pin  "ACC1:acc#338" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(6)} -pin  "ACC1:acc#338" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(7)} -pin  "ACC1:acc#338" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(8)} -pin  "ACC1:acc#338" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(9)} -pin  "ACC1:acc#338" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load inst "ACC1:acc#340" "add(13,-1,10,0,13)" "INTERFACE" -attr xrf 25645 -attr oid 941 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340} -attr area 14.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,0,12,1,13)"
+load net {ACC1:mul#20.itm(0)} -pin  "ACC1:acc#340" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(1)} -pin  "ACC1:acc#340" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(2)} -pin  "ACC1:acc#340" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(3)} -pin  "ACC1:acc#340" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(4)} -pin  "ACC1:acc#340" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(5)} -pin  "ACC1:acc#340" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(6)} -pin  "ACC1:acc#340" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(7)} -pin  "ACC1:acc#340" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(8)} -pin  "ACC1:acc#340" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(9)} -pin  "ACC1:acc#340" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(10)} -pin  "ACC1:acc#340" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(11)} -pin  "ACC1:acc#340" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(12)} -pin  "ACC1:acc#340" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:acc#338.itm(0)} -pin  "ACC1:acc#340" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(1)} -pin  "ACC1:acc#340" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(2)} -pin  "ACC1:acc#340" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(3)} -pin  "ACC1:acc#340" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(4)} -pin  "ACC1:acc#340" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(5)} -pin  "ACC1:acc#340" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(6)} -pin  "ACC1:acc#340" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(7)} -pin  "ACC1:acc#340" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(8)} -pin  "ACC1:acc#340" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(9)} -pin  "ACC1:acc#340" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#340.itm(0)} -pin  "ACC1:acc#340" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(1)} -pin  "ACC1:acc#340" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(2)} -pin  "ACC1:acc#340" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(3)} -pin  "ACC1:acc#340" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(4)} -pin  "ACC1:acc#340" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(5)} -pin  "ACC1:acc#340" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(6)} -pin  "ACC1:acc#340" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(7)} -pin  "ACC1:acc#340" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(8)} -pin  "ACC1:acc#340" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(9)} -pin  "ACC1:acc#340" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(10)} -pin  "ACC1:acc#340" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(11)} -pin  "ACC1:acc#340" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(12)} -pin  "ACC1:acc#340" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load inst "ACC2:acc#4" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 25646 -attr oid 942 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#4} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(9)} -pin  "ACC2:acc#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#10.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(9)} -pin  "ACC2:acc#4" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#10.itm}
+load net {ACC2:acc#4.itm(0)} -pin  "ACC2:acc#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#4.itm}
+load net {ACC2:acc#4.itm(1)} -pin  "ACC2:acc#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#4.itm}
+load inst "ACC1:mul#19" "mul(2,0,9,0,10)" "INTERFACE" -attr xrf 25647 -attr oid 943 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC2:acc#4.itm(0)} -pin  "ACC1:mul#19" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#4.itm}
+load net {ACC2:acc#4.itm(1)} -pin  "ACC1:mul#19" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#4.itm}
+load net {PWR} -pin  "ACC1:mul#19" {B(0)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#19" {B(1)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#19" {B(2)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#19" {B(3)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#19" {B(4)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#19" {B(5)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#19" {B(6)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#19" {B(7)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#19" {B(8)} -attr @path {/sobel/sobel:core/C341_9}
+load net {ACC1:mul#19.itm(0)} -pin  "ACC1:mul#19" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(1)} -pin  "ACC1:mul#19" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(2)} -pin  "ACC1:mul#19" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(3)} -pin  "ACC1:mul#19" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(4)} -pin  "ACC1:mul#19" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(5)} -pin  "ACC1:mul#19" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(6)} -pin  "ACC1:mul#19" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(7)} -pin  "ACC1:mul#19" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(8)} -pin  "ACC1:mul#19" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(9)} -pin  "ACC1:mul#19" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load inst "ACC1:acc#347" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 25648 -attr oid 944 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347} -attr area 2.320458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} -pin  "ACC1:acc#347" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#11.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#347" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#4.itm}
+load net {ACC1:acc#347.itm(0)} -pin  "ACC1:acc#347" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load net {ACC1:acc#347.itm(1)} -pin  "ACC1:acc#347" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load inst "ACC1:acc#348" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25649 -attr oid 945 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} -pin  "ACC1:acc#348" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:exs.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} -pin  "ACC1:acc#348" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:exs.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#348" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:exs#1.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#348" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:exs#1.itm}
+load net {ACC1:acc#348.itm(0)} -pin  "ACC1:acc#348" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {ACC1:acc#348.itm(1)} -pin  "ACC1:acc#348" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {ACC1:acc#348.itm(2)} -pin  "ACC1:acc#348" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load inst "ACC1:acc#326" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 25650 -attr oid 946 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#348.itm(0)} -pin  "ACC1:acc#326" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#657.itm}
+load net {ACC1:acc#348.itm(1)} -pin  "ACC1:acc#326" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#657.itm}
+load net {ACC1:acc#348.itm(2)} -pin  "ACC1:acc#326" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#657.itm}
+load net {ACC1:acc#347.itm(0)} -pin  "ACC1:acc#326" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#657.itm}
+load net {ACC1:acc#347.itm(1)} -pin  "ACC1:acc#326" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#657.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#326" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#615.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#326" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#615.itm}
+load net {GND} -pin  "ACC1:acc#326" {B(2)} -attr @path {/sobel/sobel:core/conc#615.itm}
+load net {GND} -pin  "ACC1:acc#326" {B(3)} -attr @path {/sobel/sobel:core/conc#615.itm}
+load net {PWR} -pin  "ACC1:acc#326" {B(4)} -attr @path {/sobel/sobel:core/conc#615.itm}
+load net {ACC1:acc#326.itm(0)} -pin  "ACC1:acc#326" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(1)} -pin  "ACC1:acc#326" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(2)} -pin  "ACC1:acc#326" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(3)} -pin  "ACC1:acc#326" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(4)} -pin  "ACC1:acc#326" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load inst "ACC1:acc#329" "add(6,0,5,1,7)" "INTERFACE" -attr xrf 25651 -attr oid 947 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#329" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#329" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {GND} -pin  "ACC1:acc#329" {A(2)} -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#329" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {GND} -pin  "ACC1:acc#329" {A(4)} -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#329" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {ACC1:acc#326.itm(0)} -pin  "ACC1:acc#329" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(1)} -pin  "ACC1:acc#329" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(2)} -pin  "ACC1:acc#329" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(3)} -pin  "ACC1:acc#329" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(4)} -pin  "ACC1:acc#329" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#329.itm(0)} -pin  "ACC1:acc#329" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(1)} -pin  "ACC1:acc#329" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(2)} -pin  "ACC1:acc#329" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(3)} -pin  "ACC1:acc#329" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(4)} -pin  "ACC1:acc#329" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(5)} -pin  "ACC1:acc#329" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(6)} -pin  "ACC1:acc#329" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load inst "ACC1:acc#333" "add(7,1,7,0,9)" "INTERFACE" -attr xrf 25652 -attr oid 948 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#329.itm(0)} -pin  "ACC1:acc#333" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(1)} -pin  "ACC1:acc#333" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(2)} -pin  "ACC1:acc#333" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(3)} -pin  "ACC1:acc#333" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(4)} -pin  "ACC1:acc#333" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(5)} -pin  "ACC1:acc#333" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(6)} -pin  "ACC1:acc#333" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#333.itm(0)} -pin  "ACC1:acc#333" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(1)} -pin  "ACC1:acc#333" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(2)} -pin  "ACC1:acc#333" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(3)} -pin  "ACC1:acc#333" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(4)} -pin  "ACC1:acc#333" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(5)} -pin  "ACC1:acc#333" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(6)} -pin  "ACC1:acc#333" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(7)} -pin  "ACC1:acc#333" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(8)} -pin  "ACC1:acc#333" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load inst "ACC1:acc#337" "add(10,0,9,1,11)" "INTERFACE" -attr xrf 25653 -attr oid 949 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11)"
+load net {ACC1:mul#19.itm(0)} -pin  "ACC1:acc#337" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(1)} -pin  "ACC1:acc#337" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(2)} -pin  "ACC1:acc#337" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(3)} -pin  "ACC1:acc#337" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(4)} -pin  "ACC1:acc#337" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(5)} -pin  "ACC1:acc#337" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(6)} -pin  "ACC1:acc#337" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(7)} -pin  "ACC1:acc#337" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(8)} -pin  "ACC1:acc#337" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(9)} -pin  "ACC1:acc#337" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:acc#333.itm(0)} -pin  "ACC1:acc#337" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(1)} -pin  "ACC1:acc#337" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(2)} -pin  "ACC1:acc#337" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(3)} -pin  "ACC1:acc#337" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(4)} -pin  "ACC1:acc#337" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(5)} -pin  "ACC1:acc#337" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(6)} -pin  "ACC1:acc#337" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(7)} -pin  "ACC1:acc#337" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(8)} -pin  "ACC1:acc#337" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#337.itm(0)} -pin  "ACC1:acc#337" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(1)} -pin  "ACC1:acc#337" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(2)} -pin  "ACC1:acc#337" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(3)} -pin  "ACC1:acc#337" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(4)} -pin  "ACC1:acc#337" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(5)} -pin  "ACC1:acc#337" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(6)} -pin  "ACC1:acc#337" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(7)} -pin  "ACC1:acc#337" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(8)} -pin  "ACC1:acc#337" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(9)} -pin  "ACC1:acc#337" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(10)} -pin  "ACC1:acc#337" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load inst "ACC2:acc#7" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 25654 -attr oid 950 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} -pin  "ACC2:acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#13.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} -pin  "ACC2:acc#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#5.itm}
+load net {ACC2:acc#7.itm(0)} -pin  "ACC2:acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(1)} -pin  "ACC2:acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load inst "ACC1:mul#22" "mul(2,0,7,0,8)" "INTERFACE" -attr xrf 25655 -attr oid 951 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC2:acc#7.itm(0)} -pin  "ACC1:mul#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(1)} -pin  "ACC1:mul#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {PWR} -pin  "ACC1:mul#22" {B(0)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#22" {B(1)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#22" {B(2)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#22" {B(3)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#22" {B(4)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#22" {B(5)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#22" {B(6)} -attr @path {/sobel/sobel:core/C85_7}
+load net {ACC1:mul#22.itm(0)} -pin  "ACC1:mul#22" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(1)} -pin  "ACC1:mul#22" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(2)} -pin  "ACC1:mul#22" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(3)} -pin  "ACC1:mul#22" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(4)} -pin  "ACC1:mul#22" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(5)} -pin  "ACC1:mul#22" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(6)} -pin  "ACC1:mul#22" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(7)} -pin  "ACC1:mul#22" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load inst "ACC1:acc#339" "add(11,1,11,0,13)" "INTERFACE" -attr xrf 25656 -attr oid 952 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13)"
+load net {ACC1:acc#337.itm(0)} -pin  "ACC1:acc#339" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(1)} -pin  "ACC1:acc#339" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(2)} -pin  "ACC1:acc#339" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(3)} -pin  "ACC1:acc#339" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(4)} -pin  "ACC1:acc#339" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(5)} -pin  "ACC1:acc#339" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(6)} -pin  "ACC1:acc#339" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(7)} -pin  "ACC1:acc#339" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(8)} -pin  "ACC1:acc#339" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(9)} -pin  "ACC1:acc#339" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(10)} -pin  "ACC1:acc#339" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#339" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#339" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(3)} -pin  "ACC1:acc#339" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(0)} -pin  "ACC1:acc#339" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(1)} -pin  "ACC1:acc#339" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(2)} -pin  "ACC1:acc#339" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(3)} -pin  "ACC1:acc#339" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(4)} -pin  "ACC1:acc#339" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(5)} -pin  "ACC1:acc#339" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(6)} -pin  "ACC1:acc#339" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(7)} -pin  "ACC1:acc#339" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:acc#339.itm(0)} -pin  "ACC1:acc#339" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(1)} -pin  "ACC1:acc#339" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(2)} -pin  "ACC1:acc#339" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(3)} -pin  "ACC1:acc#339" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(4)} -pin  "ACC1:acc#339" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(5)} -pin  "ACC1:acc#339" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(6)} -pin  "ACC1:acc#339" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(7)} -pin  "ACC1:acc#339" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(8)} -pin  "ACC1:acc#339" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(9)} -pin  "ACC1:acc#339" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(10)} -pin  "ACC1:acc#339" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(11)} -pin  "ACC1:acc#339" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(12)} -pin  "ACC1:acc#339" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load inst "ACC1:acc#341" "add(13,-1,13,-1,13)" "INTERFACE" -attr xrf 25657 -attr oid 953 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341} -attr area 14.215154 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,0,13,0,13)"
+load net {ACC1:acc#340.itm(0)} -pin  "ACC1:acc#341" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(1)} -pin  "ACC1:acc#341" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(2)} -pin  "ACC1:acc#341" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(3)} -pin  "ACC1:acc#341" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(4)} -pin  "ACC1:acc#341" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(5)} -pin  "ACC1:acc#341" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(6)} -pin  "ACC1:acc#341" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(7)} -pin  "ACC1:acc#341" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(8)} -pin  "ACC1:acc#341" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(9)} -pin  "ACC1:acc#341" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(10)} -pin  "ACC1:acc#341" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(11)} -pin  "ACC1:acc#341" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(12)} -pin  "ACC1:acc#341" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#339.itm(0)} -pin  "ACC1:acc#341" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(1)} -pin  "ACC1:acc#341" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(2)} -pin  "ACC1:acc#341" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(3)} -pin  "ACC1:acc#341" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(4)} -pin  "ACC1:acc#341" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(5)} -pin  "ACC1:acc#341" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(6)} -pin  "ACC1:acc#341" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(7)} -pin  "ACC1:acc#341" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(8)} -pin  "ACC1:acc#341" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(9)} -pin  "ACC1:acc#341" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(10)} -pin  "ACC1:acc#341" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(11)} -pin  "ACC1:acc#341" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(12)} -pin  "ACC1:acc#341" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#341.itm(0)} -pin  "ACC1:acc#341" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(1)} -pin  "ACC1:acc#341" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(2)} -pin  "ACC1:acc#341" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(3)} -pin  "ACC1:acc#341" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(4)} -pin  "ACC1:acc#341" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(5)} -pin  "ACC1:acc#341" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(6)} -pin  "ACC1:acc#341" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(7)} -pin  "ACC1:acc#341" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(8)} -pin  "ACC1:acc#341" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(9)} -pin  "ACC1:acc#341" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(10)} -pin  "ACC1:acc#341" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(11)} -pin  "ACC1:acc#341" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(12)} -pin  "ACC1:acc#341" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load inst "reg(ACC1:acc#341.itm#1)" "reg(13,1,1,-1,0)" "INTERFACE" -attr xrf 25658 -attr oid 954 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#341.itm#1)}
+load net {ACC1:acc#341.itm(0)} -pin  "reg(ACC1:acc#341.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(1)} -pin  "reg(ACC1:acc#341.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(2)} -pin  "reg(ACC1:acc#341.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(3)} -pin  "reg(ACC1:acc#341.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(4)} -pin  "reg(ACC1:acc#341.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(5)} -pin  "reg(ACC1:acc#341.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(6)} -pin  "reg(ACC1:acc#341.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(7)} -pin  "reg(ACC1:acc#341.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(8)} -pin  "reg(ACC1:acc#341.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(9)} -pin  "reg(ACC1:acc#341.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(10)} -pin  "reg(ACC1:acc#341.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(11)} -pin  "reg(ACC1:acc#341.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(12)} -pin  "reg(ACC1:acc#341.itm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_13}
+load net {clk} -pin  "reg(ACC1:acc#341.itm#1)" {clk} -attr xrf 25659 -attr oid 955 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#341.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#341.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#341.itm#1(0)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(1)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(2)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(3)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(4)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(5)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(6)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(7)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(8)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(9)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(10)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(11)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(12)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load inst "mux#2" "mux(2,16)" "INTERFACE" -attr xrf 25660 -attr oid 956 -attr vt d -attr @path {/sobel/sobel:core/mux#2} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {in(0).sva#3(0)} -pin  "mux#2" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(1)} -pin  "mux#2" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(2)} -pin  "mux#2" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(3)} -pin  "mux#2" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(4)} -pin  "mux#2" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(5)} -pin  "mux#2" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(6)} -pin  "mux#2" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(7)} -pin  "mux#2" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(8)} -pin  "mux#2" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(9)} -pin  "mux#2" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(10)} -pin  "mux#2" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(11)} -pin  "mux#2" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(12)} -pin  "mux#2" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(13)} -pin  "mux#2" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(14)} -pin  "mux#2" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(15)} -pin  "mux#2" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#1(0)} -pin  "mux#2" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(1)} -pin  "mux#2" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(2)} -pin  "mux#2" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(3)} -pin  "mux#2" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(4)} -pin  "mux#2" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(5)} -pin  "mux#2" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(6)} -pin  "mux#2" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(7)} -pin  "mux#2" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(8)} -pin  "mux#2" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(9)} -pin  "mux#2" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(10)} -pin  "mux#2" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(11)} -pin  "mux#2" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(12)} -pin  "mux#2" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(13)} -pin  "mux#2" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(14)} -pin  "mux#2" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(15)} -pin  "mux#2" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {main.stage_0#2} -pin  "mux#2" {S(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {mux#2.itm(0)} -pin  "mux#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(1)} -pin  "mux#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(2)} -pin  "mux#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(3)} -pin  "mux#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(4)} -pin  "mux#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(5)} -pin  "mux#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(6)} -pin  "mux#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(7)} -pin  "mux#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(8)} -pin  "mux#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(9)} -pin  "mux#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(10)} -pin  "mux#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(11)} -pin  "mux#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(12)} -pin  "mux#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(13)} -pin  "mux#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(14)} -pin  "mux#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(15)} -pin  "mux#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load inst "reg(in(0).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 25661 -attr oid 957 -attr vt d -attr @path {/sobel/sobel:core/reg(in(0).sva#1)}
+load net {mux#2.itm(0)} -pin  "reg(in(0).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(1)} -pin  "reg(in(0).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(2)} -pin  "reg(in(0).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(3)} -pin  "reg(in(0).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(4)} -pin  "reg(in(0).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(5)} -pin  "reg(in(0).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(6)} -pin  "reg(in(0).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(7)} -pin  "reg(in(0).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(8)} -pin  "reg(in(0).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(9)} -pin  "reg(in(0).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(10)} -pin  "reg(in(0).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(11)} -pin  "reg(in(0).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(12)} -pin  "reg(in(0).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(13)} -pin  "reg(in(0).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(14)} -pin  "reg(in(0).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(15)} -pin  "reg(in(0).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(in(0).sva#1)" {clk} -attr xrf 25662 -attr oid 958 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(in(0).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(in(0).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {in(0).sva#1(0)} -pin  "reg(in(0).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(1)} -pin  "reg(in(0).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(2)} -pin  "reg(in(0).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(3)} -pin  "reg(in(0).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(4)} -pin  "reg(in(0).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(5)} -pin  "reg(in(0).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(6)} -pin  "reg(in(0).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(7)} -pin  "reg(in(0).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(8)} -pin  "reg(in(0).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(9)} -pin  "reg(in(0).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(10)} -pin  "reg(in(0).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(11)} -pin  "reg(in(0).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(12)} -pin  "reg(in(0).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(13)} -pin  "reg(in(0).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(14)} -pin  "reg(in(0).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(15)} -pin  "reg(in(0).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load inst "FRAME:for:not#7" "not(1)" "INTERFACE" -attr xrf 25663 -attr oid 959 -attr @path {/sobel/sobel:core/FRAME:for:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:not#7" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#3.itm}
+load net {FRAME:for:not#7.itm} -pin  "FRAME:for:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#7.itm}
+load inst "reg(exit:FRAME:for.sva#1.st#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 25664 -attr oid 960 -attr @path {/sobel/sobel:core/reg(exit:FRAME:for.sva#1.st#1)}
+load net {FRAME:for:not#7.itm} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#7.itm}
+load net {GND} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {clk} -attr xrf 25665 -attr oid 961 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for.sva#1.st#1} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load inst "regs.operator[]#16:mux" "mux(4,10)" "INTERFACE" -attr xrf 25666 -attr oid 962 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(10)} -pin  "regs.operator[]#16:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(11)} -pin  "regs.operator[]#16:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(12)} -pin  "regs.operator[]#16:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(13)} -pin  "regs.operator[]#16:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(14)} -pin  "regs.operator[]#16:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(15)} -pin  "regs.operator[]#16:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(16)} -pin  "regs.operator[]#16:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(17)} -pin  "regs.operator[]#16:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(18)} -pin  "regs.operator[]#16:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(19)} -pin  "regs.operator[]#16:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "regs.operator[]#16:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "regs.operator[]#16:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "regs.operator[]#16:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "regs.operator[]#16:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "regs.operator[]#16:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "regs.operator[]#16:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "regs.operator[]#16:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "regs.operator[]#16:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "regs.operator[]#16:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "regs.operator[]#16:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "regs.operator[]#16:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "regs.operator[]#16:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "regs.operator[]#16:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "regs.operator[]#16:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "regs.operator[]#16:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "regs.operator[]#16:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "regs.operator[]#16:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "regs.operator[]#16:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "regs.operator[]#16:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "regs.operator[]#16:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#16:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#16:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#16:mux.itm(0)} -pin  "regs.operator[]#16:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(1)} -pin  "regs.operator[]#16:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(2)} -pin  "regs.operator[]#16:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(3)} -pin  "regs.operator[]#16:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(4)} -pin  "regs.operator[]#16:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(5)} -pin  "regs.operator[]#16:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(6)} -pin  "regs.operator[]#16:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(7)} -pin  "regs.operator[]#16:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(8)} -pin  "regs.operator[]#16:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(9)} -pin  "regs.operator[]#16:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load inst "FRAME:for:mul#7" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 25667 -attr oid 963 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#16:mux.itm(0)} -pin  "FRAME:for:mul#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(1)} -pin  "FRAME:for:mul#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(2)} -pin  "FRAME:for:mul#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(3)} -pin  "FRAME:for:mul#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(4)} -pin  "FRAME:for:mul#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(5)} -pin  "FRAME:for:mul#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(6)} -pin  "FRAME:for:mul#7" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(7)} -pin  "FRAME:for:mul#7" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(8)} -pin  "FRAME:for:mul#7" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(9)} -pin  "FRAME:for:mul#7" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:mul#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:mul#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:mul#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:mul#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:mul#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:mul#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:mul#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:mul#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:mul#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:mul#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:mul#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load inst "regs.operator[]#17:mux" "mux(4,10)" "INTERFACE" -attr xrf 25668 -attr oid 964 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(0)} -pin  "regs.operator[]#17:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(1)} -pin  "regs.operator[]#17:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(2)} -pin  "regs.operator[]#17:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(3)} -pin  "regs.operator[]#17:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(4)} -pin  "regs.operator[]#17:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(5)} -pin  "regs.operator[]#17:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(6)} -pin  "regs.operator[]#17:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(7)} -pin  "regs.operator[]#17:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(8)} -pin  "regs.operator[]#17:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(9)} -pin  "regs.operator[]#17:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "regs.operator[]#17:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "regs.operator[]#17:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "regs.operator[]#17:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "regs.operator[]#17:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "regs.operator[]#17:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "regs.operator[]#17:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "regs.operator[]#17:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "regs.operator[]#17:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "regs.operator[]#17:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "regs.operator[]#17:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "regs.operator[]#17:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "regs.operator[]#17:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "regs.operator[]#17:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "regs.operator[]#17:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "regs.operator[]#17:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "regs.operator[]#17:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "regs.operator[]#17:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "regs.operator[]#17:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "regs.operator[]#17:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "regs.operator[]#17:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#17:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#17:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#17:mux.itm(0)} -pin  "regs.operator[]#17:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(1)} -pin  "regs.operator[]#17:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(2)} -pin  "regs.operator[]#17:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(3)} -pin  "regs.operator[]#17:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(4)} -pin  "regs.operator[]#17:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(5)} -pin  "regs.operator[]#17:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(6)} -pin  "regs.operator[]#17:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(7)} -pin  "regs.operator[]#17:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(8)} -pin  "regs.operator[]#17:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(9)} -pin  "regs.operator[]#17:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load inst "FRAME:for:mul#8" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 25669 -attr oid 965 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#17:mux.itm(0)} -pin  "FRAME:for:mul#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(1)} -pin  "FRAME:for:mul#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(2)} -pin  "FRAME:for:mul#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(3)} -pin  "FRAME:for:mul#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(4)} -pin  "FRAME:for:mul#8" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(5)} -pin  "FRAME:for:mul#8" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(6)} -pin  "FRAME:for:mul#8" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(7)} -pin  "FRAME:for:mul#8" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(8)} -pin  "FRAME:for:mul#8" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(9)} -pin  "FRAME:for:mul#8" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:mul#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:mul#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:mul#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:mul#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:mul#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:mul#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:mul#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:mul#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:mul#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:mul#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:mul#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load inst "FRAME:for:acc#25" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 25670 -attr oid 966 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:acc#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:acc#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:acc#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:acc#25" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:acc#25" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:acc#25" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:acc#25" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:acc#25" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:acc#25" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:acc#25" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:acc#25" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:acc#25" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:acc#25" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:acc#25" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:acc#25" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:acc#25" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:acc#25" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:acc#25" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:acc#25" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:acc#25" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:acc#25" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:acc#25" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:acc#25.itm(0)} -pin  "FRAME:for:acc#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(1)} -pin  "FRAME:for:acc#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(2)} -pin  "FRAME:for:acc#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(3)} -pin  "FRAME:for:acc#25" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(4)} -pin  "FRAME:for:acc#25" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(5)} -pin  "FRAME:for:acc#25" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(6)} -pin  "FRAME:for:acc#25" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(7)} -pin  "FRAME:for:acc#25" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(8)} -pin  "FRAME:for:acc#25" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(9)} -pin  "FRAME:for:acc#25" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(10)} -pin  "FRAME:for:acc#25" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(11)} -pin  "FRAME:for:acc#25" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load inst "regs.operator[]#15:mux" "mux(4,10)" "INTERFACE" -attr xrf 25671 -attr oid 967 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(20)} -pin  "regs.operator[]#15:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(21)} -pin  "regs.operator[]#15:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(22)} -pin  "regs.operator[]#15:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(23)} -pin  "regs.operator[]#15:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(24)} -pin  "regs.operator[]#15:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(25)} -pin  "regs.operator[]#15:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(26)} -pin  "regs.operator[]#15:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(27)} -pin  "regs.operator[]#15:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(28)} -pin  "regs.operator[]#15:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(29)} -pin  "regs.operator[]#15:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "regs.operator[]#15:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "regs.operator[]#15:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "regs.operator[]#15:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "regs.operator[]#15:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "regs.operator[]#15:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "regs.operator[]#15:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "regs.operator[]#15:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "regs.operator[]#15:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "regs.operator[]#15:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "regs.operator[]#15:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "regs.operator[]#15:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "regs.operator[]#15:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "regs.operator[]#15:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "regs.operator[]#15:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "regs.operator[]#15:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "regs.operator[]#15:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "regs.operator[]#15:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "regs.operator[]#15:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "regs.operator[]#15:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "regs.operator[]#15:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#15:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#15:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#15:mux.itm(0)} -pin  "regs.operator[]#15:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(1)} -pin  "regs.operator[]#15:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(2)} -pin  "regs.operator[]#15:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(3)} -pin  "regs.operator[]#15:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(4)} -pin  "regs.operator[]#15:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(5)} -pin  "regs.operator[]#15:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(6)} -pin  "regs.operator[]#15:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(7)} -pin  "regs.operator[]#15:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(8)} -pin  "regs.operator[]#15:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(9)} -pin  "regs.operator[]#15:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load inst "FRAME:for:mul#6" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 25672 -attr oid 968 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#15:mux.itm(0)} -pin  "FRAME:for:mul#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(1)} -pin  "FRAME:for:mul#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(2)} -pin  "FRAME:for:mul#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(3)} -pin  "FRAME:for:mul#6" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(4)} -pin  "FRAME:for:mul#6" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(5)} -pin  "FRAME:for:mul#6" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(6)} -pin  "FRAME:for:mul#6" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(7)} -pin  "FRAME:for:mul#6" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(8)} -pin  "FRAME:for:mul#6" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(9)} -pin  "FRAME:for:mul#6" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:mul#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:mul#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:mul#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:mul#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:mul#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:mul#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:mul#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:mul#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:mul#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:mul#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:mul#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load inst "FRAME:for:acc#26" "add(12,-1,11,1,12)" "INTERFACE" -attr xrf 25673 -attr oid 969 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {FRAME:for:acc#25.itm(0)} -pin  "FRAME:for:acc#26" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(1)} -pin  "FRAME:for:acc#26" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(2)} -pin  "FRAME:for:acc#26" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(3)} -pin  "FRAME:for:acc#26" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(4)} -pin  "FRAME:for:acc#26" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(5)} -pin  "FRAME:for:acc#26" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(6)} -pin  "FRAME:for:acc#26" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(7)} -pin  "FRAME:for:acc#26" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(8)} -pin  "FRAME:for:acc#26" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(9)} -pin  "FRAME:for:acc#26" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(10)} -pin  "FRAME:for:acc#26" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(11)} -pin  "FRAME:for:acc#26" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:acc#26" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:acc#26" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:acc#26" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:acc#26" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:acc#26" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:acc#26" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:acc#26" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:acc#26" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:acc#26" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:acc#26" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:acc#26" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:acc#26.itm(0)} -pin  "FRAME:for:acc#26" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(1)} -pin  "FRAME:for:acc#26" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(2)} -pin  "FRAME:for:acc#26" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(3)} -pin  "FRAME:for:acc#26" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(4)} -pin  "FRAME:for:acc#26" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(5)} -pin  "FRAME:for:acc#26" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(6)} -pin  "FRAME:for:acc#26" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(7)} -pin  "FRAME:for:acc#26" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(8)} -pin  "FRAME:for:acc#26" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(9)} -pin  "FRAME:for:acc#26" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(10)} -pin  "FRAME:for:acc#26" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(11)} -pin  "FRAME:for:acc#26" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load inst "reg(FRAME:for:acc#26.itm#1)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 25674 -attr oid 970 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:for:acc#26.itm#1)}
+load net {FRAME:for:acc#26.itm(0)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(1)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(2)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(3)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(4)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(5)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(6)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(7)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(8)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(9)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(10)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(11)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(FRAME:for:acc#26.itm#1)" {clk} -attr xrf 25675 -attr oid 971 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:for:acc#26.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:for:acc#26.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:for:acc#26.itm#1(0)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(1)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(2)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(3)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(4)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(5)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(6)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(7)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(8)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(9)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(10)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(11)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load inst "ACC1:acc#242" "add(3,1,2,1,4)" "INTERFACE" -attr xrf 25676 -attr oid 972 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#242" {A(0)} -attr @path {/sobel/sobel:core/conc#617.itm}
+load net {acc#10.psp#1.sva(3)} -pin  "ACC1:acc#242" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#617.itm}
+load net {PWR} -pin  "ACC1:acc#242" {A(2)} -attr @path {/sobel/sobel:core/conc#617.itm}
+load net {acc#10.psp#1.sva(4)} -pin  "ACC1:acc#242" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#582.itm}
+load net {ACC1:acc#113.psp#1.sva(3)} -pin  "ACC1:acc#242" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#582.itm}
+load net {ACC1:acc#242.itm(0)} -pin  "ACC1:acc#242" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#242.itm(1)} -pin  "ACC1:acc#242" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#242.itm(2)} -pin  "ACC1:acc#242" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#242.itm(3)} -pin  "ACC1:acc#242" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load inst "ACC1:acc#251" "add(3,-1,2,1,3)" "INTERFACE" -attr xrf 25677 -attr oid 973 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {ACC1:acc#242.itm(1)} -pin  "ACC1:acc#251" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#68.itm}
+load net {ACC1:acc#242.itm(2)} -pin  "ACC1:acc#251" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#68.itm}
+load net {ACC1:acc#242.itm(3)} -pin  "ACC1:acc#251" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#68.itm}
+load net {ACC1:acc#120.psp.sva(1)} -pin  "ACC1:acc#251" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp.sva)#2.itm}
+load net {ACC1:acc#120.psp.sva(2)} -pin  "ACC1:acc#251" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp.sva)#2.itm}
+load net {ACC1:acc#251.itm(0)} -pin  "ACC1:acc#251" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(1)} -pin  "ACC1:acc#251" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(2)} -pin  "ACC1:acc#251" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load inst "ACC1:acc#243" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 25678 -attr oid 974 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#243" {A(0)} -attr @path {/sobel/sobel:core/conc#618.itm}
+load net {acc#10.psp#1.sva(1)} -pin  "ACC1:acc#243" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#618.itm}
+load net {acc#10.psp#1.sva(3)} -pin  "ACC1:acc#243" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#618.itm}
+load net {ACC1:acc#113.psp#1.sva(1)} -pin  "ACC1:acc#243" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#584.itm}
+load net {acc#10.psp#1.sva(2)} -pin  "ACC1:acc#243" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#584.itm}
+load net {ACC1:acc#113.psp#1.sva(3)} -pin  "ACC1:acc#243" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#584.itm}
+load net {ACC1:acc#243.itm(0)} -pin  "ACC1:acc#243" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(1)} -pin  "ACC1:acc#243" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(2)} -pin  "ACC1:acc#243" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(3)} -pin  "ACC1:acc#243" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(4)} -pin  "ACC1:acc#243" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load inst "ACC1:acc#256" "add(3,1,4,-1,4)" "INTERFACE" -attr xrf 25679 -attr oid 975 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#251.itm(0)} -pin  "ACC1:acc#256" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(1)} -pin  "ACC1:acc#256" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(2)} -pin  "ACC1:acc#256" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#243.itm(1)} -pin  "ACC1:acc#256" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#69.itm}
+load net {ACC1:acc#243.itm(2)} -pin  "ACC1:acc#256" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#69.itm}
+load net {ACC1:acc#243.itm(3)} -pin  "ACC1:acc#256" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#69.itm}
+load net {ACC1:acc#243.itm(4)} -pin  "ACC1:acc#256" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#69.itm}
+load net {ACC1:acc#256.itm(0)} -pin  "ACC1:acc#256" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(1)} -pin  "ACC1:acc#256" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(2)} -pin  "ACC1:acc#256" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(3)} -pin  "ACC1:acc#256" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load inst "ACC1:acc#255" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 25680 -attr oid 976 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#255" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#284.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#255" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#284.itm}
+load net {acc#10.psp#1.sva(4)} -pin  "ACC1:acc#255" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#284.itm}
+load net {acc#10.psp#1.sva(7)} -pin  "ACC1:acc#255" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#284.itm}
+load net {ACC1:acc#250.cse(0)} -pin  "ACC1:acc#255" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#250.cse(1)} -pin  "ACC1:acc#255" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#250.cse(2)} -pin  "ACC1:acc#255" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#255.itm(0)} -pin  "ACC1:acc#255" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(1)} -pin  "ACC1:acc#255" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(2)} -pin  "ACC1:acc#255" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(3)} -pin  "ACC1:acc#255" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(4)} -pin  "ACC1:acc#255" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load inst "ACC1:acc#259" "add(4,1,5,0,6)" "INTERFACE" -attr xrf 25681 -attr oid 977 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#256.itm(0)} -pin  "ACC1:acc#259" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(1)} -pin  "ACC1:acc#259" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(2)} -pin  "ACC1:acc#259" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(3)} -pin  "ACC1:acc#259" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#255.itm(0)} -pin  "ACC1:acc#259" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(1)} -pin  "ACC1:acc#259" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(2)} -pin  "ACC1:acc#259" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(3)} -pin  "ACC1:acc#259" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(4)} -pin  "ACC1:acc#259" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#259.itm(0)} -pin  "ACC1:acc#259" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(1)} -pin  "ACC1:acc#259" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(2)} -pin  "ACC1:acc#259" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(3)} -pin  "ACC1:acc#259" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(4)} -pin  "ACC1:acc#259" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(5)} -pin  "ACC1:acc#259" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load inst "ACC1:acc#262" "add(6,1,7,0,8)" "INTERFACE" -attr xrf 25682 -attr oid 978 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#259.itm(0)} -pin  "ACC1:acc#262" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(1)} -pin  "ACC1:acc#262" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(2)} -pin  "ACC1:acc#262" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(3)} -pin  "ACC1:acc#262" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(4)} -pin  "ACC1:acc#262" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(5)} -pin  "ACC1:acc#262" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {acc#10.psp#1.sva(8)} -pin  "ACC1:acc#262" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {GND} -pin  "ACC1:acc#262" {B(1)} -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {acc#10.psp#1.sva(8)} -pin  "ACC1:acc#262" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {GND} -pin  "ACC1:acc#262" {B(3)} -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {acc#10.psp#1.sva(8)} -pin  "ACC1:acc#262" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {GND} -pin  "ACC1:acc#262" {B(5)} -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {acc#10.psp#1.sva(8)} -pin  "ACC1:acc#262" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {ACC1:acc#262.itm(0)} -pin  "ACC1:acc#262" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(1)} -pin  "ACC1:acc#262" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(2)} -pin  "ACC1:acc#262" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(3)} -pin  "ACC1:acc#262" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(4)} -pin  "ACC1:acc#262" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(5)} -pin  "ACC1:acc#262" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(6)} -pin  "ACC1:acc#262" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(7)} -pin  "ACC1:acc#262" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load inst "ACC1-3:not#92" "not(1)" "INTERFACE" -attr xrf 25683 -attr oid 979 -attr @path {/sobel/sobel:core/ACC1-3:not#92} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#188.itm(2)} -pin  "ACC1-3:not#92" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#2.itm}
+load net {ACC1-3:not#92.itm} -pin  "ACC1-3:not#92" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#92.itm}
+load inst "ACC1-3:and#5" "and(3,1)" "INTERFACE" -attr xrf 25684 -attr oid 980 -attr @path {/sobel/sobel:core/ACC1-3:and#5} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1-3:and#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#38.itm}
+load net {ACC1-3:not#92.itm} -pin  "ACC1-3:and#5" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#92.itm}
+load net {ACC1:acc#188.itm(1)} -pin  "ACC1-3:and#5" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#1.itm}
+load net {ACC1-3:and#5.itm} -pin  "ACC1-3:and#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#5.itm}
+load inst "ACC1:acc#248" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25685 -attr oid 981 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#248" {A(0)} -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {acc#10.psp#1.sva(7)} -pin  "ACC1:acc#248" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {acc#10.psp#1.sva(7)} -pin  "ACC1:acc#248" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {ACC1-3:and#5.itm} -pin  "ACC1:acc#248" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#772.itm}
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1:acc#248" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#772.itm}
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1:acc#248" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#772.itm}
+load net {ACC1:acc#248.itm(0)} -pin  "ACC1:acc#248" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(1)} -pin  "ACC1:acc#248" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(2)} -pin  "ACC1:acc#248" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(3)} -pin  "ACC1:acc#248" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load inst "ACC1:acc#254" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25686 -attr oid 982 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#250.cse(0)} -pin  "ACC1:acc#254" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#250.cse(1)} -pin  "ACC1:acc#254" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#250.cse(2)} -pin  "ACC1:acc#254" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#248.itm(1)} -pin  "ACC1:acc#254" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:acc#248.itm(2)} -pin  "ACC1:acc#254" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:acc#248.itm(3)} -pin  "ACC1:acc#254" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:acc#254.itm(0)} -pin  "ACC1:acc#254" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(1)} -pin  "ACC1:acc#254" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(2)} -pin  "ACC1:acc#254" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(3)} -pin  "ACC1:acc#254" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load inst "ACC1:acc#258" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 25687 -attr oid 983 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {acc#10.psp#1.sva(6)} -pin  "ACC1:acc#258" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#620.itm}
+load net {GND} -pin  "ACC1:acc#258" {A(1)} -attr @path {/sobel/sobel:core/conc#620.itm}
+load net {acc#10.psp#1.sva(6)} -pin  "ACC1:acc#258" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#620.itm}
+load net {GND} -pin  "ACC1:acc#258" {A(3)} -attr @path {/sobel/sobel:core/conc#620.itm}
+load net {acc#10.psp#1.sva(6)} -pin  "ACC1:acc#258" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#620.itm}
+load net {ACC1:acc#254.itm(0)} -pin  "ACC1:acc#258" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(1)} -pin  "ACC1:acc#258" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(2)} -pin  "ACC1:acc#258" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(3)} -pin  "ACC1:acc#258" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#258.itm(0)} -pin  "ACC1:acc#258" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(1)} -pin  "ACC1:acc#258" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(2)} -pin  "ACC1:acc#258" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(3)} -pin  "ACC1:acc#258" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(4)} -pin  "ACC1:acc#258" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(5)} -pin  "ACC1:acc#258" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load inst "ACC1:acc#261" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 25688 -attr oid 984 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {ACC1:acc#258.itm(0)} -pin  "ACC1:acc#261" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(1)} -pin  "ACC1:acc#261" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(2)} -pin  "ACC1:acc#261" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(3)} -pin  "ACC1:acc#261" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(4)} -pin  "ACC1:acc#261" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(5)} -pin  "ACC1:acc#261" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#261.itm(0)} -pin  "ACC1:acc#261" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(1)} -pin  "ACC1:acc#261" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(2)} -pin  "ACC1:acc#261" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(3)} -pin  "ACC1:acc#261" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(4)} -pin  "ACC1:acc#261" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(5)} -pin  "ACC1:acc#261" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(6)} -pin  "ACC1:acc#261" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(7)} -pin  "ACC1:acc#261" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load inst "ACC1:acc#264" "add(8,1,8,0,10)" "INTERFACE" -attr xrf 25689 -attr oid 985 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#262.itm(0)} -pin  "ACC1:acc#264" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(1)} -pin  "ACC1:acc#264" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(2)} -pin  "ACC1:acc#264" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(3)} -pin  "ACC1:acc#264" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(4)} -pin  "ACC1:acc#264" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(5)} -pin  "ACC1:acc#264" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(6)} -pin  "ACC1:acc#264" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(7)} -pin  "ACC1:acc#264" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#261.itm(0)} -pin  "ACC1:acc#264" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(1)} -pin  "ACC1:acc#264" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(2)} -pin  "ACC1:acc#264" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(3)} -pin  "ACC1:acc#264" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(4)} -pin  "ACC1:acc#264" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(5)} -pin  "ACC1:acc#264" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(6)} -pin  "ACC1:acc#264" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(7)} -pin  "ACC1:acc#264" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#264.itm(0)} -pin  "ACC1:acc#264" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(1)} -pin  "ACC1:acc#264" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(2)} -pin  "ACC1:acc#264" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(3)} -pin  "ACC1:acc#264" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(4)} -pin  "ACC1:acc#264" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(5)} -pin  "ACC1:acc#264" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(6)} -pin  "ACC1:acc#264" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(7)} -pin  "ACC1:acc#264" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(8)} -pin  "ACC1:acc#264" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(9)} -pin  "ACC1:acc#264" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load inst "ACC1:acc#266" "add(10,1,10,0,11)" "INTERFACE" -attr xrf 25690 -attr oid 986 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11)"
+load net {ACC1:acc#264.itm(0)} -pin  "ACC1:acc#266" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(1)} -pin  "ACC1:acc#266" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(2)} -pin  "ACC1:acc#266" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(3)} -pin  "ACC1:acc#266" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(4)} -pin  "ACC1:acc#266" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(5)} -pin  "ACC1:acc#266" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(6)} -pin  "ACC1:acc#266" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(7)} -pin  "ACC1:acc#266" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(8)} -pin  "ACC1:acc#266" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(9)} -pin  "ACC1:acc#266" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#266" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#266" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {GND} -pin  "ACC1:acc#266" {B(2)} -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#266" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {GND} -pin  "ACC1:acc#266" {B(4)} -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#266" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {GND} -pin  "ACC1:acc#266" {B(6)} -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#266" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {GND} -pin  "ACC1:acc#266" {B(8)} -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#266" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {ACC1:acc#266.itm(0)} -pin  "ACC1:acc#266" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(1)} -pin  "ACC1:acc#266" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(2)} -pin  "ACC1:acc#266" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(3)} -pin  "ACC1:acc#266" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(4)} -pin  "ACC1:acc#266" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(5)} -pin  "ACC1:acc#266" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(6)} -pin  "ACC1:acc#266" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(7)} -pin  "ACC1:acc#266" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(8)} -pin  "ACC1:acc#266" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(9)} -pin  "ACC1:acc#266" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(10)} -pin  "ACC1:acc#266" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load inst "ACC1:acc#268" "add(10,0,11,-1,11)" "INTERFACE" -attr xrf 25691 -attr oid 987 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268} -attr area 12.237292 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,0,11)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#268" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(1)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(2)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(3)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(4)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(5)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(6)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(7)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(8)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#268" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {ACC1:acc#266.itm(0)} -pin  "ACC1:acc#268" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(1)} -pin  "ACC1:acc#268" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(2)} -pin  "ACC1:acc#268" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(3)} -pin  "ACC1:acc#268" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(4)} -pin  "ACC1:acc#268" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(5)} -pin  "ACC1:acc#268" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(6)} -pin  "ACC1:acc#268" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(7)} -pin  "ACC1:acc#268" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(8)} -pin  "ACC1:acc#268" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(9)} -pin  "ACC1:acc#268" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(10)} -pin  "ACC1:acc#268" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#268.itm(0)} -pin  "ACC1:acc#268" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(1)} -pin  "ACC1:acc#268" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(2)} -pin  "ACC1:acc#268" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(3)} -pin  "ACC1:acc#268" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(4)} -pin  "ACC1:acc#268" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(5)} -pin  "ACC1:acc#268" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(6)} -pin  "ACC1:acc#268" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(7)} -pin  "ACC1:acc#268" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(8)} -pin  "ACC1:acc#268" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(9)} -pin  "ACC1:acc#268" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(10)} -pin  "ACC1:acc#268" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load inst "ACC1-1:not#164" "not(1)" "INTERFACE" -attr xrf 25692 -attr oid 988 -attr @path {/sobel/sobel:core/ACC1-1:not#164} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:not#164" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#49.itm}
+load net {ACC1-1:not#164.itm} -pin  "ACC1-1:not#164" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#164.itm}
+load inst "ACC1-1:nand#2" "nand(2,1)" "INTERFACE" -attr xrf 25693 -attr oid 989 -attr vt c -attr @path {/sobel/sobel:core/ACC1-1:nand#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#161.itm(2)} -pin  "ACC1-1:nand#2" {A0(0)} -attr vt c -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#2.itm}
+load net {ACC1-1:not#164.itm} -pin  "ACC1-1:nand#2" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#164.itm}
+load net {ACC1-1:nand#2.itm} -pin  "ACC1-1:nand#2" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/ACC1-1:nand#2.itm}
+load inst "ACC1:acc#274" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25694 -attr oid 990 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#274} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#274" {A(0)} -attr @path {/sobel/sobel:core/exs#38.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#274" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#38.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#274" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#38.itm}
+load net {ACC1-1:nand#2.itm} -pin  "ACC1:acc#274" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:exs#774.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#274" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:exs#774.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#274" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:exs#774.itm}
+load net {ACC1:acc#274.itm(0)} -pin  "ACC1:acc#274" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(1)} -pin  "ACC1:acc#274" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(2)} -pin  "ACC1:acc#274" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(3)} -pin  "ACC1:acc#274" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load inst "ACC1-1:not#165" "not(1)" "INTERFACE" -attr xrf 25695 -attr oid 991 -attr @path {/sobel/sobel:core/ACC1-1:not#165} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#160.itm(3)} -pin  "ACC1-1:not#165" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#22.sva)#4.itm}
+load net {ACC1-1:not#165.itm} -pin  "ACC1-1:not#165" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#165.itm}
+load inst "ACC1:acc#273" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25696 -attr oid 992 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#273} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#273" {A(0)} -attr @path {/sobel/sobel:core/exs#39.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#273" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#39.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#273" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#39.itm}
+load net {ACC1-1:not#165.itm} -pin  "ACC1:acc#273" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#776.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#273" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#776.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#273" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#776.itm}
+load net {ACC1:acc#273.itm(0)} -pin  "ACC1:acc#273" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(1)} -pin  "ACC1:acc#273" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(2)} -pin  "ACC1:acc#273" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(3)} -pin  "ACC1:acc#273" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load inst "ACC1:acc#280" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25697 -attr oid 993 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#274.itm(1)} -pin  "ACC1:acc#280" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#80.itm}
+load net {ACC1:acc#274.itm(2)} -pin  "ACC1:acc#280" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#80.itm}
+load net {ACC1:acc#274.itm(3)} -pin  "ACC1:acc#280" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#80.itm}
+load net {ACC1:acc#273.itm(1)} -pin  "ACC1:acc#280" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#79.itm}
+load net {ACC1:acc#273.itm(2)} -pin  "ACC1:acc#280" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#79.itm}
+load net {ACC1:acc#273.itm(3)} -pin  "ACC1:acc#280" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#79.itm}
+load net {ACC1:acc#280.itm(0)} -pin  "ACC1:acc#280" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(1)} -pin  "ACC1:acc#280" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(2)} -pin  "ACC1:acc#280" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(3)} -pin  "ACC1:acc#280" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load inst "ACC1:acc#272" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25698 -attr oid 994 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#272" {A(0)} -attr @path {/sobel/sobel:core/exs#40.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#272" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#40.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#272" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#40.itm}
+load net {ACC1:acc#160.itm(2)} -pin  "ACC1:acc#272" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#778.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#272" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#778.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#272" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#778.itm}
+load net {ACC1:acc#272.itm(0)} -pin  "ACC1:acc#272" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(1)} -pin  "ACC1:acc#272" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(2)} -pin  "ACC1:acc#272" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(3)} -pin  "ACC1:acc#272" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load inst "ACC1:acc#271" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25699 -attr oid 995 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#271} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#271" {A(0)} -attr @path {/sobel/sobel:core/exs#41.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#271" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#41.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#271" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#41.itm}
+load net {ACC1:acc#113.psp#2.sva(2)} -pin  "ACC1:acc#271" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#780.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#271" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#780.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#271" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#780.itm}
+load net {ACC1:acc#271.itm(0)} -pin  "ACC1:acc#271" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(1)} -pin  "ACC1:acc#271" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(2)} -pin  "ACC1:acc#271" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(3)} -pin  "ACC1:acc#271" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load inst "ACC1:acc#279" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25700 -attr oid 996 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#272.itm(1)} -pin  "ACC1:acc#279" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#78.itm}
+load net {ACC1:acc#272.itm(2)} -pin  "ACC1:acc#279" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#78.itm}
+load net {ACC1:acc#272.itm(3)} -pin  "ACC1:acc#279" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#78.itm}
+load net {ACC1:acc#271.itm(1)} -pin  "ACC1:acc#279" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#77.itm}
+load net {ACC1:acc#271.itm(2)} -pin  "ACC1:acc#279" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#77.itm}
+load net {ACC1:acc#271.itm(3)} -pin  "ACC1:acc#279" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#77.itm}
+load net {ACC1:acc#279.itm(0)} -pin  "ACC1:acc#279" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(1)} -pin  "ACC1:acc#279" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(2)} -pin  "ACC1:acc#279" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(3)} -pin  "ACC1:acc#279" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load inst "ACC1:acc#284" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 25701 -attr oid 997 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#280.itm(0)} -pin  "ACC1:acc#284" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(1)} -pin  "ACC1:acc#284" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(2)} -pin  "ACC1:acc#284" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(3)} -pin  "ACC1:acc#284" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#279.itm(0)} -pin  "ACC1:acc#284" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(1)} -pin  "ACC1:acc#284" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(2)} -pin  "ACC1:acc#284" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(3)} -pin  "ACC1:acc#284" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#284.itm(0)} -pin  "ACC1:acc#284" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(1)} -pin  "ACC1:acc#284" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(2)} -pin  "ACC1:acc#284" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(3)} -pin  "ACC1:acc#284" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(4)} -pin  "ACC1:acc#284" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load inst "ACC1:acc#287" "add(6,0,5,0,7)" "INTERFACE" -attr xrf 25702 -attr oid 998 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#287" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#287" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {GND} -pin  "ACC1:acc#287" {A(2)} -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {acc#10.psp#2.sva(5)} -pin  "ACC1:acc#287" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {GND} -pin  "ACC1:acc#287" {A(4)} -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {acc#10.psp#2.sva(7)} -pin  "ACC1:acc#287" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {ACC1:acc#284.itm(0)} -pin  "ACC1:acc#287" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(1)} -pin  "ACC1:acc#287" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(2)} -pin  "ACC1:acc#287" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(3)} -pin  "ACC1:acc#287" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(4)} -pin  "ACC1:acc#287" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#287.itm(0)} -pin  "ACC1:acc#287" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(1)} -pin  "ACC1:acc#287" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(2)} -pin  "ACC1:acc#287" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(3)} -pin  "ACC1:acc#287" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(4)} -pin  "ACC1:acc#287" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(5)} -pin  "ACC1:acc#287" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(6)} -pin  "ACC1:acc#287" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load inst "ACC1:acc#290" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 25703 -attr oid 999 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {acc#10.psp#2.sva(5)} -pin  "ACC1:acc#290" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {acc#10.psp#2.sva(5)} -pin  "ACC1:acc#290" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {GND} -pin  "ACC1:acc#290" {A(2)} -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1:acc#290" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {GND} -pin  "ACC1:acc#290" {A(4)} -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1:acc#290" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {GND} -pin  "ACC1:acc#290" {A(6)} -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1:acc#290" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {ACC1:acc#287.itm(0)} -pin  "ACC1:acc#290" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(1)} -pin  "ACC1:acc#290" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(2)} -pin  "ACC1:acc#290" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(3)} -pin  "ACC1:acc#290" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(4)} -pin  "ACC1:acc#290" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(5)} -pin  "ACC1:acc#290" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(6)} -pin  "ACC1:acc#290" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#290.itm(0)} -pin  "ACC1:acc#290" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(1)} -pin  "ACC1:acc#290" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(2)} -pin  "ACC1:acc#290" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(3)} -pin  "ACC1:acc#290" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(4)} -pin  "ACC1:acc#290" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(5)} -pin  "ACC1:acc#290" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(6)} -pin  "ACC1:acc#290" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(7)} -pin  "ACC1:acc#290" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load inst "ACC1:acc#292" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 25704 -attr oid 1000 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292} -attr area 10.253676 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,0,10)"
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1:acc#292" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {GND} -pin  "ACC1:acc#292" {A(1)} -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1:acc#292" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {GND} -pin  "ACC1:acc#292" {A(3)} -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1:acc#292" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {GND} -pin  "ACC1:acc#292" {A(5)} -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1:acc#292" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {GND} -pin  "ACC1:acc#292" {A(7)} -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1:acc#292" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {ACC1:acc#290.itm(0)} -pin  "ACC1:acc#292" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(1)} -pin  "ACC1:acc#292" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(2)} -pin  "ACC1:acc#292" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(3)} -pin  "ACC1:acc#292" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(4)} -pin  "ACC1:acc#292" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(5)} -pin  "ACC1:acc#292" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(6)} -pin  "ACC1:acc#292" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(7)} -pin  "ACC1:acc#292" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#292.itm(0)} -pin  "ACC1:acc#292" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(1)} -pin  "ACC1:acc#292" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(2)} -pin  "ACC1:acc#292" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(3)} -pin  "ACC1:acc#292" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(4)} -pin  "ACC1:acc#292" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(5)} -pin  "ACC1:acc#292" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(6)} -pin  "ACC1:acc#292" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(7)} -pin  "ACC1:acc#292" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(8)} -pin  "ACC1:acc#292" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(9)} -pin  "ACC1:acc#292" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load inst "ACC1:acc#269" "add(3,1,2,1,4)" "INTERFACE" -attr xrf 25705 -attr oid 1001 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#269} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#269" {A(0)} -attr @path {/sobel/sobel:core/conc#631.itm}
+load net {acc#10.psp#2.sva(3)} -pin  "ACC1:acc#269" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#631.itm}
+load net {PWR} -pin  "ACC1:acc#269" {A(2)} -attr @path {/sobel/sobel:core/conc#631.itm}
+load net {acc#10.psp#2.sva(4)} -pin  "ACC1:acc#269" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#597.itm}
+load net {ACC1:acc#113.psp#2.sva(3)} -pin  "ACC1:acc#269" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#597.itm}
+load net {ACC1:acc#269.itm(0)} -pin  "ACC1:acc#269" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(1)} -pin  "ACC1:acc#269" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(2)} -pin  "ACC1:acc#269" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(3)} -pin  "ACC1:acc#269" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load inst "ACC1:acc#278" "add(3,-1,2,1,3)" "INTERFACE" -attr xrf 25706 -attr oid 1002 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {ACC1:acc#269.itm(1)} -pin  "ACC1:acc#278" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#75.itm}
+load net {ACC1:acc#269.itm(2)} -pin  "ACC1:acc#278" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#75.itm}
+load net {ACC1:acc#269.itm(3)} -pin  "ACC1:acc#278" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#75.itm}
+load net {ACC1:acc#120.psp#1.sva(1)} -pin  "ACC1:acc#278" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp#1.sva)#2.itm}
+load net {ACC1:acc#120.psp#1.sva(2)} -pin  "ACC1:acc#278" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp#1.sva)#2.itm}
+load net {ACC1:acc#278.itm(0)} -pin  "ACC1:acc#278" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(1)} -pin  "ACC1:acc#278" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(2)} -pin  "ACC1:acc#278" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load inst "ACC1:acc#270" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 25707 -attr oid 1003 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#270" {A(0)} -attr @path {/sobel/sobel:core/conc#632.itm}
+load net {acc#10.psp#2.sva(1)} -pin  "ACC1:acc#270" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#632.itm}
+load net {acc#10.psp#2.sva(3)} -pin  "ACC1:acc#270" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#632.itm}
+load net {ACC1:acc#113.psp#2.sva(1)} -pin  "ACC1:acc#270" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#599.itm}
+load net {acc#10.psp#2.sva(2)} -pin  "ACC1:acc#270" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#599.itm}
+load net {ACC1:acc#113.psp#2.sva(3)} -pin  "ACC1:acc#270" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#599.itm}
+load net {ACC1:acc#270.itm(0)} -pin  "ACC1:acc#270" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(1)} -pin  "ACC1:acc#270" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(2)} -pin  "ACC1:acc#270" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(3)} -pin  "ACC1:acc#270" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(4)} -pin  "ACC1:acc#270" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load inst "ACC1:acc#283" "add(3,1,4,-1,4)" "INTERFACE" -attr xrf 25708 -attr oid 1004 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#278.itm(0)} -pin  "ACC1:acc#283" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(1)} -pin  "ACC1:acc#283" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(2)} -pin  "ACC1:acc#283" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#270.itm(1)} -pin  "ACC1:acc#283" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#76.itm}
+load net {ACC1:acc#270.itm(2)} -pin  "ACC1:acc#283" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#76.itm}
+load net {ACC1:acc#270.itm(3)} -pin  "ACC1:acc#283" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#76.itm}
+load net {ACC1:acc#270.itm(4)} -pin  "ACC1:acc#283" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#76.itm}
+load net {ACC1:acc#283.itm(0)} -pin  "ACC1:acc#283" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(1)} -pin  "ACC1:acc#283" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(2)} -pin  "ACC1:acc#283" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(3)} -pin  "ACC1:acc#283" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load inst "ACC1:acc#282" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 25709 -attr oid 1005 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#282" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#284.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#282" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#284.itm}
+load net {acc#10.psp#2.sva(4)} -pin  "ACC1:acc#282" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#284.itm}
+load net {acc#10.psp#2.sva(7)} -pin  "ACC1:acc#282" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#284.itm}
+load net {ACC1:acc#277.cse(0)} -pin  "ACC1:acc#282" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#277.cse(1)} -pin  "ACC1:acc#282" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#277.cse(2)} -pin  "ACC1:acc#282" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#282.itm(0)} -pin  "ACC1:acc#282" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(1)} -pin  "ACC1:acc#282" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(2)} -pin  "ACC1:acc#282" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(3)} -pin  "ACC1:acc#282" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(4)} -pin  "ACC1:acc#282" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load inst "ACC1:acc#286" "add(4,1,5,0,6)" "INTERFACE" -attr xrf 25710 -attr oid 1006 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#283.itm(0)} -pin  "ACC1:acc#286" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(1)} -pin  "ACC1:acc#286" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(2)} -pin  "ACC1:acc#286" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(3)} -pin  "ACC1:acc#286" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#282.itm(0)} -pin  "ACC1:acc#286" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(1)} -pin  "ACC1:acc#286" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(2)} -pin  "ACC1:acc#286" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(3)} -pin  "ACC1:acc#286" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(4)} -pin  "ACC1:acc#286" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#286.itm(0)} -pin  "ACC1:acc#286" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(1)} -pin  "ACC1:acc#286" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(2)} -pin  "ACC1:acc#286" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(3)} -pin  "ACC1:acc#286" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(4)} -pin  "ACC1:acc#286" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(5)} -pin  "ACC1:acc#286" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load inst "ACC1:acc#289" "add(6,1,7,0,8)" "INTERFACE" -attr xrf 25711 -attr oid 1007 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#286.itm(0)} -pin  "ACC1:acc#289" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(1)} -pin  "ACC1:acc#289" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(2)} -pin  "ACC1:acc#289" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(3)} -pin  "ACC1:acc#289" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(4)} -pin  "ACC1:acc#289" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(5)} -pin  "ACC1:acc#289" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {acc#10.psp#2.sva(8)} -pin  "ACC1:acc#289" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {GND} -pin  "ACC1:acc#289" {B(1)} -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {acc#10.psp#2.sva(8)} -pin  "ACC1:acc#289" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {GND} -pin  "ACC1:acc#289" {B(3)} -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {acc#10.psp#2.sva(8)} -pin  "ACC1:acc#289" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {GND} -pin  "ACC1:acc#289" {B(5)} -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {acc#10.psp#2.sva(8)} -pin  "ACC1:acc#289" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {ACC1:acc#289.itm(0)} -pin  "ACC1:acc#289" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(1)} -pin  "ACC1:acc#289" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(2)} -pin  "ACC1:acc#289" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(3)} -pin  "ACC1:acc#289" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(4)} -pin  "ACC1:acc#289" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(5)} -pin  "ACC1:acc#289" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(6)} -pin  "ACC1:acc#289" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(7)} -pin  "ACC1:acc#289" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load inst "ACC1-1:not#92" "not(1)" "INTERFACE" -attr xrf 25712 -attr oid 1008 -attr @path {/sobel/sobel:core/ACC1-1:not#92} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#161.itm(2)} -pin  "ACC1-1:not#92" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva).itm}
+load net {ACC1-1:not#92.itm} -pin  "ACC1-1:not#92" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#92.itm}
+load inst "ACC1-1:and#5" "and(3,1)" "INTERFACE" -attr xrf 25713 -attr oid 1009 -attr @path {/sobel/sobel:core/ACC1-1:and#5} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:and#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#37.itm}
+load net {ACC1-1:not#92.itm} -pin  "ACC1-1:and#5" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#92.itm}
+load net {ACC1:acc#161.itm(1)} -pin  "ACC1-1:and#5" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#1.itm}
+load net {ACC1-1:and#5.itm} -pin  "ACC1-1:and#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#5.itm}
+load inst "ACC1:acc#275" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25714 -attr oid 1010 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#275" {A(0)} -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {acc#10.psp#2.sva(7)} -pin  "ACC1:acc#275" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {acc#10.psp#2.sva(7)} -pin  "ACC1:acc#275" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {ACC1-1:and#5.itm} -pin  "ACC1:acc#275" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#782.itm}
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1:acc#275" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#782.itm}
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1:acc#275" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#782.itm}
+load net {ACC1:acc#275.itm(0)} -pin  "ACC1:acc#275" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(1)} -pin  "ACC1:acc#275" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(2)} -pin  "ACC1:acc#275" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(3)} -pin  "ACC1:acc#275" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load inst "ACC1:acc#281" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25715 -attr oid 1011 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#277.cse(0)} -pin  "ACC1:acc#281" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#277.cse(1)} -pin  "ACC1:acc#281" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#277.cse(2)} -pin  "ACC1:acc#281" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#275.itm(1)} -pin  "ACC1:acc#281" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#81.itm}
+load net {ACC1:acc#275.itm(2)} -pin  "ACC1:acc#281" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#81.itm}
+load net {ACC1:acc#275.itm(3)} -pin  "ACC1:acc#281" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#81.itm}
+load net {ACC1:acc#281.itm(0)} -pin  "ACC1:acc#281" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(1)} -pin  "ACC1:acc#281" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(2)} -pin  "ACC1:acc#281" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(3)} -pin  "ACC1:acc#281" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load inst "ACC1:acc#285" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 25716 -attr oid 1012 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {acc#10.psp#2.sva(6)} -pin  "ACC1:acc#285" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#634.itm}
+load net {GND} -pin  "ACC1:acc#285" {A(1)} -attr @path {/sobel/sobel:core/conc#634.itm}
+load net {acc#10.psp#2.sva(6)} -pin  "ACC1:acc#285" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#634.itm}
+load net {GND} -pin  "ACC1:acc#285" {A(3)} -attr @path {/sobel/sobel:core/conc#634.itm}
+load net {acc#10.psp#2.sva(6)} -pin  "ACC1:acc#285" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#634.itm}
+load net {ACC1:acc#281.itm(0)} -pin  "ACC1:acc#285" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(1)} -pin  "ACC1:acc#285" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(2)} -pin  "ACC1:acc#285" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(3)} -pin  "ACC1:acc#285" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#285.itm(0)} -pin  "ACC1:acc#285" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(1)} -pin  "ACC1:acc#285" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(2)} -pin  "ACC1:acc#285" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(3)} -pin  "ACC1:acc#285" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(4)} -pin  "ACC1:acc#285" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(5)} -pin  "ACC1:acc#285" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load inst "ACC1:acc#288" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 25717 -attr oid 1013 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {ACC1:acc#285.itm(0)} -pin  "ACC1:acc#288" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(1)} -pin  "ACC1:acc#288" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(2)} -pin  "ACC1:acc#288" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(3)} -pin  "ACC1:acc#288" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(4)} -pin  "ACC1:acc#288" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(5)} -pin  "ACC1:acc#288" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#288.itm(0)} -pin  "ACC1:acc#288" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(1)} -pin  "ACC1:acc#288" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(2)} -pin  "ACC1:acc#288" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(3)} -pin  "ACC1:acc#288" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(4)} -pin  "ACC1:acc#288" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(5)} -pin  "ACC1:acc#288" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(6)} -pin  "ACC1:acc#288" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(7)} -pin  "ACC1:acc#288" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load inst "ACC1:acc#291" "add(8,1,8,0,10)" "INTERFACE" -attr xrf 25718 -attr oid 1014 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#289.itm(0)} -pin  "ACC1:acc#291" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(1)} -pin  "ACC1:acc#291" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(2)} -pin  "ACC1:acc#291" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(3)} -pin  "ACC1:acc#291" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(4)} -pin  "ACC1:acc#291" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(5)} -pin  "ACC1:acc#291" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(6)} -pin  "ACC1:acc#291" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(7)} -pin  "ACC1:acc#291" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#288.itm(0)} -pin  "ACC1:acc#291" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(1)} -pin  "ACC1:acc#291" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(2)} -pin  "ACC1:acc#291" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(3)} -pin  "ACC1:acc#291" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(4)} -pin  "ACC1:acc#291" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(5)} -pin  "ACC1:acc#291" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(6)} -pin  "ACC1:acc#291" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(7)} -pin  "ACC1:acc#291" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#291.itm(0)} -pin  "ACC1:acc#291" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(1)} -pin  "ACC1:acc#291" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(2)} -pin  "ACC1:acc#291" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(3)} -pin  "ACC1:acc#291" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(4)} -pin  "ACC1:acc#291" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(5)} -pin  "ACC1:acc#291" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(6)} -pin  "ACC1:acc#291" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(7)} -pin  "ACC1:acc#291" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(8)} -pin  "ACC1:acc#291" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(9)} -pin  "ACC1:acc#291" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load inst "ACC1:acc#294" "add(10,0,10,1,11)" "INTERFACE" -attr xrf 25719 -attr oid 1015 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11)"
+load net {ACC1:acc#292.itm(0)} -pin  "ACC1:acc#294" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(1)} -pin  "ACC1:acc#294" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(2)} -pin  "ACC1:acc#294" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(3)} -pin  "ACC1:acc#294" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(4)} -pin  "ACC1:acc#294" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(5)} -pin  "ACC1:acc#294" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(6)} -pin  "ACC1:acc#294" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(7)} -pin  "ACC1:acc#294" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(8)} -pin  "ACC1:acc#294" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(9)} -pin  "ACC1:acc#294" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#291.itm(0)} -pin  "ACC1:acc#294" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(1)} -pin  "ACC1:acc#294" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(2)} -pin  "ACC1:acc#294" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(3)} -pin  "ACC1:acc#294" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(4)} -pin  "ACC1:acc#294" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(5)} -pin  "ACC1:acc#294" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(6)} -pin  "ACC1:acc#294" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(7)} -pin  "ACC1:acc#294" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(8)} -pin  "ACC1:acc#294" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(9)} -pin  "ACC1:acc#294" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#294.itm(0)} -pin  "ACC1:acc#294" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(1)} -pin  "ACC1:acc#294" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(2)} -pin  "ACC1:acc#294" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(3)} -pin  "ACC1:acc#294" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(4)} -pin  "ACC1:acc#294" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(5)} -pin  "ACC1:acc#294" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(6)} -pin  "ACC1:acc#294" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(7)} -pin  "ACC1:acc#294" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(8)} -pin  "ACC1:acc#294" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(9)} -pin  "ACC1:acc#294" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(10)} -pin  "ACC1:acc#294" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load inst "ACC1:acc#346" "add(1,0,2,0,3)" "INTERFACE" -attr xrf 25720 -attr oid 1016 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,3)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#346" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#13.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#346" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#849.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#346" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#849.itm}
+load net {ACC1:acc#346.itm(0)} -pin  "ACC1:acc#346" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:acc#346.itm(1)} -pin  "ACC1:acc#346" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:acc#346.itm(2)} -pin  "ACC1:acc#346" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load inst "ACC1-1:acc#124" "add(11,-1,11,-1,11)" "INTERFACE" -attr xrf 25721 -attr oid 1017 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13)"
+load net {ACC1:acc#294.itm(0)} -pin  "ACC1-1:acc#124" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(1)} -pin  "ACC1-1:acc#124" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(2)} -pin  "ACC1-1:acc#124" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(3)} -pin  "ACC1-1:acc#124" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(4)} -pin  "ACC1-1:acc#124" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(5)} -pin  "ACC1-1:acc#124" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(6)} -pin  "ACC1-1:acc#124" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(7)} -pin  "ACC1-1:acc#124" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(8)} -pin  "ACC1-1:acc#124" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(9)} -pin  "ACC1-1:acc#124" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(10)} -pin  "ACC1-1:acc#124" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#346.itm(0)} -pin  "ACC1-1:acc#124" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {ACC1:acc#346.itm(1)} -pin  "ACC1-1:acc#124" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {ACC1:acc#346.itm(2)} -pin  "ACC1-1:acc#124" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:acc#124" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {GND} -pin  "ACC1-1:acc#124" {B(4)} -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:acc#124" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {GND} -pin  "ACC1-1:acc#124" {B(6)} -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:acc#124" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {GND} -pin  "ACC1-1:acc#124" {B(8)} -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {GND} -pin  "ACC1-1:acc#124" {B(9)} -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:acc#124" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {ACC1-1:acc#124.itm(0)} -pin  "ACC1-1:acc#124" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(1)} -pin  "ACC1-1:acc#124" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(2)} -pin  "ACC1-1:acc#124" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(3)} -pin  "ACC1-1:acc#124" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(4)} -pin  "ACC1-1:acc#124" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(5)} -pin  "ACC1-1:acc#124" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(6)} -pin  "ACC1-1:acc#124" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(7)} -pin  "ACC1-1:acc#124" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(8)} -pin  "ACC1-1:acc#124" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(9)} -pin  "ACC1-1:acc#124" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(10)} -pin  "ACC1-1:acc#124" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load inst "ACC1-3:not#164" "not(1)" "INTERFACE" -attr xrf 25722 -attr oid 1018 -attr @path {/sobel/sobel:core/ACC1-3:not#164} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1-3:not#164" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#57.itm}
+load net {ACC1-3:not#164.itm} -pin  "ACC1-3:not#164" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#164.itm}
+load inst "ACC1-3:nand#2" "nand(2,1)" "INTERFACE" -attr xrf 25723 -attr oid 1019 -attr @path {/sobel/sobel:core/ACC1-3:nand#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#188.itm(2)} -pin  "ACC1-3:nand#2" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva).itm}
+load net {ACC1-3:not#164.itm} -pin  "ACC1-3:nand#2" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#164.itm}
+load net {ACC1-3:nand#2.itm} -pin  "ACC1-3:nand#2" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand#2.itm}
+load inst "ACC1:acc#247" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25724 -attr oid 1020 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#247" {A(0)} -attr @path {/sobel/sobel:core/exs#42.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#247" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#42.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#247" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#42.itm}
+load net {ACC1-3:nand#2.itm} -pin  "ACC1:acc#247" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#785.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#247" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#785.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#247" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#785.itm}
+load net {ACC1:acc#247.itm(0)} -pin  "ACC1:acc#247" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(1)} -pin  "ACC1:acc#247" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(2)} -pin  "ACC1:acc#247" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(3)} -pin  "ACC1:acc#247" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load inst "ACC1-3:not#165" "not(1)" "INTERFACE" -attr xrf 25725 -attr oid 1021 -attr @path {/sobel/sobel:core/ACC1-3:not#165} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#187.itm(3)} -pin  "ACC1-3:not#165" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#10.sva)#4.itm}
+load net {ACC1-3:not#165.itm} -pin  "ACC1-3:not#165" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#165.itm}
+load inst "ACC1:acc#246" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25726 -attr oid 1022 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#246" {A(0)} -attr @path {/sobel/sobel:core/exs#43.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#246" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#43.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#246" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#43.itm}
+load net {ACC1-3:not#165.itm} -pin  "ACC1:acc#246" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#787.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#246" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#787.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#246" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#787.itm}
+load net {ACC1:acc#246.itm(0)} -pin  "ACC1:acc#246" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(1)} -pin  "ACC1:acc#246" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(2)} -pin  "ACC1:acc#246" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(3)} -pin  "ACC1:acc#246" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load inst "ACC1:acc#253" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25727 -attr oid 1023 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#247.itm(1)} -pin  "ACC1:acc#253" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#247.itm(2)} -pin  "ACC1:acc#253" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#247.itm(3)} -pin  "ACC1:acc#253" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#246.itm(1)} -pin  "ACC1:acc#253" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#246.itm(2)} -pin  "ACC1:acc#253" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#246.itm(3)} -pin  "ACC1:acc#253" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#253.itm(0)} -pin  "ACC1:acc#253" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(1)} -pin  "ACC1:acc#253" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(2)} -pin  "ACC1:acc#253" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(3)} -pin  "ACC1:acc#253" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load inst "ACC1:acc#245" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25728 -attr oid 1024 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#245" {A(0)} -attr @path {/sobel/sobel:core/exs#44.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#245" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#44.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#245" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#44.itm}
+load net {ACC1:acc#187.itm(2)} -pin  "ACC1:acc#245" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#789.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#245" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#789.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#245" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#789.itm}
+load net {ACC1:acc#245.itm(0)} -pin  "ACC1:acc#245" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(1)} -pin  "ACC1:acc#245" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(2)} -pin  "ACC1:acc#245" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(3)} -pin  "ACC1:acc#245" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load inst "ACC1:acc#244" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25729 -attr oid 1025 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#244} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#244" {A(0)} -attr @path {/sobel/sobel:core/exs#45.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#244" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#45.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#244" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#45.itm}
+load net {ACC1:acc#113.psp#1.sva(2)} -pin  "ACC1:acc#244" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#791.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#244" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#791.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#244" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#791.itm}
+load net {ACC1:acc#244.itm(0)} -pin  "ACC1:acc#244" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#244.itm}
+load net {ACC1:acc#244.itm(1)} -pin  "ACC1:acc#244" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#244.itm}
+load net {ACC1:acc#244.itm(2)} -pin  "ACC1:acc#244" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#244.itm}
+load net {ACC1:acc#244.itm(3)} -pin  "ACC1:acc#244" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#244.itm}
+load inst "ACC1:acc#252" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25730 -attr oid 1026 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#245.itm(1)} -pin  "ACC1:acc#252" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#71.itm}
+load net {ACC1:acc#245.itm(2)} -pin  "ACC1:acc#252" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#71.itm}
+load net {ACC1:acc#245.itm(3)} -pin  "ACC1:acc#252" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#71.itm}
+load net {ACC1:acc#244.itm(1)} -pin  "ACC1:acc#252" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#70.itm}
+load net {ACC1:acc#244.itm(2)} -pin  "ACC1:acc#252" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#70.itm}
+load net {ACC1:acc#244.itm(3)} -pin  "ACC1:acc#252" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#70.itm}
+load net {ACC1:acc#252.itm(0)} -pin  "ACC1:acc#252" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(1)} -pin  "ACC1:acc#252" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(2)} -pin  "ACC1:acc#252" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(3)} -pin  "ACC1:acc#252" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load inst "ACC1:acc#257" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 25731 -attr oid 1027 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#253.itm(0)} -pin  "ACC1:acc#257" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(1)} -pin  "ACC1:acc#257" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(2)} -pin  "ACC1:acc#257" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(3)} -pin  "ACC1:acc#257" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#252.itm(0)} -pin  "ACC1:acc#257" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(1)} -pin  "ACC1:acc#257" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(2)} -pin  "ACC1:acc#257" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(3)} -pin  "ACC1:acc#257" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#257.itm(0)} -pin  "ACC1:acc#257" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(1)} -pin  "ACC1:acc#257" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(2)} -pin  "ACC1:acc#257" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(3)} -pin  "ACC1:acc#257" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(4)} -pin  "ACC1:acc#257" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load inst "ACC1:acc#260" "add(6,0,5,0,7)" "INTERFACE" -attr xrf 25732 -attr oid 1028 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#260" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#260" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {GND} -pin  "ACC1:acc#260" {A(2)} -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {acc#10.psp#1.sva(5)} -pin  "ACC1:acc#260" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {GND} -pin  "ACC1:acc#260" {A(4)} -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {acc#10.psp#1.sva(7)} -pin  "ACC1:acc#260" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {ACC1:acc#257.itm(0)} -pin  "ACC1:acc#260" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(1)} -pin  "ACC1:acc#260" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(2)} -pin  "ACC1:acc#260" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(3)} -pin  "ACC1:acc#260" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(4)} -pin  "ACC1:acc#260" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#260.itm(0)} -pin  "ACC1:acc#260" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(1)} -pin  "ACC1:acc#260" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(2)} -pin  "ACC1:acc#260" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(3)} -pin  "ACC1:acc#260" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(4)} -pin  "ACC1:acc#260" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(5)} -pin  "ACC1:acc#260" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(6)} -pin  "ACC1:acc#260" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load inst "ACC1:acc#263" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 25733 -attr oid 1029 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {acc#10.psp#1.sva(5)} -pin  "ACC1:acc#263" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {acc#10.psp#1.sva(5)} -pin  "ACC1:acc#263" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {GND} -pin  "ACC1:acc#263" {A(2)} -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1:acc#263" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {GND} -pin  "ACC1:acc#263" {A(4)} -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1:acc#263" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {GND} -pin  "ACC1:acc#263" {A(6)} -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1:acc#263" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {ACC1:acc#260.itm(0)} -pin  "ACC1:acc#263" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(1)} -pin  "ACC1:acc#263" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(2)} -pin  "ACC1:acc#263" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(3)} -pin  "ACC1:acc#263" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(4)} -pin  "ACC1:acc#263" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(5)} -pin  "ACC1:acc#263" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(6)} -pin  "ACC1:acc#263" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#263.itm(0)} -pin  "ACC1:acc#263" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(1)} -pin  "ACC1:acc#263" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(2)} -pin  "ACC1:acc#263" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(3)} -pin  "ACC1:acc#263" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(4)} -pin  "ACC1:acc#263" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(5)} -pin  "ACC1:acc#263" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(6)} -pin  "ACC1:acc#263" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(7)} -pin  "ACC1:acc#263" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load inst "ACC1:acc#265" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 25734 -attr oid 1030 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265} -attr area 10.253676 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,0,10)"
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1:acc#265" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {GND} -pin  "ACC1:acc#265" {A(1)} -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1:acc#265" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {GND} -pin  "ACC1:acc#265" {A(3)} -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1:acc#265" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {GND} -pin  "ACC1:acc#265" {A(5)} -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1:acc#265" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {GND} -pin  "ACC1:acc#265" {A(7)} -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1:acc#265" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {ACC1:acc#263.itm(0)} -pin  "ACC1:acc#265" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(1)} -pin  "ACC1:acc#265" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(2)} -pin  "ACC1:acc#265" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(3)} -pin  "ACC1:acc#265" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(4)} -pin  "ACC1:acc#265" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(5)} -pin  "ACC1:acc#265" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(6)} -pin  "ACC1:acc#265" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(7)} -pin  "ACC1:acc#265" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#265.itm(0)} -pin  "ACC1:acc#265" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(1)} -pin  "ACC1:acc#265" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(2)} -pin  "ACC1:acc#265" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(3)} -pin  "ACC1:acc#265" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(4)} -pin  "ACC1:acc#265" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(5)} -pin  "ACC1:acc#265" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(6)} -pin  "ACC1:acc#265" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(7)} -pin  "ACC1:acc#265" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(8)} -pin  "ACC1:acc#265" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(9)} -pin  "ACC1:acc#265" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load inst "ACC1:acc#267" "add(11,1,10,0,12)" "INTERFACE" -attr xrf 25735 -attr oid 1031 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13)"
+load net {ACC1-1:acc#124.itm(0)} -pin  "ACC1:acc#267" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(1)} -pin  "ACC1:acc#267" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(2)} -pin  "ACC1:acc#267" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(3)} -pin  "ACC1:acc#267" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(4)} -pin  "ACC1:acc#267" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(5)} -pin  "ACC1:acc#267" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(6)} -pin  "ACC1:acc#267" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(7)} -pin  "ACC1:acc#267" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(8)} -pin  "ACC1:acc#267" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(9)} -pin  "ACC1:acc#267" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(10)} -pin  "ACC1:acc#267" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1:acc#265.itm(0)} -pin  "ACC1:acc#267" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(1)} -pin  "ACC1:acc#267" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(2)} -pin  "ACC1:acc#267" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(3)} -pin  "ACC1:acc#267" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(4)} -pin  "ACC1:acc#267" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(5)} -pin  "ACC1:acc#267" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(6)} -pin  "ACC1:acc#267" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(7)} -pin  "ACC1:acc#267" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(8)} -pin  "ACC1:acc#267" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(9)} -pin  "ACC1:acc#267" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#267.itm(0)} -pin  "ACC1:acc#267" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(1)} -pin  "ACC1:acc#267" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(2)} -pin  "ACC1:acc#267" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(3)} -pin  "ACC1:acc#267" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(4)} -pin  "ACC1:acc#267" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(5)} -pin  "ACC1:acc#267" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(6)} -pin  "ACC1:acc#267" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(7)} -pin  "ACC1:acc#267" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(8)} -pin  "ACC1:acc#267" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(9)} -pin  "ACC1:acc#267" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(10)} -pin  "ACC1:acc#267" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(11)} -pin  "ACC1:acc#267" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load inst "ACC1-3:acc#124" "add(11,1,12,-1,12)" "INTERFACE" -attr xrf 25736 -attr oid 1032 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1:acc#268.itm(0)} -pin  "ACC1-3:acc#124" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(1)} -pin  "ACC1-3:acc#124" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(2)} -pin  "ACC1-3:acc#124" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(3)} -pin  "ACC1-3:acc#124" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(4)} -pin  "ACC1-3:acc#124" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(5)} -pin  "ACC1-3:acc#124" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(6)} -pin  "ACC1-3:acc#124" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(7)} -pin  "ACC1-3:acc#124" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(8)} -pin  "ACC1-3:acc#124" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(9)} -pin  "ACC1-3:acc#124" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(10)} -pin  "ACC1-3:acc#124" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#267.itm(0)} -pin  "ACC1-3:acc#124" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(1)} -pin  "ACC1-3:acc#124" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(2)} -pin  "ACC1-3:acc#124" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(3)} -pin  "ACC1-3:acc#124" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(4)} -pin  "ACC1-3:acc#124" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(5)} -pin  "ACC1-3:acc#124" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(6)} -pin  "ACC1-3:acc#124" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(7)} -pin  "ACC1-3:acc#124" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(8)} -pin  "ACC1-3:acc#124" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(9)} -pin  "ACC1-3:acc#124" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(10)} -pin  "ACC1-3:acc#124" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(11)} -pin  "ACC1-3:acc#124" {B(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1-3:acc#124.itm(0)} -pin  "ACC1-3:acc#124" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(1)} -pin  "ACC1-3:acc#124" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(2)} -pin  "ACC1-3:acc#124" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(3)} -pin  "ACC1-3:acc#124" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(4)} -pin  "ACC1-3:acc#124" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(5)} -pin  "ACC1-3:acc#124" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(6)} -pin  "ACC1-3:acc#124" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(7)} -pin  "ACC1-3:acc#124" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(8)} -pin  "ACC1-3:acc#124" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(9)} -pin  "ACC1-3:acc#124" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(10)} -pin  "ACC1-3:acc#124" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(11)} -pin  "ACC1-3:acc#124" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load inst "reg(FRAME:for:slc(in(2).sva).itm#1)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 25737 -attr oid 1033 -attr vt dc -attr @path {/sobel/sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1)}
+load net {ACC1-3:acc#124.itm(0)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(1)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(2)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(3)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(4)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(5)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(6)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(7)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(8)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(9)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(10)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(11)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {clk} -attr xrf 25738 -attr oid 1034 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:for:slc(in(2).sva).itm#1(0)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(1)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(2)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(3)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(4)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(5)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(6)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(7)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(8)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(9)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(10)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load inst "reg(exit:FRAME:for.lpi#1.dfm#3)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 25739 -attr oid 1035 -attr @path {/sobel/sobel:core/reg(exit:FRAME:for.lpi#1.dfm#3)}
+load net {exit:FRAME:for.lpi#1.dfm#4} -pin  "reg(exit:FRAME:for.lpi#1.dfm#3)" {D(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#4}
+load net {GND} -pin  "reg(exit:FRAME:for.lpi#1.dfm#3)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(exit:FRAME:for.lpi#1.dfm#3)" {clk} -attr xrf 25740 -attr oid 1036 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for.lpi#1.dfm#3)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for.lpi#1.dfm#3)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for.lpi#1.dfm#3} -pin  "reg(exit:FRAME:for.lpi#1.dfm#3)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#3}
+load inst "regs.operator[]#10:mux" "mux(4,10)" "INTERFACE" -attr xrf 25741 -attr oid 1037 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(10)} -pin  "regs.operator[]#10:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(11)} -pin  "regs.operator[]#10:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(12)} -pin  "regs.operator[]#10:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(13)} -pin  "regs.operator[]#10:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(14)} -pin  "regs.operator[]#10:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(15)} -pin  "regs.operator[]#10:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(16)} -pin  "regs.operator[]#10:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(17)} -pin  "regs.operator[]#10:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(18)} -pin  "regs.operator[]#10:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(19)} -pin  "regs.operator[]#10:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "regs.operator[]#10:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "regs.operator[]#10:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "regs.operator[]#10:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "regs.operator[]#10:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "regs.operator[]#10:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "regs.operator[]#10:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "regs.operator[]#10:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "regs.operator[]#10:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "regs.operator[]#10:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "regs.operator[]#10:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "regs.operator[]#10:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "regs.operator[]#10:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "regs.operator[]#10:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "regs.operator[]#10:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "regs.operator[]#10:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "regs.operator[]#10:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "regs.operator[]#10:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "regs.operator[]#10:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "regs.operator[]#10:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "regs.operator[]#10:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#10:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#10:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#10:mux.itm(0)} -pin  "regs.operator[]#10:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(1)} -pin  "regs.operator[]#10:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(2)} -pin  "regs.operator[]#10:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(3)} -pin  "regs.operator[]#10:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(4)} -pin  "regs.operator[]#10:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(5)} -pin  "regs.operator[]#10:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(6)} -pin  "regs.operator[]#10:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(7)} -pin  "regs.operator[]#10:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(8)} -pin  "regs.operator[]#10:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(9)} -pin  "regs.operator[]#10:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load inst "FRAME:for:mul#1" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 25742 -attr oid 1038 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#10:mux.itm(0)} -pin  "FRAME:for:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(1)} -pin  "FRAME:for:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(2)} -pin  "FRAME:for:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(3)} -pin  "FRAME:for:mul#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(4)} -pin  "FRAME:for:mul#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(5)} -pin  "FRAME:for:mul#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(6)} -pin  "FRAME:for:mul#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(7)} -pin  "FRAME:for:mul#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(8)} -pin  "FRAME:for:mul#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(9)} -pin  "FRAME:for:mul#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#645.itm}
+load net {PWR} -pin  "FRAME:for:mul#1" {B(1)} -attr @path {/sobel/sobel:core/conc#645.itm}
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:mul#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:mul#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(11)} -pin  "FRAME:for:mul#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load inst "regs.operator[]#11:mux" "mux(4,10)" "INTERFACE" -attr xrf 25743 -attr oid 1039 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(0)} -pin  "regs.operator[]#11:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(1)} -pin  "regs.operator[]#11:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(2)} -pin  "regs.operator[]#11:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(3)} -pin  "regs.operator[]#11:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(4)} -pin  "regs.operator[]#11:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(5)} -pin  "regs.operator[]#11:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(6)} -pin  "regs.operator[]#11:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(7)} -pin  "regs.operator[]#11:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(8)} -pin  "regs.operator[]#11:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(9)} -pin  "regs.operator[]#11:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "regs.operator[]#11:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "regs.operator[]#11:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "regs.operator[]#11:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "regs.operator[]#11:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "regs.operator[]#11:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "regs.operator[]#11:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "regs.operator[]#11:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "regs.operator[]#11:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "regs.operator[]#11:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "regs.operator[]#11:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "regs.operator[]#11:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "regs.operator[]#11:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "regs.operator[]#11:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "regs.operator[]#11:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "regs.operator[]#11:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "regs.operator[]#11:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "regs.operator[]#11:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "regs.operator[]#11:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "regs.operator[]#11:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "regs.operator[]#11:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#11:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#11:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#11:mux.itm(0)} -pin  "regs.operator[]#11:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(1)} -pin  "regs.operator[]#11:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(2)} -pin  "regs.operator[]#11:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(3)} -pin  "regs.operator[]#11:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(4)} -pin  "regs.operator[]#11:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(5)} -pin  "regs.operator[]#11:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(6)} -pin  "regs.operator[]#11:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(7)} -pin  "regs.operator[]#11:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(8)} -pin  "regs.operator[]#11:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(9)} -pin  "regs.operator[]#11:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load inst "FRAME:for:mul#2" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 25744 -attr oid 1040 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#11:mux.itm(0)} -pin  "FRAME:for:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(1)} -pin  "FRAME:for:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(2)} -pin  "FRAME:for:mul#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(3)} -pin  "FRAME:for:mul#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(4)} -pin  "FRAME:for:mul#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(5)} -pin  "FRAME:for:mul#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(6)} -pin  "FRAME:for:mul#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(7)} -pin  "FRAME:for:mul#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(8)} -pin  "FRAME:for:mul#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(9)} -pin  "FRAME:for:mul#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#646.itm}
+load net {PWR} -pin  "FRAME:for:mul#2" {B(1)} -attr @path {/sobel/sobel:core/conc#646.itm}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(11)} -pin  "FRAME:for:mul#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load inst "FRAME:for:acc#23" "add(12,1,12,1,13)" "INTERFACE" -attr xrf 25745 -attr oid 1041 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:acc#23" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:acc#23" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:acc#23" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:acc#23" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:acc#23" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:acc#23" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:acc#23" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:acc#23" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:acc#23" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:acc#23" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:acc#23" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(11)} -pin  "FRAME:for:acc#23" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:acc#23" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:acc#23" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:acc#23" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:acc#23" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:acc#23" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:acc#23" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:acc#23" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:acc#23" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:acc#23" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:acc#23" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:acc#23" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(11)} -pin  "FRAME:for:acc#23" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:acc#23.itm(0)} -pin  "FRAME:for:acc#23" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(1)} -pin  "FRAME:for:acc#23" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(2)} -pin  "FRAME:for:acc#23" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(3)} -pin  "FRAME:for:acc#23" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(4)} -pin  "FRAME:for:acc#23" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(5)} -pin  "FRAME:for:acc#23" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(6)} -pin  "FRAME:for:acc#23" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(7)} -pin  "FRAME:for:acc#23" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(8)} -pin  "FRAME:for:acc#23" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(9)} -pin  "FRAME:for:acc#23" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(10)} -pin  "FRAME:for:acc#23" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(11)} -pin  "FRAME:for:acc#23" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(12)} -pin  "FRAME:for:acc#23" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load inst "regs.operator[]#9:mux" "mux(4,10)" "INTERFACE" -attr xrf 25746 -attr oid 1042 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(20)} -pin  "regs.operator[]#9:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(21)} -pin  "regs.operator[]#9:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(22)} -pin  "regs.operator[]#9:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(23)} -pin  "regs.operator[]#9:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(24)} -pin  "regs.operator[]#9:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(25)} -pin  "regs.operator[]#9:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(26)} -pin  "regs.operator[]#9:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(27)} -pin  "regs.operator[]#9:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(28)} -pin  "regs.operator[]#9:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(29)} -pin  "regs.operator[]#9:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "regs.operator[]#9:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "regs.operator[]#9:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "regs.operator[]#9:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "regs.operator[]#9:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "regs.operator[]#9:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "regs.operator[]#9:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "regs.operator[]#9:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "regs.operator[]#9:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "regs.operator[]#9:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "regs.operator[]#9:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "regs.operator[]#9:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "regs.operator[]#9:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "regs.operator[]#9:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "regs.operator[]#9:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "regs.operator[]#9:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "regs.operator[]#9:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "regs.operator[]#9:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "regs.operator[]#9:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "regs.operator[]#9:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "regs.operator[]#9:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#9:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#9:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#9:mux.itm(0)} -pin  "regs.operator[]#9:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(1)} -pin  "regs.operator[]#9:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(2)} -pin  "regs.operator[]#9:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(3)} -pin  "regs.operator[]#9:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(4)} -pin  "regs.operator[]#9:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(5)} -pin  "regs.operator[]#9:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(6)} -pin  "regs.operator[]#9:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(7)} -pin  "regs.operator[]#9:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(8)} -pin  "regs.operator[]#9:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(9)} -pin  "regs.operator[]#9:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load inst "FRAME:for:mul" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 25747 -attr oid 1043 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#9:mux.itm(0)} -pin  "FRAME:for:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(1)} -pin  "FRAME:for:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(2)} -pin  "FRAME:for:mul" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(3)} -pin  "FRAME:for:mul" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(4)} -pin  "FRAME:for:mul" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(5)} -pin  "FRAME:for:mul" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(6)} -pin  "FRAME:for:mul" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(7)} -pin  "FRAME:for:mul" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(8)} -pin  "FRAME:for:mul" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(9)} -pin  "FRAME:for:mul" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#647.itm}
+load net {PWR} -pin  "FRAME:for:mul" {B(1)} -attr @path {/sobel/sobel:core/conc#647.itm}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(11)} -pin  "FRAME:for:mul" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load inst "FRAME:for:acc#24" "add(13,-1,12,1,13)" "INTERFACE" -attr xrf 25748 -attr oid 1044 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24} -attr area 14.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,0,12,1,13)"
+load net {FRAME:for:acc#23.itm(0)} -pin  "FRAME:for:acc#24" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(1)} -pin  "FRAME:for:acc#24" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(2)} -pin  "FRAME:for:acc#24" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(3)} -pin  "FRAME:for:acc#24" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(4)} -pin  "FRAME:for:acc#24" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(5)} -pin  "FRAME:for:acc#24" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(6)} -pin  "FRAME:for:acc#24" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(7)} -pin  "FRAME:for:acc#24" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(8)} -pin  "FRAME:for:acc#24" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(9)} -pin  "FRAME:for:acc#24" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(10)} -pin  "FRAME:for:acc#24" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(11)} -pin  "FRAME:for:acc#24" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(12)} -pin  "FRAME:for:acc#24" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:acc#24" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:acc#24" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:acc#24" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:acc#24" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:acc#24" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:acc#24" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:acc#24" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:acc#24" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:acc#24" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:acc#24" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:acc#24" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(11)} -pin  "FRAME:for:acc#24" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:acc#24.itm(0)} -pin  "FRAME:for:acc#24" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(1)} -pin  "FRAME:for:acc#24" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(2)} -pin  "FRAME:for:acc#24" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(3)} -pin  "FRAME:for:acc#24" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(4)} -pin  "FRAME:for:acc#24" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(5)} -pin  "FRAME:for:acc#24" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(6)} -pin  "FRAME:for:acc#24" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(7)} -pin  "FRAME:for:acc#24" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(8)} -pin  "FRAME:for:acc#24" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(9)} -pin  "FRAME:for:acc#24" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(10)} -pin  "FRAME:for:acc#24" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(11)} -pin  "FRAME:for:acc#24" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(12)} -pin  "FRAME:for:acc#24" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load inst "reg(FRAME:for:acc#24.itm#1)" "reg(13,1,1,-1,0)" "INTERFACE" -attr xrf 25749 -attr oid 1045 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:for:acc#24.itm#1)}
+load net {FRAME:for:acc#24.itm(0)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(1)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(2)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(3)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(4)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(5)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(6)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(7)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(8)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(9)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(10)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(11)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(12)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_13}
+load net {clk} -pin  "reg(FRAME:for:acc#24.itm#1)" {clk} -attr xrf 25750 -attr oid 1046 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:for:acc#24.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:for:acc#24.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:for:acc#24.itm#1(0)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(1)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(2)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(3)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(4)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(5)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(6)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(7)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(8)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(9)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(10)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(11)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(12)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load inst "ACC1:acc#189" "add(3,1,2,1,4)" "INTERFACE" -attr xrf 25751 -attr oid 1047 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#189" {A(0)} -attr @path {/sobel/sobel:core/conc#649.itm}
+load net {acc.psp#1.sva(3)} -pin  "ACC1:acc#189" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#649.itm}
+load net {PWR} -pin  "ACC1:acc#189" {A(2)} -attr @path {/sobel/sobel:core/conc#649.itm}
+load net {acc.psp#1.sva(4)} -pin  "ACC1:acc#189" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#552.itm}
+load net {ACC1:acc#107.psp#1.sva(3)} -pin  "ACC1:acc#189" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#552.itm}
+load net {ACC1:acc#189.itm(0)} -pin  "ACC1:acc#189" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {ACC1:acc#189.itm(1)} -pin  "ACC1:acc#189" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {ACC1:acc#189.itm(2)} -pin  "ACC1:acc#189" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {ACC1:acc#189.itm(3)} -pin  "ACC1:acc#189" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load inst "ACC1:acc#198" "add(3,-1,2,1,3)" "INTERFACE" -attr xrf 25752 -attr oid 1048 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {ACC1:acc#189.itm(1)} -pin  "ACC1:acc#198" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#54.itm}
+load net {ACC1:acc#189.itm(2)} -pin  "ACC1:acc#198" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#54.itm}
+load net {ACC1:acc#189.itm(3)} -pin  "ACC1:acc#198" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#54.itm}
+load net {ACC1:acc#116.psp.sva(1)} -pin  "ACC1:acc#198" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp.sva)#2.itm}
+load net {ACC1:acc#116.psp.sva(2)} -pin  "ACC1:acc#198" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp.sva)#2.itm}
+load net {ACC1:acc#198.itm(0)} -pin  "ACC1:acc#198" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:acc#198.itm(1)} -pin  "ACC1:acc#198" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:acc#198.itm(2)} -pin  "ACC1:acc#198" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load inst "ACC1:acc#190" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 25753 -attr oid 1049 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#190" {A(0)} -attr @path {/sobel/sobel:core/conc#650.itm}
+load net {acc.psp#1.sva(1)} -pin  "ACC1:acc#190" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#650.itm}
+load net {acc.psp#1.sva(3)} -pin  "ACC1:acc#190" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#650.itm}
+load net {ACC1:acc#107.psp#1.sva(1)} -pin  "ACC1:acc#190" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#554.itm}
+load net {acc.psp#1.sva(2)} -pin  "ACC1:acc#190" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#554.itm}
+load net {ACC1:acc#107.psp#1.sva(3)} -pin  "ACC1:acc#190" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#554.itm}
+load net {ACC1:acc#190.itm(0)} -pin  "ACC1:acc#190" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load net {ACC1:acc#190.itm(1)} -pin  "ACC1:acc#190" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load net {ACC1:acc#190.itm(2)} -pin  "ACC1:acc#190" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load net {ACC1:acc#190.itm(3)} -pin  "ACC1:acc#190" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load net {ACC1:acc#190.itm(4)} -pin  "ACC1:acc#190" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load inst "ACC1:acc#203" "add(3,1,4,-1,4)" "INTERFACE" -attr xrf 25754 -attr oid 1050 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#198.itm(0)} -pin  "ACC1:acc#203" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:acc#198.itm(1)} -pin  "ACC1:acc#203" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:acc#198.itm(2)} -pin  "ACC1:acc#203" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:acc#190.itm(1)} -pin  "ACC1:acc#203" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#55.itm}
+load net {ACC1:acc#190.itm(2)} -pin  "ACC1:acc#203" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#55.itm}
+load net {ACC1:acc#190.itm(3)} -pin  "ACC1:acc#203" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#55.itm}
+load net {ACC1:acc#190.itm(4)} -pin  "ACC1:acc#203" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#55.itm}
+load net {ACC1:acc#203.itm(0)} -pin  "ACC1:acc#203" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(1)} -pin  "ACC1:acc#203" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(2)} -pin  "ACC1:acc#203" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(3)} -pin  "ACC1:acc#203" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load inst "ACC1:acc#202" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 25755 -attr oid 1051 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#202" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#260.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#202" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#260.itm}
+load net {acc.psp#1.sva(4)} -pin  "ACC1:acc#202" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#260.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#202" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#260.itm}
+load net {ACC1:acc#197.cse(0)} -pin  "ACC1:acc#202" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#197.cse(1)} -pin  "ACC1:acc#202" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#197.cse(2)} -pin  "ACC1:acc#202" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#202.itm(0)} -pin  "ACC1:acc#202" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(1)} -pin  "ACC1:acc#202" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(2)} -pin  "ACC1:acc#202" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(3)} -pin  "ACC1:acc#202" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(4)} -pin  "ACC1:acc#202" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load inst "ACC1:acc#206" "add(4,1,5,0,6)" "INTERFACE" -attr xrf 25756 -attr oid 1052 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#203.itm(0)} -pin  "ACC1:acc#206" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(1)} -pin  "ACC1:acc#206" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(2)} -pin  "ACC1:acc#206" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(3)} -pin  "ACC1:acc#206" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#202.itm(0)} -pin  "ACC1:acc#206" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(1)} -pin  "ACC1:acc#206" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(2)} -pin  "ACC1:acc#206" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(3)} -pin  "ACC1:acc#206" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(4)} -pin  "ACC1:acc#206" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#206.itm(0)} -pin  "ACC1:acc#206" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(1)} -pin  "ACC1:acc#206" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(2)} -pin  "ACC1:acc#206" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(3)} -pin  "ACC1:acc#206" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(4)} -pin  "ACC1:acc#206" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(5)} -pin  "ACC1:acc#206" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load inst "ACC1:acc#209" "add(6,1,7,0,8)" "INTERFACE" -attr xrf 25757 -attr oid 1053 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#206.itm(0)} -pin  "ACC1:acc#209" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(1)} -pin  "ACC1:acc#209" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(2)} -pin  "ACC1:acc#209" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(3)} -pin  "ACC1:acc#209" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(4)} -pin  "ACC1:acc#209" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(5)} -pin  "ACC1:acc#209" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#209" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {GND} -pin  "ACC1:acc#209" {B(1)} -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#209" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {GND} -pin  "ACC1:acc#209" {B(3)} -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#209" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {GND} -pin  "ACC1:acc#209" {B(5)} -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#209" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {ACC1:acc#209.itm(0)} -pin  "ACC1:acc#209" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(1)} -pin  "ACC1:acc#209" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(2)} -pin  "ACC1:acc#209" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(3)} -pin  "ACC1:acc#209" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(4)} -pin  "ACC1:acc#209" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(5)} -pin  "ACC1:acc#209" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(6)} -pin  "ACC1:acc#209" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(7)} -pin  "ACC1:acc#209" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load inst "ACC1-3:not#28" "not(1)" "INTERFACE" -attr xrf 25758 -attr oid 1054 -attr @path {/sobel/sobel:core/ACC1-3:not#28} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#170.itm(2)} -pin  "ACC1-3:not#28" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#2.itm}
+load net {ACC1-3:not#28.itm} -pin  "ACC1-3:not#28" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#28.itm}
+load inst "ACC1-3:and#1" "and(3,1)" "INTERFACE" -attr xrf 25759 -attr oid 1055 -attr @path {/sobel/sobel:core/ACC1-3:and#1} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:and#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#38.itm}
+load net {ACC1-3:not#28.itm} -pin  "ACC1-3:and#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#28.itm}
+load net {ACC1:acc#170.itm(1)} -pin  "ACC1-3:and#1" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#1.itm}
+load net {ACC1-3:and#1.itm} -pin  "ACC1-3:and#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#1.itm}
+load inst "ACC1:acc#195" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25760 -attr oid 1056 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#195" {A(0)} -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#195" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#195" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {ACC1-3:and#1.itm} -pin  "ACC1:acc#195" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#751.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#195" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#751.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#195" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#751.itm}
+load net {ACC1:acc#195.itm(0)} -pin  "ACC1:acc#195" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load net {ACC1:acc#195.itm(1)} -pin  "ACC1:acc#195" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load net {ACC1:acc#195.itm(2)} -pin  "ACC1:acc#195" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load net {ACC1:acc#195.itm(3)} -pin  "ACC1:acc#195" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load inst "ACC1:acc#201" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25761 -attr oid 1057 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#197.cse(0)} -pin  "ACC1:acc#201" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#197.cse(1)} -pin  "ACC1:acc#201" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#197.cse(2)} -pin  "ACC1:acc#201" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#195.itm(1)} -pin  "ACC1:acc#201" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#60.itm}
+load net {ACC1:acc#195.itm(2)} -pin  "ACC1:acc#201" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#60.itm}
+load net {ACC1:acc#195.itm(3)} -pin  "ACC1:acc#201" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#60.itm}
+load net {ACC1:acc#201.itm(0)} -pin  "ACC1:acc#201" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(1)} -pin  "ACC1:acc#201" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(2)} -pin  "ACC1:acc#201" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(3)} -pin  "ACC1:acc#201" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load inst "ACC1:acc#205" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 25762 -attr oid 1058 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {acc.psp#1.sva(6)} -pin  "ACC1:acc#205" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#652.itm}
+load net {GND} -pin  "ACC1:acc#205" {A(1)} -attr @path {/sobel/sobel:core/conc#652.itm}
+load net {acc.psp#1.sva(6)} -pin  "ACC1:acc#205" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#652.itm}
+load net {GND} -pin  "ACC1:acc#205" {A(3)} -attr @path {/sobel/sobel:core/conc#652.itm}
+load net {acc.psp#1.sva(6)} -pin  "ACC1:acc#205" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#652.itm}
+load net {ACC1:acc#201.itm(0)} -pin  "ACC1:acc#205" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(1)} -pin  "ACC1:acc#205" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(2)} -pin  "ACC1:acc#205" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(3)} -pin  "ACC1:acc#205" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#205.itm(0)} -pin  "ACC1:acc#205" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(1)} -pin  "ACC1:acc#205" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(2)} -pin  "ACC1:acc#205" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(3)} -pin  "ACC1:acc#205" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(4)} -pin  "ACC1:acc#205" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(5)} -pin  "ACC1:acc#205" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load inst "ACC1:acc#208" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 25763 -attr oid 1059 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {ACC1:acc#205.itm(0)} -pin  "ACC1:acc#208" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(1)} -pin  "ACC1:acc#208" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(2)} -pin  "ACC1:acc#208" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(3)} -pin  "ACC1:acc#208" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(4)} -pin  "ACC1:acc#208" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(5)} -pin  "ACC1:acc#208" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#208.itm(0)} -pin  "ACC1:acc#208" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(1)} -pin  "ACC1:acc#208" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(2)} -pin  "ACC1:acc#208" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(3)} -pin  "ACC1:acc#208" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(4)} -pin  "ACC1:acc#208" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(5)} -pin  "ACC1:acc#208" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(6)} -pin  "ACC1:acc#208" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(7)} -pin  "ACC1:acc#208" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load inst "ACC1:acc#211" "add(8,1,8,0,10)" "INTERFACE" -attr xrf 25764 -attr oid 1060 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#209.itm(0)} -pin  "ACC1:acc#211" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(1)} -pin  "ACC1:acc#211" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(2)} -pin  "ACC1:acc#211" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(3)} -pin  "ACC1:acc#211" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(4)} -pin  "ACC1:acc#211" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(5)} -pin  "ACC1:acc#211" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(6)} -pin  "ACC1:acc#211" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(7)} -pin  "ACC1:acc#211" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#208.itm(0)} -pin  "ACC1:acc#211" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(1)} -pin  "ACC1:acc#211" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(2)} -pin  "ACC1:acc#211" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(3)} -pin  "ACC1:acc#211" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(4)} -pin  "ACC1:acc#211" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(5)} -pin  "ACC1:acc#211" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(6)} -pin  "ACC1:acc#211" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(7)} -pin  "ACC1:acc#211" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#211.itm(0)} -pin  "ACC1:acc#211" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(1)} -pin  "ACC1:acc#211" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(2)} -pin  "ACC1:acc#211" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(3)} -pin  "ACC1:acc#211" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(4)} -pin  "ACC1:acc#211" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(5)} -pin  "ACC1:acc#211" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(6)} -pin  "ACC1:acc#211" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(7)} -pin  "ACC1:acc#211" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(8)} -pin  "ACC1:acc#211" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(9)} -pin  "ACC1:acc#211" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load inst "ACC1:acc#213" "add(10,1,10,0,11)" "INTERFACE" -attr xrf 25765 -attr oid 1061 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11)"
+load net {ACC1:acc#211.itm(0)} -pin  "ACC1:acc#213" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(1)} -pin  "ACC1:acc#213" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(2)} -pin  "ACC1:acc#213" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(3)} -pin  "ACC1:acc#213" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(4)} -pin  "ACC1:acc#213" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(5)} -pin  "ACC1:acc#213" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(6)} -pin  "ACC1:acc#213" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(7)} -pin  "ACC1:acc#213" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(8)} -pin  "ACC1:acc#213" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(9)} -pin  "ACC1:acc#213" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#213" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#213" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {GND} -pin  "ACC1:acc#213" {B(2)} -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#213" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {GND} -pin  "ACC1:acc#213" {B(4)} -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#213" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {GND} -pin  "ACC1:acc#213" {B(6)} -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#213" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {GND} -pin  "ACC1:acc#213" {B(8)} -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#213" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {ACC1:acc#213.itm(0)} -pin  "ACC1:acc#213" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(1)} -pin  "ACC1:acc#213" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(2)} -pin  "ACC1:acc#213" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(3)} -pin  "ACC1:acc#213" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(4)} -pin  "ACC1:acc#213" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(5)} -pin  "ACC1:acc#213" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(6)} -pin  "ACC1:acc#213" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(7)} -pin  "ACC1:acc#213" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(8)} -pin  "ACC1:acc#213" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(9)} -pin  "ACC1:acc#213" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(10)} -pin  "ACC1:acc#213" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load inst "ACC1:acc#215" "add(10,0,11,-1,11)" "INTERFACE" -attr xrf 25766 -attr oid 1062 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215} -attr area 12.237292 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,0,11)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#215" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(1)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(2)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(3)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(4)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(5)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(6)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(7)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(8)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#215" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {ACC1:acc#213.itm(0)} -pin  "ACC1:acc#215" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(1)} -pin  "ACC1:acc#215" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(2)} -pin  "ACC1:acc#215" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(3)} -pin  "ACC1:acc#215" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(4)} -pin  "ACC1:acc#215" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(5)} -pin  "ACC1:acc#215" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(6)} -pin  "ACC1:acc#215" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(7)} -pin  "ACC1:acc#215" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(8)} -pin  "ACC1:acc#215" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(9)} -pin  "ACC1:acc#215" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(10)} -pin  "ACC1:acc#215" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#215.itm(0)} -pin  "ACC1:acc#215" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(1)} -pin  "ACC1:acc#215" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(2)} -pin  "ACC1:acc#215" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(3)} -pin  "ACC1:acc#215" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(4)} -pin  "ACC1:acc#215" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(5)} -pin  "ACC1:acc#215" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(6)} -pin  "ACC1:acc#215" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(7)} -pin  "ACC1:acc#215" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(8)} -pin  "ACC1:acc#215" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(9)} -pin  "ACC1:acc#215" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(10)} -pin  "ACC1:acc#215" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load inst "ACC1-1:not#166" "not(1)" "INTERFACE" -attr xrf 25767 -attr oid 1063 -attr @path {/sobel/sobel:core/ACC1-1:not#166} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:not#166" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#49.itm}
+load net {ACC1-1:not#166.itm} -pin  "ACC1-1:not#166" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#166.itm}
+load inst "ACC1-1:nand" "nand(2,1)" "INTERFACE" -attr xrf 25768 -attr oid 1064 -attr @path {/sobel/sobel:core/ACC1-1:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#141.itm(2)} -pin  "ACC1-1:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#16.sva)#2.itm}
+load net {ACC1-1:not#166.itm} -pin  "ACC1-1:nand" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#166.itm}
+load net {ACC1-1:nand.itm} -pin  "ACC1-1:nand" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:nand.itm}
+load inst "ACC1:acc#221" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25769 -attr oid 1065 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#221" {A(0)} -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#221" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#221" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {ACC1-1:nand.itm} -pin  "ACC1:acc#221" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#753.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#221" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#753.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#221" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#753.itm}
+load net {ACC1:acc#221.itm(0)} -pin  "ACC1:acc#221" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {ACC1:acc#221.itm(1)} -pin  "ACC1:acc#221" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {ACC1:acc#221.itm(2)} -pin  "ACC1:acc#221" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {ACC1:acc#221.itm(3)} -pin  "ACC1:acc#221" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load inst "ACC1-1:not#167" "not(1)" "INTERFACE" -attr xrf 25770 -attr oid 1066 -attr @path {/sobel/sobel:core/ACC1-1:not#167} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#140.itm(3)} -pin  "ACC1-1:not#167" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#14.sva)#4.itm}
+load net {ACC1-1:not#167.itm} -pin  "ACC1-1:not#167" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#167.itm}
+load inst "ACC1:acc#220" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25771 -attr oid 1067 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#220" {A(0)} -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#220" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#220" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {ACC1-1:not#167.itm} -pin  "ACC1:acc#220" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#755.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#220" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#755.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#220" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#755.itm}
+load net {ACC1:acc#220.itm(0)} -pin  "ACC1:acc#220" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {ACC1:acc#220.itm(1)} -pin  "ACC1:acc#220" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {ACC1:acc#220.itm(2)} -pin  "ACC1:acc#220" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {ACC1:acc#220.itm(3)} -pin  "ACC1:acc#220" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load inst "ACC1:acc#227" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25772 -attr oid 1068 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#221.itm(1)} -pin  "ACC1:acc#227" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1:acc#221.itm(2)} -pin  "ACC1:acc#227" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1:acc#221.itm(3)} -pin  "ACC1:acc#227" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1:acc#220.itm(1)} -pin  "ACC1:acc#227" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#220.itm(2)} -pin  "ACC1:acc#227" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#220.itm(3)} -pin  "ACC1:acc#227" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#227.itm(0)} -pin  "ACC1:acc#227" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(1)} -pin  "ACC1:acc#227" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(2)} -pin  "ACC1:acc#227" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(3)} -pin  "ACC1:acc#227" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load inst "ACC1:acc#219" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25773 -attr oid 1069 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#219" {A(0)} -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#219" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#219" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {ACC1:acc#140.itm(2)} -pin  "ACC1:acc#219" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#757.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#219" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#757.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#219" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#757.itm}
+load net {ACC1:acc#219.itm(0)} -pin  "ACC1:acc#219" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {ACC1:acc#219.itm(1)} -pin  "ACC1:acc#219" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {ACC1:acc#219.itm(2)} -pin  "ACC1:acc#219" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {ACC1:acc#219.itm(3)} -pin  "ACC1:acc#219" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load inst "ACC1:acc#218" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25774 -attr oid 1070 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#218" {A(0)} -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#218" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#218" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {ACC1:acc#107.psp#2.sva(2)} -pin  "ACC1:acc#218" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#759.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#218" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#759.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#218" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#759.itm}
+load net {ACC1:acc#218.itm(0)} -pin  "ACC1:acc#218" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {ACC1:acc#218.itm(1)} -pin  "ACC1:acc#218" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {ACC1:acc#218.itm(2)} -pin  "ACC1:acc#218" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {ACC1:acc#218.itm(3)} -pin  "ACC1:acc#218" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load inst "ACC1:acc#226" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25775 -attr oid 1071 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#219.itm(1)} -pin  "ACC1:acc#226" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#219.itm(2)} -pin  "ACC1:acc#226" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#219.itm(3)} -pin  "ACC1:acc#226" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#218.itm(1)} -pin  "ACC1:acc#226" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#63.itm}
+load net {ACC1:acc#218.itm(2)} -pin  "ACC1:acc#226" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#63.itm}
+load net {ACC1:acc#218.itm(3)} -pin  "ACC1:acc#226" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#63.itm}
+load net {ACC1:acc#226.itm(0)} -pin  "ACC1:acc#226" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(1)} -pin  "ACC1:acc#226" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(2)} -pin  "ACC1:acc#226" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(3)} -pin  "ACC1:acc#226" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load inst "ACC1:acc#231" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 25776 -attr oid 1072 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#227.itm(0)} -pin  "ACC1:acc#231" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(1)} -pin  "ACC1:acc#231" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(2)} -pin  "ACC1:acc#231" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(3)} -pin  "ACC1:acc#231" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#226.itm(0)} -pin  "ACC1:acc#231" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(1)} -pin  "ACC1:acc#231" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(2)} -pin  "ACC1:acc#231" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(3)} -pin  "ACC1:acc#231" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#231.itm(0)} -pin  "ACC1:acc#231" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(1)} -pin  "ACC1:acc#231" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(2)} -pin  "ACC1:acc#231" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(3)} -pin  "ACC1:acc#231" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(4)} -pin  "ACC1:acc#231" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load inst "ACC1:acc#234" "add(6,0,5,0,7)" "INTERFACE" -attr xrf 25777 -attr oid 1073 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#234" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#234" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {GND} -pin  "ACC1:acc#234" {A(2)} -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#234" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {GND} -pin  "ACC1:acc#234" {A(4)} -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#234" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {ACC1:acc#231.itm(0)} -pin  "ACC1:acc#234" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(1)} -pin  "ACC1:acc#234" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(2)} -pin  "ACC1:acc#234" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(3)} -pin  "ACC1:acc#234" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(4)} -pin  "ACC1:acc#234" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#234.itm(0)} -pin  "ACC1:acc#234" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(1)} -pin  "ACC1:acc#234" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(2)} -pin  "ACC1:acc#234" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(3)} -pin  "ACC1:acc#234" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(4)} -pin  "ACC1:acc#234" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(5)} -pin  "ACC1:acc#234" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(6)} -pin  "ACC1:acc#234" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load inst "ACC1:acc#237" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 25778 -attr oid 1074 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#237" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#237" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {GND} -pin  "ACC1:acc#237" {A(2)} -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#237" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {GND} -pin  "ACC1:acc#237" {A(4)} -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#237" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {GND} -pin  "ACC1:acc#237" {A(6)} -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#237" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {ACC1:acc#234.itm(0)} -pin  "ACC1:acc#237" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(1)} -pin  "ACC1:acc#237" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(2)} -pin  "ACC1:acc#237" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(3)} -pin  "ACC1:acc#237" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(4)} -pin  "ACC1:acc#237" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(5)} -pin  "ACC1:acc#237" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(6)} -pin  "ACC1:acc#237" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#237.itm(0)} -pin  "ACC1:acc#237" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(1)} -pin  "ACC1:acc#237" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(2)} -pin  "ACC1:acc#237" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(3)} -pin  "ACC1:acc#237" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(4)} -pin  "ACC1:acc#237" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(5)} -pin  "ACC1:acc#237" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(6)} -pin  "ACC1:acc#237" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(7)} -pin  "ACC1:acc#237" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load inst "ACC1:acc#239" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 25779 -attr oid 1075 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239} -attr area 10.253676 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,0,10)"
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#239" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {GND} -pin  "ACC1:acc#239" {A(1)} -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#239" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {GND} -pin  "ACC1:acc#239" {A(3)} -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#239" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {GND} -pin  "ACC1:acc#239" {A(5)} -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#239" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {GND} -pin  "ACC1:acc#239" {A(7)} -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#239" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {ACC1:acc#237.itm(0)} -pin  "ACC1:acc#239" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(1)} -pin  "ACC1:acc#239" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(2)} -pin  "ACC1:acc#239" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(3)} -pin  "ACC1:acc#239" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(4)} -pin  "ACC1:acc#239" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(5)} -pin  "ACC1:acc#239" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(6)} -pin  "ACC1:acc#239" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(7)} -pin  "ACC1:acc#239" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#239.itm(0)} -pin  "ACC1:acc#239" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(1)} -pin  "ACC1:acc#239" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(2)} -pin  "ACC1:acc#239" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(3)} -pin  "ACC1:acc#239" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(4)} -pin  "ACC1:acc#239" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(5)} -pin  "ACC1:acc#239" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(6)} -pin  "ACC1:acc#239" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(7)} -pin  "ACC1:acc#239" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(8)} -pin  "ACC1:acc#239" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(9)} -pin  "ACC1:acc#239" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load inst "ACC1:acc#216" "add(3,1,2,1,4)" "INTERFACE" -attr xrf 25780 -attr oid 1076 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#216" {A(0)} -attr @path {/sobel/sobel:core/conc#663.itm}
+load net {acc.psp#2.sva(3)} -pin  "ACC1:acc#216" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#663.itm}
+load net {PWR} -pin  "ACC1:acc#216" {A(2)} -attr @path {/sobel/sobel:core/conc#663.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#216" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#567.itm}
+load net {ACC1:acc#107.psp#2.sva(3)} -pin  "ACC1:acc#216" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#567.itm}
+load net {ACC1:acc#216.itm(0)} -pin  "ACC1:acc#216" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {ACC1:acc#216.itm(1)} -pin  "ACC1:acc#216" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {ACC1:acc#216.itm(2)} -pin  "ACC1:acc#216" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {ACC1:acc#216.itm(3)} -pin  "ACC1:acc#216" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load inst "ACC1:acc#225" "add(3,-1,2,1,3)" "INTERFACE" -attr xrf 25781 -attr oid 1077 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {ACC1:acc#216.itm(1)} -pin  "ACC1:acc#225" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#61.itm}
+load net {ACC1:acc#216.itm(2)} -pin  "ACC1:acc#225" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#61.itm}
+load net {ACC1:acc#216.itm(3)} -pin  "ACC1:acc#225" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#61.itm}
+load net {ACC1:acc#116.psp#1.sva(1)} -pin  "ACC1:acc#225" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp#1.sva)#2.itm}
+load net {ACC1:acc#116.psp#1.sva(2)} -pin  "ACC1:acc#225" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp#1.sva)#2.itm}
+load net {ACC1:acc#225.itm(0)} -pin  "ACC1:acc#225" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#225.itm(1)} -pin  "ACC1:acc#225" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#225.itm(2)} -pin  "ACC1:acc#225" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load inst "ACC1:acc#217" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 25782 -attr oid 1078 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#217" {A(0)} -attr @path {/sobel/sobel:core/conc#664.itm}
+load net {acc.psp#2.sva(1)} -pin  "ACC1:acc#217" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#664.itm}
+load net {acc.psp#2.sva(3)} -pin  "ACC1:acc#217" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#664.itm}
+load net {ACC1:acc#107.psp#2.sva(1)} -pin  "ACC1:acc#217" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#569.itm}
+load net {acc.psp#2.sva(2)} -pin  "ACC1:acc#217" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#569.itm}
+load net {ACC1:acc#107.psp#2.sva(3)} -pin  "ACC1:acc#217" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#569.itm}
+load net {ACC1:acc#217.itm(0)} -pin  "ACC1:acc#217" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1:acc#217.itm(1)} -pin  "ACC1:acc#217" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1:acc#217.itm(2)} -pin  "ACC1:acc#217" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1:acc#217.itm(3)} -pin  "ACC1:acc#217" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1:acc#217.itm(4)} -pin  "ACC1:acc#217" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load inst "ACC1:acc#230" "add(3,1,4,-1,4)" "INTERFACE" -attr xrf 25783 -attr oid 1079 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#225.itm(0)} -pin  "ACC1:acc#230" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#225.itm(1)} -pin  "ACC1:acc#230" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#225.itm(2)} -pin  "ACC1:acc#230" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#217.itm(1)} -pin  "ACC1:acc#230" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#62.itm}
+load net {ACC1:acc#217.itm(2)} -pin  "ACC1:acc#230" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#62.itm}
+load net {ACC1:acc#217.itm(3)} -pin  "ACC1:acc#230" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#62.itm}
+load net {ACC1:acc#217.itm(4)} -pin  "ACC1:acc#230" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#62.itm}
+load net {ACC1:acc#230.itm(0)} -pin  "ACC1:acc#230" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#230.itm(1)} -pin  "ACC1:acc#230" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#230.itm(2)} -pin  "ACC1:acc#230" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#230.itm(3)} -pin  "ACC1:acc#230" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load inst "ACC1:acc#229" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 25784 -attr oid 1080 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#229" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#260.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#229" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#260.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#229" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#260.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#229" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#260.itm}
+load net {ACC1:acc#224.cse(0)} -pin  "ACC1:acc#229" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#224.cse(1)} -pin  "ACC1:acc#229" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#224.cse(2)} -pin  "ACC1:acc#229" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#229.itm(0)} -pin  "ACC1:acc#229" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(1)} -pin  "ACC1:acc#229" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(2)} -pin  "ACC1:acc#229" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(3)} -pin  "ACC1:acc#229" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(4)} -pin  "ACC1:acc#229" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load inst "ACC1:acc#233" "add(4,1,5,0,6)" "INTERFACE" -attr xrf 25785 -attr oid 1081 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#230.itm(0)} -pin  "ACC1:acc#233" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#230.itm(1)} -pin  "ACC1:acc#233" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#230.itm(2)} -pin  "ACC1:acc#233" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#230.itm(3)} -pin  "ACC1:acc#233" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#229.itm(0)} -pin  "ACC1:acc#233" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(1)} -pin  "ACC1:acc#233" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(2)} -pin  "ACC1:acc#233" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(3)} -pin  "ACC1:acc#233" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(4)} -pin  "ACC1:acc#233" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#233.itm(0)} -pin  "ACC1:acc#233" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(1)} -pin  "ACC1:acc#233" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(2)} -pin  "ACC1:acc#233" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(3)} -pin  "ACC1:acc#233" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(4)} -pin  "ACC1:acc#233" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(5)} -pin  "ACC1:acc#233" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load inst "ACC1:acc#236" "add(6,1,7,0,8)" "INTERFACE" -attr xrf 25786 -attr oid 1082 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#233.itm(0)} -pin  "ACC1:acc#236" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(1)} -pin  "ACC1:acc#236" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(2)} -pin  "ACC1:acc#236" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(3)} -pin  "ACC1:acc#236" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(4)} -pin  "ACC1:acc#236" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(5)} -pin  "ACC1:acc#236" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#236" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {GND} -pin  "ACC1:acc#236" {B(1)} -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#236" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {GND} -pin  "ACC1:acc#236" {B(3)} -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#236" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {GND} -pin  "ACC1:acc#236" {B(5)} -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#236" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {ACC1:acc#236.itm(0)} -pin  "ACC1:acc#236" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(1)} -pin  "ACC1:acc#236" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(2)} -pin  "ACC1:acc#236" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(3)} -pin  "ACC1:acc#236" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(4)} -pin  "ACC1:acc#236" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(5)} -pin  "ACC1:acc#236" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(6)} -pin  "ACC1:acc#236" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(7)} -pin  "ACC1:acc#236" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load inst "ACC1-1:not#28" "not(1)" "INTERFACE" -attr xrf 25787 -attr oid 1083 -attr @path {/sobel/sobel:core/ACC1-1:not#28} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#141.itm(2)} -pin  "ACC1-1:not#28" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#16.sva).itm}
+load net {ACC1-1:not#28.itm} -pin  "ACC1-1:not#28" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#28.itm}
+load inst "ACC1-1:and#1" "and(3,1)" "INTERFACE" -attr xrf 25788 -attr oid 1084 -attr @path {/sobel/sobel:core/ACC1-1:and#1} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:and#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#37.itm}
+load net {ACC1-1:not#28.itm} -pin  "ACC1-1:and#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#28.itm}
+load net {ACC1:acc#141.itm(1)} -pin  "ACC1-1:and#1" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#16.sva)#1.itm}
+load net {ACC1-1:and#1.itm} -pin  "ACC1-1:and#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#1.itm}
+load inst "ACC1:acc#222" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25789 -attr oid 1085 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#222" {A(0)} -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#222" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#222" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {ACC1-1:and#1.itm} -pin  "ACC1:acc#222" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#761.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#222" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#761.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#222" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#761.itm}
+load net {ACC1:acc#222.itm(0)} -pin  "ACC1:acc#222" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {ACC1:acc#222.itm(1)} -pin  "ACC1:acc#222" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {ACC1:acc#222.itm(2)} -pin  "ACC1:acc#222" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {ACC1:acc#222.itm(3)} -pin  "ACC1:acc#222" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load inst "ACC1:acc#228" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25790 -attr oid 1086 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#224.cse(0)} -pin  "ACC1:acc#228" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#224.cse(1)} -pin  "ACC1:acc#228" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#224.cse(2)} -pin  "ACC1:acc#228" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#222.itm(1)} -pin  "ACC1:acc#228" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#67.itm}
+load net {ACC1:acc#222.itm(2)} -pin  "ACC1:acc#228" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#67.itm}
+load net {ACC1:acc#222.itm(3)} -pin  "ACC1:acc#228" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#67.itm}
+load net {ACC1:acc#228.itm(0)} -pin  "ACC1:acc#228" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(1)} -pin  "ACC1:acc#228" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(2)} -pin  "ACC1:acc#228" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(3)} -pin  "ACC1:acc#228" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load inst "ACC1:acc#232" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 25791 -attr oid 1087 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#232" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#666.itm}
+load net {GND} -pin  "ACC1:acc#232" {A(1)} -attr @path {/sobel/sobel:core/conc#666.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#232" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#666.itm}
+load net {GND} -pin  "ACC1:acc#232" {A(3)} -attr @path {/sobel/sobel:core/conc#666.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#232" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#666.itm}
+load net {ACC1:acc#228.itm(0)} -pin  "ACC1:acc#232" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(1)} -pin  "ACC1:acc#232" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(2)} -pin  "ACC1:acc#232" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(3)} -pin  "ACC1:acc#232" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#232.itm(0)} -pin  "ACC1:acc#232" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(1)} -pin  "ACC1:acc#232" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(2)} -pin  "ACC1:acc#232" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(3)} -pin  "ACC1:acc#232" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(4)} -pin  "ACC1:acc#232" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(5)} -pin  "ACC1:acc#232" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load inst "ACC1:acc#235" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 25792 -attr oid 1088 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {ACC1:acc#232.itm(0)} -pin  "ACC1:acc#235" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(1)} -pin  "ACC1:acc#235" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(2)} -pin  "ACC1:acc#235" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(3)} -pin  "ACC1:acc#235" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(4)} -pin  "ACC1:acc#235" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(5)} -pin  "ACC1:acc#235" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#235.itm(0)} -pin  "ACC1:acc#235" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(1)} -pin  "ACC1:acc#235" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(2)} -pin  "ACC1:acc#235" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(3)} -pin  "ACC1:acc#235" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(4)} -pin  "ACC1:acc#235" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(5)} -pin  "ACC1:acc#235" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(6)} -pin  "ACC1:acc#235" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(7)} -pin  "ACC1:acc#235" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load inst "ACC1:acc#238" "add(8,1,8,0,10)" "INTERFACE" -attr xrf 25793 -attr oid 1089 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#236.itm(0)} -pin  "ACC1:acc#238" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(1)} -pin  "ACC1:acc#238" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(2)} -pin  "ACC1:acc#238" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(3)} -pin  "ACC1:acc#238" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(4)} -pin  "ACC1:acc#238" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(5)} -pin  "ACC1:acc#238" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(6)} -pin  "ACC1:acc#238" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(7)} -pin  "ACC1:acc#238" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#235.itm(0)} -pin  "ACC1:acc#238" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(1)} -pin  "ACC1:acc#238" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(2)} -pin  "ACC1:acc#238" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(3)} -pin  "ACC1:acc#238" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(4)} -pin  "ACC1:acc#238" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(5)} -pin  "ACC1:acc#238" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(6)} -pin  "ACC1:acc#238" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(7)} -pin  "ACC1:acc#238" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#238.itm(0)} -pin  "ACC1:acc#238" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(1)} -pin  "ACC1:acc#238" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(2)} -pin  "ACC1:acc#238" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(3)} -pin  "ACC1:acc#238" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(4)} -pin  "ACC1:acc#238" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(5)} -pin  "ACC1:acc#238" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(6)} -pin  "ACC1:acc#238" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(7)} -pin  "ACC1:acc#238" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(8)} -pin  "ACC1:acc#238" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(9)} -pin  "ACC1:acc#238" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load inst "ACC1:acc#241" "add(10,0,10,1,11)" "INTERFACE" -attr xrf 25794 -attr oid 1090 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11)"
+load net {ACC1:acc#239.itm(0)} -pin  "ACC1:acc#241" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(1)} -pin  "ACC1:acc#241" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(2)} -pin  "ACC1:acc#241" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(3)} -pin  "ACC1:acc#241" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(4)} -pin  "ACC1:acc#241" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(5)} -pin  "ACC1:acc#241" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(6)} -pin  "ACC1:acc#241" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(7)} -pin  "ACC1:acc#241" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(8)} -pin  "ACC1:acc#241" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(9)} -pin  "ACC1:acc#241" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#238.itm(0)} -pin  "ACC1:acc#241" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(1)} -pin  "ACC1:acc#241" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(2)} -pin  "ACC1:acc#241" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(3)} -pin  "ACC1:acc#241" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(4)} -pin  "ACC1:acc#241" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(5)} -pin  "ACC1:acc#241" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(6)} -pin  "ACC1:acc#241" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(7)} -pin  "ACC1:acc#241" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(8)} -pin  "ACC1:acc#241" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(9)} -pin  "ACC1:acc#241" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#241.itm(0)} -pin  "ACC1:acc#241" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(1)} -pin  "ACC1:acc#241" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(2)} -pin  "ACC1:acc#241" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(3)} -pin  "ACC1:acc#241" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(4)} -pin  "ACC1:acc#241" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(5)} -pin  "ACC1:acc#241" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(6)} -pin  "ACC1:acc#241" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(7)} -pin  "ACC1:acc#241" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(8)} -pin  "ACC1:acc#241" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(9)} -pin  "ACC1:acc#241" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(10)} -pin  "ACC1:acc#241" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load inst "ACC1:acc#344" "add(1,0,2,0,3)" "INTERFACE" -attr xrf 25795 -attr oid 1091 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,3)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#344" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#13.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#344" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#857.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#344" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#857.itm}
+load net {ACC1:acc#344.itm(0)} -pin  "ACC1:acc#344" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:acc#344.itm(1)} -pin  "ACC1:acc#344" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:acc#344.itm(2)} -pin  "ACC1:acc#344" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load inst "ACC1-1:acc#122" "add(11,-1,11,-1,11)" "INTERFACE" -attr xrf 25796 -attr oid 1092 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13)"
+load net {ACC1:acc#241.itm(0)} -pin  "ACC1-1:acc#122" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(1)} -pin  "ACC1-1:acc#122" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(2)} -pin  "ACC1-1:acc#122" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(3)} -pin  "ACC1-1:acc#122" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(4)} -pin  "ACC1-1:acc#122" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(5)} -pin  "ACC1-1:acc#122" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(6)} -pin  "ACC1-1:acc#122" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(7)} -pin  "ACC1-1:acc#122" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(8)} -pin  "ACC1-1:acc#122" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(9)} -pin  "ACC1-1:acc#122" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(10)} -pin  "ACC1-1:acc#122" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#344.itm(0)} -pin  "ACC1-1:acc#122" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {ACC1:acc#344.itm(1)} -pin  "ACC1-1:acc#122" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {ACC1:acc#344.itm(2)} -pin  "ACC1-1:acc#122" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#122" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {GND} -pin  "ACC1-1:acc#122" {B(4)} -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#122" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {GND} -pin  "ACC1-1:acc#122" {B(6)} -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#122" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {GND} -pin  "ACC1-1:acc#122" {B(8)} -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {GND} -pin  "ACC1-1:acc#122" {B(9)} -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#122" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {ACC1-1:acc#122.itm(0)} -pin  "ACC1-1:acc#122" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(1)} -pin  "ACC1-1:acc#122" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(2)} -pin  "ACC1-1:acc#122" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(3)} -pin  "ACC1-1:acc#122" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(4)} -pin  "ACC1-1:acc#122" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(5)} -pin  "ACC1-1:acc#122" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(6)} -pin  "ACC1-1:acc#122" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(7)} -pin  "ACC1-1:acc#122" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(8)} -pin  "ACC1-1:acc#122" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(9)} -pin  "ACC1-1:acc#122" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(10)} -pin  "ACC1-1:acc#122" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load inst "ACC1-3:not#166" "not(1)" "INTERFACE" -attr xrf 25797 -attr oid 1093 -attr @path {/sobel/sobel:core/ACC1-3:not#166} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:not#166" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#57.itm}
+load net {ACC1-3:not#166.itm} -pin  "ACC1-3:not#166" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#166.itm}
+load inst "ACC1-3:nand" "nand(2,1)" "INTERFACE" -attr xrf 25798 -attr oid 1094 -attr @path {/sobel/sobel:core/ACC1-3:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#170.itm(2)} -pin  "ACC1-3:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva).itm}
+load net {ACC1-3:not#166.itm} -pin  "ACC1-3:nand" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#166.itm}
+load net {ACC1-3:nand.itm} -pin  "ACC1-3:nand" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand.itm}
+load inst "ACC1:acc#194" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25799 -attr oid 1095 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#194" {A(0)} -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#194" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#194" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {ACC1-3:nand.itm} -pin  "ACC1:acc#194" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#764.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#194" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#764.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#194" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#764.itm}
+load net {ACC1:acc#194.itm(0)} -pin  "ACC1:acc#194" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load net {ACC1:acc#194.itm(1)} -pin  "ACC1:acc#194" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load net {ACC1:acc#194.itm(2)} -pin  "ACC1:acc#194" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load net {ACC1:acc#194.itm(3)} -pin  "ACC1:acc#194" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load inst "ACC1-3:not#167" "not(1)" "INTERFACE" -attr xrf 25800 -attr oid 1096 -attr @path {/sobel/sobel:core/ACC1-3:not#167} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#169.itm(3)} -pin  "ACC1-3:not#167" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#4.itm}
+load net {ACC1-3:not#167.itm} -pin  "ACC1-3:not#167" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#167.itm}
+load inst "ACC1:acc#193" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25801 -attr oid 1097 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#193" {A(0)} -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#193" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#193" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {ACC1-3:not#167.itm} -pin  "ACC1:acc#193" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#766.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#193" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#766.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#193" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#766.itm}
+load net {ACC1:acc#193.itm(0)} -pin  "ACC1:acc#193" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load net {ACC1:acc#193.itm(1)} -pin  "ACC1:acc#193" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load net {ACC1:acc#193.itm(2)} -pin  "ACC1:acc#193" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load net {ACC1:acc#193.itm(3)} -pin  "ACC1:acc#193" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load inst "ACC1:acc#200" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25802 -attr oid 1098 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#194.itm(1)} -pin  "ACC1:acc#200" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#59.itm}
+load net {ACC1:acc#194.itm(2)} -pin  "ACC1:acc#200" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#59.itm}
+load net {ACC1:acc#194.itm(3)} -pin  "ACC1:acc#200" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#59.itm}
+load net {ACC1:acc#193.itm(1)} -pin  "ACC1:acc#200" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:acc#193.itm(2)} -pin  "ACC1:acc#200" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:acc#193.itm(3)} -pin  "ACC1:acc#200" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:acc#200.itm(0)} -pin  "ACC1:acc#200" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(1)} -pin  "ACC1:acc#200" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(2)} -pin  "ACC1:acc#200" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(3)} -pin  "ACC1:acc#200" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load inst "ACC1:acc#192" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25803 -attr oid 1099 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#192" {A(0)} -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#192" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#192" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {ACC1:acc#169.itm(2)} -pin  "ACC1:acc#192" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#768.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#192" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#768.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#192" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#768.itm}
+load net {ACC1:acc#192.itm(0)} -pin  "ACC1:acc#192" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(1)} -pin  "ACC1:acc#192" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(2)} -pin  "ACC1:acc#192" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(3)} -pin  "ACC1:acc#192" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load inst "ACC1:acc#191" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25804 -attr oid 1100 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#191" {A(0)} -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#191" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#191" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {ACC1:acc#107.psp#1.sva(2)} -pin  "ACC1:acc#191" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#770.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#191" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#770.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#191" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#770.itm}
+load net {ACC1:acc#191.itm(0)} -pin  "ACC1:acc#191" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load net {ACC1:acc#191.itm(1)} -pin  "ACC1:acc#191" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load net {ACC1:acc#191.itm(2)} -pin  "ACC1:acc#191" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load net {ACC1:acc#191.itm(3)} -pin  "ACC1:acc#191" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load inst "ACC1:acc#199" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25805 -attr oid 1101 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#192.itm(1)} -pin  "ACC1:acc#199" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#57.itm}
+load net {ACC1:acc#192.itm(2)} -pin  "ACC1:acc#199" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#57.itm}
+load net {ACC1:acc#192.itm(3)} -pin  "ACC1:acc#199" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#57.itm}
+load net {ACC1:acc#191.itm(1)} -pin  "ACC1:acc#199" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#56.itm}
+load net {ACC1:acc#191.itm(2)} -pin  "ACC1:acc#199" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#56.itm}
+load net {ACC1:acc#191.itm(3)} -pin  "ACC1:acc#199" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#56.itm}
+load net {ACC1:acc#199.itm(0)} -pin  "ACC1:acc#199" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(1)} -pin  "ACC1:acc#199" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(2)} -pin  "ACC1:acc#199" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(3)} -pin  "ACC1:acc#199" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load inst "ACC1:acc#204" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 25806 -attr oid 1102 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#200.itm(0)} -pin  "ACC1:acc#204" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(1)} -pin  "ACC1:acc#204" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(2)} -pin  "ACC1:acc#204" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(3)} -pin  "ACC1:acc#204" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#199.itm(0)} -pin  "ACC1:acc#204" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(1)} -pin  "ACC1:acc#204" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(2)} -pin  "ACC1:acc#204" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(3)} -pin  "ACC1:acc#204" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#204.itm(0)} -pin  "ACC1:acc#204" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(1)} -pin  "ACC1:acc#204" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(2)} -pin  "ACC1:acc#204" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(3)} -pin  "ACC1:acc#204" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(4)} -pin  "ACC1:acc#204" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load inst "ACC1:acc#207" "add(6,0,5,0,7)" "INTERFACE" -attr xrf 25807 -attr oid 1103 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#207" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#207" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {GND} -pin  "ACC1:acc#207" {A(2)} -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {acc.psp#1.sva(5)} -pin  "ACC1:acc#207" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {GND} -pin  "ACC1:acc#207" {A(4)} -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#207" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {ACC1:acc#204.itm(0)} -pin  "ACC1:acc#207" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(1)} -pin  "ACC1:acc#207" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(2)} -pin  "ACC1:acc#207" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(3)} -pin  "ACC1:acc#207" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(4)} -pin  "ACC1:acc#207" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#207.itm(0)} -pin  "ACC1:acc#207" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(1)} -pin  "ACC1:acc#207" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(2)} -pin  "ACC1:acc#207" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(3)} -pin  "ACC1:acc#207" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(4)} -pin  "ACC1:acc#207" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(5)} -pin  "ACC1:acc#207" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(6)} -pin  "ACC1:acc#207" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load inst "ACC1:acc#210" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 25808 -attr oid 1104 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {acc.psp#1.sva(5)} -pin  "ACC1:acc#210" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {acc.psp#1.sva(5)} -pin  "ACC1:acc#210" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {GND} -pin  "ACC1:acc#210" {A(2)} -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#210" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {GND} -pin  "ACC1:acc#210" {A(4)} -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#210" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {GND} -pin  "ACC1:acc#210" {A(6)} -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#210" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {ACC1:acc#207.itm(0)} -pin  "ACC1:acc#210" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(1)} -pin  "ACC1:acc#210" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(2)} -pin  "ACC1:acc#210" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(3)} -pin  "ACC1:acc#210" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(4)} -pin  "ACC1:acc#210" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(5)} -pin  "ACC1:acc#210" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(6)} -pin  "ACC1:acc#210" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#210.itm(0)} -pin  "ACC1:acc#210" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(1)} -pin  "ACC1:acc#210" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(2)} -pin  "ACC1:acc#210" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(3)} -pin  "ACC1:acc#210" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(4)} -pin  "ACC1:acc#210" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(5)} -pin  "ACC1:acc#210" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(6)} -pin  "ACC1:acc#210" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(7)} -pin  "ACC1:acc#210" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load inst "ACC1:acc#212" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 25809 -attr oid 1105 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212} -attr area 10.253676 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,0,10)"
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#212" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {GND} -pin  "ACC1:acc#212" {A(1)} -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#212" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {GND} -pin  "ACC1:acc#212" {A(3)} -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#212" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {GND} -pin  "ACC1:acc#212" {A(5)} -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#212" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {GND} -pin  "ACC1:acc#212" {A(7)} -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#212" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {ACC1:acc#210.itm(0)} -pin  "ACC1:acc#212" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(1)} -pin  "ACC1:acc#212" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(2)} -pin  "ACC1:acc#212" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(3)} -pin  "ACC1:acc#212" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(4)} -pin  "ACC1:acc#212" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(5)} -pin  "ACC1:acc#212" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(6)} -pin  "ACC1:acc#212" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(7)} -pin  "ACC1:acc#212" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#212.itm(0)} -pin  "ACC1:acc#212" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(1)} -pin  "ACC1:acc#212" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(2)} -pin  "ACC1:acc#212" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(3)} -pin  "ACC1:acc#212" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(4)} -pin  "ACC1:acc#212" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(5)} -pin  "ACC1:acc#212" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(6)} -pin  "ACC1:acc#212" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(7)} -pin  "ACC1:acc#212" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(8)} -pin  "ACC1:acc#212" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(9)} -pin  "ACC1:acc#212" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load inst "ACC1:acc#214" "add(11,1,10,0,12)" "INTERFACE" -attr xrf 25810 -attr oid 1106 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13)"
+load net {ACC1-1:acc#122.itm(0)} -pin  "ACC1:acc#214" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(1)} -pin  "ACC1:acc#214" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(2)} -pin  "ACC1:acc#214" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(3)} -pin  "ACC1:acc#214" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(4)} -pin  "ACC1:acc#214" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(5)} -pin  "ACC1:acc#214" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(6)} -pin  "ACC1:acc#214" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(7)} -pin  "ACC1:acc#214" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(8)} -pin  "ACC1:acc#214" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(9)} -pin  "ACC1:acc#214" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(10)} -pin  "ACC1:acc#214" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1:acc#212.itm(0)} -pin  "ACC1:acc#214" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(1)} -pin  "ACC1:acc#214" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(2)} -pin  "ACC1:acc#214" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(3)} -pin  "ACC1:acc#214" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(4)} -pin  "ACC1:acc#214" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(5)} -pin  "ACC1:acc#214" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(6)} -pin  "ACC1:acc#214" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(7)} -pin  "ACC1:acc#214" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(8)} -pin  "ACC1:acc#214" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(9)} -pin  "ACC1:acc#214" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#214.itm(0)} -pin  "ACC1:acc#214" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(1)} -pin  "ACC1:acc#214" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(2)} -pin  "ACC1:acc#214" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(3)} -pin  "ACC1:acc#214" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(4)} -pin  "ACC1:acc#214" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(5)} -pin  "ACC1:acc#214" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(6)} -pin  "ACC1:acc#214" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(7)} -pin  "ACC1:acc#214" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(8)} -pin  "ACC1:acc#214" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(9)} -pin  "ACC1:acc#214" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(10)} -pin  "ACC1:acc#214" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(11)} -pin  "ACC1:acc#214" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load inst "ACC1-3:acc#122" "add(11,1,12,-1,12)" "INTERFACE" -attr xrf 25811 -attr oid 1107 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1:acc#215.itm(0)} -pin  "ACC1-3:acc#122" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(1)} -pin  "ACC1-3:acc#122" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(2)} -pin  "ACC1-3:acc#122" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(3)} -pin  "ACC1-3:acc#122" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(4)} -pin  "ACC1-3:acc#122" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(5)} -pin  "ACC1-3:acc#122" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(6)} -pin  "ACC1-3:acc#122" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(7)} -pin  "ACC1-3:acc#122" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(8)} -pin  "ACC1-3:acc#122" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(9)} -pin  "ACC1-3:acc#122" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(10)} -pin  "ACC1-3:acc#122" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#214.itm(0)} -pin  "ACC1-3:acc#122" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(1)} -pin  "ACC1-3:acc#122" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(2)} -pin  "ACC1-3:acc#122" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(3)} -pin  "ACC1-3:acc#122" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(4)} -pin  "ACC1-3:acc#122" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(5)} -pin  "ACC1-3:acc#122" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(6)} -pin  "ACC1-3:acc#122" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(7)} -pin  "ACC1-3:acc#122" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(8)} -pin  "ACC1-3:acc#122" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(9)} -pin  "ACC1-3:acc#122" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(10)} -pin  "ACC1-3:acc#122" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(11)} -pin  "ACC1-3:acc#122" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1-3:acc#122.itm(0)} -pin  "ACC1-3:acc#122" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(1)} -pin  "ACC1-3:acc#122" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(2)} -pin  "ACC1-3:acc#122" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(3)} -pin  "ACC1-3:acc#122" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(4)} -pin  "ACC1-3:acc#122" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(5)} -pin  "ACC1-3:acc#122" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(6)} -pin  "ACC1-3:acc#122" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(7)} -pin  "ACC1-3:acc#122" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(8)} -pin  "ACC1-3:acc#122" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(9)} -pin  "ACC1-3:acc#122" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(10)} -pin  "ACC1-3:acc#122" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(11)} -pin  "ACC1-3:acc#122" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load inst "reg(FRAME:for:slc(in(0).sva).itm#1)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 25812 -attr oid 1108 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1)}
+load net {ACC1-3:acc#122.itm(0)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(1)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(2)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(3)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(4)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(5)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(6)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(7)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(8)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(9)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(10)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(11)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {clk} -attr xrf 25813 -attr oid 1109 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:for:slc(in(0).sva).itm#1(0)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(1)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(2)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(3)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(4)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(5)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(6)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(7)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(8)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(9)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(10)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load inst "reg(i#6.sva#1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 25814 -attr oid 1110 -attr vt d -attr @path {/sobel/sobel:core/reg(i#6.sva#1)}
+load net {i#6.sva#2(0)} -pin  "reg(i#6.sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "reg(i#6.sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {GND} -pin  "reg(i#6.sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(i#6.sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(i#6.sva#1)" {clk} -attr xrf 25815 -attr oid 1111 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(i#6.sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(i#6.sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {i#6.sva#1(0)} -pin  "reg(i#6.sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "reg(i#6.sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load inst "FRAME:for:not" "not(1)" "INTERFACE" -attr xrf 25816 -attr oid 1112 -attr @path {/sobel/sobel:core/FRAME:for:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#1.itm}
+load net {FRAME:for:not.itm} -pin  "FRAME:for:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load inst "FRAME:and" "and(2,1)" "INTERFACE" -attr xrf 25817 -attr oid 1113 -attr @path {/sobel/sobel:core/FRAME:and} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {FRAME:for:not.itm} -pin  "FRAME:and" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "FRAME:and" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load net {FRAME:and.itm} -pin  "FRAME:and" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load inst "reg(exit:FRAME#1.sva)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 25818 -attr oid 1114 -attr @path {/sobel/sobel:core/reg(exit:FRAME#1.sva)}
+load net {FRAME:and.itm} -pin  "reg(exit:FRAME#1.sva)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load net {PWR} -pin  "reg(exit:FRAME#1.sva)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#10_Not}
+load net {clk} -pin  "reg(exit:FRAME#1.sva)" {clk} -attr xrf 25819 -attr oid 1115 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME#1.sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME#1.sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME#1.sva} -pin  "reg(exit:FRAME#1.sva)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load inst "reg(main.stage_0#2)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 25820 -attr oid 1116 -attr @path {/sobel/sobel:core/reg(main.stage_0#2)}
+load net {PWR} -pin  "reg(main.stage_0#2)" {D(0)} -attr @path {/sobel/sobel:core/Cn1_1#2}
+load net {GND} -pin  "reg(main.stage_0#2)" {DRa(0)} -attr @path {/sobel/sobel:core/Cn2_2#4}
+load net {clk} -pin  "reg(main.stage_0#2)" {clk} -attr xrf 25821 -attr oid 1117 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(main.stage_0#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(main.stage_0#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {main.stage_0#2} -pin  "reg(main.stage_0#2)" {Z(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load inst "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" "reg(3,1,1,-1,0)" "INTERFACE" -attr xrf 25822 -attr oid 1118 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(0)} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(1)} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(2)} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load net {GND} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {GND} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {GND} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {clk} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {clk} -attr xrf 25823 -attr oid 1119 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(0)} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(1)} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(2)} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load inst "reg(ACC1:acc#125.psp.lpi#1.dfm)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 25824 -attr oid 1120 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#125.psp.lpi#1.dfm)}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(0)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(1)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(2)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(3)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(5)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(7)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(9)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {clk} -attr xrf 25825 -attr oid 1121 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#125.psp.lpi#1.dfm(0)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(1)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(2)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(3)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(4)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(5)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(6)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(7)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(8)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(9)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(10)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(11)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load inst "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 25826 -attr oid 1122 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(0)} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(1)} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0}
+load net {GND} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {clk} -attr xrf 25827 -attr oid 1123 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1(0)} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1(1)} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1}
+load inst "reg(regs.regs(2).lpi#1.dfm.sg2)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 25828 -attr oid 1124 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(2).lpi#1.dfm.sg2)}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(0)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(1)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(2)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(3)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(4)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(5)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(6)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(7)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(8)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(9)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(10)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(11)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(12)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(13)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(14)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(15)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(16)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(17)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(18)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(19)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(20)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(21)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(22)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(23)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(24)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(25)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(26)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(27)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(28)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(29)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {clk} -attr xrf 25829 -attr oid 1125 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(2).lpi#1.dfm.sg2(0)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(1)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(2)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(3)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(4)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(5)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(6)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(7)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(8)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(9)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(10)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(11)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(12)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(13)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(14)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(15)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(16)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(17)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(18)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(19)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(20)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(21)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(22)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(23)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(24)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(25)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(26)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(27)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(28)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(29)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load inst "reg(regs.regs(2).lpi#1.dfm#1)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 25830 -attr oid 1126 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(2).lpi#1.dfm#1)}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(0)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(1)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(2)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(3)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(4)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(5)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(6)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(7)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(8)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(9)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(10)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(11)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(12)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(13)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(14)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(15)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(16)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(17)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(18)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(19)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(20)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(21)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(22)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(23)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(24)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(25)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(26)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(27)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(28)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(29)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {clk} -attr xrf 25831 -attr oid 1127 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(2).lpi#1.dfm#1(0)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(1)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(2)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(3)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(4)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(5)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(6)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(7)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(8)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(9)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(10)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(11)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(12)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(13)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(14)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(15)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(16)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(17)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(18)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(19)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(20)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(21)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(22)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(23)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(24)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(25)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(26)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(27)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(28)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(29)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load inst "reg(acc.imod#7.lpi#1.dfm)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 25832 -attr oid 1128 -attr vt d -attr @path {/sobel/sobel:core/reg(acc.imod#7.lpi#1.dfm)}
+load net {acc.imod#7.lpi#1.dfm:mx0(0)} -pin  "reg(acc.imod#7.lpi#1.dfm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm:mx0}
+load net {acc.imod#7.lpi#1.dfm:mx0(1)} -pin  "reg(acc.imod#7.lpi#1.dfm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm:mx0}
+load net {GND} -pin  "reg(acc.imod#7.lpi#1.dfm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(acc.imod#7.lpi#1.dfm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(acc.imod#7.lpi#1.dfm)" {clk} -attr xrf 25833 -attr oid 1129 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(acc.imod#7.lpi#1.dfm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(acc.imod#7.lpi#1.dfm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {acc.imod#7.lpi#1.dfm(0)} -pin  "reg(acc.imod#7.lpi#1.dfm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm}
+load net {acc.imod#7.lpi#1.dfm(1)} -pin  "reg(acc.imod#7.lpi#1.dfm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm}
+load inst "reg(acc.imod#6.lpi#1.dfm.sg1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 25834 -attr oid 1130 -attr vt d -attr @path {/sobel/sobel:core/reg(acc.imod#6.lpi#1.dfm.sg1)}
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(0)} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1:mx0}
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(1)} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1:mx0}
+load net {GND} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {clk} -attr xrf 25835 -attr oid 1131 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {acc.imod#6.lpi#1.dfm.sg1(0)} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1}
+load net {acc.imod#6.lpi#1.dfm.sg1(1)} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1}
+load inst "reg(regs.regs(1).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 25836 -attr oid 1132 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(1).sva)}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "reg(regs.regs(1).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "reg(regs.regs(1).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "reg(regs.regs(1).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "reg(regs.regs(1).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "reg(regs.regs(1).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "reg(regs.regs(1).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "reg(regs.regs(1).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "reg(regs.regs(1).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "reg(regs.regs(1).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "reg(regs.regs(1).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "reg(regs.regs(1).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "reg(regs.regs(1).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "reg(regs.regs(1).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "reg(regs.regs(1).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "reg(regs.regs(1).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "reg(regs.regs(1).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "reg(regs.regs(1).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "reg(regs.regs(1).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "reg(regs.regs(1).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "reg(regs.regs(1).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "reg(regs.regs(1).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "reg(regs.regs(1).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "reg(regs.regs(1).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "reg(regs.regs(1).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "reg(regs.regs(1).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "reg(regs.regs(1).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "reg(regs.regs(1).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "reg(regs.regs(1).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "reg(regs.regs(1).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "reg(regs.regs(1).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "reg(regs.regs(1).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "reg(regs.regs(1).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "reg(regs.regs(1).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "reg(regs.regs(1).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "reg(regs.regs(1).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "reg(regs.regs(1).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "reg(regs.regs(1).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "reg(regs.regs(1).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "reg(regs.regs(1).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "reg(regs.regs(1).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "reg(regs.regs(1).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "reg(regs.regs(1).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "reg(regs.regs(1).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "reg(regs.regs(1).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "reg(regs.regs(1).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "reg(regs.regs(1).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "reg(regs.regs(1).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "reg(regs.regs(1).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "reg(regs.regs(1).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "reg(regs.regs(1).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "reg(regs.regs(1).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "reg(regs.regs(1).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "reg(regs.regs(1).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "reg(regs.regs(1).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "reg(regs.regs(1).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "reg(regs.regs(1).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "reg(regs.regs(1).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "reg(regs.regs(1).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "reg(regs.regs(1).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "reg(regs.regs(1).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "reg(regs.regs(1).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "reg(regs.regs(1).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "reg(regs.regs(1).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "reg(regs.regs(1).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "reg(regs.regs(1).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "reg(regs.regs(1).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "reg(regs.regs(1).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "reg(regs.regs(1).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "reg(regs.regs(1).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "reg(regs.regs(1).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "reg(regs.regs(1).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "reg(regs.regs(1).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "reg(regs.regs(1).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "reg(regs.regs(1).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "reg(regs.regs(1).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "reg(regs.regs(1).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "reg(regs.regs(1).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "reg(regs.regs(1).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "reg(regs.regs(1).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "reg(regs.regs(1).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "reg(regs.regs(1).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "reg(regs.regs(1).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "reg(regs.regs(1).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "reg(regs.regs(1).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "reg(regs.regs(1).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "reg(regs.regs(1).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "reg(regs.regs(1).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "reg(regs.regs(1).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "reg(regs.regs(1).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "reg(regs.regs(1).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {clk} -pin  "reg(regs.regs(1).sva)" {clk} -attr xrf 25837 -attr oid 1133 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(1).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(1).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(1).sva(0)} -pin  "reg(regs.regs(1).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "reg(regs.regs(1).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "reg(regs.regs(1).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "reg(regs.regs(1).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "reg(regs.regs(1).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "reg(regs.regs(1).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "reg(regs.regs(1).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "reg(regs.regs(1).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "reg(regs.regs(1).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "reg(regs.regs(1).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "reg(regs.regs(1).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "reg(regs.regs(1).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "reg(regs.regs(1).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "reg(regs.regs(1).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "reg(regs.regs(1).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "reg(regs.regs(1).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "reg(regs.regs(1).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "reg(regs.regs(1).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "reg(regs.regs(1).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "reg(regs.regs(1).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "reg(regs.regs(1).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "reg(regs.regs(1).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "reg(regs.regs(1).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "reg(regs.regs(1).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "reg(regs.regs(1).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "reg(regs.regs(1).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "reg(regs.regs(1).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "reg(regs.regs(1).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "reg(regs.regs(1).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "reg(regs.regs(1).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "reg(regs.regs(1).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "reg(regs.regs(1).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "reg(regs.regs(1).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "reg(regs.regs(1).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "reg(regs.regs(1).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "reg(regs.regs(1).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "reg(regs.regs(1).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "reg(regs.regs(1).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "reg(regs.regs(1).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "reg(regs.regs(1).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "reg(regs.regs(1).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "reg(regs.regs(1).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "reg(regs.regs(1).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "reg(regs.regs(1).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "reg(regs.regs(1).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "reg(regs.regs(1).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "reg(regs.regs(1).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "reg(regs.regs(1).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "reg(regs.regs(1).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "reg(regs.regs(1).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "reg(regs.regs(1).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "reg(regs.regs(1).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "reg(regs.regs(1).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "reg(regs.regs(1).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "reg(regs.regs(1).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "reg(regs.regs(1).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "reg(regs.regs(1).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "reg(regs.regs(1).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "reg(regs.regs(1).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "reg(regs.regs(1).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "reg(regs.regs(1).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "reg(regs.regs(1).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "reg(regs.regs(1).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "reg(regs.regs(1).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "reg(regs.regs(1).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "reg(regs.regs(1).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "reg(regs.regs(1).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "reg(regs.regs(1).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "reg(regs.regs(1).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "reg(regs.regs(1).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "reg(regs.regs(1).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "reg(regs.regs(1).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "reg(regs.regs(1).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "reg(regs.regs(1).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "reg(regs.regs(1).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "reg(regs.regs(1).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "reg(regs.regs(1).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "reg(regs.regs(1).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "reg(regs.regs(1).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "reg(regs.regs(1).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "reg(regs.regs(1).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "reg(regs.regs(1).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "reg(regs.regs(1).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "reg(regs.regs(1).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "reg(regs.regs(1).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "reg(regs.regs(1).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "reg(regs.regs(1).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "reg(regs.regs(1).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "reg(regs.regs(1).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "reg(regs.regs(1).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load inst "reg(regs.regs(0).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 25838 -attr oid 1134 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva)}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "reg(regs.regs(0).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "reg(regs.regs(0).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "reg(regs.regs(0).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "reg(regs.regs(0).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "reg(regs.regs(0).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "reg(regs.regs(0).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "reg(regs.regs(0).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "reg(regs.regs(0).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "reg(regs.regs(0).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "reg(regs.regs(0).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "reg(regs.regs(0).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "reg(regs.regs(0).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "reg(regs.regs(0).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "reg(regs.regs(0).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "reg(regs.regs(0).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "reg(regs.regs(0).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "reg(regs.regs(0).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "reg(regs.regs(0).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "reg(regs.regs(0).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "reg(regs.regs(0).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "reg(regs.regs(0).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "reg(regs.regs(0).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "reg(regs.regs(0).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "reg(regs.regs(0).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "reg(regs.regs(0).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "reg(regs.regs(0).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "reg(regs.regs(0).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "reg(regs.regs(0).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "reg(regs.regs(0).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "reg(regs.regs(0).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "reg(regs.regs(0).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "reg(regs.regs(0).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "reg(regs.regs(0).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "reg(regs.regs(0).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "reg(regs.regs(0).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "reg(regs.regs(0).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "reg(regs.regs(0).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "reg(regs.regs(0).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "reg(regs.regs(0).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "reg(regs.regs(0).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "reg(regs.regs(0).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "reg(regs.regs(0).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "reg(regs.regs(0).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "reg(regs.regs(0).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "reg(regs.regs(0).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "reg(regs.regs(0).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "reg(regs.regs(0).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "reg(regs.regs(0).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "reg(regs.regs(0).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "reg(regs.regs(0).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "reg(regs.regs(0).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "reg(regs.regs(0).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "reg(regs.regs(0).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "reg(regs.regs(0).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "reg(regs.regs(0).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "reg(regs.regs(0).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "reg(regs.regs(0).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "reg(regs.regs(0).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "reg(regs.regs(0).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "reg(regs.regs(0).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "reg(regs.regs(0).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "reg(regs.regs(0).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "reg(regs.regs(0).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "reg(regs.regs(0).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "reg(regs.regs(0).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "reg(regs.regs(0).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "reg(regs.regs(0).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "reg(regs.regs(0).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "reg(regs.regs(0).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "reg(regs.regs(0).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "reg(regs.regs(0).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "reg(regs.regs(0).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "reg(regs.regs(0).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "reg(regs.regs(0).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "reg(regs.regs(0).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "reg(regs.regs(0).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "reg(regs.regs(0).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "reg(regs.regs(0).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "reg(regs.regs(0).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "reg(regs.regs(0).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "reg(regs.regs(0).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "reg(regs.regs(0).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "reg(regs.regs(0).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "reg(regs.regs(0).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "reg(regs.regs(0).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "reg(regs.regs(0).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "reg(regs.regs(0).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "reg(regs.regs(0).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "reg(regs.regs(0).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "reg(regs.regs(0).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {clk} -pin  "reg(regs.regs(0).sva)" {clk} -attr xrf 25839 -attr oid 1135 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(0).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(0).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(0).sva(0)} -pin  "reg(regs.regs(0).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "reg(regs.regs(0).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "reg(regs.regs(0).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "reg(regs.regs(0).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "reg(regs.regs(0).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "reg(regs.regs(0).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "reg(regs.regs(0).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "reg(regs.regs(0).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "reg(regs.regs(0).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "reg(regs.regs(0).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "reg(regs.regs(0).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "reg(regs.regs(0).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "reg(regs.regs(0).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "reg(regs.regs(0).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "reg(regs.regs(0).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "reg(regs.regs(0).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "reg(regs.regs(0).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "reg(regs.regs(0).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "reg(regs.regs(0).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "reg(regs.regs(0).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "reg(regs.regs(0).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "reg(regs.regs(0).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "reg(regs.regs(0).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "reg(regs.regs(0).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "reg(regs.regs(0).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "reg(regs.regs(0).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "reg(regs.regs(0).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "reg(regs.regs(0).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "reg(regs.regs(0).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "reg(regs.regs(0).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "reg(regs.regs(0).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "reg(regs.regs(0).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "reg(regs.regs(0).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "reg(regs.regs(0).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "reg(regs.regs(0).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "reg(regs.regs(0).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "reg(regs.regs(0).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "reg(regs.regs(0).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "reg(regs.regs(0).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "reg(regs.regs(0).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "reg(regs.regs(0).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "reg(regs.regs(0).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "reg(regs.regs(0).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "reg(regs.regs(0).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "reg(regs.regs(0).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "reg(regs.regs(0).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "reg(regs.regs(0).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "reg(regs.regs(0).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "reg(regs.regs(0).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "reg(regs.regs(0).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "reg(regs.regs(0).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "reg(regs.regs(0).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "reg(regs.regs(0).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "reg(regs.regs(0).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "reg(regs.regs(0).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "reg(regs.regs(0).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "reg(regs.regs(0).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "reg(regs.regs(0).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "reg(regs.regs(0).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "reg(regs.regs(0).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "reg(regs.regs(0).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "reg(regs.regs(0).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "reg(regs.regs(0).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "reg(regs.regs(0).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "reg(regs.regs(0).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "reg(regs.regs(0).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "reg(regs.regs(0).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "reg(regs.regs(0).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "reg(regs.regs(0).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "reg(regs.regs(0).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "reg(regs.regs(0).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "reg(regs.regs(0).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "reg(regs.regs(0).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "reg(regs.regs(0).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "reg(regs.regs(0).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "reg(regs.regs(0).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "reg(regs.regs(0).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "reg(regs.regs(0).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "reg(regs.regs(0).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "reg(regs.regs(0).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "reg(regs.regs(0).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "reg(regs.regs(0).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "reg(regs.regs(0).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "reg(regs.regs(0).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "reg(regs.regs(0).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "reg(regs.regs(0).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "reg(regs.regs(0).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "reg(regs.regs(0).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "reg(regs.regs(0).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "reg(regs.regs(0).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load inst "reg(exit:FRAME.lpi#1.dfm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 25840 -attr oid 1136 -attr @path {/sobel/sobel:core/reg(exit:FRAME.lpi#1.dfm#1)}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {D(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load net {GND} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {clk} -attr xrf 25841 -attr oid 1137 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME.lpi#1.dfm#1} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1}
+load inst "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 25842 -attr oid 1138 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#125.psp#1.lpi#1.dfm)}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(0)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(1)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(2)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(3)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(5)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(7)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(9)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {clk} -attr xrf 25843 -attr oid 1139 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(0)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(1)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(2)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(3)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(4)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(5)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(6)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(7)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(8)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(9)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(10)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(11)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load inst "reg(acc.imod#18.lpi#1.dfm.sg1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 25844 -attr oid 1140 -attr vt d -attr @path {/sobel/sobel:core/reg(acc.imod#18.lpi#1.dfm.sg1)}
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(0)} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1:mx0}
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(1)} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1:mx0}
+load net {GND} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {clk} -attr xrf 25845 -attr oid 1141 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {acc.imod#18.lpi#1.dfm.sg1(0)} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1}
+load net {acc.imod#18.lpi#1.dfm.sg1(1)} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1}
+load inst "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" "reg(3,1,1,-1,0)" "INTERFACE" -attr xrf 25846 -attr oid 1142 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(0)} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(1)} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(2)} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load net {GND} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {GND} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {GND} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {clk} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {clk} -attr xrf 25847 -attr oid 1143 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(0)} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(1)} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(2)} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load inst "reg(acc.imod#20.lpi#1.dfm)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 25848 -attr oid 1144 -attr vt d -attr @path {/sobel/sobel:core/reg(acc.imod#20.lpi#1.dfm)}
+load net {acc.imod#20.lpi#1.dfm:mx0(0)} -pin  "reg(acc.imod#20.lpi#1.dfm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm:mx0}
+load net {acc.imod#20.lpi#1.dfm:mx0(1)} -pin  "reg(acc.imod#20.lpi#1.dfm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm:mx0}
+load net {GND} -pin  "reg(acc.imod#20.lpi#1.dfm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(acc.imod#20.lpi#1.dfm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(acc.imod#20.lpi#1.dfm)" {clk} -attr xrf 25849 -attr oid 1145 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(acc.imod#20.lpi#1.dfm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(acc.imod#20.lpi#1.dfm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {acc.imod#20.lpi#1.dfm(0)} -pin  "reg(acc.imod#20.lpi#1.dfm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm}
+load net {acc.imod#20.lpi#1.dfm(1)} -pin  "reg(acc.imod#20.lpi#1.dfm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm}
+load inst "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 25850 -attr oid 1146 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(0)} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(1)} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0}
+load net {GND} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {clk} -attr xrf 25851 -attr oid 1147 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(0)} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(1)} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1}
+load inst "mux#18" "mux(2,19)" "INTERFACE" -attr xrf 25852 -attr oid 1148 -attr vt d -attr @path {/sobel/sobel:core/mux#18} -attr area 17.470037 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2)"
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "mux#18" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "mux#18" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "mux#18" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "mux#18" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "mux#18" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "mux#18" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "mux#18" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "mux#18" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "mux#18" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "mux#18" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "mux#18" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "mux#18" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "mux#18" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "mux#18" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "mux#18" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "mux#18" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "mux#18" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "mux#18" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "mux#18" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.sva#1(0)} -pin  "mux#18" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "mux#18" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "mux#18" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "mux#18" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "mux#18" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "mux#18" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "mux#18" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "mux#18" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "mux#18" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "mux#18" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "mux#18" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "mux#18" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "mux#18" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "mux#18" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "mux#18" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "mux#18" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "mux#18" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "mux#18" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "mux#18" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:for:acc.itm(1)} -pin  "mux#18" {S(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#4.itm}
+load net {mux#18.itm(0)} -pin  "mux#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(1)} -pin  "mux#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(2)} -pin  "mux#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(3)} -pin  "mux#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(4)} -pin  "mux#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(5)} -pin  "mux#18" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(6)} -pin  "mux#18" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(7)} -pin  "mux#18" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(8)} -pin  "mux#18" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(9)} -pin  "mux#18" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(10)} -pin  "mux#18" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(11)} -pin  "mux#18" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(12)} -pin  "mux#18" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(13)} -pin  "mux#18" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(14)} -pin  "mux#18" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(15)} -pin  "mux#18" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(16)} -pin  "mux#18" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(17)} -pin  "mux#18" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(18)} -pin  "mux#18" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load inst "reg(FRAME:p#1.lpi#1)" "reg(19,1,1,-1,0)" "INTERFACE" -attr xrf 25853 -attr oid 1149 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:p#1.lpi#1)}
+load net {mux#18.itm(0)} -pin  "reg(FRAME:p#1.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(1)} -pin  "reg(FRAME:p#1.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(2)} -pin  "reg(FRAME:p#1.lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(3)} -pin  "reg(FRAME:p#1.lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(4)} -pin  "reg(FRAME:p#1.lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(5)} -pin  "reg(FRAME:p#1.lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(6)} -pin  "reg(FRAME:p#1.lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(7)} -pin  "reg(FRAME:p#1.lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(8)} -pin  "reg(FRAME:p#1.lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(9)} -pin  "reg(FRAME:p#1.lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(10)} -pin  "reg(FRAME:p#1.lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(11)} -pin  "reg(FRAME:p#1.lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(12)} -pin  "reg(FRAME:p#1.lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(13)} -pin  "reg(FRAME:p#1.lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(14)} -pin  "reg(FRAME:p#1.lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(15)} -pin  "reg(FRAME:p#1.lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(16)} -pin  "reg(FRAME:p#1.lpi#1)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(17)} -pin  "reg(FRAME:p#1.lpi#1)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(18)} -pin  "reg(FRAME:p#1.lpi#1)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_19}
+load net {clk} -pin  "reg(FRAME:p#1.lpi#1)" {clk} -attr xrf 25854 -attr oid 1150 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:p#1.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:p#1.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:p#1.lpi#1(0)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load inst "FRAME:mul" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 25855 -attr oid 1151 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC1:acc.itm(13)} -pin  "FRAME:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#12.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#12.itm}
+load net {PWR} -pin  "FRAME:mul" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul.itm(0)} -pin  "FRAME:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(1)} -pin  "FRAME:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(2)} -pin  "FRAME:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(3)} -pin  "FRAME:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(4)} -pin  "FRAME:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(5)} -pin  "FRAME:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(6)} -pin  "FRAME:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(7)} -pin  "FRAME:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(8)} -pin  "FRAME:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(9)} -pin  "FRAME:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(10)} -pin  "FRAME:mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load inst "FRAME:mul#1" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 25856 -attr oid 1152 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc.itm(10)} -pin  "FRAME:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#13.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#13.itm}
+load net {ACC1:acc.itm(12)} -pin  "FRAME:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#13.itm}
+load net {PWR} -pin  "FRAME:mul#1" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#1.itm(0)} -pin  "FRAME:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "FRAME:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "FRAME:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "FRAME:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "FRAME:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "FRAME:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "FRAME:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "FRAME:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "FRAME:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load inst "FRAME:not#7" "not(1)" "INTERFACE" -attr xrf 25857 -attr oid 1153 -attr @path {/sobel/sobel:core/FRAME:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#12.sva(5)} -pin  "FRAME:not#7" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#6.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load inst "FRAME:not#5" "not(3)" "INTERFACE" -attr xrf 25858 -attr oid 1154 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#12.sva(3)} -pin  "FRAME:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#2.itm}
+load net {acc.imod#12.sva(4)} -pin  "FRAME:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#2.itm}
+load net {acc.imod#12.sva(5)} -pin  "FRAME:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#2.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load inst "FRAME:not#4" "not(1)" "INTERFACE" -attr xrf 25859 -attr oid 1155 -attr @path {/sobel/sobel:core/FRAME:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#12.sva(5)} -pin  "FRAME:not#4" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#3.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:not#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#4.itm}
+load inst "FRAME:acc#16" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 25860 -attr oid 1156 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "FRAME:acc#16" {A(0)} -attr @path {/sobel/sobel:core/conc#678.itm}
+load net {acc.imod#12.sva(0)} -pin  "FRAME:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#678.itm}
+load net {acc.imod#12.sva(1)} -pin  "FRAME:acc#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#678.itm}
+load net {acc.imod#12.sva(2)} -pin  "FRAME:acc#16" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#678.itm}
+load net {PWR} -pin  "FRAME:acc#16" {A(4)} -attr @path {/sobel/sobel:core/conc#678.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:acc#16" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:acc#16" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:acc#16" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:acc#16" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:acc#16.itm(0)} -pin  "FRAME:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "FRAME:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "FRAME:acc#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "FRAME:acc#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:acc#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load inst "FRAME:not#15" "not(1)" "INTERFACE" -attr xrf 25861 -attr oid 1157 -attr @path {/sobel/sobel:core/FRAME:not#15} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:not#15" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#3.itm}
+load net {FRAME:not#15.itm} -pin  "FRAME:not#15" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#15.itm}
+load inst "FRAME:acc#10" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 25862 -attr oid 1158 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {FRAME:not#15.itm} -pin  "FRAME:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#677.itm}
+load net {PWR} -pin  "FRAME:acc#10" {A(1)} -attr @path {/sobel/sobel:core/conc#677.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#677.itm}
+load net {acc.imod#12.sva(3)} -pin  "FRAME:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#4.itm}
+load net {acc.imod#12.sva(4)} -pin  "FRAME:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#4.itm}
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load inst "FRAME:not#6" "not(3)" "INTERFACE" -attr xrf 25863 -attr oid 1159 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(7)} -pin  "FRAME:not#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#7.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:not#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#7.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:not#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#7.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:not#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:not#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:not#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load inst "FRAME:acc#11" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 25864 -attr oid 1160 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#11" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#11" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#11" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#11" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:acc#11" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:acc#11" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:acc#11" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#11" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#11" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#11" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#11" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "FRAME:acc#11" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load inst "FRAME:acc#12" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 25865 -attr oid 1161 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "FRAME:acc#12" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {acc.imod#12.sva(5)} -pin  "FRAME:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#679.itm}
+load net {PWR} -pin  "FRAME:acc#12" {B(1)} -attr @path {/sobel/sobel:core/conc#679.itm}
+load net {GND} -pin  "FRAME:acc#12" {B(2)} -attr @path {/sobel/sobel:core/conc#679.itm}
+load net {GND} -pin  "FRAME:acc#12" {B(3)} -attr @path {/sobel/sobel:core/conc#679.itm}
+load net {PWR} -pin  "FRAME:acc#12" {B(4)} -attr @path {/sobel/sobel:core/conc#679.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(4)} -pin  "FRAME:acc#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load inst "FRAME:acc#13" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 25866 -attr oid 1162 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {ACC1:acc.itm(4)} -pin  "FRAME:acc#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:acc#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(6)} -pin  "FRAME:acc#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(7)} -pin  "FRAME:acc#13" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:acc#13" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:acc#13" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#13" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#13" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#13" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#13" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(4)} -pin  "FRAME:acc#13" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(4)} -pin  "FRAME:acc#13" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(5)} -pin  "FRAME:acc#13" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(6)} -pin  "FRAME:acc#13" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(7)} -pin  "FRAME:acc#13" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load inst "FRAME:acc#14" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 25867 -attr oid 1163 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul#1.itm(0)} -pin  "FRAME:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "FRAME:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "FRAME:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "FRAME:acc#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "FRAME:acc#14" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "FRAME:acc#14" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "FRAME:acc#14" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "FRAME:acc#14" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "FRAME:acc#14" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#14" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(4)} -pin  "FRAME:acc#14" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(5)} -pin  "FRAME:acc#14" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(6)} -pin  "FRAME:acc#14" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(7)} -pin  "FRAME:acc#14" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
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+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(4)} -pin  "FRAME:acc#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(5)} -pin  "FRAME:acc#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(6)} -pin  "FRAME:acc#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(7)} -pin  "FRAME:acc#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(8)} -pin  "FRAME:acc#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(9)} -pin  "FRAME:acc#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load inst "FRAME:acc#15" "add(11,0,10,1,12)" "INTERFACE" -attr xrf 25868 -attr oid 1164 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13)"
+load net {FRAME:mul.itm(0)} -pin  "FRAME:acc#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(1)} -pin  "FRAME:acc#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(2)} -pin  "FRAME:acc#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(3)} -pin  "FRAME:acc#15" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(4)} -pin  "FRAME:acc#15" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(5)} -pin  "FRAME:acc#15" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(6)} -pin  "FRAME:acc#15" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(7)} -pin  "FRAME:acc#15" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(8)} -pin  "FRAME:acc#15" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(9)} -pin  "FRAME:acc#15" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(10)} -pin  "FRAME:acc#15" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
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+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#15" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#15" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(4)} -pin  "FRAME:acc#15" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(5)} -pin  "FRAME:acc#15" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(6)} -pin  "FRAME:acc#15" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(7)} -pin  "FRAME:acc#15" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(8)} -pin  "FRAME:acc#15" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(9)} -pin  "FRAME:acc#15" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(5)} -pin  "FRAME:acc#15" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(6)} -pin  "FRAME:acc#15" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(7)} -pin  "FRAME:acc#15" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(8)} -pin  "FRAME:acc#15" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(9)} -pin  "FRAME:acc#15" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(10)} -pin  "FRAME:acc#15" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(11)} -pin  "FRAME:acc#15" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load inst "FRAME:acc#2" "add(12,-1,11,0,12)" "INTERFACE" -attr xrf 25869 -attr oid 1165 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(5)} -pin  "FRAME:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(6)} -pin  "FRAME:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(7)} -pin  "FRAME:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(8)} -pin  "FRAME:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(9)} -pin  "FRAME:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(10)} -pin  "FRAME:acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(11)} -pin  "FRAME:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(1)} -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(5)} -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(6)} -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(7)} -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {FRAME:acc#2.psp.sva(0)} -pin  "FRAME:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "FRAME:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "FRAME:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "FRAME:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "FRAME:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "FRAME:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "FRAME:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "FRAME:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "FRAME:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "FRAME:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(10)} -pin  "FRAME:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(11)} -pin  "FRAME:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load inst "ACC1:acc#342" "add(16,-1,13,1,16)" "INTERFACE" -attr xrf 25870 -attr oid 1166 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,13,1,16)"
+load net {in(2).sva#3(0)} -pin  "ACC1:acc#342" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(1)} -pin  "ACC1:acc#342" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(2)} -pin  "ACC1:acc#342" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(3)} -pin  "ACC1:acc#342" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(4)} -pin  "ACC1:acc#342" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(5)} -pin  "ACC1:acc#342" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(6)} -pin  "ACC1:acc#342" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(7)} -pin  "ACC1:acc#342" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(8)} -pin  "ACC1:acc#342" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(9)} -pin  "ACC1:acc#342" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(10)} -pin  "ACC1:acc#342" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(11)} -pin  "ACC1:acc#342" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(12)} -pin  "ACC1:acc#342" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(13)} -pin  "ACC1:acc#342" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(14)} -pin  "ACC1:acc#342" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(15)} -pin  "ACC1:acc#342" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {ACC1:acc#341.itm#1(0)} -pin  "ACC1:acc#342" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(1)} -pin  "ACC1:acc#342" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(2)} -pin  "ACC1:acc#342" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(3)} -pin  "ACC1:acc#342" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(4)} -pin  "ACC1:acc#342" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(5)} -pin  "ACC1:acc#342" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(6)} -pin  "ACC1:acc#342" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(7)} -pin  "ACC1:acc#342" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(8)} -pin  "ACC1:acc#342" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(9)} -pin  "ACC1:acc#342" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(10)} -pin  "ACC1:acc#342" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(11)} -pin  "ACC1:acc#342" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(12)} -pin  "ACC1:acc#342" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#342.itm(0)} -pin  "ACC1:acc#342" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(1)} -pin  "ACC1:acc#342" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(2)} -pin  "ACC1:acc#342" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(3)} -pin  "ACC1:acc#342" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(4)} -pin  "ACC1:acc#342" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(5)} -pin  "ACC1:acc#342" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(6)} -pin  "ACC1:acc#342" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(7)} -pin  "ACC1:acc#342" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(8)} -pin  "ACC1:acc#342" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(9)} -pin  "ACC1:acc#342" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(10)} -pin  "ACC1:acc#342" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(11)} -pin  "ACC1:acc#342" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(12)} -pin  "ACC1:acc#342" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(13)} -pin  "ACC1:acc#342" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(14)} -pin  "ACC1:acc#342" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(15)} -pin  "ACC1:acc#342" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load inst "ACC1:acc" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 25871 -attr oid 1167 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {ACC1:acc#342.itm(0)} -pin  "ACC1:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(1)} -pin  "ACC1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(2)} -pin  "ACC1:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(3)} -pin  "ACC1:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(4)} -pin  "ACC1:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(5)} -pin  "ACC1:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(6)} -pin  "ACC1:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(7)} -pin  "ACC1:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(8)} -pin  "ACC1:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(9)} -pin  "ACC1:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(10)} -pin  "ACC1:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(11)} -pin  "ACC1:acc" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(12)} -pin  "ACC1:acc" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(13)} -pin  "ACC1:acc" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(14)} -pin  "ACC1:acc" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(15)} -pin  "ACC1:acc" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {in(0).sva#3(0)} -pin  "ACC1:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(1)} -pin  "ACC1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(2)} -pin  "ACC1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(3)} -pin  "ACC1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(4)} -pin  "ACC1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(5)} -pin  "ACC1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(6)} -pin  "ACC1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(7)} -pin  "ACC1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(8)} -pin  "ACC1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(9)} -pin  "ACC1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(10)} -pin  "ACC1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(11)} -pin  "ACC1:acc" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(12)} -pin  "ACC1:acc" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(13)} -pin  "ACC1:acc" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(14)} -pin  "ACC1:acc" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(15)} -pin  "ACC1:acc" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {ACC1:acc.itm(0)} -pin  "ACC1:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(1)} -pin  "ACC1:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(2)} -pin  "ACC1:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(3)} -pin  "ACC1:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(4)} -pin  "ACC1:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(5)} -pin  "ACC1:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(6)} -pin  "ACC1:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(7)} -pin  "ACC1:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(8)} -pin  "ACC1:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(9)} -pin  "ACC1:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(10)} -pin  "ACC1:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(11)} -pin  "ACC1:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(12)} -pin  "ACC1:acc" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(13)} -pin  "ACC1:acc" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(14)} -pin  "ACC1:acc" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(15)} -pin  "ACC1:acc" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load inst "FRAME:not#2" "not(3)" "INTERFACE" -attr xrf 25872 -attr oid 1168 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(10)} -pin  "FRAME:not#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#1.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:not#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#1.itm}
+load net {ACC1:acc.itm(12)} -pin  "FRAME:not#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#1.itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:not#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:not#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:not#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load inst "FRAME:acc#6" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25873 -attr oid 1169 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc.itm(7)} -pin  "FRAME:acc#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#3.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:acc#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#3.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:acc#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#3.itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:acc#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:acc#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:acc#6" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:acc#6.itm(0)} -pin  "FRAME:acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(1)} -pin  "FRAME:acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(2)} -pin  "FRAME:acc#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(3)} -pin  "FRAME:acc#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load inst "FRAME:not#13" "not(1)" "INTERFACE" -attr xrf 25874 -attr oid 1170 -attr @path {/sobel/sobel:core/FRAME:not#13} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc.itm(15)} -pin  "FRAME:not#13" {A(0)} -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#29.itm}
+load net {FRAME:not#13.itm} -pin  "FRAME:not#13" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load inst "FRAME:not#17" "not(1)" "INTERFACE" -attr xrf 25875 -attr oid 1171 -attr @path {/sobel/sobel:core/FRAME:not#17} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc.itm(15)} -pin  "FRAME:not#17" {A(0)} -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#10.itm}
+load net {FRAME:not#17.itm} -pin  "FRAME:not#17" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load inst "FRAME:acc#5" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 25876 -attr oid 1172 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {FRAME:not#17.itm} -pin  "FRAME:acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#682.itm}
+load net {PWR} -pin  "FRAME:acc#5" {A(1)} -attr @path {/sobel/sobel:core/conc#682.itm}
+load net {FRAME:not#13.itm} -pin  "FRAME:acc#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#682.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#5" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva).itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#5" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva).itm}
+load net {FRAME:acc#5.itm(0)} -pin  "FRAME:acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(1)} -pin  "FRAME:acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(2)} -pin  "FRAME:acc#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(3)} -pin  "FRAME:acc#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load inst "FRAME:acc#8" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 25877 -attr oid 1173 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#6.itm(0)} -pin  "FRAME:acc#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(1)} -pin  "FRAME:acc#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(2)} -pin  "FRAME:acc#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(3)} -pin  "FRAME:acc#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#5.itm(0)} -pin  "FRAME:acc#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(1)} -pin  "FRAME:acc#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(2)} -pin  "FRAME:acc#8" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(3)} -pin  "FRAME:acc#8" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(4)} -pin  "FRAME:acc#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load inst "FRAME:not#1" "not(3)" "INTERFACE" -attr xrf 25878 -attr oid 1174 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(4)} -pin  "FRAME:not#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#6.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:not#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#6.itm}
+load net {ACC1:acc.itm(6)} -pin  "FRAME:not#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#6.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:not#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:not#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:not#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load inst "FRAME:acc#7" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25879 -attr oid 1175 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc.itm(1)} -pin  "FRAME:acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#5.itm}
+load net {ACC1:acc.itm(2)} -pin  "FRAME:acc#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#5.itm}
+load net {ACC1:acc.itm(3)} -pin  "FRAME:acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#5.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:acc#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:acc#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:acc#7" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load inst "FRAME:acc#9" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 25880 -attr oid 1176 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#9" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(4)} -pin  "FRAME:acc#9" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#9" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#9" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#9" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#9" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(4)} -pin  "FRAME:acc#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(5)} -pin  "FRAME:acc#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load inst "acc#15" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 25881 -attr oid 1177 -attr vt d -attr @path {/sobel/sobel:core/acc#15} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {FRAME:acc#9.itm(0)} -pin  "acc#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "acc#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "acc#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "acc#15" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(4)} -pin  "acc#15" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(5)} -pin  "acc#15" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {PWR} -pin  "acc#15" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#15" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#15" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#15" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#15" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#15" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#12.sva(0)} -pin  "acc#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load net {acc.imod#12.sva(1)} -pin  "acc#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load net {acc.imod#12.sva(2)} -pin  "acc#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load net {acc.imod#12.sva(3)} -pin  "acc#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load net {acc.imod#12.sva(4)} -pin  "acc#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load net {acc.imod#12.sva(5)} -pin  "acc#15" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load inst "FRAME:for:mux#12" "mux(2,16)" "INTERFACE" -attr xrf 25882 -attr oid 1178 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:slc(in(2).sva).itm#1(0)} -pin  "FRAME:for:mux#12" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(1)} -pin  "FRAME:for:mux#12" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(2)} -pin  "FRAME:for:mux#12" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(3)} -pin  "FRAME:for:mux#12" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(4)} -pin  "FRAME:for:mux#12" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(5)} -pin  "FRAME:for:mux#12" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(6)} -pin  "FRAME:for:mux#12" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(7)} -pin  "FRAME:for:mux#12" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(8)} -pin  "FRAME:for:mux#12" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(9)} -pin  "FRAME:for:mux#12" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(10)} -pin  "FRAME:for:mux#12" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -pin  "FRAME:for:mux#12" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -pin  "FRAME:for:mux#12" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -pin  "FRAME:for:mux#12" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -pin  "FRAME:for:mux#12" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -pin  "FRAME:for:mux#12" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {in(2).sva#1(0)} -pin  "FRAME:for:mux#12" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(1)} -pin  "FRAME:for:mux#12" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(2)} -pin  "FRAME:for:mux#12" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(3)} -pin  "FRAME:for:mux#12" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(4)} -pin  "FRAME:for:mux#12" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(5)} -pin  "FRAME:for:mux#12" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(6)} -pin  "FRAME:for:mux#12" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(7)} -pin  "FRAME:for:mux#12" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(8)} -pin  "FRAME:for:mux#12" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(9)} -pin  "FRAME:for:mux#12" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(10)} -pin  "FRAME:for:mux#12" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(11)} -pin  "FRAME:for:mux#12" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(12)} -pin  "FRAME:for:mux#12" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(13)} -pin  "FRAME:for:mux#12" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(14)} -pin  "FRAME:for:mux#12" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(15)} -pin  "FRAME:for:mux#12" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm#3} -pin  "FRAME:for:mux#12" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#3}
+load net {FRAME:for:mux#12.itm(0)} -pin  "FRAME:for:mux#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(1)} -pin  "FRAME:for:mux#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(2)} -pin  "FRAME:for:mux#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(3)} -pin  "FRAME:for:mux#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(4)} -pin  "FRAME:for:mux#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(5)} -pin  "FRAME:for:mux#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(6)} -pin  "FRAME:for:mux#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(7)} -pin  "FRAME:for:mux#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(8)} -pin  "FRAME:for:mux#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(9)} -pin  "FRAME:for:mux#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(10)} -pin  "FRAME:for:mux#12" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(11)} -pin  "FRAME:for:mux#12" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(12)} -pin  "FRAME:for:mux#12" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(13)} -pin  "FRAME:for:mux#12" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(14)} -pin  "FRAME:for:mux#12" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(15)} -pin  "FRAME:for:mux#12" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load inst "FRAME:for:acc#22" "add(12,1,16,-1,16)" "INTERFACE" -attr xrf 25883 -attr oid 1179 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#22} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,13,1,16)"
+load net {FRAME:for:acc#26.itm#1(0)} -pin  "FRAME:for:acc#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(1)} -pin  "FRAME:for:acc#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(2)} -pin  "FRAME:for:acc#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(3)} -pin  "FRAME:for:acc#22" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(4)} -pin  "FRAME:for:acc#22" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(5)} -pin  "FRAME:for:acc#22" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(6)} -pin  "FRAME:for:acc#22" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(7)} -pin  "FRAME:for:acc#22" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(8)} -pin  "FRAME:for:acc#22" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(9)} -pin  "FRAME:for:acc#22" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(10)} -pin  "FRAME:for:acc#22" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(11)} -pin  "FRAME:for:acc#22" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:mux#12.itm(0)} -pin  "FRAME:for:acc#22" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(1)} -pin  "FRAME:for:acc#22" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(2)} -pin  "FRAME:for:acc#22" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(3)} -pin  "FRAME:for:acc#22" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(4)} -pin  "FRAME:for:acc#22" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(5)} -pin  "FRAME:for:acc#22" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(6)} -pin  "FRAME:for:acc#22" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(7)} -pin  "FRAME:for:acc#22" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(8)} -pin  "FRAME:for:acc#22" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(9)} -pin  "FRAME:for:acc#22" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(10)} -pin  "FRAME:for:acc#22" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(11)} -pin  "FRAME:for:acc#22" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(12)} -pin  "FRAME:for:acc#22" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(13)} -pin  "FRAME:for:acc#22" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(14)} -pin  "FRAME:for:acc#22" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(15)} -pin  "FRAME:for:acc#22" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {in(2).sva#3(0)} -pin  "FRAME:for:acc#22" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(1)} -pin  "FRAME:for:acc#22" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(2)} -pin  "FRAME:for:acc#22" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(3)} -pin  "FRAME:for:acc#22" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(4)} -pin  "FRAME:for:acc#22" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(5)} -pin  "FRAME:for:acc#22" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(6)} -pin  "FRAME:for:acc#22" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(7)} -pin  "FRAME:for:acc#22" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(8)} -pin  "FRAME:for:acc#22" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(9)} -pin  "FRAME:for:acc#22" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(10)} -pin  "FRAME:for:acc#22" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(11)} -pin  "FRAME:for:acc#22" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(12)} -pin  "FRAME:for:acc#22" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(13)} -pin  "FRAME:for:acc#22" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(14)} -pin  "FRAME:for:acc#22" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(15)} -pin  "FRAME:for:acc#22" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load inst "FRAME:for:mux#11" "mux(2,16)" "INTERFACE" -attr xrf 25884 -attr oid 1180 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:slc(in(0).sva).itm#1(0)} -pin  "FRAME:for:mux#11" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(1)} -pin  "FRAME:for:mux#11" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(2)} -pin  "FRAME:for:mux#11" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(3)} -pin  "FRAME:for:mux#11" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(4)} -pin  "FRAME:for:mux#11" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(5)} -pin  "FRAME:for:mux#11" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(6)} -pin  "FRAME:for:mux#11" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(7)} -pin  "FRAME:for:mux#11" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(8)} -pin  "FRAME:for:mux#11" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(9)} -pin  "FRAME:for:mux#11" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(10)} -pin  "FRAME:for:mux#11" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -pin  "FRAME:for:mux#11" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -pin  "FRAME:for:mux#11" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -pin  "FRAME:for:mux#11" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -pin  "FRAME:for:mux#11" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -pin  "FRAME:for:mux#11" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {in(0).sva#1(0)} -pin  "FRAME:for:mux#11" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(1)} -pin  "FRAME:for:mux#11" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(2)} -pin  "FRAME:for:mux#11" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(3)} -pin  "FRAME:for:mux#11" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(4)} -pin  "FRAME:for:mux#11" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(5)} -pin  "FRAME:for:mux#11" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(6)} -pin  "FRAME:for:mux#11" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(7)} -pin  "FRAME:for:mux#11" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(8)} -pin  "FRAME:for:mux#11" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(9)} -pin  "FRAME:for:mux#11" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(10)} -pin  "FRAME:for:mux#11" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(11)} -pin  "FRAME:for:mux#11" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(12)} -pin  "FRAME:for:mux#11" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(13)} -pin  "FRAME:for:mux#11" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(14)} -pin  "FRAME:for:mux#11" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(15)} -pin  "FRAME:for:mux#11" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm#3} -pin  "FRAME:for:mux#11" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#3}
+load net {FRAME:for:mux#11.itm(0)} -pin  "FRAME:for:mux#11" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(1)} -pin  "FRAME:for:mux#11" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(2)} -pin  "FRAME:for:mux#11" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(3)} -pin  "FRAME:for:mux#11" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(4)} -pin  "FRAME:for:mux#11" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(5)} -pin  "FRAME:for:mux#11" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(6)} -pin  "FRAME:for:mux#11" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(7)} -pin  "FRAME:for:mux#11" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(8)} -pin  "FRAME:for:mux#11" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(9)} -pin  "FRAME:for:mux#11" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(10)} -pin  "FRAME:for:mux#11" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(11)} -pin  "FRAME:for:mux#11" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(12)} -pin  "FRAME:for:mux#11" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(13)} -pin  "FRAME:for:mux#11" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(14)} -pin  "FRAME:for:mux#11" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(15)} -pin  "FRAME:for:mux#11" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load inst "FRAME:for:acc#20" "add(13,1,16,-1,16)" "INTERFACE" -attr xrf 25885 -attr oid 1181 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#20} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,13,1,16)"
+load net {FRAME:for:acc#24.itm#1(0)} -pin  "FRAME:for:acc#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(1)} -pin  "FRAME:for:acc#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(2)} -pin  "FRAME:for:acc#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(3)} -pin  "FRAME:for:acc#20" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(4)} -pin  "FRAME:for:acc#20" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(5)} -pin  "FRAME:for:acc#20" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(6)} -pin  "FRAME:for:acc#20" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(7)} -pin  "FRAME:for:acc#20" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(8)} -pin  "FRAME:for:acc#20" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(9)} -pin  "FRAME:for:acc#20" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(10)} -pin  "FRAME:for:acc#20" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(11)} -pin  "FRAME:for:acc#20" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(12)} -pin  "FRAME:for:acc#20" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:mux#11.itm(0)} -pin  "FRAME:for:acc#20" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(1)} -pin  "FRAME:for:acc#20" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(2)} -pin  "FRAME:for:acc#20" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(3)} -pin  "FRAME:for:acc#20" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(4)} -pin  "FRAME:for:acc#20" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(5)} -pin  "FRAME:for:acc#20" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(6)} -pin  "FRAME:for:acc#20" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(7)} -pin  "FRAME:for:acc#20" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(8)} -pin  "FRAME:for:acc#20" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(9)} -pin  "FRAME:for:acc#20" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(10)} -pin  "FRAME:for:acc#20" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(11)} -pin  "FRAME:for:acc#20" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(12)} -pin  "FRAME:for:acc#20" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(13)} -pin  "FRAME:for:acc#20" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(14)} -pin  "FRAME:for:acc#20" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(15)} -pin  "FRAME:for:acc#20" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {in(0).sva#3(0)} -pin  "FRAME:for:acc#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(1)} -pin  "FRAME:for:acc#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(2)} -pin  "FRAME:for:acc#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(3)} -pin  "FRAME:for:acc#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(4)} -pin  "FRAME:for:acc#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(5)} -pin  "FRAME:for:acc#20" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(6)} -pin  "FRAME:for:acc#20" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(7)} -pin  "FRAME:for:acc#20" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(8)} -pin  "FRAME:for:acc#20" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(9)} -pin  "FRAME:for:acc#20" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(10)} -pin  "FRAME:for:acc#20" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(11)} -pin  "FRAME:for:acc#20" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(12)} -pin  "FRAME:for:acc#20" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(13)} -pin  "FRAME:for:acc#20" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(14)} -pin  "FRAME:for:acc#20" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(15)} -pin  "FRAME:for:acc#20" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load inst "FRAME:for:acc" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 25886 -attr oid 1182 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2)"
+load net {i#6.sva#2(0)} -pin  "FRAME:for:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "FRAME:for:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {PWR} -pin  "FRAME:for:acc" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:for:acc.itm(0)} -pin  "FRAME:for:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+load inst "FRAME:for:or" "or(2,1)" "INTERFACE" -attr xrf 25887 -attr oid 1183 -attr @path {/sobel/sobel:core/FRAME:for:or} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "FRAME:for:or" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {exit:FRAME#1.sva} -pin  "FRAME:for:or" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {exit:FRAME:for.lpi#1.dfm#4} -pin  "FRAME:for:or" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#4}
+load inst "FRAME:for:acc#16" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 25888 -attr oid 1184 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#16} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:for:acc#16" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {i#6.sva#2(0)} -pin  "FRAME:for:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "FRAME:for:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load inst "not#27" "not(1)" "INTERFACE" -attr xrf 25889 -attr oid 1185 -attr @path {/sobel/sobel:core/not#27} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1.dfm#4} -pin  "not#27" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#4}
+load net {not#27.itm} -pin  "not#27" {Z(0)} -attr @path {/sobel/sobel:core/not#27.itm}
+load inst "FRAME:for:and#1" "and(2,2)" "INTERFACE" -attr xrf 25890 -attr oid 1186 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#1} -attr area 1.459665 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2)"
+load net {i#6.sva#1(0)} -pin  "FRAME:for:and#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "FRAME:for:and#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {not#27.itm} -pin  "FRAME:for:and#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#19.itm}
+load net {not#27.itm} -pin  "FRAME:for:and#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#19.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:and#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:and#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load inst "mux#3" "mux(2,3)" "INTERFACE" -attr xrf 25891 -attr oid 1187 -attr vt d -attr @path {/sobel/sobel:core/mux#3} -attr area 2.759269 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(3,1,2)"
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(0)} -pin  "mux#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(1)} -pin  "mux#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(2)} -pin  "mux#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#176.itm(2)} -pin  "mux#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.sva).itm}
+load net {ACC1:acc#176.itm(3)} -pin  "mux#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.sva).itm}
+load net {ACC1:acc#176.itm(4)} -pin  "mux#3" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.sva).itm}
+load net {and.cse} -pin  "mux#3" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(0)} -pin  "mux#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(1)} -pin  "mux#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(2)} -pin  "mux#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load inst "mux#4" "mux(2,12)" "INTERFACE" -attr xrf 25892 -attr oid 1188 -attr vt d -attr @path {/sobel/sobel:core/mux#4} -attr area 11.034076 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(12,1,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm(0)} -pin  "mux#4" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(1)} -pin  "mux#4" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(2)} -pin  "mux#4" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(3)} -pin  "mux#4" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(4)} -pin  "mux#4" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(5)} -pin  "mux#4" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(6)} -pin  "mux#4" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(7)} -pin  "mux#4" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(8)} -pin  "mux#4" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(9)} -pin  "mux#4" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(10)} -pin  "mux#4" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(11)} -pin  "mux#4" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.sva(0)} -pin  "mux#4" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(1)} -pin  "mux#4" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(2)} -pin  "mux#4" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(3)} -pin  "mux#4" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(4)} -pin  "mux#4" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(5)} -pin  "mux#4" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(6)} -pin  "mux#4" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(7)} -pin  "mux#4" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(8)} -pin  "mux#4" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(9)} -pin  "mux#4" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(10)} -pin  "mux#4" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(11)} -pin  "mux#4" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {and.cse} -pin  "mux#4" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(0)} -pin  "mux#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(1)} -pin  "mux#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(2)} -pin  "mux#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(3)} -pin  "mux#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} -pin  "mux#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(5)} -pin  "mux#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -pin  "mux#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(7)} -pin  "mux#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} -pin  "mux#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(9)} -pin  "mux#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} -pin  "mux#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "mux#4" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load inst "mux#5" "mux(2,2)" "INTERFACE" -attr xrf 25893 -attr oid 1189 -attr vt d -attr @path {/sobel/sobel:core/mux#5} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1(0)} -pin  "mux#5" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1(1)} -pin  "mux#5" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp.sva(1)} -pin  "mux#5" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp.sva).itm}
+load net {ACC1:acc#118.psp.sva(2)} -pin  "mux#5" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp.sva).itm}
+load net {and.cse} -pin  "mux#5" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(0)} -pin  "mux#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(1)} -pin  "mux#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0}
+load inst "mux#6" "mux(2,30)" "INTERFACE" -attr xrf 25894 -attr oid 1190 -attr vt d -attr @path {/sobel/sobel:core/mux#6} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {regs.regs(2).lpi#1.dfm.sg2(0)} -pin  "mux#6" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(1)} -pin  "mux#6" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(2)} -pin  "mux#6" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(3)} -pin  "mux#6" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(4)} -pin  "mux#6" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(5)} -pin  "mux#6" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(6)} -pin  "mux#6" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(7)} -pin  "mux#6" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(8)} -pin  "mux#6" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(9)} -pin  "mux#6" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(10)} -pin  "mux#6" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(11)} -pin  "mux#6" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(12)} -pin  "mux#6" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(13)} -pin  "mux#6" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(14)} -pin  "mux#6" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(15)} -pin  "mux#6" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(16)} -pin  "mux#6" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(17)} -pin  "mux#6" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(18)} -pin  "mux#6" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(19)} -pin  "mux#6" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(20)} -pin  "mux#6" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(21)} -pin  "mux#6" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(22)} -pin  "mux#6" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(23)} -pin  "mux#6" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(24)} -pin  "mux#6" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(25)} -pin  "mux#6" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(26)} -pin  "mux#6" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(27)} -pin  "mux#6" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(28)} -pin  "mux#6" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(29)} -pin  "mux#6" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(1).sva(60)} -pin  "mux#6" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(61)} -pin  "mux#6" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(62)} -pin  "mux#6" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(63)} -pin  "mux#6" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(64)} -pin  "mux#6" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(65)} -pin  "mux#6" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(66)} -pin  "mux#6" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(67)} -pin  "mux#6" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(68)} -pin  "mux#6" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(69)} -pin  "mux#6" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(70)} -pin  "mux#6" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(71)} -pin  "mux#6" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(72)} -pin  "mux#6" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(73)} -pin  "mux#6" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(74)} -pin  "mux#6" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(75)} -pin  "mux#6" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(76)} -pin  "mux#6" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(77)} -pin  "mux#6" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(78)} -pin  "mux#6" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(79)} -pin  "mux#6" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(80)} -pin  "mux#6" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(81)} -pin  "mux#6" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(82)} -pin  "mux#6" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(83)} -pin  "mux#6" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(84)} -pin  "mux#6" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(85)} -pin  "mux#6" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(86)} -pin  "mux#6" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(87)} -pin  "mux#6" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(88)} -pin  "mux#6" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(89)} -pin  "mux#6" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {and.cse} -pin  "mux#6" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(0)} -pin  "mux#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(1)} -pin  "mux#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(2)} -pin  "mux#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(3)} -pin  "mux#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(4)} -pin  "mux#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(5)} -pin  "mux#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(6)} -pin  "mux#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(7)} -pin  "mux#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(8)} -pin  "mux#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(9)} -pin  "mux#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(10)} -pin  "mux#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(11)} -pin  "mux#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(12)} -pin  "mux#6" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(13)} -pin  "mux#6" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(14)} -pin  "mux#6" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(15)} -pin  "mux#6" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(16)} -pin  "mux#6" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(17)} -pin  "mux#6" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(18)} -pin  "mux#6" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(19)} -pin  "mux#6" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(20)} -pin  "mux#6" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(21)} -pin  "mux#6" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(22)} -pin  "mux#6" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(23)} -pin  "mux#6" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(24)} -pin  "mux#6" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(25)} -pin  "mux#6" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(26)} -pin  "mux#6" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(27)} -pin  "mux#6" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(28)} -pin  "mux#6" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(29)} -pin  "mux#6" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load inst "mux#7" "mux(2,30)" "INTERFACE" -attr xrf 25895 -attr oid 1191 -attr vt d -attr @path {/sobel/sobel:core/mux#7} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {regs.regs(2).lpi#1.dfm#1(0)} -pin  "mux#7" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(1)} -pin  "mux#7" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(2)} -pin  "mux#7" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(3)} -pin  "mux#7" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(4)} -pin  "mux#7" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(5)} -pin  "mux#7" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(6)} -pin  "mux#7" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(7)} -pin  "mux#7" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(8)} -pin  "mux#7" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(9)} -pin  "mux#7" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(10)} -pin  "mux#7" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(11)} -pin  "mux#7" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(12)} -pin  "mux#7" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(13)} -pin  "mux#7" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(14)} -pin  "mux#7" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(15)} -pin  "mux#7" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(16)} -pin  "mux#7" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(17)} -pin  "mux#7" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(18)} -pin  "mux#7" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(19)} -pin  "mux#7" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(20)} -pin  "mux#7" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(21)} -pin  "mux#7" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(22)} -pin  "mux#7" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(23)} -pin  "mux#7" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(24)} -pin  "mux#7" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(25)} -pin  "mux#7" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(26)} -pin  "mux#7" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(27)} -pin  "mux#7" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(28)} -pin  "mux#7" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(29)} -pin  "mux#7" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(1).sva(0)} -pin  "mux#7" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(1)} -pin  "mux#7" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(2)} -pin  "mux#7" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(3)} -pin  "mux#7" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(4)} -pin  "mux#7" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(5)} -pin  "mux#7" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(6)} -pin  "mux#7" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(7)} -pin  "mux#7" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(8)} -pin  "mux#7" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(9)} -pin  "mux#7" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(10)} -pin  "mux#7" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(11)} -pin  "mux#7" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(12)} -pin  "mux#7" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(13)} -pin  "mux#7" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(14)} -pin  "mux#7" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(15)} -pin  "mux#7" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(16)} -pin  "mux#7" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(17)} -pin  "mux#7" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(18)} -pin  "mux#7" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(19)} -pin  "mux#7" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(20)} -pin  "mux#7" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(21)} -pin  "mux#7" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(22)} -pin  "mux#7" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(23)} -pin  "mux#7" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(24)} -pin  "mux#7" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(25)} -pin  "mux#7" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(26)} -pin  "mux#7" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(27)} -pin  "mux#7" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(28)} -pin  "mux#7" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(29)} -pin  "mux#7" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {and.cse} -pin  "mux#7" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(0)} -pin  "mux#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(1)} -pin  "mux#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(2)} -pin  "mux#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(3)} -pin  "mux#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(4)} -pin  "mux#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(5)} -pin  "mux#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(6)} -pin  "mux#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(7)} -pin  "mux#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(8)} -pin  "mux#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(9)} -pin  "mux#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(10)} -pin  "mux#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(11)} -pin  "mux#7" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(12)} -pin  "mux#7" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(13)} -pin  "mux#7" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(14)} -pin  "mux#7" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(15)} -pin  "mux#7" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(16)} -pin  "mux#7" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(17)} -pin  "mux#7" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(18)} -pin  "mux#7" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(19)} -pin  "mux#7" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(20)} -pin  "mux#7" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(21)} -pin  "mux#7" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(22)} -pin  "mux#7" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(23)} -pin  "mux#7" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(24)} -pin  "mux#7" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(25)} -pin  "mux#7" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(26)} -pin  "mux#7" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(27)} -pin  "mux#7" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(28)} -pin  "mux#7" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(29)} -pin  "mux#7" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load inst "mux#8" "mux(2,90)" "INTERFACE" -attr xrf 25896 -attr oid 1192 -attr vt d -attr @path {/sobel/sobel:core/mux#8} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(1).sva(0)} -pin  "mux#8" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "mux#8" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "mux#8" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "mux#8" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "mux#8" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "mux#8" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "mux#8" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "mux#8" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "mux#8" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "mux#8" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "mux#8" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "mux#8" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "mux#8" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "mux#8" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "mux#8" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "mux#8" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "mux#8" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "mux#8" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "mux#8" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "mux#8" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "mux#8" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "mux#8" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "mux#8" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "mux#8" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "mux#8" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "mux#8" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "mux#8" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "mux#8" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "mux#8" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "mux#8" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "mux#8" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "mux#8" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "mux#8" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "mux#8" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "mux#8" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "mux#8" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "mux#8" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "mux#8" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "mux#8" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "mux#8" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "mux#8" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "mux#8" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "mux#8" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "mux#8" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "mux#8" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "mux#8" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "mux#8" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "mux#8" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "mux#8" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "mux#8" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "mux#8" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "mux#8" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "mux#8" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "mux#8" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "mux#8" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "mux#8" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "mux#8" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "mux#8" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "mux#8" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "mux#8" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "mux#8" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "mux#8" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "mux#8" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "mux#8" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "mux#8" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "mux#8" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "mux#8" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "mux#8" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "mux#8" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "mux#8" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "mux#8" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "mux#8" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "mux#8" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "mux#8" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "mux#8" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "mux#8" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "mux#8" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "mux#8" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "mux#8" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "mux#8" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "mux#8" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "mux#8" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "mux#8" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "mux#8" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "mux#8" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "mux#8" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "mux#8" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "mux#8" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "mux#8" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "mux#8" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -pin  "mux#8" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#8" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#8" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#8" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#8" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#8" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#8" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#8" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#8" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#8" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#8" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#8" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#8" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#8" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#8" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#8" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#8" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#8" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#8" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#8" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#8" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#8" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#8" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#8" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#8" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#8" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#8" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#8" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#8" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#8" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#8" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#8" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#8" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#8" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#8" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#8" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#8" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#8" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#8" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#8" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#8" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#8" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#8" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#8" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#8" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#8" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#8" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#8" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#8" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#8" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#8" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#8" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#8" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#8" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#8" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#8" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#8" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#8" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#8" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#8" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#8" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#8" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#8" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#8" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#8" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#8" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#8" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#8" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#8" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#8" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#8" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#8" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#8" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#8" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#8" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#8" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#8" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#8" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#8" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#8" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#8" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#8" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#8" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#8" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#8" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#8" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#8" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#8" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#8" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#8" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {and.cse} -pin  "mux#8" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "mux#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "mux#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "mux#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "mux#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "mux#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "mux#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "mux#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "mux#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "mux#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "mux#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "mux#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "mux#8" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "mux#8" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "mux#8" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "mux#8" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "mux#8" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "mux#8" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "mux#8" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "mux#8" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "mux#8" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "mux#8" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "mux#8" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "mux#8" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "mux#8" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "mux#8" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "mux#8" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "mux#8" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "mux#8" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "mux#8" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "mux#8" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "mux#8" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "mux#8" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "mux#8" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "mux#8" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "mux#8" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "mux#8" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "mux#8" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "mux#8" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "mux#8" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "mux#8" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "mux#8" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "mux#8" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "mux#8" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "mux#8" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "mux#8" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "mux#8" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "mux#8" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "mux#8" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "mux#8" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "mux#8" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "mux#8" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "mux#8" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "mux#8" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "mux#8" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "mux#8" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "mux#8" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "mux#8" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "mux#8" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "mux#8" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "mux#8" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "mux#8" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "mux#8" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "mux#8" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "mux#8" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "mux#8" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "mux#8" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "mux#8" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "mux#8" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "mux#8" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "mux#8" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "mux#8" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "mux#8" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "mux#8" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "mux#8" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "mux#8" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "mux#8" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "mux#8" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "mux#8" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "mux#8" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "mux#8" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "mux#8" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "mux#8" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "mux#8" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "mux#8" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "mux#8" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "mux#8" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "mux#8" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "mux#8" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "mux#8" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "mux#8" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load inst "mux#9" "mux(2,90)" "INTERFACE" -attr xrf 25897 -attr oid 1193 -attr vt d -attr @path {/sobel/sobel:core/mux#9} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(0).sva(0)} -pin  "mux#9" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#9" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#9" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#9" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#9" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#9" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#9" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#9" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#9" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#9" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#9" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#9" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#9" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#9" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#9" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#9" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#9" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#9" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#9" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#9" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#9" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#9" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#9" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#9" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#9" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#9" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#9" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#9" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#9" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#9" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#9" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#9" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#9" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#9" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#9" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#9" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#9" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#9" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#9" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#9" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#9" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#9" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#9" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#9" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#9" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#9" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#9" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#9" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#9" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#9" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#9" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#9" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#9" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#9" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#9" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#9" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#9" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#9" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#9" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#9" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#9" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#9" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#9" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#9" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#9" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#9" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#9" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#9" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#9" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#9" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#9" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#9" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#9" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#9" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#9" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#9" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#9" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#9" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#9" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#9" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#9" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#9" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#9" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#9" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#9" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#9" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#9" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#9" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#9" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#9" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "mux#9" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "mux#9" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "mux#9" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "mux#9" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "mux#9" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "mux#9" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "mux#9" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "mux#9" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "mux#9" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "mux#9" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "mux#9" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "mux#9" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "mux#9" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "mux#9" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "mux#9" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "mux#9" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "mux#9" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "mux#9" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "mux#9" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "mux#9" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "mux#9" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "mux#9" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "mux#9" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "mux#9" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "mux#9" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "mux#9" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "mux#9" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "mux#9" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "mux#9" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "mux#9" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "mux#9" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "mux#9" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "mux#9" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "mux#9" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "mux#9" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "mux#9" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "mux#9" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "mux#9" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "mux#9" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "mux#9" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "mux#9" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "mux#9" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "mux#9" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "mux#9" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "mux#9" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "mux#9" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "mux#9" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "mux#9" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "mux#9" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "mux#9" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "mux#9" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "mux#9" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "mux#9" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "mux#9" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "mux#9" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "mux#9" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "mux#9" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "mux#9" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "mux#9" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "mux#9" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "mux#9" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "mux#9" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "mux#9" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "mux#9" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "mux#9" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "mux#9" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "mux#9" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "mux#9" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "mux#9" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "mux#9" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "mux#9" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "mux#9" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "mux#9" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "mux#9" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "mux#9" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "mux#9" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "mux#9" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "mux#9" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "mux#9" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "mux#9" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "mux#9" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "mux#9" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "mux#9" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "mux#9" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "mux#9" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "mux#9" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "mux#9" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "mux#9" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "mux#9" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "mux#9" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {and.cse} -pin  "mux#9" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "mux#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "mux#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "mux#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "mux#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "mux#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "mux#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "mux#9" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "mux#9" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "mux#9" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "mux#9" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "mux#9" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "mux#9" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "mux#9" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "mux#9" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "mux#9" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "mux#9" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "mux#9" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "mux#9" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "mux#9" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "mux#9" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "mux#9" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "mux#9" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "mux#9" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "mux#9" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "mux#9" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "mux#9" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "mux#9" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "mux#9" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "mux#9" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "mux#9" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "mux#9" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "mux#9" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "mux#9" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "mux#9" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "mux#9" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "mux#9" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "mux#9" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "mux#9" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "mux#9" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "mux#9" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "mux#9" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "mux#9" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "mux#9" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "mux#9" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "mux#9" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "mux#9" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "mux#9" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "mux#9" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "mux#9" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "mux#9" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "mux#9" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "mux#9" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "mux#9" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "mux#9" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "mux#9" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "mux#9" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "mux#9" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "mux#9" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "mux#9" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "mux#9" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "mux#9" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "mux#9" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "mux#9" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "mux#9" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "mux#9" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "mux#9" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "mux#9" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "mux#9" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "mux#9" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "mux#9" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "mux#9" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "mux#9" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "mux#9" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "mux#9" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "mux#9" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "mux#9" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "mux#9" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "mux#9" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "mux#9" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "mux#9" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "mux#9" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "mux#9" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "mux#9" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "mux#9" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "mux#9" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "mux#9" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "mux#9" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "mux#9" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "mux#9" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "mux#9" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load inst "ACC1-3:not#57" "not(1)" "INTERFACE" -attr xrf 25898 -attr oid 1194 -attr @path {/sobel/sobel:core/ACC1-3:not#57} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#178.itm(2)} -pin  "ACC1-3:not#57" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#1.itm}
+load net {ACC1-3:not#57.itm} -pin  "ACC1-3:not#57" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#57.itm}
+load inst "ACC1-3:not#58" "not(1)" "INTERFACE" -attr xrf 25899 -attr oid 1195 -attr @path {/sobel/sobel:core/ACC1-3:not#58} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#178.itm(3)} -pin  "ACC1-3:not#58" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#2.itm}
+load net {ACC1-3:not#58.itm} -pin  "ACC1-3:not#58" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#58.itm}
+load inst "ACC1:acc#179" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 25900 -attr oid 1196 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#179" {A(0)} -attr @path {/sobel/sobel:core/conc#683.itm}
+load net {ACC1:acc#178.itm(1)} -pin  "ACC1:acc#179" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#683.itm}
+load net {PWR} -pin  "ACC1:acc#179" {A(2)} -attr @path {/sobel/sobel:core/conc#683.itm}
+load net {ACC1-3:not#58.itm} -pin  "ACC1:acc#179" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#531.itm}
+load net {ACC1-3:not#57.itm} -pin  "ACC1:acc#179" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#531.itm}
+load net {ACC1:acc#179.itm(0)} -pin  "ACC1:acc#179" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(1)} -pin  "ACC1:acc#179" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(2)} -pin  "ACC1:acc#179" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load inst "mux#10" "mux(2,2)" "INTERFACE" -attr xrf 25901 -attr oid 1197 -attr vt d -attr @path {/sobel/sobel:core/mux#10} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {acc.imod#7.lpi#1.dfm(0)} -pin  "mux#10" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm}
+load net {acc.imod#7.lpi#1.dfm(1)} -pin  "mux#10" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm}
+load net {ACC1:acc#179.itm(1)} -pin  "mux#10" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#45.itm}
+load net {ACC1:acc#179.itm(2)} -pin  "mux#10" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#45.itm}
+load net {and.cse} -pin  "mux#10" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {acc.imod#7.lpi#1.dfm:mx0(0)} -pin  "mux#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm:mx0}
+load net {acc.imod#7.lpi#1.dfm:mx0(1)} -pin  "mux#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm:mx0}
+load inst "mux#11" "mux(2,2)" "INTERFACE" -attr xrf 25902 -attr oid 1198 -attr vt d -attr @path {/sobel/sobel:core/mux#11} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {acc.imod#6.lpi#1.dfm.sg1(0)} -pin  "mux#11" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1}
+load net {acc.imod#6.lpi#1.dfm.sg1(1)} -pin  "mux#11" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1}
+load net {ACC1:acc#178.itm(2)} -pin  "mux#11" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#3.itm}
+load net {ACC1:acc#178.itm(3)} -pin  "mux#11" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#3.itm}
+load net {and.cse} -pin  "mux#11" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(0)} -pin  "mux#11" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1:mx0}
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(1)} -pin  "mux#11" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1:mx0}
+load inst "ACC1-1:not#147" "not(2)" "INTERFACE" -attr xrf 25903 -attr oid 1199 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#147} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#118.psp#1.sva(1)} -pin  "ACC1-1:not#147" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp#1.sva).itm}
+load net {ACC1:acc#118.psp#1.sva(2)} -pin  "ACC1-1:not#147" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp#1.sva).itm}
+load net {ACC1-1:not#147.itm(0)} -pin  "ACC1-1:not#147" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#147.itm}
+load net {ACC1-1:not#147.itm(1)} -pin  "ACC1-1:not#147" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#147.itm}
+load inst "ACC1:acc#150" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 25904 -attr oid 1200 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#150" {A(0)} -attr @path {/sobel/sobel:core/conc#684.itm}
+load net {ACC1-1:not#147.itm(0)} -pin  "ACC1:acc#150" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#684.itm}
+load net {ACC1-1:not#147.itm(1)} -pin  "ACC1:acc#150" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#684.itm}
+load net {PWR} -pin  "ACC1:acc#150" {B(0)} -attr @path {/sobel/sobel:core/conc#685.itm}
+load net {ACC1:acc#118.psp#1.sva(0)} -pin  "ACC1:acc#150" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#685.itm}
+load net {ACC1:acc#150.itm(0)} -pin  "ACC1:acc#150" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load net {ACC1:acc#150.itm(1)} -pin  "ACC1:acc#150" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load net {ACC1:acc#150.itm(2)} -pin  "ACC1:acc#150" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load net {ACC1:acc#150.itm(3)} -pin  "ACC1:acc#150" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load inst "ACC1-1:not#137" "not(1)" "INTERFACE" -attr xrf 25905 -attr oid 1201 -attr @path {/sobel/sobel:core/ACC1-1:not#137} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#148.itm(2)} -pin  "ACC1-1:not#137" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.sva)#2.itm}
+load net {ACC1-1:not#137.itm} -pin  "ACC1-1:not#137" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#137.itm}
+load inst "ACC1:acc#149" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25906 -attr oid 1202 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#149" {A(0)} -attr @path {/sobel/sobel:core/conc#686.itm}
+load net {ACC1:acc#148.itm(1)} -pin  "ACC1:acc#149" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#686.itm}
+load net {ACC1:acc#148.itm(3)} -pin  "ACC1:acc#149" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#472.itm}
+load net {ACC1-1:not#137.itm} -pin  "ACC1:acc#149" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#472.itm}
+load net {ACC1:acc#149.itm(0)} -pin  "ACC1:acc#149" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149.itm}
+load net {ACC1:acc#149.itm(1)} -pin  "ACC1:acc#149" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149.itm}
+load net {ACC1:acc#149.itm(2)} -pin  "ACC1:acc#149" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149.itm}
+load inst "ACC1-1:not#154" "not(1)" "INTERFACE" -attr xrf 25907 -attr oid 1203 -attr @path {/sobel/sobel:core/ACC1-1:not#154} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#148.itm(4)} -pin  "ACC1-1:not#154" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.sva)#4.itm}
+load net {ACC1-1:not#154.itm} -pin  "ACC1-1:not#154" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#154.itm}
+load inst "ACC1-1:acc#118" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 25908 -attr oid 1204 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#118} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#149.itm(1)} -pin  "ACC1-1:acc#118" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#19.itm}
+load net {ACC1:acc#149.itm(2)} -pin  "ACC1-1:acc#118" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#19.itm}
+load net {ACC1-1:not#154.itm} -pin  "ACC1-1:acc#118" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#154.itm}
+load net {ACC1:acc#118.psp#1.sva(0)} -pin  "ACC1-1:acc#118" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.sva}
+load net {ACC1:acc#118.psp#1.sva(1)} -pin  "ACC1-1:acc#118" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.sva}
+load net {ACC1:acc#118.psp#1.sva(2)} -pin  "ACC1-1:acc#118" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.sva}
+load inst "ACC1-1:not#115" "not(1)" "INTERFACE" -attr xrf 25909 -attr oid 1205 -attr @path {/sobel/sobel:core/ACC1-1:not#115} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp#1.sva(0)} -pin  "ACC1-1:not#115" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva).itm}
+load net {ACC1-1:not#115.itm} -pin  "ACC1-1:not#115" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#115.itm}
+load inst "ACC1-1:not#116" "not(1)" "INTERFACE" -attr xrf 25910 -attr oid 1206 -attr @path {/sobel/sobel:core/ACC1-1:not#116} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp#1.sva(2)} -pin  "ACC1-1:not#116" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#2.itm}
+load net {ACC1-1:not#116.itm} -pin  "ACC1-1:not#116" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#116.itm}
+load inst "ACC1-1:not#118" "not(1)" "INTERFACE" -attr xrf 25911 -attr oid 1207 -attr @path {/sobel/sobel:core/ACC1-1:not#118} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp#1.sva(6)} -pin  "ACC1-1:not#118" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#3.itm}
+load net {ACC1-1:not#118.itm} -pin  "ACC1-1:not#118" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#118.itm}
+load inst "ACC1:acc#145" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25912 -attr oid 1208 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#145" {A(0)} -attr @path {/sobel/sobel:core/conc#689.itm}
+load net {ACC1:acc#125.psp#1.sva(1)} -pin  "ACC1:acc#145" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#689.itm}
+load net {ACC1-1:not#118.itm} -pin  "ACC1:acc#145" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#464.itm}
+load net {ACC1-1:not#116.itm} -pin  "ACC1:acc#145" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#464.itm}
+load net {ACC1:acc#145.itm(0)} -pin  "ACC1:acc#145" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145.itm}
+load net {ACC1:acc#145.itm(1)} -pin  "ACC1:acc#145" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145.itm}
+load net {ACC1:acc#145.itm(2)} -pin  "ACC1:acc#145" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145.itm}
+load inst "ACC1-1:not#119" "not(1)" "INTERFACE" -attr xrf 25913 -attr oid 1209 -attr @path {/sobel/sobel:core/ACC1-1:not#119} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp#1.sva(8)} -pin  "ACC1-1:not#119" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#4.itm}
+load net {ACC1-1:not#119.itm} -pin  "ACC1-1:not#119" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#119.itm}
+load inst "ACC1:acc#147" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 25914 -attr oid 1210 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#147" {A(0)} -attr @path {/sobel/sobel:core/conc#688.itm}
+load net {ACC1-1:not#115.itm} -pin  "ACC1:acc#147" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#688.itm}
+load net {GND} -pin  "ACC1:acc#147" {A(2)} -attr @path {/sobel/sobel:core/conc#688.itm}
+load net {PWR} -pin  "ACC1:acc#147" {A(3)} -attr @path {/sobel/sobel:core/conc#688.itm}
+load net {ACC1-1:not#119.itm} -pin  "ACC1:acc#147" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#468.itm}
+load net {ACC1:acc#145.itm(1)} -pin  "ACC1:acc#147" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#468.itm}
+load net {ACC1:acc#145.itm(2)} -pin  "ACC1:acc#147" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#468.itm}
+load net {ACC1:acc#147.itm(0)} -pin  "ACC1:acc#147" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load net {ACC1:acc#147.itm(1)} -pin  "ACC1:acc#147" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load net {ACC1:acc#147.itm(2)} -pin  "ACC1:acc#147" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load net {ACC1:acc#147.itm(3)} -pin  "ACC1:acc#147" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load inst "ACC1-1:not#117" "not(1)" "INTERFACE" -attr xrf 25915 -attr oid 1211 -attr @path {/sobel/sobel:core/ACC1-1:not#117} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp#1.sva(4)} -pin  "ACC1-1:not#117" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#6.itm}
+load net {ACC1-1:not#117.itm} -pin  "ACC1-1:not#117" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#117.itm}
+load inst "ACC1:acc#144" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25916 -attr oid 1212 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#144" {A(0)} -attr @path {/sobel/sobel:core/conc#691.itm}
+load net {ACC1:acc#125.psp#1.sva(3)} -pin  "ACC1:acc#144" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#691.itm}
+load net {ACC1:acc#125.psp#1.sva(5)} -pin  "ACC1:acc#144" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#462.itm}
+load net {ACC1-1:not#117.itm} -pin  "ACC1:acc#144" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#462.itm}
+load net {ACC1:acc#144.itm(0)} -pin  "ACC1:acc#144" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144.itm}
+load net {ACC1:acc#144.itm(1)} -pin  "ACC1:acc#144" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144.itm}
+load net {ACC1:acc#144.itm(2)} -pin  "ACC1:acc#144" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144.itm}
+load inst "ACC1-1:not#120" "not(2)" "INTERFACE" -attr xrf 25917 -attr oid 1213 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#120} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#125.psp#1.sva(10)} -pin  "ACC1-1:not#120" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#8.itm}
+load net {ACC1:acc#125.psp#1.sva(11)} -pin  "ACC1-1:not#120" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#8.itm}
+load net {ACC1-1:not#120.itm(0)} -pin  "ACC1-1:not#120" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#120.itm}
+load net {ACC1-1:not#120.itm(1)} -pin  "ACC1-1:not#120" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#120.itm}
+load inst "ACC1:acc#146" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 25918 -attr oid 1214 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#146" {A(0)} -attr @path {/sobel/sobel:core/conc#690.itm}
+load net {ACC1:acc#144.itm(1)} -pin  "ACC1:acc#146" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#690.itm}
+load net {ACC1:acc#144.itm(2)} -pin  "ACC1:acc#146" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#690.itm}
+load net {ACC1:acc#125.psp#1.sva(7)} -pin  "ACC1:acc#146" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#466.itm}
+load net {ACC1-1:not#120.itm(0)} -pin  "ACC1:acc#146" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#466.itm}
+load net {ACC1-1:not#120.itm(1)} -pin  "ACC1:acc#146" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#466.itm}
+load net {ACC1:acc#146.itm(0)} -pin  "ACC1:acc#146" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {ACC1:acc#146.itm(1)} -pin  "ACC1:acc#146" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {ACC1:acc#146.itm(2)} -pin  "ACC1:acc#146" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {ACC1:acc#146.itm(3)} -pin  "ACC1:acc#146" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {ACC1:acc#146.itm(4)} -pin  "ACC1:acc#146" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load inst "ACC1:acc#148" "add(4,1,5,-1,5)" "INTERFACE" -attr xrf 25919 -attr oid 1215 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "ACC1:acc#148" {A(0)} -attr @path {/sobel/sobel:core/conc#687.itm}
+load net {ACC1:acc#147.itm(1)} -pin  "ACC1:acc#148" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#687.itm}
+load net {ACC1:acc#147.itm(2)} -pin  "ACC1:acc#148" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#687.itm}
+load net {ACC1:acc#147.itm(3)} -pin  "ACC1:acc#148" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#687.itm}
+load net {ACC1:acc#125.psp#1.sva(9)} -pin  "ACC1:acc#148" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#470.itm}
+load net {ACC1:acc#146.itm(1)} -pin  "ACC1:acc#148" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#470.itm}
+load net {ACC1:acc#146.itm(2)} -pin  "ACC1:acc#148" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#470.itm}
+load net {ACC1:acc#146.itm(3)} -pin  "ACC1:acc#148" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#470.itm}
+load net {ACC1:acc#146.itm(4)} -pin  "ACC1:acc#148" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#470.itm}
+load net {ACC1:acc#148.itm(0)} -pin  "ACC1:acc#148" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {ACC1:acc#148.itm(1)} -pin  "ACC1:acc#148" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {ACC1:acc#148.itm(2)} -pin  "ACC1:acc#148" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {ACC1:acc#148.itm(3)} -pin  "ACC1:acc#148" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {ACC1:acc#148.itm(4)} -pin  "ACC1:acc#148" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load inst "ACC1:not#158" "not(10)" "INTERFACE" -attr xrf 25920 -attr oid 1216 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "ACC1:not#158" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "ACC1:not#158" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "ACC1:not#158" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "ACC1:not#158" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "ACC1:not#158" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "ACC1:not#158" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "ACC1:not#158" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "ACC1:not#158" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "ACC1:not#158" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "ACC1:not#158" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:not#158.itm(0)} -pin  "ACC1:not#158" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(1)} -pin  "ACC1:not#158" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(2)} -pin  "ACC1:not#158" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(3)} -pin  "ACC1:not#158" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(4)} -pin  "ACC1:not#158" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(5)} -pin  "ACC1:not#158" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(6)} -pin  "ACC1:not#158" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(7)} -pin  "ACC1:not#158" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(8)} -pin  "ACC1:not#158" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(9)} -pin  "ACC1:not#158" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load inst "ACC1:not#159" "not(10)" "INTERFACE" -attr xrf 25921 -attr oid 1217 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "ACC1:not#159" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "ACC1:not#159" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "ACC1:not#159" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "ACC1:not#159" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "ACC1:not#159" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "ACC1:not#159" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "ACC1:not#159" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "ACC1:not#159" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "ACC1:not#159" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "ACC1:not#159" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {ACC1:not#159.itm(0)} -pin  "ACC1:not#159" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(1)} -pin  "ACC1:not#159" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(2)} -pin  "ACC1:not#159" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(3)} -pin  "ACC1:not#159" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(4)} -pin  "ACC1:not#159" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(5)} -pin  "ACC1:not#159" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(6)} -pin  "ACC1:not#159" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(7)} -pin  "ACC1:not#159" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(8)} -pin  "ACC1:not#159" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(9)} -pin  "ACC1:not#159" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load inst "ACC1:acc#143" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 25922 -attr oid 1218 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#158.itm(0)} -pin  "ACC1:acc#143" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(1)} -pin  "ACC1:acc#143" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(2)} -pin  "ACC1:acc#143" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(3)} -pin  "ACC1:acc#143" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(4)} -pin  "ACC1:acc#143" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(5)} -pin  "ACC1:acc#143" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(6)} -pin  "ACC1:acc#143" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(7)} -pin  "ACC1:acc#143" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(8)} -pin  "ACC1:acc#143" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(9)} -pin  "ACC1:acc#143" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#159.itm(0)} -pin  "ACC1:acc#143" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(1)} -pin  "ACC1:acc#143" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(2)} -pin  "ACC1:acc#143" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(3)} -pin  "ACC1:acc#143" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(4)} -pin  "ACC1:acc#143" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(5)} -pin  "ACC1:acc#143" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(6)} -pin  "ACC1:acc#143" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(7)} -pin  "ACC1:acc#143" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(8)} -pin  "ACC1:acc#143" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(9)} -pin  "ACC1:acc#143" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:acc#143.itm(0)} -pin  "ACC1:acc#143" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(1)} -pin  "ACC1:acc#143" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(2)} -pin  "ACC1:acc#143" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(3)} -pin  "ACC1:acc#143" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(4)} -pin  "ACC1:acc#143" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(5)} -pin  "ACC1:acc#143" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(6)} -pin  "ACC1:acc#143" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(7)} -pin  "ACC1:acc#143" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(8)} -pin  "ACC1:acc#143" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(9)} -pin  "ACC1:acc#143" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(10)} -pin  "ACC1:acc#143" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load inst "ACC1:not#160" "not(10)" "INTERFACE" -attr xrf 25923 -attr oid 1219 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "ACC1:not#160" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "ACC1:not#160" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "ACC1:not#160" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "ACC1:not#160" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "ACC1:not#160" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "ACC1:not#160" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "ACC1:not#160" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "ACC1:not#160" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "ACC1:not#160" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "ACC1:not#160" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:not#160.itm(0)} -pin  "ACC1:not#160" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(1)} -pin  "ACC1:not#160" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(2)} -pin  "ACC1:not#160" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(3)} -pin  "ACC1:not#160" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(4)} -pin  "ACC1:not#160" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(5)} -pin  "ACC1:not#160" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(6)} -pin  "ACC1:not#160" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(7)} -pin  "ACC1:not#160" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(8)} -pin  "ACC1:not#160" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(9)} -pin  "ACC1:not#160" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load inst "ACC1:acc#142" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 25924 -attr oid 1220 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#160.itm(0)} -pin  "ACC1:acc#142" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(1)} -pin  "ACC1:acc#142" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(2)} -pin  "ACC1:acc#142" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(3)} -pin  "ACC1:acc#142" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(4)} -pin  "ACC1:acc#142" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(5)} -pin  "ACC1:acc#142" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(6)} -pin  "ACC1:acc#142" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(7)} -pin  "ACC1:acc#142" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(8)} -pin  "ACC1:acc#142" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(9)} -pin  "ACC1:acc#142" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {PWR} -pin  "ACC1:acc#142" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#142" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#142.itm(0)} -pin  "ACC1:acc#142" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(1)} -pin  "ACC1:acc#142" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(2)} -pin  "ACC1:acc#142" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(3)} -pin  "ACC1:acc#142" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(4)} -pin  "ACC1:acc#142" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(5)} -pin  "ACC1:acc#142" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(6)} -pin  "ACC1:acc#142" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(7)} -pin  "ACC1:acc#142" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(8)} -pin  "ACC1:acc#142" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(9)} -pin  "ACC1:acc#142" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(10)} -pin  "ACC1:acc#142" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load inst "ACC1-1:acc#125" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 25925 -attr oid 1221 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#125} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#143.itm(0)} -pin  "ACC1-1:acc#125" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(1)} -pin  "ACC1-1:acc#125" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(2)} -pin  "ACC1-1:acc#125" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(3)} -pin  "ACC1-1:acc#125" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(4)} -pin  "ACC1-1:acc#125" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(5)} -pin  "ACC1-1:acc#125" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(6)} -pin  "ACC1-1:acc#125" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(7)} -pin  "ACC1-1:acc#125" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(8)} -pin  "ACC1-1:acc#125" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(9)} -pin  "ACC1-1:acc#125" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(10)} -pin  "ACC1-1:acc#125" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#142.itm(0)} -pin  "ACC1-1:acc#125" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(1)} -pin  "ACC1-1:acc#125" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(2)} -pin  "ACC1-1:acc#125" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(3)} -pin  "ACC1-1:acc#125" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(4)} -pin  "ACC1-1:acc#125" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(5)} -pin  "ACC1-1:acc#125" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(6)} -pin  "ACC1-1:acc#125" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(7)} -pin  "ACC1-1:acc#125" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(8)} -pin  "ACC1-1:acc#125" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(9)} -pin  "ACC1-1:acc#125" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(10)} -pin  "ACC1-1:acc#125" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#125.psp#1.sva(0)} -pin  "ACC1-1:acc#125" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(1)} -pin  "ACC1-1:acc#125" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(2)} -pin  "ACC1-1:acc#125" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(3)} -pin  "ACC1-1:acc#125" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(4)} -pin  "ACC1-1:acc#125" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(5)} -pin  "ACC1-1:acc#125" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(6)} -pin  "ACC1-1:acc#125" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(7)} -pin  "ACC1-1:acc#125" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(8)} -pin  "ACC1-1:acc#125" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(9)} -pin  "ACC1-1:acc#125" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(10)} -pin  "ACC1-1:acc#125" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(11)} -pin  "ACC1-1:acc#125" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load inst "ACC1-3:not#115" "not(1)" "INTERFACE" -attr xrf 25926 -attr oid 1222 -attr @path {/sobel/sobel:core/ACC1-3:not#115} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp.sva(0)} -pin  "ACC1-3:not#115" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva).itm}
+load net {ACC1-3:not#115.itm} -pin  "ACC1-3:not#115" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#115.itm}
+load inst "ACC1-3:not#116" "not(1)" "INTERFACE" -attr xrf 25927 -attr oid 1223 -attr @path {/sobel/sobel:core/ACC1-3:not#116} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp.sva(2)} -pin  "ACC1-3:not#116" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#2.itm}
+load net {ACC1-3:not#116.itm} -pin  "ACC1-3:not#116" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#116.itm}
+load inst "ACC1-3:not#118" "not(1)" "INTERFACE" -attr xrf 25928 -attr oid 1224 -attr @path {/sobel/sobel:core/ACC1-3:not#118} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp.sva(6)} -pin  "ACC1-3:not#118" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#3.itm}
+load net {ACC1-3:not#118.itm} -pin  "ACC1-3:not#118" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#118.itm}
+load inst "ACC1:acc#173" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25929 -attr oid 1225 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#173" {A(0)} -attr @path {/sobel/sobel:core/conc#694.itm}
+load net {ACC1:acc#125.psp.sva(1)} -pin  "ACC1:acc#173" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#694.itm}
+load net {ACC1-3:not#118.itm} -pin  "ACC1:acc#173" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#518.itm}
+load net {ACC1-3:not#116.itm} -pin  "ACC1:acc#173" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#518.itm}
+load net {ACC1:acc#173.itm(0)} -pin  "ACC1:acc#173" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load net {ACC1:acc#173.itm(1)} -pin  "ACC1:acc#173" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load net {ACC1:acc#173.itm(2)} -pin  "ACC1:acc#173" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load inst "ACC1-3:not#119" "not(1)" "INTERFACE" -attr xrf 25930 -attr oid 1226 -attr @path {/sobel/sobel:core/ACC1-3:not#119} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp.sva(8)} -pin  "ACC1-3:not#119" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#4.itm}
+load net {ACC1-3:not#119.itm} -pin  "ACC1-3:not#119" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#119.itm}
+load inst "ACC1:acc#175" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 25931 -attr oid 1227 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#175" {A(0)} -attr @path {/sobel/sobel:core/conc#693.itm}
+load net {ACC1-3:not#115.itm} -pin  "ACC1:acc#175" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#693.itm}
+load net {GND} -pin  "ACC1:acc#175" {A(2)} -attr @path {/sobel/sobel:core/conc#693.itm}
+load net {PWR} -pin  "ACC1:acc#175" {A(3)} -attr @path {/sobel/sobel:core/conc#693.itm}
+load net {ACC1-3:not#119.itm} -pin  "ACC1:acc#175" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#522.itm}
+load net {ACC1:acc#173.itm(1)} -pin  "ACC1:acc#175" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#522.itm}
+load net {ACC1:acc#173.itm(2)} -pin  "ACC1:acc#175" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#522.itm}
+load net {ACC1:acc#175.itm(0)} -pin  "ACC1:acc#175" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load net {ACC1:acc#175.itm(1)} -pin  "ACC1:acc#175" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load net {ACC1:acc#175.itm(2)} -pin  "ACC1:acc#175" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load net {ACC1:acc#175.itm(3)} -pin  "ACC1:acc#175" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load inst "ACC1-3:not#117" "not(1)" "INTERFACE" -attr xrf 25932 -attr oid 1228 -attr @path {/sobel/sobel:core/ACC1-3:not#117} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp.sva(4)} -pin  "ACC1-3:not#117" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#6.itm}
+load net {ACC1-3:not#117.itm} -pin  "ACC1-3:not#117" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#117.itm}
+load inst "ACC1:acc#172" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25933 -attr oid 1229 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#172" {A(0)} -attr @path {/sobel/sobel:core/conc#696.itm}
+load net {ACC1:acc#125.psp.sva(3)} -pin  "ACC1:acc#172" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#696.itm}
+load net {ACC1:acc#125.psp.sva(5)} -pin  "ACC1:acc#172" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#516.itm}
+load net {ACC1-3:not#117.itm} -pin  "ACC1:acc#172" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#516.itm}
+load net {ACC1:acc#172.itm(0)} -pin  "ACC1:acc#172" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load net {ACC1:acc#172.itm(1)} -pin  "ACC1:acc#172" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load net {ACC1:acc#172.itm(2)} -pin  "ACC1:acc#172" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load inst "ACC1-3:not#120" "not(2)" "INTERFACE" -attr xrf 25934 -attr oid 1230 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#120} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#125.psp.sva(10)} -pin  "ACC1-3:not#120" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#8.itm}
+load net {ACC1:acc#125.psp.sva(11)} -pin  "ACC1-3:not#120" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#8.itm}
+load net {ACC1-3:not#120.itm(0)} -pin  "ACC1-3:not#120" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#120.itm}
+load net {ACC1-3:not#120.itm(1)} -pin  "ACC1-3:not#120" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#120.itm}
+load inst "ACC1:acc#174" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 25935 -attr oid 1231 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#174" {A(0)} -attr @path {/sobel/sobel:core/conc#695.itm}
+load net {ACC1:acc#172.itm(1)} -pin  "ACC1:acc#174" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#695.itm}
+load net {ACC1:acc#172.itm(2)} -pin  "ACC1:acc#174" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#695.itm}
+load net {ACC1:acc#125.psp.sva(7)} -pin  "ACC1:acc#174" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#520.itm}
+load net {ACC1-3:not#120.itm(0)} -pin  "ACC1:acc#174" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#520.itm}
+load net {ACC1-3:not#120.itm(1)} -pin  "ACC1:acc#174" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#520.itm}
+load net {ACC1:acc#174.itm(0)} -pin  "ACC1:acc#174" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {ACC1:acc#174.itm(1)} -pin  "ACC1:acc#174" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {ACC1:acc#174.itm(2)} -pin  "ACC1:acc#174" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {ACC1:acc#174.itm(3)} -pin  "ACC1:acc#174" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {ACC1:acc#174.itm(4)} -pin  "ACC1:acc#174" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load inst "ACC1:acc#176" "add(4,1,5,-1,5)" "INTERFACE" -attr xrf 25936 -attr oid 1232 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "ACC1:acc#176" {A(0)} -attr @path {/sobel/sobel:core/conc#692.itm}
+load net {ACC1:acc#175.itm(1)} -pin  "ACC1:acc#176" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#692.itm}
+load net {ACC1:acc#175.itm(2)} -pin  "ACC1:acc#176" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#692.itm}
+load net {ACC1:acc#175.itm(3)} -pin  "ACC1:acc#176" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#692.itm}
+load net {ACC1:acc#125.psp.sva(9)} -pin  "ACC1:acc#176" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#524.itm}
+load net {ACC1:acc#174.itm(1)} -pin  "ACC1:acc#176" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#524.itm}
+load net {ACC1:acc#174.itm(2)} -pin  "ACC1:acc#176" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#524.itm}
+load net {ACC1:acc#174.itm(3)} -pin  "ACC1:acc#176" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#524.itm}
+load net {ACC1:acc#174.itm(4)} -pin  "ACC1:acc#176" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#524.itm}
+load net {ACC1:acc#176.itm(0)} -pin  "ACC1:acc#176" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {ACC1:acc#176.itm(1)} -pin  "ACC1:acc#176" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {ACC1:acc#176.itm(2)} -pin  "ACC1:acc#176" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {ACC1:acc#176.itm(3)} -pin  "ACC1:acc#176" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {ACC1:acc#176.itm(4)} -pin  "ACC1:acc#176" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load inst "ACC1:acc#171" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 25937 -attr oid 1233 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.regs(1).sva(40)} -pin  "ACC1:acc#171" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(41)} -pin  "ACC1:acc#171" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(42)} -pin  "ACC1:acc#171" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(43)} -pin  "ACC1:acc#171" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(44)} -pin  "ACC1:acc#171" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(45)} -pin  "ACC1:acc#171" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(46)} -pin  "ACC1:acc#171" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(47)} -pin  "ACC1:acc#171" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(48)} -pin  "ACC1:acc#171" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(49)} -pin  "ACC1:acc#171" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(30)} -pin  "ACC1:acc#171" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(31)} -pin  "ACC1:acc#171" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(32)} -pin  "ACC1:acc#171" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(33)} -pin  "ACC1:acc#171" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(34)} -pin  "ACC1:acc#171" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(35)} -pin  "ACC1:acc#171" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(36)} -pin  "ACC1:acc#171" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(37)} -pin  "ACC1:acc#171" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(38)} -pin  "ACC1:acc#171" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(39)} -pin  "ACC1:acc#171" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {ACC1:acc#171.itm(0)} -pin  "ACC1:acc#171" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(1)} -pin  "ACC1:acc#171" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(2)} -pin  "ACC1:acc#171" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(3)} -pin  "ACC1:acc#171" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(4)} -pin  "ACC1:acc#171" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(5)} -pin  "ACC1:acc#171" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(6)} -pin  "ACC1:acc#171" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(7)} -pin  "ACC1:acc#171" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(8)} -pin  "ACC1:acc#171" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(9)} -pin  "ACC1:acc#171" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(10)} -pin  "ACC1:acc#171" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load inst "ACC1-3:acc#125" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 25938 -attr oid 1234 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#125} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#171.itm(0)} -pin  "ACC1-3:acc#125" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(1)} -pin  "ACC1-3:acc#125" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(2)} -pin  "ACC1-3:acc#125" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(3)} -pin  "ACC1-3:acc#125" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(4)} -pin  "ACC1-3:acc#125" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(5)} -pin  "ACC1-3:acc#125" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(6)} -pin  "ACC1-3:acc#125" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(7)} -pin  "ACC1-3:acc#125" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(8)} -pin  "ACC1-3:acc#125" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(9)} -pin  "ACC1-3:acc#125" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(10)} -pin  "ACC1-3:acc#125" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {regs.regs(1).sva(50)} -pin  "ACC1-3:acc#125" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(51)} -pin  "ACC1-3:acc#125" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(52)} -pin  "ACC1-3:acc#125" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(53)} -pin  "ACC1-3:acc#125" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(54)} -pin  "ACC1-3:acc#125" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(55)} -pin  "ACC1-3:acc#125" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(56)} -pin  "ACC1-3:acc#125" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(57)} -pin  "ACC1-3:acc#125" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(58)} -pin  "ACC1-3:acc#125" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(59)} -pin  "ACC1-3:acc#125" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {ACC1:acc#125.psp.sva(0)} -pin  "ACC1-3:acc#125" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(1)} -pin  "ACC1-3:acc#125" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(2)} -pin  "ACC1-3:acc#125" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(3)} -pin  "ACC1-3:acc#125" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(4)} -pin  "ACC1-3:acc#125" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(5)} -pin  "ACC1-3:acc#125" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(6)} -pin  "ACC1-3:acc#125" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(7)} -pin  "ACC1-3:acc#125" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(8)} -pin  "ACC1-3:acc#125" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(9)} -pin  "ACC1-3:acc#125" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(10)} -pin  "ACC1-3:acc#125" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(11)} -pin  "ACC1-3:acc#125" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load inst "ACC1-3:not#137" "not(1)" "INTERFACE" -attr xrf 25939 -attr oid 1235 -attr @path {/sobel/sobel:core/ACC1-3:not#137} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#176.itm(2)} -pin  "ACC1-3:not#137" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.sva)#2.itm}
+load net {ACC1-3:not#137.itm} -pin  "ACC1-3:not#137" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#137.itm}
+load inst "ACC1:acc#177" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25940 -attr oid 1236 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#177" {A(0)} -attr @path {/sobel/sobel:core/conc#697.itm}
+load net {ACC1:acc#176.itm(1)} -pin  "ACC1:acc#177" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#697.itm}
+load net {ACC1:acc#176.itm(3)} -pin  "ACC1:acc#177" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#526.itm}
+load net {ACC1-3:not#137.itm} -pin  "ACC1:acc#177" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#526.itm}
+load net {ACC1:acc#177.itm(0)} -pin  "ACC1:acc#177" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(1)} -pin  "ACC1:acc#177" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(2)} -pin  "ACC1:acc#177" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load inst "ACC1-3:not#154" "not(1)" "INTERFACE" -attr xrf 25941 -attr oid 1237 -attr @path {/sobel/sobel:core/ACC1-3:not#154} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#176.itm(4)} -pin  "ACC1-3:not#154" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.sva)#4.itm}
+load net {ACC1-3:not#154.itm} -pin  "ACC1-3:not#154" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#154.itm}
+load inst "ACC1-3:acc#118" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 25942 -attr oid 1238 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#118} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#177.itm(1)} -pin  "ACC1-3:acc#118" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#43.itm}
+load net {ACC1:acc#177.itm(2)} -pin  "ACC1-3:acc#118" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#43.itm}
+load net {ACC1-3:not#154.itm} -pin  "ACC1-3:acc#118" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#154.itm}
+load net {ACC1:acc#118.psp.sva(0)} -pin  "ACC1-3:acc#118" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.sva}
+load net {ACC1:acc#118.psp.sva(1)} -pin  "ACC1-3:acc#118" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.sva}
+load net {ACC1:acc#118.psp.sva(2)} -pin  "ACC1-3:acc#118" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.sva}
+load inst "ACC1-3:not#147" "not(2)" "INTERFACE" -attr xrf 25943 -attr oid 1239 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#147} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#118.psp.sva(1)} -pin  "ACC1-3:not#147" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp.sva)#2.itm}
+load net {ACC1:acc#118.psp.sva(2)} -pin  "ACC1-3:not#147" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp.sva)#2.itm}
+load net {ACC1-3:not#147.itm(0)} -pin  "ACC1-3:not#147" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#147.itm}
+load net {ACC1-3:not#147.itm(1)} -pin  "ACC1-3:not#147" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#147.itm}
+load inst "ACC1:acc#178" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 25944 -attr oid 1240 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#178" {A(0)} -attr @path {/sobel/sobel:core/conc#698.itm}
+load net {ACC1-3:not#147.itm(0)} -pin  "ACC1:acc#178" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#698.itm}
+load net {ACC1-3:not#147.itm(1)} -pin  "ACC1:acc#178" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#698.itm}
+load net {PWR} -pin  "ACC1:acc#178" {B(0)} -attr @path {/sobel/sobel:core/conc#699.itm}
+load net {ACC1:acc#118.psp.sva(0)} -pin  "ACC1:acc#178" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#699.itm}
+load net {ACC1:acc#178.itm(0)} -pin  "ACC1:acc#178" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(1)} -pin  "ACC1:acc#178" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(2)} -pin  "ACC1:acc#178" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(3)} -pin  "ACC1:acc#178" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load inst "ACC1:acc#180" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 25945 -attr oid 1241 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.regs(1).sva(70)} -pin  "ACC1:acc#180" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(71)} -pin  "ACC1:acc#180" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(72)} -pin  "ACC1:acc#180" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(73)} -pin  "ACC1:acc#180" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(74)} -pin  "ACC1:acc#180" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(75)} -pin  "ACC1:acc#180" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(76)} -pin  "ACC1:acc#180" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(77)} -pin  "ACC1:acc#180" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(78)} -pin  "ACC1:acc#180" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(79)} -pin  "ACC1:acc#180" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(60)} -pin  "ACC1:acc#180" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(61)} -pin  "ACC1:acc#180" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(62)} -pin  "ACC1:acc#180" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(63)} -pin  "ACC1:acc#180" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(64)} -pin  "ACC1:acc#180" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(65)} -pin  "ACC1:acc#180" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(66)} -pin  "ACC1:acc#180" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(67)} -pin  "ACC1:acc#180" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(68)} -pin  "ACC1:acc#180" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(69)} -pin  "ACC1:acc#180" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {ACC1:acc#180.itm(0)} -pin  "ACC1:acc#180" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(1)} -pin  "ACC1:acc#180" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(2)} -pin  "ACC1:acc#180" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(3)} -pin  "ACC1:acc#180" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(4)} -pin  "ACC1:acc#180" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(5)} -pin  "ACC1:acc#180" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(6)} -pin  "ACC1:acc#180" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(7)} -pin  "ACC1:acc#180" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(8)} -pin  "ACC1:acc#180" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(9)} -pin  "ACC1:acc#180" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(10)} -pin  "ACC1:acc#180" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load inst "ACC1-3:acc#10" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 25946 -attr oid 1242 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#10} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#180.itm(0)} -pin  "ACC1-3:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(1)} -pin  "ACC1-3:acc#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(2)} -pin  "ACC1-3:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(3)} -pin  "ACC1-3:acc#10" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(4)} -pin  "ACC1-3:acc#10" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(5)} -pin  "ACC1-3:acc#10" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(6)} -pin  "ACC1-3:acc#10" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(7)} -pin  "ACC1-3:acc#10" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(8)} -pin  "ACC1-3:acc#10" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(9)} -pin  "ACC1-3:acc#10" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(10)} -pin  "ACC1-3:acc#10" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {regs.regs(1).sva(80)} -pin  "ACC1-3:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(81)} -pin  "ACC1-3:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(82)} -pin  "ACC1-3:acc#10" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(83)} -pin  "ACC1-3:acc#10" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(84)} -pin  "ACC1-3:acc#10" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(85)} -pin  "ACC1-3:acc#10" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(86)} -pin  "ACC1-3:acc#10" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(87)} -pin  "ACC1-3:acc#10" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(88)} -pin  "ACC1-3:acc#10" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(89)} -pin  "ACC1-3:acc#10" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {acc#10.psp#1.sva(0)} -pin  "ACC1-3:acc#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(1)} -pin  "ACC1-3:acc#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(2)} -pin  "ACC1-3:acc#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(3)} -pin  "ACC1-3:acc#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(4)} -pin  "ACC1-3:acc#10" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(5)} -pin  "ACC1-3:acc#10" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(6)} -pin  "ACC1-3:acc#10" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(7)} -pin  "ACC1-3:acc#10" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(8)} -pin  "ACC1-3:acc#10" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1-3:acc#10" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1-3:acc#10" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1-3:acc#10" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load inst "ACC1-3:not#156" "not(1)" "INTERFACE" -attr xrf 25947 -attr oid 1243 -attr @path {/sobel/sobel:core/ACC1-3:not#156} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1-3:not#156" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#42.itm}
+load net {ACC1-3:not#156.itm} -pin  "ACC1-3:not#156" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#156.itm}
+load inst "ACC1-3:not#124" "not(1)" "INTERFACE" -attr xrf 25948 -attr oid 1244 -attr @path {/sobel/sobel:core/ACC1-3:not#124} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(1)} -pin  "ACC1-3:not#124" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#4.itm}
+load net {ACC1-3:not#124.itm} -pin  "ACC1-3:not#124" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#124.itm}
+load inst "ACC1:acc#183" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 25949 -attr oid 1245 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#183" {A(0)} -attr @path {/sobel/sobel:core/conc#701.itm}
+load net {ACC1-3:not#156.itm} -pin  "ACC1:acc#183" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#701.itm}
+load net {acc#10.psp#1.sva(8)} -pin  "ACC1:acc#183" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#538.itm}
+load net {ACC1-3:not#124.itm} -pin  "ACC1:acc#183" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#538.itm}
+load net {ACC1:acc#183.itm(0)} -pin  "ACC1:acc#183" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load net {ACC1:acc#183.itm(1)} -pin  "ACC1:acc#183" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load net {ACC1:acc#183.itm(2)} -pin  "ACC1:acc#183" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load net {ACC1:acc#183.itm(3)} -pin  "ACC1:acc#183" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load inst "ACC1:acc#185" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 25950 -attr oid 1246 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#185" {A(0)} -attr @path {/sobel/sobel:core/conc#700.itm}
+load net {ACC1:acc#183.itm(1)} -pin  "ACC1:acc#185" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#700.itm}
+load net {ACC1:acc#183.itm(2)} -pin  "ACC1:acc#185" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#700.itm}
+load net {ACC1:acc#183.itm(3)} -pin  "ACC1:acc#185" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#700.itm}
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1:acc#185" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#702.itm}
+load net {acc#10.psp#1.sva(0)} -pin  "ACC1:acc#185" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#702.itm}
+load net {GND} -pin  "ACC1:acc#185" {B(2)} -attr @path {/sobel/sobel:core/conc#702.itm}
+load net {PWR} -pin  "ACC1:acc#185" {B(3)} -attr @path {/sobel/sobel:core/conc#702.itm}
+load net {ACC1:acc#185.itm(0)} -pin  "ACC1:acc#185" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {ACC1:acc#185.itm(1)} -pin  "ACC1:acc#185" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {ACC1:acc#185.itm(2)} -pin  "ACC1:acc#185" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {ACC1:acc#185.itm(3)} -pin  "ACC1:acc#185" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {ACC1:acc#185.itm(4)} -pin  "ACC1:acc#185" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load inst "ACC1-3:not#125" "not(1)" "INTERFACE" -attr xrf 25951 -attr oid 1247 -attr @path {/sobel/sobel:core/ACC1-3:not#125} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(3)} -pin  "ACC1-3:not#125" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#3.itm}
+load net {ACC1-3:not#125.itm} -pin  "ACC1-3:not#125" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#125.itm}
+load inst "ACC1-3:not#127" "not(1)" "INTERFACE" -attr xrf 25952 -attr oid 1248 -attr @path {/sobel/sobel:core/ACC1-3:not#127} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(7)} -pin  "ACC1-3:not#127" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#6.itm}
+load net {ACC1-3:not#127.itm} -pin  "ACC1-3:not#127" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#127.itm}
+load inst "ACC1:acc#182" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25953 -attr oid 1249 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#182" {A(0)} -attr @path {/sobel/sobel:core/conc#704.itm}
+load net {acc#10.psp#1.sva(2)} -pin  "ACC1:acc#182" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#704.itm}
+load net {ACC1-3:not#127.itm} -pin  "ACC1:acc#182" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#536.itm}
+load net {ACC1-3:not#125.itm} -pin  "ACC1:acc#182" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#536.itm}
+load net {ACC1:acc#182.itm(0)} -pin  "ACC1:acc#182" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182.itm}
+load net {ACC1:acc#182.itm(1)} -pin  "ACC1:acc#182" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182.itm}
+load net {ACC1:acc#182.itm(2)} -pin  "ACC1:acc#182" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182.itm}
+load inst "ACC1-3:not#126" "not(1)" "INTERFACE" -attr xrf 25954 -attr oid 1250 -attr @path {/sobel/sobel:core/ACC1-3:not#126} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(5)} -pin  "ACC1-3:not#126" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#12.itm}
+load net {ACC1-3:not#126.itm} -pin  "ACC1-3:not#126" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#126.itm}
+load inst "ACC1:acc#181" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25955 -attr oid 1251 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#181" {A(0)} -attr @path {/sobel/sobel:core/conc#705.itm}
+load net {acc#10.psp#1.sva(4)} -pin  "ACC1:acc#181" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#705.itm}
+load net {acc#10.psp#1.sva(6)} -pin  "ACC1:acc#181" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#534.itm}
+load net {ACC1-3:not#126.itm} -pin  "ACC1:acc#181" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#534.itm}
+load net {ACC1:acc#181.itm(0)} -pin  "ACC1:acc#181" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181.itm}
+load net {ACC1:acc#181.itm(1)} -pin  "ACC1:acc#181" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181.itm}
+load net {ACC1:acc#181.itm(2)} -pin  "ACC1:acc#181" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181.itm}
+load inst "ACC1-3:not#128" "not(1)" "INTERFACE" -attr xrf 25956 -attr oid 1252 -attr @path {/sobel/sobel:core/ACC1-3:not#128} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1-3:not#128" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#23.itm}
+load net {ACC1-3:not#128.itm} -pin  "ACC1-3:not#128" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#128.itm}
+load inst "ACC1:acc#184" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25957 -attr oid 1253 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#184" {A(0)} -attr @path {/sobel/sobel:core/conc#703.itm}
+load net {ACC1:acc#182.itm(1)} -pin  "ACC1:acc#184" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#703.itm}
+load net {ACC1:acc#182.itm(2)} -pin  "ACC1:acc#184" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#703.itm}
+load net {ACC1-3:not#128.itm} -pin  "ACC1:acc#184" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#540.itm}
+load net {ACC1:acc#181.itm(1)} -pin  "ACC1:acc#184" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#540.itm}
+load net {ACC1:acc#181.itm(2)} -pin  "ACC1:acc#184" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#540.itm}
+load net {ACC1:acc#184.itm(0)} -pin  "ACC1:acc#184" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load net {ACC1:acc#184.itm(1)} -pin  "ACC1:acc#184" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load net {ACC1:acc#184.itm(2)} -pin  "ACC1:acc#184" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load net {ACC1:acc#184.itm(3)} -pin  "ACC1:acc#184" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load inst "ACC1-3:acc#113" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 25958 -attr oid 1254 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#113} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#185.itm(1)} -pin  "ACC1-3:acc#113" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#185.itm(2)} -pin  "ACC1-3:acc#113" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#185.itm(3)} -pin  "ACC1-3:acc#113" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#185.itm(4)} -pin  "ACC1-3:acc#113" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#184.itm(1)} -pin  "ACC1-3:acc#113" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#49.itm}
+load net {ACC1:acc#184.itm(2)} -pin  "ACC1-3:acc#113" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#49.itm}
+load net {ACC1:acc#184.itm(3)} -pin  "ACC1-3:acc#113" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#49.itm}
+load net {ACC1:acc#113.psp#1.sva(0)} -pin  "ACC1-3:acc#113" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#1.sva}
+load net {ACC1:acc#113.psp#1.sva(1)} -pin  "ACC1-3:acc#113" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#1.sva}
+load net {ACC1:acc#113.psp#1.sva(2)} -pin  "ACC1-3:acc#113" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#1.sva}
+load net {ACC1:acc#113.psp#1.sva(3)} -pin  "ACC1-3:acc#113" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#1.sva}
+load inst "ACC1-3:not#141" "not(1)" "INTERFACE" -attr xrf 25959 -attr oid 1255 -attr @path {/sobel/sobel:core/ACC1-3:not#141} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#113.psp#1.sva(1)} -pin  "ACC1-3:not#141" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#113.psp#1.sva)#4.itm}
+load net {ACC1-3:not#141.itm} -pin  "ACC1-3:not#141" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#141.itm}
+load inst "ACC1:acc#186" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25960 -attr oid 1256 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#186" {A(0)} -attr @path {/sobel/sobel:core/conc#706.itm}
+load net {ACC1:acc#113.psp#1.sva(0)} -pin  "ACC1:acc#186" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#706.itm}
+load net {ACC1:acc#113.psp#1.sva(2)} -pin  "ACC1:acc#186" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#544.itm}
+load net {ACC1-3:not#141.itm} -pin  "ACC1:acc#186" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#544.itm}
+load net {ACC1:acc#186.itm(0)} -pin  "ACC1:acc#186" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186.itm}
+load net {ACC1:acc#186.itm(1)} -pin  "ACC1:acc#186" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186.itm}
+load net {ACC1:acc#186.itm(2)} -pin  "ACC1:acc#186" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186.itm}
+load inst "ACC1-3:not#155" "not(1)" "INTERFACE" -attr xrf 25961 -attr oid 1257 -attr @path {/sobel/sobel:core/ACC1-3:not#155} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#113.psp#1.sva(3)} -pin  "ACC1-3:not#155" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#113.psp#1.sva).itm}
+load net {ACC1-3:not#155.itm} -pin  "ACC1-3:not#155" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#155.itm}
+load inst "ACC1-3:acc#120" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 25962 -attr oid 1258 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#120} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#186.itm(1)} -pin  "ACC1-3:acc#120" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#51.itm}
+load net {ACC1:acc#186.itm(2)} -pin  "ACC1-3:acc#120" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#51.itm}
+load net {ACC1-3:not#155.itm} -pin  "ACC1-3:acc#120" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#155.itm}
+load net {ACC1:acc#120.psp.sva(0)} -pin  "ACC1-3:acc#120" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#120.psp.sva}
+load net {ACC1:acc#120.psp.sva(1)} -pin  "ACC1-3:acc#120" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#120.psp.sva}
+load net {ACC1:acc#120.psp.sva(2)} -pin  "ACC1-3:acc#120" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#120.psp.sva}
+load inst "ACC1:acc#250" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25963 -attr oid 1259 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#250" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#558.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#250" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#558.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#250" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#547.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#250" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#547.itm}
+load net {ACC1:acc#250.cse(0)} -pin  "ACC1:acc#250" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#250.cse(1)} -pin  "ACC1:acc#250" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#250.cse(2)} -pin  "ACC1:acc#250" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load inst "ACC1-3:not#89" "not(1)" "INTERFACE" -attr xrf 25964 -attr oid 1260 -attr @path {/sobel/sobel:core/ACC1-3:not#89} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#187.itm(2)} -pin  "ACC1-3:not#89" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#10.sva)#3.itm}
+load net {ACC1-3:not#89.itm} -pin  "ACC1-3:not#89" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#89.itm}
+load inst "ACC1-3:not#158" "not(1)" "INTERFACE" -attr xrf 25965 -attr oid 1261 -attr @path {/sobel/sobel:core/ACC1-3:not#158} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#187.itm(3)} -pin  "ACC1-3:not#158" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#10.sva).itm}
+load net {ACC1-3:not#158.itm} -pin  "ACC1-3:not#158" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#158.itm}
+load inst "ACC1:acc#188" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 25966 -attr oid 1262 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#188" {A(0)} -attr @path {/sobel/sobel:core/conc#707.itm}
+load net {ACC1:acc#187.itm(1)} -pin  "ACC1:acc#188" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#707.itm}
+load net {PWR} -pin  "ACC1:acc#188" {A(2)} -attr @path {/sobel/sobel:core/conc#707.itm}
+load net {ACC1-3:not#158.itm} -pin  "ACC1:acc#188" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#549.itm}
+load net {ACC1-3:not#89.itm} -pin  "ACC1:acc#188" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#549.itm}
+load net {ACC1:acc#188.itm(0)} -pin  "ACC1:acc#188" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load net {ACC1:acc#188.itm(1)} -pin  "ACC1:acc#188" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load net {ACC1:acc#188.itm(2)} -pin  "ACC1:acc#188" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load inst "ACC1:not#161" "not(10)" "INTERFACE" -attr xrf 25967 -attr oid 1263 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "ACC1:not#161" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "ACC1:not#161" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "ACC1:not#161" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "ACC1:not#161" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "ACC1:not#161" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "ACC1:not#161" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "ACC1:not#161" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "ACC1:not#161" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "ACC1:not#161" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:not#161" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {ACC1:not#161.itm(0)} -pin  "ACC1:not#161" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(1)} -pin  "ACC1:not#161" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(2)} -pin  "ACC1:not#161" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(3)} -pin  "ACC1:not#161" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(4)} -pin  "ACC1:not#161" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(5)} -pin  "ACC1:not#161" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(6)} -pin  "ACC1:not#161" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(7)} -pin  "ACC1:not#161" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(8)} -pin  "ACC1:not#161" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(9)} -pin  "ACC1:not#161" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load inst "ACC1:not#162" "not(10)" "INTERFACE" -attr xrf 25968 -attr oid 1264 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "ACC1:not#162" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "ACC1:not#162" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "ACC1:not#162" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "ACC1:not#162" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "ACC1:not#162" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "ACC1:not#162" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "ACC1:not#162" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "ACC1:not#162" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "ACC1:not#162" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:not#162" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {ACC1:not#162.itm(0)} -pin  "ACC1:not#162" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(1)} -pin  "ACC1:not#162" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(2)} -pin  "ACC1:not#162" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(3)} -pin  "ACC1:not#162" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(4)} -pin  "ACC1:not#162" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(5)} -pin  "ACC1:not#162" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(6)} -pin  "ACC1:not#162" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(7)} -pin  "ACC1:not#162" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(8)} -pin  "ACC1:not#162" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(9)} -pin  "ACC1:not#162" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load inst "ACC1:acc#153" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 25969 -attr oid 1265 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#161.itm(0)} -pin  "ACC1:acc#153" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(1)} -pin  "ACC1:acc#153" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(2)} -pin  "ACC1:acc#153" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(3)} -pin  "ACC1:acc#153" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(4)} -pin  "ACC1:acc#153" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(5)} -pin  "ACC1:acc#153" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(6)} -pin  "ACC1:acc#153" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(7)} -pin  "ACC1:acc#153" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(8)} -pin  "ACC1:acc#153" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(9)} -pin  "ACC1:acc#153" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#162.itm(0)} -pin  "ACC1:acc#153" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(1)} -pin  "ACC1:acc#153" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(2)} -pin  "ACC1:acc#153" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(3)} -pin  "ACC1:acc#153" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(4)} -pin  "ACC1:acc#153" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(5)} -pin  "ACC1:acc#153" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(6)} -pin  "ACC1:acc#153" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(7)} -pin  "ACC1:acc#153" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(8)} -pin  "ACC1:acc#153" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(9)} -pin  "ACC1:acc#153" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:acc#153.itm(0)} -pin  "ACC1:acc#153" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(1)} -pin  "ACC1:acc#153" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(2)} -pin  "ACC1:acc#153" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(3)} -pin  "ACC1:acc#153" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(4)} -pin  "ACC1:acc#153" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(5)} -pin  "ACC1:acc#153" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(6)} -pin  "ACC1:acc#153" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(7)} -pin  "ACC1:acc#153" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(8)} -pin  "ACC1:acc#153" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(9)} -pin  "ACC1:acc#153" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(10)} -pin  "ACC1:acc#153" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load inst "ACC1:not#163" "not(10)" "INTERFACE" -attr xrf 25970 -attr oid 1266 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "ACC1:not#163" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "ACC1:not#163" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "ACC1:not#163" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "ACC1:not#163" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "ACC1:not#163" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "ACC1:not#163" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "ACC1:not#163" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "ACC1:not#163" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "ACC1:not#163" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1:not#163" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {ACC1:not#163.itm(0)} -pin  "ACC1:not#163" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(1)} -pin  "ACC1:not#163" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(2)} -pin  "ACC1:not#163" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(3)} -pin  "ACC1:not#163" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(4)} -pin  "ACC1:not#163" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(5)} -pin  "ACC1:not#163" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(6)} -pin  "ACC1:not#163" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(7)} -pin  "ACC1:not#163" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(8)} -pin  "ACC1:not#163" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(9)} -pin  "ACC1:not#163" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load inst "ACC1:acc#152" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 25971 -attr oid 1267 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#163.itm(0)} -pin  "ACC1:acc#152" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(1)} -pin  "ACC1:acc#152" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(2)} -pin  "ACC1:acc#152" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(3)} -pin  "ACC1:acc#152" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(4)} -pin  "ACC1:acc#152" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(5)} -pin  "ACC1:acc#152" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(6)} -pin  "ACC1:acc#152" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(7)} -pin  "ACC1:acc#152" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(8)} -pin  "ACC1:acc#152" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(9)} -pin  "ACC1:acc#152" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {PWR} -pin  "ACC1:acc#152" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#152" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#152.itm(0)} -pin  "ACC1:acc#152" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(1)} -pin  "ACC1:acc#152" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(2)} -pin  "ACC1:acc#152" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(3)} -pin  "ACC1:acc#152" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(4)} -pin  "ACC1:acc#152" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(5)} -pin  "ACC1:acc#152" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(6)} -pin  "ACC1:acc#152" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(7)} -pin  "ACC1:acc#152" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(8)} -pin  "ACC1:acc#152" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(9)} -pin  "ACC1:acc#152" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(10)} -pin  "ACC1:acc#152" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load inst "ACC1-1:acc#10" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 25972 -attr oid 1268 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#10} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#153.itm(0)} -pin  "ACC1-1:acc#10" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(1)} -pin  "ACC1-1:acc#10" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(2)} -pin  "ACC1-1:acc#10" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(3)} -pin  "ACC1-1:acc#10" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(4)} -pin  "ACC1-1:acc#10" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(5)} -pin  "ACC1-1:acc#10" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(6)} -pin  "ACC1-1:acc#10" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(7)} -pin  "ACC1-1:acc#10" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(8)} -pin  "ACC1-1:acc#10" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(9)} -pin  "ACC1-1:acc#10" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(10)} -pin  "ACC1-1:acc#10" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#152.itm(0)} -pin  "ACC1-1:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(1)} -pin  "ACC1-1:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(2)} -pin  "ACC1-1:acc#10" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(3)} -pin  "ACC1-1:acc#10" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(4)} -pin  "ACC1-1:acc#10" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(5)} -pin  "ACC1-1:acc#10" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(6)} -pin  "ACC1-1:acc#10" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(7)} -pin  "ACC1-1:acc#10" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(8)} -pin  "ACC1-1:acc#10" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(9)} -pin  "ACC1-1:acc#10" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(10)} -pin  "ACC1-1:acc#10" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {acc#10.psp#2.sva(0)} -pin  "ACC1-1:acc#10" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(1)} -pin  "ACC1-1:acc#10" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(2)} -pin  "ACC1-1:acc#10" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(3)} -pin  "ACC1-1:acc#10" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(4)} -pin  "ACC1-1:acc#10" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(5)} -pin  "ACC1-1:acc#10" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(6)} -pin  "ACC1-1:acc#10" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(7)} -pin  "ACC1-1:acc#10" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(8)} -pin  "ACC1-1:acc#10" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1-1:acc#10" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1-1:acc#10" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:acc#10" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load inst "ACC1-1:not#89" "not(1)" "INTERFACE" -attr xrf 25973 -attr oid 1269 -attr @path {/sobel/sobel:core/ACC1-1:not#89} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#160.itm(2)} -pin  "ACC1-1:not#89" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#22.sva)#3.itm}
+load net {ACC1-1:not#89.itm} -pin  "ACC1-1:not#89" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#89.itm}
+load inst "ACC1-1:not#158" "not(1)" "INTERFACE" -attr xrf 25974 -attr oid 1270 -attr @path {/sobel/sobel:core/ACC1-1:not#158} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#160.itm(3)} -pin  "ACC1-1:not#158" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#22.sva).itm}
+load net {ACC1-1:not#158.itm} -pin  "ACC1-1:not#158" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#158.itm}
+load inst "ACC1:acc#161" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 25975 -attr oid 1271 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#161} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#161" {A(0)} -attr @path {/sobel/sobel:core/conc#708.itm}
+load net {ACC1:acc#160.itm(1)} -pin  "ACC1:acc#161" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#708.itm}
+load net {PWR} -pin  "ACC1:acc#161" {A(2)} -attr @path {/sobel/sobel:core/conc#708.itm}
+load net {ACC1-1:not#158.itm} -pin  "ACC1:acc#161" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#495.itm}
+load net {ACC1-1:not#89.itm} -pin  "ACC1:acc#161" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#495.itm}
+load net {ACC1:acc#161.itm(0)} -pin  "ACC1:acc#161" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load net {ACC1:acc#161.itm(1)} -pin  "ACC1:acc#161" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load net {ACC1:acc#161.itm(2)} -pin  "ACC1:acc#161" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load inst "ACC1-1:not#149" "not(2)" "INTERFACE" -attr xrf 25976 -attr oid 1272 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:not#149} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#120.psp#1.sva(1)} -pin  "ACC1-1:not#149" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp#1.sva).itm}
+load net {ACC1:acc#120.psp#1.sva(2)} -pin  "ACC1-1:not#149" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp#1.sva).itm}
+load net {ACC1-1:not#149.itm(0)} -pin  "ACC1-1:not#149" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:not#149.itm}
+load net {ACC1-1:not#149.itm(1)} -pin  "ACC1-1:not#149" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:not#149.itm}
+load inst "ACC1:acc#160" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 25977 -attr oid 1273 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#160} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#160" {A(0)} -attr @path {/sobel/sobel:core/conc#709.itm}
+load net {ACC1-1:not#149.itm(0)} -pin  "ACC1:acc#160" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#709.itm}
+load net {ACC1-1:not#149.itm(1)} -pin  "ACC1:acc#160" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#709.itm}
+load net {PWR} -pin  "ACC1:acc#160" {B(0)} -attr @path {/sobel/sobel:core/conc#710.itm}
+load net {ACC1:acc#120.psp#1.sva(0)} -pin  "ACC1:acc#160" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#710.itm}
+load net {ACC1:acc#160.itm(0)} -pin  "ACC1:acc#160" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load net {ACC1:acc#160.itm(1)} -pin  "ACC1:acc#160" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load net {ACC1:acc#160.itm(2)} -pin  "ACC1:acc#160" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load net {ACC1:acc#160.itm(3)} -pin  "ACC1:acc#160" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load inst "ACC1-1:not#156" "not(1)" "INTERFACE" -attr xrf 25978 -attr oid 1274 -attr @path {/sobel/sobel:core/ACC1-1:not#156} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:not#156" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#32.itm}
+load net {ACC1-1:not#156.itm} -pin  "ACC1-1:not#156" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#156.itm}
+load inst "ACC1-1:not#124" "not(1)" "INTERFACE" -attr xrf 25979 -attr oid 1275 -attr @path {/sobel/sobel:core/ACC1-1:not#124} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(1)} -pin  "ACC1-1:not#124" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#8.itm}
+load net {ACC1-1:not#124.itm} -pin  "ACC1-1:not#124" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#124.itm}
+load inst "ACC1:acc#156" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 25980 -attr oid 1276 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#156" {A(0)} -attr @path {/sobel/sobel:core/conc#712.itm}
+load net {ACC1-1:not#156.itm} -pin  "ACC1:acc#156" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#712.itm}
+load net {acc#10.psp#2.sva(8)} -pin  "ACC1:acc#156" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#484.itm}
+load net {ACC1-1:not#124.itm} -pin  "ACC1:acc#156" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#484.itm}
+load net {ACC1:acc#156.itm(0)} -pin  "ACC1:acc#156" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load net {ACC1:acc#156.itm(1)} -pin  "ACC1:acc#156" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load net {ACC1:acc#156.itm(2)} -pin  "ACC1:acc#156" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load net {ACC1:acc#156.itm(3)} -pin  "ACC1:acc#156" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load inst "ACC1:acc#158" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 25981 -attr oid 1277 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#158" {A(0)} -attr @path {/sobel/sobel:core/conc#711.itm}
+load net {ACC1:acc#156.itm(1)} -pin  "ACC1:acc#158" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#711.itm}
+load net {ACC1:acc#156.itm(2)} -pin  "ACC1:acc#158" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#711.itm}
+load net {ACC1:acc#156.itm(3)} -pin  "ACC1:acc#158" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#711.itm}
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1:acc#158" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#713.itm}
+load net {acc#10.psp#2.sva(0)} -pin  "ACC1:acc#158" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#713.itm}
+load net {GND} -pin  "ACC1:acc#158" {B(2)} -attr @path {/sobel/sobel:core/conc#713.itm}
+load net {PWR} -pin  "ACC1:acc#158" {B(3)} -attr @path {/sobel/sobel:core/conc#713.itm}
+load net {ACC1:acc#158.itm(0)} -pin  "ACC1:acc#158" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {ACC1:acc#158.itm(1)} -pin  "ACC1:acc#158" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {ACC1:acc#158.itm(2)} -pin  "ACC1:acc#158" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {ACC1:acc#158.itm(3)} -pin  "ACC1:acc#158" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {ACC1:acc#158.itm(4)} -pin  "ACC1:acc#158" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load inst "ACC1-1:not#125" "not(1)" "INTERFACE" -attr xrf 25982 -attr oid 1278 -attr @path {/sobel/sobel:core/ACC1-1:not#125} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(3)} -pin  "ACC1-1:not#125" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#7.itm}
+load net {ACC1-1:not#125.itm} -pin  "ACC1-1:not#125" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#125.itm}
+load inst "ACC1-1:not#127" "not(1)" "INTERFACE" -attr xrf 25983 -attr oid 1279 -attr @path {/sobel/sobel:core/ACC1-1:not#127} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(7)} -pin  "ACC1-1:not#127" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#3.itm}
+load net {ACC1-1:not#127.itm} -pin  "ACC1-1:not#127" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#127.itm}
+load inst "ACC1:acc#155" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25984 -attr oid 1280 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#155} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#155" {A(0)} -attr @path {/sobel/sobel:core/conc#715.itm}
+load net {acc#10.psp#2.sva(2)} -pin  "ACC1:acc#155" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#715.itm}
+load net {ACC1-1:not#127.itm} -pin  "ACC1:acc#155" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#482.itm}
+load net {ACC1-1:not#125.itm} -pin  "ACC1:acc#155" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#482.itm}
+load net {ACC1:acc#155.itm(0)} -pin  "ACC1:acc#155" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#155.itm}
+load net {ACC1:acc#155.itm(1)} -pin  "ACC1:acc#155" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#155.itm}
+load net {ACC1:acc#155.itm(2)} -pin  "ACC1:acc#155" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#155.itm}
+load inst "ACC1-1:not#126" "not(1)" "INTERFACE" -attr xrf 25985 -attr oid 1281 -attr @path {/sobel/sobel:core/ACC1-1:not#126} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(5)} -pin  "ACC1-1:not#126" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#2.itm}
+load net {ACC1-1:not#126.itm} -pin  "ACC1-1:not#126" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#126.itm}
+load inst "ACC1:acc#154" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25986 -attr oid 1282 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#154" {A(0)} -attr @path {/sobel/sobel:core/conc#716.itm}
+load net {acc#10.psp#2.sva(4)} -pin  "ACC1:acc#154" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#716.itm}
+load net {acc#10.psp#2.sva(6)} -pin  "ACC1:acc#154" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#480.itm}
+load net {ACC1-1:not#126.itm} -pin  "ACC1:acc#154" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#480.itm}
+load net {ACC1:acc#154.itm(0)} -pin  "ACC1:acc#154" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154.itm}
+load net {ACC1:acc#154.itm(1)} -pin  "ACC1:acc#154" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154.itm}
+load net {ACC1:acc#154.itm(2)} -pin  "ACC1:acc#154" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154.itm}
+load inst "ACC1-1:not#128" "not(1)" "INTERFACE" -attr xrf 25987 -attr oid 1283 -attr @path {/sobel/sobel:core/ACC1-1:not#128} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1-1:not#128" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#59.itm}
+load net {ACC1-1:not#128.itm} -pin  "ACC1-1:not#128" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#128.itm}
+load inst "ACC1:acc#157" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 25988 -attr oid 1284 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#157} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#157" {A(0)} -attr @path {/sobel/sobel:core/conc#714.itm}
+load net {ACC1:acc#155.itm(1)} -pin  "ACC1:acc#157" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#714.itm}
+load net {ACC1:acc#155.itm(2)} -pin  "ACC1:acc#157" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#714.itm}
+load net {ACC1-1:not#128.itm} -pin  "ACC1:acc#157" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#486.itm}
+load net {ACC1:acc#154.itm(1)} -pin  "ACC1:acc#157" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#486.itm}
+load net {ACC1:acc#154.itm(2)} -pin  "ACC1:acc#157" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#486.itm}
+load net {ACC1:acc#157.itm(0)} -pin  "ACC1:acc#157" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load net {ACC1:acc#157.itm(1)} -pin  "ACC1:acc#157" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load net {ACC1:acc#157.itm(2)} -pin  "ACC1:acc#157" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load net {ACC1:acc#157.itm(3)} -pin  "ACC1:acc#157" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load inst "ACC1-1:acc#113" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 25989 -attr oid 1285 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#113} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#158.itm(1)} -pin  "ACC1-1:acc#113" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#158.itm(2)} -pin  "ACC1-1:acc#113" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#158.itm(3)} -pin  "ACC1-1:acc#113" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#158.itm(4)} -pin  "ACC1-1:acc#113" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#157.itm(1)} -pin  "ACC1-1:acc#113" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#25.itm}
+load net {ACC1:acc#157.itm(2)} -pin  "ACC1-1:acc#113" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#25.itm}
+load net {ACC1:acc#157.itm(3)} -pin  "ACC1-1:acc#113" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#25.itm}
+load net {ACC1:acc#113.psp#2.sva(0)} -pin  "ACC1-1:acc#113" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#2.sva}
+load net {ACC1:acc#113.psp#2.sva(1)} -pin  "ACC1-1:acc#113" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#2.sva}
+load net {ACC1:acc#113.psp#2.sva(2)} -pin  "ACC1-1:acc#113" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#2.sva}
+load net {ACC1:acc#113.psp#2.sva(3)} -pin  "ACC1-1:acc#113" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#2.sva}
+load inst "ACC1-1:not#141" "not(1)" "INTERFACE" -attr xrf 25990 -attr oid 1286 -attr @path {/sobel/sobel:core/ACC1-1:not#141} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#113.psp#2.sva(1)} -pin  "ACC1-1:not#141" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#113.psp#2.sva)#4.itm}
+load net {ACC1-1:not#141.itm} -pin  "ACC1-1:not#141" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#141.itm}
+load inst "ACC1:acc#159" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25991 -attr oid 1287 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#159} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#159" {A(0)} -attr @path {/sobel/sobel:core/conc#717.itm}
+load net {ACC1:acc#113.psp#2.sva(0)} -pin  "ACC1:acc#159" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#717.itm}
+load net {ACC1:acc#113.psp#2.sva(2)} -pin  "ACC1:acc#159" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#490.itm}
+load net {ACC1-1:not#141.itm} -pin  "ACC1:acc#159" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#490.itm}
+load net {ACC1:acc#159.itm(0)} -pin  "ACC1:acc#159" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#159.itm}
+load net {ACC1:acc#159.itm(1)} -pin  "ACC1:acc#159" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#159.itm}
+load net {ACC1:acc#159.itm(2)} -pin  "ACC1:acc#159" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#159.itm}
+load inst "ACC1-1:not#155" "not(1)" "INTERFACE" -attr xrf 25992 -attr oid 1288 -attr @path {/sobel/sobel:core/ACC1-1:not#155} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#113.psp#2.sva(3)} -pin  "ACC1-1:not#155" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#113.psp#2.sva)#1.itm}
+load net {ACC1-1:not#155.itm} -pin  "ACC1-1:not#155" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#155.itm}
+load inst "ACC1-1:acc#120" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 25993 -attr oid 1289 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#120} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#159.itm(1)} -pin  "ACC1-1:acc#120" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#27.itm}
+load net {ACC1:acc#159.itm(2)} -pin  "ACC1-1:acc#120" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#27.itm}
+load net {ACC1-1:not#155.itm} -pin  "ACC1-1:acc#120" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#155.itm}
+load net {ACC1:acc#120.psp#1.sva(0)} -pin  "ACC1-1:acc#120" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#120.psp#1.sva}
+load net {ACC1:acc#120.psp#1.sva(1)} -pin  "ACC1-1:acc#120" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#120.psp#1.sva}
+load net {ACC1:acc#120.psp#1.sva(2)} -pin  "ACC1-1:acc#120" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#120.psp#1.sva}
+load inst "ACC1:acc#277" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 25994 -attr oid 1290 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#277" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#850.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#277" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#850.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#277" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#827.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#277" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#827.itm}
+load net {ACC1:acc#277.cse(0)} -pin  "ACC1:acc#277" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#277.cse(1)} -pin  "ACC1:acc#277" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#277.cse(2)} -pin  "ACC1:acc#277" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load inst "ACC1-3:not#149" "not(2)" "INTERFACE" -attr xrf 25995 -attr oid 1291 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#149} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#120.psp.sva(1)} -pin  "ACC1-3:not#149" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp.sva).itm}
+load net {ACC1:acc#120.psp.sva(2)} -pin  "ACC1-3:not#149" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp.sva).itm}
+load net {ACC1-3:not#149.itm(0)} -pin  "ACC1-3:not#149" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#149.itm}
+load net {ACC1-3:not#149.itm(1)} -pin  "ACC1-3:not#149" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#149.itm}
+load inst "ACC1:acc#187" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 25996 -attr oid 1292 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#187" {A(0)} -attr @path {/sobel/sobel:core/conc#718.itm}
+load net {ACC1-3:not#149.itm(0)} -pin  "ACC1:acc#187" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#718.itm}
+load net {ACC1-3:not#149.itm(1)} -pin  "ACC1:acc#187" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#718.itm}
+load net {PWR} -pin  "ACC1:acc#187" {B(0)} -attr @path {/sobel/sobel:core/conc#719.itm}
+load net {ACC1:acc#120.psp.sva(0)} -pin  "ACC1:acc#187" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#719.itm}
+load net {ACC1:acc#187.itm(0)} -pin  "ACC1:acc#187" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load net {ACC1:acc#187.itm(1)} -pin  "ACC1:acc#187" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load net {ACC1:acc#187.itm(2)} -pin  "ACC1:acc#187" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load net {ACC1:acc#187.itm(3)} -pin  "ACC1:acc#187" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load inst "ACC1:acc#162" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 25997 -attr oid 1293 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.regs(1).sva(10)} -pin  "ACC1:acc#162" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(11)} -pin  "ACC1:acc#162" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(12)} -pin  "ACC1:acc#162" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(13)} -pin  "ACC1:acc#162" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(14)} -pin  "ACC1:acc#162" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(15)} -pin  "ACC1:acc#162" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(16)} -pin  "ACC1:acc#162" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(17)} -pin  "ACC1:acc#162" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(18)} -pin  "ACC1:acc#162" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(19)} -pin  "ACC1:acc#162" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(0)} -pin  "ACC1:acc#162" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(1)} -pin  "ACC1:acc#162" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(2)} -pin  "ACC1:acc#162" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(3)} -pin  "ACC1:acc#162" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(4)} -pin  "ACC1:acc#162" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(5)} -pin  "ACC1:acc#162" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(6)} -pin  "ACC1:acc#162" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(7)} -pin  "ACC1:acc#162" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(8)} -pin  "ACC1:acc#162" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(9)} -pin  "ACC1:acc#162" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {ACC1:acc#162.itm(0)} -pin  "ACC1:acc#162" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(1)} -pin  "ACC1:acc#162" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(2)} -pin  "ACC1:acc#162" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(3)} -pin  "ACC1:acc#162" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(4)} -pin  "ACC1:acc#162" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(5)} -pin  "ACC1:acc#162" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(6)} -pin  "ACC1:acc#162" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(7)} -pin  "ACC1:acc#162" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(8)} -pin  "ACC1:acc#162" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(9)} -pin  "ACC1:acc#162" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(10)} -pin  "ACC1:acc#162" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load inst "ACC1-3:acc" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 25998 -attr oid 1294 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#162.itm(0)} -pin  "ACC1-3:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(1)} -pin  "ACC1-3:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(2)} -pin  "ACC1-3:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(3)} -pin  "ACC1-3:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(4)} -pin  "ACC1-3:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(5)} -pin  "ACC1-3:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(6)} -pin  "ACC1-3:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(7)} -pin  "ACC1-3:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(8)} -pin  "ACC1-3:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(9)} -pin  "ACC1-3:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(10)} -pin  "ACC1-3:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {regs.regs(1).sva(20)} -pin  "ACC1-3:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(21)} -pin  "ACC1-3:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(22)} -pin  "ACC1-3:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(23)} -pin  "ACC1-3:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(24)} -pin  "ACC1-3:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(25)} -pin  "ACC1-3:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(26)} -pin  "ACC1-3:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(27)} -pin  "ACC1-3:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(28)} -pin  "ACC1-3:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(29)} -pin  "ACC1-3:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {acc.psp#1.sva(0)} -pin  "ACC1-3:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(1)} -pin  "ACC1-3:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(2)} -pin  "ACC1-3:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(3)} -pin  "ACC1-3:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(4)} -pin  "ACC1-3:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(5)} -pin  "ACC1-3:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(6)} -pin  "ACC1-3:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(7)} -pin  "ACC1-3:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(8)} -pin  "ACC1-3:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(9)} -pin  "ACC1-3:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(10)} -pin  "ACC1-3:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load inst "ACC1-3:not#160" "not(1)" "INTERFACE" -attr xrf 25999 -attr oid 1295 -attr @path {/sobel/sobel:core/ACC1-3:not#160} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:not#160" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#42.itm}
+load net {ACC1-3:not#160.itm} -pin  "ACC1-3:not#160" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#160.itm}
+load inst "ACC1-3:not#106" "not(1)" "INTERFACE" -attr xrf 26000 -attr oid 1296 -attr @path {/sobel/sobel:core/ACC1-3:not#106} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(1)} -pin  "ACC1-3:not#106" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#4.itm}
+load net {ACC1-3:not#106.itm} -pin  "ACC1-3:not#106" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#106.itm}
+load inst "ACC1:acc#165" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 26001 -attr oid 1297 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#165" {A(0)} -attr @path {/sobel/sobel:core/conc#721.itm}
+load net {ACC1-3:not#160.itm} -pin  "ACC1:acc#165" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#721.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#165" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#502.itm}
+load net {ACC1-3:not#106.itm} -pin  "ACC1:acc#165" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#502.itm}
+load net {ACC1:acc#165.itm(0)} -pin  "ACC1:acc#165" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(1)} -pin  "ACC1:acc#165" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(2)} -pin  "ACC1:acc#165" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(3)} -pin  "ACC1:acc#165" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load inst "ACC1:acc#167" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 26002 -attr oid 1298 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#167" {A(0)} -attr @path {/sobel/sobel:core/conc#720.itm}
+load net {ACC1:acc#165.itm(1)} -pin  "ACC1:acc#167" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#720.itm}
+load net {ACC1:acc#165.itm(2)} -pin  "ACC1:acc#167" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#720.itm}
+load net {ACC1:acc#165.itm(3)} -pin  "ACC1:acc#167" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#720.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#167" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#722.itm}
+load net {acc.psp#1.sva(0)} -pin  "ACC1:acc#167" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#722.itm}
+load net {GND} -pin  "ACC1:acc#167" {B(2)} -attr @path {/sobel/sobel:core/conc#722.itm}
+load net {PWR} -pin  "ACC1:acc#167" {B(3)} -attr @path {/sobel/sobel:core/conc#722.itm}
+load net {ACC1:acc#167.itm(0)} -pin  "ACC1:acc#167" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load net {ACC1:acc#167.itm(1)} -pin  "ACC1:acc#167" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load net {ACC1:acc#167.itm(2)} -pin  "ACC1:acc#167" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load net {ACC1:acc#167.itm(3)} -pin  "ACC1:acc#167" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load net {ACC1:acc#167.itm(4)} -pin  "ACC1:acc#167" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load inst "ACC1-3:not#107" "not(1)" "INTERFACE" -attr xrf 26003 -attr oid 1299 -attr @path {/sobel/sobel:core/ACC1-3:not#107} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(3)} -pin  "ACC1-3:not#107" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#3.itm}
+load net {ACC1-3:not#107.itm} -pin  "ACC1-3:not#107" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#107.itm}
+load inst "ACC1-3:not#109" "not(1)" "INTERFACE" -attr xrf 26004 -attr oid 1300 -attr @path {/sobel/sobel:core/ACC1-3:not#109} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(7)} -pin  "ACC1-3:not#109" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#6.itm}
+load net {ACC1-3:not#109.itm} -pin  "ACC1-3:not#109" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#109.itm}
+load inst "ACC1:acc#164" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 26005 -attr oid 1301 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#164" {A(0)} -attr @path {/sobel/sobel:core/conc#724.itm}
+load net {acc.psp#1.sva(2)} -pin  "ACC1:acc#164" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#724.itm}
+load net {ACC1-3:not#109.itm} -pin  "ACC1:acc#164" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#500.itm}
+load net {ACC1-3:not#107.itm} -pin  "ACC1:acc#164" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#500.itm}
+load net {ACC1:acc#164.itm(0)} -pin  "ACC1:acc#164" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164.itm}
+load net {ACC1:acc#164.itm(1)} -pin  "ACC1:acc#164" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164.itm}
+load net {ACC1:acc#164.itm(2)} -pin  "ACC1:acc#164" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164.itm}
+load inst "ACC1-3:not#108" "not(1)" "INTERFACE" -attr xrf 26006 -attr oid 1302 -attr @path {/sobel/sobel:core/ACC1-3:not#108} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(5)} -pin  "ACC1-3:not#108" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#12.itm}
+load net {ACC1-3:not#108.itm} -pin  "ACC1-3:not#108" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#108.itm}
+load inst "ACC1:acc#163" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 26007 -attr oid 1303 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#163" {A(0)} -attr @path {/sobel/sobel:core/conc#725.itm}
+load net {acc.psp#1.sva(4)} -pin  "ACC1:acc#163" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#725.itm}
+load net {acc.psp#1.sva(6)} -pin  "ACC1:acc#163" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#498.itm}
+load net {ACC1-3:not#108.itm} -pin  "ACC1:acc#163" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#498.itm}
+load net {ACC1:acc#163.itm(0)} -pin  "ACC1:acc#163" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163.itm}
+load net {ACC1:acc#163.itm(1)} -pin  "ACC1:acc#163" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163.itm}
+load net {ACC1:acc#163.itm(2)} -pin  "ACC1:acc#163" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163.itm}
+load inst "ACC1-3:not#110" "not(1)" "INTERFACE" -attr xrf 26008 -attr oid 1304 -attr @path {/sobel/sobel:core/ACC1-3:not#110} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(9)} -pin  "ACC1-3:not#110" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#23.itm}
+load net {ACC1-3:not#110.itm} -pin  "ACC1-3:not#110" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#110.itm}
+load inst "ACC1:acc#166" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 26009 -attr oid 1305 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#166" {A(0)} -attr @path {/sobel/sobel:core/conc#723.itm}
+load net {ACC1:acc#164.itm(1)} -pin  "ACC1:acc#166" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#723.itm}
+load net {ACC1:acc#164.itm(2)} -pin  "ACC1:acc#166" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#723.itm}
+load net {ACC1-3:not#110.itm} -pin  "ACC1:acc#166" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#504.itm}
+load net {ACC1:acc#163.itm(1)} -pin  "ACC1:acc#166" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#504.itm}
+load net {ACC1:acc#163.itm(2)} -pin  "ACC1:acc#166" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#504.itm}
+load net {ACC1:acc#166.itm(0)} -pin  "ACC1:acc#166" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load net {ACC1:acc#166.itm(1)} -pin  "ACC1:acc#166" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load net {ACC1:acc#166.itm(2)} -pin  "ACC1:acc#166" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load net {ACC1:acc#166.itm(3)} -pin  "ACC1:acc#166" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load inst "ACC1-3:acc#107" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 26010 -attr oid 1306 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#107} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#167.itm(1)} -pin  "ACC1-3:acc#107" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#167.itm(2)} -pin  "ACC1-3:acc#107" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#167.itm(3)} -pin  "ACC1-3:acc#107" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#167.itm(4)} -pin  "ACC1-3:acc#107" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#166.itm(1)} -pin  "ACC1-3:acc#107" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#166.itm(2)} -pin  "ACC1-3:acc#107" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#166.itm(3)} -pin  "ACC1-3:acc#107" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#107.psp#1.sva(0)} -pin  "ACC1-3:acc#107" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#1.sva}
+load net {ACC1:acc#107.psp#1.sva(1)} -pin  "ACC1-3:acc#107" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#1.sva}
+load net {ACC1:acc#107.psp#1.sva(2)} -pin  "ACC1-3:acc#107" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#1.sva}
+load net {ACC1:acc#107.psp#1.sva(3)} -pin  "ACC1-3:acc#107" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#1.sva}
+load inst "ACC1-3:not#133" "not(1)" "INTERFACE" -attr xrf 26011 -attr oid 1307 -attr @path {/sobel/sobel:core/ACC1-3:not#133} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#107.psp#1.sva(1)} -pin  "ACC1-3:not#133" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#107.psp#1.sva)#4.itm}
+load net {ACC1-3:not#133.itm} -pin  "ACC1-3:not#133" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#133.itm}
+load inst "ACC1:acc#168" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 26012 -attr oid 1308 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#168" {A(0)} -attr @path {/sobel/sobel:core/conc#726.itm}
+load net {ACC1:acc#107.psp#1.sva(0)} -pin  "ACC1:acc#168" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#726.itm}
+load net {ACC1:acc#107.psp#1.sva(2)} -pin  "ACC1:acc#168" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#508.itm}
+load net {ACC1-3:not#133.itm} -pin  "ACC1:acc#168" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#508.itm}
+load net {ACC1:acc#168.itm(0)} -pin  "ACC1:acc#168" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168.itm}
+load net {ACC1:acc#168.itm(1)} -pin  "ACC1:acc#168" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168.itm}
+load net {ACC1:acc#168.itm(2)} -pin  "ACC1:acc#168" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168.itm}
+load inst "ACC1-3:not#153" "not(1)" "INTERFACE" -attr xrf 26013 -attr oid 1309 -attr @path {/sobel/sobel:core/ACC1-3:not#153} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#107.psp#1.sva(3)} -pin  "ACC1-3:not#153" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#107.psp#1.sva).itm}
+load net {ACC1-3:not#153.itm} -pin  "ACC1-3:not#153" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#153.itm}
+load inst "ACC1-3:acc#116" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 26014 -attr oid 1310 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#116} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#168.itm(1)} -pin  "ACC1-3:acc#116" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#35.itm}
+load net {ACC1:acc#168.itm(2)} -pin  "ACC1-3:acc#116" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#35.itm}
+load net {ACC1-3:not#153.itm} -pin  "ACC1-3:acc#116" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#153.itm}
+load net {ACC1:acc#116.psp.sva(0)} -pin  "ACC1-3:acc#116" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp.sva}
+load net {ACC1:acc#116.psp.sva(1)} -pin  "ACC1-3:acc#116" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp.sva}
+load net {ACC1:acc#116.psp.sva(2)} -pin  "ACC1-3:acc#116" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp.sva}
+load inst "ACC1:acc#197" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 26015 -attr oid 1311 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#197" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#562.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#197" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#562.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#197" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#551.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#197" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#551.itm}
+load net {ACC1:acc#197.cse(0)} -pin  "ACC1:acc#197" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#197.cse(1)} -pin  "ACC1:acc#197" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#197.cse(2)} -pin  "ACC1:acc#197" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load inst "ACC1-3:not#25" "not(1)" "INTERFACE" -attr xrf 26016 -attr oid 1312 -attr @path {/sobel/sobel:core/ACC1-3:not#25} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#169.itm(2)} -pin  "ACC1-3:not#25" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#3.itm}
+load net {ACC1-3:not#25.itm} -pin  "ACC1-3:not#25" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#25.itm}
+load inst "ACC1-3:not#162" "not(1)" "INTERFACE" -attr xrf 26017 -attr oid 1313 -attr @path {/sobel/sobel:core/ACC1-3:not#162} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#169.itm(3)} -pin  "ACC1-3:not#162" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva).itm}
+load net {ACC1-3:not#162.itm} -pin  "ACC1-3:not#162" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#162.itm}
+load inst "ACC1:acc#170" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 26018 -attr oid 1314 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#170" {A(0)} -attr @path {/sobel/sobel:core/conc#727.itm}
+load net {ACC1:acc#169.itm(1)} -pin  "ACC1:acc#170" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#727.itm}
+load net {PWR} -pin  "ACC1:acc#170" {A(2)} -attr @path {/sobel/sobel:core/conc#727.itm}
+load net {ACC1-3:not#162.itm} -pin  "ACC1:acc#170" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#513.itm}
+load net {ACC1-3:not#25.itm} -pin  "ACC1:acc#170" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#513.itm}
+load net {ACC1:acc#170.itm(0)} -pin  "ACC1:acc#170" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170.itm}
+load net {ACC1:acc#170.itm(1)} -pin  "ACC1:acc#170" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170.itm}
+load net {ACC1:acc#170.itm(2)} -pin  "ACC1:acc#170" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170.itm}
+load inst "ACC1:not" "not(10)" "INTERFACE" -attr xrf 26019 -attr oid 1315 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "ACC1:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "ACC1:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "ACC1:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "ACC1:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "ACC1:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "ACC1:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "ACC1:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "ACC1:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "ACC1:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load inst "ACC1:not#156" "not(10)" "INTERFACE" -attr xrf 26020 -attr oid 1316 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "ACC1:not#156" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "ACC1:not#156" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "ACC1:not#156" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "ACC1:not#156" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "ACC1:not#156" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "ACC1:not#156" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "ACC1:not#156" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "ACC1:not#156" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "ACC1:not#156" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:not#156" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {ACC1:not#156.itm(0)} -pin  "ACC1:not#156" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(1)} -pin  "ACC1:not#156" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(2)} -pin  "ACC1:not#156" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(3)} -pin  "ACC1:not#156" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(4)} -pin  "ACC1:not#156" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(5)} -pin  "ACC1:not#156" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(6)} -pin  "ACC1:not#156" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(7)} -pin  "ACC1:not#156" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(8)} -pin  "ACC1:not#156" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(9)} -pin  "ACC1:not#156" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load inst "ACC1:acc#133" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 26021 -attr oid 1317 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not.itm(0)} -pin  "ACC1:acc#133" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:acc#133" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:acc#133" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:acc#133" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:acc#133" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:acc#133" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:acc#133" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:acc#133" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:acc#133" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:acc#133" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not#156.itm(0)} -pin  "ACC1:acc#133" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(1)} -pin  "ACC1:acc#133" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(2)} -pin  "ACC1:acc#133" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(3)} -pin  "ACC1:acc#133" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(4)} -pin  "ACC1:acc#133" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(5)} -pin  "ACC1:acc#133" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(6)} -pin  "ACC1:acc#133" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(7)} -pin  "ACC1:acc#133" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(8)} -pin  "ACC1:acc#133" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(9)} -pin  "ACC1:acc#133" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:acc#133.itm(0)} -pin  "ACC1:acc#133" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(1)} -pin  "ACC1:acc#133" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(2)} -pin  "ACC1:acc#133" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(3)} -pin  "ACC1:acc#133" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(4)} -pin  "ACC1:acc#133" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(5)} -pin  "ACC1:acc#133" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(6)} -pin  "ACC1:acc#133" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(7)} -pin  "ACC1:acc#133" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(8)} -pin  "ACC1:acc#133" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(9)} -pin  "ACC1:acc#133" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(10)} -pin  "ACC1:acc#133" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load inst "ACC1:not#157" "not(10)" "INTERFACE" -attr xrf 26022 -attr oid 1318 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "ACC1:not#157" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "ACC1:not#157" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "ACC1:not#157" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "ACC1:not#157" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "ACC1:not#157" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "ACC1:not#157" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "ACC1:not#157" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "ACC1:not#157" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "ACC1:not#157" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1:not#157" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {ACC1:not#157.itm(0)} -pin  "ACC1:not#157" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(1)} -pin  "ACC1:not#157" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(2)} -pin  "ACC1:not#157" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(3)} -pin  "ACC1:not#157" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(4)} -pin  "ACC1:not#157" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(5)} -pin  "ACC1:not#157" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(6)} -pin  "ACC1:not#157" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(7)} -pin  "ACC1:not#157" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(8)} -pin  "ACC1:not#157" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(9)} -pin  "ACC1:not#157" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load inst "ACC1:acc#132" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 26023 -attr oid 1319 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#157.itm(0)} -pin  "ACC1:acc#132" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(1)} -pin  "ACC1:acc#132" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(2)} -pin  "ACC1:acc#132" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(3)} -pin  "ACC1:acc#132" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(4)} -pin  "ACC1:acc#132" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(5)} -pin  "ACC1:acc#132" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(6)} -pin  "ACC1:acc#132" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(7)} -pin  "ACC1:acc#132" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(8)} -pin  "ACC1:acc#132" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(9)} -pin  "ACC1:acc#132" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {PWR} -pin  "ACC1:acc#132" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#132" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#132.itm(0)} -pin  "ACC1:acc#132" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(1)} -pin  "ACC1:acc#132" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(2)} -pin  "ACC1:acc#132" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(3)} -pin  "ACC1:acc#132" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(4)} -pin  "ACC1:acc#132" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(5)} -pin  "ACC1:acc#132" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(6)} -pin  "ACC1:acc#132" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(7)} -pin  "ACC1:acc#132" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(8)} -pin  "ACC1:acc#132" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(9)} -pin  "ACC1:acc#132" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(10)} -pin  "ACC1:acc#132" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load inst "ACC1-1:acc" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 26024 -attr oid 1320 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#133.itm(0)} -pin  "ACC1-1:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(1)} -pin  "ACC1-1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(2)} -pin  "ACC1-1:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(3)} -pin  "ACC1-1:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(4)} -pin  "ACC1-1:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(5)} -pin  "ACC1-1:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(6)} -pin  "ACC1-1:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(7)} -pin  "ACC1-1:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(8)} -pin  "ACC1-1:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(9)} -pin  "ACC1-1:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(10)} -pin  "ACC1-1:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#132.itm(0)} -pin  "ACC1-1:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(1)} -pin  "ACC1-1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(2)} -pin  "ACC1-1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(3)} -pin  "ACC1-1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(4)} -pin  "ACC1-1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(5)} -pin  "ACC1-1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(6)} -pin  "ACC1-1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(7)} -pin  "ACC1-1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(8)} -pin  "ACC1-1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(9)} -pin  "ACC1-1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(10)} -pin  "ACC1-1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {acc.psp#2.sva(0)} -pin  "ACC1-1:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(1)} -pin  "ACC1-1:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(2)} -pin  "ACC1-1:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(3)} -pin  "ACC1-1:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(4)} -pin  "ACC1-1:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(5)} -pin  "ACC1-1:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(6)} -pin  "ACC1-1:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(7)} -pin  "ACC1-1:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(8)} -pin  "ACC1-1:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(9)} -pin  "ACC1-1:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(10)} -pin  "ACC1-1:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load inst "ACC1-1:not#25" "not(1)" "INTERFACE" -attr xrf 26025 -attr oid 1321 -attr @path {/sobel/sobel:core/ACC1-1:not#25} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#140.itm(2)} -pin  "ACC1-1:not#25" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#14.sva)#3.itm}
+load net {ACC1-1:not#25.itm} -pin  "ACC1-1:not#25" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#25.itm}
+load inst "ACC1-1:not#162" "not(1)" "INTERFACE" -attr xrf 26026 -attr oid 1322 -attr @path {/sobel/sobel:core/ACC1-1:not#162} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#140.itm(3)} -pin  "ACC1-1:not#162" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#14.sva).itm}
+load net {ACC1-1:not#162.itm} -pin  "ACC1-1:not#162" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#162.itm}
+load inst "ACC1:acc#141" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 26027 -attr oid 1323 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#141" {A(0)} -attr @path {/sobel/sobel:core/conc#728.itm}
+load net {ACC1:acc#140.itm(1)} -pin  "ACC1:acc#141" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#728.itm}
+load net {PWR} -pin  "ACC1:acc#141" {A(2)} -attr @path {/sobel/sobel:core/conc#728.itm}
+load net {ACC1-1:not#162.itm} -pin  "ACC1:acc#141" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#459.itm}
+load net {ACC1-1:not#25.itm} -pin  "ACC1:acc#141" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#459.itm}
+load net {ACC1:acc#141.itm(0)} -pin  "ACC1:acc#141" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141.itm}
+load net {ACC1:acc#141.itm(1)} -pin  "ACC1:acc#141" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141.itm}
+load net {ACC1:acc#141.itm(2)} -pin  "ACC1:acc#141" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141.itm}
+load inst "ACC1-1:not#145" "not(2)" "INTERFACE" -attr xrf 26028 -attr oid 1324 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#145} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#116.psp#1.sva(1)} -pin  "ACC1-1:not#145" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp#1.sva).itm}
+load net {ACC1:acc#116.psp#1.sva(2)} -pin  "ACC1-1:not#145" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp#1.sva).itm}
+load net {ACC1-1:not#145.itm(0)} -pin  "ACC1-1:not#145" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#145.itm}
+load net {ACC1-1:not#145.itm(1)} -pin  "ACC1-1:not#145" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#145.itm}
+load inst "ACC1:acc#140" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 26029 -attr oid 1325 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#140" {A(0)} -attr @path {/sobel/sobel:core/conc#729.itm}
+load net {ACC1-1:not#145.itm(0)} -pin  "ACC1:acc#140" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#729.itm}
+load net {ACC1-1:not#145.itm(1)} -pin  "ACC1:acc#140" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#729.itm}
+load net {PWR} -pin  "ACC1:acc#140" {B(0)} -attr @path {/sobel/sobel:core/conc#730.itm}
+load net {ACC1:acc#116.psp#1.sva(0)} -pin  "ACC1:acc#140" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#730.itm}
+load net {ACC1:acc#140.itm(0)} -pin  "ACC1:acc#140" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load net {ACC1:acc#140.itm(1)} -pin  "ACC1:acc#140" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load net {ACC1:acc#140.itm(2)} -pin  "ACC1:acc#140" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load net {ACC1:acc#140.itm(3)} -pin  "ACC1:acc#140" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load inst "ACC1-1:not#160" "not(1)" "INTERFACE" -attr xrf 26030 -attr oid 1326 -attr @path {/sobel/sobel:core/ACC1-1:not#160} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:not#160" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#32.itm}
+load net {ACC1-1:not#160.itm} -pin  "ACC1-1:not#160" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#160.itm}
+load inst "ACC1-1:not#106" "not(1)" "INTERFACE" -attr xrf 26031 -attr oid 1327 -attr @path {/sobel/sobel:core/ACC1-1:not#106} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(1)} -pin  "ACC1-1:not#106" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#8.itm}
+load net {ACC1-1:not#106.itm} -pin  "ACC1-1:not#106" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#106.itm}
+load inst "ACC1:acc#136" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 26032 -attr oid 1328 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#136" {A(0)} -attr @path {/sobel/sobel:core/conc#732.itm}
+load net {ACC1-1:not#160.itm} -pin  "ACC1:acc#136" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#732.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#136" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#448.itm}
+load net {ACC1-1:not#106.itm} -pin  "ACC1:acc#136" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#448.itm}
+load net {ACC1:acc#136.itm(0)} -pin  "ACC1:acc#136" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load net {ACC1:acc#136.itm(1)} -pin  "ACC1:acc#136" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load net {ACC1:acc#136.itm(2)} -pin  "ACC1:acc#136" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load net {ACC1:acc#136.itm(3)} -pin  "ACC1:acc#136" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load inst "ACC1:acc#138" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 26033 -attr oid 1329 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#138" {A(0)} -attr @path {/sobel/sobel:core/conc#731.itm}
+load net {ACC1:acc#136.itm(1)} -pin  "ACC1:acc#138" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#731.itm}
+load net {ACC1:acc#136.itm(2)} -pin  "ACC1:acc#138" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#731.itm}
+load net {ACC1:acc#136.itm(3)} -pin  "ACC1:acc#138" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#731.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#138" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#733.itm}
+load net {acc.psp#2.sva(0)} -pin  "ACC1:acc#138" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#733.itm}
+load net {GND} -pin  "ACC1:acc#138" {B(2)} -attr @path {/sobel/sobel:core/conc#733.itm}
+load net {PWR} -pin  "ACC1:acc#138" {B(3)} -attr @path {/sobel/sobel:core/conc#733.itm}
+load net {ACC1:acc#138.itm(0)} -pin  "ACC1:acc#138" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {ACC1:acc#138.itm(1)} -pin  "ACC1:acc#138" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {ACC1:acc#138.itm(2)} -pin  "ACC1:acc#138" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {ACC1:acc#138.itm(3)} -pin  "ACC1:acc#138" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {ACC1:acc#138.itm(4)} -pin  "ACC1:acc#138" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load inst "ACC1-1:not#107" "not(1)" "INTERFACE" -attr xrf 26034 -attr oid 1330 -attr @path {/sobel/sobel:core/ACC1-1:not#107} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(3)} -pin  "ACC1-1:not#107" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#7.itm}
+load net {ACC1-1:not#107.itm} -pin  "ACC1-1:not#107" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#107.itm}
+load inst "ACC1-1:not#109" "not(1)" "INTERFACE" -attr xrf 26035 -attr oid 1331 -attr @path {/sobel/sobel:core/ACC1-1:not#109} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(7)} -pin  "ACC1-1:not#109" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#3.itm}
+load net {ACC1-1:not#109.itm} -pin  "ACC1-1:not#109" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#109.itm}
+load inst "ACC1:acc#135" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 26036 -attr oid 1332 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#135" {A(0)} -attr @path {/sobel/sobel:core/conc#735.itm}
+load net {acc.psp#2.sva(2)} -pin  "ACC1:acc#135" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#735.itm}
+load net {ACC1-1:not#109.itm} -pin  "ACC1:acc#135" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#446.itm}
+load net {ACC1-1:not#107.itm} -pin  "ACC1:acc#135" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#446.itm}
+load net {ACC1:acc#135.itm(0)} -pin  "ACC1:acc#135" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135.itm}
+load net {ACC1:acc#135.itm(1)} -pin  "ACC1:acc#135" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135.itm}
+load net {ACC1:acc#135.itm(2)} -pin  "ACC1:acc#135" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135.itm}
+load inst "ACC1-1:not#108" "not(1)" "INTERFACE" -attr xrf 26037 -attr oid 1333 -attr @path {/sobel/sobel:core/ACC1-1:not#108} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(5)} -pin  "ACC1-1:not#108" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#2.itm}
+load net {ACC1-1:not#108.itm} -pin  "ACC1-1:not#108" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#108.itm}
+load inst "ACC1:acc#134" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 26038 -attr oid 1334 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#134" {A(0)} -attr @path {/sobel/sobel:core/conc#736.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#134" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#736.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#134" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#444.itm}
+load net {ACC1-1:not#108.itm} -pin  "ACC1:acc#134" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#444.itm}
+load net {ACC1:acc#134.itm(0)} -pin  "ACC1:acc#134" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134.itm}
+load net {ACC1:acc#134.itm(1)} -pin  "ACC1:acc#134" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134.itm}
+load net {ACC1:acc#134.itm(2)} -pin  "ACC1:acc#134" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134.itm}
+load inst "ACC1-1:not#110" "not(1)" "INTERFACE" -attr xrf 26039 -attr oid 1335 -attr @path {/sobel/sobel:core/ACC1-1:not#110} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(9)} -pin  "ACC1-1:not#110" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#59.itm}
+load net {ACC1-1:not#110.itm} -pin  "ACC1-1:not#110" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#110.itm}
+load inst "ACC1:acc#137" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 26040 -attr oid 1336 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#137" {A(0)} -attr @path {/sobel/sobel:core/conc#734.itm}
+load net {ACC1:acc#135.itm(1)} -pin  "ACC1:acc#137" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#734.itm}
+load net {ACC1:acc#135.itm(2)} -pin  "ACC1:acc#137" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#734.itm}
+load net {ACC1-1:not#110.itm} -pin  "ACC1:acc#137" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#450.itm}
+load net {ACC1:acc#134.itm(1)} -pin  "ACC1:acc#137" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#450.itm}
+load net {ACC1:acc#134.itm(2)} -pin  "ACC1:acc#137" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#450.itm}
+load net {ACC1:acc#137.itm(0)} -pin  "ACC1:acc#137" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load net {ACC1:acc#137.itm(1)} -pin  "ACC1:acc#137" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load net {ACC1:acc#137.itm(2)} -pin  "ACC1:acc#137" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load net {ACC1:acc#137.itm(3)} -pin  "ACC1:acc#137" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load inst "ACC1-1:acc#107" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 26041 -attr oid 1337 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#107} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#138.itm(1)} -pin  "ACC1-1:acc#107" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#10.itm}
+load net {ACC1:acc#138.itm(2)} -pin  "ACC1-1:acc#107" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#10.itm}
+load net {ACC1:acc#138.itm(3)} -pin  "ACC1-1:acc#107" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#10.itm}
+load net {ACC1:acc#138.itm(4)} -pin  "ACC1-1:acc#107" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#10.itm}
+load net {ACC1:acc#137.itm(1)} -pin  "ACC1-1:acc#107" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#137.itm(2)} -pin  "ACC1-1:acc#107" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#137.itm(3)} -pin  "ACC1-1:acc#107" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#107.psp#2.sva(0)} -pin  "ACC1-1:acc#107" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#2.sva}
+load net {ACC1:acc#107.psp#2.sva(1)} -pin  "ACC1-1:acc#107" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#2.sva}
+load net {ACC1:acc#107.psp#2.sva(2)} -pin  "ACC1-1:acc#107" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#2.sva}
+load net {ACC1:acc#107.psp#2.sva(3)} -pin  "ACC1-1:acc#107" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#2.sva}
+load inst "ACC1-1:not#133" "not(1)" "INTERFACE" -attr xrf 26042 -attr oid 1338 -attr @path {/sobel/sobel:core/ACC1-1:not#133} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#107.psp#2.sva(1)} -pin  "ACC1-1:not#133" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#107.psp#2.sva)#4.itm}
+load net {ACC1-1:not#133.itm} -pin  "ACC1-1:not#133" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#133.itm}
+load inst "ACC1:acc#139" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 26043 -attr oid 1339 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#139" {A(0)} -attr @path {/sobel/sobel:core/conc#737.itm}
+load net {ACC1:acc#107.psp#2.sva(0)} -pin  "ACC1:acc#139" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#737.itm}
+load net {ACC1:acc#107.psp#2.sva(2)} -pin  "ACC1:acc#139" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#454.itm}
+load net {ACC1-1:not#133.itm} -pin  "ACC1:acc#139" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#454.itm}
+load net {ACC1:acc#139.itm(0)} -pin  "ACC1:acc#139" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139.itm}
+load net {ACC1:acc#139.itm(1)} -pin  "ACC1:acc#139" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139.itm}
+load net {ACC1:acc#139.itm(2)} -pin  "ACC1:acc#139" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139.itm}
+load inst "ACC1-1:not#153" "not(1)" "INTERFACE" -attr xrf 26044 -attr oid 1340 -attr @path {/sobel/sobel:core/ACC1-1:not#153} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#107.psp#2.sva(3)} -pin  "ACC1-1:not#153" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#107.psp#2.sva)#1.itm}
+load net {ACC1-1:not#153.itm} -pin  "ACC1-1:not#153" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#153.itm}
+load inst "ACC1-1:acc#116" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 26045 -attr oid 1341 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#116} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#139.itm(1)} -pin  "ACC1-1:acc#116" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#139.itm(2)} -pin  "ACC1-1:acc#116" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1-1:not#153.itm} -pin  "ACC1-1:acc#116" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#153.itm}
+load net {ACC1:acc#116.psp#1.sva(0)} -pin  "ACC1-1:acc#116" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp#1.sva}
+load net {ACC1:acc#116.psp#1.sva(1)} -pin  "ACC1-1:acc#116" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp#1.sva}
+load net {ACC1:acc#116.psp#1.sva(2)} -pin  "ACC1-1:acc#116" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp#1.sva}
+load inst "ACC1:acc#224" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 26046 -attr oid 1342 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#224" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#858.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#224" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#858.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#224" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#833.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#224" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#833.itm}
+load net {ACC1:acc#224.cse(0)} -pin  "ACC1:acc#224" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#224.cse(1)} -pin  "ACC1:acc#224" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#224.cse(2)} -pin  "ACC1:acc#224" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load inst "ACC1-3:not#145" "not(2)" "INTERFACE" -attr xrf 26047 -attr oid 1343 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#145} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#116.psp.sva(1)} -pin  "ACC1-3:not#145" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp.sva).itm}
+load net {ACC1:acc#116.psp.sva(2)} -pin  "ACC1-3:not#145" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp.sva).itm}
+load net {ACC1-3:not#145.itm(0)} -pin  "ACC1-3:not#145" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#145.itm}
+load net {ACC1-3:not#145.itm(1)} -pin  "ACC1-3:not#145" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#145.itm}
+load inst "ACC1:acc#169" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 26048 -attr oid 1344 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#169" {A(0)} -attr @path {/sobel/sobel:core/conc#738.itm}
+load net {ACC1-3:not#145.itm(0)} -pin  "ACC1:acc#169" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#738.itm}
+load net {ACC1-3:not#145.itm(1)} -pin  "ACC1:acc#169" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#738.itm}
+load net {PWR} -pin  "ACC1:acc#169" {B(0)} -attr @path {/sobel/sobel:core/conc#739.itm}
+load net {ACC1:acc#116.psp.sva(0)} -pin  "ACC1:acc#169" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#739.itm}
+load net {ACC1:acc#169.itm(0)} -pin  "ACC1:acc#169" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load net {ACC1:acc#169.itm(1)} -pin  "ACC1:acc#169" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load net {ACC1:acc#169.itm(2)} -pin  "ACC1:acc#169" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load net {ACC1:acc#169.itm(3)} -pin  "ACC1:acc#169" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load inst "not#17" "not(1)" "INTERFACE" -attr xrf 26049 -attr oid 1345 -attr @path {/sobel/sobel:core/not#17} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1.dfm#4} -pin  "not#17" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#4}
+load net {not#17.itm} -pin  "not#17" {Z(0)} -attr @path {/sobel/sobel:core/not#17.itm}
+load inst "FRAME:for:and#2" "and(2,1)" "INTERFACE" -attr xrf 26050 -attr oid 1346 -attr @path {/sobel/sobel:core/FRAME:for:and#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {exit:FRAME.lpi#1.dfm#1} -pin  "FRAME:for:and#2" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1}
+load net {not#17.itm} -pin  "FRAME:for:and#2" {A1(0)} -attr @path {/sobel/sobel:core/not#17.itm}
+load net {FRAME:for:and#2.itm} -pin  "FRAME:for:and#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#2.itm}
+load inst "FRAME:acc" "add(7,0,8,-1,8)" "INTERFACE" -attr xrf 26051 -attr oid 1347 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {PWR} -pin  "FRAME:acc" {B(0)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(1)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(2)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(3)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(4)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(5)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(6)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(7)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {FRAME:acc.itm(0)} -pin  "FRAME:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(1)} -pin  "FRAME:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(2)} -pin  "FRAME:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(3)} -pin  "FRAME:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(4)} -pin  "FRAME:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(5)} -pin  "FRAME:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(6)} -pin  "FRAME:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(7)} -pin  "FRAME:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load inst "FRAME:not" "not(1)" "INTERFACE" -attr xrf 26052 -attr oid 1348 -attr @path {/sobel/sobel:core/FRAME:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc.itm(7)} -pin  "FRAME:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc.itm}
+load net {FRAME:not.itm} -pin  "FRAME:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load inst "mux#12" "mux(2,1)" "INTERFACE" -attr xrf 26053 -attr oid 1349 -attr @path {/sobel/sobel:core/mux#12} -attr area 0.920423 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2)"
+load net {FRAME:for:and#2.itm} -pin  "mux#12" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#2.itm}
+load net {FRAME:not.itm} -pin  "mux#12" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "mux#12" {S(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc.itm}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "mux#12" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load inst "FRAME:acc#4" "add(19,-1,1,0,19)" "INTERFACE" -attr xrf 26054 -attr oid 1350 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4} -attr area 20.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19)"
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "FRAME:acc#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "FRAME:acc#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "FRAME:acc#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "FRAME:acc#4" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "FRAME:acc#4" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "FRAME:acc#4" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "FRAME:acc#4" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "FRAME:acc#4" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "FRAME:acc#4" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "FRAME:acc#4" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "FRAME:acc#4" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "FRAME:acc#4" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "FRAME:acc#4" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "FRAME:acc#4" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "FRAME:acc#4" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "FRAME:acc#4" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "FRAME:acc#4" {A(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "FRAME:acc#4" {A(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "FRAME:acc#4" {A(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:acc#4" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:p#1.sva#1(0)} -pin  "FRAME:acc#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "FRAME:acc#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "FRAME:acc#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "FRAME:acc#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "FRAME:acc#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "FRAME:acc#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "FRAME:acc#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "FRAME:acc#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "FRAME:acc#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "FRAME:acc#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "FRAME:acc#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "FRAME:acc#4" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc#4" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc#4" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc#4" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc#4" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc#4" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc#4" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc#4" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load inst "FRAME:not#10" "not(1)" "INTERFACE" -attr xrf 26055 -attr oid 1351 -attr @path {/sobel/sobel:core/FRAME:not#10} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME#1.sva} -pin  "FRAME:not#10" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {FRAME:not#10.itm} -pin  "FRAME:not#10" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load inst "FRAME:for:and" "and(2,19)" "INTERFACE" -attr xrf 26056 -attr oid 1352 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and} -attr area 13.866816 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2)"
+load net {FRAME:p#1.lpi#1(0)} -pin  "FRAME:for:and" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "FRAME:for:and" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "FRAME:for:and" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "FRAME:for:and" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "FRAME:for:and" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "FRAME:for:and" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "FRAME:for:and" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "FRAME:for:and" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "FRAME:for:and" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "FRAME:for:and" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "FRAME:for:and" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "FRAME:for:and" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "FRAME:for:and" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "FRAME:for:and" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "FRAME:for:and" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "FRAME:for:and" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "FRAME:for:and" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "FRAME:for:and" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "FRAME:for:and" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "FRAME:for:and" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "FRAME:for:and" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "FRAME:for:and" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "FRAME:for:and" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "FRAME:for:and" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "FRAME:for:and" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "FRAME:for:and" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "FRAME:for:and" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "FRAME:for:and" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "FRAME:for:and" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "FRAME:for:and" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "FRAME:for:and" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "FRAME:for:and" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "FRAME:for:and" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "FRAME:for:and" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "FRAME:for:and" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "FRAME:for:and" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "FRAME:for:and" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "FRAME:for:and" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load inst "mux#13" "mux(2,12)" "INTERFACE" -attr xrf 26057 -attr oid 1353 -attr vt d -attr @path {/sobel/sobel:core/mux#13} -attr area 11.034076 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(12,1,2)"
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(0)} -pin  "mux#13" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(1)} -pin  "mux#13" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(2)} -pin  "mux#13" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(3)} -pin  "mux#13" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(4)} -pin  "mux#13" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(5)} -pin  "mux#13" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(6)} -pin  "mux#13" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(7)} -pin  "mux#13" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(8)} -pin  "mux#13" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(9)} -pin  "mux#13" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(10)} -pin  "mux#13" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(11)} -pin  "mux#13" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.sva(0)} -pin  "mux#13" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(1)} -pin  "mux#13" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(2)} -pin  "mux#13" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(3)} -pin  "mux#13" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(4)} -pin  "mux#13" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(5)} -pin  "mux#13" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(6)} -pin  "mux#13" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(7)} -pin  "mux#13" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(8)} -pin  "mux#13" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(9)} -pin  "mux#13" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(10)} -pin  "mux#13" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(11)} -pin  "mux#13" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {and.cse} -pin  "mux#13" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(0)} -pin  "mux#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(1)} -pin  "mux#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(2)} -pin  "mux#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(3)} -pin  "mux#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} -pin  "mux#13" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(5)} -pin  "mux#13" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -pin  "mux#13" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(7)} -pin  "mux#13" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} -pin  "mux#13" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(9)} -pin  "mux#13" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} -pin  "mux#13" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "mux#13" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load inst "mux#14" "mux(2,2)" "INTERFACE" -attr xrf 26058 -attr oid 1354 -attr vt d -attr @path {/sobel/sobel:core/mux#14} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {acc.imod#18.lpi#1.dfm.sg1(0)} -pin  "mux#14" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1}
+load net {acc.imod#18.lpi#1.dfm.sg1(1)} -pin  "mux#14" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1}
+load net {ACC1:acc#150.itm(2)} -pin  "mux#14" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva).itm}
+load net {ACC1:acc#150.itm(3)} -pin  "mux#14" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva).itm}
+load net {and.cse} -pin  "mux#14" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(0)} -pin  "mux#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1:mx0}
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(1)} -pin  "mux#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1:mx0}
+load inst "mux#15" "mux(2,3)" "INTERFACE" -attr xrf 26059 -attr oid 1355 -attr vt d -attr @path {/sobel/sobel:core/mux#15} -attr area 2.759269 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(3,1,2)"
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(0)} -pin  "mux#15" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(1)} -pin  "mux#15" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(2)} -pin  "mux#15" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load net {ACC1:acc#148.itm(2)} -pin  "mux#15" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.sva).itm}
+load net {ACC1:acc#148.itm(3)} -pin  "mux#15" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.sva).itm}
+load net {ACC1:acc#148.itm(4)} -pin  "mux#15" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.sva).itm}
+load net {and.cse} -pin  "mux#15" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(0)} -pin  "mux#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(1)} -pin  "mux#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(2)} -pin  "mux#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load inst "ACC1-1:not#57" "not(1)" "INTERFACE" -attr xrf 26060 -attr oid 1356 -attr @path {/sobel/sobel:core/ACC1-1:not#57} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#150.itm(2)} -pin  "ACC1-1:not#57" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva)#2.itm}
+load net {ACC1-1:not#57.itm} -pin  "ACC1-1:not#57" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#57.itm}
+load inst "ACC1-1:not#58" "not(1)" "INTERFACE" -attr xrf 26061 -attr oid 1357 -attr @path {/sobel/sobel:core/ACC1-1:not#58} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#150.itm(3)} -pin  "ACC1-1:not#58" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva)#3.itm}
+load net {ACC1-1:not#58.itm} -pin  "ACC1-1:not#58" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#58.itm}
+load inst "ACC1:acc#151" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 26062 -attr oid 1358 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#151" {A(0)} -attr @path {/sobel/sobel:core/conc#740.itm}
+load net {ACC1:acc#150.itm(1)} -pin  "ACC1:acc#151" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#740.itm}
+load net {PWR} -pin  "ACC1:acc#151" {A(2)} -attr @path {/sobel/sobel:core/conc#740.itm}
+load net {ACC1-1:not#58.itm} -pin  "ACC1:acc#151" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#477.itm}
+load net {ACC1-1:not#57.itm} -pin  "ACC1:acc#151" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#477.itm}
+load net {ACC1:acc#151.itm(0)} -pin  "ACC1:acc#151" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151.itm}
+load net {ACC1:acc#151.itm(1)} -pin  "ACC1:acc#151" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151.itm}
+load net {ACC1:acc#151.itm(2)} -pin  "ACC1:acc#151" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151.itm}
+load inst "mux#16" "mux(2,2)" "INTERFACE" -attr xrf 26063 -attr oid 1359 -attr vt d -attr @path {/sobel/sobel:core/mux#16} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {acc.imod#20.lpi#1.dfm(0)} -pin  "mux#16" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm}
+load net {acc.imod#20.lpi#1.dfm(1)} -pin  "mux#16" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm}
+load net {ACC1:acc#151.itm(1)} -pin  "mux#16" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#21.itm}
+load net {ACC1:acc#151.itm(2)} -pin  "mux#16" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#21.itm}
+load net {and.cse} -pin  "mux#16" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {acc.imod#20.lpi#1.dfm:mx0(0)} -pin  "mux#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm:mx0}
+load net {acc.imod#20.lpi#1.dfm:mx0(1)} -pin  "mux#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm:mx0}
+load inst "mux#17" "mux(2,2)" "INTERFACE" -attr xrf 26064 -attr oid 1360 -attr vt d -attr @path {/sobel/sobel:core/mux#17} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(0)} -pin  "mux#17" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(1)} -pin  "mux#17" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp#1.sva(1)} -pin  "mux#17" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp#1.sva)#2.itm}
+load net {ACC1:acc#118.psp#1.sva(2)} -pin  "mux#17" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp#1.sva)#2.itm}
+load net {and.cse} -pin  "mux#17" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(0)} -pin  "mux#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(1)} -pin  "mux#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0}
+load inst "FRAME:for:nor" "nor(2,1)" "INTERFACE" -attr xrf 26065 -attr oid 1361 -attr @path {/sobel/sobel:core/FRAME:for:nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:nor" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#3.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nor" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#4.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:nor" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load inst "FRAME:for:not#8" "not(1)" "INTERFACE" -attr xrf 26066 -attr oid 1362 -attr @path {/sobel/sobel:core/FRAME:for:not#8} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#8" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#10.itm}
+load net {FRAME:for:not#8.itm} -pin  "FRAME:for:not#8" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#8.itm}
+load inst "FRAME:for:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 26067 -attr oid 1363 -attr @path {/sobel/sobel:core/FRAME:for:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {FRAME:for:not#8.itm} -pin  "FRAME:for:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#8.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#5.itm}
+load net {FRAME:for:nand#1.itm} -pin  "FRAME:for:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#1.itm}
+load inst "FRAME:for:or#4" "or(2,1)" "INTERFACE" -attr xrf 26068 -attr oid 1364 -attr @path {/sobel/sobel:core/FRAME:for:or#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {FRAME:for:nand#1.itm} -pin  "FRAME:for:or#4" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#1.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or#4" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:or#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#4.itm}
+load inst "FRAME:for:not#5" "not(1)" "INTERFACE" -attr xrf 26069 -attr oid 1365 -attr @path {/sobel/sobel:core/FRAME:for:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#5" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#8.itm}
+load net {FRAME:for:not#5.itm} -pin  "FRAME:for:not#5" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#5.itm}
+load inst "FRAME:for:nand" "nand(2,1)" "INTERFACE" -attr xrf 26070 -attr oid 1366 -attr @path {/sobel/sobel:core/FRAME:for:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#6.itm}
+load net {FRAME:for:not#5.itm} -pin  "FRAME:for:nand" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#5.itm}
+load net {FRAME:for:nand.itm} -pin  "FRAME:for:nand" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand.itm}
+load inst "FRAME:for:not#2" "not(1)" "INTERFACE" -attr xrf 26071 -attr oid 1367 -attr @path {/sobel/sobel:core/FRAME:for:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:not#2" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#7.itm}
+load net {FRAME:for:not#2.itm} -pin  "FRAME:for:not#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#2.itm}
+load inst "FRAME:for:and#3" "and(2,1)" "INTERFACE" -attr xrf 26072 -attr oid 1368 -attr @path {/sobel/sobel:core/FRAME:for:and#3} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#9.itm}
+load net {FRAME:for:not#2.itm} -pin  "FRAME:for:and#3" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#2.itm}
+load net {FRAME:for:and#3.itm} -pin  "FRAME:for:and#3" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#3.itm}
+load inst "FRAME:for:or#3" "or(3,1)" "INTERFACE" -attr xrf 26073 -attr oid 1369 -attr @path {/sobel/sobel:core/FRAME:for:or#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,3)"
+load net {FRAME:for:nand.itm} -pin  "FRAME:for:or#3" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or#3" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:and#3.itm} -pin  "FRAME:for:or#3" {A2(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#3.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:or#3" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#3.itm}
+load inst "nor" "nor(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "nor" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {exit:FRAME#1.sva} -pin  "nor" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {and.cse} -pin  "nor" {Z(0)} -attr @path {/sobel/sobel:core/and.cse}
+### END MODULE 
+
+module new "sobel" "orig"
+load portBus {vin:rsc.z(89:0)} input 90 {vin:rsc.z(89)} {vin:rsc.z(88)} {vin:rsc.z(87)} {vin:rsc.z(86)} {vin:rsc.z(85)} {vin:rsc.z(84)} {vin:rsc.z(83)} {vin:rsc.z(82)} {vin:rsc.z(81)} {vin:rsc.z(80)} {vin:rsc.z(79)} {vin:rsc.z(78)} {vin:rsc.z(77)} {vin:rsc.z(76)} {vin:rsc.z(75)} {vin:rsc.z(74)} {vin:rsc.z(73)} {vin:rsc.z(72)} {vin:rsc.z(71)} {vin:rsc.z(70)} {vin:rsc.z(69)} {vin:rsc.z(68)} {vin:rsc.z(67)} {vin:rsc.z(66)} {vin:rsc.z(65)} {vin:rsc.z(64)} {vin:rsc.z(63)} {vin:rsc.z(62)} {vin:rsc.z(61)} {vin:rsc.z(60)} {vin:rsc.z(59)} {vin:rsc.z(58)} {vin:rsc.z(57)} {vin:rsc.z(56)} {vin:rsc.z(55)} {vin:rsc.z(54)} {vin:rsc.z(53)} {vin:rsc.z(52)} {vin:rsc.z(51)} {vin:rsc.z(50)} {vin:rsc.z(49)} {vin:rsc.z(48)} {vin:rsc.z(47)} {vin:rsc.z(46)} {vin:rsc.z(45)} {vin:rsc.z(44)} {vin:rsc.z(43)} {vin:rsc.z(42)} {vin:rsc.z(41)} {vin:rsc.z(40)} {vin:rsc.z(39)} {vin:rsc.z(38)} {vin:rsc.z(37)} {vin:rsc.z(36)} {vin:rsc.z(35)} {vin:rsc.z(34)} {vin:rsc.z(33)} {vin:rsc.z(32)} {vin:rsc.z(31)} {vin:rsc.z(30)} {vin:rsc.z(29)} {vin:rsc.z(28)} {vin:rsc.z(27)} {vin:rsc.z(26)} {vin:rsc.z(25)} {vin:rsc.z(24)} {vin:rsc.z(23)} {vin:rsc.z(22)} {vin:rsc.z(21)} {vin:rsc.z(20)} {vin:rsc.z(19)} {vin:rsc.z(18)} {vin:rsc.z(17)} {vin:rsc.z(16)} {vin:rsc.z(15)} {vin:rsc.z(14)} {vin:rsc.z(13)} {vin:rsc.z(12)} {vin:rsc.z(11)} {vin:rsc.z(10)} {vin:rsc.z(9)} {vin:rsc.z(8)} {vin:rsc.z(7)} {vin:rsc.z(6)} {vin:rsc.z(5)} {vin:rsc.z(4)} {vin:rsc.z(3)} {vin:rsc.z(2)} {vin:rsc.z(1)} {vin:rsc.z(0)} -attr xrf 26074 -attr oid 1370 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load portBus {vout:rsc.z(29:0)} output 30 {vout:rsc.z(29)} {vout:rsc.z(28)} {vout:rsc.z(27)} {vout:rsc.z(26)} {vout:rsc.z(25)} {vout:rsc.z(24)} {vout:rsc.z(23)} {vout:rsc.z(22)} {vout:rsc.z(21)} {vout:rsc.z(20)} {vout:rsc.z(19)} {vout:rsc.z(18)} {vout:rsc.z(17)} {vout:rsc.z(16)} {vout:rsc.z(15)} {vout:rsc.z(14)} {vout:rsc.z(13)} {vout:rsc.z(12)} {vout:rsc.z(11)} {vout:rsc.z(10)} {vout:rsc.z(9)} {vout:rsc.z(8)} {vout:rsc.z(7)} {vout:rsc.z(6)} {vout:rsc.z(5)} {vout:rsc.z(4)} {vout:rsc.z(3)} {vout:rsc.z(2)} {vout:rsc.z(1)} {vout:rsc.z(0)} -attr xrf 26075 -attr oid 1371 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load port {clk} input -attr xrf 26076 -attr oid 1372 -attr vt d -attr @path {/sobel/clk}
+load port {en} input -attr xrf 26077 -attr oid 1373 -attr vt d -attr @path {/sobel/en}
+load port {arst_n} input -attr xrf 26078 -attr oid 1374 -attr vt d -attr @path {/sobel/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(89:0)} output 90 {d(89)} {d(88)} {d(87)} {d(86)} {d(85)} {d(84)} {d(83)} {d(82)} {d(81)} {d(80)} {d(79)} {d(78)} {d(77)} {d(76)} {d(75)} {d(74)} {d(73)} {d(72)} {d(71)} {d(70)} {d(69)} {d(68)} {d(67)} {d(66)} {d(65)} {d(64)} {d(63)} {d(62)} {d(61)} {d(60)} {d(59)} {d(58)} {d(57)} {d(56)} {d(55)} {d(54)} {d(53)} {d(52)} {d(51)} {d(50)} {d(49)} {d(48)} {d(47)} {d(46)} {d(45)} {d(44)} {d(43)} {d(42)} {d(41)} {d(40)} {d(39)} {d(38)} {d(37)} {d(36)} {d(35)} {d(34)} {d(33)} {d(32)} {d(31)} {d(30)} {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(89:0)} input 90 {z(89)} {z(88)} {z(87)} {z(86)} {z(85)} {z(84)} {z(83)} {z(82)} {z(81)} {z(80)} {z(79)} {z(78)} {z(77)} {z(76)} {z(75)} {z(74)} {z(73)} {z(72)} {z(71)} {z(70)} {z(69)} {z(68)} {z(67)} {z(66)} {z(65)} {z(64)} {z(63)} {z(62)} {z(61)} {z(60)} {z(59)} {z(58)} {z(57)} {z(56)} {z(55)} {z(54)} {z(53)} {z(52)} {z(51)} {z(50)} {z(49)} {z(48)} {z(47)} {z(46)} {z(45)} {z(44)} {z(43)} {z(42)} {z(41)} {z(40)} {z(39)} {z(38)} {z(37)} {z(36)} {z(35)} {z(34)} {z(33)} {z(32)} {z(31)} {z(30)} {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(29:0)} input 30 {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(29:0)} output 30 {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "sobel:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} \
+     portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} \
+
+load net {vin:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d#1} 90 {vin:rsc:mgc_in_wire.d#1(0)} {vin:rsc:mgc_in_wire.d#1(1)} {vin:rsc:mgc_in_wire.d#1(2)} {vin:rsc:mgc_in_wire.d#1(3)} {vin:rsc:mgc_in_wire.d#1(4)} {vin:rsc:mgc_in_wire.d#1(5)} {vin:rsc:mgc_in_wire.d#1(6)} {vin:rsc:mgc_in_wire.d#1(7)} {vin:rsc:mgc_in_wire.d#1(8)} {vin:rsc:mgc_in_wire.d#1(9)} {vin:rsc:mgc_in_wire.d#1(10)} {vin:rsc:mgc_in_wire.d#1(11)} {vin:rsc:mgc_in_wire.d#1(12)} {vin:rsc:mgc_in_wire.d#1(13)} {vin:rsc:mgc_in_wire.d#1(14)} {vin:rsc:mgc_in_wire.d#1(15)} {vin:rsc:mgc_in_wire.d#1(16)} {vin:rsc:mgc_in_wire.d#1(17)} {vin:rsc:mgc_in_wire.d#1(18)} {vin:rsc:mgc_in_wire.d#1(19)} {vin:rsc:mgc_in_wire.d#1(20)} {vin:rsc:mgc_in_wire.d#1(21)} {vin:rsc:mgc_in_wire.d#1(22)} {vin:rsc:mgc_in_wire.d#1(23)} {vin:rsc:mgc_in_wire.d#1(24)} {vin:rsc:mgc_in_wire.d#1(25)} {vin:rsc:mgc_in_wire.d#1(26)} {vin:rsc:mgc_in_wire.d#1(27)} {vin:rsc:mgc_in_wire.d#1(28)} {vin:rsc:mgc_in_wire.d#1(29)} {vin:rsc:mgc_in_wire.d#1(30)} {vin:rsc:mgc_in_wire.d#1(31)} {vin:rsc:mgc_in_wire.d#1(32)} {vin:rsc:mgc_in_wire.d#1(33)} {vin:rsc:mgc_in_wire.d#1(34)} {vin:rsc:mgc_in_wire.d#1(35)} {vin:rsc:mgc_in_wire.d#1(36)} {vin:rsc:mgc_in_wire.d#1(37)} {vin:rsc:mgc_in_wire.d#1(38)} {vin:rsc:mgc_in_wire.d#1(39)} {vin:rsc:mgc_in_wire.d#1(40)} {vin:rsc:mgc_in_wire.d#1(41)} {vin:rsc:mgc_in_wire.d#1(42)} {vin:rsc:mgc_in_wire.d#1(43)} {vin:rsc:mgc_in_wire.d#1(44)} {vin:rsc:mgc_in_wire.d#1(45)} {vin:rsc:mgc_in_wire.d#1(46)} {vin:rsc:mgc_in_wire.d#1(47)} {vin:rsc:mgc_in_wire.d#1(48)} {vin:rsc:mgc_in_wire.d#1(49)} {vin:rsc:mgc_in_wire.d#1(50)} {vin:rsc:mgc_in_wire.d#1(51)} {vin:rsc:mgc_in_wire.d#1(52)} {vin:rsc:mgc_in_wire.d#1(53)} {vin:rsc:mgc_in_wire.d#1(54)} {vin:rsc:mgc_in_wire.d#1(55)} {vin:rsc:mgc_in_wire.d#1(56)} {vin:rsc:mgc_in_wire.d#1(57)} {vin:rsc:mgc_in_wire.d#1(58)} {vin:rsc:mgc_in_wire.d#1(59)} {vin:rsc:mgc_in_wire.d#1(60)} {vin:rsc:mgc_in_wire.d#1(61)} {vin:rsc:mgc_in_wire.d#1(62)} {vin:rsc:mgc_in_wire.d#1(63)} {vin:rsc:mgc_in_wire.d#1(64)} {vin:rsc:mgc_in_wire.d#1(65)} {vin:rsc:mgc_in_wire.d#1(66)} {vin:rsc:mgc_in_wire.d#1(67)} {vin:rsc:mgc_in_wire.d#1(68)} {vin:rsc:mgc_in_wire.d#1(69)} {vin:rsc:mgc_in_wire.d#1(70)} {vin:rsc:mgc_in_wire.d#1(71)} {vin:rsc:mgc_in_wire.d#1(72)} {vin:rsc:mgc_in_wire.d#1(73)} {vin:rsc:mgc_in_wire.d#1(74)} {vin:rsc:mgc_in_wire.d#1(75)} {vin:rsc:mgc_in_wire.d#1(76)} {vin:rsc:mgc_in_wire.d#1(77)} {vin:rsc:mgc_in_wire.d#1(78)} {vin:rsc:mgc_in_wire.d#1(79)} {vin:rsc:mgc_in_wire.d#1(80)} {vin:rsc:mgc_in_wire.d#1(81)} {vin:rsc:mgc_in_wire.d#1(82)} {vin:rsc:mgc_in_wire.d#1(83)} {vin:rsc:mgc_in_wire.d#1(84)} {vin:rsc:mgc_in_wire.d#1(85)} {vin:rsc:mgc_in_wire.d#1(86)} {vin:rsc:mgc_in_wire.d#1(87)} {vin:rsc:mgc_in_wire.d#1(88)} {vin:rsc:mgc_in_wire.d#1(89)} -attr xrf 26079 -attr oid 1375 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d#1} 30 {vout:rsc:mgc_out_stdreg.d#1(0)} {vout:rsc:mgc_out_stdreg.d#1(1)} {vout:rsc:mgc_out_stdreg.d#1(2)} {vout:rsc:mgc_out_stdreg.d#1(3)} {vout:rsc:mgc_out_stdreg.d#1(4)} {vout:rsc:mgc_out_stdreg.d#1(5)} {vout:rsc:mgc_out_stdreg.d#1(6)} {vout:rsc:mgc_out_stdreg.d#1(7)} {vout:rsc:mgc_out_stdreg.d#1(8)} {vout:rsc:mgc_out_stdreg.d#1(9)} {vout:rsc:mgc_out_stdreg.d#1(10)} {vout:rsc:mgc_out_stdreg.d#1(11)} {vout:rsc:mgc_out_stdreg.d#1(12)} {vout:rsc:mgc_out_stdreg.d#1(13)} {vout:rsc:mgc_out_stdreg.d#1(14)} {vout:rsc:mgc_out_stdreg.d#1(15)} {vout:rsc:mgc_out_stdreg.d#1(16)} {vout:rsc:mgc_out_stdreg.d#1(17)} {vout:rsc:mgc_out_stdreg.d#1(18)} {vout:rsc:mgc_out_stdreg.d#1(19)} {vout:rsc:mgc_out_stdreg.d#1(20)} {vout:rsc:mgc_out_stdreg.d#1(21)} {vout:rsc:mgc_out_stdreg.d#1(22)} {vout:rsc:mgc_out_stdreg.d#1(23)} {vout:rsc:mgc_out_stdreg.d#1(24)} {vout:rsc:mgc_out_stdreg.d#1(25)} {vout:rsc:mgc_out_stdreg.d#1(26)} {vout:rsc:mgc_out_stdreg.d#1(27)} {vout:rsc:mgc_out_stdreg.d#1(28)} {vout:rsc:mgc_out_stdreg.d#1(29)} -attr xrf 26080 -attr oid 1376 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -attr vt d
+load net {vin:rsc.z(13)} -attr vt d
+load net {vin:rsc.z(14)} -attr vt d
+load net {vin:rsc.z(15)} -attr vt d
+load net {vin:rsc.z(16)} -attr vt d
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+load net {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -attr vt d
+load net {vin:rsc.z(28)} -attr vt d
+load net {vin:rsc.z(29)} -attr vt d
+load net {vin:rsc.z(30)} -attr vt d
+load net {vin:rsc.z(31)} -attr vt d
+load net {vin:rsc.z(32)} -attr vt d
+load net {vin:rsc.z(33)} -attr vt d
+load net {vin:rsc.z(34)} -attr vt d
+load net {vin:rsc.z(35)} -attr vt d
+load net {vin:rsc.z(36)} -attr vt d
+load net {vin:rsc.z(37)} -attr vt d
+load net {vin:rsc.z(38)} -attr vt d
+load net {vin:rsc.z(39)} -attr vt d
+load net {vin:rsc.z(40)} -attr vt d
+load net {vin:rsc.z(41)} -attr vt d
+load net {vin:rsc.z(42)} -attr vt d
+load net {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -attr vt d
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+load net {vin:rsc.z(48)} -attr vt d
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+load net {vin:rsc.z(50)} -attr vt d
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+load net {vin:rsc.z(52)} -attr vt d
+load net {vin:rsc.z(53)} -attr vt d
+load net {vin:rsc.z(54)} -attr vt d
+load net {vin:rsc.z(55)} -attr vt d
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+load net {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -attr vt d
+load net {vin:rsc.z(63)} -attr vt d
+load net {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -attr vt d
+load net {vin:rsc.z(68)} -attr vt d
+load net {vin:rsc.z(69)} -attr vt d
+load net {vin:rsc.z(70)} -attr vt d
+load net {vin:rsc.z(71)} -attr vt d
+load net {vin:rsc.z(72)} -attr vt d
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+load net {vin:rsc.z(75)} -attr vt d
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+load net {vin:rsc.z(85)} -attr vt d
+load net {vin:rsc.z(86)} -attr vt d
+load net {vin:rsc.z(87)} -attr vt d
+load net {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 26081 -attr oid 1377 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(0)} -port {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -port {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -port {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -port {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -port {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -port {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -port {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -port {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -port {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -port {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -port {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -port {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -port {vin:rsc.z(12)} -attr vt d
+load net {vin:rsc.z(13)} -port {vin:rsc.z(13)} -attr vt d
+load net {vin:rsc.z(14)} -port {vin:rsc.z(14)} -attr vt d
+load net {vin:rsc.z(15)} -port {vin:rsc.z(15)} -attr vt d
+load net {vin:rsc.z(16)} -port {vin:rsc.z(16)} -attr vt d
+load net {vin:rsc.z(17)} -port {vin:rsc.z(17)} -attr vt d
+load net {vin:rsc.z(18)} -port {vin:rsc.z(18)} -attr vt d
+load net {vin:rsc.z(19)} -port {vin:rsc.z(19)} -attr vt d
+load net {vin:rsc.z(20)} -port {vin:rsc.z(20)} -attr vt d
+load net {vin:rsc.z(21)} -port {vin:rsc.z(21)} -attr vt d
+load net {vin:rsc.z(22)} -port {vin:rsc.z(22)} -attr vt d
+load net {vin:rsc.z(23)} -port {vin:rsc.z(23)} -attr vt d
+load net {vin:rsc.z(24)} -port {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -port {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -port {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -port {vin:rsc.z(27)} -attr vt d
+load net {vin:rsc.z(28)} -port {vin:rsc.z(28)} -attr vt d
+load net {vin:rsc.z(29)} -port {vin:rsc.z(29)} -attr vt d
+load net {vin:rsc.z(30)} -port {vin:rsc.z(30)} -attr vt d
+load net {vin:rsc.z(31)} -port {vin:rsc.z(31)} -attr vt d
+load net {vin:rsc.z(32)} -port {vin:rsc.z(32)} -attr vt d
+load net {vin:rsc.z(33)} -port {vin:rsc.z(33)} -attr vt d
+load net {vin:rsc.z(34)} -port {vin:rsc.z(34)} -attr vt d
+load net {vin:rsc.z(35)} -port {vin:rsc.z(35)} -attr vt d
+load net {vin:rsc.z(36)} -port {vin:rsc.z(36)} -attr vt d
+load net {vin:rsc.z(37)} -port {vin:rsc.z(37)} -attr vt d
+load net {vin:rsc.z(38)} -port {vin:rsc.z(38)} -attr vt d
+load net {vin:rsc.z(39)} -port {vin:rsc.z(39)} -attr vt d
+load net {vin:rsc.z(40)} -port {vin:rsc.z(40)} -attr vt d
+load net {vin:rsc.z(41)} -port {vin:rsc.z(41)} -attr vt d
+load net {vin:rsc.z(42)} -port {vin:rsc.z(42)} -attr vt d
+load net {vin:rsc.z(43)} -port {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -port {vin:rsc.z(44)} -attr vt d
+load net {vin:rsc.z(45)} -port {vin:rsc.z(45)} -attr vt d
+load net {vin:rsc.z(46)} -port {vin:rsc.z(46)} -attr vt d
+load net {vin:rsc.z(47)} -port {vin:rsc.z(47)} -attr vt d
+load net {vin:rsc.z(48)} -port {vin:rsc.z(48)} -attr vt d
+load net {vin:rsc.z(49)} -port {vin:rsc.z(49)} -attr vt d
+load net {vin:rsc.z(50)} -port {vin:rsc.z(50)} -attr vt d
+load net {vin:rsc.z(51)} -port {vin:rsc.z(51)} -attr vt d
+load net {vin:rsc.z(52)} -port {vin:rsc.z(52)} -attr vt d
+load net {vin:rsc.z(53)} -port {vin:rsc.z(53)} -attr vt d
+load net {vin:rsc.z(54)} -port {vin:rsc.z(54)} -attr vt d
+load net {vin:rsc.z(55)} -port {vin:rsc.z(55)} -attr vt d
+load net {vin:rsc.z(56)} -port {vin:rsc.z(56)} -attr vt d
+load net {vin:rsc.z(57)} -port {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -port {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -port {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -port {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -port {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -port {vin:rsc.z(62)} -attr vt d
+load net {vin:rsc.z(63)} -port {vin:rsc.z(63)} -attr vt d
+load net {vin:rsc.z(64)} -port {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -port {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -port {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -port {vin:rsc.z(67)} -attr vt d
+load net {vin:rsc.z(68)} -port {vin:rsc.z(68)} -attr vt d
+load net {vin:rsc.z(69)} -port {vin:rsc.z(69)} -attr vt d
+load net {vin:rsc.z(70)} -port {vin:rsc.z(70)} -attr vt d
+load net {vin:rsc.z(71)} -port {vin:rsc.z(71)} -attr vt d
+load net {vin:rsc.z(72)} -port {vin:rsc.z(72)} -attr vt d
+load net {vin:rsc.z(73)} -port {vin:rsc.z(73)} -attr vt d
+load net {vin:rsc.z(74)} -port {vin:rsc.z(74)} -attr vt d
+load net {vin:rsc.z(75)} -port {vin:rsc.z(75)} -attr vt d
+load net {vin:rsc.z(76)} -port {vin:rsc.z(76)} -attr vt d
+load net {vin:rsc.z(77)} -port {vin:rsc.z(77)} -attr vt d
+load net {vin:rsc.z(78)} -port {vin:rsc.z(78)} -attr vt d
+load net {vin:rsc.z(79)} -port {vin:rsc.z(79)} -attr vt d
+load net {vin:rsc.z(80)} -port {vin:rsc.z(80)} -attr vt d
+load net {vin:rsc.z(81)} -port {vin:rsc.z(81)} -attr vt d
+load net {vin:rsc.z(82)} -port {vin:rsc.z(82)} -attr vt d
+load net {vin:rsc.z(83)} -port {vin:rsc.z(83)} -attr vt d
+load net {vin:rsc.z(84)} -port {vin:rsc.z(84)} -attr vt d
+load net {vin:rsc.z(85)} -port {vin:rsc.z(85)} -attr vt d
+load net {vin:rsc.z(86)} -port {vin:rsc.z(86)} -attr vt d
+load net {vin:rsc.z(87)} -port {vin:rsc.z(87)} -attr vt d
+load net {vin:rsc.z(88)} -port {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -port {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 26082 -attr oid 1378 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vout:rsc.z(0)} -attr vt d
+load net {vout:rsc.z(1)} -attr vt d
+load net {vout:rsc.z(2)} -attr vt d
+load net {vout:rsc.z(3)} -attr vt d
+load net {vout:rsc.z(4)} -attr vt d
+load net {vout:rsc.z(5)} -attr vt d
+load net {vout:rsc.z(6)} -attr vt d
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+load net {vout:rsc.z(12)} -attr vt d
+load net {vout:rsc.z(13)} -attr vt d
+load net {vout:rsc.z(14)} -attr vt d
+load net {vout:rsc.z(15)} -attr vt d
+load net {vout:rsc.z(16)} -attr vt d
+load net {vout:rsc.z(17)} -attr vt d
+load net {vout:rsc.z(18)} -attr vt d
+load net {vout:rsc.z(19)} -attr vt d
+load net {vout:rsc.z(20)} -attr vt d
+load net {vout:rsc.z(21)} -attr vt d
+load net {vout:rsc.z(22)} -attr vt d
+load net {vout:rsc.z(23)} -attr vt d
+load net {vout:rsc.z(24)} -attr vt d
+load net {vout:rsc.z(25)} -attr vt d
+load net {vout:rsc.z(26)} -attr vt d
+load net {vout:rsc.z(27)} -attr vt d
+load net {vout:rsc.z(28)} -attr vt d
+load net {vout:rsc.z(29)} -attr vt d
+load netBundle {vout:rsc.z} 30 {vout:rsc.z(0)} {vout:rsc.z(1)} {vout:rsc.z(2)} {vout:rsc.z(3)} {vout:rsc.z(4)} {vout:rsc.z(5)} {vout:rsc.z(6)} {vout:rsc.z(7)} {vout:rsc.z(8)} {vout:rsc.z(9)} {vout:rsc.z(10)} {vout:rsc.z(11)} {vout:rsc.z(12)} {vout:rsc.z(13)} {vout:rsc.z(14)} {vout:rsc.z(15)} {vout:rsc.z(16)} {vout:rsc.z(17)} {vout:rsc.z(18)} {vout:rsc.z(19)} {vout:rsc.z(20)} {vout:rsc.z(21)} {vout:rsc.z(22)} {vout:rsc.z(23)} {vout:rsc.z(24)} {vout:rsc.z(25)} {vout:rsc.z(26)} {vout:rsc.z(27)} {vout:rsc.z(28)} {vout:rsc.z(29)} -attr xrf 26083 -attr oid 1379 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(0)} -port {vout:rsc.z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -port {vout:rsc.z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -port {vout:rsc.z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -port {vout:rsc.z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -port {vout:rsc.z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -port {vout:rsc.z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -port {vout:rsc.z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -port {vout:rsc.z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -port {vout:rsc.z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -port {vout:rsc.z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -port {vout:rsc.z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -port {vout:rsc.z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -port {vout:rsc.z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -port {vout:rsc.z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -port {vout:rsc.z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -port {vout:rsc.z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -port {vout:rsc.z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -port {vout:rsc.z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -port {vout:rsc.z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -port {vout:rsc.z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -port {vout:rsc.z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -port {vout:rsc.z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -port {vout:rsc.z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -port {vout:rsc.z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -port {vout:rsc.z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -port {vout:rsc.z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -port {vout:rsc.z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -port {vout:rsc.z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -port {vout:rsc.z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -port {vout:rsc.z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {clk} -attr xrf 26084 -attr oid 1380
+load net {clk} -port {clk} -attr xrf 26085 -attr oid 1381
+load net {en} -attr xrf 26086 -attr oid 1382
+load net {en} -port {en} -attr xrf 26087 -attr oid 1383
+load net {arst_n} -attr xrf 26088 -attr oid 1384
+load net {arst_n} -port {arst_n} -attr xrf 26089 -attr oid 1385
+load inst "sobel:core:inst" "sobel:core" "orig" -attr xrf 26090 -attr oid 1386 -attr vt dc -attr @path {/sobel/sobel:core:inst} -attr area 6772.495085 -attr delay 15.831847 -attr hier "/sobel/sobel:core" -pg 1 -lvl 3
+load net {clk} -pin  "sobel:core:inst" {clk#1} -attr xrf 26091 -attr oid 1387 -attr @path {/sobel/clk}
+load net {en} -pin  "sobel:core:inst" {en#1} -attr xrf 26092 -attr oid 1388 -attr @path {/sobel/en}
+load net {arst_n} -pin  "sobel:core:inst" {arst_n#1} -attr xrf 26093 -attr oid 1389 -attr @path {/sobel/arst_n}
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(8)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(9)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(10)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(11)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(12)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(13)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(14)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(15)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(16)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(17)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(18)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(19)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(20)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(21)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(22)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(23)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(24)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(25)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(26)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(27)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(28)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(29)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(30)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(31)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(32)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(33)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(34)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(35)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(36)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(37)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(38)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(39)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(40)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(41)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(42)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(43)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(44)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(45)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(46)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(47)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(48)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(49)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(50)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(51)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(52)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(53)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(54)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(55)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(56)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(57)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(58)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(59)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(60)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(61)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(62)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(63)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(64)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(65)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(66)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(67)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(68)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(69)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(70)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(71)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(72)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(73)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(74)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(75)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(76)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(77)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(78)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(79)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(80)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(81)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(82)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(83)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(84)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(85)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(86)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(87)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(88)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(89)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(8)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(9)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(10)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(11)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(12)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(13)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(14)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(15)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(16)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(17)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(18)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(19)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(20)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(21)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(22)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(23)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(24)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(25)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(26)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(27)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(28)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(29)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load inst "vin:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" -attr xrf 26094 -attr oid 1390 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,90)" -pg 1 -lvl 1
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "vin:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "vin:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "vin:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "vin:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "vin:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "vin:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "vin:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "vin:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "vin:rsc:mgc_in_wire" {d(8)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "vin:rsc:mgc_in_wire" {d(9)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "vin:rsc:mgc_in_wire" {d(10)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "vin:rsc:mgc_in_wire" {d(11)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "vin:rsc:mgc_in_wire" {d(12)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "vin:rsc:mgc_in_wire" {d(13)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "vin:rsc:mgc_in_wire" {d(14)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "vin:rsc:mgc_in_wire" {d(15)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "vin:rsc:mgc_in_wire" {d(16)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "vin:rsc:mgc_in_wire" {d(17)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "vin:rsc:mgc_in_wire" {d(18)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "vin:rsc:mgc_in_wire" {d(19)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "vin:rsc:mgc_in_wire" {d(20)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "vin:rsc:mgc_in_wire" {d(21)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "vin:rsc:mgc_in_wire" {d(22)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "vin:rsc:mgc_in_wire" {d(23)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "vin:rsc:mgc_in_wire" {d(24)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "vin:rsc:mgc_in_wire" {d(25)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "vin:rsc:mgc_in_wire" {d(26)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "vin:rsc:mgc_in_wire" {d(27)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "vin:rsc:mgc_in_wire" {d(28)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "vin:rsc:mgc_in_wire" {d(29)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "vin:rsc:mgc_in_wire" {d(30)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "vin:rsc:mgc_in_wire" {d(31)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "vin:rsc:mgc_in_wire" {d(32)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "vin:rsc:mgc_in_wire" {d(33)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "vin:rsc:mgc_in_wire" {d(34)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "vin:rsc:mgc_in_wire" {d(35)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "vin:rsc:mgc_in_wire" {d(36)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "vin:rsc:mgc_in_wire" {d(37)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "vin:rsc:mgc_in_wire" {d(38)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "vin:rsc:mgc_in_wire" {d(39)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "vin:rsc:mgc_in_wire" {d(40)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "vin:rsc:mgc_in_wire" {d(41)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "vin:rsc:mgc_in_wire" {d(42)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "vin:rsc:mgc_in_wire" {d(43)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "vin:rsc:mgc_in_wire" {d(44)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "vin:rsc:mgc_in_wire" {d(45)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "vin:rsc:mgc_in_wire" {d(46)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "vin:rsc:mgc_in_wire" {d(47)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "vin:rsc:mgc_in_wire" {d(48)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "vin:rsc:mgc_in_wire" {d(49)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "vin:rsc:mgc_in_wire" {d(50)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "vin:rsc:mgc_in_wire" {d(51)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "vin:rsc:mgc_in_wire" {d(52)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "vin:rsc:mgc_in_wire" {d(53)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "vin:rsc:mgc_in_wire" {d(54)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "vin:rsc:mgc_in_wire" {d(55)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "vin:rsc:mgc_in_wire" {d(56)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "vin:rsc:mgc_in_wire" {d(57)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "vin:rsc:mgc_in_wire" {d(58)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "vin:rsc:mgc_in_wire" {d(59)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "vin:rsc:mgc_in_wire" {d(60)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "vin:rsc:mgc_in_wire" {d(61)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "vin:rsc:mgc_in_wire" {d(62)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "vin:rsc:mgc_in_wire" {d(63)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "vin:rsc:mgc_in_wire" {d(64)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "vin:rsc:mgc_in_wire" {d(65)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "vin:rsc:mgc_in_wire" {d(66)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "vin:rsc:mgc_in_wire" {d(67)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "vin:rsc:mgc_in_wire" {d(68)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "vin:rsc:mgc_in_wire" {d(69)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "vin:rsc:mgc_in_wire" {d(70)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "vin:rsc:mgc_in_wire" {d(71)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "vin:rsc:mgc_in_wire" {d(72)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "vin:rsc:mgc_in_wire" {d(73)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "vin:rsc:mgc_in_wire" {d(74)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "vin:rsc:mgc_in_wire" {d(75)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "vin:rsc:mgc_in_wire" {d(76)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "vin:rsc:mgc_in_wire" {d(77)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "vin:rsc:mgc_in_wire" {d(78)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "vin:rsc:mgc_in_wire" {d(79)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "vin:rsc:mgc_in_wire" {d(80)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "vin:rsc:mgc_in_wire" {d(81)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "vin:rsc:mgc_in_wire" {d(82)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "vin:rsc:mgc_in_wire" {d(83)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "vin:rsc:mgc_in_wire" {d(84)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "vin:rsc:mgc_in_wire" {d(85)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "vin:rsc:mgc_in_wire" {d(86)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "vin:rsc:mgc_in_wire" {d(87)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "vin:rsc:mgc_in_wire" {d(88)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "vin:rsc:mgc_in_wire" {d(89)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc.z(0)} -pin  "vin:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(1)} -pin  "vin:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(2)} -pin  "vin:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(3)} -pin  "vin:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(4)} -pin  "vin:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(5)} -pin  "vin:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(6)} -pin  "vin:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(7)} -pin  "vin:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(8)} -pin  "vin:rsc:mgc_in_wire" {z(8)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(9)} -pin  "vin:rsc:mgc_in_wire" {z(9)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(10)} -pin  "vin:rsc:mgc_in_wire" {z(10)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(11)} -pin  "vin:rsc:mgc_in_wire" {z(11)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(12)} -pin  "vin:rsc:mgc_in_wire" {z(12)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(13)} -pin  "vin:rsc:mgc_in_wire" {z(13)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(14)} -pin  "vin:rsc:mgc_in_wire" {z(14)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(15)} -pin  "vin:rsc:mgc_in_wire" {z(15)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(16)} -pin  "vin:rsc:mgc_in_wire" {z(16)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(17)} -pin  "vin:rsc:mgc_in_wire" {z(17)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(18)} -pin  "vin:rsc:mgc_in_wire" {z(18)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(19)} -pin  "vin:rsc:mgc_in_wire" {z(19)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(20)} -pin  "vin:rsc:mgc_in_wire" {z(20)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(21)} -pin  "vin:rsc:mgc_in_wire" {z(21)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(22)} -pin  "vin:rsc:mgc_in_wire" {z(22)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(23)} -pin  "vin:rsc:mgc_in_wire" {z(23)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(24)} -pin  "vin:rsc:mgc_in_wire" {z(24)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(25)} -pin  "vin:rsc:mgc_in_wire" {z(25)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(26)} -pin  "vin:rsc:mgc_in_wire" {z(26)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(27)} -pin  "vin:rsc:mgc_in_wire" {z(27)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(28)} -pin  "vin:rsc:mgc_in_wire" {z(28)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(29)} -pin  "vin:rsc:mgc_in_wire" {z(29)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(30)} -pin  "vin:rsc:mgc_in_wire" {z(30)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(31)} -pin  "vin:rsc:mgc_in_wire" {z(31)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(32)} -pin  "vin:rsc:mgc_in_wire" {z(32)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(33)} -pin  "vin:rsc:mgc_in_wire" {z(33)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(34)} -pin  "vin:rsc:mgc_in_wire" {z(34)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(35)} -pin  "vin:rsc:mgc_in_wire" {z(35)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(36)} -pin  "vin:rsc:mgc_in_wire" {z(36)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(37)} -pin  "vin:rsc:mgc_in_wire" {z(37)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(38)} -pin  "vin:rsc:mgc_in_wire" {z(38)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(39)} -pin  "vin:rsc:mgc_in_wire" {z(39)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(40)} -pin  "vin:rsc:mgc_in_wire" {z(40)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(41)} -pin  "vin:rsc:mgc_in_wire" {z(41)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(42)} -pin  "vin:rsc:mgc_in_wire" {z(42)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(43)} -pin  "vin:rsc:mgc_in_wire" {z(43)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(44)} -pin  "vin:rsc:mgc_in_wire" {z(44)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(45)} -pin  "vin:rsc:mgc_in_wire" {z(45)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(46)} -pin  "vin:rsc:mgc_in_wire" {z(46)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(47)} -pin  "vin:rsc:mgc_in_wire" {z(47)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(48)} -pin  "vin:rsc:mgc_in_wire" {z(48)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(49)} -pin  "vin:rsc:mgc_in_wire" {z(49)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(50)} -pin  "vin:rsc:mgc_in_wire" {z(50)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(51)} -pin  "vin:rsc:mgc_in_wire" {z(51)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(52)} -pin  "vin:rsc:mgc_in_wire" {z(52)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(53)} -pin  "vin:rsc:mgc_in_wire" {z(53)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(54)} -pin  "vin:rsc:mgc_in_wire" {z(54)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(55)} -pin  "vin:rsc:mgc_in_wire" {z(55)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(56)} -pin  "vin:rsc:mgc_in_wire" {z(56)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(57)} -pin  "vin:rsc:mgc_in_wire" {z(57)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(58)} -pin  "vin:rsc:mgc_in_wire" {z(58)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(59)} -pin  "vin:rsc:mgc_in_wire" {z(59)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(60)} -pin  "vin:rsc:mgc_in_wire" {z(60)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(61)} -pin  "vin:rsc:mgc_in_wire" {z(61)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(62)} -pin  "vin:rsc:mgc_in_wire" {z(62)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(63)} -pin  "vin:rsc:mgc_in_wire" {z(63)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(64)} -pin  "vin:rsc:mgc_in_wire" {z(64)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(65)} -pin  "vin:rsc:mgc_in_wire" {z(65)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(66)} -pin  "vin:rsc:mgc_in_wire" {z(66)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(67)} -pin  "vin:rsc:mgc_in_wire" {z(67)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(68)} -pin  "vin:rsc:mgc_in_wire" {z(68)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(69)} -pin  "vin:rsc:mgc_in_wire" {z(69)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(70)} -pin  "vin:rsc:mgc_in_wire" {z(70)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(71)} -pin  "vin:rsc:mgc_in_wire" {z(71)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(72)} -pin  "vin:rsc:mgc_in_wire" {z(72)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(73)} -pin  "vin:rsc:mgc_in_wire" {z(73)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(74)} -pin  "vin:rsc:mgc_in_wire" {z(74)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(75)} -pin  "vin:rsc:mgc_in_wire" {z(75)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(76)} -pin  "vin:rsc:mgc_in_wire" {z(76)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(77)} -pin  "vin:rsc:mgc_in_wire" {z(77)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(78)} -pin  "vin:rsc:mgc_in_wire" {z(78)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(79)} -pin  "vin:rsc:mgc_in_wire" {z(79)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(80)} -pin  "vin:rsc:mgc_in_wire" {z(80)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(81)} -pin  "vin:rsc:mgc_in_wire" {z(81)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(82)} -pin  "vin:rsc:mgc_in_wire" {z(82)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(83)} -pin  "vin:rsc:mgc_in_wire" {z(83)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(84)} -pin  "vin:rsc:mgc_in_wire" {z(84)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(85)} -pin  "vin:rsc:mgc_in_wire" {z(85)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(86)} -pin  "vin:rsc:mgc_in_wire" {z(86)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(87)} -pin  "vin:rsc:mgc_in_wire" {z(87)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(88)} -pin  "vin:rsc:mgc_in_wire" {z(88)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(89)} -pin  "vin:rsc:mgc_in_wire" {z(89)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load inst "vout:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" -attr xrf 26095 -attr oid 1391 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(2,30)" -pg 1 -lvl 1002
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "vout:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "vout:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "vout:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "vout:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "vout:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "vout:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "vout:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "vout:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "vout:rsc:mgc_out_stdreg" {d(8)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "vout:rsc:mgc_out_stdreg" {d(9)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "vout:rsc:mgc_out_stdreg" {d(10)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "vout:rsc:mgc_out_stdreg" {d(11)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "vout:rsc:mgc_out_stdreg" {d(12)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "vout:rsc:mgc_out_stdreg" {d(13)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "vout:rsc:mgc_out_stdreg" {d(14)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "vout:rsc:mgc_out_stdreg" {d(15)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "vout:rsc:mgc_out_stdreg" {d(16)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "vout:rsc:mgc_out_stdreg" {d(17)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "vout:rsc:mgc_out_stdreg" {d(18)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "vout:rsc:mgc_out_stdreg" {d(19)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "vout:rsc:mgc_out_stdreg" {d(20)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "vout:rsc:mgc_out_stdreg" {d(21)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "vout:rsc:mgc_out_stdreg" {d(22)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "vout:rsc:mgc_out_stdreg" {d(23)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "vout:rsc:mgc_out_stdreg" {d(24)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "vout:rsc:mgc_out_stdreg" {d(25)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "vout:rsc:mgc_out_stdreg" {d(26)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "vout:rsc:mgc_out_stdreg" {d(27)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "vout:rsc:mgc_out_stdreg" {d(28)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "vout:rsc:mgc_out_stdreg" {d(29)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc.z(0)} -pin  "vout:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -pin  "vout:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -pin  "vout:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -pin  "vout:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -pin  "vout:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -pin  "vout:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -pin  "vout:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -pin  "vout:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -pin  "vout:rsc:mgc_out_stdreg" {z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -pin  "vout:rsc:mgc_out_stdreg" {z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -pin  "vout:rsc:mgc_out_stdreg" {z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -pin  "vout:rsc:mgc_out_stdreg" {z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -pin  "vout:rsc:mgc_out_stdreg" {z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -pin  "vout:rsc:mgc_out_stdreg" {z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -pin  "vout:rsc:mgc_out_stdreg" {z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -pin  "vout:rsc:mgc_out_stdreg" {z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -pin  "vout:rsc:mgc_out_stdreg" {z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -pin  "vout:rsc:mgc_out_stdreg" {z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -pin  "vout:rsc:mgc_out_stdreg" {z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -pin  "vout:rsc:mgc_out_stdreg" {z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -pin  "vout:rsc:mgc_out_stdreg" {z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -pin  "vout:rsc:mgc_out_stdreg" {z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -pin  "vout:rsc:mgc_out_stdreg" {z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -pin  "vout:rsc:mgc_out_stdreg" {z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -pin  "vout:rsc:mgc_out_stdreg" {z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -pin  "vout:rsc:mgc_out_stdreg" {z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -pin  "vout:rsc:mgc_out_stdreg" {z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -pin  "vout:rsc:mgc_out_stdreg" {z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -pin  "vout:rsc:mgc_out_stdreg" {z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -pin  "vout:rsc:mgc_out_stdreg" {z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+### END MODULE 
+
diff --git a/Sobel/sobel.v8/concat_rtl.v b/Sobel/sobel.v8/concat_rtl.v
new file mode 100644
index 0000000..0147932
--- /dev/null
+++ b/Sobel/sobel.v8/concat_rtl.v
@@ -0,0 +1,2805 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 15:23:08 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [1:0] acc_imod_7_lpi_1_dfm;
+  reg [11:0] ACC1_acc_125_psp_lpi_1_dfm;
+  reg [1:0] acc_imod_20_lpi_1_dfm;
+  reg [11:0] ACC1_acc_125_psp_1_lpi_1_dfm;
+  reg [15:0] in_0_sva_1;
+  reg [15:0] in_2_sva_1;
+  reg [1:0] i_6_sva_1;
+  reg exit_FRAME_lpi_1_dfm_1;
+  reg exit_FRAME_for_lpi_1_dfm_3;
+  reg [12:0] FRAME_for_acc_24_itm_1;
+  wire [14:0] nl_FRAME_for_acc_24_itm_1;
+  reg [11:0] FRAME_for_slc_in_0_sva_itm_1;
+  wire [14:0] nl_FRAME_for_slc_in_0_sva_itm_1;
+  reg [11:0] FRAME_for_acc_26_itm_1;
+  wire [13:0] nl_FRAME_for_acc_26_itm_1;
+  reg [11:0] FRAME_for_slc_in_2_sva_itm_1;
+  wire [14:0] nl_FRAME_for_slc_in_2_sva_itm_1;
+  reg [12:0] ACC1_acc_341_itm_1;
+  wire [14:0] nl_ACC1_acc_341_itm_1;
+  reg exit_FRAME_for_sva_1_st_1;
+  reg main_stage_0_2;
+  reg [1:0] acc_imod_6_lpi_1_dfm_sg1;
+  reg [29:0] regs_regs_2_lpi_1_dfm_sg2;
+  reg [29:0] regs_regs_2_lpi_1_dfm_1;
+  reg [1:0] ACC1_acc_118_psp_lpi_1_dfm_sg1;
+  reg [2:0] ACC1_acc_110_psp_1_lpi_1_dfm_sg1;
+  reg [1:0] acc_imod_18_lpi_1_dfm_sg1;
+  reg [1:0] ACC1_acc_118_psp_1_lpi_1_dfm_sg1;
+  reg [2:0] ACC1_acc_110_psp_2_lpi_1_dfm_sg1;
+  wire and_cse;
+  wire exit_FRAME_for_lpi_1_dfm_4;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+  wire [11:0] FRAME_acc_2_psp_sva;
+  wire [13:0] nl_FRAME_acc_2_psp_sva;
+  wire [5:0] acc_imod_12_sva;
+  wire [7:0] nl_acc_imod_12_sva;
+  wire [15:0] in_2_sva_3;
+  wire [16:0] nl_in_2_sva_3;
+  wire [15:0] in_0_sva_3;
+  wire [16:0] nl_in_0_sva_3;
+  wire [1:0] i_6_sva_2;
+  wire [2:0] nl_i_6_sva_2;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire [2:0] ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0;
+  wire [11:0] ACC1_acc_125_psp_lpi_1_dfm_mx0;
+  wire [1:0] ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0;
+  wire [29:0] regs_regs_2_lpi_1_dfm_sg2_mx0;
+  wire [29:0] regs_regs_2_lpi_1_dfm_1_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire [1:0] acc_imod_7_lpi_1_dfm_mx0;
+  wire [1:0] acc_imod_6_lpi_1_dfm_sg1_mx0;
+  wire [2:0] ACC1_acc_118_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_118_psp_1_sva;
+  wire [11:0] ACC1_acc_125_psp_1_sva;
+  wire [12:0] nl_ACC1_acc_125_psp_1_sva;
+  wire [11:0] ACC1_acc_125_psp_sva;
+  wire [12:0] nl_ACC1_acc_125_psp_sva;
+  wire [2:0] ACC1_acc_118_psp_sva;
+  wire [3:0] nl_ACC1_acc_118_psp_sva;
+  wire [11:0] acc_10_psp_1_sva;
+  wire [12:0] nl_acc_10_psp_1_sva;
+  wire [3:0] ACC1_acc_113_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_113_psp_1_sva;
+  wire [2:0] ACC1_acc_120_psp_sva;
+  wire [3:0] nl_ACC1_acc_120_psp_sva;
+  wire [2:0] ACC1_acc_250_cse;
+  wire [3:0] nl_ACC1_acc_250_cse;
+  wire [11:0] acc_10_psp_2_sva;
+  wire [12:0] nl_acc_10_psp_2_sva;
+  wire [3:0] ACC1_acc_113_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_113_psp_2_sva;
+  wire [2:0] ACC1_acc_120_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_120_psp_1_sva;
+  wire [2:0] ACC1_acc_277_cse;
+  wire [3:0] nl_ACC1_acc_277_cse;
+  wire [11:0] acc_psp_1_sva;
+  wire [12:0] nl_acc_psp_1_sva;
+  wire [3:0] ACC1_acc_107_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_107_psp_1_sva;
+  wire [2:0] ACC1_acc_116_psp_sva;
+  wire [3:0] nl_ACC1_acc_116_psp_sva;
+  wire [2:0] ACC1_acc_197_cse;
+  wire [3:0] nl_ACC1_acc_197_cse;
+  wire [11:0] acc_psp_2_sva;
+  wire [12:0] nl_acc_psp_2_sva;
+  wire [3:0] ACC1_acc_107_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_107_psp_2_sva;
+  wire [2:0] ACC1_acc_116_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_116_psp_1_sva;
+  wire [2:0] ACC1_acc_224_cse;
+  wire [3:0] nl_ACC1_acc_224_cse;
+  wire exit_FRAME_lpi_1_dfm_1_mx0;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [11:0] ACC1_acc_125_psp_1_lpi_1_dfm_mx0;
+  wire [1:0] acc_imod_18_lpi_1_dfm_sg1_mx0;
+  wire [2:0] ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0;
+  wire [1:0] acc_imod_20_lpi_1_dfm_mx0;
+  wire [1:0] ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0;
+  wire FRAME_for_nor_cse;
+  wire [15:0] ACC1_acc_itm;
+  wire [17:0] nl_ACC1_acc_itm;
+  wire [3:0] ACC1_acc_150_itm;
+  wire [4:0] nl_ACC1_acc_150_itm;
+  wire [4:0] ACC1_acc_148_itm;
+  wire [5:0] nl_ACC1_acc_148_itm;
+  wire [4:0] ACC1_acc_176_itm;
+  wire [5:0] nl_ACC1_acc_176_itm;
+  wire [3:0] ACC1_acc_178_itm;
+  wire [4:0] nl_ACC1_acc_178_itm;
+  wire [2:0] ACC1_acc_188_itm;
+  wire [3:0] nl_ACC1_acc_188_itm;
+  wire [2:0] ACC1_acc_161_itm;
+  wire [3:0] nl_ACC1_acc_161_itm;
+  wire [3:0] ACC1_acc_160_itm;
+  wire [4:0] nl_ACC1_acc_160_itm;
+  wire [3:0] ACC1_acc_187_itm;
+  wire [4:0] nl_ACC1_acc_187_itm;
+  wire [2:0] ACC1_acc_170_itm;
+  wire [3:0] nl_ACC1_acc_170_itm;
+  wire [2:0] ACC1_acc_141_itm;
+  wire [3:0] nl_ACC1_acc_141_itm;
+  wire [3:0] ACC1_acc_140_itm;
+  wire [4:0] nl_ACC1_acc_140_itm;
+  wire [3:0] ACC1_acc_169_itm;
+  wire [4:0] nl_ACC1_acc_169_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_3_itm;
+
+  wire[15:0] FRAME_for_mux_12_nl;
+  wire[15:0] FRAME_for_mux_11_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_2_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(ACC1_acc_itm[14:13])
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_itm[12:10])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_itm[9:4]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_12_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_12_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_12_sva[5:3])) , (~ (acc_imod_12_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_12_sva[4:3])) + conv_u2u_3_5(~ (ACC1_acc_itm[9:7])))
+      + ({4'b1001 , (acc_imod_12_sva[5])}))))) + conv_u2u_11_12(signext_11_9({(ACC1_acc_itm[15])
+      , 3'b0 , (signext_3_1(ACC1_acc_itm[15])) , 1'b0 , (ACC1_acc_itm[15])}));
+  assign FRAME_acc_2_psp_sva = nl_FRAME_acc_2_psp_sva[11:0];
+  assign nl_ACC1_acc_itm = (in_2_sva_3 + conv_s2s_13_16(ACC1_acc_341_itm_1)) + in_0_sva_3;
+  assign ACC1_acc_itm = nl_ACC1_acc_itm[15:0];
+  assign nl_acc_imod_12_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~ (ACC1_acc_itm[15]))
+      , 1'b1 , (~ (ACC1_acc_itm[15]))}) + conv_u2u_2_4(ACC1_acc_itm[14:13]))) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_itm[3:1])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[6:4])))) + 6'b101011;
+  assign acc_imod_12_sva = nl_acc_imod_12_sva[5:0];
+  assign FRAME_for_mux_12_nl = MUX_v_16_2_2({in_2_sva_1 , ({{4{FRAME_for_slc_in_2_sva_itm_1[11]}},
+      FRAME_for_slc_in_2_sva_itm_1})}, exit_FRAME_for_lpi_1_dfm_3);
+  assign nl_in_2_sva_3 = conv_s2u_12_16(FRAME_for_acc_26_itm_1) + (FRAME_for_mux_12_nl);
+  assign in_2_sva_3 = nl_in_2_sva_3[15:0];
+  assign FRAME_for_mux_11_nl = MUX_v_16_2_2({in_0_sva_1 , ({{4{FRAME_for_slc_in_0_sva_itm_1[11]}},
+      FRAME_for_slc_in_0_sva_itm_1})}, exit_FRAME_for_lpi_1_dfm_3);
+  assign nl_in_0_sva_3 = conv_s2u_13_16(FRAME_for_acc_24_itm_1) + (FRAME_for_mux_11_nl);
+  assign in_0_sva_3 = nl_in_0_sva_3[15:0];
+  assign nl_FRAME_for_acc_itm = i_6_sva_2 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  assign exit_FRAME_for_lpi_1_dfm_4 = exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva;
+  assign nl_i_6_sva_2 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_2 = nl_i_6_sva_2[1:0];
+  assign i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm_4));
+  assign ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0 = MUX_v_3_2_2({(ACC1_acc_176_itm[4:2])
+      , ACC1_acc_110_psp_1_lpi_1_dfm_sg1}, and_cse);
+  assign ACC1_acc_125_psp_lpi_1_dfm_mx0 = MUX_v_12_2_2({ACC1_acc_125_psp_sva , ACC1_acc_125_psp_lpi_1_dfm},
+      and_cse);
+  assign ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_118_psp_sva[2:1])
+      , ACC1_acc_118_psp_lpi_1_dfm_sg1}, and_cse);
+  assign regs_regs_2_lpi_1_dfm_sg2_mx0 = MUX_v_30_2_2({(regs_regs_1_sva[89:60]) ,
+      regs_regs_2_lpi_1_dfm_sg2}, and_cse);
+  assign regs_regs_2_lpi_1_dfm_1_mx0 = MUX_v_30_2_2({(regs_regs_1_sva[29:0]) , regs_regs_2_lpi_1_dfm_1},
+      and_cse);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_cse);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_cse);
+  assign acc_imod_7_lpi_1_dfm_mx0 = MUX_v_2_2_2({(readslicef_3_2_1((({1'b1 , (ACC1_acc_178_itm[1])
+      , 1'b1}) + conv_u2s_2_3({(~ (ACC1_acc_178_itm[2])) , (~ (ACC1_acc_178_itm[3]))}))))
+      , acc_imod_7_lpi_1_dfm}, and_cse);
+  assign acc_imod_6_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_178_itm[3:2]) , acc_imod_6_lpi_1_dfm_sg1},
+      and_cse);
+  assign nl_ACC1_acc_150_itm = conv_s2s_3_4({(~ (ACC1_acc_118_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_118_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_150_itm = nl_ACC1_acc_150_itm[3:0];
+  assign nl_ACC1_acc_118_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_148_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_148_itm[2])) , (ACC1_acc_148_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_148_itm[4]));
+  assign ACC1_acc_118_psp_1_sva = nl_ACC1_acc_118_psp_1_sva[2:0];
+  assign nl_ACC1_acc_148_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_125_psp_1_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_1_sva[2])) , (~ (ACC1_acc_125_psp_1_sva[6]))}))))
+      , (~ (ACC1_acc_125_psp_1_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_1_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_1_sva[4])) , (ACC1_acc_125_psp_1_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_125_psp_1_sva[11:10])) , (ACC1_acc_125_psp_1_sva[7])}))))
+      , (ACC1_acc_125_psp_1_sva[9])});
+  assign ACC1_acc_148_itm = nl_ACC1_acc_148_itm[4:0];
+  assign nl_ACC1_acc_125_psp_1_sva = conv_s2u_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[39:30]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[49:40]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[59:50])) + 11'b11);
+  assign ACC1_acc_125_psp_1_sva = nl_ACC1_acc_125_psp_1_sva[11:0];
+  assign nl_ACC1_acc_176_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_125_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_sva[2])) , (~ (ACC1_acc_125_psp_sva[6]))}))))
+      , (~ (ACC1_acc_125_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_sva[4])) , (ACC1_acc_125_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_125_psp_sva[11:10])) , (ACC1_acc_125_psp_sva[7])}))))
+      , (ACC1_acc_125_psp_sva[9])});
+  assign ACC1_acc_176_itm = nl_ACC1_acc_176_itm[4:0];
+  assign nl_ACC1_acc_125_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_1_sva[49:40])
+      + conv_s2s_10_11(regs_regs_1_sva[39:30])) + conv_s2u_10_12(regs_regs_1_sva[59:50]);
+  assign ACC1_acc_125_psp_sva = nl_ACC1_acc_125_psp_sva[11:0];
+  assign nl_ACC1_acc_118_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_176_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_176_itm[2])) , (ACC1_acc_176_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_176_itm[4]));
+  assign ACC1_acc_118_psp_sva = nl_ACC1_acc_118_psp_sva[2:0];
+  assign nl_ACC1_acc_178_itm = conv_s2s_3_4({(~ (ACC1_acc_118_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_118_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_178_itm = nl_ACC1_acc_178_itm[3:0];
+  assign nl_acc_10_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_1_sva[79:70])
+      + conv_s2s_10_11(regs_regs_1_sva[69:60])) + conv_s2s_10_12(regs_regs_1_sva[89:80]);
+  assign acc_10_psp_1_sva = nl_acc_10_psp_1_sva[11:0];
+  assign nl_ACC1_acc_113_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_10_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_10_psp_1_sva[1]))
+      , (acc_10_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_10_psp_1_sva[0])
+      , (acc_10_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_1_sva[3])) , (~ (acc_10_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_1_sva[5])) , (acc_10_psp_1_sva[6])}))))
+      , (~ (acc_10_psp_1_sva[9]))}))));
+  assign ACC1_acc_113_psp_1_sva = nl_ACC1_acc_113_psp_1_sva[3:0];
+  assign nl_ACC1_acc_120_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_113_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_113_psp_1_sva[1])) , (ACC1_acc_113_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_113_psp_1_sva[3]));
+  assign ACC1_acc_120_psp_sva = nl_ACC1_acc_120_psp_sva[2:0];
+  assign nl_ACC1_acc_250_cse = conv_u2u_2_3(signext_2_1(acc_10_psp_1_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_10_psp_1_sva[11]));
+  assign ACC1_acc_250_cse = nl_ACC1_acc_250_cse[2:0];
+  assign nl_ACC1_acc_188_itm = ({1'b1 , (ACC1_acc_187_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_187_itm[2])) , (~ (ACC1_acc_187_itm[3]))});
+  assign ACC1_acc_188_itm = nl_ACC1_acc_188_itm[2:0];
+  assign nl_acc_10_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[69:60]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[79:70]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[89:80])) + 11'b11);
+  assign acc_10_psp_2_sva = nl_acc_10_psp_2_sva[11:0];
+  assign nl_ACC1_acc_161_itm = ({1'b1 , (ACC1_acc_160_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_160_itm[2])) , (~ (ACC1_acc_160_itm[3]))});
+  assign ACC1_acc_161_itm = nl_ACC1_acc_161_itm[2:0];
+  assign nl_ACC1_acc_160_itm = conv_s2s_3_4({(~ (ACC1_acc_120_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_120_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_160_itm = nl_ACC1_acc_160_itm[3:0];
+  assign nl_ACC1_acc_113_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_10_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_10_psp_2_sva[1]))
+      , (acc_10_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_10_psp_2_sva[0])
+      , (acc_10_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_2_sva[3])) , (~ (acc_10_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_2_sva[5])) , (acc_10_psp_2_sva[6])}))))
+      , (~ (acc_10_psp_2_sva[9]))}))));
+  assign ACC1_acc_113_psp_2_sva = nl_ACC1_acc_113_psp_2_sva[3:0];
+  assign nl_ACC1_acc_120_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_113_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_113_psp_2_sva[1])) , (ACC1_acc_113_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_113_psp_2_sva[3]));
+  assign ACC1_acc_120_psp_1_sva = nl_ACC1_acc_120_psp_1_sva[2:0];
+  assign nl_ACC1_acc_277_cse = conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11]));
+  assign ACC1_acc_277_cse = nl_ACC1_acc_277_cse[2:0];
+  assign nl_ACC1_acc_187_itm = conv_s2s_3_4({(~ (ACC1_acc_120_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_120_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_187_itm = nl_ACC1_acc_187_itm[3:0];
+  assign nl_acc_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_1_sva[19:10])
+      + conv_s2s_10_11(regs_regs_1_sva[9:0])) + conv_s2s_10_12(regs_regs_1_sva[29:20]);
+  assign acc_psp_1_sva = nl_acc_psp_1_sva[11:0];
+  assign nl_ACC1_acc_107_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_1_sva[1])) , (acc_psp_1_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_1_sva[0]) , (acc_psp_1_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[3])) , (~ (acc_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[5])) , (acc_psp_1_sva[6])})))) ,
+      (~ (acc_psp_1_sva[9]))}))));
+  assign ACC1_acc_107_psp_1_sva = nl_ACC1_acc_107_psp_1_sva[3:0];
+  assign nl_ACC1_acc_116_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_107_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_107_psp_1_sva[1])) , (ACC1_acc_107_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_107_psp_1_sva[3]));
+  assign ACC1_acc_116_psp_sva = nl_ACC1_acc_116_psp_sva[2:0];
+  assign nl_ACC1_acc_197_cse = conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]));
+  assign ACC1_acc_197_cse = nl_ACC1_acc_197_cse[2:0];
+  assign nl_ACC1_acc_170_itm = ({1'b1 , (ACC1_acc_169_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_169_itm[2])) , (~ (ACC1_acc_169_itm[3]))});
+  assign ACC1_acc_170_itm = nl_ACC1_acc_170_itm[2:0];
+  assign nl_acc_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[9:0]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[19:10]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[29:20])) + 11'b11);
+  assign acc_psp_2_sva = nl_acc_psp_2_sva[11:0];
+  assign nl_ACC1_acc_141_itm = ({1'b1 , (ACC1_acc_140_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_140_itm[2])) , (~ (ACC1_acc_140_itm[3]))});
+  assign ACC1_acc_141_itm = nl_ACC1_acc_141_itm[2:0];
+  assign nl_ACC1_acc_140_itm = conv_s2s_3_4({(~ (ACC1_acc_116_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_116_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_140_itm = nl_ACC1_acc_140_itm[3:0];
+  assign nl_ACC1_acc_107_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_2_sva[1])) , (acc_psp_2_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_2_sva[0]) , (acc_psp_2_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[3])) , (~ (acc_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[5])) , (acc_psp_2_sva[6])})))) ,
+      (~ (acc_psp_2_sva[9]))}))));
+  assign ACC1_acc_107_psp_2_sva = nl_ACC1_acc_107_psp_2_sva[3:0];
+  assign nl_ACC1_acc_116_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_107_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_107_psp_2_sva[1])) , (ACC1_acc_107_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_107_psp_2_sva[3]));
+  assign ACC1_acc_116_psp_1_sva = nl_ACC1_acc_116_psp_1_sva[2:0];
+  assign nl_ACC1_acc_224_cse = conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11]));
+  assign ACC1_acc_224_cse = nl_ACC1_acc_224_cse[2:0];
+  assign nl_ACC1_acc_169_itm = conv_s2s_3_4({(~ (ACC1_acc_116_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_116_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_169_itm = nl_ACC1_acc_169_itm[3:0];
+  assign exit_FRAME_lpi_1_dfm_1_mx0 = MUX_s_1_2_2({(~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+      + 8'b10110101)))) , (exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm_4))},
+      FRAME_for_acc_itm[1]);
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign ACC1_acc_125_psp_1_lpi_1_dfm_mx0 = MUX_v_12_2_2({ACC1_acc_125_psp_1_sva
+      , ACC1_acc_125_psp_1_lpi_1_dfm}, and_cse);
+  assign acc_imod_18_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_150_itm[3:2]) , acc_imod_18_lpi_1_dfm_sg1},
+      and_cse);
+  assign ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0 = MUX_v_3_2_2({(ACC1_acc_148_itm[4:2])
+      , ACC1_acc_110_psp_2_lpi_1_dfm_sg1}, and_cse);
+  assign acc_imod_20_lpi_1_dfm_mx0 = MUX_v_2_2_2({(readslicef_3_2_1((({1'b1 , (ACC1_acc_150_itm[1])
+      , 1'b1}) + conv_u2s_2_3({(~ (ACC1_acc_150_itm[2])) , (~ (ACC1_acc_150_itm[3]))}))))
+      , acc_imod_20_lpi_1_dfm}, and_cse);
+  assign ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_118_psp_1_sva[2:1])
+      , ACC1_acc_118_psp_1_lpi_1_dfm_sg1}, and_cse);
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_3_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) |
+      FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+  assign and_cse = ~(exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva);
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      in_2_sva_1 <= 16'b0;
+      ACC1_acc_341_itm_1 <= 13'b0;
+      in_0_sva_1 <= 16'b0;
+      exit_FRAME_for_sva_1_st_1 <= 1'b0;
+      FRAME_for_acc_26_itm_1 <= 12'b0;
+      FRAME_for_slc_in_2_sva_itm_1 <= 12'b0;
+      exit_FRAME_for_lpi_1_dfm_3 <= 1'b0;
+      FRAME_for_acc_24_itm_1 <= 13'b0;
+      FRAME_for_slc_in_0_sva_itm_1 <= 12'b0;
+      i_6_sva_1 <= 2'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      ACC1_acc_110_psp_1_lpi_1_dfm_sg1 <= 3'b0;
+      ACC1_acc_125_psp_lpi_1_dfm <= 12'b0;
+      ACC1_acc_118_psp_lpi_1_dfm_sg1 <= 2'b0;
+      regs_regs_2_lpi_1_dfm_sg2 <= 30'b0;
+      regs_regs_2_lpi_1_dfm_1 <= 30'b0;
+      acc_imod_7_lpi_1_dfm <= 2'b0;
+      acc_imod_6_lpi_1_dfm_sg1 <= 2'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_1 <= 1'b0;
+      ACC1_acc_125_psp_1_lpi_1_dfm <= 12'b0;
+      acc_imod_18_lpi_1_dfm_sg1 <= 2'b0;
+      ACC1_acc_110_psp_2_lpi_1_dfm_sg1 <= 3'b0;
+      acc_imod_20_lpi_1_dfm <= 2'b0;
+      ACC1_acc_118_psp_1_lpi_1_dfm_sg1 <= 2'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({({((FRAME_acc_2_psp_sva[9:0])
+            | ({8'b0 , (FRAME_acc_2_psp_sva[11:10])})) , (FRAME_acc_2_psp_sva[9:6])
+            , ((FRAME_acc_2_psp_sva[5:0]) | ({4'b0 , (FRAME_acc_2_psp_sva[11:10])}))
+            , (FRAME_acc_2_psp_sva[9:0])}) , vout_rsc_mgc_out_stdreg_d}, ~(exit_FRAME_for_sva_1_st_1
+            & main_stage_0_2));
+        in_2_sva_1 <= MUX_v_16_2_2({in_2_sva_1 , in_2_sva_3}, main_stage_0_2);
+        ACC1_acc_341_itm_1 <= nl_ACC1_acc_341_itm_1[12:0];
+        in_0_sva_1 <= MUX_v_16_2_2({in_0_sva_1 , in_0_sva_3}, main_stage_0_2);
+        exit_FRAME_for_sva_1_st_1 <= ~ (FRAME_for_acc_itm[1]);
+        FRAME_for_acc_26_itm_1 <= nl_FRAME_for_acc_26_itm_1[11:0];
+        FRAME_for_slc_in_2_sva_itm_1 <= nl_FRAME_for_slc_in_2_sva_itm_1[11:0];
+        exit_FRAME_for_lpi_1_dfm_3 <= exit_FRAME_for_lpi_1_dfm_4;
+        FRAME_for_acc_24_itm_1 <= nl_FRAME_for_acc_24_itm_1[12:0];
+        FRAME_for_slc_in_0_sva_itm_1 <= nl_FRAME_for_slc_in_0_sva_itm_1[11:0];
+        i_6_sva_1 <= i_6_sva_2;
+        exit_FRAME_1_sva <= (~ (FRAME_for_acc_itm[1])) & exit_FRAME_lpi_1_dfm_1_mx0;
+        main_stage_0_2 <= 1'b1;
+        ACC1_acc_110_psp_1_lpi_1_dfm_sg1 <= ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0;
+        ACC1_acc_125_psp_lpi_1_dfm <= ACC1_acc_125_psp_lpi_1_dfm_mx0;
+        ACC1_acc_118_psp_lpi_1_dfm_sg1 <= ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0;
+        regs_regs_2_lpi_1_dfm_sg2 <= regs_regs_2_lpi_1_dfm_sg2_mx0;
+        regs_regs_2_lpi_1_dfm_1 <= regs_regs_2_lpi_1_dfm_1_mx0;
+        acc_imod_7_lpi_1_dfm <= acc_imod_7_lpi_1_dfm_mx0;
+        acc_imod_6_lpi_1_dfm_sg1 <= acc_imod_6_lpi_1_dfm_sg1_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_1 <= exit_FRAME_lpi_1_dfm_1_mx0;
+        ACC1_acc_125_psp_1_lpi_1_dfm <= ACC1_acc_125_psp_1_lpi_1_dfm_mx0;
+        acc_imod_18_lpi_1_dfm_sg1 <= acc_imod_18_lpi_1_dfm_sg1_mx0;
+        ACC1_acc_110_psp_2_lpi_1_dfm_sg1 <= ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0;
+        acc_imod_20_lpi_1_dfm <= acc_imod_20_lpi_1_dfm_mx0;
+        ACC1_acc_118_psp_1_lpi_1_dfm_sg1 <= ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0;
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_sva_1 , FRAME_p_1_lpi_1_dfm},
+            FRAME_for_acc_itm[1]);
+      end
+    end
+  end
+  assign nl_ACC1_acc_341_itm_1  = (conv_s2s_26_13(conv_u2s_2_13(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])) * 13'b1101000000001)
+      + conv_u2s_10_13((conv_u2u_9_10({conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[8])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[8])) * 6'b10101) , (ACC1_acc_125_psp_lpi_1_dfm_mx0[3])
+      , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}) + conv_u2u_8_10(conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[7])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[7])) * 8'b1010101) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[5])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[5])) * 6'b10101)) + conv_u2u_6_7({(ACC1_acc_125_psp_lpi_1_dfm_mx0[6])
+      , 1'b0 , (ACC1_acc_125_psp_lpi_1_dfm_mx0[4]) , 1'b0 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}))))
+      + conv_u2u_8_10((conv_u2u_7_8(signext_7_3({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (signext_2_1(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11]))})) + conv_u2u_6_8(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (acc_imod_18_lpi_1_dfm_sg1_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[4])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[2])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , ((ACC1_acc_125_psp_lpi_1_dfm_mx0[11]) & (~ (acc_imod_7_lpi_1_dfm_mx0[1]))
+      & (acc_imod_7_lpi_1_dfm_mx0[0]))}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[6])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[8])
+      , (~((acc_imod_7_lpi_1_dfm_mx0[1]) & (~ (ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))))})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[10])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (acc_imod_6_lpi_1_dfm_sg1_mx0[0])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[1])}))))))))) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[4:3]))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[6])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[8]) ,
+      (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[1])}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_125_psp_lpi_1_dfm_mx0[3])})))))) + conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_125_psp_lpi_1_dfm_mx0[2])
+      , (ACC1_acc_125_psp_lpi_1_dfm_mx0[0]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[2])
+      , (ACC1_acc_125_psp_lpi_1_dfm_mx0[1]) , (ACC1_acc_125_psp_lpi_1_dfm_mx0[2])}))))
+      , 1'b1}) + conv_u2u_4_5({(~ (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[2])) , 1'b1
+      , (~ (acc_imod_6_lpi_1_dfm_sg1_mx0[1])) , ((ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      & (~ (acc_imod_20_lpi_1_dfm_mx0[1])) & (acc_imod_20_lpi_1_dfm_mx0[0]))}))))))
+      + conv_u2u_4_7((readslicef_5_4_1((conv_u2u_4_5({(~ (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[2]))
+      , 1'b1 , (~ (acc_imod_18_lpi_1_dfm_sg1_mx0[1])) , 1'b1}) + conv_s2u_3_5({ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0
+      , (~((acc_imod_20_lpi_1_dfm_mx0[1]) & (~ (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11]))))}))))
+      + (readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_s2s_3_5({ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0 , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[1])})))))))))
+      + (conv_s2s_11_13(conv_u2s_10_12(conv_u2s_20_11(conv_u2u_2_10(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[9])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[9])) * 10'b101010101)) + conv_s2s_9_11(conv_s2s_7_9(conv_u2s_6_7({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[6])
+      , 1'b0 , (ACC1_acc_125_psp_lpi_1_dfm_mx0[6]) , 1'b0 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))})
+      + conv_s2s_5_7(({(conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[4]) + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[6]))
+      , (conv_u2u_2_3(signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[10])) + conv_u2u_2_3(signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])))})
+      + ({3'b100 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}))) + conv_u2s_7_9(signext_7_3({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))})))) + conv_u2s_11_13({conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[10])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[10])) * 8'b1010101) , (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[3])
+      , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}));
+  assign nl_FRAME_for_acc_26_itm_1  = (conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+      , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_sg2_mx0[19:10])
+      , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})))
+      + conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+      , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_sg2_mx0[9:0]) ,
+      10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))
+      + conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+      , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_sg2_mx0[29:20])
+      , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign nl_FRAME_for_slc_in_2_sva_itm_1  = conv_s2s_11_12(conv_u2s_10_11({(acc_10_psp_1_sva[11])
+      , 8'b0 , (acc_10_psp_1_sva[11])}) + (conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_10_psp_1_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_113_psp_1_sva[3])
+      , (acc_10_psp_1_sva[4])})))) + conv_s2s_2_3(ACC1_acc_120_psp_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_10_psp_1_sva[3])
+      , (acc_10_psp_1_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_113_psp_1_sva[3])
+      , (acc_10_psp_1_sva[2]) , (ACC1_acc_113_psp_1_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_10_psp_1_sva[7])
+      , (acc_10_psp_1_sva[4]) , (signext_2_1(acc_10_psp_1_sva[11]))}) + conv_u2u_3_5(ACC1_acc_250_cse)))
+      + conv_u2s_7_8({(acc_10_psp_1_sva[8]) , 1'b0 , (acc_10_psp_1_sva[8]) , 1'b0
+      , (acc_10_psp_1_sva[8]) , 1'b0 , (acc_10_psp_1_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_10_psp_1_sva[11])
+      , (signext_2_1(acc_10_psp_1_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_10_psp_1_sva[6])
+      , 1'b0 , (acc_10_psp_1_sva[6]) , 1'b0 , (acc_10_psp_1_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_250_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[9]) , ((acc_10_psp_1_sva[11])
+      & (~ (ACC1_acc_188_itm[2])) & (ACC1_acc_188_itm[1]))}))))))))) + conv_u2s_10_11({(acc_10_psp_1_sva[11])
+      , 1'b0 , (acc_10_psp_1_sva[11]) , 1'b0 , (acc_10_psp_1_sva[11]) , 1'b0 , (acc_10_psp_1_sva[11])
+      , 1'b0 , (signext_2_1(acc_10_psp_1_sva[11]))}))) + (conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_10_psp_2_sva[10])
+      , 1'b0 , (acc_10_psp_2_sva[10]) , 1'b0 , (acc_10_psp_2_sva[10]) , 1'b0 , (acc_10_psp_2_sva[10])
+      , 1'b0 , (acc_10_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_10_psp_2_sva[9]) ,
+      1'b0 , (acc_10_psp_2_sva[9]) , 1'b0 , (acc_10_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_10_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_10_psp_2_sva[7]) , 1'b0 , (acc_10_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_10_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (~((ACC1_acc_161_itm[2])
+      & (~ (acc_10_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (~ (ACC1_acc_160_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (ACC1_acc_160_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (ACC1_acc_113_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_10_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_113_psp_2_sva[3])
+      , (acc_10_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_120_psp_1_sva[2:1])) +
+      (readslicef_5_4_1((conv_u2s_3_5({(acc_10_psp_2_sva[3]) , (acc_10_psp_2_sva[1])
+      , 1'b1}) + conv_s2s_3_5({(ACC1_acc_113_psp_2_sva[3]) , (acc_10_psp_2_sva[2])
+      , (ACC1_acc_113_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_10_psp_2_sva[7])
+      , (acc_10_psp_2_sva[4]) , (signext_2_1(acc_10_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_277_cse)))
+      + conv_u2s_7_8({(acc_10_psp_2_sva[8]) , 1'b0 , (acc_10_psp_2_sva[8]) , 1'b0
+      , (acc_10_psp_2_sva[8]) , 1'b0 , (acc_10_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_10_psp_2_sva[11])
+      , (signext_2_1(acc_10_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_10_psp_2_sva[6])
+      , 1'b0 , (acc_10_psp_2_sva[6]) , 1'b0 , (acc_10_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_277_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[9]) , ((acc_10_psp_2_sva[11])
+      & (~ (ACC1_acc_161_itm[2])) & (ACC1_acc_161_itm[1]))})))))))))) + ({(acc_10_psp_2_sva[11])
+      , 2'b0 , (acc_10_psp_2_sva[11]) , 1'b0 , (acc_10_psp_2_sva[11]) , 1'b0 , (acc_10_psp_2_sva[11])
+      , (conv_u2u_1_3(acc_10_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11])))}))
+      + conv_u2s_10_12(conv_u2u_9_10({(acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10])
+      , 1'b0 , (acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10])})
+      + conv_u2u_8_10(({(acc_10_psp_1_sva[9]) , 1'b0 , (acc_10_psp_1_sva[9]) , 1'b0
+      , (acc_10_psp_1_sva[9]) , 1'b0 , (signext_2_1(acc_10_psp_1_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_10_psp_1_sva[7])
+      , 1'b0 , (acc_10_psp_1_sva[5]) , 1'b0 , (signext_2_1(acc_10_psp_1_sva[11]))})
+      + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (~((ACC1_acc_188_itm[2])
+      & (~ (acc_10_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (~ (ACC1_acc_187_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (ACC1_acc_187_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (ACC1_acc_113_psp_1_sva[2])})))))))))));
+  assign nl_FRAME_for_acc_24_itm_1  = (conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+      , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_1_mx0[19:10]) ,
+      10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm}))) + conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0])
+      , (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_1_mx0[9:0]) , 10'b0},
+      i_6_lpi_1_dfm)) * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})))) + conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+      , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_1_mx0[29:20]) ,
+      10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign nl_FRAME_for_slc_in_0_sva_itm_1  = conv_s2s_11_12(conv_u2s_10_11({(acc_psp_1_sva[11])
+      , 8'b0 , (acc_psp_1_sva[11])}) + (conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_psp_1_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_107_psp_1_sva[3]) ,
+      (acc_psp_1_sva[4])})))) + conv_s2s_2_3(ACC1_acc_116_psp_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_1_sva[3])
+      , (acc_psp_1_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_107_psp_1_sva[3]) ,
+      (acc_psp_1_sva[2]) , (ACC1_acc_107_psp_1_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_1_sva[7])
+      , (acc_psp_1_sva[4]) , (signext_2_1(acc_psp_1_sva[11]))}) + conv_u2u_3_5(ACC1_acc_197_cse)))
+      + conv_u2s_7_8({(acc_psp_1_sva[8]) , 1'b0 , (acc_psp_1_sva[8]) , 1'b0 , (acc_psp_1_sva[8])
+      , 1'b0 , (acc_psp_1_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_1_sva[11])
+      , (signext_2_1(acc_psp_1_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_1_sva[6])
+      , 1'b0 , (acc_psp_1_sva[6]) , 1'b0 , (acc_psp_1_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_197_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[9]) , ((acc_psp_1_sva[11])
+      & (~ (ACC1_acc_170_itm[2])) & (ACC1_acc_170_itm[1]))}))))))))) + conv_u2s_10_11({(acc_psp_1_sva[11])
+      , 1'b0 , (acc_psp_1_sva[11]) , 1'b0 , (acc_psp_1_sva[11]) , 1'b0 , (acc_psp_1_sva[11])
+      , 1'b0 , (signext_2_1(acc_psp_1_sva[11]))}))) + (conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_psp_2_sva[9]) , 1'b0
+      , (acc_psp_2_sva[9]) , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_2_sva[7]) , 1'b0 , (acc_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~((ACC1_acc_141_itm[2])
+      & (~ (acc_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~ (ACC1_acc_140_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_140_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_107_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_107_psp_2_sva[3]) ,
+      (acc_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_116_psp_1_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_2_sva[3])
+      , (acc_psp_2_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_107_psp_2_sva[3]) ,
+      (acc_psp_2_sva[2]) , (ACC1_acc_107_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_2_sva[7])
+      , (acc_psp_2_sva[4]) , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_224_cse)))
+      + conv_u2s_7_8({(acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])
+      , 1'b0 , (acc_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_2_sva[6])
+      , 1'b0 , (acc_psp_2_sva[6]) , 1'b0 , (acc_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_224_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , ((acc_psp_2_sva[11])
+      & (~ (ACC1_acc_141_itm[2])) & (ACC1_acc_141_itm[1]))})))))))))) + ({(acc_psp_2_sva[11])
+      , 2'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11])
+      , (conv_u2u_1_3(acc_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])))}))
+      + conv_u2s_10_12(conv_u2u_9_10({(acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10])
+      , 1'b0 , (acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10])})
+      + conv_u2u_8_10(({(acc_psp_1_sva[9]) , 1'b0 , (acc_psp_1_sva[9]) , 1'b0 , (acc_psp_1_sva[9])
+      , 1'b0 , (signext_2_1(acc_psp_1_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_1_sva[7])
+      , 1'b0 , (acc_psp_1_sva[5]) , 1'b0 , (signext_2_1(acc_psp_1_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (~((ACC1_acc_170_itm[2])
+      & (~ (acc_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (~ (ACC1_acc_169_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_169_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_107_psp_1_sva[2])})))))))))));
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] MUX_v_3_2_2;
+    input [5:0] inputs;
+    input [0:0] sel;
+    reg [2:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[5:3];
+      end
+      1'b1 : begin
+        result = inputs[2:0];
+      end
+      default : begin
+        result = inputs[5:3];
+      end
+    endcase
+    MUX_v_3_2_2 = result;
+  end
+  endfunction
+
+
+  function [11:0] MUX_v_12_2_2;
+    input [23:0] inputs;
+    input [0:0] sel;
+    reg [11:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[23:12];
+      end
+      1'b1 : begin
+        result = inputs[11:0];
+      end
+      default : begin
+        result = inputs[23:12];
+      end
+    endcase
+    MUX_v_12_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] MUX_v_2_2_2;
+    input [3:0] inputs;
+    input [0:0] sel;
+    reg [1:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[3:2];
+      end
+      1'b1 : begin
+        result = inputs[1:0];
+      end
+      default : begin
+        result = inputs[3:2];
+      end
+    endcase
+    MUX_v_2_2_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [6:0] signext_7_3;
+    input [2:0] vector;
+  begin
+    signext_7_3= {{4{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_2;
+    input [1:0] vector;
+  begin
+    signext_3_2= {{1{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_13_16 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_16 = {{3{vector[12]}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_13_16 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2u_13_16 = {{3{vector[12]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_26_13 ;
+    input signed [25:0]  vector ;
+  begin
+    conv_s2s_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_12_6 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_6 = vector[5:0];
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_2_6 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_6 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_2_8 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_8 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_4_7 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_7 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_s2u_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2u_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_11_13 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_13 = {{2{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_9_11 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_11 = {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2s_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_6_8 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_8 = {{2{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2s_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v8/cycle.rpt b/Sobel/sobel.v8/cycle.rpt
new file mode 100644
index 0000000..09e6645
--- /dev/null
+++ b/Sobel/sobel.v8/cycle.rpt
@@ -0,0 +1,85 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 15:22:24 +0000 2016                      
+
+Solution Settings: sobel.v8
+  Current state: schedule
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       444  921601     921600            0  1          
+    Design Total:                     444  921601     921600            0  0          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /sobel/core              
+    
+  I/O Data Ranges
+    Port       Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ---------- ---- -------- --------- --------- ------- -------- --------
+    vin:rsc.z  IN   Unsigned        90                                     
+    clk        IN   Unsigned         1                                     
+    en         IN   Unsigned         1                                     
+    arst_n     IN   Unsigned         1                                     
+    vout:rsc.z OUT  Unsigned        30                                     
+    
+  Memory Resources
+    Resource Name: /sobel/vin:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 90
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable   Indices Phys Memory Address     
+      ---------- ------- -----------------------
+      /sobel/vin    0:89 00000000-00000000 (0-0) 
+      
+    Resource Name: /sobel/vout:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 30
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable    Indices Phys Memory Address     
+      ----------- ------- -----------------------
+      /sobel/vout    0:29 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process     Loop             Iterations C-Steps Total Cycles  Duration  Unroll Init Comments 
+    ----------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
+    /sobel/core core:rlp           Infinite       0       921602  18.43 ms                       
+    /sobel/core   main             Infinite       3       921602  18.43 ms            1          
+    
+  Loop Execution Profile
+    Process     Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------- ---------------- ------------ -------------------------- ----------------- --------
+    /sobel/core core:rlp                   0                        0.00           921600           
+    /sobel/core   main                921602                      100.00           921600           
+    
+  End of Report
diff --git a/Sobel/sobel.v8/cycle.v b/Sobel/sobel.v8/cycle.v
new file mode 100644
index 0000000..fbfd347
--- /dev/null
+++ b/Sobel/sobel.v8/cycle.v
@@ -0,0 +1,1529 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 15:22:25 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg [18:0] FRAME_p_1_lpi_1;
+    reg [89:0] regs_regs_1_sva;
+    reg [89:0] regs_regs_0_sva;
+    reg exit_FRAME_1_sva;
+    reg [18:0] FRAME_p_1_lpi_1_dfm;
+    reg exit_FRAME_for_lpi_1_dfm;
+    reg [89:0] regs_regs_0_sva_1;
+    reg [11:0] acc_psp_2_sva;
+    reg [3:0] ACC1_acc_107_psp_2_sva;
+    reg [2:0] ACC1_acc_116_psp_1_sva;
+    reg [2:0] acc_imod_14_sva;
+    reg [1:0] acc_imod_16_sva;
+    reg [11:0] ACC1_acc_125_psp_1_sva;
+    reg [3:0] ACC1_acc_110_psp_2_sva;
+    reg [2:0] ACC1_acc_118_psp_1_sva;
+    reg [2:0] acc_imod_18_sva;
+    reg [1:0] acc_imod_20_sva;
+    reg [11:0] acc_10_psp_2_sva;
+    reg [3:0] ACC1_acc_113_psp_2_sva;
+    reg [2:0] ACC1_acc_120_psp_1_sva;
+    reg [2:0] acc_imod_22_sva;
+    reg [1:0] acc_imod_24_sva;
+    reg [11:0] acc_psp_1_sva;
+    reg [3:0] ACC1_acc_107_psp_1_sva;
+    reg [2:0] ACC1_acc_116_psp_sva;
+    reg [2:0] acc_imod_2_sva;
+    reg [1:0] acc_imod_3_sva;
+    reg [11:0] ACC1_acc_125_psp_sva;
+    reg [3:0] ACC1_acc_110_psp_1_sva;
+    reg [2:0] ACC1_acc_118_psp_sva;
+    reg [2:0] acc_imod_6_sva;
+    reg [11:0] acc_10_psp_1_sva;
+    reg [3:0] ACC1_acc_113_psp_1_sva;
+    reg [2:0] ACC1_acc_120_psp_sva;
+    reg [2:0] acc_imod_10_sva;
+    reg [1:0] acc_imod_11_sva;
+    reg [1:0] acc_imod_7_lpi_1_dfm;
+    reg [89:0] regs_regs_0_sva_dfm;
+    reg [89:0] regs_regs_1_sva_dfm;
+    reg [11:0] ACC1_acc_125_psp_lpi_1_dfm;
+    reg [1:0] i_6_lpi_1_dfm;
+    reg [1:0] acc_imod_20_lpi_1_dfm;
+    reg [11:0] ACC1_acc_125_psp_1_lpi_1_dfm;
+    reg FRAME_for_slc_YMATRIX_rom_11_psp_sva;
+    reg [15:0] in_0_sva_1;
+    reg [15:0] in_2_sva_1;
+    reg [1:0] i_6_sva_1;
+    reg exit_FRAME_for_sva_1;
+    reg [14:0] intensity_2_sg1_sva;
+    reg [5:0] acc_imod_12_sva;
+    reg [11:0] FRAME_acc_2_psp_sva;
+    reg [18:0] FRAME_p_1_sva_1;
+    reg exit_FRAME_lpi_1_dfm_1;
+    reg exit_FRAME_for_lpi_1_dfm_2;
+    reg exit_FRAME_for_lpi_1_dfm_3;
+    reg [12:0] FRAME_for_acc_24_itm_1;
+    reg [11:0] FRAME_for_slc_in_0_sva_itm_1;
+    reg [11:0] FRAME_for_acc_26_itm_1;
+    reg [11:0] FRAME_for_slc_in_2_sva_itm_1;
+    reg [12:0] ACC1_acc_341_itm;
+    reg [12:0] ACC1_acc_341_itm_1;
+    reg exit_FRAME_for_sva_1_st_1;
+    reg main_stage_0_2;
+    reg [11:0] in_0_sva_2;
+    reg [11:0] in_2_sva_2;
+    reg [1:0] acc_imod_6_lpi_1_dfm_sg1;
+    reg [29:0] regs_regs_2_lpi_1_dfm_sg2;
+    reg [29:0] regs_regs_2_lpi_1_dfm_1;
+    reg [1:0] ACC1_acc_118_psp_lpi_1_dfm_sg1;
+    reg [2:0] ACC1_acc_110_psp_1_lpi_1_dfm_sg1;
+    reg [1:0] acc_imod_18_lpi_1_dfm_sg1;
+    reg [1:0] ACC1_acc_118_psp_1_lpi_1_dfm_sg1;
+    reg [2:0] ACC1_acc_110_psp_2_lpi_1_dfm_sg1;
+    reg [2:0] ACC1_acc_197_cse;
+    reg [2:0] ACC1_acc_224_cse;
+    reg [2:0] ACC1_acc_250_cse;
+    reg [2:0] ACC1_acc_277_cse;
+    reg FRAME_for_nor_cse;
+    reg FRAME_for_slc_XMATRIX_rom_10_psp_sva_1;
+
+    reg[15:0] FRAME_for_mux_11_nl;
+    reg[15:0] FRAME_for_mux_12_nl;
+    reg[9:0] regs_operator_10_mux_nl;
+    reg[9:0] regs_operator_11_mux_nl;
+    reg[9:0] regs_operator_9_mux_nl;
+    reg[9:0] regs_operator_16_mux_nl;
+    reg[9:0] regs_operator_17_mux_nl;
+    reg[9:0] regs_operator_15_mux_nl;
+    begin : core_rlpExit
+      forever begin : core_rlp
+        // C-Step 0 of Loop 'core_rlp'
+        FRAME_p_1_lpi_1 = 19'b0;
+        regs_regs_1_sva = 90'b0;
+        regs_regs_0_sva = 90'b0;
+        exit_FRAME_1_sva = 1'b1;
+        main_stage_0_2 = 1'b0;
+        begin : mainExit
+          forever begin : main
+            // C-Step 0 of Loop 'main'
+            begin : waitLoop0Exit
+              forever begin : waitLoop0
+                @(posedge clk or negedge ( arst_n ));
+                if ( ~ arst_n )
+                  disable core_rlpExit;
+                if ( en )
+                  disable waitLoop0Exit;
+              end
+            end
+            // C-Step 1 of Loop 'main'
+            if ( main_stage_0_2 ) begin
+              FRAME_for_mux_11_nl = MUX_v_16_2_2({in_0_sva_1 , ({{4{FRAME_for_slc_in_0_sva_itm_1[11]}},
+                  FRAME_for_slc_in_0_sva_itm_1})}, exit_FRAME_for_lpi_1_dfm_3);
+              in_0_sva_1 = conv_s2u_13_16(FRAME_for_acc_24_itm_1) + (FRAME_for_mux_11_nl);
+              FRAME_for_mux_12_nl = MUX_v_16_2_2({in_2_sva_1 , ({{4{FRAME_for_slc_in_2_sva_itm_1[11]}},
+                  FRAME_for_slc_in_2_sva_itm_1})}, exit_FRAME_for_lpi_1_dfm_3);
+              in_2_sva_1 = conv_s2u_12_16(FRAME_for_acc_26_itm_1) + (FRAME_for_mux_12_nl);
+              if ( exit_FRAME_for_sva_1_st_1 ) begin
+                intensity_2_sg1_sva = readslicef_16_15_1(((in_2_sva_1 + conv_s2s_13_16(ACC1_acc_341_itm_1))
+                    + in_0_sva_1));
+                acc_imod_12_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(intensity_2_sg1_sva[8:6])
+                    + conv_u2u_3_4(~ (intensity_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                    (intensity_2_sg1_sva[14])) , 1'b1 , (~ (intensity_2_sg1_sva[14]))})
+                    + conv_u2u_2_4(intensity_2_sg1_sva[13:12]))) + conv_u2u_4_6(conv_u2u_3_4(intensity_2_sg1_sva[2:0])
+                    + conv_u2u_3_4(~ (intensity_2_sg1_sva[5:3])))) + 6'b101011;
+                FRAME_acc_2_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(intensity_2_sg1_sva[13:12])
+                    * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(intensity_2_sg1_sva[11:9])
+                    * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(intensity_2_sg1_sva[8:3])
+                    + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_12_sva[5]))
+                    , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_12_sva[2:0])
+                    , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_12_sva[5:3])) , (~ (acc_imod_12_sva[5]))})))))})
+                    + conv_u2u_2_4(acc_imod_12_sva[4:3])) + conv_u2u_3_5(~ (intensity_2_sg1_sva[8:6])))
+                    + ({4'b1001 , (acc_imod_12_sva[5])}))))) + conv_u2u_11_12(signext_11_9({(intensity_2_sg1_sva[14])
+                    , 3'b0 , (signext_3_1(intensity_2_sg1_sva[14])) , 1'b0 , (intensity_2_sg1_sva[14])}));
+                vout_rsc_mgc_out_stdreg_d <= {((FRAME_acc_2_psp_sva[9:0]) | ({8'b0,
+                    FRAME_acc_2_psp_sva[11:10]})) , (FRAME_acc_2_psp_sva[9:6]) ,
+                    ((FRAME_acc_2_psp_sva[5:0]) | ({4'b0, FRAME_acc_2_psp_sva[11:10]}))
+                    , (FRAME_acc_2_psp_sva[9:0])};
+              end
+            end
+            FRAME_p_1_sva_1 = 19'b0;
+            in_2_sva_2 = 12'b0;
+            in_0_sva_2 = 12'b0;
+            acc_imod_20_sva = 2'b0;
+            acc_imod_18_sva = 3'b0;
+            ACC1_acc_118_psp_1_sva = 3'b0;
+            ACC1_acc_110_psp_2_sva = 4'b0;
+            ACC1_acc_125_psp_1_sva = 12'b0;
+            FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+            exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_lpi_1_dfm_2 | exit_FRAME_1_sva;
+            if ( exit_FRAME_for_lpi_1_dfm ) begin
+              regs_regs_0_sva_1 = vin_rsc_mgc_in_wire_d;
+              acc_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (regs_regs_0_sva_1[9:0]))
+                  + conv_s2s_10_11(~ (regs_regs_0_sva_1[19:10]))) + conv_s2s_11_12(conv_s2s_10_11(~
+                  (regs_regs_0_sva_1[29:20])) + 11'b11);
+              ACC1_acc_107_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                  (acc_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_2_sva[1]))
+                  , (acc_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_2_sva[0])
+                  , (acc_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[2])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[3])) , (~ (acc_psp_2_sva[7]))}))))
+                  , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[4])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[5])) , (acc_psp_2_sva[6])}))))
+                  , (~ (acc_psp_2_sva[9]))}))));
+              ACC1_acc_116_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_107_psp_2_sva[0])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_107_psp_2_sva[1])) , (ACC1_acc_107_psp_2_sva[2])}))))
+                  + conv_s2s_1_3(~ (ACC1_acc_107_psp_2_sva[3]));
+              acc_imod_14_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_116_psp_1_sva[2:1]))
+                  , 1'b1}) + conv_u2s_2_4({(ACC1_acc_116_psp_1_sva[0]) , 1'b1})));
+              acc_imod_16_sva = readslicef_3_2_1((({1'b1 , (acc_imod_14_sva[0]) ,
+                  1'b1}) + conv_u2s_2_3({(~ (acc_imod_14_sva[1])) , (~ (acc_imod_14_sva[2]))})));
+              ACC1_acc_125_psp_1_sva = conv_s2u_11_12(conv_s2s_10_11(~ (regs_regs_0_sva_1[39:30]))
+                  + conv_s2s_10_11(~ (regs_regs_0_sva_1[49:40]))) + conv_s2u_11_12(conv_s2s_10_11(~
+                  (regs_regs_0_sva_1[59:50])) + 11'b11);
+              ACC1_acc_110_psp_2_sva = readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((({2'b10
+                  , (~ (ACC1_acc_125_psp_1_sva[0])) , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_1_sva[1])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_1_sva[2])) , (~ (ACC1_acc_125_psp_1_sva[6]))}))))
+                  , (~ (ACC1_acc_125_psp_1_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_1_sva[3])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_1_sva[4])) , (ACC1_acc_125_psp_1_sva[5])}))))
+                  , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_125_psp_1_sva[11:10])) ,
+                  (ACC1_acc_125_psp_1_sva[7])})))) , (ACC1_acc_125_psp_1_sva[9])})));
+              ACC1_acc_118_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_110_psp_2_sva[0])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_110_psp_2_sva[1])) , (ACC1_acc_110_psp_2_sva[2])}))))
+                  + conv_s2s_1_3(~ (ACC1_acc_110_psp_2_sva[3]));
+              acc_imod_18_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_118_psp_1_sva[2:1]))
+                  , 1'b1}) + conv_u2s_2_4({(ACC1_acc_118_psp_1_sva[0]) , 1'b1})));
+              acc_imod_20_sva = readslicef_3_2_1((({1'b1 , (acc_imod_18_sva[0]) ,
+                  1'b1}) + conv_u2s_2_3({(~ (acc_imod_18_sva[1])) , (~ (acc_imod_18_sva[2]))})));
+              acc_10_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (regs_regs_0_sva_1[69:60]))
+                  + conv_s2s_10_11(~ (regs_regs_0_sva_1[79:70]))) + conv_s2s_11_12(conv_s2s_10_11(~
+                  (regs_regs_0_sva_1[89:80])) + 11'b11);
+              ACC1_acc_113_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                  (acc_10_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_10_psp_2_sva[1]))
+                  , (acc_10_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_10_psp_2_sva[0])
+                  , (acc_10_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_2_sva[2])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_2_sva[3])) , (~ (acc_10_psp_2_sva[7]))}))))
+                  , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_2_sva[4])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_2_sva[5])) , (acc_10_psp_2_sva[6])}))))
+                  , (~ (acc_10_psp_2_sva[9]))}))));
+              ACC1_acc_120_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_113_psp_2_sva[0])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_113_psp_2_sva[1])) , (ACC1_acc_113_psp_2_sva[2])}))))
+                  + conv_s2s_1_3(~ (ACC1_acc_113_psp_2_sva[3]));
+              acc_imod_22_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_120_psp_1_sva[2:1]))
+                  , 1'b1}) + conv_u2s_2_4({(ACC1_acc_120_psp_1_sva[0]) , 1'b1})));
+              acc_imod_24_sva = readslicef_3_2_1((({1'b1 , (acc_imod_22_sva[0]) ,
+                  1'b1}) + conv_u2s_2_3({(~ (acc_imod_22_sva[1])) , (~ (acc_imod_22_sva[2]))})));
+              acc_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_1_sva[19:10])
+                  + conv_s2s_10_11(regs_regs_1_sva[9:0])) + conv_s2s_10_12(regs_regs_1_sva[29:20]);
+              ACC1_acc_107_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                  (acc_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_1_sva[1]))
+                  , (acc_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_1_sva[0])
+                  , (acc_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[2])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[3])) , (~ (acc_psp_1_sva[7]))}))))
+                  , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[4])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[5])) , (acc_psp_1_sva[6])}))))
+                  , (~ (acc_psp_1_sva[9]))}))));
+              ACC1_acc_116_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_107_psp_1_sva[0])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_107_psp_1_sva[1])) , (ACC1_acc_107_psp_1_sva[2])}))))
+                  + conv_s2s_1_3(~ (ACC1_acc_107_psp_1_sva[3]));
+              acc_imod_2_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_116_psp_sva[2:1]))
+                  , 1'b1}) + conv_u2s_2_4({(ACC1_acc_116_psp_sva[0]) , 1'b1})));
+              acc_imod_3_sva = readslicef_3_2_1((({1'b1 , (acc_imod_2_sva[0]) , 1'b1})
+                  + conv_u2s_2_3({(~ (acc_imod_2_sva[1])) , (~ (acc_imod_2_sva[2]))})));
+              ACC1_acc_125_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_1_sva[49:40])
+                  + conv_s2s_10_11(regs_regs_1_sva[39:30])) + conv_s2u_10_12(regs_regs_1_sva[59:50]);
+              ACC1_acc_110_psp_1_sva = readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((({2'b10
+                  , (~ (ACC1_acc_125_psp_sva[0])) , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_sva[1])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_sva[2])) , (~ (ACC1_acc_125_psp_sva[6]))}))))
+                  , (~ (ACC1_acc_125_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_sva[3])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_sva[4])) , (ACC1_acc_125_psp_sva[5])}))))
+                  , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_125_psp_sva[11:10])) , (ACC1_acc_125_psp_sva[7])}))))
+                  , (ACC1_acc_125_psp_sva[9])})));
+              ACC1_acc_118_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_110_psp_1_sva[0])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_110_psp_1_sva[1])) , (ACC1_acc_110_psp_1_sva[2])}))))
+                  + conv_s2s_1_3(~ (ACC1_acc_110_psp_1_sva[3]));
+              acc_imod_6_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_118_psp_sva[2:1]))
+                  , 1'b1}) + conv_u2s_2_4({(ACC1_acc_118_psp_sva[0]) , 1'b1})));
+              acc_10_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_1_sva[79:70])
+                  + conv_s2s_10_11(regs_regs_1_sva[69:60])) + conv_s2s_10_12(regs_regs_1_sva[89:80]);
+              ACC1_acc_113_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+                  (acc_10_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_10_psp_1_sva[1]))
+                  , (acc_10_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_10_psp_1_sva[0])
+                  , (acc_10_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_1_sva[2])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_1_sva[3])) , (~ (acc_10_psp_1_sva[7]))}))))
+                  , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_1_sva[4])
+                  , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_1_sva[5])) , (acc_10_psp_1_sva[6])}))))
+                  , (~ (acc_10_psp_1_sva[9]))}))));
+              ACC1_acc_120_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_113_psp_1_sva[0])
+                  , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_113_psp_1_sva[1])) , (ACC1_acc_113_psp_1_sva[2])}))))
+                  + conv_s2s_1_3(~ (ACC1_acc_113_psp_1_sva[3]));
+              acc_imod_10_sva = readslicef_4_3_1((conv_s2s_3_4({(~ (ACC1_acc_120_psp_sva[2:1]))
+                  , 1'b1}) + conv_u2s_2_4({(ACC1_acc_120_psp_sva[0]) , 1'b1})));
+              acc_imod_11_sva = readslicef_3_2_1((({1'b1 , (acc_imod_10_sva[0]) ,
+                  1'b1}) + conv_u2s_2_3({(~ (acc_imod_10_sva[1])) , (~ (acc_imod_10_sva[2]))})));
+              ACC1_acc_197_cse = conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]));
+              ACC1_acc_224_cse = conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11]));
+              in_0_sva_2 = conv_s2s_11_12(conv_u2s_10_11({(acc_psp_1_sva[11]) , 8'b0
+                  , (acc_psp_1_sva[11])}) + (conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+                  , (acc_psp_1_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_107_psp_1_sva[3])
+                  , (acc_psp_1_sva[4])})))) + conv_s2s_2_3(ACC1_acc_116_psp_sva[2:1]))
+                  + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_1_sva[3]) , (acc_psp_1_sva[1])
+                  , 1'b1}) + conv_s2s_3_5({(ACC1_acc_107_psp_1_sva[3]) , (acc_psp_1_sva[2])
+                  , (ACC1_acc_107_psp_1_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_1_sva[7])
+                  , (acc_psp_1_sva[4]) , (signext_2_1(acc_psp_1_sva[11]))}) + conv_u2u_3_5(ACC1_acc_197_cse)))
+                  + conv_u2s_7_8({(acc_psp_1_sva[8]) , 1'b0 , (acc_psp_1_sva[8])
+                  , 1'b0 , (acc_psp_1_sva[8]) , 1'b0 , (acc_psp_1_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_1_sva[11])
+                  , (signext_2_1(acc_psp_1_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_1_sva[6])
+                  , 1'b0 , (acc_psp_1_sva[6]) , 1'b0 , (acc_psp_1_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_197_cse)
+                  + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[7])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[9]) , ((acc_psp_1_sva[11])
+                  & (~ (acc_imod_3_sva[1])) & (acc_imod_3_sva[0]))}))))))))) + conv_u2s_10_11({(acc_psp_1_sva[11])
+                  , 1'b0 , (acc_psp_1_sva[11]) , 1'b0 , (acc_psp_1_sva[11]) , 1'b0
+                  , (acc_psp_1_sva[11]) , 1'b0 , (signext_2_1(acc_psp_1_sva[11]))})))
+                  + (conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_psp_2_sva[10])
+                  , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10]) , 1'b0
+                  , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_psp_2_sva[9])
+                  , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 , (acc_psp_2_sva[9]) , 1'b0
+                  , (signext_2_1(acc_psp_2_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_2_sva[7])
+                  , 1'b0 , (acc_psp_2_sva[5]) , 1'b0 , (signext_2_1(acc_psp_2_sva[11]))})
+                  + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~((acc_imod_16_sva[1])
+                  & (~ (acc_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~
+                  (acc_imod_14_sva[2]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (acc_imod_14_sva[1])})))))
+                  + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_107_psp_2_sva[2])}))))))))))
+                  + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+                  , (acc_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_107_psp_2_sva[3])
+                  , (acc_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_116_psp_1_sva[2:1]))
+                  + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_2_sva[3]) , (acc_psp_2_sva[1])
+                  , 1'b1}) + conv_s2s_3_5({(ACC1_acc_107_psp_2_sva[3]) , (acc_psp_2_sva[2])
+                  , (ACC1_acc_107_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_2_sva[7])
+                  , (acc_psp_2_sva[4]) , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_224_cse)))
+                  + conv_u2s_7_8({(acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])
+                  , 1'b0 , (acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+                  , (signext_2_1(acc_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_2_sva[6])
+                  , 1'b0 , (acc_psp_2_sva[6]) , 1'b0 , (acc_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_224_cse)
+                  + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , ((acc_psp_2_sva[11])
+                  & (~ (acc_imod_16_sva[1])) & (acc_imod_16_sva[0]))})))))))))) +
+                  ({(acc_psp_2_sva[11]) , 2'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11])
+                  , 1'b0 , (acc_psp_2_sva[11]) , (conv_u2u_1_3(acc_psp_2_sva[11])
+                  + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])))})) + conv_u2s_10_12(conv_u2u_9_10({(acc_psp_1_sva[10])
+                  , 1'b0 , (acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10]) , 1'b0
+                  , (acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10])}) + conv_u2u_8_10(({(acc_psp_1_sva[9])
+                  , 1'b0 , (acc_psp_1_sva[9]) , 1'b0 , (acc_psp_1_sva[9]) , 1'b0
+                  , (signext_2_1(acc_psp_1_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_1_sva[7])
+                  , 1'b0 , (acc_psp_1_sva[5]) , 1'b0 , (signext_2_1(acc_psp_1_sva[11]))})
+                  + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (~((acc_imod_3_sva[1])
+                  & (~ (acc_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (~
+                  (acc_imod_2_sva[2]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (acc_imod_2_sva[1])})))))
+                  + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_107_psp_1_sva[2])})))))))))));
+              ACC1_acc_250_cse = conv_u2u_2_3(signext_2_1(acc_10_psp_1_sva[11]))
+                  + conv_u2u_2_3(signext_2_1(acc_10_psp_1_sva[11]));
+              ACC1_acc_277_cse = conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11]))
+                  + conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11]));
+              in_2_sva_2 = conv_s2s_11_12(conv_u2s_10_11({(acc_10_psp_1_sva[11])
+                  , 8'b0 , (acc_10_psp_1_sva[11])}) + (conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+                  , (acc_10_psp_1_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_113_psp_1_sva[3])
+                  , (acc_10_psp_1_sva[4])})))) + conv_s2s_2_3(ACC1_acc_120_psp_sva[2:1]))
+                  + (readslicef_5_4_1((conv_u2s_3_5({(acc_10_psp_1_sva[3]) , (acc_10_psp_1_sva[1])
+                  , 1'b1}) + conv_s2s_3_5({(ACC1_acc_113_psp_1_sva[3]) , (acc_10_psp_1_sva[2])
+                  , (ACC1_acc_113_psp_1_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_10_psp_1_sva[7])
+                  , (acc_10_psp_1_sva[4]) , (signext_2_1(acc_10_psp_1_sva[11]))})
+                  + conv_u2u_3_5(ACC1_acc_250_cse))) + conv_u2s_7_8({(acc_10_psp_1_sva[8])
+                  , 1'b0 , (acc_10_psp_1_sva[8]) , 1'b0 , (acc_10_psp_1_sva[8]) ,
+                  1'b0 , (acc_10_psp_1_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_10_psp_1_sva[11])
+                  , (signext_2_1(acc_10_psp_1_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_10_psp_1_sva[6])
+                  , 1'b0 , (acc_10_psp_1_sva[6]) , 1'b0 , (acc_10_psp_1_sva[6])})
+                  + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_250_cse) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[7])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[9]) , ((acc_10_psp_1_sva[11])
+                  & (~ (acc_imod_11_sva[1])) & (acc_imod_11_sva[0]))}))))))))) +
+                  conv_u2s_10_11({(acc_10_psp_1_sva[11]) , 1'b0 , (acc_10_psp_1_sva[11])
+                  , 1'b0 , (acc_10_psp_1_sva[11]) , 1'b0 , (acc_10_psp_1_sva[11])
+                  , 1'b0 , (signext_2_1(acc_10_psp_1_sva[11]))}))) + (conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_10_psp_2_sva[10])
+                  , 1'b0 , (acc_10_psp_2_sva[10]) , 1'b0 , (acc_10_psp_2_sva[10])
+                  , 1'b0 , (acc_10_psp_2_sva[10]) , 1'b0 , (acc_10_psp_2_sva[10])})
+                  + conv_u2u_8_10(({(acc_10_psp_2_sva[9]) , 1'b0 , (acc_10_psp_2_sva[9])
+                  , 1'b0 , (acc_10_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_10_psp_2_sva[5]))})
+                  + conv_u2u_7_8(conv_u2u_6_7({(acc_10_psp_2_sva[7]) , 1'b0 , (acc_10_psp_2_sva[5])
+                  , 1'b0 , (signext_2_1(acc_10_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) ,
+                  (~((acc_imod_24_sva[1]) & (~ (acc_10_psp_2_sva[11]))))}))))) +
+                  conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) ,
+                  (~ (acc_imod_22_sva[2]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) ,
+                  (acc_imod_22_sva[1])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) ,
+                  (ACC1_acc_113_psp_2_sva[2])})))))))))) + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+                  , (acc_10_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_113_psp_2_sva[3])
+                  , (acc_10_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_120_psp_1_sva[2:1]))
+                  + (readslicef_5_4_1((conv_u2s_3_5({(acc_10_psp_2_sva[3]) , (acc_10_psp_2_sva[1])
+                  , 1'b1}) + conv_s2s_3_5({(ACC1_acc_113_psp_2_sva[3]) , (acc_10_psp_2_sva[2])
+                  , (ACC1_acc_113_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_10_psp_2_sva[7])
+                  , (acc_10_psp_2_sva[4]) , (signext_2_1(acc_10_psp_2_sva[11]))})
+                  + conv_u2u_3_5(ACC1_acc_277_cse))) + conv_u2s_7_8({(acc_10_psp_2_sva[8])
+                  , 1'b0 , (acc_10_psp_2_sva[8]) , 1'b0 , (acc_10_psp_2_sva[8]) ,
+                  1'b0 , (acc_10_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_10_psp_2_sva[11])
+                  , (signext_2_1(acc_10_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_10_psp_2_sva[6])
+                  , 1'b0 , (acc_10_psp_2_sva[6]) , 1'b0 , (acc_10_psp_2_sva[6])})
+                  + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_277_cse) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[7])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[9]) , ((acc_10_psp_2_sva[11])
+                  & (~ (acc_imod_24_sva[1])) & (acc_imod_24_sva[0]))})))))))))) +
+                  ({(acc_10_psp_2_sva[11]) , 2'b0 , (acc_10_psp_2_sva[11]) , 1'b0
+                  , (acc_10_psp_2_sva[11]) , 1'b0 , (acc_10_psp_2_sva[11]) , (conv_u2u_1_3(acc_10_psp_2_sva[11])
+                  + conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11])))})) + conv_u2s_10_12(conv_u2u_9_10({(acc_10_psp_1_sva[10])
+                  , 1'b0 , (acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10])
+                  , 1'b0 , (acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10])})
+                  + conv_u2u_8_10(({(acc_10_psp_1_sva[9]) , 1'b0 , (acc_10_psp_1_sva[9])
+                  , 1'b0 , (acc_10_psp_1_sva[9]) , 1'b0 , (signext_2_1(acc_10_psp_1_sva[5]))})
+                  + conv_u2u_7_8(conv_u2u_6_7({(acc_10_psp_1_sva[7]) , 1'b0 , (acc_10_psp_1_sva[5])
+                  , 1'b0 , (signext_2_1(acc_10_psp_1_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) ,
+                  (~((acc_imod_11_sva[1]) & (~ (acc_10_psp_1_sva[11]))))}))))) +
+                  conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) ,
+                  (~ (acc_imod_10_sva[2]))})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) ,
+                  (acc_imod_10_sva[1])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) ,
+                  (ACC1_acc_113_psp_1_sva[2])})))))))))));
+              acc_imod_6_lpi_1_dfm_sg1 = acc_imod_6_sva[2:1];
+              acc_imod_7_lpi_1_dfm = readslicef_3_2_1((({1'b1 , (acc_imod_6_sva[0])
+                  , 1'b1}) + conv_u2s_2_3({(~ (acc_imod_6_sva[1])) , (~ (acc_imod_6_sva[2]))})));
+              regs_regs_0_sva_dfm = regs_regs_0_sva_1;
+              regs_regs_1_sva_dfm = regs_regs_0_sva;
+              regs_regs_2_lpi_1_dfm_1 = regs_regs_1_sva[29:0];
+              regs_regs_2_lpi_1_dfm_sg2 = regs_regs_1_sva[89:60];
+              ACC1_acc_118_psp_lpi_1_dfm_sg1 = ACC1_acc_118_psp_sva[2:1];
+              ACC1_acc_125_psp_lpi_1_dfm = ACC1_acc_125_psp_sva;
+              ACC1_acc_110_psp_1_lpi_1_dfm_sg1 = ACC1_acc_110_psp_1_sva[3:1];
+            end
+            else begin
+              regs_regs_0_sva_dfm = regs_regs_0_sva;
+              regs_regs_1_sva_dfm = regs_regs_1_sva;
+            end
+            i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm));
+            acc_imod_18_lpi_1_dfm_sg1 = MUX_v_2_2_2({acc_imod_18_lpi_1_dfm_sg1 ,
+                (acc_imod_18_sva[2:1])}, exit_FRAME_for_lpi_1_dfm);
+            acc_imod_20_lpi_1_dfm = MUX_v_2_2_2({acc_imod_20_lpi_1_dfm , acc_imod_20_sva},
+                exit_FRAME_for_lpi_1_dfm);
+            ACC1_acc_118_psp_1_lpi_1_dfm_sg1 = MUX_v_2_2_2({ACC1_acc_118_psp_1_lpi_1_dfm_sg1
+                , (ACC1_acc_118_psp_1_sva[2:1])}, exit_FRAME_for_lpi_1_dfm);
+            ACC1_acc_125_psp_1_lpi_1_dfm = MUX_v_12_2_2({ACC1_acc_125_psp_1_lpi_1_dfm
+                , ACC1_acc_125_psp_1_sva}, exit_FRAME_for_lpi_1_dfm);
+            ACC1_acc_110_psp_2_lpi_1_dfm_sg1 = MUX_v_3_2_2({ACC1_acc_110_psp_2_lpi_1_dfm_sg1
+                , (ACC1_acc_110_psp_2_sva[3:1])}, exit_FRAME_for_lpi_1_dfm);
+            FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+            FRAME_for_slc_YMATRIX_rom_11_psp_sva = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1]))))
+                | FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+            FRAME_for_slc_XMATRIX_rom_10_psp_sva_1 = (~((~ (i_6_lpi_1_dfm[1])) &
+                (i_6_lpi_1_dfm[0]))) | FRAME_for_nor_cse;
+            i_6_sva_1 = i_6_lpi_1_dfm + 2'b1;
+            exit_FRAME_for_sva_1 = ~ (readslicef_3_1_2((({1'b1 , i_6_sva_1}) + 3'b1)));
+            if ( exit_FRAME_for_sva_1 ) begin
+              ACC1_acc_341_itm = (conv_s2s_26_13(conv_u2s_2_13(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[11])) * 13'b1101000000001)
+                  + conv_u2s_10_13((conv_u2u_9_10({conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm[8])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[8])) * 6'b10101) ,
+                  (ACC1_acc_125_psp_lpi_1_dfm[3]) , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11]))})
+                  + conv_u2u_8_10(conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm[7])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[7])) * 8'b1010101)
+                  + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm[5])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[5])) * 6'b10101)) +
+                  conv_u2u_6_7({(ACC1_acc_125_psp_lpi_1_dfm[6]) , 1'b0 , (ACC1_acc_125_psp_lpi_1_dfm[4])
+                  , 1'b0 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11]))})))) + conv_u2u_8_10((conv_u2u_7_8(signext_7_3({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (signext_2_1(ACC1_acc_125_psp_1_lpi_1_dfm[11]))})) + conv_u2u_6_8(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , (acc_imod_18_lpi_1_dfm_sg1[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[4])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1[2])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , ((ACC1_acc_125_psp_lpi_1_dfm[11]) & (~ (acc_imod_7_lpi_1_dfm[1]))
+                  & (acc_imod_7_lpi_1_dfm[0]))}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[6])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[8])
+                  , (~((acc_imod_7_lpi_1_dfm[1]) & (~ (ACC1_acc_125_psp_lpi_1_dfm[11]))))})))))
+                  + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[10])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (acc_imod_6_lpi_1_dfm_sg1[0])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1[1])}))))))))) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2(ACC1_acc_125_psp_1_lpi_1_dfm[4:3]))))))
+                  + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  , (ACC1_acc_125_psp_1_lpi_1_dfm[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[6])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[8])
+                  , (ACC1_acc_125_psp_1_lpi_1_dfm[1])}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , (ACC1_acc_125_psp_1_lpi_1_dfm[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , (ACC1_acc_125_psp_lpi_1_dfm[3])})))))) + conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_125_psp_lpi_1_dfm[2])
+                  , (ACC1_acc_125_psp_lpi_1_dfm[0]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_125_psp_1_lpi_1_dfm[2])
+                  , (ACC1_acc_125_psp_lpi_1_dfm[1]) , (ACC1_acc_125_psp_lpi_1_dfm[2])}))))
+                  , 1'b1}) + conv_u2u_4_5({(~ (ACC1_acc_110_psp_1_lpi_1_dfm_sg1[2]))
+                  , 1'b1 , (~ (acc_imod_6_lpi_1_dfm_sg1[1])) , ((ACC1_acc_125_psp_1_lpi_1_dfm[11])
+                  & (~ (acc_imod_20_lpi_1_dfm[1])) & (acc_imod_20_lpi_1_dfm[0]))}))))))
+                  + conv_u2u_4_7((readslicef_5_4_1((conv_u2u_4_5({(~ (ACC1_acc_110_psp_2_lpi_1_dfm_sg1[2]))
+                  , 1'b1 , (~ (acc_imod_18_lpi_1_dfm_sg1[1])) , 1'b1}) + conv_s2u_3_5({ACC1_acc_118_psp_lpi_1_dfm_sg1
+                  , (~((acc_imod_20_lpi_1_dfm[1]) & (~ (ACC1_acc_125_psp_1_lpi_1_dfm[11]))))}))))
+                  + (readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm[11])
+                  , 1'b1})) + conv_s2s_3_5({ACC1_acc_118_psp_1_lpi_1_dfm_sg1 , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1[1])})))))))))
+                  + (conv_s2s_11_13(conv_u2s_10_12(conv_u2s_20_11(conv_u2u_2_10(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm[9])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[9])) * 10'b101010101))
+                  + conv_s2s_9_11(conv_s2s_7_9(conv_u2s_6_7({(ACC1_acc_125_psp_1_lpi_1_dfm[6])
+                  , 1'b0 , (ACC1_acc_125_psp_lpi_1_dfm[6]) , 1'b0 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11]))})
+                  + conv_s2s_5_7(({(conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[4])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[6])) , (conv_u2u_2_3(signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[10]))
+                  + conv_u2u_2_3(signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11])))})
+                  + ({3'b100 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11]))})))
+                  + conv_u2s_7_9(signext_7_3({(ACC1_acc_125_psp_lpi_1_dfm[11]) ,
+                  (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11]))})))) + conv_u2s_11_13({conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm[10])
+                  + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm[10])) * 8'b1010101)
+                  , (ACC1_acc_125_psp_1_lpi_1_dfm[3]) , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm[11]))}));
+              FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+              exit_FRAME_lpi_1_dfm_1 = ~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+                  + 8'b10110101)));
+            end
+            else begin
+              exit_FRAME_lpi_1_dfm_1 = exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm);
+            end
+            exit_FRAME_for_lpi_1_dfm_2 = exit_FRAME_for_sva_1;
+            regs_regs_0_sva = regs_regs_0_sva_dfm;
+            regs_regs_1_sva = regs_regs_1_sva_dfm;
+            FRAME_p_1_lpi_1 = MUX_v_19_2_2({FRAME_p_1_lpi_1_dfm , FRAME_p_1_sva_1},
+                exit_FRAME_for_sva_1);
+            exit_FRAME_1_sva = exit_FRAME_for_sva_1 & exit_FRAME_lpi_1_dfm_1;
+            exit_FRAME_for_lpi_1_dfm_3 = exit_FRAME_for_lpi_1_dfm;
+            regs_operator_10_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[19:10])
+                , (regs_regs_1_sva_dfm[19:10]) , (regs_regs_2_lpi_1_dfm_1[19:10])
+                , 10'b0}, i_6_lpi_1_dfm);
+            regs_operator_11_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[9:0]) ,
+                (regs_regs_1_sva_dfm[9:0]) , (regs_regs_2_lpi_1_dfm_1[9:0]) , 10'b0},
+                i_6_lpi_1_dfm);
+            regs_operator_9_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[29:20]) ,
+                (regs_regs_1_sva_dfm[29:20]) , (regs_regs_2_lpi_1_dfm_1[29:20]) ,
+                10'b0}, i_6_lpi_1_dfm);
+            FRAME_for_acc_24_itm_1 = (conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(regs_operator_10_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva})))
+                + conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(regs_operator_11_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva}))))
+                + conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(regs_operator_9_mux_nl)
+                * conv_s2s_2_12({1'b1 , FRAME_for_slc_YMATRIX_rom_11_psp_sva})));
+            FRAME_for_slc_in_0_sva_itm_1 = in_0_sva_2;
+            regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[79:70])
+                , (regs_regs_1_sva_dfm[79:70]) , (regs_regs_2_lpi_1_dfm_sg2[19:10])
+                , 10'b0}, i_6_lpi_1_dfm);
+            regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[69:60])
+                , (regs_regs_1_sva_dfm[69:60]) , (regs_regs_2_lpi_1_dfm_sg2[9:0])
+                , 10'b0}, i_6_lpi_1_dfm);
+            regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[89:80])
+                , (regs_regs_1_sva_dfm[89:80]) , (regs_regs_2_lpi_1_dfm_sg2[29:20])
+                , 10'b0}, i_6_lpi_1_dfm);
+            FRAME_for_acc_26_itm_1 = (conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(regs_operator_16_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_10_psp_sva_1})))
+                + conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(regs_operator_17_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_10_psp_sva_1}))))
+                + conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(regs_operator_15_mux_nl)
+                * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_10_psp_sva_1})));
+            FRAME_for_slc_in_2_sva_itm_1 = in_2_sva_2;
+            ACC1_acc_341_itm_1 = ACC1_acc_341_itm;
+            exit_FRAME_for_sva_1_st_1 = exit_FRAME_for_sva_1;
+            main_stage_0_2 = 1'b1;
+          end
+        end
+      end
+    end
+    FRAME_for_slc_XMATRIX_rom_10_psp_sva_1 = 1'b0;
+    FRAME_for_nor_cse = 1'b0;
+    ACC1_acc_277_cse = 3'b0;
+    ACC1_acc_250_cse = 3'b0;
+    ACC1_acc_224_cse = 3'b0;
+    ACC1_acc_197_cse = 3'b0;
+    ACC1_acc_110_psp_2_lpi_1_dfm_sg1 = 3'b0;
+    ACC1_acc_118_psp_1_lpi_1_dfm_sg1 = 2'b0;
+    acc_imod_18_lpi_1_dfm_sg1 = 2'b0;
+    ACC1_acc_110_psp_1_lpi_1_dfm_sg1 = 3'b0;
+    ACC1_acc_118_psp_lpi_1_dfm_sg1 = 2'b0;
+    regs_regs_2_lpi_1_dfm_1 = 30'b0;
+    regs_regs_2_lpi_1_dfm_sg2 = 30'b0;
+    acc_imod_6_lpi_1_dfm_sg1 = 2'b0;
+    in_2_sva_2 = 12'b0;
+    in_0_sva_2 = 12'b0;
+    main_stage_0_2 = 1'b0;
+    exit_FRAME_for_sva_1_st_1 = 1'b0;
+    ACC1_acc_341_itm_1 = 13'b0;
+    ACC1_acc_341_itm = 13'b0;
+    FRAME_for_slc_in_2_sva_itm_1 = 12'b0;
+    FRAME_for_acc_26_itm_1 = 12'b0;
+    FRAME_for_slc_in_0_sva_itm_1 = 12'b0;
+    FRAME_for_acc_24_itm_1 = 13'b0;
+    exit_FRAME_for_lpi_1_dfm_3 = 1'b0;
+    exit_FRAME_for_lpi_1_dfm_2 = 1'b0;
+    exit_FRAME_lpi_1_dfm_1 = 1'b0;
+    FRAME_p_1_sva_1 = 19'b0;
+    FRAME_acc_2_psp_sva = 12'b0;
+    acc_imod_12_sva = 6'b0;
+    intensity_2_sg1_sva = 15'b0;
+    exit_FRAME_for_sva_1 = 1'b0;
+    i_6_sva_1 = 2'b0;
+    in_2_sva_1 = 16'b0;
+    in_0_sva_1 = 16'b0;
+    FRAME_for_slc_YMATRIX_rom_11_psp_sva = 1'b0;
+    ACC1_acc_125_psp_1_lpi_1_dfm = 12'b0;
+    acc_imod_20_lpi_1_dfm = 2'b0;
+    i_6_lpi_1_dfm = 2'b0;
+    ACC1_acc_125_psp_lpi_1_dfm = 12'b0;
+    regs_regs_1_sva_dfm = 90'b0;
+    regs_regs_0_sva_dfm = 90'b0;
+    acc_imod_7_lpi_1_dfm = 2'b0;
+    acc_imod_11_sva = 2'b0;
+    acc_imod_10_sva = 3'b0;
+    ACC1_acc_120_psp_sva = 3'b0;
+    ACC1_acc_113_psp_1_sva = 4'b0;
+    acc_10_psp_1_sva = 12'b0;
+    acc_imod_6_sva = 3'b0;
+    ACC1_acc_118_psp_sva = 3'b0;
+    ACC1_acc_110_psp_1_sva = 4'b0;
+    ACC1_acc_125_psp_sva = 12'b0;
+    acc_imod_3_sva = 2'b0;
+    acc_imod_2_sva = 3'b0;
+    ACC1_acc_116_psp_sva = 3'b0;
+    ACC1_acc_107_psp_1_sva = 4'b0;
+    acc_psp_1_sva = 12'b0;
+    acc_imod_24_sva = 2'b0;
+    acc_imod_22_sva = 3'b0;
+    ACC1_acc_120_psp_1_sva = 3'b0;
+    ACC1_acc_113_psp_2_sva = 4'b0;
+    acc_10_psp_2_sva = 12'b0;
+    acc_imod_20_sva = 2'b0;
+    acc_imod_18_sva = 3'b0;
+    ACC1_acc_118_psp_1_sva = 3'b0;
+    ACC1_acc_110_psp_2_sva = 4'b0;
+    ACC1_acc_125_psp_1_sva = 12'b0;
+    acc_imod_16_sva = 2'b0;
+    acc_imod_14_sva = 3'b0;
+    ACC1_acc_116_psp_1_sva = 3'b0;
+    ACC1_acc_107_psp_2_sva = 4'b0;
+    acc_psp_2_sva = 12'b0;
+    regs_regs_0_sva_1 = 90'b0;
+    exit_FRAME_for_lpi_1_dfm = 1'b0;
+    FRAME_p_1_lpi_1_dfm = 19'b0;
+    exit_FRAME_1_sva = 1'b0;
+    regs_regs_0_sva = 90'b0;
+    regs_regs_1_sva = 90'b0;
+    FRAME_p_1_lpi_1 = 19'b0;
+    vout_rsc_mgc_out_stdreg_d <= 30'b0;
+  end
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [14:0] readslicef_16_15_1;
+    input [15:0] vector;
+    reg [15:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_16_15_1 = tmp[14:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [6:0] signext_7_3;
+    input [2:0] vector;
+  begin
+    signext_7_3= {{4{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_2;
+    input [1:0] vector;
+  begin
+    signext_3_2= {{1{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] MUX_v_2_2_2;
+    input [3:0] inputs;
+    input [0:0] sel;
+    reg [1:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[3:2];
+      end
+      1'b1 : begin
+        result = inputs[1:0];
+      end
+      default : begin
+        result = inputs[3:2];
+      end
+    endcase
+    MUX_v_2_2_2 = result;
+  end
+  endfunction
+
+
+  function [11:0] MUX_v_12_2_2;
+    input [23:0] inputs;
+    input [0:0] sel;
+    reg [11:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[23:12];
+      end
+      1'b1 : begin
+        result = inputs[11:0];
+      end
+      default : begin
+        result = inputs[23:12];
+      end
+    endcase
+    MUX_v_12_2_2 = result;
+  end
+  endfunction
+
+
+  function [2:0] MUX_v_3_2_2;
+    input [5:0] inputs;
+    input [0:0] sel;
+    reg [2:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[5:3];
+      end
+      1'b1 : begin
+        result = inputs[2:0];
+      end
+      default : begin
+        result = inputs[5:3];
+      end
+    endcase
+    MUX_v_3_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_3_1_2;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 2;
+    readslicef_3_1_2 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_13_16 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2u_13_16 = {{3{vector[12]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_13_16 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_16 = {{3{vector[12]}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_6_8 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_8 = {{2{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_26_13 ;
+    input signed [25:0]  vector ;
+  begin
+    conv_s2s_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_12_6 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_6 = vector[5:0];
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_2_6 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_6 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_2_8 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_8 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_4_7 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_7 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_s2u_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2u_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_11_13 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_13 = {{2{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_9_11 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_11 = {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2s_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2s_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v8/cycle_mgc_ioport.v b/Sobel/sobel.v8/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v8/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v8/cycle_mgc_ioport_v2001.v b/Sobel/sobel.v8/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v8/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v8/cycle_set.tcl b/Sobel/sobel.v8/cycle_set.tcl
new file mode 100644
index 0000000..1b75cc6
--- /dev/null
+++ b/Sobel/sobel.v8/cycle_set.tcl
@@ -0,0 +1,316 @@
+
+# Loop constraints
+directive set /sobel/core/core:rlp CSTEPS_FROM {{. == 0}}
+directive set /sobel/core/core:rlp/main CSTEPS_FROM {{. == 3} {.. == 0}}
+
+# IO operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:io_read(vin:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:io_write(vout:rsc.d) CSTEPS_FROM {{.. == 2}}
+
+# Real operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:for:and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#133 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#132 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#136 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#138 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#135 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#134 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#137 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#107 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#139 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1-1:acc#116 CSTEPS_FROM {{.. == 1}}
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+directive set /sobel/core/core:rlp/main/ACC1:acc#325 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#305 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#304 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#317 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#303 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#302 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#316 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#324 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#328 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#332 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#301 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#300 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#315 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#299 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#298 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#314 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#323 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#297 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#296 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#313 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#295 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#312 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#322 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#327 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#311 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#308 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#321 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#331 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#335 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#338 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#340 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#19 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#320 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#326 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#329 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#333 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#337 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:mul#22 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#339 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#341 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC1:acc#342 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/ACC1:acc CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#6 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#5 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#8 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#7 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#9 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/acc#15 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#1 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#16 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#10 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#11 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#12 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#13 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#14 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#15 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#2 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#44 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#45 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#42 CSTEPS_FROM {{.. == 1}}
diff --git a/Sobel/sobel.v8/directives.tcl b/Sobel/sobel.v8/directives.tcl
new file mode 100644
index 0000000..504c4bb
--- /dev/null
+++ b/Sobel/sobel.v8/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
+go extract
diff --git a/Sobel/sobel.v8/messages.txt b/Sobel/sobel.v8/messages.txt
new file mode 100644
index 0000000..55837a4
--- /dev/null
+++ b/Sobel/sobel.v8/messages.txt
@@ -0,0 +1,253 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.17 seconds, memory usage 308128kB, peak memory usage 415668kB (SOL-9)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.cpp(128): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+
+# Messages from "go compile"
+
+Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'sobel' specified by directive (CIN-52)
+Synthesizing routine 'sobel' (CIN-13)
+Inlining routine 'sobel' (CIN-14)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Optimizing block '/sobel' ... (CIN-4)
+Inout port 'vin' is only used as an input. (OPT-10)
+Inout port 'vout' is only used as an output. (OPT-11)
+Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+Detected constant initialization of array 'in', optimizing loop 'RESET' (LOOP-12)
+Design 'sobel' was read (SOL-1)
+Optimizing partition '/sobel': (Total ops = 1035, Real ops = 214, Vars = 224) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1035, Real ops = 214, Vars = 222) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 993, Real ops = 206, Vars = 228) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 993, Real ops = 206, Vars = 230) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 993, Real ops = 206, Vars = 230) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 993, Real ops = 206, Vars = 228) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 937, Real ops = 205, Vars = 215) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 912, Real ops = 205, Vars = 214) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 912, Real ops = 205, Vars = 214) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 912, Real ops = 205, Vars = 216) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 912, Real ops = 205, Vars = 216) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 890, Real ops = 203, Vars = 258) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 39) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 670, Real ops = 125, Vars = 32) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 595, Real ops = 117, Vars = 31) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 592, Real ops = 117, Vars = 31) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 592, Real ops = 117, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 587, Real ops = 117, Vars = 36) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 584, Real ops = 117, Vars = 31) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 584, Real ops = 117, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 584, Real ops = 117, Vars = 31) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 584, Real ops = 117, Vars = 33) (SOL-10)
+Completed transformation 'compile' on solution 'sobel.v8': elapsed time 4.98 seconds, memory usage 300316kB, peak memory usage 415668kB (SOL-9)
+Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'sobel.v8' (SOL-8)
+Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+Loop '/sobel/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/sobel/core': (Total ops = 1539, Real ops = 290, Vars = 31) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 971, Real ops = 174, Vars = 40) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 970, Real ops = 174, Vars = 39) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 970, Real ops = 174, Vars = 39) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 973, Real ops = 174, Vars = 41) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 968, Real ops = 174, Vars = 41) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 939, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 939, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 939, Real ops = 187, Vars = 45) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 940, Real ops = 187, Vars = 41) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 940, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 940, Real ops = 187, Vars = 45) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 940, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 940, Real ops = 187, Vars = 45) (SOL-10)
+I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 48) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 43) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 45) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 45) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 40) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 45) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 932, Real ops = 187, Vars = 49) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 932, Real ops = 187, Vars = 44) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 913, Real ops = 192, Vars = 42) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 913, Real ops = 192, Vars = 47) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 913, Real ops = 192, Vars = 42) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 913, Real ops = 192, Vars = 47) (SOL-10)
+Design 'sobel' contains '439' real operations. (SOL-11)
+Optimizing partition '/sobel/core': (Total ops = 920, Real ops = 193, Vars = 45) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 919, Real ops = 193, Vars = 45) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 1354, Real ops = 245, Vars = 293) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 987, Real ops = 216, Vars = 83) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 986, Real ops = 216, Vars = 82) (SOL-10)
+Completed transformation 'architect' on solution 'sobel.v8': elapsed time 12.56 seconds, memory usage 300472kB, peak memory usage 415668kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'sobel.v8' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 6857.74, 0.00, 6857.74 (CRAAS-11)
+Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 6767.91, 0.00, 6767.91 (CRAAS-10)
+Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 6764.18, 0.00, 6764.18 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 6764.18, 0.00, 6764.18 (CRAAS-12)
+Completed transformation 'allocate' on solution 'sobel.v8': elapsed time 5.63 seconds, memory usage 300992kB, peak memory usage 415668kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'sobel.v8' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 1561, Real ops = 440, Vars = 122) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1551, Real ops = 439, Vars = 114) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 1542, Real ops = 440, Vars = 129) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 1433, Real ops = 426, Vars = 82) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 1422, Real ops = 425, Vars = 79) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1436, Real ops = 425, Vars = 91) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1427, Real ops = 425, Vars = 84) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 1424, Real ops = 425, Vars = 81) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 1423, Real ops = 425, Vars = 79) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1437, Real ops = 425, Vars = 91) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1428, Real ops = 425, Vars = 84) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 1423, Real ops = 425, Vars = 79) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1437, Real ops = 425, Vars = 91) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1428, Real ops = 425, Vars = 84) (SOL-10)
+Completed transformation 'schedule' on solution 'sobel.v8': elapsed time 6.38 seconds, memory usage 307280kB, peak memory usage 415668kB (SOL-9)
+Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'sobel.v8' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 1830, Real ops = 467, Vars = 1152) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1821, Real ops = 467, Vars = 1145) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 2601, Real ops = 461, Vars = 103) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 2592, Real ops = 461, Vars = 96) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+Completed transformation 'dpfsm' on solution 'sobel.v8': elapsed time 1.90 seconds, memory usage 307280kB, peak memory usage 415668kB (SOL-9)
+
+# Messages from "go extract"
+
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'sobel.v8' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 1495, Real ops = 470, Vars = 1492) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1486, Real ops = 470, Vars = 1485) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1480, Real ops = 469, Vars = 1477) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1471, Real ops = 469, Vars = 1470) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1480, Real ops = 469, Vars = 1477) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1471, Real ops = 469, Vars = 1470) (SOL-10)
+Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+Reassigned operation ACC1:acc#268:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,0,11) (ASG-1)
+Reassigned operation ACC1:acc#215:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,0,11) (ASG-1)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/sobel': (Total ops = 1480, Real ops = 469, Vars = 1477) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1471, Real ops = 469, Vars = 1470) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1402, Real ops = 457, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1393, Real ops = 457, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1402, Real ops = 457, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1393, Real ops = 457, Vars = 95) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 1402, Real ops = 457, Vars = 102) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 1393, Real ops = 457, Vars = 95) (SOL-10)
+Completed transformation 'extract' on solution 'sobel.v8': elapsed time 12.45 seconds, memory usage 308836kB, peak memory usage 415668kB (SOL-9)
diff --git a/Sobel/sobel.v8/reg_sharing.tcl b/Sobel/sobel.v8/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v8/reg_sharing.tcl
diff --git a/Sobel/sobel.v8/res_sharing.tcl b/Sobel/sobel.v8/res_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v8/res_sharing.tcl
diff --git a/Sobel/sobel.v8/rtl.rpt b/Sobel/sobel.v8/rtl.rpt
new file mode 100644
index 0000000..63494b5
--- /dev/null
+++ b/Sobel/sobel.v8/rtl.rpt
@@ -0,0 +1,1184 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 15:23:07 +0000 2016                      
+
+Solution Settings: sobel.v8
+  Current state: extract
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       444  921601     921600            0  1          
+    Design Total:                     444  921601     921600            0  0          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(1,0,1,0,2)                           2.319                       0.000      2.319 0.506          6           7 
+    mgc_add(10,0,10,0,11)                       11.241                       0.000     11.241 1.301          2           0 
+    mgc_add(10,0,10,1,11)                       11.000                       0.000     11.000 1.139          6           6 
+    mgc_add(10,1,10,1,11)                       11.000                       0.000     11.000 1.139          9           9 
+    mgc_add(11,0,10,0,11)                       12.236                       0.000     12.236 1.370          0           2 
+    mgc_add(11,0,11,1,13)                       12.000                       0.000     12.000 1.043          6           6 
+    mgc_add(11,1,11,1,12)                       12.000                       0.000     12.000 1.206          7           7 
+    mgc_add(12,1,12,1,13)                       13.000                       0.000     13.000 1.272          7           5 
+    mgc_add(13,0,12,1,13)                       14.000                       0.000     14.000 1.501          2           2 
+    mgc_add(13,0,13,0,13)                       14.215                       0.000     14.215 1.499          1           1 
+    mgc_add(16,0,13,1,16)                       17.000                       0.000     17.000 1.694          3           3 
+    mgc_add(16,0,16,0,16)                       17.189                       0.000     17.189 1.690          1           1 
+    mgc_add(19,0,2,1,19)                        20.000                       0.000     20.000 1.908          1           1 
+    mgc_add(2,0,1,0,2)                           3.315                       0.000      3.315 0.658          0           1 
+    mgc_add(2,0,1,0,3)                           3.315                       0.000      3.315 0.658          0           2 
+    mgc_add(2,0,2,0,3)                           3.311                       0.000      3.311 0.653         26          23 
+    mgc_add(2,0,2,1,4)                           3.000                       0.000      3.000 0.328         11          11 
+    mgc_add(3,0,3,0,4)                           4.302                       0.000      4.302 0.761         60          60 
+    mgc_add(3,0,3,1,5)                           4.000                       0.000      4.000 0.436         22          21 
+    mgc_add(3,1,2,1,4)                           4.000                       0.000      4.000 0.602          8           8 
+    mgc_add(4,0,4,0,5)                           5.293                       0.000      5.293 0.854         11          10 
+    mgc_add(4,0,4,1,6)                           5.000                       0.000      5.000 0.529         13          13 
+    mgc_add(4,1,4,1,5)                           5.000                       0.000      5.000 0.691          8           8 
+    mgc_add(5,0,5,0,6)                           6.285                       0.000      6.285 0.938          2           2 
+    mgc_add(5,0,5,1,7)                           6.000                       0.000      6.000 0.613         14          14 
+    mgc_add(6,0,6,0,7)                           7.276                       0.000      7.276 1.016          1           1 
+    mgc_add(6,0,6,1,8)                           7.000                       0.000      7.000 0.691          8           8 
+    mgc_add(7,0,7,1,9)                           8.000                       0.000      8.000 0.766         10          10 
+    mgc_add(8,0,8,1,10)                          9.000                       0.000      9.000 0.838         11          11 
+    mgc_add(9,0,8,0,10)                         10.254                       0.000     10.254 1.235          5           5 
+    mgc_add(9,0,8,1,10)                         10.000                       0.000     10.000 1.072          1           1 
+    mgc_and(1,2)                                 0.730                       0.000      0.730 0.263          0           3 
+    mgc_and(1,3)                                 1.054                       0.000      1.054 0.416          0           6 
+    mgc_and(19,2)                               13.867                       0.000     13.867 0.263          1           1 
+    mgc_and(2,2)                                 1.460                       0.000      1.460 0.263          2           1 
+    mgc_mul(2,0,12,1,13)                       330.000                       2.000     10.000 3.224          7           7 
+    mgc_mul(2,1,10,1,12)                       330.000                       2.000     10.000 3.087          6           6 
+    mgc_mul(3,0,6,0,9)                         330.250                       2.000     10.250 2.846          1           1 
+    mgc_mux(1,1,2)                               0.919                       0.000      0.919 0.369          2           1 
+    mgc_mux(10,2,4)                             22.259                       0.000     22.259 0.936          6           6 
+    mgc_mux(12,1,2)                             11.033                       0.000     11.033 0.369          2           2 
+    mgc_mux(16,1,2)                             14.711                       0.000     14.711 0.369          2           4 
+    mgc_mux(19,1,2)                             17.469                       0.000     17.469 0.369          1           1 
+    mgc_mux(2,1,2)                               1.839                       0.000      1.839 0.369          2           6 
+    mgc_mux(3,1,2)                               2.758                       0.000      2.758 0.369          4           2 
+    mgc_mux(30,1,2)                             27.583                       0.000     27.583 0.369          0           3 
+    mgc_mux(4,1,2)                               3.678                       0.000      3.678 0.369          2           0 
+    mgc_mux(90,1,2)                             82.748                       0.000     82.748 0.369          3           2 
+    mgc_nand(1,2)                                0.730                       0.000      0.730 0.268          0           9 
+    mgc_nor(1,2)                                 0.730                       0.000      0.730 0.263          0           2 
+    mgc_not(1)                                   0.000                       0.000      0.000 0.000          0          92 
+    mgc_not(10)                                  0.000                       0.000      0.000 0.000          0           9 
+    mgc_not(2)                                   0.000                       0.000      0.000 0.000          0           8 
+    mgc_not(3)                                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_or(1,2)                                  0.730                       0.000      0.730 0.268          0           2 
+    mgc_or(1,3)                                  1.054                       0.000      1.054 0.425          0           1 
+    mgc_or(10,2)                                 7.298                       0.000      7.298 0.268          1           1 
+    mgc_or(2,2)                                  1.460                       0.000      1.460 0.268          1           0 
+    mgc_or(6,2)                                  4.379                       0.000      4.379 0.268          1           1 
+    mgc_reg_pos(1,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           5 
+    mgc_reg_pos(12,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           5 
+    mgc_reg_pos(13,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(16,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(19,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(2,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           7 
+    mgc_reg_pos(3,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(30,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(90,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,90)                            0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(2,30)                         0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):            6772.333                      28.000   2292.000                              
+    
+  Area Scores
+                      Post-Scheduling   Post-DP & FSM Post-Assignment 
+    ----------------- --------------- --------------- ---------------
+    Total Area Score:   6764.2          6930.2          6772.3        
+    Total Reg:             0.0             0.0             0.0        
+                                                                      
+    DataPath:           6764.2 (100%)   6930.2 (100%)   6772.3 (100%) 
+      MUX:               474.7   (7%)    653.3   (9%)    497.6   (7%) 
+      FUNC:             6259.6  (93%)   6230.8  (90%)   6228.6  (92%) 
+      LOGIC:              29.9   (0%)     46.1   (1%)     46.1   (1%) 
+      BUFFER:              0.0             0.0             0.0        
+      MEM:                 0.0             0.0             0.0        
+      ROM:                 0.0             0.0             0.0        
+      REG:                 0.0             0.0             0.0        
+                                                                      
+    
+    FSM:                   0.0             0.0             0.0        
+      FSM-REG:             0.0             0.0             0.0        
+      FSM-COMB:            0.0             0.0             0.0        
+                                                                      
+    
+  Register-to-Variable Mappings
+    Register                         Size(bits) Gated Register CG Opt Done Variables                                             
+    -------------------------------- ---------- -------------- ----------- -----------------------------------------------------
+    regs.regs(0).sva                         90         Y                  regs.regs(0).sva                                      
+    regs.regs(1).sva                         90         Y                  regs.regs(1).sva                                      
+    regs.regs(2).lpi#1.dfm#1                 30         Y                  regs.regs(2).lpi#1.dfm#1                              
+    regs.regs(2).lpi#1.dfm.sg2               30         Y                  regs.regs(2).lpi#1.dfm.sg2                            
+    vout:rsc:mgc_out_stdreg.d                30         Y                  vout:rsc:mgc_out_stdreg.d                             
+    FRAME:p#1.lpi#1                          19         Y                  FRAME:p#1.lpi#1                                       
+    in(0).sva#1                              16         Y                  in(0).sva#1                                           
+    in(2).sva#1                              16         Y                  in(2).sva#1                                           
+    ACC1:acc#341.itm#1                       13         Y                  ACC1:acc#341.itm#1                                    
+    FRAME:for:acc#24.itm#1                   13         Y                  FRAME:for:acc#24.itm#1                                
+    ACC1:acc#125.psp#1.lpi#1.dfm             12         Y                  ACC1:acc#125.psp#1.lpi#1.dfm                          
+    ACC1:acc#125.psp.lpi#1.dfm               12         Y                  ACC1:acc#125.psp.lpi#1.dfm                            
+    FRAME:for:acc#26.itm#1                   12         Y                  FRAME:for:acc#26.itm#1                                
+    FRAME:for:slc(in(0).sva).itm#1           12         Y                  FRAME:for:slc(in(0).sva).itm#1                        
+    FRAME:for:slc(in(2).sva).itm#1           12         Y                  FRAME:for:slc(in(2).sva).itm#1                        
+    ACC1:acc#110.psp#1.lpi#1.dfm.sg1          3         Y                  ACC1:acc#110.psp#1.lpi#1.dfm.sg1                      
+    ACC1:acc#110.psp#2.lpi#1.dfm.sg1          3         Y                  ACC1:acc#110.psp#2.lpi#1.dfm.sg1                      
+    ACC1:acc#118.psp#1.lpi#1.dfm.sg1          2         Y                  ACC1:acc#118.psp#1.lpi#1.dfm.sg1                      
+    ACC1:acc#118.psp.lpi#1.dfm.sg1            2         Y                  ACC1:acc#118.psp.lpi#1.dfm.sg1                        
+    acc.imod#18.lpi#1.dfm.sg1                 2         Y                  acc.imod#18.lpi#1.dfm.sg1                             
+    acc.imod#20.lpi#1.dfm                     2         Y                  acc.imod#20.lpi#1.dfm                                 
+    acc.imod#6.lpi#1.dfm.sg1                  2         Y                  acc.imod#6.lpi#1.dfm.sg1                              
+    acc.imod#7.lpi#1.dfm                      2         Y                  acc.imod#7.lpi#1.dfm                                  
+    i#6.sva#1                                 2         Y                  i#6.sva#1                                             
+    exit:FRAME#1.sva                          1         Y                  exit:FRAME#1.sva                                      
+    exit:FRAME.lpi#1.dfm#1                    1         Y                  exit:FRAME.lpi#1.dfm#1                                
+    exit:FRAME:for.lpi#1.dfm#3                1         Y                  exit:FRAME:for.lpi#1.dfm#3                            
+    exit:FRAME:for.sva#1.st#1                 1         Y                  exit:FRAME:for.sva#1.st#1                             
+    main.stage_0#2                            1         Y                  main.stage_0#2                                        
+                                                                                                                                 
+    Total:                                  432            432           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  16.044071
+      Slack:      3.955929000000001
+      
+      Path                                             Startpoint                       Endpoint                                       Delay   Slack   
+      ------------------------------------------------ -------------------------------- ---------------------------------------------- ------- -------
+      1                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#1)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#1).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not#161                        mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not#161.itm                                                                                                    0.0000  0.0000  
+        sobel:core/ACC1:acc#153                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#153.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc#10                       mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc#10.psp#2.sva                                                                                                    0.0000  2.3449  
+        sobel:core/slc(acc#10.psp#2.sva)#17                                                                                            0.0000  2.3449  
+        sobel:core/slc(acc#10.psp#2.sva)#17.itm                                                                                        0.0000  2.3449  
+        sobel:core/conc#715                                                                                                            0.0000  2.3449  
+        sobel:core/conc#715.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#155                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#155.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#23                                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:slc#23.itm                                                                                                     0.0000  2.9974  
+        sobel:core/conc#714                                                                                                            0.0000  2.9974  
+        sobel:core/conc#714.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#157                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#157.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc#25                                                                                                         0.0000  3.7583  
+        sobel:core/ACC1:slc#25.itm                                                                                                     0.0000  3.7583  
+        sobel:core/ACC1-1:acc#113                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#113.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#113.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#113.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#717                                                                                                            0.0000  4.2869  
+        sobel:core/conc#717.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#159                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#159.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#27                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#27.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#120                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#120.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#120.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#120.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#149                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#149.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#709                                                                                                            0.0000  5.2670  
+        sobel:core/conc#709.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#160                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#160.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#28                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#22.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#22.sva)#2                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#22.sva)#2.itm                                                                                          0.0000  5.7029  
+        sobel:core/conc#708                                                                                                            0.0000  5.7029  
+        sobel:core/conc#708.itm                                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:acc#161                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#161.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#29                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#24.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#24.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#24.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand#2                       mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand#2.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:conc#607                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#607.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#774                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#774.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#274                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#274.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#80                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#80.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#280                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#280.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#284                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#284.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#287                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#287.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#290                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#290.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#292                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#292.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#294                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#294.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#124                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#124.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#267                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#267.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#124                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#124.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      2                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#17                                                                                               0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#17.itm                                                                                           0.0000  2.3449  
+        sobel:core/conc#735                                                                                                            0.0000  2.3449  
+        sobel:core/conc#735.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#135                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#135.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#7                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#7.itm                                                                                                      0.0000  2.9974  
+        sobel:core/conc#734                                                                                                            0.0000  2.9974  
+        sobel:core/conc#734.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#737                                                                                                            0.0000  4.2869  
+        sobel:core/conc#737.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#2                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#2.itm                                                                                          0.0000  5.7029  
+        sobel:core/conc#728                                                                                                            0.0000  5.7029  
+        sobel:core/conc#728.itm                                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      3                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#2)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#2).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not#162                        mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not#162.itm                                                                                                    0.0000  0.0000  
+        sobel:core/ACC1:acc#153                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#153.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc#10                       mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc#10.psp#2.sva                                                                                                    0.0000  2.3449  
+        sobel:core/slc(acc#10.psp#2.sva)#17                                                                                            0.0000  2.3449  
+        sobel:core/slc(acc#10.psp#2.sva)#17.itm                                                                                        0.0000  2.3449  
+        sobel:core/conc#715                                                                                                            0.0000  2.3449  
+        sobel:core/conc#715.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#155                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#155.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#23                                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:slc#23.itm                                                                                                     0.0000  2.9974  
+        sobel:core/conc#714                                                                                                            0.0000  2.9974  
+        sobel:core/conc#714.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#157                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#157.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc#25                                                                                                         0.0000  3.7583  
+        sobel:core/ACC1:slc#25.itm                                                                                                     0.0000  3.7583  
+        sobel:core/ACC1-1:acc#113                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#113.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#113.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#113.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#717                                                                                                            0.0000  4.2869  
+        sobel:core/conc#717.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#159                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#159.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#27                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#27.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#120                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#120.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#120.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#120.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#149                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#149.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#709                                                                                                            0.0000  5.2670  
+        sobel:core/conc#709.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#160                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#160.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#28                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#22.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#22.sva)#2                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#22.sva)#2.itm                                                                                          0.0000  5.7029  
+        sobel:core/conc#708                                                                                                            0.0000  5.7029  
+        sobel:core/conc#708.itm                                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:acc#161                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#161.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#29                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#24.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#24.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#24.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand#2                       mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand#2.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:conc#607                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#607.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#774                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#774.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#274                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#274.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#80                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#80.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#280                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#280.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#284                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#284.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#287                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#287.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#290                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#290.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#292                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#292.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#294                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#294.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#124                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#124.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#267                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#267.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#124                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#124.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      4                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#17                                                                                               0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#17.itm                                                                                           0.0000  2.3449  
+        sobel:core/conc#735                                                                                                            0.0000  2.3449  
+        sobel:core/conc#735.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#135                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#135.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#7                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#7.itm                                                                                                      0.0000  2.9974  
+        sobel:core/conc#734                                                                                                            0.0000  2.9974  
+        sobel:core/conc#734.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#737                                                                                                            0.0000  4.2869  
+        sobel:core/conc#737.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3.itm                                                                                          0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                       mgc_not_1                                                                       0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:conc#459                                                                                                       0.0000  5.7029  
+        sobel:core/ACC1:conc#459.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      5                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#7                                                                                                0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#7.itm                                                                                            0.0000  2.3449  
+        sobel:core/ACC1-1:not#107                      mgc_not_1                                                                       0.0000  2.3449  
+        sobel:core/ACC1-1:not#107.itm                                                                                                  0.0000  2.3449  
+        sobel:core/ACC1:conc#446                                                                                                       0.0000  2.3449  
+        sobel:core/ACC1:conc#446.itm                                                                                                   0.0000  2.3449  
+        sobel:core/ACC1:acc#135                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#135.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#7                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#7.itm                                                                                                      0.0000  2.9974  
+        sobel:core/conc#734                                                                                                            0.0000  2.9974  
+        sobel:core/conc#734.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#737                                                                                                            0.0000  4.2869  
+        sobel:core/conc#737.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3.itm                                                                                          0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                       mgc_not_1                                                                       0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:conc#459                                                                                                       0.0000  5.7029  
+        sobel:core/ACC1:conc#459.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      6                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#6                                                                                                0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#6.itm                                                                                            0.0000  2.3449  
+        sobel:core/conc#736                                                                                                            0.0000  2.3449  
+        sobel:core/conc#736.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#134                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#134.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#9                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#9.itm                                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:conc#450                                                                                                       0.0000  2.9974  
+        sobel:core/ACC1:conc#450.itm                                                                                                   0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#737                                                                                                            0.0000  4.2869  
+        sobel:core/conc#737.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3.itm                                                                                          0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                       mgc_not_1                                                                       0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:conc#459                                                                                                       0.0000  5.7029  
+        sobel:core/ACC1:conc#459.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      7                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#17                                                                                               0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#17.itm                                                                                           0.0000  2.3449  
+        sobel:core/conc#735                                                                                                            0.0000  2.3449  
+        sobel:core/conc#735.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#135                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#135.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#7                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#7.itm                                                                                                      0.0000  2.9974  
+        sobel:core/conc#734                                                                                                            0.0000  2.9974  
+        sobel:core/conc#734.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#4                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#4.itm                                                                                   0.0000  4.2869  
+        sobel:core/ACC1-1:not#133                      mgc_not_1                                                                       0.0000  4.2869  
+        sobel:core/ACC1-1:not#133.itm                                                                                                  0.0000  4.2869  
+        sobel:core/ACC1:conc#454                                                                                                       0.0000  4.2869  
+        sobel:core/ACC1:conc#454.itm                                                                                                   0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3.itm                                                                                          0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                       mgc_not_1                                                                       0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:conc#459                                                                                                       0.0000  5.7029  
+        sobel:core/ACC1:conc#459.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      8                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#6                                                                                                0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#6.itm                                                                                            0.0000  2.3449  
+        sobel:core/conc#736                                                                                                            0.0000  2.3449  
+        sobel:core/conc#736.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#134                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#134.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#9                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#9.itm                                                                                                      0.0000  2.9974  
+        sobel:core/ACC1:conc#450                                                                                                       0.0000  2.9974  
+        sobel:core/ACC1:conc#450.itm                                                                                                   0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#4                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#4.itm                                                                                   0.0000  4.2869  
+        sobel:core/ACC1-1:not#133                      mgc_not_1                                                                       0.0000  4.2869  
+        sobel:core/ACC1-1:not#133.itm                                                                                                  0.0000  4.2869  
+        sobel:core/ACC1:conc#454                                                                                                       0.0000  4.2869  
+        sobel:core/ACC1:conc#454.itm                                                                                                   0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3.itm                                                                                          0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                       mgc_not_1                                                                       0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:conc#459                                                                                                       0.0000  5.7029  
+        sobel:core/ACC1:conc#459.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      9                                                sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#7).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not                            mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not.itm                                                                                                        0.0000  0.0000  
+        sobel:core/ACC1:acc#133                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#133.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc                          mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc.psp#2.sva                                                                                                       0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#7                                                                                                0.0000  2.3449  
+        sobel:core/slc(acc.psp#2.sva)#7.itm                                                                                            0.0000  2.3449  
+        sobel:core/ACC1-1:not#107                      mgc_not_1                                                                       0.0000  2.3449  
+        sobel:core/ACC1-1:not#107.itm                                                                                                  0.0000  2.3449  
+        sobel:core/ACC1:conc#446                                                                                                       0.0000  2.3449  
+        sobel:core/ACC1:conc#446.itm                                                                                                   0.0000  2.3449  
+        sobel:core/ACC1:acc#135                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#135.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#7                                                                                                          0.0000  2.9974  
+        sobel:core/ACC1:slc#7.itm                                                                                                      0.0000  2.9974  
+        sobel:core/conc#734                                                                                                            0.0000  2.9974  
+        sobel:core/conc#734.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#137                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#137.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc                                                                                                            0.0000  3.7583  
+        sobel:core/ACC1:slc.itm                                                                                                        0.0000  3.7583  
+        sobel:core/ACC1-1:acc#107                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#107.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#4                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#107.psp#2.sva)#4.itm                                                                                   0.0000  4.2869  
+        sobel:core/ACC1-1:not#133                      mgc_not_1                                                                       0.0000  4.2869  
+        sobel:core/ACC1-1:not#133.itm                                                                                                  0.0000  4.2869  
+        sobel:core/ACC1:conc#454                                                                                                       0.0000  4.2869  
+        sobel:core/ACC1:conc#454.itm                                                                                                   0.0000  4.2869  
+        sobel:core/ACC1:acc#139                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#139.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#11                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#11.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#116                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#116.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#116.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#145                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#145.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#729                                                                                                            0.0000  5.2670  
+        sobel:core/conc#729.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#140                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#140.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#12                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#14.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#14.sva)#3.itm                                                                                          0.0000  5.7029  
+        sobel:core/ACC1-1:not#25                       mgc_not_1                                                                       0.0000  5.7029  
+        sobel:core/ACC1-1:not#25.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:conc#459                                                                                                       0.0000  5.7029  
+        sobel:core/ACC1:conc#459.itm                                                                                                   0.0000  5.7029  
+        sobel:core/ACC1:acc#141                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#141.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#13                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#16.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#16.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand                         mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand.itm                                                                                                     0.0000  6.4067  
+        sobel:core/ACC1:conc#577                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#577.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#753                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#753.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#221                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#221.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#66                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#66.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#227                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#227.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#231                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#231.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#234                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#234.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#237                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#237.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#239                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#239.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#241                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#241.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#122                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#122.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#214                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#214.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#122                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#122.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      10                                               sobel:core/vin:rsc:mgc_in_wire.d sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1) 16.0441 3.9559  
+                                                                                                                                                       
+        Instance                                       Component                                                                       Delta   Delay   
+        --------                                       ---------                                                                       -----   -----   
+        sobel:core/vin:rsc:mgc_in_wire.d                                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3)                                                                                             0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva#3).itm                                                                                         0.0000  0.0000  
+        sobel:core/ACC1:not#163                        mgc_not_10                                                                      0.0000  0.0000  
+        sobel:core/ACC1:not#163.itm                                                                                                    0.0000  0.0000  
+        sobel:core/ACC1:acc#152                        mgc_add_10_1_10_1_11                                                            1.1389  1.1389  
+        sobel:core/ACC1:acc#152.itm                                                                                                    0.0000  1.1389  
+        sobel:core/ACC1-1:acc#10                       mgc_add_11_1_11_1_12                                                            1.2059  2.3449  
+        sobel:core/acc#10.psp#2.sva                                                                                                    0.0000  2.3449  
+        sobel:core/slc(acc#10.psp#2.sva)#17                                                                                            0.0000  2.3449  
+        sobel:core/slc(acc#10.psp#2.sva)#17.itm                                                                                        0.0000  2.3449  
+        sobel:core/conc#715                                                                                                            0.0000  2.3449  
+        sobel:core/conc#715.itm                                                                                                        0.0000  2.3449  
+        sobel:core/ACC1:acc#155                        mgc_add_2_0_2_0_3                                                               0.6525  2.9974  
+        sobel:core/ACC1:acc#155.itm                                                                                                    0.0000  2.9974  
+        sobel:core/ACC1:slc#23                                                                                                         0.0000  2.9974  
+        sobel:core/ACC1:slc#23.itm                                                                                                     0.0000  2.9974  
+        sobel:core/conc#714                                                                                                            0.0000  2.9974  
+        sobel:core/conc#714.itm                                                                                                        0.0000  2.9974  
+        sobel:core/ACC1:acc#157                        mgc_add_3_0_3_0_4                                                               0.7609  3.7583  
+        sobel:core/ACC1:acc#157.itm                                                                                                    0.0000  3.7583  
+        sobel:core/ACC1:slc#25                                                                                                         0.0000  3.7583  
+        sobel:core/ACC1:slc#25.itm                                                                                                     0.0000  3.7583  
+        sobel:core/ACC1-1:acc#113                      mgc_add_4_0_4_1_6                                                               0.5286  4.2869  
+        sobel:core/ACC1:acc#113.psp#2.sva                                                                                              0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#113.psp#2.sva)#3                                                                                       0.0000  4.2869  
+        sobel:core/slc(ACC1:acc#113.psp#2.sva)#3.itm                                                                                   0.0000  4.2869  
+        sobel:core/conc#717                                                                                                            0.0000  4.2869  
+        sobel:core/conc#717.itm                                                                                                        0.0000  4.2869  
+        sobel:core/ACC1:acc#159                        mgc_add_2_0_2_0_3                                                               0.6525  4.9394  
+        sobel:core/ACC1:acc#159.itm                                                                                                    0.0000  4.9394  
+        sobel:core/ACC1:slc#27                                                                                                         0.0000  4.9394  
+        sobel:core/ACC1:slc#27.itm                                                                                                     0.0000  4.9394  
+        sobel:core/ACC1-1:acc#120                      mgc_add_2_0_2_1_4                                                               0.3276  5.2670  
+        sobel:core/ACC1:acc#120.psp#1.sva                                                                                              0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#120.psp#1.sva)                                                                                         0.0000  5.2670  
+        sobel:core/slc(ACC1:acc#120.psp#1.sva).itm                                                                                     0.0000  5.2670  
+        sobel:core/ACC1-1:not#149                      mgc_not_2                                                                       0.0000  5.2670  
+        sobel:core/ACC1-1:not#149.itm                                                                                                  0.0000  5.2670  
+        sobel:core/conc#709                                                                                                            0.0000  5.2670  
+        sobel:core/conc#709.itm                                                                                                        0.0000  5.2670  
+        sobel:core/ACC1:acc#160                        mgc_add_3_0_3_1_5                                                               0.4359  5.7029  
+        sobel:core/ACC1:acc#160.itm                                                                                                    0.0000  5.7029  
+        sobel:core/ACC1:slc#28                                                                                                         0.0000  5.7029  
+        sobel:core/acc.imod#22.sva                                                                                                     0.0000  5.7029  
+        sobel:core/slc(acc.imod#22.sva)#2                                                                                              0.0000  5.7029  
+        sobel:core/slc(acc.imod#22.sva)#2.itm                                                                                          0.0000  5.7029  
+        sobel:core/conc#708                                                                                                            0.0000  5.7029  
+        sobel:core/conc#708.itm                                                                                                        0.0000  5.7029  
+        sobel:core/ACC1:acc#161                        mgc_add_3_0_3_1_5                                                               0.4359  6.1389  
+        sobel:core/ACC1:acc#161.itm                                                                                                    0.0000  6.1389  
+        sobel:core/ACC1:slc#29                                                                                                         0.0000  6.1389  
+        sobel:core/acc.imod#24.sva                                                                                                     0.0000  6.1389  
+        sobel:core/slc(acc.imod#24.sva)#2                                                                                              0.0000  6.1389  
+        sobel:core/slc(acc.imod#24.sva)#2.itm                                                                                          0.0000  6.1389  
+        sobel:core/ACC1-1:nand#2                       mgc_nand_1_2                                                                    0.2679  6.4067  
+        sobel:core/ACC1-1:nand#2.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:conc#607                                                                                                       0.0000  6.4067  
+        sobel:core/ACC1:conc#607.itm                                                                                                   0.0000  6.4067  
+        sobel:core/ACC1:exs#774                                                                                                        0.0000  6.4067  
+        sobel:core/ACC1:exs#774.itm                                                                                                    0.0000  6.4067  
+        sobel:core/ACC1:acc#274                        mgc_add_3_0_3_0_4                                                               0.7609  7.1676  
+        sobel:core/ACC1:acc#274.itm                                                                                                    0.0000  7.1676  
+        sobel:core/ACC1:slc#80                                                                                                         0.0000  7.1676  
+        sobel:core/ACC1:slc#80.itm                                                                                                     0.0000  7.1676  
+        sobel:core/ACC1:acc#280                        mgc_add_3_0_3_0_4                                                               0.7609  7.9285  
+        sobel:core/ACC1:acc#280.itm                                                                                                    0.0000  7.9285  
+        sobel:core/ACC1:acc#284                        mgc_add_4_0_4_0_5                                                               0.8536  8.7821  
+        sobel:core/ACC1:acc#284.itm                                                                                                    0.0000  8.7821  
+        sobel:core/ACC1:acc#287                        mgc_add_6_0_6_1_8                                                               0.6912  9.4733  
+        sobel:core/ACC1:acc#287.itm                                                                                                    0.0000  9.4733  
+        sobel:core/ACC1:acc#290                        mgc_add_8_0_8_1_10                                                              0.8382  10.3115 
+        sobel:core/ACC1:acc#290.itm                                                                                                    0.0000  10.3115 
+        sobel:core/ACC1:acc#292                        mgc_add_9_0_8_0_10                                                              1.2349  11.5464 
+        sobel:core/ACC1:acc#292.itm                                                                                                    0.0000  11.5464 
+        sobel:core/ACC1:acc#294                        mgc_add_10_0_10_1_11                                                            1.1389  12.6854 
+        sobel:core/ACC1:acc#294.itm                                                                                                    0.0000  12.6854 
+        sobel:core/ACC1-1:acc#124                      mgc_add_11_0_11_1_13                                                            1.0435  13.7288 
+        sobel:core/ACC1-1:acc#124.itm                                                                                                  0.0000  13.7288 
+        sobel:core/ACC1:acc#267                        mgc_add_11_0_11_1_13                                                            1.0435  14.7723 
+        sobel:core/ACC1:acc#267.itm                                                                                                    0.0000  14.7723 
+        sobel:core/ACC1-3:acc#124                      mgc_add_12_1_12_1_13                                                            1.2718  16.0441 
+        sobel:core/ACC1-3:acc#124.itm                                                                                                  0.0000  16.0441 
+        sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1) mgc_reg_pos_12_1_0_0_0_1_1                                                      0.0000  16.0441 
+                                                                                                                                                       
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                         Port                                   Slack (Delay) Messages 
+      ------------------------------------------------ ------------------------------------ ------- ------- --------
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)        mux.itm                               4.7285 15.2715          
+      sobel:core/reg(in(2).sva#1)                      mux#1.itm                            17.5676  2.4324          
+      sobel:core/reg(ACC1:acc#341.itm#1)               ACC1:acc#341.itm                      4.1682 15.8318          
+      sobel:core/reg(in(0).sva#1)                      mux#2.itm                            17.5676  2.4324          
+      sobel:core/reg(exit:FRAME:for.sva#1.st#1)        FRAME:for:not#7.itm                  18.4843  1.5157          
+      sobel:core/reg(FRAME:for:acc#26.itm#1)           FRAME:for:acc#26.itm                 12.8675  7.1325          
+      sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1)   ACC1-3:acc#124.itm                    3.9559 16.0441          
+      sobel:core/reg(exit:FRAME:for.lpi#1.dfm#3)       exit:FRAME:for.lpi#1.dfm#4           12.6737  7.3263          
+      sobel:core/reg(FRAME:for:acc#24.itm#1)           FRAME:for:acc#24.itm                 12.5726  7.4274          
+      sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1)   ACC1-3:acc#122.itm                    3.9559 16.0441          
+      sobel:core/reg(i#6.sva#1)                        i#6.sva#2                            17.8528  2.1472          
+      sobel:core/reg(exit:FRAME#1.sva)                 FRAME:and.itm                        16.3597  3.6403          
+      sobel:core/reg(main.stage_0#2)                   Cn1_1#2                              20.0000  0.0000          
+      sobel:core/reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1) ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0  6.4362 13.5638          
+      sobel:core/reg(ACC1:acc#125.psp.lpi#1.dfm)       ACC1:acc#125.psp.lpi#1.dfm:mx0        6.3282 13.6718          
+      sobel:core/reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)   ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0    7.7867 12.2133          
+      sobel:core/reg(regs.regs(2).lpi#1.dfm.sg2)       regs.regs(2).lpi#1.dfm.sg2:mx0       12.8675  7.1325          
+      sobel:core/reg(regs.regs(2).lpi#1.dfm#1)         regs.regs(2).lpi#1.dfm#1:mx0         12.5726  7.4274          
+      sobel:core/reg(acc.imod#7.lpi#1.dfm)             acc.imod#7.lpi#1.dfm:mx0              4.1682 15.8318          
+      sobel:core/reg(acc.imod#6.lpi#1.dfm.sg1)         acc.imod#6.lpi#1.dfm.sg1:mx0          5.0202 14.9798          
+      sobel:core/reg(regs.regs(1).sva)                 regs.regs(1).sva.dfm:mx0             12.5726  7.4274          
+      sobel:core/reg(regs.regs(0).sva)                 regs.regs(0).sva.dfm:mx0             12.5726  7.4274          
+      sobel:core/reg(exit:FRAME.lpi#1.dfm#1)           exit:FRAME.lpi#1.dfm#1:mx0           16.3597  3.6403          
+      sobel:core/reg(ACC1:acc#125.psp#1.lpi#1.dfm)     ACC1:acc#125.psp#1.lpi#1.dfm:mx0      6.3282 13.6718          
+      sobel:core/reg(acc.imod#18.lpi#1.dfm.sg1)        acc.imod#18.lpi#1.dfm.sg1:mx0         5.0202 14.9798          
+      sobel:core/reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1) ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0  6.4362 13.5638          
+      sobel:core/reg(acc.imod#20.lpi#1.dfm)            acc.imod#20.lpi#1.dfm:mx0             4.9112 15.0888          
+      sobel:core/reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1) ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0  7.8794 12.1206          
+      sobel:core/reg(FRAME:p#1.lpi#1)                  mux#18.itm                           17.4604  2.5396          
+      sobel                                            vout:rsc.z                           20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                   19     1 
+    -                   16     4 
+    -                   13    14 
+    -                   12     7 
+    -                   11    17 
+    -                   10    17 
+    -                    9    10 
+    -                    8     8 
+    -                    7    15 
+    -                    6    15 
+    -                    5    39 
+    -                    4    79 
+    -                    3    25 
+    -                    2     8 
+    and                          
+    -                    3     6 
+    -                    2     5 
+    mul                          
+    -                   13     7 
+    -                   12     6 
+    -                    9     1 
+    mux                          
+    -                    2     6 
+    -                    1    21 
+    nand                         
+    -                    2     9 
+    nor                          
+    -                    2     2 
+    not                          
+    -                   10     9 
+    -                    3     4 
+    -                    2     8 
+    -                    1    92 
+    or                           
+    -                    3     1 
+    -                    2     4 
+    read_port                    
+    -                   90     1 
+    reg                          
+    -                   90     2 
+    -                   30     3 
+    -                   19     1 
+    -                   16     2 
+    -                   13     2 
+    -                   12     5 
+    -                    3     2 
+    -                    2     7 
+    -                    1     5 
+    write_port                   
+    -                   30     1 
+    
+  End of Report
diff --git a/Sobel/sobel.v8/rtl.v b/Sobel/sobel.v8/rtl.v
new file mode 100644
index 0000000..5be2f78
--- /dev/null
+++ b/Sobel/sobel.v8/rtl.v
@@ -0,0 +1,1557 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 15:23:08 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [1:0] acc_imod_7_lpi_1_dfm;
+  reg [11:0] ACC1_acc_125_psp_lpi_1_dfm;
+  reg [1:0] acc_imod_20_lpi_1_dfm;
+  reg [11:0] ACC1_acc_125_psp_1_lpi_1_dfm;
+  reg [15:0] in_0_sva_1;
+  reg [15:0] in_2_sva_1;
+  reg [1:0] i_6_sva_1;
+  reg exit_FRAME_lpi_1_dfm_1;
+  reg exit_FRAME_for_lpi_1_dfm_3;
+  reg [12:0] FRAME_for_acc_24_itm_1;
+  wire [14:0] nl_FRAME_for_acc_24_itm_1;
+  reg [11:0] FRAME_for_slc_in_0_sva_itm_1;
+  wire [14:0] nl_FRAME_for_slc_in_0_sva_itm_1;
+  reg [11:0] FRAME_for_acc_26_itm_1;
+  wire [13:0] nl_FRAME_for_acc_26_itm_1;
+  reg [11:0] FRAME_for_slc_in_2_sva_itm_1;
+  wire [14:0] nl_FRAME_for_slc_in_2_sva_itm_1;
+  reg [12:0] ACC1_acc_341_itm_1;
+  wire [14:0] nl_ACC1_acc_341_itm_1;
+  reg exit_FRAME_for_sva_1_st_1;
+  reg main_stage_0_2;
+  reg [1:0] acc_imod_6_lpi_1_dfm_sg1;
+  reg [29:0] regs_regs_2_lpi_1_dfm_sg2;
+  reg [29:0] regs_regs_2_lpi_1_dfm_1;
+  reg [1:0] ACC1_acc_118_psp_lpi_1_dfm_sg1;
+  reg [2:0] ACC1_acc_110_psp_1_lpi_1_dfm_sg1;
+  reg [1:0] acc_imod_18_lpi_1_dfm_sg1;
+  reg [1:0] ACC1_acc_118_psp_1_lpi_1_dfm_sg1;
+  reg [2:0] ACC1_acc_110_psp_2_lpi_1_dfm_sg1;
+  wire and_cse;
+  wire exit_FRAME_for_lpi_1_dfm_4;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+  wire [11:0] FRAME_acc_2_psp_sva;
+  wire [13:0] nl_FRAME_acc_2_psp_sva;
+  wire [5:0] acc_imod_12_sva;
+  wire [7:0] nl_acc_imod_12_sva;
+  wire [15:0] in_2_sva_3;
+  wire [16:0] nl_in_2_sva_3;
+  wire [15:0] in_0_sva_3;
+  wire [16:0] nl_in_0_sva_3;
+  wire [1:0] i_6_sva_2;
+  wire [2:0] nl_i_6_sva_2;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire [2:0] ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0;
+  wire [11:0] ACC1_acc_125_psp_lpi_1_dfm_mx0;
+  wire [1:0] ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0;
+  wire [29:0] regs_regs_2_lpi_1_dfm_sg2_mx0;
+  wire [29:0] regs_regs_2_lpi_1_dfm_1_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire [1:0] acc_imod_7_lpi_1_dfm_mx0;
+  wire [1:0] acc_imod_6_lpi_1_dfm_sg1_mx0;
+  wire [2:0] ACC1_acc_118_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_118_psp_1_sva;
+  wire [11:0] ACC1_acc_125_psp_1_sva;
+  wire [12:0] nl_ACC1_acc_125_psp_1_sva;
+  wire [11:0] ACC1_acc_125_psp_sva;
+  wire [12:0] nl_ACC1_acc_125_psp_sva;
+  wire [2:0] ACC1_acc_118_psp_sva;
+  wire [3:0] nl_ACC1_acc_118_psp_sva;
+  wire [11:0] acc_10_psp_1_sva;
+  wire [12:0] nl_acc_10_psp_1_sva;
+  wire [3:0] ACC1_acc_113_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_113_psp_1_sva;
+  wire [2:0] ACC1_acc_120_psp_sva;
+  wire [3:0] nl_ACC1_acc_120_psp_sva;
+  wire [2:0] ACC1_acc_250_cse;
+  wire [3:0] nl_ACC1_acc_250_cse;
+  wire [11:0] acc_10_psp_2_sva;
+  wire [12:0] nl_acc_10_psp_2_sva;
+  wire [3:0] ACC1_acc_113_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_113_psp_2_sva;
+  wire [2:0] ACC1_acc_120_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_120_psp_1_sva;
+  wire [2:0] ACC1_acc_277_cse;
+  wire [3:0] nl_ACC1_acc_277_cse;
+  wire [11:0] acc_psp_1_sva;
+  wire [12:0] nl_acc_psp_1_sva;
+  wire [3:0] ACC1_acc_107_psp_1_sva;
+  wire [4:0] nl_ACC1_acc_107_psp_1_sva;
+  wire [2:0] ACC1_acc_116_psp_sva;
+  wire [3:0] nl_ACC1_acc_116_psp_sva;
+  wire [2:0] ACC1_acc_197_cse;
+  wire [3:0] nl_ACC1_acc_197_cse;
+  wire [11:0] acc_psp_2_sva;
+  wire [12:0] nl_acc_psp_2_sva;
+  wire [3:0] ACC1_acc_107_psp_2_sva;
+  wire [4:0] nl_ACC1_acc_107_psp_2_sva;
+  wire [2:0] ACC1_acc_116_psp_1_sva;
+  wire [3:0] nl_ACC1_acc_116_psp_1_sva;
+  wire [2:0] ACC1_acc_224_cse;
+  wire [3:0] nl_ACC1_acc_224_cse;
+  wire exit_FRAME_lpi_1_dfm_1_mx0;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [11:0] ACC1_acc_125_psp_1_lpi_1_dfm_mx0;
+  wire [1:0] acc_imod_18_lpi_1_dfm_sg1_mx0;
+  wire [2:0] ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0;
+  wire [1:0] acc_imod_20_lpi_1_dfm_mx0;
+  wire [1:0] ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0;
+  wire FRAME_for_nor_cse;
+  wire [15:0] ACC1_acc_itm;
+  wire [17:0] nl_ACC1_acc_itm;
+  wire [3:0] ACC1_acc_150_itm;
+  wire [4:0] nl_ACC1_acc_150_itm;
+  wire [4:0] ACC1_acc_148_itm;
+  wire [5:0] nl_ACC1_acc_148_itm;
+  wire [4:0] ACC1_acc_176_itm;
+  wire [5:0] nl_ACC1_acc_176_itm;
+  wire [3:0] ACC1_acc_178_itm;
+  wire [4:0] nl_ACC1_acc_178_itm;
+  wire [2:0] ACC1_acc_188_itm;
+  wire [3:0] nl_ACC1_acc_188_itm;
+  wire [2:0] ACC1_acc_161_itm;
+  wire [3:0] nl_ACC1_acc_161_itm;
+  wire [3:0] ACC1_acc_160_itm;
+  wire [4:0] nl_ACC1_acc_160_itm;
+  wire [3:0] ACC1_acc_187_itm;
+  wire [4:0] nl_ACC1_acc_187_itm;
+  wire [2:0] ACC1_acc_170_itm;
+  wire [3:0] nl_ACC1_acc_170_itm;
+  wire [2:0] ACC1_acc_141_itm;
+  wire [3:0] nl_ACC1_acc_141_itm;
+  wire [3:0] ACC1_acc_140_itm;
+  wire [4:0] nl_ACC1_acc_140_itm;
+  wire [3:0] ACC1_acc_169_itm;
+  wire [4:0] nl_ACC1_acc_169_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_3_itm;
+
+  wire[15:0] FRAME_for_mux_12_nl;
+  wire[15:0] FRAME_for_mux_11_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_2_psp_sva = (conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(ACC1_acc_itm[14:13])
+      * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_itm[12:10])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_itm[9:4]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_12_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_12_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_12_sva[5:3])) , (~ (acc_imod_12_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_12_sva[4:3])) + conv_u2u_3_5(~ (ACC1_acc_itm[9:7])))
+      + ({4'b1001 , (acc_imod_12_sva[5])}))))) + conv_u2u_11_12(signext_11_9({(ACC1_acc_itm[15])
+      , 3'b0 , (signext_3_1(ACC1_acc_itm[15])) , 1'b0 , (ACC1_acc_itm[15])}));
+  assign FRAME_acc_2_psp_sva = nl_FRAME_acc_2_psp_sva[11:0];
+  assign nl_ACC1_acc_itm = (in_2_sva_3 + conv_s2s_13_16(ACC1_acc_341_itm_1)) + in_0_sva_3;
+  assign ACC1_acc_itm = nl_ACC1_acc_itm[15:0];
+  assign nl_acc_imod_12_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_itm[9:7])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~ (ACC1_acc_itm[15]))
+      , 1'b1 , (~ (ACC1_acc_itm[15]))}) + conv_u2u_2_4(ACC1_acc_itm[14:13]))) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_itm[3:1])
+      + conv_u2u_3_4(~ (ACC1_acc_itm[6:4])))) + 6'b101011;
+  assign acc_imod_12_sva = nl_acc_imod_12_sva[5:0];
+  assign FRAME_for_mux_12_nl = MUX_v_16_2_2({in_2_sva_1 , ({{4{FRAME_for_slc_in_2_sva_itm_1[11]}},
+      FRAME_for_slc_in_2_sva_itm_1})}, exit_FRAME_for_lpi_1_dfm_3);
+  assign nl_in_2_sva_3 = conv_s2u_12_16(FRAME_for_acc_26_itm_1) + (FRAME_for_mux_12_nl);
+  assign in_2_sva_3 = nl_in_2_sva_3[15:0];
+  assign FRAME_for_mux_11_nl = MUX_v_16_2_2({in_0_sva_1 , ({{4{FRAME_for_slc_in_0_sva_itm_1[11]}},
+      FRAME_for_slc_in_0_sva_itm_1})}, exit_FRAME_for_lpi_1_dfm_3);
+  assign nl_in_0_sva_3 = conv_s2u_13_16(FRAME_for_acc_24_itm_1) + (FRAME_for_mux_11_nl);
+  assign in_0_sva_3 = nl_in_0_sva_3[15:0];
+  assign nl_FRAME_for_acc_itm = i_6_sva_2 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  assign exit_FRAME_for_lpi_1_dfm_4 = exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva;
+  assign nl_i_6_sva_2 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_2 = nl_i_6_sva_2[1:0];
+  assign i_6_lpi_1_dfm = i_6_sva_1 & (signext_2_1(~ exit_FRAME_for_lpi_1_dfm_4));
+  assign ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0 = MUX_v_3_2_2({(ACC1_acc_176_itm[4:2])
+      , ACC1_acc_110_psp_1_lpi_1_dfm_sg1}, and_cse);
+  assign ACC1_acc_125_psp_lpi_1_dfm_mx0 = MUX_v_12_2_2({ACC1_acc_125_psp_sva , ACC1_acc_125_psp_lpi_1_dfm},
+      and_cse);
+  assign ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_118_psp_sva[2:1])
+      , ACC1_acc_118_psp_lpi_1_dfm_sg1}, and_cse);
+  assign regs_regs_2_lpi_1_dfm_sg2_mx0 = MUX_v_30_2_2({(regs_regs_1_sva[89:60]) ,
+      regs_regs_2_lpi_1_dfm_sg2}, and_cse);
+  assign regs_regs_2_lpi_1_dfm_1_mx0 = MUX_v_30_2_2({(regs_regs_1_sva[29:0]) , regs_regs_2_lpi_1_dfm_1},
+      and_cse);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_cse);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_cse);
+  assign acc_imod_7_lpi_1_dfm_mx0 = MUX_v_2_2_2({(readslicef_3_2_1((({1'b1 , (ACC1_acc_178_itm[1])
+      , 1'b1}) + conv_u2s_2_3({(~ (ACC1_acc_178_itm[2])) , (~ (ACC1_acc_178_itm[3]))}))))
+      , acc_imod_7_lpi_1_dfm}, and_cse);
+  assign acc_imod_6_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_178_itm[3:2]) , acc_imod_6_lpi_1_dfm_sg1},
+      and_cse);
+  assign nl_ACC1_acc_150_itm = conv_s2s_3_4({(~ (ACC1_acc_118_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_118_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_150_itm = nl_ACC1_acc_150_itm[3:0];
+  assign nl_ACC1_acc_118_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_148_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_148_itm[2])) , (ACC1_acc_148_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_148_itm[4]));
+  assign ACC1_acc_118_psp_1_sva = nl_ACC1_acc_118_psp_1_sva[2:0];
+  assign nl_ACC1_acc_148_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_125_psp_1_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_1_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_1_sva[2])) , (~ (ACC1_acc_125_psp_1_sva[6]))}))))
+      , (~ (ACC1_acc_125_psp_1_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_1_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_1_sva[4])) , (ACC1_acc_125_psp_1_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_125_psp_1_sva[11:10])) , (ACC1_acc_125_psp_1_sva[7])}))))
+      , (ACC1_acc_125_psp_1_sva[9])});
+  assign ACC1_acc_148_itm = nl_ACC1_acc_148_itm[4:0];
+  assign nl_ACC1_acc_125_psp_1_sva = conv_s2u_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[39:30]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[49:40]))) + conv_s2u_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[59:50])) + 11'b11);
+  assign ACC1_acc_125_psp_1_sva = nl_ACC1_acc_125_psp_1_sva[11:0];
+  assign nl_ACC1_acc_176_itm = conv_s2s_4_5({(readslicef_4_3_1((({2'b10 , (~ (ACC1_acc_125_psp_sva[0]))
+      , 1'b1}) + conv_u2s_3_4({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_sva[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_sva[2])) , (~ (ACC1_acc_125_psp_sva[6]))}))))
+      , (~ (ACC1_acc_125_psp_sva[8]))})))) , 1'b1}) + ({(readslicef_5_4_1((conv_u2s_3_5({(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_125_psp_sva[3])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_125_psp_sva[4])) , (ACC1_acc_125_psp_sva[5])}))))
+      , 1'b1}) + conv_s2s_3_5({(~ (ACC1_acc_125_psp_sva[11:10])) , (ACC1_acc_125_psp_sva[7])}))))
+      , (ACC1_acc_125_psp_sva[9])});
+  assign ACC1_acc_176_itm = nl_ACC1_acc_176_itm[4:0];
+  assign nl_ACC1_acc_125_psp_sva = conv_s2u_11_12(conv_s2s_10_11(regs_regs_1_sva[49:40])
+      + conv_s2s_10_11(regs_regs_1_sva[39:30])) + conv_s2u_10_12(regs_regs_1_sva[59:50]);
+  assign ACC1_acc_125_psp_sva = nl_ACC1_acc_125_psp_sva[11:0];
+  assign nl_ACC1_acc_118_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_176_itm[1])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_176_itm[2])) , (ACC1_acc_176_itm[3])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_176_itm[4]));
+  assign ACC1_acc_118_psp_sva = nl_ACC1_acc_118_psp_sva[2:0];
+  assign nl_ACC1_acc_178_itm = conv_s2s_3_4({(~ (ACC1_acc_118_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_118_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_178_itm = nl_ACC1_acc_178_itm[3:0];
+  assign nl_acc_10_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_1_sva[79:70])
+      + conv_s2s_10_11(regs_regs_1_sva[69:60])) + conv_s2s_10_12(regs_regs_1_sva[89:80]);
+  assign acc_10_psp_1_sva = nl_acc_10_psp_1_sva[11:0];
+  assign nl_ACC1_acc_113_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_10_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_10_psp_1_sva[1]))
+      , (acc_10_psp_1_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_10_psp_1_sva[0])
+      , (acc_10_psp_1_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_1_sva[3])) , (~ (acc_10_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_1_sva[5])) , (acc_10_psp_1_sva[6])}))))
+      , (~ (acc_10_psp_1_sva[9]))}))));
+  assign ACC1_acc_113_psp_1_sva = nl_ACC1_acc_113_psp_1_sva[3:0];
+  assign nl_ACC1_acc_120_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_113_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_113_psp_1_sva[1])) , (ACC1_acc_113_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_113_psp_1_sva[3]));
+  assign ACC1_acc_120_psp_sva = nl_ACC1_acc_120_psp_sva[2:0];
+  assign nl_ACC1_acc_250_cse = conv_u2u_2_3(signext_2_1(acc_10_psp_1_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_10_psp_1_sva[11]));
+  assign ACC1_acc_250_cse = nl_ACC1_acc_250_cse[2:0];
+  assign nl_ACC1_acc_188_itm = ({1'b1 , (ACC1_acc_187_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_187_itm[2])) , (~ (ACC1_acc_187_itm[3]))});
+  assign ACC1_acc_188_itm = nl_ACC1_acc_188_itm[2:0];
+  assign nl_acc_10_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[69:60]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[79:70]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[89:80])) + 11'b11);
+  assign acc_10_psp_2_sva = nl_acc_10_psp_2_sva[11:0];
+  assign nl_ACC1_acc_161_itm = ({1'b1 , (ACC1_acc_160_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_160_itm[2])) , (~ (ACC1_acc_160_itm[3]))});
+  assign ACC1_acc_161_itm = nl_ACC1_acc_161_itm[2:0];
+  assign nl_ACC1_acc_160_itm = conv_s2s_3_4({(~ (ACC1_acc_120_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_120_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_160_itm = nl_ACC1_acc_160_itm[3:0];
+  assign nl_ACC1_acc_113_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_10_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_10_psp_2_sva[1]))
+      , (acc_10_psp_2_sva[8])})))) , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_10_psp_2_sva[0])
+      , (acc_10_psp_2_sva[10])})))) + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_2_sva[3])) , (~ (acc_10_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_10_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_10_psp_2_sva[5])) , (acc_10_psp_2_sva[6])}))))
+      , (~ (acc_10_psp_2_sva[9]))}))));
+  assign ACC1_acc_113_psp_2_sva = nl_ACC1_acc_113_psp_2_sva[3:0];
+  assign nl_ACC1_acc_120_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_113_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_113_psp_2_sva[1])) , (ACC1_acc_113_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_113_psp_2_sva[3]));
+  assign ACC1_acc_120_psp_1_sva = nl_ACC1_acc_120_psp_1_sva[2:0];
+  assign nl_ACC1_acc_277_cse = conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11])) +
+      conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11]));
+  assign ACC1_acc_277_cse = nl_ACC1_acc_277_cse[2:0];
+  assign nl_ACC1_acc_187_itm = conv_s2s_3_4({(~ (ACC1_acc_120_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_120_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_187_itm = nl_ACC1_acc_187_itm[3:0];
+  assign nl_acc_psp_1_sva = conv_s2s_11_12(conv_s2s_10_11(regs_regs_1_sva[19:10])
+      + conv_s2s_10_11(regs_regs_1_sva[9:0])) + conv_s2s_10_12(regs_regs_1_sva[29:20]);
+  assign acc_psp_1_sva = nl_acc_psp_1_sva[11:0];
+  assign nl_ACC1_acc_107_psp_1_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_1_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_1_sva[1])) , (acc_psp_1_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_1_sva[0]) , (acc_psp_1_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[3])) , (~ (acc_psp_1_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_1_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_1_sva[5])) , (acc_psp_1_sva[6])})))) ,
+      (~ (acc_psp_1_sva[9]))}))));
+  assign ACC1_acc_107_psp_1_sva = nl_ACC1_acc_107_psp_1_sva[3:0];
+  assign nl_ACC1_acc_116_psp_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_107_psp_1_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_107_psp_1_sva[1])) , (ACC1_acc_107_psp_1_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_107_psp_1_sva[3]));
+  assign ACC1_acc_116_psp_sva = nl_ACC1_acc_116_psp_sva[2:0];
+  assign nl_ACC1_acc_197_cse = conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_1_sva[11]));
+  assign ACC1_acc_197_cse = nl_ACC1_acc_197_cse[2:0];
+  assign nl_ACC1_acc_170_itm = ({1'b1 , (ACC1_acc_169_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_169_itm[2])) , (~ (ACC1_acc_169_itm[3]))});
+  assign ACC1_acc_170_itm = nl_ACC1_acc_170_itm[2:0];
+  assign nl_acc_psp_2_sva = conv_s2s_11_12(conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[9:0]))
+      + conv_s2s_10_11(~ (vin_rsc_mgc_in_wire_d[19:10]))) + conv_s2s_11_12(conv_s2s_10_11(~
+      (vin_rsc_mgc_in_wire_d[29:20])) + 11'b11);
+  assign acc_psp_2_sva = nl_acc_psp_2_sva[11:0];
+  assign nl_ACC1_acc_141_itm = ({1'b1 , (ACC1_acc_140_itm[1]) , 1'b1}) + conv_u2s_2_3({(~
+      (ACC1_acc_140_itm[2])) , (~ (ACC1_acc_140_itm[3]))});
+  assign ACC1_acc_141_itm = nl_ACC1_acc_141_itm[2:0];
+  assign nl_ACC1_acc_140_itm = conv_s2s_3_4({(~ (ACC1_acc_116_psp_1_sva[2:1])) ,
+      1'b1}) + conv_u2s_2_4({(ACC1_acc_116_psp_1_sva[0]) , 1'b1});
+  assign ACC1_acc_140_itm = nl_ACC1_acc_140_itm[3:0];
+  assign nl_ACC1_acc_107_psp_2_sva = (readslicef_5_4_1((conv_s2s_4_5({(readslicef_4_3_1((conv_s2s_2_4({(~
+      (acc_psp_2_sva[11])) , 1'b1}) + conv_u2s_2_4({(~ (acc_psp_2_sva[1])) , (acc_psp_2_sva[8])}))))
+      , 1'b1}) + conv_s2s_4_5({2'b10 , (acc_psp_2_sva[0]) , (acc_psp_2_sva[10])}))))
+      + conv_u2s_3_4(readslicef_4_3_1((conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[2])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[3])) , (~ (acc_psp_2_sva[7]))}))))
+      , 1'b1}) + conv_u2u_3_4({(readslicef_3_2_1((conv_u2u_2_3({(acc_psp_2_sva[4])
+      , 1'b1}) + conv_u2u_2_3({(~ (acc_psp_2_sva[5])) , (acc_psp_2_sva[6])})))) ,
+      (~ (acc_psp_2_sva[9]))}))));
+  assign ACC1_acc_107_psp_2_sva = nl_ACC1_acc_107_psp_2_sva[3:0];
+  assign nl_ACC1_acc_116_psp_1_sva = conv_u2s_2_3(readslicef_3_2_1((conv_u2u_2_3({(ACC1_acc_107_psp_2_sva[0])
+      , 1'b1}) + conv_u2u_2_3({(~ (ACC1_acc_107_psp_2_sva[1])) , (ACC1_acc_107_psp_2_sva[2])}))))
+      + conv_s2s_1_3(~ (ACC1_acc_107_psp_2_sva[3]));
+  assign ACC1_acc_116_psp_1_sva = nl_ACC1_acc_116_psp_1_sva[2:0];
+  assign nl_ACC1_acc_224_cse = conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11]));
+  assign ACC1_acc_224_cse = nl_ACC1_acc_224_cse[2:0];
+  assign nl_ACC1_acc_169_itm = conv_s2s_3_4({(~ (ACC1_acc_116_psp_sva[2:1])) , 1'b1})
+      + conv_u2s_2_4({(ACC1_acc_116_psp_sva[0]) , 1'b1});
+  assign ACC1_acc_169_itm = nl_ACC1_acc_169_itm[3:0];
+  assign exit_FRAME_lpi_1_dfm_1_mx0 = MUX_s_1_2_2({(~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+      + 8'b10110101)))) , (exit_FRAME_lpi_1_dfm_1 & (~ exit_FRAME_for_lpi_1_dfm_4))},
+      FRAME_for_acc_itm[1]);
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign ACC1_acc_125_psp_1_lpi_1_dfm_mx0 = MUX_v_12_2_2({ACC1_acc_125_psp_1_sva
+      , ACC1_acc_125_psp_1_lpi_1_dfm}, and_cse);
+  assign acc_imod_18_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_150_itm[3:2]) , acc_imod_18_lpi_1_dfm_sg1},
+      and_cse);
+  assign ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0 = MUX_v_3_2_2({(ACC1_acc_148_itm[4:2])
+      , ACC1_acc_110_psp_2_lpi_1_dfm_sg1}, and_cse);
+  assign acc_imod_20_lpi_1_dfm_mx0 = MUX_v_2_2_2({(readslicef_3_2_1((({1'b1 , (ACC1_acc_150_itm[1])
+      , 1'b1}) + conv_u2s_2_3({(~ (ACC1_acc_150_itm[2])) , (~ (ACC1_acc_150_itm[3]))}))))
+      , acc_imod_20_lpi_1_dfm}, and_cse);
+  assign ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0 = MUX_v_2_2_2({(ACC1_acc_118_psp_1_sva[2:1])
+      , ACC1_acc_118_psp_1_lpi_1_dfm_sg1}, and_cse);
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_3_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) |
+      FRAME_for_nor_cse | ((i_6_lpi_1_dfm[1]) & (~ (i_6_lpi_1_dfm[0])));
+  assign and_cse = ~(exit_FRAME_for_sva_1_st_1 | exit_FRAME_1_sva);
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      in_2_sva_1 <= 16'b0;
+      ACC1_acc_341_itm_1 <= 13'b0;
+      in_0_sva_1 <= 16'b0;
+      exit_FRAME_for_sva_1_st_1 <= 1'b0;
+      FRAME_for_acc_26_itm_1 <= 12'b0;
+      FRAME_for_slc_in_2_sva_itm_1 <= 12'b0;
+      exit_FRAME_for_lpi_1_dfm_3 <= 1'b0;
+      FRAME_for_acc_24_itm_1 <= 13'b0;
+      FRAME_for_slc_in_0_sva_itm_1 <= 12'b0;
+      i_6_sva_1 <= 2'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      ACC1_acc_110_psp_1_lpi_1_dfm_sg1 <= 3'b0;
+      ACC1_acc_125_psp_lpi_1_dfm <= 12'b0;
+      ACC1_acc_118_psp_lpi_1_dfm_sg1 <= 2'b0;
+      regs_regs_2_lpi_1_dfm_sg2 <= 30'b0;
+      regs_regs_2_lpi_1_dfm_1 <= 30'b0;
+      acc_imod_7_lpi_1_dfm <= 2'b0;
+      acc_imod_6_lpi_1_dfm_sg1 <= 2'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_1 <= 1'b0;
+      ACC1_acc_125_psp_1_lpi_1_dfm <= 12'b0;
+      acc_imod_18_lpi_1_dfm_sg1 <= 2'b0;
+      ACC1_acc_110_psp_2_lpi_1_dfm_sg1 <= 3'b0;
+      acc_imod_20_lpi_1_dfm <= 2'b0;
+      ACC1_acc_118_psp_1_lpi_1_dfm_sg1 <= 2'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({({((FRAME_acc_2_psp_sva[9:0])
+            | ({8'b0 , (FRAME_acc_2_psp_sva[11:10])})) , (FRAME_acc_2_psp_sva[9:6])
+            , ((FRAME_acc_2_psp_sva[5:0]) | ({4'b0 , (FRAME_acc_2_psp_sva[11:10])}))
+            , (FRAME_acc_2_psp_sva[9:0])}) , vout_rsc_mgc_out_stdreg_d}, ~(exit_FRAME_for_sva_1_st_1
+            & main_stage_0_2));
+        in_2_sva_1 <= MUX_v_16_2_2({in_2_sva_1 , in_2_sva_3}, main_stage_0_2);
+        ACC1_acc_341_itm_1 <= nl_ACC1_acc_341_itm_1[12:0];
+        in_0_sva_1 <= MUX_v_16_2_2({in_0_sva_1 , in_0_sva_3}, main_stage_0_2);
+        exit_FRAME_for_sva_1_st_1 <= ~ (FRAME_for_acc_itm[1]);
+        FRAME_for_acc_26_itm_1 <= nl_FRAME_for_acc_26_itm_1[11:0];
+        FRAME_for_slc_in_2_sva_itm_1 <= nl_FRAME_for_slc_in_2_sva_itm_1[11:0];
+        exit_FRAME_for_lpi_1_dfm_3 <= exit_FRAME_for_lpi_1_dfm_4;
+        FRAME_for_acc_24_itm_1 <= nl_FRAME_for_acc_24_itm_1[12:0];
+        FRAME_for_slc_in_0_sva_itm_1 <= nl_FRAME_for_slc_in_0_sva_itm_1[11:0];
+        i_6_sva_1 <= i_6_sva_2;
+        exit_FRAME_1_sva <= (~ (FRAME_for_acc_itm[1])) & exit_FRAME_lpi_1_dfm_1_mx0;
+        main_stage_0_2 <= 1'b1;
+        ACC1_acc_110_psp_1_lpi_1_dfm_sg1 <= ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0;
+        ACC1_acc_125_psp_lpi_1_dfm <= ACC1_acc_125_psp_lpi_1_dfm_mx0;
+        ACC1_acc_118_psp_lpi_1_dfm_sg1 <= ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0;
+        regs_regs_2_lpi_1_dfm_sg2 <= regs_regs_2_lpi_1_dfm_sg2_mx0;
+        regs_regs_2_lpi_1_dfm_1 <= regs_regs_2_lpi_1_dfm_1_mx0;
+        acc_imod_7_lpi_1_dfm <= acc_imod_7_lpi_1_dfm_mx0;
+        acc_imod_6_lpi_1_dfm_sg1 <= acc_imod_6_lpi_1_dfm_sg1_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_1 <= exit_FRAME_lpi_1_dfm_1_mx0;
+        ACC1_acc_125_psp_1_lpi_1_dfm <= ACC1_acc_125_psp_1_lpi_1_dfm_mx0;
+        acc_imod_18_lpi_1_dfm_sg1 <= acc_imod_18_lpi_1_dfm_sg1_mx0;
+        ACC1_acc_110_psp_2_lpi_1_dfm_sg1 <= ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0;
+        acc_imod_20_lpi_1_dfm <= acc_imod_20_lpi_1_dfm_mx0;
+        ACC1_acc_118_psp_1_lpi_1_dfm_sg1 <= ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0;
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_sva_1 , FRAME_p_1_lpi_1_dfm},
+            FRAME_for_acc_itm[1]);
+      end
+    end
+  end
+  assign nl_ACC1_acc_341_itm_1  = (conv_s2s_26_13(conv_u2s_2_13(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])) * 13'b1101000000001)
+      + conv_u2s_10_13((conv_u2u_9_10({conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[8])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[8])) * 6'b10101) , (ACC1_acc_125_psp_lpi_1_dfm_mx0[3])
+      , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}) + conv_u2u_8_10(conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[7])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[7])) * 8'b1010101) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_12_6(conv_u2u_2_6(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[5])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[5])) * 6'b10101)) + conv_u2u_6_7({(ACC1_acc_125_psp_lpi_1_dfm_mx0[6])
+      , 1'b0 , (ACC1_acc_125_psp_lpi_1_dfm_mx0[4]) , 1'b0 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}))))
+      + conv_u2u_8_10((conv_u2u_7_8(signext_7_3({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (signext_2_1(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11]))})) + conv_u2u_6_8(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (acc_imod_18_lpi_1_dfm_sg1_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[4])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[2])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , ((ACC1_acc_125_psp_lpi_1_dfm_mx0[11]) & (~ (acc_imod_7_lpi_1_dfm_mx0[1]))
+      & (acc_imod_7_lpi_1_dfm_mx0[0]))}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[6])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[8])
+      , (~((acc_imod_7_lpi_1_dfm_mx0[1]) & (~ (ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))))})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[10])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (acc_imod_6_lpi_1_dfm_sg1_mx0[0])})))))) + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[1])}))))))))) + conv_u2u_7_8(conv_u2u_6_7(conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[4:3]))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[2])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[6])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[8]) ,
+      (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[1])}))))))) + conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[0])}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (ACC1_acc_125_psp_lpi_1_dfm_mx0[3])})))))) + conv_u2u_4_5(readslicef_5_4_1((conv_u2u_4_5({(readslicef_4_3_1((conv_u2u_3_4({(ACC1_acc_125_psp_lpi_1_dfm_mx0[2])
+      , (ACC1_acc_125_psp_lpi_1_dfm_mx0[0]) , 1'b1}) + conv_u2u_3_4({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[2])
+      , (ACC1_acc_125_psp_lpi_1_dfm_mx0[1]) , (ACC1_acc_125_psp_lpi_1_dfm_mx0[2])}))))
+      , 1'b1}) + conv_u2u_4_5({(~ (ACC1_acc_110_psp_1_lpi_1_dfm_sg1_mx0[2])) , 1'b1
+      , (~ (acc_imod_6_lpi_1_dfm_sg1_mx0[1])) , ((ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11])
+      & (~ (acc_imod_20_lpi_1_dfm_mx0[1])) & (acc_imod_20_lpi_1_dfm_mx0[0]))}))))))
+      + conv_u2u_4_7((readslicef_5_4_1((conv_u2u_4_5({(~ (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[2]))
+      , 1'b1 , (~ (acc_imod_18_lpi_1_dfm_sg1_mx0[1])) , 1'b1}) + conv_s2u_3_5({ACC1_acc_118_psp_lpi_1_dfm_sg1_mx0
+      , (~((acc_imod_20_lpi_1_dfm_mx0[1]) & (~ (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[11]))))}))))
+      + (readslicef_5_4_1((conv_u2s_3_5(signext_3_2({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , 1'b1})) + conv_s2s_3_5({ACC1_acc_118_psp_1_lpi_1_dfm_sg1_mx0 , (ACC1_acc_110_psp_2_lpi_1_dfm_sg1_mx0[1])})))))))))
+      + (conv_s2s_11_13(conv_u2s_10_12(conv_u2s_20_11(conv_u2u_2_10(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[9])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[9])) * 10'b101010101)) + conv_s2s_9_11(conv_s2s_7_9(conv_u2s_6_7({(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[6])
+      , 1'b0 , (ACC1_acc_125_psp_lpi_1_dfm_mx0[6]) , 1'b0 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))})
+      + conv_s2s_5_7(({(conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[4]) + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[6]))
+      , (conv_u2u_2_3(signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[10])) + conv_u2u_2_3(signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])))})
+      + ({3'b100 , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}))) + conv_u2s_7_9(signext_7_3({(ACC1_acc_125_psp_lpi_1_dfm_mx0[11])
+      , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))})))) + conv_u2s_11_13({conv_u2u_16_8(conv_u2u_2_8(conv_u2u_1_2(ACC1_acc_125_psp_lpi_1_dfm_mx0[10])
+      + conv_u2u_1_2(ACC1_acc_125_psp_1_lpi_1_dfm_mx0[10])) * 8'b1010101) , (ACC1_acc_125_psp_1_lpi_1_dfm_mx0[3])
+      , (signext_2_1(ACC1_acc_125_psp_lpi_1_dfm_mx0[11]))}));
+  assign nl_FRAME_for_acc_26_itm_1  = (conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+      , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_sg2_mx0[19:10])
+      , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})))
+      + conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+      , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_sg2_mx0[9:0]) ,
+      10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))
+      + conv_s2s_11_12(conv_s2s_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+      , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_sg2_mx0[29:20])
+      , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm})));
+  assign nl_FRAME_for_slc_in_2_sva_itm_1  = conv_s2s_11_12(conv_u2s_10_11({(acc_10_psp_1_sva[11])
+      , 8'b0 , (acc_10_psp_1_sva[11])}) + (conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_10_psp_1_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_113_psp_1_sva[3])
+      , (acc_10_psp_1_sva[4])})))) + conv_s2s_2_3(ACC1_acc_120_psp_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_10_psp_1_sva[3])
+      , (acc_10_psp_1_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_113_psp_1_sva[3])
+      , (acc_10_psp_1_sva[2]) , (ACC1_acc_113_psp_1_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_10_psp_1_sva[7])
+      , (acc_10_psp_1_sva[4]) , (signext_2_1(acc_10_psp_1_sva[11]))}) + conv_u2u_3_5(ACC1_acc_250_cse)))
+      + conv_u2s_7_8({(acc_10_psp_1_sva[8]) , 1'b0 , (acc_10_psp_1_sva[8]) , 1'b0
+      , (acc_10_psp_1_sva[8]) , 1'b0 , (acc_10_psp_1_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_10_psp_1_sva[11])
+      , (signext_2_1(acc_10_psp_1_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_10_psp_1_sva[6])
+      , 1'b0 , (acc_10_psp_1_sva[6]) , 1'b0 , (acc_10_psp_1_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_250_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[9]) , ((acc_10_psp_1_sva[11])
+      & (~ (ACC1_acc_188_itm[2])) & (ACC1_acc_188_itm[1]))}))))))))) + conv_u2s_10_11({(acc_10_psp_1_sva[11])
+      , 1'b0 , (acc_10_psp_1_sva[11]) , 1'b0 , (acc_10_psp_1_sva[11]) , 1'b0 , (acc_10_psp_1_sva[11])
+      , 1'b0 , (signext_2_1(acc_10_psp_1_sva[11]))}))) + (conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_10_psp_2_sva[10])
+      , 1'b0 , (acc_10_psp_2_sva[10]) , 1'b0 , (acc_10_psp_2_sva[10]) , 1'b0 , (acc_10_psp_2_sva[10])
+      , 1'b0 , (acc_10_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_10_psp_2_sva[9]) ,
+      1'b0 , (acc_10_psp_2_sva[9]) , 1'b0 , (acc_10_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_10_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_10_psp_2_sva[7]) , 1'b0 , (acc_10_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_10_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (~((ACC1_acc_161_itm[2])
+      & (~ (acc_10_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (~ (ACC1_acc_160_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (ACC1_acc_160_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[11]) , (ACC1_acc_113_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_10_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_113_psp_2_sva[3])
+      , (acc_10_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_120_psp_1_sva[2:1])) +
+      (readslicef_5_4_1((conv_u2s_3_5({(acc_10_psp_2_sva[3]) , (acc_10_psp_2_sva[1])
+      , 1'b1}) + conv_s2s_3_5({(ACC1_acc_113_psp_2_sva[3]) , (acc_10_psp_2_sva[2])
+      , (ACC1_acc_113_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_10_psp_2_sva[7])
+      , (acc_10_psp_2_sva[4]) , (signext_2_1(acc_10_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_277_cse)))
+      + conv_u2s_7_8({(acc_10_psp_2_sva[8]) , 1'b0 , (acc_10_psp_2_sva[8]) , 1'b0
+      , (acc_10_psp_2_sva[8]) , 1'b0 , (acc_10_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_10_psp_2_sva[11])
+      , (signext_2_1(acc_10_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_10_psp_2_sva[6])
+      , 1'b0 , (acc_10_psp_2_sva[6]) , 1'b0 , (acc_10_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_277_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_2_sva[9]) , ((acc_10_psp_2_sva[11])
+      & (~ (ACC1_acc_161_itm[2])) & (ACC1_acc_161_itm[1]))})))))))))) + ({(acc_10_psp_2_sva[11])
+      , 2'b0 , (acc_10_psp_2_sva[11]) , 1'b0 , (acc_10_psp_2_sva[11]) , 1'b0 , (acc_10_psp_2_sva[11])
+      , (conv_u2u_1_3(acc_10_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_10_psp_2_sva[11])))}))
+      + conv_u2s_10_12(conv_u2u_9_10({(acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10])
+      , 1'b0 , (acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10]) , 1'b0 , (acc_10_psp_1_sva[10])})
+      + conv_u2u_8_10(({(acc_10_psp_1_sva[9]) , 1'b0 , (acc_10_psp_1_sva[9]) , 1'b0
+      , (acc_10_psp_1_sva[9]) , 1'b0 , (signext_2_1(acc_10_psp_1_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_10_psp_1_sva[7])
+      , 1'b0 , (acc_10_psp_1_sva[5]) , 1'b0 , (signext_2_1(acc_10_psp_1_sva[11]))})
+      + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (~((ACC1_acc_188_itm[2])
+      & (~ (acc_10_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (~ (ACC1_acc_187_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (ACC1_acc_187_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_10_psp_1_sva[11]) , (ACC1_acc_113_psp_1_sva[2])})))))))))));
+  assign nl_FRAME_for_acc_24_itm_1  = (conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+      , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_1_mx0[19:10]) ,
+      10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm}))) + conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0])
+      , (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_1_mx0[9:0]) , 10'b0},
+      i_6_lpi_1_dfm)) * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})))) + conv_s2s_12_13(conv_s2s_24_12(conv_s2s_10_12(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+      , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_1_mx0[29:20]) ,
+      10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_12({1'b1 , FRAME_for_or_3_itm})));
+  assign nl_FRAME_for_slc_in_0_sva_itm_1  = conv_s2s_11_12(conv_u2s_10_11({(acc_psp_1_sva[11])
+      , 8'b0 , (acc_psp_1_sva[11])}) + (conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_psp_1_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_107_psp_1_sva[3]) ,
+      (acc_psp_1_sva[4])})))) + conv_s2s_2_3(ACC1_acc_116_psp_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_1_sva[3])
+      , (acc_psp_1_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_107_psp_1_sva[3]) ,
+      (acc_psp_1_sva[2]) , (ACC1_acc_107_psp_1_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_1_sva[7])
+      , (acc_psp_1_sva[4]) , (signext_2_1(acc_psp_1_sva[11]))}) + conv_u2u_3_5(ACC1_acc_197_cse)))
+      + conv_u2s_7_8({(acc_psp_1_sva[8]) , 1'b0 , (acc_psp_1_sva[8]) , 1'b0 , (acc_psp_1_sva[8])
+      , 1'b0 , (acc_psp_1_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_1_sva[11])
+      , (signext_2_1(acc_psp_1_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_1_sva[6])
+      , 1'b0 , (acc_psp_1_sva[6]) , 1'b0 , (acc_psp_1_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_197_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[9]) , ((acc_psp_1_sva[11])
+      & (~ (ACC1_acc_170_itm[2])) & (ACC1_acc_170_itm[1]))}))))))))) + conv_u2s_10_11({(acc_psp_1_sva[11])
+      , 1'b0 , (acc_psp_1_sva[11]) , 1'b0 , (acc_psp_1_sva[11]) , 1'b0 , (acc_psp_1_sva[11])
+      , 1'b0 , (signext_2_1(acc_psp_1_sva[11]))}))) + (conv_s2s_11_12((conv_u2s_10_11(conv_u2u_9_10({(acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10]) , 1'b0 , (acc_psp_2_sva[10])
+      , 1'b0 , (acc_psp_2_sva[10])}) + conv_u2u_8_10(({(acc_psp_2_sva[9]) , 1'b0
+      , (acc_psp_2_sva[9]) , 1'b0 , (acc_psp_2_sva[9]) , 1'b0 , (signext_2_1(acc_psp_2_sva[5]))})
+      + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_2_sva[7]) , 1'b0 , (acc_psp_2_sva[5])
+      , 1'b0 , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~((ACC1_acc_141_itm[2])
+      & (~ (acc_psp_2_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (~ (ACC1_acc_140_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_140_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[11]) , (ACC1_acc_107_psp_2_sva[2])}))))))))))
+      + conv_s2s_10_11(conv_s2s_8_10(conv_s2s_6_8(conv_s2s_4_6(conv_s2s_3_4((readslicef_4_3_1((conv_s2s_3_4({1'b1
+      , (acc_psp_2_sva[3]) , 1'b1}) + conv_s2s_2_4({(ACC1_acc_107_psp_2_sva[3]) ,
+      (acc_psp_2_sva[4])})))) + conv_s2s_2_3(ACC1_acc_116_psp_1_sva[2:1])) + (readslicef_5_4_1((conv_u2s_3_5({(acc_psp_2_sva[3])
+      , (acc_psp_2_sva[1]) , 1'b1}) + conv_s2s_3_5({(ACC1_acc_107_psp_2_sva[3]) ,
+      (acc_psp_2_sva[2]) , (ACC1_acc_107_psp_2_sva[1])}))))) + conv_u2s_5_6(conv_u2u_4_5({(acc_psp_2_sva[7])
+      , (acc_psp_2_sva[4]) , (signext_2_1(acc_psp_2_sva[11]))}) + conv_u2u_3_5(ACC1_acc_224_cse)))
+      + conv_u2s_7_8({(acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8]) , 1'b0 , (acc_psp_2_sva[8])
+      , 1'b0 , (acc_psp_2_sva[8])})) + conv_u2s_8_10(conv_u2u_7_8(signext_7_3({(acc_psp_2_sva[11])
+      , (signext_2_1(acc_psp_2_sva[11]))})) + conv_u2u_6_8(conv_u2u_5_6({(acc_psp_2_sva[6])
+      , 1'b0 , (acc_psp_2_sva[6]) , 1'b0 , (acc_psp_2_sva[6])}) + conv_u2u_4_6(conv_u2u_3_4(ACC1_acc_224_cse)
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[7])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_2_sva[9]) , ((acc_psp_2_sva[11])
+      & (~ (ACC1_acc_141_itm[2])) & (ACC1_acc_141_itm[1]))})))))))))) + ({(acc_psp_2_sva[11])
+      , 2'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11]) , 1'b0 , (acc_psp_2_sva[11])
+      , (conv_u2u_1_3(acc_psp_2_sva[11]) + conv_u2u_2_3(signext_2_1(acc_psp_2_sva[11])))}))
+      + conv_u2s_10_12(conv_u2u_9_10({(acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10])
+      , 1'b0 , (acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10]) , 1'b0 , (acc_psp_1_sva[10])})
+      + conv_u2u_8_10(({(acc_psp_1_sva[9]) , 1'b0 , (acc_psp_1_sva[9]) , 1'b0 , (acc_psp_1_sva[9])
+      , 1'b0 , (signext_2_1(acc_psp_1_sva[5]))}) + conv_u2u_7_8(conv_u2u_6_7({(acc_psp_1_sva[7])
+      , 1'b0 , (acc_psp_1_sva[5]) , 1'b0 , (signext_2_1(acc_psp_1_sva[11]))}) + conv_u2u_5_7(conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (~((ACC1_acc_170_itm[2])
+      & (~ (acc_psp_1_sva[11]))))}))))) + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (~ (ACC1_acc_169_itm[3]))}))))))
+      + conv_u2u_4_5(conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_169_itm[2])})))))
+      + conv_u2u_3_4(readslicef_4_3_1((conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11])
+      , 1'b1})) + conv_u2u_3_4(signext_3_2({(acc_psp_1_sva[11]) , (ACC1_acc_107_psp_1_sva[2])})))))))))));
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] MUX_v_3_2_2;
+    input [5:0] inputs;
+    input [0:0] sel;
+    reg [2:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[5:3];
+      end
+      1'b1 : begin
+        result = inputs[2:0];
+      end
+      default : begin
+        result = inputs[5:3];
+      end
+    endcase
+    MUX_v_3_2_2 = result;
+  end
+  endfunction
+
+
+  function [11:0] MUX_v_12_2_2;
+    input [23:0] inputs;
+    input [0:0] sel;
+    reg [11:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[23:12];
+      end
+      1'b1 : begin
+        result = inputs[11:0];
+      end
+      default : begin
+        result = inputs[23:12];
+      end
+    endcase
+    MUX_v_12_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] MUX_v_2_2_2;
+    input [3:0] inputs;
+    input [0:0] sel;
+    reg [1:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[3:2];
+      end
+      1'b1 : begin
+        result = inputs[1:0];
+      end
+      default : begin
+        result = inputs[3:2];
+      end
+    endcase
+    MUX_v_2_2_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] readslicef_3_2_1;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_3_2_1 = tmp[1:0];
+  end
+  endfunction
+
+
+  function [2:0] readslicef_4_3_1;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_4_3_1 = tmp[2:0];
+  end
+  endfunction
+
+
+  function [3:0] readslicef_5_4_1;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_5_4_1 = tmp[3:0];
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [6:0] signext_7_3;
+    input [2:0] vector;
+  begin
+    signext_7_3= {{4{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_2;
+    input [1:0] vector;
+  begin
+    signext_3_2= {{1{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_22_12 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2s_22_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [15:0] conv_s2s_13_16 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2s_13_16 = {{3{vector[12]}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_13_16 ;
+    input signed [12:0]  vector ;
+  begin
+    conv_s2u_13_16 = {{3{vector[12]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_u2s_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_3_4 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_4 = {vector[2], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_2_3 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_3 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_1_3 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2s_1_3 = {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_4_5 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_5 = {vector[3], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_s2s_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2s_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2u_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+
+  function signed [3:0] conv_s2s_2_4 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_4 = {{2{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_26_13 ;
+    input signed [25:0]  vector ;
+  begin
+    conv_s2s_26_13 = vector[12:0];
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_2_13 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2s_2_13 = {{11{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_u2u_1_2 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_2 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2u_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_12_6 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_6 = vector[5:0];
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_2_6 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_6 = {{4{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2u_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_2_8 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_8 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2u_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [7:0] conv_u2u_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2u_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_4_7 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_7 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_s2u_3_5 ;
+    input signed [2:0]  vector ;
+  begin
+    conv_s2u_3_5 = {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_11_13 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2s_11_13 = {{2{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_9_11 ;
+    input signed [8:0]  vector ;
+  begin
+    conv_s2s_9_11 = {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_s2s_7_9 ;
+    input signed [6:0]  vector ;
+  begin
+    conv_s2s_7_9 = {{2{vector[6]}}, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_u2s_6_7 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_7 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [6:0] conv_s2s_5_7 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_7 = {{2{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [8:0] conv_u2s_7_9 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_9 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2s_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_6_8 ;
+    input signed [5:0]  vector ;
+  begin
+    conv_s2s_6_8 = {{2{vector[5]}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_4_6 ;
+    input signed [3:0]  vector ;
+  begin
+    conv_s2s_4_6 = {{2{vector[3]}}, vector};
+  end
+  endfunction
+
+
+  function signed [2:0] conv_s2s_2_3 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_3 = {vector[1], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_8_10 ;
+    input [7:0]  vector ;
+  begin
+    conv_u2s_8_10 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [6:0] conv_u2u_5_7 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_7 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [2:0] conv_u2u_1_3 ;
+    input [0:0]  vector ;
+  begin
+    conv_u2u_1_3 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_s2s_12_13 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2s_12_13 = {vector[11], vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2s_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v8/rtl.v.psr b/Sobel/sobel.v8/rtl.v.psr
new file mode 100644
index 0000000..b7e3859
--- /dev/null
+++ b/Sobel/sobel.v8/rtl.v.psr
@@ -0,0 +1,289 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v8/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v8/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v8/rtl.v}} -format verilog
+   setup_design -design=sobel
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'sobel': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'sobel': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'sobel'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'sobel'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to vout_rsc_z(29:0)
+   report_timing -from en -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from vin_rsc_z(89:0) -to vout_rsc_z(29:0)
+   report_timing -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock clk] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock en] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'sobel'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'sobel'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v8 mapped.v]
+          puts "-- Writing mapped netlist for 'sobel' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v8 gate.v]
+          set gate_sdf [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v8 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/Sobel/sobel.v8/rtl.v.psr_timing b/Sobel/sobel.v8/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/Sobel/sobel.v8/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/Sobel/sobel.v8/rtl.v_order.txt b/Sobel/sobel.v8/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/Sobel/sobel.v8/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/Sobel/sobel.v8/rtl_mgc_ioport.v b/Sobel/sobel.v8/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v8/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v8/rtl_mgc_ioport_v2001.v b/Sobel/sobel.v8/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v8/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v8/schedule.gnt b/Sobel/sobel.v8/schedule.gnt
new file mode 100644
index 0000000..ab2a307
--- /dev/null
+++ b/Sobel/sobel.v8/schedule.gnt
@@ -0,0 +1,1570 @@
+set a(0-4407) {NAME i:asn(i#6.lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29138 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4408) {NAME in:asn(in(2).lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29139 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4409) {NAME in:asn(in(0).lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29140 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4410) {NAME ACC1:asn(acc.imod#7.lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29141 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4411) {NAME ACC1:asn(acc.imod#6.lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29142 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4412) {NAME ACC1:asn(ACC1:acc#118.psp.lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29143 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4413) {NAME ACC1:asn(ACC1:acc#110.psp#1.lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29144 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4414) {NAME ACC1:asn(ACC1:acc#125.psp.lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29145 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4415) {NAME ACC1:asn(acc.imod#20.lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29146 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4416) {NAME ACC1:asn(acc.imod#18.lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29147 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4417) {NAME ACC1:asn(ACC1:acc#118.psp#1.lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29148 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4418) {NAME ACC1:asn(ACC1:acc#110.psp#2.lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29149 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4419) {NAME ACC1:asn(ACC1:acc#125.psp#1.lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29150 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4420) {NAME regs.regs:asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29151 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4421) {NAME FRAME:asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29152 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4422) {NAME FRAME:for:asn(exit:FRAME:for.lpi#1)#1 TYPE ASSIGN PAR 0-4406 XREFS 29153 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4423) {NAME FRAME:p:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-4406 XREFS 29154 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4424) {NAME asn(regs.regs(1))#1 TYPE ASSIGN PAR 0-4406 XREFS 29155 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4425) {NAME asn(regs.regs(0))#1 TYPE ASSIGN PAR 0-4406 XREFS 29156 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{258 0 0-4427 {}}} CYCLES {}}
+set a(0-4426) {NAME FRAME:for:asn(exit:FRAME#1) TYPE ASSIGN PAR 0-4406 XREFS 29157 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-4427 {}}} SUCCS {{259 0 0-4427 {}}} CYCLES {}}
+set a(0-4428) {NAME FRAME:asn(exit:FRAME.sva#1) TYPE ASSIGN PAR 0-4427 XREFS 29158 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 1 0.9769393999999999} PREDS {} SUCCS {{258 0 0-5945 {}} {258 0 0-5946 {}}} CYCLES {}}
+set a(0-4429) {NAME FRAME:p:asn(FRAME:p#1.sva#1) TYPE ASSIGN PAR 0-4427 XREFS 29159 LOC {0 1.0 1 0.9245549 1 0.9245549 2 0.7658281499999999} PREDS {} SUCCS {{258 0 0-5959 {}}} CYCLES {}}
+set a(0-4430) {NAME in:asn(in(2).sva) TYPE ASSIGN PAR 0-4427 XREFS 29160 LOC {0 1.0 1 1.0 1 1.0 2 0.06859512499999999} PREDS {} SUCCS {{258 0 0-5585 {}}} CYCLES {}}
+set a(0-4431) {NAME in:asn(in(0).sva) TYPE ASSIGN PAR 0-4427 XREFS 29161 LOC {0 1.0 1 1.0 1 1.0 2 0.17449594999999998} PREDS {} SUCCS {{258 0 0-5547 {}}} CYCLES {}}
+set a(0-4432) {NAME ACC1:asn(acc.imod#7.sva) TYPE ASSIGN PAR 0-4427 XREFS 29162 LOC {0 1.0 1 0.410926075 1 0.410926075 1 0.59843245} PREDS {} SUCCS {{258 0 0-5495 {}}} CYCLES {}}
+set a(0-4433) {NAME ACC1:asn(acc.imod#6.sva) TYPE ASSIGN PAR 0-4427 XREFS 29163 LOC {0 1.0 1 0.38368015 1 0.38368015 1 0.59843245} PREDS {} SUCCS {{258 0 0-5494 {}}} CYCLES {}}
+set a(0-4434) {NAME ACC1:asn(ACC1:acc#118.psp.sva) TYPE ASSIGN PAR 0-4427 XREFS 29164 LOC {0 1.0 1 0.356434225 1 0.356434225 1 0.744095325} PREDS {} SUCCS {{258 0 0-5503 {}}} CYCLES {}}
+set a(0-4435) {NAME ACC1:asn(ACC1:acc#110.psp#1.sva) TYPE ASSIGN PAR 0-4427 XREFS 29165 LOC {0 1.0 1 0.295178375 1 0.295178375 1 0.59843245} PREDS {} SUCCS {{258 0 0-5505 {}}} CYCLES {}}
+set a(0-4436) {NAME ACC1:asn(ACC1:acc#125.psp.sva) TYPE ASSIGN PAR 0-4427 XREFS 29166 LOC {0 1.0 1 0.18306899999999998 1 0.18306899999999998 1 0.47957327499999997} PREDS {} SUCCS {{258 0 0-5504 {}}} CYCLES {}}
+set a(0-4437) {NAME ACC1:asn(acc.imod#20.sva) TYPE ASSIGN PAR 0-4427 XREFS 29167 LOC {0 1.0 1 0.45736869999999996 1 0.45736869999999996 1 0.644875075} PREDS {} SUCCS {{258 0 0-5510 {}}} CYCLES {}}
+set a(0-4438) {NAME ACC1:asn(acc.imod#18.sva) TYPE ASSIGN PAR 0-4427 XREFS 29168 LOC {0 1.0 1 0.410926075 1 0.410926075 1 0.59843245} PREDS {} SUCCS {{258 0 0-5509 {}}} CYCLES {}}
+set a(0-4439) {NAME ACC1:asn(ACC1:acc#118.psp#1.sva) TYPE ASSIGN PAR 0-4427 XREFS 29169 LOC {0 1.0 1 0.38368015 1 0.38368015 1 0.749886225} PREDS {} SUCCS {{258 0 0-5511 {}}} CYCLES {}}
+set a(0-4440) {NAME ACC1:asn(ACC1:acc#110.psp#2.sva) TYPE ASSIGN PAR 0-4427 XREFS 29170 LOC {0 1.0 1 0.3224243 1 0.3224243 1 0.59843245} PREDS {} SUCCS {{258 0 0-5513 {}}} CYCLES {}}
+set a(0-4441) {NAME ACC1:asn(ACC1:acc#125.psp#1.sva) TYPE ASSIGN PAR 0-4427 XREFS 29171 LOC {0 1.0 1 0.21031492499999999 1 0.21031492499999999 1 0.47957327499999997} PREDS {} SUCCS {{258 0 0-5512 {}}} CYCLES {}}
+set a(0-4442) {NAME regs.regs:asn(regs.regs(0).sva#1) TYPE ASSIGN PAR 0-4427 XREFS 29172 LOC {0 1.0 1 0.013988325 1 0.013988325 1 0.6501168749999999} PREDS {} SUCCS {{258 0 0-5497 {}}} CYCLES {}}
+set a(0-4443) {NAME FRAME:for:asn TYPE ASSIGN PAR 0-4427 XREFS 29173 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-5969 {}}} SUCCS {{259 0 0-4444 {}} {256 0 0-5969 {}}} CYCLES {}}
+set a(0-4444) {NAME FRAME:for:select TYPE SELECT PAR 0-4427 XREFS 29174 LOC {0 1.0 0 1.0 0 1.0 3 1.0} PREDS {{259 0 0-4443 {}}} SUCCS {} CYCLES {}}
+set a(0-4445) {NAME FRAME:asn TYPE ASSIGN PAR 0-4427 XREFS 29175 LOC {0 1.0 1 0.7888887499999999 1 0.7888887499999999 1 0.7888887499999999} PREDS {{262 0 0-5969 {}}} SUCCS {{259 0 0-4446 {}} {256 0 0-5969 {}}} CYCLES {}}
+set a(0-4446) {NAME FRAME:not#10 TYPE NOT PAR 0-4427 XREFS 29176 LOC {1 0.0 1 0.7888887499999999 1 0.7888887499999999 1 0.7888887499999999} PREDS {{259 0 0-4445 {}}} SUCCS {{259 0 0-4447 {}}} CYCLES {}}
+set a(0-4447) {NAME FRAME:for:exs TYPE SIGNEXTEND PAR 0-4427 XREFS 29177 LOC {1 0.0 1 0.7888887499999999 1 0.7888887499999999 1 0.7888887499999999} PREDS {{259 0 0-4446 {}}} SUCCS {{259 0 0-4448 {}}} CYCLES {}}
+set a(0-4448) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(19,2) AREA_SCORE 13.87 QUANTITY 1 NAME FRAME:for:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-4427 XREFS 29178 LOC {1 0.0 1 0.7888887499999999 1 0.7888887499999999 1 0.8052954812638539 1 0.8052954812638539} PREDS {{262 0 0-5959 {}} {259 0 0-4447 {}}} SUCCS {{258 0 0-5938 {}} {258 0 0-5959 {}}} CYCLES {}}
+set a(0-4449) {NAME FRAME:for:asn#3 TYPE ASSIGN PAR 0-4427 XREFS 29179 LOC {0 1.0 1 0.0 1 0.0 1 0.013988325} PREDS {{262 0 0-5969 {}}} SUCCS {{259 0 0-4450 {}} {256 0 0-5969 {}}} CYCLES {}}
+set a(0-4450) {NAME FRAME:for:or TYPE OR PAR 0-4427 XREFS 29180 LOC {1 0.0 1 0.0 1 0.0 1 0.013988325} PREDS {{262 0 0-5967 {}} {259 0 0-4449 {}}} SUCCS {{259 0 0-4451 {}} {258 0 0-5494 {}} {258 0 0-5495 {}} {258 0 0-5497 {}} {258 0 0-5500 {}} {258 0 0-5502 {}} {258 0 0-5503 {}} {258 0 0-5504 {}} {258 0 0-5505 {}} {258 0 0-5506 {}} {258 0 0-5509 {}} {258 0 0-5510 {}} {258 0 0-5511 {}} {258 0 0-5512 {}} {258 0 0-5513 {}} {258 0 0-5549 {}} {258 0 0-5587 {}} {258 0 0-5943 {}} {256 0 0-5967 {}}} CYCLES {}}
+set a(0-4451) {NAME FRAME:for:select#1 TYPE SELECT PAR 0-4427 XREFS 29181 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{259 0 0-4450 {}}} SUCCS {{146 0 0-4452 {}} {146 0 0-4453 {}} {146 0 0-4454 {}} {146 0 0-4455 {}} {146 0 0-4456 {}} {146 0 0-4457 {}} {146 0 0-4458 {}} {146 0 0-4459 {}} {146 0 0-4460 {}} {146 0 0-4461 {}} {146 0 0-4462 {}} {146 0 0-4463 {}} {146 0 0-4464 {}} {146 0 0-4465 {}} {146 0 0-4466 {}} {146 0 0-4467 {}} {146 0 0-4468 {}} {146 0 0-4469 {}} {146 0 0-4470 {}} {146 0 0-4471 {}} {146 0 0-4472 {}} {146 0 0-4473 {}} {146 0 0-4474 {}} {146 0 0-4475 {}} {146 0 0-4476 {}} {146 0 0-4477 {}} {146 0 0-4478 {}} {146 0 0-4479 {}} {146 0 0-4480 {}} {146 0 0-4481 {}} {146 0 0-4482 {}} {146 0 0-4483 {}} {146 0 0-4484 {}} {146 0 0-4485 {}} {146 0 0-4486 {}} {146 0 0-4487 {}} {146 0 0-4488 {}} {146 0 0-4489 {}} {146 0 0-4490 {}} {146 0 0-4491 {}} {146 0 0-4492 {}} {146 0 0-4493 {}} {146 0 0-4494 {}} {146 0 0-4495 {}} {146 0 0-4496 {}} {146 0 0-4497 {}} {146 0 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0-5386 {}} {146 0 0-5387 {}} {146 0 0-5388 {}} {146 0 0-5389 {}} {146 0 0-5390 {}} {146 0 0-5391 {}} {146 0 0-5392 {}} {146 0 0-5393 {}} {146 0 0-5394 {}} {146 0 0-5395 {}} {146 0 0-5396 {}} {146 0 0-5397 {}} {146 0 0-5398 {}} {146 0 0-5399 {}} {146 0 0-5400 {}} {146 0 0-5401 {}} {146 0 0-5402 {}} {146 0 0-5403 {}} {146 0 0-5404 {}} {146 0 0-5405 {}} {146 0 0-5406 {}} {146 0 0-5407 {}} {146 0 0-5408 {}} {146 0 0-5409 {}} {146 0 0-5410 {}} {146 0 0-5411 {}} {146 0 0-5412 {}} {146 0 0-5413 {}} {146 0 0-5414 {}} {146 0 0-5415 {}} {146 0 0-5416 {}} {146 0 0-5417 {}} {146 0 0-5418 {}} {146 0 0-5419 {}} {146 0 0-5420 {}} {146 0 0-5421 {}} {146 0 0-5422 {}} {146 0 0-5423 {}} {146 0 0-5424 {}} {146 0 0-5425 {}} {146 0 0-5426 {}} {146 0 0-5427 {}} {146 0 0-5428 {}} {146 0 0-5429 {}} {146 0 0-5430 {}} {146 0 0-5431 {}} {146 0 0-5432 {}} {146 0 0-5433 {}} {146 0 0-5434 {}} {146 0 0-5435 {}} {146 0 0-5436 {}} {146 0 0-5437 {}} {146 0 0-5438 {}} {146 0 0-5439 {}} {146 0 0-5440 {}} {146 0 0-5441 {}} {146 0 0-5442 {}} {146 0 0-5443 {}} {146 0 0-5444 {}} {146 0 0-5445 {}} {146 0 0-5446 {}} {146 0 0-5447 {}} {146 0 0-5448 {}} {146 0 0-5449 {}} {146 0 0-5450 {}} {146 0 0-5451 {}} {146 0 0-5452 {}} {146 0 0-5453 {}} {146 0 0-5454 {}} {146 0 0-5455 {}} {146 0 0-5456 {}} {146 0 0-5457 {}} {146 0 0-5458 {}} {146 0 0-5459 {}} {146 0 0-5460 {}} {146 0 0-5461 {}} {146 0 0-5462 {}} {146 0 0-5463 {}} {146 0 0-5464 {}} {146 0 0-5465 {}} {146 0 0-5466 {}} {146 0 0-5467 {}} {146 0 0-5468 {}} {146 0 0-5469 {}} {146 0 0-5470 {}} {146 0 0-5471 {}} {146 0 0-5472 {}} {146 0 0-5473 {}} {146 0 0-5474 {}} {146 0 0-5475 {}} {146 0 0-5476 {}} {146 0 0-5477 {}} {146 0 0-5478 {}} {146 0 0-5479 {}} {146 0 0-5480 {}} {146 0 0-5481 {}} {146 0 0-5482 {}} {146 0 0-5483 {}} {146 0 0-5484 {}} {146 0 0-5485 {}} {146 0 0-5486 {}} {146 0 0-5487 {}} {146 0 0-5488 {}} {146 0 0-5489 {}} {146 0 0-5490 {}} {146 0 0-5491 {}} {146 0 0-5492 {}} {146 0 0-5493 {}}} CYCLES {}}
+set a(0-4452) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,90) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_read(vin:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-4427 XREFS 29182 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-4451 {}}} SUCCS {{259 0 0-4453 {}} {258 0 0-4455 {}} {258 0 0-4458 {}} {258 0 0-4529 {}} {258 0 0-4531 {}} {258 0 0-4534 {}} {258 0 0-4602 {}} {258 0 0-4604 {}} {258 0 0-4607 {}} {258 0 0-5497 {}}} CYCLES {}}
+set a(0-4453) {NAME regs.regs:slc(regs.regs(0)) TYPE READSLICE PAR 0-4427 XREFS 29183 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15869224999999998} PREDS {{146 0 0-4451 {}} {259 0 0-4452 {}}} SUCCS {{259 0 0-4454 {}}} CYCLES {}}
+set a(0-4454) {NAME ACC1:not TYPE NOT PAR 0-4427 XREFS 29184 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15869224999999998} PREDS {{146 0 0-4451 {}} {259 0 0-4453 {}}} SUCCS {{258 0 0-4457 {}}} CYCLES {}}
+set a(0-4455) {NAME regs.regs:slc(regs.regs(0))#1 TYPE READSLICE PAR 0-4427 XREFS 29185 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15869224999999998} PREDS {{146 0 0-4451 {}} {258 0 0-4452 {}}} SUCCS {{259 0 0-4456 {}}} CYCLES {}}
+set a(0-4456) {NAME ACC1:not#156 TYPE NOT PAR 0-4427 XREFS 29186 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15869224999999998} PREDS {{146 0 0-4451 {}} {259 0 0-4455 {}}} SUCCS {{259 0 0-4457 {}}} CYCLES {}}
+set a(0-4457) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#133 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 29187 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.08517242833641131 1 0.2298763533364113} PREDS {{146 0 0-4451 {}} {258 0 0-4454 {}} {259 0 0-4456 {}}} SUCCS {{258 0 0-4461 {}}} CYCLES {}}
+set a(0-4458) {NAME regs.regs:slc(regs.regs(0))#2 TYPE READSLICE PAR 0-4427 XREFS 29188 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15869224999999998} PREDS {{146 0 0-4451 {}} {258 0 0-4452 {}}} SUCCS {{259 0 0-4459 {}}} CYCLES {}}
+set a(0-4459) {NAME ACC1:not#157 TYPE NOT PAR 0-4427 XREFS 29189 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15869224999999998} PREDS {{146 0 0-4451 {}} {259 0 0-4458 {}}} SUCCS {{259 0 0-4460 {}}} CYCLES {}}
+set a(0-4460) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#132 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 29190 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.08517242833641131 1 0.2298763533364113} PREDS {{146 0 0-4451 {}} {259 0 0-4459 {}}} SUCCS {{259 0 0-4461 {}}} CYCLES {}}
+set a(0-4461) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME ACC1-1:acc TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-4427 XREFS 29191 LOC {1 0.07118415 1 0.085172475 1 0.085172475 1 0.16054323137342835 1 0.30524715637342836} PREDS {{146 0 0-4451 {}} {258 0 0-4457 {}} {259 0 0-4460 {}}} SUCCS {{259 0 0-4462 {}} {258 0 0-4465 {}} {258 0 0-4467 {}} {258 0 0-4472 {}} {258 0 0-4474 {}} {258 0 0-4478 {}} {258 0 0-4480 {}} {258 0 0-4482 {}} {258 0 0-4488 {}} {258 0 0-4490 {}} {258 0 0-4492 {}} {258 0 0-4496 {}} {258 0 0-4984 {}} {258 0 0-4985 {}} {258 0 0-4986 {}} {258 0 0-4987 {}} {258 0 0-4988 {}} {258 0 0-4990 {}} {258 0 0-4991 {}} {258 0 0-4992 {}} {258 0 0-4993 {}} {258 0 0-4996 {}} {258 0 0-4997 {}} {258 0 0-4998 {}} {258 0 0-5001 {}} {258 0 0-5004 {}} {258 0 0-5007 {}} {258 0 0-5013 {}} {258 0 0-5016 {}} {258 0 0-5024 {}} {258 0 0-5027 {}} {258 0 0-5033 {}} {258 0 0-5036 {}} {258 0 0-5047 {}} {258 0 0-5051 {}} {258 0 0-5057 {}} {258 0 0-5058 {}} {258 0 0-5062 {}} {258 0 0-5069 {}} {258 0 0-5070 {}} {258 0 0-5071 {}} {258 0 0-5074 {}} {258 0 0-5076 {}} {258 0 0-5081 {}} {258 0 0-5082 {}} {258 0 0-5083 {}} {258 0 0-5084 {}} {258 0 0-5087 {}} {258 0 0-5088 {}} {258 0 0-5092 {}} {258 0 0-5093 {}} {258 0 0-5094 {}} {258 0 0-5096 {}} {258 0 0-5098 {}} {258 0 0-5101 {}} {258 0 0-5104 {}} {258 0 0-5106 {}} {258 0 0-5119 {}} {258 0 0-5120 {}} {258 0 0-5122 {}} {258 0 0-5123 {}} {258 0 0-5124 {}} {258 0 0-5125 {}} {258 0 0-5126 {}}} CYCLES {}}
+set a(0-4462) {NAME ACC1-1:slc(acc.psp)#11 TYPE READSLICE PAR 0-4427 XREFS 29192 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.32992167499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4461 {}}} SUCCS {{259 0 0-4463 {}}} CYCLES {}}
+set a(0-4463) {NAME ACC1-1:not#151 TYPE NOT PAR 0-4427 XREFS 29193 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.32992167499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4462 {}}} SUCCS {{259 0 0-4464 {}}} CYCLES {}}
+set a(0-4464) {NAME ACC1:conc#447 TYPE CONCATENATE PAR 0-4427 XREFS 29194 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.32992167499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4463 {}}} SUCCS {{258 0 0-4469 {}}} CYCLES {}}
+set a(0-4465) {NAME ACC1-1:slc(acc.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29195 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.32992167499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4466 {}}} CYCLES {}}
+set a(0-4466) {NAME ACC1-1:not#106 TYPE NOT PAR 0-4427 XREFS 29196 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.32992167499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4465 {}}} SUCCS {{258 0 0-4468 {}}} CYCLES {}}
+set a(0-4467) {NAME ACC1-1:slc(acc.psp)#8 TYPE READSLICE PAR 0-4427 XREFS 29197 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.32992167499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4468 {}}} CYCLES {}}
+set a(0-4468) {NAME ACC1:conc#448 TYPE CONCATENATE PAR 0-4427 XREFS 29198 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.32992167499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4466 {}} {259 0 0-4467 {}}} SUCCS {{259 0 0-4469 {}}} CYCLES {}}
+set a(0-4469) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1:acc#136 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-4427 XREFS 29199 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.20569051008947523 1 0.3503944350894752} PREDS {{146 0 0-4451 {}} {258 0 0-4464 {}} {259 0 0-4468 {}}} SUCCS {{259 0 0-4470 {}}} CYCLES {}}
+set a(0-4470) {NAME ACC1:slc#8 TYPE READSLICE PAR 0-4427 XREFS 29200 LOC {1 0.16702775 1 0.20569055 1 0.20569055 1 0.350394475} PREDS {{146 0 0-4451 {}} {259 0 0-4469 {}}} SUCCS {{259 0 0-4471 {}}} CYCLES {}}
+set a(0-4471) {NAME ACC1:conc#451 TYPE CONCATENATE PAR 0-4427 XREFS 29201 LOC {1 0.16702775 1 0.20569055 1 0.20569055 1 0.350394475} PREDS {{146 0 0-4451 {}} {259 0 0-4470 {}}} SUCCS {{258 0 0-4476 {}}} CYCLES {}}
+set a(0-4472) {NAME ACC1-1:slc(acc.psp) TYPE READSLICE PAR 0-4427 XREFS 29202 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.350394475} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4473 {}}} CYCLES {}}
+set a(0-4473) {NAME ACC1:conc#442 TYPE CONCATENATE PAR 0-4427 XREFS 29203 LOC {1 0.14655495 1 0.20569055 1 0.20569055 1 0.350394475} PREDS {{146 0 0-4451 {}} {259 0 0-4472 {}}} SUCCS {{258 0 0-4475 {}}} CYCLES {}}
+set a(0-4474) {NAME ACC1-1:slc(acc.psp)#10 TYPE READSLICE PAR 0-4427 XREFS 29204 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.350394475} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4475 {}}} CYCLES {}}
+set a(0-4475) {NAME ACC1:conc#452 TYPE CONCATENATE PAR 0-4427 XREFS 29205 LOC {1 0.14655495 1 0.20569055 1 0.20569055 1 0.350394475} PREDS {{146 0 0-4451 {}} {258 0 0-4473 {}} {259 0 0-4474 {}}} SUCCS {{259 0 0-4476 {}}} CYCLES {}}
+set a(0-4476) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#138 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 29206 LOC {1 0.16702775 1 0.20569055 1 0.20569055 1 0.24888244517895047 1 0.3935863701789505} PREDS {{146 0 0-4451 {}} {258 0 0-4471 {}} {259 0 0-4475 {}}} SUCCS {{259 0 0-4477 {}}} CYCLES {}}
+set a(0-4477) {NAME ACC1:slc#10 TYPE READSLICE PAR 0-4427 XREFS 29207 LOC {1 0.21021969999999998 1 0.24888249999999998 1 0.24888249999999998 1 0.39358642499999996} PREDS {{146 0 0-4451 {}} {259 0 0-4476 {}}} SUCCS {{258 0 0-4501 {}}} CYCLES {}}
+set a(0-4478) {NAME ACC1-1:slc(acc.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 29208 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4479 {}}} CYCLES {}}
+set a(0-4479) {NAME ACC1:conc#445 TYPE CONCATENATE PAR 0-4427 XREFS 29209 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-4451 {}} {259 0 0-4478 {}}} SUCCS {{258 0 0-4485 {}}} CYCLES {}}
+set a(0-4480) {NAME ACC1-1:slc(acc.psp)#3 TYPE READSLICE PAR 0-4427 XREFS 29210 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4481 {}}} CYCLES {}}
+set a(0-4481) {NAME ACC1-1:not#107 TYPE NOT PAR 0-4427 XREFS 29211 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-4451 {}} {259 0 0-4480 {}}} SUCCS {{258 0 0-4484 {}}} CYCLES {}}
+set a(0-4482) {NAME ACC1-1:slc(acc.psp)#7 TYPE READSLICE PAR 0-4427 XREFS 29212 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4483 {}}} CYCLES {}}
+set a(0-4483) {NAME ACC1-1:not#109 TYPE NOT PAR 0-4427 XREFS 29213 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-4451 {}} {259 0 0-4482 {}}} SUCCS {{259 0 0-4484 {}}} CYCLES {}}
+set a(0-4484) {NAME ACC1:conc#446 TYPE CONCATENATE PAR 0-4427 XREFS 29214 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-4451 {}} {258 0 0-4481 {}} {259 0 0-4483 {}}} SUCCS {{259 0 0-4485 {}}} CYCLES {}}
+set a(0-4485) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#135 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29215 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.20132628508947523 1 0.3460302100894752} PREDS {{146 0 0-4451 {}} {258 0 0-4479 {}} {259 0 0-4484 {}}} SUCCS {{259 0 0-4486 {}}} CYCLES {}}
+set a(0-4486) {NAME ACC1:slc#7 TYPE READSLICE PAR 0-4427 XREFS 29216 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.34603025} PREDS {{146 0 0-4451 {}} {259 0 0-4485 {}}} SUCCS {{259 0 0-4487 {}}} CYCLES {}}
+set a(0-4487) {NAME ACC1:conc#449 TYPE CONCATENATE PAR 0-4427 XREFS 29217 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.34603025} PREDS {{146 0 0-4451 {}} {259 0 0-4486 {}}} SUCCS {{258 0 0-4499 {}}} CYCLES {}}
+set a(0-4488) {NAME ACC1-1:slc(acc.psp)#4 TYPE READSLICE PAR 0-4427 XREFS 29218 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4489 {}}} CYCLES {}}
+set a(0-4489) {NAME ACC1:conc#443 TYPE CONCATENATE PAR 0-4427 XREFS 29219 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-4451 {}} {259 0 0-4488 {}}} SUCCS {{258 0 0-4494 {}}} CYCLES {}}
+set a(0-4490) {NAME ACC1-1:slc(acc.psp)#5 TYPE READSLICE PAR 0-4427 XREFS 29220 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4491 {}}} CYCLES {}}
+set a(0-4491) {NAME ACC1-1:not#108 TYPE NOT PAR 0-4427 XREFS 29221 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-4451 {}} {259 0 0-4490 {}}} SUCCS {{258 0 0-4493 {}}} CYCLES {}}
+set a(0-4492) {NAME ACC1-1:slc(acc.psp)#6 TYPE READSLICE PAR 0-4427 XREFS 29222 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4493 {}}} CYCLES {}}
+set a(0-4493) {NAME ACC1:conc#444 TYPE CONCATENATE PAR 0-4427 XREFS 29223 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.3052472} PREDS {{146 0 0-4451 {}} {258 0 0-4491 {}} {259 0 0-4492 {}}} SUCCS {{259 0 0-4494 {}}} CYCLES {}}
+set a(0-4494) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#134 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29224 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.20132628508947523 1 0.3460302100894752} PREDS {{146 0 0-4451 {}} {258 0 0-4489 {}} {259 0 0-4493 {}}} SUCCS {{259 0 0-4495 {}}} CYCLES {}}
+set a(0-4495) {NAME ACC1:slc#9 TYPE READSLICE PAR 0-4427 XREFS 29225 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.34603025} PREDS {{146 0 0-4451 {}} {259 0 0-4494 {}}} SUCCS {{258 0 0-4498 {}}} CYCLES {}}
+set a(0-4496) {NAME ACC1-1:slc(acc.psp)#9 TYPE READSLICE PAR 0-4427 XREFS 29226 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.34603025} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4497 {}}} CYCLES {}}
+set a(0-4497) {NAME ACC1-1:not#110 TYPE NOT PAR 0-4427 XREFS 29227 LOC {1 0.14655495 1 0.201326325 1 0.201326325 1 0.34603025} PREDS {{146 0 0-4451 {}} {259 0 0-4496 {}}} SUCCS {{259 0 0-4498 {}}} CYCLES {}}
+set a(0-4498) {NAME ACC1:conc#450 TYPE CONCATENATE PAR 0-4427 XREFS 29228 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.34603025} PREDS {{146 0 0-4451 {}} {258 0 0-4495 {}} {259 0 0-4497 {}}} SUCCS {{259 0 0-4499 {}}} CYCLES {}}
+set a(0-4499) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#137 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29229 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.24888245207082718 1 0.39358637707082716} PREDS {{146 0 0-4451 {}} {258 0 0-4487 {}} {259 0 0-4498 {}}} SUCCS {{259 0 0-4500 {}}} CYCLES {}}
+set a(0-4500) {NAME ACC1:slc TYPE READSLICE PAR 0-4427 XREFS 29230 LOC {1 0.23489417499999998 1 0.24888249999999998 1 0.24888249999999998 1 0.39358642499999996} PREDS {{146 0 0-4451 {}} {259 0 0-4499 {}}} SUCCS {{259 0 0-4501 {}}} CYCLES {}}
+set a(0-4501) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1-1:acc#107 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-4427 XREFS 29231 LOC {1 0.23489417499999998 1 0.24888249999999998 1 0.24888249999999998 1 0.28191927017895047 1 0.4266231951789505} PREDS {{146 0 0-4451 {}} {258 0 0-4477 {}} {259 0 0-4500 {}}} SUCCS {{259 0 0-4502 {}} {258 0 0-4504 {}} {258 0 0-4506 {}} {258 0 0-4510 {}} {258 0 0-5038 {}} {258 0 0-5050 {}} {258 0 0-5061 {}} {258 0 0-5064 {}}} CYCLES {}}
+set a(0-4502) {NAME ACC1-1:slc(ACC1:acc#107.psp) TYPE READSLICE PAR 0-4427 XREFS 29232 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.42662324999999995} PREDS {{146 0 0-4451 {}} {259 0 0-4501 {}}} SUCCS {{259 0 0-4503 {}}} CYCLES {}}
+set a(0-4503) {NAME ACC1:conc#453 TYPE CONCATENATE PAR 0-4427 XREFS 29233 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.42662324999999995} PREDS {{146 0 0-4451 {}} {259 0 0-4502 {}}} SUCCS {{258 0 0-4508 {}}} CYCLES {}}
+set a(0-4504) {NAME ACC1-1:slc(ACC1:acc#107.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29234 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.42662324999999995} PREDS {{146 0 0-4451 {}} {258 0 0-4501 {}}} SUCCS {{259 0 0-4505 {}}} CYCLES {}}
+set a(0-4505) {NAME ACC1-1:not#133 TYPE NOT PAR 0-4427 XREFS 29235 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.42662324999999995} PREDS {{146 0 0-4451 {}} {259 0 0-4504 {}}} SUCCS {{258 0 0-4507 {}}} CYCLES {}}
+set a(0-4506) {NAME ACC1-1:slc(ACC1:acc#107.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 29236 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.42662324999999995} PREDS {{146 0 0-4451 {}} {258 0 0-4501 {}}} SUCCS {{259 0 0-4507 {}}} CYCLES {}}
+set a(0-4507) {NAME ACC1:conc#454 TYPE CONCATENATE PAR 0-4427 XREFS 29237 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.42662324999999995} PREDS {{146 0 0-4451 {}} {258 0 0-4505 {}} {259 0 0-4506 {}}} SUCCS {{259 0 0-4508 {}}} CYCLES {}}
+set a(0-4508) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#139 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29238 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.3227023350894752 1 0.46740626008947517} PREDS {{146 0 0-4451 {}} {258 0 0-4503 {}} {259 0 0-4507 {}}} SUCCS {{259 0 0-4509 {}}} CYCLES {}}
+set a(0-4509) {NAME ACC1:slc#11 TYPE READSLICE PAR 0-4427 XREFS 29239 LOC {1 0.30871404999999996 1 0.322702375 1 0.322702375 1 0.4674063} PREDS {{146 0 0-4451 {}} {259 0 0-4508 {}}} SUCCS {{258 0 0-4512 {}}} CYCLES {}}
+set a(0-4510) {NAME ACC1-1:slc(ACC1:acc#107.psp)#3 TYPE READSLICE PAR 0-4427 XREFS 29240 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.4674063} PREDS {{146 0 0-4451 {}} {258 0 0-4501 {}}} SUCCS {{259 0 0-4511 {}}} CYCLES {}}
+set a(0-4511) {NAME ACC1-1:not#153 TYPE NOT PAR 0-4427 XREFS 29241 LOC {1 0.267931 1 0.322702375 1 0.322702375 1 0.4674063} PREDS {{146 0 0-4451 {}} {259 0 0-4510 {}}} SUCCS {{259 0 0-4512 {}}} CYCLES {}}
+set a(0-4512) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1-1:acc#116 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-4427 XREFS 29242 LOC {1 0.30871404999999996 1 0.322702375 1 0.322702375 1 0.3431751350894752 1 0.48787906008947524} PREDS {{146 0 0-4451 {}} {258 0 0-4509 {}} {259 0 0-4511 {}}} SUCCS {{259 0 0-4513 {}} {258 0 0-4516 {}} {258 0 0-5055 {}}} CYCLES {}}
+set a(0-4513) {NAME ACC1-1:slc(ACC1:acc#116.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29243 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.48787909999999995} PREDS {{146 0 0-4451 {}} {259 0 0-4512 {}}} SUCCS {{259 0 0-4514 {}}} CYCLES {}}
+set a(0-4514) {NAME ACC1-1:not#145 TYPE NOT PAR 0-4427 XREFS 29244 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.48787909999999995} PREDS {{146 0 0-4451 {}} {259 0 0-4513 {}}} SUCCS {{259 0 0-4515 {}}} CYCLES {}}
+set a(0-4515) {NAME ACC1:conc#455 TYPE CONCATENATE PAR 0-4427 XREFS 29245 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.48787909999999995} PREDS {{146 0 0-4451 {}} {259 0 0-4514 {}}} SUCCS {{258 0 0-4518 {}}} CYCLES {}}
+set a(0-4516) {NAME ACC1-1:slc(ACC1:acc#116.psp) TYPE READSLICE PAR 0-4427 XREFS 29246 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.48787909999999995} PREDS {{146 0 0-4451 {}} {258 0 0-4512 {}}} SUCCS {{259 0 0-4517 {}}} CYCLES {}}
+set a(0-4517) {NAME ACC1:conc#456 TYPE CONCATENATE PAR 0-4427 XREFS 29247 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.48787909999999995} PREDS {{146 0 0-4451 {}} {259 0 0-4516 {}}} SUCCS {{259 0 0-4518 {}}} CYCLES {}}
+set a(0-4518) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#140 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29248 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.3704210520708272 1 0.5151249770708272} PREDS {{146 0 0-4451 {}} {258 0 0-4515 {}} {259 0 0-4517 {}}} SUCCS {{259 0 0-4519 {}}} CYCLES {}}
+set a(0-4519) {NAME ACC1:slc#12 TYPE READSLICE PAR 0-4427 XREFS 29249 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-4451 {}} {259 0 0-4518 {}}} SUCCS {{259 0 0-4520 {}} {258 0 0-4522 {}} {258 0 0-4524 {}} {258 0 0-5018 {}} {258 0 0-5029 {}}} CYCLES {}}
+set a(0-4520) {NAME ACC1-1:slc(acc.imod#2) TYPE READSLICE PAR 0-4427 XREFS 29250 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-4451 {}} {259 0 0-4519 {}}} SUCCS {{259 0 0-4521 {}}} CYCLES {}}
+set a(0-4521) {NAME ACC1:conc#458 TYPE CONCATENATE PAR 0-4427 XREFS 29251 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-4451 {}} {259 0 0-4520 {}}} SUCCS {{258 0 0-4527 {}}} CYCLES {}}
+set a(0-4522) {NAME ACC1-1:slc(acc.imod#2)#1 TYPE READSLICE PAR 0-4427 XREFS 29252 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-4451 {}} {258 0 0-4519 {}}} SUCCS {{259 0 0-4523 {}}} CYCLES {}}
+set a(0-4523) {NAME ACC1-1:not#25 TYPE NOT PAR 0-4427 XREFS 29253 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-4451 {}} {259 0 0-4522 {}}} SUCCS {{258 0 0-4526 {}}} CYCLES {}}
+set a(0-4524) {NAME ACC1-1:slc(acc.imod#2)#2 TYPE READSLICE PAR 0-4427 XREFS 29254 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-4451 {}} {258 0 0-4519 {}}} SUCCS {{259 0 0-4525 {}}} CYCLES {}}
+set a(0-4525) {NAME ACC1-1:not#26 TYPE NOT PAR 0-4427 XREFS 29255 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-4451 {}} {259 0 0-4524 {}}} SUCCS {{259 0 0-4526 {}}} CYCLES {}}
+set a(0-4526) {NAME ACC1:conc#459 TYPE CONCATENATE PAR 0-4427 XREFS 29256 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.515125025} PREDS {{146 0 0-4451 {}} {258 0 0-4523 {}} {259 0 0-4525 {}}} SUCCS {{259 0 0-4527 {}}} CYCLES {}}
+set a(0-4527) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#141 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29257 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3976669770708272 1 0.5423709020708272} PREDS {{146 0 0-4451 {}} {258 0 0-4521 {}} {259 0 0-4526 {}}} SUCCS {{259 0 0-4528 {}}} CYCLES {}}
+set a(0-4528) {NAME ACC1:slc#13 TYPE READSLICE PAR 0-4427 XREFS 29258 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-4527 {}}} SUCCS {{258 0 0-5006 {}} {258 0 0-5107 {}} {258 0 0-5109 {}}} CYCLES {}}
+set a(0-4529) {NAME regs.regs:slc(regs.regs(0))#3 TYPE READSLICE PAR 0-4427 XREFS 29259 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.25126634999999997} PREDS {{146 0 0-4451 {}} {258 0 0-4452 {}}} SUCCS {{259 0 0-4530 {}}} CYCLES {}}
+set a(0-4530) {NAME ACC1:not#158 TYPE NOT PAR 0-4427 XREFS 29260 LOC {1 0.0 1 0.063759975 1 0.063759975 1 0.25126634999999997} PREDS {{146 0 0-4451 {}} {259 0 0-4529 {}}} SUCCS {{258 0 0-4533 {}}} CYCLES {}}
+set a(0-4531) {NAME regs.regs:slc(regs.regs(0))#4 TYPE READSLICE PAR 0-4427 XREFS 29261 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.25126634999999997} PREDS {{146 0 0-4451 {}} {258 0 0-4452 {}}} SUCCS {{259 0 0-4532 {}}} CYCLES {}}
+set a(0-4532) {NAME ACC1:not#159 TYPE NOT PAR 0-4427 XREFS 29262 LOC {1 0.0 1 0.063759975 1 0.063759975 1 0.25126634999999997} PREDS {{146 0 0-4451 {}} {259 0 0-4531 {}}} SUCCS {{259 0 0-4533 {}}} CYCLES {}}
+set a(0-4533) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#143 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 29263 LOC {1 0.0 1 0.063759975 1 0.063759975 1 0.1349440783364113 1 0.3224504533364113} PREDS {{146 0 0-4451 {}} {258 0 0-4530 {}} {259 0 0-4532 {}}} SUCCS {{258 0 0-4537 {}}} CYCLES {}}
+set a(0-4534) {NAME regs.regs:slc(regs.regs(0))#5 TYPE READSLICE PAR 0-4427 XREFS 29264 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.25126634999999997} PREDS {{146 0 0-4451 {}} {258 0 0-4452 {}}} SUCCS {{259 0 0-4535 {}}} CYCLES {}}
+set a(0-4535) {NAME ACC1:not#160 TYPE NOT PAR 0-4427 XREFS 29265 LOC {1 0.0 1 0.063759975 1 0.063759975 1 0.25126634999999997} PREDS {{146 0 0-4451 {}} {259 0 0-4534 {}}} SUCCS {{259 0 0-4536 {}}} CYCLES {}}
+set a(0-4536) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#142 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 29266 LOC {1 0.0 1 0.063759975 1 0.063759975 1 0.1349440783364113 1 0.3224504533364113} PREDS {{146 0 0-4451 {}} {259 0 0-4535 {}}} SUCCS {{259 0 0-4537 {}}} CYCLES {}}
+set a(0-4537) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME ACC1-1:acc#125 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-4427 XREFS 29267 LOC {1 0.07118415 1 0.134944125 1 0.134944125 1 0.21031488137342835 1 0.39782125637342836} PREDS {{146 0 0-4451 {}} {258 0 0-4533 {}} {259 0 0-4536 {}}} SUCCS {{259 0 0-4538 {}} {258 0 0-4541 {}} {258 0 0-4543 {}} {258 0 0-4545 {}} {258 0 0-4550 {}} {258 0 0-4556 {}} {258 0 0-4558 {}} {258 0 0-4560 {}} {258 0 0-4565 {}} {258 0 0-4567 {}} {258 0 0-4571 {}} {258 0 0-5512 {}}} CYCLES {}}
+set a(0-4538) {NAME ACC1-1:slc(acc#5.psp)#39 TYPE READSLICE PAR 0-4427 XREFS 29268 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.43860435} PREDS {{146 0 0-4451 {}} {259 0 0-4537 {}}} SUCCS {{259 0 0-4539 {}}} CYCLES {}}
+set a(0-4539) {NAME ACC1-1:not#115 TYPE NOT PAR 0-4427 XREFS 29269 LOC {1 0.14655495 1 0.251097975 1 0.251097975 1 0.43860435} PREDS {{146 0 0-4451 {}} {259 0 0-4538 {}}} SUCCS {{259 0 0-4540 {}}} CYCLES {}}
+set a(0-4540) {NAME ACC1:conc#467 TYPE CONCATENATE PAR 0-4427 XREFS 29270 LOC {1 0.14655495 1 0.251097975 1 0.251097975 1 0.43860435} PREDS {{146 0 0-4451 {}} {259 0 0-4539 {}}} SUCCS {{258 0 0-4553 {}}} CYCLES {}}
+set a(0-4541) {NAME ACC1-1:slc(acc#5.psp)#40 TYPE READSLICE PAR 0-4427 XREFS 29271 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-4451 {}} {258 0 0-4537 {}}} SUCCS {{259 0 0-4542 {}}} CYCLES {}}
+set a(0-4542) {NAME ACC1:conc#463 TYPE CONCATENATE PAR 0-4427 XREFS 29272 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-4451 {}} {259 0 0-4541 {}}} SUCCS {{258 0 0-4548 {}}} CYCLES {}}
+set a(0-4543) {NAME ACC1-1:slc(acc#5.psp)#41 TYPE READSLICE PAR 0-4427 XREFS 29273 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-4451 {}} {258 0 0-4537 {}}} SUCCS {{259 0 0-4544 {}}} CYCLES {}}
+set a(0-4544) {NAME ACC1-1:not#116 TYPE NOT PAR 0-4427 XREFS 29274 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-4451 {}} {259 0 0-4543 {}}} SUCCS {{258 0 0-4547 {}}} CYCLES {}}
+set a(0-4545) {NAME ACC1-1:slc(acc#5.psp)#45 TYPE READSLICE PAR 0-4427 XREFS 29275 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-4451 {}} {258 0 0-4537 {}}} SUCCS {{259 0 0-4546 {}}} CYCLES {}}
+set a(0-4546) {NAME ACC1-1:not#118 TYPE NOT PAR 0-4427 XREFS 29276 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-4451 {}} {259 0 0-4545 {}}} SUCCS {{259 0 0-4547 {}}} CYCLES {}}
+set a(0-4547) {NAME ACC1:conc#464 TYPE CONCATENATE PAR 0-4427 XREFS 29277 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.3978213} PREDS {{146 0 0-4451 {}} {258 0 0-4544 {}} {259 0 0-4546 {}}} SUCCS {{259 0 0-4548 {}}} CYCLES {}}
+set a(0-4548) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#145 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29278 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.2510979350894752 1 0.4386043100894752} PREDS {{146 0 0-4451 {}} {258 0 0-4542 {}} {259 0 0-4547 {}}} SUCCS {{259 0 0-4549 {}}} CYCLES {}}
+set a(0-4549) {NAME ACC1:slc#15 TYPE READSLICE PAR 0-4427 XREFS 29279 LOC {1 0.187338 1 0.251097975 1 0.251097975 1 0.43860435} PREDS {{146 0 0-4451 {}} {259 0 0-4548 {}}} SUCCS {{258 0 0-4552 {}}} CYCLES {}}
+set a(0-4550) {NAME ACC1-1:slc(acc#5.psp)#47 TYPE READSLICE PAR 0-4427 XREFS 29280 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.43860435} PREDS {{146 0 0-4451 {}} {258 0 0-4537 {}}} SUCCS {{259 0 0-4551 {}}} CYCLES {}}
+set a(0-4551) {NAME ACC1-1:not#119 TYPE NOT PAR 0-4427 XREFS 29281 LOC {1 0.14655495 1 0.251097975 1 0.251097975 1 0.43860435} PREDS {{146 0 0-4451 {}} {259 0 0-4550 {}}} SUCCS {{259 0 0-4552 {}}} CYCLES {}}
+set a(0-4552) {NAME ACC1:conc#468 TYPE CONCATENATE PAR 0-4427 XREFS 29282 LOC {1 0.187338 1 0.251097975 1 0.251097975 1 0.43860435} PREDS {{146 0 0-4451 {}} {258 0 0-4549 {}} {259 0 0-4551 {}}} SUCCS {{259 0 0-4553 {}}} CYCLES {}}
+set a(0-4553) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#147 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-4427 XREFS 29283 LOC {1 0.187338 1 0.251097975 1 0.251097975 1 0.2841347451789505 1 0.4716411201789505} PREDS {{146 0 0-4451 {}} {258 0 0-4540 {}} {259 0 0-4552 {}}} SUCCS {{259 0 0-4554 {}}} CYCLES {}}
+set a(0-4554) {NAME ACC1:slc#17 TYPE READSLICE PAR 0-4427 XREFS 29284 LOC {1 0.220374825 1 0.28413479999999997 1 0.28413479999999997 1 0.47164117499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4553 {}}} SUCCS {{259 0 0-4555 {}}} CYCLES {}}
+set a(0-4555) {NAME ACC1:conc#469 TYPE CONCATENATE PAR 0-4427 XREFS 29285 LOC {1 0.220374825 1 0.28413479999999997 1 0.28413479999999997 1 0.47164117499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4554 {}}} SUCCS {{258 0 0-4573 {}}} CYCLES {}}
+set a(0-4556) {NAME ACC1-1:slc(acc#5.psp)#42 TYPE READSLICE PAR 0-4427 XREFS 29286 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.4036122} PREDS {{146 0 0-4451 {}} {258 0 0-4537 {}}} SUCCS {{259 0 0-4557 {}}} CYCLES {}}
+set a(0-4557) {NAME ACC1:conc#461 TYPE CONCATENATE PAR 0-4427 XREFS 29287 LOC {1 0.14655495 1 0.216105825 1 0.216105825 1 0.4036122} PREDS {{146 0 0-4451 {}} {259 0 0-4556 {}}} SUCCS {{258 0 0-4562 {}}} CYCLES {}}
+set a(0-4558) {NAME ACC1-1:slc(acc#5.psp)#43 TYPE READSLICE PAR 0-4427 XREFS 29288 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.4036122} PREDS {{146 0 0-4451 {}} {258 0 0-4537 {}}} SUCCS {{259 0 0-4559 {}}} CYCLES {}}
+set a(0-4559) {NAME ACC1-1:not#117 TYPE NOT PAR 0-4427 XREFS 29289 LOC {1 0.14655495 1 0.216105825 1 0.216105825 1 0.4036122} PREDS {{146 0 0-4451 {}} {259 0 0-4558 {}}} SUCCS {{258 0 0-4561 {}}} CYCLES {}}
+set a(0-4560) {NAME ACC1-1:slc(acc#5.psp)#44 TYPE READSLICE PAR 0-4427 XREFS 29290 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.4036122} PREDS {{146 0 0-4451 {}} {258 0 0-4537 {}}} SUCCS {{259 0 0-4561 {}}} CYCLES {}}
+set a(0-4561) {NAME ACC1:conc#462 TYPE CONCATENATE PAR 0-4427 XREFS 29291 LOC {1 0.14655495 1 0.216105825 1 0.216105825 1 0.4036122} PREDS {{146 0 0-4451 {}} {258 0 0-4559 {}} {259 0 0-4560 {}}} SUCCS {{259 0 0-4562 {}}} CYCLES {}}
+set a(0-4562) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#144 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29292 LOC {1 0.14655495 1 0.216105825 1 0.216105825 1 0.25688883508947524 1 0.44439521008947525} PREDS {{146 0 0-4451 {}} {258 0 0-4557 {}} {259 0 0-4561 {}}} SUCCS {{259 0 0-4563 {}}} CYCLES {}}
+set a(0-4563) {NAME ACC1:slc#14 TYPE READSLICE PAR 0-4427 XREFS 29293 LOC {1 0.187338 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4562 {}}} SUCCS {{259 0 0-4564 {}}} CYCLES {}}
+set a(0-4564) {NAME ACC1:conc#465 TYPE CONCATENATE PAR 0-4427 XREFS 29294 LOC {1 0.187338 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4563 {}}} SUCCS {{258 0 0-4569 {}}} CYCLES {}}
+set a(0-4565) {NAME ACC1-1:slc(acc#5.psp)#49 TYPE READSLICE PAR 0-4427 XREFS 29295 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.44439524999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4537 {}}} SUCCS {{259 0 0-4566 {}}} CYCLES {}}
+set a(0-4566) {NAME ACC1-1:not#120 TYPE NOT PAR 0-4427 XREFS 29296 LOC {1 0.14655495 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4565 {}}} SUCCS {{258 0 0-4568 {}}} CYCLES {}}
+set a(0-4567) {NAME ACC1-1:slc(acc#5.psp)#46 TYPE READSLICE PAR 0-4427 XREFS 29297 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.44439524999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4537 {}}} SUCCS {{259 0 0-4568 {}}} CYCLES {}}
+set a(0-4568) {NAME ACC1:conc#466 TYPE CONCATENATE PAR 0-4427 XREFS 29298 LOC {1 0.14655495 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4566 {}} {259 0 0-4567 {}}} SUCCS {{259 0 0-4569 {}}} CYCLES {}}
+set a(0-4569) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#146 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29299 LOC {1 0.187338 1 0.25688887499999996 1 0.25688887499999996 1 0.28413475207082717 1 0.47164112707082717} PREDS {{146 0 0-4451 {}} {258 0 0-4564 {}} {259 0 0-4568 {}}} SUCCS {{259 0 0-4570 {}}} CYCLES {}}
+set a(0-4570) {NAME ACC1:slc#16 TYPE READSLICE PAR 0-4427 XREFS 29300 LOC {1 0.21458392499999998 1 0.28413479999999997 1 0.28413479999999997 1 0.47164117499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4569 {}}} SUCCS {{258 0 0-4572 {}}} CYCLES {}}
+set a(0-4571) {NAME ACC1-1:slc(acc#5.psp)#48 TYPE READSLICE PAR 0-4427 XREFS 29301 LOC {1 0.14655495 1 0.21031492499999999 1 0.21031492499999999 1 0.47164117499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4537 {}}} SUCCS {{259 0 0-4572 {}}} CYCLES {}}
+set a(0-4572) {NAME ACC1:conc#470 TYPE CONCATENATE PAR 0-4427 XREFS 29302 LOC {1 0.21458392499999998 1 0.28413479999999997 1 0.28413479999999997 1 0.47164117499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4570 {}} {259 0 0-4571 {}}} SUCCS {{259 0 0-4573 {}}} CYCLES {}}
+set a(0-4573) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#148 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 29303 LOC {1 0.220374825 1 0.28413479999999997 1 0.28413479999999997 1 0.32242425949693604 1 0.509930634496936} PREDS {{146 0 0-4451 {}} {258 0 0-4555 {}} {259 0 0-4572 {}}} SUCCS {{259 0 0-4574 {}}} CYCLES {}}
+set a(0-4574) {NAME ACC1:slc#18 TYPE READSLICE PAR 0-4427 XREFS 29304 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-4451 {}} {259 0 0-4573 {}}} SUCCS {{259 0 0-4575 {}} {258 0 0-4577 {}} {258 0 0-4579 {}} {258 0 0-4583 {}} {258 0 0-5513 {}}} CYCLES {}}
+set a(0-4575) {NAME ACC1-1:slc(ACC1:acc#110.psp) TYPE READSLICE PAR 0-4427 XREFS 29305 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-4451 {}} {259 0 0-4574 {}}} SUCCS {{259 0 0-4576 {}}} CYCLES {}}
+set a(0-4576) {NAME ACC1:conc#471 TYPE CONCATENATE PAR 0-4427 XREFS 29306 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-4451 {}} {259 0 0-4575 {}}} SUCCS {{258 0 0-4581 {}}} CYCLES {}}
+set a(0-4577) {NAME ACC1-1:slc(ACC1:acc#110.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29307 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-4451 {}} {258 0 0-4574 {}}} SUCCS {{259 0 0-4578 {}}} CYCLES {}}
+set a(0-4578) {NAME ACC1-1:not#137 TYPE NOT PAR 0-4427 XREFS 29308 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-4451 {}} {259 0 0-4577 {}}} SUCCS {{258 0 0-4580 {}}} CYCLES {}}
+set a(0-4579) {NAME ACC1-1:slc(ACC1:acc#110.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 29309 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-4451 {}} {258 0 0-4574 {}}} SUCCS {{259 0 0-4580 {}}} CYCLES {}}
+set a(0-4580) {NAME ACC1:conc#472 TYPE CONCATENATE PAR 0-4427 XREFS 29310 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.509930675} PREDS {{146 0 0-4451 {}} {258 0 0-4578 {}} {259 0 0-4579 {}}} SUCCS {{259 0 0-4581 {}}} CYCLES {}}
+set a(0-4581) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#149 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29311 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.36320731008947527 1 0.5507136850894753} PREDS {{146 0 0-4451 {}} {258 0 0-4576 {}} {259 0 0-4580 {}}} SUCCS {{259 0 0-4582 {}}} CYCLES {}}
+set a(0-4582) {NAME ACC1:slc#19 TYPE READSLICE PAR 0-4427 XREFS 29312 LOC {1 0.29944737499999996 1 0.36320735 1 0.36320735 1 0.5507137249999999} PREDS {{146 0 0-4451 {}} {259 0 0-4581 {}}} SUCCS {{258 0 0-4585 {}}} CYCLES {}}
+set a(0-4583) {NAME ACC1-1:slc(ACC1:acc#110.psp)#3 TYPE READSLICE PAR 0-4427 XREFS 29313 LOC {1 0.258664325 1 0.3224243 1 0.3224243 1 0.5507137249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4574 {}}} SUCCS {{259 0 0-4584 {}}} CYCLES {}}
+set a(0-4584) {NAME ACC1-1:not#154 TYPE NOT PAR 0-4427 XREFS 29314 LOC {1 0.258664325 1 0.36320735 1 0.36320735 1 0.5507137249999999} PREDS {{146 0 0-4451 {}} {259 0 0-4583 {}}} SUCCS {{259 0 0-4585 {}}} CYCLES {}}
+set a(0-4585) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1-1:acc#118 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-4427 XREFS 29315 LOC {1 0.29944737499999996 1 0.36320735 1 0.36320735 1 0.3836801100894752 1 0.5711864850894752} PREDS {{146 0 0-4451 {}} {258 0 0-4582 {}} {259 0 0-4584 {}}} SUCCS {{259 0 0-4586 {}} {258 0 0-4589 {}} {258 0 0-5511 {}}} CYCLES {}}
+set a(0-4586) {NAME ACC1-1:slc(ACC1:acc#118.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29316 LOC {1 0.319920175 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-4451 {}} {259 0 0-4585 {}}} SUCCS {{259 0 0-4587 {}}} CYCLES {}}
+set a(0-4587) {NAME ACC1-1:not#147 TYPE NOT PAR 0-4427 XREFS 29317 LOC {1 0.319920175 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-4451 {}} {259 0 0-4586 {}}} SUCCS {{259 0 0-4588 {}}} CYCLES {}}
+set a(0-4588) {NAME ACC1:conc#473 TYPE CONCATENATE PAR 0-4427 XREFS 29318 LOC {1 0.319920175 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-4451 {}} {259 0 0-4587 {}}} SUCCS {{258 0 0-4591 {}}} CYCLES {}}
+set a(0-4589) {NAME ACC1-1:slc(ACC1:acc#118.psp) TYPE READSLICE PAR 0-4427 XREFS 29319 LOC {1 0.319920175 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-4451 {}} {258 0 0-4585 {}}} SUCCS {{259 0 0-4590 {}}} CYCLES {}}
+set a(0-4590) {NAME ACC1:conc#474 TYPE CONCATENATE PAR 0-4427 XREFS 29320 LOC {1 0.319920175 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-4451 {}} {259 0 0-4589 {}}} SUCCS {{259 0 0-4591 {}}} CYCLES {}}
+set a(0-4591) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#150 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29321 LOC {1 0.319920175 1 0.38368015 1 0.38368015 1 0.41092602707082715 1 0.5984324020708272} PREDS {{146 0 0-4451 {}} {258 0 0-4588 {}} {259 0 0-4590 {}}} SUCCS {{259 0 0-4592 {}}} CYCLES {}}
+set a(0-4592) {NAME ACC1:slc#20 TYPE READSLICE PAR 0-4427 XREFS 29322 LOC {1 0.3471661 1 0.410926075 1 0.410926075 1 0.59843245} PREDS {{146 0 0-4451 {}} {259 0 0-4591 {}}} SUCCS {{259 0 0-4593 {}} {258 0 0-4595 {}} {258 0 0-4597 {}} {258 0 0-5509 {}}} CYCLES {}}
+set a(0-4593) {NAME ACC1-1:slc(acc.imod#6) TYPE READSLICE PAR 0-4427 XREFS 29323 LOC {1 0.3471661 1 0.410926075 1 0.410926075 1 0.61762915} PREDS {{146 0 0-4451 {}} {259 0 0-4592 {}}} SUCCS {{259 0 0-4594 {}}} CYCLES {}}
+set a(0-4594) {NAME ACC1:conc#476 TYPE CONCATENATE PAR 0-4427 XREFS 29324 LOC {1 0.3471661 1 0.43012277499999996 1 0.43012277499999996 1 0.61762915} PREDS {{146 0 0-4451 {}} {259 0 0-4593 {}}} SUCCS {{258 0 0-4600 {}}} CYCLES {}}
+set a(0-4595) {NAME ACC1-1:slc(acc.imod#6)#1 TYPE READSLICE PAR 0-4427 XREFS 29325 LOC {1 0.3471661 1 0.410926075 1 0.410926075 1 0.61762915} PREDS {{146 0 0-4451 {}} {258 0 0-4592 {}}} SUCCS {{259 0 0-4596 {}}} CYCLES {}}
+set a(0-4596) {NAME ACC1-1:not#57 TYPE NOT PAR 0-4427 XREFS 29326 LOC {1 0.3471661 1 0.43012277499999996 1 0.43012277499999996 1 0.61762915} PREDS {{146 0 0-4451 {}} {259 0 0-4595 {}}} SUCCS {{258 0 0-4599 {}}} CYCLES {}}
+set a(0-4597) {NAME ACC1-1:slc(acc.imod#6)#2 TYPE READSLICE PAR 0-4427 XREFS 29327 LOC {1 0.3471661 1 0.410926075 1 0.410926075 1 0.61762915} PREDS {{146 0 0-4451 {}} {258 0 0-4592 {}}} SUCCS {{259 0 0-4598 {}}} CYCLES {}}
+set a(0-4598) {NAME ACC1-1:not#58 TYPE NOT PAR 0-4427 XREFS 29328 LOC {1 0.3471661 1 0.43012277499999996 1 0.43012277499999996 1 0.61762915} PREDS {{146 0 0-4451 {}} {259 0 0-4597 {}}} SUCCS {{259 0 0-4599 {}}} CYCLES {}}
+set a(0-4599) {NAME ACC1:conc#477 TYPE CONCATENATE PAR 0-4427 XREFS 29329 LOC {1 0.3471661 1 0.43012277499999996 1 0.43012277499999996 1 0.61762915} PREDS {{146 0 0-4451 {}} {258 0 0-4596 {}} {259 0 0-4598 {}}} SUCCS {{259 0 0-4600 {}}} CYCLES {}}
+set a(0-4600) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#151 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29330 LOC {1 0.3471661 1 0.43012277499999996 1 0.43012277499999996 1 0.4573686520708271 1 0.6448750270708271} PREDS {{146 0 0-4451 {}} {258 0 0-4594 {}} {259 0 0-4599 {}}} SUCCS {{259 0 0-4601 {}}} CYCLES {}}
+set a(0-4601) {NAME ACC1:slc#21 TYPE READSLICE PAR 0-4427 XREFS 29331 LOC {1 0.374412025 1 0.45736869999999996 1 0.45736869999999996 1 0.644875075} PREDS {{146 0 0-4451 {}} {259 0 0-4600 {}}} SUCCS {{258 0 0-5510 {}}} CYCLES {}}
+set a(0-4602) {NAME regs.regs:slc(regs.regs(0))#6 TYPE READSLICE PAR 0-4427 XREFS 29332 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-4451 {}} {258 0 0-4452 {}}} SUCCS {{259 0 0-4603 {}}} CYCLES {}}
+set a(0-4603) {NAME ACC1:not#161 TYPE NOT PAR 0-4427 XREFS 29333 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-4451 {}} {259 0 0-4602 {}}} SUCCS {{258 0 0-4606 {}}} CYCLES {}}
+set a(0-4604) {NAME regs.regs:slc(regs.regs(0))#7 TYPE READSLICE PAR 0-4427 XREFS 29334 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-4451 {}} {258 0 0-4452 {}}} SUCCS {{259 0 0-4605 {}}} CYCLES {}}
+set a(0-4605) {NAME ACC1:not#162 TYPE NOT PAR 0-4427 XREFS 29335 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-4451 {}} {259 0 0-4604 {}}} SUCCS {{259 0 0-4606 {}}} CYCLES {}}
+set a(0-4606) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#153 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 29336 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.08517242833641131 1 0.08517242833641131} PREDS {{146 0 0-4451 {}} {258 0 0-4603 {}} {259 0 0-4605 {}}} SUCCS {{258 0 0-4610 {}}} CYCLES {}}
+set a(0-4607) {NAME regs.regs:slc(regs.regs(0))#8 TYPE READSLICE PAR 0-4427 XREFS 29337 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-4451 {}} {258 0 0-4452 {}}} SUCCS {{259 0 0-4608 {}}} CYCLES {}}
+set a(0-4608) {NAME ACC1:not#163 TYPE NOT PAR 0-4427 XREFS 29338 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.013988325} PREDS {{146 0 0-4451 {}} {259 0 0-4607 {}}} SUCCS {{259 0 0-4609 {}}} CYCLES {}}
+set a(0-4609) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#152 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 29339 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.08517242833641131 1 0.08517242833641131} PREDS {{146 0 0-4451 {}} {259 0 0-4608 {}}} SUCCS {{259 0 0-4610 {}}} CYCLES {}}
+set a(0-4610) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME ACC1-1:acc#10 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-4427 XREFS 29340 LOC {1 0.07118415 1 0.085172475 1 0.085172475 1 0.16054323137342835 1 0.16054323137342835} PREDS {{146 0 0-4451 {}} {258 0 0-4606 {}} {259 0 0-4609 {}}} SUCCS {{259 0 0-4611 {}} {258 0 0-4614 {}} {258 0 0-4616 {}} {258 0 0-4621 {}} {258 0 0-4623 {}} {258 0 0-4627 {}} {258 0 0-4629 {}} {258 0 0-4631 {}} {258 0 0-4637 {}} {258 0 0-4639 {}} {258 0 0-4641 {}} {258 0 0-4645 {}} {258 0 0-5281 {}} {258 0 0-5282 {}} {258 0 0-5283 {}} {258 0 0-5284 {}} {258 0 0-5285 {}} {258 0 0-5287 {}} {258 0 0-5288 {}} {258 0 0-5289 {}} {258 0 0-5290 {}} {258 0 0-5293 {}} {258 0 0-5294 {}} {258 0 0-5295 {}} {258 0 0-5298 {}} {258 0 0-5301 {}} {258 0 0-5304 {}} {258 0 0-5310 {}} {258 0 0-5313 {}} {258 0 0-5321 {}} {258 0 0-5324 {}} {258 0 0-5330 {}} {258 0 0-5333 {}} {258 0 0-5344 {}} {258 0 0-5348 {}} {258 0 0-5354 {}} {258 0 0-5355 {}} {258 0 0-5359 {}} {258 0 0-5366 {}} {258 0 0-5367 {}} {258 0 0-5368 {}} {258 0 0-5371 {}} {258 0 0-5373 {}} {258 0 0-5378 {}} {258 0 0-5379 {}} {258 0 0-5380 {}} {258 0 0-5381 {}} {258 0 0-5384 {}} {258 0 0-5385 {}} {258 0 0-5389 {}} {258 0 0-5390 {}} {258 0 0-5391 {}} {258 0 0-5393 {}} {258 0 0-5395 {}} {258 0 0-5398 {}} {258 0 0-5401 {}} {258 0 0-5403 {}} {258 0 0-5416 {}} {258 0 0-5417 {}} {258 0 0-5419 {}} {258 0 0-5420 {}} {258 0 0-5421 {}} {258 0 0-5422 {}} {258 0 0-5423 {}}} CYCLES {}}
+set a(0-4611) {NAME ACC1-1:slc(acc#10.psp)#11 TYPE READSLICE PAR 0-4427 XREFS 29341 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.18521775} PREDS {{146 0 0-4451 {}} {259 0 0-4610 {}}} SUCCS {{259 0 0-4612 {}}} CYCLES {}}
+set a(0-4612) {NAME ACC1-1:not#152 TYPE NOT PAR 0-4427 XREFS 29342 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.18521775} PREDS {{146 0 0-4451 {}} {259 0 0-4611 {}}} SUCCS {{259 0 0-4613 {}}} CYCLES {}}
+set a(0-4613) {NAME ACC1:conc#483 TYPE CONCATENATE PAR 0-4427 XREFS 29343 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.18521775} PREDS {{146 0 0-4451 {}} {259 0 0-4612 {}}} SUCCS {{258 0 0-4618 {}}} CYCLES {}}
+set a(0-4614) {NAME ACC1-1:slc(acc#10.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29344 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.18521775} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-4615 {}}} CYCLES {}}
+set a(0-4615) {NAME ACC1-1:not#124 TYPE NOT PAR 0-4427 XREFS 29345 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.18521775} PREDS {{146 0 0-4451 {}} {259 0 0-4614 {}}} SUCCS {{258 0 0-4617 {}}} CYCLES {}}
+set a(0-4616) {NAME ACC1-1:slc(acc#10.psp)#8 TYPE READSLICE PAR 0-4427 XREFS 29346 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.18521775} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-4617 {}}} CYCLES {}}
+set a(0-4617) {NAME ACC1:conc#484 TYPE CONCATENATE PAR 0-4427 XREFS 29347 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.18521775} PREDS {{146 0 0-4451 {}} {258 0 0-4615 {}} {259 0 0-4616 {}}} SUCCS {{259 0 0-4618 {}}} CYCLES {}}
+set a(0-4618) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1:acc#156 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-4427 XREFS 29348 LOC {1 0.14655495 1 0.18521775 1 0.18521775 1 0.20569051008947523 1 0.20569051008947523} PREDS {{146 0 0-4451 {}} {258 0 0-4613 {}} {259 0 0-4617 {}}} SUCCS {{259 0 0-4619 {}}} CYCLES {}}
+set a(0-4619) {NAME ACC1:slc#24 TYPE READSLICE PAR 0-4427 XREFS 29349 LOC {1 0.16702775 1 0.20569055 1 0.20569055 1 0.20569055} PREDS {{146 0 0-4451 {}} {259 0 0-4618 {}}} SUCCS {{259 0 0-4620 {}}} CYCLES {}}
+set a(0-4620) {NAME ACC1:conc#487 TYPE CONCATENATE PAR 0-4427 XREFS 29350 LOC {1 0.16702775 1 0.20569055 1 0.20569055 1 0.20569055} PREDS {{146 0 0-4451 {}} {259 0 0-4619 {}}} SUCCS {{258 0 0-4625 {}}} CYCLES {}}
+set a(0-4621) {NAME ACC1-1:slc(acc#10.psp) TYPE READSLICE PAR 0-4427 XREFS 29351 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.20569055} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-4622 {}}} CYCLES {}}
+set a(0-4622) {NAME ACC1:conc#478 TYPE CONCATENATE PAR 0-4427 XREFS 29352 LOC {1 0.14655495 1 0.20569055 1 0.20569055 1 0.20569055} PREDS {{146 0 0-4451 {}} {259 0 0-4621 {}}} SUCCS {{258 0 0-4624 {}}} CYCLES {}}
+set a(0-4623) {NAME ACC1-1:slc(acc#10.psp)#10 TYPE READSLICE PAR 0-4427 XREFS 29353 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.20569055} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-4624 {}}} CYCLES {}}
+set a(0-4624) {NAME ACC1:conc#488 TYPE CONCATENATE PAR 0-4427 XREFS 29354 LOC {1 0.14655495 1 0.20569055 1 0.20569055 1 0.20569055} PREDS {{146 0 0-4451 {}} {258 0 0-4622 {}} {259 0 0-4623 {}}} SUCCS {{259 0 0-4625 {}}} CYCLES {}}
+set a(0-4625) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#158 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 29355 LOC {1 0.16702775 1 0.20569055 1 0.20569055 1 0.24888244517895047 1 0.24888244517895047} PREDS {{146 0 0-4451 {}} {258 0 0-4620 {}} {259 0 0-4624 {}}} SUCCS {{259 0 0-4626 {}}} CYCLES {}}
+set a(0-4626) {NAME ACC1:slc#26 TYPE READSLICE PAR 0-4427 XREFS 29356 LOC {1 0.21021969999999998 1 0.24888249999999998 1 0.24888249999999998 1 0.24888249999999998} PREDS {{146 0 0-4451 {}} {259 0 0-4625 {}}} SUCCS {{258 0 0-4650 {}}} CYCLES {}}
+set a(0-4627) {NAME ACC1-1:slc(acc#10.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 29357 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-4628 {}}} CYCLES {}}
+set a(0-4628) {NAME ACC1:conc#481 TYPE CONCATENATE PAR 0-4427 XREFS 29358 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-4451 {}} {259 0 0-4627 {}}} SUCCS {{258 0 0-4634 {}}} CYCLES {}}
+set a(0-4629) {NAME ACC1-1:slc(acc#10.psp)#3 TYPE READSLICE PAR 0-4427 XREFS 29359 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-4630 {}}} CYCLES {}}
+set a(0-4630) {NAME ACC1-1:not#125 TYPE NOT PAR 0-4427 XREFS 29360 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-4451 {}} {259 0 0-4629 {}}} SUCCS {{258 0 0-4633 {}}} CYCLES {}}
+set a(0-4631) {NAME ACC1-1:slc(acc#10.psp)#7 TYPE READSLICE PAR 0-4427 XREFS 29361 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-4632 {}}} CYCLES {}}
+set a(0-4632) {NAME ACC1-1:not#127 TYPE NOT PAR 0-4427 XREFS 29362 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-4451 {}} {259 0 0-4631 {}}} SUCCS {{259 0 0-4633 {}}} CYCLES {}}
+set a(0-4633) {NAME ACC1:conc#482 TYPE CONCATENATE PAR 0-4427 XREFS 29363 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4630 {}} {259 0 0-4632 {}}} SUCCS {{259 0 0-4634 {}}} CYCLES {}}
+set a(0-4634) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#155 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29364 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.20132628508947523 1 0.20132628508947523} PREDS {{146 0 0-4451 {}} {258 0 0-4628 {}} {259 0 0-4633 {}}} SUCCS {{259 0 0-4635 {}}} CYCLES {}}
+set a(0-4635) {NAME ACC1:slc#23 TYPE READSLICE PAR 0-4427 XREFS 29365 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.201326325} PREDS {{146 0 0-4451 {}} {259 0 0-4634 {}}} SUCCS {{259 0 0-4636 {}}} CYCLES {}}
+set a(0-4636) {NAME ACC1:conc#485 TYPE CONCATENATE PAR 0-4427 XREFS 29366 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.201326325} PREDS {{146 0 0-4451 {}} {259 0 0-4635 {}}} SUCCS {{258 0 0-4648 {}}} CYCLES {}}
+set a(0-4637) {NAME ACC1-1:slc(acc#10.psp)#4 TYPE READSLICE PAR 0-4427 XREFS 29367 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-4638 {}}} CYCLES {}}
+set a(0-4638) {NAME ACC1:conc#479 TYPE CONCATENATE PAR 0-4427 XREFS 29368 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-4451 {}} {259 0 0-4637 {}}} SUCCS {{258 0 0-4643 {}}} CYCLES {}}
+set a(0-4639) {NAME ACC1-1:slc(acc#10.psp)#5 TYPE READSLICE PAR 0-4427 XREFS 29369 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-4640 {}}} CYCLES {}}
+set a(0-4640) {NAME ACC1-1:not#126 TYPE NOT PAR 0-4427 XREFS 29370 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-4451 {}} {259 0 0-4639 {}}} SUCCS {{258 0 0-4642 {}}} CYCLES {}}
+set a(0-4641) {NAME ACC1-1:slc(acc#10.psp)#6 TYPE READSLICE PAR 0-4427 XREFS 29371 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-4642 {}}} CYCLES {}}
+set a(0-4642) {NAME ACC1:conc#480 TYPE CONCATENATE PAR 0-4427 XREFS 29372 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.16054327499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4640 {}} {259 0 0-4641 {}}} SUCCS {{259 0 0-4643 {}}} CYCLES {}}
+set a(0-4643) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#154 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29373 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.20132628508947523 1 0.20132628508947523} PREDS {{146 0 0-4451 {}} {258 0 0-4638 {}} {259 0 0-4642 {}}} SUCCS {{259 0 0-4644 {}}} CYCLES {}}
+set a(0-4644) {NAME ACC1:slc#22 TYPE READSLICE PAR 0-4427 XREFS 29374 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.201326325} PREDS {{146 0 0-4451 {}} {259 0 0-4643 {}}} SUCCS {{258 0 0-4647 {}}} CYCLES {}}
+set a(0-4645) {NAME ACC1-1:slc(acc#10.psp)#9 TYPE READSLICE PAR 0-4427 XREFS 29375 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.201326325} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-4646 {}}} CYCLES {}}
+set a(0-4646) {NAME ACC1-1:not#128 TYPE NOT PAR 0-4427 XREFS 29376 LOC {1 0.14655495 1 0.201326325 1 0.201326325 1 0.201326325} PREDS {{146 0 0-4451 {}} {259 0 0-4645 {}}} SUCCS {{259 0 0-4647 {}}} CYCLES {}}
+set a(0-4647) {NAME ACC1:conc#486 TYPE CONCATENATE PAR 0-4427 XREFS 29377 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.201326325} PREDS {{146 0 0-4451 {}} {258 0 0-4644 {}} {259 0 0-4646 {}}} SUCCS {{259 0 0-4648 {}}} CYCLES {}}
+set a(0-4648) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#157 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29378 LOC {1 0.187338 1 0.201326325 1 0.201326325 1 0.24888245207082718 1 0.24888245207082718} PREDS {{146 0 0-4451 {}} {258 0 0-4636 {}} {259 0 0-4647 {}}} SUCCS {{259 0 0-4649 {}}} CYCLES {}}
+set a(0-4649) {NAME ACC1:slc#25 TYPE READSLICE PAR 0-4427 XREFS 29379 LOC {1 0.23489417499999998 1 0.24888249999999998 1 0.24888249999999998 1 0.24888249999999998} PREDS {{146 0 0-4451 {}} {259 0 0-4648 {}}} SUCCS {{259 0 0-4650 {}}} CYCLES {}}
+set a(0-4650) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1-1:acc#113 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-4427 XREFS 29380 LOC {1 0.23489417499999998 1 0.24888249999999998 1 0.24888249999999998 1 0.28191927017895047 1 0.28191927017895047} PREDS {{146 0 0-4451 {}} {258 0 0-4626 {}} {259 0 0-4649 {}}} SUCCS {{259 0 0-4651 {}} {258 0 0-4653 {}} {258 0 0-4655 {}} {258 0 0-4659 {}} {258 0 0-5335 {}} {258 0 0-5347 {}} {258 0 0-5358 {}} {258 0 0-5361 {}}} CYCLES {}}
+set a(0-4651) {NAME ACC1-1:slc(ACC1:acc#113.psp) TYPE READSLICE PAR 0-4427 XREFS 29381 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.281919325} PREDS {{146 0 0-4451 {}} {259 0 0-4650 {}}} SUCCS {{259 0 0-4652 {}}} CYCLES {}}
+set a(0-4652) {NAME ACC1:conc#489 TYPE CONCATENATE PAR 0-4427 XREFS 29382 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.281919325} PREDS {{146 0 0-4451 {}} {259 0 0-4651 {}}} SUCCS {{258 0 0-4657 {}}} CYCLES {}}
+set a(0-4653) {NAME ACC1-1:slc(ACC1:acc#113.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29383 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.281919325} PREDS {{146 0 0-4451 {}} {258 0 0-4650 {}}} SUCCS {{259 0 0-4654 {}}} CYCLES {}}
+set a(0-4654) {NAME ACC1-1:not#141 TYPE NOT PAR 0-4427 XREFS 29384 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.281919325} PREDS {{146 0 0-4451 {}} {259 0 0-4653 {}}} SUCCS {{258 0 0-4656 {}}} CYCLES {}}
+set a(0-4655) {NAME ACC1-1:slc(ACC1:acc#113.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 29385 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.281919325} PREDS {{146 0 0-4451 {}} {258 0 0-4650 {}}} SUCCS {{259 0 0-4656 {}}} CYCLES {}}
+set a(0-4656) {NAME ACC1:conc#490 TYPE CONCATENATE PAR 0-4427 XREFS 29386 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.281919325} PREDS {{146 0 0-4451 {}} {258 0 0-4654 {}} {259 0 0-4655 {}}} SUCCS {{259 0 0-4657 {}}} CYCLES {}}
+set a(0-4657) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#159 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29387 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.3227023350894752 1 0.3227023350894752} PREDS {{146 0 0-4451 {}} {258 0 0-4652 {}} {259 0 0-4656 {}}} SUCCS {{259 0 0-4658 {}}} CYCLES {}}
+set a(0-4658) {NAME ACC1:slc#27 TYPE READSLICE PAR 0-4427 XREFS 29388 LOC {1 0.30871404999999996 1 0.322702375 1 0.322702375 1 0.322702375} PREDS {{146 0 0-4451 {}} {259 0 0-4657 {}}} SUCCS {{258 0 0-4661 {}}} CYCLES {}}
+set a(0-4659) {NAME ACC1-1:slc(ACC1:acc#113.psp)#3 TYPE READSLICE PAR 0-4427 XREFS 29389 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.322702375} PREDS {{146 0 0-4451 {}} {258 0 0-4650 {}}} SUCCS {{259 0 0-4660 {}}} CYCLES {}}
+set a(0-4660) {NAME ACC1-1:not#155 TYPE NOT PAR 0-4427 XREFS 29390 LOC {1 0.267931 1 0.322702375 1 0.322702375 1 0.322702375} PREDS {{146 0 0-4451 {}} {259 0 0-4659 {}}} SUCCS {{259 0 0-4661 {}}} CYCLES {}}
+set a(0-4661) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1-1:acc#120 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-4427 XREFS 29391 LOC {1 0.30871404999999996 1 0.322702375 1 0.322702375 1 0.3431751350894752 1 0.3431751350894752} PREDS {{146 0 0-4451 {}} {258 0 0-4658 {}} {259 0 0-4660 {}}} SUCCS {{259 0 0-4662 {}} {258 0 0-4665 {}} {258 0 0-5352 {}}} CYCLES {}}
+set a(0-4662) {NAME ACC1-1:slc(ACC1:acc#120.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29392 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.343175175} PREDS {{146 0 0-4451 {}} {259 0 0-4661 {}}} SUCCS {{259 0 0-4663 {}}} CYCLES {}}
+set a(0-4663) {NAME ACC1-1:not#149 TYPE NOT PAR 0-4427 XREFS 29393 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.343175175} PREDS {{146 0 0-4451 {}} {259 0 0-4662 {}}} SUCCS {{259 0 0-4664 {}}} CYCLES {}}
+set a(0-4664) {NAME ACC1:conc#491 TYPE CONCATENATE PAR 0-4427 XREFS 29394 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.343175175} PREDS {{146 0 0-4451 {}} {259 0 0-4663 {}}} SUCCS {{258 0 0-4667 {}}} CYCLES {}}
+set a(0-4665) {NAME ACC1-1:slc(ACC1:acc#120.psp) TYPE READSLICE PAR 0-4427 XREFS 29395 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.343175175} PREDS {{146 0 0-4451 {}} {258 0 0-4661 {}}} SUCCS {{259 0 0-4666 {}}} CYCLES {}}
+set a(0-4666) {NAME ACC1:conc#492 TYPE CONCATENATE PAR 0-4427 XREFS 29396 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.343175175} PREDS {{146 0 0-4451 {}} {259 0 0-4665 {}}} SUCCS {{259 0 0-4667 {}}} CYCLES {}}
+set a(0-4667) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#160 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29397 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.3704210520708272 1 0.3704210520708272} PREDS {{146 0 0-4451 {}} {258 0 0-4664 {}} {259 0 0-4666 {}}} SUCCS {{259 0 0-4668 {}}} CYCLES {}}
+set a(0-4668) {NAME ACC1:slc#28 TYPE READSLICE PAR 0-4427 XREFS 29398 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-4451 {}} {259 0 0-4667 {}}} SUCCS {{259 0 0-4669 {}} {258 0 0-4671 {}} {258 0 0-4673 {}} {258 0 0-5315 {}} {258 0 0-5326 {}}} CYCLES {}}
+set a(0-4669) {NAME ACC1-1:slc(acc.imod#10) TYPE READSLICE PAR 0-4427 XREFS 29399 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-4451 {}} {259 0 0-4668 {}}} SUCCS {{259 0 0-4670 {}}} CYCLES {}}
+set a(0-4670) {NAME ACC1:conc#494 TYPE CONCATENATE PAR 0-4427 XREFS 29400 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-4451 {}} {259 0 0-4669 {}}} SUCCS {{258 0 0-4676 {}}} CYCLES {}}
+set a(0-4671) {NAME ACC1-1:slc(acc.imod#10)#1 TYPE READSLICE PAR 0-4427 XREFS 29401 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-4451 {}} {258 0 0-4668 {}}} SUCCS {{259 0 0-4672 {}}} CYCLES {}}
+set a(0-4672) {NAME ACC1-1:not#89 TYPE NOT PAR 0-4427 XREFS 29402 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-4451 {}} {259 0 0-4671 {}}} SUCCS {{258 0 0-4675 {}}} CYCLES {}}
+set a(0-4673) {NAME ACC1-1:slc(acc.imod#10)#2 TYPE READSLICE PAR 0-4427 XREFS 29403 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-4451 {}} {258 0 0-4668 {}}} SUCCS {{259 0 0-4674 {}}} CYCLES {}}
+set a(0-4674) {NAME ACC1-1:not#90 TYPE NOT PAR 0-4427 XREFS 29404 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-4451 {}} {259 0 0-4673 {}}} SUCCS {{259 0 0-4675 {}}} CYCLES {}}
+set a(0-4675) {NAME ACC1:conc#495 TYPE CONCATENATE PAR 0-4427 XREFS 29405 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3704211} PREDS {{146 0 0-4451 {}} {258 0 0-4672 {}} {259 0 0-4674 {}}} SUCCS {{259 0 0-4676 {}}} CYCLES {}}
+set a(0-4676) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#161 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29406 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.3976669770708272 1 0.3976669770708272} PREDS {{146 0 0-4451 {}} {258 0 0-4670 {}} {259 0 0-4675 {}}} SUCCS {{259 0 0-4677 {}}} CYCLES {}}
+set a(0-4677) {NAME ACC1:slc#29 TYPE READSLICE PAR 0-4427 XREFS 29407 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-4676 {}}} SUCCS {{258 0 0-5303 {}} {258 0 0-5404 {}} {258 0 0-5406 {}}} CYCLES {}}
+set a(0-4678) {NAME regs.regs:asn TYPE ASSIGN PAR 0-4427 XREFS 29408 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.295092075} PREDS {{146 0 0-4451 {}} {262 0 0-5952 {}}} SUCCS {{259 0 0-4679 {}} {256 0 0-5952 {}}} CYCLES {}}
+set a(0-4679) {NAME regs.regs:slc(regs.regs(2))#1 TYPE READSLICE PAR 0-4427 XREFS 29409 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.295092075} PREDS {{146 0 0-4451 {}} {259 0 0-4678 {}}} SUCCS {{258 0 0-4682 {}}} CYCLES {}}
+set a(0-4680) {NAME regs.regs:asn#1 TYPE ASSIGN PAR 0-4427 XREFS 29410 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.295092075} PREDS {{146 0 0-4451 {}} {262 0 0-5952 {}}} SUCCS {{259 0 0-4681 {}} {256 0 0-5952 {}}} CYCLES {}}
+set a(0-4681) {NAME regs.regs:slc(regs.regs(2))#2 TYPE READSLICE PAR 0-4427 XREFS 29411 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.295092075} PREDS {{146 0 0-4451 {}} {259 0 0-4680 {}}} SUCCS {{259 0 0-4682 {}}} CYCLES {}}
+set a(0-4682) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#162 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 29412 LOC {1 0.0 1 0.15038815 1 0.15038815 1 0.2215722533364113 1 0.36627617833641135} PREDS {{146 0 0-4451 {}} {258 0 0-4679 {}} {259 0 0-4681 {}}} SUCCS {{258 0 0-4685 {}}} CYCLES {}}
+set a(0-4683) {NAME regs.regs:asn#2 TYPE ASSIGN PAR 0-4427 XREFS 29413 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.366276225} PREDS {{146 0 0-4451 {}} {262 0 0-5952 {}}} SUCCS {{259 0 0-4684 {}} {256 0 0-5952 {}}} CYCLES {}}
+set a(0-4684) {NAME regs.regs:slc(regs.regs(2)) TYPE READSLICE PAR 0-4427 XREFS 29414 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.366276225} PREDS {{146 0 0-4451 {}} {259 0 0-4683 {}}} SUCCS {{259 0 0-4685 {}}} CYCLES {}}
+set a(0-4685) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME ACC1-3:acc TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-4427 XREFS 29415 LOC {1 0.07118415 1 0.2215723 1 0.2215723 1 0.2969430563734284 1 0.4416469813734284} PREDS {{146 0 0-4451 {}} {258 0 0-4682 {}} {259 0 0-4684 {}}} SUCCS {{259 0 0-4686 {}} {258 0 0-4689 {}} {258 0 0-4691 {}} {258 0 0-4696 {}} {258 0 0-4698 {}} {258 0 0-4702 {}} {258 0 0-4704 {}} {258 0 0-4706 {}} {258 0 0-4712 {}} {258 0 0-4714 {}} {258 0 0-4716 {}} {258 0 0-4720 {}} {258 0 0-4900 {}} {258 0 0-4901 {}} {258 0 0-4902 {}} {258 0 0-4904 {}} {258 0 0-4908 {}} {258 0 0-4914 {}} {258 0 0-4915 {}} {258 0 0-4919 {}} {258 0 0-4926 {}} {258 0 0-4927 {}} {258 0 0-4928 {}} {258 0 0-4931 {}} {258 0 0-4933 {}} {258 0 0-4938 {}} {258 0 0-4939 {}} {258 0 0-4940 {}} {258 0 0-4941 {}} {258 0 0-4944 {}} {258 0 0-4945 {}} {258 0 0-4949 {}} {258 0 0-4950 {}} {258 0 0-4951 {}} {258 0 0-4953 {}} {258 0 0-4955 {}} {258 0 0-4958 {}} {258 0 0-4961 {}} {258 0 0-4963 {}} {258 0 0-4975 {}} {258 0 0-4976 {}} {258 0 0-4977 {}} {258 0 0-4978 {}} {258 0 0-4979 {}} {258 0 0-5131 {}} {258 0 0-5132 {}} {258 0 0-5133 {}} {258 0 0-5134 {}} {258 0 0-5135 {}} {258 0 0-5137 {}} {258 0 0-5138 {}} {258 0 0-5139 {}} {258 0 0-5140 {}} {258 0 0-5143 {}} {258 0 0-5144 {}} {258 0 0-5145 {}} {258 0 0-5148 {}} {258 0 0-5151 {}} {258 0 0-5154 {}} {258 0 0-5160 {}} {258 0 0-5163 {}} {258 0 0-5171 {}} {258 0 0-5174 {}} {258 0 0-5180 {}} {258 0 0-5183 {}}} CYCLES {}}
+set a(0-4686) {NAME ACC1-3:slc(acc.psp)#11 TYPE READSLICE PAR 0-4427 XREFS 29416 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.4663215} PREDS {{146 0 0-4451 {}} {259 0 0-4685 {}}} SUCCS {{259 0 0-4687 {}}} CYCLES {}}
+set a(0-4687) {NAME ACC1-3:not#151 TYPE NOT PAR 0-4427 XREFS 29417 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.4663215} PREDS {{146 0 0-4451 {}} {259 0 0-4686 {}}} SUCCS {{259 0 0-4688 {}}} CYCLES {}}
+set a(0-4688) {NAME ACC1:conc#501 TYPE CONCATENATE PAR 0-4427 XREFS 29418 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.4663215} PREDS {{146 0 0-4451 {}} {259 0 0-4687 {}}} SUCCS {{258 0 0-4693 {}}} CYCLES {}}
+set a(0-4689) {NAME ACC1-3:slc(acc.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29419 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.4663215} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4690 {}}} CYCLES {}}
+set a(0-4690) {NAME ACC1-3:not#106 TYPE NOT PAR 0-4427 XREFS 29420 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.4663215} PREDS {{146 0 0-4451 {}} {259 0 0-4689 {}}} SUCCS {{258 0 0-4692 {}}} CYCLES {}}
+set a(0-4691) {NAME ACC1-3:slc(acc.psp)#8 TYPE READSLICE PAR 0-4427 XREFS 29421 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.4663215} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4692 {}}} CYCLES {}}
+set a(0-4692) {NAME ACC1:conc#502 TYPE CONCATENATE PAR 0-4427 XREFS 29422 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.4663215} PREDS {{146 0 0-4451 {}} {258 0 0-4690 {}} {259 0 0-4691 {}}} SUCCS {{259 0 0-4693 {}}} CYCLES {}}
+set a(0-4693) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1:acc#165 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-4427 XREFS 29423 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.34209033508947523 1 0.48679426008947524} PREDS {{146 0 0-4451 {}} {258 0 0-4688 {}} {259 0 0-4692 {}}} SUCCS {{259 0 0-4694 {}}} CYCLES {}}
+set a(0-4694) {NAME ACC1:slc#32 TYPE READSLICE PAR 0-4427 XREFS 29424 LOC {1 0.16702775 1 0.342090375 1 0.342090375 1 0.48679429999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4693 {}}} SUCCS {{259 0 0-4695 {}}} CYCLES {}}
+set a(0-4695) {NAME ACC1:conc#505 TYPE CONCATENATE PAR 0-4427 XREFS 29425 LOC {1 0.16702775 1 0.342090375 1 0.342090375 1 0.48679429999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4694 {}}} SUCCS {{258 0 0-4700 {}}} CYCLES {}}
+set a(0-4696) {NAME ACC1-3:slc(acc.psp) TYPE READSLICE PAR 0-4427 XREFS 29426 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.48679429999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4697 {}}} CYCLES {}}
+set a(0-4697) {NAME ACC1:conc#496 TYPE CONCATENATE PAR 0-4427 XREFS 29427 LOC {1 0.14655495 1 0.342090375 1 0.342090375 1 0.48679429999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4696 {}}} SUCCS {{258 0 0-4699 {}}} CYCLES {}}
+set a(0-4698) {NAME ACC1-3:slc(acc.psp)#10 TYPE READSLICE PAR 0-4427 XREFS 29428 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.48679429999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4699 {}}} CYCLES {}}
+set a(0-4699) {NAME ACC1:conc#506 TYPE CONCATENATE PAR 0-4427 XREFS 29429 LOC {1 0.14655495 1 0.342090375 1 0.342090375 1 0.48679429999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4697 {}} {259 0 0-4698 {}}} SUCCS {{259 0 0-4700 {}}} CYCLES {}}
+set a(0-4700) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#167 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 29430 LOC {1 0.16702775 1 0.342090375 1 0.342090375 1 0.3852822701789505 1 0.5299861951789504} PREDS {{146 0 0-4451 {}} {258 0 0-4695 {}} {259 0 0-4699 {}}} SUCCS {{259 0 0-4701 {}}} CYCLES {}}
+set a(0-4701) {NAME ACC1:slc#34 TYPE READSLICE PAR 0-4427 XREFS 29431 LOC {1 0.21021969999999998 1 0.385282325 1 0.385282325 1 0.52998625} PREDS {{146 0 0-4451 {}} {259 0 0-4700 {}}} SUCCS {{258 0 0-4725 {}}} CYCLES {}}
+set a(0-4702) {NAME ACC1-3:slc(acc.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 29432 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4703 {}}} CYCLES {}}
+set a(0-4703) {NAME ACC1:conc#499 TYPE CONCATENATE PAR 0-4427 XREFS 29433 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4702 {}}} SUCCS {{258 0 0-4709 {}}} CYCLES {}}
+set a(0-4704) {NAME ACC1-3:slc(acc.psp)#3 TYPE READSLICE PAR 0-4427 XREFS 29434 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4705 {}}} CYCLES {}}
+set a(0-4705) {NAME ACC1-3:not#107 TYPE NOT PAR 0-4427 XREFS 29435 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4704 {}}} SUCCS {{258 0 0-4708 {}}} CYCLES {}}
+set a(0-4706) {NAME ACC1-3:slc(acc.psp)#7 TYPE READSLICE PAR 0-4427 XREFS 29436 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4707 {}}} CYCLES {}}
+set a(0-4707) {NAME ACC1-3:not#109 TYPE NOT PAR 0-4427 XREFS 29437 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4706 {}}} SUCCS {{259 0 0-4708 {}}} CYCLES {}}
+set a(0-4708) {NAME ACC1:conc#500 TYPE CONCATENATE PAR 0-4427 XREFS 29438 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4705 {}} {259 0 0-4707 {}}} SUCCS {{259 0 0-4709 {}}} CYCLES {}}
+set a(0-4709) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#164 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29439 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.3377261100894752 1 0.48243003508947524} PREDS {{146 0 0-4451 {}} {258 0 0-4703 {}} {259 0 0-4708 {}}} SUCCS {{259 0 0-4710 {}}} CYCLES {}}
+set a(0-4710) {NAME ACC1:slc#31 TYPE READSLICE PAR 0-4427 XREFS 29440 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.48243007499999996} PREDS {{146 0 0-4451 {}} {259 0 0-4709 {}}} SUCCS {{259 0 0-4711 {}}} CYCLES {}}
+set a(0-4711) {NAME ACC1:conc#503 TYPE CONCATENATE PAR 0-4427 XREFS 29441 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.48243007499999996} PREDS {{146 0 0-4451 {}} {259 0 0-4710 {}}} SUCCS {{258 0 0-4723 {}}} CYCLES {}}
+set a(0-4712) {NAME ACC1-3:slc(acc.psp)#4 TYPE READSLICE PAR 0-4427 XREFS 29442 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4713 {}}} CYCLES {}}
+set a(0-4713) {NAME ACC1:conc#497 TYPE CONCATENATE PAR 0-4427 XREFS 29443 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4712 {}}} SUCCS {{258 0 0-4718 {}}} CYCLES {}}
+set a(0-4714) {NAME ACC1-3:slc(acc.psp)#5 TYPE READSLICE PAR 0-4427 XREFS 29444 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4715 {}}} CYCLES {}}
+set a(0-4715) {NAME ACC1-3:not#108 TYPE NOT PAR 0-4427 XREFS 29445 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4714 {}}} SUCCS {{258 0 0-4717 {}}} CYCLES {}}
+set a(0-4716) {NAME ACC1-3:slc(acc.psp)#6 TYPE READSLICE PAR 0-4427 XREFS 29446 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4717 {}}} CYCLES {}}
+set a(0-4717) {NAME ACC1:conc#498 TYPE CONCATENATE PAR 0-4427 XREFS 29447 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.44164702499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4715 {}} {259 0 0-4716 {}}} SUCCS {{259 0 0-4718 {}}} CYCLES {}}
+set a(0-4718) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#163 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29448 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.3377261100894752 1 0.48243003508947524} PREDS {{146 0 0-4451 {}} {258 0 0-4713 {}} {259 0 0-4717 {}}} SUCCS {{259 0 0-4719 {}}} CYCLES {}}
+set a(0-4719) {NAME ACC1:slc#30 TYPE READSLICE PAR 0-4427 XREFS 29449 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.48243007499999996} PREDS {{146 0 0-4451 {}} {259 0 0-4718 {}}} SUCCS {{258 0 0-4722 {}}} CYCLES {}}
+set a(0-4720) {NAME ACC1-3:slc(acc.psp)#9 TYPE READSLICE PAR 0-4427 XREFS 29450 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.48243007499999996} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4721 {}}} CYCLES {}}
+set a(0-4721) {NAME ACC1-3:not#110 TYPE NOT PAR 0-4427 XREFS 29451 LOC {1 0.14655495 1 0.33772615 1 0.33772615 1 0.48243007499999996} PREDS {{146 0 0-4451 {}} {259 0 0-4720 {}}} SUCCS {{259 0 0-4722 {}}} CYCLES {}}
+set a(0-4722) {NAME ACC1:conc#504 TYPE CONCATENATE PAR 0-4427 XREFS 29452 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.48243007499999996} PREDS {{146 0 0-4451 {}} {258 0 0-4719 {}} {259 0 0-4721 {}}} SUCCS {{259 0 0-4723 {}}} CYCLES {}}
+set a(0-4723) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#166 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29453 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.3852822770708272 1 0.5299862020708271} PREDS {{146 0 0-4451 {}} {258 0 0-4711 {}} {259 0 0-4722 {}}} SUCCS {{259 0 0-4724 {}}} CYCLES {}}
+set a(0-4724) {NAME ACC1:slc#33 TYPE READSLICE PAR 0-4427 XREFS 29454 LOC {1 0.23489417499999998 1 0.385282325 1 0.385282325 1 0.52998625} PREDS {{146 0 0-4451 {}} {259 0 0-4723 {}}} SUCCS {{259 0 0-4725 {}}} CYCLES {}}
+set a(0-4725) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1-3:acc#107 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-4427 XREFS 29455 LOC {1 0.23489417499999998 1 0.385282325 1 0.385282325 1 0.4183190951789505 1 0.5630230201789505} PREDS {{146 0 0-4451 {}} {258 0 0-4701 {}} {259 0 0-4724 {}}} SUCCS {{259 0 0-4726 {}} {258 0 0-4728 {}} {258 0 0-4730 {}} {258 0 0-4734 {}} {258 0 0-4907 {}} {258 0 0-4918 {}} {258 0 0-4921 {}} {258 0 0-5185 {}}} CYCLES {}}
+set a(0-4726) {NAME ACC1-3:slc(ACC1:acc#107.psp) TYPE READSLICE PAR 0-4427 XREFS 29456 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.5630230749999999} PREDS {{146 0 0-4451 {}} {259 0 0-4725 {}}} SUCCS {{259 0 0-4727 {}}} CYCLES {}}
+set a(0-4727) {NAME ACC1:conc#507 TYPE CONCATENATE PAR 0-4427 XREFS 29457 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.5630230749999999} PREDS {{146 0 0-4451 {}} {259 0 0-4726 {}}} SUCCS {{258 0 0-4732 {}}} CYCLES {}}
+set a(0-4728) {NAME ACC1-3:slc(ACC1:acc#107.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29458 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.5630230749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4725 {}}} SUCCS {{259 0 0-4729 {}}} CYCLES {}}
+set a(0-4729) {NAME ACC1-3:not#133 TYPE NOT PAR 0-4427 XREFS 29459 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.5630230749999999} PREDS {{146 0 0-4451 {}} {259 0 0-4728 {}}} SUCCS {{258 0 0-4731 {}}} CYCLES {}}
+set a(0-4730) {NAME ACC1-3:slc(ACC1:acc#107.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 29460 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.5630230749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4725 {}}} SUCCS {{259 0 0-4731 {}}} CYCLES {}}
+set a(0-4731) {NAME ACC1:conc#508 TYPE CONCATENATE PAR 0-4427 XREFS 29461 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.5630230749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4729 {}} {259 0 0-4730 {}}} SUCCS {{259 0 0-4732 {}}} CYCLES {}}
+set a(0-4732) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#168 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29462 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.45910216008947524 1 0.6038060850894752} PREDS {{146 0 0-4451 {}} {258 0 0-4727 {}} {259 0 0-4731 {}}} SUCCS {{259 0 0-4733 {}}} CYCLES {}}
+set a(0-4733) {NAME ACC1:slc#35 TYPE READSLICE PAR 0-4427 XREFS 29463 LOC {1 0.30871404999999996 1 0.45910219999999996 1 0.45910219999999996 1 0.603806125} PREDS {{146 0 0-4451 {}} {259 0 0-4732 {}}} SUCCS {{258 0 0-4736 {}}} CYCLES {}}
+set a(0-4734) {NAME ACC1-3:slc(ACC1:acc#107.psp)#3 TYPE READSLICE PAR 0-4427 XREFS 29464 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.603806125} PREDS {{146 0 0-4451 {}} {258 0 0-4725 {}}} SUCCS {{259 0 0-4735 {}}} CYCLES {}}
+set a(0-4735) {NAME ACC1-3:not#153 TYPE NOT PAR 0-4427 XREFS 29465 LOC {1 0.267931 1 0.45910219999999996 1 0.45910219999999996 1 0.603806125} PREDS {{146 0 0-4451 {}} {259 0 0-4734 {}}} SUCCS {{259 0 0-4736 {}}} CYCLES {}}
+set a(0-4736) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1-3:acc#116 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-4427 XREFS 29466 LOC {1 0.30871404999999996 1 0.45910219999999996 1 0.45910219999999996 1 0.4795749600894752 1 0.6242788850894753} PREDS {{146 0 0-4451 {}} {258 0 0-4733 {}} {259 0 0-4735 {}}} SUCCS {{259 0 0-4737 {}} {258 0 0-4740 {}} {258 0 0-4912 {}}} CYCLES {}}
+set a(0-4737) {NAME ACC1-3:slc(ACC1:acc#116.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29467 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.6242789249999999} PREDS {{146 0 0-4451 {}} {259 0 0-4736 {}}} SUCCS {{259 0 0-4738 {}}} CYCLES {}}
+set a(0-4738) {NAME ACC1-3:not#145 TYPE NOT PAR 0-4427 XREFS 29468 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.6242789249999999} PREDS {{146 0 0-4451 {}} {259 0 0-4737 {}}} SUCCS {{259 0 0-4739 {}}} CYCLES {}}
+set a(0-4739) {NAME ACC1:conc#509 TYPE CONCATENATE PAR 0-4427 XREFS 29469 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.6242789249999999} PREDS {{146 0 0-4451 {}} {259 0 0-4738 {}}} SUCCS {{258 0 0-4742 {}}} CYCLES {}}
+set a(0-4740) {NAME ACC1-3:slc(ACC1:acc#116.psp) TYPE READSLICE PAR 0-4427 XREFS 29470 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.6242789249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4736 {}}} SUCCS {{259 0 0-4741 {}}} CYCLES {}}
+set a(0-4741) {NAME ACC1:conc#510 TYPE CONCATENATE PAR 0-4427 XREFS 29471 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.6242789249999999} PREDS {{146 0 0-4451 {}} {259 0 0-4740 {}}} SUCCS {{259 0 0-4742 {}}} CYCLES {}}
+set a(0-4742) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#169 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29472 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.5068208770708271 1 0.6515248020708271} PREDS {{146 0 0-4451 {}} {258 0 0-4739 {}} {259 0 0-4741 {}}} SUCCS {{259 0 0-4743 {}}} CYCLES {}}
+set a(0-4743) {NAME ACC1:slc#36 TYPE READSLICE PAR 0-4427 XREFS 29473 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-4451 {}} {259 0 0-4742 {}}} SUCCS {{259 0 0-4744 {}} {258 0 0-4746 {}} {258 0 0-4748 {}} {258 0 0-5165 {}} {258 0 0-5176 {}}} CYCLES {}}
+set a(0-4744) {NAME ACC1-3:slc(acc.imod#2) TYPE READSLICE PAR 0-4427 XREFS 29474 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-4451 {}} {259 0 0-4743 {}}} SUCCS {{259 0 0-4745 {}}} CYCLES {}}
+set a(0-4745) {NAME ACC1:conc#512 TYPE CONCATENATE PAR 0-4427 XREFS 29475 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-4451 {}} {259 0 0-4744 {}}} SUCCS {{258 0 0-4751 {}}} CYCLES {}}
+set a(0-4746) {NAME ACC1-3:slc(acc.imod#2)#1 TYPE READSLICE PAR 0-4427 XREFS 29476 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4743 {}}} SUCCS {{259 0 0-4747 {}}} CYCLES {}}
+set a(0-4747) {NAME ACC1-3:not#25 TYPE NOT PAR 0-4427 XREFS 29477 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-4451 {}} {259 0 0-4746 {}}} SUCCS {{258 0 0-4750 {}}} CYCLES {}}
+set a(0-4748) {NAME ACC1-3:slc(acc.imod#2)#2 TYPE READSLICE PAR 0-4427 XREFS 29478 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4743 {}}} SUCCS {{259 0 0-4749 {}}} CYCLES {}}
+set a(0-4749) {NAME ACC1-3:not#26 TYPE NOT PAR 0-4427 XREFS 29479 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-4451 {}} {259 0 0-4748 {}}} SUCCS {{259 0 0-4750 {}}} CYCLES {}}
+set a(0-4750) {NAME ACC1:conc#513 TYPE CONCATENATE PAR 0-4427 XREFS 29480 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6515248499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4747 {}} {259 0 0-4749 {}}} SUCCS {{259 0 0-4751 {}}} CYCLES {}}
+set a(0-4751) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#170 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29481 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.5340668020708271 1 0.6787707270708271} PREDS {{146 0 0-4451 {}} {258 0 0-4745 {}} {259 0 0-4750 {}}} SUCCS {{259 0 0-4752 {}}} CYCLES {}}
+set a(0-4752) {NAME ACC1:slc#37 TYPE READSLICE PAR 0-4427 XREFS 29482 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-4751 {}}} SUCCS {{258 0 0-4964 {}} {258 0 0-4966 {}} {258 0 0-5153 {}}} CYCLES {}}
+set a(0-4753) {NAME regs.regs:asn#3 TYPE ASSIGN PAR 0-4427 XREFS 29483 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.224020425} PREDS {{146 0 0-4451 {}} {262 0 0-5952 {}}} SUCCS {{259 0 0-4754 {}} {256 0 0-5952 {}}} CYCLES {}}
+set a(0-4754) {NAME regs.regs:slc(regs.regs(2))#4 TYPE READSLICE PAR 0-4427 XREFS 29484 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.224020425} PREDS {{146 0 0-4451 {}} {259 0 0-4753 {}}} SUCCS {{258 0 0-4757 {}}} CYCLES {}}
+set a(0-4755) {NAME regs.regs:asn#4 TYPE ASSIGN PAR 0-4427 XREFS 29485 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.224020425} PREDS {{146 0 0-4451 {}} {262 0 0-5952 {}}} SUCCS {{259 0 0-4756 {}} {256 0 0-5952 {}}} CYCLES {}}
+set a(0-4756) {NAME regs.regs:slc(regs.regs(2))#5 TYPE READSLICE PAR 0-4427 XREFS 29486 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.224020425} PREDS {{146 0 0-4451 {}} {259 0 0-4755 {}}} SUCCS {{259 0 0-4757 {}}} CYCLES {}}
+set a(0-4757) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#171 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 29487 LOC {1 0.0 1 0.03651405 1 0.03651405 1 0.1076981533364113 1 0.2952045283364113} PREDS {{146 0 0-4451 {}} {258 0 0-4754 {}} {259 0 0-4756 {}}} SUCCS {{258 0 0-4760 {}}} CYCLES {}}
+set a(0-4758) {NAME regs.regs:asn#5 TYPE ASSIGN PAR 0-4427 XREFS 29488 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.29520457499999997} PREDS {{146 0 0-4451 {}} {262 0 0-5952 {}}} SUCCS {{259 0 0-4759 {}} {256 0 0-5952 {}}} CYCLES {}}
+set a(0-4759) {NAME regs.regs:slc(regs.regs(2))#3 TYPE READSLICE PAR 0-4427 XREFS 29489 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.29520457499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4758 {}}} SUCCS {{259 0 0-4760 {}}} CYCLES {}}
+set a(0-4760) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME ACC1-3:acc#125 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-4427 XREFS 29490 LOC {1 0.07118415 1 0.1076982 1 0.1076982 1 0.18306895637342835 1 0.37057533137342835} PREDS {{146 0 0-4451 {}} {258 0 0-4757 {}} {259 0 0-4759 {}}} SUCCS {{259 0 0-4761 {}} {258 0 0-4764 {}} {258 0 0-4766 {}} {258 0 0-4768 {}} {258 0 0-4773 {}} {258 0 0-4779 {}} {258 0 0-4781 {}} {258 0 0-4783 {}} {258 0 0-4788 {}} {258 0 0-4790 {}} {258 0 0-4794 {}} {258 0 0-5504 {}}} CYCLES {}}
+set a(0-4761) {NAME ACC1-3:slc(acc#5.psp)#39 TYPE READSLICE PAR 0-4427 XREFS 29491 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.41135842499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4760 {}}} SUCCS {{259 0 0-4762 {}}} CYCLES {}}
+set a(0-4762) {NAME ACC1-3:not#115 TYPE NOT PAR 0-4427 XREFS 29492 LOC {1 0.14655495 1 0.22385205 1 0.22385205 1 0.41135842499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4761 {}}} SUCCS {{259 0 0-4763 {}}} CYCLES {}}
+set a(0-4763) {NAME ACC1:conc#521 TYPE CONCATENATE PAR 0-4427 XREFS 29493 LOC {1 0.14655495 1 0.22385205 1 0.22385205 1 0.41135842499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4762 {}}} SUCCS {{258 0 0-4776 {}}} CYCLES {}}
+set a(0-4764) {NAME ACC1-3:slc(acc#5.psp)#40 TYPE READSLICE PAR 0-4427 XREFS 29494 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-4451 {}} {258 0 0-4760 {}}} SUCCS {{259 0 0-4765 {}}} CYCLES {}}
+set a(0-4765) {NAME ACC1:conc#517 TYPE CONCATENATE PAR 0-4427 XREFS 29495 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-4451 {}} {259 0 0-4764 {}}} SUCCS {{258 0 0-4771 {}}} CYCLES {}}
+set a(0-4766) {NAME ACC1-3:slc(acc#5.psp)#41 TYPE READSLICE PAR 0-4427 XREFS 29496 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-4451 {}} {258 0 0-4760 {}}} SUCCS {{259 0 0-4767 {}}} CYCLES {}}
+set a(0-4767) {NAME ACC1-3:not#116 TYPE NOT PAR 0-4427 XREFS 29497 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-4451 {}} {259 0 0-4766 {}}} SUCCS {{258 0 0-4770 {}}} CYCLES {}}
+set a(0-4768) {NAME ACC1-3:slc(acc#5.psp)#45 TYPE READSLICE PAR 0-4427 XREFS 29498 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-4451 {}} {258 0 0-4760 {}}} SUCCS {{259 0 0-4769 {}}} CYCLES {}}
+set a(0-4769) {NAME ACC1-3:not#118 TYPE NOT PAR 0-4427 XREFS 29499 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-4451 {}} {259 0 0-4768 {}}} SUCCS {{259 0 0-4770 {}}} CYCLES {}}
+set a(0-4770) {NAME ACC1:conc#518 TYPE CONCATENATE PAR 0-4427 XREFS 29500 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.370575375} PREDS {{146 0 0-4451 {}} {258 0 0-4767 {}} {259 0 0-4769 {}}} SUCCS {{259 0 0-4771 {}}} CYCLES {}}
+set a(0-4771) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#173 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29501 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.22385201008947522 1 0.4113583850894752} PREDS {{146 0 0-4451 {}} {258 0 0-4765 {}} {259 0 0-4770 {}}} SUCCS {{259 0 0-4772 {}}} CYCLES {}}
+set a(0-4772) {NAME ACC1:slc#39 TYPE READSLICE PAR 0-4427 XREFS 29502 LOC {1 0.187338 1 0.22385205 1 0.22385205 1 0.41135842499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4771 {}}} SUCCS {{258 0 0-4775 {}}} CYCLES {}}
+set a(0-4773) {NAME ACC1-3:slc(acc#5.psp)#47 TYPE READSLICE PAR 0-4427 XREFS 29503 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.41135842499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4760 {}}} SUCCS {{259 0 0-4774 {}}} CYCLES {}}
+set a(0-4774) {NAME ACC1-3:not#119 TYPE NOT PAR 0-4427 XREFS 29504 LOC {1 0.14655495 1 0.22385205 1 0.22385205 1 0.41135842499999997} PREDS {{146 0 0-4451 {}} {259 0 0-4773 {}}} SUCCS {{259 0 0-4775 {}}} CYCLES {}}
+set a(0-4775) {NAME ACC1:conc#522 TYPE CONCATENATE PAR 0-4427 XREFS 29505 LOC {1 0.187338 1 0.22385205 1 0.22385205 1 0.41135842499999997} PREDS {{146 0 0-4451 {}} {258 0 0-4772 {}} {259 0 0-4774 {}}} SUCCS {{259 0 0-4776 {}}} CYCLES {}}
+set a(0-4776) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#175 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-4427 XREFS 29506 LOC {1 0.187338 1 0.22385205 1 0.22385205 1 0.2568888201789505 1 0.4443951951789505} PREDS {{146 0 0-4451 {}} {258 0 0-4763 {}} {259 0 0-4775 {}}} SUCCS {{259 0 0-4777 {}}} CYCLES {}}
+set a(0-4777) {NAME ACC1:slc#41 TYPE READSLICE PAR 0-4427 XREFS 29507 LOC {1 0.220374825 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4776 {}}} SUCCS {{259 0 0-4778 {}}} CYCLES {}}
+set a(0-4778) {NAME ACC1:conc#523 TYPE CONCATENATE PAR 0-4427 XREFS 29508 LOC {1 0.220374825 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4777 {}}} SUCCS {{258 0 0-4796 {}}} CYCLES {}}
+set a(0-4779) {NAME ACC1-3:slc(acc#5.psp)#42 TYPE READSLICE PAR 0-4427 XREFS 29509 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.376366275} PREDS {{146 0 0-4451 {}} {258 0 0-4760 {}}} SUCCS {{259 0 0-4780 {}}} CYCLES {}}
+set a(0-4780) {NAME ACC1:conc#515 TYPE CONCATENATE PAR 0-4427 XREFS 29510 LOC {1 0.14655495 1 0.1888599 1 0.1888599 1 0.376366275} PREDS {{146 0 0-4451 {}} {259 0 0-4779 {}}} SUCCS {{258 0 0-4785 {}}} CYCLES {}}
+set a(0-4781) {NAME ACC1-3:slc(acc#5.psp)#43 TYPE READSLICE PAR 0-4427 XREFS 29511 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.376366275} PREDS {{146 0 0-4451 {}} {258 0 0-4760 {}}} SUCCS {{259 0 0-4782 {}}} CYCLES {}}
+set a(0-4782) {NAME ACC1-3:not#117 TYPE NOT PAR 0-4427 XREFS 29512 LOC {1 0.14655495 1 0.1888599 1 0.1888599 1 0.376366275} PREDS {{146 0 0-4451 {}} {259 0 0-4781 {}}} SUCCS {{258 0 0-4784 {}}} CYCLES {}}
+set a(0-4783) {NAME ACC1-3:slc(acc#5.psp)#44 TYPE READSLICE PAR 0-4427 XREFS 29513 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.376366275} PREDS {{146 0 0-4451 {}} {258 0 0-4760 {}}} SUCCS {{259 0 0-4784 {}}} CYCLES {}}
+set a(0-4784) {NAME ACC1:conc#516 TYPE CONCATENATE PAR 0-4427 XREFS 29514 LOC {1 0.14655495 1 0.1888599 1 0.1888599 1 0.376366275} PREDS {{146 0 0-4451 {}} {258 0 0-4782 {}} {259 0 0-4783 {}}} SUCCS {{259 0 0-4785 {}}} CYCLES {}}
+set a(0-4785) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#172 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29515 LOC {1 0.14655495 1 0.1888599 1 0.1888599 1 0.22964291008947524 1 0.41714928508947524} PREDS {{146 0 0-4451 {}} {258 0 0-4780 {}} {259 0 0-4784 {}}} SUCCS {{259 0 0-4786 {}}} CYCLES {}}
+set a(0-4786) {NAME ACC1:slc#38 TYPE READSLICE PAR 0-4427 XREFS 29516 LOC {1 0.187338 1 0.22964294999999998 1 0.22964294999999998 1 0.41714932499999996} PREDS {{146 0 0-4451 {}} {259 0 0-4785 {}}} SUCCS {{259 0 0-4787 {}}} CYCLES {}}
+set a(0-4787) {NAME ACC1:conc#519 TYPE CONCATENATE PAR 0-4427 XREFS 29517 LOC {1 0.187338 1 0.22964294999999998 1 0.22964294999999998 1 0.41714932499999996} PREDS {{146 0 0-4451 {}} {259 0 0-4786 {}}} SUCCS {{258 0 0-4792 {}}} CYCLES {}}
+set a(0-4788) {NAME ACC1-3:slc(acc#5.psp)#49 TYPE READSLICE PAR 0-4427 XREFS 29518 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.41714932499999996} PREDS {{146 0 0-4451 {}} {258 0 0-4760 {}}} SUCCS {{259 0 0-4789 {}}} CYCLES {}}
+set a(0-4789) {NAME ACC1-3:not#120 TYPE NOT PAR 0-4427 XREFS 29519 LOC {1 0.14655495 1 0.22964294999999998 1 0.22964294999999998 1 0.41714932499999996} PREDS {{146 0 0-4451 {}} {259 0 0-4788 {}}} SUCCS {{258 0 0-4791 {}}} CYCLES {}}
+set a(0-4790) {NAME ACC1-3:slc(acc#5.psp)#46 TYPE READSLICE PAR 0-4427 XREFS 29520 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.41714932499999996} PREDS {{146 0 0-4451 {}} {258 0 0-4760 {}}} SUCCS {{259 0 0-4791 {}}} CYCLES {}}
+set a(0-4791) {NAME ACC1:conc#520 TYPE CONCATENATE PAR 0-4427 XREFS 29521 LOC {1 0.14655495 1 0.22964294999999998 1 0.22964294999999998 1 0.41714932499999996} PREDS {{146 0 0-4451 {}} {258 0 0-4789 {}} {259 0 0-4790 {}}} SUCCS {{259 0 0-4792 {}}} CYCLES {}}
+set a(0-4792) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#174 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29522 LOC {1 0.187338 1 0.22964294999999998 1 0.22964294999999998 1 0.25688882707082716 1 0.44439520207082717} PREDS {{146 0 0-4451 {}} {258 0 0-4787 {}} {259 0 0-4791 {}}} SUCCS {{259 0 0-4793 {}}} CYCLES {}}
+set a(0-4793) {NAME ACC1:slc#40 TYPE READSLICE PAR 0-4427 XREFS 29523 LOC {1 0.21458392499999998 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4792 {}}} SUCCS {{258 0 0-4795 {}}} CYCLES {}}
+set a(0-4794) {NAME ACC1-3:slc(acc#5.psp)#48 TYPE READSLICE PAR 0-4427 XREFS 29524 LOC {1 0.14655495 1 0.18306899999999998 1 0.18306899999999998 1 0.44439524999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4760 {}}} SUCCS {{259 0 0-4795 {}}} CYCLES {}}
+set a(0-4795) {NAME ACC1:conc#524 TYPE CONCATENATE PAR 0-4427 XREFS 29525 LOC {1 0.21458392499999998 1 0.25688887499999996 1 0.25688887499999996 1 0.44439524999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4793 {}} {259 0 0-4794 {}}} SUCCS {{259 0 0-4796 {}}} CYCLES {}}
+set a(0-4796) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#176 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 29526 LOC {1 0.220374825 1 0.25688887499999996 1 0.25688887499999996 1 0.29517833449693603 1 0.48268470949693604} PREDS {{146 0 0-4451 {}} {258 0 0-4778 {}} {259 0 0-4795 {}}} SUCCS {{259 0 0-4797 {}}} CYCLES {}}
+set a(0-4797) {NAME ACC1:slc#42 TYPE READSLICE PAR 0-4427 XREFS 29527 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-4451 {}} {259 0 0-4796 {}}} SUCCS {{259 0 0-4798 {}} {258 0 0-4800 {}} {258 0 0-4802 {}} {258 0 0-4806 {}} {258 0 0-5505 {}}} CYCLES {}}
+set a(0-4798) {NAME ACC1-3:slc(ACC1:acc#110.psp) TYPE READSLICE PAR 0-4427 XREFS 29528 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-4451 {}} {259 0 0-4797 {}}} SUCCS {{259 0 0-4799 {}}} CYCLES {}}
+set a(0-4799) {NAME ACC1:conc#525 TYPE CONCATENATE PAR 0-4427 XREFS 29529 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-4451 {}} {259 0 0-4798 {}}} SUCCS {{258 0 0-4804 {}}} CYCLES {}}
+set a(0-4800) {NAME ACC1-3:slc(ACC1:acc#110.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29530 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-4451 {}} {258 0 0-4797 {}}} SUCCS {{259 0 0-4801 {}}} CYCLES {}}
+set a(0-4801) {NAME ACC1-3:not#137 TYPE NOT PAR 0-4427 XREFS 29531 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-4451 {}} {259 0 0-4800 {}}} SUCCS {{258 0 0-4803 {}}} CYCLES {}}
+set a(0-4802) {NAME ACC1-3:slc(ACC1:acc#110.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 29532 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-4451 {}} {258 0 0-4797 {}}} SUCCS {{259 0 0-4803 {}}} CYCLES {}}
+set a(0-4803) {NAME ACC1:conc#526 TYPE CONCATENATE PAR 0-4427 XREFS 29533 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.48268475} PREDS {{146 0 0-4451 {}} {258 0 0-4801 {}} {259 0 0-4802 {}}} SUCCS {{259 0 0-4804 {}}} CYCLES {}}
+set a(0-4804) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#177 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29534 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.33596138508947526 1 0.5234677600894753} PREDS {{146 0 0-4451 {}} {258 0 0-4799 {}} {259 0 0-4803 {}}} SUCCS {{259 0 0-4805 {}}} CYCLES {}}
+set a(0-4805) {NAME ACC1:slc#43 TYPE READSLICE PAR 0-4427 XREFS 29535 LOC {1 0.29944737499999996 1 0.335961425 1 0.335961425 1 0.5234677999999999} PREDS {{146 0 0-4451 {}} {259 0 0-4804 {}}} SUCCS {{258 0 0-4808 {}}} CYCLES {}}
+set a(0-4806) {NAME ACC1-3:slc(ACC1:acc#110.psp)#3 TYPE READSLICE PAR 0-4427 XREFS 29536 LOC {1 0.258664325 1 0.295178375 1 0.295178375 1 0.5234677999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4797 {}}} SUCCS {{259 0 0-4807 {}}} CYCLES {}}
+set a(0-4807) {NAME ACC1-3:not#154 TYPE NOT PAR 0-4427 XREFS 29537 LOC {1 0.258664325 1 0.335961425 1 0.335961425 1 0.5234677999999999} PREDS {{146 0 0-4451 {}} {259 0 0-4806 {}}} SUCCS {{259 0 0-4808 {}}} CYCLES {}}
+set a(0-4808) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1-3:acc#118 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-4427 XREFS 29538 LOC {1 0.29944737499999996 1 0.335961425 1 0.335961425 1 0.3564341850894752 1 0.5439405600894752} PREDS {{146 0 0-4451 {}} {258 0 0-4805 {}} {259 0 0-4807 {}}} SUCCS {{259 0 0-4809 {}} {258 0 0-4812 {}} {258 0 0-5503 {}}} CYCLES {}}
+set a(0-4809) {NAME ACC1-3:slc(ACC1:acc#118.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29539 LOC {1 0.319920175 1 0.356434225 1 0.356434225 1 0.5439406} PREDS {{146 0 0-4451 {}} {259 0 0-4808 {}}} SUCCS {{259 0 0-4810 {}}} CYCLES {}}
+set a(0-4810) {NAME ACC1-3:not#147 TYPE NOT PAR 0-4427 XREFS 29540 LOC {1 0.319920175 1 0.356434225 1 0.356434225 1 0.5439406} PREDS {{146 0 0-4451 {}} {259 0 0-4809 {}}} SUCCS {{259 0 0-4811 {}}} CYCLES {}}
+set a(0-4811) {NAME ACC1:conc#527 TYPE CONCATENATE PAR 0-4427 XREFS 29541 LOC {1 0.319920175 1 0.356434225 1 0.356434225 1 0.5439406} PREDS {{146 0 0-4451 {}} {259 0 0-4810 {}}} SUCCS {{258 0 0-4814 {}}} CYCLES {}}
+set a(0-4812) {NAME ACC1-3:slc(ACC1:acc#118.psp) TYPE READSLICE PAR 0-4427 XREFS 29542 LOC {1 0.319920175 1 0.356434225 1 0.356434225 1 0.5439406} PREDS {{146 0 0-4451 {}} {258 0 0-4808 {}}} SUCCS {{259 0 0-4813 {}}} CYCLES {}}
+set a(0-4813) {NAME ACC1:conc#528 TYPE CONCATENATE PAR 0-4427 XREFS 29543 LOC {1 0.319920175 1 0.356434225 1 0.356434225 1 0.5439406} PREDS {{146 0 0-4451 {}} {259 0 0-4812 {}}} SUCCS {{259 0 0-4814 {}}} CYCLES {}}
+set a(0-4814) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#178 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29544 LOC {1 0.319920175 1 0.356434225 1 0.356434225 1 0.38368010207082714 1 0.5711864770708271} PREDS {{146 0 0-4451 {}} {258 0 0-4811 {}} {259 0 0-4813 {}}} SUCCS {{259 0 0-4815 {}}} CYCLES {}}
+set a(0-4815) {NAME ACC1:slc#44 TYPE READSLICE PAR 0-4427 XREFS 29545 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-4451 {}} {259 0 0-4814 {}}} SUCCS {{259 0 0-4816 {}} {258 0 0-4818 {}} {258 0 0-4820 {}} {258 0 0-5494 {}}} CYCLES {}}
+set a(0-4816) {NAME ACC1-3:slc(acc.imod#6) TYPE READSLICE PAR 0-4427 XREFS 29546 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-4451 {}} {259 0 0-4815 {}}} SUCCS {{259 0 0-4817 {}}} CYCLES {}}
+set a(0-4817) {NAME ACC1:conc#530 TYPE CONCATENATE PAR 0-4427 XREFS 29547 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-4451 {}} {259 0 0-4816 {}}} SUCCS {{258 0 0-4823 {}}} CYCLES {}}
+set a(0-4818) {NAME ACC1-3:slc(acc.imod#6)#1 TYPE READSLICE PAR 0-4427 XREFS 29548 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-4451 {}} {258 0 0-4815 {}}} SUCCS {{259 0 0-4819 {}}} CYCLES {}}
+set a(0-4819) {NAME ACC1-3:not#57 TYPE NOT PAR 0-4427 XREFS 29549 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-4451 {}} {259 0 0-4818 {}}} SUCCS {{258 0 0-4822 {}}} CYCLES {}}
+set a(0-4820) {NAME ACC1-3:slc(acc.imod#6)#2 TYPE READSLICE PAR 0-4427 XREFS 29550 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-4451 {}} {258 0 0-4815 {}}} SUCCS {{259 0 0-4821 {}}} CYCLES {}}
+set a(0-4821) {NAME ACC1-3:not#58 TYPE NOT PAR 0-4427 XREFS 29551 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-4451 {}} {259 0 0-4820 {}}} SUCCS {{259 0 0-4822 {}}} CYCLES {}}
+set a(0-4822) {NAME ACC1:conc#531 TYPE CONCATENATE PAR 0-4427 XREFS 29552 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.571186525} PREDS {{146 0 0-4451 {}} {258 0 0-4819 {}} {259 0 0-4821 {}}} SUCCS {{259 0 0-4823 {}}} CYCLES {}}
+set a(0-4823) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#179 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29553 LOC {1 0.3471661 1 0.38368015 1 0.38368015 1 0.41092602707082715 1 0.5984324020708272} PREDS {{146 0 0-4451 {}} {258 0 0-4817 {}} {259 0 0-4822 {}}} SUCCS {{259 0 0-4824 {}}} CYCLES {}}
+set a(0-4824) {NAME ACC1:slc#45 TYPE READSLICE PAR 0-4427 XREFS 29554 LOC {1 0.374412025 1 0.410926075 1 0.410926075 1 0.59843245} PREDS {{146 0 0-4451 {}} {259 0 0-4823 {}}} SUCCS {{258 0 0-5495 {}}} CYCLES {}}
+set a(0-4825) {NAME regs.regs:asn#6 TYPE ASSIGN PAR 0-4427 XREFS 29555 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15038815} PREDS {{146 0 0-4451 {}} {262 0 0-5952 {}}} SUCCS {{259 0 0-4826 {}} {256 0 0-5952 {}}} CYCLES {}}
+set a(0-4826) {NAME regs.regs:slc(regs.regs(2))#7 TYPE READSLICE PAR 0-4427 XREFS 29556 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15038815} PREDS {{146 0 0-4451 {}} {259 0 0-4825 {}}} SUCCS {{258 0 0-4829 {}}} CYCLES {}}
+set a(0-4827) {NAME regs.regs:asn#7 TYPE ASSIGN PAR 0-4427 XREFS 29557 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15038815} PREDS {{146 0 0-4451 {}} {262 0 0-5952 {}}} SUCCS {{259 0 0-4828 {}} {256 0 0-5952 {}}} CYCLES {}}
+set a(0-4828) {NAME regs.regs:slc(regs.regs(2))#8 TYPE READSLICE PAR 0-4427 XREFS 29558 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.15038815} PREDS {{146 0 0-4451 {}} {259 0 0-4827 {}}} SUCCS {{259 0 0-4829 {}}} CYCLES {}}
+set a(0-4829) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,1,10,1,11) AREA_SCORE 11.00 QUANTITY 9 NAME ACC1:acc#180 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 29559 LOC {1 0.0 1 0.15038815 1 0.15038815 1 0.2215722533364113 1 0.2215722533364113} PREDS {{146 0 0-4451 {}} {258 0 0-4826 {}} {259 0 0-4828 {}}} SUCCS {{258 0 0-4832 {}}} CYCLES {}}
+set a(0-4830) {NAME regs.regs:asn#8 TYPE ASSIGN PAR 0-4427 XREFS 29560 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.2215723} PREDS {{146 0 0-4451 {}} {262 0 0-5952 {}}} SUCCS {{259 0 0-4831 {}} {256 0 0-5952 {}}} CYCLES {}}
+set a(0-4831) {NAME regs.regs:slc(regs.regs(2))#6 TYPE READSLICE PAR 0-4427 XREFS 29561 LOC {1 0.0 1 0.013988325 1 0.013988325 1 0.2215723} PREDS {{146 0 0-4451 {}} {259 0 0-4830 {}}} SUCCS {{259 0 0-4832 {}}} CYCLES {}}
+set a(0-4832) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME ACC1-3:acc#10 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-4427 XREFS 29562 LOC {1 0.07118415 1 0.2215723 1 0.2215723 1 0.2969430563734284 1 0.2969430563734284} PREDS {{146 0 0-4451 {}} {258 0 0-4829 {}} {259 0 0-4831 {}}} SUCCS {{259 0 0-4833 {}} {258 0 0-4836 {}} {258 0 0-4838 {}} {258 0 0-4843 {}} {258 0 0-4845 {}} {258 0 0-4849 {}} {258 0 0-4851 {}} {258 0 0-4853 {}} {258 0 0-4859 {}} {258 0 0-4861 {}} {258 0 0-4863 {}} {258 0 0-4867 {}} {258 0 0-5197 {}} {258 0 0-5198 {}} {258 0 0-5199 {}} {258 0 0-5201 {}} {258 0 0-5205 {}} {258 0 0-5211 {}} {258 0 0-5212 {}} {258 0 0-5216 {}} {258 0 0-5223 {}} {258 0 0-5224 {}} {258 0 0-5225 {}} {258 0 0-5228 {}} {258 0 0-5230 {}} {258 0 0-5235 {}} {258 0 0-5236 {}} {258 0 0-5237 {}} {258 0 0-5238 {}} {258 0 0-5241 {}} {258 0 0-5242 {}} {258 0 0-5246 {}} {258 0 0-5247 {}} {258 0 0-5248 {}} {258 0 0-5250 {}} {258 0 0-5252 {}} {258 0 0-5255 {}} {258 0 0-5258 {}} {258 0 0-5260 {}} {258 0 0-5272 {}} {258 0 0-5273 {}} {258 0 0-5274 {}} {258 0 0-5275 {}} {258 0 0-5276 {}} {258 0 0-5428 {}} {258 0 0-5429 {}} {258 0 0-5430 {}} {258 0 0-5431 {}} {258 0 0-5432 {}} {258 0 0-5434 {}} {258 0 0-5435 {}} {258 0 0-5436 {}} {258 0 0-5437 {}} {258 0 0-5440 {}} {258 0 0-5441 {}} {258 0 0-5442 {}} {258 0 0-5445 {}} {258 0 0-5448 {}} {258 0 0-5451 {}} {258 0 0-5457 {}} {258 0 0-5460 {}} {258 0 0-5468 {}} {258 0 0-5471 {}} {258 0 0-5477 {}} {258 0 0-5480 {}}} CYCLES {}}
+set a(0-4833) {NAME ACC1-3:slc(acc#10.psp)#11 TYPE READSLICE PAR 0-4427 XREFS 29563 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.321617575} PREDS {{146 0 0-4451 {}} {259 0 0-4832 {}}} SUCCS {{259 0 0-4834 {}}} CYCLES {}}
+set a(0-4834) {NAME ACC1-3:not#152 TYPE NOT PAR 0-4427 XREFS 29564 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.321617575} PREDS {{146 0 0-4451 {}} {259 0 0-4833 {}}} SUCCS {{259 0 0-4835 {}}} CYCLES {}}
+set a(0-4835) {NAME ACC1:conc#537 TYPE CONCATENATE PAR 0-4427 XREFS 29565 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.321617575} PREDS {{146 0 0-4451 {}} {259 0 0-4834 {}}} SUCCS {{258 0 0-4840 {}}} CYCLES {}}
+set a(0-4836) {NAME ACC1-3:slc(acc#10.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29566 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.321617575} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-4837 {}}} CYCLES {}}
+set a(0-4837) {NAME ACC1-3:not#124 TYPE NOT PAR 0-4427 XREFS 29567 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.321617575} PREDS {{146 0 0-4451 {}} {259 0 0-4836 {}}} SUCCS {{258 0 0-4839 {}}} CYCLES {}}
+set a(0-4838) {NAME ACC1-3:slc(acc#10.psp)#8 TYPE READSLICE PAR 0-4427 XREFS 29568 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.321617575} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-4839 {}}} CYCLES {}}
+set a(0-4839) {NAME ACC1:conc#538 TYPE CONCATENATE PAR 0-4427 XREFS 29569 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.321617575} PREDS {{146 0 0-4451 {}} {258 0 0-4837 {}} {259 0 0-4838 {}}} SUCCS {{259 0 0-4840 {}}} CYCLES {}}
+set a(0-4840) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1:acc#183 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-4427 XREFS 29570 LOC {1 0.14655495 1 0.321617575 1 0.321617575 1 0.34209033508947523 1 0.34209033508947523} PREDS {{146 0 0-4451 {}} {258 0 0-4835 {}} {259 0 0-4839 {}}} SUCCS {{259 0 0-4841 {}}} CYCLES {}}
+set a(0-4841) {NAME ACC1:slc#48 TYPE READSLICE PAR 0-4427 XREFS 29571 LOC {1 0.16702775 1 0.342090375 1 0.342090375 1 0.342090375} PREDS {{146 0 0-4451 {}} {259 0 0-4840 {}}} SUCCS {{259 0 0-4842 {}}} CYCLES {}}
+set a(0-4842) {NAME ACC1:conc#541 TYPE CONCATENATE PAR 0-4427 XREFS 29572 LOC {1 0.16702775 1 0.342090375 1 0.342090375 1 0.342090375} PREDS {{146 0 0-4451 {}} {259 0 0-4841 {}}} SUCCS {{258 0 0-4847 {}}} CYCLES {}}
+set a(0-4843) {NAME ACC1-3:slc(acc#10.psp) TYPE READSLICE PAR 0-4427 XREFS 29573 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.342090375} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-4844 {}}} CYCLES {}}
+set a(0-4844) {NAME ACC1:conc#532 TYPE CONCATENATE PAR 0-4427 XREFS 29574 LOC {1 0.14655495 1 0.342090375 1 0.342090375 1 0.342090375} PREDS {{146 0 0-4451 {}} {259 0 0-4843 {}}} SUCCS {{258 0 0-4846 {}}} CYCLES {}}
+set a(0-4845) {NAME ACC1-3:slc(acc#10.psp)#10 TYPE READSLICE PAR 0-4427 XREFS 29575 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.342090375} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-4846 {}}} CYCLES {}}
+set a(0-4846) {NAME ACC1:conc#542 TYPE CONCATENATE PAR 0-4427 XREFS 29576 LOC {1 0.14655495 1 0.342090375 1 0.342090375 1 0.342090375} PREDS {{146 0 0-4451 {}} {258 0 0-4844 {}} {259 0 0-4845 {}}} SUCCS {{259 0 0-4847 {}}} CYCLES {}}
+set a(0-4847) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#185 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 29577 LOC {1 0.16702775 1 0.342090375 1 0.342090375 1 0.3852822701789505 1 0.3852822701789505} PREDS {{146 0 0-4451 {}} {258 0 0-4842 {}} {259 0 0-4846 {}}} SUCCS {{259 0 0-4848 {}}} CYCLES {}}
+set a(0-4848) {NAME ACC1:slc#50 TYPE READSLICE PAR 0-4427 XREFS 29578 LOC {1 0.21021969999999998 1 0.385282325 1 0.385282325 1 0.385282325} PREDS {{146 0 0-4451 {}} {259 0 0-4847 {}}} SUCCS {{258 0 0-4872 {}}} CYCLES {}}
+set a(0-4849) {NAME ACC1-3:slc(acc#10.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 29579 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-4850 {}}} CYCLES {}}
+set a(0-4850) {NAME ACC1:conc#535 TYPE CONCATENATE PAR 0-4427 XREFS 29580 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4849 {}}} SUCCS {{258 0 0-4856 {}}} CYCLES {}}
+set a(0-4851) {NAME ACC1-3:slc(acc#10.psp)#3 TYPE READSLICE PAR 0-4427 XREFS 29581 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-4852 {}}} CYCLES {}}
+set a(0-4852) {NAME ACC1-3:not#125 TYPE NOT PAR 0-4427 XREFS 29582 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4851 {}}} SUCCS {{258 0 0-4855 {}}} CYCLES {}}
+set a(0-4853) {NAME ACC1-3:slc(acc#10.psp)#7 TYPE READSLICE PAR 0-4427 XREFS 29583 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-4854 {}}} CYCLES {}}
+set a(0-4854) {NAME ACC1-3:not#127 TYPE NOT PAR 0-4427 XREFS 29584 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4853 {}}} SUCCS {{259 0 0-4855 {}}} CYCLES {}}
+set a(0-4855) {NAME ACC1:conc#536 TYPE CONCATENATE PAR 0-4427 XREFS 29585 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4852 {}} {259 0 0-4854 {}}} SUCCS {{259 0 0-4856 {}}} CYCLES {}}
+set a(0-4856) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#182 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29586 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.3377261100894752 1 0.3377261100894752} PREDS {{146 0 0-4451 {}} {258 0 0-4850 {}} {259 0 0-4855 {}}} SUCCS {{259 0 0-4857 {}}} CYCLES {}}
+set a(0-4857) {NAME ACC1:slc#47 TYPE READSLICE PAR 0-4427 XREFS 29587 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.33772615} PREDS {{146 0 0-4451 {}} {259 0 0-4856 {}}} SUCCS {{259 0 0-4858 {}}} CYCLES {}}
+set a(0-4858) {NAME ACC1:conc#539 TYPE CONCATENATE PAR 0-4427 XREFS 29588 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.33772615} PREDS {{146 0 0-4451 {}} {259 0 0-4857 {}}} SUCCS {{258 0 0-4870 {}}} CYCLES {}}
+set a(0-4859) {NAME ACC1-3:slc(acc#10.psp)#4 TYPE READSLICE PAR 0-4427 XREFS 29589 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-4860 {}}} CYCLES {}}
+set a(0-4860) {NAME ACC1:conc#533 TYPE CONCATENATE PAR 0-4427 XREFS 29590 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4859 {}}} SUCCS {{258 0 0-4865 {}}} CYCLES {}}
+set a(0-4861) {NAME ACC1-3:slc(acc#10.psp)#5 TYPE READSLICE PAR 0-4427 XREFS 29591 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-4862 {}}} CYCLES {}}
+set a(0-4862) {NAME ACC1-3:not#126 TYPE NOT PAR 0-4427 XREFS 29592 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4861 {}}} SUCCS {{258 0 0-4864 {}}} CYCLES {}}
+set a(0-4863) {NAME ACC1-3:slc(acc#10.psp)#6 TYPE READSLICE PAR 0-4427 XREFS 29593 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-4864 {}}} CYCLES {}}
+set a(0-4864) {NAME ACC1:conc#534 TYPE CONCATENATE PAR 0-4427 XREFS 29594 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.29694309999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4862 {}} {259 0 0-4863 {}}} SUCCS {{259 0 0-4865 {}}} CYCLES {}}
+set a(0-4865) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#181 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29595 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.3377261100894752 1 0.3377261100894752} PREDS {{146 0 0-4451 {}} {258 0 0-4860 {}} {259 0 0-4864 {}}} SUCCS {{259 0 0-4866 {}}} CYCLES {}}
+set a(0-4866) {NAME ACC1:slc#46 TYPE READSLICE PAR 0-4427 XREFS 29596 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.33772615} PREDS {{146 0 0-4451 {}} {259 0 0-4865 {}}} SUCCS {{258 0 0-4869 {}}} CYCLES {}}
+set a(0-4867) {NAME ACC1-3:slc(acc#10.psp)#9 TYPE READSLICE PAR 0-4427 XREFS 29597 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.33772615} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-4868 {}}} CYCLES {}}
+set a(0-4868) {NAME ACC1-3:not#128 TYPE NOT PAR 0-4427 XREFS 29598 LOC {1 0.14655495 1 0.33772615 1 0.33772615 1 0.33772615} PREDS {{146 0 0-4451 {}} {259 0 0-4867 {}}} SUCCS {{259 0 0-4869 {}}} CYCLES {}}
+set a(0-4869) {NAME ACC1:conc#540 TYPE CONCATENATE PAR 0-4427 XREFS 29599 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.33772615} PREDS {{146 0 0-4451 {}} {258 0 0-4866 {}} {259 0 0-4868 {}}} SUCCS {{259 0 0-4870 {}}} CYCLES {}}
+set a(0-4870) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#184 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29600 LOC {1 0.187338 1 0.33772615 1 0.33772615 1 0.3852822770708272 1 0.3852822770708272} PREDS {{146 0 0-4451 {}} {258 0 0-4858 {}} {259 0 0-4869 {}}} SUCCS {{259 0 0-4871 {}}} CYCLES {}}
+set a(0-4871) {NAME ACC1:slc#49 TYPE READSLICE PAR 0-4427 XREFS 29601 LOC {1 0.23489417499999998 1 0.385282325 1 0.385282325 1 0.385282325} PREDS {{146 0 0-4451 {}} {259 0 0-4870 {}}} SUCCS {{259 0 0-4872 {}}} CYCLES {}}
+set a(0-4872) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1-3:acc#113 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-4427 XREFS 29602 LOC {1 0.23489417499999998 1 0.385282325 1 0.385282325 1 0.4183190951789505 1 0.4183190951789505} PREDS {{146 0 0-4451 {}} {258 0 0-4848 {}} {259 0 0-4871 {}}} SUCCS {{259 0 0-4873 {}} {258 0 0-4875 {}} {258 0 0-4877 {}} {258 0 0-4881 {}} {258 0 0-5204 {}} {258 0 0-5215 {}} {258 0 0-5218 {}} {258 0 0-5482 {}}} CYCLES {}}
+set a(0-4873) {NAME ACC1-3:slc(ACC1:acc#113.psp) TYPE READSLICE PAR 0-4427 XREFS 29603 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.41831915} PREDS {{146 0 0-4451 {}} {259 0 0-4872 {}}} SUCCS {{259 0 0-4874 {}}} CYCLES {}}
+set a(0-4874) {NAME ACC1:conc#543 TYPE CONCATENATE PAR 0-4427 XREFS 29604 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.41831915} PREDS {{146 0 0-4451 {}} {259 0 0-4873 {}}} SUCCS {{258 0 0-4879 {}}} CYCLES {}}
+set a(0-4875) {NAME ACC1-3:slc(ACC1:acc#113.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29605 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.41831915} PREDS {{146 0 0-4451 {}} {258 0 0-4872 {}}} SUCCS {{259 0 0-4876 {}}} CYCLES {}}
+set a(0-4876) {NAME ACC1-3:not#141 TYPE NOT PAR 0-4427 XREFS 29606 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.41831915} PREDS {{146 0 0-4451 {}} {259 0 0-4875 {}}} SUCCS {{258 0 0-4878 {}}} CYCLES {}}
+set a(0-4877) {NAME ACC1-3:slc(ACC1:acc#113.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 29607 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.41831915} PREDS {{146 0 0-4451 {}} {258 0 0-4872 {}}} SUCCS {{259 0 0-4878 {}}} CYCLES {}}
+set a(0-4878) {NAME ACC1:conc#544 TYPE CONCATENATE PAR 0-4427 XREFS 29608 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.41831915} PREDS {{146 0 0-4451 {}} {258 0 0-4876 {}} {259 0 0-4877 {}}} SUCCS {{259 0 0-4879 {}}} CYCLES {}}
+set a(0-4879) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#186 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29609 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.45910216008947524 1 0.45910216008947524} PREDS {{146 0 0-4451 {}} {258 0 0-4874 {}} {259 0 0-4878 {}}} SUCCS {{259 0 0-4880 {}}} CYCLES {}}
+set a(0-4880) {NAME ACC1:slc#51 TYPE READSLICE PAR 0-4427 XREFS 29610 LOC {1 0.30871404999999996 1 0.45910219999999996 1 0.45910219999999996 1 0.45910219999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4879 {}}} SUCCS {{258 0 0-4883 {}}} CYCLES {}}
+set a(0-4881) {NAME ACC1-3:slc(ACC1:acc#113.psp)#3 TYPE READSLICE PAR 0-4427 XREFS 29611 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.45910219999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4872 {}}} SUCCS {{259 0 0-4882 {}}} CYCLES {}}
+set a(0-4882) {NAME ACC1-3:not#155 TYPE NOT PAR 0-4427 XREFS 29612 LOC {1 0.267931 1 0.45910219999999996 1 0.45910219999999996 1 0.45910219999999996} PREDS {{146 0 0-4451 {}} {259 0 0-4881 {}}} SUCCS {{259 0 0-4883 {}}} CYCLES {}}
+set a(0-4883) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME ACC1-3:acc#120 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-4427 XREFS 29613 LOC {1 0.30871404999999996 1 0.45910219999999996 1 0.45910219999999996 1 0.4795749600894752 1 0.4795749600894752} PREDS {{146 0 0-4451 {}} {258 0 0-4880 {}} {259 0 0-4882 {}}} SUCCS {{259 0 0-4884 {}} {258 0 0-4887 {}} {258 0 0-5209 {}}} CYCLES {}}
+set a(0-4884) {NAME ACC1-3:slc(ACC1:acc#120.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 29614 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.479575} PREDS {{146 0 0-4451 {}} {259 0 0-4883 {}}} SUCCS {{259 0 0-4885 {}}} CYCLES {}}
+set a(0-4885) {NAME ACC1-3:not#149 TYPE NOT PAR 0-4427 XREFS 29615 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.479575} PREDS {{146 0 0-4451 {}} {259 0 0-4884 {}}} SUCCS {{259 0 0-4886 {}}} CYCLES {}}
+set a(0-4886) {NAME ACC1:conc#545 TYPE CONCATENATE PAR 0-4427 XREFS 29616 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.479575} PREDS {{146 0 0-4451 {}} {259 0 0-4885 {}}} SUCCS {{258 0 0-4889 {}}} CYCLES {}}
+set a(0-4887) {NAME ACC1-3:slc(ACC1:acc#120.psp) TYPE READSLICE PAR 0-4427 XREFS 29617 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.479575} PREDS {{146 0 0-4451 {}} {258 0 0-4883 {}}} SUCCS {{259 0 0-4888 {}}} CYCLES {}}
+set a(0-4888) {NAME ACC1:conc#546 TYPE CONCATENATE PAR 0-4427 XREFS 29618 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.479575} PREDS {{146 0 0-4451 {}} {259 0 0-4887 {}}} SUCCS {{259 0 0-4889 {}}} CYCLES {}}
+set a(0-4889) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#187 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29619 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.5068208770708271 1 0.5068208770708271} PREDS {{146 0 0-4451 {}} {258 0 0-4886 {}} {259 0 0-4888 {}}} SUCCS {{259 0 0-4890 {}}} CYCLES {}}
+set a(0-4890) {NAME ACC1:slc#52 TYPE READSLICE PAR 0-4427 XREFS 29620 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-4451 {}} {259 0 0-4889 {}}} SUCCS {{259 0 0-4891 {}} {258 0 0-4893 {}} {258 0 0-4895 {}} {258 0 0-5462 {}} {258 0 0-5473 {}}} CYCLES {}}
+set a(0-4891) {NAME ACC1-3:slc(acc.imod#10) TYPE READSLICE PAR 0-4427 XREFS 29621 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-4451 {}} {259 0 0-4890 {}}} SUCCS {{259 0 0-4892 {}}} CYCLES {}}
+set a(0-4892) {NAME ACC1:conc#548 TYPE CONCATENATE PAR 0-4427 XREFS 29622 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-4451 {}} {259 0 0-4891 {}}} SUCCS {{258 0 0-4898 {}}} CYCLES {}}
+set a(0-4893) {NAME ACC1-3:slc(acc.imod#10)#1 TYPE READSLICE PAR 0-4427 XREFS 29623 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-4451 {}} {258 0 0-4890 {}}} SUCCS {{259 0 0-4894 {}}} CYCLES {}}
+set a(0-4894) {NAME ACC1-3:not#89 TYPE NOT PAR 0-4427 XREFS 29624 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-4451 {}} {259 0 0-4893 {}}} SUCCS {{258 0 0-4897 {}}} CYCLES {}}
+set a(0-4895) {NAME ACC1-3:slc(acc.imod#10)#2 TYPE READSLICE PAR 0-4427 XREFS 29625 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-4451 {}} {258 0 0-4890 {}}} SUCCS {{259 0 0-4896 {}}} CYCLES {}}
+set a(0-4896) {NAME ACC1-3:not#90 TYPE NOT PAR 0-4427 XREFS 29626 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-4451 {}} {259 0 0-4895 {}}} SUCCS {{259 0 0-4897 {}}} CYCLES {}}
+set a(0-4897) {NAME ACC1:conc#549 TYPE CONCATENATE PAR 0-4427 XREFS 29627 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.506820925} PREDS {{146 0 0-4451 {}} {258 0 0-4894 {}} {259 0 0-4896 {}}} SUCCS {{259 0 0-4898 {}}} CYCLES {}}
+set a(0-4898) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#188 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29628 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.5340668020708271 1 0.5340668020708271} PREDS {{146 0 0-4451 {}} {258 0 0-4892 {}} {259 0 0-4897 {}}} SUCCS {{259 0 0-4899 {}}} CYCLES {}}
+set a(0-4899) {NAME ACC1:slc#53 TYPE READSLICE PAR 0-4427 XREFS 29629 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-4898 {}}} SUCCS {{258 0 0-5261 {}} {258 0 0-5263 {}} {258 0 0-5450 {}}} CYCLES {}}
+set a(0-4900) {NAME ACC1-3:slc(acc.psp)#61 TYPE READSLICE PAR 0-4427 XREFS 29630 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 2 0.015519449999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4903 {}}} CYCLES {}}
+set a(0-4901) {NAME ACC1-3:slc(acc.psp)#62 TYPE READSLICE PAR 0-4427 XREFS 29631 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 2 0.015519449999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4903 {}}} CYCLES {}}
+set a(0-4902) {NAME ACC1-3:slc(acc.psp)#49 TYPE READSLICE PAR 0-4427 XREFS 29632 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 2 0.015519449999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4903 {}}} CYCLES {}}
+set a(0-4903) {NAME ACC1-3:conc#257 TYPE CONCATENATE PAR 0-4427 XREFS 29633 LOC {1 0.14655495 1 0.8410234999999999 1 0.8410234999999999 2 0.015519449999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4901 {}} {258 0 0-4900 {}} {259 0 0-4902 {}}} SUCCS {{258 0 0-4983 {}}} CYCLES {}}
+set a(0-4904) {NAME ACC1-3:slc(acc.psp)#29 TYPE READSLICE PAR 0-4427 XREFS 29634 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6718295249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4905 {}}} CYCLES {}}
+set a(0-4905) {NAME ACC1:conc#550 TYPE CONCATENATE PAR 0-4427 XREFS 29635 LOC {1 0.14655495 1 0.512853025 1 0.512853025 1 0.6718295249999999} PREDS {{146 0 0-4451 {}} {259 0 0-4904 {}}} SUCCS {{259 0 0-4906 {}}} CYCLES {}}
+set a(0-4906) {NAME ACC1:conc#551 TYPE CONCATENATE PAR 0-4427 XREFS 29636 LOC {1 0.14655495 1 0.512853025 1 0.512853025 1 0.6718295249999999} PREDS {{146 0 0-4451 {}} {259 0 0-4905 {}}} SUCCS {{258 0 0-4910 {}}} CYCLES {}}
+set a(0-4907) {NAME ACC1-3:slc(ACC1:acc#107.psp)#10 TYPE READSLICE PAR 0-4427 XREFS 29637 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.6718295249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4725 {}}} SUCCS {{258 0 0-4909 {}}} CYCLES {}}
+set a(0-4908) {NAME ACC1-3:slc(acc.psp)#30 TYPE READSLICE PAR 0-4427 XREFS 29638 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6718295249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4909 {}}} CYCLES {}}
+set a(0-4909) {NAME ACC1:conc#552 TYPE CONCATENATE PAR 0-4427 XREFS 29639 LOC {1 0.267931 1 0.512853025 1 0.512853025 1 0.6718295249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4907 {}} {259 0 0-4908 {}}} SUCCS {{259 0 0-4910 {}}} CYCLES {}}
+set a(0-4910) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#189 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-4427 XREFS 29640 LOC {1 0.267931 1 0.512853025 1 0.512853025 1 0.5504736020241716 1 0.7094501020241716} PREDS {{146 0 0-4451 {}} {258 0 0-4906 {}} {259 0 0-4909 {}}} SUCCS {{259 0 0-4911 {}}} CYCLES {}}
+set a(0-4911) {NAME ACC1:slc#54 TYPE READSLICE PAR 0-4427 XREFS 29641 LOC {1 0.305551625 1 0.5504736499999999 1 0.5504736499999999 1 0.70945015} PREDS {{146 0 0-4451 {}} {259 0 0-4910 {}}} SUCCS {{258 0 0-4913 {}}} CYCLES {}}
+set a(0-4912) {NAME ACC1-3:slc(ACC1:acc#116.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 29642 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.70945015} PREDS {{146 0 0-4451 {}} {258 0 0-4736 {}}} SUCCS {{259 0 0-4913 {}}} CYCLES {}}
+set a(0-4913) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#198 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-4427 XREFS 29643 LOC {1 0.32918685 1 0.5504736499999999 1 0.5504736499999999 1 0.5880942270241716 1 0.7470707270241717} PREDS {{146 0 0-4451 {}} {258 0 0-4911 {}} {259 0 0-4912 {}}} SUCCS {{258 0 0-4925 {}}} CYCLES {}}
+set a(0-4914) {NAME ACC1-3:slc(acc.psp)#31 TYPE READSLICE PAR 0-4427 XREFS 29644 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.71982485} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4916 {}}} CYCLES {}}
+set a(0-4915) {NAME ACC1-3:slc(acc.psp)#32 TYPE READSLICE PAR 0-4427 XREFS 29645 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.71982485} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4916 {}}} CYCLES {}}
+set a(0-4916) {NAME ACC1-3:conc#258 TYPE CONCATENATE PAR 0-4427 XREFS 29646 LOC {1 0.14655495 1 0.56084835 1 0.56084835 1 0.71982485} PREDS {{146 0 0-4451 {}} {258 0 0-4914 {}} {259 0 0-4915 {}}} SUCCS {{259 0 0-4917 {}}} CYCLES {}}
+set a(0-4917) {NAME ACC1:conc#553 TYPE CONCATENATE PAR 0-4427 XREFS 29647 LOC {1 0.14655495 1 0.56084835 1 0.56084835 1 0.71982485} PREDS {{146 0 0-4451 {}} {259 0 0-4916 {}}} SUCCS {{258 0 0-4923 {}}} CYCLES {}}
+set a(0-4918) {NAME ACC1-3:slc(ACC1:acc#107.psp)#11 TYPE READSLICE PAR 0-4427 XREFS 29648 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.71982485} PREDS {{146 0 0-4451 {}} {258 0 0-4725 {}}} SUCCS {{258 0 0-4920 {}}} CYCLES {}}
+set a(0-4919) {NAME ACC1-3:slc(acc.psp)#33 TYPE READSLICE PAR 0-4427 XREFS 29649 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.71982485} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4920 {}}} CYCLES {}}
+set a(0-4920) {NAME ACC1-3:conc#259 TYPE CONCATENATE PAR 0-4427 XREFS 29650 LOC {1 0.267931 1 0.56084835 1 0.56084835 1 0.71982485} PREDS {{146 0 0-4451 {}} {258 0 0-4918 {}} {259 0 0-4919 {}}} SUCCS {{258 0 0-4922 {}}} CYCLES {}}
+set a(0-4921) {NAME ACC1-3:slc(ACC1:acc#107.psp)#8 TYPE READSLICE PAR 0-4427 XREFS 29651 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.71982485} PREDS {{146 0 0-4451 {}} {258 0 0-4725 {}}} SUCCS {{259 0 0-4922 {}}} CYCLES {}}
+set a(0-4922) {NAME ACC1:conc#554 TYPE CONCATENATE PAR 0-4427 XREFS 29652 LOC {1 0.267931 1 0.56084835 1 0.56084835 1 0.71982485} PREDS {{146 0 0-4451 {}} {258 0 0-4920 {}} {259 0 0-4921 {}}} SUCCS {{259 0 0-4923 {}}} CYCLES {}}
+set a(0-4923) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#190 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29653 LOC {1 0.267931 1 0.56084835 1 0.56084835 1 0.5880942270708271 1 0.7470707270708271} PREDS {{146 0 0-4451 {}} {258 0 0-4917 {}} {259 0 0-4922 {}}} SUCCS {{259 0 0-4924 {}}} CYCLES {}}
+set a(0-4924) {NAME ACC1:slc#55 TYPE READSLICE PAR 0-4427 XREFS 29654 LOC {1 0.295176925 1 0.588094275 1 0.588094275 1 0.747070775} PREDS {{146 0 0-4451 {}} {259 0 0-4923 {}}} SUCCS {{259 0 0-4925 {}}} CYCLES {}}
+set a(0-4925) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#203 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 29655 LOC {1 0.366807475 1 0.588094275 1 0.588094275 1 0.6312861701789505 1 0.7902626701789505} PREDS {{146 0 0-4451 {}} {258 0 0-4913 {}} {259 0 0-4924 {}}} SUCCS {{258 0 0-4937 {}}} CYCLES {}}
+set a(0-4926) {NAME ACC1-3:slc(acc.psp)#34 TYPE READSLICE PAR 0-4427 XREFS 29656 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7572259} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4930 {}}} CYCLES {}}
+set a(0-4927) {NAME ACC1-3:slc(acc.psp)#35 TYPE READSLICE PAR 0-4427 XREFS 29657 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7572259} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4930 {}}} CYCLES {}}
+set a(0-4928) {NAME ACC1-3:slc(acc.idiv)#31 TYPE READSLICE PAR 0-4427 XREFS 29658 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7572259} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4929 {}}} CYCLES {}}
+set a(0-4929) {NAME ACC1-3:exs#15 TYPE SIGNEXTEND PAR 0-4427 XREFS 29659 LOC {1 0.14655495 1 0.5982493999999999 1 0.5982493999999999 1 0.7572259} PREDS {{146 0 0-4451 {}} {259 0 0-4928 {}}} SUCCS {{259 0 0-4930 {}}} CYCLES {}}
+set a(0-4930) {NAME ACC1-3:conc#260 TYPE CONCATENATE PAR 0-4427 XREFS 29660 LOC {1 0.14655495 1 0.5982493999999999 1 0.5982493999999999 1 0.7572259} PREDS {{146 0 0-4451 {}} {258 0 0-4927 {}} {258 0 0-4926 {}} {259 0 0-4929 {}}} SUCCS {{258 0 0-4936 {}}} CYCLES {}}
+set a(0-4931) {NAME ACC1-3:slc(acc.idiv)#33 TYPE READSLICE PAR 0-4427 XREFS 29661 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.71644285} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4932 {}}} CYCLES {}}
+set a(0-4932) {NAME ACC1-3:exs#16 TYPE SIGNEXTEND PAR 0-4427 XREFS 29662 LOC {1 0.14655495 1 0.55746635 1 0.55746635 1 0.71644285} PREDS {{146 0 0-4451 {}} {259 0 0-4931 {}}} SUCCS {{258 0 0-4935 {}}} CYCLES {}}
+set a(0-4933) {NAME ACC1-3:slc(acc.idiv)#35 TYPE READSLICE PAR 0-4427 XREFS 29663 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.71644285} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4934 {}}} CYCLES {}}
+set a(0-4934) {NAME ACC1-3:exs#17 TYPE SIGNEXTEND PAR 0-4427 XREFS 29664 LOC {1 0.14655495 1 0.55746635 1 0.55746635 1 0.71644285} PREDS {{146 0 0-4451 {}} {259 0 0-4933 {}}} SUCCS {{259 0 0-4935 {}}} CYCLES {}}
+set a(0-4935) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#197 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29665 LOC {1 0.14655495 1 0.55746635 1 0.55746635 1 0.5982493600894753 1 0.7572258600894752} PREDS {{146 0 0-4451 {}} {258 0 0-4932 {}} {259 0 0-4934 {}}} SUCCS {{259 0 0-4936 {}}} CYCLES {}}
+set a(0-4936) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#202 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-4427 XREFS 29666 LOC {1 0.187338 1 0.5982493999999999 1 0.5982493999999999 1 0.6312861701789504 1 0.7902626701789505} PREDS {{146 0 0-4451 {}} {258 0 0-4930 {}} {259 0 0-4935 {}}} SUCCS {{259 0 0-4937 {}}} CYCLES {}}
+set a(0-4937) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#206 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 29667 LOC {1 0.409999425 1 0.631286225 1 0.631286225 1 0.669575684496936 1 0.828552184496936} PREDS {{146 0 0-4451 {}} {258 0 0-4925 {}} {259 0 0-4936 {}}} SUCCS {{258 0 0-4943 {}}} CYCLES {}}
+set a(0-4938) {NAME ACC1-3:slc(acc.psp)#54 TYPE READSLICE PAR 0-4427 XREFS 29668 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8285522249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4942 {}}} CYCLES {}}
+set a(0-4939) {NAME ACC1-3:slc(acc.psp)#55 TYPE READSLICE PAR 0-4427 XREFS 29669 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8285522249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4942 {}}} CYCLES {}}
+set a(0-4940) {NAME ACC1-3:slc(acc.psp)#56 TYPE READSLICE PAR 0-4427 XREFS 29670 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8285522249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4942 {}}} CYCLES {}}
+set a(0-4941) {NAME ACC1-3:slc(acc.psp)#47 TYPE READSLICE PAR 0-4427 XREFS 29671 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8285522249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4942 {}}} CYCLES {}}
+set a(0-4942) {NAME ACC1-3:conc#255 TYPE CONCATENATE PAR 0-4427 XREFS 29672 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.8285522249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4940 {}} {258 0 0-4939 {}} {258 0 0-4938 {}} {259 0 0-4941 {}}} SUCCS {{259 0 0-4943 {}}} CYCLES {}}
+set a(0-4943) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#209 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-4427 XREFS 29673 LOC {1 0.448288925 1 0.669575725 1 0.669575725 1 0.7174547879329679 1 0.8764312879329679} PREDS {{146 0 0-4451 {}} {258 0 0-4937 {}} {259 0 0-4942 {}}} SUCCS {{258 0 0-4974 {}}} CYCLES {}}
+set a(0-4944) {NAME ACC1-3:slc(acc.psp)#17 TYPE READSLICE PAR 0-4427 XREFS 29674 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8285522249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4947 {}}} CYCLES {}}
+set a(0-4945) {NAME ACC1-3:slc(acc.idiv)#25 TYPE READSLICE PAR 0-4427 XREFS 29675 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8285522249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4946 {}}} CYCLES {}}
+set a(0-4946) {NAME ACC1-3:exs#12 TYPE SIGNEXTEND PAR 0-4427 XREFS 29676 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.8285522249999999} PREDS {{146 0 0-4451 {}} {259 0 0-4945 {}}} SUCCS {{259 0 0-4947 {}}} CYCLES {}}
+set a(0-4947) {NAME ACC1-3:conc#226 TYPE CONCATENATE PAR 0-4427 XREFS 29677 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.8285522249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4944 {}} {259 0 0-4946 {}}} SUCCS {{259 0 0-4948 {}}} CYCLES {}}
+set a(0-4948) {NAME ACC1-3:exs#538 TYPE SIGNEXTEND PAR 0-4427 XREFS 29678 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.8285522249999999} PREDS {{146 0 0-4451 {}} {259 0 0-4947 {}}} SUCCS {{258 0 0-4973 {}}} CYCLES {}}
+set a(0-4949) {NAME ACC1-3:slc(acc.psp)#52 TYPE READSLICE PAR 0-4427 XREFS 29679 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7902627249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4952 {}}} CYCLES {}}
+set a(0-4950) {NAME ACC1-3:slc(acc.psp)#53 TYPE READSLICE PAR 0-4427 XREFS 29680 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7902627249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4952 {}}} CYCLES {}}
+set a(0-4951) {NAME ACC1-3:slc(acc.psp)#46 TYPE READSLICE PAR 0-4427 XREFS 29681 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7902627249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4952 {}}} CYCLES {}}
+set a(0-4952) {NAME ACC1-3:conc TYPE CONCATENATE PAR 0-4427 XREFS 29682 LOC {1 0.14655495 1 0.631286225 1 0.631286225 1 0.7902627249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4950 {}} {258 0 0-4949 {}} {259 0 0-4951 {}}} SUCCS {{258 0 0-4972 {}}} CYCLES {}}
+set a(0-4953) {NAME ACC1-3:slc(acc.idiv)#9 TYPE READSLICE PAR 0-4427 XREFS 29683 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7019234999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4954 {}}} CYCLES {}}
+set a(0-4954) {NAME ACC1-3:exs#4 TYPE SIGNEXTEND PAR 0-4427 XREFS 29684 LOC {1 0.14655495 1 0.542947 1 0.542947 1 0.7019234999999999} PREDS {{146 0 0-4451 {}} {259 0 0-4953 {}}} SUCCS {{258 0 0-4957 {}}} CYCLES {}}
+set a(0-4955) {NAME ACC1-3:slc(acc.idiv)#11 TYPE READSLICE PAR 0-4427 XREFS 29685 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7019234999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4956 {}}} CYCLES {}}
+set a(0-4956) {NAME ACC1-3:exs#5 TYPE SIGNEXTEND PAR 0-4427 XREFS 29686 LOC {1 0.14655495 1 0.542947 1 0.542947 1 0.7019234999999999} PREDS {{146 0 0-4451 {}} {259 0 0-4955 {}}} SUCCS {{259 0 0-4957 {}}} CYCLES {}}
+set a(0-4957) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#196 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29687 LOC {1 0.14655495 1 0.542947 1 0.542947 1 0.5837300100894752 1 0.7427065100894752} PREDS {{146 0 0-4451 {}} {258 0 0-4954 {}} {259 0 0-4956 {}}} SUCCS {{258 0 0-4971 {}}} CYCLES {}}
+set a(0-4958) {NAME ACC1-3:slc(acc.idiv)#1 TYPE READSLICE PAR 0-4427 XREFS 29688 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.695150375} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4959 {}}} CYCLES {}}
+set a(0-4959) {NAME ACC1-3:exs#496 TYPE SIGNEXTEND PAR 0-4427 XREFS 29689 LOC {1 0.14655495 1 0.536173875 1 0.536173875 1 0.695150375} PREDS {{146 0 0-4451 {}} {259 0 0-4958 {}}} SUCCS {{259 0 0-4960 {}}} CYCLES {}}
+set a(0-4960) {NAME ACC1:conc#563 TYPE CONCATENATE PAR 0-4427 XREFS 29690 LOC {1 0.14655495 1 0.536173875 1 0.536173875 1 0.695150375} PREDS {{146 0 0-4451 {}} {259 0 0-4959 {}}} SUCCS {{258 0 0-4969 {}}} CYCLES {}}
+set a(0-4961) {NAME ACC1-3:slc(acc.idiv)#3 TYPE READSLICE PAR 0-4427 XREFS 29691 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.695150375} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4962 {}}} CYCLES {}}
+set a(0-4962) {NAME ACC1-3:exs#1 TYPE SIGNEXTEND PAR 0-4427 XREFS 29692 LOC {1 0.14655495 1 0.536173875 1 0.536173875 1 0.695150375} PREDS {{146 0 0-4451 {}} {259 0 0-4961 {}}} SUCCS {{258 0 0-4968 {}}} CYCLES {}}
+set a(0-4963) {NAME ACC1-3:slc(acc.idiv)#45 TYPE READSLICE PAR 0-4427 XREFS 29693 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.695150375} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4967 {}}} CYCLES {}}
+set a(0-4964) {NAME ACC1-3:slc(acc.imod#3)#1 TYPE READSLICE PAR 0-4427 XREFS 29694 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.695150375} PREDS {{146 0 0-4451 {}} {258 0 0-4752 {}}} SUCCS {{259 0 0-4965 {}}} CYCLES {}}
+set a(0-4965) {NAME ACC1-3:not#28 TYPE NOT PAR 0-4427 XREFS 29695 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.695150375} PREDS {{146 0 0-4451 {}} {259 0 0-4964 {}}} SUCCS {{258 0 0-4967 {}}} CYCLES {}}
+set a(0-4966) {NAME ACC1-3:slc(acc.imod#3)#2 TYPE READSLICE PAR 0-4427 XREFS 29696 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.695150375} PREDS {{146 0 0-4451 {}} {258 0 0-4752 {}}} SUCCS {{259 0 0-4967 {}}} CYCLES {}}
+set a(0-4967) {NAME ACC1-3:and#1 TYPE AND PAR 0-4427 XREFS 29697 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.695150375} PREDS {{146 0 0-4451 {}} {258 0 0-4965 {}} {258 0 0-4963 {}} {259 0 0-4966 {}}} SUCCS {{259 0 0-4968 {}}} CYCLES {}}
+set a(0-4968) {NAME ACC1:conc#564 TYPE CONCATENATE PAR 0-4427 XREFS 29698 LOC {1 0.3836787 1 0.536173875 1 0.536173875 1 0.695150375} PREDS {{146 0 0-4451 {}} {258 0 0-4962 {}} {259 0 0-4967 {}}} SUCCS {{259 0 0-4969 {}}} CYCLES {}}
+set a(0-4969) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#195 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29699 LOC {1 0.3836787 1 0.536173875 1 0.536173875 1 0.5837300020708271 1 0.7427065020708271} PREDS {{146 0 0-4451 {}} {258 0 0-4960 {}} {259 0 0-4968 {}}} SUCCS {{259 0 0-4970 {}}} CYCLES {}}
+set a(0-4970) {NAME ACC1:slc#60 TYPE READSLICE PAR 0-4427 XREFS 29700 LOC {1 0.43123487499999996 1 0.58373005 1 0.58373005 1 0.74270655} PREDS {{146 0 0-4451 {}} {259 0 0-4969 {}}} SUCCS {{259 0 0-4971 {}}} CYCLES {}}
+set a(0-4971) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#201 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29701 LOC {1 0.43123487499999996 1 0.58373005 1 0.58373005 1 0.6312861770708271 1 0.7902626770708271} PREDS {{146 0 0-4451 {}} {258 0 0-4957 {}} {259 0 0-4970 {}}} SUCCS {{259 0 0-4972 {}}} CYCLES {}}
+set a(0-4972) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#205 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 29702 LOC {1 0.47879105 1 0.631286225 1 0.631286225 1 0.669575684496936 1 0.828552184496936} PREDS {{146 0 0-4451 {}} {258 0 0-4952 {}} {259 0 0-4971 {}}} SUCCS {{259 0 0-4973 {}}} CYCLES {}}
+set a(0-4973) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#208 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-4427 XREFS 29703 LOC {1 0.51708055 1 0.669575725 1 0.669575725 1 0.7174547879329679 1 0.8764312879329679} PREDS {{146 0 0-4451 {}} {258 0 0-4948 {}} {259 0 0-4972 {}}} SUCCS {{259 0 0-4974 {}}} CYCLES {}}
+set a(0-4974) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#211 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-4427 XREFS 29704 LOC {1 0.564959675 1 0.71745485 1 0.71745485 1 0.7698393027684257 1 0.9288158027684257} PREDS {{146 0 0-4451 {}} {258 0 0-4943 {}} {259 0 0-4973 {}}} SUCCS {{258 0 0-4982 {}}} CYCLES {}}
+set a(0-4975) {NAME ACC1-3:slc(acc.psp)#66 TYPE READSLICE PAR 0-4427 XREFS 29705 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.92881585} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4981 {}}} CYCLES {}}
+set a(0-4976) {NAME ACC1-3:slc(acc.psp)#67 TYPE READSLICE PAR 0-4427 XREFS 29706 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.92881585} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4981 {}}} CYCLES {}}
+set a(0-4977) {NAME ACC1-3:slc(acc.psp)#68 TYPE READSLICE PAR 0-4427 XREFS 29707 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.92881585} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4981 {}}} CYCLES {}}
+set a(0-4978) {NAME ACC1-3:slc(acc.psp)#51 TYPE READSLICE PAR 0-4427 XREFS 29708 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.92881585} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-4981 {}}} CYCLES {}}
+set a(0-4979) {NAME ACC1-3:slc(acc.idiv)#27 TYPE READSLICE PAR 0-4427 XREFS 29709 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.92881585} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-4980 {}}} CYCLES {}}
+set a(0-4980) {NAME ACC1-3:exs#13 TYPE SIGNEXTEND PAR 0-4427 XREFS 29710 LOC {1 0.14655495 1 0.7698393499999999 1 0.7698393499999999 1 0.92881585} PREDS {{146 0 0-4451 {}} {259 0 0-4979 {}}} SUCCS {{259 0 0-4981 {}}} CYCLES {}}
+set a(0-4981) {NAME ACC1-3:conc#263 TYPE CONCATENATE PAR 0-4427 XREFS 29711 LOC {1 0.14655495 1 0.7698393499999999 1 0.7698393499999999 1 0.92881585} PREDS {{146 0 0-4451 {}} {258 0 0-4978 {}} {258 0 0-4977 {}} {258 0 0-4976 {}} {258 0 0-4975 {}} {259 0 0-4980 {}}} SUCCS {{259 0 0-4982 {}}} CYCLES {}}
+set a(0-4982) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#213 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 29712 LOC {1 0.6173441749999999 1 0.7698393499999999 1 0.7698393499999999 1 0.8410234533364113 1 0.9999999533364113} PREDS {{146 0 0-4451 {}} {258 0 0-4974 {}} {259 0 0-4981 {}}} SUCCS {{259 0 0-4983 {}}} CYCLES {}}
+set a(0-4983) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME ACC1:acc#215 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-4427 XREFS 29713 LOC {1 0.6885283249999999 1 0.8410234999999999 1 0.8410234999999999 1 0.9205117034997776 2 0.09500765349977768} PREDS {{146 0 0-4451 {}} {258 0 0-4903 {}} {259 0 0-4982 {}}} SUCCS {{258 0 0-5195 {}}} CYCLES {}}
+set a(0-4984) {NAME ACC1-1:slc(acc.psp)#57 TYPE READSLICE PAR 0-4427 XREFS 29714 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7864166499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-4989 {}}} CYCLES {}}
+set a(0-4985) {NAME ACC1-1:slc(acc.psp)#58 TYPE READSLICE PAR 0-4427 XREFS 29715 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7864166499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-4989 {}}} CYCLES {}}
+set a(0-4986) {NAME ACC1-1:slc(acc.psp)#59 TYPE READSLICE PAR 0-4427 XREFS 29716 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7864166499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-4989 {}}} CYCLES {}}
+set a(0-4987) {NAME ACC1-1:slc(acc.psp)#60 TYPE READSLICE PAR 0-4427 XREFS 29717 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7864166499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-4989 {}}} CYCLES {}}
+set a(0-4988) {NAME ACC1-1:slc(acc.psp)#48 TYPE READSLICE PAR 0-4427 XREFS 29718 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7864166499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4989 {}}} CYCLES {}}
+set a(0-4989) {NAME ACC1-1:conc#256 TYPE CONCATENATE PAR 0-4427 XREFS 29719 LOC {1 0.14655495 1 0.641712725 1 0.641712725 1 0.7864166499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4987 {}} {258 0 0-4986 {}} {258 0 0-4985 {}} {258 0 0-4984 {}} {259 0 0-4988 {}}} SUCCS {{258 0 0-5046 {}}} CYCLES {}}
+set a(0-4990) {NAME ACC1-1:slc(acc.psp)#63 TYPE READSLICE PAR 0-4427 XREFS 29720 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.73403215} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-4995 {}}} CYCLES {}}
+set a(0-4991) {NAME ACC1-1:slc(acc.psp)#64 TYPE READSLICE PAR 0-4427 XREFS 29721 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.73403215} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-4995 {}}} CYCLES {}}
+set a(0-4992) {NAME ACC1-1:slc(acc.psp)#50 TYPE READSLICE PAR 0-4427 XREFS 29722 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.73403215} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-4995 {}}} CYCLES {}}
+set a(0-4993) {NAME ACC1-1:slc(acc.psp)#65 TYPE READSLICE PAR 0-4427 XREFS 29723 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.73403215} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4994 {}}} CYCLES {}}
+set a(0-4994) {NAME ACC1-1:exs TYPE SIGNEXTEND PAR 0-4427 XREFS 29724 LOC {1 0.14655495 1 0.5893282249999999 1 0.5893282249999999 1 0.73403215} PREDS {{146 0 0-4451 {}} {259 0 0-4993 {}}} SUCCS {{259 0 0-4995 {}}} CYCLES {}}
+set a(0-4995) {NAME ACC1-1:conc#261 TYPE CONCATENATE PAR 0-4427 XREFS 29725 LOC {1 0.14655495 1 0.5893282249999999 1 0.5893282249999999 1 0.73403215} PREDS {{146 0 0-4451 {}} {258 0 0-4992 {}} {258 0 0-4991 {}} {258 0 0-4990 {}} {259 0 0-4994 {}}} SUCCS {{258 0 0-5045 {}}} CYCLES {}}
+set a(0-4996) {NAME ACC1-1:slc(acc.psp)#36 TYPE READSLICE PAR 0-4427 XREFS 29726 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.690830375} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5000 {}}} CYCLES {}}
+set a(0-4997) {NAME ACC1-1:slc(acc.psp)#37 TYPE READSLICE PAR 0-4427 XREFS 29727 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.690830375} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5000 {}}} CYCLES {}}
+set a(0-4998) {NAME ACC1-1:slc(acc.idiv)#29 TYPE READSLICE PAR 0-4427 XREFS 29728 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.690830375} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-4999 {}}} CYCLES {}}
+set a(0-4999) {NAME ACC1-1:exs#14 TYPE SIGNEXTEND PAR 0-4427 XREFS 29729 LOC {1 0.14655495 1 0.5461264499999999 1 0.5461264499999999 1 0.690830375} PREDS {{146 0 0-4451 {}} {259 0 0-4998 {}}} SUCCS {{259 0 0-5000 {}}} CYCLES {}}
+set a(0-5000) {NAME ACC1-1:conc#265 TYPE CONCATENATE PAR 0-4427 XREFS 29730 LOC {1 0.14655495 1 0.5461264499999999 1 0.5461264499999999 1 0.690830375} PREDS {{146 0 0-4451 {}} {258 0 0-4997 {}} {258 0 0-4996 {}} {259 0 0-4999 {}}} SUCCS {{258 0 0-5044 {}}} CYCLES {}}
+set a(0-5001) {NAME ACC1-1:slc(acc.idiv)#5 TYPE READSLICE PAR 0-4427 XREFS 29731 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5002 {}}} CYCLES {}}
+set a(0-5002) {NAME ACC1-1:exs#2 TYPE SIGNEXTEND PAR 0-4427 XREFS 29732 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5001 {}}} SUCCS {{259 0 0-5003 {}}} CYCLES {}}
+set a(0-5003) {NAME ACC1:conc#576 TYPE CONCATENATE PAR 0-4427 XREFS 29733 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5002 {}}} SUCCS {{258 0 0-5011 {}}} CYCLES {}}
+set a(0-5004) {NAME ACC1-1:slc(acc.idiv)#7 TYPE READSLICE PAR 0-4427 XREFS 29734 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5005 {}}} CYCLES {}}
+set a(0-5005) {NAME ACC1-1:exs#3 TYPE SIGNEXTEND PAR 0-4427 XREFS 29735 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5004 {}}} SUCCS {{258 0 0-5010 {}}} CYCLES {}}
+set a(0-5006) {NAME ACC1-1:slc(acc.imod#3) TYPE READSLICE PAR 0-4427 XREFS 29736 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-4528 {}}} SUCCS {{258 0 0-5009 {}}} CYCLES {}}
+set a(0-5007) {NAME ACC1-1:slc(acc.idiv)#44 TYPE READSLICE PAR 0-4427 XREFS 29737 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5008 {}}} CYCLES {}}
+set a(0-5008) {NAME ACC1-1:not#27 TYPE NOT PAR 0-4427 XREFS 29738 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5007 {}}} SUCCS {{259 0 0-5009 {}}} CYCLES {}}
+set a(0-5009) {NAME ACC1-1:nand TYPE NAND PAR 0-4427 XREFS 29739 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-5006 {}} {259 0 0-5008 {}}} SUCCS {{259 0 0-5010 {}}} CYCLES {}}
+set a(0-5010) {NAME ACC1:conc#577 TYPE CONCATENATE PAR 0-4427 XREFS 29740 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-5005 {}} {259 0 0-5009 {}}} SUCCS {{259 0 0-5011 {}}} CYCLES {}}
+set a(0-5011) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#221 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29741 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.5899270770708271} PREDS {{146 0 0-4451 {}} {258 0 0-5003 {}} {259 0 0-5010 {}}} SUCCS {{259 0 0-5012 {}}} CYCLES {}}
+set a(0-5012) {NAME ACC1:slc#66 TYPE READSLICE PAR 0-4427 XREFS 29742 LOC {1 0.43123487499999996 1 0.4452232 1 0.4452232 1 0.589927125} PREDS {{146 0 0-4451 {}} {259 0 0-5011 {}}} SUCCS {{258 0 0-5023 {}}} CYCLES {}}
+set a(0-5013) {NAME ACC1-1:slc(acc.idiv)#15 TYPE READSLICE PAR 0-4427 XREFS 29743 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5014 {}}} CYCLES {}}
+set a(0-5014) {NAME ACC1-1:exs#7 TYPE SIGNEXTEND PAR 0-4427 XREFS 29744 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5013 {}}} SUCCS {{259 0 0-5015 {}}} CYCLES {}}
+set a(0-5015) {NAME ACC1:conc#574 TYPE CONCATENATE PAR 0-4427 XREFS 29745 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5014 {}}} SUCCS {{258 0 0-5021 {}}} CYCLES {}}
+set a(0-5016) {NAME ACC1-1:slc(acc.idiv)#17 TYPE READSLICE PAR 0-4427 XREFS 29746 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5017 {}}} CYCLES {}}
+set a(0-5017) {NAME ACC1-1:exs#8 TYPE SIGNEXTEND PAR 0-4427 XREFS 29747 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5016 {}}} SUCCS {{258 0 0-5020 {}}} CYCLES {}}
+set a(0-5018) {NAME ACC1-1:slc(acc.imod#2)#12 TYPE READSLICE PAR 0-4427 XREFS 29748 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-4519 {}}} SUCCS {{259 0 0-5019 {}}} CYCLES {}}
+set a(0-5019) {NAME ACC1-1:not#146 TYPE NOT PAR 0-4427 XREFS 29749 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5018 {}}} SUCCS {{259 0 0-5020 {}}} CYCLES {}}
+set a(0-5020) {NAME ACC1:conc#575 TYPE CONCATENATE PAR 0-4427 XREFS 29750 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-5017 {}} {259 0 0-5019 {}}} SUCCS {{259 0 0-5021 {}}} CYCLES {}}
+set a(0-5021) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#220 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29751 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.5899270770708271} PREDS {{146 0 0-4451 {}} {258 0 0-5015 {}} {259 0 0-5020 {}}} SUCCS {{259 0 0-5022 {}}} CYCLES {}}
+set a(0-5022) {NAME ACC1:slc#65 TYPE READSLICE PAR 0-4427 XREFS 29752 LOC {1 0.40398894999999996 1 0.4452232 1 0.4452232 1 0.589927125} PREDS {{146 0 0-4451 {}} {259 0 0-5021 {}}} SUCCS {{259 0 0-5023 {}}} CYCLES {}}
+set a(0-5023) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#227 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29753 LOC {1 0.43123487499999996 1 0.4452232 1 0.4452232 1 0.49277932707082717 1 0.6374832520708271} PREDS {{146 0 0-4451 {}} {258 0 0-5012 {}} {259 0 0-5022 {}}} SUCCS {{258 0 0-5043 {}}} CYCLES {}}
+set a(0-5024) {NAME ACC1-1:slc(acc.idiv)#13 TYPE READSLICE PAR 0-4427 XREFS 29754 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5025 {}}} CYCLES {}}
+set a(0-5025) {NAME ACC1-1:exs#6 TYPE SIGNEXTEND PAR 0-4427 XREFS 29755 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5024 {}}} SUCCS {{259 0 0-5026 {}}} CYCLES {}}
+set a(0-5026) {NAME ACC1:conc#572 TYPE CONCATENATE PAR 0-4427 XREFS 29756 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5025 {}}} SUCCS {{258 0 0-5031 {}}} CYCLES {}}
+set a(0-5027) {NAME ACC1-1:slc(acc.idiv)#23 TYPE READSLICE PAR 0-4427 XREFS 29757 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5028 {}}} CYCLES {}}
+set a(0-5028) {NAME ACC1-1:exs#11 TYPE SIGNEXTEND PAR 0-4427 XREFS 29758 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5027 {}}} SUCCS {{258 0 0-5030 {}}} CYCLES {}}
+set a(0-5029) {NAME ACC1-1:slc(acc.imod#2)#11 TYPE READSLICE PAR 0-4427 XREFS 29759 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-4519 {}}} SUCCS {{259 0 0-5030 {}}} CYCLES {}}
+set a(0-5030) {NAME ACC1:conc#573 TYPE CONCATENATE PAR 0-4427 XREFS 29760 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-5028 {}} {259 0 0-5029 {}}} SUCCS {{259 0 0-5031 {}}} CYCLES {}}
+set a(0-5031) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#219 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29761 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.5899270770708271} PREDS {{146 0 0-4451 {}} {258 0 0-5026 {}} {259 0 0-5030 {}}} SUCCS {{259 0 0-5032 {}}} CYCLES {}}
+set a(0-5032) {NAME ACC1:slc#64 TYPE READSLICE PAR 0-4427 XREFS 29762 LOC {1 0.40398894999999996 1 0.4452232 1 0.4452232 1 0.589927125} PREDS {{146 0 0-4451 {}} {259 0 0-5031 {}}} SUCCS {{258 0 0-5042 {}}} CYCLES {}}
+set a(0-5033) {NAME ACC1-1:slc(acc.idiv)#19 TYPE READSLICE PAR 0-4427 XREFS 29763 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5034 {}}} CYCLES {}}
+set a(0-5034) {NAME ACC1-1:exs#9 TYPE SIGNEXTEND PAR 0-4427 XREFS 29764 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5033 {}}} SUCCS {{259 0 0-5035 {}}} CYCLES {}}
+set a(0-5035) {NAME ACC1:conc#570 TYPE CONCATENATE PAR 0-4427 XREFS 29765 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5034 {}}} SUCCS {{258 0 0-5040 {}}} CYCLES {}}
+set a(0-5036) {NAME ACC1-1:slc(acc.idiv)#21 TYPE READSLICE PAR 0-4427 XREFS 29766 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5037 {}}} CYCLES {}}
+set a(0-5037) {NAME ACC1-1:exs#10 TYPE SIGNEXTEND PAR 0-4427 XREFS 29767 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {259 0 0-5036 {}}} SUCCS {{258 0 0-5039 {}}} CYCLES {}}
+set a(0-5038) {NAME ACC1-1:slc(ACC1:acc#107.psp)#9 TYPE READSLICE PAR 0-4427 XREFS 29768 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-4501 {}}} SUCCS {{259 0 0-5039 {}}} CYCLES {}}
+set a(0-5039) {NAME ACC1:conc#571 TYPE CONCATENATE PAR 0-4427 XREFS 29769 LOC {1 0.267931 1 0.397667025 1 0.397667025 1 0.54237095} PREDS {{146 0 0-4451 {}} {258 0 0-5037 {}} {259 0 0-5038 {}}} SUCCS {{259 0 0-5040 {}}} CYCLES {}}
+set a(0-5040) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#218 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29770 LOC {1 0.267931 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.5899270770708271} PREDS {{146 0 0-4451 {}} {258 0 0-5035 {}} {259 0 0-5039 {}}} SUCCS {{259 0 0-5041 {}}} CYCLES {}}
+set a(0-5041) {NAME ACC1:slc#63 TYPE READSLICE PAR 0-4427 XREFS 29771 LOC {1 0.315487175 1 0.4452232 1 0.4452232 1 0.589927125} PREDS {{146 0 0-4451 {}} {259 0 0-5040 {}}} SUCCS {{259 0 0-5042 {}}} CYCLES {}}
+set a(0-5042) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#226 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29772 LOC {1 0.40398894999999996 1 0.4452232 1 0.4452232 1 0.49277932707082717 1 0.6374832520708271} PREDS {{146 0 0-4451 {}} {258 0 0-5032 {}} {259 0 0-5041 {}}} SUCCS {{259 0 0-5043 {}}} CYCLES {}}
+set a(0-5043) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#231 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-4427 XREFS 29773 LOC {1 0.47879105 1 0.49277937499999996 1 0.49277937499999996 1 0.5461263951789505 1 0.6908303201789505} PREDS {{146 0 0-4451 {}} {258 0 0-5023 {}} {259 0 0-5042 {}}} SUCCS {{259 0 0-5044 {}}} CYCLES {}}
+set a(0-5044) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME ACC1:acc#234 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 29774 LOC {1 0.532138125 1 0.5461264499999999 1 0.5461264499999999 1 0.5893281734103023 1 0.7340320984103024} PREDS {{146 0 0-4451 {}} {258 0 0-5000 {}} {259 0 0-5043 {}}} SUCCS {{259 0 0-5045 {}}} CYCLES {}}
+set a(0-5045) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#237 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-4427 XREFS 29775 LOC {1 0.5753399 1 0.5893282249999999 1 0.5893282249999999 1 0.6417126777684257 1 0.7864166027684257} PREDS {{146 0 0-4451 {}} {258 0 0-4995 {}} {259 0 0-5044 {}}} SUCCS {{259 0 0-5046 {}}} CYCLES {}}
+set a(0-5046) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,0,10) AREA_SCORE 10.25 QUANTITY 5 NAME ACC1:acc#239 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-4427 XREFS 29776 LOC {1 0.6277244 1 0.641712725 1 0.641712725 1 0.71889620686502 1 0.8636001318650199} PREDS {{146 0 0-4451 {}} {258 0 0-4989 {}} {259 0 0-5045 {}}} SUCCS {{258 0 0-5118 {}}} CYCLES {}}
+set a(0-5047) {NAME ACC1-1:slc(acc.psp)#29 TYPE READSLICE PAR 0-4427 XREFS 29777 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.60661385} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5048 {}}} CYCLES {}}
+set a(0-5048) {NAME ACC1:conc#565 TYPE CONCATENATE PAR 0-4427 XREFS 29778 LOC {1 0.14655495 1 0.461909925 1 0.461909925 1 0.60661385} PREDS {{146 0 0-4451 {}} {259 0 0-5047 {}}} SUCCS {{259 0 0-5049 {}}} CYCLES {}}
+set a(0-5049) {NAME ACC1:conc#566 TYPE CONCATENATE PAR 0-4427 XREFS 29779 LOC {1 0.14655495 1 0.461909925 1 0.461909925 1 0.60661385} PREDS {{146 0 0-4451 {}} {259 0 0-5048 {}}} SUCCS {{258 0 0-5053 {}}} CYCLES {}}
+set a(0-5050) {NAME ACC1-1:slc(ACC1:acc#107.psp)#10 TYPE READSLICE PAR 0-4427 XREFS 29780 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.60661385} PREDS {{146 0 0-4451 {}} {258 0 0-4501 {}}} SUCCS {{258 0 0-5052 {}}} CYCLES {}}
+set a(0-5051) {NAME ACC1-1:slc(acc.psp)#30 TYPE READSLICE PAR 0-4427 XREFS 29781 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.60661385} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5052 {}}} CYCLES {}}
+set a(0-5052) {NAME ACC1:conc#567 TYPE CONCATENATE PAR 0-4427 XREFS 29782 LOC {1 0.267931 1 0.461909925 1 0.461909925 1 0.60661385} PREDS {{146 0 0-4451 {}} {258 0 0-5050 {}} {259 0 0-5051 {}}} SUCCS {{259 0 0-5053 {}}} CYCLES {}}
+set a(0-5053) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#216 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-4427 XREFS 29783 LOC {1 0.267931 1 0.461909925 1 0.461909925 1 0.49953050202417165 1 0.6442344270241717} PREDS {{146 0 0-4451 {}} {258 0 0-5049 {}} {259 0 0-5052 {}}} SUCCS {{259 0 0-5054 {}}} CYCLES {}}
+set a(0-5054) {NAME ACC1:slc#61 TYPE READSLICE PAR 0-4427 XREFS 29784 LOC {1 0.305551625 1 0.49953054999999996 1 0.49953054999999996 1 0.644234475} PREDS {{146 0 0-4451 {}} {259 0 0-5053 {}}} SUCCS {{258 0 0-5056 {}}} CYCLES {}}
+set a(0-5055) {NAME ACC1-1:slc(ACC1:acc#116.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 29785 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.644234475} PREDS {{146 0 0-4451 {}} {258 0 0-4512 {}}} SUCCS {{259 0 0-5056 {}}} CYCLES {}}
+set a(0-5056) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#225 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-4427 XREFS 29786 LOC {1 0.32918685 1 0.49953054999999996 1 0.49953054999999996 1 0.5371511270241717 1 0.6818550520241716} PREDS {{146 0 0-4451 {}} {258 0 0-5054 {}} {259 0 0-5055 {}}} SUCCS {{258 0 0-5068 {}}} CYCLES {}}
+set a(0-5057) {NAME ACC1-1:slc(acc.psp)#31 TYPE READSLICE PAR 0-4427 XREFS 29787 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6546091749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5059 {}}} CYCLES {}}
+set a(0-5058) {NAME ACC1-1:slc(acc.psp)#32 TYPE READSLICE PAR 0-4427 XREFS 29788 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6546091749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5059 {}}} CYCLES {}}
+set a(0-5059) {NAME ACC1-1:conc#258 TYPE CONCATENATE PAR 0-4427 XREFS 29789 LOC {1 0.14655495 1 0.50990525 1 0.50990525 1 0.6546091749999999} PREDS {{146 0 0-4451 {}} {258 0 0-5057 {}} {259 0 0-5058 {}}} SUCCS {{259 0 0-5060 {}}} CYCLES {}}
+set a(0-5060) {NAME ACC1:conc#568 TYPE CONCATENATE PAR 0-4427 XREFS 29790 LOC {1 0.14655495 1 0.50990525 1 0.50990525 1 0.6546091749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5059 {}}} SUCCS {{258 0 0-5066 {}}} CYCLES {}}
+set a(0-5061) {NAME ACC1-1:slc(ACC1:acc#107.psp)#11 TYPE READSLICE PAR 0-4427 XREFS 29791 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.6546091749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4501 {}}} SUCCS {{258 0 0-5063 {}}} CYCLES {}}
+set a(0-5062) {NAME ACC1-1:slc(acc.psp)#33 TYPE READSLICE PAR 0-4427 XREFS 29792 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6546091749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5063 {}}} CYCLES {}}
+set a(0-5063) {NAME ACC1-1:conc#259 TYPE CONCATENATE PAR 0-4427 XREFS 29793 LOC {1 0.267931 1 0.50990525 1 0.50990525 1 0.6546091749999999} PREDS {{146 0 0-4451 {}} {258 0 0-5061 {}} {259 0 0-5062 {}}} SUCCS {{258 0 0-5065 {}}} CYCLES {}}
+set a(0-5064) {NAME ACC1-1:slc(ACC1:acc#107.psp)#8 TYPE READSLICE PAR 0-4427 XREFS 29794 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.6546091749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4501 {}}} SUCCS {{259 0 0-5065 {}}} CYCLES {}}
+set a(0-5065) {NAME ACC1:conc#569 TYPE CONCATENATE PAR 0-4427 XREFS 29795 LOC {1 0.267931 1 0.50990525 1 0.50990525 1 0.6546091749999999} PREDS {{146 0 0-4451 {}} {258 0 0-5063 {}} {259 0 0-5064 {}}} SUCCS {{259 0 0-5066 {}}} CYCLES {}}
+set a(0-5066) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#217 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29796 LOC {1 0.267931 1 0.50990525 1 0.50990525 1 0.5371511270708271 1 0.6818550520708271} PREDS {{146 0 0-4451 {}} {258 0 0-5060 {}} {259 0 0-5065 {}}} SUCCS {{259 0 0-5067 {}}} CYCLES {}}
+set a(0-5067) {NAME ACC1:slc#62 TYPE READSLICE PAR 0-4427 XREFS 29797 LOC {1 0.295176925 1 0.537151175 1 0.537151175 1 0.6818550999999999} PREDS {{146 0 0-4451 {}} {259 0 0-5066 {}}} SUCCS {{259 0 0-5068 {}}} CYCLES {}}
+set a(0-5068) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#230 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 29798 LOC {1 0.366807475 1 0.537151175 1 0.537151175 1 0.5803430701789505 1 0.7250469951789504} PREDS {{146 0 0-4451 {}} {258 0 0-5056 {}} {259 0 0-5067 {}}} SUCCS {{258 0 0-5080 {}}} CYCLES {}}
+set a(0-5069) {NAME ACC1-1:slc(acc.psp)#34 TYPE READSLICE PAR 0-4427 XREFS 29799 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.692010225} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5073 {}}} CYCLES {}}
+set a(0-5070) {NAME ACC1-1:slc(acc.psp)#35 TYPE READSLICE PAR 0-4427 XREFS 29800 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.692010225} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5073 {}}} CYCLES {}}
+set a(0-5071) {NAME ACC1-1:slc(acc.idiv)#31 TYPE READSLICE PAR 0-4427 XREFS 29801 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.692010225} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5072 {}}} CYCLES {}}
+set a(0-5072) {NAME ACC1-1:exs#15 TYPE SIGNEXTEND PAR 0-4427 XREFS 29802 LOC {1 0.14655495 1 0.5473063 1 0.5473063 1 0.692010225} PREDS {{146 0 0-4451 {}} {259 0 0-5071 {}}} SUCCS {{259 0 0-5073 {}}} CYCLES {}}
+set a(0-5073) {NAME ACC1-1:conc#260 TYPE CONCATENATE PAR 0-4427 XREFS 29803 LOC {1 0.14655495 1 0.5473063 1 0.5473063 1 0.692010225} PREDS {{146 0 0-4451 {}} {258 0 0-5070 {}} {258 0 0-5069 {}} {259 0 0-5072 {}}} SUCCS {{258 0 0-5079 {}}} CYCLES {}}
+set a(0-5074) {NAME ACC1-1:slc(acc.idiv)#33 TYPE READSLICE PAR 0-4427 XREFS 29804 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6512271749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5075 {}}} CYCLES {}}
+set a(0-5075) {NAME ACC1-1:exs#16 TYPE SIGNEXTEND PAR 0-4427 XREFS 29805 LOC {1 0.14655495 1 0.50652325 1 0.50652325 1 0.6512271749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5074 {}}} SUCCS {{258 0 0-5078 {}}} CYCLES {}}
+set a(0-5076) {NAME ACC1-1:slc(acc.idiv)#35 TYPE READSLICE PAR 0-4427 XREFS 29806 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6512271749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5077 {}}} CYCLES {}}
+set a(0-5077) {NAME ACC1-1:exs#17 TYPE SIGNEXTEND PAR 0-4427 XREFS 29807 LOC {1 0.14655495 1 0.50652325 1 0.50652325 1 0.6512271749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5076 {}}} SUCCS {{259 0 0-5078 {}}} CYCLES {}}
+set a(0-5078) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#224 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29808 LOC {1 0.14655495 1 0.50652325 1 0.50652325 1 0.5473062600894752 1 0.6920101850894752} PREDS {{146 0 0-4451 {}} {258 0 0-5075 {}} {259 0 0-5077 {}}} SUCCS {{259 0 0-5079 {}}} CYCLES {}}
+set a(0-5079) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#229 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-4427 XREFS 29809 LOC {1 0.187338 1 0.5473063 1 0.5473063 1 0.5803430701789505 1 0.7250469951789504} PREDS {{146 0 0-4451 {}} {258 0 0-5073 {}} {259 0 0-5078 {}}} SUCCS {{259 0 0-5080 {}}} CYCLES {}}
+set a(0-5080) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#233 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 29810 LOC {1 0.409999425 1 0.580343125 1 0.580343125 1 0.618632584496936 1 0.763336509496936} PREDS {{146 0 0-4451 {}} {258 0 0-5068 {}} {259 0 0-5079 {}}} SUCCS {{258 0 0-5086 {}}} CYCLES {}}
+set a(0-5081) {NAME ACC1-1:slc(acc.psp)#54 TYPE READSLICE PAR 0-4427 XREFS 29811 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.76333655} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5085 {}}} CYCLES {}}
+set a(0-5082) {NAME ACC1-1:slc(acc.psp)#55 TYPE READSLICE PAR 0-4427 XREFS 29812 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.76333655} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5085 {}}} CYCLES {}}
+set a(0-5083) {NAME ACC1-1:slc(acc.psp)#56 TYPE READSLICE PAR 0-4427 XREFS 29813 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.76333655} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5085 {}}} CYCLES {}}
+set a(0-5084) {NAME ACC1-1:slc(acc.psp)#47 TYPE READSLICE PAR 0-4427 XREFS 29814 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.76333655} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5085 {}}} CYCLES {}}
+set a(0-5085) {NAME ACC1-1:conc#255 TYPE CONCATENATE PAR 0-4427 XREFS 29815 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.76333655} PREDS {{146 0 0-4451 {}} {258 0 0-5083 {}} {258 0 0-5082 {}} {258 0 0-5081 {}} {259 0 0-5084 {}}} SUCCS {{259 0 0-5086 {}}} CYCLES {}}
+set a(0-5086) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#236 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-4427 XREFS 29816 LOC {1 0.448288925 1 0.6186326249999999 1 0.6186326249999999 1 0.6665116879329679 1 0.811215612932968} PREDS {{146 0 0-4451 {}} {258 0 0-5080 {}} {259 0 0-5085 {}}} SUCCS {{258 0 0-5117 {}}} CYCLES {}}
+set a(0-5087) {NAME ACC1-1:slc(acc.psp)#17 TYPE READSLICE PAR 0-4427 XREFS 29817 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.76333655} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5090 {}}} CYCLES {}}
+set a(0-5088) {NAME ACC1-1:slc(acc.idiv)#25 TYPE READSLICE PAR 0-4427 XREFS 29818 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.76333655} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5089 {}}} CYCLES {}}
+set a(0-5089) {NAME ACC1-1:exs#12 TYPE SIGNEXTEND PAR 0-4427 XREFS 29819 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.76333655} PREDS {{146 0 0-4451 {}} {259 0 0-5088 {}}} SUCCS {{259 0 0-5090 {}}} CYCLES {}}
+set a(0-5090) {NAME ACC1-1:conc#226 TYPE CONCATENATE PAR 0-4427 XREFS 29820 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.76333655} PREDS {{146 0 0-4451 {}} {258 0 0-5087 {}} {259 0 0-5089 {}}} SUCCS {{259 0 0-5091 {}}} CYCLES {}}
+set a(0-5091) {NAME ACC1-1:exs#538 TYPE SIGNEXTEND PAR 0-4427 XREFS 29821 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.76333655} PREDS {{146 0 0-4451 {}} {259 0 0-5090 {}}} SUCCS {{258 0 0-5116 {}}} CYCLES {}}
+set a(0-5092) {NAME ACC1-1:slc(acc.psp)#52 TYPE READSLICE PAR 0-4427 XREFS 29822 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7250470499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5095 {}}} CYCLES {}}
+set a(0-5093) {NAME ACC1-1:slc(acc.psp)#53 TYPE READSLICE PAR 0-4427 XREFS 29823 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7250470499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5095 {}}} CYCLES {}}
+set a(0-5094) {NAME ACC1-1:slc(acc.psp)#46 TYPE READSLICE PAR 0-4427 XREFS 29824 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.7250470499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5095 {}}} CYCLES {}}
+set a(0-5095) {NAME ACC1-1:conc TYPE CONCATENATE PAR 0-4427 XREFS 29825 LOC {1 0.14655495 1 0.580343125 1 0.580343125 1 0.7250470499999999} PREDS {{146 0 0-4451 {}} {258 0 0-5093 {}} {258 0 0-5092 {}} {259 0 0-5094 {}}} SUCCS {{258 0 0-5115 {}}} CYCLES {}}
+set a(0-5096) {NAME ACC1-1:slc(acc.idiv)#9 TYPE READSLICE PAR 0-4427 XREFS 29826 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.636707825} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5097 {}}} CYCLES {}}
+set a(0-5097) {NAME ACC1-1:exs#4 TYPE SIGNEXTEND PAR 0-4427 XREFS 29827 LOC {1 0.14655495 1 0.4920039 1 0.4920039 1 0.636707825} PREDS {{146 0 0-4451 {}} {259 0 0-5096 {}}} SUCCS {{258 0 0-5100 {}}} CYCLES {}}
+set a(0-5098) {NAME ACC1-1:slc(acc.idiv)#11 TYPE READSLICE PAR 0-4427 XREFS 29828 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.636707825} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5099 {}}} CYCLES {}}
+set a(0-5099) {NAME ACC1-1:exs#5 TYPE SIGNEXTEND PAR 0-4427 XREFS 29829 LOC {1 0.14655495 1 0.4920039 1 0.4920039 1 0.636707825} PREDS {{146 0 0-4451 {}} {259 0 0-5098 {}}} SUCCS {{259 0 0-5100 {}}} CYCLES {}}
+set a(0-5100) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#223 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29830 LOC {1 0.14655495 1 0.4920039 1 0.4920039 1 0.5327869100894752 1 0.6774908350894753} PREDS {{146 0 0-4451 {}} {258 0 0-5097 {}} {259 0 0-5099 {}}} SUCCS {{258 0 0-5114 {}}} CYCLES {}}
+set a(0-5101) {NAME ACC1-1:slc(acc.idiv)#1 TYPE READSLICE PAR 0-4427 XREFS 29831 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6299347} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5102 {}}} CYCLES {}}
+set a(0-5102) {NAME ACC1-1:exs#496 TYPE SIGNEXTEND PAR 0-4427 XREFS 29832 LOC {1 0.14655495 1 0.485230775 1 0.485230775 1 0.6299347} PREDS {{146 0 0-4451 {}} {259 0 0-5101 {}}} SUCCS {{259 0 0-5103 {}}} CYCLES {}}
+set a(0-5103) {NAME ACC1:conc#578 TYPE CONCATENATE PAR 0-4427 XREFS 29833 LOC {1 0.14655495 1 0.485230775 1 0.485230775 1 0.6299347} PREDS {{146 0 0-4451 {}} {259 0 0-5102 {}}} SUCCS {{258 0 0-5112 {}}} CYCLES {}}
+set a(0-5104) {NAME ACC1-1:slc(acc.idiv)#3 TYPE READSLICE PAR 0-4427 XREFS 29834 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6299347} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5105 {}}} CYCLES {}}
+set a(0-5105) {NAME ACC1-1:exs#1 TYPE SIGNEXTEND PAR 0-4427 XREFS 29835 LOC {1 0.14655495 1 0.485230775 1 0.485230775 1 0.6299347} PREDS {{146 0 0-4451 {}} {259 0 0-5104 {}}} SUCCS {{258 0 0-5111 {}}} CYCLES {}}
+set a(0-5106) {NAME ACC1-1:slc(acc.idiv)#45 TYPE READSLICE PAR 0-4427 XREFS 29836 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6299347} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5110 {}}} CYCLES {}}
+set a(0-5107) {NAME ACC1-1:slc(acc.imod#3)#1 TYPE READSLICE PAR 0-4427 XREFS 29837 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.6299347} PREDS {{146 0 0-4451 {}} {258 0 0-4528 {}}} SUCCS {{259 0 0-5108 {}}} CYCLES {}}
+set a(0-5108) {NAME ACC1-1:not#28 TYPE NOT PAR 0-4427 XREFS 29838 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.6299347} PREDS {{146 0 0-4451 {}} {259 0 0-5107 {}}} SUCCS {{258 0 0-5110 {}}} CYCLES {}}
+set a(0-5109) {NAME ACC1-1:slc(acc.imod#3)#2 TYPE READSLICE PAR 0-4427 XREFS 29839 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.6299347} PREDS {{146 0 0-4451 {}} {258 0 0-4528 {}}} SUCCS {{259 0 0-5110 {}}} CYCLES {}}
+set a(0-5110) {NAME ACC1-1:and#1 TYPE AND PAR 0-4427 XREFS 29840 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.6299347} PREDS {{146 0 0-4451 {}} {258 0 0-5108 {}} {258 0 0-5106 {}} {259 0 0-5109 {}}} SUCCS {{259 0 0-5111 {}}} CYCLES {}}
+set a(0-5111) {NAME ACC1:conc#579 TYPE CONCATENATE PAR 0-4427 XREFS 29841 LOC {1 0.3836787 1 0.485230775 1 0.485230775 1 0.6299347} PREDS {{146 0 0-4451 {}} {258 0 0-5105 {}} {259 0 0-5110 {}}} SUCCS {{259 0 0-5112 {}}} CYCLES {}}
+set a(0-5112) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#222 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29842 LOC {1 0.3836787 1 0.485230775 1 0.485230775 1 0.5327869020708271 1 0.6774908270708271} PREDS {{146 0 0-4451 {}} {258 0 0-5103 {}} {259 0 0-5111 {}}} SUCCS {{259 0 0-5113 {}}} CYCLES {}}
+set a(0-5113) {NAME ACC1:slc#67 TYPE READSLICE PAR 0-4427 XREFS 29843 LOC {1 0.43123487499999996 1 0.53278695 1 0.53278695 1 0.6774908749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5112 {}}} SUCCS {{259 0 0-5114 {}}} CYCLES {}}
+set a(0-5114) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#228 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29844 LOC {1 0.43123487499999996 1 0.53278695 1 0.53278695 1 0.5803430770708271 1 0.7250470020708271} PREDS {{146 0 0-4451 {}} {258 0 0-5100 {}} {259 0 0-5113 {}}} SUCCS {{259 0 0-5115 {}}} CYCLES {}}
+set a(0-5115) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#232 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 29845 LOC {1 0.47879105 1 0.580343125 1 0.580343125 1 0.618632584496936 1 0.763336509496936} PREDS {{146 0 0-4451 {}} {258 0 0-5095 {}} {259 0 0-5114 {}}} SUCCS {{259 0 0-5116 {}}} CYCLES {}}
+set a(0-5116) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#235 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-4427 XREFS 29846 LOC {1 0.51708055 1 0.6186326249999999 1 0.6186326249999999 1 0.6665116879329679 1 0.811215612932968} PREDS {{146 0 0-4451 {}} {258 0 0-5091 {}} {259 0 0-5115 {}}} SUCCS {{259 0 0-5117 {}}} CYCLES {}}
+set a(0-5117) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#238 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-4427 XREFS 29847 LOC {1 0.564959675 1 0.66651175 1 0.66651175 1 0.7188962027684257 1 0.8636001277684257} PREDS {{146 0 0-4451 {}} {258 0 0-5086 {}} {259 0 0-5116 {}}} SUCCS {{259 0 0-5118 {}}} CYCLES {}}
+set a(0-5118) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#241 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 29848 LOC {1 0.704907925 1 0.71889625 1 0.71889625 1 0.7900803533364114 1 0.9347842783364113} PREDS {{146 0 0-4451 {}} {258 0 0-5046 {}} {259 0 0-5117 {}}} SUCCS {{258 0 0-5130 {}}} CYCLES {}}
+set a(0-5119) {NAME ACC1-1:slc(acc.psp)#62 TYPE READSLICE PAR 0-4427 XREFS 29849 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5121 {}}} CYCLES {}}
+set a(0-5120) {NAME ACC1-1:slc(acc.psp)#49 TYPE READSLICE PAR 0-4427 XREFS 29850 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5121 {}}} CYCLES {}}
+set a(0-5121) {NAME ACC1-1:conc#257 TYPE CONCATENATE PAR 0-4427 XREFS 29851 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.8534450499999999} PREDS {{146 0 0-4451 {}} {258 0 0-5119 {}} {259 0 0-5120 {}}} SUCCS {{258 0 0-5129 {}}} CYCLES {}}
+set a(0-5122) {NAME ACC1-1:slc(acc.psp)#66 TYPE READSLICE PAR 0-4427 XREFS 29852 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5128 {}}} CYCLES {}}
+set a(0-5123) {NAME ACC1-1:slc(acc.psp)#67 TYPE READSLICE PAR 0-4427 XREFS 29853 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5128 {}}} CYCLES {}}
+set a(0-5124) {NAME ACC1-1:slc(acc.psp)#68 TYPE READSLICE PAR 0-4427 XREFS 29854 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5128 {}}} CYCLES {}}
+set a(0-5125) {NAME ACC1-1:slc(acc.psp)#51 TYPE READSLICE PAR 0-4427 XREFS 29855 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{258 0 0-5128 {}}} CYCLES {}}
+set a(0-5126) {NAME ACC1-1:slc(acc.idiv)#27 TYPE READSLICE PAR 0-4427 XREFS 29856 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.8534450499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4461 {}}} SUCCS {{259 0 0-5127 {}}} CYCLES {}}
+set a(0-5127) {NAME ACC1-1:exs#13 TYPE SIGNEXTEND PAR 0-4427 XREFS 29857 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.8534450499999999} PREDS {{146 0 0-4451 {}} {259 0 0-5126 {}}} SUCCS {{259 0 0-5128 {}}} CYCLES {}}
+set a(0-5128) {NAME ACC1-1:conc#263 TYPE CONCATENATE PAR 0-4427 XREFS 29858 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.8534450499999999} PREDS {{146 0 0-4451 {}} {258 0 0-5125 {}} {258 0 0-5124 {}} {258 0 0-5123 {}} {258 0 0-5122 {}} {259 0 0-5127 {}}} SUCCS {{259 0 0-5129 {}}} CYCLES {}}
+set a(0-5129) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,11) AREA_SCORE 11.24 QUANTITY 2 NAME ACC1:acc#240 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-4427 XREFS 29859 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.7900803533364112 1 0.9347842783364112} PREDS {{146 0 0-4451 {}} {258 0 0-5121 {}} {259 0 0-5128 {}}} SUCCS {{259 0 0-5130 {}}} CYCLES {}}
+set a(0-5130) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,13) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1-1:acc#122 TYPE ACCU DELAY {1.04 ns} LIBRARY_DELAY {1.04 ns} PAR 0-4427 XREFS 29860 LOC {1 0.776092075 1 0.7900804 1 0.7900804 1 0.8552960313734284 1 0.9999999563734283} PREDS {{146 0 0-4451 {}} {258 0 0-5118 {}} {259 0 0-5129 {}}} SUCCS {{258 0 0-5194 {}}} CYCLES {}}
+set a(0-5131) {NAME ACC1-3:slc(acc.psp)#57 TYPE READSLICE PAR 0-4427 XREFS 29861 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.922816475} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-5136 {}}} CYCLES {}}
+set a(0-5132) {NAME ACC1-3:slc(acc.psp)#58 TYPE READSLICE PAR 0-4427 XREFS 29862 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.922816475} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-5136 {}}} CYCLES {}}
+set a(0-5133) {NAME ACC1-3:slc(acc.psp)#59 TYPE READSLICE PAR 0-4427 XREFS 29863 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.922816475} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-5136 {}}} CYCLES {}}
+set a(0-5134) {NAME ACC1-3:slc(acc.psp)#60 TYPE READSLICE PAR 0-4427 XREFS 29864 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.922816475} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-5136 {}}} CYCLES {}}
+set a(0-5135) {NAME ACC1-3:slc(acc.psp)#48 TYPE READSLICE PAR 0-4427 XREFS 29865 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.922816475} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-5136 {}}} CYCLES {}}
+set a(0-5136) {NAME ACC1-3:conc#256 TYPE CONCATENATE PAR 0-4427 XREFS 29866 LOC {1 0.14655495 1 0.77811255 1 0.77811255 1 0.922816475} PREDS {{146 0 0-4451 {}} {258 0 0-5134 {}} {258 0 0-5133 {}} {258 0 0-5132 {}} {258 0 0-5131 {}} {259 0 0-5135 {}}} SUCCS {{258 0 0-5193 {}}} CYCLES {}}
+set a(0-5137) {NAME ACC1-3:slc(acc.psp)#63 TYPE READSLICE PAR 0-4427 XREFS 29867 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8704319749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-5142 {}}} CYCLES {}}
+set a(0-5138) {NAME ACC1-3:slc(acc.psp)#64 TYPE READSLICE PAR 0-4427 XREFS 29868 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8704319749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-5142 {}}} CYCLES {}}
+set a(0-5139) {NAME ACC1-3:slc(acc.psp)#50 TYPE READSLICE PAR 0-4427 XREFS 29869 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8704319749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-5142 {}}} CYCLES {}}
+set a(0-5140) {NAME ACC1-3:slc(acc.psp)#65 TYPE READSLICE PAR 0-4427 XREFS 29870 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8704319749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-5141 {}}} CYCLES {}}
+set a(0-5141) {NAME ACC1-3:exs TYPE SIGNEXTEND PAR 0-4427 XREFS 29871 LOC {1 0.14655495 1 0.72572805 1 0.72572805 1 0.8704319749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5140 {}}} SUCCS {{259 0 0-5142 {}}} CYCLES {}}
+set a(0-5142) {NAME ACC1-3:conc#261 TYPE CONCATENATE PAR 0-4427 XREFS 29872 LOC {1 0.14655495 1 0.72572805 1 0.72572805 1 0.8704319749999999} PREDS {{146 0 0-4451 {}} {258 0 0-5139 {}} {258 0 0-5138 {}} {258 0 0-5137 {}} {259 0 0-5141 {}}} SUCCS {{258 0 0-5192 {}}} CYCLES {}}
+set a(0-5143) {NAME ACC1-3:slc(acc.psp)#36 TYPE READSLICE PAR 0-4427 XREFS 29873 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8272301999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-5147 {}}} CYCLES {}}
+set a(0-5144) {NAME ACC1-3:slc(acc.psp)#37 TYPE READSLICE PAR 0-4427 XREFS 29874 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8272301999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{258 0 0-5147 {}}} CYCLES {}}
+set a(0-5145) {NAME ACC1-3:slc(acc.idiv)#29 TYPE READSLICE PAR 0-4427 XREFS 29875 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8272301999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-5146 {}}} CYCLES {}}
+set a(0-5146) {NAME ACC1-3:exs#14 TYPE SIGNEXTEND PAR 0-4427 XREFS 29876 LOC {1 0.14655495 1 0.682526275 1 0.682526275 1 0.8272301999999999} PREDS {{146 0 0-4451 {}} {259 0 0-5145 {}}} SUCCS {{259 0 0-5147 {}}} CYCLES {}}
+set a(0-5147) {NAME ACC1-3:conc#265 TYPE CONCATENATE PAR 0-4427 XREFS 29877 LOC {1 0.14655495 1 0.682526275 1 0.682526275 1 0.8272301999999999} PREDS {{146 0 0-4451 {}} {258 0 0-5144 {}} {258 0 0-5143 {}} {259 0 0-5146 {}}} SUCCS {{258 0 0-5191 {}}} CYCLES {}}
+set a(0-5148) {NAME ACC1-3:slc(acc.idiv)#5 TYPE READSLICE PAR 0-4427 XREFS 29878 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-5149 {}}} CYCLES {}}
+set a(0-5149) {NAME ACC1-3:exs#2 TYPE SIGNEXTEND PAR 0-4427 XREFS 29879 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5148 {}}} SUCCS {{259 0 0-5150 {}}} CYCLES {}}
+set a(0-5150) {NAME ACC1:conc#561 TYPE CONCATENATE PAR 0-4427 XREFS 29880 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5149 {}}} SUCCS {{258 0 0-5158 {}}} CYCLES {}}
+set a(0-5151) {NAME ACC1-3:slc(acc.idiv)#7 TYPE READSLICE PAR 0-4427 XREFS 29881 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-5152 {}}} CYCLES {}}
+set a(0-5152) {NAME ACC1-3:exs#3 TYPE SIGNEXTEND PAR 0-4427 XREFS 29882 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5151 {}}} SUCCS {{258 0 0-5157 {}}} CYCLES {}}
+set a(0-5153) {NAME ACC1-3:slc(acc.imod#3) TYPE READSLICE PAR 0-4427 XREFS 29883 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4752 {}}} SUCCS {{258 0 0-5156 {}}} CYCLES {}}
+set a(0-5154) {NAME ACC1-3:slc(acc.idiv)#44 TYPE READSLICE PAR 0-4427 XREFS 29884 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-5155 {}}} CYCLES {}}
+set a(0-5155) {NAME ACC1-3:not#27 TYPE NOT PAR 0-4427 XREFS 29885 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5154 {}}} SUCCS {{259 0 0-5156 {}}} CYCLES {}}
+set a(0-5156) {NAME ACC1-3:nand TYPE NAND PAR 0-4427 XREFS 29886 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-5153 {}} {259 0 0-5155 {}}} SUCCS {{259 0 0-5157 {}}} CYCLES {}}
+set a(0-5157) {NAME ACC1:conc#562 TYPE CONCATENATE PAR 0-4427 XREFS 29887 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-5152 {}} {259 0 0-5156 {}}} SUCCS {{259 0 0-5158 {}}} CYCLES {}}
+set a(0-5158) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#194 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29888 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.7263269020708271} PREDS {{146 0 0-4451 {}} {258 0 0-5150 {}} {259 0 0-5157 {}}} SUCCS {{259 0 0-5159 {}}} CYCLES {}}
+set a(0-5159) {NAME ACC1:slc#59 TYPE READSLICE PAR 0-4427 XREFS 29889 LOC {1 0.43123487499999996 1 0.581623025 1 0.581623025 1 0.7263269499999999} PREDS {{146 0 0-4451 {}} {259 0 0-5158 {}}} SUCCS {{258 0 0-5170 {}}} CYCLES {}}
+set a(0-5160) {NAME ACC1-3:slc(acc.idiv)#15 TYPE READSLICE PAR 0-4427 XREFS 29890 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-5161 {}}} CYCLES {}}
+set a(0-5161) {NAME ACC1-3:exs#7 TYPE SIGNEXTEND PAR 0-4427 XREFS 29891 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5160 {}}} SUCCS {{259 0 0-5162 {}}} CYCLES {}}
+set a(0-5162) {NAME ACC1:conc#559 TYPE CONCATENATE PAR 0-4427 XREFS 29892 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5161 {}}} SUCCS {{258 0 0-5168 {}}} CYCLES {}}
+set a(0-5163) {NAME ACC1-3:slc(acc.idiv)#17 TYPE READSLICE PAR 0-4427 XREFS 29893 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-5164 {}}} CYCLES {}}
+set a(0-5164) {NAME ACC1-3:exs#8 TYPE SIGNEXTEND PAR 0-4427 XREFS 29894 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5163 {}}} SUCCS {{258 0 0-5167 {}}} CYCLES {}}
+set a(0-5165) {NAME ACC1-3:slc(acc.imod#2)#12 TYPE READSLICE PAR 0-4427 XREFS 29895 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4743 {}}} SUCCS {{259 0 0-5166 {}}} CYCLES {}}
+set a(0-5166) {NAME ACC1-3:not#146 TYPE NOT PAR 0-4427 XREFS 29896 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5165 {}}} SUCCS {{259 0 0-5167 {}}} CYCLES {}}
+set a(0-5167) {NAME ACC1:conc#560 TYPE CONCATENATE PAR 0-4427 XREFS 29897 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-5164 {}} {259 0 0-5166 {}}} SUCCS {{259 0 0-5168 {}}} CYCLES {}}
+set a(0-5168) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#193 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29898 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.7263269020708271} PREDS {{146 0 0-4451 {}} {258 0 0-5162 {}} {259 0 0-5167 {}}} SUCCS {{259 0 0-5169 {}}} CYCLES {}}
+set a(0-5169) {NAME ACC1:slc#58 TYPE READSLICE PAR 0-4427 XREFS 29899 LOC {1 0.40398894999999996 1 0.581623025 1 0.581623025 1 0.7263269499999999} PREDS {{146 0 0-4451 {}} {259 0 0-5168 {}}} SUCCS {{259 0 0-5170 {}}} CYCLES {}}
+set a(0-5170) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#200 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29900 LOC {1 0.43123487499999996 1 0.581623025 1 0.581623025 1 0.6291791520708271 1 0.773883077070827} PREDS {{146 0 0-4451 {}} {258 0 0-5159 {}} {259 0 0-5169 {}}} SUCCS {{258 0 0-5190 {}}} CYCLES {}}
+set a(0-5171) {NAME ACC1-3:slc(acc.idiv)#13 TYPE READSLICE PAR 0-4427 XREFS 29901 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-5172 {}}} CYCLES {}}
+set a(0-5172) {NAME ACC1-3:exs#6 TYPE SIGNEXTEND PAR 0-4427 XREFS 29902 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5171 {}}} SUCCS {{259 0 0-5173 {}}} CYCLES {}}
+set a(0-5173) {NAME ACC1:conc#557 TYPE CONCATENATE PAR 0-4427 XREFS 29903 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5172 {}}} SUCCS {{258 0 0-5178 {}}} CYCLES {}}
+set a(0-5174) {NAME ACC1-3:slc(acc.idiv)#23 TYPE READSLICE PAR 0-4427 XREFS 29904 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-5175 {}}} CYCLES {}}
+set a(0-5175) {NAME ACC1-3:exs#11 TYPE SIGNEXTEND PAR 0-4427 XREFS 29905 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5174 {}}} SUCCS {{258 0 0-5177 {}}} CYCLES {}}
+set a(0-5176) {NAME ACC1-3:slc(acc.imod#2)#11 TYPE READSLICE PAR 0-4427 XREFS 29906 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4743 {}}} SUCCS {{259 0 0-5177 {}}} CYCLES {}}
+set a(0-5177) {NAME ACC1:conc#558 TYPE CONCATENATE PAR 0-4427 XREFS 29907 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-5175 {}} {259 0 0-5176 {}}} SUCCS {{259 0 0-5178 {}}} CYCLES {}}
+set a(0-5178) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#192 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29908 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.7263269020708271} PREDS {{146 0 0-4451 {}} {258 0 0-5173 {}} {259 0 0-5177 {}}} SUCCS {{259 0 0-5179 {}}} CYCLES {}}
+set a(0-5179) {NAME ACC1:slc#57 TYPE READSLICE PAR 0-4427 XREFS 29909 LOC {1 0.40398894999999996 1 0.581623025 1 0.581623025 1 0.7263269499999999} PREDS {{146 0 0-4451 {}} {259 0 0-5178 {}}} SUCCS {{258 0 0-5189 {}}} CYCLES {}}
+set a(0-5180) {NAME ACC1-3:slc(acc.idiv)#19 TYPE READSLICE PAR 0-4427 XREFS 29910 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-5181 {}}} CYCLES {}}
+set a(0-5181) {NAME ACC1-3:exs#9 TYPE SIGNEXTEND PAR 0-4427 XREFS 29911 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5180 {}}} SUCCS {{259 0 0-5182 {}}} CYCLES {}}
+set a(0-5182) {NAME ACC1:conc#555 TYPE CONCATENATE PAR 0-4427 XREFS 29912 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5181 {}}} SUCCS {{258 0 0-5187 {}}} CYCLES {}}
+set a(0-5183) {NAME ACC1-3:slc(acc.idiv)#21 TYPE READSLICE PAR 0-4427 XREFS 29913 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4685 {}}} SUCCS {{259 0 0-5184 {}}} CYCLES {}}
+set a(0-5184) {NAME ACC1-3:exs#10 TYPE SIGNEXTEND PAR 0-4427 XREFS 29914 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {259 0 0-5183 {}}} SUCCS {{258 0 0-5186 {}}} CYCLES {}}
+set a(0-5185) {NAME ACC1-3:slc(ACC1:acc#107.psp)#9 TYPE READSLICE PAR 0-4427 XREFS 29915 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-4725 {}}} SUCCS {{259 0 0-5186 {}}} CYCLES {}}
+set a(0-5186) {NAME ACC1:conc#556 TYPE CONCATENATE PAR 0-4427 XREFS 29916 LOC {1 0.267931 1 0.53406685 1 0.53406685 1 0.6787707749999999} PREDS {{146 0 0-4451 {}} {258 0 0-5184 {}} {259 0 0-5185 {}}} SUCCS {{259 0 0-5187 {}}} CYCLES {}}
+set a(0-5187) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#191 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29917 LOC {1 0.267931 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.7263269020708271} PREDS {{146 0 0-4451 {}} {258 0 0-5182 {}} {259 0 0-5186 {}}} SUCCS {{259 0 0-5188 {}}} CYCLES {}}
+set a(0-5188) {NAME ACC1:slc#56 TYPE READSLICE PAR 0-4427 XREFS 29918 LOC {1 0.315487175 1 0.581623025 1 0.581623025 1 0.7263269499999999} PREDS {{146 0 0-4451 {}} {259 0 0-5187 {}}} SUCCS {{259 0 0-5189 {}}} CYCLES {}}
+set a(0-5189) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#199 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29919 LOC {1 0.40398894999999996 1 0.581623025 1 0.581623025 1 0.6291791520708271 1 0.773883077070827} PREDS {{146 0 0-4451 {}} {258 0 0-5179 {}} {259 0 0-5188 {}}} SUCCS {{259 0 0-5190 {}}} CYCLES {}}
+set a(0-5190) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#204 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-4427 XREFS 29920 LOC {1 0.47879105 1 0.6291791999999999 1 0.6291791999999999 1 0.6825262201789504 1 0.8272301451789505} PREDS {{146 0 0-4451 {}} {258 0 0-5170 {}} {259 0 0-5189 {}}} SUCCS {{259 0 0-5191 {}}} CYCLES {}}
+set a(0-5191) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME ACC1:acc#207 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 29921 LOC {1 0.532138125 1 0.682526275 1 0.682526275 1 0.7257279984103023 1 0.8704319234103023} PREDS {{146 0 0-4451 {}} {258 0 0-5147 {}} {259 0 0-5190 {}}} SUCCS {{259 0 0-5192 {}}} CYCLES {}}
+set a(0-5192) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#210 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-4427 XREFS 29922 LOC {1 0.5753399 1 0.72572805 1 0.72572805 1 0.7781125027684257 1 0.9228164277684257} PREDS {{146 0 0-4451 {}} {258 0 0-5142 {}} {259 0 0-5191 {}}} SUCCS {{259 0 0-5193 {}}} CYCLES {}}
+set a(0-5193) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,0,10) AREA_SCORE 10.25 QUANTITY 5 NAME ACC1:acc#212 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-4427 XREFS 29923 LOC {1 0.6277244 1 0.77811255 1 0.77811255 1 0.85529603186502 1 0.99999995686502} PREDS {{146 0 0-4451 {}} {258 0 0-5136 {}} {259 0 0-5192 {}}} SUCCS {{259 0 0-5194 {}}} CYCLES {}}
+set a(0-5194) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,13) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#214 TYPE ACCU DELAY {1.04 ns} LIBRARY_DELAY {1.04 ns} PAR 0-4427 XREFS 29924 LOC {1 0.8413077499999999 1 0.8552960749999999 1 0.8552960749999999 1 0.9205117063734283 2 0.09500765637342837} PREDS {{146 0 0-4451 {}} {258 0 0-5130 {}} {259 0 0-5193 {}}} SUCCS {{259 0 0-5195 {}}} CYCLES {}}
+set a(0-5195) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME ACC1-3:acc#122 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-4427 XREFS 29925 LOC {1 0.9065234249999999 1 0.92051175 1 0.92051175 1 0.9999999534997777 2 0.17449590349977767} PREDS {{146 0 0-4451 {}} {258 0 0-4983 {}} {259 0 0-5194 {}}} SUCCS {{259 0 0-5196 {}}} CYCLES {}}
+set a(0-5196) {NAME ACC1:exs#749 TYPE SIGNEXTEND PAR 0-4427 XREFS 29926 LOC {1 0.986011675 1 1.0 1 1.0 2 0.17449594999999998} PREDS {{146 0 0-4451 {}} {259 0 0-5195 {}}} SUCCS {{258 0 0-5547 {}}} CYCLES {}}
+set a(0-5197) {NAME ACC1-3:slc(acc#10.psp)#61 TYPE READSLICE PAR 0-4427 XREFS 29927 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8410234999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5200 {}}} CYCLES {}}
+set a(0-5198) {NAME ACC1-3:slc(acc#10.psp)#62 TYPE READSLICE PAR 0-4427 XREFS 29928 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8410234999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5200 {}}} CYCLES {}}
+set a(0-5199) {NAME ACC1-3:slc(acc#10.psp)#49 TYPE READSLICE PAR 0-4427 XREFS 29929 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.8410234999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5200 {}}} CYCLES {}}
+set a(0-5200) {NAME ACC1-3:conc#281 TYPE CONCATENATE PAR 0-4427 XREFS 29930 LOC {1 0.14655495 1 0.8410234999999999 1 0.8410234999999999 1 0.8410234999999999} PREDS {{146 0 0-4451 {}} {258 0 0-5198 {}} {258 0 0-5197 {}} {259 0 0-5199 {}}} SUCCS {{258 0 0-5280 {}}} CYCLES {}}
+set a(0-5201) {NAME ACC1-3:slc(acc#10.psp)#29 TYPE READSLICE PAR 0-4427 XREFS 29931 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.512853025} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5202 {}}} CYCLES {}}
+set a(0-5202) {NAME ACC1:conc#580 TYPE CONCATENATE PAR 0-4427 XREFS 29932 LOC {1 0.14655495 1 0.512853025 1 0.512853025 1 0.512853025} PREDS {{146 0 0-4451 {}} {259 0 0-5201 {}}} SUCCS {{259 0 0-5203 {}}} CYCLES {}}
+set a(0-5203) {NAME ACC1:conc#581 TYPE CONCATENATE PAR 0-4427 XREFS 29933 LOC {1 0.14655495 1 0.512853025 1 0.512853025 1 0.512853025} PREDS {{146 0 0-4451 {}} {259 0 0-5202 {}}} SUCCS {{258 0 0-5207 {}}} CYCLES {}}
+set a(0-5204) {NAME ACC1-3:slc(ACC1:acc#113.psp)#10 TYPE READSLICE PAR 0-4427 XREFS 29934 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.512853025} PREDS {{146 0 0-4451 {}} {258 0 0-4872 {}}} SUCCS {{258 0 0-5206 {}}} CYCLES {}}
+set a(0-5205) {NAME ACC1-3:slc(acc#10.psp)#30 TYPE READSLICE PAR 0-4427 XREFS 29935 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.512853025} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5206 {}}} CYCLES {}}
+set a(0-5206) {NAME ACC1:conc#582 TYPE CONCATENATE PAR 0-4427 XREFS 29936 LOC {1 0.267931 1 0.512853025 1 0.512853025 1 0.512853025} PREDS {{146 0 0-4451 {}} {258 0 0-5204 {}} {259 0 0-5205 {}}} SUCCS {{259 0 0-5207 {}}} CYCLES {}}
+set a(0-5207) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#242 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-4427 XREFS 29937 LOC {1 0.267931 1 0.512853025 1 0.512853025 1 0.5504736020241716 1 0.5504736020241716} PREDS {{146 0 0-4451 {}} {258 0 0-5203 {}} {259 0 0-5206 {}}} SUCCS {{259 0 0-5208 {}}} CYCLES {}}
+set a(0-5208) {NAME ACC1:slc#68 TYPE READSLICE PAR 0-4427 XREFS 29938 LOC {1 0.305551625 1 0.5504736499999999 1 0.5504736499999999 1 0.5504736499999999} PREDS {{146 0 0-4451 {}} {259 0 0-5207 {}}} SUCCS {{258 0 0-5210 {}}} CYCLES {}}
+set a(0-5209) {NAME ACC1-3:slc(ACC1:acc#120.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 29939 LOC {1 0.32918685 1 0.479575 1 0.479575 1 0.5504736499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4883 {}}} SUCCS {{259 0 0-5210 {}}} CYCLES {}}
+set a(0-5210) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#251 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-4427 XREFS 29940 LOC {1 0.32918685 1 0.5504736499999999 1 0.5504736499999999 1 0.5880942270241716 1 0.5880942270241716} PREDS {{146 0 0-4451 {}} {258 0 0-5208 {}} {259 0 0-5209 {}}} SUCCS {{258 0 0-5222 {}}} CYCLES {}}
+set a(0-5211) {NAME ACC1-3:slc(acc#10.psp)#31 TYPE READSLICE PAR 0-4427 XREFS 29941 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.56084835} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5213 {}}} CYCLES {}}
+set a(0-5212) {NAME ACC1-3:slc(acc#10.psp)#32 TYPE READSLICE PAR 0-4427 XREFS 29942 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.56084835} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5213 {}}} CYCLES {}}
+set a(0-5213) {NAME ACC1-3:conc#282 TYPE CONCATENATE PAR 0-4427 XREFS 29943 LOC {1 0.14655495 1 0.56084835 1 0.56084835 1 0.56084835} PREDS {{146 0 0-4451 {}} {258 0 0-5211 {}} {259 0 0-5212 {}}} SUCCS {{259 0 0-5214 {}}} CYCLES {}}
+set a(0-5214) {NAME ACC1:conc#583 TYPE CONCATENATE PAR 0-4427 XREFS 29944 LOC {1 0.14655495 1 0.56084835 1 0.56084835 1 0.56084835} PREDS {{146 0 0-4451 {}} {259 0 0-5213 {}}} SUCCS {{258 0 0-5220 {}}} CYCLES {}}
+set a(0-5215) {NAME ACC1-3:slc(ACC1:acc#113.psp)#11 TYPE READSLICE PAR 0-4427 XREFS 29945 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.56084835} PREDS {{146 0 0-4451 {}} {258 0 0-4872 {}}} SUCCS {{258 0 0-5217 {}}} CYCLES {}}
+set a(0-5216) {NAME ACC1-3:slc(acc#10.psp)#33 TYPE READSLICE PAR 0-4427 XREFS 29946 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.56084835} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5217 {}}} CYCLES {}}
+set a(0-5217) {NAME ACC1-3:conc#283 TYPE CONCATENATE PAR 0-4427 XREFS 29947 LOC {1 0.267931 1 0.56084835 1 0.56084835 1 0.56084835} PREDS {{146 0 0-4451 {}} {258 0 0-5215 {}} {259 0 0-5216 {}}} SUCCS {{258 0 0-5219 {}}} CYCLES {}}
+set a(0-5218) {NAME ACC1-3:slc(ACC1:acc#113.psp)#8 TYPE READSLICE PAR 0-4427 XREFS 29948 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.56084835} PREDS {{146 0 0-4451 {}} {258 0 0-4872 {}}} SUCCS {{259 0 0-5219 {}}} CYCLES {}}
+set a(0-5219) {NAME ACC1:conc#584 TYPE CONCATENATE PAR 0-4427 XREFS 29949 LOC {1 0.267931 1 0.56084835 1 0.56084835 1 0.56084835} PREDS {{146 0 0-4451 {}} {258 0 0-5217 {}} {259 0 0-5218 {}}} SUCCS {{259 0 0-5220 {}}} CYCLES {}}
+set a(0-5220) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#243 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 29950 LOC {1 0.267931 1 0.56084835 1 0.56084835 1 0.5880942270708271 1 0.5880942270708271} PREDS {{146 0 0-4451 {}} {258 0 0-5214 {}} {259 0 0-5219 {}}} SUCCS {{259 0 0-5221 {}}} CYCLES {}}
+set a(0-5221) {NAME ACC1:slc#69 TYPE READSLICE PAR 0-4427 XREFS 29951 LOC {1 0.295176925 1 0.588094275 1 0.588094275 1 0.588094275} PREDS {{146 0 0-4451 {}} {259 0 0-5220 {}}} SUCCS {{259 0 0-5222 {}}} CYCLES {}}
+set a(0-5222) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#256 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 29952 LOC {1 0.366807475 1 0.588094275 1 0.588094275 1 0.6312861701789505 1 0.6312861701789505} PREDS {{146 0 0-4451 {}} {258 0 0-5210 {}} {259 0 0-5221 {}}} SUCCS {{258 0 0-5234 {}}} CYCLES {}}
+set a(0-5223) {NAME ACC1-3:slc(acc#10.psp)#34 TYPE READSLICE PAR 0-4427 XREFS 29953 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.5982493999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5227 {}}} CYCLES {}}
+set a(0-5224) {NAME ACC1-3:slc(acc#10.psp)#35 TYPE READSLICE PAR 0-4427 XREFS 29954 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.5982493999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5227 {}}} CYCLES {}}
+set a(0-5225) {NAME ACC1-3:slc(acc.idiv#2)#31 TYPE READSLICE PAR 0-4427 XREFS 29955 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.5982493999999999} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5226 {}}} CYCLES {}}
+set a(0-5226) {NAME ACC1-3:exs#51 TYPE SIGNEXTEND PAR 0-4427 XREFS 29956 LOC {1 0.14655495 1 0.5982493999999999 1 0.5982493999999999 1 0.5982493999999999} PREDS {{146 0 0-4451 {}} {259 0 0-5225 {}}} SUCCS {{259 0 0-5227 {}}} CYCLES {}}
+set a(0-5227) {NAME ACC1-3:conc#284 TYPE CONCATENATE PAR 0-4427 XREFS 29957 LOC {1 0.14655495 1 0.5982493999999999 1 0.5982493999999999 1 0.5982493999999999} PREDS {{146 0 0-4451 {}} {258 0 0-5224 {}} {258 0 0-5223 {}} {259 0 0-5226 {}}} SUCCS {{258 0 0-5233 {}}} CYCLES {}}
+set a(0-5228) {NAME ACC1-3:slc(acc.idiv#2)#33 TYPE READSLICE PAR 0-4427 XREFS 29958 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.55746635} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5229 {}}} CYCLES {}}
+set a(0-5229) {NAME ACC1-3:exs#52 TYPE SIGNEXTEND PAR 0-4427 XREFS 29959 LOC {1 0.14655495 1 0.55746635 1 0.55746635 1 0.55746635} PREDS {{146 0 0-4451 {}} {259 0 0-5228 {}}} SUCCS {{258 0 0-5232 {}}} CYCLES {}}
+set a(0-5230) {NAME ACC1-3:slc(acc.idiv#2)#35 TYPE READSLICE PAR 0-4427 XREFS 29960 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.55746635} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5231 {}}} CYCLES {}}
+set a(0-5231) {NAME ACC1-3:exs#53 TYPE SIGNEXTEND PAR 0-4427 XREFS 29961 LOC {1 0.14655495 1 0.55746635 1 0.55746635 1 0.55746635} PREDS {{146 0 0-4451 {}} {259 0 0-5230 {}}} SUCCS {{259 0 0-5232 {}}} CYCLES {}}
+set a(0-5232) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#250 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29962 LOC {1 0.14655495 1 0.55746635 1 0.55746635 1 0.5982493600894753 1 0.5982493600894753} PREDS {{146 0 0-4451 {}} {258 0 0-5229 {}} {259 0 0-5231 {}}} SUCCS {{259 0 0-5233 {}}} CYCLES {}}
+set a(0-5233) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#255 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-4427 XREFS 29963 LOC {1 0.187338 1 0.5982493999999999 1 0.5982493999999999 1 0.6312861701789504 1 0.6312861701789504} PREDS {{146 0 0-4451 {}} {258 0 0-5227 {}} {259 0 0-5232 {}}} SUCCS {{259 0 0-5234 {}}} CYCLES {}}
+set a(0-5234) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#259 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 29964 LOC {1 0.409999425 1 0.631286225 1 0.631286225 1 0.669575684496936 1 0.669575684496936} PREDS {{146 0 0-4451 {}} {258 0 0-5222 {}} {259 0 0-5233 {}}} SUCCS {{258 0 0-5240 {}}} CYCLES {}}
+set a(0-5235) {NAME ACC1-3:slc(acc#10.psp)#54 TYPE READSLICE PAR 0-4427 XREFS 29965 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.669575725} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5239 {}}} CYCLES {}}
+set a(0-5236) {NAME ACC1-3:slc(acc#10.psp)#55 TYPE READSLICE PAR 0-4427 XREFS 29966 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.669575725} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5239 {}}} CYCLES {}}
+set a(0-5237) {NAME ACC1-3:slc(acc#10.psp)#56 TYPE READSLICE PAR 0-4427 XREFS 29967 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.669575725} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5239 {}}} CYCLES {}}
+set a(0-5238) {NAME ACC1-3:slc(acc#10.psp)#47 TYPE READSLICE PAR 0-4427 XREFS 29968 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.669575725} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5239 {}}} CYCLES {}}
+set a(0-5239) {NAME ACC1-3:conc#279 TYPE CONCATENATE PAR 0-4427 XREFS 29969 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.669575725} PREDS {{146 0 0-4451 {}} {258 0 0-5237 {}} {258 0 0-5236 {}} {258 0 0-5235 {}} {259 0 0-5238 {}}} SUCCS {{259 0 0-5240 {}}} CYCLES {}}
+set a(0-5240) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#262 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-4427 XREFS 29970 LOC {1 0.448288925 1 0.669575725 1 0.669575725 1 0.7174547879329679 1 0.7174547879329679} PREDS {{146 0 0-4451 {}} {258 0 0-5234 {}} {259 0 0-5239 {}}} SUCCS {{258 0 0-5271 {}}} CYCLES {}}
+set a(0-5241) {NAME ACC1-3:slc(acc#10.psp)#17 TYPE READSLICE PAR 0-4427 XREFS 29971 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.669575725} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5244 {}}} CYCLES {}}
+set a(0-5242) {NAME ACC1-3:slc(acc.idiv#2)#25 TYPE READSLICE PAR 0-4427 XREFS 29972 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.669575725} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5243 {}}} CYCLES {}}
+set a(0-5243) {NAME ACC1-3:exs#48 TYPE SIGNEXTEND PAR 0-4427 XREFS 29973 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.669575725} PREDS {{146 0 0-4451 {}} {259 0 0-5242 {}}} SUCCS {{259 0 0-5244 {}}} CYCLES {}}
+set a(0-5244) {NAME ACC1-3:conc#254 TYPE CONCATENATE PAR 0-4427 XREFS 29974 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.669575725} PREDS {{146 0 0-4451 {}} {258 0 0-5241 {}} {259 0 0-5243 {}}} SUCCS {{259 0 0-5245 {}}} CYCLES {}}
+set a(0-5245) {NAME ACC1-3:exs#544 TYPE SIGNEXTEND PAR 0-4427 XREFS 29975 LOC {1 0.14655495 1 0.669575725 1 0.669575725 1 0.669575725} PREDS {{146 0 0-4451 {}} {259 0 0-5244 {}}} SUCCS {{258 0 0-5270 {}}} CYCLES {}}
+set a(0-5246) {NAME ACC1-3:slc(acc#10.psp)#52 TYPE READSLICE PAR 0-4427 XREFS 29976 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.631286225} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5249 {}}} CYCLES {}}
+set a(0-5247) {NAME ACC1-3:slc(acc#10.psp)#53 TYPE READSLICE PAR 0-4427 XREFS 29977 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.631286225} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5249 {}}} CYCLES {}}
+set a(0-5248) {NAME ACC1-3:slc(acc#10.psp)#46 TYPE READSLICE PAR 0-4427 XREFS 29978 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.631286225} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5249 {}}} CYCLES {}}
+set a(0-5249) {NAME ACC1-3:conc#278 TYPE CONCATENATE PAR 0-4427 XREFS 29979 LOC {1 0.14655495 1 0.631286225 1 0.631286225 1 0.631286225} PREDS {{146 0 0-4451 {}} {258 0 0-5247 {}} {258 0 0-5246 {}} {259 0 0-5248 {}}} SUCCS {{258 0 0-5269 {}}} CYCLES {}}
+set a(0-5250) {NAME ACC1-3:slc(acc.idiv#2)#9 TYPE READSLICE PAR 0-4427 XREFS 29980 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.542947} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5251 {}}} CYCLES {}}
+set a(0-5251) {NAME ACC1-3:exs#40 TYPE SIGNEXTEND PAR 0-4427 XREFS 29981 LOC {1 0.14655495 1 0.542947 1 0.542947 1 0.542947} PREDS {{146 0 0-4451 {}} {259 0 0-5250 {}}} SUCCS {{258 0 0-5254 {}}} CYCLES {}}
+set a(0-5252) {NAME ACC1-3:slc(acc.idiv#2)#11 TYPE READSLICE PAR 0-4427 XREFS 29982 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.542947} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5253 {}}} CYCLES {}}
+set a(0-5253) {NAME ACC1-3:exs#41 TYPE SIGNEXTEND PAR 0-4427 XREFS 29983 LOC {1 0.14655495 1 0.542947 1 0.542947 1 0.542947} PREDS {{146 0 0-4451 {}} {259 0 0-5252 {}}} SUCCS {{259 0 0-5254 {}}} CYCLES {}}
+set a(0-5254) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#249 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 29984 LOC {1 0.14655495 1 0.542947 1 0.542947 1 0.5837300100894752 1 0.5837300100894752} PREDS {{146 0 0-4451 {}} {258 0 0-5251 {}} {259 0 0-5253 {}}} SUCCS {{258 0 0-5268 {}}} CYCLES {}}
+set a(0-5255) {NAME ACC1-3:slc(acc.idiv#2)#1 TYPE READSLICE PAR 0-4427 XREFS 29985 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.536173875} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5256 {}}} CYCLES {}}
+set a(0-5256) {NAME ACC1-3:exs#36 TYPE SIGNEXTEND PAR 0-4427 XREFS 29986 LOC {1 0.14655495 1 0.536173875 1 0.536173875 1 0.536173875} PREDS {{146 0 0-4451 {}} {259 0 0-5255 {}}} SUCCS {{259 0 0-5257 {}}} CYCLES {}}
+set a(0-5257) {NAME ACC1:conc#593 TYPE CONCATENATE PAR 0-4427 XREFS 29987 LOC {1 0.14655495 1 0.536173875 1 0.536173875 1 0.536173875} PREDS {{146 0 0-4451 {}} {259 0 0-5256 {}}} SUCCS {{258 0 0-5266 {}}} CYCLES {}}
+set a(0-5258) {NAME ACC1-3:slc(acc.idiv#2)#3 TYPE READSLICE PAR 0-4427 XREFS 29988 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.536173875} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5259 {}}} CYCLES {}}
+set a(0-5259) {NAME ACC1-3:exs#37 TYPE SIGNEXTEND PAR 0-4427 XREFS 29989 LOC {1 0.14655495 1 0.536173875 1 0.536173875 1 0.536173875} PREDS {{146 0 0-4451 {}} {259 0 0-5258 {}}} SUCCS {{258 0 0-5265 {}}} CYCLES {}}
+set a(0-5260) {NAME ACC1-3:slc(acc.idiv#2)#45 TYPE READSLICE PAR 0-4427 XREFS 29990 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.536173875} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5264 {}}} CYCLES {}}
+set a(0-5261) {NAME ACC1-3:slc(acc.imod#11)#1 TYPE READSLICE PAR 0-4427 XREFS 29991 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.536173875} PREDS {{146 0 0-4451 {}} {258 0 0-4899 {}}} SUCCS {{259 0 0-5262 {}}} CYCLES {}}
+set a(0-5262) {NAME ACC1-3:not#92 TYPE NOT PAR 0-4427 XREFS 29992 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.536173875} PREDS {{146 0 0-4451 {}} {259 0 0-5261 {}}} SUCCS {{258 0 0-5264 {}}} CYCLES {}}
+set a(0-5263) {NAME ACC1-3:slc(acc.imod#11)#2 TYPE READSLICE PAR 0-4427 XREFS 29993 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.536173875} PREDS {{146 0 0-4451 {}} {258 0 0-4899 {}}} SUCCS {{259 0 0-5264 {}}} CYCLES {}}
+set a(0-5264) {NAME ACC1-3:and#5 TYPE AND PAR 0-4427 XREFS 29994 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.536173875} PREDS {{146 0 0-4451 {}} {258 0 0-5262 {}} {258 0 0-5260 {}} {259 0 0-5263 {}}} SUCCS {{259 0 0-5265 {}}} CYCLES {}}
+set a(0-5265) {NAME ACC1:conc#594 TYPE CONCATENATE PAR 0-4427 XREFS 29995 LOC {1 0.3836787 1 0.536173875 1 0.536173875 1 0.536173875} PREDS {{146 0 0-4451 {}} {258 0 0-5259 {}} {259 0 0-5264 {}}} SUCCS {{259 0 0-5266 {}}} CYCLES {}}
+set a(0-5266) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#248 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29996 LOC {1 0.3836787 1 0.536173875 1 0.536173875 1 0.5837300020708271 1 0.5837300020708271} PREDS {{146 0 0-4451 {}} {258 0 0-5257 {}} {259 0 0-5265 {}}} SUCCS {{259 0 0-5267 {}}} CYCLES {}}
+set a(0-5267) {NAME ACC1:slc#74 TYPE READSLICE PAR 0-4427 XREFS 29997 LOC {1 0.43123487499999996 1 0.58373005 1 0.58373005 1 0.58373005} PREDS {{146 0 0-4451 {}} {259 0 0-5266 {}}} SUCCS {{259 0 0-5268 {}}} CYCLES {}}
+set a(0-5268) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#254 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 29998 LOC {1 0.43123487499999996 1 0.58373005 1 0.58373005 1 0.6312861770708271 1 0.6312861770708271} PREDS {{146 0 0-4451 {}} {258 0 0-5254 {}} {259 0 0-5267 {}}} SUCCS {{259 0 0-5269 {}}} CYCLES {}}
+set a(0-5269) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#258 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 29999 LOC {1 0.47879105 1 0.631286225 1 0.631286225 1 0.669575684496936 1 0.669575684496936} PREDS {{146 0 0-4451 {}} {258 0 0-5249 {}} {259 0 0-5268 {}}} SUCCS {{259 0 0-5270 {}}} CYCLES {}}
+set a(0-5270) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#261 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-4427 XREFS 30000 LOC {1 0.51708055 1 0.669575725 1 0.669575725 1 0.7174547879329679 1 0.7174547879329679} PREDS {{146 0 0-4451 {}} {258 0 0-5245 {}} {259 0 0-5269 {}}} SUCCS {{259 0 0-5271 {}}} CYCLES {}}
+set a(0-5271) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#264 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-4427 XREFS 30001 LOC {1 0.564959675 1 0.71745485 1 0.71745485 1 0.7698393027684257 1 0.7698393027684257} PREDS {{146 0 0-4451 {}} {258 0 0-5240 {}} {259 0 0-5270 {}}} SUCCS {{258 0 0-5279 {}}} CYCLES {}}
+set a(0-5272) {NAME ACC1-3:slc(acc#10.psp)#66 TYPE READSLICE PAR 0-4427 XREFS 30002 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7698393499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5278 {}}} CYCLES {}}
+set a(0-5273) {NAME ACC1-3:slc(acc#10.psp)#67 TYPE READSLICE PAR 0-4427 XREFS 30003 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7698393499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5278 {}}} CYCLES {}}
+set a(0-5274) {NAME ACC1-3:slc(acc#10.psp)#68 TYPE READSLICE PAR 0-4427 XREFS 30004 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7698393499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5278 {}}} CYCLES {}}
+set a(0-5275) {NAME ACC1-3:slc(acc#10.psp)#51 TYPE READSLICE PAR 0-4427 XREFS 30005 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7698393499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5278 {}}} CYCLES {}}
+set a(0-5276) {NAME ACC1-3:slc(acc.idiv#2)#27 TYPE READSLICE PAR 0-4427 XREFS 30006 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.7698393499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5277 {}}} CYCLES {}}
+set a(0-5277) {NAME ACC1-3:exs#49 TYPE SIGNEXTEND PAR 0-4427 XREFS 30007 LOC {1 0.14655495 1 0.7698393499999999 1 0.7698393499999999 1 0.7698393499999999} PREDS {{146 0 0-4451 {}} {259 0 0-5276 {}}} SUCCS {{259 0 0-5278 {}}} CYCLES {}}
+set a(0-5278) {NAME ACC1-3:conc#287 TYPE CONCATENATE PAR 0-4427 XREFS 30008 LOC {1 0.14655495 1 0.7698393499999999 1 0.7698393499999999 1 0.7698393499999999} PREDS {{146 0 0-4451 {}} {258 0 0-5275 {}} {258 0 0-5274 {}} {258 0 0-5273 {}} {258 0 0-5272 {}} {259 0 0-5277 {}}} SUCCS {{259 0 0-5279 {}}} CYCLES {}}
+set a(0-5279) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#266 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 30009 LOC {1 0.6173441749999999 1 0.7698393499999999 1 0.7698393499999999 1 0.8410234533364113 1 0.8410234533364113} PREDS {{146 0 0-4451 {}} {258 0 0-5271 {}} {259 0 0-5278 {}}} SUCCS {{259 0 0-5280 {}}} CYCLES {}}
+set a(0-5280) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME ACC1:acc#268 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-4427 XREFS 30010 LOC {1 0.6885283249999999 1 0.8410234999999999 1 0.8410234999999999 1 0.9205117034997776 1 0.9205117034997776} PREDS {{146 0 0-4451 {}} {258 0 0-5200 {}} {259 0 0-5279 {}}} SUCCS {{258 0 0-5492 {}}} CYCLES {}}
+set a(0-5281) {NAME ACC1-1:slc(acc#10.psp)#57 TYPE READSLICE PAR 0-4427 XREFS 30011 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.641712725} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5286 {}}} CYCLES {}}
+set a(0-5282) {NAME ACC1-1:slc(acc#10.psp)#58 TYPE READSLICE PAR 0-4427 XREFS 30012 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.641712725} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5286 {}}} CYCLES {}}
+set a(0-5283) {NAME ACC1-1:slc(acc#10.psp)#59 TYPE READSLICE PAR 0-4427 XREFS 30013 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.641712725} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5286 {}}} CYCLES {}}
+set a(0-5284) {NAME ACC1-1:slc(acc#10.psp)#60 TYPE READSLICE PAR 0-4427 XREFS 30014 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.641712725} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5286 {}}} CYCLES {}}
+set a(0-5285) {NAME ACC1-1:slc(acc#10.psp)#48 TYPE READSLICE PAR 0-4427 XREFS 30015 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.641712725} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5286 {}}} CYCLES {}}
+set a(0-5286) {NAME ACC1-1:conc#280 TYPE CONCATENATE PAR 0-4427 XREFS 30016 LOC {1 0.14655495 1 0.641712725 1 0.641712725 1 0.641712725} PREDS {{146 0 0-4451 {}} {258 0 0-5284 {}} {258 0 0-5283 {}} {258 0 0-5282 {}} {258 0 0-5281 {}} {259 0 0-5285 {}}} SUCCS {{258 0 0-5343 {}}} CYCLES {}}
+set a(0-5287) {NAME ACC1-1:slc(acc#10.psp)#63 TYPE READSLICE PAR 0-4427 XREFS 30017 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5893282249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5292 {}}} CYCLES {}}
+set a(0-5288) {NAME ACC1-1:slc(acc#10.psp)#64 TYPE READSLICE PAR 0-4427 XREFS 30018 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5893282249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5292 {}}} CYCLES {}}
+set a(0-5289) {NAME ACC1-1:slc(acc#10.psp)#50 TYPE READSLICE PAR 0-4427 XREFS 30019 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5893282249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5292 {}}} CYCLES {}}
+set a(0-5290) {NAME ACC1-1:slc(acc#10.psp)#65 TYPE READSLICE PAR 0-4427 XREFS 30020 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5893282249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5291 {}}} CYCLES {}}
+set a(0-5291) {NAME ACC1-1:exs#543 TYPE SIGNEXTEND PAR 0-4427 XREFS 30021 LOC {1 0.14655495 1 0.5893282249999999 1 0.5893282249999999 1 0.5893282249999999} PREDS {{146 0 0-4451 {}} {259 0 0-5290 {}}} SUCCS {{259 0 0-5292 {}}} CYCLES {}}
+set a(0-5292) {NAME ACC1-1:conc#285 TYPE CONCATENATE PAR 0-4427 XREFS 30022 LOC {1 0.14655495 1 0.5893282249999999 1 0.5893282249999999 1 0.5893282249999999} PREDS {{146 0 0-4451 {}} {258 0 0-5289 {}} {258 0 0-5288 {}} {258 0 0-5287 {}} {259 0 0-5291 {}}} SUCCS {{258 0 0-5342 {}}} CYCLES {}}
+set a(0-5293) {NAME ACC1-1:slc(acc#10.psp)#36 TYPE READSLICE PAR 0-4427 XREFS 30023 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5461264499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5297 {}}} CYCLES {}}
+set a(0-5294) {NAME ACC1-1:slc(acc#10.psp)#37 TYPE READSLICE PAR 0-4427 XREFS 30024 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5461264499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5297 {}}} CYCLES {}}
+set a(0-5295) {NAME ACC1-1:slc(acc.idiv#2)#29 TYPE READSLICE PAR 0-4427 XREFS 30025 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5461264499999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5296 {}}} CYCLES {}}
+set a(0-5296) {NAME ACC1-1:exs#50 TYPE SIGNEXTEND PAR 0-4427 XREFS 30026 LOC {1 0.14655495 1 0.5461264499999999 1 0.5461264499999999 1 0.5461264499999999} PREDS {{146 0 0-4451 {}} {259 0 0-5295 {}}} SUCCS {{259 0 0-5297 {}}} CYCLES {}}
+set a(0-5297) {NAME ACC1-1:conc#289 TYPE CONCATENATE PAR 0-4427 XREFS 30027 LOC {1 0.14655495 1 0.5461264499999999 1 0.5461264499999999 1 0.5461264499999999} PREDS {{146 0 0-4451 {}} {258 0 0-5294 {}} {258 0 0-5293 {}} {259 0 0-5296 {}}} SUCCS {{258 0 0-5341 {}}} CYCLES {}}
+set a(0-5298) {NAME ACC1-1:slc(acc.idiv#2)#5 TYPE READSLICE PAR 0-4427 XREFS 30028 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5299 {}}} CYCLES {}}
+set a(0-5299) {NAME ACC1-1:exs#38 TYPE SIGNEXTEND PAR 0-4427 XREFS 30029 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5298 {}}} SUCCS {{259 0 0-5300 {}}} CYCLES {}}
+set a(0-5300) {NAME ACC1:conc#606 TYPE CONCATENATE PAR 0-4427 XREFS 30030 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5299 {}}} SUCCS {{258 0 0-5308 {}}} CYCLES {}}
+set a(0-5301) {NAME ACC1-1:slc(acc.idiv#2)#7 TYPE READSLICE PAR 0-4427 XREFS 30031 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5302 {}}} CYCLES {}}
+set a(0-5302) {NAME ACC1-1:exs#39 TYPE SIGNEXTEND PAR 0-4427 XREFS 30032 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5301 {}}} SUCCS {{258 0 0-5307 {}}} CYCLES {}}
+set a(0-5303) {NAME ACC1-1:slc(acc.imod#11) TYPE READSLICE PAR 0-4427 XREFS 30033 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-4677 {}}} SUCCS {{258 0 0-5306 {}}} CYCLES {}}
+set a(0-5304) {NAME ACC1-1:slc(acc.idiv#2)#44 TYPE READSLICE PAR 0-4427 XREFS 30034 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5305 {}}} CYCLES {}}
+set a(0-5305) {NAME ACC1-1:not#91 TYPE NOT PAR 0-4427 XREFS 30035 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5304 {}}} SUCCS {{259 0 0-5306 {}}} CYCLES {}}
+set a(0-5306) {NAME ACC1-1:nand#2 TYPE NAND PAR 0-4427 XREFS 30036 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-5303 {}} {259 0 0-5305 {}}} SUCCS {{259 0 0-5307 {}}} CYCLES {}}
+set a(0-5307) {NAME ACC1:conc#607 TYPE CONCATENATE PAR 0-4427 XREFS 30037 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-5302 {}} {259 0 0-5306 {}}} SUCCS {{259 0 0-5308 {}}} CYCLES {}}
+set a(0-5308) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#274 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30038 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.4452231520708272} PREDS {{146 0 0-4451 {}} {258 0 0-5300 {}} {259 0 0-5307 {}}} SUCCS {{259 0 0-5309 {}}} CYCLES {}}
+set a(0-5309) {NAME ACC1:slc#80 TYPE READSLICE PAR 0-4427 XREFS 30039 LOC {1 0.43123487499999996 1 0.4452232 1 0.4452232 1 0.4452232} PREDS {{146 0 0-4451 {}} {259 0 0-5308 {}}} SUCCS {{258 0 0-5320 {}}} CYCLES {}}
+set a(0-5310) {NAME ACC1-1:slc(acc.idiv#2)#15 TYPE READSLICE PAR 0-4427 XREFS 30040 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5311 {}}} CYCLES {}}
+set a(0-5311) {NAME ACC1-1:exs#43 TYPE SIGNEXTEND PAR 0-4427 XREFS 30041 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5310 {}}} SUCCS {{259 0 0-5312 {}}} CYCLES {}}
+set a(0-5312) {NAME ACC1:conc#604 TYPE CONCATENATE PAR 0-4427 XREFS 30042 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5311 {}}} SUCCS {{258 0 0-5318 {}}} CYCLES {}}
+set a(0-5313) {NAME ACC1-1:slc(acc.idiv#2)#17 TYPE READSLICE PAR 0-4427 XREFS 30043 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5314 {}}} CYCLES {}}
+set a(0-5314) {NAME ACC1-1:exs#44 TYPE SIGNEXTEND PAR 0-4427 XREFS 30044 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5313 {}}} SUCCS {{258 0 0-5317 {}}} CYCLES {}}
+set a(0-5315) {NAME ACC1-1:slc(acc.imod#10)#12 TYPE READSLICE PAR 0-4427 XREFS 30045 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-4668 {}}} SUCCS {{259 0 0-5316 {}}} CYCLES {}}
+set a(0-5316) {NAME ACC1-1:not#150 TYPE NOT PAR 0-4427 XREFS 30046 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5315 {}}} SUCCS {{259 0 0-5317 {}}} CYCLES {}}
+set a(0-5317) {NAME ACC1:conc#605 TYPE CONCATENATE PAR 0-4427 XREFS 30047 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-5314 {}} {259 0 0-5316 {}}} SUCCS {{259 0 0-5318 {}}} CYCLES {}}
+set a(0-5318) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#273 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30048 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.4452231520708272} PREDS {{146 0 0-4451 {}} {258 0 0-5312 {}} {259 0 0-5317 {}}} SUCCS {{259 0 0-5319 {}}} CYCLES {}}
+set a(0-5319) {NAME ACC1:slc#79 TYPE READSLICE PAR 0-4427 XREFS 30049 LOC {1 0.40398894999999996 1 0.4452232 1 0.4452232 1 0.4452232} PREDS {{146 0 0-4451 {}} {259 0 0-5318 {}}} SUCCS {{259 0 0-5320 {}}} CYCLES {}}
+set a(0-5320) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#280 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30050 LOC {1 0.43123487499999996 1 0.4452232 1 0.4452232 1 0.49277932707082717 1 0.49277932707082717} PREDS {{146 0 0-4451 {}} {258 0 0-5309 {}} {259 0 0-5319 {}}} SUCCS {{258 0 0-5340 {}}} CYCLES {}}
+set a(0-5321) {NAME ACC1-1:slc(acc.idiv#2)#13 TYPE READSLICE PAR 0-4427 XREFS 30051 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5322 {}}} CYCLES {}}
+set a(0-5322) {NAME ACC1-1:exs#42 TYPE SIGNEXTEND PAR 0-4427 XREFS 30052 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5321 {}}} SUCCS {{259 0 0-5323 {}}} CYCLES {}}
+set a(0-5323) {NAME ACC1:conc#602 TYPE CONCATENATE PAR 0-4427 XREFS 30053 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5322 {}}} SUCCS {{258 0 0-5328 {}}} CYCLES {}}
+set a(0-5324) {NAME ACC1-1:slc(acc.idiv#2)#23 TYPE READSLICE PAR 0-4427 XREFS 30054 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5325 {}}} CYCLES {}}
+set a(0-5325) {NAME ACC1-1:exs#47 TYPE SIGNEXTEND PAR 0-4427 XREFS 30055 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5324 {}}} SUCCS {{258 0 0-5327 {}}} CYCLES {}}
+set a(0-5326) {NAME ACC1-1:slc(acc.imod#10)#11 TYPE READSLICE PAR 0-4427 XREFS 30056 LOC {1 0.356432775 1 0.3704211 1 0.3704211 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-4668 {}}} SUCCS {{259 0 0-5327 {}}} CYCLES {}}
+set a(0-5327) {NAME ACC1:conc#603 TYPE CONCATENATE PAR 0-4427 XREFS 30057 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-5325 {}} {259 0 0-5326 {}}} SUCCS {{259 0 0-5328 {}}} CYCLES {}}
+set a(0-5328) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#272 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30058 LOC {1 0.356432775 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.4452231520708272} PREDS {{146 0 0-4451 {}} {258 0 0-5323 {}} {259 0 0-5327 {}}} SUCCS {{259 0 0-5329 {}}} CYCLES {}}
+set a(0-5329) {NAME ACC1:slc#78 TYPE READSLICE PAR 0-4427 XREFS 30059 LOC {1 0.40398894999999996 1 0.4452232 1 0.4452232 1 0.4452232} PREDS {{146 0 0-4451 {}} {259 0 0-5328 {}}} SUCCS {{258 0 0-5339 {}}} CYCLES {}}
+set a(0-5330) {NAME ACC1-1:slc(acc.idiv#2)#19 TYPE READSLICE PAR 0-4427 XREFS 30060 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5331 {}}} CYCLES {}}
+set a(0-5331) {NAME ACC1-1:exs#45 TYPE SIGNEXTEND PAR 0-4427 XREFS 30061 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5330 {}}} SUCCS {{259 0 0-5332 {}}} CYCLES {}}
+set a(0-5332) {NAME ACC1:conc#600 TYPE CONCATENATE PAR 0-4427 XREFS 30062 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5331 {}}} SUCCS {{258 0 0-5337 {}}} CYCLES {}}
+set a(0-5333) {NAME ACC1-1:slc(acc.idiv#2)#21 TYPE READSLICE PAR 0-4427 XREFS 30063 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5334 {}}} CYCLES {}}
+set a(0-5334) {NAME ACC1-1:exs#46 TYPE SIGNEXTEND PAR 0-4427 XREFS 30064 LOC {1 0.14655495 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {259 0 0-5333 {}}} SUCCS {{258 0 0-5336 {}}} CYCLES {}}
+set a(0-5335) {NAME ACC1-1:slc(ACC1:acc#113.psp)#9 TYPE READSLICE PAR 0-4427 XREFS 30065 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-4650 {}}} SUCCS {{259 0 0-5336 {}}} CYCLES {}}
+set a(0-5336) {NAME ACC1:conc#601 TYPE CONCATENATE PAR 0-4427 XREFS 30066 LOC {1 0.267931 1 0.397667025 1 0.397667025 1 0.397667025} PREDS {{146 0 0-4451 {}} {258 0 0-5334 {}} {259 0 0-5335 {}}} SUCCS {{259 0 0-5337 {}}} CYCLES {}}
+set a(0-5337) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#271 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30067 LOC {1 0.267931 1 0.397667025 1 0.397667025 1 0.4452231520708272 1 0.4452231520708272} PREDS {{146 0 0-4451 {}} {258 0 0-5332 {}} {259 0 0-5336 {}}} SUCCS {{259 0 0-5338 {}}} CYCLES {}}
+set a(0-5338) {NAME ACC1:slc#77 TYPE READSLICE PAR 0-4427 XREFS 30068 LOC {1 0.315487175 1 0.4452232 1 0.4452232 1 0.4452232} PREDS {{146 0 0-4451 {}} {259 0 0-5337 {}}} SUCCS {{259 0 0-5339 {}}} CYCLES {}}
+set a(0-5339) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#279 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30069 LOC {1 0.40398894999999996 1 0.4452232 1 0.4452232 1 0.49277932707082717 1 0.49277932707082717} PREDS {{146 0 0-4451 {}} {258 0 0-5329 {}} {259 0 0-5338 {}}} SUCCS {{259 0 0-5340 {}}} CYCLES {}}
+set a(0-5340) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#284 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-4427 XREFS 30070 LOC {1 0.47879105 1 0.49277937499999996 1 0.49277937499999996 1 0.5461263951789505 1 0.5461263951789505} PREDS {{146 0 0-4451 {}} {258 0 0-5320 {}} {259 0 0-5339 {}}} SUCCS {{259 0 0-5341 {}}} CYCLES {}}
+set a(0-5341) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME ACC1:acc#287 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 30071 LOC {1 0.532138125 1 0.5461264499999999 1 0.5461264499999999 1 0.5893281734103023 1 0.5893281734103023} PREDS {{146 0 0-4451 {}} {258 0 0-5297 {}} {259 0 0-5340 {}}} SUCCS {{259 0 0-5342 {}}} CYCLES {}}
+set a(0-5342) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#290 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-4427 XREFS 30072 LOC {1 0.5753399 1 0.5893282249999999 1 0.5893282249999999 1 0.6417126777684257 1 0.6417126777684257} PREDS {{146 0 0-4451 {}} {258 0 0-5292 {}} {259 0 0-5341 {}}} SUCCS {{259 0 0-5343 {}}} CYCLES {}}
+set a(0-5343) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,0,10) AREA_SCORE 10.25 QUANTITY 5 NAME ACC1:acc#292 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-4427 XREFS 30073 LOC {1 0.6277244 1 0.641712725 1 0.641712725 1 0.71889620686502 1 0.71889620686502} PREDS {{146 0 0-4451 {}} {258 0 0-5286 {}} {259 0 0-5342 {}}} SUCCS {{258 0 0-5415 {}}} CYCLES {}}
+set a(0-5344) {NAME ACC1-1:slc(acc#10.psp)#29 TYPE READSLICE PAR 0-4427 XREFS 30074 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.461909925} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5345 {}}} CYCLES {}}
+set a(0-5345) {NAME ACC1:conc#595 TYPE CONCATENATE PAR 0-4427 XREFS 30075 LOC {1 0.14655495 1 0.461909925 1 0.461909925 1 0.461909925} PREDS {{146 0 0-4451 {}} {259 0 0-5344 {}}} SUCCS {{259 0 0-5346 {}}} CYCLES {}}
+set a(0-5346) {NAME ACC1:conc#596 TYPE CONCATENATE PAR 0-4427 XREFS 30076 LOC {1 0.14655495 1 0.461909925 1 0.461909925 1 0.461909925} PREDS {{146 0 0-4451 {}} {259 0 0-5345 {}}} SUCCS {{258 0 0-5350 {}}} CYCLES {}}
+set a(0-5347) {NAME ACC1-1:slc(ACC1:acc#113.psp)#10 TYPE READSLICE PAR 0-4427 XREFS 30077 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.461909925} PREDS {{146 0 0-4451 {}} {258 0 0-4650 {}}} SUCCS {{258 0 0-5349 {}}} CYCLES {}}
+set a(0-5348) {NAME ACC1-1:slc(acc#10.psp)#30 TYPE READSLICE PAR 0-4427 XREFS 30078 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.461909925} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5349 {}}} CYCLES {}}
+set a(0-5349) {NAME ACC1:conc#597 TYPE CONCATENATE PAR 0-4427 XREFS 30079 LOC {1 0.267931 1 0.461909925 1 0.461909925 1 0.461909925} PREDS {{146 0 0-4451 {}} {258 0 0-5347 {}} {259 0 0-5348 {}}} SUCCS {{259 0 0-5350 {}}} CYCLES {}}
+set a(0-5350) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#269 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-4427 XREFS 30080 LOC {1 0.267931 1 0.461909925 1 0.461909925 1 0.49953050202417165 1 0.49953050202417165} PREDS {{146 0 0-4451 {}} {258 0 0-5346 {}} {259 0 0-5349 {}}} SUCCS {{259 0 0-5351 {}}} CYCLES {}}
+set a(0-5351) {NAME ACC1:slc#75 TYPE READSLICE PAR 0-4427 XREFS 30081 LOC {1 0.305551625 1 0.49953054999999996 1 0.49953054999999996 1 0.49953054999999996} PREDS {{146 0 0-4451 {}} {259 0 0-5350 {}}} SUCCS {{258 0 0-5353 {}}} CYCLES {}}
+set a(0-5352) {NAME ACC1-1:slc(ACC1:acc#120.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 30082 LOC {1 0.32918685 1 0.343175175 1 0.343175175 1 0.49953054999999996} PREDS {{146 0 0-4451 {}} {258 0 0-4661 {}}} SUCCS {{259 0 0-5353 {}}} CYCLES {}}
+set a(0-5353) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,1,2,1,4) AREA_SCORE 4.00 QUANTITY 8 NAME ACC1:acc#278 TYPE ACCU DELAY {0.60 ns} LIBRARY_DELAY {0.60 ns} PAR 0-4427 XREFS 30083 LOC {1 0.32918685 1 0.49953054999999996 1 0.49953054999999996 1 0.5371511270241717 1 0.5371511270241717} PREDS {{146 0 0-4451 {}} {258 0 0-5351 {}} {259 0 0-5352 {}}} SUCCS {{258 0 0-5365 {}}} CYCLES {}}
+set a(0-5354) {NAME ACC1-1:slc(acc#10.psp)#31 TYPE READSLICE PAR 0-4427 XREFS 30084 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.50990525} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5356 {}}} CYCLES {}}
+set a(0-5355) {NAME ACC1-1:slc(acc#10.psp)#32 TYPE READSLICE PAR 0-4427 XREFS 30085 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.50990525} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5356 {}}} CYCLES {}}
+set a(0-5356) {NAME ACC1-1:conc#282 TYPE CONCATENATE PAR 0-4427 XREFS 30086 LOC {1 0.14655495 1 0.50990525 1 0.50990525 1 0.50990525} PREDS {{146 0 0-4451 {}} {258 0 0-5354 {}} {259 0 0-5355 {}}} SUCCS {{259 0 0-5357 {}}} CYCLES {}}
+set a(0-5357) {NAME ACC1:conc#598 TYPE CONCATENATE PAR 0-4427 XREFS 30087 LOC {1 0.14655495 1 0.50990525 1 0.50990525 1 0.50990525} PREDS {{146 0 0-4451 {}} {259 0 0-5356 {}}} SUCCS {{258 0 0-5363 {}}} CYCLES {}}
+set a(0-5358) {NAME ACC1-1:slc(ACC1:acc#113.psp)#11 TYPE READSLICE PAR 0-4427 XREFS 30088 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.50990525} PREDS {{146 0 0-4451 {}} {258 0 0-4650 {}}} SUCCS {{258 0 0-5360 {}}} CYCLES {}}
+set a(0-5359) {NAME ACC1-1:slc(acc#10.psp)#33 TYPE READSLICE PAR 0-4427 XREFS 30089 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.50990525} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5360 {}}} CYCLES {}}
+set a(0-5360) {NAME ACC1-1:conc#283 TYPE CONCATENATE PAR 0-4427 XREFS 30090 LOC {1 0.267931 1 0.50990525 1 0.50990525 1 0.50990525} PREDS {{146 0 0-4451 {}} {258 0 0-5358 {}} {259 0 0-5359 {}}} SUCCS {{258 0 0-5362 {}}} CYCLES {}}
+set a(0-5361) {NAME ACC1-1:slc(ACC1:acc#113.psp)#8 TYPE READSLICE PAR 0-4427 XREFS 30091 LOC {1 0.267931 1 0.281919325 1 0.281919325 1 0.50990525} PREDS {{146 0 0-4451 {}} {258 0 0-4650 {}}} SUCCS {{259 0 0-5362 {}}} CYCLES {}}
+set a(0-5362) {NAME ACC1:conc#599 TYPE CONCATENATE PAR 0-4427 XREFS 30092 LOC {1 0.267931 1 0.50990525 1 0.50990525 1 0.50990525} PREDS {{146 0 0-4451 {}} {258 0 0-5360 {}} {259 0 0-5361 {}}} SUCCS {{259 0 0-5363 {}}} CYCLES {}}
+set a(0-5363) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#270 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 30093 LOC {1 0.267931 1 0.50990525 1 0.50990525 1 0.5371511270708271 1 0.5371511270708271} PREDS {{146 0 0-4451 {}} {258 0 0-5357 {}} {259 0 0-5362 {}}} SUCCS {{259 0 0-5364 {}}} CYCLES {}}
+set a(0-5364) {NAME ACC1:slc#76 TYPE READSLICE PAR 0-4427 XREFS 30094 LOC {1 0.295176925 1 0.537151175 1 0.537151175 1 0.537151175} PREDS {{146 0 0-4451 {}} {259 0 0-5363 {}}} SUCCS {{259 0 0-5365 {}}} CYCLES {}}
+set a(0-5365) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,1,4,1,5) AREA_SCORE 5.00 QUANTITY 8 NAME ACC1:acc#283 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 30095 LOC {1 0.366807475 1 0.537151175 1 0.537151175 1 0.5803430701789505 1 0.5803430701789505} PREDS {{146 0 0-4451 {}} {258 0 0-5353 {}} {259 0 0-5364 {}}} SUCCS {{258 0 0-5377 {}}} CYCLES {}}
+set a(0-5366) {NAME ACC1-1:slc(acc#10.psp)#34 TYPE READSLICE PAR 0-4427 XREFS 30096 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5473063} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5370 {}}} CYCLES {}}
+set a(0-5367) {NAME ACC1-1:slc(acc#10.psp)#35 TYPE READSLICE PAR 0-4427 XREFS 30097 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5473063} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5370 {}}} CYCLES {}}
+set a(0-5368) {NAME ACC1-1:slc(acc.idiv#2)#31 TYPE READSLICE PAR 0-4427 XREFS 30098 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.5473063} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5369 {}}} CYCLES {}}
+set a(0-5369) {NAME ACC1-1:exs#51 TYPE SIGNEXTEND PAR 0-4427 XREFS 30099 LOC {1 0.14655495 1 0.5473063 1 0.5473063 1 0.5473063} PREDS {{146 0 0-4451 {}} {259 0 0-5368 {}}} SUCCS {{259 0 0-5370 {}}} CYCLES {}}
+set a(0-5370) {NAME ACC1-1:conc#284 TYPE CONCATENATE PAR 0-4427 XREFS 30100 LOC {1 0.14655495 1 0.5473063 1 0.5473063 1 0.5473063} PREDS {{146 0 0-4451 {}} {258 0 0-5367 {}} {258 0 0-5366 {}} {259 0 0-5369 {}}} SUCCS {{258 0 0-5376 {}}} CYCLES {}}
+set a(0-5371) {NAME ACC1-1:slc(acc.idiv#2)#33 TYPE READSLICE PAR 0-4427 XREFS 30101 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.50652325} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5372 {}}} CYCLES {}}
+set a(0-5372) {NAME ACC1-1:exs#52 TYPE SIGNEXTEND PAR 0-4427 XREFS 30102 LOC {1 0.14655495 1 0.50652325 1 0.50652325 1 0.50652325} PREDS {{146 0 0-4451 {}} {259 0 0-5371 {}}} SUCCS {{258 0 0-5375 {}}} CYCLES {}}
+set a(0-5373) {NAME ACC1-1:slc(acc.idiv#2)#35 TYPE READSLICE PAR 0-4427 XREFS 30103 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.50652325} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5374 {}}} CYCLES {}}
+set a(0-5374) {NAME ACC1-1:exs#53 TYPE SIGNEXTEND PAR 0-4427 XREFS 30104 LOC {1 0.14655495 1 0.50652325 1 0.50652325 1 0.50652325} PREDS {{146 0 0-4451 {}} {259 0 0-5373 {}}} SUCCS {{259 0 0-5375 {}}} CYCLES {}}
+set a(0-5375) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#277 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 30105 LOC {1 0.14655495 1 0.50652325 1 0.50652325 1 0.5473062600894752 1 0.5473062600894752} PREDS {{146 0 0-4451 {}} {258 0 0-5372 {}} {259 0 0-5374 {}}} SUCCS {{259 0 0-5376 {}}} CYCLES {}}
+set a(0-5376) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#282 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-4427 XREFS 30106 LOC {1 0.187338 1 0.5473063 1 0.5473063 1 0.5803430701789505 1 0.5803430701789505} PREDS {{146 0 0-4451 {}} {258 0 0-5370 {}} {259 0 0-5375 {}}} SUCCS {{259 0 0-5377 {}}} CYCLES {}}
+set a(0-5377) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#286 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 30107 LOC {1 0.409999425 1 0.580343125 1 0.580343125 1 0.618632584496936 1 0.618632584496936} PREDS {{146 0 0-4451 {}} {258 0 0-5365 {}} {259 0 0-5376 {}}} SUCCS {{258 0 0-5383 {}}} CYCLES {}}
+set a(0-5378) {NAME ACC1-1:slc(acc#10.psp)#54 TYPE READSLICE PAR 0-4427 XREFS 30108 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6186326249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5382 {}}} CYCLES {}}
+set a(0-5379) {NAME ACC1-1:slc(acc#10.psp)#55 TYPE READSLICE PAR 0-4427 XREFS 30109 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6186326249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5382 {}}} CYCLES {}}
+set a(0-5380) {NAME ACC1-1:slc(acc#10.psp)#56 TYPE READSLICE PAR 0-4427 XREFS 30110 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6186326249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5382 {}}} CYCLES {}}
+set a(0-5381) {NAME ACC1-1:slc(acc#10.psp)#47 TYPE READSLICE PAR 0-4427 XREFS 30111 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6186326249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5382 {}}} CYCLES {}}
+set a(0-5382) {NAME ACC1-1:conc#279 TYPE CONCATENATE PAR 0-4427 XREFS 30112 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.6186326249999999} PREDS {{146 0 0-4451 {}} {258 0 0-5380 {}} {258 0 0-5379 {}} {258 0 0-5378 {}} {259 0 0-5381 {}}} SUCCS {{259 0 0-5383 {}}} CYCLES {}}
+set a(0-5383) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#289 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-4427 XREFS 30113 LOC {1 0.448288925 1 0.6186326249999999 1 0.6186326249999999 1 0.6665116879329679 1 0.6665116879329679} PREDS {{146 0 0-4451 {}} {258 0 0-5377 {}} {259 0 0-5382 {}}} SUCCS {{258 0 0-5414 {}}} CYCLES {}}
+set a(0-5384) {NAME ACC1-1:slc(acc#10.psp)#17 TYPE READSLICE PAR 0-4427 XREFS 30114 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6186326249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5387 {}}} CYCLES {}}
+set a(0-5385) {NAME ACC1-1:slc(acc.idiv#2)#25 TYPE READSLICE PAR 0-4427 XREFS 30115 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.6186326249999999} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5386 {}}} CYCLES {}}
+set a(0-5386) {NAME ACC1-1:exs#48 TYPE SIGNEXTEND PAR 0-4427 XREFS 30116 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.6186326249999999} PREDS {{146 0 0-4451 {}} {259 0 0-5385 {}}} SUCCS {{259 0 0-5387 {}}} CYCLES {}}
+set a(0-5387) {NAME ACC1-1:conc#254 TYPE CONCATENATE PAR 0-4427 XREFS 30117 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.6186326249999999} PREDS {{146 0 0-4451 {}} {258 0 0-5384 {}} {259 0 0-5386 {}}} SUCCS {{259 0 0-5388 {}}} CYCLES {}}
+set a(0-5388) {NAME ACC1-1:exs#544 TYPE SIGNEXTEND PAR 0-4427 XREFS 30118 LOC {1 0.14655495 1 0.6186326249999999 1 0.6186326249999999 1 0.6186326249999999} PREDS {{146 0 0-4451 {}} {259 0 0-5387 {}}} SUCCS {{258 0 0-5413 {}}} CYCLES {}}
+set a(0-5389) {NAME ACC1-1:slc(acc#10.psp)#52 TYPE READSLICE PAR 0-4427 XREFS 30119 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.580343125} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5392 {}}} CYCLES {}}
+set a(0-5390) {NAME ACC1-1:slc(acc#10.psp)#53 TYPE READSLICE PAR 0-4427 XREFS 30120 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.580343125} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5392 {}}} CYCLES {}}
+set a(0-5391) {NAME ACC1-1:slc(acc#10.psp)#46 TYPE READSLICE PAR 0-4427 XREFS 30121 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.580343125} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5392 {}}} CYCLES {}}
+set a(0-5392) {NAME ACC1-1:conc#278 TYPE CONCATENATE PAR 0-4427 XREFS 30122 LOC {1 0.14655495 1 0.580343125 1 0.580343125 1 0.580343125} PREDS {{146 0 0-4451 {}} {258 0 0-5390 {}} {258 0 0-5389 {}} {259 0 0-5391 {}}} SUCCS {{258 0 0-5412 {}}} CYCLES {}}
+set a(0-5393) {NAME ACC1-1:slc(acc.idiv#2)#9 TYPE READSLICE PAR 0-4427 XREFS 30123 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.4920039} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5394 {}}} CYCLES {}}
+set a(0-5394) {NAME ACC1-1:exs#40 TYPE SIGNEXTEND PAR 0-4427 XREFS 30124 LOC {1 0.14655495 1 0.4920039 1 0.4920039 1 0.4920039} PREDS {{146 0 0-4451 {}} {259 0 0-5393 {}}} SUCCS {{258 0 0-5397 {}}} CYCLES {}}
+set a(0-5395) {NAME ACC1-1:slc(acc.idiv#2)#11 TYPE READSLICE PAR 0-4427 XREFS 30125 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.4920039} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5396 {}}} CYCLES {}}
+set a(0-5396) {NAME ACC1-1:exs#41 TYPE SIGNEXTEND PAR 0-4427 XREFS 30126 LOC {1 0.14655495 1 0.4920039 1 0.4920039 1 0.4920039} PREDS {{146 0 0-4451 {}} {259 0 0-5395 {}}} SUCCS {{259 0 0-5397 {}}} CYCLES {}}
+set a(0-5397) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,3) AREA_SCORE 3.31 QUANTITY 26 NAME ACC1:acc#276 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-4427 XREFS 30127 LOC {1 0.14655495 1 0.4920039 1 0.4920039 1 0.5327869100894752 1 0.5327869100894752} PREDS {{146 0 0-4451 {}} {258 0 0-5394 {}} {259 0 0-5396 {}}} SUCCS {{258 0 0-5411 {}}} CYCLES {}}
+set a(0-5398) {NAME ACC1-1:slc(acc.idiv#2)#1 TYPE READSLICE PAR 0-4427 XREFS 30128 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.485230775} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5399 {}}} CYCLES {}}
+set a(0-5399) {NAME ACC1-1:exs#36 TYPE SIGNEXTEND PAR 0-4427 XREFS 30129 LOC {1 0.14655495 1 0.485230775 1 0.485230775 1 0.485230775} PREDS {{146 0 0-4451 {}} {259 0 0-5398 {}}} SUCCS {{259 0 0-5400 {}}} CYCLES {}}
+set a(0-5400) {NAME ACC1:conc#608 TYPE CONCATENATE PAR 0-4427 XREFS 30130 LOC {1 0.14655495 1 0.485230775 1 0.485230775 1 0.485230775} PREDS {{146 0 0-4451 {}} {259 0 0-5399 {}}} SUCCS {{258 0 0-5409 {}}} CYCLES {}}
+set a(0-5401) {NAME ACC1-1:slc(acc.idiv#2)#3 TYPE READSLICE PAR 0-4427 XREFS 30131 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.485230775} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5402 {}}} CYCLES {}}
+set a(0-5402) {NAME ACC1-1:exs#37 TYPE SIGNEXTEND PAR 0-4427 XREFS 30132 LOC {1 0.14655495 1 0.485230775 1 0.485230775 1 0.485230775} PREDS {{146 0 0-4451 {}} {259 0 0-5401 {}}} SUCCS {{258 0 0-5408 {}}} CYCLES {}}
+set a(0-5403) {NAME ACC1-1:slc(acc.idiv#2)#45 TYPE READSLICE PAR 0-4427 XREFS 30133 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.485230775} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5407 {}}} CYCLES {}}
+set a(0-5404) {NAME ACC1-1:slc(acc.imod#11)#1 TYPE READSLICE PAR 0-4427 XREFS 30134 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.485230775} PREDS {{146 0 0-4451 {}} {258 0 0-4677 {}}} SUCCS {{259 0 0-5405 {}}} CYCLES {}}
+set a(0-5405) {NAME ACC1-1:not#92 TYPE NOT PAR 0-4427 XREFS 30135 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.485230775} PREDS {{146 0 0-4451 {}} {259 0 0-5404 {}}} SUCCS {{258 0 0-5407 {}}} CYCLES {}}
+set a(0-5406) {NAME ACC1-1:slc(acc.imod#11)#2 TYPE READSLICE PAR 0-4427 XREFS 30136 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.485230775} PREDS {{146 0 0-4451 {}} {258 0 0-4677 {}}} SUCCS {{259 0 0-5407 {}}} CYCLES {}}
+set a(0-5407) {NAME ACC1-1:and#5 TYPE AND PAR 0-4427 XREFS 30137 LOC {1 0.3836787 1 0.397667025 1 0.397667025 1 0.485230775} PREDS {{146 0 0-4451 {}} {258 0 0-5405 {}} {258 0 0-5403 {}} {259 0 0-5406 {}}} SUCCS {{259 0 0-5408 {}}} CYCLES {}}
+set a(0-5408) {NAME ACC1:conc#609 TYPE CONCATENATE PAR 0-4427 XREFS 30138 LOC {1 0.3836787 1 0.485230775 1 0.485230775 1 0.485230775} PREDS {{146 0 0-4451 {}} {258 0 0-5402 {}} {259 0 0-5407 {}}} SUCCS {{259 0 0-5409 {}}} CYCLES {}}
+set a(0-5409) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#275 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30139 LOC {1 0.3836787 1 0.485230775 1 0.485230775 1 0.5327869020708271 1 0.5327869020708271} PREDS {{146 0 0-4451 {}} {258 0 0-5400 {}} {259 0 0-5408 {}}} SUCCS {{259 0 0-5410 {}}} CYCLES {}}
+set a(0-5410) {NAME ACC1:slc#81 TYPE READSLICE PAR 0-4427 XREFS 30140 LOC {1 0.43123487499999996 1 0.53278695 1 0.53278695 1 0.53278695} PREDS {{146 0 0-4451 {}} {259 0 0-5409 {}}} SUCCS {{259 0 0-5411 {}}} CYCLES {}}
+set a(0-5411) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#281 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30141 LOC {1 0.43123487499999996 1 0.53278695 1 0.53278695 1 0.5803430770708271 1 0.5803430770708271} PREDS {{146 0 0-4451 {}} {258 0 0-5397 {}} {259 0 0-5410 {}}} SUCCS {{259 0 0-5412 {}}} CYCLES {}}
+set a(0-5412) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#285 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 30142 LOC {1 0.47879105 1 0.580343125 1 0.580343125 1 0.618632584496936 1 0.618632584496936} PREDS {{146 0 0-4451 {}} {258 0 0-5392 {}} {259 0 0-5411 {}}} SUCCS {{259 0 0-5413 {}}} CYCLES {}}
+set a(0-5413) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#288 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-4427 XREFS 30143 LOC {1 0.51708055 1 0.6186326249999999 1 0.6186326249999999 1 0.6665116879329679 1 0.6665116879329679} PREDS {{146 0 0-4451 {}} {258 0 0-5388 {}} {259 0 0-5412 {}}} SUCCS {{259 0 0-5414 {}}} CYCLES {}}
+set a(0-5414) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#291 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-4427 XREFS 30144 LOC {1 0.564959675 1 0.66651175 1 0.66651175 1 0.7188962027684257 1 0.7188962027684257} PREDS {{146 0 0-4451 {}} {258 0 0-5383 {}} {259 0 0-5413 {}}} SUCCS {{259 0 0-5415 {}}} CYCLES {}}
+set a(0-5415) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#294 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 30145 LOC {1 0.704907925 1 0.71889625 1 0.71889625 1 0.7900803533364114 1 0.7900803533364114} PREDS {{146 0 0-4451 {}} {258 0 0-5343 {}} {259 0 0-5414 {}}} SUCCS {{258 0 0-5427 {}}} CYCLES {}}
+set a(0-5416) {NAME ACC1-1:slc(acc#10.psp)#62 TYPE READSLICE PAR 0-4427 XREFS 30146 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5418 {}}} CYCLES {}}
+set a(0-5417) {NAME ACC1-1:slc(acc#10.psp)#49 TYPE READSLICE PAR 0-4427 XREFS 30147 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5418 {}}} CYCLES {}}
+set a(0-5418) {NAME ACC1-1:conc#281 TYPE CONCATENATE PAR 0-4427 XREFS 30148 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.708741125} PREDS {{146 0 0-4451 {}} {258 0 0-5416 {}} {259 0 0-5417 {}}} SUCCS {{258 0 0-5426 {}}} CYCLES {}}
+set a(0-5419) {NAME ACC1-1:slc(acc#10.psp)#66 TYPE READSLICE PAR 0-4427 XREFS 30149 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5425 {}}} CYCLES {}}
+set a(0-5420) {NAME ACC1-1:slc(acc#10.psp)#67 TYPE READSLICE PAR 0-4427 XREFS 30150 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5425 {}}} CYCLES {}}
+set a(0-5421) {NAME ACC1-1:slc(acc#10.psp)#68 TYPE READSLICE PAR 0-4427 XREFS 30151 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5425 {}}} CYCLES {}}
+set a(0-5422) {NAME ACC1-1:slc(acc#10.psp)#51 TYPE READSLICE PAR 0-4427 XREFS 30152 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{258 0 0-5425 {}}} CYCLES {}}
+set a(0-5423) {NAME ACC1-1:slc(acc.idiv#2)#27 TYPE READSLICE PAR 0-4427 XREFS 30153 LOC {1 0.14655495 1 0.16054327499999999 1 0.16054327499999999 1 0.708741125} PREDS {{146 0 0-4451 {}} {258 0 0-4610 {}}} SUCCS {{259 0 0-5424 {}}} CYCLES {}}
+set a(0-5424) {NAME ACC1-1:exs#49 TYPE SIGNEXTEND PAR 0-4427 XREFS 30154 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.708741125} PREDS {{146 0 0-4451 {}} {259 0 0-5423 {}}} SUCCS {{259 0 0-5425 {}}} CYCLES {}}
+set a(0-5425) {NAME ACC1-1:conc#287 TYPE CONCATENATE PAR 0-4427 XREFS 30155 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.708741125} PREDS {{146 0 0-4451 {}} {258 0 0-5422 {}} {258 0 0-5421 {}} {258 0 0-5420 {}} {258 0 0-5419 {}} {259 0 0-5424 {}}} SUCCS {{259 0 0-5426 {}}} CYCLES {}}
+set a(0-5426) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,11) AREA_SCORE 11.24 QUANTITY 2 NAME ACC1:acc#293 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-4427 XREFS 30156 LOC {1 0.14655495 1 0.708741125 1 0.708741125 1 0.7900803533364112 1 0.7900803533364112} PREDS {{146 0 0-4451 {}} {258 0 0-5418 {}} {259 0 0-5425 {}}} SUCCS {{259 0 0-5427 {}}} CYCLES {}}
+set a(0-5427) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,13) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1-1:acc#124 TYPE ACCU DELAY {1.04 ns} LIBRARY_DELAY {1.04 ns} PAR 0-4427 XREFS 30157 LOC {1 0.776092075 1 0.7900804 1 0.7900804 1 0.8552960313734284 1 0.8552960313734284} PREDS {{146 0 0-4451 {}} {258 0 0-5415 {}} {259 0 0-5426 {}}} SUCCS {{258 0 0-5491 {}}} CYCLES {}}
+set a(0-5428) {NAME ACC1-3:slc(acc#10.psp)#57 TYPE READSLICE PAR 0-4427 XREFS 30158 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.77811255} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5433 {}}} CYCLES {}}
+set a(0-5429) {NAME ACC1-3:slc(acc#10.psp)#58 TYPE READSLICE PAR 0-4427 XREFS 30159 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.77811255} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5433 {}}} CYCLES {}}
+set a(0-5430) {NAME ACC1-3:slc(acc#10.psp)#59 TYPE READSLICE PAR 0-4427 XREFS 30160 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.77811255} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5433 {}}} CYCLES {}}
+set a(0-5431) {NAME ACC1-3:slc(acc#10.psp)#60 TYPE READSLICE PAR 0-4427 XREFS 30161 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.77811255} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5433 {}}} CYCLES {}}
+set a(0-5432) {NAME ACC1-3:slc(acc#10.psp)#48 TYPE READSLICE PAR 0-4427 XREFS 30162 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.77811255} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5433 {}}} CYCLES {}}
+set a(0-5433) {NAME ACC1-3:conc#280 TYPE CONCATENATE PAR 0-4427 XREFS 30163 LOC {1 0.14655495 1 0.77811255 1 0.77811255 1 0.77811255} PREDS {{146 0 0-4451 {}} {258 0 0-5431 {}} {258 0 0-5430 {}} {258 0 0-5429 {}} {258 0 0-5428 {}} {259 0 0-5432 {}}} SUCCS {{258 0 0-5490 {}}} CYCLES {}}
+set a(0-5434) {NAME ACC1-3:slc(acc#10.psp)#63 TYPE READSLICE PAR 0-4427 XREFS 30164 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.72572805} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5439 {}}} CYCLES {}}
+set a(0-5435) {NAME ACC1-3:slc(acc#10.psp)#64 TYPE READSLICE PAR 0-4427 XREFS 30165 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.72572805} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5439 {}}} CYCLES {}}
+set a(0-5436) {NAME ACC1-3:slc(acc#10.psp)#50 TYPE READSLICE PAR 0-4427 XREFS 30166 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.72572805} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5439 {}}} CYCLES {}}
+set a(0-5437) {NAME ACC1-3:slc(acc#10.psp)#65 TYPE READSLICE PAR 0-4427 XREFS 30167 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.72572805} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5438 {}}} CYCLES {}}
+set a(0-5438) {NAME ACC1-3:exs#543 TYPE SIGNEXTEND PAR 0-4427 XREFS 30168 LOC {1 0.14655495 1 0.72572805 1 0.72572805 1 0.72572805} PREDS {{146 0 0-4451 {}} {259 0 0-5437 {}}} SUCCS {{259 0 0-5439 {}}} CYCLES {}}
+set a(0-5439) {NAME ACC1-3:conc#285 TYPE CONCATENATE PAR 0-4427 XREFS 30169 LOC {1 0.14655495 1 0.72572805 1 0.72572805 1 0.72572805} PREDS {{146 0 0-4451 {}} {258 0 0-5436 {}} {258 0 0-5435 {}} {258 0 0-5434 {}} {259 0 0-5438 {}}} SUCCS {{258 0 0-5489 {}}} CYCLES {}}
+set a(0-5440) {NAME ACC1-3:slc(acc#10.psp)#36 TYPE READSLICE PAR 0-4427 XREFS 30170 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.682526275} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5444 {}}} CYCLES {}}
+set a(0-5441) {NAME ACC1-3:slc(acc#10.psp)#37 TYPE READSLICE PAR 0-4427 XREFS 30171 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.682526275} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{258 0 0-5444 {}}} CYCLES {}}
+set a(0-5442) {NAME ACC1-3:slc(acc.idiv#2)#29 TYPE READSLICE PAR 0-4427 XREFS 30172 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.682526275} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5443 {}}} CYCLES {}}
+set a(0-5443) {NAME ACC1-3:exs#50 TYPE SIGNEXTEND PAR 0-4427 XREFS 30173 LOC {1 0.14655495 1 0.682526275 1 0.682526275 1 0.682526275} PREDS {{146 0 0-4451 {}} {259 0 0-5442 {}}} SUCCS {{259 0 0-5444 {}}} CYCLES {}}
+set a(0-5444) {NAME ACC1-3:conc#289 TYPE CONCATENATE PAR 0-4427 XREFS 30174 LOC {1 0.14655495 1 0.682526275 1 0.682526275 1 0.682526275} PREDS {{146 0 0-4451 {}} {258 0 0-5441 {}} {258 0 0-5440 {}} {259 0 0-5443 {}}} SUCCS {{258 0 0-5488 {}}} CYCLES {}}
+set a(0-5445) {NAME ACC1-3:slc(acc.idiv#2)#5 TYPE READSLICE PAR 0-4427 XREFS 30175 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5446 {}}} CYCLES {}}
+set a(0-5446) {NAME ACC1-3:exs#38 TYPE SIGNEXTEND PAR 0-4427 XREFS 30176 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5445 {}}} SUCCS {{259 0 0-5447 {}}} CYCLES {}}
+set a(0-5447) {NAME ACC1:conc#591 TYPE CONCATENATE PAR 0-4427 XREFS 30177 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5446 {}}} SUCCS {{258 0 0-5455 {}}} CYCLES {}}
+set a(0-5448) {NAME ACC1-3:slc(acc.idiv#2)#7 TYPE READSLICE PAR 0-4427 XREFS 30178 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5449 {}}} CYCLES {}}
+set a(0-5449) {NAME ACC1-3:exs#39 TYPE SIGNEXTEND PAR 0-4427 XREFS 30179 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5448 {}}} SUCCS {{258 0 0-5454 {}}} CYCLES {}}
+set a(0-5450) {NAME ACC1-3:slc(acc.imod#11) TYPE READSLICE PAR 0-4427 XREFS 30180 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-4899 {}}} SUCCS {{258 0 0-5453 {}}} CYCLES {}}
+set a(0-5451) {NAME ACC1-3:slc(acc.idiv#2)#44 TYPE READSLICE PAR 0-4427 XREFS 30181 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5452 {}}} CYCLES {}}
+set a(0-5452) {NAME ACC1-3:not#91 TYPE NOT PAR 0-4427 XREFS 30182 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5451 {}}} SUCCS {{259 0 0-5453 {}}} CYCLES {}}
+set a(0-5453) {NAME ACC1-3:nand#2 TYPE NAND PAR 0-4427 XREFS 30183 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-5450 {}} {259 0 0-5452 {}}} SUCCS {{259 0 0-5454 {}}} CYCLES {}}
+set a(0-5454) {NAME ACC1:conc#592 TYPE CONCATENATE PAR 0-4427 XREFS 30184 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-5449 {}} {259 0 0-5453 {}}} SUCCS {{259 0 0-5455 {}}} CYCLES {}}
+set a(0-5455) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#247 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30185 LOC {1 0.3836787 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.5816229770708271} PREDS {{146 0 0-4451 {}} {258 0 0-5447 {}} {259 0 0-5454 {}}} SUCCS {{259 0 0-5456 {}}} CYCLES {}}
+set a(0-5456) {NAME ACC1:slc#73 TYPE READSLICE PAR 0-4427 XREFS 30186 LOC {1 0.43123487499999996 1 0.581623025 1 0.581623025 1 0.581623025} PREDS {{146 0 0-4451 {}} {259 0 0-5455 {}}} SUCCS {{258 0 0-5467 {}}} CYCLES {}}
+set a(0-5457) {NAME ACC1-3:slc(acc.idiv#2)#15 TYPE READSLICE PAR 0-4427 XREFS 30187 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5458 {}}} CYCLES {}}
+set a(0-5458) {NAME ACC1-3:exs#43 TYPE SIGNEXTEND PAR 0-4427 XREFS 30188 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5457 {}}} SUCCS {{259 0 0-5459 {}}} CYCLES {}}
+set a(0-5459) {NAME ACC1:conc#589 TYPE CONCATENATE PAR 0-4427 XREFS 30189 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5458 {}}} SUCCS {{258 0 0-5465 {}}} CYCLES {}}
+set a(0-5460) {NAME ACC1-3:slc(acc.idiv#2)#17 TYPE READSLICE PAR 0-4427 XREFS 30190 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5461 {}}} CYCLES {}}
+set a(0-5461) {NAME ACC1-3:exs#44 TYPE SIGNEXTEND PAR 0-4427 XREFS 30191 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5460 {}}} SUCCS {{258 0 0-5464 {}}} CYCLES {}}
+set a(0-5462) {NAME ACC1-3:slc(acc.imod#10)#12 TYPE READSLICE PAR 0-4427 XREFS 30192 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-4890 {}}} SUCCS {{259 0 0-5463 {}}} CYCLES {}}
+set a(0-5463) {NAME ACC1-3:not#150 TYPE NOT PAR 0-4427 XREFS 30193 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5462 {}}} SUCCS {{259 0 0-5464 {}}} CYCLES {}}
+set a(0-5464) {NAME ACC1:conc#590 TYPE CONCATENATE PAR 0-4427 XREFS 30194 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-5461 {}} {259 0 0-5463 {}}} SUCCS {{259 0 0-5465 {}}} CYCLES {}}
+set a(0-5465) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#246 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30195 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.5816229770708271} PREDS {{146 0 0-4451 {}} {258 0 0-5459 {}} {259 0 0-5464 {}}} SUCCS {{259 0 0-5466 {}}} CYCLES {}}
+set a(0-5466) {NAME ACC1:slc#72 TYPE READSLICE PAR 0-4427 XREFS 30196 LOC {1 0.40398894999999996 1 0.581623025 1 0.581623025 1 0.581623025} PREDS {{146 0 0-4451 {}} {259 0 0-5465 {}}} SUCCS {{259 0 0-5467 {}}} CYCLES {}}
+set a(0-5467) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#253 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30197 LOC {1 0.43123487499999996 1 0.581623025 1 0.581623025 1 0.6291791520708271 1 0.6291791520708271} PREDS {{146 0 0-4451 {}} {258 0 0-5456 {}} {259 0 0-5466 {}}} SUCCS {{258 0 0-5487 {}}} CYCLES {}}
+set a(0-5468) {NAME ACC1-3:slc(acc.idiv#2)#13 TYPE READSLICE PAR 0-4427 XREFS 30198 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5469 {}}} CYCLES {}}
+set a(0-5469) {NAME ACC1-3:exs#42 TYPE SIGNEXTEND PAR 0-4427 XREFS 30199 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5468 {}}} SUCCS {{259 0 0-5470 {}}} CYCLES {}}
+set a(0-5470) {NAME ACC1:conc#587 TYPE CONCATENATE PAR 0-4427 XREFS 30200 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5469 {}}} SUCCS {{258 0 0-5475 {}}} CYCLES {}}
+set a(0-5471) {NAME ACC1-3:slc(acc.idiv#2)#23 TYPE READSLICE PAR 0-4427 XREFS 30201 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5472 {}}} CYCLES {}}
+set a(0-5472) {NAME ACC1-3:exs#47 TYPE SIGNEXTEND PAR 0-4427 XREFS 30202 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5471 {}}} SUCCS {{258 0 0-5474 {}}} CYCLES {}}
+set a(0-5473) {NAME ACC1-3:slc(acc.imod#10)#11 TYPE READSLICE PAR 0-4427 XREFS 30203 LOC {1 0.356432775 1 0.506820925 1 0.506820925 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-4890 {}}} SUCCS {{259 0 0-5474 {}}} CYCLES {}}
+set a(0-5474) {NAME ACC1:conc#588 TYPE CONCATENATE PAR 0-4427 XREFS 30204 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-5472 {}} {259 0 0-5473 {}}} SUCCS {{259 0 0-5475 {}}} CYCLES {}}
+set a(0-5475) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#245 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30205 LOC {1 0.356432775 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.5816229770708271} PREDS {{146 0 0-4451 {}} {258 0 0-5470 {}} {259 0 0-5474 {}}} SUCCS {{259 0 0-5476 {}}} CYCLES {}}
+set a(0-5476) {NAME ACC1:slc#71 TYPE READSLICE PAR 0-4427 XREFS 30206 LOC {1 0.40398894999999996 1 0.581623025 1 0.581623025 1 0.581623025} PREDS {{146 0 0-4451 {}} {259 0 0-5475 {}}} SUCCS {{258 0 0-5486 {}}} CYCLES {}}
+set a(0-5477) {NAME ACC1-3:slc(acc.idiv#2)#19 TYPE READSLICE PAR 0-4427 XREFS 30207 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5478 {}}} CYCLES {}}
+set a(0-5478) {NAME ACC1-3:exs#45 TYPE SIGNEXTEND PAR 0-4427 XREFS 30208 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5477 {}}} SUCCS {{259 0 0-5479 {}}} CYCLES {}}
+set a(0-5479) {NAME ACC1:conc#585 TYPE CONCATENATE PAR 0-4427 XREFS 30209 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5478 {}}} SUCCS {{258 0 0-5484 {}}} CYCLES {}}
+set a(0-5480) {NAME ACC1-3:slc(acc.idiv#2)#21 TYPE READSLICE PAR 0-4427 XREFS 30210 LOC {1 0.14655495 1 0.29694309999999996 1 0.29694309999999996 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-4832 {}}} SUCCS {{259 0 0-5481 {}}} CYCLES {}}
+set a(0-5481) {NAME ACC1-3:exs#46 TYPE SIGNEXTEND PAR 0-4427 XREFS 30211 LOC {1 0.14655495 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {259 0 0-5480 {}}} SUCCS {{258 0 0-5483 {}}} CYCLES {}}
+set a(0-5482) {NAME ACC1-3:slc(ACC1:acc#113.psp)#9 TYPE READSLICE PAR 0-4427 XREFS 30212 LOC {1 0.267931 1 0.41831915 1 0.41831915 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-4872 {}}} SUCCS {{259 0 0-5483 {}}} CYCLES {}}
+set a(0-5483) {NAME ACC1:conc#586 TYPE CONCATENATE PAR 0-4427 XREFS 30213 LOC {1 0.267931 1 0.53406685 1 0.53406685 1 0.53406685} PREDS {{146 0 0-4451 {}} {258 0 0-5481 {}} {259 0 0-5482 {}}} SUCCS {{259 0 0-5484 {}}} CYCLES {}}
+set a(0-5484) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#244 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30214 LOC {1 0.267931 1 0.53406685 1 0.53406685 1 0.5816229770708271 1 0.5816229770708271} PREDS {{146 0 0-4451 {}} {258 0 0-5479 {}} {259 0 0-5483 {}}} SUCCS {{259 0 0-5485 {}}} CYCLES {}}
+set a(0-5485) {NAME ACC1:slc#70 TYPE READSLICE PAR 0-4427 XREFS 30215 LOC {1 0.315487175 1 0.581623025 1 0.581623025 1 0.581623025} PREDS {{146 0 0-4451 {}} {259 0 0-5484 {}}} SUCCS {{259 0 0-5486 {}}} CYCLES {}}
+set a(0-5486) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#252 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30216 LOC {1 0.40398894999999996 1 0.581623025 1 0.581623025 1 0.6291791520708271 1 0.6291791520708271} PREDS {{146 0 0-4451 {}} {258 0 0-5476 {}} {259 0 0-5485 {}}} SUCCS {{259 0 0-5487 {}}} CYCLES {}}
+set a(0-5487) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#257 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-4427 XREFS 30217 LOC {1 0.47879105 1 0.6291791999999999 1 0.6291791999999999 1 0.6825262201789504 1 0.6825262201789504} PREDS {{146 0 0-4451 {}} {258 0 0-5467 {}} {259 0 0-5486 {}}} SUCCS {{259 0 0-5488 {}}} CYCLES {}}
+set a(0-5488) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME ACC1:acc#260 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 30218 LOC {1 0.532138125 1 0.682526275 1 0.682526275 1 0.7257279984103023 1 0.7257279984103023} PREDS {{146 0 0-4451 {}} {258 0 0-5444 {}} {259 0 0-5487 {}}} SUCCS {{259 0 0-5489 {}}} CYCLES {}}
+set a(0-5489) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#263 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-4427 XREFS 30219 LOC {1 0.5753399 1 0.72572805 1 0.72572805 1 0.7781125027684257 1 0.7781125027684257} PREDS {{146 0 0-4451 {}} {258 0 0-5439 {}} {259 0 0-5488 {}}} SUCCS {{259 0 0-5490 {}}} CYCLES {}}
+set a(0-5490) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,0,10) AREA_SCORE 10.25 QUANTITY 5 NAME ACC1:acc#265 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-4427 XREFS 30220 LOC {1 0.6277244 1 0.77811255 1 0.77811255 1 0.85529603186502 1 0.85529603186502} PREDS {{146 0 0-4451 {}} {258 0 0-5433 {}} {259 0 0-5489 {}}} SUCCS {{259 0 0-5491 {}}} CYCLES {}}
+set a(0-5491) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,13) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#267 TYPE ACCU DELAY {1.04 ns} LIBRARY_DELAY {1.04 ns} PAR 0-4427 XREFS 30221 LOC {1 0.8413077499999999 1 0.8552960749999999 1 0.8552960749999999 1 0.9205117063734283 1 0.9205117063734283} PREDS {{146 0 0-4451 {}} {258 0 0-5427 {}} {259 0 0-5490 {}}} SUCCS {{259 0 0-5492 {}}} CYCLES {}}
+set a(0-5492) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME ACC1-3:acc#124 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-4427 XREFS 30222 LOC {1 0.9065234249999999 1 0.92051175 1 0.92051175 1 0.9999999534997777 1 0.9999999534997777} PREDS {{146 0 0-4451 {}} {258 0 0-5280 {}} {259 0 0-5491 {}}} SUCCS {{259 0 0-5493 {}}} CYCLES {}}
+set a(0-5493) {NAME ACC1:exs#750 TYPE SIGNEXTEND PAR 0-4427 XREFS 30223 LOC {1 0.986011675 1 1.0 1 1.0 2 0.06859512499999999} PREDS {{146 0 0-4451 {}} {259 0 0-5492 {}}} SUCCS {{258 0 0-5585 {}}} CYCLES {}}
+set a(0-5494) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(3,1,2) AREA_SCORE 2.76 QUANTITY 4 NAME FRAME:for:mux#4 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30224 LOC {1 0.3471661 1 0.410926075 1 0.410926075 1 0.4339866375 1 0.6214930125} PREDS {{258 0 0-4450 {}} {262 0 0-5949 {}} {258 0 0-4815 {}} {258 0 0-4433 {}}} SUCCS {{258 0 0-5689 {}} {258 0 0-5788 {}} {258 0 0-5949 {}}} CYCLES {}}
+set a(0-5495) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(2,1,2) AREA_SCORE 1.84 QUANTITY 2 NAME FRAME:for:mux#5 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30225 LOC {1 0.374412025 1 0.410926075 1 0.410926075 1 0.4339866375 1 0.6214930125} PREDS {{258 0 0-4450 {}} {262 0 0-5950 {}} {258 0 0-4824 {}} {258 0 0-4432 {}}} SUCCS {{258 0 0-5663 {}} {258 0 0-5665 {}} {258 0 0-5677 {}} {258 0 0-5950 {}}} CYCLES {}}
+set a(0-5496) {NAME FRAME:for:asn#4 TYPE ASSIGN PAR 0-4427 XREFS 30226 LOC {0 1.0 1 0.55219575 1 0.55219575 1 0.6501168749999999} PREDS {{262 0 0-5951 {}}} SUCCS {{259 0 0-5497 {}} {256 0 0-5951 {}}} CYCLES {}}
+set a(0-5497) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#8 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30227 LOC {1 0.0 1 0.55219575 1 0.55219575 1 0.5752563125 1 0.6731774374999999} PREDS {{258 0 0-4450 {}} {258 0 0-4452 {}} {258 0 0-4442 {}} {259 0 0-5496 {}}} SUCCS {{258 0 0-5529 {}} {258 0 0-5535 {}} {258 0 0-5542 {}} {258 0 0-5570 {}} {258 0 0-5575 {}} {258 0 0-5581 {}} {258 0 0-5951 {}}} CYCLES {}}
+set a(0-5498) {NAME FRAME:for:asn#5 TYPE ASSIGN PAR 0-4427 XREFS 30228 LOC {0 1.0 1 0.55219575 1 0.55219575 1 0.6501168749999999} PREDS {{262 0 0-5951 {}}} SUCCS {{258 0 0-5500 {}} {256 0 0-5951 {}}} CYCLES {}}
+set a(0-5499) {NAME FRAME:for:asn#6 TYPE ASSIGN PAR 0-4427 XREFS 30229 LOC {0 1.0 1 0.55219575 1 0.55219575 1 0.6501168749999999} PREDS {{262 0 0-5952 {}}} SUCCS {{259 0 0-5500 {}} {256 0 0-5952 {}}} CYCLES {}}
+set a(0-5500) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#9 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30230 LOC {1 0.0 1 0.55219575 1 0.55219575 1 0.5752563125 1 0.6731774374999999} PREDS {{258 0 0-4450 {}} {258 0 0-5498 {}} {259 0 0-5499 {}}} SUCCS {{258 0 0-5528 {}} {258 0 0-5534 {}} {258 0 0-5541 {}} {258 0 0-5569 {}} {258 0 0-5574 {}} {258 0 0-5580 {}} {258 0 0-5952 {}}} CYCLES {}}
+set a(0-5501) {NAME FRAME:for:asn#7 TYPE ASSIGN PAR 0-4427 XREFS 30231 LOC {0 1.0 1 0.55219575 1 0.55219575 1 0.6501168749999999} PREDS {{262 0 0-5952 {}}} SUCCS {{259 0 0-5502 {}} {256 0 0-5952 {}}} CYCLES {}}
+set a(0-5502) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#10 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30232 LOC {1 0.0 1 0.55219575 1 0.55219575 1 0.5752563125 1 0.6731774374999999} PREDS {{258 0 0-4450 {}} {262 0 0-5953 {}} {259 0 0-5501 {}}} SUCCS {{258 0 0-5527 {}} {258 0 0-5533 {}} {258 0 0-5540 {}} {258 0 0-5568 {}} {258 0 0-5573 {}} {258 0 0-5579 {}} {258 0 0-5953 {}}} CYCLES {}}
+set a(0-5503) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(3,1,2) AREA_SCORE 2.76 QUANTITY 4 NAME FRAME:for:mux#14 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30233 LOC {1 0.319920175 1 0.55658895 1 0.55658895 1 0.5796495125 1 0.7671558875} PREDS {{258 0 0-4450 {}} {262 0 0-5956 {}} {258 0 0-4808 {}} {258 0 0-4434 {}}} SUCCS {{258 0 0-5807 {}} {258 0 0-5956 {}}} CYCLES {}}
+set a(0-5504) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(12,1,2) AREA_SCORE 11.03 QUANTITY 2 NAME FRAME:for:mux#17 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30234 LOC {1 0.14655495 1 0.29206689999999996 1 0.29206689999999996 1 0.31512746249999996 1 0.5026338375} PREDS {{258 0 0-4450 {}} {262 0 0-5957 {}} {258 0 0-4760 {}} {258 0 0-4436 {}}} SUCCS {{258 0 0-5596 {}} {258 0 0-5600 {}} {258 0 0-5604 {}} {258 0 0-5605 {}} {258 0 0-5608 {}} {258 0 0-5612 {}} {258 0 0-5616 {}} {258 0 0-5617 {}} {258 0 0-5618 {}} {258 0 0-5629 {}} {258 0 0-5632 {}} {258 0 0-5638 {}} {258 0 0-5641 {}} {258 0 0-5662 {}} {258 0 0-5678 {}} {258 0 0-5744 {}} {258 0 0-5747 {}} {258 0 0-5755 {}} {258 0 0-5758 {}} {258 0 0-5764 {}} {258 0 0-5767 {}} {258 0 0-5769 {}} {258 0 0-5774 {}} {258 0 0-5775 {}} {258 0 0-5779 {}} {258 0 0-5781 {}} {258 0 0-5815 {}} {258 0 0-5828 {}} {258 0 0-5833 {}} {258 0 0-5834 {}} {258 0 0-5838 {}} {258 0 0-5842 {}} {258 0 0-5846 {}} {258 0 0-5851 {}} {258 0 0-5852 {}} {258 0 0-5858 {}} {258 0 0-5863 {}} {258 0 0-5957 {}}} CYCLES {}}
+set a(0-5505) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(4,1,2) AREA_SCORE 3.68 QUANTITY 2 NAME FRAME:for:mux#20 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30235 LOC {1 0.258664325 1 0.410926075 1 0.410926075 1 0.4339866375 1 0.6214930125} PREDS {{258 0 0-4450 {}} {262 0 0-5958 {}} {258 0 0-4797 {}} {258 0 0-4435 {}}} SUCCS {{258 0 0-5699 {}} {258 0 0-5708 {}} {258 0 0-5721 {}} {258 0 0-5786 {}} {258 0 0-5958 {}}} CYCLES {}}
+set a(0-5506) {NAME not#16 TYPE NOT PAR 0-4427 XREFS 30236 LOC {1 0.0 1 0.251002 1 0.251002 1 0.438508375} PREDS {{258 0 0-4450 {}}} SUCCS {{259 0 0-5507 {}}} CYCLES {}}
+set a(0-5507) {NAME FRAME:for:exs#19 TYPE SIGNEXTEND PAR 0-4427 XREFS 30237 LOC {1 0.0 1 0.251002 1 0.251002 1 0.438508375} PREDS {{259 0 0-5506 {}}} SUCCS {{259 0 0-5508 {}}} CYCLES {}}
+set a(0-5508) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 2 NAME FRAME:for:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-4427 XREFS 30238 LOC {1 0.0 1 0.251002 1 0.251002 1 0.2674087312638539 1 0.4549151062638539} PREDS {{262 0 0-5960 {}} {259 0 0-5507 {}}} SUCCS {{258 0 0-5514 {}} {258 0 0-5515 {}} {258 0 0-5516 {}} {258 0 0-5517 {}} {258 0 0-5518 {}} {258 0 0-5521 {}} {258 0 0-5523 {}} {258 0 0-5530 {}} {258 0 0-5536 {}} {258 0 0-5543 {}} {258 0 0-5551 {}} {258 0 0-5553 {}} {258 0 0-5571 {}} {258 0 0-5576 {}} {258 0 0-5582 {}} {258 0 0-5589 {}} {256 0 0-5960 {}}} CYCLES {}}
+set a(0-5509) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(3,1,2) AREA_SCORE 2.76 QUANTITY 4 NAME FRAME:for:mux#25 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30239 LOC {1 0.3471661 1 0.410926075 1 0.410926075 1 0.4339866375 1 0.6214930125} PREDS {{258 0 0-4450 {}} {262 0 0-5961 {}} {258 0 0-4592 {}} {258 0 0-4438 {}}} SUCCS {{258 0 0-5634 {}} {258 0 0-5803 {}} {258 0 0-5961 {}}} CYCLES {}}
+set a(0-5510) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(2,1,2) AREA_SCORE 1.84 QUANTITY 2 NAME FRAME:for:mux#26 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30240 LOC {1 0.374412025 1 0.45736869999999996 1 0.45736869999999996 1 0.48042926249999995 1 0.6679356375} PREDS {{258 0 0-4450 {}} {262 0 0-5962 {}} {258 0 0-4601 {}} {258 0 0-4437 {}}} SUCCS {{258 0 0-5792 {}} {258 0 0-5794 {}} {258 0 0-5808 {}} {258 0 0-5962 {}}} CYCLES {}}
+set a(0-5511) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(3,1,2) AREA_SCORE 2.76 QUANTITY 4 NAME FRAME:for:mux#30 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30241 LOC {1 0.319920175 1 0.56237985 1 0.56237985 1 0.5854404125 1 0.7729467875} PREDS {{258 0 0-4450 {}} {262 0 0-5963 {}} {258 0 0-4585 {}} {258 0 0-4439 {}}} SUCCS {{258 0 0-5818 {}} {258 0 0-5963 {}}} CYCLES {}}
+set a(0-5512) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(12,1,2) AREA_SCORE 11.03 QUANTITY 2 NAME FRAME:for:mux#33 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30242 LOC {1 0.14655495 1 0.29206689999999996 1 0.29206689999999996 1 0.31512746249999996 1 0.5026338375} PREDS {{258 0 0-4450 {}} {262 0 0-5964 {}} {258 0 0-4537 {}} {258 0 0-4441 {}}} SUCCS {{258 0 0-5597 {}} {258 0 0-5601 {}} {258 0 0-5609 {}} {258 0 0-5613 {}} {258 0 0-5624 {}} {258 0 0-5625 {}} {258 0 0-5648 {}} {258 0 0-5651 {}} {258 0 0-5657 {}} {258 0 0-5660 {}} {258 0 0-5672 {}} {258 0 0-5675 {}} {258 0 0-5684 {}} {258 0 0-5687 {}} {258 0 0-5694 {}} {258 0 0-5697 {}} {258 0 0-5703 {}} {258 0 0-5706 {}} {258 0 0-5716 {}} {258 0 0-5719 {}} {258 0 0-5725 {}} {258 0 0-5728 {}} {258 0 0-5730 {}} {258 0 0-5735 {}} {258 0 0-5738 {}} {258 0 0-5740 {}} {258 0 0-5749 {}} {258 0 0-5760 {}} {258 0 0-5778 {}} {258 0 0-5791 {}} {258 0 0-5809 {}} {258 0 0-5829 {}} {258 0 0-5832 {}} {258 0 0-5837 {}} {258 0 0-5841 {}} {258 0 0-5859 {}} {258 0 0-5862 {}} {258 0 0-5964 {}}} CYCLES {}}
+set a(0-5513) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(4,1,2) AREA_SCORE 3.68 QUANTITY 2 NAME FRAME:for:mux#36 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30243 LOC {1 0.258664325 1 0.410926075 1 0.410926075 1 0.4339866375 1 0.6214930125} PREDS {{258 0 0-4450 {}} {262 0 0-5965 {}} {258 0 0-4574 {}} {258 0 0-4440 {}}} SUCCS {{258 0 0-5643 {}} {258 0 0-5653 {}} {258 0 0-5801 {}} {258 0 0-5819 {}} {258 0 0-5965 {}}} CYCLES {}}
+set a(0-5514) {NAME slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-4427 XREFS 30244 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-5508 {}}} SUCCS {{258 0 0-5522 {}}} CYCLES {}}
+set a(0-5515) {NAME slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-4427 XREFS 30245 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-5508 {}}} SUCCS {{258 0 0-5519 {}}} CYCLES {}}
+set a(0-5516) {NAME slc(i#6.lpi#1.dfm)#2 TYPE READSLICE PAR 0-4427 XREFS 30246 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-5508 {}}} SUCCS {{258 0 0-5525 {}}} CYCLES {}}
+set a(0-5517) {NAME slc(i#6.lpi#1.dfm)#3 TYPE READSLICE PAR 0-4427 XREFS 30247 LOC {1 0.016406775 1 0.267408775 1 0.267408775 3 1.0} PREDS {{258 0 0-5508 {}}} SUCCS {} CYCLES {}}
+set a(0-5518) {NAME FRAME:for:slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-4427 XREFS 30248 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-5508 {}}} SUCCS {{258 0 0-5520 {}}} CYCLES {}}
+set a(0-5519) {NAME FRAME:for:not#1 TYPE NOT PAR 0-4427 XREFS 30249 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-5515 {}}} SUCCS {{259 0 0-5520 {}}} CYCLES {}}
+set a(0-5520) {NAME FRAME:for:nand TYPE NAND PAR 0-4427 XREFS 30250 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-5518 {}} {259 0 0-5519 {}}} SUCCS {{258 0 0-5526 {}}} CYCLES {}}
+set a(0-5521) {NAME FRAME:for:slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-4427 XREFS 30251 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-5508 {}}} SUCCS {{259 0 0-5522 {}}} CYCLES {}}
+set a(0-5522) {NAME FRAME:for:nor TYPE NOR PAR 0-4427 XREFS 30252 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-5514 {}} {259 0 0-5521 {}}} SUCCS {{258 0 0-5526 {}}} CYCLES {}}
+set a(0-5523) {NAME FRAME:for:slc(i#6.lpi#1.dfm)#2 TYPE READSLICE PAR 0-4427 XREFS 30253 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-5508 {}}} SUCCS {{259 0 0-5524 {}}} CYCLES {}}
+set a(0-5524) {NAME FRAME:for:not#2 TYPE NOT PAR 0-4427 XREFS 30254 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{259 0 0-5523 {}}} SUCCS {{259 0 0-5525 {}}} CYCLES {}}
+set a(0-5525) {NAME FRAME:for:and#3 TYPE AND PAR 0-4427 XREFS 30255 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-5516 {}} {259 0 0-5524 {}}} SUCCS {{259 0 0-5526 {}}} CYCLES {}}
+set a(0-5526) {NAME FRAME:for:or#3 TYPE OR PAR 0-4427 XREFS 30256 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.807076075} PREDS {{258 0 0-5522 {}} {258 0 0-5520 {}} {259 0 0-5525 {}}} SUCCS {{258 0 0-5531 {}} {258 0 0-5537 {}} {258 0 0-5544 {}}} CYCLES {}}
+set a(0-5527) {NAME {regs.operator[]#10:slc(regs.regs(2))} TYPE READSLICE PAR 0-4427 XREFS 30257 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-5502 {}}} SUCCS {{258 0 0-5530 {}}} CYCLES {}}
+set a(0-5528) {NAME {regs.operator[]#10:slc(regs.regs(1))} TYPE READSLICE PAR 0-4427 XREFS 30258 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-5500 {}}} SUCCS {{258 0 0-5530 {}}} CYCLES {}}
+set a(0-5529) {NAME {regs.operator[]#10:slc(regs.regs(0))} TYPE READSLICE PAR 0-4427 XREFS 30259 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-5497 {}}} SUCCS {{259 0 0-5530 {}}} CYCLES {}}
+set a(0-5530) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#10:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-4427 XREFS 30260 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6337841 1 0.807076025} PREDS {{258 0 0-5508 {}} {258 0 0-5528 {}} {258 0 0-5527 {}} {259 0 0-5529 {}}} SUCCS {{258 0 0-5532 {}}} CYCLES {}}
+set a(0-5531) {NAME FRAME:for:conc#6 TYPE CONCATENATE PAR 0-4427 XREFS 30261 LOC {1 0.016406775 1 0.63378415 1 0.63378415 1 0.807076075} PREDS {{258 0 0-5526 {}}} SUCCS {{259 0 0-5532 {}}} CYCLES {}}
+set a(0-5532) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#1 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-4427 XREFS 30262 LOC {1 0.08158839999999999 1 0.63378415 1 0.63378415 1 0.8267080124999999 1 0.9999999374999999} PREDS {{258 0 0-5530 {}} {259 0 0-5531 {}}} SUCCS {{258 0 0-5539 {}}} CYCLES {}}
+set a(0-5533) {NAME {regs.operator[]#11:slc(regs.regs(2))} TYPE READSLICE PAR 0-4427 XREFS 30263 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-5502 {}}} SUCCS {{258 0 0-5536 {}}} CYCLES {}}
+set a(0-5534) {NAME {regs.operator[]#11:slc(regs.regs(1))} TYPE READSLICE PAR 0-4427 XREFS 30264 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-5500 {}}} SUCCS {{258 0 0-5536 {}}} CYCLES {}}
+set a(0-5535) {NAME {regs.operator[]#11:slc(regs.regs(0))} TYPE READSLICE PAR 0-4427 XREFS 30265 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-5497 {}}} SUCCS {{259 0 0-5536 {}}} CYCLES {}}
+set a(0-5536) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#11:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-4427 XREFS 30266 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6337841 1 0.807076025} PREDS {{258 0 0-5508 {}} {258 0 0-5534 {}} {258 0 0-5533 {}} {259 0 0-5535 {}}} SUCCS {{258 0 0-5538 {}}} CYCLES {}}
+set a(0-5537) {NAME FRAME:for:conc#7 TYPE CONCATENATE PAR 0-4427 XREFS 30267 LOC {1 0.016406775 1 0.63378415 1 0.63378415 1 0.807076075} PREDS {{258 0 0-5526 {}}} SUCCS {{259 0 0-5538 {}}} CYCLES {}}
+set a(0-5538) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#2 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-4427 XREFS 30268 LOC {1 0.08158839999999999 1 0.63378415 1 0.63378415 1 0.8267080124999999 1 0.9999999374999999} PREDS {{258 0 0-5536 {}} {259 0 0-5537 {}}} SUCCS {{259 0 0-5539 {}}} CYCLES {}}
+set a(0-5539) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME FRAME:for:acc#23 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-4427 XREFS 30269 LOC {1 0.274512325 1 0.826708075 1 0.826708075 1 0.9061962784997777 2 0.10375282849977767} PREDS {{258 0 0-5532 {}} {259 0 0-5538 {}}} SUCCS {{258 0 0-5546 {}}} CYCLES {}}
+set a(0-5540) {NAME {regs.operator[]#9:slc(regs.regs(2))} TYPE READSLICE PAR 0-4427 XREFS 30270 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-5502 {}}} SUCCS {{258 0 0-5543 {}}} CYCLES {}}
+set a(0-5541) {NAME {regs.operator[]#9:slc(regs.regs(1))} TYPE READSLICE PAR 0-4427 XREFS 30271 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-5500 {}}} SUCCS {{258 0 0-5543 {}}} CYCLES {}}
+set a(0-5542) {NAME {regs.operator[]#9:slc(regs.regs(0))} TYPE READSLICE PAR 0-4427 XREFS 30272 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-5497 {}}} SUCCS {{259 0 0-5543 {}}} CYCLES {}}
+set a(0-5543) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#9:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-4427 XREFS 30273 LOC {1 0.0230606 1 0.6547446 1 0.6547446 1 0.71327235 1 0.807076025} PREDS {{258 0 0-5508 {}} {258 0 0-5541 {}} {258 0 0-5540 {}} {259 0 0-5542 {}}} SUCCS {{258 0 0-5545 {}}} CYCLES {}}
+set a(0-5544) {NAME FRAME:for:conc#5 TYPE CONCATENATE PAR 0-4427 XREFS 30274 LOC {1 0.016406775 1 0.7132723999999999 1 0.7132723999999999 1 0.807076075} PREDS {{258 0 0-5526 {}}} SUCCS {{259 0 0-5545 {}}} CYCLES {}}
+set a(0-5545) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-4427 XREFS 30275 LOC {1 0.08158839999999999 1 0.7132723999999999 1 0.7132723999999999 1 0.9061962625 1 0.9999999374999999} PREDS {{258 0 0-5543 {}} {259 0 0-5544 {}}} SUCCS {{259 0 0-5546 {}}} CYCLES {}}
+set a(0-5546) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,0,12,1,13) AREA_SCORE 14.00 QUANTITY 2 NAME FRAME:for:acc#24 TYPE ACCU DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-4427 XREFS 30276 LOC {1 0.354000575 1 0.9061963249999999 1 0.9061963249999999 1 0.9999999502166911 2 0.1975565002166912} PREDS {{258 0 0-5539 {}} {259 0 0-5545 {}}} SUCCS {{258 0 0-5550 {}}} CYCLES {}}
+set a(0-5547) {NAME FRAME:for:slc(in(0).sva) TYPE READSLICE PAR 0-4427 XREFS 30277 LOC {1 0.986011675 1 1.0 1 1.0 2 0.17449594999999998} PREDS {{258 0 0-5196 {}} {258 0 0-4431 {}}} SUCCS {{259 0 0-5548 {}}} CYCLES {}}
+set a(0-5548) {NAME FRAME:for:exs#20 TYPE SIGNEXTEND PAR 0-4427 XREFS 30278 LOC {1 0.986011675 2 0.17449594999999998 2 0.17449594999999998 2 0.17449594999999998} PREDS {{259 0 0-5547 {}}} SUCCS {{259 0 0-5549 {}}} CYCLES {}}
+set a(0-5549) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 2 NAME FRAME:for:mux#11 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30279 LOC {2 0.0 2 0.17449594999999998 2 0.17449594999999998 2 0.19755651249999998 2 0.19755651249999998} PREDS {{258 0 0-4450 {}} {262 0 0-5954 {}} {259 0 0-5548 {}}} SUCCS {{259 0 0-5550 {}} {256 0 0-5954 {}}} CYCLES {}}
+set a(0-5550) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,13,1,16) AREA_SCORE 17.00 QUANTITY 3 NAME FRAME:for:acc#20 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-4427 XREFS 30280 LOC {2 0.0230606 2 0.19755655 2 0.19755655 2 0.3034573281715468 2 0.3034573281715468} PREDS {{258 0 0-5546 {}} {259 0 0-5549 {}}} SUCCS {{258 0 0-5869 {}} {258 0 0-5954 {}}} CYCLES {}}
+set a(0-5551) {NAME i:slc(i#3)#1 TYPE READSLICE PAR 0-4427 XREFS 30281 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{258 0 0-5508 {}}} SUCCS {{259 0 0-5552 {}}} CYCLES {}}
+set a(0-5552) {NAME FRAME:for:not#4 TYPE NOT PAR 0-4427 XREFS 30282 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{259 0 0-5551 {}}} SUCCS {{258 0 0-5554 {}}} CYCLES {}}
+set a(0-5553) {NAME i:slc(i#3)#2 TYPE READSLICE PAR 0-4427 XREFS 30283 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{258 0 0-5508 {}}} SUCCS {{259 0 0-5554 {}}} CYCLES {}}
+set a(0-5554) {NAME FRAME:for:conc TYPE CONCATENATE PAR 0-4427 XREFS 30284 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{258 0 0-5552 {}} {259 0 0-5553 {}}} SUCCS {{259 0 0-5555 {}} {258 0 0-5556 {}} {258 0 0-5557 {}} {258 0 0-5558 {}} {258 0 0-5559 {}} {258 0 0-5563 {}}} CYCLES {}}
+set a(0-5555) {NAME slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-4427 XREFS 30285 LOC {1 0.016406775 1 0.267408775 1 0.267408775 3 1.0} PREDS {{259 0 0-5554 {}}} SUCCS {} CYCLES {}}
+set a(0-5556) {NAME slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-4427 XREFS 30286 LOC {1 0.016406775 1 0.267408775 1 0.267408775 3 1.0} PREDS {{258 0 0-5554 {}}} SUCCS {} CYCLES {}}
+set a(0-5557) {NAME slc(FRAME:for:conc.tmp)#2 TYPE READSLICE PAR 0-4427 XREFS 30287 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.7149628} PREDS {{258 0 0-5554 {}}} SUCCS {{258 0 0-5565 {}}} CYCLES {}}
+set a(0-5558) {NAME slc(FRAME:for:conc.tmp)#3 TYPE READSLICE PAR 0-4427 XREFS 30288 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{258 0 0-5554 {}}} SUCCS {{258 0 0-5560 {}}} CYCLES {}}
+set a(0-5559) {NAME FRAME:for:slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-4427 XREFS 30289 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{258 0 0-5554 {}}} SUCCS {{259 0 0-5560 {}}} CYCLES {}}
+set a(0-5560) {NAME FRAME:for:nand#1 TYPE NAND PAR 0-4427 XREFS 30290 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.6985560249999999} PREDS {{258 0 0-5558 {}} {259 0 0-5559 {}}} SUCCS {{259 0 0-5561 {}}} CYCLES {}}
+set a(0-5561) {NAME FRAME:for:exs#22 TYPE SIGNEXTEND PAR 0-4427 XREFS 30291 LOC {1 0.016406775 1 0.619067775 1 0.619067775 1 0.6985560249999999} PREDS {{259 0 0-5560 {}}} SUCCS {{259 0 0-5562 {}}} CYCLES {}}
+set a(0-5562) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 2 NAME FRAME:for:and#4 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-4427 XREFS 30292 LOC {1 0.016406775 1 0.619067775 1 0.619067775 1 0.6354745062638539 1 0.7149627562638539} PREDS {{259 0 0-5561 {}}} SUCCS {{258 0 0-5567 {}}} CYCLES {}}
+set a(0-5563) {NAME FRAME:for:slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-4427 XREFS 30293 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.7149628} PREDS {{258 0 0-5554 {}}} SUCCS {{259 0 0-5564 {}}} CYCLES {}}
+set a(0-5564) {NAME FRAME:for:not#3 TYPE NOT PAR 0-4427 XREFS 30294 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.7149628} PREDS {{259 0 0-5563 {}}} SUCCS {{259 0 0-5565 {}}} CYCLES {}}
+set a(0-5565) {NAME FRAME:for:and#5 TYPE AND PAR 0-4427 XREFS 30295 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.7149628} PREDS {{258 0 0-5557 {}} {259 0 0-5564 {}}} SUCCS {{259 0 0-5566 {}}} CYCLES {}}
+set a(0-5566) {NAME FRAME:for:exs#23 TYPE SIGNEXTEND PAR 0-4427 XREFS 30296 LOC {1 0.016406775 1 0.63547455 1 0.63547455 1 0.7149628} PREDS {{259 0 0-5565 {}}} SUCCS {{259 0 0-5567 {}}} CYCLES {}}
+set a(0-5567) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(2,2) AREA_SCORE 1.46 QUANTITY 1 NAME FRAME:for:or#4 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-4427 XREFS 30297 LOC {1 0.03281355 1 0.63547455 1 0.63547455 1 0.6522169811077388 1 0.7317052311077389} PREDS {{258 0 0-5562 {}} {259 0 0-5566 {}}} SUCCS {{258 0 0-5572 {}} {258 0 0-5577 {}} {258 0 0-5583 {}}} CYCLES {}}
+set a(0-5568) {NAME {regs.operator[]#16:slc(regs.regs(2))} TYPE READSLICE PAR 0-4427 XREFS 30298 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6731774749999999} PREDS {{258 0 0-5502 {}}} SUCCS {{258 0 0-5571 {}}} CYCLES {}}
+set a(0-5569) {NAME {regs.operator[]#16:slc(regs.regs(1))} TYPE READSLICE PAR 0-4427 XREFS 30299 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6731774749999999} PREDS {{258 0 0-5500 {}}} SUCCS {{258 0 0-5571 {}}} CYCLES {}}
+set a(0-5570) {NAME {regs.operator[]#16:slc(regs.regs(0))} TYPE READSLICE PAR 0-4427 XREFS 30300 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6731774749999999} PREDS {{258 0 0-5497 {}}} SUCCS {{259 0 0-5571 {}}} CYCLES {}}
+set a(0-5571) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#16:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-4427 XREFS 30301 LOC {1 0.0230606 1 0.593689225 1 0.593689225 1 0.652216975 1 0.7317052249999999} PREDS {{258 0 0-5508 {}} {258 0 0-5569 {}} {258 0 0-5568 {}} {259 0 0-5570 {}}} SUCCS {{259 0 0-5572 {}}} CYCLES {}}
+set a(0-5572) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#7 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-4427 XREFS 30302 LOC {1 0.08158839999999999 1 0.652217025 1 0.652217025 1 0.8451408874999999 1 0.9246291375} PREDS {{258 0 0-5567 {}} {259 0 0-5571 {}}} SUCCS {{258 0 0-5578 {}}} CYCLES {}}
+set a(0-5573) {NAME {regs.operator[]#17:slc(regs.regs(2))} TYPE READSLICE PAR 0-4427 XREFS 30303 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6731774749999999} PREDS {{258 0 0-5502 {}}} SUCCS {{258 0 0-5576 {}}} CYCLES {}}
+set a(0-5574) {NAME {regs.operator[]#17:slc(regs.regs(1))} TYPE READSLICE PAR 0-4427 XREFS 30304 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6731774749999999} PREDS {{258 0 0-5500 {}}} SUCCS {{258 0 0-5576 {}}} CYCLES {}}
+set a(0-5575) {NAME {regs.operator[]#17:slc(regs.regs(0))} TYPE READSLICE PAR 0-4427 XREFS 30305 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.6731774749999999} PREDS {{258 0 0-5497 {}}} SUCCS {{259 0 0-5576 {}}} CYCLES {}}
+set a(0-5576) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#17:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-4427 XREFS 30306 LOC {1 0.0230606 1 0.593689225 1 0.593689225 1 0.652216975 1 0.7317052249999999} PREDS {{258 0 0-5508 {}} {258 0 0-5574 {}} {258 0 0-5573 {}} {259 0 0-5575 {}}} SUCCS {{259 0 0-5577 {}}} CYCLES {}}
+set a(0-5577) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#8 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-4427 XREFS 30307 LOC {1 0.08158839999999999 1 0.652217025 1 0.652217025 1 0.8451408874999999 1 0.9246291375} PREDS {{258 0 0-5567 {}} {259 0 0-5576 {}}} SUCCS {{259 0 0-5578 {}}} CYCLES {}}
+set a(0-5578) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,1,11,1,12) AREA_SCORE 12.00 QUANTITY 7 NAME FRAME:for:acc#25 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-4427 XREFS 30308 LOC {1 0.274512325 1 0.84514095 1 0.84514095 1 0.9205117063734284 1 0.9999999563734283} PREDS {{258 0 0-5572 {}} {259 0 0-5577 {}}} SUCCS {{258 0 0-5584 {}}} CYCLES {}}
+set a(0-5579) {NAME {regs.operator[]#15:slc(regs.regs(2))} TYPE READSLICE PAR 0-4427 XREFS 30309 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-5502 {}}} SUCCS {{258 0 0-5582 {}}} CYCLES {}}
+set a(0-5580) {NAME {regs.operator[]#15:slc(regs.regs(1))} TYPE READSLICE PAR 0-4427 XREFS 30310 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-5500 {}}} SUCCS {{258 0 0-5582 {}}} CYCLES {}}
+set a(0-5581) {NAME {regs.operator[]#15:slc(regs.regs(0))} TYPE READSLICE PAR 0-4427 XREFS 30311 LOC {1 0.0230606 1 0.57525635 1 0.57525635 1 0.748548275} PREDS {{258 0 0-5497 {}}} SUCCS {{259 0 0-5582 {}}} CYCLES {}}
+set a(0-5582) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 6 NAME {regs.operator[]#15:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-4427 XREFS 30312 LOC {1 0.0230606 1 0.669060025 1 0.669060025 1 0.7275877749999999 1 0.807076025} PREDS {{258 0 0-5508 {}} {258 0 0-5580 {}} {258 0 0-5579 {}} {259 0 0-5581 {}}} SUCCS {{259 0 0-5583 {}}} CYCLES {}}
+set a(0-5583) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 6 NAME FRAME:for:mul#6 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-4427 XREFS 30313 LOC {1 0.08158839999999999 1 0.727587825 1 0.727587825 1 0.9205116874999999 1 0.9999999374999999} PREDS {{258 0 0-5567 {}} {259 0 0-5582 {}}} SUCCS {{259 0 0-5584 {}}} CYCLES {}}
+set a(0-5584) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME FRAME:for:acc#26 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-4427 XREFS 30314 LOC {1 0.34988312499999996 1 0.92051175 1 0.92051175 1 0.9999999534997777 2 0.09165567849977767} PREDS {{258 0 0-5578 {}} {259 0 0-5583 {}}} SUCCS {{258 0 0-5588 {}}} CYCLES {}}
+set a(0-5585) {NAME FRAME:for:slc(in(2).sva) TYPE READSLICE PAR 0-4427 XREFS 30315 LOC {1 0.986011675 1 1.0 1 1.0 2 0.06859512499999999} PREDS {{258 0 0-5493 {}} {258 0 0-4430 {}}} SUCCS {{259 0 0-5586 {}}} CYCLES {}}
+set a(0-5586) {NAME FRAME:for:exs#21 TYPE SIGNEXTEND PAR 0-4427 XREFS 30316 LOC {1 0.986011675 2 0.06859512499999999 2 0.06859512499999999 2 0.06859512499999999} PREDS {{259 0 0-5585 {}}} SUCCS {{259 0 0-5587 {}}} CYCLES {}}
+set a(0-5587) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 2 NAME FRAME:for:mux#12 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30317 LOC {2 0.0 2 0.06859512499999999 2 0.06859512499999999 2 0.0916556875 2 0.0916556875} PREDS {{258 0 0-4450 {}} {262 0 0-5955 {}} {259 0 0-5586 {}}} SUCCS {{259 0 0-5588 {}} {256 0 0-5955 {}}} CYCLES {}}
+set a(0-5588) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,13,1,16) AREA_SCORE 17.00 QUANTITY 3 NAME FRAME:for:acc#22 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-4427 XREFS 30318 LOC {2 0.0230606 2 0.091655725 2 0.091655725 2 0.19755650317154677 2 0.19755650317154677} PREDS {{258 0 0-5584 {}} {259 0 0-5587 {}}} SUCCS {{258 0 0-5868 {}} {258 0 0-5955 {}}} CYCLES {}}
+set a(0-5589) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,1,4) AREA_SCORE 3.00 QUANTITY 11 NAME FRAME:for:acc#16 TYPE ACCU DELAY {0.33 ns} LIBRARY_DELAY {0.33 ns} PAR 0-4427 XREFS 30319 LOC {1 0.016406775 1 0.267408775 1 0.267408775 1 0.2878815350894752 1 0.47538791008947523} PREDS {{258 0 0-5508 {}}} SUCCS {{259 0 0-5590 {}} {258 0 0-5960 {}}} CYCLES {}}
+set a(0-5590) {NAME FRAME:for:asn#2 TYPE ASSIGN PAR 0-4427 XREFS 30320 LOC {1 0.036879575 1 0.287881575 1 0.287881575 1 0.47538795} PREDS {{259 0 0-5589 {}}} SUCCS {{259 0 0-5591 {}}} CYCLES {}}
+set a(0-5591) {NAME FRAME:for:conc#11 TYPE CONCATENATE PAR 0-4427 XREFS 30321 LOC {1 0.036879575 1 0.287881575 1 0.287881575 1 0.47538795} PREDS {{259 0 0-5590 {}}} SUCCS {{259 0 0-5592 {}}} CYCLES {}}
+set a(0-5592) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME FRAME:for:acc TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 30322 LOC {1 0.036879575 1 0.287881575 1 0.287881575 1 0.31512745207082715 1 0.5026338270708272} PREDS {{259 0 0-5591 {}}} SUCCS {{259 0 0-5593 {}}} CYCLES {}}
+set a(0-5593) {NAME FRAME:for:slc TYPE READSLICE PAR 0-4427 XREFS 30323 LOC {1 0.0641255 1 0.3151275 1 0.3151275 1 0.502633875} PREDS {{259 0 0-5592 {}}} SUCCS {{259 0 0-5594 {}}} CYCLES {}}
+set a(0-5594) {NAME FRAME:for:not TYPE NOT PAR 0-4427 XREFS 30324 LOC {1 0.0641255 1 0.3151275 1 0.3151275 1 0.502633875} PREDS {{259 0 0-5593 {}}} SUCCS {{259 0 0-5595 {}} {258 0 0-5945 {}} {258 0 0-5947 {}} {258 0 0-5948 {}} {258 0 0-5959 {}}} CYCLES {}}
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0-5864 {}} {146 0 0-5865 {}} {146 0 0-5866 {}} {146 0 0-5867 {}} {146 0 0-5868 {}} {146 0 0-5869 {}} {146 0 0-5870 {}} {146 0 0-5871 {}} {146 0 0-5872 {}} {146 0 0-5873 {}} {146 0 0-5874 {}} {146 0 0-5875 {}} {146 0 0-5876 {}} {146 0 0-5877 {}} {146 0 0-5878 {}} {146 0 0-5879 {}} {146 0 0-5880 {}} {146 0 0-5881 {}} {146 0 0-5882 {}} {146 0 0-5883 {}} {146 0 0-5884 {}} {146 0 0-5885 {}} {146 0 0-5886 {}} {146 0 0-5887 {}} {146 0 0-5888 {}} {146 0 0-5889 {}} {146 0 0-5890 {}} {146 0 0-5891 {}} {146 0 0-5892 {}} {146 0 0-5893 {}} {146 0 0-5894 {}} {146 0 0-5895 {}} {146 0 0-5896 {}} {146 0 0-5897 {}} {146 0 0-5898 {}} {146 0 0-5899 {}} {146 0 0-5900 {}} {146 0 0-5901 {}} {146 0 0-5902 {}} {146 0 0-5903 {}} {146 0 0-5904 {}} {146 0 0-5905 {}} {146 0 0-5906 {}} {146 0 0-5907 {}} {146 0 0-5908 {}} {146 0 0-5909 {}} {146 0 0-5910 {}} {146 0 0-5911 {}} {146 0 0-5912 {}} {146 0 0-5913 {}} {146 0 0-5914 {}} {146 0 0-5915 {}} {146 0 0-5916 {}} {146 0 0-5917 {}} {146 0 0-5918 {}} {146 0 0-5919 {}} {146 0 0-5920 {}} {146 0 0-5921 {}} {146 0 0-5922 {}} {146 0 0-5923 {}} {146 0 0-5924 {}} {146 0 0-5925 {}} {146 0 0-5926 {}} {146 0 0-5927 {}} {146 0 0-5928 {}} {146 0 0-5929 {}} {146 0 0-5930 {}} {146 0 0-5931 {}} {146 0 0-5932 {}} {146 0 0-5933 {}} {146 0 0-5934 {}} {146 0 0-5935 {}} {146 0 0-5936 {}} {130 0 0-5937 {}} {146 0 0-5938 {}} {146 0 0-5939 {}} {146 0 0-5940 {}} {146 0 0-5941 {}} {146 0 0-5942 {}}} CYCLES {}}
+set a(0-5596) {NAME ACC2:slc(ACC1:acc#125.psp)#5 TYPE READSLICE PAR 0-4427 XREFS 30326 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.766898075} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{258 0 0-5598 {}}} CYCLES {}}
+set a(0-5597) {NAME ACC2:slc(ACC1:acc#125.psp#1)#3 TYPE READSLICE PAR 0-4427 XREFS 30327 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.766898075} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5598 {}}} CYCLES {}}
+set a(0-5598) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 6 NAME ACC2:acc#5 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-4427 XREFS 30328 LOC {1 0.16961555 1 0.5793917 1 0.5793917 1 0.61100253625 1 0.7985089112499999} PREDS {{146 0 0-5595 {}} {258 0 0-5596 {}} {259 0 0-5597 {}}} SUCCS {{259 0 0-5599 {}}} CYCLES {}}
+set a(0-5599) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME ACC1:mul#20 TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-4427 XREFS 30329 LOC {1 0.201226425 1 0.611002575 1 0.611002575 1 0.8124935812499999 1 0.9999999562499999} PREDS {{146 0 0-5595 {}} {259 0 0-5598 {}}} SUCCS {{258 0 0-5827 {}}} CYCLES {}}
+set a(0-5600) {NAME ACC2:slc(ACC1:acc#125.psp)#9 TYPE READSLICE PAR 0-4427 XREFS 30330 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6185303999999999} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{258 0 0-5602 {}}} CYCLES {}}
+set a(0-5601) {NAME ACC2:slc(ACC1:acc#125.psp#1)#9 TYPE READSLICE PAR 0-4427 XREFS 30331 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6185303999999999} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5602 {}}} CYCLES {}}
+set a(0-5602) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 6 NAME ACC2:acc#6 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-4427 XREFS 30332 LOC {1 0.16961555 1 0.431024025 1 0.431024025 1 0.46263486125 1 0.6501412362499999} PREDS {{146 0 0-5595 {}} {258 0 0-5600 {}} {259 0 0-5601 {}}} SUCCS {{259 0 0-5603 {}}} CYCLES {}}
+set a(0-5603) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME ACC1:mul#21 TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-4427 XREFS 30333 LOC {1 0.201226425 1 0.46263489999999996 1 0.46263489999999996 1 0.6641259062499999 1 0.8516322812499999} PREDS {{146 0 0-5595 {}} {259 0 0-5602 {}}} SUCCS {{258 0 0-5607 {}}} CYCLES {}}
+set a(0-5604) {NAME ACC2:slc(ACC1:acc#125.psp)#10 TYPE READSLICE PAR 0-4427 XREFS 30334 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.851632325} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{258 0 0-5607 {}}} CYCLES {}}
+set a(0-5605) {NAME ACC1-3:slc(acc#5.psp)#57 TYPE READSLICE PAR 0-4427 XREFS 30335 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.851632325} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5606 {}}} CYCLES {}}
+set a(0-5606) {NAME ACC1-3:exs#24 TYPE SIGNEXTEND PAR 0-4427 XREFS 30336 LOC {1 0.16961555 1 0.66412595 1 0.66412595 1 0.851632325} PREDS {{146 0 0-5595 {}} {259 0 0-5605 {}}} SUCCS {{259 0 0-5607 {}}} CYCLES {}}
+set a(0-5607) {NAME ACC1:conc TYPE CONCATENATE PAR 0-4427 XREFS 30337 LOC {1 0.402717475 1 0.66412595 1 0.66412595 1 0.851632325} PREDS {{146 0 0-5595 {}} {258 0 0-5604 {}} {258 0 0-5603 {}} {259 0 0-5606 {}}} SUCCS {{258 0 0-5623 {}}} CYCLES {}}
+set a(0-5608) {NAME ACC2:slc(ACC1:acc#125.psp)#3 TYPE READSLICE PAR 0-4427 XREFS 30338 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.5661459} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{258 0 0-5610 {}}} CYCLES {}}
+set a(0-5609) {NAME ACC2:slc(ACC1:acc#125.psp#1)#1 TYPE READSLICE PAR 0-4427 XREFS 30339 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.5661459} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5610 {}}} CYCLES {}}
+set a(0-5610) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 6 NAME ACC2:acc#3 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-4427 XREFS 30340 LOC {1 0.16961555 1 0.378639525 1 0.378639525 1 0.41025036125 1 0.59775673625} PREDS {{146 0 0-5595 {}} {258 0 0-5608 {}} {259 0 0-5609 {}}} SUCCS {{259 0 0-5611 {}}} CYCLES {}}
+set a(0-5611) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME ACC1:mul#18 TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-4427 XREFS 30341 LOC {1 0.201226425 1 0.41025039999999996 1 0.41025039999999996 1 0.61174140625 1 0.79924778125} PREDS {{146 0 0-5595 {}} {259 0 0-5610 {}}} SUCCS {{258 0 0-5622 {}}} CYCLES {}}
+set a(0-5612) {NAME ACC2:slc(ACC1:acc#125.psp)#2 TYPE READSLICE PAR 0-4427 XREFS 30342 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.502633875} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{258 0 0-5614 {}}} CYCLES {}}
+set a(0-5613) {NAME ACC2:slc(ACC1:acc#125.psp#1) TYPE READSLICE PAR 0-4427 XREFS 30343 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.502633875} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5614 {}}} CYCLES {}}
+set a(0-5614) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 6 NAME ACC2:acc TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-4427 XREFS 30344 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.34673833625 1 0.53424471125} PREDS {{146 0 0-5595 {}} {258 0 0-5612 {}} {259 0 0-5613 {}}} SUCCS {{259 0 0-5615 {}}} CYCLES {}}
+set a(0-5615) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME ACC1:mul TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-4427 XREFS 30345 LOC {1 0.201226425 1 0.346738375 1 0.346738375 1 0.54822938125 1 0.7357357562499999} PREDS {{146 0 0-5595 {}} {259 0 0-5614 {}}} SUCCS {{258 0 0-5621 {}}} CYCLES {}}
+set a(0-5616) {NAME ACC2:slc(ACC1:acc#125.psp)#12 TYPE READSLICE PAR 0-4427 XREFS 30346 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.7357357999999999} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{258 0 0-5620 {}}} CYCLES {}}
+set a(0-5617) {NAME ACC2:slc(ACC1:acc#125.psp)#13 TYPE READSLICE PAR 0-4427 XREFS 30347 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.7357357999999999} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{258 0 0-5620 {}}} CYCLES {}}
+set a(0-5618) {NAME ACC1-3:slc(acc#5.psp)#59 TYPE READSLICE PAR 0-4427 XREFS 30348 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.7357357999999999} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5619 {}}} CYCLES {}}
+set a(0-5619) {NAME ACC1-3:exs#25 TYPE SIGNEXTEND PAR 0-4427 XREFS 30349 LOC {1 0.16961555 1 0.5482294249999999 1 0.5482294249999999 1 0.7357357999999999} PREDS {{146 0 0-5595 {}} {259 0 0-5618 {}}} SUCCS {{259 0 0-5620 {}}} CYCLES {}}
+set a(0-5620) {NAME ACC2:conc#6 TYPE CONCATENATE PAR 0-4427 XREFS 30350 LOC {1 0.16961555 1 0.5482294249999999 1 0.5482294249999999 1 0.7357357999999999} PREDS {{146 0 0-5595 {}} {258 0 0-5617 {}} {258 0 0-5616 {}} {259 0 0-5619 {}}} SUCCS {{259 0 0-5621 {}}} CYCLES {}}
+set a(0-5621) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,7) AREA_SCORE 7.28 QUANTITY 1 NAME ACC1:acc#330 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-4427 XREFS 30351 LOC {1 0.402717475 1 0.5482294249999999 1 0.5482294249999999 1 0.6117413984103024 1 0.7992477734103024} PREDS {{146 0 0-5595 {}} {258 0 0-5615 {}} {259 0 0-5620 {}}} SUCCS {{259 0 0-5622 {}}} CYCLES {}}
+set a(0-5622) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#334 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-4427 XREFS 30352 LOC {1 0.46622949999999996 1 0.61174145 1 0.61174145 1 0.6641259027684258 1 0.8516322777684256} PREDS {{146 0 0-5595 {}} {258 0 0-5611 {}} {259 0 0-5621 {}}} SUCCS {{259 0 0-5623 {}}} CYCLES {}}
+set a(0-5623) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,0,10) AREA_SCORE 10.25 QUANTITY 5 NAME ACC1:acc#336 TYPE ACCU DELAY {1.23 ns} LIBRARY_DELAY {1.23 ns} PAR 0-4427 XREFS 30353 LOC {1 0.518614 1 0.66412595 1 0.66412595 1 0.74130943186502 1 0.92881580686502} PREDS {{146 0 0-5595 {}} {258 0 0-5607 {}} {259 0 0-5622 {}}} SUCCS {{258 0 0-5826 {}}} CYCLES {}}
+set a(0-5624) {NAME ACC1-1:slc(acc#5.psp)#52 TYPE READSLICE PAR 0-4427 XREFS 30354 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.8285522249999999} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{258 0 0-5627 {}}} CYCLES {}}
+set a(0-5625) {NAME ACC1-1:slc(acc#5.psp)#53 TYPE READSLICE PAR 0-4427 XREFS 30355 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.8285522249999999} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5626 {}}} CYCLES {}}
+set a(0-5626) {NAME ACC1-1:exs#30 TYPE SIGNEXTEND PAR 0-4427 XREFS 30356 LOC {1 0.16961555 1 0.6410458499999999 1 0.6410458499999999 1 0.8285522249999999} PREDS {{146 0 0-5595 {}} {259 0 0-5625 {}}} SUCCS {{259 0 0-5627 {}}} CYCLES {}}
+set a(0-5627) {NAME ACC1-1:conc#240 TYPE CONCATENATE PAR 0-4427 XREFS 30357 LOC {1 0.16961555 1 0.6410458499999999 1 0.6410458499999999 1 0.8285522249999999} PREDS {{146 0 0-5595 {}} {258 0 0-5624 {}} {259 0 0-5626 {}}} SUCCS {{259 0 0-5628 {}}} CYCLES {}}
+set a(0-5628) {NAME ACC1-1:exs#541 TYPE SIGNEXTEND PAR 0-4427 XREFS 30358 LOC {1 0.16961555 1 0.6410458499999999 1 0.6410458499999999 1 0.8285522249999999} PREDS {{146 0 0-5595 {}} {259 0 0-5627 {}}} SUCCS {{258 0 0-5715 {}}} CYCLES {}}
+set a(0-5629) {NAME ACC1-3:slc(acc#5.psp)#54 TYPE READSLICE PAR 0-4427 XREFS 30359 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5630 {}}} CYCLES {}}
+set a(0-5630) {NAME ACC1-3:exs#28 TYPE SIGNEXTEND PAR 0-4427 XREFS 30360 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5629 {}}} SUCCS {{259 0 0-5631 {}}} CYCLES {}}
+set a(0-5631) {NAME ACC1:conc#641 TYPE CONCATENATE PAR 0-4427 XREFS 30361 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5630 {}}} SUCCS {{258 0 0-5636 {}}} CYCLES {}}
+set a(0-5632) {NAME ACC1-3:slc(acc#5.psp)#68 TYPE READSLICE PAR 0-4427 XREFS 30362 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5633 {}}} CYCLES {}}
+set a(0-5633) {NAME ACC1-3:exs#33 TYPE SIGNEXTEND PAR 0-4427 XREFS 30363 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5632 {}}} SUCCS {{258 0 0-5635 {}}} CYCLES {}}
+set a(0-5634) {NAME ACC2:slc(acc.imod#18) TYPE READSLICE PAR 0-4427 XREFS 30364 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5509 {}}} SUCCS {{259 0 0-5635 {}}} CYCLES {}}
+set a(0-5635) {NAME ACC1:conc#642 TYPE CONCATENATE PAR 0-4427 XREFS 30365 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5633 {}} {259 0 0-5634 {}}} SUCCS {{259 0 0-5636 {}}} CYCLES {}}
+set a(0-5636) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#310 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30366 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-5595 {}} {258 0 0-5631 {}} {259 0 0-5635 {}}} SUCCS {{259 0 0-5637 {}}} CYCLES {}}
+set a(0-5637) {NAME ACC1:slc#97 TYPE READSLICE PAR 0-4427 XREFS 30367 LOC {1 0.417782875 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-5595 {}} {259 0 0-5636 {}}} SUCCS {{258 0 0-5647 {}}} CYCLES {}}
+set a(0-5638) {NAME ACC1-3:slc(acc#5.psp)#71 TYPE READSLICE PAR 0-4427 XREFS 30368 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5639 {}}} CYCLES {}}
+set a(0-5639) {NAME ACC1-3:exs#540 TYPE SIGNEXTEND PAR 0-4427 XREFS 30369 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5638 {}}} SUCCS {{259 0 0-5640 {}}} CYCLES {}}
+set a(0-5640) {NAME ACC1:conc#639 TYPE CONCATENATE PAR 0-4427 XREFS 30370 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5639 {}}} SUCCS {{258 0 0-5645 {}}} CYCLES {}}
+set a(0-5641) {NAME ACC1-3:slc(acc#5.psp)#70 TYPE READSLICE PAR 0-4427 XREFS 30371 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5642 {}}} CYCLES {}}
+set a(0-5642) {NAME ACC1-3:exs#31 TYPE SIGNEXTEND PAR 0-4427 XREFS 30372 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5641 {}}} SUCCS {{258 0 0-5644 {}}} CYCLES {}}
+set a(0-5643) {NAME ACC2:slc(ACC1:acc#110.psp#2)#2 TYPE READSLICE PAR 0-4427 XREFS 30373 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5513 {}}} SUCCS {{259 0 0-5644 {}}} CYCLES {}}
+set a(0-5644) {NAME ACC1:conc#640 TYPE CONCATENATE PAR 0-4427 XREFS 30374 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5642 {}} {259 0 0-5643 {}}} SUCCS {{259 0 0-5645 {}}} CYCLES {}}
+set a(0-5645) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#309 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30375 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-5595 {}} {258 0 0-5640 {}} {259 0 0-5644 {}}} SUCCS {{259 0 0-5646 {}}} CYCLES {}}
+set a(0-5646) {NAME ACC1:slc#96 TYPE READSLICE PAR 0-4427 XREFS 30376 LOC {1 0.3292811 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-5595 {}} {259 0 0-5645 {}}} SUCCS {{259 0 0-5647 {}}} CYCLES {}}
+set a(0-5647) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#319 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30377 LOC {1 0.417782875 1 0.48154284999999997 1 0.48154284999999997 1 0.5290989770708271 1 0.7166053520708271} PREDS {{146 0 0-5595 {}} {258 0 0-5637 {}} {259 0 0-5646 {}}} SUCCS {{258 0 0-5671 {}}} CYCLES {}}
+set a(0-5648) {NAME ACC1-1:slc(acc#5.psp)#67 TYPE READSLICE PAR 0-4427 XREFS 30378 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5649 {}}} CYCLES {}}
+set a(0-5649) {NAME ACC1-1:exs#34 TYPE SIGNEXTEND PAR 0-4427 XREFS 30379 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5648 {}}} SUCCS {{259 0 0-5650 {}}} CYCLES {}}
+set a(0-5650) {NAME ACC1:conc#635 TYPE CONCATENATE PAR 0-4427 XREFS 30380 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5649 {}}} SUCCS {{258 0 0-5655 {}}} CYCLES {}}
+set a(0-5651) {NAME ACC1-1:slc(acc#5.psp)#66 TYPE READSLICE PAR 0-4427 XREFS 30381 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5652 {}}} CYCLES {}}
+set a(0-5652) {NAME ACC1-1:exs#35 TYPE SIGNEXTEND PAR 0-4427 XREFS 30382 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5651 {}}} SUCCS {{258 0 0-5654 {}}} CYCLES {}}
+set a(0-5653) {NAME ACC2:slc(ACC1:acc#110.psp#2) TYPE READSLICE PAR 0-4427 XREFS 30383 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5513 {}}} SUCCS {{259 0 0-5654 {}}} CYCLES {}}
+set a(0-5654) {NAME ACC1:conc#636 TYPE CONCATENATE PAR 0-4427 XREFS 30384 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5652 {}} {259 0 0-5653 {}}} SUCCS {{259 0 0-5655 {}}} CYCLES {}}
+set a(0-5655) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#307 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30385 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-5595 {}} {258 0 0-5650 {}} {259 0 0-5654 {}}} SUCCS {{259 0 0-5656 {}}} CYCLES {}}
+set a(0-5656) {NAME ACC1:slc#94 TYPE READSLICE PAR 0-4427 XREFS 30386 LOC {1 0.3292811 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-5595 {}} {259 0 0-5655 {}}} SUCCS {{258 0 0-5670 {}}} CYCLES {}}
+set a(0-5657) {NAME ACC1-1:slc(acc#5.psp)#65 TYPE READSLICE PAR 0-4427 XREFS 30387 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5658 {}}} CYCLES {}}
+set a(0-5658) {NAME ACC1-1:exs#22 TYPE SIGNEXTEND PAR 0-4427 XREFS 30388 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5657 {}}} SUCCS {{259 0 0-5659 {}}} CYCLES {}}
+set a(0-5659) {NAME ACC1:conc#633 TYPE CONCATENATE PAR 0-4427 XREFS 30389 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5658 {}}} SUCCS {{258 0 0-5668 {}}} CYCLES {}}
+set a(0-5660) {NAME ACC1-1:slc(acc#5.psp)#64 TYPE READSLICE PAR 0-4427 XREFS 30390 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5661 {}}} CYCLES {}}
+set a(0-5661) {NAME ACC1-1:exs#23 TYPE SIGNEXTEND PAR 0-4427 XREFS 30391 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5660 {}}} SUCCS {{258 0 0-5667 {}}} CYCLES {}}
+set a(0-5662) {NAME ACC1-3:slc(acc#5.psp)#51 TYPE READSLICE PAR 0-4427 XREFS 30392 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{258 0 0-5666 {}}} CYCLES {}}
+set a(0-5663) {NAME ACC1-3:slc(acc.imod#7)#1 TYPE READSLICE PAR 0-4427 XREFS 30393 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5495 {}}} SUCCS {{259 0 0-5664 {}}} CYCLES {}}
+set a(0-5664) {NAME ACC1-3:not#60 TYPE NOT PAR 0-4427 XREFS 30394 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5663 {}}} SUCCS {{258 0 0-5666 {}}} CYCLES {}}
+set a(0-5665) {NAME ACC1-3:slc(acc.imod#7)#2 TYPE READSLICE PAR 0-4427 XREFS 30395 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5495 {}}} SUCCS {{259 0 0-5666 {}}} CYCLES {}}
+set a(0-5666) {NAME ACC1-3:and#3 TYPE AND PAR 0-4427 XREFS 30396 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5664 {}} {258 0 0-5662 {}} {259 0 0-5665 {}}} SUCCS {{259 0 0-5667 {}}} CYCLES {}}
+set a(0-5667) {NAME ACC1:conc#634 TYPE CONCATENATE PAR 0-4427 XREFS 30397 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5661 {}} {259 0 0-5666 {}}} SUCCS {{259 0 0-5668 {}}} CYCLES {}}
+set a(0-5668) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#306 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30398 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-5595 {}} {258 0 0-5659 {}} {259 0 0-5667 {}}} SUCCS {{259 0 0-5669 {}}} CYCLES {}}
+set a(0-5669) {NAME ACC1:slc#93 TYPE READSLICE PAR 0-4427 XREFS 30399 LOC {1 0.4450288 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-5595 {}} {259 0 0-5668 {}}} SUCCS {{259 0 0-5670 {}}} CYCLES {}}
+set a(0-5670) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#318 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30400 LOC {1 0.4450288 1 0.48154284999999997 1 0.48154284999999997 1 0.5290989770708271 1 0.7166053520708271} PREDS {{146 0 0-5595 {}} {258 0 0-5656 {}} {259 0 0-5669 {}}} SUCCS {{259 0 0-5671 {}}} CYCLES {}}
+set a(0-5671) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#325 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-4427 XREFS 30401 LOC {1 0.492584975 1 0.529099025 1 0.529099025 1 0.5824460451789504 1 0.7699524201789505} PREDS {{146 0 0-5595 {}} {258 0 0-5647 {}} {259 0 0-5670 {}}} SUCCS {{258 0 0-5714 {}}} CYCLES {}}
+set a(0-5672) {NAME ACC1-1:slc(acc#5.psp)#63 TYPE READSLICE PAR 0-4427 XREFS 30402 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5673 {}}} CYCLES {}}
+set a(0-5673) {NAME ACC1-1:exs#18 TYPE SIGNEXTEND PAR 0-4427 XREFS 30403 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5672 {}}} SUCCS {{259 0 0-5674 {}}} CYCLES {}}
+set a(0-5674) {NAME ACC1:conc#631 TYPE CONCATENATE PAR 0-4427 XREFS 30404 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5673 {}}} SUCCS {{258 0 0-5682 {}}} CYCLES {}}
+set a(0-5675) {NAME ACC1-1:slc(acc#5.psp)#62 TYPE READSLICE PAR 0-4427 XREFS 30405 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5676 {}}} CYCLES {}}
+set a(0-5676) {NAME ACC1-1:exs#19 TYPE SIGNEXTEND PAR 0-4427 XREFS 30406 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5675 {}}} SUCCS {{258 0 0-5681 {}}} CYCLES {}}
+set a(0-5677) {NAME ACC1-3:slc(acc.imod#7) TYPE READSLICE PAR 0-4427 XREFS 30407 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5495 {}}} SUCCS {{258 0 0-5680 {}}} CYCLES {}}
+set a(0-5678) {NAME ACC1-3:slc(acc#5.psp)#50 TYPE READSLICE PAR 0-4427 XREFS 30408 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5679 {}}} CYCLES {}}
+set a(0-5679) {NAME ACC1-3:not#59 TYPE NOT PAR 0-4427 XREFS 30409 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5678 {}}} SUCCS {{259 0 0-5680 {}}} CYCLES {}}
+set a(0-5680) {NAME ACC1-3:nand#1 TYPE NAND PAR 0-4427 XREFS 30410 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5677 {}} {259 0 0-5679 {}}} SUCCS {{259 0 0-5681 {}}} CYCLES {}}
+set a(0-5681) {NAME ACC1:conc#632 TYPE CONCATENATE PAR 0-4427 XREFS 30411 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5676 {}} {259 0 0-5680 {}}} SUCCS {{259 0 0-5682 {}}} CYCLES {}}
+set a(0-5682) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#305 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30412 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-5595 {}} {258 0 0-5674 {}} {259 0 0-5681 {}}} SUCCS {{259 0 0-5683 {}}} CYCLES {}}
+set a(0-5683) {NAME ACC1:slc#92 TYPE READSLICE PAR 0-4427 XREFS 30413 LOC {1 0.4450288 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-5595 {}} {259 0 0-5682 {}}} SUCCS {{258 0 0-5693 {}}} CYCLES {}}
+set a(0-5684) {NAME ACC1-1:slc(acc#5.psp)#61 TYPE READSLICE PAR 0-4427 XREFS 30414 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5685 {}}} CYCLES {}}
+set a(0-5685) {NAME ACC1-1:exs#20 TYPE SIGNEXTEND PAR 0-4427 XREFS 30415 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5684 {}}} SUCCS {{259 0 0-5686 {}}} CYCLES {}}
+set a(0-5686) {NAME ACC1:conc#629 TYPE CONCATENATE PAR 0-4427 XREFS 30416 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5685 {}}} SUCCS {{258 0 0-5691 {}}} CYCLES {}}
+set a(0-5687) {NAME ACC1-1:slc(acc#5.psp)#60 TYPE READSLICE PAR 0-4427 XREFS 30417 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5688 {}}} CYCLES {}}
+set a(0-5688) {NAME ACC1-1:exs#21 TYPE SIGNEXTEND PAR 0-4427 XREFS 30418 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5687 {}}} SUCCS {{258 0 0-5690 {}}} CYCLES {}}
+set a(0-5689) {NAME ACC2:slc(acc.imod#6) TYPE READSLICE PAR 0-4427 XREFS 30419 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5494 {}}} SUCCS {{259 0 0-5690 {}}} CYCLES {}}
+set a(0-5690) {NAME ACC1:conc#630 TYPE CONCATENATE PAR 0-4427 XREFS 30420 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5688 {}} {259 0 0-5689 {}}} SUCCS {{259 0 0-5691 {}}} CYCLES {}}
+set a(0-5691) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#304 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30421 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-5595 {}} {258 0 0-5686 {}} {259 0 0-5690 {}}} SUCCS {{259 0 0-5692 {}}} CYCLES {}}
+set a(0-5692) {NAME ACC1:slc#91 TYPE READSLICE PAR 0-4427 XREFS 30422 LOC {1 0.417782875 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-5595 {}} {259 0 0-5691 {}}} SUCCS {{259 0 0-5693 {}}} CYCLES {}}
+set a(0-5693) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#317 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30423 LOC {1 0.4450288 1 0.48154284999999997 1 0.48154284999999997 1 0.5290989770708271 1 0.7166053520708271} PREDS {{146 0 0-5595 {}} {258 0 0-5683 {}} {259 0 0-5692 {}}} SUCCS {{258 0 0-5713 {}}} CYCLES {}}
+set a(0-5694) {NAME ACC1-1:slc(acc#5.psp)#59 TYPE READSLICE PAR 0-4427 XREFS 30424 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5695 {}}} CYCLES {}}
+set a(0-5695) {NAME ACC1-1:exs#25 TYPE SIGNEXTEND PAR 0-4427 XREFS 30425 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5694 {}}} SUCCS {{259 0 0-5696 {}}} CYCLES {}}
+set a(0-5696) {NAME ACC1:conc#627 TYPE CONCATENATE PAR 0-4427 XREFS 30426 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5695 {}}} SUCCS {{258 0 0-5701 {}}} CYCLES {}}
+set a(0-5697) {NAME ACC1-1:slc(acc#5.psp)#58 TYPE READSLICE PAR 0-4427 XREFS 30427 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5698 {}}} CYCLES {}}
+set a(0-5698) {NAME ACC1-1:exs#26 TYPE SIGNEXTEND PAR 0-4427 XREFS 30428 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5697 {}}} SUCCS {{258 0 0-5700 {}}} CYCLES {}}
+set a(0-5699) {NAME ACC2:slc(ACC1:acc#110.psp#1)#2 TYPE READSLICE PAR 0-4427 XREFS 30429 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5505 {}}} SUCCS {{259 0 0-5700 {}}} CYCLES {}}
+set a(0-5700) {NAME ACC1:conc#628 TYPE CONCATENATE PAR 0-4427 XREFS 30430 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5698 {}} {259 0 0-5699 {}}} SUCCS {{259 0 0-5701 {}}} CYCLES {}}
+set a(0-5701) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#303 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30431 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-5595 {}} {258 0 0-5696 {}} {259 0 0-5700 {}}} SUCCS {{259 0 0-5702 {}}} CYCLES {}}
+set a(0-5702) {NAME ACC1:slc#90 TYPE READSLICE PAR 0-4427 XREFS 30432 LOC {1 0.3292811 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-5595 {}} {259 0 0-5701 {}}} SUCCS {{258 0 0-5712 {}}} CYCLES {}}
+set a(0-5703) {NAME ACC1-1:slc(acc#5.psp)#57 TYPE READSLICE PAR 0-4427 XREFS 30433 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5704 {}}} CYCLES {}}
+set a(0-5704) {NAME ACC1-1:exs#24 TYPE SIGNEXTEND PAR 0-4427 XREFS 30434 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5703 {}}} SUCCS {{259 0 0-5705 {}}} CYCLES {}}
+set a(0-5705) {NAME ACC1:conc#625 TYPE CONCATENATE PAR 0-4427 XREFS 30435 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5704 {}}} SUCCS {{258 0 0-5710 {}}} CYCLES {}}
+set a(0-5706) {NAME ACC1-1:slc(acc#5.psp)#56 TYPE READSLICE PAR 0-4427 XREFS 30436 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5707 {}}} CYCLES {}}
+set a(0-5707) {NAME ACC1-1:exs#29 TYPE SIGNEXTEND PAR 0-4427 XREFS 30437 LOC {1 0.16961555 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {259 0 0-5706 {}}} SUCCS {{258 0 0-5709 {}}} CYCLES {}}
+set a(0-5708) {NAME ACC2:slc(ACC1:acc#110.psp#1)#1 TYPE READSLICE PAR 0-4427 XREFS 30438 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5505 {}}} SUCCS {{259 0 0-5709 {}}} CYCLES {}}
+set a(0-5709) {NAME ACC1:conc#626 TYPE CONCATENATE PAR 0-4427 XREFS 30439 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.62149305} PREDS {{146 0 0-5595 {}} {258 0 0-5707 {}} {259 0 0-5708 {}}} SUCCS {{259 0 0-5710 {}}} CYCLES {}}
+set a(0-5710) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#302 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30440 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.48154280207082717 1 0.6690491770708271} PREDS {{146 0 0-5595 {}} {258 0 0-5705 {}} {259 0 0-5709 {}}} SUCCS {{259 0 0-5711 {}}} CYCLES {}}
+set a(0-5711) {NAME ACC1:slc#89 TYPE READSLICE PAR 0-4427 XREFS 30441 LOC {1 0.3292811 1 0.48154284999999997 1 0.48154284999999997 1 0.669049225} PREDS {{146 0 0-5595 {}} {259 0 0-5710 {}}} SUCCS {{259 0 0-5712 {}}} CYCLES {}}
+set a(0-5712) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#316 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30442 LOC {1 0.3292811 1 0.48154284999999997 1 0.48154284999999997 1 0.5290989770708271 1 0.7166053520708271} PREDS {{146 0 0-5595 {}} {258 0 0-5702 {}} {259 0 0-5711 {}}} SUCCS {{259 0 0-5713 {}}} CYCLES {}}
+set a(0-5713) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#324 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-4427 XREFS 30443 LOC {1 0.492584975 1 0.529099025 1 0.529099025 1 0.5824460451789504 1 0.7699524201789505} PREDS {{146 0 0-5595 {}} {258 0 0-5693 {}} {259 0 0-5712 {}}} SUCCS {{259 0 0-5714 {}}} CYCLES {}}
+set a(0-5714) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 2 NAME ACC1:acc#328 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-4427 XREFS 30444 LOC {1 0.54593205 1 0.5824461 1 0.5824461 1 0.641045809496936 1 0.828552184496936} PREDS {{146 0 0-5595 {}} {258 0 0-5671 {}} {259 0 0-5713 {}}} SUCCS {{259 0 0-5715 {}}} CYCLES {}}
+set a(0-5715) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#332 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-4427 XREFS 30445 LOC {1 0.6045318 1 0.6410458499999999 1 0.6410458499999999 1 0.6889249129329679 1 0.8764312879329679} PREDS {{146 0 0-5595 {}} {258 0 0-5628 {}} {259 0 0-5714 {}}} SUCCS {{258 0 0-5825 {}}} CYCLES {}}
+set a(0-5716) {NAME ACC1-1:slc(acc#5.psp)#55 TYPE READSLICE PAR 0-4427 XREFS 30446 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5717 {}}} CYCLES {}}
+set a(0-5717) {NAME ACC1-1:exs#27 TYPE SIGNEXTEND PAR 0-4427 XREFS 30447 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5716 {}}} SUCCS {{259 0 0-5718 {}}} CYCLES {}}
+set a(0-5718) {NAME ACC1:conc#623 TYPE CONCATENATE PAR 0-4427 XREFS 30448 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5717 {}}} SUCCS {{258 0 0-5723 {}}} CYCLES {}}
+set a(0-5719) {NAME ACC1-1:slc(acc#5.psp)#54 TYPE READSLICE PAR 0-4427 XREFS 30449 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5720 {}}} CYCLES {}}
+set a(0-5720) {NAME ACC1-1:exs#28 TYPE SIGNEXTEND PAR 0-4427 XREFS 30450 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5719 {}}} SUCCS {{258 0 0-5722 {}}} CYCLES {}}
+set a(0-5721) {NAME ACC2:slc(ACC1:acc#110.psp#1) TYPE READSLICE PAR 0-4427 XREFS 30451 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5505 {}}} SUCCS {{259 0 0-5722 {}}} CYCLES {}}
+set a(0-5722) {NAME ACC1:conc#624 TYPE CONCATENATE PAR 0-4427 XREFS 30452 LOC {1 0.281724925 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5720 {}} {259 0 0-5721 {}}} SUCCS {{259 0 0-5723 {}}} CYCLES {}}
+set a(0-5723) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#301 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30453 LOC {1 0.281724925 1 0.43866402499999996 1 0.43866402499999996 1 0.48622015207082714 1 0.6737265270708271} PREDS {{146 0 0-5595 {}} {258 0 0-5718 {}} {259 0 0-5722 {}}} SUCCS {{259 0 0-5724 {}}} CYCLES {}}
+set a(0-5724) {NAME ACC1:slc#88 TYPE READSLICE PAR 0-4427 XREFS 30454 LOC {1 0.3292811 1 0.4862202 1 0.4862202 1 0.673726575} PREDS {{146 0 0-5595 {}} {259 0 0-5723 {}}} SUCCS {{258 0 0-5734 {}}} CYCLES {}}
+set a(0-5725) {NAME ACC1-1:slc(acc#5.psp)#68 TYPE READSLICE PAR 0-4427 XREFS 30455 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5726 {}}} CYCLES {}}
+set a(0-5726) {NAME ACC1-1:exs#33 TYPE SIGNEXTEND PAR 0-4427 XREFS 30456 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5725 {}}} SUCCS {{259 0 0-5727 {}}} CYCLES {}}
+set a(0-5727) {NAME ACC1:conc#621 TYPE CONCATENATE PAR 0-4427 XREFS 30457 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5726 {}}} SUCCS {{258 0 0-5732 {}}} CYCLES {}}
+set a(0-5728) {NAME ACC1-1:slc(acc#5.psp)#71 TYPE READSLICE PAR 0-4427 XREFS 30458 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5729 {}}} CYCLES {}}
+set a(0-5729) {NAME ACC1-1:exs#540 TYPE SIGNEXTEND PAR 0-4427 XREFS 30459 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5728 {}}} SUCCS {{258 0 0-5731 {}}} CYCLES {}}
+set a(0-5730) {NAME ACC2:slc(ACC1:acc#125.psp#1)#7 TYPE READSLICE PAR 0-4427 XREFS 30460 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5731 {}}} CYCLES {}}
+set a(0-5731) {NAME ACC1:conc#622 TYPE CONCATENATE PAR 0-4427 XREFS 30461 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5729 {}} {259 0 0-5730 {}}} SUCCS {{259 0 0-5732 {}}} CYCLES {}}
+set a(0-5732) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#300 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30462 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.48622015207082714 1 0.6737265270708271} PREDS {{146 0 0-5595 {}} {258 0 0-5727 {}} {259 0 0-5731 {}}} SUCCS {{259 0 0-5733 {}}} CYCLES {}}
+set a(0-5733) {NAME ACC1:slc#87 TYPE READSLICE PAR 0-4427 XREFS 30463 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.673726575} PREDS {{146 0 0-5595 {}} {259 0 0-5732 {}}} SUCCS {{259 0 0-5734 {}}} CYCLES {}}
+set a(0-5734) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#315 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30464 LOC {1 0.3292811 1 0.4862202 1 0.4862202 1 0.5337763270708271 1 0.7212827020708271} PREDS {{146 0 0-5595 {}} {258 0 0-5724 {}} {259 0 0-5733 {}}} SUCCS {{258 0 0-5754 {}}} CYCLES {}}
+set a(0-5735) {NAME ACC1-1:slc(acc#5.psp)#70 TYPE READSLICE PAR 0-4427 XREFS 30465 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5736 {}}} CYCLES {}}
+set a(0-5736) {NAME ACC1-1:exs#31 TYPE SIGNEXTEND PAR 0-4427 XREFS 30466 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5735 {}}} SUCCS {{259 0 0-5737 {}}} CYCLES {}}
+set a(0-5737) {NAME ACC1:conc#619 TYPE CONCATENATE PAR 0-4427 XREFS 30467 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5736 {}}} SUCCS {{258 0 0-5742 {}}} CYCLES {}}
+set a(0-5738) {NAME ACC1-1:slc(acc#5.psp)#69 TYPE READSLICE PAR 0-4427 XREFS 30468 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5739 {}}} CYCLES {}}
+set a(0-5739) {NAME ACC1-1:exs#32 TYPE SIGNEXTEND PAR 0-4427 XREFS 30469 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5738 {}}} SUCCS {{258 0 0-5741 {}}} CYCLES {}}
+set a(0-5740) {NAME ACC2:slc(ACC1:acc#125.psp#1)#6 TYPE READSLICE PAR 0-4427 XREFS 30470 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5741 {}}} CYCLES {}}
+set a(0-5741) {NAME ACC1:conc#620 TYPE CONCATENATE PAR 0-4427 XREFS 30471 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5739 {}} {259 0 0-5740 {}}} SUCCS {{259 0 0-5742 {}}} CYCLES {}}
+set a(0-5742) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#299 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30472 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.48622015207082714 1 0.6737265270708271} PREDS {{146 0 0-5595 {}} {258 0 0-5737 {}} {259 0 0-5741 {}}} SUCCS {{259 0 0-5743 {}}} CYCLES {}}
+set a(0-5743) {NAME ACC1:slc#86 TYPE READSLICE PAR 0-4427 XREFS 30473 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.673726575} PREDS {{146 0 0-5595 {}} {259 0 0-5742 {}}} SUCCS {{258 0 0-5753 {}}} CYCLES {}}
+set a(0-5744) {NAME ACC1-3:slc(acc#5.psp)#63 TYPE READSLICE PAR 0-4427 XREFS 30474 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5745 {}}} CYCLES {}}
+set a(0-5745) {NAME ACC1-3:exs#18 TYPE SIGNEXTEND PAR 0-4427 XREFS 30475 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5744 {}}} SUCCS {{259 0 0-5746 {}}} CYCLES {}}
+set a(0-5746) {NAME ACC1:conc#617 TYPE CONCATENATE PAR 0-4427 XREFS 30476 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5745 {}}} SUCCS {{258 0 0-5751 {}}} CYCLES {}}
+set a(0-5747) {NAME ACC1-3:slc(acc#5.psp)#62 TYPE READSLICE PAR 0-4427 XREFS 30477 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5748 {}}} CYCLES {}}
+set a(0-5748) {NAME ACC1-3:exs#19 TYPE SIGNEXTEND PAR 0-4427 XREFS 30478 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5747 {}}} SUCCS {{258 0 0-5750 {}}} CYCLES {}}
+set a(0-5749) {NAME ACC2:slc(ACC1:acc#125.psp#1)#5 TYPE READSLICE PAR 0-4427 XREFS 30479 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5750 {}}} CYCLES {}}
+set a(0-5750) {NAME ACC1:conc#618 TYPE CONCATENATE PAR 0-4427 XREFS 30480 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5748 {}} {259 0 0-5749 {}}} SUCCS {{259 0 0-5751 {}}} CYCLES {}}
+set a(0-5751) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#298 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30481 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.48622015207082714 1 0.6737265270708271} PREDS {{146 0 0-5595 {}} {258 0 0-5746 {}} {259 0 0-5750 {}}} SUCCS {{259 0 0-5752 {}}} CYCLES {}}
+set a(0-5752) {NAME ACC1:slc#85 TYPE READSLICE PAR 0-4427 XREFS 30482 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.673726575} PREDS {{146 0 0-5595 {}} {259 0 0-5751 {}}} SUCCS {{259 0 0-5753 {}}} CYCLES {}}
+set a(0-5753) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#314 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30483 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.5337763270708271 1 0.7212827020708271} PREDS {{146 0 0-5595 {}} {258 0 0-5743 {}} {259 0 0-5752 {}}} SUCCS {{259 0 0-5754 {}}} CYCLES {}}
+set a(0-5754) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#323 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-4427 XREFS 30484 LOC {1 0.37683727499999997 1 0.533776375 1 0.533776375 1 0.5871233951789505 1 0.7746297701789504} PREDS {{146 0 0-5595 {}} {258 0 0-5734 {}} {259 0 0-5753 {}}} SUCCS {{258 0 0-5800 {}}} CYCLES {}}
+set a(0-5755) {NAME ACC1-3:slc(acc#5.psp)#67 TYPE READSLICE PAR 0-4427 XREFS 30485 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5756 {}}} CYCLES {}}
+set a(0-5756) {NAME ACC1-3:exs#34 TYPE SIGNEXTEND PAR 0-4427 XREFS 30486 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5755 {}}} SUCCS {{259 0 0-5757 {}}} CYCLES {}}
+set a(0-5757) {NAME ACC1:conc#615 TYPE CONCATENATE PAR 0-4427 XREFS 30487 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5756 {}}} SUCCS {{258 0 0-5762 {}}} CYCLES {}}
+set a(0-5758) {NAME ACC1-3:slc(acc#5.psp)#66 TYPE READSLICE PAR 0-4427 XREFS 30488 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5759 {}}} CYCLES {}}
+set a(0-5759) {NAME ACC1-3:exs#35 TYPE SIGNEXTEND PAR 0-4427 XREFS 30489 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5758 {}}} SUCCS {{258 0 0-5761 {}}} CYCLES {}}
+set a(0-5760) {NAME ACC2:slc(ACC1:acc#125.psp#1)#4 TYPE READSLICE PAR 0-4427 XREFS 30490 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5761 {}}} CYCLES {}}
+set a(0-5761) {NAME ACC1:conc#616 TYPE CONCATENATE PAR 0-4427 XREFS 30491 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5759 {}} {259 0 0-5760 {}}} SUCCS {{259 0 0-5762 {}}} CYCLES {}}
+set a(0-5762) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#297 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30492 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.48622015207082714 1 0.6737265270708271} PREDS {{146 0 0-5595 {}} {258 0 0-5757 {}} {259 0 0-5761 {}}} SUCCS {{259 0 0-5763 {}}} CYCLES {}}
+set a(0-5763) {NAME ACC1:slc#84 TYPE READSLICE PAR 0-4427 XREFS 30493 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.673726575} PREDS {{146 0 0-5595 {}} {259 0 0-5762 {}}} SUCCS {{258 0 0-5773 {}}} CYCLES {}}
+set a(0-5764) {NAME ACC1-3:slc(acc#5.psp)#65 TYPE READSLICE PAR 0-4427 XREFS 30494 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5765 {}}} CYCLES {}}
+set a(0-5765) {NAME ACC1-3:exs#22 TYPE SIGNEXTEND PAR 0-4427 XREFS 30495 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5764 {}}} SUCCS {{259 0 0-5766 {}}} CYCLES {}}
+set a(0-5766) {NAME ACC1:conc#613 TYPE CONCATENATE PAR 0-4427 XREFS 30496 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5765 {}}} SUCCS {{258 0 0-5771 {}}} CYCLES {}}
+set a(0-5767) {NAME ACC1-3:slc(acc#5.psp)#64 TYPE READSLICE PAR 0-4427 XREFS 30497 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5768 {}}} CYCLES {}}
+set a(0-5768) {NAME ACC1-3:exs#23 TYPE SIGNEXTEND PAR 0-4427 XREFS 30498 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {259 0 0-5767 {}}} SUCCS {{258 0 0-5770 {}}} CYCLES {}}
+set a(0-5769) {NAME ACC2:slc(ACC1:acc#125.psp)#1 TYPE READSLICE PAR 0-4427 XREFS 30499 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5770 {}}} CYCLES {}}
+set a(0-5770) {NAME ACC1:conc#614 TYPE CONCATENATE PAR 0-4427 XREFS 30500 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.6261704} PREDS {{146 0 0-5595 {}} {258 0 0-5768 {}} {259 0 0-5769 {}}} SUCCS {{259 0 0-5771 {}}} CYCLES {}}
+set a(0-5771) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#296 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30501 LOC {1 0.16961555 1 0.43866402499999996 1 0.43866402499999996 1 0.48622015207082714 1 0.6737265270708271} PREDS {{146 0 0-5595 {}} {258 0 0-5766 {}} {259 0 0-5770 {}}} SUCCS {{259 0 0-5772 {}}} CYCLES {}}
+set a(0-5772) {NAME ACC1:slc#83 TYPE READSLICE PAR 0-4427 XREFS 30502 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.673726575} PREDS {{146 0 0-5595 {}} {259 0 0-5771 {}}} SUCCS {{259 0 0-5773 {}}} CYCLES {}}
+set a(0-5773) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#313 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30503 LOC {1 0.21717172499999998 1 0.4862202 1 0.4862202 1 0.5337763270708271 1 0.7212827020708271} PREDS {{146 0 0-5595 {}} {258 0 0-5763 {}} {259 0 0-5772 {}}} SUCCS {{258 0 0-5799 {}}} CYCLES {}}
+set a(0-5774) {NAME ACC2:slc(ACC1:acc#125.psp)#6 TYPE READSLICE PAR 0-4427 XREFS 30504 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6203795} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{258 0 0-5776 {}}} CYCLES {}}
+set a(0-5775) {NAME ACC2:slc(ACC1:acc#125.psp)#7 TYPE READSLICE PAR 0-4427 XREFS 30505 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6203795} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5776 {}}} CYCLES {}}
+set a(0-5776) {NAME ACC2:conc TYPE CONCATENATE PAR 0-4427 XREFS 30506 LOC {1 0.16961555 1 0.43287312499999997 1 0.43287312499999997 1 0.6203795} PREDS {{146 0 0-5595 {}} {258 0 0-5774 {}} {259 0 0-5775 {}}} SUCCS {{259 0 0-5777 {}}} CYCLES {}}
+set a(0-5777) {NAME ACC1:conc#611 TYPE CONCATENATE PAR 0-4427 XREFS 30507 LOC {1 0.16961555 1 0.43287312499999997 1 0.43287312499999997 1 0.6203795} PREDS {{146 0 0-5595 {}} {259 0 0-5776 {}}} SUCCS {{258 0 0-5783 {}}} CYCLES {}}
+set a(0-5778) {NAME ACC2:slc(ACC1:acc#125.psp#1)#8 TYPE READSLICE PAR 0-4427 XREFS 30508 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6203795} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{258 0 0-5780 {}}} CYCLES {}}
+set a(0-5779) {NAME ACC2:slc(ACC1:acc#125.psp)#8 TYPE READSLICE PAR 0-4427 XREFS 30509 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6203795} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5780 {}}} CYCLES {}}
+set a(0-5780) {NAME ACC2:conc#1 TYPE CONCATENATE PAR 0-4427 XREFS 30510 LOC {1 0.16961555 1 0.43287312499999997 1 0.43287312499999997 1 0.6203795} PREDS {{146 0 0-5595 {}} {258 0 0-5778 {}} {259 0 0-5779 {}}} SUCCS {{258 0 0-5782 {}}} CYCLES {}}
+set a(0-5781) {NAME ACC2:slc(ACC1:acc#125.psp) TYPE READSLICE PAR 0-4427 XREFS 30511 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.6203795} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5782 {}}} CYCLES {}}
+set a(0-5782) {NAME ACC1:conc#612 TYPE CONCATENATE PAR 0-4427 XREFS 30512 LOC {1 0.16961555 1 0.43287312499999997 1 0.43287312499999997 1 0.6203795} PREDS {{146 0 0-5595 {}} {258 0 0-5780 {}} {259 0 0-5781 {}}} SUCCS {{259 0 0-5783 {}}} CYCLES {}}
+set a(0-5783) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME ACC1:acc#295 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30513 LOC {1 0.16961555 1 0.43287312499999997 1 0.43287312499999997 1 0.48042925207082715 1 0.6679356270708271} PREDS {{146 0 0-5595 {}} {258 0 0-5777 {}} {259 0 0-5782 {}}} SUCCS {{259 0 0-5784 {}}} CYCLES {}}
+set a(0-5784) {NAME ACC1:slc#82 TYPE READSLICE PAR 0-4427 XREFS 30514 LOC {1 0.21717172499999998 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-5595 {}} {259 0 0-5783 {}}} SUCCS {{259 0 0-5785 {}}} CYCLES {}}
+set a(0-5785) {NAME ACC1:conc#645 TYPE CONCATENATE PAR 0-4427 XREFS 30515 LOC {1 0.21717172499999998 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-5595 {}} {259 0 0-5784 {}}} SUCCS {{258 0 0-5797 {}}} CYCLES {}}
+set a(0-5786) {NAME ACC2:slc(ACC1:acc#110.psp#1)#3 TYPE READSLICE PAR 0-4427 XREFS 30516 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.667935675} PREDS {{146 0 0-5595 {}} {258 0 0-5505 {}}} SUCCS {{259 0 0-5787 {}}} CYCLES {}}
+set a(0-5787) {NAME ACC2:not TYPE NOT PAR 0-4427 XREFS 30517 LOC {1 0.281724925 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-5595 {}} {259 0 0-5786 {}}} SUCCS {{258 0 0-5790 {}}} CYCLES {}}
+set a(0-5788) {NAME ACC2:slc(acc.imod#6)#1 TYPE READSLICE PAR 0-4427 XREFS 30518 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.667935675} PREDS {{146 0 0-5595 {}} {258 0 0-5494 {}}} SUCCS {{259 0 0-5789 {}}} CYCLES {}}
+set a(0-5789) {NAME ACC2:not#1 TYPE NOT PAR 0-4427 XREFS 30519 LOC {1 0.37022669999999996 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-5595 {}} {259 0 0-5788 {}}} SUCCS {{259 0 0-5790 {}}} CYCLES {}}
+set a(0-5790) {NAME ACC2:conc#2 TYPE CONCATENATE PAR 0-4427 XREFS 30520 LOC {1 0.37022669999999996 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-5595 {}} {258 0 0-5787 {}} {259 0 0-5789 {}}} SUCCS {{258 0 0-5796 {}}} CYCLES {}}
+set a(0-5791) {NAME ACC1-1:slc(acc#5.psp)#51 TYPE READSLICE PAR 0-4427 XREFS 30521 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.667935675} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{258 0 0-5795 {}}} CYCLES {}}
+set a(0-5792) {NAME ACC1-1:slc(acc.imod#7)#1 TYPE READSLICE PAR 0-4427 XREFS 30522 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-5595 {}} {258 0 0-5510 {}}} SUCCS {{259 0 0-5793 {}}} CYCLES {}}
+set a(0-5793) {NAME ACC1-1:not#60 TYPE NOT PAR 0-4427 XREFS 30523 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-5595 {}} {259 0 0-5792 {}}} SUCCS {{258 0 0-5795 {}}} CYCLES {}}
+set a(0-5794) {NAME ACC1-1:slc(acc.imod#7)#2 TYPE READSLICE PAR 0-4427 XREFS 30524 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-5595 {}} {258 0 0-5510 {}}} SUCCS {{259 0 0-5795 {}}} CYCLES {}}
+set a(0-5795) {NAME ACC1-1:and#3 TYPE AND PAR 0-4427 XREFS 30525 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-5595 {}} {258 0 0-5793 {}} {258 0 0-5791 {}} {259 0 0-5794 {}}} SUCCS {{259 0 0-5796 {}}} CYCLES {}}
+set a(0-5796) {NAME ACC1:conc#646 TYPE CONCATENATE PAR 0-4427 XREFS 30526 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.667935675} PREDS {{146 0 0-5595 {}} {258 0 0-5790 {}} {259 0 0-5795 {}}} SUCCS {{259 0 0-5797 {}}} CYCLES {}}
+set a(0-5797) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#312 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-4427 XREFS 30527 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.5337763201789505 1 0.7212826951789504} PREDS {{146 0 0-5595 {}} {258 0 0-5785 {}} {259 0 0-5796 {}}} SUCCS {{259 0 0-5798 {}}} CYCLES {}}
+set a(0-5798) {NAME ACC1:slc#99 TYPE READSLICE PAR 0-4427 XREFS 30528 LOC {1 0.4508197 1 0.533776375 1 0.533776375 1 0.72128275} PREDS {{146 0 0-5595 {}} {259 0 0-5797 {}}} SUCCS {{259 0 0-5799 {}}} CYCLES {}}
+set a(0-5799) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#322 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-4427 XREFS 30529 LOC {1 0.4508197 1 0.533776375 1 0.533776375 1 0.5871233951789505 1 0.7746297701789504} PREDS {{146 0 0-5595 {}} {258 0 0-5773 {}} {259 0 0-5798 {}}} SUCCS {{259 0 0-5800 {}}} CYCLES {}}
+set a(0-5800) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,6) AREA_SCORE 6.28 QUANTITY 2 NAME ACC1:acc#327 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-4427 XREFS 30530 LOC {1 0.504166775 1 0.58712345 1 0.58712345 1 0.645723159496936 1 0.833229534496936} PREDS {{146 0 0-5595 {}} {258 0 0-5754 {}} {259 0 0-5799 {}}} SUCCS {{258 0 0-5824 {}}} CYCLES {}}
+set a(0-5801) {NAME ACC2:slc(ACC1:acc#110.psp#2)#3 TYPE READSLICE PAR 0-4427 XREFS 30531 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.767155925} PREDS {{146 0 0-5595 {}} {258 0 0-5513 {}}} SUCCS {{259 0 0-5802 {}}} CYCLES {}}
+set a(0-5802) {NAME ACC2:not#2 TYPE NOT PAR 0-4427 XREFS 30532 LOC {1 0.281724925 1 0.57964955 1 0.57964955 1 0.767155925} PREDS {{146 0 0-5595 {}} {259 0 0-5801 {}}} SUCCS {{258 0 0-5805 {}}} CYCLES {}}
+set a(0-5803) {NAME ACC2:slc(acc.imod#18)#1 TYPE READSLICE PAR 0-4427 XREFS 30533 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 1 0.767155925} PREDS {{146 0 0-5595 {}} {258 0 0-5509 {}}} SUCCS {{259 0 0-5804 {}}} CYCLES {}}
+set a(0-5804) {NAME ACC2:not#3 TYPE NOT PAR 0-4427 XREFS 30534 LOC {1 0.37022669999999996 1 0.57964955 1 0.57964955 1 0.767155925} PREDS {{146 0 0-5595 {}} {259 0 0-5803 {}}} SUCCS {{259 0 0-5805 {}}} CYCLES {}}
+set a(0-5805) {NAME ACC2:conc#3 TYPE CONCATENATE PAR 0-4427 XREFS 30535 LOC {1 0.37022669999999996 1 0.57964955 1 0.57964955 1 0.767155925} PREDS {{146 0 0-5595 {}} {258 0 0-5802 {}} {259 0 0-5804 {}}} SUCCS {{259 0 0-5806 {}}} CYCLES {}}
+set a(0-5806) {NAME ACC1:conc#643 TYPE CONCATENATE PAR 0-4427 XREFS 30536 LOC {1 0.37022669999999996 1 0.57964955 1 0.57964955 1 0.767155925} PREDS {{146 0 0-5595 {}} {259 0 0-5805 {}}} SUCCS {{258 0 0-5813 {}}} CYCLES {}}
+set a(0-5807) {NAME ACC2:slc(ACC1:acc#118.psp) TYPE READSLICE PAR 0-4427 XREFS 30537 LOC {1 0.34298077499999996 1 0.57964955 1 0.57964955 1 0.767155925} PREDS {{146 0 0-5595 {}} {258 0 0-5503 {}}} SUCCS {{258 0 0-5812 {}}} CYCLES {}}
+set a(0-5808) {NAME ACC1-1:slc(acc.imod#7) TYPE READSLICE PAR 0-4427 XREFS 30538 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.767155925} PREDS {{146 0 0-5595 {}} {258 0 0-5510 {}}} SUCCS {{258 0 0-5811 {}}} CYCLES {}}
+set a(0-5809) {NAME ACC1-1:slc(acc#5.psp)#50 TYPE READSLICE PAR 0-4427 XREFS 30539 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.767155925} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5810 {}}} CYCLES {}}
+set a(0-5810) {NAME ACC1-1:not#59 TYPE NOT PAR 0-4427 XREFS 30540 LOC {1 0.16961555 1 0.4804293 1 0.4804293 1 0.767155925} PREDS {{146 0 0-5595 {}} {259 0 0-5809 {}}} SUCCS {{259 0 0-5811 {}}} CYCLES {}}
+set a(0-5811) {NAME ACC1-1:nand#1 TYPE NAND PAR 0-4427 XREFS 30541 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 1 0.767155925} PREDS {{146 0 0-5595 {}} {258 0 0-5808 {}} {259 0 0-5810 {}}} SUCCS {{259 0 0-5812 {}}} CYCLES {}}
+set a(0-5812) {NAME ACC1:conc#644 TYPE CONCATENATE PAR 0-4427 XREFS 30542 LOC {1 0.39747262499999997 1 0.57964955 1 0.57964955 1 0.767155925} PREDS {{146 0 0-5595 {}} {258 0 0-5807 {}} {259 0 0-5811 {}}} SUCCS {{259 0 0-5813 {}}} CYCLES {}}
+set a(0-5813) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#311 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-4427 XREFS 30543 LOC {1 0.39747262499999997 1 0.57964955 1 0.57964955 1 0.6126863201789504 1 0.8001926951789504} PREDS {{146 0 0-5595 {}} {258 0 0-5806 {}} {259 0 0-5812 {}}} SUCCS {{259 0 0-5814 {}}} CYCLES {}}
+set a(0-5814) {NAME ACC1:slc#98 TYPE READSLICE PAR 0-4427 XREFS 30544 LOC {1 0.43050944999999996 1 0.612686375 1 0.612686375 1 0.80019275} PREDS {{146 0 0-5595 {}} {259 0 0-5813 {}}} SUCCS {{258 0 0-5823 {}}} CYCLES {}}
+set a(0-5815) {NAME ACC1-3:slc(acc#5.psp)#69 TYPE READSLICE PAR 0-4427 XREFS 30545 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.772946825} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5816 {}}} CYCLES {}}
+set a(0-5816) {NAME ACC1-3:exs#32 TYPE SIGNEXTEND PAR 0-4427 XREFS 30546 LOC {1 0.16961555 1 0.58544045 1 0.58544045 1 0.772946825} PREDS {{146 0 0-5595 {}} {259 0 0-5815 {}}} SUCCS {{259 0 0-5817 {}}} CYCLES {}}
+set a(0-5817) {NAME ACC1:conc#637 TYPE CONCATENATE PAR 0-4427 XREFS 30547 LOC {1 0.16961555 1 0.58544045 1 0.58544045 1 0.772946825} PREDS {{146 0 0-5595 {}} {259 0 0-5816 {}}} SUCCS {{258 0 0-5821 {}}} CYCLES {}}
+set a(0-5818) {NAME ACC2:slc(ACC1:acc#118.psp#1) TYPE READSLICE PAR 0-4427 XREFS 30548 LOC {1 0.34298077499999996 1 0.58544045 1 0.58544045 1 0.772946825} PREDS {{146 0 0-5595 {}} {258 0 0-5511 {}}} SUCCS {{258 0 0-5820 {}}} CYCLES {}}
+set a(0-5819) {NAME ACC2:slc(ACC1:acc#110.psp#2)#1 TYPE READSLICE PAR 0-4427 XREFS 30549 LOC {1 0.281724925 1 0.433986675 1 0.433986675 1 0.772946825} PREDS {{146 0 0-5595 {}} {258 0 0-5513 {}}} SUCCS {{259 0 0-5820 {}}} CYCLES {}}
+set a(0-5820) {NAME ACC1:conc#638 TYPE CONCATENATE PAR 0-4427 XREFS 30550 LOC {1 0.34298077499999996 1 0.58544045 1 0.58544045 1 0.772946825} PREDS {{146 0 0-5595 {}} {258 0 0-5818 {}} {259 0 0-5819 {}}} SUCCS {{259 0 0-5821 {}}} CYCLES {}}
+set a(0-5821) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME ACC1:acc#308 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 30551 LOC {1 0.34298077499999996 1 0.58544045 1 0.58544045 1 0.6126863270708272 1 0.8001927020708272} PREDS {{146 0 0-5595 {}} {258 0 0-5817 {}} {259 0 0-5820 {}}} SUCCS {{259 0 0-5822 {}}} CYCLES {}}
+set a(0-5822) {NAME ACC1:slc#95 TYPE READSLICE PAR 0-4427 XREFS 30552 LOC {1 0.37022669999999996 1 0.612686375 1 0.612686375 1 0.80019275} PREDS {{146 0 0-5595 {}} {259 0 0-5821 {}}} SUCCS {{259 0 0-5823 {}}} CYCLES {}}
+set a(0-5823) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME ACC1:acc#321 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-4427 XREFS 30553 LOC {1 0.43050944999999996 1 0.612686375 1 0.612686375 1 0.6457231451789505 1 0.8332295201789505} PREDS {{146 0 0-5595 {}} {258 0 0-5814 {}} {259 0 0-5822 {}}} SUCCS {{259 0 0-5824 {}}} CYCLES {}}
+set a(0-5824) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME ACC1:acc#331 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 30554 LOC {1 0.562766525 1 0.6457231999999999 1 0.6457231999999999 1 0.6889249234103023 1 0.8764312984103023} PREDS {{146 0 0-5595 {}} {258 0 0-5800 {}} {259 0 0-5823 {}}} SUCCS {{259 0 0-5825 {}}} CYCLES {}}
+set a(0-5825) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME ACC1:acc#335 TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-4427 XREFS 30555 LOC {1 0.652410925 1 0.6889249749999999 1 0.6889249749999999 1 0.7413094277684257 1 0.9288158027684257} PREDS {{146 0 0-5595 {}} {258 0 0-5715 {}} {259 0 0-5824 {}}} SUCCS {{259 0 0-5826 {}}} CYCLES {}}
+set a(0-5826) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#338 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 30556 LOC {1 0.7047954249999999 1 0.741309475 1 0.741309475 1 0.8124935783364113 1 0.9999999533364113} PREDS {{146 0 0-5595 {}} {258 0 0-5623 {}} {259 0 0-5825 {}}} SUCCS {{259 0 0-5827 {}}} CYCLES {}}
+set a(0-5827) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,0,12,1,13) AREA_SCORE 14.00 QUANTITY 2 NAME ACC1:acc#340 TYPE ACCU DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-4427 XREFS 30557 LOC {1 0.7759795749999999 1 0.812493625 1 0.812493625 1 0.9062972502166912 2 0.1038538002166912} PREDS {{146 0 0-5595 {}} {258 0 0-5599 {}} {259 0 0-5826 {}}} SUCCS {{258 0 0-5867 {}}} CYCLES {}}
+set a(0-5828) {NAME ACC2:slc(ACC1:acc#125.psp)#4 TYPE READSLICE PAR 0-4427 XREFS 30558 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.695713925} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{258 0 0-5830 {}}} CYCLES {}}
+set a(0-5829) {NAME ACC2:slc(ACC1:acc#125.psp#1)#2 TYPE READSLICE PAR 0-4427 XREFS 30559 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.695713925} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5830 {}}} CYCLES {}}
+set a(0-5830) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 6 NAME ACC2:acc#4 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-4427 XREFS 30560 LOC {1 0.16961555 1 0.53679555 1 0.53679555 1 0.56840638625 1 0.72732476125} PREDS {{146 0 0-5595 {}} {258 0 0-5828 {}} {259 0 0-5829 {}}} SUCCS {{259 0 0-5831 {}}} CYCLES {}}
+set a(0-5831) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME ACC1:mul#19 TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-4427 XREFS 30561 LOC {1 0.201226425 1 0.5684064249999999 1 0.5684064249999999 1 0.7698974312499999 1 0.9288158062499999} PREDS {{146 0 0-5595 {}} {259 0 0-5830 {}}} SUCCS {{258 0 0-5857 {}}} CYCLES {}}
+set a(0-5832) {NAME ACC2:slc(ACC1:acc#125.psp#1)#14 TYPE READSLICE PAR 0-4427 XREFS 30562 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.83773495} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{258 0 0-5836 {}}} CYCLES {}}
+set a(0-5833) {NAME ACC2:slc(ACC1:acc#125.psp)#14 TYPE READSLICE PAR 0-4427 XREFS 30563 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.83773495} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{258 0 0-5836 {}}} CYCLES {}}
+set a(0-5834) {NAME ACC1-3:slc(acc#5.psp)#58 TYPE READSLICE PAR 0-4427 XREFS 30564 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.83773495} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5835 {}}} CYCLES {}}
+set a(0-5835) {NAME ACC1-3:exs#26 TYPE SIGNEXTEND PAR 0-4427 XREFS 30565 LOC {1 0.16961555 1 0.6788165749999999 1 0.6788165749999999 1 0.83773495} PREDS {{146 0 0-5595 {}} {259 0 0-5834 {}}} SUCCS {{259 0 0-5836 {}}} CYCLES {}}
+set a(0-5836) {NAME ACC2:conc#7 TYPE CONCATENATE PAR 0-4427 XREFS 30566 LOC {1 0.16961555 1 0.6788165749999999 1 0.6788165749999999 1 0.83773495} PREDS {{146 0 0-5595 {}} {258 0 0-5833 {}} {258 0 0-5832 {}} {259 0 0-5835 {}}} SUCCS {{258 0 0-5850 {}}} CYCLES {}}
+set a(0-5837) {NAME ACC2:slc(ACC1:acc#125.psp#1)#12 TYPE READSLICE PAR 0-4427 XREFS 30567 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.746098375} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{258 0 0-5840 {}}} CYCLES {}}
+set a(0-5838) {NAME ACC1-3:slc(acc#5.psp)#61 TYPE READSLICE PAR 0-4427 XREFS 30568 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.746098375} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5839 {}}} CYCLES {}}
+set a(0-5839) {NAME ACC1-3:exs#20 TYPE SIGNEXTEND PAR 0-4427 XREFS 30569 LOC {1 0.16961555 1 0.5871799999999999 1 0.5871799999999999 1 0.746098375} PREDS {{146 0 0-5595 {}} {259 0 0-5838 {}}} SUCCS {{259 0 0-5840 {}}} CYCLES {}}
+set a(0-5840) {NAME ACC2:conc#4 TYPE CONCATENATE PAR 0-4427 XREFS 30570 LOC {1 0.16961555 1 0.5871799999999999 1 0.5871799999999999 1 0.746098375} PREDS {{146 0 0-5595 {}} {258 0 0-5837 {}} {259 0 0-5839 {}}} SUCCS {{258 0 0-5845 {}}} CYCLES {}}
+set a(0-5841) {NAME ACC2:slc(ACC1:acc#125.psp#1)#13 TYPE READSLICE PAR 0-4427 XREFS 30571 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.746098375} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{258 0 0-5844 {}}} CYCLES {}}
+set a(0-5842) {NAME ACC1-3:slc(acc#5.psp)#60 TYPE READSLICE PAR 0-4427 XREFS 30572 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.746098375} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5843 {}}} CYCLES {}}
+set a(0-5843) {NAME ACC1-3:exs#21 TYPE SIGNEXTEND PAR 0-4427 XREFS 30573 LOC {1 0.16961555 1 0.5871799999999999 1 0.5871799999999999 1 0.746098375} PREDS {{146 0 0-5595 {}} {259 0 0-5842 {}}} SUCCS {{259 0 0-5844 {}}} CYCLES {}}
+set a(0-5844) {NAME ACC2:conc#5 TYPE CONCATENATE PAR 0-4427 XREFS 30574 LOC {1 0.16961555 1 0.5871799999999999 1 0.5871799999999999 1 0.746098375} PREDS {{146 0 0-5595 {}} {258 0 0-5841 {}} {259 0 0-5843 {}}} SUCCS {{259 0 0-5845 {}}} CYCLES {}}
+set a(0-5845) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME ACC1:acc#320 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-4427 XREFS 30575 LOC {1 0.16961555 1 0.5871799999999999 1 0.5871799999999999 1 0.6405270201789504 1 0.7994453951789504} PREDS {{146 0 0-5595 {}} {258 0 0-5840 {}} {259 0 0-5844 {}}} SUCCS {{258 0 0-5849 {}}} CYCLES {}}
+set a(0-5846) {NAME ACC1-3:slc(acc#5.psp)#55 TYPE READSLICE PAR 0-4427 XREFS 30576 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.79944545} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5847 {}}} CYCLES {}}
+set a(0-5847) {NAME ACC1-3:exs#27 TYPE SIGNEXTEND PAR 0-4427 XREFS 30577 LOC {1 0.16961555 1 0.640527075 1 0.640527075 1 0.79944545} PREDS {{146 0 0-5595 {}} {259 0 0-5846 {}}} SUCCS {{259 0 0-5848 {}}} CYCLES {}}
+set a(0-5848) {NAME ACC1:conc#610 TYPE CONCATENATE PAR 0-4427 XREFS 30578 LOC {1 0.16961555 1 0.640527075 1 0.640527075 1 0.79944545} PREDS {{146 0 0-5595 {}} {259 0 0-5847 {}}} SUCCS {{259 0 0-5849 {}}} CYCLES {}}
+set a(0-5849) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME ACC1:acc#326 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 30579 LOC {1 0.222962625 1 0.640527075 1 0.640527075 1 0.678816534496936 1 0.8377349094969361} PREDS {{146 0 0-5595 {}} {258 0 0-5845 {}} {259 0 0-5848 {}}} SUCCS {{259 0 0-5850 {}}} CYCLES {}}
+set a(0-5850) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME ACC1:acc#329 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 30580 LOC {1 0.261252125 1 0.6788165749999999 1 0.6788165749999999 1 0.7220182984103023 1 0.8809366734103024} PREDS {{146 0 0-5595 {}} {258 0 0-5836 {}} {259 0 0-5849 {}}} SUCCS {{258 0 0-5856 {}}} CYCLES {}}
+set a(0-5851) {NAME ACC1-3:slc(acc#5.psp)#52 TYPE READSLICE PAR 0-4427 XREFS 30581 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.880936725} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{258 0 0-5854 {}}} CYCLES {}}
+set a(0-5852) {NAME ACC1-3:slc(acc#5.psp)#53 TYPE READSLICE PAR 0-4427 XREFS 30582 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.880936725} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5853 {}}} CYCLES {}}
+set a(0-5853) {NAME ACC1-3:exs#30 TYPE SIGNEXTEND PAR 0-4427 XREFS 30583 LOC {1 0.16961555 1 0.7220183499999999 1 0.7220183499999999 1 0.880936725} PREDS {{146 0 0-5595 {}} {259 0 0-5852 {}}} SUCCS {{259 0 0-5854 {}}} CYCLES {}}
+set a(0-5854) {NAME ACC1-3:conc#240 TYPE CONCATENATE PAR 0-4427 XREFS 30584 LOC {1 0.16961555 1 0.7220183499999999 1 0.7220183499999999 1 0.880936725} PREDS {{146 0 0-5595 {}} {258 0 0-5851 {}} {259 0 0-5853 {}}} SUCCS {{259 0 0-5855 {}}} CYCLES {}}
+set a(0-5855) {NAME ACC1-3:exs#541 TYPE SIGNEXTEND PAR 0-4427 XREFS 30585 LOC {1 0.16961555 1 0.7220183499999999 1 0.7220183499999999 1 0.880936725} PREDS {{146 0 0-5595 {}} {259 0 0-5854 {}}} SUCCS {{259 0 0-5856 {}}} CYCLES {}}
+set a(0-5856) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(7,0,7,1,9) AREA_SCORE 8.00 QUANTITY 10 NAME ACC1:acc#333 TYPE ACCU DELAY {0.77 ns} LIBRARY_DELAY {0.77 ns} PAR 0-4427 XREFS 30586 LOC {1 0.3044539 1 0.7220183499999999 1 0.7220183499999999 1 0.7698974129329679 1 0.9288157879329679} PREDS {{146 0 0-5595 {}} {258 0 0-5850 {}} {259 0 0-5855 {}}} SUCCS {{259 0 0-5857 {}}} CYCLES {}}
+set a(0-5857) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,1,11) AREA_SCORE 11.00 QUANTITY 6 NAME ACC1:acc#337 TYPE ACCU DELAY {1.14 ns} LIBRARY_DELAY {1.14 ns} PAR 0-4427 XREFS 30587 LOC {1 0.402717475 1 0.7698974749999999 1 0.7698974749999999 1 0.8410815783364113 1 0.9999999533364113} PREDS {{146 0 0-5595 {}} {258 0 0-5831 {}} {259 0 0-5856 {}}} SUCCS {{258 0 0-5866 {}}} CYCLES {}}
+set a(0-5858) {NAME ACC2:slc(ACC1:acc#125.psp)#11 TYPE READSLICE PAR 0-4427 XREFS 30588 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.766898075} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{258 0 0-5860 {}}} CYCLES {}}
+set a(0-5859) {NAME ACC2:slc(ACC1:acc#125.psp#1)#10 TYPE READSLICE PAR 0-4427 XREFS 30589 LOC {1 0.16961555 1 0.3151275 1 0.3151275 1 0.766898075} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{259 0 0-5860 {}}} CYCLES {}}
+set a(0-5860) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(1,0,1,0,2) AREA_SCORE 2.32 QUANTITY 6 NAME ACC2:acc#7 TYPE ACCU DELAY {0.51 ns} LIBRARY_DELAY {0.51 ns} PAR 0-4427 XREFS 30590 LOC {1 0.16961555 1 0.6079797 1 0.6079797 1 0.6395905362500001 1 0.7985089112499999} PREDS {{146 0 0-5595 {}} {258 0 0-5858 {}} {259 0 0-5859 {}}} SUCCS {{259 0 0-5861 {}}} CYCLES {}}
+set a(0-5861) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME ACC1:mul#22 TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-4427 XREFS 30591 LOC {1 0.201226425 1 0.6395905749999999 1 0.6395905749999999 1 0.8410815812499999 1 0.9999999562499999} PREDS {{146 0 0-5595 {}} {259 0 0-5860 {}}} SUCCS {{258 0 0-5865 {}}} CYCLES {}}
+set a(0-5862) {NAME ACC2:slc(ACC1:acc#125.psp#1)#11 TYPE READSLICE PAR 0-4427 XREFS 30592 LOC {1 0.16961555 1 0.3151275 1 0.3151275 2 0.038638175} PREDS {{146 0 0-5595 {}} {258 0 0-5512 {}}} SUCCS {{258 0 0-5865 {}}} CYCLES {}}
+set a(0-5863) {NAME ACC1-3:slc(acc#5.psp)#56 TYPE READSLICE PAR 0-4427 XREFS 30593 LOC {1 0.16961555 1 0.3151275 1 0.3151275 2 0.038638175} PREDS {{146 0 0-5595 {}} {258 0 0-5504 {}}} SUCCS {{259 0 0-5864 {}}} CYCLES {}}
+set a(0-5864) {NAME ACC1-3:exs#29 TYPE SIGNEXTEND PAR 0-4427 XREFS 30594 LOC {1 0.16961555 1 0.8410816249999999 1 0.8410816249999999 2 0.038638175} PREDS {{146 0 0-5595 {}} {259 0 0-5863 {}}} SUCCS {{259 0 0-5865 {}}} CYCLES {}}
+set a(0-5865) {NAME ACC1:conc#441 TYPE CONCATENATE PAR 0-4427 XREFS 30595 LOC {1 0.402717475 1 0.8410816249999999 1 0.8410816249999999 2 0.038638175} PREDS {{146 0 0-5595 {}} {258 0 0-5862 {}} {258 0 0-5861 {}} {259 0 0-5864 {}}} SUCCS {{259 0 0-5866 {}}} CYCLES {}}
+set a(0-5866) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,13) AREA_SCORE 12.00 QUANTITY 6 NAME ACC1:acc#339 TYPE ACCU DELAY {1.04 ns} LIBRARY_DELAY {1.04 ns} PAR 0-4427 XREFS 30596 LOC {1 0.473901625 1 0.8410816249999999 1 0.8410816249999999 1 0.9062972563734283 2 0.10385380637342836} PREDS {{146 0 0-5595 {}} {258 0 0-5857 {}} {259 0 0-5865 {}}} SUCCS {{259 0 0-5867 {}}} CYCLES {}}
+set a(0-5867) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(13,0,13,0,13) AREA_SCORE 14.22 QUANTITY 1 NAME ACC1:acc#341 TYPE ACCU DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-4427 XREFS 30597 LOC {1 0.86978325 1 0.9062973 1 0.9062973 1 0.9999999620503581 2 0.19755651205035812} PREDS {{146 0 0-5595 {}} {258 0 0-5827 {}} {259 0 0-5866 {}}} SUCCS {{259 0 0-5868 {}}} CYCLES {}}
+set a(0-5868) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,13,1,16) AREA_SCORE 17.00 QUANTITY 3 NAME ACC1:acc#342 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-4427 XREFS 30598 LOC {2 0.128961425 2 0.19755655 2 0.19755655 2 0.3034573281715468 2 0.3034573281715468} PREDS {{146 0 0-5595 {}} {258 0 0-5588 {}} {259 0 0-5867 {}}} SUCCS {{259 0 0-5869 {}}} CYCLES {}}
+set a(0-5869) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 1 NAME ACC1:acc TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-4427 XREFS 30599 LOC {2 0.23486225 2 0.303457375 2 0.303457375 2 0.409067105357901 2 0.409067105357901} PREDS {{146 0 0-5595 {}} {258 0 0-5550 {}} {259 0 0-5868 {}}} SUCCS {{259 0 0-5870 {}}} CYCLES {}}
+set a(0-5870) {NAME ACC2:slc TYPE READSLICE PAR 0-4427 XREFS 30600 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.40906715} PREDS {{146 0 0-5595 {}} {259 0 0-5869 {}}} SUCCS {{259 0 0-5871 {}} {258 0 0-5872 {}} {258 0 0-5875 {}} {258 0 0-5877 {}} {258 0 0-5880 {}} {258 0 0-5883 {}} {258 0 0-5884 {}} {258 0 0-5889 {}} {258 0 0-5891 {}} {258 0 0-5893 {}} {258 0 0-5910 {}} {258 0 0-5919 {}} {258 0 0-5920 {}} {258 0 0-5922 {}}} CYCLES {}}
+set a(0-5871) {NAME intensity:slc(intensity#2.sg1)#4 TYPE READSLICE PAR 0-4427 XREFS 30601 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.40906715} PREDS {{146 0 0-5595 {}} {259 0 0-5870 {}}} SUCCS {{258 0 0-5874 {}}} CYCLES {}}
+set a(0-5872) {NAME intensity:slc(intensity#2.sg1)#5 TYPE READSLICE PAR 0-4427 XREFS 30602 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.40906715} PREDS {{146 0 0-5595 {}} {258 0 0-5870 {}}} SUCCS {{259 0 0-5873 {}}} CYCLES {}}
+set a(0-5873) {NAME FRAME:not#2 TYPE NOT PAR 0-4427 XREFS 30603 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.40906715} PREDS {{146 0 0-5595 {}} {259 0 0-5872 {}}} SUCCS {{259 0 0-5874 {}}} CYCLES {}}
+set a(0-5874) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME FRAME:acc#6 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30604 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.45662327707082717 2 0.45662327707082717} PREDS {{146 0 0-5595 {}} {258 0 0-5871 {}} {259 0 0-5873 {}}} SUCCS {{258 0 0-5882 {}}} CYCLES {}}
+set a(0-5875) {NAME intensity:slc(intensity#2.sg1)#6 TYPE READSLICE PAR 0-4427 XREFS 30605 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.42937739999999996} PREDS {{146 0 0-5595 {}} {258 0 0-5870 {}}} SUCCS {{259 0 0-5876 {}}} CYCLES {}}
+set a(0-5876) {NAME FRAME:not#3 TYPE NOT PAR 0-4427 XREFS 30606 LOC {2 0.340472025 2 0.42937739999999996 2 0.42937739999999996 2 0.42937739999999996} PREDS {{146 0 0-5595 {}} {259 0 0-5875 {}}} SUCCS {{258 0 0-5879 {}}} CYCLES {}}
+set a(0-5877) {NAME intensity:slc(intensity#2.sg1)#7 TYPE READSLICE PAR 0-4427 XREFS 30607 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.42937739999999996} PREDS {{146 0 0-5595 {}} {258 0 0-5870 {}}} SUCCS {{259 0 0-5878 {}}} CYCLES {}}
+set a(0-5878) {NAME FRAME:not#9 TYPE NOT PAR 0-4427 XREFS 30608 LOC {2 0.340472025 2 0.42937739999999996 2 0.42937739999999996 2 0.42937739999999996} PREDS {{146 0 0-5595 {}} {259 0 0-5877 {}}} SUCCS {{259 0 0-5879 {}}} CYCLES {}}
+set a(0-5879) {NAME FRAME:conc TYPE CONCATENATE PAR 0-4427 XREFS 30609 LOC {2 0.340472025 2 0.42937739999999996 2 0.42937739999999996 2 0.42937739999999996} PREDS {{146 0 0-5595 {}} {258 0 0-5876 {}} {259 0 0-5878 {}}} SUCCS {{258 0 0-5881 {}}} CYCLES {}}
+set a(0-5880) {NAME intensity:slc(intensity#2.sg1)#1 TYPE READSLICE PAR 0-4427 XREFS 30610 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.42937739999999996} PREDS {{146 0 0-5595 {}} {258 0 0-5870 {}}} SUCCS {{259 0 0-5881 {}}} CYCLES {}}
+set a(0-5881) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME FRAME:acc#5 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 30611 LOC {2 0.340472025 2 0.42937739999999996 2 0.42937739999999996 2 0.45662327707082717 2 0.45662327707082717} PREDS {{146 0 0-5595 {}} {258 0 0-5879 {}} {259 0 0-5880 {}}} SUCCS {{259 0 0-5882 {}}} CYCLES {}}
+set a(0-5882) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 11 NAME FRAME:acc#8 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-4427 XREFS 30612 LOC {2 0.3880282 2 0.45662332499999997 2 0.45662332499999997 2 0.5099703451789505 2 0.5099703451789505} PREDS {{146 0 0-5595 {}} {258 0 0-5874 {}} {259 0 0-5881 {}}} SUCCS {{258 0 0-5887 {}}} CYCLES {}}
+set a(0-5883) {NAME intensity:slc(intensity#2.sg1)#2 TYPE READSLICE PAR 0-4427 XREFS 30613 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.46241422499999996} PREDS {{146 0 0-5595 {}} {258 0 0-5870 {}}} SUCCS {{258 0 0-5886 {}}} CYCLES {}}
+set a(0-5884) {NAME intensity:slc(intensity#2.sg1)#3 TYPE READSLICE PAR 0-4427 XREFS 30614 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.46241422499999996} PREDS {{146 0 0-5595 {}} {258 0 0-5870 {}}} SUCCS {{259 0 0-5885 {}}} CYCLES {}}
+set a(0-5885) {NAME FRAME:not#1 TYPE NOT PAR 0-4427 XREFS 30615 LOC {2 0.340472025 2 0.46241422499999996 2 0.46241422499999996 2 0.46241422499999996} PREDS {{146 0 0-5595 {}} {259 0 0-5884 {}}} SUCCS {{259 0 0-5886 {}}} CYCLES {}}
+set a(0-5886) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 60 NAME FRAME:acc#7 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-4427 XREFS 30616 LOC {2 0.340472025 2 0.46241422499999996 2 0.46241422499999996 2 0.5099703520708271 2 0.5099703520708271} PREDS {{146 0 0-5595 {}} {258 0 0-5883 {}} {259 0 0-5885 {}}} SUCCS {{259 0 0-5887 {}}} CYCLES {}}
+set a(0-5887) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME FRAME:acc#9 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 30617 LOC {2 0.44137527499999996 2 0.5099703999999999 2 0.5099703999999999 2 0.548259859496936 2 0.548259859496936} PREDS {{146 0 0-5595 {}} {258 0 0-5882 {}} {259 0 0-5886 {}}} SUCCS {{259 0 0-5888 {}}} CYCLES {}}
+set a(0-5888) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME acc#15 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 30618 LOC {2 0.479664775 2 0.5482599 2 0.5482599 2 0.5914616234103024 2 0.5914616234103024} PREDS {{146 0 0-5595 {}} {259 0 0-5887 {}}} SUCCS {{258 0 0-5894 {}} {258 0 0-5896 {}} {258 0 0-5898 {}} {258 0 0-5900 {}} {258 0 0-5908 {}} {258 0 0-5913 {}}} CYCLES {}}
+set a(0-5889) {NAME intensity:slc(intensity#2.sg1)#9 TYPE READSLICE PAR 0-4427 XREFS 30619 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.63706255} PREDS {{146 0 0-5595 {}} {258 0 0-5870 {}}} SUCCS {{259 0 0-5890 {}}} CYCLES {}}
+set a(0-5890) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,12,1,13) AREA_SCORE 330.00 QUANTITY 7 NAME FRAME:mul TYPE MUL DELAY {3.22 ns} LIBRARY_DELAY {3.22 ns} PAR 0-4427 XREFS 30620 LOC {2 0.340472025 2 0.63706255 2 0.63706255 2 0.8385535562499999 2 0.8385535562499999} PREDS {{146 0 0-5595 {}} {259 0 0-5889 {}}} SUCCS {{258 0 0-5918 {}}} CYCLES {}}
+set a(0-5891) {NAME intensity:slc(intensity#2.sg1)#11 TYPE READSLICE PAR 0-4427 XREFS 30621 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.59364335} PREDS {{146 0 0-5595 {}} {258 0 0-5870 {}}} SUCCS {{259 0 0-5892 {}}} CYCLES {}}
+set a(0-5892) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 1 NAME FRAME:mul#1 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-4427 XREFS 30622 LOC {2 0.340472025 2 0.59364335 2 0.59364335 2 0.7715251421744312 2 0.7715251421744312} PREDS {{146 0 0-5595 {}} {259 0 0-5891 {}}} SUCCS {{258 0 0-5917 {}}} CYCLES {}}
+set a(0-5893) {NAME intensity:slc(intensity#2.sg1) TYPE READSLICE PAR 0-4427 XREFS 30623 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.7283234249999999} PREDS {{146 0 0-5595 {}} {258 0 0-5870 {}}} SUCCS {{258 0 0-5916 {}}} CYCLES {}}
+set a(0-5894) {NAME FRAME:slc(acc.imod#12)#6 TYPE READSLICE PAR 0-4427 XREFS 30624 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.629751175} PREDS {{146 0 0-5595 {}} {258 0 0-5888 {}}} SUCCS {{259 0 0-5895 {}}} CYCLES {}}
+set a(0-5895) {NAME FRAME:not#7 TYPE NOT PAR 0-4427 XREFS 30625 LOC {2 0.5228665499999999 2 0.629751175 2 0.629751175 2 0.629751175} PREDS {{146 0 0-5595 {}} {259 0 0-5894 {}}} SUCCS {{258 0 0-5907 {}}} CYCLES {}}
+set a(0-5896) {NAME FRAME:slc(acc.imod#12)#1 TYPE READSLICE PAR 0-4427 XREFS 30626 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-5595 {}} {258 0 0-5888 {}}} SUCCS {{259 0 0-5897 {}}} CYCLES {}}
+set a(0-5897) {NAME FRAME:conc#14 TYPE CONCATENATE PAR 0-4427 XREFS 30627 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-5595 {}} {259 0 0-5896 {}}} SUCCS {{258 0 0-5903 {}}} CYCLES {}}
+set a(0-5898) {NAME FRAME:slc(acc.imod#12)#2 TYPE READSLICE PAR 0-4427 XREFS 30628 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-5595 {}} {258 0 0-5888 {}}} SUCCS {{259 0 0-5899 {}}} CYCLES {}}
+set a(0-5899) {NAME FRAME:not#5 TYPE NOT PAR 0-4427 XREFS 30629 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-5595 {}} {259 0 0-5898 {}}} SUCCS {{258 0 0-5902 {}}} CYCLES {}}
+set a(0-5900) {NAME FRAME:slc(acc.imod#12) TYPE READSLICE PAR 0-4427 XREFS 30630 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-5595 {}} {258 0 0-5888 {}}} SUCCS {{259 0 0-5901 {}}} CYCLES {}}
+set a(0-5901) {NAME FRAME:not#4 TYPE NOT PAR 0-4427 XREFS 30631 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-5595 {}} {259 0 0-5900 {}}} SUCCS {{259 0 0-5902 {}}} CYCLES {}}
+set a(0-5902) {NAME FRAME:conc#15 TYPE CONCATENATE PAR 0-4427 XREFS 30632 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.591461675} PREDS {{146 0 0-5595 {}} {258 0 0-5899 {}} {259 0 0-5901 {}}} SUCCS {{259 0 0-5903 {}}} CYCLES {}}
+set a(0-5903) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME FRAME:acc#16 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 30633 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.6297511344969361 2 0.6297511344969361} PREDS {{146 0 0-5595 {}} {258 0 0-5897 {}} {259 0 0-5902 {}}} SUCCS {{259 0 0-5904 {}}} CYCLES {}}
+set a(0-5904) {NAME FRAME:slc#3 TYPE READSLICE PAR 0-4427 XREFS 30634 LOC {2 0.56115605 2 0.629751175 2 0.629751175 2 0.629751175} PREDS {{146 0 0-5595 {}} {259 0 0-5903 {}}} SUCCS {{259 0 0-5905 {}}} CYCLES {}}
+set a(0-5905) {NAME FRAME:slc#2 TYPE READSLICE PAR 0-4427 XREFS 30635 LOC {2 0.56115605 2 0.629751175 2 0.629751175 2 0.629751175} PREDS {{146 0 0-5595 {}} {259 0 0-5904 {}}} SUCCS {{259 0 0-5906 {}}} CYCLES {}}
+set a(0-5906) {NAME FRAME:not#8 TYPE NOT PAR 0-4427 XREFS 30636 LOC {2 0.56115605 2 0.629751175 2 0.629751175 2 0.629751175} PREDS {{146 0 0-5595 {}} {259 0 0-5905 {}}} SUCCS {{259 0 0-5907 {}}} CYCLES {}}
+set a(0-5907) {NAME FRAME:conc#3 TYPE CONCATENATE PAR 0-4427 XREFS 30637 LOC {2 0.56115605 2 0.629751175 2 0.629751175 2 0.629751175} PREDS {{146 0 0-5595 {}} {258 0 0-5895 {}} {259 0 0-5906 {}}} SUCCS {{258 0 0-5909 {}}} CYCLES {}}
+set a(0-5908) {NAME FRAME:slc(acc.imod#12)#5 TYPE READSLICE PAR 0-4427 XREFS 30638 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.629751175} PREDS {{146 0 0-5595 {}} {258 0 0-5888 {}}} SUCCS {{259 0 0-5909 {}}} CYCLES {}}
+set a(0-5909) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,1,5) AREA_SCORE 4.00 QUANTITY 22 NAME FRAME:acc#10 TYPE ACCU DELAY {0.44 ns} LIBRARY_DELAY {0.44 ns} PAR 0-4427 XREFS 30639 LOC {2 0.56115605 2 0.629751175 2 0.629751175 2 0.6569970520708271 2 0.6569970520708271} PREDS {{146 0 0-5595 {}} {258 0 0-5907 {}} {259 0 0-5908 {}}} SUCCS {{258 0 0-5912 {}}} CYCLES {}}
+set a(0-5910) {NAME intensity:slc(intensity#2.sg1)#10 TYPE READSLICE PAR 0-4427 XREFS 30640 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.6569971} PREDS {{146 0 0-5595 {}} {258 0 0-5870 {}}} SUCCS {{259 0 0-5911 {}}} CYCLES {}}
+set a(0-5911) {NAME FRAME:not#6 TYPE NOT PAR 0-4427 XREFS 30641 LOC {2 0.340472025 2 0.6569971 2 0.6569971 2 0.6569971} PREDS {{146 0 0-5595 {}} {259 0 0-5910 {}}} SUCCS {{259 0 0-5912 {}}} CYCLES {}}
+set a(0-5912) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,1,6) AREA_SCORE 5.00 QUANTITY 13 NAME FRAME:acc#11 TYPE ACCU DELAY {0.53 ns} LIBRARY_DELAY {0.53 ns} PAR 0-4427 XREFS 30642 LOC {2 0.588401975 2 0.6569971 2 0.6569971 2 0.6900338701789505 2 0.6900338701789505} PREDS {{146 0 0-5595 {}} {258 0 0-5909 {}} {259 0 0-5911 {}}} SUCCS {{258 0 0-5915 {}}} CYCLES {}}
+set a(0-5913) {NAME FRAME:slc(acc.imod#12)#4 TYPE READSLICE PAR 0-4427 XREFS 30643 LOC {2 0.5228665499999999 2 0.591461675 2 0.591461675 2 0.6900339249999999} PREDS {{146 0 0-5595 {}} {258 0 0-5888 {}}} SUCCS {{259 0 0-5914 {}}} CYCLES {}}
+set a(0-5914) {NAME FRAME:conc#12 TYPE CONCATENATE PAR 0-4427 XREFS 30644 LOC {2 0.5228665499999999 2 0.6900339249999999 2 0.6900339249999999 2 0.6900339249999999} PREDS {{146 0 0-5595 {}} {259 0 0-5913 {}}} SUCCS {{259 0 0-5915 {}}} CYCLES {}}
+set a(0-5915) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,1,7) AREA_SCORE 6.00 QUANTITY 14 NAME FRAME:acc#12 TYPE ACCU DELAY {0.61 ns} LIBRARY_DELAY {0.61 ns} PAR 0-4427 XREFS 30645 LOC {2 0.6214388 2 0.6900339249999999 2 0.6900339249999999 2 0.728323384496936 2 0.728323384496936} PREDS {{146 0 0-5595 {}} {258 0 0-5912 {}} {259 0 0-5914 {}}} SUCCS {{259 0 0-5916 {}}} CYCLES {}}
+set a(0-5916) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,1,8) AREA_SCORE 7.00 QUANTITY 8 NAME FRAME:acc#13 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-4427 XREFS 30646 LOC {2 0.6597282999999999 2 0.7283234249999999 2 0.7283234249999999 2 0.7715251484103023 2 0.7715251484103023} PREDS {{146 0 0-5595 {}} {258 0 0-5893 {}} {259 0 0-5915 {}}} SUCCS {{259 0 0-5917 {}}} CYCLES {}}
+set a(0-5917) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 1 NAME FRAME:acc#14 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-4427 XREFS 30647 LOC {2 0.7029300749999999 2 0.7715251999999999 2 0.7715251999999999 2 0.8385535568650199 2 0.8385535568650199} PREDS {{146 0 0-5595 {}} {258 0 0-5892 {}} {259 0 0-5916 {}}} SUCCS {{259 0 0-5918 {}}} CYCLES {}}
+set a(0-5918) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,11,1,13) AREA_SCORE 12.00 QUANTITY 6 NAME FRAME:acc#15 TYPE ACCU DELAY {1.04 ns} LIBRARY_DELAY {1.04 ns} PAR 0-4427 XREFS 30648 LOC {2 0.7699584749999999 2 0.8385536 2 0.8385536 2 0.9037692313734284 2 0.9037692313734284} PREDS {{146 0 0-5595 {}} {258 0 0-5890 {}} {259 0 0-5917 {}}} SUCCS {{258 0 0-5925 {}}} CYCLES {}}
+set a(0-5919) {NAME intensity:slc(intensity#2.sg1)#12 TYPE READSLICE PAR 0-4427 XREFS 30649 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.9037692749999999} PREDS {{146 0 0-5595 {}} {258 0 0-5870 {}}} SUCCS {{258 0 0-5923 {}}} CYCLES {}}
+set a(0-5920) {NAME intensity:slc(intensity#2.sg1)#13 TYPE READSLICE PAR 0-4427 XREFS 30650 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.9037692749999999} PREDS {{146 0 0-5595 {}} {258 0 0-5870 {}}} SUCCS {{259 0 0-5921 {}}} CYCLES {}}
+set a(0-5921) {NAME FRAME:exs#1 TYPE SIGNEXTEND PAR 0-4427 XREFS 30651 LOC {2 0.340472025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-5595 {}} {259 0 0-5920 {}}} SUCCS {{258 0 0-5923 {}}} CYCLES {}}
+set a(0-5922) {NAME intensity:slc(intensity#2.sg1)#8 TYPE READSLICE PAR 0-4427 XREFS 30652 LOC {2 0.340472025 2 0.40906715 2 0.40906715 2 0.9037692749999999} PREDS {{146 0 0-5595 {}} {258 0 0-5870 {}}} SUCCS {{259 0 0-5923 {}}} CYCLES {}}
+set a(0-5923) {NAME FRAME:conc#2 TYPE CONCATENATE PAR 0-4427 XREFS 30653 LOC {2 0.340472025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-5595 {}} {258 0 0-5921 {}} {258 0 0-5919 {}} {259 0 0-5922 {}}} SUCCS {{259 0 0-5924 {}}} CYCLES {}}
+set a(0-5924) {NAME FRAME:exs TYPE SIGNEXTEND PAR 0-4427 XREFS 30654 LOC {2 0.340472025 2 0.9037692749999999 2 0.9037692749999999 2 0.9037692749999999} PREDS {{146 0 0-5595 {}} {259 0 0-5923 {}}} SUCCS {{259 0 0-5925 {}}} CYCLES {}}
+set a(0-5925) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,1,12,1,13) AREA_SCORE 13.00 QUANTITY 7 NAME FRAME:acc#2 TYPE ACCU DELAY {1.27 ns} LIBRARY_DELAY {1.27 ns} PAR 0-4427 XREFS 30655 LOC {2 0.83517415 2 0.9037692749999999 2 0.9037692749999999 2 0.9832574784997776 2 0.9832574784997776} PREDS {{146 0 0-5595 {}} {258 0 0-5918 {}} {259 0 0-5924 {}}} SUCCS {{259 0 0-5926 {}} {258 0 0-5927 {}} {258 0 0-5930 {}} {258 0 0-5931 {}} {258 0 0-5932 {}} {258 0 0-5935 {}}} CYCLES {}}
+set a(0-5926) {NAME intensity:slc(intensity) TYPE READSLICE PAR 0-4427 XREFS 30656 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-5595 {}} {259 0 0-5925 {}}} SUCCS {{258 0 0-5929 {}}} CYCLES {}}
+set a(0-5927) {NAME intensity:slc(intensity)#1 TYPE READSLICE PAR 0-4427 XREFS 30657 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-5595 {}} {258 0 0-5925 {}}} SUCCS {{259 0 0-5928 {}}} CYCLES {}}
+set a(0-5928) {NAME FRAME:exu TYPE PADZEROES PAR 0-4427 XREFS 30658 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-5595 {}} {259 0 0-5927 {}}} SUCCS {{259 0 0-5929 {}}} CYCLES {}}
+set a(0-5929) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(10,2) AREA_SCORE 7.30 QUANTITY 1 NAME FRAME:or TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-4427 XREFS 30659 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{146 0 0-5595 {}} {258 0 0-5926 {}} {259 0 0-5928 {}}} SUCCS {{258 0 0-5936 {}}} CYCLES {}}
+set a(0-5930) {NAME intensity:slc(intensity)#2 TYPE READSLICE PAR 0-4427 XREFS 30660 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 1.0} PREDS {{146 0 0-5595 {}} {258 0 0-5925 {}}} SUCCS {{258 0 0-5936 {}}} CYCLES {}}
+set a(0-5931) {NAME intensity:slc(intensity)#3 TYPE READSLICE PAR 0-4427 XREFS 30661 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-5595 {}} {258 0 0-5925 {}}} SUCCS {{258 0 0-5934 {}}} CYCLES {}}
+set a(0-5932) {NAME intensity:slc(intensity)#4 TYPE READSLICE PAR 0-4427 XREFS 30662 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-5595 {}} {258 0 0-5925 {}}} SUCCS {{259 0 0-5933 {}}} CYCLES {}}
+set a(0-5933) {NAME FRAME:exu#6 TYPE PADZEROES PAR 0-4427 XREFS 30663 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-5595 {}} {259 0 0-5932 {}}} SUCCS {{259 0 0-5934 {}}} CYCLES {}}
+set a(0-5934) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(6,2) AREA_SCORE 4.38 QUANTITY 1 NAME FRAME:or#3 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-4427 XREFS 30664 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{146 0 0-5595 {}} {258 0 0-5931 {}} {259 0 0-5933 {}}} SUCCS {{258 0 0-5936 {}}} CYCLES {}}
+set a(0-5935) {NAME intensity:slc(intensity)#5 TYPE READSLICE PAR 0-4427 XREFS 30665 LOC {2 0.9146624 2 0.983257525 2 0.983257525 2 1.0} PREDS {{146 0 0-5595 {}} {258 0 0-5925 {}}} SUCCS {{259 0 0-5936 {}}} CYCLES {}}
+set a(0-5936) {NAME FRAME:conc#11 TYPE CONCATENATE PAR 0-4427 XREFS 30666 LOC {2 0.9314048749999999 2 1.0 2 1.0 2 1.0} PREDS {{146 0 0-5595 {}} {258 0 0-5934 {}} {258 0 0-5930 {}} {258 0 0-5929 {}} {259 0 0-5935 {}}} SUCCS {{259 0 0-5937 {}}} CYCLES {}}
+set a(0-5937) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(2,30) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_write(vout:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-4427 XREFS 30667 LOC {2 1.0 2 1.0 2 1.0 3 0.0 2 0.9999} PREDS {{130 0 0-5595 {}} {260 0 0-5937 {}} {259 0 0-5936 {}}} SUCCS {{260 0 0-5937 {}}} CYCLES {}}
+set a(0-5938) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(19,0,2,1,19) AREA_SCORE 20.00 QUANTITY 1 NAME FRAME:acc#4 TYPE ACCU DELAY {1.91 ns} LIBRARY_DELAY {1.91 ns} PAR 0-4427 XREFS 30668 LOC {1 0.0641255 1 0.805295525 1 0.805295525 1 0.9245548410815966 1 0.9245548410815966} PREDS {{146 0 0-5595 {}} {258 0 0-4448 {}}} SUCCS {{259 0 0-5939 {}} {258 0 0-5959 {}}} CYCLES {}}
+set a(0-5939) {NAME FRAME:p:slc(FRAME:p)#1 TYPE READSLICE PAR 0-4427 XREFS 30669 LOC {1 0.183384875 1 0.9245549 1 0.9245549 1 0.9245549} PREDS {{146 0 0-5595 {}} {259 0 0-5938 {}}} SUCCS {{259 0 0-5940 {}}} CYCLES {}}
+set a(0-5940) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,1,10) AREA_SCORE 9.00 QUANTITY 11 NAME FRAME:acc TYPE ACCU DELAY {0.84 ns} LIBRARY_DELAY {0.84 ns} PAR 0-4427 XREFS 30670 LOC {1 0.183384875 1 0.9245549 1 0.9245549 1 0.9769393527684257 1 0.9769393527684257} PREDS {{146 0 0-5595 {}} {259 0 0-5939 {}}} SUCCS {{259 0 0-5941 {}}} CYCLES {}}
+set a(0-5941) {NAME FRAME:slc TYPE READSLICE PAR 0-4427 XREFS 30671 LOC {1 0.23576937499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9769393999999999} PREDS {{146 0 0-5595 {}} {259 0 0-5940 {}}} SUCCS {{259 0 0-5942 {}}} CYCLES {}}
+set a(0-5942) {NAME FRAME:not TYPE NOT PAR 0-4427 XREFS 30672 LOC {1 0.23576937499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9769393999999999} PREDS {{146 0 0-5595 {}} {259 0 0-5941 {}}} SUCCS {{258 0 0-5945 {}} {258 0 0-5946 {}}} CYCLES {}}
+set a(0-5943) {NAME not#1 TYPE NOT PAR 0-4427 XREFS 30673 LOC {1 0.0 1 0.0 1 0.0 1 0.9769393999999999} PREDS {{258 0 0-4450 {}}} SUCCS {{259 0 0-5944 {}}} CYCLES {}}
+set a(0-5944) {NAME FRAME:for:and#2 TYPE AND PAR 0-4427 XREFS 30674 LOC {1 0.0 1 0.0 1 0.0 1 0.9769393999999999} PREDS {{262 0 0-5966 {}} {259 0 0-5943 {}}} SUCCS {{259 0 0-5945 {}} {256 0 0-5966 {}}} CYCLES {}}
+set a(0-5945) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 2 NAME FRAME:for:mux#44 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30675 LOC {1 0.23576937499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 1 0.9999999624999999} PREDS {{258 0 0-5594 {}} {258 0 0-5942 {}} {258 0 0-4428 {}} {259 0 0-5944 {}}} SUCCS {{258 0 0-5966 {}} {258 0 0-5968 {}}} CYCLES {}}
+set a(0-5946) {NAME not#2 TYPE NOT PAR 0-4427 XREFS 30676 LOC {1 0.23576937499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9769393999999999} PREDS {{258 0 0-5942 {}} {258 0 0-4428 {}}} SUCCS {{259 0 0-5947 {}}} CYCLES {}}
+set a(0-5947) {NAME FRAME:for:or#1 TYPE OR PAR 0-4427 XREFS 30677 LOC {1 0.23576937499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9769393999999999} PREDS {{258 0 0-5594 {}} {259 0 0-5946 {}}} SUCCS {{259 0 0-5948 {}}} CYCLES {}}
+set a(0-5948) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 2 NAME FRAME:for:mux#45 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30678 LOC {1 0.23576937499999998 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 1 0.9999999624999999} PREDS {{258 0 0-5594 {}} {259 0 0-5947 {}}} SUCCS {{258 0 0-5967 {}} {258 0 0-5968 {}}} CYCLES {}}
+set a(0-5949) {NAME FRAME:for:asn(acc.imod#6.lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30679 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 2 0.59843245} PREDS {{260 0 0-5949 {}} {258 0 0-5494 {}}} SUCCS {{262 0 0-5494 {}} {260 0 0-5949 {}}} CYCLES {}}
+set a(0-5950) {NAME FRAME:for:asn(acc.imod#7.lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30680 LOC {1 0.39747262499999997 1 0.433986675 1 0.433986675 2 0.59843245} PREDS {{260 0 0-5950 {}} {258 0 0-5495 {}}} SUCCS {{262 0 0-5495 {}} {260 0 0-5950 {}}} CYCLES {}}
+set a(0-5951) {NAME FRAME:for:asn(regs.regs(0).sva) TYPE ASSIGN PAR 0-4427 XREFS 30681 LOC {1 0.0230606 1 0.57525635 1 0.57525635 2 0.6501168749999999} PREDS {{260 0 0-5951 {}} {256 0 0-5496 {}} {256 0 0-5498 {}} {258 0 0-5497 {}}} SUCCS {{262 0 0-5496 {}} {262 0 0-5498 {}} {260 0 0-5951 {}}} CYCLES {}}
+set a(0-5952) {NAME FRAME:for:asn(regs.regs(1).sva) TYPE ASSIGN PAR 0-4427 XREFS 30682 LOC {1 0.0230606 1 0.57525635 1 0.57525635 2 0.15038815} PREDS {{260 0 0-5952 {}} {256 0 0-4678 {}} {256 0 0-4680 {}} {256 0 0-4683 {}} {256 0 0-4753 {}} {256 0 0-4755 {}} {256 0 0-4758 {}} {256 0 0-4825 {}} {256 0 0-4827 {}} {256 0 0-4830 {}} {256 0 0-5499 {}} {256 0 0-5501 {}} {258 0 0-5500 {}}} SUCCS {{262 0 0-4678 {}} {262 0 0-4680 {}} {262 0 0-4683 {}} {262 0 0-4753 {}} {262 0 0-4755 {}} {262 0 0-4758 {}} {262 0 0-4825 {}} {262 0 0-4827 {}} {262 0 0-4830 {}} {262 0 0-5499 {}} {262 0 0-5501 {}} {260 0 0-5952 {}}} CYCLES {}}
+set a(0-5953) {NAME FRAME:for:asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30683 LOC {1 0.0230606 1 0.57525635 1 0.57525635 2 0.6501168749999999} PREDS {{260 0 0-5953 {}} {258 0 0-5502 {}}} SUCCS {{262 0 0-5502 {}} {260 0 0-5953 {}}} CYCLES {}}
+set a(0-5954) {NAME FRAME:for:asn(in(0).lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30684 LOC {2 0.128961425 2 0.303457375 2 0.303457375 3 0.17449594999999998} PREDS {{260 0 0-5954 {}} {256 0 0-5549 {}} {258 0 0-5550 {}}} SUCCS {{262 0 0-5549 {}} {260 0 0-5954 {}}} CYCLES {}}
+set a(0-5955) {NAME FRAME:for:asn(in(2).lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30685 LOC {2 0.128961425 2 0.19755655 2 0.19755655 3 0.06859512499999999} PREDS {{260 0 0-5955 {}} {256 0 0-5587 {}} {258 0 0-5588 {}}} SUCCS {{262 0 0-5587 {}} {260 0 0-5955 {}}} CYCLES {}}
+set a(0-5956) {NAME FRAME:for:asn(ACC1:acc#118.psp.lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30686 LOC {1 0.34298077499999996 1 0.57964955 1 0.57964955 2 0.744095325} PREDS {{260 0 0-5956 {}} {258 0 0-5503 {}}} SUCCS {{262 0 0-5503 {}} {260 0 0-5956 {}}} CYCLES {}}
+set a(0-5957) {NAME FRAME:for:asn(ACC1:acc#125.psp.lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30687 LOC {1 0.16961555 1 0.3151275 1 0.3151275 2 0.47957327499999997} PREDS {{260 0 0-5957 {}} {258 0 0-5504 {}}} SUCCS {{262 0 0-5504 {}} {260 0 0-5957 {}}} CYCLES {}}
+set a(0-5958) {NAME FRAME:for:asn(ACC1:acc#110.psp#1.lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30688 LOC {1 0.281724925 1 0.433986675 1 0.433986675 2 0.59843245} PREDS {{260 0 0-5958 {}} {258 0 0-5505 {}}} SUCCS {{262 0 0-5505 {}} {260 0 0-5958 {}}} CYCLES {}}
+set a(0-5959) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(19,1,2) AREA_SCORE 17.47 QUANTITY 1 NAME FRAME:for:mux#42 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-4427 XREFS 30689 LOC {1 0.183384875 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.7888887124999999} PREDS {{260 0 0-5959 {}} {258 0 0-5594 {}} {258 0 0-4448 {}} {258 0 0-5938 {}} {258 0 0-4429 {}}} SUCCS {{262 0 0-4448 {}} {260 0 0-5959 {}}} CYCLES {}}
+set a(0-5960) {NAME FRAME:for:asn(i#6.lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30690 LOC {1 0.036879575 1 0.287881575 1 0.287881575 2 0.438508375} PREDS {{260 0 0-5960 {}} {256 0 0-5508 {}} {258 0 0-5589 {}}} SUCCS {{262 0 0-5508 {}} {260 0 0-5960 {}}} CYCLES {}}
+set a(0-5961) {NAME FRAME:for:asn(acc.imod#18.lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30691 LOC {1 0.37022669999999996 1 0.433986675 1 0.433986675 2 0.59843245} PREDS {{260 0 0-5961 {}} {258 0 0-5509 {}}} SUCCS {{262 0 0-5509 {}} {260 0 0-5961 {}}} CYCLES {}}
+set a(0-5962) {NAME FRAME:for:asn(acc.imod#20.lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30692 LOC {1 0.39747262499999997 1 0.4804293 1 0.4804293 2 0.644875075} PREDS {{260 0 0-5962 {}} {258 0 0-5510 {}}} SUCCS {{262 0 0-5510 {}} {260 0 0-5962 {}}} CYCLES {}}
+set a(0-5963) {NAME FRAME:for:asn(ACC1:acc#118.psp#1.lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30693 LOC {1 0.34298077499999996 1 0.58544045 1 0.58544045 2 0.749886225} PREDS {{260 0 0-5963 {}} {258 0 0-5511 {}}} SUCCS {{262 0 0-5511 {}} {260 0 0-5963 {}}} CYCLES {}}
+set a(0-5964) {NAME FRAME:for:asn(ACC1:acc#125.psp#1.lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30694 LOC {1 0.16961555 1 0.3151275 1 0.3151275 2 0.47957327499999997} PREDS {{260 0 0-5964 {}} {258 0 0-5512 {}}} SUCCS {{262 0 0-5512 {}} {260 0 0-5964 {}}} CYCLES {}}
+set a(0-5965) {NAME FRAME:for:asn(ACC1:acc#110.psp#2.lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30695 LOC {1 0.281724925 1 0.433986675 1 0.433986675 2 0.59843245} PREDS {{260 0 0-5965 {}} {258 0 0-5513 {}}} SUCCS {{262 0 0-5513 {}} {260 0 0-5965 {}}} CYCLES {}}
+set a(0-5966) {NAME FRAME:for:asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30696 LOC {1 0.258829975 1 1.0 1 1.0 2 0.9769393999999999} PREDS {{260 0 0-5966 {}} {256 0 0-5944 {}} {258 0 0-5945 {}}} SUCCS {{262 0 0-5944 {}} {260 0 0-5966 {}}} CYCLES {}}
+set a(0-5967) {NAME FRAME:for:asn(exit:FRAME:for.lpi#1) TYPE ASSIGN PAR 0-4427 XREFS 30697 LOC {1 0.258829975 1 1.0 1 1.0 2 0.013988325} PREDS {{260 0 0-5967 {}} {256 0 0-4450 {}} {258 0 0-5948 {}}} SUCCS {{262 0 0-4450 {}} {260 0 0-5967 {}}} CYCLES {}}
+set a(0-5968) {NAME FRAME:and TYPE AND PAR 0-4427 XREFS 30698 LOC {1 0.258829975 1 1.0 1 1.0 2 0.013988325} PREDS {{258 0 0-5945 {}} {258 0 0-5948 {}}} SUCCS {{259 0 0-5969 {}}} CYCLES {}}
+set a(0-5969) {NAME FRAME:asn#3 TYPE ASSIGN PAR 0-4427 XREFS 30699 LOC {1 0.258829975 1 1.0 1 1.0 2 0.013988325} PREDS {{260 0 0-5969 {}} {256 0 0-4443 {}} {256 0 0-4445 {}} {256 0 0-4449 {}} {259 0 0-5968 {}}} SUCCS {{262 0 0-4443 {}} {262 0 0-4445 {}} {262 0 0-4449 {}} {260 0 0-5969 {}}} CYCLES {}}
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0-5283 0-5284 0-5285 0-5286 0-5287 0-5288 0-5289 0-5290 0-5291 0-5292 0-5293 0-5294 0-5295 0-5296 0-5297 0-5298 0-5299 0-5300 0-5301 0-5302 0-5303 0-5304 0-5305 0-5306 0-5307 0-5308 0-5309 0-5310 0-5311 0-5312 0-5313 0-5314 0-5315 0-5316 0-5317 0-5318 0-5319 0-5320 0-5321 0-5322 0-5323 0-5324 0-5325 0-5326 0-5327 0-5328 0-5329 0-5330 0-5331 0-5332 0-5333 0-5334 0-5335 0-5336 0-5337 0-5338 0-5339 0-5340 0-5341 0-5342 0-5343 0-5344 0-5345 0-5346 0-5347 0-5348 0-5349 0-5350 0-5351 0-5352 0-5353 0-5354 0-5355 0-5356 0-5357 0-5358 0-5359 0-5360 0-5361 0-5362 0-5363 0-5364 0-5365 0-5366 0-5367 0-5368 0-5369 0-5370 0-5371 0-5372 0-5373 0-5374 0-5375 0-5376 0-5377 0-5378 0-5379 0-5380 0-5381 0-5382 0-5383 0-5384 0-5385 0-5386 0-5387 0-5388 0-5389 0-5390 0-5391 0-5392 0-5393 0-5394 0-5395 0-5396 0-5397 0-5398 0-5399 0-5400 0-5401 0-5402 0-5403 0-5404 0-5405 0-5406 0-5407 0-5408 0-5409 0-5410 0-5411 0-5412 0-5413 0-5414 0-5415 0-5416 0-5417 0-5418 0-5419 0-5420 0-5421 0-5422 0-5423 0-5424 0-5425 0-5426 0-5427 0-5428 0-5429 0-5430 0-5431 0-5432 0-5433 0-5434 0-5435 0-5436 0-5437 0-5438 0-5439 0-5440 0-5441 0-5442 0-5443 0-5444 0-5445 0-5446 0-5447 0-5448 0-5449 0-5450 0-5451 0-5452 0-5453 0-5454 0-5455 0-5456 0-5457 0-5458 0-5459 0-5460 0-5461 0-5462 0-5463 0-5464 0-5465 0-5466 0-5467 0-5468 0-5469 0-5470 0-5471 0-5472 0-5473 0-5474 0-5475 0-5476 0-5477 0-5478 0-5479 0-5480 0-5481 0-5482 0-5483 0-5484 0-5485 0-5486 0-5487 0-5488 0-5489 0-5490 0-5491 0-5492 0-5493 0-5494 0-5495 0-5496 0-5497 0-5498 0-5499 0-5500 0-5501 0-5502 0-5503 0-5504 0-5505 0-5506 0-5507 0-5508 0-5509 0-5510 0-5511 0-5512 0-5513 0-5514 0-5515 0-5516 0-5517 0-5518 0-5519 0-5520 0-5521 0-5522 0-5523 0-5524 0-5525 0-5526 0-5527 0-5528 0-5529 0-5530 0-5531 0-5532 0-5533 0-5534 0-5535 0-5536 0-5537 0-5538 0-5539 0-5540 0-5541 0-5542 0-5543 0-5544 0-5545 0-5546 0-5547 0-5548 0-5549 0-5550 0-5551 0-5552 0-5553 0-5554 0-5555 0-5556 0-5557 0-5558 0-5559 0-5560 0-5561 0-5562 0-5563 0-5564 0-5565 0-5566 0-5567 0-5568 0-5569 0-5570 0-5571 0-5572 0-5573 0-5574 0-5575 0-5576 0-5577 0-5578 0-5579 0-5580 0-5581 0-5582 0-5583 0-5584 0-5585 0-5586 0-5587 0-5588 0-5589 0-5590 0-5591 0-5592 0-5593 0-5594 0-5595 0-5596 0-5597 0-5598 0-5599 0-5600 0-5601 0-5602 0-5603 0-5604 0-5605 0-5606 0-5607 0-5608 0-5609 0-5610 0-5611 0-5612 0-5613 0-5614 0-5615 0-5616 0-5617 0-5618 0-5619 0-5620 0-5621 0-5622 0-5623 0-5624 0-5625 0-5626 0-5627 0-5628 0-5629 0-5630 0-5631 0-5632 0-5633 0-5634 0-5635 0-5636 0-5637 0-5638 0-5639 0-5640 0-5641 0-5642 0-5643 0-5644 0-5645 0-5646 0-5647 0-5648 0-5649 0-5650 0-5651 0-5652 0-5653 0-5654 0-5655 0-5656 0-5657 0-5658 0-5659 0-5660 0-5661 0-5662 0-5663 0-5664 0-5665 0-5666 0-5667 0-5668 0-5669 0-5670 0-5671 0-5672 0-5673 0-5674 0-5675 0-5676 0-5677 0-5678 0-5679 0-5680 0-5681 0-5682 0-5683 0-5684 0-5685 0-5686 0-5687 0-5688 0-5689 0-5690 0-5691 0-5692 0-5693 0-5694 0-5695 0-5696 0-5697 0-5698 0-5699 0-5700 0-5701 0-5702 0-5703 0-5704 0-5705 0-5706 0-5707 0-5708 0-5709 0-5710 0-5711 0-5712 0-5713 0-5714 0-5715 0-5716 0-5717 0-5718 0-5719 0-5720 0-5721 0-5722 0-5723 0-5724 0-5725 0-5726 0-5727 0-5728 0-5729 0-5730 0-5731 0-5732 0-5733 0-5734 0-5735 0-5736 0-5737 0-5738 0-5739 0-5740 0-5741 0-5742 0-5743 0-5744 0-5745 0-5746 0-5747 0-5748 0-5749 0-5750 0-5751 0-5752 0-5753 0-5754 0-5755 0-5756 0-5757 0-5758 0-5759 0-5760 0-5761 0-5762 0-5763 0-5764 0-5765 0-5766 0-5767 0-5768 0-5769 0-5770 0-5771 0-5772 0-5773 0-5774 0-5775 0-5776 0-5777 0-5778 0-5779 0-5780 0-5781 0-5782 0-5783 0-5784 0-5785 0-5786 0-5787 0-5788 0-5789 0-5790 0-5791 0-5792 0-5793 0-5794 0-5795 0-5796 0-5797 0-5798 0-5799 0-5800 0-5801 0-5802 0-5803 0-5804 0-5805 0-5806 0-5807 0-5808 0-5809 0-5810 0-5811 0-5812 0-5813 0-5814 0-5815 0-5816 0-5817 0-5818 0-5819 0-5820 0-5821 0-5822 0-5823 0-5824 0-5825 0-5826 0-5827 0-5828 0-5829 0-5830 0-5831 0-5832 0-5833 0-5834 0-5835 0-5836 0-5837 0-5838 0-5839 0-5840 0-5841 0-5842 0-5843 0-5844 0-5845 0-5846 0-5847 0-5848 0-5849 0-5850 0-5851 0-5852 0-5853 0-5854 0-5855 0-5856 0-5857 0-5858 0-5859 0-5860 0-5861 0-5862 0-5863 0-5864 0-5865 0-5866 0-5867 0-5868 0-5869 0-5870 0-5871 0-5872 0-5873 0-5874 0-5875 0-5876 0-5877 0-5878 0-5879 0-5880 0-5881 0-5882 0-5883 0-5884 0-5885 0-5886 0-5887 0-5888 0-5889 0-5890 0-5891 0-5892 0-5893 0-5894 0-5895 0-5896 0-5897 0-5898 0-5899 0-5900 0-5901 0-5902 0-5903 0-5904 0-5905 0-5906 0-5907 0-5908 0-5909 0-5910 0-5911 0-5912 0-5913 0-5914 0-5915 0-5916 0-5917 0-5918 0-5919 0-5920 0-5921 0-5922 0-5923 0-5924 0-5925 0-5926 0-5927 0-5928 0-5929 0-5930 0-5931 0-5932 0-5933 0-5934 0-5935 0-5936 0-5937 0-5938 0-5939 0-5940 0-5941 0-5942 0-5943 0-5944 0-5945 0-5946 0-5947 0-5948 0-5949 0-5950 0-5951 0-5952 0-5953 0-5954 0-5955 0-5956 0-5957 0-5958 0-5959 0-5960 0-5961 0-5962 0-5963 0-5964 0-5965 0-5966 0-5967 0-5968 0-5969} ITERATIONS Infinite LATENCY 921601 RESET_LATENCY 0 CSTEPS 3 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 921600 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 3.0 CYCLES_IN 921602 TOTAL_CYCLES_IN 921602 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 921602 NAME main TYPE LOOP DELAY {18432060.00 ns} PAR 0-4406 XREFS 30700 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{258 0 0-4421 {}} {258 0 0-4408 {}} {258 0 0-4409 {}} {258 0 0-4418 {}} {258 0 0-4419 {}} {258 0 0-4417 {}} {258 0 0-4415 {}} {258 0 0-4416 {}} {258 0 0-4407 {}} {258 0 0-4413 {}} {258 0 0-4414 {}} {258 0 0-4412 {}} {258 0 0-4420 {}} {258 0 0-4425 {}} {258 0 0-4410 {}} {258 0 0-4411 {}} {258 0 0-4424 {}} {258 0 0-4422 {}} {258 0 0-4423 {}} {259 0 0-4426 {}}} SUCCS {{772 0 0-4407 {}} {772 0 0-4408 {}} {772 0 0-4409 {}} {772 0 0-4410 {}} {772 0 0-4411 {}} {772 0 0-4412 {}} {772 0 0-4413 {}} {772 0 0-4414 {}} {772 0 0-4415 {}} {772 0 0-4416 {}} {772 0 0-4417 {}} {772 0 0-4418 {}} {772 0 0-4419 {}} {772 0 0-4420 {}} {772 0 0-4421 {}} {772 0 0-4422 {}} {772 0 0-4423 {}} {772 0 0-4424 {}} {772 0 0-4425 {}} {772 0 0-4426 {}}} CYCLES {}}
+set a(0-4406) {CHI {0-4407 0-4408 0-4409 0-4410 0-4411 0-4412 0-4413 0-4414 0-4415 0-4416 0-4417 0-4418 0-4419 0-4420 0-4421 0-4422 0-4423 0-4424 0-4425 0-4426 0-4427} ITERATIONS Infinite LATENCY 921601 RESET_LATENCY 0 CSTEPS 0 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 921600 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 0 TOTAL_CYCLES_IN 0 TOTAL_CYCLES_UNDER 921602 TOTAL_CYCLES 921602 NAME core:rlp TYPE LOOP DELAY {18432060.00 ns} PAR {} XREFS 30701 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-4406-TOTALCYCLES) {921602}
+set a(0-4406-QMOD) {mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2) 0-4448 mgc_ioport.mgc_in_wire(1,90) 0-4452 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11) {0-4457 0-4460 0-4533 0-4536 0-4606 0-4609 0-4682 0-4757 0-4829} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12) {0-4461 0-4537 0-4610 0-4685 0-4760 0-4832 0-5578} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4) {0-4469 0-4512 0-4585 0-4618 0-4661 0-4693 0-4736 0-4808 0-4840 0-4883 0-5589} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5) {0-4476 0-4625 0-4700 0-4847 0-4925 0-5068 0-5222 0-5365} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3) {0-4485 0-4494 0-4508 0-4548 0-4562 0-4581 0-4634 0-4643 0-4657 0-4709 0-4718 0-4732 0-4771 0-4785 0-4804 0-4856 0-4865 0-4879 0-4935 0-4957 0-5078 0-5100 0-5232 0-5254 0-5375 0-5397} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4) {0-4499 0-4648 0-4723 0-4870 0-4969 0-4971 0-5011 0-5021 0-5023 0-5031 0-5040 0-5042 0-5112 0-5114 0-5158 0-5168 0-5170 0-5178 0-5187 0-5189 0-5266 0-5268 0-5308 0-5318 0-5320 0-5328 0-5337 0-5339 0-5409 0-5411 0-5455 0-5465 0-5467 0-5475 0-5484 0-5486 0-5636 0-5645 0-5647 0-5655 0-5668 0-5670 0-5682 0-5691 0-5693 0-5701 0-5710 0-5712 0-5723 0-5732 0-5734 0-5742 0-5751 0-5753 0-5762 0-5771 0-5773 0-5783 0-5874 0-5886} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6) {0-4501 0-4553 0-4650 0-4725 0-4776 0-4872 0-4936 0-5079 0-5233 0-5376 0-5813 0-5823 0-5912} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5) {0-4518 0-4527 0-4569 0-4591 0-4600 0-4667 0-4676 0-4742 0-4751 0-4792 0-4814 0-4823 0-4889 0-4898 0-4923 0-5066 0-5220 0-5363 0-5592 0-5821 0-5881 0-5909} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7) {0-4573 0-4796 0-4937 0-4972 0-5080 0-5115 0-5234 0-5269 0-5377 0-5412 0-5849 0-5887 0-5903 0-5915} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4) {0-4910 0-4913 0-5053 0-5056 0-5207 0-5210 0-5350 0-5353} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9) {0-4943 0-4973 0-5086 0-5116 0-5240 0-5270 0-5383 0-5413 0-5715 0-5856} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10) {0-4974 0-5045 0-5117 0-5192 0-5271 0-5342 0-5414 0-5489 0-5622 0-5825 0-5940} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11) {0-4982 0-5118 0-5279 0-5415 0-5826 0-5857} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) {0-4983 0-5195 0-5280 0-5492 0-5539 0-5584 0-5925} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5) {0-5043 0-5190 0-5340 0-5487 0-5671 0-5713 0-5754 0-5797 0-5799 0-5845 0-5882} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8) {0-5044 0-5191 0-5341 0-5488 0-5824 0-5850 0-5888 0-5916} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,0,10) {0-5046 0-5193 0-5343 0-5490 0-5623} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,11) {0-5129 0-5426} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13) {0-5130 0-5194 0-5427 0-5491 0-5866 0-5918} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(3,1,2) {0-5494 0-5503 0-5509 0-5511} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2) {0-5495 0-5510} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2) {0-5497 0-5500 0-5502} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(12,1,2) {0-5504 0-5512} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(4,1,2) {0-5505 0-5513} mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2) {0-5508 0-5562} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4) {0-5530 0-5536 0-5543 0-5571 0-5576 0-5582} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12) {0-5532 0-5538 0-5545 0-5572 0-5577 0-5583} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,0,12,1,13) {0-5546 0-5827} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2) {0-5549 0-5587} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,13,1,16) {0-5550 0-5588 0-5868} mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(2,2) 0-5567 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2) {0-5598 0-5602 0-5610 0-5614 0-5830 0-5860} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13) {0-5599 0-5603 0-5611 0-5615 0-5831 0-5861 0-5890} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7) 0-5621 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6) {0-5714 0-5800} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,0,13,0,13) 0-5867 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16) 0-5869 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9) 0-5892 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10) 0-5917 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2) 0-5929 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2) 0-5934 mgc_ioport.mgc_out_stdreg(2,30) 0-5937 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19) 0-5938 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2) {0-5945 0-5948} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2) 0-5959}
+set a(0-4406-PROC_NAME) {core}
+set a(0-4406-HIER_NAME) {/sobel/core}
+set a(TOP) {0-4406}
+
diff --git a/Sobel/sobel.v8/schematic.nlv b/Sobel/sobel.v8/schematic.nlv
new file mode 100644
index 0000000..f0ad7e9
--- /dev/null
+++ b/Sobel/sobel.v8/schematic.nlv
@@ -0,0 +1,15334 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "sobel:core" "orig"
+load port {clk} input -attr xrf 32837 -attr oid 1 -attr vt d -attr @path {/sobel/sobel:core/clk}
+load port {en} input -attr xrf 32838 -attr oid 2 -attr vt d -attr @path {/sobel/sobel:core/en}
+load port {arst_n} input -attr xrf 32839 -attr oid 3 -attr vt d -attr @path {/sobel/sobel:core/arst_n}
+load portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} -attr xrf 32840 -attr oid 4 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} -attr xrf 32841 -attr oid 5 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load symbol "or(2,10)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,6)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(5:0)} input 6 {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(5:0)} input 6 {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nand(2,1)" "INTERFACE" NAND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,30)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(29:0)} input 30 {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(29:0)} input 30 {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(30,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(29:0)} input 30 {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(29:0)} input 30 {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,16)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(15:0)} input 16 {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(15:0)} input 16 {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(16,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(15:0)} input 16 {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(15:0)} input 16 {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(1,0,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,12,1,13)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,5,0,6)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,7,0,8)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,6,0,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,-1,7,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "and(3,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(4,0,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,6,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,-1,4,-1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,4,0,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,-1,8,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(13,-1,10,0,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(12:0)} input 13 {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,10)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,1,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,1,7,0,9)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,9,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,11,0,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(13,-1,13,-1,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(12:0)} input 13 {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(12:0)} input 13 {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(13,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(12:0)} input 13 {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(12:0)} input 13 {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(1,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(0:0)} input 1 {D(0)} \
+     portBus {DRa(0:0)} input 1 {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(4,10)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {A2(9:0)} input 10 {A2(9)} {A2(8)} {A2(7)} {A2(6)} {A2(5)} {A2(4)} {A2(3)} {A2(2)} {A2(1)} {A2(0)} \
+     portBus {A3(9:0)} input 10 {A3(9)} {A3(8)} {A3(7)} {A3(6)} {A3(5)} {A3(4)} {A3(3)} {A3(2)} {A3(1)} {A3(0)} \
+     portBus {S(1:0)} input.top 2 {S(1)} {S(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,11,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,-1,11,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(12,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(11:0)} input 12 {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(11:0)} input 12 {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,2,1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,2,1,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,4,-1,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,1,7,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(6:0)} input 7 {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,1,8,0,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,10,0,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,11,-1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,0,7)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(6:0)} output 7 {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,0,10,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(1,0,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,-1,11,-1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,10,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,12,-1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,12)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,1,12,1,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(13,-1,12,1,13)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(12:0)} input 13 {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(12:0)} output 13 {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(2,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(1:0)} input 2 {D(1)} {D(0)} \
+     portBus {DRa(1:0)} input 2 {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "and(2,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "reg(3,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(2:0)} input 3 {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(2:0)} input 3 {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(90,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(89:0)} input 90 {D(89)} {D(88)} {D(87)} {D(86)} {D(85)} {D(84)} {D(83)} {D(82)} {D(81)} {D(80)} {D(79)} {D(78)} {D(77)} {D(76)} {D(75)} {D(74)} {D(73)} {D(72)} {D(71)} {D(70)} {D(69)} {D(68)} {D(67)} {D(66)} {D(65)} {D(64)} {D(63)} {D(62)} {D(61)} {D(60)} {D(59)} {D(58)} {D(57)} {D(56)} {D(55)} {D(54)} {D(53)} {D(52)} {D(51)} {D(50)} {D(49)} {D(48)} {D(47)} {D(46)} {D(45)} {D(44)} {D(43)} {D(42)} {D(41)} {D(40)} {D(39)} {D(38)} {D(37)} {D(36)} {D(35)} {D(34)} {D(33)} {D(32)} {D(31)} {D(30)} {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(89:0)} input 90 {DRa(89)} {DRa(88)} {DRa(87)} {DRa(86)} {DRa(85)} {DRa(84)} {DRa(83)} {DRa(82)} {DRa(81)} {DRa(80)} {DRa(79)} {DRa(78)} {DRa(77)} {DRa(76)} {DRa(75)} {DRa(74)} {DRa(73)} {DRa(72)} {DRa(71)} {DRa(70)} {DRa(69)} {DRa(68)} {DRa(67)} {DRa(66)} {DRa(65)} {DRa(64)} {DRa(63)} {DRa(62)} {DRa(61)} {DRa(60)} {DRa(59)} {DRa(58)} {DRa(57)} {DRa(56)} {DRa(55)} {DRa(54)} {DRa(53)} {DRa(52)} {DRa(51)} {DRa(50)} {DRa(49)} {DRa(48)} {DRa(47)} {DRa(46)} {DRa(45)} {DRa(44)} {DRa(43)} {DRa(42)} {DRa(41)} {DRa(40)} {DRa(39)} {DRa(38)} {DRa(37)} {DRa(36)} {DRa(35)} {DRa(34)} {DRa(33)} {DRa(32)} {DRa(31)} {DRa(30)} {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,19)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(19,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(18:0)} input 19 {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(18:0)} input 19 {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,6,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(3)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,0,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,-1,11,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,13,1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(12:0)} input 13 {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,16,-1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,-1,6,-1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,1,16,-1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(13,1,16,-1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(12:0)} input 13 {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "or(2,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "and(2,2)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(1:0)} input 2 {A0(1)} {A0(0)} \
+     portBus {A1(1:0)} input 2 {A1(1)} {A1(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "mux(2,3)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(2:0)} input 3 {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(2:0)} input 3 {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,12)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(11:0)} input 12 {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(11:0)} input 12 {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,2)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(1:0)} input 2 {A0(1)} {A0(0)} \
+     portBus {A1(1:0)} input 2 {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "mux(2,90)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(89:0)} input 90 {A0(89)} {A0(88)} {A0(87)} {A0(86)} {A0(85)} {A0(84)} {A0(83)} {A0(82)} {A0(81)} {A0(80)} {A0(79)} {A0(78)} {A0(77)} {A0(76)} {A0(75)} {A0(74)} {A0(73)} {A0(72)} {A0(71)} {A0(70)} {A0(69)} {A0(68)} {A0(67)} {A0(66)} {A0(65)} {A0(64)} {A0(63)} {A0(62)} {A0(61)} {A0(60)} {A0(59)} {A0(58)} {A0(57)} {A0(56)} {A0(55)} {A0(54)} {A0(53)} {A0(52)} {A0(51)} {A0(50)} {A0(49)} {A0(48)} {A0(47)} {A0(46)} {A0(45)} {A0(44)} {A0(43)} {A0(42)} {A0(41)} {A0(40)} {A0(39)} {A0(38)} {A0(37)} {A0(36)} {A0(35)} {A0(34)} {A0(33)} {A0(32)} {A0(31)} {A0(30)} {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(89:0)} input 90 {A1(89)} {A1(88)} {A1(87)} {A1(86)} {A1(85)} {A1(84)} {A1(83)} {A1(82)} {A1(81)} {A1(80)} {A1(79)} {A1(78)} {A1(77)} {A1(76)} {A1(75)} {A1(74)} {A1(73)} {A1(72)} {A1(71)} {A1(70)} {A1(69)} {A1(68)} {A1(67)} {A1(66)} {A1(65)} {A1(64)} {A1(63)} {A1(62)} {A1(61)} {A1(60)} {A1(59)} {A1(58)} {A1(57)} {A1(56)} {A1(55)} {A1(54)} {A1(53)} {A1(52)} {A1(51)} {A1(50)} {A1(49)} {A1(48)} {A1(47)} {A1(46)} {A1(45)} {A1(44)} {A1(43)} {A1(42)} {A1(41)} {A1(40)} {A1(39)} {A1(38)} {A1(37)} {A1(36)} {A1(35)} {A1(34)} {A1(33)} {A1(32)} {A1(31)} {A1(30)} {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(2)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(3,1,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,0,1,1,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,-1,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(10)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,10,1,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,1,2,0,11)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,1,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,1,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,1,4,1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,8,-1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,1)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "add(19,-1,1,0,19)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(18:0)} input 19 {A(18)} {A(17)} {A(16)} {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,19)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nor(2,1)" "INTERFACE" NOR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "or(3,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load net {FRAME:p#1.lpi#1(0)} -attr vt d
+load net {FRAME:p#1.lpi#1(1)} -attr vt d
+load net {FRAME:p#1.lpi#1(2)} -attr vt d
+load net {FRAME:p#1.lpi#1(3)} -attr vt d
+load net {FRAME:p#1.lpi#1(4)} -attr vt d
+load net {FRAME:p#1.lpi#1(5)} -attr vt d
+load net {FRAME:p#1.lpi#1(6)} -attr vt d
+load net {FRAME:p#1.lpi#1(7)} -attr vt d
+load net {FRAME:p#1.lpi#1(8)} -attr vt d
+load net {FRAME:p#1.lpi#1(9)} -attr vt d
+load net {FRAME:p#1.lpi#1(10)} -attr vt d
+load net {FRAME:p#1.lpi#1(11)} -attr vt d
+load net {FRAME:p#1.lpi#1(12)} -attr vt d
+load net {FRAME:p#1.lpi#1(13)} -attr vt d
+load net {FRAME:p#1.lpi#1(14)} -attr vt d
+load net {FRAME:p#1.lpi#1(15)} -attr vt d
+load net {FRAME:p#1.lpi#1(16)} -attr vt d
+load net {FRAME:p#1.lpi#1(17)} -attr vt d
+load net {FRAME:p#1.lpi#1(18)} -attr vt d
+load netBundle {FRAME:p#1.lpi#1} 19 {FRAME:p#1.lpi#1(0)} {FRAME:p#1.lpi#1(1)} {FRAME:p#1.lpi#1(2)} {FRAME:p#1.lpi#1(3)} {FRAME:p#1.lpi#1(4)} {FRAME:p#1.lpi#1(5)} {FRAME:p#1.lpi#1(6)} {FRAME:p#1.lpi#1(7)} {FRAME:p#1.lpi#1(8)} {FRAME:p#1.lpi#1(9)} {FRAME:p#1.lpi#1(10)} {FRAME:p#1.lpi#1(11)} {FRAME:p#1.lpi#1(12)} {FRAME:p#1.lpi#1(13)} {FRAME:p#1.lpi#1(14)} {FRAME:p#1.lpi#1(15)} {FRAME:p#1.lpi#1(16)} {FRAME:p#1.lpi#1(17)} {FRAME:p#1.lpi#1(18)} -attr xrf 32842 -attr oid 6 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {regs.regs(1).sva(0)} -attr vt d
+load net {regs.regs(1).sva(1)} -attr vt d
+load net {regs.regs(1).sva(2)} -attr vt d
+load net {regs.regs(1).sva(3)} -attr vt d
+load net {regs.regs(1).sva(4)} -attr vt d
+load net {regs.regs(1).sva(5)} -attr vt d
+load net {regs.regs(1).sva(6)} -attr vt d
+load net {regs.regs(1).sva(7)} -attr vt d
+load net {regs.regs(1).sva(8)} -attr vt d
+load net {regs.regs(1).sva(9)} -attr vt d
+load net {regs.regs(1).sva(10)} -attr vt d
+load net {regs.regs(1).sva(11)} -attr vt d
+load net {regs.regs(1).sva(12)} -attr vt d
+load net {regs.regs(1).sva(13)} -attr vt d
+load net {regs.regs(1).sva(14)} -attr vt d
+load net {regs.regs(1).sva(15)} -attr vt d
+load net {regs.regs(1).sva(16)} -attr vt d
+load net {regs.regs(1).sva(17)} -attr vt d
+load net {regs.regs(1).sva(18)} -attr vt d
+load net {regs.regs(1).sva(19)} -attr vt d
+load net {regs.regs(1).sva(20)} -attr vt d
+load net {regs.regs(1).sva(21)} -attr vt d
+load net {regs.regs(1).sva(22)} -attr vt d
+load net {regs.regs(1).sva(23)} -attr vt d
+load net {regs.regs(1).sva(24)} -attr vt d
+load net {regs.regs(1).sva(25)} -attr vt d
+load net {regs.regs(1).sva(26)} -attr vt d
+load net {regs.regs(1).sva(27)} -attr vt d
+load net {regs.regs(1).sva(28)} -attr vt d
+load net {regs.regs(1).sva(29)} -attr vt d
+load net {regs.regs(1).sva(30)} -attr vt d
+load net {regs.regs(1).sva(31)} -attr vt d
+load net {regs.regs(1).sva(32)} -attr vt d
+load net {regs.regs(1).sva(33)} -attr vt d
+load net {regs.regs(1).sva(34)} -attr vt d
+load net {regs.regs(1).sva(35)} -attr vt d
+load net {regs.regs(1).sva(36)} -attr vt d
+load net {regs.regs(1).sva(37)} -attr vt d
+load net {regs.regs(1).sva(38)} -attr vt d
+load net {regs.regs(1).sva(39)} -attr vt d
+load net {regs.regs(1).sva(40)} -attr vt d
+load net {regs.regs(1).sva(41)} -attr vt d
+load net {regs.regs(1).sva(42)} -attr vt d
+load net {regs.regs(1).sva(43)} -attr vt d
+load net {regs.regs(1).sva(44)} -attr vt d
+load net {regs.regs(1).sva(45)} -attr vt d
+load net {regs.regs(1).sva(46)} -attr vt d
+load net {regs.regs(1).sva(47)} -attr vt d
+load net {regs.regs(1).sva(48)} -attr vt d
+load net {regs.regs(1).sva(49)} -attr vt d
+load net {regs.regs(1).sva(50)} -attr vt d
+load net {regs.regs(1).sva(51)} -attr vt d
+load net {regs.regs(1).sva(52)} -attr vt d
+load net {regs.regs(1).sva(53)} -attr vt d
+load net {regs.regs(1).sva(54)} -attr vt d
+load net {regs.regs(1).sva(55)} -attr vt d
+load net {regs.regs(1).sva(56)} -attr vt d
+load net {regs.regs(1).sva(57)} -attr vt d
+load net {regs.regs(1).sva(58)} -attr vt d
+load net {regs.regs(1).sva(59)} -attr vt d
+load net {regs.regs(1).sva(60)} -attr vt d
+load net {regs.regs(1).sva(61)} -attr vt d
+load net {regs.regs(1).sva(62)} -attr vt d
+load net {regs.regs(1).sva(63)} -attr vt d
+load net {regs.regs(1).sva(64)} -attr vt d
+load net {regs.regs(1).sva(65)} -attr vt d
+load net {regs.regs(1).sva(66)} -attr vt d
+load net {regs.regs(1).sva(67)} -attr vt d
+load net {regs.regs(1).sva(68)} -attr vt d
+load net {regs.regs(1).sva(69)} -attr vt d
+load net {regs.regs(1).sva(70)} -attr vt d
+load net {regs.regs(1).sva(71)} -attr vt d
+load net {regs.regs(1).sva(72)} -attr vt d
+load net {regs.regs(1).sva(73)} -attr vt d
+load net {regs.regs(1).sva(74)} -attr vt d
+load net {regs.regs(1).sva(75)} -attr vt d
+load net {regs.regs(1).sva(76)} -attr vt d
+load net {regs.regs(1).sva(77)} -attr vt d
+load net {regs.regs(1).sva(78)} -attr vt d
+load net {regs.regs(1).sva(79)} -attr vt d
+load net {regs.regs(1).sva(80)} -attr vt d
+load net {regs.regs(1).sva(81)} -attr vt d
+load net {regs.regs(1).sva(82)} -attr vt d
+load net {regs.regs(1).sva(83)} -attr vt d
+load net {regs.regs(1).sva(84)} -attr vt d
+load net {regs.regs(1).sva(85)} -attr vt d
+load net {regs.regs(1).sva(86)} -attr vt d
+load net {regs.regs(1).sva(87)} -attr vt d
+load net {regs.regs(1).sva(88)} -attr vt d
+load net {regs.regs(1).sva(89)} -attr vt d
+load netBundle {regs.regs(1).sva} 90 {regs.regs(1).sva(0)} {regs.regs(1).sva(1)} {regs.regs(1).sva(2)} {regs.regs(1).sva(3)} {regs.regs(1).sva(4)} {regs.regs(1).sva(5)} {regs.regs(1).sva(6)} {regs.regs(1).sva(7)} {regs.regs(1).sva(8)} {regs.regs(1).sva(9)} {regs.regs(1).sva(10)} {regs.regs(1).sva(11)} {regs.regs(1).sva(12)} {regs.regs(1).sva(13)} {regs.regs(1).sva(14)} {regs.regs(1).sva(15)} {regs.regs(1).sva(16)} {regs.regs(1).sva(17)} {regs.regs(1).sva(18)} {regs.regs(1).sva(19)} {regs.regs(1).sva(20)} {regs.regs(1).sva(21)} {regs.regs(1).sva(22)} {regs.regs(1).sva(23)} {regs.regs(1).sva(24)} {regs.regs(1).sva(25)} {regs.regs(1).sva(26)} {regs.regs(1).sva(27)} {regs.regs(1).sva(28)} {regs.regs(1).sva(29)} {regs.regs(1).sva(30)} {regs.regs(1).sva(31)} {regs.regs(1).sva(32)} {regs.regs(1).sva(33)} {regs.regs(1).sva(34)} {regs.regs(1).sva(35)} {regs.regs(1).sva(36)} {regs.regs(1).sva(37)} {regs.regs(1).sva(38)} {regs.regs(1).sva(39)} {regs.regs(1).sva(40)} {regs.regs(1).sva(41)} {regs.regs(1).sva(42)} {regs.regs(1).sva(43)} {regs.regs(1).sva(44)} {regs.regs(1).sva(45)} {regs.regs(1).sva(46)} {regs.regs(1).sva(47)} {regs.regs(1).sva(48)} {regs.regs(1).sva(49)} {regs.regs(1).sva(50)} {regs.regs(1).sva(51)} {regs.regs(1).sva(52)} {regs.regs(1).sva(53)} {regs.regs(1).sva(54)} {regs.regs(1).sva(55)} {regs.regs(1).sva(56)} {regs.regs(1).sva(57)} {regs.regs(1).sva(58)} {regs.regs(1).sva(59)} {regs.regs(1).sva(60)} {regs.regs(1).sva(61)} {regs.regs(1).sva(62)} {regs.regs(1).sva(63)} {regs.regs(1).sva(64)} {regs.regs(1).sva(65)} {regs.regs(1).sva(66)} {regs.regs(1).sva(67)} {regs.regs(1).sva(68)} {regs.regs(1).sva(69)} {regs.regs(1).sva(70)} {regs.regs(1).sva(71)} {regs.regs(1).sva(72)} {regs.regs(1).sva(73)} {regs.regs(1).sva(74)} {regs.regs(1).sva(75)} {regs.regs(1).sva(76)} {regs.regs(1).sva(77)} {regs.regs(1).sva(78)} {regs.regs(1).sva(79)} {regs.regs(1).sva(80)} {regs.regs(1).sva(81)} {regs.regs(1).sva(82)} {regs.regs(1).sva(83)} {regs.regs(1).sva(84)} {regs.regs(1).sva(85)} {regs.regs(1).sva(86)} {regs.regs(1).sva(87)} {regs.regs(1).sva(88)} {regs.regs(1).sva(89)} -attr xrf 32843 -attr oid 7 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -attr vt d
+load net {regs.regs(0).sva(1)} -attr vt d
+load net {regs.regs(0).sva(2)} -attr vt d
+load net {regs.regs(0).sva(3)} -attr vt d
+load net {regs.regs(0).sva(4)} -attr vt d
+load net {regs.regs(0).sva(5)} -attr vt d
+load net {regs.regs(0).sva(6)} -attr vt d
+load net {regs.regs(0).sva(7)} -attr vt d
+load net {regs.regs(0).sva(8)} -attr vt d
+load net {regs.regs(0).sva(9)} -attr vt d
+load net {regs.regs(0).sva(10)} -attr vt d
+load net {regs.regs(0).sva(11)} -attr vt d
+load net {regs.regs(0).sva(12)} -attr vt d
+load net {regs.regs(0).sva(13)} -attr vt d
+load net {regs.regs(0).sva(14)} -attr vt d
+load net {regs.regs(0).sva(15)} -attr vt d
+load net {regs.regs(0).sva(16)} -attr vt d
+load net {regs.regs(0).sva(17)} -attr vt d
+load net {regs.regs(0).sva(18)} -attr vt d
+load net {regs.regs(0).sva(19)} -attr vt d
+load net {regs.regs(0).sva(20)} -attr vt d
+load net {regs.regs(0).sva(21)} -attr vt d
+load net {regs.regs(0).sva(22)} -attr vt d
+load net {regs.regs(0).sva(23)} -attr vt d
+load net {regs.regs(0).sva(24)} -attr vt d
+load net {regs.regs(0).sva(25)} -attr vt d
+load net {regs.regs(0).sva(26)} -attr vt d
+load net {regs.regs(0).sva(27)} -attr vt d
+load net {regs.regs(0).sva(28)} -attr vt d
+load net {regs.regs(0).sva(29)} -attr vt d
+load net {regs.regs(0).sva(30)} -attr vt d
+load net {regs.regs(0).sva(31)} -attr vt d
+load net {regs.regs(0).sva(32)} -attr vt d
+load net {regs.regs(0).sva(33)} -attr vt d
+load net {regs.regs(0).sva(34)} -attr vt d
+load net {regs.regs(0).sva(35)} -attr vt d
+load net {regs.regs(0).sva(36)} -attr vt d
+load net {regs.regs(0).sva(37)} -attr vt d
+load net {regs.regs(0).sva(38)} -attr vt d
+load net {regs.regs(0).sva(39)} -attr vt d
+load net {regs.regs(0).sva(40)} -attr vt d
+load net {regs.regs(0).sva(41)} -attr vt d
+load net {regs.regs(0).sva(42)} -attr vt d
+load net {regs.regs(0).sva(43)} -attr vt d
+load net {regs.regs(0).sva(44)} -attr vt d
+load net {regs.regs(0).sva(45)} -attr vt d
+load net {regs.regs(0).sva(46)} -attr vt d
+load net {regs.regs(0).sva(47)} -attr vt d
+load net {regs.regs(0).sva(48)} -attr vt d
+load net {regs.regs(0).sva(49)} -attr vt d
+load net {regs.regs(0).sva(50)} -attr vt d
+load net {regs.regs(0).sva(51)} -attr vt d
+load net {regs.regs(0).sva(52)} -attr vt d
+load net {regs.regs(0).sva(53)} -attr vt d
+load net {regs.regs(0).sva(54)} -attr vt d
+load net {regs.regs(0).sva(55)} -attr vt d
+load net {regs.regs(0).sva(56)} -attr vt d
+load net {regs.regs(0).sva(57)} -attr vt d
+load net {regs.regs(0).sva(58)} -attr vt d
+load net {regs.regs(0).sva(59)} -attr vt d
+load net {regs.regs(0).sva(60)} -attr vt d
+load net {regs.regs(0).sva(61)} -attr vt d
+load net {regs.regs(0).sva(62)} -attr vt d
+load net {regs.regs(0).sva(63)} -attr vt d
+load net {regs.regs(0).sva(64)} -attr vt d
+load net {regs.regs(0).sva(65)} -attr vt d
+load net {regs.regs(0).sva(66)} -attr vt d
+load net {regs.regs(0).sva(67)} -attr vt d
+load net {regs.regs(0).sva(68)} -attr vt d
+load net {regs.regs(0).sva(69)} -attr vt d
+load net {regs.regs(0).sva(70)} -attr vt d
+load net {regs.regs(0).sva(71)} -attr vt d
+load net {regs.regs(0).sva(72)} -attr vt d
+load net {regs.regs(0).sva(73)} -attr vt d
+load net {regs.regs(0).sva(74)} -attr vt d
+load net {regs.regs(0).sva(75)} -attr vt d
+load net {regs.regs(0).sva(76)} -attr vt d
+load net {regs.regs(0).sva(77)} -attr vt d
+load net {regs.regs(0).sva(78)} -attr vt d
+load net {regs.regs(0).sva(79)} -attr vt d
+load net {regs.regs(0).sva(80)} -attr vt d
+load net {regs.regs(0).sva(81)} -attr vt d
+load net {regs.regs(0).sva(82)} -attr vt d
+load net {regs.regs(0).sva(83)} -attr vt d
+load net {regs.regs(0).sva(84)} -attr vt d
+load net {regs.regs(0).sva(85)} -attr vt d
+load net {regs.regs(0).sva(86)} -attr vt d
+load net {regs.regs(0).sva(87)} -attr vt d
+load net {regs.regs(0).sva(88)} -attr vt d
+load net {regs.regs(0).sva(89)} -attr vt d
+load netBundle {regs.regs(0).sva} 90 {regs.regs(0).sva(0)} {regs.regs(0).sva(1)} {regs.regs(0).sva(2)} {regs.regs(0).sva(3)} {regs.regs(0).sva(4)} {regs.regs(0).sva(5)} {regs.regs(0).sva(6)} {regs.regs(0).sva(7)} {regs.regs(0).sva(8)} {regs.regs(0).sva(9)} {regs.regs(0).sva(10)} {regs.regs(0).sva(11)} {regs.regs(0).sva(12)} {regs.regs(0).sva(13)} {regs.regs(0).sva(14)} {regs.regs(0).sva(15)} {regs.regs(0).sva(16)} {regs.regs(0).sva(17)} {regs.regs(0).sva(18)} {regs.regs(0).sva(19)} {regs.regs(0).sva(20)} {regs.regs(0).sva(21)} {regs.regs(0).sva(22)} {regs.regs(0).sva(23)} {regs.regs(0).sva(24)} {regs.regs(0).sva(25)} {regs.regs(0).sva(26)} {regs.regs(0).sva(27)} {regs.regs(0).sva(28)} {regs.regs(0).sva(29)} {regs.regs(0).sva(30)} {regs.regs(0).sva(31)} {regs.regs(0).sva(32)} {regs.regs(0).sva(33)} {regs.regs(0).sva(34)} {regs.regs(0).sva(35)} {regs.regs(0).sva(36)} {regs.regs(0).sva(37)} {regs.regs(0).sva(38)} {regs.regs(0).sva(39)} {regs.regs(0).sva(40)} {regs.regs(0).sva(41)} {regs.regs(0).sva(42)} {regs.regs(0).sva(43)} {regs.regs(0).sva(44)} {regs.regs(0).sva(45)} {regs.regs(0).sva(46)} {regs.regs(0).sva(47)} {regs.regs(0).sva(48)} {regs.regs(0).sva(49)} {regs.regs(0).sva(50)} {regs.regs(0).sva(51)} {regs.regs(0).sva(52)} {regs.regs(0).sva(53)} {regs.regs(0).sva(54)} {regs.regs(0).sva(55)} {regs.regs(0).sva(56)} {regs.regs(0).sva(57)} {regs.regs(0).sva(58)} {regs.regs(0).sva(59)} {regs.regs(0).sva(60)} {regs.regs(0).sva(61)} {regs.regs(0).sva(62)} {regs.regs(0).sva(63)} {regs.regs(0).sva(64)} {regs.regs(0).sva(65)} {regs.regs(0).sva(66)} {regs.regs(0).sva(67)} {regs.regs(0).sva(68)} {regs.regs(0).sva(69)} {regs.regs(0).sva(70)} {regs.regs(0).sva(71)} {regs.regs(0).sva(72)} {regs.regs(0).sva(73)} {regs.regs(0).sva(74)} {regs.regs(0).sva(75)} {regs.regs(0).sva(76)} {regs.regs(0).sva(77)} {regs.regs(0).sva(78)} {regs.regs(0).sva(79)} {regs.regs(0).sva(80)} {regs.regs(0).sva(81)} {regs.regs(0).sva(82)} {regs.regs(0).sva(83)} {regs.regs(0).sva(84)} {regs.regs(0).sva(85)} {regs.regs(0).sva(86)} {regs.regs(0).sva(87)} {regs.regs(0).sva(88)} {regs.regs(0).sva(89)} -attr xrf 32844 -attr oid 8 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {acc.imod#7.lpi#1.dfm(0)} -attr vt d
+load net {acc.imod#7.lpi#1.dfm(1)} -attr vt d
+load netBundle {acc.imod#7.lpi#1.dfm} 2 {acc.imod#7.lpi#1.dfm(0)} {acc.imod#7.lpi#1.dfm(1)} -attr xrf 32845 -attr oid 9 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(0)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(1)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(2)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(3)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(4)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(5)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(6)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(7)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(8)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(9)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(10)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm(11)} -attr vt d
+load netBundle {ACC1:acc#125.psp.lpi#1.dfm} 12 {ACC1:acc#125.psp.lpi#1.dfm(0)} {ACC1:acc#125.psp.lpi#1.dfm(1)} {ACC1:acc#125.psp.lpi#1.dfm(2)} {ACC1:acc#125.psp.lpi#1.dfm(3)} {ACC1:acc#125.psp.lpi#1.dfm(4)} {ACC1:acc#125.psp.lpi#1.dfm(5)} {ACC1:acc#125.psp.lpi#1.dfm(6)} {ACC1:acc#125.psp.lpi#1.dfm(7)} {ACC1:acc#125.psp.lpi#1.dfm(8)} {ACC1:acc#125.psp.lpi#1.dfm(9)} {ACC1:acc#125.psp.lpi#1.dfm(10)} {ACC1:acc#125.psp.lpi#1.dfm(11)} -attr xrf 32846 -attr oid 10 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {acc.imod#20.lpi#1.dfm(0)} -attr vt d
+load net {acc.imod#20.lpi#1.dfm(1)} -attr vt d
+load netBundle {acc.imod#20.lpi#1.dfm} 2 {acc.imod#20.lpi#1.dfm(0)} {acc.imod#20.lpi#1.dfm(1)} -attr xrf 32847 -attr oid 11 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(0)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(1)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(2)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(3)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(4)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(5)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(6)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(7)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(8)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(9)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(10)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(11)} -attr vt d
+load netBundle {ACC1:acc#125.psp#1.lpi#1.dfm} 12 {ACC1:acc#125.psp#1.lpi#1.dfm(0)} {ACC1:acc#125.psp#1.lpi#1.dfm(1)} {ACC1:acc#125.psp#1.lpi#1.dfm(2)} {ACC1:acc#125.psp#1.lpi#1.dfm(3)} {ACC1:acc#125.psp#1.lpi#1.dfm(4)} {ACC1:acc#125.psp#1.lpi#1.dfm(5)} {ACC1:acc#125.psp#1.lpi#1.dfm(6)} {ACC1:acc#125.psp#1.lpi#1.dfm(7)} {ACC1:acc#125.psp#1.lpi#1.dfm(8)} {ACC1:acc#125.psp#1.lpi#1.dfm(9)} {ACC1:acc#125.psp#1.lpi#1.dfm(10)} {ACC1:acc#125.psp#1.lpi#1.dfm(11)} -attr xrf 32848 -attr oid 12 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {in(0).sva#1(0)} -attr vt d
+load net {in(0).sva#1(1)} -attr vt d
+load net {in(0).sva#1(2)} -attr vt d
+load net {in(0).sva#1(3)} -attr vt d
+load net {in(0).sva#1(4)} -attr vt d
+load net {in(0).sva#1(5)} -attr vt d
+load net {in(0).sva#1(6)} -attr vt d
+load net {in(0).sva#1(7)} -attr vt d
+load net {in(0).sva#1(8)} -attr vt d
+load net {in(0).sva#1(9)} -attr vt d
+load net {in(0).sva#1(10)} -attr vt d
+load net {in(0).sva#1(11)} -attr vt d
+load net {in(0).sva#1(12)} -attr vt d
+load net {in(0).sva#1(13)} -attr vt d
+load net {in(0).sva#1(14)} -attr vt d
+load net {in(0).sva#1(15)} -attr vt d
+load netBundle {in(0).sva#1} 16 {in(0).sva#1(0)} {in(0).sva#1(1)} {in(0).sva#1(2)} {in(0).sva#1(3)} {in(0).sva#1(4)} {in(0).sva#1(5)} {in(0).sva#1(6)} {in(0).sva#1(7)} {in(0).sva#1(8)} {in(0).sva#1(9)} {in(0).sva#1(10)} {in(0).sva#1(11)} {in(0).sva#1(12)} {in(0).sva#1(13)} {in(0).sva#1(14)} {in(0).sva#1(15)} -attr xrf 32849 -attr oid 13 -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(2).sva#1(0)} -attr vt d
+load net {in(2).sva#1(1)} -attr vt d
+load net {in(2).sva#1(2)} -attr vt d
+load net {in(2).sva#1(3)} -attr vt d
+load net {in(2).sva#1(4)} -attr vt d
+load net {in(2).sva#1(5)} -attr vt d
+load net {in(2).sva#1(6)} -attr vt d
+load net {in(2).sva#1(7)} -attr vt d
+load net {in(2).sva#1(8)} -attr vt d
+load net {in(2).sva#1(9)} -attr vt d
+load net {in(2).sva#1(10)} -attr vt d
+load net {in(2).sva#1(11)} -attr vt d
+load net {in(2).sva#1(12)} -attr vt d
+load net {in(2).sva#1(13)} -attr vt d
+load net {in(2).sva#1(14)} -attr vt d
+load net {in(2).sva#1(15)} -attr vt d
+load netBundle {in(2).sva#1} 16 {in(2).sva#1(0)} {in(2).sva#1(1)} {in(2).sva#1(2)} {in(2).sva#1(3)} {in(2).sva#1(4)} {in(2).sva#1(5)} {in(2).sva#1(6)} {in(2).sva#1(7)} {in(2).sva#1(8)} {in(2).sva#1(9)} {in(2).sva#1(10)} {in(2).sva#1(11)} {in(2).sva#1(12)} {in(2).sva#1(13)} {in(2).sva#1(14)} {in(2).sva#1(15)} -attr xrf 32850 -attr oid 14 -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {i#6.sva#1(0)} -attr vt d
+load net {i#6.sva#1(1)} -attr vt d
+load netBundle {i#6.sva#1} 2 {i#6.sva#1(0)} {i#6.sva#1(1)} -attr xrf 32851 -attr oid 15 -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {FRAME:for:acc#24.itm#1(0)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(1)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(2)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(3)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(4)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(5)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(6)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(7)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(8)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(9)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(10)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(11)} -attr vt d
+load net {FRAME:for:acc#24.itm#1(12)} -attr vt d
+load netBundle {FRAME:for:acc#24.itm#1} 13 {FRAME:for:acc#24.itm#1(0)} {FRAME:for:acc#24.itm#1(1)} {FRAME:for:acc#24.itm#1(2)} {FRAME:for:acc#24.itm#1(3)} {FRAME:for:acc#24.itm#1(4)} {FRAME:for:acc#24.itm#1(5)} {FRAME:for:acc#24.itm#1(6)} {FRAME:for:acc#24.itm#1(7)} {FRAME:for:acc#24.itm#1(8)} {FRAME:for:acc#24.itm#1(9)} {FRAME:for:acc#24.itm#1(10)} {FRAME:for:acc#24.itm#1(11)} {FRAME:for:acc#24.itm#1(12)} -attr xrf 32852 -attr oid 16 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(0)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(1)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(2)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(3)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(4)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(5)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(6)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(7)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(8)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(9)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(10)} -attr vt d
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -attr vt d
+load netBundle {FRAME:for:slc(in(0).sva).itm#1} 12 {FRAME:for:slc(in(0).sva).itm#1(0)} {FRAME:for:slc(in(0).sva).itm#1(1)} {FRAME:for:slc(in(0).sva).itm#1(2)} {FRAME:for:slc(in(0).sva).itm#1(3)} {FRAME:for:slc(in(0).sva).itm#1(4)} {FRAME:for:slc(in(0).sva).itm#1(5)} {FRAME:for:slc(in(0).sva).itm#1(6)} {FRAME:for:slc(in(0).sva).itm#1(7)} {FRAME:for:slc(in(0).sva).itm#1(8)} {FRAME:for:slc(in(0).sva).itm#1(9)} {FRAME:for:slc(in(0).sva).itm#1(10)} {FRAME:for:slc(in(0).sva).itm#1(11)} -attr xrf 32853 -attr oid 17 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:acc#26.itm#1(0)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(1)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(2)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(3)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(4)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(5)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(6)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(7)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(8)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(9)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(10)} -attr vt d
+load net {FRAME:for:acc#26.itm#1(11)} -attr vt d
+load netBundle {FRAME:for:acc#26.itm#1} 12 {FRAME:for:acc#26.itm#1(0)} {FRAME:for:acc#26.itm#1(1)} {FRAME:for:acc#26.itm#1(2)} {FRAME:for:acc#26.itm#1(3)} {FRAME:for:acc#26.itm#1(4)} {FRAME:for:acc#26.itm#1(5)} {FRAME:for:acc#26.itm#1(6)} {FRAME:for:acc#26.itm#1(7)} {FRAME:for:acc#26.itm#1(8)} {FRAME:for:acc#26.itm#1(9)} {FRAME:for:acc#26.itm#1(10)} {FRAME:for:acc#26.itm#1(11)} -attr xrf 32854 -attr oid 18 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(0)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(1)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(2)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(3)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(4)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(5)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(6)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(7)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(8)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(9)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(10)} -attr vt d
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -attr vt d
+load netBundle {FRAME:for:slc(in(2).sva).itm#1} 12 {FRAME:for:slc(in(2).sva).itm#1(0)} {FRAME:for:slc(in(2).sva).itm#1(1)} {FRAME:for:slc(in(2).sva).itm#1(2)} {FRAME:for:slc(in(2).sva).itm#1(3)} {FRAME:for:slc(in(2).sva).itm#1(4)} {FRAME:for:slc(in(2).sva).itm#1(5)} {FRAME:for:slc(in(2).sva).itm#1(6)} {FRAME:for:slc(in(2).sva).itm#1(7)} {FRAME:for:slc(in(2).sva).itm#1(8)} {FRAME:for:slc(in(2).sva).itm#1(9)} {FRAME:for:slc(in(2).sva).itm#1(10)} {FRAME:for:slc(in(2).sva).itm#1(11)} -attr xrf 32855 -attr oid 19 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {ACC1:acc#341.itm#1(0)} -attr vt d
+load net {ACC1:acc#341.itm#1(1)} -attr vt d
+load net {ACC1:acc#341.itm#1(2)} -attr vt d
+load net {ACC1:acc#341.itm#1(3)} -attr vt d
+load net {ACC1:acc#341.itm#1(4)} -attr vt d
+load net {ACC1:acc#341.itm#1(5)} -attr vt d
+load net {ACC1:acc#341.itm#1(6)} -attr vt d
+load net {ACC1:acc#341.itm#1(7)} -attr vt d
+load net {ACC1:acc#341.itm#1(8)} -attr vt d
+load net {ACC1:acc#341.itm#1(9)} -attr vt d
+load net {ACC1:acc#341.itm#1(10)} -attr vt d
+load net {ACC1:acc#341.itm#1(11)} -attr vt d
+load net {ACC1:acc#341.itm#1(12)} -attr vt d
+load netBundle {ACC1:acc#341.itm#1} 13 {ACC1:acc#341.itm#1(0)} {ACC1:acc#341.itm#1(1)} {ACC1:acc#341.itm#1(2)} {ACC1:acc#341.itm#1(3)} {ACC1:acc#341.itm#1(4)} {ACC1:acc#341.itm#1(5)} {ACC1:acc#341.itm#1(6)} {ACC1:acc#341.itm#1(7)} {ACC1:acc#341.itm#1(8)} {ACC1:acc#341.itm#1(9)} {ACC1:acc#341.itm#1(10)} {ACC1:acc#341.itm#1(11)} {ACC1:acc#341.itm#1(12)} -attr xrf 32856 -attr oid 20 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {acc.imod#6.lpi#1.dfm.sg1(0)} -attr vt d
+load net {acc.imod#6.lpi#1.dfm.sg1(1)} -attr vt d
+load netBundle {acc.imod#6.lpi#1.dfm.sg1} 2 {acc.imod#6.lpi#1.dfm.sg1(0)} {acc.imod#6.lpi#1.dfm.sg1(1)} -attr xrf 32857 -attr oid 21 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1}
+load net {regs.regs(2).lpi#1.dfm.sg2(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2(29)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm.sg2} 30 {regs.regs(2).lpi#1.dfm.sg2(0)} {regs.regs(2).lpi#1.dfm.sg2(1)} {regs.regs(2).lpi#1.dfm.sg2(2)} {regs.regs(2).lpi#1.dfm.sg2(3)} {regs.regs(2).lpi#1.dfm.sg2(4)} {regs.regs(2).lpi#1.dfm.sg2(5)} {regs.regs(2).lpi#1.dfm.sg2(6)} {regs.regs(2).lpi#1.dfm.sg2(7)} {regs.regs(2).lpi#1.dfm.sg2(8)} {regs.regs(2).lpi#1.dfm.sg2(9)} {regs.regs(2).lpi#1.dfm.sg2(10)} {regs.regs(2).lpi#1.dfm.sg2(11)} {regs.regs(2).lpi#1.dfm.sg2(12)} {regs.regs(2).lpi#1.dfm.sg2(13)} {regs.regs(2).lpi#1.dfm.sg2(14)} {regs.regs(2).lpi#1.dfm.sg2(15)} {regs.regs(2).lpi#1.dfm.sg2(16)} {regs.regs(2).lpi#1.dfm.sg2(17)} {regs.regs(2).lpi#1.dfm.sg2(18)} {regs.regs(2).lpi#1.dfm.sg2(19)} {regs.regs(2).lpi#1.dfm.sg2(20)} {regs.regs(2).lpi#1.dfm.sg2(21)} {regs.regs(2).lpi#1.dfm.sg2(22)} {regs.regs(2).lpi#1.dfm.sg2(23)} {regs.regs(2).lpi#1.dfm.sg2(24)} {regs.regs(2).lpi#1.dfm.sg2(25)} {regs.regs(2).lpi#1.dfm.sg2(26)} {regs.regs(2).lpi#1.dfm.sg2(27)} {regs.regs(2).lpi#1.dfm.sg2(28)} {regs.regs(2).lpi#1.dfm.sg2(29)} -attr xrf 32858 -attr oid 22 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm#1(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1(29)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm#1} 30 {regs.regs(2).lpi#1.dfm#1(0)} {regs.regs(2).lpi#1.dfm#1(1)} {regs.regs(2).lpi#1.dfm#1(2)} {regs.regs(2).lpi#1.dfm#1(3)} {regs.regs(2).lpi#1.dfm#1(4)} {regs.regs(2).lpi#1.dfm#1(5)} {regs.regs(2).lpi#1.dfm#1(6)} {regs.regs(2).lpi#1.dfm#1(7)} {regs.regs(2).lpi#1.dfm#1(8)} {regs.regs(2).lpi#1.dfm#1(9)} {regs.regs(2).lpi#1.dfm#1(10)} {regs.regs(2).lpi#1.dfm#1(11)} {regs.regs(2).lpi#1.dfm#1(12)} {regs.regs(2).lpi#1.dfm#1(13)} {regs.regs(2).lpi#1.dfm#1(14)} {regs.regs(2).lpi#1.dfm#1(15)} {regs.regs(2).lpi#1.dfm#1(16)} {regs.regs(2).lpi#1.dfm#1(17)} {regs.regs(2).lpi#1.dfm#1(18)} {regs.regs(2).lpi#1.dfm#1(19)} {regs.regs(2).lpi#1.dfm#1(20)} {regs.regs(2).lpi#1.dfm#1(21)} {regs.regs(2).lpi#1.dfm#1(22)} {regs.regs(2).lpi#1.dfm#1(23)} {regs.regs(2).lpi#1.dfm#1(24)} {regs.regs(2).lpi#1.dfm#1(25)} {regs.regs(2).lpi#1.dfm#1(26)} {regs.regs(2).lpi#1.dfm#1(27)} {regs.regs(2).lpi#1.dfm#1(28)} {regs.regs(2).lpi#1.dfm#1(29)} -attr xrf 32859 -attr oid 23 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1(0)} -attr vt d
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1(1)} -attr vt d
+load netBundle {ACC1:acc#118.psp.lpi#1.dfm.sg1} 2 {ACC1:acc#118.psp.lpi#1.dfm.sg1(0)} {ACC1:acc#118.psp.lpi#1.dfm.sg1(1)} -attr xrf 32860 -attr oid 24 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(0)} -attr vt d
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(1)} -attr vt d
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(2)} -attr vt d
+load netBundle {ACC1:acc#110.psp#1.lpi#1.dfm.sg1} 3 {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(0)} {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(1)} {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(2)} -attr xrf 32861 -attr oid 25 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load net {acc.imod#18.lpi#1.dfm.sg1(0)} -attr vt d
+load net {acc.imod#18.lpi#1.dfm.sg1(1)} -attr vt d
+load netBundle {acc.imod#18.lpi#1.dfm.sg1} 2 {acc.imod#18.lpi#1.dfm.sg1(0)} {acc.imod#18.lpi#1.dfm.sg1(1)} -attr xrf 32862 -attr oid 26 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(0)} -attr vt d
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(1)} -attr vt d
+load netBundle {ACC1:acc#118.psp#1.lpi#1.dfm.sg1} 2 {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(0)} {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(1)} -attr xrf 32863 -attr oid 27 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(0)} -attr vt d
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(1)} -attr vt d
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(2)} -attr vt d
+load netBundle {ACC1:acc#110.psp#2.lpi#1.dfm.sg1} 3 {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(0)} {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(1)} {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(2)} -attr xrf 32864 -attr oid 28 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load net {FRAME:p#1.sva#1(0)} -attr vt d
+load net {FRAME:p#1.sva#1(1)} -attr vt d
+load net {FRAME:p#1.sva#1(2)} -attr vt d
+load net {FRAME:p#1.sva#1(3)} -attr vt d
+load net {FRAME:p#1.sva#1(4)} -attr vt d
+load net {FRAME:p#1.sva#1(5)} -attr vt d
+load net {FRAME:p#1.sva#1(6)} -attr vt d
+load net {FRAME:p#1.sva#1(7)} -attr vt d
+load net {FRAME:p#1.sva#1(8)} -attr vt d
+load net {FRAME:p#1.sva#1(9)} -attr vt d
+load net {FRAME:p#1.sva#1(10)} -attr vt d
+load net {FRAME:p#1.sva#1(11)} -attr vt d
+load net {FRAME:p#1.sva#1(12)} -attr vt d
+load net {FRAME:p#1.sva#1(13)} -attr vt d
+load net {FRAME:p#1.sva#1(14)} -attr vt d
+load net {FRAME:p#1.sva#1(15)} -attr vt d
+load net {FRAME:p#1.sva#1(16)} -attr vt d
+load net {FRAME:p#1.sva#1(17)} -attr vt d
+load net {FRAME:p#1.sva#1(18)} -attr vt d
+load netBundle {FRAME:p#1.sva#1} 19 {FRAME:p#1.sva#1(0)} {FRAME:p#1.sva#1(1)} {FRAME:p#1.sva#1(2)} {FRAME:p#1.sva#1(3)} {FRAME:p#1.sva#1(4)} {FRAME:p#1.sva#1(5)} {FRAME:p#1.sva#1(6)} {FRAME:p#1.sva#1(7)} {FRAME:p#1.sva#1(8)} {FRAME:p#1.sva#1(9)} {FRAME:p#1.sva#1(10)} {FRAME:p#1.sva#1(11)} {FRAME:p#1.sva#1(12)} {FRAME:p#1.sva#1(13)} {FRAME:p#1.sva#1(14)} {FRAME:p#1.sva#1(15)} {FRAME:p#1.sva#1(16)} {FRAME:p#1.sva#1(17)} {FRAME:p#1.sva#1(18)} -attr xrf 32865 -attr oid 29 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:acc#2.psp.sva(0)} -attr vt d
+load net {FRAME:acc#2.psp.sva(1)} -attr vt d
+load net {FRAME:acc#2.psp.sva(2)} -attr vt d
+load net {FRAME:acc#2.psp.sva(3)} -attr vt d
+load net {FRAME:acc#2.psp.sva(4)} -attr vt d
+load net {FRAME:acc#2.psp.sva(5)} -attr vt d
+load net {FRAME:acc#2.psp.sva(6)} -attr vt d
+load net {FRAME:acc#2.psp.sva(7)} -attr vt d
+load net {FRAME:acc#2.psp.sva(8)} -attr vt d
+load net {FRAME:acc#2.psp.sva(9)} -attr vt d
+load net {FRAME:acc#2.psp.sva(10)} -attr vt d
+load net {FRAME:acc#2.psp.sva(11)} -attr vt d
+load netBundle {FRAME:acc#2.psp.sva} 12 {FRAME:acc#2.psp.sva(0)} {FRAME:acc#2.psp.sva(1)} {FRAME:acc#2.psp.sva(2)} {FRAME:acc#2.psp.sva(3)} {FRAME:acc#2.psp.sva(4)} {FRAME:acc#2.psp.sva(5)} {FRAME:acc#2.psp.sva(6)} {FRAME:acc#2.psp.sva(7)} {FRAME:acc#2.psp.sva(8)} {FRAME:acc#2.psp.sva(9)} {FRAME:acc#2.psp.sva(10)} {FRAME:acc#2.psp.sva(11)} -attr xrf 32866 -attr oid 30 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {intensity#2.sg1.sva(0)} -attr vt d
+load net {intensity#2.sg1.sva(1)} -attr vt d
+load net {intensity#2.sg1.sva(2)} -attr vt d
+load net {intensity#2.sg1.sva(3)} -attr vt d
+load net {intensity#2.sg1.sva(4)} -attr vt d
+load net {intensity#2.sg1.sva(5)} -attr vt d
+load net {intensity#2.sg1.sva(6)} -attr vt d
+load net {intensity#2.sg1.sva(7)} -attr vt d
+load net {intensity#2.sg1.sva(8)} -attr vt d
+load net {intensity#2.sg1.sva(9)} -attr vt d
+load net {intensity#2.sg1.sva(10)} -attr vt d
+load net {intensity#2.sg1.sva(11)} -attr vt d
+load net {intensity#2.sg1.sva(12)} -attr vt d
+load net {intensity#2.sg1.sva(13)} -attr vt d
+load net {intensity#2.sg1.sva(14)} -attr vt d
+load netBundle {intensity#2.sg1.sva} 15 {intensity#2.sg1.sva(0)} {intensity#2.sg1.sva(1)} {intensity#2.sg1.sva(2)} {intensity#2.sg1.sva(3)} {intensity#2.sg1.sva(4)} {intensity#2.sg1.sva(5)} {intensity#2.sg1.sva(6)} {intensity#2.sg1.sva(7)} {intensity#2.sg1.sva(8)} {intensity#2.sg1.sva(9)} {intensity#2.sg1.sva(10)} {intensity#2.sg1.sva(11)} {intensity#2.sg1.sva(12)} {intensity#2.sg1.sva(13)} {intensity#2.sg1.sva(14)} -attr xrf 32867 -attr oid 31 -attr vt d -attr @path {/sobel/sobel:core/intensity#2.sg1.sva}
+load net {acc.imod#12.sva(0)} -attr vt d
+load net {acc.imod#12.sva(1)} -attr vt d
+load net {acc.imod#12.sva(2)} -attr vt d
+load net {acc.imod#12.sva(3)} -attr vt d
+load net {acc.imod#12.sva(4)} -attr vt d
+load net {acc.imod#12.sva(5)} -attr vt d
+load netBundle {acc.imod#12.sva} 6 {acc.imod#12.sva(0)} {acc.imod#12.sva(1)} {acc.imod#12.sva(2)} {acc.imod#12.sva(3)} {acc.imod#12.sva(4)} {acc.imod#12.sva(5)} -attr xrf 32868 -attr oid 32 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load net {in(2).sva#3(0)} -attr vt d
+load net {in(2).sva#3(1)} -attr vt d
+load net {in(2).sva#3(2)} -attr vt d
+load net {in(2).sva#3(3)} -attr vt d
+load net {in(2).sva#3(4)} -attr vt d
+load net {in(2).sva#3(5)} -attr vt d
+load net {in(2).sva#3(6)} -attr vt d
+load net {in(2).sva#3(7)} -attr vt d
+load net {in(2).sva#3(8)} -attr vt d
+load net {in(2).sva#3(9)} -attr vt d
+load net {in(2).sva#3(10)} -attr vt d
+load net {in(2).sva#3(11)} -attr vt d
+load net {in(2).sva#3(12)} -attr vt d
+load net {in(2).sva#3(13)} -attr vt d
+load net {in(2).sva#3(14)} -attr vt d
+load net {in(2).sva#3(15)} -attr vt d
+load netBundle {in(2).sva#3} 16 {in(2).sva#3(0)} {in(2).sva#3(1)} {in(2).sva#3(2)} {in(2).sva#3(3)} {in(2).sva#3(4)} {in(2).sva#3(5)} {in(2).sva#3(6)} {in(2).sva#3(7)} {in(2).sva#3(8)} {in(2).sva#3(9)} {in(2).sva#3(10)} {in(2).sva#3(11)} {in(2).sva#3(12)} {in(2).sva#3(13)} {in(2).sva#3(14)} {in(2).sva#3(15)} -attr xrf 32869 -attr oid 33 -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(0).sva#3(0)} -attr vt d
+load net {in(0).sva#3(1)} -attr vt d
+load net {in(0).sva#3(2)} -attr vt d
+load net {in(0).sva#3(3)} -attr vt d
+load net {in(0).sva#3(4)} -attr vt d
+load net {in(0).sva#3(5)} -attr vt d
+load net {in(0).sva#3(6)} -attr vt d
+load net {in(0).sva#3(7)} -attr vt d
+load net {in(0).sva#3(8)} -attr vt d
+load net {in(0).sva#3(9)} -attr vt d
+load net {in(0).sva#3(10)} -attr vt d
+load net {in(0).sva#3(11)} -attr vt d
+load net {in(0).sva#3(12)} -attr vt d
+load net {in(0).sva#3(13)} -attr vt d
+load net {in(0).sva#3(14)} -attr vt d
+load net {in(0).sva#3(15)} -attr vt d
+load netBundle {in(0).sva#3} 16 {in(0).sva#3(0)} {in(0).sva#3(1)} {in(0).sva#3(2)} {in(0).sva#3(3)} {in(0).sva#3(4)} {in(0).sva#3(5)} {in(0).sva#3(6)} {in(0).sva#3(7)} {in(0).sva#3(8)} {in(0).sva#3(9)} {in(0).sva#3(10)} {in(0).sva#3(11)} {in(0).sva#3(12)} {in(0).sva#3(13)} {in(0).sva#3(14)} {in(0).sva#3(15)} -attr xrf 32870 -attr oid 34 -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {i#6.sva#2(0)} -attr vt d
+load net {i#6.sva#2(1)} -attr vt d
+load netBundle {i#6.sva#2} 2 {i#6.sva#2(0)} {i#6.sva#2(1)} -attr xrf 32871 -attr oid 35 -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.lpi#1.dfm(0)} -attr vt d
+load net {i#6.lpi#1.dfm(1)} -attr vt d
+load netBundle {i#6.lpi#1.dfm} 2 {i#6.lpi#1.dfm(0)} {i#6.lpi#1.dfm(1)} -attr xrf 32872 -attr oid 36 -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(0)} -attr vt d
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(1)} -attr vt d
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(2)} -attr vt d
+load netBundle {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0} 3 {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(0)} {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(1)} {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(2)} -attr xrf 32873 -attr oid 37 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(0)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(1)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(2)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(3)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(5)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(7)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(9)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} -attr vt d
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -attr vt d
+load netBundle {ACC1:acc#125.psp.lpi#1.dfm:mx0} 12 {ACC1:acc#125.psp.lpi#1.dfm:mx0(0)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(1)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(2)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(3)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(5)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(7)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(9)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -attr xrf 32874 -attr oid 38 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(0)} -attr vt d
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(1)} -attr vt d
+load netBundle {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0} 2 {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(0)} {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(1)} -attr xrf 32875 -attr oid 39 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(29)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm.sg2:mx0} 30 {regs.regs(2).lpi#1.dfm.sg2:mx0(0)} {regs.regs(2).lpi#1.dfm.sg2:mx0(1)} {regs.regs(2).lpi#1.dfm.sg2:mx0(2)} {regs.regs(2).lpi#1.dfm.sg2:mx0(3)} {regs.regs(2).lpi#1.dfm.sg2:mx0(4)} {regs.regs(2).lpi#1.dfm.sg2:mx0(5)} {regs.regs(2).lpi#1.dfm.sg2:mx0(6)} {regs.regs(2).lpi#1.dfm.sg2:mx0(7)} {regs.regs(2).lpi#1.dfm.sg2:mx0(8)} {regs.regs(2).lpi#1.dfm.sg2:mx0(9)} {regs.regs(2).lpi#1.dfm.sg2:mx0(10)} {regs.regs(2).lpi#1.dfm.sg2:mx0(11)} {regs.regs(2).lpi#1.dfm.sg2:mx0(12)} {regs.regs(2).lpi#1.dfm.sg2:mx0(13)} {regs.regs(2).lpi#1.dfm.sg2:mx0(14)} {regs.regs(2).lpi#1.dfm.sg2:mx0(15)} {regs.regs(2).lpi#1.dfm.sg2:mx0(16)} {regs.regs(2).lpi#1.dfm.sg2:mx0(17)} {regs.regs(2).lpi#1.dfm.sg2:mx0(18)} {regs.regs(2).lpi#1.dfm.sg2:mx0(19)} {regs.regs(2).lpi#1.dfm.sg2:mx0(20)} {regs.regs(2).lpi#1.dfm.sg2:mx0(21)} {regs.regs(2).lpi#1.dfm.sg2:mx0(22)} {regs.regs(2).lpi#1.dfm.sg2:mx0(23)} {regs.regs(2).lpi#1.dfm.sg2:mx0(24)} {regs.regs(2).lpi#1.dfm.sg2:mx0(25)} {regs.regs(2).lpi#1.dfm.sg2:mx0(26)} {regs.regs(2).lpi#1.dfm.sg2:mx0(27)} {regs.regs(2).lpi#1.dfm.sg2:mx0(28)} {regs.regs(2).lpi#1.dfm.sg2:mx0(29)} -attr xrf 32876 -attr oid 40 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm#1:mx0(29)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm#1:mx0} 30 {regs.regs(2).lpi#1.dfm#1:mx0(0)} {regs.regs(2).lpi#1.dfm#1:mx0(1)} {regs.regs(2).lpi#1.dfm#1:mx0(2)} {regs.regs(2).lpi#1.dfm#1:mx0(3)} {regs.regs(2).lpi#1.dfm#1:mx0(4)} {regs.regs(2).lpi#1.dfm#1:mx0(5)} {regs.regs(2).lpi#1.dfm#1:mx0(6)} {regs.regs(2).lpi#1.dfm#1:mx0(7)} {regs.regs(2).lpi#1.dfm#1:mx0(8)} {regs.regs(2).lpi#1.dfm#1:mx0(9)} {regs.regs(2).lpi#1.dfm#1:mx0(10)} {regs.regs(2).lpi#1.dfm#1:mx0(11)} {regs.regs(2).lpi#1.dfm#1:mx0(12)} {regs.regs(2).lpi#1.dfm#1:mx0(13)} {regs.regs(2).lpi#1.dfm#1:mx0(14)} {regs.regs(2).lpi#1.dfm#1:mx0(15)} {regs.regs(2).lpi#1.dfm#1:mx0(16)} {regs.regs(2).lpi#1.dfm#1:mx0(17)} {regs.regs(2).lpi#1.dfm#1:mx0(18)} {regs.regs(2).lpi#1.dfm#1:mx0(19)} {regs.regs(2).lpi#1.dfm#1:mx0(20)} {regs.regs(2).lpi#1.dfm#1:mx0(21)} {regs.regs(2).lpi#1.dfm#1:mx0(22)} {regs.regs(2).lpi#1.dfm#1:mx0(23)} {regs.regs(2).lpi#1.dfm#1:mx0(24)} {regs.regs(2).lpi#1.dfm#1:mx0(25)} {regs.regs(2).lpi#1.dfm#1:mx0(26)} {regs.regs(2).lpi#1.dfm#1:mx0(27)} {regs.regs(2).lpi#1.dfm#1:mx0(28)} {regs.regs(2).lpi#1.dfm#1:mx0(29)} -attr xrf 32877 -attr oid 41 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(1).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(1).sva.dfm:mx0} 90 {regs.regs(1).sva.dfm:mx0(0)} {regs.regs(1).sva.dfm:mx0(1)} {regs.regs(1).sva.dfm:mx0(2)} {regs.regs(1).sva.dfm:mx0(3)} {regs.regs(1).sva.dfm:mx0(4)} {regs.regs(1).sva.dfm:mx0(5)} {regs.regs(1).sva.dfm:mx0(6)} {regs.regs(1).sva.dfm:mx0(7)} {regs.regs(1).sva.dfm:mx0(8)} {regs.regs(1).sva.dfm:mx0(9)} {regs.regs(1).sva.dfm:mx0(10)} {regs.regs(1).sva.dfm:mx0(11)} {regs.regs(1).sva.dfm:mx0(12)} {regs.regs(1).sva.dfm:mx0(13)} {regs.regs(1).sva.dfm:mx0(14)} {regs.regs(1).sva.dfm:mx0(15)} {regs.regs(1).sva.dfm:mx0(16)} {regs.regs(1).sva.dfm:mx0(17)} {regs.regs(1).sva.dfm:mx0(18)} {regs.regs(1).sva.dfm:mx0(19)} {regs.regs(1).sva.dfm:mx0(20)} {regs.regs(1).sva.dfm:mx0(21)} {regs.regs(1).sva.dfm:mx0(22)} {regs.regs(1).sva.dfm:mx0(23)} {regs.regs(1).sva.dfm:mx0(24)} {regs.regs(1).sva.dfm:mx0(25)} {regs.regs(1).sva.dfm:mx0(26)} {regs.regs(1).sva.dfm:mx0(27)} {regs.regs(1).sva.dfm:mx0(28)} {regs.regs(1).sva.dfm:mx0(29)} {regs.regs(1).sva.dfm:mx0(30)} {regs.regs(1).sva.dfm:mx0(31)} {regs.regs(1).sva.dfm:mx0(32)} {regs.regs(1).sva.dfm:mx0(33)} {regs.regs(1).sva.dfm:mx0(34)} {regs.regs(1).sva.dfm:mx0(35)} {regs.regs(1).sva.dfm:mx0(36)} {regs.regs(1).sva.dfm:mx0(37)} {regs.regs(1).sva.dfm:mx0(38)} {regs.regs(1).sva.dfm:mx0(39)} {regs.regs(1).sva.dfm:mx0(40)} {regs.regs(1).sva.dfm:mx0(41)} {regs.regs(1).sva.dfm:mx0(42)} {regs.regs(1).sva.dfm:mx0(43)} {regs.regs(1).sva.dfm:mx0(44)} {regs.regs(1).sva.dfm:mx0(45)} {regs.regs(1).sva.dfm:mx0(46)} {regs.regs(1).sva.dfm:mx0(47)} {regs.regs(1).sva.dfm:mx0(48)} {regs.regs(1).sva.dfm:mx0(49)} {regs.regs(1).sva.dfm:mx0(50)} {regs.regs(1).sva.dfm:mx0(51)} {regs.regs(1).sva.dfm:mx0(52)} {regs.regs(1).sva.dfm:mx0(53)} {regs.regs(1).sva.dfm:mx0(54)} {regs.regs(1).sva.dfm:mx0(55)} {regs.regs(1).sva.dfm:mx0(56)} {regs.regs(1).sva.dfm:mx0(57)} {regs.regs(1).sva.dfm:mx0(58)} {regs.regs(1).sva.dfm:mx0(59)} {regs.regs(1).sva.dfm:mx0(60)} {regs.regs(1).sva.dfm:mx0(61)} {regs.regs(1).sva.dfm:mx0(62)} {regs.regs(1).sva.dfm:mx0(63)} {regs.regs(1).sva.dfm:mx0(64)} {regs.regs(1).sva.dfm:mx0(65)} {regs.regs(1).sva.dfm:mx0(66)} {regs.regs(1).sva.dfm:mx0(67)} {regs.regs(1).sva.dfm:mx0(68)} {regs.regs(1).sva.dfm:mx0(69)} {regs.regs(1).sva.dfm:mx0(70)} {regs.regs(1).sva.dfm:mx0(71)} {regs.regs(1).sva.dfm:mx0(72)} {regs.regs(1).sva.dfm:mx0(73)} {regs.regs(1).sva.dfm:mx0(74)} {regs.regs(1).sva.dfm:mx0(75)} {regs.regs(1).sva.dfm:mx0(76)} {regs.regs(1).sva.dfm:mx0(77)} {regs.regs(1).sva.dfm:mx0(78)} {regs.regs(1).sva.dfm:mx0(79)} {regs.regs(1).sva.dfm:mx0(80)} {regs.regs(1).sva.dfm:mx0(81)} {regs.regs(1).sva.dfm:mx0(82)} {regs.regs(1).sva.dfm:mx0(83)} {regs.regs(1).sva.dfm:mx0(84)} {regs.regs(1).sva.dfm:mx0(85)} {regs.regs(1).sva.dfm:mx0(86)} {regs.regs(1).sva.dfm:mx0(87)} {regs.regs(1).sva.dfm:mx0(88)} {regs.regs(1).sva.dfm:mx0(89)} -attr xrf 32878 -attr oid 42 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(0).sva.dfm:mx0} 90 {regs.regs(0).sva.dfm:mx0(0)} {regs.regs(0).sva.dfm:mx0(1)} {regs.regs(0).sva.dfm:mx0(2)} {regs.regs(0).sva.dfm:mx0(3)} {regs.regs(0).sva.dfm:mx0(4)} {regs.regs(0).sva.dfm:mx0(5)} {regs.regs(0).sva.dfm:mx0(6)} {regs.regs(0).sva.dfm:mx0(7)} {regs.regs(0).sva.dfm:mx0(8)} {regs.regs(0).sva.dfm:mx0(9)} {regs.regs(0).sva.dfm:mx0(10)} {regs.regs(0).sva.dfm:mx0(11)} {regs.regs(0).sva.dfm:mx0(12)} {regs.regs(0).sva.dfm:mx0(13)} {regs.regs(0).sva.dfm:mx0(14)} {regs.regs(0).sva.dfm:mx0(15)} {regs.regs(0).sva.dfm:mx0(16)} {regs.regs(0).sva.dfm:mx0(17)} {regs.regs(0).sva.dfm:mx0(18)} {regs.regs(0).sva.dfm:mx0(19)} {regs.regs(0).sva.dfm:mx0(20)} {regs.regs(0).sva.dfm:mx0(21)} {regs.regs(0).sva.dfm:mx0(22)} {regs.regs(0).sva.dfm:mx0(23)} {regs.regs(0).sva.dfm:mx0(24)} {regs.regs(0).sva.dfm:mx0(25)} {regs.regs(0).sva.dfm:mx0(26)} {regs.regs(0).sva.dfm:mx0(27)} {regs.regs(0).sva.dfm:mx0(28)} {regs.regs(0).sva.dfm:mx0(29)} {regs.regs(0).sva.dfm:mx0(30)} {regs.regs(0).sva.dfm:mx0(31)} {regs.regs(0).sva.dfm:mx0(32)} {regs.regs(0).sva.dfm:mx0(33)} {regs.regs(0).sva.dfm:mx0(34)} {regs.regs(0).sva.dfm:mx0(35)} {regs.regs(0).sva.dfm:mx0(36)} {regs.regs(0).sva.dfm:mx0(37)} {regs.regs(0).sva.dfm:mx0(38)} {regs.regs(0).sva.dfm:mx0(39)} {regs.regs(0).sva.dfm:mx0(40)} {regs.regs(0).sva.dfm:mx0(41)} {regs.regs(0).sva.dfm:mx0(42)} {regs.regs(0).sva.dfm:mx0(43)} {regs.regs(0).sva.dfm:mx0(44)} {regs.regs(0).sva.dfm:mx0(45)} {regs.regs(0).sva.dfm:mx0(46)} {regs.regs(0).sva.dfm:mx0(47)} {regs.regs(0).sva.dfm:mx0(48)} {regs.regs(0).sva.dfm:mx0(49)} {regs.regs(0).sva.dfm:mx0(50)} {regs.regs(0).sva.dfm:mx0(51)} {regs.regs(0).sva.dfm:mx0(52)} {regs.regs(0).sva.dfm:mx0(53)} {regs.regs(0).sva.dfm:mx0(54)} {regs.regs(0).sva.dfm:mx0(55)} {regs.regs(0).sva.dfm:mx0(56)} {regs.regs(0).sva.dfm:mx0(57)} {regs.regs(0).sva.dfm:mx0(58)} {regs.regs(0).sva.dfm:mx0(59)} {regs.regs(0).sva.dfm:mx0(60)} {regs.regs(0).sva.dfm:mx0(61)} {regs.regs(0).sva.dfm:mx0(62)} {regs.regs(0).sva.dfm:mx0(63)} {regs.regs(0).sva.dfm:mx0(64)} {regs.regs(0).sva.dfm:mx0(65)} {regs.regs(0).sva.dfm:mx0(66)} {regs.regs(0).sva.dfm:mx0(67)} {regs.regs(0).sva.dfm:mx0(68)} {regs.regs(0).sva.dfm:mx0(69)} {regs.regs(0).sva.dfm:mx0(70)} {regs.regs(0).sva.dfm:mx0(71)} {regs.regs(0).sva.dfm:mx0(72)} {regs.regs(0).sva.dfm:mx0(73)} {regs.regs(0).sva.dfm:mx0(74)} {regs.regs(0).sva.dfm:mx0(75)} {regs.regs(0).sva.dfm:mx0(76)} {regs.regs(0).sva.dfm:mx0(77)} {regs.regs(0).sva.dfm:mx0(78)} {regs.regs(0).sva.dfm:mx0(79)} {regs.regs(0).sva.dfm:mx0(80)} {regs.regs(0).sva.dfm:mx0(81)} {regs.regs(0).sva.dfm:mx0(82)} {regs.regs(0).sva.dfm:mx0(83)} {regs.regs(0).sva.dfm:mx0(84)} {regs.regs(0).sva.dfm:mx0(85)} {regs.regs(0).sva.dfm:mx0(86)} {regs.regs(0).sva.dfm:mx0(87)} {regs.regs(0).sva.dfm:mx0(88)} {regs.regs(0).sva.dfm:mx0(89)} -attr xrf 32879 -attr oid 43 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {acc.imod#7.lpi#1.dfm:mx0(0)} -attr vt d
+load net {acc.imod#7.lpi#1.dfm:mx0(1)} -attr vt d
+load netBundle {acc.imod#7.lpi#1.dfm:mx0} 2 {acc.imod#7.lpi#1.dfm:mx0(0)} {acc.imod#7.lpi#1.dfm:mx0(1)} -attr xrf 32880 -attr oid 44 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm:mx0}
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(0)} -attr vt d
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(1)} -attr vt d
+load netBundle {acc.imod#6.lpi#1.dfm.sg1:mx0} 2 {acc.imod#6.lpi#1.dfm.sg1:mx0(0)} {acc.imod#6.lpi#1.dfm.sg1:mx0(1)} -attr xrf 32881 -attr oid 45 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1:mx0}
+load net {acc.imod#18.sva(0)} -attr vt d
+load net {acc.imod#18.sva(1)} -attr vt d
+load net {acc.imod#18.sva(2)} -attr vt d
+load netBundle {acc.imod#18.sva} 3 {acc.imod#18.sva(0)} {acc.imod#18.sva(1)} {acc.imod#18.sva(2)} -attr xrf 32882 -attr oid 46 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.sva}
+load net {ACC1:acc#118.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#118.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#118.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#118.psp#1.sva} 3 {ACC1:acc#118.psp#1.sva(0)} {ACC1:acc#118.psp#1.sva(1)} {ACC1:acc#118.psp#1.sva(2)} -attr xrf 32883 -attr oid 47 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.sva}
+load net {ACC1:acc#110.psp#2.sva(0)} -attr vt d
+load net {ACC1:acc#110.psp#2.sva(1)} -attr vt d
+load net {ACC1:acc#110.psp#2.sva(2)} -attr vt d
+load net {ACC1:acc#110.psp#2.sva(3)} -attr vt d
+load netBundle {ACC1:acc#110.psp#2.sva} 4 {ACC1:acc#110.psp#2.sva(0)} {ACC1:acc#110.psp#2.sva(1)} {ACC1:acc#110.psp#2.sva(2)} {ACC1:acc#110.psp#2.sva(3)} -attr xrf 32884 -attr oid 48 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.sva}
+load net {ACC1:acc#125.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(2)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(3)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(4)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(5)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(6)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(7)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(8)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(9)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(10)} -attr vt d
+load net {ACC1:acc#125.psp#1.sva(11)} -attr vt d
+load netBundle {ACC1:acc#125.psp#1.sva} 12 {ACC1:acc#125.psp#1.sva(0)} {ACC1:acc#125.psp#1.sva(1)} {ACC1:acc#125.psp#1.sva(2)} {ACC1:acc#125.psp#1.sva(3)} {ACC1:acc#125.psp#1.sva(4)} {ACC1:acc#125.psp#1.sva(5)} {ACC1:acc#125.psp#1.sva(6)} {ACC1:acc#125.psp#1.sva(7)} {ACC1:acc#125.psp#1.sva(8)} {ACC1:acc#125.psp#1.sva(9)} {ACC1:acc#125.psp#1.sva(10)} {ACC1:acc#125.psp#1.sva(11)} -attr xrf 32885 -attr oid 49 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#110.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#110.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#110.psp#1.sva(2)} -attr vt d
+load net {ACC1:acc#110.psp#1.sva(3)} -attr vt d
+load netBundle {ACC1:acc#110.psp#1.sva} 4 {ACC1:acc#110.psp#1.sva(0)} {ACC1:acc#110.psp#1.sva(1)} {ACC1:acc#110.psp#1.sva(2)} {ACC1:acc#110.psp#1.sva(3)} -attr xrf 32886 -attr oid 50 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.sva}
+load net {ACC1:acc#125.psp.sva(0)} -attr vt d
+load net {ACC1:acc#125.psp.sva(1)} -attr vt d
+load net {ACC1:acc#125.psp.sva(2)} -attr vt d
+load net {ACC1:acc#125.psp.sva(3)} -attr vt d
+load net {ACC1:acc#125.psp.sva(4)} -attr vt d
+load net {ACC1:acc#125.psp.sva(5)} -attr vt d
+load net {ACC1:acc#125.psp.sva(6)} -attr vt d
+load net {ACC1:acc#125.psp.sva(7)} -attr vt d
+load net {ACC1:acc#125.psp.sva(8)} -attr vt d
+load net {ACC1:acc#125.psp.sva(9)} -attr vt d
+load net {ACC1:acc#125.psp.sva(10)} -attr vt d
+load net {ACC1:acc#125.psp.sva(11)} -attr vt d
+load netBundle {ACC1:acc#125.psp.sva} 12 {ACC1:acc#125.psp.sva(0)} {ACC1:acc#125.psp.sva(1)} {ACC1:acc#125.psp.sva(2)} {ACC1:acc#125.psp.sva(3)} {ACC1:acc#125.psp.sva(4)} {ACC1:acc#125.psp.sva(5)} {ACC1:acc#125.psp.sva(6)} {ACC1:acc#125.psp.sva(7)} {ACC1:acc#125.psp.sva(8)} {ACC1:acc#125.psp.sva(9)} {ACC1:acc#125.psp.sva(10)} {ACC1:acc#125.psp.sva(11)} -attr xrf 32887 -attr oid 51 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#118.psp.sva(0)} -attr vt d
+load net {ACC1:acc#118.psp.sva(1)} -attr vt d
+load net {ACC1:acc#118.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#118.psp.sva} 3 {ACC1:acc#118.psp.sva(0)} {ACC1:acc#118.psp.sva(1)} {ACC1:acc#118.psp.sva(2)} -attr xrf 32888 -attr oid 52 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.sva}
+load net {acc.imod#6.sva(0)} -attr vt d
+load net {acc.imod#6.sva(1)} -attr vt d
+load net {acc.imod#6.sva(2)} -attr vt d
+load netBundle {acc.imod#6.sva} 3 {acc.imod#6.sva(0)} {acc.imod#6.sva(1)} {acc.imod#6.sva(2)} -attr xrf 32889 -attr oid 53 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.sva}
+load net {ACC1:acc#120.psp.sva(0)} -attr vt d
+load net {ACC1:acc#120.psp.sva(1)} -attr vt d
+load net {ACC1:acc#120.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#120.psp.sva} 3 {ACC1:acc#120.psp.sva(0)} {ACC1:acc#120.psp.sva(1)} {ACC1:acc#120.psp.sva(2)} -attr xrf 32890 -attr oid 54 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#120.psp.sva}
+load net {ACC1:acc#250.cse(0)} -attr vt d
+load net {ACC1:acc#250.cse(1)} -attr vt d
+load net {ACC1:acc#250.cse(2)} -attr vt d
+load netBundle {ACC1:acc#250.cse} 3 {ACC1:acc#250.cse(0)} {ACC1:acc#250.cse(1)} {ACC1:acc#250.cse(2)} -attr xrf 32891 -attr oid 55 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#120.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#120.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#120.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#120.psp#1.sva} 3 {ACC1:acc#120.psp#1.sva(0)} {ACC1:acc#120.psp#1.sva(1)} {ACC1:acc#120.psp#1.sva(2)} -attr xrf 32892 -attr oid 56 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#120.psp#1.sva}
+load net {ACC1:acc#277.cse(0)} -attr vt d
+load net {ACC1:acc#277.cse(1)} -attr vt d
+load net {ACC1:acc#277.cse(2)} -attr vt d
+load netBundle {ACC1:acc#277.cse} 3 {ACC1:acc#277.cse(0)} {ACC1:acc#277.cse(1)} {ACC1:acc#277.cse(2)} -attr xrf 32893 -attr oid 57 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#116.psp.sva(0)} -attr vt d
+load net {ACC1:acc#116.psp.sva(1)} -attr vt d
+load net {ACC1:acc#116.psp.sva(2)} -attr vt d
+load netBundle {ACC1:acc#116.psp.sva} 3 {ACC1:acc#116.psp.sva(0)} {ACC1:acc#116.psp.sva(1)} {ACC1:acc#116.psp.sva(2)} -attr xrf 32894 -attr oid 58 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp.sva}
+load net {ACC1:acc#197.cse(0)} -attr vt d
+load net {ACC1:acc#197.cse(1)} -attr vt d
+load net {ACC1:acc#197.cse(2)} -attr vt d
+load netBundle {ACC1:acc#197.cse} 3 {ACC1:acc#197.cse(0)} {ACC1:acc#197.cse(1)} {ACC1:acc#197.cse(2)} -attr xrf 32895 -attr oid 59 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#116.psp#1.sva(0)} -attr vt d
+load net {ACC1:acc#116.psp#1.sva(1)} -attr vt d
+load net {ACC1:acc#116.psp#1.sva(2)} -attr vt d
+load netBundle {ACC1:acc#116.psp#1.sva} 3 {ACC1:acc#116.psp#1.sva(0)} {ACC1:acc#116.psp#1.sva(1)} {ACC1:acc#116.psp#1.sva(2)} -attr xrf 32896 -attr oid 60 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp#1.sva}
+load net {ACC1:acc#224.cse(0)} -attr vt d
+load net {ACC1:acc#224.cse(1)} -attr vt d
+load net {ACC1:acc#224.cse(2)} -attr vt d
+load netBundle {ACC1:acc#224.cse} 3 {ACC1:acc#224.cse(0)} {ACC1:acc#224.cse(1)} {ACC1:acc#224.cse(2)} -attr xrf 32897 -attr oid 61 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {FRAME:p#1.lpi#1.dfm(0)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(1)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(2)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(3)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(4)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(5)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(6)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(7)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(8)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(9)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(10)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(11)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(12)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(13)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(14)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(15)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(16)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(17)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(18)} -attr vt d
+load netBundle {FRAME:p#1.lpi#1.dfm} 19 {FRAME:p#1.lpi#1.dfm(0)} {FRAME:p#1.lpi#1.dfm(1)} {FRAME:p#1.lpi#1.dfm(2)} {FRAME:p#1.lpi#1.dfm(3)} {FRAME:p#1.lpi#1.dfm(4)} {FRAME:p#1.lpi#1.dfm(5)} {FRAME:p#1.lpi#1.dfm(6)} {FRAME:p#1.lpi#1.dfm(7)} {FRAME:p#1.lpi#1.dfm(8)} {FRAME:p#1.lpi#1.dfm(9)} {FRAME:p#1.lpi#1.dfm(10)} {FRAME:p#1.lpi#1.dfm(11)} {FRAME:p#1.lpi#1.dfm(12)} {FRAME:p#1.lpi#1.dfm(13)} {FRAME:p#1.lpi#1.dfm(14)} {FRAME:p#1.lpi#1.dfm(15)} {FRAME:p#1.lpi#1.dfm(16)} {FRAME:p#1.lpi#1.dfm(17)} {FRAME:p#1.lpi#1.dfm(18)} -attr xrf 32898 -attr oid 62 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(0)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(1)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(2)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(3)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(5)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(7)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(9)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} -attr vt d
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -attr vt d
+load netBundle {ACC1:acc#125.psp#1.lpi#1.dfm:mx0} 12 {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(0)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(1)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(2)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(3)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(5)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(7)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(9)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -attr xrf 32899 -attr oid 63 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(0)} -attr vt d
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(1)} -attr vt d
+load netBundle {acc.imod#18.lpi#1.dfm.sg1:mx0} 2 {acc.imod#18.lpi#1.dfm.sg1:mx0(0)} {acc.imod#18.lpi#1.dfm.sg1:mx0(1)} -attr xrf 32900 -attr oid 64 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(0)} -attr vt d
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(1)} -attr vt d
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(2)} -attr vt d
+load netBundle {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0} 3 {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(0)} {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(1)} {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(2)} -attr xrf 32901 -attr oid 65 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load net {acc.imod#20.lpi#1.dfm:mx0(0)} -attr vt d
+load net {acc.imod#20.lpi#1.dfm:mx0(1)} -attr vt d
+load netBundle {acc.imod#20.lpi#1.dfm:mx0} 2 {acc.imod#20.lpi#1.dfm:mx0(0)} {acc.imod#20.lpi#1.dfm:mx0(1)} -attr xrf 32902 -attr oid 66 -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm:mx0}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(0)} -attr vt d
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(1)} -attr vt d
+load netBundle {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0} 2 {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(0)} {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(1)} -attr xrf 32903 -attr oid 67 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0}
+load net {FRAME:for:conc#16(0)} -attr vt d
+load net {FRAME:for:conc#16(1)} -attr vt d
+load netBundle {FRAME:for:conc#16} 2 {FRAME:for:conc#16(0)} {FRAME:for:conc#16(1)} -attr xrf 32904 -attr oid 68 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {mux.itm(0)} -attr vt d
+load net {mux.itm(1)} -attr vt d
+load net {mux.itm(2)} -attr vt d
+load net {mux.itm(3)} -attr vt d
+load net {mux.itm(4)} -attr vt d
+load net {mux.itm(5)} -attr vt d
+load net {mux.itm(6)} -attr vt d
+load net {mux.itm(7)} -attr vt d
+load net {mux.itm(8)} -attr vt d
+load net {mux.itm(9)} -attr vt d
+load net {mux.itm(10)} -attr vt d
+load net {mux.itm(11)} -attr vt d
+load net {mux.itm(12)} -attr vt d
+load net {mux.itm(13)} -attr vt d
+load net {mux.itm(14)} -attr vt d
+load net {mux.itm(15)} -attr vt d
+load net {mux.itm(16)} -attr vt d
+load net {mux.itm(17)} -attr vt d
+load net {mux.itm(18)} -attr vt d
+load net {mux.itm(19)} -attr vt d
+load net {mux.itm(20)} -attr vt d
+load net {mux.itm(21)} -attr vt d
+load net {mux.itm(22)} -attr vt d
+load net {mux.itm(23)} -attr vt d
+load net {mux.itm(24)} -attr vt d
+load net {mux.itm(25)} -attr vt d
+load net {mux.itm(26)} -attr vt d
+load net {mux.itm(27)} -attr vt d
+load net {mux.itm(28)} -attr vt d
+load net {mux.itm(29)} -attr vt d
+load netBundle {mux.itm} 30 {mux.itm(0)} {mux.itm(1)} {mux.itm(2)} {mux.itm(3)} {mux.itm(4)} {mux.itm(5)} {mux.itm(6)} {mux.itm(7)} {mux.itm(8)} {mux.itm(9)} {mux.itm(10)} {mux.itm(11)} {mux.itm(12)} {mux.itm(13)} {mux.itm(14)} {mux.itm(15)} {mux.itm(16)} {mux.itm(17)} {mux.itm(18)} {mux.itm(19)} {mux.itm(20)} {mux.itm(21)} {mux.itm(22)} {mux.itm(23)} {mux.itm(24)} {mux.itm(25)} {mux.itm(26)} {mux.itm(27)} {mux.itm(28)} {mux.itm(29)} -attr xrf 32905 -attr oid 69 -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {FRAME:conc#11.itm(0)} -attr vt d
+load net {FRAME:conc#11.itm(1)} -attr vt d
+load net {FRAME:conc#11.itm(2)} -attr vt d
+load net {FRAME:conc#11.itm(3)} -attr vt d
+load net {FRAME:conc#11.itm(4)} -attr vt d
+load net {FRAME:conc#11.itm(5)} -attr vt d
+load net {FRAME:conc#11.itm(6)} -attr vt d
+load net {FRAME:conc#11.itm(7)} -attr vt d
+load net {FRAME:conc#11.itm(8)} -attr vt d
+load net {FRAME:conc#11.itm(9)} -attr vt d
+load net {FRAME:conc#11.itm(10)} -attr vt d
+load net {FRAME:conc#11.itm(11)} -attr vt d
+load net {FRAME:conc#11.itm(12)} -attr vt d
+load net {FRAME:conc#11.itm(13)} -attr vt d
+load net {FRAME:conc#11.itm(14)} -attr vt d
+load net {FRAME:conc#11.itm(15)} -attr vt d
+load net {FRAME:conc#11.itm(16)} -attr vt d
+load net {FRAME:conc#11.itm(17)} -attr vt d
+load net {FRAME:conc#11.itm(18)} -attr vt d
+load net {FRAME:conc#11.itm(19)} -attr vt d
+load net {FRAME:conc#11.itm(20)} -attr vt d
+load net {FRAME:conc#11.itm(21)} -attr vt d
+load net {FRAME:conc#11.itm(22)} -attr vt d
+load net {FRAME:conc#11.itm(23)} -attr vt d
+load net {FRAME:conc#11.itm(24)} -attr vt d
+load net {FRAME:conc#11.itm(25)} -attr vt d
+load net {FRAME:conc#11.itm(26)} -attr vt d
+load net {FRAME:conc#11.itm(27)} -attr vt d
+load net {FRAME:conc#11.itm(28)} -attr vt d
+load net {FRAME:conc#11.itm(29)} -attr vt d
+load netBundle {FRAME:conc#11.itm} 30 {FRAME:conc#11.itm(0)} {FRAME:conc#11.itm(1)} {FRAME:conc#11.itm(2)} {FRAME:conc#11.itm(3)} {FRAME:conc#11.itm(4)} {FRAME:conc#11.itm(5)} {FRAME:conc#11.itm(6)} {FRAME:conc#11.itm(7)} {FRAME:conc#11.itm(8)} {FRAME:conc#11.itm(9)} {FRAME:conc#11.itm(10)} {FRAME:conc#11.itm(11)} {FRAME:conc#11.itm(12)} {FRAME:conc#11.itm(13)} {FRAME:conc#11.itm(14)} {FRAME:conc#11.itm(15)} {FRAME:conc#11.itm(16)} {FRAME:conc#11.itm(17)} {FRAME:conc#11.itm(18)} {FRAME:conc#11.itm(19)} {FRAME:conc#11.itm(20)} {FRAME:conc#11.itm(21)} {FRAME:conc#11.itm(22)} {FRAME:conc#11.itm(23)} {FRAME:conc#11.itm(24)} {FRAME:conc#11.itm(25)} {FRAME:conc#11.itm(26)} {FRAME:conc#11.itm(27)} {FRAME:conc#11.itm(28)} {FRAME:conc#11.itm(29)} -attr xrf 32906 -attr oid 70 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(0)} -attr vt d
+load net {FRAME:or.itm(1)} -attr vt d
+load net {FRAME:or.itm(2)} -attr vt d
+load net {FRAME:or.itm(3)} -attr vt d
+load net {FRAME:or.itm(4)} -attr vt d
+load net {FRAME:or.itm(5)} -attr vt d
+load net {FRAME:or.itm(6)} -attr vt d
+load net {FRAME:or.itm(7)} -attr vt d
+load net {FRAME:or.itm(8)} -attr vt d
+load net {FRAME:or.itm(9)} -attr vt d
+load netBundle {FRAME:or.itm} 10 {FRAME:or.itm(0)} {FRAME:or.itm(1)} {FRAME:or.itm(2)} {FRAME:or.itm(3)} {FRAME:or.itm(4)} {FRAME:or.itm(5)} {FRAME:or.itm(6)} {FRAME:or.itm(7)} {FRAME:or.itm(8)} {FRAME:or.itm(9)} -attr xrf 32907 -attr oid 71 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(3)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(4)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(5)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(6)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(7)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(8)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#4.itm(9)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#4.itm} 10 {slc(FRAME:acc#2.psp.sva)#4.itm(0)} {slc(FRAME:acc#2.psp.sva)#4.itm(1)} {slc(FRAME:acc#2.psp.sva)#4.itm(2)} {slc(FRAME:acc#2.psp.sva)#4.itm(3)} {slc(FRAME:acc#2.psp.sva)#4.itm(4)} {slc(FRAME:acc#2.psp.sva)#4.itm(5)} {slc(FRAME:acc#2.psp.sva)#4.itm(6)} {slc(FRAME:acc#2.psp.sva)#4.itm(7)} {slc(FRAME:acc#2.psp.sva)#4.itm(8)} {slc(FRAME:acc#2.psp.sva)#4.itm(9)} -attr xrf 32908 -attr oid 72 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {conc.itm(0)} -attr vt d
+load net {conc.itm(1)} -attr vt d
+load net {conc.itm(2)} -attr vt d
+load net {conc.itm(3)} -attr vt d
+load net {conc.itm(4)} -attr vt d
+load net {conc.itm(5)} -attr vt d
+load net {conc.itm(6)} -attr vt d
+load net {conc.itm(7)} -attr vt d
+load net {conc.itm(8)} -attr vt d
+load net {conc.itm(9)} -attr vt d
+load netBundle {conc.itm} 10 {conc.itm(0)} {conc.itm(1)} {conc.itm(2)} {conc.itm(3)} {conc.itm(4)} {conc.itm(5)} {conc.itm(6)} {conc.itm(7)} {conc.itm(8)} {conc.itm(9)} -attr xrf 32909 -attr oid 73 -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {slc(FRAME:acc#2.psp.sva)#5.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#5.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#5.itm} 2 {slc(FRAME:acc#2.psp.sva)#5.itm(0)} {slc(FRAME:acc#2.psp.sva)#5.itm(1)} -attr xrf 32910 -attr oid 74 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#5.itm}
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#2.itm(3)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#2.itm} 4 {slc(FRAME:acc#2.psp.sva)#2.itm(0)} {slc(FRAME:acc#2.psp.sva)#2.itm(1)} {slc(FRAME:acc#2.psp.sva)#2.itm(2)} {slc(FRAME:acc#2.psp.sva)#2.itm(3)} -attr xrf 32911 -attr oid 75 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#2.itm}
+load net {FRAME:or#3.itm(0)} -attr vt d
+load net {FRAME:or#3.itm(1)} -attr vt d
+load net {FRAME:or#3.itm(2)} -attr vt d
+load net {FRAME:or#3.itm(3)} -attr vt d
+load net {FRAME:or#3.itm(4)} -attr vt d
+load net {FRAME:or#3.itm(5)} -attr vt d
+load netBundle {FRAME:or#3.itm} 6 {FRAME:or#3.itm(0)} {FRAME:or#3.itm(1)} {FRAME:or#3.itm(2)} {FRAME:or#3.itm(3)} {FRAME:or#3.itm(4)} {FRAME:or#3.itm(5)} -attr xrf 32912 -attr oid 76 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(3)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(4)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#3.itm(5)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#3.itm} 6 {slc(FRAME:acc#2.psp.sva)#3.itm(0)} {slc(FRAME:acc#2.psp.sva)#3.itm(1)} {slc(FRAME:acc#2.psp.sva)#3.itm(2)} {slc(FRAME:acc#2.psp.sva)#3.itm(3)} {slc(FRAME:acc#2.psp.sva)#3.itm(4)} {slc(FRAME:acc#2.psp.sva)#3.itm(5)} -attr xrf 32913 -attr oid 77 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {conc#589.itm(0)} -attr vt d
+load net {conc#589.itm(1)} -attr vt d
+load net {conc#589.itm(2)} -attr vt d
+load net {conc#589.itm(3)} -attr vt d
+load net {conc#589.itm(4)} -attr vt d
+load net {conc#589.itm(5)} -attr vt d
+load netBundle {conc#589.itm} 6 {conc#589.itm(0)} {conc#589.itm(1)} {conc#589.itm(2)} {conc#589.itm(3)} {conc#589.itm(4)} {conc#589.itm(5)} -attr xrf 32914 -attr oid 78 -attr vt d -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {slc(FRAME:acc#2.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva)#1.itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva)#1.itm} 2 {slc(FRAME:acc#2.psp.sva)#1.itm(0)} {slc(FRAME:acc#2.psp.sva)#1.itm(1)} -attr xrf 32915 -attr oid 79 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#1.itm}
+load net {slc(FRAME:acc#2.psp.sva).itm(0)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(1)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(2)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(3)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(4)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(5)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(6)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(7)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(8)} -attr vt d
+load net {slc(FRAME:acc#2.psp.sva).itm(9)} -attr vt d
+load netBundle {slc(FRAME:acc#2.psp.sva).itm} 10 {slc(FRAME:acc#2.psp.sva).itm(0)} {slc(FRAME:acc#2.psp.sva).itm(1)} {slc(FRAME:acc#2.psp.sva).itm(2)} {slc(FRAME:acc#2.psp.sva).itm(3)} {slc(FRAME:acc#2.psp.sva).itm(4)} {slc(FRAME:acc#2.psp.sva).itm(5)} {slc(FRAME:acc#2.psp.sva).itm(6)} {slc(FRAME:acc#2.psp.sva).itm(7)} {slc(FRAME:acc#2.psp.sva).itm(8)} {slc(FRAME:acc#2.psp.sva).itm(9)} -attr xrf 32916 -attr oid 80 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva).itm}
+load net {mux#1.itm(0)} -attr vt d
+load net {mux#1.itm(1)} -attr vt d
+load net {mux#1.itm(2)} -attr vt d
+load net {mux#1.itm(3)} -attr vt d
+load net {mux#1.itm(4)} -attr vt d
+load net {mux#1.itm(5)} -attr vt d
+load net {mux#1.itm(6)} -attr vt d
+load net {mux#1.itm(7)} -attr vt d
+load net {mux#1.itm(8)} -attr vt d
+load net {mux#1.itm(9)} -attr vt d
+load net {mux#1.itm(10)} -attr vt d
+load net {mux#1.itm(11)} -attr vt d
+load net {mux#1.itm(12)} -attr vt d
+load net {mux#1.itm(13)} -attr vt d
+load net {mux#1.itm(14)} -attr vt d
+load net {mux#1.itm(15)} -attr vt d
+load netBundle {mux#1.itm} 16 {mux#1.itm(0)} {mux#1.itm(1)} {mux#1.itm(2)} {mux#1.itm(3)} {mux#1.itm(4)} {mux#1.itm(5)} {mux#1.itm(6)} {mux#1.itm(7)} {mux#1.itm(8)} {mux#1.itm(9)} {mux#1.itm(10)} {mux#1.itm(11)} {mux#1.itm(12)} {mux#1.itm(13)} {mux#1.itm(14)} {mux#1.itm(15)} -attr xrf 32917 -attr oid 81 -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {ACC1:acc#341.itm(0)} -attr vt d
+load net {ACC1:acc#341.itm(1)} -attr vt d
+load net {ACC1:acc#341.itm(2)} -attr vt d
+load net {ACC1:acc#341.itm(3)} -attr vt d
+load net {ACC1:acc#341.itm(4)} -attr vt d
+load net {ACC1:acc#341.itm(5)} -attr vt d
+load net {ACC1:acc#341.itm(6)} -attr vt d
+load net {ACC1:acc#341.itm(7)} -attr vt d
+load net {ACC1:acc#341.itm(8)} -attr vt d
+load net {ACC1:acc#341.itm(9)} -attr vt d
+load net {ACC1:acc#341.itm(10)} -attr vt d
+load net {ACC1:acc#341.itm(11)} -attr vt d
+load net {ACC1:acc#341.itm(12)} -attr vt d
+load netBundle {ACC1:acc#341.itm} 13 {ACC1:acc#341.itm(0)} {ACC1:acc#341.itm(1)} {ACC1:acc#341.itm(2)} {ACC1:acc#341.itm(3)} {ACC1:acc#341.itm(4)} {ACC1:acc#341.itm(5)} {ACC1:acc#341.itm(6)} {ACC1:acc#341.itm(7)} {ACC1:acc#341.itm(8)} {ACC1:acc#341.itm(9)} {ACC1:acc#341.itm(10)} {ACC1:acc#341.itm(11)} {ACC1:acc#341.itm(12)} -attr xrf 32918 -attr oid 82 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#340.itm(0)} -attr vt d
+load net {ACC1:acc#340.itm(1)} -attr vt d
+load net {ACC1:acc#340.itm(2)} -attr vt d
+load net {ACC1:acc#340.itm(3)} -attr vt d
+load net {ACC1:acc#340.itm(4)} -attr vt d
+load net {ACC1:acc#340.itm(5)} -attr vt d
+load net {ACC1:acc#340.itm(6)} -attr vt d
+load net {ACC1:acc#340.itm(7)} -attr vt d
+load net {ACC1:acc#340.itm(8)} -attr vt d
+load net {ACC1:acc#340.itm(9)} -attr vt d
+load net {ACC1:acc#340.itm(10)} -attr vt d
+load net {ACC1:acc#340.itm(11)} -attr vt d
+load net {ACC1:acc#340.itm(12)} -attr vt d
+load netBundle {ACC1:acc#340.itm} 13 {ACC1:acc#340.itm(0)} {ACC1:acc#340.itm(1)} {ACC1:acc#340.itm(2)} {ACC1:acc#340.itm(3)} {ACC1:acc#340.itm(4)} {ACC1:acc#340.itm(5)} {ACC1:acc#340.itm(6)} {ACC1:acc#340.itm(7)} {ACC1:acc#340.itm(8)} {ACC1:acc#340.itm(9)} {ACC1:acc#340.itm(10)} {ACC1:acc#340.itm(11)} {ACC1:acc#340.itm(12)} -attr xrf 32919 -attr oid 83 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:mul#20.itm(0)} -attr vt d
+load net {ACC1:mul#20.itm(1)} -attr vt d
+load net {ACC1:mul#20.itm(2)} -attr vt d
+load net {ACC1:mul#20.itm(3)} -attr vt d
+load net {ACC1:mul#20.itm(4)} -attr vt d
+load net {ACC1:mul#20.itm(5)} -attr vt d
+load net {ACC1:mul#20.itm(6)} -attr vt d
+load net {ACC1:mul#20.itm(7)} -attr vt d
+load net {ACC1:mul#20.itm(8)} -attr vt d
+load net {ACC1:mul#20.itm(9)} -attr vt d
+load net {ACC1:mul#20.itm(10)} -attr vt d
+load net {ACC1:mul#20.itm(11)} -attr vt d
+load net {ACC1:mul#20.itm(12)} -attr vt d
+load netBundle {ACC1:mul#20.itm} 13 {ACC1:mul#20.itm(0)} {ACC1:mul#20.itm(1)} {ACC1:mul#20.itm(2)} {ACC1:mul#20.itm(3)} {ACC1:mul#20.itm(4)} {ACC1:mul#20.itm(5)} {ACC1:mul#20.itm(6)} {ACC1:mul#20.itm(7)} {ACC1:mul#20.itm(8)} {ACC1:mul#20.itm(9)} {ACC1:mul#20.itm(10)} {ACC1:mul#20.itm(11)} {ACC1:mul#20.itm(12)} -attr xrf 32920 -attr oid 84 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC2:acc#5.itm(0)} -attr vt d
+load net {ACC2:acc#5.itm(1)} -attr vt d
+load netBundle {ACC2:acc#5.itm} 2 {ACC2:acc#5.itm(0)} {ACC2:acc#5.itm(1)} -attr xrf 32921 -attr oid 85 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#5.itm}
+load net {ACC1:acc#338.itm(0)} -attr vt d
+load net {ACC1:acc#338.itm(1)} -attr vt d
+load net {ACC1:acc#338.itm(2)} -attr vt d
+load net {ACC1:acc#338.itm(3)} -attr vt d
+load net {ACC1:acc#338.itm(4)} -attr vt d
+load net {ACC1:acc#338.itm(5)} -attr vt d
+load net {ACC1:acc#338.itm(6)} -attr vt d
+load net {ACC1:acc#338.itm(7)} -attr vt d
+load net {ACC1:acc#338.itm(8)} -attr vt d
+load net {ACC1:acc#338.itm(9)} -attr vt d
+load netBundle {ACC1:acc#338.itm} 10 {ACC1:acc#338.itm(0)} {ACC1:acc#338.itm(1)} {ACC1:acc#338.itm(2)} {ACC1:acc#338.itm(3)} {ACC1:acc#338.itm(4)} {ACC1:acc#338.itm(5)} {ACC1:acc#338.itm(6)} {ACC1:acc#338.itm(7)} {ACC1:acc#338.itm(8)} {ACC1:acc#338.itm(9)} -attr xrf 32922 -attr oid 86 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#336.itm(0)} -attr vt d
+load net {ACC1:acc#336.itm(1)} -attr vt d
+load net {ACC1:acc#336.itm(2)} -attr vt d
+load net {ACC1:acc#336.itm(3)} -attr vt d
+load net {ACC1:acc#336.itm(4)} -attr vt d
+load net {ACC1:acc#336.itm(5)} -attr vt d
+load net {ACC1:acc#336.itm(6)} -attr vt d
+load net {ACC1:acc#336.itm(7)} -attr vt d
+load net {ACC1:acc#336.itm(8)} -attr vt d
+load net {ACC1:acc#336.itm(9)} -attr vt d
+load netBundle {ACC1:acc#336.itm} 10 {ACC1:acc#336.itm(0)} {ACC1:acc#336.itm(1)} {ACC1:acc#336.itm(2)} {ACC1:acc#336.itm(3)} {ACC1:acc#336.itm(4)} {ACC1:acc#336.itm(5)} {ACC1:acc#336.itm(6)} {ACC1:acc#336.itm(7)} {ACC1:acc#336.itm(8)} {ACC1:acc#336.itm(9)} -attr xrf 32923 -attr oid 87 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:conc.itm(0)} -attr vt d
+load net {ACC1:conc.itm(1)} -attr vt d
+load net {ACC1:conc.itm(2)} -attr vt d
+load net {ACC1:conc.itm(3)} -attr vt d
+load net {ACC1:conc.itm(4)} -attr vt d
+load net {ACC1:conc.itm(5)} -attr vt d
+load net {ACC1:conc.itm(6)} -attr vt d
+load net {ACC1:conc.itm(7)} -attr vt d
+load net {ACC1:conc.itm(8)} -attr vt d
+load netBundle {ACC1:conc.itm} 9 {ACC1:conc.itm(0)} {ACC1:conc.itm(1)} {ACC1:conc.itm(2)} {ACC1:conc.itm(3)} {ACC1:conc.itm(4)} {ACC1:conc.itm(5)} {ACC1:conc.itm(6)} {ACC1:conc.itm(7)} {ACC1:conc.itm(8)} -attr xrf 32924 -attr oid 88 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(0)} -attr vt d
+load net {ACC1:mul#21.itm(1)} -attr vt d
+load net {ACC1:mul#21.itm(2)} -attr vt d
+load net {ACC1:mul#21.itm(3)} -attr vt d
+load net {ACC1:mul#21.itm(4)} -attr vt d
+load net {ACC1:mul#21.itm(5)} -attr vt d
+load netBundle {ACC1:mul#21.itm} 6 {ACC1:mul#21.itm(0)} {ACC1:mul#21.itm(1)} {ACC1:mul#21.itm(2)} {ACC1:mul#21.itm(3)} {ACC1:mul#21.itm(4)} {ACC1:mul#21.itm(5)} -attr xrf 32925 -attr oid 89 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load net {ACC2:acc#6.itm(0)} -attr vt d
+load net {ACC2:acc#6.itm(1)} -attr vt d
+load netBundle {ACC2:acc#6.itm} 2 {ACC2:acc#6.itm(0)} {ACC2:acc#6.itm(1)} -attr xrf 32926 -attr oid 90 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#6.itm}
+load net {ACC1-3:exs#563.itm(0)} -attr vt d
+load net {ACC1-3:exs#563.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#563.itm} 2 {ACC1-3:exs#563.itm(0)} {ACC1-3:exs#563.itm(1)} -attr xrf 32927 -attr oid 91 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#563.itm}
+load net {ACC1:acc#334.itm(0)} -attr vt d
+load net {ACC1:acc#334.itm(1)} -attr vt d
+load net {ACC1:acc#334.itm(2)} -attr vt d
+load net {ACC1:acc#334.itm(3)} -attr vt d
+load net {ACC1:acc#334.itm(4)} -attr vt d
+load net {ACC1:acc#334.itm(5)} -attr vt d
+load net {ACC1:acc#334.itm(6)} -attr vt d
+load net {ACC1:acc#334.itm(7)} -attr vt d
+load netBundle {ACC1:acc#334.itm} 8 {ACC1:acc#334.itm(0)} {ACC1:acc#334.itm(1)} {ACC1:acc#334.itm(2)} {ACC1:acc#334.itm(3)} {ACC1:acc#334.itm(4)} {ACC1:acc#334.itm(5)} {ACC1:acc#334.itm(6)} {ACC1:acc#334.itm(7)} -attr xrf 32928 -attr oid 92 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:mul#18.itm(0)} -attr vt d
+load net {ACC1:mul#18.itm(1)} -attr vt d
+load net {ACC1:mul#18.itm(2)} -attr vt d
+load net {ACC1:mul#18.itm(3)} -attr vt d
+load net {ACC1:mul#18.itm(4)} -attr vt d
+load net {ACC1:mul#18.itm(5)} -attr vt d
+load net {ACC1:mul#18.itm(6)} -attr vt d
+load net {ACC1:mul#18.itm(7)} -attr vt d
+load netBundle {ACC1:mul#18.itm} 8 {ACC1:mul#18.itm(0)} {ACC1:mul#18.itm(1)} {ACC1:mul#18.itm(2)} {ACC1:mul#18.itm(3)} {ACC1:mul#18.itm(4)} {ACC1:mul#18.itm(5)} {ACC1:mul#18.itm(6)} {ACC1:mul#18.itm(7)} -attr xrf 32929 -attr oid 93 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC2:acc#3.itm(0)} -attr vt d
+load net {ACC2:acc#3.itm(1)} -attr vt d
+load netBundle {ACC2:acc#3.itm} 2 {ACC2:acc#3.itm(0)} {ACC2:acc#3.itm(1)} -attr xrf 32930 -attr oid 94 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#3.itm}
+load net {ACC1:acc#330.itm(0)} -attr vt d
+load net {ACC1:acc#330.itm(1)} -attr vt d
+load net {ACC1:acc#330.itm(2)} -attr vt d
+load net {ACC1:acc#330.itm(3)} -attr vt d
+load net {ACC1:acc#330.itm(4)} -attr vt d
+load net {ACC1:acc#330.itm(5)} -attr vt d
+load net {ACC1:acc#330.itm(6)} -attr vt d
+load netBundle {ACC1:acc#330.itm} 7 {ACC1:acc#330.itm(0)} {ACC1:acc#330.itm(1)} {ACC1:acc#330.itm(2)} {ACC1:acc#330.itm(3)} {ACC1:acc#330.itm(4)} {ACC1:acc#330.itm(5)} {ACC1:acc#330.itm(6)} -attr xrf 32931 -attr oid 95 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:mul.itm(0)} -attr vt d
+load net {ACC1:mul.itm(1)} -attr vt d
+load net {ACC1:mul.itm(2)} -attr vt d
+load net {ACC1:mul.itm(3)} -attr vt d
+load net {ACC1:mul.itm(4)} -attr vt d
+load net {ACC1:mul.itm(5)} -attr vt d
+load netBundle {ACC1:mul.itm} 6 {ACC1:mul.itm(0)} {ACC1:mul.itm(1)} {ACC1:mul.itm(2)} {ACC1:mul.itm(3)} {ACC1:mul.itm(4)} {ACC1:mul.itm(5)} -attr xrf 32932 -attr oid 96 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC2:acc.itm(0)} -attr vt d
+load net {ACC2:acc.itm(1)} -attr vt d
+load netBundle {ACC2:acc.itm} 2 {ACC2:acc.itm(0)} {ACC2:acc.itm(1)} -attr xrf 32933 -attr oid 97 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {conc#590.itm(0)} -attr vt d
+load net {conc#590.itm(1)} -attr vt d
+load net {conc#590.itm(2)} -attr vt d
+load net {conc#590.itm(3)} -attr vt d
+load net {conc#590.itm(4)} -attr vt d
+load net {conc#590.itm(5)} -attr vt d
+load netBundle {conc#590.itm} 6 {conc#590.itm(0)} {conc#590.itm(1)} {conc#590.itm(2)} {conc#590.itm(3)} {conc#590.itm(4)} {conc#590.itm(5)} -attr xrf 32934 -attr oid 98 -attr vt d -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {ACC1-3:exs#568.itm(0)} -attr vt d
+load net {ACC1-3:exs#568.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#568.itm} 2 {ACC1-3:exs#568.itm(0)} {ACC1-3:exs#568.itm(1)} -attr xrf 32935 -attr oid 99 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#568.itm}
+load net {ACC1:acc#335.itm(0)} -attr vt d
+load net {ACC1:acc#335.itm(1)} -attr vt d
+load net {ACC1:acc#335.itm(2)} -attr vt d
+load net {ACC1:acc#335.itm(3)} -attr vt d
+load net {ACC1:acc#335.itm(4)} -attr vt d
+load net {ACC1:acc#335.itm(5)} -attr vt d
+load net {ACC1:acc#335.itm(6)} -attr vt d
+load net {ACC1:acc#335.itm(7)} -attr vt d
+load netBundle {ACC1:acc#335.itm} 8 {ACC1:acc#335.itm(0)} {ACC1:acc#335.itm(1)} {ACC1:acc#335.itm(2)} {ACC1:acc#335.itm(3)} {ACC1:acc#335.itm(4)} {ACC1:acc#335.itm(5)} {ACC1:acc#335.itm(6)} {ACC1:acc#335.itm(7)} -attr xrf 32936 -attr oid 100 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#332.itm(0)} -attr vt d
+load net {ACC1:acc#332.itm(1)} -attr vt d
+load net {ACC1:acc#332.itm(2)} -attr vt d
+load net {ACC1:acc#332.itm(3)} -attr vt d
+load net {ACC1:acc#332.itm(4)} -attr vt d
+load net {ACC1:acc#332.itm(5)} -attr vt d
+load net {ACC1:acc#332.itm(6)} -attr vt d
+load net {ACC1:acc#332.itm(7)} -attr vt d
+load netBundle {ACC1:acc#332.itm} 8 {ACC1:acc#332.itm(0)} {ACC1:acc#332.itm(1)} {ACC1:acc#332.itm(2)} {ACC1:acc#332.itm(3)} {ACC1:acc#332.itm(4)} {ACC1:acc#332.itm(5)} {ACC1:acc#332.itm(6)} {ACC1:acc#332.itm(7)} -attr xrf 32937 -attr oid 101 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1-1:exs#541.itm(0)} -attr vt d
+load net {ACC1-1:exs#541.itm(1)} -attr vt d
+load net {ACC1-1:exs#541.itm(2)} -attr vt d
+load net {ACC1-1:exs#541.itm(3)} -attr vt d
+load net {ACC1-1:exs#541.itm(4)} -attr vt d
+load net {ACC1-1:exs#541.itm(5)} -attr vt d
+load net {ACC1-1:exs#541.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#541.itm} 7 {ACC1-1:exs#541.itm(0)} {ACC1-1:exs#541.itm(1)} {ACC1-1:exs#541.itm(2)} {ACC1-1:exs#541.itm(3)} {ACC1-1:exs#541.itm(4)} {ACC1-1:exs#541.itm(5)} {ACC1-1:exs#541.itm(6)} -attr xrf 32938 -attr oid 102 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1-1:conc#240.itm(0)} -attr vt d
+load net {ACC1-1:conc#240.itm(1)} -attr vt d
+load net {ACC1-1:conc#240.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#240.itm} 3 {ACC1-1:conc#240.itm(0)} {ACC1-1:conc#240.itm(1)} {ACC1-1:conc#240.itm(2)} -attr xrf 32939 -attr oid 103 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#240.itm}
+load net {ACC1-1:exs#30.itm(0)} -attr vt d
+load net {ACC1-1:exs#30.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#30.itm} 2 {ACC1-1:exs#30.itm(0)} {ACC1-1:exs#30.itm(1)} -attr xrf 32940 -attr oid 104 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#30.itm}
+load net {ACC1:acc#328.itm(0)} -attr vt d
+load net {ACC1:acc#328.itm(1)} -attr vt d
+load net {ACC1:acc#328.itm(2)} -attr vt d
+load net {ACC1:acc#328.itm(3)} -attr vt d
+load net {ACC1:acc#328.itm(4)} -attr vt d
+load net {ACC1:acc#328.itm(5)} -attr vt d
+load netBundle {ACC1:acc#328.itm} 6 {ACC1:acc#328.itm(0)} {ACC1:acc#328.itm(1)} {ACC1:acc#328.itm(2)} {ACC1:acc#328.itm(3)} {ACC1:acc#328.itm(4)} {ACC1:acc#328.itm(5)} -attr xrf 32941 -attr oid 105 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#325.itm(0)} -attr vt d
+load net {ACC1:acc#325.itm(1)} -attr vt d
+load net {ACC1:acc#325.itm(2)} -attr vt d
+load net {ACC1:acc#325.itm(3)} -attr vt d
+load net {ACC1:acc#325.itm(4)} -attr vt d
+load netBundle {ACC1:acc#325.itm} 5 {ACC1:acc#325.itm(0)} {ACC1:acc#325.itm(1)} {ACC1:acc#325.itm(2)} {ACC1:acc#325.itm(3)} {ACC1:acc#325.itm(4)} -attr xrf 32942 -attr oid 106 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#319.itm(0)} -attr vt d
+load net {ACC1:acc#319.itm(1)} -attr vt d
+load net {ACC1:acc#319.itm(2)} -attr vt d
+load net {ACC1:acc#319.itm(3)} -attr vt d
+load netBundle {ACC1:acc#319.itm} 4 {ACC1:acc#319.itm(0)} {ACC1:acc#319.itm(1)} {ACC1:acc#319.itm(2)} {ACC1:acc#319.itm(3)} -attr xrf 32943 -attr oid 107 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:slc#97.itm(0)} -attr vt d
+load net {ACC1:slc#97.itm(1)} -attr vt d
+load net {ACC1:slc#97.itm(2)} -attr vt d
+load netBundle {ACC1:slc#97.itm} 3 {ACC1:slc#97.itm(0)} {ACC1:slc#97.itm(1)} {ACC1:slc#97.itm(2)} -attr xrf 32944 -attr oid 108 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#310.itm(0)} -attr vt d
+load net {ACC1:acc#310.itm(1)} -attr vt d
+load net {ACC1:acc#310.itm(2)} -attr vt d
+load net {ACC1:acc#310.itm(3)} -attr vt d
+load netBundle {ACC1:acc#310.itm} 4 {ACC1:acc#310.itm(0)} {ACC1:acc#310.itm(1)} {ACC1:acc#310.itm(2)} {ACC1:acc#310.itm(3)} -attr xrf 32945 -attr oid 109 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {exs.itm(0)} -attr vt d
+load net {exs.itm(1)} -attr vt d
+load net {exs.itm(2)} -attr vt d
+load netBundle {exs.itm} 3 {exs.itm(0)} {exs.itm(1)} {exs.itm(2)} -attr xrf 32946 -attr oid 110 -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {conc#591.itm(0)} -attr vt d
+load net {conc#591.itm(1)} -attr vt d
+load netBundle {conc#591.itm} 2 {conc#591.itm(0)} {conc#591.itm(1)} -attr xrf 32947 -attr oid 111 -attr vt d -attr @path {/sobel/sobel:core/conc#591.itm}
+load net {ACC1:exs#793.itm(0)} -attr vt d
+load net {ACC1:exs#793.itm(1)} -attr vt d
+load net {ACC1:exs#793.itm(2)} -attr vt d
+load netBundle {ACC1:exs#793.itm} 3 {ACC1:exs#793.itm(0)} {ACC1:exs#793.itm(1)} {ACC1:exs#793.itm(2)} -attr xrf 32948 -attr oid 112 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#793.itm}
+load net {ACC1:conc#642.itm(0)} -attr vt d
+load net {ACC1:conc#642.itm(1)} -attr vt d
+load netBundle {ACC1:conc#642.itm} 2 {ACC1:conc#642.itm(0)} {ACC1:conc#642.itm(1)} -attr xrf 32949 -attr oid 113 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#642.itm}
+load net {ACC1:slc#96.itm(0)} -attr vt d
+load net {ACC1:slc#96.itm(1)} -attr vt d
+load net {ACC1:slc#96.itm(2)} -attr vt d
+load netBundle {ACC1:slc#96.itm} 3 {ACC1:slc#96.itm(0)} {ACC1:slc#96.itm(1)} {ACC1:slc#96.itm(2)} -attr xrf 32950 -attr oid 114 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#309.itm(0)} -attr vt d
+load net {ACC1:acc#309.itm(1)} -attr vt d
+load net {ACC1:acc#309.itm(2)} -attr vt d
+load net {ACC1:acc#309.itm(3)} -attr vt d
+load netBundle {ACC1:acc#309.itm} 4 {ACC1:acc#309.itm(0)} {ACC1:acc#309.itm(1)} {ACC1:acc#309.itm(2)} {ACC1:acc#309.itm(3)} -attr xrf 32951 -attr oid 115 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {exs#54.itm(0)} -attr vt d
+load net {exs#54.itm(1)} -attr vt d
+load net {exs#54.itm(2)} -attr vt d
+load netBundle {exs#54.itm} 3 {exs#54.itm(0)} {exs#54.itm(1)} {exs#54.itm(2)} -attr xrf 32952 -attr oid 116 -attr vt d -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {conc#592.itm(0)} -attr vt d
+load net {conc#592.itm(1)} -attr vt d
+load netBundle {conc#592.itm} 2 {conc#592.itm(0)} {conc#592.itm(1)} -attr xrf 32953 -attr oid 117 -attr vt d -attr @path {/sobel/sobel:core/conc#592.itm}
+load net {ACC1:exs#795.itm(0)} -attr vt d
+load net {ACC1:exs#795.itm(1)} -attr vt d
+load net {ACC1:exs#795.itm(2)} -attr vt d
+load netBundle {ACC1:exs#795.itm} 3 {ACC1:exs#795.itm(0)} {ACC1:exs#795.itm(1)} {ACC1:exs#795.itm(2)} -attr xrf 32954 -attr oid 118 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#795.itm}
+load net {ACC1:conc#640.itm(0)} -attr vt d
+load net {ACC1:conc#640.itm(1)} -attr vt d
+load netBundle {ACC1:conc#640.itm} 2 {ACC1:conc#640.itm(0)} {ACC1:conc#640.itm(1)} -attr xrf 32955 -attr oid 119 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#640.itm}
+load net {ACC1:acc#318.itm(0)} -attr vt d
+load net {ACC1:acc#318.itm(1)} -attr vt d
+load net {ACC1:acc#318.itm(2)} -attr vt d
+load net {ACC1:acc#318.itm(3)} -attr vt d
+load netBundle {ACC1:acc#318.itm} 4 {ACC1:acc#318.itm(0)} {ACC1:acc#318.itm(1)} {ACC1:acc#318.itm(2)} {ACC1:acc#318.itm(3)} -attr xrf 32956 -attr oid 120 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:slc#94.itm(0)} -attr vt d
+load net {ACC1:slc#94.itm(1)} -attr vt d
+load net {ACC1:slc#94.itm(2)} -attr vt d
+load netBundle {ACC1:slc#94.itm} 3 {ACC1:slc#94.itm(0)} {ACC1:slc#94.itm(1)} {ACC1:slc#94.itm(2)} -attr xrf 32957 -attr oid 121 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#307.itm(0)} -attr vt d
+load net {ACC1:acc#307.itm(1)} -attr vt d
+load net {ACC1:acc#307.itm(2)} -attr vt d
+load net {ACC1:acc#307.itm(3)} -attr vt d
+load netBundle {ACC1:acc#307.itm} 4 {ACC1:acc#307.itm(0)} {ACC1:acc#307.itm(1)} {ACC1:acc#307.itm(2)} {ACC1:acc#307.itm(3)} -attr xrf 32958 -attr oid 122 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {exs#28.itm(0)} -attr vt d
+load net {exs#28.itm(1)} -attr vt d
+load net {exs#28.itm(2)} -attr vt d
+load netBundle {exs#28.itm} 3 {exs#28.itm(0)} {exs#28.itm(1)} {exs#28.itm(2)} -attr xrf 32959 -attr oid 123 -attr vt d -attr @path {/sobel/sobel:core/exs#28.itm}
+load net {conc#594.itm(0)} -attr vt d
+load net {conc#594.itm(1)} -attr vt d
+load netBundle {conc#594.itm} 2 {conc#594.itm(0)} {conc#594.itm(1)} -attr xrf 32960 -attr oid 124 -attr vt d -attr @path {/sobel/sobel:core/conc#594.itm}
+load net {ACC1:exs#797.itm(0)} -attr vt d
+load net {ACC1:exs#797.itm(1)} -attr vt d
+load net {ACC1:exs#797.itm(2)} -attr vt d
+load netBundle {ACC1:exs#797.itm} 3 {ACC1:exs#797.itm(0)} {ACC1:exs#797.itm(1)} {ACC1:exs#797.itm(2)} -attr xrf 32961 -attr oid 125 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#797.itm}
+load net {ACC1:conc#636.itm(0)} -attr vt d
+load net {ACC1:conc#636.itm(1)} -attr vt d
+load netBundle {ACC1:conc#636.itm} 2 {ACC1:conc#636.itm(0)} {ACC1:conc#636.itm(1)} -attr xrf 32962 -attr oid 126 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#636.itm}
+load net {ACC1:slc#93.itm(0)} -attr vt d
+load net {ACC1:slc#93.itm(1)} -attr vt d
+load net {ACC1:slc#93.itm(2)} -attr vt d
+load netBundle {ACC1:slc#93.itm} 3 {ACC1:slc#93.itm(0)} {ACC1:slc#93.itm(1)} {ACC1:slc#93.itm(2)} -attr xrf 32963 -attr oid 127 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#306.itm(0)} -attr vt d
+load net {ACC1:acc#306.itm(1)} -attr vt d
+load net {ACC1:acc#306.itm(2)} -attr vt d
+load net {ACC1:acc#306.itm(3)} -attr vt d
+load netBundle {ACC1:acc#306.itm} 4 {ACC1:acc#306.itm(0)} {ACC1:acc#306.itm(1)} {ACC1:acc#306.itm(2)} {ACC1:acc#306.itm(3)} -attr xrf 32964 -attr oid 128 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {exs#29.itm(0)} -attr vt d
+load net {exs#29.itm(1)} -attr vt d
+load net {exs#29.itm(2)} -attr vt d
+load netBundle {exs#29.itm} 3 {exs#29.itm(0)} {exs#29.itm(1)} {exs#29.itm(2)} -attr xrf 32965 -attr oid 129 -attr vt d -attr @path {/sobel/sobel:core/exs#29.itm}
+load net {conc#595.itm(0)} -attr vt d
+load net {conc#595.itm(1)} -attr vt d
+load netBundle {conc#595.itm} 2 {conc#595.itm(0)} {conc#595.itm(1)} -attr xrf 32966 -attr oid 130 -attr vt d -attr @path {/sobel/sobel:core/conc#595.itm}
+load net {ACC1:exs#799.itm(0)} -attr vt d
+load net {ACC1:exs#799.itm(1)} -attr vt d
+load net {ACC1:exs#799.itm(2)} -attr vt d
+load netBundle {ACC1:exs#799.itm} 3 {ACC1:exs#799.itm(0)} {ACC1:exs#799.itm(1)} {ACC1:exs#799.itm(2)} -attr xrf 32967 -attr oid 131 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#799.itm}
+load net {ACC1:conc#634.itm(0)} -attr vt d
+load net {ACC1:conc#634.itm(1)} -attr vt d
+load netBundle {ACC1:conc#634.itm} 2 {ACC1:conc#634.itm(0)} {ACC1:conc#634.itm(1)} -attr xrf 32968 -attr oid 132 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#634.itm}
+load net {ACC1:acc#324.itm(0)} -attr vt d
+load net {ACC1:acc#324.itm(1)} -attr vt d
+load net {ACC1:acc#324.itm(2)} -attr vt d
+load net {ACC1:acc#324.itm(3)} -attr vt d
+load net {ACC1:acc#324.itm(4)} -attr vt d
+load netBundle {ACC1:acc#324.itm} 5 {ACC1:acc#324.itm(0)} {ACC1:acc#324.itm(1)} {ACC1:acc#324.itm(2)} {ACC1:acc#324.itm(3)} {ACC1:acc#324.itm(4)} -attr xrf 32969 -attr oid 133 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#317.itm(0)} -attr vt d
+load net {ACC1:acc#317.itm(1)} -attr vt d
+load net {ACC1:acc#317.itm(2)} -attr vt d
+load net {ACC1:acc#317.itm(3)} -attr vt d
+load netBundle {ACC1:acc#317.itm} 4 {ACC1:acc#317.itm(0)} {ACC1:acc#317.itm(1)} {ACC1:acc#317.itm(2)} {ACC1:acc#317.itm(3)} -attr xrf 32970 -attr oid 134 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:slc#92.itm(0)} -attr vt d
+load net {ACC1:slc#92.itm(1)} -attr vt d
+load net {ACC1:slc#92.itm(2)} -attr vt d
+load netBundle {ACC1:slc#92.itm} 3 {ACC1:slc#92.itm(0)} {ACC1:slc#92.itm(1)} {ACC1:slc#92.itm(2)} -attr xrf 32971 -attr oid 135 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#92.itm}
+load net {ACC1:acc#305.itm(0)} -attr vt d
+load net {ACC1:acc#305.itm(1)} -attr vt d
+load net {ACC1:acc#305.itm(2)} -attr vt d
+load net {ACC1:acc#305.itm(3)} -attr vt d
+load netBundle {ACC1:acc#305.itm} 4 {ACC1:acc#305.itm(0)} {ACC1:acc#305.itm(1)} {ACC1:acc#305.itm(2)} {ACC1:acc#305.itm(3)} -attr xrf 32972 -attr oid 136 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {exs#55.itm(0)} -attr vt d
+load net {exs#55.itm(1)} -attr vt d
+load net {exs#55.itm(2)} -attr vt d
+load netBundle {exs#55.itm} 3 {exs#55.itm(0)} {exs#55.itm(1)} {exs#55.itm(2)} -attr xrf 32973 -attr oid 137 -attr vt d -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {conc#596.itm(0)} -attr vt d
+load net {conc#596.itm(1)} -attr vt d
+load netBundle {conc#596.itm} 2 {conc#596.itm(0)} {conc#596.itm(1)} -attr xrf 32974 -attr oid 138 -attr vt d -attr @path {/sobel/sobel:core/conc#596.itm}
+load net {ACC1:exs#801.itm(0)} -attr vt d
+load net {ACC1:exs#801.itm(1)} -attr vt d
+load net {ACC1:exs#801.itm(2)} -attr vt d
+load netBundle {ACC1:exs#801.itm} 3 {ACC1:exs#801.itm(0)} {ACC1:exs#801.itm(1)} {ACC1:exs#801.itm(2)} -attr xrf 32975 -attr oid 139 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#801.itm}
+load net {ACC1:conc#632.itm(0)} -attr vt d
+load net {ACC1:conc#632.itm(1)} -attr vt d
+load netBundle {ACC1:conc#632.itm} 2 {ACC1:conc#632.itm(0)} {ACC1:conc#632.itm(1)} -attr xrf 32976 -attr oid 140 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#632.itm}
+load net {ACC1:slc#91.itm(0)} -attr vt d
+load net {ACC1:slc#91.itm(1)} -attr vt d
+load net {ACC1:slc#91.itm(2)} -attr vt d
+load netBundle {ACC1:slc#91.itm} 3 {ACC1:slc#91.itm(0)} {ACC1:slc#91.itm(1)} {ACC1:slc#91.itm(2)} -attr xrf 32977 -attr oid 141 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#91.itm}
+load net {ACC1:acc#304.itm(0)} -attr vt d
+load net {ACC1:acc#304.itm(1)} -attr vt d
+load net {ACC1:acc#304.itm(2)} -attr vt d
+load net {ACC1:acc#304.itm(3)} -attr vt d
+load netBundle {ACC1:acc#304.itm} 4 {ACC1:acc#304.itm(0)} {ACC1:acc#304.itm(1)} {ACC1:acc#304.itm(2)} {ACC1:acc#304.itm(3)} -attr xrf 32978 -attr oid 142 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {exs#56.itm(0)} -attr vt d
+load net {exs#56.itm(1)} -attr vt d
+load net {exs#56.itm(2)} -attr vt d
+load netBundle {exs#56.itm} 3 {exs#56.itm(0)} {exs#56.itm(1)} {exs#56.itm(2)} -attr xrf 32979 -attr oid 143 -attr vt d -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {conc#598.itm(0)} -attr vt d
+load net {conc#598.itm(1)} -attr vt d
+load netBundle {conc#598.itm} 2 {conc#598.itm(0)} {conc#598.itm(1)} -attr xrf 32980 -attr oid 144 -attr vt d -attr @path {/sobel/sobel:core/conc#598.itm}
+load net {ACC1:exs#803.itm(0)} -attr vt d
+load net {ACC1:exs#803.itm(1)} -attr vt d
+load net {ACC1:exs#803.itm(2)} -attr vt d
+load netBundle {ACC1:exs#803.itm} 3 {ACC1:exs#803.itm(0)} {ACC1:exs#803.itm(1)} {ACC1:exs#803.itm(2)} -attr xrf 32981 -attr oid 145 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#803.itm}
+load net {ACC1:conc#630.itm(0)} -attr vt d
+load net {ACC1:conc#630.itm(1)} -attr vt d
+load netBundle {ACC1:conc#630.itm} 2 {ACC1:conc#630.itm(0)} {ACC1:conc#630.itm(1)} -attr xrf 32982 -attr oid 146 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#630.itm}
+load net {ACC1:acc#316.itm(0)} -attr vt d
+load net {ACC1:acc#316.itm(1)} -attr vt d
+load net {ACC1:acc#316.itm(2)} -attr vt d
+load net {ACC1:acc#316.itm(3)} -attr vt d
+load netBundle {ACC1:acc#316.itm} 4 {ACC1:acc#316.itm(0)} {ACC1:acc#316.itm(1)} {ACC1:acc#316.itm(2)} {ACC1:acc#316.itm(3)} -attr xrf 32983 -attr oid 147 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:slc#90.itm(0)} -attr vt d
+load net {ACC1:slc#90.itm(1)} -attr vt d
+load net {ACC1:slc#90.itm(2)} -attr vt d
+load netBundle {ACC1:slc#90.itm} 3 {ACC1:slc#90.itm(0)} {ACC1:slc#90.itm(1)} {ACC1:slc#90.itm(2)} -attr xrf 32984 -attr oid 148 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1:acc#303.itm(0)} -attr vt d
+load net {ACC1:acc#303.itm(1)} -attr vt d
+load net {ACC1:acc#303.itm(2)} -attr vt d
+load net {ACC1:acc#303.itm(3)} -attr vt d
+load netBundle {ACC1:acc#303.itm} 4 {ACC1:acc#303.itm(0)} {ACC1:acc#303.itm(1)} {ACC1:acc#303.itm(2)} {ACC1:acc#303.itm(3)} -attr xrf 32985 -attr oid 149 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {exs#30.itm(0)} -attr vt d
+load net {exs#30.itm(1)} -attr vt d
+load net {exs#30.itm(2)} -attr vt d
+load netBundle {exs#30.itm} 3 {exs#30.itm(0)} {exs#30.itm(1)} {exs#30.itm(2)} -attr xrf 32986 -attr oid 150 -attr vt d -attr @path {/sobel/sobel:core/exs#30.itm}
+load net {conc#600.itm(0)} -attr vt d
+load net {conc#600.itm(1)} -attr vt d
+load netBundle {conc#600.itm} 2 {conc#600.itm(0)} {conc#600.itm(1)} -attr xrf 32987 -attr oid 151 -attr vt d -attr @path {/sobel/sobel:core/conc#600.itm}
+load net {ACC1:exs#805.itm(0)} -attr vt d
+load net {ACC1:exs#805.itm(1)} -attr vt d
+load net {ACC1:exs#805.itm(2)} -attr vt d
+load netBundle {ACC1:exs#805.itm} 3 {ACC1:exs#805.itm(0)} {ACC1:exs#805.itm(1)} {ACC1:exs#805.itm(2)} -attr xrf 32988 -attr oid 152 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#805.itm}
+load net {ACC1:conc#628.itm(0)} -attr vt d
+load net {ACC1:conc#628.itm(1)} -attr vt d
+load netBundle {ACC1:conc#628.itm} 2 {ACC1:conc#628.itm(0)} {ACC1:conc#628.itm(1)} -attr xrf 32989 -attr oid 153 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#628.itm}
+load net {ACC1:slc#89.itm(0)} -attr vt d
+load net {ACC1:slc#89.itm(1)} -attr vt d
+load net {ACC1:slc#89.itm(2)} -attr vt d
+load netBundle {ACC1:slc#89.itm} 3 {ACC1:slc#89.itm(0)} {ACC1:slc#89.itm(1)} {ACC1:slc#89.itm(2)} -attr xrf 32990 -attr oid 154 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#302.itm(0)} -attr vt d
+load net {ACC1:acc#302.itm(1)} -attr vt d
+load net {ACC1:acc#302.itm(2)} -attr vt d
+load net {ACC1:acc#302.itm(3)} -attr vt d
+load netBundle {ACC1:acc#302.itm} 4 {ACC1:acc#302.itm(0)} {ACC1:acc#302.itm(1)} {ACC1:acc#302.itm(2)} {ACC1:acc#302.itm(3)} -attr xrf 32991 -attr oid 155 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {exs#31.itm(0)} -attr vt d
+load net {exs#31.itm(1)} -attr vt d
+load net {exs#31.itm(2)} -attr vt d
+load netBundle {exs#31.itm} 3 {exs#31.itm(0)} {exs#31.itm(1)} {exs#31.itm(2)} -attr xrf 32992 -attr oid 156 -attr vt d -attr @path {/sobel/sobel:core/exs#31.itm}
+load net {conc#601.itm(0)} -attr vt d
+load net {conc#601.itm(1)} -attr vt d
+load netBundle {conc#601.itm} 2 {conc#601.itm(0)} {conc#601.itm(1)} -attr xrf 32993 -attr oid 157 -attr vt d -attr @path {/sobel/sobel:core/conc#601.itm}
+load net {ACC1:exs#807.itm(0)} -attr vt d
+load net {ACC1:exs#807.itm(1)} -attr vt d
+load net {ACC1:exs#807.itm(2)} -attr vt d
+load netBundle {ACC1:exs#807.itm} 3 {ACC1:exs#807.itm(0)} {ACC1:exs#807.itm(1)} {ACC1:exs#807.itm(2)} -attr xrf 32994 -attr oid 158 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#807.itm}
+load net {ACC1:conc#626.itm(0)} -attr vt d
+load net {ACC1:conc#626.itm(1)} -attr vt d
+load netBundle {ACC1:conc#626.itm} 2 {ACC1:conc#626.itm(0)} {ACC1:conc#626.itm(1)} -attr xrf 32995 -attr oid 159 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#626.itm}
+load net {ACC1:acc#331.itm(0)} -attr vt d
+load net {ACC1:acc#331.itm(1)} -attr vt d
+load net {ACC1:acc#331.itm(2)} -attr vt d
+load net {ACC1:acc#331.itm(3)} -attr vt d
+load net {ACC1:acc#331.itm(4)} -attr vt d
+load net {ACC1:acc#331.itm(5)} -attr vt d
+load net {ACC1:acc#331.itm(6)} -attr vt d
+load netBundle {ACC1:acc#331.itm} 7 {ACC1:acc#331.itm(0)} {ACC1:acc#331.itm(1)} {ACC1:acc#331.itm(2)} {ACC1:acc#331.itm(3)} {ACC1:acc#331.itm(4)} {ACC1:acc#331.itm(5)} {ACC1:acc#331.itm(6)} -attr xrf 32996 -attr oid 160 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#327.itm(0)} -attr vt d
+load net {ACC1:acc#327.itm(1)} -attr vt d
+load net {ACC1:acc#327.itm(2)} -attr vt d
+load net {ACC1:acc#327.itm(3)} -attr vt d
+load net {ACC1:acc#327.itm(4)} -attr vt d
+load net {ACC1:acc#327.itm(5)} -attr vt d
+load netBundle {ACC1:acc#327.itm} 6 {ACC1:acc#327.itm(0)} {ACC1:acc#327.itm(1)} {ACC1:acc#327.itm(2)} {ACC1:acc#327.itm(3)} {ACC1:acc#327.itm(4)} {ACC1:acc#327.itm(5)} -attr xrf 32997 -attr oid 161 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#323.itm(0)} -attr vt d
+load net {ACC1:acc#323.itm(1)} -attr vt d
+load net {ACC1:acc#323.itm(2)} -attr vt d
+load net {ACC1:acc#323.itm(3)} -attr vt d
+load net {ACC1:acc#323.itm(4)} -attr vt d
+load netBundle {ACC1:acc#323.itm} 5 {ACC1:acc#323.itm(0)} {ACC1:acc#323.itm(1)} {ACC1:acc#323.itm(2)} {ACC1:acc#323.itm(3)} {ACC1:acc#323.itm(4)} -attr xrf 32998 -attr oid 162 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#315.itm(0)} -attr vt d
+load net {ACC1:acc#315.itm(1)} -attr vt d
+load net {ACC1:acc#315.itm(2)} -attr vt d
+load net {ACC1:acc#315.itm(3)} -attr vt d
+load netBundle {ACC1:acc#315.itm} 4 {ACC1:acc#315.itm(0)} {ACC1:acc#315.itm(1)} {ACC1:acc#315.itm(2)} {ACC1:acc#315.itm(3)} -attr xrf 32999 -attr oid 163 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:slc#88.itm(0)} -attr vt d
+load net {ACC1:slc#88.itm(1)} -attr vt d
+load net {ACC1:slc#88.itm(2)} -attr vt d
+load netBundle {ACC1:slc#88.itm} 3 {ACC1:slc#88.itm(0)} {ACC1:slc#88.itm(1)} {ACC1:slc#88.itm(2)} -attr xrf 33000 -attr oid 164 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#301.itm(0)} -attr vt d
+load net {ACC1:acc#301.itm(1)} -attr vt d
+load net {ACC1:acc#301.itm(2)} -attr vt d
+load net {ACC1:acc#301.itm(3)} -attr vt d
+load netBundle {ACC1:acc#301.itm} 4 {ACC1:acc#301.itm(0)} {ACC1:acc#301.itm(1)} {ACC1:acc#301.itm(2)} {ACC1:acc#301.itm(3)} -attr xrf 33001 -attr oid 165 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {exs#32.itm(0)} -attr vt d
+load net {exs#32.itm(1)} -attr vt d
+load net {exs#32.itm(2)} -attr vt d
+load netBundle {exs#32.itm} 3 {exs#32.itm(0)} {exs#32.itm(1)} {exs#32.itm(2)} -attr xrf 33002 -attr oid 166 -attr vt d -attr @path {/sobel/sobel:core/exs#32.itm}
+load net {conc#602.itm(0)} -attr vt d
+load net {conc#602.itm(1)} -attr vt d
+load netBundle {conc#602.itm} 2 {conc#602.itm(0)} {conc#602.itm(1)} -attr xrf 33003 -attr oid 167 -attr vt d -attr @path {/sobel/sobel:core/conc#602.itm}
+load net {ACC1:exs#809.itm(0)} -attr vt d
+load net {ACC1:exs#809.itm(1)} -attr vt d
+load net {ACC1:exs#809.itm(2)} -attr vt d
+load netBundle {ACC1:exs#809.itm} 3 {ACC1:exs#809.itm(0)} {ACC1:exs#809.itm(1)} {ACC1:exs#809.itm(2)} -attr xrf 33004 -attr oid 168 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#809.itm}
+load net {ACC1:conc#624.itm(0)} -attr vt d
+load net {ACC1:conc#624.itm(1)} -attr vt d
+load netBundle {ACC1:conc#624.itm} 2 {ACC1:conc#624.itm(0)} {ACC1:conc#624.itm(1)} -attr xrf 33005 -attr oid 169 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#624.itm}
+load net {ACC1:slc#87.itm(0)} -attr vt d
+load net {ACC1:slc#87.itm(1)} -attr vt d
+load net {ACC1:slc#87.itm(2)} -attr vt d
+load netBundle {ACC1:slc#87.itm} 3 {ACC1:slc#87.itm(0)} {ACC1:slc#87.itm(1)} {ACC1:slc#87.itm(2)} -attr xrf 33006 -attr oid 170 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#87.itm}
+load net {ACC1:acc#300.itm(0)} -attr vt d
+load net {ACC1:acc#300.itm(1)} -attr vt d
+load net {ACC1:acc#300.itm(2)} -attr vt d
+load net {ACC1:acc#300.itm(3)} -attr vt d
+load netBundle {ACC1:acc#300.itm} 4 {ACC1:acc#300.itm(0)} {ACC1:acc#300.itm(1)} {ACC1:acc#300.itm(2)} {ACC1:acc#300.itm(3)} -attr xrf 33007 -attr oid 171 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {exs#33.itm(0)} -attr vt d
+load net {exs#33.itm(1)} -attr vt d
+load net {exs#33.itm(2)} -attr vt d
+load netBundle {exs#33.itm} 3 {exs#33.itm(0)} {exs#33.itm(1)} {exs#33.itm(2)} -attr xrf 33008 -attr oid 172 -attr vt d -attr @path {/sobel/sobel:core/exs#33.itm}
+load net {conc#603.itm(0)} -attr vt d
+load net {conc#603.itm(1)} -attr vt d
+load netBundle {conc#603.itm} 2 {conc#603.itm(0)} {conc#603.itm(1)} -attr xrf 33009 -attr oid 173 -attr vt d -attr @path {/sobel/sobel:core/conc#603.itm}
+load net {ACC1:exs#811.itm(0)} -attr vt d
+load net {ACC1:exs#811.itm(1)} -attr vt d
+load net {ACC1:exs#811.itm(2)} -attr vt d
+load netBundle {ACC1:exs#811.itm} 3 {ACC1:exs#811.itm(0)} {ACC1:exs#811.itm(1)} {ACC1:exs#811.itm(2)} -attr xrf 33010 -attr oid 174 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#811.itm}
+load net {slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#6.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#6.itm} 2 {slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#6.itm(0)} {slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#6.itm(1)} -attr xrf 33011 -attr oid 175 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#6.itm}
+load net {ACC1:acc#314.itm(0)} -attr vt d
+load net {ACC1:acc#314.itm(1)} -attr vt d
+load net {ACC1:acc#314.itm(2)} -attr vt d
+load net {ACC1:acc#314.itm(3)} -attr vt d
+load netBundle {ACC1:acc#314.itm} 4 {ACC1:acc#314.itm(0)} {ACC1:acc#314.itm(1)} {ACC1:acc#314.itm(2)} {ACC1:acc#314.itm(3)} -attr xrf 33012 -attr oid 176 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:slc#86.itm(0)} -attr vt d
+load net {ACC1:slc#86.itm(1)} -attr vt d
+load net {ACC1:slc#86.itm(2)} -attr vt d
+load netBundle {ACC1:slc#86.itm} 3 {ACC1:slc#86.itm(0)} {ACC1:slc#86.itm(1)} {ACC1:slc#86.itm(2)} -attr xrf 33013 -attr oid 177 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#86.itm}
+load net {ACC1:acc#299.itm(0)} -attr vt d
+load net {ACC1:acc#299.itm(1)} -attr vt d
+load net {ACC1:acc#299.itm(2)} -attr vt d
+load net {ACC1:acc#299.itm(3)} -attr vt d
+load netBundle {ACC1:acc#299.itm} 4 {ACC1:acc#299.itm(0)} {ACC1:acc#299.itm(1)} {ACC1:acc#299.itm(2)} {ACC1:acc#299.itm(3)} -attr xrf 33014 -attr oid 178 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {exs#34.itm(0)} -attr vt d
+load net {exs#34.itm(1)} -attr vt d
+load net {exs#34.itm(2)} -attr vt d
+load netBundle {exs#34.itm} 3 {exs#34.itm(0)} {exs#34.itm(1)} {exs#34.itm(2)} -attr xrf 33015 -attr oid 179 -attr vt d -attr @path {/sobel/sobel:core/exs#34.itm}
+load net {conc#604.itm(0)} -attr vt d
+load net {conc#604.itm(1)} -attr vt d
+load netBundle {conc#604.itm} 2 {conc#604.itm(0)} {conc#604.itm(1)} -attr xrf 33016 -attr oid 180 -attr vt d -attr @path {/sobel/sobel:core/conc#604.itm}
+load net {ACC1:exs#813.itm(0)} -attr vt d
+load net {ACC1:exs#813.itm(1)} -attr vt d
+load net {ACC1:exs#813.itm(2)} -attr vt d
+load netBundle {ACC1:exs#813.itm} 3 {ACC1:exs#813.itm(0)} {ACC1:exs#813.itm(1)} {ACC1:exs#813.itm(2)} -attr xrf 33017 -attr oid 181 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#813.itm}
+load net {ACC1:conc#620.itm(0)} -attr vt d
+load net {ACC1:conc#620.itm(1)} -attr vt d
+load netBundle {ACC1:conc#620.itm} 2 {ACC1:conc#620.itm(0)} {ACC1:conc#620.itm(1)} -attr xrf 33018 -attr oid 182 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#620.itm}
+load net {ACC1:slc#85.itm(0)} -attr vt d
+load net {ACC1:slc#85.itm(1)} -attr vt d
+load net {ACC1:slc#85.itm(2)} -attr vt d
+load netBundle {ACC1:slc#85.itm} 3 {ACC1:slc#85.itm(0)} {ACC1:slc#85.itm(1)} {ACC1:slc#85.itm(2)} -attr xrf 33019 -attr oid 183 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#85.itm}
+load net {ACC1:acc#298.itm(0)} -attr vt d
+load net {ACC1:acc#298.itm(1)} -attr vt d
+load net {ACC1:acc#298.itm(2)} -attr vt d
+load net {ACC1:acc#298.itm(3)} -attr vt d
+load netBundle {ACC1:acc#298.itm} 4 {ACC1:acc#298.itm(0)} {ACC1:acc#298.itm(1)} {ACC1:acc#298.itm(2)} {ACC1:acc#298.itm(3)} -attr xrf 33020 -attr oid 184 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {exs#57.itm(0)} -attr vt d
+load net {exs#57.itm(1)} -attr vt d
+load net {exs#57.itm(2)} -attr vt d
+load netBundle {exs#57.itm} 3 {exs#57.itm(0)} {exs#57.itm(1)} {exs#57.itm(2)} -attr xrf 33021 -attr oid 185 -attr vt d -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {conc#605.itm(0)} -attr vt d
+load net {conc#605.itm(1)} -attr vt d
+load netBundle {conc#605.itm} 2 {conc#605.itm(0)} {conc#605.itm(1)} -attr xrf 33022 -attr oid 186 -attr vt d -attr @path {/sobel/sobel:core/conc#605.itm}
+load net {ACC1:exs#815.itm(0)} -attr vt d
+load net {ACC1:exs#815.itm(1)} -attr vt d
+load net {ACC1:exs#815.itm(2)} -attr vt d
+load netBundle {ACC1:exs#815.itm} 3 {ACC1:exs#815.itm(0)} {ACC1:exs#815.itm(1)} {ACC1:exs#815.itm(2)} -attr xrf 33023 -attr oid 187 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#815.itm}
+load net {ACC1:conc#618.itm(0)} -attr vt d
+load net {ACC1:conc#618.itm(1)} -attr vt d
+load netBundle {ACC1:conc#618.itm} 2 {ACC1:conc#618.itm(0)} {ACC1:conc#618.itm(1)} -attr xrf 33024 -attr oid 188 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#618.itm}
+load net {ACC1:acc#322.itm(0)} -attr vt d
+load net {ACC1:acc#322.itm(1)} -attr vt d
+load net {ACC1:acc#322.itm(2)} -attr vt d
+load net {ACC1:acc#322.itm(3)} -attr vt d
+load net {ACC1:acc#322.itm(4)} -attr vt d
+load netBundle {ACC1:acc#322.itm} 5 {ACC1:acc#322.itm(0)} {ACC1:acc#322.itm(1)} {ACC1:acc#322.itm(2)} {ACC1:acc#322.itm(3)} {ACC1:acc#322.itm(4)} -attr xrf 33025 -attr oid 189 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#313.itm(0)} -attr vt d
+load net {ACC1:acc#313.itm(1)} -attr vt d
+load net {ACC1:acc#313.itm(2)} -attr vt d
+load net {ACC1:acc#313.itm(3)} -attr vt d
+load netBundle {ACC1:acc#313.itm} 4 {ACC1:acc#313.itm(0)} {ACC1:acc#313.itm(1)} {ACC1:acc#313.itm(2)} {ACC1:acc#313.itm(3)} -attr xrf 33026 -attr oid 190 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:slc#84.itm(0)} -attr vt d
+load net {ACC1:slc#84.itm(1)} -attr vt d
+load net {ACC1:slc#84.itm(2)} -attr vt d
+load netBundle {ACC1:slc#84.itm} 3 {ACC1:slc#84.itm(0)} {ACC1:slc#84.itm(1)} {ACC1:slc#84.itm(2)} -attr xrf 33027 -attr oid 191 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#84.itm}
+load net {ACC1:acc#297.itm(0)} -attr vt d
+load net {ACC1:acc#297.itm(1)} -attr vt d
+load net {ACC1:acc#297.itm(2)} -attr vt d
+load net {ACC1:acc#297.itm(3)} -attr vt d
+load netBundle {ACC1:acc#297.itm} 4 {ACC1:acc#297.itm(0)} {ACC1:acc#297.itm(1)} {ACC1:acc#297.itm(2)} {ACC1:acc#297.itm(3)} -attr xrf 33028 -attr oid 192 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {exs#35.itm(0)} -attr vt d
+load net {exs#35.itm(1)} -attr vt d
+load net {exs#35.itm(2)} -attr vt d
+load netBundle {exs#35.itm} 3 {exs#35.itm(0)} {exs#35.itm(1)} {exs#35.itm(2)} -attr xrf 33029 -attr oid 193 -attr vt d -attr @path {/sobel/sobel:core/exs#35.itm}
+load net {conc#607.itm(0)} -attr vt d
+load net {conc#607.itm(1)} -attr vt d
+load netBundle {conc#607.itm} 2 {conc#607.itm(0)} {conc#607.itm(1)} -attr xrf 33030 -attr oid 194 -attr vt d -attr @path {/sobel/sobel:core/conc#607.itm}
+load net {ACC1:exs#817.itm(0)} -attr vt d
+load net {ACC1:exs#817.itm(1)} -attr vt d
+load net {ACC1:exs#817.itm(2)} -attr vt d
+load netBundle {ACC1:exs#817.itm} 3 {ACC1:exs#817.itm(0)} {ACC1:exs#817.itm(1)} {ACC1:exs#817.itm(2)} -attr xrf 33031 -attr oid 195 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#817.itm}
+load net {ACC1:conc#616.itm(0)} -attr vt d
+load net {ACC1:conc#616.itm(1)} -attr vt d
+load netBundle {ACC1:conc#616.itm} 2 {ACC1:conc#616.itm(0)} {ACC1:conc#616.itm(1)} -attr xrf 33032 -attr oid 196 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#616.itm}
+load net {ACC1:slc#83.itm(0)} -attr vt d
+load net {ACC1:slc#83.itm(1)} -attr vt d
+load net {ACC1:slc#83.itm(2)} -attr vt d
+load netBundle {ACC1:slc#83.itm} 3 {ACC1:slc#83.itm(0)} {ACC1:slc#83.itm(1)} {ACC1:slc#83.itm(2)} -attr xrf 33033 -attr oid 197 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#83.itm}
+load net {ACC1:acc#296.itm(0)} -attr vt d
+load net {ACC1:acc#296.itm(1)} -attr vt d
+load net {ACC1:acc#296.itm(2)} -attr vt d
+load net {ACC1:acc#296.itm(3)} -attr vt d
+load netBundle {ACC1:acc#296.itm} 4 {ACC1:acc#296.itm(0)} {ACC1:acc#296.itm(1)} {ACC1:acc#296.itm(2)} {ACC1:acc#296.itm(3)} -attr xrf 33034 -attr oid 198 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {exs#36.itm(0)} -attr vt d
+load net {exs#36.itm(1)} -attr vt d
+load net {exs#36.itm(2)} -attr vt d
+load netBundle {exs#36.itm} 3 {exs#36.itm(0)} {exs#36.itm(1)} {exs#36.itm(2)} -attr xrf 33035 -attr oid 199 -attr vt d -attr @path {/sobel/sobel:core/exs#36.itm}
+load net {conc#608.itm(0)} -attr vt d
+load net {conc#608.itm(1)} -attr vt d
+load netBundle {conc#608.itm} 2 {conc#608.itm(0)} {conc#608.itm(1)} -attr xrf 33036 -attr oid 200 -attr vt d -attr @path {/sobel/sobel:core/conc#608.itm}
+load net {ACC1:exs#819.itm(0)} -attr vt d
+load net {ACC1:exs#819.itm(1)} -attr vt d
+load net {ACC1:exs#819.itm(2)} -attr vt d
+load netBundle {ACC1:exs#819.itm} 3 {ACC1:exs#819.itm(0)} {ACC1:exs#819.itm(1)} {ACC1:exs#819.itm(2)} -attr xrf 33037 -attr oid 201 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#819.itm}
+load net {ACC1:conc#614.itm(0)} -attr vt d
+load net {ACC1:conc#614.itm(1)} -attr vt d
+load netBundle {ACC1:conc#614.itm} 2 {ACC1:conc#614.itm(0)} {ACC1:conc#614.itm(1)} -attr xrf 33038 -attr oid 202 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#614.itm}
+load net {ACC1:slc#99.itm(0)} -attr vt d
+load net {ACC1:slc#99.itm(1)} -attr vt d
+load net {ACC1:slc#99.itm(2)} -attr vt d
+load net {ACC1:slc#99.itm(3)} -attr vt d
+load netBundle {ACC1:slc#99.itm} 4 {ACC1:slc#99.itm(0)} {ACC1:slc#99.itm(1)} {ACC1:slc#99.itm(2)} {ACC1:slc#99.itm(3)} -attr xrf 33039 -attr oid 203 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#312.itm(0)} -attr vt d
+load net {ACC1:acc#312.itm(1)} -attr vt d
+load net {ACC1:acc#312.itm(2)} -attr vt d
+load net {ACC1:acc#312.itm(3)} -attr vt d
+load net {ACC1:acc#312.itm(4)} -attr vt d
+load netBundle {ACC1:acc#312.itm} 5 {ACC1:acc#312.itm(0)} {ACC1:acc#312.itm(1)} {ACC1:acc#312.itm(2)} {ACC1:acc#312.itm(3)} {ACC1:acc#312.itm(4)} -attr xrf 33040 -attr oid 204 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {conc#609.itm(0)} -attr vt d
+load net {conc#609.itm(1)} -attr vt d
+load net {conc#609.itm(2)} -attr vt d
+load net {conc#609.itm(3)} -attr vt d
+load netBundle {conc#609.itm} 4 {conc#609.itm(0)} {conc#609.itm(1)} {conc#609.itm(2)} {conc#609.itm(3)} -attr xrf 33041 -attr oid 205 -attr vt d -attr @path {/sobel/sobel:core/conc#609.itm}
+load net {ACC1:slc#82.itm(0)} -attr vt d
+load net {ACC1:slc#82.itm(1)} -attr vt d
+load net {ACC1:slc#82.itm(2)} -attr vt d
+load netBundle {ACC1:slc#82.itm} 3 {ACC1:slc#82.itm(0)} {ACC1:slc#82.itm(1)} {ACC1:slc#82.itm(2)} -attr xrf 33042 -attr oid 206 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#82.itm}
+load net {ACC1:acc#295.itm(0)} -attr vt d
+load net {ACC1:acc#295.itm(1)} -attr vt d
+load net {ACC1:acc#295.itm(2)} -attr vt d
+load net {ACC1:acc#295.itm(3)} -attr vt d
+load netBundle {ACC1:acc#295.itm} 4 {ACC1:acc#295.itm(0)} {ACC1:acc#295.itm(1)} {ACC1:acc#295.itm(2)} {ACC1:acc#295.itm(3)} -attr xrf 33043 -attr oid 207 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {conc#610.itm(0)} -attr vt d
+load net {conc#610.itm(1)} -attr vt d
+load net {conc#610.itm(2)} -attr vt d
+load netBundle {conc#610.itm} 3 {conc#610.itm(0)} {conc#610.itm(1)} {conc#610.itm(2)} -attr xrf 33044 -attr oid 208 -attr vt d -attr @path {/sobel/sobel:core/conc#610.itm}
+load net {ACC1:conc#612.itm(0)} -attr vt d
+load net {ACC1:conc#612.itm(1)} -attr vt d
+load net {ACC1:conc#612.itm(2)} -attr vt d
+load netBundle {ACC1:conc#612.itm} 3 {ACC1:conc#612.itm(0)} {ACC1:conc#612.itm(1)} {ACC1:conc#612.itm(2)} -attr xrf 33045 -attr oid 209 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#612.itm}
+load net {conc#611.itm(0)} -attr vt d
+load net {conc#611.itm(1)} -attr vt d
+load net {conc#611.itm(2)} -attr vt d
+load net {conc#611.itm(3)} -attr vt d
+load netBundle {conc#611.itm} 4 {conc#611.itm(0)} {conc#611.itm(1)} {conc#611.itm(2)} {conc#611.itm(3)} -attr xrf 33046 -attr oid 210 -attr vt d -attr @path {/sobel/sobel:core/conc#611.itm}
+load net {ACC1:acc#321.itm(0)} -attr vt d
+load net {ACC1:acc#321.itm(1)} -attr vt d
+load net {ACC1:acc#321.itm(2)} -attr vt d
+load net {ACC1:acc#321.itm(3)} -attr vt d
+load netBundle {ACC1:acc#321.itm} 4 {ACC1:acc#321.itm(0)} {ACC1:acc#321.itm(1)} {ACC1:acc#321.itm(2)} {ACC1:acc#321.itm(3)} -attr xrf 33047 -attr oid 211 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:slc#98.itm(0)} -attr vt d
+load net {ACC1:slc#98.itm(1)} -attr vt d
+load net {ACC1:slc#98.itm(2)} -attr vt d
+load net {ACC1:slc#98.itm(3)} -attr vt d
+load netBundle {ACC1:slc#98.itm} 4 {ACC1:slc#98.itm(0)} {ACC1:slc#98.itm(1)} {ACC1:slc#98.itm(2)} {ACC1:slc#98.itm(3)} -attr xrf 33048 -attr oid 212 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#311.itm(0)} -attr vt d
+load net {ACC1:acc#311.itm(1)} -attr vt d
+load net {ACC1:acc#311.itm(2)} -attr vt d
+load net {ACC1:acc#311.itm(3)} -attr vt d
+load net {ACC1:acc#311.itm(4)} -attr vt d
+load netBundle {ACC1:acc#311.itm} 5 {ACC1:acc#311.itm(0)} {ACC1:acc#311.itm(1)} {ACC1:acc#311.itm(2)} {ACC1:acc#311.itm(3)} {ACC1:acc#311.itm(4)} -attr xrf 33049 -attr oid 213 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {conc#612.itm(0)} -attr vt d
+load net {conc#612.itm(1)} -attr vt d
+load net {conc#612.itm(2)} -attr vt d
+load net {conc#612.itm(3)} -attr vt d
+load netBundle {conc#612.itm} 4 {conc#612.itm(0)} {conc#612.itm(1)} {conc#612.itm(2)} {conc#612.itm(3)} -attr xrf 33050 -attr oid 214 -attr vt d -attr @path {/sobel/sobel:core/conc#612.itm}
+load net {ACC1:conc#644.itm(0)} -attr vt d
+load net {ACC1:conc#644.itm(1)} -attr vt d
+load net {ACC1:conc#644.itm(2)} -attr vt d
+load netBundle {ACC1:conc#644.itm} 3 {ACC1:conc#644.itm(0)} {ACC1:conc#644.itm(1)} {ACC1:conc#644.itm(2)} -attr xrf 33051 -attr oid 215 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#644.itm}
+load net {ACC1:slc#95.itm(0)} -attr vt d
+load net {ACC1:slc#95.itm(1)} -attr vt d
+load net {ACC1:slc#95.itm(2)} -attr vt d
+load net {ACC1:slc#95.itm(3)} -attr vt d
+load netBundle {ACC1:slc#95.itm} 4 {ACC1:slc#95.itm(0)} {ACC1:slc#95.itm(1)} {ACC1:slc#95.itm(2)} {ACC1:slc#95.itm(3)} -attr xrf 33052 -attr oid 216 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#308.itm(0)} -attr vt d
+load net {ACC1:acc#308.itm(1)} -attr vt d
+load net {ACC1:acc#308.itm(2)} -attr vt d
+load net {ACC1:acc#308.itm(3)} -attr vt d
+load net {ACC1:acc#308.itm(4)} -attr vt d
+load netBundle {ACC1:acc#308.itm} 5 {ACC1:acc#308.itm(0)} {ACC1:acc#308.itm(1)} {ACC1:acc#308.itm(2)} {ACC1:acc#308.itm(3)} {ACC1:acc#308.itm(4)} -attr xrf 33053 -attr oid 217 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {exs#37.itm(0)} -attr vt d
+load net {exs#37.itm(1)} -attr vt d
+load net {exs#37.itm(2)} -attr vt d
+load netBundle {exs#37.itm} 3 {exs#37.itm(0)} {exs#37.itm(1)} {exs#37.itm(2)} -attr xrf 33054 -attr oid 218 -attr vt d -attr @path {/sobel/sobel:core/exs#37.itm}
+load net {conc#613.itm(0)} -attr vt d
+load net {conc#613.itm(1)} -attr vt d
+load netBundle {conc#613.itm} 2 {conc#613.itm(0)} {conc#613.itm(1)} -attr xrf 33055 -attr oid 219 -attr vt d -attr @path {/sobel/sobel:core/conc#613.itm}
+load net {ACC1:conc#638.itm(0)} -attr vt d
+load net {ACC1:conc#638.itm(1)} -attr vt d
+load net {ACC1:conc#638.itm(2)} -attr vt d
+load netBundle {ACC1:conc#638.itm} 3 {ACC1:conc#638.itm(0)} {ACC1:conc#638.itm(1)} {ACC1:conc#638.itm(2)} -attr xrf 33056 -attr oid 220 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#638.itm}
+load net {ACC1:acc#339.itm(0)} -attr vt d
+load net {ACC1:acc#339.itm(1)} -attr vt d
+load net {ACC1:acc#339.itm(2)} -attr vt d
+load net {ACC1:acc#339.itm(3)} -attr vt d
+load net {ACC1:acc#339.itm(4)} -attr vt d
+load net {ACC1:acc#339.itm(5)} -attr vt d
+load net {ACC1:acc#339.itm(6)} -attr vt d
+load net {ACC1:acc#339.itm(7)} -attr vt d
+load net {ACC1:acc#339.itm(8)} -attr vt d
+load net {ACC1:acc#339.itm(9)} -attr vt d
+load net {ACC1:acc#339.itm(10)} -attr vt d
+load net {ACC1:acc#339.itm(11)} -attr vt d
+load net {ACC1:acc#339.itm(12)} -attr vt d
+load netBundle {ACC1:acc#339.itm} 13 {ACC1:acc#339.itm(0)} {ACC1:acc#339.itm(1)} {ACC1:acc#339.itm(2)} {ACC1:acc#339.itm(3)} {ACC1:acc#339.itm(4)} {ACC1:acc#339.itm(5)} {ACC1:acc#339.itm(6)} {ACC1:acc#339.itm(7)} {ACC1:acc#339.itm(8)} {ACC1:acc#339.itm(9)} {ACC1:acc#339.itm(10)} {ACC1:acc#339.itm(11)} {ACC1:acc#339.itm(12)} -attr xrf 33057 -attr oid 221 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#337.itm(0)} -attr vt d
+load net {ACC1:acc#337.itm(1)} -attr vt d
+load net {ACC1:acc#337.itm(2)} -attr vt d
+load net {ACC1:acc#337.itm(3)} -attr vt d
+load net {ACC1:acc#337.itm(4)} -attr vt d
+load net {ACC1:acc#337.itm(5)} -attr vt d
+load net {ACC1:acc#337.itm(6)} -attr vt d
+load net {ACC1:acc#337.itm(7)} -attr vt d
+load net {ACC1:acc#337.itm(8)} -attr vt d
+load net {ACC1:acc#337.itm(9)} -attr vt d
+load net {ACC1:acc#337.itm(10)} -attr vt d
+load netBundle {ACC1:acc#337.itm} 11 {ACC1:acc#337.itm(0)} {ACC1:acc#337.itm(1)} {ACC1:acc#337.itm(2)} {ACC1:acc#337.itm(3)} {ACC1:acc#337.itm(4)} {ACC1:acc#337.itm(5)} {ACC1:acc#337.itm(6)} {ACC1:acc#337.itm(7)} {ACC1:acc#337.itm(8)} {ACC1:acc#337.itm(9)} {ACC1:acc#337.itm(10)} -attr xrf 33058 -attr oid 222 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:mul#19.itm(0)} -attr vt d
+load net {ACC1:mul#19.itm(1)} -attr vt d
+load net {ACC1:mul#19.itm(2)} -attr vt d
+load net {ACC1:mul#19.itm(3)} -attr vt d
+load net {ACC1:mul#19.itm(4)} -attr vt d
+load net {ACC1:mul#19.itm(5)} -attr vt d
+load net {ACC1:mul#19.itm(6)} -attr vt d
+load net {ACC1:mul#19.itm(7)} -attr vt d
+load net {ACC1:mul#19.itm(8)} -attr vt d
+load net {ACC1:mul#19.itm(9)} -attr vt d
+load netBundle {ACC1:mul#19.itm} 10 {ACC1:mul#19.itm(0)} {ACC1:mul#19.itm(1)} {ACC1:mul#19.itm(2)} {ACC1:mul#19.itm(3)} {ACC1:mul#19.itm(4)} {ACC1:mul#19.itm(5)} {ACC1:mul#19.itm(6)} {ACC1:mul#19.itm(7)} {ACC1:mul#19.itm(8)} {ACC1:mul#19.itm(9)} -attr xrf 33059 -attr oid 223 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC2:acc#4.itm(0)} -attr vt d
+load net {ACC2:acc#4.itm(1)} -attr vt d
+load netBundle {ACC2:acc#4.itm} 2 {ACC2:acc#4.itm(0)} {ACC2:acc#4.itm(1)} -attr xrf 33060 -attr oid 224 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#4.itm}
+load net {ACC1:acc#333.itm(0)} -attr vt d
+load net {ACC1:acc#333.itm(1)} -attr vt d
+load net {ACC1:acc#333.itm(2)} -attr vt d
+load net {ACC1:acc#333.itm(3)} -attr vt d
+load net {ACC1:acc#333.itm(4)} -attr vt d
+load net {ACC1:acc#333.itm(5)} -attr vt d
+load net {ACC1:acc#333.itm(6)} -attr vt d
+load net {ACC1:acc#333.itm(7)} -attr vt d
+load net {ACC1:acc#333.itm(8)} -attr vt d
+load netBundle {ACC1:acc#333.itm} 9 {ACC1:acc#333.itm(0)} {ACC1:acc#333.itm(1)} {ACC1:acc#333.itm(2)} {ACC1:acc#333.itm(3)} {ACC1:acc#333.itm(4)} {ACC1:acc#333.itm(5)} {ACC1:acc#333.itm(6)} {ACC1:acc#333.itm(7)} {ACC1:acc#333.itm(8)} -attr xrf 33061 -attr oid 225 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#329.itm(0)} -attr vt d
+load net {ACC1:acc#329.itm(1)} -attr vt d
+load net {ACC1:acc#329.itm(2)} -attr vt d
+load net {ACC1:acc#329.itm(3)} -attr vt d
+load net {ACC1:acc#329.itm(4)} -attr vt d
+load net {ACC1:acc#329.itm(5)} -attr vt d
+load net {ACC1:acc#329.itm(6)} -attr vt d
+load netBundle {ACC1:acc#329.itm} 7 {ACC1:acc#329.itm(0)} {ACC1:acc#329.itm(1)} {ACC1:acc#329.itm(2)} {ACC1:acc#329.itm(3)} {ACC1:acc#329.itm(4)} {ACC1:acc#329.itm(5)} {ACC1:acc#329.itm(6)} -attr xrf 33062 -attr oid 226 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {conc#614.itm(0)} -attr vt d
+load net {conc#614.itm(1)} -attr vt d
+load net {conc#614.itm(2)} -attr vt d
+load net {conc#614.itm(3)} -attr vt d
+load net {conc#614.itm(4)} -attr vt d
+load net {conc#614.itm(5)} -attr vt d
+load netBundle {conc#614.itm} 6 {conc#614.itm(0)} {conc#614.itm(1)} {conc#614.itm(2)} {conc#614.itm(3)} {conc#614.itm(4)} {conc#614.itm(5)} -attr xrf 33063 -attr oid 227 -attr vt d -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {ACC1-3:exs#570.itm(0)} -attr vt d
+load net {ACC1-3:exs#570.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#570.itm} 2 {ACC1-3:exs#570.itm(0)} {ACC1-3:exs#570.itm(1)} -attr xrf 33064 -attr oid 228 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#570.itm}
+load net {ACC1:acc#326.itm(0)} -attr vt d
+load net {ACC1:acc#326.itm(1)} -attr vt d
+load net {ACC1:acc#326.itm(2)} -attr vt d
+load net {ACC1:acc#326.itm(3)} -attr vt d
+load net {ACC1:acc#326.itm(4)} -attr vt d
+load netBundle {ACC1:acc#326.itm} 5 {ACC1:acc#326.itm(0)} {ACC1:acc#326.itm(1)} {ACC1:acc#326.itm(2)} {ACC1:acc#326.itm(3)} {ACC1:acc#326.itm(4)} -attr xrf 33065 -attr oid 229 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:conc#657.itm(0)} -attr vt d
+load net {ACC1:conc#657.itm(1)} -attr vt d
+load net {ACC1:conc#657.itm(2)} -attr vt d
+load net {ACC1:conc#657.itm(3)} -attr vt d
+load net {ACC1:conc#657.itm(4)} -attr vt d
+load netBundle {ACC1:conc#657.itm} 5 {ACC1:conc#657.itm(0)} {ACC1:conc#657.itm(1)} {ACC1:conc#657.itm(2)} {ACC1:conc#657.itm(3)} {ACC1:conc#657.itm(4)} -attr xrf 33066 -attr oid 230 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#657.itm}
+load net {ACC1:acc#347.itm(0)} -attr vt d
+load net {ACC1:acc#347.itm(1)} -attr vt d
+load netBundle {ACC1:acc#347.itm} 2 {ACC1:acc#347.itm(0)} {ACC1:acc#347.itm(1)} -attr xrf 33067 -attr oid 231 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load net {ACC1:acc#348.itm(0)} -attr vt d
+load net {ACC1:acc#348.itm(1)} -attr vt d
+load net {ACC1:acc#348.itm(2)} -attr vt d
+load netBundle {ACC1:acc#348.itm} 3 {ACC1:acc#348.itm(0)} {ACC1:acc#348.itm(1)} {ACC1:acc#348.itm(2)} -attr xrf 33068 -attr oid 232 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {ACC2:exs.itm(0)} -attr vt d
+load net {ACC2:exs.itm(1)} -attr vt d
+load netBundle {ACC2:exs.itm} 2 {ACC2:exs.itm(0)} {ACC2:exs.itm(1)} -attr xrf 33069 -attr oid 233 -attr vt d -attr @path {/sobel/sobel:core/ACC2:exs.itm}
+load net {ACC2:exs#1.itm(0)} -attr vt d
+load net {ACC2:exs#1.itm(1)} -attr vt d
+load netBundle {ACC2:exs#1.itm} 2 {ACC2:exs#1.itm(0)} {ACC2:exs#1.itm(1)} -attr xrf 33070 -attr oid 234 -attr vt d -attr @path {/sobel/sobel:core/ACC2:exs#1.itm}
+load net {conc#615.itm(0)} -attr vt d
+load net {conc#615.itm(1)} -attr vt d
+load net {conc#615.itm(2)} -attr vt d
+load net {conc#615.itm(3)} -attr vt d
+load net {conc#615.itm(4)} -attr vt d
+load netBundle {conc#615.itm} 5 {conc#615.itm(0)} {conc#615.itm(1)} {conc#615.itm(2)} {conc#615.itm(3)} {conc#615.itm(4)} -attr xrf 33071 -attr oid 235 -attr vt d -attr @path {/sobel/sobel:core/conc#615.itm}
+load net {ACC1-3:exs#566.itm(0)} -attr vt d
+load net {ACC1-3:exs#566.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#566.itm} 2 {ACC1-3:exs#566.itm(0)} {ACC1-3:exs#566.itm(1)} -attr xrf 33072 -attr oid 236 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#566.itm}
+load net {ACC1-3:exs#541.itm(0)} -attr vt d
+load net {ACC1-3:exs#541.itm(1)} -attr vt d
+load net {ACC1-3:exs#541.itm(2)} -attr vt d
+load net {ACC1-3:exs#541.itm(3)} -attr vt d
+load net {ACC1-3:exs#541.itm(4)} -attr vt d
+load net {ACC1-3:exs#541.itm(5)} -attr vt d
+load net {ACC1-3:exs#541.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#541.itm} 7 {ACC1-3:exs#541.itm(0)} {ACC1-3:exs#541.itm(1)} {ACC1-3:exs#541.itm(2)} {ACC1-3:exs#541.itm(3)} {ACC1-3:exs#541.itm(4)} {ACC1-3:exs#541.itm(5)} {ACC1-3:exs#541.itm(6)} -attr xrf 33073 -attr oid 237 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1-3:conc#240.itm(0)} -attr vt d
+load net {ACC1-3:conc#240.itm(1)} -attr vt d
+load net {ACC1-3:conc#240.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#240.itm} 3 {ACC1-3:conc#240.itm(0)} {ACC1-3:conc#240.itm(1)} {ACC1-3:conc#240.itm(2)} -attr xrf 33074 -attr oid 238 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#240.itm}
+load net {ACC1-3:exs#567.itm(0)} -attr vt d
+load net {ACC1-3:exs#567.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#567.itm} 2 {ACC1-3:exs#567.itm(0)} {ACC1-3:exs#567.itm(1)} -attr xrf 33075 -attr oid 239 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#567.itm}
+load net {ACC1:conc#441.itm(0)} -attr vt d
+load net {ACC1:conc#441.itm(1)} -attr vt d
+load net {ACC1:conc#441.itm(2)} -attr vt d
+load net {ACC1:conc#441.itm(3)} -attr vt d
+load net {ACC1:conc#441.itm(4)} -attr vt d
+load net {ACC1:conc#441.itm(5)} -attr vt d
+load net {ACC1:conc#441.itm(6)} -attr vt d
+load net {ACC1:conc#441.itm(7)} -attr vt d
+load net {ACC1:conc#441.itm(8)} -attr vt d
+load net {ACC1:conc#441.itm(9)} -attr vt d
+load net {ACC1:conc#441.itm(10)} -attr vt d
+load netBundle {ACC1:conc#441.itm} 11 {ACC1:conc#441.itm(0)} {ACC1:conc#441.itm(1)} {ACC1:conc#441.itm(2)} {ACC1:conc#441.itm(3)} {ACC1:conc#441.itm(4)} {ACC1:conc#441.itm(5)} {ACC1:conc#441.itm(6)} {ACC1:conc#441.itm(7)} {ACC1:conc#441.itm(8)} {ACC1:conc#441.itm(9)} {ACC1:conc#441.itm(10)} -attr xrf 33076 -attr oid 240 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(0)} -attr vt d
+load net {ACC1:mul#22.itm(1)} -attr vt d
+load net {ACC1:mul#22.itm(2)} -attr vt d
+load net {ACC1:mul#22.itm(3)} -attr vt d
+load net {ACC1:mul#22.itm(4)} -attr vt d
+load net {ACC1:mul#22.itm(5)} -attr vt d
+load net {ACC1:mul#22.itm(6)} -attr vt d
+load net {ACC1:mul#22.itm(7)} -attr vt d
+load netBundle {ACC1:mul#22.itm} 8 {ACC1:mul#22.itm(0)} {ACC1:mul#22.itm(1)} {ACC1:mul#22.itm(2)} {ACC1:mul#22.itm(3)} {ACC1:mul#22.itm(4)} {ACC1:mul#22.itm(5)} {ACC1:mul#22.itm(6)} {ACC1:mul#22.itm(7)} -attr xrf 33077 -attr oid 241 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC2:acc#7.itm(0)} -attr vt d
+load net {ACC2:acc#7.itm(1)} -attr vt d
+load netBundle {ACC2:acc#7.itm} 2 {ACC2:acc#7.itm(0)} {ACC2:acc#7.itm(1)} -attr xrf 33078 -attr oid 242 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC1-3:exs#553.itm(0)} -attr vt d
+load net {ACC1-3:exs#553.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#553.itm} 2 {ACC1-3:exs#553.itm(0)} {ACC1-3:exs#553.itm(1)} -attr xrf 33079 -attr oid 243 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#553.itm}
+load net {mux#2.itm(0)} -attr vt d
+load net {mux#2.itm(1)} -attr vt d
+load net {mux#2.itm(2)} -attr vt d
+load net {mux#2.itm(3)} -attr vt d
+load net {mux#2.itm(4)} -attr vt d
+load net {mux#2.itm(5)} -attr vt d
+load net {mux#2.itm(6)} -attr vt d
+load net {mux#2.itm(7)} -attr vt d
+load net {mux#2.itm(8)} -attr vt d
+load net {mux#2.itm(9)} -attr vt d
+load net {mux#2.itm(10)} -attr vt d
+load net {mux#2.itm(11)} -attr vt d
+load net {mux#2.itm(12)} -attr vt d
+load net {mux#2.itm(13)} -attr vt d
+load net {mux#2.itm(14)} -attr vt d
+load net {mux#2.itm(15)} -attr vt d
+load netBundle {mux#2.itm} 16 {mux#2.itm(0)} {mux#2.itm(1)} {mux#2.itm(2)} {mux#2.itm(3)} {mux#2.itm(4)} {mux#2.itm(5)} {mux#2.itm(6)} {mux#2.itm(7)} {mux#2.itm(8)} {mux#2.itm(9)} {mux#2.itm(10)} {mux#2.itm(11)} {mux#2.itm(12)} {mux#2.itm(13)} {mux#2.itm(14)} {mux#2.itm(15)} -attr xrf 33080 -attr oid 244 -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {FRAME:for:acc#26.itm(0)} -attr vt d
+load net {FRAME:for:acc#26.itm(1)} -attr vt d
+load net {FRAME:for:acc#26.itm(2)} -attr vt d
+load net {FRAME:for:acc#26.itm(3)} -attr vt d
+load net {FRAME:for:acc#26.itm(4)} -attr vt d
+load net {FRAME:for:acc#26.itm(5)} -attr vt d
+load net {FRAME:for:acc#26.itm(6)} -attr vt d
+load net {FRAME:for:acc#26.itm(7)} -attr vt d
+load net {FRAME:for:acc#26.itm(8)} -attr vt d
+load net {FRAME:for:acc#26.itm(9)} -attr vt d
+load net {FRAME:for:acc#26.itm(10)} -attr vt d
+load net {FRAME:for:acc#26.itm(11)} -attr vt d
+load netBundle {FRAME:for:acc#26.itm} 12 {FRAME:for:acc#26.itm(0)} {FRAME:for:acc#26.itm(1)} {FRAME:for:acc#26.itm(2)} {FRAME:for:acc#26.itm(3)} {FRAME:for:acc#26.itm(4)} {FRAME:for:acc#26.itm(5)} {FRAME:for:acc#26.itm(6)} {FRAME:for:acc#26.itm(7)} {FRAME:for:acc#26.itm(8)} {FRAME:for:acc#26.itm(9)} {FRAME:for:acc#26.itm(10)} {FRAME:for:acc#26.itm(11)} -attr xrf 33081 -attr oid 245 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#25.itm(0)} -attr vt d
+load net {FRAME:for:acc#25.itm(1)} -attr vt d
+load net {FRAME:for:acc#25.itm(2)} -attr vt d
+load net {FRAME:for:acc#25.itm(3)} -attr vt d
+load net {FRAME:for:acc#25.itm(4)} -attr vt d
+load net {FRAME:for:acc#25.itm(5)} -attr vt d
+load net {FRAME:for:acc#25.itm(6)} -attr vt d
+load net {FRAME:for:acc#25.itm(7)} -attr vt d
+load net {FRAME:for:acc#25.itm(8)} -attr vt d
+load net {FRAME:for:acc#25.itm(9)} -attr vt d
+load net {FRAME:for:acc#25.itm(10)} -attr vt d
+load net {FRAME:for:acc#25.itm(11)} -attr vt d
+load netBundle {FRAME:for:acc#25.itm} 12 {FRAME:for:acc#25.itm(0)} {FRAME:for:acc#25.itm(1)} {FRAME:for:acc#25.itm(2)} {FRAME:for:acc#25.itm(3)} {FRAME:for:acc#25.itm(4)} {FRAME:for:acc#25.itm(5)} {FRAME:for:acc#25.itm(6)} {FRAME:for:acc#25.itm(7)} {FRAME:for:acc#25.itm(8)} {FRAME:for:acc#25.itm(9)} {FRAME:for:acc#25.itm(10)} {FRAME:for:acc#25.itm(11)} -attr xrf 33082 -attr oid 246 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:mul#7.itm(0)} -attr vt d
+load net {FRAME:for:mul#7.itm(1)} -attr vt d
+load net {FRAME:for:mul#7.itm(2)} -attr vt d
+load net {FRAME:for:mul#7.itm(3)} -attr vt d
+load net {FRAME:for:mul#7.itm(4)} -attr vt d
+load net {FRAME:for:mul#7.itm(5)} -attr vt d
+load net {FRAME:for:mul#7.itm(6)} -attr vt d
+load net {FRAME:for:mul#7.itm(7)} -attr vt d
+load net {FRAME:for:mul#7.itm(8)} -attr vt d
+load net {FRAME:for:mul#7.itm(9)} -attr vt d
+load net {FRAME:for:mul#7.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#7.itm} 11 {FRAME:for:mul#7.itm(0)} {FRAME:for:mul#7.itm(1)} {FRAME:for:mul#7.itm(2)} {FRAME:for:mul#7.itm(3)} {FRAME:for:mul#7.itm(4)} {FRAME:for:mul#7.itm(5)} {FRAME:for:mul#7.itm(6)} {FRAME:for:mul#7.itm(7)} {FRAME:for:mul#7.itm(8)} {FRAME:for:mul#7.itm(9)} {FRAME:for:mul#7.itm(10)} -attr xrf 33083 -attr oid 247 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {regs.operator[]#16:mux.itm(0)} -attr vt d
+load net {regs.operator[]#16:mux.itm(1)} -attr vt d
+load net {regs.operator[]#16:mux.itm(2)} -attr vt d
+load net {regs.operator[]#16:mux.itm(3)} -attr vt d
+load net {regs.operator[]#16:mux.itm(4)} -attr vt d
+load net {regs.operator[]#16:mux.itm(5)} -attr vt d
+load net {regs.operator[]#16:mux.itm(6)} -attr vt d
+load net {regs.operator[]#16:mux.itm(7)} -attr vt d
+load net {regs.operator[]#16:mux.itm(8)} -attr vt d
+load net {regs.operator[]#16:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#16:mux.itm} 10 {regs.operator[]#16:mux.itm(0)} {regs.operator[]#16:mux.itm(1)} {regs.operator[]#16:mux.itm(2)} {regs.operator[]#16:mux.itm(3)} {regs.operator[]#16:mux.itm(4)} {regs.operator[]#16:mux.itm(5)} {regs.operator[]#16:mux.itm(6)} {regs.operator[]#16:mux.itm(7)} {regs.operator[]#16:mux.itm(8)} {regs.operator[]#16:mux.itm(9)} -attr xrf 33084 -attr oid 248 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm} 10 {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(0)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(1)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(2)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(3)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(4)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(5)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(6)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(7)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(8)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm(9)} -attr xrf 33085 -attr oid 249 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0).itm} 10 {slc(regs.regs(1).sva.dfm:mx0).itm(0)} {slc(regs.regs(1).sva.dfm:mx0).itm(1)} {slc(regs.regs(1).sva.dfm:mx0).itm(2)} {slc(regs.regs(1).sva.dfm:mx0).itm(3)} {slc(regs.regs(1).sva.dfm:mx0).itm(4)} {slc(regs.regs(1).sva.dfm:mx0).itm(5)} {slc(regs.regs(1).sva.dfm:mx0).itm(6)} {slc(regs.regs(1).sva.dfm:mx0).itm(7)} {slc(regs.regs(1).sva.dfm:mx0).itm(8)} {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr xrf 33086 -attr oid 250 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0).itm} 10 {slc(regs.regs(0).sva.dfm:mx0).itm(0)} {slc(regs.regs(0).sva.dfm:mx0).itm(1)} {slc(regs.regs(0).sva.dfm:mx0).itm(2)} {slc(regs.regs(0).sva.dfm:mx0).itm(3)} {slc(regs.regs(0).sva.dfm:mx0).itm(4)} {slc(regs.regs(0).sva.dfm:mx0).itm(5)} {slc(regs.regs(0).sva.dfm:mx0).itm(6)} {slc(regs.regs(0).sva.dfm:mx0).itm(7)} {slc(regs.regs(0).sva.dfm:mx0).itm(8)} {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr xrf 33087 -attr oid 251 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {FRAME:for:mul#8.itm(0)} -attr vt d
+load net {FRAME:for:mul#8.itm(1)} -attr vt d
+load net {FRAME:for:mul#8.itm(2)} -attr vt d
+load net {FRAME:for:mul#8.itm(3)} -attr vt d
+load net {FRAME:for:mul#8.itm(4)} -attr vt d
+load net {FRAME:for:mul#8.itm(5)} -attr vt d
+load net {FRAME:for:mul#8.itm(6)} -attr vt d
+load net {FRAME:for:mul#8.itm(7)} -attr vt d
+load net {FRAME:for:mul#8.itm(8)} -attr vt d
+load net {FRAME:for:mul#8.itm(9)} -attr vt d
+load net {FRAME:for:mul#8.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#8.itm} 11 {FRAME:for:mul#8.itm(0)} {FRAME:for:mul#8.itm(1)} {FRAME:for:mul#8.itm(2)} {FRAME:for:mul#8.itm(3)} {FRAME:for:mul#8.itm(4)} {FRAME:for:mul#8.itm(5)} {FRAME:for:mul#8.itm(6)} {FRAME:for:mul#8.itm(7)} {FRAME:for:mul#8.itm(8)} {FRAME:for:mul#8.itm(9)} {FRAME:for:mul#8.itm(10)} -attr xrf 33088 -attr oid 252 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {regs.operator[]#17:mux.itm(0)} -attr vt d
+load net {regs.operator[]#17:mux.itm(1)} -attr vt d
+load net {regs.operator[]#17:mux.itm(2)} -attr vt d
+load net {regs.operator[]#17:mux.itm(3)} -attr vt d
+load net {regs.operator[]#17:mux.itm(4)} -attr vt d
+load net {regs.operator[]#17:mux.itm(5)} -attr vt d
+load net {regs.operator[]#17:mux.itm(6)} -attr vt d
+load net {regs.operator[]#17:mux.itm(7)} -attr vt d
+load net {regs.operator[]#17:mux.itm(8)} -attr vt d
+load net {regs.operator[]#17:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#17:mux.itm} 10 {regs.operator[]#17:mux.itm(0)} {regs.operator[]#17:mux.itm(1)} {regs.operator[]#17:mux.itm(2)} {regs.operator[]#17:mux.itm(3)} {regs.operator[]#17:mux.itm(4)} {regs.operator[]#17:mux.itm(5)} {regs.operator[]#17:mux.itm(6)} {regs.operator[]#17:mux.itm(7)} {regs.operator[]#17:mux.itm(8)} {regs.operator[]#17:mux.itm(9)} -attr xrf 33089 -attr oid 253 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm} 10 {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(0)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(1)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(2)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(3)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(4)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(5)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(6)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(7)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(8)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm(9)} -attr xrf 33090 -attr oid 254 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr xrf 33091 -attr oid 255 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr xrf 33092 -attr oid 256 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {FRAME:for:mul#6.itm(0)} -attr vt d
+load net {FRAME:for:mul#6.itm(1)} -attr vt d
+load net {FRAME:for:mul#6.itm(2)} -attr vt d
+load net {FRAME:for:mul#6.itm(3)} -attr vt d
+load net {FRAME:for:mul#6.itm(4)} -attr vt d
+load net {FRAME:for:mul#6.itm(5)} -attr vt d
+load net {FRAME:for:mul#6.itm(6)} -attr vt d
+load net {FRAME:for:mul#6.itm(7)} -attr vt d
+load net {FRAME:for:mul#6.itm(8)} -attr vt d
+load net {FRAME:for:mul#6.itm(9)} -attr vt d
+load net {FRAME:for:mul#6.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#6.itm} 11 {FRAME:for:mul#6.itm(0)} {FRAME:for:mul#6.itm(1)} {FRAME:for:mul#6.itm(2)} {FRAME:for:mul#6.itm(3)} {FRAME:for:mul#6.itm(4)} {FRAME:for:mul#6.itm(5)} {FRAME:for:mul#6.itm(6)} {FRAME:for:mul#6.itm(7)} {FRAME:for:mul#6.itm(8)} {FRAME:for:mul#6.itm(9)} {FRAME:for:mul#6.itm(10)} -attr xrf 33093 -attr oid 257 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {regs.operator[]#15:mux.itm(0)} -attr vt d
+load net {regs.operator[]#15:mux.itm(1)} -attr vt d
+load net {regs.operator[]#15:mux.itm(2)} -attr vt d
+load net {regs.operator[]#15:mux.itm(3)} -attr vt d
+load net {regs.operator[]#15:mux.itm(4)} -attr vt d
+load net {regs.operator[]#15:mux.itm(5)} -attr vt d
+load net {regs.operator[]#15:mux.itm(6)} -attr vt d
+load net {regs.operator[]#15:mux.itm(7)} -attr vt d
+load net {regs.operator[]#15:mux.itm(8)} -attr vt d
+load net {regs.operator[]#15:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#15:mux.itm} 10 {regs.operator[]#15:mux.itm(0)} {regs.operator[]#15:mux.itm(1)} {regs.operator[]#15:mux.itm(2)} {regs.operator[]#15:mux.itm(3)} {regs.operator[]#15:mux.itm(4)} {regs.operator[]#15:mux.itm(5)} {regs.operator[]#15:mux.itm(6)} {regs.operator[]#15:mux.itm(7)} {regs.operator[]#15:mux.itm(8)} {regs.operator[]#15:mux.itm(9)} -attr xrf 33094 -attr oid 258 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm} 10 {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(0)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(1)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(2)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(3)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(4)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(5)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(6)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(7)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(8)} {slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm(9)} -attr xrf 33095 -attr oid 259 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr xrf 33096 -attr oid 260 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr xrf 33097 -attr oid 261 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {ACC1-3:acc#124.itm(0)} -attr vt d
+load net {ACC1-3:acc#124.itm(1)} -attr vt d
+load net {ACC1-3:acc#124.itm(2)} -attr vt d
+load net {ACC1-3:acc#124.itm(3)} -attr vt d
+load net {ACC1-3:acc#124.itm(4)} -attr vt d
+load net {ACC1-3:acc#124.itm(5)} -attr vt d
+load net {ACC1-3:acc#124.itm(6)} -attr vt d
+load net {ACC1-3:acc#124.itm(7)} -attr vt d
+load net {ACC1-3:acc#124.itm(8)} -attr vt d
+load net {ACC1-3:acc#124.itm(9)} -attr vt d
+load net {ACC1-3:acc#124.itm(10)} -attr vt d
+load net {ACC1-3:acc#124.itm(11)} -attr vt d
+load netBundle {ACC1-3:acc#124.itm} 12 {ACC1-3:acc#124.itm(0)} {ACC1-3:acc#124.itm(1)} {ACC1-3:acc#124.itm(2)} {ACC1-3:acc#124.itm(3)} {ACC1-3:acc#124.itm(4)} {ACC1-3:acc#124.itm(5)} {ACC1-3:acc#124.itm(6)} {ACC1-3:acc#124.itm(7)} {ACC1-3:acc#124.itm(8)} {ACC1-3:acc#124.itm(9)} {ACC1-3:acc#124.itm(10)} {ACC1-3:acc#124.itm(11)} -attr xrf 33098 -attr oid 262 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1:acc#268.itm(0)} -attr vt d
+load net {ACC1:acc#268.itm(1)} -attr vt d
+load net {ACC1:acc#268.itm(2)} -attr vt d
+load net {ACC1:acc#268.itm(3)} -attr vt d
+load net {ACC1:acc#268.itm(4)} -attr vt d
+load net {ACC1:acc#268.itm(5)} -attr vt d
+load net {ACC1:acc#268.itm(6)} -attr vt d
+load net {ACC1:acc#268.itm(7)} -attr vt d
+load net {ACC1:acc#268.itm(8)} -attr vt d
+load net {ACC1:acc#268.itm(9)} -attr vt d
+load net {ACC1:acc#268.itm(10)} -attr vt d
+load netBundle {ACC1:acc#268.itm} 11 {ACC1:acc#268.itm(0)} {ACC1:acc#268.itm(1)} {ACC1:acc#268.itm(2)} {ACC1:acc#268.itm(3)} {ACC1:acc#268.itm(4)} {ACC1:acc#268.itm(5)} {ACC1:acc#268.itm(6)} {ACC1:acc#268.itm(7)} {ACC1:acc#268.itm(8)} {ACC1:acc#268.itm(9)} {ACC1:acc#268.itm(10)} -attr xrf 33099 -attr oid 263 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {conc#616.itm(0)} -attr vt d
+load net {conc#616.itm(1)} -attr vt d
+load net {conc#616.itm(2)} -attr vt d
+load net {conc#616.itm(3)} -attr vt d
+load net {conc#616.itm(4)} -attr vt d
+load net {conc#616.itm(5)} -attr vt d
+load net {conc#616.itm(6)} -attr vt d
+load net {conc#616.itm(7)} -attr vt d
+load net {conc#616.itm(8)} -attr vt d
+load net {conc#616.itm(9)} -attr vt d
+load netBundle {conc#616.itm} 10 {conc#616.itm(0)} {conc#616.itm(1)} {conc#616.itm(2)} {conc#616.itm(3)} {conc#616.itm(4)} {conc#616.itm(5)} {conc#616.itm(6)} {conc#616.itm(7)} {conc#616.itm(8)} {conc#616.itm(9)} -attr xrf 33100 -attr oid 264 -attr vt d -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {ACC1:acc#266.itm(0)} -attr vt d
+load net {ACC1:acc#266.itm(1)} -attr vt d
+load net {ACC1:acc#266.itm(2)} -attr vt d
+load net {ACC1:acc#266.itm(3)} -attr vt d
+load net {ACC1:acc#266.itm(4)} -attr vt d
+load net {ACC1:acc#266.itm(5)} -attr vt d
+load net {ACC1:acc#266.itm(6)} -attr vt d
+load net {ACC1:acc#266.itm(7)} -attr vt d
+load net {ACC1:acc#266.itm(8)} -attr vt d
+load net {ACC1:acc#266.itm(9)} -attr vt d
+load net {ACC1:acc#266.itm(10)} -attr vt d
+load netBundle {ACC1:acc#266.itm} 11 {ACC1:acc#266.itm(0)} {ACC1:acc#266.itm(1)} {ACC1:acc#266.itm(2)} {ACC1:acc#266.itm(3)} {ACC1:acc#266.itm(4)} {ACC1:acc#266.itm(5)} {ACC1:acc#266.itm(6)} {ACC1:acc#266.itm(7)} {ACC1:acc#266.itm(8)} {ACC1:acc#266.itm(9)} {ACC1:acc#266.itm(10)} -attr xrf 33101 -attr oid 265 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#264.itm(0)} -attr vt d
+load net {ACC1:acc#264.itm(1)} -attr vt d
+load net {ACC1:acc#264.itm(2)} -attr vt d
+load net {ACC1:acc#264.itm(3)} -attr vt d
+load net {ACC1:acc#264.itm(4)} -attr vt d
+load net {ACC1:acc#264.itm(5)} -attr vt d
+load net {ACC1:acc#264.itm(6)} -attr vt d
+load net {ACC1:acc#264.itm(7)} -attr vt d
+load net {ACC1:acc#264.itm(8)} -attr vt d
+load net {ACC1:acc#264.itm(9)} -attr vt d
+load netBundle {ACC1:acc#264.itm} 10 {ACC1:acc#264.itm(0)} {ACC1:acc#264.itm(1)} {ACC1:acc#264.itm(2)} {ACC1:acc#264.itm(3)} {ACC1:acc#264.itm(4)} {ACC1:acc#264.itm(5)} {ACC1:acc#264.itm(6)} {ACC1:acc#264.itm(7)} {ACC1:acc#264.itm(8)} {ACC1:acc#264.itm(9)} -attr xrf 33102 -attr oid 266 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#262.itm(0)} -attr vt d
+load net {ACC1:acc#262.itm(1)} -attr vt d
+load net {ACC1:acc#262.itm(2)} -attr vt d
+load net {ACC1:acc#262.itm(3)} -attr vt d
+load net {ACC1:acc#262.itm(4)} -attr vt d
+load net {ACC1:acc#262.itm(5)} -attr vt d
+load net {ACC1:acc#262.itm(6)} -attr vt d
+load net {ACC1:acc#262.itm(7)} -attr vt d
+load netBundle {ACC1:acc#262.itm} 8 {ACC1:acc#262.itm(0)} {ACC1:acc#262.itm(1)} {ACC1:acc#262.itm(2)} {ACC1:acc#262.itm(3)} {ACC1:acc#262.itm(4)} {ACC1:acc#262.itm(5)} {ACC1:acc#262.itm(6)} {ACC1:acc#262.itm(7)} -attr xrf 33103 -attr oid 267 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#259.itm(0)} -attr vt d
+load net {ACC1:acc#259.itm(1)} -attr vt d
+load net {ACC1:acc#259.itm(2)} -attr vt d
+load net {ACC1:acc#259.itm(3)} -attr vt d
+load net {ACC1:acc#259.itm(4)} -attr vt d
+load net {ACC1:acc#259.itm(5)} -attr vt d
+load netBundle {ACC1:acc#259.itm} 6 {ACC1:acc#259.itm(0)} {ACC1:acc#259.itm(1)} {ACC1:acc#259.itm(2)} {ACC1:acc#259.itm(3)} {ACC1:acc#259.itm(4)} {ACC1:acc#259.itm(5)} -attr xrf 33104 -attr oid 268 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#256.itm(0)} -attr vt d
+load net {ACC1:acc#256.itm(1)} -attr vt d
+load net {ACC1:acc#256.itm(2)} -attr vt d
+load net {ACC1:acc#256.itm(3)} -attr vt d
+load netBundle {ACC1:acc#256.itm} 4 {ACC1:acc#256.itm(0)} {ACC1:acc#256.itm(1)} {ACC1:acc#256.itm(2)} {ACC1:acc#256.itm(3)} -attr xrf 33105 -attr oid 269 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#251.itm(0)} -attr vt d
+load net {ACC1:acc#251.itm(1)} -attr vt d
+load net {ACC1:acc#251.itm(2)} -attr vt d
+load netBundle {ACC1:acc#251.itm} 3 {ACC1:acc#251.itm(0)} {ACC1:acc#251.itm(1)} {ACC1:acc#251.itm(2)} -attr xrf 33106 -attr oid 270 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:slc#68.itm(0)} -attr vt d
+load net {ACC1:slc#68.itm(1)} -attr vt d
+load net {ACC1:slc#68.itm(2)} -attr vt d
+load netBundle {ACC1:slc#68.itm} 3 {ACC1:slc#68.itm(0)} {ACC1:slc#68.itm(1)} {ACC1:slc#68.itm(2)} -attr xrf 33107 -attr oid 271 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#68.itm}
+load net {ACC1:acc#242.itm(0)} -attr vt d
+load net {ACC1:acc#242.itm(1)} -attr vt d
+load net {ACC1:acc#242.itm(2)} -attr vt d
+load net {ACC1:acc#242.itm(3)} -attr vt d
+load netBundle {ACC1:acc#242.itm} 4 {ACC1:acc#242.itm(0)} {ACC1:acc#242.itm(1)} {ACC1:acc#242.itm(2)} {ACC1:acc#242.itm(3)} -attr xrf 33108 -attr oid 272 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {conc#617.itm(0)} -attr vt d
+load net {conc#617.itm(1)} -attr vt d
+load net {conc#617.itm(2)} -attr vt d
+load netBundle {conc#617.itm} 3 {conc#617.itm(0)} {conc#617.itm(1)} {conc#617.itm(2)} -attr xrf 33109 -attr oid 273 -attr vt d -attr @path {/sobel/sobel:core/conc#617.itm}
+load net {ACC1:conc#582.itm(0)} -attr vt d
+load net {ACC1:conc#582.itm(1)} -attr vt d
+load netBundle {ACC1:conc#582.itm} 2 {ACC1:conc#582.itm(0)} {ACC1:conc#582.itm(1)} -attr xrf 33110 -attr oid 274 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#582.itm}
+load net {slc(ACC1:acc#120.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#120.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#120.psp.sva)#2.itm} 2 {slc(ACC1:acc#120.psp.sva)#2.itm(0)} {slc(ACC1:acc#120.psp.sva)#2.itm(1)} -attr xrf 33111 -attr oid 275 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp.sva)#2.itm}
+load net {ACC1:slc#69.itm(0)} -attr vt d
+load net {ACC1:slc#69.itm(1)} -attr vt d
+load net {ACC1:slc#69.itm(2)} -attr vt d
+load net {ACC1:slc#69.itm(3)} -attr vt d
+load netBundle {ACC1:slc#69.itm} 4 {ACC1:slc#69.itm(0)} {ACC1:slc#69.itm(1)} {ACC1:slc#69.itm(2)} {ACC1:slc#69.itm(3)} -attr xrf 33112 -attr oid 276 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#69.itm}
+load net {ACC1:acc#243.itm(0)} -attr vt d
+load net {ACC1:acc#243.itm(1)} -attr vt d
+load net {ACC1:acc#243.itm(2)} -attr vt d
+load net {ACC1:acc#243.itm(3)} -attr vt d
+load net {ACC1:acc#243.itm(4)} -attr vt d
+load netBundle {ACC1:acc#243.itm} 5 {ACC1:acc#243.itm(0)} {ACC1:acc#243.itm(1)} {ACC1:acc#243.itm(2)} {ACC1:acc#243.itm(3)} {ACC1:acc#243.itm(4)} -attr xrf 33113 -attr oid 277 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {conc#618.itm(0)} -attr vt d
+load net {conc#618.itm(1)} -attr vt d
+load net {conc#618.itm(2)} -attr vt d
+load netBundle {conc#618.itm} 3 {conc#618.itm(0)} {conc#618.itm(1)} {conc#618.itm(2)} -attr xrf 33114 -attr oid 278 -attr vt d -attr @path {/sobel/sobel:core/conc#618.itm}
+load net {ACC1:conc#584.itm(0)} -attr vt d
+load net {ACC1:conc#584.itm(1)} -attr vt d
+load net {ACC1:conc#584.itm(2)} -attr vt d
+load netBundle {ACC1:conc#584.itm} 3 {ACC1:conc#584.itm(0)} {ACC1:conc#584.itm(1)} {ACC1:conc#584.itm(2)} -attr xrf 33115 -attr oid 279 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#584.itm}
+load net {ACC1:acc#255.itm(0)} -attr vt d
+load net {ACC1:acc#255.itm(1)} -attr vt d
+load net {ACC1:acc#255.itm(2)} -attr vt d
+load net {ACC1:acc#255.itm(3)} -attr vt d
+load net {ACC1:acc#255.itm(4)} -attr vt d
+load netBundle {ACC1:acc#255.itm} 5 {ACC1:acc#255.itm(0)} {ACC1:acc#255.itm(1)} {ACC1:acc#255.itm(2)} {ACC1:acc#255.itm(3)} {ACC1:acc#255.itm(4)} -attr xrf 33116 -attr oid 280 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1-3:conc#284.itm(0)} -attr vt d
+load net {ACC1-3:conc#284.itm(1)} -attr vt d
+load net {ACC1-3:conc#284.itm(2)} -attr vt d
+load net {ACC1-3:conc#284.itm(3)} -attr vt d
+load netBundle {ACC1-3:conc#284.itm} 4 {ACC1-3:conc#284.itm(0)} {ACC1-3:conc#284.itm(1)} {ACC1-3:conc#284.itm(2)} {ACC1-3:conc#284.itm(3)} -attr xrf 33117 -attr oid 281 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#284.itm}
+load net {ACC1-3:exs#555.itm(0)} -attr vt d
+load net {ACC1-3:exs#555.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#555.itm} 2 {ACC1-3:exs#555.itm(0)} {ACC1-3:exs#555.itm(1)} -attr xrf 33118 -attr oid 282 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#555.itm}
+load net {conc#619.itm(0)} -attr vt d
+load net {conc#619.itm(1)} -attr vt d
+load net {conc#619.itm(2)} -attr vt d
+load net {conc#619.itm(3)} -attr vt d
+load net {conc#619.itm(4)} -attr vt d
+load net {conc#619.itm(5)} -attr vt d
+load net {conc#619.itm(6)} -attr vt d
+load netBundle {conc#619.itm} 7 {conc#619.itm(0)} {conc#619.itm(1)} {conc#619.itm(2)} {conc#619.itm(3)} {conc#619.itm(4)} {conc#619.itm(5)} {conc#619.itm(6)} -attr xrf 33119 -attr oid 283 -attr vt d -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {ACC1:acc#261.itm(0)} -attr vt d
+load net {ACC1:acc#261.itm(1)} -attr vt d
+load net {ACC1:acc#261.itm(2)} -attr vt d
+load net {ACC1:acc#261.itm(3)} -attr vt d
+load net {ACC1:acc#261.itm(4)} -attr vt d
+load net {ACC1:acc#261.itm(5)} -attr vt d
+load net {ACC1:acc#261.itm(6)} -attr vt d
+load net {ACC1:acc#261.itm(7)} -attr vt d
+load netBundle {ACC1:acc#261.itm} 8 {ACC1:acc#261.itm(0)} {ACC1:acc#261.itm(1)} {ACC1:acc#261.itm(2)} {ACC1:acc#261.itm(3)} {ACC1:acc#261.itm(4)} {ACC1:acc#261.itm(5)} {ACC1:acc#261.itm(6)} {ACC1:acc#261.itm(7)} -attr xrf 33120 -attr oid 284 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1-3:exs#544.itm(0)} -attr vt d
+load net {ACC1-3:exs#544.itm(1)} -attr vt d
+load net {ACC1-3:exs#544.itm(2)} -attr vt d
+load net {ACC1-3:exs#544.itm(3)} -attr vt d
+load net {ACC1-3:exs#544.itm(4)} -attr vt d
+load net {ACC1-3:exs#544.itm(5)} -attr vt d
+load net {ACC1-3:exs#544.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#544.itm} 7 {ACC1-3:exs#544.itm(0)} {ACC1-3:exs#544.itm(1)} {ACC1-3:exs#544.itm(2)} {ACC1-3:exs#544.itm(3)} {ACC1-3:exs#544.itm(4)} {ACC1-3:exs#544.itm(5)} {ACC1-3:exs#544.itm(6)} -attr xrf 33121 -attr oid 285 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {ACC1-3:conc#254.itm(0)} -attr vt d
+load net {ACC1-3:conc#254.itm(1)} -attr vt d
+load net {ACC1-3:conc#254.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#254.itm} 3 {ACC1-3:conc#254.itm(0)} {ACC1-3:conc#254.itm(1)} {ACC1-3:conc#254.itm(2)} -attr xrf 33122 -attr oid 286 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#254.itm}
+load net {ACC1-3:exs#556.itm(0)} -attr vt d
+load net {ACC1-3:exs#556.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#556.itm} 2 {ACC1-3:exs#556.itm(0)} {ACC1-3:exs#556.itm(1)} -attr xrf 33123 -attr oid 287 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#556.itm}
+load net {ACC1:acc#258.itm(0)} -attr vt d
+load net {ACC1:acc#258.itm(1)} -attr vt d
+load net {ACC1:acc#258.itm(2)} -attr vt d
+load net {ACC1:acc#258.itm(3)} -attr vt d
+load net {ACC1:acc#258.itm(4)} -attr vt d
+load net {ACC1:acc#258.itm(5)} -attr vt d
+load netBundle {ACC1:acc#258.itm} 6 {ACC1:acc#258.itm(0)} {ACC1:acc#258.itm(1)} {ACC1:acc#258.itm(2)} {ACC1:acc#258.itm(3)} {ACC1:acc#258.itm(4)} {ACC1:acc#258.itm(5)} -attr xrf 33124 -attr oid 288 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {conc#620.itm(0)} -attr vt d
+load net {conc#620.itm(1)} -attr vt d
+load net {conc#620.itm(2)} -attr vt d
+load net {conc#620.itm(3)} -attr vt d
+load net {conc#620.itm(4)} -attr vt d
+load netBundle {conc#620.itm} 5 {conc#620.itm(0)} {conc#620.itm(1)} {conc#620.itm(2)} {conc#620.itm(3)} {conc#620.itm(4)} -attr xrf 33125 -attr oid 289 -attr vt d -attr @path {/sobel/sobel:core/conc#620.itm}
+load net {ACC1:acc#254.itm(0)} -attr vt d
+load net {ACC1:acc#254.itm(1)} -attr vt d
+load net {ACC1:acc#254.itm(2)} -attr vt d
+load net {ACC1:acc#254.itm(3)} -attr vt d
+load netBundle {ACC1:acc#254.itm} 4 {ACC1:acc#254.itm(0)} {ACC1:acc#254.itm(1)} {ACC1:acc#254.itm(2)} {ACC1:acc#254.itm(3)} -attr xrf 33126 -attr oid 290 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:slc#74.itm(0)} -attr vt d
+load net {ACC1:slc#74.itm(1)} -attr vt d
+load net {ACC1:slc#74.itm(2)} -attr vt d
+load netBundle {ACC1:slc#74.itm} 3 {ACC1:slc#74.itm(0)} {ACC1:slc#74.itm(1)} {ACC1:slc#74.itm(2)} -attr xrf 33127 -attr oid 291 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:acc#248.itm(0)} -attr vt d
+load net {ACC1:acc#248.itm(1)} -attr vt d
+load net {ACC1:acc#248.itm(2)} -attr vt d
+load net {ACC1:acc#248.itm(3)} -attr vt d
+load netBundle {ACC1:acc#248.itm} 4 {ACC1:acc#248.itm(0)} {ACC1:acc#248.itm(1)} {ACC1:acc#248.itm(2)} {ACC1:acc#248.itm(3)} -attr xrf 33128 -attr oid 292 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {exs#58.itm(0)} -attr vt d
+load net {exs#58.itm(1)} -attr vt d
+load net {exs#58.itm(2)} -attr vt d
+load netBundle {exs#58.itm} 3 {exs#58.itm(0)} {exs#58.itm(1)} {exs#58.itm(2)} -attr xrf 33129 -attr oid 293 -attr vt d -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {conc#621.itm(0)} -attr vt d
+load net {conc#621.itm(1)} -attr vt d
+load netBundle {conc#621.itm} 2 {conc#621.itm(0)} {conc#621.itm(1)} -attr xrf 33130 -attr oid 294 -attr vt d -attr @path {/sobel/sobel:core/conc#621.itm}
+load net {ACC1:exs#772.itm(0)} -attr vt d
+load net {ACC1:exs#772.itm(1)} -attr vt d
+load net {ACC1:exs#772.itm(2)} -attr vt d
+load netBundle {ACC1:exs#772.itm} 3 {ACC1:exs#772.itm(0)} {ACC1:exs#772.itm(1)} {ACC1:exs#772.itm(2)} -attr xrf 33131 -attr oid 295 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#772.itm}
+load net {ACC1:conc#594.itm(0)} -attr vt d
+load net {ACC1:conc#594.itm(1)} -attr vt d
+load netBundle {ACC1:conc#594.itm} 2 {ACC1:conc#594.itm(0)} {ACC1:conc#594.itm(1)} -attr xrf 33132 -attr oid 296 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#594.itm}
+load net {conc#623.itm(0)} -attr vt d
+load net {conc#623.itm(1)} -attr vt d
+load net {conc#623.itm(2)} -attr vt d
+load net {conc#623.itm(3)} -attr vt d
+load net {conc#623.itm(4)} -attr vt d
+load net {conc#623.itm(5)} -attr vt d
+load net {conc#623.itm(6)} -attr vt d
+load net {conc#623.itm(7)} -attr vt d
+load net {conc#623.itm(8)} -attr vt d
+load net {conc#623.itm(9)} -attr vt d
+load netBundle {conc#623.itm} 10 {conc#623.itm(0)} {conc#623.itm(1)} {conc#623.itm(2)} {conc#623.itm(3)} {conc#623.itm(4)} {conc#623.itm(5)} {conc#623.itm(6)} {conc#623.itm(7)} {conc#623.itm(8)} {conc#623.itm(9)} -attr xrf 33133 -attr oid 297 -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {ACC1-3:exs#572.itm(0)} -attr vt d
+load net {ACC1-3:exs#572.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#572.itm} 2 {ACC1-3:exs#572.itm(0)} {ACC1-3:exs#572.itm(1)} -attr xrf 33134 -attr oid 298 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#572.itm}
+load net {ACC1:acc#267.itm(0)} -attr vt d
+load net {ACC1:acc#267.itm(1)} -attr vt d
+load net {ACC1:acc#267.itm(2)} -attr vt d
+load net {ACC1:acc#267.itm(3)} -attr vt d
+load net {ACC1:acc#267.itm(4)} -attr vt d
+load net {ACC1:acc#267.itm(5)} -attr vt d
+load net {ACC1:acc#267.itm(6)} -attr vt d
+load net {ACC1:acc#267.itm(7)} -attr vt d
+load net {ACC1:acc#267.itm(8)} -attr vt d
+load net {ACC1:acc#267.itm(9)} -attr vt d
+load net {ACC1:acc#267.itm(10)} -attr vt d
+load net {ACC1:acc#267.itm(11)} -attr vt d
+load netBundle {ACC1:acc#267.itm} 12 {ACC1:acc#267.itm(0)} {ACC1:acc#267.itm(1)} {ACC1:acc#267.itm(2)} {ACC1:acc#267.itm(3)} {ACC1:acc#267.itm(4)} {ACC1:acc#267.itm(5)} {ACC1:acc#267.itm(6)} {ACC1:acc#267.itm(7)} {ACC1:acc#267.itm(8)} {ACC1:acc#267.itm(9)} {ACC1:acc#267.itm(10)} {ACC1:acc#267.itm(11)} -attr xrf 33135 -attr oid 299 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1-1:acc#124.itm(0)} -attr vt d
+load net {ACC1-1:acc#124.itm(1)} -attr vt d
+load net {ACC1-1:acc#124.itm(2)} -attr vt d
+load net {ACC1-1:acc#124.itm(3)} -attr vt d
+load net {ACC1-1:acc#124.itm(4)} -attr vt d
+load net {ACC1-1:acc#124.itm(5)} -attr vt d
+load net {ACC1-1:acc#124.itm(6)} -attr vt d
+load net {ACC1-1:acc#124.itm(7)} -attr vt d
+load net {ACC1-1:acc#124.itm(8)} -attr vt d
+load net {ACC1-1:acc#124.itm(9)} -attr vt d
+load net {ACC1-1:acc#124.itm(10)} -attr vt d
+load netBundle {ACC1-1:acc#124.itm} 11 {ACC1-1:acc#124.itm(0)} {ACC1-1:acc#124.itm(1)} {ACC1-1:acc#124.itm(2)} {ACC1-1:acc#124.itm(3)} {ACC1-1:acc#124.itm(4)} {ACC1-1:acc#124.itm(5)} {ACC1-1:acc#124.itm(6)} {ACC1-1:acc#124.itm(7)} {ACC1-1:acc#124.itm(8)} {ACC1-1:acc#124.itm(9)} {ACC1-1:acc#124.itm(10)} -attr xrf 33136 -attr oid 300 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1:acc#294.itm(0)} -attr vt d
+load net {ACC1:acc#294.itm(1)} -attr vt d
+load net {ACC1:acc#294.itm(2)} -attr vt d
+load net {ACC1:acc#294.itm(3)} -attr vt d
+load net {ACC1:acc#294.itm(4)} -attr vt d
+load net {ACC1:acc#294.itm(5)} -attr vt d
+load net {ACC1:acc#294.itm(6)} -attr vt d
+load net {ACC1:acc#294.itm(7)} -attr vt d
+load net {ACC1:acc#294.itm(8)} -attr vt d
+load net {ACC1:acc#294.itm(9)} -attr vt d
+load net {ACC1:acc#294.itm(10)} -attr vt d
+load netBundle {ACC1:acc#294.itm} 11 {ACC1:acc#294.itm(0)} {ACC1:acc#294.itm(1)} {ACC1:acc#294.itm(2)} {ACC1:acc#294.itm(3)} {ACC1:acc#294.itm(4)} {ACC1:acc#294.itm(5)} {ACC1:acc#294.itm(6)} {ACC1:acc#294.itm(7)} {ACC1:acc#294.itm(8)} {ACC1:acc#294.itm(9)} {ACC1:acc#294.itm(10)} -attr xrf 33137 -attr oid 301 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#292.itm(0)} -attr vt d
+load net {ACC1:acc#292.itm(1)} -attr vt d
+load net {ACC1:acc#292.itm(2)} -attr vt d
+load net {ACC1:acc#292.itm(3)} -attr vt d
+load net {ACC1:acc#292.itm(4)} -attr vt d
+load net {ACC1:acc#292.itm(5)} -attr vt d
+load net {ACC1:acc#292.itm(6)} -attr vt d
+load net {ACC1:acc#292.itm(7)} -attr vt d
+load net {ACC1:acc#292.itm(8)} -attr vt d
+load net {ACC1:acc#292.itm(9)} -attr vt d
+load netBundle {ACC1:acc#292.itm} 10 {ACC1:acc#292.itm(0)} {ACC1:acc#292.itm(1)} {ACC1:acc#292.itm(2)} {ACC1:acc#292.itm(3)} {ACC1:acc#292.itm(4)} {ACC1:acc#292.itm(5)} {ACC1:acc#292.itm(6)} {ACC1:acc#292.itm(7)} {ACC1:acc#292.itm(8)} {ACC1:acc#292.itm(9)} -attr xrf 33138 -attr oid 302 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {conc#624.itm(0)} -attr vt d
+load net {conc#624.itm(1)} -attr vt d
+load net {conc#624.itm(2)} -attr vt d
+load net {conc#624.itm(3)} -attr vt d
+load net {conc#624.itm(4)} -attr vt d
+load net {conc#624.itm(5)} -attr vt d
+load net {conc#624.itm(6)} -attr vt d
+load net {conc#624.itm(7)} -attr vt d
+load net {conc#624.itm(8)} -attr vt d
+load netBundle {conc#624.itm} 9 {conc#624.itm(0)} {conc#624.itm(1)} {conc#624.itm(2)} {conc#624.itm(3)} {conc#624.itm(4)} {conc#624.itm(5)} {conc#624.itm(6)} {conc#624.itm(7)} {conc#624.itm(8)} -attr xrf 33139 -attr oid 303 -attr vt d -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {ACC1:acc#290.itm(0)} -attr vt d
+load net {ACC1:acc#290.itm(1)} -attr vt d
+load net {ACC1:acc#290.itm(2)} -attr vt d
+load net {ACC1:acc#290.itm(3)} -attr vt d
+load net {ACC1:acc#290.itm(4)} -attr vt d
+load net {ACC1:acc#290.itm(5)} -attr vt d
+load net {ACC1:acc#290.itm(6)} -attr vt d
+load net {ACC1:acc#290.itm(7)} -attr vt d
+load netBundle {ACC1:acc#290.itm} 8 {ACC1:acc#290.itm(0)} {ACC1:acc#290.itm(1)} {ACC1:acc#290.itm(2)} {ACC1:acc#290.itm(3)} {ACC1:acc#290.itm(4)} {ACC1:acc#290.itm(5)} {ACC1:acc#290.itm(6)} {ACC1:acc#290.itm(7)} -attr xrf 33140 -attr oid 304 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {conc#625.itm(0)} -attr vt d
+load net {conc#625.itm(1)} -attr vt d
+load net {conc#625.itm(2)} -attr vt d
+load net {conc#625.itm(3)} -attr vt d
+load net {conc#625.itm(4)} -attr vt d
+load net {conc#625.itm(5)} -attr vt d
+load net {conc#625.itm(6)} -attr vt d
+load net {conc#625.itm(7)} -attr vt d
+load netBundle {conc#625.itm} 8 {conc#625.itm(0)} {conc#625.itm(1)} {conc#625.itm(2)} {conc#625.itm(3)} {conc#625.itm(4)} {conc#625.itm(5)} {conc#625.itm(6)} {conc#625.itm(7)} -attr xrf 33141 -attr oid 305 -attr vt d -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {ACC1-1:exs#553.itm(0)} -attr vt d
+load net {ACC1-1:exs#553.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#553.itm} 2 {ACC1-1:exs#553.itm(0)} {ACC1-1:exs#553.itm(1)} -attr xrf 33142 -attr oid 306 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#553.itm}
+load net {ACC1:acc#287.itm(0)} -attr vt d
+load net {ACC1:acc#287.itm(1)} -attr vt d
+load net {ACC1:acc#287.itm(2)} -attr vt d
+load net {ACC1:acc#287.itm(3)} -attr vt d
+load net {ACC1:acc#287.itm(4)} -attr vt d
+load net {ACC1:acc#287.itm(5)} -attr vt d
+load net {ACC1:acc#287.itm(6)} -attr vt d
+load netBundle {ACC1:acc#287.itm} 7 {ACC1:acc#287.itm(0)} {ACC1:acc#287.itm(1)} {ACC1:acc#287.itm(2)} {ACC1:acc#287.itm(3)} {ACC1:acc#287.itm(4)} {ACC1:acc#287.itm(5)} {ACC1:acc#287.itm(6)} -attr xrf 33143 -attr oid 307 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {conc#626.itm(0)} -attr vt d
+load net {conc#626.itm(1)} -attr vt d
+load net {conc#626.itm(2)} -attr vt d
+load net {conc#626.itm(3)} -attr vt d
+load net {conc#626.itm(4)} -attr vt d
+load net {conc#626.itm(5)} -attr vt d
+load netBundle {conc#626.itm} 6 {conc#626.itm(0)} {conc#626.itm(1)} {conc#626.itm(2)} {conc#626.itm(3)} {conc#626.itm(4)} {conc#626.itm(5)} -attr xrf 33144 -attr oid 308 -attr vt d -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {ACC1-1:exs#556.itm(0)} -attr vt d
+load net {ACC1-1:exs#556.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#556.itm} 2 {ACC1-1:exs#556.itm(0)} {ACC1-1:exs#556.itm(1)} -attr xrf 33145 -attr oid 309 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#556.itm}
+load net {ACC1:acc#284.itm(0)} -attr vt d
+load net {ACC1:acc#284.itm(1)} -attr vt d
+load net {ACC1:acc#284.itm(2)} -attr vt d
+load net {ACC1:acc#284.itm(3)} -attr vt d
+load net {ACC1:acc#284.itm(4)} -attr vt d
+load netBundle {ACC1:acc#284.itm} 5 {ACC1:acc#284.itm(0)} {ACC1:acc#284.itm(1)} {ACC1:acc#284.itm(2)} {ACC1:acc#284.itm(3)} {ACC1:acc#284.itm(4)} -attr xrf 33146 -attr oid 310 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#280.itm(0)} -attr vt d
+load net {ACC1:acc#280.itm(1)} -attr vt d
+load net {ACC1:acc#280.itm(2)} -attr vt d
+load net {ACC1:acc#280.itm(3)} -attr vt d
+load netBundle {ACC1:acc#280.itm} 4 {ACC1:acc#280.itm(0)} {ACC1:acc#280.itm(1)} {ACC1:acc#280.itm(2)} {ACC1:acc#280.itm(3)} -attr xrf 33147 -attr oid 311 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:slc#80.itm(0)} -attr vt d
+load net {ACC1:slc#80.itm(1)} -attr vt d
+load net {ACC1:slc#80.itm(2)} -attr vt d
+load netBundle {ACC1:slc#80.itm} 3 {ACC1:slc#80.itm(0)} {ACC1:slc#80.itm(1)} {ACC1:slc#80.itm(2)} -attr xrf 33148 -attr oid 312 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#80.itm}
+load net {ACC1:acc#274.itm(0)} -attr vt d
+load net {ACC1:acc#274.itm(1)} -attr vt d
+load net {ACC1:acc#274.itm(2)} -attr vt d
+load net {ACC1:acc#274.itm(3)} -attr vt d
+load netBundle {ACC1:acc#274.itm} 4 {ACC1:acc#274.itm(0)} {ACC1:acc#274.itm(1)} {ACC1:acc#274.itm(2)} {ACC1:acc#274.itm(3)} -attr xrf 33149 -attr oid 313 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {exs#38.itm(0)} -attr vt d
+load net {exs#38.itm(1)} -attr vt d
+load net {exs#38.itm(2)} -attr vt d
+load netBundle {exs#38.itm} 3 {exs#38.itm(0)} {exs#38.itm(1)} {exs#38.itm(2)} -attr xrf 33150 -attr oid 314 -attr vt d -attr @path {/sobel/sobel:core/exs#38.itm}
+load net {conc#627.itm(0)} -attr vt d
+load net {conc#627.itm(1)} -attr vt d
+load netBundle {conc#627.itm} 2 {conc#627.itm(0)} {conc#627.itm(1)} -attr xrf 33151 -attr oid 315 -attr vt d -attr @path {/sobel/sobel:core/conc#627.itm}
+load net {ACC1:exs#774.itm(0)} -attr vt d
+load net {ACC1:exs#774.itm(1)} -attr vt d
+load net {ACC1:exs#774.itm(2)} -attr vt d
+load netBundle {ACC1:exs#774.itm} 3 {ACC1:exs#774.itm(0)} {ACC1:exs#774.itm(1)} {ACC1:exs#774.itm(2)} -attr xrf 33152 -attr oid 316 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#774.itm}
+load net {ACC1:conc#607.itm(0)} -attr vt d
+load net {ACC1:conc#607.itm(1)} -attr vt d
+load netBundle {ACC1:conc#607.itm} 2 {ACC1:conc#607.itm(0)} {ACC1:conc#607.itm(1)} -attr xrf 33153 -attr oid 317 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#607.itm}
+load net {ACC1:slc#79.itm(0)} -attr vt d
+load net {ACC1:slc#79.itm(1)} -attr vt d
+load net {ACC1:slc#79.itm(2)} -attr vt d
+load netBundle {ACC1:slc#79.itm} 3 {ACC1:slc#79.itm(0)} {ACC1:slc#79.itm(1)} {ACC1:slc#79.itm(2)} -attr xrf 33154 -attr oid 318 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#79.itm}
+load net {ACC1:acc#273.itm(0)} -attr vt d
+load net {ACC1:acc#273.itm(1)} -attr vt d
+load net {ACC1:acc#273.itm(2)} -attr vt d
+load net {ACC1:acc#273.itm(3)} -attr vt d
+load netBundle {ACC1:acc#273.itm} 4 {ACC1:acc#273.itm(0)} {ACC1:acc#273.itm(1)} {ACC1:acc#273.itm(2)} {ACC1:acc#273.itm(3)} -attr xrf 33155 -attr oid 319 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {exs#39.itm(0)} -attr vt d
+load net {exs#39.itm(1)} -attr vt d
+load net {exs#39.itm(2)} -attr vt d
+load netBundle {exs#39.itm} 3 {exs#39.itm(0)} {exs#39.itm(1)} {exs#39.itm(2)} -attr xrf 33156 -attr oid 320 -attr vt d -attr @path {/sobel/sobel:core/exs#39.itm}
+load net {conc#628.itm(0)} -attr vt d
+load net {conc#628.itm(1)} -attr vt d
+load netBundle {conc#628.itm} 2 {conc#628.itm(0)} {conc#628.itm(1)} -attr xrf 33157 -attr oid 321 -attr vt d -attr @path {/sobel/sobel:core/conc#628.itm}
+load net {ACC1:exs#776.itm(0)} -attr vt d
+load net {ACC1:exs#776.itm(1)} -attr vt d
+load net {ACC1:exs#776.itm(2)} -attr vt d
+load netBundle {ACC1:exs#776.itm} 3 {ACC1:exs#776.itm(0)} {ACC1:exs#776.itm(1)} {ACC1:exs#776.itm(2)} -attr xrf 33158 -attr oid 322 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#776.itm}
+load net {ACC1:conc#605.itm(0)} -attr vt d
+load net {ACC1:conc#605.itm(1)} -attr vt d
+load netBundle {ACC1:conc#605.itm} 2 {ACC1:conc#605.itm(0)} {ACC1:conc#605.itm(1)} -attr xrf 33159 -attr oid 323 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#605.itm}
+load net {ACC1:acc#279.itm(0)} -attr vt d
+load net {ACC1:acc#279.itm(1)} -attr vt d
+load net {ACC1:acc#279.itm(2)} -attr vt d
+load net {ACC1:acc#279.itm(3)} -attr vt d
+load netBundle {ACC1:acc#279.itm} 4 {ACC1:acc#279.itm(0)} {ACC1:acc#279.itm(1)} {ACC1:acc#279.itm(2)} {ACC1:acc#279.itm(3)} -attr xrf 33160 -attr oid 324 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:slc#78.itm(0)} -attr vt d
+load net {ACC1:slc#78.itm(1)} -attr vt d
+load net {ACC1:slc#78.itm(2)} -attr vt d
+load netBundle {ACC1:slc#78.itm} 3 {ACC1:slc#78.itm(0)} {ACC1:slc#78.itm(1)} {ACC1:slc#78.itm(2)} -attr xrf 33161 -attr oid 325 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#78.itm}
+load net {ACC1:acc#272.itm(0)} -attr vt d
+load net {ACC1:acc#272.itm(1)} -attr vt d
+load net {ACC1:acc#272.itm(2)} -attr vt d
+load net {ACC1:acc#272.itm(3)} -attr vt d
+load netBundle {ACC1:acc#272.itm} 4 {ACC1:acc#272.itm(0)} {ACC1:acc#272.itm(1)} {ACC1:acc#272.itm(2)} {ACC1:acc#272.itm(3)} -attr xrf 33162 -attr oid 326 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {exs#40.itm(0)} -attr vt d
+load net {exs#40.itm(1)} -attr vt d
+load net {exs#40.itm(2)} -attr vt d
+load netBundle {exs#40.itm} 3 {exs#40.itm(0)} {exs#40.itm(1)} {exs#40.itm(2)} -attr xrf 33163 -attr oid 327 -attr vt d -attr @path {/sobel/sobel:core/exs#40.itm}
+load net {conc#629.itm(0)} -attr vt d
+load net {conc#629.itm(1)} -attr vt d
+load netBundle {conc#629.itm} 2 {conc#629.itm(0)} {conc#629.itm(1)} -attr xrf 33164 -attr oid 328 -attr vt d -attr @path {/sobel/sobel:core/conc#629.itm}
+load net {ACC1:exs#778.itm(0)} -attr vt d
+load net {ACC1:exs#778.itm(1)} -attr vt d
+load net {ACC1:exs#778.itm(2)} -attr vt d
+load netBundle {ACC1:exs#778.itm} 3 {ACC1:exs#778.itm(0)} {ACC1:exs#778.itm(1)} {ACC1:exs#778.itm(2)} -attr xrf 33165 -attr oid 329 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#778.itm}
+load net {ACC1:conc#603.itm(0)} -attr vt d
+load net {ACC1:conc#603.itm(1)} -attr vt d
+load netBundle {ACC1:conc#603.itm} 2 {ACC1:conc#603.itm(0)} {ACC1:conc#603.itm(1)} -attr xrf 33166 -attr oid 330 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#603.itm}
+load net {ACC1:slc#77.itm(0)} -attr vt d
+load net {ACC1:slc#77.itm(1)} -attr vt d
+load net {ACC1:slc#77.itm(2)} -attr vt d
+load netBundle {ACC1:slc#77.itm} 3 {ACC1:slc#77.itm(0)} {ACC1:slc#77.itm(1)} {ACC1:slc#77.itm(2)} -attr xrf 33167 -attr oid 331 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#77.itm}
+load net {ACC1:acc#271.itm(0)} -attr vt d
+load net {ACC1:acc#271.itm(1)} -attr vt d
+load net {ACC1:acc#271.itm(2)} -attr vt d
+load net {ACC1:acc#271.itm(3)} -attr vt d
+load netBundle {ACC1:acc#271.itm} 4 {ACC1:acc#271.itm(0)} {ACC1:acc#271.itm(1)} {ACC1:acc#271.itm(2)} {ACC1:acc#271.itm(3)} -attr xrf 33168 -attr oid 332 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {exs#41.itm(0)} -attr vt d
+load net {exs#41.itm(1)} -attr vt d
+load net {exs#41.itm(2)} -attr vt d
+load netBundle {exs#41.itm} 3 {exs#41.itm(0)} {exs#41.itm(1)} {exs#41.itm(2)} -attr xrf 33169 -attr oid 333 -attr vt d -attr @path {/sobel/sobel:core/exs#41.itm}
+load net {conc#630.itm(0)} -attr vt d
+load net {conc#630.itm(1)} -attr vt d
+load netBundle {conc#630.itm} 2 {conc#630.itm(0)} {conc#630.itm(1)} -attr xrf 33170 -attr oid 334 -attr vt d -attr @path {/sobel/sobel:core/conc#630.itm}
+load net {ACC1:exs#780.itm(0)} -attr vt d
+load net {ACC1:exs#780.itm(1)} -attr vt d
+load net {ACC1:exs#780.itm(2)} -attr vt d
+load netBundle {ACC1:exs#780.itm} 3 {ACC1:exs#780.itm(0)} {ACC1:exs#780.itm(1)} {ACC1:exs#780.itm(2)} -attr xrf 33171 -attr oid 335 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#780.itm}
+load net {ACC1:conc#601.itm(0)} -attr vt d
+load net {ACC1:conc#601.itm(1)} -attr vt d
+load netBundle {ACC1:conc#601.itm} 2 {ACC1:conc#601.itm(0)} {ACC1:conc#601.itm(1)} -attr xrf 33172 -attr oid 336 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#601.itm}
+load net {ACC1:acc#291.itm(0)} -attr vt d
+load net {ACC1:acc#291.itm(1)} -attr vt d
+load net {ACC1:acc#291.itm(2)} -attr vt d
+load net {ACC1:acc#291.itm(3)} -attr vt d
+load net {ACC1:acc#291.itm(4)} -attr vt d
+load net {ACC1:acc#291.itm(5)} -attr vt d
+load net {ACC1:acc#291.itm(6)} -attr vt d
+load net {ACC1:acc#291.itm(7)} -attr vt d
+load net {ACC1:acc#291.itm(8)} -attr vt d
+load net {ACC1:acc#291.itm(9)} -attr vt d
+load netBundle {ACC1:acc#291.itm} 10 {ACC1:acc#291.itm(0)} {ACC1:acc#291.itm(1)} {ACC1:acc#291.itm(2)} {ACC1:acc#291.itm(3)} {ACC1:acc#291.itm(4)} {ACC1:acc#291.itm(5)} {ACC1:acc#291.itm(6)} {ACC1:acc#291.itm(7)} {ACC1:acc#291.itm(8)} {ACC1:acc#291.itm(9)} -attr xrf 33173 -attr oid 337 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#289.itm(0)} -attr vt d
+load net {ACC1:acc#289.itm(1)} -attr vt d
+load net {ACC1:acc#289.itm(2)} -attr vt d
+load net {ACC1:acc#289.itm(3)} -attr vt d
+load net {ACC1:acc#289.itm(4)} -attr vt d
+load net {ACC1:acc#289.itm(5)} -attr vt d
+load net {ACC1:acc#289.itm(6)} -attr vt d
+load net {ACC1:acc#289.itm(7)} -attr vt d
+load netBundle {ACC1:acc#289.itm} 8 {ACC1:acc#289.itm(0)} {ACC1:acc#289.itm(1)} {ACC1:acc#289.itm(2)} {ACC1:acc#289.itm(3)} {ACC1:acc#289.itm(4)} {ACC1:acc#289.itm(5)} {ACC1:acc#289.itm(6)} {ACC1:acc#289.itm(7)} -attr xrf 33174 -attr oid 338 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#286.itm(0)} -attr vt d
+load net {ACC1:acc#286.itm(1)} -attr vt d
+load net {ACC1:acc#286.itm(2)} -attr vt d
+load net {ACC1:acc#286.itm(3)} -attr vt d
+load net {ACC1:acc#286.itm(4)} -attr vt d
+load net {ACC1:acc#286.itm(5)} -attr vt d
+load netBundle {ACC1:acc#286.itm} 6 {ACC1:acc#286.itm(0)} {ACC1:acc#286.itm(1)} {ACC1:acc#286.itm(2)} {ACC1:acc#286.itm(3)} {ACC1:acc#286.itm(4)} {ACC1:acc#286.itm(5)} -attr xrf 33175 -attr oid 339 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#283.itm(0)} -attr vt d
+load net {ACC1:acc#283.itm(1)} -attr vt d
+load net {ACC1:acc#283.itm(2)} -attr vt d
+load net {ACC1:acc#283.itm(3)} -attr vt d
+load netBundle {ACC1:acc#283.itm} 4 {ACC1:acc#283.itm(0)} {ACC1:acc#283.itm(1)} {ACC1:acc#283.itm(2)} {ACC1:acc#283.itm(3)} -attr xrf 33176 -attr oid 340 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#278.itm(0)} -attr vt d
+load net {ACC1:acc#278.itm(1)} -attr vt d
+load net {ACC1:acc#278.itm(2)} -attr vt d
+load netBundle {ACC1:acc#278.itm} 3 {ACC1:acc#278.itm(0)} {ACC1:acc#278.itm(1)} {ACC1:acc#278.itm(2)} -attr xrf 33177 -attr oid 341 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:slc#75.itm(0)} -attr vt d
+load net {ACC1:slc#75.itm(1)} -attr vt d
+load net {ACC1:slc#75.itm(2)} -attr vt d
+load netBundle {ACC1:slc#75.itm} 3 {ACC1:slc#75.itm(0)} {ACC1:slc#75.itm(1)} {ACC1:slc#75.itm(2)} -attr xrf 33178 -attr oid 342 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#75.itm}
+load net {ACC1:acc#269.itm(0)} -attr vt d
+load net {ACC1:acc#269.itm(1)} -attr vt d
+load net {ACC1:acc#269.itm(2)} -attr vt d
+load net {ACC1:acc#269.itm(3)} -attr vt d
+load netBundle {ACC1:acc#269.itm} 4 {ACC1:acc#269.itm(0)} {ACC1:acc#269.itm(1)} {ACC1:acc#269.itm(2)} {ACC1:acc#269.itm(3)} -attr xrf 33179 -attr oid 343 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {conc#631.itm(0)} -attr vt d
+load net {conc#631.itm(1)} -attr vt d
+load net {conc#631.itm(2)} -attr vt d
+load netBundle {conc#631.itm} 3 {conc#631.itm(0)} {conc#631.itm(1)} {conc#631.itm(2)} -attr xrf 33180 -attr oid 344 -attr vt d -attr @path {/sobel/sobel:core/conc#631.itm}
+load net {ACC1:conc#597.itm(0)} -attr vt d
+load net {ACC1:conc#597.itm(1)} -attr vt d
+load netBundle {ACC1:conc#597.itm} 2 {ACC1:conc#597.itm(0)} {ACC1:conc#597.itm(1)} -attr xrf 33181 -attr oid 345 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#597.itm}
+load net {slc(ACC1:acc#120.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#120.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#120.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#120.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#120.psp#1.sva)#2.itm(1)} -attr xrf 33182 -attr oid 346 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp#1.sva)#2.itm}
+load net {ACC1:slc#76.itm(0)} -attr vt d
+load net {ACC1:slc#76.itm(1)} -attr vt d
+load net {ACC1:slc#76.itm(2)} -attr vt d
+load net {ACC1:slc#76.itm(3)} -attr vt d
+load netBundle {ACC1:slc#76.itm} 4 {ACC1:slc#76.itm(0)} {ACC1:slc#76.itm(1)} {ACC1:slc#76.itm(2)} {ACC1:slc#76.itm(3)} -attr xrf 33183 -attr oid 347 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#76.itm}
+load net {ACC1:acc#270.itm(0)} -attr vt d
+load net {ACC1:acc#270.itm(1)} -attr vt d
+load net {ACC1:acc#270.itm(2)} -attr vt d
+load net {ACC1:acc#270.itm(3)} -attr vt d
+load net {ACC1:acc#270.itm(4)} -attr vt d
+load netBundle {ACC1:acc#270.itm} 5 {ACC1:acc#270.itm(0)} {ACC1:acc#270.itm(1)} {ACC1:acc#270.itm(2)} {ACC1:acc#270.itm(3)} {ACC1:acc#270.itm(4)} -attr xrf 33184 -attr oid 348 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {conc#632.itm(0)} -attr vt d
+load net {conc#632.itm(1)} -attr vt d
+load net {conc#632.itm(2)} -attr vt d
+load netBundle {conc#632.itm} 3 {conc#632.itm(0)} {conc#632.itm(1)} {conc#632.itm(2)} -attr xrf 33185 -attr oid 349 -attr vt d -attr @path {/sobel/sobel:core/conc#632.itm}
+load net {ACC1:conc#599.itm(0)} -attr vt d
+load net {ACC1:conc#599.itm(1)} -attr vt d
+load net {ACC1:conc#599.itm(2)} -attr vt d
+load netBundle {ACC1:conc#599.itm} 3 {ACC1:conc#599.itm(0)} {ACC1:conc#599.itm(1)} {ACC1:conc#599.itm(2)} -attr xrf 33186 -attr oid 350 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#599.itm}
+load net {ACC1:acc#282.itm(0)} -attr vt d
+load net {ACC1:acc#282.itm(1)} -attr vt d
+load net {ACC1:acc#282.itm(2)} -attr vt d
+load net {ACC1:acc#282.itm(3)} -attr vt d
+load net {ACC1:acc#282.itm(4)} -attr vt d
+load netBundle {ACC1:acc#282.itm} 5 {ACC1:acc#282.itm(0)} {ACC1:acc#282.itm(1)} {ACC1:acc#282.itm(2)} {ACC1:acc#282.itm(3)} {ACC1:acc#282.itm(4)} -attr xrf 33187 -attr oid 351 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1-1:conc#284.itm(0)} -attr vt d
+load net {ACC1-1:conc#284.itm(1)} -attr vt d
+load net {ACC1-1:conc#284.itm(2)} -attr vt d
+load net {ACC1-1:conc#284.itm(3)} -attr vt d
+load netBundle {ACC1-1:conc#284.itm} 4 {ACC1-1:conc#284.itm(0)} {ACC1-1:conc#284.itm(1)} {ACC1-1:conc#284.itm(2)} {ACC1-1:conc#284.itm(3)} -attr xrf 33188 -attr oid 352 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#284.itm}
+load net {ACC1-1:exs#550.itm(0)} -attr vt d
+load net {ACC1-1:exs#550.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#550.itm} 2 {ACC1-1:exs#550.itm(0)} {ACC1-1:exs#550.itm(1)} -attr xrf 33189 -attr oid 353 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#550.itm}
+load net {conc#633.itm(0)} -attr vt d
+load net {conc#633.itm(1)} -attr vt d
+load net {conc#633.itm(2)} -attr vt d
+load net {conc#633.itm(3)} -attr vt d
+load net {conc#633.itm(4)} -attr vt d
+load net {conc#633.itm(5)} -attr vt d
+load net {conc#633.itm(6)} -attr vt d
+load netBundle {conc#633.itm} 7 {conc#633.itm(0)} {conc#633.itm(1)} {conc#633.itm(2)} {conc#633.itm(3)} {conc#633.itm(4)} {conc#633.itm(5)} {conc#633.itm(6)} -attr xrf 33190 -attr oid 354 -attr vt d -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {ACC1:acc#288.itm(0)} -attr vt d
+load net {ACC1:acc#288.itm(1)} -attr vt d
+load net {ACC1:acc#288.itm(2)} -attr vt d
+load net {ACC1:acc#288.itm(3)} -attr vt d
+load net {ACC1:acc#288.itm(4)} -attr vt d
+load net {ACC1:acc#288.itm(5)} -attr vt d
+load net {ACC1:acc#288.itm(6)} -attr vt d
+load net {ACC1:acc#288.itm(7)} -attr vt d
+load netBundle {ACC1:acc#288.itm} 8 {ACC1:acc#288.itm(0)} {ACC1:acc#288.itm(1)} {ACC1:acc#288.itm(2)} {ACC1:acc#288.itm(3)} {ACC1:acc#288.itm(4)} {ACC1:acc#288.itm(5)} {ACC1:acc#288.itm(6)} {ACC1:acc#288.itm(7)} -attr xrf 33191 -attr oid 355 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1-1:exs#544.itm(0)} -attr vt d
+load net {ACC1-1:exs#544.itm(1)} -attr vt d
+load net {ACC1-1:exs#544.itm(2)} -attr vt d
+load net {ACC1-1:exs#544.itm(3)} -attr vt d
+load net {ACC1-1:exs#544.itm(4)} -attr vt d
+load net {ACC1-1:exs#544.itm(5)} -attr vt d
+load net {ACC1-1:exs#544.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#544.itm} 7 {ACC1-1:exs#544.itm(0)} {ACC1-1:exs#544.itm(1)} {ACC1-1:exs#544.itm(2)} {ACC1-1:exs#544.itm(3)} {ACC1-1:exs#544.itm(4)} {ACC1-1:exs#544.itm(5)} {ACC1-1:exs#544.itm(6)} -attr xrf 33192 -attr oid 356 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {ACC1-1:conc#254.itm(0)} -attr vt d
+load net {ACC1-1:conc#254.itm(1)} -attr vt d
+load net {ACC1-1:conc#254.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#254.itm} 3 {ACC1-1:conc#254.itm(0)} {ACC1-1:conc#254.itm(1)} {ACC1-1:conc#254.itm(2)} -attr xrf 33193 -attr oid 357 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#254.itm}
+load net {ACC1-1:exs#545.itm(0)} -attr vt d
+load net {ACC1-1:exs#545.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#545.itm} 2 {ACC1-1:exs#545.itm(0)} {ACC1-1:exs#545.itm(1)} -attr xrf 33194 -attr oid 358 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#545.itm}
+load net {ACC1:acc#285.itm(0)} -attr vt d
+load net {ACC1:acc#285.itm(1)} -attr vt d
+load net {ACC1:acc#285.itm(2)} -attr vt d
+load net {ACC1:acc#285.itm(3)} -attr vt d
+load net {ACC1:acc#285.itm(4)} -attr vt d
+load net {ACC1:acc#285.itm(5)} -attr vt d
+load netBundle {ACC1:acc#285.itm} 6 {ACC1:acc#285.itm(0)} {ACC1:acc#285.itm(1)} {ACC1:acc#285.itm(2)} {ACC1:acc#285.itm(3)} {ACC1:acc#285.itm(4)} {ACC1:acc#285.itm(5)} -attr xrf 33195 -attr oid 359 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {conc#634.itm(0)} -attr vt d
+load net {conc#634.itm(1)} -attr vt d
+load net {conc#634.itm(2)} -attr vt d
+load net {conc#634.itm(3)} -attr vt d
+load net {conc#634.itm(4)} -attr vt d
+load netBundle {conc#634.itm} 5 {conc#634.itm(0)} {conc#634.itm(1)} {conc#634.itm(2)} {conc#634.itm(3)} {conc#634.itm(4)} -attr xrf 33196 -attr oid 360 -attr vt d -attr @path {/sobel/sobel:core/conc#634.itm}
+load net {ACC1:acc#281.itm(0)} -attr vt d
+load net {ACC1:acc#281.itm(1)} -attr vt d
+load net {ACC1:acc#281.itm(2)} -attr vt d
+load net {ACC1:acc#281.itm(3)} -attr vt d
+load netBundle {ACC1:acc#281.itm} 4 {ACC1:acc#281.itm(0)} {ACC1:acc#281.itm(1)} {ACC1:acc#281.itm(2)} {ACC1:acc#281.itm(3)} -attr xrf 33197 -attr oid 361 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:slc#81.itm(0)} -attr vt d
+load net {ACC1:slc#81.itm(1)} -attr vt d
+load net {ACC1:slc#81.itm(2)} -attr vt d
+load netBundle {ACC1:slc#81.itm} 3 {ACC1:slc#81.itm(0)} {ACC1:slc#81.itm(1)} {ACC1:slc#81.itm(2)} -attr xrf 33198 -attr oid 362 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#81.itm}
+load net {ACC1:acc#275.itm(0)} -attr vt d
+load net {ACC1:acc#275.itm(1)} -attr vt d
+load net {ACC1:acc#275.itm(2)} -attr vt d
+load net {ACC1:acc#275.itm(3)} -attr vt d
+load netBundle {ACC1:acc#275.itm} 4 {ACC1:acc#275.itm(0)} {ACC1:acc#275.itm(1)} {ACC1:acc#275.itm(2)} {ACC1:acc#275.itm(3)} -attr xrf 33199 -attr oid 363 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {exs#59.itm(0)} -attr vt d
+load net {exs#59.itm(1)} -attr vt d
+load net {exs#59.itm(2)} -attr vt d
+load netBundle {exs#59.itm} 3 {exs#59.itm(0)} {exs#59.itm(1)} {exs#59.itm(2)} -attr xrf 33200 -attr oid 364 -attr vt d -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {conc#635.itm(0)} -attr vt d
+load net {conc#635.itm(1)} -attr vt d
+load netBundle {conc#635.itm} 2 {conc#635.itm(0)} {conc#635.itm(1)} -attr xrf 33201 -attr oid 365 -attr vt d -attr @path {/sobel/sobel:core/conc#635.itm}
+load net {ACC1:exs#782.itm(0)} -attr vt d
+load net {ACC1:exs#782.itm(1)} -attr vt d
+load net {ACC1:exs#782.itm(2)} -attr vt d
+load netBundle {ACC1:exs#782.itm} 3 {ACC1:exs#782.itm(0)} {ACC1:exs#782.itm(1)} {ACC1:exs#782.itm(2)} -attr xrf 33202 -attr oid 366 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#782.itm}
+load net {ACC1:conc#609.itm(0)} -attr vt d
+load net {ACC1:conc#609.itm(1)} -attr vt d
+load netBundle {ACC1:conc#609.itm} 2 {ACC1:conc#609.itm(0)} {ACC1:conc#609.itm(1)} -attr xrf 33203 -attr oid 367 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#609.itm}
+load net {conc#637.itm(0)} -attr vt d
+load net {conc#637.itm(1)} -attr vt d
+load net {conc#637.itm(2)} -attr vt d
+load net {conc#637.itm(3)} -attr vt d
+load net {conc#637.itm(4)} -attr vt d
+load net {conc#637.itm(5)} -attr vt d
+load net {conc#637.itm(6)} -attr vt d
+load net {conc#637.itm(7)} -attr vt d
+load net {conc#637.itm(8)} -attr vt d
+load net {conc#637.itm(9)} -attr vt d
+load net {conc#637.itm(10)} -attr vt d
+load netBundle {conc#637.itm} 11 {conc#637.itm(0)} {conc#637.itm(1)} {conc#637.itm(2)} {conc#637.itm(3)} {conc#637.itm(4)} {conc#637.itm(5)} {conc#637.itm(6)} {conc#637.itm(7)} {conc#637.itm(8)} {conc#637.itm(9)} {conc#637.itm(10)} -attr xrf 33204 -attr oid 368 -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {ACC1:acc#346.itm(0)} -attr vt d
+load net {ACC1:acc#346.itm(1)} -attr vt d
+load net {ACC1:acc#346.itm(2)} -attr vt d
+load netBundle {ACC1:acc#346.itm} 3 {ACC1:acc#346.itm(0)} {ACC1:acc#346.itm(1)} {ACC1:acc#346.itm(2)} -attr xrf 33205 -attr oid 369 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:exs#849.itm(0)} -attr vt d
+load net {ACC1:exs#849.itm(1)} -attr vt d
+load netBundle {ACC1:exs#849.itm} 2 {ACC1:exs#849.itm(0)} {ACC1:exs#849.itm(1)} -attr xrf 33206 -attr oid 370 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#849.itm}
+load net {ACC1:acc#265.itm(0)} -attr vt d
+load net {ACC1:acc#265.itm(1)} -attr vt d
+load net {ACC1:acc#265.itm(2)} -attr vt d
+load net {ACC1:acc#265.itm(3)} -attr vt d
+load net {ACC1:acc#265.itm(4)} -attr vt d
+load net {ACC1:acc#265.itm(5)} -attr vt d
+load net {ACC1:acc#265.itm(6)} -attr vt d
+load net {ACC1:acc#265.itm(7)} -attr vt d
+load net {ACC1:acc#265.itm(8)} -attr vt d
+load net {ACC1:acc#265.itm(9)} -attr vt d
+load netBundle {ACC1:acc#265.itm} 10 {ACC1:acc#265.itm(0)} {ACC1:acc#265.itm(1)} {ACC1:acc#265.itm(2)} {ACC1:acc#265.itm(3)} {ACC1:acc#265.itm(4)} {ACC1:acc#265.itm(5)} {ACC1:acc#265.itm(6)} {ACC1:acc#265.itm(7)} {ACC1:acc#265.itm(8)} {ACC1:acc#265.itm(9)} -attr xrf 33207 -attr oid 371 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {conc#638.itm(0)} -attr vt d
+load net {conc#638.itm(1)} -attr vt d
+load net {conc#638.itm(2)} -attr vt d
+load net {conc#638.itm(3)} -attr vt d
+load net {conc#638.itm(4)} -attr vt d
+load net {conc#638.itm(5)} -attr vt d
+load net {conc#638.itm(6)} -attr vt d
+load net {conc#638.itm(7)} -attr vt d
+load net {conc#638.itm(8)} -attr vt d
+load netBundle {conc#638.itm} 9 {conc#638.itm(0)} {conc#638.itm(1)} {conc#638.itm(2)} {conc#638.itm(3)} {conc#638.itm(4)} {conc#638.itm(5)} {conc#638.itm(6)} {conc#638.itm(7)} {conc#638.itm(8)} -attr xrf 33208 -attr oid 372 -attr vt d -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {ACC1:acc#263.itm(0)} -attr vt d
+load net {ACC1:acc#263.itm(1)} -attr vt d
+load net {ACC1:acc#263.itm(2)} -attr vt d
+load net {ACC1:acc#263.itm(3)} -attr vt d
+load net {ACC1:acc#263.itm(4)} -attr vt d
+load net {ACC1:acc#263.itm(5)} -attr vt d
+load net {ACC1:acc#263.itm(6)} -attr vt d
+load net {ACC1:acc#263.itm(7)} -attr vt d
+load netBundle {ACC1:acc#263.itm} 8 {ACC1:acc#263.itm(0)} {ACC1:acc#263.itm(1)} {ACC1:acc#263.itm(2)} {ACC1:acc#263.itm(3)} {ACC1:acc#263.itm(4)} {ACC1:acc#263.itm(5)} {ACC1:acc#263.itm(6)} {ACC1:acc#263.itm(7)} -attr xrf 33209 -attr oid 373 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {conc#639.itm(0)} -attr vt d
+load net {conc#639.itm(1)} -attr vt d
+load net {conc#639.itm(2)} -attr vt d
+load net {conc#639.itm(3)} -attr vt d
+load net {conc#639.itm(4)} -attr vt d
+load net {conc#639.itm(5)} -attr vt d
+load net {conc#639.itm(6)} -attr vt d
+load net {conc#639.itm(7)} -attr vt d
+load netBundle {conc#639.itm} 8 {conc#639.itm(0)} {conc#639.itm(1)} {conc#639.itm(2)} {conc#639.itm(3)} {conc#639.itm(4)} {conc#639.itm(5)} {conc#639.itm(6)} {conc#639.itm(7)} -attr xrf 33210 -attr oid 374 -attr vt d -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {ACC1-3:exs#576.itm(0)} -attr vt d
+load net {ACC1-3:exs#576.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#576.itm} 2 {ACC1-3:exs#576.itm(0)} {ACC1-3:exs#576.itm(1)} -attr xrf 33211 -attr oid 375 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#576.itm}
+load net {ACC1:acc#260.itm(0)} -attr vt d
+load net {ACC1:acc#260.itm(1)} -attr vt d
+load net {ACC1:acc#260.itm(2)} -attr vt d
+load net {ACC1:acc#260.itm(3)} -attr vt d
+load net {ACC1:acc#260.itm(4)} -attr vt d
+load net {ACC1:acc#260.itm(5)} -attr vt d
+load net {ACC1:acc#260.itm(6)} -attr vt d
+load netBundle {ACC1:acc#260.itm} 7 {ACC1:acc#260.itm(0)} {ACC1:acc#260.itm(1)} {ACC1:acc#260.itm(2)} {ACC1:acc#260.itm(3)} {ACC1:acc#260.itm(4)} {ACC1:acc#260.itm(5)} {ACC1:acc#260.itm(6)} -attr xrf 33212 -attr oid 376 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {conc#640.itm(0)} -attr vt d
+load net {conc#640.itm(1)} -attr vt d
+load net {conc#640.itm(2)} -attr vt d
+load net {conc#640.itm(3)} -attr vt d
+load net {conc#640.itm(4)} -attr vt d
+load net {conc#640.itm(5)} -attr vt d
+load netBundle {conc#640.itm} 6 {conc#640.itm(0)} {conc#640.itm(1)} {conc#640.itm(2)} {conc#640.itm(3)} {conc#640.itm(4)} {conc#640.itm(5)} -attr xrf 33213 -attr oid 377 -attr vt d -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {ACC1-3:exs#579.itm(0)} -attr vt d
+load net {ACC1-3:exs#579.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#579.itm} 2 {ACC1-3:exs#579.itm(0)} {ACC1-3:exs#579.itm(1)} -attr xrf 33214 -attr oid 378 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#579.itm}
+load net {ACC1:acc#257.itm(0)} -attr vt d
+load net {ACC1:acc#257.itm(1)} -attr vt d
+load net {ACC1:acc#257.itm(2)} -attr vt d
+load net {ACC1:acc#257.itm(3)} -attr vt d
+load net {ACC1:acc#257.itm(4)} -attr vt d
+load netBundle {ACC1:acc#257.itm} 5 {ACC1:acc#257.itm(0)} {ACC1:acc#257.itm(1)} {ACC1:acc#257.itm(2)} {ACC1:acc#257.itm(3)} {ACC1:acc#257.itm(4)} -attr xrf 33215 -attr oid 379 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#253.itm(0)} -attr vt d
+load net {ACC1:acc#253.itm(1)} -attr vt d
+load net {ACC1:acc#253.itm(2)} -attr vt d
+load net {ACC1:acc#253.itm(3)} -attr vt d
+load netBundle {ACC1:acc#253.itm} 4 {ACC1:acc#253.itm(0)} {ACC1:acc#253.itm(1)} {ACC1:acc#253.itm(2)} {ACC1:acc#253.itm(3)} -attr xrf 33216 -attr oid 380 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:slc#73.itm(0)} -attr vt d
+load net {ACC1:slc#73.itm(1)} -attr vt d
+load net {ACC1:slc#73.itm(2)} -attr vt d
+load netBundle {ACC1:slc#73.itm} 3 {ACC1:slc#73.itm(0)} {ACC1:slc#73.itm(1)} {ACC1:slc#73.itm(2)} -attr xrf 33217 -attr oid 381 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#247.itm(0)} -attr vt d
+load net {ACC1:acc#247.itm(1)} -attr vt d
+load net {ACC1:acc#247.itm(2)} -attr vt d
+load net {ACC1:acc#247.itm(3)} -attr vt d
+load netBundle {ACC1:acc#247.itm} 4 {ACC1:acc#247.itm(0)} {ACC1:acc#247.itm(1)} {ACC1:acc#247.itm(2)} {ACC1:acc#247.itm(3)} -attr xrf 33218 -attr oid 382 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {exs#42.itm(0)} -attr vt d
+load net {exs#42.itm(1)} -attr vt d
+load net {exs#42.itm(2)} -attr vt d
+load netBundle {exs#42.itm} 3 {exs#42.itm(0)} {exs#42.itm(1)} {exs#42.itm(2)} -attr xrf 33219 -attr oid 383 -attr vt d -attr @path {/sobel/sobel:core/exs#42.itm}
+load net {conc#641.itm(0)} -attr vt d
+load net {conc#641.itm(1)} -attr vt d
+load netBundle {conc#641.itm} 2 {conc#641.itm(0)} {conc#641.itm(1)} -attr xrf 33220 -attr oid 384 -attr vt d -attr @path {/sobel/sobel:core/conc#641.itm}
+load net {ACC1:exs#785.itm(0)} -attr vt d
+load net {ACC1:exs#785.itm(1)} -attr vt d
+load net {ACC1:exs#785.itm(2)} -attr vt d
+load netBundle {ACC1:exs#785.itm} 3 {ACC1:exs#785.itm(0)} {ACC1:exs#785.itm(1)} {ACC1:exs#785.itm(2)} -attr xrf 33221 -attr oid 385 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#785.itm}
+load net {ACC1:conc#592.itm(0)} -attr vt d
+load net {ACC1:conc#592.itm(1)} -attr vt d
+load netBundle {ACC1:conc#592.itm} 2 {ACC1:conc#592.itm(0)} {ACC1:conc#592.itm(1)} -attr xrf 33222 -attr oid 386 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#592.itm}
+load net {ACC1:slc#72.itm(0)} -attr vt d
+load net {ACC1:slc#72.itm(1)} -attr vt d
+load net {ACC1:slc#72.itm(2)} -attr vt d
+load netBundle {ACC1:slc#72.itm} 3 {ACC1:slc#72.itm(0)} {ACC1:slc#72.itm(1)} {ACC1:slc#72.itm(2)} -attr xrf 33223 -attr oid 387 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#246.itm(0)} -attr vt d
+load net {ACC1:acc#246.itm(1)} -attr vt d
+load net {ACC1:acc#246.itm(2)} -attr vt d
+load net {ACC1:acc#246.itm(3)} -attr vt d
+load netBundle {ACC1:acc#246.itm} 4 {ACC1:acc#246.itm(0)} {ACC1:acc#246.itm(1)} {ACC1:acc#246.itm(2)} {ACC1:acc#246.itm(3)} -attr xrf 33224 -attr oid 388 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {exs#43.itm(0)} -attr vt d
+load net {exs#43.itm(1)} -attr vt d
+load net {exs#43.itm(2)} -attr vt d
+load netBundle {exs#43.itm} 3 {exs#43.itm(0)} {exs#43.itm(1)} {exs#43.itm(2)} -attr xrf 33225 -attr oid 389 -attr vt d -attr @path {/sobel/sobel:core/exs#43.itm}
+load net {conc#642.itm(0)} -attr vt d
+load net {conc#642.itm(1)} -attr vt d
+load netBundle {conc#642.itm} 2 {conc#642.itm(0)} {conc#642.itm(1)} -attr xrf 33226 -attr oid 390 -attr vt d -attr @path {/sobel/sobel:core/conc#642.itm}
+load net {ACC1:exs#787.itm(0)} -attr vt d
+load net {ACC1:exs#787.itm(1)} -attr vt d
+load net {ACC1:exs#787.itm(2)} -attr vt d
+load netBundle {ACC1:exs#787.itm} 3 {ACC1:exs#787.itm(0)} {ACC1:exs#787.itm(1)} {ACC1:exs#787.itm(2)} -attr xrf 33227 -attr oid 391 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#787.itm}
+load net {ACC1:conc#590.itm(0)} -attr vt d
+load net {ACC1:conc#590.itm(1)} -attr vt d
+load netBundle {ACC1:conc#590.itm} 2 {ACC1:conc#590.itm(0)} {ACC1:conc#590.itm(1)} -attr xrf 33228 -attr oid 392 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#590.itm}
+load net {ACC1:acc#252.itm(0)} -attr vt d
+load net {ACC1:acc#252.itm(1)} -attr vt d
+load net {ACC1:acc#252.itm(2)} -attr vt d
+load net {ACC1:acc#252.itm(3)} -attr vt d
+load netBundle {ACC1:acc#252.itm} 4 {ACC1:acc#252.itm(0)} {ACC1:acc#252.itm(1)} {ACC1:acc#252.itm(2)} {ACC1:acc#252.itm(3)} -attr xrf 33229 -attr oid 393 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:slc#71.itm(0)} -attr vt d
+load net {ACC1:slc#71.itm(1)} -attr vt d
+load net {ACC1:slc#71.itm(2)} -attr vt d
+load netBundle {ACC1:slc#71.itm} 3 {ACC1:slc#71.itm(0)} {ACC1:slc#71.itm(1)} {ACC1:slc#71.itm(2)} -attr xrf 33230 -attr oid 394 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#71.itm}
+load net {ACC1:acc#245.itm(0)} -attr vt d
+load net {ACC1:acc#245.itm(1)} -attr vt d
+load net {ACC1:acc#245.itm(2)} -attr vt d
+load net {ACC1:acc#245.itm(3)} -attr vt d
+load netBundle {ACC1:acc#245.itm} 4 {ACC1:acc#245.itm(0)} {ACC1:acc#245.itm(1)} {ACC1:acc#245.itm(2)} {ACC1:acc#245.itm(3)} -attr xrf 33231 -attr oid 395 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {exs#44.itm(0)} -attr vt d
+load net {exs#44.itm(1)} -attr vt d
+load net {exs#44.itm(2)} -attr vt d
+load netBundle {exs#44.itm} 3 {exs#44.itm(0)} {exs#44.itm(1)} {exs#44.itm(2)} -attr xrf 33232 -attr oid 396 -attr vt d -attr @path {/sobel/sobel:core/exs#44.itm}
+load net {conc#643.itm(0)} -attr vt d
+load net {conc#643.itm(1)} -attr vt d
+load netBundle {conc#643.itm} 2 {conc#643.itm(0)} {conc#643.itm(1)} -attr xrf 33233 -attr oid 397 -attr vt d -attr @path {/sobel/sobel:core/conc#643.itm}
+load net {ACC1:exs#789.itm(0)} -attr vt d
+load net {ACC1:exs#789.itm(1)} -attr vt d
+load net {ACC1:exs#789.itm(2)} -attr vt d
+load netBundle {ACC1:exs#789.itm} 3 {ACC1:exs#789.itm(0)} {ACC1:exs#789.itm(1)} {ACC1:exs#789.itm(2)} -attr xrf 33234 -attr oid 398 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#789.itm}
+load net {ACC1:conc#588.itm(0)} -attr vt d
+load net {ACC1:conc#588.itm(1)} -attr vt d
+load netBundle {ACC1:conc#588.itm} 2 {ACC1:conc#588.itm(0)} {ACC1:conc#588.itm(1)} -attr xrf 33235 -attr oid 399 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#588.itm}
+load net {ACC1:slc#70.itm(0)} -attr vt d
+load net {ACC1:slc#70.itm(1)} -attr vt d
+load net {ACC1:slc#70.itm(2)} -attr vt d
+load netBundle {ACC1:slc#70.itm} 3 {ACC1:slc#70.itm(0)} {ACC1:slc#70.itm(1)} {ACC1:slc#70.itm(2)} -attr xrf 33236 -attr oid 400 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#70.itm}
+load net {ACC1:acc#244.itm(0)} -attr vt d
+load net {ACC1:acc#244.itm(1)} -attr vt d
+load net {ACC1:acc#244.itm(2)} -attr vt d
+load net {ACC1:acc#244.itm(3)} -attr vt d
+load netBundle {ACC1:acc#244.itm} 4 {ACC1:acc#244.itm(0)} {ACC1:acc#244.itm(1)} {ACC1:acc#244.itm(2)} {ACC1:acc#244.itm(3)} -attr xrf 33237 -attr oid 401 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#244.itm}
+load net {exs#45.itm(0)} -attr vt d
+load net {exs#45.itm(1)} -attr vt d
+load net {exs#45.itm(2)} -attr vt d
+load netBundle {exs#45.itm} 3 {exs#45.itm(0)} {exs#45.itm(1)} {exs#45.itm(2)} -attr xrf 33238 -attr oid 402 -attr vt d -attr @path {/sobel/sobel:core/exs#45.itm}
+load net {conc#644.itm(0)} -attr vt d
+load net {conc#644.itm(1)} -attr vt d
+load netBundle {conc#644.itm} 2 {conc#644.itm(0)} {conc#644.itm(1)} -attr xrf 33239 -attr oid 403 -attr vt d -attr @path {/sobel/sobel:core/conc#644.itm}
+load net {ACC1:exs#791.itm(0)} -attr vt d
+load net {ACC1:exs#791.itm(1)} -attr vt d
+load net {ACC1:exs#791.itm(2)} -attr vt d
+load netBundle {ACC1:exs#791.itm} 3 {ACC1:exs#791.itm(0)} {ACC1:exs#791.itm(1)} {ACC1:exs#791.itm(2)} -attr xrf 33240 -attr oid 404 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#791.itm}
+load net {ACC1:conc#586.itm(0)} -attr vt d
+load net {ACC1:conc#586.itm(1)} -attr vt d
+load netBundle {ACC1:conc#586.itm} 2 {ACC1:conc#586.itm(0)} {ACC1:conc#586.itm(1)} -attr xrf 33241 -attr oid 405 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#586.itm}
+load net {FRAME:for:acc#24.itm(0)} -attr vt d
+load net {FRAME:for:acc#24.itm(1)} -attr vt d
+load net {FRAME:for:acc#24.itm(2)} -attr vt d
+load net {FRAME:for:acc#24.itm(3)} -attr vt d
+load net {FRAME:for:acc#24.itm(4)} -attr vt d
+load net {FRAME:for:acc#24.itm(5)} -attr vt d
+load net {FRAME:for:acc#24.itm(6)} -attr vt d
+load net {FRAME:for:acc#24.itm(7)} -attr vt d
+load net {FRAME:for:acc#24.itm(8)} -attr vt d
+load net {FRAME:for:acc#24.itm(9)} -attr vt d
+load net {FRAME:for:acc#24.itm(10)} -attr vt d
+load net {FRAME:for:acc#24.itm(11)} -attr vt d
+load net {FRAME:for:acc#24.itm(12)} -attr vt d
+load netBundle {FRAME:for:acc#24.itm} 13 {FRAME:for:acc#24.itm(0)} {FRAME:for:acc#24.itm(1)} {FRAME:for:acc#24.itm(2)} {FRAME:for:acc#24.itm(3)} {FRAME:for:acc#24.itm(4)} {FRAME:for:acc#24.itm(5)} {FRAME:for:acc#24.itm(6)} {FRAME:for:acc#24.itm(7)} {FRAME:for:acc#24.itm(8)} {FRAME:for:acc#24.itm(9)} {FRAME:for:acc#24.itm(10)} {FRAME:for:acc#24.itm(11)} {FRAME:for:acc#24.itm(12)} -attr xrf 33242 -attr oid 406 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#23.itm(0)} -attr vt d
+load net {FRAME:for:acc#23.itm(1)} -attr vt d
+load net {FRAME:for:acc#23.itm(2)} -attr vt d
+load net {FRAME:for:acc#23.itm(3)} -attr vt d
+load net {FRAME:for:acc#23.itm(4)} -attr vt d
+load net {FRAME:for:acc#23.itm(5)} -attr vt d
+load net {FRAME:for:acc#23.itm(6)} -attr vt d
+load net {FRAME:for:acc#23.itm(7)} -attr vt d
+load net {FRAME:for:acc#23.itm(8)} -attr vt d
+load net {FRAME:for:acc#23.itm(9)} -attr vt d
+load net {FRAME:for:acc#23.itm(10)} -attr vt d
+load net {FRAME:for:acc#23.itm(11)} -attr vt d
+load net {FRAME:for:acc#23.itm(12)} -attr vt d
+load netBundle {FRAME:for:acc#23.itm} 13 {FRAME:for:acc#23.itm(0)} {FRAME:for:acc#23.itm(1)} {FRAME:for:acc#23.itm(2)} {FRAME:for:acc#23.itm(3)} {FRAME:for:acc#23.itm(4)} {FRAME:for:acc#23.itm(5)} {FRAME:for:acc#23.itm(6)} {FRAME:for:acc#23.itm(7)} {FRAME:for:acc#23.itm(8)} {FRAME:for:acc#23.itm(9)} {FRAME:for:acc#23.itm(10)} {FRAME:for:acc#23.itm(11)} {FRAME:for:acc#23.itm(12)} -attr xrf 33243 -attr oid 407 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:mul#1.itm(0)} -attr vt d
+load net {FRAME:for:mul#1.itm(1)} -attr vt d
+load net {FRAME:for:mul#1.itm(2)} -attr vt d
+load net {FRAME:for:mul#1.itm(3)} -attr vt d
+load net {FRAME:for:mul#1.itm(4)} -attr vt d
+load net {FRAME:for:mul#1.itm(5)} -attr vt d
+load net {FRAME:for:mul#1.itm(6)} -attr vt d
+load net {FRAME:for:mul#1.itm(7)} -attr vt d
+load net {FRAME:for:mul#1.itm(8)} -attr vt d
+load net {FRAME:for:mul#1.itm(9)} -attr vt d
+load net {FRAME:for:mul#1.itm(10)} -attr vt d
+load net {FRAME:for:mul#1.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul#1.itm} 12 {FRAME:for:mul#1.itm(0)} {FRAME:for:mul#1.itm(1)} {FRAME:for:mul#1.itm(2)} {FRAME:for:mul#1.itm(3)} {FRAME:for:mul#1.itm(4)} {FRAME:for:mul#1.itm(5)} {FRAME:for:mul#1.itm(6)} {FRAME:for:mul#1.itm(7)} {FRAME:for:mul#1.itm(8)} {FRAME:for:mul#1.itm(9)} {FRAME:for:mul#1.itm(10)} {FRAME:for:mul#1.itm(11)} -attr xrf 33244 -attr oid 408 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {regs.operator[]#10:mux.itm(0)} -attr vt d
+load net {regs.operator[]#10:mux.itm(1)} -attr vt d
+load net {regs.operator[]#10:mux.itm(2)} -attr vt d
+load net {regs.operator[]#10:mux.itm(3)} -attr vt d
+load net {regs.operator[]#10:mux.itm(4)} -attr vt d
+load net {regs.operator[]#10:mux.itm(5)} -attr vt d
+load net {regs.operator[]#10:mux.itm(6)} -attr vt d
+load net {regs.operator[]#10:mux.itm(7)} -attr vt d
+load net {regs.operator[]#10:mux.itm(8)} -attr vt d
+load net {regs.operator[]#10:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#10:mux.itm} 10 {regs.operator[]#10:mux.itm(0)} {regs.operator[]#10:mux.itm(1)} {regs.operator[]#10:mux.itm(2)} {regs.operator[]#10:mux.itm(3)} {regs.operator[]#10:mux.itm(4)} {regs.operator[]#10:mux.itm(5)} {regs.operator[]#10:mux.itm(6)} {regs.operator[]#10:mux.itm(7)} {regs.operator[]#10:mux.itm(8)} {regs.operator[]#10:mux.itm(9)} -attr xrf 33245 -attr oid 409 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm} 10 {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(0)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(1)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(2)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(3)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(4)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(5)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(6)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(7)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(8)} {slc(regs.regs(2).lpi#1.dfm#1:mx0).itm(9)} -attr xrf 33246 -attr oid 410 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr xrf 33247 -attr oid 411 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr xrf 33248 -attr oid 412 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {conc#645.itm(0)} -attr vt d
+load net {conc#645.itm(1)} -attr vt d
+load netBundle {conc#645.itm} 2 {conc#645.itm(0)} {conc#645.itm(1)} -attr xrf 33249 -attr oid 413 -attr vt d -attr @path {/sobel/sobel:core/conc#645.itm}
+load net {FRAME:for:mul#2.itm(0)} -attr vt d
+load net {FRAME:for:mul#2.itm(1)} -attr vt d
+load net {FRAME:for:mul#2.itm(2)} -attr vt d
+load net {FRAME:for:mul#2.itm(3)} -attr vt d
+load net {FRAME:for:mul#2.itm(4)} -attr vt d
+load net {FRAME:for:mul#2.itm(5)} -attr vt d
+load net {FRAME:for:mul#2.itm(6)} -attr vt d
+load net {FRAME:for:mul#2.itm(7)} -attr vt d
+load net {FRAME:for:mul#2.itm(8)} -attr vt d
+load net {FRAME:for:mul#2.itm(9)} -attr vt d
+load net {FRAME:for:mul#2.itm(10)} -attr vt d
+load net {FRAME:for:mul#2.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul#2.itm} 12 {FRAME:for:mul#2.itm(0)} {FRAME:for:mul#2.itm(1)} {FRAME:for:mul#2.itm(2)} {FRAME:for:mul#2.itm(3)} {FRAME:for:mul#2.itm(4)} {FRAME:for:mul#2.itm(5)} {FRAME:for:mul#2.itm(6)} {FRAME:for:mul#2.itm(7)} {FRAME:for:mul#2.itm(8)} {FRAME:for:mul#2.itm(9)} {FRAME:for:mul#2.itm(10)} {FRAME:for:mul#2.itm(11)} -attr xrf 33250 -attr oid 414 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {regs.operator[]#11:mux.itm(0)} -attr vt d
+load net {regs.operator[]#11:mux.itm(1)} -attr vt d
+load net {regs.operator[]#11:mux.itm(2)} -attr vt d
+load net {regs.operator[]#11:mux.itm(3)} -attr vt d
+load net {regs.operator[]#11:mux.itm(4)} -attr vt d
+load net {regs.operator[]#11:mux.itm(5)} -attr vt d
+load net {regs.operator[]#11:mux.itm(6)} -attr vt d
+load net {regs.operator[]#11:mux.itm(7)} -attr vt d
+load net {regs.operator[]#11:mux.itm(8)} -attr vt d
+load net {regs.operator[]#11:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#11:mux.itm} 10 {regs.operator[]#11:mux.itm(0)} {regs.operator[]#11:mux.itm(1)} {regs.operator[]#11:mux.itm(2)} {regs.operator[]#11:mux.itm(3)} {regs.operator[]#11:mux.itm(4)} {regs.operator[]#11:mux.itm(5)} {regs.operator[]#11:mux.itm(6)} {regs.operator[]#11:mux.itm(7)} {regs.operator[]#11:mux.itm(8)} {regs.operator[]#11:mux.itm(9)} -attr xrf 33251 -attr oid 415 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm} 10 {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(0)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(1)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(2)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(3)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(4)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(5)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(6)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(7)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(8)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm(9)} -attr xrf 33252 -attr oid 416 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr xrf 33253 -attr oid 417 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr xrf 33254 -attr oid 418 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {conc#646.itm(0)} -attr vt d
+load net {conc#646.itm(1)} -attr vt d
+load netBundle {conc#646.itm} 2 {conc#646.itm(0)} {conc#646.itm(1)} -attr xrf 33255 -attr oid 419 -attr vt d -attr @path {/sobel/sobel:core/conc#646.itm}
+load net {FRAME:for:mul.itm(0)} -attr vt d
+load net {FRAME:for:mul.itm(1)} -attr vt d
+load net {FRAME:for:mul.itm(2)} -attr vt d
+load net {FRAME:for:mul.itm(3)} -attr vt d
+load net {FRAME:for:mul.itm(4)} -attr vt d
+load net {FRAME:for:mul.itm(5)} -attr vt d
+load net {FRAME:for:mul.itm(6)} -attr vt d
+load net {FRAME:for:mul.itm(7)} -attr vt d
+load net {FRAME:for:mul.itm(8)} -attr vt d
+load net {FRAME:for:mul.itm(9)} -attr vt d
+load net {FRAME:for:mul.itm(10)} -attr vt d
+load net {FRAME:for:mul.itm(11)} -attr vt d
+load netBundle {FRAME:for:mul.itm} 12 {FRAME:for:mul.itm(0)} {FRAME:for:mul.itm(1)} {FRAME:for:mul.itm(2)} {FRAME:for:mul.itm(3)} {FRAME:for:mul.itm(4)} {FRAME:for:mul.itm(5)} {FRAME:for:mul.itm(6)} {FRAME:for:mul.itm(7)} {FRAME:for:mul.itm(8)} {FRAME:for:mul.itm(9)} {FRAME:for:mul.itm(10)} {FRAME:for:mul.itm(11)} -attr xrf 33256 -attr oid 420 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {regs.operator[]#9:mux.itm(0)} -attr vt d
+load net {regs.operator[]#9:mux.itm(1)} -attr vt d
+load net {regs.operator[]#9:mux.itm(2)} -attr vt d
+load net {regs.operator[]#9:mux.itm(3)} -attr vt d
+load net {regs.operator[]#9:mux.itm(4)} -attr vt d
+load net {regs.operator[]#9:mux.itm(5)} -attr vt d
+load net {regs.operator[]#9:mux.itm(6)} -attr vt d
+load net {regs.operator[]#9:mux.itm(7)} -attr vt d
+load net {regs.operator[]#9:mux.itm(8)} -attr vt d
+load net {regs.operator[]#9:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#9:mux.itm} 10 {regs.operator[]#9:mux.itm(0)} {regs.operator[]#9:mux.itm(1)} {regs.operator[]#9:mux.itm(2)} {regs.operator[]#9:mux.itm(3)} {regs.operator[]#9:mux.itm(4)} {regs.operator[]#9:mux.itm(5)} {regs.operator[]#9:mux.itm(6)} {regs.operator[]#9:mux.itm(7)} {regs.operator[]#9:mux.itm(8)} {regs.operator[]#9:mux.itm(9)} -attr xrf 33257 -attr oid 421 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm} 10 {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(0)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(1)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(2)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(3)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(4)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(5)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(6)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(7)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(8)} {slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm(9)} -attr xrf 33258 -attr oid 422 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr xrf 33259 -attr oid 423 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr xrf 33260 -attr oid 424 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {conc#647.itm(0)} -attr vt d
+load net {conc#647.itm(1)} -attr vt d
+load netBundle {conc#647.itm} 2 {conc#647.itm(0)} {conc#647.itm(1)} -attr xrf 33261 -attr oid 425 -attr vt d -attr @path {/sobel/sobel:core/conc#647.itm}
+load net {ACC1-3:acc#122.itm(0)} -attr vt d
+load net {ACC1-3:acc#122.itm(1)} -attr vt d
+load net {ACC1-3:acc#122.itm(2)} -attr vt d
+load net {ACC1-3:acc#122.itm(3)} -attr vt d
+load net {ACC1-3:acc#122.itm(4)} -attr vt d
+load net {ACC1-3:acc#122.itm(5)} -attr vt d
+load net {ACC1-3:acc#122.itm(6)} -attr vt d
+load net {ACC1-3:acc#122.itm(7)} -attr vt d
+load net {ACC1-3:acc#122.itm(8)} -attr vt d
+load net {ACC1-3:acc#122.itm(9)} -attr vt d
+load net {ACC1-3:acc#122.itm(10)} -attr vt d
+load net {ACC1-3:acc#122.itm(11)} -attr vt d
+load netBundle {ACC1-3:acc#122.itm} 12 {ACC1-3:acc#122.itm(0)} {ACC1-3:acc#122.itm(1)} {ACC1-3:acc#122.itm(2)} {ACC1-3:acc#122.itm(3)} {ACC1-3:acc#122.itm(4)} {ACC1-3:acc#122.itm(5)} {ACC1-3:acc#122.itm(6)} {ACC1-3:acc#122.itm(7)} {ACC1-3:acc#122.itm(8)} {ACC1-3:acc#122.itm(9)} {ACC1-3:acc#122.itm(10)} {ACC1-3:acc#122.itm(11)} -attr xrf 33262 -attr oid 426 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1:acc#215.itm(0)} -attr vt d
+load net {ACC1:acc#215.itm(1)} -attr vt d
+load net {ACC1:acc#215.itm(2)} -attr vt d
+load net {ACC1:acc#215.itm(3)} -attr vt d
+load net {ACC1:acc#215.itm(4)} -attr vt d
+load net {ACC1:acc#215.itm(5)} -attr vt d
+load net {ACC1:acc#215.itm(6)} -attr vt d
+load net {ACC1:acc#215.itm(7)} -attr vt d
+load net {ACC1:acc#215.itm(8)} -attr vt d
+load net {ACC1:acc#215.itm(9)} -attr vt d
+load net {ACC1:acc#215.itm(10)} -attr vt d
+load netBundle {ACC1:acc#215.itm} 11 {ACC1:acc#215.itm(0)} {ACC1:acc#215.itm(1)} {ACC1:acc#215.itm(2)} {ACC1:acc#215.itm(3)} {ACC1:acc#215.itm(4)} {ACC1:acc#215.itm(5)} {ACC1:acc#215.itm(6)} {ACC1:acc#215.itm(7)} {ACC1:acc#215.itm(8)} {ACC1:acc#215.itm(9)} {ACC1:acc#215.itm(10)} -attr xrf 33263 -attr oid 427 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {conc#648.itm(0)} -attr vt d
+load net {conc#648.itm(1)} -attr vt d
+load net {conc#648.itm(2)} -attr vt d
+load net {conc#648.itm(3)} -attr vt d
+load net {conc#648.itm(4)} -attr vt d
+load net {conc#648.itm(5)} -attr vt d
+load net {conc#648.itm(6)} -attr vt d
+load net {conc#648.itm(7)} -attr vt d
+load net {conc#648.itm(8)} -attr vt d
+load net {conc#648.itm(9)} -attr vt d
+load netBundle {conc#648.itm} 10 {conc#648.itm(0)} {conc#648.itm(1)} {conc#648.itm(2)} {conc#648.itm(3)} {conc#648.itm(4)} {conc#648.itm(5)} {conc#648.itm(6)} {conc#648.itm(7)} {conc#648.itm(8)} {conc#648.itm(9)} -attr xrf 33264 -attr oid 428 -attr vt d -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {ACC1:acc#213.itm(0)} -attr vt d
+load net {ACC1:acc#213.itm(1)} -attr vt d
+load net {ACC1:acc#213.itm(2)} -attr vt d
+load net {ACC1:acc#213.itm(3)} -attr vt d
+load net {ACC1:acc#213.itm(4)} -attr vt d
+load net {ACC1:acc#213.itm(5)} -attr vt d
+load net {ACC1:acc#213.itm(6)} -attr vt d
+load net {ACC1:acc#213.itm(7)} -attr vt d
+load net {ACC1:acc#213.itm(8)} -attr vt d
+load net {ACC1:acc#213.itm(9)} -attr vt d
+load net {ACC1:acc#213.itm(10)} -attr vt d
+load netBundle {ACC1:acc#213.itm} 11 {ACC1:acc#213.itm(0)} {ACC1:acc#213.itm(1)} {ACC1:acc#213.itm(2)} {ACC1:acc#213.itm(3)} {ACC1:acc#213.itm(4)} {ACC1:acc#213.itm(5)} {ACC1:acc#213.itm(6)} {ACC1:acc#213.itm(7)} {ACC1:acc#213.itm(8)} {ACC1:acc#213.itm(9)} {ACC1:acc#213.itm(10)} -attr xrf 33265 -attr oid 429 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#211.itm(0)} -attr vt d
+load net {ACC1:acc#211.itm(1)} -attr vt d
+load net {ACC1:acc#211.itm(2)} -attr vt d
+load net {ACC1:acc#211.itm(3)} -attr vt d
+load net {ACC1:acc#211.itm(4)} -attr vt d
+load net {ACC1:acc#211.itm(5)} -attr vt d
+load net {ACC1:acc#211.itm(6)} -attr vt d
+load net {ACC1:acc#211.itm(7)} -attr vt d
+load net {ACC1:acc#211.itm(8)} -attr vt d
+load net {ACC1:acc#211.itm(9)} -attr vt d
+load netBundle {ACC1:acc#211.itm} 10 {ACC1:acc#211.itm(0)} {ACC1:acc#211.itm(1)} {ACC1:acc#211.itm(2)} {ACC1:acc#211.itm(3)} {ACC1:acc#211.itm(4)} {ACC1:acc#211.itm(5)} {ACC1:acc#211.itm(6)} {ACC1:acc#211.itm(7)} {ACC1:acc#211.itm(8)} {ACC1:acc#211.itm(9)} -attr xrf 33266 -attr oid 430 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#209.itm(0)} -attr vt d
+load net {ACC1:acc#209.itm(1)} -attr vt d
+load net {ACC1:acc#209.itm(2)} -attr vt d
+load net {ACC1:acc#209.itm(3)} -attr vt d
+load net {ACC1:acc#209.itm(4)} -attr vt d
+load net {ACC1:acc#209.itm(5)} -attr vt d
+load net {ACC1:acc#209.itm(6)} -attr vt d
+load net {ACC1:acc#209.itm(7)} -attr vt d
+load netBundle {ACC1:acc#209.itm} 8 {ACC1:acc#209.itm(0)} {ACC1:acc#209.itm(1)} {ACC1:acc#209.itm(2)} {ACC1:acc#209.itm(3)} {ACC1:acc#209.itm(4)} {ACC1:acc#209.itm(5)} {ACC1:acc#209.itm(6)} {ACC1:acc#209.itm(7)} -attr xrf 33267 -attr oid 431 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#206.itm(0)} -attr vt d
+load net {ACC1:acc#206.itm(1)} -attr vt d
+load net {ACC1:acc#206.itm(2)} -attr vt d
+load net {ACC1:acc#206.itm(3)} -attr vt d
+load net {ACC1:acc#206.itm(4)} -attr vt d
+load net {ACC1:acc#206.itm(5)} -attr vt d
+load netBundle {ACC1:acc#206.itm} 6 {ACC1:acc#206.itm(0)} {ACC1:acc#206.itm(1)} {ACC1:acc#206.itm(2)} {ACC1:acc#206.itm(3)} {ACC1:acc#206.itm(4)} {ACC1:acc#206.itm(5)} -attr xrf 33268 -attr oid 432 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#203.itm(0)} -attr vt d
+load net {ACC1:acc#203.itm(1)} -attr vt d
+load net {ACC1:acc#203.itm(2)} -attr vt d
+load net {ACC1:acc#203.itm(3)} -attr vt d
+load netBundle {ACC1:acc#203.itm} 4 {ACC1:acc#203.itm(0)} {ACC1:acc#203.itm(1)} {ACC1:acc#203.itm(2)} {ACC1:acc#203.itm(3)} -attr xrf 33269 -attr oid 433 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#198.itm(0)} -attr vt d
+load net {ACC1:acc#198.itm(1)} -attr vt d
+load net {ACC1:acc#198.itm(2)} -attr vt d
+load netBundle {ACC1:acc#198.itm} 3 {ACC1:acc#198.itm(0)} {ACC1:acc#198.itm(1)} {ACC1:acc#198.itm(2)} -attr xrf 33270 -attr oid 434 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:slc#54.itm(0)} -attr vt d
+load net {ACC1:slc#54.itm(1)} -attr vt d
+load net {ACC1:slc#54.itm(2)} -attr vt d
+load netBundle {ACC1:slc#54.itm} 3 {ACC1:slc#54.itm(0)} {ACC1:slc#54.itm(1)} {ACC1:slc#54.itm(2)} -attr xrf 33271 -attr oid 435 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#54.itm}
+load net {ACC1:acc#189.itm(0)} -attr vt d
+load net {ACC1:acc#189.itm(1)} -attr vt d
+load net {ACC1:acc#189.itm(2)} -attr vt d
+load net {ACC1:acc#189.itm(3)} -attr vt d
+load netBundle {ACC1:acc#189.itm} 4 {ACC1:acc#189.itm(0)} {ACC1:acc#189.itm(1)} {ACC1:acc#189.itm(2)} {ACC1:acc#189.itm(3)} -attr xrf 33272 -attr oid 436 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {conc#649.itm(0)} -attr vt d
+load net {conc#649.itm(1)} -attr vt d
+load net {conc#649.itm(2)} -attr vt d
+load netBundle {conc#649.itm} 3 {conc#649.itm(0)} {conc#649.itm(1)} {conc#649.itm(2)} -attr xrf 33273 -attr oid 437 -attr vt d -attr @path {/sobel/sobel:core/conc#649.itm}
+load net {ACC1:conc#552.itm(0)} -attr vt d
+load net {ACC1:conc#552.itm(1)} -attr vt d
+load netBundle {ACC1:conc#552.itm} 2 {ACC1:conc#552.itm(0)} {ACC1:conc#552.itm(1)} -attr xrf 33274 -attr oid 438 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#552.itm}
+load net {slc(ACC1:acc#116.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#116.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#116.psp.sva)#2.itm} 2 {slc(ACC1:acc#116.psp.sva)#2.itm(0)} {slc(ACC1:acc#116.psp.sva)#2.itm(1)} -attr xrf 33275 -attr oid 439 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp.sva)#2.itm}
+load net {ACC1:slc#55.itm(0)} -attr vt d
+load net {ACC1:slc#55.itm(1)} -attr vt d
+load net {ACC1:slc#55.itm(2)} -attr vt d
+load net {ACC1:slc#55.itm(3)} -attr vt d
+load netBundle {ACC1:slc#55.itm} 4 {ACC1:slc#55.itm(0)} {ACC1:slc#55.itm(1)} {ACC1:slc#55.itm(2)} {ACC1:slc#55.itm(3)} -attr xrf 33276 -attr oid 440 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#55.itm}
+load net {ACC1:acc#190.itm(0)} -attr vt d
+load net {ACC1:acc#190.itm(1)} -attr vt d
+load net {ACC1:acc#190.itm(2)} -attr vt d
+load net {ACC1:acc#190.itm(3)} -attr vt d
+load net {ACC1:acc#190.itm(4)} -attr vt d
+load netBundle {ACC1:acc#190.itm} 5 {ACC1:acc#190.itm(0)} {ACC1:acc#190.itm(1)} {ACC1:acc#190.itm(2)} {ACC1:acc#190.itm(3)} {ACC1:acc#190.itm(4)} -attr xrf 33277 -attr oid 441 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load net {conc#650.itm(0)} -attr vt d
+load net {conc#650.itm(1)} -attr vt d
+load net {conc#650.itm(2)} -attr vt d
+load netBundle {conc#650.itm} 3 {conc#650.itm(0)} {conc#650.itm(1)} {conc#650.itm(2)} -attr xrf 33278 -attr oid 442 -attr vt d -attr @path {/sobel/sobel:core/conc#650.itm}
+load net {ACC1:conc#554.itm(0)} -attr vt d
+load net {ACC1:conc#554.itm(1)} -attr vt d
+load net {ACC1:conc#554.itm(2)} -attr vt d
+load netBundle {ACC1:conc#554.itm} 3 {ACC1:conc#554.itm(0)} {ACC1:conc#554.itm(1)} {ACC1:conc#554.itm(2)} -attr xrf 33279 -attr oid 443 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#554.itm}
+load net {ACC1:acc#202.itm(0)} -attr vt d
+load net {ACC1:acc#202.itm(1)} -attr vt d
+load net {ACC1:acc#202.itm(2)} -attr vt d
+load net {ACC1:acc#202.itm(3)} -attr vt d
+load net {ACC1:acc#202.itm(4)} -attr vt d
+load netBundle {ACC1:acc#202.itm} 5 {ACC1:acc#202.itm(0)} {ACC1:acc#202.itm(1)} {ACC1:acc#202.itm(2)} {ACC1:acc#202.itm(3)} {ACC1:acc#202.itm(4)} -attr xrf 33280 -attr oid 444 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1-3:conc#260.itm(0)} -attr vt d
+load net {ACC1-3:conc#260.itm(1)} -attr vt d
+load net {ACC1-3:conc#260.itm(2)} -attr vt d
+load net {ACC1-3:conc#260.itm(3)} -attr vt d
+load netBundle {ACC1-3:conc#260.itm} 4 {ACC1-3:conc#260.itm(0)} {ACC1-3:conc#260.itm(1)} {ACC1-3:conc#260.itm(2)} {ACC1-3:conc#260.itm(3)} -attr xrf 33281 -attr oid 445 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#260.itm}
+load net {ACC1-3:exs#559.itm(0)} -attr vt d
+load net {ACC1-3:exs#559.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#559.itm} 2 {ACC1-3:exs#559.itm(0)} {ACC1-3:exs#559.itm(1)} -attr xrf 33282 -attr oid 446 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#559.itm}
+load net {conc#651.itm(0)} -attr vt d
+load net {conc#651.itm(1)} -attr vt d
+load net {conc#651.itm(2)} -attr vt d
+load net {conc#651.itm(3)} -attr vt d
+load net {conc#651.itm(4)} -attr vt d
+load net {conc#651.itm(5)} -attr vt d
+load net {conc#651.itm(6)} -attr vt d
+load netBundle {conc#651.itm} 7 {conc#651.itm(0)} {conc#651.itm(1)} {conc#651.itm(2)} {conc#651.itm(3)} {conc#651.itm(4)} {conc#651.itm(5)} {conc#651.itm(6)} -attr xrf 33283 -attr oid 447 -attr vt d -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {ACC1:acc#208.itm(0)} -attr vt d
+load net {ACC1:acc#208.itm(1)} -attr vt d
+load net {ACC1:acc#208.itm(2)} -attr vt d
+load net {ACC1:acc#208.itm(3)} -attr vt d
+load net {ACC1:acc#208.itm(4)} -attr vt d
+load net {ACC1:acc#208.itm(5)} -attr vt d
+load net {ACC1:acc#208.itm(6)} -attr vt d
+load net {ACC1:acc#208.itm(7)} -attr vt d
+load netBundle {ACC1:acc#208.itm} 8 {ACC1:acc#208.itm(0)} {ACC1:acc#208.itm(1)} {ACC1:acc#208.itm(2)} {ACC1:acc#208.itm(3)} {ACC1:acc#208.itm(4)} {ACC1:acc#208.itm(5)} {ACC1:acc#208.itm(6)} {ACC1:acc#208.itm(7)} -attr xrf 33284 -attr oid 448 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1-3:exs#538.itm(0)} -attr vt d
+load net {ACC1-3:exs#538.itm(1)} -attr vt d
+load net {ACC1-3:exs#538.itm(2)} -attr vt d
+load net {ACC1-3:exs#538.itm(3)} -attr vt d
+load net {ACC1-3:exs#538.itm(4)} -attr vt d
+load net {ACC1-3:exs#538.itm(5)} -attr vt d
+load net {ACC1-3:exs#538.itm(6)} -attr vt d
+load netBundle {ACC1-3:exs#538.itm} 7 {ACC1-3:exs#538.itm(0)} {ACC1-3:exs#538.itm(1)} {ACC1-3:exs#538.itm(2)} {ACC1-3:exs#538.itm(3)} {ACC1-3:exs#538.itm(4)} {ACC1-3:exs#538.itm(5)} {ACC1-3:exs#538.itm(6)} -attr xrf 33285 -attr oid 449 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {ACC1-3:conc#226.itm(0)} -attr vt d
+load net {ACC1-3:conc#226.itm(1)} -attr vt d
+load net {ACC1-3:conc#226.itm(2)} -attr vt d
+load netBundle {ACC1-3:conc#226.itm} 3 {ACC1-3:conc#226.itm(0)} {ACC1-3:conc#226.itm(1)} {ACC1-3:conc#226.itm(2)} -attr xrf 33286 -attr oid 450 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#226.itm}
+load net {ACC1-3:exs#560.itm(0)} -attr vt d
+load net {ACC1-3:exs#560.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#560.itm} 2 {ACC1-3:exs#560.itm(0)} {ACC1-3:exs#560.itm(1)} -attr xrf 33287 -attr oid 451 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#560.itm}
+load net {ACC1:acc#205.itm(0)} -attr vt d
+load net {ACC1:acc#205.itm(1)} -attr vt d
+load net {ACC1:acc#205.itm(2)} -attr vt d
+load net {ACC1:acc#205.itm(3)} -attr vt d
+load net {ACC1:acc#205.itm(4)} -attr vt d
+load net {ACC1:acc#205.itm(5)} -attr vt d
+load netBundle {ACC1:acc#205.itm} 6 {ACC1:acc#205.itm(0)} {ACC1:acc#205.itm(1)} {ACC1:acc#205.itm(2)} {ACC1:acc#205.itm(3)} {ACC1:acc#205.itm(4)} {ACC1:acc#205.itm(5)} -attr xrf 33288 -attr oid 452 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {conc#652.itm(0)} -attr vt d
+load net {conc#652.itm(1)} -attr vt d
+load net {conc#652.itm(2)} -attr vt d
+load net {conc#652.itm(3)} -attr vt d
+load net {conc#652.itm(4)} -attr vt d
+load netBundle {conc#652.itm} 5 {conc#652.itm(0)} {conc#652.itm(1)} {conc#652.itm(2)} {conc#652.itm(3)} {conc#652.itm(4)} -attr xrf 33289 -attr oid 453 -attr vt d -attr @path {/sobel/sobel:core/conc#652.itm}
+load net {ACC1:acc#201.itm(0)} -attr vt d
+load net {ACC1:acc#201.itm(1)} -attr vt d
+load net {ACC1:acc#201.itm(2)} -attr vt d
+load net {ACC1:acc#201.itm(3)} -attr vt d
+load netBundle {ACC1:acc#201.itm} 4 {ACC1:acc#201.itm(0)} {ACC1:acc#201.itm(1)} {ACC1:acc#201.itm(2)} {ACC1:acc#201.itm(3)} -attr xrf 33290 -attr oid 454 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:slc#60.itm(0)} -attr vt d
+load net {ACC1:slc#60.itm(1)} -attr vt d
+load net {ACC1:slc#60.itm(2)} -attr vt d
+load netBundle {ACC1:slc#60.itm} 3 {ACC1:slc#60.itm(0)} {ACC1:slc#60.itm(1)} {ACC1:slc#60.itm(2)} -attr xrf 33291 -attr oid 455 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#60.itm}
+load net {ACC1:acc#195.itm(0)} -attr vt d
+load net {ACC1:acc#195.itm(1)} -attr vt d
+load net {ACC1:acc#195.itm(2)} -attr vt d
+load net {ACC1:acc#195.itm(3)} -attr vt d
+load netBundle {ACC1:acc#195.itm} 4 {ACC1:acc#195.itm(0)} {ACC1:acc#195.itm(1)} {ACC1:acc#195.itm(2)} {ACC1:acc#195.itm(3)} -attr xrf 33292 -attr oid 456 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load net {exs#60.itm(0)} -attr vt d
+load net {exs#60.itm(1)} -attr vt d
+load net {exs#60.itm(2)} -attr vt d
+load netBundle {exs#60.itm} 3 {exs#60.itm(0)} {exs#60.itm(1)} {exs#60.itm(2)} -attr xrf 33293 -attr oid 457 -attr vt d -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {conc#653.itm(0)} -attr vt d
+load net {conc#653.itm(1)} -attr vt d
+load netBundle {conc#653.itm} 2 {conc#653.itm(0)} {conc#653.itm(1)} -attr xrf 33294 -attr oid 458 -attr vt d -attr @path {/sobel/sobel:core/conc#653.itm}
+load net {ACC1:exs#751.itm(0)} -attr vt d
+load net {ACC1:exs#751.itm(1)} -attr vt d
+load net {ACC1:exs#751.itm(2)} -attr vt d
+load netBundle {ACC1:exs#751.itm} 3 {ACC1:exs#751.itm(0)} {ACC1:exs#751.itm(1)} {ACC1:exs#751.itm(2)} -attr xrf 33295 -attr oid 459 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#751.itm}
+load net {ACC1:conc#564.itm(0)} -attr vt d
+load net {ACC1:conc#564.itm(1)} -attr vt d
+load netBundle {ACC1:conc#564.itm} 2 {ACC1:conc#564.itm(0)} {ACC1:conc#564.itm(1)} -attr xrf 33296 -attr oid 460 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#564.itm}
+load net {conc#655.itm(0)} -attr vt d
+load net {conc#655.itm(1)} -attr vt d
+load net {conc#655.itm(2)} -attr vt d
+load net {conc#655.itm(3)} -attr vt d
+load net {conc#655.itm(4)} -attr vt d
+load net {conc#655.itm(5)} -attr vt d
+load net {conc#655.itm(6)} -attr vt d
+load net {conc#655.itm(7)} -attr vt d
+load net {conc#655.itm(8)} -attr vt d
+load net {conc#655.itm(9)} -attr vt d
+load netBundle {conc#655.itm} 10 {conc#655.itm(0)} {conc#655.itm(1)} {conc#655.itm(2)} {conc#655.itm(3)} {conc#655.itm(4)} {conc#655.itm(5)} {conc#655.itm(6)} {conc#655.itm(7)} {conc#655.itm(8)} {conc#655.itm(9)} -attr xrf 33297 -attr oid 461 -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {ACC1-3:exs#581.itm(0)} -attr vt d
+load net {ACC1-3:exs#581.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#581.itm} 2 {ACC1-3:exs#581.itm(0)} {ACC1-3:exs#581.itm(1)} -attr xrf 33298 -attr oid 462 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#581.itm}
+load net {ACC1:acc#214.itm(0)} -attr vt d
+load net {ACC1:acc#214.itm(1)} -attr vt d
+load net {ACC1:acc#214.itm(2)} -attr vt d
+load net {ACC1:acc#214.itm(3)} -attr vt d
+load net {ACC1:acc#214.itm(4)} -attr vt d
+load net {ACC1:acc#214.itm(5)} -attr vt d
+load net {ACC1:acc#214.itm(6)} -attr vt d
+load net {ACC1:acc#214.itm(7)} -attr vt d
+load net {ACC1:acc#214.itm(8)} -attr vt d
+load net {ACC1:acc#214.itm(9)} -attr vt d
+load net {ACC1:acc#214.itm(10)} -attr vt d
+load net {ACC1:acc#214.itm(11)} -attr vt d
+load netBundle {ACC1:acc#214.itm} 12 {ACC1:acc#214.itm(0)} {ACC1:acc#214.itm(1)} {ACC1:acc#214.itm(2)} {ACC1:acc#214.itm(3)} {ACC1:acc#214.itm(4)} {ACC1:acc#214.itm(5)} {ACC1:acc#214.itm(6)} {ACC1:acc#214.itm(7)} {ACC1:acc#214.itm(8)} {ACC1:acc#214.itm(9)} {ACC1:acc#214.itm(10)} {ACC1:acc#214.itm(11)} -attr xrf 33299 -attr oid 463 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1-1:acc#122.itm(0)} -attr vt d
+load net {ACC1-1:acc#122.itm(1)} -attr vt d
+load net {ACC1-1:acc#122.itm(2)} -attr vt d
+load net {ACC1-1:acc#122.itm(3)} -attr vt d
+load net {ACC1-1:acc#122.itm(4)} -attr vt d
+load net {ACC1-1:acc#122.itm(5)} -attr vt d
+load net {ACC1-1:acc#122.itm(6)} -attr vt d
+load net {ACC1-1:acc#122.itm(7)} -attr vt d
+load net {ACC1-1:acc#122.itm(8)} -attr vt d
+load net {ACC1-1:acc#122.itm(9)} -attr vt d
+load net {ACC1-1:acc#122.itm(10)} -attr vt d
+load netBundle {ACC1-1:acc#122.itm} 11 {ACC1-1:acc#122.itm(0)} {ACC1-1:acc#122.itm(1)} {ACC1-1:acc#122.itm(2)} {ACC1-1:acc#122.itm(3)} {ACC1-1:acc#122.itm(4)} {ACC1-1:acc#122.itm(5)} {ACC1-1:acc#122.itm(6)} {ACC1-1:acc#122.itm(7)} {ACC1-1:acc#122.itm(8)} {ACC1-1:acc#122.itm(9)} {ACC1-1:acc#122.itm(10)} -attr xrf 33300 -attr oid 464 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1:acc#241.itm(0)} -attr vt d
+load net {ACC1:acc#241.itm(1)} -attr vt d
+load net {ACC1:acc#241.itm(2)} -attr vt d
+load net {ACC1:acc#241.itm(3)} -attr vt d
+load net {ACC1:acc#241.itm(4)} -attr vt d
+load net {ACC1:acc#241.itm(5)} -attr vt d
+load net {ACC1:acc#241.itm(6)} -attr vt d
+load net {ACC1:acc#241.itm(7)} -attr vt d
+load net {ACC1:acc#241.itm(8)} -attr vt d
+load net {ACC1:acc#241.itm(9)} -attr vt d
+load net {ACC1:acc#241.itm(10)} -attr vt d
+load netBundle {ACC1:acc#241.itm} 11 {ACC1:acc#241.itm(0)} {ACC1:acc#241.itm(1)} {ACC1:acc#241.itm(2)} {ACC1:acc#241.itm(3)} {ACC1:acc#241.itm(4)} {ACC1:acc#241.itm(5)} {ACC1:acc#241.itm(6)} {ACC1:acc#241.itm(7)} {ACC1:acc#241.itm(8)} {ACC1:acc#241.itm(9)} {ACC1:acc#241.itm(10)} -attr xrf 33301 -attr oid 465 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#239.itm(0)} -attr vt d
+load net {ACC1:acc#239.itm(1)} -attr vt d
+load net {ACC1:acc#239.itm(2)} -attr vt d
+load net {ACC1:acc#239.itm(3)} -attr vt d
+load net {ACC1:acc#239.itm(4)} -attr vt d
+load net {ACC1:acc#239.itm(5)} -attr vt d
+load net {ACC1:acc#239.itm(6)} -attr vt d
+load net {ACC1:acc#239.itm(7)} -attr vt d
+load net {ACC1:acc#239.itm(8)} -attr vt d
+load net {ACC1:acc#239.itm(9)} -attr vt d
+load netBundle {ACC1:acc#239.itm} 10 {ACC1:acc#239.itm(0)} {ACC1:acc#239.itm(1)} {ACC1:acc#239.itm(2)} {ACC1:acc#239.itm(3)} {ACC1:acc#239.itm(4)} {ACC1:acc#239.itm(5)} {ACC1:acc#239.itm(6)} {ACC1:acc#239.itm(7)} {ACC1:acc#239.itm(8)} {ACC1:acc#239.itm(9)} -attr xrf 33302 -attr oid 466 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {conc#656.itm(0)} -attr vt d
+load net {conc#656.itm(1)} -attr vt d
+load net {conc#656.itm(2)} -attr vt d
+load net {conc#656.itm(3)} -attr vt d
+load net {conc#656.itm(4)} -attr vt d
+load net {conc#656.itm(5)} -attr vt d
+load net {conc#656.itm(6)} -attr vt d
+load net {conc#656.itm(7)} -attr vt d
+load net {conc#656.itm(8)} -attr vt d
+load netBundle {conc#656.itm} 9 {conc#656.itm(0)} {conc#656.itm(1)} {conc#656.itm(2)} {conc#656.itm(3)} {conc#656.itm(4)} {conc#656.itm(5)} {conc#656.itm(6)} {conc#656.itm(7)} {conc#656.itm(8)} -attr xrf 33303 -attr oid 467 -attr vt d -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {ACC1:acc#237.itm(0)} -attr vt d
+load net {ACC1:acc#237.itm(1)} -attr vt d
+load net {ACC1:acc#237.itm(2)} -attr vt d
+load net {ACC1:acc#237.itm(3)} -attr vt d
+load net {ACC1:acc#237.itm(4)} -attr vt d
+load net {ACC1:acc#237.itm(5)} -attr vt d
+load net {ACC1:acc#237.itm(6)} -attr vt d
+load net {ACC1:acc#237.itm(7)} -attr vt d
+load netBundle {ACC1:acc#237.itm} 8 {ACC1:acc#237.itm(0)} {ACC1:acc#237.itm(1)} {ACC1:acc#237.itm(2)} {ACC1:acc#237.itm(3)} {ACC1:acc#237.itm(4)} {ACC1:acc#237.itm(5)} {ACC1:acc#237.itm(6)} {ACC1:acc#237.itm(7)} -attr xrf 33304 -attr oid 468 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {conc#657.itm(0)} -attr vt d
+load net {conc#657.itm(1)} -attr vt d
+load net {conc#657.itm(2)} -attr vt d
+load net {conc#657.itm(3)} -attr vt d
+load net {conc#657.itm(4)} -attr vt d
+load net {conc#657.itm(5)} -attr vt d
+load net {conc#657.itm(6)} -attr vt d
+load net {conc#657.itm(7)} -attr vt d
+load netBundle {conc#657.itm} 8 {conc#657.itm(0)} {conc#657.itm(1)} {conc#657.itm(2)} {conc#657.itm(3)} {conc#657.itm(4)} {conc#657.itm(5)} {conc#657.itm(6)} {conc#657.itm(7)} -attr xrf 33305 -attr oid 469 -attr vt d -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {ACC1-1:exs#558.itm(0)} -attr vt d
+load net {ACC1-1:exs#558.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#558.itm} 2 {ACC1-1:exs#558.itm(0)} {ACC1-1:exs#558.itm(1)} -attr xrf 33306 -attr oid 470 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#558.itm}
+load net {ACC1:acc#234.itm(0)} -attr vt d
+load net {ACC1:acc#234.itm(1)} -attr vt d
+load net {ACC1:acc#234.itm(2)} -attr vt d
+load net {ACC1:acc#234.itm(3)} -attr vt d
+load net {ACC1:acc#234.itm(4)} -attr vt d
+load net {ACC1:acc#234.itm(5)} -attr vt d
+load net {ACC1:acc#234.itm(6)} -attr vt d
+load netBundle {ACC1:acc#234.itm} 7 {ACC1:acc#234.itm(0)} {ACC1:acc#234.itm(1)} {ACC1:acc#234.itm(2)} {ACC1:acc#234.itm(3)} {ACC1:acc#234.itm(4)} {ACC1:acc#234.itm(5)} {ACC1:acc#234.itm(6)} -attr xrf 33307 -attr oid 471 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {conc#658.itm(0)} -attr vt d
+load net {conc#658.itm(1)} -attr vt d
+load net {conc#658.itm(2)} -attr vt d
+load net {conc#658.itm(3)} -attr vt d
+load net {conc#658.itm(4)} -attr vt d
+load net {conc#658.itm(5)} -attr vt d
+load netBundle {conc#658.itm} 6 {conc#658.itm(0)} {conc#658.itm(1)} {conc#658.itm(2)} {conc#658.itm(3)} {conc#658.itm(4)} {conc#658.itm(5)} -attr xrf 33308 -attr oid 472 -attr vt d -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {ACC1-1:exs#561.itm(0)} -attr vt d
+load net {ACC1-1:exs#561.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#561.itm} 2 {ACC1-1:exs#561.itm(0)} {ACC1-1:exs#561.itm(1)} -attr xrf 33309 -attr oid 473 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#561.itm}
+load net {ACC1:acc#231.itm(0)} -attr vt d
+load net {ACC1:acc#231.itm(1)} -attr vt d
+load net {ACC1:acc#231.itm(2)} -attr vt d
+load net {ACC1:acc#231.itm(3)} -attr vt d
+load net {ACC1:acc#231.itm(4)} -attr vt d
+load netBundle {ACC1:acc#231.itm} 5 {ACC1:acc#231.itm(0)} {ACC1:acc#231.itm(1)} {ACC1:acc#231.itm(2)} {ACC1:acc#231.itm(3)} {ACC1:acc#231.itm(4)} -attr xrf 33310 -attr oid 474 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#227.itm(0)} -attr vt d
+load net {ACC1:acc#227.itm(1)} -attr vt d
+load net {ACC1:acc#227.itm(2)} -attr vt d
+load net {ACC1:acc#227.itm(3)} -attr vt d
+load netBundle {ACC1:acc#227.itm} 4 {ACC1:acc#227.itm(0)} {ACC1:acc#227.itm(1)} {ACC1:acc#227.itm(2)} {ACC1:acc#227.itm(3)} -attr xrf 33311 -attr oid 475 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:slc#66.itm(0)} -attr vt d
+load net {ACC1:slc#66.itm(1)} -attr vt d
+load net {ACC1:slc#66.itm(2)} -attr vt d
+load netBundle {ACC1:slc#66.itm} 3 {ACC1:slc#66.itm(0)} {ACC1:slc#66.itm(1)} {ACC1:slc#66.itm(2)} -attr xrf 33312 -attr oid 476 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1:acc#221.itm(0)} -attr vt d
+load net {ACC1:acc#221.itm(1)} -attr vt d
+load net {ACC1:acc#221.itm(2)} -attr vt d
+load net {ACC1:acc#221.itm(3)} -attr vt d
+load netBundle {ACC1:acc#221.itm} 4 {ACC1:acc#221.itm(0)} {ACC1:acc#221.itm(1)} {ACC1:acc#221.itm(2)} {ACC1:acc#221.itm(3)} -attr xrf 33313 -attr oid 477 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {exs#46.itm(0)} -attr vt d
+load net {exs#46.itm(1)} -attr vt d
+load net {exs#46.itm(2)} -attr vt d
+load netBundle {exs#46.itm} 3 {exs#46.itm(0)} {exs#46.itm(1)} {exs#46.itm(2)} -attr xrf 33314 -attr oid 478 -attr vt d -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {conc#659.itm(0)} -attr vt d
+load net {conc#659.itm(1)} -attr vt d
+load netBundle {conc#659.itm} 2 {conc#659.itm(0)} {conc#659.itm(1)} -attr xrf 33315 -attr oid 479 -attr vt d -attr @path {/sobel/sobel:core/conc#659.itm}
+load net {ACC1:exs#753.itm(0)} -attr vt d
+load net {ACC1:exs#753.itm(1)} -attr vt d
+load net {ACC1:exs#753.itm(2)} -attr vt d
+load netBundle {ACC1:exs#753.itm} 3 {ACC1:exs#753.itm(0)} {ACC1:exs#753.itm(1)} {ACC1:exs#753.itm(2)} -attr xrf 33316 -attr oid 480 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#753.itm}
+load net {ACC1:conc#577.itm(0)} -attr vt d
+load net {ACC1:conc#577.itm(1)} -attr vt d
+load netBundle {ACC1:conc#577.itm} 2 {ACC1:conc#577.itm(0)} {ACC1:conc#577.itm(1)} -attr xrf 33317 -attr oid 481 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#577.itm}
+load net {ACC1:slc#65.itm(0)} -attr vt d
+load net {ACC1:slc#65.itm(1)} -attr vt d
+load net {ACC1:slc#65.itm(2)} -attr vt d
+load netBundle {ACC1:slc#65.itm} 3 {ACC1:slc#65.itm(0)} {ACC1:slc#65.itm(1)} {ACC1:slc#65.itm(2)} -attr xrf 33318 -attr oid 482 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#220.itm(0)} -attr vt d
+load net {ACC1:acc#220.itm(1)} -attr vt d
+load net {ACC1:acc#220.itm(2)} -attr vt d
+load net {ACC1:acc#220.itm(3)} -attr vt d
+load netBundle {ACC1:acc#220.itm} 4 {ACC1:acc#220.itm(0)} {ACC1:acc#220.itm(1)} {ACC1:acc#220.itm(2)} {ACC1:acc#220.itm(3)} -attr xrf 33319 -attr oid 483 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {exs#47.itm(0)} -attr vt d
+load net {exs#47.itm(1)} -attr vt d
+load net {exs#47.itm(2)} -attr vt d
+load netBundle {exs#47.itm} 3 {exs#47.itm(0)} {exs#47.itm(1)} {exs#47.itm(2)} -attr xrf 33320 -attr oid 484 -attr vt d -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {conc#660.itm(0)} -attr vt d
+load net {conc#660.itm(1)} -attr vt d
+load netBundle {conc#660.itm} 2 {conc#660.itm(0)} {conc#660.itm(1)} -attr xrf 33321 -attr oid 485 -attr vt d -attr @path {/sobel/sobel:core/conc#660.itm}
+load net {ACC1:exs#755.itm(0)} -attr vt d
+load net {ACC1:exs#755.itm(1)} -attr vt d
+load net {ACC1:exs#755.itm(2)} -attr vt d
+load netBundle {ACC1:exs#755.itm} 3 {ACC1:exs#755.itm(0)} {ACC1:exs#755.itm(1)} {ACC1:exs#755.itm(2)} -attr xrf 33322 -attr oid 486 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#755.itm}
+load net {ACC1:conc#575.itm(0)} -attr vt d
+load net {ACC1:conc#575.itm(1)} -attr vt d
+load netBundle {ACC1:conc#575.itm} 2 {ACC1:conc#575.itm(0)} {ACC1:conc#575.itm(1)} -attr xrf 33323 -attr oid 487 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#575.itm}
+load net {ACC1:acc#226.itm(0)} -attr vt d
+load net {ACC1:acc#226.itm(1)} -attr vt d
+load net {ACC1:acc#226.itm(2)} -attr vt d
+load net {ACC1:acc#226.itm(3)} -attr vt d
+load netBundle {ACC1:acc#226.itm} 4 {ACC1:acc#226.itm(0)} {ACC1:acc#226.itm(1)} {ACC1:acc#226.itm(2)} {ACC1:acc#226.itm(3)} -attr xrf 33324 -attr oid 488 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:slc#64.itm(0)} -attr vt d
+load net {ACC1:slc#64.itm(1)} -attr vt d
+load net {ACC1:slc#64.itm(2)} -attr vt d
+load netBundle {ACC1:slc#64.itm} 3 {ACC1:slc#64.itm(0)} {ACC1:slc#64.itm(1)} {ACC1:slc#64.itm(2)} -attr xrf 33325 -attr oid 489 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#219.itm(0)} -attr vt d
+load net {ACC1:acc#219.itm(1)} -attr vt d
+load net {ACC1:acc#219.itm(2)} -attr vt d
+load net {ACC1:acc#219.itm(3)} -attr vt d
+load netBundle {ACC1:acc#219.itm} 4 {ACC1:acc#219.itm(0)} {ACC1:acc#219.itm(1)} {ACC1:acc#219.itm(2)} {ACC1:acc#219.itm(3)} -attr xrf 33326 -attr oid 490 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {exs#48.itm(0)} -attr vt d
+load net {exs#48.itm(1)} -attr vt d
+load net {exs#48.itm(2)} -attr vt d
+load netBundle {exs#48.itm} 3 {exs#48.itm(0)} {exs#48.itm(1)} {exs#48.itm(2)} -attr xrf 33327 -attr oid 491 -attr vt d -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {conc#661.itm(0)} -attr vt d
+load net {conc#661.itm(1)} -attr vt d
+load netBundle {conc#661.itm} 2 {conc#661.itm(0)} {conc#661.itm(1)} -attr xrf 33328 -attr oid 492 -attr vt d -attr @path {/sobel/sobel:core/conc#661.itm}
+load net {ACC1:exs#757.itm(0)} -attr vt d
+load net {ACC1:exs#757.itm(1)} -attr vt d
+load net {ACC1:exs#757.itm(2)} -attr vt d
+load netBundle {ACC1:exs#757.itm} 3 {ACC1:exs#757.itm(0)} {ACC1:exs#757.itm(1)} {ACC1:exs#757.itm(2)} -attr xrf 33329 -attr oid 493 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#757.itm}
+load net {ACC1:conc#573.itm(0)} -attr vt d
+load net {ACC1:conc#573.itm(1)} -attr vt d
+load netBundle {ACC1:conc#573.itm} 2 {ACC1:conc#573.itm(0)} {ACC1:conc#573.itm(1)} -attr xrf 33330 -attr oid 494 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#573.itm}
+load net {ACC1:slc#63.itm(0)} -attr vt d
+load net {ACC1:slc#63.itm(1)} -attr vt d
+load net {ACC1:slc#63.itm(2)} -attr vt d
+load netBundle {ACC1:slc#63.itm} 3 {ACC1:slc#63.itm(0)} {ACC1:slc#63.itm(1)} {ACC1:slc#63.itm(2)} -attr xrf 33331 -attr oid 495 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#63.itm}
+load net {ACC1:acc#218.itm(0)} -attr vt d
+load net {ACC1:acc#218.itm(1)} -attr vt d
+load net {ACC1:acc#218.itm(2)} -attr vt d
+load net {ACC1:acc#218.itm(3)} -attr vt d
+load netBundle {ACC1:acc#218.itm} 4 {ACC1:acc#218.itm(0)} {ACC1:acc#218.itm(1)} {ACC1:acc#218.itm(2)} {ACC1:acc#218.itm(3)} -attr xrf 33332 -attr oid 496 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {exs#49.itm(0)} -attr vt d
+load net {exs#49.itm(1)} -attr vt d
+load net {exs#49.itm(2)} -attr vt d
+load netBundle {exs#49.itm} 3 {exs#49.itm(0)} {exs#49.itm(1)} {exs#49.itm(2)} -attr xrf 33333 -attr oid 497 -attr vt d -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {conc#662.itm(0)} -attr vt d
+load net {conc#662.itm(1)} -attr vt d
+load netBundle {conc#662.itm} 2 {conc#662.itm(0)} {conc#662.itm(1)} -attr xrf 33334 -attr oid 498 -attr vt d -attr @path {/sobel/sobel:core/conc#662.itm}
+load net {ACC1:exs#759.itm(0)} -attr vt d
+load net {ACC1:exs#759.itm(1)} -attr vt d
+load net {ACC1:exs#759.itm(2)} -attr vt d
+load netBundle {ACC1:exs#759.itm} 3 {ACC1:exs#759.itm(0)} {ACC1:exs#759.itm(1)} {ACC1:exs#759.itm(2)} -attr xrf 33335 -attr oid 499 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#759.itm}
+load net {ACC1:conc#571.itm(0)} -attr vt d
+load net {ACC1:conc#571.itm(1)} -attr vt d
+load netBundle {ACC1:conc#571.itm} 2 {ACC1:conc#571.itm(0)} {ACC1:conc#571.itm(1)} -attr xrf 33336 -attr oid 500 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#571.itm}
+load net {ACC1:acc#238.itm(0)} -attr vt d
+load net {ACC1:acc#238.itm(1)} -attr vt d
+load net {ACC1:acc#238.itm(2)} -attr vt d
+load net {ACC1:acc#238.itm(3)} -attr vt d
+load net {ACC1:acc#238.itm(4)} -attr vt d
+load net {ACC1:acc#238.itm(5)} -attr vt d
+load net {ACC1:acc#238.itm(6)} -attr vt d
+load net {ACC1:acc#238.itm(7)} -attr vt d
+load net {ACC1:acc#238.itm(8)} -attr vt d
+load net {ACC1:acc#238.itm(9)} -attr vt d
+load netBundle {ACC1:acc#238.itm} 10 {ACC1:acc#238.itm(0)} {ACC1:acc#238.itm(1)} {ACC1:acc#238.itm(2)} {ACC1:acc#238.itm(3)} {ACC1:acc#238.itm(4)} {ACC1:acc#238.itm(5)} {ACC1:acc#238.itm(6)} {ACC1:acc#238.itm(7)} {ACC1:acc#238.itm(8)} {ACC1:acc#238.itm(9)} -attr xrf 33337 -attr oid 501 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#236.itm(0)} -attr vt d
+load net {ACC1:acc#236.itm(1)} -attr vt d
+load net {ACC1:acc#236.itm(2)} -attr vt d
+load net {ACC1:acc#236.itm(3)} -attr vt d
+load net {ACC1:acc#236.itm(4)} -attr vt d
+load net {ACC1:acc#236.itm(5)} -attr vt d
+load net {ACC1:acc#236.itm(6)} -attr vt d
+load net {ACC1:acc#236.itm(7)} -attr vt d
+load netBundle {ACC1:acc#236.itm} 8 {ACC1:acc#236.itm(0)} {ACC1:acc#236.itm(1)} {ACC1:acc#236.itm(2)} {ACC1:acc#236.itm(3)} {ACC1:acc#236.itm(4)} {ACC1:acc#236.itm(5)} {ACC1:acc#236.itm(6)} {ACC1:acc#236.itm(7)} -attr xrf 33338 -attr oid 502 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#233.itm(0)} -attr vt d
+load net {ACC1:acc#233.itm(1)} -attr vt d
+load net {ACC1:acc#233.itm(2)} -attr vt d
+load net {ACC1:acc#233.itm(3)} -attr vt d
+load net {ACC1:acc#233.itm(4)} -attr vt d
+load net {ACC1:acc#233.itm(5)} -attr vt d
+load netBundle {ACC1:acc#233.itm} 6 {ACC1:acc#233.itm(0)} {ACC1:acc#233.itm(1)} {ACC1:acc#233.itm(2)} {ACC1:acc#233.itm(3)} {ACC1:acc#233.itm(4)} {ACC1:acc#233.itm(5)} -attr xrf 33339 -attr oid 503 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#230.itm(0)} -attr vt d
+load net {ACC1:acc#230.itm(1)} -attr vt d
+load net {ACC1:acc#230.itm(2)} -attr vt d
+load net {ACC1:acc#230.itm(3)} -attr vt d
+load netBundle {ACC1:acc#230.itm} 4 {ACC1:acc#230.itm(0)} {ACC1:acc#230.itm(1)} {ACC1:acc#230.itm(2)} {ACC1:acc#230.itm(3)} -attr xrf 33340 -attr oid 504 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#225.itm(0)} -attr vt d
+load net {ACC1:acc#225.itm(1)} -attr vt d
+load net {ACC1:acc#225.itm(2)} -attr vt d
+load netBundle {ACC1:acc#225.itm} 3 {ACC1:acc#225.itm(0)} {ACC1:acc#225.itm(1)} {ACC1:acc#225.itm(2)} -attr xrf 33341 -attr oid 505 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:slc#61.itm(0)} -attr vt d
+load net {ACC1:slc#61.itm(1)} -attr vt d
+load net {ACC1:slc#61.itm(2)} -attr vt d
+load netBundle {ACC1:slc#61.itm} 3 {ACC1:slc#61.itm(0)} {ACC1:slc#61.itm(1)} {ACC1:slc#61.itm(2)} -attr xrf 33342 -attr oid 506 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#61.itm}
+load net {ACC1:acc#216.itm(0)} -attr vt d
+load net {ACC1:acc#216.itm(1)} -attr vt d
+load net {ACC1:acc#216.itm(2)} -attr vt d
+load net {ACC1:acc#216.itm(3)} -attr vt d
+load netBundle {ACC1:acc#216.itm} 4 {ACC1:acc#216.itm(0)} {ACC1:acc#216.itm(1)} {ACC1:acc#216.itm(2)} {ACC1:acc#216.itm(3)} -attr xrf 33343 -attr oid 507 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {conc#663.itm(0)} -attr vt d
+load net {conc#663.itm(1)} -attr vt d
+load net {conc#663.itm(2)} -attr vt d
+load netBundle {conc#663.itm} 3 {conc#663.itm(0)} {conc#663.itm(1)} {conc#663.itm(2)} -attr xrf 33344 -attr oid 508 -attr vt d -attr @path {/sobel/sobel:core/conc#663.itm}
+load net {ACC1:conc#567.itm(0)} -attr vt d
+load net {ACC1:conc#567.itm(1)} -attr vt d
+load netBundle {ACC1:conc#567.itm} 2 {ACC1:conc#567.itm(0)} {ACC1:conc#567.itm(1)} -attr xrf 33345 -attr oid 509 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#567.itm}
+load net {slc(ACC1:acc#116.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#116.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#116.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#116.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#116.psp#1.sva)#2.itm(1)} -attr xrf 33346 -attr oid 510 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp#1.sva)#2.itm}
+load net {ACC1:slc#62.itm(0)} -attr vt d
+load net {ACC1:slc#62.itm(1)} -attr vt d
+load net {ACC1:slc#62.itm(2)} -attr vt d
+load net {ACC1:slc#62.itm(3)} -attr vt d
+load netBundle {ACC1:slc#62.itm} 4 {ACC1:slc#62.itm(0)} {ACC1:slc#62.itm(1)} {ACC1:slc#62.itm(2)} {ACC1:slc#62.itm(3)} -attr xrf 33347 -attr oid 511 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#62.itm}
+load net {ACC1:acc#217.itm(0)} -attr vt d
+load net {ACC1:acc#217.itm(1)} -attr vt d
+load net {ACC1:acc#217.itm(2)} -attr vt d
+load net {ACC1:acc#217.itm(3)} -attr vt d
+load net {ACC1:acc#217.itm(4)} -attr vt d
+load netBundle {ACC1:acc#217.itm} 5 {ACC1:acc#217.itm(0)} {ACC1:acc#217.itm(1)} {ACC1:acc#217.itm(2)} {ACC1:acc#217.itm(3)} {ACC1:acc#217.itm(4)} -attr xrf 33348 -attr oid 512 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {conc#664.itm(0)} -attr vt d
+load net {conc#664.itm(1)} -attr vt d
+load net {conc#664.itm(2)} -attr vt d
+load netBundle {conc#664.itm} 3 {conc#664.itm(0)} {conc#664.itm(1)} {conc#664.itm(2)} -attr xrf 33349 -attr oid 513 -attr vt d -attr @path {/sobel/sobel:core/conc#664.itm}
+load net {ACC1:conc#569.itm(0)} -attr vt d
+load net {ACC1:conc#569.itm(1)} -attr vt d
+load net {ACC1:conc#569.itm(2)} -attr vt d
+load netBundle {ACC1:conc#569.itm} 3 {ACC1:conc#569.itm(0)} {ACC1:conc#569.itm(1)} {ACC1:conc#569.itm(2)} -attr xrf 33350 -attr oid 514 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#569.itm}
+load net {ACC1:acc#229.itm(0)} -attr vt d
+load net {ACC1:acc#229.itm(1)} -attr vt d
+load net {ACC1:acc#229.itm(2)} -attr vt d
+load net {ACC1:acc#229.itm(3)} -attr vt d
+load net {ACC1:acc#229.itm(4)} -attr vt d
+load netBundle {ACC1:acc#229.itm} 5 {ACC1:acc#229.itm(0)} {ACC1:acc#229.itm(1)} {ACC1:acc#229.itm(2)} {ACC1:acc#229.itm(3)} {ACC1:acc#229.itm(4)} -attr xrf 33351 -attr oid 515 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1-1:conc#260.itm(0)} -attr vt d
+load net {ACC1-1:conc#260.itm(1)} -attr vt d
+load net {ACC1-1:conc#260.itm(2)} -attr vt d
+load net {ACC1-1:conc#260.itm(3)} -attr vt d
+load netBundle {ACC1-1:conc#260.itm} 4 {ACC1-1:conc#260.itm(0)} {ACC1-1:conc#260.itm(1)} {ACC1-1:conc#260.itm(2)} {ACC1-1:conc#260.itm(3)} -attr xrf 33352 -attr oid 516 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#260.itm}
+load net {ACC1-1:exs#552.itm(0)} -attr vt d
+load net {ACC1-1:exs#552.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#552.itm} 2 {ACC1-1:exs#552.itm(0)} {ACC1-1:exs#552.itm(1)} -attr xrf 33353 -attr oid 517 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#552.itm}
+load net {conc#665.itm(0)} -attr vt d
+load net {conc#665.itm(1)} -attr vt d
+load net {conc#665.itm(2)} -attr vt d
+load net {conc#665.itm(3)} -attr vt d
+load net {conc#665.itm(4)} -attr vt d
+load net {conc#665.itm(5)} -attr vt d
+load net {conc#665.itm(6)} -attr vt d
+load netBundle {conc#665.itm} 7 {conc#665.itm(0)} {conc#665.itm(1)} {conc#665.itm(2)} {conc#665.itm(3)} {conc#665.itm(4)} {conc#665.itm(5)} {conc#665.itm(6)} -attr xrf 33354 -attr oid 518 -attr vt d -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {ACC1:acc#235.itm(0)} -attr vt d
+load net {ACC1:acc#235.itm(1)} -attr vt d
+load net {ACC1:acc#235.itm(2)} -attr vt d
+load net {ACC1:acc#235.itm(3)} -attr vt d
+load net {ACC1:acc#235.itm(4)} -attr vt d
+load net {ACC1:acc#235.itm(5)} -attr vt d
+load net {ACC1:acc#235.itm(6)} -attr vt d
+load net {ACC1:acc#235.itm(7)} -attr vt d
+load netBundle {ACC1:acc#235.itm} 8 {ACC1:acc#235.itm(0)} {ACC1:acc#235.itm(1)} {ACC1:acc#235.itm(2)} {ACC1:acc#235.itm(3)} {ACC1:acc#235.itm(4)} {ACC1:acc#235.itm(5)} {ACC1:acc#235.itm(6)} {ACC1:acc#235.itm(7)} -attr xrf 33355 -attr oid 519 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1-1:exs#538.itm(0)} -attr vt d
+load net {ACC1-1:exs#538.itm(1)} -attr vt d
+load net {ACC1-1:exs#538.itm(2)} -attr vt d
+load net {ACC1-1:exs#538.itm(3)} -attr vt d
+load net {ACC1-1:exs#538.itm(4)} -attr vt d
+load net {ACC1-1:exs#538.itm(5)} -attr vt d
+load net {ACC1-1:exs#538.itm(6)} -attr vt d
+load netBundle {ACC1-1:exs#538.itm} 7 {ACC1-1:exs#538.itm(0)} {ACC1-1:exs#538.itm(1)} {ACC1-1:exs#538.itm(2)} {ACC1-1:exs#538.itm(3)} {ACC1-1:exs#538.itm(4)} {ACC1-1:exs#538.itm(5)} {ACC1-1:exs#538.itm(6)} -attr xrf 33356 -attr oid 520 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {ACC1-1:conc#226.itm(0)} -attr vt d
+load net {ACC1-1:conc#226.itm(1)} -attr vt d
+load net {ACC1-1:conc#226.itm(2)} -attr vt d
+load netBundle {ACC1-1:conc#226.itm} 3 {ACC1-1:conc#226.itm(0)} {ACC1-1:conc#226.itm(1)} {ACC1-1:conc#226.itm(2)} -attr xrf 33357 -attr oid 521 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#226.itm}
+load net {ACC1-1:exs#547.itm(0)} -attr vt d
+load net {ACC1-1:exs#547.itm(1)} -attr vt d
+load netBundle {ACC1-1:exs#547.itm} 2 {ACC1-1:exs#547.itm(0)} {ACC1-1:exs#547.itm(1)} -attr xrf 33358 -attr oid 522 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#547.itm}
+load net {ACC1:acc#232.itm(0)} -attr vt d
+load net {ACC1:acc#232.itm(1)} -attr vt d
+load net {ACC1:acc#232.itm(2)} -attr vt d
+load net {ACC1:acc#232.itm(3)} -attr vt d
+load net {ACC1:acc#232.itm(4)} -attr vt d
+load net {ACC1:acc#232.itm(5)} -attr vt d
+load netBundle {ACC1:acc#232.itm} 6 {ACC1:acc#232.itm(0)} {ACC1:acc#232.itm(1)} {ACC1:acc#232.itm(2)} {ACC1:acc#232.itm(3)} {ACC1:acc#232.itm(4)} {ACC1:acc#232.itm(5)} -attr xrf 33359 -attr oid 523 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {conc#666.itm(0)} -attr vt d
+load net {conc#666.itm(1)} -attr vt d
+load net {conc#666.itm(2)} -attr vt d
+load net {conc#666.itm(3)} -attr vt d
+load net {conc#666.itm(4)} -attr vt d
+load netBundle {conc#666.itm} 5 {conc#666.itm(0)} {conc#666.itm(1)} {conc#666.itm(2)} {conc#666.itm(3)} {conc#666.itm(4)} -attr xrf 33360 -attr oid 524 -attr vt d -attr @path {/sobel/sobel:core/conc#666.itm}
+load net {ACC1:acc#228.itm(0)} -attr vt d
+load net {ACC1:acc#228.itm(1)} -attr vt d
+load net {ACC1:acc#228.itm(2)} -attr vt d
+load net {ACC1:acc#228.itm(3)} -attr vt d
+load netBundle {ACC1:acc#228.itm} 4 {ACC1:acc#228.itm(0)} {ACC1:acc#228.itm(1)} {ACC1:acc#228.itm(2)} {ACC1:acc#228.itm(3)} -attr xrf 33361 -attr oid 525 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:slc#67.itm(0)} -attr vt d
+load net {ACC1:slc#67.itm(1)} -attr vt d
+load net {ACC1:slc#67.itm(2)} -attr vt d
+load netBundle {ACC1:slc#67.itm} 3 {ACC1:slc#67.itm(0)} {ACC1:slc#67.itm(1)} {ACC1:slc#67.itm(2)} -attr xrf 33362 -attr oid 526 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#67.itm}
+load net {ACC1:acc#222.itm(0)} -attr vt d
+load net {ACC1:acc#222.itm(1)} -attr vt d
+load net {ACC1:acc#222.itm(2)} -attr vt d
+load net {ACC1:acc#222.itm(3)} -attr vt d
+load netBundle {ACC1:acc#222.itm} 4 {ACC1:acc#222.itm(0)} {ACC1:acc#222.itm(1)} {ACC1:acc#222.itm(2)} {ACC1:acc#222.itm(3)} -attr xrf 33363 -attr oid 527 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {exs#61.itm(0)} -attr vt d
+load net {exs#61.itm(1)} -attr vt d
+load net {exs#61.itm(2)} -attr vt d
+load netBundle {exs#61.itm} 3 {exs#61.itm(0)} {exs#61.itm(1)} {exs#61.itm(2)} -attr xrf 33364 -attr oid 528 -attr vt d -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {conc#667.itm(0)} -attr vt d
+load net {conc#667.itm(1)} -attr vt d
+load netBundle {conc#667.itm} 2 {conc#667.itm(0)} {conc#667.itm(1)} -attr xrf 33365 -attr oid 529 -attr vt d -attr @path {/sobel/sobel:core/conc#667.itm}
+load net {ACC1:exs#761.itm(0)} -attr vt d
+load net {ACC1:exs#761.itm(1)} -attr vt d
+load net {ACC1:exs#761.itm(2)} -attr vt d
+load netBundle {ACC1:exs#761.itm} 3 {ACC1:exs#761.itm(0)} {ACC1:exs#761.itm(1)} {ACC1:exs#761.itm(2)} -attr xrf 33366 -attr oid 530 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#761.itm}
+load net {ACC1:conc#579.itm(0)} -attr vt d
+load net {ACC1:conc#579.itm(1)} -attr vt d
+load netBundle {ACC1:conc#579.itm} 2 {ACC1:conc#579.itm(0)} {ACC1:conc#579.itm(1)} -attr xrf 33367 -attr oid 531 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#579.itm}
+load net {conc#669.itm(0)} -attr vt d
+load net {conc#669.itm(1)} -attr vt d
+load net {conc#669.itm(2)} -attr vt d
+load net {conc#669.itm(3)} -attr vt d
+load net {conc#669.itm(4)} -attr vt d
+load net {conc#669.itm(5)} -attr vt d
+load net {conc#669.itm(6)} -attr vt d
+load net {conc#669.itm(7)} -attr vt d
+load net {conc#669.itm(8)} -attr vt d
+load net {conc#669.itm(9)} -attr vt d
+load net {conc#669.itm(10)} -attr vt d
+load netBundle {conc#669.itm} 11 {conc#669.itm(0)} {conc#669.itm(1)} {conc#669.itm(2)} {conc#669.itm(3)} {conc#669.itm(4)} {conc#669.itm(5)} {conc#669.itm(6)} {conc#669.itm(7)} {conc#669.itm(8)} {conc#669.itm(9)} {conc#669.itm(10)} -attr xrf 33368 -attr oid 532 -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {ACC1:acc#344.itm(0)} -attr vt d
+load net {ACC1:acc#344.itm(1)} -attr vt d
+load net {ACC1:acc#344.itm(2)} -attr vt d
+load netBundle {ACC1:acc#344.itm} 3 {ACC1:acc#344.itm(0)} {ACC1:acc#344.itm(1)} {ACC1:acc#344.itm(2)} -attr xrf 33369 -attr oid 533 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:exs#857.itm(0)} -attr vt d
+load net {ACC1:exs#857.itm(1)} -attr vt d
+load netBundle {ACC1:exs#857.itm} 2 {ACC1:exs#857.itm(0)} {ACC1:exs#857.itm(1)} -attr xrf 33370 -attr oid 534 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#857.itm}
+load net {ACC1:acc#212.itm(0)} -attr vt d
+load net {ACC1:acc#212.itm(1)} -attr vt d
+load net {ACC1:acc#212.itm(2)} -attr vt d
+load net {ACC1:acc#212.itm(3)} -attr vt d
+load net {ACC1:acc#212.itm(4)} -attr vt d
+load net {ACC1:acc#212.itm(5)} -attr vt d
+load net {ACC1:acc#212.itm(6)} -attr vt d
+load net {ACC1:acc#212.itm(7)} -attr vt d
+load net {ACC1:acc#212.itm(8)} -attr vt d
+load net {ACC1:acc#212.itm(9)} -attr vt d
+load netBundle {ACC1:acc#212.itm} 10 {ACC1:acc#212.itm(0)} {ACC1:acc#212.itm(1)} {ACC1:acc#212.itm(2)} {ACC1:acc#212.itm(3)} {ACC1:acc#212.itm(4)} {ACC1:acc#212.itm(5)} {ACC1:acc#212.itm(6)} {ACC1:acc#212.itm(7)} {ACC1:acc#212.itm(8)} {ACC1:acc#212.itm(9)} -attr xrf 33371 -attr oid 535 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {conc#670.itm(0)} -attr vt d
+load net {conc#670.itm(1)} -attr vt d
+load net {conc#670.itm(2)} -attr vt d
+load net {conc#670.itm(3)} -attr vt d
+load net {conc#670.itm(4)} -attr vt d
+load net {conc#670.itm(5)} -attr vt d
+load net {conc#670.itm(6)} -attr vt d
+load net {conc#670.itm(7)} -attr vt d
+load net {conc#670.itm(8)} -attr vt d
+load netBundle {conc#670.itm} 9 {conc#670.itm(0)} {conc#670.itm(1)} {conc#670.itm(2)} {conc#670.itm(3)} {conc#670.itm(4)} {conc#670.itm(5)} {conc#670.itm(6)} {conc#670.itm(7)} {conc#670.itm(8)} -attr xrf 33372 -attr oid 536 -attr vt d -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {ACC1:acc#210.itm(0)} -attr vt d
+load net {ACC1:acc#210.itm(1)} -attr vt d
+load net {ACC1:acc#210.itm(2)} -attr vt d
+load net {ACC1:acc#210.itm(3)} -attr vt d
+load net {ACC1:acc#210.itm(4)} -attr vt d
+load net {ACC1:acc#210.itm(5)} -attr vt d
+load net {ACC1:acc#210.itm(6)} -attr vt d
+load net {ACC1:acc#210.itm(7)} -attr vt d
+load netBundle {ACC1:acc#210.itm} 8 {ACC1:acc#210.itm(0)} {ACC1:acc#210.itm(1)} {ACC1:acc#210.itm(2)} {ACC1:acc#210.itm(3)} {ACC1:acc#210.itm(4)} {ACC1:acc#210.itm(5)} {ACC1:acc#210.itm(6)} {ACC1:acc#210.itm(7)} -attr xrf 33373 -attr oid 537 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {conc#671.itm(0)} -attr vt d
+load net {conc#671.itm(1)} -attr vt d
+load net {conc#671.itm(2)} -attr vt d
+load net {conc#671.itm(3)} -attr vt d
+load net {conc#671.itm(4)} -attr vt d
+load net {conc#671.itm(5)} -attr vt d
+load net {conc#671.itm(6)} -attr vt d
+load net {conc#671.itm(7)} -attr vt d
+load netBundle {conc#671.itm} 8 {conc#671.itm(0)} {conc#671.itm(1)} {conc#671.itm(2)} {conc#671.itm(3)} {conc#671.itm(4)} {conc#671.itm(5)} {conc#671.itm(6)} {conc#671.itm(7)} -attr xrf 33374 -attr oid 538 -attr vt d -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {ACC1-3:exs#585.itm(0)} -attr vt d
+load net {ACC1-3:exs#585.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#585.itm} 2 {ACC1-3:exs#585.itm(0)} {ACC1-3:exs#585.itm(1)} -attr xrf 33375 -attr oid 539 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#585.itm}
+load net {ACC1:acc#207.itm(0)} -attr vt d
+load net {ACC1:acc#207.itm(1)} -attr vt d
+load net {ACC1:acc#207.itm(2)} -attr vt d
+load net {ACC1:acc#207.itm(3)} -attr vt d
+load net {ACC1:acc#207.itm(4)} -attr vt d
+load net {ACC1:acc#207.itm(5)} -attr vt d
+load net {ACC1:acc#207.itm(6)} -attr vt d
+load netBundle {ACC1:acc#207.itm} 7 {ACC1:acc#207.itm(0)} {ACC1:acc#207.itm(1)} {ACC1:acc#207.itm(2)} {ACC1:acc#207.itm(3)} {ACC1:acc#207.itm(4)} {ACC1:acc#207.itm(5)} {ACC1:acc#207.itm(6)} -attr xrf 33376 -attr oid 540 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {conc#672.itm(0)} -attr vt d
+load net {conc#672.itm(1)} -attr vt d
+load net {conc#672.itm(2)} -attr vt d
+load net {conc#672.itm(3)} -attr vt d
+load net {conc#672.itm(4)} -attr vt d
+load net {conc#672.itm(5)} -attr vt d
+load netBundle {conc#672.itm} 6 {conc#672.itm(0)} {conc#672.itm(1)} {conc#672.itm(2)} {conc#672.itm(3)} {conc#672.itm(4)} {conc#672.itm(5)} -attr xrf 33377 -attr oid 541 -attr vt d -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {ACC1-3:exs#588.itm(0)} -attr vt d
+load net {ACC1-3:exs#588.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#588.itm} 2 {ACC1-3:exs#588.itm(0)} {ACC1-3:exs#588.itm(1)} -attr xrf 33378 -attr oid 542 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#588.itm}
+load net {ACC1:acc#204.itm(0)} -attr vt d
+load net {ACC1:acc#204.itm(1)} -attr vt d
+load net {ACC1:acc#204.itm(2)} -attr vt d
+load net {ACC1:acc#204.itm(3)} -attr vt d
+load net {ACC1:acc#204.itm(4)} -attr vt d
+load netBundle {ACC1:acc#204.itm} 5 {ACC1:acc#204.itm(0)} {ACC1:acc#204.itm(1)} {ACC1:acc#204.itm(2)} {ACC1:acc#204.itm(3)} {ACC1:acc#204.itm(4)} -attr xrf 33379 -attr oid 543 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#200.itm(0)} -attr vt d
+load net {ACC1:acc#200.itm(1)} -attr vt d
+load net {ACC1:acc#200.itm(2)} -attr vt d
+load net {ACC1:acc#200.itm(3)} -attr vt d
+load netBundle {ACC1:acc#200.itm} 4 {ACC1:acc#200.itm(0)} {ACC1:acc#200.itm(1)} {ACC1:acc#200.itm(2)} {ACC1:acc#200.itm(3)} -attr xrf 33380 -attr oid 544 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:slc#59.itm(0)} -attr vt d
+load net {ACC1:slc#59.itm(1)} -attr vt d
+load net {ACC1:slc#59.itm(2)} -attr vt d
+load netBundle {ACC1:slc#59.itm} 3 {ACC1:slc#59.itm(0)} {ACC1:slc#59.itm(1)} {ACC1:slc#59.itm(2)} -attr xrf 33381 -attr oid 545 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#59.itm}
+load net {ACC1:acc#194.itm(0)} -attr vt d
+load net {ACC1:acc#194.itm(1)} -attr vt d
+load net {ACC1:acc#194.itm(2)} -attr vt d
+load net {ACC1:acc#194.itm(3)} -attr vt d
+load netBundle {ACC1:acc#194.itm} 4 {ACC1:acc#194.itm(0)} {ACC1:acc#194.itm(1)} {ACC1:acc#194.itm(2)} {ACC1:acc#194.itm(3)} -attr xrf 33382 -attr oid 546 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load net {exs#50.itm(0)} -attr vt d
+load net {exs#50.itm(1)} -attr vt d
+load net {exs#50.itm(2)} -attr vt d
+load netBundle {exs#50.itm} 3 {exs#50.itm(0)} {exs#50.itm(1)} {exs#50.itm(2)} -attr xrf 33383 -attr oid 547 -attr vt d -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {conc#673.itm(0)} -attr vt d
+load net {conc#673.itm(1)} -attr vt d
+load netBundle {conc#673.itm} 2 {conc#673.itm(0)} {conc#673.itm(1)} -attr xrf 33384 -attr oid 548 -attr vt d -attr @path {/sobel/sobel:core/conc#673.itm}
+load net {ACC1:exs#764.itm(0)} -attr vt d
+load net {ACC1:exs#764.itm(1)} -attr vt d
+load net {ACC1:exs#764.itm(2)} -attr vt d
+load netBundle {ACC1:exs#764.itm} 3 {ACC1:exs#764.itm(0)} {ACC1:exs#764.itm(1)} {ACC1:exs#764.itm(2)} -attr xrf 33385 -attr oid 549 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#764.itm}
+load net {ACC1:conc#562.itm(0)} -attr vt d
+load net {ACC1:conc#562.itm(1)} -attr vt d
+load netBundle {ACC1:conc#562.itm} 2 {ACC1:conc#562.itm(0)} {ACC1:conc#562.itm(1)} -attr xrf 33386 -attr oid 550 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#562.itm}
+load net {ACC1:slc#58.itm(0)} -attr vt d
+load net {ACC1:slc#58.itm(1)} -attr vt d
+load net {ACC1:slc#58.itm(2)} -attr vt d
+load netBundle {ACC1:slc#58.itm} 3 {ACC1:slc#58.itm(0)} {ACC1:slc#58.itm(1)} {ACC1:slc#58.itm(2)} -attr xrf 33387 -attr oid 551 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:acc#193.itm(0)} -attr vt d
+load net {ACC1:acc#193.itm(1)} -attr vt d
+load net {ACC1:acc#193.itm(2)} -attr vt d
+load net {ACC1:acc#193.itm(3)} -attr vt d
+load netBundle {ACC1:acc#193.itm} 4 {ACC1:acc#193.itm(0)} {ACC1:acc#193.itm(1)} {ACC1:acc#193.itm(2)} {ACC1:acc#193.itm(3)} -attr xrf 33388 -attr oid 552 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load net {exs#51.itm(0)} -attr vt d
+load net {exs#51.itm(1)} -attr vt d
+load net {exs#51.itm(2)} -attr vt d
+load netBundle {exs#51.itm} 3 {exs#51.itm(0)} {exs#51.itm(1)} {exs#51.itm(2)} -attr xrf 33389 -attr oid 553 -attr vt d -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {conc#674.itm(0)} -attr vt d
+load net {conc#674.itm(1)} -attr vt d
+load netBundle {conc#674.itm} 2 {conc#674.itm(0)} {conc#674.itm(1)} -attr xrf 33390 -attr oid 554 -attr vt d -attr @path {/sobel/sobel:core/conc#674.itm}
+load net {ACC1:exs#766.itm(0)} -attr vt d
+load net {ACC1:exs#766.itm(1)} -attr vt d
+load net {ACC1:exs#766.itm(2)} -attr vt d
+load netBundle {ACC1:exs#766.itm} 3 {ACC1:exs#766.itm(0)} {ACC1:exs#766.itm(1)} {ACC1:exs#766.itm(2)} -attr xrf 33391 -attr oid 555 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#766.itm}
+load net {ACC1:conc#560.itm(0)} -attr vt d
+load net {ACC1:conc#560.itm(1)} -attr vt d
+load netBundle {ACC1:conc#560.itm} 2 {ACC1:conc#560.itm(0)} {ACC1:conc#560.itm(1)} -attr xrf 33392 -attr oid 556 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#560.itm}
+load net {ACC1:acc#199.itm(0)} -attr vt d
+load net {ACC1:acc#199.itm(1)} -attr vt d
+load net {ACC1:acc#199.itm(2)} -attr vt d
+load net {ACC1:acc#199.itm(3)} -attr vt d
+load netBundle {ACC1:acc#199.itm} 4 {ACC1:acc#199.itm(0)} {ACC1:acc#199.itm(1)} {ACC1:acc#199.itm(2)} {ACC1:acc#199.itm(3)} -attr xrf 33393 -attr oid 557 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:slc#57.itm(0)} -attr vt d
+load net {ACC1:slc#57.itm(1)} -attr vt d
+load net {ACC1:slc#57.itm(2)} -attr vt d
+load netBundle {ACC1:slc#57.itm} 3 {ACC1:slc#57.itm(0)} {ACC1:slc#57.itm(1)} {ACC1:slc#57.itm(2)} -attr xrf 33394 -attr oid 558 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#57.itm}
+load net {ACC1:acc#192.itm(0)} -attr vt d
+load net {ACC1:acc#192.itm(1)} -attr vt d
+load net {ACC1:acc#192.itm(2)} -attr vt d
+load net {ACC1:acc#192.itm(3)} -attr vt d
+load netBundle {ACC1:acc#192.itm} 4 {ACC1:acc#192.itm(0)} {ACC1:acc#192.itm(1)} {ACC1:acc#192.itm(2)} {ACC1:acc#192.itm(3)} -attr xrf 33395 -attr oid 559 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {exs#52.itm(0)} -attr vt d
+load net {exs#52.itm(1)} -attr vt d
+load net {exs#52.itm(2)} -attr vt d
+load netBundle {exs#52.itm} 3 {exs#52.itm(0)} {exs#52.itm(1)} {exs#52.itm(2)} -attr xrf 33396 -attr oid 560 -attr vt d -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {conc#675.itm(0)} -attr vt d
+load net {conc#675.itm(1)} -attr vt d
+load netBundle {conc#675.itm} 2 {conc#675.itm(0)} {conc#675.itm(1)} -attr xrf 33397 -attr oid 561 -attr vt d -attr @path {/sobel/sobel:core/conc#675.itm}
+load net {ACC1:exs#768.itm(0)} -attr vt d
+load net {ACC1:exs#768.itm(1)} -attr vt d
+load net {ACC1:exs#768.itm(2)} -attr vt d
+load netBundle {ACC1:exs#768.itm} 3 {ACC1:exs#768.itm(0)} {ACC1:exs#768.itm(1)} {ACC1:exs#768.itm(2)} -attr xrf 33398 -attr oid 562 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#768.itm}
+load net {ACC1:conc#558.itm(0)} -attr vt d
+load net {ACC1:conc#558.itm(1)} -attr vt d
+load netBundle {ACC1:conc#558.itm} 2 {ACC1:conc#558.itm(0)} {ACC1:conc#558.itm(1)} -attr xrf 33399 -attr oid 563 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#558.itm}
+load net {ACC1:slc#56.itm(0)} -attr vt d
+load net {ACC1:slc#56.itm(1)} -attr vt d
+load net {ACC1:slc#56.itm(2)} -attr vt d
+load netBundle {ACC1:slc#56.itm} 3 {ACC1:slc#56.itm(0)} {ACC1:slc#56.itm(1)} {ACC1:slc#56.itm(2)} -attr xrf 33400 -attr oid 564 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#56.itm}
+load net {ACC1:acc#191.itm(0)} -attr vt d
+load net {ACC1:acc#191.itm(1)} -attr vt d
+load net {ACC1:acc#191.itm(2)} -attr vt d
+load net {ACC1:acc#191.itm(3)} -attr vt d
+load netBundle {ACC1:acc#191.itm} 4 {ACC1:acc#191.itm(0)} {ACC1:acc#191.itm(1)} {ACC1:acc#191.itm(2)} {ACC1:acc#191.itm(3)} -attr xrf 33401 -attr oid 565 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load net {exs#53.itm(0)} -attr vt d
+load net {exs#53.itm(1)} -attr vt d
+load net {exs#53.itm(2)} -attr vt d
+load netBundle {exs#53.itm} 3 {exs#53.itm(0)} {exs#53.itm(1)} {exs#53.itm(2)} -attr xrf 33402 -attr oid 566 -attr vt d -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {conc#676.itm(0)} -attr vt d
+load net {conc#676.itm(1)} -attr vt d
+load netBundle {conc#676.itm} 2 {conc#676.itm(0)} {conc#676.itm(1)} -attr xrf 33403 -attr oid 567 -attr vt d -attr @path {/sobel/sobel:core/conc#676.itm}
+load net {ACC1:exs#770.itm(0)} -attr vt d
+load net {ACC1:exs#770.itm(1)} -attr vt d
+load net {ACC1:exs#770.itm(2)} -attr vt d
+load netBundle {ACC1:exs#770.itm} 3 {ACC1:exs#770.itm(0)} {ACC1:exs#770.itm(1)} {ACC1:exs#770.itm(2)} -attr xrf 33404 -attr oid 568 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#770.itm}
+load net {ACC1:conc#556.itm(0)} -attr vt d
+load net {ACC1:conc#556.itm(1)} -attr vt d
+load netBundle {ACC1:conc#556.itm} 2 {ACC1:conc#556.itm(0)} {ACC1:conc#556.itm(1)} -attr xrf 33405 -attr oid 569 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#556.itm}
+load net {mux#18.itm(0)} -attr vt d
+load net {mux#18.itm(1)} -attr vt d
+load net {mux#18.itm(2)} -attr vt d
+load net {mux#18.itm(3)} -attr vt d
+load net {mux#18.itm(4)} -attr vt d
+load net {mux#18.itm(5)} -attr vt d
+load net {mux#18.itm(6)} -attr vt d
+load net {mux#18.itm(7)} -attr vt d
+load net {mux#18.itm(8)} -attr vt d
+load net {mux#18.itm(9)} -attr vt d
+load net {mux#18.itm(10)} -attr vt d
+load net {mux#18.itm(11)} -attr vt d
+load net {mux#18.itm(12)} -attr vt d
+load net {mux#18.itm(13)} -attr vt d
+load net {mux#18.itm(14)} -attr vt d
+load net {mux#18.itm(15)} -attr vt d
+load net {mux#18.itm(16)} -attr vt d
+load net {mux#18.itm(17)} -attr vt d
+load net {mux#18.itm(18)} -attr vt d
+load netBundle {mux#18.itm} 19 {mux#18.itm(0)} {mux#18.itm(1)} {mux#18.itm(2)} {mux#18.itm(3)} {mux#18.itm(4)} {mux#18.itm(5)} {mux#18.itm(6)} {mux#18.itm(7)} {mux#18.itm(8)} {mux#18.itm(9)} {mux#18.itm(10)} {mux#18.itm(11)} {mux#18.itm(12)} {mux#18.itm(13)} {mux#18.itm(14)} {mux#18.itm(15)} {mux#18.itm(16)} {mux#18.itm(17)} {mux#18.itm(18)} -attr xrf 33406 -attr oid 570 -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {FRAME:acc#15.itm(0)} -attr vt d
+load net {FRAME:acc#15.itm(1)} -attr vt d
+load net {FRAME:acc#15.itm(2)} -attr vt d
+load net {FRAME:acc#15.itm(3)} -attr vt d
+load net {FRAME:acc#15.itm(4)} -attr vt d
+load net {FRAME:acc#15.itm(5)} -attr vt d
+load net {FRAME:acc#15.itm(6)} -attr vt d
+load net {FRAME:acc#15.itm(7)} -attr vt d
+load net {FRAME:acc#15.itm(8)} -attr vt d
+load net {FRAME:acc#15.itm(9)} -attr vt d
+load net {FRAME:acc#15.itm(10)} -attr vt d
+load net {FRAME:acc#15.itm(11)} -attr vt d
+load netBundle {FRAME:acc#15.itm} 12 {FRAME:acc#15.itm(0)} {FRAME:acc#15.itm(1)} {FRAME:acc#15.itm(2)} {FRAME:acc#15.itm(3)} {FRAME:acc#15.itm(4)} {FRAME:acc#15.itm(5)} {FRAME:acc#15.itm(6)} {FRAME:acc#15.itm(7)} {FRAME:acc#15.itm(8)} {FRAME:acc#15.itm(9)} {FRAME:acc#15.itm(10)} {FRAME:acc#15.itm(11)} -attr xrf 33407 -attr oid 571 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:mul.itm(0)} -attr vt d
+load net {FRAME:mul.itm(1)} -attr vt d
+load net {FRAME:mul.itm(2)} -attr vt d
+load net {FRAME:mul.itm(3)} -attr vt d
+load net {FRAME:mul.itm(4)} -attr vt d
+load net {FRAME:mul.itm(5)} -attr vt d
+load net {FRAME:mul.itm(6)} -attr vt d
+load net {FRAME:mul.itm(7)} -attr vt d
+load net {FRAME:mul.itm(8)} -attr vt d
+load net {FRAME:mul.itm(9)} -attr vt d
+load net {FRAME:mul.itm(10)} -attr vt d
+load netBundle {FRAME:mul.itm} 11 {FRAME:mul.itm(0)} {FRAME:mul.itm(1)} {FRAME:mul.itm(2)} {FRAME:mul.itm(3)} {FRAME:mul.itm(4)} {FRAME:mul.itm(5)} {FRAME:mul.itm(6)} {FRAME:mul.itm(7)} {FRAME:mul.itm(8)} {FRAME:mul.itm(9)} {FRAME:mul.itm(10)} -attr xrf 33408 -attr oid 572 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {slc(intensity#2.sg1.sva)#12.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#12.itm(1)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#12.itm} 2 {slc(intensity#2.sg1.sva)#12.itm(0)} {slc(intensity#2.sg1.sva)#12.itm(1)} -attr xrf 33409 -attr oid 573 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#12.itm}
+load net {FRAME:acc#14.itm(0)} -attr vt d
+load net {FRAME:acc#14.itm(1)} -attr vt d
+load net {FRAME:acc#14.itm(2)} -attr vt d
+load net {FRAME:acc#14.itm(3)} -attr vt d
+load net {FRAME:acc#14.itm(4)} -attr vt d
+load net {FRAME:acc#14.itm(5)} -attr vt d
+load net {FRAME:acc#14.itm(6)} -attr vt d
+load net {FRAME:acc#14.itm(7)} -attr vt d
+load net {FRAME:acc#14.itm(8)} -attr vt d
+load net {FRAME:acc#14.itm(9)} -attr vt d
+load netBundle {FRAME:acc#14.itm} 10 {FRAME:acc#14.itm(0)} {FRAME:acc#14.itm(1)} {FRAME:acc#14.itm(2)} {FRAME:acc#14.itm(3)} {FRAME:acc#14.itm(4)} {FRAME:acc#14.itm(5)} {FRAME:acc#14.itm(6)} {FRAME:acc#14.itm(7)} {FRAME:acc#14.itm(8)} {FRAME:acc#14.itm(9)} -attr xrf 33410 -attr oid 574 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:mul#1.itm(0)} -attr vt d
+load net {FRAME:mul#1.itm(1)} -attr vt d
+load net {FRAME:mul#1.itm(2)} -attr vt d
+load net {FRAME:mul#1.itm(3)} -attr vt d
+load net {FRAME:mul#1.itm(4)} -attr vt d
+load net {FRAME:mul#1.itm(5)} -attr vt d
+load net {FRAME:mul#1.itm(6)} -attr vt d
+load net {FRAME:mul#1.itm(7)} -attr vt d
+load net {FRAME:mul#1.itm(8)} -attr vt d
+load netBundle {FRAME:mul#1.itm} 9 {FRAME:mul#1.itm(0)} {FRAME:mul#1.itm(1)} {FRAME:mul#1.itm(2)} {FRAME:mul#1.itm(3)} {FRAME:mul#1.itm(4)} {FRAME:mul#1.itm(5)} {FRAME:mul#1.itm(6)} {FRAME:mul#1.itm(7)} {FRAME:mul#1.itm(8)} -attr xrf 33411 -attr oid 575 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {slc(intensity#2.sg1.sva)#13.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#13.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#13.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#13.itm} 3 {slc(intensity#2.sg1.sva)#13.itm(0)} {slc(intensity#2.sg1.sva)#13.itm(1)} {slc(intensity#2.sg1.sva)#13.itm(2)} -attr xrf 33412 -attr oid 576 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#13.itm}
+load net {FRAME:acc#13.itm(0)} -attr vt d
+load net {FRAME:acc#13.itm(1)} -attr vt d
+load net {FRAME:acc#13.itm(2)} -attr vt d
+load net {FRAME:acc#13.itm(3)} -attr vt d
+load net {FRAME:acc#13.itm(4)} -attr vt d
+load net {FRAME:acc#13.itm(5)} -attr vt d
+load net {FRAME:acc#13.itm(6)} -attr vt d
+load net {FRAME:acc#13.itm(7)} -attr vt d
+load netBundle {FRAME:acc#13.itm} 8 {FRAME:acc#13.itm(0)} {FRAME:acc#13.itm(1)} {FRAME:acc#13.itm(2)} {FRAME:acc#13.itm(3)} {FRAME:acc#13.itm(4)} {FRAME:acc#13.itm(5)} {FRAME:acc#13.itm(6)} {FRAME:acc#13.itm(7)} -attr xrf 33413 -attr oid 577 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {slc(intensity#2.sg1.sva)#2.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#2.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#2.itm(2)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#2.itm(3)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#2.itm(4)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#2.itm} 6 {slc(intensity#2.sg1.sva)#2.itm(0)} {slc(intensity#2.sg1.sva)#2.itm(1)} {slc(intensity#2.sg1.sva)#2.itm(2)} {slc(intensity#2.sg1.sva)#2.itm(3)} {slc(intensity#2.sg1.sva)#2.itm(4)} {slc(intensity#2.sg1.sva)#2.itm(5)} -attr xrf 33414 -attr oid 578 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {FRAME:acc#12.itm(0)} -attr vt d
+load net {FRAME:acc#12.itm(1)} -attr vt d
+load net {FRAME:acc#12.itm(2)} -attr vt d
+load net {FRAME:acc#12.itm(3)} -attr vt d
+load net {FRAME:acc#12.itm(4)} -attr vt d
+load netBundle {FRAME:acc#12.itm} 5 {FRAME:acc#12.itm(0)} {FRAME:acc#12.itm(1)} {FRAME:acc#12.itm(2)} {FRAME:acc#12.itm(3)} {FRAME:acc#12.itm(4)} -attr xrf 33415 -attr oid 579 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#11.itm(0)} -attr vt d
+load net {FRAME:acc#11.itm(1)} -attr vt d
+load net {FRAME:acc#11.itm(2)} -attr vt d
+load net {FRAME:acc#11.itm(3)} -attr vt d
+load net {FRAME:acc#11.itm(4)} -attr vt d
+load netBundle {FRAME:acc#11.itm} 5 {FRAME:acc#11.itm(0)} {FRAME:acc#11.itm(1)} {FRAME:acc#11.itm(2)} {FRAME:acc#11.itm(3)} {FRAME:acc#11.itm(4)} -attr xrf 33416 -attr oid 580 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#10.itm(0)} -attr vt d
+load net {FRAME:acc#10.itm(1)} -attr vt d
+load net {FRAME:acc#10.itm(2)} -attr vt d
+load net {FRAME:acc#10.itm(3)} -attr vt d
+load netBundle {FRAME:acc#10.itm} 4 {FRAME:acc#10.itm(0)} {FRAME:acc#10.itm(1)} {FRAME:acc#10.itm(2)} {FRAME:acc#10.itm(3)} -attr xrf 33417 -attr oid 581 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {conc#677.itm(0)} -attr vt d
+load net {conc#677.itm(1)} -attr vt d
+load net {conc#677.itm(2)} -attr vt d
+load netBundle {conc#677.itm} 3 {conc#677.itm(0)} {conc#677.itm(1)} {conc#677.itm(2)} -attr xrf 33418 -attr oid 582 -attr vt d -attr @path {/sobel/sobel:core/conc#677.itm}
+load net {conc#678.itm(0)} -attr vt d
+load net {conc#678.itm(1)} -attr vt d
+load net {conc#678.itm(2)} -attr vt d
+load net {conc#678.itm(3)} -attr vt d
+load net {conc#678.itm(4)} -attr vt d
+load netBundle {conc#678.itm} 5 {conc#678.itm(0)} {conc#678.itm(1)} {conc#678.itm(2)} {conc#678.itm(3)} {conc#678.itm(4)} -attr xrf 33419 -attr oid 583 -attr vt d -attr @path {/sobel/sobel:core/conc#678.itm}
+load net {slc(acc.imod#12.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#12.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#12.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#12.sva)#1.itm} 3 {slc(acc.imod#12.sva)#1.itm(0)} {slc(acc.imod#12.sva)#1.itm(1)} {slc(acc.imod#12.sva)#1.itm(2)} -attr xrf 33420 -attr oid 584 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#1.itm}
+load net {FRAME:conc#15.itm(0)} -attr vt d
+load net {FRAME:conc#15.itm(1)} -attr vt d
+load net {FRAME:conc#15.itm(2)} -attr vt d
+load net {FRAME:conc#15.itm(3)} -attr vt d
+load netBundle {FRAME:conc#15.itm} 4 {FRAME:conc#15.itm(0)} {FRAME:conc#15.itm(1)} {FRAME:conc#15.itm(2)} {FRAME:conc#15.itm(3)} -attr xrf 33421 -attr oid 585 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(0)} -attr vt d
+load net {FRAME:not#5.itm(1)} -attr vt d
+load net {FRAME:not#5.itm(2)} -attr vt d
+load netBundle {FRAME:not#5.itm} 3 {FRAME:not#5.itm(0)} {FRAME:not#5.itm(1)} {FRAME:not#5.itm(2)} -attr xrf 33422 -attr oid 586 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {slc(acc.imod#12.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#12.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#12.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#12.sva)#2.itm} 3 {slc(acc.imod#12.sva)#2.itm(0)} {slc(acc.imod#12.sva)#2.itm(1)} {slc(acc.imod#12.sva)#2.itm(2)} -attr xrf 33423 -attr oid 587 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#2.itm}
+load net {slc(acc.imod#12.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#12.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#12.sva)#4.itm} 2 {slc(acc.imod#12.sva)#4.itm(0)} {slc(acc.imod#12.sva)#4.itm(1)} -attr xrf 33424 -attr oid 588 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#4.itm}
+load net {FRAME:not#6.itm(0)} -attr vt d
+load net {FRAME:not#6.itm(1)} -attr vt d
+load net {FRAME:not#6.itm(2)} -attr vt d
+load netBundle {FRAME:not#6.itm} 3 {FRAME:not#6.itm(0)} {FRAME:not#6.itm(1)} {FRAME:not#6.itm(2)} -attr xrf 33425 -attr oid 589 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {slc(intensity#2.sg1.sva)#7.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#7.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#7.itm} 3 {slc(intensity#2.sg1.sva)#7.itm(0)} {slc(intensity#2.sg1.sva)#7.itm(1)} {slc(intensity#2.sg1.sva)#7.itm(2)} -attr xrf 33426 -attr oid 590 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#7.itm}
+load net {conc#679.itm(0)} -attr vt d
+load net {conc#679.itm(1)} -attr vt d
+load net {conc#679.itm(2)} -attr vt d
+load net {conc#679.itm(3)} -attr vt d
+load net {conc#679.itm(4)} -attr vt d
+load netBundle {conc#679.itm} 5 {conc#679.itm(0)} {conc#679.itm(1)} {conc#679.itm(2)} {conc#679.itm(3)} {conc#679.itm(4)} -attr xrf 33427 -attr oid 591 -attr vt d -attr @path {/sobel/sobel:core/conc#679.itm}
+load net {exs#62.itm(0)} -attr vt d
+load net {exs#62.itm(1)} -attr vt d
+load net {exs#62.itm(2)} -attr vt d
+load net {exs#62.itm(3)} -attr vt d
+load net {exs#62.itm(4)} -attr vt d
+load net {exs#62.itm(5)} -attr vt d
+load net {exs#62.itm(6)} -attr vt d
+load net {exs#62.itm(7)} -attr vt d
+load net {exs#62.itm(8)} -attr vt d
+load net {exs#62.itm(9)} -attr vt d
+load net {exs#62.itm(10)} -attr vt d
+load netBundle {exs#62.itm} 11 {exs#62.itm(0)} {exs#62.itm(1)} {exs#62.itm(2)} {exs#62.itm(3)} {exs#62.itm(4)} {exs#62.itm(5)} {exs#62.itm(6)} {exs#62.itm(7)} {exs#62.itm(8)} {exs#62.itm(9)} {exs#62.itm(10)} -attr xrf 33428 -attr oid 592 -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {conc#680.itm(0)} -attr vt d
+load net {conc#680.itm(1)} -attr vt d
+load net {conc#680.itm(2)} -attr vt d
+load net {conc#680.itm(3)} -attr vt d
+load net {conc#680.itm(4)} -attr vt d
+load net {conc#680.itm(5)} -attr vt d
+load net {conc#680.itm(6)} -attr vt d
+load net {conc#680.itm(7)} -attr vt d
+load net {conc#680.itm(8)} -attr vt d
+load netBundle {conc#680.itm} 9 {conc#680.itm(0)} {conc#680.itm(1)} {conc#680.itm(2)} {conc#680.itm(3)} {conc#680.itm(4)} {conc#680.itm(5)} {conc#680.itm(6)} {conc#680.itm(7)} {conc#680.itm(8)} -attr xrf 33429 -attr oid 593 -attr vt d -attr @path {/sobel/sobel:core/conc#680.itm}
+load net {FRAME:exs#5.itm(0)} -attr vt d
+load net {FRAME:exs#5.itm(1)} -attr vt d
+load net {FRAME:exs#5.itm(2)} -attr vt d
+load netBundle {FRAME:exs#5.itm} 3 {FRAME:exs#5.itm(0)} {FRAME:exs#5.itm(1)} {FRAME:exs#5.itm(2)} -attr xrf 33430 -attr oid 594 -attr vt d -attr @path {/sobel/sobel:core/FRAME:exs#5.itm}
+load net {ACC1:acc.itm(0)} -attr vt d
+load net {ACC1:acc.itm(1)} -attr vt d
+load net {ACC1:acc.itm(2)} -attr vt d
+load net {ACC1:acc.itm(3)} -attr vt d
+load net {ACC1:acc.itm(4)} -attr vt d
+load net {ACC1:acc.itm(5)} -attr vt d
+load net {ACC1:acc.itm(6)} -attr vt d
+load net {ACC1:acc.itm(7)} -attr vt d
+load net {ACC1:acc.itm(8)} -attr vt d
+load net {ACC1:acc.itm(9)} -attr vt d
+load net {ACC1:acc.itm(10)} -attr vt d
+load net {ACC1:acc.itm(11)} -attr vt d
+load net {ACC1:acc.itm(12)} -attr vt d
+load net {ACC1:acc.itm(13)} -attr vt d
+load net {ACC1:acc.itm(14)} -attr vt d
+load net {ACC1:acc.itm(15)} -attr vt d
+load netBundle {ACC1:acc.itm} 16 {ACC1:acc.itm(0)} {ACC1:acc.itm(1)} {ACC1:acc.itm(2)} {ACC1:acc.itm(3)} {ACC1:acc.itm(4)} {ACC1:acc.itm(5)} {ACC1:acc.itm(6)} {ACC1:acc.itm(7)} {ACC1:acc.itm(8)} {ACC1:acc.itm(9)} {ACC1:acc.itm(10)} {ACC1:acc.itm(11)} {ACC1:acc.itm(12)} {ACC1:acc.itm(13)} {ACC1:acc.itm(14)} {ACC1:acc.itm(15)} -attr xrf 33431 -attr oid 595 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc#342.itm(0)} -attr vt d
+load net {ACC1:acc#342.itm(1)} -attr vt d
+load net {ACC1:acc#342.itm(2)} -attr vt d
+load net {ACC1:acc#342.itm(3)} -attr vt d
+load net {ACC1:acc#342.itm(4)} -attr vt d
+load net {ACC1:acc#342.itm(5)} -attr vt d
+load net {ACC1:acc#342.itm(6)} -attr vt d
+load net {ACC1:acc#342.itm(7)} -attr vt d
+load net {ACC1:acc#342.itm(8)} -attr vt d
+load net {ACC1:acc#342.itm(9)} -attr vt d
+load net {ACC1:acc#342.itm(10)} -attr vt d
+load net {ACC1:acc#342.itm(11)} -attr vt d
+load net {ACC1:acc#342.itm(12)} -attr vt d
+load net {ACC1:acc#342.itm(13)} -attr vt d
+load net {ACC1:acc#342.itm(14)} -attr vt d
+load net {ACC1:acc#342.itm(15)} -attr vt d
+load netBundle {ACC1:acc#342.itm} 16 {ACC1:acc#342.itm(0)} {ACC1:acc#342.itm(1)} {ACC1:acc#342.itm(2)} {ACC1:acc#342.itm(3)} {ACC1:acc#342.itm(4)} {ACC1:acc#342.itm(5)} {ACC1:acc#342.itm(6)} {ACC1:acc#342.itm(7)} {ACC1:acc#342.itm(8)} {ACC1:acc#342.itm(9)} {ACC1:acc#342.itm(10)} {ACC1:acc#342.itm(11)} {ACC1:acc#342.itm(12)} {ACC1:acc#342.itm(13)} {ACC1:acc#342.itm(14)} {ACC1:acc#342.itm(15)} -attr xrf 33432 -attr oid 596 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {FRAME:acc#9.itm(0)} -attr vt d
+load net {FRAME:acc#9.itm(1)} -attr vt d
+load net {FRAME:acc#9.itm(2)} -attr vt d
+load net {FRAME:acc#9.itm(3)} -attr vt d
+load net {FRAME:acc#9.itm(4)} -attr vt d
+load net {FRAME:acc#9.itm(5)} -attr vt d
+load netBundle {FRAME:acc#9.itm} 6 {FRAME:acc#9.itm(0)} {FRAME:acc#9.itm(1)} {FRAME:acc#9.itm(2)} {FRAME:acc#9.itm(3)} {FRAME:acc#9.itm(4)} {FRAME:acc#9.itm(5)} -attr xrf 33433 -attr oid 597 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#8.itm(0)} -attr vt d
+load net {FRAME:acc#8.itm(1)} -attr vt d
+load net {FRAME:acc#8.itm(2)} -attr vt d
+load net {FRAME:acc#8.itm(3)} -attr vt d
+load net {FRAME:acc#8.itm(4)} -attr vt d
+load netBundle {FRAME:acc#8.itm} 5 {FRAME:acc#8.itm(0)} {FRAME:acc#8.itm(1)} {FRAME:acc#8.itm(2)} {FRAME:acc#8.itm(3)} {FRAME:acc#8.itm(4)} -attr xrf 33434 -attr oid 598 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#6.itm(0)} -attr vt d
+load net {FRAME:acc#6.itm(1)} -attr vt d
+load net {FRAME:acc#6.itm(2)} -attr vt d
+load net {FRAME:acc#6.itm(3)} -attr vt d
+load netBundle {FRAME:acc#6.itm} 4 {FRAME:acc#6.itm(0)} {FRAME:acc#6.itm(1)} {FRAME:acc#6.itm(2)} {FRAME:acc#6.itm(3)} -attr xrf 33435 -attr oid 599 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {slc(intensity#2.sg1.sva)#3.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#3.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#3.itm} 3 {slc(intensity#2.sg1.sva)#3.itm(0)} {slc(intensity#2.sg1.sva)#3.itm(1)} {slc(intensity#2.sg1.sva)#3.itm(2)} -attr xrf 33436 -attr oid 600 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#3.itm}
+load net {FRAME:not#2.itm(0)} -attr vt d
+load net {FRAME:not#2.itm(1)} -attr vt d
+load net {FRAME:not#2.itm(2)} -attr vt d
+load netBundle {FRAME:not#2.itm} 3 {FRAME:not#2.itm(0)} {FRAME:not#2.itm(1)} {FRAME:not#2.itm(2)} -attr xrf 33437 -attr oid 601 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {slc(intensity#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#1.itm} 3 {slc(intensity#2.sg1.sva)#1.itm(0)} {slc(intensity#2.sg1.sva)#1.itm(1)} {slc(intensity#2.sg1.sva)#1.itm(2)} -attr xrf 33438 -attr oid 602 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#1.itm}
+load net {FRAME:acc#5.itm(0)} -attr vt d
+load net {FRAME:acc#5.itm(1)} -attr vt d
+load net {FRAME:acc#5.itm(2)} -attr vt d
+load net {FRAME:acc#5.itm(3)} -attr vt d
+load netBundle {FRAME:acc#5.itm} 4 {FRAME:acc#5.itm(0)} {FRAME:acc#5.itm(1)} {FRAME:acc#5.itm(2)} {FRAME:acc#5.itm(3)} -attr xrf 33439 -attr oid 603 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {conc#682.itm(0)} -attr vt d
+load net {conc#682.itm(1)} -attr vt d
+load net {conc#682.itm(2)} -attr vt d
+load netBundle {conc#682.itm} 3 {conc#682.itm(0)} {conc#682.itm(1)} {conc#682.itm(2)} -attr xrf 33440 -attr oid 604 -attr vt d -attr @path {/sobel/sobel:core/conc#682.itm}
+load net {slc(intensity#2.sg1.sva).itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva).itm(1)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva).itm} 2 {slc(intensity#2.sg1.sva).itm(0)} {slc(intensity#2.sg1.sva).itm(1)} -attr xrf 33441 -attr oid 605 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva).itm}
+load net {FRAME:acc#7.itm(0)} -attr vt d
+load net {FRAME:acc#7.itm(1)} -attr vt d
+load net {FRAME:acc#7.itm(2)} -attr vt d
+load net {FRAME:acc#7.itm(3)} -attr vt d
+load netBundle {FRAME:acc#7.itm} 4 {FRAME:acc#7.itm(0)} {FRAME:acc#7.itm(1)} {FRAME:acc#7.itm(2)} {FRAME:acc#7.itm(3)} -attr xrf 33442 -attr oid 606 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {slc(intensity#2.sg1.sva)#5.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#5.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#5.itm} 3 {slc(intensity#2.sg1.sva)#5.itm(0)} {slc(intensity#2.sg1.sva)#5.itm(1)} {slc(intensity#2.sg1.sva)#5.itm(2)} -attr xrf 33443 -attr oid 607 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#5.itm}
+load net {FRAME:not#1.itm(0)} -attr vt d
+load net {FRAME:not#1.itm(1)} -attr vt d
+load net {FRAME:not#1.itm(2)} -attr vt d
+load netBundle {FRAME:not#1.itm} 3 {FRAME:not#1.itm(0)} {FRAME:not#1.itm(1)} {FRAME:not#1.itm(2)} -attr xrf 33444 -attr oid 608 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {slc(intensity#2.sg1.sva)#6.itm(0)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#6.itm(1)} -attr vt d
+load net {slc(intensity#2.sg1.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(intensity#2.sg1.sva)#6.itm} 3 {slc(intensity#2.sg1.sva)#6.itm(0)} {slc(intensity#2.sg1.sva)#6.itm(1)} {slc(intensity#2.sg1.sva)#6.itm(2)} -attr xrf 33445 -attr oid 609 -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#6.itm}
+load net {FRAME:for:mux#12.itm(0)} -attr vt d
+load net {FRAME:for:mux#12.itm(1)} -attr vt d
+load net {FRAME:for:mux#12.itm(2)} -attr vt d
+load net {FRAME:for:mux#12.itm(3)} -attr vt d
+load net {FRAME:for:mux#12.itm(4)} -attr vt d
+load net {FRAME:for:mux#12.itm(5)} -attr vt d
+load net {FRAME:for:mux#12.itm(6)} -attr vt d
+load net {FRAME:for:mux#12.itm(7)} -attr vt d
+load net {FRAME:for:mux#12.itm(8)} -attr vt d
+load net {FRAME:for:mux#12.itm(9)} -attr vt d
+load net {FRAME:for:mux#12.itm(10)} -attr vt d
+load net {FRAME:for:mux#12.itm(11)} -attr vt d
+load net {FRAME:for:mux#12.itm(12)} -attr vt d
+load net {FRAME:for:mux#12.itm(13)} -attr vt d
+load net {FRAME:for:mux#12.itm(14)} -attr vt d
+load net {FRAME:for:mux#12.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#12.itm} 16 {FRAME:for:mux#12.itm(0)} {FRAME:for:mux#12.itm(1)} {FRAME:for:mux#12.itm(2)} {FRAME:for:mux#12.itm(3)} {FRAME:for:mux#12.itm(4)} {FRAME:for:mux#12.itm(5)} {FRAME:for:mux#12.itm(6)} {FRAME:for:mux#12.itm(7)} {FRAME:for:mux#12.itm(8)} {FRAME:for:mux#12.itm(9)} {FRAME:for:mux#12.itm(10)} {FRAME:for:mux#12.itm(11)} {FRAME:for:mux#12.itm(12)} {FRAME:for:mux#12.itm(13)} {FRAME:for:mux#12.itm(14)} {FRAME:for:mux#12.itm(15)} -attr xrf 33446 -attr oid 610 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:exs#21.itm(0)} -attr vt d
+load net {FRAME:for:exs#21.itm(1)} -attr vt d
+load net {FRAME:for:exs#21.itm(2)} -attr vt d
+load net {FRAME:for:exs#21.itm(3)} -attr vt d
+load net {FRAME:for:exs#21.itm(4)} -attr vt d
+load net {FRAME:for:exs#21.itm(5)} -attr vt d
+load net {FRAME:for:exs#21.itm(6)} -attr vt d
+load net {FRAME:for:exs#21.itm(7)} -attr vt d
+load net {FRAME:for:exs#21.itm(8)} -attr vt d
+load net {FRAME:for:exs#21.itm(9)} -attr vt d
+load net {FRAME:for:exs#21.itm(10)} -attr vt d
+load net {FRAME:for:exs#21.itm(11)} -attr vt d
+load net {FRAME:for:exs#21.itm(12)} -attr vt d
+load net {FRAME:for:exs#21.itm(13)} -attr vt d
+load net {FRAME:for:exs#21.itm(14)} -attr vt d
+load net {FRAME:for:exs#21.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#21.itm} 16 {FRAME:for:exs#21.itm(0)} {FRAME:for:exs#21.itm(1)} {FRAME:for:exs#21.itm(2)} {FRAME:for:exs#21.itm(3)} {FRAME:for:exs#21.itm(4)} {FRAME:for:exs#21.itm(5)} {FRAME:for:exs#21.itm(6)} {FRAME:for:exs#21.itm(7)} {FRAME:for:exs#21.itm(8)} {FRAME:for:exs#21.itm(9)} {FRAME:for:exs#21.itm(10)} {FRAME:for:exs#21.itm(11)} {FRAME:for:exs#21.itm(12)} {FRAME:for:exs#21.itm(13)} {FRAME:for:exs#21.itm(14)} {FRAME:for:exs#21.itm(15)} -attr xrf 33447 -attr oid 611 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:mux#11.itm(0)} -attr vt d
+load net {FRAME:for:mux#11.itm(1)} -attr vt d
+load net {FRAME:for:mux#11.itm(2)} -attr vt d
+load net {FRAME:for:mux#11.itm(3)} -attr vt d
+load net {FRAME:for:mux#11.itm(4)} -attr vt d
+load net {FRAME:for:mux#11.itm(5)} -attr vt d
+load net {FRAME:for:mux#11.itm(6)} -attr vt d
+load net {FRAME:for:mux#11.itm(7)} -attr vt d
+load net {FRAME:for:mux#11.itm(8)} -attr vt d
+load net {FRAME:for:mux#11.itm(9)} -attr vt d
+load net {FRAME:for:mux#11.itm(10)} -attr vt d
+load net {FRAME:for:mux#11.itm(11)} -attr vt d
+load net {FRAME:for:mux#11.itm(12)} -attr vt d
+load net {FRAME:for:mux#11.itm(13)} -attr vt d
+load net {FRAME:for:mux#11.itm(14)} -attr vt d
+load net {FRAME:for:mux#11.itm(15)} -attr vt d
+load netBundle {FRAME:for:mux#11.itm} 16 {FRAME:for:mux#11.itm(0)} {FRAME:for:mux#11.itm(1)} {FRAME:for:mux#11.itm(2)} {FRAME:for:mux#11.itm(3)} {FRAME:for:mux#11.itm(4)} {FRAME:for:mux#11.itm(5)} {FRAME:for:mux#11.itm(6)} {FRAME:for:mux#11.itm(7)} {FRAME:for:mux#11.itm(8)} {FRAME:for:mux#11.itm(9)} {FRAME:for:mux#11.itm(10)} {FRAME:for:mux#11.itm(11)} {FRAME:for:mux#11.itm(12)} {FRAME:for:mux#11.itm(13)} {FRAME:for:mux#11.itm(14)} {FRAME:for:mux#11.itm(15)} -attr xrf 33448 -attr oid 612 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:exs#20.itm(0)} -attr vt d
+load net {FRAME:for:exs#20.itm(1)} -attr vt d
+load net {FRAME:for:exs#20.itm(2)} -attr vt d
+load net {FRAME:for:exs#20.itm(3)} -attr vt d
+load net {FRAME:for:exs#20.itm(4)} -attr vt d
+load net {FRAME:for:exs#20.itm(5)} -attr vt d
+load net {FRAME:for:exs#20.itm(6)} -attr vt d
+load net {FRAME:for:exs#20.itm(7)} -attr vt d
+load net {FRAME:for:exs#20.itm(8)} -attr vt d
+load net {FRAME:for:exs#20.itm(9)} -attr vt d
+load net {FRAME:for:exs#20.itm(10)} -attr vt d
+load net {FRAME:for:exs#20.itm(11)} -attr vt d
+load net {FRAME:for:exs#20.itm(12)} -attr vt d
+load net {FRAME:for:exs#20.itm(13)} -attr vt d
+load net {FRAME:for:exs#20.itm(14)} -attr vt d
+load net {FRAME:for:exs#20.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#20.itm} 16 {FRAME:for:exs#20.itm(0)} {FRAME:for:exs#20.itm(1)} {FRAME:for:exs#20.itm(2)} {FRAME:for:exs#20.itm(3)} {FRAME:for:exs#20.itm(4)} {FRAME:for:exs#20.itm(5)} {FRAME:for:exs#20.itm(6)} {FRAME:for:exs#20.itm(7)} {FRAME:for:exs#20.itm(8)} {FRAME:for:exs#20.itm(9)} {FRAME:for:exs#20.itm(10)} {FRAME:for:exs#20.itm(11)} {FRAME:for:exs#20.itm(12)} {FRAME:for:exs#20.itm(13)} {FRAME:for:exs#20.itm(14)} {FRAME:for:exs#20.itm(15)} -attr xrf 33449 -attr oid 613 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:exs#19.itm(0)} -attr vt d
+load net {FRAME:for:exs#19.itm(1)} -attr vt d
+load netBundle {FRAME:for:exs#19.itm} 2 {FRAME:for:exs#19.itm(0)} {FRAME:for:exs#19.itm(1)} -attr xrf 33450 -attr oid 614 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#19.itm}
+load net {slc(ACC1:acc#110.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#110.psp#1.sva).itm(1)} -attr vt d
+load net {slc(ACC1:acc#110.psp#1.sva).itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#110.psp#1.sva).itm} 3 {slc(ACC1:acc#110.psp#1.sva).itm(0)} {slc(ACC1:acc#110.psp#1.sva).itm(1)} {slc(ACC1:acc#110.psp#1.sva).itm(2)} -attr xrf 33451 -attr oid 615 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.sva).itm}
+load net {slc(ACC1:acc#118.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#118.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#118.psp.sva).itm} 2 {slc(ACC1:acc#118.psp.sva).itm(0)} {slc(ACC1:acc#118.psp.sva).itm(1)} -attr xrf 33452 -attr oid 616 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp.sva).itm}
+load net {slc(regs.regs(1).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(9)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(10)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(11)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(12)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(13)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(14)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(15)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(16)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(17)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(18)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(19)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(20)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(21)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(22)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(23)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(24)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(25)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(26)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(27)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(28)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(29)} -attr vt d
+load netBundle {slc(regs.regs(1).sva).itm} 30 {slc(regs.regs(1).sva).itm(0)} {slc(regs.regs(1).sva).itm(1)} {slc(regs.regs(1).sva).itm(2)} {slc(regs.regs(1).sva).itm(3)} {slc(regs.regs(1).sva).itm(4)} {slc(regs.regs(1).sva).itm(5)} {slc(regs.regs(1).sva).itm(6)} {slc(regs.regs(1).sva).itm(7)} {slc(regs.regs(1).sva).itm(8)} {slc(regs.regs(1).sva).itm(9)} {slc(regs.regs(1).sva).itm(10)} {slc(regs.regs(1).sva).itm(11)} {slc(regs.regs(1).sva).itm(12)} {slc(regs.regs(1).sva).itm(13)} {slc(regs.regs(1).sva).itm(14)} {slc(regs.regs(1).sva).itm(15)} {slc(regs.regs(1).sva).itm(16)} {slc(regs.regs(1).sva).itm(17)} {slc(regs.regs(1).sva).itm(18)} {slc(regs.regs(1).sva).itm(19)} {slc(regs.regs(1).sva).itm(20)} {slc(regs.regs(1).sva).itm(21)} {slc(regs.regs(1).sva).itm(22)} {slc(regs.regs(1).sva).itm(23)} {slc(regs.regs(1).sva).itm(24)} {slc(regs.regs(1).sva).itm(25)} {slc(regs.regs(1).sva).itm(26)} {slc(regs.regs(1).sva).itm(27)} {slc(regs.regs(1).sva).itm(28)} {slc(regs.regs(1).sva).itm(29)} -attr xrf 33453 -attr oid 617 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {slc(regs.regs(1).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(9)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(10)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(11)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(12)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(13)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(14)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(15)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(16)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(17)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(18)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(19)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(20)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(21)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(22)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(23)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(24)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(25)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(26)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(27)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(28)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(29)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#1.itm} 30 {slc(regs.regs(1).sva)#1.itm(0)} {slc(regs.regs(1).sva)#1.itm(1)} {slc(regs.regs(1).sva)#1.itm(2)} {slc(regs.regs(1).sva)#1.itm(3)} {slc(regs.regs(1).sva)#1.itm(4)} {slc(regs.regs(1).sva)#1.itm(5)} {slc(regs.regs(1).sva)#1.itm(6)} {slc(regs.regs(1).sva)#1.itm(7)} {slc(regs.regs(1).sva)#1.itm(8)} {slc(regs.regs(1).sva)#1.itm(9)} {slc(regs.regs(1).sva)#1.itm(10)} {slc(regs.regs(1).sva)#1.itm(11)} {slc(regs.regs(1).sva)#1.itm(12)} {slc(regs.regs(1).sva)#1.itm(13)} {slc(regs.regs(1).sva)#1.itm(14)} {slc(regs.regs(1).sva)#1.itm(15)} {slc(regs.regs(1).sva)#1.itm(16)} {slc(regs.regs(1).sva)#1.itm(17)} {slc(regs.regs(1).sva)#1.itm(18)} {slc(regs.regs(1).sva)#1.itm(19)} {slc(regs.regs(1).sva)#1.itm(20)} {slc(regs.regs(1).sva)#1.itm(21)} {slc(regs.regs(1).sva)#1.itm(22)} {slc(regs.regs(1).sva)#1.itm(23)} {slc(regs.regs(1).sva)#1.itm(24)} {slc(regs.regs(1).sva)#1.itm(25)} {slc(regs.regs(1).sva)#1.itm(26)} {slc(regs.regs(1).sva)#1.itm(27)} {slc(regs.regs(1).sva)#1.itm(28)} {slc(regs.regs(1).sva)#1.itm(29)} -attr xrf 33454 -attr oid 618 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {ACC1:slc#45.itm(0)} -attr vt d
+load net {ACC1:slc#45.itm(1)} -attr vt d
+load netBundle {ACC1:slc#45.itm} 2 {ACC1:slc#45.itm(0)} {ACC1:slc#45.itm(1)} -attr xrf 33455 -attr oid 619 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#45.itm}
+load net {ACC1:acc#179.itm(0)} -attr vt d
+load net {ACC1:acc#179.itm(1)} -attr vt d
+load net {ACC1:acc#179.itm(2)} -attr vt d
+load netBundle {ACC1:acc#179.itm} 3 {ACC1:acc#179.itm(0)} {ACC1:acc#179.itm(1)} {ACC1:acc#179.itm(2)} -attr xrf 33456 -attr oid 620 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {conc#683.itm(0)} -attr vt d
+load net {conc#683.itm(1)} -attr vt d
+load net {conc#683.itm(2)} -attr vt d
+load netBundle {conc#683.itm} 3 {conc#683.itm(0)} {conc#683.itm(1)} {conc#683.itm(2)} -attr xrf 33457 -attr oid 621 -attr vt d -attr @path {/sobel/sobel:core/conc#683.itm}
+load net {ACC1:conc#531.itm(0)} -attr vt d
+load net {ACC1:conc#531.itm(1)} -attr vt d
+load netBundle {ACC1:conc#531.itm} 2 {ACC1:conc#531.itm(0)} {ACC1:conc#531.itm(1)} -attr xrf 33458 -attr oid 622 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#531.itm}
+load net {slc(acc.imod#6.sva)#3.itm(0)} -attr vt d
+load net {slc(acc.imod#6.sva)#3.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#6.sva)#3.itm} 2 {slc(acc.imod#6.sva)#3.itm(0)} {slc(acc.imod#6.sva)#3.itm(1)} -attr xrf 33459 -attr oid 623 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#3.itm}
+load net {ACC1:acc#150.itm(0)} -attr vt d
+load net {ACC1:acc#150.itm(1)} -attr vt d
+load net {ACC1:acc#150.itm(2)} -attr vt d
+load net {ACC1:acc#150.itm(3)} -attr vt d
+load netBundle {ACC1:acc#150.itm} 4 {ACC1:acc#150.itm(0)} {ACC1:acc#150.itm(1)} {ACC1:acc#150.itm(2)} {ACC1:acc#150.itm(3)} -attr xrf 33460 -attr oid 624 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load net {conc#684.itm(0)} -attr vt d
+load net {conc#684.itm(1)} -attr vt d
+load net {conc#684.itm(2)} -attr vt d
+load netBundle {conc#684.itm} 3 {conc#684.itm(0)} {conc#684.itm(1)} {conc#684.itm(2)} -attr xrf 33461 -attr oid 625 -attr vt d -attr @path {/sobel/sobel:core/conc#684.itm}
+load net {ACC1-1:not#147.itm(0)} -attr vt d
+load net {ACC1-1:not#147.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#147.itm} 2 {ACC1-1:not#147.itm(0)} {ACC1-1:not#147.itm(1)} -attr xrf 33462 -attr oid 626 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#147.itm}
+load net {slc(ACC1:acc#118.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#118.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#118.psp#1.sva).itm} 2 {slc(ACC1:acc#118.psp#1.sva).itm(0)} {slc(ACC1:acc#118.psp#1.sva).itm(1)} -attr xrf 33463 -attr oid 627 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp#1.sva).itm}
+load net {conc#685.itm(0)} -attr vt d
+load net {conc#685.itm(1)} -attr vt d
+load netBundle {conc#685.itm} 2 {conc#685.itm(0)} {conc#685.itm(1)} -attr xrf 33464 -attr oid 628 -attr vt d -attr @path {/sobel/sobel:core/conc#685.itm}
+load net {ACC1:slc#19.itm(0)} -attr vt d
+load net {ACC1:slc#19.itm(1)} -attr vt d
+load netBundle {ACC1:slc#19.itm} 2 {ACC1:slc#19.itm(0)} {ACC1:slc#19.itm(1)} -attr xrf 33465 -attr oid 629 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#19.itm}
+load net {ACC1:acc#149.itm(0)} -attr vt d
+load net {ACC1:acc#149.itm(1)} -attr vt d
+load net {ACC1:acc#149.itm(2)} -attr vt d
+load netBundle {ACC1:acc#149.itm} 3 {ACC1:acc#149.itm(0)} {ACC1:acc#149.itm(1)} {ACC1:acc#149.itm(2)} -attr xrf 33466 -attr oid 630 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149.itm}
+load net {conc#686.itm(0)} -attr vt d
+load net {conc#686.itm(1)} -attr vt d
+load netBundle {conc#686.itm} 2 {conc#686.itm(0)} {conc#686.itm(1)} -attr xrf 33467 -attr oid 631 -attr vt d -attr @path {/sobel/sobel:core/conc#686.itm}
+load net {ACC1:conc#472.itm(0)} -attr vt d
+load net {ACC1:conc#472.itm(1)} -attr vt d
+load netBundle {ACC1:conc#472.itm} 2 {ACC1:conc#472.itm(0)} {ACC1:conc#472.itm(1)} -attr xrf 33468 -attr oid 632 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#472.itm}
+load net {ACC1:acc#148.itm(0)} -attr vt d
+load net {ACC1:acc#148.itm(1)} -attr vt d
+load net {ACC1:acc#148.itm(2)} -attr vt d
+load net {ACC1:acc#148.itm(3)} -attr vt d
+load net {ACC1:acc#148.itm(4)} -attr vt d
+load netBundle {ACC1:acc#148.itm} 5 {ACC1:acc#148.itm(0)} {ACC1:acc#148.itm(1)} {ACC1:acc#148.itm(2)} {ACC1:acc#148.itm(3)} {ACC1:acc#148.itm(4)} -attr xrf 33469 -attr oid 633 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {conc#687.itm(0)} -attr vt d
+load net {conc#687.itm(1)} -attr vt d
+load net {conc#687.itm(2)} -attr vt d
+load net {conc#687.itm(3)} -attr vt d
+load netBundle {conc#687.itm} 4 {conc#687.itm(0)} {conc#687.itm(1)} {conc#687.itm(2)} {conc#687.itm(3)} -attr xrf 33470 -attr oid 634 -attr vt d -attr @path {/sobel/sobel:core/conc#687.itm}
+load net {ACC1:slc#17.itm(0)} -attr vt d
+load net {ACC1:slc#17.itm(1)} -attr vt d
+load net {ACC1:slc#17.itm(2)} -attr vt d
+load netBundle {ACC1:slc#17.itm} 3 {ACC1:slc#17.itm(0)} {ACC1:slc#17.itm(1)} {ACC1:slc#17.itm(2)} -attr xrf 33471 -attr oid 635 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#17.itm}
+load net {ACC1:acc#147.itm(0)} -attr vt d
+load net {ACC1:acc#147.itm(1)} -attr vt d
+load net {ACC1:acc#147.itm(2)} -attr vt d
+load net {ACC1:acc#147.itm(3)} -attr vt d
+load netBundle {ACC1:acc#147.itm} 4 {ACC1:acc#147.itm(0)} {ACC1:acc#147.itm(1)} {ACC1:acc#147.itm(2)} {ACC1:acc#147.itm(3)} -attr xrf 33472 -attr oid 636 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load net {conc#688.itm(0)} -attr vt d
+load net {conc#688.itm(1)} -attr vt d
+load net {conc#688.itm(2)} -attr vt d
+load net {conc#688.itm(3)} -attr vt d
+load netBundle {conc#688.itm} 4 {conc#688.itm(0)} {conc#688.itm(1)} {conc#688.itm(2)} {conc#688.itm(3)} -attr xrf 33473 -attr oid 637 -attr vt d -attr @path {/sobel/sobel:core/conc#688.itm}
+load net {ACC1:conc#468.itm(0)} -attr vt d
+load net {ACC1:conc#468.itm(1)} -attr vt d
+load net {ACC1:conc#468.itm(2)} -attr vt d
+load netBundle {ACC1:conc#468.itm} 3 {ACC1:conc#468.itm(0)} {ACC1:conc#468.itm(1)} {ACC1:conc#468.itm(2)} -attr xrf 33474 -attr oid 638 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#468.itm}
+load net {ACC1:slc#15.itm(0)} -attr vt d
+load net {ACC1:slc#15.itm(1)} -attr vt d
+load netBundle {ACC1:slc#15.itm} 2 {ACC1:slc#15.itm(0)} {ACC1:slc#15.itm(1)} -attr xrf 33475 -attr oid 639 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#15.itm}
+load net {ACC1:acc#145.itm(0)} -attr vt d
+load net {ACC1:acc#145.itm(1)} -attr vt d
+load net {ACC1:acc#145.itm(2)} -attr vt d
+load netBundle {ACC1:acc#145.itm} 3 {ACC1:acc#145.itm(0)} {ACC1:acc#145.itm(1)} {ACC1:acc#145.itm(2)} -attr xrf 33476 -attr oid 640 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145.itm}
+load net {conc#689.itm(0)} -attr vt d
+load net {conc#689.itm(1)} -attr vt d
+load netBundle {conc#689.itm} 2 {conc#689.itm(0)} {conc#689.itm(1)} -attr xrf 33477 -attr oid 641 -attr vt d -attr @path {/sobel/sobel:core/conc#689.itm}
+load net {ACC1:conc#464.itm(0)} -attr vt d
+load net {ACC1:conc#464.itm(1)} -attr vt d
+load netBundle {ACC1:conc#464.itm} 2 {ACC1:conc#464.itm(0)} {ACC1:conc#464.itm(1)} -attr xrf 33478 -attr oid 642 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#464.itm}
+load net {ACC1:conc#470.itm(0)} -attr vt d
+load net {ACC1:conc#470.itm(1)} -attr vt d
+load net {ACC1:conc#470.itm(2)} -attr vt d
+load net {ACC1:conc#470.itm(3)} -attr vt d
+load net {ACC1:conc#470.itm(4)} -attr vt d
+load netBundle {ACC1:conc#470.itm} 5 {ACC1:conc#470.itm(0)} {ACC1:conc#470.itm(1)} {ACC1:conc#470.itm(2)} {ACC1:conc#470.itm(3)} {ACC1:conc#470.itm(4)} -attr xrf 33479 -attr oid 643 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#470.itm}
+load net {ACC1:slc#16.itm(0)} -attr vt d
+load net {ACC1:slc#16.itm(1)} -attr vt d
+load net {ACC1:slc#16.itm(2)} -attr vt d
+load net {ACC1:slc#16.itm(3)} -attr vt d
+load netBundle {ACC1:slc#16.itm} 4 {ACC1:slc#16.itm(0)} {ACC1:slc#16.itm(1)} {ACC1:slc#16.itm(2)} {ACC1:slc#16.itm(3)} -attr xrf 33480 -attr oid 644 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#16.itm}
+load net {ACC1:acc#146.itm(0)} -attr vt d
+load net {ACC1:acc#146.itm(1)} -attr vt d
+load net {ACC1:acc#146.itm(2)} -attr vt d
+load net {ACC1:acc#146.itm(3)} -attr vt d
+load net {ACC1:acc#146.itm(4)} -attr vt d
+load netBundle {ACC1:acc#146.itm} 5 {ACC1:acc#146.itm(0)} {ACC1:acc#146.itm(1)} {ACC1:acc#146.itm(2)} {ACC1:acc#146.itm(3)} {ACC1:acc#146.itm(4)} -attr xrf 33481 -attr oid 645 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {conc#690.itm(0)} -attr vt d
+load net {conc#690.itm(1)} -attr vt d
+load net {conc#690.itm(2)} -attr vt d
+load netBundle {conc#690.itm} 3 {conc#690.itm(0)} {conc#690.itm(1)} {conc#690.itm(2)} -attr xrf 33482 -attr oid 646 -attr vt d -attr @path {/sobel/sobel:core/conc#690.itm}
+load net {ACC1:slc#14.itm(0)} -attr vt d
+load net {ACC1:slc#14.itm(1)} -attr vt d
+load netBundle {ACC1:slc#14.itm} 2 {ACC1:slc#14.itm(0)} {ACC1:slc#14.itm(1)} -attr xrf 33483 -attr oid 647 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#14.itm}
+load net {ACC1:acc#144.itm(0)} -attr vt d
+load net {ACC1:acc#144.itm(1)} -attr vt d
+load net {ACC1:acc#144.itm(2)} -attr vt d
+load netBundle {ACC1:acc#144.itm} 3 {ACC1:acc#144.itm(0)} {ACC1:acc#144.itm(1)} {ACC1:acc#144.itm(2)} -attr xrf 33484 -attr oid 648 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144.itm}
+load net {conc#691.itm(0)} -attr vt d
+load net {conc#691.itm(1)} -attr vt d
+load netBundle {conc#691.itm} 2 {conc#691.itm(0)} {conc#691.itm(1)} -attr xrf 33485 -attr oid 649 -attr vt d -attr @path {/sobel/sobel:core/conc#691.itm}
+load net {ACC1:conc#462.itm(0)} -attr vt d
+load net {ACC1:conc#462.itm(1)} -attr vt d
+load netBundle {ACC1:conc#462.itm} 2 {ACC1:conc#462.itm(0)} {ACC1:conc#462.itm(1)} -attr xrf 33486 -attr oid 650 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#462.itm}
+load net {ACC1:conc#466.itm(0)} -attr vt d
+load net {ACC1:conc#466.itm(1)} -attr vt d
+load net {ACC1:conc#466.itm(2)} -attr vt d
+load netBundle {ACC1:conc#466.itm} 3 {ACC1:conc#466.itm(0)} {ACC1:conc#466.itm(1)} {ACC1:conc#466.itm(2)} -attr xrf 33487 -attr oid 651 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#466.itm}
+load net {ACC1-1:not#120.itm(0)} -attr vt d
+load net {ACC1-1:not#120.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#120.itm} 2 {ACC1-1:not#120.itm(0)} {ACC1-1:not#120.itm(1)} -attr xrf 33488 -attr oid 652 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#120.itm}
+load net {slc(ACC1:acc#125.psp#1.sva)#8.itm(0)} -attr vt d
+load net {slc(ACC1:acc#125.psp#1.sva)#8.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#125.psp#1.sva)#8.itm} 2 {slc(ACC1:acc#125.psp#1.sva)#8.itm(0)} {slc(ACC1:acc#125.psp#1.sva)#8.itm(1)} -attr xrf 33489 -attr oid 653 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#8.itm}
+load net {ACC1:acc#143.itm(0)} -attr vt d
+load net {ACC1:acc#143.itm(1)} -attr vt d
+load net {ACC1:acc#143.itm(2)} -attr vt d
+load net {ACC1:acc#143.itm(3)} -attr vt d
+load net {ACC1:acc#143.itm(4)} -attr vt d
+load net {ACC1:acc#143.itm(5)} -attr vt d
+load net {ACC1:acc#143.itm(6)} -attr vt d
+load net {ACC1:acc#143.itm(7)} -attr vt d
+load net {ACC1:acc#143.itm(8)} -attr vt d
+load net {ACC1:acc#143.itm(9)} -attr vt d
+load net {ACC1:acc#143.itm(10)} -attr vt d
+load netBundle {ACC1:acc#143.itm} 11 {ACC1:acc#143.itm(0)} {ACC1:acc#143.itm(1)} {ACC1:acc#143.itm(2)} {ACC1:acc#143.itm(3)} {ACC1:acc#143.itm(4)} {ACC1:acc#143.itm(5)} {ACC1:acc#143.itm(6)} {ACC1:acc#143.itm(7)} {ACC1:acc#143.itm(8)} {ACC1:acc#143.itm(9)} {ACC1:acc#143.itm(10)} -attr xrf 33490 -attr oid 654 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:not#158.itm(0)} -attr vt d
+load net {ACC1:not#158.itm(1)} -attr vt d
+load net {ACC1:not#158.itm(2)} -attr vt d
+load net {ACC1:not#158.itm(3)} -attr vt d
+load net {ACC1:not#158.itm(4)} -attr vt d
+load net {ACC1:not#158.itm(5)} -attr vt d
+load net {ACC1:not#158.itm(6)} -attr vt d
+load net {ACC1:not#158.itm(7)} -attr vt d
+load net {ACC1:not#158.itm(8)} -attr vt d
+load net {ACC1:not#158.itm(9)} -attr vt d
+load netBundle {ACC1:not#158.itm} 10 {ACC1:not#158.itm(0)} {ACC1:not#158.itm(1)} {ACC1:not#158.itm(2)} {ACC1:not#158.itm(3)} {ACC1:not#158.itm(4)} {ACC1:not#158.itm(5)} {ACC1:not#158.itm(6)} {ACC1:not#158.itm(7)} {ACC1:not#158.itm(8)} {ACC1:not#158.itm(9)} -attr xrf 33491 -attr oid 655 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {slc(regs.regs(0).sva#4).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#4).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#4).itm} 10 {slc(regs.regs(0).sva#4).itm(0)} {slc(regs.regs(0).sva#4).itm(1)} {slc(regs.regs(0).sva#4).itm(2)} {slc(regs.regs(0).sva#4).itm(3)} {slc(regs.regs(0).sva#4).itm(4)} {slc(regs.regs(0).sva#4).itm(5)} {slc(regs.regs(0).sva#4).itm(6)} {slc(regs.regs(0).sva#4).itm(7)} {slc(regs.regs(0).sva#4).itm(8)} {slc(regs.regs(0).sva#4).itm(9)} -attr xrf 33492 -attr oid 656 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:not#159.itm(0)} -attr vt d
+load net {ACC1:not#159.itm(1)} -attr vt d
+load net {ACC1:not#159.itm(2)} -attr vt d
+load net {ACC1:not#159.itm(3)} -attr vt d
+load net {ACC1:not#159.itm(4)} -attr vt d
+load net {ACC1:not#159.itm(5)} -attr vt d
+load net {ACC1:not#159.itm(6)} -attr vt d
+load net {ACC1:not#159.itm(7)} -attr vt d
+load net {ACC1:not#159.itm(8)} -attr vt d
+load net {ACC1:not#159.itm(9)} -attr vt d
+load netBundle {ACC1:not#159.itm} 10 {ACC1:not#159.itm(0)} {ACC1:not#159.itm(1)} {ACC1:not#159.itm(2)} {ACC1:not#159.itm(3)} {ACC1:not#159.itm(4)} {ACC1:not#159.itm(5)} {ACC1:not#159.itm(6)} {ACC1:not#159.itm(7)} {ACC1:not#159.itm(8)} {ACC1:not#159.itm(9)} -attr xrf 33493 -attr oid 657 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {slc(regs.regs(0).sva#5).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#5).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#5).itm} 10 {slc(regs.regs(0).sva#5).itm(0)} {slc(regs.regs(0).sva#5).itm(1)} {slc(regs.regs(0).sva#5).itm(2)} {slc(regs.regs(0).sva#5).itm(3)} {slc(regs.regs(0).sva#5).itm(4)} {slc(regs.regs(0).sva#5).itm(5)} {slc(regs.regs(0).sva#5).itm(6)} {slc(regs.regs(0).sva#5).itm(7)} {slc(regs.regs(0).sva#5).itm(8)} {slc(regs.regs(0).sva#5).itm(9)} -attr xrf 33494 -attr oid 658 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {ACC1:acc#142.itm(0)} -attr vt d
+load net {ACC1:acc#142.itm(1)} -attr vt d
+load net {ACC1:acc#142.itm(2)} -attr vt d
+load net {ACC1:acc#142.itm(3)} -attr vt d
+load net {ACC1:acc#142.itm(4)} -attr vt d
+load net {ACC1:acc#142.itm(5)} -attr vt d
+load net {ACC1:acc#142.itm(6)} -attr vt d
+load net {ACC1:acc#142.itm(7)} -attr vt d
+load net {ACC1:acc#142.itm(8)} -attr vt d
+load net {ACC1:acc#142.itm(9)} -attr vt d
+load net {ACC1:acc#142.itm(10)} -attr vt d
+load netBundle {ACC1:acc#142.itm} 11 {ACC1:acc#142.itm(0)} {ACC1:acc#142.itm(1)} {ACC1:acc#142.itm(2)} {ACC1:acc#142.itm(3)} {ACC1:acc#142.itm(4)} {ACC1:acc#142.itm(5)} {ACC1:acc#142.itm(6)} {ACC1:acc#142.itm(7)} {ACC1:acc#142.itm(8)} {ACC1:acc#142.itm(9)} {ACC1:acc#142.itm(10)} -attr xrf 33495 -attr oid 659 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:not#160.itm(0)} -attr vt d
+load net {ACC1:not#160.itm(1)} -attr vt d
+load net {ACC1:not#160.itm(2)} -attr vt d
+load net {ACC1:not#160.itm(3)} -attr vt d
+load net {ACC1:not#160.itm(4)} -attr vt d
+load net {ACC1:not#160.itm(5)} -attr vt d
+load net {ACC1:not#160.itm(6)} -attr vt d
+load net {ACC1:not#160.itm(7)} -attr vt d
+load net {ACC1:not#160.itm(8)} -attr vt d
+load net {ACC1:not#160.itm(9)} -attr vt d
+load netBundle {ACC1:not#160.itm} 10 {ACC1:not#160.itm(0)} {ACC1:not#160.itm(1)} {ACC1:not#160.itm(2)} {ACC1:not#160.itm(3)} {ACC1:not#160.itm(4)} {ACC1:not#160.itm(5)} {ACC1:not#160.itm(6)} {ACC1:not#160.itm(7)} {ACC1:not#160.itm(8)} {ACC1:not#160.itm(9)} -attr xrf 33496 -attr oid 660 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {slc(regs.regs(0).sva#6).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#6).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#6).itm} 10 {slc(regs.regs(0).sva#6).itm(0)} {slc(regs.regs(0).sva#6).itm(1)} {slc(regs.regs(0).sva#6).itm(2)} {slc(regs.regs(0).sva#6).itm(3)} {slc(regs.regs(0).sva#6).itm(4)} {slc(regs.regs(0).sva#6).itm(5)} {slc(regs.regs(0).sva#6).itm(6)} {slc(regs.regs(0).sva#6).itm(7)} {slc(regs.regs(0).sva#6).itm(8)} {slc(regs.regs(0).sva#6).itm(9)} -attr xrf 33497 -attr oid 661 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:acc#176.itm(0)} -attr vt d
+load net {ACC1:acc#176.itm(1)} -attr vt d
+load net {ACC1:acc#176.itm(2)} -attr vt d
+load net {ACC1:acc#176.itm(3)} -attr vt d
+load net {ACC1:acc#176.itm(4)} -attr vt d
+load netBundle {ACC1:acc#176.itm} 5 {ACC1:acc#176.itm(0)} {ACC1:acc#176.itm(1)} {ACC1:acc#176.itm(2)} {ACC1:acc#176.itm(3)} {ACC1:acc#176.itm(4)} -attr xrf 33498 -attr oid 662 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {conc#692.itm(0)} -attr vt d
+load net {conc#692.itm(1)} -attr vt d
+load net {conc#692.itm(2)} -attr vt d
+load net {conc#692.itm(3)} -attr vt d
+load netBundle {conc#692.itm} 4 {conc#692.itm(0)} {conc#692.itm(1)} {conc#692.itm(2)} {conc#692.itm(3)} -attr xrf 33499 -attr oid 663 -attr vt d -attr @path {/sobel/sobel:core/conc#692.itm}
+load net {ACC1:slc#41.itm(0)} -attr vt d
+load net {ACC1:slc#41.itm(1)} -attr vt d
+load net {ACC1:slc#41.itm(2)} -attr vt d
+load netBundle {ACC1:slc#41.itm} 3 {ACC1:slc#41.itm(0)} {ACC1:slc#41.itm(1)} {ACC1:slc#41.itm(2)} -attr xrf 33500 -attr oid 664 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#41.itm}
+load net {ACC1:acc#175.itm(0)} -attr vt d
+load net {ACC1:acc#175.itm(1)} -attr vt d
+load net {ACC1:acc#175.itm(2)} -attr vt d
+load net {ACC1:acc#175.itm(3)} -attr vt d
+load netBundle {ACC1:acc#175.itm} 4 {ACC1:acc#175.itm(0)} {ACC1:acc#175.itm(1)} {ACC1:acc#175.itm(2)} {ACC1:acc#175.itm(3)} -attr xrf 33501 -attr oid 665 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load net {conc#693.itm(0)} -attr vt d
+load net {conc#693.itm(1)} -attr vt d
+load net {conc#693.itm(2)} -attr vt d
+load net {conc#693.itm(3)} -attr vt d
+load netBundle {conc#693.itm} 4 {conc#693.itm(0)} {conc#693.itm(1)} {conc#693.itm(2)} {conc#693.itm(3)} -attr xrf 33502 -attr oid 666 -attr vt d -attr @path {/sobel/sobel:core/conc#693.itm}
+load net {ACC1:conc#522.itm(0)} -attr vt d
+load net {ACC1:conc#522.itm(1)} -attr vt d
+load net {ACC1:conc#522.itm(2)} -attr vt d
+load netBundle {ACC1:conc#522.itm} 3 {ACC1:conc#522.itm(0)} {ACC1:conc#522.itm(1)} {ACC1:conc#522.itm(2)} -attr xrf 33503 -attr oid 667 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#522.itm}
+load net {ACC1:slc#39.itm(0)} -attr vt d
+load net {ACC1:slc#39.itm(1)} -attr vt d
+load netBundle {ACC1:slc#39.itm} 2 {ACC1:slc#39.itm(0)} {ACC1:slc#39.itm(1)} -attr xrf 33504 -attr oid 668 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#39.itm}
+load net {ACC1:acc#173.itm(0)} -attr vt d
+load net {ACC1:acc#173.itm(1)} -attr vt d
+load net {ACC1:acc#173.itm(2)} -attr vt d
+load netBundle {ACC1:acc#173.itm} 3 {ACC1:acc#173.itm(0)} {ACC1:acc#173.itm(1)} {ACC1:acc#173.itm(2)} -attr xrf 33505 -attr oid 669 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load net {conc#694.itm(0)} -attr vt d
+load net {conc#694.itm(1)} -attr vt d
+load netBundle {conc#694.itm} 2 {conc#694.itm(0)} {conc#694.itm(1)} -attr xrf 33506 -attr oid 670 -attr vt d -attr @path {/sobel/sobel:core/conc#694.itm}
+load net {ACC1:conc#518.itm(0)} -attr vt d
+load net {ACC1:conc#518.itm(1)} -attr vt d
+load netBundle {ACC1:conc#518.itm} 2 {ACC1:conc#518.itm(0)} {ACC1:conc#518.itm(1)} -attr xrf 33507 -attr oid 671 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#518.itm}
+load net {ACC1:conc#524.itm(0)} -attr vt d
+load net {ACC1:conc#524.itm(1)} -attr vt d
+load net {ACC1:conc#524.itm(2)} -attr vt d
+load net {ACC1:conc#524.itm(3)} -attr vt d
+load net {ACC1:conc#524.itm(4)} -attr vt d
+load netBundle {ACC1:conc#524.itm} 5 {ACC1:conc#524.itm(0)} {ACC1:conc#524.itm(1)} {ACC1:conc#524.itm(2)} {ACC1:conc#524.itm(3)} {ACC1:conc#524.itm(4)} -attr xrf 33508 -attr oid 672 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#524.itm}
+load net {ACC1:slc#40.itm(0)} -attr vt d
+load net {ACC1:slc#40.itm(1)} -attr vt d
+load net {ACC1:slc#40.itm(2)} -attr vt d
+load net {ACC1:slc#40.itm(3)} -attr vt d
+load netBundle {ACC1:slc#40.itm} 4 {ACC1:slc#40.itm(0)} {ACC1:slc#40.itm(1)} {ACC1:slc#40.itm(2)} {ACC1:slc#40.itm(3)} -attr xrf 33509 -attr oid 673 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#40.itm}
+load net {ACC1:acc#174.itm(0)} -attr vt d
+load net {ACC1:acc#174.itm(1)} -attr vt d
+load net {ACC1:acc#174.itm(2)} -attr vt d
+load net {ACC1:acc#174.itm(3)} -attr vt d
+load net {ACC1:acc#174.itm(4)} -attr vt d
+load netBundle {ACC1:acc#174.itm} 5 {ACC1:acc#174.itm(0)} {ACC1:acc#174.itm(1)} {ACC1:acc#174.itm(2)} {ACC1:acc#174.itm(3)} {ACC1:acc#174.itm(4)} -attr xrf 33510 -attr oid 674 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {conc#695.itm(0)} -attr vt d
+load net {conc#695.itm(1)} -attr vt d
+load net {conc#695.itm(2)} -attr vt d
+load netBundle {conc#695.itm} 3 {conc#695.itm(0)} {conc#695.itm(1)} {conc#695.itm(2)} -attr xrf 33511 -attr oid 675 -attr vt d -attr @path {/sobel/sobel:core/conc#695.itm}
+load net {ACC1:slc#38.itm(0)} -attr vt d
+load net {ACC1:slc#38.itm(1)} -attr vt d
+load netBundle {ACC1:slc#38.itm} 2 {ACC1:slc#38.itm(0)} {ACC1:slc#38.itm(1)} -attr xrf 33512 -attr oid 676 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#38.itm}
+load net {ACC1:acc#172.itm(0)} -attr vt d
+load net {ACC1:acc#172.itm(1)} -attr vt d
+load net {ACC1:acc#172.itm(2)} -attr vt d
+load netBundle {ACC1:acc#172.itm} 3 {ACC1:acc#172.itm(0)} {ACC1:acc#172.itm(1)} {ACC1:acc#172.itm(2)} -attr xrf 33513 -attr oid 677 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load net {conc#696.itm(0)} -attr vt d
+load net {conc#696.itm(1)} -attr vt d
+load netBundle {conc#696.itm} 2 {conc#696.itm(0)} {conc#696.itm(1)} -attr xrf 33514 -attr oid 678 -attr vt d -attr @path {/sobel/sobel:core/conc#696.itm}
+load net {ACC1:conc#516.itm(0)} -attr vt d
+load net {ACC1:conc#516.itm(1)} -attr vt d
+load netBundle {ACC1:conc#516.itm} 2 {ACC1:conc#516.itm(0)} {ACC1:conc#516.itm(1)} -attr xrf 33515 -attr oid 679 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#516.itm}
+load net {ACC1:conc#520.itm(0)} -attr vt d
+load net {ACC1:conc#520.itm(1)} -attr vt d
+load net {ACC1:conc#520.itm(2)} -attr vt d
+load netBundle {ACC1:conc#520.itm} 3 {ACC1:conc#520.itm(0)} {ACC1:conc#520.itm(1)} {ACC1:conc#520.itm(2)} -attr xrf 33516 -attr oid 680 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#520.itm}
+load net {ACC1-3:not#120.itm(0)} -attr vt d
+load net {ACC1-3:not#120.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#120.itm} 2 {ACC1-3:not#120.itm(0)} {ACC1-3:not#120.itm(1)} -attr xrf 33517 -attr oid 681 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#120.itm}
+load net {slc(ACC1:acc#125.psp.sva)#8.itm(0)} -attr vt d
+load net {slc(ACC1:acc#125.psp.sva)#8.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#125.psp.sva)#8.itm} 2 {slc(ACC1:acc#125.psp.sva)#8.itm(0)} {slc(ACC1:acc#125.psp.sva)#8.itm(1)} -attr xrf 33518 -attr oid 682 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#8.itm}
+load net {ACC1:acc#171.itm(0)} -attr vt d
+load net {ACC1:acc#171.itm(1)} -attr vt d
+load net {ACC1:acc#171.itm(2)} -attr vt d
+load net {ACC1:acc#171.itm(3)} -attr vt d
+load net {ACC1:acc#171.itm(4)} -attr vt d
+load net {ACC1:acc#171.itm(5)} -attr vt d
+load net {ACC1:acc#171.itm(6)} -attr vt d
+load net {ACC1:acc#171.itm(7)} -attr vt d
+load net {ACC1:acc#171.itm(8)} -attr vt d
+load net {ACC1:acc#171.itm(9)} -attr vt d
+load net {ACC1:acc#171.itm(10)} -attr vt d
+load netBundle {ACC1:acc#171.itm} 11 {ACC1:acc#171.itm(0)} {ACC1:acc#171.itm(1)} {ACC1:acc#171.itm(2)} {ACC1:acc#171.itm(3)} {ACC1:acc#171.itm(4)} {ACC1:acc#171.itm(5)} {ACC1:acc#171.itm(6)} {ACC1:acc#171.itm(7)} {ACC1:acc#171.itm(8)} {ACC1:acc#171.itm(9)} {ACC1:acc#171.itm(10)} -attr xrf 33519 -attr oid 683 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {slc(regs.regs(1).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#5.itm} 10 {slc(regs.regs(1).sva)#5.itm(0)} {slc(regs.regs(1).sva)#5.itm(1)} {slc(regs.regs(1).sva)#5.itm(2)} {slc(regs.regs(1).sva)#5.itm(3)} {slc(regs.regs(1).sva)#5.itm(4)} {slc(regs.regs(1).sva)#5.itm(5)} {slc(regs.regs(1).sva)#5.itm(6)} {slc(regs.regs(1).sva)#5.itm(7)} {slc(regs.regs(1).sva)#5.itm(8)} {slc(regs.regs(1).sva)#5.itm(9)} -attr xrf 33520 -attr oid 684 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {slc(regs.regs(1).sva)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#6.itm} 10 {slc(regs.regs(1).sva)#6.itm(0)} {slc(regs.regs(1).sva)#6.itm(1)} {slc(regs.regs(1).sva)#6.itm(2)} {slc(regs.regs(1).sva)#6.itm(3)} {slc(regs.regs(1).sva)#6.itm(4)} {slc(regs.regs(1).sva)#6.itm(5)} {slc(regs.regs(1).sva)#6.itm(6)} {slc(regs.regs(1).sva)#6.itm(7)} {slc(regs.regs(1).sva)#6.itm(8)} {slc(regs.regs(1).sva)#6.itm(9)} -attr xrf 33521 -attr oid 685 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {slc(regs.regs(1).sva)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#7.itm} 10 {slc(regs.regs(1).sva)#7.itm(0)} {slc(regs.regs(1).sva)#7.itm(1)} {slc(regs.regs(1).sva)#7.itm(2)} {slc(regs.regs(1).sva)#7.itm(3)} {slc(regs.regs(1).sva)#7.itm(4)} {slc(regs.regs(1).sva)#7.itm(5)} {slc(regs.regs(1).sva)#7.itm(6)} {slc(regs.regs(1).sva)#7.itm(7)} {slc(regs.regs(1).sva)#7.itm(8)} {slc(regs.regs(1).sva)#7.itm(9)} -attr xrf 33522 -attr oid 686 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {ACC1:slc#43.itm(0)} -attr vt d
+load net {ACC1:slc#43.itm(1)} -attr vt d
+load netBundle {ACC1:slc#43.itm} 2 {ACC1:slc#43.itm(0)} {ACC1:slc#43.itm(1)} -attr xrf 33523 -attr oid 687 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#43.itm}
+load net {ACC1:acc#177.itm(0)} -attr vt d
+load net {ACC1:acc#177.itm(1)} -attr vt d
+load net {ACC1:acc#177.itm(2)} -attr vt d
+load netBundle {ACC1:acc#177.itm} 3 {ACC1:acc#177.itm(0)} {ACC1:acc#177.itm(1)} {ACC1:acc#177.itm(2)} -attr xrf 33524 -attr oid 688 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {conc#697.itm(0)} -attr vt d
+load net {conc#697.itm(1)} -attr vt d
+load netBundle {conc#697.itm} 2 {conc#697.itm(0)} {conc#697.itm(1)} -attr xrf 33525 -attr oid 689 -attr vt d -attr @path {/sobel/sobel:core/conc#697.itm}
+load net {ACC1:conc#526.itm(0)} -attr vt d
+load net {ACC1:conc#526.itm(1)} -attr vt d
+load netBundle {ACC1:conc#526.itm} 2 {ACC1:conc#526.itm(0)} {ACC1:conc#526.itm(1)} -attr xrf 33526 -attr oid 690 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#526.itm}
+load net {ACC1:acc#178.itm(0)} -attr vt d
+load net {ACC1:acc#178.itm(1)} -attr vt d
+load net {ACC1:acc#178.itm(2)} -attr vt d
+load net {ACC1:acc#178.itm(3)} -attr vt d
+load netBundle {ACC1:acc#178.itm} 4 {ACC1:acc#178.itm(0)} {ACC1:acc#178.itm(1)} {ACC1:acc#178.itm(2)} {ACC1:acc#178.itm(3)} -attr xrf 33527 -attr oid 691 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {conc#698.itm(0)} -attr vt d
+load net {conc#698.itm(1)} -attr vt d
+load net {conc#698.itm(2)} -attr vt d
+load netBundle {conc#698.itm} 3 {conc#698.itm(0)} {conc#698.itm(1)} {conc#698.itm(2)} -attr xrf 33528 -attr oid 692 -attr vt d -attr @path {/sobel/sobel:core/conc#698.itm}
+load net {ACC1-3:not#147.itm(0)} -attr vt d
+load net {ACC1-3:not#147.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#147.itm} 2 {ACC1-3:not#147.itm(0)} {ACC1-3:not#147.itm(1)} -attr xrf 33529 -attr oid 693 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#147.itm}
+load net {slc(ACC1:acc#118.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#118.psp.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#118.psp.sva)#2.itm} 2 {slc(ACC1:acc#118.psp.sva)#2.itm(0)} {slc(ACC1:acc#118.psp.sva)#2.itm(1)} -attr xrf 33530 -attr oid 694 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp.sva)#2.itm}
+load net {conc#699.itm(0)} -attr vt d
+load net {conc#699.itm(1)} -attr vt d
+load netBundle {conc#699.itm} 2 {conc#699.itm(0)} {conc#699.itm(1)} -attr xrf 33531 -attr oid 695 -attr vt d -attr @path {/sobel/sobel:core/conc#699.itm}
+load net {ACC1:acc#180.itm(0)} -attr vt d
+load net {ACC1:acc#180.itm(1)} -attr vt d
+load net {ACC1:acc#180.itm(2)} -attr vt d
+load net {ACC1:acc#180.itm(3)} -attr vt d
+load net {ACC1:acc#180.itm(4)} -attr vt d
+load net {ACC1:acc#180.itm(5)} -attr vt d
+load net {ACC1:acc#180.itm(6)} -attr vt d
+load net {ACC1:acc#180.itm(7)} -attr vt d
+load net {ACC1:acc#180.itm(8)} -attr vt d
+load net {ACC1:acc#180.itm(9)} -attr vt d
+load net {ACC1:acc#180.itm(10)} -attr vt d
+load netBundle {ACC1:acc#180.itm} 11 {ACC1:acc#180.itm(0)} {ACC1:acc#180.itm(1)} {ACC1:acc#180.itm(2)} {ACC1:acc#180.itm(3)} {ACC1:acc#180.itm(4)} {ACC1:acc#180.itm(5)} {ACC1:acc#180.itm(6)} {ACC1:acc#180.itm(7)} {ACC1:acc#180.itm(8)} {ACC1:acc#180.itm(9)} {ACC1:acc#180.itm(10)} -attr xrf 33532 -attr oid 696 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {slc(regs.regs(1).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#2.itm} 10 {slc(regs.regs(1).sva)#2.itm(0)} {slc(regs.regs(1).sva)#2.itm(1)} {slc(regs.regs(1).sva)#2.itm(2)} {slc(regs.regs(1).sva)#2.itm(3)} {slc(regs.regs(1).sva)#2.itm(4)} {slc(regs.regs(1).sva)#2.itm(5)} {slc(regs.regs(1).sva)#2.itm(6)} {slc(regs.regs(1).sva)#2.itm(7)} {slc(regs.regs(1).sva)#2.itm(8)} {slc(regs.regs(1).sva)#2.itm(9)} -attr xrf 33533 -attr oid 697 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {slc(regs.regs(1).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#3.itm} 10 {slc(regs.regs(1).sva)#3.itm(0)} {slc(regs.regs(1).sva)#3.itm(1)} {slc(regs.regs(1).sva)#3.itm(2)} {slc(regs.regs(1).sva)#3.itm(3)} {slc(regs.regs(1).sva)#3.itm(4)} {slc(regs.regs(1).sva)#3.itm(5)} {slc(regs.regs(1).sva)#3.itm(6)} {slc(regs.regs(1).sva)#3.itm(7)} {slc(regs.regs(1).sva)#3.itm(8)} {slc(regs.regs(1).sva)#3.itm(9)} -attr xrf 33534 -attr oid 698 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {slc(regs.regs(1).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#4.itm} 10 {slc(regs.regs(1).sva)#4.itm(0)} {slc(regs.regs(1).sva)#4.itm(1)} {slc(regs.regs(1).sva)#4.itm(2)} {slc(regs.regs(1).sva)#4.itm(3)} {slc(regs.regs(1).sva)#4.itm(4)} {slc(regs.regs(1).sva)#4.itm(5)} {slc(regs.regs(1).sva)#4.itm(6)} {slc(regs.regs(1).sva)#4.itm(7)} {slc(regs.regs(1).sva)#4.itm(8)} {slc(regs.regs(1).sva)#4.itm(9)} -attr xrf 33535 -attr oid 699 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {ACC1:slc#50.itm(0)} -attr vt d
+load net {ACC1:slc#50.itm(1)} -attr vt d
+load net {ACC1:slc#50.itm(2)} -attr vt d
+load net {ACC1:slc#50.itm(3)} -attr vt d
+load netBundle {ACC1:slc#50.itm} 4 {ACC1:slc#50.itm(0)} {ACC1:slc#50.itm(1)} {ACC1:slc#50.itm(2)} {ACC1:slc#50.itm(3)} -attr xrf 33536 -attr oid 700 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#185.itm(0)} -attr vt d
+load net {ACC1:acc#185.itm(1)} -attr vt d
+load net {ACC1:acc#185.itm(2)} -attr vt d
+load net {ACC1:acc#185.itm(3)} -attr vt d
+load net {ACC1:acc#185.itm(4)} -attr vt d
+load netBundle {ACC1:acc#185.itm} 5 {ACC1:acc#185.itm(0)} {ACC1:acc#185.itm(1)} {ACC1:acc#185.itm(2)} {ACC1:acc#185.itm(3)} {ACC1:acc#185.itm(4)} -attr xrf 33537 -attr oid 701 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {conc#700.itm(0)} -attr vt d
+load net {conc#700.itm(1)} -attr vt d
+load net {conc#700.itm(2)} -attr vt d
+load net {conc#700.itm(3)} -attr vt d
+load netBundle {conc#700.itm} 4 {conc#700.itm(0)} {conc#700.itm(1)} {conc#700.itm(2)} {conc#700.itm(3)} -attr xrf 33538 -attr oid 702 -attr vt d -attr @path {/sobel/sobel:core/conc#700.itm}
+load net {ACC1:slc#48.itm(0)} -attr vt d
+load net {ACC1:slc#48.itm(1)} -attr vt d
+load net {ACC1:slc#48.itm(2)} -attr vt d
+load netBundle {ACC1:slc#48.itm} 3 {ACC1:slc#48.itm(0)} {ACC1:slc#48.itm(1)} {ACC1:slc#48.itm(2)} -attr xrf 33539 -attr oid 703 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#48.itm}
+load net {ACC1:acc#183.itm(0)} -attr vt d
+load net {ACC1:acc#183.itm(1)} -attr vt d
+load net {ACC1:acc#183.itm(2)} -attr vt d
+load net {ACC1:acc#183.itm(3)} -attr vt d
+load netBundle {ACC1:acc#183.itm} 4 {ACC1:acc#183.itm(0)} {ACC1:acc#183.itm(1)} {ACC1:acc#183.itm(2)} {ACC1:acc#183.itm(3)} -attr xrf 33540 -attr oid 704 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load net {conc#701.itm(0)} -attr vt d
+load net {conc#701.itm(1)} -attr vt d
+load netBundle {conc#701.itm} 2 {conc#701.itm(0)} {conc#701.itm(1)} -attr xrf 33541 -attr oid 705 -attr vt d -attr @path {/sobel/sobel:core/conc#701.itm}
+load net {ACC1:conc#538.itm(0)} -attr vt d
+load net {ACC1:conc#538.itm(1)} -attr vt d
+load netBundle {ACC1:conc#538.itm} 2 {ACC1:conc#538.itm(0)} {ACC1:conc#538.itm(1)} -attr xrf 33542 -attr oid 706 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#538.itm}
+load net {conc#702.itm(0)} -attr vt d
+load net {conc#702.itm(1)} -attr vt d
+load net {conc#702.itm(2)} -attr vt d
+load net {conc#702.itm(3)} -attr vt d
+load netBundle {conc#702.itm} 4 {conc#702.itm(0)} {conc#702.itm(1)} {conc#702.itm(2)} {conc#702.itm(3)} -attr xrf 33543 -attr oid 707 -attr vt d -attr @path {/sobel/sobel:core/conc#702.itm}
+load net {ACC1:slc#49.itm(0)} -attr vt d
+load net {ACC1:slc#49.itm(1)} -attr vt d
+load net {ACC1:slc#49.itm(2)} -attr vt d
+load netBundle {ACC1:slc#49.itm} 3 {ACC1:slc#49.itm(0)} {ACC1:slc#49.itm(1)} {ACC1:slc#49.itm(2)} -attr xrf 33544 -attr oid 708 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#49.itm}
+load net {ACC1:acc#184.itm(0)} -attr vt d
+load net {ACC1:acc#184.itm(1)} -attr vt d
+load net {ACC1:acc#184.itm(2)} -attr vt d
+load net {ACC1:acc#184.itm(3)} -attr vt d
+load netBundle {ACC1:acc#184.itm} 4 {ACC1:acc#184.itm(0)} {ACC1:acc#184.itm(1)} {ACC1:acc#184.itm(2)} {ACC1:acc#184.itm(3)} -attr xrf 33545 -attr oid 709 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load net {conc#703.itm(0)} -attr vt d
+load net {conc#703.itm(1)} -attr vt d
+load net {conc#703.itm(2)} -attr vt d
+load netBundle {conc#703.itm} 3 {conc#703.itm(0)} {conc#703.itm(1)} {conc#703.itm(2)} -attr xrf 33546 -attr oid 710 -attr vt d -attr @path {/sobel/sobel:core/conc#703.itm}
+load net {ACC1:slc#47.itm(0)} -attr vt d
+load net {ACC1:slc#47.itm(1)} -attr vt d
+load netBundle {ACC1:slc#47.itm} 2 {ACC1:slc#47.itm(0)} {ACC1:slc#47.itm(1)} -attr xrf 33547 -attr oid 711 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#47.itm}
+load net {ACC1:acc#182.itm(0)} -attr vt d
+load net {ACC1:acc#182.itm(1)} -attr vt d
+load net {ACC1:acc#182.itm(2)} -attr vt d
+load netBundle {ACC1:acc#182.itm} 3 {ACC1:acc#182.itm(0)} {ACC1:acc#182.itm(1)} {ACC1:acc#182.itm(2)} -attr xrf 33548 -attr oid 712 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182.itm}
+load net {conc#704.itm(0)} -attr vt d
+load net {conc#704.itm(1)} -attr vt d
+load netBundle {conc#704.itm} 2 {conc#704.itm(0)} {conc#704.itm(1)} -attr xrf 33549 -attr oid 713 -attr vt d -attr @path {/sobel/sobel:core/conc#704.itm}
+load net {ACC1:conc#536.itm(0)} -attr vt d
+load net {ACC1:conc#536.itm(1)} -attr vt d
+load netBundle {ACC1:conc#536.itm} 2 {ACC1:conc#536.itm(0)} {ACC1:conc#536.itm(1)} -attr xrf 33550 -attr oid 714 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#536.itm}
+load net {ACC1:conc#540.itm(0)} -attr vt d
+load net {ACC1:conc#540.itm(1)} -attr vt d
+load net {ACC1:conc#540.itm(2)} -attr vt d
+load netBundle {ACC1:conc#540.itm} 3 {ACC1:conc#540.itm(0)} {ACC1:conc#540.itm(1)} {ACC1:conc#540.itm(2)} -attr xrf 33551 -attr oid 715 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#540.itm}
+load net {ACC1:slc#46.itm(0)} -attr vt d
+load net {ACC1:slc#46.itm(1)} -attr vt d
+load netBundle {ACC1:slc#46.itm} 2 {ACC1:slc#46.itm(0)} {ACC1:slc#46.itm(1)} -attr xrf 33552 -attr oid 716 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#46.itm}
+load net {ACC1:acc#181.itm(0)} -attr vt d
+load net {ACC1:acc#181.itm(1)} -attr vt d
+load net {ACC1:acc#181.itm(2)} -attr vt d
+load netBundle {ACC1:acc#181.itm} 3 {ACC1:acc#181.itm(0)} {ACC1:acc#181.itm(1)} {ACC1:acc#181.itm(2)} -attr xrf 33553 -attr oid 717 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181.itm}
+load net {conc#705.itm(0)} -attr vt d
+load net {conc#705.itm(1)} -attr vt d
+load netBundle {conc#705.itm} 2 {conc#705.itm(0)} {conc#705.itm(1)} -attr xrf 33554 -attr oid 718 -attr vt d -attr @path {/sobel/sobel:core/conc#705.itm}
+load net {ACC1:conc#534.itm(0)} -attr vt d
+load net {ACC1:conc#534.itm(1)} -attr vt d
+load netBundle {ACC1:conc#534.itm} 2 {ACC1:conc#534.itm(0)} {ACC1:conc#534.itm(1)} -attr xrf 33555 -attr oid 719 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#534.itm}
+load net {ACC1:slc#51.itm(0)} -attr vt d
+load net {ACC1:slc#51.itm(1)} -attr vt d
+load netBundle {ACC1:slc#51.itm} 2 {ACC1:slc#51.itm(0)} {ACC1:slc#51.itm(1)} -attr xrf 33556 -attr oid 720 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#51.itm}
+load net {ACC1:acc#186.itm(0)} -attr vt d
+load net {ACC1:acc#186.itm(1)} -attr vt d
+load net {ACC1:acc#186.itm(2)} -attr vt d
+load netBundle {ACC1:acc#186.itm} 3 {ACC1:acc#186.itm(0)} {ACC1:acc#186.itm(1)} {ACC1:acc#186.itm(2)} -attr xrf 33557 -attr oid 721 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186.itm}
+load net {conc#706.itm(0)} -attr vt d
+load net {conc#706.itm(1)} -attr vt d
+load netBundle {conc#706.itm} 2 {conc#706.itm(0)} {conc#706.itm(1)} -attr xrf 33558 -attr oid 722 -attr vt d -attr @path {/sobel/sobel:core/conc#706.itm}
+load net {ACC1:conc#544.itm(0)} -attr vt d
+load net {ACC1:conc#544.itm(1)} -attr vt d
+load netBundle {ACC1:conc#544.itm} 2 {ACC1:conc#544.itm(0)} {ACC1:conc#544.itm(1)} -attr xrf 33559 -attr oid 723 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#544.itm}
+load net {ACC1-3:exs#558.itm(0)} -attr vt d
+load net {ACC1-3:exs#558.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#558.itm} 2 {ACC1-3:exs#558.itm(0)} {ACC1-3:exs#558.itm(1)} -attr xrf 33560 -attr oid 724 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#558.itm}
+load net {ACC1-3:exs#547.itm(0)} -attr vt d
+load net {ACC1-3:exs#547.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#547.itm} 2 {ACC1-3:exs#547.itm(0)} {ACC1-3:exs#547.itm(1)} -attr xrf 33561 -attr oid 725 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#547.itm}
+load net {ACC1:acc#188.itm(0)} -attr vt d
+load net {ACC1:acc#188.itm(1)} -attr vt d
+load net {ACC1:acc#188.itm(2)} -attr vt d
+load netBundle {ACC1:acc#188.itm} 3 {ACC1:acc#188.itm(0)} {ACC1:acc#188.itm(1)} {ACC1:acc#188.itm(2)} -attr xrf 33562 -attr oid 726 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load net {conc#707.itm(0)} -attr vt d
+load net {conc#707.itm(1)} -attr vt d
+load net {conc#707.itm(2)} -attr vt d
+load netBundle {conc#707.itm} 3 {conc#707.itm(0)} {conc#707.itm(1)} {conc#707.itm(2)} -attr xrf 33563 -attr oid 727 -attr vt d -attr @path {/sobel/sobel:core/conc#707.itm}
+load net {ACC1:conc#549.itm(0)} -attr vt d
+load net {ACC1:conc#549.itm(1)} -attr vt d
+load netBundle {ACC1:conc#549.itm} 2 {ACC1:conc#549.itm(0)} {ACC1:conc#549.itm(1)} -attr xrf 33564 -attr oid 728 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#549.itm}
+load net {ACC1:acc#153.itm(0)} -attr vt d
+load net {ACC1:acc#153.itm(1)} -attr vt d
+load net {ACC1:acc#153.itm(2)} -attr vt d
+load net {ACC1:acc#153.itm(3)} -attr vt d
+load net {ACC1:acc#153.itm(4)} -attr vt d
+load net {ACC1:acc#153.itm(5)} -attr vt d
+load net {ACC1:acc#153.itm(6)} -attr vt d
+load net {ACC1:acc#153.itm(7)} -attr vt d
+load net {ACC1:acc#153.itm(8)} -attr vt d
+load net {ACC1:acc#153.itm(9)} -attr vt d
+load net {ACC1:acc#153.itm(10)} -attr vt d
+load netBundle {ACC1:acc#153.itm} 11 {ACC1:acc#153.itm(0)} {ACC1:acc#153.itm(1)} {ACC1:acc#153.itm(2)} {ACC1:acc#153.itm(3)} {ACC1:acc#153.itm(4)} {ACC1:acc#153.itm(5)} {ACC1:acc#153.itm(6)} {ACC1:acc#153.itm(7)} {ACC1:acc#153.itm(8)} {ACC1:acc#153.itm(9)} {ACC1:acc#153.itm(10)} -attr xrf 33565 -attr oid 729 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:not#161.itm(0)} -attr vt d
+load net {ACC1:not#161.itm(1)} -attr vt d
+load net {ACC1:not#161.itm(2)} -attr vt d
+load net {ACC1:not#161.itm(3)} -attr vt d
+load net {ACC1:not#161.itm(4)} -attr vt d
+load net {ACC1:not#161.itm(5)} -attr vt d
+load net {ACC1:not#161.itm(6)} -attr vt d
+load net {ACC1:not#161.itm(7)} -attr vt d
+load net {ACC1:not#161.itm(8)} -attr vt d
+load net {ACC1:not#161.itm(9)} -attr vt d
+load netBundle {ACC1:not#161.itm} 10 {ACC1:not#161.itm(0)} {ACC1:not#161.itm(1)} {ACC1:not#161.itm(2)} {ACC1:not#161.itm(3)} {ACC1:not#161.itm(4)} {ACC1:not#161.itm(5)} {ACC1:not#161.itm(6)} {ACC1:not#161.itm(7)} {ACC1:not#161.itm(8)} {ACC1:not#161.itm(9)} -attr xrf 33566 -attr oid 730 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {slc(regs.regs(0).sva#1).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#1).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#1).itm} 10 {slc(regs.regs(0).sva#1).itm(0)} {slc(regs.regs(0).sva#1).itm(1)} {slc(regs.regs(0).sva#1).itm(2)} {slc(regs.regs(0).sva#1).itm(3)} {slc(regs.regs(0).sva#1).itm(4)} {slc(regs.regs(0).sva#1).itm(5)} {slc(regs.regs(0).sva#1).itm(6)} {slc(regs.regs(0).sva#1).itm(7)} {slc(regs.regs(0).sva#1).itm(8)} {slc(regs.regs(0).sva#1).itm(9)} -attr xrf 33567 -attr oid 731 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {ACC1:not#162.itm(0)} -attr vt d
+load net {ACC1:not#162.itm(1)} -attr vt d
+load net {ACC1:not#162.itm(2)} -attr vt d
+load net {ACC1:not#162.itm(3)} -attr vt d
+load net {ACC1:not#162.itm(4)} -attr vt d
+load net {ACC1:not#162.itm(5)} -attr vt d
+load net {ACC1:not#162.itm(6)} -attr vt d
+load net {ACC1:not#162.itm(7)} -attr vt d
+load net {ACC1:not#162.itm(8)} -attr vt d
+load net {ACC1:not#162.itm(9)} -attr vt d
+load netBundle {ACC1:not#162.itm} 10 {ACC1:not#162.itm(0)} {ACC1:not#162.itm(1)} {ACC1:not#162.itm(2)} {ACC1:not#162.itm(3)} {ACC1:not#162.itm(4)} {ACC1:not#162.itm(5)} {ACC1:not#162.itm(6)} {ACC1:not#162.itm(7)} {ACC1:not#162.itm(8)} {ACC1:not#162.itm(9)} -attr xrf 33568 -attr oid 732 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {slc(regs.regs(0).sva#2).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#2).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#2).itm} 10 {slc(regs.regs(0).sva#2).itm(0)} {slc(regs.regs(0).sva#2).itm(1)} {slc(regs.regs(0).sva#2).itm(2)} {slc(regs.regs(0).sva#2).itm(3)} {slc(regs.regs(0).sva#2).itm(4)} {slc(regs.regs(0).sva#2).itm(5)} {slc(regs.regs(0).sva#2).itm(6)} {slc(regs.regs(0).sva#2).itm(7)} {slc(regs.regs(0).sva#2).itm(8)} {slc(regs.regs(0).sva#2).itm(9)} -attr xrf 33569 -attr oid 733 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {ACC1:acc#152.itm(0)} -attr vt d
+load net {ACC1:acc#152.itm(1)} -attr vt d
+load net {ACC1:acc#152.itm(2)} -attr vt d
+load net {ACC1:acc#152.itm(3)} -attr vt d
+load net {ACC1:acc#152.itm(4)} -attr vt d
+load net {ACC1:acc#152.itm(5)} -attr vt d
+load net {ACC1:acc#152.itm(6)} -attr vt d
+load net {ACC1:acc#152.itm(7)} -attr vt d
+load net {ACC1:acc#152.itm(8)} -attr vt d
+load net {ACC1:acc#152.itm(9)} -attr vt d
+load net {ACC1:acc#152.itm(10)} -attr vt d
+load netBundle {ACC1:acc#152.itm} 11 {ACC1:acc#152.itm(0)} {ACC1:acc#152.itm(1)} {ACC1:acc#152.itm(2)} {ACC1:acc#152.itm(3)} {ACC1:acc#152.itm(4)} {ACC1:acc#152.itm(5)} {ACC1:acc#152.itm(6)} {ACC1:acc#152.itm(7)} {ACC1:acc#152.itm(8)} {ACC1:acc#152.itm(9)} {ACC1:acc#152.itm(10)} -attr xrf 33570 -attr oid 734 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:not#163.itm(0)} -attr vt d
+load net {ACC1:not#163.itm(1)} -attr vt d
+load net {ACC1:not#163.itm(2)} -attr vt d
+load net {ACC1:not#163.itm(3)} -attr vt d
+load net {ACC1:not#163.itm(4)} -attr vt d
+load net {ACC1:not#163.itm(5)} -attr vt d
+load net {ACC1:not#163.itm(6)} -attr vt d
+load net {ACC1:not#163.itm(7)} -attr vt d
+load net {ACC1:not#163.itm(8)} -attr vt d
+load net {ACC1:not#163.itm(9)} -attr vt d
+load netBundle {ACC1:not#163.itm} 10 {ACC1:not#163.itm(0)} {ACC1:not#163.itm(1)} {ACC1:not#163.itm(2)} {ACC1:not#163.itm(3)} {ACC1:not#163.itm(4)} {ACC1:not#163.itm(5)} {ACC1:not#163.itm(6)} {ACC1:not#163.itm(7)} {ACC1:not#163.itm(8)} {ACC1:not#163.itm(9)} -attr xrf 33571 -attr oid 735 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {slc(regs.regs(0).sva#3).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#3).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#3).itm} 10 {slc(regs.regs(0).sva#3).itm(0)} {slc(regs.regs(0).sva#3).itm(1)} {slc(regs.regs(0).sva#3).itm(2)} {slc(regs.regs(0).sva#3).itm(3)} {slc(regs.regs(0).sva#3).itm(4)} {slc(regs.regs(0).sva#3).itm(5)} {slc(regs.regs(0).sva#3).itm(6)} {slc(regs.regs(0).sva#3).itm(7)} {slc(regs.regs(0).sva#3).itm(8)} {slc(regs.regs(0).sva#3).itm(9)} -attr xrf 33572 -attr oid 736 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {ACC1:acc#161.itm(0)} -attr vt d
+load net {ACC1:acc#161.itm(1)} -attr vt d
+load net {ACC1:acc#161.itm(2)} -attr vt d
+load netBundle {ACC1:acc#161.itm} 3 {ACC1:acc#161.itm(0)} {ACC1:acc#161.itm(1)} {ACC1:acc#161.itm(2)} -attr xrf 33573 -attr oid 737 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load net {conc#708.itm(0)} -attr vt d
+load net {conc#708.itm(1)} -attr vt d
+load net {conc#708.itm(2)} -attr vt d
+load netBundle {conc#708.itm} 3 {conc#708.itm(0)} {conc#708.itm(1)} {conc#708.itm(2)} -attr xrf 33574 -attr oid 738 -attr vt d -attr @path {/sobel/sobel:core/conc#708.itm}
+load net {ACC1:conc#495.itm(0)} -attr vt d
+load net {ACC1:conc#495.itm(1)} -attr vt d
+load netBundle {ACC1:conc#495.itm} 2 {ACC1:conc#495.itm(0)} {ACC1:conc#495.itm(1)} -attr xrf 33575 -attr oid 739 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#495.itm}
+load net {ACC1:acc#160.itm(0)} -attr vt d
+load net {ACC1:acc#160.itm(1)} -attr vt d
+load net {ACC1:acc#160.itm(2)} -attr vt d
+load net {ACC1:acc#160.itm(3)} -attr vt d
+load netBundle {ACC1:acc#160.itm} 4 {ACC1:acc#160.itm(0)} {ACC1:acc#160.itm(1)} {ACC1:acc#160.itm(2)} {ACC1:acc#160.itm(3)} -attr xrf 33576 -attr oid 740 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load net {conc#709.itm(0)} -attr vt d
+load net {conc#709.itm(1)} -attr vt d
+load net {conc#709.itm(2)} -attr vt d
+load netBundle {conc#709.itm} 3 {conc#709.itm(0)} {conc#709.itm(1)} {conc#709.itm(2)} -attr xrf 33577 -attr oid 741 -attr vt d -attr @path {/sobel/sobel:core/conc#709.itm}
+load net {ACC1-1:not#149.itm(0)} -attr vt d
+load net {ACC1-1:not#149.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#149.itm} 2 {ACC1-1:not#149.itm(0)} {ACC1-1:not#149.itm(1)} -attr xrf 33578 -attr oid 742 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#149.itm}
+load net {slc(ACC1:acc#120.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#120.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#120.psp#1.sva).itm} 2 {slc(ACC1:acc#120.psp#1.sva).itm(0)} {slc(ACC1:acc#120.psp#1.sva).itm(1)} -attr xrf 33579 -attr oid 743 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp#1.sva).itm}
+load net {conc#710.itm(0)} -attr vt d
+load net {conc#710.itm(1)} -attr vt d
+load netBundle {conc#710.itm} 2 {conc#710.itm(0)} {conc#710.itm(1)} -attr xrf 33580 -attr oid 744 -attr vt d -attr @path {/sobel/sobel:core/conc#710.itm}
+load net {ACC1:slc#26.itm(0)} -attr vt d
+load net {ACC1:slc#26.itm(1)} -attr vt d
+load net {ACC1:slc#26.itm(2)} -attr vt d
+load net {ACC1:slc#26.itm(3)} -attr vt d
+load netBundle {ACC1:slc#26.itm} 4 {ACC1:slc#26.itm(0)} {ACC1:slc#26.itm(1)} {ACC1:slc#26.itm(2)} {ACC1:slc#26.itm(3)} -attr xrf 33581 -attr oid 745 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#158.itm(0)} -attr vt d
+load net {ACC1:acc#158.itm(1)} -attr vt d
+load net {ACC1:acc#158.itm(2)} -attr vt d
+load net {ACC1:acc#158.itm(3)} -attr vt d
+load net {ACC1:acc#158.itm(4)} -attr vt d
+load netBundle {ACC1:acc#158.itm} 5 {ACC1:acc#158.itm(0)} {ACC1:acc#158.itm(1)} {ACC1:acc#158.itm(2)} {ACC1:acc#158.itm(3)} {ACC1:acc#158.itm(4)} -attr xrf 33582 -attr oid 746 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {conc#711.itm(0)} -attr vt d
+load net {conc#711.itm(1)} -attr vt d
+load net {conc#711.itm(2)} -attr vt d
+load net {conc#711.itm(3)} -attr vt d
+load netBundle {conc#711.itm} 4 {conc#711.itm(0)} {conc#711.itm(1)} {conc#711.itm(2)} {conc#711.itm(3)} -attr xrf 33583 -attr oid 747 -attr vt d -attr @path {/sobel/sobel:core/conc#711.itm}
+load net {ACC1:slc#24.itm(0)} -attr vt d
+load net {ACC1:slc#24.itm(1)} -attr vt d
+load net {ACC1:slc#24.itm(2)} -attr vt d
+load netBundle {ACC1:slc#24.itm} 3 {ACC1:slc#24.itm(0)} {ACC1:slc#24.itm(1)} {ACC1:slc#24.itm(2)} -attr xrf 33584 -attr oid 748 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#24.itm}
+load net {ACC1:acc#156.itm(0)} -attr vt d
+load net {ACC1:acc#156.itm(1)} -attr vt d
+load net {ACC1:acc#156.itm(2)} -attr vt d
+load net {ACC1:acc#156.itm(3)} -attr vt d
+load netBundle {ACC1:acc#156.itm} 4 {ACC1:acc#156.itm(0)} {ACC1:acc#156.itm(1)} {ACC1:acc#156.itm(2)} {ACC1:acc#156.itm(3)} -attr xrf 33585 -attr oid 749 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load net {conc#712.itm(0)} -attr vt d
+load net {conc#712.itm(1)} -attr vt d
+load netBundle {conc#712.itm} 2 {conc#712.itm(0)} {conc#712.itm(1)} -attr xrf 33586 -attr oid 750 -attr vt d -attr @path {/sobel/sobel:core/conc#712.itm}
+load net {ACC1:conc#484.itm(0)} -attr vt d
+load net {ACC1:conc#484.itm(1)} -attr vt d
+load netBundle {ACC1:conc#484.itm} 2 {ACC1:conc#484.itm(0)} {ACC1:conc#484.itm(1)} -attr xrf 33587 -attr oid 751 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#484.itm}
+load net {conc#713.itm(0)} -attr vt d
+load net {conc#713.itm(1)} -attr vt d
+load net {conc#713.itm(2)} -attr vt d
+load net {conc#713.itm(3)} -attr vt d
+load netBundle {conc#713.itm} 4 {conc#713.itm(0)} {conc#713.itm(1)} {conc#713.itm(2)} {conc#713.itm(3)} -attr xrf 33588 -attr oid 752 -attr vt d -attr @path {/sobel/sobel:core/conc#713.itm}
+load net {ACC1:slc#25.itm(0)} -attr vt d
+load net {ACC1:slc#25.itm(1)} -attr vt d
+load net {ACC1:slc#25.itm(2)} -attr vt d
+load netBundle {ACC1:slc#25.itm} 3 {ACC1:slc#25.itm(0)} {ACC1:slc#25.itm(1)} {ACC1:slc#25.itm(2)} -attr xrf 33589 -attr oid 753 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#25.itm}
+load net {ACC1:acc#157.itm(0)} -attr vt d
+load net {ACC1:acc#157.itm(1)} -attr vt d
+load net {ACC1:acc#157.itm(2)} -attr vt d
+load net {ACC1:acc#157.itm(3)} -attr vt d
+load netBundle {ACC1:acc#157.itm} 4 {ACC1:acc#157.itm(0)} {ACC1:acc#157.itm(1)} {ACC1:acc#157.itm(2)} {ACC1:acc#157.itm(3)} -attr xrf 33590 -attr oid 754 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load net {conc#714.itm(0)} -attr vt d
+load net {conc#714.itm(1)} -attr vt d
+load net {conc#714.itm(2)} -attr vt d
+load netBundle {conc#714.itm} 3 {conc#714.itm(0)} {conc#714.itm(1)} {conc#714.itm(2)} -attr xrf 33591 -attr oid 755 -attr vt d -attr @path {/sobel/sobel:core/conc#714.itm}
+load net {ACC1:slc#23.itm(0)} -attr vt d
+load net {ACC1:slc#23.itm(1)} -attr vt d
+load netBundle {ACC1:slc#23.itm} 2 {ACC1:slc#23.itm(0)} {ACC1:slc#23.itm(1)} -attr xrf 33592 -attr oid 756 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#23.itm}
+load net {ACC1:acc#155.itm(0)} -attr vt d
+load net {ACC1:acc#155.itm(1)} -attr vt d
+load net {ACC1:acc#155.itm(2)} -attr vt d
+load netBundle {ACC1:acc#155.itm} 3 {ACC1:acc#155.itm(0)} {ACC1:acc#155.itm(1)} {ACC1:acc#155.itm(2)} -attr xrf 33593 -attr oid 757 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#155.itm}
+load net {conc#715.itm(0)} -attr vt d
+load net {conc#715.itm(1)} -attr vt d
+load netBundle {conc#715.itm} 2 {conc#715.itm(0)} {conc#715.itm(1)} -attr xrf 33594 -attr oid 758 -attr vt d -attr @path {/sobel/sobel:core/conc#715.itm}
+load net {ACC1:conc#482.itm(0)} -attr vt d
+load net {ACC1:conc#482.itm(1)} -attr vt d
+load netBundle {ACC1:conc#482.itm} 2 {ACC1:conc#482.itm(0)} {ACC1:conc#482.itm(1)} -attr xrf 33595 -attr oid 759 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#482.itm}
+load net {ACC1:conc#486.itm(0)} -attr vt d
+load net {ACC1:conc#486.itm(1)} -attr vt d
+load net {ACC1:conc#486.itm(2)} -attr vt d
+load netBundle {ACC1:conc#486.itm} 3 {ACC1:conc#486.itm(0)} {ACC1:conc#486.itm(1)} {ACC1:conc#486.itm(2)} -attr xrf 33596 -attr oid 760 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#486.itm}
+load net {ACC1:slc#22.itm(0)} -attr vt d
+load net {ACC1:slc#22.itm(1)} -attr vt d
+load netBundle {ACC1:slc#22.itm} 2 {ACC1:slc#22.itm(0)} {ACC1:slc#22.itm(1)} -attr xrf 33597 -attr oid 761 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#22.itm}
+load net {ACC1:acc#154.itm(0)} -attr vt d
+load net {ACC1:acc#154.itm(1)} -attr vt d
+load net {ACC1:acc#154.itm(2)} -attr vt d
+load netBundle {ACC1:acc#154.itm} 3 {ACC1:acc#154.itm(0)} {ACC1:acc#154.itm(1)} {ACC1:acc#154.itm(2)} -attr xrf 33598 -attr oid 762 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154.itm}
+load net {conc#716.itm(0)} -attr vt d
+load net {conc#716.itm(1)} -attr vt d
+load netBundle {conc#716.itm} 2 {conc#716.itm(0)} {conc#716.itm(1)} -attr xrf 33599 -attr oid 763 -attr vt d -attr @path {/sobel/sobel:core/conc#716.itm}
+load net {ACC1:conc#480.itm(0)} -attr vt d
+load net {ACC1:conc#480.itm(1)} -attr vt d
+load netBundle {ACC1:conc#480.itm} 2 {ACC1:conc#480.itm(0)} {ACC1:conc#480.itm(1)} -attr xrf 33600 -attr oid 764 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#480.itm}
+load net {ACC1:slc#27.itm(0)} -attr vt d
+load net {ACC1:slc#27.itm(1)} -attr vt d
+load netBundle {ACC1:slc#27.itm} 2 {ACC1:slc#27.itm(0)} {ACC1:slc#27.itm(1)} -attr xrf 33601 -attr oid 765 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#27.itm}
+load net {ACC1:acc#159.itm(0)} -attr vt d
+load net {ACC1:acc#159.itm(1)} -attr vt d
+load net {ACC1:acc#159.itm(2)} -attr vt d
+load netBundle {ACC1:acc#159.itm} 3 {ACC1:acc#159.itm(0)} {ACC1:acc#159.itm(1)} {ACC1:acc#159.itm(2)} -attr xrf 33602 -attr oid 766 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#159.itm}
+load net {conc#717.itm(0)} -attr vt d
+load net {conc#717.itm(1)} -attr vt d
+load netBundle {conc#717.itm} 2 {conc#717.itm(0)} {conc#717.itm(1)} -attr xrf 33603 -attr oid 767 -attr vt d -attr @path {/sobel/sobel:core/conc#717.itm}
+load net {ACC1:conc#490.itm(0)} -attr vt d
+load net {ACC1:conc#490.itm(1)} -attr vt d
+load netBundle {ACC1:conc#490.itm} 2 {ACC1:conc#490.itm(0)} {ACC1:conc#490.itm(1)} -attr xrf 33604 -attr oid 768 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#490.itm}
+load net {ACC1:exs#850.itm(0)} -attr vt d
+load net {ACC1:exs#850.itm(1)} -attr vt d
+load netBundle {ACC1:exs#850.itm} 2 {ACC1:exs#850.itm(0)} {ACC1:exs#850.itm(1)} -attr xrf 33605 -attr oid 769 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#850.itm}
+load net {ACC1:exs#827.itm(0)} -attr vt d
+load net {ACC1:exs#827.itm(1)} -attr vt d
+load netBundle {ACC1:exs#827.itm} 2 {ACC1:exs#827.itm(0)} {ACC1:exs#827.itm(1)} -attr xrf 33606 -attr oid 770 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#827.itm}
+load net {ACC1:acc#187.itm(0)} -attr vt d
+load net {ACC1:acc#187.itm(1)} -attr vt d
+load net {ACC1:acc#187.itm(2)} -attr vt d
+load net {ACC1:acc#187.itm(3)} -attr vt d
+load netBundle {ACC1:acc#187.itm} 4 {ACC1:acc#187.itm(0)} {ACC1:acc#187.itm(1)} {ACC1:acc#187.itm(2)} {ACC1:acc#187.itm(3)} -attr xrf 33607 -attr oid 771 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load net {conc#718.itm(0)} -attr vt d
+load net {conc#718.itm(1)} -attr vt d
+load net {conc#718.itm(2)} -attr vt d
+load netBundle {conc#718.itm} 3 {conc#718.itm(0)} {conc#718.itm(1)} {conc#718.itm(2)} -attr xrf 33608 -attr oid 772 -attr vt d -attr @path {/sobel/sobel:core/conc#718.itm}
+load net {ACC1-3:not#149.itm(0)} -attr vt d
+load net {ACC1-3:not#149.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#149.itm} 2 {ACC1-3:not#149.itm(0)} {ACC1-3:not#149.itm(1)} -attr xrf 33609 -attr oid 773 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#149.itm}
+load net {slc(ACC1:acc#120.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#120.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#120.psp.sva).itm} 2 {slc(ACC1:acc#120.psp.sva).itm(0)} {slc(ACC1:acc#120.psp.sva).itm(1)} -attr xrf 33610 -attr oid 774 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp.sva).itm}
+load net {conc#719.itm(0)} -attr vt d
+load net {conc#719.itm(1)} -attr vt d
+load netBundle {conc#719.itm} 2 {conc#719.itm(0)} {conc#719.itm(1)} -attr xrf 33611 -attr oid 775 -attr vt d -attr @path {/sobel/sobel:core/conc#719.itm}
+load net {ACC1:acc#162.itm(0)} -attr vt d
+load net {ACC1:acc#162.itm(1)} -attr vt d
+load net {ACC1:acc#162.itm(2)} -attr vt d
+load net {ACC1:acc#162.itm(3)} -attr vt d
+load net {ACC1:acc#162.itm(4)} -attr vt d
+load net {ACC1:acc#162.itm(5)} -attr vt d
+load net {ACC1:acc#162.itm(6)} -attr vt d
+load net {ACC1:acc#162.itm(7)} -attr vt d
+load net {ACC1:acc#162.itm(8)} -attr vt d
+load net {ACC1:acc#162.itm(9)} -attr vt d
+load net {ACC1:acc#162.itm(10)} -attr vt d
+load netBundle {ACC1:acc#162.itm} 11 {ACC1:acc#162.itm(0)} {ACC1:acc#162.itm(1)} {ACC1:acc#162.itm(2)} {ACC1:acc#162.itm(3)} {ACC1:acc#162.itm(4)} {ACC1:acc#162.itm(5)} {ACC1:acc#162.itm(6)} {ACC1:acc#162.itm(7)} {ACC1:acc#162.itm(8)} {ACC1:acc#162.itm(9)} {ACC1:acc#162.itm(10)} -attr xrf 33612 -attr oid 776 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {slc(regs.regs(1).sva)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#8.itm} 10 {slc(regs.regs(1).sva)#8.itm(0)} {slc(regs.regs(1).sva)#8.itm(1)} {slc(regs.regs(1).sva)#8.itm(2)} {slc(regs.regs(1).sva)#8.itm(3)} {slc(regs.regs(1).sva)#8.itm(4)} {slc(regs.regs(1).sva)#8.itm(5)} {slc(regs.regs(1).sva)#8.itm(6)} {slc(regs.regs(1).sva)#8.itm(7)} {slc(regs.regs(1).sva)#8.itm(8)} {slc(regs.regs(1).sva)#8.itm(9)} -attr xrf 33613 -attr oid 777 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {slc(regs.regs(1).sva)#9.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#9.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#9.itm} 10 {slc(regs.regs(1).sva)#9.itm(0)} {slc(regs.regs(1).sva)#9.itm(1)} {slc(regs.regs(1).sva)#9.itm(2)} {slc(regs.regs(1).sva)#9.itm(3)} {slc(regs.regs(1).sva)#9.itm(4)} {slc(regs.regs(1).sva)#9.itm(5)} {slc(regs.regs(1).sva)#9.itm(6)} {slc(regs.regs(1).sva)#9.itm(7)} {slc(regs.regs(1).sva)#9.itm(8)} {slc(regs.regs(1).sva)#9.itm(9)} -attr xrf 33614 -attr oid 778 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {slc(regs.regs(1).sva)#10.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#10.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#10.itm} 10 {slc(regs.regs(1).sva)#10.itm(0)} {slc(regs.regs(1).sva)#10.itm(1)} {slc(regs.regs(1).sva)#10.itm(2)} {slc(regs.regs(1).sva)#10.itm(3)} {slc(regs.regs(1).sva)#10.itm(4)} {slc(regs.regs(1).sva)#10.itm(5)} {slc(regs.regs(1).sva)#10.itm(6)} {slc(regs.regs(1).sva)#10.itm(7)} {slc(regs.regs(1).sva)#10.itm(8)} {slc(regs.regs(1).sva)#10.itm(9)} -attr xrf 33615 -attr oid 779 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {ACC1:slc#34.itm(0)} -attr vt d
+load net {ACC1:slc#34.itm(1)} -attr vt d
+load net {ACC1:slc#34.itm(2)} -attr vt d
+load net {ACC1:slc#34.itm(3)} -attr vt d
+load netBundle {ACC1:slc#34.itm} 4 {ACC1:slc#34.itm(0)} {ACC1:slc#34.itm(1)} {ACC1:slc#34.itm(2)} {ACC1:slc#34.itm(3)} -attr xrf 33616 -attr oid 780 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#167.itm(0)} -attr vt d
+load net {ACC1:acc#167.itm(1)} -attr vt d
+load net {ACC1:acc#167.itm(2)} -attr vt d
+load net {ACC1:acc#167.itm(3)} -attr vt d
+load net {ACC1:acc#167.itm(4)} -attr vt d
+load netBundle {ACC1:acc#167.itm} 5 {ACC1:acc#167.itm(0)} {ACC1:acc#167.itm(1)} {ACC1:acc#167.itm(2)} {ACC1:acc#167.itm(3)} {ACC1:acc#167.itm(4)} -attr xrf 33617 -attr oid 781 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load net {conc#720.itm(0)} -attr vt d
+load net {conc#720.itm(1)} -attr vt d
+load net {conc#720.itm(2)} -attr vt d
+load net {conc#720.itm(3)} -attr vt d
+load netBundle {conc#720.itm} 4 {conc#720.itm(0)} {conc#720.itm(1)} {conc#720.itm(2)} {conc#720.itm(3)} -attr xrf 33618 -attr oid 782 -attr vt d -attr @path {/sobel/sobel:core/conc#720.itm}
+load net {ACC1:slc#32.itm(0)} -attr vt d
+load net {ACC1:slc#32.itm(1)} -attr vt d
+load net {ACC1:slc#32.itm(2)} -attr vt d
+load netBundle {ACC1:slc#32.itm} 3 {ACC1:slc#32.itm(0)} {ACC1:slc#32.itm(1)} {ACC1:slc#32.itm(2)} -attr xrf 33619 -attr oid 783 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#32.itm}
+load net {ACC1:acc#165.itm(0)} -attr vt d
+load net {ACC1:acc#165.itm(1)} -attr vt d
+load net {ACC1:acc#165.itm(2)} -attr vt d
+load net {ACC1:acc#165.itm(3)} -attr vt d
+load netBundle {ACC1:acc#165.itm} 4 {ACC1:acc#165.itm(0)} {ACC1:acc#165.itm(1)} {ACC1:acc#165.itm(2)} {ACC1:acc#165.itm(3)} -attr xrf 33620 -attr oid 784 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {conc#721.itm(0)} -attr vt d
+load net {conc#721.itm(1)} -attr vt d
+load netBundle {conc#721.itm} 2 {conc#721.itm(0)} {conc#721.itm(1)} -attr xrf 33621 -attr oid 785 -attr vt d -attr @path {/sobel/sobel:core/conc#721.itm}
+load net {ACC1:conc#502.itm(0)} -attr vt d
+load net {ACC1:conc#502.itm(1)} -attr vt d
+load netBundle {ACC1:conc#502.itm} 2 {ACC1:conc#502.itm(0)} {ACC1:conc#502.itm(1)} -attr xrf 33622 -attr oid 786 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#502.itm}
+load net {conc#722.itm(0)} -attr vt d
+load net {conc#722.itm(1)} -attr vt d
+load net {conc#722.itm(2)} -attr vt d
+load net {conc#722.itm(3)} -attr vt d
+load netBundle {conc#722.itm} 4 {conc#722.itm(0)} {conc#722.itm(1)} {conc#722.itm(2)} {conc#722.itm(3)} -attr xrf 33623 -attr oid 787 -attr vt d -attr @path {/sobel/sobel:core/conc#722.itm}
+load net {ACC1:slc#33.itm(0)} -attr vt d
+load net {ACC1:slc#33.itm(1)} -attr vt d
+load net {ACC1:slc#33.itm(2)} -attr vt d
+load netBundle {ACC1:slc#33.itm} 3 {ACC1:slc#33.itm(0)} {ACC1:slc#33.itm(1)} {ACC1:slc#33.itm(2)} -attr xrf 33624 -attr oid 788 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#166.itm(0)} -attr vt d
+load net {ACC1:acc#166.itm(1)} -attr vt d
+load net {ACC1:acc#166.itm(2)} -attr vt d
+load net {ACC1:acc#166.itm(3)} -attr vt d
+load netBundle {ACC1:acc#166.itm} 4 {ACC1:acc#166.itm(0)} {ACC1:acc#166.itm(1)} {ACC1:acc#166.itm(2)} {ACC1:acc#166.itm(3)} -attr xrf 33625 -attr oid 789 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load net {conc#723.itm(0)} -attr vt d
+load net {conc#723.itm(1)} -attr vt d
+load net {conc#723.itm(2)} -attr vt d
+load netBundle {conc#723.itm} 3 {conc#723.itm(0)} {conc#723.itm(1)} {conc#723.itm(2)} -attr xrf 33626 -attr oid 790 -attr vt d -attr @path {/sobel/sobel:core/conc#723.itm}
+load net {ACC1:slc#31.itm(0)} -attr vt d
+load net {ACC1:slc#31.itm(1)} -attr vt d
+load netBundle {ACC1:slc#31.itm} 2 {ACC1:slc#31.itm(0)} {ACC1:slc#31.itm(1)} -attr xrf 33627 -attr oid 791 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#31.itm}
+load net {ACC1:acc#164.itm(0)} -attr vt d
+load net {ACC1:acc#164.itm(1)} -attr vt d
+load net {ACC1:acc#164.itm(2)} -attr vt d
+load netBundle {ACC1:acc#164.itm} 3 {ACC1:acc#164.itm(0)} {ACC1:acc#164.itm(1)} {ACC1:acc#164.itm(2)} -attr xrf 33628 -attr oid 792 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164.itm}
+load net {conc#724.itm(0)} -attr vt d
+load net {conc#724.itm(1)} -attr vt d
+load netBundle {conc#724.itm} 2 {conc#724.itm(0)} {conc#724.itm(1)} -attr xrf 33629 -attr oid 793 -attr vt d -attr @path {/sobel/sobel:core/conc#724.itm}
+load net {ACC1:conc#500.itm(0)} -attr vt d
+load net {ACC1:conc#500.itm(1)} -attr vt d
+load netBundle {ACC1:conc#500.itm} 2 {ACC1:conc#500.itm(0)} {ACC1:conc#500.itm(1)} -attr xrf 33630 -attr oid 794 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#500.itm}
+load net {ACC1:conc#504.itm(0)} -attr vt d
+load net {ACC1:conc#504.itm(1)} -attr vt d
+load net {ACC1:conc#504.itm(2)} -attr vt d
+load netBundle {ACC1:conc#504.itm} 3 {ACC1:conc#504.itm(0)} {ACC1:conc#504.itm(1)} {ACC1:conc#504.itm(2)} -attr xrf 33631 -attr oid 795 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#504.itm}
+load net {ACC1:slc#30.itm(0)} -attr vt d
+load net {ACC1:slc#30.itm(1)} -attr vt d
+load netBundle {ACC1:slc#30.itm} 2 {ACC1:slc#30.itm(0)} {ACC1:slc#30.itm(1)} -attr xrf 33632 -attr oid 796 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#30.itm}
+load net {ACC1:acc#163.itm(0)} -attr vt d
+load net {ACC1:acc#163.itm(1)} -attr vt d
+load net {ACC1:acc#163.itm(2)} -attr vt d
+load netBundle {ACC1:acc#163.itm} 3 {ACC1:acc#163.itm(0)} {ACC1:acc#163.itm(1)} {ACC1:acc#163.itm(2)} -attr xrf 33633 -attr oid 797 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163.itm}
+load net {conc#725.itm(0)} -attr vt d
+load net {conc#725.itm(1)} -attr vt d
+load netBundle {conc#725.itm} 2 {conc#725.itm(0)} {conc#725.itm(1)} -attr xrf 33634 -attr oid 798 -attr vt d -attr @path {/sobel/sobel:core/conc#725.itm}
+load net {ACC1:conc#498.itm(0)} -attr vt d
+load net {ACC1:conc#498.itm(1)} -attr vt d
+load netBundle {ACC1:conc#498.itm} 2 {ACC1:conc#498.itm(0)} {ACC1:conc#498.itm(1)} -attr xrf 33635 -attr oid 799 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#498.itm}
+load net {ACC1:slc#35.itm(0)} -attr vt d
+load net {ACC1:slc#35.itm(1)} -attr vt d
+load netBundle {ACC1:slc#35.itm} 2 {ACC1:slc#35.itm(0)} {ACC1:slc#35.itm(1)} -attr xrf 33636 -attr oid 800 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#35.itm}
+load net {ACC1:acc#168.itm(0)} -attr vt d
+load net {ACC1:acc#168.itm(1)} -attr vt d
+load net {ACC1:acc#168.itm(2)} -attr vt d
+load netBundle {ACC1:acc#168.itm} 3 {ACC1:acc#168.itm(0)} {ACC1:acc#168.itm(1)} {ACC1:acc#168.itm(2)} -attr xrf 33637 -attr oid 801 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168.itm}
+load net {conc#726.itm(0)} -attr vt d
+load net {conc#726.itm(1)} -attr vt d
+load netBundle {conc#726.itm} 2 {conc#726.itm(0)} {conc#726.itm(1)} -attr xrf 33638 -attr oid 802 -attr vt d -attr @path {/sobel/sobel:core/conc#726.itm}
+load net {ACC1:conc#508.itm(0)} -attr vt d
+load net {ACC1:conc#508.itm(1)} -attr vt d
+load netBundle {ACC1:conc#508.itm} 2 {ACC1:conc#508.itm(0)} {ACC1:conc#508.itm(1)} -attr xrf 33639 -attr oid 803 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#508.itm}
+load net {ACC1-3:exs#562.itm(0)} -attr vt d
+load net {ACC1-3:exs#562.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#562.itm} 2 {ACC1-3:exs#562.itm(0)} {ACC1-3:exs#562.itm(1)} -attr xrf 33640 -attr oid 804 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#562.itm}
+load net {ACC1-3:exs#551.itm(0)} -attr vt d
+load net {ACC1-3:exs#551.itm(1)} -attr vt d
+load netBundle {ACC1-3:exs#551.itm} 2 {ACC1-3:exs#551.itm(0)} {ACC1-3:exs#551.itm(1)} -attr xrf 33641 -attr oid 805 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#551.itm}
+load net {ACC1:acc#170.itm(0)} -attr vt d
+load net {ACC1:acc#170.itm(1)} -attr vt d
+load net {ACC1:acc#170.itm(2)} -attr vt d
+load netBundle {ACC1:acc#170.itm} 3 {ACC1:acc#170.itm(0)} {ACC1:acc#170.itm(1)} {ACC1:acc#170.itm(2)} -attr xrf 33642 -attr oid 806 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170.itm}
+load net {conc#727.itm(0)} -attr vt d
+load net {conc#727.itm(1)} -attr vt d
+load net {conc#727.itm(2)} -attr vt d
+load netBundle {conc#727.itm} 3 {conc#727.itm(0)} {conc#727.itm(1)} {conc#727.itm(2)} -attr xrf 33643 -attr oid 807 -attr vt d -attr @path {/sobel/sobel:core/conc#727.itm}
+load net {ACC1:conc#513.itm(0)} -attr vt d
+load net {ACC1:conc#513.itm(1)} -attr vt d
+load netBundle {ACC1:conc#513.itm} 2 {ACC1:conc#513.itm(0)} {ACC1:conc#513.itm(1)} -attr xrf 33644 -attr oid 808 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#513.itm}
+load net {ACC1:acc#133.itm(0)} -attr vt d
+load net {ACC1:acc#133.itm(1)} -attr vt d
+load net {ACC1:acc#133.itm(2)} -attr vt d
+load net {ACC1:acc#133.itm(3)} -attr vt d
+load net {ACC1:acc#133.itm(4)} -attr vt d
+load net {ACC1:acc#133.itm(5)} -attr vt d
+load net {ACC1:acc#133.itm(6)} -attr vt d
+load net {ACC1:acc#133.itm(7)} -attr vt d
+load net {ACC1:acc#133.itm(8)} -attr vt d
+load net {ACC1:acc#133.itm(9)} -attr vt d
+load net {ACC1:acc#133.itm(10)} -attr vt d
+load netBundle {ACC1:acc#133.itm} 11 {ACC1:acc#133.itm(0)} {ACC1:acc#133.itm(1)} {ACC1:acc#133.itm(2)} {ACC1:acc#133.itm(3)} {ACC1:acc#133.itm(4)} {ACC1:acc#133.itm(5)} {ACC1:acc#133.itm(6)} {ACC1:acc#133.itm(7)} {ACC1:acc#133.itm(8)} {ACC1:acc#133.itm(9)} {ACC1:acc#133.itm(10)} -attr xrf 33645 -attr oid 809 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:not.itm(0)} -attr vt d
+load net {ACC1:not.itm(1)} -attr vt d
+load net {ACC1:not.itm(2)} -attr vt d
+load net {ACC1:not.itm(3)} -attr vt d
+load net {ACC1:not.itm(4)} -attr vt d
+load net {ACC1:not.itm(5)} -attr vt d
+load net {ACC1:not.itm(6)} -attr vt d
+load net {ACC1:not.itm(7)} -attr vt d
+load net {ACC1:not.itm(8)} -attr vt d
+load net {ACC1:not.itm(9)} -attr vt d
+load netBundle {ACC1:not.itm} 10 {ACC1:not.itm(0)} {ACC1:not.itm(1)} {ACC1:not.itm(2)} {ACC1:not.itm(3)} {ACC1:not.itm(4)} {ACC1:not.itm(5)} {ACC1:not.itm(6)} {ACC1:not.itm(7)} {ACC1:not.itm(8)} {ACC1:not.itm(9)} -attr xrf 33646 -attr oid 810 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {slc(regs.regs(0).sva#7).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#7).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#7).itm} 10 {slc(regs.regs(0).sva#7).itm(0)} {slc(regs.regs(0).sva#7).itm(1)} {slc(regs.regs(0).sva#7).itm(2)} {slc(regs.regs(0).sva#7).itm(3)} {slc(regs.regs(0).sva#7).itm(4)} {slc(regs.regs(0).sva#7).itm(5)} {slc(regs.regs(0).sva#7).itm(6)} {slc(regs.regs(0).sva#7).itm(7)} {slc(regs.regs(0).sva#7).itm(8)} {slc(regs.regs(0).sva#7).itm(9)} -attr xrf 33647 -attr oid 811 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {ACC1:not#156.itm(0)} -attr vt d
+load net {ACC1:not#156.itm(1)} -attr vt d
+load net {ACC1:not#156.itm(2)} -attr vt d
+load net {ACC1:not#156.itm(3)} -attr vt d
+load net {ACC1:not#156.itm(4)} -attr vt d
+load net {ACC1:not#156.itm(5)} -attr vt d
+load net {ACC1:not#156.itm(6)} -attr vt d
+load net {ACC1:not#156.itm(7)} -attr vt d
+load net {ACC1:not#156.itm(8)} -attr vt d
+load net {ACC1:not#156.itm(9)} -attr vt d
+load netBundle {ACC1:not#156.itm} 10 {ACC1:not#156.itm(0)} {ACC1:not#156.itm(1)} {ACC1:not#156.itm(2)} {ACC1:not#156.itm(3)} {ACC1:not#156.itm(4)} {ACC1:not#156.itm(5)} {ACC1:not#156.itm(6)} {ACC1:not#156.itm(7)} {ACC1:not#156.itm(8)} {ACC1:not#156.itm(9)} -attr xrf 33648 -attr oid 812 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {slc(regs.regs(0).sva#8).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#8).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#8).itm} 10 {slc(regs.regs(0).sva#8).itm(0)} {slc(regs.regs(0).sva#8).itm(1)} {slc(regs.regs(0).sva#8).itm(2)} {slc(regs.regs(0).sva#8).itm(3)} {slc(regs.regs(0).sva#8).itm(4)} {slc(regs.regs(0).sva#8).itm(5)} {slc(regs.regs(0).sva#8).itm(6)} {slc(regs.regs(0).sva#8).itm(7)} {slc(regs.regs(0).sva#8).itm(8)} {slc(regs.regs(0).sva#8).itm(9)} -attr xrf 33649 -attr oid 813 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {ACC1:acc#132.itm(0)} -attr vt d
+load net {ACC1:acc#132.itm(1)} -attr vt d
+load net {ACC1:acc#132.itm(2)} -attr vt d
+load net {ACC1:acc#132.itm(3)} -attr vt d
+load net {ACC1:acc#132.itm(4)} -attr vt d
+load net {ACC1:acc#132.itm(5)} -attr vt d
+load net {ACC1:acc#132.itm(6)} -attr vt d
+load net {ACC1:acc#132.itm(7)} -attr vt d
+load net {ACC1:acc#132.itm(8)} -attr vt d
+load net {ACC1:acc#132.itm(9)} -attr vt d
+load net {ACC1:acc#132.itm(10)} -attr vt d
+load netBundle {ACC1:acc#132.itm} 11 {ACC1:acc#132.itm(0)} {ACC1:acc#132.itm(1)} {ACC1:acc#132.itm(2)} {ACC1:acc#132.itm(3)} {ACC1:acc#132.itm(4)} {ACC1:acc#132.itm(5)} {ACC1:acc#132.itm(6)} {ACC1:acc#132.itm(7)} {ACC1:acc#132.itm(8)} {ACC1:acc#132.itm(9)} {ACC1:acc#132.itm(10)} -attr xrf 33650 -attr oid 814 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:not#157.itm(0)} -attr vt d
+load net {ACC1:not#157.itm(1)} -attr vt d
+load net {ACC1:not#157.itm(2)} -attr vt d
+load net {ACC1:not#157.itm(3)} -attr vt d
+load net {ACC1:not#157.itm(4)} -attr vt d
+load net {ACC1:not#157.itm(5)} -attr vt d
+load net {ACC1:not#157.itm(6)} -attr vt d
+load net {ACC1:not#157.itm(7)} -attr vt d
+load net {ACC1:not#157.itm(8)} -attr vt d
+load net {ACC1:not#157.itm(9)} -attr vt d
+load netBundle {ACC1:not#157.itm} 10 {ACC1:not#157.itm(0)} {ACC1:not#157.itm(1)} {ACC1:not#157.itm(2)} {ACC1:not#157.itm(3)} {ACC1:not#157.itm(4)} {ACC1:not#157.itm(5)} {ACC1:not#157.itm(6)} {ACC1:not#157.itm(7)} {ACC1:not#157.itm(8)} {ACC1:not#157.itm(9)} -attr xrf 33651 -attr oid 815 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {slc(regs.regs(0).sva#9).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva#9).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva#9).itm} 10 {slc(regs.regs(0).sva#9).itm(0)} {slc(regs.regs(0).sva#9).itm(1)} {slc(regs.regs(0).sva#9).itm(2)} {slc(regs.regs(0).sva#9).itm(3)} {slc(regs.regs(0).sva#9).itm(4)} {slc(regs.regs(0).sva#9).itm(5)} {slc(regs.regs(0).sva#9).itm(6)} {slc(regs.regs(0).sva#9).itm(7)} {slc(regs.regs(0).sva#9).itm(8)} {slc(regs.regs(0).sva#9).itm(9)} -attr xrf 33652 -attr oid 816 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {ACC1:acc#141.itm(0)} -attr vt d
+load net {ACC1:acc#141.itm(1)} -attr vt d
+load net {ACC1:acc#141.itm(2)} -attr vt d
+load netBundle {ACC1:acc#141.itm} 3 {ACC1:acc#141.itm(0)} {ACC1:acc#141.itm(1)} {ACC1:acc#141.itm(2)} -attr xrf 33653 -attr oid 817 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141.itm}
+load net {conc#728.itm(0)} -attr vt d
+load net {conc#728.itm(1)} -attr vt d
+load net {conc#728.itm(2)} -attr vt d
+load netBundle {conc#728.itm} 3 {conc#728.itm(0)} {conc#728.itm(1)} {conc#728.itm(2)} -attr xrf 33654 -attr oid 818 -attr vt d -attr @path {/sobel/sobel:core/conc#728.itm}
+load net {ACC1:conc#459.itm(0)} -attr vt d
+load net {ACC1:conc#459.itm(1)} -attr vt d
+load netBundle {ACC1:conc#459.itm} 2 {ACC1:conc#459.itm(0)} {ACC1:conc#459.itm(1)} -attr xrf 33655 -attr oid 819 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#459.itm}
+load net {ACC1:acc#140.itm(0)} -attr vt d
+load net {ACC1:acc#140.itm(1)} -attr vt d
+load net {ACC1:acc#140.itm(2)} -attr vt d
+load net {ACC1:acc#140.itm(3)} -attr vt d
+load netBundle {ACC1:acc#140.itm} 4 {ACC1:acc#140.itm(0)} {ACC1:acc#140.itm(1)} {ACC1:acc#140.itm(2)} {ACC1:acc#140.itm(3)} -attr xrf 33656 -attr oid 820 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load net {conc#729.itm(0)} -attr vt d
+load net {conc#729.itm(1)} -attr vt d
+load net {conc#729.itm(2)} -attr vt d
+load netBundle {conc#729.itm} 3 {conc#729.itm(0)} {conc#729.itm(1)} {conc#729.itm(2)} -attr xrf 33657 -attr oid 821 -attr vt d -attr @path {/sobel/sobel:core/conc#729.itm}
+load net {ACC1-1:not#145.itm(0)} -attr vt d
+load net {ACC1-1:not#145.itm(1)} -attr vt d
+load netBundle {ACC1-1:not#145.itm} 2 {ACC1-1:not#145.itm(0)} {ACC1-1:not#145.itm(1)} -attr xrf 33658 -attr oid 822 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#145.itm}
+load net {slc(ACC1:acc#116.psp#1.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#116.psp#1.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#116.psp#1.sva).itm} 2 {slc(ACC1:acc#116.psp#1.sva).itm(0)} {slc(ACC1:acc#116.psp#1.sva).itm(1)} -attr xrf 33659 -attr oid 823 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp#1.sva).itm}
+load net {conc#730.itm(0)} -attr vt d
+load net {conc#730.itm(1)} -attr vt d
+load netBundle {conc#730.itm} 2 {conc#730.itm(0)} {conc#730.itm(1)} -attr xrf 33660 -attr oid 824 -attr vt d -attr @path {/sobel/sobel:core/conc#730.itm}
+load net {ACC1:slc#10.itm(0)} -attr vt d
+load net {ACC1:slc#10.itm(1)} -attr vt d
+load net {ACC1:slc#10.itm(2)} -attr vt d
+load net {ACC1:slc#10.itm(3)} -attr vt d
+load netBundle {ACC1:slc#10.itm} 4 {ACC1:slc#10.itm(0)} {ACC1:slc#10.itm(1)} {ACC1:slc#10.itm(2)} {ACC1:slc#10.itm(3)} -attr xrf 33661 -attr oid 825 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#10.itm}
+load net {ACC1:acc#138.itm(0)} -attr vt d
+load net {ACC1:acc#138.itm(1)} -attr vt d
+load net {ACC1:acc#138.itm(2)} -attr vt d
+load net {ACC1:acc#138.itm(3)} -attr vt d
+load net {ACC1:acc#138.itm(4)} -attr vt d
+load netBundle {ACC1:acc#138.itm} 5 {ACC1:acc#138.itm(0)} {ACC1:acc#138.itm(1)} {ACC1:acc#138.itm(2)} {ACC1:acc#138.itm(3)} {ACC1:acc#138.itm(4)} -attr xrf 33662 -attr oid 826 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {conc#731.itm(0)} -attr vt d
+load net {conc#731.itm(1)} -attr vt d
+load net {conc#731.itm(2)} -attr vt d
+load net {conc#731.itm(3)} -attr vt d
+load netBundle {conc#731.itm} 4 {conc#731.itm(0)} {conc#731.itm(1)} {conc#731.itm(2)} {conc#731.itm(3)} -attr xrf 33663 -attr oid 827 -attr vt d -attr @path {/sobel/sobel:core/conc#731.itm}
+load net {ACC1:slc#8.itm(0)} -attr vt d
+load net {ACC1:slc#8.itm(1)} -attr vt d
+load net {ACC1:slc#8.itm(2)} -attr vt d
+load netBundle {ACC1:slc#8.itm} 3 {ACC1:slc#8.itm(0)} {ACC1:slc#8.itm(1)} {ACC1:slc#8.itm(2)} -attr xrf 33664 -attr oid 828 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#8.itm}
+load net {ACC1:acc#136.itm(0)} -attr vt d
+load net {ACC1:acc#136.itm(1)} -attr vt d
+load net {ACC1:acc#136.itm(2)} -attr vt d
+load net {ACC1:acc#136.itm(3)} -attr vt d
+load netBundle {ACC1:acc#136.itm} 4 {ACC1:acc#136.itm(0)} {ACC1:acc#136.itm(1)} {ACC1:acc#136.itm(2)} {ACC1:acc#136.itm(3)} -attr xrf 33665 -attr oid 829 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load net {conc#732.itm(0)} -attr vt d
+load net {conc#732.itm(1)} -attr vt d
+load netBundle {conc#732.itm} 2 {conc#732.itm(0)} {conc#732.itm(1)} -attr xrf 33666 -attr oid 830 -attr vt d -attr @path {/sobel/sobel:core/conc#732.itm}
+load net {ACC1:conc#448.itm(0)} -attr vt d
+load net {ACC1:conc#448.itm(1)} -attr vt d
+load netBundle {ACC1:conc#448.itm} 2 {ACC1:conc#448.itm(0)} {ACC1:conc#448.itm(1)} -attr xrf 33667 -attr oid 831 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#448.itm}
+load net {conc#733.itm(0)} -attr vt d
+load net {conc#733.itm(1)} -attr vt d
+load net {conc#733.itm(2)} -attr vt d
+load net {conc#733.itm(3)} -attr vt d
+load netBundle {conc#733.itm} 4 {conc#733.itm(0)} {conc#733.itm(1)} {conc#733.itm(2)} {conc#733.itm(3)} -attr xrf 33668 -attr oid 832 -attr vt d -attr @path {/sobel/sobel:core/conc#733.itm}
+load net {ACC1:slc.itm(0)} -attr vt d
+load net {ACC1:slc.itm(1)} -attr vt d
+load net {ACC1:slc.itm(2)} -attr vt d
+load netBundle {ACC1:slc.itm} 3 {ACC1:slc.itm(0)} {ACC1:slc.itm(1)} {ACC1:slc.itm(2)} -attr xrf 33669 -attr oid 833 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#137.itm(0)} -attr vt d
+load net {ACC1:acc#137.itm(1)} -attr vt d
+load net {ACC1:acc#137.itm(2)} -attr vt d
+load net {ACC1:acc#137.itm(3)} -attr vt d
+load netBundle {ACC1:acc#137.itm} 4 {ACC1:acc#137.itm(0)} {ACC1:acc#137.itm(1)} {ACC1:acc#137.itm(2)} {ACC1:acc#137.itm(3)} -attr xrf 33670 -attr oid 834 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load net {conc#734.itm(0)} -attr vt d
+load net {conc#734.itm(1)} -attr vt d
+load net {conc#734.itm(2)} -attr vt d
+load netBundle {conc#734.itm} 3 {conc#734.itm(0)} {conc#734.itm(1)} {conc#734.itm(2)} -attr xrf 33671 -attr oid 835 -attr vt d -attr @path {/sobel/sobel:core/conc#734.itm}
+load net {ACC1:slc#7.itm(0)} -attr vt d
+load net {ACC1:slc#7.itm(1)} -attr vt d
+load netBundle {ACC1:slc#7.itm} 2 {ACC1:slc#7.itm(0)} {ACC1:slc#7.itm(1)} -attr xrf 33672 -attr oid 836 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#7.itm}
+load net {ACC1:acc#135.itm(0)} -attr vt d
+load net {ACC1:acc#135.itm(1)} -attr vt d
+load net {ACC1:acc#135.itm(2)} -attr vt d
+load netBundle {ACC1:acc#135.itm} 3 {ACC1:acc#135.itm(0)} {ACC1:acc#135.itm(1)} {ACC1:acc#135.itm(2)} -attr xrf 33673 -attr oid 837 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135.itm}
+load net {conc#735.itm(0)} -attr vt d
+load net {conc#735.itm(1)} -attr vt d
+load netBundle {conc#735.itm} 2 {conc#735.itm(0)} {conc#735.itm(1)} -attr xrf 33674 -attr oid 838 -attr vt d -attr @path {/sobel/sobel:core/conc#735.itm}
+load net {ACC1:conc#446.itm(0)} -attr vt d
+load net {ACC1:conc#446.itm(1)} -attr vt d
+load netBundle {ACC1:conc#446.itm} 2 {ACC1:conc#446.itm(0)} {ACC1:conc#446.itm(1)} -attr xrf 33675 -attr oid 839 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#446.itm}
+load net {ACC1:conc#450.itm(0)} -attr vt d
+load net {ACC1:conc#450.itm(1)} -attr vt d
+load net {ACC1:conc#450.itm(2)} -attr vt d
+load netBundle {ACC1:conc#450.itm} 3 {ACC1:conc#450.itm(0)} {ACC1:conc#450.itm(1)} {ACC1:conc#450.itm(2)} -attr xrf 33676 -attr oid 840 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#450.itm}
+load net {ACC1:slc#9.itm(0)} -attr vt d
+load net {ACC1:slc#9.itm(1)} -attr vt d
+load netBundle {ACC1:slc#9.itm} 2 {ACC1:slc#9.itm(0)} {ACC1:slc#9.itm(1)} -attr xrf 33677 -attr oid 841 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#9.itm}
+load net {ACC1:acc#134.itm(0)} -attr vt d
+load net {ACC1:acc#134.itm(1)} -attr vt d
+load net {ACC1:acc#134.itm(2)} -attr vt d
+load netBundle {ACC1:acc#134.itm} 3 {ACC1:acc#134.itm(0)} {ACC1:acc#134.itm(1)} {ACC1:acc#134.itm(2)} -attr xrf 33678 -attr oid 842 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134.itm}
+load net {conc#736.itm(0)} -attr vt d
+load net {conc#736.itm(1)} -attr vt d
+load netBundle {conc#736.itm} 2 {conc#736.itm(0)} {conc#736.itm(1)} -attr xrf 33679 -attr oid 843 -attr vt d -attr @path {/sobel/sobel:core/conc#736.itm}
+load net {ACC1:conc#444.itm(0)} -attr vt d
+load net {ACC1:conc#444.itm(1)} -attr vt d
+load netBundle {ACC1:conc#444.itm} 2 {ACC1:conc#444.itm(0)} {ACC1:conc#444.itm(1)} -attr xrf 33680 -attr oid 844 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#444.itm}
+load net {ACC1:slc#11.itm(0)} -attr vt d
+load net {ACC1:slc#11.itm(1)} -attr vt d
+load netBundle {ACC1:slc#11.itm} 2 {ACC1:slc#11.itm(0)} {ACC1:slc#11.itm(1)} -attr xrf 33681 -attr oid 845 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#139.itm(0)} -attr vt d
+load net {ACC1:acc#139.itm(1)} -attr vt d
+load net {ACC1:acc#139.itm(2)} -attr vt d
+load netBundle {ACC1:acc#139.itm} 3 {ACC1:acc#139.itm(0)} {ACC1:acc#139.itm(1)} {ACC1:acc#139.itm(2)} -attr xrf 33682 -attr oid 846 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139.itm}
+load net {conc#737.itm(0)} -attr vt d
+load net {conc#737.itm(1)} -attr vt d
+load netBundle {conc#737.itm} 2 {conc#737.itm(0)} {conc#737.itm(1)} -attr xrf 33683 -attr oid 847 -attr vt d -attr @path {/sobel/sobel:core/conc#737.itm}
+load net {ACC1:conc#454.itm(0)} -attr vt d
+load net {ACC1:conc#454.itm(1)} -attr vt d
+load netBundle {ACC1:conc#454.itm} 2 {ACC1:conc#454.itm(0)} {ACC1:conc#454.itm(1)} -attr xrf 33684 -attr oid 848 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#454.itm}
+load net {ACC1:exs#858.itm(0)} -attr vt d
+load net {ACC1:exs#858.itm(1)} -attr vt d
+load netBundle {ACC1:exs#858.itm} 2 {ACC1:exs#858.itm(0)} {ACC1:exs#858.itm(1)} -attr xrf 33685 -attr oid 849 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#858.itm}
+load net {ACC1:exs#833.itm(0)} -attr vt d
+load net {ACC1:exs#833.itm(1)} -attr vt d
+load netBundle {ACC1:exs#833.itm} 2 {ACC1:exs#833.itm(0)} {ACC1:exs#833.itm(1)} -attr xrf 33686 -attr oid 850 -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#833.itm}
+load net {ACC1:acc#169.itm(0)} -attr vt d
+load net {ACC1:acc#169.itm(1)} -attr vt d
+load net {ACC1:acc#169.itm(2)} -attr vt d
+load net {ACC1:acc#169.itm(3)} -attr vt d
+load netBundle {ACC1:acc#169.itm} 4 {ACC1:acc#169.itm(0)} {ACC1:acc#169.itm(1)} {ACC1:acc#169.itm(2)} {ACC1:acc#169.itm(3)} -attr xrf 33687 -attr oid 851 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load net {conc#738.itm(0)} -attr vt d
+load net {conc#738.itm(1)} -attr vt d
+load net {conc#738.itm(2)} -attr vt d
+load netBundle {conc#738.itm} 3 {conc#738.itm(0)} {conc#738.itm(1)} {conc#738.itm(2)} -attr xrf 33688 -attr oid 852 -attr vt d -attr @path {/sobel/sobel:core/conc#738.itm}
+load net {ACC1-3:not#145.itm(0)} -attr vt d
+load net {ACC1-3:not#145.itm(1)} -attr vt d
+load netBundle {ACC1-3:not#145.itm} 2 {ACC1-3:not#145.itm(0)} {ACC1-3:not#145.itm(1)} -attr xrf 33689 -attr oid 853 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#145.itm}
+load net {slc(ACC1:acc#116.psp.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#116.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#116.psp.sva).itm} 2 {slc(ACC1:acc#116.psp.sva).itm(0)} {slc(ACC1:acc#116.psp.sva).itm(1)} -attr xrf 33690 -attr oid 854 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp.sva).itm}
+load net {conc#739.itm(0)} -attr vt d
+load net {conc#739.itm(1)} -attr vt d
+load netBundle {conc#739.itm} 2 {conc#739.itm(0)} {conc#739.itm(1)} -attr xrf 33691 -attr oid 855 -attr vt d -attr @path {/sobel/sobel:core/conc#739.itm}
+load net {slc(FRAME:p#1.sva#2).itm(0)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(1)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(2)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(3)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(4)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(5)} -attr vt d
+load net {slc(FRAME:p#1.sva#2).itm(6)} -attr vt d
+load netBundle {slc(FRAME:p#1.sva#2).itm} 7 {slc(FRAME:p#1.sva#2).itm(0)} {slc(FRAME:p#1.sva#2).itm(1)} {slc(FRAME:p#1.sva#2).itm(2)} {slc(FRAME:p#1.sva#2).itm(3)} {slc(FRAME:p#1.sva#2).itm(4)} {slc(FRAME:p#1.sva#2).itm(5)} {slc(FRAME:p#1.sva#2).itm(6)} -attr xrf 33692 -attr oid 856 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:for:exs.itm(0)} -attr vt d
+load net {FRAME:for:exs.itm(1)} -attr vt d
+load net {FRAME:for:exs.itm(2)} -attr vt d
+load net {FRAME:for:exs.itm(3)} -attr vt d
+load net {FRAME:for:exs.itm(4)} -attr vt d
+load net {FRAME:for:exs.itm(5)} -attr vt d
+load net {FRAME:for:exs.itm(6)} -attr vt d
+load net {FRAME:for:exs.itm(7)} -attr vt d
+load net {FRAME:for:exs.itm(8)} -attr vt d
+load net {FRAME:for:exs.itm(9)} -attr vt d
+load net {FRAME:for:exs.itm(10)} -attr vt d
+load net {FRAME:for:exs.itm(11)} -attr vt d
+load net {FRAME:for:exs.itm(12)} -attr vt d
+load net {FRAME:for:exs.itm(13)} -attr vt d
+load net {FRAME:for:exs.itm(14)} -attr vt d
+load net {FRAME:for:exs.itm(15)} -attr vt d
+load net {FRAME:for:exs.itm(16)} -attr vt d
+load net {FRAME:for:exs.itm(17)} -attr vt d
+load net {FRAME:for:exs.itm(18)} -attr vt d
+load netBundle {FRAME:for:exs.itm} 19 {FRAME:for:exs.itm(0)} {FRAME:for:exs.itm(1)} {FRAME:for:exs.itm(2)} {FRAME:for:exs.itm(3)} {FRAME:for:exs.itm(4)} {FRAME:for:exs.itm(5)} {FRAME:for:exs.itm(6)} {FRAME:for:exs.itm(7)} {FRAME:for:exs.itm(8)} {FRAME:for:exs.itm(9)} {FRAME:for:exs.itm(10)} {FRAME:for:exs.itm(11)} {FRAME:for:exs.itm(12)} {FRAME:for:exs.itm(13)} {FRAME:for:exs.itm(14)} {FRAME:for:exs.itm(15)} {FRAME:for:exs.itm(16)} {FRAME:for:exs.itm(17)} {FRAME:for:exs.itm(18)} -attr xrf 33693 -attr oid 857 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {slc(acc.imod#18.sva).itm(0)} -attr vt d
+load net {slc(acc.imod#18.sva).itm(1)} -attr vt d
+load netBundle {slc(acc.imod#18.sva).itm} 2 {slc(acc.imod#18.sva).itm(0)} {slc(acc.imod#18.sva).itm(1)} -attr xrf 33694 -attr oid 858 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva).itm}
+load net {slc(ACC1:acc#110.psp#2.sva).itm(0)} -attr vt d
+load net {slc(ACC1:acc#110.psp#2.sva).itm(1)} -attr vt d
+load net {slc(ACC1:acc#110.psp#2.sva).itm(2)} -attr vt d
+load netBundle {slc(ACC1:acc#110.psp#2.sva).itm} 3 {slc(ACC1:acc#110.psp#2.sva).itm(0)} {slc(ACC1:acc#110.psp#2.sva).itm(1)} {slc(ACC1:acc#110.psp#2.sva).itm(2)} -attr xrf 33695 -attr oid 859 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.sva).itm}
+load net {ACC1:slc#21.itm(0)} -attr vt d
+load net {ACC1:slc#21.itm(1)} -attr vt d
+load netBundle {ACC1:slc#21.itm} 2 {ACC1:slc#21.itm(0)} {ACC1:slc#21.itm(1)} -attr xrf 33696 -attr oid 860 -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#21.itm}
+load net {ACC1:acc#151.itm(0)} -attr vt d
+load net {ACC1:acc#151.itm(1)} -attr vt d
+load net {ACC1:acc#151.itm(2)} -attr vt d
+load netBundle {ACC1:acc#151.itm} 3 {ACC1:acc#151.itm(0)} {ACC1:acc#151.itm(1)} {ACC1:acc#151.itm(2)} -attr xrf 33697 -attr oid 861 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151.itm}
+load net {conc#740.itm(0)} -attr vt d
+load net {conc#740.itm(1)} -attr vt d
+load net {conc#740.itm(2)} -attr vt d
+load netBundle {conc#740.itm} 3 {conc#740.itm(0)} {conc#740.itm(1)} {conc#740.itm(2)} -attr xrf 33698 -attr oid 862 -attr vt d -attr @path {/sobel/sobel:core/conc#740.itm}
+load net {ACC1:conc#477.itm(0)} -attr vt d
+load net {ACC1:conc#477.itm(1)} -attr vt d
+load netBundle {ACC1:conc#477.itm} 2 {ACC1:conc#477.itm(0)} {ACC1:conc#477.itm(1)} -attr xrf 33699 -attr oid 863 -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#477.itm}
+load net {slc(ACC1:acc#118.psp#1.sva)#2.itm(0)} -attr vt d
+load net {slc(ACC1:acc#118.psp#1.sva)#2.itm(1)} -attr vt d
+load netBundle {slc(ACC1:acc#118.psp#1.sva)#2.itm} 2 {slc(ACC1:acc#118.psp#1.sva)#2.itm(0)} {slc(ACC1:acc#118.psp#1.sva)#2.itm(1)} -attr xrf 33700 -attr oid 864 -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp#1.sva)#2.itm}
+load net {clk} -attr xrf 33701 -attr oid 865
+load net {clk} -port {clk} -attr xrf 33702 -attr oid 866
+load net {en} -attr xrf 33703 -attr oid 867
+load net {en} -port {en} -attr xrf 33704 -attr oid 868
+load net {arst_n} -attr xrf 33705 -attr oid 869
+load net {arst_n} -port {arst_n} -attr xrf 33706 -attr oid 870
+load net {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 33707 -attr oid 871 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(0)} -port {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -port {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -port {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -port {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -port {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -port {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -port {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -port {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -port {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -port {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -port {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -port {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -port {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -port {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -port {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -port {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -port {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -port {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -port {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -port {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -port {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -port {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -port {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -port {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -port {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -port {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -port {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -port {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -port {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -port {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -port {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -port {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -port {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -port {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -port {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -port {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -port {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -port {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -port {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -port {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -port {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -port {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -port {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -port {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -port {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -port {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -port {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -port {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -port {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -port {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -port {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -port {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -port {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -port {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -port {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -port {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -port {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -port {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -port {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -port {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -port {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -port {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -port {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -port {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -port {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -port {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -port {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -port {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -port {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -port {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -port {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -port {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -port {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -port {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -port {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -port {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -port {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -port {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -port {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -port {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -port {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -port {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -port {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -port {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -port {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -port {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -port {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -port {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -port {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -port {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 33708 -attr oid 872 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d} 30 {vout:rsc:mgc_out_stdreg.d(0)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(29)} -attr xrf 33709 -attr oid 873 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -port {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -port {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -port {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -port {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -port {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -port {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -port {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -port {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -port {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -port {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -port {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -port {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -port {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -port {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -port {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -port {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -port {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -port {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -port {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -port {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -port {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -port {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -port {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -port {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -port {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -port {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -port {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -port {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -port {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -port {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:or" "or(2,10)" "INTERFACE" -attr xrf 33710 -attr oid 874 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or} -attr area 7.298324 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2)"
+load net {FRAME:acc#2.psp.sva(0)} -pin  "FRAME:or" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "FRAME:or" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "FRAME:or" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "FRAME:or" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "FRAME:or" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "FRAME:or" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "FRAME:or" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "FRAME:or" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "FRAME:or" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "FRAME:or" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#4.itm}
+load net {FRAME:acc#2.psp.sva(10)} -pin  "FRAME:or" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {FRAME:acc#2.psp.sva(11)} -pin  "FRAME:or" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(2)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(3)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(4)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(5)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(6)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(7)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(8)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:or" {A1(9)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {FRAME:or.itm(0)} -pin  "FRAME:or" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(1)} -pin  "FRAME:or" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(2)} -pin  "FRAME:or" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(3)} -pin  "FRAME:or" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(4)} -pin  "FRAME:or" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(5)} -pin  "FRAME:or" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(6)} -pin  "FRAME:or" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(7)} -pin  "FRAME:or" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(8)} -pin  "FRAME:or" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(9)} -pin  "FRAME:or" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load inst "FRAME:or#3" "or(2,6)" "INTERFACE" -attr xrf 33711 -attr oid 875 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3} -attr area 4.378994 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2)"
+load net {FRAME:acc#2.psp.sva(0)} -pin  "FRAME:or#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "FRAME:or#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "FRAME:or#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "FRAME:or#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "FRAME:or#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "FRAME:or#3" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#2.psp.sva)#3.itm}
+load net {FRAME:acc#2.psp.sva(10)} -pin  "FRAME:or#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {FRAME:acc#2.psp.sva(11)} -pin  "FRAME:or#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(2)} -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(3)} -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(4)} -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(5)} -attr @path {/sobel/sobel:core/conc#589.itm}
+load net {FRAME:or#3.itm(0)} -pin  "FRAME:or#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(1)} -pin  "FRAME:or#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(2)} -pin  "FRAME:or#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(3)} -pin  "FRAME:or#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(4)} -pin  "FRAME:or#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(5)} -pin  "FRAME:or#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load inst "nand" "nand(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "nand" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {main.stage_0#2} -pin  "nand" {A1(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {nand.itm} -pin  "nand" {Z(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load inst "mux" "mux(2,30)" "INTERFACE" -attr xrf 33712 -attr oid 876 -attr vt d -attr @path {/sobel/sobel:core/mux} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "mux" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "mux" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "mux" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "mux" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "mux" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "mux" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "mux" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "mux" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "mux" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "mux" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "mux" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "mux" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "mux" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "mux" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "mux" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "mux" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "mux" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "mux" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "mux" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "mux" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "mux" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "mux" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "mux" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "mux" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "mux" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "mux" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "mux" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "mux" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "mux" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "mux" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {FRAME:acc#2.psp.sva(0)} -pin  "mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(0)} -pin  "mux" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(1)} -pin  "mux" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(2)} -pin  "mux" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(3)} -pin  "mux" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(4)} -pin  "mux" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or#3.itm(5)} -pin  "mux" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "mux" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "mux" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "mux" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "mux" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(0)} -pin  "mux" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(1)} -pin  "mux" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(2)} -pin  "mux" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(3)} -pin  "mux" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(4)} -pin  "mux" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(5)} -pin  "mux" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(6)} -pin  "mux" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(7)} -pin  "mux" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(8)} -pin  "mux" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {FRAME:or.itm(9)} -pin  "mux" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#11.itm}
+load net {nand.itm} -pin  "mux" {S(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load net {mux.itm(0)} -pin  "mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "mux" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "mux" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "mux" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "mux" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "mux" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "mux" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "mux" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "mux" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "mux" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "mux" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "mux" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "mux" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "mux" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "mux" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "mux" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "mux" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "mux" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "mux" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "mux" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "mux" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 33713 -attr oid 877 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)}
+load net {mux.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 33714 -attr oid 878 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "mux#1" "mux(2,16)" "INTERFACE" -attr xrf 33715 -attr oid 879 -attr vt d -attr @path {/sobel/sobel:core/mux#1} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {in(2).sva#3(0)} -pin  "mux#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(1)} -pin  "mux#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(2)} -pin  "mux#1" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(3)} -pin  "mux#1" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(4)} -pin  "mux#1" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(5)} -pin  "mux#1" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(6)} -pin  "mux#1" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(7)} -pin  "mux#1" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(8)} -pin  "mux#1" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(9)} -pin  "mux#1" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(10)} -pin  "mux#1" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(11)} -pin  "mux#1" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(12)} -pin  "mux#1" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(13)} -pin  "mux#1" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(14)} -pin  "mux#1" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(15)} -pin  "mux#1" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#1(0)} -pin  "mux#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(1)} -pin  "mux#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(2)} -pin  "mux#1" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(3)} -pin  "mux#1" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(4)} -pin  "mux#1" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(5)} -pin  "mux#1" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(6)} -pin  "mux#1" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(7)} -pin  "mux#1" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(8)} -pin  "mux#1" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(9)} -pin  "mux#1" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(10)} -pin  "mux#1" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(11)} -pin  "mux#1" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(12)} -pin  "mux#1" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(13)} -pin  "mux#1" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(14)} -pin  "mux#1" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(15)} -pin  "mux#1" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {main.stage_0#2} -pin  "mux#1" {S(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {mux#1.itm(0)} -pin  "mux#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(1)} -pin  "mux#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(2)} -pin  "mux#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(3)} -pin  "mux#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(4)} -pin  "mux#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(5)} -pin  "mux#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(6)} -pin  "mux#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(7)} -pin  "mux#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(8)} -pin  "mux#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(9)} -pin  "mux#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(10)} -pin  "mux#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(11)} -pin  "mux#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(12)} -pin  "mux#1" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(13)} -pin  "mux#1" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(14)} -pin  "mux#1" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(15)} -pin  "mux#1" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load inst "reg(in(2).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 33716 -attr oid 880 -attr vt d -attr @path {/sobel/sobel:core/reg(in(2).sva#1)}
+load net {mux#1.itm(0)} -pin  "reg(in(2).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(1)} -pin  "reg(in(2).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(2)} -pin  "reg(in(2).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(3)} -pin  "reg(in(2).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(4)} -pin  "reg(in(2).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(5)} -pin  "reg(in(2).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(6)} -pin  "reg(in(2).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(7)} -pin  "reg(in(2).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(8)} -pin  "reg(in(2).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(9)} -pin  "reg(in(2).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(10)} -pin  "reg(in(2).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(11)} -pin  "reg(in(2).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(12)} -pin  "reg(in(2).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(13)} -pin  "reg(in(2).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(14)} -pin  "reg(in(2).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(15)} -pin  "reg(in(2).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(2).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(in(2).sva#1)" {clk} -attr xrf 33717 -attr oid 881 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(in(2).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(in(2).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {in(2).sva#1(0)} -pin  "reg(in(2).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(1)} -pin  "reg(in(2).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(2)} -pin  "reg(in(2).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(3)} -pin  "reg(in(2).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(4)} -pin  "reg(in(2).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(5)} -pin  "reg(in(2).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(6)} -pin  "reg(in(2).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(7)} -pin  "reg(in(2).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(8)} -pin  "reg(in(2).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(9)} -pin  "reg(in(2).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(10)} -pin  "reg(in(2).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(11)} -pin  "reg(in(2).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(12)} -pin  "reg(in(2).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(13)} -pin  "reg(in(2).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(14)} -pin  "reg(in(2).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(15)} -pin  "reg(in(2).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load inst "ACC2:acc#5" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 33718 -attr oid 882 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#5} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC2:acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#14.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC2:acc#5" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#13.itm}
+load net {ACC2:acc#5.itm(0)} -pin  "ACC2:acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#5.itm}
+load net {ACC2:acc#5.itm(1)} -pin  "ACC2:acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#5.itm}
+load inst "ACC1:mul#20" "mul(2,0,12,1,13)" "INTERFACE" -attr xrf 33719 -attr oid 883 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC2:acc#5.itm(0)} -pin  "ACC1:mul#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#5.itm}
+load net {ACC2:acc#5.itm(1)} -pin  "ACC1:mul#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#5.itm}
+load net {PWR} -pin  "ACC1:mul#20" {B(0)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(1)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(2)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(3)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(4)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(5)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(6)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(7)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(8)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {PWR} -pin  "ACC1:mul#20" {B(9)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {GND} -pin  "ACC1:mul#20" {B(10)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {PWR} -pin  "ACC1:mul#20" {B(11)} -attr @path {/sobel/sobel:core/Cn1535_12}
+load net {ACC1:mul#20.itm(0)} -pin  "ACC1:mul#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(1)} -pin  "ACC1:mul#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(2)} -pin  "ACC1:mul#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(3)} -pin  "ACC1:mul#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(4)} -pin  "ACC1:mul#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(5)} -pin  "ACC1:mul#20" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(6)} -pin  "ACC1:mul#20" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(7)} -pin  "ACC1:mul#20" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(8)} -pin  "ACC1:mul#20" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(9)} -pin  "ACC1:mul#20" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(10)} -pin  "ACC1:mul#20" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(11)} -pin  "ACC1:mul#20" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(12)} -pin  "ACC1:mul#20" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load inst "ACC2:acc#6" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 33720 -attr oid 884 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#6} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} -pin  "ACC2:acc#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#31.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} -pin  "ACC2:acc#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#31.itm}
+load net {ACC2:acc#6.itm(0)} -pin  "ACC2:acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#6.itm}
+load net {ACC2:acc#6.itm(1)} -pin  "ACC2:acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#6.itm}
+load inst "ACC1:mul#21" "mul(2,0,5,0,6)" "INTERFACE" -attr xrf 33721 -attr oid 885 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC2:acc#6.itm(0)} -pin  "ACC1:mul#21" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#6.itm}
+load net {ACC2:acc#6.itm(1)} -pin  "ACC1:mul#21" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#6.itm}
+load net {PWR} -pin  "ACC1:mul#21" {B(0)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#21" {B(1)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#21" {B(2)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul#21" {B(3)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul#21" {B(4)} -attr @path {/sobel/sobel:core/C21_5}
+load net {ACC1:mul#21.itm(0)} -pin  "ACC1:mul#21" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load net {ACC1:mul#21.itm(1)} -pin  "ACC1:mul#21" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load net {ACC1:mul#21.itm(2)} -pin  "ACC1:mul#21" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load net {ACC1:mul#21.itm(3)} -pin  "ACC1:mul#21" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load net {ACC1:mul#21.itm(4)} -pin  "ACC1:mul#21" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load net {ACC1:mul#21.itm(5)} -pin  "ACC1:mul#21" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#21.itm}
+load inst "ACC2:acc#3" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 33722 -attr oid 886 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#3} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(7)} -pin  "ACC2:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#3.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(7)} -pin  "ACC2:acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#2.itm}
+load net {ACC2:acc#3.itm(0)} -pin  "ACC2:acc#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#3.itm}
+load net {ACC2:acc#3.itm(1)} -pin  "ACC2:acc#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#3.itm}
+load inst "ACC1:mul#18" "mul(2,0,7,0,8)" "INTERFACE" -attr xrf 33723 -attr oid 887 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC2:acc#3.itm(0)} -pin  "ACC1:mul#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#3.itm}
+load net {ACC2:acc#3.itm(1)} -pin  "ACC1:mul#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#3.itm}
+load net {PWR} -pin  "ACC1:mul#18" {B(0)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#18" {B(1)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#18" {B(2)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#18" {B(3)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#18" {B(4)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#18" {B(5)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#18" {B(6)} -attr @path {/sobel/sobel:core/C85_7}
+load net {ACC1:mul#18.itm(0)} -pin  "ACC1:mul#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(1)} -pin  "ACC1:mul#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(2)} -pin  "ACC1:mul#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(3)} -pin  "ACC1:mul#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(4)} -pin  "ACC1:mul#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(5)} -pin  "ACC1:mul#18" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(6)} -pin  "ACC1:mul#18" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(7)} -pin  "ACC1:mul#18" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load inst "ACC2:acc" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 33724 -attr oid 888 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(5)} -pin  "ACC2:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#4.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(5)} -pin  "ACC2:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#3.itm}
+load net {ACC2:acc.itm(0)} -pin  "ACC2:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(1)} -pin  "ACC2:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load inst "ACC1:mul" "mul(2,0,5,0,6)" "INTERFACE" -attr xrf 33725 -attr oid 889 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC2:acc.itm(0)} -pin  "ACC1:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(1)} -pin  "ACC1:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {PWR} -pin  "ACC1:mul" {B(0)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul" {B(1)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul" {B(2)} -attr @path {/sobel/sobel:core/C21_5}
+load net {GND} -pin  "ACC1:mul" {B(3)} -attr @path {/sobel/sobel:core/C21_5}
+load net {PWR} -pin  "ACC1:mul" {B(4)} -attr @path {/sobel/sobel:core/C21_5}
+load net {ACC1:mul.itm(0)} -pin  "ACC1:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(1)} -pin  "ACC1:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(2)} -pin  "ACC1:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(3)} -pin  "ACC1:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(4)} -pin  "ACC1:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(5)} -pin  "ACC1:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load inst "ACC1:acc#330" "add(6,0,6,0,7)" "INTERFACE" -attr xrf 33726 -attr oid 890 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,7)"
+load net {ACC1:mul.itm(0)} -pin  "ACC1:acc#330" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(1)} -pin  "ACC1:acc#330" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(2)} -pin  "ACC1:acc#330" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(3)} -pin  "ACC1:acc#330" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(4)} -pin  "ACC1:acc#330" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:mul.itm(5)} -pin  "ACC1:acc#330" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#330" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#330" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {GND} -pin  "ACC1:acc#330" {B(2)} -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} -pin  "ACC1:acc#330" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {GND} -pin  "ACC1:acc#330" {B(4)} -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#330" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#590.itm}
+load net {ACC1:acc#330.itm(0)} -pin  "ACC1:acc#330" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(1)} -pin  "ACC1:acc#330" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(2)} -pin  "ACC1:acc#330" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(3)} -pin  "ACC1:acc#330" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(4)} -pin  "ACC1:acc#330" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(5)} -pin  "ACC1:acc#330" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(6)} -pin  "ACC1:acc#330" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load inst "ACC1:acc#334" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 33727 -attr oid 891 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:mul#18.itm(0)} -pin  "ACC1:acc#334" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(1)} -pin  "ACC1:acc#334" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(2)} -pin  "ACC1:acc#334" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(3)} -pin  "ACC1:acc#334" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(4)} -pin  "ACC1:acc#334" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(5)} -pin  "ACC1:acc#334" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(6)} -pin  "ACC1:acc#334" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:mul#18.itm(7)} -pin  "ACC1:acc#334" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#18.itm}
+load net {ACC1:acc#330.itm(0)} -pin  "ACC1:acc#334" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(1)} -pin  "ACC1:acc#334" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(2)} -pin  "ACC1:acc#334" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(3)} -pin  "ACC1:acc#334" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(4)} -pin  "ACC1:acc#334" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(5)} -pin  "ACC1:acc#334" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#330.itm(6)} -pin  "ACC1:acc#334" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#330.itm}
+load net {ACC1:acc#334.itm(0)} -pin  "ACC1:acc#334" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(1)} -pin  "ACC1:acc#334" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(2)} -pin  "ACC1:acc#334" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(3)} -pin  "ACC1:acc#334" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(4)} -pin  "ACC1:acc#334" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(5)} -pin  "ACC1:acc#334" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(6)} -pin  "ACC1:acc#334" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(7)} -pin  "ACC1:acc#334" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load inst "ACC1:acc#336" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 33728 -attr oid 892 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336} -attr area 10.253676 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,0,10)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#336" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#336" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(3)} -pin  "ACC1:acc#336" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(0)} -pin  "ACC1:acc#336" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(1)} -pin  "ACC1:acc#336" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(2)} -pin  "ACC1:acc#336" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(3)} -pin  "ACC1:acc#336" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(4)} -pin  "ACC1:acc#336" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:mul#21.itm(5)} -pin  "ACC1:acc#336" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc.itm}
+load net {ACC1:acc#334.itm(0)} -pin  "ACC1:acc#336" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(1)} -pin  "ACC1:acc#336" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(2)} -pin  "ACC1:acc#336" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(3)} -pin  "ACC1:acc#336" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(4)} -pin  "ACC1:acc#336" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(5)} -pin  "ACC1:acc#336" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(6)} -pin  "ACC1:acc#336" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#334.itm(7)} -pin  "ACC1:acc#336" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#334.itm}
+load net {ACC1:acc#336.itm(0)} -pin  "ACC1:acc#336" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(1)} -pin  "ACC1:acc#336" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(2)} -pin  "ACC1:acc#336" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(3)} -pin  "ACC1:acc#336" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(4)} -pin  "ACC1:acc#336" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(5)} -pin  "ACC1:acc#336" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(6)} -pin  "ACC1:acc#336" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(7)} -pin  "ACC1:acc#336" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(8)} -pin  "ACC1:acc#336" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(9)} -pin  "ACC1:acc#336" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load inst "ACC1:acc#310" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33729 -attr oid 893 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#310" {A(0)} -attr @path {/sobel/sobel:core/exs.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#310" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#310" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(0)} -pin  "ACC1:acc#310" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#793.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#310" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#793.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#310" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#793.itm}
+load net {ACC1:acc#310.itm(0)} -pin  "ACC1:acc#310" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(1)} -pin  "ACC1:acc#310" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(2)} -pin  "ACC1:acc#310" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load net {ACC1:acc#310.itm(3)} -pin  "ACC1:acc#310" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#310.itm}
+load inst "ACC1:acc#309" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33730 -attr oid 894 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#309" {A(0)} -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} -pin  "ACC1:acc#309" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} -pin  "ACC1:acc#309" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#54.itm}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(2)} -pin  "ACC1:acc#309" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#795.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#309" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#795.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#309" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#795.itm}
+load net {ACC1:acc#309.itm(0)} -pin  "ACC1:acc#309" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(1)} -pin  "ACC1:acc#309" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(2)} -pin  "ACC1:acc#309" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load net {ACC1:acc#309.itm(3)} -pin  "ACC1:acc#309" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#309.itm}
+load inst "ACC1:acc#319" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33731 -attr oid 895 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#310.itm(1)} -pin  "ACC1:acc#319" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#310.itm(2)} -pin  "ACC1:acc#319" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#310.itm(3)} -pin  "ACC1:acc#319" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#97.itm}
+load net {ACC1:acc#309.itm(1)} -pin  "ACC1:acc#319" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#309.itm(2)} -pin  "ACC1:acc#319" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#309.itm(3)} -pin  "ACC1:acc#319" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#96.itm}
+load net {ACC1:acc#319.itm(0)} -pin  "ACC1:acc#319" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(1)} -pin  "ACC1:acc#319" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(2)} -pin  "ACC1:acc#319" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(3)} -pin  "ACC1:acc#319" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load inst "ACC1:acc#307" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33732 -attr oid 896 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#307" {A(0)} -attr @path {/sobel/sobel:core/exs#28.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#307" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#28.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#307" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#28.itm}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(0)} -pin  "ACC1:acc#307" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#797.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#307" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#797.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#307" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#797.itm}
+load net {ACC1:acc#307.itm(0)} -pin  "ACC1:acc#307" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#307.itm(1)} -pin  "ACC1:acc#307" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#307.itm(2)} -pin  "ACC1:acc#307" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load net {ACC1:acc#307.itm(3)} -pin  "ACC1:acc#307" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#307.itm}
+load inst "ACC1-3:not#60" "not(1)" "INTERFACE" -attr xrf 33733 -attr oid 897 -attr @path {/sobel/sobel:core/ACC1-3:not#60} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#7.lpi#1.dfm:mx0(1)} -pin  "ACC1-3:not#60" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.lpi#1.dfm:mx0)#2.itm}
+load net {ACC1-3:not#60.itm} -pin  "ACC1-3:not#60" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#60.itm}
+load inst "ACC1-3:and#3" "and(3,1)" "INTERFACE" -attr xrf 33734 -attr oid 898 -attr @path {/sobel/sobel:core/ACC1-3:and#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1-3:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#19.itm}
+load net {ACC1-3:not#60.itm} -pin  "ACC1-3:and#3" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#60.itm}
+load net {acc.imod#7.lpi#1.dfm:mx0(0)} -pin  "ACC1-3:and#3" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.lpi#1.dfm:mx0)#1.itm}
+load net {ACC1-3:and#3.itm} -pin  "ACC1-3:and#3" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#3.itm}
+load inst "ACC1:acc#306" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33735 -attr oid 899 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#306" {A(0)} -attr @path {/sobel/sobel:core/exs#29.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#306" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#29.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#306" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#29.itm}
+load net {ACC1-3:and#3.itm} -pin  "ACC1:acc#306" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#799.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#306" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#799.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#306" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#799.itm}
+load net {ACC1:acc#306.itm(0)} -pin  "ACC1:acc#306" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(1)} -pin  "ACC1:acc#306" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(2)} -pin  "ACC1:acc#306" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load net {ACC1:acc#306.itm(3)} -pin  "ACC1:acc#306" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#306.itm}
+load inst "ACC1:acc#318" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33736 -attr oid 900 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#307.itm(1)} -pin  "ACC1:acc#318" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#307.itm(2)} -pin  "ACC1:acc#318" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#307.itm(3)} -pin  "ACC1:acc#318" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#94.itm}
+load net {ACC1:acc#306.itm(1)} -pin  "ACC1:acc#318" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#306.itm(2)} -pin  "ACC1:acc#318" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#306.itm(3)} -pin  "ACC1:acc#318" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#93.itm}
+load net {ACC1:acc#318.itm(0)} -pin  "ACC1:acc#318" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(1)} -pin  "ACC1:acc#318" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(2)} -pin  "ACC1:acc#318" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(3)} -pin  "ACC1:acc#318" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load inst "ACC1:acc#325" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 33737 -attr oid 901 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#319.itm(0)} -pin  "ACC1:acc#325" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(1)} -pin  "ACC1:acc#325" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(2)} -pin  "ACC1:acc#325" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#319.itm(3)} -pin  "ACC1:acc#325" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#319.itm}
+load net {ACC1:acc#318.itm(0)} -pin  "ACC1:acc#325" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(1)} -pin  "ACC1:acc#325" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(2)} -pin  "ACC1:acc#325" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#318.itm(3)} -pin  "ACC1:acc#325" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#318.itm}
+load net {ACC1:acc#325.itm(0)} -pin  "ACC1:acc#325" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(1)} -pin  "ACC1:acc#325" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(2)} -pin  "ACC1:acc#325" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(3)} -pin  "ACC1:acc#325" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(4)} -pin  "ACC1:acc#325" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load inst "ACC1-3:not#59" "not(1)" "INTERFACE" -attr xrf 33738 -attr oid 902 -attr @path {/sobel/sobel:core/ACC1-3:not#59} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1-3:not#59" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#20.itm}
+load net {ACC1-3:not#59.itm} -pin  "ACC1-3:not#59" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#59.itm}
+load inst "ACC1-3:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 33739 -attr oid 903 -attr @path {/sobel/sobel:core/ACC1-3:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {acc.imod#7.lpi#1.dfm:mx0(1)} -pin  "ACC1-3:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.lpi#1.dfm:mx0).itm}
+load net {ACC1-3:not#59.itm} -pin  "ACC1-3:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#59.itm}
+load net {ACC1-3:nand#1.itm} -pin  "ACC1-3:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand#1.itm}
+load inst "ACC1:acc#305" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33740 -attr oid 904 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#305" {A(0)} -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#305" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#305" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#55.itm}
+load net {ACC1-3:nand#1.itm} -pin  "ACC1:acc#305" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#801.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} -pin  "ACC1:acc#305" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#801.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} -pin  "ACC1:acc#305" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#801.itm}
+load net {ACC1:acc#305.itm(0)} -pin  "ACC1:acc#305" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(1)} -pin  "ACC1:acc#305" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(2)} -pin  "ACC1:acc#305" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load net {ACC1:acc#305.itm(3)} -pin  "ACC1:acc#305" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#305.itm}
+load inst "ACC1:acc#304" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33741 -attr oid 905 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#304" {A(0)} -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} -pin  "ACC1:acc#304" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} -pin  "ACC1:acc#304" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#56.itm}
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(0)} -pin  "ACC1:acc#304" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#803.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#304" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#803.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#304" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#803.itm}
+load net {ACC1:acc#304.itm(0)} -pin  "ACC1:acc#304" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(1)} -pin  "ACC1:acc#304" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(2)} -pin  "ACC1:acc#304" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load net {ACC1:acc#304.itm(3)} -pin  "ACC1:acc#304" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#304.itm}
+load inst "ACC1:acc#317" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33742 -attr oid 906 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#305.itm(1)} -pin  "ACC1:acc#317" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#92.itm}
+load net {ACC1:acc#305.itm(2)} -pin  "ACC1:acc#317" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#92.itm}
+load net {ACC1:acc#305.itm(3)} -pin  "ACC1:acc#317" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#92.itm}
+load net {ACC1:acc#304.itm(1)} -pin  "ACC1:acc#317" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#91.itm}
+load net {ACC1:acc#304.itm(2)} -pin  "ACC1:acc#317" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#91.itm}
+load net {ACC1:acc#304.itm(3)} -pin  "ACC1:acc#317" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#91.itm}
+load net {ACC1:acc#317.itm(0)} -pin  "ACC1:acc#317" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(1)} -pin  "ACC1:acc#317" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(2)} -pin  "ACC1:acc#317" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(3)} -pin  "ACC1:acc#317" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load inst "ACC1:acc#303" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33743 -attr oid 907 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#303" {A(0)} -attr @path {/sobel/sobel:core/exs#30.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#303" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#30.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#303" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#30.itm}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(2)} -pin  "ACC1:acc#303" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#805.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#303" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#805.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#303" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#805.itm}
+load net {ACC1:acc#303.itm(0)} -pin  "ACC1:acc#303" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(1)} -pin  "ACC1:acc#303" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(2)} -pin  "ACC1:acc#303" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load net {ACC1:acc#303.itm(3)} -pin  "ACC1:acc#303" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#303.itm}
+load inst "ACC1:acc#302" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33744 -attr oid 908 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#302" {A(0)} -attr @path {/sobel/sobel:core/exs#31.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#302" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#31.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#302" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#31.itm}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(1)} -pin  "ACC1:acc#302" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#807.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#302" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#807.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#302" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#807.itm}
+load net {ACC1:acc#302.itm(0)} -pin  "ACC1:acc#302" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(1)} -pin  "ACC1:acc#302" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(2)} -pin  "ACC1:acc#302" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load net {ACC1:acc#302.itm(3)} -pin  "ACC1:acc#302" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#302.itm}
+load inst "ACC1:acc#316" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33745 -attr oid 909 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#303.itm(1)} -pin  "ACC1:acc#316" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1:acc#303.itm(2)} -pin  "ACC1:acc#316" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1:acc#303.itm(3)} -pin  "ACC1:acc#316" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#90.itm}
+load net {ACC1:acc#302.itm(1)} -pin  "ACC1:acc#316" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#302.itm(2)} -pin  "ACC1:acc#316" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#302.itm(3)} -pin  "ACC1:acc#316" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#89.itm}
+load net {ACC1:acc#316.itm(0)} -pin  "ACC1:acc#316" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(1)} -pin  "ACC1:acc#316" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(2)} -pin  "ACC1:acc#316" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(3)} -pin  "ACC1:acc#316" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load inst "ACC1:acc#324" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 33746 -attr oid 910 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#317.itm(0)} -pin  "ACC1:acc#324" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(1)} -pin  "ACC1:acc#324" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(2)} -pin  "ACC1:acc#324" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#317.itm(3)} -pin  "ACC1:acc#324" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#317.itm}
+load net {ACC1:acc#316.itm(0)} -pin  "ACC1:acc#324" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(1)} -pin  "ACC1:acc#324" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(2)} -pin  "ACC1:acc#324" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#316.itm(3)} -pin  "ACC1:acc#324" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#316.itm}
+load net {ACC1:acc#324.itm(0)} -pin  "ACC1:acc#324" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(1)} -pin  "ACC1:acc#324" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(2)} -pin  "ACC1:acc#324" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(3)} -pin  "ACC1:acc#324" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(4)} -pin  "ACC1:acc#324" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load inst "ACC1:acc#328" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 33747 -attr oid 911 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#325.itm(0)} -pin  "ACC1:acc#328" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(1)} -pin  "ACC1:acc#328" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(2)} -pin  "ACC1:acc#328" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(3)} -pin  "ACC1:acc#328" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#325.itm(4)} -pin  "ACC1:acc#328" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#325.itm}
+load net {ACC1:acc#324.itm(0)} -pin  "ACC1:acc#328" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(1)} -pin  "ACC1:acc#328" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(2)} -pin  "ACC1:acc#328" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(3)} -pin  "ACC1:acc#328" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#324.itm(4)} -pin  "ACC1:acc#328" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#324.itm}
+load net {ACC1:acc#328.itm(0)} -pin  "ACC1:acc#328" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(1)} -pin  "ACC1:acc#328" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(2)} -pin  "ACC1:acc#328" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(3)} -pin  "ACC1:acc#328" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(4)} -pin  "ACC1:acc#328" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(5)} -pin  "ACC1:acc#328" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load inst "ACC1:acc#332" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 33748 -attr oid 912 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#332" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#541.itm}
+load net {ACC1:acc#328.itm(0)} -pin  "ACC1:acc#332" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(1)} -pin  "ACC1:acc#332" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(2)} -pin  "ACC1:acc#332" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(3)} -pin  "ACC1:acc#332" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(4)} -pin  "ACC1:acc#332" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#328.itm(5)} -pin  "ACC1:acc#332" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#328.itm}
+load net {ACC1:acc#332.itm(0)} -pin  "ACC1:acc#332" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(1)} -pin  "ACC1:acc#332" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(2)} -pin  "ACC1:acc#332" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(3)} -pin  "ACC1:acc#332" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(4)} -pin  "ACC1:acc#332" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(5)} -pin  "ACC1:acc#332" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(6)} -pin  "ACC1:acc#332" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(7)} -pin  "ACC1:acc#332" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load inst "ACC1:acc#301" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33749 -attr oid 913 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#301" {A(0)} -attr @path {/sobel/sobel:core/exs#32.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#301" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#32.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#301" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#32.itm}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(0)} -pin  "ACC1:acc#301" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#809.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#301" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#809.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#301" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#809.itm}
+load net {ACC1:acc#301.itm(0)} -pin  "ACC1:acc#301" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {ACC1:acc#301.itm(1)} -pin  "ACC1:acc#301" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {ACC1:acc#301.itm(2)} -pin  "ACC1:acc#301" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load net {ACC1:acc#301.itm(3)} -pin  "ACC1:acc#301" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#301.itm}
+load inst "ACC1:acc#300" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33750 -attr oid 914 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#300" {A(0)} -attr @path {/sobel/sobel:core/exs#33.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#300" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#33.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#300" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#33.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(3)} -pin  "ACC1:acc#300" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#811.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} -pin  "ACC1:acc#300" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#811.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} -pin  "ACC1:acc#300" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#811.itm}
+load net {ACC1:acc#300.itm(0)} -pin  "ACC1:acc#300" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#300.itm(1)} -pin  "ACC1:acc#300" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#300.itm(2)} -pin  "ACC1:acc#300" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load net {ACC1:acc#300.itm(3)} -pin  "ACC1:acc#300" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#300.itm}
+load inst "ACC1:acc#315" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33751 -attr oid 915 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#301.itm(1)} -pin  "ACC1:acc#315" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#301.itm(2)} -pin  "ACC1:acc#315" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#301.itm(3)} -pin  "ACC1:acc#315" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#88.itm}
+load net {ACC1:acc#300.itm(1)} -pin  "ACC1:acc#315" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#87.itm}
+load net {ACC1:acc#300.itm(2)} -pin  "ACC1:acc#315" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#87.itm}
+load net {ACC1:acc#300.itm(3)} -pin  "ACC1:acc#315" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#87.itm}
+load net {ACC1:acc#315.itm(0)} -pin  "ACC1:acc#315" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(1)} -pin  "ACC1:acc#315" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(2)} -pin  "ACC1:acc#315" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(3)} -pin  "ACC1:acc#315" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load inst "ACC1:acc#299" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33752 -attr oid 916 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#299" {A(0)} -attr @path {/sobel/sobel:core/exs#34.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#299" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#34.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#299" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#34.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(2)} -pin  "ACC1:acc#299" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#813.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#299" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#813.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#299" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#813.itm}
+load net {ACC1:acc#299.itm(0)} -pin  "ACC1:acc#299" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(1)} -pin  "ACC1:acc#299" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(2)} -pin  "ACC1:acc#299" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load net {ACC1:acc#299.itm(3)} -pin  "ACC1:acc#299" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#299.itm}
+load inst "ACC1:acc#298" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33753 -attr oid 917 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#298" {A(0)} -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#298" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#298" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#57.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(1)} -pin  "ACC1:acc#298" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#815.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} -pin  "ACC1:acc#298" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#815.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} -pin  "ACC1:acc#298" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#815.itm}
+load net {ACC1:acc#298.itm(0)} -pin  "ACC1:acc#298" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(1)} -pin  "ACC1:acc#298" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(2)} -pin  "ACC1:acc#298" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load net {ACC1:acc#298.itm(3)} -pin  "ACC1:acc#298" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#298.itm}
+load inst "ACC1:acc#314" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33754 -attr oid 918 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#299.itm(1)} -pin  "ACC1:acc#314" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#86.itm}
+load net {ACC1:acc#299.itm(2)} -pin  "ACC1:acc#314" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#86.itm}
+load net {ACC1:acc#299.itm(3)} -pin  "ACC1:acc#314" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#86.itm}
+load net {ACC1:acc#298.itm(1)} -pin  "ACC1:acc#314" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#85.itm}
+load net {ACC1:acc#298.itm(2)} -pin  "ACC1:acc#314" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#85.itm}
+load net {ACC1:acc#298.itm(3)} -pin  "ACC1:acc#314" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#85.itm}
+load net {ACC1:acc#314.itm(0)} -pin  "ACC1:acc#314" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(1)} -pin  "ACC1:acc#314" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(2)} -pin  "ACC1:acc#314" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(3)} -pin  "ACC1:acc#314" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load inst "ACC1:acc#323" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 33755 -attr oid 919 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#315.itm(0)} -pin  "ACC1:acc#323" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(1)} -pin  "ACC1:acc#323" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(2)} -pin  "ACC1:acc#323" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#315.itm(3)} -pin  "ACC1:acc#323" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#315.itm}
+load net {ACC1:acc#314.itm(0)} -pin  "ACC1:acc#323" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(1)} -pin  "ACC1:acc#323" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(2)} -pin  "ACC1:acc#323" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#314.itm(3)} -pin  "ACC1:acc#323" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#314.itm}
+load net {ACC1:acc#323.itm(0)} -pin  "ACC1:acc#323" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(1)} -pin  "ACC1:acc#323" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(2)} -pin  "ACC1:acc#323" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(3)} -pin  "ACC1:acc#323" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(4)} -pin  "ACC1:acc#323" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load inst "ACC1:acc#297" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33756 -attr oid 920 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#297" {A(0)} -attr @path {/sobel/sobel:core/exs#35.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#297" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#35.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#297" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#35.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(0)} -pin  "ACC1:acc#297" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#817.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#297" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#817.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#297" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#817.itm}
+load net {ACC1:acc#297.itm(0)} -pin  "ACC1:acc#297" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(1)} -pin  "ACC1:acc#297" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(2)} -pin  "ACC1:acc#297" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load net {ACC1:acc#297.itm(3)} -pin  "ACC1:acc#297" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#297.itm}
+load inst "ACC1:acc#296" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33757 -attr oid 921 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#296" {A(0)} -attr @path {/sobel/sobel:core/exs#36.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#296" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#36.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#296" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#36.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(3)} -pin  "ACC1:acc#296" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#819.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#296" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#819.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#296" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#819.itm}
+load net {ACC1:acc#296.itm(0)} -pin  "ACC1:acc#296" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(1)} -pin  "ACC1:acc#296" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(2)} -pin  "ACC1:acc#296" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load net {ACC1:acc#296.itm(3)} -pin  "ACC1:acc#296" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#296.itm}
+load inst "ACC1:acc#313" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33758 -attr oid 922 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#297.itm(1)} -pin  "ACC1:acc#313" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#84.itm}
+load net {ACC1:acc#297.itm(2)} -pin  "ACC1:acc#313" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#84.itm}
+load net {ACC1:acc#297.itm(3)} -pin  "ACC1:acc#313" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#84.itm}
+load net {ACC1:acc#296.itm(1)} -pin  "ACC1:acc#313" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#83.itm}
+load net {ACC1:acc#296.itm(2)} -pin  "ACC1:acc#313" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#83.itm}
+load net {ACC1:acc#296.itm(3)} -pin  "ACC1:acc#313" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#83.itm}
+load net {ACC1:acc#313.itm(0)} -pin  "ACC1:acc#313" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(1)} -pin  "ACC1:acc#313" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(2)} -pin  "ACC1:acc#313" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(3)} -pin  "ACC1:acc#313" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load inst "ACC1:acc#295" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33759 -attr oid 923 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#295" {A(0)} -attr @path {/sobel/sobel:core/conc#610.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(0)} -pin  "ACC1:acc#295" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#610.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(2)} -pin  "ACC1:acc#295" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#610.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(2)} -pin  "ACC1:acc#295" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#612.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(1)} -pin  "ACC1:acc#295" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#612.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(2)} -pin  "ACC1:acc#295" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#612.itm}
+load net {ACC1:acc#295.itm(0)} -pin  "ACC1:acc#295" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(1)} -pin  "ACC1:acc#295" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(2)} -pin  "ACC1:acc#295" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load net {ACC1:acc#295.itm(3)} -pin  "ACC1:acc#295" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#295.itm}
+load inst "ACC2:not" "not(1)" "INTERFACE" -attr xrf 33760 -attr oid 924 -attr @path {/sobel/sobel:core/ACC2:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(2)} -pin  "ACC2:not" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0)#4.itm}
+load net {ACC2:not.itm} -pin  "ACC2:not" {Z(0)} -attr @path {/sobel/sobel:core/ACC2:not.itm}
+load inst "ACC2:not#5" "not(1)" "INTERFACE" -attr xrf 33761 -attr oid 925 -attr @path {/sobel/sobel:core/ACC2:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(1)} -pin  "ACC2:not#5" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.lpi#1.dfm.sg1:mx0)#1.itm}
+load net {ACC2:not#5.itm} -pin  "ACC2:not#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC2:not#5.itm}
+load inst "ACC1-1:not#60" "not(1)" "INTERFACE" -attr xrf 33762 -attr oid 926 -attr @path {/sobel/sobel:core/ACC1-1:not#60} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#20.lpi#1.dfm:mx0(1)} -pin  "ACC1-1:not#60" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#20.lpi#1.dfm:mx0)#2.itm}
+load net {ACC1-1:not#60.itm} -pin  "ACC1-1:not#60" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#60.itm}
+load inst "ACC1-1:and#3" "and(3,1)" "INTERFACE" -attr xrf 33763 -attr oid 927 -attr @path {/sobel/sobel:core/ACC1-1:and#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1-1:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#24.itm}
+load net {ACC1-1:not#60.itm} -pin  "ACC1-1:and#3" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#60.itm}
+load net {acc.imod#20.lpi#1.dfm:mx0(0)} -pin  "ACC1-1:and#3" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#20.lpi#1.dfm:mx0)#1.itm}
+load net {ACC1-1:and#3.itm} -pin  "ACC1-1:and#3" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#3.itm}
+load inst "ACC1:acc#312" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 33764 -attr oid 928 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {PWR} -pin  "ACC1:acc#312" {A(0)} -attr @path {/sobel/sobel:core/conc#609.itm}
+load net {ACC1:acc#295.itm(1)} -pin  "ACC1:acc#312" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#609.itm}
+load net {ACC1:acc#295.itm(2)} -pin  "ACC1:acc#312" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#609.itm}
+load net {ACC1:acc#295.itm(3)} -pin  "ACC1:acc#312" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#609.itm}
+load net {ACC1-1:and#3.itm} -pin  "ACC1:acc#312" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#611.itm}
+load net {ACC2:not#5.itm} -pin  "ACC1:acc#312" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#611.itm}
+load net {PWR} -pin  "ACC1:acc#312" {B(2)} -attr @path {/sobel/sobel:core/conc#611.itm}
+load net {ACC2:not.itm} -pin  "ACC1:acc#312" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#611.itm}
+load net {ACC1:acc#312.itm(0)} -pin  "ACC1:acc#312" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(1)} -pin  "ACC1:acc#312" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(2)} -pin  "ACC1:acc#312" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(3)} -pin  "ACC1:acc#312" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load net {ACC1:acc#312.itm(4)} -pin  "ACC1:acc#312" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#312.itm}
+load inst "ACC1:acc#322" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 33765 -attr oid 929 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#313.itm(0)} -pin  "ACC1:acc#322" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(1)} -pin  "ACC1:acc#322" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(2)} -pin  "ACC1:acc#322" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#313.itm(3)} -pin  "ACC1:acc#322" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#313.itm}
+load net {ACC1:acc#312.itm(1)} -pin  "ACC1:acc#322" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#312.itm(2)} -pin  "ACC1:acc#322" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#312.itm(3)} -pin  "ACC1:acc#322" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#312.itm(4)} -pin  "ACC1:acc#322" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#99.itm}
+load net {ACC1:acc#322.itm(0)} -pin  "ACC1:acc#322" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(1)} -pin  "ACC1:acc#322" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(2)} -pin  "ACC1:acc#322" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(3)} -pin  "ACC1:acc#322" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(4)} -pin  "ACC1:acc#322" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load inst "ACC1:acc#327" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 33766 -attr oid 930 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {ACC1:acc#323.itm(0)} -pin  "ACC1:acc#327" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(1)} -pin  "ACC1:acc#327" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(2)} -pin  "ACC1:acc#327" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(3)} -pin  "ACC1:acc#327" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#323.itm(4)} -pin  "ACC1:acc#327" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#323.itm}
+load net {ACC1:acc#322.itm(0)} -pin  "ACC1:acc#327" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(1)} -pin  "ACC1:acc#327" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(2)} -pin  "ACC1:acc#327" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(3)} -pin  "ACC1:acc#327" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#322.itm(4)} -pin  "ACC1:acc#327" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#322.itm}
+load net {ACC1:acc#327.itm(0)} -pin  "ACC1:acc#327" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(1)} -pin  "ACC1:acc#327" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(2)} -pin  "ACC1:acc#327" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(3)} -pin  "ACC1:acc#327" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(4)} -pin  "ACC1:acc#327" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(5)} -pin  "ACC1:acc#327" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load inst "ACC2:not#2" "not(1)" "INTERFACE" -attr xrf 33767 -attr oid 931 -attr @path {/sobel/sobel:core/ACC2:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(2)} -pin  "ACC2:not#2" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0)#4.itm}
+load net {ACC2:not#2.itm} -pin  "ACC2:not#2" {Z(0)} -attr @path {/sobel/sobel:core/ACC2:not#2.itm}
+load inst "ACC2:not#7" "not(1)" "INTERFACE" -attr xrf 33768 -attr oid 932 -attr @path {/sobel/sobel:core/ACC2:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(1)} -pin  "ACC2:not#7" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#18.lpi#1.dfm.sg1:mx0)#1.itm}
+load net {ACC2:not#7.itm} -pin  "ACC2:not#7" {Z(0)} -attr @path {/sobel/sobel:core/ACC2:not#7.itm}
+load inst "ACC1-1:not#59" "not(1)" "INTERFACE" -attr xrf 33769 -attr oid 933 -attr @path {/sobel/sobel:core/ACC1-1:not#59} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "ACC1-1:not#59" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0).itm}
+load net {ACC1-1:not#59.itm} -pin  "ACC1-1:not#59" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#59.itm}
+load inst "ACC1-1:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 33770 -attr oid 934 -attr @path {/sobel/sobel:core/ACC1-1:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {acc.imod#20.lpi#1.dfm:mx0(1)} -pin  "ACC1-1:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#20.lpi#1.dfm:mx0).itm}
+load net {ACC1-1:not#59.itm} -pin  "ACC1-1:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#59.itm}
+load net {ACC1-1:nand#1.itm} -pin  "ACC1-1:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:nand#1.itm}
+load inst "ACC1:acc#311" "add(4,0,3,1,5)" "INTERFACE" -attr xrf 33771 -attr oid 935 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#311" {A(0)} -attr @path {/sobel/sobel:core/conc#612.itm}
+load net {ACC2:not#7.itm} -pin  "ACC1:acc#311" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#612.itm}
+load net {PWR} -pin  "ACC1:acc#311" {A(2)} -attr @path {/sobel/sobel:core/conc#612.itm}
+load net {ACC2:not#2.itm} -pin  "ACC1:acc#311" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#612.itm}
+load net {ACC1-1:nand#1.itm} -pin  "ACC1:acc#311" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#644.itm}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(0)} -pin  "ACC1:acc#311" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#644.itm}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(1)} -pin  "ACC1:acc#311" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#644.itm}
+load net {ACC1:acc#311.itm(0)} -pin  "ACC1:acc#311" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(1)} -pin  "ACC1:acc#311" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(2)} -pin  "ACC1:acc#311" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(3)} -pin  "ACC1:acc#311" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load net {ACC1:acc#311.itm(4)} -pin  "ACC1:acc#311" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#311.itm}
+load inst "ACC1:acc#308" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 33772 -attr oid 936 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#308" {A(0)} -attr @path {/sobel/sobel:core/exs#37.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#308" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#37.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#308" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#37.itm}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(1)} -pin  "ACC1:acc#308" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#638.itm}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(0)} -pin  "ACC1:acc#308" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#638.itm}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(1)} -pin  "ACC1:acc#308" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#638.itm}
+load net {ACC1:acc#308.itm(0)} -pin  "ACC1:acc#308" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#308.itm(1)} -pin  "ACC1:acc#308" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#308.itm(2)} -pin  "ACC1:acc#308" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#308.itm(3)} -pin  "ACC1:acc#308" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load net {ACC1:acc#308.itm(4)} -pin  "ACC1:acc#308" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#308.itm}
+load inst "ACC1:acc#321" "add(4,-1,4,-1,4)" "INTERFACE" -attr xrf 33773 -attr oid 937 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#311.itm(1)} -pin  "ACC1:acc#321" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#311.itm(2)} -pin  "ACC1:acc#321" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#311.itm(3)} -pin  "ACC1:acc#321" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#311.itm(4)} -pin  "ACC1:acc#321" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#98.itm}
+load net {ACC1:acc#308.itm(1)} -pin  "ACC1:acc#321" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#308.itm(2)} -pin  "ACC1:acc#321" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#308.itm(3)} -pin  "ACC1:acc#321" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#308.itm(4)} -pin  "ACC1:acc#321" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#95.itm}
+load net {ACC1:acc#321.itm(0)} -pin  "ACC1:acc#321" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(1)} -pin  "ACC1:acc#321" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(2)} -pin  "ACC1:acc#321" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(3)} -pin  "ACC1:acc#321" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load inst "ACC1:acc#331" "add(6,0,4,0,7)" "INTERFACE" -attr xrf 33774 -attr oid 938 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {ACC1:acc#327.itm(0)} -pin  "ACC1:acc#331" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(1)} -pin  "ACC1:acc#331" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(2)} -pin  "ACC1:acc#331" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(3)} -pin  "ACC1:acc#331" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(4)} -pin  "ACC1:acc#331" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#327.itm(5)} -pin  "ACC1:acc#331" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#327.itm}
+load net {ACC1:acc#321.itm(0)} -pin  "ACC1:acc#331" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(1)} -pin  "ACC1:acc#331" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(2)} -pin  "ACC1:acc#331" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#321.itm(3)} -pin  "ACC1:acc#331" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#321.itm}
+load net {ACC1:acc#331.itm(0)} -pin  "ACC1:acc#331" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(1)} -pin  "ACC1:acc#331" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(2)} -pin  "ACC1:acc#331" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(3)} -pin  "ACC1:acc#331" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(4)} -pin  "ACC1:acc#331" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(5)} -pin  "ACC1:acc#331" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(6)} -pin  "ACC1:acc#331" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load inst "ACC1:acc#335" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 33775 -attr oid 939 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#332.itm(0)} -pin  "ACC1:acc#335" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(1)} -pin  "ACC1:acc#335" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(2)} -pin  "ACC1:acc#335" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(3)} -pin  "ACC1:acc#335" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(4)} -pin  "ACC1:acc#335" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(5)} -pin  "ACC1:acc#335" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(6)} -pin  "ACC1:acc#335" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#332.itm(7)} -pin  "ACC1:acc#335" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#332.itm}
+load net {ACC1:acc#331.itm(0)} -pin  "ACC1:acc#335" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(1)} -pin  "ACC1:acc#335" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(2)} -pin  "ACC1:acc#335" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(3)} -pin  "ACC1:acc#335" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(4)} -pin  "ACC1:acc#335" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(5)} -pin  "ACC1:acc#335" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#331.itm(6)} -pin  "ACC1:acc#335" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#331.itm}
+load net {ACC1:acc#335.itm(0)} -pin  "ACC1:acc#335" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(1)} -pin  "ACC1:acc#335" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(2)} -pin  "ACC1:acc#335" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(3)} -pin  "ACC1:acc#335" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(4)} -pin  "ACC1:acc#335" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(5)} -pin  "ACC1:acc#335" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(6)} -pin  "ACC1:acc#335" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(7)} -pin  "ACC1:acc#335" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load inst "ACC1:acc#338" "add(10,-1,8,0,10)" "INTERFACE" -attr xrf 33776 -attr oid 940 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11)"
+load net {ACC1:acc#336.itm(0)} -pin  "ACC1:acc#338" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(1)} -pin  "ACC1:acc#338" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(2)} -pin  "ACC1:acc#338" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(3)} -pin  "ACC1:acc#338" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(4)} -pin  "ACC1:acc#338" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(5)} -pin  "ACC1:acc#338" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(6)} -pin  "ACC1:acc#338" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(7)} -pin  "ACC1:acc#338" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(8)} -pin  "ACC1:acc#338" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#336.itm(9)} -pin  "ACC1:acc#338" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#336.itm}
+load net {ACC1:acc#335.itm(0)} -pin  "ACC1:acc#338" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(1)} -pin  "ACC1:acc#338" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(2)} -pin  "ACC1:acc#338" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(3)} -pin  "ACC1:acc#338" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(4)} -pin  "ACC1:acc#338" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(5)} -pin  "ACC1:acc#338" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(6)} -pin  "ACC1:acc#338" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#335.itm(7)} -pin  "ACC1:acc#338" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#335.itm}
+load net {ACC1:acc#338.itm(0)} -pin  "ACC1:acc#338" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(1)} -pin  "ACC1:acc#338" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(2)} -pin  "ACC1:acc#338" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(3)} -pin  "ACC1:acc#338" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(4)} -pin  "ACC1:acc#338" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(5)} -pin  "ACC1:acc#338" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(6)} -pin  "ACC1:acc#338" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(7)} -pin  "ACC1:acc#338" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(8)} -pin  "ACC1:acc#338" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(9)} -pin  "ACC1:acc#338" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load inst "ACC1:acc#340" "add(13,-1,10,0,13)" "INTERFACE" -attr xrf 33777 -attr oid 941 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340} -attr area 14.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,0,12,1,13)"
+load net {ACC1:mul#20.itm(0)} -pin  "ACC1:acc#340" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(1)} -pin  "ACC1:acc#340" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(2)} -pin  "ACC1:acc#340" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(3)} -pin  "ACC1:acc#340" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(4)} -pin  "ACC1:acc#340" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(5)} -pin  "ACC1:acc#340" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(6)} -pin  "ACC1:acc#340" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(7)} -pin  "ACC1:acc#340" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(8)} -pin  "ACC1:acc#340" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(9)} -pin  "ACC1:acc#340" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(10)} -pin  "ACC1:acc#340" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(11)} -pin  "ACC1:acc#340" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:mul#20.itm(12)} -pin  "ACC1:acc#340" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#20.itm}
+load net {ACC1:acc#338.itm(0)} -pin  "ACC1:acc#340" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(1)} -pin  "ACC1:acc#340" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(2)} -pin  "ACC1:acc#340" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(3)} -pin  "ACC1:acc#340" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(4)} -pin  "ACC1:acc#340" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(5)} -pin  "ACC1:acc#340" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(6)} -pin  "ACC1:acc#340" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(7)} -pin  "ACC1:acc#340" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(8)} -pin  "ACC1:acc#340" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#338.itm(9)} -pin  "ACC1:acc#340" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#338.itm}
+load net {ACC1:acc#340.itm(0)} -pin  "ACC1:acc#340" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(1)} -pin  "ACC1:acc#340" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(2)} -pin  "ACC1:acc#340" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(3)} -pin  "ACC1:acc#340" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(4)} -pin  "ACC1:acc#340" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(5)} -pin  "ACC1:acc#340" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(6)} -pin  "ACC1:acc#340" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(7)} -pin  "ACC1:acc#340" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(8)} -pin  "ACC1:acc#340" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(9)} -pin  "ACC1:acc#340" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(10)} -pin  "ACC1:acc#340" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(11)} -pin  "ACC1:acc#340" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(12)} -pin  "ACC1:acc#340" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load inst "ACC2:acc#4" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 33778 -attr oid 942 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#4} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(9)} -pin  "ACC2:acc#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#10.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(9)} -pin  "ACC2:acc#4" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#10.itm}
+load net {ACC2:acc#4.itm(0)} -pin  "ACC2:acc#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#4.itm}
+load net {ACC2:acc#4.itm(1)} -pin  "ACC2:acc#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#4.itm}
+load inst "ACC1:mul#19" "mul(2,0,9,0,10)" "INTERFACE" -attr xrf 33779 -attr oid 943 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC2:acc#4.itm(0)} -pin  "ACC1:mul#19" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#4.itm}
+load net {ACC2:acc#4.itm(1)} -pin  "ACC1:mul#19" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#4.itm}
+load net {PWR} -pin  "ACC1:mul#19" {B(0)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#19" {B(1)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#19" {B(2)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#19" {B(3)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#19" {B(4)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#19" {B(5)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#19" {B(6)} -attr @path {/sobel/sobel:core/C341_9}
+load net {GND} -pin  "ACC1:mul#19" {B(7)} -attr @path {/sobel/sobel:core/C341_9}
+load net {PWR} -pin  "ACC1:mul#19" {B(8)} -attr @path {/sobel/sobel:core/C341_9}
+load net {ACC1:mul#19.itm(0)} -pin  "ACC1:mul#19" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(1)} -pin  "ACC1:mul#19" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(2)} -pin  "ACC1:mul#19" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(3)} -pin  "ACC1:mul#19" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(4)} -pin  "ACC1:mul#19" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(5)} -pin  "ACC1:mul#19" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(6)} -pin  "ACC1:mul#19" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(7)} -pin  "ACC1:mul#19" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(8)} -pin  "ACC1:mul#19" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(9)} -pin  "ACC1:mul#19" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load inst "ACC1:acc#347" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 33780 -attr oid 944 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347} -attr area 2.320458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} -pin  "ACC1:acc#347" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#11.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#347" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#4.itm}
+load net {ACC1:acc#347.itm(0)} -pin  "ACC1:acc#347" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load net {ACC1:acc#347.itm(1)} -pin  "ACC1:acc#347" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#347.itm}
+load inst "ACC1:acc#348" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 33781 -attr oid 945 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348} -attr area 3.311766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} -pin  "ACC1:acc#348" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:exs.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} -pin  "ACC1:acc#348" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:exs.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#348" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:exs#1.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#348" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:exs#1.itm}
+load net {ACC1:acc#348.itm(0)} -pin  "ACC1:acc#348" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {ACC1:acc#348.itm(1)} -pin  "ACC1:acc#348" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load net {ACC1:acc#348.itm(2)} -pin  "ACC1:acc#348" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#348.itm}
+load inst "ACC1:acc#326" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 33782 -attr oid 946 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#348.itm(0)} -pin  "ACC1:acc#326" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#657.itm}
+load net {ACC1:acc#348.itm(1)} -pin  "ACC1:acc#326" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#657.itm}
+load net {ACC1:acc#348.itm(2)} -pin  "ACC1:acc#326" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#657.itm}
+load net {ACC1:acc#347.itm(0)} -pin  "ACC1:acc#326" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#657.itm}
+load net {ACC1:acc#347.itm(1)} -pin  "ACC1:acc#326" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#657.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#326" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#615.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#326" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#615.itm}
+load net {GND} -pin  "ACC1:acc#326" {B(2)} -attr @path {/sobel/sobel:core/conc#615.itm}
+load net {GND} -pin  "ACC1:acc#326" {B(3)} -attr @path {/sobel/sobel:core/conc#615.itm}
+load net {PWR} -pin  "ACC1:acc#326" {B(4)} -attr @path {/sobel/sobel:core/conc#615.itm}
+load net {ACC1:acc#326.itm(0)} -pin  "ACC1:acc#326" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(1)} -pin  "ACC1:acc#326" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(2)} -pin  "ACC1:acc#326" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(3)} -pin  "ACC1:acc#326" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(4)} -pin  "ACC1:acc#326" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load inst "ACC1:acc#329" "add(6,0,5,1,7)" "INTERFACE" -attr xrf 33783 -attr oid 947 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#329" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#329" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {GND} -pin  "ACC1:acc#329" {A(2)} -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#329" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {GND} -pin  "ACC1:acc#329" {A(4)} -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -pin  "ACC1:acc#329" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#614.itm}
+load net {ACC1:acc#326.itm(0)} -pin  "ACC1:acc#329" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(1)} -pin  "ACC1:acc#329" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(2)} -pin  "ACC1:acc#329" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(3)} -pin  "ACC1:acc#329" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#326.itm(4)} -pin  "ACC1:acc#329" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#326.itm}
+load net {ACC1:acc#329.itm(0)} -pin  "ACC1:acc#329" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(1)} -pin  "ACC1:acc#329" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(2)} -pin  "ACC1:acc#329" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(3)} -pin  "ACC1:acc#329" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(4)} -pin  "ACC1:acc#329" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(5)} -pin  "ACC1:acc#329" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(6)} -pin  "ACC1:acc#329" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load inst "ACC1:acc#333" "add(7,1,7,0,9)" "INTERFACE" -attr xrf 33784 -attr oid 948 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#329.itm(0)} -pin  "ACC1:acc#333" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(1)} -pin  "ACC1:acc#333" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(2)} -pin  "ACC1:acc#333" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(3)} -pin  "ACC1:acc#333" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(4)} -pin  "ACC1:acc#333" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(5)} -pin  "ACC1:acc#333" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#329.itm(6)} -pin  "ACC1:acc#333" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#329.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#333" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#541.itm}
+load net {ACC1:acc#333.itm(0)} -pin  "ACC1:acc#333" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(1)} -pin  "ACC1:acc#333" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(2)} -pin  "ACC1:acc#333" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(3)} -pin  "ACC1:acc#333" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(4)} -pin  "ACC1:acc#333" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(5)} -pin  "ACC1:acc#333" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(6)} -pin  "ACC1:acc#333" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(7)} -pin  "ACC1:acc#333" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(8)} -pin  "ACC1:acc#333" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load inst "ACC1:acc#337" "add(10,0,9,1,11)" "INTERFACE" -attr xrf 33785 -attr oid 949 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11)"
+load net {ACC1:mul#19.itm(0)} -pin  "ACC1:acc#337" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(1)} -pin  "ACC1:acc#337" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(2)} -pin  "ACC1:acc#337" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(3)} -pin  "ACC1:acc#337" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(4)} -pin  "ACC1:acc#337" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(5)} -pin  "ACC1:acc#337" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(6)} -pin  "ACC1:acc#337" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(7)} -pin  "ACC1:acc#337" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(8)} -pin  "ACC1:acc#337" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:mul#19.itm(9)} -pin  "ACC1:acc#337" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#19.itm}
+load net {ACC1:acc#333.itm(0)} -pin  "ACC1:acc#337" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(1)} -pin  "ACC1:acc#337" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(2)} -pin  "ACC1:acc#337" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(3)} -pin  "ACC1:acc#337" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(4)} -pin  "ACC1:acc#337" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(5)} -pin  "ACC1:acc#337" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(6)} -pin  "ACC1:acc#337" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(7)} -pin  "ACC1:acc#337" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#333.itm(8)} -pin  "ACC1:acc#337" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#333.itm}
+load net {ACC1:acc#337.itm(0)} -pin  "ACC1:acc#337" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(1)} -pin  "ACC1:acc#337" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(2)} -pin  "ACC1:acc#337" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(3)} -pin  "ACC1:acc#337" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(4)} -pin  "ACC1:acc#337" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(5)} -pin  "ACC1:acc#337" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(6)} -pin  "ACC1:acc#337" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(7)} -pin  "ACC1:acc#337" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(8)} -pin  "ACC1:acc#337" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(9)} -pin  "ACC1:acc#337" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(10)} -pin  "ACC1:acc#337" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load inst "ACC2:acc#7" "add(1,0,1,0,2)" "INTERFACE" -attr xrf 33786 -attr oid 950 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7} -attr area 2.319458 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(1,0,1,0,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} -pin  "ACC2:acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.lpi#1.dfm:mx0)#13.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} -pin  "ACC2:acc#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.lpi#1.dfm:mx0)#5.itm}
+load net {ACC2:acc#7.itm(0)} -pin  "ACC2:acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(1)} -pin  "ACC2:acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load inst "ACC1:mul#22" "mul(2,0,7,0,8)" "INTERFACE" -attr xrf 33787 -attr oid 951 -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC2:acc#7.itm(0)} -pin  "ACC1:mul#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(1)} -pin  "ACC1:mul#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {PWR} -pin  "ACC1:mul#22" {B(0)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#22" {B(1)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#22" {B(2)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#22" {B(3)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#22" {B(4)} -attr @path {/sobel/sobel:core/C85_7}
+load net {GND} -pin  "ACC1:mul#22" {B(5)} -attr @path {/sobel/sobel:core/C85_7}
+load net {PWR} -pin  "ACC1:mul#22" {B(6)} -attr @path {/sobel/sobel:core/C85_7}
+load net {ACC1:mul#22.itm(0)} -pin  "ACC1:mul#22" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(1)} -pin  "ACC1:mul#22" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(2)} -pin  "ACC1:mul#22" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(3)} -pin  "ACC1:mul#22" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(4)} -pin  "ACC1:mul#22" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(5)} -pin  "ACC1:mul#22" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(6)} -pin  "ACC1:mul#22" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load net {ACC1:mul#22.itm(7)} -pin  "ACC1:mul#22" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:mul#22.itm}
+load inst "ACC1:acc#339" "add(11,1,11,0,13)" "INTERFACE" -attr xrf 33788 -attr oid 952 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13)"
+load net {ACC1:acc#337.itm(0)} -pin  "ACC1:acc#339" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(1)} -pin  "ACC1:acc#339" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(2)} -pin  "ACC1:acc#339" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(3)} -pin  "ACC1:acc#339" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(4)} -pin  "ACC1:acc#339" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(5)} -pin  "ACC1:acc#339" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(6)} -pin  "ACC1:acc#339" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(7)} -pin  "ACC1:acc#339" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(8)} -pin  "ACC1:acc#339" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(9)} -pin  "ACC1:acc#339" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#337.itm(10)} -pin  "ACC1:acc#339" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#337.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#339" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "ACC1:acc#339" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(3)} -pin  "ACC1:acc#339" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(0)} -pin  "ACC1:acc#339" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(1)} -pin  "ACC1:acc#339" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(2)} -pin  "ACC1:acc#339" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(3)} -pin  "ACC1:acc#339" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(4)} -pin  "ACC1:acc#339" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(5)} -pin  "ACC1:acc#339" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(6)} -pin  "ACC1:acc#339" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:mul#22.itm(7)} -pin  "ACC1:acc#339" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#441.itm}
+load net {ACC1:acc#339.itm(0)} -pin  "ACC1:acc#339" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(1)} -pin  "ACC1:acc#339" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(2)} -pin  "ACC1:acc#339" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(3)} -pin  "ACC1:acc#339" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(4)} -pin  "ACC1:acc#339" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(5)} -pin  "ACC1:acc#339" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(6)} -pin  "ACC1:acc#339" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(7)} -pin  "ACC1:acc#339" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(8)} -pin  "ACC1:acc#339" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(9)} -pin  "ACC1:acc#339" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(10)} -pin  "ACC1:acc#339" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(11)} -pin  "ACC1:acc#339" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(12)} -pin  "ACC1:acc#339" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load inst "ACC1:acc#341" "add(13,-1,13,-1,13)" "INTERFACE" -attr xrf 33789 -attr oid 953 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341} -attr area 14.215154 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,0,13,0,13)"
+load net {ACC1:acc#340.itm(0)} -pin  "ACC1:acc#341" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(1)} -pin  "ACC1:acc#341" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(2)} -pin  "ACC1:acc#341" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(3)} -pin  "ACC1:acc#341" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(4)} -pin  "ACC1:acc#341" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(5)} -pin  "ACC1:acc#341" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(6)} -pin  "ACC1:acc#341" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(7)} -pin  "ACC1:acc#341" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(8)} -pin  "ACC1:acc#341" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(9)} -pin  "ACC1:acc#341" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(10)} -pin  "ACC1:acc#341" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(11)} -pin  "ACC1:acc#341" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#340.itm(12)} -pin  "ACC1:acc#341" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#340.itm}
+load net {ACC1:acc#339.itm(0)} -pin  "ACC1:acc#341" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(1)} -pin  "ACC1:acc#341" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(2)} -pin  "ACC1:acc#341" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(3)} -pin  "ACC1:acc#341" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(4)} -pin  "ACC1:acc#341" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(5)} -pin  "ACC1:acc#341" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(6)} -pin  "ACC1:acc#341" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(7)} -pin  "ACC1:acc#341" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(8)} -pin  "ACC1:acc#341" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(9)} -pin  "ACC1:acc#341" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(10)} -pin  "ACC1:acc#341" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(11)} -pin  "ACC1:acc#341" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#339.itm(12)} -pin  "ACC1:acc#341" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#339.itm}
+load net {ACC1:acc#341.itm(0)} -pin  "ACC1:acc#341" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(1)} -pin  "ACC1:acc#341" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(2)} -pin  "ACC1:acc#341" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(3)} -pin  "ACC1:acc#341" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(4)} -pin  "ACC1:acc#341" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(5)} -pin  "ACC1:acc#341" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(6)} -pin  "ACC1:acc#341" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(7)} -pin  "ACC1:acc#341" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(8)} -pin  "ACC1:acc#341" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(9)} -pin  "ACC1:acc#341" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(10)} -pin  "ACC1:acc#341" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(11)} -pin  "ACC1:acc#341" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(12)} -pin  "ACC1:acc#341" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load inst "reg(ACC1:acc#341.itm#1)" "reg(13,1,1,-1,0)" "INTERFACE" -attr xrf 33790 -attr oid 954 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#341.itm#1)}
+load net {ACC1:acc#341.itm(0)} -pin  "reg(ACC1:acc#341.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(1)} -pin  "reg(ACC1:acc#341.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(2)} -pin  "reg(ACC1:acc#341.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(3)} -pin  "reg(ACC1:acc#341.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(4)} -pin  "reg(ACC1:acc#341.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(5)} -pin  "reg(ACC1:acc#341.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(6)} -pin  "reg(ACC1:acc#341.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(7)} -pin  "reg(ACC1:acc#341.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(8)} -pin  "reg(ACC1:acc#341.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(9)} -pin  "reg(ACC1:acc#341.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(10)} -pin  "reg(ACC1:acc#341.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(11)} -pin  "reg(ACC1:acc#341.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {ACC1:acc#341.itm(12)} -pin  "reg(ACC1:acc#341.itm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(ACC1:acc#341.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_13}
+load net {clk} -pin  "reg(ACC1:acc#341.itm#1)" {clk} -attr xrf 33791 -attr oid 955 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#341.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#341.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#341.itm#1(0)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(1)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(2)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(3)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(4)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(5)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(6)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(7)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(8)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(9)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(10)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(11)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(12)} -pin  "reg(ACC1:acc#341.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load inst "mux#2" "mux(2,16)" "INTERFACE" -attr xrf 33792 -attr oid 956 -attr vt d -attr @path {/sobel/sobel:core/mux#2} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {in(0).sva#3(0)} -pin  "mux#2" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(1)} -pin  "mux#2" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(2)} -pin  "mux#2" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(3)} -pin  "mux#2" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(4)} -pin  "mux#2" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(5)} -pin  "mux#2" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(6)} -pin  "mux#2" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(7)} -pin  "mux#2" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(8)} -pin  "mux#2" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(9)} -pin  "mux#2" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(10)} -pin  "mux#2" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(11)} -pin  "mux#2" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(12)} -pin  "mux#2" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(13)} -pin  "mux#2" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(14)} -pin  "mux#2" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(15)} -pin  "mux#2" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#1(0)} -pin  "mux#2" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(1)} -pin  "mux#2" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(2)} -pin  "mux#2" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(3)} -pin  "mux#2" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(4)} -pin  "mux#2" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(5)} -pin  "mux#2" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(6)} -pin  "mux#2" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(7)} -pin  "mux#2" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(8)} -pin  "mux#2" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(9)} -pin  "mux#2" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(10)} -pin  "mux#2" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(11)} -pin  "mux#2" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(12)} -pin  "mux#2" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(13)} -pin  "mux#2" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(14)} -pin  "mux#2" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(15)} -pin  "mux#2" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {main.stage_0#2} -pin  "mux#2" {S(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {mux#2.itm(0)} -pin  "mux#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(1)} -pin  "mux#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(2)} -pin  "mux#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(3)} -pin  "mux#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(4)} -pin  "mux#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(5)} -pin  "mux#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(6)} -pin  "mux#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(7)} -pin  "mux#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(8)} -pin  "mux#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(9)} -pin  "mux#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(10)} -pin  "mux#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(11)} -pin  "mux#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(12)} -pin  "mux#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(13)} -pin  "mux#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(14)} -pin  "mux#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(15)} -pin  "mux#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load inst "reg(in(0).sva#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 33793 -attr oid 957 -attr vt d -attr @path {/sobel/sobel:core/reg(in(0).sva#1)}
+load net {mux#2.itm(0)} -pin  "reg(in(0).sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(1)} -pin  "reg(in(0).sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(2)} -pin  "reg(in(0).sva#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(3)} -pin  "reg(in(0).sva#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(4)} -pin  "reg(in(0).sva#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(5)} -pin  "reg(in(0).sva#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(6)} -pin  "reg(in(0).sva#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(7)} -pin  "reg(in(0).sva#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(8)} -pin  "reg(in(0).sva#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(9)} -pin  "reg(in(0).sva#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(10)} -pin  "reg(in(0).sva#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(11)} -pin  "reg(in(0).sva#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(12)} -pin  "reg(in(0).sva#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(13)} -pin  "reg(in(0).sva#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(14)} -pin  "reg(in(0).sva#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {mux#2.itm(15)} -pin  "reg(in(0).sva#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(in(0).sva#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(in(0).sva#1)" {clk} -attr xrf 33794 -attr oid 958 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(in(0).sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(in(0).sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {in(0).sva#1(0)} -pin  "reg(in(0).sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(1)} -pin  "reg(in(0).sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(2)} -pin  "reg(in(0).sva#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(3)} -pin  "reg(in(0).sva#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(4)} -pin  "reg(in(0).sva#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(5)} -pin  "reg(in(0).sva#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(6)} -pin  "reg(in(0).sva#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(7)} -pin  "reg(in(0).sva#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(8)} -pin  "reg(in(0).sva#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(9)} -pin  "reg(in(0).sva#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(10)} -pin  "reg(in(0).sva#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(11)} -pin  "reg(in(0).sva#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(12)} -pin  "reg(in(0).sva#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(13)} -pin  "reg(in(0).sva#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(14)} -pin  "reg(in(0).sva#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(15)} -pin  "reg(in(0).sva#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load inst "FRAME:for:not#7" "not(1)" "INTERFACE" -attr xrf 33795 -attr oid 959 -attr @path {/sobel/sobel:core/FRAME:for:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:not#7" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#3.itm}
+load net {FRAME:for:not#7.itm} -pin  "FRAME:for:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#7.itm}
+load inst "reg(exit:FRAME:for.sva#1.st#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 33796 -attr oid 960 -attr @path {/sobel/sobel:core/reg(exit:FRAME:for.sva#1.st#1)}
+load net {FRAME:for:not#7.itm} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#7.itm}
+load net {GND} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {clk} -attr xrf 33797 -attr oid 961 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for.sva#1.st#1} -pin  "reg(exit:FRAME:for.sva#1.st#1)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load inst "regs.operator[]#16:mux" "mux(4,10)" "INTERFACE" -attr xrf 33798 -attr oid 962 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(10)} -pin  "regs.operator[]#16:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(11)} -pin  "regs.operator[]#16:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(12)} -pin  "regs.operator[]#16:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(13)} -pin  "regs.operator[]#16:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(14)} -pin  "regs.operator[]#16:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(15)} -pin  "regs.operator[]#16:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(16)} -pin  "regs.operator[]#16:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(17)} -pin  "regs.operator[]#16:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(18)} -pin  "regs.operator[]#16:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(19)} -pin  "regs.operator[]#16:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "regs.operator[]#16:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "regs.operator[]#16:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "regs.operator[]#16:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "regs.operator[]#16:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "regs.operator[]#16:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "regs.operator[]#16:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "regs.operator[]#16:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "regs.operator[]#16:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "regs.operator[]#16:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "regs.operator[]#16:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "regs.operator[]#16:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "regs.operator[]#16:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "regs.operator[]#16:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "regs.operator[]#16:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "regs.operator[]#16:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "regs.operator[]#16:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "regs.operator[]#16:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "regs.operator[]#16:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "regs.operator[]#16:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "regs.operator[]#16:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#16:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#16:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#16:mux.itm(0)} -pin  "regs.operator[]#16:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(1)} -pin  "regs.operator[]#16:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(2)} -pin  "regs.operator[]#16:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(3)} -pin  "regs.operator[]#16:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(4)} -pin  "regs.operator[]#16:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(5)} -pin  "regs.operator[]#16:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(6)} -pin  "regs.operator[]#16:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(7)} -pin  "regs.operator[]#16:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(8)} -pin  "regs.operator[]#16:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(9)} -pin  "regs.operator[]#16:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load inst "FRAME:for:mul#7" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 33799 -attr oid 963 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#16:mux.itm(0)} -pin  "FRAME:for:mul#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(1)} -pin  "FRAME:for:mul#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(2)} -pin  "FRAME:for:mul#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(3)} -pin  "FRAME:for:mul#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(4)} -pin  "FRAME:for:mul#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(5)} -pin  "FRAME:for:mul#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(6)} -pin  "FRAME:for:mul#7" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(7)} -pin  "FRAME:for:mul#7" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(8)} -pin  "FRAME:for:mul#7" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(9)} -pin  "FRAME:for:mul#7" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:mul#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:mul#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:mul#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:mul#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:mul#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:mul#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:mul#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:mul#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:mul#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:mul#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:mul#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load inst "regs.operator[]#17:mux" "mux(4,10)" "INTERFACE" -attr xrf 33800 -attr oid 964 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(0)} -pin  "regs.operator[]#17:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(1)} -pin  "regs.operator[]#17:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(2)} -pin  "regs.operator[]#17:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(3)} -pin  "regs.operator[]#17:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(4)} -pin  "regs.operator[]#17:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(5)} -pin  "regs.operator[]#17:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(6)} -pin  "regs.operator[]#17:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(7)} -pin  "regs.operator[]#17:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(8)} -pin  "regs.operator[]#17:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(9)} -pin  "regs.operator[]#17:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "regs.operator[]#17:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "regs.operator[]#17:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "regs.operator[]#17:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "regs.operator[]#17:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "regs.operator[]#17:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "regs.operator[]#17:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "regs.operator[]#17:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "regs.operator[]#17:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "regs.operator[]#17:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "regs.operator[]#17:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "regs.operator[]#17:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "regs.operator[]#17:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "regs.operator[]#17:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "regs.operator[]#17:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "regs.operator[]#17:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "regs.operator[]#17:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "regs.operator[]#17:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "regs.operator[]#17:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "regs.operator[]#17:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "regs.operator[]#17:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#17:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#17:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#17:mux.itm(0)} -pin  "regs.operator[]#17:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(1)} -pin  "regs.operator[]#17:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(2)} -pin  "regs.operator[]#17:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(3)} -pin  "regs.operator[]#17:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(4)} -pin  "regs.operator[]#17:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(5)} -pin  "regs.operator[]#17:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(6)} -pin  "regs.operator[]#17:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(7)} -pin  "regs.operator[]#17:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(8)} -pin  "regs.operator[]#17:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(9)} -pin  "regs.operator[]#17:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load inst "FRAME:for:mul#8" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 33801 -attr oid 965 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#17:mux.itm(0)} -pin  "FRAME:for:mul#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(1)} -pin  "FRAME:for:mul#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(2)} -pin  "FRAME:for:mul#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(3)} -pin  "FRAME:for:mul#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(4)} -pin  "FRAME:for:mul#8" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(5)} -pin  "FRAME:for:mul#8" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(6)} -pin  "FRAME:for:mul#8" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(7)} -pin  "FRAME:for:mul#8" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(8)} -pin  "FRAME:for:mul#8" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(9)} -pin  "FRAME:for:mul#8" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:mul#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:mul#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:mul#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:mul#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:mul#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:mul#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:mul#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:mul#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:mul#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:mul#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:mul#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load inst "FRAME:for:acc#25" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 33802 -attr oid 966 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:acc#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:acc#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:acc#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:acc#25" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:acc#25" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:acc#25" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:acc#25" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:acc#25" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:acc#25" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:acc#25" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:acc#25" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:acc#25" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:acc#25" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:acc#25" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:acc#25" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:acc#25" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:acc#25" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:acc#25" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:acc#25" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:acc#25" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:acc#25" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:acc#25" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:acc#25.itm(0)} -pin  "FRAME:for:acc#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(1)} -pin  "FRAME:for:acc#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(2)} -pin  "FRAME:for:acc#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(3)} -pin  "FRAME:for:acc#25" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(4)} -pin  "FRAME:for:acc#25" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(5)} -pin  "FRAME:for:acc#25" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(6)} -pin  "FRAME:for:acc#25" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(7)} -pin  "FRAME:for:acc#25" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(8)} -pin  "FRAME:for:acc#25" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(9)} -pin  "FRAME:for:acc#25" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(10)} -pin  "FRAME:for:acc#25" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(11)} -pin  "FRAME:for:acc#25" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load inst "regs.operator[]#15:mux" "mux(4,10)" "INTERFACE" -attr xrf 33803 -attr oid 967 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(20)} -pin  "regs.operator[]#15:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(21)} -pin  "regs.operator[]#15:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(22)} -pin  "regs.operator[]#15:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(23)} -pin  "regs.operator[]#15:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(24)} -pin  "regs.operator[]#15:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(25)} -pin  "regs.operator[]#15:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(26)} -pin  "regs.operator[]#15:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(27)} -pin  "regs.operator[]#15:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(28)} -pin  "regs.operator[]#15:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(29)} -pin  "regs.operator[]#15:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm.sg2:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "regs.operator[]#15:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "regs.operator[]#15:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "regs.operator[]#15:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "regs.operator[]#15:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "regs.operator[]#15:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "regs.operator[]#15:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "regs.operator[]#15:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "regs.operator[]#15:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "regs.operator[]#15:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "regs.operator[]#15:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "regs.operator[]#15:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "regs.operator[]#15:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "regs.operator[]#15:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "regs.operator[]#15:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "regs.operator[]#15:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "regs.operator[]#15:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "regs.operator[]#15:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "regs.operator[]#15:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "regs.operator[]#15:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "regs.operator[]#15:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#15:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#15:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#15:mux.itm(0)} -pin  "regs.operator[]#15:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(1)} -pin  "regs.operator[]#15:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(2)} -pin  "regs.operator[]#15:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(3)} -pin  "regs.operator[]#15:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(4)} -pin  "regs.operator[]#15:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(5)} -pin  "regs.operator[]#15:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(6)} -pin  "regs.operator[]#15:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(7)} -pin  "regs.operator[]#15:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(8)} -pin  "regs.operator[]#15:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(9)} -pin  "regs.operator[]#15:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load inst "FRAME:for:mul#6" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 33804 -attr oid 968 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#15:mux.itm(0)} -pin  "FRAME:for:mul#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(1)} -pin  "FRAME:for:mul#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(2)} -pin  "FRAME:for:mul#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(3)} -pin  "FRAME:for:mul#6" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(4)} -pin  "FRAME:for:mul#6" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(5)} -pin  "FRAME:for:mul#6" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(6)} -pin  "FRAME:for:mul#6" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(7)} -pin  "FRAME:for:mul#6" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(8)} -pin  "FRAME:for:mul#6" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(9)} -pin  "FRAME:for:mul#6" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#16}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:mul#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:mul#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:mul#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:mul#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:mul#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:mul#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:mul#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:mul#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:mul#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:mul#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:mul#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load inst "FRAME:for:acc#26" "add(12,-1,11,1,12)" "INTERFACE" -attr xrf 33805 -attr oid 969 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {FRAME:for:acc#25.itm(0)} -pin  "FRAME:for:acc#26" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(1)} -pin  "FRAME:for:acc#26" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(2)} -pin  "FRAME:for:acc#26" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(3)} -pin  "FRAME:for:acc#26" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(4)} -pin  "FRAME:for:acc#26" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(5)} -pin  "FRAME:for:acc#26" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(6)} -pin  "FRAME:for:acc#26" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(7)} -pin  "FRAME:for:acc#26" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(8)} -pin  "FRAME:for:acc#26" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(9)} -pin  "FRAME:for:acc#26" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(10)} -pin  "FRAME:for:acc#26" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:acc#25.itm(11)} -pin  "FRAME:for:acc#26" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#25.itm}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:acc#26" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:acc#26" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:acc#26" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:acc#26" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:acc#26" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:acc#26" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:acc#26" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:acc#26" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:acc#26" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:acc#26" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:acc#26" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:acc#26.itm(0)} -pin  "FRAME:for:acc#26" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(1)} -pin  "FRAME:for:acc#26" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(2)} -pin  "FRAME:for:acc#26" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(3)} -pin  "FRAME:for:acc#26" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(4)} -pin  "FRAME:for:acc#26" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(5)} -pin  "FRAME:for:acc#26" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(6)} -pin  "FRAME:for:acc#26" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(7)} -pin  "FRAME:for:acc#26" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(8)} -pin  "FRAME:for:acc#26" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(9)} -pin  "FRAME:for:acc#26" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(10)} -pin  "FRAME:for:acc#26" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(11)} -pin  "FRAME:for:acc#26" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load inst "reg(FRAME:for:acc#26.itm#1)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 33806 -attr oid 970 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:for:acc#26.itm#1)}
+load net {FRAME:for:acc#26.itm(0)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(1)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(2)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(3)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(4)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(5)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(6)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(7)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(8)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(9)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(10)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(11)} -pin  "reg(FRAME:for:acc#26.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:acc#26.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(FRAME:for:acc#26.itm#1)" {clk} -attr xrf 33807 -attr oid 971 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:for:acc#26.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:for:acc#26.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:for:acc#26.itm#1(0)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(1)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(2)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(3)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(4)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(5)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(6)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(7)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(8)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(9)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(10)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(11)} -pin  "reg(FRAME:for:acc#26.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load inst "ACC1:acc#242" "add(3,1,2,1,4)" "INTERFACE" -attr xrf 33808 -attr oid 972 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#242" {A(0)} -attr @path {/sobel/sobel:core/conc#617.itm}
+load net {acc#10.psp#1.sva(3)} -pin  "ACC1:acc#242" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#617.itm}
+load net {PWR} -pin  "ACC1:acc#242" {A(2)} -attr @path {/sobel/sobel:core/conc#617.itm}
+load net {acc#10.psp#1.sva(4)} -pin  "ACC1:acc#242" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#582.itm}
+load net {ACC1:acc#113.psp#1.sva(3)} -pin  "ACC1:acc#242" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#582.itm}
+load net {ACC1:acc#242.itm(0)} -pin  "ACC1:acc#242" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#242.itm(1)} -pin  "ACC1:acc#242" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#242.itm(2)} -pin  "ACC1:acc#242" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load net {ACC1:acc#242.itm(3)} -pin  "ACC1:acc#242" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#242.itm}
+load inst "ACC1:acc#251" "add(3,-1,2,1,3)" "INTERFACE" -attr xrf 33809 -attr oid 973 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {ACC1:acc#242.itm(1)} -pin  "ACC1:acc#251" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#68.itm}
+load net {ACC1:acc#242.itm(2)} -pin  "ACC1:acc#251" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#68.itm}
+load net {ACC1:acc#242.itm(3)} -pin  "ACC1:acc#251" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#68.itm}
+load net {ACC1:acc#120.psp.sva(1)} -pin  "ACC1:acc#251" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp.sva)#2.itm}
+load net {ACC1:acc#120.psp.sva(2)} -pin  "ACC1:acc#251" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp.sva)#2.itm}
+load net {ACC1:acc#251.itm(0)} -pin  "ACC1:acc#251" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(1)} -pin  "ACC1:acc#251" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(2)} -pin  "ACC1:acc#251" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load inst "ACC1:acc#243" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 33810 -attr oid 974 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#243" {A(0)} -attr @path {/sobel/sobel:core/conc#618.itm}
+load net {acc#10.psp#1.sva(1)} -pin  "ACC1:acc#243" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#618.itm}
+load net {acc#10.psp#1.sva(3)} -pin  "ACC1:acc#243" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#618.itm}
+load net {ACC1:acc#113.psp#1.sva(1)} -pin  "ACC1:acc#243" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#584.itm}
+load net {acc#10.psp#1.sva(2)} -pin  "ACC1:acc#243" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#584.itm}
+load net {ACC1:acc#113.psp#1.sva(3)} -pin  "ACC1:acc#243" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#584.itm}
+load net {ACC1:acc#243.itm(0)} -pin  "ACC1:acc#243" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(1)} -pin  "ACC1:acc#243" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(2)} -pin  "ACC1:acc#243" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(3)} -pin  "ACC1:acc#243" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load net {ACC1:acc#243.itm(4)} -pin  "ACC1:acc#243" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#243.itm}
+load inst "ACC1:acc#256" "add(3,1,4,-1,4)" "INTERFACE" -attr xrf 33811 -attr oid 975 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#251.itm(0)} -pin  "ACC1:acc#256" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(1)} -pin  "ACC1:acc#256" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#251.itm(2)} -pin  "ACC1:acc#256" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#251.itm}
+load net {ACC1:acc#243.itm(1)} -pin  "ACC1:acc#256" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#69.itm}
+load net {ACC1:acc#243.itm(2)} -pin  "ACC1:acc#256" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#69.itm}
+load net {ACC1:acc#243.itm(3)} -pin  "ACC1:acc#256" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#69.itm}
+load net {ACC1:acc#243.itm(4)} -pin  "ACC1:acc#256" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#69.itm}
+load net {ACC1:acc#256.itm(0)} -pin  "ACC1:acc#256" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(1)} -pin  "ACC1:acc#256" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(2)} -pin  "ACC1:acc#256" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(3)} -pin  "ACC1:acc#256" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load inst "ACC1:acc#255" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 33812 -attr oid 976 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#255" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#284.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#255" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#284.itm}
+load net {acc#10.psp#1.sva(4)} -pin  "ACC1:acc#255" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#284.itm}
+load net {acc#10.psp#1.sva(7)} -pin  "ACC1:acc#255" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#284.itm}
+load net {ACC1:acc#250.cse(0)} -pin  "ACC1:acc#255" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#250.cse(1)} -pin  "ACC1:acc#255" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#250.cse(2)} -pin  "ACC1:acc#255" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#255.itm(0)} -pin  "ACC1:acc#255" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(1)} -pin  "ACC1:acc#255" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(2)} -pin  "ACC1:acc#255" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(3)} -pin  "ACC1:acc#255" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(4)} -pin  "ACC1:acc#255" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load inst "ACC1:acc#259" "add(4,1,5,0,6)" "INTERFACE" -attr xrf 33813 -attr oid 977 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#256.itm(0)} -pin  "ACC1:acc#259" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(1)} -pin  "ACC1:acc#259" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(2)} -pin  "ACC1:acc#259" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#256.itm(3)} -pin  "ACC1:acc#259" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#256.itm}
+load net {ACC1:acc#255.itm(0)} -pin  "ACC1:acc#259" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(1)} -pin  "ACC1:acc#259" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(2)} -pin  "ACC1:acc#259" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(3)} -pin  "ACC1:acc#259" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#255.itm(4)} -pin  "ACC1:acc#259" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#255.itm}
+load net {ACC1:acc#259.itm(0)} -pin  "ACC1:acc#259" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(1)} -pin  "ACC1:acc#259" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(2)} -pin  "ACC1:acc#259" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(3)} -pin  "ACC1:acc#259" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(4)} -pin  "ACC1:acc#259" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(5)} -pin  "ACC1:acc#259" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load inst "ACC1:acc#262" "add(6,1,7,0,8)" "INTERFACE" -attr xrf 33814 -attr oid 978 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#259.itm(0)} -pin  "ACC1:acc#262" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(1)} -pin  "ACC1:acc#262" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(2)} -pin  "ACC1:acc#262" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(3)} -pin  "ACC1:acc#262" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(4)} -pin  "ACC1:acc#262" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {ACC1:acc#259.itm(5)} -pin  "ACC1:acc#262" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#259.itm}
+load net {acc#10.psp#1.sva(8)} -pin  "ACC1:acc#262" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {GND} -pin  "ACC1:acc#262" {B(1)} -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {acc#10.psp#1.sva(8)} -pin  "ACC1:acc#262" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {GND} -pin  "ACC1:acc#262" {B(3)} -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {acc#10.psp#1.sva(8)} -pin  "ACC1:acc#262" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {GND} -pin  "ACC1:acc#262" {B(5)} -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {acc#10.psp#1.sva(8)} -pin  "ACC1:acc#262" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#619.itm}
+load net {ACC1:acc#262.itm(0)} -pin  "ACC1:acc#262" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(1)} -pin  "ACC1:acc#262" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(2)} -pin  "ACC1:acc#262" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(3)} -pin  "ACC1:acc#262" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(4)} -pin  "ACC1:acc#262" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(5)} -pin  "ACC1:acc#262" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(6)} -pin  "ACC1:acc#262" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(7)} -pin  "ACC1:acc#262" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load inst "ACC1-3:not#92" "not(1)" "INTERFACE" -attr xrf 33815 -attr oid 979 -attr @path {/sobel/sobel:core/ACC1-3:not#92} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#188.itm(2)} -pin  "ACC1-3:not#92" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#2.itm}
+load net {ACC1-3:not#92.itm} -pin  "ACC1-3:not#92" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#92.itm}
+load inst "ACC1-3:and#5" "and(3,1)" "INTERFACE" -attr xrf 33816 -attr oid 980 -attr @path {/sobel/sobel:core/ACC1-3:and#5} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1-3:and#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#38.itm}
+load net {ACC1-3:not#92.itm} -pin  "ACC1-3:and#5" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#92.itm}
+load net {ACC1:acc#188.itm(1)} -pin  "ACC1-3:and#5" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva)#1.itm}
+load net {ACC1-3:and#5.itm} -pin  "ACC1-3:and#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#5.itm}
+load inst "ACC1:acc#248" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33817 -attr oid 981 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#248" {A(0)} -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {acc#10.psp#1.sva(7)} -pin  "ACC1:acc#248" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {acc#10.psp#1.sva(7)} -pin  "ACC1:acc#248" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#58.itm}
+load net {ACC1-3:and#5.itm} -pin  "ACC1:acc#248" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#772.itm}
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1:acc#248" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#772.itm}
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1:acc#248" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#772.itm}
+load net {ACC1:acc#248.itm(0)} -pin  "ACC1:acc#248" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(1)} -pin  "ACC1:acc#248" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(2)} -pin  "ACC1:acc#248" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load net {ACC1:acc#248.itm(3)} -pin  "ACC1:acc#248" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#248.itm}
+load inst "ACC1:acc#254" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33818 -attr oid 982 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#250.cse(0)} -pin  "ACC1:acc#254" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#250.cse(1)} -pin  "ACC1:acc#254" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#250.cse(2)} -pin  "ACC1:acc#254" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#248.itm(1)} -pin  "ACC1:acc#254" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:acc#248.itm(2)} -pin  "ACC1:acc#254" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:acc#248.itm(3)} -pin  "ACC1:acc#254" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#74.itm}
+load net {ACC1:acc#254.itm(0)} -pin  "ACC1:acc#254" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(1)} -pin  "ACC1:acc#254" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(2)} -pin  "ACC1:acc#254" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(3)} -pin  "ACC1:acc#254" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load inst "ACC1:acc#258" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 33819 -attr oid 983 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {acc#10.psp#1.sva(6)} -pin  "ACC1:acc#258" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#620.itm}
+load net {GND} -pin  "ACC1:acc#258" {A(1)} -attr @path {/sobel/sobel:core/conc#620.itm}
+load net {acc#10.psp#1.sva(6)} -pin  "ACC1:acc#258" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#620.itm}
+load net {GND} -pin  "ACC1:acc#258" {A(3)} -attr @path {/sobel/sobel:core/conc#620.itm}
+load net {acc#10.psp#1.sva(6)} -pin  "ACC1:acc#258" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#620.itm}
+load net {ACC1:acc#254.itm(0)} -pin  "ACC1:acc#258" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(1)} -pin  "ACC1:acc#258" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(2)} -pin  "ACC1:acc#258" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#254.itm(3)} -pin  "ACC1:acc#258" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#254.itm}
+load net {ACC1:acc#258.itm(0)} -pin  "ACC1:acc#258" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(1)} -pin  "ACC1:acc#258" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(2)} -pin  "ACC1:acc#258" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(3)} -pin  "ACC1:acc#258" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(4)} -pin  "ACC1:acc#258" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(5)} -pin  "ACC1:acc#258" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load inst "ACC1:acc#261" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 33820 -attr oid 984 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#261" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#544.itm}
+load net {ACC1:acc#258.itm(0)} -pin  "ACC1:acc#261" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(1)} -pin  "ACC1:acc#261" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(2)} -pin  "ACC1:acc#261" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(3)} -pin  "ACC1:acc#261" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(4)} -pin  "ACC1:acc#261" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#258.itm(5)} -pin  "ACC1:acc#261" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#258.itm}
+load net {ACC1:acc#261.itm(0)} -pin  "ACC1:acc#261" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(1)} -pin  "ACC1:acc#261" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(2)} -pin  "ACC1:acc#261" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(3)} -pin  "ACC1:acc#261" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(4)} -pin  "ACC1:acc#261" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(5)} -pin  "ACC1:acc#261" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(6)} -pin  "ACC1:acc#261" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(7)} -pin  "ACC1:acc#261" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load inst "ACC1:acc#264" "add(8,1,8,0,10)" "INTERFACE" -attr xrf 33821 -attr oid 985 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#262.itm(0)} -pin  "ACC1:acc#264" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(1)} -pin  "ACC1:acc#264" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(2)} -pin  "ACC1:acc#264" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(3)} -pin  "ACC1:acc#264" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(4)} -pin  "ACC1:acc#264" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(5)} -pin  "ACC1:acc#264" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(6)} -pin  "ACC1:acc#264" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#262.itm(7)} -pin  "ACC1:acc#264" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#262.itm}
+load net {ACC1:acc#261.itm(0)} -pin  "ACC1:acc#264" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(1)} -pin  "ACC1:acc#264" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(2)} -pin  "ACC1:acc#264" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(3)} -pin  "ACC1:acc#264" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(4)} -pin  "ACC1:acc#264" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(5)} -pin  "ACC1:acc#264" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(6)} -pin  "ACC1:acc#264" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#261.itm(7)} -pin  "ACC1:acc#264" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#261.itm}
+load net {ACC1:acc#264.itm(0)} -pin  "ACC1:acc#264" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(1)} -pin  "ACC1:acc#264" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(2)} -pin  "ACC1:acc#264" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(3)} -pin  "ACC1:acc#264" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(4)} -pin  "ACC1:acc#264" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(5)} -pin  "ACC1:acc#264" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(6)} -pin  "ACC1:acc#264" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(7)} -pin  "ACC1:acc#264" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(8)} -pin  "ACC1:acc#264" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(9)} -pin  "ACC1:acc#264" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load inst "ACC1:acc#266" "add(10,1,10,0,11)" "INTERFACE" -attr xrf 33822 -attr oid 986 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11)"
+load net {ACC1:acc#264.itm(0)} -pin  "ACC1:acc#266" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(1)} -pin  "ACC1:acc#266" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(2)} -pin  "ACC1:acc#266" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(3)} -pin  "ACC1:acc#266" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(4)} -pin  "ACC1:acc#266" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(5)} -pin  "ACC1:acc#266" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(6)} -pin  "ACC1:acc#266" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(7)} -pin  "ACC1:acc#266" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(8)} -pin  "ACC1:acc#266" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {ACC1:acc#264.itm(9)} -pin  "ACC1:acc#266" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#264.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#266" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#266" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {GND} -pin  "ACC1:acc#266" {B(2)} -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#266" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {GND} -pin  "ACC1:acc#266" {B(4)} -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#266" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {GND} -pin  "ACC1:acc#266" {B(6)} -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#266" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {GND} -pin  "ACC1:acc#266" {B(8)} -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#266" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#623.itm}
+load net {ACC1:acc#266.itm(0)} -pin  "ACC1:acc#266" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(1)} -pin  "ACC1:acc#266" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(2)} -pin  "ACC1:acc#266" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(3)} -pin  "ACC1:acc#266" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(4)} -pin  "ACC1:acc#266" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(5)} -pin  "ACC1:acc#266" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(6)} -pin  "ACC1:acc#266" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(7)} -pin  "ACC1:acc#266" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(8)} -pin  "ACC1:acc#266" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(9)} -pin  "ACC1:acc#266" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(10)} -pin  "ACC1:acc#266" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load inst "ACC1:acc#268" "add(10,0,11,-1,11)" "INTERFACE" -attr xrf 33823 -attr oid 987 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268} -attr area 12.237292 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,0,11)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#268" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(1)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(2)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(3)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(4)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(5)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(6)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(7)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {GND} -pin  "ACC1:acc#268" {A(8)} -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#268" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#616.itm}
+load net {ACC1:acc#266.itm(0)} -pin  "ACC1:acc#268" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(1)} -pin  "ACC1:acc#268" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(2)} -pin  "ACC1:acc#268" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(3)} -pin  "ACC1:acc#268" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(4)} -pin  "ACC1:acc#268" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(5)} -pin  "ACC1:acc#268" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(6)} -pin  "ACC1:acc#268" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(7)} -pin  "ACC1:acc#268" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(8)} -pin  "ACC1:acc#268" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(9)} -pin  "ACC1:acc#268" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#266.itm(10)} -pin  "ACC1:acc#268" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#266.itm}
+load net {ACC1:acc#268.itm(0)} -pin  "ACC1:acc#268" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(1)} -pin  "ACC1:acc#268" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(2)} -pin  "ACC1:acc#268" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(3)} -pin  "ACC1:acc#268" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(4)} -pin  "ACC1:acc#268" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(5)} -pin  "ACC1:acc#268" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(6)} -pin  "ACC1:acc#268" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(7)} -pin  "ACC1:acc#268" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(8)} -pin  "ACC1:acc#268" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(9)} -pin  "ACC1:acc#268" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(10)} -pin  "ACC1:acc#268" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load inst "ACC1-1:not#164" "not(1)" "INTERFACE" -attr xrf 33824 -attr oid 988 -attr @path {/sobel/sobel:core/ACC1-1:not#164} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:not#164" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#49.itm}
+load net {ACC1-1:not#164.itm} -pin  "ACC1-1:not#164" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#164.itm}
+load inst "ACC1-1:nand#2" "nand(2,1)" "INTERFACE" -attr xrf 33825 -attr oid 989 -attr vt c -attr @path {/sobel/sobel:core/ACC1-1:nand#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#161.itm(2)} -pin  "ACC1-1:nand#2" {A0(0)} -attr vt c -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#2.itm}
+load net {ACC1-1:not#164.itm} -pin  "ACC1-1:nand#2" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#164.itm}
+load net {ACC1-1:nand#2.itm} -pin  "ACC1-1:nand#2" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/ACC1-1:nand#2.itm}
+load inst "ACC1:acc#274" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33826 -attr oid 990 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#274} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#274" {A(0)} -attr @path {/sobel/sobel:core/exs#38.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#274" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#38.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#274" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#38.itm}
+load net {ACC1-1:nand#2.itm} -pin  "ACC1:acc#274" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:exs#774.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#274" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:exs#774.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#274" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:exs#774.itm}
+load net {ACC1:acc#274.itm(0)} -pin  "ACC1:acc#274" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(1)} -pin  "ACC1:acc#274" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(2)} -pin  "ACC1:acc#274" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load net {ACC1:acc#274.itm(3)} -pin  "ACC1:acc#274" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#274.itm}
+load inst "ACC1-1:not#165" "not(1)" "INTERFACE" -attr xrf 33827 -attr oid 991 -attr @path {/sobel/sobel:core/ACC1-1:not#165} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#160.itm(3)} -pin  "ACC1-1:not#165" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#22.sva)#4.itm}
+load net {ACC1-1:not#165.itm} -pin  "ACC1-1:not#165" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#165.itm}
+load inst "ACC1:acc#273" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33828 -attr oid 992 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#273} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#273" {A(0)} -attr @path {/sobel/sobel:core/exs#39.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#273" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#39.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#273" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#39.itm}
+load net {ACC1-1:not#165.itm} -pin  "ACC1:acc#273" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#776.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#273" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#776.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#273" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#776.itm}
+load net {ACC1:acc#273.itm(0)} -pin  "ACC1:acc#273" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(1)} -pin  "ACC1:acc#273" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(2)} -pin  "ACC1:acc#273" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load net {ACC1:acc#273.itm(3)} -pin  "ACC1:acc#273" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#273.itm}
+load inst "ACC1:acc#280" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33829 -attr oid 993 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#274.itm(1)} -pin  "ACC1:acc#280" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#80.itm}
+load net {ACC1:acc#274.itm(2)} -pin  "ACC1:acc#280" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#80.itm}
+load net {ACC1:acc#274.itm(3)} -pin  "ACC1:acc#280" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#80.itm}
+load net {ACC1:acc#273.itm(1)} -pin  "ACC1:acc#280" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#79.itm}
+load net {ACC1:acc#273.itm(2)} -pin  "ACC1:acc#280" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#79.itm}
+load net {ACC1:acc#273.itm(3)} -pin  "ACC1:acc#280" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#79.itm}
+load net {ACC1:acc#280.itm(0)} -pin  "ACC1:acc#280" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(1)} -pin  "ACC1:acc#280" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(2)} -pin  "ACC1:acc#280" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(3)} -pin  "ACC1:acc#280" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load inst "ACC1:acc#272" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33830 -attr oid 994 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#272" {A(0)} -attr @path {/sobel/sobel:core/exs#40.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#272" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#40.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#272" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#40.itm}
+load net {ACC1:acc#160.itm(2)} -pin  "ACC1:acc#272" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#778.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#272" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#778.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#272" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#778.itm}
+load net {ACC1:acc#272.itm(0)} -pin  "ACC1:acc#272" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(1)} -pin  "ACC1:acc#272" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(2)} -pin  "ACC1:acc#272" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load net {ACC1:acc#272.itm(3)} -pin  "ACC1:acc#272" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#272.itm}
+load inst "ACC1:acc#271" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33831 -attr oid 995 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#271} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#271" {A(0)} -attr @path {/sobel/sobel:core/exs#41.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#271" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#41.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#271" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#41.itm}
+load net {ACC1:acc#113.psp#2.sva(2)} -pin  "ACC1:acc#271" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#780.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#271" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#780.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#271" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#780.itm}
+load net {ACC1:acc#271.itm(0)} -pin  "ACC1:acc#271" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(1)} -pin  "ACC1:acc#271" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(2)} -pin  "ACC1:acc#271" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load net {ACC1:acc#271.itm(3)} -pin  "ACC1:acc#271" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#271.itm}
+load inst "ACC1:acc#279" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33832 -attr oid 996 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#272.itm(1)} -pin  "ACC1:acc#279" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#78.itm}
+load net {ACC1:acc#272.itm(2)} -pin  "ACC1:acc#279" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#78.itm}
+load net {ACC1:acc#272.itm(3)} -pin  "ACC1:acc#279" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#78.itm}
+load net {ACC1:acc#271.itm(1)} -pin  "ACC1:acc#279" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#77.itm}
+load net {ACC1:acc#271.itm(2)} -pin  "ACC1:acc#279" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#77.itm}
+load net {ACC1:acc#271.itm(3)} -pin  "ACC1:acc#279" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#77.itm}
+load net {ACC1:acc#279.itm(0)} -pin  "ACC1:acc#279" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(1)} -pin  "ACC1:acc#279" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(2)} -pin  "ACC1:acc#279" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(3)} -pin  "ACC1:acc#279" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load inst "ACC1:acc#284" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 33833 -attr oid 997 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#280.itm(0)} -pin  "ACC1:acc#284" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(1)} -pin  "ACC1:acc#284" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(2)} -pin  "ACC1:acc#284" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#280.itm(3)} -pin  "ACC1:acc#284" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#280.itm}
+load net {ACC1:acc#279.itm(0)} -pin  "ACC1:acc#284" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(1)} -pin  "ACC1:acc#284" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(2)} -pin  "ACC1:acc#284" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#279.itm(3)} -pin  "ACC1:acc#284" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#279.itm}
+load net {ACC1:acc#284.itm(0)} -pin  "ACC1:acc#284" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(1)} -pin  "ACC1:acc#284" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(2)} -pin  "ACC1:acc#284" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(3)} -pin  "ACC1:acc#284" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(4)} -pin  "ACC1:acc#284" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load inst "ACC1:acc#287" "add(6,0,5,0,7)" "INTERFACE" -attr xrf 33834 -attr oid 998 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#287" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#287" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {GND} -pin  "ACC1:acc#287" {A(2)} -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {acc#10.psp#2.sva(5)} -pin  "ACC1:acc#287" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {GND} -pin  "ACC1:acc#287" {A(4)} -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {acc#10.psp#2.sva(7)} -pin  "ACC1:acc#287" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#626.itm}
+load net {ACC1:acc#284.itm(0)} -pin  "ACC1:acc#287" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(1)} -pin  "ACC1:acc#287" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(2)} -pin  "ACC1:acc#287" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(3)} -pin  "ACC1:acc#287" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#284.itm(4)} -pin  "ACC1:acc#287" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#284.itm}
+load net {ACC1:acc#287.itm(0)} -pin  "ACC1:acc#287" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(1)} -pin  "ACC1:acc#287" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(2)} -pin  "ACC1:acc#287" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(3)} -pin  "ACC1:acc#287" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(4)} -pin  "ACC1:acc#287" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(5)} -pin  "ACC1:acc#287" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(6)} -pin  "ACC1:acc#287" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load inst "ACC1:acc#290" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 33835 -attr oid 999 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {acc#10.psp#2.sva(5)} -pin  "ACC1:acc#290" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {acc#10.psp#2.sva(5)} -pin  "ACC1:acc#290" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {GND} -pin  "ACC1:acc#290" {A(2)} -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1:acc#290" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {GND} -pin  "ACC1:acc#290" {A(4)} -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1:acc#290" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {GND} -pin  "ACC1:acc#290" {A(6)} -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1:acc#290" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#625.itm}
+load net {ACC1:acc#287.itm(0)} -pin  "ACC1:acc#290" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(1)} -pin  "ACC1:acc#290" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(2)} -pin  "ACC1:acc#290" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(3)} -pin  "ACC1:acc#290" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(4)} -pin  "ACC1:acc#290" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(5)} -pin  "ACC1:acc#290" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#287.itm(6)} -pin  "ACC1:acc#290" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#287.itm}
+load net {ACC1:acc#290.itm(0)} -pin  "ACC1:acc#290" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(1)} -pin  "ACC1:acc#290" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(2)} -pin  "ACC1:acc#290" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(3)} -pin  "ACC1:acc#290" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(4)} -pin  "ACC1:acc#290" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(5)} -pin  "ACC1:acc#290" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(6)} -pin  "ACC1:acc#290" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(7)} -pin  "ACC1:acc#290" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load inst "ACC1:acc#292" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 33836 -attr oid 1000 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292} -attr area 10.253676 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,0,10)"
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1:acc#292" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {GND} -pin  "ACC1:acc#292" {A(1)} -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1:acc#292" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {GND} -pin  "ACC1:acc#292" {A(3)} -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1:acc#292" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {GND} -pin  "ACC1:acc#292" {A(5)} -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1:acc#292" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {GND} -pin  "ACC1:acc#292" {A(7)} -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1:acc#292" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#624.itm}
+load net {ACC1:acc#290.itm(0)} -pin  "ACC1:acc#292" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(1)} -pin  "ACC1:acc#292" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(2)} -pin  "ACC1:acc#292" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(3)} -pin  "ACC1:acc#292" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(4)} -pin  "ACC1:acc#292" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(5)} -pin  "ACC1:acc#292" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(6)} -pin  "ACC1:acc#292" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#290.itm(7)} -pin  "ACC1:acc#292" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#290.itm}
+load net {ACC1:acc#292.itm(0)} -pin  "ACC1:acc#292" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(1)} -pin  "ACC1:acc#292" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(2)} -pin  "ACC1:acc#292" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(3)} -pin  "ACC1:acc#292" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(4)} -pin  "ACC1:acc#292" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(5)} -pin  "ACC1:acc#292" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(6)} -pin  "ACC1:acc#292" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(7)} -pin  "ACC1:acc#292" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(8)} -pin  "ACC1:acc#292" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(9)} -pin  "ACC1:acc#292" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load inst "ACC1:acc#269" "add(3,1,2,1,4)" "INTERFACE" -attr xrf 33837 -attr oid 1001 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#269} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#269" {A(0)} -attr @path {/sobel/sobel:core/conc#631.itm}
+load net {acc#10.psp#2.sva(3)} -pin  "ACC1:acc#269" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#631.itm}
+load net {PWR} -pin  "ACC1:acc#269" {A(2)} -attr @path {/sobel/sobel:core/conc#631.itm}
+load net {acc#10.psp#2.sva(4)} -pin  "ACC1:acc#269" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#597.itm}
+load net {ACC1:acc#113.psp#2.sva(3)} -pin  "ACC1:acc#269" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#597.itm}
+load net {ACC1:acc#269.itm(0)} -pin  "ACC1:acc#269" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(1)} -pin  "ACC1:acc#269" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(2)} -pin  "ACC1:acc#269" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load net {ACC1:acc#269.itm(3)} -pin  "ACC1:acc#269" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#269.itm}
+load inst "ACC1:acc#278" "add(3,-1,2,1,3)" "INTERFACE" -attr xrf 33838 -attr oid 1002 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {ACC1:acc#269.itm(1)} -pin  "ACC1:acc#278" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#75.itm}
+load net {ACC1:acc#269.itm(2)} -pin  "ACC1:acc#278" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#75.itm}
+load net {ACC1:acc#269.itm(3)} -pin  "ACC1:acc#278" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#75.itm}
+load net {ACC1:acc#120.psp#1.sva(1)} -pin  "ACC1:acc#278" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp#1.sva)#2.itm}
+load net {ACC1:acc#120.psp#1.sva(2)} -pin  "ACC1:acc#278" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp#1.sva)#2.itm}
+load net {ACC1:acc#278.itm(0)} -pin  "ACC1:acc#278" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(1)} -pin  "ACC1:acc#278" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(2)} -pin  "ACC1:acc#278" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load inst "ACC1:acc#270" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 33839 -attr oid 1003 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#270" {A(0)} -attr @path {/sobel/sobel:core/conc#632.itm}
+load net {acc#10.psp#2.sva(1)} -pin  "ACC1:acc#270" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#632.itm}
+load net {acc#10.psp#2.sva(3)} -pin  "ACC1:acc#270" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#632.itm}
+load net {ACC1:acc#113.psp#2.sva(1)} -pin  "ACC1:acc#270" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#599.itm}
+load net {acc#10.psp#2.sva(2)} -pin  "ACC1:acc#270" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#599.itm}
+load net {ACC1:acc#113.psp#2.sva(3)} -pin  "ACC1:acc#270" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#599.itm}
+load net {ACC1:acc#270.itm(0)} -pin  "ACC1:acc#270" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(1)} -pin  "ACC1:acc#270" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(2)} -pin  "ACC1:acc#270" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(3)} -pin  "ACC1:acc#270" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load net {ACC1:acc#270.itm(4)} -pin  "ACC1:acc#270" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#270.itm}
+load inst "ACC1:acc#283" "add(3,1,4,-1,4)" "INTERFACE" -attr xrf 33840 -attr oid 1004 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#278.itm(0)} -pin  "ACC1:acc#283" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(1)} -pin  "ACC1:acc#283" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#278.itm(2)} -pin  "ACC1:acc#283" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#278.itm}
+load net {ACC1:acc#270.itm(1)} -pin  "ACC1:acc#283" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#76.itm}
+load net {ACC1:acc#270.itm(2)} -pin  "ACC1:acc#283" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#76.itm}
+load net {ACC1:acc#270.itm(3)} -pin  "ACC1:acc#283" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#76.itm}
+load net {ACC1:acc#270.itm(4)} -pin  "ACC1:acc#283" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#76.itm}
+load net {ACC1:acc#283.itm(0)} -pin  "ACC1:acc#283" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(1)} -pin  "ACC1:acc#283" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(2)} -pin  "ACC1:acc#283" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(3)} -pin  "ACC1:acc#283" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load inst "ACC1:acc#282" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 33841 -attr oid 1005 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#282" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#284.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#282" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#284.itm}
+load net {acc#10.psp#2.sva(4)} -pin  "ACC1:acc#282" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#284.itm}
+load net {acc#10.psp#2.sva(7)} -pin  "ACC1:acc#282" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#284.itm}
+load net {ACC1:acc#277.cse(0)} -pin  "ACC1:acc#282" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#277.cse(1)} -pin  "ACC1:acc#282" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#277.cse(2)} -pin  "ACC1:acc#282" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#282.itm(0)} -pin  "ACC1:acc#282" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(1)} -pin  "ACC1:acc#282" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(2)} -pin  "ACC1:acc#282" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(3)} -pin  "ACC1:acc#282" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(4)} -pin  "ACC1:acc#282" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load inst "ACC1:acc#286" "add(4,1,5,0,6)" "INTERFACE" -attr xrf 33842 -attr oid 1006 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#283.itm(0)} -pin  "ACC1:acc#286" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(1)} -pin  "ACC1:acc#286" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(2)} -pin  "ACC1:acc#286" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#283.itm(3)} -pin  "ACC1:acc#286" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#283.itm}
+load net {ACC1:acc#282.itm(0)} -pin  "ACC1:acc#286" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(1)} -pin  "ACC1:acc#286" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(2)} -pin  "ACC1:acc#286" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(3)} -pin  "ACC1:acc#286" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#282.itm(4)} -pin  "ACC1:acc#286" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#282.itm}
+load net {ACC1:acc#286.itm(0)} -pin  "ACC1:acc#286" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(1)} -pin  "ACC1:acc#286" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(2)} -pin  "ACC1:acc#286" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(3)} -pin  "ACC1:acc#286" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(4)} -pin  "ACC1:acc#286" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(5)} -pin  "ACC1:acc#286" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load inst "ACC1:acc#289" "add(6,1,7,0,8)" "INTERFACE" -attr xrf 33843 -attr oid 1007 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#286.itm(0)} -pin  "ACC1:acc#289" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(1)} -pin  "ACC1:acc#289" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(2)} -pin  "ACC1:acc#289" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(3)} -pin  "ACC1:acc#289" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(4)} -pin  "ACC1:acc#289" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {ACC1:acc#286.itm(5)} -pin  "ACC1:acc#289" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#286.itm}
+load net {acc#10.psp#2.sva(8)} -pin  "ACC1:acc#289" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {GND} -pin  "ACC1:acc#289" {B(1)} -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {acc#10.psp#2.sva(8)} -pin  "ACC1:acc#289" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {GND} -pin  "ACC1:acc#289" {B(3)} -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {acc#10.psp#2.sva(8)} -pin  "ACC1:acc#289" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {GND} -pin  "ACC1:acc#289" {B(5)} -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {acc#10.psp#2.sva(8)} -pin  "ACC1:acc#289" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#633.itm}
+load net {ACC1:acc#289.itm(0)} -pin  "ACC1:acc#289" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(1)} -pin  "ACC1:acc#289" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(2)} -pin  "ACC1:acc#289" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(3)} -pin  "ACC1:acc#289" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(4)} -pin  "ACC1:acc#289" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(5)} -pin  "ACC1:acc#289" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(6)} -pin  "ACC1:acc#289" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(7)} -pin  "ACC1:acc#289" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load inst "ACC1-1:not#92" "not(1)" "INTERFACE" -attr xrf 33844 -attr oid 1008 -attr @path {/sobel/sobel:core/ACC1-1:not#92} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#161.itm(2)} -pin  "ACC1-1:not#92" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva).itm}
+load net {ACC1-1:not#92.itm} -pin  "ACC1-1:not#92" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#92.itm}
+load inst "ACC1-1:and#5" "and(3,1)" "INTERFACE" -attr xrf 33845 -attr oid 1009 -attr @path {/sobel/sobel:core/ACC1-1:and#5} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:and#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#37.itm}
+load net {ACC1-1:not#92.itm} -pin  "ACC1-1:and#5" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#92.itm}
+load net {ACC1:acc#161.itm(1)} -pin  "ACC1-1:and#5" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#24.sva)#1.itm}
+load net {ACC1-1:and#5.itm} -pin  "ACC1-1:and#5" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#5.itm}
+load inst "ACC1:acc#275" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33846 -attr oid 1010 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#275" {A(0)} -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {acc#10.psp#2.sva(7)} -pin  "ACC1:acc#275" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {acc#10.psp#2.sva(7)} -pin  "ACC1:acc#275" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#59.itm}
+load net {ACC1-1:and#5.itm} -pin  "ACC1:acc#275" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#782.itm}
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1:acc#275" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#782.itm}
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1:acc#275" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#782.itm}
+load net {ACC1:acc#275.itm(0)} -pin  "ACC1:acc#275" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(1)} -pin  "ACC1:acc#275" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(2)} -pin  "ACC1:acc#275" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load net {ACC1:acc#275.itm(3)} -pin  "ACC1:acc#275" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#275.itm}
+load inst "ACC1:acc#281" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33847 -attr oid 1011 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#277.cse(0)} -pin  "ACC1:acc#281" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#277.cse(1)} -pin  "ACC1:acc#281" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#277.cse(2)} -pin  "ACC1:acc#281" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#275.itm(1)} -pin  "ACC1:acc#281" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#81.itm}
+load net {ACC1:acc#275.itm(2)} -pin  "ACC1:acc#281" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#81.itm}
+load net {ACC1:acc#275.itm(3)} -pin  "ACC1:acc#281" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#81.itm}
+load net {ACC1:acc#281.itm(0)} -pin  "ACC1:acc#281" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(1)} -pin  "ACC1:acc#281" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(2)} -pin  "ACC1:acc#281" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(3)} -pin  "ACC1:acc#281" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load inst "ACC1:acc#285" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 33848 -attr oid 1012 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {acc#10.psp#2.sva(6)} -pin  "ACC1:acc#285" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#634.itm}
+load net {GND} -pin  "ACC1:acc#285" {A(1)} -attr @path {/sobel/sobel:core/conc#634.itm}
+load net {acc#10.psp#2.sva(6)} -pin  "ACC1:acc#285" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#634.itm}
+load net {GND} -pin  "ACC1:acc#285" {A(3)} -attr @path {/sobel/sobel:core/conc#634.itm}
+load net {acc#10.psp#2.sva(6)} -pin  "ACC1:acc#285" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#634.itm}
+load net {ACC1:acc#281.itm(0)} -pin  "ACC1:acc#285" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(1)} -pin  "ACC1:acc#285" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(2)} -pin  "ACC1:acc#285" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#281.itm(3)} -pin  "ACC1:acc#285" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#281.itm}
+load net {ACC1:acc#285.itm(0)} -pin  "ACC1:acc#285" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(1)} -pin  "ACC1:acc#285" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(2)} -pin  "ACC1:acc#285" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(3)} -pin  "ACC1:acc#285" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(4)} -pin  "ACC1:acc#285" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(5)} -pin  "ACC1:acc#285" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load inst "ACC1:acc#288" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 33849 -attr oid 1013 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#288" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#544.itm}
+load net {ACC1:acc#285.itm(0)} -pin  "ACC1:acc#288" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(1)} -pin  "ACC1:acc#288" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(2)} -pin  "ACC1:acc#288" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(3)} -pin  "ACC1:acc#288" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(4)} -pin  "ACC1:acc#288" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#285.itm(5)} -pin  "ACC1:acc#288" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#285.itm}
+load net {ACC1:acc#288.itm(0)} -pin  "ACC1:acc#288" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(1)} -pin  "ACC1:acc#288" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(2)} -pin  "ACC1:acc#288" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(3)} -pin  "ACC1:acc#288" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(4)} -pin  "ACC1:acc#288" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(5)} -pin  "ACC1:acc#288" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(6)} -pin  "ACC1:acc#288" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(7)} -pin  "ACC1:acc#288" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load inst "ACC1:acc#291" "add(8,1,8,0,10)" "INTERFACE" -attr xrf 33850 -attr oid 1014 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#289.itm(0)} -pin  "ACC1:acc#291" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(1)} -pin  "ACC1:acc#291" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(2)} -pin  "ACC1:acc#291" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(3)} -pin  "ACC1:acc#291" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(4)} -pin  "ACC1:acc#291" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(5)} -pin  "ACC1:acc#291" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(6)} -pin  "ACC1:acc#291" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#289.itm(7)} -pin  "ACC1:acc#291" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#289.itm}
+load net {ACC1:acc#288.itm(0)} -pin  "ACC1:acc#291" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(1)} -pin  "ACC1:acc#291" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(2)} -pin  "ACC1:acc#291" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(3)} -pin  "ACC1:acc#291" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(4)} -pin  "ACC1:acc#291" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(5)} -pin  "ACC1:acc#291" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(6)} -pin  "ACC1:acc#291" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#288.itm(7)} -pin  "ACC1:acc#291" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#288.itm}
+load net {ACC1:acc#291.itm(0)} -pin  "ACC1:acc#291" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(1)} -pin  "ACC1:acc#291" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(2)} -pin  "ACC1:acc#291" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(3)} -pin  "ACC1:acc#291" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(4)} -pin  "ACC1:acc#291" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(5)} -pin  "ACC1:acc#291" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(6)} -pin  "ACC1:acc#291" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(7)} -pin  "ACC1:acc#291" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(8)} -pin  "ACC1:acc#291" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(9)} -pin  "ACC1:acc#291" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load inst "ACC1:acc#294" "add(10,0,10,1,11)" "INTERFACE" -attr xrf 33851 -attr oid 1015 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11)"
+load net {ACC1:acc#292.itm(0)} -pin  "ACC1:acc#294" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(1)} -pin  "ACC1:acc#294" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(2)} -pin  "ACC1:acc#294" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(3)} -pin  "ACC1:acc#294" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(4)} -pin  "ACC1:acc#294" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(5)} -pin  "ACC1:acc#294" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(6)} -pin  "ACC1:acc#294" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(7)} -pin  "ACC1:acc#294" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(8)} -pin  "ACC1:acc#294" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#292.itm(9)} -pin  "ACC1:acc#294" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#292.itm}
+load net {ACC1:acc#291.itm(0)} -pin  "ACC1:acc#294" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(1)} -pin  "ACC1:acc#294" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(2)} -pin  "ACC1:acc#294" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(3)} -pin  "ACC1:acc#294" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(4)} -pin  "ACC1:acc#294" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(5)} -pin  "ACC1:acc#294" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(6)} -pin  "ACC1:acc#294" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(7)} -pin  "ACC1:acc#294" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(8)} -pin  "ACC1:acc#294" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#291.itm(9)} -pin  "ACC1:acc#294" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#291.itm}
+load net {ACC1:acc#294.itm(0)} -pin  "ACC1:acc#294" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(1)} -pin  "ACC1:acc#294" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(2)} -pin  "ACC1:acc#294" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(3)} -pin  "ACC1:acc#294" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(4)} -pin  "ACC1:acc#294" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(5)} -pin  "ACC1:acc#294" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(6)} -pin  "ACC1:acc#294" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(7)} -pin  "ACC1:acc#294" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(8)} -pin  "ACC1:acc#294" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(9)} -pin  "ACC1:acc#294" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(10)} -pin  "ACC1:acc#294" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load inst "ACC1:acc#346" "add(1,0,2,0,3)" "INTERFACE" -attr xrf 33852 -attr oid 1016 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,3)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#346" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#13.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#346" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#849.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#346" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#849.itm}
+load net {ACC1:acc#346.itm(0)} -pin  "ACC1:acc#346" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:acc#346.itm(1)} -pin  "ACC1:acc#346" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load net {ACC1:acc#346.itm(2)} -pin  "ACC1:acc#346" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#346.itm}
+load inst "ACC1-1:acc#124" "add(11,-1,11,-1,11)" "INTERFACE" -attr xrf 33853 -attr oid 1017 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13)"
+load net {ACC1:acc#294.itm(0)} -pin  "ACC1-1:acc#124" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(1)} -pin  "ACC1-1:acc#124" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(2)} -pin  "ACC1-1:acc#124" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(3)} -pin  "ACC1-1:acc#124" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(4)} -pin  "ACC1-1:acc#124" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(5)} -pin  "ACC1-1:acc#124" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(6)} -pin  "ACC1-1:acc#124" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(7)} -pin  "ACC1-1:acc#124" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(8)} -pin  "ACC1-1:acc#124" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(9)} -pin  "ACC1-1:acc#124" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#294.itm(10)} -pin  "ACC1-1:acc#124" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#294.itm}
+load net {ACC1:acc#346.itm(0)} -pin  "ACC1-1:acc#124" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {ACC1:acc#346.itm(1)} -pin  "ACC1-1:acc#124" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {ACC1:acc#346.itm(2)} -pin  "ACC1-1:acc#124" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:acc#124" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {GND} -pin  "ACC1-1:acc#124" {B(4)} -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:acc#124" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {GND} -pin  "ACC1-1:acc#124" {B(6)} -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:acc#124" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {GND} -pin  "ACC1-1:acc#124" {B(8)} -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {GND} -pin  "ACC1-1:acc#124" {B(9)} -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:acc#124" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#637.itm}
+load net {ACC1-1:acc#124.itm(0)} -pin  "ACC1-1:acc#124" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(1)} -pin  "ACC1-1:acc#124" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(2)} -pin  "ACC1-1:acc#124" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(3)} -pin  "ACC1-1:acc#124" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(4)} -pin  "ACC1-1:acc#124" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(5)} -pin  "ACC1-1:acc#124" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(6)} -pin  "ACC1-1:acc#124" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(7)} -pin  "ACC1-1:acc#124" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(8)} -pin  "ACC1-1:acc#124" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(9)} -pin  "ACC1-1:acc#124" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(10)} -pin  "ACC1-1:acc#124" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load inst "ACC1-3:not#164" "not(1)" "INTERFACE" -attr xrf 33854 -attr oid 1018 -attr @path {/sobel/sobel:core/ACC1-3:not#164} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1-3:not#164" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#57.itm}
+load net {ACC1-3:not#164.itm} -pin  "ACC1-3:not#164" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#164.itm}
+load inst "ACC1-3:nand#2" "nand(2,1)" "INTERFACE" -attr xrf 33855 -attr oid 1019 -attr @path {/sobel/sobel:core/ACC1-3:nand#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#188.itm(2)} -pin  "ACC1-3:nand#2" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#11.sva).itm}
+load net {ACC1-3:not#164.itm} -pin  "ACC1-3:nand#2" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#164.itm}
+load net {ACC1-3:nand#2.itm} -pin  "ACC1-3:nand#2" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand#2.itm}
+load inst "ACC1:acc#247" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33856 -attr oid 1020 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#247" {A(0)} -attr @path {/sobel/sobel:core/exs#42.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#247" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#42.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#247" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#42.itm}
+load net {ACC1-3:nand#2.itm} -pin  "ACC1:acc#247" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#785.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#247" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#785.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#247" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#785.itm}
+load net {ACC1:acc#247.itm(0)} -pin  "ACC1:acc#247" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(1)} -pin  "ACC1:acc#247" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(2)} -pin  "ACC1:acc#247" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load net {ACC1:acc#247.itm(3)} -pin  "ACC1:acc#247" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#247.itm}
+load inst "ACC1-3:not#165" "not(1)" "INTERFACE" -attr xrf 33857 -attr oid 1021 -attr @path {/sobel/sobel:core/ACC1-3:not#165} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#187.itm(3)} -pin  "ACC1-3:not#165" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#10.sva)#4.itm}
+load net {ACC1-3:not#165.itm} -pin  "ACC1-3:not#165" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#165.itm}
+load inst "ACC1:acc#246" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33858 -attr oid 1022 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#246" {A(0)} -attr @path {/sobel/sobel:core/exs#43.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#246" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#43.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#246" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#43.itm}
+load net {ACC1-3:not#165.itm} -pin  "ACC1:acc#246" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#787.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#246" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#787.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#246" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#787.itm}
+load net {ACC1:acc#246.itm(0)} -pin  "ACC1:acc#246" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(1)} -pin  "ACC1:acc#246" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(2)} -pin  "ACC1:acc#246" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load net {ACC1:acc#246.itm(3)} -pin  "ACC1:acc#246" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#246.itm}
+load inst "ACC1:acc#253" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33859 -attr oid 1023 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#247.itm(1)} -pin  "ACC1:acc#253" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#247.itm(2)} -pin  "ACC1:acc#253" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#247.itm(3)} -pin  "ACC1:acc#253" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#73.itm}
+load net {ACC1:acc#246.itm(1)} -pin  "ACC1:acc#253" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#246.itm(2)} -pin  "ACC1:acc#253" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#246.itm(3)} -pin  "ACC1:acc#253" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#72.itm}
+load net {ACC1:acc#253.itm(0)} -pin  "ACC1:acc#253" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(1)} -pin  "ACC1:acc#253" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(2)} -pin  "ACC1:acc#253" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(3)} -pin  "ACC1:acc#253" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load inst "ACC1:acc#245" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33860 -attr oid 1024 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#245" {A(0)} -attr @path {/sobel/sobel:core/exs#44.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#245" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#44.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#245" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#44.itm}
+load net {ACC1:acc#187.itm(2)} -pin  "ACC1:acc#245" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#789.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#245" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#789.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#245" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#789.itm}
+load net {ACC1:acc#245.itm(0)} -pin  "ACC1:acc#245" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(1)} -pin  "ACC1:acc#245" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(2)} -pin  "ACC1:acc#245" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load net {ACC1:acc#245.itm(3)} -pin  "ACC1:acc#245" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#245.itm}
+load inst "ACC1:acc#244" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33861 -attr oid 1025 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#244} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#244" {A(0)} -attr @path {/sobel/sobel:core/exs#45.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#244" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#45.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#244" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#45.itm}
+load net {ACC1:acc#113.psp#1.sva(2)} -pin  "ACC1:acc#244" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#791.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#244" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#791.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#244" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#791.itm}
+load net {ACC1:acc#244.itm(0)} -pin  "ACC1:acc#244" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#244.itm}
+load net {ACC1:acc#244.itm(1)} -pin  "ACC1:acc#244" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#244.itm}
+load net {ACC1:acc#244.itm(2)} -pin  "ACC1:acc#244" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#244.itm}
+load net {ACC1:acc#244.itm(3)} -pin  "ACC1:acc#244" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#244.itm}
+load inst "ACC1:acc#252" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33862 -attr oid 1026 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#245.itm(1)} -pin  "ACC1:acc#252" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#71.itm}
+load net {ACC1:acc#245.itm(2)} -pin  "ACC1:acc#252" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#71.itm}
+load net {ACC1:acc#245.itm(3)} -pin  "ACC1:acc#252" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#71.itm}
+load net {ACC1:acc#244.itm(1)} -pin  "ACC1:acc#252" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#70.itm}
+load net {ACC1:acc#244.itm(2)} -pin  "ACC1:acc#252" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#70.itm}
+load net {ACC1:acc#244.itm(3)} -pin  "ACC1:acc#252" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#70.itm}
+load net {ACC1:acc#252.itm(0)} -pin  "ACC1:acc#252" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(1)} -pin  "ACC1:acc#252" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(2)} -pin  "ACC1:acc#252" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(3)} -pin  "ACC1:acc#252" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load inst "ACC1:acc#257" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 33863 -attr oid 1027 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#253.itm(0)} -pin  "ACC1:acc#257" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(1)} -pin  "ACC1:acc#257" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(2)} -pin  "ACC1:acc#257" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#253.itm(3)} -pin  "ACC1:acc#257" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#253.itm}
+load net {ACC1:acc#252.itm(0)} -pin  "ACC1:acc#257" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(1)} -pin  "ACC1:acc#257" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(2)} -pin  "ACC1:acc#257" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#252.itm(3)} -pin  "ACC1:acc#257" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#252.itm}
+load net {ACC1:acc#257.itm(0)} -pin  "ACC1:acc#257" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(1)} -pin  "ACC1:acc#257" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(2)} -pin  "ACC1:acc#257" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(3)} -pin  "ACC1:acc#257" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(4)} -pin  "ACC1:acc#257" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load inst "ACC1:acc#260" "add(6,0,5,0,7)" "INTERFACE" -attr xrf 33864 -attr oid 1028 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#260" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#260" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {GND} -pin  "ACC1:acc#260" {A(2)} -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {acc#10.psp#1.sva(5)} -pin  "ACC1:acc#260" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {GND} -pin  "ACC1:acc#260" {A(4)} -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {acc#10.psp#1.sva(7)} -pin  "ACC1:acc#260" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#640.itm}
+load net {ACC1:acc#257.itm(0)} -pin  "ACC1:acc#260" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(1)} -pin  "ACC1:acc#260" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(2)} -pin  "ACC1:acc#260" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(3)} -pin  "ACC1:acc#260" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#257.itm(4)} -pin  "ACC1:acc#260" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#257.itm}
+load net {ACC1:acc#260.itm(0)} -pin  "ACC1:acc#260" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(1)} -pin  "ACC1:acc#260" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(2)} -pin  "ACC1:acc#260" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(3)} -pin  "ACC1:acc#260" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(4)} -pin  "ACC1:acc#260" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(5)} -pin  "ACC1:acc#260" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(6)} -pin  "ACC1:acc#260" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load inst "ACC1:acc#263" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 33865 -attr oid 1029 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {acc#10.psp#1.sva(5)} -pin  "ACC1:acc#263" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {acc#10.psp#1.sva(5)} -pin  "ACC1:acc#263" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {GND} -pin  "ACC1:acc#263" {A(2)} -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1:acc#263" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {GND} -pin  "ACC1:acc#263" {A(4)} -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1:acc#263" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {GND} -pin  "ACC1:acc#263" {A(6)} -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1:acc#263" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#639.itm}
+load net {ACC1:acc#260.itm(0)} -pin  "ACC1:acc#263" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(1)} -pin  "ACC1:acc#263" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(2)} -pin  "ACC1:acc#263" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(3)} -pin  "ACC1:acc#263" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(4)} -pin  "ACC1:acc#263" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(5)} -pin  "ACC1:acc#263" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#260.itm(6)} -pin  "ACC1:acc#263" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#260.itm}
+load net {ACC1:acc#263.itm(0)} -pin  "ACC1:acc#263" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(1)} -pin  "ACC1:acc#263" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(2)} -pin  "ACC1:acc#263" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(3)} -pin  "ACC1:acc#263" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(4)} -pin  "ACC1:acc#263" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(5)} -pin  "ACC1:acc#263" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(6)} -pin  "ACC1:acc#263" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(7)} -pin  "ACC1:acc#263" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load inst "ACC1:acc#265" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 33866 -attr oid 1030 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265} -attr area 10.253676 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,0,10)"
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1:acc#265" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {GND} -pin  "ACC1:acc#265" {A(1)} -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1:acc#265" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {GND} -pin  "ACC1:acc#265" {A(3)} -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1:acc#265" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {GND} -pin  "ACC1:acc#265" {A(5)} -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1:acc#265" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {GND} -pin  "ACC1:acc#265" {A(7)} -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1:acc#265" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#638.itm}
+load net {ACC1:acc#263.itm(0)} -pin  "ACC1:acc#265" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(1)} -pin  "ACC1:acc#265" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(2)} -pin  "ACC1:acc#265" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(3)} -pin  "ACC1:acc#265" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(4)} -pin  "ACC1:acc#265" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(5)} -pin  "ACC1:acc#265" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(6)} -pin  "ACC1:acc#265" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#263.itm(7)} -pin  "ACC1:acc#265" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#263.itm}
+load net {ACC1:acc#265.itm(0)} -pin  "ACC1:acc#265" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(1)} -pin  "ACC1:acc#265" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(2)} -pin  "ACC1:acc#265" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(3)} -pin  "ACC1:acc#265" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(4)} -pin  "ACC1:acc#265" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(5)} -pin  "ACC1:acc#265" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(6)} -pin  "ACC1:acc#265" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(7)} -pin  "ACC1:acc#265" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(8)} -pin  "ACC1:acc#265" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(9)} -pin  "ACC1:acc#265" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load inst "ACC1:acc#267" "add(11,1,10,0,12)" "INTERFACE" -attr xrf 33867 -attr oid 1031 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13)"
+load net {ACC1-1:acc#124.itm(0)} -pin  "ACC1:acc#267" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(1)} -pin  "ACC1:acc#267" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(2)} -pin  "ACC1:acc#267" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(3)} -pin  "ACC1:acc#267" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(4)} -pin  "ACC1:acc#267" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(5)} -pin  "ACC1:acc#267" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(6)} -pin  "ACC1:acc#267" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(7)} -pin  "ACC1:acc#267" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(8)} -pin  "ACC1:acc#267" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(9)} -pin  "ACC1:acc#267" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1-1:acc#124.itm(10)} -pin  "ACC1:acc#267" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#124.itm}
+load net {ACC1:acc#265.itm(0)} -pin  "ACC1:acc#267" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(1)} -pin  "ACC1:acc#267" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(2)} -pin  "ACC1:acc#267" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(3)} -pin  "ACC1:acc#267" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(4)} -pin  "ACC1:acc#267" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(5)} -pin  "ACC1:acc#267" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(6)} -pin  "ACC1:acc#267" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(7)} -pin  "ACC1:acc#267" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(8)} -pin  "ACC1:acc#267" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#265.itm(9)} -pin  "ACC1:acc#267" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#265.itm}
+load net {ACC1:acc#267.itm(0)} -pin  "ACC1:acc#267" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(1)} -pin  "ACC1:acc#267" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(2)} -pin  "ACC1:acc#267" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(3)} -pin  "ACC1:acc#267" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(4)} -pin  "ACC1:acc#267" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(5)} -pin  "ACC1:acc#267" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(6)} -pin  "ACC1:acc#267" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(7)} -pin  "ACC1:acc#267" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(8)} -pin  "ACC1:acc#267" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(9)} -pin  "ACC1:acc#267" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(10)} -pin  "ACC1:acc#267" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(11)} -pin  "ACC1:acc#267" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load inst "ACC1-3:acc#124" "add(11,1,12,-1,12)" "INTERFACE" -attr xrf 33868 -attr oid 1032 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1:acc#268.itm(0)} -pin  "ACC1-3:acc#124" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(1)} -pin  "ACC1-3:acc#124" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(2)} -pin  "ACC1-3:acc#124" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(3)} -pin  "ACC1-3:acc#124" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(4)} -pin  "ACC1-3:acc#124" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(5)} -pin  "ACC1-3:acc#124" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(6)} -pin  "ACC1-3:acc#124" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(7)} -pin  "ACC1-3:acc#124" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(8)} -pin  "ACC1-3:acc#124" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(9)} -pin  "ACC1-3:acc#124" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#268.itm(10)} -pin  "ACC1-3:acc#124" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#268.itm}
+load net {ACC1:acc#267.itm(0)} -pin  "ACC1-3:acc#124" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(1)} -pin  "ACC1-3:acc#124" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(2)} -pin  "ACC1-3:acc#124" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(3)} -pin  "ACC1-3:acc#124" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(4)} -pin  "ACC1-3:acc#124" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(5)} -pin  "ACC1-3:acc#124" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(6)} -pin  "ACC1-3:acc#124" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(7)} -pin  "ACC1-3:acc#124" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(8)} -pin  "ACC1-3:acc#124" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(9)} -pin  "ACC1-3:acc#124" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(10)} -pin  "ACC1-3:acc#124" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1:acc#267.itm(11)} -pin  "ACC1-3:acc#124" {B(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#267.itm}
+load net {ACC1-3:acc#124.itm(0)} -pin  "ACC1-3:acc#124" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(1)} -pin  "ACC1-3:acc#124" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(2)} -pin  "ACC1-3:acc#124" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(3)} -pin  "ACC1-3:acc#124" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(4)} -pin  "ACC1-3:acc#124" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(5)} -pin  "ACC1-3:acc#124" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(6)} -pin  "ACC1-3:acc#124" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(7)} -pin  "ACC1-3:acc#124" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(8)} -pin  "ACC1-3:acc#124" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(9)} -pin  "ACC1-3:acc#124" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(10)} -pin  "ACC1-3:acc#124" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(11)} -pin  "ACC1-3:acc#124" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load inst "reg(FRAME:for:slc(in(2).sva).itm#1)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 33869 -attr oid 1033 -attr vt dc -attr @path {/sobel/sobel:core/reg(FRAME:for:slc(in(2).sva).itm#1)}
+load net {ACC1-3:acc#124.itm(0)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(1)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(2)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(3)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(4)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(5)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(6)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(7)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(8)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(9)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(10)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {ACC1-3:acc#124.itm(11)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {D(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-3:acc#124.itm}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {clk} -attr xrf 33870 -attr oid 1034 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:for:slc(in(2).sva).itm#1(0)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(1)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(2)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(3)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(4)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(5)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(6)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(7)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(8)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(9)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(10)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -pin  "reg(FRAME:for:slc(in(2).sva).itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(2).sva).itm#1}
+load inst "reg(exit:FRAME:for.lpi#1.dfm#3)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 33871 -attr oid 1035 -attr @path {/sobel/sobel:core/reg(exit:FRAME:for.lpi#1.dfm#3)}
+load net {exit:FRAME:for.lpi#1.dfm#4} -pin  "reg(exit:FRAME:for.lpi#1.dfm#3)" {D(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#4}
+load net {GND} -pin  "reg(exit:FRAME:for.lpi#1.dfm#3)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(exit:FRAME:for.lpi#1.dfm#3)" {clk} -attr xrf 33872 -attr oid 1036 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for.lpi#1.dfm#3)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for.lpi#1.dfm#3)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for.lpi#1.dfm#3} -pin  "reg(exit:FRAME:for.lpi#1.dfm#3)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#3}
+load inst "regs.operator[]#10:mux" "mux(4,10)" "INTERFACE" -attr xrf 33873 -attr oid 1037 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(10)} -pin  "regs.operator[]#10:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(11)} -pin  "regs.operator[]#10:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(12)} -pin  "regs.operator[]#10:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(13)} -pin  "regs.operator[]#10:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(14)} -pin  "regs.operator[]#10:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(15)} -pin  "regs.operator[]#10:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(16)} -pin  "regs.operator[]#10:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(17)} -pin  "regs.operator[]#10:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(18)} -pin  "regs.operator[]#10:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(19)} -pin  "regs.operator[]#10:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "regs.operator[]#10:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "regs.operator[]#10:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "regs.operator[]#10:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "regs.operator[]#10:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "regs.operator[]#10:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "regs.operator[]#10:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "regs.operator[]#10:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "regs.operator[]#10:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "regs.operator[]#10:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "regs.operator[]#10:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "regs.operator[]#10:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "regs.operator[]#10:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "regs.operator[]#10:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "regs.operator[]#10:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "regs.operator[]#10:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "regs.operator[]#10:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "regs.operator[]#10:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "regs.operator[]#10:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "regs.operator[]#10:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "regs.operator[]#10:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#10:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#10:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#10:mux.itm(0)} -pin  "regs.operator[]#10:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(1)} -pin  "regs.operator[]#10:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(2)} -pin  "regs.operator[]#10:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(3)} -pin  "regs.operator[]#10:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(4)} -pin  "regs.operator[]#10:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(5)} -pin  "regs.operator[]#10:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(6)} -pin  "regs.operator[]#10:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(7)} -pin  "regs.operator[]#10:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(8)} -pin  "regs.operator[]#10:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(9)} -pin  "regs.operator[]#10:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load inst "FRAME:for:mul#1" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 33874 -attr oid 1038 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#10:mux.itm(0)} -pin  "FRAME:for:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(1)} -pin  "FRAME:for:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(2)} -pin  "FRAME:for:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(3)} -pin  "FRAME:for:mul#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(4)} -pin  "FRAME:for:mul#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(5)} -pin  "FRAME:for:mul#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(6)} -pin  "FRAME:for:mul#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(7)} -pin  "FRAME:for:mul#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(8)} -pin  "FRAME:for:mul#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(9)} -pin  "FRAME:for:mul#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#645.itm}
+load net {PWR} -pin  "FRAME:for:mul#1" {B(1)} -attr @path {/sobel/sobel:core/conc#645.itm}
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:mul#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:mul#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(11)} -pin  "FRAME:for:mul#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load inst "regs.operator[]#11:mux" "mux(4,10)" "INTERFACE" -attr xrf 33875 -attr oid 1039 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(0)} -pin  "regs.operator[]#11:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(1)} -pin  "regs.operator[]#11:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(2)} -pin  "regs.operator[]#11:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(3)} -pin  "regs.operator[]#11:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(4)} -pin  "regs.operator[]#11:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(5)} -pin  "regs.operator[]#11:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(6)} -pin  "regs.operator[]#11:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(7)} -pin  "regs.operator[]#11:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(8)} -pin  "regs.operator[]#11:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(9)} -pin  "regs.operator[]#11:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "regs.operator[]#11:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "regs.operator[]#11:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "regs.operator[]#11:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "regs.operator[]#11:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "regs.operator[]#11:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "regs.operator[]#11:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "regs.operator[]#11:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "regs.operator[]#11:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "regs.operator[]#11:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "regs.operator[]#11:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "regs.operator[]#11:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "regs.operator[]#11:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "regs.operator[]#11:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "regs.operator[]#11:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "regs.operator[]#11:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "regs.operator[]#11:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "regs.operator[]#11:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "regs.operator[]#11:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "regs.operator[]#11:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "regs.operator[]#11:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#11:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#11:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#11:mux.itm(0)} -pin  "regs.operator[]#11:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(1)} -pin  "regs.operator[]#11:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(2)} -pin  "regs.operator[]#11:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(3)} -pin  "regs.operator[]#11:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(4)} -pin  "regs.operator[]#11:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(5)} -pin  "regs.operator[]#11:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(6)} -pin  "regs.operator[]#11:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(7)} -pin  "regs.operator[]#11:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(8)} -pin  "regs.operator[]#11:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(9)} -pin  "regs.operator[]#11:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load inst "FRAME:for:mul#2" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 33876 -attr oid 1040 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#11:mux.itm(0)} -pin  "FRAME:for:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(1)} -pin  "FRAME:for:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(2)} -pin  "FRAME:for:mul#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(3)} -pin  "FRAME:for:mul#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(4)} -pin  "FRAME:for:mul#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(5)} -pin  "FRAME:for:mul#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(6)} -pin  "FRAME:for:mul#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(7)} -pin  "FRAME:for:mul#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(8)} -pin  "FRAME:for:mul#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(9)} -pin  "FRAME:for:mul#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#646.itm}
+load net {PWR} -pin  "FRAME:for:mul#2" {B(1)} -attr @path {/sobel/sobel:core/conc#646.itm}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(11)} -pin  "FRAME:for:mul#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load inst "FRAME:for:acc#23" "add(12,1,12,1,13)" "INTERFACE" -attr xrf 33877 -attr oid 1041 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:acc#23" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:acc#23" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:acc#23" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:acc#23" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:acc#23" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:acc#23" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:acc#23" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:acc#23" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:acc#23" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:acc#23" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:acc#23" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(11)} -pin  "FRAME:for:acc#23" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:acc#23" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:acc#23" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:acc#23" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:acc#23" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:acc#23" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:acc#23" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:acc#23" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:acc#23" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:acc#23" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:acc#23" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:acc#23" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(11)} -pin  "FRAME:for:acc#23" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:acc#23.itm(0)} -pin  "FRAME:for:acc#23" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(1)} -pin  "FRAME:for:acc#23" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(2)} -pin  "FRAME:for:acc#23" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(3)} -pin  "FRAME:for:acc#23" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(4)} -pin  "FRAME:for:acc#23" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(5)} -pin  "FRAME:for:acc#23" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(6)} -pin  "FRAME:for:acc#23" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(7)} -pin  "FRAME:for:acc#23" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(8)} -pin  "FRAME:for:acc#23" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(9)} -pin  "FRAME:for:acc#23" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(10)} -pin  "FRAME:for:acc#23" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(11)} -pin  "FRAME:for:acc#23" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(12)} -pin  "FRAME:for:acc#23" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load inst "regs.operator[]#9:mux" "mux(4,10)" "INTERFACE" -attr xrf 33878 -attr oid 1042 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(20)} -pin  "regs.operator[]#9:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(21)} -pin  "regs.operator[]#9:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(22)} -pin  "regs.operator[]#9:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(23)} -pin  "regs.operator[]#9:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(24)} -pin  "regs.operator[]#9:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(25)} -pin  "regs.operator[]#9:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(26)} -pin  "regs.operator[]#9:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(27)} -pin  "regs.operator[]#9:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(28)} -pin  "regs.operator[]#9:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(29)} -pin  "regs.operator[]#9:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm#1:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "regs.operator[]#9:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "regs.operator[]#9:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "regs.operator[]#9:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "regs.operator[]#9:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "regs.operator[]#9:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "regs.operator[]#9:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "regs.operator[]#9:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "regs.operator[]#9:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "regs.operator[]#9:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "regs.operator[]#9:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "regs.operator[]#9:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "regs.operator[]#9:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "regs.operator[]#9:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "regs.operator[]#9:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "regs.operator[]#9:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "regs.operator[]#9:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "regs.operator[]#9:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "regs.operator[]#9:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "regs.operator[]#9:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "regs.operator[]#9:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#9:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#9:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#9:mux.itm(0)} -pin  "regs.operator[]#9:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(1)} -pin  "regs.operator[]#9:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(2)} -pin  "regs.operator[]#9:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(3)} -pin  "regs.operator[]#9:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(4)} -pin  "regs.operator[]#9:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(5)} -pin  "regs.operator[]#9:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(6)} -pin  "regs.operator[]#9:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(7)} -pin  "regs.operator[]#9:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(8)} -pin  "regs.operator[]#9:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(9)} -pin  "regs.operator[]#9:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load inst "FRAME:for:mul" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 33879 -attr oid 1043 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#9:mux.itm(0)} -pin  "FRAME:for:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(1)} -pin  "FRAME:for:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(2)} -pin  "FRAME:for:mul" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(3)} -pin  "FRAME:for:mul" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(4)} -pin  "FRAME:for:mul" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(5)} -pin  "FRAME:for:mul" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(6)} -pin  "FRAME:for:mul" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(7)} -pin  "FRAME:for:mul" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(8)} -pin  "FRAME:for:mul" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(9)} -pin  "FRAME:for:mul" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:mul" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#647.itm}
+load net {PWR} -pin  "FRAME:for:mul" {B(1)} -attr @path {/sobel/sobel:core/conc#647.itm}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(11)} -pin  "FRAME:for:mul" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load inst "FRAME:for:acc#24" "add(13,-1,12,1,13)" "INTERFACE" -attr xrf 33880 -attr oid 1044 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24} -attr area 14.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(13,0,12,1,13)"
+load net {FRAME:for:acc#23.itm(0)} -pin  "FRAME:for:acc#24" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(1)} -pin  "FRAME:for:acc#24" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(2)} -pin  "FRAME:for:acc#24" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(3)} -pin  "FRAME:for:acc#24" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(4)} -pin  "FRAME:for:acc#24" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(5)} -pin  "FRAME:for:acc#24" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(6)} -pin  "FRAME:for:acc#24" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(7)} -pin  "FRAME:for:acc#24" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(8)} -pin  "FRAME:for:acc#24" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(9)} -pin  "FRAME:for:acc#24" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(10)} -pin  "FRAME:for:acc#24" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(11)} -pin  "FRAME:for:acc#24" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:acc#23.itm(12)} -pin  "FRAME:for:acc#24" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#23.itm}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:acc#24" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:acc#24" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:acc#24" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:acc#24" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:acc#24" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:acc#24" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:acc#24" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:acc#24" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:acc#24" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:acc#24" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:acc#24" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(11)} -pin  "FRAME:for:acc#24" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:acc#24.itm(0)} -pin  "FRAME:for:acc#24" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(1)} -pin  "FRAME:for:acc#24" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(2)} -pin  "FRAME:for:acc#24" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(3)} -pin  "FRAME:for:acc#24" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(4)} -pin  "FRAME:for:acc#24" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(5)} -pin  "FRAME:for:acc#24" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(6)} -pin  "FRAME:for:acc#24" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(7)} -pin  "FRAME:for:acc#24" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(8)} -pin  "FRAME:for:acc#24" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(9)} -pin  "FRAME:for:acc#24" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(10)} -pin  "FRAME:for:acc#24" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(11)} -pin  "FRAME:for:acc#24" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(12)} -pin  "FRAME:for:acc#24" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load inst "reg(FRAME:for:acc#24.itm#1)" "reg(13,1,1,-1,0)" "INTERFACE" -attr xrf 33881 -attr oid 1045 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:for:acc#24.itm#1)}
+load net {FRAME:for:acc#24.itm(0)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(1)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(2)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(3)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(4)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(5)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(6)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(7)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(8)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(9)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(10)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(11)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {FRAME:for:acc#24.itm(12)} -pin  "reg(FRAME:for:acc#24.itm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_13}
+load net {GND} -pin  "reg(FRAME:for:acc#24.itm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_13}
+load net {clk} -pin  "reg(FRAME:for:acc#24.itm#1)" {clk} -attr xrf 33882 -attr oid 1046 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:for:acc#24.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:for:acc#24.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:for:acc#24.itm#1(0)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(1)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(2)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(3)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(4)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(5)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(6)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(7)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(8)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(9)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(10)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(11)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(12)} -pin  "reg(FRAME:for:acc#24.itm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load inst "ACC1:acc#189" "add(3,1,2,1,4)" "INTERFACE" -attr xrf 33883 -attr oid 1047 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#189" {A(0)} -attr @path {/sobel/sobel:core/conc#649.itm}
+load net {acc.psp#1.sva(3)} -pin  "ACC1:acc#189" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#649.itm}
+load net {PWR} -pin  "ACC1:acc#189" {A(2)} -attr @path {/sobel/sobel:core/conc#649.itm}
+load net {acc.psp#1.sva(4)} -pin  "ACC1:acc#189" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#552.itm}
+load net {ACC1:acc#107.psp#1.sva(3)} -pin  "ACC1:acc#189" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#552.itm}
+load net {ACC1:acc#189.itm(0)} -pin  "ACC1:acc#189" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {ACC1:acc#189.itm(1)} -pin  "ACC1:acc#189" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {ACC1:acc#189.itm(2)} -pin  "ACC1:acc#189" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load net {ACC1:acc#189.itm(3)} -pin  "ACC1:acc#189" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#189.itm}
+load inst "ACC1:acc#198" "add(3,-1,2,1,3)" "INTERFACE" -attr xrf 33884 -attr oid 1048 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {ACC1:acc#189.itm(1)} -pin  "ACC1:acc#198" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#54.itm}
+load net {ACC1:acc#189.itm(2)} -pin  "ACC1:acc#198" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#54.itm}
+load net {ACC1:acc#189.itm(3)} -pin  "ACC1:acc#198" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#54.itm}
+load net {ACC1:acc#116.psp.sva(1)} -pin  "ACC1:acc#198" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp.sva)#2.itm}
+load net {ACC1:acc#116.psp.sva(2)} -pin  "ACC1:acc#198" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp.sva)#2.itm}
+load net {ACC1:acc#198.itm(0)} -pin  "ACC1:acc#198" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:acc#198.itm(1)} -pin  "ACC1:acc#198" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:acc#198.itm(2)} -pin  "ACC1:acc#198" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load inst "ACC1:acc#190" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 33885 -attr oid 1049 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#190" {A(0)} -attr @path {/sobel/sobel:core/conc#650.itm}
+load net {acc.psp#1.sva(1)} -pin  "ACC1:acc#190" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#650.itm}
+load net {acc.psp#1.sva(3)} -pin  "ACC1:acc#190" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#650.itm}
+load net {ACC1:acc#107.psp#1.sva(1)} -pin  "ACC1:acc#190" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#554.itm}
+load net {acc.psp#1.sva(2)} -pin  "ACC1:acc#190" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#554.itm}
+load net {ACC1:acc#107.psp#1.sva(3)} -pin  "ACC1:acc#190" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#554.itm}
+load net {ACC1:acc#190.itm(0)} -pin  "ACC1:acc#190" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load net {ACC1:acc#190.itm(1)} -pin  "ACC1:acc#190" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load net {ACC1:acc#190.itm(2)} -pin  "ACC1:acc#190" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load net {ACC1:acc#190.itm(3)} -pin  "ACC1:acc#190" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load net {ACC1:acc#190.itm(4)} -pin  "ACC1:acc#190" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#190.itm}
+load inst "ACC1:acc#203" "add(3,1,4,-1,4)" "INTERFACE" -attr xrf 33886 -attr oid 1050 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#198.itm(0)} -pin  "ACC1:acc#203" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:acc#198.itm(1)} -pin  "ACC1:acc#203" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:acc#198.itm(2)} -pin  "ACC1:acc#203" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#198.itm}
+load net {ACC1:acc#190.itm(1)} -pin  "ACC1:acc#203" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#55.itm}
+load net {ACC1:acc#190.itm(2)} -pin  "ACC1:acc#203" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#55.itm}
+load net {ACC1:acc#190.itm(3)} -pin  "ACC1:acc#203" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#55.itm}
+load net {ACC1:acc#190.itm(4)} -pin  "ACC1:acc#203" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#55.itm}
+load net {ACC1:acc#203.itm(0)} -pin  "ACC1:acc#203" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(1)} -pin  "ACC1:acc#203" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(2)} -pin  "ACC1:acc#203" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(3)} -pin  "ACC1:acc#203" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load inst "ACC1:acc#202" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 33887 -attr oid 1051 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#202" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#260.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#202" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#260.itm}
+load net {acc.psp#1.sva(4)} -pin  "ACC1:acc#202" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#260.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#202" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:conc#260.itm}
+load net {ACC1:acc#197.cse(0)} -pin  "ACC1:acc#202" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#197.cse(1)} -pin  "ACC1:acc#202" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#197.cse(2)} -pin  "ACC1:acc#202" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#202.itm(0)} -pin  "ACC1:acc#202" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(1)} -pin  "ACC1:acc#202" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(2)} -pin  "ACC1:acc#202" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(3)} -pin  "ACC1:acc#202" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(4)} -pin  "ACC1:acc#202" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load inst "ACC1:acc#206" "add(4,1,5,0,6)" "INTERFACE" -attr xrf 33888 -attr oid 1052 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#203.itm(0)} -pin  "ACC1:acc#206" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(1)} -pin  "ACC1:acc#206" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(2)} -pin  "ACC1:acc#206" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#203.itm(3)} -pin  "ACC1:acc#206" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#203.itm}
+load net {ACC1:acc#202.itm(0)} -pin  "ACC1:acc#206" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(1)} -pin  "ACC1:acc#206" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(2)} -pin  "ACC1:acc#206" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(3)} -pin  "ACC1:acc#206" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#202.itm(4)} -pin  "ACC1:acc#206" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#202.itm}
+load net {ACC1:acc#206.itm(0)} -pin  "ACC1:acc#206" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(1)} -pin  "ACC1:acc#206" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(2)} -pin  "ACC1:acc#206" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(3)} -pin  "ACC1:acc#206" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(4)} -pin  "ACC1:acc#206" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(5)} -pin  "ACC1:acc#206" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load inst "ACC1:acc#209" "add(6,1,7,0,8)" "INTERFACE" -attr xrf 33889 -attr oid 1053 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#206.itm(0)} -pin  "ACC1:acc#209" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(1)} -pin  "ACC1:acc#209" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(2)} -pin  "ACC1:acc#209" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(3)} -pin  "ACC1:acc#209" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(4)} -pin  "ACC1:acc#209" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {ACC1:acc#206.itm(5)} -pin  "ACC1:acc#209" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#206.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#209" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {GND} -pin  "ACC1:acc#209" {B(1)} -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#209" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {GND} -pin  "ACC1:acc#209" {B(3)} -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#209" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {GND} -pin  "ACC1:acc#209" {B(5)} -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#209" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#651.itm}
+load net {ACC1:acc#209.itm(0)} -pin  "ACC1:acc#209" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(1)} -pin  "ACC1:acc#209" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(2)} -pin  "ACC1:acc#209" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(3)} -pin  "ACC1:acc#209" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(4)} -pin  "ACC1:acc#209" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(5)} -pin  "ACC1:acc#209" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(6)} -pin  "ACC1:acc#209" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(7)} -pin  "ACC1:acc#209" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load inst "ACC1-3:not#28" "not(1)" "INTERFACE" -attr xrf 33890 -attr oid 1054 -attr @path {/sobel/sobel:core/ACC1-3:not#28} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#170.itm(2)} -pin  "ACC1-3:not#28" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#2.itm}
+load net {ACC1-3:not#28.itm} -pin  "ACC1-3:not#28" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#28.itm}
+load inst "ACC1-3:and#1" "and(3,1)" "INTERFACE" -attr xrf 33891 -attr oid 1055 -attr @path {/sobel/sobel:core/ACC1-3:and#1} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:and#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#38.itm}
+load net {ACC1-3:not#28.itm} -pin  "ACC1-3:and#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#28.itm}
+load net {ACC1:acc#170.itm(1)} -pin  "ACC1-3:and#1" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#1.itm}
+load net {ACC1-3:and#1.itm} -pin  "ACC1-3:and#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:and#1.itm}
+load inst "ACC1:acc#195" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33892 -attr oid 1056 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#195" {A(0)} -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#195" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#195" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#60.itm}
+load net {ACC1-3:and#1.itm} -pin  "ACC1:acc#195" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#751.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#195" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#751.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#195" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#751.itm}
+load net {ACC1:acc#195.itm(0)} -pin  "ACC1:acc#195" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load net {ACC1:acc#195.itm(1)} -pin  "ACC1:acc#195" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load net {ACC1:acc#195.itm(2)} -pin  "ACC1:acc#195" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load net {ACC1:acc#195.itm(3)} -pin  "ACC1:acc#195" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#195.itm}
+load inst "ACC1:acc#201" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33893 -attr oid 1057 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#197.cse(0)} -pin  "ACC1:acc#201" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#197.cse(1)} -pin  "ACC1:acc#201" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#197.cse(2)} -pin  "ACC1:acc#201" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#195.itm(1)} -pin  "ACC1:acc#201" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#60.itm}
+load net {ACC1:acc#195.itm(2)} -pin  "ACC1:acc#201" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#60.itm}
+load net {ACC1:acc#195.itm(3)} -pin  "ACC1:acc#201" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#60.itm}
+load net {ACC1:acc#201.itm(0)} -pin  "ACC1:acc#201" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(1)} -pin  "ACC1:acc#201" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(2)} -pin  "ACC1:acc#201" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(3)} -pin  "ACC1:acc#201" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load inst "ACC1:acc#205" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 33894 -attr oid 1058 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {acc.psp#1.sva(6)} -pin  "ACC1:acc#205" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#652.itm}
+load net {GND} -pin  "ACC1:acc#205" {A(1)} -attr @path {/sobel/sobel:core/conc#652.itm}
+load net {acc.psp#1.sva(6)} -pin  "ACC1:acc#205" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#652.itm}
+load net {GND} -pin  "ACC1:acc#205" {A(3)} -attr @path {/sobel/sobel:core/conc#652.itm}
+load net {acc.psp#1.sva(6)} -pin  "ACC1:acc#205" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#652.itm}
+load net {ACC1:acc#201.itm(0)} -pin  "ACC1:acc#205" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(1)} -pin  "ACC1:acc#205" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(2)} -pin  "ACC1:acc#205" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#201.itm(3)} -pin  "ACC1:acc#205" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#201.itm}
+load net {ACC1:acc#205.itm(0)} -pin  "ACC1:acc#205" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(1)} -pin  "ACC1:acc#205" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(2)} -pin  "ACC1:acc#205" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(3)} -pin  "ACC1:acc#205" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(4)} -pin  "ACC1:acc#205" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(5)} -pin  "ACC1:acc#205" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load inst "ACC1:acc#208" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 33895 -attr oid 1059 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#208" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#538.itm}
+load net {ACC1:acc#205.itm(0)} -pin  "ACC1:acc#208" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(1)} -pin  "ACC1:acc#208" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(2)} -pin  "ACC1:acc#208" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(3)} -pin  "ACC1:acc#208" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(4)} -pin  "ACC1:acc#208" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#205.itm(5)} -pin  "ACC1:acc#208" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#205.itm}
+load net {ACC1:acc#208.itm(0)} -pin  "ACC1:acc#208" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(1)} -pin  "ACC1:acc#208" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(2)} -pin  "ACC1:acc#208" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(3)} -pin  "ACC1:acc#208" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(4)} -pin  "ACC1:acc#208" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(5)} -pin  "ACC1:acc#208" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(6)} -pin  "ACC1:acc#208" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(7)} -pin  "ACC1:acc#208" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load inst "ACC1:acc#211" "add(8,1,8,0,10)" "INTERFACE" -attr xrf 33896 -attr oid 1060 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#209.itm(0)} -pin  "ACC1:acc#211" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(1)} -pin  "ACC1:acc#211" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(2)} -pin  "ACC1:acc#211" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(3)} -pin  "ACC1:acc#211" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(4)} -pin  "ACC1:acc#211" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(5)} -pin  "ACC1:acc#211" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(6)} -pin  "ACC1:acc#211" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#209.itm(7)} -pin  "ACC1:acc#211" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#209.itm}
+load net {ACC1:acc#208.itm(0)} -pin  "ACC1:acc#211" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(1)} -pin  "ACC1:acc#211" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(2)} -pin  "ACC1:acc#211" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(3)} -pin  "ACC1:acc#211" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(4)} -pin  "ACC1:acc#211" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(5)} -pin  "ACC1:acc#211" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(6)} -pin  "ACC1:acc#211" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#208.itm(7)} -pin  "ACC1:acc#211" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#208.itm}
+load net {ACC1:acc#211.itm(0)} -pin  "ACC1:acc#211" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(1)} -pin  "ACC1:acc#211" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(2)} -pin  "ACC1:acc#211" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(3)} -pin  "ACC1:acc#211" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(4)} -pin  "ACC1:acc#211" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(5)} -pin  "ACC1:acc#211" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(6)} -pin  "ACC1:acc#211" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(7)} -pin  "ACC1:acc#211" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(8)} -pin  "ACC1:acc#211" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(9)} -pin  "ACC1:acc#211" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load inst "ACC1:acc#213" "add(10,1,10,0,11)" "INTERFACE" -attr xrf 33897 -attr oid 1061 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11)"
+load net {ACC1:acc#211.itm(0)} -pin  "ACC1:acc#213" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(1)} -pin  "ACC1:acc#213" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(2)} -pin  "ACC1:acc#213" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(3)} -pin  "ACC1:acc#213" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(4)} -pin  "ACC1:acc#213" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(5)} -pin  "ACC1:acc#213" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(6)} -pin  "ACC1:acc#213" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(7)} -pin  "ACC1:acc#213" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(8)} -pin  "ACC1:acc#213" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {ACC1:acc#211.itm(9)} -pin  "ACC1:acc#213" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#211.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#213" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#213" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {GND} -pin  "ACC1:acc#213" {B(2)} -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#213" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {GND} -pin  "ACC1:acc#213" {B(4)} -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#213" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {GND} -pin  "ACC1:acc#213" {B(6)} -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#213" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {GND} -pin  "ACC1:acc#213" {B(8)} -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#213" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#655.itm}
+load net {ACC1:acc#213.itm(0)} -pin  "ACC1:acc#213" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(1)} -pin  "ACC1:acc#213" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(2)} -pin  "ACC1:acc#213" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(3)} -pin  "ACC1:acc#213" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(4)} -pin  "ACC1:acc#213" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(5)} -pin  "ACC1:acc#213" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(6)} -pin  "ACC1:acc#213" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(7)} -pin  "ACC1:acc#213" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(8)} -pin  "ACC1:acc#213" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(9)} -pin  "ACC1:acc#213" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(10)} -pin  "ACC1:acc#213" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load inst "ACC1:acc#215" "add(10,0,11,-1,11)" "INTERFACE" -attr xrf 33898 -attr oid 1062 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215} -attr area 12.237292 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,0,11)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#215" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(1)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(2)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(3)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(4)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(5)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(6)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(7)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {GND} -pin  "ACC1:acc#215" {A(8)} -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#215" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/conc#648.itm}
+load net {ACC1:acc#213.itm(0)} -pin  "ACC1:acc#215" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(1)} -pin  "ACC1:acc#215" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(2)} -pin  "ACC1:acc#215" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(3)} -pin  "ACC1:acc#215" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(4)} -pin  "ACC1:acc#215" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(5)} -pin  "ACC1:acc#215" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(6)} -pin  "ACC1:acc#215" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(7)} -pin  "ACC1:acc#215" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(8)} -pin  "ACC1:acc#215" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(9)} -pin  "ACC1:acc#215" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#213.itm(10)} -pin  "ACC1:acc#215" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#213.itm}
+load net {ACC1:acc#215.itm(0)} -pin  "ACC1:acc#215" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(1)} -pin  "ACC1:acc#215" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(2)} -pin  "ACC1:acc#215" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(3)} -pin  "ACC1:acc#215" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(4)} -pin  "ACC1:acc#215" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(5)} -pin  "ACC1:acc#215" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(6)} -pin  "ACC1:acc#215" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(7)} -pin  "ACC1:acc#215" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(8)} -pin  "ACC1:acc#215" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(9)} -pin  "ACC1:acc#215" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(10)} -pin  "ACC1:acc#215" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load inst "ACC1-1:not#166" "not(1)" "INTERFACE" -attr xrf 33899 -attr oid 1063 -attr @path {/sobel/sobel:core/ACC1-1:not#166} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:not#166" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#49.itm}
+load net {ACC1-1:not#166.itm} -pin  "ACC1-1:not#166" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#166.itm}
+load inst "ACC1-1:nand" "nand(2,1)" "INTERFACE" -attr xrf 33900 -attr oid 1064 -attr @path {/sobel/sobel:core/ACC1-1:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#141.itm(2)} -pin  "ACC1-1:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#16.sva)#2.itm}
+load net {ACC1-1:not#166.itm} -pin  "ACC1-1:nand" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#166.itm}
+load net {ACC1-1:nand.itm} -pin  "ACC1-1:nand" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:nand.itm}
+load inst "ACC1:acc#221" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33901 -attr oid 1065 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#221" {A(0)} -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#221" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#221" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#46.itm}
+load net {ACC1-1:nand.itm} -pin  "ACC1:acc#221" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#753.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#221" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#753.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#221" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#753.itm}
+load net {ACC1:acc#221.itm(0)} -pin  "ACC1:acc#221" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {ACC1:acc#221.itm(1)} -pin  "ACC1:acc#221" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {ACC1:acc#221.itm(2)} -pin  "ACC1:acc#221" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load net {ACC1:acc#221.itm(3)} -pin  "ACC1:acc#221" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#221.itm}
+load inst "ACC1-1:not#167" "not(1)" "INTERFACE" -attr xrf 33902 -attr oid 1066 -attr @path {/sobel/sobel:core/ACC1-1:not#167} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#140.itm(3)} -pin  "ACC1-1:not#167" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#14.sva)#4.itm}
+load net {ACC1-1:not#167.itm} -pin  "ACC1-1:not#167" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#167.itm}
+load inst "ACC1:acc#220" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33903 -attr oid 1067 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#220" {A(0)} -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#220" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#220" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#47.itm}
+load net {ACC1-1:not#167.itm} -pin  "ACC1:acc#220" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#755.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#220" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#755.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#220" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#755.itm}
+load net {ACC1:acc#220.itm(0)} -pin  "ACC1:acc#220" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {ACC1:acc#220.itm(1)} -pin  "ACC1:acc#220" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {ACC1:acc#220.itm(2)} -pin  "ACC1:acc#220" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load net {ACC1:acc#220.itm(3)} -pin  "ACC1:acc#220" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#220.itm}
+load inst "ACC1:acc#227" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33904 -attr oid 1068 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#221.itm(1)} -pin  "ACC1:acc#227" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1:acc#221.itm(2)} -pin  "ACC1:acc#227" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1:acc#221.itm(3)} -pin  "ACC1:acc#227" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#66.itm}
+load net {ACC1:acc#220.itm(1)} -pin  "ACC1:acc#227" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#220.itm(2)} -pin  "ACC1:acc#227" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#220.itm(3)} -pin  "ACC1:acc#227" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#65.itm}
+load net {ACC1:acc#227.itm(0)} -pin  "ACC1:acc#227" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(1)} -pin  "ACC1:acc#227" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(2)} -pin  "ACC1:acc#227" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(3)} -pin  "ACC1:acc#227" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load inst "ACC1:acc#219" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33905 -attr oid 1069 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#219" {A(0)} -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#219" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#219" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#48.itm}
+load net {ACC1:acc#140.itm(2)} -pin  "ACC1:acc#219" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#757.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#219" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#757.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#219" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#757.itm}
+load net {ACC1:acc#219.itm(0)} -pin  "ACC1:acc#219" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {ACC1:acc#219.itm(1)} -pin  "ACC1:acc#219" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {ACC1:acc#219.itm(2)} -pin  "ACC1:acc#219" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load net {ACC1:acc#219.itm(3)} -pin  "ACC1:acc#219" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#219.itm}
+load inst "ACC1:acc#218" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33906 -attr oid 1070 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#218" {A(0)} -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#218" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#218" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#49.itm}
+load net {ACC1:acc#107.psp#2.sva(2)} -pin  "ACC1:acc#218" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#759.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#218" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#759.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#218" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#759.itm}
+load net {ACC1:acc#218.itm(0)} -pin  "ACC1:acc#218" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {ACC1:acc#218.itm(1)} -pin  "ACC1:acc#218" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {ACC1:acc#218.itm(2)} -pin  "ACC1:acc#218" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load net {ACC1:acc#218.itm(3)} -pin  "ACC1:acc#218" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#218.itm}
+load inst "ACC1:acc#226" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33907 -attr oid 1071 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#219.itm(1)} -pin  "ACC1:acc#226" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#219.itm(2)} -pin  "ACC1:acc#226" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#219.itm(3)} -pin  "ACC1:acc#226" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#64.itm}
+load net {ACC1:acc#218.itm(1)} -pin  "ACC1:acc#226" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#63.itm}
+load net {ACC1:acc#218.itm(2)} -pin  "ACC1:acc#226" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#63.itm}
+load net {ACC1:acc#218.itm(3)} -pin  "ACC1:acc#226" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#63.itm}
+load net {ACC1:acc#226.itm(0)} -pin  "ACC1:acc#226" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(1)} -pin  "ACC1:acc#226" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(2)} -pin  "ACC1:acc#226" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(3)} -pin  "ACC1:acc#226" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load inst "ACC1:acc#231" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 33908 -attr oid 1072 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#227.itm(0)} -pin  "ACC1:acc#231" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(1)} -pin  "ACC1:acc#231" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(2)} -pin  "ACC1:acc#231" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#227.itm(3)} -pin  "ACC1:acc#231" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#227.itm}
+load net {ACC1:acc#226.itm(0)} -pin  "ACC1:acc#231" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(1)} -pin  "ACC1:acc#231" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(2)} -pin  "ACC1:acc#231" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#226.itm(3)} -pin  "ACC1:acc#231" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#226.itm}
+load net {ACC1:acc#231.itm(0)} -pin  "ACC1:acc#231" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(1)} -pin  "ACC1:acc#231" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(2)} -pin  "ACC1:acc#231" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(3)} -pin  "ACC1:acc#231" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(4)} -pin  "ACC1:acc#231" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load inst "ACC1:acc#234" "add(6,0,5,0,7)" "INTERFACE" -attr xrf 33909 -attr oid 1073 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#234" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#234" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {GND} -pin  "ACC1:acc#234" {A(2)} -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#234" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {GND} -pin  "ACC1:acc#234" {A(4)} -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#234" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#658.itm}
+load net {ACC1:acc#231.itm(0)} -pin  "ACC1:acc#234" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(1)} -pin  "ACC1:acc#234" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(2)} -pin  "ACC1:acc#234" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(3)} -pin  "ACC1:acc#234" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#231.itm(4)} -pin  "ACC1:acc#234" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#231.itm}
+load net {ACC1:acc#234.itm(0)} -pin  "ACC1:acc#234" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(1)} -pin  "ACC1:acc#234" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(2)} -pin  "ACC1:acc#234" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(3)} -pin  "ACC1:acc#234" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(4)} -pin  "ACC1:acc#234" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(5)} -pin  "ACC1:acc#234" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(6)} -pin  "ACC1:acc#234" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load inst "ACC1:acc#237" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 33910 -attr oid 1074 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#237" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {acc.psp#2.sva(5)} -pin  "ACC1:acc#237" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {GND} -pin  "ACC1:acc#237" {A(2)} -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#237" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {GND} -pin  "ACC1:acc#237" {A(4)} -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#237" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {GND} -pin  "ACC1:acc#237" {A(6)} -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#237" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#657.itm}
+load net {ACC1:acc#234.itm(0)} -pin  "ACC1:acc#237" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(1)} -pin  "ACC1:acc#237" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(2)} -pin  "ACC1:acc#237" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(3)} -pin  "ACC1:acc#237" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(4)} -pin  "ACC1:acc#237" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(5)} -pin  "ACC1:acc#237" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#234.itm(6)} -pin  "ACC1:acc#237" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#234.itm}
+load net {ACC1:acc#237.itm(0)} -pin  "ACC1:acc#237" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(1)} -pin  "ACC1:acc#237" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(2)} -pin  "ACC1:acc#237" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(3)} -pin  "ACC1:acc#237" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(4)} -pin  "ACC1:acc#237" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(5)} -pin  "ACC1:acc#237" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(6)} -pin  "ACC1:acc#237" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(7)} -pin  "ACC1:acc#237" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load inst "ACC1:acc#239" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 33911 -attr oid 1075 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239} -attr area 10.253676 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,0,10)"
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#239" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {GND} -pin  "ACC1:acc#239" {A(1)} -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#239" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {GND} -pin  "ACC1:acc#239" {A(3)} -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#239" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {GND} -pin  "ACC1:acc#239" {A(5)} -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#239" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {GND} -pin  "ACC1:acc#239" {A(7)} -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#239" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#656.itm}
+load net {ACC1:acc#237.itm(0)} -pin  "ACC1:acc#239" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(1)} -pin  "ACC1:acc#239" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(2)} -pin  "ACC1:acc#239" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(3)} -pin  "ACC1:acc#239" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(4)} -pin  "ACC1:acc#239" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(5)} -pin  "ACC1:acc#239" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(6)} -pin  "ACC1:acc#239" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#237.itm(7)} -pin  "ACC1:acc#239" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#237.itm}
+load net {ACC1:acc#239.itm(0)} -pin  "ACC1:acc#239" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(1)} -pin  "ACC1:acc#239" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(2)} -pin  "ACC1:acc#239" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(3)} -pin  "ACC1:acc#239" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(4)} -pin  "ACC1:acc#239" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(5)} -pin  "ACC1:acc#239" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(6)} -pin  "ACC1:acc#239" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(7)} -pin  "ACC1:acc#239" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(8)} -pin  "ACC1:acc#239" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(9)} -pin  "ACC1:acc#239" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load inst "ACC1:acc#216" "add(3,1,2,1,4)" "INTERFACE" -attr xrf 33912 -attr oid 1076 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#216" {A(0)} -attr @path {/sobel/sobel:core/conc#663.itm}
+load net {acc.psp#2.sva(3)} -pin  "ACC1:acc#216" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#663.itm}
+load net {PWR} -pin  "ACC1:acc#216" {A(2)} -attr @path {/sobel/sobel:core/conc#663.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#216" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#567.itm}
+load net {ACC1:acc#107.psp#2.sva(3)} -pin  "ACC1:acc#216" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#567.itm}
+load net {ACC1:acc#216.itm(0)} -pin  "ACC1:acc#216" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {ACC1:acc#216.itm(1)} -pin  "ACC1:acc#216" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {ACC1:acc#216.itm(2)} -pin  "ACC1:acc#216" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load net {ACC1:acc#216.itm(3)} -pin  "ACC1:acc#216" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#216.itm}
+load inst "ACC1:acc#225" "add(3,-1,2,1,3)" "INTERFACE" -attr xrf 33913 -attr oid 1077 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,1,2,1,4)"
+load net {ACC1:acc#216.itm(1)} -pin  "ACC1:acc#225" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#61.itm}
+load net {ACC1:acc#216.itm(2)} -pin  "ACC1:acc#225" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#61.itm}
+load net {ACC1:acc#216.itm(3)} -pin  "ACC1:acc#225" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#61.itm}
+load net {ACC1:acc#116.psp#1.sva(1)} -pin  "ACC1:acc#225" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp#1.sva)#2.itm}
+load net {ACC1:acc#116.psp#1.sva(2)} -pin  "ACC1:acc#225" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp#1.sva)#2.itm}
+load net {ACC1:acc#225.itm(0)} -pin  "ACC1:acc#225" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#225.itm(1)} -pin  "ACC1:acc#225" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#225.itm(2)} -pin  "ACC1:acc#225" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load inst "ACC1:acc#217" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 33914 -attr oid 1078 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#217" {A(0)} -attr @path {/sobel/sobel:core/conc#664.itm}
+load net {acc.psp#2.sva(1)} -pin  "ACC1:acc#217" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#664.itm}
+load net {acc.psp#2.sva(3)} -pin  "ACC1:acc#217" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#664.itm}
+load net {ACC1:acc#107.psp#2.sva(1)} -pin  "ACC1:acc#217" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#569.itm}
+load net {acc.psp#2.sva(2)} -pin  "ACC1:acc#217" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#569.itm}
+load net {ACC1:acc#107.psp#2.sva(3)} -pin  "ACC1:acc#217" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#569.itm}
+load net {ACC1:acc#217.itm(0)} -pin  "ACC1:acc#217" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1:acc#217.itm(1)} -pin  "ACC1:acc#217" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1:acc#217.itm(2)} -pin  "ACC1:acc#217" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1:acc#217.itm(3)} -pin  "ACC1:acc#217" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load net {ACC1:acc#217.itm(4)} -pin  "ACC1:acc#217" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#217.itm}
+load inst "ACC1:acc#230" "add(3,1,4,-1,4)" "INTERFACE" -attr xrf 33915 -attr oid 1079 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {ACC1:acc#225.itm(0)} -pin  "ACC1:acc#230" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#225.itm(1)} -pin  "ACC1:acc#230" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#225.itm(2)} -pin  "ACC1:acc#230" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#225.itm}
+load net {ACC1:acc#217.itm(1)} -pin  "ACC1:acc#230" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#62.itm}
+load net {ACC1:acc#217.itm(2)} -pin  "ACC1:acc#230" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#62.itm}
+load net {ACC1:acc#217.itm(3)} -pin  "ACC1:acc#230" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#62.itm}
+load net {ACC1:acc#217.itm(4)} -pin  "ACC1:acc#230" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#62.itm}
+load net {ACC1:acc#230.itm(0)} -pin  "ACC1:acc#230" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#230.itm(1)} -pin  "ACC1:acc#230" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#230.itm(2)} -pin  "ACC1:acc#230" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#230.itm(3)} -pin  "ACC1:acc#230" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load inst "ACC1:acc#229" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 33916 -attr oid 1080 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#229" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#260.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#229" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#260.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#229" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#260.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#229" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:conc#260.itm}
+load net {ACC1:acc#224.cse(0)} -pin  "ACC1:acc#229" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#224.cse(1)} -pin  "ACC1:acc#229" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#224.cse(2)} -pin  "ACC1:acc#229" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#229.itm(0)} -pin  "ACC1:acc#229" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(1)} -pin  "ACC1:acc#229" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(2)} -pin  "ACC1:acc#229" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(3)} -pin  "ACC1:acc#229" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(4)} -pin  "ACC1:acc#229" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load inst "ACC1:acc#233" "add(4,1,5,0,6)" "INTERFACE" -attr xrf 33917 -attr oid 1081 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {ACC1:acc#230.itm(0)} -pin  "ACC1:acc#233" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#230.itm(1)} -pin  "ACC1:acc#233" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#230.itm(2)} -pin  "ACC1:acc#233" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#230.itm(3)} -pin  "ACC1:acc#233" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#230.itm}
+load net {ACC1:acc#229.itm(0)} -pin  "ACC1:acc#233" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(1)} -pin  "ACC1:acc#233" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(2)} -pin  "ACC1:acc#233" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(3)} -pin  "ACC1:acc#233" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#229.itm(4)} -pin  "ACC1:acc#233" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#229.itm}
+load net {ACC1:acc#233.itm(0)} -pin  "ACC1:acc#233" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(1)} -pin  "ACC1:acc#233" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(2)} -pin  "ACC1:acc#233" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(3)} -pin  "ACC1:acc#233" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(4)} -pin  "ACC1:acc#233" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(5)} -pin  "ACC1:acc#233" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load inst "ACC1:acc#236" "add(6,1,7,0,8)" "INTERFACE" -attr xrf 33918 -attr oid 1082 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {ACC1:acc#233.itm(0)} -pin  "ACC1:acc#236" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(1)} -pin  "ACC1:acc#236" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(2)} -pin  "ACC1:acc#236" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(3)} -pin  "ACC1:acc#236" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(4)} -pin  "ACC1:acc#236" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {ACC1:acc#233.itm(5)} -pin  "ACC1:acc#236" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#233.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#236" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {GND} -pin  "ACC1:acc#236" {B(1)} -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#236" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {GND} -pin  "ACC1:acc#236" {B(3)} -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#236" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {GND} -pin  "ACC1:acc#236" {B(5)} -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#236" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#665.itm}
+load net {ACC1:acc#236.itm(0)} -pin  "ACC1:acc#236" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(1)} -pin  "ACC1:acc#236" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(2)} -pin  "ACC1:acc#236" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(3)} -pin  "ACC1:acc#236" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(4)} -pin  "ACC1:acc#236" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(5)} -pin  "ACC1:acc#236" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(6)} -pin  "ACC1:acc#236" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(7)} -pin  "ACC1:acc#236" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load inst "ACC1-1:not#28" "not(1)" "INTERFACE" -attr xrf 33919 -attr oid 1083 -attr @path {/sobel/sobel:core/ACC1-1:not#28} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#141.itm(2)} -pin  "ACC1-1:not#28" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#16.sva).itm}
+load net {ACC1-1:not#28.itm} -pin  "ACC1-1:not#28" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#28.itm}
+load inst "ACC1-1:and#1" "and(3,1)" "INTERFACE" -attr xrf 33920 -attr oid 1084 -attr @path {/sobel/sobel:core/ACC1-1:and#1} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:and#1" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#37.itm}
+load net {ACC1-1:not#28.itm} -pin  "ACC1-1:and#1" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#28.itm}
+load net {ACC1:acc#141.itm(1)} -pin  "ACC1-1:and#1" {A2(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#16.sva)#1.itm}
+load net {ACC1-1:and#1.itm} -pin  "ACC1-1:and#1" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:and#1.itm}
+load inst "ACC1:acc#222" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33921 -attr oid 1085 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#222" {A(0)} -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#222" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {acc.psp#2.sva(7)} -pin  "ACC1:acc#222" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#61.itm}
+load net {ACC1-1:and#1.itm} -pin  "ACC1:acc#222" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#761.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#222" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#761.itm}
+load net {acc.psp#2.sva(9)} -pin  "ACC1:acc#222" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#761.itm}
+load net {ACC1:acc#222.itm(0)} -pin  "ACC1:acc#222" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {ACC1:acc#222.itm(1)} -pin  "ACC1:acc#222" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {ACC1:acc#222.itm(2)} -pin  "ACC1:acc#222" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load net {ACC1:acc#222.itm(3)} -pin  "ACC1:acc#222" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#222.itm}
+load inst "ACC1:acc#228" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33922 -attr oid 1086 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#224.cse(0)} -pin  "ACC1:acc#228" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#224.cse(1)} -pin  "ACC1:acc#228" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#224.cse(2)} -pin  "ACC1:acc#228" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#222.itm(1)} -pin  "ACC1:acc#228" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#67.itm}
+load net {ACC1:acc#222.itm(2)} -pin  "ACC1:acc#228" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#67.itm}
+load net {ACC1:acc#222.itm(3)} -pin  "ACC1:acc#228" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#67.itm}
+load net {ACC1:acc#228.itm(0)} -pin  "ACC1:acc#228" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(1)} -pin  "ACC1:acc#228" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(2)} -pin  "ACC1:acc#228" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(3)} -pin  "ACC1:acc#228" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load inst "ACC1:acc#232" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 33923 -attr oid 1087 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#232" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#666.itm}
+load net {GND} -pin  "ACC1:acc#232" {A(1)} -attr @path {/sobel/sobel:core/conc#666.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#232" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#666.itm}
+load net {GND} -pin  "ACC1:acc#232" {A(3)} -attr @path {/sobel/sobel:core/conc#666.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#232" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#666.itm}
+load net {ACC1:acc#228.itm(0)} -pin  "ACC1:acc#232" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(1)} -pin  "ACC1:acc#232" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(2)} -pin  "ACC1:acc#232" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#228.itm(3)} -pin  "ACC1:acc#232" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#228.itm}
+load net {ACC1:acc#232.itm(0)} -pin  "ACC1:acc#232" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(1)} -pin  "ACC1:acc#232" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(2)} -pin  "ACC1:acc#232" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(3)} -pin  "ACC1:acc#232" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(4)} -pin  "ACC1:acc#232" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(5)} -pin  "ACC1:acc#232" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load inst "ACC1:acc#235" "add(7,0,6,0,8)" "INTERFACE" -attr xrf 33924 -attr oid 1088 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235} -attr area 8.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(7,0,7,1,9)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#235" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:exs#538.itm}
+load net {ACC1:acc#232.itm(0)} -pin  "ACC1:acc#235" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(1)} -pin  "ACC1:acc#235" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(2)} -pin  "ACC1:acc#235" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(3)} -pin  "ACC1:acc#235" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(4)} -pin  "ACC1:acc#235" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#232.itm(5)} -pin  "ACC1:acc#235" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#232.itm}
+load net {ACC1:acc#235.itm(0)} -pin  "ACC1:acc#235" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(1)} -pin  "ACC1:acc#235" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(2)} -pin  "ACC1:acc#235" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(3)} -pin  "ACC1:acc#235" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(4)} -pin  "ACC1:acc#235" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(5)} -pin  "ACC1:acc#235" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(6)} -pin  "ACC1:acc#235" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(7)} -pin  "ACC1:acc#235" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load inst "ACC1:acc#238" "add(8,1,8,0,10)" "INTERFACE" -attr xrf 33925 -attr oid 1089 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {ACC1:acc#236.itm(0)} -pin  "ACC1:acc#238" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(1)} -pin  "ACC1:acc#238" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(2)} -pin  "ACC1:acc#238" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(3)} -pin  "ACC1:acc#238" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(4)} -pin  "ACC1:acc#238" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(5)} -pin  "ACC1:acc#238" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(6)} -pin  "ACC1:acc#238" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#236.itm(7)} -pin  "ACC1:acc#238" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#236.itm}
+load net {ACC1:acc#235.itm(0)} -pin  "ACC1:acc#238" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(1)} -pin  "ACC1:acc#238" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(2)} -pin  "ACC1:acc#238" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(3)} -pin  "ACC1:acc#238" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(4)} -pin  "ACC1:acc#238" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(5)} -pin  "ACC1:acc#238" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(6)} -pin  "ACC1:acc#238" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#235.itm(7)} -pin  "ACC1:acc#238" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#235.itm}
+load net {ACC1:acc#238.itm(0)} -pin  "ACC1:acc#238" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(1)} -pin  "ACC1:acc#238" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(2)} -pin  "ACC1:acc#238" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(3)} -pin  "ACC1:acc#238" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(4)} -pin  "ACC1:acc#238" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(5)} -pin  "ACC1:acc#238" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(6)} -pin  "ACC1:acc#238" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(7)} -pin  "ACC1:acc#238" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(8)} -pin  "ACC1:acc#238" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(9)} -pin  "ACC1:acc#238" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load inst "ACC1:acc#241" "add(10,0,10,1,11)" "INTERFACE" -attr xrf 33926 -attr oid 1090 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,1,11)"
+load net {ACC1:acc#239.itm(0)} -pin  "ACC1:acc#241" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(1)} -pin  "ACC1:acc#241" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(2)} -pin  "ACC1:acc#241" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(3)} -pin  "ACC1:acc#241" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(4)} -pin  "ACC1:acc#241" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(5)} -pin  "ACC1:acc#241" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(6)} -pin  "ACC1:acc#241" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(7)} -pin  "ACC1:acc#241" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(8)} -pin  "ACC1:acc#241" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#239.itm(9)} -pin  "ACC1:acc#241" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#239.itm}
+load net {ACC1:acc#238.itm(0)} -pin  "ACC1:acc#241" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(1)} -pin  "ACC1:acc#241" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(2)} -pin  "ACC1:acc#241" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(3)} -pin  "ACC1:acc#241" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(4)} -pin  "ACC1:acc#241" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(5)} -pin  "ACC1:acc#241" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(6)} -pin  "ACC1:acc#241" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(7)} -pin  "ACC1:acc#241" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(8)} -pin  "ACC1:acc#241" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#238.itm(9)} -pin  "ACC1:acc#241" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#238.itm}
+load net {ACC1:acc#241.itm(0)} -pin  "ACC1:acc#241" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(1)} -pin  "ACC1:acc#241" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(2)} -pin  "ACC1:acc#241" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(3)} -pin  "ACC1:acc#241" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(4)} -pin  "ACC1:acc#241" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(5)} -pin  "ACC1:acc#241" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(6)} -pin  "ACC1:acc#241" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(7)} -pin  "ACC1:acc#241" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(8)} -pin  "ACC1:acc#241" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(9)} -pin  "ACC1:acc#241" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(10)} -pin  "ACC1:acc#241" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load inst "ACC1:acc#344" "add(1,0,2,0,3)" "INTERFACE" -attr xrf 33927 -attr oid 1091 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,3)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#344" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#13.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#344" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#857.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#344" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#857.itm}
+load net {ACC1:acc#344.itm(0)} -pin  "ACC1:acc#344" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:acc#344.itm(1)} -pin  "ACC1:acc#344" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load net {ACC1:acc#344.itm(2)} -pin  "ACC1:acc#344" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#344.itm}
+load inst "ACC1-1:acc#122" "add(11,-1,11,-1,11)" "INTERFACE" -attr xrf 33928 -attr oid 1092 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13)"
+load net {ACC1:acc#241.itm(0)} -pin  "ACC1-1:acc#122" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(1)} -pin  "ACC1-1:acc#122" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(2)} -pin  "ACC1-1:acc#122" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(3)} -pin  "ACC1-1:acc#122" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(4)} -pin  "ACC1-1:acc#122" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(5)} -pin  "ACC1-1:acc#122" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(6)} -pin  "ACC1-1:acc#122" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(7)} -pin  "ACC1-1:acc#122" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(8)} -pin  "ACC1-1:acc#122" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(9)} -pin  "ACC1-1:acc#122" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#241.itm(10)} -pin  "ACC1-1:acc#122" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#241.itm}
+load net {ACC1:acc#344.itm(0)} -pin  "ACC1-1:acc#122" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {ACC1:acc#344.itm(1)} -pin  "ACC1-1:acc#122" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {ACC1:acc#344.itm(2)} -pin  "ACC1-1:acc#122" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#122" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {GND} -pin  "ACC1-1:acc#122" {B(4)} -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#122" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {GND} -pin  "ACC1-1:acc#122" {B(6)} -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#122" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {GND} -pin  "ACC1-1:acc#122" {B(8)} -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {GND} -pin  "ACC1-1:acc#122" {B(9)} -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc#122" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/conc#669.itm}
+load net {ACC1-1:acc#122.itm(0)} -pin  "ACC1-1:acc#122" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(1)} -pin  "ACC1-1:acc#122" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(2)} -pin  "ACC1-1:acc#122" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(3)} -pin  "ACC1-1:acc#122" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(4)} -pin  "ACC1-1:acc#122" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(5)} -pin  "ACC1-1:acc#122" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(6)} -pin  "ACC1-1:acc#122" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(7)} -pin  "ACC1-1:acc#122" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(8)} -pin  "ACC1-1:acc#122" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(9)} -pin  "ACC1-1:acc#122" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(10)} -pin  "ACC1-1:acc#122" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load inst "ACC1-3:not#166" "not(1)" "INTERFACE" -attr xrf 33929 -attr oid 1093 -attr @path {/sobel/sobel:core/ACC1-3:not#166} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:not#166" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#57.itm}
+load net {ACC1-3:not#166.itm} -pin  "ACC1-3:not#166" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#166.itm}
+load inst "ACC1-3:nand" "nand(2,1)" "INTERFACE" -attr xrf 33930 -attr oid 1094 -attr @path {/sobel/sobel:core/ACC1-3:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {ACC1:acc#170.itm(2)} -pin  "ACC1-3:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva).itm}
+load net {ACC1-3:not#166.itm} -pin  "ACC1-3:nand" {A1(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#166.itm}
+load net {ACC1-3:nand.itm} -pin  "ACC1-3:nand" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:nand.itm}
+load inst "ACC1:acc#194" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33931 -attr oid 1095 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#194" {A(0)} -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#194" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#194" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#50.itm}
+load net {ACC1-3:nand.itm} -pin  "ACC1:acc#194" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#764.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#194" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#764.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#194" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#764.itm}
+load net {ACC1:acc#194.itm(0)} -pin  "ACC1:acc#194" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load net {ACC1:acc#194.itm(1)} -pin  "ACC1:acc#194" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load net {ACC1:acc#194.itm(2)} -pin  "ACC1:acc#194" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load net {ACC1:acc#194.itm(3)} -pin  "ACC1:acc#194" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#194.itm}
+load inst "ACC1-3:not#167" "not(1)" "INTERFACE" -attr xrf 33932 -attr oid 1096 -attr @path {/sobel/sobel:core/ACC1-3:not#167} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#169.itm(3)} -pin  "ACC1-3:not#167" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#4.itm}
+load net {ACC1-3:not#167.itm} -pin  "ACC1-3:not#167" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#167.itm}
+load inst "ACC1:acc#193" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33933 -attr oid 1097 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#193" {A(0)} -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#193" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#193" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#51.itm}
+load net {ACC1-3:not#167.itm} -pin  "ACC1:acc#193" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#766.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#193" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#766.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#193" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#766.itm}
+load net {ACC1:acc#193.itm(0)} -pin  "ACC1:acc#193" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load net {ACC1:acc#193.itm(1)} -pin  "ACC1:acc#193" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load net {ACC1:acc#193.itm(2)} -pin  "ACC1:acc#193" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load net {ACC1:acc#193.itm(3)} -pin  "ACC1:acc#193" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#193.itm}
+load inst "ACC1:acc#200" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33934 -attr oid 1098 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#194.itm(1)} -pin  "ACC1:acc#200" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#59.itm}
+load net {ACC1:acc#194.itm(2)} -pin  "ACC1:acc#200" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#59.itm}
+load net {ACC1:acc#194.itm(3)} -pin  "ACC1:acc#200" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#59.itm}
+load net {ACC1:acc#193.itm(1)} -pin  "ACC1:acc#200" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:acc#193.itm(2)} -pin  "ACC1:acc#200" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:acc#193.itm(3)} -pin  "ACC1:acc#200" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#58.itm}
+load net {ACC1:acc#200.itm(0)} -pin  "ACC1:acc#200" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(1)} -pin  "ACC1:acc#200" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(2)} -pin  "ACC1:acc#200" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(3)} -pin  "ACC1:acc#200" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load inst "ACC1:acc#192" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33935 -attr oid 1099 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#192" {A(0)} -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#192" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#192" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#52.itm}
+load net {ACC1:acc#169.itm(2)} -pin  "ACC1:acc#192" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#768.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#192" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#768.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#192" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#768.itm}
+load net {ACC1:acc#192.itm(0)} -pin  "ACC1:acc#192" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(1)} -pin  "ACC1:acc#192" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(2)} -pin  "ACC1:acc#192" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load net {ACC1:acc#192.itm(3)} -pin  "ACC1:acc#192" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#192.itm}
+load inst "ACC1:acc#191" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33936 -attr oid 1100 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#191" {A(0)} -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#191" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#191" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#53.itm}
+load net {ACC1:acc#107.psp#1.sva(2)} -pin  "ACC1:acc#191" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#770.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#191" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#770.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#191" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#770.itm}
+load net {ACC1:acc#191.itm(0)} -pin  "ACC1:acc#191" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load net {ACC1:acc#191.itm(1)} -pin  "ACC1:acc#191" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load net {ACC1:acc#191.itm(2)} -pin  "ACC1:acc#191" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load net {ACC1:acc#191.itm(3)} -pin  "ACC1:acc#191" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#191.itm}
+load inst "ACC1:acc#199" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 33937 -attr oid 1101 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc#192.itm(1)} -pin  "ACC1:acc#199" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#57.itm}
+load net {ACC1:acc#192.itm(2)} -pin  "ACC1:acc#199" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#57.itm}
+load net {ACC1:acc#192.itm(3)} -pin  "ACC1:acc#199" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#57.itm}
+load net {ACC1:acc#191.itm(1)} -pin  "ACC1:acc#199" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#56.itm}
+load net {ACC1:acc#191.itm(2)} -pin  "ACC1:acc#199" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#56.itm}
+load net {ACC1:acc#191.itm(3)} -pin  "ACC1:acc#199" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#56.itm}
+load net {ACC1:acc#199.itm(0)} -pin  "ACC1:acc#199" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(1)} -pin  "ACC1:acc#199" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(2)} -pin  "ACC1:acc#199" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(3)} -pin  "ACC1:acc#199" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load inst "ACC1:acc#204" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 33938 -attr oid 1102 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {ACC1:acc#200.itm(0)} -pin  "ACC1:acc#204" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(1)} -pin  "ACC1:acc#204" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(2)} -pin  "ACC1:acc#204" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#200.itm(3)} -pin  "ACC1:acc#204" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#200.itm}
+load net {ACC1:acc#199.itm(0)} -pin  "ACC1:acc#204" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(1)} -pin  "ACC1:acc#204" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(2)} -pin  "ACC1:acc#204" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#199.itm(3)} -pin  "ACC1:acc#204" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#199.itm}
+load net {ACC1:acc#204.itm(0)} -pin  "ACC1:acc#204" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(1)} -pin  "ACC1:acc#204" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(2)} -pin  "ACC1:acc#204" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(3)} -pin  "ACC1:acc#204" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(4)} -pin  "ACC1:acc#204" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load inst "ACC1:acc#207" "add(6,0,5,0,7)" "INTERFACE" -attr xrf 33939 -attr oid 1103 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#207" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#207" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {GND} -pin  "ACC1:acc#207" {A(2)} -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {acc.psp#1.sva(5)} -pin  "ACC1:acc#207" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {GND} -pin  "ACC1:acc#207" {A(4)} -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {acc.psp#1.sva(7)} -pin  "ACC1:acc#207" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#672.itm}
+load net {ACC1:acc#204.itm(0)} -pin  "ACC1:acc#207" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(1)} -pin  "ACC1:acc#207" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(2)} -pin  "ACC1:acc#207" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(3)} -pin  "ACC1:acc#207" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#204.itm(4)} -pin  "ACC1:acc#207" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#204.itm}
+load net {ACC1:acc#207.itm(0)} -pin  "ACC1:acc#207" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(1)} -pin  "ACC1:acc#207" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(2)} -pin  "ACC1:acc#207" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(3)} -pin  "ACC1:acc#207" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(4)} -pin  "ACC1:acc#207" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(5)} -pin  "ACC1:acc#207" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(6)} -pin  "ACC1:acc#207" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load inst "ACC1:acc#210" "add(8,-1,7,0,8)" "INTERFACE" -attr xrf 33940 -attr oid 1104 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {acc.psp#1.sva(5)} -pin  "ACC1:acc#210" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {acc.psp#1.sva(5)} -pin  "ACC1:acc#210" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {GND} -pin  "ACC1:acc#210" {A(2)} -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#210" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {GND} -pin  "ACC1:acc#210" {A(4)} -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#210" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {GND} -pin  "ACC1:acc#210" {A(6)} -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {acc.psp#1.sva(9)} -pin  "ACC1:acc#210" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/conc#671.itm}
+load net {ACC1:acc#207.itm(0)} -pin  "ACC1:acc#210" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(1)} -pin  "ACC1:acc#210" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(2)} -pin  "ACC1:acc#210" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(3)} -pin  "ACC1:acc#210" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(4)} -pin  "ACC1:acc#210" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(5)} -pin  "ACC1:acc#210" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#207.itm(6)} -pin  "ACC1:acc#210" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#207.itm}
+load net {ACC1:acc#210.itm(0)} -pin  "ACC1:acc#210" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(1)} -pin  "ACC1:acc#210" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(2)} -pin  "ACC1:acc#210" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(3)} -pin  "ACC1:acc#210" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(4)} -pin  "ACC1:acc#210" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(5)} -pin  "ACC1:acc#210" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(6)} -pin  "ACC1:acc#210" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(7)} -pin  "ACC1:acc#210" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load inst "ACC1:acc#212" "add(9,0,8,0,10)" "INTERFACE" -attr xrf 33941 -attr oid 1105 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212} -attr area 10.253676 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,0,10)"
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#212" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {GND} -pin  "ACC1:acc#212" {A(1)} -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#212" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {GND} -pin  "ACC1:acc#212" {A(3)} -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#212" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {GND} -pin  "ACC1:acc#212" {A(5)} -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#212" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {GND} -pin  "ACC1:acc#212" {A(7)} -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#212" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/conc#670.itm}
+load net {ACC1:acc#210.itm(0)} -pin  "ACC1:acc#212" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(1)} -pin  "ACC1:acc#212" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(2)} -pin  "ACC1:acc#212" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(3)} -pin  "ACC1:acc#212" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(4)} -pin  "ACC1:acc#212" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(5)} -pin  "ACC1:acc#212" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(6)} -pin  "ACC1:acc#212" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#210.itm(7)} -pin  "ACC1:acc#212" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#210.itm}
+load net {ACC1:acc#212.itm(0)} -pin  "ACC1:acc#212" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(1)} -pin  "ACC1:acc#212" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(2)} -pin  "ACC1:acc#212" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(3)} -pin  "ACC1:acc#212" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(4)} -pin  "ACC1:acc#212" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(5)} -pin  "ACC1:acc#212" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(6)} -pin  "ACC1:acc#212" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(7)} -pin  "ACC1:acc#212" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(8)} -pin  "ACC1:acc#212" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(9)} -pin  "ACC1:acc#212" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load inst "ACC1:acc#214" "add(11,1,10,0,12)" "INTERFACE" -attr xrf 33942 -attr oid 1106 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13)"
+load net {ACC1-1:acc#122.itm(0)} -pin  "ACC1:acc#214" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(1)} -pin  "ACC1:acc#214" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(2)} -pin  "ACC1:acc#214" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(3)} -pin  "ACC1:acc#214" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(4)} -pin  "ACC1:acc#214" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(5)} -pin  "ACC1:acc#214" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(6)} -pin  "ACC1:acc#214" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(7)} -pin  "ACC1:acc#214" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(8)} -pin  "ACC1:acc#214" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(9)} -pin  "ACC1:acc#214" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1-1:acc#122.itm(10)} -pin  "ACC1:acc#214" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#122.itm}
+load net {ACC1:acc#212.itm(0)} -pin  "ACC1:acc#214" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(1)} -pin  "ACC1:acc#214" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(2)} -pin  "ACC1:acc#214" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(3)} -pin  "ACC1:acc#214" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(4)} -pin  "ACC1:acc#214" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(5)} -pin  "ACC1:acc#214" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(6)} -pin  "ACC1:acc#214" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(7)} -pin  "ACC1:acc#214" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(8)} -pin  "ACC1:acc#214" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#212.itm(9)} -pin  "ACC1:acc#214" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#212.itm}
+load net {ACC1:acc#214.itm(0)} -pin  "ACC1:acc#214" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(1)} -pin  "ACC1:acc#214" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(2)} -pin  "ACC1:acc#214" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(3)} -pin  "ACC1:acc#214" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(4)} -pin  "ACC1:acc#214" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(5)} -pin  "ACC1:acc#214" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(6)} -pin  "ACC1:acc#214" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(7)} -pin  "ACC1:acc#214" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(8)} -pin  "ACC1:acc#214" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(9)} -pin  "ACC1:acc#214" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(10)} -pin  "ACC1:acc#214" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(11)} -pin  "ACC1:acc#214" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load inst "ACC1-3:acc#122" "add(11,1,12,-1,12)" "INTERFACE" -attr xrf 33943 -attr oid 1107 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {ACC1:acc#215.itm(0)} -pin  "ACC1-3:acc#122" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(1)} -pin  "ACC1-3:acc#122" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(2)} -pin  "ACC1-3:acc#122" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(3)} -pin  "ACC1-3:acc#122" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(4)} -pin  "ACC1-3:acc#122" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(5)} -pin  "ACC1-3:acc#122" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(6)} -pin  "ACC1-3:acc#122" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(7)} -pin  "ACC1-3:acc#122" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(8)} -pin  "ACC1-3:acc#122" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(9)} -pin  "ACC1-3:acc#122" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#215.itm(10)} -pin  "ACC1-3:acc#122" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#215.itm}
+load net {ACC1:acc#214.itm(0)} -pin  "ACC1-3:acc#122" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(1)} -pin  "ACC1-3:acc#122" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(2)} -pin  "ACC1-3:acc#122" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(3)} -pin  "ACC1-3:acc#122" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(4)} -pin  "ACC1-3:acc#122" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(5)} -pin  "ACC1-3:acc#122" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(6)} -pin  "ACC1-3:acc#122" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(7)} -pin  "ACC1-3:acc#122" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(8)} -pin  "ACC1-3:acc#122" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(9)} -pin  "ACC1-3:acc#122" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(10)} -pin  "ACC1-3:acc#122" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1:acc#214.itm(11)} -pin  "ACC1-3:acc#122" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#214.itm}
+load net {ACC1-3:acc#122.itm(0)} -pin  "ACC1-3:acc#122" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(1)} -pin  "ACC1-3:acc#122" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(2)} -pin  "ACC1-3:acc#122" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(3)} -pin  "ACC1-3:acc#122" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(4)} -pin  "ACC1-3:acc#122" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(5)} -pin  "ACC1-3:acc#122" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(6)} -pin  "ACC1-3:acc#122" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(7)} -pin  "ACC1-3:acc#122" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(8)} -pin  "ACC1-3:acc#122" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(9)} -pin  "ACC1-3:acc#122" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(10)} -pin  "ACC1-3:acc#122" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(11)} -pin  "ACC1-3:acc#122" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load inst "reg(FRAME:for:slc(in(0).sva).itm#1)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 33944 -attr oid 1108 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:for:slc(in(0).sva).itm#1)}
+load net {ACC1-3:acc#122.itm(0)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(1)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(2)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(3)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(4)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(5)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(6)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(7)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(8)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(9)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(10)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {ACC1-3:acc#122.itm(11)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#122.itm}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {clk} -attr xrf 33945 -attr oid 1109 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:for:slc(in(0).sva).itm#1(0)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(1)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(2)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(3)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(4)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(5)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(6)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(7)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(8)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(9)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(10)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -pin  "reg(FRAME:for:slc(in(0).sva).itm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:slc(in(0).sva).itm#1}
+load inst "reg(i#6.sva#1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 33946 -attr oid 1110 -attr vt d -attr @path {/sobel/sobel:core/reg(i#6.sva#1)}
+load net {i#6.sva#2(0)} -pin  "reg(i#6.sva#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "reg(i#6.sva#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {GND} -pin  "reg(i#6.sva#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(i#6.sva#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(i#6.sva#1)" {clk} -attr xrf 33947 -attr oid 1111 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(i#6.sva#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(i#6.sva#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {i#6.sva#1(0)} -pin  "reg(i#6.sva#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "reg(i#6.sva#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load inst "FRAME:for:not" "not(1)" "INTERFACE" -attr xrf 33948 -attr oid 1112 -attr @path {/sobel/sobel:core/FRAME:for:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#1.itm}
+load net {FRAME:for:not.itm} -pin  "FRAME:for:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load inst "FRAME:and" "and(2,1)" "INTERFACE" -attr xrf 33949 -attr oid 1113 -attr @path {/sobel/sobel:core/FRAME:and} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {FRAME:for:not.itm} -pin  "FRAME:and" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "FRAME:and" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load net {FRAME:and.itm} -pin  "FRAME:and" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load inst "reg(exit:FRAME#1.sva)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 33950 -attr oid 1114 -attr @path {/sobel/sobel:core/reg(exit:FRAME#1.sva)}
+load net {FRAME:and.itm} -pin  "reg(exit:FRAME#1.sva)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load net {PWR} -pin  "reg(exit:FRAME#1.sva)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_10#10_Not}
+load net {clk} -pin  "reg(exit:FRAME#1.sva)" {clk} -attr xrf 33951 -attr oid 1115 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME#1.sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME#1.sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME#1.sva} -pin  "reg(exit:FRAME#1.sva)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load inst "reg(main.stage_0#2)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 33952 -attr oid 1116 -attr @path {/sobel/sobel:core/reg(main.stage_0#2)}
+load net {PWR} -pin  "reg(main.stage_0#2)" {D(0)} -attr @path {/sobel/sobel:core/Cn1_1#2}
+load net {GND} -pin  "reg(main.stage_0#2)" {DRa(0)} -attr @path {/sobel/sobel:core/Cn2_2#4}
+load net {clk} -pin  "reg(main.stage_0#2)" {clk} -attr xrf 33953 -attr oid 1117 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(main.stage_0#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(main.stage_0#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {main.stage_0#2} -pin  "reg(main.stage_0#2)" {Z(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load inst "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" "reg(3,1,1,-1,0)" "INTERFACE" -attr xrf 33954 -attr oid 1118 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(0)} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(1)} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(2)} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load net {GND} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {GND} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {GND} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {clk} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {clk} -attr xrf 33955 -attr oid 1119 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(0)} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(1)} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(2)} -pin  "reg(ACC1:acc#110.psp#1.lpi#1.dfm.sg1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load inst "reg(ACC1:acc#125.psp.lpi#1.dfm)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 33956 -attr oid 1120 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#125.psp.lpi#1.dfm)}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(0)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(1)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(2)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(3)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(5)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(7)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(9)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {clk} -attr xrf 33957 -attr oid 1121 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#125.psp.lpi#1.dfm(0)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(1)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(2)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(3)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(4)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(5)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(6)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(7)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(8)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(9)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(10)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(11)} -pin  "reg(ACC1:acc#125.psp.lpi#1.dfm)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load inst "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 33958 -attr oid 1122 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(0)} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(1)} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0}
+load net {GND} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {clk} -attr xrf 33959 -attr oid 1123 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1(0)} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1(1)} -pin  "reg(ACC1:acc#118.psp.lpi#1.dfm.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1}
+load inst "reg(regs.regs(2).lpi#1.dfm.sg2)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 33960 -attr oid 1124 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(2).lpi#1.dfm.sg2)}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(0)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(1)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(2)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(3)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(4)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(5)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(6)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(7)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(8)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(9)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(10)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(11)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(12)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(13)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(14)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(15)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(16)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(17)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(18)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(19)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(20)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(21)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(22)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(23)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(24)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(25)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(26)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(27)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(28)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(29)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {clk} -attr xrf 33961 -attr oid 1125 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(2).lpi#1.dfm.sg2(0)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(1)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(2)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(3)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(4)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(5)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(6)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(7)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(8)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(9)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(10)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(11)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(12)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(13)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(14)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(15)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(16)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(17)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(18)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(19)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(20)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(21)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(22)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(23)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(24)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(25)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(26)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(27)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(28)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(29)} -pin  "reg(regs.regs(2).lpi#1.dfm.sg2)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load inst "reg(regs.regs(2).lpi#1.dfm#1)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 33962 -attr oid 1126 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(2).lpi#1.dfm#1)}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(0)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(1)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(2)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(3)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(4)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(5)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(6)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(7)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(8)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(9)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(10)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(11)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(12)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(13)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(14)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(15)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(16)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(17)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(18)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(19)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(20)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(21)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(22)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(23)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(24)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(25)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(26)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(27)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(28)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(29)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {clk} -attr xrf 33963 -attr oid 1127 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(2).lpi#1.dfm#1(0)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(1)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(2)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(3)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(4)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(5)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(6)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(7)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(8)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(9)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(10)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(11)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(12)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(13)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(14)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(15)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(16)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(17)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(18)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(19)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(20)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(21)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(22)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(23)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(24)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(25)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(26)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(27)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(28)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(29)} -pin  "reg(regs.regs(2).lpi#1.dfm#1)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load inst "reg(acc.imod#7.lpi#1.dfm)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 33964 -attr oid 1128 -attr vt d -attr @path {/sobel/sobel:core/reg(acc.imod#7.lpi#1.dfm)}
+load net {acc.imod#7.lpi#1.dfm:mx0(0)} -pin  "reg(acc.imod#7.lpi#1.dfm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm:mx0}
+load net {acc.imod#7.lpi#1.dfm:mx0(1)} -pin  "reg(acc.imod#7.lpi#1.dfm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm:mx0}
+load net {GND} -pin  "reg(acc.imod#7.lpi#1.dfm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(acc.imod#7.lpi#1.dfm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(acc.imod#7.lpi#1.dfm)" {clk} -attr xrf 33965 -attr oid 1129 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(acc.imod#7.lpi#1.dfm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(acc.imod#7.lpi#1.dfm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {acc.imod#7.lpi#1.dfm(0)} -pin  "reg(acc.imod#7.lpi#1.dfm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm}
+load net {acc.imod#7.lpi#1.dfm(1)} -pin  "reg(acc.imod#7.lpi#1.dfm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm}
+load inst "reg(acc.imod#6.lpi#1.dfm.sg1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 33966 -attr oid 1130 -attr vt d -attr @path {/sobel/sobel:core/reg(acc.imod#6.lpi#1.dfm.sg1)}
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(0)} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1:mx0}
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(1)} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1:mx0}
+load net {GND} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {clk} -attr xrf 33967 -attr oid 1131 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {acc.imod#6.lpi#1.dfm.sg1(0)} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1}
+load net {acc.imod#6.lpi#1.dfm.sg1(1)} -pin  "reg(acc.imod#6.lpi#1.dfm.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1}
+load inst "reg(regs.regs(1).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 33968 -attr oid 1132 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(1).sva)}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "reg(regs.regs(1).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "reg(regs.regs(1).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "reg(regs.regs(1).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "reg(regs.regs(1).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "reg(regs.regs(1).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "reg(regs.regs(1).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "reg(regs.regs(1).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "reg(regs.regs(1).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "reg(regs.regs(1).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "reg(regs.regs(1).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "reg(regs.regs(1).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "reg(regs.regs(1).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "reg(regs.regs(1).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "reg(regs.regs(1).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "reg(regs.regs(1).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "reg(regs.regs(1).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "reg(regs.regs(1).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "reg(regs.regs(1).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "reg(regs.regs(1).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "reg(regs.regs(1).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "reg(regs.regs(1).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "reg(regs.regs(1).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "reg(regs.regs(1).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "reg(regs.regs(1).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "reg(regs.regs(1).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "reg(regs.regs(1).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "reg(regs.regs(1).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "reg(regs.regs(1).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "reg(regs.regs(1).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "reg(regs.regs(1).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "reg(regs.regs(1).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "reg(regs.regs(1).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "reg(regs.regs(1).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "reg(regs.regs(1).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "reg(regs.regs(1).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "reg(regs.regs(1).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "reg(regs.regs(1).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "reg(regs.regs(1).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "reg(regs.regs(1).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "reg(regs.regs(1).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "reg(regs.regs(1).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "reg(regs.regs(1).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "reg(regs.regs(1).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "reg(regs.regs(1).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "reg(regs.regs(1).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "reg(regs.regs(1).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "reg(regs.regs(1).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "reg(regs.regs(1).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "reg(regs.regs(1).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "reg(regs.regs(1).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "reg(regs.regs(1).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "reg(regs.regs(1).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "reg(regs.regs(1).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "reg(regs.regs(1).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "reg(regs.regs(1).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "reg(regs.regs(1).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "reg(regs.regs(1).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "reg(regs.regs(1).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "reg(regs.regs(1).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "reg(regs.regs(1).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "reg(regs.regs(1).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "reg(regs.regs(1).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "reg(regs.regs(1).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "reg(regs.regs(1).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "reg(regs.regs(1).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "reg(regs.regs(1).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "reg(regs.regs(1).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "reg(regs.regs(1).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "reg(regs.regs(1).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "reg(regs.regs(1).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "reg(regs.regs(1).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "reg(regs.regs(1).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "reg(regs.regs(1).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "reg(regs.regs(1).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "reg(regs.regs(1).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "reg(regs.regs(1).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "reg(regs.regs(1).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "reg(regs.regs(1).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "reg(regs.regs(1).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "reg(regs.regs(1).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "reg(regs.regs(1).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "reg(regs.regs(1).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "reg(regs.regs(1).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "reg(regs.regs(1).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "reg(regs.regs(1).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "reg(regs.regs(1).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "reg(regs.regs(1).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "reg(regs.regs(1).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "reg(regs.regs(1).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "reg(regs.regs(1).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {clk} -pin  "reg(regs.regs(1).sva)" {clk} -attr xrf 33969 -attr oid 1133 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(1).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(1).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(1).sva(0)} -pin  "reg(regs.regs(1).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "reg(regs.regs(1).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "reg(regs.regs(1).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "reg(regs.regs(1).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "reg(regs.regs(1).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "reg(regs.regs(1).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "reg(regs.regs(1).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "reg(regs.regs(1).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "reg(regs.regs(1).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "reg(regs.regs(1).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "reg(regs.regs(1).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "reg(regs.regs(1).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "reg(regs.regs(1).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "reg(regs.regs(1).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "reg(regs.regs(1).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "reg(regs.regs(1).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "reg(regs.regs(1).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "reg(regs.regs(1).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "reg(regs.regs(1).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "reg(regs.regs(1).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "reg(regs.regs(1).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "reg(regs.regs(1).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "reg(regs.regs(1).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "reg(regs.regs(1).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "reg(regs.regs(1).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "reg(regs.regs(1).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "reg(regs.regs(1).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "reg(regs.regs(1).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "reg(regs.regs(1).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "reg(regs.regs(1).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "reg(regs.regs(1).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "reg(regs.regs(1).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "reg(regs.regs(1).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "reg(regs.regs(1).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "reg(regs.regs(1).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "reg(regs.regs(1).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "reg(regs.regs(1).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "reg(regs.regs(1).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "reg(regs.regs(1).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "reg(regs.regs(1).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "reg(regs.regs(1).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "reg(regs.regs(1).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "reg(regs.regs(1).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "reg(regs.regs(1).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "reg(regs.regs(1).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "reg(regs.regs(1).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "reg(regs.regs(1).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "reg(regs.regs(1).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "reg(regs.regs(1).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "reg(regs.regs(1).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "reg(regs.regs(1).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "reg(regs.regs(1).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "reg(regs.regs(1).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "reg(regs.regs(1).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "reg(regs.regs(1).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "reg(regs.regs(1).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "reg(regs.regs(1).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "reg(regs.regs(1).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "reg(regs.regs(1).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "reg(regs.regs(1).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "reg(regs.regs(1).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "reg(regs.regs(1).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "reg(regs.regs(1).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "reg(regs.regs(1).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "reg(regs.regs(1).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "reg(regs.regs(1).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "reg(regs.regs(1).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "reg(regs.regs(1).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "reg(regs.regs(1).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "reg(regs.regs(1).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "reg(regs.regs(1).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "reg(regs.regs(1).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "reg(regs.regs(1).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "reg(regs.regs(1).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "reg(regs.regs(1).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "reg(regs.regs(1).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "reg(regs.regs(1).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "reg(regs.regs(1).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "reg(regs.regs(1).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "reg(regs.regs(1).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "reg(regs.regs(1).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "reg(regs.regs(1).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "reg(regs.regs(1).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "reg(regs.regs(1).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "reg(regs.regs(1).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "reg(regs.regs(1).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "reg(regs.regs(1).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "reg(regs.regs(1).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "reg(regs.regs(1).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "reg(regs.regs(1).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load inst "reg(regs.regs(0).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 33970 -attr oid 1134 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva)}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "reg(regs.regs(0).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "reg(regs.regs(0).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "reg(regs.regs(0).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "reg(regs.regs(0).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "reg(regs.regs(0).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "reg(regs.regs(0).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "reg(regs.regs(0).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "reg(regs.regs(0).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "reg(regs.regs(0).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "reg(regs.regs(0).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "reg(regs.regs(0).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "reg(regs.regs(0).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "reg(regs.regs(0).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "reg(regs.regs(0).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "reg(regs.regs(0).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "reg(regs.regs(0).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "reg(regs.regs(0).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "reg(regs.regs(0).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "reg(regs.regs(0).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "reg(regs.regs(0).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "reg(regs.regs(0).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "reg(regs.regs(0).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "reg(regs.regs(0).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "reg(regs.regs(0).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "reg(regs.regs(0).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "reg(regs.regs(0).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "reg(regs.regs(0).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "reg(regs.regs(0).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "reg(regs.regs(0).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "reg(regs.regs(0).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "reg(regs.regs(0).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "reg(regs.regs(0).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "reg(regs.regs(0).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "reg(regs.regs(0).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "reg(regs.regs(0).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "reg(regs.regs(0).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "reg(regs.regs(0).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "reg(regs.regs(0).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "reg(regs.regs(0).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "reg(regs.regs(0).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "reg(regs.regs(0).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "reg(regs.regs(0).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "reg(regs.regs(0).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "reg(regs.regs(0).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "reg(regs.regs(0).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "reg(regs.regs(0).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "reg(regs.regs(0).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "reg(regs.regs(0).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "reg(regs.regs(0).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "reg(regs.regs(0).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "reg(regs.regs(0).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "reg(regs.regs(0).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "reg(regs.regs(0).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "reg(regs.regs(0).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "reg(regs.regs(0).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "reg(regs.regs(0).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "reg(regs.regs(0).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "reg(regs.regs(0).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "reg(regs.regs(0).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "reg(regs.regs(0).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "reg(regs.regs(0).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "reg(regs.regs(0).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "reg(regs.regs(0).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "reg(regs.regs(0).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "reg(regs.regs(0).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "reg(regs.regs(0).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "reg(regs.regs(0).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "reg(regs.regs(0).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "reg(regs.regs(0).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "reg(regs.regs(0).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "reg(regs.regs(0).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "reg(regs.regs(0).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "reg(regs.regs(0).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "reg(regs.regs(0).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "reg(regs.regs(0).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "reg(regs.regs(0).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "reg(regs.regs(0).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "reg(regs.regs(0).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "reg(regs.regs(0).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "reg(regs.regs(0).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "reg(regs.regs(0).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "reg(regs.regs(0).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "reg(regs.regs(0).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "reg(regs.regs(0).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "reg(regs.regs(0).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "reg(regs.regs(0).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "reg(regs.regs(0).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "reg(regs.regs(0).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "reg(regs.regs(0).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "reg(regs.regs(0).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {clk} -pin  "reg(regs.regs(0).sva)" {clk} -attr xrf 33971 -attr oid 1135 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(0).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(0).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(0).sva(0)} -pin  "reg(regs.regs(0).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "reg(regs.regs(0).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "reg(regs.regs(0).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "reg(regs.regs(0).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "reg(regs.regs(0).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "reg(regs.regs(0).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "reg(regs.regs(0).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "reg(regs.regs(0).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "reg(regs.regs(0).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "reg(regs.regs(0).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "reg(regs.regs(0).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "reg(regs.regs(0).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "reg(regs.regs(0).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "reg(regs.regs(0).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "reg(regs.regs(0).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "reg(regs.regs(0).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "reg(regs.regs(0).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "reg(regs.regs(0).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "reg(regs.regs(0).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "reg(regs.regs(0).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "reg(regs.regs(0).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "reg(regs.regs(0).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "reg(regs.regs(0).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "reg(regs.regs(0).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "reg(regs.regs(0).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "reg(regs.regs(0).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "reg(regs.regs(0).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "reg(regs.regs(0).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "reg(regs.regs(0).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "reg(regs.regs(0).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "reg(regs.regs(0).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "reg(regs.regs(0).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "reg(regs.regs(0).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "reg(regs.regs(0).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "reg(regs.regs(0).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "reg(regs.regs(0).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "reg(regs.regs(0).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "reg(regs.regs(0).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "reg(regs.regs(0).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "reg(regs.regs(0).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "reg(regs.regs(0).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "reg(regs.regs(0).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "reg(regs.regs(0).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "reg(regs.regs(0).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "reg(regs.regs(0).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "reg(regs.regs(0).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "reg(regs.regs(0).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "reg(regs.regs(0).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "reg(regs.regs(0).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "reg(regs.regs(0).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "reg(regs.regs(0).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "reg(regs.regs(0).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "reg(regs.regs(0).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "reg(regs.regs(0).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "reg(regs.regs(0).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "reg(regs.regs(0).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "reg(regs.regs(0).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "reg(regs.regs(0).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "reg(regs.regs(0).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "reg(regs.regs(0).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "reg(regs.regs(0).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "reg(regs.regs(0).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "reg(regs.regs(0).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "reg(regs.regs(0).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "reg(regs.regs(0).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "reg(regs.regs(0).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "reg(regs.regs(0).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "reg(regs.regs(0).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "reg(regs.regs(0).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "reg(regs.regs(0).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "reg(regs.regs(0).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "reg(regs.regs(0).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "reg(regs.regs(0).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "reg(regs.regs(0).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "reg(regs.regs(0).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "reg(regs.regs(0).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "reg(regs.regs(0).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "reg(regs.regs(0).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "reg(regs.regs(0).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "reg(regs.regs(0).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "reg(regs.regs(0).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "reg(regs.regs(0).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "reg(regs.regs(0).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "reg(regs.regs(0).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "reg(regs.regs(0).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "reg(regs.regs(0).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "reg(regs.regs(0).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "reg(regs.regs(0).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "reg(regs.regs(0).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "reg(regs.regs(0).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load inst "reg(exit:FRAME.lpi#1.dfm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 33972 -attr oid 1136 -attr @path {/sobel/sobel:core/reg(exit:FRAME.lpi#1.dfm#1)}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {D(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load net {GND} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1}
+load net {clk} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {clk} -attr xrf 33973 -attr oid 1137 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME.lpi#1.dfm#1} -pin  "reg(exit:FRAME.lpi#1.dfm#1)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1}
+load inst "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" "reg(12,1,1,-1,0)" "INTERFACE" -attr xrf 33974 -attr oid 1138 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#125.psp#1.lpi#1.dfm)}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(0)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(1)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(2)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(3)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(5)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(7)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(9)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_12}
+load net {GND} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_12}
+load net {clk} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {clk} -attr xrf 33975 -attr oid 1139 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(0)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(1)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(2)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(3)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(4)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(5)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(6)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(7)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(8)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(9)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(10)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(11)} -pin  "reg(ACC1:acc#125.psp#1.lpi#1.dfm)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load inst "reg(acc.imod#18.lpi#1.dfm.sg1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 33976 -attr oid 1140 -attr vt d -attr @path {/sobel/sobel:core/reg(acc.imod#18.lpi#1.dfm.sg1)}
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(0)} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1:mx0}
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(1)} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1:mx0}
+load net {GND} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {clk} -attr xrf 33977 -attr oid 1141 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {acc.imod#18.lpi#1.dfm.sg1(0)} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1}
+load net {acc.imod#18.lpi#1.dfm.sg1(1)} -pin  "reg(acc.imod#18.lpi#1.dfm.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1}
+load inst "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" "reg(3,1,1,-1,0)" "INTERFACE" -attr xrf 33978 -attr oid 1142 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(0)} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(1)} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(2)} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load net {GND} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {GND} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {GND} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_3#1}
+load net {clk} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {clk} -attr xrf 33979 -attr oid 1143 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(0)} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(1)} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(2)} -pin  "reg(ACC1:acc#110.psp#2.lpi#1.dfm.sg1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load inst "reg(acc.imod#20.lpi#1.dfm)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 33980 -attr oid 1144 -attr vt d -attr @path {/sobel/sobel:core/reg(acc.imod#20.lpi#1.dfm)}
+load net {acc.imod#20.lpi#1.dfm:mx0(0)} -pin  "reg(acc.imod#20.lpi#1.dfm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm:mx0}
+load net {acc.imod#20.lpi#1.dfm:mx0(1)} -pin  "reg(acc.imod#20.lpi#1.dfm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm:mx0}
+load net {GND} -pin  "reg(acc.imod#20.lpi#1.dfm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(acc.imod#20.lpi#1.dfm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(acc.imod#20.lpi#1.dfm)" {clk} -attr xrf 33981 -attr oid 1145 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(acc.imod#20.lpi#1.dfm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(acc.imod#20.lpi#1.dfm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {acc.imod#20.lpi#1.dfm(0)} -pin  "reg(acc.imod#20.lpi#1.dfm)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm}
+load net {acc.imod#20.lpi#1.dfm(1)} -pin  "reg(acc.imod#20.lpi#1.dfm)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm}
+load inst "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 33982 -attr oid 1146 -attr vt d -attr @path {/sobel/sobel:core/reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(0)} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(1)} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0}
+load net {GND} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {GND} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_8#14}
+load net {clk} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {clk} -attr xrf 33983 -attr oid 1147 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(0)} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(1)} -pin  "reg(ACC1:acc#118.psp#1.lpi#1.dfm.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1}
+load inst "mux#18" "mux(2,19)" "INTERFACE" -attr xrf 33984 -attr oid 1148 -attr vt d -attr @path {/sobel/sobel:core/mux#18} -attr area 17.470037 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2)"
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "mux#18" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "mux#18" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "mux#18" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "mux#18" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "mux#18" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "mux#18" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "mux#18" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "mux#18" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "mux#18" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "mux#18" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "mux#18" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "mux#18" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "mux#18" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "mux#18" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "mux#18" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "mux#18" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "mux#18" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "mux#18" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "mux#18" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.sva#1(0)} -pin  "mux#18" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "mux#18" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "mux#18" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "mux#18" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "mux#18" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "mux#18" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "mux#18" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "mux#18" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "mux#18" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "mux#18" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "mux#18" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "mux#18" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "mux#18" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "mux#18" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "mux#18" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "mux#18" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "mux#18" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "mux#18" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "mux#18" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:for:acc.itm(1)} -pin  "mux#18" {S(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc#4.itm}
+load net {mux#18.itm(0)} -pin  "mux#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(1)} -pin  "mux#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(2)} -pin  "mux#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(3)} -pin  "mux#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(4)} -pin  "mux#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(5)} -pin  "mux#18" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(6)} -pin  "mux#18" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(7)} -pin  "mux#18" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(8)} -pin  "mux#18" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(9)} -pin  "mux#18" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(10)} -pin  "mux#18" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(11)} -pin  "mux#18" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(12)} -pin  "mux#18" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(13)} -pin  "mux#18" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(14)} -pin  "mux#18" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(15)} -pin  "mux#18" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(16)} -pin  "mux#18" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(17)} -pin  "mux#18" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(18)} -pin  "mux#18" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load inst "reg(FRAME:p#1.lpi#1)" "reg(19,1,1,-1,0)" "INTERFACE" -attr xrf 33985 -attr oid 1149 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:p#1.lpi#1)}
+load net {mux#18.itm(0)} -pin  "reg(FRAME:p#1.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(1)} -pin  "reg(FRAME:p#1.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(2)} -pin  "reg(FRAME:p#1.lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(3)} -pin  "reg(FRAME:p#1.lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(4)} -pin  "reg(FRAME:p#1.lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(5)} -pin  "reg(FRAME:p#1.lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(6)} -pin  "reg(FRAME:p#1.lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(7)} -pin  "reg(FRAME:p#1.lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(8)} -pin  "reg(FRAME:p#1.lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(9)} -pin  "reg(FRAME:p#1.lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(10)} -pin  "reg(FRAME:p#1.lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(11)} -pin  "reg(FRAME:p#1.lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(12)} -pin  "reg(FRAME:p#1.lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(13)} -pin  "reg(FRAME:p#1.lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(14)} -pin  "reg(FRAME:p#1.lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(15)} -pin  "reg(FRAME:p#1.lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(16)} -pin  "reg(FRAME:p#1.lpi#1)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(17)} -pin  "reg(FRAME:p#1.lpi#1)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(18)} -pin  "reg(FRAME:p#1.lpi#1)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_19}
+load net {clk} -pin  "reg(FRAME:p#1.lpi#1)" {clk} -attr xrf 33986 -attr oid 1150 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:p#1.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:p#1.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:p#1.lpi#1(0)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load inst "FRAME:mul" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 33987 -attr oid 1151 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,12,1,13)"
+load net {ACC1:acc.itm(13)} -pin  "FRAME:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#12.itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#12.itm}
+load net {PWR} -pin  "FRAME:mul" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul.itm(0)} -pin  "FRAME:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(1)} -pin  "FRAME:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(2)} -pin  "FRAME:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(3)} -pin  "FRAME:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(4)} -pin  "FRAME:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(5)} -pin  "FRAME:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(6)} -pin  "FRAME:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(7)} -pin  "FRAME:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(8)} -pin  "FRAME:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(9)} -pin  "FRAME:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(10)} -pin  "FRAME:mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load inst "FRAME:mul#1" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 33988 -attr oid 1152 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC1:acc.itm(10)} -pin  "FRAME:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#13.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#13.itm}
+load net {ACC1:acc.itm(12)} -pin  "FRAME:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#13.itm}
+load net {PWR} -pin  "FRAME:mul#1" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#1.itm(0)} -pin  "FRAME:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "FRAME:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "FRAME:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "FRAME:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "FRAME:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "FRAME:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "FRAME:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "FRAME:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "FRAME:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load inst "FRAME:not#7" "not(1)" "INTERFACE" -attr xrf 33989 -attr oid 1153 -attr @path {/sobel/sobel:core/FRAME:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#12.sva(5)} -pin  "FRAME:not#7" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#6.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load inst "FRAME:not#5" "not(3)" "INTERFACE" -attr xrf 33990 -attr oid 1154 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#12.sva(3)} -pin  "FRAME:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#2.itm}
+load net {acc.imod#12.sva(4)} -pin  "FRAME:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#2.itm}
+load net {acc.imod#12.sva(5)} -pin  "FRAME:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#2.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load inst "FRAME:not#4" "not(1)" "INTERFACE" -attr xrf 33991 -attr oid 1155 -attr @path {/sobel/sobel:core/FRAME:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#12.sva(5)} -pin  "FRAME:not#4" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#3.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:not#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#4.itm}
+load inst "FRAME:acc#16" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 33992 -attr oid 1156 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "FRAME:acc#16" {A(0)} -attr @path {/sobel/sobel:core/conc#678.itm}
+load net {acc.imod#12.sva(0)} -pin  "FRAME:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#678.itm}
+load net {acc.imod#12.sva(1)} -pin  "FRAME:acc#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#678.itm}
+load net {acc.imod#12.sva(2)} -pin  "FRAME:acc#16" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#678.itm}
+load net {PWR} -pin  "FRAME:acc#16" {A(4)} -attr @path {/sobel/sobel:core/conc#678.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:acc#16" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:acc#16" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:acc#16" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:acc#16" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#15.itm}
+load net {FRAME:acc#16.itm(0)} -pin  "FRAME:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "FRAME:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "FRAME:acc#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "FRAME:acc#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:acc#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load inst "FRAME:not#15" "not(1)" "INTERFACE" -attr xrf 33993 -attr oid 1157 -attr @path {/sobel/sobel:core/FRAME:not#15} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:not#15" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#3.itm}
+load net {FRAME:not#15.itm} -pin  "FRAME:not#15" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#15.itm}
+load inst "FRAME:acc#10" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 33994 -attr oid 1158 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {FRAME:not#15.itm} -pin  "FRAME:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#677.itm}
+load net {PWR} -pin  "FRAME:acc#10" {A(1)} -attr @path {/sobel/sobel:core/conc#677.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#677.itm}
+load net {acc.imod#12.sva(3)} -pin  "FRAME:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#4.itm}
+load net {acc.imod#12.sva(4)} -pin  "FRAME:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#12.sva)#4.itm}
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load inst "FRAME:not#6" "not(3)" "INTERFACE" -attr xrf 33995 -attr oid 1159 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(7)} -pin  "FRAME:not#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#7.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:not#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#7.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:not#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#7.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:not#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:not#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:not#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load inst "FRAME:acc#11" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 33996 -attr oid 1160 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#11" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#11" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#11" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#11" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:acc#11" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:acc#11" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:acc#11" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#11" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#11" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#11" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#11" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "FRAME:acc#11" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load inst "FRAME:acc#12" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 33997 -attr oid 1161 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "FRAME:acc#12" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {acc.imod#12.sva(5)} -pin  "FRAME:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#679.itm}
+load net {PWR} -pin  "FRAME:acc#12" {B(1)} -attr @path {/sobel/sobel:core/conc#679.itm}
+load net {GND} -pin  "FRAME:acc#12" {B(2)} -attr @path {/sobel/sobel:core/conc#679.itm}
+load net {GND} -pin  "FRAME:acc#12" {B(3)} -attr @path {/sobel/sobel:core/conc#679.itm}
+load net {PWR} -pin  "FRAME:acc#12" {B(4)} -attr @path {/sobel/sobel:core/conc#679.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(4)} -pin  "FRAME:acc#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load inst "FRAME:acc#13" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 33998 -attr oid 1162 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {ACC1:acc.itm(4)} -pin  "FRAME:acc#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:acc#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(6)} -pin  "FRAME:acc#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(7)} -pin  "FRAME:acc#13" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:acc#13" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:acc#13" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#2.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#13" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#13" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#13" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#13" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(4)} -pin  "FRAME:acc#13" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(4)} -pin  "FRAME:acc#13" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(5)} -pin  "FRAME:acc#13" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(6)} -pin  "FRAME:acc#13" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(7)} -pin  "FRAME:acc#13" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load inst "FRAME:acc#14" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 33999 -attr oid 1163 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul#1.itm(0)} -pin  "FRAME:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "FRAME:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "FRAME:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "FRAME:acc#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "FRAME:acc#14" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "FRAME:acc#14" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "FRAME:acc#14" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "FRAME:acc#14" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "FRAME:acc#14" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#14" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(4)} -pin  "FRAME:acc#14" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(5)} -pin  "FRAME:acc#14" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(6)} -pin  "FRAME:acc#14" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(7)} -pin  "FRAME:acc#14" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(4)} -pin  "FRAME:acc#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(5)} -pin  "FRAME:acc#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(6)} -pin  "FRAME:acc#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(7)} -pin  "FRAME:acc#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(8)} -pin  "FRAME:acc#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(9)} -pin  "FRAME:acc#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load inst "FRAME:acc#15" "add(11,0,10,1,12)" "INTERFACE" -attr xrf 34000 -attr oid 1164 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,11,1,13)"
+load net {FRAME:mul.itm(0)} -pin  "FRAME:acc#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(1)} -pin  "FRAME:acc#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(2)} -pin  "FRAME:acc#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(3)} -pin  "FRAME:acc#15" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(4)} -pin  "FRAME:acc#15" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(5)} -pin  "FRAME:acc#15" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(6)} -pin  "FRAME:acc#15" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(7)} -pin  "FRAME:acc#15" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(8)} -pin  "FRAME:acc#15" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(9)} -pin  "FRAME:acc#15" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:mul.itm(10)} -pin  "FRAME:acc#15" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#15" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#15" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#15" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#15" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(4)} -pin  "FRAME:acc#15" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(5)} -pin  "FRAME:acc#15" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(6)} -pin  "FRAME:acc#15" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(7)} -pin  "FRAME:acc#15" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(8)} -pin  "FRAME:acc#15" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(9)} -pin  "FRAME:acc#15" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(5)} -pin  "FRAME:acc#15" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(6)} -pin  "FRAME:acc#15" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(7)} -pin  "FRAME:acc#15" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(8)} -pin  "FRAME:acc#15" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(9)} -pin  "FRAME:acc#15" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(10)} -pin  "FRAME:acc#15" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(11)} -pin  "FRAME:acc#15" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load inst "FRAME:acc#2" "add(12,-1,11,0,12)" "INTERFACE" -attr xrf 34001 -attr oid 1165 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2} -attr area 13.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13)"
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(5)} -pin  "FRAME:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(6)} -pin  "FRAME:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(7)} -pin  "FRAME:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(8)} -pin  "FRAME:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(9)} -pin  "FRAME:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(10)} -pin  "FRAME:acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(11)} -pin  "FRAME:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(1)} -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(5)} -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(6)} -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {GND} -pin  "FRAME:acc#2" {B(7)} -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {ACC1:acc.itm(15)} -pin  "FRAME:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/exs#62.itm}
+load net {FRAME:acc#2.psp.sva(0)} -pin  "FRAME:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(1)} -pin  "FRAME:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(2)} -pin  "FRAME:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(3)} -pin  "FRAME:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(4)} -pin  "FRAME:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(5)} -pin  "FRAME:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(6)} -pin  "FRAME:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(7)} -pin  "FRAME:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(8)} -pin  "FRAME:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(9)} -pin  "FRAME:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(10)} -pin  "FRAME:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load net {FRAME:acc#2.psp.sva(11)} -pin  "FRAME:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.psp.sva}
+load inst "ACC1:acc#342" "add(16,-1,13,1,16)" "INTERFACE" -attr xrf 34002 -attr oid 1166 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,13,1,16)"
+load net {in(2).sva#3(0)} -pin  "ACC1:acc#342" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(1)} -pin  "ACC1:acc#342" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(2)} -pin  "ACC1:acc#342" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(3)} -pin  "ACC1:acc#342" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(4)} -pin  "ACC1:acc#342" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(5)} -pin  "ACC1:acc#342" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(6)} -pin  "ACC1:acc#342" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(7)} -pin  "ACC1:acc#342" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(8)} -pin  "ACC1:acc#342" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(9)} -pin  "ACC1:acc#342" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(10)} -pin  "ACC1:acc#342" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(11)} -pin  "ACC1:acc#342" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(12)} -pin  "ACC1:acc#342" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(13)} -pin  "ACC1:acc#342" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(14)} -pin  "ACC1:acc#342" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(15)} -pin  "ACC1:acc#342" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {ACC1:acc#341.itm#1(0)} -pin  "ACC1:acc#342" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(1)} -pin  "ACC1:acc#342" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(2)} -pin  "ACC1:acc#342" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(3)} -pin  "ACC1:acc#342" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(4)} -pin  "ACC1:acc#342" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(5)} -pin  "ACC1:acc#342" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(6)} -pin  "ACC1:acc#342" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(7)} -pin  "ACC1:acc#342" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(8)} -pin  "ACC1:acc#342" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(9)} -pin  "ACC1:acc#342" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(10)} -pin  "ACC1:acc#342" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(11)} -pin  "ACC1:acc#342" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#341.itm#1(12)} -pin  "ACC1:acc#342" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#341.itm#1}
+load net {ACC1:acc#342.itm(0)} -pin  "ACC1:acc#342" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(1)} -pin  "ACC1:acc#342" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(2)} -pin  "ACC1:acc#342" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(3)} -pin  "ACC1:acc#342" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(4)} -pin  "ACC1:acc#342" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(5)} -pin  "ACC1:acc#342" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(6)} -pin  "ACC1:acc#342" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(7)} -pin  "ACC1:acc#342" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(8)} -pin  "ACC1:acc#342" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(9)} -pin  "ACC1:acc#342" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(10)} -pin  "ACC1:acc#342" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(11)} -pin  "ACC1:acc#342" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(12)} -pin  "ACC1:acc#342" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(13)} -pin  "ACC1:acc#342" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(14)} -pin  "ACC1:acc#342" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(15)} -pin  "ACC1:acc#342" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load inst "ACC1:acc" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 34003 -attr oid 1167 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {ACC1:acc#342.itm(0)} -pin  "ACC1:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(1)} -pin  "ACC1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(2)} -pin  "ACC1:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(3)} -pin  "ACC1:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(4)} -pin  "ACC1:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(5)} -pin  "ACC1:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(6)} -pin  "ACC1:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(7)} -pin  "ACC1:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(8)} -pin  "ACC1:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(9)} -pin  "ACC1:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(10)} -pin  "ACC1:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(11)} -pin  "ACC1:acc" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(12)} -pin  "ACC1:acc" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(13)} -pin  "ACC1:acc" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(14)} -pin  "ACC1:acc" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {ACC1:acc#342.itm(15)} -pin  "ACC1:acc" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#342.itm}
+load net {in(0).sva#3(0)} -pin  "ACC1:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(1)} -pin  "ACC1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(2)} -pin  "ACC1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(3)} -pin  "ACC1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(4)} -pin  "ACC1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(5)} -pin  "ACC1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(6)} -pin  "ACC1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(7)} -pin  "ACC1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(8)} -pin  "ACC1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(9)} -pin  "ACC1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(10)} -pin  "ACC1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(11)} -pin  "ACC1:acc" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(12)} -pin  "ACC1:acc" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(13)} -pin  "ACC1:acc" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(14)} -pin  "ACC1:acc" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(15)} -pin  "ACC1:acc" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {ACC1:acc.itm(0)} -pin  "ACC1:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(1)} -pin  "ACC1:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(2)} -pin  "ACC1:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(3)} -pin  "ACC1:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(4)} -pin  "ACC1:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(5)} -pin  "ACC1:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(6)} -pin  "ACC1:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(7)} -pin  "ACC1:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(8)} -pin  "ACC1:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(9)} -pin  "ACC1:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(10)} -pin  "ACC1:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(11)} -pin  "ACC1:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(12)} -pin  "ACC1:acc" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(13)} -pin  "ACC1:acc" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(14)} -pin  "ACC1:acc" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load net {ACC1:acc.itm(15)} -pin  "ACC1:acc" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc.itm}
+load inst "FRAME:not#2" "not(3)" "INTERFACE" -attr xrf 34004 -attr oid 1168 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(10)} -pin  "FRAME:not#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#1.itm}
+load net {ACC1:acc.itm(11)} -pin  "FRAME:not#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#1.itm}
+load net {ACC1:acc.itm(12)} -pin  "FRAME:not#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#1.itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:not#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:not#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:not#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load inst "FRAME:acc#6" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 34005 -attr oid 1169 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc.itm(7)} -pin  "FRAME:acc#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#3.itm}
+load net {ACC1:acc.itm(8)} -pin  "FRAME:acc#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#3.itm}
+load net {ACC1:acc.itm(9)} -pin  "FRAME:acc#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#3.itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:acc#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:acc#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:acc#6" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:acc#6.itm(0)} -pin  "FRAME:acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(1)} -pin  "FRAME:acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(2)} -pin  "FRAME:acc#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(3)} -pin  "FRAME:acc#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load inst "FRAME:not#13" "not(1)" "INTERFACE" -attr xrf 34006 -attr oid 1170 -attr @path {/sobel/sobel:core/FRAME:not#13} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc.itm(15)} -pin  "FRAME:not#13" {A(0)} -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#29.itm}
+load net {FRAME:not#13.itm} -pin  "FRAME:not#13" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load inst "FRAME:not#17" "not(1)" "INTERFACE" -attr xrf 34007 -attr oid 1171 -attr @path {/sobel/sobel:core/FRAME:not#17} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc.itm(15)} -pin  "FRAME:not#17" {A(0)} -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#10.itm}
+load net {FRAME:not#17.itm} -pin  "FRAME:not#17" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load inst "FRAME:acc#5" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 34008 -attr oid 1172 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {FRAME:not#17.itm} -pin  "FRAME:acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#682.itm}
+load net {PWR} -pin  "FRAME:acc#5" {A(1)} -attr @path {/sobel/sobel:core/conc#682.itm}
+load net {FRAME:not#13.itm} -pin  "FRAME:acc#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#682.itm}
+load net {ACC1:acc.itm(13)} -pin  "FRAME:acc#5" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva).itm}
+load net {ACC1:acc.itm(14)} -pin  "FRAME:acc#5" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva).itm}
+load net {FRAME:acc#5.itm(0)} -pin  "FRAME:acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(1)} -pin  "FRAME:acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(2)} -pin  "FRAME:acc#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(3)} -pin  "FRAME:acc#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load inst "FRAME:acc#8" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 34009 -attr oid 1173 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#6.itm(0)} -pin  "FRAME:acc#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(1)} -pin  "FRAME:acc#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(2)} -pin  "FRAME:acc#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#6.itm(3)} -pin  "FRAME:acc#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6.itm}
+load net {FRAME:acc#5.itm(0)} -pin  "FRAME:acc#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(1)} -pin  "FRAME:acc#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(2)} -pin  "FRAME:acc#8" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#5.itm(3)} -pin  "FRAME:acc#8" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#5.itm}
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(4)} -pin  "FRAME:acc#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load inst "FRAME:not#1" "not(3)" "INTERFACE" -attr xrf 34010 -attr oid 1174 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC1:acc.itm(4)} -pin  "FRAME:not#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#6.itm}
+load net {ACC1:acc.itm(5)} -pin  "FRAME:not#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#6.itm}
+load net {ACC1:acc.itm(6)} -pin  "FRAME:not#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#6.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:not#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:not#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:not#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load inst "FRAME:acc#7" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 34011 -attr oid 1175 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC1:acc.itm(1)} -pin  "FRAME:acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#5.itm}
+load net {ACC1:acc.itm(2)} -pin  "FRAME:acc#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#5.itm}
+load net {ACC1:acc.itm(3)} -pin  "FRAME:acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(intensity#2.sg1.sva)#5.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:acc#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:acc#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:acc#7" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load inst "FRAME:acc#9" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 34012 -attr oid 1176 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#9" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(4)} -pin  "FRAME:acc#9" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#9" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#9" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#9" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#9" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(4)} -pin  "FRAME:acc#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(5)} -pin  "FRAME:acc#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load inst "acc#15" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 34013 -attr oid 1177 -attr vt d -attr @path {/sobel/sobel:core/acc#15} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,1,8)"
+load net {FRAME:acc#9.itm(0)} -pin  "acc#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "acc#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "acc#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "acc#15" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(4)} -pin  "acc#15" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(5)} -pin  "acc#15" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {PWR} -pin  "acc#15" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#15" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#15" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#15" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#15" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#15" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#12.sva(0)} -pin  "acc#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load net {acc.imod#12.sva(1)} -pin  "acc#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load net {acc.imod#12.sva(2)} -pin  "acc#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load net {acc.imod#12.sva(3)} -pin  "acc#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load net {acc.imod#12.sva(4)} -pin  "acc#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load net {acc.imod#12.sva(5)} -pin  "acc#15" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#12.sva}
+load inst "FRAME:for:mux#12" "mux(2,16)" "INTERFACE" -attr xrf 34014 -attr oid 1178 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:slc(in(2).sva).itm#1(0)} -pin  "FRAME:for:mux#12" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(1)} -pin  "FRAME:for:mux#12" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(2)} -pin  "FRAME:for:mux#12" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(3)} -pin  "FRAME:for:mux#12" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(4)} -pin  "FRAME:for:mux#12" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(5)} -pin  "FRAME:for:mux#12" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(6)} -pin  "FRAME:for:mux#12" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(7)} -pin  "FRAME:for:mux#12" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(8)} -pin  "FRAME:for:mux#12" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(9)} -pin  "FRAME:for:mux#12" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(10)} -pin  "FRAME:for:mux#12" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -pin  "FRAME:for:mux#12" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -pin  "FRAME:for:mux#12" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -pin  "FRAME:for:mux#12" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -pin  "FRAME:for:mux#12" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {FRAME:for:slc(in(2).sva).itm#1(11)} -pin  "FRAME:for:mux#12" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#21.itm}
+load net {in(2).sva#1(0)} -pin  "FRAME:for:mux#12" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(1)} -pin  "FRAME:for:mux#12" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(2)} -pin  "FRAME:for:mux#12" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(3)} -pin  "FRAME:for:mux#12" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(4)} -pin  "FRAME:for:mux#12" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(5)} -pin  "FRAME:for:mux#12" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(6)} -pin  "FRAME:for:mux#12" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(7)} -pin  "FRAME:for:mux#12" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(8)} -pin  "FRAME:for:mux#12" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(9)} -pin  "FRAME:for:mux#12" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(10)} -pin  "FRAME:for:mux#12" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(11)} -pin  "FRAME:for:mux#12" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(12)} -pin  "FRAME:for:mux#12" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(13)} -pin  "FRAME:for:mux#12" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(14)} -pin  "FRAME:for:mux#12" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {in(2).sva#1(15)} -pin  "FRAME:for:mux#12" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm#3} -pin  "FRAME:for:mux#12" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#3}
+load net {FRAME:for:mux#12.itm(0)} -pin  "FRAME:for:mux#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(1)} -pin  "FRAME:for:mux#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(2)} -pin  "FRAME:for:mux#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(3)} -pin  "FRAME:for:mux#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(4)} -pin  "FRAME:for:mux#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(5)} -pin  "FRAME:for:mux#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(6)} -pin  "FRAME:for:mux#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(7)} -pin  "FRAME:for:mux#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(8)} -pin  "FRAME:for:mux#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(9)} -pin  "FRAME:for:mux#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(10)} -pin  "FRAME:for:mux#12" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(11)} -pin  "FRAME:for:mux#12" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(12)} -pin  "FRAME:for:mux#12" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(13)} -pin  "FRAME:for:mux#12" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(14)} -pin  "FRAME:for:mux#12" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(15)} -pin  "FRAME:for:mux#12" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load inst "FRAME:for:acc#22" "add(12,1,16,-1,16)" "INTERFACE" -attr xrf 34015 -attr oid 1179 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#22} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,13,1,16)"
+load net {FRAME:for:acc#26.itm#1(0)} -pin  "FRAME:for:acc#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(1)} -pin  "FRAME:for:acc#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(2)} -pin  "FRAME:for:acc#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(3)} -pin  "FRAME:for:acc#22" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(4)} -pin  "FRAME:for:acc#22" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(5)} -pin  "FRAME:for:acc#22" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(6)} -pin  "FRAME:for:acc#22" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(7)} -pin  "FRAME:for:acc#22" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(8)} -pin  "FRAME:for:acc#22" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(9)} -pin  "FRAME:for:acc#22" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(10)} -pin  "FRAME:for:acc#22" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:acc#26.itm#1(11)} -pin  "FRAME:for:acc#22" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm#1}
+load net {FRAME:for:mux#12.itm(0)} -pin  "FRAME:for:acc#22" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(1)} -pin  "FRAME:for:acc#22" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(2)} -pin  "FRAME:for:acc#22" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(3)} -pin  "FRAME:for:acc#22" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(4)} -pin  "FRAME:for:acc#22" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(5)} -pin  "FRAME:for:acc#22" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(6)} -pin  "FRAME:for:acc#22" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(7)} -pin  "FRAME:for:acc#22" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(8)} -pin  "FRAME:for:acc#22" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(9)} -pin  "FRAME:for:acc#22" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(10)} -pin  "FRAME:for:acc#22" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(11)} -pin  "FRAME:for:acc#22" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(12)} -pin  "FRAME:for:acc#22" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(13)} -pin  "FRAME:for:acc#22" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(14)} -pin  "FRAME:for:acc#22" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {FRAME:for:mux#12.itm(15)} -pin  "FRAME:for:acc#22" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#12.itm}
+load net {in(2).sva#3(0)} -pin  "FRAME:for:acc#22" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(1)} -pin  "FRAME:for:acc#22" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(2)} -pin  "FRAME:for:acc#22" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(3)} -pin  "FRAME:for:acc#22" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(4)} -pin  "FRAME:for:acc#22" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(5)} -pin  "FRAME:for:acc#22" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(6)} -pin  "FRAME:for:acc#22" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(7)} -pin  "FRAME:for:acc#22" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(8)} -pin  "FRAME:for:acc#22" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(9)} -pin  "FRAME:for:acc#22" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(10)} -pin  "FRAME:for:acc#22" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(11)} -pin  "FRAME:for:acc#22" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(12)} -pin  "FRAME:for:acc#22" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(13)} -pin  "FRAME:for:acc#22" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(14)} -pin  "FRAME:for:acc#22" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load net {in(2).sva#3(15)} -pin  "FRAME:for:acc#22" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/in(2).sva#3}
+load inst "FRAME:for:mux#11" "mux(2,16)" "INTERFACE" -attr xrf 34016 -attr oid 1180 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11} -attr area 14.710768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:slc(in(0).sva).itm#1(0)} -pin  "FRAME:for:mux#11" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(1)} -pin  "FRAME:for:mux#11" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(2)} -pin  "FRAME:for:mux#11" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(3)} -pin  "FRAME:for:mux#11" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(4)} -pin  "FRAME:for:mux#11" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(5)} -pin  "FRAME:for:mux#11" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(6)} -pin  "FRAME:for:mux#11" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(7)} -pin  "FRAME:for:mux#11" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(8)} -pin  "FRAME:for:mux#11" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(9)} -pin  "FRAME:for:mux#11" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(10)} -pin  "FRAME:for:mux#11" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -pin  "FRAME:for:mux#11" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -pin  "FRAME:for:mux#11" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -pin  "FRAME:for:mux#11" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -pin  "FRAME:for:mux#11" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {FRAME:for:slc(in(0).sva).itm#1(11)} -pin  "FRAME:for:mux#11" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#20.itm}
+load net {in(0).sva#1(0)} -pin  "FRAME:for:mux#11" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(1)} -pin  "FRAME:for:mux#11" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(2)} -pin  "FRAME:for:mux#11" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(3)} -pin  "FRAME:for:mux#11" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(4)} -pin  "FRAME:for:mux#11" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(5)} -pin  "FRAME:for:mux#11" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(6)} -pin  "FRAME:for:mux#11" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(7)} -pin  "FRAME:for:mux#11" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(8)} -pin  "FRAME:for:mux#11" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(9)} -pin  "FRAME:for:mux#11" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(10)} -pin  "FRAME:for:mux#11" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(11)} -pin  "FRAME:for:mux#11" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(12)} -pin  "FRAME:for:mux#11" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(13)} -pin  "FRAME:for:mux#11" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(14)} -pin  "FRAME:for:mux#11" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {in(0).sva#1(15)} -pin  "FRAME:for:mux#11" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#1}
+load net {exit:FRAME:for.lpi#1.dfm#3} -pin  "FRAME:for:mux#11" {S(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#3}
+load net {FRAME:for:mux#11.itm(0)} -pin  "FRAME:for:mux#11" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(1)} -pin  "FRAME:for:mux#11" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(2)} -pin  "FRAME:for:mux#11" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(3)} -pin  "FRAME:for:mux#11" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(4)} -pin  "FRAME:for:mux#11" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(5)} -pin  "FRAME:for:mux#11" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(6)} -pin  "FRAME:for:mux#11" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(7)} -pin  "FRAME:for:mux#11" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(8)} -pin  "FRAME:for:mux#11" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(9)} -pin  "FRAME:for:mux#11" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(10)} -pin  "FRAME:for:mux#11" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(11)} -pin  "FRAME:for:mux#11" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(12)} -pin  "FRAME:for:mux#11" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(13)} -pin  "FRAME:for:mux#11" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(14)} -pin  "FRAME:for:mux#11" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(15)} -pin  "FRAME:for:mux#11" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load inst "FRAME:for:acc#20" "add(13,1,16,-1,16)" "INTERFACE" -attr xrf 34017 -attr oid 1181 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#20} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,13,1,16)"
+load net {FRAME:for:acc#24.itm#1(0)} -pin  "FRAME:for:acc#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(1)} -pin  "FRAME:for:acc#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(2)} -pin  "FRAME:for:acc#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(3)} -pin  "FRAME:for:acc#20" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(4)} -pin  "FRAME:for:acc#20" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(5)} -pin  "FRAME:for:acc#20" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(6)} -pin  "FRAME:for:acc#20" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(7)} -pin  "FRAME:for:acc#20" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(8)} -pin  "FRAME:for:acc#20" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(9)} -pin  "FRAME:for:acc#20" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(10)} -pin  "FRAME:for:acc#20" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(11)} -pin  "FRAME:for:acc#20" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:acc#24.itm#1(12)} -pin  "FRAME:for:acc#20" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#24.itm#1}
+load net {FRAME:for:mux#11.itm(0)} -pin  "FRAME:for:acc#20" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(1)} -pin  "FRAME:for:acc#20" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(2)} -pin  "FRAME:for:acc#20" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(3)} -pin  "FRAME:for:acc#20" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(4)} -pin  "FRAME:for:acc#20" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(5)} -pin  "FRAME:for:acc#20" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(6)} -pin  "FRAME:for:acc#20" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(7)} -pin  "FRAME:for:acc#20" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(8)} -pin  "FRAME:for:acc#20" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(9)} -pin  "FRAME:for:acc#20" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(10)} -pin  "FRAME:for:acc#20" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(11)} -pin  "FRAME:for:acc#20" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(12)} -pin  "FRAME:for:acc#20" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(13)} -pin  "FRAME:for:acc#20" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(14)} -pin  "FRAME:for:acc#20" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {FRAME:for:mux#11.itm(15)} -pin  "FRAME:for:acc#20" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mux#11.itm}
+load net {in(0).sva#3(0)} -pin  "FRAME:for:acc#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(1)} -pin  "FRAME:for:acc#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(2)} -pin  "FRAME:for:acc#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(3)} -pin  "FRAME:for:acc#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(4)} -pin  "FRAME:for:acc#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(5)} -pin  "FRAME:for:acc#20" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(6)} -pin  "FRAME:for:acc#20" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(7)} -pin  "FRAME:for:acc#20" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(8)} -pin  "FRAME:for:acc#20" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(9)} -pin  "FRAME:for:acc#20" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(10)} -pin  "FRAME:for:acc#20" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(11)} -pin  "FRAME:for:acc#20" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(12)} -pin  "FRAME:for:acc#20" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(13)} -pin  "FRAME:for:acc#20" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(14)} -pin  "FRAME:for:acc#20" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load net {in(0).sva#3(15)} -pin  "FRAME:for:acc#20" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/in(0).sva#3}
+load inst "FRAME:for:acc" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 34018 -attr oid 1182 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2)"
+load net {i#6.sva#2(0)} -pin  "FRAME:for:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "FRAME:for:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {PWR} -pin  "FRAME:for:acc" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:for:acc.itm(0)} -pin  "FRAME:for:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+load inst "FRAME:for:or" "or(2,1)" "INTERFACE" -attr xrf 34019 -attr oid 1183 -attr @path {/sobel/sobel:core/FRAME:for:or} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "FRAME:for:or" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {exit:FRAME#1.sva} -pin  "FRAME:for:or" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {exit:FRAME:for.lpi#1.dfm#4} -pin  "FRAME:for:or" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#4}
+load inst "FRAME:for:acc#16" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 34020 -attr oid 1184 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#16} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:for:acc#16" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {i#6.sva#2(0)} -pin  "FRAME:for:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load net {i#6.sva#2(1)} -pin  "FRAME:for:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#2}
+load inst "not#27" "not(1)" "INTERFACE" -attr xrf 34021 -attr oid 1185 -attr @path {/sobel/sobel:core/not#27} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1.dfm#4} -pin  "not#27" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#4}
+load net {not#27.itm} -pin  "not#27" {Z(0)} -attr @path {/sobel/sobel:core/not#27.itm}
+load inst "FRAME:for:and#1" "and(2,2)" "INTERFACE" -attr xrf 34022 -attr oid 1186 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#1} -attr area 1.459665 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2)"
+load net {i#6.sva#1(0)} -pin  "FRAME:for:and#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "FRAME:for:and#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {not#27.itm} -pin  "FRAME:for:and#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#19.itm}
+load net {not#27.itm} -pin  "FRAME:for:and#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#19.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:and#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:and#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load inst "mux#3" "mux(2,3)" "INTERFACE" -attr xrf 34023 -attr oid 1187 -attr vt d -attr @path {/sobel/sobel:core/mux#3} -attr area 2.759269 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(3,1,2)"
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(0)} -pin  "mux#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(1)} -pin  "mux#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1(2)} -pin  "mux#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#176.itm(2)} -pin  "mux#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.sva).itm}
+load net {ACC1:acc#176.itm(3)} -pin  "mux#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.sva).itm}
+load net {ACC1:acc#176.itm(4)} -pin  "mux#3" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.sva).itm}
+load net {and.cse} -pin  "mux#3" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(0)} -pin  "mux#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(1)} -pin  "mux#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0(2)} -pin  "mux#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#1.lpi#1.dfm.sg1:mx0}
+load inst "mux#4" "mux(2,12)" "INTERFACE" -attr xrf 34024 -attr oid 1188 -attr vt d -attr @path {/sobel/sobel:core/mux#4} -attr area 11.034076 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(12,1,2)"
+load net {ACC1:acc#125.psp.lpi#1.dfm(0)} -pin  "mux#4" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(1)} -pin  "mux#4" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(2)} -pin  "mux#4" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(3)} -pin  "mux#4" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(4)} -pin  "mux#4" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(5)} -pin  "mux#4" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(6)} -pin  "mux#4" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(7)} -pin  "mux#4" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(8)} -pin  "mux#4" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(9)} -pin  "mux#4" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(10)} -pin  "mux#4" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.lpi#1.dfm(11)} -pin  "mux#4" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm}
+load net {ACC1:acc#125.psp.sva(0)} -pin  "mux#4" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(1)} -pin  "mux#4" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(2)} -pin  "mux#4" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(3)} -pin  "mux#4" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(4)} -pin  "mux#4" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(5)} -pin  "mux#4" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(6)} -pin  "mux#4" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(7)} -pin  "mux#4" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(8)} -pin  "mux#4" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(9)} -pin  "mux#4" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(10)} -pin  "mux#4" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(11)} -pin  "mux#4" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {and.cse} -pin  "mux#4" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(0)} -pin  "mux#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(1)} -pin  "mux#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(2)} -pin  "mux#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(3)} -pin  "mux#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(4)} -pin  "mux#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(5)} -pin  "mux#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(6)} -pin  "mux#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(7)} -pin  "mux#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(8)} -pin  "mux#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(9)} -pin  "mux#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(10)} -pin  "mux#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp.lpi#1.dfm:mx0(11)} -pin  "mux#4" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.lpi#1.dfm:mx0}
+load inst "mux#5" "mux(2,2)" "INTERFACE" -attr xrf 34025 -attr oid 1189 -attr vt d -attr @path {/sobel/sobel:core/mux#5} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1(0)} -pin  "mux#5" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1(1)} -pin  "mux#5" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp.sva(1)} -pin  "mux#5" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp.sva).itm}
+load net {ACC1:acc#118.psp.sva(2)} -pin  "mux#5" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp.sva).itm}
+load net {and.cse} -pin  "mux#5" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(0)} -pin  "mux#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0(1)} -pin  "mux#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.lpi#1.dfm.sg1:mx0}
+load inst "mux#6" "mux(2,30)" "INTERFACE" -attr xrf 34026 -attr oid 1190 -attr vt d -attr @path {/sobel/sobel:core/mux#6} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {regs.regs(2).lpi#1.dfm.sg2(0)} -pin  "mux#6" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(1)} -pin  "mux#6" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(2)} -pin  "mux#6" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(3)} -pin  "mux#6" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(4)} -pin  "mux#6" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(5)} -pin  "mux#6" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(6)} -pin  "mux#6" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(7)} -pin  "mux#6" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(8)} -pin  "mux#6" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(9)} -pin  "mux#6" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(10)} -pin  "mux#6" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(11)} -pin  "mux#6" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(12)} -pin  "mux#6" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(13)} -pin  "mux#6" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(14)} -pin  "mux#6" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(15)} -pin  "mux#6" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(16)} -pin  "mux#6" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(17)} -pin  "mux#6" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(18)} -pin  "mux#6" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(19)} -pin  "mux#6" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(20)} -pin  "mux#6" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(21)} -pin  "mux#6" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(22)} -pin  "mux#6" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(23)} -pin  "mux#6" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(24)} -pin  "mux#6" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(25)} -pin  "mux#6" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(26)} -pin  "mux#6" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(27)} -pin  "mux#6" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(28)} -pin  "mux#6" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(2).lpi#1.dfm.sg2(29)} -pin  "mux#6" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2}
+load net {regs.regs(1).sva(60)} -pin  "mux#6" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(61)} -pin  "mux#6" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(62)} -pin  "mux#6" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(63)} -pin  "mux#6" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(64)} -pin  "mux#6" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(65)} -pin  "mux#6" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(66)} -pin  "mux#6" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(67)} -pin  "mux#6" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(68)} -pin  "mux#6" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(69)} -pin  "mux#6" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(70)} -pin  "mux#6" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(71)} -pin  "mux#6" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(72)} -pin  "mux#6" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(73)} -pin  "mux#6" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(74)} -pin  "mux#6" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(75)} -pin  "mux#6" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(76)} -pin  "mux#6" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(77)} -pin  "mux#6" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(78)} -pin  "mux#6" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(79)} -pin  "mux#6" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(80)} -pin  "mux#6" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(81)} -pin  "mux#6" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(82)} -pin  "mux#6" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(83)} -pin  "mux#6" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(84)} -pin  "mux#6" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(85)} -pin  "mux#6" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(86)} -pin  "mux#6" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(87)} -pin  "mux#6" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(88)} -pin  "mux#6" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(89)} -pin  "mux#6" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {and.cse} -pin  "mux#6" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(0)} -pin  "mux#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(1)} -pin  "mux#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(2)} -pin  "mux#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(3)} -pin  "mux#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(4)} -pin  "mux#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(5)} -pin  "mux#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(6)} -pin  "mux#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(7)} -pin  "mux#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(8)} -pin  "mux#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(9)} -pin  "mux#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(10)} -pin  "mux#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(11)} -pin  "mux#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(12)} -pin  "mux#6" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(13)} -pin  "mux#6" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(14)} -pin  "mux#6" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(15)} -pin  "mux#6" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(16)} -pin  "mux#6" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(17)} -pin  "mux#6" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(18)} -pin  "mux#6" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(19)} -pin  "mux#6" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(20)} -pin  "mux#6" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(21)} -pin  "mux#6" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(22)} -pin  "mux#6" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(23)} -pin  "mux#6" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(24)} -pin  "mux#6" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(25)} -pin  "mux#6" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(26)} -pin  "mux#6" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(27)} -pin  "mux#6" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(28)} -pin  "mux#6" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load net {regs.regs(2).lpi#1.dfm.sg2:mx0(29)} -pin  "mux#6" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm.sg2:mx0}
+load inst "mux#7" "mux(2,30)" "INTERFACE" -attr xrf 34027 -attr oid 1191 -attr vt d -attr @path {/sobel/sobel:core/mux#7} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {regs.regs(2).lpi#1.dfm#1(0)} -pin  "mux#7" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(1)} -pin  "mux#7" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(2)} -pin  "mux#7" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(3)} -pin  "mux#7" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(4)} -pin  "mux#7" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(5)} -pin  "mux#7" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(6)} -pin  "mux#7" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(7)} -pin  "mux#7" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(8)} -pin  "mux#7" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(9)} -pin  "mux#7" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(10)} -pin  "mux#7" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(11)} -pin  "mux#7" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(12)} -pin  "mux#7" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(13)} -pin  "mux#7" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(14)} -pin  "mux#7" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(15)} -pin  "mux#7" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(16)} -pin  "mux#7" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(17)} -pin  "mux#7" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(18)} -pin  "mux#7" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(19)} -pin  "mux#7" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(20)} -pin  "mux#7" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(21)} -pin  "mux#7" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(22)} -pin  "mux#7" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(23)} -pin  "mux#7" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(24)} -pin  "mux#7" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(25)} -pin  "mux#7" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(26)} -pin  "mux#7" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(27)} -pin  "mux#7" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(28)} -pin  "mux#7" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(2).lpi#1.dfm#1(29)} -pin  "mux#7" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1}
+load net {regs.regs(1).sva(0)} -pin  "mux#7" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(1)} -pin  "mux#7" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(2)} -pin  "mux#7" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(3)} -pin  "mux#7" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(4)} -pin  "mux#7" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(5)} -pin  "mux#7" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(6)} -pin  "mux#7" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(7)} -pin  "mux#7" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(8)} -pin  "mux#7" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(9)} -pin  "mux#7" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(10)} -pin  "mux#7" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(11)} -pin  "mux#7" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(12)} -pin  "mux#7" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(13)} -pin  "mux#7" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(14)} -pin  "mux#7" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(15)} -pin  "mux#7" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(16)} -pin  "mux#7" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(17)} -pin  "mux#7" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(18)} -pin  "mux#7" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(19)} -pin  "mux#7" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(20)} -pin  "mux#7" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(21)} -pin  "mux#7" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(22)} -pin  "mux#7" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(23)} -pin  "mux#7" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(24)} -pin  "mux#7" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(25)} -pin  "mux#7" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(26)} -pin  "mux#7" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(27)} -pin  "mux#7" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(28)} -pin  "mux#7" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(29)} -pin  "mux#7" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {and.cse} -pin  "mux#7" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(0)} -pin  "mux#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(1)} -pin  "mux#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(2)} -pin  "mux#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(3)} -pin  "mux#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(4)} -pin  "mux#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(5)} -pin  "mux#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(6)} -pin  "mux#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(7)} -pin  "mux#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(8)} -pin  "mux#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(9)} -pin  "mux#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(10)} -pin  "mux#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(11)} -pin  "mux#7" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(12)} -pin  "mux#7" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(13)} -pin  "mux#7" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(14)} -pin  "mux#7" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(15)} -pin  "mux#7" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(16)} -pin  "mux#7" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(17)} -pin  "mux#7" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(18)} -pin  "mux#7" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(19)} -pin  "mux#7" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(20)} -pin  "mux#7" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(21)} -pin  "mux#7" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(22)} -pin  "mux#7" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(23)} -pin  "mux#7" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(24)} -pin  "mux#7" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(25)} -pin  "mux#7" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(26)} -pin  "mux#7" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(27)} -pin  "mux#7" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(28)} -pin  "mux#7" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load net {regs.regs(2).lpi#1.dfm#1:mx0(29)} -pin  "mux#7" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm#1:mx0}
+load inst "mux#8" "mux(2,90)" "INTERFACE" -attr xrf 34028 -attr oid 1192 -attr vt d -attr @path {/sobel/sobel:core/mux#8} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(1).sva(0)} -pin  "mux#8" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "mux#8" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "mux#8" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "mux#8" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "mux#8" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "mux#8" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "mux#8" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "mux#8" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "mux#8" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "mux#8" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "mux#8" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "mux#8" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "mux#8" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "mux#8" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "mux#8" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "mux#8" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "mux#8" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "mux#8" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "mux#8" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "mux#8" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "mux#8" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "mux#8" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "mux#8" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "mux#8" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "mux#8" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "mux#8" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "mux#8" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "mux#8" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "mux#8" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "mux#8" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "mux#8" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "mux#8" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "mux#8" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "mux#8" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "mux#8" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "mux#8" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "mux#8" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "mux#8" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "mux#8" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "mux#8" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "mux#8" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "mux#8" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "mux#8" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "mux#8" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "mux#8" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "mux#8" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "mux#8" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "mux#8" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "mux#8" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "mux#8" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "mux#8" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "mux#8" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "mux#8" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "mux#8" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "mux#8" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "mux#8" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "mux#8" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "mux#8" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "mux#8" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "mux#8" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "mux#8" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "mux#8" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "mux#8" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "mux#8" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "mux#8" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "mux#8" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "mux#8" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "mux#8" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "mux#8" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "mux#8" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "mux#8" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "mux#8" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "mux#8" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "mux#8" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "mux#8" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "mux#8" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "mux#8" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "mux#8" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "mux#8" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "mux#8" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "mux#8" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "mux#8" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "mux#8" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "mux#8" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "mux#8" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "mux#8" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "mux#8" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "mux#8" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "mux#8" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "mux#8" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -pin  "mux#8" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#8" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#8" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#8" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#8" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#8" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#8" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#8" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#8" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#8" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#8" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#8" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#8" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#8" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#8" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#8" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#8" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#8" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#8" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#8" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#8" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#8" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#8" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#8" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#8" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#8" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#8" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#8" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#8" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#8" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#8" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#8" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#8" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#8" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#8" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#8" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#8" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#8" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#8" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#8" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#8" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#8" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#8" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#8" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#8" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#8" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#8" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#8" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#8" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#8" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#8" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#8" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#8" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#8" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#8" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#8" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#8" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#8" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#8" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#8" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#8" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#8" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#8" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#8" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#8" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#8" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#8" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#8" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#8" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#8" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#8" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#8" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#8" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#8" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#8" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#8" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#8" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#8" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#8" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#8" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#8" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#8" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#8" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#8" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#8" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#8" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#8" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#8" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#8" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#8" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {and.cse} -pin  "mux#8" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "mux#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "mux#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "mux#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "mux#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "mux#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "mux#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "mux#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "mux#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "mux#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "mux#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "mux#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "mux#8" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "mux#8" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "mux#8" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "mux#8" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "mux#8" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "mux#8" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "mux#8" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "mux#8" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "mux#8" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "mux#8" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "mux#8" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "mux#8" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "mux#8" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "mux#8" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "mux#8" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "mux#8" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "mux#8" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "mux#8" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "mux#8" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "mux#8" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "mux#8" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "mux#8" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "mux#8" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "mux#8" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "mux#8" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "mux#8" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "mux#8" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "mux#8" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "mux#8" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "mux#8" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "mux#8" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "mux#8" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "mux#8" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "mux#8" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "mux#8" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "mux#8" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "mux#8" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "mux#8" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "mux#8" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "mux#8" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "mux#8" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "mux#8" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "mux#8" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "mux#8" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "mux#8" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "mux#8" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "mux#8" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "mux#8" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "mux#8" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "mux#8" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "mux#8" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "mux#8" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "mux#8" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "mux#8" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "mux#8" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "mux#8" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "mux#8" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "mux#8" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "mux#8" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "mux#8" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "mux#8" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "mux#8" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "mux#8" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "mux#8" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "mux#8" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "mux#8" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "mux#8" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "mux#8" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "mux#8" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "mux#8" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "mux#8" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "mux#8" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "mux#8" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "mux#8" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "mux#8" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "mux#8" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "mux#8" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "mux#8" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "mux#8" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load inst "mux#9" "mux(2,90)" "INTERFACE" -attr xrf 34029 -attr oid 1193 -attr vt d -attr @path {/sobel/sobel:core/mux#9} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(0).sva(0)} -pin  "mux#9" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#9" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#9" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#9" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#9" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#9" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#9" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#9" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#9" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#9" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#9" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#9" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#9" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#9" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#9" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#9" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#9" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#9" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#9" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#9" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#9" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#9" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#9" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#9" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#9" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#9" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#9" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#9" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#9" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#9" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#9" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#9" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#9" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#9" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#9" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#9" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#9" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#9" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#9" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#9" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#9" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#9" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#9" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#9" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#9" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#9" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#9" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#9" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#9" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#9" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#9" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#9" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#9" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#9" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#9" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#9" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#9" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#9" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#9" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#9" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#9" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#9" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#9" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#9" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#9" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#9" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#9" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#9" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#9" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#9" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#9" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#9" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#9" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#9" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#9" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#9" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#9" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#9" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#9" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#9" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#9" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#9" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#9" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#9" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#9" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#9" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#9" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#9" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#9" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#9" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "mux#9" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "mux#9" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "mux#9" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "mux#9" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "mux#9" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "mux#9" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "mux#9" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "mux#9" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "mux#9" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "mux#9" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "mux#9" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "mux#9" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "mux#9" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "mux#9" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "mux#9" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "mux#9" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "mux#9" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "mux#9" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "mux#9" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "mux#9" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "mux#9" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "mux#9" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "mux#9" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "mux#9" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "mux#9" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "mux#9" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "mux#9" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "mux#9" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "mux#9" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "mux#9" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "mux#9" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "mux#9" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "mux#9" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "mux#9" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "mux#9" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "mux#9" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "mux#9" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "mux#9" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "mux#9" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "mux#9" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "mux#9" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "mux#9" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "mux#9" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "mux#9" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "mux#9" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "mux#9" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "mux#9" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "mux#9" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "mux#9" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "mux#9" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "mux#9" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "mux#9" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "mux#9" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "mux#9" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "mux#9" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "mux#9" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "mux#9" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "mux#9" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "mux#9" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "mux#9" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "mux#9" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "mux#9" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "mux#9" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "mux#9" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "mux#9" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "mux#9" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "mux#9" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "mux#9" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "mux#9" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "mux#9" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "mux#9" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "mux#9" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "mux#9" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "mux#9" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "mux#9" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "mux#9" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "mux#9" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "mux#9" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "mux#9" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "mux#9" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "mux#9" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "mux#9" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "mux#9" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "mux#9" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "mux#9" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "mux#9" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "mux#9" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "mux#9" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "mux#9" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "mux#9" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {and.cse} -pin  "mux#9" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "mux#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "mux#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "mux#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "mux#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "mux#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "mux#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "mux#9" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "mux#9" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "mux#9" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "mux#9" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "mux#9" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "mux#9" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "mux#9" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "mux#9" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "mux#9" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "mux#9" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "mux#9" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "mux#9" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "mux#9" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "mux#9" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "mux#9" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "mux#9" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "mux#9" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "mux#9" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "mux#9" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "mux#9" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "mux#9" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "mux#9" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "mux#9" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "mux#9" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "mux#9" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "mux#9" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "mux#9" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "mux#9" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "mux#9" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "mux#9" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "mux#9" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "mux#9" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "mux#9" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "mux#9" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "mux#9" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "mux#9" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "mux#9" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "mux#9" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "mux#9" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "mux#9" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "mux#9" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "mux#9" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "mux#9" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "mux#9" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "mux#9" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "mux#9" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "mux#9" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "mux#9" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "mux#9" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "mux#9" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "mux#9" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "mux#9" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "mux#9" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "mux#9" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "mux#9" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "mux#9" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "mux#9" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "mux#9" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "mux#9" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "mux#9" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "mux#9" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "mux#9" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "mux#9" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "mux#9" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "mux#9" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "mux#9" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "mux#9" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "mux#9" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "mux#9" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "mux#9" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "mux#9" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "mux#9" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "mux#9" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "mux#9" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "mux#9" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "mux#9" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "mux#9" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "mux#9" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "mux#9" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "mux#9" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "mux#9" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "mux#9" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "mux#9" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "mux#9" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load inst "ACC1-3:not#57" "not(1)" "INTERFACE" -attr xrf 34030 -attr oid 1194 -attr @path {/sobel/sobel:core/ACC1-3:not#57} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#178.itm(2)} -pin  "ACC1-3:not#57" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#1.itm}
+load net {ACC1-3:not#57.itm} -pin  "ACC1-3:not#57" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#57.itm}
+load inst "ACC1-3:not#58" "not(1)" "INTERFACE" -attr xrf 34031 -attr oid 1195 -attr @path {/sobel/sobel:core/ACC1-3:not#58} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#178.itm(3)} -pin  "ACC1-3:not#58" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#2.itm}
+load net {ACC1-3:not#58.itm} -pin  "ACC1-3:not#58" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#58.itm}
+load inst "ACC1:acc#179" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 34032 -attr oid 1196 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#179" {A(0)} -attr @path {/sobel/sobel:core/conc#683.itm}
+load net {ACC1:acc#178.itm(1)} -pin  "ACC1:acc#179" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#683.itm}
+load net {PWR} -pin  "ACC1:acc#179" {A(2)} -attr @path {/sobel/sobel:core/conc#683.itm}
+load net {ACC1-3:not#58.itm} -pin  "ACC1:acc#179" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#531.itm}
+load net {ACC1-3:not#57.itm} -pin  "ACC1:acc#179" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#531.itm}
+load net {ACC1:acc#179.itm(0)} -pin  "ACC1:acc#179" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(1)} -pin  "ACC1:acc#179" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load net {ACC1:acc#179.itm(2)} -pin  "ACC1:acc#179" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#179.itm}
+load inst "mux#10" "mux(2,2)" "INTERFACE" -attr xrf 34033 -attr oid 1197 -attr vt d -attr @path {/sobel/sobel:core/mux#10} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {acc.imod#7.lpi#1.dfm(0)} -pin  "mux#10" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm}
+load net {acc.imod#7.lpi#1.dfm(1)} -pin  "mux#10" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm}
+load net {ACC1:acc#179.itm(1)} -pin  "mux#10" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#45.itm}
+load net {ACC1:acc#179.itm(2)} -pin  "mux#10" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#45.itm}
+load net {and.cse} -pin  "mux#10" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {acc.imod#7.lpi#1.dfm:mx0(0)} -pin  "mux#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm:mx0}
+load net {acc.imod#7.lpi#1.dfm:mx0(1)} -pin  "mux#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.lpi#1.dfm:mx0}
+load inst "mux#11" "mux(2,2)" "INTERFACE" -attr xrf 34034 -attr oid 1198 -attr vt d -attr @path {/sobel/sobel:core/mux#11} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {acc.imod#6.lpi#1.dfm.sg1(0)} -pin  "mux#11" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1}
+load net {acc.imod#6.lpi#1.dfm.sg1(1)} -pin  "mux#11" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1}
+load net {ACC1:acc#178.itm(2)} -pin  "mux#11" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#3.itm}
+load net {ACC1:acc#178.itm(3)} -pin  "mux#11" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#6.sva)#3.itm}
+load net {and.cse} -pin  "mux#11" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(0)} -pin  "mux#11" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1:mx0}
+load net {acc.imod#6.lpi#1.dfm.sg1:mx0(1)} -pin  "mux#11" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#6.lpi#1.dfm.sg1:mx0}
+load inst "ACC1-1:not#147" "not(2)" "INTERFACE" -attr xrf 34035 -attr oid 1199 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#147} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#118.psp#1.sva(1)} -pin  "ACC1-1:not#147" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp#1.sva).itm}
+load net {ACC1:acc#118.psp#1.sva(2)} -pin  "ACC1-1:not#147" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp#1.sva).itm}
+load net {ACC1-1:not#147.itm(0)} -pin  "ACC1-1:not#147" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#147.itm}
+load net {ACC1-1:not#147.itm(1)} -pin  "ACC1-1:not#147" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#147.itm}
+load inst "ACC1:acc#150" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 34036 -attr oid 1200 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#150" {A(0)} -attr @path {/sobel/sobel:core/conc#684.itm}
+load net {ACC1-1:not#147.itm(0)} -pin  "ACC1:acc#150" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#684.itm}
+load net {ACC1-1:not#147.itm(1)} -pin  "ACC1:acc#150" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#684.itm}
+load net {PWR} -pin  "ACC1:acc#150" {B(0)} -attr @path {/sobel/sobel:core/conc#685.itm}
+load net {ACC1:acc#118.psp#1.sva(0)} -pin  "ACC1:acc#150" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#685.itm}
+load net {ACC1:acc#150.itm(0)} -pin  "ACC1:acc#150" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load net {ACC1:acc#150.itm(1)} -pin  "ACC1:acc#150" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load net {ACC1:acc#150.itm(2)} -pin  "ACC1:acc#150" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load net {ACC1:acc#150.itm(3)} -pin  "ACC1:acc#150" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#150.itm}
+load inst "ACC1-1:not#137" "not(1)" "INTERFACE" -attr xrf 34037 -attr oid 1201 -attr @path {/sobel/sobel:core/ACC1-1:not#137} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#148.itm(2)} -pin  "ACC1-1:not#137" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.sva)#2.itm}
+load net {ACC1-1:not#137.itm} -pin  "ACC1-1:not#137" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#137.itm}
+load inst "ACC1:acc#149" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34038 -attr oid 1202 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#149" {A(0)} -attr @path {/sobel/sobel:core/conc#686.itm}
+load net {ACC1:acc#148.itm(1)} -pin  "ACC1:acc#149" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#686.itm}
+load net {ACC1:acc#148.itm(3)} -pin  "ACC1:acc#149" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#472.itm}
+load net {ACC1-1:not#137.itm} -pin  "ACC1:acc#149" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#472.itm}
+load net {ACC1:acc#149.itm(0)} -pin  "ACC1:acc#149" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149.itm}
+load net {ACC1:acc#149.itm(1)} -pin  "ACC1:acc#149" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149.itm}
+load net {ACC1:acc#149.itm(2)} -pin  "ACC1:acc#149" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#149.itm}
+load inst "ACC1-1:not#154" "not(1)" "INTERFACE" -attr xrf 34039 -attr oid 1203 -attr @path {/sobel/sobel:core/ACC1-1:not#154} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#148.itm(4)} -pin  "ACC1-1:not#154" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.sva)#4.itm}
+load net {ACC1-1:not#154.itm} -pin  "ACC1-1:not#154" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#154.itm}
+load inst "ACC1-1:acc#118" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 34040 -attr oid 1204 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#118} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#149.itm(1)} -pin  "ACC1-1:acc#118" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#19.itm}
+load net {ACC1:acc#149.itm(2)} -pin  "ACC1-1:acc#118" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#19.itm}
+load net {ACC1-1:not#154.itm} -pin  "ACC1-1:acc#118" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#154.itm}
+load net {ACC1:acc#118.psp#1.sva(0)} -pin  "ACC1-1:acc#118" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.sva}
+load net {ACC1:acc#118.psp#1.sva(1)} -pin  "ACC1-1:acc#118" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.sva}
+load net {ACC1:acc#118.psp#1.sva(2)} -pin  "ACC1-1:acc#118" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.sva}
+load inst "ACC1-1:not#115" "not(1)" "INTERFACE" -attr xrf 34041 -attr oid 1205 -attr @path {/sobel/sobel:core/ACC1-1:not#115} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp#1.sva(0)} -pin  "ACC1-1:not#115" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva).itm}
+load net {ACC1-1:not#115.itm} -pin  "ACC1-1:not#115" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#115.itm}
+load inst "ACC1-1:not#116" "not(1)" "INTERFACE" -attr xrf 34042 -attr oid 1206 -attr @path {/sobel/sobel:core/ACC1-1:not#116} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp#1.sva(2)} -pin  "ACC1-1:not#116" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#2.itm}
+load net {ACC1-1:not#116.itm} -pin  "ACC1-1:not#116" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#116.itm}
+load inst "ACC1-1:not#118" "not(1)" "INTERFACE" -attr xrf 34043 -attr oid 1207 -attr @path {/sobel/sobel:core/ACC1-1:not#118} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp#1.sva(6)} -pin  "ACC1-1:not#118" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#3.itm}
+load net {ACC1-1:not#118.itm} -pin  "ACC1-1:not#118" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#118.itm}
+load inst "ACC1:acc#145" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34044 -attr oid 1208 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#145" {A(0)} -attr @path {/sobel/sobel:core/conc#689.itm}
+load net {ACC1:acc#125.psp#1.sva(1)} -pin  "ACC1:acc#145" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#689.itm}
+load net {ACC1-1:not#118.itm} -pin  "ACC1:acc#145" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#464.itm}
+load net {ACC1-1:not#116.itm} -pin  "ACC1:acc#145" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#464.itm}
+load net {ACC1:acc#145.itm(0)} -pin  "ACC1:acc#145" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145.itm}
+load net {ACC1:acc#145.itm(1)} -pin  "ACC1:acc#145" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145.itm}
+load net {ACC1:acc#145.itm(2)} -pin  "ACC1:acc#145" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#145.itm}
+load inst "ACC1-1:not#119" "not(1)" "INTERFACE" -attr xrf 34045 -attr oid 1209 -attr @path {/sobel/sobel:core/ACC1-1:not#119} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp#1.sva(8)} -pin  "ACC1-1:not#119" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#4.itm}
+load net {ACC1-1:not#119.itm} -pin  "ACC1-1:not#119" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#119.itm}
+load inst "ACC1:acc#147" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 34046 -attr oid 1210 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#147" {A(0)} -attr @path {/sobel/sobel:core/conc#688.itm}
+load net {ACC1-1:not#115.itm} -pin  "ACC1:acc#147" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#688.itm}
+load net {GND} -pin  "ACC1:acc#147" {A(2)} -attr @path {/sobel/sobel:core/conc#688.itm}
+load net {PWR} -pin  "ACC1:acc#147" {A(3)} -attr @path {/sobel/sobel:core/conc#688.itm}
+load net {ACC1-1:not#119.itm} -pin  "ACC1:acc#147" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#468.itm}
+load net {ACC1:acc#145.itm(1)} -pin  "ACC1:acc#147" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#468.itm}
+load net {ACC1:acc#145.itm(2)} -pin  "ACC1:acc#147" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#468.itm}
+load net {ACC1:acc#147.itm(0)} -pin  "ACC1:acc#147" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load net {ACC1:acc#147.itm(1)} -pin  "ACC1:acc#147" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load net {ACC1:acc#147.itm(2)} -pin  "ACC1:acc#147" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load net {ACC1:acc#147.itm(3)} -pin  "ACC1:acc#147" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#147.itm}
+load inst "ACC1-1:not#117" "not(1)" "INTERFACE" -attr xrf 34047 -attr oid 1211 -attr @path {/sobel/sobel:core/ACC1-1:not#117} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp#1.sva(4)} -pin  "ACC1-1:not#117" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#6.itm}
+load net {ACC1-1:not#117.itm} -pin  "ACC1-1:not#117" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#117.itm}
+load inst "ACC1:acc#144" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34048 -attr oid 1212 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#144" {A(0)} -attr @path {/sobel/sobel:core/conc#691.itm}
+load net {ACC1:acc#125.psp#1.sva(3)} -pin  "ACC1:acc#144" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#691.itm}
+load net {ACC1:acc#125.psp#1.sva(5)} -pin  "ACC1:acc#144" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#462.itm}
+load net {ACC1-1:not#117.itm} -pin  "ACC1:acc#144" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#462.itm}
+load net {ACC1:acc#144.itm(0)} -pin  "ACC1:acc#144" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144.itm}
+load net {ACC1:acc#144.itm(1)} -pin  "ACC1:acc#144" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144.itm}
+load net {ACC1:acc#144.itm(2)} -pin  "ACC1:acc#144" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#144.itm}
+load inst "ACC1-1:not#120" "not(2)" "INTERFACE" -attr xrf 34049 -attr oid 1213 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#120} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#125.psp#1.sva(10)} -pin  "ACC1-1:not#120" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#8.itm}
+load net {ACC1:acc#125.psp#1.sva(11)} -pin  "ACC1-1:not#120" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp#1.sva)#8.itm}
+load net {ACC1-1:not#120.itm(0)} -pin  "ACC1-1:not#120" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#120.itm}
+load net {ACC1-1:not#120.itm(1)} -pin  "ACC1-1:not#120" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#120.itm}
+load inst "ACC1:acc#146" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 34050 -attr oid 1214 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#146" {A(0)} -attr @path {/sobel/sobel:core/conc#690.itm}
+load net {ACC1:acc#144.itm(1)} -pin  "ACC1:acc#146" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#690.itm}
+load net {ACC1:acc#144.itm(2)} -pin  "ACC1:acc#146" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#690.itm}
+load net {ACC1:acc#125.psp#1.sva(7)} -pin  "ACC1:acc#146" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#466.itm}
+load net {ACC1-1:not#120.itm(0)} -pin  "ACC1:acc#146" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#466.itm}
+load net {ACC1-1:not#120.itm(1)} -pin  "ACC1:acc#146" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#466.itm}
+load net {ACC1:acc#146.itm(0)} -pin  "ACC1:acc#146" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {ACC1:acc#146.itm(1)} -pin  "ACC1:acc#146" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {ACC1:acc#146.itm(2)} -pin  "ACC1:acc#146" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {ACC1:acc#146.itm(3)} -pin  "ACC1:acc#146" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load net {ACC1:acc#146.itm(4)} -pin  "ACC1:acc#146" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#146.itm}
+load inst "ACC1:acc#148" "add(4,1,5,-1,5)" "INTERFACE" -attr xrf 34051 -attr oid 1215 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "ACC1:acc#148" {A(0)} -attr @path {/sobel/sobel:core/conc#687.itm}
+load net {ACC1:acc#147.itm(1)} -pin  "ACC1:acc#148" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#687.itm}
+load net {ACC1:acc#147.itm(2)} -pin  "ACC1:acc#148" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#687.itm}
+load net {ACC1:acc#147.itm(3)} -pin  "ACC1:acc#148" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#687.itm}
+load net {ACC1:acc#125.psp#1.sva(9)} -pin  "ACC1:acc#148" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#470.itm}
+load net {ACC1:acc#146.itm(1)} -pin  "ACC1:acc#148" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#470.itm}
+load net {ACC1:acc#146.itm(2)} -pin  "ACC1:acc#148" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#470.itm}
+load net {ACC1:acc#146.itm(3)} -pin  "ACC1:acc#148" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#470.itm}
+load net {ACC1:acc#146.itm(4)} -pin  "ACC1:acc#148" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#470.itm}
+load net {ACC1:acc#148.itm(0)} -pin  "ACC1:acc#148" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {ACC1:acc#148.itm(1)} -pin  "ACC1:acc#148" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {ACC1:acc#148.itm(2)} -pin  "ACC1:acc#148" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {ACC1:acc#148.itm(3)} -pin  "ACC1:acc#148" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load net {ACC1:acc#148.itm(4)} -pin  "ACC1:acc#148" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#148.itm}
+load inst "ACC1:not#158" "not(10)" "INTERFACE" -attr xrf 34052 -attr oid 1216 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "ACC1:not#158" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "ACC1:not#158" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "ACC1:not#158" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "ACC1:not#158" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "ACC1:not#158" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "ACC1:not#158" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "ACC1:not#158" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "ACC1:not#158" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "ACC1:not#158" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "ACC1:not#158" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#4).itm}
+load net {ACC1:not#158.itm(0)} -pin  "ACC1:not#158" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(1)} -pin  "ACC1:not#158" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(2)} -pin  "ACC1:not#158" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(3)} -pin  "ACC1:not#158" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(4)} -pin  "ACC1:not#158" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(5)} -pin  "ACC1:not#158" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(6)} -pin  "ACC1:not#158" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(7)} -pin  "ACC1:not#158" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(8)} -pin  "ACC1:not#158" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(9)} -pin  "ACC1:not#158" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load inst "ACC1:not#159" "not(10)" "INTERFACE" -attr xrf 34053 -attr oid 1217 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "ACC1:not#159" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "ACC1:not#159" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "ACC1:not#159" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "ACC1:not#159" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "ACC1:not#159" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "ACC1:not#159" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "ACC1:not#159" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "ACC1:not#159" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "ACC1:not#159" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "ACC1:not#159" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#5).itm}
+load net {ACC1:not#159.itm(0)} -pin  "ACC1:not#159" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(1)} -pin  "ACC1:not#159" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(2)} -pin  "ACC1:not#159" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(3)} -pin  "ACC1:not#159" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(4)} -pin  "ACC1:not#159" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(5)} -pin  "ACC1:not#159" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(6)} -pin  "ACC1:not#159" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(7)} -pin  "ACC1:not#159" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(8)} -pin  "ACC1:not#159" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(9)} -pin  "ACC1:not#159" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load inst "ACC1:acc#143" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 34054 -attr oid 1218 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#158.itm(0)} -pin  "ACC1:acc#143" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(1)} -pin  "ACC1:acc#143" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(2)} -pin  "ACC1:acc#143" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(3)} -pin  "ACC1:acc#143" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(4)} -pin  "ACC1:acc#143" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(5)} -pin  "ACC1:acc#143" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(6)} -pin  "ACC1:acc#143" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(7)} -pin  "ACC1:acc#143" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(8)} -pin  "ACC1:acc#143" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#158.itm(9)} -pin  "ACC1:acc#143" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#158.itm}
+load net {ACC1:not#159.itm(0)} -pin  "ACC1:acc#143" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(1)} -pin  "ACC1:acc#143" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(2)} -pin  "ACC1:acc#143" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(3)} -pin  "ACC1:acc#143" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(4)} -pin  "ACC1:acc#143" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(5)} -pin  "ACC1:acc#143" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(6)} -pin  "ACC1:acc#143" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(7)} -pin  "ACC1:acc#143" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(8)} -pin  "ACC1:acc#143" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:not#159.itm(9)} -pin  "ACC1:acc#143" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#159.itm}
+load net {ACC1:acc#143.itm(0)} -pin  "ACC1:acc#143" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(1)} -pin  "ACC1:acc#143" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(2)} -pin  "ACC1:acc#143" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(3)} -pin  "ACC1:acc#143" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(4)} -pin  "ACC1:acc#143" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(5)} -pin  "ACC1:acc#143" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(6)} -pin  "ACC1:acc#143" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(7)} -pin  "ACC1:acc#143" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(8)} -pin  "ACC1:acc#143" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(9)} -pin  "ACC1:acc#143" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(10)} -pin  "ACC1:acc#143" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load inst "ACC1:not#160" "not(10)" "INTERFACE" -attr xrf 34055 -attr oid 1219 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "ACC1:not#160" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "ACC1:not#160" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "ACC1:not#160" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "ACC1:not#160" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "ACC1:not#160" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "ACC1:not#160" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "ACC1:not#160" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "ACC1:not#160" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "ACC1:not#160" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "ACC1:not#160" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#6).itm}
+load net {ACC1:not#160.itm(0)} -pin  "ACC1:not#160" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(1)} -pin  "ACC1:not#160" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(2)} -pin  "ACC1:not#160" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(3)} -pin  "ACC1:not#160" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(4)} -pin  "ACC1:not#160" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(5)} -pin  "ACC1:not#160" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(6)} -pin  "ACC1:not#160" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(7)} -pin  "ACC1:not#160" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(8)} -pin  "ACC1:not#160" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(9)} -pin  "ACC1:not#160" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load inst "ACC1:acc#142" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 34056 -attr oid 1220 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#160.itm(0)} -pin  "ACC1:acc#142" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(1)} -pin  "ACC1:acc#142" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(2)} -pin  "ACC1:acc#142" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(3)} -pin  "ACC1:acc#142" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(4)} -pin  "ACC1:acc#142" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(5)} -pin  "ACC1:acc#142" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(6)} -pin  "ACC1:acc#142" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(7)} -pin  "ACC1:acc#142" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(8)} -pin  "ACC1:acc#142" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {ACC1:not#160.itm(9)} -pin  "ACC1:acc#142" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#160.itm}
+load net {PWR} -pin  "ACC1:acc#142" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#142" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#142.itm(0)} -pin  "ACC1:acc#142" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(1)} -pin  "ACC1:acc#142" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(2)} -pin  "ACC1:acc#142" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(3)} -pin  "ACC1:acc#142" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(4)} -pin  "ACC1:acc#142" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(5)} -pin  "ACC1:acc#142" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(6)} -pin  "ACC1:acc#142" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(7)} -pin  "ACC1:acc#142" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(8)} -pin  "ACC1:acc#142" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(9)} -pin  "ACC1:acc#142" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(10)} -pin  "ACC1:acc#142" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load inst "ACC1-1:acc#125" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 34057 -attr oid 1221 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#125} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#143.itm(0)} -pin  "ACC1-1:acc#125" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(1)} -pin  "ACC1-1:acc#125" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(2)} -pin  "ACC1-1:acc#125" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(3)} -pin  "ACC1-1:acc#125" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(4)} -pin  "ACC1-1:acc#125" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(5)} -pin  "ACC1-1:acc#125" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(6)} -pin  "ACC1-1:acc#125" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(7)} -pin  "ACC1-1:acc#125" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(8)} -pin  "ACC1-1:acc#125" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(9)} -pin  "ACC1-1:acc#125" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#143.itm(10)} -pin  "ACC1-1:acc#125" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#143.itm}
+load net {ACC1:acc#142.itm(0)} -pin  "ACC1-1:acc#125" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(1)} -pin  "ACC1-1:acc#125" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(2)} -pin  "ACC1-1:acc#125" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(3)} -pin  "ACC1-1:acc#125" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(4)} -pin  "ACC1-1:acc#125" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(5)} -pin  "ACC1-1:acc#125" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(6)} -pin  "ACC1-1:acc#125" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(7)} -pin  "ACC1-1:acc#125" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(8)} -pin  "ACC1-1:acc#125" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(9)} -pin  "ACC1-1:acc#125" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#142.itm(10)} -pin  "ACC1-1:acc#125" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#142.itm}
+load net {ACC1:acc#125.psp#1.sva(0)} -pin  "ACC1-1:acc#125" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(1)} -pin  "ACC1-1:acc#125" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(2)} -pin  "ACC1-1:acc#125" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(3)} -pin  "ACC1-1:acc#125" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(4)} -pin  "ACC1-1:acc#125" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(5)} -pin  "ACC1-1:acc#125" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(6)} -pin  "ACC1-1:acc#125" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(7)} -pin  "ACC1-1:acc#125" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(8)} -pin  "ACC1-1:acc#125" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(9)} -pin  "ACC1-1:acc#125" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(10)} -pin  "ACC1-1:acc#125" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(11)} -pin  "ACC1-1:acc#125" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load inst "ACC1-3:not#115" "not(1)" "INTERFACE" -attr xrf 34058 -attr oid 1222 -attr @path {/sobel/sobel:core/ACC1-3:not#115} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp.sva(0)} -pin  "ACC1-3:not#115" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva).itm}
+load net {ACC1-3:not#115.itm} -pin  "ACC1-3:not#115" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#115.itm}
+load inst "ACC1-3:not#116" "not(1)" "INTERFACE" -attr xrf 34059 -attr oid 1223 -attr @path {/sobel/sobel:core/ACC1-3:not#116} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp.sva(2)} -pin  "ACC1-3:not#116" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#2.itm}
+load net {ACC1-3:not#116.itm} -pin  "ACC1-3:not#116" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#116.itm}
+load inst "ACC1-3:not#118" "not(1)" "INTERFACE" -attr xrf 34060 -attr oid 1224 -attr @path {/sobel/sobel:core/ACC1-3:not#118} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp.sva(6)} -pin  "ACC1-3:not#118" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#3.itm}
+load net {ACC1-3:not#118.itm} -pin  "ACC1-3:not#118" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#118.itm}
+load inst "ACC1:acc#173" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34061 -attr oid 1225 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#173" {A(0)} -attr @path {/sobel/sobel:core/conc#694.itm}
+load net {ACC1:acc#125.psp.sva(1)} -pin  "ACC1:acc#173" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#694.itm}
+load net {ACC1-3:not#118.itm} -pin  "ACC1:acc#173" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#518.itm}
+load net {ACC1-3:not#116.itm} -pin  "ACC1:acc#173" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#518.itm}
+load net {ACC1:acc#173.itm(0)} -pin  "ACC1:acc#173" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load net {ACC1:acc#173.itm(1)} -pin  "ACC1:acc#173" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load net {ACC1:acc#173.itm(2)} -pin  "ACC1:acc#173" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#173.itm}
+load inst "ACC1-3:not#119" "not(1)" "INTERFACE" -attr xrf 34062 -attr oid 1226 -attr @path {/sobel/sobel:core/ACC1-3:not#119} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp.sva(8)} -pin  "ACC1-3:not#119" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#4.itm}
+load net {ACC1-3:not#119.itm} -pin  "ACC1-3:not#119" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#119.itm}
+load inst "ACC1:acc#175" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 34063 -attr oid 1227 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {PWR} -pin  "ACC1:acc#175" {A(0)} -attr @path {/sobel/sobel:core/conc#693.itm}
+load net {ACC1-3:not#115.itm} -pin  "ACC1:acc#175" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#693.itm}
+load net {GND} -pin  "ACC1:acc#175" {A(2)} -attr @path {/sobel/sobel:core/conc#693.itm}
+load net {PWR} -pin  "ACC1:acc#175" {A(3)} -attr @path {/sobel/sobel:core/conc#693.itm}
+load net {ACC1-3:not#119.itm} -pin  "ACC1:acc#175" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#522.itm}
+load net {ACC1:acc#173.itm(1)} -pin  "ACC1:acc#175" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#522.itm}
+load net {ACC1:acc#173.itm(2)} -pin  "ACC1:acc#175" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#522.itm}
+load net {ACC1:acc#175.itm(0)} -pin  "ACC1:acc#175" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load net {ACC1:acc#175.itm(1)} -pin  "ACC1:acc#175" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load net {ACC1:acc#175.itm(2)} -pin  "ACC1:acc#175" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load net {ACC1:acc#175.itm(3)} -pin  "ACC1:acc#175" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#175.itm}
+load inst "ACC1-3:not#117" "not(1)" "INTERFACE" -attr xrf 34064 -attr oid 1228 -attr @path {/sobel/sobel:core/ACC1-3:not#117} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#125.psp.sva(4)} -pin  "ACC1-3:not#117" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#6.itm}
+load net {ACC1-3:not#117.itm} -pin  "ACC1-3:not#117" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#117.itm}
+load inst "ACC1:acc#172" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34065 -attr oid 1229 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#172" {A(0)} -attr @path {/sobel/sobel:core/conc#696.itm}
+load net {ACC1:acc#125.psp.sva(3)} -pin  "ACC1:acc#172" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#696.itm}
+load net {ACC1:acc#125.psp.sva(5)} -pin  "ACC1:acc#172" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#516.itm}
+load net {ACC1-3:not#117.itm} -pin  "ACC1:acc#172" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#516.itm}
+load net {ACC1:acc#172.itm(0)} -pin  "ACC1:acc#172" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load net {ACC1:acc#172.itm(1)} -pin  "ACC1:acc#172" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load net {ACC1:acc#172.itm(2)} -pin  "ACC1:acc#172" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#172.itm}
+load inst "ACC1-3:not#120" "not(2)" "INTERFACE" -attr xrf 34066 -attr oid 1230 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#120} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#125.psp.sva(10)} -pin  "ACC1-3:not#120" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#8.itm}
+load net {ACC1:acc#125.psp.sva(11)} -pin  "ACC1-3:not#120" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#125.psp.sva)#8.itm}
+load net {ACC1-3:not#120.itm(0)} -pin  "ACC1-3:not#120" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#120.itm}
+load net {ACC1-3:not#120.itm(1)} -pin  "ACC1-3:not#120" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#120.itm}
+load inst "ACC1:acc#174" "add(3,0,3,1,5)" "INTERFACE" -attr xrf 34067 -attr oid 1231 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#174" {A(0)} -attr @path {/sobel/sobel:core/conc#695.itm}
+load net {ACC1:acc#172.itm(1)} -pin  "ACC1:acc#174" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#695.itm}
+load net {ACC1:acc#172.itm(2)} -pin  "ACC1:acc#174" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#695.itm}
+load net {ACC1:acc#125.psp.sva(7)} -pin  "ACC1:acc#174" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#520.itm}
+load net {ACC1-3:not#120.itm(0)} -pin  "ACC1:acc#174" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#520.itm}
+load net {ACC1-3:not#120.itm(1)} -pin  "ACC1:acc#174" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#520.itm}
+load net {ACC1:acc#174.itm(0)} -pin  "ACC1:acc#174" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {ACC1:acc#174.itm(1)} -pin  "ACC1:acc#174" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {ACC1:acc#174.itm(2)} -pin  "ACC1:acc#174" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {ACC1:acc#174.itm(3)} -pin  "ACC1:acc#174" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load net {ACC1:acc#174.itm(4)} -pin  "ACC1:acc#174" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#174.itm}
+load inst "ACC1:acc#176" "add(4,1,5,-1,5)" "INTERFACE" -attr xrf 34068 -attr oid 1232 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176} -attr area 6.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,1,7)"
+load net {PWR} -pin  "ACC1:acc#176" {A(0)} -attr @path {/sobel/sobel:core/conc#692.itm}
+load net {ACC1:acc#175.itm(1)} -pin  "ACC1:acc#176" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#692.itm}
+load net {ACC1:acc#175.itm(2)} -pin  "ACC1:acc#176" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#692.itm}
+load net {ACC1:acc#175.itm(3)} -pin  "ACC1:acc#176" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#692.itm}
+load net {ACC1:acc#125.psp.sva(9)} -pin  "ACC1:acc#176" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#524.itm}
+load net {ACC1:acc#174.itm(1)} -pin  "ACC1:acc#176" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#524.itm}
+load net {ACC1:acc#174.itm(2)} -pin  "ACC1:acc#176" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#524.itm}
+load net {ACC1:acc#174.itm(3)} -pin  "ACC1:acc#176" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#524.itm}
+load net {ACC1:acc#174.itm(4)} -pin  "ACC1:acc#176" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#524.itm}
+load net {ACC1:acc#176.itm(0)} -pin  "ACC1:acc#176" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {ACC1:acc#176.itm(1)} -pin  "ACC1:acc#176" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {ACC1:acc#176.itm(2)} -pin  "ACC1:acc#176" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {ACC1:acc#176.itm(3)} -pin  "ACC1:acc#176" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load net {ACC1:acc#176.itm(4)} -pin  "ACC1:acc#176" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#176.itm}
+load inst "ACC1:acc#171" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 34069 -attr oid 1233 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.regs(1).sva(40)} -pin  "ACC1:acc#171" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(41)} -pin  "ACC1:acc#171" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(42)} -pin  "ACC1:acc#171" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(43)} -pin  "ACC1:acc#171" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(44)} -pin  "ACC1:acc#171" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(45)} -pin  "ACC1:acc#171" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(46)} -pin  "ACC1:acc#171" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(47)} -pin  "ACC1:acc#171" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(48)} -pin  "ACC1:acc#171" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(49)} -pin  "ACC1:acc#171" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(30)} -pin  "ACC1:acc#171" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(31)} -pin  "ACC1:acc#171" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(32)} -pin  "ACC1:acc#171" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(33)} -pin  "ACC1:acc#171" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(34)} -pin  "ACC1:acc#171" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(35)} -pin  "ACC1:acc#171" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(36)} -pin  "ACC1:acc#171" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(37)} -pin  "ACC1:acc#171" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(38)} -pin  "ACC1:acc#171" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {regs.regs(1).sva(39)} -pin  "ACC1:acc#171" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#6.itm}
+load net {ACC1:acc#171.itm(0)} -pin  "ACC1:acc#171" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(1)} -pin  "ACC1:acc#171" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(2)} -pin  "ACC1:acc#171" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(3)} -pin  "ACC1:acc#171" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(4)} -pin  "ACC1:acc#171" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(5)} -pin  "ACC1:acc#171" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(6)} -pin  "ACC1:acc#171" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(7)} -pin  "ACC1:acc#171" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(8)} -pin  "ACC1:acc#171" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(9)} -pin  "ACC1:acc#171" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(10)} -pin  "ACC1:acc#171" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load inst "ACC1-3:acc#125" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 34070 -attr oid 1234 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#125} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#171.itm(0)} -pin  "ACC1-3:acc#125" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(1)} -pin  "ACC1-3:acc#125" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(2)} -pin  "ACC1-3:acc#125" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(3)} -pin  "ACC1-3:acc#125" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(4)} -pin  "ACC1-3:acc#125" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(5)} -pin  "ACC1-3:acc#125" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(6)} -pin  "ACC1-3:acc#125" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(7)} -pin  "ACC1-3:acc#125" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(8)} -pin  "ACC1-3:acc#125" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(9)} -pin  "ACC1-3:acc#125" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {ACC1:acc#171.itm(10)} -pin  "ACC1-3:acc#125" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#171.itm}
+load net {regs.regs(1).sva(50)} -pin  "ACC1-3:acc#125" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(51)} -pin  "ACC1-3:acc#125" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(52)} -pin  "ACC1-3:acc#125" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(53)} -pin  "ACC1-3:acc#125" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(54)} -pin  "ACC1-3:acc#125" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(55)} -pin  "ACC1-3:acc#125" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(56)} -pin  "ACC1-3:acc#125" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(57)} -pin  "ACC1-3:acc#125" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(58)} -pin  "ACC1-3:acc#125" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {regs.regs(1).sva(59)} -pin  "ACC1-3:acc#125" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#7.itm}
+load net {ACC1:acc#125.psp.sva(0)} -pin  "ACC1-3:acc#125" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(1)} -pin  "ACC1-3:acc#125" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(2)} -pin  "ACC1-3:acc#125" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(3)} -pin  "ACC1-3:acc#125" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(4)} -pin  "ACC1-3:acc#125" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(5)} -pin  "ACC1-3:acc#125" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(6)} -pin  "ACC1-3:acc#125" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(7)} -pin  "ACC1-3:acc#125" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(8)} -pin  "ACC1-3:acc#125" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(9)} -pin  "ACC1-3:acc#125" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(10)} -pin  "ACC1-3:acc#125" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load net {ACC1:acc#125.psp.sva(11)} -pin  "ACC1-3:acc#125" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp.sva}
+load inst "ACC1-3:not#137" "not(1)" "INTERFACE" -attr xrf 34071 -attr oid 1235 -attr @path {/sobel/sobel:core/ACC1-3:not#137} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#176.itm(2)} -pin  "ACC1-3:not#137" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.sva)#2.itm}
+load net {ACC1-3:not#137.itm} -pin  "ACC1-3:not#137" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#137.itm}
+load inst "ACC1:acc#177" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34072 -attr oid 1236 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#177" {A(0)} -attr @path {/sobel/sobel:core/conc#697.itm}
+load net {ACC1:acc#176.itm(1)} -pin  "ACC1:acc#177" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#697.itm}
+load net {ACC1:acc#176.itm(3)} -pin  "ACC1:acc#177" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#526.itm}
+load net {ACC1-3:not#137.itm} -pin  "ACC1:acc#177" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#526.itm}
+load net {ACC1:acc#177.itm(0)} -pin  "ACC1:acc#177" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(1)} -pin  "ACC1:acc#177" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load net {ACC1:acc#177.itm(2)} -pin  "ACC1:acc#177" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#177.itm}
+load inst "ACC1-3:not#154" "not(1)" "INTERFACE" -attr xrf 34073 -attr oid 1237 -attr @path {/sobel/sobel:core/ACC1-3:not#154} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#176.itm(4)} -pin  "ACC1-3:not#154" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#1.sva)#4.itm}
+load net {ACC1-3:not#154.itm} -pin  "ACC1-3:not#154" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#154.itm}
+load inst "ACC1-3:acc#118" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 34074 -attr oid 1238 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#118} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#177.itm(1)} -pin  "ACC1-3:acc#118" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#43.itm}
+load net {ACC1:acc#177.itm(2)} -pin  "ACC1-3:acc#118" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#43.itm}
+load net {ACC1-3:not#154.itm} -pin  "ACC1-3:acc#118" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#154.itm}
+load net {ACC1:acc#118.psp.sva(0)} -pin  "ACC1-3:acc#118" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.sva}
+load net {ACC1:acc#118.psp.sva(1)} -pin  "ACC1-3:acc#118" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.sva}
+load net {ACC1:acc#118.psp.sva(2)} -pin  "ACC1-3:acc#118" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp.sva}
+load inst "ACC1-3:not#147" "not(2)" "INTERFACE" -attr xrf 34075 -attr oid 1239 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#147} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#118.psp.sva(1)} -pin  "ACC1-3:not#147" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp.sva)#2.itm}
+load net {ACC1:acc#118.psp.sva(2)} -pin  "ACC1-3:not#147" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp.sva)#2.itm}
+load net {ACC1-3:not#147.itm(0)} -pin  "ACC1-3:not#147" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#147.itm}
+load net {ACC1-3:not#147.itm(1)} -pin  "ACC1-3:not#147" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#147.itm}
+load inst "ACC1:acc#178" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 34076 -attr oid 1240 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#178" {A(0)} -attr @path {/sobel/sobel:core/conc#698.itm}
+load net {ACC1-3:not#147.itm(0)} -pin  "ACC1:acc#178" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#698.itm}
+load net {ACC1-3:not#147.itm(1)} -pin  "ACC1:acc#178" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#698.itm}
+load net {PWR} -pin  "ACC1:acc#178" {B(0)} -attr @path {/sobel/sobel:core/conc#699.itm}
+load net {ACC1:acc#118.psp.sva(0)} -pin  "ACC1:acc#178" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#699.itm}
+load net {ACC1:acc#178.itm(0)} -pin  "ACC1:acc#178" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(1)} -pin  "ACC1:acc#178" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(2)} -pin  "ACC1:acc#178" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load net {ACC1:acc#178.itm(3)} -pin  "ACC1:acc#178" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#178.itm}
+load inst "ACC1:acc#180" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 34077 -attr oid 1241 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.regs(1).sva(70)} -pin  "ACC1:acc#180" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(71)} -pin  "ACC1:acc#180" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(72)} -pin  "ACC1:acc#180" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(73)} -pin  "ACC1:acc#180" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(74)} -pin  "ACC1:acc#180" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(75)} -pin  "ACC1:acc#180" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(76)} -pin  "ACC1:acc#180" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(77)} -pin  "ACC1:acc#180" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(78)} -pin  "ACC1:acc#180" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(79)} -pin  "ACC1:acc#180" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(60)} -pin  "ACC1:acc#180" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(61)} -pin  "ACC1:acc#180" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(62)} -pin  "ACC1:acc#180" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(63)} -pin  "ACC1:acc#180" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(64)} -pin  "ACC1:acc#180" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(65)} -pin  "ACC1:acc#180" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(66)} -pin  "ACC1:acc#180" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(67)} -pin  "ACC1:acc#180" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(68)} -pin  "ACC1:acc#180" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(69)} -pin  "ACC1:acc#180" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {ACC1:acc#180.itm(0)} -pin  "ACC1:acc#180" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(1)} -pin  "ACC1:acc#180" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(2)} -pin  "ACC1:acc#180" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(3)} -pin  "ACC1:acc#180" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(4)} -pin  "ACC1:acc#180" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(5)} -pin  "ACC1:acc#180" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(6)} -pin  "ACC1:acc#180" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(7)} -pin  "ACC1:acc#180" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(8)} -pin  "ACC1:acc#180" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(9)} -pin  "ACC1:acc#180" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(10)} -pin  "ACC1:acc#180" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load inst "ACC1-3:acc#10" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 34078 -attr oid 1242 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#10} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#180.itm(0)} -pin  "ACC1-3:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(1)} -pin  "ACC1-3:acc#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(2)} -pin  "ACC1-3:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(3)} -pin  "ACC1-3:acc#10" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(4)} -pin  "ACC1-3:acc#10" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(5)} -pin  "ACC1-3:acc#10" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(6)} -pin  "ACC1-3:acc#10" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(7)} -pin  "ACC1-3:acc#10" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(8)} -pin  "ACC1-3:acc#10" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(9)} -pin  "ACC1-3:acc#10" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {ACC1:acc#180.itm(10)} -pin  "ACC1-3:acc#10" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#180.itm}
+load net {regs.regs(1).sva(80)} -pin  "ACC1-3:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(81)} -pin  "ACC1-3:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(82)} -pin  "ACC1-3:acc#10" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(83)} -pin  "ACC1-3:acc#10" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(84)} -pin  "ACC1-3:acc#10" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(85)} -pin  "ACC1-3:acc#10" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(86)} -pin  "ACC1-3:acc#10" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(87)} -pin  "ACC1-3:acc#10" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(88)} -pin  "ACC1-3:acc#10" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(89)} -pin  "ACC1-3:acc#10" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {acc#10.psp#1.sva(0)} -pin  "ACC1-3:acc#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(1)} -pin  "ACC1-3:acc#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(2)} -pin  "ACC1-3:acc#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(3)} -pin  "ACC1-3:acc#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(4)} -pin  "ACC1-3:acc#10" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(5)} -pin  "ACC1-3:acc#10" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(6)} -pin  "ACC1-3:acc#10" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(7)} -pin  "ACC1-3:acc#10" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(8)} -pin  "ACC1-3:acc#10" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1-3:acc#10" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1-3:acc#10" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1-3:acc#10" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc#10.psp#1.sva}
+load inst "ACC1-3:not#156" "not(1)" "INTERFACE" -attr xrf 34079 -attr oid 1243 -attr @path {/sobel/sobel:core/ACC1-3:not#156} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1-3:not#156" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#42.itm}
+load net {ACC1-3:not#156.itm} -pin  "ACC1-3:not#156" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#156.itm}
+load inst "ACC1-3:not#124" "not(1)" "INTERFACE" -attr xrf 34080 -attr oid 1244 -attr @path {/sobel/sobel:core/ACC1-3:not#124} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(1)} -pin  "ACC1-3:not#124" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#4.itm}
+load net {ACC1-3:not#124.itm} -pin  "ACC1-3:not#124" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#124.itm}
+load inst "ACC1:acc#183" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 34081 -attr oid 1245 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#183" {A(0)} -attr @path {/sobel/sobel:core/conc#701.itm}
+load net {ACC1-3:not#156.itm} -pin  "ACC1:acc#183" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#701.itm}
+load net {acc#10.psp#1.sva(8)} -pin  "ACC1:acc#183" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#538.itm}
+load net {ACC1-3:not#124.itm} -pin  "ACC1:acc#183" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#538.itm}
+load net {ACC1:acc#183.itm(0)} -pin  "ACC1:acc#183" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load net {ACC1:acc#183.itm(1)} -pin  "ACC1:acc#183" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load net {ACC1:acc#183.itm(2)} -pin  "ACC1:acc#183" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load net {ACC1:acc#183.itm(3)} -pin  "ACC1:acc#183" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#183.itm}
+load inst "ACC1:acc#185" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 34082 -attr oid 1246 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#185" {A(0)} -attr @path {/sobel/sobel:core/conc#700.itm}
+load net {ACC1:acc#183.itm(1)} -pin  "ACC1:acc#185" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#700.itm}
+load net {ACC1:acc#183.itm(2)} -pin  "ACC1:acc#185" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#700.itm}
+load net {ACC1:acc#183.itm(3)} -pin  "ACC1:acc#185" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#700.itm}
+load net {acc#10.psp#1.sva(10)} -pin  "ACC1:acc#185" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#702.itm}
+load net {acc#10.psp#1.sva(0)} -pin  "ACC1:acc#185" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#702.itm}
+load net {GND} -pin  "ACC1:acc#185" {B(2)} -attr @path {/sobel/sobel:core/conc#702.itm}
+load net {PWR} -pin  "ACC1:acc#185" {B(3)} -attr @path {/sobel/sobel:core/conc#702.itm}
+load net {ACC1:acc#185.itm(0)} -pin  "ACC1:acc#185" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {ACC1:acc#185.itm(1)} -pin  "ACC1:acc#185" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {ACC1:acc#185.itm(2)} -pin  "ACC1:acc#185" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {ACC1:acc#185.itm(3)} -pin  "ACC1:acc#185" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load net {ACC1:acc#185.itm(4)} -pin  "ACC1:acc#185" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#185.itm}
+load inst "ACC1-3:not#125" "not(1)" "INTERFACE" -attr xrf 34083 -attr oid 1247 -attr @path {/sobel/sobel:core/ACC1-3:not#125} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(3)} -pin  "ACC1-3:not#125" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#3.itm}
+load net {ACC1-3:not#125.itm} -pin  "ACC1-3:not#125" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#125.itm}
+load inst "ACC1-3:not#127" "not(1)" "INTERFACE" -attr xrf 34084 -attr oid 1248 -attr @path {/sobel/sobel:core/ACC1-3:not#127} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(7)} -pin  "ACC1-3:not#127" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#6.itm}
+load net {ACC1-3:not#127.itm} -pin  "ACC1-3:not#127" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#127.itm}
+load inst "ACC1:acc#182" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34085 -attr oid 1249 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#182" {A(0)} -attr @path {/sobel/sobel:core/conc#704.itm}
+load net {acc#10.psp#1.sva(2)} -pin  "ACC1:acc#182" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#704.itm}
+load net {ACC1-3:not#127.itm} -pin  "ACC1:acc#182" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#536.itm}
+load net {ACC1-3:not#125.itm} -pin  "ACC1:acc#182" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#536.itm}
+load net {ACC1:acc#182.itm(0)} -pin  "ACC1:acc#182" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182.itm}
+load net {ACC1:acc#182.itm(1)} -pin  "ACC1:acc#182" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182.itm}
+load net {ACC1:acc#182.itm(2)} -pin  "ACC1:acc#182" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#182.itm}
+load inst "ACC1-3:not#126" "not(1)" "INTERFACE" -attr xrf 34086 -attr oid 1250 -attr @path {/sobel/sobel:core/ACC1-3:not#126} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(5)} -pin  "ACC1-3:not#126" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#12.itm}
+load net {ACC1-3:not#126.itm} -pin  "ACC1-3:not#126" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#126.itm}
+load inst "ACC1:acc#181" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34087 -attr oid 1251 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#181" {A(0)} -attr @path {/sobel/sobel:core/conc#705.itm}
+load net {acc#10.psp#1.sva(4)} -pin  "ACC1:acc#181" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#705.itm}
+load net {acc#10.psp#1.sva(6)} -pin  "ACC1:acc#181" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#534.itm}
+load net {ACC1-3:not#126.itm} -pin  "ACC1:acc#181" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#534.itm}
+load net {ACC1:acc#181.itm(0)} -pin  "ACC1:acc#181" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181.itm}
+load net {ACC1:acc#181.itm(1)} -pin  "ACC1:acc#181" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181.itm}
+load net {ACC1:acc#181.itm(2)} -pin  "ACC1:acc#181" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#181.itm}
+load inst "ACC1-3:not#128" "not(1)" "INTERFACE" -attr xrf 34088 -attr oid 1252 -attr @path {/sobel/sobel:core/ACC1-3:not#128} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#1.sva(9)} -pin  "ACC1-3:not#128" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#1.sva)#23.itm}
+load net {ACC1-3:not#128.itm} -pin  "ACC1-3:not#128" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#128.itm}
+load inst "ACC1:acc#184" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 34089 -attr oid 1253 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#184" {A(0)} -attr @path {/sobel/sobel:core/conc#703.itm}
+load net {ACC1:acc#182.itm(1)} -pin  "ACC1:acc#184" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#703.itm}
+load net {ACC1:acc#182.itm(2)} -pin  "ACC1:acc#184" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#703.itm}
+load net {ACC1-3:not#128.itm} -pin  "ACC1:acc#184" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#540.itm}
+load net {ACC1:acc#181.itm(1)} -pin  "ACC1:acc#184" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#540.itm}
+load net {ACC1:acc#181.itm(2)} -pin  "ACC1:acc#184" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#540.itm}
+load net {ACC1:acc#184.itm(0)} -pin  "ACC1:acc#184" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load net {ACC1:acc#184.itm(1)} -pin  "ACC1:acc#184" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load net {ACC1:acc#184.itm(2)} -pin  "ACC1:acc#184" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load net {ACC1:acc#184.itm(3)} -pin  "ACC1:acc#184" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#184.itm}
+load inst "ACC1-3:acc#113" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 34090 -attr oid 1254 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#113} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#185.itm(1)} -pin  "ACC1-3:acc#113" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#185.itm(2)} -pin  "ACC1-3:acc#113" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#185.itm(3)} -pin  "ACC1-3:acc#113" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#185.itm(4)} -pin  "ACC1-3:acc#113" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#50.itm}
+load net {ACC1:acc#184.itm(1)} -pin  "ACC1-3:acc#113" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#49.itm}
+load net {ACC1:acc#184.itm(2)} -pin  "ACC1-3:acc#113" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#49.itm}
+load net {ACC1:acc#184.itm(3)} -pin  "ACC1-3:acc#113" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#49.itm}
+load net {ACC1:acc#113.psp#1.sva(0)} -pin  "ACC1-3:acc#113" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#1.sva}
+load net {ACC1:acc#113.psp#1.sva(1)} -pin  "ACC1-3:acc#113" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#1.sva}
+load net {ACC1:acc#113.psp#1.sva(2)} -pin  "ACC1-3:acc#113" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#1.sva}
+load net {ACC1:acc#113.psp#1.sva(3)} -pin  "ACC1-3:acc#113" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#1.sva}
+load inst "ACC1-3:not#141" "not(1)" "INTERFACE" -attr xrf 34091 -attr oid 1255 -attr @path {/sobel/sobel:core/ACC1-3:not#141} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#113.psp#1.sva(1)} -pin  "ACC1-3:not#141" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#113.psp#1.sva)#4.itm}
+load net {ACC1-3:not#141.itm} -pin  "ACC1-3:not#141" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#141.itm}
+load inst "ACC1:acc#186" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34092 -attr oid 1256 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#186" {A(0)} -attr @path {/sobel/sobel:core/conc#706.itm}
+load net {ACC1:acc#113.psp#1.sva(0)} -pin  "ACC1:acc#186" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#706.itm}
+load net {ACC1:acc#113.psp#1.sva(2)} -pin  "ACC1:acc#186" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#544.itm}
+load net {ACC1-3:not#141.itm} -pin  "ACC1:acc#186" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#544.itm}
+load net {ACC1:acc#186.itm(0)} -pin  "ACC1:acc#186" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186.itm}
+load net {ACC1:acc#186.itm(1)} -pin  "ACC1:acc#186" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186.itm}
+load net {ACC1:acc#186.itm(2)} -pin  "ACC1:acc#186" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#186.itm}
+load inst "ACC1-3:not#155" "not(1)" "INTERFACE" -attr xrf 34093 -attr oid 1257 -attr @path {/sobel/sobel:core/ACC1-3:not#155} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#113.psp#1.sva(3)} -pin  "ACC1-3:not#155" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#113.psp#1.sva).itm}
+load net {ACC1-3:not#155.itm} -pin  "ACC1-3:not#155" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#155.itm}
+load inst "ACC1-3:acc#120" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 34094 -attr oid 1258 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#120} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#186.itm(1)} -pin  "ACC1-3:acc#120" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#51.itm}
+load net {ACC1:acc#186.itm(2)} -pin  "ACC1-3:acc#120" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#51.itm}
+load net {ACC1-3:not#155.itm} -pin  "ACC1-3:acc#120" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#155.itm}
+load net {ACC1:acc#120.psp.sva(0)} -pin  "ACC1-3:acc#120" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#120.psp.sva}
+load net {ACC1:acc#120.psp.sva(1)} -pin  "ACC1-3:acc#120" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#120.psp.sva}
+load net {ACC1:acc#120.psp.sva(2)} -pin  "ACC1-3:acc#120" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#120.psp.sva}
+load inst "ACC1:acc#250" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34095 -attr oid 1259 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#250" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#558.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#250" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#558.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#250" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#547.itm}
+load net {acc#10.psp#1.sva(11)} -pin  "ACC1:acc#250" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#547.itm}
+load net {ACC1:acc#250.cse(0)} -pin  "ACC1:acc#250" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#250.cse(1)} -pin  "ACC1:acc#250" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load net {ACC1:acc#250.cse(2)} -pin  "ACC1:acc#250" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#250.cse}
+load inst "ACC1-3:not#89" "not(1)" "INTERFACE" -attr xrf 34096 -attr oid 1260 -attr @path {/sobel/sobel:core/ACC1-3:not#89} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#187.itm(2)} -pin  "ACC1-3:not#89" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#10.sva)#3.itm}
+load net {ACC1-3:not#89.itm} -pin  "ACC1-3:not#89" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#89.itm}
+load inst "ACC1-3:not#158" "not(1)" "INTERFACE" -attr xrf 34097 -attr oid 1261 -attr @path {/sobel/sobel:core/ACC1-3:not#158} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#187.itm(3)} -pin  "ACC1-3:not#158" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#10.sva).itm}
+load net {ACC1-3:not#158.itm} -pin  "ACC1-3:not#158" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#158.itm}
+load inst "ACC1:acc#188" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 34098 -attr oid 1262 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#188" {A(0)} -attr @path {/sobel/sobel:core/conc#707.itm}
+load net {ACC1:acc#187.itm(1)} -pin  "ACC1:acc#188" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#707.itm}
+load net {PWR} -pin  "ACC1:acc#188" {A(2)} -attr @path {/sobel/sobel:core/conc#707.itm}
+load net {ACC1-3:not#158.itm} -pin  "ACC1:acc#188" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#549.itm}
+load net {ACC1-3:not#89.itm} -pin  "ACC1:acc#188" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#549.itm}
+load net {ACC1:acc#188.itm(0)} -pin  "ACC1:acc#188" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load net {ACC1:acc#188.itm(1)} -pin  "ACC1:acc#188" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load net {ACC1:acc#188.itm(2)} -pin  "ACC1:acc#188" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#188.itm}
+load inst "ACC1:not#161" "not(10)" "INTERFACE" -attr xrf 34099 -attr oid 1263 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "ACC1:not#161" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "ACC1:not#161" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "ACC1:not#161" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "ACC1:not#161" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "ACC1:not#161" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "ACC1:not#161" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "ACC1:not#161" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "ACC1:not#161" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "ACC1:not#161" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "ACC1:not#161" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#1).itm}
+load net {ACC1:not#161.itm(0)} -pin  "ACC1:not#161" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(1)} -pin  "ACC1:not#161" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(2)} -pin  "ACC1:not#161" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(3)} -pin  "ACC1:not#161" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(4)} -pin  "ACC1:not#161" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(5)} -pin  "ACC1:not#161" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(6)} -pin  "ACC1:not#161" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(7)} -pin  "ACC1:not#161" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(8)} -pin  "ACC1:not#161" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(9)} -pin  "ACC1:not#161" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load inst "ACC1:not#162" "not(10)" "INTERFACE" -attr xrf 34100 -attr oid 1264 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "ACC1:not#162" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "ACC1:not#162" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "ACC1:not#162" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "ACC1:not#162" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "ACC1:not#162" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "ACC1:not#162" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "ACC1:not#162" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "ACC1:not#162" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "ACC1:not#162" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "ACC1:not#162" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#2).itm}
+load net {ACC1:not#162.itm(0)} -pin  "ACC1:not#162" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(1)} -pin  "ACC1:not#162" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(2)} -pin  "ACC1:not#162" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(3)} -pin  "ACC1:not#162" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(4)} -pin  "ACC1:not#162" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(5)} -pin  "ACC1:not#162" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(6)} -pin  "ACC1:not#162" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(7)} -pin  "ACC1:not#162" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(8)} -pin  "ACC1:not#162" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(9)} -pin  "ACC1:not#162" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load inst "ACC1:acc#153" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 34101 -attr oid 1265 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#161.itm(0)} -pin  "ACC1:acc#153" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(1)} -pin  "ACC1:acc#153" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(2)} -pin  "ACC1:acc#153" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(3)} -pin  "ACC1:acc#153" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(4)} -pin  "ACC1:acc#153" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(5)} -pin  "ACC1:acc#153" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(6)} -pin  "ACC1:acc#153" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(7)} -pin  "ACC1:acc#153" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(8)} -pin  "ACC1:acc#153" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#161.itm(9)} -pin  "ACC1:acc#153" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:not#161.itm}
+load net {ACC1:not#162.itm(0)} -pin  "ACC1:acc#153" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(1)} -pin  "ACC1:acc#153" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(2)} -pin  "ACC1:acc#153" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(3)} -pin  "ACC1:acc#153" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(4)} -pin  "ACC1:acc#153" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(5)} -pin  "ACC1:acc#153" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(6)} -pin  "ACC1:acc#153" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(7)} -pin  "ACC1:acc#153" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(8)} -pin  "ACC1:acc#153" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:not#162.itm(9)} -pin  "ACC1:acc#153" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#162.itm}
+load net {ACC1:acc#153.itm(0)} -pin  "ACC1:acc#153" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(1)} -pin  "ACC1:acc#153" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(2)} -pin  "ACC1:acc#153" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(3)} -pin  "ACC1:acc#153" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(4)} -pin  "ACC1:acc#153" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(5)} -pin  "ACC1:acc#153" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(6)} -pin  "ACC1:acc#153" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(7)} -pin  "ACC1:acc#153" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(8)} -pin  "ACC1:acc#153" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(9)} -pin  "ACC1:acc#153" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(10)} -pin  "ACC1:acc#153" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load inst "ACC1:not#163" "not(10)" "INTERFACE" -attr xrf 34102 -attr oid 1266 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "ACC1:not#163" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "ACC1:not#163" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "ACC1:not#163" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "ACC1:not#163" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "ACC1:not#163" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "ACC1:not#163" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "ACC1:not#163" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "ACC1:not#163" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "ACC1:not#163" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "ACC1:not#163" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#3).itm}
+load net {ACC1:not#163.itm(0)} -pin  "ACC1:not#163" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(1)} -pin  "ACC1:not#163" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(2)} -pin  "ACC1:not#163" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(3)} -pin  "ACC1:not#163" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(4)} -pin  "ACC1:not#163" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(5)} -pin  "ACC1:not#163" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(6)} -pin  "ACC1:not#163" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(7)} -pin  "ACC1:not#163" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(8)} -pin  "ACC1:not#163" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(9)} -pin  "ACC1:not#163" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load inst "ACC1:acc#152" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 34103 -attr oid 1267 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#163.itm(0)} -pin  "ACC1:acc#152" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(1)} -pin  "ACC1:acc#152" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(2)} -pin  "ACC1:acc#152" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(3)} -pin  "ACC1:acc#152" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(4)} -pin  "ACC1:acc#152" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(5)} -pin  "ACC1:acc#152" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(6)} -pin  "ACC1:acc#152" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(7)} -pin  "ACC1:acc#152" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(8)} -pin  "ACC1:acc#152" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {ACC1:not#163.itm(9)} -pin  "ACC1:acc#152" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#163.itm}
+load net {PWR} -pin  "ACC1:acc#152" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#152" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#152.itm(0)} -pin  "ACC1:acc#152" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(1)} -pin  "ACC1:acc#152" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(2)} -pin  "ACC1:acc#152" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(3)} -pin  "ACC1:acc#152" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(4)} -pin  "ACC1:acc#152" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(5)} -pin  "ACC1:acc#152" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(6)} -pin  "ACC1:acc#152" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(7)} -pin  "ACC1:acc#152" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(8)} -pin  "ACC1:acc#152" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(9)} -pin  "ACC1:acc#152" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(10)} -pin  "ACC1:acc#152" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load inst "ACC1-1:acc#10" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 34104 -attr oid 1268 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#10} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#153.itm(0)} -pin  "ACC1-1:acc#10" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(1)} -pin  "ACC1-1:acc#10" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(2)} -pin  "ACC1-1:acc#10" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(3)} -pin  "ACC1-1:acc#10" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(4)} -pin  "ACC1-1:acc#10" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(5)} -pin  "ACC1-1:acc#10" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(6)} -pin  "ACC1-1:acc#10" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(7)} -pin  "ACC1-1:acc#10" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(8)} -pin  "ACC1-1:acc#10" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(9)} -pin  "ACC1-1:acc#10" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#153.itm(10)} -pin  "ACC1-1:acc#10" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#153.itm}
+load net {ACC1:acc#152.itm(0)} -pin  "ACC1-1:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(1)} -pin  "ACC1-1:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(2)} -pin  "ACC1-1:acc#10" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(3)} -pin  "ACC1-1:acc#10" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(4)} -pin  "ACC1-1:acc#10" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(5)} -pin  "ACC1-1:acc#10" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(6)} -pin  "ACC1-1:acc#10" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(7)} -pin  "ACC1-1:acc#10" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(8)} -pin  "ACC1-1:acc#10" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(9)} -pin  "ACC1-1:acc#10" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {ACC1:acc#152.itm(10)} -pin  "ACC1-1:acc#10" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#152.itm}
+load net {acc#10.psp#2.sva(0)} -pin  "ACC1-1:acc#10" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(1)} -pin  "ACC1-1:acc#10" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(2)} -pin  "ACC1-1:acc#10" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(3)} -pin  "ACC1-1:acc#10" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(4)} -pin  "ACC1-1:acc#10" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(5)} -pin  "ACC1-1:acc#10" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(6)} -pin  "ACC1-1:acc#10" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(7)} -pin  "ACC1-1:acc#10" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(8)} -pin  "ACC1-1:acc#10" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1-1:acc#10" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1-1:acc#10" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:acc#10" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/acc#10.psp#2.sva}
+load inst "ACC1-1:not#89" "not(1)" "INTERFACE" -attr xrf 34105 -attr oid 1269 -attr @path {/sobel/sobel:core/ACC1-1:not#89} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#160.itm(2)} -pin  "ACC1-1:not#89" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#22.sva)#3.itm}
+load net {ACC1-1:not#89.itm} -pin  "ACC1-1:not#89" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#89.itm}
+load inst "ACC1-1:not#158" "not(1)" "INTERFACE" -attr xrf 34106 -attr oid 1270 -attr @path {/sobel/sobel:core/ACC1-1:not#158} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#160.itm(3)} -pin  "ACC1-1:not#158" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#22.sva).itm}
+load net {ACC1-1:not#158.itm} -pin  "ACC1-1:not#158" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#158.itm}
+load inst "ACC1:acc#161" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 34107 -attr oid 1271 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#161} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#161" {A(0)} -attr @path {/sobel/sobel:core/conc#708.itm}
+load net {ACC1:acc#160.itm(1)} -pin  "ACC1:acc#161" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#708.itm}
+load net {PWR} -pin  "ACC1:acc#161" {A(2)} -attr @path {/sobel/sobel:core/conc#708.itm}
+load net {ACC1-1:not#158.itm} -pin  "ACC1:acc#161" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#495.itm}
+load net {ACC1-1:not#89.itm} -pin  "ACC1:acc#161" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#495.itm}
+load net {ACC1:acc#161.itm(0)} -pin  "ACC1:acc#161" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load net {ACC1:acc#161.itm(1)} -pin  "ACC1:acc#161" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load net {ACC1:acc#161.itm(2)} -pin  "ACC1:acc#161" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#161.itm}
+load inst "ACC1-1:not#149" "not(2)" "INTERFACE" -attr xrf 34108 -attr oid 1272 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:not#149} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#120.psp#1.sva(1)} -pin  "ACC1-1:not#149" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp#1.sva).itm}
+load net {ACC1:acc#120.psp#1.sva(2)} -pin  "ACC1-1:not#149" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp#1.sva).itm}
+load net {ACC1-1:not#149.itm(0)} -pin  "ACC1-1:not#149" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:not#149.itm}
+load net {ACC1-1:not#149.itm(1)} -pin  "ACC1-1:not#149" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:not#149.itm}
+load inst "ACC1:acc#160" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 34109 -attr oid 1273 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#160} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#160" {A(0)} -attr @path {/sobel/sobel:core/conc#709.itm}
+load net {ACC1-1:not#149.itm(0)} -pin  "ACC1:acc#160" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#709.itm}
+load net {ACC1-1:not#149.itm(1)} -pin  "ACC1:acc#160" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#709.itm}
+load net {PWR} -pin  "ACC1:acc#160" {B(0)} -attr @path {/sobel/sobel:core/conc#710.itm}
+load net {ACC1:acc#120.psp#1.sva(0)} -pin  "ACC1:acc#160" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#710.itm}
+load net {ACC1:acc#160.itm(0)} -pin  "ACC1:acc#160" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load net {ACC1:acc#160.itm(1)} -pin  "ACC1:acc#160" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load net {ACC1:acc#160.itm(2)} -pin  "ACC1:acc#160" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load net {ACC1:acc#160.itm(3)} -pin  "ACC1:acc#160" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#160.itm}
+load inst "ACC1-1:not#156" "not(1)" "INTERFACE" -attr xrf 34110 -attr oid 1274 -attr @path {/sobel/sobel:core/ACC1-1:not#156} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1-1:not#156" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#32.itm}
+load net {ACC1-1:not#156.itm} -pin  "ACC1-1:not#156" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#156.itm}
+load inst "ACC1-1:not#124" "not(1)" "INTERFACE" -attr xrf 34111 -attr oid 1275 -attr @path {/sobel/sobel:core/ACC1-1:not#124} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(1)} -pin  "ACC1-1:not#124" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#8.itm}
+load net {ACC1-1:not#124.itm} -pin  "ACC1-1:not#124" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#124.itm}
+load inst "ACC1:acc#156" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 34112 -attr oid 1276 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#156" {A(0)} -attr @path {/sobel/sobel:core/conc#712.itm}
+load net {ACC1-1:not#156.itm} -pin  "ACC1:acc#156" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#712.itm}
+load net {acc#10.psp#2.sva(8)} -pin  "ACC1:acc#156" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#484.itm}
+load net {ACC1-1:not#124.itm} -pin  "ACC1:acc#156" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#484.itm}
+load net {ACC1:acc#156.itm(0)} -pin  "ACC1:acc#156" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load net {ACC1:acc#156.itm(1)} -pin  "ACC1:acc#156" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load net {ACC1:acc#156.itm(2)} -pin  "ACC1:acc#156" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load net {ACC1:acc#156.itm(3)} -pin  "ACC1:acc#156" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#156.itm}
+load inst "ACC1:acc#158" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 34113 -attr oid 1277 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#158" {A(0)} -attr @path {/sobel/sobel:core/conc#711.itm}
+load net {ACC1:acc#156.itm(1)} -pin  "ACC1:acc#158" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#711.itm}
+load net {ACC1:acc#156.itm(2)} -pin  "ACC1:acc#158" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#711.itm}
+load net {ACC1:acc#156.itm(3)} -pin  "ACC1:acc#158" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#711.itm}
+load net {acc#10.psp#2.sva(10)} -pin  "ACC1:acc#158" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#713.itm}
+load net {acc#10.psp#2.sva(0)} -pin  "ACC1:acc#158" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#713.itm}
+load net {GND} -pin  "ACC1:acc#158" {B(2)} -attr @path {/sobel/sobel:core/conc#713.itm}
+load net {PWR} -pin  "ACC1:acc#158" {B(3)} -attr @path {/sobel/sobel:core/conc#713.itm}
+load net {ACC1:acc#158.itm(0)} -pin  "ACC1:acc#158" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {ACC1:acc#158.itm(1)} -pin  "ACC1:acc#158" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {ACC1:acc#158.itm(2)} -pin  "ACC1:acc#158" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {ACC1:acc#158.itm(3)} -pin  "ACC1:acc#158" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load net {ACC1:acc#158.itm(4)} -pin  "ACC1:acc#158" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#158.itm}
+load inst "ACC1-1:not#125" "not(1)" "INTERFACE" -attr xrf 34114 -attr oid 1278 -attr @path {/sobel/sobel:core/ACC1-1:not#125} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(3)} -pin  "ACC1-1:not#125" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#7.itm}
+load net {ACC1-1:not#125.itm} -pin  "ACC1-1:not#125" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#125.itm}
+load inst "ACC1-1:not#127" "not(1)" "INTERFACE" -attr xrf 34115 -attr oid 1279 -attr @path {/sobel/sobel:core/ACC1-1:not#127} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(7)} -pin  "ACC1-1:not#127" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#3.itm}
+load net {ACC1-1:not#127.itm} -pin  "ACC1-1:not#127" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#127.itm}
+load inst "ACC1:acc#155" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34116 -attr oid 1280 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#155} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#155" {A(0)} -attr @path {/sobel/sobel:core/conc#715.itm}
+load net {acc#10.psp#2.sva(2)} -pin  "ACC1:acc#155" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#715.itm}
+load net {ACC1-1:not#127.itm} -pin  "ACC1:acc#155" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#482.itm}
+load net {ACC1-1:not#125.itm} -pin  "ACC1:acc#155" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#482.itm}
+load net {ACC1:acc#155.itm(0)} -pin  "ACC1:acc#155" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#155.itm}
+load net {ACC1:acc#155.itm(1)} -pin  "ACC1:acc#155" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#155.itm}
+load net {ACC1:acc#155.itm(2)} -pin  "ACC1:acc#155" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#155.itm}
+load inst "ACC1-1:not#126" "not(1)" "INTERFACE" -attr xrf 34117 -attr oid 1281 -attr @path {/sobel/sobel:core/ACC1-1:not#126} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(5)} -pin  "ACC1-1:not#126" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#2.itm}
+load net {ACC1-1:not#126.itm} -pin  "ACC1-1:not#126" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#126.itm}
+load inst "ACC1:acc#154" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34118 -attr oid 1282 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#154" {A(0)} -attr @path {/sobel/sobel:core/conc#716.itm}
+load net {acc#10.psp#2.sva(4)} -pin  "ACC1:acc#154" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#716.itm}
+load net {acc#10.psp#2.sva(6)} -pin  "ACC1:acc#154" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#480.itm}
+load net {ACC1-1:not#126.itm} -pin  "ACC1:acc#154" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#480.itm}
+load net {ACC1:acc#154.itm(0)} -pin  "ACC1:acc#154" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154.itm}
+load net {ACC1:acc#154.itm(1)} -pin  "ACC1:acc#154" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154.itm}
+load net {ACC1:acc#154.itm(2)} -pin  "ACC1:acc#154" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#154.itm}
+load inst "ACC1-1:not#128" "not(1)" "INTERFACE" -attr xrf 34119 -attr oid 1283 -attr @path {/sobel/sobel:core/ACC1-1:not#128} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc#10.psp#2.sva(9)} -pin  "ACC1-1:not#128" {A(0)} -attr @path {/sobel/sobel:core/slc(acc#10.psp#2.sva)#59.itm}
+load net {ACC1-1:not#128.itm} -pin  "ACC1-1:not#128" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#128.itm}
+load inst "ACC1:acc#157" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 34120 -attr oid 1284 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#157} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#157" {A(0)} -attr @path {/sobel/sobel:core/conc#714.itm}
+load net {ACC1:acc#155.itm(1)} -pin  "ACC1:acc#157" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#714.itm}
+load net {ACC1:acc#155.itm(2)} -pin  "ACC1:acc#157" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#714.itm}
+load net {ACC1-1:not#128.itm} -pin  "ACC1:acc#157" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#486.itm}
+load net {ACC1:acc#154.itm(1)} -pin  "ACC1:acc#157" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#486.itm}
+load net {ACC1:acc#154.itm(2)} -pin  "ACC1:acc#157" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#486.itm}
+load net {ACC1:acc#157.itm(0)} -pin  "ACC1:acc#157" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load net {ACC1:acc#157.itm(1)} -pin  "ACC1:acc#157" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load net {ACC1:acc#157.itm(2)} -pin  "ACC1:acc#157" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load net {ACC1:acc#157.itm(3)} -pin  "ACC1:acc#157" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#157.itm}
+load inst "ACC1-1:acc#113" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 34121 -attr oid 1285 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#113} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#158.itm(1)} -pin  "ACC1-1:acc#113" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#158.itm(2)} -pin  "ACC1-1:acc#113" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#158.itm(3)} -pin  "ACC1-1:acc#113" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#158.itm(4)} -pin  "ACC1-1:acc#113" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#26.itm}
+load net {ACC1:acc#157.itm(1)} -pin  "ACC1-1:acc#113" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#25.itm}
+load net {ACC1:acc#157.itm(2)} -pin  "ACC1-1:acc#113" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#25.itm}
+load net {ACC1:acc#157.itm(3)} -pin  "ACC1-1:acc#113" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#25.itm}
+load net {ACC1:acc#113.psp#2.sva(0)} -pin  "ACC1-1:acc#113" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#2.sva}
+load net {ACC1:acc#113.psp#2.sva(1)} -pin  "ACC1-1:acc#113" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#2.sva}
+load net {ACC1:acc#113.psp#2.sva(2)} -pin  "ACC1-1:acc#113" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#2.sva}
+load net {ACC1:acc#113.psp#2.sva(3)} -pin  "ACC1-1:acc#113" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#113.psp#2.sva}
+load inst "ACC1-1:not#141" "not(1)" "INTERFACE" -attr xrf 34122 -attr oid 1286 -attr @path {/sobel/sobel:core/ACC1-1:not#141} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#113.psp#2.sva(1)} -pin  "ACC1-1:not#141" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#113.psp#2.sva)#4.itm}
+load net {ACC1-1:not#141.itm} -pin  "ACC1-1:not#141" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#141.itm}
+load inst "ACC1:acc#159" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34123 -attr oid 1287 -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#159} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#159" {A(0)} -attr @path {/sobel/sobel:core/conc#717.itm}
+load net {ACC1:acc#113.psp#2.sva(0)} -pin  "ACC1:acc#159" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#717.itm}
+load net {ACC1:acc#113.psp#2.sva(2)} -pin  "ACC1:acc#159" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#490.itm}
+load net {ACC1-1:not#141.itm} -pin  "ACC1:acc#159" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#490.itm}
+load net {ACC1:acc#159.itm(0)} -pin  "ACC1:acc#159" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#159.itm}
+load net {ACC1:acc#159.itm(1)} -pin  "ACC1:acc#159" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#159.itm}
+load net {ACC1:acc#159.itm(2)} -pin  "ACC1:acc#159" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#159.itm}
+load inst "ACC1-1:not#155" "not(1)" "INTERFACE" -attr xrf 34124 -attr oid 1288 -attr @path {/sobel/sobel:core/ACC1-1:not#155} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#113.psp#2.sva(3)} -pin  "ACC1-1:not#155" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#113.psp#2.sva)#1.itm}
+load net {ACC1-1:not#155.itm} -pin  "ACC1-1:not#155" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#155.itm}
+load inst "ACC1-1:acc#120" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 34125 -attr oid 1289 -attr vt dc -attr @path {/sobel/sobel:core/ACC1-1:acc#120} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#159.itm(1)} -pin  "ACC1-1:acc#120" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#27.itm}
+load net {ACC1:acc#159.itm(2)} -pin  "ACC1-1:acc#120" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:slc#27.itm}
+load net {ACC1-1:not#155.itm} -pin  "ACC1-1:acc#120" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#155.itm}
+load net {ACC1:acc#120.psp#1.sva(0)} -pin  "ACC1-1:acc#120" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#120.psp#1.sva}
+load net {ACC1:acc#120.psp#1.sva(1)} -pin  "ACC1-1:acc#120" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#120.psp#1.sva}
+load net {ACC1:acc#120.psp#1.sva(2)} -pin  "ACC1-1:acc#120" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC1:acc#120.psp#1.sva}
+load inst "ACC1:acc#277" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34126 -attr oid 1290 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#277" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#850.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#277" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#850.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#277" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#827.itm}
+load net {acc#10.psp#2.sva(11)} -pin  "ACC1:acc#277" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#827.itm}
+load net {ACC1:acc#277.cse(0)} -pin  "ACC1:acc#277" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#277.cse(1)} -pin  "ACC1:acc#277" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load net {ACC1:acc#277.cse(2)} -pin  "ACC1:acc#277" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#277.cse}
+load inst "ACC1-3:not#149" "not(2)" "INTERFACE" -attr xrf 34127 -attr oid 1291 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#149} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#120.psp.sva(1)} -pin  "ACC1-3:not#149" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp.sva).itm}
+load net {ACC1:acc#120.psp.sva(2)} -pin  "ACC1-3:not#149" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#120.psp.sva).itm}
+load net {ACC1-3:not#149.itm(0)} -pin  "ACC1-3:not#149" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#149.itm}
+load net {ACC1-3:not#149.itm(1)} -pin  "ACC1-3:not#149" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#149.itm}
+load inst "ACC1:acc#187" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 34128 -attr oid 1292 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#187" {A(0)} -attr @path {/sobel/sobel:core/conc#718.itm}
+load net {ACC1-3:not#149.itm(0)} -pin  "ACC1:acc#187" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#718.itm}
+load net {ACC1-3:not#149.itm(1)} -pin  "ACC1:acc#187" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#718.itm}
+load net {PWR} -pin  "ACC1:acc#187" {B(0)} -attr @path {/sobel/sobel:core/conc#719.itm}
+load net {ACC1:acc#120.psp.sva(0)} -pin  "ACC1:acc#187" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#719.itm}
+load net {ACC1:acc#187.itm(0)} -pin  "ACC1:acc#187" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load net {ACC1:acc#187.itm(1)} -pin  "ACC1:acc#187" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load net {ACC1:acc#187.itm(2)} -pin  "ACC1:acc#187" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load net {ACC1:acc#187.itm(3)} -pin  "ACC1:acc#187" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#187.itm}
+load inst "ACC1:acc#162" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 34129 -attr oid 1293 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {regs.regs(1).sva(10)} -pin  "ACC1:acc#162" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(11)} -pin  "ACC1:acc#162" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(12)} -pin  "ACC1:acc#162" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(13)} -pin  "ACC1:acc#162" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(14)} -pin  "ACC1:acc#162" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(15)} -pin  "ACC1:acc#162" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(16)} -pin  "ACC1:acc#162" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(17)} -pin  "ACC1:acc#162" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(18)} -pin  "ACC1:acc#162" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(19)} -pin  "ACC1:acc#162" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#8.itm}
+load net {regs.regs(1).sva(0)} -pin  "ACC1:acc#162" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(1)} -pin  "ACC1:acc#162" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(2)} -pin  "ACC1:acc#162" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(3)} -pin  "ACC1:acc#162" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(4)} -pin  "ACC1:acc#162" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(5)} -pin  "ACC1:acc#162" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(6)} -pin  "ACC1:acc#162" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(7)} -pin  "ACC1:acc#162" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(8)} -pin  "ACC1:acc#162" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {regs.regs(1).sva(9)} -pin  "ACC1:acc#162" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#9.itm}
+load net {ACC1:acc#162.itm(0)} -pin  "ACC1:acc#162" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(1)} -pin  "ACC1:acc#162" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(2)} -pin  "ACC1:acc#162" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(3)} -pin  "ACC1:acc#162" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(4)} -pin  "ACC1:acc#162" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(5)} -pin  "ACC1:acc#162" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(6)} -pin  "ACC1:acc#162" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(7)} -pin  "ACC1:acc#162" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(8)} -pin  "ACC1:acc#162" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(9)} -pin  "ACC1:acc#162" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(10)} -pin  "ACC1:acc#162" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load inst "ACC1-3:acc" "add(11,1,10,1,12)" "INTERFACE" -attr xrf 34130 -attr oid 1294 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#162.itm(0)} -pin  "ACC1-3:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(1)} -pin  "ACC1-3:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(2)} -pin  "ACC1-3:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(3)} -pin  "ACC1-3:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(4)} -pin  "ACC1-3:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(5)} -pin  "ACC1-3:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(6)} -pin  "ACC1-3:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(7)} -pin  "ACC1-3:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(8)} -pin  "ACC1-3:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(9)} -pin  "ACC1-3:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {ACC1:acc#162.itm(10)} -pin  "ACC1-3:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#162.itm}
+load net {regs.regs(1).sva(20)} -pin  "ACC1-3:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(21)} -pin  "ACC1-3:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(22)} -pin  "ACC1-3:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(23)} -pin  "ACC1-3:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(24)} -pin  "ACC1-3:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(25)} -pin  "ACC1-3:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(26)} -pin  "ACC1-3:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(27)} -pin  "ACC1-3:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(28)} -pin  "ACC1-3:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {regs.regs(1).sva(29)} -pin  "ACC1-3:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#10.itm}
+load net {acc.psp#1.sva(0)} -pin  "ACC1-3:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(1)} -pin  "ACC1-3:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(2)} -pin  "ACC1-3:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(3)} -pin  "ACC1-3:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(4)} -pin  "ACC1-3:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(5)} -pin  "ACC1-3:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(6)} -pin  "ACC1-3:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(7)} -pin  "ACC1-3:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(8)} -pin  "ACC1-3:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(9)} -pin  "ACC1-3:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(10)} -pin  "ACC1-3:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#1.sva}
+load inst "ACC1-3:not#160" "not(1)" "INTERFACE" -attr xrf 34131 -attr oid 1295 -attr @path {/sobel/sobel:core/ACC1-3:not#160} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1-3:not#160" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#42.itm}
+load net {ACC1-3:not#160.itm} -pin  "ACC1-3:not#160" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#160.itm}
+load inst "ACC1-3:not#106" "not(1)" "INTERFACE" -attr xrf 34132 -attr oid 1296 -attr @path {/sobel/sobel:core/ACC1-3:not#106} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(1)} -pin  "ACC1-3:not#106" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#4.itm}
+load net {ACC1-3:not#106.itm} -pin  "ACC1-3:not#106" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#106.itm}
+load inst "ACC1:acc#165" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 34133 -attr oid 1297 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#165" {A(0)} -attr @path {/sobel/sobel:core/conc#721.itm}
+load net {ACC1-3:not#160.itm} -pin  "ACC1:acc#165" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#721.itm}
+load net {acc.psp#1.sva(8)} -pin  "ACC1:acc#165" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#502.itm}
+load net {ACC1-3:not#106.itm} -pin  "ACC1:acc#165" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#502.itm}
+load net {ACC1:acc#165.itm(0)} -pin  "ACC1:acc#165" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(1)} -pin  "ACC1:acc#165" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(2)} -pin  "ACC1:acc#165" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load net {ACC1:acc#165.itm(3)} -pin  "ACC1:acc#165" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#165.itm}
+load inst "ACC1:acc#167" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 34134 -attr oid 1298 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#167" {A(0)} -attr @path {/sobel/sobel:core/conc#720.itm}
+load net {ACC1:acc#165.itm(1)} -pin  "ACC1:acc#167" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#720.itm}
+load net {ACC1:acc#165.itm(2)} -pin  "ACC1:acc#167" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#720.itm}
+load net {ACC1:acc#165.itm(3)} -pin  "ACC1:acc#167" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#720.itm}
+load net {acc.psp#1.sva(10)} -pin  "ACC1:acc#167" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#722.itm}
+load net {acc.psp#1.sva(0)} -pin  "ACC1:acc#167" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#722.itm}
+load net {GND} -pin  "ACC1:acc#167" {B(2)} -attr @path {/sobel/sobel:core/conc#722.itm}
+load net {PWR} -pin  "ACC1:acc#167" {B(3)} -attr @path {/sobel/sobel:core/conc#722.itm}
+load net {ACC1:acc#167.itm(0)} -pin  "ACC1:acc#167" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load net {ACC1:acc#167.itm(1)} -pin  "ACC1:acc#167" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load net {ACC1:acc#167.itm(2)} -pin  "ACC1:acc#167" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load net {ACC1:acc#167.itm(3)} -pin  "ACC1:acc#167" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load net {ACC1:acc#167.itm(4)} -pin  "ACC1:acc#167" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#167.itm}
+load inst "ACC1-3:not#107" "not(1)" "INTERFACE" -attr xrf 34135 -attr oid 1299 -attr @path {/sobel/sobel:core/ACC1-3:not#107} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(3)} -pin  "ACC1-3:not#107" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#3.itm}
+load net {ACC1-3:not#107.itm} -pin  "ACC1-3:not#107" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#107.itm}
+load inst "ACC1-3:not#109" "not(1)" "INTERFACE" -attr xrf 34136 -attr oid 1300 -attr @path {/sobel/sobel:core/ACC1-3:not#109} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(7)} -pin  "ACC1-3:not#109" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#6.itm}
+load net {ACC1-3:not#109.itm} -pin  "ACC1-3:not#109" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#109.itm}
+load inst "ACC1:acc#164" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34137 -attr oid 1301 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#164" {A(0)} -attr @path {/sobel/sobel:core/conc#724.itm}
+load net {acc.psp#1.sva(2)} -pin  "ACC1:acc#164" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#724.itm}
+load net {ACC1-3:not#109.itm} -pin  "ACC1:acc#164" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#500.itm}
+load net {ACC1-3:not#107.itm} -pin  "ACC1:acc#164" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#500.itm}
+load net {ACC1:acc#164.itm(0)} -pin  "ACC1:acc#164" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164.itm}
+load net {ACC1:acc#164.itm(1)} -pin  "ACC1:acc#164" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164.itm}
+load net {ACC1:acc#164.itm(2)} -pin  "ACC1:acc#164" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#164.itm}
+load inst "ACC1-3:not#108" "not(1)" "INTERFACE" -attr xrf 34138 -attr oid 1302 -attr @path {/sobel/sobel:core/ACC1-3:not#108} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(5)} -pin  "ACC1-3:not#108" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#12.itm}
+load net {ACC1-3:not#108.itm} -pin  "ACC1-3:not#108" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#108.itm}
+load inst "ACC1:acc#163" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34139 -attr oid 1303 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#163" {A(0)} -attr @path {/sobel/sobel:core/conc#725.itm}
+load net {acc.psp#1.sva(4)} -pin  "ACC1:acc#163" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#725.itm}
+load net {acc.psp#1.sva(6)} -pin  "ACC1:acc#163" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#498.itm}
+load net {ACC1-3:not#108.itm} -pin  "ACC1:acc#163" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#498.itm}
+load net {ACC1:acc#163.itm(0)} -pin  "ACC1:acc#163" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163.itm}
+load net {ACC1:acc#163.itm(1)} -pin  "ACC1:acc#163" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163.itm}
+load net {ACC1:acc#163.itm(2)} -pin  "ACC1:acc#163" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#163.itm}
+load inst "ACC1-3:not#110" "not(1)" "INTERFACE" -attr xrf 34140 -attr oid 1304 -attr @path {/sobel/sobel:core/ACC1-3:not#110} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#1.sva(9)} -pin  "ACC1-3:not#110" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#1.sva)#23.itm}
+load net {ACC1-3:not#110.itm} -pin  "ACC1-3:not#110" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#110.itm}
+load inst "ACC1:acc#166" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 34141 -attr oid 1305 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#166" {A(0)} -attr @path {/sobel/sobel:core/conc#723.itm}
+load net {ACC1:acc#164.itm(1)} -pin  "ACC1:acc#166" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#723.itm}
+load net {ACC1:acc#164.itm(2)} -pin  "ACC1:acc#166" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#723.itm}
+load net {ACC1-3:not#110.itm} -pin  "ACC1:acc#166" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#504.itm}
+load net {ACC1:acc#163.itm(1)} -pin  "ACC1:acc#166" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#504.itm}
+load net {ACC1:acc#163.itm(2)} -pin  "ACC1:acc#166" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#504.itm}
+load net {ACC1:acc#166.itm(0)} -pin  "ACC1:acc#166" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load net {ACC1:acc#166.itm(1)} -pin  "ACC1:acc#166" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load net {ACC1:acc#166.itm(2)} -pin  "ACC1:acc#166" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load net {ACC1:acc#166.itm(3)} -pin  "ACC1:acc#166" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#166.itm}
+load inst "ACC1-3:acc#107" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 34142 -attr oid 1306 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#107} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#167.itm(1)} -pin  "ACC1-3:acc#107" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#167.itm(2)} -pin  "ACC1-3:acc#107" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#167.itm(3)} -pin  "ACC1-3:acc#107" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#167.itm(4)} -pin  "ACC1-3:acc#107" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#34.itm}
+load net {ACC1:acc#166.itm(1)} -pin  "ACC1-3:acc#107" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#166.itm(2)} -pin  "ACC1-3:acc#107" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#166.itm(3)} -pin  "ACC1-3:acc#107" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#33.itm}
+load net {ACC1:acc#107.psp#1.sva(0)} -pin  "ACC1-3:acc#107" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#1.sva}
+load net {ACC1:acc#107.psp#1.sva(1)} -pin  "ACC1-3:acc#107" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#1.sva}
+load net {ACC1:acc#107.psp#1.sva(2)} -pin  "ACC1-3:acc#107" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#1.sva}
+load net {ACC1:acc#107.psp#1.sva(3)} -pin  "ACC1-3:acc#107" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#1.sva}
+load inst "ACC1-3:not#133" "not(1)" "INTERFACE" -attr xrf 34143 -attr oid 1307 -attr @path {/sobel/sobel:core/ACC1-3:not#133} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#107.psp#1.sva(1)} -pin  "ACC1-3:not#133" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#107.psp#1.sva)#4.itm}
+load net {ACC1-3:not#133.itm} -pin  "ACC1-3:not#133" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#133.itm}
+load inst "ACC1:acc#168" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34144 -attr oid 1308 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#168" {A(0)} -attr @path {/sobel/sobel:core/conc#726.itm}
+load net {ACC1:acc#107.psp#1.sva(0)} -pin  "ACC1:acc#168" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#726.itm}
+load net {ACC1:acc#107.psp#1.sva(2)} -pin  "ACC1:acc#168" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#508.itm}
+load net {ACC1-3:not#133.itm} -pin  "ACC1:acc#168" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#508.itm}
+load net {ACC1:acc#168.itm(0)} -pin  "ACC1:acc#168" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168.itm}
+load net {ACC1:acc#168.itm(1)} -pin  "ACC1:acc#168" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168.itm}
+load net {ACC1:acc#168.itm(2)} -pin  "ACC1:acc#168" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#168.itm}
+load inst "ACC1-3:not#153" "not(1)" "INTERFACE" -attr xrf 34145 -attr oid 1309 -attr @path {/sobel/sobel:core/ACC1-3:not#153} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#107.psp#1.sva(3)} -pin  "ACC1-3:not#153" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#107.psp#1.sva).itm}
+load net {ACC1-3:not#153.itm} -pin  "ACC1-3:not#153" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#153.itm}
+load inst "ACC1-3:acc#116" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 34146 -attr oid 1310 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:acc#116} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#168.itm(1)} -pin  "ACC1-3:acc#116" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#35.itm}
+load net {ACC1:acc#168.itm(2)} -pin  "ACC1-3:acc#116" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#35.itm}
+load net {ACC1-3:not#153.itm} -pin  "ACC1-3:acc#116" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#153.itm}
+load net {ACC1:acc#116.psp.sva(0)} -pin  "ACC1-3:acc#116" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp.sva}
+load net {ACC1:acc#116.psp.sva(1)} -pin  "ACC1-3:acc#116" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp.sva}
+load net {ACC1:acc#116.psp.sva(2)} -pin  "ACC1-3:acc#116" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp.sva}
+load inst "ACC1:acc#197" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34147 -attr oid 1311 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#197" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#562.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#197" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#562.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#197" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#551.itm}
+load net {acc.psp#1.sva(11)} -pin  "ACC1:acc#197" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:exs#551.itm}
+load net {ACC1:acc#197.cse(0)} -pin  "ACC1:acc#197" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#197.cse(1)} -pin  "ACC1:acc#197" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load net {ACC1:acc#197.cse(2)} -pin  "ACC1:acc#197" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#197.cse}
+load inst "ACC1-3:not#25" "not(1)" "INTERFACE" -attr xrf 34148 -attr oid 1312 -attr @path {/sobel/sobel:core/ACC1-3:not#25} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#169.itm(2)} -pin  "ACC1-3:not#25" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva)#3.itm}
+load net {ACC1-3:not#25.itm} -pin  "ACC1-3:not#25" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#25.itm}
+load inst "ACC1-3:not#162" "not(1)" "INTERFACE" -attr xrf 34149 -attr oid 1313 -attr @path {/sobel/sobel:core/ACC1-3:not#162} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#169.itm(3)} -pin  "ACC1-3:not#162" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#2.sva).itm}
+load net {ACC1-3:not#162.itm} -pin  "ACC1-3:not#162" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-3:not#162.itm}
+load inst "ACC1:acc#170" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 34150 -attr oid 1314 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#170" {A(0)} -attr @path {/sobel/sobel:core/conc#727.itm}
+load net {ACC1:acc#169.itm(1)} -pin  "ACC1:acc#170" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#727.itm}
+load net {PWR} -pin  "ACC1:acc#170" {A(2)} -attr @path {/sobel/sobel:core/conc#727.itm}
+load net {ACC1-3:not#162.itm} -pin  "ACC1:acc#170" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#513.itm}
+load net {ACC1-3:not#25.itm} -pin  "ACC1:acc#170" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#513.itm}
+load net {ACC1:acc#170.itm(0)} -pin  "ACC1:acc#170" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170.itm}
+load net {ACC1:acc#170.itm(1)} -pin  "ACC1:acc#170" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170.itm}
+load net {ACC1:acc#170.itm(2)} -pin  "ACC1:acc#170" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#170.itm}
+load inst "ACC1:not" "not(10)" "INTERFACE" -attr xrf 34151 -attr oid 1315 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "ACC1:not" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "ACC1:not" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "ACC1:not" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "ACC1:not" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "ACC1:not" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "ACC1:not" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "ACC1:not" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "ACC1:not" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "ACC1:not" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "ACC1:not" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#7).itm}
+load net {ACC1:not.itm(0)} -pin  "ACC1:not" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:not" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:not" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:not" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:not" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:not" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:not" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:not" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:not" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:not" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load inst "ACC1:not#156" "not(10)" "INTERFACE" -attr xrf 34152 -attr oid 1316 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "ACC1:not#156" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "ACC1:not#156" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "ACC1:not#156" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "ACC1:not#156" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "ACC1:not#156" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "ACC1:not#156" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "ACC1:not#156" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "ACC1:not#156" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "ACC1:not#156" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "ACC1:not#156" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#8).itm}
+load net {ACC1:not#156.itm(0)} -pin  "ACC1:not#156" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(1)} -pin  "ACC1:not#156" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(2)} -pin  "ACC1:not#156" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(3)} -pin  "ACC1:not#156" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(4)} -pin  "ACC1:not#156" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(5)} -pin  "ACC1:not#156" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(6)} -pin  "ACC1:not#156" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(7)} -pin  "ACC1:not#156" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(8)} -pin  "ACC1:not#156" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(9)} -pin  "ACC1:not#156" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load inst "ACC1:acc#133" "add(10,1,10,1,11)" "INTERFACE" -attr xrf 34153 -attr oid 1317 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not.itm(0)} -pin  "ACC1:acc#133" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(1)} -pin  "ACC1:acc#133" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(2)} -pin  "ACC1:acc#133" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(3)} -pin  "ACC1:acc#133" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(4)} -pin  "ACC1:acc#133" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(5)} -pin  "ACC1:acc#133" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(6)} -pin  "ACC1:acc#133" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(7)} -pin  "ACC1:acc#133" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(8)} -pin  "ACC1:acc#133" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not.itm(9)} -pin  "ACC1:acc#133" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not.itm}
+load net {ACC1:not#156.itm(0)} -pin  "ACC1:acc#133" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(1)} -pin  "ACC1:acc#133" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(2)} -pin  "ACC1:acc#133" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(3)} -pin  "ACC1:acc#133" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(4)} -pin  "ACC1:acc#133" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(5)} -pin  "ACC1:acc#133" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(6)} -pin  "ACC1:acc#133" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(7)} -pin  "ACC1:acc#133" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(8)} -pin  "ACC1:acc#133" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:not#156.itm(9)} -pin  "ACC1:acc#133" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#156.itm}
+load net {ACC1:acc#133.itm(0)} -pin  "ACC1:acc#133" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(1)} -pin  "ACC1:acc#133" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(2)} -pin  "ACC1:acc#133" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(3)} -pin  "ACC1:acc#133" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(4)} -pin  "ACC1:acc#133" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(5)} -pin  "ACC1:acc#133" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(6)} -pin  "ACC1:acc#133" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(7)} -pin  "ACC1:acc#133" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(8)} -pin  "ACC1:acc#133" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(9)} -pin  "ACC1:acc#133" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(10)} -pin  "ACC1:acc#133" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load inst "ACC1:not#157" "not(10)" "INTERFACE" -attr xrf 34154 -attr oid 1318 -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(10)"
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "ACC1:not#157" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "ACC1:not#157" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "ACC1:not#157" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "ACC1:not#157" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "ACC1:not#157" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "ACC1:not#157" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "ACC1:not#157" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "ACC1:not#157" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "ACC1:not#157" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "ACC1:not#157" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva#9).itm}
+load net {ACC1:not#157.itm(0)} -pin  "ACC1:not#157" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(1)} -pin  "ACC1:not#157" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(2)} -pin  "ACC1:not#157" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(3)} -pin  "ACC1:not#157" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(4)} -pin  "ACC1:not#157" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(5)} -pin  "ACC1:not#157" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(6)} -pin  "ACC1:not#157" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(7)} -pin  "ACC1:not#157" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(8)} -pin  "ACC1:not#157" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(9)} -pin  "ACC1:not#157" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load inst "ACC1:acc#132" "add(10,1,2,0,11)" "INTERFACE" -attr xrf 34155 -attr oid 1319 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132} -attr area 11.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,1,10,1,11)"
+load net {ACC1:not#157.itm(0)} -pin  "ACC1:acc#132" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(1)} -pin  "ACC1:acc#132" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(2)} -pin  "ACC1:acc#132" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(3)} -pin  "ACC1:acc#132" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(4)} -pin  "ACC1:acc#132" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(5)} -pin  "ACC1:acc#132" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(6)} -pin  "ACC1:acc#132" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(7)} -pin  "ACC1:acc#132" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(8)} -pin  "ACC1:acc#132" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {ACC1:not#157.itm(9)} -pin  "ACC1:acc#132" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:not#157.itm}
+load net {PWR} -pin  "ACC1:acc#132" {B(0)} -attr @path {/sobel/sobel:core/C3_2}
+load net {PWR} -pin  "ACC1:acc#132" {B(1)} -attr @path {/sobel/sobel:core/C3_2}
+load net {ACC1:acc#132.itm(0)} -pin  "ACC1:acc#132" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(1)} -pin  "ACC1:acc#132" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(2)} -pin  "ACC1:acc#132" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(3)} -pin  "ACC1:acc#132" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(4)} -pin  "ACC1:acc#132" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(5)} -pin  "ACC1:acc#132" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(6)} -pin  "ACC1:acc#132" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(7)} -pin  "ACC1:acc#132" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(8)} -pin  "ACC1:acc#132" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(9)} -pin  "ACC1:acc#132" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(10)} -pin  "ACC1:acc#132" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load inst "ACC1-1:acc" "add(11,1,11,1,12)" "INTERFACE" -attr xrf 34156 -attr oid 1320 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,1,11,1,12)"
+load net {ACC1:acc#133.itm(0)} -pin  "ACC1-1:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(1)} -pin  "ACC1-1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(2)} -pin  "ACC1-1:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(3)} -pin  "ACC1-1:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(4)} -pin  "ACC1-1:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(5)} -pin  "ACC1-1:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(6)} -pin  "ACC1-1:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(7)} -pin  "ACC1-1:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(8)} -pin  "ACC1-1:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(9)} -pin  "ACC1-1:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#133.itm(10)} -pin  "ACC1-1:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#133.itm}
+load net {ACC1:acc#132.itm(0)} -pin  "ACC1-1:acc" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(1)} -pin  "ACC1-1:acc" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(2)} -pin  "ACC1-1:acc" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(3)} -pin  "ACC1-1:acc" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(4)} -pin  "ACC1-1:acc" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(5)} -pin  "ACC1-1:acc" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(6)} -pin  "ACC1-1:acc" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(7)} -pin  "ACC1-1:acc" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(8)} -pin  "ACC1-1:acc" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(9)} -pin  "ACC1-1:acc" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {ACC1:acc#132.itm(10)} -pin  "ACC1-1:acc" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#132.itm}
+load net {acc.psp#2.sva(0)} -pin  "ACC1-1:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(1)} -pin  "ACC1-1:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(2)} -pin  "ACC1-1:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(3)} -pin  "ACC1-1:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(4)} -pin  "ACC1-1:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(5)} -pin  "ACC1-1:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(6)} -pin  "ACC1-1:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(7)} -pin  "ACC1-1:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(8)} -pin  "ACC1-1:acc" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(9)} -pin  "ACC1-1:acc" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(10)} -pin  "ACC1-1:acc" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:acc" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/acc.psp#2.sva}
+load inst "ACC1-1:not#25" "not(1)" "INTERFACE" -attr xrf 34157 -attr oid 1321 -attr @path {/sobel/sobel:core/ACC1-1:not#25} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#140.itm(2)} -pin  "ACC1-1:not#25" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#14.sva)#3.itm}
+load net {ACC1-1:not#25.itm} -pin  "ACC1-1:not#25" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#25.itm}
+load inst "ACC1-1:not#162" "not(1)" "INTERFACE" -attr xrf 34158 -attr oid 1322 -attr @path {/sobel/sobel:core/ACC1-1:not#162} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#140.itm(3)} -pin  "ACC1-1:not#162" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#14.sva).itm}
+load net {ACC1-1:not#162.itm} -pin  "ACC1-1:not#162" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#162.itm}
+load inst "ACC1:acc#141" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 34159 -attr oid 1323 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#141" {A(0)} -attr @path {/sobel/sobel:core/conc#728.itm}
+load net {ACC1:acc#140.itm(1)} -pin  "ACC1:acc#141" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#728.itm}
+load net {PWR} -pin  "ACC1:acc#141" {A(2)} -attr @path {/sobel/sobel:core/conc#728.itm}
+load net {ACC1-1:not#162.itm} -pin  "ACC1:acc#141" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#459.itm}
+load net {ACC1-1:not#25.itm} -pin  "ACC1:acc#141" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#459.itm}
+load net {ACC1:acc#141.itm(0)} -pin  "ACC1:acc#141" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141.itm}
+load net {ACC1:acc#141.itm(1)} -pin  "ACC1:acc#141" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141.itm}
+load net {ACC1:acc#141.itm(2)} -pin  "ACC1:acc#141" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#141.itm}
+load inst "ACC1-1:not#145" "not(2)" "INTERFACE" -attr xrf 34160 -attr oid 1324 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#145} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#116.psp#1.sva(1)} -pin  "ACC1-1:not#145" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp#1.sva).itm}
+load net {ACC1:acc#116.psp#1.sva(2)} -pin  "ACC1-1:not#145" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp#1.sva).itm}
+load net {ACC1-1:not#145.itm(0)} -pin  "ACC1-1:not#145" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#145.itm}
+load net {ACC1-1:not#145.itm(1)} -pin  "ACC1-1:not#145" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#145.itm}
+load inst "ACC1:acc#140" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 34161 -attr oid 1325 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#140" {A(0)} -attr @path {/sobel/sobel:core/conc#729.itm}
+load net {ACC1-1:not#145.itm(0)} -pin  "ACC1:acc#140" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#729.itm}
+load net {ACC1-1:not#145.itm(1)} -pin  "ACC1:acc#140" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#729.itm}
+load net {PWR} -pin  "ACC1:acc#140" {B(0)} -attr @path {/sobel/sobel:core/conc#730.itm}
+load net {ACC1:acc#116.psp#1.sva(0)} -pin  "ACC1:acc#140" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#730.itm}
+load net {ACC1:acc#140.itm(0)} -pin  "ACC1:acc#140" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load net {ACC1:acc#140.itm(1)} -pin  "ACC1:acc#140" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load net {ACC1:acc#140.itm(2)} -pin  "ACC1:acc#140" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load net {ACC1:acc#140.itm(3)} -pin  "ACC1:acc#140" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#140.itm}
+load inst "ACC1-1:not#160" "not(1)" "INTERFACE" -attr xrf 34162 -attr oid 1326 -attr @path {/sobel/sobel:core/ACC1-1:not#160} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1-1:not#160" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#32.itm}
+load net {ACC1-1:not#160.itm} -pin  "ACC1-1:not#160" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#160.itm}
+load inst "ACC1-1:not#106" "not(1)" "INTERFACE" -attr xrf 34163 -attr oid 1327 -attr @path {/sobel/sobel:core/ACC1-1:not#106} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(1)} -pin  "ACC1-1:not#106" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#8.itm}
+load net {ACC1-1:not#106.itm} -pin  "ACC1-1:not#106" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#106.itm}
+load inst "ACC1:acc#136" "add(2,1,2,0,4)" "INTERFACE" -attr xrf 34164 -attr oid 1328 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {PWR} -pin  "ACC1:acc#136" {A(0)} -attr @path {/sobel/sobel:core/conc#732.itm}
+load net {ACC1-1:not#160.itm} -pin  "ACC1:acc#136" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#732.itm}
+load net {acc.psp#2.sva(8)} -pin  "ACC1:acc#136" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#448.itm}
+load net {ACC1-1:not#106.itm} -pin  "ACC1:acc#136" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#448.itm}
+load net {ACC1:acc#136.itm(0)} -pin  "ACC1:acc#136" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load net {ACC1:acc#136.itm(1)} -pin  "ACC1:acc#136" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load net {ACC1:acc#136.itm(2)} -pin  "ACC1:acc#136" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load net {ACC1:acc#136.itm(3)} -pin  "ACC1:acc#136" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#136.itm}
+load inst "ACC1:acc#138" "add(4,1,4,1,5)" "INTERFACE" -attr xrf 34165 -attr oid 1329 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5)"
+load net {PWR} -pin  "ACC1:acc#138" {A(0)} -attr @path {/sobel/sobel:core/conc#731.itm}
+load net {ACC1:acc#136.itm(1)} -pin  "ACC1:acc#138" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#731.itm}
+load net {ACC1:acc#136.itm(2)} -pin  "ACC1:acc#138" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#731.itm}
+load net {ACC1:acc#136.itm(3)} -pin  "ACC1:acc#138" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#731.itm}
+load net {acc.psp#2.sva(10)} -pin  "ACC1:acc#138" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#733.itm}
+load net {acc.psp#2.sva(0)} -pin  "ACC1:acc#138" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#733.itm}
+load net {GND} -pin  "ACC1:acc#138" {B(2)} -attr @path {/sobel/sobel:core/conc#733.itm}
+load net {PWR} -pin  "ACC1:acc#138" {B(3)} -attr @path {/sobel/sobel:core/conc#733.itm}
+load net {ACC1:acc#138.itm(0)} -pin  "ACC1:acc#138" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {ACC1:acc#138.itm(1)} -pin  "ACC1:acc#138" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {ACC1:acc#138.itm(2)} -pin  "ACC1:acc#138" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {ACC1:acc#138.itm(3)} -pin  "ACC1:acc#138" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load net {ACC1:acc#138.itm(4)} -pin  "ACC1:acc#138" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#138.itm}
+load inst "ACC1-1:not#107" "not(1)" "INTERFACE" -attr xrf 34166 -attr oid 1330 -attr @path {/sobel/sobel:core/ACC1-1:not#107} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(3)} -pin  "ACC1-1:not#107" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#7.itm}
+load net {ACC1-1:not#107.itm} -pin  "ACC1-1:not#107" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#107.itm}
+load inst "ACC1-1:not#109" "not(1)" "INTERFACE" -attr xrf 34167 -attr oid 1331 -attr @path {/sobel/sobel:core/ACC1-1:not#109} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(7)} -pin  "ACC1-1:not#109" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#3.itm}
+load net {ACC1-1:not#109.itm} -pin  "ACC1-1:not#109" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#109.itm}
+load inst "ACC1:acc#135" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34168 -attr oid 1332 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#135" {A(0)} -attr @path {/sobel/sobel:core/conc#735.itm}
+load net {acc.psp#2.sva(2)} -pin  "ACC1:acc#135" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#735.itm}
+load net {ACC1-1:not#109.itm} -pin  "ACC1:acc#135" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#446.itm}
+load net {ACC1-1:not#107.itm} -pin  "ACC1:acc#135" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#446.itm}
+load net {ACC1:acc#135.itm(0)} -pin  "ACC1:acc#135" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135.itm}
+load net {ACC1:acc#135.itm(1)} -pin  "ACC1:acc#135" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135.itm}
+load net {ACC1:acc#135.itm(2)} -pin  "ACC1:acc#135" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#135.itm}
+load inst "ACC1-1:not#108" "not(1)" "INTERFACE" -attr xrf 34169 -attr oid 1333 -attr @path {/sobel/sobel:core/ACC1-1:not#108} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(5)} -pin  "ACC1-1:not#108" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#2.itm}
+load net {ACC1-1:not#108.itm} -pin  "ACC1-1:not#108" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#108.itm}
+load inst "ACC1:acc#134" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34170 -attr oid 1334 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#134" {A(0)} -attr @path {/sobel/sobel:core/conc#736.itm}
+load net {acc.psp#2.sva(4)} -pin  "ACC1:acc#134" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#736.itm}
+load net {acc.psp#2.sva(6)} -pin  "ACC1:acc#134" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#444.itm}
+load net {ACC1-1:not#108.itm} -pin  "ACC1:acc#134" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#444.itm}
+load net {ACC1:acc#134.itm(0)} -pin  "ACC1:acc#134" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134.itm}
+load net {ACC1:acc#134.itm(1)} -pin  "ACC1:acc#134" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134.itm}
+load net {ACC1:acc#134.itm(2)} -pin  "ACC1:acc#134" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#134.itm}
+load inst "ACC1-1:not#110" "not(1)" "INTERFACE" -attr xrf 34171 -attr oid 1335 -attr @path {/sobel/sobel:core/ACC1-1:not#110} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.psp#2.sva(9)} -pin  "ACC1-1:not#110" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.psp#2.sva)#59.itm}
+load net {ACC1-1:not#110.itm} -pin  "ACC1-1:not#110" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#110.itm}
+load inst "ACC1:acc#137" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 34172 -attr oid 1336 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {PWR} -pin  "ACC1:acc#137" {A(0)} -attr @path {/sobel/sobel:core/conc#734.itm}
+load net {ACC1:acc#135.itm(1)} -pin  "ACC1:acc#137" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#734.itm}
+load net {ACC1:acc#135.itm(2)} -pin  "ACC1:acc#137" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#734.itm}
+load net {ACC1-1:not#110.itm} -pin  "ACC1:acc#137" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#450.itm}
+load net {ACC1:acc#134.itm(1)} -pin  "ACC1:acc#137" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#450.itm}
+load net {ACC1:acc#134.itm(2)} -pin  "ACC1:acc#137" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#450.itm}
+load net {ACC1:acc#137.itm(0)} -pin  "ACC1:acc#137" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load net {ACC1:acc#137.itm(1)} -pin  "ACC1:acc#137" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load net {ACC1:acc#137.itm(2)} -pin  "ACC1:acc#137" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load net {ACC1:acc#137.itm(3)} -pin  "ACC1:acc#137" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#137.itm}
+load inst "ACC1-1:acc#107" "add(4,-1,3,0,4)" "INTERFACE" -attr xrf 34173 -attr oid 1337 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#107} -attr area 5.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,1,6)"
+load net {ACC1:acc#138.itm(1)} -pin  "ACC1-1:acc#107" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#10.itm}
+load net {ACC1:acc#138.itm(2)} -pin  "ACC1-1:acc#107" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#10.itm}
+load net {ACC1:acc#138.itm(3)} -pin  "ACC1-1:acc#107" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#10.itm}
+load net {ACC1:acc#138.itm(4)} -pin  "ACC1-1:acc#107" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#10.itm}
+load net {ACC1:acc#137.itm(1)} -pin  "ACC1-1:acc#107" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#137.itm(2)} -pin  "ACC1-1:acc#107" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#137.itm(3)} -pin  "ACC1-1:acc#107" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc.itm}
+load net {ACC1:acc#107.psp#2.sva(0)} -pin  "ACC1-1:acc#107" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#2.sva}
+load net {ACC1:acc#107.psp#2.sva(1)} -pin  "ACC1-1:acc#107" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#2.sva}
+load net {ACC1:acc#107.psp#2.sva(2)} -pin  "ACC1-1:acc#107" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#2.sva}
+load net {ACC1:acc#107.psp#2.sva(3)} -pin  "ACC1-1:acc#107" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#107.psp#2.sva}
+load inst "ACC1-1:not#133" "not(1)" "INTERFACE" -attr xrf 34174 -attr oid 1338 -attr @path {/sobel/sobel:core/ACC1-1:not#133} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#107.psp#2.sva(1)} -pin  "ACC1-1:not#133" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#107.psp#2.sva)#4.itm}
+load net {ACC1-1:not#133.itm} -pin  "ACC1-1:not#133" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#133.itm}
+load inst "ACC1:acc#139" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34175 -attr oid 1339 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {PWR} -pin  "ACC1:acc#139" {A(0)} -attr @path {/sobel/sobel:core/conc#737.itm}
+load net {ACC1:acc#107.psp#2.sva(0)} -pin  "ACC1:acc#139" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#737.itm}
+load net {ACC1:acc#107.psp#2.sva(2)} -pin  "ACC1:acc#139" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#454.itm}
+load net {ACC1-1:not#133.itm} -pin  "ACC1:acc#139" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#454.itm}
+load net {ACC1:acc#139.itm(0)} -pin  "ACC1:acc#139" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139.itm}
+load net {ACC1:acc#139.itm(1)} -pin  "ACC1:acc#139" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139.itm}
+load net {ACC1:acc#139.itm(2)} -pin  "ACC1:acc#139" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#139.itm}
+load inst "ACC1-1:not#153" "not(1)" "INTERFACE" -attr xrf 34176 -attr oid 1340 -attr @path {/sobel/sobel:core/ACC1-1:not#153} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#107.psp#2.sva(3)} -pin  "ACC1-1:not#153" {A(0)} -attr @path {/sobel/sobel:core/slc(ACC1:acc#107.psp#2.sva)#1.itm}
+load net {ACC1-1:not#153.itm} -pin  "ACC1-1:not#153" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#153.itm}
+load inst "ACC1-1:acc#116" "add(2,0,1,1,3)" "INTERFACE" -attr xrf 34177 -attr oid 1341 -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:acc#116} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,1,4)"
+load net {ACC1:acc#139.itm(1)} -pin  "ACC1-1:acc#116" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1:acc#139.itm(2)} -pin  "ACC1-1:acc#116" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#11.itm}
+load net {ACC1-1:not#153.itm} -pin  "ACC1-1:acc#116" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-1:not#153.itm}
+load net {ACC1:acc#116.psp#1.sva(0)} -pin  "ACC1-1:acc#116" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp#1.sva}
+load net {ACC1:acc#116.psp#1.sva(1)} -pin  "ACC1-1:acc#116" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp#1.sva}
+load net {ACC1:acc#116.psp#1.sva(2)} -pin  "ACC1-1:acc#116" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#116.psp#1.sva}
+load inst "ACC1:acc#224" "add(2,0,2,0,3)" "INTERFACE" -attr xrf 34178 -attr oid 1342 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,3)"
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#224" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#858.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#224" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#858.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#224" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#833.itm}
+load net {acc.psp#2.sva(11)} -pin  "ACC1:acc#224" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:exs#833.itm}
+load net {ACC1:acc#224.cse(0)} -pin  "ACC1:acc#224" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#224.cse(1)} -pin  "ACC1:acc#224" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load net {ACC1:acc#224.cse(2)} -pin  "ACC1:acc#224" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#224.cse}
+load inst "ACC1-3:not#145" "not(2)" "INTERFACE" -attr xrf 34179 -attr oid 1343 -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#145} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(2)"
+load net {ACC1:acc#116.psp.sva(1)} -pin  "ACC1-3:not#145" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp.sva).itm}
+load net {ACC1:acc#116.psp.sva(2)} -pin  "ACC1-3:not#145" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#116.psp.sva).itm}
+load net {ACC1-3:not#145.itm(0)} -pin  "ACC1-3:not#145" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#145.itm}
+load net {ACC1-3:not#145.itm(1)} -pin  "ACC1-3:not#145" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1-3:not#145.itm}
+load inst "ACC1:acc#169" "add(3,1,2,0,4)" "INTERFACE" -attr xrf 34180 -attr oid 1344 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#169" {A(0)} -attr @path {/sobel/sobel:core/conc#738.itm}
+load net {ACC1-3:not#145.itm(0)} -pin  "ACC1:acc#169" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#738.itm}
+load net {ACC1-3:not#145.itm(1)} -pin  "ACC1:acc#169" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#738.itm}
+load net {PWR} -pin  "ACC1:acc#169" {B(0)} -attr @path {/sobel/sobel:core/conc#739.itm}
+load net {ACC1:acc#116.psp.sva(0)} -pin  "ACC1:acc#169" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#739.itm}
+load net {ACC1:acc#169.itm(0)} -pin  "ACC1:acc#169" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load net {ACC1:acc#169.itm(1)} -pin  "ACC1:acc#169" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load net {ACC1:acc#169.itm(2)} -pin  "ACC1:acc#169" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load net {ACC1:acc#169.itm(3)} -pin  "ACC1:acc#169" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#169.itm}
+load inst "not#17" "not(1)" "INTERFACE" -attr xrf 34181 -attr oid 1345 -attr @path {/sobel/sobel:core/not#17} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1.dfm#4} -pin  "not#17" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm#4}
+load net {not#17.itm} -pin  "not#17" {Z(0)} -attr @path {/sobel/sobel:core/not#17.itm}
+load inst "FRAME:for:and#2" "and(2,1)" "INTERFACE" -attr xrf 34182 -attr oid 1346 -attr @path {/sobel/sobel:core/FRAME:for:and#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {exit:FRAME.lpi#1.dfm#1} -pin  "FRAME:for:and#2" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1}
+load net {not#17.itm} -pin  "FRAME:for:and#2" {A1(0)} -attr @path {/sobel/sobel:core/not#17.itm}
+load net {FRAME:for:and#2.itm} -pin  "FRAME:for:and#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#2.itm}
+load inst "FRAME:acc" "add(7,0,8,-1,8)" "INTERFACE" -attr xrf 34183 -attr oid 1347 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc} -attr area 9.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,1,10)"
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {PWR} -pin  "FRAME:acc" {B(0)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(1)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(2)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(3)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(4)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(5)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(6)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(7)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {FRAME:acc.itm(0)} -pin  "FRAME:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(1)} -pin  "FRAME:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(2)} -pin  "FRAME:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(3)} -pin  "FRAME:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(4)} -pin  "FRAME:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(5)} -pin  "FRAME:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(6)} -pin  "FRAME:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(7)} -pin  "FRAME:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load inst "FRAME:not" "not(1)" "INTERFACE" -attr xrf 34184 -attr oid 1348 -attr @path {/sobel/sobel:core/FRAME:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc.itm(7)} -pin  "FRAME:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc.itm}
+load net {FRAME:not.itm} -pin  "FRAME:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load inst "mux#12" "mux(2,1)" "INTERFACE" -attr xrf 34185 -attr oid 1349 -attr @path {/sobel/sobel:core/mux#12} -attr area 0.920423 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2)"
+load net {FRAME:for:and#2.itm} -pin  "mux#12" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#2.itm}
+load net {FRAME:not.itm} -pin  "mux#12" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "mux#12" {S(0)} -attr @path {/sobel/sobel:core/FRAME:for:slc.itm}
+load net {exit:FRAME.lpi#1.dfm#1:mx0} -pin  "mux#12" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#1:mx0}
+load inst "FRAME:acc#4" "add(19,-1,1,0,19)" "INTERFACE" -attr xrf 34186 -attr oid 1350 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4} -attr area 20.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19)"
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "FRAME:acc#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "FRAME:acc#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "FRAME:acc#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "FRAME:acc#4" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "FRAME:acc#4" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "FRAME:acc#4" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "FRAME:acc#4" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "FRAME:acc#4" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "FRAME:acc#4" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "FRAME:acc#4" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "FRAME:acc#4" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "FRAME:acc#4" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "FRAME:acc#4" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "FRAME:acc#4" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "FRAME:acc#4" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "FRAME:acc#4" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "FRAME:acc#4" {A(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "FRAME:acc#4" {A(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "FRAME:acc#4" {A(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:acc#4" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:p#1.sva#1(0)} -pin  "FRAME:acc#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "FRAME:acc#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "FRAME:acc#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "FRAME:acc#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "FRAME:acc#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "FRAME:acc#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "FRAME:acc#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "FRAME:acc#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "FRAME:acc#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "FRAME:acc#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "FRAME:acc#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "FRAME:acc#4" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc#4" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc#4" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc#4" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc#4" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc#4" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc#4" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc#4" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load inst "FRAME:not#10" "not(1)" "INTERFACE" -attr xrf 34187 -attr oid 1351 -attr @path {/sobel/sobel:core/FRAME:not#10} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME#1.sva} -pin  "FRAME:not#10" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {FRAME:not#10.itm} -pin  "FRAME:not#10" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load inst "FRAME:for:and" "and(2,19)" "INTERFACE" -attr xrf 34188 -attr oid 1352 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and} -attr area 13.866816 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2)"
+load net {FRAME:p#1.lpi#1(0)} -pin  "FRAME:for:and" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "FRAME:for:and" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "FRAME:for:and" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "FRAME:for:and" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "FRAME:for:and" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "FRAME:for:and" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "FRAME:for:and" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "FRAME:for:and" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "FRAME:for:and" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "FRAME:for:and" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "FRAME:for:and" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "FRAME:for:and" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "FRAME:for:and" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "FRAME:for:and" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "FRAME:for:and" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "FRAME:for:and" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "FRAME:for:and" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "FRAME:for:and" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "FRAME:for:and" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:not#10.itm} -pin  "FRAME:for:and" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs.itm}
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "FRAME:for:and" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "FRAME:for:and" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "FRAME:for:and" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "FRAME:for:and" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "FRAME:for:and" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "FRAME:for:and" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "FRAME:for:and" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "FRAME:for:and" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "FRAME:for:and" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "FRAME:for:and" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "FRAME:for:and" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "FRAME:for:and" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "FRAME:for:and" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "FRAME:for:and" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "FRAME:for:and" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "FRAME:for:and" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "FRAME:for:and" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "FRAME:for:and" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "FRAME:for:and" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load inst "mux#13" "mux(2,12)" "INTERFACE" -attr xrf 34189 -attr oid 1353 -attr vt d -attr @path {/sobel/sobel:core/mux#13} -attr area 11.034076 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(12,1,2)"
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(0)} -pin  "mux#13" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(1)} -pin  "mux#13" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(2)} -pin  "mux#13" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(3)} -pin  "mux#13" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(4)} -pin  "mux#13" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(5)} -pin  "mux#13" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(6)} -pin  "mux#13" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(7)} -pin  "mux#13" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(8)} -pin  "mux#13" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(9)} -pin  "mux#13" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(10)} -pin  "mux#13" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm(11)} -pin  "mux#13" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm}
+load net {ACC1:acc#125.psp#1.sva(0)} -pin  "mux#13" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(1)} -pin  "mux#13" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(2)} -pin  "mux#13" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(3)} -pin  "mux#13" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(4)} -pin  "mux#13" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(5)} -pin  "mux#13" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(6)} -pin  "mux#13" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(7)} -pin  "mux#13" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(8)} -pin  "mux#13" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(9)} -pin  "mux#13" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(10)} -pin  "mux#13" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {ACC1:acc#125.psp#1.sva(11)} -pin  "mux#13" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.sva}
+load net {and.cse} -pin  "mux#13" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(0)} -pin  "mux#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(1)} -pin  "mux#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(2)} -pin  "mux#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(3)} -pin  "mux#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(4)} -pin  "mux#13" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(5)} -pin  "mux#13" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(6)} -pin  "mux#13" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(7)} -pin  "mux#13" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(8)} -pin  "mux#13" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(9)} -pin  "mux#13" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(10)} -pin  "mux#13" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load net {ACC1:acc#125.psp#1.lpi#1.dfm:mx0(11)} -pin  "mux#13" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#125.psp#1.lpi#1.dfm:mx0}
+load inst "mux#14" "mux(2,2)" "INTERFACE" -attr xrf 34190 -attr oid 1354 -attr vt d -attr @path {/sobel/sobel:core/mux#14} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {acc.imod#18.lpi#1.dfm.sg1(0)} -pin  "mux#14" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1}
+load net {acc.imod#18.lpi#1.dfm.sg1(1)} -pin  "mux#14" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1}
+load net {ACC1:acc#150.itm(2)} -pin  "mux#14" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva).itm}
+load net {ACC1:acc#150.itm(3)} -pin  "mux#14" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva).itm}
+load net {and.cse} -pin  "mux#14" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(0)} -pin  "mux#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1:mx0}
+load net {acc.imod#18.lpi#1.dfm.sg1:mx0(1)} -pin  "mux#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#18.lpi#1.dfm.sg1:mx0}
+load inst "mux#15" "mux(2,3)" "INTERFACE" -attr xrf 34191 -attr oid 1355 -attr vt d -attr @path {/sobel/sobel:core/mux#15} -attr area 2.759269 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(3,1,2)"
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(0)} -pin  "mux#15" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(1)} -pin  "mux#15" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1(2)} -pin  "mux#15" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1}
+load net {ACC1:acc#148.itm(2)} -pin  "mux#15" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.sva).itm}
+load net {ACC1:acc#148.itm(3)} -pin  "mux#15" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.sva).itm}
+load net {ACC1:acc#148.itm(4)} -pin  "mux#15" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#110.psp#2.sva).itm}
+load net {and.cse} -pin  "mux#15" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(0)} -pin  "mux#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(1)} -pin  "mux#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0(2)} -pin  "mux#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#110.psp#2.lpi#1.dfm.sg1:mx0}
+load inst "ACC1-1:not#57" "not(1)" "INTERFACE" -attr xrf 34192 -attr oid 1356 -attr @path {/sobel/sobel:core/ACC1-1:not#57} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#150.itm(2)} -pin  "ACC1-1:not#57" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva)#2.itm}
+load net {ACC1-1:not#57.itm} -pin  "ACC1-1:not#57" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#57.itm}
+load inst "ACC1-1:not#58" "not(1)" "INTERFACE" -attr xrf 34193 -attr oid 1357 -attr @path {/sobel/sobel:core/ACC1-1:not#58} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC1:acc#150.itm(3)} -pin  "ACC1-1:not#58" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#18.sva)#3.itm}
+load net {ACC1-1:not#58.itm} -pin  "ACC1-1:not#58" {Z(0)} -attr @path {/sobel/sobel:core/ACC1-1:not#58.itm}
+load inst "ACC1:acc#151" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 34194 -attr oid 1358 -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5)"
+load net {PWR} -pin  "ACC1:acc#151" {A(0)} -attr @path {/sobel/sobel:core/conc#740.itm}
+load net {ACC1:acc#150.itm(1)} -pin  "ACC1:acc#151" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#740.itm}
+load net {PWR} -pin  "ACC1:acc#151" {A(2)} -attr @path {/sobel/sobel:core/conc#740.itm}
+load net {ACC1-1:not#58.itm} -pin  "ACC1:acc#151" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#477.itm}
+load net {ACC1-1:not#57.itm} -pin  "ACC1:acc#151" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:conc#477.itm}
+load net {ACC1:acc#151.itm(0)} -pin  "ACC1:acc#151" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151.itm}
+load net {ACC1:acc#151.itm(1)} -pin  "ACC1:acc#151" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151.itm}
+load net {ACC1:acc#151.itm(2)} -pin  "ACC1:acc#151" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#151.itm}
+load inst "mux#16" "mux(2,2)" "INTERFACE" -attr xrf 34195 -attr oid 1359 -attr vt d -attr @path {/sobel/sobel:core/mux#16} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {acc.imod#20.lpi#1.dfm(0)} -pin  "mux#16" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm}
+load net {acc.imod#20.lpi#1.dfm(1)} -pin  "mux#16" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm}
+load net {ACC1:acc#151.itm(1)} -pin  "mux#16" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#21.itm}
+load net {ACC1:acc#151.itm(2)} -pin  "mux#16" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:slc#21.itm}
+load net {and.cse} -pin  "mux#16" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {acc.imod#20.lpi#1.dfm:mx0(0)} -pin  "mux#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm:mx0}
+load net {acc.imod#20.lpi#1.dfm:mx0(1)} -pin  "mux#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#20.lpi#1.dfm:mx0}
+load inst "mux#17" "mux(2,2)" "INTERFACE" -attr xrf 34196 -attr oid 1360 -attr vt d -attr @path {/sobel/sobel:core/mux#17} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(0)} -pin  "mux#17" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1(1)} -pin  "mux#17" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1}
+load net {ACC1:acc#118.psp#1.sva(1)} -pin  "mux#17" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp#1.sva)#2.itm}
+load net {ACC1:acc#118.psp#1.sva(2)} -pin  "mux#17" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(ACC1:acc#118.psp#1.sva)#2.itm}
+load net {and.cse} -pin  "mux#17" {S(0)} -attr @path {/sobel/sobel:core/and.cse}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(0)} -pin  "mux#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0}
+load net {ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0(1)} -pin  "mux#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC1:acc#118.psp#1.lpi#1.dfm.sg1:mx0}
+load inst "FRAME:for:nor" "nor(2,1)" "INTERFACE" -attr xrf 34197 -attr oid 1361 -attr @path {/sobel/sobel:core/FRAME:for:nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:nor" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#3.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nor" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#4.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:nor" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load inst "FRAME:for:not#8" "not(1)" "INTERFACE" -attr xrf 34198 -attr oid 1362 -attr @path {/sobel/sobel:core/FRAME:for:not#8} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#8" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#10.itm}
+load net {FRAME:for:not#8.itm} -pin  "FRAME:for:not#8" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#8.itm}
+load inst "FRAME:for:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 34199 -attr oid 1363 -attr @path {/sobel/sobel:core/FRAME:for:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {FRAME:for:not#8.itm} -pin  "FRAME:for:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#8.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#5.itm}
+load net {FRAME:for:nand#1.itm} -pin  "FRAME:for:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#1.itm}
+load inst "FRAME:for:or#4" "or(2,1)" "INTERFACE" -attr xrf 34200 -attr oid 1364 -attr @path {/sobel/sobel:core/FRAME:for:or#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {FRAME:for:nand#1.itm} -pin  "FRAME:for:or#4" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#1.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or#4" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:or#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#4.itm}
+load inst "FRAME:for:not#5" "not(1)" "INTERFACE" -attr xrf 34201 -attr oid 1365 -attr @path {/sobel/sobel:core/FRAME:for:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#5" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#8.itm}
+load net {FRAME:for:not#5.itm} -pin  "FRAME:for:not#5" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#5.itm}
+load inst "FRAME:for:nand" "nand(2,1)" "INTERFACE" -attr xrf 34202 -attr oid 1366 -attr @path {/sobel/sobel:core/FRAME:for:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#6.itm}
+load net {FRAME:for:not#5.itm} -pin  "FRAME:for:nand" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#5.itm}
+load net {FRAME:for:nand.itm} -pin  "FRAME:for:nand" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand.itm}
+load inst "FRAME:for:not#2" "not(1)" "INTERFACE" -attr xrf 34203 -attr oid 1367 -attr @path {/sobel/sobel:core/FRAME:for:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:not#2" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#7.itm}
+load net {FRAME:for:not#2.itm} -pin  "FRAME:for:not#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#2.itm}
+load inst "FRAME:for:and#3" "and(2,1)" "INTERFACE" -attr xrf 34204 -attr oid 1368 -attr @path {/sobel/sobel:core/FRAME:for:and#3} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:and#3" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#9.itm}
+load net {FRAME:for:not#2.itm} -pin  "FRAME:for:and#3" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#2.itm}
+load net {FRAME:for:and#3.itm} -pin  "FRAME:for:and#3" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#3.itm}
+load inst "FRAME:for:or#3" "or(3,1)" "INTERFACE" -attr xrf 34205 -attr oid 1369 -attr @path {/sobel/sobel:core/FRAME:for:or#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,3)"
+load net {FRAME:for:nand.itm} -pin  "FRAME:for:or#3" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or#3" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:and#3.itm} -pin  "FRAME:for:or#3" {A2(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#3.itm}
+load net {FRAME:for:or#3.itm} -pin  "FRAME:for:or#3" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#3.itm}
+load inst "nor" "nor(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {exit:FRAME:for.sva#1.st#1} -pin  "nor" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.sva#1.st#1}
+load net {exit:FRAME#1.sva} -pin  "nor" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {and.cse} -pin  "nor" {Z(0)} -attr @path {/sobel/sobel:core/and.cse}
+### END MODULE 
+
+module new "sobel" "orig"
+load portBus {vin:rsc.z(89:0)} input 90 {vin:rsc.z(89)} {vin:rsc.z(88)} {vin:rsc.z(87)} {vin:rsc.z(86)} {vin:rsc.z(85)} {vin:rsc.z(84)} {vin:rsc.z(83)} {vin:rsc.z(82)} {vin:rsc.z(81)} {vin:rsc.z(80)} {vin:rsc.z(79)} {vin:rsc.z(78)} {vin:rsc.z(77)} {vin:rsc.z(76)} {vin:rsc.z(75)} {vin:rsc.z(74)} {vin:rsc.z(73)} {vin:rsc.z(72)} {vin:rsc.z(71)} {vin:rsc.z(70)} {vin:rsc.z(69)} {vin:rsc.z(68)} {vin:rsc.z(67)} {vin:rsc.z(66)} {vin:rsc.z(65)} {vin:rsc.z(64)} {vin:rsc.z(63)} {vin:rsc.z(62)} {vin:rsc.z(61)} {vin:rsc.z(60)} {vin:rsc.z(59)} {vin:rsc.z(58)} {vin:rsc.z(57)} {vin:rsc.z(56)} {vin:rsc.z(55)} {vin:rsc.z(54)} {vin:rsc.z(53)} {vin:rsc.z(52)} {vin:rsc.z(51)} {vin:rsc.z(50)} {vin:rsc.z(49)} {vin:rsc.z(48)} {vin:rsc.z(47)} {vin:rsc.z(46)} {vin:rsc.z(45)} {vin:rsc.z(44)} {vin:rsc.z(43)} {vin:rsc.z(42)} {vin:rsc.z(41)} {vin:rsc.z(40)} {vin:rsc.z(39)} {vin:rsc.z(38)} {vin:rsc.z(37)} {vin:rsc.z(36)} {vin:rsc.z(35)} {vin:rsc.z(34)} {vin:rsc.z(33)} {vin:rsc.z(32)} {vin:rsc.z(31)} {vin:rsc.z(30)} {vin:rsc.z(29)} {vin:rsc.z(28)} {vin:rsc.z(27)} {vin:rsc.z(26)} {vin:rsc.z(25)} {vin:rsc.z(24)} {vin:rsc.z(23)} {vin:rsc.z(22)} {vin:rsc.z(21)} {vin:rsc.z(20)} {vin:rsc.z(19)} {vin:rsc.z(18)} {vin:rsc.z(17)} {vin:rsc.z(16)} {vin:rsc.z(15)} {vin:rsc.z(14)} {vin:rsc.z(13)} {vin:rsc.z(12)} {vin:rsc.z(11)} {vin:rsc.z(10)} {vin:rsc.z(9)} {vin:rsc.z(8)} {vin:rsc.z(7)} {vin:rsc.z(6)} {vin:rsc.z(5)} {vin:rsc.z(4)} {vin:rsc.z(3)} {vin:rsc.z(2)} {vin:rsc.z(1)} {vin:rsc.z(0)} -attr xrf 34206 -attr oid 1370 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load portBus {vout:rsc.z(29:0)} output 30 {vout:rsc.z(29)} {vout:rsc.z(28)} {vout:rsc.z(27)} {vout:rsc.z(26)} {vout:rsc.z(25)} {vout:rsc.z(24)} {vout:rsc.z(23)} {vout:rsc.z(22)} {vout:rsc.z(21)} {vout:rsc.z(20)} {vout:rsc.z(19)} {vout:rsc.z(18)} {vout:rsc.z(17)} {vout:rsc.z(16)} {vout:rsc.z(15)} {vout:rsc.z(14)} {vout:rsc.z(13)} {vout:rsc.z(12)} {vout:rsc.z(11)} {vout:rsc.z(10)} {vout:rsc.z(9)} {vout:rsc.z(8)} {vout:rsc.z(7)} {vout:rsc.z(6)} {vout:rsc.z(5)} {vout:rsc.z(4)} {vout:rsc.z(3)} {vout:rsc.z(2)} {vout:rsc.z(1)} {vout:rsc.z(0)} -attr xrf 34207 -attr oid 1371 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load port {clk} input -attr xrf 34208 -attr oid 1372 -attr vt d -attr @path {/sobel/clk}
+load port {en} input -attr xrf 34209 -attr oid 1373 -attr vt d -attr @path {/sobel/en}
+load port {arst_n} input -attr xrf 34210 -attr oid 1374 -attr vt d -attr @path {/sobel/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(89:0)} output 90 {d(89)} {d(88)} {d(87)} {d(86)} {d(85)} {d(84)} {d(83)} {d(82)} {d(81)} {d(80)} {d(79)} {d(78)} {d(77)} {d(76)} {d(75)} {d(74)} {d(73)} {d(72)} {d(71)} {d(70)} {d(69)} {d(68)} {d(67)} {d(66)} {d(65)} {d(64)} {d(63)} {d(62)} {d(61)} {d(60)} {d(59)} {d(58)} {d(57)} {d(56)} {d(55)} {d(54)} {d(53)} {d(52)} {d(51)} {d(50)} {d(49)} {d(48)} {d(47)} {d(46)} {d(45)} {d(44)} {d(43)} {d(42)} {d(41)} {d(40)} {d(39)} {d(38)} {d(37)} {d(36)} {d(35)} {d(34)} {d(33)} {d(32)} {d(31)} {d(30)} {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(89:0)} input 90 {z(89)} {z(88)} {z(87)} {z(86)} {z(85)} {z(84)} {z(83)} {z(82)} {z(81)} {z(80)} {z(79)} {z(78)} {z(77)} {z(76)} {z(75)} {z(74)} {z(73)} {z(72)} {z(71)} {z(70)} {z(69)} {z(68)} {z(67)} {z(66)} {z(65)} {z(64)} {z(63)} {z(62)} {z(61)} {z(60)} {z(59)} {z(58)} {z(57)} {z(56)} {z(55)} {z(54)} {z(53)} {z(52)} {z(51)} {z(50)} {z(49)} {z(48)} {z(47)} {z(46)} {z(45)} {z(44)} {z(43)} {z(42)} {z(41)} {z(40)} {z(39)} {z(38)} {z(37)} {z(36)} {z(35)} {z(34)} {z(33)} {z(32)} {z(31)} {z(30)} {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(29:0)} input 30 {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(29:0)} output 30 {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "sobel:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} \
+     portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} \
+
+load net {vin:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d#1} 90 {vin:rsc:mgc_in_wire.d#1(0)} {vin:rsc:mgc_in_wire.d#1(1)} {vin:rsc:mgc_in_wire.d#1(2)} {vin:rsc:mgc_in_wire.d#1(3)} {vin:rsc:mgc_in_wire.d#1(4)} {vin:rsc:mgc_in_wire.d#1(5)} {vin:rsc:mgc_in_wire.d#1(6)} {vin:rsc:mgc_in_wire.d#1(7)} {vin:rsc:mgc_in_wire.d#1(8)} {vin:rsc:mgc_in_wire.d#1(9)} {vin:rsc:mgc_in_wire.d#1(10)} {vin:rsc:mgc_in_wire.d#1(11)} {vin:rsc:mgc_in_wire.d#1(12)} {vin:rsc:mgc_in_wire.d#1(13)} {vin:rsc:mgc_in_wire.d#1(14)} {vin:rsc:mgc_in_wire.d#1(15)} {vin:rsc:mgc_in_wire.d#1(16)} {vin:rsc:mgc_in_wire.d#1(17)} {vin:rsc:mgc_in_wire.d#1(18)} {vin:rsc:mgc_in_wire.d#1(19)} {vin:rsc:mgc_in_wire.d#1(20)} {vin:rsc:mgc_in_wire.d#1(21)} {vin:rsc:mgc_in_wire.d#1(22)} {vin:rsc:mgc_in_wire.d#1(23)} {vin:rsc:mgc_in_wire.d#1(24)} {vin:rsc:mgc_in_wire.d#1(25)} {vin:rsc:mgc_in_wire.d#1(26)} {vin:rsc:mgc_in_wire.d#1(27)} {vin:rsc:mgc_in_wire.d#1(28)} {vin:rsc:mgc_in_wire.d#1(29)} {vin:rsc:mgc_in_wire.d#1(30)} {vin:rsc:mgc_in_wire.d#1(31)} {vin:rsc:mgc_in_wire.d#1(32)} {vin:rsc:mgc_in_wire.d#1(33)} {vin:rsc:mgc_in_wire.d#1(34)} {vin:rsc:mgc_in_wire.d#1(35)} {vin:rsc:mgc_in_wire.d#1(36)} {vin:rsc:mgc_in_wire.d#1(37)} {vin:rsc:mgc_in_wire.d#1(38)} {vin:rsc:mgc_in_wire.d#1(39)} {vin:rsc:mgc_in_wire.d#1(40)} {vin:rsc:mgc_in_wire.d#1(41)} {vin:rsc:mgc_in_wire.d#1(42)} {vin:rsc:mgc_in_wire.d#1(43)} {vin:rsc:mgc_in_wire.d#1(44)} {vin:rsc:mgc_in_wire.d#1(45)} {vin:rsc:mgc_in_wire.d#1(46)} {vin:rsc:mgc_in_wire.d#1(47)} {vin:rsc:mgc_in_wire.d#1(48)} {vin:rsc:mgc_in_wire.d#1(49)} {vin:rsc:mgc_in_wire.d#1(50)} {vin:rsc:mgc_in_wire.d#1(51)} {vin:rsc:mgc_in_wire.d#1(52)} {vin:rsc:mgc_in_wire.d#1(53)} {vin:rsc:mgc_in_wire.d#1(54)} {vin:rsc:mgc_in_wire.d#1(55)} {vin:rsc:mgc_in_wire.d#1(56)} {vin:rsc:mgc_in_wire.d#1(57)} {vin:rsc:mgc_in_wire.d#1(58)} {vin:rsc:mgc_in_wire.d#1(59)} {vin:rsc:mgc_in_wire.d#1(60)} {vin:rsc:mgc_in_wire.d#1(61)} {vin:rsc:mgc_in_wire.d#1(62)} {vin:rsc:mgc_in_wire.d#1(63)} {vin:rsc:mgc_in_wire.d#1(64)} {vin:rsc:mgc_in_wire.d#1(65)} {vin:rsc:mgc_in_wire.d#1(66)} {vin:rsc:mgc_in_wire.d#1(67)} {vin:rsc:mgc_in_wire.d#1(68)} {vin:rsc:mgc_in_wire.d#1(69)} {vin:rsc:mgc_in_wire.d#1(70)} {vin:rsc:mgc_in_wire.d#1(71)} {vin:rsc:mgc_in_wire.d#1(72)} {vin:rsc:mgc_in_wire.d#1(73)} {vin:rsc:mgc_in_wire.d#1(74)} {vin:rsc:mgc_in_wire.d#1(75)} {vin:rsc:mgc_in_wire.d#1(76)} {vin:rsc:mgc_in_wire.d#1(77)} {vin:rsc:mgc_in_wire.d#1(78)} {vin:rsc:mgc_in_wire.d#1(79)} {vin:rsc:mgc_in_wire.d#1(80)} {vin:rsc:mgc_in_wire.d#1(81)} {vin:rsc:mgc_in_wire.d#1(82)} {vin:rsc:mgc_in_wire.d#1(83)} {vin:rsc:mgc_in_wire.d#1(84)} {vin:rsc:mgc_in_wire.d#1(85)} {vin:rsc:mgc_in_wire.d#1(86)} {vin:rsc:mgc_in_wire.d#1(87)} {vin:rsc:mgc_in_wire.d#1(88)} {vin:rsc:mgc_in_wire.d#1(89)} -attr xrf 34211 -attr oid 1375 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d#1} 30 {vout:rsc:mgc_out_stdreg.d#1(0)} {vout:rsc:mgc_out_stdreg.d#1(1)} {vout:rsc:mgc_out_stdreg.d#1(2)} {vout:rsc:mgc_out_stdreg.d#1(3)} {vout:rsc:mgc_out_stdreg.d#1(4)} {vout:rsc:mgc_out_stdreg.d#1(5)} {vout:rsc:mgc_out_stdreg.d#1(6)} {vout:rsc:mgc_out_stdreg.d#1(7)} {vout:rsc:mgc_out_stdreg.d#1(8)} {vout:rsc:mgc_out_stdreg.d#1(9)} {vout:rsc:mgc_out_stdreg.d#1(10)} {vout:rsc:mgc_out_stdreg.d#1(11)} {vout:rsc:mgc_out_stdreg.d#1(12)} {vout:rsc:mgc_out_stdreg.d#1(13)} {vout:rsc:mgc_out_stdreg.d#1(14)} {vout:rsc:mgc_out_stdreg.d#1(15)} {vout:rsc:mgc_out_stdreg.d#1(16)} {vout:rsc:mgc_out_stdreg.d#1(17)} {vout:rsc:mgc_out_stdreg.d#1(18)} {vout:rsc:mgc_out_stdreg.d#1(19)} {vout:rsc:mgc_out_stdreg.d#1(20)} {vout:rsc:mgc_out_stdreg.d#1(21)} {vout:rsc:mgc_out_stdreg.d#1(22)} {vout:rsc:mgc_out_stdreg.d#1(23)} {vout:rsc:mgc_out_stdreg.d#1(24)} {vout:rsc:mgc_out_stdreg.d#1(25)} {vout:rsc:mgc_out_stdreg.d#1(26)} {vout:rsc:mgc_out_stdreg.d#1(27)} {vout:rsc:mgc_out_stdreg.d#1(28)} {vout:rsc:mgc_out_stdreg.d#1(29)} -attr xrf 34212 -attr oid 1376 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -attr vt d
+load net {vin:rsc.z(13)} -attr vt d
+load net {vin:rsc.z(14)} -attr vt d
+load net {vin:rsc.z(15)} -attr vt d
+load net {vin:rsc.z(16)} -attr vt d
+load net {vin:rsc.z(17)} -attr vt d
+load net {vin:rsc.z(18)} -attr vt d
+load net {vin:rsc.z(19)} -attr vt d
+load net {vin:rsc.z(20)} -attr vt d
+load net {vin:rsc.z(21)} -attr vt d
+load net {vin:rsc.z(22)} -attr vt d
+load net {vin:rsc.z(23)} -attr vt d
+load net {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -attr vt d
+load net {vin:rsc.z(28)} -attr vt d
+load net {vin:rsc.z(29)} -attr vt d
+load net {vin:rsc.z(30)} -attr vt d
+load net {vin:rsc.z(31)} -attr vt d
+load net {vin:rsc.z(32)} -attr vt d
+load net {vin:rsc.z(33)} -attr vt d
+load net {vin:rsc.z(34)} -attr vt d
+load net {vin:rsc.z(35)} -attr vt d
+load net {vin:rsc.z(36)} -attr vt d
+load net {vin:rsc.z(37)} -attr vt d
+load net {vin:rsc.z(38)} -attr vt d
+load net {vin:rsc.z(39)} -attr vt d
+load net {vin:rsc.z(40)} -attr vt d
+load net {vin:rsc.z(41)} -attr vt d
+load net {vin:rsc.z(42)} -attr vt d
+load net {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -attr vt d
+load net {vin:rsc.z(45)} -attr vt d
+load net {vin:rsc.z(46)} -attr vt d
+load net {vin:rsc.z(47)} -attr vt d
+load net {vin:rsc.z(48)} -attr vt d
+load net {vin:rsc.z(49)} -attr vt d
+load net {vin:rsc.z(50)} -attr vt d
+load net {vin:rsc.z(51)} -attr vt d
+load net {vin:rsc.z(52)} -attr vt d
+load net {vin:rsc.z(53)} -attr vt d
+load net {vin:rsc.z(54)} -attr vt d
+load net {vin:rsc.z(55)} -attr vt d
+load net {vin:rsc.z(56)} -attr vt d
+load net {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -attr vt d
+load net {vin:rsc.z(63)} -attr vt d
+load net {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -attr vt d
+load net {vin:rsc.z(68)} -attr vt d
+load net {vin:rsc.z(69)} -attr vt d
+load net {vin:rsc.z(70)} -attr vt d
+load net {vin:rsc.z(71)} -attr vt d
+load net {vin:rsc.z(72)} -attr vt d
+load net {vin:rsc.z(73)} -attr vt d
+load net {vin:rsc.z(74)} -attr vt d
+load net {vin:rsc.z(75)} -attr vt d
+load net {vin:rsc.z(76)} -attr vt d
+load net {vin:rsc.z(77)} -attr vt d
+load net {vin:rsc.z(78)} -attr vt d
+load net {vin:rsc.z(79)} -attr vt d
+load net {vin:rsc.z(80)} -attr vt d
+load net {vin:rsc.z(81)} -attr vt d
+load net {vin:rsc.z(82)} -attr vt d
+load net {vin:rsc.z(83)} -attr vt d
+load net {vin:rsc.z(84)} -attr vt d
+load net {vin:rsc.z(85)} -attr vt d
+load net {vin:rsc.z(86)} -attr vt d
+load net {vin:rsc.z(87)} -attr vt d
+load net {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 34213 -attr oid 1377 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(0)} -port {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -port {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -port {vin:rsc.z(2)} -attr vt d
+load net {vin:rsc.z(3)} -port {vin:rsc.z(3)} -attr vt d
+load net {vin:rsc.z(4)} -port {vin:rsc.z(4)} -attr vt d
+load net {vin:rsc.z(5)} -port {vin:rsc.z(5)} -attr vt d
+load net {vin:rsc.z(6)} -port {vin:rsc.z(6)} -attr vt d
+load net {vin:rsc.z(7)} -port {vin:rsc.z(7)} -attr vt d
+load net {vin:rsc.z(8)} -port {vin:rsc.z(8)} -attr vt d
+load net {vin:rsc.z(9)} -port {vin:rsc.z(9)} -attr vt d
+load net {vin:rsc.z(10)} -port {vin:rsc.z(10)} -attr vt d
+load net {vin:rsc.z(11)} -port {vin:rsc.z(11)} -attr vt d
+load net {vin:rsc.z(12)} -port {vin:rsc.z(12)} -attr vt d
+load net {vin:rsc.z(13)} -port {vin:rsc.z(13)} -attr vt d
+load net {vin:rsc.z(14)} -port {vin:rsc.z(14)} -attr vt d
+load net {vin:rsc.z(15)} -port {vin:rsc.z(15)} -attr vt d
+load net {vin:rsc.z(16)} -port {vin:rsc.z(16)} -attr vt d
+load net {vin:rsc.z(17)} -port {vin:rsc.z(17)} -attr vt d
+load net {vin:rsc.z(18)} -port {vin:rsc.z(18)} -attr vt d
+load net {vin:rsc.z(19)} -port {vin:rsc.z(19)} -attr vt d
+load net {vin:rsc.z(20)} -port {vin:rsc.z(20)} -attr vt d
+load net {vin:rsc.z(21)} -port {vin:rsc.z(21)} -attr vt d
+load net {vin:rsc.z(22)} -port {vin:rsc.z(22)} -attr vt d
+load net {vin:rsc.z(23)} -port {vin:rsc.z(23)} -attr vt d
+load net {vin:rsc.z(24)} -port {vin:rsc.z(24)} -attr vt d
+load net {vin:rsc.z(25)} -port {vin:rsc.z(25)} -attr vt d
+load net {vin:rsc.z(26)} -port {vin:rsc.z(26)} -attr vt d
+load net {vin:rsc.z(27)} -port {vin:rsc.z(27)} -attr vt d
+load net {vin:rsc.z(28)} -port {vin:rsc.z(28)} -attr vt d
+load net {vin:rsc.z(29)} -port {vin:rsc.z(29)} -attr vt d
+load net {vin:rsc.z(30)} -port {vin:rsc.z(30)} -attr vt d
+load net {vin:rsc.z(31)} -port {vin:rsc.z(31)} -attr vt d
+load net {vin:rsc.z(32)} -port {vin:rsc.z(32)} -attr vt d
+load net {vin:rsc.z(33)} -port {vin:rsc.z(33)} -attr vt d
+load net {vin:rsc.z(34)} -port {vin:rsc.z(34)} -attr vt d
+load net {vin:rsc.z(35)} -port {vin:rsc.z(35)} -attr vt d
+load net {vin:rsc.z(36)} -port {vin:rsc.z(36)} -attr vt d
+load net {vin:rsc.z(37)} -port {vin:rsc.z(37)} -attr vt d
+load net {vin:rsc.z(38)} -port {vin:rsc.z(38)} -attr vt d
+load net {vin:rsc.z(39)} -port {vin:rsc.z(39)} -attr vt d
+load net {vin:rsc.z(40)} -port {vin:rsc.z(40)} -attr vt d
+load net {vin:rsc.z(41)} -port {vin:rsc.z(41)} -attr vt d
+load net {vin:rsc.z(42)} -port {vin:rsc.z(42)} -attr vt d
+load net {vin:rsc.z(43)} -port {vin:rsc.z(43)} -attr vt d
+load net {vin:rsc.z(44)} -port {vin:rsc.z(44)} -attr vt d
+load net {vin:rsc.z(45)} -port {vin:rsc.z(45)} -attr vt d
+load net {vin:rsc.z(46)} -port {vin:rsc.z(46)} -attr vt d
+load net {vin:rsc.z(47)} -port {vin:rsc.z(47)} -attr vt d
+load net {vin:rsc.z(48)} -port {vin:rsc.z(48)} -attr vt d
+load net {vin:rsc.z(49)} -port {vin:rsc.z(49)} -attr vt d
+load net {vin:rsc.z(50)} -port {vin:rsc.z(50)} -attr vt d
+load net {vin:rsc.z(51)} -port {vin:rsc.z(51)} -attr vt d
+load net {vin:rsc.z(52)} -port {vin:rsc.z(52)} -attr vt d
+load net {vin:rsc.z(53)} -port {vin:rsc.z(53)} -attr vt d
+load net {vin:rsc.z(54)} -port {vin:rsc.z(54)} -attr vt d
+load net {vin:rsc.z(55)} -port {vin:rsc.z(55)} -attr vt d
+load net {vin:rsc.z(56)} -port {vin:rsc.z(56)} -attr vt d
+load net {vin:rsc.z(57)} -port {vin:rsc.z(57)} -attr vt d
+load net {vin:rsc.z(58)} -port {vin:rsc.z(58)} -attr vt d
+load net {vin:rsc.z(59)} -port {vin:rsc.z(59)} -attr vt d
+load net {vin:rsc.z(60)} -port {vin:rsc.z(60)} -attr vt d
+load net {vin:rsc.z(61)} -port {vin:rsc.z(61)} -attr vt d
+load net {vin:rsc.z(62)} -port {vin:rsc.z(62)} -attr vt d
+load net {vin:rsc.z(63)} -port {vin:rsc.z(63)} -attr vt d
+load net {vin:rsc.z(64)} -port {vin:rsc.z(64)} -attr vt d
+load net {vin:rsc.z(65)} -port {vin:rsc.z(65)} -attr vt d
+load net {vin:rsc.z(66)} -port {vin:rsc.z(66)} -attr vt d
+load net {vin:rsc.z(67)} -port {vin:rsc.z(67)} -attr vt d
+load net {vin:rsc.z(68)} -port {vin:rsc.z(68)} -attr vt d
+load net {vin:rsc.z(69)} -port {vin:rsc.z(69)} -attr vt d
+load net {vin:rsc.z(70)} -port {vin:rsc.z(70)} -attr vt d
+load net {vin:rsc.z(71)} -port {vin:rsc.z(71)} -attr vt d
+load net {vin:rsc.z(72)} -port {vin:rsc.z(72)} -attr vt d
+load net {vin:rsc.z(73)} -port {vin:rsc.z(73)} -attr vt d
+load net {vin:rsc.z(74)} -port {vin:rsc.z(74)} -attr vt d
+load net {vin:rsc.z(75)} -port {vin:rsc.z(75)} -attr vt d
+load net {vin:rsc.z(76)} -port {vin:rsc.z(76)} -attr vt d
+load net {vin:rsc.z(77)} -port {vin:rsc.z(77)} -attr vt d
+load net {vin:rsc.z(78)} -port {vin:rsc.z(78)} -attr vt d
+load net {vin:rsc.z(79)} -port {vin:rsc.z(79)} -attr vt d
+load net {vin:rsc.z(80)} -port {vin:rsc.z(80)} -attr vt d
+load net {vin:rsc.z(81)} -port {vin:rsc.z(81)} -attr vt d
+load net {vin:rsc.z(82)} -port {vin:rsc.z(82)} -attr vt d
+load net {vin:rsc.z(83)} -port {vin:rsc.z(83)} -attr vt d
+load net {vin:rsc.z(84)} -port {vin:rsc.z(84)} -attr vt d
+load net {vin:rsc.z(85)} -port {vin:rsc.z(85)} -attr vt d
+load net {vin:rsc.z(86)} -port {vin:rsc.z(86)} -attr vt d
+load net {vin:rsc.z(87)} -port {vin:rsc.z(87)} -attr vt d
+load net {vin:rsc.z(88)} -port {vin:rsc.z(88)} -attr vt d
+load net {vin:rsc.z(89)} -port {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 34214 -attr oid 1378 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vout:rsc.z(0)} -attr vt d
+load net {vout:rsc.z(1)} -attr vt d
+load net {vout:rsc.z(2)} -attr vt d
+load net {vout:rsc.z(3)} -attr vt d
+load net {vout:rsc.z(4)} -attr vt d
+load net {vout:rsc.z(5)} -attr vt d
+load net {vout:rsc.z(6)} -attr vt d
+load net {vout:rsc.z(7)} -attr vt d
+load net {vout:rsc.z(8)} -attr vt d
+load net {vout:rsc.z(9)} -attr vt d
+load net {vout:rsc.z(10)} -attr vt d
+load net {vout:rsc.z(11)} -attr vt d
+load net {vout:rsc.z(12)} -attr vt d
+load net {vout:rsc.z(13)} -attr vt d
+load net {vout:rsc.z(14)} -attr vt d
+load net {vout:rsc.z(15)} -attr vt d
+load net {vout:rsc.z(16)} -attr vt d
+load net {vout:rsc.z(17)} -attr vt d
+load net {vout:rsc.z(18)} -attr vt d
+load net {vout:rsc.z(19)} -attr vt d
+load net {vout:rsc.z(20)} -attr vt d
+load net {vout:rsc.z(21)} -attr vt d
+load net {vout:rsc.z(22)} -attr vt d
+load net {vout:rsc.z(23)} -attr vt d
+load net {vout:rsc.z(24)} -attr vt d
+load net {vout:rsc.z(25)} -attr vt d
+load net {vout:rsc.z(26)} -attr vt d
+load net {vout:rsc.z(27)} -attr vt d
+load net {vout:rsc.z(28)} -attr vt d
+load net {vout:rsc.z(29)} -attr vt d
+load netBundle {vout:rsc.z} 30 {vout:rsc.z(0)} {vout:rsc.z(1)} {vout:rsc.z(2)} {vout:rsc.z(3)} {vout:rsc.z(4)} {vout:rsc.z(5)} {vout:rsc.z(6)} {vout:rsc.z(7)} {vout:rsc.z(8)} {vout:rsc.z(9)} {vout:rsc.z(10)} {vout:rsc.z(11)} {vout:rsc.z(12)} {vout:rsc.z(13)} {vout:rsc.z(14)} {vout:rsc.z(15)} {vout:rsc.z(16)} {vout:rsc.z(17)} {vout:rsc.z(18)} {vout:rsc.z(19)} {vout:rsc.z(20)} {vout:rsc.z(21)} {vout:rsc.z(22)} {vout:rsc.z(23)} {vout:rsc.z(24)} {vout:rsc.z(25)} {vout:rsc.z(26)} {vout:rsc.z(27)} {vout:rsc.z(28)} {vout:rsc.z(29)} -attr xrf 34215 -attr oid 1379 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(0)} -port {vout:rsc.z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -port {vout:rsc.z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -port {vout:rsc.z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -port {vout:rsc.z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -port {vout:rsc.z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -port {vout:rsc.z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -port {vout:rsc.z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -port {vout:rsc.z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -port {vout:rsc.z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -port {vout:rsc.z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -port {vout:rsc.z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -port {vout:rsc.z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -port {vout:rsc.z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -port {vout:rsc.z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -port {vout:rsc.z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -port {vout:rsc.z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -port {vout:rsc.z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -port {vout:rsc.z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -port {vout:rsc.z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -port {vout:rsc.z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -port {vout:rsc.z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -port {vout:rsc.z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -port {vout:rsc.z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -port {vout:rsc.z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -port {vout:rsc.z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -port {vout:rsc.z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -port {vout:rsc.z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -port {vout:rsc.z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -port {vout:rsc.z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -port {vout:rsc.z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {clk} -attr xrf 34216 -attr oid 1380
+load net {clk} -port {clk} -attr xrf 34217 -attr oid 1381
+load net {en} -attr xrf 34218 -attr oid 1382
+load net {en} -port {en} -attr xrf 34219 -attr oid 1383
+load net {arst_n} -attr xrf 34220 -attr oid 1384
+load net {arst_n} -port {arst_n} -attr xrf 34221 -attr oid 1385
+load inst "sobel:core:inst" "sobel:core" "orig" -attr xrf 34222 -attr oid 1386 -attr vt dc -attr @path {/sobel/sobel:core:inst} -attr area 6772.495085 -attr delay 15.831847 -attr hier "/sobel/sobel:core" -pg 1 -lvl 3
+load net {clk} -pin  "sobel:core:inst" {clk#1} -attr xrf 34223 -attr oid 1387 -attr @path {/sobel/clk}
+load net {en} -pin  "sobel:core:inst" {en#1} -attr xrf 34224 -attr oid 1388 -attr @path {/sobel/en}
+load net {arst_n} -pin  "sobel:core:inst" {arst_n#1} -attr xrf 34225 -attr oid 1389 -attr @path {/sobel/arst_n}
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(8)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(9)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(10)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(11)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(12)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(13)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(14)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(15)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(16)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(17)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(18)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(19)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(20)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(21)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(22)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(23)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(24)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(25)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(26)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(27)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(28)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(29)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(30)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(31)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(32)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(33)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(34)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(35)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(36)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(37)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(38)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(39)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(40)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(41)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(42)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(43)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(44)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(45)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(46)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(47)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(48)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(49)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(50)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(51)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(52)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(53)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(54)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(55)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(56)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(57)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(58)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(59)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(60)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(61)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(62)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(63)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(64)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(65)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(66)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(67)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(68)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(69)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(70)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(71)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(72)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(73)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(74)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(75)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(76)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(77)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(78)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(79)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(80)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(81)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(82)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(83)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(84)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(85)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(86)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(87)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(88)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(89)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(8)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(9)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(10)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(11)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(12)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(13)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(14)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(15)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(16)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(17)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(18)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(19)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(20)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(21)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(22)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(23)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(24)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(25)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(26)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(27)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(28)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(29)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load inst "vin:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" -attr xrf 34226 -attr oid 1390 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,90)" -pg 1 -lvl 1
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "vin:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "vin:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "vin:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "vin:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "vin:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "vin:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "vin:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "vin:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "vin:rsc:mgc_in_wire" {d(8)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "vin:rsc:mgc_in_wire" {d(9)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "vin:rsc:mgc_in_wire" {d(10)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "vin:rsc:mgc_in_wire" {d(11)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "vin:rsc:mgc_in_wire" {d(12)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "vin:rsc:mgc_in_wire" {d(13)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "vin:rsc:mgc_in_wire" {d(14)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "vin:rsc:mgc_in_wire" {d(15)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "vin:rsc:mgc_in_wire" {d(16)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "vin:rsc:mgc_in_wire" {d(17)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "vin:rsc:mgc_in_wire" {d(18)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "vin:rsc:mgc_in_wire" {d(19)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "vin:rsc:mgc_in_wire" {d(20)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "vin:rsc:mgc_in_wire" {d(21)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "vin:rsc:mgc_in_wire" {d(22)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "vin:rsc:mgc_in_wire" {d(23)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "vin:rsc:mgc_in_wire" {d(24)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "vin:rsc:mgc_in_wire" {d(25)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "vin:rsc:mgc_in_wire" {d(26)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "vin:rsc:mgc_in_wire" {d(27)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "vin:rsc:mgc_in_wire" {d(28)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "vin:rsc:mgc_in_wire" {d(29)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "vin:rsc:mgc_in_wire" {d(30)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "vin:rsc:mgc_in_wire" {d(31)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "vin:rsc:mgc_in_wire" {d(32)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "vin:rsc:mgc_in_wire" {d(33)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "vin:rsc:mgc_in_wire" {d(34)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "vin:rsc:mgc_in_wire" {d(35)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "vin:rsc:mgc_in_wire" {d(36)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "vin:rsc:mgc_in_wire" {d(37)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "vin:rsc:mgc_in_wire" {d(38)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "vin:rsc:mgc_in_wire" {d(39)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "vin:rsc:mgc_in_wire" {d(40)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "vin:rsc:mgc_in_wire" {d(41)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "vin:rsc:mgc_in_wire" {d(42)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "vin:rsc:mgc_in_wire" {d(43)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "vin:rsc:mgc_in_wire" {d(44)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "vin:rsc:mgc_in_wire" {d(45)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "vin:rsc:mgc_in_wire" {d(46)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "vin:rsc:mgc_in_wire" {d(47)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "vin:rsc:mgc_in_wire" {d(48)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "vin:rsc:mgc_in_wire" {d(49)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "vin:rsc:mgc_in_wire" {d(50)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "vin:rsc:mgc_in_wire" {d(51)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "vin:rsc:mgc_in_wire" {d(52)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "vin:rsc:mgc_in_wire" {d(53)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "vin:rsc:mgc_in_wire" {d(54)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "vin:rsc:mgc_in_wire" {d(55)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "vin:rsc:mgc_in_wire" {d(56)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "vin:rsc:mgc_in_wire" {d(57)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "vin:rsc:mgc_in_wire" {d(58)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "vin:rsc:mgc_in_wire" {d(59)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "vin:rsc:mgc_in_wire" {d(60)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "vin:rsc:mgc_in_wire" {d(61)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "vin:rsc:mgc_in_wire" {d(62)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "vin:rsc:mgc_in_wire" {d(63)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "vin:rsc:mgc_in_wire" {d(64)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "vin:rsc:mgc_in_wire" {d(65)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "vin:rsc:mgc_in_wire" {d(66)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "vin:rsc:mgc_in_wire" {d(67)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "vin:rsc:mgc_in_wire" {d(68)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "vin:rsc:mgc_in_wire" {d(69)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "vin:rsc:mgc_in_wire" {d(70)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "vin:rsc:mgc_in_wire" {d(71)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "vin:rsc:mgc_in_wire" {d(72)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "vin:rsc:mgc_in_wire" {d(73)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "vin:rsc:mgc_in_wire" {d(74)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "vin:rsc:mgc_in_wire" {d(75)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "vin:rsc:mgc_in_wire" {d(76)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "vin:rsc:mgc_in_wire" {d(77)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "vin:rsc:mgc_in_wire" {d(78)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "vin:rsc:mgc_in_wire" {d(79)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "vin:rsc:mgc_in_wire" {d(80)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "vin:rsc:mgc_in_wire" {d(81)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "vin:rsc:mgc_in_wire" {d(82)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "vin:rsc:mgc_in_wire" {d(83)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "vin:rsc:mgc_in_wire" {d(84)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "vin:rsc:mgc_in_wire" {d(85)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "vin:rsc:mgc_in_wire" {d(86)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "vin:rsc:mgc_in_wire" {d(87)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "vin:rsc:mgc_in_wire" {d(88)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "vin:rsc:mgc_in_wire" {d(89)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc.z(0)} -pin  "vin:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(1)} -pin  "vin:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(2)} -pin  "vin:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(3)} -pin  "vin:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(4)} -pin  "vin:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(5)} -pin  "vin:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(6)} -pin  "vin:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(7)} -pin  "vin:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(8)} -pin  "vin:rsc:mgc_in_wire" {z(8)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(9)} -pin  "vin:rsc:mgc_in_wire" {z(9)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(10)} -pin  "vin:rsc:mgc_in_wire" {z(10)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(11)} -pin  "vin:rsc:mgc_in_wire" {z(11)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(12)} -pin  "vin:rsc:mgc_in_wire" {z(12)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(13)} -pin  "vin:rsc:mgc_in_wire" {z(13)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(14)} -pin  "vin:rsc:mgc_in_wire" {z(14)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(15)} -pin  "vin:rsc:mgc_in_wire" {z(15)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(16)} -pin  "vin:rsc:mgc_in_wire" {z(16)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(17)} -pin  "vin:rsc:mgc_in_wire" {z(17)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(18)} -pin  "vin:rsc:mgc_in_wire" {z(18)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(19)} -pin  "vin:rsc:mgc_in_wire" {z(19)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(20)} -pin  "vin:rsc:mgc_in_wire" {z(20)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(21)} -pin  "vin:rsc:mgc_in_wire" {z(21)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(22)} -pin  "vin:rsc:mgc_in_wire" {z(22)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(23)} -pin  "vin:rsc:mgc_in_wire" {z(23)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(24)} -pin  "vin:rsc:mgc_in_wire" {z(24)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(25)} -pin  "vin:rsc:mgc_in_wire" {z(25)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(26)} -pin  "vin:rsc:mgc_in_wire" {z(26)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(27)} -pin  "vin:rsc:mgc_in_wire" {z(27)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(28)} -pin  "vin:rsc:mgc_in_wire" {z(28)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(29)} -pin  "vin:rsc:mgc_in_wire" {z(29)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(30)} -pin  "vin:rsc:mgc_in_wire" {z(30)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(31)} -pin  "vin:rsc:mgc_in_wire" {z(31)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(32)} -pin  "vin:rsc:mgc_in_wire" {z(32)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(33)} -pin  "vin:rsc:mgc_in_wire" {z(33)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(34)} -pin  "vin:rsc:mgc_in_wire" {z(34)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(35)} -pin  "vin:rsc:mgc_in_wire" {z(35)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(36)} -pin  "vin:rsc:mgc_in_wire" {z(36)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(37)} -pin  "vin:rsc:mgc_in_wire" {z(37)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(38)} -pin  "vin:rsc:mgc_in_wire" {z(38)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(39)} -pin  "vin:rsc:mgc_in_wire" {z(39)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(40)} -pin  "vin:rsc:mgc_in_wire" {z(40)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(41)} -pin  "vin:rsc:mgc_in_wire" {z(41)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(42)} -pin  "vin:rsc:mgc_in_wire" {z(42)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(43)} -pin  "vin:rsc:mgc_in_wire" {z(43)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(44)} -pin  "vin:rsc:mgc_in_wire" {z(44)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(45)} -pin  "vin:rsc:mgc_in_wire" {z(45)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(46)} -pin  "vin:rsc:mgc_in_wire" {z(46)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(47)} -pin  "vin:rsc:mgc_in_wire" {z(47)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(48)} -pin  "vin:rsc:mgc_in_wire" {z(48)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(49)} -pin  "vin:rsc:mgc_in_wire" {z(49)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(50)} -pin  "vin:rsc:mgc_in_wire" {z(50)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(51)} -pin  "vin:rsc:mgc_in_wire" {z(51)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(52)} -pin  "vin:rsc:mgc_in_wire" {z(52)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(53)} -pin  "vin:rsc:mgc_in_wire" {z(53)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(54)} -pin  "vin:rsc:mgc_in_wire" {z(54)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(55)} -pin  "vin:rsc:mgc_in_wire" {z(55)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(56)} -pin  "vin:rsc:mgc_in_wire" {z(56)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(57)} -pin  "vin:rsc:mgc_in_wire" {z(57)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(58)} -pin  "vin:rsc:mgc_in_wire" {z(58)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(59)} -pin  "vin:rsc:mgc_in_wire" {z(59)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(60)} -pin  "vin:rsc:mgc_in_wire" {z(60)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(61)} -pin  "vin:rsc:mgc_in_wire" {z(61)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(62)} -pin  "vin:rsc:mgc_in_wire" {z(62)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(63)} -pin  "vin:rsc:mgc_in_wire" {z(63)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(64)} -pin  "vin:rsc:mgc_in_wire" {z(64)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(65)} -pin  "vin:rsc:mgc_in_wire" {z(65)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(66)} -pin  "vin:rsc:mgc_in_wire" {z(66)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(67)} -pin  "vin:rsc:mgc_in_wire" {z(67)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(68)} -pin  "vin:rsc:mgc_in_wire" {z(68)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(69)} -pin  "vin:rsc:mgc_in_wire" {z(69)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(70)} -pin  "vin:rsc:mgc_in_wire" {z(70)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(71)} -pin  "vin:rsc:mgc_in_wire" {z(71)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(72)} -pin  "vin:rsc:mgc_in_wire" {z(72)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(73)} -pin  "vin:rsc:mgc_in_wire" {z(73)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(74)} -pin  "vin:rsc:mgc_in_wire" {z(74)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(75)} -pin  "vin:rsc:mgc_in_wire" {z(75)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(76)} -pin  "vin:rsc:mgc_in_wire" {z(76)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(77)} -pin  "vin:rsc:mgc_in_wire" {z(77)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(78)} -pin  "vin:rsc:mgc_in_wire" {z(78)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(79)} -pin  "vin:rsc:mgc_in_wire" {z(79)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(80)} -pin  "vin:rsc:mgc_in_wire" {z(80)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(81)} -pin  "vin:rsc:mgc_in_wire" {z(81)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(82)} -pin  "vin:rsc:mgc_in_wire" {z(82)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(83)} -pin  "vin:rsc:mgc_in_wire" {z(83)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(84)} -pin  "vin:rsc:mgc_in_wire" {z(84)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(85)} -pin  "vin:rsc:mgc_in_wire" {z(85)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(86)} -pin  "vin:rsc:mgc_in_wire" {z(86)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(87)} -pin  "vin:rsc:mgc_in_wire" {z(87)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(88)} -pin  "vin:rsc:mgc_in_wire" {z(88)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(89)} -pin  "vin:rsc:mgc_in_wire" {z(89)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load inst "vout:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" -attr xrf 34227 -attr oid 1391 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(2,30)" -pg 1 -lvl 1002
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "vout:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "vout:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "vout:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "vout:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "vout:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "vout:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "vout:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "vout:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "vout:rsc:mgc_out_stdreg" {d(8)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "vout:rsc:mgc_out_stdreg" {d(9)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "vout:rsc:mgc_out_stdreg" {d(10)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "vout:rsc:mgc_out_stdreg" {d(11)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "vout:rsc:mgc_out_stdreg" {d(12)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "vout:rsc:mgc_out_stdreg" {d(13)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "vout:rsc:mgc_out_stdreg" {d(14)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "vout:rsc:mgc_out_stdreg" {d(15)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "vout:rsc:mgc_out_stdreg" {d(16)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "vout:rsc:mgc_out_stdreg" {d(17)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "vout:rsc:mgc_out_stdreg" {d(18)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "vout:rsc:mgc_out_stdreg" {d(19)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "vout:rsc:mgc_out_stdreg" {d(20)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "vout:rsc:mgc_out_stdreg" {d(21)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "vout:rsc:mgc_out_stdreg" {d(22)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "vout:rsc:mgc_out_stdreg" {d(23)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "vout:rsc:mgc_out_stdreg" {d(24)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "vout:rsc:mgc_out_stdreg" {d(25)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "vout:rsc:mgc_out_stdreg" {d(26)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "vout:rsc:mgc_out_stdreg" {d(27)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "vout:rsc:mgc_out_stdreg" {d(28)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "vout:rsc:mgc_out_stdreg" {d(29)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc.z(0)} -pin  "vout:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -pin  "vout:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -pin  "vout:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -pin  "vout:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -pin  "vout:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -pin  "vout:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -pin  "vout:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -pin  "vout:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -pin  "vout:rsc:mgc_out_stdreg" {z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -pin  "vout:rsc:mgc_out_stdreg" {z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -pin  "vout:rsc:mgc_out_stdreg" {z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -pin  "vout:rsc:mgc_out_stdreg" {z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -pin  "vout:rsc:mgc_out_stdreg" {z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -pin  "vout:rsc:mgc_out_stdreg" {z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -pin  "vout:rsc:mgc_out_stdreg" {z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -pin  "vout:rsc:mgc_out_stdreg" {z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -pin  "vout:rsc:mgc_out_stdreg" {z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -pin  "vout:rsc:mgc_out_stdreg" {z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -pin  "vout:rsc:mgc_out_stdreg" {z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -pin  "vout:rsc:mgc_out_stdreg" {z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -pin  "vout:rsc:mgc_out_stdreg" {z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -pin  "vout:rsc:mgc_out_stdreg" {z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -pin  "vout:rsc:mgc_out_stdreg" {z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -pin  "vout:rsc:mgc_out_stdreg" {z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -pin  "vout:rsc:mgc_out_stdreg" {z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -pin  "vout:rsc:mgc_out_stdreg" {z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -pin  "vout:rsc:mgc_out_stdreg" {z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -pin  "vout:rsc:mgc_out_stdreg" {z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -pin  "vout:rsc:mgc_out_stdreg" {z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -pin  "vout:rsc:mgc_out_stdreg" {z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+### END MODULE 
+
diff --git a/Sobel/sobel.v9/concat_rtl.v b/Sobel/sobel.v9/concat_rtl.v
new file mode 100644
index 0000000..974ecad
--- /dev/null
+++ b/Sobel/sobel.v9/concat_rtl.v
@@ -0,0 +1,2160 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 15:38:55 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  wire and_dcpl_1;
+  wire or_dcpl_2;
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [14:0] b_1_sg1_lpi_1;
+  reg [15:0] b_0_lpi_1;
+  reg [15:0] b_2_lpi_1;
+  reg [14:0] g_1_sg1_lpi_1;
+  reg [15:0] g_0_lpi_1;
+  reg [15:0] g_2_lpi_1;
+  reg [14:0] r_1_sg1_lpi_1;
+  reg [15:0] r_0_lpi_1;
+  reg [15:0] r_2_lpi_1;
+  reg [1:0] i_6_lpi_1;
+  reg exit_FRAME_for_lpi_1;
+  reg [1:0] i_7_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [89:0] regs_regs_2_lpi_1_dfm;
+  reg exit_FRAME_lpi_1_dfm_2;
+  reg exit_FRAME_for_1_lpi_1_dfm_4;
+  reg [10:0] FRAME_mul_2_itm_1;
+  wire [21:0] nl_FRAME_mul_2_itm_1;
+  reg [8:0] FRAME_mul_3_itm_1;
+  wire [17:0] nl_FRAME_mul_3_itm_1;
+  reg [5:0] green_slc_green_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_18_itm_1;
+  wire [5:0] nl_FRAME_acc_18_itm_1;
+  reg FRAME_slc_acc_imod_5_4_itm_1;
+  reg green_slc_green_2_sg1_12_itm_1;
+  reg [10:0] FRAME_mul_4_itm_1;
+  wire [21:0] nl_FRAME_mul_4_itm_1;
+  reg [8:0] FRAME_mul_5_itm_1;
+  wire [17:0] nl_FRAME_mul_5_itm_1;
+  reg [5:0] blue_slc_blue_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_30_itm_1;
+  wire [5:0] nl_FRAME_acc_30_itm_1;
+  reg FRAME_slc_acc_imod_7_4_itm_1;
+  reg blue_slc_blue_2_sg1_12_itm_1;
+  reg [8:0] FRAME_mul_1_itm_1;
+  wire [17:0] nl_FRAME_mul_1_itm_1;
+  reg [5:0] red_slc_red_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_37_itm_1;
+  wire [5:0] nl_FRAME_acc_37_itm_1;
+  reg FRAME_slc_acc_imod_3_4_itm_1;
+  reg exit_FRAME_for_lpi_1_dfm_st_1;
+  reg exit_FRAME_for_1_sva_2_st_1;
+  reg main_stage_0_2;
+  reg [1:0] FRAME_acc_41_itm_1_sg2;
+  wire [2:0] nl_FRAME_acc_41_itm_1_sg2;
+  reg [1:0] FRAME_acc_41_itm_1_sg1;
+  reg [5:0] FRAME_acc_41_itm_3;
+  wire [6:0] nl_FRAME_acc_41_itm_3;
+  wire or_4_cse;
+  wire or_9_cse;
+  wire exit_FRAME_for_1_lpi_1_dfm_5;
+  wire [1:0] FRAME_for_1_acc_itm;
+  wire [2:0] nl_FRAME_for_1_acc_itm;
+  wire [7:0] FRAME_acc_itm;
+  wire [8:0] nl_FRAME_acc_itm;
+  wire [11:0] FRAME_acc_3_psp_sva;
+  wire [13:0] nl_FRAME_acc_3_psp_sva;
+  wire [11:0] FRAME_acc_4_psp_sva;
+  wire [13:0] nl_FRAME_acc_4_psp_sva;
+  wire exit_FRAME_for_lpi_1_dfm;
+  wire [1:0] i_7_sva;
+  wire [2:0] nl_i_7_sva;
+  wire exit_FRAME_for_1_lpi_1_dfm_4_mx0;
+  wire [89:0] regs_regs_2_lpi_1_dfm_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire exit_FRAME_lpi_1_dfm_2_mx0;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [5:0] acc_imod_3_sva;
+  wire [7:0] nl_acc_imod_3_sva;
+  wire [9:0] FRAME_mul_sdt;
+  wire [19:0] nl_FRAME_mul_sdt;
+  wire [5:0] acc_imod_7_sva;
+  wire [7:0] nl_acc_imod_7_sva;
+  wire [5:0] acc_imod_5_sva;
+  wire [7:0] nl_acc_imod_5_sva;
+  wire [14:0] b_1_sg1_lpi_1_dfm;
+  wire [15:0] b_2_sva_1;
+  wire [16:0] nl_b_2_sva_1;
+  wire [15:0] b_0_sva_1;
+  wire [16:0] nl_b_0_sva_1;
+  wire [14:0] g_1_sg1_lpi_1_dfm;
+  wire [15:0] g_2_sva_1;
+  wire [16:0] nl_g_2_sva_1;
+  wire [15:0] g_0_sva_1;
+  wire [16:0] nl_g_0_sva_1;
+  wire [14:0] r_1_sg1_lpi_1_dfm;
+  wire [15:0] r_2_sva_1;
+  wire [16:0] nl_r_2_sva_1;
+  wire [15:0] r_0_sva_1;
+  wire [16:0] nl_r_0_sva_1;
+  wire [15:0] b_2_lpi_1_dfm;
+  wire FRAME_for_1_nor_cse;
+  wire [15:0] g_2_lpi_1_dfm;
+  wire [15:0] r_2_lpi_1_dfm;
+  wire [15:0] b_0_lpi_1_dfm;
+  wire [15:0] g_0_lpi_1_dfm;
+  wire [15:0] r_0_lpi_1_dfm;
+  wire [1:0] i_6_sva_1;
+  wire [2:0] nl_i_6_sva_1;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire FRAME_for_nor_cse;
+  wire FRAME_for_and_18_seb;
+  wire [1:0] FRAME_for_acc_5_tmp;
+  wire [2:0] nl_FRAME_for_acc_5_tmp;
+  wire not_24;
+  wire [15:0] ACC2_3_acc_1_itm;
+  wire [16:0] nl_ACC2_3_acc_1_itm;
+  wire [15:0] ACC2_3_acc_3_itm;
+  wire [16:0] nl_ACC2_3_acc_3_itm;
+  wire [15:0] ACC2_3_acc_2_itm;
+  wire [16:0] nl_ACC2_3_acc_2_itm;
+  wire FRAME_for_1_or_1_itm;
+  wire FRAME_for_1_or_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_itm;
+  wire FRAME_for_or_5_itm;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+
+  wire[9:0] regs_operator_23_mux_nl;
+  wire[9:0] regs_operator_17_mux_nl;
+  wire[9:0] regs_operator_22_mux_nl;
+  wire[9:0] regs_operator_16_mux_nl;
+  wire[9:0] regs_operator_21_mux_nl;
+  wire[9:0] regs_operator_15_mux_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_3_psp_sva = (conv_u2s_11_12(FRAME_mul_2_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_3_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(green_slc_green_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_18_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_5_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({green_slc_green_2_sg1_12_itm_1
+      , 3'b0 , ({{2{green_slc_green_2_sg1_12_itm_1}}, green_slc_green_2_sg1_12_itm_1})
+      , 1'b0 , green_slc_green_2_sg1_12_itm_1}));
+  assign FRAME_acc_3_psp_sva = nl_FRAME_acc_3_psp_sva[11:0];
+  assign nl_FRAME_acc_4_psp_sva = (conv_u2s_11_12(FRAME_mul_4_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_5_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(blue_slc_blue_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_30_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_7_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({blue_slc_blue_2_sg1_12_itm_1
+      , 3'b0 , ({{2{blue_slc_blue_2_sg1_12_itm_1}}, blue_slc_blue_2_sg1_12_itm_1})
+      , 1'b0 , blue_slc_blue_2_sg1_12_itm_1}));
+  assign FRAME_acc_4_psp_sva = nl_FRAME_acc_4_psp_sva[11:0];
+  assign nl_FRAME_for_1_acc_itm = i_7_sva + 2'b1;
+  assign FRAME_for_1_acc_itm = nl_FRAME_for_1_acc_itm[1:0];
+  assign exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_lpi_1 & not_24;
+  assign nl_i_7_sva = i_7_lpi_1 + 2'b1;
+  assign i_7_sva = nl_i_7_sva[1:0];
+  assign exit_FRAME_for_1_lpi_1_dfm_4_mx0 = MUX_s_1_2_2({(exit_FRAME_for_1_lpi_1_dfm_5
+      | (FRAME_acc_itm[7])) , exit_FRAME_for_1_lpi_1_dfm_5}, or_9_cse);
+  assign regs_regs_2_lpi_1_dfm_mx0 = MUX_v_90_2_2({regs_regs_1_sva , regs_regs_2_lpi_1_dfm},
+      and_dcpl_1);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_dcpl_1);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_dcpl_1);
+  assign nl_FRAME_acc_itm = conv_u2s_7_8(FRAME_p_1_sva_1[18:12]) + 8'b10110101;
+  assign FRAME_acc_itm = nl_FRAME_acc_itm[7:0];
+  assign exit_FRAME_lpi_1_dfm_2_mx0 = MUX_s_1_2_2({(~ (FRAME_acc_itm[7])) , (exit_FRAME_lpi_1_dfm_2
+      & not_24)}, or_9_cse);
+  assign exit_FRAME_for_1_lpi_1_dfm_5 = (~ (FRAME_for_1_acc_itm[1])) & exit_FRAME_for_lpi_1_dfm;
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign nl_acc_imod_3_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC2_3_acc_1_itm[9:7])
+      + conv_u2u_3_4(~ (ACC2_3_acc_1_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC2_3_acc_1_itm[15])) , 1'b1 , (~ (ACC2_3_acc_1_itm[15]))}) + conv_u2u_2_4(ACC2_3_acc_1_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC2_3_acc_1_itm[3:1]) + conv_u2u_3_4(~ (ACC2_3_acc_1_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_3_sva = nl_acc_imod_3_sva[5:0];
+  assign nl_ACC2_3_acc_1_itm = ({(r_1_sg1_lpi_1_dfm + (r_2_sva_1[15:1])) , (r_2_sva_1[0])})
+      + r_0_sva_1;
+  assign ACC2_3_acc_1_itm = nl_ACC2_3_acc_1_itm[15:0];
+  assign nl_FRAME_mul_sdt = conv_u2u_2_10(ACC2_3_acc_1_itm[14:13]) * 10'b111000111;
+  assign FRAME_mul_sdt = nl_FRAME_mul_sdt[9:0];
+  assign nl_ACC2_3_acc_3_itm = ({(b_1_sg1_lpi_1_dfm + (b_2_sva_1[15:1])) , (b_2_sva_1[0])})
+      + b_0_sva_1;
+  assign ACC2_3_acc_3_itm = nl_ACC2_3_acc_3_itm[15:0];
+  assign nl_acc_imod_7_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC2_3_acc_3_itm[9:7])
+      + conv_u2u_3_4(~ (ACC2_3_acc_3_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC2_3_acc_3_itm[15])) , 1'b1 , (~ (ACC2_3_acc_3_itm[15]))}) + conv_u2u_2_4(ACC2_3_acc_3_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC2_3_acc_3_itm[3:1]) + conv_u2u_3_4(~ (ACC2_3_acc_3_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_7_sva = nl_acc_imod_7_sva[5:0];
+  assign nl_ACC2_3_acc_2_itm = ({(g_1_sg1_lpi_1_dfm + (g_2_sva_1[15:1])) , (g_2_sva_1[0])})
+      + g_0_sva_1;
+  assign ACC2_3_acc_2_itm = nl_ACC2_3_acc_2_itm[15:0];
+  assign nl_acc_imod_5_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC2_3_acc_2_itm[9:7])
+      + conv_u2u_3_4(~ (ACC2_3_acc_2_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC2_3_acc_2_itm[15])) , 1'b1 , (~ (ACC2_3_acc_2_itm[15]))}) + conv_u2u_2_4(ACC2_3_acc_2_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC2_3_acc_2_itm[3:1]) + conv_u2u_3_4(~ (ACC2_3_acc_2_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_5_sva = nl_acc_imod_5_sva[5:0];
+  assign b_1_sg1_lpi_1_dfm = b_1_sg1_lpi_1 & ({{14{not_24}}, not_24});
+  assign regs_operator_23_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[69:60]) , (regs_regs_1_sva[69:60])
+      , (regs_regs_2_lpi_1_dfm[69:60]) , 10'b0}, i_7_lpi_1);
+  assign nl_b_2_sva_1 = b_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_23_mux_nl)
+      * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_or_1_itm})));
+  assign b_2_sva_1 = nl_b_2_sva_1[15:0];
+  assign regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[9:0]) , (regs_regs_1_sva[9:0])
+      , (regs_regs_2_lpi_1_dfm[9:0]) , 10'b0}, i_7_lpi_1);
+  assign nl_b_0_sva_1 = b_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_17_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_1_or_itm})));
+  assign b_0_sva_1 = nl_b_0_sva_1[15:0];
+  assign g_1_sg1_lpi_1_dfm = g_1_sg1_lpi_1 & ({{14{not_24}}, not_24});
+  assign regs_operator_22_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[79:70]) , (regs_regs_1_sva[79:70])
+      , (regs_regs_2_lpi_1_dfm[79:70]) , 10'b0}, i_7_lpi_1);
+  assign nl_g_2_sva_1 = g_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_22_mux_nl)
+      * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_or_1_itm})));
+  assign g_2_sva_1 = nl_g_2_sva_1[15:0];
+  assign regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[19:10]) , (regs_regs_1_sva[19:10])
+      , (regs_regs_2_lpi_1_dfm[19:10]) , 10'b0}, i_7_lpi_1);
+  assign nl_g_0_sva_1 = g_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_16_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_1_or_itm})));
+  assign g_0_sva_1 = nl_g_0_sva_1[15:0];
+  assign r_1_sg1_lpi_1_dfm = r_1_sg1_lpi_1 & ({{14{not_24}}, not_24});
+  assign regs_operator_21_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[89:80]) , (regs_regs_1_sva[89:80])
+      , (regs_regs_2_lpi_1_dfm[89:80]) , 10'b0}, i_7_lpi_1);
+  assign nl_r_2_sva_1 = r_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_21_mux_nl)
+      * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_or_1_itm})));
+  assign r_2_sva_1 = nl_r_2_sva_1[15:0];
+  assign regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[29:20]) , (regs_regs_1_sva[29:20])
+      , (regs_regs_2_lpi_1_dfm[29:20]) , 10'b0}, i_7_lpi_1);
+  assign nl_r_0_sva_1 = r_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_15_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_1_or_itm})));
+  assign r_0_sva_1 = nl_r_0_sva_1[15:0];
+  assign b_2_lpi_1_dfm = b_2_lpi_1 & ({{15{not_24}}, not_24});
+  assign FRAME_for_1_nor_cse = ~((i_7_lpi_1[1]) | (i_7_lpi_1[0]));
+  assign g_2_lpi_1_dfm = g_2_lpi_1 & ({{15{not_24}}, not_24});
+  assign r_2_lpi_1_dfm = r_2_lpi_1 & ({{15{not_24}}, not_24});
+  assign b_0_lpi_1_dfm = b_0_lpi_1 & ({{15{not_24}}, not_24});
+  assign g_0_lpi_1_dfm = g_0_lpi_1 & ({{15{not_24}}, not_24});
+  assign r_0_lpi_1_dfm = r_0_lpi_1 & ({{15{not_24}}, not_24});
+  assign nl_i_6_sva_1 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_1 = nl_i_6_sva_1[1:0];
+  assign i_6_lpi_1_dfm = i_6_lpi_1 & ({{1{not_24}}, not_24});
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_and_18_seb = (FRAME_for_acc_5_tmp[1]) & (FRAME_for_acc_5_tmp[0]);
+  assign nl_FRAME_for_acc_5_tmp = i_6_lpi_1_dfm + 2'b11;
+  assign FRAME_for_acc_5_tmp = nl_FRAME_for_acc_5_tmp[1:0];
+  assign not_24 = ~(exit_FRAME_for_1_lpi_1_dfm_4 | exit_FRAME_1_sva);
+  assign FRAME_for_1_or_1_itm = (~((~ (i_7_lpi_1[1])) & (i_7_lpi_1[0]))) | FRAME_for_1_nor_cse;
+  assign FRAME_for_1_or_itm = (~((i_7_lpi_1[0]) & (~ (i_7_lpi_1[1])))) | FRAME_for_1_nor_cse
+      | ((i_7_lpi_1[1]) & (~ (i_7_lpi_1[0])));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) | FRAME_for_nor_cse;
+  assign FRAME_for_or_5_itm = (FRAME_for_acc_5_tmp[1]) | (FRAME_for_acc_5_tmp[0])
+      | FRAME_for_and_18_seb;
+  assign and_dcpl_1 = ~(exit_FRAME_1_sva | exit_FRAME_for_1_lpi_1_dfm_4);
+  assign or_dcpl_2 = exit_FRAME_1_sva | exit_FRAME_for_1_lpi_1_dfm_4;
+  assign or_4_cse = or_dcpl_2 | (~ exit_FRAME_for_lpi_1);
+  assign or_9_cse = or_dcpl_2 | (~ exit_FRAME_for_lpi_1) | (FRAME_for_1_acc_itm[1]);
+  assign nl_FRAME_for_acc_itm = i_6_sva_1 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      FRAME_acc_41_itm_1_sg2 <= 2'b0;
+      FRAME_acc_41_itm_1_sg1 <= 2'b0;
+      FRAME_acc_41_itm_3 <= 6'b0;
+      FRAME_mul_1_itm_1 <= 9'b0;
+      red_slc_red_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_37_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_3_4_itm_1 <= 1'b0;
+      FRAME_mul_4_itm_1 <= 11'b0;
+      FRAME_mul_5_itm_1 <= 9'b0;
+      blue_slc_blue_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_30_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_7_4_itm_1 <= 1'b0;
+      blue_slc_blue_2_sg1_12_itm_1 <= 1'b0;
+      FRAME_mul_2_itm_1 <= 11'b0;
+      FRAME_mul_3_itm_1 <= 9'b0;
+      green_slc_green_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_18_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_5_4_itm_1 <= 1'b0;
+      green_slc_green_2_sg1_12_itm_1 <= 1'b0;
+      exit_FRAME_for_1_sva_2_st_1 <= 1'b0;
+      exit_FRAME_for_lpi_1_dfm_st_1 <= 1'b0;
+      i_7_lpi_1 <= 2'b0;
+      exit_FRAME_for_lpi_1 <= 1'b0;
+      exit_FRAME_for_1_lpi_1_dfm_4 <= 1'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_2_lpi_1_dfm <= 90'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_2 <= 1'b0;
+      b_1_sg1_lpi_1 <= 15'b0;
+      g_1_sg1_lpi_1 <= 15'b0;
+      r_1_sg1_lpi_1 <= 15'b0;
+      i_6_lpi_1 <= 2'b0;
+      b_2_lpi_1 <= 16'b0;
+      b_0_lpi_1 <= 16'b0;
+      g_2_lpi_1 <= 16'b0;
+      g_0_lpi_1 <= 16'b0;
+      r_2_lpi_1 <= 16'b0;
+      r_0_lpi_1 <= 16'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({({((({FRAME_acc_41_itm_1_sg2 ,
+            FRAME_acc_41_itm_1_sg1 , FRAME_acc_41_itm_3}) + (conv_u2s_9_10(FRAME_mul_1_itm_1)
+            + conv_s2s_8_10(conv_u2s_6_8(red_slc_red_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_37_itm_1
+            + ({4'b1001 , FRAME_slc_acc_imod_3_4_itm_1}))))) | ({8'b0 , (FRAME_acc_3_psp_sva[11:10])}))
+            , (FRAME_acc_3_psp_sva[9:6]) , ((FRAME_acc_3_psp_sva[5:0]) | ({4'b0 ,
+            (FRAME_acc_4_psp_sva[11:10])})) , (FRAME_acc_4_psp_sva[9:0])}) , vout_rsc_mgc_out_stdreg_d},
+            ~(exit_FRAME_for_1_sva_2_st_1 & exit_FRAME_for_lpi_1_dfm_st_1 & main_stage_0_2));
+        FRAME_acc_41_itm_1_sg2 <= nl_FRAME_acc_41_itm_1_sg2[1:0];
+        FRAME_acc_41_itm_1_sg1 <= FRAME_mul_sdt[7:6];
+        FRAME_acc_41_itm_3 <= nl_FRAME_acc_41_itm_3[5:0];
+        FRAME_mul_1_itm_1 <= nl_FRAME_mul_1_itm_1[8:0];
+        red_slc_red_2_sg1_itm_1 <= ACC2_3_acc_1_itm[9:4];
+        FRAME_acc_37_itm_1 <= nl_FRAME_acc_37_itm_1[4:0];
+        FRAME_slc_acc_imod_3_4_itm_1 <= acc_imod_3_sva[5];
+        FRAME_mul_4_itm_1 <= nl_FRAME_mul_4_itm_1[10:0];
+        FRAME_mul_5_itm_1 <= nl_FRAME_mul_5_itm_1[8:0];
+        blue_slc_blue_2_sg1_itm_1 <= ACC2_3_acc_3_itm[9:4];
+        FRAME_acc_30_itm_1 <= nl_FRAME_acc_30_itm_1[4:0];
+        FRAME_slc_acc_imod_7_4_itm_1 <= acc_imod_7_sva[5];
+        blue_slc_blue_2_sg1_12_itm_1 <= ACC2_3_acc_3_itm[15];
+        FRAME_mul_2_itm_1 <= nl_FRAME_mul_2_itm_1[10:0];
+        FRAME_mul_3_itm_1 <= nl_FRAME_mul_3_itm_1[8:0];
+        green_slc_green_2_sg1_itm_1 <= ACC2_3_acc_2_itm[9:4];
+        FRAME_acc_18_itm_1 <= nl_FRAME_acc_18_itm_1[4:0];
+        FRAME_slc_acc_imod_5_4_itm_1 <= acc_imod_5_sva[5];
+        green_slc_green_2_sg1_12_itm_1 <= ACC2_3_acc_2_itm[15];
+        exit_FRAME_for_1_sva_2_st_1 <= ~ (FRAME_for_1_acc_itm[1]);
+        exit_FRAME_for_lpi_1_dfm_st_1 <= exit_FRAME_for_lpi_1_dfm;
+        i_7_lpi_1 <= MUX_v_2_2_2({i_7_sva , (i_7_lpi_1 & (signext_2_1(FRAME_for_acc_itm[1])))},
+            or_4_cse);
+        exit_FRAME_for_lpi_1 <= MUX_s_1_2_2({exit_FRAME_for_lpi_1_dfm , (~ (FRAME_for_acc_itm[1]))},
+            or_4_cse);
+        exit_FRAME_for_1_lpi_1_dfm_4 <= exit_FRAME_for_1_lpi_1_dfm_4_mx0;
+        exit_FRAME_1_sva <= exit_FRAME_for_1_lpi_1_dfm_4_mx0 & exit_FRAME_lpi_1_dfm_2_mx0;
+        main_stage_0_2 <= 1'b1;
+        regs_regs_2_lpi_1_dfm <= regs_regs_2_lpi_1_dfm_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_2 <= exit_FRAME_lpi_1_dfm_2_mx0;
+        b_1_sg1_lpi_1 <= MUX_v_15_2_2({b_1_sg1_lpi_1_dfm , (b_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[39:30])
+            , (regs_regs_1_sva_dfm_mx0[39:30]) , (regs_regs_2_lpi_1_dfm_mx0[39:30])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_or_5_itm}))))},
+            or_4_cse);
+        g_1_sg1_lpi_1 <= MUX_v_15_2_2({g_1_sg1_lpi_1_dfm , (g_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[49:40])
+            , (regs_regs_1_sva_dfm_mx0[49:40]) , (regs_regs_2_lpi_1_dfm_mx0[49:40])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_or_5_itm}))))},
+            or_4_cse);
+        r_1_sg1_lpi_1 <= MUX_v_15_2_2({r_1_sg1_lpi_1_dfm , (r_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[59:50])
+            , (regs_regs_1_sva_dfm_mx0[59:50]) , (regs_regs_2_lpi_1_dfm_mx0[59:50])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_or_5_itm}))))},
+            or_4_cse);
+        i_6_lpi_1 <= MUX_v_2_2_2({i_6_lpi_1_dfm , i_6_sva_1}, or_4_cse);
+        b_2_lpi_1 <= MUX_v_16_2_2({b_2_sva_1 , (b_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+            , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_mx0[69:60])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))},
+            or_4_cse);
+        b_0_lpi_1 <= MUX_v_16_2_2({b_0_sva_1 , (b_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0])
+            , (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_mx0[9:0]) ,
+            10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_itm}))))},
+            or_4_cse);
+        g_2_lpi_1 <= MUX_v_16_2_2({g_2_sva_1 , (g_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+            , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_mx0[79:70])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))},
+            or_4_cse);
+        g_0_lpi_1 <= MUX_v_16_2_2({g_0_sva_1 , (g_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+            , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_mx0[19:10])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_itm}))))},
+            or_4_cse);
+        r_2_lpi_1 <= MUX_v_16_2_2({r_2_sva_1 , (r_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+            , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_mx0[89:80])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))},
+            or_4_cse);
+        r_0_lpi_1 <= MUX_v_16_2_2({r_0_sva_1 , (r_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+            , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_mx0[29:20])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_itm}))))},
+            or_4_cse);
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_lpi_1_dfm , FRAME_p_1_sva_1},
+            and_dcpl_1 & exit_FRAME_for_lpi_1 & (~ (FRAME_for_1_acc_itm[1])));
+      end
+    end
+  end
+  assign nl_FRAME_acc_41_itm_1_sg2  = (FRAME_mul_sdt[9:8]) + conv_s2u_1_2(ACC2_3_acc_1_itm[15]);
+  assign nl_FRAME_acc_41_itm_3  = conv_u2u_5_6(FRAME_mul_sdt[4:0]) + conv_u2u_5_6(signext_5_3({(ACC2_3_acc_1_itm[15])
+      , 1'b0 , (ACC2_3_acc_1_itm[15])}));
+  assign nl_FRAME_mul_1_itm_1  = conv_u2u_3_9(ACC2_3_acc_1_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_37_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_3_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_3_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_3_sva[5:3])) , (~ (acc_imod_3_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_3_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC2_3_acc_1_itm[9:7]));
+  assign nl_FRAME_mul_4_itm_1  = conv_u2u_2_11(ACC2_3_acc_3_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_5_itm_1  = conv_u2u_3_9(ACC2_3_acc_3_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_30_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_7_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_7_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_7_sva[5:3])) , (~ (acc_imod_7_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_7_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC2_3_acc_3_itm[9:7]));
+  assign nl_FRAME_mul_2_itm_1  = conv_u2u_2_11(ACC2_3_acc_2_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_3_itm_1  = conv_u2u_3_9(ACC2_3_acc_2_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_18_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_5_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_5_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_5_sva[5:3])) , (~ (acc_imod_5_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_5_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC2_3_acc_2_itm[9:7]));
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] MUX_v_2_2_2;
+    input [3:0] inputs;
+    input [0:0] sel;
+    reg [1:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[3:2];
+      end
+      1'b1 : begin
+        result = inputs[1:0];
+      end
+      default : begin
+        result = inputs[3:2];
+      end
+    endcase
+    MUX_v_2_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [14:0] MUX_v_15_2_2;
+    input [29:0] inputs;
+    input [0:0] sel;
+    reg [14:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[29:15];
+      end
+      1'b1 : begin
+        result = inputs[14:0];
+      end
+      default : begin
+        result = inputs[29:15];
+      end
+    endcase
+    MUX_v_15_2_2 = result;
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_11_15 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_15 = {{4{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_s2u_1_2 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_2 = {vector[0], vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v9/cycle.rpt b/Sobel/sobel.v9/cycle.rpt
new file mode 100644
index 0000000..892aa71
--- /dev/null
+++ b/Sobel/sobel.v9/cycle.rpt
@@ -0,0 +1,85 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 15:38:08 +0000 2016                      
+
+Solution Settings: sobel.v9
+  Current state: schedule
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       220 1843201    1843200            0  1          
+    Design Total:                     220 1843201    1843200            0  0          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /sobel/core              
+    
+  I/O Data Ranges
+    Port       Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ---------- ---- -------- --------- --------- ------- -------- --------
+    vin:rsc.z  IN   Unsigned        90                                     
+    clk        IN   Unsigned         1                                     
+    en         IN   Unsigned         1                                     
+    arst_n     IN   Unsigned         1                                     
+    vout:rsc.z OUT  Unsigned        30                                     
+    
+  Memory Resources
+    Resource Name: /sobel/vin:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 90
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable   Indices Phys Memory Address     
+      ---------- ------- -----------------------
+      /sobel/vin    0:89 00000000-00000000 (0-0) 
+      
+    Resource Name: /sobel/vout:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 30
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable    Indices Phys Memory Address     
+      ----------- ------- -----------------------
+      /sobel/vout    0:29 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process     Loop             Iterations C-Steps Total Cycles  Duration  Unroll Init Comments 
+    ----------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
+    /sobel/core core:rlp           Infinite       0      1843202  36.86 ms                       
+    /sobel/core   main             Infinite       3      1843202  36.86 ms            1          
+    
+  Loop Execution Profile
+    Process     Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------- ---------------- ------------ -------------------------- ----------------- --------
+    /sobel/core core:rlp                   0                        0.00          1843200           
+    /sobel/core   main               1843202                      100.00          1843200           
+    
+  End of Report
diff --git a/Sobel/sobel.v9/cycle.v b/Sobel/sobel.v9/cycle.v
new file mode 100644
index 0000000..3644c18
--- /dev/null
+++ b/Sobel/sobel.v9/cycle.v
@@ -0,0 +1,1129 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 15:38:09 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg [18:0] FRAME_p_1_lpi_1;
+    reg [14:0] b_1_sg1_lpi_1;
+    reg [15:0] b_0_lpi_1;
+    reg [15:0] b_2_lpi_1;
+    reg [14:0] g_1_sg1_lpi_1;
+    reg [15:0] g_0_lpi_1;
+    reg [15:0] g_2_lpi_1;
+    reg [14:0] r_1_sg1_lpi_1;
+    reg [15:0] r_0_lpi_1;
+    reg [15:0] r_2_lpi_1;
+    reg [1:0] i_6_lpi_1;
+    reg exit_FRAME_for_lpi_1;
+    reg [1:0] i_7_lpi_1;
+    reg [89:0] regs_regs_1_sva;
+    reg [89:0] regs_regs_0_sva;
+    reg exit_FRAME_1_sva;
+    reg [18:0] FRAME_p_1_lpi_1_dfm;
+    reg exit_FRAME_for_1_lpi_1_dfm;
+    reg [89:0] regs_regs_0_sva_dfm;
+    reg [89:0] regs_regs_1_sva_dfm;
+    reg [89:0] regs_regs_2_lpi_1_dfm;
+    reg [15:0] r_0_lpi_1_dfm;
+    reg [15:0] r_2_lpi_1_dfm;
+    reg [15:0] g_0_lpi_1_dfm;
+    reg [15:0] g_2_lpi_1_dfm;
+    reg [15:0] b_0_lpi_1_dfm;
+    reg [15:0] b_2_lpi_1_dfm;
+    reg [1:0] i_6_lpi_1_dfm;
+    reg [14:0] r_1_sg1_lpi_1_dfm;
+    reg [14:0] g_1_sg1_lpi_1_dfm;
+    reg [14:0] b_1_sg1_lpi_1_dfm;
+    reg exit_FRAME_lpi_1_dfm;
+    reg exit_FRAME_for_lpi_1_dfm;
+    reg FRAME_for_1_slc_YMATRIX_rom_11_psp_sva;
+    reg [15:0] r_0_sva_1;
+    reg [15:0] g_0_sva_1;
+    reg [15:0] b_0_sva_1;
+    reg [15:0] r_2_sva_1;
+    reg [15:0] g_2_sva_1;
+    reg [15:0] b_2_sva_1;
+    reg [1:0] i_7_sva;
+    reg exit_FRAME_for_1_sva_2;
+    reg [14:0] red_2_sg1_sva;
+    reg [14:0] green_2_sg1_sva;
+    reg [14:0] blue_2_sg1_sva;
+    reg [5:0] acc_imod_3_sva;
+    reg [5:0] acc_imod_5_sva;
+    reg [11:0] FRAME_acc_3_psp_sva;
+    reg [5:0] acc_imod_7_sva;
+    reg [11:0] FRAME_acc_4_psp_sva;
+    reg [18:0] FRAME_p_1_sva_1;
+    reg [15:0] r_0_sva_2;
+    reg [15:0] g_0_sva_2;
+    reg [15:0] b_0_sva_2;
+    reg [14:0] r_1_sg1_sva_1;
+    reg [14:0] g_1_sg1_sva_1;
+    reg [14:0] b_1_sg1_sva_1;
+    reg [15:0] r_2_sva_2;
+    reg [15:0] g_2_sva_2;
+    reg [15:0] b_2_sva_2;
+    reg [1:0] i_6_sva_1;
+    reg exit_FRAME_for_sva_1;
+    reg [1:0] i_7_lpi_1_dfm;
+    reg exit_FRAME_lpi_1_dfm_2;
+    reg exit_FRAME_for_1_lpi_1_dfm_2;
+    reg exit_FRAME_for_1_lpi_1_dfm_4;
+    reg [1:0] FRAME_for_acc_5_tmp;
+    reg exit_FRAME_for_1_sva_2_st;
+    reg [10:0] FRAME_mul_2_itm;
+    reg [10:0] FRAME_mul_2_itm_1;
+    reg [8:0] FRAME_mul_3_itm;
+    reg [8:0] FRAME_mul_3_itm_1;
+    reg [5:0] green_slc_green_2_sg1_itm;
+    reg [5:0] green_slc_green_2_sg1_itm_1;
+    reg [4:0] FRAME_acc_18_itm;
+    reg [4:0] FRAME_acc_18_itm_1;
+    reg FRAME_slc_acc_imod_5_4_itm;
+    reg FRAME_slc_acc_imod_5_4_itm_1;
+    reg green_slc_green_2_sg1_12_itm;
+    reg green_slc_green_2_sg1_12_itm_1;
+    reg green_slc_green_2_sg1_13_itm;
+    reg green_slc_green_2_sg1_13_itm_1;
+    reg green_slc_green_2_sg1_8_itm;
+    reg green_slc_green_2_sg1_8_itm_1;
+    reg [10:0] FRAME_mul_4_itm;
+    reg [10:0] FRAME_mul_4_itm_1;
+    reg [8:0] FRAME_mul_5_itm;
+    reg [8:0] FRAME_mul_5_itm_1;
+    reg [5:0] blue_slc_blue_2_sg1_itm;
+    reg [5:0] blue_slc_blue_2_sg1_itm_1;
+    reg [4:0] FRAME_acc_30_itm;
+    reg [4:0] FRAME_acc_30_itm_1;
+    reg FRAME_slc_acc_imod_7_4_itm;
+    reg FRAME_slc_acc_imod_7_4_itm_1;
+    reg blue_slc_blue_2_sg1_12_itm;
+    reg blue_slc_blue_2_sg1_12_itm_1;
+    reg blue_slc_blue_2_sg1_13_itm;
+    reg blue_slc_blue_2_sg1_13_itm_1;
+    reg blue_slc_blue_2_sg1_8_itm;
+    reg blue_slc_blue_2_sg1_8_itm_1;
+    reg [8:0] FRAME_mul_1_itm;
+    reg [8:0] FRAME_mul_1_itm_1;
+    reg [5:0] red_slc_red_2_sg1_itm;
+    reg [5:0] red_slc_red_2_sg1_itm_1;
+    reg [4:0] FRAME_acc_37_itm;
+    reg [4:0] FRAME_acc_37_itm_1;
+    reg FRAME_slc_acc_imod_3_4_itm;
+    reg FRAME_slc_acc_imod_3_4_itm_1;
+    reg exit_FRAME_for_lpi_1_dfm_st_1;
+    reg exit_FRAME_for_1_sva_2_st_1;
+    reg main_stage_0_2;
+    reg [9:0] FRAME_mul_sdt;
+    reg FRAME_for_1_nor_cse;
+    reg FRAME_for_nor_cse;
+    reg FRAME_for_1_slc_XMATRIX_rom_11_psp_sva_1;
+    reg FRAME_for_slc_XMATRIX_rom_11_psp_sva_1;
+    reg FRAME_for_and_18_seb;
+    reg FRAME_for_slc_XMATRIX_rom_11_1_psp_sva_1;
+    reg FRAME_for_slc_XMATRIX_rom_11_2_psp_sva_1;
+    reg [1:0] FRAME_acc_41_itm_sg2;
+    reg [1:0] FRAME_acc_41_itm_sg1;
+    reg [5:0] FRAME_acc_41_itm_2;
+    reg [1:0] FRAME_acc_41_itm_1_sg2;
+    reg [1:0] FRAME_acc_41_itm_1_sg1;
+    reg [5:0] FRAME_acc_41_itm_3;
+
+    reg[9:0] regs_operator_15_mux_nl;
+    reg[9:0] regs_operator_16_mux_nl;
+    reg[9:0] regs_operator_17_mux_nl;
+    reg[9:0] regs_operator_21_mux_nl;
+    reg[9:0] regs_operator_22_mux_nl;
+    reg[9:0] regs_operator_23_mux_nl;
+    reg[9:0] regs_operator_6_mux_nl;
+    reg[9:0] regs_operator_7_mux_nl;
+    reg[9:0] regs_operator_8_mux_nl;
+    reg[9:0] regs_operator_9_mux_nl;
+    reg[9:0] regs_operator_10_mux_nl;
+    reg[9:0] regs_operator_11_mux_nl;
+    reg[9:0] regs_operator_12_mux_nl;
+    reg[9:0] regs_operator_13_mux_nl;
+    reg[9:0] regs_operator_14_mux_nl;
+    begin : core_rlpExit
+      forever begin : core_rlp
+        // C-Step 0 of Loop 'core_rlp'
+        i_7_lpi_1 = 2'b0;
+        exit_FRAME_for_lpi_1 = 1'b0;
+        i_6_lpi_1 = 2'b0;
+        r_2_lpi_1 = 16'b0;
+        r_0_lpi_1 = 16'b0;
+        r_1_sg1_lpi_1 = 15'b0;
+        g_2_lpi_1 = 16'b0;
+        g_0_lpi_1 = 16'b0;
+        g_1_sg1_lpi_1 = 15'b0;
+        b_2_lpi_1 = 16'b0;
+        b_0_lpi_1 = 16'b0;
+        b_1_sg1_lpi_1 = 15'b0;
+        FRAME_p_1_lpi_1 = 19'b0;
+        regs_regs_1_sva = 90'b0;
+        regs_regs_0_sva = 90'b0;
+        exit_FRAME_1_sva = 1'b1;
+        main_stage_0_2 = 1'b0;
+        begin : mainExit
+          forever begin : main
+            // C-Step 0 of Loop 'main'
+            begin : waitLoop0Exit
+              forever begin : waitLoop0
+                @(posedge clk or negedge ( arst_n ));
+                if ( ~ arst_n )
+                  disable core_rlpExit;
+                if ( en )
+                  disable waitLoop0Exit;
+              end
+            end
+            // C-Step 1 of Loop 'main'
+            if ( main_stage_0_2 ) begin
+              if ( exit_FRAME_for_lpi_1_dfm_st_1 ) begin
+                if ( exit_FRAME_for_1_sva_2_st_1 ) begin
+                  FRAME_acc_3_psp_sva = (conv_u2s_11_12(FRAME_mul_2_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_3_itm_1)
+                      + conv_s2s_8_10(conv_u2s_6_8(green_slc_green_2_sg1_itm_1) +
+                      conv_s2s_5_8(FRAME_acc_18_itm_1 + ({4'b1001 , FRAME_slc_acc_imod_5_4_itm_1})))))
+                      + conv_u2u_11_12(signext_11_9({green_slc_green_2_sg1_12_itm_1
+                      , 3'b0 , ({{2{green_slc_green_2_sg1_13_itm_1}}, green_slc_green_2_sg1_13_itm_1})
+                      , 1'b0 , green_slc_green_2_sg1_8_itm_1}));
+                  FRAME_acc_4_psp_sva = (conv_u2s_11_12(FRAME_mul_4_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_5_itm_1)
+                      + conv_s2s_8_10(conv_u2s_6_8(blue_slc_blue_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_30_itm_1
+                      + ({4'b1001 , FRAME_slc_acc_imod_7_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({blue_slc_blue_2_sg1_12_itm_1
+                      , 3'b0 , ({{2{blue_slc_blue_2_sg1_13_itm_1}}, blue_slc_blue_2_sg1_13_itm_1})
+                      , 1'b0 , blue_slc_blue_2_sg1_8_itm_1}));
+                  vout_rsc_mgc_out_stdreg_d <= {((({FRAME_acc_41_itm_1_sg2 , FRAME_acc_41_itm_1_sg1
+                      , FRAME_acc_41_itm_3}) + (conv_u2s_9_10(FRAME_mul_1_itm_1)
+                      + conv_s2s_8_10(conv_u2s_6_8(red_slc_red_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_37_itm_1
+                      + ({4'b1001 , FRAME_slc_acc_imod_3_4_itm_1}))))) | ({8'b0,
+                      FRAME_acc_3_psp_sva[11:10]})) , (FRAME_acc_3_psp_sva[9:6])
+                      , ((FRAME_acc_3_psp_sva[5:0]) | ({4'b0, FRAME_acc_4_psp_sva[11:10]}))
+                      , (FRAME_acc_4_psp_sva[9:0])};
+                end
+              end
+            end
+            i_7_lpi_1_dfm = 2'b0;
+            exit_FRAME_for_sva_1 = 1'b0;
+            i_6_sva_1 = 2'b0;
+            b_2_sva_2 = 16'b0;
+            g_2_sva_2 = 16'b0;
+            r_2_sva_2 = 16'b0;
+            b_1_sg1_sva_1 = 15'b0;
+            g_1_sg1_sva_1 = 15'b0;
+            r_1_sg1_sva_1 = 15'b0;
+            b_0_sva_2 = 16'b0;
+            g_0_sva_2 = 16'b0;
+            r_0_sva_2 = 16'b0;
+            FRAME_p_1_sva_1 = 19'b0;
+            exit_FRAME_for_1_sva_2 = 1'b0;
+            i_7_sva = 2'b0;
+            b_2_sva_1 = 16'b0;
+            g_2_sva_1 = 16'b0;
+            r_2_sva_1 = 16'b0;
+            b_0_sva_1 = 16'b0;
+            g_0_sva_1 = 16'b0;
+            r_0_sva_1 = 16'b0;
+            FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+            exit_FRAME_for_1_lpi_1_dfm = exit_FRAME_for_1_lpi_1_dfm_4 | exit_FRAME_1_sva;
+            if ( exit_FRAME_for_1_lpi_1_dfm ) begin
+              regs_regs_0_sva_dfm = vin_rsc_mgc_in_wire_d;
+              regs_regs_1_sva_dfm = regs_regs_0_sva;
+              regs_regs_2_lpi_1_dfm = regs_regs_1_sva;
+            end
+            else begin
+              regs_regs_0_sva_dfm = regs_regs_0_sva;
+              regs_regs_1_sva_dfm = regs_regs_1_sva;
+            end
+            r_0_lpi_1_dfm = r_0_lpi_1 & (signext_16_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            r_2_lpi_1_dfm = r_2_lpi_1 & (signext_16_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            g_0_lpi_1_dfm = g_0_lpi_1 & (signext_16_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            g_2_lpi_1_dfm = g_2_lpi_1 & (signext_16_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            b_0_lpi_1_dfm = b_0_lpi_1 & (signext_16_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            b_2_lpi_1_dfm = b_2_lpi_1 & (signext_16_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            i_6_lpi_1_dfm = i_6_lpi_1 & (signext_2_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            r_1_sg1_lpi_1_dfm = r_1_sg1_lpi_1 & (signext_15_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            g_1_sg1_lpi_1_dfm = g_1_sg1_lpi_1 & (signext_15_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            b_1_sg1_lpi_1_dfm = b_1_sg1_lpi_1 & (signext_15_1(~ exit_FRAME_for_1_lpi_1_dfm));
+            exit_FRAME_lpi_1_dfm = exit_FRAME_lpi_1_dfm_2 & (~ exit_FRAME_for_1_lpi_1_dfm);
+            exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_lpi_1 & (~ exit_FRAME_for_1_lpi_1_dfm);
+            if ( exit_FRAME_for_lpi_1_dfm ) begin
+              FRAME_for_1_nor_cse = ~((i_7_lpi_1[1]) | (i_7_lpi_1[0]));
+              FRAME_for_1_slc_YMATRIX_rom_11_psp_sva = (~((i_7_lpi_1[0]) & (~ (i_7_lpi_1[1]))))
+                  | FRAME_for_1_nor_cse | ((i_7_lpi_1[1]) & (~ (i_7_lpi_1[0])));
+              regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[29:20])
+                  , (regs_regs_1_sva_dfm[29:20]) , (regs_regs_2_lpi_1_dfm[29:20])
+                  , 10'b0}, i_7_lpi_1);
+              r_0_sva_1 = r_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_15_mux_nl)
+                  * conv_s2s_2_12({1'b1 , FRAME_for_1_slc_YMATRIX_rom_11_psp_sva})));
+              regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[19:10])
+                  , (regs_regs_1_sva_dfm[19:10]) , (regs_regs_2_lpi_1_dfm[19:10])
+                  , 10'b0}, i_7_lpi_1);
+              g_0_sva_1 = g_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_16_mux_nl)
+                  * conv_s2s_2_12({1'b1 , FRAME_for_1_slc_YMATRIX_rom_11_psp_sva})));
+              regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[9:0])
+                  , (regs_regs_1_sva_dfm[9:0]) , (regs_regs_2_lpi_1_dfm[9:0]) , 10'b0},
+                  i_7_lpi_1);
+              b_0_sva_1 = b_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_17_mux_nl)
+                  * conv_s2s_2_12({1'b1 , FRAME_for_1_slc_YMATRIX_rom_11_psp_sva})));
+              FRAME_for_1_slc_XMATRIX_rom_11_psp_sva_1 = (~((~ (i_7_lpi_1[1])) &
+                  (i_7_lpi_1[0]))) | FRAME_for_1_nor_cse;
+              regs_operator_21_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[89:80])
+                  , (regs_regs_1_sva_dfm[89:80]) , (regs_regs_2_lpi_1_dfm[89:80])
+                  , 10'b0}, i_7_lpi_1);
+              r_2_sva_1 = r_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_21_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_slc_XMATRIX_rom_11_psp_sva_1})));
+              regs_operator_22_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[79:70])
+                  , (regs_regs_1_sva_dfm[79:70]) , (regs_regs_2_lpi_1_dfm[79:70])
+                  , 10'b0}, i_7_lpi_1);
+              g_2_sva_1 = g_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_22_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_slc_XMATRIX_rom_11_psp_sva_1})));
+              regs_operator_23_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[69:60])
+                  , (regs_regs_1_sva_dfm[69:60]) , (regs_regs_2_lpi_1_dfm[69:60])
+                  , 10'b0}, i_7_lpi_1);
+              b_2_sva_1 = b_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_23_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_slc_XMATRIX_rom_11_psp_sva_1})));
+              i_7_sva = i_7_lpi_1 + 2'b1;
+              exit_FRAME_for_1_sva_2 = ~ (readslicef_3_1_2((({1'b1 , i_7_sva}) +
+                  3'b1)));
+              exit_FRAME_for_1_sva_2_st = exit_FRAME_for_1_sva_2;
+              if ( exit_FRAME_for_1_sva_2 ) begin
+                red_2_sg1_sva = readslicef_16_15_1((({(r_1_sg1_lpi_1_dfm + (r_2_sva_1[15:1]))
+                    , (r_2_sva_1[0])}) + r_0_sva_1));
+                green_2_sg1_sva = readslicef_16_15_1((({(g_1_sg1_lpi_1_dfm + (g_2_sva_1[15:1]))
+                    , (g_2_sva_1[0])}) + g_0_sva_1));
+                blue_2_sg1_sva = readslicef_16_15_1((({(b_1_sg1_lpi_1_dfm + (b_2_sva_1[15:1]))
+                    , (b_2_sva_1[0])}) + b_0_sva_1));
+                acc_imod_3_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(red_2_sg1_sva[8:6])
+                    + conv_u2u_3_4(~ (red_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                    (red_2_sg1_sva[14])) , 1'b1 , (~ (red_2_sg1_sva[14]))}) + conv_u2u_2_4(red_2_sg1_sva[13:12])))
+                    + conv_u2u_4_6(conv_u2u_3_4(red_2_sg1_sva[2:0]) + conv_u2u_3_4(~
+                    (red_2_sg1_sva[5:3])))) + 6'b101011;
+                acc_imod_5_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(green_2_sg1_sva[8:6])
+                    + conv_u2u_3_4(~ (green_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                    (green_2_sg1_sva[14])) , 1'b1 , (~ (green_2_sg1_sva[14]))}) +
+                    conv_u2u_2_4(green_2_sg1_sva[13:12]))) + conv_u2u_4_6(conv_u2u_3_4(green_2_sg1_sva[2:0])
+                    + conv_u2u_3_4(~ (green_2_sg1_sva[5:3])))) + 6'b101011;
+                FRAME_mul_2_itm = conv_u2u_22_11(conv_u2u_2_11(green_2_sg1_sva[13:12])
+                    * 11'b111000111);
+                FRAME_mul_3_itm = conv_u2u_18_9(conv_u2u_3_9(green_2_sg1_sva[11:9])
+                    * 9'b111001);
+                green_slc_green_2_sg1_itm = green_2_sg1_sva[8:3];
+                FRAME_acc_18_itm = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_5_sva[5]))
+                    , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_5_sva[2:0])
+                    , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_5_sva[5:3])) , (~ (acc_imod_5_sva[5]))})))))})
+                    + conv_u2u_2_4(acc_imod_5_sva[4:3])) + conv_u2u_3_5(~ (green_2_sg1_sva[8:6]));
+                FRAME_slc_acc_imod_5_4_itm = acc_imod_5_sva[5];
+                green_slc_green_2_sg1_12_itm = green_2_sg1_sva[14];
+                green_slc_green_2_sg1_13_itm = green_2_sg1_sva[14];
+                green_slc_green_2_sg1_8_itm = green_2_sg1_sva[14];
+                acc_imod_7_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(blue_2_sg1_sva[8:6])
+                    + conv_u2u_3_4(~ (blue_2_sg1_sva[11:9]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+                    (blue_2_sg1_sva[14])) , 1'b1 , (~ (blue_2_sg1_sva[14]))}) + conv_u2u_2_4(blue_2_sg1_sva[13:12])))
+                    + conv_u2u_4_6(conv_u2u_3_4(blue_2_sg1_sva[2:0]) + conv_u2u_3_4(~
+                    (blue_2_sg1_sva[5:3])))) + 6'b101011;
+                FRAME_mul_4_itm = conv_u2u_22_11(conv_u2u_2_11(blue_2_sg1_sva[13:12])
+                    * 11'b111000111);
+                FRAME_mul_5_itm = conv_u2u_18_9(conv_u2u_3_9(blue_2_sg1_sva[11:9])
+                    * 9'b111001);
+                blue_slc_blue_2_sg1_itm = blue_2_sg1_sva[8:3];
+                FRAME_acc_30_itm = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_7_sva[5]))
+                    , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_7_sva[2:0])
+                    , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_7_sva[5:3])) , (~ (acc_imod_7_sva[5]))})))))})
+                    + conv_u2u_2_4(acc_imod_7_sva[4:3])) + conv_u2u_3_5(~ (blue_2_sg1_sva[8:6]));
+                FRAME_slc_acc_imod_7_4_itm = acc_imod_7_sva[5];
+                blue_slc_blue_2_sg1_12_itm = blue_2_sg1_sva[14];
+                blue_slc_blue_2_sg1_13_itm = blue_2_sg1_sva[14];
+                blue_slc_blue_2_sg1_8_itm = blue_2_sg1_sva[14];
+                FRAME_mul_sdt = conv_u2u_20_10(conv_u2u_2_10(red_2_sg1_sva[13:12])
+                    * 10'b111000111);
+                FRAME_acc_41_itm_sg1 = FRAME_mul_sdt[7:6];
+                FRAME_acc_41_itm_2 = conv_u2u_5_6(FRAME_mul_sdt[4:0]) + conv_u2u_5_6(signext_5_3({(red_2_sg1_sva[14])
+                    , 1'b0 , (red_2_sg1_sva[14])}));
+                FRAME_acc_41_itm_sg2 = (FRAME_mul_sdt[9:8]) + conv_s2u_1_2(red_2_sg1_sva[14]);
+                FRAME_mul_1_itm = conv_u2u_18_9(conv_u2u_3_9(red_2_sg1_sva[11:9])
+                    * 9'b111001);
+                red_slc_red_2_sg1_itm = red_2_sg1_sva[8:3];
+                FRAME_acc_37_itm = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_3_sva[5]))
+                    , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_3_sva[2:0])
+                    , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_3_sva[5:3])) , (~ (acc_imod_3_sva[5]))})))))})
+                    + conv_u2u_2_4(acc_imod_3_sva[4:3])) + conv_u2u_3_5(~ (red_2_sg1_sva[8:6]));
+                FRAME_slc_acc_imod_3_4_itm = acc_imod_3_sva[5];
+                FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+                exit_FRAME_lpi_1_dfm_2 = ~ (readslicef_8_1_7((conv_u2s_7_8(FRAME_p_1_sva_1[18:12])
+                    + 8'b10110101)));
+              end
+              else begin
+                exit_FRAME_lpi_1_dfm_2 = exit_FRAME_lpi_1_dfm;
+              end
+            end
+            else begin
+              FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+              FRAME_for_slc_XMATRIX_rom_11_psp_sva_1 = (~((i_6_lpi_1_dfm[0]) & (~
+                  (i_6_lpi_1_dfm[1])))) | FRAME_for_nor_cse;
+              regs_operator_6_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[29:20])
+                  , (regs_regs_1_sva_dfm[29:20]) , (regs_regs_2_lpi_1_dfm[29:20])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              r_0_sva_2 = r_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_6_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+              regs_operator_7_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[19:10])
+                  , (regs_regs_1_sva_dfm[19:10]) , (regs_regs_2_lpi_1_dfm[19:10])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              g_0_sva_2 = g_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_7_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+              regs_operator_8_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[9:0]) ,
+                  (regs_regs_1_sva_dfm[9:0]) , (regs_regs_2_lpi_1_dfm[9:0]) , 10'b0},
+                  i_6_lpi_1_dfm);
+              b_0_sva_2 = b_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_8_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_psp_sva_1})));
+              FRAME_for_acc_5_tmp = i_6_lpi_1_dfm + 2'b11;
+              FRAME_for_and_18_seb = (FRAME_for_acc_5_tmp[1]) & (FRAME_for_acc_5_tmp[0]);
+              FRAME_for_slc_XMATRIX_rom_11_1_psp_sva_1 = (FRAME_for_acc_5_tmp[1])
+                  | (FRAME_for_acc_5_tmp[0]) | FRAME_for_and_18_seb;
+              regs_operator_9_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[59:50])
+                  , (regs_regs_1_sva_dfm[59:50]) , (regs_regs_2_lpi_1_dfm[59:50])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              r_1_sg1_sva_1 = r_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(regs_operator_9_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_slc_XMATRIX_rom_11_1_psp_sva_1})));
+              regs_operator_10_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[49:40])
+                  , (regs_regs_1_sva_dfm[49:40]) , (regs_regs_2_lpi_1_dfm[49:40])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              g_1_sg1_sva_1 = g_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(regs_operator_10_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_slc_XMATRIX_rom_11_1_psp_sva_1})));
+              regs_operator_11_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[39:30])
+                  , (regs_regs_1_sva_dfm[39:30]) , (regs_regs_2_lpi_1_dfm[39:30])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              b_1_sg1_sva_1 = b_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(regs_operator_11_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_slc_XMATRIX_rom_11_1_psp_sva_1})));
+              FRAME_for_slc_XMATRIX_rom_11_2_psp_sva_1 = (~((~ (i_6_lpi_1_dfm[1]))
+                  & (i_6_lpi_1_dfm[0]))) | FRAME_for_nor_cse;
+              regs_operator_12_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[89:80])
+                  , (regs_regs_1_sva_dfm[89:80]) , (regs_regs_2_lpi_1_dfm[89:80])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              r_2_sva_2 = r_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_12_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_2_psp_sva_1})));
+              regs_operator_13_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[79:70])
+                  , (regs_regs_1_sva_dfm[79:70]) , (regs_regs_2_lpi_1_dfm[79:70])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              g_2_sva_2 = g_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_13_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_2_psp_sva_1})));
+              regs_operator_14_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva_dfm[69:60])
+                  , (regs_regs_1_sva_dfm[69:60]) , (regs_regs_2_lpi_1_dfm[69:60])
+                  , 10'b0}, i_6_lpi_1_dfm);
+              b_2_sva_2 = b_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_14_mux_nl)
+                  * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_slc_XMATRIX_rom_11_2_psp_sva_1})));
+              i_6_sva_1 = i_6_lpi_1_dfm + 2'b1;
+              exit_FRAME_for_sva_1 = ~ (readslicef_3_1_2((({1'b1 , i_6_sva_1}) +
+                  3'b1)));
+              i_7_lpi_1_dfm = i_7_lpi_1 & (signext_2_1(~ exit_FRAME_for_sva_1));
+              exit_FRAME_lpi_1_dfm_2 = exit_FRAME_lpi_1_dfm;
+            end
+            exit_FRAME_for_1_lpi_1_dfm_2 = exit_FRAME_for_1_sva_2 & exit_FRAME_for_lpi_1_dfm;
+            exit_FRAME_for_1_lpi_1_dfm_4 = MUX_s_1_2_2({exit_FRAME_for_1_lpi_1_dfm_2
+                , (exit_FRAME_for_1_lpi_1_dfm_2 | (~ exit_FRAME_lpi_1_dfm_2))}, exit_FRAME_for_1_lpi_1_dfm_2);
+            regs_regs_0_sva = regs_regs_0_sva_dfm;
+            regs_regs_1_sva = regs_regs_1_sva_dfm;
+            r_0_lpi_1 = MUX_v_16_2_2({r_0_sva_2 , r_0_sva_1}, exit_FRAME_for_lpi_1_dfm);
+            r_2_lpi_1 = MUX_v_16_2_2({r_2_sva_2 , r_2_sva_1}, exit_FRAME_for_lpi_1_dfm);
+            g_0_lpi_1 = MUX_v_16_2_2({g_0_sva_2 , g_0_sva_1}, exit_FRAME_for_lpi_1_dfm);
+            g_2_lpi_1 = MUX_v_16_2_2({g_2_sva_2 , g_2_sva_1}, exit_FRAME_for_lpi_1_dfm);
+            b_0_lpi_1 = MUX_v_16_2_2({b_0_sva_2 , b_0_sva_1}, exit_FRAME_for_lpi_1_dfm);
+            b_2_lpi_1 = MUX_v_16_2_2({b_2_sva_2 , b_2_sva_1}, exit_FRAME_for_lpi_1_dfm);
+            FRAME_p_1_lpi_1 = MUX_v_19_2_2({FRAME_p_1_sva_1 , FRAME_p_1_lpi_1_dfm},
+                ~(exit_FRAME_for_1_sva_2 & exit_FRAME_for_lpi_1_dfm));
+            i_6_lpi_1 = MUX_v_2_2_2({i_6_sva_1 , i_6_lpi_1_dfm}, exit_FRAME_for_lpi_1_dfm);
+            i_7_lpi_1 = MUX_v_2_2_2({i_7_lpi_1_dfm , i_7_sva}, exit_FRAME_for_lpi_1_dfm);
+            r_1_sg1_lpi_1 = MUX_v_15_2_2({r_1_sg1_sva_1 , r_1_sg1_lpi_1_dfm}, exit_FRAME_for_lpi_1_dfm);
+            g_1_sg1_lpi_1 = MUX_v_15_2_2({g_1_sg1_sva_1 , g_1_sg1_lpi_1_dfm}, exit_FRAME_for_lpi_1_dfm);
+            b_1_sg1_lpi_1 = MUX_v_15_2_2({b_1_sg1_sva_1 , b_1_sg1_lpi_1_dfm}, exit_FRAME_for_lpi_1_dfm);
+            exit_FRAME_for_lpi_1 = MUX_s_1_2_2({exit_FRAME_for_sva_1 , exit_FRAME_for_lpi_1_dfm},
+                exit_FRAME_for_lpi_1_dfm);
+            exit_FRAME_1_sva = exit_FRAME_for_1_lpi_1_dfm_4 & exit_FRAME_lpi_1_dfm_2;
+            FRAME_mul_2_itm_1 = FRAME_mul_2_itm;
+            FRAME_mul_3_itm_1 = FRAME_mul_3_itm;
+            green_slc_green_2_sg1_itm_1 = green_slc_green_2_sg1_itm;
+            FRAME_acc_18_itm_1 = FRAME_acc_18_itm;
+            FRAME_slc_acc_imod_5_4_itm_1 = FRAME_slc_acc_imod_5_4_itm;
+            green_slc_green_2_sg1_12_itm_1 = green_slc_green_2_sg1_12_itm;
+            green_slc_green_2_sg1_13_itm_1 = green_slc_green_2_sg1_13_itm;
+            green_slc_green_2_sg1_8_itm_1 = green_slc_green_2_sg1_8_itm;
+            FRAME_mul_4_itm_1 = FRAME_mul_4_itm;
+            FRAME_mul_5_itm_1 = FRAME_mul_5_itm;
+            blue_slc_blue_2_sg1_itm_1 = blue_slc_blue_2_sg1_itm;
+            FRAME_acc_30_itm_1 = FRAME_acc_30_itm;
+            FRAME_slc_acc_imod_7_4_itm_1 = FRAME_slc_acc_imod_7_4_itm;
+            blue_slc_blue_2_sg1_12_itm_1 = blue_slc_blue_2_sg1_12_itm;
+            blue_slc_blue_2_sg1_13_itm_1 = blue_slc_blue_2_sg1_13_itm;
+            blue_slc_blue_2_sg1_8_itm_1 = blue_slc_blue_2_sg1_8_itm;
+            FRAME_acc_41_itm_1_sg1 = FRAME_acc_41_itm_sg1;
+            FRAME_acc_41_itm_3 = FRAME_acc_41_itm_2;
+            FRAME_acc_41_itm_1_sg2 = FRAME_acc_41_itm_sg2;
+            FRAME_mul_1_itm_1 = FRAME_mul_1_itm;
+            red_slc_red_2_sg1_itm_1 = red_slc_red_2_sg1_itm;
+            FRAME_acc_37_itm_1 = FRAME_acc_37_itm;
+            FRAME_slc_acc_imod_3_4_itm_1 = FRAME_slc_acc_imod_3_4_itm;
+            exit_FRAME_for_lpi_1_dfm_st_1 = exit_FRAME_for_lpi_1_dfm;
+            exit_FRAME_for_1_sva_2_st_1 = exit_FRAME_for_1_sva_2_st;
+            main_stage_0_2 = 1'b1;
+          end
+        end
+      end
+    end
+    FRAME_acc_41_itm_3 = 6'b0;
+    FRAME_acc_41_itm_1_sg1 = 2'b0;
+    FRAME_acc_41_itm_1_sg2 = 2'b0;
+    FRAME_acc_41_itm_2 = 6'b0;
+    FRAME_acc_41_itm_sg1 = 2'b0;
+    FRAME_acc_41_itm_sg2 = 2'b0;
+    FRAME_for_slc_XMATRIX_rom_11_2_psp_sva_1 = 1'b0;
+    FRAME_for_slc_XMATRIX_rom_11_1_psp_sva_1 = 1'b0;
+    FRAME_for_and_18_seb = 1'b0;
+    FRAME_for_slc_XMATRIX_rom_11_psp_sva_1 = 1'b0;
+    FRAME_for_1_slc_XMATRIX_rom_11_psp_sva_1 = 1'b0;
+    FRAME_for_nor_cse = 1'b0;
+    FRAME_for_1_nor_cse = 1'b0;
+    FRAME_mul_sdt = 10'b0;
+    main_stage_0_2 = 1'b0;
+    exit_FRAME_for_1_sva_2_st_1 = 1'b0;
+    exit_FRAME_for_lpi_1_dfm_st_1 = 1'b0;
+    FRAME_slc_acc_imod_3_4_itm_1 = 1'b0;
+    FRAME_slc_acc_imod_3_4_itm = 1'b0;
+    FRAME_acc_37_itm_1 = 5'b0;
+    FRAME_acc_37_itm = 5'b0;
+    red_slc_red_2_sg1_itm_1 = 6'b0;
+    red_slc_red_2_sg1_itm = 6'b0;
+    FRAME_mul_1_itm_1 = 9'b0;
+    FRAME_mul_1_itm = 9'b0;
+    blue_slc_blue_2_sg1_8_itm_1 = 1'b0;
+    blue_slc_blue_2_sg1_8_itm = 1'b0;
+    blue_slc_blue_2_sg1_13_itm_1 = 1'b0;
+    blue_slc_blue_2_sg1_13_itm = 1'b0;
+    blue_slc_blue_2_sg1_12_itm_1 = 1'b0;
+    blue_slc_blue_2_sg1_12_itm = 1'b0;
+    FRAME_slc_acc_imod_7_4_itm_1 = 1'b0;
+    FRAME_slc_acc_imod_7_4_itm = 1'b0;
+    FRAME_acc_30_itm_1 = 5'b0;
+    FRAME_acc_30_itm = 5'b0;
+    blue_slc_blue_2_sg1_itm_1 = 6'b0;
+    blue_slc_blue_2_sg1_itm = 6'b0;
+    FRAME_mul_5_itm_1 = 9'b0;
+    FRAME_mul_5_itm = 9'b0;
+    FRAME_mul_4_itm_1 = 11'b0;
+    FRAME_mul_4_itm = 11'b0;
+    green_slc_green_2_sg1_8_itm_1 = 1'b0;
+    green_slc_green_2_sg1_8_itm = 1'b0;
+    green_slc_green_2_sg1_13_itm_1 = 1'b0;
+    green_slc_green_2_sg1_13_itm = 1'b0;
+    green_slc_green_2_sg1_12_itm_1 = 1'b0;
+    green_slc_green_2_sg1_12_itm = 1'b0;
+    FRAME_slc_acc_imod_5_4_itm_1 = 1'b0;
+    FRAME_slc_acc_imod_5_4_itm = 1'b0;
+    FRAME_acc_18_itm_1 = 5'b0;
+    FRAME_acc_18_itm = 5'b0;
+    green_slc_green_2_sg1_itm_1 = 6'b0;
+    green_slc_green_2_sg1_itm = 6'b0;
+    FRAME_mul_3_itm_1 = 9'b0;
+    FRAME_mul_3_itm = 9'b0;
+    FRAME_mul_2_itm_1 = 11'b0;
+    FRAME_mul_2_itm = 11'b0;
+    exit_FRAME_for_1_sva_2_st = 1'b0;
+    FRAME_for_acc_5_tmp = 2'b0;
+    exit_FRAME_for_1_lpi_1_dfm_4 = 1'b0;
+    exit_FRAME_for_1_lpi_1_dfm_2 = 1'b0;
+    exit_FRAME_lpi_1_dfm_2 = 1'b0;
+    i_7_lpi_1_dfm = 2'b0;
+    exit_FRAME_for_sva_1 = 1'b0;
+    i_6_sva_1 = 2'b0;
+    b_2_sva_2 = 16'b0;
+    g_2_sva_2 = 16'b0;
+    r_2_sva_2 = 16'b0;
+    b_1_sg1_sva_1 = 15'b0;
+    g_1_sg1_sva_1 = 15'b0;
+    r_1_sg1_sva_1 = 15'b0;
+    b_0_sva_2 = 16'b0;
+    g_0_sva_2 = 16'b0;
+    r_0_sva_2 = 16'b0;
+    FRAME_p_1_sva_1 = 19'b0;
+    FRAME_acc_4_psp_sva = 12'b0;
+    acc_imod_7_sva = 6'b0;
+    FRAME_acc_3_psp_sva = 12'b0;
+    acc_imod_5_sva = 6'b0;
+    acc_imod_3_sva = 6'b0;
+    blue_2_sg1_sva = 15'b0;
+    green_2_sg1_sva = 15'b0;
+    red_2_sg1_sva = 15'b0;
+    exit_FRAME_for_1_sva_2 = 1'b0;
+    i_7_sva = 2'b0;
+    b_2_sva_1 = 16'b0;
+    g_2_sva_1 = 16'b0;
+    r_2_sva_1 = 16'b0;
+    b_0_sva_1 = 16'b0;
+    g_0_sva_1 = 16'b0;
+    r_0_sva_1 = 16'b0;
+    FRAME_for_1_slc_YMATRIX_rom_11_psp_sva = 1'b0;
+    exit_FRAME_for_lpi_1_dfm = 1'b0;
+    exit_FRAME_lpi_1_dfm = 1'b0;
+    b_1_sg1_lpi_1_dfm = 15'b0;
+    g_1_sg1_lpi_1_dfm = 15'b0;
+    r_1_sg1_lpi_1_dfm = 15'b0;
+    i_6_lpi_1_dfm = 2'b0;
+    b_2_lpi_1_dfm = 16'b0;
+    b_0_lpi_1_dfm = 16'b0;
+    g_2_lpi_1_dfm = 16'b0;
+    g_0_lpi_1_dfm = 16'b0;
+    r_2_lpi_1_dfm = 16'b0;
+    r_0_lpi_1_dfm = 16'b0;
+    regs_regs_2_lpi_1_dfm = 90'b0;
+    regs_regs_1_sva_dfm = 90'b0;
+    regs_regs_0_sva_dfm = 90'b0;
+    exit_FRAME_for_1_lpi_1_dfm = 1'b0;
+    FRAME_p_1_lpi_1_dfm = 19'b0;
+    exit_FRAME_1_sva = 1'b0;
+    regs_regs_0_sva = 90'b0;
+    regs_regs_1_sva = 90'b0;
+    i_7_lpi_1 = 2'b0;
+    exit_FRAME_for_lpi_1 = 1'b0;
+    i_6_lpi_1 = 2'b0;
+    r_2_lpi_1 = 16'b0;
+    r_0_lpi_1 = 16'b0;
+    r_1_sg1_lpi_1 = 15'b0;
+    g_2_lpi_1 = 16'b0;
+    g_0_lpi_1 = 16'b0;
+    g_1_sg1_lpi_1 = 15'b0;
+    b_2_lpi_1 = 16'b0;
+    b_0_lpi_1 = 16'b0;
+    b_1_sg1_lpi_1 = 15'b0;
+    FRAME_p_1_lpi_1 = 19'b0;
+    vout_rsc_mgc_out_stdreg_d <= 30'b0;
+  end
+
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [15:0] signext_16_1;
+    input [0:0] vector;
+  begin
+    signext_16_1= {{15{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [14:0] signext_15_1;
+    input [0:0] vector;
+  begin
+    signext_15_1= {{14{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [0:0] readslicef_3_1_2;
+    input [2:0] vector;
+    reg [2:0] tmp;
+  begin
+    tmp = vector >> 2;
+    readslicef_3_1_2 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [14:0] readslicef_16_15_1;
+    input [15:0] vector;
+    reg [15:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_16_15_1 = tmp[14:0];
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_8_1_7;
+    input [7:0] vector;
+    reg [7:0] tmp;
+  begin
+    tmp = vector >> 7;
+    readslicef_8_1_7 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] MUX_v_2_2_2;
+    input [3:0] inputs;
+    input [0:0] sel;
+    reg [1:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[3:2];
+      end
+      1'b1 : begin
+        result = inputs[1:0];
+      end
+      default : begin
+        result = inputs[3:2];
+      end
+    endcase
+    MUX_v_2_2_2 = result;
+  end
+  endfunction
+
+
+  function [14:0] MUX_v_15_2_2;
+    input [29:0] inputs;
+    input [0:0] sel;
+    reg [14:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[29:15];
+      end
+      1'b1 : begin
+        result = inputs[14:0];
+      end
+      default : begin
+        result = inputs[29:15];
+      end
+    endcase
+    MUX_v_15_2_2 = result;
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_22_11 ;
+    input [21:0]  vector ;
+  begin
+    conv_u2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_18_9 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2u_18_9 = vector[8:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_s2u_1_2 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_2 = {vector[0], vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_11_15 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_15 = {{4{vector[10]}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v9/cycle_mgc_ioport.v b/Sobel/sobel.v9/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v9/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v9/cycle_mgc_ioport_v2001.v b/Sobel/sobel.v9/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v9/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v9/cycle_set.tcl b/Sobel/sobel.v9/cycle_set.tcl
new file mode 100644
index 0000000..6c21a3e
--- /dev/null
+++ b/Sobel/sobel.v9/cycle_set.tcl
@@ -0,0 +1,157 @@
+
+# Loop constraints
+directive set /sobel/core/core:rlp CSTEPS_FROM {{. == 0}}
+directive set /sobel/core/core:rlp/main CSTEPS_FROM {{. == 3} {.. == 0}}
+
+# IO operation constraints
+directive set /sobel/core/core:rlp/main/FRAME:io_read(vin:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:io_write(vout:rsc.d) CSTEPS_FROM {{.. == 2}}
+
+# Real operation constraints
+directive set /sobel/core/core:rlp/main/and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#9 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#15:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#1 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#16:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mul#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#2 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#17:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:and#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:or#1 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#21:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mul#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#22:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mul#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#12 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#23:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mul#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2-3:acc#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2-3:acc#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2:acc#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/ACC2-3:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#9 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#11 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#13 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#12 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#15 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#23 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#17 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#18 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#19 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#20 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#21 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#22 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#24 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#27 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#26 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#28 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/acc#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#35 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#29 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#30 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#31 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#32 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#33 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#34 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#4 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#41 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:mul#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#42 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#36 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#37 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#38 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#39 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#40 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#2 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:or#3 CSTEPS_FROM {{.. == 2}}
+directive set /sobel/core/core:rlp/main/FRAME:acc#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:or CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#6:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#1 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#7:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#1 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#2 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#8:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#2 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#17 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:or#2 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#9:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#3 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#26 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#10:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#4 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#27 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#11:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#5 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#28 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#19 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:or#4 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#12:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#6 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#10 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#13:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#7 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#12 CSTEPS_FROM {{.. == 1}}
+directive set {/sobel/core/core:rlp/main/regs.operator[]#14:mux} CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mul#8 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#14 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc#16 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:acc CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:and#13 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for#1:mux#9 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#42 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#46 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#20 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#21 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#22 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#23 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#24 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#25 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#33 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#34 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#35 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#39 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#40 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#41 CSTEPS_FROM {{.. == 1}}
+directive set /sobel/core/core:rlp/main/FRAME:for:mux#44 CSTEPS_FROM {{.. == 1}}
diff --git a/Sobel/sobel.v9/directives.tcl b/Sobel/sobel.v9/directives.tcl
new file mode 100644
index 0000000..504c4bb
--- /dev/null
+++ b/Sobel/sobel.v9/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
+go extract
diff --git a/Sobel/sobel.v9/messages.txt b/Sobel/sobel.v9/messages.txt
new file mode 100644
index 0000000..e2ad891
--- /dev/null
+++ b/Sobel/sobel.v9/messages.txt
@@ -0,0 +1,252 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.14 seconds, memory usage 313484kB, peak memory usage 437356kB (SOL-9)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.cpp(156): last line of file ends without a newline (CRD-1)
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+$PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+$PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+          detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+
+# Messages from "go compile"
+
+Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'sobel' specified by directive (CIN-52)
+Synthesizing routine 'sobel' (CIN-13)
+Inlining routine 'sobel' (CIN-14)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+Optimizing block '/sobel' ... (CIN-4)
+Inout port 'vin' is only used as an input. (OPT-10)
+Inout port 'vout' is only used as an output. (OPT-11)
+Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME:for#1' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+Design 'sobel' was read (SOL-1)
+Optimizing partition '/sobel': (Total ops = 644, Real ops = 142, Vars = 142) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 644, Real ops = 142, Vars = 140) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 604, Real ops = 134, Vars = 146) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 604, Real ops = 134, Vars = 148) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 604, Real ops = 134, Vars = 148) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 604, Real ops = 134, Vars = 146) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 405, Real ops = 110, Vars = 97) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 380, Real ops = 110, Vars = 96) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 380, Real ops = 110, Vars = 96) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 380, Real ops = 110, Vars = 98) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 380, Real ops = 110, Vars = 98) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 360, Real ops = 108, Vars = 146) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 32) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 392, Real ops = 104, Vars = 24) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 303, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 303, Real ops = 94, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 298, Real ops = 94, Vars = 28) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+Completed transformation 'compile' on solution 'sobel.v9': elapsed time 4.46 seconds, memory usage 319744kB, peak memory usage 437356kB (SOL-9)
+Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'sobel.v9' (SOL-8)
+Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+Loop '/sobel/core/FRAME:for#1' is left rolled. (LOOP-4)
+Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+Loop '/sobel/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/sobel/core': (Total ops = 346, Real ops = 111, Vars = 23) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 21) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 20) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 20) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 283, Real ops = 90, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 23) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 283, Real ops = 90, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 34) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 237, Real ops = 105, Vars = 28) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 237, Real ops = 105, Vars = 33) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 237, Real ops = 105, Vars = 28) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 237, Real ops = 105, Vars = 33) (SOL-10)
+Design 'sobel' contains '216' real operations. (SOL-11)
+Optimizing partition '/sobel/core': (Total ops = 247, Real ops = 106, Vars = 32) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 640, Real ops = 174, Vars = 263) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 331, Real ops = 155, Vars = 76) (SOL-10)
+Optimizing partition '/sobel/core': (Total ops = 330, Real ops = 155, Vars = 75) (SOL-10)
+Completed transformation 'architect' on solution 'sobel.v9': elapsed time 11.28 seconds, memory usage 319928kB, peak memory usage 437356kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'sobel.v9' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 1843201, Area (Datapath, Register, Total) = 6576.18, 0.00, 6576.18 (CRAAS-11)
+Optimized LOOP 'main': Latency = 1843201, Area (Datapath, Register, Total) = 6570.04, 0.00, 6570.04 (CRAAS-10)
+Optimized LOOP 'main': Latency = 1843201, Area (Datapath, Register, Total) = 6519.24, 0.00, 6519.24 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 1843201, Area (Datapath, Register, Total) = 6519.24, 0.00, 6519.24 (CRAAS-12)
+Completed transformation 'allocate' on solution 'sobel.v9': elapsed time 1.44 seconds, memory usage 320116kB, peak memory usage 437356kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'sobel.v9' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 484, Real ops = 217, Vars = 158) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 474, Real ops = 216, Vars = 150) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 463, Real ops = 216, Vars = 149) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 441, Real ops = 208, Vars = 119) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 434, Real ops = 205, Vars = 120) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 448, Real ops = 205, Vars = 132) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 439, Real ops = 205, Vars = 125) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 443, Real ops = 204, Vars = 135) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 439, Real ops = 204, Vars = 125) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 453, Real ops = 204, Vars = 137) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 444, Real ops = 204, Vars = 130) (SOL-10)
+Optimizing partition '/sobel/sobel:core/core': (Total ops = 439, Real ops = 204, Vars = 125) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 453, Real ops = 204, Vars = 137) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 444, Real ops = 204, Vars = 130) (SOL-10)
+Completed transformation 'schedule' on solution 'sobel.v9': elapsed time 2.40 seconds, memory usage 319848kB, peak memory usage 437356kB (SOL-9)
+Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'sobel.v9' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 805, Real ops = 328, Vars = 743) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 796, Real ops = 328, Vars = 736) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 647, Real ops = 236, Vars = 109) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 638, Real ops = 236, Vars = 102) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 390, Real ops = 215, Vars = 108) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 381, Real ops = 215, Vars = 101) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+Completed transformation 'dpfsm' on solution 'sobel.v9': elapsed time 0.78 seconds, memory usage 320236kB, peak memory usage 437356kB (SOL-9)
+
+# Messages from "go extract"
+
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'sobel.v9' (SOL-8)
+Optimizing partition '/sobel': (Total ops = 481, Real ops = 250, Vars = 478) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 472, Real ops = 250, Vars = 471) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 109) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 102) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 461, Real ops = 247, Vars = 458) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 452, Real ops = 247, Vars = 451) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 461, Real ops = 247, Vars = 458) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 452, Real ops = 247, Vars = 451) (SOL-10)
+Reassigned operation FRAME:for#1:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/sobel': (Total ops = 461, Real ops = 247, Vars = 458) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 452, Real ops = 247, Vars = 451) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 356, Real ops = 209, Vars = 109) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 347, Real ops = 209, Vars = 102) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 356, Real ops = 209, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 347, Real ops = 209, Vars = 99) (SOL-10)
+Optimizing partition '/sobel': (Total ops = 356, Real ops = 209, Vars = 106) (SOL-10)
+Optimizing partition '/sobel/sobel:core': (Total ops = 347, Real ops = 209, Vars = 99) (SOL-10)
+Completed transformation 'extract' on solution 'sobel.v9': elapsed time 8.88 seconds, memory usage 320524kB, peak memory usage 437356kB (SOL-9)
diff --git a/Sobel/sobel.v9/reg_sharing.tcl b/Sobel/sobel.v9/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v9/reg_sharing.tcl
diff --git a/Sobel/sobel.v9/res_sharing.tcl b/Sobel/sobel.v9/res_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/Sobel/sobel.v9/res_sharing.tcl
diff --git a/Sobel/sobel.v9/rtl.rpt b/Sobel/sobel.v9/rtl.rpt
new file mode 100644
index 0000000..49c0be8
--- /dev/null
+++ b/Sobel/sobel.v9/rtl.rpt
@@ -0,0 +1,825 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-013                                 
+-- Generated date:              Tue Mar 08 15:38:54 +0000 2016                      
+
+Solution Settings: sobel.v9
+  Current state: extract
+  Project: Sobel
+  
+  Design Input Files Specified
+    $PROJECT_HOME/sobel.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/bmp_io.cpp
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/tb_blur.cpp
+      $MGC_HOME/shared/include/mc_testbench.h
+      $MGC_HOME/shared/include/mc_scverify.h
+      $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/bmp_io.h
+    $PROJECT_HOME/shift_class.h
+    $PROJECT_HOME/sobel.cpp
+      $MGC_HOME/shared/include/ac_fixed.h
+        $MGC_HOME/shared/include/ac_int.h
+      $PROJECT_HOME/sobel.h
+      $PROJECT_HOME/shift_class.h
+  
+  Processes/Blocks in Design
+    Process       Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ------------- ----------------------- ------- ---------- ------------ -- --------
+    /sobel/core                       220 1843201    1843200            0  1          
+    Design Total:                     220 1843201    1843200            0  0          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(10,0,10,0,10)                       11.241                       0.000     11.241 1.301          1           1 
+    mgc_add(10,0,9,1,10)                        11.000                       0.000     11.000 1.303          1           0 
+    mgc_add(11,0,10,1,12)                       12.000                       0.000     12.000 1.208          2           2 
+    mgc_add(12,0,11,0,12)                       13.228                       0.000     13.228 1.436          2           2 
+    mgc_add(15,0,11,1,15)                       16.000                       0.000     16.000 1.633          3           3 
+    mgc_add(15,0,15,0,15)                       16.198                       0.000     16.198 1.627          0           3 
+    mgc_add(16,0,12,1,16)                       17.000                       0.000     17.000 1.696         12          12 
+    mgc_add(16,0,16,0,16)                       17.189                       0.000     17.189 1.690          6           3 
+    mgc_add(19,0,2,1,19)                        20.000                       0.000     20.000 1.908          1           1 
+    mgc_add(2,0,1,0,2)                           3.315                       0.000      3.315 0.658          0           2 
+    mgc_add(2,0,1,1,2)                           3.000                       0.000      3.000 0.658          1           2 
+    mgc_add(2,0,2,0,2)                           3.311                       0.000      3.311 0.653          2           2 
+    mgc_add(3,0,3,0,3)                           4.302                       0.000      4.302 0.761          2           0 
+    mgc_add(3,0,3,0,4)                           4.302                       0.000      4.302 0.761         12          12 
+    mgc_add(4,0,4,0,5)                           5.293                       0.000      5.293 0.854          6           6 
+    mgc_add(5,0,4,0,6)                           6.288                       0.000      6.288 0.940          3           3 
+    mgc_add(5,0,5,0,5)                           6.285                       0.000      6.285 0.938          6           6 
+    mgc_add(5,0,5,0,6)                           6.285                       0.000      6.285 0.938          0           1 
+    mgc_add(6,0,5,1,8)                           7.000                       0.000      7.000 0.693          3           3 
+    mgc_add(6,0,6,0,6)                           7.276                       0.000      7.276 1.016          3           3 
+    mgc_add(8,0,7,0,8)                           9.262                       0.000      9.262 1.165          1           1 
+    mgc_add(9,0,8,1,10)                         10.000                       0.000     10.000 1.072          3           3 
+    mgc_and(1,2)                                 0.730                       0.000      0.730 0.263          0           6 
+    mgc_and(1,3)                                 1.054                       0.000      1.054 0.416          0           1 
+    mgc_and(15,2)                               10.947                       0.000     10.947 0.263          3           3 
+    mgc_and(16,2)                               11.677                       0.000     11.677 0.263          6           6 
+    mgc_and(19,2)                               13.867                       0.000     13.867 0.263          1           1 
+    mgc_and(2,2)                                 1.460                       0.000      1.460 0.263          6           2 
+    mgc_mul(2,0,9,0,11)                        330.250                       2.000     10.250 3.044          3           3 
+    mgc_mul(2,1,10,1,12)                       330.000                       2.000     10.000 3.087          9          15 
+    mgc_mul(3,0,6,0,9)                         330.250                       2.000     10.250 2.846          3           3 
+    mgc_mux(1,1,2)                               0.919                       0.000      0.919 0.369          4           3 
+    mgc_mux(10,2,4)                             22.259                       0.000     22.259 0.936         15          15 
+    mgc_mux(15,1,2)                             13.791                       0.000     13.791 0.369          3           3 
+    mgc_mux(16,1,2)                             14.711                       0.000     14.711 0.369          6           6 
+    mgc_mux(19,1,2)                             17.469                       0.000     17.469 0.369          1           1 
+    mgc_mux(2,1,2)                               1.839                       0.000      1.839 0.369          2           2 
+    mgc_mux(30,1,2)                             27.583                       0.000     27.583 0.369          0           1 
+    mgc_mux(90,1,2)                             82.748                       0.000     82.748 0.369          3           3 
+    mgc_nand(1,2)                                0.730                       0.000      0.730 0.268          0           4 
+    mgc_nand(1,3)                                1.054                       0.000      1.054 0.425          0           1 
+    mgc_nor(1,2)                                 0.730                       0.000      0.730 0.263          0           4 
+    mgc_not(1)                                   0.000                       0.000      0.000 0.000          0          28 
+    mgc_not(3)                                   0.000                       0.000      0.000 0.000          0          12 
+    mgc_or(1,2)                                  0.730                       0.000      0.730 0.268          0           6 
+    mgc_or(1,3)                                  1.054                       0.000      1.054 0.425          0           3 
+    mgc_or(10,2)                                 7.298                       0.000      7.298 0.268          1           1 
+    mgc_or(2,2)                                  1.460                       0.000      1.460 0.268          4           0 
+    mgc_or(6,2)                                  4.379                       0.000      4.379 0.268          1           1 
+    mgc_reg_pos(1,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0          12 
+    mgc_reg_pos(11,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           2 
+    mgc_reg_pos(15,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(16,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           6 
+    mgc_reg_pos(19,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(2,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_reg_pos(30,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(5,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(6,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           4 
+    mgc_reg_pos(9,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(90,1,0,0,0,1,1)                  0.000                       0.000      0.000 0.000          0           3 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,90)                            0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(2,30)                         0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):            8527.433                      42.000   1807.000                              
+    
+  Area Scores
+                      Post-Scheduling   Post-DP & FSM Post-Assignment 
+    ----------------- --------------- --------------- ---------------
+    Total Area Score:   6519.2          8702.1          8527.4        
+    Total Reg:             0.0             0.0             0.0        
+                                                                      
+    DataPath:           6519.2 (100%)   8702.1 (100%)   8527.4 (100%) 
+      MUX:               736.6  (11%)    935.3  (11%)    763.3   (9%) 
+      FUNC:             5639.6  (87%)   7614.9  (88%)   7612.9  (89%) 
+      LOGIC:             143.0   (2%)    152.0   (2%)    151.2   (2%) 
+      BUFFER:              0.0             0.0             0.0        
+      MEM:                 0.0             0.0             0.0        
+      ROM:                 0.0             0.0             0.0        
+      REG:                 0.0             0.0             0.0        
+                                                                      
+    
+    FSM:                   0.0             0.0             0.0        
+      FSM-REG:             0.0             0.0             0.0        
+      FSM-COMB:            0.0             0.0             0.0        
+                                                                      
+    
+  Register-to-Variable Mappings
+    Register                        Size(bits) Gated Register CG Opt Done Variables                                             
+    ------------------------------- ---------- -------------- ----------- -----------------------------------------------------
+    regs.regs(0).sva                        90         Y                  regs.regs(0).sva                                      
+    regs.regs(1).sva                        90         Y                  regs.regs(1).sva                                      
+    regs.regs(2).lpi#1.dfm                  90         Y                  regs.regs(2).lpi#1.dfm                                
+    vout:rsc:mgc_out_stdreg.d               30         Y                  vout:rsc:mgc_out_stdreg.d                             
+    FRAME:p#1.lpi#1                         19         Y                  FRAME:p#1.lpi#1                                       
+    b(0).lpi#1                              16         Y                  b(0).lpi#1                                            
+    b(2).lpi#1                              16         Y                  b(2).lpi#1                                            
+    g(0).lpi#1                              16         Y                  g(0).lpi#1                                            
+    g(2).lpi#1                              16         Y                  g(2).lpi#1                                            
+    r(0).lpi#1                              16         Y                  r(0).lpi#1                                            
+    r(2).lpi#1                              16         Y                  r(2).lpi#1                                            
+    b(1).sg1.lpi#1                          15         Y                  b(1).sg1.lpi#1                                        
+    g(1).sg1.lpi#1                          15         Y                  g(1).sg1.lpi#1                                        
+    r(1).sg1.lpi#1                          15         Y                  r(1).sg1.lpi#1                                        
+    FRAME:mul#2.itm#1                       11         Y                  FRAME:mul#2.itm#1                                     
+    FRAME:mul#4.itm#1                       11         Y                  FRAME:mul#4.itm#1                                     
+    FRAME:mul#1.itm#1                        9         Y                  FRAME:mul#1.itm#1                                     
+    FRAME:mul#3.itm#1                        9         Y                  FRAME:mul#3.itm#1                                     
+    FRAME:mul#5.itm#1                        9         Y                  FRAME:mul#5.itm#1                                     
+    FRAME:acc#41.itm#3                       6         Y                  FRAME:acc#41.itm#3                                    
+    blue:slc(blue#2.sg1).itm#1               6         Y                  blue:slc(blue#2.sg1).itm#1                            
+    green:slc(green#2.sg1).itm#1             6         Y                  green:slc(green#2.sg1).itm#1                          
+    red:slc(red#2.sg1).itm#1                 6         Y                  red:slc(red#2.sg1).itm#1                              
+    FRAME:acc#18.itm#1                       5         Y                  FRAME:acc#18.itm#1                                    
+    FRAME:acc#30.itm#1                       5         Y                  FRAME:acc#30.itm#1                                    
+    FRAME:acc#37.itm#1                       5         Y                  FRAME:acc#37.itm#1                                    
+    FRAME:acc#41.itm#1.sg1                   2         Y                  FRAME:acc#41.itm#1.sg1                                
+    FRAME:acc#41.itm#1.sg2                   2         Y                  FRAME:acc#41.itm#1.sg2                                
+    i#6.lpi#1                                2         Y                  i#6.lpi#1                                             
+    i#7.lpi#1                                2         Y                  i#7.lpi#1                                             
+    FRAME:slc(acc.imod#3)#4.itm#1            1         Y                  FRAME:slc(acc.imod#3)#4.itm#1                         
+    FRAME:slc(acc.imod#5)#4.itm#1            1         Y                  FRAME:slc(acc.imod#5)#4.itm#1                         
+    FRAME:slc(acc.imod#7)#4.itm#1            1         Y                  FRAME:slc(acc.imod#7)#4.itm#1                         
+    blue:slc(blue#2.sg1)#12.itm#1            1         Y                  blue:slc(blue#2.sg1)#12.itm#1                         
+    exit:FRAME#1.sva                         1         Y                  exit:FRAME#1.sva                                      
+    exit:FRAME.lpi#1.dfm#2                   1         Y                  exit:FRAME.lpi#1.dfm#2                                
+    exit:FRAME:for#1.lpi#1.dfm#4             1         Y                  exit:FRAME:for#1.lpi#1.dfm#4                          
+    exit:FRAME:for#1.sva#2.st#1              1         Y                  exit:FRAME:for#1.sva#2.st#1                           
+    exit:FRAME:for.lpi#1                     1         Y                  exit:FRAME:for.lpi#1                                  
+    exit:FRAME:for.lpi#1.dfm.st#1            1         Y                  exit:FRAME:for.lpi#1.dfm.st#1                         
+    green:slc(green#2.sg1)#12.itm#1          1         Y                  green:slc(green#2.sg1)#12.itm#1                       
+    main.stage_0#2                           1         Y                  main.stage_0#2                                        
+                                                                                                                                
+    Total:                                 568            568           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  15.158629
+      Slack:      4.8413710000000005
+      
+      Path                                           Startpoint                             Endpoint                           Delay   Slack   
+      ---------------------------------------------- -------------------------------------- ---------------------------------- ------- -------
+      1                                              sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#37.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(2).lpi#1.dfm)       mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(2).lpi#1.dfm                                                                                      0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)#2                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#21:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#21:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#6                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#6.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#10                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/r(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(r(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(r(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc                          mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc.itm                                                                                                0.0000  7.3461  
+        sobel:core/ACC2:conc                                                                                                   0.0000  7.3461  
+        sobel:core/ACC2:conc.itm                                                                                               0.0000  7.3461  
+        sobel:core/ACC2-3:acc#1                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#1.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc                                                                                                    0.0000  9.0359  
+        sobel:core/red#2.sg1.sva                                                                                               0.0000  9.0359  
+        sobel:core/slc(red#2.sg1.sva)                                                                                          0.0000  9.0359  
+        sobel:core/slc(red#2.sg1.sva).itm                                                                                      0.0000  9.0359  
+        sobel:core/FRAME:acc#8                       mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#8.itm                                                                                             0.0000  9.7968  
+        sobel:core/FRAME:acc#10                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#10.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#11                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#11.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#3                             mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#3.sva                                                                                              0.0000  12.6066 
+        sobel:core/slc(acc.imod#3.sva)#1                                                                                       0.0000  12.6066 
+        sobel:core/slc(acc.imod#3.sva)#1.itm                                                                                   0.0000  12.6066 
+        sobel:core/conc#142                                                                                                    0.0000  12.6066 
+        sobel:core/conc#142.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#42                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#42.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#7                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#7.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#39                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#39.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#141                                                                                                    0.0000  13.5442 
+        sobel:core/conc#141.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#36                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#36.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#37                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#37.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#37.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      2                                              sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(2).lpi#1.dfm)       mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(2).lpi#1.dfm                                                                                      0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)#1                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#22:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#22:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#7                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#7.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#12                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/g(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#7                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#7.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#1                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#1.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#2                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#2.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#1                                                                                                  0.0000  9.0359  
+        sobel:core/green#2.sg1.sva                                                                                             0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#1                                                                                      0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#1.itm                                                                                  0.0000  9.0359  
+        sobel:core/FRAME:acc#13                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#13.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#15                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#15.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#16                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#16.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#5                             mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#5.sva                                                                                              0.0000  12.6066 
+        sobel:core/slc(acc.imod#5.sva)#1                                                                                       0.0000  12.6066 
+        sobel:core/slc(acc.imod#5.sva)#1.itm                                                                                   0.0000  12.6066 
+        sobel:core/conc#146                                                                                                    0.0000  12.6066 
+        sobel:core/conc#146.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#23                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#23.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#5                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#5.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#43                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#43.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#145                                                                                                    0.0000  13.5442 
+        sobel:core/conc#145.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#17                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#17.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#18                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#18.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#18.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      3                                              sobel:core/reg(regs.regs(1).sva)       sobel:core/reg(FRAME:acc#37.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(1).sva)             mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(1).sva                                                                                            0.0000  0.0000  
+        sobel:core/slc(regs.regs(1).sva)#2                                                                                     0.0000  0.0000  
+        sobel:core/slc(regs.regs(1).sva)#2.itm                                                                                 0.0000  0.0000  
+        sobel:core/regs.operator[]#21:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#21:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#6                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#6.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#10                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/r(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(r(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(r(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc                          mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc.itm                                                                                                0.0000  7.3461  
+        sobel:core/ACC2:conc                                                                                                   0.0000  7.3461  
+        sobel:core/ACC2:conc.itm                                                                                               0.0000  7.3461  
+        sobel:core/ACC2-3:acc#1                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#1.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc                                                                                                    0.0000  9.0359  
+        sobel:core/red#2.sg1.sva                                                                                               0.0000  9.0359  
+        sobel:core/slc(red#2.sg1.sva)                                                                                          0.0000  9.0359  
+        sobel:core/slc(red#2.sg1.sva).itm                                                                                      0.0000  9.0359  
+        sobel:core/FRAME:acc#8                       mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#8.itm                                                                                             0.0000  9.7968  
+        sobel:core/FRAME:acc#10                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#10.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#11                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#11.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#3                             mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#3.sva                                                                                              0.0000  12.6066 
+        sobel:core/slc(acc.imod#3.sva)#1                                                                                       0.0000  12.6066 
+        sobel:core/slc(acc.imod#3.sva)#1.itm                                                                                   0.0000  12.6066 
+        sobel:core/conc#142                                                                                                    0.0000  12.6066 
+        sobel:core/conc#142.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#42                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#42.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#7                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#7.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#39                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#39.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#141                                                                                                    0.0000  13.5442 
+        sobel:core/conc#141.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#36                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#36.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#37                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#37.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#37.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      4                                              sobel:core/reg(regs.regs(0).sva)       sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(0).sva)             mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(0).sva                                                                                            0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva)#1                                                                                     0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva)#1.itm                                                                                 0.0000  0.0000  
+        sobel:core/regs.operator[]#22:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#22:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#7                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#7.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#12                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/g(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#7                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#7.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#1                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#1.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#2                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#2.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#1                                                                                                  0.0000  9.0359  
+        sobel:core/green#2.sg1.sva                                                                                             0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#1                                                                                      0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#1.itm                                                                                  0.0000  9.0359  
+        sobel:core/FRAME:acc#13                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#13.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#15                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#15.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#16                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#16.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#5                             mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#5.sva                                                                                              0.0000  12.6066 
+        sobel:core/slc(acc.imod#5.sva)#1                                                                                       0.0000  12.6066 
+        sobel:core/slc(acc.imod#5.sva)#1.itm                                                                                   0.0000  12.6066 
+        sobel:core/conc#146                                                                                                    0.0000  12.6066 
+        sobel:core/conc#146.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#23                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#23.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#5                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#5.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#43                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#43.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#145                                                                                                    0.0000  13.5442 
+        sobel:core/conc#145.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#17                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#17.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#18                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#18.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#18.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      5                                              sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(2).lpi#1.dfm)       mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(2).lpi#1.dfm                                                                                      0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)#1                                                                               0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm                                                                           0.0000  0.0000  
+        sobel:core/regs.operator[]#22:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#22:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#7                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#7.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#12                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/g(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#7                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#7.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#1                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#1.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#2                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#2.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#1                                                                                                  0.0000  9.0359  
+        sobel:core/green#2.sg1.sva                                                                                             0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#12                                                                                     0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#12.itm                                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#37                      mgc_not_1                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#37.itm                                                                                            0.0000  9.0359  
+        sobel:core/conc#155                                                                                                    0.0000  9.0359  
+        sobel:core/conc#155.itm                                                                                                0.0000  9.0359  
+        sobel:core/FRAME:acc#12                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#12.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#15                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#15.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#16                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#16.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#5                             mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#5.sva                                                                                              0.0000  12.6066 
+        sobel:core/slc(acc.imod#5.sva)#1                                                                                       0.0000  12.6066 
+        sobel:core/slc(acc.imod#5.sva)#1.itm                                                                                   0.0000  12.6066 
+        sobel:core/conc#146                                                                                                    0.0000  12.6066 
+        sobel:core/conc#146.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#23                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#23.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#5                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#5.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#43                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#43.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#145                                                                                                    0.0000  13.5442 
+        sobel:core/conc#145.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#17                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#17.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#18                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#18.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#18.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      6                                              sobel:core/reg(regs.regs(0).sva)       sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(0).sva)             mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(0).sva                                                                                            0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva)#1                                                                                     0.0000  0.0000  
+        sobel:core/slc(regs.regs(0).sva)#1.itm                                                                                 0.0000  0.0000  
+        sobel:core/regs.operator[]#22:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#22:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#7                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#7.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#12                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/g(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#7                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#7.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#1                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#1.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#2                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#2.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#1                                                                                                  0.0000  9.0359  
+        sobel:core/green#2.sg1.sva                                                                                             0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#12                                                                                     0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#12.itm                                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#37                      mgc_not_1                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#37.itm                                                                                            0.0000  9.0359  
+        sobel:core/conc#155                                                                                                    0.0000  9.0359  
+        sobel:core/conc#155.itm                                                                                                0.0000  9.0359  
+        sobel:core/FRAME:acc#12                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#12.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#15                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#15.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#16                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#16.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#5                             mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#5.sva                                                                                              0.0000  12.6066 
+        sobel:core/slc(acc.imod#5.sva)#1                                                                                       0.0000  12.6066 
+        sobel:core/slc(acc.imod#5.sva)#1.itm                                                                                   0.0000  12.6066 
+        sobel:core/conc#146                                                                                                    0.0000  12.6066 
+        sobel:core/conc#146.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#23                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#23.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#5                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#5.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#43                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#43.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#145                                                                                                    0.0000  13.5442 
+        sobel:core/conc#145.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#17                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#17.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#18                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#18.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#18.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      7                                              sobel:core/reg(regs.regs(1).sva)       sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(1).sva)             mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(1).sva                                                                                            0.0000  0.0000  
+        sobel:core/slc(regs.regs(1).sva)#1                                                                                     0.0000  0.0000  
+        sobel:core/slc(regs.regs(1).sva)#1.itm                                                                                 0.0000  0.0000  
+        sobel:core/regs.operator[]#22:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#22:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#7                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#7.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#12                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/g(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(g(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#7                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#7.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#1                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#1.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#2                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#2.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#1                                                                                                  0.0000  9.0359  
+        sobel:core/green#2.sg1.sva                                                                                             0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#12                                                                                     0.0000  9.0359  
+        sobel:core/slc(green#2.sg1.sva)#12.itm                                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#37                      mgc_not_1                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#37.itm                                                                                            0.0000  9.0359  
+        sobel:core/conc#155                                                                                                    0.0000  9.0359  
+        sobel:core/conc#155.itm                                                                                                0.0000  9.0359  
+        sobel:core/FRAME:acc#12                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#12.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#15                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#15.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#16                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#16.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#5                             mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#5.sva                                                                                              0.0000  12.6066 
+        sobel:core/slc(acc.imod#5.sva)#1                                                                                       0.0000  12.6066 
+        sobel:core/slc(acc.imod#5.sva)#1.itm                                                                                   0.0000  12.6066 
+        sobel:core/conc#146                                                                                                    0.0000  12.6066 
+        sobel:core/conc#146.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#23                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#23.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#5                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#5.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#43                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#43.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#145                                                                                                    0.0000  13.5442 
+        sobel:core/conc#145.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#17                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#17.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#18                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#18.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#18.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      8                                              sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#30.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(2).lpi#1.dfm)       mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(2).lpi#1.dfm                                                                                      0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm).itm                                                                             0.0000  0.0000  
+        sobel:core/regs.operator[]#23:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#23:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#8                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#8.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#14                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/b(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(b(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(b(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#8                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#8.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#2                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#2.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#3                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#3.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#2                                                                                                  0.0000  9.0359  
+        sobel:core/blue#2.sg1.sva                                                                                              0.0000  9.0359  
+        sobel:core/slc(blue#2.sg1.sva)#1                                                                                       0.0000  9.0359  
+        sobel:core/slc(blue#2.sg1.sva)#1.itm                                                                                   0.0000  9.0359  
+        sobel:core/FRAME:acc#25                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#25.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#27                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#27.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#28                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#28.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#7                             mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#7.sva                                                                                              0.0000  12.6066 
+        sobel:core/slc(acc.imod#7.sva)#1                                                                                       0.0000  12.6066 
+        sobel:core/slc(acc.imod#7.sva)#1.itm                                                                                   0.0000  12.6066 
+        sobel:core/conc#144                                                                                                    0.0000  12.6066 
+        sobel:core/conc#144.itm                                                                                                0.0000  12.6066 
+        sobel:core/FRAME:acc#35                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#35.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#6                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#6.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#41                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#41.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#143                                                                                                    0.0000  13.5442 
+        sobel:core/conc#143.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#29                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#29.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#30                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#30.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#30.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      9                                              sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#30.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(2).lpi#1.dfm)       mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(2).lpi#1.dfm                                                                                      0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm).itm                                                                             0.0000  0.0000  
+        sobel:core/regs.operator[]#23:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#23:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#8                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#8.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#14                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/b(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(b(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(b(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#8                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#8.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#2                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#2.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#3                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#3.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#2                                                                                                  0.0000  9.0359  
+        sobel:core/blue#2.sg1.sva                                                                                              0.0000  9.0359  
+        sobel:core/slc(blue#2.sg1.sva)#1                                                                                       0.0000  9.0359  
+        sobel:core/slc(blue#2.sg1.sva)#1.itm                                                                                   0.0000  9.0359  
+        sobel:core/FRAME:acc#25                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#25.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#27                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#27.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#28                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#28.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#7                             mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#7.sva                                                                                              0.0000  12.6066 
+        sobel:core/slc(acc.imod#7.sva)#2                                                                                       0.0000  12.6066 
+        sobel:core/slc(acc.imod#7.sva)#2.itm                                                                                   0.0000  12.6066 
+        sobel:core/FRAME:not#21                      mgc_not_3                                                                 0.0000  12.6066 
+        sobel:core/FRAME:not#21.itm                                                                                            0.0000  12.6066 
+        sobel:core/FRAME:conc#29                                                                                               0.0000  12.6066 
+        sobel:core/FRAME:conc#29.itm                                                                                           0.0000  12.6066 
+        sobel:core/FRAME:acc#35                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#35.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#6                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#6.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#41                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#41.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#143                                                                                                    0.0000  13.5442 
+        sobel:core/conc#143.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#29                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#29.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#30                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#30.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#30.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      10                                             sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#30.itm#1) 15.1586 4.8414  
+                                                                                                                                               
+        Instance                                     Component                                                                 Delta   Delay   
+        --------                                     ---------                                                                 -----   -----   
+        sobel:core/reg(regs.regs(2).lpi#1.dfm)       mgc_reg_pos_90_1_0_0_0_1_1                                                0.0000  0.0000  
+        sobel:core/regs.regs(2).lpi#1.dfm                                                                                      0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm)                                                                                 0.0000  0.0000  
+        sobel:core/slc(regs.regs(2).lpi#1.dfm).itm                                                                             0.0000  0.0000  
+        sobel:core/regs.operator[]#23:mux            mgc_mux_10_2_4                                                            0.9364  0.9364  
+        sobel:core/regs.operator[]#23:mux.itm                                                                                  0.0000  0.9364  
+        sobel:core/FRAME:for#1:mul#8                 mgc_mul_2_1_10_1_12                                                       3.0868  4.0232  
+        sobel:core/FRAME:for#1:mul#8.itm                                                                                       0.0000  4.0232  
+        sobel:core/FRAME:for#1:acc#14                mgc_add_16_0_12_1_16                                                      1.6960  5.7193  
+        sobel:core/b(2).sva#1                                                                                                  0.0000  5.7193  
+        sobel:core/slc(b(2).sva#1)                                                                                             0.0000  5.7193  
+        sobel:core/slc(b(2).sva#1).itm                                                                                         0.0000  5.7193  
+        sobel:core/ACC2:acc#8                        mgc_add_15_0_15_0_15                                                      1.6269  7.3461  
+        sobel:core/ACC2:acc#8.itm                                                                                              0.0000  7.3461  
+        sobel:core/ACC2:conc#2                                                                                                 0.0000  7.3461  
+        sobel:core/ACC2:conc#2.itm                                                                                             0.0000  7.3461  
+        sobel:core/ACC2-3:acc#3                      mgc_add_16_0_16_0_16                                                      1.6898  9.0359  
+        sobel:core/ACC2-3:acc#3.itm                                                                                            0.0000  9.0359  
+        sobel:core/ACC2:slc#2                                                                                                  0.0000  9.0359  
+        sobel:core/blue#2.sg1.sva                                                                                              0.0000  9.0359  
+        sobel:core/slc(blue#2.sg1.sva)#3                                                                                       0.0000  9.0359  
+        sobel:core/slc(blue#2.sg1.sva)#3.itm                                                                                   0.0000  9.0359  
+        sobel:core/FRAME:not#18                      mgc_not_3                                                                 0.0000  9.0359  
+        sobel:core/FRAME:not#18.itm                                                                                            0.0000  9.0359  
+        sobel:core/FRAME:acc#25                      mgc_add_3_0_3_0_4                                                         0.7609  9.7968  
+        sobel:core/FRAME:acc#25.itm                                                                                            0.0000  9.7968  
+        sobel:core/FRAME:acc#27                      mgc_add_4_0_4_0_5                                                         0.8536  10.6503 
+        sobel:core/FRAME:acc#27.itm                                                                                            0.0000  10.6503 
+        sobel:core/FRAME:acc#28                      mgc_add_5_0_4_0_6                                                         0.9400  11.5904 
+        sobel:core/FRAME:acc#28.itm                                                                                            0.0000  11.5904 
+        sobel:core/acc#7                             mgc_add_6_0_6_0_6                                                         1.0162  12.6066 
+        sobel:core/acc.imod#7.sva                                                                                              0.0000  12.6066 
+        sobel:core/slc(acc.imod#7.sva)#2                                                                                       0.0000  12.6066 
+        sobel:core/slc(acc.imod#7.sva)#2.itm                                                                                   0.0000  12.6066 
+        sobel:core/FRAME:not#21                      mgc_not_3                                                                 0.0000  12.6066 
+        sobel:core/FRAME:not#21.itm                                                                                            0.0000  12.6066 
+        sobel:core/FRAME:conc#29                                                                                               0.0000  12.6066 
+        sobel:core/FRAME:conc#29.itm                                                                                           0.0000  12.6066 
+        sobel:core/FRAME:acc#35                      mgc_add_5_0_5_0_5                                                         0.9376  13.5442 
+        sobel:core/FRAME:acc#35.itm                                                                                            0.0000  13.5442 
+        sobel:core/FRAME:slc#6                                                                                                 0.0000  13.5442 
+        sobel:core/FRAME:slc#6.itm                                                                                             0.0000  13.5442 
+        sobel:core/FRAME:not#41                      mgc_not_1                                                                 0.0000  13.5442 
+        sobel:core/FRAME:not#41.itm                                                                                            0.0000  13.5442 
+        sobel:core/conc#143                                                                                                    0.0000  13.5442 
+        sobel:core/conc#143.itm                                                                                                0.0000  13.5442 
+        sobel:core/FRAME:acc#29                      mgc_add_3_0_3_0_4                                                         0.7609  14.3051 
+        sobel:core/FRAME:acc#29.itm                                                                                            0.0000  14.3051 
+        sobel:core/FRAME:acc#30                      mgc_add_4_0_4_0_5                                                         0.8536  15.1586 
+        sobel:core/FRAME:acc#30.itm                                                                                            0.0000  15.1586 
+        sobel:core/reg(FRAME:acc#30.itm#1)           mgc_reg_pos_5_1_0_0_0_1_1                                                 0.0000  15.1586 
+                                                                                                                                               
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                        Port                               Slack (Delay) Messages 
+      ----------------------------------------------- -------------------------------- ------- ------- --------
+      sobel:core/reg(vout:rsc:mgc_out_stdreg.d)       mux.itm                          14.0161  5.9839          
+      sobel:core/reg(FRAME:acc#41.itm#1.sg2)          FRAME:acc#43.itm                  7.2622 12.7378          
+      sobel:core/reg(FRAME:acc#41.itm#1.sg1)          slc(FRAME:mul.sdt)#2.itm          7.9199 12.0801          
+      sobel:core/reg(FRAME:acc#41.itm#3)              FRAME:acc#44.itm                  6.9824 13.0176          
+      sobel:core/reg(FRAME:mul#1.itm#1)               FRAME:mul#1.itm                   8.1180 11.8820          
+      sobel:core/reg(red:slc(red#2.sg1).itm#1)        slc(red#2.sg1.sva)#1.itm         10.9641  9.0359          
+      sobel:core/reg(FRAME:acc#37.itm#1)              FRAME:acc#37.itm                  4.8414 15.1586          
+      sobel:core/reg(FRAME:slc(acc.imod#3)#4.itm#1)   slc(acc.imod#3.sva).itm           7.3934 12.6066          
+      sobel:core/reg(FRAME:mul#4.itm#1)               FRAME:mul#4.itm                   7.9199 12.0801          
+      sobel:core/reg(FRAME:mul#5.itm#1)               FRAME:mul#5.itm                   8.1180 11.8820          
+      sobel:core/reg(blue:slc(blue#2.sg1).itm#1)      slc(blue#2.sg1.sva)#2.itm        10.9641  9.0359          
+      sobel:core/reg(FRAME:acc#30.itm#1)              FRAME:acc#30.itm                  4.8414 15.1586          
+      sobel:core/reg(FRAME:slc(acc.imod#7)#4.itm#1)   slc(acc.imod#7.sva).itm           7.3934 12.6066          
+      sobel:core/reg(blue:slc(blue#2.sg1)#12.itm#1)   slc(blue#2.sg1.sva).itm          10.9641  9.0359          
+      sobel:core/reg(FRAME:mul#2.itm#1)               FRAME:mul#2.itm                   7.9199 12.0801          
+      sobel:core/reg(FRAME:mul#3.itm#1)               FRAME:mul#3.itm                   8.1180 11.8820          
+      sobel:core/reg(green:slc(green#2.sg1).itm#1)    slc(green#2.sg1.sva)#2.itm       10.9641  9.0359          
+      sobel:core/reg(FRAME:acc#18.itm#1)              FRAME:acc#18.itm                  4.8414 15.1586          
+      sobel:core/reg(FRAME:slc(acc.imod#5)#4.itm#1)   slc(acc.imod#5.sva).itm           7.3934 12.6066          
+      sobel:core/reg(green:slc(green#2.sg1)#12.itm#1) slc(green#2.sg1.sva).itm         10.9641  9.0359          
+      sobel:core/reg(exit:FRAME:for#1.sva#2.st#1)     FRAME:for#1:not#7.itm            18.6898  1.3102          
+      sobel:core/reg(exit:FRAME:for.lpi#1.dfm.st#1)   exit:FRAME:for.lpi#1.dfm         18.3131  1.6869          
+      sobel:core/reg(i#7.lpi#1)                       mux#1.itm                        17.5333  2.4667          
+      sobel:core/reg(exit:FRAME:for.lpi#1)            mux#2.itm                        17.7958  2.2042          
+      sobel:core/reg(exit:FRAME:for#1.lpi#1.dfm#4)    exit:FRAME:for#1.lpi#1.dfm#4:mx0 15.7649  4.2351          
+      sobel:core/reg(exit:FRAME#1.sva)                FRAME:and.itm                    15.7649  4.2351          
+      sobel:core/reg(main.stage_0#2)                  Cn1_1#4                          20.0000  0.0000          
+      sobel:core/reg(regs.regs(2).lpi#1.dfm)          regs.regs(2).lpi#1.dfm:mx0       13.2803  6.7197          
+      sobel:core/reg(regs.regs(1).sva)                regs.regs(1).sva.dfm:mx0         13.2803  6.7197          
+      sobel:core/reg(regs.regs(0).sva)                regs.regs(0).sva.dfm:mx0         13.2803  6.7197          
+      sobel:core/reg(exit:FRAME.lpi#1.dfm#2)          exit:FRAME.lpi#1.dfm#2:mx0       16.0328  3.9672          
+      sobel:core/reg(b(1).sg1.lpi#1)                  mux#8.itm                        13.0411  6.9589          
+      sobel:core/reg(g(1).sg1.lpi#1)                  mux#9.itm                        13.0411  6.9589          
+      sobel:core/reg(r(1).sg1.lpi#1)                  mux#10.itm                       13.0411  6.9589          
+      sobel:core/reg(i#6.lpi#1)                       mux#11.itm                       18.4535  1.5465          
+      sobel:core/reg(b(2).lpi#1)                      mux#12.itm                       13.2803  6.7197          
+      sobel:core/reg(b(0).lpi#1)                      mux#13.itm                       13.2803  6.7197          
+      sobel:core/reg(g(2).lpi#1)                      mux#14.itm                       13.2803  6.7197          
+      sobel:core/reg(g(0).lpi#1)                      mux#15.itm                       13.2803  6.7197          
+      sobel:core/reg(r(2).lpi#1)                      mux#16.itm                       13.2803  6.7197          
+      sobel:core/reg(r(0).lpi#1)                      mux#17.itm                       13.2803  6.7197          
+      sobel:core/reg(FRAME:p#1.lpi#1)                 mux#18.itm                       17.4604  2.5396          
+      sobel                                           vout:rsc.z                       20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                   19     1 
+    -                   16    15 
+    -                   15     6 
+    -                   12     4 
+    -                   10     4 
+    -                    8     4 
+    -                    6     7 
+    -                    5    12 
+    -                    4    12 
+    -                    2     6 
+    and                          
+    -                    3     1 
+    -                    2    18 
+    mul                          
+    -                   12    15 
+    -                   11     3 
+    -                    9     3 
+    mux                          
+    -                    2    15 
+    -                    1    19 
+    nand                         
+    -                    3     1 
+    -                    2     4 
+    nor                          
+    -                    2     4 
+    not                          
+    -                    3    12 
+    -                    1    28 
+    or                           
+    -                    3     3 
+    -                    2     8 
+    read_port                    
+    -                   90     1 
+    reg                          
+    -                   90     3 
+    -                   30     1 
+    -                   19     1 
+    -                   16     6 
+    -                   15     3 
+    -                   11     2 
+    -                    9     3 
+    -                    6     4 
+    -                    5     3 
+    -                    2     4 
+    -                    1    12 
+    write_port                   
+    -                   30     1 
+    
+  End of Report
diff --git a/Sobel/sobel.v9/rtl.v b/Sobel/sobel.v9/rtl.v
new file mode 100644
index 0000000..9d97352
--- /dev/null
+++ b/Sobel/sobel.v9/rtl.v
@@ -0,0 +1,912 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-013
+//  Generated date: Tue Mar 08 15:38:55 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    sobel_core
+// ------------------------------------------------------------------
+
+
+module sobel_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+  reg [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  wire and_dcpl_1;
+  wire or_dcpl_2;
+  reg [18:0] FRAME_p_1_lpi_1;
+  reg [14:0] b_1_sg1_lpi_1;
+  reg [15:0] b_0_lpi_1;
+  reg [15:0] b_2_lpi_1;
+  reg [14:0] g_1_sg1_lpi_1;
+  reg [15:0] g_0_lpi_1;
+  reg [15:0] g_2_lpi_1;
+  reg [14:0] r_1_sg1_lpi_1;
+  reg [15:0] r_0_lpi_1;
+  reg [15:0] r_2_lpi_1;
+  reg [1:0] i_6_lpi_1;
+  reg exit_FRAME_for_lpi_1;
+  reg [1:0] i_7_lpi_1;
+  reg [89:0] regs_regs_1_sva;
+  reg [89:0] regs_regs_0_sva;
+  reg exit_FRAME_1_sva;
+  reg [89:0] regs_regs_2_lpi_1_dfm;
+  reg exit_FRAME_lpi_1_dfm_2;
+  reg exit_FRAME_for_1_lpi_1_dfm_4;
+  reg [10:0] FRAME_mul_2_itm_1;
+  wire [21:0] nl_FRAME_mul_2_itm_1;
+  reg [8:0] FRAME_mul_3_itm_1;
+  wire [17:0] nl_FRAME_mul_3_itm_1;
+  reg [5:0] green_slc_green_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_18_itm_1;
+  wire [5:0] nl_FRAME_acc_18_itm_1;
+  reg FRAME_slc_acc_imod_5_4_itm_1;
+  reg green_slc_green_2_sg1_12_itm_1;
+  reg [10:0] FRAME_mul_4_itm_1;
+  wire [21:0] nl_FRAME_mul_4_itm_1;
+  reg [8:0] FRAME_mul_5_itm_1;
+  wire [17:0] nl_FRAME_mul_5_itm_1;
+  reg [5:0] blue_slc_blue_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_30_itm_1;
+  wire [5:0] nl_FRAME_acc_30_itm_1;
+  reg FRAME_slc_acc_imod_7_4_itm_1;
+  reg blue_slc_blue_2_sg1_12_itm_1;
+  reg [8:0] FRAME_mul_1_itm_1;
+  wire [17:0] nl_FRAME_mul_1_itm_1;
+  reg [5:0] red_slc_red_2_sg1_itm_1;
+  reg [4:0] FRAME_acc_37_itm_1;
+  wire [5:0] nl_FRAME_acc_37_itm_1;
+  reg FRAME_slc_acc_imod_3_4_itm_1;
+  reg exit_FRAME_for_lpi_1_dfm_st_1;
+  reg exit_FRAME_for_1_sva_2_st_1;
+  reg main_stage_0_2;
+  reg [1:0] FRAME_acc_41_itm_1_sg2;
+  wire [2:0] nl_FRAME_acc_41_itm_1_sg2;
+  reg [1:0] FRAME_acc_41_itm_1_sg1;
+  reg [5:0] FRAME_acc_41_itm_3;
+  wire [6:0] nl_FRAME_acc_41_itm_3;
+  wire or_4_cse;
+  wire or_9_cse;
+  wire exit_FRAME_for_1_lpi_1_dfm_5;
+  wire [1:0] FRAME_for_1_acc_itm;
+  wire [2:0] nl_FRAME_for_1_acc_itm;
+  wire [7:0] FRAME_acc_itm;
+  wire [8:0] nl_FRAME_acc_itm;
+  wire [11:0] FRAME_acc_3_psp_sva;
+  wire [13:0] nl_FRAME_acc_3_psp_sva;
+  wire [11:0] FRAME_acc_4_psp_sva;
+  wire [13:0] nl_FRAME_acc_4_psp_sva;
+  wire exit_FRAME_for_lpi_1_dfm;
+  wire [1:0] i_7_sva;
+  wire [2:0] nl_i_7_sva;
+  wire exit_FRAME_for_1_lpi_1_dfm_4_mx0;
+  wire [89:0] regs_regs_2_lpi_1_dfm_mx0;
+  wire [89:0] regs_regs_1_sva_dfm_mx0;
+  wire [89:0] regs_regs_0_sva_dfm_mx0;
+  wire exit_FRAME_lpi_1_dfm_2_mx0;
+  wire [18:0] FRAME_p_1_sva_1;
+  wire [19:0] nl_FRAME_p_1_sva_1;
+  wire [18:0] FRAME_p_1_lpi_1_dfm;
+  wire [5:0] acc_imod_3_sva;
+  wire [7:0] nl_acc_imod_3_sva;
+  wire [9:0] FRAME_mul_sdt;
+  wire [19:0] nl_FRAME_mul_sdt;
+  wire [5:0] acc_imod_7_sva;
+  wire [7:0] nl_acc_imod_7_sva;
+  wire [5:0] acc_imod_5_sva;
+  wire [7:0] nl_acc_imod_5_sva;
+  wire [14:0] b_1_sg1_lpi_1_dfm;
+  wire [15:0] b_2_sva_1;
+  wire [16:0] nl_b_2_sva_1;
+  wire [15:0] b_0_sva_1;
+  wire [16:0] nl_b_0_sva_1;
+  wire [14:0] g_1_sg1_lpi_1_dfm;
+  wire [15:0] g_2_sva_1;
+  wire [16:0] nl_g_2_sva_1;
+  wire [15:0] g_0_sva_1;
+  wire [16:0] nl_g_0_sva_1;
+  wire [14:0] r_1_sg1_lpi_1_dfm;
+  wire [15:0] r_2_sva_1;
+  wire [16:0] nl_r_2_sva_1;
+  wire [15:0] r_0_sva_1;
+  wire [16:0] nl_r_0_sva_1;
+  wire [15:0] b_2_lpi_1_dfm;
+  wire FRAME_for_1_nor_cse;
+  wire [15:0] g_2_lpi_1_dfm;
+  wire [15:0] r_2_lpi_1_dfm;
+  wire [15:0] b_0_lpi_1_dfm;
+  wire [15:0] g_0_lpi_1_dfm;
+  wire [15:0] r_0_lpi_1_dfm;
+  wire [1:0] i_6_sva_1;
+  wire [2:0] nl_i_6_sva_1;
+  wire [1:0] i_6_lpi_1_dfm;
+  wire FRAME_for_nor_cse;
+  wire FRAME_for_and_18_seb;
+  wire [1:0] FRAME_for_acc_5_tmp;
+  wire [2:0] nl_FRAME_for_acc_5_tmp;
+  wire not_24;
+  wire [15:0] ACC2_3_acc_1_itm;
+  wire [16:0] nl_ACC2_3_acc_1_itm;
+  wire [15:0] ACC2_3_acc_3_itm;
+  wire [16:0] nl_ACC2_3_acc_3_itm;
+  wire [15:0] ACC2_3_acc_2_itm;
+  wire [16:0] nl_ACC2_3_acc_2_itm;
+  wire FRAME_for_1_or_1_itm;
+  wire FRAME_for_1_or_itm;
+  wire FRAME_for_or_4_itm;
+  wire FRAME_for_or_itm;
+  wire FRAME_for_or_5_itm;
+  wire [1:0] FRAME_for_acc_itm;
+  wire [2:0] nl_FRAME_for_acc_itm;
+
+  wire[9:0] regs_operator_23_mux_nl;
+  wire[9:0] regs_operator_17_mux_nl;
+  wire[9:0] regs_operator_22_mux_nl;
+  wire[9:0] regs_operator_16_mux_nl;
+  wire[9:0] regs_operator_21_mux_nl;
+  wire[9:0] regs_operator_15_mux_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_FRAME_acc_3_psp_sva = (conv_u2s_11_12(FRAME_mul_2_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_3_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(green_slc_green_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_18_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_5_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({green_slc_green_2_sg1_12_itm_1
+      , 3'b0 , ({{2{green_slc_green_2_sg1_12_itm_1}}, green_slc_green_2_sg1_12_itm_1})
+      , 1'b0 , green_slc_green_2_sg1_12_itm_1}));
+  assign FRAME_acc_3_psp_sva = nl_FRAME_acc_3_psp_sva[11:0];
+  assign nl_FRAME_acc_4_psp_sva = (conv_u2s_11_12(FRAME_mul_4_itm_1) + conv_s2s_10_12(conv_u2s_9_10(FRAME_mul_5_itm_1)
+      + conv_s2s_8_10(conv_u2s_6_8(blue_slc_blue_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_30_itm_1
+      + ({4'b1001 , FRAME_slc_acc_imod_7_4_itm_1}))))) + conv_u2u_11_12(signext_11_9({blue_slc_blue_2_sg1_12_itm_1
+      , 3'b0 , ({{2{blue_slc_blue_2_sg1_12_itm_1}}, blue_slc_blue_2_sg1_12_itm_1})
+      , 1'b0 , blue_slc_blue_2_sg1_12_itm_1}));
+  assign FRAME_acc_4_psp_sva = nl_FRAME_acc_4_psp_sva[11:0];
+  assign nl_FRAME_for_1_acc_itm = i_7_sva + 2'b1;
+  assign FRAME_for_1_acc_itm = nl_FRAME_for_1_acc_itm[1:0];
+  assign exit_FRAME_for_lpi_1_dfm = exit_FRAME_for_lpi_1 & not_24;
+  assign nl_i_7_sva = i_7_lpi_1 + 2'b1;
+  assign i_7_sva = nl_i_7_sva[1:0];
+  assign exit_FRAME_for_1_lpi_1_dfm_4_mx0 = MUX_s_1_2_2({(exit_FRAME_for_1_lpi_1_dfm_5
+      | (FRAME_acc_itm[7])) , exit_FRAME_for_1_lpi_1_dfm_5}, or_9_cse);
+  assign regs_regs_2_lpi_1_dfm_mx0 = MUX_v_90_2_2({regs_regs_1_sva , regs_regs_2_lpi_1_dfm},
+      and_dcpl_1);
+  assign regs_regs_1_sva_dfm_mx0 = MUX_v_90_2_2({regs_regs_0_sva , regs_regs_1_sva},
+      and_dcpl_1);
+  assign regs_regs_0_sva_dfm_mx0 = MUX_v_90_2_2({vin_rsc_mgc_in_wire_d , regs_regs_0_sva},
+      and_dcpl_1);
+  assign nl_FRAME_acc_itm = conv_u2s_7_8(FRAME_p_1_sva_1[18:12]) + 8'b10110101;
+  assign FRAME_acc_itm = nl_FRAME_acc_itm[7:0];
+  assign exit_FRAME_lpi_1_dfm_2_mx0 = MUX_s_1_2_2({(~ (FRAME_acc_itm[7])) , (exit_FRAME_lpi_1_dfm_2
+      & not_24)}, or_9_cse);
+  assign exit_FRAME_for_1_lpi_1_dfm_5 = (~ (FRAME_for_1_acc_itm[1])) & exit_FRAME_for_lpi_1_dfm;
+  assign nl_FRAME_p_1_sva_1 = FRAME_p_1_lpi_1_dfm + 19'b1;
+  assign FRAME_p_1_sva_1 = nl_FRAME_p_1_sva_1[18:0];
+  assign FRAME_p_1_lpi_1_dfm = FRAME_p_1_lpi_1 & (signext_19_1(~ exit_FRAME_1_sva));
+  assign nl_acc_imod_3_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC2_3_acc_1_itm[9:7])
+      + conv_u2u_3_4(~ (ACC2_3_acc_1_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC2_3_acc_1_itm[15])) , 1'b1 , (~ (ACC2_3_acc_1_itm[15]))}) + conv_u2u_2_4(ACC2_3_acc_1_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC2_3_acc_1_itm[3:1]) + conv_u2u_3_4(~ (ACC2_3_acc_1_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_3_sva = nl_acc_imod_3_sva[5:0];
+  assign nl_ACC2_3_acc_1_itm = ({(r_1_sg1_lpi_1_dfm + (r_2_sva_1[15:1])) , (r_2_sva_1[0])})
+      + r_0_sva_1;
+  assign ACC2_3_acc_1_itm = nl_ACC2_3_acc_1_itm[15:0];
+  assign nl_FRAME_mul_sdt = conv_u2u_2_10(ACC2_3_acc_1_itm[14:13]) * 10'b111000111;
+  assign FRAME_mul_sdt = nl_FRAME_mul_sdt[9:0];
+  assign nl_ACC2_3_acc_3_itm = ({(b_1_sg1_lpi_1_dfm + (b_2_sva_1[15:1])) , (b_2_sva_1[0])})
+      + b_0_sva_1;
+  assign ACC2_3_acc_3_itm = nl_ACC2_3_acc_3_itm[15:0];
+  assign nl_acc_imod_7_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC2_3_acc_3_itm[9:7])
+      + conv_u2u_3_4(~ (ACC2_3_acc_3_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC2_3_acc_3_itm[15])) , 1'b1 , (~ (ACC2_3_acc_3_itm[15]))}) + conv_u2u_2_4(ACC2_3_acc_3_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC2_3_acc_3_itm[3:1]) + conv_u2u_3_4(~ (ACC2_3_acc_3_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_7_sva = nl_acc_imod_7_sva[5:0];
+  assign nl_ACC2_3_acc_2_itm = ({(g_1_sg1_lpi_1_dfm + (g_2_sva_1[15:1])) , (g_2_sva_1[0])})
+      + g_0_sva_1;
+  assign ACC2_3_acc_2_itm = nl_ACC2_3_acc_2_itm[15:0];
+  assign nl_acc_imod_5_sva = (conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC2_3_acc_2_itm[9:7])
+      + conv_u2u_3_4(~ (ACC2_3_acc_2_itm[12:10]))) + conv_u2u_4_5(conv_u2u_3_4({(~
+      (ACC2_3_acc_2_itm[15])) , 1'b1 , (~ (ACC2_3_acc_2_itm[15]))}) + conv_u2u_2_4(ACC2_3_acc_2_itm[14:13])))
+      + conv_u2u_4_6(conv_u2u_3_4(ACC2_3_acc_2_itm[3:1]) + conv_u2u_3_4(~ (ACC2_3_acc_2_itm[6:4]))))
+      + 6'b101011;
+  assign acc_imod_5_sva = nl_acc_imod_5_sva[5:0];
+  assign b_1_sg1_lpi_1_dfm = b_1_sg1_lpi_1 & ({{14{not_24}}, not_24});
+  assign regs_operator_23_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[69:60]) , (regs_regs_1_sva[69:60])
+      , (regs_regs_2_lpi_1_dfm[69:60]) , 10'b0}, i_7_lpi_1);
+  assign nl_b_2_sva_1 = b_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_23_mux_nl)
+      * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_or_1_itm})));
+  assign b_2_sva_1 = nl_b_2_sva_1[15:0];
+  assign regs_operator_17_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[9:0]) , (regs_regs_1_sva[9:0])
+      , (regs_regs_2_lpi_1_dfm[9:0]) , 10'b0}, i_7_lpi_1);
+  assign nl_b_0_sva_1 = b_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_17_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_1_or_itm})));
+  assign b_0_sva_1 = nl_b_0_sva_1[15:0];
+  assign g_1_sg1_lpi_1_dfm = g_1_sg1_lpi_1 & ({{14{not_24}}, not_24});
+  assign regs_operator_22_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[79:70]) , (regs_regs_1_sva[79:70])
+      , (regs_regs_2_lpi_1_dfm[79:70]) , 10'b0}, i_7_lpi_1);
+  assign nl_g_2_sva_1 = g_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_22_mux_nl)
+      * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_or_1_itm})));
+  assign g_2_sva_1 = nl_g_2_sva_1[15:0];
+  assign regs_operator_16_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[19:10]) , (regs_regs_1_sva[19:10])
+      , (regs_regs_2_lpi_1_dfm[19:10]) , 10'b0}, i_7_lpi_1);
+  assign nl_g_0_sva_1 = g_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_16_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_1_or_itm})));
+  assign g_0_sva_1 = nl_g_0_sva_1[15:0];
+  assign r_1_sg1_lpi_1_dfm = r_1_sg1_lpi_1 & ({{14{not_24}}, not_24});
+  assign regs_operator_21_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[89:80]) , (regs_regs_1_sva[89:80])
+      , (regs_regs_2_lpi_1_dfm[89:80]) , 10'b0}, i_7_lpi_1);
+  assign nl_r_2_sva_1 = r_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(regs_operator_21_mux_nl)
+      * conv_s2s_2_11({FRAME_for_1_nor_cse , FRAME_for_1_or_1_itm})));
+  assign r_2_sva_1 = nl_r_2_sva_1[15:0];
+  assign regs_operator_15_mux_nl = MUX_v_10_4_2({(regs_regs_0_sva[29:20]) , (regs_regs_1_sva[29:20])
+      , (regs_regs_2_lpi_1_dfm[29:20]) , 10'b0}, i_7_lpi_1);
+  assign nl_r_0_sva_1 = r_0_lpi_1_dfm + conv_s2u_12_16(conv_s2u_24_12(conv_s2s_10_12(regs_operator_15_mux_nl)
+      * conv_s2s_2_12({1'b1 , FRAME_for_1_or_itm})));
+  assign r_0_sva_1 = nl_r_0_sva_1[15:0];
+  assign b_2_lpi_1_dfm = b_2_lpi_1 & ({{15{not_24}}, not_24});
+  assign FRAME_for_1_nor_cse = ~((i_7_lpi_1[1]) | (i_7_lpi_1[0]));
+  assign g_2_lpi_1_dfm = g_2_lpi_1 & ({{15{not_24}}, not_24});
+  assign r_2_lpi_1_dfm = r_2_lpi_1 & ({{15{not_24}}, not_24});
+  assign b_0_lpi_1_dfm = b_0_lpi_1 & ({{15{not_24}}, not_24});
+  assign g_0_lpi_1_dfm = g_0_lpi_1 & ({{15{not_24}}, not_24});
+  assign r_0_lpi_1_dfm = r_0_lpi_1 & ({{15{not_24}}, not_24});
+  assign nl_i_6_sva_1 = i_6_lpi_1_dfm + 2'b1;
+  assign i_6_sva_1 = nl_i_6_sva_1[1:0];
+  assign i_6_lpi_1_dfm = i_6_lpi_1 & ({{1{not_24}}, not_24});
+  assign FRAME_for_nor_cse = ~((i_6_lpi_1_dfm[1]) | (i_6_lpi_1_dfm[0]));
+  assign FRAME_for_and_18_seb = (FRAME_for_acc_5_tmp[1]) & (FRAME_for_acc_5_tmp[0]);
+  assign nl_FRAME_for_acc_5_tmp = i_6_lpi_1_dfm + 2'b11;
+  assign FRAME_for_acc_5_tmp = nl_FRAME_for_acc_5_tmp[1:0];
+  assign not_24 = ~(exit_FRAME_for_1_lpi_1_dfm_4 | exit_FRAME_1_sva);
+  assign FRAME_for_1_or_1_itm = (~((~ (i_7_lpi_1[1])) & (i_7_lpi_1[0]))) | FRAME_for_1_nor_cse;
+  assign FRAME_for_1_or_itm = (~((i_7_lpi_1[0]) & (~ (i_7_lpi_1[1])))) | FRAME_for_1_nor_cse
+      | ((i_7_lpi_1[1]) & (~ (i_7_lpi_1[0])));
+  assign FRAME_for_or_4_itm = (~((~ (i_6_lpi_1_dfm[1])) & (i_6_lpi_1_dfm[0]))) |
+      FRAME_for_nor_cse;
+  assign FRAME_for_or_itm = (~((i_6_lpi_1_dfm[0]) & (~ (i_6_lpi_1_dfm[1])))) | FRAME_for_nor_cse;
+  assign FRAME_for_or_5_itm = (FRAME_for_acc_5_tmp[1]) | (FRAME_for_acc_5_tmp[0])
+      | FRAME_for_and_18_seb;
+  assign and_dcpl_1 = ~(exit_FRAME_1_sva | exit_FRAME_for_1_lpi_1_dfm_4);
+  assign or_dcpl_2 = exit_FRAME_1_sva | exit_FRAME_for_1_lpi_1_dfm_4;
+  assign or_4_cse = or_dcpl_2 | (~ exit_FRAME_for_lpi_1);
+  assign or_9_cse = or_dcpl_2 | (~ exit_FRAME_for_lpi_1) | (FRAME_for_1_acc_itm[1]);
+  assign nl_FRAME_for_acc_itm = i_6_sva_1 + 2'b1;
+  assign FRAME_for_acc_itm = nl_FRAME_for_acc_itm[1:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      vout_rsc_mgc_out_stdreg_d <= 30'b0;
+      FRAME_acc_41_itm_1_sg2 <= 2'b0;
+      FRAME_acc_41_itm_1_sg1 <= 2'b0;
+      FRAME_acc_41_itm_3 <= 6'b0;
+      FRAME_mul_1_itm_1 <= 9'b0;
+      red_slc_red_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_37_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_3_4_itm_1 <= 1'b0;
+      FRAME_mul_4_itm_1 <= 11'b0;
+      FRAME_mul_5_itm_1 <= 9'b0;
+      blue_slc_blue_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_30_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_7_4_itm_1 <= 1'b0;
+      blue_slc_blue_2_sg1_12_itm_1 <= 1'b0;
+      FRAME_mul_2_itm_1 <= 11'b0;
+      FRAME_mul_3_itm_1 <= 9'b0;
+      green_slc_green_2_sg1_itm_1 <= 6'b0;
+      FRAME_acc_18_itm_1 <= 5'b0;
+      FRAME_slc_acc_imod_5_4_itm_1 <= 1'b0;
+      green_slc_green_2_sg1_12_itm_1 <= 1'b0;
+      exit_FRAME_for_1_sva_2_st_1 <= 1'b0;
+      exit_FRAME_for_lpi_1_dfm_st_1 <= 1'b0;
+      i_7_lpi_1 <= 2'b0;
+      exit_FRAME_for_lpi_1 <= 1'b0;
+      exit_FRAME_for_1_lpi_1_dfm_4 <= 1'b0;
+      exit_FRAME_1_sva <= 1'b1;
+      main_stage_0_2 <= 1'b0;
+      regs_regs_2_lpi_1_dfm <= 90'b0;
+      regs_regs_1_sva <= 90'b0;
+      regs_regs_0_sva <= 90'b0;
+      exit_FRAME_lpi_1_dfm_2 <= 1'b0;
+      b_1_sg1_lpi_1 <= 15'b0;
+      g_1_sg1_lpi_1 <= 15'b0;
+      r_1_sg1_lpi_1 <= 15'b0;
+      i_6_lpi_1 <= 2'b0;
+      b_2_lpi_1 <= 16'b0;
+      b_0_lpi_1 <= 16'b0;
+      g_2_lpi_1 <= 16'b0;
+      g_0_lpi_1 <= 16'b0;
+      r_2_lpi_1 <= 16'b0;
+      r_0_lpi_1 <= 16'b0;
+      FRAME_p_1_lpi_1 <= 19'b0;
+    end
+    else begin
+      if ( en ) begin
+        vout_rsc_mgc_out_stdreg_d <= MUX_v_30_2_2({({((({FRAME_acc_41_itm_1_sg2 ,
+            FRAME_acc_41_itm_1_sg1 , FRAME_acc_41_itm_3}) + (conv_u2s_9_10(FRAME_mul_1_itm_1)
+            + conv_s2s_8_10(conv_u2s_6_8(red_slc_red_2_sg1_itm_1) + conv_s2s_5_8(FRAME_acc_37_itm_1
+            + ({4'b1001 , FRAME_slc_acc_imod_3_4_itm_1}))))) | ({8'b0 , (FRAME_acc_3_psp_sva[11:10])}))
+            , (FRAME_acc_3_psp_sva[9:6]) , ((FRAME_acc_3_psp_sva[5:0]) | ({4'b0 ,
+            (FRAME_acc_4_psp_sva[11:10])})) , (FRAME_acc_4_psp_sva[9:0])}) , vout_rsc_mgc_out_stdreg_d},
+            ~(exit_FRAME_for_1_sva_2_st_1 & exit_FRAME_for_lpi_1_dfm_st_1 & main_stage_0_2));
+        FRAME_acc_41_itm_1_sg2 <= nl_FRAME_acc_41_itm_1_sg2[1:0];
+        FRAME_acc_41_itm_1_sg1 <= FRAME_mul_sdt[7:6];
+        FRAME_acc_41_itm_3 <= nl_FRAME_acc_41_itm_3[5:0];
+        FRAME_mul_1_itm_1 <= nl_FRAME_mul_1_itm_1[8:0];
+        red_slc_red_2_sg1_itm_1 <= ACC2_3_acc_1_itm[9:4];
+        FRAME_acc_37_itm_1 <= nl_FRAME_acc_37_itm_1[4:0];
+        FRAME_slc_acc_imod_3_4_itm_1 <= acc_imod_3_sva[5];
+        FRAME_mul_4_itm_1 <= nl_FRAME_mul_4_itm_1[10:0];
+        FRAME_mul_5_itm_1 <= nl_FRAME_mul_5_itm_1[8:0];
+        blue_slc_blue_2_sg1_itm_1 <= ACC2_3_acc_3_itm[9:4];
+        FRAME_acc_30_itm_1 <= nl_FRAME_acc_30_itm_1[4:0];
+        FRAME_slc_acc_imod_7_4_itm_1 <= acc_imod_7_sva[5];
+        blue_slc_blue_2_sg1_12_itm_1 <= ACC2_3_acc_3_itm[15];
+        FRAME_mul_2_itm_1 <= nl_FRAME_mul_2_itm_1[10:0];
+        FRAME_mul_3_itm_1 <= nl_FRAME_mul_3_itm_1[8:0];
+        green_slc_green_2_sg1_itm_1 <= ACC2_3_acc_2_itm[9:4];
+        FRAME_acc_18_itm_1 <= nl_FRAME_acc_18_itm_1[4:0];
+        FRAME_slc_acc_imod_5_4_itm_1 <= acc_imod_5_sva[5];
+        green_slc_green_2_sg1_12_itm_1 <= ACC2_3_acc_2_itm[15];
+        exit_FRAME_for_1_sva_2_st_1 <= ~ (FRAME_for_1_acc_itm[1]);
+        exit_FRAME_for_lpi_1_dfm_st_1 <= exit_FRAME_for_lpi_1_dfm;
+        i_7_lpi_1 <= MUX_v_2_2_2({i_7_sva , (i_7_lpi_1 & (signext_2_1(FRAME_for_acc_itm[1])))},
+            or_4_cse);
+        exit_FRAME_for_lpi_1 <= MUX_s_1_2_2({exit_FRAME_for_lpi_1_dfm , (~ (FRAME_for_acc_itm[1]))},
+            or_4_cse);
+        exit_FRAME_for_1_lpi_1_dfm_4 <= exit_FRAME_for_1_lpi_1_dfm_4_mx0;
+        exit_FRAME_1_sva <= exit_FRAME_for_1_lpi_1_dfm_4_mx0 & exit_FRAME_lpi_1_dfm_2_mx0;
+        main_stage_0_2 <= 1'b1;
+        regs_regs_2_lpi_1_dfm <= regs_regs_2_lpi_1_dfm_mx0;
+        regs_regs_1_sva <= regs_regs_1_sva_dfm_mx0;
+        regs_regs_0_sva <= regs_regs_0_sva_dfm_mx0;
+        exit_FRAME_lpi_1_dfm_2 <= exit_FRAME_lpi_1_dfm_2_mx0;
+        b_1_sg1_lpi_1 <= MUX_v_15_2_2({b_1_sg1_lpi_1_dfm , (b_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[39:30])
+            , (regs_regs_1_sva_dfm_mx0[39:30]) , (regs_regs_2_lpi_1_dfm_mx0[39:30])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_or_5_itm}))))},
+            or_4_cse);
+        g_1_sg1_lpi_1 <= MUX_v_15_2_2({g_1_sg1_lpi_1_dfm , (g_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[49:40])
+            , (regs_regs_1_sva_dfm_mx0[49:40]) , (regs_regs_2_lpi_1_dfm_mx0[49:40])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_or_5_itm}))))},
+            or_4_cse);
+        r_1_sg1_lpi_1 <= MUX_v_15_2_2({r_1_sg1_lpi_1_dfm , (r_1_sg1_lpi_1_dfm + conv_s2u_11_15(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[59:50])
+            , (regs_regs_1_sva_dfm_mx0[59:50]) , (regs_regs_2_lpi_1_dfm_mx0[59:50])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_and_18_seb , FRAME_for_or_5_itm}))))},
+            or_4_cse);
+        i_6_lpi_1 <= MUX_v_2_2_2({i_6_lpi_1_dfm , i_6_sva_1}, or_4_cse);
+        b_2_lpi_1 <= MUX_v_16_2_2({b_2_sva_1 , (b_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[69:60])
+            , (regs_regs_1_sva_dfm_mx0[69:60]) , (regs_regs_2_lpi_1_dfm_mx0[69:60])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))},
+            or_4_cse);
+        b_0_lpi_1 <= MUX_v_16_2_2({b_0_sva_1 , (b_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[9:0])
+            , (regs_regs_1_sva_dfm_mx0[9:0]) , (regs_regs_2_lpi_1_dfm_mx0[9:0]) ,
+            10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_itm}))))},
+            or_4_cse);
+        g_2_lpi_1 <= MUX_v_16_2_2({g_2_sva_1 , (g_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[79:70])
+            , (regs_regs_1_sva_dfm_mx0[79:70]) , (regs_regs_2_lpi_1_dfm_mx0[79:70])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))},
+            or_4_cse);
+        g_0_lpi_1 <= MUX_v_16_2_2({g_0_sva_1 , (g_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[19:10])
+            , (regs_regs_1_sva_dfm_mx0[19:10]) , (regs_regs_2_lpi_1_dfm_mx0[19:10])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_itm}))))},
+            or_4_cse);
+        r_2_lpi_1 <= MUX_v_16_2_2({r_2_sva_1 , (r_2_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[89:80])
+            , (regs_regs_1_sva_dfm_mx0[89:80]) , (regs_regs_2_lpi_1_dfm_mx0[89:80])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_4_itm}))))},
+            or_4_cse);
+        r_0_lpi_1 <= MUX_v_16_2_2({r_0_sva_1 , (r_0_lpi_1_dfm + conv_s2u_11_16(conv_s2u_22_11(conv_s2s_10_11(MUX_v_10_4_2({(regs_regs_0_sva_dfm_mx0[29:20])
+            , (regs_regs_1_sva_dfm_mx0[29:20]) , (regs_regs_2_lpi_1_dfm_mx0[29:20])
+            , 10'b0}, i_6_lpi_1_dfm)) * conv_s2s_2_11({FRAME_for_nor_cse , FRAME_for_or_itm}))))},
+            or_4_cse);
+        FRAME_p_1_lpi_1 <= MUX_v_19_2_2({FRAME_p_1_lpi_1_dfm , FRAME_p_1_sva_1},
+            and_dcpl_1 & exit_FRAME_for_lpi_1 & (~ (FRAME_for_1_acc_itm[1])));
+      end
+    end
+  end
+  assign nl_FRAME_acc_41_itm_1_sg2  = (FRAME_mul_sdt[9:8]) + conv_s2u_1_2(ACC2_3_acc_1_itm[15]);
+  assign nl_FRAME_acc_41_itm_3  = conv_u2u_5_6(FRAME_mul_sdt[4:0]) + conv_u2u_5_6(signext_5_3({(ACC2_3_acc_1_itm[15])
+      , 1'b0 , (ACC2_3_acc_1_itm[15])}));
+  assign nl_FRAME_mul_1_itm_1  = conv_u2u_3_9(ACC2_3_acc_1_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_37_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_3_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_3_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_3_sva[5:3])) , (~ (acc_imod_3_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_3_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC2_3_acc_1_itm[9:7]));
+  assign nl_FRAME_mul_4_itm_1  = conv_u2u_2_11(ACC2_3_acc_3_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_5_itm_1  = conv_u2u_3_9(ACC2_3_acc_3_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_30_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_7_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_7_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_7_sva[5:3])) , (~ (acc_imod_7_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_7_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC2_3_acc_3_itm[9:7]));
+  assign nl_FRAME_mul_2_itm_1  = conv_u2u_2_11(ACC2_3_acc_2_itm[14:13]) * 11'b111000111;
+  assign nl_FRAME_mul_3_itm_1  = conv_u2u_3_9(ACC2_3_acc_2_itm[12:10]) * 9'b111001;
+  assign nl_FRAME_acc_18_itm_1  = conv_u2u_4_5(conv_u2u_3_4({(~ (acc_imod_5_sva[5]))
+      , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_5_sva[2:0]) , 1'b1}) + conv_u2s_4_5({(~
+      (acc_imod_5_sva[5:3])) , (~ (acc_imod_5_sva[5]))})))))}) + conv_u2u_2_4(acc_imod_5_sva[4:3]))
+      + conv_u2u_3_5(~ (ACC2_3_acc_2_itm[9:7]));
+
+  function [10:0] signext_11_9;
+    input [8:0] vector;
+  begin
+    signext_11_9= {{2{vector[8]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] MUX_s_1_2_2;
+    input [1:0] inputs;
+    input [0:0] sel;
+    reg [0:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[1:1];
+      end
+      1'b1 : begin
+        result = inputs[0:0];
+      end
+      default : begin
+        result = inputs[1:1];
+      end
+    endcase
+    MUX_s_1_2_2 = result;
+  end
+  endfunction
+
+
+  function [89:0] MUX_v_90_2_2;
+    input [179:0] inputs;
+    input [0:0] sel;
+    reg [89:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[179:90];
+      end
+      1'b1 : begin
+        result = inputs[89:0];
+      end
+      default : begin
+        result = inputs[179:90];
+      end
+    endcase
+    MUX_v_90_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] signext_19_1;
+    input [0:0] vector;
+  begin
+    signext_19_1= {{18{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [9:0] MUX_v_10_4_2;
+    input [39:0] inputs;
+    input [1:0] sel;
+    reg [9:0] result;
+  begin
+    case (sel)
+      2'b00 : begin
+        result = inputs[39:30];
+      end
+      2'b01 : begin
+        result = inputs[29:20];
+      end
+      2'b10 : begin
+        result = inputs[19:10];
+      end
+      2'b11 : begin
+        result = inputs[9:0];
+      end
+      default : begin
+        result = inputs[39:30];
+      end
+    endcase
+    MUX_v_10_4_2 = result;
+  end
+  endfunction
+
+
+  function [29:0] MUX_v_30_2_2;
+    input [59:0] inputs;
+    input [0:0] sel;
+    reg [29:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[59:30];
+      end
+      1'b1 : begin
+        result = inputs[29:0];
+      end
+      default : begin
+        result = inputs[59:30];
+      end
+    endcase
+    MUX_v_30_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] MUX_v_2_2_2;
+    input [3:0] inputs;
+    input [0:0] sel;
+    reg [1:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[3:2];
+      end
+      1'b1 : begin
+        result = inputs[1:0];
+      end
+      default : begin
+        result = inputs[3:2];
+      end
+    endcase
+    MUX_v_2_2_2 = result;
+  end
+  endfunction
+
+
+  function [1:0] signext_2_1;
+    input [0:0] vector;
+  begin
+    signext_2_1= {{1{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [14:0] MUX_v_15_2_2;
+    input [29:0] inputs;
+    input [0:0] sel;
+    reg [14:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[29:15];
+      end
+      1'b1 : begin
+        result = inputs[14:0];
+      end
+      default : begin
+        result = inputs[29:15];
+      end
+    endcase
+    MUX_v_15_2_2 = result;
+  end
+  endfunction
+
+
+  function [15:0] MUX_v_16_2_2;
+    input [31:0] inputs;
+    input [0:0] sel;
+    reg [15:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[31:16];
+      end
+      1'b1 : begin
+        result = inputs[15:0];
+      end
+      default : begin
+        result = inputs[31:16];
+      end
+    endcase
+    MUX_v_16_2_2 = result;
+  end
+  endfunction
+
+
+  function [18:0] MUX_v_19_2_2;
+    input [37:0] inputs;
+    input [0:0] sel;
+    reg [18:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[37:19];
+      end
+      1'b1 : begin
+        result = inputs[18:0];
+      end
+      default : begin
+        result = inputs[37:19];
+      end
+    endcase
+    MUX_v_19_2_2 = result;
+  end
+  endfunction
+
+
+  function [4:0] signext_5_3;
+    input [2:0] vector;
+  begin
+    signext_5_3= {{2{vector[2]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_u2s_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2s_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_9_10 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_10 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_7_8 ;
+    input [6:0]  vector ;
+  begin
+    conv_u2s_7_8 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2u_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [5:0] conv_u2u_4_6 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_6 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_11_16 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_16 = {{5{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_s2u_22_11 ;
+    input signed [21:0]  vector ;
+  begin
+    conv_s2u_22_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_10_11 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_11 = {vector[9], vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_s2s_2_11 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_11 = {{9{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [15:0] conv_s2u_12_16 ;
+    input signed [11:0]  vector ;
+  begin
+    conv_s2u_12_16 = {{4{vector[11]}}, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_24_12 ;
+    input signed [23:0]  vector ;
+  begin
+    conv_s2u_24_12 = vector[11:0];
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_2_12 ;
+    input signed [1:0]  vector ;
+  begin
+    conv_s2s_2_12 = {{10{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [14:0] conv_s2u_11_15 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_15 = {{4{vector[10]}}, vector};
+  end
+  endfunction
+
+
+  function  [1:0] conv_s2u_1_2 ;
+    input signed [0:0]  vector ;
+  begin
+    conv_s2u_1_2 = {vector[0], vector};
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_2_11 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_11 = {{9{1'b0}}, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    sobel
+//  Generated from file(s):
+//    7) $PROJECT_HOME/sobel.cpp
+// ------------------------------------------------------------------
+
+
+module sobel (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  sobel_core sobel_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/Sobel/sobel.v9/rtl.v.psr b/Sobel/sobel.v9/rtl.v.psr
new file mode 100644
index 0000000..1e55f8c
--- /dev/null
+++ b/Sobel/sobel.v9/rtl.v.psr
@@ -0,0 +1,289 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v9/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v9/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v9/rtl.v}} -format verilog
+   setup_design -design=sobel
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'sobel': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'sobel': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'sobel'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'sobel'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to vout_rsc_z(29:0)
+   report_timing -from en -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from vin_rsc_z(89:0) -to vout_rsc_z(29:0)
+   report_timing -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 vin_rsc_z(89:0)
+      report_timing -from vin_rsc_z(89:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock clk] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 vout_rsc_z(29:0)
+      report_timing -from [all_registers -clock en] -to vout_rsc_z(29:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'sobel'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'sobel'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v9 mapped.v]
+          puts "-- Writing mapped netlist for 'sobel' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v9 gate.v]
+          set gate_sdf [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v9 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/Sobel/sobel.v9/rtl.v.psr_timing b/Sobel/sobel.v9/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/Sobel/sobel.v9/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/Sobel/sobel.v9/rtl.v_order.txt b/Sobel/sobel.v9/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/Sobel/sobel.v9/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/Sobel/sobel.v9/rtl_mgc_ioport.v b/Sobel/sobel.v9/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/Sobel/sobel.v9/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/Sobel/sobel.v9/rtl_mgc_ioport_v2001.v b/Sobel/sobel.v9/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/Sobel/sobel.v9/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/Sobel/sobel.v9/schedule.gnt b/Sobel/sobel.v9/schedule.gnt
new file mode 100644
index 0000000..2a37dce
--- /dev/null
+++ b/Sobel/sobel.v9/schedule.gnt
@@ -0,0 +1,501 @@
+set a(0-5987) {NAME i:asn(i#7.lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37692 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-5988) {NAME FRAME:for:asn(exit:FRAME:for.lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37693 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-5989) {NAME i:asn(i#6.lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37694 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-5990) {NAME regs.regs:asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37695 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-5991) {NAME r:asn(r(2).lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37696 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-5992) {NAME r:asn(r(0).lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37697 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-5993) {NAME r:asn(r(1).sg1.lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37698 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-5994) {NAME g:asn(g(2).lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37699 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-5995) {NAME g:asn(g(0).lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37700 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-5996) {NAME g:asn(g(1).sg1.lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37701 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-5997) {NAME b:asn(b(2).lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37702 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-5998) {NAME b:asn(b(0).lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37703 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-5999) {NAME b:asn(b(1).sg1.lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37704 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-6000) {NAME FRAME:asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37705 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-6001) {NAME FRAME:for#1:asn(exit:FRAME:for#1.lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37706 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-6002) {NAME FRAME:p:asn(FRAME:p#1.lpi#1) TYPE ASSIGN PAR 0-5986 XREFS 37707 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-6003) {NAME asn(regs.regs(1))#1 TYPE ASSIGN PAR 0-5986 XREFS 37708 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-6004) {NAME asn(regs.regs(0))#1 TYPE ASSIGN PAR 0-5986 XREFS 37709 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{258 0 0-6006 {}}} CYCLES {}}
+set a(0-6005) {NAME asn(exit:FRAME#1)#2 TYPE ASSIGN PAR 0-5986 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{772 0 0-6006 {}}} SUCCS {{259 0 0-6006 {}}} CYCLES {}}
+set a(0-6007) {NAME FRAME:for:asn(i#7.lpi#1.dfm) TYPE ASSIGN PAR 0-6006 XREFS 37710 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 2 0.619485875} PREDS {} SUCCS {{258 0 0-6472 {}}} CYCLES {}}
+set a(0-6008) {NAME FRAME:for:asn(exit:FRAME:for.sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37711 LOC {0 1.0 1 0.9605326249999999 1 0.9605326249999999 2 0.619485875} PREDS {} SUCCS {{258 0 0-6478 {}}} CYCLES {}}
+set a(0-6009) {NAME i:asn(i#6.sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37712 LOC {0 1.0 1 0.9129764499999999 1 0.9129764499999999 3 0.457609925} PREDS {} SUCCS {{258 0 0-6471 {}}} CYCLES {}}
+set a(0-6010) {NAME b:asn(b(2).sva#2) TYPE ASSIGN PAR 0-6006 XREFS 37713 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 2 0.854530825} PREDS {} SUCCS {{258 0 0-6468 {}}} CYCLES {}}
+set a(0-6011) {NAME g:asn(g(2).sva#2) TYPE ASSIGN PAR 0-6006 XREFS 37714 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 2 0.854530825} PREDS {} SUCCS {{258 0 0-6466 {}}} CYCLES {}}
+set a(0-6012) {NAME r:asn(r(2).sva#2) TYPE ASSIGN PAR 0-6006 XREFS 37715 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 2 0.9769393999999999} PREDS {} SUCCS {{258 0 0-6464 {}}} CYCLES {}}
+set a(0-6013) {NAME b:asn(b(1).sg1.sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37716 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 3 0.015707075} PREDS {} SUCCS {{258 0 0-6475 {}}} CYCLES {}}
+set a(0-6014) {NAME g:asn(g(1).sg1.sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37717 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 3 0.015707075} PREDS {} SUCCS {{258 0 0-6474 {}}} CYCLES {}}
+set a(0-6015) {NAME r:asn(r(1).sg1.sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37718 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 3 0.099592} PREDS {} SUCCS {{258 0 0-6473 {}}} CYCLES {}}
+set a(0-6016) {NAME b:asn(b(0).sva#2) TYPE ASSIGN PAR 0-6006 XREFS 37719 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 3 0.015315049999999998} PREDS {} SUCCS {{258 0 0-6467 {}}} CYCLES {}}
+set a(0-6017) {NAME g:asn(g(0).sva#2) TYPE ASSIGN PAR 0-6006 XREFS 37720 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 3 0.015315049999999998} PREDS {} SUCCS {{258 0 0-6465 {}}} CYCLES {}}
+set a(0-6018) {NAME r:asn(r(0).sva#2) TYPE ASSIGN PAR 0-6006 XREFS 37721 LOC {0 1.0 1 0.9769393999999999 1 0.9769393999999999 3 0.099199975} PREDS {} SUCCS {{258 0 0-6463 {}}} CYCLES {}}
+set a(0-6019) {NAME FRAME:asn(exit:FRAME.sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37722 LOC {0 1.0 1 0.9308181999999999 1 0.9308181999999999 2 0.550304075} PREDS {} SUCCS {{258 0 0-6454 {}}} CYCLES {}}
+set a(0-6020) {NAME FRAME:p:asn(FRAME:p#1.sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37723 LOC {0 1.0 1 0.858003 1 0.858003 3 0.318762125} PREDS {} SUCCS {{258 0 0-6470 {}}} CYCLES {}}
+set a(0-6021) {NAME FRAME:for#1:asn(exit:FRAME:for#1.sva#2) TYPE ASSIGN PAR 0-6006 XREFS 37724 LOC {0 1.0 1 0.4061093 1 0.4061093 2 0.550304075} PREDS {} SUCCS {{258 0 0-6454 {}} {258 0 0-6456 {}} {258 0 0-6469 {}}} CYCLES {}}
+set a(0-6022) {NAME i:asn(i#7.sva) TYPE ASSIGN PAR 0-6006 XREFS 37725 LOC {0 1.0 1 0.358553125 1 0.358553125 2 0.619485875} PREDS {} SUCCS {{258 0 0-6472 {}}} CYCLES {}}
+set a(0-6023) {NAME b:asn(b(2).sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37726 LOC {0 1.0 1 0.4061093 1 0.4061093 2 0.854530825} PREDS {} SUCCS {{258 0 0-6468 {}}} CYCLES {}}
+set a(0-6024) {NAME g:asn(g(2).sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37727 LOC {0 1.0 1 0.4061093 1 0.4061093 2 0.854530825} PREDS {} SUCCS {{258 0 0-6466 {}}} CYCLES {}}
+set a(0-6025) {NAME r:asn(r(2).sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37728 LOC {0 1.0 1 0.4061093 1 0.4061093 2 0.9769393999999999} PREDS {} SUCCS {{258 0 0-6464 {}}} CYCLES {}}
+set a(0-6026) {NAME b:asn(b(0).sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37729 LOC {0 1.0 1 0.511719075 1 0.511719075 3 0.015315049999999998} PREDS {} SUCCS {{258 0 0-6467 {}}} CYCLES {}}
+set a(0-6027) {NAME g:asn(g(0).sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37730 LOC {0 1.0 1 0.511719075 1 0.511719075 3 0.015315049999999998} PREDS {} SUCCS {{258 0 0-6465 {}}} CYCLES {}}
+set a(0-6028) {NAME r:asn(r(0).sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37731 LOC {0 1.0 1 0.511719075 1 0.511719075 3 0.099199975} PREDS {} SUCCS {{258 0 0-6463 {}}} CYCLES {}}
+set a(0-6029) {NAME regs.regs:asn(regs.regs(0).sva#1) TYPE ASSIGN PAR 0-6006 XREFS 37732 LOC {0 1.0 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {} SUCCS {{258 0 0-6041 {}}} CYCLES {}}
+set a(0-6030) {NAME asn#175 TYPE ASSIGN PAR 0-6006 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-6480 {}}} SUCCS {{259 0 0-6031 {}} {256 0 0-6480 {}}} CYCLES {}}
+set a(0-6031) {NAME select TYPE SELECT PAR 0-6006 LOC {0 1.0 0 1.0 0 1.0 3 1.0} PREDS {{259 0 0-6030 {}}} SUCCS {} CYCLES {}}
+set a(0-6032) {NAME FRAME:asn TYPE ASSIGN PAR 0-6006 XREFS 37733 LOC {0 1.0 1 0.7223368499999999 1 0.7223368499999999 2 0.341822725} PREDS {{262 0 0-6480 {}}} SUCCS {{259 0 0-6033 {}} {256 0 0-6480 {}}} CYCLES {}}
+set a(0-6033) {NAME FRAME:not#28 TYPE NOT PAR 0-6006 XREFS 37734 LOC {1 0.0 1 0.7223368499999999 1 0.7223368499999999 2 0.341822725} PREDS {{259 0 0-6032 {}}} SUCCS {{259 0 0-6034 {}}} CYCLES {}}
+set a(0-6034) {NAME exs TYPE SIGNEXTEND PAR 0-6006 LOC {1 0.0 1 0.7223368499999999 1 0.7223368499999999 2 0.341822725} PREDS {{259 0 0-6033 {}}} SUCCS {{259 0 0-6035 {}}} CYCLES {}}
+set a(0-6035) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(19,2) AREA_SCORE 13.87 QUANTITY 1 NAME and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 LOC {1 0.0 1 0.7223368499999999 1 0.7223368499999999 1 0.7387435812638539 2 0.3582294562638539} PREDS {{262 0 0-6470 {}} {259 0 0-6034 {}}} SUCCS {{258 0 0-6345 {}} {258 0 0-6470 {}}} CYCLES {}}
+set a(0-6036) {NAME asn#176 TYPE ASSIGN PAR 0-6006 LOC {0 1.0 1 0.0 1 0.0 1 0.619485875} PREDS {{262 0 0-6480 {}}} SUCCS {{259 0 0-6037 {}} {256 0 0-6480 {}}} CYCLES {}}
+set a(0-6037) {NAME or TYPE OR PAR 0-6006 LOC {1 0.0 1 0.0 1 0.0 1 0.619485875} PREDS {{262 0 0-6477 {}} {259 0 0-6036 {}}} SUCCS {{259 0 0-6038 {}} {258 0 0-6041 {}} {258 0 0-6044 {}} {258 0 0-6046 {}} {258 0 0-6047 {}} {258 0 0-6050 {}} {258 0 0-6053 {}} {258 0 0-6056 {}} {258 0 0-6059 {}} {258 0 0-6062 {}} {258 0 0-6065 {}} {258 0 0-6068 {}} {258 0 0-6071 {}} {258 0 0-6074 {}} {258 0 0-6077 {}} {258 0 0-6079 {}} {256 0 0-6477 {}}} CYCLES {}}
+set a(0-6038) {NAME FRAME:for:select TYPE SELECT PAR 0-6006 XREFS 37735 LOC {1 0.0 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {{259 0 0-6037 {}}} SUCCS {{146 0 0-6039 {}}} CYCLES {}}
+set a(0-6039) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,90) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_read(vin:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-6006 XREFS 37736 LOC {1 0.0 1 0.025595174999999998 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {{146 0 0-6038 {}}} SUCCS {{258 0 0-6041 {}}} CYCLES {}}
+set a(0-6040) {NAME FRAME:for:asn TYPE ASSIGN PAR 0-6006 XREFS 37737 LOC {0 1.0 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {{262 0 0-6460 {}}} SUCCS {{259 0 0-6041 {}} {256 0 0-6460 {}}} CYCLES {}}
+set a(0-6041) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 37738 LOC {1 0.0 1 0.025595174999999998 1 0.025595174999999998 1 0.0486557375 1 0.6425464375} PREDS {{258 0 0-6037 {}} {258 0 0-6039 {}} {258 0 0-6029 {}} {259 0 0-6040 {}}} SUCCS {{258 0 0-6097 {}} {258 0 0-6104 {}} {258 0 0-6111 {}} {258 0 0-6135 {}} {258 0 0-6141 {}} {258 0 0-6147 {}} {258 0 0-6365 {}} {258 0 0-6371 {}} {258 0 0-6377 {}} {258 0 0-6394 {}} {258 0 0-6400 {}} {258 0 0-6406 {}} {258 0 0-6429 {}} {258 0 0-6435 {}} {258 0 0-6441 {}} {258 0 0-6460 {}}} CYCLES {}}
+set a(0-6042) {NAME FRAME:for:asn#10 TYPE ASSIGN PAR 0-6006 XREFS 37739 LOC {0 1.0 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {{262 0 0-6460 {}}} SUCCS {{258 0 0-6044 {}} {256 0 0-6460 {}}} CYCLES {}}
+set a(0-6043) {NAME FRAME:for:asn#11 TYPE ASSIGN PAR 0-6006 XREFS 37740 LOC {0 1.0 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {{262 0 0-6461 {}}} SUCCS {{259 0 0-6044 {}} {256 0 0-6461 {}}} CYCLES {}}
+set a(0-6044) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#1 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 37741 LOC {1 0.0 1 0.025595174999999998 1 0.025595174999999998 1 0.0486557375 1 0.6425464375} PREDS {{258 0 0-6037 {}} {258 0 0-6042 {}} {259 0 0-6043 {}}} SUCCS {{258 0 0-6096 {}} {258 0 0-6103 {}} {258 0 0-6110 {}} {258 0 0-6134 {}} {258 0 0-6140 {}} {258 0 0-6146 {}} {258 0 0-6364 {}} {258 0 0-6370 {}} {258 0 0-6376 {}} {258 0 0-6393 {}} {258 0 0-6399 {}} {258 0 0-6405 {}} {258 0 0-6428 {}} {258 0 0-6434 {}} {258 0 0-6440 {}} {258 0 0-6461 {}}} CYCLES {}}
+set a(0-6045) {NAME FRAME:for:asn#12 TYPE ASSIGN PAR 0-6006 XREFS 37742 LOC {0 1.0 1 0.025595174999999998 1 0.025595174999999998 1 0.619485875} PREDS {{262 0 0-6461 {}}} SUCCS {{259 0 0-6046 {}} {256 0 0-6461 {}}} CYCLES {}}
+set a(0-6046) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(90,1,2) AREA_SCORE 82.75 QUANTITY 3 NAME FRAME:for:mux#2 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 37743 LOC {1 0.0 1 0.025595174999999998 1 0.025595174999999998 1 0.0486557375 1 0.6425464375} PREDS {{258 0 0-6037 {}} {262 0 0-6462 {}} {259 0 0-6045 {}}} SUCCS {{258 0 0-6095 {}} {258 0 0-6102 {}} {258 0 0-6109 {}} {258 0 0-6133 {}} {258 0 0-6139 {}} {258 0 0-6145 {}} {258 0 0-6363 {}} {258 0 0-6369 {}} {258 0 0-6375 {}} {258 0 0-6392 {}} {258 0 0-6398 {}} {258 0 0-6404 {}} {258 0 0-6427 {}} {258 0 0-6433 {}} {258 0 0-6439 {}} {258 0 0-6462 {}}} CYCLES {}}
+set a(0-6047) {NAME not#12 TYPE NOT PAR 0-6006 XREFS 37744 LOC {1 0.0 1 0.3893105 1 0.3893105 2 0.122260575} PREDS {{258 0 0-6037 {}}} SUCCS {{259 0 0-6048 {}}} CYCLES {}}
+set a(0-6048) {NAME FRAME:for:exs TYPE SIGNEXTEND PAR 0-6006 XREFS 37745 LOC {1 0.0 1 0.3893105 1 0.3893105 2 0.122260575} PREDS {{259 0 0-6047 {}}} SUCCS {{259 0 0-6049 {}}} CYCLES {}}
+set a(0-6049) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(16,2) AREA_SCORE 11.68 QUANTITY 6 NAME FRAME:for:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 37746 LOC {1 0.0 1 0.3893105 1 0.3893105 1 0.4057172312638539 2 0.1386673062638539} PREDS {{262 0 0-6463 {}} {259 0 0-6048 {}}} SUCCS {{258 0 0-6101 {}} {258 0 0-6368 {}} {256 0 0-6463 {}}} CYCLES {}}
+set a(0-6050) {NAME not#13 TYPE NOT PAR 0-6006 XREFS 37747 LOC {1 0.0 1 0.283700725 1 0.283700725 2 0.0166508} PREDS {{258 0 0-6037 {}}} SUCCS {{259 0 0-6051 {}}} CYCLES {}}
+set a(0-6051) {NAME FRAME:for:exs#21 TYPE SIGNEXTEND PAR 0-6006 XREFS 37748 LOC {1 0.0 1 0.283700725 1 0.283700725 2 0.0166508} PREDS {{259 0 0-6050 {}}} SUCCS {{259 0 0-6052 {}}} CYCLES {}}
+set a(0-6052) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(16,2) AREA_SCORE 11.68 QUANTITY 6 NAME FRAME:for:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 37749 LOC {1 0.0 1 0.283700725 1 0.283700725 1 0.3001074562638539 2 0.03305753126385391} PREDS {{262 0 0-6464 {}} {259 0 0-6051 {}}} SUCCS {{258 0 0-6138 {}} {258 0 0-6432 {}} {256 0 0-6464 {}}} CYCLES {}}
+set a(0-6053) {NAME not#14 TYPE NOT PAR 0-6006 XREFS 37750 LOC {1 0.0 1 0.3893105 1 0.3893105 2 0.03837565} PREDS {{258 0 0-6037 {}}} SUCCS {{259 0 0-6054 {}}} CYCLES {}}
+set a(0-6054) {NAME FRAME:for:exs#22 TYPE SIGNEXTEND PAR 0-6006 XREFS 37751 LOC {1 0.0 1 0.3893105 1 0.3893105 2 0.03837565} PREDS {{259 0 0-6053 {}}} SUCCS {{259 0 0-6055 {}}} CYCLES {}}
+set a(0-6055) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(16,2) AREA_SCORE 11.68 QUANTITY 6 NAME FRAME:for:and#2 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 37752 LOC {1 0.0 1 0.3893105 1 0.3893105 1 0.4057172312638539 2 0.0547823812638539} PREDS {{262 0 0-6465 {}} {259 0 0-6054 {}}} SUCCS {{258 0 0-6108 {}} {258 0 0-6374 {}} {256 0 0-6465 {}}} CYCLES {}}
+set a(0-6056) {NAME not#15 TYPE NOT PAR 0-6006 XREFS 37753 LOC {1 0.0 1 0.283700725 1 0.283700725 1 0.877591425} PREDS {{258 0 0-6037 {}}} SUCCS {{259 0 0-6057 {}}} CYCLES {}}
+set a(0-6057) {NAME FRAME:for:exs#23 TYPE SIGNEXTEND PAR 0-6006 XREFS 37754 LOC {1 0.0 1 0.283700725 1 0.283700725 1 0.877591425} PREDS {{259 0 0-6056 {}}} SUCCS {{259 0 0-6058 {}}} CYCLES {}}
+set a(0-6058) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(16,2) AREA_SCORE 11.68 QUANTITY 6 NAME FRAME:for:and#3 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 37755 LOC {1 0.0 1 0.283700725 1 0.283700725 1 0.3001074562638539 1 0.8939981562638539} PREDS {{262 0 0-6466 {}} {259 0 0-6057 {}}} SUCCS {{258 0 0-6144 {}} {258 0 0-6438 {}} {256 0 0-6466 {}}} CYCLES {}}
+set a(0-6059) {NAME not#16 TYPE NOT PAR 0-6006 XREFS 37756 LOC {1 0.0 1 0.3893105 1 0.3893105 2 0.03837565} PREDS {{258 0 0-6037 {}}} SUCCS {{259 0 0-6060 {}}} CYCLES {}}
+set a(0-6060) {NAME FRAME:for:exs#24 TYPE SIGNEXTEND PAR 0-6006 XREFS 37757 LOC {1 0.0 1 0.3893105 1 0.3893105 2 0.03837565} PREDS {{259 0 0-6059 {}}} SUCCS {{259 0 0-6061 {}}} CYCLES {}}
+set a(0-6061) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(16,2) AREA_SCORE 11.68 QUANTITY 6 NAME FRAME:for:and#4 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 37758 LOC {1 0.0 1 0.3893105 1 0.3893105 1 0.4057172312638539 2 0.0547823812638539} PREDS {{262 0 0-6467 {}} {259 0 0-6060 {}}} SUCCS {{258 0 0-6115 {}} {258 0 0-6380 {}} {256 0 0-6467 {}}} CYCLES {}}
+set a(0-6062) {NAME not#17 TYPE NOT PAR 0-6006 XREFS 37759 LOC {1 0.0 1 0.283700725 1 0.283700725 1 0.877591425} PREDS {{258 0 0-6037 {}}} SUCCS {{259 0 0-6063 {}}} CYCLES {}}
+set a(0-6063) {NAME FRAME:for:exs#25 TYPE SIGNEXTEND PAR 0-6006 XREFS 37760 LOC {1 0.0 1 0.283700725 1 0.283700725 1 0.877591425} PREDS {{259 0 0-6062 {}}} SUCCS {{259 0 0-6064 {}}} CYCLES {}}
+set a(0-6064) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(16,2) AREA_SCORE 11.68 QUANTITY 6 NAME FRAME:for:and#5 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 37761 LOC {1 0.0 1 0.283700725 1 0.283700725 1 0.3001074562638539 1 0.8939981562638539} PREDS {{262 0 0-6468 {}} {259 0 0-6063 {}}} SUCCS {{258 0 0-6150 {}} {258 0 0-6444 {}} {256 0 0-6468 {}}} CYCLES {}}
+set a(0-6065) {NAME not#18 TYPE NOT PAR 0-6006 XREFS 37762 LOC {1 0.0 1 0.591272 1 0.591272 2 0.48067052499999996} PREDS {{258 0 0-6037 {}}} SUCCS {{259 0 0-6066 {}}} CYCLES {}}
+set a(0-6066) {NAME FRAME:for:exs#26 TYPE SIGNEXTEND PAR 0-6006 XREFS 37763 LOC {1 0.0 1 0.591272 1 0.591272 2 0.48067052499999996} PREDS {{259 0 0-6065 {}}} SUCCS {{259 0 0-6067 {}}} CYCLES {}}
+set a(0-6067) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 6 NAME FRAME:for:and#6 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 37764 LOC {1 0.0 1 0.591272 1 0.591272 1 0.607678731263854 2 0.49707725626385385} PREDS {{262 0 0-6471 {}} {259 0 0-6066 {}}} SUCCS {{258 0 0-6350 {}} {258 0 0-6351 {}} {258 0 0-6352 {}} {258 0 0-6353 {}} {258 0 0-6354 {}} {258 0 0-6359 {}} {258 0 0-6366 {}} {258 0 0-6372 {}} {258 0 0-6378 {}} {258 0 0-6381 {}} {258 0 0-6395 {}} {258 0 0-6401 {}} {258 0 0-6407 {}} {258 0 0-6410 {}} {258 0 0-6412 {}} {258 0 0-6430 {}} {258 0 0-6436 {}} {258 0 0-6442 {}} {258 0 0-6445 {}} {258 0 0-6471 {}}} CYCLES {}}
+set a(0-6068) {NAME not#19 TYPE NOT PAR 0-6006 XREFS 37765 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 2 0.1226526} PREDS {{258 0 0-6037 {}}} SUCCS {{259 0 0-6069 {}}} CYCLES {}}
+set a(0-6069) {NAME FRAME:for:exs#27 TYPE SIGNEXTEND PAR 0-6006 XREFS 37766 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 2 0.1226526} PREDS {{259 0 0-6068 {}}} SUCCS {{259 0 0-6070 {}}} CYCLES {}}
+set a(0-6070) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(15,2) AREA_SCORE 10.95 QUANTITY 3 NAME FRAME:for:and#7 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 37767 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 1 0.40610925626385386 2 0.13905933126385392} PREDS {{262 0 0-6473 {}} {259 0 0-6069 {}}} SUCCS {{258 0 0-6158 {}} {258 0 0-6397 {}} {258 0 0-6473 {}}} CYCLES {}}
+set a(0-6071) {NAME not#20 TYPE NOT PAR 0-6006 XREFS 37768 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 2 0.038767675} PREDS {{258 0 0-6037 {}}} SUCCS {{259 0 0-6072 {}}} CYCLES {}}
+set a(0-6072) {NAME FRAME:for:exs#28 TYPE SIGNEXTEND PAR 0-6006 XREFS 37769 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 2 0.038767675} PREDS {{259 0 0-6071 {}}} SUCCS {{259 0 0-6073 {}}} CYCLES {}}
+set a(0-6073) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(15,2) AREA_SCORE 10.95 QUANTITY 3 NAME FRAME:for:and#8 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 37770 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 1 0.40610925626385386 2 0.055174406263853906} PREDS {{262 0 0-6474 {}} {259 0 0-6072 {}}} SUCCS {{258 0 0-6162 {}} {258 0 0-6403 {}} {258 0 0-6474 {}}} CYCLES {}}
+set a(0-6074) {NAME not#21 TYPE NOT PAR 0-6006 XREFS 37771 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 2 0.038767675} PREDS {{258 0 0-6037 {}}} SUCCS {{259 0 0-6075 {}}} CYCLES {}}
+set a(0-6075) {NAME FRAME:for:exs#29 TYPE SIGNEXTEND PAR 0-6006 XREFS 37772 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 2 0.038767675} PREDS {{259 0 0-6074 {}}} SUCCS {{259 0 0-6076 {}}} CYCLES {}}
+set a(0-6076) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(15,2) AREA_SCORE 10.95 QUANTITY 3 NAME FRAME:for:and#9 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 37773 LOC {1 0.0 1 0.38970252499999997 1 0.38970252499999997 1 0.40610925626385386 2 0.055174406263853906} PREDS {{262 0 0-6475 {}} {259 0 0-6075 {}}} SUCCS {{258 0 0-6166 {}} {258 0 0-6409 {}} {258 0 0-6475 {}}} CYCLES {}}
+set a(0-6077) {NAME not#22 TYPE NOT PAR 0-6006 XREFS 37774 LOC {1 0.0 1 0.0 1 0.0 2 0.550304075} PREDS {{258 0 0-6037 {}}} SUCCS {{259 0 0-6078 {}}} CYCLES {}}
+set a(0-6078) {NAME FRAME:for:and#10 TYPE AND PAR 0-6006 XREFS 37775 LOC {1 0.0 1 0.0 1 0.0 2 0.550304075} PREDS {{262 0 0-6476 {}} {259 0 0-6077 {}}} SUCCS {{258 0 0-6454 {}} {258 0 0-6455 {}} {256 0 0-6476 {}}} CYCLES {}}
+set a(0-6079) {NAME not#1 TYPE NOT PAR 0-6006 XREFS 37776 LOC {1 0.0 1 0.0 1 0.0 1 0.642546475} PREDS {{258 0 0-6037 {}}} SUCCS {{259 0 0-6080 {}}} CYCLES {}}
+set a(0-6080) {NAME FRAME:for:and#12 TYPE AND PAR 0-6006 XREFS 37777 LOC {1 0.0 1 0.0 1 0.0 1 0.642546475} PREDS {{262 0 0-6478 {}} {259 0 0-6079 {}}} SUCCS {{259 0 0-6081 {}} {258 0 0-6455 {}} {258 0 0-6456 {}} {258 0 0-6463 {}} {258 0 0-6464 {}} {258 0 0-6465 {}} {258 0 0-6466 {}} {258 0 0-6467 {}} {258 0 0-6468 {}} {258 0 0-6469 {}} {258 0 0-6471 {}} {258 0 0-6472 {}} {258 0 0-6473 {}} {258 0 0-6474 {}} {258 0 0-6475 {}} {258 0 0-6478 {}}} CYCLES {}}
+set a(0-6081) {NAME FRAME:for:select#1 TYPE SELECT PAR 0-6006 XREFS 37778 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{259 0 0-6080 {}}} SUCCS {{146 0 0-6082 {}} {146 0 0-6083 {}} {146 0 0-6084 {}} {146 0 0-6085 {}} {146 0 0-6086 {}} {146 0 0-6087 {}} {146 0 0-6088 {}} {146 0 0-6089 {}} {146 0 0-6090 {}} {146 0 0-6091 {}} {146 0 0-6092 {}} {146 0 0-6093 {}} {146 0 0-6094 {}} {146 0 0-6095 {}} {146 0 0-6096 {}} {146 0 0-6097 {}} {146 0 0-6098 {}} {146 0 0-6099 {}} {146 0 0-6100 {}} {146 0 0-6101 {}} {146 0 0-6102 {}} {146 0 0-6103 {}} {146 0 0-6104 {}} {146 0 0-6105 {}} {146 0 0-6106 {}} {146 0 0-6107 {}} {146 0 0-6108 {}} {146 0 0-6109 {}} {146 0 0-6110 {}} {146 0 0-6111 {}} {146 0 0-6112 {}} {146 0 0-6113 {}} {146 0 0-6114 {}} {146 0 0-6115 {}} {146 0 0-6116 {}} {146 0 0-6117 {}} {146 0 0-6118 {}} {146 0 0-6119 {}} {146 0 0-6120 {}} {146 0 0-6121 {}} {146 0 0-6122 {}} {146 0 0-6123 {}} {146 0 0-6124 {}} {146 0 0-6125 {}} {146 0 0-6126 {}} {146 0 0-6127 {}} {146 0 0-6128 {}} {146 0 0-6129 {}} {146 0 0-6130 {}} {146 0 0-6131 {}} {146 0 0-6132 {}} {146 0 0-6133 {}} {146 0 0-6134 {}} {146 0 0-6135 {}} {146 0 0-6136 {}} {146 0 0-6137 {}} {146 0 0-6138 {}} {146 0 0-6139 {}} {146 0 0-6140 {}} {146 0 0-6141 {}} {146 0 0-6142 {}} {146 0 0-6143 {}} {146 0 0-6144 {}} {146 0 0-6145 {}} {146 0 0-6146 {}} {146 0 0-6147 {}} {146 0 0-6148 {}} {146 0 0-6149 {}} {146 0 0-6150 {}} {146 0 0-6151 {}} {146 0 0-6152 {}} {146 0 0-6153 {}} {146 0 0-6154 {}} {146 0 0-6155 {}} {146 0 0-6156 {}} {130 0 0-6157 {}} {146 0 0-6350 {}} {146 0 0-6351 {}} {146 0 0-6352 {}} {146 0 0-6353 {}} {146 0 0-6354 {}} {146 0 0-6355 {}} {146 0 0-6356 {}} {146 0 0-6357 {}} {146 0 0-6358 {}} {146 0 0-6359 {}} {146 0 0-6360 {}} {146 0 0-6361 {}} {146 0 0-6362 {}} {146 0 0-6363 {}} {146 0 0-6364 {}} {146 0 0-6365 {}} {146 0 0-6366 {}} {146 0 0-6367 {}} {146 0 0-6368 {}} {146 0 0-6369 {}} {146 0 0-6370 {}} {146 0 0-6371 {}} {146 0 0-6372 {}} {146 0 0-6373 {}} {146 0 0-6374 {}} {146 0 0-6375 {}} {146 0 0-6376 {}} {146 0 0-6377 {}} {146 0 0-6378 {}} {146 0 0-6379 {}} {146 0 0-6380 {}} {146 0 0-6381 {}} {146 0 0-6382 {}} {146 0 0-6383 {}} {146 0 0-6384 {}} {146 0 0-6385 {}} {146 0 0-6386 {}} {146 0 0-6387 {}} {146 0 0-6388 {}} {146 0 0-6389 {}} {146 0 0-6390 {}} {146 0 0-6391 {}} {146 0 0-6392 {}} {146 0 0-6393 {}} {146 0 0-6394 {}} {146 0 0-6395 {}} {146 0 0-6396 {}} {146 0 0-6397 {}} {146 0 0-6398 {}} {146 0 0-6399 {}} {146 0 0-6400 {}} {146 0 0-6401 {}} {146 0 0-6402 {}} {146 0 0-6403 {}} {146 0 0-6404 {}} {146 0 0-6405 {}} {146 0 0-6406 {}} {146 0 0-6407 {}} {146 0 0-6408 {}} {146 0 0-6409 {}} {146 0 0-6410 {}} {146 0 0-6411 {}} {146 0 0-6412 {}} {146 0 0-6413 {}} {146 0 0-6414 {}} {146 0 0-6415 {}} {146 0 0-6416 {}} {146 0 0-6417 {}} {146 0 0-6418 {}} {146 0 0-6419 {}} {146 0 0-6420 {}} {146 0 0-6421 {}} {146 0 0-6422 {}} {146 0 0-6423 {}} {146 0 0-6424 {}} {146 0 0-6425 {}} {146 0 0-6426 {}} {146 0 0-6427 {}} {146 0 0-6428 {}} {146 0 0-6429 {}} {146 0 0-6430 {}} {146 0 0-6431 {}} {146 0 0-6432 {}} {146 0 0-6433 {}} {146 0 0-6434 {}} {146 0 0-6435 {}} {146 0 0-6436 {}} {146 0 0-6437 {}} {146 0 0-6438 {}} {146 0 0-6439 {}} {146 0 0-6440 {}} {146 0 0-6441 {}} {146 0 0-6442 {}} {146 0 0-6443 {}} {146 0 0-6444 {}} {146 0 0-6445 {}} {146 0 0-6446 {}} {146 0 0-6447 {}} {146 0 0-6448 {}} {146 0 0-6449 {}} {146 0 0-6450 {}} {146 0 0-6451 {}} {146 0 0-6452 {}} {146 0 0-6453 {}}} CYCLES {}}
+set a(0-6082) {NAME slc(i#7.lpi#1) TYPE READSLICE PAR 0-6006 XREFS 37779 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}}} SUCCS {{258 0 0-6090 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6083) {NAME slc(i#7.lpi#1)#1 TYPE READSLICE PAR 0-6006 XREFS 37780 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}}} SUCCS {{258 0 0-6087 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6084) {NAME slc(i#7.lpi#1)#2 TYPE READSLICE PAR 0-6006 XREFS 37781 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}}} SUCCS {{258 0 0-6093 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6085) {NAME slc(i#7.lpi#1)#3 TYPE READSLICE PAR 0-6006 XREFS 37782 LOC {1 0.0 1 0.048655775 1 0.048655775 2 1.0} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}}} SUCCS {{256 0 0-6472 {}}} CYCLES {}}
+set a(0-6086) {NAME FRAME:for#1:slc(i#7.lpi#1) TYPE READSLICE PAR 0-6006 XREFS 37783 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}}} SUCCS {{258 0 0-6088 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6087) {NAME FRAME:for#1:not#1 TYPE NOT PAR 0-6006 XREFS 37784 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6081 {}} {258 0 0-6083 {}}} SUCCS {{259 0 0-6088 {}}} CYCLES {}}
+set a(0-6088) {NAME FRAME:for#1:nand TYPE NAND PAR 0-6006 XREFS 37785 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6081 {}} {258 0 0-6086 {}} {259 0 0-6087 {}}} SUCCS {{258 0 0-6094 {}}} CYCLES {}}
+set a(0-6089) {NAME FRAME:for#1:slc(i#7.lpi#1)#1 TYPE READSLICE PAR 0-6006 XREFS 37786 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}}} SUCCS {{259 0 0-6090 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6090) {NAME FRAME:for#1:nor TYPE NOR PAR 0-6006 XREFS 37787 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6081 {}} {258 0 0-6082 {}} {259 0 0-6089 {}}} SUCCS {{258 0 0-6094 {}}} CYCLES {}}
+set a(0-6091) {NAME FRAME:for#1:slc(i#7.lpi#1)#2 TYPE READSLICE PAR 0-6006 XREFS 37788 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}}} SUCCS {{259 0 0-6092 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6092) {NAME FRAME:for#1:not#2 TYPE NOT PAR 0-6006 XREFS 37789 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6081 {}} {259 0 0-6091 {}}} SUCCS {{259 0 0-6093 {}}} CYCLES {}}
+set a(0-6093) {NAME FRAME:for#1:and TYPE AND PAR 0-6006 XREFS 37790 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6081 {}} {258 0 0-6084 {}} {259 0 0-6092 {}}} SUCCS {{259 0 0-6094 {}}} CYCLES {}}
+set a(0-6094) {NAME FRAME:for#1:or TYPE OR PAR 0-6006 XREFS 37791 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.807076075} PREDS {{146 0 0-6081 {}} {258 0 0-6090 {}} {258 0 0-6088 {}} {259 0 0-6093 {}}} SUCCS {{258 0 0-6099 {}} {258 0 0-6106 {}} {258 0 0-6113 {}}} CYCLES {}}
+set a(0-6095) {NAME {regs.operator[]#15:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 37792 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6098 {}}} CYCLES {}}
+set a(0-6096) {NAME {regs.operator[]#15:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 37793 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6098 {}}} CYCLES {}}
+set a(0-6097) {NAME {regs.operator[]#15:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 37794 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6098 {}}} CYCLES {}}
+set a(0-6098) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#15:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 37795 LOC {1 0.0230606 1 0.15426555 1 0.15426555 1 0.2127933 1 0.807076025} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}} {258 0 0-6096 {}} {258 0 0-6095 {}} {259 0 0-6097 {}}} SUCCS {{258 0 0-6100 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6099) {NAME FRAME:for#1:conc#5 TYPE CONCATENATE PAR 0-6006 XREFS 37796 LOC {1 0.0 1 0.21279335 1 0.21279335 1 0.807076075} PREDS {{146 0 0-6081 {}} {258 0 0-6094 {}}} SUCCS {{259 0 0-6100 {}}} CYCLES {}}
+set a(0-6100) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for#1:mul TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 37797 LOC {1 0.08158839999999999 1 0.21279335 1 0.21279335 1 0.4057172125 1 0.9999999374999999} PREDS {{146 0 0-6081 {}} {258 0 0-6098 {}} {259 0 0-6099 {}}} SUCCS {{259 0 0-6101 {}}} CYCLES {}}
+set a(0-6101) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for#1:acc#1 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6006 XREFS 37798 LOC {1 0.274512325 1 0.405717275 1 0.405717275 1 0.5117190163378799 2 0.24466909133787984} PREDS {{146 0 0-6081 {}} {258 0 0-6049 {}} {259 0 0-6100 {}}} SUCCS {{258 0 0-6160 {}} {258 0 0-6463 {}}} CYCLES {}}
+set a(0-6102) {NAME {regs.operator[]#16:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 37799 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6105 {}}} CYCLES {}}
+set a(0-6103) {NAME {regs.operator[]#16:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 37800 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6105 {}}} CYCLES {}}
+set a(0-6104) {NAME {regs.operator[]#16:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 37801 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6105 {}}} CYCLES {}}
+set a(0-6105) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#16:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 37802 LOC {1 0.0230606 1 0.15426555 1 0.15426555 1 0.2127933 1 0.807076025} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}} {258 0 0-6103 {}} {258 0 0-6102 {}} {259 0 0-6104 {}}} SUCCS {{258 0 0-6107 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6106) {NAME FRAME:for#1:conc#6 TYPE CONCATENATE PAR 0-6006 XREFS 37803 LOC {1 0.0 1 0.21279335 1 0.21279335 1 0.807076075} PREDS {{146 0 0-6081 {}} {258 0 0-6094 {}}} SUCCS {{259 0 0-6107 {}}} CYCLES {}}
+set a(0-6107) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for#1:mul#1 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 37804 LOC {1 0.08158839999999999 1 0.21279335 1 0.21279335 1 0.4057172125 1 0.9999999374999999} PREDS {{146 0 0-6081 {}} {258 0 0-6105 {}} {259 0 0-6106 {}}} SUCCS {{259 0 0-6108 {}}} CYCLES {}}
+set a(0-6108) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for#1:acc#2 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6006 XREFS 37805 LOC {1 0.274512325 1 0.405717275 1 0.405717275 1 0.5117190163378799 2 0.16078416633787984} PREDS {{146 0 0-6081 {}} {258 0 0-6055 {}} {259 0 0-6107 {}}} SUCCS {{258 0 0-6164 {}} {258 0 0-6465 {}}} CYCLES {}}
+set a(0-6109) {NAME {regs.operator[]#17:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 37806 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6112 {}}} CYCLES {}}
+set a(0-6110) {NAME {regs.operator[]#17:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 37807 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6112 {}}} CYCLES {}}
+set a(0-6111) {NAME {regs.operator[]#17:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 37808 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6112 {}}} CYCLES {}}
+set a(0-6112) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#17:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 37809 LOC {1 0.0230606 1 0.15426555 1 0.15426555 1 0.2127933 1 0.807076025} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}} {258 0 0-6110 {}} {258 0 0-6109 {}} {259 0 0-6111 {}}} SUCCS {{258 0 0-6114 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6113) {NAME FRAME:for#1:conc#7 TYPE CONCATENATE PAR 0-6006 XREFS 37810 LOC {1 0.0 1 0.21279335 1 0.21279335 1 0.807076075} PREDS {{146 0 0-6081 {}} {258 0 0-6094 {}}} SUCCS {{259 0 0-6114 {}}} CYCLES {}}
+set a(0-6114) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for#1:mul#2 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 37811 LOC {1 0.08158839999999999 1 0.21279335 1 0.21279335 1 0.4057172125 1 0.9999999374999999} PREDS {{146 0 0-6081 {}} {258 0 0-6112 {}} {259 0 0-6113 {}}} SUCCS {{259 0 0-6115 {}}} CYCLES {}}
+set a(0-6115) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for#1:acc#3 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6006 XREFS 37812 LOC {1 0.274512325 1 0.405717275 1 0.405717275 1 0.5117190163378799 2 0.16078416633787984} PREDS {{146 0 0-6081 {}} {258 0 0-6061 {}} {259 0 0-6114 {}}} SUCCS {{258 0 0-6168 {}} {258 0 0-6467 {}}} CYCLES {}}
+set a(0-6116) {NAME i:slc(i#4)#1 TYPE READSLICE PAR 0-6006 XREFS 37813 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}}} SUCCS {{259 0 0-6117 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6117) {NAME FRAME:for#1:not#4 TYPE NOT PAR 0-6006 XREFS 37814 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6081 {}} {259 0 0-6116 {}}} SUCCS {{258 0 0-6119 {}}} CYCLES {}}
+set a(0-6118) {NAME i:slc(i#4)#2 TYPE READSLICE PAR 0-6006 XREFS 37815 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}}} SUCCS {{259 0 0-6119 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6119) {NAME FRAME:for#1:conc TYPE CONCATENATE PAR 0-6006 XREFS 37816 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6081 {}} {258 0 0-6117 {}} {259 0 0-6118 {}}} SUCCS {{259 0 0-6120 {}} {258 0 0-6121 {}} {258 0 0-6122 {}} {258 0 0-6123 {}} {258 0 0-6124 {}} {258 0 0-6128 {}}} CYCLES {}}
+set a(0-6120) {NAME slc(FRAME:for#1:conc.tmp) TYPE READSLICE PAR 0-6006 XREFS 37817 LOC {1 0.0 1 0.048655775 1 0.048655775 3 1.0} PREDS {{146 0 0-6081 {}} {259 0 0-6119 {}}} SUCCS {} CYCLES {}}
+set a(0-6121) {NAME slc(FRAME:for#1:conc.tmp)#1 TYPE READSLICE PAR 0-6006 XREFS 37818 LOC {1 0.0 1 0.048655775 1 0.048655775 3 1.0} PREDS {{146 0 0-6081 {}} {258 0 0-6119 {}}} SUCCS {} CYCLES {}}
+set a(0-6122) {NAME slc(FRAME:for#1:conc.tmp)#2 TYPE READSLICE PAR 0-6006 XREFS 37819 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.6843317999999999} PREDS {{146 0 0-6081 {}} {258 0 0-6119 {}}} SUCCS {{258 0 0-6130 {}}} CYCLES {}}
+set a(0-6123) {NAME slc(FRAME:for#1:conc.tmp)#3 TYPE READSLICE PAR 0-6006 XREFS 37820 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6081 {}} {258 0 0-6119 {}}} SUCCS {{258 0 0-6125 {}}} CYCLES {}}
+set a(0-6124) {NAME FRAME:for#1:slc(FRAME:for#1:conc.tmp) TYPE READSLICE PAR 0-6006 XREFS 37821 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6081 {}} {258 0 0-6119 {}}} SUCCS {{259 0 0-6125 {}}} CYCLES {}}
+set a(0-6125) {NAME FRAME:for#1:nand#1 TYPE NAND PAR 0-6006 XREFS 37822 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.667925025} PREDS {{146 0 0-6081 {}} {258 0 0-6123 {}} {259 0 0-6124 {}}} SUCCS {{259 0 0-6126 {}}} CYCLES {}}
+set a(0-6126) {NAME FRAME:for#1:exs TYPE SIGNEXTEND PAR 0-6006 XREFS 37823 LOC {1 0.0 1 0.074034325 1 0.074034325 1 0.667925025} PREDS {{146 0 0-6081 {}} {259 0 0-6125 {}}} SUCCS {{259 0 0-6127 {}}} CYCLES {}}
+set a(0-6127) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 6 NAME FRAME:for#1:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 37824 LOC {1 0.0 1 0.074034325 1 0.074034325 1 0.0904410562638539 1 0.6843317562638539} PREDS {{146 0 0-6081 {}} {259 0 0-6126 {}}} SUCCS {{258 0 0-6132 {}}} CYCLES {}}
+set a(0-6128) {NAME FRAME:for#1:slc(FRAME:for#1:conc.tmp)#1 TYPE READSLICE PAR 0-6006 XREFS 37825 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.6843317999999999} PREDS {{146 0 0-6081 {}} {258 0 0-6119 {}}} SUCCS {{259 0 0-6129 {}}} CYCLES {}}
+set a(0-6129) {NAME FRAME:for#1:not#3 TYPE NOT PAR 0-6006 XREFS 37826 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.6843317999999999} PREDS {{146 0 0-6081 {}} {259 0 0-6128 {}}} SUCCS {{259 0 0-6130 {}}} CYCLES {}}
+set a(0-6130) {NAME FRAME:for#1:and#2 TYPE AND PAR 0-6006 XREFS 37827 LOC {1 0.0 1 0.048655775 1 0.048655775 1 0.6843317999999999} PREDS {{146 0 0-6081 {}} {258 0 0-6122 {}} {259 0 0-6129 {}}} SUCCS {{259 0 0-6131 {}}} CYCLES {}}
+set a(0-6131) {NAME FRAME:for#1:exs#19 TYPE SIGNEXTEND PAR 0-6006 XREFS 37828 LOC {1 0.0 1 0.0904411 1 0.0904411 1 0.6843317999999999} PREDS {{146 0 0-6081 {}} {259 0 0-6130 {}}} SUCCS {{259 0 0-6132 {}}} CYCLES {}}
+set a(0-6132) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(2,2) AREA_SCORE 1.46 QUANTITY 4 NAME FRAME:for#1:or#1 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-6006 XREFS 37829 LOC {1 0.016406775 1 0.0904411 1 0.0904411 1 0.10718353110773884 1 0.7010742311077388} PREDS {{146 0 0-6081 {}} {258 0 0-6127 {}} {259 0 0-6131 {}}} SUCCS {{258 0 0-6137 {}} {258 0 0-6143 {}} {258 0 0-6149 {}}} CYCLES {}}
+set a(0-6133) {NAME {regs.operator[]#21:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 37830 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6136 {}}} CYCLES {}}
+set a(0-6134) {NAME {regs.operator[]#21:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 37831 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6136 {}}} CYCLES {}}
+set a(0-6135) {NAME {regs.operator[]#21:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 37832 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.748548275} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6136 {}}} CYCLES {}}
+set a(0-6136) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#21:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 37833 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.107183525 1 0.807076025} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}} {258 0 0-6134 {}} {258 0 0-6133 {}} {259 0 0-6135 {}}} SUCCS {{259 0 0-6137 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6137) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for#1:mul#6 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 37834 LOC {1 0.08158839999999999 1 0.10718357499999999 1 0.10718357499999999 1 0.30010743749999996 1 0.9999999374999999} PREDS {{146 0 0-6081 {}} {258 0 0-6132 {}} {259 0 0-6136 {}}} SUCCS {{259 0 0-6138 {}}} CYCLES {}}
+set a(0-6138) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for#1:acc#10 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6006 XREFS 37835 LOC {1 0.274512325 1 0.30010749999999997 1 0.30010749999999997 1 0.40610924133787984 2 0.13905931633787985} PREDS {{146 0 0-6081 {}} {258 0 0-6052 {}} {259 0 0-6137 {}}} SUCCS {{258 0 0-6159 {}} {258 0 0-6464 {}}} CYCLES {}}
+set a(0-6139) {NAME {regs.operator[]#22:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 37836 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6142 {}}} CYCLES {}}
+set a(0-6140) {NAME {regs.operator[]#22:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 37837 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6142 {}}} CYCLES {}}
+set a(0-6141) {NAME {regs.operator[]#22:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 37838 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6142 {}}} CYCLES {}}
+set a(0-6142) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#22:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 37839 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.107183525 1 0.7010742249999999} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}} {258 0 0-6140 {}} {258 0 0-6139 {}} {259 0 0-6141 {}}} SUCCS {{259 0 0-6143 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6143) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for#1:mul#7 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 37840 LOC {1 0.08158839999999999 1 0.10718357499999999 1 0.10718357499999999 1 0.30010743749999996 1 0.8939981374999999} PREDS {{146 0 0-6081 {}} {258 0 0-6132 {}} {259 0 0-6142 {}}} SUCCS {{259 0 0-6144 {}}} CYCLES {}}
+set a(0-6144) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for#1:acc#12 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6006 XREFS 37841 LOC {1 0.274512325 1 0.30010749999999997 1 0.30010749999999997 1 0.40610924133787984 1 0.9999999413378798} PREDS {{146 0 0-6081 {}} {258 0 0-6058 {}} {259 0 0-6143 {}}} SUCCS {{258 0 0-6163 {}} {258 0 0-6466 {}}} CYCLES {}}
+set a(0-6145) {NAME {regs.operator[]#23:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 37842 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6148 {}}} CYCLES {}}
+set a(0-6146) {NAME {regs.operator[]#23:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 37843 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6148 {}}} CYCLES {}}
+set a(0-6147) {NAME {regs.operator[]#23:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 37844 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6148 {}}} CYCLES {}}
+set a(0-6148) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#23:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 37845 LOC {1 0.0230606 1 0.048655775 1 0.048655775 1 0.107183525 1 0.7010742249999999} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}} {258 0 0-6146 {}} {258 0 0-6145 {}} {259 0 0-6147 {}}} SUCCS {{259 0 0-6149 {}} {256 0 0-6472 {}}} CYCLES {}}
+set a(0-6149) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for#1:mul#8 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 37846 LOC {1 0.08158839999999999 1 0.10718357499999999 1 0.10718357499999999 1 0.30010743749999996 1 0.8939981374999999} PREDS {{146 0 0-6081 {}} {258 0 0-6132 {}} {259 0 0-6148 {}}} SUCCS {{259 0 0-6150 {}}} CYCLES {}}
+set a(0-6150) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for#1:acc#14 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6006 XREFS 37847 LOC {1 0.274512325 1 0.30010749999999997 1 0.30010749999999997 1 0.40610924133787984 1 0.9999999413378798} PREDS {{146 0 0-6081 {}} {258 0 0-6064 {}} {259 0 0-6149 {}}} SUCCS {{258 0 0-6167 {}} {258 0 0-6468 {}}} CYCLES {}}
+set a(0-6151) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,2) AREA_SCORE 3.31 QUANTITY 2 NAME FRAME:for#1:acc#16 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-6006 XREFS 37848 LOC {1 0.0 1 0.317770075 1 0.317770075 1 0.35855308508947525 1 0.9999999600894752} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}}} SUCCS {{259 0 0-6152 {}} {258 0 0-6472 {}}} CYCLES {}}
+set a(0-6152) {NAME FRAME:for#1:asn#2 TYPE ASSIGN PAR 0-6006 XREFS 37849 LOC {1 0.04078305 1 0.358553125 1 0.358553125 2 0.007618275} PREDS {{146 0 0-6081 {}} {259 0 0-6151 {}}} SUCCS {{259 0 0-6153 {}}} CYCLES {}}
+set a(0-6153) {NAME FRAME:for#1:conc#11 TYPE CONCATENATE PAR 0-6006 XREFS 37850 LOC {1 0.04078305 1 0.358553125 1 0.358553125 2 0.007618275} PREDS {{146 0 0-6081 {}} {259 0 0-6152 {}}} SUCCS {{259 0 0-6154 {}}} CYCLES {}}
+set a(0-6154) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,3) AREA_SCORE 4.30 QUANTITY 2 NAME FRAME:for#1:acc TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 37851 LOC {1 0.04078305 1 0.358553125 1 0.358553125 1 0.40610925207082715 2 0.055174402070827175} PREDS {{146 0 0-6081 {}} {259 0 0-6153 {}}} SUCCS {{259 0 0-6155 {}}} CYCLES {}}
+set a(0-6155) {NAME FRAME:for#1:slc TYPE READSLICE PAR 0-6006 XREFS 37852 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.05517445} PREDS {{146 0 0-6081 {}} {259 0 0-6154 {}}} SUCCS {{259 0 0-6156 {}}} CYCLES {}}
+set a(0-6156) {NAME FRAME:for#1:not TYPE NOT PAR 0-6006 XREFS 37853 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.05517445} PREDS {{146 0 0-6081 {}} {259 0 0-6155 {}}} SUCCS {{259 0 0-6157 {}} {258 0 0-6454 {}} {258 0 0-6456 {}} {258 0 0-6469 {}}} CYCLES {}}
+set a(0-6157) {NAME FRAME:for#1:select TYPE SELECT PAR 0-6006 XREFS 37854 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.05517445} PREDS {{130 0 0-6081 {}} {259 0 0-6156 {}}} SUCCS {{146 0 0-6158 {}} {146 0 0-6159 {}} {146 0 0-6160 {}} {146 0 0-6161 {}} {146 0 0-6162 {}} {146 0 0-6163 {}} {146 0 0-6164 {}} {146 0 0-6165 {}} {146 0 0-6166 {}} {146 0 0-6167 {}} {146 0 0-6168 {}} {146 0 0-6169 {}} {146 0 0-6170 {}} {146 0 0-6171 {}} {146 0 0-6172 {}} {146 0 0-6173 {}} {146 0 0-6174 {}} {146 0 0-6175 {}} {146 0 0-6176 {}} {146 0 0-6177 {}} {146 0 0-6178 {}} {146 0 0-6179 {}} {146 0 0-6180 {}} {146 0 0-6181 {}} {146 0 0-6182 {}} {146 0 0-6183 {}} {146 0 0-6184 {}} {146 0 0-6185 {}} {146 0 0-6186 {}} {146 0 0-6187 {}} {146 0 0-6188 {}} {146 0 0-6189 {}} {146 0 0-6190 {}} {146 0 0-6191 {}} {146 0 0-6192 {}} {146 0 0-6193 {}} {146 0 0-6194 {}} {146 0 0-6195 {}} {146 0 0-6196 {}} {146 0 0-6197 {}} {146 0 0-6198 {}} {146 0 0-6199 {}} {146 0 0-6200 {}} {146 0 0-6201 {}} {146 0 0-6202 {}} {146 0 0-6203 {}} {146 0 0-6204 {}} {146 0 0-6205 {}} {146 0 0-6206 {}} {146 0 0-6207 {}} {146 0 0-6208 {}} {146 0 0-6209 {}} {146 0 0-6210 {}} {146 0 0-6211 {}} {146 0 0-6212 {}} {146 0 0-6213 {}} {146 0 0-6214 {}} {146 0 0-6215 {}} {146 0 0-6216 {}} {146 0 0-6217 {}} {146 0 0-6218 {}} {146 0 0-6219 {}} {146 0 0-6220 {}} {146 0 0-6221 {}} {146 0 0-6222 {}} {146 0 0-6223 {}} {146 0 0-6224 {}} {146 0 0-6225 {}} {146 0 0-6226 {}} {146 0 0-6227 {}} {146 0 0-6228 {}} {146 0 0-6229 {}} {146 0 0-6230 {}} {146 0 0-6231 {}} {146 0 0-6232 {}} {146 0 0-6233 {}} {146 0 0-6234 {}} {146 0 0-6235 {}} {146 0 0-6236 {}} {146 0 0-6237 {}} {146 0 0-6238 {}} {146 0 0-6239 {}} {146 0 0-6240 {}} {146 0 0-6241 {}} {146 0 0-6242 {}} {146 0 0-6243 {}} {146 0 0-6244 {}} {146 0 0-6245 {}} {146 0 0-6246 {}} {146 0 0-6247 {}} {146 0 0-6248 {}} {146 0 0-6249 {}} {146 0 0-6250 {}} {146 0 0-6251 {}} {146 0 0-6252 {}} {146 0 0-6253 {}} {146 0 0-6254 {}} {146 0 0-6255 {}} {146 0 0-6256 {}} {146 0 0-6257 {}} {146 0 0-6258 {}} {146 0 0-6259 {}} {146 0 0-6260 {}} {146 0 0-6261 {}} {146 0 0-6262 {}} {146 0 0-6263 {}} {146 0 0-6264 {}} {146 0 0-6265 {}} {146 0 0-6266 {}} {146 0 0-6267 {}} {146 0 0-6268 {}} {146 0 0-6269 {}} {146 0 0-6270 {}} {146 0 0-6271 {}} {146 0 0-6272 {}} {146 0 0-6273 {}} {146 0 0-6274 {}} {146 0 0-6275 {}} {146 0 0-6276 {}} {146 0 0-6277 {}} {146 0 0-6278 {}} {146 0 0-6279 {}} {146 0 0-6280 {}} {146 0 0-6281 {}} {146 0 0-6282 {}} {146 0 0-6283 {}} {146 0 0-6284 {}} {146 0 0-6285 {}} {146 0 0-6286 {}} {146 0 0-6287 {}} {146 0 0-6288 {}} {146 0 0-6289 {}} {146 0 0-6290 {}} {146 0 0-6291 {}} {146 0 0-6292 {}} {146 0 0-6293 {}} {146 0 0-6294 {}} {146 0 0-6295 {}} {146 0 0-6296 {}} {146 0 0-6297 {}} {146 0 0-6298 {}} {146 0 0-6299 {}} {146 0 0-6300 {}} {146 0 0-6301 {}} {146 0 0-6302 {}} {146 0 0-6303 {}} {146 0 0-6304 {}} {146 0 0-6305 {}} {146 0 0-6306 {}} {146 0 0-6307 {}} {146 0 0-6308 {}} {146 0 0-6309 {}} {146 0 0-6310 {}} {146 0 0-6311 {}} {146 0 0-6312 {}} {146 0 0-6313 {}} {146 0 0-6314 {}} {146 0 0-6315 {}} {146 0 0-6316 {}} {146 0 0-6317 {}} {146 0 0-6318 {}} {146 0 0-6319 {}} {146 0 0-6320 {}} {146 0 0-6321 {}} {146 0 0-6322 {}} {146 0 0-6323 {}} {146 0 0-6324 {}} {146 0 0-6325 {}} {146 0 0-6326 {}} {146 0 0-6327 {}} {146 0 0-6328 {}} {146 0 0-6329 {}} {146 0 0-6330 {}} {146 0 0-6331 {}} {146 0 0-6332 {}} {146 0 0-6333 {}} {146 0 0-6334 {}} {146 0 0-6335 {}} {146 0 0-6336 {}} {146 0 0-6337 {}} {146 0 0-6338 {}} {146 0 0-6339 {}} {146 0 0-6340 {}} {146 0 0-6341 {}} {146 0 0-6342 {}} {146 0 0-6343 {}} {130 0 0-6344 {}} {146 0 0-6345 {}} {146 0 0-6346 {}} {146 0 0-6347 {}} {146 0 0-6348 {}} {146 0 0-6349 {}}} CYCLES {}}
+set a(0-6158) {NAME r:conc TYPE CONCATENATE PAR 0-6006 XREFS 37855 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.13905937499999999} PREDS {{146 0 0-6157 {}} {258 0 0-6070 {}}} SUCCS {{259 0 0-6159 {}}} CYCLES {}}
+set a(0-6159) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 6 NAME ACC2:acc TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-6006 XREFS 37856 LOC {1 0.380514125 1 0.4061093 1 0.4061093 1 0.511719030357901 2 0.24466910535790098} PREDS {{146 0 0-6157 {}} {258 0 0-6138 {}} {259 0 0-6158 {}}} SUCCS {{259 0 0-6160 {}}} CYCLES {}}
+set a(0-6160) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 6 NAME ACC2-3:acc#1 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-6006 XREFS 37857 LOC {1 0.4861239 1 0.511719075 1 0.511719075 1 0.617328805357901 2 0.350278880357901} PREDS {{146 0 0-6157 {}} {258 0 0-6101 {}} {259 0 0-6159 {}}} SUCCS {{259 0 0-6161 {}}} CYCLES {}}
+set a(0-6161) {NAME ACC2:slc TYPE READSLICE PAR 0-6006 XREFS 37858 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6157 {}} {259 0 0-6160 {}}} SUCCS {{258 0 0-6170 {}} {258 0 0-6171 {}} {258 0 0-6174 {}} {258 0 0-6176 {}} {258 0 0-6179 {}} {258 0 0-6182 {}} {258 0 0-6183 {}} {258 0 0-6298 {}} {258 0 0-6300 {}} {258 0 0-6301 {}} {258 0 0-6303 {}} {258 0 0-6306 {}} {258 0 0-6308 {}} {258 0 0-6325 {}}} CYCLES {}}
+set a(0-6162) {NAME g:conc TYPE CONCATENATE PAR 0-6006 XREFS 37859 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.05517445} PREDS {{146 0 0-6157 {}} {258 0 0-6073 {}}} SUCCS {{259 0 0-6163 {}}} CYCLES {}}
+set a(0-6163) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 6 NAME ACC2:acc#5 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-6006 XREFS 37860 LOC {1 0.380514125 1 0.4061093 1 0.4061093 1 0.511719030357901 2 0.16078418035790099} PREDS {{146 0 0-6157 {}} {258 0 0-6144 {}} {259 0 0-6162 {}}} SUCCS {{259 0 0-6164 {}}} CYCLES {}}
+set a(0-6164) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 6 NAME ACC2-3:acc#2 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-6006 XREFS 37861 LOC {1 0.4861239 1 0.511719075 1 0.511719075 1 0.617328805357901 2 0.266393955357901} PREDS {{146 0 0-6157 {}} {258 0 0-6108 {}} {259 0 0-6163 {}}} SUCCS {{259 0 0-6165 {}}} CYCLES {}}
+set a(0-6165) {NAME ACC2:slc#1 TYPE READSLICE PAR 0-6006 XREFS 37862 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {259 0 0-6164 {}}} SUCCS {{258 0 0-6188 {}} {258 0 0-6189 {}} {258 0 0-6192 {}} {258 0 0-6194 {}} {258 0 0-6197 {}} {258 0 0-6200 {}} {258 0 0-6201 {}} {258 0 0-6206 {}} {258 0 0-6208 {}} {258 0 0-6210 {}} {258 0 0-6227 {}} {258 0 0-6236 {}} {258 0 0-6237 {}} {258 0 0-6239 {}}} CYCLES {}}
+set a(0-6166) {NAME b:conc TYPE CONCATENATE PAR 0-6006 XREFS 37863 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.05517445} PREDS {{146 0 0-6157 {}} {258 0 0-6076 {}}} SUCCS {{259 0 0-6167 {}}} CYCLES {}}
+set a(0-6167) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 6 NAME ACC2:acc#6 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-6006 XREFS 37864 LOC {1 0.380514125 1 0.4061093 1 0.4061093 1 0.511719030357901 2 0.16078418035790099} PREDS {{146 0 0-6157 {}} {258 0 0-6150 {}} {259 0 0-6166 {}}} SUCCS {{259 0 0-6168 {}}} CYCLES {}}
+set a(0-6168) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,16,0,16) AREA_SCORE 17.19 QUANTITY 6 NAME ACC2-3:acc#3 TYPE ACCU DELAY {1.69 ns} LIBRARY_DELAY {1.69 ns} PAR 0-6006 XREFS 37865 LOC {1 0.4861239 1 0.511719075 1 0.511719075 1 0.617328805357901 2 0.266393955357901} PREDS {{146 0 0-6157 {}} {258 0 0-6115 {}} {259 0 0-6167 {}}} SUCCS {{259 0 0-6169 {}}} CYCLES {}}
+set a(0-6169) {NAME ACC2:slc#2 TYPE READSLICE PAR 0-6006 XREFS 37866 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {259 0 0-6168 {}}} SUCCS {{258 0 0-6243 {}} {258 0 0-6244 {}} {258 0 0-6247 {}} {258 0 0-6249 {}} {258 0 0-6252 {}} {258 0 0-6255 {}} {258 0 0-6256 {}} {258 0 0-6261 {}} {258 0 0-6263 {}} {258 0 0-6265 {}} {258 0 0-6282 {}} {258 0 0-6291 {}} {258 0 0-6292 {}} {258 0 0-6294 {}}} CYCLES {}}
+set a(0-6170) {NAME red:slc(red#2.sg1)#4 TYPE READSLICE PAR 0-6006 XREFS 37867 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{258 0 0-6173 {}}} CYCLES {}}
+set a(0-6171) {NAME red:slc(red#2.sg1)#5 TYPE READSLICE PAR 0-6006 XREFS 37868 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{259 0 0-6172 {}}} CYCLES {}}
+set a(0-6172) {NAME FRAME:not#2 TYPE NOT PAR 0-6006 XREFS 37869 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6157 {}} {259 0 0-6171 {}}} SUCCS {{259 0 0-6173 {}}} CYCLES {}}
+set a(0-6173) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#8 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 37870 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.39783505207082714} PREDS {{146 0 0-6157 {}} {258 0 0-6170 {}} {259 0 0-6172 {}}} SUCCS {{258 0 0-6181 {}}} CYCLES {}}
+set a(0-6174) {NAME red:slc(red#2.sg1)#6 TYPE READSLICE PAR 0-6006 XREFS 37871 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{259 0 0-6175 {}}} CYCLES {}}
+set a(0-6175) {NAME FRAME:not#3 TYPE NOT PAR 0-6006 XREFS 37872 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6157 {}} {259 0 0-6174 {}}} SUCCS {{258 0 0-6178 {}}} CYCLES {}}
+set a(0-6176) {NAME red:slc(red#2.sg1)#7 TYPE READSLICE PAR 0-6006 XREFS 37873 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{259 0 0-6177 {}}} CYCLES {}}
+set a(0-6177) {NAME FRAME:not#25 TYPE NOT PAR 0-6006 XREFS 37874 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6157 {}} {259 0 0-6176 {}}} SUCCS {{259 0 0-6178 {}}} CYCLES {}}
+set a(0-6178) {NAME FRAME:conc TYPE CONCATENATE PAR 0-6006 XREFS 37875 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6157 {}} {258 0 0-6175 {}} {259 0 0-6177 {}}} SUCCS {{258 0 0-6180 {}}} CYCLES {}}
+set a(0-6179) {NAME red:slc(red#2.sg1)#1 TYPE READSLICE PAR 0-6006 XREFS 37876 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.35027892499999996} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{259 0 0-6180 {}}} CYCLES {}}
+set a(0-6180) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#7 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 37877 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.39783505207082714} PREDS {{146 0 0-6157 {}} {258 0 0-6178 {}} {259 0 0-6179 {}}} SUCCS {{259 0 0-6181 {}}} CYCLES {}}
+set a(0-6181) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#10 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-6006 XREFS 37878 LOC {1 0.6392898499999999 1 0.664885025 1 0.664885025 1 0.7182320451789506 2 0.4511821201789505} PREDS {{146 0 0-6157 {}} {258 0 0-6173 {}} {259 0 0-6180 {}}} SUCCS {{258 0 0-6186 {}}} CYCLES {}}
+set a(0-6182) {NAME red:slc(red#2.sg1)#2 TYPE READSLICE PAR 0-6006 XREFS 37879 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.403626} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{258 0 0-6185 {}}} CYCLES {}}
+set a(0-6183) {NAME red:slc(red#2.sg1)#3 TYPE READSLICE PAR 0-6006 XREFS 37880 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.403626} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{259 0 0-6184 {}}} CYCLES {}}
+set a(0-6184) {NAME FRAME:not#1 TYPE NOT PAR 0-6006 XREFS 37881 LOC {1 0.591733675 1 0.670675925 1 0.670675925 2 0.403626} PREDS {{146 0 0-6157 {}} {259 0 0-6183 {}}} SUCCS {{259 0 0-6185 {}}} CYCLES {}}
+set a(0-6185) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#9 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 37882 LOC {1 0.591733675 1 0.670675925 1 0.670675925 1 0.7182320520708271 2 0.45118212707082717} PREDS {{146 0 0-6157 {}} {258 0 0-6182 {}} {259 0 0-6184 {}}} SUCCS {{259 0 0-6186 {}}} CYCLES {}}
+set a(0-6186) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,4,0,6) AREA_SCORE 6.29 QUANTITY 3 NAME FRAME:acc#11 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 37883 LOC {1 0.692636925 1 0.7182320999999999 1 0.7182320999999999 1 0.7769849308637015 2 0.5099350058637016} PREDS {{146 0 0-6157 {}} {258 0 0-6181 {}} {259 0 0-6185 {}}} SUCCS {{259 0 0-6187 {}}} CYCLES {}}
+set a(0-6187) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc#3 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-6006 XREFS 37884 LOC {1 0.7513898 1 0.776984975 1 0.776984975 1 0.8404969484103024 2 0.5734470234103024} PREDS {{146 0 0-6157 {}} {259 0 0-6186 {}}} SUCCS {{258 0 0-6309 {}} {258 0 0-6311 {}} {258 0 0-6313 {}} {258 0 0-6315 {}} {258 0 0-6323 {}} {258 0 0-6328 {}}} CYCLES {}}
+set a(0-6188) {NAME green:slc(green#2.sg1)#4 TYPE READSLICE PAR 0-6006 XREFS 37885 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{258 0 0-6191 {}}} CYCLES {}}
+set a(0-6189) {NAME green:slc(green#2.sg1)#5 TYPE READSLICE PAR 0-6006 XREFS 37886 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{259 0 0-6190 {}}} CYCLES {}}
+set a(0-6190) {NAME FRAME:not#10 TYPE NOT PAR 0-6006 XREFS 37887 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {259 0 0-6189 {}}} SUCCS {{259 0 0-6191 {}}} CYCLES {}}
+set a(0-6191) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#13 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 37888 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.31395012707082715} PREDS {{146 0 0-6157 {}} {258 0 0-6188 {}} {259 0 0-6190 {}}} SUCCS {{258 0 0-6199 {}}} CYCLES {}}
+set a(0-6192) {NAME green:slc(green#2.sg1)#6 TYPE READSLICE PAR 0-6006 XREFS 37889 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{259 0 0-6193 {}}} CYCLES {}}
+set a(0-6193) {NAME FRAME:not#11 TYPE NOT PAR 0-6006 XREFS 37890 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {259 0 0-6192 {}}} SUCCS {{258 0 0-6196 {}}} CYCLES {}}
+set a(0-6194) {NAME green:slc(green#2.sg1)#7 TYPE READSLICE PAR 0-6006 XREFS 37891 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{259 0 0-6195 {}}} CYCLES {}}
+set a(0-6195) {NAME FRAME:not#26 TYPE NOT PAR 0-6006 XREFS 37892 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {259 0 0-6194 {}}} SUCCS {{259 0 0-6196 {}}} CYCLES {}}
+set a(0-6196) {NAME FRAME:conc#16 TYPE CONCATENATE PAR 0-6006 XREFS 37893 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {258 0 0-6193 {}} {259 0 0-6195 {}}} SUCCS {{258 0 0-6198 {}}} CYCLES {}}
+set a(0-6197) {NAME green:slc(green#2.sg1)#1 TYPE READSLICE PAR 0-6006 XREFS 37894 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{259 0 0-6198 {}}} CYCLES {}}
+set a(0-6198) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#12 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 37895 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.31395012707082715} PREDS {{146 0 0-6157 {}} {258 0 0-6196 {}} {259 0 0-6197 {}}} SUCCS {{259 0 0-6199 {}}} CYCLES {}}
+set a(0-6199) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#15 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-6006 XREFS 37896 LOC {1 0.6392898499999999 1 0.664885025 1 0.664885025 1 0.7182320451789506 2 0.3672971951789505} PREDS {{146 0 0-6157 {}} {258 0 0-6191 {}} {259 0 0-6198 {}}} SUCCS {{258 0 0-6204 {}}} CYCLES {}}
+set a(0-6200) {NAME green:slc(green#2.sg1)#2 TYPE READSLICE PAR 0-6006 XREFS 37897 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.319741075} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{258 0 0-6203 {}}} CYCLES {}}
+set a(0-6201) {NAME green:slc(green#2.sg1)#3 TYPE READSLICE PAR 0-6006 XREFS 37898 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.319741075} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{259 0 0-6202 {}}} CYCLES {}}
+set a(0-6202) {NAME FRAME:not#9 TYPE NOT PAR 0-6006 XREFS 37899 LOC {1 0.591733675 1 0.670675925 1 0.670675925 2 0.319741075} PREDS {{146 0 0-6157 {}} {259 0 0-6201 {}}} SUCCS {{259 0 0-6203 {}}} CYCLES {}}
+set a(0-6203) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#14 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 37900 LOC {1 0.591733675 1 0.670675925 1 0.670675925 1 0.7182320520708271 2 0.36729720207082717} PREDS {{146 0 0-6157 {}} {258 0 0-6200 {}} {259 0 0-6202 {}}} SUCCS {{259 0 0-6204 {}}} CYCLES {}}
+set a(0-6204) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,4,0,6) AREA_SCORE 6.29 QUANTITY 3 NAME FRAME:acc#16 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 37901 LOC {1 0.692636925 1 0.7182320999999999 1 0.7182320999999999 1 0.7769849308637015 2 0.4260500808637015} PREDS {{146 0 0-6157 {}} {258 0 0-6199 {}} {259 0 0-6203 {}}} SUCCS {{259 0 0-6205 {}}} CYCLES {}}
+set a(0-6205) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc#5 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-6006 XREFS 37902 LOC {1 0.7513898 1 0.776984975 1 0.776984975 1 0.8404969484103024 2 0.4895620984103024} PREDS {{146 0 0-6157 {}} {259 0 0-6204 {}}} SUCCS {{258 0 0-6211 {}} {258 0 0-6213 {}} {258 0 0-6215 {}} {258 0 0-6217 {}} {258 0 0-6225 {}} {258 0 0-6230 {}}} CYCLES {}}
+set a(0-6206) {NAME green:slc(green#2.sg1)#9 TYPE READSLICE PAR 0-6006 XREFS 37903 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.6277733} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{259 0 0-6207 {}}} CYCLES {}}
+set a(0-6207) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#2 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-6006 XREFS 37904 LOC {1 0.591733675 1 0.809739975 1 0.809739975 1 0.9999999562499999 2 0.81803328125} PREDS {{146 0 0-6157 {}} {259 0 0-6206 {}}} SUCCS {{258 0 0-6235 {}}} CYCLES {}}
+set a(0-6208) {NAME green:slc(green#2.sg1)#11 TYPE READSLICE PAR 0-6006 XREFS 37905 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.5731230749999999} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{259 0 0-6209 {}}} CYCLES {}}
+set a(0-6209) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#3 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-6006 XREFS 37906 LOC {1 0.591733675 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.7510048671744312} PREDS {{146 0 0-6157 {}} {259 0 0-6208 {}}} SUCCS {{258 0 0-6234 {}}} CYCLES {}}
+set a(0-6210) {NAME green:slc(green#2.sg1) TYPE READSLICE PAR 0-6006 XREFS 37907 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.7076648999999999} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{258 0 0-6233 {}}} CYCLES {}}
+set a(0-6211) {NAME FRAME:slc(acc.imod#5)#6 TYPE READSLICE PAR 0-6006 XREFS 37908 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.5481619} PREDS {{146 0 0-6157 {}} {258 0 0-6205 {}}} SUCCS {{259 0 0-6212 {}}} CYCLES {}}
+set a(0-6212) {NAME FRAME:not#15 TYPE NOT PAR 0-6006 XREFS 37909 LOC {1 0.814901825 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6157 {}} {259 0 0-6211 {}}} SUCCS {{258 0 0-6224 {}}} CYCLES {}}
+set a(0-6213) {NAME FRAME:slc(acc.imod#5)#1 TYPE READSLICE PAR 0-6006 XREFS 37910 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {258 0 0-6205 {}}} SUCCS {{259 0 0-6214 {}}} CYCLES {}}
+set a(0-6214) {NAME FRAME:conc#24 TYPE CONCATENATE PAR 0-6006 XREFS 37911 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {259 0 0-6213 {}}} SUCCS {{258 0 0-6220 {}}} CYCLES {}}
+set a(0-6215) {NAME FRAME:slc(acc.imod#5)#2 TYPE READSLICE PAR 0-6006 XREFS 37912 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {258 0 0-6205 {}}} SUCCS {{259 0 0-6216 {}}} CYCLES {}}
+set a(0-6216) {NAME FRAME:not#13 TYPE NOT PAR 0-6006 XREFS 37913 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {259 0 0-6215 {}}} SUCCS {{258 0 0-6219 {}}} CYCLES {}}
+set a(0-6217) {NAME FRAME:slc(acc.imod#5) TYPE READSLICE PAR 0-6006 XREFS 37914 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {258 0 0-6205 {}}} SUCCS {{259 0 0-6218 {}}} CYCLES {}}
+set a(0-6218) {NAME FRAME:not#12 TYPE NOT PAR 0-6006 XREFS 37915 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {259 0 0-6217 {}}} SUCCS {{259 0 0-6219 {}}} CYCLES {}}
+set a(0-6219) {NAME FRAME:conc#25 TYPE CONCATENATE PAR 0-6006 XREFS 37916 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {258 0 0-6216 {}} {259 0 0-6218 {}}} SUCCS {{259 0 0-6220 {}}} CYCLES {}}
+set a(0-6220) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#23 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 37917 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 1 0.899096709496936 2 0.5481618594969361} PREDS {{146 0 0-6157 {}} {258 0 0-6214 {}} {259 0 0-6219 {}}} SUCCS {{259 0 0-6221 {}}} CYCLES {}}
+set a(0-6221) {NAME FRAME:slc#5 TYPE READSLICE PAR 0-6006 XREFS 37918 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6157 {}} {259 0 0-6220 {}}} SUCCS {{259 0 0-6222 {}}} CYCLES {}}
+set a(0-6222) {NAME FRAME:slc#3 TYPE READSLICE PAR 0-6006 XREFS 37919 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6157 {}} {259 0 0-6221 {}}} SUCCS {{259 0 0-6223 {}}} CYCLES {}}
+set a(0-6223) {NAME FRAME:not#16 TYPE NOT PAR 0-6006 XREFS 37920 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6157 {}} {259 0 0-6222 {}}} SUCCS {{259 0 0-6224 {}}} CYCLES {}}
+set a(0-6224) {NAME FRAME:conc#7 TYPE CONCATENATE PAR 0-6006 XREFS 37921 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6157 {}} {258 0 0-6212 {}} {259 0 0-6223 {}}} SUCCS {{258 0 0-6226 {}}} CYCLES {}}
+set a(0-6225) {NAME FRAME:slc(acc.imod#5)#5 TYPE READSLICE PAR 0-6006 XREFS 37922 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.5481619} PREDS {{146 0 0-6157 {}} {258 0 0-6205 {}}} SUCCS {{259 0 0-6226 {}}} CYCLES {}}
+set a(0-6226) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#17 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 37923 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 1 0.9466528770708271 2 0.5957180270708271} PREDS {{146 0 0-6157 {}} {258 0 0-6224 {}} {259 0 0-6225 {}}} SUCCS {{258 0 0-6229 {}}} CYCLES {}}
+set a(0-6227) {NAME green:slc(green#2.sg1)#10 TYPE READSLICE PAR 0-6006 XREFS 37924 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.595718075} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{259 0 0-6228 {}}} CYCLES {}}
+set a(0-6228) {NAME FRAME:not#14 TYPE NOT PAR 0-6006 XREFS 37925 LOC {1 0.591733675 1 0.946652925 1 0.946652925 2 0.595718075} PREDS {{146 0 0-6157 {}} {259 0 0-6227 {}}} SUCCS {{259 0 0-6229 {}}} CYCLES {}}
+set a(0-6229) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#18 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-6006 XREFS 37926 LOC {1 0.92105775 1 0.946652925 1 0.946652925 1 0.9999999451789505 2 0.6490650951789505} PREDS {{146 0 0-6157 {}} {258 0 0-6226 {}} {259 0 0-6228 {}}} SUCCS {{258 0 0-6232 {}}} CYCLES {}}
+set a(0-6230) {NAME FRAME:slc(acc.imod#5)#4 TYPE READSLICE PAR 0-6006 XREFS 37927 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.64906515} PREDS {{146 0 0-6157 {}} {258 0 0-6205 {}}} SUCCS {{259 0 0-6231 {}}} CYCLES {}}
+set a(0-6231) {NAME FRAME:conc#22 TYPE CONCATENATE PAR 0-6006 XREFS 37928 LOC {1 0.814901825 2 0.64906515 2 0.64906515 2 0.64906515} PREDS {{146 0 0-6157 {}} {259 0 0-6230 {}}} SUCCS {{259 0 0-6232 {}}} CYCLES {}}
+set a(0-6232) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#19 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 37929 LOC {2 0.0 2 0.64906515 2 0.64906515 2 0.707664859496936 2 0.707664859496936} PREDS {{146 0 0-6157 {}} {258 0 0-6229 {}} {259 0 0-6231 {}}} SUCCS {{259 0 0-6233 {}}} CYCLES {}}
+set a(0-6233) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#20 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-6006 XREFS 37930 LOC {2 0.05859975 2 0.7076648999999999 2 0.7076648999999999 2 0.7510048657468814 2 0.7510048657468814} PREDS {{146 0 0-6157 {}} {258 0 0-6210 {}} {259 0 0-6232 {}}} SUCCS {{259 0 0-6234 {}}} CYCLES {}}
+set a(0-6234) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#21 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-6006 XREFS 37931 LOC {2 0.101939775 2 0.7510049249999999 2 0.7510049249999999 2 0.8180332818650199 2 0.8180332818650199} PREDS {{146 0 0-6157 {}} {258 0 0-6209 {}} {259 0 0-6233 {}}} SUCCS {{259 0 0-6235 {}}} CYCLES {}}
+set a(0-6235) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,10,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME FRAME:acc#22 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-6006 XREFS 37932 LOC {2 0.168968175 2 0.8180333249999999 2 0.8180333249999999 2 0.8935106093138832 2 0.8935106093138832} PREDS {{146 0 0-6157 {}} {258 0 0-6207 {}} {259 0 0-6234 {}}} SUCCS {{258 0 0-6242 {}}} CYCLES {}}
+set a(0-6236) {NAME green:slc(green#2.sg1)#12 TYPE READSLICE PAR 0-6006 XREFS 37933 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.89351065} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{258 0 0-6240 {}}} CYCLES {}}
+set a(0-6237) {NAME green:slc(green#2.sg1)#13 TYPE READSLICE PAR 0-6006 XREFS 37934 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.89351065} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{259 0 0-6238 {}}} CYCLES {}}
+set a(0-6238) {NAME FRAME:exs#3 TYPE SIGNEXTEND PAR 0-6006 XREFS 37935 LOC {1 0.591733675 2 0.89351065 2 0.89351065 2 0.89351065} PREDS {{146 0 0-6157 {}} {259 0 0-6237 {}}} SUCCS {{258 0 0-6240 {}}} CYCLES {}}
+set a(0-6239) {NAME green:slc(green#2.sg1)#8 TYPE READSLICE PAR 0-6006 XREFS 37936 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.89351065} PREDS {{146 0 0-6157 {}} {258 0 0-6165 {}}} SUCCS {{259 0 0-6240 {}}} CYCLES {}}
+set a(0-6240) {NAME FRAME:conc#6 TYPE CONCATENATE PAR 0-6006 XREFS 37937 LOC {1 0.591733675 2 0.89351065 2 0.89351065 2 0.89351065} PREDS {{146 0 0-6157 {}} {258 0 0-6238 {}} {258 0 0-6236 {}} {259 0 0-6239 {}}} SUCCS {{259 0 0-6241 {}}} CYCLES {}}
+set a(0-6241) {NAME FRAME:exs#2 TYPE SIGNEXTEND PAR 0-6006 XREFS 37938 LOC {1 0.591733675 2 0.89351065 2 0.89351065 2 0.89351065} PREDS {{146 0 0-6157 {}} {259 0 0-6240 {}}} SUCCS {{259 0 0-6242 {}}} CYCLES {}}
+set a(0-6242) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,11,0,12) AREA_SCORE 13.23 QUANTITY 2 NAME FRAME:acc#3 TYPE ACCU DELAY {1.44 ns} LIBRARY_DELAY {1.44 ns} PAR 0-6006 XREFS 37939 LOC {2 0.24444549999999998 2 0.89351065 2 0.89351065 2 0.9832574816459019 2 0.9832574816459019} PREDS {{146 0 0-6157 {}} {258 0 0-6235 {}} {259 0 0-6241 {}}} SUCCS {{258 0 0-6334 {}} {258 0 0-6337 {}} {258 0 0-6338 {}}} CYCLES {}}
+set a(0-6243) {NAME blue:slc(blue#2.sg1)#4 TYPE READSLICE PAR 0-6006 XREFS 37940 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{258 0 0-6246 {}}} CYCLES {}}
+set a(0-6244) {NAME blue:slc(blue#2.sg1)#5 TYPE READSLICE PAR 0-6006 XREFS 37941 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{259 0 0-6245 {}}} CYCLES {}}
+set a(0-6245) {NAME FRAME:not#18 TYPE NOT PAR 0-6006 XREFS 37942 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {259 0 0-6244 {}}} SUCCS {{259 0 0-6246 {}}} CYCLES {}}
+set a(0-6246) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#25 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 37943 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.31395012707082715} PREDS {{146 0 0-6157 {}} {258 0 0-6243 {}} {259 0 0-6245 {}}} SUCCS {{258 0 0-6254 {}}} CYCLES {}}
+set a(0-6247) {NAME blue:slc(blue#2.sg1)#6 TYPE READSLICE PAR 0-6006 XREFS 37944 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{259 0 0-6248 {}}} CYCLES {}}
+set a(0-6248) {NAME FRAME:not#19 TYPE NOT PAR 0-6006 XREFS 37945 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {259 0 0-6247 {}}} SUCCS {{258 0 0-6251 {}}} CYCLES {}}
+set a(0-6249) {NAME blue:slc(blue#2.sg1)#7 TYPE READSLICE PAR 0-6006 XREFS 37946 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{259 0 0-6250 {}}} CYCLES {}}
+set a(0-6250) {NAME FRAME:not#27 TYPE NOT PAR 0-6006 XREFS 37947 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {259 0 0-6249 {}}} SUCCS {{259 0 0-6251 {}}} CYCLES {}}
+set a(0-6251) {NAME FRAME:conc#17 TYPE CONCATENATE PAR 0-6006 XREFS 37948 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {258 0 0-6248 {}} {259 0 0-6250 {}}} SUCCS {{258 0 0-6253 {}}} CYCLES {}}
+set a(0-6252) {NAME blue:slc(blue#2.sg1)#1 TYPE READSLICE PAR 0-6006 XREFS 37949 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.26639399999999996} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{259 0 0-6253 {}}} CYCLES {}}
+set a(0-6253) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#24 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 37950 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 1 0.664884977070827 2 0.31395012707082715} PREDS {{146 0 0-6157 {}} {258 0 0-6251 {}} {259 0 0-6252 {}}} SUCCS {{259 0 0-6254 {}}} CYCLES {}}
+set a(0-6254) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#27 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-6006 XREFS 37951 LOC {1 0.6392898499999999 1 0.664885025 1 0.664885025 1 0.7182320451789506 2 0.3672971951789505} PREDS {{146 0 0-6157 {}} {258 0 0-6246 {}} {259 0 0-6253 {}}} SUCCS {{258 0 0-6259 {}}} CYCLES {}}
+set a(0-6255) {NAME blue:slc(blue#2.sg1)#2 TYPE READSLICE PAR 0-6006 XREFS 37952 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.319741075} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{258 0 0-6258 {}}} CYCLES {}}
+set a(0-6256) {NAME blue:slc(blue#2.sg1)#3 TYPE READSLICE PAR 0-6006 XREFS 37953 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.319741075} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{259 0 0-6257 {}}} CYCLES {}}
+set a(0-6257) {NAME FRAME:not#17 TYPE NOT PAR 0-6006 XREFS 37954 LOC {1 0.591733675 1 0.670675925 1 0.670675925 2 0.319741075} PREDS {{146 0 0-6157 {}} {259 0 0-6256 {}}} SUCCS {{259 0 0-6258 {}}} CYCLES {}}
+set a(0-6258) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#26 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 37955 LOC {1 0.591733675 1 0.670675925 1 0.670675925 1 0.7182320520708271 2 0.36729720207082717} PREDS {{146 0 0-6157 {}} {258 0 0-6255 {}} {259 0 0-6257 {}}} SUCCS {{259 0 0-6259 {}}} CYCLES {}}
+set a(0-6259) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,4,0,6) AREA_SCORE 6.29 QUANTITY 3 NAME FRAME:acc#28 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 37956 LOC {1 0.692636925 1 0.7182320999999999 1 0.7182320999999999 1 0.7769849308637015 2 0.4260500808637015} PREDS {{146 0 0-6157 {}} {258 0 0-6254 {}} {259 0 0-6258 {}}} SUCCS {{259 0 0-6260 {}}} CYCLES {}}
+set a(0-6260) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,6,0,6) AREA_SCORE 7.28 QUANTITY 3 NAME acc#7 TYPE ACCU DELAY {1.02 ns} LIBRARY_DELAY {1.02 ns} PAR 0-6006 XREFS 37957 LOC {1 0.7513898 1 0.776984975 1 0.776984975 1 0.8404969484103024 2 0.4895620984103024} PREDS {{146 0 0-6157 {}} {259 0 0-6259 {}}} SUCCS {{258 0 0-6266 {}} {258 0 0-6268 {}} {258 0 0-6270 {}} {258 0 0-6272 {}} {258 0 0-6280 {}} {258 0 0-6285 {}}} CYCLES {}}
+set a(0-6261) {NAME blue:slc(blue#2.sg1)#9 TYPE READSLICE PAR 0-6006 XREFS 37958 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.6277733} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{259 0 0-6262 {}}} CYCLES {}}
+set a(0-6262) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#4 TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-6006 XREFS 37959 LOC {1 0.591733675 1 0.809739975 1 0.809739975 1 0.9999999562499999 2 0.81803328125} PREDS {{146 0 0-6157 {}} {259 0 0-6261 {}}} SUCCS {{258 0 0-6290 {}}} CYCLES {}}
+set a(0-6263) {NAME blue:slc(blue#2.sg1)#11 TYPE READSLICE PAR 0-6006 XREFS 37960 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.5731230749999999} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{259 0 0-6264 {}}} CYCLES {}}
+set a(0-6264) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#5 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-6006 XREFS 37961 LOC {1 0.591733675 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.7510048671744312} PREDS {{146 0 0-6157 {}} {259 0 0-6263 {}}} SUCCS {{258 0 0-6289 {}}} CYCLES {}}
+set a(0-6265) {NAME blue:slc(blue#2.sg1) TYPE READSLICE PAR 0-6006 XREFS 37962 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.7076648999999999} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{258 0 0-6288 {}}} CYCLES {}}
+set a(0-6266) {NAME FRAME:slc(acc.imod#7)#6 TYPE READSLICE PAR 0-6006 XREFS 37963 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.5481619} PREDS {{146 0 0-6157 {}} {258 0 0-6260 {}}} SUCCS {{259 0 0-6267 {}}} CYCLES {}}
+set a(0-6267) {NAME FRAME:not#23 TYPE NOT PAR 0-6006 XREFS 37964 LOC {1 0.814901825 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6157 {}} {259 0 0-6266 {}}} SUCCS {{258 0 0-6279 {}}} CYCLES {}}
+set a(0-6268) {NAME FRAME:slc(acc.imod#7)#1 TYPE READSLICE PAR 0-6006 XREFS 37965 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {258 0 0-6260 {}}} SUCCS {{259 0 0-6269 {}}} CYCLES {}}
+set a(0-6269) {NAME FRAME:conc#28 TYPE CONCATENATE PAR 0-6006 XREFS 37966 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {259 0 0-6268 {}}} SUCCS {{258 0 0-6275 {}}} CYCLES {}}
+set a(0-6270) {NAME FRAME:slc(acc.imod#7)#2 TYPE READSLICE PAR 0-6006 XREFS 37967 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {258 0 0-6260 {}}} SUCCS {{259 0 0-6271 {}}} CYCLES {}}
+set a(0-6271) {NAME FRAME:not#21 TYPE NOT PAR 0-6006 XREFS 37968 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {259 0 0-6270 {}}} SUCCS {{258 0 0-6274 {}}} CYCLES {}}
+set a(0-6272) {NAME FRAME:slc(acc.imod#7) TYPE READSLICE PAR 0-6006 XREFS 37969 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {258 0 0-6260 {}}} SUCCS {{259 0 0-6273 {}}} CYCLES {}}
+set a(0-6273) {NAME FRAME:not#20 TYPE NOT PAR 0-6006 XREFS 37970 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {259 0 0-6272 {}}} SUCCS {{259 0 0-6274 {}}} CYCLES {}}
+set a(0-6274) {NAME FRAME:conc#29 TYPE CONCATENATE PAR 0-6006 XREFS 37971 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.48956215} PREDS {{146 0 0-6157 {}} {258 0 0-6271 {}} {259 0 0-6273 {}}} SUCCS {{259 0 0-6275 {}}} CYCLES {}}
+set a(0-6275) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#35 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 37972 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 1 0.899096709496936 2 0.5481618594969361} PREDS {{146 0 0-6157 {}} {258 0 0-6269 {}} {259 0 0-6274 {}}} SUCCS {{259 0 0-6276 {}}} CYCLES {}}
+set a(0-6276) {NAME FRAME:slc#6 TYPE READSLICE PAR 0-6006 XREFS 37973 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6157 {}} {259 0 0-6275 {}}} SUCCS {{259 0 0-6277 {}}} CYCLES {}}
+set a(0-6277) {NAME FRAME:slc#4 TYPE READSLICE PAR 0-6006 XREFS 37974 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6157 {}} {259 0 0-6276 {}}} SUCCS {{259 0 0-6278 {}}} CYCLES {}}
+set a(0-6278) {NAME FRAME:not#24 TYPE NOT PAR 0-6006 XREFS 37975 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6157 {}} {259 0 0-6277 {}}} SUCCS {{259 0 0-6279 {}}} CYCLES {}}
+set a(0-6279) {NAME FRAME:conc#11 TYPE CONCATENATE PAR 0-6006 XREFS 37976 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.5481619} PREDS {{146 0 0-6157 {}} {258 0 0-6267 {}} {259 0 0-6278 {}}} SUCCS {{258 0 0-6281 {}}} CYCLES {}}
+set a(0-6280) {NAME FRAME:slc(acc.imod#7)#5 TYPE READSLICE PAR 0-6006 XREFS 37977 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.5481619} PREDS {{146 0 0-6157 {}} {258 0 0-6260 {}}} SUCCS {{259 0 0-6281 {}}} CYCLES {}}
+set a(0-6281) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#29 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 37978 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 1 0.9466528770708271 2 0.5957180270708271} PREDS {{146 0 0-6157 {}} {258 0 0-6279 {}} {259 0 0-6280 {}}} SUCCS {{258 0 0-6284 {}}} CYCLES {}}
+set a(0-6282) {NAME blue:slc(blue#2.sg1)#10 TYPE READSLICE PAR 0-6006 XREFS 37979 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.595718075} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{259 0 0-6283 {}}} CYCLES {}}
+set a(0-6283) {NAME FRAME:not#22 TYPE NOT PAR 0-6006 XREFS 37980 LOC {1 0.591733675 1 0.946652925 1 0.946652925 2 0.595718075} PREDS {{146 0 0-6157 {}} {259 0 0-6282 {}}} SUCCS {{259 0 0-6284 {}}} CYCLES {}}
+set a(0-6284) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#30 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-6006 XREFS 37981 LOC {1 0.92105775 1 0.946652925 1 0.946652925 1 0.9999999451789505 2 0.6490650951789505} PREDS {{146 0 0-6157 {}} {258 0 0-6281 {}} {259 0 0-6283 {}}} SUCCS {{258 0 0-6287 {}}} CYCLES {}}
+set a(0-6285) {NAME FRAME:slc(acc.imod#7)#4 TYPE READSLICE PAR 0-6006 XREFS 37982 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.64906515} PREDS {{146 0 0-6157 {}} {258 0 0-6260 {}}} SUCCS {{259 0 0-6286 {}}} CYCLES {}}
+set a(0-6286) {NAME FRAME:conc#26 TYPE CONCATENATE PAR 0-6006 XREFS 37983 LOC {1 0.814901825 2 0.64906515 2 0.64906515 2 0.64906515} PREDS {{146 0 0-6157 {}} {259 0 0-6285 {}}} SUCCS {{259 0 0-6287 {}}} CYCLES {}}
+set a(0-6287) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#31 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 37984 LOC {2 0.0 2 0.64906515 2 0.64906515 2 0.707664859496936 2 0.707664859496936} PREDS {{146 0 0-6157 {}} {258 0 0-6284 {}} {259 0 0-6286 {}}} SUCCS {{259 0 0-6288 {}}} CYCLES {}}
+set a(0-6288) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#32 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-6006 XREFS 37985 LOC {2 0.05859975 2 0.7076648999999999 2 0.7076648999999999 2 0.7510048657468814 2 0.7510048657468814} PREDS {{146 0 0-6157 {}} {258 0 0-6265 {}} {259 0 0-6287 {}}} SUCCS {{259 0 0-6289 {}}} CYCLES {}}
+set a(0-6289) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#33 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-6006 XREFS 37986 LOC {2 0.101939775 2 0.7510049249999999 2 0.7510049249999999 2 0.8180332818650199 2 0.8180332818650199} PREDS {{146 0 0-6157 {}} {258 0 0-6264 {}} {259 0 0-6288 {}}} SUCCS {{259 0 0-6290 {}}} CYCLES {}}
+set a(0-6290) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(11,0,10,1,12) AREA_SCORE 12.00 QUANTITY 2 NAME FRAME:acc#34 TYPE ACCU DELAY {1.21 ns} LIBRARY_DELAY {1.21 ns} PAR 0-6006 XREFS 37987 LOC {2 0.168968175 2 0.8180333249999999 2 0.8180333249999999 2 0.8935106093138832 2 0.8935106093138832} PREDS {{146 0 0-6157 {}} {258 0 0-6262 {}} {259 0 0-6289 {}}} SUCCS {{258 0 0-6297 {}}} CYCLES {}}
+set a(0-6291) {NAME blue:slc(blue#2.sg1)#12 TYPE READSLICE PAR 0-6006 XREFS 37988 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.89351065} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{258 0 0-6295 {}}} CYCLES {}}
+set a(0-6292) {NAME blue:slc(blue#2.sg1)#13 TYPE READSLICE PAR 0-6006 XREFS 37989 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.89351065} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{259 0 0-6293 {}}} CYCLES {}}
+set a(0-6293) {NAME FRAME:exs#5 TYPE SIGNEXTEND PAR 0-6006 XREFS 37990 LOC {1 0.591733675 2 0.89351065 2 0.89351065 2 0.89351065} PREDS {{146 0 0-6157 {}} {259 0 0-6292 {}}} SUCCS {{258 0 0-6295 {}}} CYCLES {}}
+set a(0-6294) {NAME blue:slc(blue#2.sg1)#8 TYPE READSLICE PAR 0-6006 XREFS 37991 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.89351065} PREDS {{146 0 0-6157 {}} {258 0 0-6169 {}}} SUCCS {{259 0 0-6295 {}}} CYCLES {}}
+set a(0-6295) {NAME FRAME:conc#10 TYPE CONCATENATE PAR 0-6006 XREFS 37992 LOC {1 0.591733675 2 0.89351065 2 0.89351065 2 0.89351065} PREDS {{146 0 0-6157 {}} {258 0 0-6293 {}} {258 0 0-6291 {}} {259 0 0-6294 {}}} SUCCS {{259 0 0-6296 {}}} CYCLES {}}
+set a(0-6296) {NAME FRAME:exs#4 TYPE SIGNEXTEND PAR 0-6006 XREFS 37993 LOC {1 0.591733675 2 0.89351065 2 0.89351065 2 0.89351065} PREDS {{146 0 0-6157 {}} {259 0 0-6295 {}}} SUCCS {{259 0 0-6297 {}}} CYCLES {}}
+set a(0-6297) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(12,0,11,0,12) AREA_SCORE 13.23 QUANTITY 2 NAME FRAME:acc#4 TYPE ACCU DELAY {1.44 ns} LIBRARY_DELAY {1.44 ns} PAR 0-6006 XREFS 37994 LOC {2 0.24444549999999998 2 0.89351065 2 0.89351065 2 0.9832574816459019 2 0.9832574816459019} PREDS {{146 0 0-6157 {}} {258 0 0-6290 {}} {259 0 0-6296 {}}} SUCCS {{258 0 0-6339 {}} {258 0 0-6342 {}}} CYCLES {}}
+set a(0-6298) {NAME red:slc(red#2.sg1)#13 TYPE READSLICE PAR 0-6006 XREFS 37995 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.63020875} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{259 0 0-6299 {}}} CYCLES {}}
+set a(0-6299) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,0,9,0,11) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul TYPE MUL DELAY {3.04 ns} LIBRARY_DELAY {3.04 ns} PAR 0-6006 XREFS 37996 LOC {1 0.591733675 1 0.7282905 1 0.7282905 1 0.9185504812499999 2 0.82046873125} PREDS {{146 0 0-6157 {}} {259 0 0-6298 {}}} SUCCS {{258 0 0-6305 {}}} CYCLES {}}
+set a(0-6300) {NAME red:slc(red#2.sg1)#11 TYPE READSLICE PAR 0-6006 XREFS 37997 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.8204687749999999} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{258 0 0-6304 {}}} CYCLES {}}
+set a(0-6301) {NAME red:slc(red#2.sg1)#12 TYPE READSLICE PAR 0-6006 XREFS 37998 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.8204687749999999} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{259 0 0-6302 {}}} CYCLES {}}
+set a(0-6302) {NAME FRAME:exs#1 TYPE SIGNEXTEND PAR 0-6006 XREFS 37999 LOC {1 0.591733675 1 0.918550525 1 0.918550525 2 0.8204687749999999} PREDS {{146 0 0-6157 {}} {259 0 0-6301 {}}} SUCCS {{258 0 0-6304 {}}} CYCLES {}}
+set a(0-6303) {NAME red:slc(red#2.sg1)#8 TYPE READSLICE PAR 0-6006 XREFS 38000 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.8204687749999999} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{259 0 0-6304 {}}} CYCLES {}}
+set a(0-6304) {NAME FRAME:conc#2 TYPE CONCATENATE PAR 0-6006 XREFS 38001 LOC {1 0.591733675 1 0.918550525 1 0.918550525 2 0.8204687749999999} PREDS {{146 0 0-6157 {}} {258 0 0-6302 {}} {258 0 0-6300 {}} {259 0 0-6303 {}}} SUCCS {{259 0 0-6305 {}}} CYCLES {}}
+set a(0-6305) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,9,1,10) AREA_SCORE 11.00 QUANTITY 1 NAME FRAME:acc#41 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-6006 XREFS 38002 LOC {1 0.7819937 1 0.918550525 1 0.918550525 1 0.9999999444798112 2 0.9019181944798111} PREDS {{146 0 0-6157 {}} {258 0 0-6299 {}} {259 0 0-6304 {}}} SUCCS {{258 0 0-6333 {}}} CYCLES {}}
+set a(0-6306) {NAME red:slc(red#2.sg1)#10 TYPE READSLICE PAR 0-6006 XREFS 38003 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.6570079999999999} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{259 0 0-6307 {}}} CYCLES {}}
+set a(0-6307) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(3,0,6,0,9) AREA_SCORE 330.25 QUANTITY 3 NAME FRAME:mul#1 TYPE MUL DELAY {2.85 ns} LIBRARY_DELAY {2.85 ns} PAR 0-6006 XREFS 38004 LOC {1 0.591733675 1 0.82211815 1 0.82211815 1 0.9999999421744312 2 0.8348897921744312} PREDS {{146 0 0-6157 {}} {259 0 0-6306 {}}} SUCCS {{258 0 0-6332 {}}} CYCLES {}}
+set a(0-6308) {NAME red:slc(red#2.sg1) TYPE READSLICE PAR 0-6006 XREFS 38005 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.7915498249999999} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{258 0 0-6331 {}}} CYCLES {}}
+set a(0-6309) {NAME FRAME:slc(acc.imod#3)#6 TYPE READSLICE PAR 0-6006 XREFS 38006 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.632046825} PREDS {{146 0 0-6157 {}} {258 0 0-6187 {}}} SUCCS {{259 0 0-6310 {}}} CYCLES {}}
+set a(0-6310) {NAME FRAME:not#7 TYPE NOT PAR 0-6006 XREFS 38007 LOC {1 0.814901825 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-6157 {}} {259 0 0-6309 {}}} SUCCS {{258 0 0-6322 {}}} CYCLES {}}
+set a(0-6311) {NAME FRAME:slc(acc.imod#3)#1 TYPE READSLICE PAR 0-6006 XREFS 38008 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6157 {}} {258 0 0-6187 {}}} SUCCS {{259 0 0-6312 {}}} CYCLES {}}
+set a(0-6312) {NAME FRAME:conc#32 TYPE CONCATENATE PAR 0-6006 XREFS 38009 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6157 {}} {259 0 0-6311 {}}} SUCCS {{258 0 0-6318 {}}} CYCLES {}}
+set a(0-6313) {NAME FRAME:slc(acc.imod#3)#2 TYPE READSLICE PAR 0-6006 XREFS 38010 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6157 {}} {258 0 0-6187 {}}} SUCCS {{259 0 0-6314 {}}} CYCLES {}}
+set a(0-6314) {NAME FRAME:not#5 TYPE NOT PAR 0-6006 XREFS 38011 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6157 {}} {259 0 0-6313 {}}} SUCCS {{258 0 0-6317 {}}} CYCLES {}}
+set a(0-6315) {NAME FRAME:slc(acc.imod#3) TYPE READSLICE PAR 0-6006 XREFS 38012 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6157 {}} {258 0 0-6187 {}}} SUCCS {{259 0 0-6316 {}}} CYCLES {}}
+set a(0-6316) {NAME FRAME:not#4 TYPE NOT PAR 0-6006 XREFS 38013 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6157 {}} {259 0 0-6315 {}}} SUCCS {{259 0 0-6317 {}}} CYCLES {}}
+set a(0-6317) {NAME FRAME:conc#33 TYPE CONCATENATE PAR 0-6006 XREFS 38014 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.573447075} PREDS {{146 0 0-6157 {}} {258 0 0-6314 {}} {259 0 0-6316 {}}} SUCCS {{259 0 0-6318 {}}} CYCLES {}}
+set a(0-6318) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#42 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 38015 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 1 0.899096709496936 2 0.6320467844969361} PREDS {{146 0 0-6157 {}} {258 0 0-6312 {}} {259 0 0-6317 {}}} SUCCS {{259 0 0-6319 {}}} CYCLES {}}
+set a(0-6319) {NAME FRAME:slc#7 TYPE READSLICE PAR 0-6006 XREFS 38016 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-6157 {}} {259 0 0-6318 {}}} SUCCS {{259 0 0-6320 {}}} CYCLES {}}
+set a(0-6320) {NAME FRAME:slc#2 TYPE READSLICE PAR 0-6006 XREFS 38017 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-6157 {}} {259 0 0-6319 {}}} SUCCS {{259 0 0-6321 {}}} CYCLES {}}
+set a(0-6321) {NAME FRAME:not#8 TYPE NOT PAR 0-6006 XREFS 38018 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-6157 {}} {259 0 0-6320 {}}} SUCCS {{259 0 0-6322 {}}} CYCLES {}}
+set a(0-6322) {NAME FRAME:conc#3 TYPE CONCATENATE PAR 0-6006 XREFS 38019 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 2 0.632046825} PREDS {{146 0 0-6157 {}} {258 0 0-6310 {}} {259 0 0-6321 {}}} SUCCS {{258 0 0-6324 {}}} CYCLES {}}
+set a(0-6323) {NAME FRAME:slc(acc.imod#3)#5 TYPE READSLICE PAR 0-6006 XREFS 38020 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.632046825} PREDS {{146 0 0-6157 {}} {258 0 0-6187 {}}} SUCCS {{259 0 0-6324 {}}} CYCLES {}}
+set a(0-6324) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,4) AREA_SCORE 4.30 QUANTITY 12 NAME FRAME:acc#36 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 38021 LOC {1 0.8735015749999999 1 0.89909675 1 0.89909675 1 0.9466528770708271 2 0.6796029520708271} PREDS {{146 0 0-6157 {}} {258 0 0-6322 {}} {259 0 0-6323 {}}} SUCCS {{258 0 0-6327 {}}} CYCLES {}}
+set a(0-6325) {NAME red:slc(red#2.sg1)#9 TYPE READSLICE PAR 0-6006 XREFS 38022 LOC {1 0.591733675 1 0.6173288499999999 1 0.6173288499999999 2 0.679603} PREDS {{146 0 0-6157 {}} {258 0 0-6161 {}}} SUCCS {{259 0 0-6326 {}}} CYCLES {}}
+set a(0-6326) {NAME FRAME:not#6 TYPE NOT PAR 0-6006 XREFS 38023 LOC {1 0.591733675 1 0.946652925 1 0.946652925 2 0.679603} PREDS {{146 0 0-6157 {}} {259 0 0-6325 {}}} SUCCS {{259 0 0-6327 {}}} CYCLES {}}
+set a(0-6327) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,4,0,5) AREA_SCORE 5.29 QUANTITY 6 NAME FRAME:acc#37 TYPE ACCU DELAY {0.85 ns} LIBRARY_DELAY {0.85 ns} PAR 0-6006 XREFS 38024 LOC {1 0.92105775 1 0.946652925 1 0.946652925 1 0.9999999451789505 2 0.7329500201789505} PREDS {{146 0 0-6157 {}} {258 0 0-6324 {}} {259 0 0-6326 {}}} SUCCS {{258 0 0-6330 {}}} CYCLES {}}
+set a(0-6328) {NAME FRAME:slc(acc.imod#3)#4 TYPE READSLICE PAR 0-6006 XREFS 38025 LOC {1 0.814901825 1 0.8404969999999999 1 0.8404969999999999 2 0.732950075} PREDS {{146 0 0-6157 {}} {258 0 0-6187 {}}} SUCCS {{259 0 0-6329 {}}} CYCLES {}}
+set a(0-6329) {NAME FRAME:conc#30 TYPE CONCATENATE PAR 0-6006 XREFS 38026 LOC {1 0.814901825 2 0.732950075 2 0.732950075 2 0.732950075} PREDS {{146 0 0-6157 {}} {259 0 0-6328 {}}} SUCCS {{259 0 0-6330 {}}} CYCLES {}}
+set a(0-6330) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(5,0,5,0,5) AREA_SCORE 6.28 QUANTITY 6 NAME FRAME:acc#38 TYPE ACCU DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 38027 LOC {2 0.0 2 0.732950075 2 0.732950075 2 0.791549784496936 2 0.791549784496936} PREDS {{146 0 0-6157 {}} {258 0 0-6327 {}} {259 0 0-6329 {}}} SUCCS {{259 0 0-6331 {}}} CYCLES {}}
+set a(0-6331) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(6,0,5,1,8) AREA_SCORE 7.00 QUANTITY 3 NAME FRAME:acc#39 TYPE ACCU DELAY {0.69 ns} LIBRARY_DELAY {0.69 ns} PAR 0-6006 XREFS 38028 LOC {2 0.05859975 2 0.7915498249999999 2 0.7915498249999999 2 0.8348897907468814 2 0.8348897907468814} PREDS {{146 0 0-6157 {}} {258 0 0-6308 {}} {259 0 0-6330 {}}} SUCCS {{259 0 0-6332 {}}} CYCLES {}}
+set a(0-6332) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(9,0,8,1,10) AREA_SCORE 10.00 QUANTITY 3 NAME FRAME:acc#40 TYPE ACCU DELAY {1.07 ns} LIBRARY_DELAY {1.07 ns} PAR 0-6006 XREFS 38029 LOC {2 0.101939775 2 0.8348898499999999 2 0.8348898499999999 2 0.9019182068650199 2 0.9019182068650199} PREDS {{146 0 0-6157 {}} {258 0 0-6307 {}} {259 0 0-6331 {}}} SUCCS {{259 0 0-6333 {}}} CYCLES {}}
+set a(0-6333) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(10,0,10,0,10) AREA_SCORE 11.24 QUANTITY 1 NAME FRAME:acc#2 TYPE ACCU DELAY {1.30 ns} LIBRARY_DELAY {1.30 ns} PAR 0-6006 XREFS 38030 LOC {2 0.168968175 2 0.9019182499999999 2 0.9019182499999999 2 0.9832574783364112 2 0.9832574783364112} PREDS {{146 0 0-6157 {}} {258 0 0-6305 {}} {259 0 0-6332 {}}} SUCCS {{258 0 0-6336 {}}} CYCLES {}}
+set a(0-6334) {NAME green:slc(green) TYPE READSLICE PAR 0-6006 XREFS 38031 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-6157 {}} {258 0 0-6242 {}}} SUCCS {{259 0 0-6335 {}}} CYCLES {}}
+set a(0-6335) {NAME FRAME:exu TYPE PADZEROES PAR 0-6006 XREFS 38032 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-6157 {}} {259 0 0-6334 {}}} SUCCS {{259 0 0-6336 {}}} CYCLES {}}
+set a(0-6336) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(10,2) AREA_SCORE 7.30 QUANTITY 1 NAME FRAME:or TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-6006 XREFS 38033 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{146 0 0-6157 {}} {258 0 0-6333 {}} {259 0 0-6335 {}}} SUCCS {{258 0 0-6343 {}}} CYCLES {}}
+set a(0-6337) {NAME green:slc(green)#1 TYPE READSLICE PAR 0-6006 XREFS 38034 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 1.0} PREDS {{146 0 0-6157 {}} {258 0 0-6242 {}}} SUCCS {{258 0 0-6343 {}}} CYCLES {}}
+set a(0-6338) {NAME green:slc(green)#2 TYPE READSLICE PAR 0-6006 XREFS 38035 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-6157 {}} {258 0 0-6242 {}}} SUCCS {{258 0 0-6341 {}}} CYCLES {}}
+set a(0-6339) {NAME blue:slc(blue) TYPE READSLICE PAR 0-6006 XREFS 38036 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-6157 {}} {258 0 0-6297 {}}} SUCCS {{259 0 0-6340 {}}} CYCLES {}}
+set a(0-6340) {NAME FRAME:exu#10 TYPE PADZEROES PAR 0-6006 XREFS 38037 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.983257525} PREDS {{146 0 0-6157 {}} {259 0 0-6339 {}}} SUCCS {{259 0 0-6341 {}}} CYCLES {}}
+set a(0-6341) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(6,2) AREA_SCORE 4.38 QUANTITY 1 NAME FRAME:or#3 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-6006 XREFS 38038 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 0.9999999561077388 2 0.9999999561077388} PREDS {{146 0 0-6157 {}} {258 0 0-6338 {}} {259 0 0-6340 {}}} SUCCS {{258 0 0-6343 {}}} CYCLES {}}
+set a(0-6342) {NAME blue:slc(blue)#1 TYPE READSLICE PAR 0-6006 XREFS 38039 LOC {2 0.334192375 2 0.983257525 2 0.983257525 2 1.0} PREDS {{146 0 0-6157 {}} {258 0 0-6297 {}}} SUCCS {{259 0 0-6343 {}}} CYCLES {}}
+set a(0-6343) {NAME FRAME:conc#21 TYPE CONCATENATE PAR 0-6006 XREFS 38040 LOC {2 0.35093484999999996 2 1.0 2 1.0 2 1.0} PREDS {{146 0 0-6157 {}} {258 0 0-6341 {}} {258 0 0-6337 {}} {258 0 0-6336 {}} {259 0 0-6342 {}}} SUCCS {{259 0 0-6344 {}}} CYCLES {}}
+set a(0-6344) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(2,30) AREA_SCORE 0.00 QUANTITY 1 NAME FRAME:io_write(vout:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-6006 XREFS 38041 LOC {2 1.0 2 1.0 2 1.0 3 0.0 2 0.9999} PREDS {{130 0 0-6157 {}} {260 0 0-6344 {}} {259 0 0-6343 {}}} SUCCS {{260 0 0-6344 {}}} CYCLES {}}
+set a(0-6345) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(19,0,2,1,19) AREA_SCORE 20.00 QUANTITY 1 NAME FRAME:acc#6 TYPE ACCU DELAY {1.91 ns} LIBRARY_DELAY {1.91 ns} PAR 0-6006 XREFS 38042 LOC {1 0.088339225 1 0.738743625 1 0.738743625 1 0.8580029410815966 2 0.4774888160815965} PREDS {{146 0 0-6157 {}} {258 0 0-6035 {}}} SUCCS {{259 0 0-6346 {}} {258 0 0-6470 {}}} CYCLES {}}
+set a(0-6346) {NAME FRAME:p:slc(FRAME:p)#1 TYPE READSLICE PAR 0-6006 XREFS 38043 LOC {1 0.2075986 1 0.858003 1 0.858003 2 0.477488875} PREDS {{146 0 0-6157 {}} {259 0 0-6345 {}}} SUCCS {{259 0 0-6347 {}}} CYCLES {}}
+set a(0-6347) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,7,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME FRAME:acc TYPE ACCU DELAY {1.17 ns} LIBRARY_DELAY {1.17 ns} PAR 0-6006 XREFS 38044 LOC {1 0.2075986 1 0.858003 1 0.858003 1 0.9308181617915235 2 0.5503040367915236} PREDS {{146 0 0-6157 {}} {259 0 0-6346 {}}} SUCCS {{259 0 0-6348 {}}} CYCLES {}}
+set a(0-6348) {NAME FRAME:slc TYPE READSLICE PAR 0-6006 XREFS 38045 LOC {1 0.2804138 1 0.9308181999999999 1 0.9308181999999999 2 0.550304075} PREDS {{146 0 0-6157 {}} {259 0 0-6347 {}}} SUCCS {{259 0 0-6349 {}}} CYCLES {}}
+set a(0-6349) {NAME FRAME:not TYPE NOT PAR 0-6006 XREFS 38046 LOC {1 0.2804138 1 0.9308181999999999 1 0.9308181999999999 2 0.550304075} PREDS {{146 0 0-6157 {}} {259 0 0-6348 {}}} SUCCS {{259 0 0-6454 {}}} CYCLES {}}
+set a(0-6350) {NAME slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-6006 XREFS 38047 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.6843317999999999} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}}} SUCCS {{258 0 0-6360 {}}} CYCLES {}}
+set a(0-6351) {NAME slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-6006 XREFS 38048 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.667925025} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}}} SUCCS {{258 0 0-6355 {}}} CYCLES {}}
+set a(0-6352) {NAME slc(i#6.lpi#1.dfm)#2 TYPE READSLICE PAR 0-6006 XREFS 38049 LOC {1 0.016406775 1 0.607678775 1 0.607678775 3 1.0} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}}} SUCCS {} CYCLES {}}
+set a(0-6353) {NAME slc(i#6.lpi#1.dfm)#3 TYPE READSLICE PAR 0-6006 XREFS 38050 LOC {1 0.016406775 1 0.607678775 1 0.607678775 3 1.0} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}}} SUCCS {} CYCLES {}}
+set a(0-6354) {NAME FRAME:for:slc(i#6.lpi#1.dfm) TYPE READSLICE PAR 0-6006 XREFS 38051 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.667925025} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}}} SUCCS {{258 0 0-6356 {}}} CYCLES {}}
+set a(0-6355) {NAME FRAME:for:not#1 TYPE NOT PAR 0-6006 XREFS 38052 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.667925025} PREDS {{146 0 0-6081 {}} {258 0 0-6351 {}}} SUCCS {{259 0 0-6356 {}}} CYCLES {}}
+set a(0-6356) {NAME FRAME:for:nand#2 TYPE NAND PAR 0-6006 XREFS 38053 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.667925025} PREDS {{146 0 0-6081 {}} {258 0 0-6354 {}} {259 0 0-6355 {}}} SUCCS {{259 0 0-6357 {}}} CYCLES {}}
+set a(0-6357) {NAME FRAME:for:exs#31 TYPE SIGNEXTEND PAR 0-6006 XREFS 38054 LOC {1 0.016406775 1 0.644864425 1 0.644864425 2 0.667925025} PREDS {{146 0 0-6081 {}} {259 0 0-6356 {}}} SUCCS {{259 0 0-6358 {}}} CYCLES {}}
+set a(0-6358) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 6 NAME FRAME:for:and#16 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 38055 LOC {1 0.016406775 1 0.644864425 1 0.644864425 1 0.6612711562638539 2 0.6843317562638539} PREDS {{146 0 0-6081 {}} {259 0 0-6357 {}}} SUCCS {{258 0 0-6362 {}}} CYCLES {}}
+set a(0-6359) {NAME FRAME:for:slc(i#6.lpi#1.dfm)#1 TYPE READSLICE PAR 0-6006 XREFS 38056 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.6843317999999999} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}}} SUCCS {{259 0 0-6360 {}}} CYCLES {}}
+set a(0-6360) {NAME FRAME:for:nor TYPE NOR PAR 0-6006 XREFS 38057 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.6843317999999999} PREDS {{146 0 0-6081 {}} {258 0 0-6350 {}} {259 0 0-6359 {}}} SUCCS {{259 0 0-6361 {}}} CYCLES {}}
+set a(0-6361) {NAME FRAME:for:exs#32 TYPE SIGNEXTEND PAR 0-6006 XREFS 38058 LOC {1 0.016406775 1 0.6612712 1 0.6612712 2 0.6843317999999999} PREDS {{146 0 0-6081 {}} {259 0 0-6360 {}}} SUCCS {{259 0 0-6362 {}}} CYCLES {}}
+set a(0-6362) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(2,2) AREA_SCORE 1.46 QUANTITY 4 NAME FRAME:for:or TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-6006 XREFS 38059 LOC {1 0.03281355 1 0.6612712 1 0.6612712 1 0.6780136311077388 2 0.7010742311077388} PREDS {{146 0 0-6081 {}} {258 0 0-6358 {}} {259 0 0-6361 {}}} SUCCS {{258 0 0-6367 {}} {258 0 0-6373 {}} {258 0 0-6379 {}}} CYCLES {}}
+set a(0-6363) {NAME {regs.operator[]#6:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 38060 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6366 {}}} CYCLES {}}
+set a(0-6364) {NAME {regs.operator[]#6:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 38061 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6366 {}}} CYCLES {}}
+set a(0-6365) {NAME {regs.operator[]#6:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 38062 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6366 {}}} CYCLES {}}
+set a(0-6366) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#6:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 38063 LOC {1 0.0230606 1 0.619485875 1 0.619485875 1 0.678013625 2 0.7010742249999999} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}} {258 0 0-6364 {}} {258 0 0-6363 {}} {259 0 0-6365 {}}} SUCCS {{259 0 0-6367 {}}} CYCLES {}}
+set a(0-6367) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 38064 LOC {1 0.08158839999999999 1 0.678013675 1 0.678013675 1 0.8709375374999999 2 0.8939981374999999} PREDS {{146 0 0-6081 {}} {258 0 0-6362 {}} {259 0 0-6366 {}}} SUCCS {{259 0 0-6368 {}}} CYCLES {}}
+set a(0-6368) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for:acc#1 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6006 XREFS 38065 LOC {1 0.274512325 1 0.8709376 1 0.8709376 1 0.9769393413378799 2 0.9999999413378798} PREDS {{146 0 0-6081 {}} {258 0 0-6049 {}} {259 0 0-6367 {}}} SUCCS {{258 0 0-6463 {}}} CYCLES {}}
+set a(0-6369) {NAME {regs.operator[]#7:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 38066 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6372 {}}} CYCLES {}}
+set a(0-6370) {NAME {regs.operator[]#7:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 38067 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6372 {}}} CYCLES {}}
+set a(0-6371) {NAME {regs.operator[]#7:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 38068 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6372 {}}} CYCLES {}}
+set a(0-6372) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#7:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 38069 LOC {1 0.0230606 1 0.619485875 1 0.619485875 1 0.678013625 2 0.7010742249999999} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}} {258 0 0-6370 {}} {258 0 0-6369 {}} {259 0 0-6371 {}}} SUCCS {{259 0 0-6373 {}}} CYCLES {}}
+set a(0-6373) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#1 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 38070 LOC {1 0.08158839999999999 1 0.678013675 1 0.678013675 1 0.8709375374999999 2 0.8939981374999999} PREDS {{146 0 0-6081 {}} {258 0 0-6362 {}} {259 0 0-6372 {}}} SUCCS {{259 0 0-6374 {}}} CYCLES {}}
+set a(0-6374) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for:acc#2 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6006 XREFS 38071 LOC {1 0.274512325 1 0.8709376 1 0.8709376 1 0.9769393413378799 2 0.9999999413378798} PREDS {{146 0 0-6081 {}} {258 0 0-6055 {}} {259 0 0-6373 {}}} SUCCS {{258 0 0-6465 {}}} CYCLES {}}
+set a(0-6375) {NAME {regs.operator[]#8:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 38072 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6378 {}}} CYCLES {}}
+set a(0-6376) {NAME {regs.operator[]#8:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 38073 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6378 {}}} CYCLES {}}
+set a(0-6377) {NAME {regs.operator[]#8:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 38074 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.642546475} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6378 {}}} CYCLES {}}
+set a(0-6378) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#8:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 38075 LOC {1 0.0230606 1 0.619485875 1 0.619485875 1 0.678013625 2 0.7010742249999999} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}} {258 0 0-6376 {}} {258 0 0-6375 {}} {259 0 0-6377 {}}} SUCCS {{259 0 0-6379 {}}} CYCLES {}}
+set a(0-6379) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#2 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 38076 LOC {1 0.08158839999999999 1 0.678013675 1 0.678013675 1 0.8709375374999999 2 0.8939981374999999} PREDS {{146 0 0-6081 {}} {258 0 0-6362 {}} {259 0 0-6378 {}}} SUCCS {{259 0 0-6380 {}}} CYCLES {}}
+set a(0-6380) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for:acc#3 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6006 XREFS 38077 LOC {1 0.274512325 1 0.8709376 1 0.8709376 1 0.9769393413378799 2 0.9999999413378798} PREDS {{146 0 0-6081 {}} {258 0 0-6061 {}} {259 0 0-6379 {}}} SUCCS {{258 0 0-6467 {}}} CYCLES {}}
+set a(0-6381) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,1,1,2) AREA_SCORE 3.00 QUANTITY 1 NAME FRAME:for:acc#5 TYPE ACCU DELAY {0.66 ns} LIBRARY_DELAY {0.66 ns} PAR 0-6006 XREFS 38078 LOC {1 0.016406775 1 0.607678775 1 0.607678775 1 0.6487862160227986 2 0.6718468160227986} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}}} SUCCS {{259 0 0-6382 {}} {258 0 0-6383 {}} {258 0 0-6387 {}} {258 0 0-6388 {}}} CYCLES {}}
+set a(0-6382) {NAME FRAME:for:slc(FRAME:for:acc#5.tmp) TYPE READSLICE PAR 0-6006 XREFS 38079 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.671846875} PREDS {{146 0 0-6081 {}} {259 0 0-6381 {}}} SUCCS {{258 0 0-6384 {}}} CYCLES {}}
+set a(0-6383) {NAME FRAME:for:slc(FRAME:for:acc#5.tmp)#1 TYPE READSLICE PAR 0-6006 XREFS 38080 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.671846875} PREDS {{146 0 0-6081 {}} {258 0 0-6381 {}}} SUCCS {{259 0 0-6384 {}}} CYCLES {}}
+set a(0-6384) {NAME FRAME:for:or#3 TYPE OR PAR 0-6006 XREFS 38081 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.671846875} PREDS {{146 0 0-6081 {}} {258 0 0-6382 {}} {259 0 0-6383 {}}} SUCCS {{259 0 0-6385 {}}} CYCLES {}}
+set a(0-6385) {NAME FRAME:for:exs#33 TYPE SIGNEXTEND PAR 0-6006 XREFS 38082 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.671846875} PREDS {{146 0 0-6081 {}} {259 0 0-6384 {}}} SUCCS {{259 0 0-6386 {}}} CYCLES {}}
+set a(0-6386) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 6 NAME FRAME:for:and#17 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 38083 LOC {1 0.057514275 1 0.648786275 1 0.648786275 1 0.6651930062638539 2 0.6882536062638539} PREDS {{146 0 0-6081 {}} {259 0 0-6385 {}}} SUCCS {{258 0 0-6391 {}}} CYCLES {}}
+set a(0-6387) {NAME FRAME:for:slc(FRAME:for:acc#5.tmp)#2 TYPE READSLICE PAR 0-6006 XREFS 38084 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.6882536499999999} PREDS {{146 0 0-6081 {}} {258 0 0-6381 {}}} SUCCS {{258 0 0-6389 {}}} CYCLES {}}
+set a(0-6388) {NAME FRAME:for:slc(FRAME:for:acc#5.tmp)#3 TYPE READSLICE PAR 0-6006 XREFS 38085 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.6882536499999999} PREDS {{146 0 0-6081 {}} {258 0 0-6381 {}}} SUCCS {{259 0 0-6389 {}}} CYCLES {}}
+set a(0-6389) {NAME FRAME:for:and#18 TYPE AND PAR 0-6006 XREFS 38086 LOC {1 0.057514275 1 0.648786275 1 0.648786275 2 0.6882536499999999} PREDS {{146 0 0-6081 {}} {258 0 0-6387 {}} {259 0 0-6388 {}}} SUCCS {{259 0 0-6390 {}}} CYCLES {}}
+set a(0-6390) {NAME FRAME:for:exs#34 TYPE SIGNEXTEND PAR 0-6006 XREFS 38087 LOC {1 0.057514275 1 0.66519305 1 0.66519305 2 0.6882536499999999} PREDS {{146 0 0-6081 {}} {259 0 0-6389 {}}} SUCCS {{259 0 0-6391 {}}} CYCLES {}}
+set a(0-6391) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(2,2) AREA_SCORE 1.46 QUANTITY 4 NAME FRAME:for:or#2 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-6006 XREFS 38088 LOC {1 0.07392105 1 0.66519305 1 0.66519305 1 0.6819354811077388 2 0.7049960811077388} PREDS {{146 0 0-6081 {}} {258 0 0-6386 {}} {259 0 0-6390 {}}} SUCCS {{258 0 0-6396 {}} {258 0 0-6402 {}} {258 0 0-6408 {}}} CYCLES {}}
+set a(0-6392) {NAME {regs.operator[]#9:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 38089 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6395 {}}} CYCLES {}}
+set a(0-6393) {NAME {regs.operator[]#9:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 38090 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6395 {}}} CYCLES {}}
+set a(0-6394) {NAME {regs.operator[]#9:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 38091 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6395 {}}} CYCLES {}}
+set a(0-6395) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#9:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 38092 LOC {1 0.0230606 1 0.623407725 1 0.623407725 1 0.681935475 2 0.7049960749999999} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}} {258 0 0-6393 {}} {258 0 0-6392 {}} {259 0 0-6394 {}}} SUCCS {{259 0 0-6396 {}}} CYCLES {}}
+set a(0-6396) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#3 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 38093 LOC {1 0.090663525 1 0.681935525 1 0.681935525 1 0.8748593874999999 2 0.8979199874999999} PREDS {{146 0 0-6081 {}} {258 0 0-6391 {}} {259 0 0-6395 {}}} SUCCS {{259 0 0-6397 {}}} CYCLES {}}
+set a(0-6397) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(15,0,11,1,15) AREA_SCORE 16.00 QUANTITY 3 NAME FRAME:for:acc#26 TYPE ACCU DELAY {1.63 ns} LIBRARY_DELAY {1.63 ns} PAR 0-6006 XREFS 38094 LOC {1 0.28358744999999996 1 0.87485945 1 0.87485945 1 0.9769393423306529 2 0.9999999423306529} PREDS {{146 0 0-6081 {}} {258 0 0-6070 {}} {259 0 0-6396 {}}} SUCCS {{258 0 0-6473 {}}} CYCLES {}}
+set a(0-6398) {NAME {regs.operator[]#10:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 38095 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6401 {}}} CYCLES {}}
+set a(0-6399) {NAME {regs.operator[]#10:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 38096 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6401 {}}} CYCLES {}}
+set a(0-6400) {NAME {regs.operator[]#10:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 38097 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6401 {}}} CYCLES {}}
+set a(0-6401) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#10:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 38098 LOC {1 0.0230606 1 0.623407725 1 0.623407725 1 0.681935475 2 0.7049960749999999} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}} {258 0 0-6399 {}} {258 0 0-6398 {}} {259 0 0-6400 {}}} SUCCS {{259 0 0-6402 {}}} CYCLES {}}
+set a(0-6402) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#4 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 38099 LOC {1 0.090663525 1 0.681935525 1 0.681935525 1 0.8748593874999999 2 0.8979199874999999} PREDS {{146 0 0-6081 {}} {258 0 0-6391 {}} {259 0 0-6401 {}}} SUCCS {{259 0 0-6403 {}}} CYCLES {}}
+set a(0-6403) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(15,0,11,1,15) AREA_SCORE 16.00 QUANTITY 3 NAME FRAME:for:acc#27 TYPE ACCU DELAY {1.63 ns} LIBRARY_DELAY {1.63 ns} PAR 0-6006 XREFS 38100 LOC {1 0.28358744999999996 1 0.87485945 1 0.87485945 1 0.9769393423306529 2 0.9999999423306529} PREDS {{146 0 0-6081 {}} {258 0 0-6073 {}} {259 0 0-6402 {}}} SUCCS {{258 0 0-6474 {}}} CYCLES {}}
+set a(0-6404) {NAME {regs.operator[]#11:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 38101 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6407 {}}} CYCLES {}}
+set a(0-6405) {NAME {regs.operator[]#11:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 38102 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6407 {}}} CYCLES {}}
+set a(0-6406) {NAME {regs.operator[]#11:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 38103 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.646468325} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6407 {}}} CYCLES {}}
+set a(0-6407) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#11:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 38104 LOC {1 0.0230606 1 0.623407725 1 0.623407725 1 0.681935475 2 0.7049960749999999} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}} {258 0 0-6405 {}} {258 0 0-6404 {}} {259 0 0-6406 {}}} SUCCS {{259 0 0-6408 {}}} CYCLES {}}
+set a(0-6408) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#5 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 38105 LOC {1 0.090663525 1 0.681935525 1 0.681935525 1 0.8748593874999999 2 0.8979199874999999} PREDS {{146 0 0-6081 {}} {258 0 0-6391 {}} {259 0 0-6407 {}}} SUCCS {{259 0 0-6409 {}}} CYCLES {}}
+set a(0-6409) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(15,0,11,1,15) AREA_SCORE 16.00 QUANTITY 3 NAME FRAME:for:acc#28 TYPE ACCU DELAY {1.63 ns} LIBRARY_DELAY {1.63 ns} PAR 0-6006 XREFS 38106 LOC {1 0.28358744999999996 1 0.87485945 1 0.87485945 1 0.9769393423306529 2 0.9999999423306529} PREDS {{146 0 0-6081 {}} {258 0 0-6076 {}} {259 0 0-6408 {}}} SUCCS {{258 0 0-6475 {}}} CYCLES {}}
+set a(0-6410) {NAME i:slc(i#3)#1 TYPE READSLICE PAR 0-6006 XREFS 38107 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}}} SUCCS {{259 0 0-6411 {}}} CYCLES {}}
+set a(0-6411) {NAME FRAME:for:not#3 TYPE NOT PAR 0-6006 XREFS 38108 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6081 {}} {259 0 0-6410 {}}} SUCCS {{258 0 0-6413 {}}} CYCLES {}}
+set a(0-6412) {NAME i:slc(i#3)#2 TYPE READSLICE PAR 0-6006 XREFS 38109 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}}} SUCCS {{259 0 0-6413 {}}} CYCLES {}}
+set a(0-6413) {NAME FRAME:for:conc TYPE CONCATENATE PAR 0-6006 XREFS 38110 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6081 {}} {258 0 0-6411 {}} {259 0 0-6412 {}}} SUCCS {{259 0 0-6414 {}} {258 0 0-6415 {}} {258 0 0-6416 {}} {258 0 0-6417 {}} {258 0 0-6418 {}} {258 0 0-6422 {}}} CYCLES {}}
+set a(0-6414) {NAME slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-6006 XREFS 38111 LOC {1 0.016406775 1 0.607678775 1 0.607678775 3 1.0} PREDS {{146 0 0-6081 {}} {259 0 0-6413 {}}} SUCCS {} CYCLES {}}
+set a(0-6415) {NAME slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-6006 XREFS 38112 LOC {1 0.016406775 1 0.607678775 1 0.607678775 3 1.0} PREDS {{146 0 0-6081 {}} {258 0 0-6413 {}}} SUCCS {} CYCLES {}}
+set a(0-6416) {NAME slc(FRAME:for:conc.tmp)#2 TYPE READSLICE PAR 0-6006 XREFS 38113 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5388626249999999} PREDS {{146 0 0-6081 {}} {258 0 0-6413 {}}} SUCCS {{258 0 0-6424 {}}} CYCLES {}}
+set a(0-6417) {NAME slc(FRAME:for:conc.tmp)#3 TYPE READSLICE PAR 0-6006 XREFS 38114 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6081 {}} {258 0 0-6413 {}}} SUCCS {{258 0 0-6419 {}}} CYCLES {}}
+set a(0-6418) {NAME FRAME:for:slc(FRAME:for:conc.tmp) TYPE READSLICE PAR 0-6006 XREFS 38115 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6081 {}} {258 0 0-6413 {}}} SUCCS {{259 0 0-6419 {}}} CYCLES {}}
+set a(0-6419) {NAME FRAME:for:nand#3 TYPE NAND PAR 0-6006 XREFS 38116 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5224558499999999} PREDS {{146 0 0-6081 {}} {258 0 0-6417 {}} {259 0 0-6418 {}}} SUCCS {{259 0 0-6420 {}}} CYCLES {}}
+set a(0-6420) {NAME FRAME:for:exs#35 TYPE SIGNEXTEND PAR 0-6006 XREFS 38117 LOC {1 0.016406775 1 0.644864425 1 0.644864425 2 0.5224558499999999} PREDS {{146 0 0-6081 {}} {259 0 0-6419 {}}} SUCCS {{259 0 0-6421 {}}} CYCLES {}}
+set a(0-6421) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 6 NAME FRAME:for:and#19 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 38118 LOC {1 0.016406775 1 0.644864425 1 0.644864425 1 0.6612711562638539 2 0.5388625812638539} PREDS {{146 0 0-6081 {}} {259 0 0-6420 {}}} SUCCS {{258 0 0-6426 {}}} CYCLES {}}
+set a(0-6422) {NAME FRAME:for:slc(FRAME:for:conc.tmp)#1 TYPE READSLICE PAR 0-6006 XREFS 38119 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5388626249999999} PREDS {{146 0 0-6081 {}} {258 0 0-6413 {}}} SUCCS {{259 0 0-6423 {}}} CYCLES {}}
+set a(0-6423) {NAME FRAME:for:not#2 TYPE NOT PAR 0-6006 XREFS 38120 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5388626249999999} PREDS {{146 0 0-6081 {}} {259 0 0-6422 {}}} SUCCS {{259 0 0-6424 {}}} CYCLES {}}
+set a(0-6424) {NAME FRAME:for:and#20 TYPE AND PAR 0-6006 XREFS 38121 LOC {1 0.016406775 1 0.607678775 1 0.607678775 2 0.5388626249999999} PREDS {{146 0 0-6081 {}} {258 0 0-6416 {}} {259 0 0-6423 {}}} SUCCS {{259 0 0-6425 {}}} CYCLES {}}
+set a(0-6425) {NAME FRAME:for:exs#36 TYPE SIGNEXTEND PAR 0-6006 XREFS 38122 LOC {1 0.016406775 1 0.6612712 1 0.6612712 2 0.5388626249999999} PREDS {{146 0 0-6081 {}} {259 0 0-6424 {}}} SUCCS {{259 0 0-6426 {}}} CYCLES {}}
+set a(0-6426) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_or(2,2) AREA_SCORE 1.46 QUANTITY 4 NAME FRAME:for:or#4 TYPE OR DELAY {0.27 ns} LIBRARY_DELAY {0.27 ns} PAR 0-6006 XREFS 38123 LOC {1 0.03281355 1 0.6612712 1 0.6612712 1 0.6780136311077388 2 0.5556050561077388} PREDS {{146 0 0-6081 {}} {258 0 0-6421 {}} {259 0 0-6425 {}}} SUCCS {{258 0 0-6431 {}} {258 0 0-6437 {}} {258 0 0-6443 {}}} CYCLES {}}
+set a(0-6427) {NAME {regs.operator[]#12:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 38124 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.619485875} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6430 {}}} CYCLES {}}
+set a(0-6428) {NAME {regs.operator[]#12:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 38125 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.619485875} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6430 {}}} CYCLES {}}
+set a(0-6429) {NAME {regs.operator[]#12:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 38126 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.619485875} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6430 {}}} CYCLES {}}
+set a(0-6430) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#12:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 38127 LOC {1 0.0230606 1 0.619485875 1 0.619485875 1 0.678013625 2 0.678013625} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}} {258 0 0-6428 {}} {258 0 0-6427 {}} {259 0 0-6429 {}}} SUCCS {{259 0 0-6431 {}}} CYCLES {}}
+set a(0-6431) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#6 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 38128 LOC {1 0.08158839999999999 1 0.678013675 1 0.678013675 1 0.8709375374999999 2 0.8709375374999999} PREDS {{146 0 0-6081 {}} {258 0 0-6426 {}} {259 0 0-6430 {}}} SUCCS {{259 0 0-6432 {}}} CYCLES {}}
+set a(0-6432) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for:acc#10 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6006 XREFS 38129 LOC {1 0.274512325 1 0.8709376 1 0.8709376 1 0.9769393413378799 2 0.9769393413378799} PREDS {{146 0 0-6081 {}} {258 0 0-6052 {}} {259 0 0-6431 {}}} SUCCS {{258 0 0-6464 {}}} CYCLES {}}
+set a(0-6433) {NAME {regs.operator[]#13:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 38130 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.4970773} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6436 {}}} CYCLES {}}
+set a(0-6434) {NAME {regs.operator[]#13:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 38131 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.4970773} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6436 {}}} CYCLES {}}
+set a(0-6435) {NAME {regs.operator[]#13:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 38132 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.4970773} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6436 {}}} CYCLES {}}
+set a(0-6436) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#13:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 38133 LOC {1 0.0230606 1 0.619485875 1 0.619485875 1 0.678013625 2 0.55560505} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}} {258 0 0-6434 {}} {258 0 0-6433 {}} {259 0 0-6435 {}}} SUCCS {{259 0 0-6437 {}}} CYCLES {}}
+set a(0-6437) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#7 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 38134 LOC {1 0.08158839999999999 1 0.678013675 1 0.678013675 1 0.8709375374999999 2 0.7485289625} PREDS {{146 0 0-6081 {}} {258 0 0-6426 {}} {259 0 0-6436 {}}} SUCCS {{259 0 0-6438 {}}} CYCLES {}}
+set a(0-6438) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for:acc#12 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6006 XREFS 38135 LOC {1 0.274512325 1 0.8709376 1 0.8709376 1 0.9769393413378799 2 0.8545307663378798} PREDS {{146 0 0-6081 {}} {258 0 0-6058 {}} {259 0 0-6437 {}}} SUCCS {{258 0 0-6466 {}}} CYCLES {}}
+set a(0-6439) {NAME {regs.operator[]#14:slc(regs.regs(2))} TYPE READSLICE PAR 0-6006 XREFS 38136 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.4970773} PREDS {{146 0 0-6081 {}} {258 0 0-6046 {}}} SUCCS {{258 0 0-6442 {}}} CYCLES {}}
+set a(0-6440) {NAME {regs.operator[]#14:slc(regs.regs(1))} TYPE READSLICE PAR 0-6006 XREFS 38137 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.4970773} PREDS {{146 0 0-6081 {}} {258 0 0-6044 {}}} SUCCS {{258 0 0-6442 {}}} CYCLES {}}
+set a(0-6441) {NAME {regs.operator[]#14:slc(regs.regs(0))} TYPE READSLICE PAR 0-6006 XREFS 38138 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.4970773} PREDS {{146 0 0-6081 {}} {258 0 0-6041 {}}} SUCCS {{259 0 0-6442 {}}} CYCLES {}}
+set a(0-6442) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(10,2,4) AREA_SCORE 22.26 QUANTITY 15 NAME {regs.operator[]#14:mux} TYPE MUX DELAY {0.94 ns} LIBRARY_DELAY {0.94 ns} PAR 0-6006 XREFS 38139 LOC {1 0.0230606 1 0.619485875 1 0.619485875 1 0.678013625 2 0.55560505} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}} {258 0 0-6440 {}} {258 0 0-6439 {}} {259 0 0-6441 {}}} SUCCS {{259 0 0-6443 {}}} CYCLES {}}
+set a(0-6443) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(2,1,10,1,12) AREA_SCORE 330.00 QUANTITY 9 NAME FRAME:for:mul#8 TYPE MUL DELAY {3.09 ns} LIBRARY_DELAY {3.09 ns} PAR 0-6006 XREFS 38140 LOC {1 0.08158839999999999 1 0.678013675 1 0.678013675 1 0.8709375374999999 2 0.7485289625} PREDS {{146 0 0-6081 {}} {258 0 0-6426 {}} {259 0 0-6442 {}}} SUCCS {{259 0 0-6444 {}}} CYCLES {}}
+set a(0-6444) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(16,0,12,1,16) AREA_SCORE 17.00 QUANTITY 12 NAME FRAME:for:acc#14 TYPE ACCU DELAY {1.70 ns} LIBRARY_DELAY {1.70 ns} PAR 0-6006 XREFS 38141 LOC {1 0.274512325 1 0.8709376 1 0.8709376 1 0.9769393413378799 2 0.8545307663378798} PREDS {{146 0 0-6081 {}} {258 0 0-6064 {}} {259 0 0-6443 {}}} SUCCS {{258 0 0-6468 {}}} CYCLES {}}
+set a(0-6445) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(2,0,2,0,2) AREA_SCORE 3.31 QUANTITY 2 NAME FRAME:for:acc#16 TYPE ACCU DELAY {0.65 ns} LIBRARY_DELAY {0.65 ns} PAR 0-6006 XREFS 38142 LOC {1 0.016406775 1 0.8721934 1 0.8721934 1 0.9129764100894753 2 0.5555228850894752} PREDS {{146 0 0-6081 {}} {258 0 0-6067 {}}} SUCCS {{259 0 0-6446 {}} {258 0 0-6471 {}}} CYCLES {}}
+set a(0-6446) {NAME FRAME:for:asn#3 TYPE ASSIGN PAR 0-6006 XREFS 38143 LOC {1 0.057189825 1 0.9129764499999999 1 0.9129764499999999 2 0.555522925} PREDS {{146 0 0-6081 {}} {259 0 0-6445 {}}} SUCCS {{259 0 0-6447 {}}} CYCLES {}}
+set a(0-6447) {NAME FRAME:for:conc#16 TYPE CONCATENATE PAR 0-6006 XREFS 38144 LOC {1 0.057189825 1 0.9129764499999999 1 0.9129764499999999 2 0.555522925} PREDS {{146 0 0-6081 {}} {259 0 0-6446 {}}} SUCCS {{259 0 0-6448 {}}} CYCLES {}}
+set a(0-6448) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,3,0,3) AREA_SCORE 4.30 QUANTITY 2 NAME FRAME:for:acc TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-6006 XREFS 38145 LOC {1 0.057189825 1 0.9129764499999999 1 0.9129764499999999 1 0.9605325770708271 2 0.6030790520708271} PREDS {{146 0 0-6081 {}} {259 0 0-6447 {}}} SUCCS {{259 0 0-6449 {}}} CYCLES {}}
+set a(0-6449) {NAME FRAME:for:slc TYPE READSLICE PAR 0-6006 XREFS 38146 LOC {1 0.10474599999999999 1 0.9605326249999999 1 0.9605326249999999 2 0.6030791} PREDS {{146 0 0-6081 {}} {259 0 0-6448 {}}} SUCCS {{259 0 0-6450 {}}} CYCLES {}}
+set a(0-6450) {NAME FRAME:for:not TYPE NOT PAR 0-6006 XREFS 38147 LOC {1 0.10474599999999999 1 0.9605326249999999 1 0.9605326249999999 2 0.6030791} PREDS {{146 0 0-6081 {}} {259 0 0-6449 {}}} SUCCS {{259 0 0-6451 {}} {258 0 0-6478 {}}} CYCLES {}}
+set a(0-6451) {NAME not#4 TYPE NOT PAR 0-6006 XREFS 38148 LOC {1 0.10474599999999999 1 0.9605326249999999 1 0.9605326249999999 2 0.6030791} PREDS {{146 0 0-6081 {}} {259 0 0-6450 {}}} SUCCS {{259 0 0-6452 {}}} CYCLES {}}
+set a(0-6452) {NAME FRAME:for:exs#30 TYPE SIGNEXTEND PAR 0-6006 XREFS 38149 LOC {1 0.10474599999999999 1 0.9605326249999999 1 0.9605326249999999 2 0.6030791} PREDS {{146 0 0-6081 {}} {259 0 0-6451 {}}} SUCCS {{259 0 0-6453 {}}} CYCLES {}}
+set a(0-6453) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(2,2) AREA_SCORE 1.46 QUANTITY 6 NAME FRAME:for:and#13 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-6006 XREFS 38150 LOC {1 0.10474599999999999 1 0.9605326249999999 1 0.9605326249999999 1 0.9769393562638539 2 0.6194858312638539} PREDS {{146 0 0-6081 {}} {262 0 0-6472 {}} {259 0 0-6452 {}}} SUCCS {{258 0 0-6472 {}}} CYCLES {}}
+set a(0-6454) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 4 NAME FRAME:for#1:mux#9 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38151 LOC {1 0.2804138 1 0.9308181999999999 1 0.9308181999999999 1 0.9538787624999999 2 0.5733646375} PREDS {{258 0 0-6156 {}} {258 0 0-6021 {}} {258 0 0-6078 {}} {258 0 0-6019 {}} {259 0 0-6349 {}}} SUCCS {{259 0 0-6455 {}}} CYCLES {}}
+set a(0-6455) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 4 NAME FRAME:for:mux#42 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38152 LOC {1 0.3034744 1 0.9538787999999999 1 0.9538787999999999 1 0.9769393624999999 2 0.5964252375} PREDS {{258 0 0-6080 {}} {258 0 0-6078 {}} {259 0 0-6454 {}}} SUCCS {{258 0 0-6457 {}} {258 0 0-6476 {}} {258 0 0-6479 {}}} CYCLES {}}
+set a(0-6456) {NAME FRAME:for:and#15 TYPE AND PAR 0-6006 XREFS 38153 LOC {1 0.088339225 1 0.4061093 1 0.4061093 2 0.596425275} PREDS {{258 0 0-6080 {}} {258 0 0-6156 {}} {258 0 0-6021 {}}} SUCCS {{258 0 0-6458 {}} {258 0 0-6459 {}}} CYCLES {}}
+set a(0-6457) {NAME not#5 TYPE NOT PAR 0-6006 XREFS 38154 LOC {1 0.32653499999999996 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {{258 0 0-6455 {}}} SUCCS {{259 0 0-6458 {}}} CYCLES {}}
+set a(0-6458) {NAME FRAME:for:or#1 TYPE OR PAR 0-6006 XREFS 38155 LOC {1 0.32653499999999996 1 0.9769393999999999 1 0.9769393999999999 2 0.596425275} PREDS {{258 0 0-6456 {}} {259 0 0-6457 {}}} SUCCS {{259 0 0-6459 {}}} CYCLES {}}
+set a(0-6459) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 4 NAME FRAME:for:mux#46 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38156 LOC {1 0.32653499999999996 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.6194858375} PREDS {{258 0 0-6456 {}} {259 0 0-6458 {}}} SUCCS {{258 0 0-6477 {}} {258 0 0-6479 {}}} CYCLES {}}
+set a(0-6460) {NAME asn(regs.regs(0).sva) TYPE ASSIGN PAR 0-6006 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.619485875} PREDS {{260 0 0-6460 {}} {256 0 0-6040 {}} {256 0 0-6042 {}} {258 0 0-6041 {}}} SUCCS {{262 0 0-6040 {}} {262 0 0-6042 {}} {260 0 0-6460 {}}} CYCLES {}}
+set a(0-6461) {NAME asn(regs.regs(1).sva) TYPE ASSIGN PAR 0-6006 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.619485875} PREDS {{260 0 0-6461 {}} {256 0 0-6043 {}} {256 0 0-6045 {}} {258 0 0-6044 {}}} SUCCS {{262 0 0-6043 {}} {262 0 0-6045 {}} {260 0 0-6461 {}}} CYCLES {}}
+set a(0-6462) {NAME asn(regs.regs(2).lpi#1) TYPE ASSIGN PAR 0-6006 LOC {1 0.0230606 1 0.048655775 1 0.048655775 2 0.619485875} PREDS {{260 0 0-6462 {}} {258 0 0-6046 {}}} SUCCS {{262 0 0-6046 {}} {260 0 0-6462 {}}} CYCLES {}}
+set a(0-6463) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#20 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38157 LOC {1 0.380514125 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.12226053749999999} PREDS {{260 0 0-6463 {}} {256 0 0-6049 {}} {258 0 0-6080 {}} {258 0 0-6018 {}} {258 0 0-6368 {}} {258 0 0-6101 {}} {258 0 0-6028 {}}} SUCCS {{262 0 0-6049 {}} {260 0 0-6463 {}}} CYCLES {}}
+set a(0-6464) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#21 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38158 LOC {1 0.380514125 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.9999999624999999} PREDS {{260 0 0-6464 {}} {256 0 0-6052 {}} {258 0 0-6080 {}} {258 0 0-6012 {}} {258 0 0-6432 {}} {258 0 0-6138 {}} {258 0 0-6025 {}}} SUCCS {{262 0 0-6052 {}} {260 0 0-6464 {}}} CYCLES {}}
+set a(0-6465) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#22 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38159 LOC {1 0.380514125 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.038375612499999996} PREDS {{260 0 0-6465 {}} {256 0 0-6055 {}} {258 0 0-6080 {}} {258 0 0-6017 {}} {258 0 0-6374 {}} {258 0 0-6108 {}} {258 0 0-6027 {}}} SUCCS {{262 0 0-6055 {}} {260 0 0-6465 {}}} CYCLES {}}
+set a(0-6466) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#23 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38160 LOC {1 0.380514125 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.8775913875} PREDS {{260 0 0-6466 {}} {256 0 0-6058 {}} {258 0 0-6080 {}} {258 0 0-6011 {}} {258 0 0-6438 {}} {258 0 0-6144 {}} {258 0 0-6024 {}}} SUCCS {{262 0 0-6058 {}} {260 0 0-6466 {}}} CYCLES {}}
+set a(0-6467) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#24 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38161 LOC {1 0.380514125 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.038375612499999996} PREDS {{260 0 0-6467 {}} {256 0 0-6061 {}} {258 0 0-6080 {}} {258 0 0-6016 {}} {258 0 0-6380 {}} {258 0 0-6115 {}} {258 0 0-6026 {}}} SUCCS {{262 0 0-6061 {}} {260 0 0-6467 {}}} CYCLES {}}
+set a(0-6468) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(16,1,2) AREA_SCORE 14.71 QUANTITY 6 NAME FRAME:for:mux#25 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38162 LOC {1 0.380514125 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.8775913875} PREDS {{260 0 0-6468 {}} {256 0 0-6064 {}} {258 0 0-6080 {}} {258 0 0-6010 {}} {258 0 0-6444 {}} {258 0 0-6150 {}} {258 0 0-6023 {}}} SUCCS {{262 0 0-6064 {}} {260 0 0-6468 {}}} CYCLES {}}
+set a(0-6469) {NAME FRAME:for:nand TYPE NAND PAR 0-6006 XREFS 38163 LOC {1 0.088339225 1 0.4061093 1 0.4061093 3 0.318762125} PREDS {{258 0 0-6080 {}} {258 0 0-6156 {}} {258 0 0-6021 {}}} SUCCS {{259 0 0-6470 {}}} CYCLES {}}
+set a(0-6470) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(19,1,2) AREA_SCORE 17.47 QUANTITY 1 NAME FRAME:for:mux#33 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38164 LOC {1 0.2075986 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.3418226875} PREDS {{260 0 0-6470 {}} {258 0 0-6345 {}} {258 0 0-6020 {}} {258 0 0-6035 {}} {259 0 0-6469 {}}} SUCCS {{262 0 0-6035 {}} {260 0 0-6470 {}}} CYCLES {}}
+set a(0-6471) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(2,1,2) AREA_SCORE 1.84 QUANTITY 2 NAME FRAME:for:mux#34 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38165 LOC {1 0.057189825 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.48067048749999997} PREDS {{260 0 0-6471 {}} {258 0 0-6080 {}} {258 0 0-6009 {}} {258 0 0-6445 {}} {258 0 0-6067 {}}} SUCCS {{262 0 0-6067 {}} {260 0 0-6471 {}}} CYCLES {}}
+set a(0-6472) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(2,1,2) AREA_SCORE 1.84 QUANTITY 2 NAME FRAME:for:mux#35 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38166 LOC {1 0.12115277499999999 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.6425464375} PREDS {{260 0 0-6472 {}} {256 0 0-6082 {}} {256 0 0-6083 {}} {256 0 0-6084 {}} {256 0 0-6085 {}} {256 0 0-6086 {}} {256 0 0-6089 {}} {256 0 0-6091 {}} {256 0 0-6098 {}} {256 0 0-6105 {}} {256 0 0-6112 {}} {256 0 0-6116 {}} {256 0 0-6118 {}} {256 0 0-6136 {}} {256 0 0-6142 {}} {256 0 0-6148 {}} {258 0 0-6080 {}} {258 0 0-6007 {}} {258 0 0-6453 {}} {258 0 0-6151 {}} {258 0 0-6022 {}}} SUCCS {{262 0 0-6082 {}} {262 0 0-6083 {}} {262 0 0-6084 {}} {262 0 0-6085 {}} {262 0 0-6086 {}} {262 0 0-6089 {}} {262 0 0-6091 {}} {262 0 0-6098 {}} {262 0 0-6105 {}} {262 0 0-6112 {}} {262 0 0-6116 {}} {262 0 0-6118 {}} {262 0 0-6136 {}} {262 0 0-6142 {}} {262 0 0-6148 {}} {262 0 0-6151 {}} {262 0 0-6453 {}} {260 0 0-6472 {}}} CYCLES {}}
+set a(0-6473) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(15,1,2) AREA_SCORE 13.79 QUANTITY 3 NAME FRAME:for:mux#39 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38167 LOC {1 0.3856674 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.1226525625} PREDS {{260 0 0-6473 {}} {258 0 0-6080 {}} {258 0 0-6015 {}} {258 0 0-6397 {}} {258 0 0-6070 {}}} SUCCS {{262 0 0-6070 {}} {260 0 0-6473 {}}} CYCLES {}}
+set a(0-6474) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(15,1,2) AREA_SCORE 13.79 QUANTITY 3 NAME FRAME:for:mux#40 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38168 LOC {1 0.3856674 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.0387676375} PREDS {{260 0 0-6474 {}} {258 0 0-6080 {}} {258 0 0-6014 {}} {258 0 0-6403 {}} {258 0 0-6073 {}}} SUCCS {{262 0 0-6073 {}} {260 0 0-6474 {}}} CYCLES {}}
+set a(0-6475) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(15,1,2) AREA_SCORE 13.79 QUANTITY 3 NAME FRAME:for:mux#41 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38169 LOC {1 0.3856674 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 3 0.0387676375} PREDS {{260 0 0-6475 {}} {258 0 0-6080 {}} {258 0 0-6013 {}} {258 0 0-6409 {}} {258 0 0-6076 {}}} SUCCS {{262 0 0-6076 {}} {260 0 0-6475 {}}} CYCLES {}}
+set a(0-6476) {NAME asn(exit:FRAME.lpi#1) TYPE ASSIGN PAR 0-6006 LOC {1 0.32653499999999996 1 0.9769393999999999 1 0.9769393999999999 3 0.550304075} PREDS {{260 0 0-6476 {}} {256 0 0-6078 {}} {258 0 0-6455 {}}} SUCCS {{262 0 0-6078 {}} {260 0 0-6476 {}}} CYCLES {}}
+set a(0-6477) {NAME asn(exit:FRAME:for#1.lpi#1) TYPE ASSIGN PAR 0-6006 LOC {1 0.3495956 1 1.0 1 1.0 2 0.619485875} PREDS {{260 0 0-6477 {}} {256 0 0-6037 {}} {258 0 0-6459 {}}} SUCCS {{262 0 0-6037 {}} {260 0 0-6477 {}}} CYCLES {}}
+set a(0-6478) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(1,1,2) AREA_SCORE 0.92 QUANTITY 4 NAME FRAME:for:mux#44 TYPE MUX DELAY {0.37 ns} LIBRARY_DELAY {0.37 ns} PAR 0-6006 XREFS 38170 LOC {1 0.10474599999999999 1 0.9769393999999999 1 0.9769393999999999 1 0.9999999624999999 2 0.6425464375} PREDS {{260 0 0-6478 {}} {258 0 0-6008 {}} {258 0 0-6450 {}} {258 0 0-6080 {}}} SUCCS {{262 0 0-6080 {}} {260 0 0-6478 {}}} CYCLES {}}
+set a(0-6479) {NAME FRAME:and TYPE AND PAR 0-6006 XREFS 38171 LOC {1 0.3495956 1 1.0 1 1.0 2 0.619485875} PREDS {{258 0 0-6455 {}} {258 0 0-6459 {}}} SUCCS {{259 0 0-6480 {}}} CYCLES {}}
+set a(0-6480) {NAME FRAME:asn#3 TYPE ASSIGN PAR 0-6006 XREFS 38172 LOC {1 0.3495956 1 1.0 1 1.0 2 0.619485875} PREDS {{260 0 0-6480 {}} {256 0 0-6030 {}} {256 0 0-6032 {}} {256 0 0-6036 {}} {259 0 0-6479 {}}} SUCCS {{262 0 0-6030 {}} {262 0 0-6032 {}} {262 0 0-6036 {}} {260 0 0-6480 {}}} CYCLES {}}
+set a(0-6006) {CHI {0-6007 0-6008 0-6009 0-6010 0-6011 0-6012 0-6013 0-6014 0-6015 0-6016 0-6017 0-6018 0-6019 0-6020 0-6021 0-6022 0-6023 0-6024 0-6025 0-6026 0-6027 0-6028 0-6029 0-6030 0-6031 0-6032 0-6033 0-6034 0-6035 0-6036 0-6037 0-6038 0-6039 0-6040 0-6041 0-6042 0-6043 0-6044 0-6045 0-6046 0-6047 0-6048 0-6049 0-6050 0-6051 0-6052 0-6053 0-6054 0-6055 0-6056 0-6057 0-6058 0-6059 0-6060 0-6061 0-6062 0-6063 0-6064 0-6065 0-6066 0-6067 0-6068 0-6069 0-6070 0-6071 0-6072 0-6073 0-6074 0-6075 0-6076 0-6077 0-6078 0-6079 0-6080 0-6081 0-6082 0-6083 0-6084 0-6085 0-6086 0-6087 0-6088 0-6089 0-6090 0-6091 0-6092 0-6093 0-6094 0-6095 0-6096 0-6097 0-6098 0-6099 0-6100 0-6101 0-6102 0-6103 0-6104 0-6105 0-6106 0-6107 0-6108 0-6109 0-6110 0-6111 0-6112 0-6113 0-6114 0-6115 0-6116 0-6117 0-6118 0-6119 0-6120 0-6121 0-6122 0-6123 0-6124 0-6125 0-6126 0-6127 0-6128 0-6129 0-6130 0-6131 0-6132 0-6133 0-6134 0-6135 0-6136 0-6137 0-6138 0-6139 0-6140 0-6141 0-6142 0-6143 0-6144 0-6145 0-6146 0-6147 0-6148 0-6149 0-6150 0-6151 0-6152 0-6153 0-6154 0-6155 0-6156 0-6157 0-6158 0-6159 0-6160 0-6161 0-6162 0-6163 0-6164 0-6165 0-6166 0-6167 0-6168 0-6169 0-6170 0-6171 0-6172 0-6173 0-6174 0-6175 0-6176 0-6177 0-6178 0-6179 0-6180 0-6181 0-6182 0-6183 0-6184 0-6185 0-6186 0-6187 0-6188 0-6189 0-6190 0-6191 0-6192 0-6193 0-6194 0-6195 0-6196 0-6197 0-6198 0-6199 0-6200 0-6201 0-6202 0-6203 0-6204 0-6205 0-6206 0-6207 0-6208 0-6209 0-6210 0-6211 0-6212 0-6213 0-6214 0-6215 0-6216 0-6217 0-6218 0-6219 0-6220 0-6221 0-6222 0-6223 0-6224 0-6225 0-6226 0-6227 0-6228 0-6229 0-6230 0-6231 0-6232 0-6233 0-6234 0-6235 0-6236 0-6237 0-6238 0-6239 0-6240 0-6241 0-6242 0-6243 0-6244 0-6245 0-6246 0-6247 0-6248 0-6249 0-6250 0-6251 0-6252 0-6253 0-6254 0-6255 0-6256 0-6257 0-6258 0-6259 0-6260 0-6261 0-6262 0-6263 0-6264 0-6265 0-6266 0-6267 0-6268 0-6269 0-6270 0-6271 0-6272 0-6273 0-6274 0-6275 0-6276 0-6277 0-6278 0-6279 0-6280 0-6281 0-6282 0-6283 0-6284 0-6285 0-6286 0-6287 0-6288 0-6289 0-6290 0-6291 0-6292 0-6293 0-6294 0-6295 0-6296 0-6297 0-6298 0-6299 0-6300 0-6301 0-6302 0-6303 0-6304 0-6305 0-6306 0-6307 0-6308 0-6309 0-6310 0-6311 0-6312 0-6313 0-6314 0-6315 0-6316 0-6317 0-6318 0-6319 0-6320 0-6321 0-6322 0-6323 0-6324 0-6325 0-6326 0-6327 0-6328 0-6329 0-6330 0-6331 0-6332 0-6333 0-6334 0-6335 0-6336 0-6337 0-6338 0-6339 0-6340 0-6341 0-6342 0-6343 0-6344 0-6345 0-6346 0-6347 0-6348 0-6349 0-6350 0-6351 0-6352 0-6353 0-6354 0-6355 0-6356 0-6357 0-6358 0-6359 0-6360 0-6361 0-6362 0-6363 0-6364 0-6365 0-6366 0-6367 0-6368 0-6369 0-6370 0-6371 0-6372 0-6373 0-6374 0-6375 0-6376 0-6377 0-6378 0-6379 0-6380 0-6381 0-6382 0-6383 0-6384 0-6385 0-6386 0-6387 0-6388 0-6389 0-6390 0-6391 0-6392 0-6393 0-6394 0-6395 0-6396 0-6397 0-6398 0-6399 0-6400 0-6401 0-6402 0-6403 0-6404 0-6405 0-6406 0-6407 0-6408 0-6409 0-6410 0-6411 0-6412 0-6413 0-6414 0-6415 0-6416 0-6417 0-6418 0-6419 0-6420 0-6421 0-6422 0-6423 0-6424 0-6425 0-6426 0-6427 0-6428 0-6429 0-6430 0-6431 0-6432 0-6433 0-6434 0-6435 0-6436 0-6437 0-6438 0-6439 0-6440 0-6441 0-6442 0-6443 0-6444 0-6445 0-6446 0-6447 0-6448 0-6449 0-6450 0-6451 0-6452 0-6453 0-6454 0-6455 0-6456 0-6457 0-6458 0-6459 0-6460 0-6461 0-6462 0-6463 0-6464 0-6465 0-6466 0-6467 0-6468 0-6469 0-6470 0-6471 0-6472 0-6473 0-6474 0-6475 0-6476 0-6477 0-6478 0-6479 0-6480} ITERATIONS Infinite LATENCY 1843201 RESET_LATENCY 0 CSTEPS 3 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 1843200 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 3.0 CYCLES_IN 1843202 TOTAL_CYCLES_IN 1843202 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 1843202 NAME main TYPE LOOP DELAY {36864060.00 ns} PAR 0-5986 XREFS 38173 LOC {0 1.0 0 1.0 0 1.0 0 1.0} PREDS {{258 0 0-5987 {}} {258 0 0-5988 {}} {258 0 0-6000 {}} {258 0 0-5999 {}} {258 0 0-5996 {}} {258 0 0-5993 {}} {258 0 0-5989 {}} {258 0 0-5997 {}} {258 0 0-5998 {}} {258 0 0-5994 {}} {258 0 0-5995 {}} {258 0 0-5991 {}} {258 0 0-5992 {}} {258 0 0-5990 {}} {258 0 0-6003 {}} {258 0 0-6004 {}} {258 0 0-6001 {}} {258 0 0-6002 {}} {259 0 0-6005 {}}} SUCCS {{772 0 0-5987 {}} {772 0 0-5988 {}} {772 0 0-5989 {}} {772 0 0-5990 {}} {772 0 0-5991 {}} {772 0 0-5992 {}} {772 0 0-5993 {}} {772 0 0-5994 {}} {772 0 0-5995 {}} {772 0 0-5996 {}} {772 0 0-5997 {}} {772 0 0-5998 {}} {772 0 0-5999 {}} {772 0 0-6000 {}} {772 0 0-6001 {}} {772 0 0-6002 {}} {772 0 0-6003 {}} {772 0 0-6004 {}} {772 0 0-6005 {}}} CYCLES {}}
+set a(0-5986) {CHI {0-5987 0-5988 0-5989 0-5990 0-5991 0-5992 0-5993 0-5994 0-5995 0-5996 0-5997 0-5998 0-5999 0-6000 0-6001 0-6002 0-6003 0-6004 0-6005 0-6006} ITERATIONS Infinite LATENCY 1843201 RESET_LATENCY 0 CSTEPS 0 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 1843200 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 0 TOTAL_CYCLES_IN 0 TOTAL_CYCLES_UNDER 1843202 TOTAL_CYCLES 1843202 NAME core:rlp TYPE LOOP DELAY {36864060.00 ns} PAR {} XREFS 38174 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-5986-TOTALCYCLES) {1843202}
+set a(0-5986-QMOD) {mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2) 0-6035 mgc_ioport.mgc_in_wire(1,90) 0-6039 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2) {0-6041 0-6044 0-6046} mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2) {0-6049 0-6052 0-6055 0-6058 0-6061 0-6064} mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2) {0-6067 0-6127 0-6358 0-6386 0-6421 0-6453} mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(15,2) {0-6070 0-6073 0-6076} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4) {0-6098 0-6105 0-6112 0-6136 0-6142 0-6148 0-6366 0-6372 0-6378 0-6395 0-6401 0-6407 0-6430 0-6436 0-6442} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12) {0-6100 0-6107 0-6114 0-6137 0-6143 0-6149 0-6367 0-6373 0-6379 0-6396 0-6402 0-6408 0-6431 0-6437 0-6443} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16) {0-6101 0-6108 0-6115 0-6138 0-6144 0-6150 0-6368 0-6374 0-6380 0-6432 0-6438 0-6444} mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(2,2) {0-6132 0-6362 0-6391 0-6426} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2) {0-6151 0-6445} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) {0-6154 0-6448} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16) {0-6159 0-6160 0-6163 0-6164 0-6167 0-6168} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4) {0-6173 0-6180 0-6185 0-6191 0-6198 0-6203 0-6226 0-6246 0-6253 0-6258 0-6281 0-6324} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5) {0-6181 0-6199 0-6229 0-6254 0-6284 0-6327} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6) {0-6186 0-6204 0-6259} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6) {0-6187 0-6205 0-6260} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11) {0-6207 0-6262 0-6299} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9) {0-6209 0-6264 0-6307} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5) {0-6220 0-6232 0-6275 0-6287 0-6318 0-6330} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8) {0-6233 0-6288 0-6331} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10) {0-6234 0-6289 0-6332} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12) {0-6235 0-6290} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,11,0,12) {0-6242 0-6297} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,9,1,10) 0-6305 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,10) 0-6333 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2) 0-6336 mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2) 0-6341 mgc_ioport.mgc_out_stdreg(2,30) 0-6344 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19) 0-6345 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,7,0,8) 0-6347 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) 0-6381 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) {0-6397 0-6403 0-6409} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2) {0-6454 0-6455 0-6459 0-6478} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2) {0-6463 0-6464 0-6465 0-6466 0-6467 0-6468} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2) 0-6470 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2) {0-6471 0-6472} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(15,1,2) {0-6473 0-6474 0-6475}}
+set a(0-5986-PROC_NAME) {core}
+set a(0-5986-HIER_NAME) {/sobel/core}
+set a(TOP) {0-5986}
+
diff --git a/Sobel/sobel.v9/schematic.nlv b/Sobel/sobel.v9/schematic.nlv
new file mode 100644
index 0000000..a74b528
--- /dev/null
+++ b/Sobel/sobel.v9/schematic.nlv
@@ -0,0 +1,12161 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "sobel:core" "orig"
+load port {clk} input -attr xrf 39514 -attr oid 1 -attr vt d -attr @path {/sobel/sobel:core/clk}
+load port {en} input -attr xrf 39515 -attr oid 2 -attr vt d -attr @path {/sobel/sobel:core/en}
+load port {arst_n} input -attr xrf 39516 -attr oid 3 -attr vt d -attr @path {/sobel/sobel:core/arst_n}
+load portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} -attr xrf 39517 -attr oid 4 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} -attr xrf 39518 -attr oid 5 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load symbol "add(5,-1,5,-1,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,0,5,1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(9,0,8,1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(8:0)} input 9 {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(10,-1,10,-1,10)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,10)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "or(2,6)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(5:0)} input 6 {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(5:0)} input 6 {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nand(3,1)" "INTERFACE" NAND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,30)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(29:0)} input 30 {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(29:0)} input 30 {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(30,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(29:0)} input 30 {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(29:0)} input 30 {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(29:0)} output 30 {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,1,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "reg(2,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(1:0)} input 2 {D(1)} {D(0)} \
+     portBus {DRa(1:0)} input 2 {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,5,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(4:0)} input 5 {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(6,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(5:0)} input 6 {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(5:0)} input 6 {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(3,0,6,0,9)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(9,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(8:0)} input 9 {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(8:0)} input 9 {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(8:0)} output 9 {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "not(3)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,-1,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,2,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,3,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(5,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(4:0)} input 5 {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(4:0)} input 5 {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(1,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(0:0)} input 1 {D(0)} \
+     portBus {DRa(0:0)} input 1 {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mul(2,0,9,0,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(11,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(10:0)} input 11 {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(10:0)} input 11 {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,2)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(1:0)} input 2 {A0(1)} {A0(0)} \
+     portBus {A1(1:0)} input 2 {A1(1)} {A1(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "mux(2,2)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(1:0)} input 2 {A0(1)} {A0(0)} \
+     portBus {A1(1:0)} input 2 {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "mux(2,1)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "and(2,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "reg(90,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(89:0)} input 90 {D(89)} {D(88)} {D(87)} {D(86)} {D(85)} {D(84)} {D(83)} {D(82)} {D(81)} {D(80)} {D(79)} {D(78)} {D(77)} {D(76)} {D(75)} {D(74)} {D(73)} {D(72)} {D(71)} {D(70)} {D(69)} {D(68)} {D(67)} {D(66)} {D(65)} {D(64)} {D(63)} {D(62)} {D(61)} {D(60)} {D(59)} {D(58)} {D(57)} {D(56)} {D(55)} {D(54)} {D(53)} {D(52)} {D(51)} {D(50)} {D(49)} {D(48)} {D(47)} {D(46)} {D(45)} {D(44)} {D(43)} {D(42)} {D(41)} {D(40)} {D(39)} {D(38)} {D(37)} {D(36)} {D(35)} {D(34)} {D(33)} {D(32)} {D(31)} {D(30)} {D(29)} {D(28)} {D(27)} {D(26)} {D(25)} {D(24)} {D(23)} {D(22)} {D(21)} {D(20)} {D(19)} {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(89:0)} input 90 {DRa(89)} {DRa(88)} {DRa(87)} {DRa(86)} {DRa(85)} {DRa(84)} {DRa(83)} {DRa(82)} {DRa(81)} {DRa(80)} {DRa(79)} {DRa(78)} {DRa(77)} {DRa(76)} {DRa(75)} {DRa(74)} {DRa(73)} {DRa(72)} {DRa(71)} {DRa(70)} {DRa(69)} {DRa(68)} {DRa(67)} {DRa(66)} {DRa(65)} {DRa(64)} {DRa(63)} {DRa(62)} {DRa(61)} {DRa(60)} {DRa(59)} {DRa(58)} {DRa(57)} {DRa(56)} {DRa(55)} {DRa(54)} {DRa(53)} {DRa(52)} {DRa(51)} {DRa(50)} {DRa(49)} {DRa(48)} {DRa(47)} {DRa(46)} {DRa(45)} {DRa(44)} {DRa(43)} {DRa(42)} {DRa(41)} {DRa(40)} {DRa(39)} {DRa(38)} {DRa(37)} {DRa(36)} {DRa(35)} {DRa(34)} {DRa(33)} {DRa(32)} {DRa(31)} {DRa(30)} {DRa(29)} {DRa(28)} {DRa(27)} {DRa(26)} {DRa(25)} {DRa(24)} {DRa(23)} {DRa(22)} {DRa(21)} {DRa(20)} {DRa(19)} {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(4,10)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(9:0)} input 10 {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(9:0)} input 10 {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {A2(9:0)} input 10 {A2(9)} {A2(8)} {A2(7)} {A2(6)} {A2(5)} {A2(4)} {A2(3)} {A2(2)} {A2(1)} {A2(0)} \
+     portBus {A3(9:0)} input 10 {A3(9)} {A3(8)} {A3(7)} {A3(6)} {A3(5)} {A3(4)} {A3(3)} {A3(2)} {A3(1)} {A3(0)} \
+     portBus {S(1:0)} input.top 2 {S(1)} {S(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,11)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(10:0)} output 11 {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(15,-1,11,1,15)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(14:0)} input 15 {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,15)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(14:0)} input 15 {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(14:0)} input 15 {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(15,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(14:0)} input 15 {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(14:0)} input 15 {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,11,1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,16)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(15:0)} input 16 {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(15:0)} input 16 {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(16,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(15:0)} input 16 {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(15:0)} input 16 {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(3,1)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,19)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(19,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(18:0)} input 19 {D(18)} {D(17)} {D(16)} {D(15)} {D(14)} {D(13)} {D(12)} {D(11)} {D(10)} {D(9)} {D(8)} {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(18:0)} input 19 {DRa(18)} {DRa(17)} {DRa(16)} {DRa(15)} {DRa(14)} {DRa(13)} {DRa(12)} {DRa(11)} {DRa(10)} {DRa(9)} {DRa(8)} {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(11,0,10,1,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(10:0)} input 11 {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(9:0)} input 10 {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(12,-1,11,0,12)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(11:0)} input 12 {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(10:0)} input 11 {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(2,-1,1,0,2)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(1:0)} output 2 {Z(1)} {Z(0)} \
+
+load symbol "or(2,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "mux(2,90)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(89:0)} input 90 {A0(89)} {A0(88)} {A0(87)} {A0(86)} {A0(85)} {A0(84)} {A0(83)} {A0(82)} {A0(81)} {A0(80)} {A0(79)} {A0(78)} {A0(77)} {A0(76)} {A0(75)} {A0(74)} {A0(73)} {A0(72)} {A0(71)} {A0(70)} {A0(69)} {A0(68)} {A0(67)} {A0(66)} {A0(65)} {A0(64)} {A0(63)} {A0(62)} {A0(61)} {A0(60)} {A0(59)} {A0(58)} {A0(57)} {A0(56)} {A0(55)} {A0(54)} {A0(53)} {A0(52)} {A0(51)} {A0(50)} {A0(49)} {A0(48)} {A0(47)} {A0(46)} {A0(45)} {A0(44)} {A0(43)} {A0(42)} {A0(41)} {A0(40)} {A0(39)} {A0(38)} {A0(37)} {A0(36)} {A0(35)} {A0(34)} {A0(33)} {A0(32)} {A0(31)} {A0(30)} {A0(29)} {A0(28)} {A0(27)} {A0(26)} {A0(25)} {A0(24)} {A0(23)} {A0(22)} {A0(21)} {A0(20)} {A0(19)} {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(89:0)} input 90 {A1(89)} {A1(88)} {A1(87)} {A1(86)} {A1(85)} {A1(84)} {A1(83)} {A1(82)} {A1(81)} {A1(80)} {A1(79)} {A1(78)} {A1(77)} {A1(76)} {A1(75)} {A1(74)} {A1(73)} {A1(72)} {A1(71)} {A1(70)} {A1(69)} {A1(68)} {A1(67)} {A1(66)} {A1(65)} {A1(64)} {A1(63)} {A1(62)} {A1(61)} {A1(60)} {A1(59)} {A1(58)} {A1(57)} {A1(56)} {A1(55)} {A1(54)} {A1(53)} {A1(52)} {A1(51)} {A1(50)} {A1(49)} {A1(48)} {A1(47)} {A1(46)} {A1(45)} {A1(44)} {A1(43)} {A1(42)} {A1(41)} {A1(40)} {A1(39)} {A1(38)} {A1(37)} {A1(36)} {A1(35)} {A1(34)} {A1(33)} {A1(32)} {A1(31)} {A1(30)} {A1(29)} {A1(28)} {A1(27)} {A1(26)} {A1(25)} {A1(24)} {A1(23)} {A1(22)} {A1(21)} {A1(20)} {A1(19)} {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(89:0)} output 90 {Z(89)} {Z(88)} {Z(87)} {Z(86)} {Z(85)} {Z(84)} {Z(83)} {Z(82)} {Z(81)} {Z(80)} {Z(79)} {Z(78)} {Z(77)} {Z(76)} {Z(75)} {Z(74)} {Z(73)} {Z(72)} {Z(71)} {Z(70)} {Z(69)} {Z(68)} {Z(67)} {Z(66)} {Z(65)} {Z(64)} {Z(63)} {Z(62)} {Z(61)} {Z(60)} {Z(59)} {Z(58)} {Z(57)} {Z(56)} {Z(55)} {Z(54)} {Z(53)} {Z(52)} {Z(51)} {Z(50)} {Z(49)} {Z(48)} {Z(47)} {Z(46)} {Z(45)} {Z(44)} {Z(43)} {Z(42)} {Z(41)} {Z(40)} {Z(39)} {Z(38)} {Z(37)} {Z(36)} {Z(35)} {Z(34)} {Z(33)} {Z(32)} {Z(31)} {Z(30)} {Z(29)} {Z(28)} {Z(27)} {Z(26)} {Z(25)} {Z(24)} {Z(23)} {Z(22)} {Z(21)} {Z(20)} {Z(19)} {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(7,0,8,-1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(6:0)} input 7 {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(19,-1,1,0,19)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(18:0)} input 19 {A(18)} {A(17)} {A(16)} {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,19)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(18:0)} input 19 {A0(18)} {A0(17)} {A0(16)} {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(18:0)} input 19 {A1(18)} {A1(17)} {A1(16)} {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(18:0)} output 19 {Z(18)} {Z(17)} {Z(16)} {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,0,3,0,4)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(2:0)} input 3 {B(2)} {B(1)} {B(0)} \
+     portBus {Z(3:0)} output 4 {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(4,0,4,0,5)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(3:0)} input 4 {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(4:0)} output 5 {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(5,0,4,0,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(4:0)} input 5 {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(3:0)} input 4 {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(6,-1,6,-1,6)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(5:0)} input 6 {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(5:0)} input 6 {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(5:0)} output 6 {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(15,-1,15,-1,15)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(14:0)} input 15 {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(14:0)} input 15 {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,16,-1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(15:0)} input 16 {B(15)} {B(14)} {B(13)} {B(12)} {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(2,0,9,0,10)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(1:0)} input 2 {A(1)} {A(0)} \
+     portBus {B(8:0)} input 9 {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(9:0)} output 10 {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,15)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(14:0)} input 15 {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(14:0)} input 15 {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(14:0)} output 15 {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(10,1,2,1,12)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(9:0)} input 10 {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(11:0)} output 12 {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(16,-1,12,1,16)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(15:0)} input 16 {A(15)} {A(14)} {A(13)} {A(12)} {A(11)} {A(10)} {A(9)} {A(8)} {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(11:0)} input 12 {B(11)} {B(10)} {B(9)} {B(8)} {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,16)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(15:0)} input 16 {A0(15)} {A0(14)} {A0(13)} {A0(12)} {A0(11)} {A0(10)} {A0(9)} {A0(8)} {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(15:0)} input 16 {A1(15)} {A1(14)} {A1(13)} {A1(12)} {A1(11)} {A1(10)} {A1(9)} {A1(8)} {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(15:0)} output 16 {Z(15)} {Z(14)} {Z(13)} {Z(12)} {Z(11)} {Z(10)} {Z(9)} {Z(8)} {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "nor(2,1)" "INTERFACE" NOR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "nand(2,1)" "INTERFACE" NAND boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "or(3,1)" "INTERFACE" OR boxcolor 0 \
+     portBus {A0(0:0)} input 1 {A0(0)} \
+     portBus {A1(0:0)} input 1 {A1(0)} \
+     portBus {A2(0:0)} input 1 {A2(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load net {FRAME:p#1.lpi#1(0)} -attr vt d
+load net {FRAME:p#1.lpi#1(1)} -attr vt d
+load net {FRAME:p#1.lpi#1(2)} -attr vt d
+load net {FRAME:p#1.lpi#1(3)} -attr vt d
+load net {FRAME:p#1.lpi#1(4)} -attr vt d
+load net {FRAME:p#1.lpi#1(5)} -attr vt d
+load net {FRAME:p#1.lpi#1(6)} -attr vt d
+load net {FRAME:p#1.lpi#1(7)} -attr vt d
+load net {FRAME:p#1.lpi#1(8)} -attr vt d
+load net {FRAME:p#1.lpi#1(9)} -attr vt d
+load net {FRAME:p#1.lpi#1(10)} -attr vt d
+load net {FRAME:p#1.lpi#1(11)} -attr vt d
+load net {FRAME:p#1.lpi#1(12)} -attr vt d
+load net {FRAME:p#1.lpi#1(13)} -attr vt d
+load net {FRAME:p#1.lpi#1(14)} -attr vt d
+load net {FRAME:p#1.lpi#1(15)} -attr vt d
+load net {FRAME:p#1.lpi#1(16)} -attr vt d
+load net {FRAME:p#1.lpi#1(17)} -attr vt d
+load net {FRAME:p#1.lpi#1(18)} -attr vt d
+load netBundle {FRAME:p#1.lpi#1} 19 {FRAME:p#1.lpi#1(0)} {FRAME:p#1.lpi#1(1)} {FRAME:p#1.lpi#1(2)} {FRAME:p#1.lpi#1(3)} {FRAME:p#1.lpi#1(4)} {FRAME:p#1.lpi#1(5)} {FRAME:p#1.lpi#1(6)} {FRAME:p#1.lpi#1(7)} {FRAME:p#1.lpi#1(8)} {FRAME:p#1.lpi#1(9)} {FRAME:p#1.lpi#1(10)} {FRAME:p#1.lpi#1(11)} {FRAME:p#1.lpi#1(12)} {FRAME:p#1.lpi#1(13)} {FRAME:p#1.lpi#1(14)} {FRAME:p#1.lpi#1(15)} {FRAME:p#1.lpi#1(16)} {FRAME:p#1.lpi#1(17)} {FRAME:p#1.lpi#1(18)} -attr xrf 39519 -attr oid 6 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {b(1).sg1.lpi#1(0)} -attr vt d
+load net {b(1).sg1.lpi#1(1)} -attr vt d
+load net {b(1).sg1.lpi#1(2)} -attr vt d
+load net {b(1).sg1.lpi#1(3)} -attr vt d
+load net {b(1).sg1.lpi#1(4)} -attr vt d
+load net {b(1).sg1.lpi#1(5)} -attr vt d
+load net {b(1).sg1.lpi#1(6)} -attr vt d
+load net {b(1).sg1.lpi#1(7)} -attr vt d
+load net {b(1).sg1.lpi#1(8)} -attr vt d
+load net {b(1).sg1.lpi#1(9)} -attr vt d
+load net {b(1).sg1.lpi#1(10)} -attr vt d
+load net {b(1).sg1.lpi#1(11)} -attr vt d
+load net {b(1).sg1.lpi#1(12)} -attr vt d
+load net {b(1).sg1.lpi#1(13)} -attr vt d
+load net {b(1).sg1.lpi#1(14)} -attr vt d
+load netBundle {b(1).sg1.lpi#1} 15 {b(1).sg1.lpi#1(0)} {b(1).sg1.lpi#1(1)} {b(1).sg1.lpi#1(2)} {b(1).sg1.lpi#1(3)} {b(1).sg1.lpi#1(4)} {b(1).sg1.lpi#1(5)} {b(1).sg1.lpi#1(6)} {b(1).sg1.lpi#1(7)} {b(1).sg1.lpi#1(8)} {b(1).sg1.lpi#1(9)} {b(1).sg1.lpi#1(10)} {b(1).sg1.lpi#1(11)} {b(1).sg1.lpi#1(12)} {b(1).sg1.lpi#1(13)} {b(1).sg1.lpi#1(14)} -attr xrf 39520 -attr oid 7 -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(0).lpi#1(0)} -attr vt d
+load net {b(0).lpi#1(1)} -attr vt d
+load net {b(0).lpi#1(2)} -attr vt d
+load net {b(0).lpi#1(3)} -attr vt d
+load net {b(0).lpi#1(4)} -attr vt d
+load net {b(0).lpi#1(5)} -attr vt d
+load net {b(0).lpi#1(6)} -attr vt d
+load net {b(0).lpi#1(7)} -attr vt d
+load net {b(0).lpi#1(8)} -attr vt d
+load net {b(0).lpi#1(9)} -attr vt d
+load net {b(0).lpi#1(10)} -attr vt d
+load net {b(0).lpi#1(11)} -attr vt d
+load net {b(0).lpi#1(12)} -attr vt d
+load net {b(0).lpi#1(13)} -attr vt d
+load net {b(0).lpi#1(14)} -attr vt d
+load net {b(0).lpi#1(15)} -attr vt d
+load netBundle {b(0).lpi#1} 16 {b(0).lpi#1(0)} {b(0).lpi#1(1)} {b(0).lpi#1(2)} {b(0).lpi#1(3)} {b(0).lpi#1(4)} {b(0).lpi#1(5)} {b(0).lpi#1(6)} {b(0).lpi#1(7)} {b(0).lpi#1(8)} {b(0).lpi#1(9)} {b(0).lpi#1(10)} {b(0).lpi#1(11)} {b(0).lpi#1(12)} {b(0).lpi#1(13)} {b(0).lpi#1(14)} {b(0).lpi#1(15)} -attr xrf 39521 -attr oid 8 -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(2).lpi#1(0)} -attr vt d
+load net {b(2).lpi#1(1)} -attr vt d
+load net {b(2).lpi#1(2)} -attr vt d
+load net {b(2).lpi#1(3)} -attr vt d
+load net {b(2).lpi#1(4)} -attr vt d
+load net {b(2).lpi#1(5)} -attr vt d
+load net {b(2).lpi#1(6)} -attr vt d
+load net {b(2).lpi#1(7)} -attr vt d
+load net {b(2).lpi#1(8)} -attr vt d
+load net {b(2).lpi#1(9)} -attr vt d
+load net {b(2).lpi#1(10)} -attr vt d
+load net {b(2).lpi#1(11)} -attr vt d
+load net {b(2).lpi#1(12)} -attr vt d
+load net {b(2).lpi#1(13)} -attr vt d
+load net {b(2).lpi#1(14)} -attr vt d
+load net {b(2).lpi#1(15)} -attr vt d
+load netBundle {b(2).lpi#1} 16 {b(2).lpi#1(0)} {b(2).lpi#1(1)} {b(2).lpi#1(2)} {b(2).lpi#1(3)} {b(2).lpi#1(4)} {b(2).lpi#1(5)} {b(2).lpi#1(6)} {b(2).lpi#1(7)} {b(2).lpi#1(8)} {b(2).lpi#1(9)} {b(2).lpi#1(10)} {b(2).lpi#1(11)} {b(2).lpi#1(12)} {b(2).lpi#1(13)} {b(2).lpi#1(14)} {b(2).lpi#1(15)} -attr xrf 39522 -attr oid 9 -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {g(1).sg1.lpi#1(0)} -attr vt d
+load net {g(1).sg1.lpi#1(1)} -attr vt d
+load net {g(1).sg1.lpi#1(2)} -attr vt d
+load net {g(1).sg1.lpi#1(3)} -attr vt d
+load net {g(1).sg1.lpi#1(4)} -attr vt d
+load net {g(1).sg1.lpi#1(5)} -attr vt d
+load net {g(1).sg1.lpi#1(6)} -attr vt d
+load net {g(1).sg1.lpi#1(7)} -attr vt d
+load net {g(1).sg1.lpi#1(8)} -attr vt d
+load net {g(1).sg1.lpi#1(9)} -attr vt d
+load net {g(1).sg1.lpi#1(10)} -attr vt d
+load net {g(1).sg1.lpi#1(11)} -attr vt d
+load net {g(1).sg1.lpi#1(12)} -attr vt d
+load net {g(1).sg1.lpi#1(13)} -attr vt d
+load net {g(1).sg1.lpi#1(14)} -attr vt d
+load netBundle {g(1).sg1.lpi#1} 15 {g(1).sg1.lpi#1(0)} {g(1).sg1.lpi#1(1)} {g(1).sg1.lpi#1(2)} {g(1).sg1.lpi#1(3)} {g(1).sg1.lpi#1(4)} {g(1).sg1.lpi#1(5)} {g(1).sg1.lpi#1(6)} {g(1).sg1.lpi#1(7)} {g(1).sg1.lpi#1(8)} {g(1).sg1.lpi#1(9)} {g(1).sg1.lpi#1(10)} {g(1).sg1.lpi#1(11)} {g(1).sg1.lpi#1(12)} {g(1).sg1.lpi#1(13)} {g(1).sg1.lpi#1(14)} -attr xrf 39523 -attr oid 10 -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(0).lpi#1(0)} -attr vt d
+load net {g(0).lpi#1(1)} -attr vt d
+load net {g(0).lpi#1(2)} -attr vt d
+load net {g(0).lpi#1(3)} -attr vt d
+load net {g(0).lpi#1(4)} -attr vt d
+load net {g(0).lpi#1(5)} -attr vt d
+load net {g(0).lpi#1(6)} -attr vt d
+load net {g(0).lpi#1(7)} -attr vt d
+load net {g(0).lpi#1(8)} -attr vt d
+load net {g(0).lpi#1(9)} -attr vt d
+load net {g(0).lpi#1(10)} -attr vt d
+load net {g(0).lpi#1(11)} -attr vt d
+load net {g(0).lpi#1(12)} -attr vt d
+load net {g(0).lpi#1(13)} -attr vt d
+load net {g(0).lpi#1(14)} -attr vt d
+load net {g(0).lpi#1(15)} -attr vt d
+load netBundle {g(0).lpi#1} 16 {g(0).lpi#1(0)} {g(0).lpi#1(1)} {g(0).lpi#1(2)} {g(0).lpi#1(3)} {g(0).lpi#1(4)} {g(0).lpi#1(5)} {g(0).lpi#1(6)} {g(0).lpi#1(7)} {g(0).lpi#1(8)} {g(0).lpi#1(9)} {g(0).lpi#1(10)} {g(0).lpi#1(11)} {g(0).lpi#1(12)} {g(0).lpi#1(13)} {g(0).lpi#1(14)} {g(0).lpi#1(15)} -attr xrf 39524 -attr oid 11 -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(2).lpi#1(0)} -attr vt d
+load net {g(2).lpi#1(1)} -attr vt d
+load net {g(2).lpi#1(2)} -attr vt d
+load net {g(2).lpi#1(3)} -attr vt d
+load net {g(2).lpi#1(4)} -attr vt d
+load net {g(2).lpi#1(5)} -attr vt d
+load net {g(2).lpi#1(6)} -attr vt d
+load net {g(2).lpi#1(7)} -attr vt d
+load net {g(2).lpi#1(8)} -attr vt d
+load net {g(2).lpi#1(9)} -attr vt d
+load net {g(2).lpi#1(10)} -attr vt d
+load net {g(2).lpi#1(11)} -attr vt d
+load net {g(2).lpi#1(12)} -attr vt d
+load net {g(2).lpi#1(13)} -attr vt d
+load net {g(2).lpi#1(14)} -attr vt d
+load net {g(2).lpi#1(15)} -attr vt d
+load netBundle {g(2).lpi#1} 16 {g(2).lpi#1(0)} {g(2).lpi#1(1)} {g(2).lpi#1(2)} {g(2).lpi#1(3)} {g(2).lpi#1(4)} {g(2).lpi#1(5)} {g(2).lpi#1(6)} {g(2).lpi#1(7)} {g(2).lpi#1(8)} {g(2).lpi#1(9)} {g(2).lpi#1(10)} {g(2).lpi#1(11)} {g(2).lpi#1(12)} {g(2).lpi#1(13)} {g(2).lpi#1(14)} {g(2).lpi#1(15)} -attr xrf 39525 -attr oid 12 -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {r(1).sg1.lpi#1(0)} -attr vt d
+load net {r(1).sg1.lpi#1(1)} -attr vt d
+load net {r(1).sg1.lpi#1(2)} -attr vt d
+load net {r(1).sg1.lpi#1(3)} -attr vt d
+load net {r(1).sg1.lpi#1(4)} -attr vt d
+load net {r(1).sg1.lpi#1(5)} -attr vt d
+load net {r(1).sg1.lpi#1(6)} -attr vt d
+load net {r(1).sg1.lpi#1(7)} -attr vt d
+load net {r(1).sg1.lpi#1(8)} -attr vt d
+load net {r(1).sg1.lpi#1(9)} -attr vt d
+load net {r(1).sg1.lpi#1(10)} -attr vt d
+load net {r(1).sg1.lpi#1(11)} -attr vt d
+load net {r(1).sg1.lpi#1(12)} -attr vt d
+load net {r(1).sg1.lpi#1(13)} -attr vt d
+load net {r(1).sg1.lpi#1(14)} -attr vt d
+load netBundle {r(1).sg1.lpi#1} 15 {r(1).sg1.lpi#1(0)} {r(1).sg1.lpi#1(1)} {r(1).sg1.lpi#1(2)} {r(1).sg1.lpi#1(3)} {r(1).sg1.lpi#1(4)} {r(1).sg1.lpi#1(5)} {r(1).sg1.lpi#1(6)} {r(1).sg1.lpi#1(7)} {r(1).sg1.lpi#1(8)} {r(1).sg1.lpi#1(9)} {r(1).sg1.lpi#1(10)} {r(1).sg1.lpi#1(11)} {r(1).sg1.lpi#1(12)} {r(1).sg1.lpi#1(13)} {r(1).sg1.lpi#1(14)} -attr xrf 39526 -attr oid 13 -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(0).lpi#1(0)} -attr vt d
+load net {r(0).lpi#1(1)} -attr vt d
+load net {r(0).lpi#1(2)} -attr vt d
+load net {r(0).lpi#1(3)} -attr vt d
+load net {r(0).lpi#1(4)} -attr vt d
+load net {r(0).lpi#1(5)} -attr vt d
+load net {r(0).lpi#1(6)} -attr vt d
+load net {r(0).lpi#1(7)} -attr vt d
+load net {r(0).lpi#1(8)} -attr vt d
+load net {r(0).lpi#1(9)} -attr vt d
+load net {r(0).lpi#1(10)} -attr vt d
+load net {r(0).lpi#1(11)} -attr vt d
+load net {r(0).lpi#1(12)} -attr vt d
+load net {r(0).lpi#1(13)} -attr vt d
+load net {r(0).lpi#1(14)} -attr vt d
+load net {r(0).lpi#1(15)} -attr vt d
+load netBundle {r(0).lpi#1} 16 {r(0).lpi#1(0)} {r(0).lpi#1(1)} {r(0).lpi#1(2)} {r(0).lpi#1(3)} {r(0).lpi#1(4)} {r(0).lpi#1(5)} {r(0).lpi#1(6)} {r(0).lpi#1(7)} {r(0).lpi#1(8)} {r(0).lpi#1(9)} {r(0).lpi#1(10)} {r(0).lpi#1(11)} {r(0).lpi#1(12)} {r(0).lpi#1(13)} {r(0).lpi#1(14)} {r(0).lpi#1(15)} -attr xrf 39527 -attr oid 14 -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(2).lpi#1(0)} -attr vt d
+load net {r(2).lpi#1(1)} -attr vt d
+load net {r(2).lpi#1(2)} -attr vt d
+load net {r(2).lpi#1(3)} -attr vt d
+load net {r(2).lpi#1(4)} -attr vt d
+load net {r(2).lpi#1(5)} -attr vt d
+load net {r(2).lpi#1(6)} -attr vt d
+load net {r(2).lpi#1(7)} -attr vt d
+load net {r(2).lpi#1(8)} -attr vt d
+load net {r(2).lpi#1(9)} -attr vt d
+load net {r(2).lpi#1(10)} -attr vt d
+load net {r(2).lpi#1(11)} -attr vt d
+load net {r(2).lpi#1(12)} -attr vt d
+load net {r(2).lpi#1(13)} -attr vt d
+load net {r(2).lpi#1(14)} -attr vt d
+load net {r(2).lpi#1(15)} -attr vt d
+load netBundle {r(2).lpi#1} 16 {r(2).lpi#1(0)} {r(2).lpi#1(1)} {r(2).lpi#1(2)} {r(2).lpi#1(3)} {r(2).lpi#1(4)} {r(2).lpi#1(5)} {r(2).lpi#1(6)} {r(2).lpi#1(7)} {r(2).lpi#1(8)} {r(2).lpi#1(9)} {r(2).lpi#1(10)} {r(2).lpi#1(11)} {r(2).lpi#1(12)} {r(2).lpi#1(13)} {r(2).lpi#1(14)} {r(2).lpi#1(15)} -attr xrf 39528 -attr oid 15 -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {i#6.lpi#1(0)} -attr vt d
+load net {i#6.lpi#1(1)} -attr vt d
+load netBundle {i#6.lpi#1} 2 {i#6.lpi#1(0)} {i#6.lpi#1(1)} -attr xrf 39529 -attr oid 16 -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1}
+load net {i#7.lpi#1(0)} -attr vt d
+load net {i#7.lpi#1(1)} -attr vt d
+load netBundle {i#7.lpi#1} 2 {i#7.lpi#1(0)} {i#7.lpi#1(1)} -attr xrf 39530 -attr oid 17 -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.regs(1).sva(0)} -attr vt d
+load net {regs.regs(1).sva(1)} -attr vt d
+load net {regs.regs(1).sva(2)} -attr vt d
+load net {regs.regs(1).sva(3)} -attr vt d
+load net {regs.regs(1).sva(4)} -attr vt d
+load net {regs.regs(1).sva(5)} -attr vt d
+load net {regs.regs(1).sva(6)} -attr vt d
+load net {regs.regs(1).sva(7)} -attr vt d
+load net {regs.regs(1).sva(8)} -attr vt d
+load net {regs.regs(1).sva(9)} -attr vt d
+load net {regs.regs(1).sva(10)} -attr vt d
+load net {regs.regs(1).sva(11)} -attr vt d
+load net {regs.regs(1).sva(12)} -attr vt d
+load net {regs.regs(1).sva(13)} -attr vt d
+load net {regs.regs(1).sva(14)} -attr vt d
+load net {regs.regs(1).sva(15)} -attr vt d
+load net {regs.regs(1).sva(16)} -attr vt d
+load net {regs.regs(1).sva(17)} -attr vt d
+load net {regs.regs(1).sva(18)} -attr vt d
+load net {regs.regs(1).sva(19)} -attr vt d
+load net {regs.regs(1).sva(20)} -attr vt d
+load net {regs.regs(1).sva(21)} -attr vt d
+load net {regs.regs(1).sva(22)} -attr vt d
+load net {regs.regs(1).sva(23)} -attr vt d
+load net {regs.regs(1).sva(24)} -attr vt d
+load net {regs.regs(1).sva(25)} -attr vt d
+load net {regs.regs(1).sva(26)} -attr vt d
+load net {regs.regs(1).sva(27)} -attr vt d
+load net {regs.regs(1).sva(28)} -attr vt d
+load net {regs.regs(1).sva(29)} -attr vt d
+load net {regs.regs(1).sva(30)} -attr vt d
+load net {regs.regs(1).sva(31)} -attr vt d
+load net {regs.regs(1).sva(32)} -attr vt d
+load net {regs.regs(1).sva(33)} -attr vt d
+load net {regs.regs(1).sva(34)} -attr vt d
+load net {regs.regs(1).sva(35)} -attr vt d
+load net {regs.regs(1).sva(36)} -attr vt d
+load net {regs.regs(1).sva(37)} -attr vt d
+load net {regs.regs(1).sva(38)} -attr vt d
+load net {regs.regs(1).sva(39)} -attr vt d
+load net {regs.regs(1).sva(40)} -attr vt d
+load net {regs.regs(1).sva(41)} -attr vt d
+load net {regs.regs(1).sva(42)} -attr vt d
+load net {regs.regs(1).sva(43)} -attr vt d
+load net {regs.regs(1).sva(44)} -attr vt d
+load net {regs.regs(1).sva(45)} -attr vt d
+load net {regs.regs(1).sva(46)} -attr vt d
+load net {regs.regs(1).sva(47)} -attr vt d
+load net {regs.regs(1).sva(48)} -attr vt d
+load net {regs.regs(1).sva(49)} -attr vt d
+load net {regs.regs(1).sva(50)} -attr vt d
+load net {regs.regs(1).sva(51)} -attr vt d
+load net {regs.regs(1).sva(52)} -attr vt d
+load net {regs.regs(1).sva(53)} -attr vt d
+load net {regs.regs(1).sva(54)} -attr vt d
+load net {regs.regs(1).sva(55)} -attr vt d
+load net {regs.regs(1).sva(56)} -attr vt d
+load net {regs.regs(1).sva(57)} -attr vt d
+load net {regs.regs(1).sva(58)} -attr vt d
+load net {regs.regs(1).sva(59)} -attr vt d
+load net {regs.regs(1).sva(60)} -attr vt d
+load net {regs.regs(1).sva(61)} -attr vt d
+load net {regs.regs(1).sva(62)} -attr vt d
+load net {regs.regs(1).sva(63)} -attr vt d
+load net {regs.regs(1).sva(64)} -attr vt d
+load net {regs.regs(1).sva(65)} -attr vt d
+load net {regs.regs(1).sva(66)} -attr vt d
+load net {regs.regs(1).sva(67)} -attr vt d
+load net {regs.regs(1).sva(68)} -attr vt d
+load net {regs.regs(1).sva(69)} -attr vt d
+load net {regs.regs(1).sva(70)} -attr vt d
+load net {regs.regs(1).sva(71)} -attr vt d
+load net {regs.regs(1).sva(72)} -attr vt d
+load net {regs.regs(1).sva(73)} -attr vt d
+load net {regs.regs(1).sva(74)} -attr vt d
+load net {regs.regs(1).sva(75)} -attr vt d
+load net {regs.regs(1).sva(76)} -attr vt d
+load net {regs.regs(1).sva(77)} -attr vt d
+load net {regs.regs(1).sva(78)} -attr vt d
+load net {regs.regs(1).sva(79)} -attr vt d
+load net {regs.regs(1).sva(80)} -attr vt d
+load net {regs.regs(1).sva(81)} -attr vt d
+load net {regs.regs(1).sva(82)} -attr vt d
+load net {regs.regs(1).sva(83)} -attr vt d
+load net {regs.regs(1).sva(84)} -attr vt d
+load net {regs.regs(1).sva(85)} -attr vt d
+load net {regs.regs(1).sva(86)} -attr vt d
+load net {regs.regs(1).sva(87)} -attr vt d
+load net {regs.regs(1).sva(88)} -attr vt d
+load net {regs.regs(1).sva(89)} -attr vt d
+load netBundle {regs.regs(1).sva} 90 {regs.regs(1).sva(0)} {regs.regs(1).sva(1)} {regs.regs(1).sva(2)} {regs.regs(1).sva(3)} {regs.regs(1).sva(4)} {regs.regs(1).sva(5)} {regs.regs(1).sva(6)} {regs.regs(1).sva(7)} {regs.regs(1).sva(8)} {regs.regs(1).sva(9)} {regs.regs(1).sva(10)} {regs.regs(1).sva(11)} {regs.regs(1).sva(12)} {regs.regs(1).sva(13)} {regs.regs(1).sva(14)} {regs.regs(1).sva(15)} {regs.regs(1).sva(16)} {regs.regs(1).sva(17)} {regs.regs(1).sva(18)} {regs.regs(1).sva(19)} {regs.regs(1).sva(20)} {regs.regs(1).sva(21)} {regs.regs(1).sva(22)} {regs.regs(1).sva(23)} {regs.regs(1).sva(24)} {regs.regs(1).sva(25)} {regs.regs(1).sva(26)} {regs.regs(1).sva(27)} {regs.regs(1).sva(28)} {regs.regs(1).sva(29)} {regs.regs(1).sva(30)} {regs.regs(1).sva(31)} {regs.regs(1).sva(32)} {regs.regs(1).sva(33)} {regs.regs(1).sva(34)} {regs.regs(1).sva(35)} {regs.regs(1).sva(36)} {regs.regs(1).sva(37)} {regs.regs(1).sva(38)} {regs.regs(1).sva(39)} {regs.regs(1).sva(40)} {regs.regs(1).sva(41)} {regs.regs(1).sva(42)} {regs.regs(1).sva(43)} {regs.regs(1).sva(44)} {regs.regs(1).sva(45)} {regs.regs(1).sva(46)} {regs.regs(1).sva(47)} {regs.regs(1).sva(48)} {regs.regs(1).sva(49)} {regs.regs(1).sva(50)} {regs.regs(1).sva(51)} {regs.regs(1).sva(52)} {regs.regs(1).sva(53)} {regs.regs(1).sva(54)} {regs.regs(1).sva(55)} {regs.regs(1).sva(56)} {regs.regs(1).sva(57)} {regs.regs(1).sva(58)} {regs.regs(1).sva(59)} {regs.regs(1).sva(60)} {regs.regs(1).sva(61)} {regs.regs(1).sva(62)} {regs.regs(1).sva(63)} {regs.regs(1).sva(64)} {regs.regs(1).sva(65)} {regs.regs(1).sva(66)} {regs.regs(1).sva(67)} {regs.regs(1).sva(68)} {regs.regs(1).sva(69)} {regs.regs(1).sva(70)} {regs.regs(1).sva(71)} {regs.regs(1).sva(72)} {regs.regs(1).sva(73)} {regs.regs(1).sva(74)} {regs.regs(1).sva(75)} {regs.regs(1).sva(76)} {regs.regs(1).sva(77)} {regs.regs(1).sva(78)} {regs.regs(1).sva(79)} {regs.regs(1).sva(80)} {regs.regs(1).sva(81)} {regs.regs(1).sva(82)} {regs.regs(1).sva(83)} {regs.regs(1).sva(84)} {regs.regs(1).sva(85)} {regs.regs(1).sva(86)} {regs.regs(1).sva(87)} {regs.regs(1).sva(88)} {regs.regs(1).sva(89)} -attr xrf 39531 -attr oid 18 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -attr vt d
+load net {regs.regs(0).sva(1)} -attr vt d
+load net {regs.regs(0).sva(2)} -attr vt d
+load net {regs.regs(0).sva(3)} -attr vt d
+load net {regs.regs(0).sva(4)} -attr vt d
+load net {regs.regs(0).sva(5)} -attr vt d
+load net {regs.regs(0).sva(6)} -attr vt d
+load net {regs.regs(0).sva(7)} -attr vt d
+load net {regs.regs(0).sva(8)} -attr vt d
+load net {regs.regs(0).sva(9)} -attr vt d
+load net {regs.regs(0).sva(10)} -attr vt d
+load net {regs.regs(0).sva(11)} -attr vt d
+load net {regs.regs(0).sva(12)} -attr vt d
+load net {regs.regs(0).sva(13)} -attr vt d
+load net {regs.regs(0).sva(14)} -attr vt d
+load net {regs.regs(0).sva(15)} -attr vt d
+load net {regs.regs(0).sva(16)} -attr vt d
+load net {regs.regs(0).sva(17)} -attr vt d
+load net {regs.regs(0).sva(18)} -attr vt d
+load net {regs.regs(0).sva(19)} -attr vt d
+load net {regs.regs(0).sva(20)} -attr vt d
+load net {regs.regs(0).sva(21)} -attr vt d
+load net {regs.regs(0).sva(22)} -attr vt d
+load net {regs.regs(0).sva(23)} -attr vt d
+load net {regs.regs(0).sva(24)} -attr vt d
+load net {regs.regs(0).sva(25)} -attr vt d
+load net {regs.regs(0).sva(26)} -attr vt d
+load net {regs.regs(0).sva(27)} -attr vt d
+load net {regs.regs(0).sva(28)} -attr vt d
+load net {regs.regs(0).sva(29)} -attr vt d
+load net {regs.regs(0).sva(30)} -attr vt d
+load net {regs.regs(0).sva(31)} -attr vt d
+load net {regs.regs(0).sva(32)} -attr vt d
+load net {regs.regs(0).sva(33)} -attr vt d
+load net {regs.regs(0).sva(34)} -attr vt d
+load net {regs.regs(0).sva(35)} -attr vt d
+load net {regs.regs(0).sva(36)} -attr vt d
+load net {regs.regs(0).sva(37)} -attr vt d
+load net {regs.regs(0).sva(38)} -attr vt d
+load net {regs.regs(0).sva(39)} -attr vt d
+load net {regs.regs(0).sva(40)} -attr vt d
+load net {regs.regs(0).sva(41)} -attr vt d
+load net {regs.regs(0).sva(42)} -attr vt d
+load net {regs.regs(0).sva(43)} -attr vt d
+load net {regs.regs(0).sva(44)} -attr vt d
+load net {regs.regs(0).sva(45)} -attr vt d
+load net {regs.regs(0).sva(46)} -attr vt d
+load net {regs.regs(0).sva(47)} -attr vt d
+load net {regs.regs(0).sva(48)} -attr vt d
+load net {regs.regs(0).sva(49)} -attr vt d
+load net {regs.regs(0).sva(50)} -attr vt d
+load net {regs.regs(0).sva(51)} -attr vt d
+load net {regs.regs(0).sva(52)} -attr vt d
+load net {regs.regs(0).sva(53)} -attr vt d
+load net {regs.regs(0).sva(54)} -attr vt d
+load net {regs.regs(0).sva(55)} -attr vt d
+load net {regs.regs(0).sva(56)} -attr vt d
+load net {regs.regs(0).sva(57)} -attr vt d
+load net {regs.regs(0).sva(58)} -attr vt d
+load net {regs.regs(0).sva(59)} -attr vt d
+load net {regs.regs(0).sva(60)} -attr vt d
+load net {regs.regs(0).sva(61)} -attr vt d
+load net {regs.regs(0).sva(62)} -attr vt d
+load net {regs.regs(0).sva(63)} -attr vt d
+load net {regs.regs(0).sva(64)} -attr vt d
+load net {regs.regs(0).sva(65)} -attr vt d
+load net {regs.regs(0).sva(66)} -attr vt d
+load net {regs.regs(0).sva(67)} -attr vt d
+load net {regs.regs(0).sva(68)} -attr vt d
+load net {regs.regs(0).sva(69)} -attr vt d
+load net {regs.regs(0).sva(70)} -attr vt d
+load net {regs.regs(0).sva(71)} -attr vt d
+load net {regs.regs(0).sva(72)} -attr vt d
+load net {regs.regs(0).sva(73)} -attr vt d
+load net {regs.regs(0).sva(74)} -attr vt d
+load net {regs.regs(0).sva(75)} -attr vt d
+load net {regs.regs(0).sva(76)} -attr vt d
+load net {regs.regs(0).sva(77)} -attr vt d
+load net {regs.regs(0).sva(78)} -attr vt d
+load net {regs.regs(0).sva(79)} -attr vt d
+load net {regs.regs(0).sva(80)} -attr vt d
+load net {regs.regs(0).sva(81)} -attr vt d
+load net {regs.regs(0).sva(82)} -attr vt d
+load net {regs.regs(0).sva(83)} -attr vt d
+load net {regs.regs(0).sva(84)} -attr vt d
+load net {regs.regs(0).sva(85)} -attr vt d
+load net {regs.regs(0).sva(86)} -attr vt d
+load net {regs.regs(0).sva(87)} -attr vt d
+load net {regs.regs(0).sva(88)} -attr vt d
+load net {regs.regs(0).sva(89)} -attr vt d
+load netBundle {regs.regs(0).sva} 90 {regs.regs(0).sva(0)} {regs.regs(0).sva(1)} {regs.regs(0).sva(2)} {regs.regs(0).sva(3)} {regs.regs(0).sva(4)} {regs.regs(0).sva(5)} {regs.regs(0).sva(6)} {regs.regs(0).sva(7)} {regs.regs(0).sva(8)} {regs.regs(0).sva(9)} {regs.regs(0).sva(10)} {regs.regs(0).sva(11)} {regs.regs(0).sva(12)} {regs.regs(0).sva(13)} {regs.regs(0).sva(14)} {regs.regs(0).sva(15)} {regs.regs(0).sva(16)} {regs.regs(0).sva(17)} {regs.regs(0).sva(18)} {regs.regs(0).sva(19)} {regs.regs(0).sva(20)} {regs.regs(0).sva(21)} {regs.regs(0).sva(22)} {regs.regs(0).sva(23)} {regs.regs(0).sva(24)} {regs.regs(0).sva(25)} {regs.regs(0).sva(26)} {regs.regs(0).sva(27)} {regs.regs(0).sva(28)} {regs.regs(0).sva(29)} {regs.regs(0).sva(30)} {regs.regs(0).sva(31)} {regs.regs(0).sva(32)} {regs.regs(0).sva(33)} {regs.regs(0).sva(34)} {regs.regs(0).sva(35)} {regs.regs(0).sva(36)} {regs.regs(0).sva(37)} {regs.regs(0).sva(38)} {regs.regs(0).sva(39)} {regs.regs(0).sva(40)} {regs.regs(0).sva(41)} {regs.regs(0).sva(42)} {regs.regs(0).sva(43)} {regs.regs(0).sva(44)} {regs.regs(0).sva(45)} {regs.regs(0).sva(46)} {regs.regs(0).sva(47)} {regs.regs(0).sva(48)} {regs.regs(0).sva(49)} {regs.regs(0).sva(50)} {regs.regs(0).sva(51)} {regs.regs(0).sva(52)} {regs.regs(0).sva(53)} {regs.regs(0).sva(54)} {regs.regs(0).sva(55)} {regs.regs(0).sva(56)} {regs.regs(0).sva(57)} {regs.regs(0).sva(58)} {regs.regs(0).sva(59)} {regs.regs(0).sva(60)} {regs.regs(0).sva(61)} {regs.regs(0).sva(62)} {regs.regs(0).sva(63)} {regs.regs(0).sva(64)} {regs.regs(0).sva(65)} {regs.regs(0).sva(66)} {regs.regs(0).sva(67)} {regs.regs(0).sva(68)} {regs.regs(0).sva(69)} {regs.regs(0).sva(70)} {regs.regs(0).sva(71)} {regs.regs(0).sva(72)} {regs.regs(0).sva(73)} {regs.regs(0).sva(74)} {regs.regs(0).sva(75)} {regs.regs(0).sva(76)} {regs.regs(0).sva(77)} {regs.regs(0).sva(78)} {regs.regs(0).sva(79)} {regs.regs(0).sva(80)} {regs.regs(0).sva(81)} {regs.regs(0).sva(82)} {regs.regs(0).sva(83)} {regs.regs(0).sva(84)} {regs.regs(0).sva(85)} {regs.regs(0).sva(86)} {regs.regs(0).sva(87)} {regs.regs(0).sva(88)} {regs.regs(0).sva(89)} -attr xrf 39532 -attr oid 19 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(2).lpi#1.dfm(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(29)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(30)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(31)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(32)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(33)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(34)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(35)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(36)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(37)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(38)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(39)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(40)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(41)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(42)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(43)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(44)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(45)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(46)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(47)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(48)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(49)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(50)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(51)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(52)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(53)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(54)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(55)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(56)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(57)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(58)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(59)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(60)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(61)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(62)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(63)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(64)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(65)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(66)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(67)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(68)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(69)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(70)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(71)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(72)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(73)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(74)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(75)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(76)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(77)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(78)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(79)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(80)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(81)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(82)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(83)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(84)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(85)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(86)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(87)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(88)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm(89)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm} 90 {regs.regs(2).lpi#1.dfm(0)} {regs.regs(2).lpi#1.dfm(1)} {regs.regs(2).lpi#1.dfm(2)} {regs.regs(2).lpi#1.dfm(3)} {regs.regs(2).lpi#1.dfm(4)} {regs.regs(2).lpi#1.dfm(5)} {regs.regs(2).lpi#1.dfm(6)} {regs.regs(2).lpi#1.dfm(7)} {regs.regs(2).lpi#1.dfm(8)} {regs.regs(2).lpi#1.dfm(9)} {regs.regs(2).lpi#1.dfm(10)} {regs.regs(2).lpi#1.dfm(11)} {regs.regs(2).lpi#1.dfm(12)} {regs.regs(2).lpi#1.dfm(13)} {regs.regs(2).lpi#1.dfm(14)} {regs.regs(2).lpi#1.dfm(15)} {regs.regs(2).lpi#1.dfm(16)} {regs.regs(2).lpi#1.dfm(17)} {regs.regs(2).lpi#1.dfm(18)} {regs.regs(2).lpi#1.dfm(19)} {regs.regs(2).lpi#1.dfm(20)} {regs.regs(2).lpi#1.dfm(21)} {regs.regs(2).lpi#1.dfm(22)} {regs.regs(2).lpi#1.dfm(23)} {regs.regs(2).lpi#1.dfm(24)} {regs.regs(2).lpi#1.dfm(25)} {regs.regs(2).lpi#1.dfm(26)} {regs.regs(2).lpi#1.dfm(27)} {regs.regs(2).lpi#1.dfm(28)} {regs.regs(2).lpi#1.dfm(29)} {regs.regs(2).lpi#1.dfm(30)} {regs.regs(2).lpi#1.dfm(31)} {regs.regs(2).lpi#1.dfm(32)} {regs.regs(2).lpi#1.dfm(33)} {regs.regs(2).lpi#1.dfm(34)} {regs.regs(2).lpi#1.dfm(35)} {regs.regs(2).lpi#1.dfm(36)} {regs.regs(2).lpi#1.dfm(37)} {regs.regs(2).lpi#1.dfm(38)} {regs.regs(2).lpi#1.dfm(39)} {regs.regs(2).lpi#1.dfm(40)} {regs.regs(2).lpi#1.dfm(41)} {regs.regs(2).lpi#1.dfm(42)} {regs.regs(2).lpi#1.dfm(43)} {regs.regs(2).lpi#1.dfm(44)} {regs.regs(2).lpi#1.dfm(45)} {regs.regs(2).lpi#1.dfm(46)} {regs.regs(2).lpi#1.dfm(47)} {regs.regs(2).lpi#1.dfm(48)} {regs.regs(2).lpi#1.dfm(49)} {regs.regs(2).lpi#1.dfm(50)} {regs.regs(2).lpi#1.dfm(51)} {regs.regs(2).lpi#1.dfm(52)} {regs.regs(2).lpi#1.dfm(53)} {regs.regs(2).lpi#1.dfm(54)} {regs.regs(2).lpi#1.dfm(55)} {regs.regs(2).lpi#1.dfm(56)} {regs.regs(2).lpi#1.dfm(57)} {regs.regs(2).lpi#1.dfm(58)} {regs.regs(2).lpi#1.dfm(59)} {regs.regs(2).lpi#1.dfm(60)} {regs.regs(2).lpi#1.dfm(61)} {regs.regs(2).lpi#1.dfm(62)} {regs.regs(2).lpi#1.dfm(63)} {regs.regs(2).lpi#1.dfm(64)} {regs.regs(2).lpi#1.dfm(65)} {regs.regs(2).lpi#1.dfm(66)} {regs.regs(2).lpi#1.dfm(67)} {regs.regs(2).lpi#1.dfm(68)} {regs.regs(2).lpi#1.dfm(69)} {regs.regs(2).lpi#1.dfm(70)} {regs.regs(2).lpi#1.dfm(71)} {regs.regs(2).lpi#1.dfm(72)} {regs.regs(2).lpi#1.dfm(73)} {regs.regs(2).lpi#1.dfm(74)} {regs.regs(2).lpi#1.dfm(75)} {regs.regs(2).lpi#1.dfm(76)} {regs.regs(2).lpi#1.dfm(77)} {regs.regs(2).lpi#1.dfm(78)} {regs.regs(2).lpi#1.dfm(79)} {regs.regs(2).lpi#1.dfm(80)} {regs.regs(2).lpi#1.dfm(81)} {regs.regs(2).lpi#1.dfm(82)} {regs.regs(2).lpi#1.dfm(83)} {regs.regs(2).lpi#1.dfm(84)} {regs.regs(2).lpi#1.dfm(85)} {regs.regs(2).lpi#1.dfm(86)} {regs.regs(2).lpi#1.dfm(87)} {regs.regs(2).lpi#1.dfm(88)} {regs.regs(2).lpi#1.dfm(89)} -attr xrf 39533 -attr oid 20 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {FRAME:mul#2.itm#1(0)} -attr vt d
+load net {FRAME:mul#2.itm#1(1)} -attr vt d
+load net {FRAME:mul#2.itm#1(2)} -attr vt d
+load net {FRAME:mul#2.itm#1(3)} -attr vt d
+load net {FRAME:mul#2.itm#1(4)} -attr vt d
+load net {FRAME:mul#2.itm#1(5)} -attr vt d
+load net {FRAME:mul#2.itm#1(6)} -attr vt d
+load net {FRAME:mul#2.itm#1(7)} -attr vt d
+load net {FRAME:mul#2.itm#1(8)} -attr vt d
+load net {FRAME:mul#2.itm#1(9)} -attr vt d
+load net {FRAME:mul#2.itm#1(10)} -attr vt d
+load netBundle {FRAME:mul#2.itm#1} 11 {FRAME:mul#2.itm#1(0)} {FRAME:mul#2.itm#1(1)} {FRAME:mul#2.itm#1(2)} {FRAME:mul#2.itm#1(3)} {FRAME:mul#2.itm#1(4)} {FRAME:mul#2.itm#1(5)} {FRAME:mul#2.itm#1(6)} {FRAME:mul#2.itm#1(7)} {FRAME:mul#2.itm#1(8)} {FRAME:mul#2.itm#1(9)} {FRAME:mul#2.itm#1(10)} -attr xrf 39534 -attr oid 21 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#3.itm#1(0)} -attr vt d
+load net {FRAME:mul#3.itm#1(1)} -attr vt d
+load net {FRAME:mul#3.itm#1(2)} -attr vt d
+load net {FRAME:mul#3.itm#1(3)} -attr vt d
+load net {FRAME:mul#3.itm#1(4)} -attr vt d
+load net {FRAME:mul#3.itm#1(5)} -attr vt d
+load net {FRAME:mul#3.itm#1(6)} -attr vt d
+load net {FRAME:mul#3.itm#1(7)} -attr vt d
+load net {FRAME:mul#3.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#3.itm#1} 9 {FRAME:mul#3.itm#1(0)} {FRAME:mul#3.itm#1(1)} {FRAME:mul#3.itm#1(2)} {FRAME:mul#3.itm#1(3)} {FRAME:mul#3.itm#1(4)} {FRAME:mul#3.itm#1(5)} {FRAME:mul#3.itm#1(6)} {FRAME:mul#3.itm#1(7)} {FRAME:mul#3.itm#1(8)} -attr xrf 39535 -attr oid 22 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {green:slc(green#2.sg1).itm#1(0)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(1)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(2)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(3)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(4)} -attr vt d
+load net {green:slc(green#2.sg1).itm#1(5)} -attr vt d
+load netBundle {green:slc(green#2.sg1).itm#1} 6 {green:slc(green#2.sg1).itm#1(0)} {green:slc(green#2.sg1).itm#1(1)} {green:slc(green#2.sg1).itm#1(2)} {green:slc(green#2.sg1).itm#1(3)} {green:slc(green#2.sg1).itm#1(4)} {green:slc(green#2.sg1).itm#1(5)} -attr xrf 39536 -attr oid 23 -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {FRAME:acc#18.itm#1(0)} -attr vt d
+load net {FRAME:acc#18.itm#1(1)} -attr vt d
+load net {FRAME:acc#18.itm#1(2)} -attr vt d
+load net {FRAME:acc#18.itm#1(3)} -attr vt d
+load net {FRAME:acc#18.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#18.itm#1} 5 {FRAME:acc#18.itm#1(0)} {FRAME:acc#18.itm#1(1)} {FRAME:acc#18.itm#1(2)} {FRAME:acc#18.itm#1(3)} {FRAME:acc#18.itm#1(4)} -attr xrf 39537 -attr oid 24 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:mul#4.itm#1(0)} -attr vt d
+load net {FRAME:mul#4.itm#1(1)} -attr vt d
+load net {FRAME:mul#4.itm#1(2)} -attr vt d
+load net {FRAME:mul#4.itm#1(3)} -attr vt d
+load net {FRAME:mul#4.itm#1(4)} -attr vt d
+load net {FRAME:mul#4.itm#1(5)} -attr vt d
+load net {FRAME:mul#4.itm#1(6)} -attr vt d
+load net {FRAME:mul#4.itm#1(7)} -attr vt d
+load net {FRAME:mul#4.itm#1(8)} -attr vt d
+load net {FRAME:mul#4.itm#1(9)} -attr vt d
+load net {FRAME:mul#4.itm#1(10)} -attr vt d
+load netBundle {FRAME:mul#4.itm#1} 11 {FRAME:mul#4.itm#1(0)} {FRAME:mul#4.itm#1(1)} {FRAME:mul#4.itm#1(2)} {FRAME:mul#4.itm#1(3)} {FRAME:mul#4.itm#1(4)} {FRAME:mul#4.itm#1(5)} {FRAME:mul#4.itm#1(6)} {FRAME:mul#4.itm#1(7)} {FRAME:mul#4.itm#1(8)} {FRAME:mul#4.itm#1(9)} {FRAME:mul#4.itm#1(10)} -attr xrf 39538 -attr oid 25 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#5.itm#1(0)} -attr vt d
+load net {FRAME:mul#5.itm#1(1)} -attr vt d
+load net {FRAME:mul#5.itm#1(2)} -attr vt d
+load net {FRAME:mul#5.itm#1(3)} -attr vt d
+load net {FRAME:mul#5.itm#1(4)} -attr vt d
+load net {FRAME:mul#5.itm#1(5)} -attr vt d
+load net {FRAME:mul#5.itm#1(6)} -attr vt d
+load net {FRAME:mul#5.itm#1(7)} -attr vt d
+load net {FRAME:mul#5.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#5.itm#1} 9 {FRAME:mul#5.itm#1(0)} {FRAME:mul#5.itm#1(1)} {FRAME:mul#5.itm#1(2)} {FRAME:mul#5.itm#1(3)} {FRAME:mul#5.itm#1(4)} {FRAME:mul#5.itm#1(5)} {FRAME:mul#5.itm#1(6)} {FRAME:mul#5.itm#1(7)} {FRAME:mul#5.itm#1(8)} -attr xrf 39539 -attr oid 26 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(0)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(1)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(2)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(3)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(4)} -attr vt d
+load net {blue:slc(blue#2.sg1).itm#1(5)} -attr vt d
+load netBundle {blue:slc(blue#2.sg1).itm#1} 6 {blue:slc(blue#2.sg1).itm#1(0)} {blue:slc(blue#2.sg1).itm#1(1)} {blue:slc(blue#2.sg1).itm#1(2)} {blue:slc(blue#2.sg1).itm#1(3)} {blue:slc(blue#2.sg1).itm#1(4)} {blue:slc(blue#2.sg1).itm#1(5)} -attr xrf 39540 -attr oid 27 -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {FRAME:acc#30.itm#1(0)} -attr vt d
+load net {FRAME:acc#30.itm#1(1)} -attr vt d
+load net {FRAME:acc#30.itm#1(2)} -attr vt d
+load net {FRAME:acc#30.itm#1(3)} -attr vt d
+load net {FRAME:acc#30.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#30.itm#1} 5 {FRAME:acc#30.itm#1(0)} {FRAME:acc#30.itm#1(1)} {FRAME:acc#30.itm#1(2)} {FRAME:acc#30.itm#1(3)} {FRAME:acc#30.itm#1(4)} -attr xrf 39541 -attr oid 28 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:mul#1.itm#1(0)} -attr vt d
+load net {FRAME:mul#1.itm#1(1)} -attr vt d
+load net {FRAME:mul#1.itm#1(2)} -attr vt d
+load net {FRAME:mul#1.itm#1(3)} -attr vt d
+load net {FRAME:mul#1.itm#1(4)} -attr vt d
+load net {FRAME:mul#1.itm#1(5)} -attr vt d
+load net {FRAME:mul#1.itm#1(6)} -attr vt d
+load net {FRAME:mul#1.itm#1(7)} -attr vt d
+load net {FRAME:mul#1.itm#1(8)} -attr vt d
+load netBundle {FRAME:mul#1.itm#1} 9 {FRAME:mul#1.itm#1(0)} {FRAME:mul#1.itm#1(1)} {FRAME:mul#1.itm#1(2)} {FRAME:mul#1.itm#1(3)} {FRAME:mul#1.itm#1(4)} {FRAME:mul#1.itm#1(5)} {FRAME:mul#1.itm#1(6)} {FRAME:mul#1.itm#1(7)} {FRAME:mul#1.itm#1(8)} -attr xrf 39542 -attr oid 29 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {red:slc(red#2.sg1).itm#1(0)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(1)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(2)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(3)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(4)} -attr vt d
+load net {red:slc(red#2.sg1).itm#1(5)} -attr vt d
+load netBundle {red:slc(red#2.sg1).itm#1} 6 {red:slc(red#2.sg1).itm#1(0)} {red:slc(red#2.sg1).itm#1(1)} {red:slc(red#2.sg1).itm#1(2)} {red:slc(red#2.sg1).itm#1(3)} {red:slc(red#2.sg1).itm#1(4)} {red:slc(red#2.sg1).itm#1(5)} -attr xrf 39543 -attr oid 30 -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {FRAME:acc#37.itm#1(0)} -attr vt d
+load net {FRAME:acc#37.itm#1(1)} -attr vt d
+load net {FRAME:acc#37.itm#1(2)} -attr vt d
+load net {FRAME:acc#37.itm#1(3)} -attr vt d
+load net {FRAME:acc#37.itm#1(4)} -attr vt d
+load netBundle {FRAME:acc#37.itm#1} 5 {FRAME:acc#37.itm#1(0)} {FRAME:acc#37.itm#1(1)} {FRAME:acc#37.itm#1(2)} {FRAME:acc#37.itm#1(3)} {FRAME:acc#37.itm#1(4)} -attr xrf 39544 -attr oid 31 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#41.itm#1.sg2(0)} -attr vt d
+load net {FRAME:acc#41.itm#1.sg2(1)} -attr vt d
+load netBundle {FRAME:acc#41.itm#1.sg2} 2 {FRAME:acc#41.itm#1.sg2(0)} {FRAME:acc#41.itm#1.sg2(1)} -attr xrf 39545 -attr oid 32 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg2}
+load net {FRAME:acc#41.itm#1.sg1(0)} -attr vt d
+load net {FRAME:acc#41.itm#1.sg1(1)} -attr vt d
+load netBundle {FRAME:acc#41.itm#1.sg1} 2 {FRAME:acc#41.itm#1.sg1(0)} {FRAME:acc#41.itm#1.sg1(1)} -attr xrf 39546 -attr oid 33 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg1}
+load net {FRAME:acc#41.itm#3(0)} -attr vt d
+load net {FRAME:acc#41.itm#3(1)} -attr vt d
+load net {FRAME:acc#41.itm#3(2)} -attr vt d
+load net {FRAME:acc#41.itm#3(3)} -attr vt d
+load net {FRAME:acc#41.itm#3(4)} -attr vt d
+load net {FRAME:acc#41.itm#3(5)} -attr vt d
+load netBundle {FRAME:acc#41.itm#3} 6 {FRAME:acc#41.itm#3(0)} {FRAME:acc#41.itm#3(1)} {FRAME:acc#41.itm#3(2)} {FRAME:acc#41.itm#3(3)} {FRAME:acc#41.itm#3(4)} {FRAME:acc#41.itm#3(5)} -attr xrf 39547 -attr oid 34 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#3.psp.sva(0)} -attr vt d
+load net {FRAME:acc#3.psp.sva(1)} -attr vt d
+load net {FRAME:acc#3.psp.sva(2)} -attr vt d
+load net {FRAME:acc#3.psp.sva(3)} -attr vt d
+load net {FRAME:acc#3.psp.sva(4)} -attr vt d
+load net {FRAME:acc#3.psp.sva(5)} -attr vt d
+load net {FRAME:acc#3.psp.sva(6)} -attr vt d
+load net {FRAME:acc#3.psp.sva(7)} -attr vt d
+load net {FRAME:acc#3.psp.sva(8)} -attr vt d
+load net {FRAME:acc#3.psp.sva(9)} -attr vt d
+load net {FRAME:acc#3.psp.sva(10)} -attr vt d
+load net {FRAME:acc#3.psp.sva(11)} -attr vt d
+load netBundle {FRAME:acc#3.psp.sva} 12 {FRAME:acc#3.psp.sva(0)} {FRAME:acc#3.psp.sva(1)} {FRAME:acc#3.psp.sva(2)} {FRAME:acc#3.psp.sva(3)} {FRAME:acc#3.psp.sva(4)} {FRAME:acc#3.psp.sva(5)} {FRAME:acc#3.psp.sva(6)} {FRAME:acc#3.psp.sva(7)} {FRAME:acc#3.psp.sva(8)} {FRAME:acc#3.psp.sva(9)} {FRAME:acc#3.psp.sva(10)} {FRAME:acc#3.psp.sva(11)} -attr xrf 39548 -attr oid 35 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#3.psp.sva}
+load net {FRAME:acc#4.psp.sva(0)} -attr vt d
+load net {FRAME:acc#4.psp.sva(1)} -attr vt d
+load net {FRAME:acc#4.psp.sva(2)} -attr vt d
+load net {FRAME:acc#4.psp.sva(3)} -attr vt d
+load net {FRAME:acc#4.psp.sva(4)} -attr vt d
+load net {FRAME:acc#4.psp.sva(5)} -attr vt d
+load net {FRAME:acc#4.psp.sva(6)} -attr vt d
+load net {FRAME:acc#4.psp.sva(7)} -attr vt d
+load net {FRAME:acc#4.psp.sva(8)} -attr vt d
+load net {FRAME:acc#4.psp.sva(9)} -attr vt d
+load net {FRAME:acc#4.psp.sva(10)} -attr vt d
+load net {FRAME:acc#4.psp.sva(11)} -attr vt d
+load netBundle {FRAME:acc#4.psp.sva} 12 {FRAME:acc#4.psp.sva(0)} {FRAME:acc#4.psp.sva(1)} {FRAME:acc#4.psp.sva(2)} {FRAME:acc#4.psp.sva(3)} {FRAME:acc#4.psp.sva(4)} {FRAME:acc#4.psp.sva(5)} {FRAME:acc#4.psp.sva(6)} {FRAME:acc#4.psp.sva(7)} {FRAME:acc#4.psp.sva(8)} {FRAME:acc#4.psp.sva(9)} {FRAME:acc#4.psp.sva(10)} {FRAME:acc#4.psp.sva(11)} -attr xrf 39549 -attr oid 36 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {i#7.sva(0)} -attr vt d
+load net {i#7.sva(1)} -attr vt d
+load netBundle {i#7.sva} 2 {i#7.sva(0)} {i#7.sva(1)} -attr xrf 39550 -attr oid 37 -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -attr vt d
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(2).lpi#1.dfm:mx0} 90 {regs.regs(2).lpi#1.dfm:mx0(0)} {regs.regs(2).lpi#1.dfm:mx0(1)} {regs.regs(2).lpi#1.dfm:mx0(2)} {regs.regs(2).lpi#1.dfm:mx0(3)} {regs.regs(2).lpi#1.dfm:mx0(4)} {regs.regs(2).lpi#1.dfm:mx0(5)} {regs.regs(2).lpi#1.dfm:mx0(6)} {regs.regs(2).lpi#1.dfm:mx0(7)} {regs.regs(2).lpi#1.dfm:mx0(8)} {regs.regs(2).lpi#1.dfm:mx0(9)} {regs.regs(2).lpi#1.dfm:mx0(10)} {regs.regs(2).lpi#1.dfm:mx0(11)} {regs.regs(2).lpi#1.dfm:mx0(12)} {regs.regs(2).lpi#1.dfm:mx0(13)} {regs.regs(2).lpi#1.dfm:mx0(14)} {regs.regs(2).lpi#1.dfm:mx0(15)} {regs.regs(2).lpi#1.dfm:mx0(16)} {regs.regs(2).lpi#1.dfm:mx0(17)} {regs.regs(2).lpi#1.dfm:mx0(18)} {regs.regs(2).lpi#1.dfm:mx0(19)} {regs.regs(2).lpi#1.dfm:mx0(20)} {regs.regs(2).lpi#1.dfm:mx0(21)} {regs.regs(2).lpi#1.dfm:mx0(22)} {regs.regs(2).lpi#1.dfm:mx0(23)} {regs.regs(2).lpi#1.dfm:mx0(24)} {regs.regs(2).lpi#1.dfm:mx0(25)} {regs.regs(2).lpi#1.dfm:mx0(26)} {regs.regs(2).lpi#1.dfm:mx0(27)} {regs.regs(2).lpi#1.dfm:mx0(28)} {regs.regs(2).lpi#1.dfm:mx0(29)} {regs.regs(2).lpi#1.dfm:mx0(30)} {regs.regs(2).lpi#1.dfm:mx0(31)} {regs.regs(2).lpi#1.dfm:mx0(32)} {regs.regs(2).lpi#1.dfm:mx0(33)} {regs.regs(2).lpi#1.dfm:mx0(34)} {regs.regs(2).lpi#1.dfm:mx0(35)} {regs.regs(2).lpi#1.dfm:mx0(36)} {regs.regs(2).lpi#1.dfm:mx0(37)} {regs.regs(2).lpi#1.dfm:mx0(38)} {regs.regs(2).lpi#1.dfm:mx0(39)} {regs.regs(2).lpi#1.dfm:mx0(40)} {regs.regs(2).lpi#1.dfm:mx0(41)} {regs.regs(2).lpi#1.dfm:mx0(42)} {regs.regs(2).lpi#1.dfm:mx0(43)} {regs.regs(2).lpi#1.dfm:mx0(44)} {regs.regs(2).lpi#1.dfm:mx0(45)} {regs.regs(2).lpi#1.dfm:mx0(46)} {regs.regs(2).lpi#1.dfm:mx0(47)} {regs.regs(2).lpi#1.dfm:mx0(48)} {regs.regs(2).lpi#1.dfm:mx0(49)} {regs.regs(2).lpi#1.dfm:mx0(50)} {regs.regs(2).lpi#1.dfm:mx0(51)} {regs.regs(2).lpi#1.dfm:mx0(52)} {regs.regs(2).lpi#1.dfm:mx0(53)} {regs.regs(2).lpi#1.dfm:mx0(54)} {regs.regs(2).lpi#1.dfm:mx0(55)} {regs.regs(2).lpi#1.dfm:mx0(56)} {regs.regs(2).lpi#1.dfm:mx0(57)} {regs.regs(2).lpi#1.dfm:mx0(58)} {regs.regs(2).lpi#1.dfm:mx0(59)} {regs.regs(2).lpi#1.dfm:mx0(60)} {regs.regs(2).lpi#1.dfm:mx0(61)} {regs.regs(2).lpi#1.dfm:mx0(62)} {regs.regs(2).lpi#1.dfm:mx0(63)} {regs.regs(2).lpi#1.dfm:mx0(64)} {regs.regs(2).lpi#1.dfm:mx0(65)} {regs.regs(2).lpi#1.dfm:mx0(66)} {regs.regs(2).lpi#1.dfm:mx0(67)} {regs.regs(2).lpi#1.dfm:mx0(68)} {regs.regs(2).lpi#1.dfm:mx0(69)} {regs.regs(2).lpi#1.dfm:mx0(70)} {regs.regs(2).lpi#1.dfm:mx0(71)} {regs.regs(2).lpi#1.dfm:mx0(72)} {regs.regs(2).lpi#1.dfm:mx0(73)} {regs.regs(2).lpi#1.dfm:mx0(74)} {regs.regs(2).lpi#1.dfm:mx0(75)} {regs.regs(2).lpi#1.dfm:mx0(76)} {regs.regs(2).lpi#1.dfm:mx0(77)} {regs.regs(2).lpi#1.dfm:mx0(78)} {regs.regs(2).lpi#1.dfm:mx0(79)} {regs.regs(2).lpi#1.dfm:mx0(80)} {regs.regs(2).lpi#1.dfm:mx0(81)} {regs.regs(2).lpi#1.dfm:mx0(82)} {regs.regs(2).lpi#1.dfm:mx0(83)} {regs.regs(2).lpi#1.dfm:mx0(84)} {regs.regs(2).lpi#1.dfm:mx0(85)} {regs.regs(2).lpi#1.dfm:mx0(86)} {regs.regs(2).lpi#1.dfm:mx0(87)} {regs.regs(2).lpi#1.dfm:mx0(88)} {regs.regs(2).lpi#1.dfm:mx0(89)} -attr xrf 39551 -attr oid 38 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(1).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(1).sva.dfm:mx0} 90 {regs.regs(1).sva.dfm:mx0(0)} {regs.regs(1).sva.dfm:mx0(1)} {regs.regs(1).sva.dfm:mx0(2)} {regs.regs(1).sva.dfm:mx0(3)} {regs.regs(1).sva.dfm:mx0(4)} {regs.regs(1).sva.dfm:mx0(5)} {regs.regs(1).sva.dfm:mx0(6)} {regs.regs(1).sva.dfm:mx0(7)} {regs.regs(1).sva.dfm:mx0(8)} {regs.regs(1).sva.dfm:mx0(9)} {regs.regs(1).sva.dfm:mx0(10)} {regs.regs(1).sva.dfm:mx0(11)} {regs.regs(1).sva.dfm:mx0(12)} {regs.regs(1).sva.dfm:mx0(13)} {regs.regs(1).sva.dfm:mx0(14)} {regs.regs(1).sva.dfm:mx0(15)} {regs.regs(1).sva.dfm:mx0(16)} {regs.regs(1).sva.dfm:mx0(17)} {regs.regs(1).sva.dfm:mx0(18)} {regs.regs(1).sva.dfm:mx0(19)} {regs.regs(1).sva.dfm:mx0(20)} {regs.regs(1).sva.dfm:mx0(21)} {regs.regs(1).sva.dfm:mx0(22)} {regs.regs(1).sva.dfm:mx0(23)} {regs.regs(1).sva.dfm:mx0(24)} {regs.regs(1).sva.dfm:mx0(25)} {regs.regs(1).sva.dfm:mx0(26)} {regs.regs(1).sva.dfm:mx0(27)} {regs.regs(1).sva.dfm:mx0(28)} {regs.regs(1).sva.dfm:mx0(29)} {regs.regs(1).sva.dfm:mx0(30)} {regs.regs(1).sva.dfm:mx0(31)} {regs.regs(1).sva.dfm:mx0(32)} {regs.regs(1).sva.dfm:mx0(33)} {regs.regs(1).sva.dfm:mx0(34)} {regs.regs(1).sva.dfm:mx0(35)} {regs.regs(1).sva.dfm:mx0(36)} {regs.regs(1).sva.dfm:mx0(37)} {regs.regs(1).sva.dfm:mx0(38)} {regs.regs(1).sva.dfm:mx0(39)} {regs.regs(1).sva.dfm:mx0(40)} {regs.regs(1).sva.dfm:mx0(41)} {regs.regs(1).sva.dfm:mx0(42)} {regs.regs(1).sva.dfm:mx0(43)} {regs.regs(1).sva.dfm:mx0(44)} {regs.regs(1).sva.dfm:mx0(45)} {regs.regs(1).sva.dfm:mx0(46)} {regs.regs(1).sva.dfm:mx0(47)} {regs.regs(1).sva.dfm:mx0(48)} {regs.regs(1).sva.dfm:mx0(49)} {regs.regs(1).sva.dfm:mx0(50)} {regs.regs(1).sva.dfm:mx0(51)} {regs.regs(1).sva.dfm:mx0(52)} {regs.regs(1).sva.dfm:mx0(53)} {regs.regs(1).sva.dfm:mx0(54)} {regs.regs(1).sva.dfm:mx0(55)} {regs.regs(1).sva.dfm:mx0(56)} {regs.regs(1).sva.dfm:mx0(57)} {regs.regs(1).sva.dfm:mx0(58)} {regs.regs(1).sva.dfm:mx0(59)} {regs.regs(1).sva.dfm:mx0(60)} {regs.regs(1).sva.dfm:mx0(61)} {regs.regs(1).sva.dfm:mx0(62)} {regs.regs(1).sva.dfm:mx0(63)} {regs.regs(1).sva.dfm:mx0(64)} {regs.regs(1).sva.dfm:mx0(65)} {regs.regs(1).sva.dfm:mx0(66)} {regs.regs(1).sva.dfm:mx0(67)} {regs.regs(1).sva.dfm:mx0(68)} {regs.regs(1).sva.dfm:mx0(69)} {regs.regs(1).sva.dfm:mx0(70)} {regs.regs(1).sva.dfm:mx0(71)} {regs.regs(1).sva.dfm:mx0(72)} {regs.regs(1).sva.dfm:mx0(73)} {regs.regs(1).sva.dfm:mx0(74)} {regs.regs(1).sva.dfm:mx0(75)} {regs.regs(1).sva.dfm:mx0(76)} {regs.regs(1).sva.dfm:mx0(77)} {regs.regs(1).sva.dfm:mx0(78)} {regs.regs(1).sva.dfm:mx0(79)} {regs.regs(1).sva.dfm:mx0(80)} {regs.regs(1).sva.dfm:mx0(81)} {regs.regs(1).sva.dfm:mx0(82)} {regs.regs(1).sva.dfm:mx0(83)} {regs.regs(1).sva.dfm:mx0(84)} {regs.regs(1).sva.dfm:mx0(85)} {regs.regs(1).sva.dfm:mx0(86)} {regs.regs(1).sva.dfm:mx0(87)} {regs.regs(1).sva.dfm:mx0(88)} {regs.regs(1).sva.dfm:mx0(89)} -attr xrf 39552 -attr oid 39 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(0)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(1)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(2)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(3)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(4)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(5)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(6)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(7)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(8)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(9)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(10)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(11)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(12)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(13)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(14)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(15)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(16)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(17)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(18)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(19)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(20)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(21)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(22)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(23)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(24)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(25)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(26)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(27)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(28)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(29)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(30)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(31)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(32)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(33)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(34)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(35)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(36)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(37)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(38)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(39)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(40)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(41)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(42)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(43)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(44)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(45)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(46)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(47)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(48)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(49)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(50)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(51)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(52)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(53)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(54)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(55)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(56)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(57)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(58)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(59)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(60)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(61)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(62)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(63)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(64)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(65)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(66)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(67)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(68)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(69)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(70)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(71)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(72)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(73)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(74)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(75)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(76)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(77)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(78)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(79)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(80)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(81)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(82)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(83)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(84)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(85)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(86)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(87)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(88)} -attr vt d
+load net {regs.regs(0).sva.dfm:mx0(89)} -attr vt d
+load netBundle {regs.regs(0).sva.dfm:mx0} 90 {regs.regs(0).sva.dfm:mx0(0)} {regs.regs(0).sva.dfm:mx0(1)} {regs.regs(0).sva.dfm:mx0(2)} {regs.regs(0).sva.dfm:mx0(3)} {regs.regs(0).sva.dfm:mx0(4)} {regs.regs(0).sva.dfm:mx0(5)} {regs.regs(0).sva.dfm:mx0(6)} {regs.regs(0).sva.dfm:mx0(7)} {regs.regs(0).sva.dfm:mx0(8)} {regs.regs(0).sva.dfm:mx0(9)} {regs.regs(0).sva.dfm:mx0(10)} {regs.regs(0).sva.dfm:mx0(11)} {regs.regs(0).sva.dfm:mx0(12)} {regs.regs(0).sva.dfm:mx0(13)} {regs.regs(0).sva.dfm:mx0(14)} {regs.regs(0).sva.dfm:mx0(15)} {regs.regs(0).sva.dfm:mx0(16)} {regs.regs(0).sva.dfm:mx0(17)} {regs.regs(0).sva.dfm:mx0(18)} {regs.regs(0).sva.dfm:mx0(19)} {regs.regs(0).sva.dfm:mx0(20)} {regs.regs(0).sva.dfm:mx0(21)} {regs.regs(0).sva.dfm:mx0(22)} {regs.regs(0).sva.dfm:mx0(23)} {regs.regs(0).sva.dfm:mx0(24)} {regs.regs(0).sva.dfm:mx0(25)} {regs.regs(0).sva.dfm:mx0(26)} {regs.regs(0).sva.dfm:mx0(27)} {regs.regs(0).sva.dfm:mx0(28)} {regs.regs(0).sva.dfm:mx0(29)} {regs.regs(0).sva.dfm:mx0(30)} {regs.regs(0).sva.dfm:mx0(31)} {regs.regs(0).sva.dfm:mx0(32)} {regs.regs(0).sva.dfm:mx0(33)} {regs.regs(0).sva.dfm:mx0(34)} {regs.regs(0).sva.dfm:mx0(35)} {regs.regs(0).sva.dfm:mx0(36)} {regs.regs(0).sva.dfm:mx0(37)} {regs.regs(0).sva.dfm:mx0(38)} {regs.regs(0).sva.dfm:mx0(39)} {regs.regs(0).sva.dfm:mx0(40)} {regs.regs(0).sva.dfm:mx0(41)} {regs.regs(0).sva.dfm:mx0(42)} {regs.regs(0).sva.dfm:mx0(43)} {regs.regs(0).sva.dfm:mx0(44)} {regs.regs(0).sva.dfm:mx0(45)} {regs.regs(0).sva.dfm:mx0(46)} {regs.regs(0).sva.dfm:mx0(47)} {regs.regs(0).sva.dfm:mx0(48)} {regs.regs(0).sva.dfm:mx0(49)} {regs.regs(0).sva.dfm:mx0(50)} {regs.regs(0).sva.dfm:mx0(51)} {regs.regs(0).sva.dfm:mx0(52)} {regs.regs(0).sva.dfm:mx0(53)} {regs.regs(0).sva.dfm:mx0(54)} {regs.regs(0).sva.dfm:mx0(55)} {regs.regs(0).sva.dfm:mx0(56)} {regs.regs(0).sva.dfm:mx0(57)} {regs.regs(0).sva.dfm:mx0(58)} {regs.regs(0).sva.dfm:mx0(59)} {regs.regs(0).sva.dfm:mx0(60)} {regs.regs(0).sva.dfm:mx0(61)} {regs.regs(0).sva.dfm:mx0(62)} {regs.regs(0).sva.dfm:mx0(63)} {regs.regs(0).sva.dfm:mx0(64)} {regs.regs(0).sva.dfm:mx0(65)} {regs.regs(0).sva.dfm:mx0(66)} {regs.regs(0).sva.dfm:mx0(67)} {regs.regs(0).sva.dfm:mx0(68)} {regs.regs(0).sva.dfm:mx0(69)} {regs.regs(0).sva.dfm:mx0(70)} {regs.regs(0).sva.dfm:mx0(71)} {regs.regs(0).sva.dfm:mx0(72)} {regs.regs(0).sva.dfm:mx0(73)} {regs.regs(0).sva.dfm:mx0(74)} {regs.regs(0).sva.dfm:mx0(75)} {regs.regs(0).sva.dfm:mx0(76)} {regs.regs(0).sva.dfm:mx0(77)} {regs.regs(0).sva.dfm:mx0(78)} {regs.regs(0).sva.dfm:mx0(79)} {regs.regs(0).sva.dfm:mx0(80)} {regs.regs(0).sva.dfm:mx0(81)} {regs.regs(0).sva.dfm:mx0(82)} {regs.regs(0).sva.dfm:mx0(83)} {regs.regs(0).sva.dfm:mx0(84)} {regs.regs(0).sva.dfm:mx0(85)} {regs.regs(0).sva.dfm:mx0(86)} {regs.regs(0).sva.dfm:mx0(87)} {regs.regs(0).sva.dfm:mx0(88)} {regs.regs(0).sva.dfm:mx0(89)} -attr xrf 39553 -attr oid 40 -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {FRAME:p#1.sva#1(0)} -attr vt d
+load net {FRAME:p#1.sva#1(1)} -attr vt d
+load net {FRAME:p#1.sva#1(2)} -attr vt d
+load net {FRAME:p#1.sva#1(3)} -attr vt d
+load net {FRAME:p#1.sva#1(4)} -attr vt d
+load net {FRAME:p#1.sva#1(5)} -attr vt d
+load net {FRAME:p#1.sva#1(6)} -attr vt d
+load net {FRAME:p#1.sva#1(7)} -attr vt d
+load net {FRAME:p#1.sva#1(8)} -attr vt d
+load net {FRAME:p#1.sva#1(9)} -attr vt d
+load net {FRAME:p#1.sva#1(10)} -attr vt d
+load net {FRAME:p#1.sva#1(11)} -attr vt d
+load net {FRAME:p#1.sva#1(12)} -attr vt d
+load net {FRAME:p#1.sva#1(13)} -attr vt d
+load net {FRAME:p#1.sva#1(14)} -attr vt d
+load net {FRAME:p#1.sva#1(15)} -attr vt d
+load net {FRAME:p#1.sva#1(16)} -attr vt d
+load net {FRAME:p#1.sva#1(17)} -attr vt d
+load net {FRAME:p#1.sva#1(18)} -attr vt d
+load netBundle {FRAME:p#1.sva#1} 19 {FRAME:p#1.sva#1(0)} {FRAME:p#1.sva#1(1)} {FRAME:p#1.sva#1(2)} {FRAME:p#1.sva#1(3)} {FRAME:p#1.sva#1(4)} {FRAME:p#1.sva#1(5)} {FRAME:p#1.sva#1(6)} {FRAME:p#1.sva#1(7)} {FRAME:p#1.sva#1(8)} {FRAME:p#1.sva#1(9)} {FRAME:p#1.sva#1(10)} {FRAME:p#1.sva#1(11)} {FRAME:p#1.sva#1(12)} {FRAME:p#1.sva#1(13)} {FRAME:p#1.sva#1(14)} {FRAME:p#1.sva#1(15)} {FRAME:p#1.sva#1(16)} {FRAME:p#1.sva#1(17)} {FRAME:p#1.sva#1(18)} -attr xrf 39554 -attr oid 41 -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.lpi#1.dfm(0)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(1)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(2)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(3)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(4)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(5)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(6)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(7)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(8)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(9)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(10)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(11)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(12)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(13)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(14)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(15)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(16)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(17)} -attr vt d
+load net {FRAME:p#1.lpi#1.dfm(18)} -attr vt d
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+load net {b(2).lpi#1.dfm(0)} -attr vt d
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+load net {g(2).lpi#1.dfm(0)} -attr vt d
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+load net {r(2).lpi#1.dfm(0)} -attr vt d
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+load net {b(0).lpi#1.dfm(0)} -attr vt d
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+load net {g(0).lpi#1.dfm(0)} -attr vt d
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+load netBundle {g(0).lpi#1.dfm} 16 {g(0).lpi#1.dfm(0)} {g(0).lpi#1.dfm(1)} {g(0).lpi#1.dfm(2)} {g(0).lpi#1.dfm(3)} {g(0).lpi#1.dfm(4)} {g(0).lpi#1.dfm(5)} {g(0).lpi#1.dfm(6)} {g(0).lpi#1.dfm(7)} {g(0).lpi#1.dfm(8)} {g(0).lpi#1.dfm(9)} {g(0).lpi#1.dfm(10)} {g(0).lpi#1.dfm(11)} {g(0).lpi#1.dfm(12)} {g(0).lpi#1.dfm(13)} {g(0).lpi#1.dfm(14)} {g(0).lpi#1.dfm(15)} -attr xrf 39576 -attr oid 63 -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(0)} -attr vt d
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+load netBundle {r(0).lpi#1.dfm} 16 {r(0).lpi#1.dfm(0)} {r(0).lpi#1.dfm(1)} {r(0).lpi#1.dfm(2)} {r(0).lpi#1.dfm(3)} {r(0).lpi#1.dfm(4)} {r(0).lpi#1.dfm(5)} {r(0).lpi#1.dfm(6)} {r(0).lpi#1.dfm(7)} {r(0).lpi#1.dfm(8)} {r(0).lpi#1.dfm(9)} {r(0).lpi#1.dfm(10)} {r(0).lpi#1.dfm(11)} {r(0).lpi#1.dfm(12)} {r(0).lpi#1.dfm(13)} {r(0).lpi#1.dfm(14)} {r(0).lpi#1.dfm(15)} -attr xrf 39577 -attr oid 64 -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {i#6.sva#1(0)} -attr vt d
+load net {i#6.sva#1(1)} -attr vt d
+load netBundle {i#6.sva#1} 2 {i#6.sva#1(0)} {i#6.sva#1(1)} -attr xrf 39578 -attr oid 65 -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.lpi#1.dfm(0)} -attr vt d
+load net {i#6.lpi#1.dfm(1)} -attr vt d
+load netBundle {i#6.lpi#1.dfm} 2 {i#6.lpi#1.dfm(0)} {i#6.lpi#1.dfm(1)} -attr xrf 39579 -attr oid 66 -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {FRAME:for#1:conc#16(0)} -attr vt d
+load net {FRAME:for#1:conc#16(1)} -attr vt d
+load netBundle {FRAME:for#1:conc#16} 2 {FRAME:for#1:conc#16(0)} {FRAME:for#1:conc#16(1)} -attr xrf 39580 -attr oid 67 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for:conc#28(0)} -attr vt d
+load net {FRAME:for:conc#28(1)} -attr vt d
+load netBundle {FRAME:for:conc#28} 2 {FRAME:for:conc#28(0)} {FRAME:for:conc#28(1)} -attr xrf 39581 -attr oid 68 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:conc#30(0)} -attr vt d
+load net {FRAME:for:conc#30(1)} -attr vt d
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+load net {FRAME:for:conc#32(0)} -attr vt d
+load net {FRAME:for:conc#32(1)} -attr vt d
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+load net {mux.itm(0)} -attr vt d
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+load net {FRAME:conc#21.itm(0)} -attr vt d
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+load net {FRAME:conc#21.itm(29)} -attr vt d
+load netBundle {FRAME:conc#21.itm} 30 {FRAME:conc#21.itm(0)} {FRAME:conc#21.itm(1)} {FRAME:conc#21.itm(2)} {FRAME:conc#21.itm(3)} {FRAME:conc#21.itm(4)} {FRAME:conc#21.itm(5)} {FRAME:conc#21.itm(6)} {FRAME:conc#21.itm(7)} {FRAME:conc#21.itm(8)} {FRAME:conc#21.itm(9)} {FRAME:conc#21.itm(10)} {FRAME:conc#21.itm(11)} {FRAME:conc#21.itm(12)} {FRAME:conc#21.itm(13)} {FRAME:conc#21.itm(14)} {FRAME:conc#21.itm(15)} {FRAME:conc#21.itm(16)} {FRAME:conc#21.itm(17)} {FRAME:conc#21.itm(18)} {FRAME:conc#21.itm(19)} {FRAME:conc#21.itm(20)} {FRAME:conc#21.itm(21)} {FRAME:conc#21.itm(22)} {FRAME:conc#21.itm(23)} {FRAME:conc#21.itm(24)} {FRAME:conc#21.itm(25)} {FRAME:conc#21.itm(26)} {FRAME:conc#21.itm(27)} {FRAME:conc#21.itm(28)} {FRAME:conc#21.itm(29)} -attr xrf 39585 -attr oid 72 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(0)} -attr vt d
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+load net {FRAME:or.itm(8)} -attr vt d
+load net {FRAME:or.itm(9)} -attr vt d
+load netBundle {FRAME:or.itm} 10 {FRAME:or.itm(0)} {FRAME:or.itm(1)} {FRAME:or.itm(2)} {FRAME:or.itm(3)} {FRAME:or.itm(4)} {FRAME:or.itm(5)} {FRAME:or.itm(6)} {FRAME:or.itm(7)} {FRAME:or.itm(8)} {FRAME:or.itm(9)} -attr xrf 39586 -attr oid 73 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:acc#2.itm(0)} -attr vt d
+load net {FRAME:acc#2.itm(1)} -attr vt d
+load net {FRAME:acc#2.itm(2)} -attr vt d
+load net {FRAME:acc#2.itm(3)} -attr vt d
+load net {FRAME:acc#2.itm(4)} -attr vt d
+load net {FRAME:acc#2.itm(5)} -attr vt d
+load net {FRAME:acc#2.itm(6)} -attr vt d
+load net {FRAME:acc#2.itm(7)} -attr vt d
+load net {FRAME:acc#2.itm(8)} -attr vt d
+load net {FRAME:acc#2.itm(9)} -attr vt d
+load netBundle {FRAME:acc#2.itm} 10 {FRAME:acc#2.itm(0)} {FRAME:acc#2.itm(1)} {FRAME:acc#2.itm(2)} {FRAME:acc#2.itm(3)} {FRAME:acc#2.itm(4)} {FRAME:acc#2.itm(5)} {FRAME:acc#2.itm(6)} {FRAME:acc#2.itm(7)} {FRAME:acc#2.itm(8)} {FRAME:acc#2.itm(9)} -attr xrf 39587 -attr oid 74 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:conc#36.itm(0)} -attr vt d
+load net {FRAME:conc#36.itm(1)} -attr vt d
+load net {FRAME:conc#36.itm(2)} -attr vt d
+load net {FRAME:conc#36.itm(3)} -attr vt d
+load net {FRAME:conc#36.itm(4)} -attr vt d
+load net {FRAME:conc#36.itm(5)} -attr vt d
+load net {FRAME:conc#36.itm(6)} -attr vt d
+load net {FRAME:conc#36.itm(7)} -attr vt d
+load net {FRAME:conc#36.itm(8)} -attr vt d
+load net {FRAME:conc#36.itm(9)} -attr vt d
+load netBundle {FRAME:conc#36.itm} 10 {FRAME:conc#36.itm(0)} {FRAME:conc#36.itm(1)} {FRAME:conc#36.itm(2)} {FRAME:conc#36.itm(3)} {FRAME:conc#36.itm(4)} {FRAME:conc#36.itm(5)} {FRAME:conc#36.itm(6)} {FRAME:conc#36.itm(7)} {FRAME:conc#36.itm(8)} {FRAME:conc#36.itm(9)} -attr xrf 39588 -attr oid 75 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#40.itm(0)} -attr vt d
+load net {FRAME:acc#40.itm(1)} -attr vt d
+load net {FRAME:acc#40.itm(2)} -attr vt d
+load net {FRAME:acc#40.itm(3)} -attr vt d
+load net {FRAME:acc#40.itm(4)} -attr vt d
+load net {FRAME:acc#40.itm(5)} -attr vt d
+load net {FRAME:acc#40.itm(6)} -attr vt d
+load net {FRAME:acc#40.itm(7)} -attr vt d
+load net {FRAME:acc#40.itm(8)} -attr vt d
+load net {FRAME:acc#40.itm(9)} -attr vt d
+load netBundle {FRAME:acc#40.itm} 10 {FRAME:acc#40.itm(0)} {FRAME:acc#40.itm(1)} {FRAME:acc#40.itm(2)} {FRAME:acc#40.itm(3)} {FRAME:acc#40.itm(4)} {FRAME:acc#40.itm(5)} {FRAME:acc#40.itm(6)} {FRAME:acc#40.itm(7)} {FRAME:acc#40.itm(8)} {FRAME:acc#40.itm(9)} -attr xrf 39589 -attr oid 76 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#39.itm(0)} -attr vt d
+load net {FRAME:acc#39.itm(1)} -attr vt d
+load net {FRAME:acc#39.itm(2)} -attr vt d
+load net {FRAME:acc#39.itm(3)} -attr vt d
+load net {FRAME:acc#39.itm(4)} -attr vt d
+load net {FRAME:acc#39.itm(5)} -attr vt d
+load net {FRAME:acc#39.itm(6)} -attr vt d
+load net {FRAME:acc#39.itm(7)} -attr vt d
+load netBundle {FRAME:acc#39.itm} 8 {FRAME:acc#39.itm(0)} {FRAME:acc#39.itm(1)} {FRAME:acc#39.itm(2)} {FRAME:acc#39.itm(3)} {FRAME:acc#39.itm(4)} {FRAME:acc#39.itm(5)} {FRAME:acc#39.itm(6)} {FRAME:acc#39.itm(7)} -attr xrf 39590 -attr oid 77 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#38.itm(0)} -attr vt d
+load net {FRAME:acc#38.itm(1)} -attr vt d
+load net {FRAME:acc#38.itm(2)} -attr vt d
+load net {FRAME:acc#38.itm(3)} -attr vt d
+load net {FRAME:acc#38.itm(4)} -attr vt d
+load netBundle {FRAME:acc#38.itm} 5 {FRAME:acc#38.itm(0)} {FRAME:acc#38.itm(1)} {FRAME:acc#38.itm(2)} {FRAME:acc#38.itm(3)} {FRAME:acc#38.itm(4)} -attr xrf 39591 -attr oid 78 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {conc.itm(0)} -attr vt d
+load net {conc.itm(1)} -attr vt d
+load net {conc.itm(2)} -attr vt d
+load net {conc.itm(3)} -attr vt d
+load net {conc.itm(4)} -attr vt d
+load netBundle {conc.itm} 5 {conc.itm(0)} {conc.itm(1)} {conc.itm(2)} {conc.itm(3)} {conc.itm(4)} -attr xrf 39592 -attr oid 79 -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {conc#137.itm(0)} -attr vt d
+load net {conc#137.itm(1)} -attr vt d
+load net {conc#137.itm(2)} -attr vt d
+load net {conc#137.itm(3)} -attr vt d
+load net {conc#137.itm(4)} -attr vt d
+load net {conc#137.itm(5)} -attr vt d
+load net {conc#137.itm(6)} -attr vt d
+load net {conc#137.itm(7)} -attr vt d
+load net {conc#137.itm(8)} -attr vt d
+load net {conc#137.itm(9)} -attr vt d
+load netBundle {conc#137.itm} 10 {conc#137.itm(0)} {conc#137.itm(1)} {conc#137.itm(2)} {conc#137.itm(3)} {conc#137.itm(4)} {conc#137.itm(5)} {conc#137.itm(6)} {conc#137.itm(7)} {conc#137.itm(8)} {conc#137.itm(9)} -attr xrf 39593 -attr oid 80 -attr vt d -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {slc(FRAME:acc#3.psp.sva).itm(0)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#3.psp.sva).itm} 2 {slc(FRAME:acc#3.psp.sva).itm(0)} {slc(FRAME:acc#3.psp.sva).itm(1)} -attr xrf 39594 -attr oid 81 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva).itm}
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#1.itm(3)} -attr vt d
+load netBundle {slc(FRAME:acc#3.psp.sva)#1.itm} 4 {slc(FRAME:acc#3.psp.sva)#1.itm(0)} {slc(FRAME:acc#3.psp.sva)#1.itm(1)} {slc(FRAME:acc#3.psp.sva)#1.itm(2)} {slc(FRAME:acc#3.psp.sva)#1.itm(3)} -attr xrf 39595 -attr oid 82 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#1.itm}
+load net {FRAME:or#3.itm(0)} -attr vt d
+load net {FRAME:or#3.itm(1)} -attr vt d
+load net {FRAME:or#3.itm(2)} -attr vt d
+load net {FRAME:or#3.itm(3)} -attr vt d
+load net {FRAME:or#3.itm(4)} -attr vt d
+load net {FRAME:or#3.itm(5)} -attr vt d
+load netBundle {FRAME:or#3.itm} 6 {FRAME:or#3.itm(0)} {FRAME:or#3.itm(1)} {FRAME:or#3.itm(2)} {FRAME:or#3.itm(3)} {FRAME:or#3.itm(4)} {FRAME:or#3.itm(5)} -attr xrf 39596 -attr oid 83 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(0)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(1)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(2)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(3)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(4)} -attr vt d
+load net {slc(FRAME:acc#3.psp.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(FRAME:acc#3.psp.sva)#2.itm} 6 {slc(FRAME:acc#3.psp.sva)#2.itm(0)} {slc(FRAME:acc#3.psp.sva)#2.itm(1)} {slc(FRAME:acc#3.psp.sva)#2.itm(2)} {slc(FRAME:acc#3.psp.sva)#2.itm(3)} {slc(FRAME:acc#3.psp.sva)#2.itm(4)} {slc(FRAME:acc#3.psp.sva)#2.itm(5)} -attr xrf 39597 -attr oid 84 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {conc#138.itm(0)} -attr vt d
+load net {conc#138.itm(1)} -attr vt d
+load net {conc#138.itm(2)} -attr vt d
+load net {conc#138.itm(3)} -attr vt d
+load net {conc#138.itm(4)} -attr vt d
+load net {conc#138.itm(5)} -attr vt d
+load netBundle {conc#138.itm} 6 {conc#138.itm(0)} {conc#138.itm(1)} {conc#138.itm(2)} {conc#138.itm(3)} {conc#138.itm(4)} {conc#138.itm(5)} -attr xrf 39598 -attr oid 85 -attr vt d -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {slc(FRAME:acc#4.psp.sva).itm(0)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva).itm(1)} -attr vt d
+load netBundle {slc(FRAME:acc#4.psp.sva).itm} 2 {slc(FRAME:acc#4.psp.sva).itm(0)} {slc(FRAME:acc#4.psp.sva).itm(1)} -attr xrf 39599 -attr oid 86 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#4.psp.sva).itm}
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(0)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(1)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(2)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(3)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(4)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(5)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(6)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(7)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(8)} -attr vt d
+load net {slc(FRAME:acc#4.psp.sva)#1.itm(9)} -attr vt d
+load netBundle {slc(FRAME:acc#4.psp.sva)#1.itm} 10 {slc(FRAME:acc#4.psp.sva)#1.itm(0)} {slc(FRAME:acc#4.psp.sva)#1.itm(1)} {slc(FRAME:acc#4.psp.sva)#1.itm(2)} {slc(FRAME:acc#4.psp.sva)#1.itm(3)} {slc(FRAME:acc#4.psp.sva)#1.itm(4)} {slc(FRAME:acc#4.psp.sva)#1.itm(5)} {slc(FRAME:acc#4.psp.sva)#1.itm(6)} {slc(FRAME:acc#4.psp.sva)#1.itm(7)} {slc(FRAME:acc#4.psp.sva)#1.itm(8)} {slc(FRAME:acc#4.psp.sva)#1.itm(9)} -attr xrf 39600 -attr oid 87 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#4.psp.sva)#1.itm}
+load net {FRAME:acc#43.itm(0)} -attr vt d
+load net {FRAME:acc#43.itm(1)} -attr vt d
+load netBundle {FRAME:acc#43.itm} 2 {FRAME:acc#43.itm(0)} {FRAME:acc#43.itm(1)} -attr xrf 39601 -attr oid 88 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {slc(FRAME:mul.sdt).itm(0)} -attr vt d
+load net {slc(FRAME:mul.sdt).itm(1)} -attr vt d
+load netBundle {slc(FRAME:mul.sdt).itm} 2 {slc(FRAME:mul.sdt).itm(0)} {slc(FRAME:mul.sdt).itm(1)} -attr xrf 39602 -attr oid 89 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt).itm}
+load net {slc(FRAME:mul.sdt)#2.itm(0)} -attr vt d
+load net {slc(FRAME:mul.sdt)#2.itm(1)} -attr vt d
+load netBundle {slc(FRAME:mul.sdt)#2.itm} 2 {slc(FRAME:mul.sdt)#2.itm(0)} {slc(FRAME:mul.sdt)#2.itm(1)} -attr xrf 39603 -attr oid 90 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#2.itm}
+load net {FRAME:acc#44.itm(0)} -attr vt d
+load net {FRAME:acc#44.itm(1)} -attr vt d
+load net {FRAME:acc#44.itm(2)} -attr vt d
+load net {FRAME:acc#44.itm(3)} -attr vt d
+load net {FRAME:acc#44.itm(4)} -attr vt d
+load net {FRAME:acc#44.itm(5)} -attr vt d
+load netBundle {FRAME:acc#44.itm} 6 {FRAME:acc#44.itm(0)} {FRAME:acc#44.itm(1)} {FRAME:acc#44.itm(2)} {FRAME:acc#44.itm(3)} {FRAME:acc#44.itm(4)} {FRAME:acc#44.itm(5)} -attr xrf 39604 -attr oid 91 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {slc(FRAME:mul.sdt)#1.itm(0)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(1)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(2)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(3)} -attr vt d
+load net {slc(FRAME:mul.sdt)#1.itm(4)} -attr vt d
+load netBundle {slc(FRAME:mul.sdt)#1.itm} 5 {slc(FRAME:mul.sdt)#1.itm(0)} {slc(FRAME:mul.sdt)#1.itm(1)} {slc(FRAME:mul.sdt)#1.itm(2)} {slc(FRAME:mul.sdt)#1.itm(3)} {slc(FRAME:mul.sdt)#1.itm(4)} -attr xrf 39605 -attr oid 92 -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {exs#3.itm(0)} -attr vt d
+load net {exs#3.itm(1)} -attr vt d
+load net {exs#3.itm(2)} -attr vt d
+load net {exs#3.itm(3)} -attr vt d
+load net {exs#3.itm(4)} -attr vt d
+load netBundle {exs#3.itm} 5 {exs#3.itm(0)} {exs#3.itm(1)} {exs#3.itm(2)} {exs#3.itm(3)} {exs#3.itm(4)} -attr xrf 39606 -attr oid 93 -attr vt d -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {conc#139.itm(0)} -attr vt d
+load net {conc#139.itm(1)} -attr vt d
+load net {conc#139.itm(2)} -attr vt d
+load netBundle {conc#139.itm} 3 {conc#139.itm(0)} {conc#139.itm(1)} {conc#139.itm(2)} -attr xrf 39607 -attr oid 94 -attr vt d -attr @path {/sobel/sobel:core/conc#139.itm}
+load net {FRAME:mul#1.itm(0)} -attr vt d
+load net {FRAME:mul#1.itm(1)} -attr vt d
+load net {FRAME:mul#1.itm(2)} -attr vt d
+load net {FRAME:mul#1.itm(3)} -attr vt d
+load net {FRAME:mul#1.itm(4)} -attr vt d
+load net {FRAME:mul#1.itm(5)} -attr vt d
+load net {FRAME:mul#1.itm(6)} -attr vt d
+load net {FRAME:mul#1.itm(7)} -attr vt d
+load net {FRAME:mul#1.itm(8)} -attr vt d
+load netBundle {FRAME:mul#1.itm} 9 {FRAME:mul#1.itm(0)} {FRAME:mul#1.itm(1)} {FRAME:mul#1.itm(2)} {FRAME:mul#1.itm(3)} {FRAME:mul#1.itm(4)} {FRAME:mul#1.itm(5)} {FRAME:mul#1.itm(6)} {FRAME:mul#1.itm(7)} {FRAME:mul#1.itm(8)} -attr xrf 39608 -attr oid 95 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {slc(red#2.sg1.sva)#13.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#13.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#13.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#13.itm} 3 {slc(red#2.sg1.sva)#13.itm(0)} {slc(red#2.sg1.sva)#13.itm(1)} {slc(red#2.sg1.sva)#13.itm(2)} -attr xrf 39609 -attr oid 96 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {slc(red#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(2)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(3)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(4)} -attr vt d
+load net {slc(red#2.sg1.sva)#1.itm(5)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#1.itm} 6 {slc(red#2.sg1.sva)#1.itm(0)} {slc(red#2.sg1.sva)#1.itm(1)} {slc(red#2.sg1.sva)#1.itm(2)} {slc(red#2.sg1.sva)#1.itm(3)} {slc(red#2.sg1.sva)#1.itm(4)} {slc(red#2.sg1.sva)#1.itm(5)} -attr xrf 39610 -attr oid 97 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {FRAME:acc#37.itm(0)} -attr vt d
+load net {FRAME:acc#37.itm(1)} -attr vt d
+load net {FRAME:acc#37.itm(2)} -attr vt d
+load net {FRAME:acc#37.itm(3)} -attr vt d
+load net {FRAME:acc#37.itm(4)} -attr vt d
+load netBundle {FRAME:acc#37.itm} 5 {FRAME:acc#37.itm(0)} {FRAME:acc#37.itm(1)} {FRAME:acc#37.itm(2)} {FRAME:acc#37.itm(3)} {FRAME:acc#37.itm(4)} -attr xrf 39611 -attr oid 98 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#36.itm(0)} -attr vt d
+load net {FRAME:acc#36.itm(1)} -attr vt d
+load net {FRAME:acc#36.itm(2)} -attr vt d
+load net {FRAME:acc#36.itm(3)} -attr vt d
+load netBundle {FRAME:acc#36.itm} 4 {FRAME:acc#36.itm(0)} {FRAME:acc#36.itm(1)} {FRAME:acc#36.itm(2)} {FRAME:acc#36.itm(3)} -attr xrf 39612 -attr oid 99 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {conc#141.itm(0)} -attr vt d
+load net {conc#141.itm(1)} -attr vt d
+load net {conc#141.itm(2)} -attr vt d
+load netBundle {conc#141.itm} 3 {conc#141.itm(0)} {conc#141.itm(1)} {conc#141.itm(2)} -attr xrf 39613 -attr oid 100 -attr vt d -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {conc#142.itm(0)} -attr vt d
+load net {conc#142.itm(1)} -attr vt d
+load net {conc#142.itm(2)} -attr vt d
+load net {conc#142.itm(3)} -attr vt d
+load net {conc#142.itm(4)} -attr vt d
+load netBundle {conc#142.itm} 5 {conc#142.itm(0)} {conc#142.itm(1)} {conc#142.itm(2)} {conc#142.itm(3)} {conc#142.itm(4)} -attr xrf 39614 -attr oid 101 -attr vt d -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {slc(acc.imod#3.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#3.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#3.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#3.sva)#1.itm} 3 {slc(acc.imod#3.sva)#1.itm(0)} {slc(acc.imod#3.sva)#1.itm(1)} {slc(acc.imod#3.sva)#1.itm(2)} -attr xrf 39615 -attr oid 102 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#1.itm}
+load net {FRAME:conc#33.itm(0)} -attr vt d
+load net {FRAME:conc#33.itm(1)} -attr vt d
+load net {FRAME:conc#33.itm(2)} -attr vt d
+load net {FRAME:conc#33.itm(3)} -attr vt d
+load netBundle {FRAME:conc#33.itm} 4 {FRAME:conc#33.itm(0)} {FRAME:conc#33.itm(1)} {FRAME:conc#33.itm(2)} {FRAME:conc#33.itm(3)} -attr xrf 39616 -attr oid 103 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(0)} -attr vt d
+load net {FRAME:not#5.itm(1)} -attr vt d
+load net {FRAME:not#5.itm(2)} -attr vt d
+load netBundle {FRAME:not#5.itm} 3 {FRAME:not#5.itm(0)} {FRAME:not#5.itm(1)} {FRAME:not#5.itm(2)} -attr xrf 39617 -attr oid 104 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {slc(acc.imod#3.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#3.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#3.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#3.sva)#2.itm} 3 {slc(acc.imod#3.sva)#2.itm(0)} {slc(acc.imod#3.sva)#2.itm(1)} {slc(acc.imod#3.sva)#2.itm(2)} -attr xrf 39618 -attr oid 105 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#2.itm}
+load net {slc(acc.imod#3.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#3.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#3.sva)#4.itm} 2 {slc(acc.imod#3.sva)#4.itm(0)} {slc(acc.imod#3.sva)#4.itm(1)} -attr xrf 39619 -attr oid 106 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#4.itm}
+load net {FRAME:not#6.itm(0)} -attr vt d
+load net {FRAME:not#6.itm(1)} -attr vt d
+load net {FRAME:not#6.itm(2)} -attr vt d
+load netBundle {FRAME:not#6.itm} 3 {FRAME:not#6.itm(0)} {FRAME:not#6.itm(1)} {FRAME:not#6.itm(2)} -attr xrf 39620 -attr oid 107 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {slc(red#2.sg1.sva)#8.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#8.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#8.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#8.itm} 3 {slc(red#2.sg1.sva)#8.itm(0)} {slc(red#2.sg1.sva)#8.itm(1)} {slc(red#2.sg1.sva)#8.itm(2)} -attr xrf 39621 -attr oid 108 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {FRAME:mul#4.itm(0)} -attr vt d
+load net {FRAME:mul#4.itm(1)} -attr vt d
+load net {FRAME:mul#4.itm(2)} -attr vt d
+load net {FRAME:mul#4.itm(3)} -attr vt d
+load net {FRAME:mul#4.itm(4)} -attr vt d
+load net {FRAME:mul#4.itm(5)} -attr vt d
+load net {FRAME:mul#4.itm(6)} -attr vt d
+load net {FRAME:mul#4.itm(7)} -attr vt d
+load net {FRAME:mul#4.itm(8)} -attr vt d
+load net {FRAME:mul#4.itm(9)} -attr vt d
+load net {FRAME:mul#4.itm(10)} -attr vt d
+load netBundle {FRAME:mul#4.itm} 11 {FRAME:mul#4.itm(0)} {FRAME:mul#4.itm(1)} {FRAME:mul#4.itm(2)} {FRAME:mul#4.itm(3)} {FRAME:mul#4.itm(4)} {FRAME:mul#4.itm(5)} {FRAME:mul#4.itm(6)} {FRAME:mul#4.itm(7)} {FRAME:mul#4.itm(8)} {FRAME:mul#4.itm(9)} {FRAME:mul#4.itm(10)} -attr xrf 39622 -attr oid 109 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {slc(blue#2.sg1.sva)#10.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#10.itm(1)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#10.itm} 2 {slc(blue#2.sg1.sva)#10.itm(0)} {slc(blue#2.sg1.sva)#10.itm(1)} -attr xrf 39623 -attr oid 110 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#10.itm}
+load net {FRAME:mul#5.itm(0)} -attr vt d
+load net {FRAME:mul#5.itm(1)} -attr vt d
+load net {FRAME:mul#5.itm(2)} -attr vt d
+load net {FRAME:mul#5.itm(3)} -attr vt d
+load net {FRAME:mul#5.itm(4)} -attr vt d
+load net {FRAME:mul#5.itm(5)} -attr vt d
+load net {FRAME:mul#5.itm(6)} -attr vt d
+load net {FRAME:mul#5.itm(7)} -attr vt d
+load net {FRAME:mul#5.itm(8)} -attr vt d
+load netBundle {FRAME:mul#5.itm} 9 {FRAME:mul#5.itm(0)} {FRAME:mul#5.itm(1)} {FRAME:mul#5.itm(2)} {FRAME:mul#5.itm(3)} {FRAME:mul#5.itm(4)} {FRAME:mul#5.itm(5)} {FRAME:mul#5.itm(6)} {FRAME:mul#5.itm(7)} {FRAME:mul#5.itm(8)} -attr xrf 39624 -attr oid 111 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {slc(blue#2.sg1.sva)#11.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#11.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#11.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#11.itm} 3 {slc(blue#2.sg1.sva)#11.itm(0)} {slc(blue#2.sg1.sva)#11.itm(1)} {slc(blue#2.sg1.sva)#11.itm(2)} -attr xrf 39625 -attr oid 112 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {slc(blue#2.sg1.sva)#2.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(2)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(3)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(4)} -attr vt d
+load net {slc(blue#2.sg1.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#2.itm} 6 {slc(blue#2.sg1.sva)#2.itm(0)} {slc(blue#2.sg1.sva)#2.itm(1)} {slc(blue#2.sg1.sva)#2.itm(2)} {slc(blue#2.sg1.sva)#2.itm(3)} {slc(blue#2.sg1.sva)#2.itm(4)} {slc(blue#2.sg1.sva)#2.itm(5)} -attr xrf 39626 -attr oid 113 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {FRAME:acc#30.itm(0)} -attr vt d
+load net {FRAME:acc#30.itm(1)} -attr vt d
+load net {FRAME:acc#30.itm(2)} -attr vt d
+load net {FRAME:acc#30.itm(3)} -attr vt d
+load net {FRAME:acc#30.itm(4)} -attr vt d
+load netBundle {FRAME:acc#30.itm} 5 {FRAME:acc#30.itm(0)} {FRAME:acc#30.itm(1)} {FRAME:acc#30.itm(2)} {FRAME:acc#30.itm(3)} {FRAME:acc#30.itm(4)} -attr xrf 39627 -attr oid 114 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#29.itm(0)} -attr vt d
+load net {FRAME:acc#29.itm(1)} -attr vt d
+load net {FRAME:acc#29.itm(2)} -attr vt d
+load net {FRAME:acc#29.itm(3)} -attr vt d
+load netBundle {FRAME:acc#29.itm} 4 {FRAME:acc#29.itm(0)} {FRAME:acc#29.itm(1)} {FRAME:acc#29.itm(2)} {FRAME:acc#29.itm(3)} -attr xrf 39628 -attr oid 115 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {conc#143.itm(0)} -attr vt d
+load net {conc#143.itm(1)} -attr vt d
+load net {conc#143.itm(2)} -attr vt d
+load netBundle {conc#143.itm} 3 {conc#143.itm(0)} {conc#143.itm(1)} {conc#143.itm(2)} -attr xrf 39629 -attr oid 116 -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {conc#144.itm(0)} -attr vt d
+load net {conc#144.itm(1)} -attr vt d
+load net {conc#144.itm(2)} -attr vt d
+load net {conc#144.itm(3)} -attr vt d
+load net {conc#144.itm(4)} -attr vt d
+load netBundle {conc#144.itm} 5 {conc#144.itm(0)} {conc#144.itm(1)} {conc#144.itm(2)} {conc#144.itm(3)} {conc#144.itm(4)} -attr xrf 39630 -attr oid 117 -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {slc(acc.imod#7.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#7.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#7.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#7.sva)#1.itm} 3 {slc(acc.imod#7.sva)#1.itm(0)} {slc(acc.imod#7.sva)#1.itm(1)} {slc(acc.imod#7.sva)#1.itm(2)} -attr xrf 39631 -attr oid 118 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#1.itm}
+load net {FRAME:conc#29.itm(0)} -attr vt d
+load net {FRAME:conc#29.itm(1)} -attr vt d
+load net {FRAME:conc#29.itm(2)} -attr vt d
+load net {FRAME:conc#29.itm(3)} -attr vt d
+load netBundle {FRAME:conc#29.itm} 4 {FRAME:conc#29.itm(0)} {FRAME:conc#29.itm(1)} {FRAME:conc#29.itm(2)} {FRAME:conc#29.itm(3)} -attr xrf 39632 -attr oid 119 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(0)} -attr vt d
+load net {FRAME:not#21.itm(1)} -attr vt d
+load net {FRAME:not#21.itm(2)} -attr vt d
+load netBundle {FRAME:not#21.itm} 3 {FRAME:not#21.itm(0)} {FRAME:not#21.itm(1)} {FRAME:not#21.itm(2)} -attr xrf 39633 -attr oid 120 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {slc(acc.imod#7.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#7.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#7.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#7.sva)#2.itm} 3 {slc(acc.imod#7.sva)#2.itm(0)} {slc(acc.imod#7.sva)#2.itm(1)} {slc(acc.imod#7.sva)#2.itm(2)} -attr xrf 39634 -attr oid 121 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#2.itm}
+load net {slc(acc.imod#7.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#7.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#7.sva)#4.itm} 2 {slc(acc.imod#7.sva)#4.itm(0)} {slc(acc.imod#7.sva)#4.itm(1)} -attr xrf 39635 -attr oid 122 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#4.itm}
+load net {FRAME:not#22.itm(0)} -attr vt d
+load net {FRAME:not#22.itm(1)} -attr vt d
+load net {FRAME:not#22.itm(2)} -attr vt d
+load netBundle {FRAME:not#22.itm} 3 {FRAME:not#22.itm(0)} {FRAME:not#22.itm(1)} {FRAME:not#22.itm(2)} -attr xrf 39636 -attr oid 123 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {slc(blue#2.sg1.sva)#9.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#9.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#9.itm} 3 {slc(blue#2.sg1.sva)#9.itm(0)} {slc(blue#2.sg1.sva)#9.itm(1)} {slc(blue#2.sg1.sva)#9.itm(2)} -attr xrf 39637 -attr oid 124 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {FRAME:mul#2.itm(0)} -attr vt d
+load net {FRAME:mul#2.itm(1)} -attr vt d
+load net {FRAME:mul#2.itm(2)} -attr vt d
+load net {FRAME:mul#2.itm(3)} -attr vt d
+load net {FRAME:mul#2.itm(4)} -attr vt d
+load net {FRAME:mul#2.itm(5)} -attr vt d
+load net {FRAME:mul#2.itm(6)} -attr vt d
+load net {FRAME:mul#2.itm(7)} -attr vt d
+load net {FRAME:mul#2.itm(8)} -attr vt d
+load net {FRAME:mul#2.itm(9)} -attr vt d
+load net {FRAME:mul#2.itm(10)} -attr vt d
+load netBundle {FRAME:mul#2.itm} 11 {FRAME:mul#2.itm(0)} {FRAME:mul#2.itm(1)} {FRAME:mul#2.itm(2)} {FRAME:mul#2.itm(3)} {FRAME:mul#2.itm(4)} {FRAME:mul#2.itm(5)} {FRAME:mul#2.itm(6)} {FRAME:mul#2.itm(7)} {FRAME:mul#2.itm(8)} {FRAME:mul#2.itm(9)} {FRAME:mul#2.itm(10)} -attr xrf 39638 -attr oid 125 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {slc(green#2.sg1.sva)#10.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#10.itm(1)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#10.itm} 2 {slc(green#2.sg1.sva)#10.itm(0)} {slc(green#2.sg1.sva)#10.itm(1)} -attr xrf 39639 -attr oid 126 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#10.itm}
+load net {FRAME:mul#3.itm(0)} -attr vt d
+load net {FRAME:mul#3.itm(1)} -attr vt d
+load net {FRAME:mul#3.itm(2)} -attr vt d
+load net {FRAME:mul#3.itm(3)} -attr vt d
+load net {FRAME:mul#3.itm(4)} -attr vt d
+load net {FRAME:mul#3.itm(5)} -attr vt d
+load net {FRAME:mul#3.itm(6)} -attr vt d
+load net {FRAME:mul#3.itm(7)} -attr vt d
+load net {FRAME:mul#3.itm(8)} -attr vt d
+load netBundle {FRAME:mul#3.itm} 9 {FRAME:mul#3.itm(0)} {FRAME:mul#3.itm(1)} {FRAME:mul#3.itm(2)} {FRAME:mul#3.itm(3)} {FRAME:mul#3.itm(4)} {FRAME:mul#3.itm(5)} {FRAME:mul#3.itm(6)} {FRAME:mul#3.itm(7)} {FRAME:mul#3.itm(8)} -attr xrf 39640 -attr oid 127 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {slc(green#2.sg1.sva)#11.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#11.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#11.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#11.itm} 3 {slc(green#2.sg1.sva)#11.itm(0)} {slc(green#2.sg1.sva)#11.itm(1)} {slc(green#2.sg1.sva)#11.itm(2)} -attr xrf 39641 -attr oid 128 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {slc(green#2.sg1.sva)#2.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(2)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(3)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(4)} -attr vt d
+load net {slc(green#2.sg1.sva)#2.itm(5)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#2.itm} 6 {slc(green#2.sg1.sva)#2.itm(0)} {slc(green#2.sg1.sva)#2.itm(1)} {slc(green#2.sg1.sva)#2.itm(2)} {slc(green#2.sg1.sva)#2.itm(3)} {slc(green#2.sg1.sva)#2.itm(4)} {slc(green#2.sg1.sva)#2.itm(5)} -attr xrf 39642 -attr oid 129 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {FRAME:acc#18.itm(0)} -attr vt d
+load net {FRAME:acc#18.itm(1)} -attr vt d
+load net {FRAME:acc#18.itm(2)} -attr vt d
+load net {FRAME:acc#18.itm(3)} -attr vt d
+load net {FRAME:acc#18.itm(4)} -attr vt d
+load netBundle {FRAME:acc#18.itm} 5 {FRAME:acc#18.itm(0)} {FRAME:acc#18.itm(1)} {FRAME:acc#18.itm(2)} {FRAME:acc#18.itm(3)} {FRAME:acc#18.itm(4)} -attr xrf 39643 -attr oid 130 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#17.itm(0)} -attr vt d
+load net {FRAME:acc#17.itm(1)} -attr vt d
+load net {FRAME:acc#17.itm(2)} -attr vt d
+load net {FRAME:acc#17.itm(3)} -attr vt d
+load netBundle {FRAME:acc#17.itm} 4 {FRAME:acc#17.itm(0)} {FRAME:acc#17.itm(1)} {FRAME:acc#17.itm(2)} {FRAME:acc#17.itm(3)} -attr xrf 39644 -attr oid 131 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {conc#145.itm(0)} -attr vt d
+load net {conc#145.itm(1)} -attr vt d
+load net {conc#145.itm(2)} -attr vt d
+load netBundle {conc#145.itm} 3 {conc#145.itm(0)} {conc#145.itm(1)} {conc#145.itm(2)} -attr xrf 39645 -attr oid 132 -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {conc#146.itm(0)} -attr vt d
+load net {conc#146.itm(1)} -attr vt d
+load net {conc#146.itm(2)} -attr vt d
+load net {conc#146.itm(3)} -attr vt d
+load net {conc#146.itm(4)} -attr vt d
+load netBundle {conc#146.itm} 5 {conc#146.itm(0)} {conc#146.itm(1)} {conc#146.itm(2)} {conc#146.itm(3)} {conc#146.itm(4)} -attr xrf 39646 -attr oid 133 -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {slc(acc.imod#5.sva)#1.itm(0)} -attr vt d
+load net {slc(acc.imod#5.sva)#1.itm(1)} -attr vt d
+load net {slc(acc.imod#5.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#5.sva)#1.itm} 3 {slc(acc.imod#5.sva)#1.itm(0)} {slc(acc.imod#5.sva)#1.itm(1)} {slc(acc.imod#5.sva)#1.itm(2)} -attr xrf 39647 -attr oid 134 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#5.sva)#1.itm}
+load net {FRAME:conc#25.itm(0)} -attr vt d
+load net {FRAME:conc#25.itm(1)} -attr vt d
+load net {FRAME:conc#25.itm(2)} -attr vt d
+load net {FRAME:conc#25.itm(3)} -attr vt d
+load netBundle {FRAME:conc#25.itm} 4 {FRAME:conc#25.itm(0)} {FRAME:conc#25.itm(1)} {FRAME:conc#25.itm(2)} {FRAME:conc#25.itm(3)} -attr xrf 39648 -attr oid 135 -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(0)} -attr vt d
+load net {FRAME:not#13.itm(1)} -attr vt d
+load net {FRAME:not#13.itm(2)} -attr vt d
+load netBundle {FRAME:not#13.itm} 3 {FRAME:not#13.itm(0)} {FRAME:not#13.itm(1)} {FRAME:not#13.itm(2)} -attr xrf 39649 -attr oid 136 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {slc(acc.imod#5.sva)#2.itm(0)} -attr vt d
+load net {slc(acc.imod#5.sva)#2.itm(1)} -attr vt d
+load net {slc(acc.imod#5.sva)#2.itm(2)} -attr vt d
+load netBundle {slc(acc.imod#5.sva)#2.itm} 3 {slc(acc.imod#5.sva)#2.itm(0)} {slc(acc.imod#5.sva)#2.itm(1)} {slc(acc.imod#5.sva)#2.itm(2)} -attr xrf 39650 -attr oid 137 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#5.sva)#2.itm}
+load net {slc(acc.imod#5.sva)#4.itm(0)} -attr vt d
+load net {slc(acc.imod#5.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(acc.imod#5.sva)#4.itm} 2 {slc(acc.imod#5.sva)#4.itm(0)} {slc(acc.imod#5.sva)#4.itm(1)} -attr xrf 39651 -attr oid 138 -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#5.sva)#4.itm}
+load net {FRAME:not#14.itm(0)} -attr vt d
+load net {FRAME:not#14.itm(1)} -attr vt d
+load net {FRAME:not#14.itm(2)} -attr vt d
+load netBundle {FRAME:not#14.itm} 3 {FRAME:not#14.itm(0)} {FRAME:not#14.itm(1)} {FRAME:not#14.itm(2)} -attr xrf 39652 -attr oid 139 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {slc(green#2.sg1.sva)#9.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#9.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#9.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#9.itm} 3 {slc(green#2.sg1.sva)#9.itm(0)} {slc(green#2.sg1.sva)#9.itm(1)} {slc(green#2.sg1.sva)#9.itm(2)} -attr xrf 39653 -attr oid 140 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {mux#1.itm(0)} -attr vt d
+load net {mux#1.itm(1)} -attr vt d
+load netBundle {mux#1.itm} 2 {mux#1.itm(0)} {mux#1.itm(1)} -attr xrf 39654 -attr oid 141 -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {FRAME:for:and#13.itm(0)} -attr vt d
+load net {FRAME:for:and#13.itm(1)} -attr vt d
+load netBundle {FRAME:for:and#13.itm} 2 {FRAME:for:and#13.itm(0)} {FRAME:for:and#13.itm(1)} -attr xrf 39655 -attr oid 142 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#13.itm}
+load net {FRAME:for:exs#30.itm(0)} -attr vt d
+load net {FRAME:for:exs#30.itm(1)} -attr vt d
+load netBundle {FRAME:for:exs#30.itm} 2 {FRAME:for:exs#30.itm(0)} {FRAME:for:exs#30.itm(1)} -attr xrf 39656 -attr oid 143 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#30.itm}
+load net {mux#8.itm(0)} -attr vt d
+load net {mux#8.itm(1)} -attr vt d
+load net {mux#8.itm(2)} -attr vt d
+load net {mux#8.itm(3)} -attr vt d
+load net {mux#8.itm(4)} -attr vt d
+load net {mux#8.itm(5)} -attr vt d
+load net {mux#8.itm(6)} -attr vt d
+load net {mux#8.itm(7)} -attr vt d
+load net {mux#8.itm(8)} -attr vt d
+load net {mux#8.itm(9)} -attr vt d
+load net {mux#8.itm(10)} -attr vt d
+load net {mux#8.itm(11)} -attr vt d
+load net {mux#8.itm(12)} -attr vt d
+load net {mux#8.itm(13)} -attr vt d
+load net {mux#8.itm(14)} -attr vt d
+load netBundle {mux#8.itm} 15 {mux#8.itm(0)} {mux#8.itm(1)} {mux#8.itm(2)} {mux#8.itm(3)} {mux#8.itm(4)} {mux#8.itm(5)} {mux#8.itm(6)} {mux#8.itm(7)} {mux#8.itm(8)} {mux#8.itm(9)} {mux#8.itm(10)} {mux#8.itm(11)} {mux#8.itm(12)} {mux#8.itm(13)} {mux#8.itm(14)} -attr xrf 39657 -attr oid 144 -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {FRAME:for:acc#28.itm(0)} -attr vt d
+load net {FRAME:for:acc#28.itm(1)} -attr vt d
+load net {FRAME:for:acc#28.itm(2)} -attr vt d
+load net {FRAME:for:acc#28.itm(3)} -attr vt d
+load net {FRAME:for:acc#28.itm(4)} -attr vt d
+load net {FRAME:for:acc#28.itm(5)} -attr vt d
+load net {FRAME:for:acc#28.itm(6)} -attr vt d
+load net {FRAME:for:acc#28.itm(7)} -attr vt d
+load net {FRAME:for:acc#28.itm(8)} -attr vt d
+load net {FRAME:for:acc#28.itm(9)} -attr vt d
+load net {FRAME:for:acc#28.itm(10)} -attr vt d
+load net {FRAME:for:acc#28.itm(11)} -attr vt d
+load net {FRAME:for:acc#28.itm(12)} -attr vt d
+load net {FRAME:for:acc#28.itm(13)} -attr vt d
+load net {FRAME:for:acc#28.itm(14)} -attr vt d
+load netBundle {FRAME:for:acc#28.itm} 15 {FRAME:for:acc#28.itm(0)} {FRAME:for:acc#28.itm(1)} {FRAME:for:acc#28.itm(2)} {FRAME:for:acc#28.itm(3)} {FRAME:for:acc#28.itm(4)} {FRAME:for:acc#28.itm(5)} {FRAME:for:acc#28.itm(6)} {FRAME:for:acc#28.itm(7)} {FRAME:for:acc#28.itm(8)} {FRAME:for:acc#28.itm(9)} {FRAME:for:acc#28.itm(10)} {FRAME:for:acc#28.itm(11)} {FRAME:for:acc#28.itm(12)} {FRAME:for:acc#28.itm(13)} {FRAME:for:acc#28.itm(14)} -attr xrf 39658 -attr oid 145 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:mul#5.itm(0)} -attr vt d
+load net {FRAME:for:mul#5.itm(1)} -attr vt d
+load net {FRAME:for:mul#5.itm(2)} -attr vt d
+load net {FRAME:for:mul#5.itm(3)} -attr vt d
+load net {FRAME:for:mul#5.itm(4)} -attr vt d
+load net {FRAME:for:mul#5.itm(5)} -attr vt d
+load net {FRAME:for:mul#5.itm(6)} -attr vt d
+load net {FRAME:for:mul#5.itm(7)} -attr vt d
+load net {FRAME:for:mul#5.itm(8)} -attr vt d
+load net {FRAME:for:mul#5.itm(9)} -attr vt d
+load net {FRAME:for:mul#5.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#5.itm} 11 {FRAME:for:mul#5.itm(0)} {FRAME:for:mul#5.itm(1)} {FRAME:for:mul#5.itm(2)} {FRAME:for:mul#5.itm(3)} {FRAME:for:mul#5.itm(4)} {FRAME:for:mul#5.itm(5)} {FRAME:for:mul#5.itm(6)} {FRAME:for:mul#5.itm(7)} {FRAME:for:mul#5.itm(8)} {FRAME:for:mul#5.itm(9)} {FRAME:for:mul#5.itm(10)} -attr xrf 39659 -attr oid 146 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {regs.operator[]#11:mux.itm(0)} -attr vt d
+load net {regs.operator[]#11:mux.itm(1)} -attr vt d
+load net {regs.operator[]#11:mux.itm(2)} -attr vt d
+load net {regs.operator[]#11:mux.itm(3)} -attr vt d
+load net {regs.operator[]#11:mux.itm(4)} -attr vt d
+load net {regs.operator[]#11:mux.itm(5)} -attr vt d
+load net {regs.operator[]#11:mux.itm(6)} -attr vt d
+load net {regs.operator[]#11:mux.itm(7)} -attr vt d
+load net {regs.operator[]#11:mux.itm(8)} -attr vt d
+load net {regs.operator[]#11:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#11:mux.itm} 10 {regs.operator[]#11:mux.itm(0)} {regs.operator[]#11:mux.itm(1)} {regs.operator[]#11:mux.itm(2)} {regs.operator[]#11:mux.itm(3)} {regs.operator[]#11:mux.itm(4)} {regs.operator[]#11:mux.itm(5)} {regs.operator[]#11:mux.itm(6)} {regs.operator[]#11:mux.itm(7)} {regs.operator[]#11:mux.itm(8)} {regs.operator[]#11:mux.itm(9)} -attr xrf 39660 -attr oid 147 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm(9)} -attr xrf 39661 -attr oid 148 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#3.itm(9)} -attr xrf 39662 -attr oid 149 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#3.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#3.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#3.itm(9)} -attr xrf 39663 -attr oid 150 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {mux#9.itm(0)} -attr vt d
+load net {mux#9.itm(1)} -attr vt d
+load net {mux#9.itm(2)} -attr vt d
+load net {mux#9.itm(3)} -attr vt d
+load net {mux#9.itm(4)} -attr vt d
+load net {mux#9.itm(5)} -attr vt d
+load net {mux#9.itm(6)} -attr vt d
+load net {mux#9.itm(7)} -attr vt d
+load net {mux#9.itm(8)} -attr vt d
+load net {mux#9.itm(9)} -attr vt d
+load net {mux#9.itm(10)} -attr vt d
+load net {mux#9.itm(11)} -attr vt d
+load net {mux#9.itm(12)} -attr vt d
+load net {mux#9.itm(13)} -attr vt d
+load net {mux#9.itm(14)} -attr vt d
+load netBundle {mux#9.itm} 15 {mux#9.itm(0)} {mux#9.itm(1)} {mux#9.itm(2)} {mux#9.itm(3)} {mux#9.itm(4)} {mux#9.itm(5)} {mux#9.itm(6)} {mux#9.itm(7)} {mux#9.itm(8)} {mux#9.itm(9)} {mux#9.itm(10)} {mux#9.itm(11)} {mux#9.itm(12)} {mux#9.itm(13)} {mux#9.itm(14)} -attr xrf 39664 -attr oid 151 -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {FRAME:for:acc#27.itm(0)} -attr vt d
+load net {FRAME:for:acc#27.itm(1)} -attr vt d
+load net {FRAME:for:acc#27.itm(2)} -attr vt d
+load net {FRAME:for:acc#27.itm(3)} -attr vt d
+load net {FRAME:for:acc#27.itm(4)} -attr vt d
+load net {FRAME:for:acc#27.itm(5)} -attr vt d
+load net {FRAME:for:acc#27.itm(6)} -attr vt d
+load net {FRAME:for:acc#27.itm(7)} -attr vt d
+load net {FRAME:for:acc#27.itm(8)} -attr vt d
+load net {FRAME:for:acc#27.itm(9)} -attr vt d
+load net {FRAME:for:acc#27.itm(10)} -attr vt d
+load net {FRAME:for:acc#27.itm(11)} -attr vt d
+load net {FRAME:for:acc#27.itm(12)} -attr vt d
+load net {FRAME:for:acc#27.itm(13)} -attr vt d
+load net {FRAME:for:acc#27.itm(14)} -attr vt d
+load netBundle {FRAME:for:acc#27.itm} 15 {FRAME:for:acc#27.itm(0)} {FRAME:for:acc#27.itm(1)} {FRAME:for:acc#27.itm(2)} {FRAME:for:acc#27.itm(3)} {FRAME:for:acc#27.itm(4)} {FRAME:for:acc#27.itm(5)} {FRAME:for:acc#27.itm(6)} {FRAME:for:acc#27.itm(7)} {FRAME:for:acc#27.itm(8)} {FRAME:for:acc#27.itm(9)} {FRAME:for:acc#27.itm(10)} {FRAME:for:acc#27.itm(11)} {FRAME:for:acc#27.itm(12)} {FRAME:for:acc#27.itm(13)} {FRAME:for:acc#27.itm(14)} -attr xrf 39665 -attr oid 152 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:mul#4.itm(0)} -attr vt d
+load net {FRAME:for:mul#4.itm(1)} -attr vt d
+load net {FRAME:for:mul#4.itm(2)} -attr vt d
+load net {FRAME:for:mul#4.itm(3)} -attr vt d
+load net {FRAME:for:mul#4.itm(4)} -attr vt d
+load net {FRAME:for:mul#4.itm(5)} -attr vt d
+load net {FRAME:for:mul#4.itm(6)} -attr vt d
+load net {FRAME:for:mul#4.itm(7)} -attr vt d
+load net {FRAME:for:mul#4.itm(8)} -attr vt d
+load net {FRAME:for:mul#4.itm(9)} -attr vt d
+load net {FRAME:for:mul#4.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#4.itm} 11 {FRAME:for:mul#4.itm(0)} {FRAME:for:mul#4.itm(1)} {FRAME:for:mul#4.itm(2)} {FRAME:for:mul#4.itm(3)} {FRAME:for:mul#4.itm(4)} {FRAME:for:mul#4.itm(5)} {FRAME:for:mul#4.itm(6)} {FRAME:for:mul#4.itm(7)} {FRAME:for:mul#4.itm(8)} {FRAME:for:mul#4.itm(9)} {FRAME:for:mul#4.itm(10)} -attr xrf 39666 -attr oid 153 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {regs.operator[]#10:mux.itm(0)} -attr vt d
+load net {regs.operator[]#10:mux.itm(1)} -attr vt d
+load net {regs.operator[]#10:mux.itm(2)} -attr vt d
+load net {regs.operator[]#10:mux.itm(3)} -attr vt d
+load net {regs.operator[]#10:mux.itm(4)} -attr vt d
+load net {regs.operator[]#10:mux.itm(5)} -attr vt d
+load net {regs.operator[]#10:mux.itm(6)} -attr vt d
+load net {regs.operator[]#10:mux.itm(7)} -attr vt d
+load net {regs.operator[]#10:mux.itm(8)} -attr vt d
+load net {regs.operator[]#10:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#10:mux.itm} 10 {regs.operator[]#10:mux.itm(0)} {regs.operator[]#10:mux.itm(1)} {regs.operator[]#10:mux.itm(2)} {regs.operator[]#10:mux.itm(3)} {regs.operator[]#10:mux.itm(4)} {regs.operator[]#10:mux.itm(5)} {regs.operator[]#10:mux.itm(6)} {regs.operator[]#10:mux.itm(7)} {regs.operator[]#10:mux.itm(8)} {regs.operator[]#10:mux.itm(9)} -attr xrf 39667 -attr oid 154 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm(9)} -attr xrf 39668 -attr oid 155 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#4.itm(9)} -attr xrf 39669 -attr oid 156 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#4.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#4.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#4.itm(9)} -attr xrf 39670 -attr oid 157 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {mux#10.itm(0)} -attr vt d
+load net {mux#10.itm(1)} -attr vt d
+load net {mux#10.itm(2)} -attr vt d
+load net {mux#10.itm(3)} -attr vt d
+load net {mux#10.itm(4)} -attr vt d
+load net {mux#10.itm(5)} -attr vt d
+load net {mux#10.itm(6)} -attr vt d
+load net {mux#10.itm(7)} -attr vt d
+load net {mux#10.itm(8)} -attr vt d
+load net {mux#10.itm(9)} -attr vt d
+load net {mux#10.itm(10)} -attr vt d
+load net {mux#10.itm(11)} -attr vt d
+load net {mux#10.itm(12)} -attr vt d
+load net {mux#10.itm(13)} -attr vt d
+load net {mux#10.itm(14)} -attr vt d
+load netBundle {mux#10.itm} 15 {mux#10.itm(0)} {mux#10.itm(1)} {mux#10.itm(2)} {mux#10.itm(3)} {mux#10.itm(4)} {mux#10.itm(5)} {mux#10.itm(6)} {mux#10.itm(7)} {mux#10.itm(8)} {mux#10.itm(9)} {mux#10.itm(10)} {mux#10.itm(11)} {mux#10.itm(12)} {mux#10.itm(13)} {mux#10.itm(14)} -attr xrf 39671 -attr oid 158 -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {FRAME:for:acc#26.itm(0)} -attr vt d
+load net {FRAME:for:acc#26.itm(1)} -attr vt d
+load net {FRAME:for:acc#26.itm(2)} -attr vt d
+load net {FRAME:for:acc#26.itm(3)} -attr vt d
+load net {FRAME:for:acc#26.itm(4)} -attr vt d
+load net {FRAME:for:acc#26.itm(5)} -attr vt d
+load net {FRAME:for:acc#26.itm(6)} -attr vt d
+load net {FRAME:for:acc#26.itm(7)} -attr vt d
+load net {FRAME:for:acc#26.itm(8)} -attr vt d
+load net {FRAME:for:acc#26.itm(9)} -attr vt d
+load net {FRAME:for:acc#26.itm(10)} -attr vt d
+load net {FRAME:for:acc#26.itm(11)} -attr vt d
+load net {FRAME:for:acc#26.itm(12)} -attr vt d
+load net {FRAME:for:acc#26.itm(13)} -attr vt d
+load net {FRAME:for:acc#26.itm(14)} -attr vt d
+load netBundle {FRAME:for:acc#26.itm} 15 {FRAME:for:acc#26.itm(0)} {FRAME:for:acc#26.itm(1)} {FRAME:for:acc#26.itm(2)} {FRAME:for:acc#26.itm(3)} {FRAME:for:acc#26.itm(4)} {FRAME:for:acc#26.itm(5)} {FRAME:for:acc#26.itm(6)} {FRAME:for:acc#26.itm(7)} {FRAME:for:acc#26.itm(8)} {FRAME:for:acc#26.itm(9)} {FRAME:for:acc#26.itm(10)} {FRAME:for:acc#26.itm(11)} {FRAME:for:acc#26.itm(12)} {FRAME:for:acc#26.itm(13)} {FRAME:for:acc#26.itm(14)} -attr xrf 39672 -attr oid 159 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:mul#3.itm(0)} -attr vt d
+load net {FRAME:for:mul#3.itm(1)} -attr vt d
+load net {FRAME:for:mul#3.itm(2)} -attr vt d
+load net {FRAME:for:mul#3.itm(3)} -attr vt d
+load net {FRAME:for:mul#3.itm(4)} -attr vt d
+load net {FRAME:for:mul#3.itm(5)} -attr vt d
+load net {FRAME:for:mul#3.itm(6)} -attr vt d
+load net {FRAME:for:mul#3.itm(7)} -attr vt d
+load net {FRAME:for:mul#3.itm(8)} -attr vt d
+load net {FRAME:for:mul#3.itm(9)} -attr vt d
+load net {FRAME:for:mul#3.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#3.itm} 11 {FRAME:for:mul#3.itm(0)} {FRAME:for:mul#3.itm(1)} {FRAME:for:mul#3.itm(2)} {FRAME:for:mul#3.itm(3)} {FRAME:for:mul#3.itm(4)} {FRAME:for:mul#3.itm(5)} {FRAME:for:mul#3.itm(6)} {FRAME:for:mul#3.itm(7)} {FRAME:for:mul#3.itm(8)} {FRAME:for:mul#3.itm(9)} {FRAME:for:mul#3.itm(10)} -attr xrf 39673 -attr oid 160 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {regs.operator[]#9:mux.itm(0)} -attr vt d
+load net {regs.operator[]#9:mux.itm(1)} -attr vt d
+load net {regs.operator[]#9:mux.itm(2)} -attr vt d
+load net {regs.operator[]#9:mux.itm(3)} -attr vt d
+load net {regs.operator[]#9:mux.itm(4)} -attr vt d
+load net {regs.operator[]#9:mux.itm(5)} -attr vt d
+load net {regs.operator[]#9:mux.itm(6)} -attr vt d
+load net {regs.operator[]#9:mux.itm(7)} -attr vt d
+load net {regs.operator[]#9:mux.itm(8)} -attr vt d
+load net {regs.operator[]#9:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#9:mux.itm} 10 {regs.operator[]#9:mux.itm(0)} {regs.operator[]#9:mux.itm(1)} {regs.operator[]#9:mux.itm(2)} {regs.operator[]#9:mux.itm(3)} {regs.operator[]#9:mux.itm(4)} {regs.operator[]#9:mux.itm(5)} {regs.operator[]#9:mux.itm(6)} {regs.operator[]#9:mux.itm(7)} {regs.operator[]#9:mux.itm(8)} {regs.operator[]#9:mux.itm(9)} -attr xrf 39674 -attr oid 161 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm(9)} -attr xrf 39675 -attr oid 162 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#5.itm(9)} -attr xrf 39676 -attr oid 163 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#5.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#5.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#5.itm(9)} -attr xrf 39677 -attr oid 164 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {mux#11.itm(0)} -attr vt d
+load net {mux#11.itm(1)} -attr vt d
+load netBundle {mux#11.itm} 2 {mux#11.itm(0)} {mux#11.itm(1)} -attr xrf 39678 -attr oid 165 -attr vt d -attr @path {/sobel/sobel:core/mux#11.itm}
+load net {mux#12.itm(0)} -attr vt d
+load net {mux#12.itm(1)} -attr vt d
+load net {mux#12.itm(2)} -attr vt d
+load net {mux#12.itm(3)} -attr vt d
+load net {mux#12.itm(4)} -attr vt d
+load net {mux#12.itm(5)} -attr vt d
+load net {mux#12.itm(6)} -attr vt d
+load net {mux#12.itm(7)} -attr vt d
+load net {mux#12.itm(8)} -attr vt d
+load net {mux#12.itm(9)} -attr vt d
+load net {mux#12.itm(10)} -attr vt d
+load net {mux#12.itm(11)} -attr vt d
+load net {mux#12.itm(12)} -attr vt d
+load net {mux#12.itm(13)} -attr vt d
+load net {mux#12.itm(14)} -attr vt d
+load net {mux#12.itm(15)} -attr vt d
+load netBundle {mux#12.itm} 16 {mux#12.itm(0)} {mux#12.itm(1)} {mux#12.itm(2)} {mux#12.itm(3)} {mux#12.itm(4)} {mux#12.itm(5)} {mux#12.itm(6)} {mux#12.itm(7)} {mux#12.itm(8)} {mux#12.itm(9)} {mux#12.itm(10)} {mux#12.itm(11)} {mux#12.itm(12)} {mux#12.itm(13)} {mux#12.itm(14)} {mux#12.itm(15)} -attr xrf 39679 -attr oid 166 -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {FRAME:for:acc#14.itm(0)} -attr vt d
+load net {FRAME:for:acc#14.itm(1)} -attr vt d
+load net {FRAME:for:acc#14.itm(2)} -attr vt d
+load net {FRAME:for:acc#14.itm(3)} -attr vt d
+load net {FRAME:for:acc#14.itm(4)} -attr vt d
+load net {FRAME:for:acc#14.itm(5)} -attr vt d
+load net {FRAME:for:acc#14.itm(6)} -attr vt d
+load net {FRAME:for:acc#14.itm(7)} -attr vt d
+load net {FRAME:for:acc#14.itm(8)} -attr vt d
+load net {FRAME:for:acc#14.itm(9)} -attr vt d
+load net {FRAME:for:acc#14.itm(10)} -attr vt d
+load net {FRAME:for:acc#14.itm(11)} -attr vt d
+load net {FRAME:for:acc#14.itm(12)} -attr vt d
+load net {FRAME:for:acc#14.itm(13)} -attr vt d
+load net {FRAME:for:acc#14.itm(14)} -attr vt d
+load net {FRAME:for:acc#14.itm(15)} -attr vt d
+load netBundle {FRAME:for:acc#14.itm} 16 {FRAME:for:acc#14.itm(0)} {FRAME:for:acc#14.itm(1)} {FRAME:for:acc#14.itm(2)} {FRAME:for:acc#14.itm(3)} {FRAME:for:acc#14.itm(4)} {FRAME:for:acc#14.itm(5)} {FRAME:for:acc#14.itm(6)} {FRAME:for:acc#14.itm(7)} {FRAME:for:acc#14.itm(8)} {FRAME:for:acc#14.itm(9)} {FRAME:for:acc#14.itm(10)} {FRAME:for:acc#14.itm(11)} {FRAME:for:acc#14.itm(12)} {FRAME:for:acc#14.itm(13)} {FRAME:for:acc#14.itm(14)} {FRAME:for:acc#14.itm(15)} -attr xrf 39680 -attr oid 167 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:mul#8.itm(0)} -attr vt d
+load net {FRAME:for:mul#8.itm(1)} -attr vt d
+load net {FRAME:for:mul#8.itm(2)} -attr vt d
+load net {FRAME:for:mul#8.itm(3)} -attr vt d
+load net {FRAME:for:mul#8.itm(4)} -attr vt d
+load net {FRAME:for:mul#8.itm(5)} -attr vt d
+load net {FRAME:for:mul#8.itm(6)} -attr vt d
+load net {FRAME:for:mul#8.itm(7)} -attr vt d
+load net {FRAME:for:mul#8.itm(8)} -attr vt d
+load net {FRAME:for:mul#8.itm(9)} -attr vt d
+load net {FRAME:for:mul#8.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#8.itm} 11 {FRAME:for:mul#8.itm(0)} {FRAME:for:mul#8.itm(1)} {FRAME:for:mul#8.itm(2)} {FRAME:for:mul#8.itm(3)} {FRAME:for:mul#8.itm(4)} {FRAME:for:mul#8.itm(5)} {FRAME:for:mul#8.itm(6)} {FRAME:for:mul#8.itm(7)} {FRAME:for:mul#8.itm(8)} {FRAME:for:mul#8.itm(9)} {FRAME:for:mul#8.itm(10)} -attr xrf 39681 -attr oid 168 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {regs.operator[]#14:mux.itm(0)} -attr vt d
+load net {regs.operator[]#14:mux.itm(1)} -attr vt d
+load net {regs.operator[]#14:mux.itm(2)} -attr vt d
+load net {regs.operator[]#14:mux.itm(3)} -attr vt d
+load net {regs.operator[]#14:mux.itm(4)} -attr vt d
+load net {regs.operator[]#14:mux.itm(5)} -attr vt d
+load net {regs.operator[]#14:mux.itm(6)} -attr vt d
+load net {regs.operator[]#14:mux.itm(7)} -attr vt d
+load net {regs.operator[]#14:mux.itm(8)} -attr vt d
+load net {regs.operator[]#14:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#14:mux.itm} 10 {regs.operator[]#14:mux.itm(0)} {regs.operator[]#14:mux.itm(1)} {regs.operator[]#14:mux.itm(2)} {regs.operator[]#14:mux.itm(3)} {regs.operator[]#14:mux.itm(4)} {regs.operator[]#14:mux.itm(5)} {regs.operator[]#14:mux.itm(6)} {regs.operator[]#14:mux.itm(7)} {regs.operator[]#14:mux.itm(8)} {regs.operator[]#14:mux.itm(9)} -attr xrf 39682 -attr oid 169 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0).itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0).itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0).itm(9)} -attr xrf 39683 -attr oid 170 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0).itm} 10 {slc(regs.regs(1).sva.dfm:mx0).itm(0)} {slc(regs.regs(1).sva.dfm:mx0).itm(1)} {slc(regs.regs(1).sva.dfm:mx0).itm(2)} {slc(regs.regs(1).sva.dfm:mx0).itm(3)} {slc(regs.regs(1).sva.dfm:mx0).itm(4)} {slc(regs.regs(1).sva.dfm:mx0).itm(5)} {slc(regs.regs(1).sva.dfm:mx0).itm(6)} {slc(regs.regs(1).sva.dfm:mx0).itm(7)} {slc(regs.regs(1).sva.dfm:mx0).itm(8)} {slc(regs.regs(1).sva.dfm:mx0).itm(9)} -attr xrf 39684 -attr oid 171 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0).itm} 10 {slc(regs.regs(0).sva.dfm:mx0).itm(0)} {slc(regs.regs(0).sva.dfm:mx0).itm(1)} {slc(regs.regs(0).sva.dfm:mx0).itm(2)} {slc(regs.regs(0).sva.dfm:mx0).itm(3)} {slc(regs.regs(0).sva.dfm:mx0).itm(4)} {slc(regs.regs(0).sva.dfm:mx0).itm(5)} {slc(regs.regs(0).sva.dfm:mx0).itm(6)} {slc(regs.regs(0).sva.dfm:mx0).itm(7)} {slc(regs.regs(0).sva.dfm:mx0).itm(8)} {slc(regs.regs(0).sva.dfm:mx0).itm(9)} -attr xrf 39685 -attr oid 172 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {mux#13.itm(0)} -attr vt d
+load net {mux#13.itm(1)} -attr vt d
+load net {mux#13.itm(2)} -attr vt d
+load net {mux#13.itm(3)} -attr vt d
+load net {mux#13.itm(4)} -attr vt d
+load net {mux#13.itm(5)} -attr vt d
+load net {mux#13.itm(6)} -attr vt d
+load net {mux#13.itm(7)} -attr vt d
+load net {mux#13.itm(8)} -attr vt d
+load net {mux#13.itm(9)} -attr vt d
+load net {mux#13.itm(10)} -attr vt d
+load net {mux#13.itm(11)} -attr vt d
+load net {mux#13.itm(12)} -attr vt d
+load net {mux#13.itm(13)} -attr vt d
+load net {mux#13.itm(14)} -attr vt d
+load net {mux#13.itm(15)} -attr vt d
+load netBundle {mux#13.itm} 16 {mux#13.itm(0)} {mux#13.itm(1)} {mux#13.itm(2)} {mux#13.itm(3)} {mux#13.itm(4)} {mux#13.itm(5)} {mux#13.itm(6)} {mux#13.itm(7)} {mux#13.itm(8)} {mux#13.itm(9)} {mux#13.itm(10)} {mux#13.itm(11)} {mux#13.itm(12)} {mux#13.itm(13)} {mux#13.itm(14)} {mux#13.itm(15)} -attr xrf 39686 -attr oid 173 -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {FRAME:for:acc#3.itm(0)} -attr vt d
+load net {FRAME:for:acc#3.itm(1)} -attr vt d
+load net {FRAME:for:acc#3.itm(2)} -attr vt d
+load net {FRAME:for:acc#3.itm(3)} -attr vt d
+load net {FRAME:for:acc#3.itm(4)} -attr vt d
+load net {FRAME:for:acc#3.itm(5)} -attr vt d
+load net {FRAME:for:acc#3.itm(6)} -attr vt d
+load net {FRAME:for:acc#3.itm(7)} -attr vt d
+load net {FRAME:for:acc#3.itm(8)} -attr vt d
+load net {FRAME:for:acc#3.itm(9)} -attr vt d
+load net {FRAME:for:acc#3.itm(10)} -attr vt d
+load net {FRAME:for:acc#3.itm(11)} -attr vt d
+load net {FRAME:for:acc#3.itm(12)} -attr vt d
+load net {FRAME:for:acc#3.itm(13)} -attr vt d
+load net {FRAME:for:acc#3.itm(14)} -attr vt d
+load net {FRAME:for:acc#3.itm(15)} -attr vt d
+load netBundle {FRAME:for:acc#3.itm} 16 {FRAME:for:acc#3.itm(0)} {FRAME:for:acc#3.itm(1)} {FRAME:for:acc#3.itm(2)} {FRAME:for:acc#3.itm(3)} {FRAME:for:acc#3.itm(4)} {FRAME:for:acc#3.itm(5)} {FRAME:for:acc#3.itm(6)} {FRAME:for:acc#3.itm(7)} {FRAME:for:acc#3.itm(8)} {FRAME:for:acc#3.itm(9)} {FRAME:for:acc#3.itm(10)} {FRAME:for:acc#3.itm(11)} {FRAME:for:acc#3.itm(12)} {FRAME:for:acc#3.itm(13)} {FRAME:for:acc#3.itm(14)} {FRAME:for:acc#3.itm(15)} -attr xrf 39687 -attr oid 174 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:mul#2.itm(0)} -attr vt d
+load net {FRAME:for:mul#2.itm(1)} -attr vt d
+load net {FRAME:for:mul#2.itm(2)} -attr vt d
+load net {FRAME:for:mul#2.itm(3)} -attr vt d
+load net {FRAME:for:mul#2.itm(4)} -attr vt d
+load net {FRAME:for:mul#2.itm(5)} -attr vt d
+load net {FRAME:for:mul#2.itm(6)} -attr vt d
+load net {FRAME:for:mul#2.itm(7)} -attr vt d
+load net {FRAME:for:mul#2.itm(8)} -attr vt d
+load net {FRAME:for:mul#2.itm(9)} -attr vt d
+load net {FRAME:for:mul#2.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#2.itm} 11 {FRAME:for:mul#2.itm(0)} {FRAME:for:mul#2.itm(1)} {FRAME:for:mul#2.itm(2)} {FRAME:for:mul#2.itm(3)} {FRAME:for:mul#2.itm(4)} {FRAME:for:mul#2.itm(5)} {FRAME:for:mul#2.itm(6)} {FRAME:for:mul#2.itm(7)} {FRAME:for:mul#2.itm(8)} {FRAME:for:mul#2.itm(9)} {FRAME:for:mul#2.itm(10)} -attr xrf 39688 -attr oid 175 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {regs.operator[]#8:mux.itm(0)} -attr vt d
+load net {regs.operator[]#8:mux.itm(1)} -attr vt d
+load net {regs.operator[]#8:mux.itm(2)} -attr vt d
+load net {regs.operator[]#8:mux.itm(3)} -attr vt d
+load net {regs.operator[]#8:mux.itm(4)} -attr vt d
+load net {regs.operator[]#8:mux.itm(5)} -attr vt d
+load net {regs.operator[]#8:mux.itm(6)} -attr vt d
+load net {regs.operator[]#8:mux.itm(7)} -attr vt d
+load net {regs.operator[]#8:mux.itm(8)} -attr vt d
+load net {regs.operator[]#8:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#8:mux.itm} 10 {regs.operator[]#8:mux.itm(0)} {regs.operator[]#8:mux.itm(1)} {regs.operator[]#8:mux.itm(2)} {regs.operator[]#8:mux.itm(3)} {regs.operator[]#8:mux.itm(4)} {regs.operator[]#8:mux.itm(5)} {regs.operator[]#8:mux.itm(6)} {regs.operator[]#8:mux.itm(7)} {regs.operator[]#8:mux.itm(8)} {regs.operator[]#8:mux.itm(9)} -attr xrf 39689 -attr oid 176 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm(9)} -attr xrf 39690 -attr oid 177 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#6.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#6.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#6.itm(9)} -attr xrf 39691 -attr oid 178 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#6.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#6.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#6.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#6.itm(9)} -attr xrf 39692 -attr oid 179 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {mux#14.itm(0)} -attr vt d
+load net {mux#14.itm(1)} -attr vt d
+load net {mux#14.itm(2)} -attr vt d
+load net {mux#14.itm(3)} -attr vt d
+load net {mux#14.itm(4)} -attr vt d
+load net {mux#14.itm(5)} -attr vt d
+load net {mux#14.itm(6)} -attr vt d
+load net {mux#14.itm(7)} -attr vt d
+load net {mux#14.itm(8)} -attr vt d
+load net {mux#14.itm(9)} -attr vt d
+load net {mux#14.itm(10)} -attr vt d
+load net {mux#14.itm(11)} -attr vt d
+load net {mux#14.itm(12)} -attr vt d
+load net {mux#14.itm(13)} -attr vt d
+load net {mux#14.itm(14)} -attr vt d
+load net {mux#14.itm(15)} -attr vt d
+load netBundle {mux#14.itm} 16 {mux#14.itm(0)} {mux#14.itm(1)} {mux#14.itm(2)} {mux#14.itm(3)} {mux#14.itm(4)} {mux#14.itm(5)} {mux#14.itm(6)} {mux#14.itm(7)} {mux#14.itm(8)} {mux#14.itm(9)} {mux#14.itm(10)} {mux#14.itm(11)} {mux#14.itm(12)} {mux#14.itm(13)} {mux#14.itm(14)} {mux#14.itm(15)} -attr xrf 39693 -attr oid 180 -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {FRAME:for:acc#12.itm(0)} -attr vt d
+load net {FRAME:for:acc#12.itm(1)} -attr vt d
+load net {FRAME:for:acc#12.itm(2)} -attr vt d
+load net {FRAME:for:acc#12.itm(3)} -attr vt d
+load net {FRAME:for:acc#12.itm(4)} -attr vt d
+load net {FRAME:for:acc#12.itm(5)} -attr vt d
+load net {FRAME:for:acc#12.itm(6)} -attr vt d
+load net {FRAME:for:acc#12.itm(7)} -attr vt d
+load net {FRAME:for:acc#12.itm(8)} -attr vt d
+load net {FRAME:for:acc#12.itm(9)} -attr vt d
+load net {FRAME:for:acc#12.itm(10)} -attr vt d
+load net {FRAME:for:acc#12.itm(11)} -attr vt d
+load net {FRAME:for:acc#12.itm(12)} -attr vt d
+load net {FRAME:for:acc#12.itm(13)} -attr vt d
+load net {FRAME:for:acc#12.itm(14)} -attr vt d
+load net {FRAME:for:acc#12.itm(15)} -attr vt d
+load netBundle {FRAME:for:acc#12.itm} 16 {FRAME:for:acc#12.itm(0)} {FRAME:for:acc#12.itm(1)} {FRAME:for:acc#12.itm(2)} {FRAME:for:acc#12.itm(3)} {FRAME:for:acc#12.itm(4)} {FRAME:for:acc#12.itm(5)} {FRAME:for:acc#12.itm(6)} {FRAME:for:acc#12.itm(7)} {FRAME:for:acc#12.itm(8)} {FRAME:for:acc#12.itm(9)} {FRAME:for:acc#12.itm(10)} {FRAME:for:acc#12.itm(11)} {FRAME:for:acc#12.itm(12)} {FRAME:for:acc#12.itm(13)} {FRAME:for:acc#12.itm(14)} {FRAME:for:acc#12.itm(15)} -attr xrf 39694 -attr oid 181 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:mul#7.itm(0)} -attr vt d
+load net {FRAME:for:mul#7.itm(1)} -attr vt d
+load net {FRAME:for:mul#7.itm(2)} -attr vt d
+load net {FRAME:for:mul#7.itm(3)} -attr vt d
+load net {FRAME:for:mul#7.itm(4)} -attr vt d
+load net {FRAME:for:mul#7.itm(5)} -attr vt d
+load net {FRAME:for:mul#7.itm(6)} -attr vt d
+load net {FRAME:for:mul#7.itm(7)} -attr vt d
+load net {FRAME:for:mul#7.itm(8)} -attr vt d
+load net {FRAME:for:mul#7.itm(9)} -attr vt d
+load net {FRAME:for:mul#7.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#7.itm} 11 {FRAME:for:mul#7.itm(0)} {FRAME:for:mul#7.itm(1)} {FRAME:for:mul#7.itm(2)} {FRAME:for:mul#7.itm(3)} {FRAME:for:mul#7.itm(4)} {FRAME:for:mul#7.itm(5)} {FRAME:for:mul#7.itm(6)} {FRAME:for:mul#7.itm(7)} {FRAME:for:mul#7.itm(8)} {FRAME:for:mul#7.itm(9)} {FRAME:for:mul#7.itm(10)} -attr xrf 39695 -attr oid 182 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {regs.operator[]#13:mux.itm(0)} -attr vt d
+load net {regs.operator[]#13:mux.itm(1)} -attr vt d
+load net {regs.operator[]#13:mux.itm(2)} -attr vt d
+load net {regs.operator[]#13:mux.itm(3)} -attr vt d
+load net {regs.operator[]#13:mux.itm(4)} -attr vt d
+load net {regs.operator[]#13:mux.itm(5)} -attr vt d
+load net {regs.operator[]#13:mux.itm(6)} -attr vt d
+load net {regs.operator[]#13:mux.itm(7)} -attr vt d
+load net {regs.operator[]#13:mux.itm(8)} -attr vt d
+load net {regs.operator[]#13:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#13:mux.itm} 10 {regs.operator[]#13:mux.itm(0)} {regs.operator[]#13:mux.itm(1)} {regs.operator[]#13:mux.itm(2)} {regs.operator[]#13:mux.itm(3)} {regs.operator[]#13:mux.itm(4)} {regs.operator[]#13:mux.itm(5)} {regs.operator[]#13:mux.itm(6)} {regs.operator[]#13:mux.itm(7)} {regs.operator[]#13:mux.itm(8)} {regs.operator[]#13:mux.itm(9)} -attr xrf 39696 -attr oid 183 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm(9)} -attr xrf 39697 -attr oid 184 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#1.itm(9)} -attr xrf 39698 -attr oid 185 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#1.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#1.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#1.itm(9)} -attr xrf 39699 -attr oid 186 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {mux#15.itm(0)} -attr vt d
+load net {mux#15.itm(1)} -attr vt d
+load net {mux#15.itm(2)} -attr vt d
+load net {mux#15.itm(3)} -attr vt d
+load net {mux#15.itm(4)} -attr vt d
+load net {mux#15.itm(5)} -attr vt d
+load net {mux#15.itm(6)} -attr vt d
+load net {mux#15.itm(7)} -attr vt d
+load net {mux#15.itm(8)} -attr vt d
+load net {mux#15.itm(9)} -attr vt d
+load net {mux#15.itm(10)} -attr vt d
+load net {mux#15.itm(11)} -attr vt d
+load net {mux#15.itm(12)} -attr vt d
+load net {mux#15.itm(13)} -attr vt d
+load net {mux#15.itm(14)} -attr vt d
+load net {mux#15.itm(15)} -attr vt d
+load netBundle {mux#15.itm} 16 {mux#15.itm(0)} {mux#15.itm(1)} {mux#15.itm(2)} {mux#15.itm(3)} {mux#15.itm(4)} {mux#15.itm(5)} {mux#15.itm(6)} {mux#15.itm(7)} {mux#15.itm(8)} {mux#15.itm(9)} {mux#15.itm(10)} {mux#15.itm(11)} {mux#15.itm(12)} {mux#15.itm(13)} {mux#15.itm(14)} {mux#15.itm(15)} -attr xrf 39700 -attr oid 187 -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {FRAME:for:acc#2.itm(0)} -attr vt d
+load net {FRAME:for:acc#2.itm(1)} -attr vt d
+load net {FRAME:for:acc#2.itm(2)} -attr vt d
+load net {FRAME:for:acc#2.itm(3)} -attr vt d
+load net {FRAME:for:acc#2.itm(4)} -attr vt d
+load net {FRAME:for:acc#2.itm(5)} -attr vt d
+load net {FRAME:for:acc#2.itm(6)} -attr vt d
+load net {FRAME:for:acc#2.itm(7)} -attr vt d
+load net {FRAME:for:acc#2.itm(8)} -attr vt d
+load net {FRAME:for:acc#2.itm(9)} -attr vt d
+load net {FRAME:for:acc#2.itm(10)} -attr vt d
+load net {FRAME:for:acc#2.itm(11)} -attr vt d
+load net {FRAME:for:acc#2.itm(12)} -attr vt d
+load net {FRAME:for:acc#2.itm(13)} -attr vt d
+load net {FRAME:for:acc#2.itm(14)} -attr vt d
+load net {FRAME:for:acc#2.itm(15)} -attr vt d
+load netBundle {FRAME:for:acc#2.itm} 16 {FRAME:for:acc#2.itm(0)} {FRAME:for:acc#2.itm(1)} {FRAME:for:acc#2.itm(2)} {FRAME:for:acc#2.itm(3)} {FRAME:for:acc#2.itm(4)} {FRAME:for:acc#2.itm(5)} {FRAME:for:acc#2.itm(6)} {FRAME:for:acc#2.itm(7)} {FRAME:for:acc#2.itm(8)} {FRAME:for:acc#2.itm(9)} {FRAME:for:acc#2.itm(10)} {FRAME:for:acc#2.itm(11)} {FRAME:for:acc#2.itm(12)} {FRAME:for:acc#2.itm(13)} {FRAME:for:acc#2.itm(14)} {FRAME:for:acc#2.itm(15)} -attr xrf 39701 -attr oid 188 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:mul#1.itm(0)} -attr vt d
+load net {FRAME:for:mul#1.itm(1)} -attr vt d
+load net {FRAME:for:mul#1.itm(2)} -attr vt d
+load net {FRAME:for:mul#1.itm(3)} -attr vt d
+load net {FRAME:for:mul#1.itm(4)} -attr vt d
+load net {FRAME:for:mul#1.itm(5)} -attr vt d
+load net {FRAME:for:mul#1.itm(6)} -attr vt d
+load net {FRAME:for:mul#1.itm(7)} -attr vt d
+load net {FRAME:for:mul#1.itm(8)} -attr vt d
+load net {FRAME:for:mul#1.itm(9)} -attr vt d
+load net {FRAME:for:mul#1.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#1.itm} 11 {FRAME:for:mul#1.itm(0)} {FRAME:for:mul#1.itm(1)} {FRAME:for:mul#1.itm(2)} {FRAME:for:mul#1.itm(3)} {FRAME:for:mul#1.itm(4)} {FRAME:for:mul#1.itm(5)} {FRAME:for:mul#1.itm(6)} {FRAME:for:mul#1.itm(7)} {FRAME:for:mul#1.itm(8)} {FRAME:for:mul#1.itm(9)} {FRAME:for:mul#1.itm(10)} -attr xrf 39702 -attr oid 189 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {regs.operator[]#7:mux.itm(0)} -attr vt d
+load net {regs.operator[]#7:mux.itm(1)} -attr vt d
+load net {regs.operator[]#7:mux.itm(2)} -attr vt d
+load net {regs.operator[]#7:mux.itm(3)} -attr vt d
+load net {regs.operator[]#7:mux.itm(4)} -attr vt d
+load net {regs.operator[]#7:mux.itm(5)} -attr vt d
+load net {regs.operator[]#7:mux.itm(6)} -attr vt d
+load net {regs.operator[]#7:mux.itm(7)} -attr vt d
+load net {regs.operator[]#7:mux.itm(8)} -attr vt d
+load net {regs.operator[]#7:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#7:mux.itm} 10 {regs.operator[]#7:mux.itm(0)} {regs.operator[]#7:mux.itm(1)} {regs.operator[]#7:mux.itm(2)} {regs.operator[]#7:mux.itm(3)} {regs.operator[]#7:mux.itm(4)} {regs.operator[]#7:mux.itm(5)} {regs.operator[]#7:mux.itm(6)} {regs.operator[]#7:mux.itm(7)} {regs.operator[]#7:mux.itm(8)} {regs.operator[]#7:mux.itm(9)} -attr xrf 39703 -attr oid 190 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm(9)} -attr xrf 39704 -attr oid 191 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#7.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#7.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#7.itm(9)} -attr xrf 39705 -attr oid 192 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#7.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#7.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#7.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#7.itm(9)} -attr xrf 39706 -attr oid 193 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {mux#16.itm(0)} -attr vt d
+load net {mux#16.itm(1)} -attr vt d
+load net {mux#16.itm(2)} -attr vt d
+load net {mux#16.itm(3)} -attr vt d
+load net {mux#16.itm(4)} -attr vt d
+load net {mux#16.itm(5)} -attr vt d
+load net {mux#16.itm(6)} -attr vt d
+load net {mux#16.itm(7)} -attr vt d
+load net {mux#16.itm(8)} -attr vt d
+load net {mux#16.itm(9)} -attr vt d
+load net {mux#16.itm(10)} -attr vt d
+load net {mux#16.itm(11)} -attr vt d
+load net {mux#16.itm(12)} -attr vt d
+load net {mux#16.itm(13)} -attr vt d
+load net {mux#16.itm(14)} -attr vt d
+load net {mux#16.itm(15)} -attr vt d
+load netBundle {mux#16.itm} 16 {mux#16.itm(0)} {mux#16.itm(1)} {mux#16.itm(2)} {mux#16.itm(3)} {mux#16.itm(4)} {mux#16.itm(5)} {mux#16.itm(6)} {mux#16.itm(7)} {mux#16.itm(8)} {mux#16.itm(9)} {mux#16.itm(10)} {mux#16.itm(11)} {mux#16.itm(12)} {mux#16.itm(13)} {mux#16.itm(14)} {mux#16.itm(15)} -attr xrf 39707 -attr oid 194 -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {FRAME:for:acc#10.itm(0)} -attr vt d
+load net {FRAME:for:acc#10.itm(1)} -attr vt d
+load net {FRAME:for:acc#10.itm(2)} -attr vt d
+load net {FRAME:for:acc#10.itm(3)} -attr vt d
+load net {FRAME:for:acc#10.itm(4)} -attr vt d
+load net {FRAME:for:acc#10.itm(5)} -attr vt d
+load net {FRAME:for:acc#10.itm(6)} -attr vt d
+load net {FRAME:for:acc#10.itm(7)} -attr vt d
+load net {FRAME:for:acc#10.itm(8)} -attr vt d
+load net {FRAME:for:acc#10.itm(9)} -attr vt d
+load net {FRAME:for:acc#10.itm(10)} -attr vt d
+load net {FRAME:for:acc#10.itm(11)} -attr vt d
+load net {FRAME:for:acc#10.itm(12)} -attr vt d
+load net {FRAME:for:acc#10.itm(13)} -attr vt d
+load net {FRAME:for:acc#10.itm(14)} -attr vt d
+load net {FRAME:for:acc#10.itm(15)} -attr vt d
+load netBundle {FRAME:for:acc#10.itm} 16 {FRAME:for:acc#10.itm(0)} {FRAME:for:acc#10.itm(1)} {FRAME:for:acc#10.itm(2)} {FRAME:for:acc#10.itm(3)} {FRAME:for:acc#10.itm(4)} {FRAME:for:acc#10.itm(5)} {FRAME:for:acc#10.itm(6)} {FRAME:for:acc#10.itm(7)} {FRAME:for:acc#10.itm(8)} {FRAME:for:acc#10.itm(9)} {FRAME:for:acc#10.itm(10)} {FRAME:for:acc#10.itm(11)} {FRAME:for:acc#10.itm(12)} {FRAME:for:acc#10.itm(13)} {FRAME:for:acc#10.itm(14)} {FRAME:for:acc#10.itm(15)} -attr xrf 39708 -attr oid 195 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:mul#6.itm(0)} -attr vt d
+load net {FRAME:for:mul#6.itm(1)} -attr vt d
+load net {FRAME:for:mul#6.itm(2)} -attr vt d
+load net {FRAME:for:mul#6.itm(3)} -attr vt d
+load net {FRAME:for:mul#6.itm(4)} -attr vt d
+load net {FRAME:for:mul#6.itm(5)} -attr vt d
+load net {FRAME:for:mul#6.itm(6)} -attr vt d
+load net {FRAME:for:mul#6.itm(7)} -attr vt d
+load net {FRAME:for:mul#6.itm(8)} -attr vt d
+load net {FRAME:for:mul#6.itm(9)} -attr vt d
+load net {FRAME:for:mul#6.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul#6.itm} 11 {FRAME:for:mul#6.itm(0)} {FRAME:for:mul#6.itm(1)} {FRAME:for:mul#6.itm(2)} {FRAME:for:mul#6.itm(3)} {FRAME:for:mul#6.itm(4)} {FRAME:for:mul#6.itm(5)} {FRAME:for:mul#6.itm(6)} {FRAME:for:mul#6.itm(7)} {FRAME:for:mul#6.itm(8)} {FRAME:for:mul#6.itm(9)} {FRAME:for:mul#6.itm(10)} -attr xrf 39709 -attr oid 196 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {regs.operator[]#12:mux.itm(0)} -attr vt d
+load net {regs.operator[]#12:mux.itm(1)} -attr vt d
+load net {regs.operator[]#12:mux.itm(2)} -attr vt d
+load net {regs.operator[]#12:mux.itm(3)} -attr vt d
+load net {regs.operator[]#12:mux.itm(4)} -attr vt d
+load net {regs.operator[]#12:mux.itm(5)} -attr vt d
+load net {regs.operator[]#12:mux.itm(6)} -attr vt d
+load net {regs.operator[]#12:mux.itm(7)} -attr vt d
+load net {regs.operator[]#12:mux.itm(8)} -attr vt d
+load net {regs.operator[]#12:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#12:mux.itm} 10 {regs.operator[]#12:mux.itm(0)} {regs.operator[]#12:mux.itm(1)} {regs.operator[]#12:mux.itm(2)} {regs.operator[]#12:mux.itm(3)} {regs.operator[]#12:mux.itm(4)} {regs.operator[]#12:mux.itm(5)} {regs.operator[]#12:mux.itm(6)} {regs.operator[]#12:mux.itm(7)} {regs.operator[]#12:mux.itm(8)} {regs.operator[]#12:mux.itm(9)} -attr xrf 39710 -attr oid 197 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm(9)} -attr xrf 39711 -attr oid 198 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#2.itm(9)} -attr xrf 39712 -attr oid 199 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#2.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#2.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#2.itm(9)} -attr xrf 39713 -attr oid 200 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {mux#17.itm(0)} -attr vt d
+load net {mux#17.itm(1)} -attr vt d
+load net {mux#17.itm(2)} -attr vt d
+load net {mux#17.itm(3)} -attr vt d
+load net {mux#17.itm(4)} -attr vt d
+load net {mux#17.itm(5)} -attr vt d
+load net {mux#17.itm(6)} -attr vt d
+load net {mux#17.itm(7)} -attr vt d
+load net {mux#17.itm(8)} -attr vt d
+load net {mux#17.itm(9)} -attr vt d
+load net {mux#17.itm(10)} -attr vt d
+load net {mux#17.itm(11)} -attr vt d
+load net {mux#17.itm(12)} -attr vt d
+load net {mux#17.itm(13)} -attr vt d
+load net {mux#17.itm(14)} -attr vt d
+load net {mux#17.itm(15)} -attr vt d
+load netBundle {mux#17.itm} 16 {mux#17.itm(0)} {mux#17.itm(1)} {mux#17.itm(2)} {mux#17.itm(3)} {mux#17.itm(4)} {mux#17.itm(5)} {mux#17.itm(6)} {mux#17.itm(7)} {mux#17.itm(8)} {mux#17.itm(9)} {mux#17.itm(10)} {mux#17.itm(11)} {mux#17.itm(12)} {mux#17.itm(13)} {mux#17.itm(14)} {mux#17.itm(15)} -attr xrf 39714 -attr oid 201 -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {FRAME:for:acc#1.itm(0)} -attr vt d
+load net {FRAME:for:acc#1.itm(1)} -attr vt d
+load net {FRAME:for:acc#1.itm(2)} -attr vt d
+load net {FRAME:for:acc#1.itm(3)} -attr vt d
+load net {FRAME:for:acc#1.itm(4)} -attr vt d
+load net {FRAME:for:acc#1.itm(5)} -attr vt d
+load net {FRAME:for:acc#1.itm(6)} -attr vt d
+load net {FRAME:for:acc#1.itm(7)} -attr vt d
+load net {FRAME:for:acc#1.itm(8)} -attr vt d
+load net {FRAME:for:acc#1.itm(9)} -attr vt d
+load net {FRAME:for:acc#1.itm(10)} -attr vt d
+load net {FRAME:for:acc#1.itm(11)} -attr vt d
+load net {FRAME:for:acc#1.itm(12)} -attr vt d
+load net {FRAME:for:acc#1.itm(13)} -attr vt d
+load net {FRAME:for:acc#1.itm(14)} -attr vt d
+load net {FRAME:for:acc#1.itm(15)} -attr vt d
+load netBundle {FRAME:for:acc#1.itm} 16 {FRAME:for:acc#1.itm(0)} {FRAME:for:acc#1.itm(1)} {FRAME:for:acc#1.itm(2)} {FRAME:for:acc#1.itm(3)} {FRAME:for:acc#1.itm(4)} {FRAME:for:acc#1.itm(5)} {FRAME:for:acc#1.itm(6)} {FRAME:for:acc#1.itm(7)} {FRAME:for:acc#1.itm(8)} {FRAME:for:acc#1.itm(9)} {FRAME:for:acc#1.itm(10)} {FRAME:for:acc#1.itm(11)} {FRAME:for:acc#1.itm(12)} {FRAME:for:acc#1.itm(13)} {FRAME:for:acc#1.itm(14)} {FRAME:for:acc#1.itm(15)} -attr xrf 39715 -attr oid 202 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:mul.itm(0)} -attr vt d
+load net {FRAME:for:mul.itm(1)} -attr vt d
+load net {FRAME:for:mul.itm(2)} -attr vt d
+load net {FRAME:for:mul.itm(3)} -attr vt d
+load net {FRAME:for:mul.itm(4)} -attr vt d
+load net {FRAME:for:mul.itm(5)} -attr vt d
+load net {FRAME:for:mul.itm(6)} -attr vt d
+load net {FRAME:for:mul.itm(7)} -attr vt d
+load net {FRAME:for:mul.itm(8)} -attr vt d
+load net {FRAME:for:mul.itm(9)} -attr vt d
+load net {FRAME:for:mul.itm(10)} -attr vt d
+load netBundle {FRAME:for:mul.itm} 11 {FRAME:for:mul.itm(0)} {FRAME:for:mul.itm(1)} {FRAME:for:mul.itm(2)} {FRAME:for:mul.itm(3)} {FRAME:for:mul.itm(4)} {FRAME:for:mul.itm(5)} {FRAME:for:mul.itm(6)} {FRAME:for:mul.itm(7)} {FRAME:for:mul.itm(8)} {FRAME:for:mul.itm(9)} {FRAME:for:mul.itm(10)} -attr xrf 39716 -attr oid 203 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {regs.operator[]#6:mux.itm(0)} -attr vt d
+load net {regs.operator[]#6:mux.itm(1)} -attr vt d
+load net {regs.operator[]#6:mux.itm(2)} -attr vt d
+load net {regs.operator[]#6:mux.itm(3)} -attr vt d
+load net {regs.operator[]#6:mux.itm(4)} -attr vt d
+load net {regs.operator[]#6:mux.itm(5)} -attr vt d
+load net {regs.operator[]#6:mux.itm(6)} -attr vt d
+load net {regs.operator[]#6:mux.itm(7)} -attr vt d
+load net {regs.operator[]#6:mux.itm(8)} -attr vt d
+load net {regs.operator[]#6:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#6:mux.itm} 10 {regs.operator[]#6:mux.itm(0)} {regs.operator[]#6:mux.itm(1)} {regs.operator[]#6:mux.itm(2)} {regs.operator[]#6:mux.itm(3)} {regs.operator[]#6:mux.itm(4)} {regs.operator[]#6:mux.itm(5)} {regs.operator[]#6:mux.itm(6)} {regs.operator[]#6:mux.itm(7)} {regs.operator[]#6:mux.itm(8)} {regs.operator[]#6:mux.itm(9)} -attr xrf 39717 -attr oid 204 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm} 10 {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(0)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(1)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(2)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(3)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(4)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(5)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(6)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(7)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(8)} {slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm(9)} -attr xrf 39718 -attr oid 205 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva.dfm:mx0)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva.dfm:mx0)#8.itm} 10 {slc(regs.regs(1).sva.dfm:mx0)#8.itm(0)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(1)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(2)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(3)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(4)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(5)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(6)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(7)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(8)} {slc(regs.regs(1).sva.dfm:mx0)#8.itm(9)} -attr xrf 39719 -attr oid 206 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva.dfm:mx0)#8.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva.dfm:mx0)#8.itm} 10 {slc(regs.regs(0).sva.dfm:mx0)#8.itm(0)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(1)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(2)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(3)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(4)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(5)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(6)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(7)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(8)} {slc(regs.regs(0).sva.dfm:mx0)#8.itm(9)} -attr xrf 39720 -attr oid 207 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {mux#18.itm(0)} -attr vt d
+load net {mux#18.itm(1)} -attr vt d
+load net {mux#18.itm(2)} -attr vt d
+load net {mux#18.itm(3)} -attr vt d
+load net {mux#18.itm(4)} -attr vt d
+load net {mux#18.itm(5)} -attr vt d
+load net {mux#18.itm(6)} -attr vt d
+load net {mux#18.itm(7)} -attr vt d
+load net {mux#18.itm(8)} -attr vt d
+load net {mux#18.itm(9)} -attr vt d
+load net {mux#18.itm(10)} -attr vt d
+load net {mux#18.itm(11)} -attr vt d
+load net {mux#18.itm(12)} -attr vt d
+load net {mux#18.itm(13)} -attr vt d
+load net {mux#18.itm(14)} -attr vt d
+load net {mux#18.itm(15)} -attr vt d
+load net {mux#18.itm(16)} -attr vt d
+load net {mux#18.itm(17)} -attr vt d
+load net {mux#18.itm(18)} -attr vt d
+load netBundle {mux#18.itm} 19 {mux#18.itm(0)} {mux#18.itm(1)} {mux#18.itm(2)} {mux#18.itm(3)} {mux#18.itm(4)} {mux#18.itm(5)} {mux#18.itm(6)} {mux#18.itm(7)} {mux#18.itm(8)} {mux#18.itm(9)} {mux#18.itm(10)} {mux#18.itm(11)} {mux#18.itm(12)} {mux#18.itm(13)} {mux#18.itm(14)} {mux#18.itm(15)} {mux#18.itm(16)} {mux#18.itm(17)} {mux#18.itm(18)} -attr xrf 39721 -attr oid 208 -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {FRAME:acc#22.itm(0)} -attr vt d
+load net {FRAME:acc#22.itm(1)} -attr vt d
+load net {FRAME:acc#22.itm(2)} -attr vt d
+load net {FRAME:acc#22.itm(3)} -attr vt d
+load net {FRAME:acc#22.itm(4)} -attr vt d
+load net {FRAME:acc#22.itm(5)} -attr vt d
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+load netBundle {slc(red#2.sg1.sva)#6.itm} 3 {slc(red#2.sg1.sva)#6.itm(0)} {slc(red#2.sg1.sva)#6.itm(1)} {slc(red#2.sg1.sva)#6.itm(2)} -attr xrf 39749 -attr oid 236 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {FRAME:not#1.itm(0)} -attr vt d
+load net {FRAME:not#1.itm(1)} -attr vt d
+load net {FRAME:not#1.itm(2)} -attr vt d
+load netBundle {FRAME:not#1.itm} 3 {FRAME:not#1.itm(0)} {FRAME:not#1.itm(1)} {FRAME:not#1.itm(2)} -attr xrf 39750 -attr oid 237 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {slc(red#2.sg1.sva)#7.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#7.itm(1)} -attr vt d
+load net {slc(red#2.sg1.sva)#7.itm(2)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#7.itm} 3 {slc(red#2.sg1.sva)#7.itm(0)} {slc(red#2.sg1.sva)#7.itm(1)} {slc(red#2.sg1.sva)#7.itm(2)} -attr xrf 39751 -attr oid 238 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {ACC2-3:acc#1.itm(0)} -attr vt d
+load net {ACC2-3:acc#1.itm(1)} -attr vt d
+load net {ACC2-3:acc#1.itm(2)} -attr vt d
+load net {ACC2-3:acc#1.itm(3)} -attr vt d
+load net {ACC2-3:acc#1.itm(4)} -attr vt d
+load net {ACC2-3:acc#1.itm(5)} -attr vt d
+load net {ACC2-3:acc#1.itm(6)} -attr vt d
+load net {ACC2-3:acc#1.itm(7)} -attr vt d
+load net {ACC2-3:acc#1.itm(8)} -attr vt d
+load net {ACC2-3:acc#1.itm(9)} -attr vt d
+load net {ACC2-3:acc#1.itm(10)} -attr vt d
+load net {ACC2-3:acc#1.itm(11)} -attr vt d
+load net {ACC2-3:acc#1.itm(12)} -attr vt d
+load net {ACC2-3:acc#1.itm(13)} -attr vt d
+load net {ACC2-3:acc#1.itm(14)} -attr vt d
+load net {ACC2-3:acc#1.itm(15)} -attr vt d
+load netBundle {ACC2-3:acc#1.itm} 16 {ACC2-3:acc#1.itm(0)} {ACC2-3:acc#1.itm(1)} {ACC2-3:acc#1.itm(2)} {ACC2-3:acc#1.itm(3)} {ACC2-3:acc#1.itm(4)} {ACC2-3:acc#1.itm(5)} {ACC2-3:acc#1.itm(6)} {ACC2-3:acc#1.itm(7)} {ACC2-3:acc#1.itm(8)} {ACC2-3:acc#1.itm(9)} {ACC2-3:acc#1.itm(10)} {ACC2-3:acc#1.itm(11)} {ACC2-3:acc#1.itm(12)} {ACC2-3:acc#1.itm(13)} {ACC2-3:acc#1.itm(14)} {ACC2-3:acc#1.itm(15)} -attr xrf 39752 -attr oid 239 -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2:conc.itm(0)} -attr vt d
+load net {ACC2:conc.itm(1)} -attr vt d
+load net {ACC2:conc.itm(2)} -attr vt d
+load net {ACC2:conc.itm(3)} -attr vt d
+load net {ACC2:conc.itm(4)} -attr vt d
+load net {ACC2:conc.itm(5)} -attr vt d
+load net {ACC2:conc.itm(6)} -attr vt d
+load net {ACC2:conc.itm(7)} -attr vt d
+load net {ACC2:conc.itm(8)} -attr vt d
+load net {ACC2:conc.itm(9)} -attr vt d
+load net {ACC2:conc.itm(10)} -attr vt d
+load net {ACC2:conc.itm(11)} -attr vt d
+load net {ACC2:conc.itm(12)} -attr vt d
+load net {ACC2:conc.itm(13)} -attr vt d
+load net {ACC2:conc.itm(14)} -attr vt d
+load net {ACC2:conc.itm(15)} -attr vt d
+load netBundle {ACC2:conc.itm} 16 {ACC2:conc.itm(0)} {ACC2:conc.itm(1)} {ACC2:conc.itm(2)} {ACC2:conc.itm(3)} {ACC2:conc.itm(4)} {ACC2:conc.itm(5)} {ACC2:conc.itm(6)} {ACC2:conc.itm(7)} {ACC2:conc.itm(8)} {ACC2:conc.itm(9)} {ACC2:conc.itm(10)} {ACC2:conc.itm(11)} {ACC2:conc.itm(12)} {ACC2:conc.itm(13)} {ACC2:conc.itm(14)} {ACC2:conc.itm(15)} -attr xrf 39753 -attr oid 240 -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(0)} -attr vt d
+load net {ACC2:acc.itm(1)} -attr vt d
+load net {ACC2:acc.itm(2)} -attr vt d
+load net {ACC2:acc.itm(3)} -attr vt d
+load net {ACC2:acc.itm(4)} -attr vt d
+load net {ACC2:acc.itm(5)} -attr vt d
+load net {ACC2:acc.itm(6)} -attr vt d
+load net {ACC2:acc.itm(7)} -attr vt d
+load net {ACC2:acc.itm(8)} -attr vt d
+load net {ACC2:acc.itm(9)} -attr vt d
+load net {ACC2:acc.itm(10)} -attr vt d
+load net {ACC2:acc.itm(11)} -attr vt d
+load net {ACC2:acc.itm(12)} -attr vt d
+load net {ACC2:acc.itm(13)} -attr vt d
+load net {ACC2:acc.itm(14)} -attr vt d
+load netBundle {ACC2:acc.itm} 15 {ACC2:acc.itm(0)} {ACC2:acc.itm(1)} {ACC2:acc.itm(2)} {ACC2:acc.itm(3)} {ACC2:acc.itm(4)} {ACC2:acc.itm(5)} {ACC2:acc.itm(6)} {ACC2:acc.itm(7)} {ACC2:acc.itm(8)} {ACC2:acc.itm(9)} {ACC2:acc.itm(10)} {ACC2:acc.itm(11)} {ACC2:acc.itm(12)} {ACC2:acc.itm(13)} {ACC2:acc.itm(14)} -attr xrf 39754 -attr oid 241 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {slc(r(2).sva#1).itm(0)} -attr vt d
+load net {slc(r(2).sva#1).itm(1)} -attr vt d
+load net {slc(r(2).sva#1).itm(2)} -attr vt d
+load net {slc(r(2).sva#1).itm(3)} -attr vt d
+load net {slc(r(2).sva#1).itm(4)} -attr vt d
+load net {slc(r(2).sva#1).itm(5)} -attr vt d
+load net {slc(r(2).sva#1).itm(6)} -attr vt d
+load net {slc(r(2).sva#1).itm(7)} -attr vt d
+load net {slc(r(2).sva#1).itm(8)} -attr vt d
+load net {slc(r(2).sva#1).itm(9)} -attr vt d
+load net {slc(r(2).sva#1).itm(10)} -attr vt d
+load net {slc(r(2).sva#1).itm(11)} -attr vt d
+load net {slc(r(2).sva#1).itm(12)} -attr vt d
+load net {slc(r(2).sva#1).itm(13)} -attr vt d
+load net {slc(r(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(r(2).sva#1).itm} 15 {slc(r(2).sva#1).itm(0)} {slc(r(2).sva#1).itm(1)} {slc(r(2).sva#1).itm(2)} {slc(r(2).sva#1).itm(3)} {slc(r(2).sva#1).itm(4)} {slc(r(2).sva#1).itm(5)} {slc(r(2).sva#1).itm(6)} {slc(r(2).sva#1).itm(7)} {slc(r(2).sva#1).itm(8)} {slc(r(2).sva#1).itm(9)} {slc(r(2).sva#1).itm(10)} {slc(r(2).sva#1).itm(11)} {slc(r(2).sva#1).itm(12)} {slc(r(2).sva#1).itm(13)} {slc(r(2).sva#1).itm(14)} -attr xrf 39755 -attr oid 242 -attr vt d -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {slc(red#2.sg1.sva)#12.itm(0)} -attr vt d
+load net {slc(red#2.sg1.sva)#12.itm(1)} -attr vt d
+load netBundle {slc(red#2.sg1.sva)#12.itm} 2 {slc(red#2.sg1.sva)#12.itm(0)} {slc(red#2.sg1.sva)#12.itm(1)} -attr xrf 39756 -attr oid 243 -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#12.itm}
+load net {ACC2-3:acc#3.itm(0)} -attr vt d
+load net {ACC2-3:acc#3.itm(1)} -attr vt d
+load net {ACC2-3:acc#3.itm(2)} -attr vt d
+load net {ACC2-3:acc#3.itm(3)} -attr vt d
+load net {ACC2-3:acc#3.itm(4)} -attr vt d
+load net {ACC2-3:acc#3.itm(5)} -attr vt d
+load net {ACC2-3:acc#3.itm(6)} -attr vt d
+load net {ACC2-3:acc#3.itm(7)} -attr vt d
+load net {ACC2-3:acc#3.itm(8)} -attr vt d
+load net {ACC2-3:acc#3.itm(9)} -attr vt d
+load net {ACC2-3:acc#3.itm(10)} -attr vt d
+load net {ACC2-3:acc#3.itm(11)} -attr vt d
+load net {ACC2-3:acc#3.itm(12)} -attr vt d
+load net {ACC2-3:acc#3.itm(13)} -attr vt d
+load net {ACC2-3:acc#3.itm(14)} -attr vt d
+load net {ACC2-3:acc#3.itm(15)} -attr vt d
+load netBundle {ACC2-3:acc#3.itm} 16 {ACC2-3:acc#3.itm(0)} {ACC2-3:acc#3.itm(1)} {ACC2-3:acc#3.itm(2)} {ACC2-3:acc#3.itm(3)} {ACC2-3:acc#3.itm(4)} {ACC2-3:acc#3.itm(5)} {ACC2-3:acc#3.itm(6)} {ACC2-3:acc#3.itm(7)} {ACC2-3:acc#3.itm(8)} {ACC2-3:acc#3.itm(9)} {ACC2-3:acc#3.itm(10)} {ACC2-3:acc#3.itm(11)} {ACC2-3:acc#3.itm(12)} {ACC2-3:acc#3.itm(13)} {ACC2-3:acc#3.itm(14)} {ACC2-3:acc#3.itm(15)} -attr xrf 39757 -attr oid 244 -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2:conc#2.itm(0)} -attr vt d
+load net {ACC2:conc#2.itm(1)} -attr vt d
+load net {ACC2:conc#2.itm(2)} -attr vt d
+load net {ACC2:conc#2.itm(3)} -attr vt d
+load net {ACC2:conc#2.itm(4)} -attr vt d
+load net {ACC2:conc#2.itm(5)} -attr vt d
+load net {ACC2:conc#2.itm(6)} -attr vt d
+load net {ACC2:conc#2.itm(7)} -attr vt d
+load net {ACC2:conc#2.itm(8)} -attr vt d
+load net {ACC2:conc#2.itm(9)} -attr vt d
+load net {ACC2:conc#2.itm(10)} -attr vt d
+load net {ACC2:conc#2.itm(11)} -attr vt d
+load net {ACC2:conc#2.itm(12)} -attr vt d
+load net {ACC2:conc#2.itm(13)} -attr vt d
+load net {ACC2:conc#2.itm(14)} -attr vt d
+load net {ACC2:conc#2.itm(15)} -attr vt d
+load netBundle {ACC2:conc#2.itm} 16 {ACC2:conc#2.itm(0)} {ACC2:conc#2.itm(1)} {ACC2:conc#2.itm(2)} {ACC2:conc#2.itm(3)} {ACC2:conc#2.itm(4)} {ACC2:conc#2.itm(5)} {ACC2:conc#2.itm(6)} {ACC2:conc#2.itm(7)} {ACC2:conc#2.itm(8)} {ACC2:conc#2.itm(9)} {ACC2:conc#2.itm(10)} {ACC2:conc#2.itm(11)} {ACC2:conc#2.itm(12)} {ACC2:conc#2.itm(13)} {ACC2:conc#2.itm(14)} {ACC2:conc#2.itm(15)} -attr xrf 39758 -attr oid 245 -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(0)} -attr vt d
+load net {ACC2:acc#8.itm(1)} -attr vt d
+load net {ACC2:acc#8.itm(2)} -attr vt d
+load net {ACC2:acc#8.itm(3)} -attr vt d
+load net {ACC2:acc#8.itm(4)} -attr vt d
+load net {ACC2:acc#8.itm(5)} -attr vt d
+load net {ACC2:acc#8.itm(6)} -attr vt d
+load net {ACC2:acc#8.itm(7)} -attr vt d
+load net {ACC2:acc#8.itm(8)} -attr vt d
+load net {ACC2:acc#8.itm(9)} -attr vt d
+load net {ACC2:acc#8.itm(10)} -attr vt d
+load net {ACC2:acc#8.itm(11)} -attr vt d
+load net {ACC2:acc#8.itm(12)} -attr vt d
+load net {ACC2:acc#8.itm(13)} -attr vt d
+load net {ACC2:acc#8.itm(14)} -attr vt d
+load netBundle {ACC2:acc#8.itm} 15 {ACC2:acc#8.itm(0)} {ACC2:acc#8.itm(1)} {ACC2:acc#8.itm(2)} {ACC2:acc#8.itm(3)} {ACC2:acc#8.itm(4)} {ACC2:acc#8.itm(5)} {ACC2:acc#8.itm(6)} {ACC2:acc#8.itm(7)} {ACC2:acc#8.itm(8)} {ACC2:acc#8.itm(9)} {ACC2:acc#8.itm(10)} {ACC2:acc#8.itm(11)} {ACC2:acc#8.itm(12)} {ACC2:acc#8.itm(13)} {ACC2:acc#8.itm(14)} -attr xrf 39759 -attr oid 246 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {slc(b(2).sva#1).itm(0)} -attr vt d
+load net {slc(b(2).sva#1).itm(1)} -attr vt d
+load net {slc(b(2).sva#1).itm(2)} -attr vt d
+load net {slc(b(2).sva#1).itm(3)} -attr vt d
+load net {slc(b(2).sva#1).itm(4)} -attr vt d
+load net {slc(b(2).sva#1).itm(5)} -attr vt d
+load net {slc(b(2).sva#1).itm(6)} -attr vt d
+load net {slc(b(2).sva#1).itm(7)} -attr vt d
+load net {slc(b(2).sva#1).itm(8)} -attr vt d
+load net {slc(b(2).sva#1).itm(9)} -attr vt d
+load net {slc(b(2).sva#1).itm(10)} -attr vt d
+load net {slc(b(2).sva#1).itm(11)} -attr vt d
+load net {slc(b(2).sva#1).itm(12)} -attr vt d
+load net {slc(b(2).sva#1).itm(13)} -attr vt d
+load net {slc(b(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(b(2).sva#1).itm} 15 {slc(b(2).sva#1).itm(0)} {slc(b(2).sva#1).itm(1)} {slc(b(2).sva#1).itm(2)} {slc(b(2).sva#1).itm(3)} {slc(b(2).sva#1).itm(4)} {slc(b(2).sva#1).itm(5)} {slc(b(2).sva#1).itm(6)} {slc(b(2).sva#1).itm(7)} {slc(b(2).sva#1).itm(8)} {slc(b(2).sva#1).itm(9)} {slc(b(2).sva#1).itm(10)} {slc(b(2).sva#1).itm(11)} {slc(b(2).sva#1).itm(12)} {slc(b(2).sva#1).itm(13)} {slc(b(2).sva#1).itm(14)} -attr xrf 39760 -attr oid 247 -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {FRAME:acc#28.itm(0)} -attr vt d
+load net {FRAME:acc#28.itm(1)} -attr vt d
+load net {FRAME:acc#28.itm(2)} -attr vt d
+load net {FRAME:acc#28.itm(3)} -attr vt d
+load net {FRAME:acc#28.itm(4)} -attr vt d
+load net {FRAME:acc#28.itm(5)} -attr vt d
+load netBundle {FRAME:acc#28.itm} 6 {FRAME:acc#28.itm(0)} {FRAME:acc#28.itm(1)} {FRAME:acc#28.itm(2)} {FRAME:acc#28.itm(3)} {FRAME:acc#28.itm(4)} {FRAME:acc#28.itm(5)} -attr xrf 39761 -attr oid 248 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#27.itm(0)} -attr vt d
+load net {FRAME:acc#27.itm(1)} -attr vt d
+load net {FRAME:acc#27.itm(2)} -attr vt d
+load net {FRAME:acc#27.itm(3)} -attr vt d
+load net {FRAME:acc#27.itm(4)} -attr vt d
+load netBundle {FRAME:acc#27.itm} 5 {FRAME:acc#27.itm(0)} {FRAME:acc#27.itm(1)} {FRAME:acc#27.itm(2)} {FRAME:acc#27.itm(3)} {FRAME:acc#27.itm(4)} -attr xrf 39762 -attr oid 249 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#25.itm(0)} -attr vt d
+load net {FRAME:acc#25.itm(1)} -attr vt d
+load net {FRAME:acc#25.itm(2)} -attr vt d
+load net {FRAME:acc#25.itm(3)} -attr vt d
+load netBundle {FRAME:acc#25.itm} 4 {FRAME:acc#25.itm(0)} {FRAME:acc#25.itm(1)} {FRAME:acc#25.itm(2)} {FRAME:acc#25.itm(3)} -attr xrf 39763 -attr oid 250 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {slc(blue#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#1.itm} 3 {slc(blue#2.sg1.sva)#1.itm(0)} {slc(blue#2.sg1.sva)#1.itm(1)} {slc(blue#2.sg1.sva)#1.itm(2)} -attr xrf 39764 -attr oid 251 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {FRAME:not#18.itm(0)} -attr vt d
+load net {FRAME:not#18.itm(1)} -attr vt d
+load net {FRAME:not#18.itm(2)} -attr vt d
+load netBundle {FRAME:not#18.itm} 3 {FRAME:not#18.itm(0)} {FRAME:not#18.itm(1)} {FRAME:not#18.itm(2)} -attr xrf 39765 -attr oid 252 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {slc(blue#2.sg1.sva)#3.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#3.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#3.itm} 3 {slc(blue#2.sg1.sva)#3.itm(0)} {slc(blue#2.sg1.sva)#3.itm(1)} {slc(blue#2.sg1.sva)#3.itm(2)} -attr xrf 39766 -attr oid 253 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {FRAME:acc#24.itm(0)} -attr vt d
+load net {FRAME:acc#24.itm(1)} -attr vt d
+load net {FRAME:acc#24.itm(2)} -attr vt d
+load net {FRAME:acc#24.itm(3)} -attr vt d
+load netBundle {FRAME:acc#24.itm} 4 {FRAME:acc#24.itm(0)} {FRAME:acc#24.itm(1)} {FRAME:acc#24.itm(2)} {FRAME:acc#24.itm(3)} -attr xrf 39767 -attr oid 254 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {conc#154.itm(0)} -attr vt d
+load net {conc#154.itm(1)} -attr vt d
+load net {conc#154.itm(2)} -attr vt d
+load netBundle {conc#154.itm} 3 {conc#154.itm(0)} {conc#154.itm(1)} {conc#154.itm(2)} -attr xrf 39768 -attr oid 255 -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {slc(blue#2.sg1.sva)#4.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#4.itm} 2 {slc(blue#2.sg1.sva)#4.itm(0)} {slc(blue#2.sg1.sva)#4.itm(1)} -attr xrf 39769 -attr oid 256 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#4.itm}
+load net {FRAME:acc#26.itm(0)} -attr vt d
+load net {FRAME:acc#26.itm(1)} -attr vt d
+load net {FRAME:acc#26.itm(2)} -attr vt d
+load net {FRAME:acc#26.itm(3)} -attr vt d
+load netBundle {FRAME:acc#26.itm} 4 {FRAME:acc#26.itm(0)} {FRAME:acc#26.itm(1)} {FRAME:acc#26.itm(2)} {FRAME:acc#26.itm(3)} -attr xrf 39770 -attr oid 257 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {slc(blue#2.sg1.sva)#5.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#5.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#5.itm} 3 {slc(blue#2.sg1.sva)#5.itm(0)} {slc(blue#2.sg1.sva)#5.itm(1)} {slc(blue#2.sg1.sva)#5.itm(2)} -attr xrf 39771 -attr oid 258 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {FRAME:not#17.itm(0)} -attr vt d
+load net {FRAME:not#17.itm(1)} -attr vt d
+load net {FRAME:not#17.itm(2)} -attr vt d
+load netBundle {FRAME:not#17.itm} 3 {FRAME:not#17.itm(0)} {FRAME:not#17.itm(1)} {FRAME:not#17.itm(2)} -attr xrf 39772 -attr oid 259 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {slc(blue#2.sg1.sva)#6.itm(0)} -attr vt d
+load net {slc(blue#2.sg1.sva)#6.itm(1)} -attr vt d
+load net {slc(blue#2.sg1.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(blue#2.sg1.sva)#6.itm} 3 {slc(blue#2.sg1.sva)#6.itm(0)} {slc(blue#2.sg1.sva)#6.itm(1)} {slc(blue#2.sg1.sva)#6.itm(2)} -attr xrf 39773 -attr oid 260 -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#2.itm(0)} -attr vt d
+load net {ACC2-3:acc#2.itm(1)} -attr vt d
+load net {ACC2-3:acc#2.itm(2)} -attr vt d
+load net {ACC2-3:acc#2.itm(3)} -attr vt d
+load net {ACC2-3:acc#2.itm(4)} -attr vt d
+load net {ACC2-3:acc#2.itm(5)} -attr vt d
+load net {ACC2-3:acc#2.itm(6)} -attr vt d
+load net {ACC2-3:acc#2.itm(7)} -attr vt d
+load net {ACC2-3:acc#2.itm(8)} -attr vt d
+load net {ACC2-3:acc#2.itm(9)} -attr vt d
+load net {ACC2-3:acc#2.itm(10)} -attr vt d
+load net {ACC2-3:acc#2.itm(11)} -attr vt d
+load net {ACC2-3:acc#2.itm(12)} -attr vt d
+load net {ACC2-3:acc#2.itm(13)} -attr vt d
+load net {ACC2-3:acc#2.itm(14)} -attr vt d
+load net {ACC2-3:acc#2.itm(15)} -attr vt d
+load netBundle {ACC2-3:acc#2.itm} 16 {ACC2-3:acc#2.itm(0)} {ACC2-3:acc#2.itm(1)} {ACC2-3:acc#2.itm(2)} {ACC2-3:acc#2.itm(3)} {ACC2-3:acc#2.itm(4)} {ACC2-3:acc#2.itm(5)} {ACC2-3:acc#2.itm(6)} {ACC2-3:acc#2.itm(7)} {ACC2-3:acc#2.itm(8)} {ACC2-3:acc#2.itm(9)} {ACC2-3:acc#2.itm(10)} {ACC2-3:acc#2.itm(11)} {ACC2-3:acc#2.itm(12)} {ACC2-3:acc#2.itm(13)} {ACC2-3:acc#2.itm(14)} {ACC2-3:acc#2.itm(15)} -attr xrf 39774 -attr oid 261 -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2:conc#1.itm(0)} -attr vt d
+load net {ACC2:conc#1.itm(1)} -attr vt d
+load net {ACC2:conc#1.itm(2)} -attr vt d
+load net {ACC2:conc#1.itm(3)} -attr vt d
+load net {ACC2:conc#1.itm(4)} -attr vt d
+load net {ACC2:conc#1.itm(5)} -attr vt d
+load net {ACC2:conc#1.itm(6)} -attr vt d
+load net {ACC2:conc#1.itm(7)} -attr vt d
+load net {ACC2:conc#1.itm(8)} -attr vt d
+load net {ACC2:conc#1.itm(9)} -attr vt d
+load net {ACC2:conc#1.itm(10)} -attr vt d
+load net {ACC2:conc#1.itm(11)} -attr vt d
+load net {ACC2:conc#1.itm(12)} -attr vt d
+load net {ACC2:conc#1.itm(13)} -attr vt d
+load net {ACC2:conc#1.itm(14)} -attr vt d
+load net {ACC2:conc#1.itm(15)} -attr vt d
+load netBundle {ACC2:conc#1.itm} 16 {ACC2:conc#1.itm(0)} {ACC2:conc#1.itm(1)} {ACC2:conc#1.itm(2)} {ACC2:conc#1.itm(3)} {ACC2:conc#1.itm(4)} {ACC2:conc#1.itm(5)} {ACC2:conc#1.itm(6)} {ACC2:conc#1.itm(7)} {ACC2:conc#1.itm(8)} {ACC2:conc#1.itm(9)} {ACC2:conc#1.itm(10)} {ACC2:conc#1.itm(11)} {ACC2:conc#1.itm(12)} {ACC2:conc#1.itm(13)} {ACC2:conc#1.itm(14)} {ACC2:conc#1.itm(15)} -attr xrf 39775 -attr oid 262 -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(0)} -attr vt d
+load net {ACC2:acc#7.itm(1)} -attr vt d
+load net {ACC2:acc#7.itm(2)} -attr vt d
+load net {ACC2:acc#7.itm(3)} -attr vt d
+load net {ACC2:acc#7.itm(4)} -attr vt d
+load net {ACC2:acc#7.itm(5)} -attr vt d
+load net {ACC2:acc#7.itm(6)} -attr vt d
+load net {ACC2:acc#7.itm(7)} -attr vt d
+load net {ACC2:acc#7.itm(8)} -attr vt d
+load net {ACC2:acc#7.itm(9)} -attr vt d
+load net {ACC2:acc#7.itm(10)} -attr vt d
+load net {ACC2:acc#7.itm(11)} -attr vt d
+load net {ACC2:acc#7.itm(12)} -attr vt d
+load net {ACC2:acc#7.itm(13)} -attr vt d
+load net {ACC2:acc#7.itm(14)} -attr vt d
+load netBundle {ACC2:acc#7.itm} 15 {ACC2:acc#7.itm(0)} {ACC2:acc#7.itm(1)} {ACC2:acc#7.itm(2)} {ACC2:acc#7.itm(3)} {ACC2:acc#7.itm(4)} {ACC2:acc#7.itm(5)} {ACC2:acc#7.itm(6)} {ACC2:acc#7.itm(7)} {ACC2:acc#7.itm(8)} {ACC2:acc#7.itm(9)} {ACC2:acc#7.itm(10)} {ACC2:acc#7.itm(11)} {ACC2:acc#7.itm(12)} {ACC2:acc#7.itm(13)} {ACC2:acc#7.itm(14)} -attr xrf 39776 -attr oid 263 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {slc(g(2).sva#1).itm(0)} -attr vt d
+load net {slc(g(2).sva#1).itm(1)} -attr vt d
+load net {slc(g(2).sva#1).itm(2)} -attr vt d
+load net {slc(g(2).sva#1).itm(3)} -attr vt d
+load net {slc(g(2).sva#1).itm(4)} -attr vt d
+load net {slc(g(2).sva#1).itm(5)} -attr vt d
+load net {slc(g(2).sva#1).itm(6)} -attr vt d
+load net {slc(g(2).sva#1).itm(7)} -attr vt d
+load net {slc(g(2).sva#1).itm(8)} -attr vt d
+load net {slc(g(2).sva#1).itm(9)} -attr vt d
+load net {slc(g(2).sva#1).itm(10)} -attr vt d
+load net {slc(g(2).sva#1).itm(11)} -attr vt d
+load net {slc(g(2).sva#1).itm(12)} -attr vt d
+load net {slc(g(2).sva#1).itm(13)} -attr vt d
+load net {slc(g(2).sva#1).itm(14)} -attr vt d
+load netBundle {slc(g(2).sva#1).itm} 15 {slc(g(2).sva#1).itm(0)} {slc(g(2).sva#1).itm(1)} {slc(g(2).sva#1).itm(2)} {slc(g(2).sva#1).itm(3)} {slc(g(2).sva#1).itm(4)} {slc(g(2).sva#1).itm(5)} {slc(g(2).sva#1).itm(6)} {slc(g(2).sva#1).itm(7)} {slc(g(2).sva#1).itm(8)} {slc(g(2).sva#1).itm(9)} {slc(g(2).sva#1).itm(10)} {slc(g(2).sva#1).itm(11)} {slc(g(2).sva#1).itm(12)} {slc(g(2).sva#1).itm(13)} {slc(g(2).sva#1).itm(14)} -attr xrf 39777 -attr oid 264 -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {FRAME:acc#16.itm(0)} -attr vt d
+load net {FRAME:acc#16.itm(1)} -attr vt d
+load net {FRAME:acc#16.itm(2)} -attr vt d
+load net {FRAME:acc#16.itm(3)} -attr vt d
+load net {FRAME:acc#16.itm(4)} -attr vt d
+load net {FRAME:acc#16.itm(5)} -attr vt d
+load netBundle {FRAME:acc#16.itm} 6 {FRAME:acc#16.itm(0)} {FRAME:acc#16.itm(1)} {FRAME:acc#16.itm(2)} {FRAME:acc#16.itm(3)} {FRAME:acc#16.itm(4)} {FRAME:acc#16.itm(5)} -attr xrf 39778 -attr oid 265 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#15.itm(0)} -attr vt d
+load net {FRAME:acc#15.itm(1)} -attr vt d
+load net {FRAME:acc#15.itm(2)} -attr vt d
+load net {FRAME:acc#15.itm(3)} -attr vt d
+load net {FRAME:acc#15.itm(4)} -attr vt d
+load netBundle {FRAME:acc#15.itm} 5 {FRAME:acc#15.itm(0)} {FRAME:acc#15.itm(1)} {FRAME:acc#15.itm(2)} {FRAME:acc#15.itm(3)} {FRAME:acc#15.itm(4)} -attr xrf 39779 -attr oid 266 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#13.itm(0)} -attr vt d
+load net {FRAME:acc#13.itm(1)} -attr vt d
+load net {FRAME:acc#13.itm(2)} -attr vt d
+load net {FRAME:acc#13.itm(3)} -attr vt d
+load netBundle {FRAME:acc#13.itm} 4 {FRAME:acc#13.itm(0)} {FRAME:acc#13.itm(1)} {FRAME:acc#13.itm(2)} {FRAME:acc#13.itm(3)} -attr xrf 39780 -attr oid 267 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {slc(green#2.sg1.sva)#1.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#1.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#1.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#1.itm} 3 {slc(green#2.sg1.sva)#1.itm(0)} {slc(green#2.sg1.sva)#1.itm(1)} {slc(green#2.sg1.sva)#1.itm(2)} -attr xrf 39781 -attr oid 268 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {FRAME:not#10.itm(0)} -attr vt d
+load net {FRAME:not#10.itm(1)} -attr vt d
+load net {FRAME:not#10.itm(2)} -attr vt d
+load netBundle {FRAME:not#10.itm} 3 {FRAME:not#10.itm(0)} {FRAME:not#10.itm(1)} {FRAME:not#10.itm(2)} -attr xrf 39782 -attr oid 269 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {slc(green#2.sg1.sva)#3.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#3.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#3.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#3.itm} 3 {slc(green#2.sg1.sva)#3.itm(0)} {slc(green#2.sg1.sva)#3.itm(1)} {slc(green#2.sg1.sva)#3.itm(2)} -attr xrf 39783 -attr oid 270 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {FRAME:acc#12.itm(0)} -attr vt d
+load net {FRAME:acc#12.itm(1)} -attr vt d
+load net {FRAME:acc#12.itm(2)} -attr vt d
+load net {FRAME:acc#12.itm(3)} -attr vt d
+load netBundle {FRAME:acc#12.itm} 4 {FRAME:acc#12.itm(0)} {FRAME:acc#12.itm(1)} {FRAME:acc#12.itm(2)} {FRAME:acc#12.itm(3)} -attr xrf 39784 -attr oid 271 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {conc#155.itm(0)} -attr vt d
+load net {conc#155.itm(1)} -attr vt d
+load net {conc#155.itm(2)} -attr vt d
+load netBundle {conc#155.itm} 3 {conc#155.itm(0)} {conc#155.itm(1)} {conc#155.itm(2)} -attr xrf 39785 -attr oid 272 -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {slc(green#2.sg1.sva)#4.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#4.itm(1)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#4.itm} 2 {slc(green#2.sg1.sva)#4.itm(0)} {slc(green#2.sg1.sva)#4.itm(1)} -attr xrf 39786 -attr oid 273 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#4.itm}
+load net {FRAME:acc#14.itm(0)} -attr vt d
+load net {FRAME:acc#14.itm(1)} -attr vt d
+load net {FRAME:acc#14.itm(2)} -attr vt d
+load net {FRAME:acc#14.itm(3)} -attr vt d
+load netBundle {FRAME:acc#14.itm} 4 {FRAME:acc#14.itm(0)} {FRAME:acc#14.itm(1)} {FRAME:acc#14.itm(2)} {FRAME:acc#14.itm(3)} -attr xrf 39787 -attr oid 274 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {slc(green#2.sg1.sva)#5.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#5.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#5.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#5.itm} 3 {slc(green#2.sg1.sva)#5.itm(0)} {slc(green#2.sg1.sva)#5.itm(1)} {slc(green#2.sg1.sva)#5.itm(2)} -attr xrf 39788 -attr oid 275 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {FRAME:not#9.itm(0)} -attr vt d
+load net {FRAME:not#9.itm(1)} -attr vt d
+load net {FRAME:not#9.itm(2)} -attr vt d
+load netBundle {FRAME:not#9.itm} 3 {FRAME:not#9.itm(0)} {FRAME:not#9.itm(1)} {FRAME:not#9.itm(2)} -attr xrf 39789 -attr oid 276 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {slc(green#2.sg1.sva)#6.itm(0)} -attr vt d
+load net {slc(green#2.sg1.sva)#6.itm(1)} -attr vt d
+load net {slc(green#2.sg1.sva)#6.itm(2)} -attr vt d
+load netBundle {slc(green#2.sg1.sva)#6.itm} 3 {slc(green#2.sg1.sva)#6.itm(0)} {slc(green#2.sg1.sva)#6.itm(1)} {slc(green#2.sg1.sva)#6.itm(2)} -attr xrf 39790 -attr oid 277 -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {FRAME:for:exs#35.itm(0)} -attr vt d
+load net {FRAME:for:exs#35.itm(1)} -attr vt d
+load net {FRAME:for:exs#35.itm(2)} -attr vt d
+load net {FRAME:for:exs#35.itm(3)} -attr vt d
+load net {FRAME:for:exs#35.itm(4)} -attr vt d
+load net {FRAME:for:exs#35.itm(5)} -attr vt d
+load net {FRAME:for:exs#35.itm(6)} -attr vt d
+load net {FRAME:for:exs#35.itm(7)} -attr vt d
+load net {FRAME:for:exs#35.itm(8)} -attr vt d
+load net {FRAME:for:exs#35.itm(9)} -attr vt d
+load net {FRAME:for:exs#35.itm(10)} -attr vt d
+load net {FRAME:for:exs#35.itm(11)} -attr vt d
+load net {FRAME:for:exs#35.itm(12)} -attr vt d
+load net {FRAME:for:exs#35.itm(13)} -attr vt d
+load net {FRAME:for:exs#35.itm(14)} -attr vt d
+load netBundle {FRAME:for:exs#35.itm} 15 {FRAME:for:exs#35.itm(0)} {FRAME:for:exs#35.itm(1)} {FRAME:for:exs#35.itm(2)} {FRAME:for:exs#35.itm(3)} {FRAME:for:exs#35.itm(4)} {FRAME:for:exs#35.itm(5)} {FRAME:for:exs#35.itm(6)} {FRAME:for:exs#35.itm(7)} {FRAME:for:exs#35.itm(8)} {FRAME:for:exs#35.itm(9)} {FRAME:for:exs#35.itm(10)} {FRAME:for:exs#35.itm(11)} {FRAME:for:exs#35.itm(12)} {FRAME:for:exs#35.itm(13)} {FRAME:for:exs#35.itm(14)} -attr xrf 39791 -attr oid 278 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {FRAME:for#1:mul#8.itm(0)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(1)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(2)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(3)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(4)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(5)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(6)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(7)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(8)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(9)} -attr vt d
+load net {FRAME:for#1:mul#8.itm(10)} -attr vt d
+load netBundle {FRAME:for#1:mul#8.itm} 11 {FRAME:for#1:mul#8.itm(0)} {FRAME:for#1:mul#8.itm(1)} {FRAME:for#1:mul#8.itm(2)} {FRAME:for#1:mul#8.itm(3)} {FRAME:for#1:mul#8.itm(4)} {FRAME:for#1:mul#8.itm(5)} {FRAME:for#1:mul#8.itm(6)} {FRAME:for#1:mul#8.itm(7)} {FRAME:for#1:mul#8.itm(8)} {FRAME:for#1:mul#8.itm(9)} {FRAME:for#1:mul#8.itm(10)} -attr xrf 39792 -attr oid 279 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {regs.operator[]#23:mux.itm(0)} -attr vt d
+load net {regs.operator[]#23:mux.itm(1)} -attr vt d
+load net {regs.operator[]#23:mux.itm(2)} -attr vt d
+load net {regs.operator[]#23:mux.itm(3)} -attr vt d
+load net {regs.operator[]#23:mux.itm(4)} -attr vt d
+load net {regs.operator[]#23:mux.itm(5)} -attr vt d
+load net {regs.operator[]#23:mux.itm(6)} -attr vt d
+load net {regs.operator[]#23:mux.itm(7)} -attr vt d
+load net {regs.operator[]#23:mux.itm(8)} -attr vt d
+load net {regs.operator[]#23:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#23:mux.itm} 10 {regs.operator[]#23:mux.itm(0)} {regs.operator[]#23:mux.itm(1)} {regs.operator[]#23:mux.itm(2)} {regs.operator[]#23:mux.itm(3)} {regs.operator[]#23:mux.itm(4)} {regs.operator[]#23:mux.itm(5)} {regs.operator[]#23:mux.itm(6)} {regs.operator[]#23:mux.itm(7)} {regs.operator[]#23:mux.itm(8)} {regs.operator[]#23:mux.itm(9)} -attr xrf 39793 -attr oid 280 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm).itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm).itm} 10 {slc(regs.regs(2).lpi#1.dfm).itm(0)} {slc(regs.regs(2).lpi#1.dfm).itm(1)} {slc(regs.regs(2).lpi#1.dfm).itm(2)} {slc(regs.regs(2).lpi#1.dfm).itm(3)} {slc(regs.regs(2).lpi#1.dfm).itm(4)} {slc(regs.regs(2).lpi#1.dfm).itm(5)} {slc(regs.regs(2).lpi#1.dfm).itm(6)} {slc(regs.regs(2).lpi#1.dfm).itm(7)} {slc(regs.regs(2).lpi#1.dfm).itm(8)} {slc(regs.regs(2).lpi#1.dfm).itm(9)} -attr xrf 39794 -attr oid 281 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {slc(regs.regs(1).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva).itm} 10 {slc(regs.regs(1).sva).itm(0)} {slc(regs.regs(1).sva).itm(1)} {slc(regs.regs(1).sva).itm(2)} {slc(regs.regs(1).sva).itm(3)} {slc(regs.regs(1).sva).itm(4)} {slc(regs.regs(1).sva).itm(5)} {slc(regs.regs(1).sva).itm(6)} {slc(regs.regs(1).sva).itm(7)} {slc(regs.regs(1).sva).itm(8)} {slc(regs.regs(1).sva).itm(9)} -attr xrf 39795 -attr oid 282 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {slc(regs.regs(0).sva).itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva).itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva).itm} 10 {slc(regs.regs(0).sva).itm(0)} {slc(regs.regs(0).sva).itm(1)} {slc(regs.regs(0).sva).itm(2)} {slc(regs.regs(0).sva).itm(3)} {slc(regs.regs(0).sva).itm(4)} {slc(regs.regs(0).sva).itm(5)} {slc(regs.regs(0).sva).itm(6)} {slc(regs.regs(0).sva).itm(7)} {slc(regs.regs(0).sva).itm(8)} {slc(regs.regs(0).sva).itm(9)} -attr xrf 39796 -attr oid 283 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {FRAME:for#1:mul#2.itm(0)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(1)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(2)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(3)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(4)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(5)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(6)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(7)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(8)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(9)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(10)} -attr vt d
+load net {FRAME:for#1:mul#2.itm(11)} -attr vt d
+load netBundle {FRAME:for#1:mul#2.itm} 12 {FRAME:for#1:mul#2.itm(0)} {FRAME:for#1:mul#2.itm(1)} {FRAME:for#1:mul#2.itm(2)} {FRAME:for#1:mul#2.itm(3)} {FRAME:for#1:mul#2.itm(4)} {FRAME:for#1:mul#2.itm(5)} {FRAME:for#1:mul#2.itm(6)} {FRAME:for#1:mul#2.itm(7)} {FRAME:for#1:mul#2.itm(8)} {FRAME:for#1:mul#2.itm(9)} {FRAME:for#1:mul#2.itm(10)} {FRAME:for#1:mul#2.itm(11)} -attr xrf 39797 -attr oid 284 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {regs.operator[]#17:mux.itm(0)} -attr vt d
+load net {regs.operator[]#17:mux.itm(1)} -attr vt d
+load net {regs.operator[]#17:mux.itm(2)} -attr vt d
+load net {regs.operator[]#17:mux.itm(3)} -attr vt d
+load net {regs.operator[]#17:mux.itm(4)} -attr vt d
+load net {regs.operator[]#17:mux.itm(5)} -attr vt d
+load net {regs.operator[]#17:mux.itm(6)} -attr vt d
+load net {regs.operator[]#17:mux.itm(7)} -attr vt d
+load net {regs.operator[]#17:mux.itm(8)} -attr vt d
+load net {regs.operator[]#17:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#17:mux.itm} 10 {regs.operator[]#17:mux.itm(0)} {regs.operator[]#17:mux.itm(1)} {regs.operator[]#17:mux.itm(2)} {regs.operator[]#17:mux.itm(3)} {regs.operator[]#17:mux.itm(4)} {regs.operator[]#17:mux.itm(5)} {regs.operator[]#17:mux.itm(6)} {regs.operator[]#17:mux.itm(7)} {regs.operator[]#17:mux.itm(8)} {regs.operator[]#17:mux.itm(9)} -attr xrf 39798 -attr oid 285 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm)#3.itm} 10 {slc(regs.regs(2).lpi#1.dfm)#3.itm(0)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(1)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(2)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(3)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(4)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(5)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(6)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(7)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(8)} {slc(regs.regs(2).lpi#1.dfm)#3.itm(9)} -attr xrf 39799 -attr oid 286 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {slc(regs.regs(1).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#3.itm} 10 {slc(regs.regs(1).sva)#3.itm(0)} {slc(regs.regs(1).sva)#3.itm(1)} {slc(regs.regs(1).sva)#3.itm(2)} {slc(regs.regs(1).sva)#3.itm(3)} {slc(regs.regs(1).sva)#3.itm(4)} {slc(regs.regs(1).sva)#3.itm(5)} {slc(regs.regs(1).sva)#3.itm(6)} {slc(regs.regs(1).sva)#3.itm(7)} {slc(regs.regs(1).sva)#3.itm(8)} {slc(regs.regs(1).sva)#3.itm(9)} -attr xrf 39800 -attr oid 287 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {slc(regs.regs(0).sva)#3.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#3.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#3.itm} 10 {slc(regs.regs(0).sva)#3.itm(0)} {slc(regs.regs(0).sva)#3.itm(1)} {slc(regs.regs(0).sva)#3.itm(2)} {slc(regs.regs(0).sva)#3.itm(3)} {slc(regs.regs(0).sva)#3.itm(4)} {slc(regs.regs(0).sva)#3.itm(5)} {slc(regs.regs(0).sva)#3.itm(6)} {slc(regs.regs(0).sva)#3.itm(7)} {slc(regs.regs(0).sva)#3.itm(8)} {slc(regs.regs(0).sva)#3.itm(9)} -attr xrf 39801 -attr oid 288 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {conc#156.itm(0)} -attr vt d
+load net {conc#156.itm(1)} -attr vt d
+load netBundle {conc#156.itm} 2 {conc#156.itm(0)} {conc#156.itm(1)} -attr xrf 39802 -attr oid 289 -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {FRAME:for:exs#36.itm(0)} -attr vt d
+load net {FRAME:for:exs#36.itm(1)} -attr vt d
+load net {FRAME:for:exs#36.itm(2)} -attr vt d
+load net {FRAME:for:exs#36.itm(3)} -attr vt d
+load net {FRAME:for:exs#36.itm(4)} -attr vt d
+load net {FRAME:for:exs#36.itm(5)} -attr vt d
+load net {FRAME:for:exs#36.itm(6)} -attr vt d
+load net {FRAME:for:exs#36.itm(7)} -attr vt d
+load net {FRAME:for:exs#36.itm(8)} -attr vt d
+load net {FRAME:for:exs#36.itm(9)} -attr vt d
+load net {FRAME:for:exs#36.itm(10)} -attr vt d
+load net {FRAME:for:exs#36.itm(11)} -attr vt d
+load net {FRAME:for:exs#36.itm(12)} -attr vt d
+load net {FRAME:for:exs#36.itm(13)} -attr vt d
+load net {FRAME:for:exs#36.itm(14)} -attr vt d
+load netBundle {FRAME:for:exs#36.itm} 15 {FRAME:for:exs#36.itm(0)} {FRAME:for:exs#36.itm(1)} {FRAME:for:exs#36.itm(2)} {FRAME:for:exs#36.itm(3)} {FRAME:for:exs#36.itm(4)} {FRAME:for:exs#36.itm(5)} {FRAME:for:exs#36.itm(6)} {FRAME:for:exs#36.itm(7)} {FRAME:for:exs#36.itm(8)} {FRAME:for:exs#36.itm(9)} {FRAME:for:exs#36.itm(10)} {FRAME:for:exs#36.itm(11)} {FRAME:for:exs#36.itm(12)} {FRAME:for:exs#36.itm(13)} {FRAME:for:exs#36.itm(14)} -attr xrf 39803 -attr oid 290 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {FRAME:for#1:mul#7.itm(0)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(1)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(2)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(3)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(4)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(5)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(6)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(7)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(8)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(9)} -attr vt d
+load net {FRAME:for#1:mul#7.itm(10)} -attr vt d
+load netBundle {FRAME:for#1:mul#7.itm} 11 {FRAME:for#1:mul#7.itm(0)} {FRAME:for#1:mul#7.itm(1)} {FRAME:for#1:mul#7.itm(2)} {FRAME:for#1:mul#7.itm(3)} {FRAME:for#1:mul#7.itm(4)} {FRAME:for#1:mul#7.itm(5)} {FRAME:for#1:mul#7.itm(6)} {FRAME:for#1:mul#7.itm(7)} {FRAME:for#1:mul#7.itm(8)} {FRAME:for#1:mul#7.itm(9)} {FRAME:for#1:mul#7.itm(10)} -attr xrf 39804 -attr oid 291 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {regs.operator[]#22:mux.itm(0)} -attr vt d
+load net {regs.operator[]#22:mux.itm(1)} -attr vt d
+load net {regs.operator[]#22:mux.itm(2)} -attr vt d
+load net {regs.operator[]#22:mux.itm(3)} -attr vt d
+load net {regs.operator[]#22:mux.itm(4)} -attr vt d
+load net {regs.operator[]#22:mux.itm(5)} -attr vt d
+load net {regs.operator[]#22:mux.itm(6)} -attr vt d
+load net {regs.operator[]#22:mux.itm(7)} -attr vt d
+load net {regs.operator[]#22:mux.itm(8)} -attr vt d
+load net {regs.operator[]#22:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#22:mux.itm} 10 {regs.operator[]#22:mux.itm(0)} {regs.operator[]#22:mux.itm(1)} {regs.operator[]#22:mux.itm(2)} {regs.operator[]#22:mux.itm(3)} {regs.operator[]#22:mux.itm(4)} {regs.operator[]#22:mux.itm(5)} {regs.operator[]#22:mux.itm(6)} {regs.operator[]#22:mux.itm(7)} {regs.operator[]#22:mux.itm(8)} {regs.operator[]#22:mux.itm(9)} -attr xrf 39805 -attr oid 292 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm)#1.itm} 10 {slc(regs.regs(2).lpi#1.dfm)#1.itm(0)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(1)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(2)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(3)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(4)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(5)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(6)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(7)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(8)} {slc(regs.regs(2).lpi#1.dfm)#1.itm(9)} -attr xrf 39806 -attr oid 293 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {slc(regs.regs(1).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#1.itm} 10 {slc(regs.regs(1).sva)#1.itm(0)} {slc(regs.regs(1).sva)#1.itm(1)} {slc(regs.regs(1).sva)#1.itm(2)} {slc(regs.regs(1).sva)#1.itm(3)} {slc(regs.regs(1).sva)#1.itm(4)} {slc(regs.regs(1).sva)#1.itm(5)} {slc(regs.regs(1).sva)#1.itm(6)} {slc(regs.regs(1).sva)#1.itm(7)} {slc(regs.regs(1).sva)#1.itm(8)} {slc(regs.regs(1).sva)#1.itm(9)} -attr xrf 39807 -attr oid 294 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {slc(regs.regs(0).sva)#1.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#1.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#1.itm} 10 {slc(regs.regs(0).sva)#1.itm(0)} {slc(regs.regs(0).sva)#1.itm(1)} {slc(regs.regs(0).sva)#1.itm(2)} {slc(regs.regs(0).sva)#1.itm(3)} {slc(regs.regs(0).sva)#1.itm(4)} {slc(regs.regs(0).sva)#1.itm(5)} {slc(regs.regs(0).sva)#1.itm(6)} {slc(regs.regs(0).sva)#1.itm(7)} {slc(regs.regs(0).sva)#1.itm(8)} {slc(regs.regs(0).sva)#1.itm(9)} -attr xrf 39808 -attr oid 295 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {FRAME:for#1:mul#1.itm(0)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(1)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(2)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(3)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(4)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(5)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(6)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(7)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(8)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(9)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(10)} -attr vt d
+load net {FRAME:for#1:mul#1.itm(11)} -attr vt d
+load netBundle {FRAME:for#1:mul#1.itm} 12 {FRAME:for#1:mul#1.itm(0)} {FRAME:for#1:mul#1.itm(1)} {FRAME:for#1:mul#1.itm(2)} {FRAME:for#1:mul#1.itm(3)} {FRAME:for#1:mul#1.itm(4)} {FRAME:for#1:mul#1.itm(5)} {FRAME:for#1:mul#1.itm(6)} {FRAME:for#1:mul#1.itm(7)} {FRAME:for#1:mul#1.itm(8)} {FRAME:for#1:mul#1.itm(9)} {FRAME:for#1:mul#1.itm(10)} {FRAME:for#1:mul#1.itm(11)} -attr xrf 39809 -attr oid 296 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {regs.operator[]#16:mux.itm(0)} -attr vt d
+load net {regs.operator[]#16:mux.itm(1)} -attr vt d
+load net {regs.operator[]#16:mux.itm(2)} -attr vt d
+load net {regs.operator[]#16:mux.itm(3)} -attr vt d
+load net {regs.operator[]#16:mux.itm(4)} -attr vt d
+load net {regs.operator[]#16:mux.itm(5)} -attr vt d
+load net {regs.operator[]#16:mux.itm(6)} -attr vt d
+load net {regs.operator[]#16:mux.itm(7)} -attr vt d
+load net {regs.operator[]#16:mux.itm(8)} -attr vt d
+load net {regs.operator[]#16:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#16:mux.itm} 10 {regs.operator[]#16:mux.itm(0)} {regs.operator[]#16:mux.itm(1)} {regs.operator[]#16:mux.itm(2)} {regs.operator[]#16:mux.itm(3)} {regs.operator[]#16:mux.itm(4)} {regs.operator[]#16:mux.itm(5)} {regs.operator[]#16:mux.itm(6)} {regs.operator[]#16:mux.itm(7)} {regs.operator[]#16:mux.itm(8)} {regs.operator[]#16:mux.itm(9)} -attr xrf 39810 -attr oid 297 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm)#4.itm} 10 {slc(regs.regs(2).lpi#1.dfm)#4.itm(0)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(1)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(2)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(3)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(4)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(5)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(6)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(7)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(8)} {slc(regs.regs(2).lpi#1.dfm)#4.itm(9)} -attr xrf 39811 -attr oid 298 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {slc(regs.regs(1).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#4.itm} 10 {slc(regs.regs(1).sva)#4.itm(0)} {slc(regs.regs(1).sva)#4.itm(1)} {slc(regs.regs(1).sva)#4.itm(2)} {slc(regs.regs(1).sva)#4.itm(3)} {slc(regs.regs(1).sva)#4.itm(4)} {slc(regs.regs(1).sva)#4.itm(5)} {slc(regs.regs(1).sva)#4.itm(6)} {slc(regs.regs(1).sva)#4.itm(7)} {slc(regs.regs(1).sva)#4.itm(8)} {slc(regs.regs(1).sva)#4.itm(9)} -attr xrf 39812 -attr oid 299 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {slc(regs.regs(0).sva)#4.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#4.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#4.itm} 10 {slc(regs.regs(0).sva)#4.itm(0)} {slc(regs.regs(0).sva)#4.itm(1)} {slc(regs.regs(0).sva)#4.itm(2)} {slc(regs.regs(0).sva)#4.itm(3)} {slc(regs.regs(0).sva)#4.itm(4)} {slc(regs.regs(0).sva)#4.itm(5)} {slc(regs.regs(0).sva)#4.itm(6)} {slc(regs.regs(0).sva)#4.itm(7)} {slc(regs.regs(0).sva)#4.itm(8)} {slc(regs.regs(0).sva)#4.itm(9)} -attr xrf 39813 -attr oid 300 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {conc#157.itm(0)} -attr vt d
+load net {conc#157.itm(1)} -attr vt d
+load netBundle {conc#157.itm} 2 {conc#157.itm(0)} {conc#157.itm(1)} -attr xrf 39814 -attr oid 301 -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {FRAME:for:exs#31.itm(0)} -attr vt d
+load net {FRAME:for:exs#31.itm(1)} -attr vt d
+load net {FRAME:for:exs#31.itm(2)} -attr vt d
+load net {FRAME:for:exs#31.itm(3)} -attr vt d
+load net {FRAME:for:exs#31.itm(4)} -attr vt d
+load net {FRAME:for:exs#31.itm(5)} -attr vt d
+load net {FRAME:for:exs#31.itm(6)} -attr vt d
+load net {FRAME:for:exs#31.itm(7)} -attr vt d
+load net {FRAME:for:exs#31.itm(8)} -attr vt d
+load net {FRAME:for:exs#31.itm(9)} -attr vt d
+load net {FRAME:for:exs#31.itm(10)} -attr vt d
+load net {FRAME:for:exs#31.itm(11)} -attr vt d
+load net {FRAME:for:exs#31.itm(12)} -attr vt d
+load net {FRAME:for:exs#31.itm(13)} -attr vt d
+load net {FRAME:for:exs#31.itm(14)} -attr vt d
+load netBundle {FRAME:for:exs#31.itm} 15 {FRAME:for:exs#31.itm(0)} {FRAME:for:exs#31.itm(1)} {FRAME:for:exs#31.itm(2)} {FRAME:for:exs#31.itm(3)} {FRAME:for:exs#31.itm(4)} {FRAME:for:exs#31.itm(5)} {FRAME:for:exs#31.itm(6)} {FRAME:for:exs#31.itm(7)} {FRAME:for:exs#31.itm(8)} {FRAME:for:exs#31.itm(9)} {FRAME:for:exs#31.itm(10)} {FRAME:for:exs#31.itm(11)} {FRAME:for:exs#31.itm(12)} {FRAME:for:exs#31.itm(13)} {FRAME:for:exs#31.itm(14)} -attr xrf 39815 -attr oid 302 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {FRAME:for#1:mul#6.itm(0)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(1)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(2)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(3)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(4)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(5)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(6)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(7)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(8)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(9)} -attr vt d
+load net {FRAME:for#1:mul#6.itm(10)} -attr vt d
+load netBundle {FRAME:for#1:mul#6.itm} 11 {FRAME:for#1:mul#6.itm(0)} {FRAME:for#1:mul#6.itm(1)} {FRAME:for#1:mul#6.itm(2)} {FRAME:for#1:mul#6.itm(3)} {FRAME:for#1:mul#6.itm(4)} {FRAME:for#1:mul#6.itm(5)} {FRAME:for#1:mul#6.itm(6)} {FRAME:for#1:mul#6.itm(7)} {FRAME:for#1:mul#6.itm(8)} {FRAME:for#1:mul#6.itm(9)} {FRAME:for#1:mul#6.itm(10)} -attr xrf 39816 -attr oid 303 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {regs.operator[]#21:mux.itm(0)} -attr vt d
+load net {regs.operator[]#21:mux.itm(1)} -attr vt d
+load net {regs.operator[]#21:mux.itm(2)} -attr vt d
+load net {regs.operator[]#21:mux.itm(3)} -attr vt d
+load net {regs.operator[]#21:mux.itm(4)} -attr vt d
+load net {regs.operator[]#21:mux.itm(5)} -attr vt d
+load net {regs.operator[]#21:mux.itm(6)} -attr vt d
+load net {regs.operator[]#21:mux.itm(7)} -attr vt d
+load net {regs.operator[]#21:mux.itm(8)} -attr vt d
+load net {regs.operator[]#21:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#21:mux.itm} 10 {regs.operator[]#21:mux.itm(0)} {regs.operator[]#21:mux.itm(1)} {regs.operator[]#21:mux.itm(2)} {regs.operator[]#21:mux.itm(3)} {regs.operator[]#21:mux.itm(4)} {regs.operator[]#21:mux.itm(5)} {regs.operator[]#21:mux.itm(6)} {regs.operator[]#21:mux.itm(7)} {regs.operator[]#21:mux.itm(8)} {regs.operator[]#21:mux.itm(9)} -attr xrf 39817 -attr oid 304 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm)#2.itm} 10 {slc(regs.regs(2).lpi#1.dfm)#2.itm(0)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(1)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(2)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(3)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(4)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(5)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(6)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(7)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(8)} {slc(regs.regs(2).lpi#1.dfm)#2.itm(9)} -attr xrf 39818 -attr oid 305 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {slc(regs.regs(1).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#2.itm} 10 {slc(regs.regs(1).sva)#2.itm(0)} {slc(regs.regs(1).sva)#2.itm(1)} {slc(regs.regs(1).sva)#2.itm(2)} {slc(regs.regs(1).sva)#2.itm(3)} {slc(regs.regs(1).sva)#2.itm(4)} {slc(regs.regs(1).sva)#2.itm(5)} {slc(regs.regs(1).sva)#2.itm(6)} {slc(regs.regs(1).sva)#2.itm(7)} {slc(regs.regs(1).sva)#2.itm(8)} {slc(regs.regs(1).sva)#2.itm(9)} -attr xrf 39819 -attr oid 306 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {slc(regs.regs(0).sva)#2.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#2.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#2.itm} 10 {slc(regs.regs(0).sva)#2.itm(0)} {slc(regs.regs(0).sva)#2.itm(1)} {slc(regs.regs(0).sva)#2.itm(2)} {slc(regs.regs(0).sva)#2.itm(3)} {slc(regs.regs(0).sva)#2.itm(4)} {slc(regs.regs(0).sva)#2.itm(5)} {slc(regs.regs(0).sva)#2.itm(6)} {slc(regs.regs(0).sva)#2.itm(7)} {slc(regs.regs(0).sva)#2.itm(8)} {slc(regs.regs(0).sva)#2.itm(9)} -attr xrf 39820 -attr oid 307 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {FRAME:for#1:mul.itm(0)} -attr vt d
+load net {FRAME:for#1:mul.itm(1)} -attr vt d
+load net {FRAME:for#1:mul.itm(2)} -attr vt d
+load net {FRAME:for#1:mul.itm(3)} -attr vt d
+load net {FRAME:for#1:mul.itm(4)} -attr vt d
+load net {FRAME:for#1:mul.itm(5)} -attr vt d
+load net {FRAME:for#1:mul.itm(6)} -attr vt d
+load net {FRAME:for#1:mul.itm(7)} -attr vt d
+load net {FRAME:for#1:mul.itm(8)} -attr vt d
+load net {FRAME:for#1:mul.itm(9)} -attr vt d
+load net {FRAME:for#1:mul.itm(10)} -attr vt d
+load net {FRAME:for#1:mul.itm(11)} -attr vt d
+load netBundle {FRAME:for#1:mul.itm} 12 {FRAME:for#1:mul.itm(0)} {FRAME:for#1:mul.itm(1)} {FRAME:for#1:mul.itm(2)} {FRAME:for#1:mul.itm(3)} {FRAME:for#1:mul.itm(4)} {FRAME:for#1:mul.itm(5)} {FRAME:for#1:mul.itm(6)} {FRAME:for#1:mul.itm(7)} {FRAME:for#1:mul.itm(8)} {FRAME:for#1:mul.itm(9)} {FRAME:for#1:mul.itm(10)} {FRAME:for#1:mul.itm(11)} -attr xrf 39821 -attr oid 308 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {regs.operator[]#15:mux.itm(0)} -attr vt d
+load net {regs.operator[]#15:mux.itm(1)} -attr vt d
+load net {regs.operator[]#15:mux.itm(2)} -attr vt d
+load net {regs.operator[]#15:mux.itm(3)} -attr vt d
+load net {regs.operator[]#15:mux.itm(4)} -attr vt d
+load net {regs.operator[]#15:mux.itm(5)} -attr vt d
+load net {regs.operator[]#15:mux.itm(6)} -attr vt d
+load net {regs.operator[]#15:mux.itm(7)} -attr vt d
+load net {regs.operator[]#15:mux.itm(8)} -attr vt d
+load net {regs.operator[]#15:mux.itm(9)} -attr vt d
+load netBundle {regs.operator[]#15:mux.itm} 10 {regs.operator[]#15:mux.itm(0)} {regs.operator[]#15:mux.itm(1)} {regs.operator[]#15:mux.itm(2)} {regs.operator[]#15:mux.itm(3)} {regs.operator[]#15:mux.itm(4)} {regs.operator[]#15:mux.itm(5)} {regs.operator[]#15:mux.itm(6)} {regs.operator[]#15:mux.itm(7)} {regs.operator[]#15:mux.itm(8)} {regs.operator[]#15:mux.itm(9)} -attr xrf 39822 -attr oid 309 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(2).lpi#1.dfm)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(2).lpi#1.dfm)#5.itm} 10 {slc(regs.regs(2).lpi#1.dfm)#5.itm(0)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(1)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(2)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(3)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(4)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(5)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(6)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(7)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(8)} {slc(regs.regs(2).lpi#1.dfm)#5.itm(9)} -attr xrf 39823 -attr oid 310 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {slc(regs.regs(1).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(1).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(1).sva)#5.itm} 10 {slc(regs.regs(1).sva)#5.itm(0)} {slc(regs.regs(1).sva)#5.itm(1)} {slc(regs.regs(1).sva)#5.itm(2)} {slc(regs.regs(1).sva)#5.itm(3)} {slc(regs.regs(1).sva)#5.itm(4)} {slc(regs.regs(1).sva)#5.itm(5)} {slc(regs.regs(1).sva)#5.itm(6)} {slc(regs.regs(1).sva)#5.itm(7)} {slc(regs.regs(1).sva)#5.itm(8)} {slc(regs.regs(1).sva)#5.itm(9)} -attr xrf 39824 -attr oid 311 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {slc(regs.regs(0).sva)#5.itm(0)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(1)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(2)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(3)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(4)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(5)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(6)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(7)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(8)} -attr vt d
+load net {slc(regs.regs(0).sva)#5.itm(9)} -attr vt d
+load netBundle {slc(regs.regs(0).sva)#5.itm} 10 {slc(regs.regs(0).sva)#5.itm(0)} {slc(regs.regs(0).sva)#5.itm(1)} {slc(regs.regs(0).sva)#5.itm(2)} {slc(regs.regs(0).sva)#5.itm(3)} {slc(regs.regs(0).sva)#5.itm(4)} {slc(regs.regs(0).sva)#5.itm(5)} {slc(regs.regs(0).sva)#5.itm(6)} {slc(regs.regs(0).sva)#5.itm(7)} {slc(regs.regs(0).sva)#5.itm(8)} {slc(regs.regs(0).sva)#5.itm(9)} -attr xrf 39825 -attr oid 312 -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {conc#158.itm(0)} -attr vt d
+load net {conc#158.itm(1)} -attr vt d
+load netBundle {conc#158.itm} 2 {conc#158.itm(0)} {conc#158.itm(1)} -attr xrf 39826 -attr oid 313 -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {FRAME:for:exs#37.itm(0)} -attr vt d
+load net {FRAME:for:exs#37.itm(1)} -attr vt d
+load net {FRAME:for:exs#37.itm(2)} -attr vt d
+load net {FRAME:for:exs#37.itm(3)} -attr vt d
+load net {FRAME:for:exs#37.itm(4)} -attr vt d
+load net {FRAME:for:exs#37.itm(5)} -attr vt d
+load net {FRAME:for:exs#37.itm(6)} -attr vt d
+load net {FRAME:for:exs#37.itm(7)} -attr vt d
+load net {FRAME:for:exs#37.itm(8)} -attr vt d
+load net {FRAME:for:exs#37.itm(9)} -attr vt d
+load net {FRAME:for:exs#37.itm(10)} -attr vt d
+load net {FRAME:for:exs#37.itm(11)} -attr vt d
+load net {FRAME:for:exs#37.itm(12)} -attr vt d
+load net {FRAME:for:exs#37.itm(13)} -attr vt d
+load net {FRAME:for:exs#37.itm(14)} -attr vt d
+load net {FRAME:for:exs#37.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#37.itm} 16 {FRAME:for:exs#37.itm(0)} {FRAME:for:exs#37.itm(1)} {FRAME:for:exs#37.itm(2)} {FRAME:for:exs#37.itm(3)} {FRAME:for:exs#37.itm(4)} {FRAME:for:exs#37.itm(5)} {FRAME:for:exs#37.itm(6)} {FRAME:for:exs#37.itm(7)} {FRAME:for:exs#37.itm(8)} {FRAME:for:exs#37.itm(9)} {FRAME:for:exs#37.itm(10)} {FRAME:for:exs#37.itm(11)} {FRAME:for:exs#37.itm(12)} {FRAME:for:exs#37.itm(13)} {FRAME:for:exs#37.itm(14)} {FRAME:for:exs#37.itm(15)} -attr xrf 39827 -attr oid 314 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {FRAME:for:exs#39.itm(0)} -attr vt d
+load net {FRAME:for:exs#39.itm(1)} -attr vt d
+load net {FRAME:for:exs#39.itm(2)} -attr vt d
+load net {FRAME:for:exs#39.itm(3)} -attr vt d
+load net {FRAME:for:exs#39.itm(4)} -attr vt d
+load net {FRAME:for:exs#39.itm(5)} -attr vt d
+load net {FRAME:for:exs#39.itm(6)} -attr vt d
+load net {FRAME:for:exs#39.itm(7)} -attr vt d
+load net {FRAME:for:exs#39.itm(8)} -attr vt d
+load net {FRAME:for:exs#39.itm(9)} -attr vt d
+load net {FRAME:for:exs#39.itm(10)} -attr vt d
+load net {FRAME:for:exs#39.itm(11)} -attr vt d
+load net {FRAME:for:exs#39.itm(12)} -attr vt d
+load net {FRAME:for:exs#39.itm(13)} -attr vt d
+load net {FRAME:for:exs#39.itm(14)} -attr vt d
+load net {FRAME:for:exs#39.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#39.itm} 16 {FRAME:for:exs#39.itm(0)} {FRAME:for:exs#39.itm(1)} {FRAME:for:exs#39.itm(2)} {FRAME:for:exs#39.itm(3)} {FRAME:for:exs#39.itm(4)} {FRAME:for:exs#39.itm(5)} {FRAME:for:exs#39.itm(6)} {FRAME:for:exs#39.itm(7)} {FRAME:for:exs#39.itm(8)} {FRAME:for:exs#39.itm(9)} {FRAME:for:exs#39.itm(10)} {FRAME:for:exs#39.itm(11)} {FRAME:for:exs#39.itm(12)} {FRAME:for:exs#39.itm(13)} {FRAME:for:exs#39.itm(14)} {FRAME:for:exs#39.itm(15)} -attr xrf 39828 -attr oid 315 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {FRAME:for:exs#41.itm(0)} -attr vt d
+load net {FRAME:for:exs#41.itm(1)} -attr vt d
+load net {FRAME:for:exs#41.itm(2)} -attr vt d
+load net {FRAME:for:exs#41.itm(3)} -attr vt d
+load net {FRAME:for:exs#41.itm(4)} -attr vt d
+load net {FRAME:for:exs#41.itm(5)} -attr vt d
+load net {FRAME:for:exs#41.itm(6)} -attr vt d
+load net {FRAME:for:exs#41.itm(7)} -attr vt d
+load net {FRAME:for:exs#41.itm(8)} -attr vt d
+load net {FRAME:for:exs#41.itm(9)} -attr vt d
+load net {FRAME:for:exs#41.itm(10)} -attr vt d
+load net {FRAME:for:exs#41.itm(11)} -attr vt d
+load net {FRAME:for:exs#41.itm(12)} -attr vt d
+load net {FRAME:for:exs#41.itm(13)} -attr vt d
+load net {FRAME:for:exs#41.itm(14)} -attr vt d
+load net {FRAME:for:exs#41.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#41.itm} 16 {FRAME:for:exs#41.itm(0)} {FRAME:for:exs#41.itm(1)} {FRAME:for:exs#41.itm(2)} {FRAME:for:exs#41.itm(3)} {FRAME:for:exs#41.itm(4)} {FRAME:for:exs#41.itm(5)} {FRAME:for:exs#41.itm(6)} {FRAME:for:exs#41.itm(7)} {FRAME:for:exs#41.itm(8)} {FRAME:for:exs#41.itm(9)} {FRAME:for:exs#41.itm(10)} {FRAME:for:exs#41.itm(11)} {FRAME:for:exs#41.itm(12)} {FRAME:for:exs#41.itm(13)} {FRAME:for:exs#41.itm(14)} {FRAME:for:exs#41.itm(15)} -attr xrf 39829 -attr oid 316 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {FRAME:for:exs#38.itm(0)} -attr vt d
+load net {FRAME:for:exs#38.itm(1)} -attr vt d
+load net {FRAME:for:exs#38.itm(2)} -attr vt d
+load net {FRAME:for:exs#38.itm(3)} -attr vt d
+load net {FRAME:for:exs#38.itm(4)} -attr vt d
+load net {FRAME:for:exs#38.itm(5)} -attr vt d
+load net {FRAME:for:exs#38.itm(6)} -attr vt d
+load net {FRAME:for:exs#38.itm(7)} -attr vt d
+load net {FRAME:for:exs#38.itm(8)} -attr vt d
+load net {FRAME:for:exs#38.itm(9)} -attr vt d
+load net {FRAME:for:exs#38.itm(10)} -attr vt d
+load net {FRAME:for:exs#38.itm(11)} -attr vt d
+load net {FRAME:for:exs#38.itm(12)} -attr vt d
+load net {FRAME:for:exs#38.itm(13)} -attr vt d
+load net {FRAME:for:exs#38.itm(14)} -attr vt d
+load net {FRAME:for:exs#38.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#38.itm} 16 {FRAME:for:exs#38.itm(0)} {FRAME:for:exs#38.itm(1)} {FRAME:for:exs#38.itm(2)} {FRAME:for:exs#38.itm(3)} {FRAME:for:exs#38.itm(4)} {FRAME:for:exs#38.itm(5)} {FRAME:for:exs#38.itm(6)} {FRAME:for:exs#38.itm(7)} {FRAME:for:exs#38.itm(8)} {FRAME:for:exs#38.itm(9)} {FRAME:for:exs#38.itm(10)} {FRAME:for:exs#38.itm(11)} {FRAME:for:exs#38.itm(12)} {FRAME:for:exs#38.itm(13)} {FRAME:for:exs#38.itm(14)} {FRAME:for:exs#38.itm(15)} -attr xrf 39830 -attr oid 317 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {FRAME:for:exs#40.itm(0)} -attr vt d
+load net {FRAME:for:exs#40.itm(1)} -attr vt d
+load net {FRAME:for:exs#40.itm(2)} -attr vt d
+load net {FRAME:for:exs#40.itm(3)} -attr vt d
+load net {FRAME:for:exs#40.itm(4)} -attr vt d
+load net {FRAME:for:exs#40.itm(5)} -attr vt d
+load net {FRAME:for:exs#40.itm(6)} -attr vt d
+load net {FRAME:for:exs#40.itm(7)} -attr vt d
+load net {FRAME:for:exs#40.itm(8)} -attr vt d
+load net {FRAME:for:exs#40.itm(9)} -attr vt d
+load net {FRAME:for:exs#40.itm(10)} -attr vt d
+load net {FRAME:for:exs#40.itm(11)} -attr vt d
+load net {FRAME:for:exs#40.itm(12)} -attr vt d
+load net {FRAME:for:exs#40.itm(13)} -attr vt d
+load net {FRAME:for:exs#40.itm(14)} -attr vt d
+load net {FRAME:for:exs#40.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#40.itm} 16 {FRAME:for:exs#40.itm(0)} {FRAME:for:exs#40.itm(1)} {FRAME:for:exs#40.itm(2)} {FRAME:for:exs#40.itm(3)} {FRAME:for:exs#40.itm(4)} {FRAME:for:exs#40.itm(5)} {FRAME:for:exs#40.itm(6)} {FRAME:for:exs#40.itm(7)} {FRAME:for:exs#40.itm(8)} {FRAME:for:exs#40.itm(9)} {FRAME:for:exs#40.itm(10)} {FRAME:for:exs#40.itm(11)} {FRAME:for:exs#40.itm(12)} {FRAME:for:exs#40.itm(13)} {FRAME:for:exs#40.itm(14)} {FRAME:for:exs#40.itm(15)} -attr xrf 39831 -attr oid 318 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {FRAME:for:exs#33.itm(0)} -attr vt d
+load net {FRAME:for:exs#33.itm(1)} -attr vt d
+load net {FRAME:for:exs#33.itm(2)} -attr vt d
+load net {FRAME:for:exs#33.itm(3)} -attr vt d
+load net {FRAME:for:exs#33.itm(4)} -attr vt d
+load net {FRAME:for:exs#33.itm(5)} -attr vt d
+load net {FRAME:for:exs#33.itm(6)} -attr vt d
+load net {FRAME:for:exs#33.itm(7)} -attr vt d
+load net {FRAME:for:exs#33.itm(8)} -attr vt d
+load net {FRAME:for:exs#33.itm(9)} -attr vt d
+load net {FRAME:for:exs#33.itm(10)} -attr vt d
+load net {FRAME:for:exs#33.itm(11)} -attr vt d
+load net {FRAME:for:exs#33.itm(12)} -attr vt d
+load net {FRAME:for:exs#33.itm(13)} -attr vt d
+load net {FRAME:for:exs#33.itm(14)} -attr vt d
+load net {FRAME:for:exs#33.itm(15)} -attr vt d
+load netBundle {FRAME:for:exs#33.itm} 16 {FRAME:for:exs#33.itm(0)} {FRAME:for:exs#33.itm(1)} {FRAME:for:exs#33.itm(2)} {FRAME:for:exs#33.itm(3)} {FRAME:for:exs#33.itm(4)} {FRAME:for:exs#33.itm(5)} {FRAME:for:exs#33.itm(6)} {FRAME:for:exs#33.itm(7)} {FRAME:for:exs#33.itm(8)} {FRAME:for:exs#33.itm(9)} {FRAME:for:exs#33.itm(10)} {FRAME:for:exs#33.itm(11)} {FRAME:for:exs#33.itm(12)} {FRAME:for:exs#33.itm(13)} {FRAME:for:exs#33.itm(14)} {FRAME:for:exs#33.itm(15)} -attr xrf 39832 -attr oid 319 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {FRAME:for:exs#26.itm(0)} -attr vt d
+load net {FRAME:for:exs#26.itm(1)} -attr vt d
+load netBundle {FRAME:for:exs#26.itm} 2 {FRAME:for:exs#26.itm(0)} {FRAME:for:exs#26.itm(1)} -attr xrf 39833 -attr oid 320 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#26.itm}
+load net {clk} -attr xrf 39834 -attr oid 321
+load net {clk} -port {clk} -attr xrf 39835 -attr oid 322
+load net {en} -attr xrf 39836 -attr oid 323
+load net {en} -port {en} -attr xrf 39837 -attr oid 324
+load net {arst_n} -attr xrf 39838 -attr oid 325
+load net {arst_n} -port {arst_n} -attr xrf 39839 -attr oid 326
+load net {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 39840 -attr oid 327 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(0)} -port {vin:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(1)} -port {vin:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(2)} -port {vin:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(3)} -port {vin:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(4)} -port {vin:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(5)} -port {vin:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(6)} -port {vin:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(7)} -port {vin:rsc:mgc_in_wire.d(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(8)} -port {vin:rsc:mgc_in_wire.d(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(9)} -port {vin:rsc:mgc_in_wire.d(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(10)} -port {vin:rsc:mgc_in_wire.d(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(11)} -port {vin:rsc:mgc_in_wire.d(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(12)} -port {vin:rsc:mgc_in_wire.d(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(13)} -port {vin:rsc:mgc_in_wire.d(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(14)} -port {vin:rsc:mgc_in_wire.d(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(15)} -port {vin:rsc:mgc_in_wire.d(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(16)} -port {vin:rsc:mgc_in_wire.d(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(17)} -port {vin:rsc:mgc_in_wire.d(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(18)} -port {vin:rsc:mgc_in_wire.d(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(19)} -port {vin:rsc:mgc_in_wire.d(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(20)} -port {vin:rsc:mgc_in_wire.d(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(21)} -port {vin:rsc:mgc_in_wire.d(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(22)} -port {vin:rsc:mgc_in_wire.d(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(23)} -port {vin:rsc:mgc_in_wire.d(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(24)} -port {vin:rsc:mgc_in_wire.d(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(25)} -port {vin:rsc:mgc_in_wire.d(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(26)} -port {vin:rsc:mgc_in_wire.d(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(27)} -port {vin:rsc:mgc_in_wire.d(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(28)} -port {vin:rsc:mgc_in_wire.d(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(29)} -port {vin:rsc:mgc_in_wire.d(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(30)} -port {vin:rsc:mgc_in_wire.d(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(31)} -port {vin:rsc:mgc_in_wire.d(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(32)} -port {vin:rsc:mgc_in_wire.d(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(33)} -port {vin:rsc:mgc_in_wire.d(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(34)} -port {vin:rsc:mgc_in_wire.d(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(35)} -port {vin:rsc:mgc_in_wire.d(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(36)} -port {vin:rsc:mgc_in_wire.d(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(37)} -port {vin:rsc:mgc_in_wire.d(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(38)} -port {vin:rsc:mgc_in_wire.d(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(39)} -port {vin:rsc:mgc_in_wire.d(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(40)} -port {vin:rsc:mgc_in_wire.d(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(41)} -port {vin:rsc:mgc_in_wire.d(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(42)} -port {vin:rsc:mgc_in_wire.d(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(43)} -port {vin:rsc:mgc_in_wire.d(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(44)} -port {vin:rsc:mgc_in_wire.d(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(45)} -port {vin:rsc:mgc_in_wire.d(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(46)} -port {vin:rsc:mgc_in_wire.d(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(47)} -port {vin:rsc:mgc_in_wire.d(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(48)} -port {vin:rsc:mgc_in_wire.d(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(49)} -port {vin:rsc:mgc_in_wire.d(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(50)} -port {vin:rsc:mgc_in_wire.d(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(51)} -port {vin:rsc:mgc_in_wire.d(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(52)} -port {vin:rsc:mgc_in_wire.d(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(53)} -port {vin:rsc:mgc_in_wire.d(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(54)} -port {vin:rsc:mgc_in_wire.d(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(55)} -port {vin:rsc:mgc_in_wire.d(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(56)} -port {vin:rsc:mgc_in_wire.d(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(57)} -port {vin:rsc:mgc_in_wire.d(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(58)} -port {vin:rsc:mgc_in_wire.d(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(59)} -port {vin:rsc:mgc_in_wire.d(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(60)} -port {vin:rsc:mgc_in_wire.d(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(61)} -port {vin:rsc:mgc_in_wire.d(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(62)} -port {vin:rsc:mgc_in_wire.d(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(63)} -port {vin:rsc:mgc_in_wire.d(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(64)} -port {vin:rsc:mgc_in_wire.d(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(65)} -port {vin:rsc:mgc_in_wire.d(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(66)} -port {vin:rsc:mgc_in_wire.d(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(67)} -port {vin:rsc:mgc_in_wire.d(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(68)} -port {vin:rsc:mgc_in_wire.d(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(69)} -port {vin:rsc:mgc_in_wire.d(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(70)} -port {vin:rsc:mgc_in_wire.d(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(71)} -port {vin:rsc:mgc_in_wire.d(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(72)} -port {vin:rsc:mgc_in_wire.d(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(73)} -port {vin:rsc:mgc_in_wire.d(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(74)} -port {vin:rsc:mgc_in_wire.d(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(75)} -port {vin:rsc:mgc_in_wire.d(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(76)} -port {vin:rsc:mgc_in_wire.d(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(77)} -port {vin:rsc:mgc_in_wire.d(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(78)} -port {vin:rsc:mgc_in_wire.d(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(79)} -port {vin:rsc:mgc_in_wire.d(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(80)} -port {vin:rsc:mgc_in_wire.d(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(81)} -port {vin:rsc:mgc_in_wire.d(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(82)} -port {vin:rsc:mgc_in_wire.d(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(83)} -port {vin:rsc:mgc_in_wire.d(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(84)} -port {vin:rsc:mgc_in_wire.d(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(85)} -port {vin:rsc:mgc_in_wire.d(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(86)} -port {vin:rsc:mgc_in_wire.d(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(87)} -port {vin:rsc:mgc_in_wire.d(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(88)} -port {vin:rsc:mgc_in_wire.d(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d(89)} -port {vin:rsc:mgc_in_wire.d(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d} 90 {vin:rsc:mgc_in_wire.d(0)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(89)} -attr xrf 39841 -attr oid 328 -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d} 30 {vout:rsc:mgc_out_stdreg.d(0)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(29)} -attr xrf 39842 -attr oid 329 -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -port {vout:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -port {vout:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -port {vout:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -port {vout:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -port {vout:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -port {vout:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -port {vout:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -port {vout:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -port {vout:rsc:mgc_out_stdreg.d(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -port {vout:rsc:mgc_out_stdreg.d(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -port {vout:rsc:mgc_out_stdreg.d(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -port {vout:rsc:mgc_out_stdreg.d(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -port {vout:rsc:mgc_out_stdreg.d(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -port {vout:rsc:mgc_out_stdreg.d(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -port {vout:rsc:mgc_out_stdreg.d(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -port {vout:rsc:mgc_out_stdreg.d(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -port {vout:rsc:mgc_out_stdreg.d(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -port {vout:rsc:mgc_out_stdreg.d(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -port {vout:rsc:mgc_out_stdreg.d(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -port {vout:rsc:mgc_out_stdreg.d(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -port {vout:rsc:mgc_out_stdreg.d(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -port {vout:rsc:mgc_out_stdreg.d(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -port {vout:rsc:mgc_out_stdreg.d(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -port {vout:rsc:mgc_out_stdreg.d(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -port {vout:rsc:mgc_out_stdreg.d(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -port {vout:rsc:mgc_out_stdreg.d(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -port {vout:rsc:mgc_out_stdreg.d(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -port {vout:rsc:mgc_out_stdreg.d(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -port {vout:rsc:mgc_out_stdreg.d(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -port {vout:rsc:mgc_out_stdreg.d(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:acc#38" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 39843 -attr oid 330 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {FRAME:acc#37.itm#1(0)} -pin  "FRAME:acc#38" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(1)} -pin  "FRAME:acc#38" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(2)} -pin  "FRAME:acc#38" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(3)} -pin  "FRAME:acc#38" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(4)} -pin  "FRAME:acc#38" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:slc(acc.imod#3)#4.itm#1} -pin  "FRAME:acc#38" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc.itm}
+load net {PWR} -pin  "FRAME:acc#38" {B(1)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:acc#38" {B(2)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {GND} -pin  "FRAME:acc#38" {B(3)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {PWR} -pin  "FRAME:acc#38" {B(4)} -attr @path {/sobel/sobel:core/conc.itm}
+load net {FRAME:acc#38.itm(0)} -pin  "FRAME:acc#38" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(1)} -pin  "FRAME:acc#38" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(2)} -pin  "FRAME:acc#38" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(3)} -pin  "FRAME:acc#38" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(4)} -pin  "FRAME:acc#38" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load inst "FRAME:acc#39" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 39844 -attr oid 331 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {red:slc(red#2.sg1).itm#1(0)} -pin  "FRAME:acc#39" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(1)} -pin  "FRAME:acc#39" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(2)} -pin  "FRAME:acc#39" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(3)} -pin  "FRAME:acc#39" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(4)} -pin  "FRAME:acc#39" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(5)} -pin  "FRAME:acc#39" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {FRAME:acc#38.itm(0)} -pin  "FRAME:acc#39" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(1)} -pin  "FRAME:acc#39" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(2)} -pin  "FRAME:acc#39" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(3)} -pin  "FRAME:acc#39" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#38.itm(4)} -pin  "FRAME:acc#39" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#38.itm}
+load net {FRAME:acc#39.itm(0)} -pin  "FRAME:acc#39" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(1)} -pin  "FRAME:acc#39" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(2)} -pin  "FRAME:acc#39" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(3)} -pin  "FRAME:acc#39" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(4)} -pin  "FRAME:acc#39" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(5)} -pin  "FRAME:acc#39" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(6)} -pin  "FRAME:acc#39" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(7)} -pin  "FRAME:acc#39" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load inst "FRAME:acc#40" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 39845 -attr oid 332 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul#1.itm#1(0)} -pin  "FRAME:acc#40" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(1)} -pin  "FRAME:acc#40" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(2)} -pin  "FRAME:acc#40" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(3)} -pin  "FRAME:acc#40" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(4)} -pin  "FRAME:acc#40" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(5)} -pin  "FRAME:acc#40" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(6)} -pin  "FRAME:acc#40" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(7)} -pin  "FRAME:acc#40" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(8)} -pin  "FRAME:acc#40" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:acc#39.itm(0)} -pin  "FRAME:acc#40" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(1)} -pin  "FRAME:acc#40" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(2)} -pin  "FRAME:acc#40" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(3)} -pin  "FRAME:acc#40" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(4)} -pin  "FRAME:acc#40" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(5)} -pin  "FRAME:acc#40" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(6)} -pin  "FRAME:acc#40" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#39.itm(7)} -pin  "FRAME:acc#40" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#39.itm}
+load net {FRAME:acc#40.itm(0)} -pin  "FRAME:acc#40" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(1)} -pin  "FRAME:acc#40" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(2)} -pin  "FRAME:acc#40" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(3)} -pin  "FRAME:acc#40" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(4)} -pin  "FRAME:acc#40" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(5)} -pin  "FRAME:acc#40" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(6)} -pin  "FRAME:acc#40" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(7)} -pin  "FRAME:acc#40" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(8)} -pin  "FRAME:acc#40" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(9)} -pin  "FRAME:acc#40" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load inst "FRAME:acc#2" "add(10,-1,10,-1,10)" "INTERFACE" -attr xrf 39846 -attr oid 333 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2} -attr area 11.241230 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(10,0,10,0,10)"
+load net {FRAME:acc#41.itm#3(0)} -pin  "FRAME:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#3(1)} -pin  "FRAME:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#3(2)} -pin  "FRAME:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#3(3)} -pin  "FRAME:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#3(4)} -pin  "FRAME:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#3(5)} -pin  "FRAME:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#1.sg1(0)} -pin  "FRAME:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#1.sg1(1)} -pin  "FRAME:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#1.sg2(0)} -pin  "FRAME:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#41.itm#1.sg2(1)} -pin  "FRAME:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#36.itm}
+load net {FRAME:acc#40.itm(0)} -pin  "FRAME:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(1)} -pin  "FRAME:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(2)} -pin  "FRAME:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(3)} -pin  "FRAME:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(4)} -pin  "FRAME:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(5)} -pin  "FRAME:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(6)} -pin  "FRAME:acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(7)} -pin  "FRAME:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(8)} -pin  "FRAME:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#40.itm(9)} -pin  "FRAME:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#40.itm}
+load net {FRAME:acc#2.itm(0)} -pin  "FRAME:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(1)} -pin  "FRAME:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(2)} -pin  "FRAME:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(3)} -pin  "FRAME:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(4)} -pin  "FRAME:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(5)} -pin  "FRAME:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(6)} -pin  "FRAME:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(7)} -pin  "FRAME:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(8)} -pin  "FRAME:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(9)} -pin  "FRAME:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load inst "FRAME:or" "or(2,10)" "INTERFACE" -attr xrf 39847 -attr oid 334 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or} -attr area 7.298324 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(10,2)"
+load net {FRAME:acc#2.itm(0)} -pin  "FRAME:or" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(1)} -pin  "FRAME:or" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(2)} -pin  "FRAME:or" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(3)} -pin  "FRAME:or" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(4)} -pin  "FRAME:or" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(5)} -pin  "FRAME:or" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(6)} -pin  "FRAME:or" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(7)} -pin  "FRAME:or" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(8)} -pin  "FRAME:or" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#2.itm(9)} -pin  "FRAME:or" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#2.itm}
+load net {FRAME:acc#3.psp.sva(10)} -pin  "FRAME:or" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {FRAME:acc#3.psp.sva(11)} -pin  "FRAME:or" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(2)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(3)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(4)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(5)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(6)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(7)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(8)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {GND} -pin  "FRAME:or" {A1(9)} -attr @path {/sobel/sobel:core/conc#137.itm}
+load net {FRAME:or.itm(0)} -pin  "FRAME:or" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(1)} -pin  "FRAME:or" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(2)} -pin  "FRAME:or" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(3)} -pin  "FRAME:or" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(4)} -pin  "FRAME:or" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(5)} -pin  "FRAME:or" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(6)} -pin  "FRAME:or" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(7)} -pin  "FRAME:or" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(8)} -pin  "FRAME:or" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load net {FRAME:or.itm(9)} -pin  "FRAME:or" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or.itm}
+load inst "FRAME:or#3" "or(2,6)" "INTERFACE" -attr xrf 39848 -attr oid 335 -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3} -attr area 4.378994 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(6,2)"
+load net {FRAME:acc#3.psp.sva(0)} -pin  "FRAME:or#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {FRAME:acc#3.psp.sva(1)} -pin  "FRAME:or#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {FRAME:acc#3.psp.sva(2)} -pin  "FRAME:or#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {FRAME:acc#3.psp.sva(3)} -pin  "FRAME:or#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {FRAME:acc#3.psp.sva(4)} -pin  "FRAME:or#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {FRAME:acc#3.psp.sva(5)} -pin  "FRAME:or#3" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:acc#3.psp.sva)#2.itm}
+load net {FRAME:acc#4.psp.sva(10)} -pin  "FRAME:or#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {FRAME:acc#4.psp.sva(11)} -pin  "FRAME:or#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(2)} -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(3)} -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(4)} -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {GND} -pin  "FRAME:or#3" {A1(5)} -attr @path {/sobel/sobel:core/conc#138.itm}
+load net {FRAME:or#3.itm(0)} -pin  "FRAME:or#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(1)} -pin  "FRAME:or#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(2)} -pin  "FRAME:or#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(3)} -pin  "FRAME:or#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(4)} -pin  "FRAME:or#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load net {FRAME:or#3.itm(5)} -pin  "FRAME:or#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:or#3.itm}
+load inst "nand" "nand(3,1)" "INTERFACE" -attr @path {/sobel/sobel:core/nand} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,3)"
+load net {exit:FRAME:for#1.sva#2.st#1} -pin  "nand" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.sva#2.st#1}
+load net {exit:FRAME:for.lpi#1.dfm.st#1} -pin  "nand" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm.st#1}
+load net {main.stage_0#2} -pin  "nand" {A2(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load net {nand.itm} -pin  "nand" {Z(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load inst "mux" "mux(2,30)" "INTERFACE" -attr xrf 39849 -attr oid 336 -attr vt d -attr @path {/sobel/sobel:core/mux} -attr area 27.583690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(30,1,2)"
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "mux" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "mux" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "mux" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "mux" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "mux" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "mux" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "mux" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "mux" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "mux" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "mux" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "mux" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "mux" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "mux" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "mux" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "mux" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "mux" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "mux" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "mux" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "mux" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "mux" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "mux" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "mux" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "mux" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "mux" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "mux" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "mux" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "mux" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "mux" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "mux" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "mux" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {FRAME:acc#4.psp.sva(0)} -pin  "mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(1)} -pin  "mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(2)} -pin  "mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(3)} -pin  "mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(4)} -pin  "mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(5)} -pin  "mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(6)} -pin  "mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(7)} -pin  "mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(8)} -pin  "mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#4.psp.sva(9)} -pin  "mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(0)} -pin  "mux" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(1)} -pin  "mux" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(2)} -pin  "mux" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(3)} -pin  "mux" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(4)} -pin  "mux" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or#3.itm(5)} -pin  "mux" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(6)} -pin  "mux" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(7)} -pin  "mux" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(8)} -pin  "mux" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:acc#3.psp.sva(9)} -pin  "mux" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(0)} -pin  "mux" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(1)} -pin  "mux" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(2)} -pin  "mux" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(3)} -pin  "mux" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(4)} -pin  "mux" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(5)} -pin  "mux" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(6)} -pin  "mux" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(7)} -pin  "mux" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(8)} -pin  "mux" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {FRAME:or.itm(9)} -pin  "mux" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#21.itm}
+load net {nand.itm} -pin  "mux" {S(0)} -attr @path {/sobel/sobel:core/nand.itm}
+load net {mux.itm(0)} -pin  "mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "mux" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "mux" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "mux" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "mux" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "mux" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "mux" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "mux" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "mux" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "mux" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "mux" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "mux" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "mux" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "mux" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "mux" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "mux" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "mux" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "mux" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "mux" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "mux" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "mux" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load inst "reg(vout:rsc:mgc_out_stdreg.d)" "reg(30,1,1,-1,0)" "INTERFACE" -attr xrf 39850 -attr oid 337 -attr vt d -attr @path {/sobel/sobel:core/reg(vout:rsc:mgc_out_stdreg.d)}
+load net {mux.itm(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {mux.itm(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/mux.itm}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_30}
+load net {GND} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_30}
+load net {clk} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 39851 -attr oid 338 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {vout:rsc:mgc_out_stdreg.d(0)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(1)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(2)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(3)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(4)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(5)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(6)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(7)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(8)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(9)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(10)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(11)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(12)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(13)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(14)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(15)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(16)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(17)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(18)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(19)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(20)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(21)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(22)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(23)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(24)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(25)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(26)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(27)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(28)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d(29)} -pin  "reg(vout:rsc:mgc_out_stdreg.d)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/vout:rsc:mgc_out_stdreg.d}
+load inst "FRAME:acc#43" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 39852 -attr oid 339 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43} -attr area 3.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {FRAME:mul.sdt(8)} -pin  "FRAME:acc#43" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt).itm}
+load net {FRAME:mul.sdt(9)} -pin  "FRAME:acc#43" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt).itm}
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:acc#43" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#3.itm}
+load net {FRAME:acc#43.itm(0)} -pin  "FRAME:acc#43" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {FRAME:acc#43.itm(1)} -pin  "FRAME:acc#43" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load inst "reg(FRAME:acc#41.itm#1.sg2)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 39853 -attr oid 340 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#41.itm#1.sg2)}
+load net {FRAME:acc#43.itm(0)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {FRAME:acc#43.itm(1)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#43.itm}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {clk} -attr xrf 39854 -attr oid 341 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#41.itm#1.sg2(0)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg2}
+load net {FRAME:acc#41.itm#1.sg2(1)} -pin  "reg(FRAME:acc#41.itm#1.sg2)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg2}
+load inst "reg(FRAME:acc#41.itm#1.sg1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 39855 -attr oid 342 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#41.itm#1.sg1)}
+load net {FRAME:mul.sdt(6)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#2.itm}
+load net {FRAME:mul.sdt(7)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#2.itm}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {clk} -attr xrf 39856 -attr oid 343 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#41.itm#1.sg1(0)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg1}
+load net {FRAME:acc#41.itm#1.sg1(1)} -pin  "reg(FRAME:acc#41.itm#1.sg1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#1.sg1}
+load inst "FRAME:acc#44" "add(5,0,5,0,6)" "INTERFACE" -attr xrf 39857 -attr oid 344 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44} -attr area 6.285690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,6)"
+load net {FRAME:mul.sdt(0)} -pin  "FRAME:acc#44" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(1)} -pin  "FRAME:acc#44" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(2)} -pin  "FRAME:acc#44" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(3)} -pin  "FRAME:acc#44" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {FRAME:mul.sdt(4)} -pin  "FRAME:acc#44" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:mul.sdt)#1.itm}
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:acc#44" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {GND} -pin  "FRAME:acc#44" {B(1)} -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:acc#44" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:acc#44" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:acc#44" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#3.itm}
+load net {FRAME:acc#44.itm(0)} -pin  "FRAME:acc#44" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(1)} -pin  "FRAME:acc#44" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(2)} -pin  "FRAME:acc#44" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(3)} -pin  "FRAME:acc#44" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(4)} -pin  "FRAME:acc#44" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(5)} -pin  "FRAME:acc#44" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load inst "reg(FRAME:acc#41.itm#3)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 39858 -attr oid 345 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#41.itm#3)}
+load net {FRAME:acc#44.itm(0)} -pin  "reg(FRAME:acc#41.itm#3)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(1)} -pin  "reg(FRAME:acc#41.itm#3)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(2)} -pin  "reg(FRAME:acc#41.itm#3)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(3)} -pin  "reg(FRAME:acc#41.itm#3)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(4)} -pin  "reg(FRAME:acc#41.itm#3)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {FRAME:acc#44.itm(5)} -pin  "reg(FRAME:acc#41.itm#3)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#44.itm}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(FRAME:acc#41.itm#3)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(FRAME:acc#41.itm#3)" {clk} -attr xrf 39859 -attr oid 346 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#41.itm#3)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#41.itm#3)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#41.itm#3(0)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(1)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(2)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(3)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(4)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load net {FRAME:acc#41.itm#3(5)} -pin  "reg(FRAME:acc#41.itm#3)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#41.itm#3}
+load inst "FRAME:mul#1" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 39860 -attr oid 347 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC2-3:acc#1.itm(10)} -pin  "FRAME:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {ACC2-3:acc#1.itm(11)} -pin  "FRAME:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {ACC2-3:acc#1.itm(12)} -pin  "FRAME:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#13.itm}
+load net {PWR} -pin  "FRAME:mul#1" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#1" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#1" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#1.itm(0)} -pin  "FRAME:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "FRAME:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "FRAME:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "FRAME:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "FRAME:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "FRAME:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "FRAME:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "FRAME:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "FRAME:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load inst "reg(FRAME:mul#1.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 39861 -attr oid 348 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#1.itm#1)}
+load net {FRAME:mul#1.itm(0)} -pin  "reg(FRAME:mul#1.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(1)} -pin  "reg(FRAME:mul#1.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(2)} -pin  "reg(FRAME:mul#1.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(3)} -pin  "reg(FRAME:mul#1.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(4)} -pin  "reg(FRAME:mul#1.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(5)} -pin  "reg(FRAME:mul#1.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(6)} -pin  "reg(FRAME:mul#1.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(7)} -pin  "reg(FRAME:mul#1.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {FRAME:mul#1.itm(8)} -pin  "reg(FRAME:mul#1.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#1.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#1.itm#1)" {clk} -attr xrf 39862 -attr oid 349 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#1.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#1.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#1.itm#1(0)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(1)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(2)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(3)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(4)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(5)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(6)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(7)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load net {FRAME:mul#1.itm#1(8)} -pin  "reg(FRAME:mul#1.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#1.itm#1}
+load inst "reg(red:slc(red#2.sg1).itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 39863 -attr oid 350 -attr vt d -attr @path {/sobel/sobel:core/reg(red:slc(red#2.sg1).itm#1)}
+load net {ACC2-3:acc#1.itm(4)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#1.itm(5)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#1.itm(6)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#1.itm(7)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#1.itm(8)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#1.itm(9)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#1.itm}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(red:slc(red#2.sg1).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(red:slc(red#2.sg1).itm#1)" {clk} -attr xrf 39864 -attr oid 351 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(red:slc(red#2.sg1).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {red:slc(red#2.sg1).itm#1(0)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(1)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(2)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(3)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(4)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load net {red:slc(red#2.sg1).itm#1(5)} -pin  "reg(red:slc(red#2.sg1).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/red:slc(red#2.sg1).itm#1}
+load inst "FRAME:not#7" "not(1)" "INTERFACE" -attr xrf 39865 -attr oid 352 -attr @path {/sobel/sobel:core/FRAME:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#3.sva(5)} -pin  "FRAME:not#7" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#6.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#7.itm}
+load inst "FRAME:not#5" "not(3)" "INTERFACE" -attr xrf 39866 -attr oid 353 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#3.sva(3)} -pin  "FRAME:not#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#2.itm}
+load net {acc.imod#3.sva(4)} -pin  "FRAME:not#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#2.itm}
+load net {acc.imod#3.sva(5)} -pin  "FRAME:not#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#2.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:not#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:not#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:not#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#5.itm}
+load inst "FRAME:not#4" "not(1)" "INTERFACE" -attr xrf 39867 -attr oid 354 -attr @path {/sobel/sobel:core/FRAME:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#3.sva(5)} -pin  "FRAME:not#4" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#3.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:not#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#4.itm}
+load inst "FRAME:acc#42" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 39868 -attr oid 355 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {PWR} -pin  "FRAME:acc#42" {A(0)} -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {acc.imod#3.sva(0)} -pin  "FRAME:acc#42" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {acc.imod#3.sva(1)} -pin  "FRAME:acc#42" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {acc.imod#3.sva(2)} -pin  "FRAME:acc#42" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {PWR} -pin  "FRAME:acc#42" {A(4)} -attr @path {/sobel/sobel:core/conc#142.itm}
+load net {FRAME:not#4.itm} -pin  "FRAME:acc#42" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(0)} -pin  "FRAME:acc#42" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(1)} -pin  "FRAME:acc#42" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:not#5.itm(2)} -pin  "FRAME:acc#42" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#33.itm}
+load net {FRAME:acc#42.itm(0)} -pin  "FRAME:acc#42" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(1)} -pin  "FRAME:acc#42" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(2)} -pin  "FRAME:acc#42" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(3)} -pin  "FRAME:acc#42" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load net {FRAME:acc#42.itm(4)} -pin  "FRAME:acc#42" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#42.itm}
+load inst "FRAME:not#39" "not(1)" "INTERFACE" -attr xrf 39869 -attr oid 356 -attr vt c -attr @path {/sobel/sobel:core/FRAME:not#39} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#42.itm(4)} -pin  "FRAME:not#39" {A(0)} -attr vt c -attr @path {/sobel/sobel:core/FRAME:slc#7.itm}
+load net {FRAME:not#39.itm} -pin  "FRAME:not#39" {Z(0)} -attr vt c -attr @path {/sobel/sobel:core/FRAME:not#39.itm}
+load inst "FRAME:acc#36" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 39870 -attr oid 357 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#39.itm} -pin  "FRAME:acc#36" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {PWR} -pin  "FRAME:acc#36" {A(1)} -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {FRAME:not#7.itm} -pin  "FRAME:acc#36" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/conc#141.itm}
+load net {acc.imod#3.sva(3)} -pin  "FRAME:acc#36" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#4.itm}
+load net {acc.imod#3.sva(4)} -pin  "FRAME:acc#36" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva)#4.itm}
+load net {FRAME:acc#36.itm(0)} -pin  "FRAME:acc#36" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(1)} -pin  "FRAME:acc#36" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(2)} -pin  "FRAME:acc#36" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(3)} -pin  "FRAME:acc#36" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load inst "FRAME:not#6" "not(3)" "INTERFACE" -attr xrf 39871 -attr oid 358 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#1.itm(7)} -pin  "FRAME:not#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {ACC2-3:acc#1.itm(8)} -pin  "FRAME:not#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {ACC2-3:acc#1.itm(9)} -pin  "FRAME:not#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#8.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:not#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:not#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:not#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load inst "FRAME:acc#37" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 39872 -attr oid 359 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#36.itm(0)} -pin  "FRAME:acc#37" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(1)} -pin  "FRAME:acc#37" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(2)} -pin  "FRAME:acc#37" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:acc#36.itm(3)} -pin  "FRAME:acc#37" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#36.itm}
+load net {FRAME:not#6.itm(0)} -pin  "FRAME:acc#37" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(1)} -pin  "FRAME:acc#37" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:not#6.itm(2)} -pin  "FRAME:acc#37" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#6.itm}
+load net {FRAME:acc#37.itm(0)} -pin  "FRAME:acc#37" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(1)} -pin  "FRAME:acc#37" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(2)} -pin  "FRAME:acc#37" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(3)} -pin  "FRAME:acc#37" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(4)} -pin  "FRAME:acc#37" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load inst "reg(FRAME:acc#37.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 39873 -attr oid 360 -attr vt dc -attr @path {/sobel/sobel:core/reg(FRAME:acc#37.itm#1)}
+load net {FRAME:acc#37.itm(0)} -pin  "reg(FRAME:acc#37.itm#1)" {D(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(1)} -pin  "reg(FRAME:acc#37.itm#1)" {D(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(2)} -pin  "reg(FRAME:acc#37.itm#1)" {D(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(3)} -pin  "reg(FRAME:acc#37.itm#1)" {D(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {FRAME:acc#37.itm(4)} -pin  "reg(FRAME:acc#37.itm#1)" {D(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#37.itm}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#37.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#37.itm#1)" {clk} -attr xrf 39874 -attr oid 361 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#37.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#37.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#37.itm#1(0)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(1)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(2)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(3)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load net {FRAME:acc#37.itm#1(4)} -pin  "reg(FRAME:acc#37.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#37.itm#1}
+load inst "reg(FRAME:slc(acc.imod#3)#4.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 39875 -attr oid 362 -attr @path {/sobel/sobel:core/reg(FRAME:slc(acc.imod#3)#4.itm#1)}
+load net {acc.imod#3.sva(5)} -pin  "reg(FRAME:slc(acc.imod#3)#4.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#3.sva).itm}
+load net {GND} -pin  "reg(FRAME:slc(acc.imod#3)#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(FRAME:slc(acc.imod#3)#4.itm#1)" {clk} -attr xrf 39876 -attr oid 363 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(acc.imod#3)#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(acc.imod#3)#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(acc.imod#3)#4.itm#1} -pin  "reg(FRAME:slc(acc.imod#3)#4.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:slc(acc.imod#3)#4.itm#1}
+load inst "FRAME:mul#4" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 39877 -attr oid 364 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC2-3:acc#3.itm(13)} -pin  "FRAME:mul#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#10.itm}
+load net {ACC2-3:acc#3.itm(14)} -pin  "FRAME:mul#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#10.itm}
+load net {PWR} -pin  "FRAME:mul#4" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#4" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#4" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#4.itm(0)} -pin  "FRAME:mul#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(1)} -pin  "FRAME:mul#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(2)} -pin  "FRAME:mul#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(3)} -pin  "FRAME:mul#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(4)} -pin  "FRAME:mul#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(5)} -pin  "FRAME:mul#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(6)} -pin  "FRAME:mul#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(7)} -pin  "FRAME:mul#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(8)} -pin  "FRAME:mul#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(9)} -pin  "FRAME:mul#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(10)} -pin  "FRAME:mul#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load inst "reg(FRAME:mul#4.itm#1)" "reg(11,1,1,-1,0)" "INTERFACE" -attr xrf 39878 -attr oid 365 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#4.itm#1)}
+load net {FRAME:mul#4.itm(0)} -pin  "reg(FRAME:mul#4.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(1)} -pin  "reg(FRAME:mul#4.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(2)} -pin  "reg(FRAME:mul#4.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(3)} -pin  "reg(FRAME:mul#4.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(4)} -pin  "reg(FRAME:mul#4.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(5)} -pin  "reg(FRAME:mul#4.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(6)} -pin  "reg(FRAME:mul#4.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(7)} -pin  "reg(FRAME:mul#4.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(8)} -pin  "reg(FRAME:mul#4.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(9)} -pin  "reg(FRAME:mul#4.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {FRAME:mul#4.itm(10)} -pin  "reg(FRAME:mul#4.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#4.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_11}
+load net {clk} -pin  "reg(FRAME:mul#4.itm#1)" {clk} -attr xrf 39879 -attr oid 366 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#4.itm#1(0)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(1)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(2)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(3)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(4)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(5)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(6)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(7)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(8)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(9)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(10)} -pin  "reg(FRAME:mul#4.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load inst "FRAME:mul#5" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 39880 -attr oid 367 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC2-3:acc#3.itm(10)} -pin  "FRAME:mul#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {ACC2-3:acc#3.itm(11)} -pin  "FRAME:mul#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {ACC2-3:acc#3.itm(12)} -pin  "FRAME:mul#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#11.itm}
+load net {PWR} -pin  "FRAME:mul#5" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#5" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#5" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#5" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#5.itm(0)} -pin  "FRAME:mul#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(1)} -pin  "FRAME:mul#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(2)} -pin  "FRAME:mul#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(3)} -pin  "FRAME:mul#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(4)} -pin  "FRAME:mul#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(5)} -pin  "FRAME:mul#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(6)} -pin  "FRAME:mul#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(7)} -pin  "FRAME:mul#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(8)} -pin  "FRAME:mul#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load inst "reg(FRAME:mul#5.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 39881 -attr oid 368 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#5.itm#1)}
+load net {FRAME:mul#5.itm(0)} -pin  "reg(FRAME:mul#5.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(1)} -pin  "reg(FRAME:mul#5.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(2)} -pin  "reg(FRAME:mul#5.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(3)} -pin  "reg(FRAME:mul#5.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(4)} -pin  "reg(FRAME:mul#5.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(5)} -pin  "reg(FRAME:mul#5.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(6)} -pin  "reg(FRAME:mul#5.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(7)} -pin  "reg(FRAME:mul#5.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {FRAME:mul#5.itm(8)} -pin  "reg(FRAME:mul#5.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#5.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#5.itm#1)" {clk} -attr xrf 39882 -attr oid 369 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#5.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#5.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#5.itm#1(0)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(1)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(2)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(3)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(4)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(5)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(6)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(7)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(8)} -pin  "reg(FRAME:mul#5.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load inst "reg(blue:slc(blue#2.sg1).itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 39883 -attr oid 370 -attr vt d -attr @path {/sobel/sobel:core/reg(blue:slc(blue#2.sg1).itm#1)}
+load net {ACC2-3:acc#3.itm(4)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#3.itm(5)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#3.itm(6)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#3.itm(7)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#3.itm(8)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#3.itm(9)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#2.itm}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {clk} -attr xrf 39884 -attr oid 371 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {blue:slc(blue#2.sg1).itm#1(0)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(1)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(2)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(3)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(4)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load net {blue:slc(blue#2.sg1).itm#1(5)} -pin  "reg(blue:slc(blue#2.sg1).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1).itm#1}
+load inst "FRAME:not#23" "not(1)" "INTERFACE" -attr xrf 39885 -attr oid 372 -attr @path {/sobel/sobel:core/FRAME:not#23} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#7.sva(5)} -pin  "FRAME:not#23" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#6.itm}
+load net {FRAME:not#23.itm} -pin  "FRAME:not#23" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#23.itm}
+load inst "FRAME:not#21" "not(3)" "INTERFACE" -attr xrf 39886 -attr oid 373 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#7.sva(3)} -pin  "FRAME:not#21" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#2.itm}
+load net {acc.imod#7.sva(4)} -pin  "FRAME:not#21" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#2.itm}
+load net {acc.imod#7.sva(5)} -pin  "FRAME:not#21" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#2.itm}
+load net {FRAME:not#21.itm(0)} -pin  "FRAME:not#21" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {FRAME:not#21.itm(1)} -pin  "FRAME:not#21" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load net {FRAME:not#21.itm(2)} -pin  "FRAME:not#21" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#21.itm}
+load inst "FRAME:not#20" "not(1)" "INTERFACE" -attr xrf 39887 -attr oid 374 -attr @path {/sobel/sobel:core/FRAME:not#20} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#7.sva(5)} -pin  "FRAME:not#20" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#3.itm}
+load net {FRAME:not#20.itm} -pin  "FRAME:not#20" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#20.itm}
+load inst "FRAME:acc#35" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 39888 -attr oid 375 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {PWR} -pin  "FRAME:acc#35" {A(0)} -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {acc.imod#7.sva(0)} -pin  "FRAME:acc#35" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {acc.imod#7.sva(1)} -pin  "FRAME:acc#35" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {acc.imod#7.sva(2)} -pin  "FRAME:acc#35" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {PWR} -pin  "FRAME:acc#35" {A(4)} -attr @path {/sobel/sobel:core/conc#144.itm}
+load net {FRAME:not#20.itm} -pin  "FRAME:acc#35" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(0)} -pin  "FRAME:acc#35" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(1)} -pin  "FRAME:acc#35" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:not#21.itm(2)} -pin  "FRAME:acc#35" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#29.itm}
+load net {FRAME:acc#35.itm(0)} -pin  "FRAME:acc#35" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(1)} -pin  "FRAME:acc#35" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(2)} -pin  "FRAME:acc#35" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(3)} -pin  "FRAME:acc#35" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load net {FRAME:acc#35.itm(4)} -pin  "FRAME:acc#35" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#35.itm}
+load inst "FRAME:not#41" "not(1)" "INTERFACE" -attr xrf 39889 -attr oid 376 -attr @path {/sobel/sobel:core/FRAME:not#41} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#35.itm(4)} -pin  "FRAME:not#41" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#6.itm}
+load net {FRAME:not#41.itm} -pin  "FRAME:not#41" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#41.itm}
+load inst "FRAME:acc#29" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 39890 -attr oid 377 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#41.itm} -pin  "FRAME:acc#29" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {PWR} -pin  "FRAME:acc#29" {A(1)} -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {FRAME:not#23.itm} -pin  "FRAME:acc#29" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#143.itm}
+load net {acc.imod#7.sva(3)} -pin  "FRAME:acc#29" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#4.itm}
+load net {acc.imod#7.sva(4)} -pin  "FRAME:acc#29" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva)#4.itm}
+load net {FRAME:acc#29.itm(0)} -pin  "FRAME:acc#29" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(1)} -pin  "FRAME:acc#29" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(2)} -pin  "FRAME:acc#29" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(3)} -pin  "FRAME:acc#29" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load inst "FRAME:not#22" "not(3)" "INTERFACE" -attr xrf 39891 -attr oid 378 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#3.itm(7)} -pin  "FRAME:not#22" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {ACC2-3:acc#3.itm(8)} -pin  "FRAME:not#22" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {ACC2-3:acc#3.itm(9)} -pin  "FRAME:not#22" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#9.itm}
+load net {FRAME:not#22.itm(0)} -pin  "FRAME:not#22" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(1)} -pin  "FRAME:not#22" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(2)} -pin  "FRAME:not#22" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load inst "FRAME:acc#30" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 39892 -attr oid 379 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#29.itm(0)} -pin  "FRAME:acc#30" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(1)} -pin  "FRAME:acc#30" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(2)} -pin  "FRAME:acc#30" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:acc#29.itm(3)} -pin  "FRAME:acc#30" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#29.itm}
+load net {FRAME:not#22.itm(0)} -pin  "FRAME:acc#30" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(1)} -pin  "FRAME:acc#30" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:not#22.itm(2)} -pin  "FRAME:acc#30" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#22.itm}
+load net {FRAME:acc#30.itm(0)} -pin  "FRAME:acc#30" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(1)} -pin  "FRAME:acc#30" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(2)} -pin  "FRAME:acc#30" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(3)} -pin  "FRAME:acc#30" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(4)} -pin  "FRAME:acc#30" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load inst "reg(FRAME:acc#30.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 39893 -attr oid 380 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#30.itm#1)}
+load net {FRAME:acc#30.itm(0)} -pin  "reg(FRAME:acc#30.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(1)} -pin  "reg(FRAME:acc#30.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(2)} -pin  "reg(FRAME:acc#30.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(3)} -pin  "reg(FRAME:acc#30.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {FRAME:acc#30.itm(4)} -pin  "reg(FRAME:acc#30.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#30.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#30.itm#1)" {clk} -attr xrf 39894 -attr oid 381 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#30.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#30.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#30.itm#1(0)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(1)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(2)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(3)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load net {FRAME:acc#30.itm#1(4)} -pin  "reg(FRAME:acc#30.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#30.itm#1}
+load inst "reg(FRAME:slc(acc.imod#7)#4.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 39895 -attr oid 382 -attr @path {/sobel/sobel:core/reg(FRAME:slc(acc.imod#7)#4.itm#1)}
+load net {acc.imod#7.sva(5)} -pin  "reg(FRAME:slc(acc.imod#7)#4.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#7.sva).itm}
+load net {GND} -pin  "reg(FRAME:slc(acc.imod#7)#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(FRAME:slc(acc.imod#7)#4.itm#1)" {clk} -attr xrf 39896 -attr oid 383 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(acc.imod#7)#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(acc.imod#7)#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(acc.imod#7)#4.itm#1} -pin  "reg(FRAME:slc(acc.imod#7)#4.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:slc(acc.imod#7)#4.itm#1}
+load inst "reg(blue:slc(blue#2.sg1)#12.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 39897 -attr oid 384 -attr @path {/sobel/sobel:core/reg(blue:slc(blue#2.sg1)#12.itm#1)}
+load net {ACC2-3:acc#3.itm(15)} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva).itm}
+load net {GND} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {clk} -attr xrf 39898 -attr oid 385 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "reg(blue:slc(blue#2.sg1)#12.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/blue:slc(blue#2.sg1)#12.itm#1}
+load inst "FRAME:mul#2" "mul(2,0,9,0,11)" "INTERFACE" -attr xrf 39899 -attr oid 386 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC2-3:acc#2.itm(13)} -pin  "FRAME:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#10.itm}
+load net {ACC2-3:acc#2.itm(14)} -pin  "FRAME:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#10.itm}
+load net {PWR} -pin  "FRAME:mul#2" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul#2" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul#2" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul#2.itm(0)} -pin  "FRAME:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(1)} -pin  "FRAME:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(2)} -pin  "FRAME:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(3)} -pin  "FRAME:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(4)} -pin  "FRAME:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(5)} -pin  "FRAME:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(6)} -pin  "FRAME:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(7)} -pin  "FRAME:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(8)} -pin  "FRAME:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(9)} -pin  "FRAME:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(10)} -pin  "FRAME:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load inst "reg(FRAME:mul#2.itm#1)" "reg(11,1,1,-1,0)" "INTERFACE" -attr xrf 39900 -attr oid 387 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#2.itm#1)}
+load net {FRAME:mul#2.itm(0)} -pin  "reg(FRAME:mul#2.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(1)} -pin  "reg(FRAME:mul#2.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(2)} -pin  "reg(FRAME:mul#2.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(3)} -pin  "reg(FRAME:mul#2.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(4)} -pin  "reg(FRAME:mul#2.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(5)} -pin  "reg(FRAME:mul#2.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(6)} -pin  "reg(FRAME:mul#2.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(7)} -pin  "reg(FRAME:mul#2.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(8)} -pin  "reg(FRAME:mul#2.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(9)} -pin  "reg(FRAME:mul#2.itm#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {FRAME:mul#2.itm(10)} -pin  "reg(FRAME:mul#2.itm#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_11}
+load net {GND} -pin  "reg(FRAME:mul#2.itm#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_11}
+load net {clk} -pin  "reg(FRAME:mul#2.itm#1)" {clk} -attr xrf 39901 -attr oid 388 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#2.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#2.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#2.itm#1(0)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(1)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(2)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(3)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(4)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(5)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(6)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(7)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(8)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(9)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load net {FRAME:mul#2.itm#1(10)} -pin  "reg(FRAME:mul#2.itm#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#2.itm#1}
+load inst "FRAME:mul#3" "mul(3,0,6,0,9)" "INTERFACE" -attr xrf 39902 -attr oid 389 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(3,0,6,0,9)"
+load net {ACC2-3:acc#2.itm(10)} -pin  "FRAME:mul#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {ACC2-3:acc#2.itm(11)} -pin  "FRAME:mul#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {ACC2-3:acc#2.itm(12)} -pin  "FRAME:mul#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#11.itm}
+load net {PWR} -pin  "FRAME:mul#3" {B(0)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#3" {B(1)} -attr @path {/sobel/sobel:core/C57_6}
+load net {GND} -pin  "FRAME:mul#3" {B(2)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(3)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(4)} -attr @path {/sobel/sobel:core/C57_6}
+load net {PWR} -pin  "FRAME:mul#3" {B(5)} -attr @path {/sobel/sobel:core/C57_6}
+load net {FRAME:mul#3.itm(0)} -pin  "FRAME:mul#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "FRAME:mul#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "FRAME:mul#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "FRAME:mul#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "FRAME:mul#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "FRAME:mul#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "FRAME:mul#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "FRAME:mul#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "FRAME:mul#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load inst "reg(FRAME:mul#3.itm#1)" "reg(9,1,1,-1,0)" "INTERFACE" -attr xrf 39903 -attr oid 390 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:mul#3.itm#1)}
+load net {FRAME:mul#3.itm(0)} -pin  "reg(FRAME:mul#3.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(1)} -pin  "reg(FRAME:mul#3.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(2)} -pin  "reg(FRAME:mul#3.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(3)} -pin  "reg(FRAME:mul#3.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(4)} -pin  "reg(FRAME:mul#3.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(5)} -pin  "reg(FRAME:mul#3.itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(6)} -pin  "reg(FRAME:mul#3.itm#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(7)} -pin  "reg(FRAME:mul#3.itm#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {FRAME:mul#3.itm(8)} -pin  "reg(FRAME:mul#3.itm#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_9}
+load net {GND} -pin  "reg(FRAME:mul#3.itm#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_9}
+load net {clk} -pin  "reg(FRAME:mul#3.itm#1)" {clk} -attr xrf 39904 -attr oid 391 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:mul#3.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:mul#3.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:mul#3.itm#1(0)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(1)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(2)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(3)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(4)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(5)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(6)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(7)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(8)} -pin  "reg(FRAME:mul#3.itm#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load inst "reg(green:slc(green#2.sg1).itm#1)" "reg(6,1,1,-1,0)" "INTERFACE" -attr xrf 39905 -attr oid 392 -attr vt d -attr @path {/sobel/sobel:core/reg(green:slc(green#2.sg1).itm#1)}
+load net {ACC2-3:acc#2.itm(4)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#2.itm(5)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#2.itm(6)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#2.itm(7)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#2.itm(8)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#2.itm(9)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#2.itm}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_6}
+load net {GND} -pin  "reg(green:slc(green#2.sg1).itm#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_6}
+load net {clk} -pin  "reg(green:slc(green#2.sg1).itm#1)" {clk} -attr xrf 39906 -attr oid 393 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(green:slc(green#2.sg1).itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {green:slc(green#2.sg1).itm#1(0)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(1)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(2)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(3)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(4)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(5)} -pin  "reg(green:slc(green#2.sg1).itm#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load inst "FRAME:not#15" "not(1)" "INTERFACE" -attr xrf 39907 -attr oid 394 -attr @path {/sobel/sobel:core/FRAME:not#15} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#5.sva(5)} -pin  "FRAME:not#15" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#5.sva)#6.itm}
+load net {FRAME:not#15.itm} -pin  "FRAME:not#15" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#15.itm}
+load inst "FRAME:not#13" "not(3)" "INTERFACE" -attr xrf 39908 -attr oid 395 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {acc.imod#5.sva(3)} -pin  "FRAME:not#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#5.sva)#2.itm}
+load net {acc.imod#5.sva(4)} -pin  "FRAME:not#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#5.sva)#2.itm}
+load net {acc.imod#5.sva(5)} -pin  "FRAME:not#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#5.sva)#2.itm}
+load net {FRAME:not#13.itm(0)} -pin  "FRAME:not#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {FRAME:not#13.itm(1)} -pin  "FRAME:not#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load net {FRAME:not#13.itm(2)} -pin  "FRAME:not#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#13.itm}
+load inst "FRAME:not#12" "not(1)" "INTERFACE" -attr xrf 39909 -attr oid 396 -attr @path {/sobel/sobel:core/FRAME:not#12} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {acc.imod#5.sva(5)} -pin  "FRAME:not#12" {A(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#5.sva)#3.itm}
+load net {FRAME:not#12.itm} -pin  "FRAME:not#12" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#12.itm}
+load inst "FRAME:acc#23" "add(5,-1,4,0,5)" "INTERFACE" -attr xrf 39910 -attr oid 397 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {PWR} -pin  "FRAME:acc#23" {A(0)} -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {acc.imod#5.sva(0)} -pin  "FRAME:acc#23" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {acc.imod#5.sva(1)} -pin  "FRAME:acc#23" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {acc.imod#5.sva(2)} -pin  "FRAME:acc#23" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {PWR} -pin  "FRAME:acc#23" {A(4)} -attr @path {/sobel/sobel:core/conc#146.itm}
+load net {FRAME:not#12.itm} -pin  "FRAME:acc#23" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(0)} -pin  "FRAME:acc#23" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(1)} -pin  "FRAME:acc#23" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:not#13.itm(2)} -pin  "FRAME:acc#23" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:conc#25.itm}
+load net {FRAME:acc#23.itm(0)} -pin  "FRAME:acc#23" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(1)} -pin  "FRAME:acc#23" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(2)} -pin  "FRAME:acc#23" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(3)} -pin  "FRAME:acc#23" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load net {FRAME:acc#23.itm(4)} -pin  "FRAME:acc#23" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#23.itm}
+load inst "FRAME:not#43" "not(1)" "INTERFACE" -attr xrf 39911 -attr oid 398 -attr @path {/sobel/sobel:core/FRAME:not#43} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc#23.itm(4)} -pin  "FRAME:not#43" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#5.itm}
+load net {FRAME:not#43.itm} -pin  "FRAME:not#43" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#43.itm}
+load inst "FRAME:acc#17" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 39912 -attr oid 399 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#43.itm} -pin  "FRAME:acc#17" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {PWR} -pin  "FRAME:acc#17" {A(1)} -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {FRAME:not#15.itm} -pin  "FRAME:acc#17" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#145.itm}
+load net {acc.imod#5.sva(3)} -pin  "FRAME:acc#17" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#5.sva)#4.itm}
+load net {acc.imod#5.sva(4)} -pin  "FRAME:acc#17" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(acc.imod#5.sva)#4.itm}
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:acc#17" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:acc#17" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load inst "FRAME:not#14" "not(3)" "INTERFACE" -attr xrf 39913 -attr oid 400 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#2.itm(7)} -pin  "FRAME:not#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {ACC2-3:acc#2.itm(8)} -pin  "FRAME:not#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {ACC2-3:acc#2.itm(9)} -pin  "FRAME:not#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#9.itm}
+load net {FRAME:not#14.itm(0)} -pin  "FRAME:not#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(1)} -pin  "FRAME:not#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(2)} -pin  "FRAME:not#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load inst "FRAME:acc#18" "add(4,0,3,0,5)" "INTERFACE" -attr xrf 39914 -attr oid 401 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#17.itm(0)} -pin  "FRAME:acc#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(1)} -pin  "FRAME:acc#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(2)} -pin  "FRAME:acc#18" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:acc#17.itm(3)} -pin  "FRAME:acc#18" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#17.itm}
+load net {FRAME:not#14.itm(0)} -pin  "FRAME:acc#18" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(1)} -pin  "FRAME:acc#18" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:not#14.itm(2)} -pin  "FRAME:acc#18" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#14.itm}
+load net {FRAME:acc#18.itm(0)} -pin  "FRAME:acc#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(1)} -pin  "FRAME:acc#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(2)} -pin  "FRAME:acc#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(3)} -pin  "FRAME:acc#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(4)} -pin  "FRAME:acc#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load inst "reg(FRAME:acc#18.itm#1)" "reg(5,1,1,-1,0)" "INTERFACE" -attr xrf 39915 -attr oid 402 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:acc#18.itm#1)}
+load net {FRAME:acc#18.itm(0)} -pin  "reg(FRAME:acc#18.itm#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(1)} -pin  "reg(FRAME:acc#18.itm#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(2)} -pin  "reg(FRAME:acc#18.itm#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(3)} -pin  "reg(FRAME:acc#18.itm#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {FRAME:acc#18.itm(4)} -pin  "reg(FRAME:acc#18.itm#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_5}
+load net {GND} -pin  "reg(FRAME:acc#18.itm#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_5}
+load net {clk} -pin  "reg(FRAME:acc#18.itm#1)" {clk} -attr xrf 39916 -attr oid 403 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:acc#18.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:acc#18.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:acc#18.itm#1(0)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(1)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(2)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(3)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(4)} -pin  "reg(FRAME:acc#18.itm#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load inst "reg(FRAME:slc(acc.imod#5)#4.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 39917 -attr oid 404 -attr @path {/sobel/sobel:core/reg(FRAME:slc(acc.imod#5)#4.itm#1)}
+load net {acc.imod#5.sva(5)} -pin  "reg(FRAME:slc(acc.imod#5)#4.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(acc.imod#5.sva).itm}
+load net {GND} -pin  "reg(FRAME:slc(acc.imod#5)#4.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(FRAME:slc(acc.imod#5)#4.itm#1)" {clk} -attr xrf 39918 -attr oid 405 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:slc(acc.imod#5)#4.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:slc(acc.imod#5)#4.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:slc(acc.imod#5)#4.itm#1} -pin  "reg(FRAME:slc(acc.imod#5)#4.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:slc(acc.imod#5)#4.itm#1}
+load inst "reg(green:slc(green#2.sg1)#12.itm#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 39919 -attr oid 406 -attr @path {/sobel/sobel:core/reg(green:slc(green#2.sg1)#12.itm#1)}
+load net {ACC2-3:acc#2.itm(15)} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {D(0)} -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva).itm}
+load net {GND} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {clk} -attr xrf 39920 -attr oid 407 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {green:slc(green#2.sg1)#12.itm#1} -pin  "reg(green:slc(green#2.sg1)#12.itm#1)" {Z(0)} -attr @path {/sobel/sobel:core/green:slc(green#2.sg1)#12.itm#1}
+load inst "FRAME:for#1:not#7" "not(1)" "INTERFACE" -attr xrf 39921 -attr oid 408 -attr @path {/sobel/sobel:core/FRAME:for#1:not#7} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for#1:acc.itm(1)} -pin  "FRAME:for#1:not#7" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:slc.itm}
+load net {FRAME:for#1:not#7.itm} -pin  "FRAME:for#1:not#7" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#7.itm}
+load inst "reg(exit:FRAME:for#1.sva#2.st#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 39922 -attr oid 409 -attr @path {/sobel/sobel:core/reg(exit:FRAME:for#1.sva#2.st#1)}
+load net {FRAME:for#1:not#7.itm} -pin  "reg(exit:FRAME:for#1.sva#2.st#1)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#7.itm}
+load net {GND} -pin  "reg(exit:FRAME:for#1.sva#2.st#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME:for#1.sva#2.st#1)" {clk} -attr xrf 39923 -attr oid 410 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for#1.sva#2.st#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for#1.sva#2.st#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for#1.sva#2.st#1} -pin  "reg(exit:FRAME:for#1.sva#2.st#1)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.sva#2.st#1}
+load inst "reg(exit:FRAME:for.lpi#1.dfm.st#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 39924 -attr oid 411 -attr @path {/sobel/sobel:core/reg(exit:FRAME:for.lpi#1.dfm.st#1)}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "reg(exit:FRAME:for.lpi#1.dfm.st#1)" {D(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {GND} -pin  "reg(exit:FRAME:for.lpi#1.dfm.st#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME:for.lpi#1.dfm.st#1)" {clk} -attr xrf 39925 -attr oid 412 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for.lpi#1.dfm.st#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for.lpi#1.dfm.st#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for.lpi#1.dfm.st#1} -pin  "reg(exit:FRAME:for.lpi#1.dfm.st#1)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm.st#1}
+load inst "FRAME:for:and#13" "and(2,2)" "INTERFACE" -attr xrf 39926 -attr oid 413 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#13} -attr area 1.459665 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2)"
+load net {i#7.lpi#1(0)} -pin  "FRAME:for:and#13" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "FRAME:for:and#13" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:and#13" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#30.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:and#13" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#30.itm}
+load net {FRAME:for:and#13.itm(0)} -pin  "FRAME:for:and#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#13.itm}
+load net {FRAME:for:and#13.itm(1)} -pin  "FRAME:for:and#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#13.itm}
+load inst "mux#1" "mux(2,2)" "INTERFACE" -attr xrf 39927 -attr oid 414 -attr vt d -attr @path {/sobel/sobel:core/mux#1} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {FRAME:for:and#13.itm(0)} -pin  "mux#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#13.itm}
+load net {FRAME:for:and#13.itm(1)} -pin  "mux#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#13.itm}
+load net {i#7.sva(0)} -pin  "mux#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load net {i#7.sva(1)} -pin  "mux#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load net {or#4.cse} -pin  "mux#1" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#1.itm(0)} -pin  "mux#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(1)} -pin  "mux#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load inst "reg(i#7.lpi#1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 39928 -attr oid 415 -attr vt d -attr @path {/sobel/sobel:core/reg(i#7.lpi#1)}
+load net {mux#1.itm(0)} -pin  "reg(i#7.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {mux#1.itm(1)} -pin  "reg(i#7.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#1.itm}
+load net {GND} -pin  "reg(i#7.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(i#7.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(i#7.lpi#1)" {clk} -attr xrf 39929 -attr oid 416 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(i#7.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(i#7.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {i#7.lpi#1(0)} -pin  "reg(i#7.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "reg(i#7.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load inst "FRAME:for:not" "not(1)" "INTERFACE" -attr xrf 39930 -attr oid 417 -attr @path {/sobel/sobel:core/FRAME:for:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:not" {A(0)} -attr @path {/sobel/sobel:core/xor_cse#2}
+load net {FRAME:for:not.itm} -pin  "FRAME:for:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load inst "mux#2" "mux(2,1)" "INTERFACE" -attr xrf 39931 -attr oid 418 -attr @path {/sobel/sobel:core/mux#2} -attr area 0.920423 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2)"
+load net {FRAME:for:not.itm} -pin  "mux#2" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not.itm}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "mux#2" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {or#4.cse} -pin  "mux#2" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#2.itm} -pin  "mux#2" {Z(0)} -attr @path {/sobel/sobel:core/mux#2.itm}
+load inst "reg(exit:FRAME:for.lpi#1)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 39932 -attr oid 419 -attr @path {/sobel/sobel:core/reg(exit:FRAME:for.lpi#1)}
+load net {mux#2.itm} -pin  "reg(exit:FRAME:for.lpi#1)" {D(0)} -attr @path {/sobel/sobel:core/mux#2.itm}
+load net {GND} -pin  "reg(exit:FRAME:for.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME:for.lpi#1)" {clk} -attr xrf 39933 -attr oid 420 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for.lpi#1} -pin  "reg(exit:FRAME:for.lpi#1)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1}
+load inst "reg(exit:FRAME:for#1.lpi#1.dfm#4)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 39934 -attr oid 421 -attr @path {/sobel/sobel:core/reg(exit:FRAME:for#1.lpi#1.dfm#4)}
+load net {exit:FRAME:for#1.lpi#1.dfm#4:mx0} -pin  "reg(exit:FRAME:for#1.lpi#1.dfm#4)" {D(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4:mx0}
+load net {GND} -pin  "reg(exit:FRAME:for#1.lpi#1.dfm#4)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME:for#1.lpi#1.dfm#4)" {clk} -attr xrf 39935 -attr oid 422 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME:for#1.lpi#1.dfm#4)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME:for#1.lpi#1.dfm#4)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME:for#1.lpi#1.dfm#4} -pin  "reg(exit:FRAME:for#1.lpi#1.dfm#4)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4}
+load inst "FRAME:and" "and(2,1)" "INTERFACE" -attr xrf 39936 -attr oid 423 -attr @path {/sobel/sobel:core/FRAME:and} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {exit:FRAME:for#1.lpi#1.dfm#4:mx0} -pin  "FRAME:and" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4:mx0}
+load net {exit:FRAME.lpi#1.dfm#2:mx0} -pin  "FRAME:and" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#2:mx0}
+load net {FRAME:and.itm} -pin  "FRAME:and" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load inst "reg(exit:FRAME#1.sva)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 39937 -attr oid 424 -attr @path {/sobel/sobel:core/reg(exit:FRAME#1.sva)}
+load net {FRAME:and.itm} -pin  "reg(exit:FRAME#1.sva)" {D(0)} -attr @path {/sobel/sobel:core/FRAME:and.itm}
+load net {PWR} -pin  "reg(exit:FRAME#1.sva)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1#1_Not}
+load net {clk} -pin  "reg(exit:FRAME#1.sva)" {clk} -attr xrf 39938 -attr oid 425 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME#1.sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME#1.sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME#1.sva} -pin  "reg(exit:FRAME#1.sva)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load inst "reg(main.stage_0#2)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 39939 -attr oid 426 -attr @path {/sobel/sobel:core/reg(main.stage_0#2)}
+load net {PWR} -pin  "reg(main.stage_0#2)" {D(0)} -attr @path {/sobel/sobel:core/Cn1_1#4}
+load net {GND} -pin  "reg(main.stage_0#2)" {DRa(0)} -attr @path {/sobel/sobel:core/Cn2_2#8}
+load net {clk} -pin  "reg(main.stage_0#2)" {clk} -attr xrf 39940 -attr oid 427 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(main.stage_0#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(main.stage_0#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {main.stage_0#2} -pin  "reg(main.stage_0#2)" {Z(0)} -attr @path {/sobel/sobel:core/main.stage_0#2}
+load inst "reg(regs.regs(2).lpi#1.dfm)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 39941 -attr oid 428 -attr vt dc -attr @path {/sobel/sobel:core/reg(regs.regs(2).lpi#1.dfm)}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(19)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(20)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(21)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(22)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(23)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(24)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(25)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(26)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(27)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(28)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(29)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(30)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(31)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(32)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(33)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(34)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(35)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(36)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(37)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(38)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(39)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(40)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(41)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(42)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(43)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(44)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(45)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(46)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(47)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(48)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(49)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(50)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(51)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(52)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(53)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(54)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(55)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(56)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(57)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(58)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(59)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(60)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(61)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(62)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(63)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(64)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(65)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(66)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(67)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(68)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(69)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(70)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(71)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(72)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(73)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(74)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(75)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(76)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(77)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(78)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(79)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(80)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(81)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(82)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(83)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(84)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(85)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(86)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(87)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(88)} -attr @path {/sobel/sobel:core/C0_90}
+load net {GND} -pin  "reg(regs.regs(2).lpi#1.dfm)" {DRa(89)} -attr @path {/sobel/sobel:core/C0_90}
+load net {clk} -pin  "reg(regs.regs(2).lpi#1.dfm)" {clk} -attr xrf 39942 -attr oid 429 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(2).lpi#1.dfm)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(2).lpi#1.dfm(0)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(1)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(2)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(3)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(4)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(5)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(6)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(7)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(8)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(9)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(10)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(11)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(12)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(13)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(14)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(15)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(16)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(16)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(17)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(17)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(18)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(18)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(19)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(19)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(20)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(20)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(21)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(21)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(22)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(22)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(23)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(23)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(24)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(24)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(25)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(25)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(26)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(26)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(27)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(27)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(28)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(28)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(29)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(29)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(30)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(30)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(31)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(31)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(32)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(32)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(33)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(33)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(34)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(34)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(35)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(35)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(36)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(36)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(37)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(37)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(38)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(38)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(39)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(39)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(40)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(40)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(41)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(41)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(42)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(42)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(43)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(43)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(44)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(44)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(45)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(45)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(46)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(46)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(47)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(47)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(48)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(48)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(49)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(49)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(50)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(50)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(51)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(51)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(52)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(52)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(53)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(53)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(54)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(54)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(55)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(55)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(56)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(56)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(57)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(57)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(58)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(58)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(59)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(59)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(60)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(60)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(61)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(61)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(62)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(62)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(63)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(63)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(64)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(64)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(65)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(65)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(66)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(66)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(67)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(67)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(68)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(68)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(69)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(69)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(70)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(70)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(71)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(71)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(72)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(72)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(73)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(73)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(74)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(74)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(75)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(75)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(76)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(76)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(77)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(77)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(78)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(78)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(79)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(79)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(80)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(80)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(81)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(81)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(82)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(82)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(83)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(83)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(84)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(84)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(85)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(85)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(86)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(86)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(87)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(87)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(88)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(88)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(89)} -pin  "reg(regs.regs(2).lpi#1.dfm)" {Z(89)} -attr vt dc -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load inst "reg(regs.regs(1).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 39943 -attr oid 430 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(1).sva)}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "reg(regs.regs(1).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "reg(regs.regs(1).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "reg(regs.regs(1).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "reg(regs.regs(1).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "reg(regs.regs(1).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "reg(regs.regs(1).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "reg(regs.regs(1).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "reg(regs.regs(1).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "reg(regs.regs(1).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "reg(regs.regs(1).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "reg(regs.regs(1).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "reg(regs.regs(1).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "reg(regs.regs(1).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "reg(regs.regs(1).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "reg(regs.regs(1).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "reg(regs.regs(1).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "reg(regs.regs(1).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "reg(regs.regs(1).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "reg(regs.regs(1).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "reg(regs.regs(1).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "reg(regs.regs(1).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "reg(regs.regs(1).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "reg(regs.regs(1).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "reg(regs.regs(1).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "reg(regs.regs(1).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "reg(regs.regs(1).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "reg(regs.regs(1).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "reg(regs.regs(1).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "reg(regs.regs(1).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "reg(regs.regs(1).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "reg(regs.regs(1).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "reg(regs.regs(1).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "reg(regs.regs(1).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "reg(regs.regs(1).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "reg(regs.regs(1).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "reg(regs.regs(1).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "reg(regs.regs(1).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "reg(regs.regs(1).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "reg(regs.regs(1).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "reg(regs.regs(1).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "reg(regs.regs(1).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "reg(regs.regs(1).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "reg(regs.regs(1).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "reg(regs.regs(1).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "reg(regs.regs(1).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "reg(regs.regs(1).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "reg(regs.regs(1).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "reg(regs.regs(1).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "reg(regs.regs(1).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "reg(regs.regs(1).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "reg(regs.regs(1).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "reg(regs.regs(1).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "reg(regs.regs(1).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "reg(regs.regs(1).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "reg(regs.regs(1).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "reg(regs.regs(1).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "reg(regs.regs(1).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "reg(regs.regs(1).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "reg(regs.regs(1).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "reg(regs.regs(1).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "reg(regs.regs(1).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "reg(regs.regs(1).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "reg(regs.regs(1).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "reg(regs.regs(1).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "reg(regs.regs(1).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "reg(regs.regs(1).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "reg(regs.regs(1).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "reg(regs.regs(1).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "reg(regs.regs(1).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "reg(regs.regs(1).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "reg(regs.regs(1).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "reg(regs.regs(1).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "reg(regs.regs(1).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "reg(regs.regs(1).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "reg(regs.regs(1).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "reg(regs.regs(1).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "reg(regs.regs(1).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "reg(regs.regs(1).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "reg(regs.regs(1).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "reg(regs.regs(1).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "reg(regs.regs(1).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "reg(regs.regs(1).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "reg(regs.regs(1).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "reg(regs.regs(1).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "reg(regs.regs(1).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "reg(regs.regs(1).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "reg(regs.regs(1).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "reg(regs.regs(1).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "reg(regs.regs(1).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "reg(regs.regs(1).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {GND} -pin  "reg(regs.regs(1).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#2}
+load net {clk} -pin  "reg(regs.regs(1).sva)" {clk} -attr xrf 39944 -attr oid 431 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(1).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(1).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(1).sva(0)} -pin  "reg(regs.regs(1).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "reg(regs.regs(1).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "reg(regs.regs(1).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "reg(regs.regs(1).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "reg(regs.regs(1).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "reg(regs.regs(1).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "reg(regs.regs(1).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "reg(regs.regs(1).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "reg(regs.regs(1).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "reg(regs.regs(1).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "reg(regs.regs(1).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "reg(regs.regs(1).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "reg(regs.regs(1).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "reg(regs.regs(1).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "reg(regs.regs(1).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "reg(regs.regs(1).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "reg(regs.regs(1).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "reg(regs.regs(1).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "reg(regs.regs(1).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "reg(regs.regs(1).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "reg(regs.regs(1).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "reg(regs.regs(1).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "reg(regs.regs(1).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "reg(regs.regs(1).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "reg(regs.regs(1).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "reg(regs.regs(1).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "reg(regs.regs(1).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "reg(regs.regs(1).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "reg(regs.regs(1).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "reg(regs.regs(1).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "reg(regs.regs(1).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "reg(regs.regs(1).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "reg(regs.regs(1).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "reg(regs.regs(1).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "reg(regs.regs(1).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "reg(regs.regs(1).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "reg(regs.regs(1).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "reg(regs.regs(1).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "reg(regs.regs(1).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "reg(regs.regs(1).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "reg(regs.regs(1).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "reg(regs.regs(1).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "reg(regs.regs(1).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "reg(regs.regs(1).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "reg(regs.regs(1).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "reg(regs.regs(1).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "reg(regs.regs(1).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "reg(regs.regs(1).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "reg(regs.regs(1).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "reg(regs.regs(1).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "reg(regs.regs(1).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "reg(regs.regs(1).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "reg(regs.regs(1).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "reg(regs.regs(1).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "reg(regs.regs(1).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "reg(regs.regs(1).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "reg(regs.regs(1).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "reg(regs.regs(1).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "reg(regs.regs(1).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "reg(regs.regs(1).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "reg(regs.regs(1).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "reg(regs.regs(1).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "reg(regs.regs(1).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "reg(regs.regs(1).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "reg(regs.regs(1).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "reg(regs.regs(1).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "reg(regs.regs(1).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "reg(regs.regs(1).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "reg(regs.regs(1).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "reg(regs.regs(1).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "reg(regs.regs(1).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "reg(regs.regs(1).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "reg(regs.regs(1).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "reg(regs.regs(1).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "reg(regs.regs(1).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "reg(regs.regs(1).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "reg(regs.regs(1).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "reg(regs.regs(1).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "reg(regs.regs(1).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "reg(regs.regs(1).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "reg(regs.regs(1).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "reg(regs.regs(1).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "reg(regs.regs(1).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "reg(regs.regs(1).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "reg(regs.regs(1).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "reg(regs.regs(1).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "reg(regs.regs(1).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "reg(regs.regs(1).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "reg(regs.regs(1).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "reg(regs.regs(1).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load inst "reg(regs.regs(0).sva)" "reg(90,1,1,-1,0)" "INTERFACE" -attr xrf 39945 -attr oid 432 -attr vt d -attr @path {/sobel/sobel:core/reg(regs.regs(0).sva)}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "reg(regs.regs(0).sva)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "reg(regs.regs(0).sva)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "reg(regs.regs(0).sva)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "reg(regs.regs(0).sva)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "reg(regs.regs(0).sva)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "reg(regs.regs(0).sva)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "reg(regs.regs(0).sva)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "reg(regs.regs(0).sva)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "reg(regs.regs(0).sva)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "reg(regs.regs(0).sva)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "reg(regs.regs(0).sva)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "reg(regs.regs(0).sva)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "reg(regs.regs(0).sva)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "reg(regs.regs(0).sva)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "reg(regs.regs(0).sva)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "reg(regs.regs(0).sva)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "reg(regs.regs(0).sva)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "reg(regs.regs(0).sva)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "reg(regs.regs(0).sva)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "reg(regs.regs(0).sva)" {D(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "reg(regs.regs(0).sva)" {D(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "reg(regs.regs(0).sva)" {D(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "reg(regs.regs(0).sva)" {D(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "reg(regs.regs(0).sva)" {D(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "reg(regs.regs(0).sva)" {D(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "reg(regs.regs(0).sva)" {D(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "reg(regs.regs(0).sva)" {D(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "reg(regs.regs(0).sva)" {D(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "reg(regs.regs(0).sva)" {D(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "reg(regs.regs(0).sva)" {D(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "reg(regs.regs(0).sva)" {D(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "reg(regs.regs(0).sva)" {D(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "reg(regs.regs(0).sva)" {D(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "reg(regs.regs(0).sva)" {D(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "reg(regs.regs(0).sva)" {D(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "reg(regs.regs(0).sva)" {D(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "reg(regs.regs(0).sva)" {D(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "reg(regs.regs(0).sva)" {D(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "reg(regs.regs(0).sva)" {D(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "reg(regs.regs(0).sva)" {D(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "reg(regs.regs(0).sva)" {D(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "reg(regs.regs(0).sva)" {D(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "reg(regs.regs(0).sva)" {D(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "reg(regs.regs(0).sva)" {D(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "reg(regs.regs(0).sva)" {D(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "reg(regs.regs(0).sva)" {D(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "reg(regs.regs(0).sva)" {D(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "reg(regs.regs(0).sva)" {D(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "reg(regs.regs(0).sva)" {D(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "reg(regs.regs(0).sva)" {D(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "reg(regs.regs(0).sva)" {D(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "reg(regs.regs(0).sva)" {D(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "reg(regs.regs(0).sva)" {D(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "reg(regs.regs(0).sva)" {D(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "reg(regs.regs(0).sva)" {D(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "reg(regs.regs(0).sva)" {D(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "reg(regs.regs(0).sva)" {D(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "reg(regs.regs(0).sva)" {D(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "reg(regs.regs(0).sva)" {D(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "reg(regs.regs(0).sva)" {D(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "reg(regs.regs(0).sva)" {D(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "reg(regs.regs(0).sva)" {D(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "reg(regs.regs(0).sva)" {D(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "reg(regs.regs(0).sva)" {D(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "reg(regs.regs(0).sva)" {D(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "reg(regs.regs(0).sva)" {D(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "reg(regs.regs(0).sva)" {D(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "reg(regs.regs(0).sva)" {D(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "reg(regs.regs(0).sva)" {D(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "reg(regs.regs(0).sva)" {D(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "reg(regs.regs(0).sva)" {D(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "reg(regs.regs(0).sva)" {D(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "reg(regs.regs(0).sva)" {D(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "reg(regs.regs(0).sva)" {D(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "reg(regs.regs(0).sva)" {D(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "reg(regs.regs(0).sva)" {D(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "reg(regs.regs(0).sva)" {D(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "reg(regs.regs(0).sva)" {D(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "reg(regs.regs(0).sva)" {D(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "reg(regs.regs(0).sva)" {D(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "reg(regs.regs(0).sva)" {D(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "reg(regs.regs(0).sva)" {D(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "reg(regs.regs(0).sva)" {D(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "reg(regs.regs(0).sva)" {D(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "reg(regs.regs(0).sva)" {D(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "reg(regs.regs(0).sva)" {D(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "reg(regs.regs(0).sva)" {D(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "reg(regs.regs(0).sva)" {D(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "reg(regs.regs(0).sva)" {D(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "reg(regs.regs(0).sva)" {D(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(0)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(1)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(2)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(3)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(4)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(5)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(6)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(7)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(8)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(9)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(10)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(11)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(12)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(13)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(14)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(15)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(16)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(17)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(18)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(19)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(20)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(21)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(22)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(23)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(24)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(25)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(26)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(27)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(28)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(29)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(30)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(31)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(32)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(33)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(34)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(35)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(36)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(37)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(38)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(39)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(40)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(41)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(42)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(43)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(44)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(45)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(46)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(47)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(48)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(49)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(50)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(51)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(52)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(53)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(54)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(55)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(56)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(57)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(58)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(59)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(60)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(61)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(62)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(63)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(64)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(65)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(66)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(67)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(68)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(69)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(70)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(71)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(72)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(73)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(74)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(75)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(76)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(77)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(78)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(79)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(80)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(81)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(82)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(83)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(84)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(85)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(86)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(87)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(88)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {GND} -pin  "reg(regs.regs(0).sva)" {DRa(89)} -attr @path {/sobel/sobel:core/regs.regs_decl#3}
+load net {clk} -pin  "reg(regs.regs(0).sva)" {clk} -attr xrf 39946 -attr oid 433 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(regs.regs(0).sva)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(regs.regs(0).sva)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {regs.regs(0).sva(0)} -pin  "reg(regs.regs(0).sva)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "reg(regs.regs(0).sva)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "reg(regs.regs(0).sva)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "reg(regs.regs(0).sva)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "reg(regs.regs(0).sva)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "reg(regs.regs(0).sva)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "reg(regs.regs(0).sva)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "reg(regs.regs(0).sva)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "reg(regs.regs(0).sva)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "reg(regs.regs(0).sva)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "reg(regs.regs(0).sva)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "reg(regs.regs(0).sva)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "reg(regs.regs(0).sva)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "reg(regs.regs(0).sva)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "reg(regs.regs(0).sva)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "reg(regs.regs(0).sva)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "reg(regs.regs(0).sva)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "reg(regs.regs(0).sva)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "reg(regs.regs(0).sva)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "reg(regs.regs(0).sva)" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "reg(regs.regs(0).sva)" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "reg(regs.regs(0).sva)" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "reg(regs.regs(0).sva)" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "reg(regs.regs(0).sva)" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "reg(regs.regs(0).sva)" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "reg(regs.regs(0).sva)" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "reg(regs.regs(0).sva)" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "reg(regs.regs(0).sva)" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "reg(regs.regs(0).sva)" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "reg(regs.regs(0).sva)" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "reg(regs.regs(0).sva)" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "reg(regs.regs(0).sva)" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "reg(regs.regs(0).sva)" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "reg(regs.regs(0).sva)" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "reg(regs.regs(0).sva)" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "reg(regs.regs(0).sva)" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "reg(regs.regs(0).sva)" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "reg(regs.regs(0).sva)" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "reg(regs.regs(0).sva)" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "reg(regs.regs(0).sva)" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "reg(regs.regs(0).sva)" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "reg(regs.regs(0).sva)" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "reg(regs.regs(0).sva)" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "reg(regs.regs(0).sva)" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "reg(regs.regs(0).sva)" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "reg(regs.regs(0).sva)" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "reg(regs.regs(0).sva)" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "reg(regs.regs(0).sva)" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "reg(regs.regs(0).sva)" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "reg(regs.regs(0).sva)" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "reg(regs.regs(0).sva)" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "reg(regs.regs(0).sva)" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "reg(regs.regs(0).sva)" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "reg(regs.regs(0).sva)" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "reg(regs.regs(0).sva)" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "reg(regs.regs(0).sva)" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "reg(regs.regs(0).sva)" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "reg(regs.regs(0).sva)" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "reg(regs.regs(0).sva)" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "reg(regs.regs(0).sva)" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "reg(regs.regs(0).sva)" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "reg(regs.regs(0).sva)" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "reg(regs.regs(0).sva)" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "reg(regs.regs(0).sva)" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "reg(regs.regs(0).sva)" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "reg(regs.regs(0).sva)" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "reg(regs.regs(0).sva)" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "reg(regs.regs(0).sva)" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "reg(regs.regs(0).sva)" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "reg(regs.regs(0).sva)" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "reg(regs.regs(0).sva)" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "reg(regs.regs(0).sva)" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "reg(regs.regs(0).sva)" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "reg(regs.regs(0).sva)" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "reg(regs.regs(0).sva)" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "reg(regs.regs(0).sva)" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "reg(regs.regs(0).sva)" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "reg(regs.regs(0).sva)" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "reg(regs.regs(0).sva)" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "reg(regs.regs(0).sva)" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "reg(regs.regs(0).sva)" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "reg(regs.regs(0).sva)" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "reg(regs.regs(0).sva)" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "reg(regs.regs(0).sva)" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "reg(regs.regs(0).sva)" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "reg(regs.regs(0).sva)" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "reg(regs.regs(0).sva)" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "reg(regs.regs(0).sva)" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "reg(regs.regs(0).sva)" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "reg(regs.regs(0).sva)" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load inst "reg(exit:FRAME.lpi#1.dfm#2)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 39947 -attr oid 434 -attr @path {/sobel/sobel:core/reg(exit:FRAME.lpi#1.dfm#2)}
+load net {exit:FRAME.lpi#1.dfm#2:mx0} -pin  "reg(exit:FRAME.lpi#1.dfm#2)" {D(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#2:mx0}
+load net {GND} -pin  "reg(exit:FRAME.lpi#1.dfm#2)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_1}
+load net {clk} -pin  "reg(exit:FRAME.lpi#1.dfm#2)" {clk} -attr xrf 39948 -attr oid 435 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(exit:FRAME.lpi#1.dfm#2)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(exit:FRAME.lpi#1.dfm#2)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {exit:FRAME.lpi#1.dfm#2} -pin  "reg(exit:FRAME.lpi#1.dfm#2)" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#2}
+load inst "regs.operator[]#11:mux" "mux(4,10)" "INTERFACE" -attr xrf 39949 -attr oid 436 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#11:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "regs.operator[]#11:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "regs.operator[]#11:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "regs.operator[]#11:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "regs.operator[]#11:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "regs.operator[]#11:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "regs.operator[]#11:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "regs.operator[]#11:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "regs.operator[]#11:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "regs.operator[]#11:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "regs.operator[]#11:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "regs.operator[]#11:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "regs.operator[]#11:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "regs.operator[]#11:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "regs.operator[]#11:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "regs.operator[]#11:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "regs.operator[]#11:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "regs.operator[]#11:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "regs.operator[]#11:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "regs.operator[]#11:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "regs.operator[]#11:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "regs.operator[]#11:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "regs.operator[]#11:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "regs.operator[]#11:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "regs.operator[]#11:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "regs.operator[]#11:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "regs.operator[]#11:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "regs.operator[]#11:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "regs.operator[]#11:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "regs.operator[]#11:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "regs.operator[]#11:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#3.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#11:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#11:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#11:mux.itm(0)} -pin  "regs.operator[]#11:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(1)} -pin  "regs.operator[]#11:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(2)} -pin  "regs.operator[]#11:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(3)} -pin  "regs.operator[]#11:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(4)} -pin  "regs.operator[]#11:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(5)} -pin  "regs.operator[]#11:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(6)} -pin  "regs.operator[]#11:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(7)} -pin  "regs.operator[]#11:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(8)} -pin  "regs.operator[]#11:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(9)} -pin  "regs.operator[]#11:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load inst "FRAME:for:mul#5" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 39950 -attr oid 437 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#11:mux.itm(0)} -pin  "FRAME:for:mul#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(1)} -pin  "FRAME:for:mul#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(2)} -pin  "FRAME:for:mul#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(3)} -pin  "FRAME:for:mul#5" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(4)} -pin  "FRAME:for:mul#5" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(5)} -pin  "FRAME:for:mul#5" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(6)} -pin  "FRAME:for:mul#5" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(7)} -pin  "FRAME:for:mul#5" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(8)} -pin  "FRAME:for:mul#5" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {regs.operator[]#11:mux.itm(9)} -pin  "FRAME:for:mul#5" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#11:mux.itm}
+load net {FRAME:for:or#5.itm} -pin  "FRAME:for:mul#5" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#32}
+load net {FRAME:for:and#18.seb} -pin  "FRAME:for:mul#5" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#32}
+load net {FRAME:for:mul#5.itm(0)} -pin  "FRAME:for:mul#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(1)} -pin  "FRAME:for:mul#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(2)} -pin  "FRAME:for:mul#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(3)} -pin  "FRAME:for:mul#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(4)} -pin  "FRAME:for:mul#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(5)} -pin  "FRAME:for:mul#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(6)} -pin  "FRAME:for:mul#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(7)} -pin  "FRAME:for:mul#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(8)} -pin  "FRAME:for:mul#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(9)} -pin  "FRAME:for:mul#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(10)} -pin  "FRAME:for:mul#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load inst "FRAME:for:acc#28" "add(15,-1,11,1,15)" "INTERFACE" -attr xrf 39951 -attr oid 438 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28} -attr area 16.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {b(1).sg1.lpi#1.dfm(0)} -pin  "FRAME:for:acc#28" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(1)} -pin  "FRAME:for:acc#28" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(2)} -pin  "FRAME:for:acc#28" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(3)} -pin  "FRAME:for:acc#28" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(4)} -pin  "FRAME:for:acc#28" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(5)} -pin  "FRAME:for:acc#28" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(6)} -pin  "FRAME:for:acc#28" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(7)} -pin  "FRAME:for:acc#28" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(8)} -pin  "FRAME:for:acc#28" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(9)} -pin  "FRAME:for:acc#28" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(10)} -pin  "FRAME:for:acc#28" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(11)} -pin  "FRAME:for:acc#28" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(12)} -pin  "FRAME:for:acc#28" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(13)} -pin  "FRAME:for:acc#28" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(14)} -pin  "FRAME:for:acc#28" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {FRAME:for:mul#5.itm(0)} -pin  "FRAME:for:acc#28" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(1)} -pin  "FRAME:for:acc#28" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(2)} -pin  "FRAME:for:acc#28" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(3)} -pin  "FRAME:for:acc#28" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(4)} -pin  "FRAME:for:acc#28" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(5)} -pin  "FRAME:for:acc#28" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(6)} -pin  "FRAME:for:acc#28" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(7)} -pin  "FRAME:for:acc#28" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(8)} -pin  "FRAME:for:acc#28" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(9)} -pin  "FRAME:for:acc#28" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:mul#5.itm(10)} -pin  "FRAME:for:acc#28" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#5.itm}
+load net {FRAME:for:acc#28.itm(0)} -pin  "FRAME:for:acc#28" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(1)} -pin  "FRAME:for:acc#28" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(2)} -pin  "FRAME:for:acc#28" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(3)} -pin  "FRAME:for:acc#28" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(4)} -pin  "FRAME:for:acc#28" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(5)} -pin  "FRAME:for:acc#28" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(6)} -pin  "FRAME:for:acc#28" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(7)} -pin  "FRAME:for:acc#28" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(8)} -pin  "FRAME:for:acc#28" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(9)} -pin  "FRAME:for:acc#28" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(10)} -pin  "FRAME:for:acc#28" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(11)} -pin  "FRAME:for:acc#28" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(12)} -pin  "FRAME:for:acc#28" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(13)} -pin  "FRAME:for:acc#28" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(14)} -pin  "FRAME:for:acc#28" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load inst "mux#8" "mux(2,15)" "INTERFACE" -attr xrf 39952 -attr oid 439 -attr vt d -attr @path {/sobel/sobel:core/mux#8} -attr area 13.792345 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(15,1,2)"
+load net {FRAME:for:acc#28.itm(0)} -pin  "mux#8" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(1)} -pin  "mux#8" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(2)} -pin  "mux#8" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(3)} -pin  "mux#8" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(4)} -pin  "mux#8" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(5)} -pin  "mux#8" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(6)} -pin  "mux#8" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(7)} -pin  "mux#8" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(8)} -pin  "mux#8" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(9)} -pin  "mux#8" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(10)} -pin  "mux#8" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(11)} -pin  "mux#8" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(12)} -pin  "mux#8" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(13)} -pin  "mux#8" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {FRAME:for:acc#28.itm(14)} -pin  "mux#8" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#28.itm}
+load net {b(1).sg1.lpi#1.dfm(0)} -pin  "mux#8" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(1)} -pin  "mux#8" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(2)} -pin  "mux#8" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(3)} -pin  "mux#8" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(4)} -pin  "mux#8" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(5)} -pin  "mux#8" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(6)} -pin  "mux#8" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(7)} -pin  "mux#8" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(8)} -pin  "mux#8" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(9)} -pin  "mux#8" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(10)} -pin  "mux#8" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(11)} -pin  "mux#8" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(12)} -pin  "mux#8" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(13)} -pin  "mux#8" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(14)} -pin  "mux#8" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {or#4.cse} -pin  "mux#8" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#8.itm(0)} -pin  "mux#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(1)} -pin  "mux#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(2)} -pin  "mux#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(3)} -pin  "mux#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(4)} -pin  "mux#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(5)} -pin  "mux#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(6)} -pin  "mux#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(7)} -pin  "mux#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(8)} -pin  "mux#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(9)} -pin  "mux#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(10)} -pin  "mux#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(11)} -pin  "mux#8" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(12)} -pin  "mux#8" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(13)} -pin  "mux#8" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(14)} -pin  "mux#8" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load inst "reg(b(1).sg1.lpi#1)" "reg(15,1,1,-1,0)" "INTERFACE" -attr xrf 39953 -attr oid 440 -attr vt d -attr @path {/sobel/sobel:core/reg(b(1).sg1.lpi#1)}
+load net {mux#8.itm(0)} -pin  "reg(b(1).sg1.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(1)} -pin  "reg(b(1).sg1.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(2)} -pin  "reg(b(1).sg1.lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(3)} -pin  "reg(b(1).sg1.lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(4)} -pin  "reg(b(1).sg1.lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(5)} -pin  "reg(b(1).sg1.lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(6)} -pin  "reg(b(1).sg1.lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(7)} -pin  "reg(b(1).sg1.lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(8)} -pin  "reg(b(1).sg1.lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(9)} -pin  "reg(b(1).sg1.lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(10)} -pin  "reg(b(1).sg1.lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(11)} -pin  "reg(b(1).sg1.lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(12)} -pin  "reg(b(1).sg1.lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(13)} -pin  "reg(b(1).sg1.lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {mux#8.itm(14)} -pin  "reg(b(1).sg1.lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#8.itm}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(b(1).sg1.lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_15}
+load net {clk} -pin  "reg(b(1).sg1.lpi#1)" {clk} -attr xrf 39954 -attr oid 441 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(b(1).sg1.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(b(1).sg1.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {b(1).sg1.lpi#1(0)} -pin  "reg(b(1).sg1.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(1)} -pin  "reg(b(1).sg1.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(2)} -pin  "reg(b(1).sg1.lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(3)} -pin  "reg(b(1).sg1.lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(4)} -pin  "reg(b(1).sg1.lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(5)} -pin  "reg(b(1).sg1.lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(6)} -pin  "reg(b(1).sg1.lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(7)} -pin  "reg(b(1).sg1.lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(8)} -pin  "reg(b(1).sg1.lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(9)} -pin  "reg(b(1).sg1.lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(10)} -pin  "reg(b(1).sg1.lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(11)} -pin  "reg(b(1).sg1.lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(12)} -pin  "reg(b(1).sg1.lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(13)} -pin  "reg(b(1).sg1.lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(14)} -pin  "reg(b(1).sg1.lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load inst "regs.operator[]#10:mux" "mux(4,10)" "INTERFACE" -attr xrf 39955 -attr oid 442 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#10:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "regs.operator[]#10:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "regs.operator[]#10:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "regs.operator[]#10:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "regs.operator[]#10:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "regs.operator[]#10:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "regs.operator[]#10:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "regs.operator[]#10:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "regs.operator[]#10:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "regs.operator[]#10:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "regs.operator[]#10:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "regs.operator[]#10:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "regs.operator[]#10:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "regs.operator[]#10:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "regs.operator[]#10:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "regs.operator[]#10:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "regs.operator[]#10:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "regs.operator[]#10:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "regs.operator[]#10:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "regs.operator[]#10:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "regs.operator[]#10:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "regs.operator[]#10:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "regs.operator[]#10:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "regs.operator[]#10:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "regs.operator[]#10:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "regs.operator[]#10:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "regs.operator[]#10:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "regs.operator[]#10:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "regs.operator[]#10:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "regs.operator[]#10:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "regs.operator[]#10:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#4.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#10:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#10:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#10:mux.itm(0)} -pin  "regs.operator[]#10:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(1)} -pin  "regs.operator[]#10:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(2)} -pin  "regs.operator[]#10:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(3)} -pin  "regs.operator[]#10:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(4)} -pin  "regs.operator[]#10:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(5)} -pin  "regs.operator[]#10:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(6)} -pin  "regs.operator[]#10:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(7)} -pin  "regs.operator[]#10:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(8)} -pin  "regs.operator[]#10:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(9)} -pin  "regs.operator[]#10:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load inst "FRAME:for:mul#4" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 39956 -attr oid 443 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#10:mux.itm(0)} -pin  "FRAME:for:mul#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(1)} -pin  "FRAME:for:mul#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(2)} -pin  "FRAME:for:mul#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(3)} -pin  "FRAME:for:mul#4" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(4)} -pin  "FRAME:for:mul#4" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(5)} -pin  "FRAME:for:mul#4" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(6)} -pin  "FRAME:for:mul#4" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(7)} -pin  "FRAME:for:mul#4" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(8)} -pin  "FRAME:for:mul#4" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {regs.operator[]#10:mux.itm(9)} -pin  "FRAME:for:mul#4" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#10:mux.itm}
+load net {FRAME:for:or#5.itm} -pin  "FRAME:for:mul#4" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#32}
+load net {FRAME:for:and#18.seb} -pin  "FRAME:for:mul#4" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#32}
+load net {FRAME:for:mul#4.itm(0)} -pin  "FRAME:for:mul#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(1)} -pin  "FRAME:for:mul#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(2)} -pin  "FRAME:for:mul#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(3)} -pin  "FRAME:for:mul#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(4)} -pin  "FRAME:for:mul#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(5)} -pin  "FRAME:for:mul#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(6)} -pin  "FRAME:for:mul#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(7)} -pin  "FRAME:for:mul#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(8)} -pin  "FRAME:for:mul#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(9)} -pin  "FRAME:for:mul#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(10)} -pin  "FRAME:for:mul#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load inst "FRAME:for:acc#27" "add(15,-1,11,1,15)" "INTERFACE" -attr xrf 39957 -attr oid 444 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27} -attr area 16.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {g(1).sg1.lpi#1.dfm(0)} -pin  "FRAME:for:acc#27" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(1)} -pin  "FRAME:for:acc#27" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(2)} -pin  "FRAME:for:acc#27" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(3)} -pin  "FRAME:for:acc#27" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(4)} -pin  "FRAME:for:acc#27" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(5)} -pin  "FRAME:for:acc#27" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(6)} -pin  "FRAME:for:acc#27" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(7)} -pin  "FRAME:for:acc#27" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(8)} -pin  "FRAME:for:acc#27" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(9)} -pin  "FRAME:for:acc#27" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(10)} -pin  "FRAME:for:acc#27" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(11)} -pin  "FRAME:for:acc#27" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(12)} -pin  "FRAME:for:acc#27" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(13)} -pin  "FRAME:for:acc#27" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(14)} -pin  "FRAME:for:acc#27" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {FRAME:for:mul#4.itm(0)} -pin  "FRAME:for:acc#27" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(1)} -pin  "FRAME:for:acc#27" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(2)} -pin  "FRAME:for:acc#27" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(3)} -pin  "FRAME:for:acc#27" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(4)} -pin  "FRAME:for:acc#27" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(5)} -pin  "FRAME:for:acc#27" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(6)} -pin  "FRAME:for:acc#27" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(7)} -pin  "FRAME:for:acc#27" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(8)} -pin  "FRAME:for:acc#27" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(9)} -pin  "FRAME:for:acc#27" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:mul#4.itm(10)} -pin  "FRAME:for:acc#27" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#4.itm}
+load net {FRAME:for:acc#27.itm(0)} -pin  "FRAME:for:acc#27" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(1)} -pin  "FRAME:for:acc#27" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(2)} -pin  "FRAME:for:acc#27" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(3)} -pin  "FRAME:for:acc#27" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(4)} -pin  "FRAME:for:acc#27" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(5)} -pin  "FRAME:for:acc#27" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(6)} -pin  "FRAME:for:acc#27" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(7)} -pin  "FRAME:for:acc#27" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(8)} -pin  "FRAME:for:acc#27" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(9)} -pin  "FRAME:for:acc#27" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(10)} -pin  "FRAME:for:acc#27" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(11)} -pin  "FRAME:for:acc#27" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(12)} -pin  "FRAME:for:acc#27" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(13)} -pin  "FRAME:for:acc#27" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(14)} -pin  "FRAME:for:acc#27" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load inst "mux#9" "mux(2,15)" "INTERFACE" -attr xrf 39958 -attr oid 445 -attr vt d -attr @path {/sobel/sobel:core/mux#9} -attr area 13.792345 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(15,1,2)"
+load net {FRAME:for:acc#27.itm(0)} -pin  "mux#9" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(1)} -pin  "mux#9" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(2)} -pin  "mux#9" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(3)} -pin  "mux#9" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(4)} -pin  "mux#9" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(5)} -pin  "mux#9" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(6)} -pin  "mux#9" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(7)} -pin  "mux#9" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(8)} -pin  "mux#9" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(9)} -pin  "mux#9" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(10)} -pin  "mux#9" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(11)} -pin  "mux#9" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(12)} -pin  "mux#9" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(13)} -pin  "mux#9" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {FRAME:for:acc#27.itm(14)} -pin  "mux#9" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#27.itm}
+load net {g(1).sg1.lpi#1.dfm(0)} -pin  "mux#9" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(1)} -pin  "mux#9" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(2)} -pin  "mux#9" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(3)} -pin  "mux#9" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(4)} -pin  "mux#9" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(5)} -pin  "mux#9" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(6)} -pin  "mux#9" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(7)} -pin  "mux#9" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(8)} -pin  "mux#9" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(9)} -pin  "mux#9" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(10)} -pin  "mux#9" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(11)} -pin  "mux#9" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(12)} -pin  "mux#9" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(13)} -pin  "mux#9" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(14)} -pin  "mux#9" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {or#4.cse} -pin  "mux#9" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#9.itm(0)} -pin  "mux#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(1)} -pin  "mux#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(2)} -pin  "mux#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(3)} -pin  "mux#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(4)} -pin  "mux#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(5)} -pin  "mux#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(6)} -pin  "mux#9" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(7)} -pin  "mux#9" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(8)} -pin  "mux#9" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(9)} -pin  "mux#9" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(10)} -pin  "mux#9" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(11)} -pin  "mux#9" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(12)} -pin  "mux#9" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(13)} -pin  "mux#9" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(14)} -pin  "mux#9" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load inst "reg(g(1).sg1.lpi#1)" "reg(15,1,1,-1,0)" "INTERFACE" -attr xrf 39959 -attr oid 446 -attr vt d -attr @path {/sobel/sobel:core/reg(g(1).sg1.lpi#1)}
+load net {mux#9.itm(0)} -pin  "reg(g(1).sg1.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(1)} -pin  "reg(g(1).sg1.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(2)} -pin  "reg(g(1).sg1.lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(3)} -pin  "reg(g(1).sg1.lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(4)} -pin  "reg(g(1).sg1.lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(5)} -pin  "reg(g(1).sg1.lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(6)} -pin  "reg(g(1).sg1.lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(7)} -pin  "reg(g(1).sg1.lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(8)} -pin  "reg(g(1).sg1.lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(9)} -pin  "reg(g(1).sg1.lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(10)} -pin  "reg(g(1).sg1.lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(11)} -pin  "reg(g(1).sg1.lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(12)} -pin  "reg(g(1).sg1.lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(13)} -pin  "reg(g(1).sg1.lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {mux#9.itm(14)} -pin  "reg(g(1).sg1.lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#9.itm}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(g(1).sg1.lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_15}
+load net {clk} -pin  "reg(g(1).sg1.lpi#1)" {clk} -attr xrf 39960 -attr oid 447 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(g(1).sg1.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(g(1).sg1.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {g(1).sg1.lpi#1(0)} -pin  "reg(g(1).sg1.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(1)} -pin  "reg(g(1).sg1.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(2)} -pin  "reg(g(1).sg1.lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(3)} -pin  "reg(g(1).sg1.lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(4)} -pin  "reg(g(1).sg1.lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(5)} -pin  "reg(g(1).sg1.lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(6)} -pin  "reg(g(1).sg1.lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(7)} -pin  "reg(g(1).sg1.lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(8)} -pin  "reg(g(1).sg1.lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(9)} -pin  "reg(g(1).sg1.lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(10)} -pin  "reg(g(1).sg1.lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(11)} -pin  "reg(g(1).sg1.lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(12)} -pin  "reg(g(1).sg1.lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(13)} -pin  "reg(g(1).sg1.lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(14)} -pin  "reg(g(1).sg1.lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load inst "regs.operator[]#9:mux" "mux(4,10)" "INTERFACE" -attr xrf 39961 -attr oid 448 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#9:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "regs.operator[]#9:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "regs.operator[]#9:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "regs.operator[]#9:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "regs.operator[]#9:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "regs.operator[]#9:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "regs.operator[]#9:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "regs.operator[]#9:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "regs.operator[]#9:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "regs.operator[]#9:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "regs.operator[]#9:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "regs.operator[]#9:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "regs.operator[]#9:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "regs.operator[]#9:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "regs.operator[]#9:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "regs.operator[]#9:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "regs.operator[]#9:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "regs.operator[]#9:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "regs.operator[]#9:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "regs.operator[]#9:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "regs.operator[]#9:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "regs.operator[]#9:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "regs.operator[]#9:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "regs.operator[]#9:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "regs.operator[]#9:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "regs.operator[]#9:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "regs.operator[]#9:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "regs.operator[]#9:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "regs.operator[]#9:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "regs.operator[]#9:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "regs.operator[]#9:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#5.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#9:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#9:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#9:mux.itm(0)} -pin  "regs.operator[]#9:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(1)} -pin  "regs.operator[]#9:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(2)} -pin  "regs.operator[]#9:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(3)} -pin  "regs.operator[]#9:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(4)} -pin  "regs.operator[]#9:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(5)} -pin  "regs.operator[]#9:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(6)} -pin  "regs.operator[]#9:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(7)} -pin  "regs.operator[]#9:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(8)} -pin  "regs.operator[]#9:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(9)} -pin  "regs.operator[]#9:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load inst "FRAME:for:mul#3" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 39962 -attr oid 449 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#9:mux.itm(0)} -pin  "FRAME:for:mul#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(1)} -pin  "FRAME:for:mul#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(2)} -pin  "FRAME:for:mul#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(3)} -pin  "FRAME:for:mul#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(4)} -pin  "FRAME:for:mul#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(5)} -pin  "FRAME:for:mul#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(6)} -pin  "FRAME:for:mul#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(7)} -pin  "FRAME:for:mul#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(8)} -pin  "FRAME:for:mul#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {regs.operator[]#9:mux.itm(9)} -pin  "FRAME:for:mul#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#9:mux.itm}
+load net {FRAME:for:or#5.itm} -pin  "FRAME:for:mul#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#32}
+load net {FRAME:for:and#18.seb} -pin  "FRAME:for:mul#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#32}
+load net {FRAME:for:mul#3.itm(0)} -pin  "FRAME:for:mul#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(1)} -pin  "FRAME:for:mul#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(2)} -pin  "FRAME:for:mul#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(3)} -pin  "FRAME:for:mul#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(4)} -pin  "FRAME:for:mul#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(5)} -pin  "FRAME:for:mul#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(6)} -pin  "FRAME:for:mul#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(7)} -pin  "FRAME:for:mul#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(8)} -pin  "FRAME:for:mul#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(9)} -pin  "FRAME:for:mul#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(10)} -pin  "FRAME:for:mul#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load inst "FRAME:for:acc#26" "add(15,-1,11,1,15)" "INTERFACE" -attr xrf 39963 -attr oid 450 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26} -attr area 16.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15)"
+load net {r(1).sg1.lpi#1.dfm(0)} -pin  "FRAME:for:acc#26" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(1)} -pin  "FRAME:for:acc#26" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(2)} -pin  "FRAME:for:acc#26" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(3)} -pin  "FRAME:for:acc#26" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(4)} -pin  "FRAME:for:acc#26" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(5)} -pin  "FRAME:for:acc#26" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(6)} -pin  "FRAME:for:acc#26" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(7)} -pin  "FRAME:for:acc#26" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(8)} -pin  "FRAME:for:acc#26" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(9)} -pin  "FRAME:for:acc#26" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(10)} -pin  "FRAME:for:acc#26" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(11)} -pin  "FRAME:for:acc#26" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(12)} -pin  "FRAME:for:acc#26" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(13)} -pin  "FRAME:for:acc#26" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(14)} -pin  "FRAME:for:acc#26" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {FRAME:for:mul#3.itm(0)} -pin  "FRAME:for:acc#26" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(1)} -pin  "FRAME:for:acc#26" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(2)} -pin  "FRAME:for:acc#26" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(3)} -pin  "FRAME:for:acc#26" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(4)} -pin  "FRAME:for:acc#26" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(5)} -pin  "FRAME:for:acc#26" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(6)} -pin  "FRAME:for:acc#26" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(7)} -pin  "FRAME:for:acc#26" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(8)} -pin  "FRAME:for:acc#26" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(9)} -pin  "FRAME:for:acc#26" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:mul#3.itm(10)} -pin  "FRAME:for:acc#26" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#3.itm}
+load net {FRAME:for:acc#26.itm(0)} -pin  "FRAME:for:acc#26" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(1)} -pin  "FRAME:for:acc#26" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(2)} -pin  "FRAME:for:acc#26" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(3)} -pin  "FRAME:for:acc#26" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(4)} -pin  "FRAME:for:acc#26" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(5)} -pin  "FRAME:for:acc#26" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(6)} -pin  "FRAME:for:acc#26" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(7)} -pin  "FRAME:for:acc#26" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(8)} -pin  "FRAME:for:acc#26" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(9)} -pin  "FRAME:for:acc#26" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(10)} -pin  "FRAME:for:acc#26" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(11)} -pin  "FRAME:for:acc#26" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(12)} -pin  "FRAME:for:acc#26" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(13)} -pin  "FRAME:for:acc#26" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(14)} -pin  "FRAME:for:acc#26" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load inst "mux#10" "mux(2,15)" "INTERFACE" -attr xrf 39964 -attr oid 451 -attr vt d -attr @path {/sobel/sobel:core/mux#10} -attr area 13.792345 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(15,1,2)"
+load net {FRAME:for:acc#26.itm(0)} -pin  "mux#10" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(1)} -pin  "mux#10" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(2)} -pin  "mux#10" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(3)} -pin  "mux#10" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(4)} -pin  "mux#10" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(5)} -pin  "mux#10" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(6)} -pin  "mux#10" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(7)} -pin  "mux#10" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(8)} -pin  "mux#10" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(9)} -pin  "mux#10" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(10)} -pin  "mux#10" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(11)} -pin  "mux#10" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(12)} -pin  "mux#10" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(13)} -pin  "mux#10" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {FRAME:for:acc#26.itm(14)} -pin  "mux#10" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#26.itm}
+load net {r(1).sg1.lpi#1.dfm(0)} -pin  "mux#10" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(1)} -pin  "mux#10" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(2)} -pin  "mux#10" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(3)} -pin  "mux#10" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(4)} -pin  "mux#10" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(5)} -pin  "mux#10" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(6)} -pin  "mux#10" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(7)} -pin  "mux#10" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(8)} -pin  "mux#10" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(9)} -pin  "mux#10" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(10)} -pin  "mux#10" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(11)} -pin  "mux#10" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(12)} -pin  "mux#10" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(13)} -pin  "mux#10" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(14)} -pin  "mux#10" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {or#4.cse} -pin  "mux#10" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#10.itm(0)} -pin  "mux#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(1)} -pin  "mux#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(2)} -pin  "mux#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(3)} -pin  "mux#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(4)} -pin  "mux#10" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(5)} -pin  "mux#10" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(6)} -pin  "mux#10" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(7)} -pin  "mux#10" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(8)} -pin  "mux#10" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(9)} -pin  "mux#10" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(10)} -pin  "mux#10" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(11)} -pin  "mux#10" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(12)} -pin  "mux#10" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(13)} -pin  "mux#10" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(14)} -pin  "mux#10" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load inst "reg(r(1).sg1.lpi#1)" "reg(15,1,1,-1,0)" "INTERFACE" -attr xrf 39965 -attr oid 452 -attr vt d -attr @path {/sobel/sobel:core/reg(r(1).sg1.lpi#1)}
+load net {mux#10.itm(0)} -pin  "reg(r(1).sg1.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(1)} -pin  "reg(r(1).sg1.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(2)} -pin  "reg(r(1).sg1.lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(3)} -pin  "reg(r(1).sg1.lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(4)} -pin  "reg(r(1).sg1.lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(5)} -pin  "reg(r(1).sg1.lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(6)} -pin  "reg(r(1).sg1.lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(7)} -pin  "reg(r(1).sg1.lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(8)} -pin  "reg(r(1).sg1.lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(9)} -pin  "reg(r(1).sg1.lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(10)} -pin  "reg(r(1).sg1.lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(11)} -pin  "reg(r(1).sg1.lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(12)} -pin  "reg(r(1).sg1.lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(13)} -pin  "reg(r(1).sg1.lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {mux#10.itm(14)} -pin  "reg(r(1).sg1.lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#10.itm}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_15}
+load net {GND} -pin  "reg(r(1).sg1.lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_15}
+load net {clk} -pin  "reg(r(1).sg1.lpi#1)" {clk} -attr xrf 39966 -attr oid 453 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(r(1).sg1.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(r(1).sg1.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {r(1).sg1.lpi#1(0)} -pin  "reg(r(1).sg1.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(1)} -pin  "reg(r(1).sg1.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(2)} -pin  "reg(r(1).sg1.lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(3)} -pin  "reg(r(1).sg1.lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(4)} -pin  "reg(r(1).sg1.lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(5)} -pin  "reg(r(1).sg1.lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(6)} -pin  "reg(r(1).sg1.lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(7)} -pin  "reg(r(1).sg1.lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(8)} -pin  "reg(r(1).sg1.lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(9)} -pin  "reg(r(1).sg1.lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(10)} -pin  "reg(r(1).sg1.lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(11)} -pin  "reg(r(1).sg1.lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(12)} -pin  "reg(r(1).sg1.lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(13)} -pin  "reg(r(1).sg1.lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(14)} -pin  "reg(r(1).sg1.lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load inst "mux#11" "mux(2,2)" "INTERFACE" -attr xrf 39967 -attr oid 454 -attr vt d -attr @path {/sobel/sobel:core/mux#11} -attr area 1.839846 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(2,1,2)"
+load net {i#6.sva#1(0)} -pin  "mux#11" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "mux#11" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.lpi#1.dfm(0)} -pin  "mux#11" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "mux#11" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {or#4.cse} -pin  "mux#11" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#11.itm(0)} -pin  "mux#11" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#11.itm}
+load net {mux#11.itm(1)} -pin  "mux#11" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#11.itm}
+load inst "reg(i#6.lpi#1)" "reg(2,1,1,-1,0)" "INTERFACE" -attr xrf 39968 -attr oid 455 -attr vt d -attr @path {/sobel/sobel:core/reg(i#6.lpi#1)}
+load net {mux#11.itm(0)} -pin  "reg(i#6.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#11.itm}
+load net {mux#11.itm(1)} -pin  "reg(i#6.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#11.itm}
+load net {GND} -pin  "reg(i#6.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_2}
+load net {GND} -pin  "reg(i#6.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_2}
+load net {clk} -pin  "reg(i#6.lpi#1)" {clk} -attr xrf 39969 -attr oid 456 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(i#6.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(i#6.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {i#6.lpi#1(0)} -pin  "reg(i#6.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1}
+load net {i#6.lpi#1(1)} -pin  "reg(i#6.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1}
+load inst "regs.operator[]#14:mux" "mux(4,10)" "INTERFACE" -attr xrf 39970 -attr oid 457 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#14:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#14:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#14:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#14:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#14:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#14:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#14:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#14:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#14:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#14:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "regs.operator[]#14:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "regs.operator[]#14:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "regs.operator[]#14:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "regs.operator[]#14:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "regs.operator[]#14:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "regs.operator[]#14:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "regs.operator[]#14:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "regs.operator[]#14:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "regs.operator[]#14:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "regs.operator[]#14:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "regs.operator[]#14:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "regs.operator[]#14:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "regs.operator[]#14:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "regs.operator[]#14:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "regs.operator[]#14:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "regs.operator[]#14:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "regs.operator[]#14:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "regs.operator[]#14:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "regs.operator[]#14:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "regs.operator[]#14:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "regs.operator[]#14:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "regs.operator[]#14:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "regs.operator[]#14:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "regs.operator[]#14:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "regs.operator[]#14:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "regs.operator[]#14:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "regs.operator[]#14:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "regs.operator[]#14:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "regs.operator[]#14:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "regs.operator[]#14:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0).itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#14:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#14:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#14:mux.itm(0)} -pin  "regs.operator[]#14:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(1)} -pin  "regs.operator[]#14:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(2)} -pin  "regs.operator[]#14:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(3)} -pin  "regs.operator[]#14:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(4)} -pin  "regs.operator[]#14:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(5)} -pin  "regs.operator[]#14:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(6)} -pin  "regs.operator[]#14:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(7)} -pin  "regs.operator[]#14:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(8)} -pin  "regs.operator[]#14:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(9)} -pin  "regs.operator[]#14:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load inst "FRAME:for:mul#8" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 39971 -attr oid 458 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#14:mux.itm(0)} -pin  "FRAME:for:mul#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(1)} -pin  "FRAME:for:mul#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(2)} -pin  "FRAME:for:mul#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(3)} -pin  "FRAME:for:mul#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(4)} -pin  "FRAME:for:mul#8" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(5)} -pin  "FRAME:for:mul#8" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(6)} -pin  "FRAME:for:mul#8" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(7)} -pin  "FRAME:for:mul#8" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(8)} -pin  "FRAME:for:mul#8" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {regs.operator[]#14:mux.itm(9)} -pin  "FRAME:for:mul#8" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#14:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:mul#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:mul#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:mul#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:mul#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:mul#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:mul#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:mul#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:mul#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:mul#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:mul#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:mul#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load inst "FRAME:for:acc#14" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 39972 -attr oid 459 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {b(2).lpi#1.dfm(0)} -pin  "FRAME:for:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(1)} -pin  "FRAME:for:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(2)} -pin  "FRAME:for:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(3)} -pin  "FRAME:for:acc#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(4)} -pin  "FRAME:for:acc#14" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(5)} -pin  "FRAME:for:acc#14" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(6)} -pin  "FRAME:for:acc#14" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(7)} -pin  "FRAME:for:acc#14" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(8)} -pin  "FRAME:for:acc#14" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(9)} -pin  "FRAME:for:acc#14" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(10)} -pin  "FRAME:for:acc#14" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(11)} -pin  "FRAME:for:acc#14" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(12)} -pin  "FRAME:for:acc#14" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(13)} -pin  "FRAME:for:acc#14" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(14)} -pin  "FRAME:for:acc#14" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(15)} -pin  "FRAME:for:acc#14" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {FRAME:for:mul#8.itm(0)} -pin  "FRAME:for:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(1)} -pin  "FRAME:for:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(2)} -pin  "FRAME:for:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(3)} -pin  "FRAME:for:acc#14" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(4)} -pin  "FRAME:for:acc#14" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(5)} -pin  "FRAME:for:acc#14" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(6)} -pin  "FRAME:for:acc#14" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(7)} -pin  "FRAME:for:acc#14" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(8)} -pin  "FRAME:for:acc#14" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(9)} -pin  "FRAME:for:acc#14" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:mul#8.itm(10)} -pin  "FRAME:for:acc#14" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#8.itm}
+load net {FRAME:for:acc#14.itm(0)} -pin  "FRAME:for:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(1)} -pin  "FRAME:for:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(2)} -pin  "FRAME:for:acc#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(3)} -pin  "FRAME:for:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(4)} -pin  "FRAME:for:acc#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(5)} -pin  "FRAME:for:acc#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(6)} -pin  "FRAME:for:acc#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(7)} -pin  "FRAME:for:acc#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(8)} -pin  "FRAME:for:acc#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(9)} -pin  "FRAME:for:acc#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(10)} -pin  "FRAME:for:acc#14" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(11)} -pin  "FRAME:for:acc#14" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(12)} -pin  "FRAME:for:acc#14" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(13)} -pin  "FRAME:for:acc#14" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(14)} -pin  "FRAME:for:acc#14" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(15)} -pin  "FRAME:for:acc#14" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load inst "mux#12" "mux(2,16)" "INTERFACE" -attr xrf 39973 -attr oid 460 -attr vt d -attr @path {/sobel/sobel:core/mux#12} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:acc#14.itm(0)} -pin  "mux#12" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(1)} -pin  "mux#12" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(2)} -pin  "mux#12" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(3)} -pin  "mux#12" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(4)} -pin  "mux#12" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(5)} -pin  "mux#12" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(6)} -pin  "mux#12" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(7)} -pin  "mux#12" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(8)} -pin  "mux#12" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(9)} -pin  "mux#12" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(10)} -pin  "mux#12" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(11)} -pin  "mux#12" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(12)} -pin  "mux#12" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(13)} -pin  "mux#12" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(14)} -pin  "mux#12" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {FRAME:for:acc#14.itm(15)} -pin  "mux#12" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#14.itm}
+load net {b(2).sva#1(0)} -pin  "mux#12" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(1)} -pin  "mux#12" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(2)} -pin  "mux#12" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(3)} -pin  "mux#12" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(4)} -pin  "mux#12" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(5)} -pin  "mux#12" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(6)} -pin  "mux#12" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(7)} -pin  "mux#12" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(8)} -pin  "mux#12" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(9)} -pin  "mux#12" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(10)} -pin  "mux#12" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(11)} -pin  "mux#12" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(12)} -pin  "mux#12" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(13)} -pin  "mux#12" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(14)} -pin  "mux#12" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(15)} -pin  "mux#12" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {or#4.cse} -pin  "mux#12" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#12.itm(0)} -pin  "mux#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(1)} -pin  "mux#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(2)} -pin  "mux#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(3)} -pin  "mux#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(4)} -pin  "mux#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(5)} -pin  "mux#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(6)} -pin  "mux#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(7)} -pin  "mux#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(8)} -pin  "mux#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(9)} -pin  "mux#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(10)} -pin  "mux#12" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(11)} -pin  "mux#12" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(12)} -pin  "mux#12" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(13)} -pin  "mux#12" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(14)} -pin  "mux#12" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(15)} -pin  "mux#12" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load inst "reg(b(2).lpi#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 39974 -attr oid 461 -attr vt d -attr @path {/sobel/sobel:core/reg(b(2).lpi#1)}
+load net {mux#12.itm(0)} -pin  "reg(b(2).lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(1)} -pin  "reg(b(2).lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(2)} -pin  "reg(b(2).lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(3)} -pin  "reg(b(2).lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(4)} -pin  "reg(b(2).lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(5)} -pin  "reg(b(2).lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(6)} -pin  "reg(b(2).lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(7)} -pin  "reg(b(2).lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(8)} -pin  "reg(b(2).lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(9)} -pin  "reg(b(2).lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(10)} -pin  "reg(b(2).lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(11)} -pin  "reg(b(2).lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(12)} -pin  "reg(b(2).lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(13)} -pin  "reg(b(2).lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(14)} -pin  "reg(b(2).lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {mux#12.itm(15)} -pin  "reg(b(2).lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#12.itm}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(2).lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(b(2).lpi#1)" {clk} -attr xrf 39975 -attr oid 462 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(b(2).lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(b(2).lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {b(2).lpi#1(0)} -pin  "reg(b(2).lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(1)} -pin  "reg(b(2).lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(2)} -pin  "reg(b(2).lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(3)} -pin  "reg(b(2).lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(4)} -pin  "reg(b(2).lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(5)} -pin  "reg(b(2).lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(6)} -pin  "reg(b(2).lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(7)} -pin  "reg(b(2).lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(8)} -pin  "reg(b(2).lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(9)} -pin  "reg(b(2).lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(10)} -pin  "reg(b(2).lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(11)} -pin  "reg(b(2).lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(12)} -pin  "reg(b(2).lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(13)} -pin  "reg(b(2).lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(14)} -pin  "reg(b(2).lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(15)} -pin  "reg(b(2).lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load inst "regs.operator[]#8:mux" "mux(4,10)" "INTERFACE" -attr xrf 39976 -attr oid 463 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#8:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#8:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#8:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#8:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#8:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#8:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#8:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#8:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#8:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#8:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "regs.operator[]#8:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "regs.operator[]#8:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "regs.operator[]#8:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "regs.operator[]#8:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "regs.operator[]#8:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "regs.operator[]#8:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "regs.operator[]#8:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "regs.operator[]#8:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "regs.operator[]#8:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "regs.operator[]#8:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "regs.operator[]#8:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "regs.operator[]#8:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "regs.operator[]#8:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "regs.operator[]#8:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "regs.operator[]#8:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "regs.operator[]#8:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "regs.operator[]#8:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "regs.operator[]#8:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "regs.operator[]#8:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "regs.operator[]#8:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "regs.operator[]#8:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "regs.operator[]#8:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "regs.operator[]#8:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "regs.operator[]#8:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "regs.operator[]#8:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "regs.operator[]#8:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "regs.operator[]#8:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "regs.operator[]#8:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "regs.operator[]#8:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "regs.operator[]#8:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#6.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#8:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#8:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#8:mux.itm(0)} -pin  "regs.operator[]#8:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(1)} -pin  "regs.operator[]#8:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(2)} -pin  "regs.operator[]#8:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(3)} -pin  "regs.operator[]#8:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(4)} -pin  "regs.operator[]#8:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(5)} -pin  "regs.operator[]#8:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(6)} -pin  "regs.operator[]#8:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(7)} -pin  "regs.operator[]#8:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(8)} -pin  "regs.operator[]#8:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(9)} -pin  "regs.operator[]#8:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load inst "FRAME:for:mul#2" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 39977 -attr oid 464 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#8:mux.itm(0)} -pin  "FRAME:for:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(1)} -pin  "FRAME:for:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(2)} -pin  "FRAME:for:mul#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(3)} -pin  "FRAME:for:mul#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(4)} -pin  "FRAME:for:mul#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(5)} -pin  "FRAME:for:mul#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(6)} -pin  "FRAME:for:mul#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(7)} -pin  "FRAME:for:mul#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(8)} -pin  "FRAME:for:mul#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {regs.operator[]#8:mux.itm(9)} -pin  "FRAME:for:mul#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#8:mux.itm}
+load net {FRAME:for:or.itm} -pin  "FRAME:for:mul#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#30}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#30}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load inst "FRAME:for:acc#3" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 39978 -attr oid 465 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {b(0).lpi#1.dfm(0)} -pin  "FRAME:for:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(1)} -pin  "FRAME:for:acc#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(2)} -pin  "FRAME:for:acc#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(3)} -pin  "FRAME:for:acc#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(4)} -pin  "FRAME:for:acc#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(5)} -pin  "FRAME:for:acc#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(6)} -pin  "FRAME:for:acc#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(7)} -pin  "FRAME:for:acc#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(8)} -pin  "FRAME:for:acc#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(9)} -pin  "FRAME:for:acc#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(10)} -pin  "FRAME:for:acc#3" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(11)} -pin  "FRAME:for:acc#3" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(12)} -pin  "FRAME:for:acc#3" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(13)} -pin  "FRAME:for:acc#3" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(14)} -pin  "FRAME:for:acc#3" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(15)} -pin  "FRAME:for:acc#3" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {FRAME:for:mul#2.itm(0)} -pin  "FRAME:for:acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(1)} -pin  "FRAME:for:acc#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(2)} -pin  "FRAME:for:acc#3" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(3)} -pin  "FRAME:for:acc#3" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(4)} -pin  "FRAME:for:acc#3" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(5)} -pin  "FRAME:for:acc#3" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(6)} -pin  "FRAME:for:acc#3" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(7)} -pin  "FRAME:for:acc#3" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(8)} -pin  "FRAME:for:acc#3" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(9)} -pin  "FRAME:for:acc#3" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:mul#2.itm(10)} -pin  "FRAME:for:acc#3" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#2.itm}
+load net {FRAME:for:acc#3.itm(0)} -pin  "FRAME:for:acc#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(1)} -pin  "FRAME:for:acc#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(2)} -pin  "FRAME:for:acc#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(3)} -pin  "FRAME:for:acc#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(4)} -pin  "FRAME:for:acc#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(5)} -pin  "FRAME:for:acc#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(6)} -pin  "FRAME:for:acc#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(7)} -pin  "FRAME:for:acc#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(8)} -pin  "FRAME:for:acc#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(9)} -pin  "FRAME:for:acc#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(10)} -pin  "FRAME:for:acc#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(11)} -pin  "FRAME:for:acc#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(12)} -pin  "FRAME:for:acc#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(13)} -pin  "FRAME:for:acc#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(14)} -pin  "FRAME:for:acc#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(15)} -pin  "FRAME:for:acc#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load inst "mux#13" "mux(2,16)" "INTERFACE" -attr xrf 39979 -attr oid 466 -attr vt d -attr @path {/sobel/sobel:core/mux#13} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:acc#3.itm(0)} -pin  "mux#13" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(1)} -pin  "mux#13" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(2)} -pin  "mux#13" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(3)} -pin  "mux#13" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(4)} -pin  "mux#13" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(5)} -pin  "mux#13" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(6)} -pin  "mux#13" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(7)} -pin  "mux#13" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(8)} -pin  "mux#13" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(9)} -pin  "mux#13" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(10)} -pin  "mux#13" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(11)} -pin  "mux#13" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(12)} -pin  "mux#13" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(13)} -pin  "mux#13" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(14)} -pin  "mux#13" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {FRAME:for:acc#3.itm(15)} -pin  "mux#13" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#3.itm}
+load net {b(0).sva#1(0)} -pin  "mux#13" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(1)} -pin  "mux#13" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(2)} -pin  "mux#13" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(3)} -pin  "mux#13" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(4)} -pin  "mux#13" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(5)} -pin  "mux#13" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(6)} -pin  "mux#13" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(7)} -pin  "mux#13" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(8)} -pin  "mux#13" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(9)} -pin  "mux#13" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(10)} -pin  "mux#13" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(11)} -pin  "mux#13" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(12)} -pin  "mux#13" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(13)} -pin  "mux#13" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(14)} -pin  "mux#13" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(15)} -pin  "mux#13" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {or#4.cse} -pin  "mux#13" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#13.itm(0)} -pin  "mux#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(1)} -pin  "mux#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(2)} -pin  "mux#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(3)} -pin  "mux#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(4)} -pin  "mux#13" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(5)} -pin  "mux#13" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(6)} -pin  "mux#13" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(7)} -pin  "mux#13" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(8)} -pin  "mux#13" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(9)} -pin  "mux#13" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(10)} -pin  "mux#13" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(11)} -pin  "mux#13" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(12)} -pin  "mux#13" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(13)} -pin  "mux#13" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(14)} -pin  "mux#13" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(15)} -pin  "mux#13" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load inst "reg(b(0).lpi#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 39980 -attr oid 467 -attr vt d -attr @path {/sobel/sobel:core/reg(b(0).lpi#1)}
+load net {mux#13.itm(0)} -pin  "reg(b(0).lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(1)} -pin  "reg(b(0).lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(2)} -pin  "reg(b(0).lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(3)} -pin  "reg(b(0).lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(4)} -pin  "reg(b(0).lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(5)} -pin  "reg(b(0).lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(6)} -pin  "reg(b(0).lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(7)} -pin  "reg(b(0).lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(8)} -pin  "reg(b(0).lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(9)} -pin  "reg(b(0).lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(10)} -pin  "reg(b(0).lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(11)} -pin  "reg(b(0).lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(12)} -pin  "reg(b(0).lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(13)} -pin  "reg(b(0).lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(14)} -pin  "reg(b(0).lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {mux#13.itm(15)} -pin  "reg(b(0).lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#13.itm}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(b(0).lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(b(0).lpi#1)" {clk} -attr xrf 39981 -attr oid 468 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(b(0).lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(b(0).lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {b(0).lpi#1(0)} -pin  "reg(b(0).lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(1)} -pin  "reg(b(0).lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(2)} -pin  "reg(b(0).lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(3)} -pin  "reg(b(0).lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(4)} -pin  "reg(b(0).lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(5)} -pin  "reg(b(0).lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(6)} -pin  "reg(b(0).lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(7)} -pin  "reg(b(0).lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(8)} -pin  "reg(b(0).lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(9)} -pin  "reg(b(0).lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(10)} -pin  "reg(b(0).lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(11)} -pin  "reg(b(0).lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(12)} -pin  "reg(b(0).lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(13)} -pin  "reg(b(0).lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(14)} -pin  "reg(b(0).lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(15)} -pin  "reg(b(0).lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load inst "regs.operator[]#13:mux" "mux(4,10)" "INTERFACE" -attr xrf 39982 -attr oid 469 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#13:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#13:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#13:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#13:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#13:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#13:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#13:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#13:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#13:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#13:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "regs.operator[]#13:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "regs.operator[]#13:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "regs.operator[]#13:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "regs.operator[]#13:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "regs.operator[]#13:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "regs.operator[]#13:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "regs.operator[]#13:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "regs.operator[]#13:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "regs.operator[]#13:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "regs.operator[]#13:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "regs.operator[]#13:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "regs.operator[]#13:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "regs.operator[]#13:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "regs.operator[]#13:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "regs.operator[]#13:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "regs.operator[]#13:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "regs.operator[]#13:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "regs.operator[]#13:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "regs.operator[]#13:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "regs.operator[]#13:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "regs.operator[]#13:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "regs.operator[]#13:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "regs.operator[]#13:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "regs.operator[]#13:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "regs.operator[]#13:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "regs.operator[]#13:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "regs.operator[]#13:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "regs.operator[]#13:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "regs.operator[]#13:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "regs.operator[]#13:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#1.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#13:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#13:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#13:mux.itm(0)} -pin  "regs.operator[]#13:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(1)} -pin  "regs.operator[]#13:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(2)} -pin  "regs.operator[]#13:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(3)} -pin  "regs.operator[]#13:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(4)} -pin  "regs.operator[]#13:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(5)} -pin  "regs.operator[]#13:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(6)} -pin  "regs.operator[]#13:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(7)} -pin  "regs.operator[]#13:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(8)} -pin  "regs.operator[]#13:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(9)} -pin  "regs.operator[]#13:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load inst "FRAME:for:mul#7" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 39983 -attr oid 470 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#13:mux.itm(0)} -pin  "FRAME:for:mul#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(1)} -pin  "FRAME:for:mul#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(2)} -pin  "FRAME:for:mul#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(3)} -pin  "FRAME:for:mul#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(4)} -pin  "FRAME:for:mul#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(5)} -pin  "FRAME:for:mul#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(6)} -pin  "FRAME:for:mul#7" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(7)} -pin  "FRAME:for:mul#7" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(8)} -pin  "FRAME:for:mul#7" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {regs.operator[]#13:mux.itm(9)} -pin  "FRAME:for:mul#7" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#13:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:mul#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:mul#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:mul#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:mul#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:mul#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:mul#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:mul#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:mul#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:mul#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:mul#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:mul#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load inst "FRAME:for:acc#12" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 39984 -attr oid 471 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {g(2).lpi#1.dfm(0)} -pin  "FRAME:for:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(1)} -pin  "FRAME:for:acc#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(2)} -pin  "FRAME:for:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(3)} -pin  "FRAME:for:acc#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(4)} -pin  "FRAME:for:acc#12" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(5)} -pin  "FRAME:for:acc#12" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(6)} -pin  "FRAME:for:acc#12" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(7)} -pin  "FRAME:for:acc#12" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(8)} -pin  "FRAME:for:acc#12" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(9)} -pin  "FRAME:for:acc#12" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(10)} -pin  "FRAME:for:acc#12" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(11)} -pin  "FRAME:for:acc#12" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(12)} -pin  "FRAME:for:acc#12" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(13)} -pin  "FRAME:for:acc#12" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(14)} -pin  "FRAME:for:acc#12" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(15)} -pin  "FRAME:for:acc#12" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {FRAME:for:mul#7.itm(0)} -pin  "FRAME:for:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(1)} -pin  "FRAME:for:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(2)} -pin  "FRAME:for:acc#12" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(3)} -pin  "FRAME:for:acc#12" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(4)} -pin  "FRAME:for:acc#12" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(5)} -pin  "FRAME:for:acc#12" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(6)} -pin  "FRAME:for:acc#12" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(7)} -pin  "FRAME:for:acc#12" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(8)} -pin  "FRAME:for:acc#12" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(9)} -pin  "FRAME:for:acc#12" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:mul#7.itm(10)} -pin  "FRAME:for:acc#12" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#7.itm}
+load net {FRAME:for:acc#12.itm(0)} -pin  "FRAME:for:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(1)} -pin  "FRAME:for:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(2)} -pin  "FRAME:for:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(3)} -pin  "FRAME:for:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(4)} -pin  "FRAME:for:acc#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(5)} -pin  "FRAME:for:acc#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(6)} -pin  "FRAME:for:acc#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(7)} -pin  "FRAME:for:acc#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(8)} -pin  "FRAME:for:acc#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(9)} -pin  "FRAME:for:acc#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(10)} -pin  "FRAME:for:acc#12" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(11)} -pin  "FRAME:for:acc#12" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(12)} -pin  "FRAME:for:acc#12" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(13)} -pin  "FRAME:for:acc#12" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(14)} -pin  "FRAME:for:acc#12" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(15)} -pin  "FRAME:for:acc#12" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load inst "mux#14" "mux(2,16)" "INTERFACE" -attr xrf 39985 -attr oid 472 -attr vt d -attr @path {/sobel/sobel:core/mux#14} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:acc#12.itm(0)} -pin  "mux#14" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(1)} -pin  "mux#14" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(2)} -pin  "mux#14" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(3)} -pin  "mux#14" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(4)} -pin  "mux#14" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(5)} -pin  "mux#14" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(6)} -pin  "mux#14" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(7)} -pin  "mux#14" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(8)} -pin  "mux#14" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(9)} -pin  "mux#14" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(10)} -pin  "mux#14" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(11)} -pin  "mux#14" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(12)} -pin  "mux#14" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(13)} -pin  "mux#14" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(14)} -pin  "mux#14" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {FRAME:for:acc#12.itm(15)} -pin  "mux#14" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#12.itm}
+load net {g(2).sva#1(0)} -pin  "mux#14" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(1)} -pin  "mux#14" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(2)} -pin  "mux#14" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(3)} -pin  "mux#14" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(4)} -pin  "mux#14" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(5)} -pin  "mux#14" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(6)} -pin  "mux#14" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(7)} -pin  "mux#14" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(8)} -pin  "mux#14" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(9)} -pin  "mux#14" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(10)} -pin  "mux#14" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(11)} -pin  "mux#14" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(12)} -pin  "mux#14" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(13)} -pin  "mux#14" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(14)} -pin  "mux#14" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(15)} -pin  "mux#14" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {or#4.cse} -pin  "mux#14" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#14.itm(0)} -pin  "mux#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(1)} -pin  "mux#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(2)} -pin  "mux#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(3)} -pin  "mux#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(4)} -pin  "mux#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(5)} -pin  "mux#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(6)} -pin  "mux#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(7)} -pin  "mux#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(8)} -pin  "mux#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(9)} -pin  "mux#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(10)} -pin  "mux#14" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(11)} -pin  "mux#14" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(12)} -pin  "mux#14" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(13)} -pin  "mux#14" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(14)} -pin  "mux#14" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(15)} -pin  "mux#14" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load inst "reg(g(2).lpi#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 39986 -attr oid 473 -attr vt d -attr @path {/sobel/sobel:core/reg(g(2).lpi#1)}
+load net {mux#14.itm(0)} -pin  "reg(g(2).lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(1)} -pin  "reg(g(2).lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(2)} -pin  "reg(g(2).lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(3)} -pin  "reg(g(2).lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(4)} -pin  "reg(g(2).lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(5)} -pin  "reg(g(2).lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(6)} -pin  "reg(g(2).lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(7)} -pin  "reg(g(2).lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(8)} -pin  "reg(g(2).lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(9)} -pin  "reg(g(2).lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(10)} -pin  "reg(g(2).lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(11)} -pin  "reg(g(2).lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(12)} -pin  "reg(g(2).lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(13)} -pin  "reg(g(2).lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(14)} -pin  "reg(g(2).lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {mux#14.itm(15)} -pin  "reg(g(2).lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#14.itm}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(2).lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(g(2).lpi#1)" {clk} -attr xrf 39987 -attr oid 474 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(g(2).lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(g(2).lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {g(2).lpi#1(0)} -pin  "reg(g(2).lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(1)} -pin  "reg(g(2).lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(2)} -pin  "reg(g(2).lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(3)} -pin  "reg(g(2).lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(4)} -pin  "reg(g(2).lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(5)} -pin  "reg(g(2).lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(6)} -pin  "reg(g(2).lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(7)} -pin  "reg(g(2).lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(8)} -pin  "reg(g(2).lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(9)} -pin  "reg(g(2).lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(10)} -pin  "reg(g(2).lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(11)} -pin  "reg(g(2).lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(12)} -pin  "reg(g(2).lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(13)} -pin  "reg(g(2).lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(14)} -pin  "reg(g(2).lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(15)} -pin  "reg(g(2).lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load inst "regs.operator[]#7:mux" "mux(4,10)" "INTERFACE" -attr xrf 39988 -attr oid 475 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#7:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#7:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#7:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#7:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#7:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#7:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#7:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#7:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#7:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#7:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "regs.operator[]#7:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "regs.operator[]#7:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "regs.operator[]#7:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "regs.operator[]#7:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "regs.operator[]#7:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "regs.operator[]#7:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "regs.operator[]#7:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "regs.operator[]#7:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "regs.operator[]#7:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "regs.operator[]#7:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "regs.operator[]#7:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "regs.operator[]#7:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "regs.operator[]#7:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "regs.operator[]#7:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "regs.operator[]#7:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "regs.operator[]#7:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "regs.operator[]#7:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "regs.operator[]#7:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "regs.operator[]#7:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "regs.operator[]#7:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "regs.operator[]#7:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "regs.operator[]#7:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "regs.operator[]#7:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "regs.operator[]#7:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "regs.operator[]#7:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "regs.operator[]#7:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "regs.operator[]#7:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "regs.operator[]#7:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "regs.operator[]#7:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "regs.operator[]#7:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#7.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#7:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#7:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#7:mux.itm(0)} -pin  "regs.operator[]#7:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(1)} -pin  "regs.operator[]#7:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(2)} -pin  "regs.operator[]#7:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(3)} -pin  "regs.operator[]#7:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(4)} -pin  "regs.operator[]#7:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(5)} -pin  "regs.operator[]#7:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(6)} -pin  "regs.operator[]#7:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(7)} -pin  "regs.operator[]#7:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(8)} -pin  "regs.operator[]#7:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(9)} -pin  "regs.operator[]#7:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load inst "FRAME:for:mul#1" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 39989 -attr oid 476 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#7:mux.itm(0)} -pin  "FRAME:for:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(1)} -pin  "FRAME:for:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(2)} -pin  "FRAME:for:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(3)} -pin  "FRAME:for:mul#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(4)} -pin  "FRAME:for:mul#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(5)} -pin  "FRAME:for:mul#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(6)} -pin  "FRAME:for:mul#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(7)} -pin  "FRAME:for:mul#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(8)} -pin  "FRAME:for:mul#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {regs.operator[]#7:mux.itm(9)} -pin  "FRAME:for:mul#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#7:mux.itm}
+load net {FRAME:for:or.itm} -pin  "FRAME:for:mul#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#30}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#1" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#30}
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:mul#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:mul#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load inst "FRAME:for:acc#2" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 39990 -attr oid 477 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {g(0).lpi#1.dfm(0)} -pin  "FRAME:for:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(1)} -pin  "FRAME:for:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(2)} -pin  "FRAME:for:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(3)} -pin  "FRAME:for:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(4)} -pin  "FRAME:for:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(5)} -pin  "FRAME:for:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(6)} -pin  "FRAME:for:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(7)} -pin  "FRAME:for:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(8)} -pin  "FRAME:for:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(9)} -pin  "FRAME:for:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(10)} -pin  "FRAME:for:acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(11)} -pin  "FRAME:for:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(12)} -pin  "FRAME:for:acc#2" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(13)} -pin  "FRAME:for:acc#2" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(14)} -pin  "FRAME:for:acc#2" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(15)} -pin  "FRAME:for:acc#2" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {FRAME:for:mul#1.itm(0)} -pin  "FRAME:for:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(1)} -pin  "FRAME:for:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(2)} -pin  "FRAME:for:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(3)} -pin  "FRAME:for:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(4)} -pin  "FRAME:for:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(5)} -pin  "FRAME:for:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(6)} -pin  "FRAME:for:acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(7)} -pin  "FRAME:for:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(8)} -pin  "FRAME:for:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(9)} -pin  "FRAME:for:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:mul#1.itm(10)} -pin  "FRAME:for:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#1.itm}
+load net {FRAME:for:acc#2.itm(0)} -pin  "FRAME:for:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(1)} -pin  "FRAME:for:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(2)} -pin  "FRAME:for:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(3)} -pin  "FRAME:for:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(4)} -pin  "FRAME:for:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(5)} -pin  "FRAME:for:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(6)} -pin  "FRAME:for:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(7)} -pin  "FRAME:for:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(8)} -pin  "FRAME:for:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(9)} -pin  "FRAME:for:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(10)} -pin  "FRAME:for:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(11)} -pin  "FRAME:for:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(12)} -pin  "FRAME:for:acc#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(13)} -pin  "FRAME:for:acc#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(14)} -pin  "FRAME:for:acc#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(15)} -pin  "FRAME:for:acc#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load inst "mux#15" "mux(2,16)" "INTERFACE" -attr xrf 39991 -attr oid 478 -attr vt d -attr @path {/sobel/sobel:core/mux#15} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:acc#2.itm(0)} -pin  "mux#15" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(1)} -pin  "mux#15" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(2)} -pin  "mux#15" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(3)} -pin  "mux#15" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(4)} -pin  "mux#15" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(5)} -pin  "mux#15" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(6)} -pin  "mux#15" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(7)} -pin  "mux#15" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(8)} -pin  "mux#15" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(9)} -pin  "mux#15" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(10)} -pin  "mux#15" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(11)} -pin  "mux#15" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(12)} -pin  "mux#15" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(13)} -pin  "mux#15" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(14)} -pin  "mux#15" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {FRAME:for:acc#2.itm(15)} -pin  "mux#15" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#2.itm}
+load net {g(0).sva#1(0)} -pin  "mux#15" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(1)} -pin  "mux#15" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(2)} -pin  "mux#15" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(3)} -pin  "mux#15" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(4)} -pin  "mux#15" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(5)} -pin  "mux#15" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(6)} -pin  "mux#15" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(7)} -pin  "mux#15" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(8)} -pin  "mux#15" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(9)} -pin  "mux#15" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(10)} -pin  "mux#15" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(11)} -pin  "mux#15" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(12)} -pin  "mux#15" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(13)} -pin  "mux#15" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(14)} -pin  "mux#15" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(15)} -pin  "mux#15" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {or#4.cse} -pin  "mux#15" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#15.itm(0)} -pin  "mux#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(1)} -pin  "mux#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(2)} -pin  "mux#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(3)} -pin  "mux#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(4)} -pin  "mux#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(5)} -pin  "mux#15" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(6)} -pin  "mux#15" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(7)} -pin  "mux#15" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(8)} -pin  "mux#15" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(9)} -pin  "mux#15" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(10)} -pin  "mux#15" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(11)} -pin  "mux#15" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(12)} -pin  "mux#15" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(13)} -pin  "mux#15" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(14)} -pin  "mux#15" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(15)} -pin  "mux#15" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load inst "reg(g(0).lpi#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 39992 -attr oid 479 -attr vt d -attr @path {/sobel/sobel:core/reg(g(0).lpi#1)}
+load net {mux#15.itm(0)} -pin  "reg(g(0).lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(1)} -pin  "reg(g(0).lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(2)} -pin  "reg(g(0).lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(3)} -pin  "reg(g(0).lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(4)} -pin  "reg(g(0).lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(5)} -pin  "reg(g(0).lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(6)} -pin  "reg(g(0).lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(7)} -pin  "reg(g(0).lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(8)} -pin  "reg(g(0).lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(9)} -pin  "reg(g(0).lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(10)} -pin  "reg(g(0).lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(11)} -pin  "reg(g(0).lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(12)} -pin  "reg(g(0).lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(13)} -pin  "reg(g(0).lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(14)} -pin  "reg(g(0).lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {mux#15.itm(15)} -pin  "reg(g(0).lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#15.itm}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(g(0).lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(g(0).lpi#1)" {clk} -attr xrf 39993 -attr oid 480 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(g(0).lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(g(0).lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {g(0).lpi#1(0)} -pin  "reg(g(0).lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(1)} -pin  "reg(g(0).lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(2)} -pin  "reg(g(0).lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(3)} -pin  "reg(g(0).lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(4)} -pin  "reg(g(0).lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(5)} -pin  "reg(g(0).lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(6)} -pin  "reg(g(0).lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(7)} -pin  "reg(g(0).lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(8)} -pin  "reg(g(0).lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(9)} -pin  "reg(g(0).lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(10)} -pin  "reg(g(0).lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(11)} -pin  "reg(g(0).lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(12)} -pin  "reg(g(0).lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(13)} -pin  "reg(g(0).lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(14)} -pin  "reg(g(0).lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(15)} -pin  "reg(g(0).lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load inst "regs.operator[]#12:mux" "mux(4,10)" "INTERFACE" -attr xrf 39994 -attr oid 481 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#12:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#12:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#12:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#12:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#12:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#12:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#12:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#12:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#12:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#12:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "regs.operator[]#12:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "regs.operator[]#12:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "regs.operator[]#12:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "regs.operator[]#12:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "regs.operator[]#12:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "regs.operator[]#12:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "regs.operator[]#12:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "regs.operator[]#12:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "regs.operator[]#12:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "regs.operator[]#12:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "regs.operator[]#12:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "regs.operator[]#12:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "regs.operator[]#12:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "regs.operator[]#12:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "regs.operator[]#12:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "regs.operator[]#12:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "regs.operator[]#12:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "regs.operator[]#12:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "regs.operator[]#12:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "regs.operator[]#12:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "regs.operator[]#12:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "regs.operator[]#12:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "regs.operator[]#12:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "regs.operator[]#12:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "regs.operator[]#12:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "regs.operator[]#12:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "regs.operator[]#12:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "regs.operator[]#12:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "regs.operator[]#12:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "regs.operator[]#12:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#2.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#12:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#12:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#12:mux.itm(0)} -pin  "regs.operator[]#12:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(1)} -pin  "regs.operator[]#12:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(2)} -pin  "regs.operator[]#12:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(3)} -pin  "regs.operator[]#12:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(4)} -pin  "regs.operator[]#12:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(5)} -pin  "regs.operator[]#12:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(6)} -pin  "regs.operator[]#12:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(7)} -pin  "regs.operator[]#12:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(8)} -pin  "regs.operator[]#12:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(9)} -pin  "regs.operator[]#12:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load inst "FRAME:for:mul#6" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 39995 -attr oid 482 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#12:mux.itm(0)} -pin  "FRAME:for:mul#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(1)} -pin  "FRAME:for:mul#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(2)} -pin  "FRAME:for:mul#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(3)} -pin  "FRAME:for:mul#6" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(4)} -pin  "FRAME:for:mul#6" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(5)} -pin  "FRAME:for:mul#6" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(6)} -pin  "FRAME:for:mul#6" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(7)} -pin  "FRAME:for:mul#6" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(8)} -pin  "FRAME:for:mul#6" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {regs.operator[]#12:mux.itm(9)} -pin  "FRAME:for:mul#6" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#12:mux.itm}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:mul#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#28}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:mul#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:mul#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:mul#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:mul#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:mul#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:mul#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:mul#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:mul#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:mul#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:mul#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:mul#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load inst "FRAME:for:acc#10" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 39996 -attr oid 483 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {r(2).lpi#1.dfm(0)} -pin  "FRAME:for:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(1)} -pin  "FRAME:for:acc#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(2)} -pin  "FRAME:for:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(3)} -pin  "FRAME:for:acc#10" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(4)} -pin  "FRAME:for:acc#10" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(5)} -pin  "FRAME:for:acc#10" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(6)} -pin  "FRAME:for:acc#10" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(7)} -pin  "FRAME:for:acc#10" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(8)} -pin  "FRAME:for:acc#10" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(9)} -pin  "FRAME:for:acc#10" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(10)} -pin  "FRAME:for:acc#10" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(11)} -pin  "FRAME:for:acc#10" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(12)} -pin  "FRAME:for:acc#10" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(13)} -pin  "FRAME:for:acc#10" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(14)} -pin  "FRAME:for:acc#10" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(15)} -pin  "FRAME:for:acc#10" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {FRAME:for:mul#6.itm(0)} -pin  "FRAME:for:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(1)} -pin  "FRAME:for:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(2)} -pin  "FRAME:for:acc#10" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(3)} -pin  "FRAME:for:acc#10" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(4)} -pin  "FRAME:for:acc#10" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(5)} -pin  "FRAME:for:acc#10" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(6)} -pin  "FRAME:for:acc#10" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(7)} -pin  "FRAME:for:acc#10" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(8)} -pin  "FRAME:for:acc#10" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(9)} -pin  "FRAME:for:acc#10" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:mul#6.itm(10)} -pin  "FRAME:for:acc#10" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul#6.itm}
+load net {FRAME:for:acc#10.itm(0)} -pin  "FRAME:for:acc#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(1)} -pin  "FRAME:for:acc#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(2)} -pin  "FRAME:for:acc#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(3)} -pin  "FRAME:for:acc#10" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(4)} -pin  "FRAME:for:acc#10" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(5)} -pin  "FRAME:for:acc#10" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(6)} -pin  "FRAME:for:acc#10" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(7)} -pin  "FRAME:for:acc#10" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(8)} -pin  "FRAME:for:acc#10" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(9)} -pin  "FRAME:for:acc#10" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(10)} -pin  "FRAME:for:acc#10" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(11)} -pin  "FRAME:for:acc#10" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(12)} -pin  "FRAME:for:acc#10" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(13)} -pin  "FRAME:for:acc#10" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(14)} -pin  "FRAME:for:acc#10" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(15)} -pin  "FRAME:for:acc#10" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load inst "mux#16" "mux(2,16)" "INTERFACE" -attr xrf 39997 -attr oid 484 -attr vt d -attr @path {/sobel/sobel:core/mux#16} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:acc#10.itm(0)} -pin  "mux#16" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(1)} -pin  "mux#16" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(2)} -pin  "mux#16" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(3)} -pin  "mux#16" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(4)} -pin  "mux#16" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(5)} -pin  "mux#16" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(6)} -pin  "mux#16" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(7)} -pin  "mux#16" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(8)} -pin  "mux#16" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(9)} -pin  "mux#16" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(10)} -pin  "mux#16" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(11)} -pin  "mux#16" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(12)} -pin  "mux#16" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(13)} -pin  "mux#16" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(14)} -pin  "mux#16" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {FRAME:for:acc#10.itm(15)} -pin  "mux#16" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#10.itm}
+load net {r(2).sva#1(0)} -pin  "mux#16" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(1)} -pin  "mux#16" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(2)} -pin  "mux#16" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(3)} -pin  "mux#16" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(4)} -pin  "mux#16" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(5)} -pin  "mux#16" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(6)} -pin  "mux#16" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(7)} -pin  "mux#16" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(8)} -pin  "mux#16" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(9)} -pin  "mux#16" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(10)} -pin  "mux#16" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(11)} -pin  "mux#16" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(12)} -pin  "mux#16" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(13)} -pin  "mux#16" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(14)} -pin  "mux#16" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(15)} -pin  "mux#16" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {or#4.cse} -pin  "mux#16" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#16.itm(0)} -pin  "mux#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(1)} -pin  "mux#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(2)} -pin  "mux#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(3)} -pin  "mux#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(4)} -pin  "mux#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(5)} -pin  "mux#16" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(6)} -pin  "mux#16" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(7)} -pin  "mux#16" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(8)} -pin  "mux#16" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(9)} -pin  "mux#16" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(10)} -pin  "mux#16" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(11)} -pin  "mux#16" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(12)} -pin  "mux#16" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(13)} -pin  "mux#16" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(14)} -pin  "mux#16" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(15)} -pin  "mux#16" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load inst "reg(r(2).lpi#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 39998 -attr oid 485 -attr vt d -attr @path {/sobel/sobel:core/reg(r(2).lpi#1)}
+load net {mux#16.itm(0)} -pin  "reg(r(2).lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(1)} -pin  "reg(r(2).lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(2)} -pin  "reg(r(2).lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(3)} -pin  "reg(r(2).lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(4)} -pin  "reg(r(2).lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(5)} -pin  "reg(r(2).lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(6)} -pin  "reg(r(2).lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(7)} -pin  "reg(r(2).lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(8)} -pin  "reg(r(2).lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(9)} -pin  "reg(r(2).lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(10)} -pin  "reg(r(2).lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(11)} -pin  "reg(r(2).lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(12)} -pin  "reg(r(2).lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(13)} -pin  "reg(r(2).lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(14)} -pin  "reg(r(2).lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {mux#16.itm(15)} -pin  "reg(r(2).lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#16.itm}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(2).lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(r(2).lpi#1)" {clk} -attr xrf 39999 -attr oid 486 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(r(2).lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(r(2).lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {r(2).lpi#1(0)} -pin  "reg(r(2).lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(1)} -pin  "reg(r(2).lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(2)} -pin  "reg(r(2).lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(3)} -pin  "reg(r(2).lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(4)} -pin  "reg(r(2).lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(5)} -pin  "reg(r(2).lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(6)} -pin  "reg(r(2).lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(7)} -pin  "reg(r(2).lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(8)} -pin  "reg(r(2).lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(9)} -pin  "reg(r(2).lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(10)} -pin  "reg(r(2).lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(11)} -pin  "reg(r(2).lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(12)} -pin  "reg(r(2).lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(13)} -pin  "reg(r(2).lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(14)} -pin  "reg(r(2).lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(15)} -pin  "reg(r(2).lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load inst "regs.operator[]#6:mux" "mux(4,10)" "INTERFACE" -attr xrf 40000 -attr oid 487 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#6:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#6:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#6:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#6:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#6:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#6:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#6:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#6:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#6:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#6:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "regs.operator[]#6:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "regs.operator[]#6:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "regs.operator[]#6:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "regs.operator[]#6:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "regs.operator[]#6:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "regs.operator[]#6:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "regs.operator[]#6:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "regs.operator[]#6:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "regs.operator[]#6:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "regs.operator[]#6:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "regs.operator[]#6:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "regs.operator[]#6:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "regs.operator[]#6:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "regs.operator[]#6:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "regs.operator[]#6:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "regs.operator[]#6:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "regs.operator[]#6:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "regs.operator[]#6:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "regs.operator[]#6:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "regs.operator[]#6:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "regs.operator[]#6:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "regs.operator[]#6:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "regs.operator[]#6:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "regs.operator[]#6:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "regs.operator[]#6:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "regs.operator[]#6:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "regs.operator[]#6:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "regs.operator[]#6:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "regs.operator[]#6:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "regs.operator[]#6:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva.dfm:mx0)#8.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "regs.operator[]#6:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "regs.operator[]#6:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {regs.operator[]#6:mux.itm(0)} -pin  "regs.operator[]#6:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(1)} -pin  "regs.operator[]#6:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(2)} -pin  "regs.operator[]#6:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(3)} -pin  "regs.operator[]#6:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(4)} -pin  "regs.operator[]#6:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(5)} -pin  "regs.operator[]#6:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(6)} -pin  "regs.operator[]#6:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(7)} -pin  "regs.operator[]#6:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(8)} -pin  "regs.operator[]#6:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(9)} -pin  "regs.operator[]#6:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load inst "FRAME:for:mul" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 40001 -attr oid 488 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#6:mux.itm(0)} -pin  "FRAME:for:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(1)} -pin  "FRAME:for:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(2)} -pin  "FRAME:for:mul" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(3)} -pin  "FRAME:for:mul" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(4)} -pin  "FRAME:for:mul" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(5)} -pin  "FRAME:for:mul" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(6)} -pin  "FRAME:for:mul" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(7)} -pin  "FRAME:for:mul" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(8)} -pin  "FRAME:for:mul" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {regs.operator[]#6:mux.itm(9)} -pin  "FRAME:for:mul" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#6:mux.itm}
+load net {FRAME:for:or.itm} -pin  "FRAME:for:mul" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#30}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:mul" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:conc#30}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load inst "FRAME:for:acc#1" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 40002 -attr oid 489 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {r(0).lpi#1.dfm(0)} -pin  "FRAME:for:acc#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(1)} -pin  "FRAME:for:acc#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(2)} -pin  "FRAME:for:acc#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(3)} -pin  "FRAME:for:acc#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(4)} -pin  "FRAME:for:acc#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(5)} -pin  "FRAME:for:acc#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(6)} -pin  "FRAME:for:acc#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(7)} -pin  "FRAME:for:acc#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(8)} -pin  "FRAME:for:acc#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(9)} -pin  "FRAME:for:acc#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(10)} -pin  "FRAME:for:acc#1" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(11)} -pin  "FRAME:for:acc#1" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(12)} -pin  "FRAME:for:acc#1" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(13)} -pin  "FRAME:for:acc#1" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(14)} -pin  "FRAME:for:acc#1" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(15)} -pin  "FRAME:for:acc#1" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {FRAME:for:mul.itm(0)} -pin  "FRAME:for:acc#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(1)} -pin  "FRAME:for:acc#1" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(2)} -pin  "FRAME:for:acc#1" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(3)} -pin  "FRAME:for:acc#1" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(4)} -pin  "FRAME:for:acc#1" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(5)} -pin  "FRAME:for:acc#1" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(6)} -pin  "FRAME:for:acc#1" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(7)} -pin  "FRAME:for:acc#1" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(8)} -pin  "FRAME:for:acc#1" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(9)} -pin  "FRAME:for:acc#1" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:mul.itm(10)} -pin  "FRAME:for:acc#1" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:mul.itm}
+load net {FRAME:for:acc#1.itm(0)} -pin  "FRAME:for:acc#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(1)} -pin  "FRAME:for:acc#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(2)} -pin  "FRAME:for:acc#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(3)} -pin  "FRAME:for:acc#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(4)} -pin  "FRAME:for:acc#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(5)} -pin  "FRAME:for:acc#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(6)} -pin  "FRAME:for:acc#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(7)} -pin  "FRAME:for:acc#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(8)} -pin  "FRAME:for:acc#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(9)} -pin  "FRAME:for:acc#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(10)} -pin  "FRAME:for:acc#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(11)} -pin  "FRAME:for:acc#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(12)} -pin  "FRAME:for:acc#1" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(13)} -pin  "FRAME:for:acc#1" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(14)} -pin  "FRAME:for:acc#1" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(15)} -pin  "FRAME:for:acc#1" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load inst "mux#17" "mux(2,16)" "INTERFACE" -attr xrf 40003 -attr oid 490 -attr vt d -attr @path {/sobel/sobel:core/mux#17} -attr area 14.711768 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(16,1,2)"
+load net {FRAME:for:acc#1.itm(0)} -pin  "mux#17" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(1)} -pin  "mux#17" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(2)} -pin  "mux#17" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(3)} -pin  "mux#17" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(4)} -pin  "mux#17" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(5)} -pin  "mux#17" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(6)} -pin  "mux#17" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(7)} -pin  "mux#17" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(8)} -pin  "mux#17" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(9)} -pin  "mux#17" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(10)} -pin  "mux#17" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(11)} -pin  "mux#17" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(12)} -pin  "mux#17" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(13)} -pin  "mux#17" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(14)} -pin  "mux#17" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {FRAME:for:acc#1.itm(15)} -pin  "mux#17" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#1.itm}
+load net {r(0).sva#1(0)} -pin  "mux#17" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(1)} -pin  "mux#17" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(2)} -pin  "mux#17" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(3)} -pin  "mux#17" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(4)} -pin  "mux#17" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(5)} -pin  "mux#17" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(6)} -pin  "mux#17" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(7)} -pin  "mux#17" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(8)} -pin  "mux#17" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(9)} -pin  "mux#17" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(10)} -pin  "mux#17" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(11)} -pin  "mux#17" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(12)} -pin  "mux#17" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(13)} -pin  "mux#17" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(14)} -pin  "mux#17" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(15)} -pin  "mux#17" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {or#4.cse} -pin  "mux#17" {S(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load net {mux#17.itm(0)} -pin  "mux#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(1)} -pin  "mux#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(2)} -pin  "mux#17" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(3)} -pin  "mux#17" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(4)} -pin  "mux#17" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(5)} -pin  "mux#17" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(6)} -pin  "mux#17" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(7)} -pin  "mux#17" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(8)} -pin  "mux#17" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(9)} -pin  "mux#17" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(10)} -pin  "mux#17" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(11)} -pin  "mux#17" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(12)} -pin  "mux#17" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(13)} -pin  "mux#17" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(14)} -pin  "mux#17" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(15)} -pin  "mux#17" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load inst "reg(r(0).lpi#1)" "reg(16,1,1,-1,0)" "INTERFACE" -attr xrf 40004 -attr oid 491 -attr vt d -attr @path {/sobel/sobel:core/reg(r(0).lpi#1)}
+load net {mux#17.itm(0)} -pin  "reg(r(0).lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(1)} -pin  "reg(r(0).lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(2)} -pin  "reg(r(0).lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(3)} -pin  "reg(r(0).lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(4)} -pin  "reg(r(0).lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(5)} -pin  "reg(r(0).lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(6)} -pin  "reg(r(0).lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(7)} -pin  "reg(r(0).lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(8)} -pin  "reg(r(0).lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(9)} -pin  "reg(r(0).lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(10)} -pin  "reg(r(0).lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(11)} -pin  "reg(r(0).lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(12)} -pin  "reg(r(0).lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(13)} -pin  "reg(r(0).lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(14)} -pin  "reg(r(0).lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {mux#17.itm(15)} -pin  "reg(r(0).lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#17.itm}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_16}
+load net {GND} -pin  "reg(r(0).lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_16}
+load net {clk} -pin  "reg(r(0).lpi#1)" {clk} -attr xrf 40005 -attr oid 492 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(r(0).lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(r(0).lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {r(0).lpi#1(0)} -pin  "reg(r(0).lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(1)} -pin  "reg(r(0).lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(2)} -pin  "reg(r(0).lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(3)} -pin  "reg(r(0).lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(4)} -pin  "reg(r(0).lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(5)} -pin  "reg(r(0).lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(6)} -pin  "reg(r(0).lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(7)} -pin  "reg(r(0).lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(8)} -pin  "reg(r(0).lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(9)} -pin  "reg(r(0).lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(10)} -pin  "reg(r(0).lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(11)} -pin  "reg(r(0).lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(12)} -pin  "reg(r(0).lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(13)} -pin  "reg(r(0).lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(14)} -pin  "reg(r(0).lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(15)} -pin  "reg(r(0).lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load inst "not" "not(1)" "INTERFACE" -attr @path {/sobel/sobel:core/not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for#1:acc.itm(1)} -pin  "not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:slc#2.itm}
+load net {not.itm} -pin  "not" {Z(0)} -attr @path {/sobel/sobel:core/not.itm}
+load inst "and#3" "and(3,1)" "INTERFACE" -attr @path {/sobel/sobel:core/and#3} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,3)"
+load net {and.dcpl#1} -pin  "and#3" {A0(0)} -attr @path {/sobel/sobel:core/and.dcpl#1}
+load net {exit:FRAME:for.lpi#1} -pin  "and#3" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1}
+load net {not.itm} -pin  "and#3" {A2(0)} -attr @path {/sobel/sobel:core/not.itm}
+load net {and#3.itm} -pin  "and#3" {Z(0)} -attr @path {/sobel/sobel:core/and#3.itm}
+load inst "mux#18" "mux(2,19)" "INTERFACE" -attr xrf 40006 -attr oid 493 -attr vt d -attr @path {/sobel/sobel:core/mux#18} -attr area 17.470037 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(19,1,2)"
+load net {FRAME:p#1.sva#1(0)} -pin  "mux#18" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "mux#18" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "mux#18" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "mux#18" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "mux#18" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "mux#18" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "mux#18" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "mux#18" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "mux#18" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "mux#18" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "mux#18" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "mux#18" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "mux#18" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "mux#18" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "mux#18" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "mux#18" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "mux#18" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "mux#18" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "mux#18" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "mux#18" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "mux#18" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "mux#18" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "mux#18" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "mux#18" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "mux#18" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "mux#18" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "mux#18" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "mux#18" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "mux#18" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "mux#18" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "mux#18" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "mux#18" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "mux#18" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "mux#18" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "mux#18" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "mux#18" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "mux#18" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "mux#18" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {and#3.itm} -pin  "mux#18" {S(0)} -attr @path {/sobel/sobel:core/and#3.itm}
+load net {mux#18.itm(0)} -pin  "mux#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(1)} -pin  "mux#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(2)} -pin  "mux#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(3)} -pin  "mux#18" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(4)} -pin  "mux#18" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(5)} -pin  "mux#18" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(6)} -pin  "mux#18" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(7)} -pin  "mux#18" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(8)} -pin  "mux#18" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(9)} -pin  "mux#18" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(10)} -pin  "mux#18" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(11)} -pin  "mux#18" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(12)} -pin  "mux#18" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(13)} -pin  "mux#18" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(14)} -pin  "mux#18" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(15)} -pin  "mux#18" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(16)} -pin  "mux#18" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(17)} -pin  "mux#18" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(18)} -pin  "mux#18" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load inst "reg(FRAME:p#1.lpi#1)" "reg(19,1,1,-1,0)" "INTERFACE" -attr xrf 40007 -attr oid 494 -attr vt d -attr @path {/sobel/sobel:core/reg(FRAME:p#1.lpi#1)}
+load net {mux#18.itm(0)} -pin  "reg(FRAME:p#1.lpi#1)" {D(0)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(1)} -pin  "reg(FRAME:p#1.lpi#1)" {D(1)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(2)} -pin  "reg(FRAME:p#1.lpi#1)" {D(2)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(3)} -pin  "reg(FRAME:p#1.lpi#1)" {D(3)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(4)} -pin  "reg(FRAME:p#1.lpi#1)" {D(4)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(5)} -pin  "reg(FRAME:p#1.lpi#1)" {D(5)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(6)} -pin  "reg(FRAME:p#1.lpi#1)" {D(6)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(7)} -pin  "reg(FRAME:p#1.lpi#1)" {D(7)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(8)} -pin  "reg(FRAME:p#1.lpi#1)" {D(8)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(9)} -pin  "reg(FRAME:p#1.lpi#1)" {D(9)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(10)} -pin  "reg(FRAME:p#1.lpi#1)" {D(10)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(11)} -pin  "reg(FRAME:p#1.lpi#1)" {D(11)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(12)} -pin  "reg(FRAME:p#1.lpi#1)" {D(12)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(13)} -pin  "reg(FRAME:p#1.lpi#1)" {D(13)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(14)} -pin  "reg(FRAME:p#1.lpi#1)" {D(14)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(15)} -pin  "reg(FRAME:p#1.lpi#1)" {D(15)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(16)} -pin  "reg(FRAME:p#1.lpi#1)" {D(16)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(17)} -pin  "reg(FRAME:p#1.lpi#1)" {D(17)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {mux#18.itm(18)} -pin  "reg(FRAME:p#1.lpi#1)" {D(18)} -attr vt d -attr @path {/sobel/sobel:core/mux#18.itm}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(0)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(1)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(2)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(3)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(4)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(5)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(6)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(7)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(8)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(9)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(10)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(11)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(12)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(13)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(14)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(15)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(16)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(17)} -attr @path {/sobel/sobel:core/C0_19}
+load net {GND} -pin  "reg(FRAME:p#1.lpi#1)" {DRa(18)} -attr @path {/sobel/sobel:core/C0_19}
+load net {clk} -pin  "reg(FRAME:p#1.lpi#1)" {clk} -attr xrf 40008 -attr oid 495 -attr @path {/sobel/sobel:core/clk}
+load net {en} -pin  "reg(FRAME:p#1.lpi#1)" {en(0)} -attr @path {/sobel/sobel:core/en}
+load net {arst_n} -pin  "reg(FRAME:p#1.lpi#1)" {Ra(0)} -attr @path {/sobel/sobel:core/arst_n}
+load net {FRAME:p#1.lpi#1(0)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "reg(FRAME:p#1.lpi#1)" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load inst "FRAME:acc#19" "add(5,-1,5,-1,5)" "INTERFACE" -attr xrf 40009 -attr oid 496 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19} -attr area 6.284690 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5)"
+load net {FRAME:acc#18.itm#1(0)} -pin  "FRAME:acc#19" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(1)} -pin  "FRAME:acc#19" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(2)} -pin  "FRAME:acc#19" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(3)} -pin  "FRAME:acc#19" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:acc#18.itm#1(4)} -pin  "FRAME:acc#19" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#18.itm#1}
+load net {FRAME:slc(acc.imod#5)#4.itm#1} -pin  "FRAME:acc#19" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {PWR} -pin  "FRAME:acc#19" {B(1)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {GND} -pin  "FRAME:acc#19" {B(2)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {GND} -pin  "FRAME:acc#19" {B(3)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {PWR} -pin  "FRAME:acc#19" {B(4)} -attr @path {/sobel/sobel:core/conc#147.itm}
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#19" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#19" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#19" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(3)} -pin  "FRAME:acc#19" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(4)} -pin  "FRAME:acc#19" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load inst "FRAME:acc#20" "add(6,0,5,1,8)" "INTERFACE" -attr xrf 40010 -attr oid 497 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20} -attr area 7.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,5,1,8)"
+load net {green:slc(green#2.sg1).itm#1(0)} -pin  "FRAME:acc#20" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(1)} -pin  "FRAME:acc#20" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(2)} -pin  "FRAME:acc#20" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(3)} -pin  "FRAME:acc#20" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(4)} -pin  "FRAME:acc#20" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {green:slc(green#2.sg1).itm#1(5)} -pin  "FRAME:acc#20" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/green:slc(green#2.sg1).itm#1}
+load net {FRAME:acc#19.itm(0)} -pin  "FRAME:acc#20" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(1)} -pin  "FRAME:acc#20" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(2)} -pin  "FRAME:acc#20" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(3)} -pin  "FRAME:acc#20" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#19.itm(4)} -pin  "FRAME:acc#20" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#19.itm}
+load net {FRAME:acc#20.itm(0)} -pin  "FRAME:acc#20" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(1)} -pin  "FRAME:acc#20" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(2)} -pin  "FRAME:acc#20" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(3)} -pin  "FRAME:acc#20" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(4)} -pin  "FRAME:acc#20" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(5)} -pin  "FRAME:acc#20" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(6)} -pin  "FRAME:acc#20" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load net {FRAME:acc#20.itm(7)} -pin  "FRAME:acc#20" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#20.itm}
+load inst "FRAME:acc#21" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 40011 -attr oid 498 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#21} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul#3.itm#1(0)} -pin  "FRAME:acc#21" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(1)} -pin  "FRAME:acc#21" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(2)} -pin  "FRAME:acc#21" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(3)} -pin  "FRAME:acc#21" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(4)} -pin  "FRAME:acc#21" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(5)} -pin  "FRAME:acc#21" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(6)} -pin  "FRAME:acc#21" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(7)} -pin  "FRAME:acc#21" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
+load net {FRAME:mul#3.itm#1(8)} -pin  "FRAME:acc#21" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#3.itm#1}
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+load inst "FRAME:acc#33" "add(9,0,8,1,10)" "INTERFACE" -attr xrf 40016 -attr oid 503 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33} -attr area 10.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(9,0,8,1,10)"
+load net {FRAME:mul#5.itm#1(0)} -pin  "FRAME:acc#33" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(1)} -pin  "FRAME:acc#33" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(2)} -pin  "FRAME:acc#33" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(3)} -pin  "FRAME:acc#33" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(4)} -pin  "FRAME:acc#33" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(5)} -pin  "FRAME:acc#33" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(6)} -pin  "FRAME:acc#33" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(7)} -pin  "FRAME:acc#33" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:mul#5.itm#1(8)} -pin  "FRAME:acc#33" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#5.itm#1}
+load net {FRAME:acc#32.itm(0)} -pin  "FRAME:acc#33" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(1)} -pin  "FRAME:acc#33" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(2)} -pin  "FRAME:acc#33" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(3)} -pin  "FRAME:acc#33" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(4)} -pin  "FRAME:acc#33" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(5)} -pin  "FRAME:acc#33" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(6)} -pin  "FRAME:acc#33" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#32.itm(7)} -pin  "FRAME:acc#33" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#32.itm}
+load net {FRAME:acc#33.itm(0)} -pin  "FRAME:acc#33" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(1)} -pin  "FRAME:acc#33" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(2)} -pin  "FRAME:acc#33" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(3)} -pin  "FRAME:acc#33" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(4)} -pin  "FRAME:acc#33" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(5)} -pin  "FRAME:acc#33" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(6)} -pin  "FRAME:acc#33" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(7)} -pin  "FRAME:acc#33" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(8)} -pin  "FRAME:acc#33" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(9)} -pin  "FRAME:acc#33" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load inst "FRAME:acc#34" "add(11,0,10,1,12)" "INTERFACE" -attr xrf 40017 -attr oid 504 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34} -attr area 12.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,1,12)"
+load net {FRAME:mul#4.itm#1(0)} -pin  "FRAME:acc#34" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(1)} -pin  "FRAME:acc#34" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(2)} -pin  "FRAME:acc#34" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(3)} -pin  "FRAME:acc#34" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(4)} -pin  "FRAME:acc#34" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(5)} -pin  "FRAME:acc#34" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(6)} -pin  "FRAME:acc#34" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(7)} -pin  "FRAME:acc#34" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(8)} -pin  "FRAME:acc#34" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(9)} -pin  "FRAME:acc#34" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:mul#4.itm#1(10)} -pin  "FRAME:acc#34" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul#4.itm#1}
+load net {FRAME:acc#33.itm(0)} -pin  "FRAME:acc#34" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(1)} -pin  "FRAME:acc#34" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(2)} -pin  "FRAME:acc#34" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(3)} -pin  "FRAME:acc#34" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(4)} -pin  "FRAME:acc#34" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(5)} -pin  "FRAME:acc#34" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(6)} -pin  "FRAME:acc#34" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(7)} -pin  "FRAME:acc#34" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(8)} -pin  "FRAME:acc#34" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#33.itm(9)} -pin  "FRAME:acc#34" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#33.itm}
+load net {FRAME:acc#34.itm(0)} -pin  "FRAME:acc#34" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(1)} -pin  "FRAME:acc#34" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(2)} -pin  "FRAME:acc#34" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(3)} -pin  "FRAME:acc#34" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(4)} -pin  "FRAME:acc#34" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(5)} -pin  "FRAME:acc#34" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(6)} -pin  "FRAME:acc#34" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(7)} -pin  "FRAME:acc#34" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(8)} -pin  "FRAME:acc#34" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(9)} -pin  "FRAME:acc#34" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(10)} -pin  "FRAME:acc#34" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(11)} -pin  "FRAME:acc#34" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load inst "FRAME:acc#4" "add(12,-1,11,0,12)" "INTERFACE" -attr xrf 40018 -attr oid 505 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4} -attr area 13.227600 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,11,0,12)"
+load net {FRAME:acc#34.itm(0)} -pin  "FRAME:acc#4" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(1)} -pin  "FRAME:acc#4" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(2)} -pin  "FRAME:acc#4" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(3)} -pin  "FRAME:acc#4" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(4)} -pin  "FRAME:acc#4" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(5)} -pin  "FRAME:acc#4" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(6)} -pin  "FRAME:acc#4" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(7)} -pin  "FRAME:acc#4" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(8)} -pin  "FRAME:acc#4" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(9)} -pin  "FRAME:acc#4" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(10)} -pin  "FRAME:acc#4" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {FRAME:acc#34.itm(11)} -pin  "FRAME:acc#4" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#34.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(1)} -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(5)} -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(6)} -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {GND} -pin  "FRAME:acc#4" {B(7)} -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {blue:slc(blue#2.sg1)#12.itm#1} -pin  "FRAME:acc#4" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/exs#5.itm}
+load net {FRAME:acc#4.psp.sva(0)} -pin  "FRAME:acc#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(1)} -pin  "FRAME:acc#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(2)} -pin  "FRAME:acc#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(3)} -pin  "FRAME:acc#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(4)} -pin  "FRAME:acc#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(5)} -pin  "FRAME:acc#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(6)} -pin  "FRAME:acc#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(7)} -pin  "FRAME:acc#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(8)} -pin  "FRAME:acc#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(9)} -pin  "FRAME:acc#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(10)} -pin  "FRAME:acc#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load net {FRAME:acc#4.psp.sva(11)} -pin  "FRAME:acc#4" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#4.psp.sva}
+load inst "FRAME:for#1:acc" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 40019 -attr oid 506 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2)"
+load net {i#7.sva(0)} -pin  "FRAME:for#1:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load net {i#7.sva(1)} -pin  "FRAME:for#1:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load net {PWR} -pin  "FRAME:for#1:acc" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:for#1:acc.itm(0)} -pin  "FRAME:for#1:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc.itm}
+load net {FRAME:for#1:acc.itm(1)} -pin  "FRAME:for#1:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc.itm}
+load inst "FRAME:for:and#12" "and(2,1)" "INTERFACE" -attr xrf 40020 -attr oid 507 -attr @path {/sobel/sobel:core/FRAME:for:and#12} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {exit:FRAME:for.lpi#1} -pin  "FRAME:for:and#12" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1}
+load net {not#24} -pin  "FRAME:for:and#12" {A1(0)} -attr @path {/sobel/sobel:core/not#24}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:and#12" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load inst "FRAME:for#1:acc#16" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 40021 -attr oid 508 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc#16} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2)"
+load net {i#7.lpi#1(0)} -pin  "FRAME:for#1:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "FRAME:for#1:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {PWR} -pin  "FRAME:for#1:acc#16" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {i#7.sva(0)} -pin  "FRAME:for#1:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load net {i#7.sva(1)} -pin  "FRAME:for#1:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.sva}
+load inst "FRAME:for:or#2" "or(2,1)" "INTERFACE" -attr xrf 40022 -attr oid 509 -attr @path {/sobel/sobel:core/FRAME:for:or#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {exit:FRAME:for#1.lpi#1.dfm#5} -pin  "FRAME:for:or#2" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#5}
+load net {FRAME:acc.itm(7)} -pin  "FRAME:for:or#2" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:slc.itm}
+load net {FRAME:for:or#2.itm} -pin  "FRAME:for:or#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#2.itm}
+load inst "mux#3" "mux(2,1)" "INTERFACE" -attr xrf 40023 -attr oid 510 -attr @path {/sobel/sobel:core/mux#3} -attr area 0.920423 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2)"
+load net {exit:FRAME:for#1.lpi#1.dfm#5} -pin  "mux#3" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#5}
+load net {FRAME:for:or#2.itm} -pin  "mux#3" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#2.itm}
+load net {or#9.cse} -pin  "mux#3" {S(0)} -attr @path {/sobel/sobel:core/or#9.cse}
+load net {exit:FRAME:for#1.lpi#1.dfm#4:mx0} -pin  "mux#3" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4:mx0}
+load inst "mux#4" "mux(2,90)" "INTERFACE" -attr xrf 40024 -attr oid 511 -attr vt d -attr @path {/sobel/sobel:core/mux#4} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(2).lpi#1.dfm(0)} -pin  "mux#4" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(1)} -pin  "mux#4" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(2)} -pin  "mux#4" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(3)} -pin  "mux#4" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(4)} -pin  "mux#4" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(5)} -pin  "mux#4" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(6)} -pin  "mux#4" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(7)} -pin  "mux#4" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(8)} -pin  "mux#4" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(9)} -pin  "mux#4" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(10)} -pin  "mux#4" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(11)} -pin  "mux#4" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(12)} -pin  "mux#4" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(13)} -pin  "mux#4" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(14)} -pin  "mux#4" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(15)} -pin  "mux#4" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(16)} -pin  "mux#4" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(17)} -pin  "mux#4" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(18)} -pin  "mux#4" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(19)} -pin  "mux#4" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(20)} -pin  "mux#4" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(21)} -pin  "mux#4" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(22)} -pin  "mux#4" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(23)} -pin  "mux#4" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(24)} -pin  "mux#4" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(25)} -pin  "mux#4" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(26)} -pin  "mux#4" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(27)} -pin  "mux#4" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(28)} -pin  "mux#4" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(29)} -pin  "mux#4" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(30)} -pin  "mux#4" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(31)} -pin  "mux#4" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(32)} -pin  "mux#4" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(33)} -pin  "mux#4" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(34)} -pin  "mux#4" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(35)} -pin  "mux#4" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(36)} -pin  "mux#4" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(37)} -pin  "mux#4" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(38)} -pin  "mux#4" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(39)} -pin  "mux#4" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(40)} -pin  "mux#4" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(41)} -pin  "mux#4" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(42)} -pin  "mux#4" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(43)} -pin  "mux#4" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(44)} -pin  "mux#4" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(45)} -pin  "mux#4" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(46)} -pin  "mux#4" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(47)} -pin  "mux#4" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(48)} -pin  "mux#4" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(49)} -pin  "mux#4" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(50)} -pin  "mux#4" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(51)} -pin  "mux#4" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(52)} -pin  "mux#4" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(53)} -pin  "mux#4" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(54)} -pin  "mux#4" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(55)} -pin  "mux#4" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(56)} -pin  "mux#4" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(57)} -pin  "mux#4" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(58)} -pin  "mux#4" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(59)} -pin  "mux#4" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(60)} -pin  "mux#4" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(61)} -pin  "mux#4" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(62)} -pin  "mux#4" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(63)} -pin  "mux#4" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(64)} -pin  "mux#4" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(65)} -pin  "mux#4" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(66)} -pin  "mux#4" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(67)} -pin  "mux#4" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(68)} -pin  "mux#4" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(69)} -pin  "mux#4" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(70)} -pin  "mux#4" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(71)} -pin  "mux#4" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(72)} -pin  "mux#4" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(73)} -pin  "mux#4" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(74)} -pin  "mux#4" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(75)} -pin  "mux#4" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(76)} -pin  "mux#4" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(77)} -pin  "mux#4" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(78)} -pin  "mux#4" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(79)} -pin  "mux#4" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(80)} -pin  "mux#4" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(81)} -pin  "mux#4" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(82)} -pin  "mux#4" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(83)} -pin  "mux#4" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(84)} -pin  "mux#4" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(85)} -pin  "mux#4" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(86)} -pin  "mux#4" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(87)} -pin  "mux#4" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(88)} -pin  "mux#4" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(2).lpi#1.dfm(89)} -pin  "mux#4" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm}
+load net {regs.regs(1).sva(0)} -pin  "mux#4" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "mux#4" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "mux#4" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "mux#4" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "mux#4" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "mux#4" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "mux#4" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "mux#4" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "mux#4" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "mux#4" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "mux#4" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "mux#4" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "mux#4" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "mux#4" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "mux#4" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "mux#4" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "mux#4" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "mux#4" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "mux#4" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "mux#4" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "mux#4" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "mux#4" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "mux#4" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "mux#4" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "mux#4" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "mux#4" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "mux#4" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "mux#4" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "mux#4" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "mux#4" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "mux#4" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "mux#4" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "mux#4" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "mux#4" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "mux#4" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "mux#4" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "mux#4" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "mux#4" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "mux#4" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "mux#4" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "mux#4" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "mux#4" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "mux#4" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "mux#4" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "mux#4" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "mux#4" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "mux#4" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "mux#4" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "mux#4" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "mux#4" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "mux#4" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "mux#4" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "mux#4" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "mux#4" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "mux#4" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "mux#4" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "mux#4" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "mux#4" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "mux#4" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "mux#4" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "mux#4" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "mux#4" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "mux#4" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "mux#4" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "mux#4" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "mux#4" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "mux#4" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "mux#4" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "mux#4" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "mux#4" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "mux#4" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "mux#4" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "mux#4" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "mux#4" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "mux#4" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "mux#4" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "mux#4" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "mux#4" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "mux#4" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "mux#4" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "mux#4" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "mux#4" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "mux#4" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "mux#4" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "mux#4" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "mux#4" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "mux#4" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "mux#4" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "mux#4" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "mux#4" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {and.dcpl#1} -pin  "mux#4" {S(0)} -attr @path {/sobel/sobel:core/and.dcpl#1}
+load net {regs.regs(2).lpi#1.dfm:mx0(0)} -pin  "mux#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(1)} -pin  "mux#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(2)} -pin  "mux#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(3)} -pin  "mux#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(4)} -pin  "mux#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(5)} -pin  "mux#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(6)} -pin  "mux#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(7)} -pin  "mux#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(8)} -pin  "mux#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(9)} -pin  "mux#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(10)} -pin  "mux#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(11)} -pin  "mux#4" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(12)} -pin  "mux#4" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(13)} -pin  "mux#4" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(14)} -pin  "mux#4" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(15)} -pin  "mux#4" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(16)} -pin  "mux#4" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(17)} -pin  "mux#4" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(18)} -pin  "mux#4" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(19)} -pin  "mux#4" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(20)} -pin  "mux#4" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(21)} -pin  "mux#4" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(22)} -pin  "mux#4" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(23)} -pin  "mux#4" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(24)} -pin  "mux#4" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(25)} -pin  "mux#4" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(26)} -pin  "mux#4" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(27)} -pin  "mux#4" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(28)} -pin  "mux#4" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(29)} -pin  "mux#4" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(30)} -pin  "mux#4" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(31)} -pin  "mux#4" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(32)} -pin  "mux#4" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(33)} -pin  "mux#4" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(34)} -pin  "mux#4" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(35)} -pin  "mux#4" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(36)} -pin  "mux#4" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(37)} -pin  "mux#4" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(38)} -pin  "mux#4" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(39)} -pin  "mux#4" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(40)} -pin  "mux#4" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(41)} -pin  "mux#4" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(42)} -pin  "mux#4" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(43)} -pin  "mux#4" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(44)} -pin  "mux#4" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(45)} -pin  "mux#4" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(46)} -pin  "mux#4" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(47)} -pin  "mux#4" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(48)} -pin  "mux#4" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(49)} -pin  "mux#4" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(50)} -pin  "mux#4" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(51)} -pin  "mux#4" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(52)} -pin  "mux#4" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(53)} -pin  "mux#4" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(54)} -pin  "mux#4" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(55)} -pin  "mux#4" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(56)} -pin  "mux#4" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(57)} -pin  "mux#4" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(58)} -pin  "mux#4" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(59)} -pin  "mux#4" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(60)} -pin  "mux#4" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(61)} -pin  "mux#4" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(62)} -pin  "mux#4" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(63)} -pin  "mux#4" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(64)} -pin  "mux#4" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(65)} -pin  "mux#4" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(66)} -pin  "mux#4" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(67)} -pin  "mux#4" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(68)} -pin  "mux#4" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(69)} -pin  "mux#4" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(70)} -pin  "mux#4" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(71)} -pin  "mux#4" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(72)} -pin  "mux#4" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(73)} -pin  "mux#4" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(74)} -pin  "mux#4" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(75)} -pin  "mux#4" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(76)} -pin  "mux#4" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(77)} -pin  "mux#4" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(78)} -pin  "mux#4" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(79)} -pin  "mux#4" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(80)} -pin  "mux#4" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(81)} -pin  "mux#4" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(82)} -pin  "mux#4" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(83)} -pin  "mux#4" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(84)} -pin  "mux#4" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(85)} -pin  "mux#4" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(86)} -pin  "mux#4" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(87)} -pin  "mux#4" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(88)} -pin  "mux#4" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load net {regs.regs(2).lpi#1.dfm:mx0(89)} -pin  "mux#4" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(2).lpi#1.dfm:mx0}
+load inst "mux#5" "mux(2,90)" "INTERFACE" -attr xrf 40025 -attr oid 512 -attr vt d -attr @path {/sobel/sobel:core/mux#5} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(1).sva(0)} -pin  "mux#5" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(1)} -pin  "mux#5" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(2)} -pin  "mux#5" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(3)} -pin  "mux#5" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(4)} -pin  "mux#5" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(5)} -pin  "mux#5" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(6)} -pin  "mux#5" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(7)} -pin  "mux#5" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(8)} -pin  "mux#5" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(9)} -pin  "mux#5" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(10)} -pin  "mux#5" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(11)} -pin  "mux#5" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(12)} -pin  "mux#5" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(13)} -pin  "mux#5" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(14)} -pin  "mux#5" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(15)} -pin  "mux#5" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(16)} -pin  "mux#5" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(17)} -pin  "mux#5" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(18)} -pin  "mux#5" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(19)} -pin  "mux#5" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(20)} -pin  "mux#5" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(21)} -pin  "mux#5" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(22)} -pin  "mux#5" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(23)} -pin  "mux#5" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(24)} -pin  "mux#5" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(25)} -pin  "mux#5" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(26)} -pin  "mux#5" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(27)} -pin  "mux#5" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(28)} -pin  "mux#5" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(29)} -pin  "mux#5" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(30)} -pin  "mux#5" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(31)} -pin  "mux#5" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(32)} -pin  "mux#5" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(33)} -pin  "mux#5" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(34)} -pin  "mux#5" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(35)} -pin  "mux#5" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(36)} -pin  "mux#5" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(37)} -pin  "mux#5" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(38)} -pin  "mux#5" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(39)} -pin  "mux#5" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(40)} -pin  "mux#5" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(41)} -pin  "mux#5" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(42)} -pin  "mux#5" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(43)} -pin  "mux#5" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(44)} -pin  "mux#5" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(45)} -pin  "mux#5" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(46)} -pin  "mux#5" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(47)} -pin  "mux#5" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(48)} -pin  "mux#5" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(49)} -pin  "mux#5" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(50)} -pin  "mux#5" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(51)} -pin  "mux#5" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(52)} -pin  "mux#5" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(53)} -pin  "mux#5" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(54)} -pin  "mux#5" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(55)} -pin  "mux#5" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(56)} -pin  "mux#5" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(57)} -pin  "mux#5" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(58)} -pin  "mux#5" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(59)} -pin  "mux#5" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(60)} -pin  "mux#5" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(61)} -pin  "mux#5" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(62)} -pin  "mux#5" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(63)} -pin  "mux#5" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(64)} -pin  "mux#5" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(65)} -pin  "mux#5" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(66)} -pin  "mux#5" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(67)} -pin  "mux#5" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(68)} -pin  "mux#5" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(69)} -pin  "mux#5" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(70)} -pin  "mux#5" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(71)} -pin  "mux#5" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(72)} -pin  "mux#5" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(73)} -pin  "mux#5" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(74)} -pin  "mux#5" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(75)} -pin  "mux#5" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(76)} -pin  "mux#5" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(77)} -pin  "mux#5" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(78)} -pin  "mux#5" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(79)} -pin  "mux#5" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(80)} -pin  "mux#5" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(81)} -pin  "mux#5" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(82)} -pin  "mux#5" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(83)} -pin  "mux#5" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(84)} -pin  "mux#5" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(85)} -pin  "mux#5" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(86)} -pin  "mux#5" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(87)} -pin  "mux#5" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(88)} -pin  "mux#5" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(1).sva(89)} -pin  "mux#5" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva}
+load net {regs.regs(0).sva(0)} -pin  "mux#5" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#5" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#5" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#5" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#5" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#5" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#5" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#5" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#5" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#5" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#5" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#5" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#5" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#5" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#5" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#5" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#5" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#5" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#5" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#5" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#5" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#5" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#5" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#5" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#5" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#5" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#5" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#5" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#5" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#5" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#5" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#5" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#5" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#5" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#5" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#5" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#5" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#5" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#5" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#5" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#5" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#5" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#5" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#5" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#5" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#5" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#5" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#5" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#5" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#5" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#5" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#5" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#5" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#5" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#5" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#5" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#5" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#5" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#5" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#5" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#5" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#5" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#5" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#5" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#5" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#5" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#5" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#5" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#5" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#5" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#5" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#5" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#5" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#5" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#5" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#5" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#5" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#5" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#5" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#5" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#5" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#5" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#5" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#5" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#5" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#5" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#5" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#5" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#5" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#5" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {and.dcpl#1} -pin  "mux#5" {S(0)} -attr @path {/sobel/sobel:core/and.dcpl#1}
+load net {regs.regs(1).sva.dfm:mx0(0)} -pin  "mux#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(1)} -pin  "mux#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(2)} -pin  "mux#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(3)} -pin  "mux#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(4)} -pin  "mux#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(5)} -pin  "mux#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(6)} -pin  "mux#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(7)} -pin  "mux#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(8)} -pin  "mux#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(9)} -pin  "mux#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(10)} -pin  "mux#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(11)} -pin  "mux#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(12)} -pin  "mux#5" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(13)} -pin  "mux#5" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(14)} -pin  "mux#5" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(15)} -pin  "mux#5" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(16)} -pin  "mux#5" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(17)} -pin  "mux#5" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(18)} -pin  "mux#5" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(19)} -pin  "mux#5" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(20)} -pin  "mux#5" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(21)} -pin  "mux#5" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(22)} -pin  "mux#5" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(23)} -pin  "mux#5" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(24)} -pin  "mux#5" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(25)} -pin  "mux#5" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(26)} -pin  "mux#5" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(27)} -pin  "mux#5" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(28)} -pin  "mux#5" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(29)} -pin  "mux#5" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(30)} -pin  "mux#5" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(31)} -pin  "mux#5" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(32)} -pin  "mux#5" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(33)} -pin  "mux#5" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(34)} -pin  "mux#5" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(35)} -pin  "mux#5" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(36)} -pin  "mux#5" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(37)} -pin  "mux#5" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(38)} -pin  "mux#5" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(39)} -pin  "mux#5" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(40)} -pin  "mux#5" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(41)} -pin  "mux#5" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(42)} -pin  "mux#5" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(43)} -pin  "mux#5" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(44)} -pin  "mux#5" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(45)} -pin  "mux#5" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(46)} -pin  "mux#5" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(47)} -pin  "mux#5" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(48)} -pin  "mux#5" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(49)} -pin  "mux#5" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(50)} -pin  "mux#5" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(51)} -pin  "mux#5" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(52)} -pin  "mux#5" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(53)} -pin  "mux#5" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(54)} -pin  "mux#5" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(55)} -pin  "mux#5" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(56)} -pin  "mux#5" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(57)} -pin  "mux#5" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(58)} -pin  "mux#5" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(59)} -pin  "mux#5" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(60)} -pin  "mux#5" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(61)} -pin  "mux#5" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(62)} -pin  "mux#5" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(63)} -pin  "mux#5" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(64)} -pin  "mux#5" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(65)} -pin  "mux#5" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(66)} -pin  "mux#5" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(67)} -pin  "mux#5" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(68)} -pin  "mux#5" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(69)} -pin  "mux#5" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(70)} -pin  "mux#5" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(71)} -pin  "mux#5" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(72)} -pin  "mux#5" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(73)} -pin  "mux#5" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(74)} -pin  "mux#5" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(75)} -pin  "mux#5" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(76)} -pin  "mux#5" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(77)} -pin  "mux#5" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(78)} -pin  "mux#5" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(79)} -pin  "mux#5" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(80)} -pin  "mux#5" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(81)} -pin  "mux#5" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(82)} -pin  "mux#5" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(83)} -pin  "mux#5" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(84)} -pin  "mux#5" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(85)} -pin  "mux#5" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(86)} -pin  "mux#5" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(87)} -pin  "mux#5" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(88)} -pin  "mux#5" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load net {regs.regs(1).sva.dfm:mx0(89)} -pin  "mux#5" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(1).sva.dfm:mx0}
+load inst "mux#6" "mux(2,90)" "INTERFACE" -attr xrf 40026 -attr oid 513 -attr vt d -attr @path {/sobel/sobel:core/mux#6} -attr area 82.749070 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(90,1,2)"
+load net {regs.regs(0).sva(0)} -pin  "mux#6" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(1)} -pin  "mux#6" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(2)} -pin  "mux#6" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(3)} -pin  "mux#6" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(4)} -pin  "mux#6" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(5)} -pin  "mux#6" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(6)} -pin  "mux#6" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(7)} -pin  "mux#6" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(8)} -pin  "mux#6" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(9)} -pin  "mux#6" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(10)} -pin  "mux#6" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(11)} -pin  "mux#6" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(12)} -pin  "mux#6" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(13)} -pin  "mux#6" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(14)} -pin  "mux#6" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(15)} -pin  "mux#6" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(16)} -pin  "mux#6" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(17)} -pin  "mux#6" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(18)} -pin  "mux#6" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(19)} -pin  "mux#6" {A0(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(20)} -pin  "mux#6" {A0(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(21)} -pin  "mux#6" {A0(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(22)} -pin  "mux#6" {A0(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(23)} -pin  "mux#6" {A0(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(24)} -pin  "mux#6" {A0(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(25)} -pin  "mux#6" {A0(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(26)} -pin  "mux#6" {A0(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(27)} -pin  "mux#6" {A0(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(28)} -pin  "mux#6" {A0(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(29)} -pin  "mux#6" {A0(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(30)} -pin  "mux#6" {A0(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(31)} -pin  "mux#6" {A0(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(32)} -pin  "mux#6" {A0(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(33)} -pin  "mux#6" {A0(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(34)} -pin  "mux#6" {A0(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(35)} -pin  "mux#6" {A0(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(36)} -pin  "mux#6" {A0(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(37)} -pin  "mux#6" {A0(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(38)} -pin  "mux#6" {A0(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(39)} -pin  "mux#6" {A0(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(40)} -pin  "mux#6" {A0(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(41)} -pin  "mux#6" {A0(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(42)} -pin  "mux#6" {A0(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(43)} -pin  "mux#6" {A0(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(44)} -pin  "mux#6" {A0(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(45)} -pin  "mux#6" {A0(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(46)} -pin  "mux#6" {A0(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(47)} -pin  "mux#6" {A0(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(48)} -pin  "mux#6" {A0(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(49)} -pin  "mux#6" {A0(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(50)} -pin  "mux#6" {A0(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(51)} -pin  "mux#6" {A0(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(52)} -pin  "mux#6" {A0(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(53)} -pin  "mux#6" {A0(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(54)} -pin  "mux#6" {A0(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(55)} -pin  "mux#6" {A0(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(56)} -pin  "mux#6" {A0(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(57)} -pin  "mux#6" {A0(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(58)} -pin  "mux#6" {A0(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(59)} -pin  "mux#6" {A0(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(60)} -pin  "mux#6" {A0(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(61)} -pin  "mux#6" {A0(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(62)} -pin  "mux#6" {A0(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(63)} -pin  "mux#6" {A0(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(64)} -pin  "mux#6" {A0(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(65)} -pin  "mux#6" {A0(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(66)} -pin  "mux#6" {A0(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(67)} -pin  "mux#6" {A0(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(68)} -pin  "mux#6" {A0(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(69)} -pin  "mux#6" {A0(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(70)} -pin  "mux#6" {A0(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(71)} -pin  "mux#6" {A0(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(72)} -pin  "mux#6" {A0(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(73)} -pin  "mux#6" {A0(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(74)} -pin  "mux#6" {A0(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(75)} -pin  "mux#6" {A0(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(76)} -pin  "mux#6" {A0(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(77)} -pin  "mux#6" {A0(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(78)} -pin  "mux#6" {A0(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(79)} -pin  "mux#6" {A0(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(80)} -pin  "mux#6" {A0(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(81)} -pin  "mux#6" {A0(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(82)} -pin  "mux#6" {A0(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(83)} -pin  "mux#6" {A0(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(84)} -pin  "mux#6" {A0(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(85)} -pin  "mux#6" {A0(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(86)} -pin  "mux#6" {A0(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(87)} -pin  "mux#6" {A0(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(88)} -pin  "mux#6" {A0(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {regs.regs(0).sva(89)} -pin  "mux#6" {A0(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva}
+load net {vin:rsc:mgc_in_wire.d(0)} -pin  "mux#6" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(1)} -pin  "mux#6" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(2)} -pin  "mux#6" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(3)} -pin  "mux#6" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(4)} -pin  "mux#6" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(5)} -pin  "mux#6" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(6)} -pin  "mux#6" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(7)} -pin  "mux#6" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(8)} -pin  "mux#6" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(9)} -pin  "mux#6" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(10)} -pin  "mux#6" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(11)} -pin  "mux#6" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(12)} -pin  "mux#6" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(13)} -pin  "mux#6" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(14)} -pin  "mux#6" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(15)} -pin  "mux#6" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(16)} -pin  "mux#6" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(17)} -pin  "mux#6" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(18)} -pin  "mux#6" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(19)} -pin  "mux#6" {A1(19)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(20)} -pin  "mux#6" {A1(20)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(21)} -pin  "mux#6" {A1(21)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(22)} -pin  "mux#6" {A1(22)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(23)} -pin  "mux#6" {A1(23)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(24)} -pin  "mux#6" {A1(24)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(25)} -pin  "mux#6" {A1(25)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(26)} -pin  "mux#6" {A1(26)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(27)} -pin  "mux#6" {A1(27)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(28)} -pin  "mux#6" {A1(28)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(29)} -pin  "mux#6" {A1(29)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(30)} -pin  "mux#6" {A1(30)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(31)} -pin  "mux#6" {A1(31)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(32)} -pin  "mux#6" {A1(32)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(33)} -pin  "mux#6" {A1(33)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(34)} -pin  "mux#6" {A1(34)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(35)} -pin  "mux#6" {A1(35)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(36)} -pin  "mux#6" {A1(36)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(37)} -pin  "mux#6" {A1(37)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(38)} -pin  "mux#6" {A1(38)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(39)} -pin  "mux#6" {A1(39)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(40)} -pin  "mux#6" {A1(40)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(41)} -pin  "mux#6" {A1(41)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(42)} -pin  "mux#6" {A1(42)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(43)} -pin  "mux#6" {A1(43)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(44)} -pin  "mux#6" {A1(44)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(45)} -pin  "mux#6" {A1(45)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(46)} -pin  "mux#6" {A1(46)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(47)} -pin  "mux#6" {A1(47)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(48)} -pin  "mux#6" {A1(48)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(49)} -pin  "mux#6" {A1(49)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(50)} -pin  "mux#6" {A1(50)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(51)} -pin  "mux#6" {A1(51)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(52)} -pin  "mux#6" {A1(52)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(53)} -pin  "mux#6" {A1(53)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(54)} -pin  "mux#6" {A1(54)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(55)} -pin  "mux#6" {A1(55)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(56)} -pin  "mux#6" {A1(56)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(57)} -pin  "mux#6" {A1(57)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(58)} -pin  "mux#6" {A1(58)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(59)} -pin  "mux#6" {A1(59)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(60)} -pin  "mux#6" {A1(60)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(61)} -pin  "mux#6" {A1(61)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(62)} -pin  "mux#6" {A1(62)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(63)} -pin  "mux#6" {A1(63)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(64)} -pin  "mux#6" {A1(64)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(65)} -pin  "mux#6" {A1(65)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(66)} -pin  "mux#6" {A1(66)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(67)} -pin  "mux#6" {A1(67)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(68)} -pin  "mux#6" {A1(68)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(69)} -pin  "mux#6" {A1(69)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(70)} -pin  "mux#6" {A1(70)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(71)} -pin  "mux#6" {A1(71)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(72)} -pin  "mux#6" {A1(72)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(73)} -pin  "mux#6" {A1(73)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(74)} -pin  "mux#6" {A1(74)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(75)} -pin  "mux#6" {A1(75)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(76)} -pin  "mux#6" {A1(76)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(77)} -pin  "mux#6" {A1(77)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(78)} -pin  "mux#6" {A1(78)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(79)} -pin  "mux#6" {A1(79)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(80)} -pin  "mux#6" {A1(80)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(81)} -pin  "mux#6" {A1(81)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(82)} -pin  "mux#6" {A1(82)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(83)} -pin  "mux#6" {A1(83)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(84)} -pin  "mux#6" {A1(84)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(85)} -pin  "mux#6" {A1(85)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(86)} -pin  "mux#6" {A1(86)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(87)} -pin  "mux#6" {A1(87)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(88)} -pin  "mux#6" {A1(88)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d(89)} -pin  "mux#6" {A1(89)} -attr vt d -attr @path {/sobel/sobel:core/vin:rsc:mgc_in_wire.d}
+load net {and.dcpl#1} -pin  "mux#6" {S(0)} -attr @path {/sobel/sobel:core/and.dcpl#1}
+load net {regs.regs(0).sva.dfm:mx0(0)} -pin  "mux#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(1)} -pin  "mux#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(2)} -pin  "mux#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(3)} -pin  "mux#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(4)} -pin  "mux#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(5)} -pin  "mux#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(6)} -pin  "mux#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(7)} -pin  "mux#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(8)} -pin  "mux#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(9)} -pin  "mux#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(10)} -pin  "mux#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(11)} -pin  "mux#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(12)} -pin  "mux#6" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(13)} -pin  "mux#6" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(14)} -pin  "mux#6" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(15)} -pin  "mux#6" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(16)} -pin  "mux#6" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(17)} -pin  "mux#6" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(18)} -pin  "mux#6" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(19)} -pin  "mux#6" {Z(19)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(20)} -pin  "mux#6" {Z(20)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(21)} -pin  "mux#6" {Z(21)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(22)} -pin  "mux#6" {Z(22)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(23)} -pin  "mux#6" {Z(23)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(24)} -pin  "mux#6" {Z(24)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(25)} -pin  "mux#6" {Z(25)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(26)} -pin  "mux#6" {Z(26)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(27)} -pin  "mux#6" {Z(27)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(28)} -pin  "mux#6" {Z(28)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(29)} -pin  "mux#6" {Z(29)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(30)} -pin  "mux#6" {Z(30)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(31)} -pin  "mux#6" {Z(31)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(32)} -pin  "mux#6" {Z(32)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(33)} -pin  "mux#6" {Z(33)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(34)} -pin  "mux#6" {Z(34)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(35)} -pin  "mux#6" {Z(35)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(36)} -pin  "mux#6" {Z(36)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(37)} -pin  "mux#6" {Z(37)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(38)} -pin  "mux#6" {Z(38)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(39)} -pin  "mux#6" {Z(39)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(40)} -pin  "mux#6" {Z(40)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(41)} -pin  "mux#6" {Z(41)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(42)} -pin  "mux#6" {Z(42)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(43)} -pin  "mux#6" {Z(43)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(44)} -pin  "mux#6" {Z(44)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(45)} -pin  "mux#6" {Z(45)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(46)} -pin  "mux#6" {Z(46)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(47)} -pin  "mux#6" {Z(47)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(48)} -pin  "mux#6" {Z(48)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(49)} -pin  "mux#6" {Z(49)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(50)} -pin  "mux#6" {Z(50)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(51)} -pin  "mux#6" {Z(51)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(52)} -pin  "mux#6" {Z(52)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(53)} -pin  "mux#6" {Z(53)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(54)} -pin  "mux#6" {Z(54)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(55)} -pin  "mux#6" {Z(55)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(56)} -pin  "mux#6" {Z(56)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(57)} -pin  "mux#6" {Z(57)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(58)} -pin  "mux#6" {Z(58)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(59)} -pin  "mux#6" {Z(59)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(60)} -pin  "mux#6" {Z(60)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(61)} -pin  "mux#6" {Z(61)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(62)} -pin  "mux#6" {Z(62)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(63)} -pin  "mux#6" {Z(63)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(64)} -pin  "mux#6" {Z(64)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(65)} -pin  "mux#6" {Z(65)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(66)} -pin  "mux#6" {Z(66)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(67)} -pin  "mux#6" {Z(67)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(68)} -pin  "mux#6" {Z(68)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(69)} -pin  "mux#6" {Z(69)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(70)} -pin  "mux#6" {Z(70)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(71)} -pin  "mux#6" {Z(71)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(72)} -pin  "mux#6" {Z(72)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(73)} -pin  "mux#6" {Z(73)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(74)} -pin  "mux#6" {Z(74)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(75)} -pin  "mux#6" {Z(75)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(76)} -pin  "mux#6" {Z(76)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(77)} -pin  "mux#6" {Z(77)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(78)} -pin  "mux#6" {Z(78)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(79)} -pin  "mux#6" {Z(79)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(80)} -pin  "mux#6" {Z(80)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(81)} -pin  "mux#6" {Z(81)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(82)} -pin  "mux#6" {Z(82)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(83)} -pin  "mux#6" {Z(83)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(84)} -pin  "mux#6" {Z(84)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(85)} -pin  "mux#6" {Z(85)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(86)} -pin  "mux#6" {Z(86)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(87)} -pin  "mux#6" {Z(87)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(88)} -pin  "mux#6" {Z(88)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load net {regs.regs(0).sva.dfm:mx0(89)} -pin  "mux#6" {Z(89)} -attr vt d -attr @path {/sobel/sobel:core/regs.regs(0).sva.dfm:mx0}
+load inst "FRAME:acc" "add(7,0,8,-1,8)" "INTERFACE" -attr xrf 40027 -attr oid 514 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc} -attr area 9.262368 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,7,0,8)"
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(FRAME:p#1.sva#2).itm}
+load net {PWR} -pin  "FRAME:acc" {B(0)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(1)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(2)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(3)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(4)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(5)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {GND} -pin  "FRAME:acc" {B(6)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {PWR} -pin  "FRAME:acc" {B(7)} -attr @path {/sobel/sobel:core/Cn75_8}
+load net {FRAME:acc.itm(0)} -pin  "FRAME:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(1)} -pin  "FRAME:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(2)} -pin  "FRAME:acc" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(3)} -pin  "FRAME:acc" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(4)} -pin  "FRAME:acc" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(5)} -pin  "FRAME:acc" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(6)} -pin  "FRAME:acc" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load net {FRAME:acc.itm(7)} -pin  "FRAME:acc" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc.itm}
+load inst "FRAME:for:and#10" "and(2,1)" "INTERFACE" -attr xrf 40028 -attr oid 515 -attr @path {/sobel/sobel:core/FRAME:for:and#10} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {exit:FRAME.lpi#1.dfm#2} -pin  "FRAME:for:and#10" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#2}
+load net {not#24} -pin  "FRAME:for:and#10" {A1(0)} -attr @path {/sobel/sobel:core/not#24}
+load net {FRAME:for:and#10.itm} -pin  "FRAME:for:and#10" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#10.itm}
+load inst "FRAME:not" "not(1)" "INTERFACE" -attr xrf 40029 -attr oid 516 -attr @path {/sobel/sobel:core/FRAME:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:acc.itm(7)} -pin  "FRAME:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:slc#8.itm}
+load net {FRAME:not.itm} -pin  "FRAME:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load inst "mux#7" "mux(2,1)" "INTERFACE" -attr xrf 40030 -attr oid 517 -attr @path {/sobel/sobel:core/mux#7} -attr area 0.920423 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(1,1,2)"
+load net {FRAME:for:and#10.itm} -pin  "mux#7" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#10.itm}
+load net {FRAME:not.itm} -pin  "mux#7" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:not.itm}
+load net {or#9.cse} -pin  "mux#7" {S(0)} -attr @path {/sobel/sobel:core/or#9.cse}
+load net {exit:FRAME.lpi#1.dfm#2:mx0} -pin  "mux#7" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME.lpi#1.dfm#2:mx0}
+load inst "FRAME:for#1:not" "not(1)" "INTERFACE" -attr xrf 40031 -attr oid 518 -attr @path {/sobel/sobel:core/FRAME:for#1:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {FRAME:for#1:acc.itm(1)} -pin  "FRAME:for#1:not" {A(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:slc#1.itm}
+load net {FRAME:for#1:not.itm} -pin  "FRAME:for#1:not" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not.itm}
+load inst "FRAME:for:and#15" "and(2,1)" "INTERFACE" -attr xrf 40032 -attr oid 519 -attr @path {/sobel/sobel:core/FRAME:for:and#15} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {FRAME:for#1:not.itm} -pin  "FRAME:for:and#15" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not.itm}
+load net {exit:FRAME:for.lpi#1.dfm} -pin  "FRAME:for:and#15" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1.dfm}
+load net {exit:FRAME:for#1.lpi#1.dfm#5} -pin  "FRAME:for:and#15" {Z(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#5}
+load inst "FRAME:acc#6" "add(19,-1,1,0,19)" "INTERFACE" -attr xrf 40033 -attr oid 520 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#6} -attr area 20.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(19,0,2,1,19)"
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "FRAME:acc#6" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "FRAME:acc#6" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "FRAME:acc#6" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "FRAME:acc#6" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "FRAME:acc#6" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "FRAME:acc#6" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "FRAME:acc#6" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "FRAME:acc#6" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "FRAME:acc#6" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "FRAME:acc#6" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "FRAME:acc#6" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "FRAME:acc#6" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "FRAME:acc#6" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "FRAME:acc#6" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "FRAME:acc#6" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "FRAME:acc#6" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "FRAME:acc#6" {A(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "FRAME:acc#6" {A(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "FRAME:acc#6" {A(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:acc#6" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:p#1.sva#1(0)} -pin  "FRAME:acc#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(1)} -pin  "FRAME:acc#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(2)} -pin  "FRAME:acc#6" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(3)} -pin  "FRAME:acc#6" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(4)} -pin  "FRAME:acc#6" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(5)} -pin  "FRAME:acc#6" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(6)} -pin  "FRAME:acc#6" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(7)} -pin  "FRAME:acc#6" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(8)} -pin  "FRAME:acc#6" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(9)} -pin  "FRAME:acc#6" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(10)} -pin  "FRAME:acc#6" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(11)} -pin  "FRAME:acc#6" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(12)} -pin  "FRAME:acc#6" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(13)} -pin  "FRAME:acc#6" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(14)} -pin  "FRAME:acc#6" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(15)} -pin  "FRAME:acc#6" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(16)} -pin  "FRAME:acc#6" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(17)} -pin  "FRAME:acc#6" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load net {FRAME:p#1.sva#1(18)} -pin  "FRAME:acc#6" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.sva#1}
+load inst "FRAME:not#28" "not(1)" "INTERFACE" -attr xrf 40034 -attr oid 521 -attr @path {/sobel/sobel:core/FRAME:not#28} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME#1.sva} -pin  "FRAME:not#28" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {FRAME:not#28.itm} -pin  "FRAME:not#28" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#28.itm}
+load inst "and" "and(2,19)" "INTERFACE" -attr vt d -attr @path {/sobel/sobel:core/and} -attr area 13.866816 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(19,2)"
+load net {FRAME:p#1.lpi#1(0)} -pin  "and" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(1)} -pin  "and" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(2)} -pin  "and" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(3)} -pin  "and" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(4)} -pin  "and" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(5)} -pin  "and" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(6)} -pin  "and" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(7)} -pin  "and" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(8)} -pin  "and" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(9)} -pin  "and" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(10)} -pin  "and" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(11)} -pin  "and" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(12)} -pin  "and" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(13)} -pin  "and" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(14)} -pin  "and" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(15)} -pin  "and" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(16)} -pin  "and" {A0(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(17)} -pin  "and" {A0(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:p#1.lpi#1(18)} -pin  "and" {A0(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1}
+load net {FRAME:not#28.itm} -pin  "and" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(16)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(17)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:not#28.itm} -pin  "and" {A1(18)} -attr vt d -attr @path {/sobel/sobel:core/exs.itm}
+load net {FRAME:p#1.lpi#1.dfm(0)} -pin  "and" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(1)} -pin  "and" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(2)} -pin  "and" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(3)} -pin  "and" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(4)} -pin  "and" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(5)} -pin  "and" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(6)} -pin  "and" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(7)} -pin  "and" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(8)} -pin  "and" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(9)} -pin  "and" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(10)} -pin  "and" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(11)} -pin  "and" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(12)} -pin  "and" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(13)} -pin  "and" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(14)} -pin  "and" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(15)} -pin  "and" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(16)} -pin  "and" {Z(16)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(17)} -pin  "and" {Z(17)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load net {FRAME:p#1.lpi#1.dfm(18)} -pin  "and" {Z(18)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:p#1.lpi#1.dfm}
+load inst "FRAME:not#2" "not(3)" "INTERFACE" -attr xrf 40035 -attr oid 522 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#1.itm(10)} -pin  "FRAME:not#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#1.itm(11)} -pin  "FRAME:not#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#2.itm}
+load net {ACC2-3:acc#1.itm(12)} -pin  "FRAME:not#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#2.itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:not#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:not#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:not#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load inst "FRAME:acc#8" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 40036 -attr oid 523 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC2-3:acc#1.itm(7)} -pin  "FRAME:acc#8" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva).itm}
+load net {ACC2-3:acc#1.itm(8)} -pin  "FRAME:acc#8" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva).itm}
+load net {ACC2-3:acc#1.itm(9)} -pin  "FRAME:acc#8" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva).itm}
+load net {FRAME:not#2.itm(0)} -pin  "FRAME:acc#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(1)} -pin  "FRAME:acc#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:not#2.itm(2)} -pin  "FRAME:acc#8" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#2.itm}
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#8" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#8" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#8" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#8" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load inst "FRAME:not#35" "not(1)" "INTERFACE" -attr xrf 40037 -attr oid 524 -attr @path {/sobel/sobel:core/FRAME:not#35} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:not#35" {A(0)} -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#20.itm}
+load net {FRAME:not#35.itm} -pin  "FRAME:not#35" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#35.itm}
+load inst "FRAME:not#45" "not(1)" "INTERFACE" -attr xrf 40038 -attr oid 525 -attr @path {/sobel/sobel:core/FRAME:not#45} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC2-3:acc#1.itm(15)} -pin  "FRAME:not#45" {A(0)} -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#10.itm}
+load net {FRAME:not#45.itm} -pin  "FRAME:not#45" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#45.itm}
+load inst "FRAME:acc#7" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 40039 -attr oid 526 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#45.itm} -pin  "FRAME:acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {PWR} -pin  "FRAME:acc#7" {A(1)} -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {FRAME:not#35.itm} -pin  "FRAME:acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#153.itm}
+load net {ACC2-3:acc#1.itm(13)} -pin  "FRAME:acc#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#5.itm}
+load net {ACC2-3:acc#1.itm(14)} -pin  "FRAME:acc#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#5.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load inst "FRAME:acc#10" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 40040 -attr oid 527 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#8.itm(0)} -pin  "FRAME:acc#10" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(1)} -pin  "FRAME:acc#10" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(2)} -pin  "FRAME:acc#10" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#8.itm(3)} -pin  "FRAME:acc#10" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#8.itm}
+load net {FRAME:acc#7.itm(0)} -pin  "FRAME:acc#10" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(1)} -pin  "FRAME:acc#10" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(2)} -pin  "FRAME:acc#10" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#7.itm(3)} -pin  "FRAME:acc#10" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#7.itm}
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#10" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#10" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#10" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#10" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(4)} -pin  "FRAME:acc#10" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load inst "FRAME:not#1" "not(3)" "INTERFACE" -attr xrf 40041 -attr oid 528 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#1.itm(4)} -pin  "FRAME:not#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {ACC2-3:acc#1.itm(5)} -pin  "FRAME:not#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {ACC2-3:acc#1.itm(6)} -pin  "FRAME:not#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#7.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:not#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:not#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:not#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load inst "FRAME:acc#9" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 40042 -attr oid 529 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC2-3:acc#1.itm(1)} -pin  "FRAME:acc#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#1.itm(2)} -pin  "FRAME:acc#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#1.itm(3)} -pin  "FRAME:acc#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#6.itm}
+load net {FRAME:not#1.itm(0)} -pin  "FRAME:acc#9" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(1)} -pin  "FRAME:acc#9" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:not#1.itm(2)} -pin  "FRAME:acc#9" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#1.itm}
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load inst "FRAME:acc#11" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 40043 -attr oid 530 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11} -attr area 6.288444 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6)"
+load net {FRAME:acc#10.itm(0)} -pin  "FRAME:acc#11" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(1)} -pin  "FRAME:acc#11" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(2)} -pin  "FRAME:acc#11" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(3)} -pin  "FRAME:acc#11" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#10.itm(4)} -pin  "FRAME:acc#11" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#10.itm}
+load net {FRAME:acc#9.itm(0)} -pin  "FRAME:acc#11" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(1)} -pin  "FRAME:acc#11" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(2)} -pin  "FRAME:acc#11" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#9.itm(3)} -pin  "FRAME:acc#11" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#9.itm}
+load net {FRAME:acc#11.itm(0)} -pin  "FRAME:acc#11" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "FRAME:acc#11" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "FRAME:acc#11" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "FRAME:acc#11" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "FRAME:acc#11" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(5)} -pin  "FRAME:acc#11" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load inst "acc#3" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 40044 -attr oid 531 -attr vt dc -attr @path {/sobel/sobel:core/acc#3} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {FRAME:acc#11.itm(0)} -pin  "acc#3" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(1)} -pin  "acc#3" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(2)} -pin  "acc#3" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(3)} -pin  "acc#3" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(4)} -pin  "acc#3" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {FRAME:acc#11.itm(5)} -pin  "acc#3" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:acc#11.itm}
+load net {PWR} -pin  "acc#3" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#3" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#3" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#3" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#3" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#3" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#3.sva(0)} -pin  "acc#3" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod#3.sva}
+load net {acc.imod#3.sva(1)} -pin  "acc#3" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod#3.sva}
+load net {acc.imod#3.sva(2)} -pin  "acc#3" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod#3.sva}
+load net {acc.imod#3.sva(3)} -pin  "acc#3" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod#3.sva}
+load net {acc.imod#3.sva(4)} -pin  "acc#3" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod#3.sva}
+load net {acc.imod#3.sva(5)} -pin  "acc#3" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/acc.imod#3.sva}
+load inst "ACC2:acc" "add(15,-1,15,-1,15)" "INTERFACE" -attr xrf 40045 -attr oid 532 -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc} -attr area 16.198770 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,15,0,15)"
+load net {r(1).sg1.lpi#1.dfm(0)} -pin  "ACC2:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(1)} -pin  "ACC2:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(2)} -pin  "ACC2:acc" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(3)} -pin  "ACC2:acc" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(4)} -pin  "ACC2:acc" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(5)} -pin  "ACC2:acc" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(6)} -pin  "ACC2:acc" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(7)} -pin  "ACC2:acc" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(8)} -pin  "ACC2:acc" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(9)} -pin  "ACC2:acc" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(10)} -pin  "ACC2:acc" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(11)} -pin  "ACC2:acc" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(12)} -pin  "ACC2:acc" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(13)} -pin  "ACC2:acc" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(14)} -pin  "ACC2:acc" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(2).sva#1(1)} -pin  "ACC2:acc" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(2)} -pin  "ACC2:acc" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(3)} -pin  "ACC2:acc" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(4)} -pin  "ACC2:acc" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(5)} -pin  "ACC2:acc" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(6)} -pin  "ACC2:acc" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(7)} -pin  "ACC2:acc" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(8)} -pin  "ACC2:acc" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(9)} -pin  "ACC2:acc" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(10)} -pin  "ACC2:acc" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(11)} -pin  "ACC2:acc" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(12)} -pin  "ACC2:acc" {B(11)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(13)} -pin  "ACC2:acc" {B(12)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(14)} -pin  "ACC2:acc" {B(13)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {r(2).sva#1(15)} -pin  "ACC2:acc" {B(14)} -attr vt dc -attr @path {/sobel/sobel:core/slc(r(2).sva#1).itm}
+load net {ACC2:acc.itm(0)} -pin  "ACC2:acc" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(1)} -pin  "ACC2:acc" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(2)} -pin  "ACC2:acc" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(3)} -pin  "ACC2:acc" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(4)} -pin  "ACC2:acc" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(5)} -pin  "ACC2:acc" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(6)} -pin  "ACC2:acc" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(7)} -pin  "ACC2:acc" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(8)} -pin  "ACC2:acc" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(9)} -pin  "ACC2:acc" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(10)} -pin  "ACC2:acc" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(11)} -pin  "ACC2:acc" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(12)} -pin  "ACC2:acc" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(13)} -pin  "ACC2:acc" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load net {ACC2:acc.itm(14)} -pin  "ACC2:acc" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:acc.itm}
+load inst "ACC2-3:acc#1" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 40046 -attr oid 533 -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {r(2).sva#1(0)} -pin  "ACC2-3:acc#1" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(0)} -pin  "ACC2-3:acc#1" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(1)} -pin  "ACC2-3:acc#1" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(2)} -pin  "ACC2-3:acc#1" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(3)} -pin  "ACC2-3:acc#1" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(4)} -pin  "ACC2-3:acc#1" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(5)} -pin  "ACC2-3:acc#1" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(6)} -pin  "ACC2-3:acc#1" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(7)} -pin  "ACC2-3:acc#1" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(8)} -pin  "ACC2-3:acc#1" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(9)} -pin  "ACC2-3:acc#1" {A(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(10)} -pin  "ACC2-3:acc#1" {A(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(11)} -pin  "ACC2-3:acc#1" {A(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(12)} -pin  "ACC2-3:acc#1" {A(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(13)} -pin  "ACC2-3:acc#1" {A(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {ACC2:acc.itm(14)} -pin  "ACC2-3:acc#1" {A(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2:conc.itm}
+load net {r(0).sva#1(0)} -pin  "ACC2-3:acc#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(1)} -pin  "ACC2-3:acc#1" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(2)} -pin  "ACC2-3:acc#1" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(3)} -pin  "ACC2-3:acc#1" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(4)} -pin  "ACC2-3:acc#1" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(5)} -pin  "ACC2-3:acc#1" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(6)} -pin  "ACC2-3:acc#1" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(7)} -pin  "ACC2-3:acc#1" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(8)} -pin  "ACC2-3:acc#1" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(9)} -pin  "ACC2-3:acc#1" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(10)} -pin  "ACC2-3:acc#1" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(11)} -pin  "ACC2-3:acc#1" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(12)} -pin  "ACC2-3:acc#1" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(13)} -pin  "ACC2-3:acc#1" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(14)} -pin  "ACC2-3:acc#1" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(15)} -pin  "ACC2-3:acc#1" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {ACC2-3:acc#1.itm(0)} -pin  "ACC2-3:acc#1" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(1)} -pin  "ACC2-3:acc#1" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(2)} -pin  "ACC2-3:acc#1" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(3)} -pin  "ACC2-3:acc#1" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(4)} -pin  "ACC2-3:acc#1" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(5)} -pin  "ACC2-3:acc#1" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(6)} -pin  "ACC2-3:acc#1" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(7)} -pin  "ACC2-3:acc#1" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(8)} -pin  "ACC2-3:acc#1" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(9)} -pin  "ACC2-3:acc#1" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(10)} -pin  "ACC2-3:acc#1" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(11)} -pin  "ACC2-3:acc#1" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(12)} -pin  "ACC2-3:acc#1" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(13)} -pin  "ACC2-3:acc#1" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(14)} -pin  "ACC2-3:acc#1" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load net {ACC2-3:acc#1.itm(15)} -pin  "ACC2-3:acc#1" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/ACC2-3:acc#1.itm}
+load inst "FRAME:mul" "mul(2,0,9,0,10)" "INTERFACE" -attr xrf 40047 -attr oid 534 -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,0,9,0,11)"
+load net {ACC2-3:acc#1.itm(13)} -pin  "FRAME:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#12.itm}
+load net {ACC2-3:acc#1.itm(14)} -pin  "FRAME:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(red#2.sg1.sva)#12.itm}
+load net {PWR} -pin  "FRAME:mul" {B(0)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(1)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(2)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(3)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(4)} -attr @path {/sobel/sobel:core/C455_9}
+load net {GND} -pin  "FRAME:mul" {B(5)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(6)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(7)} -attr @path {/sobel/sobel:core/C455_9}
+load net {PWR} -pin  "FRAME:mul" {B(8)} -attr @path {/sobel/sobel:core/C455_9}
+load net {FRAME:mul.sdt(0)} -pin  "FRAME:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(1)} -pin  "FRAME:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(2)} -pin  "FRAME:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(3)} -pin  "FRAME:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(4)} -pin  "FRAME:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(5)} -pin  "FRAME:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(6)} -pin  "FRAME:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(7)} -pin  "FRAME:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(8)} -pin  "FRAME:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load net {FRAME:mul.sdt(9)} -pin  "FRAME:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:mul.sdt}
+load inst "ACC2:acc#8" "add(15,-1,15,-1,15)" "INTERFACE" -attr xrf 40048 -attr oid 535 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8} -attr area 16.198770 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,15,0,15)"
+load net {b(1).sg1.lpi#1.dfm(0)} -pin  "ACC2:acc#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(1)} -pin  "ACC2:acc#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(2)} -pin  "ACC2:acc#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(3)} -pin  "ACC2:acc#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(4)} -pin  "ACC2:acc#8" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(5)} -pin  "ACC2:acc#8" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(6)} -pin  "ACC2:acc#8" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(7)} -pin  "ACC2:acc#8" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(8)} -pin  "ACC2:acc#8" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(9)} -pin  "ACC2:acc#8" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(10)} -pin  "ACC2:acc#8" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(11)} -pin  "ACC2:acc#8" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(12)} -pin  "ACC2:acc#8" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(13)} -pin  "ACC2:acc#8" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(14)} -pin  "ACC2:acc#8" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(2).sva#1(1)} -pin  "ACC2:acc#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(2)} -pin  "ACC2:acc#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(3)} -pin  "ACC2:acc#8" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(4)} -pin  "ACC2:acc#8" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(5)} -pin  "ACC2:acc#8" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(6)} -pin  "ACC2:acc#8" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(7)} -pin  "ACC2:acc#8" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(8)} -pin  "ACC2:acc#8" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(9)} -pin  "ACC2:acc#8" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(10)} -pin  "ACC2:acc#8" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(11)} -pin  "ACC2:acc#8" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(12)} -pin  "ACC2:acc#8" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(13)} -pin  "ACC2:acc#8" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(14)} -pin  "ACC2:acc#8" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {b(2).sva#1(15)} -pin  "ACC2:acc#8" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(b(2).sva#1).itm}
+load net {ACC2:acc#8.itm(0)} -pin  "ACC2:acc#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(1)} -pin  "ACC2:acc#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(2)} -pin  "ACC2:acc#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(3)} -pin  "ACC2:acc#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(4)} -pin  "ACC2:acc#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(5)} -pin  "ACC2:acc#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(6)} -pin  "ACC2:acc#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(7)} -pin  "ACC2:acc#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(8)} -pin  "ACC2:acc#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(9)} -pin  "ACC2:acc#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(10)} -pin  "ACC2:acc#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(11)} -pin  "ACC2:acc#8" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(12)} -pin  "ACC2:acc#8" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(13)} -pin  "ACC2:acc#8" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load net {ACC2:acc#8.itm(14)} -pin  "ACC2:acc#8" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#8.itm}
+load inst "ACC2-3:acc#3" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 40049 -attr oid 536 -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {b(2).sva#1(0)} -pin  "ACC2-3:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(0)} -pin  "ACC2-3:acc#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(1)} -pin  "ACC2-3:acc#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(2)} -pin  "ACC2-3:acc#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(3)} -pin  "ACC2-3:acc#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(4)} -pin  "ACC2-3:acc#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(5)} -pin  "ACC2-3:acc#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(6)} -pin  "ACC2-3:acc#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(7)} -pin  "ACC2-3:acc#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(8)} -pin  "ACC2-3:acc#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(9)} -pin  "ACC2-3:acc#3" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(10)} -pin  "ACC2-3:acc#3" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(11)} -pin  "ACC2-3:acc#3" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(12)} -pin  "ACC2-3:acc#3" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(13)} -pin  "ACC2-3:acc#3" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {ACC2:acc#8.itm(14)} -pin  "ACC2-3:acc#3" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#2.itm}
+load net {b(0).sva#1(0)} -pin  "ACC2-3:acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(1)} -pin  "ACC2-3:acc#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(2)} -pin  "ACC2-3:acc#3" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(3)} -pin  "ACC2-3:acc#3" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(4)} -pin  "ACC2-3:acc#3" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(5)} -pin  "ACC2-3:acc#3" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(6)} -pin  "ACC2-3:acc#3" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(7)} -pin  "ACC2-3:acc#3" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(8)} -pin  "ACC2-3:acc#3" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(9)} -pin  "ACC2-3:acc#3" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(10)} -pin  "ACC2-3:acc#3" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(11)} -pin  "ACC2-3:acc#3" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(12)} -pin  "ACC2-3:acc#3" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(13)} -pin  "ACC2-3:acc#3" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(14)} -pin  "ACC2-3:acc#3" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(15)} -pin  "ACC2-3:acc#3" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {ACC2-3:acc#3.itm(0)} -pin  "ACC2-3:acc#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(1)} -pin  "ACC2-3:acc#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(2)} -pin  "ACC2-3:acc#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(3)} -pin  "ACC2-3:acc#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(4)} -pin  "ACC2-3:acc#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(5)} -pin  "ACC2-3:acc#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(6)} -pin  "ACC2-3:acc#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(7)} -pin  "ACC2-3:acc#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(8)} -pin  "ACC2-3:acc#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(9)} -pin  "ACC2-3:acc#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(10)} -pin  "ACC2-3:acc#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(11)} -pin  "ACC2-3:acc#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(12)} -pin  "ACC2-3:acc#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(13)} -pin  "ACC2-3:acc#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(14)} -pin  "ACC2-3:acc#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load net {ACC2-3:acc#3.itm(15)} -pin  "ACC2-3:acc#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#3.itm}
+load inst "FRAME:not#18" "not(3)" "INTERFACE" -attr xrf 40050 -attr oid 537 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#3.itm(10)} -pin  "FRAME:not#18" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {ACC2-3:acc#3.itm(11)} -pin  "FRAME:not#18" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {ACC2-3:acc#3.itm(12)} -pin  "FRAME:not#18" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#3.itm}
+load net {FRAME:not#18.itm(0)} -pin  "FRAME:not#18" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(1)} -pin  "FRAME:not#18" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(2)} -pin  "FRAME:not#18" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load inst "FRAME:acc#25" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 40051 -attr oid 538 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC2-3:acc#3.itm(7)} -pin  "FRAME:acc#25" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#3.itm(8)} -pin  "FRAME:acc#25" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#3.itm(9)} -pin  "FRAME:acc#25" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#1.itm}
+load net {FRAME:not#18.itm(0)} -pin  "FRAME:acc#25" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(1)} -pin  "FRAME:acc#25" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:not#18.itm(2)} -pin  "FRAME:acc#25" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#18.itm}
+load net {FRAME:acc#25.itm(0)} -pin  "FRAME:acc#25" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(1)} -pin  "FRAME:acc#25" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(2)} -pin  "FRAME:acc#25" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(3)} -pin  "FRAME:acc#25" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load inst "FRAME:not#36" "not(1)" "INTERFACE" -attr xrf 40052 -attr oid 539 -attr @path {/sobel/sobel:core/FRAME:not#36} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC2-3:acc#3.itm(15)} -pin  "FRAME:not#36" {A(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#12.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:not#36" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#36.itm}
+load inst "FRAME:not#47" "not(1)" "INTERFACE" -attr xrf 40053 -attr oid 540 -attr @path {/sobel/sobel:core/FRAME:not#47} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC2-3:acc#3.itm(15)} -pin  "FRAME:not#47" {A(0)} -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#7.itm}
+load net {FRAME:not#47.itm} -pin  "FRAME:not#47" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#47.itm}
+load inst "FRAME:acc#24" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 40054 -attr oid 541 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#47.itm} -pin  "FRAME:acc#24" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {PWR} -pin  "FRAME:acc#24" {A(1)} -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {FRAME:not#36.itm} -pin  "FRAME:acc#24" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#154.itm}
+load net {ACC2-3:acc#3.itm(13)} -pin  "FRAME:acc#24" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#4.itm}
+load net {ACC2-3:acc#3.itm(14)} -pin  "FRAME:acc#24" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#4.itm}
+load net {FRAME:acc#24.itm(0)} -pin  "FRAME:acc#24" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(1)} -pin  "FRAME:acc#24" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(2)} -pin  "FRAME:acc#24" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(3)} -pin  "FRAME:acc#24" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load inst "FRAME:acc#27" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 40055 -attr oid 542 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#25.itm(0)} -pin  "FRAME:acc#27" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(1)} -pin  "FRAME:acc#27" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(2)} -pin  "FRAME:acc#27" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#25.itm(3)} -pin  "FRAME:acc#27" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#25.itm}
+load net {FRAME:acc#24.itm(0)} -pin  "FRAME:acc#27" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(1)} -pin  "FRAME:acc#27" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(2)} -pin  "FRAME:acc#27" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#24.itm(3)} -pin  "FRAME:acc#27" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#24.itm}
+load net {FRAME:acc#27.itm(0)} -pin  "FRAME:acc#27" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(1)} -pin  "FRAME:acc#27" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(2)} -pin  "FRAME:acc#27" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(3)} -pin  "FRAME:acc#27" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(4)} -pin  "FRAME:acc#27" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load inst "FRAME:not#17" "not(3)" "INTERFACE" -attr xrf 40056 -attr oid 543 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#3.itm(4)} -pin  "FRAME:not#17" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#3.itm(5)} -pin  "FRAME:not#17" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#3.itm(6)} -pin  "FRAME:not#17" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#6.itm}
+load net {FRAME:not#17.itm(0)} -pin  "FRAME:not#17" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(1)} -pin  "FRAME:not#17" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(2)} -pin  "FRAME:not#17" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load inst "FRAME:acc#26" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 40057 -attr oid 544 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC2-3:acc#3.itm(1)} -pin  "FRAME:acc#26" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {ACC2-3:acc#3.itm(2)} -pin  "FRAME:acc#26" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {ACC2-3:acc#3.itm(3)} -pin  "FRAME:acc#26" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(blue#2.sg1.sva)#5.itm}
+load net {FRAME:not#17.itm(0)} -pin  "FRAME:acc#26" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(1)} -pin  "FRAME:acc#26" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:not#17.itm(2)} -pin  "FRAME:acc#26" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#17.itm}
+load net {FRAME:acc#26.itm(0)} -pin  "FRAME:acc#26" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(1)} -pin  "FRAME:acc#26" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(2)} -pin  "FRAME:acc#26" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(3)} -pin  "FRAME:acc#26" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load inst "FRAME:acc#28" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 40058 -attr oid 545 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28} -attr area 6.288444 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6)"
+load net {FRAME:acc#27.itm(0)} -pin  "FRAME:acc#28" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(1)} -pin  "FRAME:acc#28" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(2)} -pin  "FRAME:acc#28" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(3)} -pin  "FRAME:acc#28" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#27.itm(4)} -pin  "FRAME:acc#28" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#27.itm}
+load net {FRAME:acc#26.itm(0)} -pin  "FRAME:acc#28" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(1)} -pin  "FRAME:acc#28" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(2)} -pin  "FRAME:acc#28" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#26.itm(3)} -pin  "FRAME:acc#28" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#26.itm}
+load net {FRAME:acc#28.itm(0)} -pin  "FRAME:acc#28" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(1)} -pin  "FRAME:acc#28" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(2)} -pin  "FRAME:acc#28" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(3)} -pin  "FRAME:acc#28" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(4)} -pin  "FRAME:acc#28" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(5)} -pin  "FRAME:acc#28" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load inst "acc#7" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 40059 -attr oid 546 -attr vt d -attr @path {/sobel/sobel:core/acc#7} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {FRAME:acc#28.itm(0)} -pin  "acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(1)} -pin  "acc#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(2)} -pin  "acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(3)} -pin  "acc#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(4)} -pin  "acc#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {FRAME:acc#28.itm(5)} -pin  "acc#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#28.itm}
+load net {PWR} -pin  "acc#7" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#7" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#7" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#7" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#7" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#7" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#7.sva(0)} -pin  "acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.sva}
+load net {acc.imod#7.sva(1)} -pin  "acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.sva}
+load net {acc.imod#7.sva(2)} -pin  "acc#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.sva}
+load net {acc.imod#7.sva(3)} -pin  "acc#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.sva}
+load net {acc.imod#7.sva(4)} -pin  "acc#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.sva}
+load net {acc.imod#7.sva(5)} -pin  "acc#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#7.sva}
+load inst "ACC2:acc#7" "add(15,-1,15,-1,15)" "INTERFACE" -attr xrf 40060 -attr oid 547 -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7} -attr area 16.198770 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,15,0,15)"
+load net {g(1).sg1.lpi#1.dfm(0)} -pin  "ACC2:acc#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(1)} -pin  "ACC2:acc#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(2)} -pin  "ACC2:acc#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(3)} -pin  "ACC2:acc#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(4)} -pin  "ACC2:acc#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(5)} -pin  "ACC2:acc#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(6)} -pin  "ACC2:acc#7" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(7)} -pin  "ACC2:acc#7" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(8)} -pin  "ACC2:acc#7" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(9)} -pin  "ACC2:acc#7" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(10)} -pin  "ACC2:acc#7" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(11)} -pin  "ACC2:acc#7" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(12)} -pin  "ACC2:acc#7" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(13)} -pin  "ACC2:acc#7" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(14)} -pin  "ACC2:acc#7" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(2).sva#1(1)} -pin  "ACC2:acc#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(2)} -pin  "ACC2:acc#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(3)} -pin  "ACC2:acc#7" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(4)} -pin  "ACC2:acc#7" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(5)} -pin  "ACC2:acc#7" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(6)} -pin  "ACC2:acc#7" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(7)} -pin  "ACC2:acc#7" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(8)} -pin  "ACC2:acc#7" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(9)} -pin  "ACC2:acc#7" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(10)} -pin  "ACC2:acc#7" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(11)} -pin  "ACC2:acc#7" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(12)} -pin  "ACC2:acc#7" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(13)} -pin  "ACC2:acc#7" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(14)} -pin  "ACC2:acc#7" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {g(2).sva#1(15)} -pin  "ACC2:acc#7" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/slc(g(2).sva#1).itm}
+load net {ACC2:acc#7.itm(0)} -pin  "ACC2:acc#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(1)} -pin  "ACC2:acc#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(2)} -pin  "ACC2:acc#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(3)} -pin  "ACC2:acc#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(4)} -pin  "ACC2:acc#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(5)} -pin  "ACC2:acc#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(6)} -pin  "ACC2:acc#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(7)} -pin  "ACC2:acc#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(8)} -pin  "ACC2:acc#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(9)} -pin  "ACC2:acc#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(10)} -pin  "ACC2:acc#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(11)} -pin  "ACC2:acc#7" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(12)} -pin  "ACC2:acc#7" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(13)} -pin  "ACC2:acc#7" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load net {ACC2:acc#7.itm(14)} -pin  "ACC2:acc#7" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:acc#7.itm}
+load inst "ACC2-3:acc#2" "add(16,-1,16,-1,16)" "INTERFACE" -attr xrf 40061 -attr oid 548 -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2} -attr area 17.189078 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,16,0,16)"
+load net {g(2).sva#1(0)} -pin  "ACC2-3:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(0)} -pin  "ACC2-3:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(1)} -pin  "ACC2-3:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(2)} -pin  "ACC2-3:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(3)} -pin  "ACC2-3:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(4)} -pin  "ACC2-3:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(5)} -pin  "ACC2-3:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(6)} -pin  "ACC2-3:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(7)} -pin  "ACC2-3:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(8)} -pin  "ACC2-3:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(9)} -pin  "ACC2-3:acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(10)} -pin  "ACC2-3:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(11)} -pin  "ACC2-3:acc#2" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(12)} -pin  "ACC2-3:acc#2" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(13)} -pin  "ACC2-3:acc#2" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {ACC2:acc#7.itm(14)} -pin  "ACC2-3:acc#2" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC2:conc#1.itm}
+load net {g(0).sva#1(0)} -pin  "ACC2-3:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(1)} -pin  "ACC2-3:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(2)} -pin  "ACC2-3:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(3)} -pin  "ACC2-3:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(4)} -pin  "ACC2-3:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(5)} -pin  "ACC2-3:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(6)} -pin  "ACC2-3:acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(7)} -pin  "ACC2-3:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(8)} -pin  "ACC2-3:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(9)} -pin  "ACC2-3:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(10)} -pin  "ACC2-3:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(11)} -pin  "ACC2-3:acc#2" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(12)} -pin  "ACC2-3:acc#2" {B(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(13)} -pin  "ACC2-3:acc#2" {B(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(14)} -pin  "ACC2-3:acc#2" {B(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(15)} -pin  "ACC2-3:acc#2" {B(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {ACC2-3:acc#2.itm(0)} -pin  "ACC2-3:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(1)} -pin  "ACC2-3:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(2)} -pin  "ACC2-3:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(3)} -pin  "ACC2-3:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(4)} -pin  "ACC2-3:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(5)} -pin  "ACC2-3:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(6)} -pin  "ACC2-3:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(7)} -pin  "ACC2-3:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(8)} -pin  "ACC2-3:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(9)} -pin  "ACC2-3:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(10)} -pin  "ACC2-3:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(11)} -pin  "ACC2-3:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(12)} -pin  "ACC2-3:acc#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(13)} -pin  "ACC2-3:acc#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(14)} -pin  "ACC2-3:acc#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load net {ACC2-3:acc#2.itm(15)} -pin  "ACC2-3:acc#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/ACC2-3:acc#2.itm}
+load inst "FRAME:not#10" "not(3)" "INTERFACE" -attr xrf 40062 -attr oid 549 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#2.itm(10)} -pin  "FRAME:not#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {ACC2-3:acc#2.itm(11)} -pin  "FRAME:not#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {ACC2-3:acc#2.itm(12)} -pin  "FRAME:not#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#3.itm}
+load net {FRAME:not#10.itm(0)} -pin  "FRAME:not#10" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(1)} -pin  "FRAME:not#10" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(2)} -pin  "FRAME:not#10" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load inst "FRAME:acc#13" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 40063 -attr oid 550 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC2-3:acc#2.itm(7)} -pin  "FRAME:acc#13" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#2.itm(8)} -pin  "FRAME:acc#13" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {ACC2-3:acc#2.itm(9)} -pin  "FRAME:acc#13" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#1.itm}
+load net {FRAME:not#10.itm(0)} -pin  "FRAME:acc#13" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(1)} -pin  "FRAME:acc#13" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:not#10.itm(2)} -pin  "FRAME:acc#13" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#10.itm}
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#13" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#13" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#13" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#13" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load inst "FRAME:not#37" "not(1)" "INTERFACE" -attr xrf 40064 -attr oid 551 -attr @path {/sobel/sobel:core/FRAME:not#37} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC2-3:acc#2.itm(15)} -pin  "FRAME:not#37" {A(0)} -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#12.itm}
+load net {FRAME:not#37.itm} -pin  "FRAME:not#37" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#37.itm}
+load inst "FRAME:not#49" "not(1)" "INTERFACE" -attr xrf 40065 -attr oid 552 -attr @path {/sobel/sobel:core/FRAME:not#49} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {ACC2-3:acc#2.itm(15)} -pin  "FRAME:not#49" {A(0)} -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#7.itm}
+load net {FRAME:not#49.itm} -pin  "FRAME:not#49" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:not#49.itm}
+load inst "FRAME:acc#12" "add(3,0,2,0,4)" "INTERFACE" -attr xrf 40066 -attr oid 553 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {FRAME:not#49.itm} -pin  "FRAME:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {PWR} -pin  "FRAME:acc#12" {A(1)} -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {FRAME:not#37.itm} -pin  "FRAME:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/conc#155.itm}
+load net {ACC2-3:acc#2.itm(13)} -pin  "FRAME:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#4.itm}
+load net {ACC2-3:acc#2.itm(14)} -pin  "FRAME:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#4.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load inst "FRAME:acc#15" "add(4,0,4,0,5)" "INTERFACE" -attr xrf 40067 -attr oid 554 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15} -attr area 5.293382 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,4,0,5)"
+load net {FRAME:acc#13.itm(0)} -pin  "FRAME:acc#15" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(1)} -pin  "FRAME:acc#15" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(2)} -pin  "FRAME:acc#15" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#13.itm(3)} -pin  "FRAME:acc#15" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#13.itm}
+load net {FRAME:acc#12.itm(0)} -pin  "FRAME:acc#15" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(1)} -pin  "FRAME:acc#15" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(2)} -pin  "FRAME:acc#15" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#12.itm(3)} -pin  "FRAME:acc#15" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#12.itm}
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#15" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#15" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#15" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#15" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#15" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load inst "FRAME:not#9" "not(3)" "INTERFACE" -attr xrf 40068 -attr oid 555 -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(3)"
+load net {ACC2-3:acc#2.itm(4)} -pin  "FRAME:not#9" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#2.itm(5)} -pin  "FRAME:not#9" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {ACC2-3:acc#2.itm(6)} -pin  "FRAME:not#9" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#6.itm}
+load net {FRAME:not#9.itm(0)} -pin  "FRAME:not#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(1)} -pin  "FRAME:not#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(2)} -pin  "FRAME:not#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load inst "FRAME:acc#14" "add(3,0,3,0,4)" "INTERFACE" -attr xrf 40069 -attr oid 556 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14} -attr area 4.302074 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,4)"
+load net {ACC2-3:acc#2.itm(1)} -pin  "FRAME:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {ACC2-3:acc#2.itm(2)} -pin  "FRAME:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {ACC2-3:acc#2.itm(3)} -pin  "FRAME:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(green#2.sg1.sva)#5.itm}
+load net {FRAME:not#9.itm(0)} -pin  "FRAME:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(1)} -pin  "FRAME:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:not#9.itm(2)} -pin  "FRAME:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:not#9.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load inst "FRAME:acc#16" "add(5,0,4,0,6)" "INTERFACE" -attr xrf 40070 -attr oid 557 -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16} -attr area 6.288444 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,4,0,6)"
+load net {FRAME:acc#15.itm(0)} -pin  "FRAME:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(1)} -pin  "FRAME:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(2)} -pin  "FRAME:acc#16" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(3)} -pin  "FRAME:acc#16" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#15.itm(4)} -pin  "FRAME:acc#16" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#15.itm}
+load net {FRAME:acc#14.itm(0)} -pin  "FRAME:acc#16" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(1)} -pin  "FRAME:acc#16" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(2)} -pin  "FRAME:acc#16" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#14.itm(3)} -pin  "FRAME:acc#16" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#14.itm}
+load net {FRAME:acc#16.itm(0)} -pin  "FRAME:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "FRAME:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "FRAME:acc#16" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "FRAME:acc#16" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "FRAME:acc#16" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(5)} -pin  "FRAME:acc#16" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load inst "acc#5" "add(6,-1,6,-1,6)" "INTERFACE" -attr xrf 40071 -attr oid 558 -attr vt d -attr @path {/sobel/sobel:core/acc#5} -attr area 7.275998 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(6,0,6,0,6)"
+load net {FRAME:acc#16.itm(0)} -pin  "acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(1)} -pin  "acc#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(2)} -pin  "acc#5" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(3)} -pin  "acc#5" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(4)} -pin  "acc#5" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {FRAME:acc#16.itm(5)} -pin  "acc#5" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:acc#16.itm}
+load net {PWR} -pin  "acc#5" {B(0)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#5" {B(1)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#5" {B(2)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#5" {B(3)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {GND} -pin  "acc#5" {B(4)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {PWR} -pin  "acc#5" {B(5)} -attr @path {/sobel/sobel:core/Cn21_6}
+load net {acc.imod#5.sva(0)} -pin  "acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#5.sva}
+load net {acc.imod#5.sva(1)} -pin  "acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#5.sva}
+load net {acc.imod#5.sva(2)} -pin  "acc#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#5.sva}
+load net {acc.imod#5.sva(3)} -pin  "acc#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#5.sva}
+load net {acc.imod#5.sva(4)} -pin  "acc#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#5.sva}
+load net {acc.imod#5.sva(5)} -pin  "acc#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/acc.imod#5.sva}
+load inst "FRAME:for:and#9" "and(2,15)" "INTERFACE" -attr xrf 40072 -attr oid 559 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#9} -attr area 10.947486 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(15,2)"
+load net {b(1).sg1.lpi#1(0)} -pin  "FRAME:for:and#9" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(1)} -pin  "FRAME:for:and#9" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(2)} -pin  "FRAME:for:and#9" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(3)} -pin  "FRAME:for:and#9" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(4)} -pin  "FRAME:for:and#9" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(5)} -pin  "FRAME:for:and#9" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(6)} -pin  "FRAME:for:and#9" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(7)} -pin  "FRAME:for:and#9" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(8)} -pin  "FRAME:for:and#9" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(9)} -pin  "FRAME:for:and#9" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(10)} -pin  "FRAME:for:and#9" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(11)} -pin  "FRAME:for:and#9" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(12)} -pin  "FRAME:for:and#9" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(13)} -pin  "FRAME:for:and#9" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {b(1).sg1.lpi#1(14)} -pin  "FRAME:for:and#9" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {not#24} -pin  "FRAME:for:and#9" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#35.itm}
+load net {b(1).sg1.lpi#1.dfm(0)} -pin  "FRAME:for:and#9" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(1)} -pin  "FRAME:for:and#9" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(2)} -pin  "FRAME:for:and#9" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(3)} -pin  "FRAME:for:and#9" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(4)} -pin  "FRAME:for:and#9" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(5)} -pin  "FRAME:for:and#9" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(6)} -pin  "FRAME:for:and#9" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(7)} -pin  "FRAME:for:and#9" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(8)} -pin  "FRAME:for:and#9" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(9)} -pin  "FRAME:for:and#9" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(10)} -pin  "FRAME:for:and#9" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(11)} -pin  "FRAME:for:and#9" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(12)} -pin  "FRAME:for:and#9" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(13)} -pin  "FRAME:for:and#9" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load net {b(1).sg1.lpi#1.dfm(14)} -pin  "FRAME:for:and#9" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(1).sg1.lpi#1.dfm}
+load inst "regs.operator[]#23:mux" "mux(4,10)" "INTERFACE" -attr xrf 40073 -attr oid 560 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#23:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm(60)} -pin  "regs.operator[]#23:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(61)} -pin  "regs.operator[]#23:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(62)} -pin  "regs.operator[]#23:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(63)} -pin  "regs.operator[]#23:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(64)} -pin  "regs.operator[]#23:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(65)} -pin  "regs.operator[]#23:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(66)} -pin  "regs.operator[]#23:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(67)} -pin  "regs.operator[]#23:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(68)} -pin  "regs.operator[]#23:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(2).lpi#1.dfm(69)} -pin  "regs.operator[]#23:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm).itm}
+load net {regs.regs(1).sva(60)} -pin  "regs.operator[]#23:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(61)} -pin  "regs.operator[]#23:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(62)} -pin  "regs.operator[]#23:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(63)} -pin  "regs.operator[]#23:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(64)} -pin  "regs.operator[]#23:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(65)} -pin  "regs.operator[]#23:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(66)} -pin  "regs.operator[]#23:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(67)} -pin  "regs.operator[]#23:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(68)} -pin  "regs.operator[]#23:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(1).sva(69)} -pin  "regs.operator[]#23:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva).itm}
+load net {regs.regs(0).sva(60)} -pin  "regs.operator[]#23:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(61)} -pin  "regs.operator[]#23:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(62)} -pin  "regs.operator[]#23:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(63)} -pin  "regs.operator[]#23:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(64)} -pin  "regs.operator[]#23:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(65)} -pin  "regs.operator[]#23:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(66)} -pin  "regs.operator[]#23:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(67)} -pin  "regs.operator[]#23:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(68)} -pin  "regs.operator[]#23:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {regs.regs(0).sva(69)} -pin  "regs.operator[]#23:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva).itm}
+load net {i#7.lpi#1(0)} -pin  "regs.operator[]#23:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "regs.operator[]#23:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.operator[]#23:mux.itm(0)} -pin  "regs.operator[]#23:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(1)} -pin  "regs.operator[]#23:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(2)} -pin  "regs.operator[]#23:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(3)} -pin  "regs.operator[]#23:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(4)} -pin  "regs.operator[]#23:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(5)} -pin  "regs.operator[]#23:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(6)} -pin  "regs.operator[]#23:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(7)} -pin  "regs.operator[]#23:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(8)} -pin  "regs.operator[]#23:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(9)} -pin  "regs.operator[]#23:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load inst "FRAME:for#1:mul#8" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 40074 -attr oid 561 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#23:mux.itm(0)} -pin  "FRAME:for#1:mul#8" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(1)} -pin  "FRAME:for#1:mul#8" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(2)} -pin  "FRAME:for#1:mul#8" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(3)} -pin  "FRAME:for#1:mul#8" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(4)} -pin  "FRAME:for#1:mul#8" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(5)} -pin  "FRAME:for#1:mul#8" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(6)} -pin  "FRAME:for#1:mul#8" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(7)} -pin  "FRAME:for#1:mul#8" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(8)} -pin  "FRAME:for#1:mul#8" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {regs.operator[]#23:mux.itm(9)} -pin  "FRAME:for#1:mul#8" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#23:mux.itm}
+load net {FRAME:for#1:or#1.itm} -pin  "FRAME:for#1:mul#8" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for#1:nor.cse} -pin  "FRAME:for#1:mul#8" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for#1:mul#8.itm(0)} -pin  "FRAME:for#1:mul#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(1)} -pin  "FRAME:for#1:mul#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(2)} -pin  "FRAME:for#1:mul#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(3)} -pin  "FRAME:for#1:mul#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(4)} -pin  "FRAME:for#1:mul#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(5)} -pin  "FRAME:for#1:mul#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(6)} -pin  "FRAME:for#1:mul#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(7)} -pin  "FRAME:for#1:mul#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(8)} -pin  "FRAME:for#1:mul#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(9)} -pin  "FRAME:for#1:mul#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(10)} -pin  "FRAME:for#1:mul#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load inst "FRAME:for#1:acc#14" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 40075 -attr oid 562 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc#14} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {b(2).lpi#1.dfm(0)} -pin  "FRAME:for#1:acc#14" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(1)} -pin  "FRAME:for#1:acc#14" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(2)} -pin  "FRAME:for#1:acc#14" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(3)} -pin  "FRAME:for#1:acc#14" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(4)} -pin  "FRAME:for#1:acc#14" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(5)} -pin  "FRAME:for#1:acc#14" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(6)} -pin  "FRAME:for#1:acc#14" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(7)} -pin  "FRAME:for#1:acc#14" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(8)} -pin  "FRAME:for#1:acc#14" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(9)} -pin  "FRAME:for#1:acc#14" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(10)} -pin  "FRAME:for#1:acc#14" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(11)} -pin  "FRAME:for#1:acc#14" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(12)} -pin  "FRAME:for#1:acc#14" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(13)} -pin  "FRAME:for#1:acc#14" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(14)} -pin  "FRAME:for#1:acc#14" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(15)} -pin  "FRAME:for#1:acc#14" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {FRAME:for#1:mul#8.itm(0)} -pin  "FRAME:for#1:acc#14" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(1)} -pin  "FRAME:for#1:acc#14" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(2)} -pin  "FRAME:for#1:acc#14" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(3)} -pin  "FRAME:for#1:acc#14" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(4)} -pin  "FRAME:for#1:acc#14" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(5)} -pin  "FRAME:for#1:acc#14" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(6)} -pin  "FRAME:for#1:acc#14" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(7)} -pin  "FRAME:for#1:acc#14" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(8)} -pin  "FRAME:for#1:acc#14" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(9)} -pin  "FRAME:for#1:acc#14" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {FRAME:for#1:mul#8.itm(10)} -pin  "FRAME:for#1:acc#14" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#8.itm}
+load net {b(2).sva#1(0)} -pin  "FRAME:for#1:acc#14" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(1)} -pin  "FRAME:for#1:acc#14" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(2)} -pin  "FRAME:for#1:acc#14" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(3)} -pin  "FRAME:for#1:acc#14" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(4)} -pin  "FRAME:for#1:acc#14" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(5)} -pin  "FRAME:for#1:acc#14" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(6)} -pin  "FRAME:for#1:acc#14" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(7)} -pin  "FRAME:for#1:acc#14" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(8)} -pin  "FRAME:for#1:acc#14" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(9)} -pin  "FRAME:for#1:acc#14" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(10)} -pin  "FRAME:for#1:acc#14" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(11)} -pin  "FRAME:for#1:acc#14" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(12)} -pin  "FRAME:for#1:acc#14" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(13)} -pin  "FRAME:for#1:acc#14" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(14)} -pin  "FRAME:for#1:acc#14" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load net {b(2).sva#1(15)} -pin  "FRAME:for#1:acc#14" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).sva#1}
+load inst "regs.operator[]#17:mux" "mux(4,10)" "INTERFACE" -attr xrf 40076 -attr oid 563 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#17:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm(0)} -pin  "regs.operator[]#17:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(1)} -pin  "regs.operator[]#17:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(2)} -pin  "regs.operator[]#17:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(3)} -pin  "regs.operator[]#17:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(4)} -pin  "regs.operator[]#17:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(5)} -pin  "regs.operator[]#17:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(6)} -pin  "regs.operator[]#17:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(7)} -pin  "regs.operator[]#17:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(8)} -pin  "regs.operator[]#17:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(2).lpi#1.dfm(9)} -pin  "regs.operator[]#17:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#3.itm}
+load net {regs.regs(1).sva(0)} -pin  "regs.operator[]#17:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(1)} -pin  "regs.operator[]#17:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(2)} -pin  "regs.operator[]#17:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(3)} -pin  "regs.operator[]#17:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(4)} -pin  "regs.operator[]#17:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(5)} -pin  "regs.operator[]#17:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(6)} -pin  "regs.operator[]#17:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(7)} -pin  "regs.operator[]#17:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(8)} -pin  "regs.operator[]#17:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(1).sva(9)} -pin  "regs.operator[]#17:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#3.itm}
+load net {regs.regs(0).sva(0)} -pin  "regs.operator[]#17:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(1)} -pin  "regs.operator[]#17:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(2)} -pin  "regs.operator[]#17:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(3)} -pin  "regs.operator[]#17:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(4)} -pin  "regs.operator[]#17:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(5)} -pin  "regs.operator[]#17:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(6)} -pin  "regs.operator[]#17:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(7)} -pin  "regs.operator[]#17:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(8)} -pin  "regs.operator[]#17:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {regs.regs(0).sva(9)} -pin  "regs.operator[]#17:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#3.itm}
+load net {i#7.lpi#1(0)} -pin  "regs.operator[]#17:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "regs.operator[]#17:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.operator[]#17:mux.itm(0)} -pin  "regs.operator[]#17:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(1)} -pin  "regs.operator[]#17:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(2)} -pin  "regs.operator[]#17:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(3)} -pin  "regs.operator[]#17:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(4)} -pin  "regs.operator[]#17:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(5)} -pin  "regs.operator[]#17:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(6)} -pin  "regs.operator[]#17:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(7)} -pin  "regs.operator[]#17:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(8)} -pin  "regs.operator[]#17:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(9)} -pin  "regs.operator[]#17:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load inst "FRAME:for#1:mul#2" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 40077 -attr oid 564 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#17:mux.itm(0)} -pin  "FRAME:for#1:mul#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(1)} -pin  "FRAME:for#1:mul#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(2)} -pin  "FRAME:for#1:mul#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(3)} -pin  "FRAME:for#1:mul#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(4)} -pin  "FRAME:for#1:mul#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(5)} -pin  "FRAME:for#1:mul#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(6)} -pin  "FRAME:for#1:mul#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(7)} -pin  "FRAME:for#1:mul#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(8)} -pin  "FRAME:for#1:mul#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {regs.operator[]#17:mux.itm(9)} -pin  "FRAME:for#1:mul#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#17:mux.itm}
+load net {FRAME:for#1:or.itm} -pin  "FRAME:for#1:mul#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {PWR} -pin  "FRAME:for#1:mul#2" {B(1)} -attr @path {/sobel/sobel:core/conc#156.itm}
+load net {FRAME:for#1:mul#2.itm(0)} -pin  "FRAME:for#1:mul#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(1)} -pin  "FRAME:for#1:mul#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(2)} -pin  "FRAME:for#1:mul#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(3)} -pin  "FRAME:for#1:mul#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(4)} -pin  "FRAME:for#1:mul#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(5)} -pin  "FRAME:for#1:mul#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(6)} -pin  "FRAME:for#1:mul#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(7)} -pin  "FRAME:for#1:mul#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(8)} -pin  "FRAME:for#1:mul#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(9)} -pin  "FRAME:for#1:mul#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(10)} -pin  "FRAME:for#1:mul#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(11)} -pin  "FRAME:for#1:mul#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load inst "FRAME:for#1:acc#3" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 40078 -attr oid 565 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc#3} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {b(0).lpi#1.dfm(0)} -pin  "FRAME:for#1:acc#3" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(1)} -pin  "FRAME:for#1:acc#3" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(2)} -pin  "FRAME:for#1:acc#3" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(3)} -pin  "FRAME:for#1:acc#3" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(4)} -pin  "FRAME:for#1:acc#3" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(5)} -pin  "FRAME:for#1:acc#3" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(6)} -pin  "FRAME:for#1:acc#3" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(7)} -pin  "FRAME:for#1:acc#3" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(8)} -pin  "FRAME:for#1:acc#3" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(9)} -pin  "FRAME:for#1:acc#3" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(10)} -pin  "FRAME:for#1:acc#3" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(11)} -pin  "FRAME:for#1:acc#3" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(12)} -pin  "FRAME:for#1:acc#3" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(13)} -pin  "FRAME:for#1:acc#3" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(14)} -pin  "FRAME:for#1:acc#3" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(15)} -pin  "FRAME:for#1:acc#3" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {FRAME:for#1:mul#2.itm(0)} -pin  "FRAME:for#1:acc#3" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(1)} -pin  "FRAME:for#1:acc#3" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(2)} -pin  "FRAME:for#1:acc#3" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(3)} -pin  "FRAME:for#1:acc#3" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(4)} -pin  "FRAME:for#1:acc#3" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(5)} -pin  "FRAME:for#1:acc#3" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(6)} -pin  "FRAME:for#1:acc#3" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(7)} -pin  "FRAME:for#1:acc#3" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(8)} -pin  "FRAME:for#1:acc#3" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(9)} -pin  "FRAME:for#1:acc#3" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(10)} -pin  "FRAME:for#1:acc#3" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {FRAME:for#1:mul#2.itm(11)} -pin  "FRAME:for#1:acc#3" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#2.itm}
+load net {b(0).sva#1(0)} -pin  "FRAME:for#1:acc#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(1)} -pin  "FRAME:for#1:acc#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(2)} -pin  "FRAME:for#1:acc#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(3)} -pin  "FRAME:for#1:acc#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(4)} -pin  "FRAME:for#1:acc#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(5)} -pin  "FRAME:for#1:acc#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(6)} -pin  "FRAME:for#1:acc#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(7)} -pin  "FRAME:for#1:acc#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(8)} -pin  "FRAME:for#1:acc#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(9)} -pin  "FRAME:for#1:acc#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(10)} -pin  "FRAME:for#1:acc#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(11)} -pin  "FRAME:for#1:acc#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(12)} -pin  "FRAME:for#1:acc#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(13)} -pin  "FRAME:for#1:acc#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(14)} -pin  "FRAME:for#1:acc#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load net {b(0).sva#1(15)} -pin  "FRAME:for#1:acc#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).sva#1}
+load inst "FRAME:for:and#8" "and(2,15)" "INTERFACE" -attr xrf 40079 -attr oid 566 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#8} -attr area 10.947486 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(15,2)"
+load net {g(1).sg1.lpi#1(0)} -pin  "FRAME:for:and#8" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(1)} -pin  "FRAME:for:and#8" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(2)} -pin  "FRAME:for:and#8" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(3)} -pin  "FRAME:for:and#8" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(4)} -pin  "FRAME:for:and#8" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(5)} -pin  "FRAME:for:and#8" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(6)} -pin  "FRAME:for:and#8" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(7)} -pin  "FRAME:for:and#8" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(8)} -pin  "FRAME:for:and#8" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(9)} -pin  "FRAME:for:and#8" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(10)} -pin  "FRAME:for:and#8" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(11)} -pin  "FRAME:for:and#8" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(12)} -pin  "FRAME:for:and#8" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(13)} -pin  "FRAME:for:and#8" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {g(1).sg1.lpi#1(14)} -pin  "FRAME:for:and#8" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {not#24} -pin  "FRAME:for:and#8" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#36.itm}
+load net {g(1).sg1.lpi#1.dfm(0)} -pin  "FRAME:for:and#8" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(1)} -pin  "FRAME:for:and#8" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(2)} -pin  "FRAME:for:and#8" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(3)} -pin  "FRAME:for:and#8" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(4)} -pin  "FRAME:for:and#8" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(5)} -pin  "FRAME:for:and#8" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(6)} -pin  "FRAME:for:and#8" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(7)} -pin  "FRAME:for:and#8" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(8)} -pin  "FRAME:for:and#8" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(9)} -pin  "FRAME:for:and#8" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(10)} -pin  "FRAME:for:and#8" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(11)} -pin  "FRAME:for:and#8" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(12)} -pin  "FRAME:for:and#8" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(13)} -pin  "FRAME:for:and#8" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load net {g(1).sg1.lpi#1.dfm(14)} -pin  "FRAME:for:and#8" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(1).sg1.lpi#1.dfm}
+load inst "regs.operator[]#22:mux" "mux(4,10)" "INTERFACE" -attr xrf 40080 -attr oid 567 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#22:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm(70)} -pin  "regs.operator[]#22:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(71)} -pin  "regs.operator[]#22:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(72)} -pin  "regs.operator[]#22:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(73)} -pin  "regs.operator[]#22:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(74)} -pin  "regs.operator[]#22:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(75)} -pin  "regs.operator[]#22:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(76)} -pin  "regs.operator[]#22:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(77)} -pin  "regs.operator[]#22:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(78)} -pin  "regs.operator[]#22:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(2).lpi#1.dfm(79)} -pin  "regs.operator[]#22:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm}
+load net {regs.regs(1).sva(70)} -pin  "regs.operator[]#22:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(71)} -pin  "regs.operator[]#22:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(72)} -pin  "regs.operator[]#22:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(73)} -pin  "regs.operator[]#22:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(74)} -pin  "regs.operator[]#22:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(75)} -pin  "regs.operator[]#22:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(76)} -pin  "regs.operator[]#22:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(77)} -pin  "regs.operator[]#22:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(78)} -pin  "regs.operator[]#22:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(1).sva(79)} -pin  "regs.operator[]#22:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#1.itm}
+load net {regs.regs(0).sva(70)} -pin  "regs.operator[]#22:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(71)} -pin  "regs.operator[]#22:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(72)} -pin  "regs.operator[]#22:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(73)} -pin  "regs.operator[]#22:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(74)} -pin  "regs.operator[]#22:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(75)} -pin  "regs.operator[]#22:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(76)} -pin  "regs.operator[]#22:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(77)} -pin  "regs.operator[]#22:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(78)} -pin  "regs.operator[]#22:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {regs.regs(0).sva(79)} -pin  "regs.operator[]#22:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#1.itm}
+load net {i#7.lpi#1(0)} -pin  "regs.operator[]#22:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "regs.operator[]#22:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.operator[]#22:mux.itm(0)} -pin  "regs.operator[]#22:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(1)} -pin  "regs.operator[]#22:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(2)} -pin  "regs.operator[]#22:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(3)} -pin  "regs.operator[]#22:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(4)} -pin  "regs.operator[]#22:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(5)} -pin  "regs.operator[]#22:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(6)} -pin  "regs.operator[]#22:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(7)} -pin  "regs.operator[]#22:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(8)} -pin  "regs.operator[]#22:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(9)} -pin  "regs.operator[]#22:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load inst "FRAME:for#1:mul#7" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 40081 -attr oid 568 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#22:mux.itm(0)} -pin  "FRAME:for#1:mul#7" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(1)} -pin  "FRAME:for#1:mul#7" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(2)} -pin  "FRAME:for#1:mul#7" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(3)} -pin  "FRAME:for#1:mul#7" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(4)} -pin  "FRAME:for#1:mul#7" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(5)} -pin  "FRAME:for#1:mul#7" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(6)} -pin  "FRAME:for#1:mul#7" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(7)} -pin  "FRAME:for#1:mul#7" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(8)} -pin  "FRAME:for#1:mul#7" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {regs.operator[]#22:mux.itm(9)} -pin  "FRAME:for#1:mul#7" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#22:mux.itm}
+load net {FRAME:for#1:or#1.itm} -pin  "FRAME:for#1:mul#7" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for#1:nor.cse} -pin  "FRAME:for#1:mul#7" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for#1:mul#7.itm(0)} -pin  "FRAME:for#1:mul#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(1)} -pin  "FRAME:for#1:mul#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(2)} -pin  "FRAME:for#1:mul#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(3)} -pin  "FRAME:for#1:mul#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(4)} -pin  "FRAME:for#1:mul#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(5)} -pin  "FRAME:for#1:mul#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(6)} -pin  "FRAME:for#1:mul#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(7)} -pin  "FRAME:for#1:mul#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(8)} -pin  "FRAME:for#1:mul#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(9)} -pin  "FRAME:for#1:mul#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(10)} -pin  "FRAME:for#1:mul#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load inst "FRAME:for#1:acc#12" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 40082 -attr oid 569 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc#12} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {g(2).lpi#1.dfm(0)} -pin  "FRAME:for#1:acc#12" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(1)} -pin  "FRAME:for#1:acc#12" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(2)} -pin  "FRAME:for#1:acc#12" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(3)} -pin  "FRAME:for#1:acc#12" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(4)} -pin  "FRAME:for#1:acc#12" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(5)} -pin  "FRAME:for#1:acc#12" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(6)} -pin  "FRAME:for#1:acc#12" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(7)} -pin  "FRAME:for#1:acc#12" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(8)} -pin  "FRAME:for#1:acc#12" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(9)} -pin  "FRAME:for#1:acc#12" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(10)} -pin  "FRAME:for#1:acc#12" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(11)} -pin  "FRAME:for#1:acc#12" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(12)} -pin  "FRAME:for#1:acc#12" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(13)} -pin  "FRAME:for#1:acc#12" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(14)} -pin  "FRAME:for#1:acc#12" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(15)} -pin  "FRAME:for#1:acc#12" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {FRAME:for#1:mul#7.itm(0)} -pin  "FRAME:for#1:acc#12" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(1)} -pin  "FRAME:for#1:acc#12" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(2)} -pin  "FRAME:for#1:acc#12" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(3)} -pin  "FRAME:for#1:acc#12" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(4)} -pin  "FRAME:for#1:acc#12" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(5)} -pin  "FRAME:for#1:acc#12" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(6)} -pin  "FRAME:for#1:acc#12" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(7)} -pin  "FRAME:for#1:acc#12" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(8)} -pin  "FRAME:for#1:acc#12" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(9)} -pin  "FRAME:for#1:acc#12" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {FRAME:for#1:mul#7.itm(10)} -pin  "FRAME:for#1:acc#12" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#7.itm}
+load net {g(2).sva#1(0)} -pin  "FRAME:for#1:acc#12" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(1)} -pin  "FRAME:for#1:acc#12" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(2)} -pin  "FRAME:for#1:acc#12" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(3)} -pin  "FRAME:for#1:acc#12" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(4)} -pin  "FRAME:for#1:acc#12" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(5)} -pin  "FRAME:for#1:acc#12" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(6)} -pin  "FRAME:for#1:acc#12" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(7)} -pin  "FRAME:for#1:acc#12" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(8)} -pin  "FRAME:for#1:acc#12" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(9)} -pin  "FRAME:for#1:acc#12" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(10)} -pin  "FRAME:for#1:acc#12" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(11)} -pin  "FRAME:for#1:acc#12" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(12)} -pin  "FRAME:for#1:acc#12" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(13)} -pin  "FRAME:for#1:acc#12" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(14)} -pin  "FRAME:for#1:acc#12" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load net {g(2).sva#1(15)} -pin  "FRAME:for#1:acc#12" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).sva#1}
+load inst "regs.operator[]#16:mux" "mux(4,10)" "INTERFACE" -attr xrf 40083 -attr oid 570 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#16:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm(10)} -pin  "regs.operator[]#16:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(11)} -pin  "regs.operator[]#16:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(12)} -pin  "regs.operator[]#16:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(13)} -pin  "regs.operator[]#16:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(14)} -pin  "regs.operator[]#16:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(15)} -pin  "regs.operator[]#16:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(16)} -pin  "regs.operator[]#16:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(17)} -pin  "regs.operator[]#16:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(18)} -pin  "regs.operator[]#16:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(2).lpi#1.dfm(19)} -pin  "regs.operator[]#16:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#4.itm}
+load net {regs.regs(1).sva(10)} -pin  "regs.operator[]#16:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(11)} -pin  "regs.operator[]#16:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(12)} -pin  "regs.operator[]#16:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(13)} -pin  "regs.operator[]#16:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(14)} -pin  "regs.operator[]#16:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(15)} -pin  "regs.operator[]#16:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(16)} -pin  "regs.operator[]#16:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(17)} -pin  "regs.operator[]#16:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(18)} -pin  "regs.operator[]#16:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(1).sva(19)} -pin  "regs.operator[]#16:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#4.itm}
+load net {regs.regs(0).sva(10)} -pin  "regs.operator[]#16:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(11)} -pin  "regs.operator[]#16:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(12)} -pin  "regs.operator[]#16:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(13)} -pin  "regs.operator[]#16:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(14)} -pin  "regs.operator[]#16:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(15)} -pin  "regs.operator[]#16:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(16)} -pin  "regs.operator[]#16:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(17)} -pin  "regs.operator[]#16:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(18)} -pin  "regs.operator[]#16:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {regs.regs(0).sva(19)} -pin  "regs.operator[]#16:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#4.itm}
+load net {i#7.lpi#1(0)} -pin  "regs.operator[]#16:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "regs.operator[]#16:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.operator[]#16:mux.itm(0)} -pin  "regs.operator[]#16:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(1)} -pin  "regs.operator[]#16:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(2)} -pin  "regs.operator[]#16:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(3)} -pin  "regs.operator[]#16:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(4)} -pin  "regs.operator[]#16:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(5)} -pin  "regs.operator[]#16:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(6)} -pin  "regs.operator[]#16:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(7)} -pin  "regs.operator[]#16:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(8)} -pin  "regs.operator[]#16:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(9)} -pin  "regs.operator[]#16:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load inst "FRAME:for#1:mul#1" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 40084 -attr oid 571 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#16:mux.itm(0)} -pin  "FRAME:for#1:mul#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(1)} -pin  "FRAME:for#1:mul#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(2)} -pin  "FRAME:for#1:mul#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(3)} -pin  "FRAME:for#1:mul#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(4)} -pin  "FRAME:for#1:mul#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(5)} -pin  "FRAME:for#1:mul#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(6)} -pin  "FRAME:for#1:mul#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(7)} -pin  "FRAME:for#1:mul#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(8)} -pin  "FRAME:for#1:mul#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {regs.operator[]#16:mux.itm(9)} -pin  "FRAME:for#1:mul#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#16:mux.itm}
+load net {FRAME:for#1:or.itm} -pin  "FRAME:for#1:mul#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {PWR} -pin  "FRAME:for#1:mul#1" {B(1)} -attr @path {/sobel/sobel:core/conc#157.itm}
+load net {FRAME:for#1:mul#1.itm(0)} -pin  "FRAME:for#1:mul#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(1)} -pin  "FRAME:for#1:mul#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(2)} -pin  "FRAME:for#1:mul#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(3)} -pin  "FRAME:for#1:mul#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(4)} -pin  "FRAME:for#1:mul#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(5)} -pin  "FRAME:for#1:mul#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(6)} -pin  "FRAME:for#1:mul#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(7)} -pin  "FRAME:for#1:mul#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(8)} -pin  "FRAME:for#1:mul#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(9)} -pin  "FRAME:for#1:mul#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(10)} -pin  "FRAME:for#1:mul#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(11)} -pin  "FRAME:for#1:mul#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load inst "FRAME:for#1:acc#2" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 40085 -attr oid 572 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc#2} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {g(0).lpi#1.dfm(0)} -pin  "FRAME:for#1:acc#2" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(1)} -pin  "FRAME:for#1:acc#2" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(2)} -pin  "FRAME:for#1:acc#2" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(3)} -pin  "FRAME:for#1:acc#2" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(4)} -pin  "FRAME:for#1:acc#2" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(5)} -pin  "FRAME:for#1:acc#2" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(6)} -pin  "FRAME:for#1:acc#2" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(7)} -pin  "FRAME:for#1:acc#2" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(8)} -pin  "FRAME:for#1:acc#2" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(9)} -pin  "FRAME:for#1:acc#2" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(10)} -pin  "FRAME:for#1:acc#2" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(11)} -pin  "FRAME:for#1:acc#2" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(12)} -pin  "FRAME:for#1:acc#2" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(13)} -pin  "FRAME:for#1:acc#2" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(14)} -pin  "FRAME:for#1:acc#2" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(15)} -pin  "FRAME:for#1:acc#2" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {FRAME:for#1:mul#1.itm(0)} -pin  "FRAME:for#1:acc#2" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(1)} -pin  "FRAME:for#1:acc#2" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(2)} -pin  "FRAME:for#1:acc#2" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(3)} -pin  "FRAME:for#1:acc#2" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(4)} -pin  "FRAME:for#1:acc#2" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(5)} -pin  "FRAME:for#1:acc#2" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(6)} -pin  "FRAME:for#1:acc#2" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(7)} -pin  "FRAME:for#1:acc#2" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(8)} -pin  "FRAME:for#1:acc#2" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(9)} -pin  "FRAME:for#1:acc#2" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(10)} -pin  "FRAME:for#1:acc#2" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {FRAME:for#1:mul#1.itm(11)} -pin  "FRAME:for#1:acc#2" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul#1.itm}
+load net {g(0).sva#1(0)} -pin  "FRAME:for#1:acc#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(1)} -pin  "FRAME:for#1:acc#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(2)} -pin  "FRAME:for#1:acc#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(3)} -pin  "FRAME:for#1:acc#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(4)} -pin  "FRAME:for#1:acc#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(5)} -pin  "FRAME:for#1:acc#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(6)} -pin  "FRAME:for#1:acc#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(7)} -pin  "FRAME:for#1:acc#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(8)} -pin  "FRAME:for#1:acc#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(9)} -pin  "FRAME:for#1:acc#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(10)} -pin  "FRAME:for#1:acc#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(11)} -pin  "FRAME:for#1:acc#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(12)} -pin  "FRAME:for#1:acc#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(13)} -pin  "FRAME:for#1:acc#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(14)} -pin  "FRAME:for#1:acc#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load net {g(0).sva#1(15)} -pin  "FRAME:for#1:acc#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).sva#1}
+load inst "FRAME:for:and#7" "and(2,15)" "INTERFACE" -attr xrf 40086 -attr oid 573 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#7} -attr area 10.947486 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(15,2)"
+load net {r(1).sg1.lpi#1(0)} -pin  "FRAME:for:and#7" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(1)} -pin  "FRAME:for:and#7" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(2)} -pin  "FRAME:for:and#7" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(3)} -pin  "FRAME:for:and#7" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(4)} -pin  "FRAME:for:and#7" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(5)} -pin  "FRAME:for:and#7" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(6)} -pin  "FRAME:for:and#7" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(7)} -pin  "FRAME:for:and#7" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(8)} -pin  "FRAME:for:and#7" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(9)} -pin  "FRAME:for:and#7" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(10)} -pin  "FRAME:for:and#7" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(11)} -pin  "FRAME:for:and#7" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(12)} -pin  "FRAME:for:and#7" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(13)} -pin  "FRAME:for:and#7" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {r(1).sg1.lpi#1(14)} -pin  "FRAME:for:and#7" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {not#24} -pin  "FRAME:for:and#7" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#31.itm}
+load net {r(1).sg1.lpi#1.dfm(0)} -pin  "FRAME:for:and#7" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(1)} -pin  "FRAME:for:and#7" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(2)} -pin  "FRAME:for:and#7" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(3)} -pin  "FRAME:for:and#7" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(4)} -pin  "FRAME:for:and#7" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(5)} -pin  "FRAME:for:and#7" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(6)} -pin  "FRAME:for:and#7" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(7)} -pin  "FRAME:for:and#7" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(8)} -pin  "FRAME:for:and#7" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(9)} -pin  "FRAME:for:and#7" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(10)} -pin  "FRAME:for:and#7" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(11)} -pin  "FRAME:for:and#7" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(12)} -pin  "FRAME:for:and#7" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(13)} -pin  "FRAME:for:and#7" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load net {r(1).sg1.lpi#1.dfm(14)} -pin  "FRAME:for:and#7" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(1).sg1.lpi#1.dfm}
+load inst "regs.operator[]#21:mux" "mux(4,10)" "INTERFACE" -attr xrf 40087 -attr oid 574 -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#21:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm(80)} -pin  "regs.operator[]#21:mux" {A1(0)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(81)} -pin  "regs.operator[]#21:mux" {A1(1)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(82)} -pin  "regs.operator[]#21:mux" {A1(2)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(83)} -pin  "regs.operator[]#21:mux" {A1(3)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(84)} -pin  "regs.operator[]#21:mux" {A1(4)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(85)} -pin  "regs.operator[]#21:mux" {A1(5)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(86)} -pin  "regs.operator[]#21:mux" {A1(6)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(87)} -pin  "regs.operator[]#21:mux" {A1(7)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(88)} -pin  "regs.operator[]#21:mux" {A1(8)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(2).lpi#1.dfm(89)} -pin  "regs.operator[]#21:mux" {A1(9)} -attr vt dc -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm}
+load net {regs.regs(1).sva(80)} -pin  "regs.operator[]#21:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(81)} -pin  "regs.operator[]#21:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(82)} -pin  "regs.operator[]#21:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(83)} -pin  "regs.operator[]#21:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(84)} -pin  "regs.operator[]#21:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(85)} -pin  "regs.operator[]#21:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(86)} -pin  "regs.operator[]#21:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(87)} -pin  "regs.operator[]#21:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(88)} -pin  "regs.operator[]#21:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(1).sva(89)} -pin  "regs.operator[]#21:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#2.itm}
+load net {regs.regs(0).sva(80)} -pin  "regs.operator[]#21:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(81)} -pin  "regs.operator[]#21:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(82)} -pin  "regs.operator[]#21:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(83)} -pin  "regs.operator[]#21:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(84)} -pin  "regs.operator[]#21:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(85)} -pin  "regs.operator[]#21:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(86)} -pin  "regs.operator[]#21:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(87)} -pin  "regs.operator[]#21:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(88)} -pin  "regs.operator[]#21:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {regs.regs(0).sva(89)} -pin  "regs.operator[]#21:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#2.itm}
+load net {i#7.lpi#1(0)} -pin  "regs.operator[]#21:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "regs.operator[]#21:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.operator[]#21:mux.itm(0)} -pin  "regs.operator[]#21:mux" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(1)} -pin  "regs.operator[]#21:mux" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(2)} -pin  "regs.operator[]#21:mux" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(3)} -pin  "regs.operator[]#21:mux" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(4)} -pin  "regs.operator[]#21:mux" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(5)} -pin  "regs.operator[]#21:mux" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(6)} -pin  "regs.operator[]#21:mux" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(7)} -pin  "regs.operator[]#21:mux" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(8)} -pin  "regs.operator[]#21:mux" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(9)} -pin  "regs.operator[]#21:mux" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load inst "FRAME:for#1:mul#6" "mul(10,1,2,1,11)" "INTERFACE" -attr xrf 40088 -attr oid 575 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#21:mux.itm(0)} -pin  "FRAME:for#1:mul#6" {A(0)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(1)} -pin  "FRAME:for#1:mul#6" {A(1)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(2)} -pin  "FRAME:for#1:mul#6" {A(2)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(3)} -pin  "FRAME:for#1:mul#6" {A(3)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(4)} -pin  "FRAME:for#1:mul#6" {A(4)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(5)} -pin  "FRAME:for#1:mul#6" {A(5)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(6)} -pin  "FRAME:for#1:mul#6" {A(6)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(7)} -pin  "FRAME:for#1:mul#6" {A(7)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(8)} -pin  "FRAME:for#1:mul#6" {A(8)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {regs.operator[]#21:mux.itm(9)} -pin  "FRAME:for#1:mul#6" {A(9)} -attr vt dc -attr @path {/sobel/sobel:core/regs.operator[]#21:mux.itm}
+load net {FRAME:for#1:or#1.itm} -pin  "FRAME:for#1:mul#6" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for#1:nor.cse} -pin  "FRAME:for#1:mul#6" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:conc#16}
+load net {FRAME:for#1:mul#6.itm(0)} -pin  "FRAME:for#1:mul#6" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(1)} -pin  "FRAME:for#1:mul#6" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(2)} -pin  "FRAME:for#1:mul#6" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(3)} -pin  "FRAME:for#1:mul#6" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(4)} -pin  "FRAME:for#1:mul#6" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(5)} -pin  "FRAME:for#1:mul#6" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(6)} -pin  "FRAME:for#1:mul#6" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(7)} -pin  "FRAME:for#1:mul#6" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(8)} -pin  "FRAME:for#1:mul#6" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(9)} -pin  "FRAME:for#1:mul#6" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(10)} -pin  "FRAME:for#1:mul#6" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load inst "FRAME:for#1:acc#10" "add(16,-1,11,1,16)" "INTERFACE" -attr xrf 40089 -attr oid 576 -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:acc#10} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {r(2).lpi#1.dfm(0)} -pin  "FRAME:for#1:acc#10" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(1)} -pin  "FRAME:for#1:acc#10" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(2)} -pin  "FRAME:for#1:acc#10" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(3)} -pin  "FRAME:for#1:acc#10" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(4)} -pin  "FRAME:for#1:acc#10" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(5)} -pin  "FRAME:for#1:acc#10" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(6)} -pin  "FRAME:for#1:acc#10" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(7)} -pin  "FRAME:for#1:acc#10" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(8)} -pin  "FRAME:for#1:acc#10" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(9)} -pin  "FRAME:for#1:acc#10" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(10)} -pin  "FRAME:for#1:acc#10" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(11)} -pin  "FRAME:for#1:acc#10" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(12)} -pin  "FRAME:for#1:acc#10" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(13)} -pin  "FRAME:for#1:acc#10" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(14)} -pin  "FRAME:for#1:acc#10" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(15)} -pin  "FRAME:for#1:acc#10" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {FRAME:for#1:mul#6.itm(0)} -pin  "FRAME:for#1:acc#10" {B(0)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(1)} -pin  "FRAME:for#1:acc#10" {B(1)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(2)} -pin  "FRAME:for#1:acc#10" {B(2)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(3)} -pin  "FRAME:for#1:acc#10" {B(3)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(4)} -pin  "FRAME:for#1:acc#10" {B(4)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(5)} -pin  "FRAME:for#1:acc#10" {B(5)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(6)} -pin  "FRAME:for#1:acc#10" {B(6)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(7)} -pin  "FRAME:for#1:acc#10" {B(7)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(8)} -pin  "FRAME:for#1:acc#10" {B(8)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(9)} -pin  "FRAME:for#1:acc#10" {B(9)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {FRAME:for#1:mul#6.itm(10)} -pin  "FRAME:for#1:acc#10" {B(10)} -attr vt dc -attr @path {/sobel/sobel:core/FRAME:for#1:mul#6.itm}
+load net {r(2).sva#1(0)} -pin  "FRAME:for#1:acc#10" {Z(0)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(1)} -pin  "FRAME:for#1:acc#10" {Z(1)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(2)} -pin  "FRAME:for#1:acc#10" {Z(2)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(3)} -pin  "FRAME:for#1:acc#10" {Z(3)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(4)} -pin  "FRAME:for#1:acc#10" {Z(4)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(5)} -pin  "FRAME:for#1:acc#10" {Z(5)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(6)} -pin  "FRAME:for#1:acc#10" {Z(6)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(7)} -pin  "FRAME:for#1:acc#10" {Z(7)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(8)} -pin  "FRAME:for#1:acc#10" {Z(8)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(9)} -pin  "FRAME:for#1:acc#10" {Z(9)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(10)} -pin  "FRAME:for#1:acc#10" {Z(10)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(11)} -pin  "FRAME:for#1:acc#10" {Z(11)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(12)} -pin  "FRAME:for#1:acc#10" {Z(12)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(13)} -pin  "FRAME:for#1:acc#10" {Z(13)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(14)} -pin  "FRAME:for#1:acc#10" {Z(14)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load net {r(2).sva#1(15)} -pin  "FRAME:for#1:acc#10" {Z(15)} -attr vt dc -attr @path {/sobel/sobel:core/r(2).sva#1}
+load inst "regs.operator[]#15:mux" "mux(4,10)" "INTERFACE" -attr xrf 40090 -attr oid 577 -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux} -attr area 22.258830 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(10,2,4)"
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(0)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(1)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(2)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(3)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(4)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(5)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(6)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(7)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(8)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {DC} -pin  "regs.operator[]#15:mux" {A0(9)} -attr @path {/sobel/sobel:core/C----------_10}
+load net {regs.regs(2).lpi#1.dfm(20)} -pin  "regs.operator[]#15:mux" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(21)} -pin  "regs.operator[]#15:mux" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(22)} -pin  "regs.operator[]#15:mux" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(23)} -pin  "regs.operator[]#15:mux" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(24)} -pin  "regs.operator[]#15:mux" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(25)} -pin  "regs.operator[]#15:mux" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(26)} -pin  "regs.operator[]#15:mux" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(27)} -pin  "regs.operator[]#15:mux" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(28)} -pin  "regs.operator[]#15:mux" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(2).lpi#1.dfm(29)} -pin  "regs.operator[]#15:mux" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(2).lpi#1.dfm)#5.itm}
+load net {regs.regs(1).sva(20)} -pin  "regs.operator[]#15:mux" {A2(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(21)} -pin  "regs.operator[]#15:mux" {A2(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(22)} -pin  "regs.operator[]#15:mux" {A2(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(23)} -pin  "regs.operator[]#15:mux" {A2(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(24)} -pin  "regs.operator[]#15:mux" {A2(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(25)} -pin  "regs.operator[]#15:mux" {A2(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(26)} -pin  "regs.operator[]#15:mux" {A2(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(27)} -pin  "regs.operator[]#15:mux" {A2(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(28)} -pin  "regs.operator[]#15:mux" {A2(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(1).sva(29)} -pin  "regs.operator[]#15:mux" {A2(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(1).sva)#5.itm}
+load net {regs.regs(0).sva(20)} -pin  "regs.operator[]#15:mux" {A3(0)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(21)} -pin  "regs.operator[]#15:mux" {A3(1)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(22)} -pin  "regs.operator[]#15:mux" {A3(2)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(23)} -pin  "regs.operator[]#15:mux" {A3(3)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(24)} -pin  "regs.operator[]#15:mux" {A3(4)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(25)} -pin  "regs.operator[]#15:mux" {A3(5)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(26)} -pin  "regs.operator[]#15:mux" {A3(6)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(27)} -pin  "regs.operator[]#15:mux" {A3(7)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(28)} -pin  "regs.operator[]#15:mux" {A3(8)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {regs.regs(0).sva(29)} -pin  "regs.operator[]#15:mux" {A3(9)} -attr vt d -attr @path {/sobel/sobel:core/slc(regs.regs(0).sva)#5.itm}
+load net {i#7.lpi#1(0)} -pin  "regs.operator[]#15:mux" {S(0)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {i#7.lpi#1(1)} -pin  "regs.operator[]#15:mux" {S(1)} -attr vt d -attr @path {/sobel/sobel:core/i#7.lpi#1}
+load net {regs.operator[]#15:mux.itm(0)} -pin  "regs.operator[]#15:mux" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(1)} -pin  "regs.operator[]#15:mux" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(2)} -pin  "regs.operator[]#15:mux" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(3)} -pin  "regs.operator[]#15:mux" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(4)} -pin  "regs.operator[]#15:mux" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(5)} -pin  "regs.operator[]#15:mux" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(6)} -pin  "regs.operator[]#15:mux" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(7)} -pin  "regs.operator[]#15:mux" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(8)} -pin  "regs.operator[]#15:mux" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(9)} -pin  "regs.operator[]#15:mux" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load inst "FRAME:for#1:mul" "mul(10,1,2,1,12)" "INTERFACE" -attr xrf 40091 -attr oid 578 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul} -attr area 330.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(2,1,10,1,12)"
+load net {regs.operator[]#15:mux.itm(0)} -pin  "FRAME:for#1:mul" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(1)} -pin  "FRAME:for#1:mul" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(2)} -pin  "FRAME:for#1:mul" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(3)} -pin  "FRAME:for#1:mul" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(4)} -pin  "FRAME:for#1:mul" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(5)} -pin  "FRAME:for#1:mul" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(6)} -pin  "FRAME:for#1:mul" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(7)} -pin  "FRAME:for#1:mul" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(8)} -pin  "FRAME:for#1:mul" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {regs.operator[]#15:mux.itm(9)} -pin  "FRAME:for#1:mul" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/regs.operator[]#15:mux.itm}
+load net {FRAME:for#1:or.itm} -pin  "FRAME:for#1:mul" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {PWR} -pin  "FRAME:for#1:mul" {B(1)} -attr @path {/sobel/sobel:core/conc#158.itm}
+load net {FRAME:for#1:mul.itm(0)} -pin  "FRAME:for#1:mul" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(1)} -pin  "FRAME:for#1:mul" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(2)} -pin  "FRAME:for#1:mul" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(3)} -pin  "FRAME:for#1:mul" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(4)} -pin  "FRAME:for#1:mul" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(5)} -pin  "FRAME:for#1:mul" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(6)} -pin  "FRAME:for#1:mul" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(7)} -pin  "FRAME:for#1:mul" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(8)} -pin  "FRAME:for#1:mul" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(9)} -pin  "FRAME:for#1:mul" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(10)} -pin  "FRAME:for#1:mul" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(11)} -pin  "FRAME:for#1:mul" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load inst "FRAME:for#1:acc#1" "add(16,-1,12,1,16)" "INTERFACE" -attr xrf 40092 -attr oid 579 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:acc#1} -attr area 17.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(16,0,12,1,16)"
+load net {r(0).lpi#1.dfm(0)} -pin  "FRAME:for#1:acc#1" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(1)} -pin  "FRAME:for#1:acc#1" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(2)} -pin  "FRAME:for#1:acc#1" {A(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(3)} -pin  "FRAME:for#1:acc#1" {A(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(4)} -pin  "FRAME:for#1:acc#1" {A(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(5)} -pin  "FRAME:for#1:acc#1" {A(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(6)} -pin  "FRAME:for#1:acc#1" {A(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(7)} -pin  "FRAME:for#1:acc#1" {A(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(8)} -pin  "FRAME:for#1:acc#1" {A(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(9)} -pin  "FRAME:for#1:acc#1" {A(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(10)} -pin  "FRAME:for#1:acc#1" {A(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(11)} -pin  "FRAME:for#1:acc#1" {A(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(12)} -pin  "FRAME:for#1:acc#1" {A(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(13)} -pin  "FRAME:for#1:acc#1" {A(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(14)} -pin  "FRAME:for#1:acc#1" {A(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(15)} -pin  "FRAME:for#1:acc#1" {A(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {FRAME:for#1:mul.itm(0)} -pin  "FRAME:for#1:acc#1" {B(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(1)} -pin  "FRAME:for#1:acc#1" {B(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(2)} -pin  "FRAME:for#1:acc#1" {B(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(3)} -pin  "FRAME:for#1:acc#1" {B(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(4)} -pin  "FRAME:for#1:acc#1" {B(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(5)} -pin  "FRAME:for#1:acc#1" {B(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(6)} -pin  "FRAME:for#1:acc#1" {B(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(7)} -pin  "FRAME:for#1:acc#1" {B(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(8)} -pin  "FRAME:for#1:acc#1" {B(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(9)} -pin  "FRAME:for#1:acc#1" {B(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(10)} -pin  "FRAME:for#1:acc#1" {B(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {FRAME:for#1:mul.itm(11)} -pin  "FRAME:for#1:acc#1" {B(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for#1:mul.itm}
+load net {r(0).sva#1(0)} -pin  "FRAME:for#1:acc#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(1)} -pin  "FRAME:for#1:acc#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(2)} -pin  "FRAME:for#1:acc#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(3)} -pin  "FRAME:for#1:acc#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(4)} -pin  "FRAME:for#1:acc#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(5)} -pin  "FRAME:for#1:acc#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(6)} -pin  "FRAME:for#1:acc#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(7)} -pin  "FRAME:for#1:acc#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(8)} -pin  "FRAME:for#1:acc#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(9)} -pin  "FRAME:for#1:acc#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(10)} -pin  "FRAME:for#1:acc#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(11)} -pin  "FRAME:for#1:acc#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(12)} -pin  "FRAME:for#1:acc#1" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(13)} -pin  "FRAME:for#1:acc#1" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(14)} -pin  "FRAME:for#1:acc#1" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load net {r(0).sva#1(15)} -pin  "FRAME:for#1:acc#1" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).sva#1}
+load inst "FRAME:for:and#5" "and(2,16)" "INTERFACE" -attr xrf 40093 -attr oid 580 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#5} -attr area 11.677318 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2)"
+load net {b(2).lpi#1(0)} -pin  "FRAME:for:and#5" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(1)} -pin  "FRAME:for:and#5" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(2)} -pin  "FRAME:for:and#5" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(3)} -pin  "FRAME:for:and#5" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(4)} -pin  "FRAME:for:and#5" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(5)} -pin  "FRAME:for:and#5" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(6)} -pin  "FRAME:for:and#5" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(7)} -pin  "FRAME:for:and#5" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(8)} -pin  "FRAME:for:and#5" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(9)} -pin  "FRAME:for:and#5" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(10)} -pin  "FRAME:for:and#5" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(11)} -pin  "FRAME:for:and#5" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(12)} -pin  "FRAME:for:and#5" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(13)} -pin  "FRAME:for:and#5" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(14)} -pin  "FRAME:for:and#5" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {b(2).lpi#1(15)} -pin  "FRAME:for:and#5" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {not#24} -pin  "FRAME:for:and#5" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#37.itm}
+load net {b(2).lpi#1.dfm(0)} -pin  "FRAME:for:and#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(1)} -pin  "FRAME:for:and#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(2)} -pin  "FRAME:for:and#5" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(3)} -pin  "FRAME:for:and#5" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(4)} -pin  "FRAME:for:and#5" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(5)} -pin  "FRAME:for:and#5" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(6)} -pin  "FRAME:for:and#5" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(7)} -pin  "FRAME:for:and#5" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(8)} -pin  "FRAME:for:and#5" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(9)} -pin  "FRAME:for:and#5" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(10)} -pin  "FRAME:for:and#5" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(11)} -pin  "FRAME:for:and#5" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(12)} -pin  "FRAME:for:and#5" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(13)} -pin  "FRAME:for:and#5" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(14)} -pin  "FRAME:for:and#5" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load net {b(2).lpi#1.dfm(15)} -pin  "FRAME:for:and#5" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(2).lpi#1.dfm}
+load inst "FRAME:for#1:nor" "nor(2,1)" "INTERFACE" -attr xrf 40094 -attr oid 581 -attr @path {/sobel/sobel:core/FRAME:for#1:nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {i#7.lpi#1(1)} -pin  "FRAME:for#1:nor" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#3.itm}
+load net {i#7.lpi#1(0)} -pin  "FRAME:for#1:nor" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#4.itm}
+load net {FRAME:for#1:nor.cse} -pin  "FRAME:for#1:nor" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nor.cse}
+load inst "FRAME:for:and#3" "and(2,16)" "INTERFACE" -attr xrf 40095 -attr oid 582 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#3} -attr area 11.677318 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2)"
+load net {g(2).lpi#1(0)} -pin  "FRAME:for:and#3" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(1)} -pin  "FRAME:for:and#3" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(2)} -pin  "FRAME:for:and#3" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(3)} -pin  "FRAME:for:and#3" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(4)} -pin  "FRAME:for:and#3" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(5)} -pin  "FRAME:for:and#3" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(6)} -pin  "FRAME:for:and#3" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(7)} -pin  "FRAME:for:and#3" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(8)} -pin  "FRAME:for:and#3" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(9)} -pin  "FRAME:for:and#3" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(10)} -pin  "FRAME:for:and#3" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(11)} -pin  "FRAME:for:and#3" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(12)} -pin  "FRAME:for:and#3" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(13)} -pin  "FRAME:for:and#3" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(14)} -pin  "FRAME:for:and#3" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {g(2).lpi#1(15)} -pin  "FRAME:for:and#3" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {not#24} -pin  "FRAME:for:and#3" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#39.itm}
+load net {g(2).lpi#1.dfm(0)} -pin  "FRAME:for:and#3" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(1)} -pin  "FRAME:for:and#3" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(2)} -pin  "FRAME:for:and#3" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(3)} -pin  "FRAME:for:and#3" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(4)} -pin  "FRAME:for:and#3" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(5)} -pin  "FRAME:for:and#3" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(6)} -pin  "FRAME:for:and#3" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(7)} -pin  "FRAME:for:and#3" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(8)} -pin  "FRAME:for:and#3" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(9)} -pin  "FRAME:for:and#3" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(10)} -pin  "FRAME:for:and#3" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(11)} -pin  "FRAME:for:and#3" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(12)} -pin  "FRAME:for:and#3" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(13)} -pin  "FRAME:for:and#3" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(14)} -pin  "FRAME:for:and#3" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load net {g(2).lpi#1.dfm(15)} -pin  "FRAME:for:and#3" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(2).lpi#1.dfm}
+load inst "FRAME:for:and#1" "and(2,16)" "INTERFACE" -attr xrf 40096 -attr oid 583 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#1} -attr area 11.677318 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2)"
+load net {r(2).lpi#1(0)} -pin  "FRAME:for:and#1" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(1)} -pin  "FRAME:for:and#1" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(2)} -pin  "FRAME:for:and#1" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(3)} -pin  "FRAME:for:and#1" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(4)} -pin  "FRAME:for:and#1" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(5)} -pin  "FRAME:for:and#1" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(6)} -pin  "FRAME:for:and#1" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(7)} -pin  "FRAME:for:and#1" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(8)} -pin  "FRAME:for:and#1" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(9)} -pin  "FRAME:for:and#1" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(10)} -pin  "FRAME:for:and#1" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(11)} -pin  "FRAME:for:and#1" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(12)} -pin  "FRAME:for:and#1" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(13)} -pin  "FRAME:for:and#1" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(14)} -pin  "FRAME:for:and#1" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {r(2).lpi#1(15)} -pin  "FRAME:for:and#1" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {not#24} -pin  "FRAME:for:and#1" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#41.itm}
+load net {r(2).lpi#1.dfm(0)} -pin  "FRAME:for:and#1" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(1)} -pin  "FRAME:for:and#1" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(2)} -pin  "FRAME:for:and#1" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(3)} -pin  "FRAME:for:and#1" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(4)} -pin  "FRAME:for:and#1" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(5)} -pin  "FRAME:for:and#1" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(6)} -pin  "FRAME:for:and#1" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(7)} -pin  "FRAME:for:and#1" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(8)} -pin  "FRAME:for:and#1" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(9)} -pin  "FRAME:for:and#1" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(10)} -pin  "FRAME:for:and#1" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(11)} -pin  "FRAME:for:and#1" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(12)} -pin  "FRAME:for:and#1" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(13)} -pin  "FRAME:for:and#1" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(14)} -pin  "FRAME:for:and#1" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load net {r(2).lpi#1.dfm(15)} -pin  "FRAME:for:and#1" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(2).lpi#1.dfm}
+load inst "FRAME:for:and#4" "and(2,16)" "INTERFACE" -attr xrf 40097 -attr oid 584 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#4} -attr area 11.677318 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2)"
+load net {b(0).lpi#1(0)} -pin  "FRAME:for:and#4" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(1)} -pin  "FRAME:for:and#4" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(2)} -pin  "FRAME:for:and#4" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(3)} -pin  "FRAME:for:and#4" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(4)} -pin  "FRAME:for:and#4" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(5)} -pin  "FRAME:for:and#4" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(6)} -pin  "FRAME:for:and#4" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(7)} -pin  "FRAME:for:and#4" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(8)} -pin  "FRAME:for:and#4" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(9)} -pin  "FRAME:for:and#4" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(10)} -pin  "FRAME:for:and#4" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(11)} -pin  "FRAME:for:and#4" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(12)} -pin  "FRAME:for:and#4" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(13)} -pin  "FRAME:for:and#4" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(14)} -pin  "FRAME:for:and#4" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {b(0).lpi#1(15)} -pin  "FRAME:for:and#4" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {not#24} -pin  "FRAME:for:and#4" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#38.itm}
+load net {b(0).lpi#1.dfm(0)} -pin  "FRAME:for:and#4" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(1)} -pin  "FRAME:for:and#4" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(2)} -pin  "FRAME:for:and#4" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(3)} -pin  "FRAME:for:and#4" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(4)} -pin  "FRAME:for:and#4" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(5)} -pin  "FRAME:for:and#4" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(6)} -pin  "FRAME:for:and#4" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(7)} -pin  "FRAME:for:and#4" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(8)} -pin  "FRAME:for:and#4" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(9)} -pin  "FRAME:for:and#4" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(10)} -pin  "FRAME:for:and#4" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(11)} -pin  "FRAME:for:and#4" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(12)} -pin  "FRAME:for:and#4" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(13)} -pin  "FRAME:for:and#4" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(14)} -pin  "FRAME:for:and#4" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load net {b(0).lpi#1.dfm(15)} -pin  "FRAME:for:and#4" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/b(0).lpi#1.dfm}
+load inst "FRAME:for:and#2" "and(2,16)" "INTERFACE" -attr xrf 40098 -attr oid 585 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#2} -attr area 11.677318 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2)"
+load net {g(0).lpi#1(0)} -pin  "FRAME:for:and#2" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(1)} -pin  "FRAME:for:and#2" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(2)} -pin  "FRAME:for:and#2" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(3)} -pin  "FRAME:for:and#2" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(4)} -pin  "FRAME:for:and#2" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(5)} -pin  "FRAME:for:and#2" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(6)} -pin  "FRAME:for:and#2" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(7)} -pin  "FRAME:for:and#2" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(8)} -pin  "FRAME:for:and#2" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(9)} -pin  "FRAME:for:and#2" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(10)} -pin  "FRAME:for:and#2" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(11)} -pin  "FRAME:for:and#2" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(12)} -pin  "FRAME:for:and#2" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(13)} -pin  "FRAME:for:and#2" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(14)} -pin  "FRAME:for:and#2" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {g(0).lpi#1(15)} -pin  "FRAME:for:and#2" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {not#24} -pin  "FRAME:for:and#2" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#40.itm}
+load net {g(0).lpi#1.dfm(0)} -pin  "FRAME:for:and#2" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(1)} -pin  "FRAME:for:and#2" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(2)} -pin  "FRAME:for:and#2" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(3)} -pin  "FRAME:for:and#2" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(4)} -pin  "FRAME:for:and#2" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(5)} -pin  "FRAME:for:and#2" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(6)} -pin  "FRAME:for:and#2" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(7)} -pin  "FRAME:for:and#2" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(8)} -pin  "FRAME:for:and#2" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(9)} -pin  "FRAME:for:and#2" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(10)} -pin  "FRAME:for:and#2" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(11)} -pin  "FRAME:for:and#2" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(12)} -pin  "FRAME:for:and#2" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(13)} -pin  "FRAME:for:and#2" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(14)} -pin  "FRAME:for:and#2" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load net {g(0).lpi#1.dfm(15)} -pin  "FRAME:for:and#2" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/g(0).lpi#1.dfm}
+load inst "FRAME:for:and" "and(2,16)" "INTERFACE" -attr xrf 40099 -attr oid 586 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and} -attr area 11.677318 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(16,2)"
+load net {r(0).lpi#1(0)} -pin  "FRAME:for:and" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(1)} -pin  "FRAME:for:and" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(2)} -pin  "FRAME:for:and" {A0(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(3)} -pin  "FRAME:for:and" {A0(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(4)} -pin  "FRAME:for:and" {A0(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(5)} -pin  "FRAME:for:and" {A0(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(6)} -pin  "FRAME:for:and" {A0(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(7)} -pin  "FRAME:for:and" {A0(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(8)} -pin  "FRAME:for:and" {A0(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(9)} -pin  "FRAME:for:and" {A0(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(10)} -pin  "FRAME:for:and" {A0(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(11)} -pin  "FRAME:for:and" {A0(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(12)} -pin  "FRAME:for:and" {A0(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(13)} -pin  "FRAME:for:and" {A0(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(14)} -pin  "FRAME:for:and" {A0(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {r(0).lpi#1(15)} -pin  "FRAME:for:and" {A0(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1}
+load net {not#24} -pin  "FRAME:for:and" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(2)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(3)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(4)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(5)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(6)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(7)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(8)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(9)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(10)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(11)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(12)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(13)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(14)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {not#24} -pin  "FRAME:for:and" {A1(15)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#33.itm}
+load net {r(0).lpi#1.dfm(0)} -pin  "FRAME:for:and" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(1)} -pin  "FRAME:for:and" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(2)} -pin  "FRAME:for:and" {Z(2)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(3)} -pin  "FRAME:for:and" {Z(3)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(4)} -pin  "FRAME:for:and" {Z(4)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(5)} -pin  "FRAME:for:and" {Z(5)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(6)} -pin  "FRAME:for:and" {Z(6)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(7)} -pin  "FRAME:for:and" {Z(7)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(8)} -pin  "FRAME:for:and" {Z(8)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(9)} -pin  "FRAME:for:and" {Z(9)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(10)} -pin  "FRAME:for:and" {Z(10)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(11)} -pin  "FRAME:for:and" {Z(11)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(12)} -pin  "FRAME:for:and" {Z(12)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(13)} -pin  "FRAME:for:and" {Z(13)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(14)} -pin  "FRAME:for:and" {Z(14)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load net {r(0).lpi#1.dfm(15)} -pin  "FRAME:for:and" {Z(15)} -attr vt d -attr @path {/sobel/sobel:core/r(0).lpi#1.dfm}
+load inst "FRAME:for:acc#16" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 40100 -attr oid 587 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#16} -attr area 3.310766 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,2,0,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:acc#16" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:acc#16" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:for:acc#16" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {i#6.sva#1(0)} -pin  "FRAME:for:acc#16" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "FRAME:for:acc#16" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load inst "FRAME:for:and#6" "and(2,2)" "INTERFACE" -attr xrf 40101 -attr oid 588 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:and#6} -attr area 1.459665 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(2,2)"
+load net {i#6.lpi#1(0)} -pin  "FRAME:for:and#6" {A0(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1}
+load net {i#6.lpi#1(1)} -pin  "FRAME:for:and#6" {A0(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1}
+load net {not#24} -pin  "FRAME:for:and#6" {A1(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#26.itm}
+load net {not#24} -pin  "FRAME:for:and#6" {A1(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:exs#26.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:and#6" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:and#6" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load inst "FRAME:for:nor" "nor(2,1)" "INTERFACE" -attr xrf 40102 -attr oid 589 -attr @path {/sobel/sobel:core/FRAME:for:nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:nor" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#2.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nor" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#3.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:nor" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load inst "FRAME:for:and#18" "and(2,1)" "INTERFACE" -attr xrf 40103 -attr oid 590 -attr @path {/sobel/sobel:core/FRAME:for:and#18} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {FRAME:for:acc#5.tmp(1)} -pin  "FRAME:for:and#18" {A0(0)} -attr @path {/sobel/sobel:core/slc(FRAME:for:acc#5.tmp).itm}
+load net {FRAME:for:acc#5.tmp(0)} -pin  "FRAME:for:and#18" {A1(0)} -attr @path {/sobel/sobel:core/slc(FRAME:for:acc#5.tmp)#1.itm}
+load net {FRAME:for:and#18.seb} -pin  "FRAME:for:and#18" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#18.seb}
+load inst "FRAME:for:acc#5" "add(2,-1,1,1,2)" "INTERFACE" -attr xrf 40104 -attr oid 591 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#5} -attr area 3.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:acc#5" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:acc#5" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.lpi#1.dfm}
+load net {PWR} -pin  "FRAME:for:acc#5" {B(0)} -attr @path {/sobel/sobel:core/Cn1_1}
+load net {FRAME:for:acc#5.tmp(0)} -pin  "FRAME:for:acc#5" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#5.tmp}
+load net {FRAME:for:acc#5.tmp(1)} -pin  "FRAME:for:acc#5" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc#5.tmp}
+load inst "nor#2" "nor(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/nor#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {exit:FRAME:for#1.lpi#1.dfm#4} -pin  "nor#2" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4}
+load net {exit:FRAME#1.sva} -pin  "nor#2" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {not#24} -pin  "nor#2" {Z(0)} -attr @path {/sobel/sobel:core/not#24}
+load inst "FRAME:for#1:not#8" "not(1)" "INTERFACE" -attr xrf 40105 -attr oid 592 -attr @path {/sobel/sobel:core/FRAME:for#1:not#8} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#7.lpi#1(1)} -pin  "FRAME:for#1:not#8" {A(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#7.itm}
+load net {FRAME:for#1:not#8.itm} -pin  "FRAME:for#1:not#8" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#8.itm}
+load inst "FRAME:for#1:nand#1" "nand(2,1)" "INTERFACE" -attr xrf 40106 -attr oid 593 -attr @path {/sobel/sobel:core/FRAME:for#1:nand#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {FRAME:for#1:not#8.itm} -pin  "FRAME:for#1:nand#1" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#8.itm}
+load net {i#7.lpi#1(0)} -pin  "FRAME:for#1:nand#1" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#8.itm}
+load net {FRAME:for#1:nand#1.itm} -pin  "FRAME:for#1:nand#1" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nand#1.itm}
+load inst "FRAME:for#1:or#1" "or(2,1)" "INTERFACE" -attr xrf 40107 -attr oid 594 -attr @path {/sobel/sobel:core/FRAME:for#1:or#1} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {FRAME:for#1:nand#1.itm} -pin  "FRAME:for#1:or#1" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nand#1.itm}
+load net {FRAME:for#1:nor.cse} -pin  "FRAME:for#1:or#1" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nor.cse}
+load net {FRAME:for#1:or#1.itm} -pin  "FRAME:for#1:or#1" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:or#1.itm}
+load inst "FRAME:for#1:not#5" "not(1)" "INTERFACE" -attr xrf 40108 -attr oid 595 -attr @path {/sobel/sobel:core/FRAME:for#1:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#7.lpi#1(1)} -pin  "FRAME:for#1:not#5" {A(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#5.itm}
+load net {FRAME:for#1:not#5.itm} -pin  "FRAME:for#1:not#5" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#5.itm}
+load inst "FRAME:for#1:nand" "nand(2,1)" "INTERFACE" -attr xrf 40109 -attr oid 596 -attr @path {/sobel/sobel:core/FRAME:for#1:nand} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {i#7.lpi#1(0)} -pin  "FRAME:for#1:nand" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#9.itm}
+load net {FRAME:for#1:not#5.itm} -pin  "FRAME:for#1:nand" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#5.itm}
+load net {FRAME:for#1:nand.itm} -pin  "FRAME:for#1:nand" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nand.itm}
+load inst "FRAME:for#1:not#2" "not(1)" "INTERFACE" -attr xrf 40110 -attr oid 597 -attr @path {/sobel/sobel:core/FRAME:for#1:not#2} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#7.lpi#1(0)} -pin  "FRAME:for#1:not#2" {A(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#10.itm}
+load net {FRAME:for#1:not#2.itm} -pin  "FRAME:for#1:not#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#2.itm}
+load inst "FRAME:for#1:and" "and(2,1)" "INTERFACE" -attr xrf 40111 -attr oid 598 -attr @path {/sobel/sobel:core/FRAME:for#1:and} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(1,2)"
+load net {i#7.lpi#1(1)} -pin  "FRAME:for#1:and" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#7.lpi#1)#6.itm}
+load net {FRAME:for#1:not#2.itm} -pin  "FRAME:for#1:and" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:not#2.itm}
+load net {FRAME:for#1:and.itm} -pin  "FRAME:for#1:and" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:and.itm}
+load inst "FRAME:for#1:or" "or(3,1)" "INTERFACE" -attr xrf 40112 -attr oid 599 -attr @path {/sobel/sobel:core/FRAME:for#1:or} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,3)"
+load net {FRAME:for#1:nand.itm} -pin  "FRAME:for#1:or" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nand.itm}
+load net {FRAME:for#1:nor.cse} -pin  "FRAME:for#1:or" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:nor.cse}
+load net {FRAME:for#1:and.itm} -pin  "FRAME:for#1:or" {A2(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:and.itm}
+load net {FRAME:for#1:or.itm} -pin  "FRAME:for#1:or" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:or.itm}
+load inst "FRAME:for:not#6" "not(1)" "INTERFACE" -attr xrf 40113 -attr oid 600 -attr @path {/sobel/sobel:core/FRAME:for:not#6} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#6" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#5.itm}
+load net {FRAME:for:not#6.itm} -pin  "FRAME:for:not#6" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#6.itm}
+load inst "FRAME:for:nand#3" "nand(2,1)" "INTERFACE" -attr xrf 40114 -attr oid 601 -attr @path {/sobel/sobel:core/FRAME:for:nand#3} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {FRAME:for:not#6.itm} -pin  "FRAME:for:nand#3" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#6.itm}
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand#3" {A1(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#6.itm}
+load net {FRAME:for:nand#3.itm} -pin  "FRAME:for:nand#3" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#3.itm}
+load inst "FRAME:for:or#4" "or(2,1)" "INTERFACE" -attr xrf 40115 -attr oid 602 -attr @path {/sobel/sobel:core/FRAME:for:or#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {FRAME:for:nand#3.itm} -pin  "FRAME:for:or#4" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#3.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or#4" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:or#4.itm} -pin  "FRAME:for:or#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#4.itm}
+load inst "FRAME:for:not#4" "not(1)" "INTERFACE" -attr xrf 40116 -attr oid 603 -attr @path {/sobel/sobel:core/FRAME:for:not#4} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {i#6.lpi#1.dfm(1)} -pin  "FRAME:for:not#4" {A(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#4.itm}
+load net {FRAME:for:not#4.itm} -pin  "FRAME:for:not#4" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#4.itm}
+load inst "FRAME:for:nand#2" "nand(2,1)" "INTERFACE" -attr xrf 40117 -attr oid 604 -attr @path {/sobel/sobel:core/FRAME:for:nand#2} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nand(1,2)"
+load net {i#6.lpi#1.dfm(0)} -pin  "FRAME:for:nand#2" {A0(0)} -attr @path {/sobel/sobel:core/slc(i#6.lpi#1.dfm)#7.itm}
+load net {FRAME:for:not#4.itm} -pin  "FRAME:for:nand#2" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:not#4.itm}
+load net {FRAME:for:nand#2.itm} -pin  "FRAME:for:nand#2" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#2.itm}
+load inst "FRAME:for:or" "or(2,1)" "INTERFACE" -attr xrf 40118 -attr oid 605 -attr @path {/sobel/sobel:core/FRAME:for:or} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {FRAME:for:nand#2.itm} -pin  "FRAME:for:or" {A0(0)} -attr @path {/sobel/sobel:core/FRAME:for:nand#2.itm}
+load net {FRAME:for:nor.cse} -pin  "FRAME:for:or" {A1(0)} -attr @path {/sobel/sobel:core/FRAME:for:nor.cse}
+load net {FRAME:for:or.itm} -pin  "FRAME:for:or" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or.itm}
+load inst "FRAME:for:or#5" "or(3,1)" "INTERFACE" -attr xrf 40119 -attr oid 606 -attr @path {/sobel/sobel:core/FRAME:for:or#5} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,3)"
+load net {FRAME:for:acc#5.tmp(1)} -pin  "FRAME:for:or#5" {A0(0)} -attr @path {/sobel/sobel:core/slc(FRAME:for:acc#5.tmp)#2.itm}
+load net {FRAME:for:acc#5.tmp(0)} -pin  "FRAME:for:or#5" {A1(0)} -attr @path {/sobel/sobel:core/slc(FRAME:for:acc#5.tmp)#3.itm}
+load net {FRAME:for:and#18.seb} -pin  "FRAME:for:or#5" {A2(0)} -attr @path {/sobel/sobel:core/FRAME:for:and#18.seb}
+load net {FRAME:for:or#5.itm} -pin  "FRAME:for:or#5" {Z(0)} -attr @path {/sobel/sobel:core/FRAME:for:or#5.itm}
+load inst "nor" "nor(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/nor} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_nor(1,2)"
+load net {exit:FRAME#1.sva} -pin  "nor" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {exit:FRAME:for#1.lpi#1.dfm#4} -pin  "nor" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4}
+load net {and.dcpl#1} -pin  "nor" {Z(0)} -attr @path {/sobel/sobel:core/and.dcpl#1}
+load inst "or#3" "or(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/or#3} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {exit:FRAME#1.sva} -pin  "or#3" {A0(0)} -attr @path {/sobel/sobel:core/exit:FRAME#1.sva}
+load net {exit:FRAME:for#1.lpi#1.dfm#4} -pin  "or#3" {A1(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for#1.lpi#1.dfm#4}
+load net {or.dcpl#2} -pin  "or#3" {Z(0)} -attr @path {/sobel/sobel:core/or.dcpl#2}
+load inst "not#35" "not(1)" "INTERFACE" -attr @path {/sobel/sobel:core/not#35} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1} -pin  "not#35" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1}
+load net {not#35.itm} -pin  "not#35" {Z(0)} -attr @path {/sobel/sobel:core/not#35.itm}
+load inst "or#4" "or(2,1)" "INTERFACE" -attr @path {/sobel/sobel:core/or#4} -attr area 0.730832 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,2)"
+load net {or.dcpl#2} -pin  "or#4" {A0(0)} -attr @path {/sobel/sobel:core/or.dcpl#2}
+load net {not#35.itm} -pin  "or#4" {A1(0)} -attr @path {/sobel/sobel:core/not#35.itm}
+load net {or#4.cse} -pin  "or#4" {Z(0)} -attr @path {/sobel/sobel:core/or#4.cse}
+load inst "not#31" "not(1)" "INTERFACE" -attr @path {/sobel/sobel:core/not#31} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:FRAME:for.lpi#1} -pin  "not#31" {A(0)} -attr @path {/sobel/sobel:core/exit:FRAME:for.lpi#1}
+load net {not#31.itm} -pin  "not#31" {Z(0)} -attr @path {/sobel/sobel:core/not#31.itm}
+load inst "or#9" "or(3,1)" "INTERFACE" -attr @path {/sobel/sobel:core/or#9} -attr area 1.055476 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_or(1,3)"
+load net {or.dcpl#2} -pin  "or#9" {A0(0)} -attr @path {/sobel/sobel:core/or.dcpl#2}
+load net {not#31.itm} -pin  "or#9" {A1(0)} -attr @path {/sobel/sobel:core/not#31.itm}
+load net {FRAME:for#1:acc.itm(1)} -pin  "or#9" {A2(0)} -attr @path {/sobel/sobel:core/FRAME:for#1:slc#3.itm}
+load net {or#9.cse} -pin  "or#9" {Z(0)} -attr @path {/sobel/sobel:core/or#9.cse}
+load inst "FRAME:for:acc" "add(2,-1,1,0,2)" "INTERFACE" -attr xrf 40120 -attr oid 607 -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc} -attr area 3.315520 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2)"
+load net {i#6.sva#1(0)} -pin  "FRAME:for:acc" {A(0)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {i#6.sva#1(1)} -pin  "FRAME:for:acc" {A(1)} -attr vt d -attr @path {/sobel/sobel:core/i#6.sva#1}
+load net {PWR} -pin  "FRAME:for:acc" {B(0)} -attr @path {/sobel/sobel:core/C1_1#1}
+load net {FRAME:for:acc.itm(0)} -pin  "FRAME:for:acc" {Z(0)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+load net {FRAME:for:acc.itm(1)} -pin  "FRAME:for:acc" {Z(1)} -attr vt d -attr @path {/sobel/sobel:core/FRAME:for:acc.itm}
+### END MODULE 
+
+module new "sobel" "orig"
+load portBus {vin:rsc.z(89:0)} input 90 {vin:rsc.z(89)} {vin:rsc.z(88)} {vin:rsc.z(87)} {vin:rsc.z(86)} {vin:rsc.z(85)} {vin:rsc.z(84)} {vin:rsc.z(83)} {vin:rsc.z(82)} {vin:rsc.z(81)} {vin:rsc.z(80)} {vin:rsc.z(79)} {vin:rsc.z(78)} {vin:rsc.z(77)} {vin:rsc.z(76)} {vin:rsc.z(75)} {vin:rsc.z(74)} {vin:rsc.z(73)} {vin:rsc.z(72)} {vin:rsc.z(71)} {vin:rsc.z(70)} {vin:rsc.z(69)} {vin:rsc.z(68)} {vin:rsc.z(67)} {vin:rsc.z(66)} {vin:rsc.z(65)} {vin:rsc.z(64)} {vin:rsc.z(63)} {vin:rsc.z(62)} {vin:rsc.z(61)} {vin:rsc.z(60)} {vin:rsc.z(59)} {vin:rsc.z(58)} {vin:rsc.z(57)} {vin:rsc.z(56)} {vin:rsc.z(55)} {vin:rsc.z(54)} {vin:rsc.z(53)} {vin:rsc.z(52)} {vin:rsc.z(51)} {vin:rsc.z(50)} {vin:rsc.z(49)} {vin:rsc.z(48)} {vin:rsc.z(47)} {vin:rsc.z(46)} {vin:rsc.z(45)} {vin:rsc.z(44)} {vin:rsc.z(43)} {vin:rsc.z(42)} {vin:rsc.z(41)} {vin:rsc.z(40)} {vin:rsc.z(39)} {vin:rsc.z(38)} {vin:rsc.z(37)} {vin:rsc.z(36)} {vin:rsc.z(35)} {vin:rsc.z(34)} {vin:rsc.z(33)} {vin:rsc.z(32)} {vin:rsc.z(31)} {vin:rsc.z(30)} {vin:rsc.z(29)} {vin:rsc.z(28)} {vin:rsc.z(27)} {vin:rsc.z(26)} {vin:rsc.z(25)} {vin:rsc.z(24)} {vin:rsc.z(23)} {vin:rsc.z(22)} {vin:rsc.z(21)} {vin:rsc.z(20)} {vin:rsc.z(19)} {vin:rsc.z(18)} {vin:rsc.z(17)} {vin:rsc.z(16)} {vin:rsc.z(15)} {vin:rsc.z(14)} {vin:rsc.z(13)} {vin:rsc.z(12)} {vin:rsc.z(11)} {vin:rsc.z(10)} {vin:rsc.z(9)} {vin:rsc.z(8)} {vin:rsc.z(7)} {vin:rsc.z(6)} {vin:rsc.z(5)} {vin:rsc.z(4)} {vin:rsc.z(3)} {vin:rsc.z(2)} {vin:rsc.z(1)} {vin:rsc.z(0)} -attr xrf 40121 -attr oid 608 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load portBus {vout:rsc.z(29:0)} output 30 {vout:rsc.z(29)} {vout:rsc.z(28)} {vout:rsc.z(27)} {vout:rsc.z(26)} {vout:rsc.z(25)} {vout:rsc.z(24)} {vout:rsc.z(23)} {vout:rsc.z(22)} {vout:rsc.z(21)} {vout:rsc.z(20)} {vout:rsc.z(19)} {vout:rsc.z(18)} {vout:rsc.z(17)} {vout:rsc.z(16)} {vout:rsc.z(15)} {vout:rsc.z(14)} {vout:rsc.z(13)} {vout:rsc.z(12)} {vout:rsc.z(11)} {vout:rsc.z(10)} {vout:rsc.z(9)} {vout:rsc.z(8)} {vout:rsc.z(7)} {vout:rsc.z(6)} {vout:rsc.z(5)} {vout:rsc.z(4)} {vout:rsc.z(3)} {vout:rsc.z(2)} {vout:rsc.z(1)} {vout:rsc.z(0)} -attr xrf 40122 -attr oid 609 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load port {clk} input -attr xrf 40123 -attr oid 610 -attr vt d -attr @path {/sobel/clk}
+load port {en} input -attr xrf 40124 -attr oid 611 -attr vt d -attr @path {/sobel/en}
+load port {arst_n} input -attr xrf 40125 -attr oid 612 -attr vt d -attr @path {/sobel/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(89:0)} output 90 {d(89)} {d(88)} {d(87)} {d(86)} {d(85)} {d(84)} {d(83)} {d(82)} {d(81)} {d(80)} {d(79)} {d(78)} {d(77)} {d(76)} {d(75)} {d(74)} {d(73)} {d(72)} {d(71)} {d(70)} {d(69)} {d(68)} {d(67)} {d(66)} {d(65)} {d(64)} {d(63)} {d(62)} {d(61)} {d(60)} {d(59)} {d(58)} {d(57)} {d(56)} {d(55)} {d(54)} {d(53)} {d(52)} {d(51)} {d(50)} {d(49)} {d(48)} {d(47)} {d(46)} {d(45)} {d(44)} {d(43)} {d(42)} {d(41)} {d(40)} {d(39)} {d(38)} {d(37)} {d(36)} {d(35)} {d(34)} {d(33)} {d(32)} {d(31)} {d(30)} {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(89:0)} input 90 {z(89)} {z(88)} {z(87)} {z(86)} {z(85)} {z(84)} {z(83)} {z(82)} {z(81)} {z(80)} {z(79)} {z(78)} {z(77)} {z(76)} {z(75)} {z(74)} {z(73)} {z(72)} {z(71)} {z(70)} {z(69)} {z(68)} {z(67)} {z(66)} {z(65)} {z(64)} {z(63)} {z(62)} {z(61)} {z(60)} {z(59)} {z(58)} {z(57)} {z(56)} {z(55)} {z(54)} {z(53)} {z(52)} {z(51)} {z(50)} {z(49)} {z(48)} {z(47)} {z(46)} {z(45)} {z(44)} {z(43)} {z(42)} {z(41)} {z(40)} {z(39)} {z(38)} {z(37)} {z(36)} {z(35)} {z(34)} {z(33)} {z(32)} {z(31)} {z(30)} {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(29:0)} input 30 {d(29)} {d(28)} {d(27)} {d(26)} {d(25)} {d(24)} {d(23)} {d(22)} {d(21)} {d(20)} {d(19)} {d(18)} {d(17)} {d(16)} {d(15)} {d(14)} {d(13)} {d(12)} {d(11)} {d(10)} {d(9)} {d(8)} {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(29:0)} output 30 {z(29)} {z(28)} {z(27)} {z(26)} {z(25)} {z(24)} {z(23)} {z(22)} {z(21)} {z(20)} {z(19)} {z(18)} {z(17)} {z(16)} {z(15)} {z(14)} {z(13)} {z(12)} {z(11)} {z(10)} {z(9)} {z(8)} {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "sobel:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {vin:rsc:mgc_in_wire.d(89:0)} input 90 {vin:rsc:mgc_in_wire.d(89)} {vin:rsc:mgc_in_wire.d(88)} {vin:rsc:mgc_in_wire.d(87)} {vin:rsc:mgc_in_wire.d(86)} {vin:rsc:mgc_in_wire.d(85)} {vin:rsc:mgc_in_wire.d(84)} {vin:rsc:mgc_in_wire.d(83)} {vin:rsc:mgc_in_wire.d(82)} {vin:rsc:mgc_in_wire.d(81)} {vin:rsc:mgc_in_wire.d(80)} {vin:rsc:mgc_in_wire.d(79)} {vin:rsc:mgc_in_wire.d(78)} {vin:rsc:mgc_in_wire.d(77)} {vin:rsc:mgc_in_wire.d(76)} {vin:rsc:mgc_in_wire.d(75)} {vin:rsc:mgc_in_wire.d(74)} {vin:rsc:mgc_in_wire.d(73)} {vin:rsc:mgc_in_wire.d(72)} {vin:rsc:mgc_in_wire.d(71)} {vin:rsc:mgc_in_wire.d(70)} {vin:rsc:mgc_in_wire.d(69)} {vin:rsc:mgc_in_wire.d(68)} {vin:rsc:mgc_in_wire.d(67)} {vin:rsc:mgc_in_wire.d(66)} {vin:rsc:mgc_in_wire.d(65)} {vin:rsc:mgc_in_wire.d(64)} {vin:rsc:mgc_in_wire.d(63)} {vin:rsc:mgc_in_wire.d(62)} {vin:rsc:mgc_in_wire.d(61)} {vin:rsc:mgc_in_wire.d(60)} {vin:rsc:mgc_in_wire.d(59)} {vin:rsc:mgc_in_wire.d(58)} {vin:rsc:mgc_in_wire.d(57)} {vin:rsc:mgc_in_wire.d(56)} {vin:rsc:mgc_in_wire.d(55)} {vin:rsc:mgc_in_wire.d(54)} {vin:rsc:mgc_in_wire.d(53)} {vin:rsc:mgc_in_wire.d(52)} {vin:rsc:mgc_in_wire.d(51)} {vin:rsc:mgc_in_wire.d(50)} {vin:rsc:mgc_in_wire.d(49)} {vin:rsc:mgc_in_wire.d(48)} {vin:rsc:mgc_in_wire.d(47)} {vin:rsc:mgc_in_wire.d(46)} {vin:rsc:mgc_in_wire.d(45)} {vin:rsc:mgc_in_wire.d(44)} {vin:rsc:mgc_in_wire.d(43)} {vin:rsc:mgc_in_wire.d(42)} {vin:rsc:mgc_in_wire.d(41)} {vin:rsc:mgc_in_wire.d(40)} {vin:rsc:mgc_in_wire.d(39)} {vin:rsc:mgc_in_wire.d(38)} {vin:rsc:mgc_in_wire.d(37)} {vin:rsc:mgc_in_wire.d(36)} {vin:rsc:mgc_in_wire.d(35)} {vin:rsc:mgc_in_wire.d(34)} {vin:rsc:mgc_in_wire.d(33)} {vin:rsc:mgc_in_wire.d(32)} {vin:rsc:mgc_in_wire.d(31)} {vin:rsc:mgc_in_wire.d(30)} {vin:rsc:mgc_in_wire.d(29)} {vin:rsc:mgc_in_wire.d(28)} {vin:rsc:mgc_in_wire.d(27)} {vin:rsc:mgc_in_wire.d(26)} {vin:rsc:mgc_in_wire.d(25)} {vin:rsc:mgc_in_wire.d(24)} {vin:rsc:mgc_in_wire.d(23)} {vin:rsc:mgc_in_wire.d(22)} {vin:rsc:mgc_in_wire.d(21)} {vin:rsc:mgc_in_wire.d(20)} {vin:rsc:mgc_in_wire.d(19)} {vin:rsc:mgc_in_wire.d(18)} {vin:rsc:mgc_in_wire.d(17)} {vin:rsc:mgc_in_wire.d(16)} {vin:rsc:mgc_in_wire.d(15)} {vin:rsc:mgc_in_wire.d(14)} {vin:rsc:mgc_in_wire.d(13)} {vin:rsc:mgc_in_wire.d(12)} {vin:rsc:mgc_in_wire.d(11)} {vin:rsc:mgc_in_wire.d(10)} {vin:rsc:mgc_in_wire.d(9)} {vin:rsc:mgc_in_wire.d(8)} {vin:rsc:mgc_in_wire.d(7)} {vin:rsc:mgc_in_wire.d(6)} {vin:rsc:mgc_in_wire.d(5)} {vin:rsc:mgc_in_wire.d(4)} {vin:rsc:mgc_in_wire.d(3)} {vin:rsc:mgc_in_wire.d(2)} {vin:rsc:mgc_in_wire.d(1)} {vin:rsc:mgc_in_wire.d(0)} \
+     portBus {vout:rsc:mgc_out_stdreg.d(29:0)} output 30 {vout:rsc:mgc_out_stdreg.d(29)} {vout:rsc:mgc_out_stdreg.d(28)} {vout:rsc:mgc_out_stdreg.d(27)} {vout:rsc:mgc_out_stdreg.d(26)} {vout:rsc:mgc_out_stdreg.d(25)} {vout:rsc:mgc_out_stdreg.d(24)} {vout:rsc:mgc_out_stdreg.d(23)} {vout:rsc:mgc_out_stdreg.d(22)} {vout:rsc:mgc_out_stdreg.d(21)} {vout:rsc:mgc_out_stdreg.d(20)} {vout:rsc:mgc_out_stdreg.d(19)} {vout:rsc:mgc_out_stdreg.d(18)} {vout:rsc:mgc_out_stdreg.d(17)} {vout:rsc:mgc_out_stdreg.d(16)} {vout:rsc:mgc_out_stdreg.d(15)} {vout:rsc:mgc_out_stdreg.d(14)} {vout:rsc:mgc_out_stdreg.d(13)} {vout:rsc:mgc_out_stdreg.d(12)} {vout:rsc:mgc_out_stdreg.d(11)} {vout:rsc:mgc_out_stdreg.d(10)} {vout:rsc:mgc_out_stdreg.d(9)} {vout:rsc:mgc_out_stdreg.d(8)} {vout:rsc:mgc_out_stdreg.d(7)} {vout:rsc:mgc_out_stdreg.d(6)} {vout:rsc:mgc_out_stdreg.d(5)} {vout:rsc:mgc_out_stdreg.d(4)} {vout:rsc:mgc_out_stdreg.d(3)} {vout:rsc:mgc_out_stdreg.d(2)} {vout:rsc:mgc_out_stdreg.d(1)} {vout:rsc:mgc_out_stdreg.d(0)} \
+
+load net {vin:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(8)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(9)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(10)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(11)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(12)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(13)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(14)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(15)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(16)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(17)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(18)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(19)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(20)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(21)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(22)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(23)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(24)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(25)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(26)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(27)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(28)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(29)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(30)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(31)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(32)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(33)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(34)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(35)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(36)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(37)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(38)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(39)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(40)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(41)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(42)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(43)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(44)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(45)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(46)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(47)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(48)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(49)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(50)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(51)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(52)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(53)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(54)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(55)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(56)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(57)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(58)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(59)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(60)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(61)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(62)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(63)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(64)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(65)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(66)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(67)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(68)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(69)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(70)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(71)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(72)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(73)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(74)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(75)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(76)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(77)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(78)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(79)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(80)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(81)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(82)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(83)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(84)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(85)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(86)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(87)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(88)} -attr vt d
+load net {vin:rsc:mgc_in_wire.d#1(89)} -attr vt d
+load netBundle {vin:rsc:mgc_in_wire.d#1} 90 {vin:rsc:mgc_in_wire.d#1(0)} {vin:rsc:mgc_in_wire.d#1(1)} {vin:rsc:mgc_in_wire.d#1(2)} {vin:rsc:mgc_in_wire.d#1(3)} {vin:rsc:mgc_in_wire.d#1(4)} {vin:rsc:mgc_in_wire.d#1(5)} {vin:rsc:mgc_in_wire.d#1(6)} {vin:rsc:mgc_in_wire.d#1(7)} {vin:rsc:mgc_in_wire.d#1(8)} {vin:rsc:mgc_in_wire.d#1(9)} {vin:rsc:mgc_in_wire.d#1(10)} {vin:rsc:mgc_in_wire.d#1(11)} {vin:rsc:mgc_in_wire.d#1(12)} {vin:rsc:mgc_in_wire.d#1(13)} {vin:rsc:mgc_in_wire.d#1(14)} {vin:rsc:mgc_in_wire.d#1(15)} {vin:rsc:mgc_in_wire.d#1(16)} {vin:rsc:mgc_in_wire.d#1(17)} {vin:rsc:mgc_in_wire.d#1(18)} {vin:rsc:mgc_in_wire.d#1(19)} {vin:rsc:mgc_in_wire.d#1(20)} {vin:rsc:mgc_in_wire.d#1(21)} {vin:rsc:mgc_in_wire.d#1(22)} {vin:rsc:mgc_in_wire.d#1(23)} {vin:rsc:mgc_in_wire.d#1(24)} {vin:rsc:mgc_in_wire.d#1(25)} {vin:rsc:mgc_in_wire.d#1(26)} {vin:rsc:mgc_in_wire.d#1(27)} {vin:rsc:mgc_in_wire.d#1(28)} {vin:rsc:mgc_in_wire.d#1(29)} {vin:rsc:mgc_in_wire.d#1(30)} {vin:rsc:mgc_in_wire.d#1(31)} {vin:rsc:mgc_in_wire.d#1(32)} {vin:rsc:mgc_in_wire.d#1(33)} {vin:rsc:mgc_in_wire.d#1(34)} {vin:rsc:mgc_in_wire.d#1(35)} {vin:rsc:mgc_in_wire.d#1(36)} {vin:rsc:mgc_in_wire.d#1(37)} {vin:rsc:mgc_in_wire.d#1(38)} {vin:rsc:mgc_in_wire.d#1(39)} {vin:rsc:mgc_in_wire.d#1(40)} {vin:rsc:mgc_in_wire.d#1(41)} {vin:rsc:mgc_in_wire.d#1(42)} {vin:rsc:mgc_in_wire.d#1(43)} {vin:rsc:mgc_in_wire.d#1(44)} {vin:rsc:mgc_in_wire.d#1(45)} {vin:rsc:mgc_in_wire.d#1(46)} {vin:rsc:mgc_in_wire.d#1(47)} {vin:rsc:mgc_in_wire.d#1(48)} {vin:rsc:mgc_in_wire.d#1(49)} {vin:rsc:mgc_in_wire.d#1(50)} {vin:rsc:mgc_in_wire.d#1(51)} {vin:rsc:mgc_in_wire.d#1(52)} {vin:rsc:mgc_in_wire.d#1(53)} {vin:rsc:mgc_in_wire.d#1(54)} {vin:rsc:mgc_in_wire.d#1(55)} {vin:rsc:mgc_in_wire.d#1(56)} {vin:rsc:mgc_in_wire.d#1(57)} {vin:rsc:mgc_in_wire.d#1(58)} {vin:rsc:mgc_in_wire.d#1(59)} {vin:rsc:mgc_in_wire.d#1(60)} {vin:rsc:mgc_in_wire.d#1(61)} {vin:rsc:mgc_in_wire.d#1(62)} {vin:rsc:mgc_in_wire.d#1(63)} {vin:rsc:mgc_in_wire.d#1(64)} {vin:rsc:mgc_in_wire.d#1(65)} {vin:rsc:mgc_in_wire.d#1(66)} {vin:rsc:mgc_in_wire.d#1(67)} {vin:rsc:mgc_in_wire.d#1(68)} {vin:rsc:mgc_in_wire.d#1(69)} {vin:rsc:mgc_in_wire.d#1(70)} {vin:rsc:mgc_in_wire.d#1(71)} {vin:rsc:mgc_in_wire.d#1(72)} {vin:rsc:mgc_in_wire.d#1(73)} {vin:rsc:mgc_in_wire.d#1(74)} {vin:rsc:mgc_in_wire.d#1(75)} {vin:rsc:mgc_in_wire.d#1(76)} {vin:rsc:mgc_in_wire.d#1(77)} {vin:rsc:mgc_in_wire.d#1(78)} {vin:rsc:mgc_in_wire.d#1(79)} {vin:rsc:mgc_in_wire.d#1(80)} {vin:rsc:mgc_in_wire.d#1(81)} {vin:rsc:mgc_in_wire.d#1(82)} {vin:rsc:mgc_in_wire.d#1(83)} {vin:rsc:mgc_in_wire.d#1(84)} {vin:rsc:mgc_in_wire.d#1(85)} {vin:rsc:mgc_in_wire.d#1(86)} {vin:rsc:mgc_in_wire.d#1(87)} {vin:rsc:mgc_in_wire.d#1(88)} {vin:rsc:mgc_in_wire.d#1(89)} -attr xrf 40126 -attr oid 613 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -attr vt d
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+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -attr vt d
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+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -attr vt d
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+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -attr vt d
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -attr vt d
+load netBundle {vout:rsc:mgc_out_stdreg.d#1} 30 {vout:rsc:mgc_out_stdreg.d#1(0)} {vout:rsc:mgc_out_stdreg.d#1(1)} {vout:rsc:mgc_out_stdreg.d#1(2)} {vout:rsc:mgc_out_stdreg.d#1(3)} {vout:rsc:mgc_out_stdreg.d#1(4)} {vout:rsc:mgc_out_stdreg.d#1(5)} {vout:rsc:mgc_out_stdreg.d#1(6)} {vout:rsc:mgc_out_stdreg.d#1(7)} {vout:rsc:mgc_out_stdreg.d#1(8)} {vout:rsc:mgc_out_stdreg.d#1(9)} {vout:rsc:mgc_out_stdreg.d#1(10)} {vout:rsc:mgc_out_stdreg.d#1(11)} {vout:rsc:mgc_out_stdreg.d#1(12)} {vout:rsc:mgc_out_stdreg.d#1(13)} {vout:rsc:mgc_out_stdreg.d#1(14)} {vout:rsc:mgc_out_stdreg.d#1(15)} {vout:rsc:mgc_out_stdreg.d#1(16)} {vout:rsc:mgc_out_stdreg.d#1(17)} {vout:rsc:mgc_out_stdreg.d#1(18)} {vout:rsc:mgc_out_stdreg.d#1(19)} {vout:rsc:mgc_out_stdreg.d#1(20)} {vout:rsc:mgc_out_stdreg.d#1(21)} {vout:rsc:mgc_out_stdreg.d#1(22)} {vout:rsc:mgc_out_stdreg.d#1(23)} {vout:rsc:mgc_out_stdreg.d#1(24)} {vout:rsc:mgc_out_stdreg.d#1(25)} {vout:rsc:mgc_out_stdreg.d#1(26)} {vout:rsc:mgc_out_stdreg.d#1(27)} {vout:rsc:mgc_out_stdreg.d#1(28)} {vout:rsc:mgc_out_stdreg.d#1(29)} -attr xrf 40127 -attr oid 614 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vin:rsc.z(0)} -attr vt d
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+load net {vin:rsc.z(89)} -attr vt d
+load netBundle {vin:rsc.z} 90 {vin:rsc.z(0)} {vin:rsc.z(1)} {vin:rsc.z(2)} {vin:rsc.z(3)} {vin:rsc.z(4)} {vin:rsc.z(5)} {vin:rsc.z(6)} {vin:rsc.z(7)} {vin:rsc.z(8)} {vin:rsc.z(9)} {vin:rsc.z(10)} {vin:rsc.z(11)} {vin:rsc.z(12)} {vin:rsc.z(13)} {vin:rsc.z(14)} {vin:rsc.z(15)} {vin:rsc.z(16)} {vin:rsc.z(17)} {vin:rsc.z(18)} {vin:rsc.z(19)} {vin:rsc.z(20)} {vin:rsc.z(21)} {vin:rsc.z(22)} {vin:rsc.z(23)} {vin:rsc.z(24)} {vin:rsc.z(25)} {vin:rsc.z(26)} {vin:rsc.z(27)} {vin:rsc.z(28)} {vin:rsc.z(29)} {vin:rsc.z(30)} {vin:rsc.z(31)} {vin:rsc.z(32)} {vin:rsc.z(33)} {vin:rsc.z(34)} {vin:rsc.z(35)} {vin:rsc.z(36)} {vin:rsc.z(37)} {vin:rsc.z(38)} {vin:rsc.z(39)} {vin:rsc.z(40)} {vin:rsc.z(41)} {vin:rsc.z(42)} {vin:rsc.z(43)} {vin:rsc.z(44)} {vin:rsc.z(45)} {vin:rsc.z(46)} {vin:rsc.z(47)} {vin:rsc.z(48)} {vin:rsc.z(49)} {vin:rsc.z(50)} {vin:rsc.z(51)} {vin:rsc.z(52)} {vin:rsc.z(53)} {vin:rsc.z(54)} {vin:rsc.z(55)} {vin:rsc.z(56)} {vin:rsc.z(57)} {vin:rsc.z(58)} {vin:rsc.z(59)} {vin:rsc.z(60)} {vin:rsc.z(61)} {vin:rsc.z(62)} {vin:rsc.z(63)} {vin:rsc.z(64)} {vin:rsc.z(65)} {vin:rsc.z(66)} {vin:rsc.z(67)} {vin:rsc.z(68)} {vin:rsc.z(69)} {vin:rsc.z(70)} {vin:rsc.z(71)} {vin:rsc.z(72)} {vin:rsc.z(73)} {vin:rsc.z(74)} {vin:rsc.z(75)} {vin:rsc.z(76)} {vin:rsc.z(77)} {vin:rsc.z(78)} {vin:rsc.z(79)} {vin:rsc.z(80)} {vin:rsc.z(81)} {vin:rsc.z(82)} {vin:rsc.z(83)} {vin:rsc.z(84)} {vin:rsc.z(85)} {vin:rsc.z(86)} {vin:rsc.z(87)} {vin:rsc.z(88)} {vin:rsc.z(89)} -attr xrf 40128 -attr oid 615 -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(0)} -port {vin:rsc.z(0)} -attr vt d
+load net {vin:rsc.z(1)} -port {vin:rsc.z(1)} -attr vt d
+load net {vin:rsc.z(2)} -port {vin:rsc.z(2)} -attr vt d
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+load net {vout:rsc.z(0)} -attr vt d
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+load net {vout:rsc.z(6)} -attr vt d
+load net {vout:rsc.z(7)} -attr vt d
+load net {vout:rsc.z(8)} -attr vt d
+load net {vout:rsc.z(9)} -attr vt d
+load net {vout:rsc.z(10)} -attr vt d
+load net {vout:rsc.z(11)} -attr vt d
+load net {vout:rsc.z(12)} -attr vt d
+load net {vout:rsc.z(13)} -attr vt d
+load net {vout:rsc.z(14)} -attr vt d
+load net {vout:rsc.z(15)} -attr vt d
+load net {vout:rsc.z(16)} -attr vt d
+load net {vout:rsc.z(17)} -attr vt d
+load net {vout:rsc.z(18)} -attr vt d
+load net {vout:rsc.z(19)} -attr vt d
+load net {vout:rsc.z(20)} -attr vt d
+load net {vout:rsc.z(21)} -attr vt d
+load net {vout:rsc.z(22)} -attr vt d
+load net {vout:rsc.z(23)} -attr vt d
+load net {vout:rsc.z(24)} -attr vt d
+load net {vout:rsc.z(25)} -attr vt d
+load net {vout:rsc.z(26)} -attr vt d
+load net {vout:rsc.z(27)} -attr vt d
+load net {vout:rsc.z(28)} -attr vt d
+load net {vout:rsc.z(29)} -attr vt d
+load netBundle {vout:rsc.z} 30 {vout:rsc.z(0)} {vout:rsc.z(1)} {vout:rsc.z(2)} {vout:rsc.z(3)} {vout:rsc.z(4)} {vout:rsc.z(5)} {vout:rsc.z(6)} {vout:rsc.z(7)} {vout:rsc.z(8)} {vout:rsc.z(9)} {vout:rsc.z(10)} {vout:rsc.z(11)} {vout:rsc.z(12)} {vout:rsc.z(13)} {vout:rsc.z(14)} {vout:rsc.z(15)} {vout:rsc.z(16)} {vout:rsc.z(17)} {vout:rsc.z(18)} {vout:rsc.z(19)} {vout:rsc.z(20)} {vout:rsc.z(21)} {vout:rsc.z(22)} {vout:rsc.z(23)} {vout:rsc.z(24)} {vout:rsc.z(25)} {vout:rsc.z(26)} {vout:rsc.z(27)} {vout:rsc.z(28)} {vout:rsc.z(29)} -attr xrf 40130 -attr oid 617 -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(0)} -port {vout:rsc.z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -port {vout:rsc.z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -port {vout:rsc.z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -port {vout:rsc.z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -port {vout:rsc.z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -port {vout:rsc.z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -port {vout:rsc.z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -port {vout:rsc.z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -port {vout:rsc.z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -port {vout:rsc.z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -port {vout:rsc.z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -port {vout:rsc.z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -port {vout:rsc.z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -port {vout:rsc.z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -port {vout:rsc.z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -port {vout:rsc.z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -port {vout:rsc.z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -port {vout:rsc.z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -port {vout:rsc.z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -port {vout:rsc.z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -port {vout:rsc.z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -port {vout:rsc.z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -port {vout:rsc.z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -port {vout:rsc.z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -port {vout:rsc.z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -port {vout:rsc.z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -port {vout:rsc.z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -port {vout:rsc.z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -port {vout:rsc.z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -port {vout:rsc.z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {clk} -attr xrf 40131 -attr oid 618
+load net {clk} -port {clk} -attr xrf 40132 -attr oid 619
+load net {en} -attr xrf 40133 -attr oid 620
+load net {en} -port {en} -attr xrf 40134 -attr oid 621
+load net {arst_n} -attr xrf 40135 -attr oid 622
+load net {arst_n} -port {arst_n} -attr xrf 40136 -attr oid 623
+load inst "sobel:core:inst" "sobel:core" "orig" -attr xrf 40137 -attr oid 624 -attr vt dc -attr @path {/sobel/sobel:core:inst} -attr area 8527.523639 -attr delay 15.158629 -attr hier "/sobel/sobel:core" -pg 1 -lvl 3
+load net {clk} -pin  "sobel:core:inst" {clk#1} -attr xrf 40138 -attr oid 625 -attr @path {/sobel/clk}
+load net {en} -pin  "sobel:core:inst" {en#1} -attr xrf 40139 -attr oid 626 -attr @path {/sobel/en}
+load net {arst_n} -pin  "sobel:core:inst" {arst_n#1} -attr xrf 40140 -attr oid 627 -attr @path {/sobel/arst_n}
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(8)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(9)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(10)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(11)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(12)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(13)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(14)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(15)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(16)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(17)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(18)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(19)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(20)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(21)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(22)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(23)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(24)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(25)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(26)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(27)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(28)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(29)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(30)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(31)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(32)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(33)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(34)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(35)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(36)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(37)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(38)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(39)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(40)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(41)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(42)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(43)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(44)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(45)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(46)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(47)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(48)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(49)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(50)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(51)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(52)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(53)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(54)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(55)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(56)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(57)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(58)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(59)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(60)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(61)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(62)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(63)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(64)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(65)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(66)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(67)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(68)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(69)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(70)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(71)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(72)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(73)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(74)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(75)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(76)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(77)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(78)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(79)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(80)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(81)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(82)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(83)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(84)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(85)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(86)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(87)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(88)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "sobel:core:inst" {vin:rsc:mgc_in_wire.d(89)} -attr vt dc -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(8)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(9)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(10)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(11)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(12)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(13)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(14)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(15)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(16)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(17)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(18)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(19)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(20)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(21)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(22)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(23)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(24)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(25)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(26)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(27)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(28)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "sobel:core:inst" {vout:rsc:mgc_out_stdreg.d(29)} -attr vt dc -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load inst "vin:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,90)" "INTERFACE" -attr xrf 40141 -attr oid 628 -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,90)" -pg 1 -lvl 1
+load net {vin:rsc:mgc_in_wire.d#1(0)} -pin  "vin:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(1)} -pin  "vin:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(2)} -pin  "vin:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(3)} -pin  "vin:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(4)} -pin  "vin:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(5)} -pin  "vin:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(6)} -pin  "vin:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(7)} -pin  "vin:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(8)} -pin  "vin:rsc:mgc_in_wire" {d(8)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(9)} -pin  "vin:rsc:mgc_in_wire" {d(9)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(10)} -pin  "vin:rsc:mgc_in_wire" {d(10)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(11)} -pin  "vin:rsc:mgc_in_wire" {d(11)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(12)} -pin  "vin:rsc:mgc_in_wire" {d(12)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(13)} -pin  "vin:rsc:mgc_in_wire" {d(13)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(14)} -pin  "vin:rsc:mgc_in_wire" {d(14)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(15)} -pin  "vin:rsc:mgc_in_wire" {d(15)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(16)} -pin  "vin:rsc:mgc_in_wire" {d(16)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(17)} -pin  "vin:rsc:mgc_in_wire" {d(17)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(18)} -pin  "vin:rsc:mgc_in_wire" {d(18)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(19)} -pin  "vin:rsc:mgc_in_wire" {d(19)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(20)} -pin  "vin:rsc:mgc_in_wire" {d(20)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(21)} -pin  "vin:rsc:mgc_in_wire" {d(21)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(22)} -pin  "vin:rsc:mgc_in_wire" {d(22)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(23)} -pin  "vin:rsc:mgc_in_wire" {d(23)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(24)} -pin  "vin:rsc:mgc_in_wire" {d(24)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(25)} -pin  "vin:rsc:mgc_in_wire" {d(25)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(26)} -pin  "vin:rsc:mgc_in_wire" {d(26)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(27)} -pin  "vin:rsc:mgc_in_wire" {d(27)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(28)} -pin  "vin:rsc:mgc_in_wire" {d(28)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(29)} -pin  "vin:rsc:mgc_in_wire" {d(29)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(30)} -pin  "vin:rsc:mgc_in_wire" {d(30)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(31)} -pin  "vin:rsc:mgc_in_wire" {d(31)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(32)} -pin  "vin:rsc:mgc_in_wire" {d(32)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(33)} -pin  "vin:rsc:mgc_in_wire" {d(33)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(34)} -pin  "vin:rsc:mgc_in_wire" {d(34)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(35)} -pin  "vin:rsc:mgc_in_wire" {d(35)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(36)} -pin  "vin:rsc:mgc_in_wire" {d(36)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(37)} -pin  "vin:rsc:mgc_in_wire" {d(37)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(38)} -pin  "vin:rsc:mgc_in_wire" {d(38)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(39)} -pin  "vin:rsc:mgc_in_wire" {d(39)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(40)} -pin  "vin:rsc:mgc_in_wire" {d(40)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(41)} -pin  "vin:rsc:mgc_in_wire" {d(41)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(42)} -pin  "vin:rsc:mgc_in_wire" {d(42)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(43)} -pin  "vin:rsc:mgc_in_wire" {d(43)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(44)} -pin  "vin:rsc:mgc_in_wire" {d(44)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(45)} -pin  "vin:rsc:mgc_in_wire" {d(45)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(46)} -pin  "vin:rsc:mgc_in_wire" {d(46)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(47)} -pin  "vin:rsc:mgc_in_wire" {d(47)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(48)} -pin  "vin:rsc:mgc_in_wire" {d(48)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(49)} -pin  "vin:rsc:mgc_in_wire" {d(49)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(50)} -pin  "vin:rsc:mgc_in_wire" {d(50)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(51)} -pin  "vin:rsc:mgc_in_wire" {d(51)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(52)} -pin  "vin:rsc:mgc_in_wire" {d(52)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(53)} -pin  "vin:rsc:mgc_in_wire" {d(53)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(54)} -pin  "vin:rsc:mgc_in_wire" {d(54)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(55)} -pin  "vin:rsc:mgc_in_wire" {d(55)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(56)} -pin  "vin:rsc:mgc_in_wire" {d(56)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(57)} -pin  "vin:rsc:mgc_in_wire" {d(57)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(58)} -pin  "vin:rsc:mgc_in_wire" {d(58)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(59)} -pin  "vin:rsc:mgc_in_wire" {d(59)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(60)} -pin  "vin:rsc:mgc_in_wire" {d(60)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(61)} -pin  "vin:rsc:mgc_in_wire" {d(61)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(62)} -pin  "vin:rsc:mgc_in_wire" {d(62)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(63)} -pin  "vin:rsc:mgc_in_wire" {d(63)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(64)} -pin  "vin:rsc:mgc_in_wire" {d(64)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(65)} -pin  "vin:rsc:mgc_in_wire" {d(65)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(66)} -pin  "vin:rsc:mgc_in_wire" {d(66)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(67)} -pin  "vin:rsc:mgc_in_wire" {d(67)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(68)} -pin  "vin:rsc:mgc_in_wire" {d(68)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(69)} -pin  "vin:rsc:mgc_in_wire" {d(69)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(70)} -pin  "vin:rsc:mgc_in_wire" {d(70)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(71)} -pin  "vin:rsc:mgc_in_wire" {d(71)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(72)} -pin  "vin:rsc:mgc_in_wire" {d(72)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(73)} -pin  "vin:rsc:mgc_in_wire" {d(73)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(74)} -pin  "vin:rsc:mgc_in_wire" {d(74)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(75)} -pin  "vin:rsc:mgc_in_wire" {d(75)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(76)} -pin  "vin:rsc:mgc_in_wire" {d(76)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(77)} -pin  "vin:rsc:mgc_in_wire" {d(77)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(78)} -pin  "vin:rsc:mgc_in_wire" {d(78)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(79)} -pin  "vin:rsc:mgc_in_wire" {d(79)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(80)} -pin  "vin:rsc:mgc_in_wire" {d(80)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(81)} -pin  "vin:rsc:mgc_in_wire" {d(81)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(82)} -pin  "vin:rsc:mgc_in_wire" {d(82)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(83)} -pin  "vin:rsc:mgc_in_wire" {d(83)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(84)} -pin  "vin:rsc:mgc_in_wire" {d(84)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(85)} -pin  "vin:rsc:mgc_in_wire" {d(85)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(86)} -pin  "vin:rsc:mgc_in_wire" {d(86)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(87)} -pin  "vin:rsc:mgc_in_wire" {d(87)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(88)} -pin  "vin:rsc:mgc_in_wire" {d(88)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc:mgc_in_wire.d#1(89)} -pin  "vin:rsc:mgc_in_wire" {d(89)} -attr vt d -attr @path {/sobel/vin:rsc:mgc_in_wire.d}
+load net {vin:rsc.z(0)} -pin  "vin:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(1)} -pin  "vin:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(2)} -pin  "vin:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(3)} -pin  "vin:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(4)} -pin  "vin:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(5)} -pin  "vin:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(6)} -pin  "vin:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(7)} -pin  "vin:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(8)} -pin  "vin:rsc:mgc_in_wire" {z(8)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(9)} -pin  "vin:rsc:mgc_in_wire" {z(9)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(10)} -pin  "vin:rsc:mgc_in_wire" {z(10)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(11)} -pin  "vin:rsc:mgc_in_wire" {z(11)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(12)} -pin  "vin:rsc:mgc_in_wire" {z(12)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(13)} -pin  "vin:rsc:mgc_in_wire" {z(13)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(14)} -pin  "vin:rsc:mgc_in_wire" {z(14)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(15)} -pin  "vin:rsc:mgc_in_wire" {z(15)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(16)} -pin  "vin:rsc:mgc_in_wire" {z(16)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(17)} -pin  "vin:rsc:mgc_in_wire" {z(17)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(18)} -pin  "vin:rsc:mgc_in_wire" {z(18)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(19)} -pin  "vin:rsc:mgc_in_wire" {z(19)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(20)} -pin  "vin:rsc:mgc_in_wire" {z(20)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(21)} -pin  "vin:rsc:mgc_in_wire" {z(21)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(22)} -pin  "vin:rsc:mgc_in_wire" {z(22)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(23)} -pin  "vin:rsc:mgc_in_wire" {z(23)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(24)} -pin  "vin:rsc:mgc_in_wire" {z(24)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(25)} -pin  "vin:rsc:mgc_in_wire" {z(25)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(26)} -pin  "vin:rsc:mgc_in_wire" {z(26)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(27)} -pin  "vin:rsc:mgc_in_wire" {z(27)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(28)} -pin  "vin:rsc:mgc_in_wire" {z(28)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(29)} -pin  "vin:rsc:mgc_in_wire" {z(29)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(30)} -pin  "vin:rsc:mgc_in_wire" {z(30)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(31)} -pin  "vin:rsc:mgc_in_wire" {z(31)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(32)} -pin  "vin:rsc:mgc_in_wire" {z(32)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(33)} -pin  "vin:rsc:mgc_in_wire" {z(33)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(34)} -pin  "vin:rsc:mgc_in_wire" {z(34)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(35)} -pin  "vin:rsc:mgc_in_wire" {z(35)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(36)} -pin  "vin:rsc:mgc_in_wire" {z(36)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(37)} -pin  "vin:rsc:mgc_in_wire" {z(37)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(38)} -pin  "vin:rsc:mgc_in_wire" {z(38)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(39)} -pin  "vin:rsc:mgc_in_wire" {z(39)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(40)} -pin  "vin:rsc:mgc_in_wire" {z(40)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(41)} -pin  "vin:rsc:mgc_in_wire" {z(41)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(42)} -pin  "vin:rsc:mgc_in_wire" {z(42)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(43)} -pin  "vin:rsc:mgc_in_wire" {z(43)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(44)} -pin  "vin:rsc:mgc_in_wire" {z(44)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(45)} -pin  "vin:rsc:mgc_in_wire" {z(45)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(46)} -pin  "vin:rsc:mgc_in_wire" {z(46)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(47)} -pin  "vin:rsc:mgc_in_wire" {z(47)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(48)} -pin  "vin:rsc:mgc_in_wire" {z(48)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(49)} -pin  "vin:rsc:mgc_in_wire" {z(49)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(50)} -pin  "vin:rsc:mgc_in_wire" {z(50)} -attr vt d -attr @path {/sobel/vin:rsc.z}
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+load net {vin:rsc.z(52)} -pin  "vin:rsc:mgc_in_wire" {z(52)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(53)} -pin  "vin:rsc:mgc_in_wire" {z(53)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(54)} -pin  "vin:rsc:mgc_in_wire" {z(54)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(55)} -pin  "vin:rsc:mgc_in_wire" {z(55)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(56)} -pin  "vin:rsc:mgc_in_wire" {z(56)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(57)} -pin  "vin:rsc:mgc_in_wire" {z(57)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(58)} -pin  "vin:rsc:mgc_in_wire" {z(58)} -attr vt d -attr @path {/sobel/vin:rsc.z}
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+load net {vin:rsc.z(65)} -pin  "vin:rsc:mgc_in_wire" {z(65)} -attr vt d -attr @path {/sobel/vin:rsc.z}
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+load net {vin:rsc.z(74)} -pin  "vin:rsc:mgc_in_wire" {z(74)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(75)} -pin  "vin:rsc:mgc_in_wire" {z(75)} -attr vt d -attr @path {/sobel/vin:rsc.z}
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+load net {vin:rsc.z(78)} -pin  "vin:rsc:mgc_in_wire" {z(78)} -attr vt d -attr @path {/sobel/vin:rsc.z}
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+load net {vin:rsc.z(80)} -pin  "vin:rsc:mgc_in_wire" {z(80)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(81)} -pin  "vin:rsc:mgc_in_wire" {z(81)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(82)} -pin  "vin:rsc:mgc_in_wire" {z(82)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(83)} -pin  "vin:rsc:mgc_in_wire" {z(83)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(84)} -pin  "vin:rsc:mgc_in_wire" {z(84)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(85)} -pin  "vin:rsc:mgc_in_wire" {z(85)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(86)} -pin  "vin:rsc:mgc_in_wire" {z(86)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(87)} -pin  "vin:rsc:mgc_in_wire" {z(87)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(88)} -pin  "vin:rsc:mgc_in_wire" {z(88)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load net {vin:rsc.z(89)} -pin  "vin:rsc:mgc_in_wire" {z(89)} -attr vt d -attr @path {/sobel/vin:rsc.z}
+load inst "vout:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(2,30)" "INTERFACE" -attr xrf 40142 -attr oid 629 -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(2,30)" -pg 1 -lvl 1002
+load net {vout:rsc:mgc_out_stdreg.d#1(0)} -pin  "vout:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(1)} -pin  "vout:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(2)} -pin  "vout:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(3)} -pin  "vout:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(4)} -pin  "vout:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(5)} -pin  "vout:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(6)} -pin  "vout:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(7)} -pin  "vout:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(8)} -pin  "vout:rsc:mgc_out_stdreg" {d(8)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(9)} -pin  "vout:rsc:mgc_out_stdreg" {d(9)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(10)} -pin  "vout:rsc:mgc_out_stdreg" {d(10)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(11)} -pin  "vout:rsc:mgc_out_stdreg" {d(11)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(12)} -pin  "vout:rsc:mgc_out_stdreg" {d(12)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(13)} -pin  "vout:rsc:mgc_out_stdreg" {d(13)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(14)} -pin  "vout:rsc:mgc_out_stdreg" {d(14)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(15)} -pin  "vout:rsc:mgc_out_stdreg" {d(15)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(16)} -pin  "vout:rsc:mgc_out_stdreg" {d(16)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(17)} -pin  "vout:rsc:mgc_out_stdreg" {d(17)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(18)} -pin  "vout:rsc:mgc_out_stdreg" {d(18)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(19)} -pin  "vout:rsc:mgc_out_stdreg" {d(19)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(20)} -pin  "vout:rsc:mgc_out_stdreg" {d(20)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(21)} -pin  "vout:rsc:mgc_out_stdreg" {d(21)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(22)} -pin  "vout:rsc:mgc_out_stdreg" {d(22)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(23)} -pin  "vout:rsc:mgc_out_stdreg" {d(23)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(24)} -pin  "vout:rsc:mgc_out_stdreg" {d(24)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(25)} -pin  "vout:rsc:mgc_out_stdreg" {d(25)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(26)} -pin  "vout:rsc:mgc_out_stdreg" {d(26)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(27)} -pin  "vout:rsc:mgc_out_stdreg" {d(27)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(28)} -pin  "vout:rsc:mgc_out_stdreg" {d(28)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc:mgc_out_stdreg.d#1(29)} -pin  "vout:rsc:mgc_out_stdreg" {d(29)} -attr vt d -attr @path {/sobel/vout:rsc:mgc_out_stdreg.d}
+load net {vout:rsc.z(0)} -pin  "vout:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(1)} -pin  "vout:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(2)} -pin  "vout:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(3)} -pin  "vout:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(4)} -pin  "vout:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(5)} -pin  "vout:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(6)} -pin  "vout:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(7)} -pin  "vout:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(8)} -pin  "vout:rsc:mgc_out_stdreg" {z(8)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(9)} -pin  "vout:rsc:mgc_out_stdreg" {z(9)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(10)} -pin  "vout:rsc:mgc_out_stdreg" {z(10)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(11)} -pin  "vout:rsc:mgc_out_stdreg" {z(11)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(12)} -pin  "vout:rsc:mgc_out_stdreg" {z(12)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(13)} -pin  "vout:rsc:mgc_out_stdreg" {z(13)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(14)} -pin  "vout:rsc:mgc_out_stdreg" {z(14)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(15)} -pin  "vout:rsc:mgc_out_stdreg" {z(15)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(16)} -pin  "vout:rsc:mgc_out_stdreg" {z(16)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(17)} -pin  "vout:rsc:mgc_out_stdreg" {z(17)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(18)} -pin  "vout:rsc:mgc_out_stdreg" {z(18)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(19)} -pin  "vout:rsc:mgc_out_stdreg" {z(19)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(20)} -pin  "vout:rsc:mgc_out_stdreg" {z(20)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(21)} -pin  "vout:rsc:mgc_out_stdreg" {z(21)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(22)} -pin  "vout:rsc:mgc_out_stdreg" {z(22)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(23)} -pin  "vout:rsc:mgc_out_stdreg" {z(23)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(24)} -pin  "vout:rsc:mgc_out_stdreg" {z(24)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(25)} -pin  "vout:rsc:mgc_out_stdreg" {z(25)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(26)} -pin  "vout:rsc:mgc_out_stdreg" {z(26)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(27)} -pin  "vout:rsc:mgc_out_stdreg" {z(27)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(28)} -pin  "vout:rsc:mgc_out_stdreg" {z(28)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+load net {vout:rsc.z(29)} -pin  "vout:rsc:mgc_out_stdreg" {z(29)} -attr vt d -attr @path {/sobel/vout:rsc.z}
+### END MODULE 
+
diff --git a/Sobel/solution.v1/directives.tcl b/Sobel/solution.v1/directives.tcl
new file mode 100644
index 0000000..4214ca9
--- /dev/null
+++ b/Sobel/solution.v1/directives.tcl
@@ -0,0 +1,58 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
diff --git a/Sobel/solution.v1/messages.txt b/Sobel/solution.v1/messages.txt
new file mode 100644
index 0000000..705f159
--- /dev/null
+++ b/Sobel/solution.v1/messages.txt
@@ -0,0 +1,6 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
diff --git a/Sobel/solution.v2/directives.tcl b/Sobel/solution.v2/directives.tcl
new file mode 100644
index 0000000..4214ca9
--- /dev/null
+++ b/Sobel/solution.v2/directives.tcl
@@ -0,0 +1,58 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+solution file add {./sobel.h} -type CHEADER
+solution file add {./bmp_io.cpp} -type C++
+solution file add {./tb_blur.cpp} -type C++
+solution file add {./bmp_io.h} -type CHEADER
+solution file add {./shift_class.h} -type CHEADER
+solution file add {./sobel.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY sobel
+go compile
+directive set /sobel/core/ACC2 -UNROLL yes
+directive set /sobel/core/ACC1 -UNROLL yes
+directive set /sobel/core/SHIFT -UNROLL yes
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /sobel/vout -STREAM 30
+directive set /sobel/vin -STREAM 90
+go architect
diff --git a/Sobel/solution.v2/messages.txt b/Sobel/solution.v2/messages.txt
new file mode 100644
index 0000000..572f994
--- /dev/null
+++ b/Sobel/solution.v2/messages.txt
@@ -0,0 +1,15 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+Branching solution 'solution.v1' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
+Branching solution 'solution.v2' at state 'new' (PRJ-2)
diff --git a/bmp_io.cpp b/bmp_io.cpp
new file mode 100644
index 0000000..a3d7bff
--- /dev/null
+++ b/bmp_io.cpp
@@ -0,0 +1,2967 @@
+#include <cstdlib>
+#include <iostream>
+#include <iomanip>
+#include <fstream>
+
+using namespace std;
+
+#include "bmp_io.h"
+
+//
+//  BMP_BYTE_SWAP controls how the program assumes that the bytes in 
+//  multi-byte data are ordered.
+//
+//  "true" is the correct value to use when running on a little-endian machine,
+//  and "false" is for big-endian.
+//
+
+static bool bmp_byte_swap = true;
+
+//****************************************************************************80
+
+bool bmp_byte_swap_get ( void )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_BYTE_SWAP_GET returns the internal value of BMP_BYTE_SWAP.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    26 February 2003
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, bool BMP_BYTE_SWAP_GET, the internal value of BMP_BYTE_SWAP.
+//
+{
+  return bmp_byte_swap;
+}
+//****************************************************************************80
+
+void bmp_byte_swap_set ( bool value )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_BYTE_SWAP_SET sets the internal value of BMP_BYTE_SWAP.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    26 February 2003
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, bool VALUE, the new value of BMP_BYTE_SWAP.
+//
+{
+  bmp_byte_swap = value;
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_08_data_read ( ifstream &file_in, unsigned long int width, 
+  long int height, unsigned char *rarray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_08_DATA_READ reads 8 bit image data of the BMP file.
+// 
+//  Discussion:
+//
+//    On output, the RGB information in the file has been copied into the
+//    R, G and B arrays.
+//
+//    Thanks to Peter Kionga-Kamau for pointing out an error in the
+//    previous implementation.
+//
+//    The standard ">>" operator cannot be used to transfer data, because
+//    it will be deceived by characters that "look like" new lines.
+//
+//    Thanks to Kelly Anderson for pointing out how to modify the program
+//    to handle monochrome images.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    01 April 2005
+//
+//  Author:
+//
+//    Kelly Anderson
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, a pointer to the red color arrays.
+//
+//    Output, bool BMP_08_DATA_READ, is true if an error occurred.
+//
+{
+  char c;
+  bool error;
+  int i;
+  unsigned int i2;
+  unsigned char *indexr;
+  int j;
+  int numbyte;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 1 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+  numbyte = 0;
+
+  for ( j = 0; j < abs ( height ); j++ ) 
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error ) 
+      {
+        cout << "\n";
+        cout << "BMP_08_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading R for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexr = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexr = indexr + 1;
+    }
+//
+//  If necessary, read a few padding characters.
+//
+    for ( i = 0; i < padding; i++ )
+    {
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error )
+      {
+        cout << "\n";
+        cout << "BMP_08_DATA_READ - Warning!\n";
+        cout << "  Failed while reading padding character " << i << "\n";
+        cout << "  of total " << padding << " characters\n";
+        cout << "  at the end of line " << j << "\n";
+        cout << "\n";
+        cout << "  This is a minor error.\n";
+        return false;
+      }
+    }
+  }
+
+  return false;
+}
+//****************************************************************************80
+
+void bmp_08_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_08_DATA_WRITE writes 8 bit image data to a BMP file.
+//
+//  Discussion:
+//
+//    This routine does not seem to be performing properly.  The monochrome
+//    images it creates cannot be read by the XV program, which says that 
+//    they seem to have been prematurely truncated.
+//
+//    The BMP format requires that each horizontal line be a multiple of 4 bytes.
+//    If the data itself does not have a WIDTH that is a multiple of 4, then
+//    the file must be padded with a few extra bytes so that each line has the
+//    appropriate length.  This information, and the corresponding corrective
+//    code, was supplied by Lee Mulcahy.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    02 April 2005
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image in bytes.
+//
+//    Input, long int HEIGHT, the Y dimension of the image in bytes.
+//
+//    Input, unsigned char *RARRAY, pointer to the red color array.
+//
+{
+  int i;
+  unsigned int i2;
+  unsigned char *indexr;
+  int j;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 1 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+
+  for ( j = 0; j < abs ( height ); j++ )
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+      file_out << *indexr;
+      indexr = indexr + 1;
+    }
+
+    for ( i = 0; i < padding; i++ )
+    {
+      file_out << 0;
+    }
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_24_data_read ( ifstream &file_in, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, 
+  unsigned char *barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_24_DATA_READ reads 24 bit image data of the BMP file.
+// 
+//  Discussion:
+//
+//    On output, the RGB information in the file has been copied into the
+//    R, G and B arrays.
+//
+//    Thanks to Peter Kionga-Kamau for pointing out an error in the
+//    previous implementation.
+//
+//    The standard ">>" operator cannot be used to transfer data, because
+//    it will be deceived by characters that "look like" new lines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    11 December 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, *GARRAY, *BARRAY, pointers to the 
+//    red, green and blue color arrays.
+//
+//    Output, bool BMP_24_DATA_READ, is true if an error occurred.
+//
+{
+  char c;
+  bool error;
+  int i;
+  unsigned int i2;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+  int j;
+  int numbyte;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 3 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+  indexg = garray;
+  indexb = barray;
+  numbyte = 0;
+
+  for ( j = 0; j < abs ( height ); j++ ) 
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error )
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading B for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexb = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexb = indexb + 1;
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error ) 
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading G for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexg = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexg = indexg + 1;
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error ) 
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading R for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexr = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexr = indexr + 1;
+    }
+//
+//  If necessary, read a few padding characters.
+//
+    for ( i = 0; i < padding; i++ )
+    {
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error )
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ - Warning!\n";
+        cout << "  Failed while reading padding character " << i << "\n";
+        cout << "  of total " << padding << " characters\n";
+        cout << "  at the end of line " << j << "\n";
+        cout << "\n";
+        cout << "  This is a minor error.\n";
+        return false;
+      }
+    }
+  }
+
+  return false;
+}
+//****************************************************************************80
+
+void bmp_24_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, 
+  unsigned char *barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_24_DATA_WRITE writes 24 bit image data to the BMP file.
+//
+//  Discussion:
+//
+//    The BMP format requires that each horizontal line be a multiple of 4 bytes.
+//    If the data itself does not have a WIDTH that is a multiple of 4, then
+//    the file must be padded with a few extra bytes so that each line has the
+//    appropriate length.  This information, and the corresponding corrective
+//    code, was supplied by Lee Mulcahy.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    11 December 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image in bytes.
+//
+//    Input, long int HEIGHT, the Y dimension of the image in bytes.
+//
+//    Input, unsigned char *RARRAY, *GARRAY, *BARRAY, pointers to the red, green
+//    and blue color arrays.
+//
+{
+  int i;
+  unsigned int i2;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+  int j;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 3 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+  indexg = garray;
+  indexb = barray;
+
+  for ( j = 0; j < abs ( height ); j++ )
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+      file_out << *indexb;
+      file_out << *indexg;
+      file_out << *indexr;
+
+      indexb = indexb + 1;
+      indexg = indexg + 1;
+      indexr = indexr + 1;
+    }
+
+    for ( i = 0; i < padding; i++ )
+    {
+      file_out << 0;
+    }
+  }
+
+  return;
+}
+//****************************************************************************80
+
+void bmp_header1_print ( unsigned short int filetype, 
+  unsigned long int filesize, unsigned short int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER1_PRINT prints the header information of a BMP file.
+//
+//  Discussion:
+//
+//    The header comprises 14 bytes:
+//
+//    2 bytes FILETYPE;        Magic number: "BM",
+//    4 bytes FILESIZE;        Size of file in 32 byte integers,
+//    2 bytes RESERVED1;       Always 0,
+//    2 bytes RESERVED2;       Always 0,
+//    4 bytes BITMAPOFFSET.    Starting position of image data, in bytes.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    05 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, unsigned short int FILETYPE, the file type.
+//
+//    Input, unsigned long int FILESIZE, the file size.
+//
+//    Input, unsigned short int RESERVED1, a reserved value.
+//
+//    Input, unsigned short int RESERVED2, a reserved value.
+//
+//    Input, unsigned long int BITMAPOFFSET, the bitmap offset.
+//
+{
+  cout << "\n";
+  cout << "  Contents of BMP file header:\n";
+  cout << "\n";
+  cout << "    FILETYPE =     " << filetype     << "\n";
+  cout << "    FILESIZE =     " << filesize     << "\n";
+  cout << "    RESERVED1 =    " << reserved1    << "\n";
+  cout << "    RESERVED2 =    " << reserved2    << "\n";
+  cout << "    BITMAPOFFSET = " << bitmapoffset << "\n";
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_header1_read ( ifstream &file_in, unsigned short int *filetype, 
+  unsigned long int *filesize, unsigned short int *reserved1, 
+  unsigned short int *reserved2, unsigned long int *bitmapoffset )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER1_READ reads the header information of a BMP file.
+//
+//  Discussion:
+//
+//    The header comprises 14 bytes:
+//
+//    2 bytes FILETYPE;        Magic number: "BM",
+//    4 bytes FILESIZE;        Size of file in 32 byte integers,
+//    2 bytes RESERVED1;       Always 0,
+//    2 bytes RESERVED2;       Always 0,
+//    4 bytes BITMAPOFFSET.    Starting position of image data, in bytes.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    15 December 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, unsigned short int *FILETYPE, the file type.
+//
+//    Output, unsigned long int *FILESIZE, the file size.
+//
+//    Output, unsigned short int *RESERVED1, a reserved value.
+//
+//    Output, unsigned short int *RESERVED2, a reserved value.
+//
+//    Output, unsigned long int *BITMAPOFFSET, the bitmap offset.
+//
+{
+  bool error;
+  char i1;
+  char i2;  
+//
+//  Read FILETYPE.
+//
+  error = u_short_int_read ( filetype, file_in );
+
+  if ( error )
+  {
+    return error;
+  }
+//
+//  If you are doing swapping, you have to reunswap the filetype, I think, JVB 15 December 2004.
+//
+  if ( bmp_byte_swap )
+  {
+    i1 = ( char ) ( *filetype / 256 );
+    i2 = ( char ) ( *filetype % 256 );
+    *filetype = i2 * 256 + i1;
+  }
+//
+//  Read FILESIZE.
+//
+  error = u_long_int_read ( filesize, file_in );
+  if ( error ) 
+  {
+    return error;
+  }
+//
+//  Read RESERVED1.
+//
+  error = u_short_int_read ( reserved1, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read RESERVED2.
+//
+  error = u_short_int_read ( reserved2, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read BITMAPOFFSET.
+//
+  error = u_long_int_read ( bitmapoffset, file_in );
+  if ( error )
+  {
+    return error;
+  }
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+void bmp_header1_write ( ofstream &file_out, unsigned short int filetype,
+  unsigned long int filesize, unsigned short int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER1_WRITE writes the header information to a BMP file.
+//
+//  Discussion:
+//
+//    The header comprises 14 bytes:
+//
+//    2 bytes FILETYPE;        Magic number: "BM",
+//    4 bytes FILESIZE;        Size of file in 32 byte integers,
+//    2 bytes RESERVED1;       Always 0,
+//    2 bytes RESERVED2;       Always 0,
+//    4 bytes BITMAPOFFSET.    Starting position of image data, in bytes.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    04 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned short int FILETYPE, the file type.
+//
+//    Input, unsigned long int FILESIZE, the file size.
+//
+//    Input, unsigned short int RESERVED1, a reserved value.
+//
+//    Input, unsigned short int RESERVED2, a reserved value.
+//
+//    Input, unsigned long int BITMAPOFFSET, the bitmap offset.
+//
+{
+  u_short_int_write ( filetype, file_out );
+  u_long_int_write ( filesize, file_out );
+  u_short_int_write ( reserved1, file_out );
+  u_short_int_write ( reserved2, file_out );
+  u_long_int_write ( bitmapoffset, file_out );
+
+  return;
+}
+//****************************************************************************80
+
+void bmp_header2_print ( unsigned long int size, unsigned long int width, 
+  long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel, 
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused,  unsigned long int colorsimportant )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER2_PRINT prints the bitmap header information of a BMP file.
+//
+//  Discussion:
+//
+//    The bitmap header is 40 bytes long:
+//
+//    4 bytes SIZE;                Size of this header ( = 40 bytes).
+//    4 bytes WIDTH;               Image width, in pixels.   
+//    4 bytes HEIGHT;              Image height, in pixels.  
+//                                 (Pos/Neg, origin at bottom, top)
+//    2 bytes PLANES;              Number of color planes (always 1).
+//    2 bytes BITSPERPIXEL;        1 to 24.  1, 4, 8, 16, 24 or 32.
+//    4 bytes COMPRESSION;         0, uncompressed; 1, 8 bit RLE; 
+//                                 2, 4 bit RLE; 3, bitfields.
+//    4 bytes SIZEOFBITMAP;        Size of bitmap in bytes. (0 if uncompressed).
+//    4 bytes HORZRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes VERTRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes COLORSUSED;          Number of colors in palette.  (Can be zero).
+//    4 bytes COLORSIMPORTANT.     Minimum number of important colors. (Can be zero).
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    06 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, unsigned short int SIZE, the size of this header in bytes.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned short int PLANES, the number of color planes.
+//
+//    Input, unsigned short int BITSPERPIXEL, color bits per pixel.
+//
+//    Input, unsigned long int COMPRESSION, the compression option.
+//
+//    Input, unsigned long int SIZEOFBITMAP, the size of the bitmap.
+//
+//    Input, unsigned long int HORZRESOLUTION, the horizontal resolution.
+//
+//    Input, unsigned long int VERTRESOLUTION, the vertical resolution.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned long int COLORSIMPORTANT, the minimum number of colors.
+//
+{
+  cout << "\n";
+  cout << "  Contents of BMP file bitmap header:\n";
+  cout << "\n";
+  cout << "    SIZE =            " << size            << "\n";
+  cout << "    WIDTH =           " << width           << "\n";
+  cout << "    HEIGHT =          " << height          << "\n";
+  cout << "    PLANES =          " << planes          << "\n";
+  cout << "    BITSPERPIXEL =    " << bitsperpixel    << "\n";
+  cout << "    COMPRESSION =     " << compression     << "\n";
+  cout << "    SIZEOFBITMAP =    " << sizeofbitmap    << "\n";
+  cout << "    HORZRESOLUTION =  " << horzresolution  << "\n";
+  cout << "    VERTRESOLUTION =  " << vertresolution  << "\n";
+  cout << "    COLORSUSED =      " << colorsused      << "\n";
+  cout << "    COLORSIMPORTANT = " << colorsimportant << "\n";
+
+  return;
+} 
+//****************************************************************************80
+
+bool bmp_header2_read ( ifstream &file_in, unsigned long int *size,
+  unsigned long int *width, long int *height, 
+  unsigned short int *planes, unsigned short int *bitsperpixel,
+  unsigned long int *compression, unsigned long int *sizeofbitmap,
+  unsigned long int *horzresolution, unsigned long int *vertresolution,
+  unsigned long int *colorsused, unsigned long int *colorsimportant )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER2_READ reads the bitmap header information of a BMP file.
+//
+//  Discussion:
+//
+//    The bitmap header is 40 bytes long:
+//
+//    4 bytes SIZE;                Size of this header, in bytes.
+//    4 bytes WIDTH;               Image width, in pixels.   
+//    4 bytes HEIGHT;              Image height, in pixels.  
+//                                 (Pos/Neg, origin at bottom, top)
+//    2 bytes PLANES;              Number of color planes (always 1).
+//    2 bytes BITSPERPIXEL;        1 to 24.  1, 4, 8, 16, 24 or 32.
+//    4 bytes COMPRESSION;         0, uncompressed; 1, 8 bit RLE; 
+//                                 2, 4 bit RLE; 3, bitfields.
+//    4 bytes SIZEOFBITMAP;        Size of bitmap in bytes. (0 if uncompressed).
+//    4 bytes HORZRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes VERTRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes COLORSUSED;          Number of colors in palette.  (Can be zero).
+//    4 bytes COLORSIMPORTANT.     Minimum number of important colors. (Can be zero).
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    03 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, unsigned long int *SIZE, the size of this header in bytes.
+//
+//    Output, unsigned long int *WIDTH, the X dimension of the image.
+//
+//    Output, long int *HEIGHT, the Y dimension of the image.
+//
+//    Output, unsigned short int *PLANES, the number of color planes.
+//
+//    Output, unsigned short int *BITSPERPIXEL, color bits per pixel.
+//
+//    Output, unsigned long int *COMPRESSION, the compression option.
+//
+//    Output, unsigned long int *SIZEOFBITMAP, the size of the bitmap.
+//
+//    Output, unsigned long int *HORZRESOLUTION, the horizontal resolution.
+//
+//    Output, unsigned long int *VERTRESOLUTION, the vertical resolution.
+//
+//    Output, unsigned long int *COLORSUSED, the number of colors in the palette.
+//
+//    Output, unsigned long int *COLORSIMPORTANT, the minimum number of colors.
+//
+//    Output, bool BMP_HEADER2_READ, is true if an error occurred.
+//
+{
+  bool error;
+//
+//  Read SIZE, the size of the header in bytes.
+//
+  error = u_long_int_read ( size, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read WIDTH, the image width in pixels.
+//
+  error = u_long_int_read ( width, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read HEIGHT, the image height in pixels.
+//
+  error = long_int_read ( height, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read PLANES, the number of color planes.
+//
+  error = u_short_int_read ( planes, file_in ); 
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read BITSPERPIXEL.
+//
+  error = u_short_int_read ( bitsperpixel, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read COMPRESSION.
+//
+  error = u_long_int_read ( compression, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read SIZEOFBITMAP.
+//
+  error = u_long_int_read ( sizeofbitmap, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read HORZRESOLUTION.
+//
+  error = u_long_int_read ( horzresolution, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read VERTRESOLUTION.
+//
+  error = u_long_int_read ( vertresolution, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read COLORSUSED.
+//
+  error = u_long_int_read ( colorsused, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read COLORSIMPORTANT.
+//
+  error = u_long_int_read ( colorsimportant, file_in );
+  if ( error )
+  {
+    return error;
+  }
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+void bmp_header2_write ( ofstream &file_out, unsigned long int size,
+  unsigned long int width, long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel,
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused, unsigned long int colorsimportant )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER2_WRITE writes the bitmap header information to a BMP file.
+//
+//  Discussion:
+//
+//    Thanks to Mark Cave-Ayland, mca198@ecs.soton.ac.uk, for pointing out an 
+//    error which caused the code to write one too many long ints, 19 May 2001.
+//
+//    The bitmap header is 40 bytes long:
+//
+//    4 bytes SIZE;                Size of this header, in bytes.
+//    4 bytes WIDTH;               Image width, in pixels.   
+//    4 bytes HEIGHT;              Image height, in pixels.  
+//                                 (Pos/Neg, origin at bottom, top)
+//    2 bytes PLANES;              Number of color planes (always 1).
+//    2 bytes BITSPERPIXEL;        1 to 24.  1, 4, 8, 16, 24 or 32.
+//    4 bytes COMPRESSION;         0, uncompressed; 1, 8 bit RLE; 
+//                                 2, 4 bit RLE; 3, bitfields.
+//    4 bytes SIZEOFBITMAP;        Size of bitmap in bytes. (0 if uncompressed).
+//    4 bytes HORZRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes VERTRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes COLORSUSED;          Number of colors in palette.  (Can be zero).
+//    4 bytes COLORSIMPORTANT.     Minimum number of important colors. (Can be zero).
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    03 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int SIZE, the size of this header in bytes.
+//
+//    Input, unsigned long int WIDTH, the X dimensions of the image.
+//
+//    Input, long int HEIGHT, the Y dimensions of the image.
+//
+//    Input, unsigned short int PLANES, the number of color planes.
+//
+//    Input, unsigned short int BITSPERPIXEL, color bits per pixel.
+//
+//    Input, unsigned long int COMPRESSION, the compression option.
+//
+//    Input, unsigned long int SIZEOFBITMAP, the size of the bitmap.
+//
+//    Input, unsigned long int HORZRESOLUTION, the horizontal resolution.
+//
+//    Input, unsigned long int VERTRESOLUTION, the vertical resolution.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned long int COLORSIMPORTANT, the minimum number of colors.
+//
+{
+  u_long_int_write ( size, file_out );
+  u_long_int_write ( width, file_out );
+  long_int_write ( height, file_out );
+  u_short_int_write ( planes, file_out ); 
+  u_short_int_write ( bitsperpixel, file_out );
+  u_long_int_write ( compression, file_out );
+  u_long_int_write ( sizeofbitmap, file_out );
+  u_long_int_write ( horzresolution, file_out );
+  u_long_int_write ( vertresolution, file_out );
+  u_long_int_write ( colorsused, file_out );
+  u_long_int_write ( colorsimportant, file_out );
+
+  return;
+}
+//****************************************************************************80
+
+void bmp_palette_print ( unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_PALETTE_PRINT prints the palette data in a BMP file.
+// 
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    05 March 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned char *RPARRAY, *GPARRAY, *BPARRAY, *APARRAY, pointers to the 
+//    red, green, blue and transparency palette arrays.
+//
+{
+  unsigned int i;
+  unsigned char *indexa;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+
+  cout << "\n";
+  cout << "  Palette information from BMP file:\n";
+  cout << "\n";
+
+  if ( colorsused < 1 )
+  {
+    cout << "    There are NO colors defined for the palette.\n";
+    return;
+  }
+
+  indexr = rparray;
+  indexg = gparray;
+  indexb = bparray;
+  indexa = aparray;
+
+  cout << "\n";
+  cout << " Color    Blue   Green     Red   Trans\n";
+  cout << "\n";
+
+  for ( i = 0; i < colorsused; i++ )
+  {
+    cout << setw(6) << i       << "  "
+         << setw(6) << *indexb << "  "
+         << setw(6) << *indexg << "  "
+         << setw(6) << *indexr << "  "
+         << setw(6) << *indexa << "\n";
+
+    indexb = indexb + 1;
+    indexg = indexg + 1;
+    indexr = indexr + 1;
+    indexa = indexa + 1;
+
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_palette_read ( ifstream &file_in, unsigned long int colorsused,
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray, 
+  unsigned char *aparray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_PALETTE_READ reads the palette information of a BMP file.
+//
+//  Discussion:
+// 
+//    There are COLORSUSED colors listed.  For each color, the values of
+//    (B,G,R,A) are listed, where A is a quantity reserved for future use.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    05 March 2003
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned char *RPARRAY, *GPARRAY, *BPARRAY, *APARRAY pointers to the 
+//    red, green, blue and transparency palette arrays.
+//
+//    Output, bool BMP_PALETTE_READ, is true if an error occurred.
+//
+{
+  char c;
+  bool error;
+  unsigned int i;
+  unsigned char *indexa;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+
+  indexr = rparray;
+  indexg = gparray;
+  indexb = bparray;
+  indexa = aparray;
+
+  for ( i = 0; i < colorsused; i++ )
+  {
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading B for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexb = ( unsigned char ) c;
+    indexb = indexb + 1;
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading G for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexg = ( unsigned char ) c;
+    indexg = indexg + 1;
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading R for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexr = ( unsigned char ) c;
+    indexr = indexr + 1;
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading A for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexa = ( unsigned char ) c;
+    indexa = indexa + 1;
+  }
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+void bmp_palette_write ( ofstream &file_out, unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_PALETTE_WRITE writes the palette data to the BMP file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    04 March 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned char *RPARRAY, *GPARRAY, *BPARRAY, *APARRAY, pointers to the 
+//    red, green, blue and transparency palette arrays.
+//
+{
+  unsigned int i;
+  unsigned char *indexa;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+
+  indexr = rparray;
+  indexg = gparray;
+  indexb = bparray;
+  indexa = aparray;
+
+  for ( i = 0; i < colorsused; i++ )
+  {
+    file_out << *indexb;
+    file_out << *indexg;
+    file_out << *indexr;
+    file_out << *indexa;
+
+    indexb = indexb + 1;
+    indexg = indexg + 1;
+    indexr = indexr + 1;
+    indexa = indexa + 1;
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_print_test ( char *file_in_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_PRINT_TEST tests the BMP print routines.
+//
+//  Discussion:
+//
+//    Thanks to Tak Fung for suggesting that BMP files should be opened with
+//    the binary option.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    13 August 2007
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_IN_NAME, the name of the input file.
+//
+//    Output, bool BMP_PRINT_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  unsigned char *aparray;
+  unsigned char *barray;
+  unsigned char *bparray;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ifstream file_in;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *garray;
+  unsigned char *gparray;
+  long int height;
+  unsigned long int horzresolution;
+  int numbytes;
+  unsigned short int planes;
+  unsigned char *rarray;
+  unsigned char *rparray;
+  unsigned short int reserved1;
+  unsigned short int reserved2;
+  unsigned long int size;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+  unsigned long int width;
+//
+//  Open the input file.
+//
+  file_in.open ( file_in_name, ios::in | ios::binary );
+
+  if ( !file_in ) 
+  {
+    error = true;
+    cout << "\n";
+    cout << "BMP_PRINT_TEST - Fatal error!\n";
+    cout << "  Could not open the input file.\n";
+    return error;
+  }
+  cout << "\n";
+  cout << "BMP_PRINT_TEST:\n";
+  cout << "  Contents of BMP file \"" << file_in_name << "\"\n";
+//
+//  Read header 1.
+//
+  error = bmp_header1_read ( file_in, &filetype, &filesize, &reserved1, 
+    &reserved2, &bitmapoffset );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_PRINT_TEST: Fatal error!\n";
+    cout << "  BMP_HEADER1_READ failed.\n";
+    return error;
+  }
+
+  bmp_header1_print ( filetype, filesize, reserved1, reserved2, bitmapoffset );
+//
+//  Read header 2.
+//
+  error = bmp_header2_read ( file_in, &size, &width, &height, &planes,
+    &bitsperpixel, &compression, &sizeofbitmap, &horzresolution,
+    &vertresolution, &colorsused, &colorsimportant );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_PRINT_TEST: Fatal error!\n";
+    cout << "  BMP_HEADER2_READ failed.\n";
+    return error;
+  }
+
+  bmp_header2_print ( size, width, height, planes, bitsperpixel,
+    compression, sizeofbitmap, horzresolution, vertresolution, 
+    colorsused, colorsimportant );
+//
+//  Read the palette.
+//
+//if ( 0 < colorsused )
+//{
+    rparray = new unsigned char[colorsused];
+    gparray = new unsigned char[colorsused];
+    bparray = new unsigned char[colorsused];
+    aparray = new unsigned char[colorsused];
+
+    error = bmp_palette_read ( file_in, colorsused, rparray, gparray,
+      bparray, aparray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_PRINT_TEST: Fatal error!\n";
+      cout << "  BMP_PALETTE_READ failed.\n";
+      return error;
+    }
+
+    bmp_palette_print ( colorsused, rparray, gparray, bparray, aparray );
+
+    delete [] rparray;
+    delete [] gparray;
+    delete [] bparray;
+    delete [] aparray;
+//}
+//
+//  Allocate storage.
+//
+  numbytes = width * abs ( height ) * sizeof ( unsigned char );
+//
+//  Read the data.
+//
+  if ( bitsperpixel == 8 )
+  {
+    rarray = new unsigned char[numbytes];
+
+    error = bmp_08_data_read ( file_in, width, height, rarray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_PRINT_TEST: Fatal error!\n";
+      cout << "  BMP_08_DATA_READ failed.\n";
+      return error;
+    }
+
+    *garray = *rarray;
+    *barray = *rarray;
+  }
+  else if ( bitsperpixel == 24 )
+  {
+    rarray = new unsigned char[numbytes];
+    garray = new unsigned char[numbytes];
+    barray = new unsigned char[numbytes];
+    
+    error = bmp_24_data_read ( file_in, width, height, rarray, garray, 
+      barray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_PRINT_TEST: Fatal error!\n";
+      cout << "  BMP_24_DATA_READ failed.\n";
+      return error;
+    }
+  }
+  else
+  {
+    cout << "\n";
+    cout << "BMP_PRINT_TEST: Fatal error!\n";
+    cout << "  Unrecognized value of BITSPERPIXEL = " << bitsperpixel << "\n";
+    return 1;
+  }
+
+  delete [] rarray;
+  delete [] garray;
+  delete [] barray;
+//
+//  Close the file.
+//
+  file_in.close ( );
+
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool bmp_read ( char *file_in_name, unsigned long int *width, long int *height, 
+  unsigned char **rarray, unsigned char **garray, unsigned char **barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_READ reads the header and data of a BMP file.
+//
+//  Discussion:
+//
+//    Thanks to Tak Fung for suggesting that BMP files should be opened with
+//    the binary option.
+//
+//    Thanks to Kelly Anderson for discovering that the routine could not read
+//    monochrome images (bitsperpixel = 8 ) and suggesting how to fix that.
+//
+//    Thanks to Vladimir Levin for correcting a memory leak in the monochrome
+//    image portion of the test, 13 August 2007.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    13 August 2007
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_IN_NAME, the name of the input file.
+//
+//    Output, unsigned long int *WIDTH, the X dimension of the image.
+//
+//    Output, long int *HEIGHT, the Y dimension of the image.
+//
+//    Output, unsigned char **RARRAY, **GARRAY, **BARRAY, pointers to the red, green
+//    and blue color arrays.
+//
+//    Output, bool BMP_READ, is true if an error occurred.
+//
+{
+  unsigned char *aparray;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned char *bparray;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ifstream file_in;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *gparray;
+  unsigned long int horzresolution;
+  unsigned short int magic;
+  int numbytes;
+  unsigned short int planes;
+  unsigned short int reserved1;
+  unsigned short int reserved2;
+  unsigned char *rparray;
+  unsigned long int size;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+//
+//  Open the input file.
+//
+  file_in.open ( file_in_name, ios::in | ios::binary );
+
+  if ( !file_in ) 
+  {
+    error = true;
+    cout << "\n";
+    cout << "BMP_READ - Fatal error!\n";
+    cout << "  Could not open the input file.\n";
+    return error;
+  }
+//
+//  Read header 1.
+//
+  error = bmp_header1_read ( file_in, &filetype, &filesize, &reserved1, 
+    &reserved2, &bitmapoffset );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  BMP_HEADER1_READ failed.\n";
+    return error;
+  }
+//
+//  Make sure the filetype is 'BM'.
+//
+  magic = 'B' * 256 + 'M';
+
+  if ( filetype != magic )
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  The file's internal magic number is not \"BM\".\n";
+    cout << "  with the numeric value " << magic << "\n";
+    cout << "\n";
+    cout << "  Instead, it is \"" 
+         << ( char ) ( filetype / 256 ) 
+         << ( char ) ( filetype % 256 )
+         << "\".\n";
+    cout << "  with the numeric value " << filetype << "\n";
+    cout << "\n";
+    cout << "  (Perhaps you need to reverse the byte swapping option!)\n";
+    return 1;
+  }
+//
+//  Read header 2.
+//
+  error = bmp_header2_read ( file_in, &size, width, height, &planes,
+    &bitsperpixel, &compression, &sizeofbitmap, &horzresolution,
+    &vertresolution, &colorsused, &colorsimportant );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  BMP_HEADER2_READ failed.\n";
+    return error;
+  }
+//
+//  Read the palette.
+//
+  if ( 0 < colorsused )
+  {
+    rparray = new unsigned char[colorsused];
+    gparray = new unsigned char[colorsused];
+    bparray = new unsigned char[colorsused];
+    aparray = new unsigned char[colorsused];
+
+    error = bmp_palette_read ( file_in, colorsused, rparray, gparray,
+      bparray, aparray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_READ: Fatal error!\n";
+      cout << "  BMP_PALETTE_READ failed.\n";
+      return error;
+    }
+    delete [] rparray;
+    delete [] gparray;
+    delete [] bparray;
+    delete [] aparray;
+  }
+//
+//  Allocate storage.
+//
+  numbytes = ( *width ) * ( abs ( *height ) ) * sizeof ( unsigned char );
+//
+//  Read the data.
+//
+  if ( bitsperpixel == 8 )
+  {
+    *rarray = new unsigned char[numbytes];
+
+    error = bmp_08_data_read ( file_in, *width, *height, *rarray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_READ: Fatal error!\n";
+      cout << "  BMP_08_DATA_READ failed.\n";
+      return error;
+    }
+
+    *garray = *rarray;
+    *barray = *rarray;
+  }
+  else if ( bitsperpixel == 24 )
+  {
+    *rarray = new unsigned char[numbytes];
+    *garray = new unsigned char[numbytes];
+    *barray = new unsigned char[numbytes];
+
+    error = bmp_24_data_read ( file_in, *width, *height, *rarray, *garray, 
+      *barray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_READ: Fatal error!\n";
+      cout << "  BMP_24_DATA_READ failed.\n";
+      return error;
+    }
+  }
+  else
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  Unrecognized value of BITSPERPIXEL = " << bitsperpixel << "\n";
+    return 1;
+  }
+//
+//  Close the file.
+//
+  file_in.close ( );
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+bool bmp_read_test ( char *file_in_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_READ_TEST tests the BMP read routines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_IN_NAME, the name of the input file.
+//
+//    Output, bool BMP_READ_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  unsigned char *barray;
+  bool error;
+  unsigned char *garray;
+  long int height;
+  unsigned char *rarray;
+  unsigned long int width;
+
+  rarray = NULL;
+  garray = NULL;
+  barray = NULL;
+//
+//  Read the data from file.
+//
+  error = bmp_read ( file_in_name, &width, &height, &rarray, &garray, 
+    &barray );
+//
+//  Free the memory.
+//
+  delete [] rarray;
+  delete [] garray;
+  delete [] barray;
+
+  if ( VERBOSE )
+  {
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_READ_TEST - Fatal error!\n";
+      cout << "  The test failed.\n";
+    }
+    else
+    {
+      cout << "\n";
+      cout << "BMP_READ_TEST:\n";
+      cout << "  WIDTH =  " << width  << ".\n";
+      cout << "  HEIGHT = " << height << ".\n";
+      cout << "\n";
+      cout << "BMP_READ_TEST:\n";
+      cout << "  The test was successful.\n";
+    }
+  }
+
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool bmp_08_write ( char *file_out_name, unsigned long int width,
+  long int height, unsigned char *rarray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_08_WRITE writes the header and data for a monochrome BMP file.
+//
+//  Discussion:
+//
+//    XV seems to think the resulting BMP file is "unexpectedly truncated".
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    02 April 2005
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, pointer to the red color array.
+//
+//    Output, bool BMP_08_WRITE, is true if an error occurred.
+//
+{
+  unsigned char *aparray = NULL;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned char *bparray = NULL;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ofstream file_out;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *gparray = NULL;
+  unsigned long int horzresolution;
+  int padding;
+  unsigned short int planes;
+  unsigned short int reserved1 = 0;
+  unsigned short int reserved2 = 0;
+  unsigned char *rparray = NULL;
+  unsigned long int size = 40;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+//
+//  Open the output file.
+//
+  file_out.open ( file_out_name, ios::out | ios::binary );
+
+  error = !file_out;
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_08_WRITE - Fatal error!\n";
+    cout << "  Could not open the output file.\n";
+    return error;
+  }
+//
+//  Write header 1.
+//
+  if ( bmp_byte_swap )
+  {
+    filetype = 'M' * 256 + 'B';
+  }
+  else
+  {
+    filetype = 'B' * 256 + 'M';
+  }
+//
+//  Determine the padding needed when WIDTH is not a multiple of 4.
+//
+  padding = ( 4 - ( ( 1 * width ) % 4 ) ) % 4;
+
+  filesize = 54 + ( width + padding ) * abs ( height );
+  bitmapoffset = 54;
+
+  bmp_header1_write ( file_out, filetype, filesize, reserved1, 
+    reserved2, bitmapoffset );
+//
+//  Write header 2.
+//
+  planes = 1;
+  bitsperpixel = 8;
+  compression = 0;
+  sizeofbitmap = 0;
+  horzresolution = 0;
+  vertresolution = 0;
+  colorsused = 0;
+  colorsimportant = 0;
+
+  bmp_header2_write ( file_out, size, width, height, planes, bitsperpixel, 
+    compression, sizeofbitmap, horzresolution, vertresolution,
+    colorsused, colorsimportant );
+//
+//  Write the palette.
+//
+  bmp_palette_write ( file_out, colorsused, rparray, gparray, bparray, 
+    aparray );
+//
+//  Write the data.
+//
+  bmp_08_data_write ( file_out, width, height, rarray );
+//
+//  Close the file.
+//
+  file_out.close ( );
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+bool bmp_08_write_test ( char *file_out_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_08_WRITE_TEST tests the BMP write routines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    02 April 2005
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Output, bool BMP_08_WRITE_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  bool error;
+  long int height;
+  int i;
+  unsigned char *indexr;
+  int j;
+  int numbytes;
+  unsigned char *rarray;
+  unsigned long int width;
+
+  width = 255;
+  height = 255;
+//
+//  Allocate the memory.
+//
+  numbytes = width * abs ( height ) * sizeof ( unsigned char );  
+
+  rarray = new unsigned char[numbytes];
+//
+//  Set the data.
+//
+  indexr = rarray;
+
+  for ( j = 0; j < height; j++ )
+  {
+    for ( i = 0; i < ( int ) width; i++ )
+    {
+      *indexr = i % ( j + 1 );
+      indexr = indexr + 1;
+    }
+  }
+//
+//  Write the data to a file.
+//
+  error = bmp_08_write ( file_out_name, width, height, rarray );
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_08_WRITE_TEST - Fatal error!\n";
+    cout << "  The test failed.\n";
+    return error;
+  }
+//
+//  Free the memory.
+//
+  delete [] rarray;
+
+  if ( VERBOSE )
+  {
+    cout << "\n";
+    cout << "BMP_08_WRITE_TEST:\n";
+    cout << "  The test was successful.\n";
+  }
+
+  error = false;
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool bmp_24_write ( char *file_out_name, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, 
+  unsigned char *barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_24_WRITE writes the header and data for a BMP file using three colors.
+//
+//  Discussion
+//
+//    Thanks to Keefe Roedersheimer for pointing out that I was creating
+//    a filetype of 'MB' instead of 'BM'.
+//
+//    Lee Mulcahy pointed out that the BMP format requires that horizonal lines
+//    must have a length that is a multiple of 4, or be padded so that this is the case.
+//
+//    Thanks to Tak Fung for suggesting that BMP files should be opened with
+//    the binary option.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    02 April 2005
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, *GARRAY, *BARRAY, pointers to the red, green
+//    and blue color arrays.
+//
+//    Output, bool BMP_24_WRITE, is true if an error occurred.
+//
+{
+  unsigned char *aparray = NULL;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned char *bparray = NULL;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ofstream file_out;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *gparray = NULL;
+  unsigned long int horzresolution;
+  int padding;
+  unsigned short int planes;
+  unsigned short int reserved1 = 0;
+  unsigned short int reserved2 = 0;
+  unsigned char *rparray = NULL;
+  unsigned long int size = 40;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+//
+//  Open the output file.
+//
+  file_out.open ( file_out_name, ios::out | ios::binary );
+
+  error = !file_out;
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_24_WRITE - Fatal error!\n";
+    cout << "  Could not open the output file.\n";
+    return error;
+  }
+//
+//  Write header 1.
+//
+  if ( bmp_byte_swap )
+  {
+    filetype = 'M' * 256 + 'B';
+  }
+  else
+  {
+    filetype = 'B' * 256 + 'M';
+  }
+//
+//  Determine the padding needed when WIDTH is not a multiple of 4.
+//
+  padding = ( 4 - ( ( 3 * width ) % 4 ) ) % 4;
+
+  filesize = 54 + ( ( 3 * width ) + padding ) * abs ( height );
+  bitmapoffset = 54;
+
+  bmp_header1_write ( file_out, filetype, filesize, reserved1, 
+    reserved2, bitmapoffset );
+//
+//  Write header 2.
+//
+  planes = 1;
+  bitsperpixel = 24;
+  compression = 0;
+  sizeofbitmap = 0;
+  horzresolution = 0;
+  vertresolution = 0;
+  colorsused = 0;
+  colorsimportant = 0;
+
+  bmp_header2_write ( file_out, size, width, height, planes, bitsperpixel, 
+    compression, sizeofbitmap, horzresolution, vertresolution,
+    colorsused, colorsimportant );
+//
+//  Write the palette.
+//
+  bmp_palette_write ( file_out, colorsused, rparray, gparray, bparray, 
+    aparray );
+//
+//  Write the data.
+//
+  bmp_24_data_write ( file_out, width, height, rarray, garray, barray );
+//
+//  Close the file.
+//
+  file_out.close ( );
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+bool bmp_24_write_test ( char *file_out_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_24_WRITE_TEST tests the BMP write routines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Output, bool BMP_24_WRITE_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  unsigned char *barray;
+  bool error;
+  unsigned char *garray;
+  long int height;
+  int i;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+  int j;
+  int j2;
+  int numbytes;
+  unsigned char *rarray;
+  unsigned long int width;
+
+  width = 200;
+  height = 200;
+//
+//  Allocate the memory.
+//
+  numbytes = width * abs ( height ) * sizeof ( unsigned char );  
+
+  rarray = new unsigned char[numbytes];
+  garray = new unsigned char[numbytes];
+  barray = new unsigned char[numbytes];
+//
+//  Set the data.
+//  Note that BMP files go from "bottom" up, so we'll reverse the
+//  sense of "J" here to get what we want.
+//
+  indexr = rarray;
+  indexg = garray;
+  indexb = barray;
+
+  for ( j2 = 0; j2 < abs ( height ); j2++ )
+  {
+    j = abs ( height ) - j2;
+    for ( i = 0; i < ( int ) width; i++ )
+    {
+      if ( i <= j )
+      {
+        *indexr = 255;
+        *indexg = 0;
+        *indexb = 0;
+      }
+      else if ( ( width - 1 ) * j + ( abs ( height ) - 1 ) * i <= 
+        ( width - 1 ) * ( abs ( height ) - 1 ) )
+      {
+        *indexr = 0;
+        *indexg = 255;
+        *indexb = 0;
+      }
+      else
+      {
+        *indexr = 0;
+        *indexg = 0;
+        *indexb = 255;
+      }
+      indexr = indexr + 1;
+      indexg = indexg + 1;
+      indexb = indexb + 1;
+    }
+  }
+//
+//  Write the data to a file.
+//
+  error = bmp_24_write ( file_out_name, width, height, rarray, garray, barray );
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_24_WRITE_TEST - Fatal error!\n";
+    cout << "  The test failed.\n";
+    return error;
+  }
+//
+//  Free the memory.
+//
+  delete [] rarray;
+  delete [] garray;
+  delete [] barray;
+
+  if ( VERBOSE )
+  {
+    cout << "\n";
+    cout << "BMP_24_WRITE_TEST:\n";
+    cout << "  The test was successful.\n";
+  }
+
+  error = false;
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool long_int_read ( long int *long_int_val, ifstream &file_in )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    LONG_INT_READ reads a long int from a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    06 March 2004
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, long int *LONG_INT_VAL, the value that was read.
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, bool LONG_INT_READ, is true if an error occurred.
+//
+{
+  bool error;
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  if ( bmp_byte_swap )
+  {
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+  else
+  {
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+
+  *long_int_val = ( long int ) 
+    ( u_short_int_val_hi << 16 ) | u_short_int_val_lo;
+
+  return false;
+}
+//****************************************************************************80
+
+void long_int_write ( long int long_int_val, ofstream &file_out )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    LONG_INT_WRITE writes a long int to a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    06 March 2004
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, long int *LONG_INT_VAL, the value to be written.
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+{
+  long int temp;
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  temp = long_int_val / 65536;
+  if ( temp < 0 )
+  {
+    temp = temp + 65536;
+  }
+  u_short_int_val_hi = ( unsigned short ) temp;
+
+  temp = long_int_val % 65536;
+  if ( temp < 0 )
+  {
+    temp = temp + 65536;
+  }
+  u_short_int_val_lo = ( unsigned short ) temp;
+
+  if ( bmp_byte_swap )
+  {
+    u_short_int_write ( u_short_int_val_lo, file_out );
+    u_short_int_write ( u_short_int_val_hi, file_out );
+  }
+  else
+  {
+    u_short_int_write ( u_short_int_val_hi, file_out );
+    u_short_int_write ( u_short_int_val_lo, file_out );
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool u_long_int_read ( unsigned long int *u_long_int_val, 
+  ifstream &file_in )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_LONG_INT_READ reads an unsigned long int from a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, unsigned long int *U_LONG_INT_VAL, the value that was read.
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, bool U_LONG_INT_READ, is true if an error occurred.
+//
+{
+  bool error;
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  if ( bmp_byte_swap )
+  {
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+  else
+  {
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+//
+//  Acknowledgement:
+//
+//    A correction to the following line was supplied by
+//    Peter Kionga-Kamau, 20 May 2000.
+//
+
+  *u_long_int_val = ( u_short_int_val_hi << 16 ) | u_short_int_val_lo;
+
+  return false;
+}
+//****************************************************************************80
+
+void u_long_int_write ( unsigned long int u_long_int_val, 
+  ofstream &file_out )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_LONG_INT_WRITE writes an unsigned long int to a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, unsigned long int *U_LONG_INT_VAL, the value to be written.
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+{
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  u_short_int_val_hi = ( unsigned short ) ( u_long_int_val / 65536 );
+  u_short_int_val_lo = ( unsigned short ) ( u_long_int_val % 65536 );
+
+  if ( bmp_byte_swap )
+  {
+    u_short_int_write ( u_short_int_val_lo, file_out );
+    u_short_int_write ( u_short_int_val_hi, file_out );
+  }
+  else
+  {
+    u_short_int_write ( u_short_int_val_hi, file_out );
+    u_short_int_write ( u_short_int_val_lo, file_out );
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool u_short_int_read ( unsigned short int *u_short_int_val, 
+  ifstream &file_in )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_SHORT_INT_READ reads an unsigned short int from a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    30 March 2005
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, unsigned short int *U_SHORT_INT_VAL, the value that was read.
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, bool U_SHORT_INT_READ, is true if an error occurred.
+//
+{
+  char c;
+  unsigned char chi;
+  unsigned char clo;
+
+  if ( bmp_byte_swap )
+    {
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    clo = ( unsigned char ) c;
+
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    chi = ( unsigned char ) c;
+  }
+  else
+  {
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    chi = ( unsigned char ) c;
+
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    clo = ( unsigned char ) c;
+  }
+
+  *u_short_int_val = ( chi << 8 ) | clo;
+
+  return false;
+}
+//****************************************************************************80
+
+void u_short_int_write ( unsigned short int u_short_int_val, 
+  ofstream &file_out )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_SHORT_INT_WRITE writes an unsigned short int to a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    26 February 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, unsigned short int *U_SHORT_INT_VAL, the value to be written.
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+{
+  unsigned char chi;
+  unsigned char clo;
+
+  chi = ( unsigned char ) ( u_short_int_val / 256 );
+  clo = ( unsigned char ) ( u_short_int_val % 256 );
+
+  if ( bmp_byte_swap )
+  {
+    file_out << clo << chi;
+  }
+  else
+  {
+    file_out << chi << clo;
+  }
+
+  return;
+}
diff --git a/bmp_io.h b/bmp_io.h
new file mode 100644
index 0000000..2fe3298
--- /dev/null
+++ b/bmp_io.h
@@ -0,0 +1,80 @@
+#include <fstream>
+#include <iostream>
+
+using namespace std;
+
+
+bool bmp_byte_swap_get ( void );
+void bmp_byte_swap_set ( bool value );
+
+bool bmp_08_data_read ( ifstream &file_in, unsigned long int width, long int height, 
+  unsigned char *rarray );
+void bmp_08_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray );
+
+bool bmp_24_data_read ( ifstream &file_in, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+void bmp_24_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+
+void bmp_header1_print ( unsigned short int filetype, 
+  unsigned long int filesize, unsigned short int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset );
+bool bmp_header1_read ( ifstream &file_in, unsigned short int *filetype, 
+  unsigned long int *filesize, unsigned long int *reserved1, 
+  unsigned short int *reserved2, unsigned long int *bitmapoffset );
+void bmp_header1_write ( ofstream &file_out, unsigned short int filetype,
+  unsigned long int filesize, unsigned long int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset );
+
+void bmp_header2_print ( unsigned long int size, unsigned long int width, 
+  long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel, 
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused,  unsigned long int colorsimportant );
+bool bmp_header2_read ( ifstream &file_in, unsigned long int *size,
+  unsigned long int *width, long int *height, 
+  unsigned short int *planes, unsigned short int *bitsperpixel,
+  unsigned long int *compression, unsigned long int *sizeofbitmap,
+  unsigned long int *horzresolution, unsigned long int *vertresolution,
+  unsigned long int *colorsused, unsigned long int *colorsimportant );
+void bmp_header2_write ( ofstream &file_out, unsigned long int size,
+  unsigned long int width, long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel,
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused, unsigned long int colorsimportant );
+
+void bmp_palette_print ( unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray );
+bool bmp_palette_read ( ifstream &file_in, unsigned long int colorsused,
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray, 
+  unsigned char *aparray );
+void bmp_palette_write ( ofstream &file_out, unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray );
+
+bool bmp_print_test ( char *file_in_name );
+
+bool bmp_read ( char *file_in_name, unsigned long int *width, long int *height, 
+  unsigned char **rarray, unsigned char **garray, unsigned char **barray );
+bool bmp_read_test ( char *file_in_name );
+
+bool bmp_08_write ( char *file_out_name, unsigned long int width, long int height, 
+  unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+bool bmp_08_write_test ( char *file_out_name );
+
+bool bmp_24_write ( char *file_out_name, unsigned long int width, long int height, 
+  unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+bool bmp_24_write_test ( char *file_out_name );
+
+bool long_int_read ( long int *long_int_val, ifstream &file_in );
+void long_int_write ( long int long_int_val, ofstream &file_out );
+
+bool u_long_int_read ( unsigned long int *u_long_int_val, ifstream &file_in );
+void u_long_int_write ( unsigned long int u_long_int_val, ofstream &file_out );
+
+bool u_short_int_read ( unsigned short int *u_short_int_val, ifstream &file_in );
+void u_short_int_write ( unsigned short int u_short_int_val, ofstream &file_out );
diff --git a/catapult.log b/catapult.log
new file mode 100644
index 0000000..624a4e9
--- /dev/null
+++ b/catapult.log
@@ -0,0 +1,3058 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-013 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+//  Start time Tue Mar 08 13:24:38 2016
+# -------------------------------------------------
+# Logging session transcript to file "C:\Users\mg3115\AppData\Local\Temp\log8808d498e0.0"
+# Loading options from registry.
+project new -name Sobel
+set_working_dir {//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult}
+solution file add ./sobel.h
+# /INPUTFILES/1
+solution file add ./bmp_io.cpp
+# /INPUTFILES/2
+solution file add ./tb_blur.cpp
+# /INPUTFILES/3
+solution file add ./bmp_io.h
+# /INPUTFILES/4
+solution file add ./shift_class.h
+# /INPUTFILES/5
+solution file add ./sobel.cpp
+# /INPUTFILES/6
+# File '//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/sobel.h' saved
+# File '//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/sobel.cpp' saved
+# File '//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/sobel.cpp' saved
+# File '//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/sobel.cpp' saved
+# File '//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/sobel.h' saved
+# File '//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/sobel.cpp' saved
+# File '//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/sobel.cpp' saved
+# File '//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/sobel.h' saved
+# File '//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/sobel.h' saved
+# File '//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/sobel.cpp' saved
+# File '//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/sobel.cpp' saved
+go analyze
+# Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\Sobel'. (PRJ-1)
+# Moving session transcript to file "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\catapult.log"
+# Info: Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(129): $PROJECT_HOME/sobel.cpp(129): last line of file ends without a newline (CRD-1)
+# Error: $PROJECT_HOME/tb_blur.cpp(43): $PROJECT_HOME/tb_blur.cpp(43): could not open source file "blur.h" (CRD-5)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Error: Compilation aborted (CIN-5)
+# Error: go analyze: Failed analyze
+# File '$PROJECT_HOME/tb_blur.cpp' saved
+go analyze
+# Info: Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(129): $PROJECT_HOME/sobel.cpp(129): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Error: $PROJECT_HOME/tb_blur.cpp(184): $PROJECT_HOME/tb_blur.cpp(184): identifier "mean_vga" is undefined (CRD-20)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# Error: Compilation aborted (CIN-5)
+# Error: go analyze: Failed analyze
+# File '$PROJECT_HOME/tb_blur.cpp' saved
+go analyze
+# Info: Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(129): $PROJECT_HOME/sobel.cpp(129): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# $PROJECT_HOME/sobel.cpp(49): Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+# Source file analysis completed (CIN-68)
+# Info: Completed transformation 'analyze' on solution 'solution.v1': elapsed time 2.95 seconds, memory usage 161640kB, peak memory usage 279044kB (SOL-9)
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+# /TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_HIGH_TIME 10.00 -CLOCK_OFFSET 0.000000 -CLOCK_UNCERTAINTY 0.0 -RESET_KIND sync -RESET_SYNC_NAME rst -RESET_SYNC_ACTIVE high -RESET_ASYNC_NAME arst_n -RESET_ASYNC_ACTIVE low -ENABLE_NAME {} -ENABLE_ACTIVE high}}
+# /CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND sync -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME {} -ENABLE_ACTIVE high}}
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_HIGH_TIME 10.00 -CLOCK_OFFSET 0.000000 -CLOCK_UNCERTAINTY 0.0 -RESET_KIND async -RESET_SYNC_NAME rst -RESET_SYNC_ACTIVE high -RESET_ASYNC_NAME arst_n -RESET_ASYNC_ACTIVE low -ENABLE_NAME {} -ENABLE_ACTIVE high}}
+# /CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME {} -ENABLE_ACTIVE high}}
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_HIGH_TIME 10.00 -CLOCK_OFFSET 0.000000 -CLOCK_UNCERTAINTY 0.0 -RESET_KIND async -RESET_SYNC_NAME rst -RESET_SYNC_ACTIVE high -RESET_ASYNC_NAME arst_n -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+# /CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -DESIGN_HIERARCHY sobel
+# /DESIGN_HIERARCHY sobel
+go compile
+# Info: Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+# Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
+# Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49)
+# Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49)
+# Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49)
+# Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49)
+# Generating synthesis internal form... (CIN-3)
+# $PROJECT_HOME/sobel.cpp(50): Found top design routine 'sobel' specified by directive (CIN-52)
+# $PROJECT_HOME/sobel.cpp(50): Synthesizing routine 'sobel' (CIN-13)
+# $PROJECT_HOME/sobel.cpp(50): Inlining routine 'sobel' (CIN-14)
+# $PROJECT_HOME/shift_class.h(13): Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(32): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(80): Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/sobel.cpp(50): Optimizing block '/sobel' ... (CIN-4)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vin' is only used as an input. (OPT-10)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vout' is only used as an output. (OPT-11)
+# Info: Optimizing partition '/sobel': (Total ops = 383, Real ops = 92, Vars = 82) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 383, Real ops = 92, Vars = 80) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 363, Real ops = 88, Vars = 83) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 363, Real ops = 88, Vars = 85) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 363, Real ops = 88, Vars = 85) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 363, Real ops = 88, Vars = 83) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 318, Real ops = 87, Vars = 66) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 302, Real ops = 87, Vars = 65) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 302, Real ops = 87, Vars = 65) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 302, Real ops = 87, Vars = 67) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 302, Real ops = 87, Vars = 67) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 291, Real ops = 85, Vars = 94) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 306, Real ops = 85, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 306, Real ops = 85, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 306, Real ops = 85, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 306, Real ops = 85, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 306, Real ops = 85, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 306, Real ops = 85, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 306, Real ops = 85, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 306, Real ops = 85, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 306, Real ops = 85, Vars = 21) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(68): Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(78): Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(93): Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(69): Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(70): Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(71): Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+# Info: Optimizing partition '/sobel/core': (Total ops = 325, Real ops = 85, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 272, Real ops = 81, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 272, Real ops = 81, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 268, Real ops = 81, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 266, Real ops = 81, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 266, Real ops = 81, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 266, Real ops = 81, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 266, Real ops = 81, Vars = 22) (SOL-10)
+# Design 'sobel' was read (SOL-1)
+# Info: Completed transformation 'compile' on solution 'sobel.v1': elapsed time 1.64 seconds, memory usage 173676kB, peak memory usage 279044kB (SOL-9)
+directive set /sobel/vin -STREAM 90
+# /sobel/vin/STREAM 90
+directive set /sobel/vout -STREAM 30
+# /sobel/vout/STREAM 30
+directive set /sobel/core/main -PIPELINE_INIT_INTERVAL 1
+# /sobel/core/main/PIPELINE_INIT_INTERVAL 1
+directive set /sobel/core/main -DISTRIBUTED_PIPELINE true
+# /sobel/core/main/DISTRIBUTED_PIPELINE true
+directive set /sobel/core/main/FRAME/SHIFT -UNROLL yes
+# /sobel/core/main/FRAME/SHIFT/UNROLL yes
+directive set /sobel/core/main/FRAME/ACC1 -UNROLL yes
+# /sobel/core/main/FRAME/ACC1/UNROLL yes
+directive set /sobel/core/main/FRAME/ACC2 -UNROLL yes
+# /sobel/core/main/FRAME/ACC2/UNROLL yes
+go extract
+# Info: Starting transformation 'architect' on solution 'sobel.v1' (SOL-8)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(78): Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(93): Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+# Info: Optimizing partition '/sobel/core': (Total ops = 455, Real ops = 144, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 265, Real ops = 81, Vars = 14) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 262, Real ops = 81, Vars = 13) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 262, Real ops = 81, Vars = 13) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 268, Real ops = 81, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 250, Real ops = 81, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 244, Real ops = 75, Vars = 19) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(50): Loop '/sobel/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/sobel': (Total ops = 244, Real ops = 75, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 244, Real ops = 75, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 244, Real ops = 75, Vars = 24) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+# Info: Optimizing partition '/sobel': (Total ops = 244, Real ops = 75, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 244, Real ops = 75, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 244, Real ops = 75, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 244, Real ops = 75, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 238, Real ops = 75, Vars = 32) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 241, Real ops = 75, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 198, Real ops = 54, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 199, Real ops = 56, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 199, Real ops = 56, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 199, Real ops = 56, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 199, Real ops = 56, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 202, Real ops = 56, Vars = 13) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 307, Real ops = 60, Vars = 76) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 206, Real ops = 58, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 205, Real ops = 58, Vars = 15) (SOL-10)
+# Design 'sobel' contains '104' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'sobel.v1': elapsed time 2.11 seconds, memory usage 174460kB, peak memory usage 279044kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'sobel.v1' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 307200, Area (Datapath, Register, Total) = 2560.33, 0.00, 2560.33 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 307200, Area (Datapath, Register, Total) = 2559.59, 0.00, 2559.59 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 307200, Area (Datapath, Register, Total) = 2531.89, 0.00, 2531.89 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 307200, Area (Datapath, Register, Total) = 2531.89, 0.00, 2531.89 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'sobel.v1': elapsed time 0.33 seconds, memory usage 174920kB, peak memory usage 279044kB (SOL-9)
+# Info: Starting transformation 'schedule' on solution 'sobel.v1' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Warning: Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+# Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/sobel': (Total ops = 332, Real ops = 105, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 322, Real ops = 104, Vars = 32) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 317, Real ops = 104, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 282, Real ops = 94, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 296, Real ops = 94, Vars = 38) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 287, Real ops = 94, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 282, Real ops = 94, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 296, Real ops = 94, Vars = 38) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 287, Real ops = 94, Vars = 31) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Info: Completed transformation 'schedule' on solution 'sobel.v1': elapsed time 0.98 seconds, memory usage 184552kB, peak memory usage 279044kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'sobel.v1' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/sobel': (Total ops = 437, Real ops = 102, Vars = 215) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 428, Real ops = 102, Vars = 208) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 526, Real ops = 104, Vars = 36) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 517, Real ops = 104, Vars = 29) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 307, Real ops = 110, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 298, Real ops = 110, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 307, Real ops = 110, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 298, Real ops = 110, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 298, Real ops = 110, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 307, Real ops = 110, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 307, Real ops = 110, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 298, Real ops = 110, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 307, Real ops = 110, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 298, Real ops = 110, Vars = 35) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'sobel.v1': elapsed time 0.33 seconds, memory usage 184552kB, peak memory usage 279044kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'sobel.v1' (SOL-8)
+# Warning: Reassigned operation FRAME:acc:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,11,1,12) (ASG-1)
+# Warning: Reassigned operation FRAME:acc#61:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,0,11,1,12) (ASG-1)
+# Warning: Reassigned operation FRAME:acc#47:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5) (ASG-1)
+# Warning: Reassigned operation FRAME:acc#55:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5) (ASG-1)
+# Warning: Reassigned operation FRAME:acc#49:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(5,0,5,0,5) (ASG-1)
+# Warning: Reassigned operation FRAME:acc#60:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add_pipe(16,1,16,0,17,1,1,0,0,0,2,0,0,0) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,3,0,5) (ASG-1)
+# Info: Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 308) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 301) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 43) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 308) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 301) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 308) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 301) (SOL-10)
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Info: Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 308) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 301) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 48) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 41) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 311, Real ops = 114, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 302, Real ops = 114, Vars = 35) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v1/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Info: Completed transformation 'extract' on solution 'sobel.v1': elapsed time 3.39 seconds, memory usage 184552kB, peak memory usage 279044kB (SOL-9)
+# File '$PROJECT_HOME/sobel.h' saved
+# Input file has changed
+go new
+solution file set {$PROJECT_HOME/sobel.h} -recurse -updated
+# Info: Branching solution 'solution.v1' at state 'new' (PRJ-2)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Error: $PROJECT_HOME/sobel.cpp(101): $PROJECT_HOME/sobel.cpp(101): label "ACC1" has already been defined (CRD-247)
+# Error: $PROJECT_HOME/sobel.cpp(117): $PROJECT_HOME/sobel.cpp(117): label "ACC2" has already been defined (CRD-247)
+# Warning: $PROJECT_HOME/sobel.cpp(156): $PROJECT_HOME/sobel.cpp(156): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# Error: Compilation aborted (CIN-5)
+# Error: go analyze: Failed analyze
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(146): $PROJECT_HOME/sobel.cpp(146): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# $PROJECT_HOME/sobel.cpp(49): Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+# Source file analysis completed (CIN-68)
+# Info: Completed transformation 'analyze' on solution 'solution.v1': elapsed time 2.98 seconds, memory usage 181920kB, peak memory usage 304392kB (SOL-9)
+# Info: Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+# Generating synthesis internal form... (CIN-3)
+# $PROJECT_HOME/sobel.cpp(50): Found top design routine 'sobel' specified by directive (CIN-52)
+# $PROJECT_HOME/sobel.cpp(50): Synthesizing routine 'sobel' (CIN-13)
+# $PROJECT_HOME/sobel.cpp(50): Inlining routine 'sobel' (CIN-14)
+# $PROJECT_HOME/shift_class.h(13): Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(32): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(80): Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(96): Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/sobel.cpp(50): Optimizing block '/sobel' ... (CIN-4)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vin' is only used as an input. (OPT-10)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vout' is only used as an output. (OPT-11)
+# Info: Optimizing partition '/sobel': (Total ops = 504, Real ops = 116, Vars = 110) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 504, Real ops = 116, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 464, Real ops = 108, Vars = 114) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 464, Real ops = 108, Vars = 116) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 464, Real ops = 108, Vars = 116) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 464, Real ops = 108, Vars = 114) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 400, Real ops = 107, Vars = 97) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 375, Real ops = 107, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 375, Real ops = 107, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 375, Real ops = 107, Vars = 98) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 375, Real ops = 107, Vars = 98) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 355, Real ops = 105, Vars = 146) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(68): Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(78): Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(94): Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(110): Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(69): Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(70): Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(71): Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+# Info: Optimizing partition '/sobel/core': (Total ops = 392, Real ops = 104, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 303, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 303, Real ops = 94, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 298, Real ops = 94, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+# Design 'sobel' was read (SOL-1)
+# Info: Completed transformation 'compile' on solution 'sobel.v2': elapsed time 1.90 seconds, memory usage 184324kB, peak memory usage 304392kB (SOL-9)
+# Info: Starting transformation 'architect' on solution 'sobel.v2' (SOL-8)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(78): Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(94): Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(110): Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+# Info: Optimizing partition '/sobel/core': (Total ops = 484, Real ops = 157, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 294, Real ops = 94, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 291, Real ops = 94, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 291, Real ops = 94, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 303, Real ops = 94, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 94, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 282, Real ops = 91, Vars = 19) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(50): Loop '/sobel/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/sobel': (Total ops = 282, Real ops = 91, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+# Info: Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 267, Real ops = 91, Vars = 32) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 270, Real ops = 91, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 227, Real ops = 88, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 227, Real ops = 88, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 227, Real ops = 88, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 227, Real ops = 88, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 234, Real ops = 89, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 233, Real ops = 89, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 483, Real ops = 120, Vars = 171) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 277, Real ops = 106, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 276, Real ops = 106, Vars = 49) (SOL-10)
+# Design 'sobel' contains '156' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'sobel.v2': elapsed time 3.10 seconds, memory usage 184672kB, peak memory usage 304392kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'sobel.v2' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 5175.50, 0.00, 5175.50 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5172.06, 0.00, 5172.06 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5121.26, 0.00, 5121.26 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 5121.26, 0.00, 5121.26 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'sobel.v2': elapsed time 0.48 seconds, memory usage 184692kB, peak memory usage 304392kB (SOL-9)
+# Info: Starting transformation 'schedule' on solution 'sobel.v2' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Warning: Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+# Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/sobel': (Total ops = 441, Real ops = 157, Vars = 120) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 431, Real ops = 156, Vars = 112) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 411, Real ops = 156, Vars = 115) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 373, Real ops = 152, Vars = 85) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 366, Real ops = 151, Vars = 84) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 380, Real ops = 151, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 371, Real ops = 151, Vars = 89) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 370, Real ops = 151, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 369, Real ops = 151, Vars = 88) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 383, Real ops = 151, Vars = 100) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 374, Real ops = 151, Vars = 93) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 369, Real ops = 151, Vars = 88) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 383, Real ops = 151, Vars = 100) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 374, Real ops = 151, Vars = 93) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Info: Completed transformation 'schedule' on solution 'sobel.v2': elapsed time 1.78 seconds, memory usage 195488kB, peak memory usage 304392kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'sobel.v2' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/sobel': (Total ops = 645, Real ops = 191, Vars = 448) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 636, Real ops = 191, Vars = 441) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 567, Real ops = 190, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 558, Real ops = 190, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'sobel.v2': elapsed time 0.40 seconds, memory usage 195488kB, peak memory usage 304392kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'sobel.v2' (SOL-8)
+# Warning: Reassigned operation ACC1:acc#61:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#69:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#65:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+# Warning: Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#62:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#70:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#66:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+# Info: Optimizing partition '/sobel': (Total ops = 457, Real ops = 215, Vars = 454) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 448, Real ops = 215, Vars = 447) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 78) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 71) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 415, Real ops = 196, Vars = 412) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 406, Real ops = 196, Vars = 405) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 415, Real ops = 196, Vars = 412) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 406, Real ops = 196, Vars = 405) (SOL-10)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Input file has changed
+go new
+solution file set {$PROJECT_HOME/sobel.cpp} -updated
+# Info: Branching solution 'solution.v1' at state 'new' (PRJ-2)
+# Info: Optimizing partition '/sobel': (Total ops = 415, Real ops = 196, Vars = 412) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 406, Real ops = 196, Vars = 405) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 322, Real ops = 174, Vars = 78) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 313, Real ops = 174, Vars = 71) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 322, Real ops = 174, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 313, Real ops = 174, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 322, Real ops = 174, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 313, Real ops = 174, Vars = 68) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v2/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Info: Completed transformation 'extract' on solution 'sobel.v2': elapsed time 5.79 seconds, memory usage 195488kB, peak memory usage 304392kB (SOL-9)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# Input file has changed
+go new
+solution file set {$PROJECT_HOME/sobel.cpp} -updated
+# Info: Branching solution 'solution.v2' at state 'new' (PRJ-2)
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(146): $PROJECT_HOME/sobel.cpp(146): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# $PROJECT_HOME/sobel.cpp(49): Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+# Source file analysis completed (CIN-68)
+# Info: Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.09 seconds, memory usage 192856kB, peak memory usage 315340kB (SOL-9)
+# Info: Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+# Generating synthesis internal form... (CIN-3)
+# $PROJECT_HOME/sobel.cpp(50): Found top design routine 'sobel' specified by directive (CIN-52)
+# $PROJECT_HOME/sobel.cpp(50): Synthesizing routine 'sobel' (CIN-13)
+# $PROJECT_HOME/sobel.cpp(50): Inlining routine 'sobel' (CIN-14)
+# $PROJECT_HOME/shift_class.h(13): Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(32): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(80): Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(96): Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/sobel.cpp(50): Optimizing block '/sobel' ... (CIN-4)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vin' is only used as an input. (OPT-10)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vout' is only used as an output. (OPT-11)
+# Info: Optimizing partition '/sobel': (Total ops = 504, Real ops = 116, Vars = 110) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 504, Real ops = 116, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 464, Real ops = 108, Vars = 114) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 464, Real ops = 108, Vars = 116) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 464, Real ops = 108, Vars = 116) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 464, Real ops = 108, Vars = 114) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 400, Real ops = 107, Vars = 97) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 375, Real ops = 107, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 375, Real ops = 107, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 375, Real ops = 107, Vars = 98) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 375, Real ops = 107, Vars = 98) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 355, Real ops = 105, Vars = 146) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 352, Real ops = 105, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 352, Real ops = 105, Vars = 25) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(68): Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(78): Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(94): Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(110): Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(69): Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(70): Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(71): Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+# Info: Optimizing partition '/sobel/core': (Total ops = 392, Real ops = 104, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 303, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 303, Real ops = 94, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 298, Real ops = 94, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+# Design 'sobel' was read (SOL-1)
+# Info: Completed transformation 'compile' on solution 'sobel.v3': elapsed time 2.14 seconds, memory usage 197424kB, peak memory usage 315340kB (SOL-9)
+# Info: Starting transformation 'architect' on solution 'sobel.v3' (SOL-8)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(78): Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(94): Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(110): Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+# Info: Optimizing partition '/sobel/core': (Total ops = 484, Real ops = 157, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 294, Real ops = 94, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 291, Real ops = 94, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 291, Real ops = 94, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 303, Real ops = 94, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 94, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 282, Real ops = 91, Vars = 19) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(50): Loop '/sobel/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/sobel': (Total ops = 282, Real ops = 91, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+# Info: Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 285, Real ops = 91, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 285, Real ops = 91, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 267, Real ops = 91, Vars = 32) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 270, Real ops = 91, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 227, Real ops = 88, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 227, Real ops = 88, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 227, Real ops = 88, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 227, Real ops = 88, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 234, Real ops = 89, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 233, Real ops = 89, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 483, Real ops = 120, Vars = 171) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 277, Real ops = 106, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 276, Real ops = 106, Vars = 49) (SOL-10)
+# Design 'sobel' contains '156' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'sobel.v3': elapsed time 4.01 seconds, memory usage 197796kB, peak memory usage 315340kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'sobel.v3' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 5175.50, 0.00, 5175.50 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5172.06, 0.00, 5172.06 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5121.26, 0.00, 5121.26 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 5121.26, 0.00, 5121.26 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'sobel.v3': elapsed time 0.58 seconds, memory usage 197796kB, peak memory usage 315340kB (SOL-9)
+# Info: Starting transformation 'schedule' on solution 'sobel.v3' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Warning: Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+# Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/sobel': (Total ops = 441, Real ops = 157, Vars = 120) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 431, Real ops = 156, Vars = 112) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 411, Real ops = 156, Vars = 115) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 373, Real ops = 152, Vars = 85) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 366, Real ops = 151, Vars = 84) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 380, Real ops = 151, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 371, Real ops = 151, Vars = 89) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 370, Real ops = 151, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 369, Real ops = 151, Vars = 88) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 383, Real ops = 151, Vars = 100) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 374, Real ops = 151, Vars = 93) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 369, Real ops = 151, Vars = 88) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 383, Real ops = 151, Vars = 100) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 374, Real ops = 151, Vars = 93) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Info: Completed transformation 'schedule' on solution 'sobel.v3': elapsed time 1.89 seconds, memory usage 203124kB, peak memory usage 315340kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'sobel.v3' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/sobel': (Total ops = 645, Real ops = 191, Vars = 448) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 636, Real ops = 191, Vars = 441) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 567, Real ops = 190, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 558, Real ops = 190, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 190, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 348, Real ops = 190, Vars = 68) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'sobel.v3': elapsed time 0.42 seconds, memory usage 203124kB, peak memory usage 315340kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'sobel.v3' (SOL-8)
+# Warning: Reassigned operation ACC1:acc#61:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#69:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#65:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+# Warning: Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#62:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#70:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#66:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+# Info: Optimizing partition '/sobel': (Total ops = 457, Real ops = 215, Vars = 454) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 448, Real ops = 215, Vars = 447) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 78) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 71) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 327, Real ops = 174, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 318, Real ops = 174, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 415, Real ops = 196, Vars = 412) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 406, Real ops = 196, Vars = 405) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 415, Real ops = 196, Vars = 412) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 406, Real ops = 196, Vars = 405) (SOL-10)
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Info: Optimizing partition '/sobel': (Total ops = 415, Real ops = 196, Vars = 412) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 406, Real ops = 196, Vars = 405) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 322, Real ops = 174, Vars = 78) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 313, Real ops = 174, Vars = 71) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 322, Real ops = 174, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 313, Real ops = 174, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 322, Real ops = 174, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 313, Real ops = 174, Vars = 68) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v3/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Info: Completed transformation 'extract' on solution 'sobel.v3': elapsed time 5.87 seconds, memory usage 203124kB, peak memory usage 315340kB (SOL-9)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# Input file has changed
+go new
+solution file set {$PROJECT_HOME/sobel.cpp} -updated
+# Info: Branching solution 'solution.v2' at state 'new' (PRJ-2)
+# File '$PROJECT_HOME/sobel.cpp' saved
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(146): $PROJECT_HOME/sobel.cpp(146): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(46): $PROJECT_HOME/sobel.h(46): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# $PROJECT_HOME/sobel.cpp(49): Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+# Source file analysis completed (CIN-68)
+# Info: Completed transformation 'analyze' on solution 'solution.v2': elapsed time 2.75 seconds, memory usage 211704kB, peak memory usage 327424kB (SOL-9)
+# Info: Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+# Generating synthesis internal form... (CIN-3)
+# $PROJECT_HOME/sobel.cpp(50): Found top design routine 'sobel' specified by directive (CIN-52)
+# $PROJECT_HOME/sobel.cpp(50): Synthesizing routine 'sobel' (CIN-13)
+# $PROJECT_HOME/sobel.cpp(50): Inlining routine 'sobel' (CIN-14)
+# $PROJECT_HOME/shift_class.h(13): Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(32): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(80): Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(96): Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/sobel.cpp(50): Optimizing block '/sobel' ... (CIN-4)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vin' is only used as an input. (OPT-10)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vout' is only used as an output. (OPT-11)
+# Info: Optimizing partition '/sobel': (Total ops = 531, Real ops = 128, Vars = 107) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 531, Real ops = 128, Vars = 105) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 491, Real ops = 120, Vars = 111) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 491, Real ops = 120, Vars = 113) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 491, Real ops = 120, Vars = 113) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 491, Real ops = 120, Vars = 111) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 421, Real ops = 119, Vars = 94) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 396, Real ops = 119, Vars = 93) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 396, Real ops = 119, Vars = 93) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 396, Real ops = 119, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 396, Real ops = 119, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 376, Real ops = 117, Vars = 137) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 350, Real ops = 111, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 350, Real ops = 111, Vars = 29) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 350, Real ops = 111, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 350, Real ops = 111, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 350, Real ops = 111, Vars = 29) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 350, Real ops = 111, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 350, Real ops = 111, Vars = 29) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 350, Real ops = 111, Vars = 29) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 350, Real ops = 111, Vars = 27) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(68): Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(78): Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(94): Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(110): Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(69): Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(70): Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(71): Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+# Info: Optimizing partition '/sobel/core': (Total ops = 390, Real ops = 110, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 301, Real ops = 100, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 301, Real ops = 100, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 296, Real ops = 100, Vars = 30) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 293, Real ops = 100, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 293, Real ops = 100, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 293, Real ops = 100, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 293, Real ops = 100, Vars = 27) (SOL-10)
+# Design 'sobel' was read (SOL-1)
+# Info: Completed transformation 'compile' on solution 'sobel.v4': elapsed time 2.40 seconds, memory usage 207912kB, peak memory usage 327424kB (SOL-9)
+# Info: Starting transformation 'architect' on solution 'sobel.v4' (SOL-8)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(78): Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(94): Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(110): Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+# Info: Optimizing partition '/sobel/core': (Total ops = 482, Real ops = 163, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 292, Real ops = 100, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 289, Real ops = 100, Vars = 18) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 289, Real ops = 100, Vars = 18) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 100, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 100, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 280, Real ops = 97, Vars = 21) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(50): Loop '/sobel/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/sobel': (Total ops = 280, Real ops = 97, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 280, Real ops = 97, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 280, Real ops = 97, Vars = 26) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+# Info: Optimizing partition '/sobel': (Total ops = 280, Real ops = 97, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 280, Real ops = 97, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 280, Real ops = 97, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 280, Real ops = 97, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 262, Real ops = 97, Vars = 34) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 262, Real ops = 97, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 222, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 222, Real ops = 94, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 222, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 222, Real ops = 94, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 229, Real ops = 95, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 228, Real ops = 95, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 496, Real ops = 128, Vars = 183) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 272, Real ops = 112, Vars = 52) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 271, Real ops = 112, Vars = 51) (SOL-10)
+# Design 'sobel' contains '156' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'sobel.v4': elapsed time 4.82 seconds, memory usage 208208kB, peak memory usage 327424kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'sobel.v4' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 5135.97, 0.00, 5135.97 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5134.54, 0.00, 5134.54 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5106.69, 0.00, 5106.69 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 5100.36, 0.00, 5100.36 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 5100.36, 0.00, 5100.36 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'sobel.v4': elapsed time 0.69 seconds, memory usage 208316kB, peak memory usage 327424kB (SOL-9)
+# Info: Starting transformation 'schedule' on solution 'sobel.v4' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Warning: Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+# Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/sobel': (Total ops = 430, Real ops = 157, Vars = 104) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 420, Real ops = 156, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 400, Real ops = 156, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 366, Real ops = 151, Vars = 71) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 359, Real ops = 150, Vars = 70) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 373, Real ops = 150, Vars = 82) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 364, Real ops = 150, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 361, Real ops = 150, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 360, Real ops = 150, Vars = 70) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 374, Real ops = 150, Vars = 82) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 365, Real ops = 150, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 360, Real ops = 150, Vars = 70) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 374, Real ops = 150, Vars = 82) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 365, Real ops = 150, Vars = 75) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Info: Completed transformation 'schedule' on solution 'sobel.v4': elapsed time 1.89 seconds, memory usage 212032kB, peak memory usage 327424kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'sobel.v4' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/sobel': (Total ops = 646, Real ops = 183, Vars = 414) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 637, Real ops = 183, Vars = 407) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 577, Real ops = 173, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 568, Real ops = 173, Vars = 65) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 345, Real ops = 173, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 336, Real ops = 173, Vars = 65) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 345, Real ops = 173, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 336, Real ops = 173, Vars = 65) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 336, Real ops = 173, Vars = 65) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 345, Real ops = 173, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 345, Real ops = 173, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 336, Real ops = 173, Vars = 65) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 345, Real ops = 173, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 336, Real ops = 173, Vars = 65) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'sobel.v4': elapsed time 0.41 seconds, memory usage 212168kB, peak memory usage 327424kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'sobel.v4' (SOL-8)
+# Warning: Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#67:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#59:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#63:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(15,0,11,1,15) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#66:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#58:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#62:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,1,2) (ASG-1)
+# Warning: Reassigned operation FRAME:acc#45:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5) (ASG-1)
+# Warning: Reassigned operation FRAME:acc#43:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5) (ASG-1)
+# Warning: Reassigned operation FRAME:acc#44:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,1,4,1,5) (ASG-1)
+# Info: Optimizing partition '/sobel': (Total ops = 442, Real ops = 200, Vars = 439) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 433, Real ops = 200, Vars = 432) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 329, Real ops = 164, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 320, Real ops = 164, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 329, Real ops = 164, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 320, Real ops = 164, Vars = 65) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 320, Real ops = 164, Vars = 65) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 329, Real ops = 164, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 329, Real ops = 164, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 320, Real ops = 164, Vars = 65) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 329, Real ops = 164, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 320, Real ops = 164, Vars = 65) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 414, Real ops = 188, Vars = 411) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 405, Real ops = 188, Vars = 404) (SOL-10)
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Info: Optimizing partition '/sobel': (Total ops = 414, Real ops = 188, Vars = 411) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 405, Real ops = 188, Vars = 404) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 324, Real ops = 164, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 315, Real ops = 164, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 324, Real ops = 164, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 315, Real ops = 164, Vars = 65) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 324, Real ops = 164, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 315, Real ops = 164, Vars = 65) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v4/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Info: Completed transformation 'extract' on solution 'sobel.v4': elapsed time 5.65 seconds, memory usage 212732kB, peak memory usage 327424kB (SOL-9)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# Input file has changed
+go new
+solution file set {$PROJECT_HOME/sobel.cpp} -updated
+# Info: Branching solution 'solution.v2' at state 'new' (PRJ-2)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.h' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(130): $PROJECT_HOME/sobel.cpp(130): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# $PROJECT_HOME/sobel.cpp(49): Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+# Source file analysis completed (CIN-68)
+# Info: Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.26 seconds, memory usage 216924kB, peak memory usage 339848kB (SOL-9)
+# Info: Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+# Generating synthesis internal form... (CIN-3)
+# $PROJECT_HOME/sobel.cpp(50): Found top design routine 'sobel' specified by directive (CIN-52)
+# $PROJECT_HOME/sobel.cpp(50): Synthesizing routine 'sobel' (CIN-13)
+# $PROJECT_HOME/sobel.cpp(50): Inlining routine 'sobel' (CIN-14)
+# $PROJECT_HOME/shift_class.h(13): Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(32): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(80): Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+# Warning: $PROJECT_HOME/sobel.cpp(80): Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/sobel.cpp(50): Optimizing block '/sobel' ... (CIN-4)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vin' is only used as an input. (OPT-10)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vout' is only used as an output. (OPT-11)
+# Info: Optimizing partition '/sobel': (Total ops = 454, Real ops = 107, Vars = 89) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 454, Real ops = 107, Vars = 87) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 395, Real ops = 93, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 395, Real ops = 93, Vars = 94) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 395, Real ops = 93, Vars = 94) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 395, Real ops = 93, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 340, Real ops = 92, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 324, Real ops = 92, Vars = 74) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 324, Real ops = 92, Vars = 74) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 324, Real ops = 92, Vars = 76) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 324, Real ops = 92, Vars = 76) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 313, Real ops = 90, Vars = 103) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 328, Real ops = 86, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 328, Real ops = 86, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 328, Real ops = 86, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 328, Real ops = 86, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 328, Real ops = 86, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 328, Real ops = 86, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 328, Real ops = 86, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 328, Real ops = 86, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 328, Real ops = 86, Vars = 23) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(68): Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(78): Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(94): Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(69): Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(70): Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(71): Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+# Info: Optimizing partition '/sobel/core': (Total ops = 361, Real ops = 86, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 268, Real ops = 72, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 268, Real ops = 72, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 264, Real ops = 72, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 262, Real ops = 72, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 262, Real ops = 72, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 262, Real ops = 72, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 262, Real ops = 72, Vars = 23) (SOL-10)
+# Design 'sobel' was read (SOL-1)
+# Info: Completed transformation 'compile' on solution 'sobel.v5': elapsed time 2.76 seconds, memory usage 217440kB, peak memory usage 339848kB (SOL-9)
+# Info: Starting transformation 'architect' on solution 'sobel.v5' (SOL-8)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(78): Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(94): Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+# Info: Optimizing partition '/sobel/core': (Total ops = 433, Real ops = 135, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 252, Real ops = 72, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 234, Real ops = 57, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 234, Real ops = 57, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 161, Real ops = 30, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 137, Real ops = 30, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 134, Real ops = 27, Vars = 13) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(50): Loop '/sobel/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/sobel': (Total ops = 134, Real ops = 27, Vars = 18) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 134, Real ops = 27, Vars = 15) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 134, Real ops = 27, Vars = 13) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 134, Real ops = 27, Vars = 18) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 134, Real ops = 27, Vars = 13) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 134, Real ops = 27, Vars = 18) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+# Info: Optimizing partition '/sobel': (Total ops = 134, Real ops = 27, Vars = 18) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 134, Real ops = 27, Vars = 13) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 134, Real ops = 27, Vars = 13) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 134, Real ops = 27, Vars = 18) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 128, Real ops = 27, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 132, Real ops = 27, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 107, Real ops = 20, Vars = 11) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 107, Real ops = 20, Vars = 11) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 107, Real ops = 20, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 107, Real ops = 20, Vars = 11) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 107, Real ops = 20, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 110, Real ops = 20, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 209, Real ops = 24, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 114, Real ops = 22, Vars = 15) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 113, Real ops = 22, Vars = 14) (SOL-10)
+# Design 'sobel' contains '55' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'sobel.v5': elapsed time 5.57 seconds, memory usage 217692kB, peak memory usage 339848kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'sobel.v5' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 307200, Area (Datapath, Register, Total) = 677.70, 0.00, 677.70 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 307200, Area (Datapath, Register, Total) = 675.96, 0.00, 675.96 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 307200, Area (Datapath, Register, Total) = 670.96, 0.00, 670.96 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 307200, Area (Datapath, Register, Total) = 668.89, 0.00, 668.89 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 307200, Area (Datapath, Register, Total) = 668.89, 0.00, 668.89 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'sobel.v5': elapsed time 0.34 seconds, memory usage 217892kB, peak memory usage 339848kB (SOL-9)
+# Info: Starting transformation 'schedule' on solution 'sobel.v5' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Warning: Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+# Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/sobel': (Total ops = 184, Real ops = 56, Vars = 36) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 174, Real ops = 55, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 169, Real ops = 55, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 123, Real ops = 39, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 137, Real ops = 39, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 39, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 123, Real ops = 39, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 137, Real ops = 39, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 39, Vars = 21) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Info: Completed transformation 'schedule' on solution 'sobel.v5': elapsed time 0.86 seconds, memory usage 219240kB, peak memory usage 339848kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'sobel.v5' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/sobel': (Total ops = 205, Real ops = 47, Vars = 127) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 196, Real ops = 47, Vars = 120) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 250, Real ops = 47, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 241, Real ops = 47, Vars = 18) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 138, Real ops = 50, Vars = 29) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 129, Real ops = 50, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 138, Real ops = 50, Vars = 29) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 129, Real ops = 50, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'sobel.v5': elapsed time 0.23 seconds, memory usage 219620kB, peak memory usage 339848kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'sobel.v5' (SOL-8)
+# Info: Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 134) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 127) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 134) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 127) (SOL-10)
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Info: Optimizing partition '/sobel': (Total ops = 137, Real ops = 49, Vars = 134) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 128, Real ops = 49, Vars = 127) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 139, Real ops = 49, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 130, Real ops = 49, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 139, Real ops = 49, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 130, Real ops = 49, Vars = 21) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v5/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Info: Completed transformation 'extract' on solution 'sobel.v5': elapsed time 3.42 seconds, memory usage 219996kB, peak memory usage 339848kB (SOL-9)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# Input file has changed
+go new
+solution file set {$PROJECT_HOME/sobel.cpp} -updated
+# Info: Branching solution 'solution.v2' at state 'new' (PRJ-2)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Error: $PROJECT_HOME/sobel.cpp(52): $PROJECT_HOME/sobel.cpp(52): "intensity" has already been declared in the current scope (CRD-101)
+# Error: $PROJECT_HOME/sobel.cpp(68): $PROJECT_HOME/sobel.cpp(68): expression must be a modifiable lvalue (CRD-137)
+# Error: $PROJECT_HOME/sobel.cpp(104): $PROJECT_HOME/sobel.cpp(104): expression must be a modifiable lvalue (CRD-137)
+# Error: $PROJECT_HOME/sobel.cpp(111): $PROJECT_HOME/sobel.cpp(111): expression must be a modifiable lvalue (CRD-137)
+# Warning: $PROJECT_HOME/sobel.cpp(137): $PROJECT_HOME/sobel.cpp(137): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# Error: Compilation aborted (CIN-5)
+# Error: go analyze: Failed analyze
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+go allocate
+# Info: Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(137): $PROJECT_HOME/sobel.cpp(137): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# $PROJECT_HOME/sobel.cpp(49): Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+# Source file analysis completed (CIN-68)
+# Info: Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.14 seconds, memory usage 217816kB, peak memory usage 349092kB (SOL-9)
+# Info: Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+# Generating synthesis internal form... (CIN-3)
+# $PROJECT_HOME/sobel.cpp(50): Found top design routine 'sobel' specified by directive (CIN-52)
+# $PROJECT_HOME/sobel.cpp(50): Synthesizing routine 'sobel' (CIN-13)
+# $PROJECT_HOME/sobel.cpp(50): Inlining routine 'sobel' (CIN-14)
+# $PROJECT_HOME/shift_class.h(13): Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(32): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(82): Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+# Warning: $PROJECT_HOME/sobel.cpp(82): Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/sobel.cpp(50): Optimizing block '/sobel' ... (CIN-4)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vin' is only used as an input. (OPT-10)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vout' is only used as an output. (OPT-11)
+# Info: Optimizing partition '/sobel': (Total ops = 784, Real ops = 193, Vars = 149) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 784, Real ops = 193, Vars = 147) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 741, Real ops = 183, Vars = 151) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 741, Real ops = 183, Vars = 153) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 741, Real ops = 183, Vars = 153) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 741, Real ops = 183, Vars = 151) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 541, Real ops = 140, Vars = 114) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 525, Real ops = 140, Vars = 113) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 525, Real ops = 140, Vars = 113) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 525, Real ops = 140, Vars = 115) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 525, Real ops = 140, Vars = 115) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 515, Real ops = 138, Vars = 143) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 696, Real ops = 130, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 696, Real ops = 130, Vars = 29) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 696, Real ops = 130, Vars = 30) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 696, Real ops = 130, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 696, Real ops = 130, Vars = 29) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 696, Real ops = 130, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 696, Real ops = 130, Vars = 29) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 696, Real ops = 130, Vars = 29) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 696, Real ops = 130, Vars = 27) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(69): Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(80): Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(99): Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(70): Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(71): Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(72): Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(73): Detected constant initialization of array 'in', optimizing loop 'RESET' (LOOP-12)
+# Info: Optimizing partition '/sobel/core': (Total ops = 721, Real ops = 130, Vars = 37) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 628, Real ops = 116, Vars = 34) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 628, Real ops = 116, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 628, Real ops = 116, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 624, Real ops = 116, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 622, Real ops = 116, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 622, Real ops = 116, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 622, Real ops = 116, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 622, Real ops = 116, Vars = 33) (SOL-10)
+# Design 'sobel' was read (SOL-1)
+# Info: Completed transformation 'compile' on solution 'sobel.v6': elapsed time 3.40 seconds, memory usage 222280kB, peak memory usage 349092kB (SOL-9)
+# Info: Starting transformation 'architect' on solution 'sobel.v6' (SOL-8)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(80): Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(99): Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1727, Real ops = 311, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1566, Real ops = 252, Vars = 49) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1394, Real ops = 214, Vars = 36) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1394, Real ops = 214, Vars = 36) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1401, Real ops = 214, Vars = 46) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1097, Real ops = 274, Vars = 37) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 256, Vars = 35) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(50): Loop '/sobel/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/sobel': (Total ops = 1047, Real ops = 256, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 256, Vars = 37) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 256, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1047, Real ops = 256, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 256, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1047, Real ops = 256, Vars = 40) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+# Info: Optimizing partition '/sobel': (Total ops = 1047, Real ops = 256, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 256, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 256, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1047, Real ops = 256, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1034, Real ops = 256, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1038, Real ops = 256, Vars = 49) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 702, Real ops = 186, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 589, Real ops = 162, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 589, Real ops = 162, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 589, Real ops = 162, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 589, Real ops = 162, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 592, Real ops = 162, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 761, Real ops = 166, Vars = 122) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 596, Real ops = 164, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 595, Real ops = 164, Vars = 24) (SOL-10)
+# Design 'sobel' contains '297' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'sobel.v6': elapsed time 9.61 seconds, memory usage 222648kB, peak memory usage 349092kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'sobel.v6' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'main' (4 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled SEQUENTIAL 'core' (total length 4 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 307202, Area (Datapath, Register, Total) = 8953.75, 0.00, 8953.75 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 307202, Area (Datapath, Register, Total) = 8953.01, 0.00, 8953.01 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 307202, Area (Datapath, Register, Total) = 8801.09, 0.00, 8801.09 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 307202, Area (Datapath, Register, Total) = 8799.57, 0.00, 8799.57 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 307202, Area (Datapath, Register, Total) = 8799.57, 0.00, 8799.57 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'sobel.v6': elapsed time 3.67 seconds, memory usage 225368kB, peak memory usage 349092kB (SOL-9)
+go extract
+# Info: Starting transformation 'schedule' on solution 'sobel.v6' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Warning: Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+# Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/sobel': (Total ops = 956, Real ops = 298, Vars = 114) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 946, Real ops = 297, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 941, Real ops = 297, Vars = 103) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 904, Real ops = 288, Vars = 85) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 879, Real ops = 288, Vars = 70) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 893, Real ops = 288, Vars = 82) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 884, Real ops = 288, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 879, Real ops = 288, Vars = 70) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 893, Real ops = 288, Vars = 82) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 884, Real ops = 288, Vars = 75) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Info: Completed transformation 'schedule' on solution 'sobel.v6': elapsed time 3.10 seconds, memory usage 256952kB, peak memory usage 349092kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'sobel.v6' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/sobel': (Total ops = 1129, Real ops = 326, Vars = 703) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1120, Real ops = 326, Vars = 696) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1567, Real ops = 329, Vars = 69) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1558, Real ops = 329, Vars = 62) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 909, Real ops = 328, Vars = 69) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 900, Real ops = 328, Vars = 62) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 909, Real ops = 328, Vars = 69) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 900, Real ops = 328, Vars = 62) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 900, Real ops = 328, Vars = 62) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 909, Real ops = 328, Vars = 69) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 909, Real ops = 328, Vars = 69) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 900, Real ops = 328, Vars = 62) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 909, Real ops = 328, Vars = 69) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 900, Real ops = 328, Vars = 62) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'sobel.v6': elapsed time 1.56 seconds, memory usage 257960kB, peak memory usage 349092kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'sobel.v6' (SOL-8)
+# Warning: Reassigned operation ACC1:acc#294:DEFAULT to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,3) (ASG-1)
+# Info: Optimizing partition '/sobel': (Total ops = 931, Real ops = 332, Vars = 928) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 922, Real ops = 332, Vars = 921) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 914, Real ops = 330, Vars = 72) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 905, Real ops = 330, Vars = 65) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 914, Real ops = 330, Vars = 69) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 905, Real ops = 330, Vars = 62) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 904, Real ops = 329, Vars = 62) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 904, Real ops = 329, Vars = 61) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 913, Real ops = 329, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 913, Real ops = 329, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 904, Real ops = 329, Vars = 61) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 913, Real ops = 329, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 904, Real ops = 329, Vars = 61) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 924, Real ops = 331, Vars = 921) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 915, Real ops = 331, Vars = 914) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 924, Real ops = 331, Vars = 921) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 915, Real ops = 331, Vars = 914) (SOL-10)
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Info: Optimizing partition '/sobel': (Total ops = 924, Real ops = 331, Vars = 921) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 915, Real ops = 331, Vars = 914) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 908, Real ops = 329, Vars = 71) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 899, Real ops = 329, Vars = 64) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 908, Real ops = 329, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 899, Real ops = 329, Vars = 61) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 908, Real ops = 329, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 899, Real ops = 329, Vars = 61) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v6/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Info: Completed transformation 'extract' on solution 'sobel.v6': elapsed time 7.89 seconds, memory usage 260480kB, peak memory usage 349092kB (SOL-9)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# Input file has changed
+go new
+solution file set {$PROJECT_HOME/sobel.cpp} -updated
+# Info: Branching solution 'solution.v2' at state 'new' (PRJ-2)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(128): $PROJECT_HOME/sobel.cpp(128): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# $PROJECT_HOME/sobel.cpp(49): Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+# Source file analysis completed (CIN-68)
+# Info: Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.23 seconds, memory usage 269072kB, peak memory usage 388764kB (SOL-9)
+# Info: Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+# Generating synthesis internal form... (CIN-3)
+# $PROJECT_HOME/sobel.cpp(50): Found top design routine 'sobel' specified by directive (CIN-52)
+# $PROJECT_HOME/sobel.cpp(50): Synthesizing routine 'sobel' (CIN-13)
+# $PROJECT_HOME/sobel.cpp(50): Inlining routine 'sobel' (CIN-14)
+# $PROJECT_HOME/shift_class.h(13): Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(32): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(76): Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(86): Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/sobel.cpp(50): Optimizing block '/sobel' ... (CIN-4)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vin' is only used as an input. (OPT-10)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vout' is only used as an output. (OPT-11)
+# Info: Optimizing partition '/sobel': (Total ops = 1035, Real ops = 214, Vars = 224) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1035, Real ops = 214, Vars = 222) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 993, Real ops = 206, Vars = 228) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 993, Real ops = 206, Vars = 230) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 993, Real ops = 206, Vars = 230) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 993, Real ops = 206, Vars = 228) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 937, Real ops = 205, Vars = 215) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 912, Real ops = 205, Vars = 214) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 912, Real ops = 205, Vars = 214) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 912, Real ops = 205, Vars = 216) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 912, Real ops = 205, Vars = 216) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 890, Real ops = 203, Vars = 258) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 39) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(66): Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(74): Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(84): Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(94): Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(67): Detected constant initialization of array 'in', optimizing loop 'RESET' (LOOP-12)
+# Info: Optimizing partition '/sobel/core': (Total ops = 670, Real ops = 125, Vars = 32) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 595, Real ops = 117, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 592, Real ops = 117, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 592, Real ops = 117, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 587, Real ops = 117, Vars = 36) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 584, Real ops = 117, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 584, Real ops = 117, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 584, Real ops = 117, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 584, Real ops = 117, Vars = 33) (SOL-10)
+# Design 'sobel' was read (SOL-1)
+# Info: Completed transformation 'compile' on solution 'sobel.v7': elapsed time 4.54 seconds, memory usage 276108kB, peak memory usage 388764kB (SOL-9)
+# Info: Starting transformation 'architect' on solution 'sobel.v7' (SOL-8)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(74): Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(84): Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(94): Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1539, Real ops = 290, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 971, Real ops = 174, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 970, Real ops = 174, Vars = 39) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 970, Real ops = 174, Vars = 39) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 973, Real ops = 174, Vars = 41) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 968, Real ops = 174, Vars = 41) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 939, Real ops = 187, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 939, Real ops = 187, Vars = 40) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(50): Loop '/sobel/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/sobel': (Total ops = 939, Real ops = 187, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 940, Real ops = 187, Vars = 41) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 940, Real ops = 187, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 940, Real ops = 187, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 940, Real ops = 187, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 940, Real ops = 187, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 48) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 43) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 45) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+# Info: Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 932, Real ops = 187, Vars = 49) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 932, Real ops = 187, Vars = 44) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 913, Real ops = 192, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 913, Real ops = 192, Vars = 47) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 913, Real ops = 192, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 913, Real ops = 192, Vars = 47) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 920, Real ops = 193, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 919, Real ops = 193, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1354, Real ops = 245, Vars = 293) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 987, Real ops = 216, Vars = 83) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 986, Real ops = 216, Vars = 82) (SOL-10)
+# Design 'sobel' contains '439' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'sobel.v7': elapsed time 10.84 seconds, memory usage 276144kB, peak memory usage 388764kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'sobel.v7' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 6857.74, 0.00, 6857.74 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 6767.91, 0.00, 6767.91 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 6764.18, 0.00, 6764.18 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 6764.18, 0.00, 6764.18 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'sobel.v7': elapsed time 4.90 seconds, memory usage 276616kB, peak memory usage 388764kB (SOL-9)
+# Info: Starting transformation 'schedule' on solution 'sobel.v7' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Warning: Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+# Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/sobel': (Total ops = 1561, Real ops = 440, Vars = 122) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1551, Real ops = 439, Vars = 114) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 1542, Real ops = 440, Vars = 129) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 1433, Real ops = 426, Vars = 82) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 1422, Real ops = 425, Vars = 79) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1436, Real ops = 425, Vars = 91) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1427, Real ops = 425, Vars = 84) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 1424, Real ops = 425, Vars = 81) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 1423, Real ops = 425, Vars = 79) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1437, Real ops = 425, Vars = 91) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1428, Real ops = 425, Vars = 84) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 1423, Real ops = 425, Vars = 79) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1437, Real ops = 425, Vars = 91) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1428, Real ops = 425, Vars = 84) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Info: Completed transformation 'schedule' on solution 'sobel.v7': elapsed time 6.12 seconds, memory usage 285508kB, peak memory usage 388764kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'sobel.v7' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/sobel': (Total ops = 1830, Real ops = 467, Vars = 1152) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1821, Real ops = 467, Vars = 1145) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2601, Real ops = 461, Vars = 103) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2592, Real ops = 461, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'sobel.v7': elapsed time 1.70 seconds, memory usage 285896kB, peak memory usage 388764kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'sobel.v7' (SOL-8)
+# Warning: Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#268:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,0,11) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#215:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,0,11) (ASG-1)
+# Info: Optimizing partition '/sobel': (Total ops = 1495, Real ops = 470, Vars = 1492) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1486, Real ops = 470, Vars = 1485) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1480, Real ops = 469, Vars = 1477) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1471, Real ops = 469, Vars = 1470) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1480, Real ops = 469, Vars = 1477) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1471, Real ops = 469, Vars = 1470) (SOL-10)
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Info: Optimizing partition '/sobel': (Total ops = 1480, Real ops = 469, Vars = 1477) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1471, Real ops = 469, Vars = 1470) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1402, Real ops = 457, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1393, Real ops = 457, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1402, Real ops = 457, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1393, Real ops = 457, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1402, Real ops = 457, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1393, Real ops = 457, Vars = 95) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v7/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Info: Completed transformation 'extract' on solution 'sobel.v7': elapsed time 11.58 seconds, memory usage 287424kB, peak memory usage 388764kB (SOL-9)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# Input file has changed
+go new
+solution file set {$PROJECT_HOME/sobel.cpp} -updated
+# Info: Branching solution 'solution.v2' at state 'new' (PRJ-2)
+# File '$PROJECT_HOME/sobel.cpp' saved
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(128): $PROJECT_HOME/sobel.cpp(128): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# $PROJECT_HOME/sobel.cpp(49): Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+# Source file analysis completed (CIN-68)
+# Info: Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.17 seconds, memory usage 308128kB, peak memory usage 415668kB (SOL-9)
+# Info: Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+# Generating synthesis internal form... (CIN-3)
+# $PROJECT_HOME/sobel.cpp(50): Found top design routine 'sobel' specified by directive (CIN-52)
+# $PROJECT_HOME/sobel.cpp(50): Synthesizing routine 'sobel' (CIN-13)
+# $PROJECT_HOME/sobel.cpp(50): Inlining routine 'sobel' (CIN-14)
+# $PROJECT_HOME/shift_class.h(13): Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(32): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(76): Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(86): Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/sobel.cpp(50): Optimizing block '/sobel' ... (CIN-4)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vin' is only used as an input. (OPT-10)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vout' is only used as an output. (OPT-11)
+# Info: Optimizing partition '/sobel': (Total ops = 1035, Real ops = 214, Vars = 224) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1035, Real ops = 214, Vars = 222) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 993, Real ops = 206, Vars = 228) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 993, Real ops = 206, Vars = 230) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 993, Real ops = 206, Vars = 230) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 993, Real ops = 206, Vars = 228) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 937, Real ops = 205, Vars = 215) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 912, Real ops = 205, Vars = 214) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 912, Real ops = 205, Vars = 214) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 912, Real ops = 205, Vars = 216) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 912, Real ops = 205, Vars = 216) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 890, Real ops = 203, Vars = 258) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 39) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 632, Real ops = 126, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 632, Real ops = 126, Vars = 33) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(66): Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(74): Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(84): Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(94): Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(67): Detected constant initialization of array 'in', optimizing loop 'RESET' (LOOP-12)
+# Info: Optimizing partition '/sobel/core': (Total ops = 670, Real ops = 125, Vars = 32) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 595, Real ops = 117, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 592, Real ops = 117, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 592, Real ops = 117, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 587, Real ops = 117, Vars = 36) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 584, Real ops = 117, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 584, Real ops = 117, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 584, Real ops = 117, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 584, Real ops = 117, Vars = 33) (SOL-10)
+# Design 'sobel' was read (SOL-1)
+# Info: Completed transformation 'compile' on solution 'sobel.v8': elapsed time 4.98 seconds, memory usage 300316kB, peak memory usage 415668kB (SOL-9)
+# Info: Starting transformation 'architect' on solution 'sobel.v8' (SOL-8)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(74): Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(84): Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(94): Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1539, Real ops = 290, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 971, Real ops = 174, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 970, Real ops = 174, Vars = 39) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 970, Real ops = 174, Vars = 39) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 973, Real ops = 174, Vars = 41) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 968, Real ops = 174, Vars = 41) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 939, Real ops = 187, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 939, Real ops = 187, Vars = 40) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(50): Loop '/sobel/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/sobel': (Total ops = 939, Real ops = 187, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 940, Real ops = 187, Vars = 41) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 940, Real ops = 187, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 940, Real ops = 187, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 940, Real ops = 187, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 940, Real ops = 187, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 48) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 43) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 45) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+# Info: Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 938, Real ops = 187, Vars = 40) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 938, Real ops = 187, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 932, Real ops = 187, Vars = 49) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 932, Real ops = 187, Vars = 44) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 913, Real ops = 192, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 913, Real ops = 192, Vars = 47) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 913, Real ops = 192, Vars = 42) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 913, Real ops = 192, Vars = 47) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 920, Real ops = 193, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 919, Real ops = 193, Vars = 45) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1354, Real ops = 245, Vars = 293) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 987, Real ops = 216, Vars = 83) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 986, Real ops = 216, Vars = 82) (SOL-10)
+# Design 'sobel' contains '439' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'sobel.v8': elapsed time 12.56 seconds, memory usage 300472kB, peak memory usage 415668kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'sobel.v8' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 6857.74, 0.00, 6857.74 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 6767.91, 0.00, 6767.91 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 921601, Area (Datapath, Register, Total) = 6764.18, 0.00, 6764.18 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 921601, Area (Datapath, Register, Total) = 6764.18, 0.00, 6764.18 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'sobel.v8': elapsed time 5.63 seconds, memory usage 300992kB, peak memory usage 415668kB (SOL-9)
+# Info: Starting transformation 'schedule' on solution 'sobel.v8' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Warning: Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+# Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/sobel': (Total ops = 1561, Real ops = 440, Vars = 122) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1551, Real ops = 439, Vars = 114) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 1542, Real ops = 440, Vars = 129) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 1433, Real ops = 426, Vars = 82) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 1422, Real ops = 425, Vars = 79) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1436, Real ops = 425, Vars = 91) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1427, Real ops = 425, Vars = 84) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 1424, Real ops = 425, Vars = 81) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 1423, Real ops = 425, Vars = 79) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1437, Real ops = 425, Vars = 91) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1428, Real ops = 425, Vars = 84) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 1423, Real ops = 425, Vars = 79) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1437, Real ops = 425, Vars = 91) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1428, Real ops = 425, Vars = 84) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Info: Completed transformation 'schedule' on solution 'sobel.v8': elapsed time 6.38 seconds, memory usage 307280kB, peak memory usage 415668kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'sobel.v8' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/sobel': (Total ops = 1830, Real ops = 467, Vars = 1152) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1821, Real ops = 467, Vars = 1145) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2601, Real ops = 461, Vars = 103) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2592, Real ops = 461, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1432, Real ops = 458, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1423, Real ops = 458, Vars = 95) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'sobel.v8': elapsed time 1.90 seconds, memory usage 307280kB, peak memory usage 415668kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'sobel.v8' (SOL-8)
+# Warning: Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,1,5) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#268:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,0,11) (ASG-1)
+# Warning: Reassigned operation ACC1:acc#215:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(12,1,12,1,13) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(11,0,10,0,11) (ASG-1)
+# Info: Optimizing partition '/sobel': (Total ops = 1495, Real ops = 470, Vars = 1492) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1486, Real ops = 470, Vars = 1485) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1417, Real ops = 457, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1408, Real ops = 457, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1480, Real ops = 469, Vars = 1477) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1471, Real ops = 469, Vars = 1470) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1480, Real ops = 469, Vars = 1477) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1471, Real ops = 469, Vars = 1470) (SOL-10)
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Info: Optimizing partition '/sobel': (Total ops = 1480, Real ops = 469, Vars = 1477) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1471, Real ops = 469, Vars = 1470) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1402, Real ops = 457, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1393, Real ops = 457, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1402, Real ops = 457, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1393, Real ops = 457, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1402, Real ops = 457, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 1393, Real ops = 457, Vars = 95) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v8/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Info: Completed transformation 'extract' on solution 'sobel.v8': elapsed time 12.45 seconds, memory usage 308836kB, peak memory usage 415668kB (SOL-9)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# Input file has changed
+go new
+solution file set {$PROJECT_HOME/sobel.cpp} -updated
+# Info: Branching solution 'solution.v2' at state 'new' (PRJ-2)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(156): $PROJECT_HOME/sobel.cpp(156): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# $PROJECT_HOME/sobel.cpp(49): Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+# Source file analysis completed (CIN-68)
+# Info: Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.14 seconds, memory usage 313484kB, peak memory usage 437356kB (SOL-9)
+# Info: Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+# Generating synthesis internal form... (CIN-3)
+# $PROJECT_HOME/sobel.cpp(50): Found top design routine 'sobel' specified by directive (CIN-52)
+# $PROJECT_HOME/sobel.cpp(50): Synthesizing routine 'sobel' (CIN-13)
+# $PROJECT_HOME/sobel.cpp(50): Inlining routine 'sobel' (CIN-14)
+# $PROJECT_HOME/shift_class.h(13): Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(32): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(88): Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(104): Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/sobel.cpp(50): Optimizing block '/sobel' ... (CIN-4)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vin' is only used as an input. (OPT-10)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vout' is only used as an output. (OPT-11)
+# Info: Optimizing partition '/sobel': (Total ops = 644, Real ops = 142, Vars = 142) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 644, Real ops = 142, Vars = 140) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 604, Real ops = 134, Vars = 146) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 604, Real ops = 134, Vars = 148) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 604, Real ops = 134, Vars = 148) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 604, Real ops = 134, Vars = 146) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 405, Real ops = 110, Vars = 97) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 380, Real ops = 110, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 380, Real ops = 110, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 380, Real ops = 110, Vars = 98) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 380, Real ops = 110, Vars = 98) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 360, Real ops = 108, Vars = 146) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 32) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(68): Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(78): Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(86): Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(102): Loop '/sobel/core/FRAME:for#1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(118): Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(69): Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(70): Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(71): Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+# Info: Optimizing partition '/sobel/core': (Total ops = 392, Real ops = 104, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 303, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 303, Real ops = 94, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 298, Real ops = 94, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+# Design 'sobel' was read (SOL-1)
+# Info: Completed transformation 'compile' on solution 'sobel.v9': elapsed time 4.46 seconds, memory usage 319744kB, peak memory usage 437356kB (SOL-9)
+# Info: Starting transformation 'architect' on solution 'sobel.v9' (SOL-8)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(86): Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(102): Loop '/sobel/core/FRAME:for#1' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(118): Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+# Info: Optimizing partition '/sobel/core': (Total ops = 346, Real ops = 111, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 20) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(50): Loop '/sobel/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/sobel': (Total ops = 283, Real ops = 90, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+# Info: Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 283, Real ops = 90, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 34) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 237, Real ops = 105, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 237, Real ops = 105, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 237, Real ops = 105, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 237, Real ops = 105, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 247, Real ops = 106, Vars = 32) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 640, Real ops = 174, Vars = 263) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 331, Real ops = 155, Vars = 76) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 330, Real ops = 155, Vars = 75) (SOL-10)
+# Design 'sobel' contains '216' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'sobel.v9': elapsed time 11.28 seconds, memory usage 319928kB, peak memory usage 437356kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'sobel.v9' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 1843201, Area (Datapath, Register, Total) = 6576.18, 0.00, 6576.18 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 1843201, Area (Datapath, Register, Total) = 6570.04, 0.00, 6570.04 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 1843201, Area (Datapath, Register, Total) = 6519.24, 0.00, 6519.24 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 1843201, Area (Datapath, Register, Total) = 6519.24, 0.00, 6519.24 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'sobel.v9': elapsed time 1.44 seconds, memory usage 320116kB, peak memory usage 437356kB (SOL-9)
+# Info: Starting transformation 'schedule' on solution 'sobel.v9' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Warning: Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+# Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/sobel': (Total ops = 484, Real ops = 217, Vars = 158) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 474, Real ops = 216, Vars = 150) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 463, Real ops = 216, Vars = 149) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 441, Real ops = 208, Vars = 119) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 434, Real ops = 205, Vars = 120) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 448, Real ops = 205, Vars = 132) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 439, Real ops = 205, Vars = 125) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 443, Real ops = 204, Vars = 135) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 439, Real ops = 204, Vars = 125) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 453, Real ops = 204, Vars = 137) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 444, Real ops = 204, Vars = 130) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 439, Real ops = 204, Vars = 125) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 453, Real ops = 204, Vars = 137) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 444, Real ops = 204, Vars = 130) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Info: Completed transformation 'schedule' on solution 'sobel.v9': elapsed time 2.40 seconds, memory usage 319848kB, peak memory usage 437356kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'sobel.v9' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/sobel': (Total ops = 805, Real ops = 328, Vars = 743) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 796, Real ops = 328, Vars = 736) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 647, Real ops = 236, Vars = 109) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 638, Real ops = 236, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 390, Real ops = 215, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 381, Real ops = 215, Vars = 101) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'sobel.v9': elapsed time 0.78 seconds, memory usage 320236kB, peak memory usage 437356kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'sobel.v9' (SOL-8)
+# Warning: Reassigned operation FRAME:for#1:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+# Warning: Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+# Info: Optimizing partition '/sobel': (Total ops = 481, Real ops = 250, Vars = 478) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 472, Real ops = 250, Vars = 471) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 109) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 461, Real ops = 247, Vars = 458) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 452, Real ops = 247, Vars = 451) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 461, Real ops = 247, Vars = 458) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 452, Real ops = 247, Vars = 451) (SOL-10)
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Info: Optimizing partition '/sobel': (Total ops = 461, Real ops = 247, Vars = 458) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 452, Real ops = 247, Vars = 451) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 356, Real ops = 209, Vars = 109) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 347, Real ops = 209, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 356, Real ops = 209, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 347, Real ops = 209, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 356, Real ops = 209, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 347, Real ops = 209, Vars = 99) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v9/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Info: Completed transformation 'extract' on solution 'sobel.v9': elapsed time 8.88 seconds, memory usage 320524kB, peak memory usage 437356kB (SOL-9)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# Input file has changed
+go new
+solution file set {$PROJECT_HOME/sobel.cpp} -updated
+# Info: Branching solution 'solution.v2' at state 'new' (PRJ-2)
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Error: $PROJECT_HOME/sobel.cpp(85): $PROJECT_HOME/sobel.cpp(85): expected a ")" (CRD-18)
+# Error: $PROJECT_HOME/sobel.cpp(85): $PROJECT_HOME/sobel.cpp(85): expected a ")" (CRD-18)
+# Error: $PROJECT_HOME/sobel.cpp(85): $PROJECT_HOME/sobel.cpp(85): expected a ")" (CRD-18)
+# Warning: $PROJECT_HOME/sobel.cpp(168): $PROJECT_HOME/sobel.cpp(168): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# Error: Compilation aborted (CIN-5)
+# Error: go analyze: Failed analyze
+# File '$PROJECT_HOME/sobel.cpp' saved
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(168): $PROJECT_HOME/sobel.cpp(168): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# $PROJECT_HOME/sobel.cpp(49): Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+# Source file analysis completed (CIN-68)
+# Info: Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.07 seconds, memory usage 351284kB, peak memory usage 448912kB (SOL-9)
+# Info: Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+# Generating synthesis internal form... (CIN-3)
+# $PROJECT_HOME/sobel.cpp(50): Found top design routine 'sobel' specified by directive (CIN-52)
+# $PROJECT_HOME/sobel.cpp(50): Synthesizing routine 'sobel' (CIN-13)
+# $PROJECT_HOME/sobel.cpp(50): Inlining routine 'sobel' (CIN-14)
+# $PROJECT_HOME/shift_class.h(13): Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(32): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(100): Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(116): Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/sobel.cpp(50): Optimizing block '/sobel' ... (CIN-4)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vin' is only used as an input. (OPT-10)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vout' is only used as an output. (OPT-11)
+# Info: Optimizing partition '/sobel': (Total ops = 910, Real ops = 188, Vars = 204) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 910, Real ops = 188, Vars = 202) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 870, Real ops = 180, Vars = 208) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 870, Real ops = 180, Vars = 210) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 870, Real ops = 180, Vars = 210) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 870, Real ops = 180, Vars = 208) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 405, Real ops = 110, Vars = 97) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 380, Real ops = 110, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 380, Real ops = 110, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 380, Real ops = 110, Vars = 98) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 380, Real ops = 110, Vars = 98) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 360, Real ops = 108, Vars = 146) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 32) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 357, Real ops = 108, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 357, Real ops = 108, Vars = 26) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(68): Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(78): Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(98): Loop '/sobel/core/FRAME:for' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(114): Loop '/sobel/core/FRAME:for#1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(130): Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(69): Detected constant initialization of array 'r', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(70): Detected constant initialization of array 'g', optimizing loop 'RESET' (LOOP-12)
+# $PROJECT_HOME/sobel.cpp(71): Detected constant initialization of array 'b', optimizing loop 'RESET' (LOOP-12)
+# Info: Optimizing partition '/sobel/core': (Total ops = 392, Real ops = 104, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 303, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 303, Real ops = 94, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 298, Real ops = 94, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 295, Real ops = 94, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 295, Real ops = 94, Vars = 25) (SOL-10)
+# Design 'sobel' was read (SOL-1)
+# Info: Completed transformation 'compile' on solution 'sobel.v10': elapsed time 5.01 seconds, memory usage 326452kB, peak memory usage 448912kB (SOL-9)
+# Info: Starting transformation 'architect' on solution 'sobel.v10' (SOL-8)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(98): Loop '/sobel/core/FRAME:for' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(114): Loop '/sobel/core/FRAME:for#1' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(130): Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+# Info: Optimizing partition '/sobel/core': (Total ops = 346, Real ops = 111, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 20) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(50): Loop '/sobel/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/sobel': (Total ops = 283, Real ops = 90, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+# Info: Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 286, Real ops = 90, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 286, Real ops = 90, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 283, Real ops = 90, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 283, Real ops = 90, Vars = 34) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 237, Real ops = 105, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 237, Real ops = 105, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 237, Real ops = 105, Vars = 28) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 237, Real ops = 105, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 247, Real ops = 106, Vars = 32) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 640, Real ops = 174, Vars = 263) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 331, Real ops = 155, Vars = 76) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 330, Real ops = 155, Vars = 75) (SOL-10)
+# Design 'sobel' contains '216' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'sobel.v10': elapsed time 12.37 seconds, memory usage 326652kB, peak memory usage 448912kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'sobel.v10' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 1843201, Area (Datapath, Register, Total) = 6576.18, 0.00, 6576.18 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 1843201, Area (Datapath, Register, Total) = 6570.04, 0.00, 6570.04 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 1843201, Area (Datapath, Register, Total) = 6519.24, 0.00, 6519.24 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 1843201, Area (Datapath, Register, Total) = 6519.24, 0.00, 6519.24 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'sobel.v10': elapsed time 1.64 seconds, memory usage 326776kB, peak memory usage 448912kB (SOL-9)
+# Info: Starting transformation 'schedule' on solution 'sobel.v10' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Warning: Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+# Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/sobel': (Total ops = 484, Real ops = 217, Vars = 158) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 474, Real ops = 216, Vars = 150) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 463, Real ops = 216, Vars = 149) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 441, Real ops = 208, Vars = 119) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 434, Real ops = 205, Vars = 120) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 448, Real ops = 205, Vars = 132) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 439, Real ops = 205, Vars = 125) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 443, Real ops = 204, Vars = 135) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 439, Real ops = 204, Vars = 125) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 453, Real ops = 204, Vars = 137) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 444, Real ops = 204, Vars = 130) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 439, Real ops = 204, Vars = 125) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 453, Real ops = 204, Vars = 137) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 444, Real ops = 204, Vars = 130) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Info: Completed transformation 'schedule' on solution 'sobel.v10': elapsed time 2.39 seconds, memory usage 327016kB, peak memory usage 448912kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'sobel.v10' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/sobel': (Total ops = 805, Real ops = 328, Vars = 743) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 796, Real ops = 328, Vars = 736) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 647, Real ops = 236, Vars = 109) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 638, Real ops = 236, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 390, Real ops = 215, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 381, Real ops = 215, Vars = 101) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 388, Real ops = 213, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 379, Real ops = 213, Vars = 101) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'sobel.v10': elapsed time 0.81 seconds, memory usage 327628kB, peak memory usage 448912kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'sobel.v10' (SOL-8)
+# Warning: Reassigned operation FRAME:for#1:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+# Warning: Reassigned operation FRAME:for:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,3,0,3) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(2,0,1,0,2) (ASG-1)
+# Info: Optimizing partition '/sobel': (Total ops = 481, Real ops = 250, Vars = 478) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 472, Real ops = 250, Vars = 471) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 109) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 365, Real ops = 209, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 356, Real ops = 209, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 461, Real ops = 247, Vars = 458) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 452, Real ops = 247, Vars = 451) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 461, Real ops = 247, Vars = 458) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 452, Real ops = 247, Vars = 451) (SOL-10)
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Info: Optimizing partition '/sobel': (Total ops = 461, Real ops = 247, Vars = 458) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 452, Real ops = 247, Vars = 451) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 356, Real ops = 209, Vars = 109) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 347, Real ops = 209, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 356, Real ops = 209, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 347, Real ops = 209, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 356, Real ops = 209, Vars = 106) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 347, Real ops = 209, Vars = 99) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v10/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Info: Completed transformation 'extract' on solution 'sobel.v10': elapsed time 9.19 seconds, memory usage 327636kB, peak memory usage 448912kB (SOL-9)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# Input file has changed
+go new
+solution file set {$PROJECT_HOME/sobel.cpp} -updated
+# Info: Branching solution 'solution.v2' at state 'new' (PRJ-2)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+# File '$PROJECT_HOME/sobel.cpp' saved
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Error: $PROJECT_HOME/sobel.cpp(90): $PROJECT_HOME/sobel.cpp(90): expected a ";" (CRD-65)
+# Warning: $PROJECT_HOME/sobel.cpp(121): $PROJECT_HOME/sobel.cpp(121): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# Error: Compilation aborted (CIN-5)
+# Error: go analyze: Failed analyze
+# File '$PROJECT_HOME/sobel.cpp' saved
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v2' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(121): $PROJECT_HOME/sobel.cpp(121): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# $PROJECT_HOME/sobel.cpp(49): Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+# Source file analysis completed (CIN-68)
+# Info: Completed transformation 'analyze' on solution 'solution.v2': elapsed time 3.17 seconds, memory usage 353576kB, peak memory usage 457688kB (SOL-9)
+# Info: Starting transformation 'compile' on solution 'solution.v2' (SOL-8)
+# Generating synthesis internal form... (CIN-3)
+# $PROJECT_HOME/sobel.cpp(50): Found top design routine 'sobel' specified by directive (CIN-52)
+# $PROJECT_HOME/sobel.cpp(50): Synthesizing routine 'sobel' (CIN-13)
+# $PROJECT_HOME/sobel.cpp(50): Inlining routine 'sobel' (CIN-14)
+# $PROJECT_HOME/shift_class.h(13): Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(32): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(76): Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(77): Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/sobel.cpp(50): Optimizing block '/sobel' ... (CIN-4)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vin' is only used as an input. (OPT-10)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vout' is only used as an output. (OPT-11)
+# Info: Optimizing partition '/sobel': (Total ops = 1693, Real ops = 337, Vars = 368) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1693, Real ops = 337, Vars = 366) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1658, Real ops = 327, Vars = 372) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1658, Real ops = 327, Vars = 374) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1658, Real ops = 327, Vars = 374) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1658, Real ops = 327, Vars = 372) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1602, Real ops = 326, Vars = 359) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1577, Real ops = 326, Vars = 358) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1577, Real ops = 326, Vars = 358) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1577, Real ops = 326, Vars = 360) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1577, Real ops = 326, Vars = 360) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1556, Real ops = 324, Vars = 402) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 57) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(66): Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(74): Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(87): Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(67): Detected constant initialization of array 'inte', optimizing loop 'RESET' (LOOP-12)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1177, Real ops = 184, Vars = 60) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 848, Real ops = 155, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 846, Real ops = 155, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 846, Real ops = 155, Vars = 52) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 842, Real ops = 155, Vars = 54) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 840, Real ops = 155, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 840, Real ops = 155, Vars = 52) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 840, Real ops = 155, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 840, Real ops = 155, Vars = 52) (SOL-10)
+# Design 'sobel' was read (SOL-1)
+# Input file has changed
+go new
+solution file set {$PROJECT_HOME/sobel.cpp} -updated
+# Info: Branching solution 'solution.v2' at state 'new' (PRJ-2)
+# Info: Completed transformation 'compile' on solution 'sobel.v11': elapsed time 12.09 seconds, memory usage 335932kB, peak memory usage 457688kB (SOL-9)
+# Info: Starting transformation 'architect' on solution 'sobel.v11' (SOL-8)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(74): Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(87): Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+# Info: Optimizing partition '/sobel/core': (Total ops = 2387, Real ops = 428, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1805, Real ops = 303, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1797, Real ops = 303, Vars = 73) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1797, Real ops = 303, Vars = 73) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1701, Real ops = 260, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1548, Real ops = 285, Vars = 61) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1519, Real ops = 295, Vars = 59) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(50): Loop '/sobel/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/sobel': (Total ops = 1519, Real ops = 295, Vars = 64) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 60) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+# Info: Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1516, Real ops = 295, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1516, Real ops = 295, Vars = 63) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1489, Real ops = 300, Vars = 59) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1489, Real ops = 300, Vars = 64) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1489, Real ops = 300, Vars = 59) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1489, Real ops = 300, Vars = 64) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1492, Real ops = 300, Vars = 60) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1926, Real ops = 304, Vars = 311) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1496, Real ops = 302, Vars = 63) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1495, Real ops = 302, Vars = 62) (SOL-10)
+# Design 'sobel' contains '676' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'sobel.v11': elapsed time 21.20 seconds, memory usage 336332kB, peak memory usage 457688kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'sobel.v11' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 307201, Area (Datapath, Register, Total) = 5750.29, 0.00, 5750.29 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 307201, Area (Datapath, Register, Total) = 5558.68, 0.00, 5558.68 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 307201, Area (Datapath, Register, Total) = 5558.68, 0.00, 5558.68 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'sobel.v11': elapsed time 15.13 seconds, memory usage 338928kB, peak memory usage 457688kB (SOL-9)
+# Info: Starting transformation 'schedule' on solution 'sobel.v11' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Warning: Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+# Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/sobel': (Total ops = 2382, Real ops = 677, Vars = 121) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2372, Real ops = 676, Vars = 113) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 2367, Real ops = 676, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 2174, Real ops = 648, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 2158, Real ops = 648, Vars = 91) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2172, Real ops = 648, Vars = 103) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2163, Real ops = 648, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 2155, Real ops = 648, Vars = 93) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 2155, Real ops = 648, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2169, Real ops = 648, Vars = 104) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2160, Real ops = 648, Vars = 97) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 2155, Real ops = 648, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2169, Real ops = 648, Vars = 104) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2160, Real ops = 648, Vars = 97) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Info: Completed transformation 'schedule' on solution 'sobel.v11': elapsed time 7.44 seconds, memory usage 363120kB, peak memory usage 457688kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'sobel.v11' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/sobel': (Total ops = 2428, Real ops = 663, Vars = 1568) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2419, Real ops = 663, Vars = 1561) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 3946, Real ops = 670, Vars = 100) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 3937, Real ops = 670, Vars = 93) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'sobel.v11': elapsed time 3.82 seconds, memory usage 364816kB, peak memory usage 457688kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'sobel.v11' (SOL-8)
+# Info: Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Info: Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2151, Real ops = 668, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2142, Real ops = 668, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2151, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2142, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2151, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2142, Real ops = 668, Vars = 92) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v11/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Info: Completed transformation 'extract' on solution 'sobel.v11': elapsed time 17.32 seconds, memory usage 368816kB, peak memory usage 457688kB (SOL-9)
+# File '$PROJECT_HOME/sobel.cpp' saved
+# Input file has changed
+go new
+solution file set {$PROJECT_HOME/sobel.cpp} -updated
+# Info: Branching solution 'solution.v3' at state 'new' (PRJ-2)
+go extract
+# Info: Starting transformation 'analyze' on solution 'solution.v3' (SOL-8)
+# Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\shift_class.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h} (CIN-69)
+# Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.cpp(121): $PROJECT_HOME/sobel.cpp(121): last line of file ends without a newline (CRD-1)
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(262): $PROJECT_HOME/tb_blur.cpp(262): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(263): $PROJECT_HOME/tb_blur.cpp(263): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(264): $PROJECT_HOME/tb_blur.cpp(264): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/tb_blur.cpp(265): $PROJECT_HOME/tb_blur.cpp(265): nested comment is not allowed (CRD-9)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\tb_blur.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1699): $PROJECT_HOME/bmp_io.cpp(1699): variable "garray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/bmp_io.cpp(1700): $PROJECT_HOME/bmp_io.cpp(1700): variable "barray" is used before its value is set (CRD-549)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\bmp_io.cpp"
+# Warning: $PROJECT_HOME/sobel.h(91): $PROJECT_HOME/sobel.h(91): last line of file ends without a newline (CRD-1)
+# Warning:           detected during compilation of secondary translation unit "\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Sobel Filter Catapult\sobel.h"
+# $PROJECT_HOME/sobel.cpp(49): Pragma 'hls_design<top>' detected on routine 'sobel' (CIN-6)
+# Source file analysis completed (CIN-68)
+# Info: Completed transformation 'analyze' on solution 'solution.v3': elapsed time 3.14 seconds, memory usage 379144kB, peak memory usage 498484kB (SOL-9)
+# Info: Starting transformation 'compile' on solution 'solution.v3' (SOL-8)
+# Generating synthesis internal form... (CIN-3)
+# $PROJECT_HOME/sobel.cpp(50): Found top design routine 'sobel' specified by directive (CIN-52)
+# $PROJECT_HOME/sobel.cpp(50): Synthesizing routine 'sobel' (CIN-13)
+# $PROJECT_HOME/sobel.cpp(50): Inlining routine 'sobel' (CIN-14)
+# $PROJECT_HOME/shift_class.h(13): Inlining member function 'shift_class<ac_int<90, true>, 3>::shift_class' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(32): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator<<' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(76): Instantiating global variable 'XMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# Warning: $PROJECT_HOME/sobel.cpp(77): Instantiating global variable 'YMATRIX' which may be accessed outside this scope (CIN-18)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/shift_class.h(48): Inlining member function 'shift_class<ac_int<90, true>, 3>::operator[]' on object 'regs' (CIN-64)
+# $PROJECT_HOME/sobel.cpp(50): Optimizing block '/sobel' ... (CIN-4)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vin' is only used as an input. (OPT-10)
+# $PROJECT_HOME/sobel.cpp(50): Inout port 'vout' is only used as an output. (OPT-11)
+# Info: Optimizing partition '/sobel': (Total ops = 1693, Real ops = 337, Vars = 368) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1693, Real ops = 337, Vars = 366) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1658, Real ops = 327, Vars = 372) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1658, Real ops = 327, Vars = 374) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1658, Real ops = 327, Vars = 374) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1658, Real ops = 327, Vars = 372) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1602, Real ops = 326, Vars = 359) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1577, Real ops = 326, Vars = 358) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1577, Real ops = 326, Vars = 358) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1577, Real ops = 326, Vars = 360) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1577, Real ops = 326, Vars = 360) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1556, Real ops = 324, Vars = 402) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 57) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1047, Real ops = 184, Vars = 49) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1047, Real ops = 184, Vars = 47) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(66): Loop '/sobel/core/RESET' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(74): Loop '/sobel/core/ACC1' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(87): Loop '/sobel/core/ACC2' iterated at most 3 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' iterated at most 307200 times. (LOOP-2)
+# $PROJECT_HOME/sobel.cpp(67): Detected constant initialization of array 'inte', optimizing loop 'RESET' (LOOP-12)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1177, Real ops = 184, Vars = 60) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 848, Real ops = 155, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 846, Real ops = 155, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 846, Real ops = 155, Vars = 52) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 842, Real ops = 155, Vars = 54) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 840, Real ops = 155, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 840, Real ops = 155, Vars = 52) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 840, Real ops = 155, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 840, Real ops = 155, Vars = 52) (SOL-10)
+# Design 'sobel' was read (SOL-1)
+# Info: Completed transformation 'compile' on solution 'sobel.v12': elapsed time 9.08 seconds, memory usage 376880kB, peak memory usage 498484kB (SOL-9)
+# Info: Starting transformation 'architect' on solution 'sobel.v12' (SOL-8)
+# $PROJECT_HOME/shift_class.h(34): Loop '/sobel/core/SHIFT' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(74): Loop '/sobel/core/ACC1' is being fully unrolled (3 times). (LOOP-7)
+# $PROJECT_HOME/sobel.cpp(87): Loop '/sobel/core/ACC2' is being fully unrolled (3 times). (LOOP-7)
+# Info: Optimizing partition '/sobel/core': (Total ops = 2387, Real ops = 428, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1805, Real ops = 303, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1797, Real ops = 303, Vars = 73) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1797, Real ops = 303, Vars = 73) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1701, Real ops = 260, Vars = 75) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1548, Real ops = 285, Vars = 61) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1519, Real ops = 295, Vars = 59) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(63): Loop '/sobel/core/FRAME' is left rolled. (LOOP-4)
+# $PROJECT_HOME/sobel.cpp(50): Loop '/sobel/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/sobel': (Total ops = 1519, Real ops = 295, Vars = 64) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 60) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vin:rsc' (from var: vin) mapped to 'mgc_ioport.mgc_in_wire' (size: 90). (MEM-2)
+# $PROJECT_HOME/sobel.cpp(50): I/O-Port inferred - resource 'vout:rsc' (from var: vout) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 30). (MEM-2)
+# Info: Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1520, Real ops = 295, Vars = 59) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1520, Real ops = 295, Vars = 64) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1516, Real ops = 295, Vars = 68) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1516, Real ops = 295, Vars = 63) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1489, Real ops = 300, Vars = 59) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1489, Real ops = 300, Vars = 64) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1489, Real ops = 300, Vars = 59) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 1489, Real ops = 300, Vars = 64) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1492, Real ops = 300, Vars = 60) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1926, Real ops = 304, Vars = 311) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1496, Real ops = 302, Vars = 63) (SOL-10)
+# Info: Optimizing partition '/sobel/core': (Total ops = 1495, Real ops = 302, Vars = 62) (SOL-10)
+# Design 'sobel' contains '676' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'sobel.v12': elapsed time 23.82 seconds, memory usage 377284kB, peak memory usage 498484kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'sobel.v12' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'main' (3 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled LOOP 'core:rlp' (0 c-steps) (SCHD-7)
+# $PROJECT_HOME/sobel.cpp(50): Prescheduled SEQUENTIAL 'core' (total length 3 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 307201, Area (Datapath, Register, Total) = 5750.29, 0.00, 5750.29 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 307201, Area (Datapath, Register, Total) = 5558.68, 0.00, 5558.68 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 307201, Area (Datapath, Register, Total) = 5558.68, 0.00, 5558.68 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'sobel.v12': elapsed time 16.72 seconds, memory usage 382608kB, peak memory usage 498484kB (SOL-9)
+# Info: Starting transformation 'schedule' on solution 'sobel.v12' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/sobel/core' (CRAAS-1)
+# Warning: Cannot build distributed pipeline in process 'core' because of missing handshake for resource 'vout:rsc' (SCHD-15)
+# Global signal 'vin:rsc.z' added to design 'sobel' for component 'vin:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'vout:rsc.z' added to design 'sobel' for component 'vout:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/sobel': (Total ops = 2382, Real ops = 677, Vars = 121) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2372, Real ops = 676, Vars = 113) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 2367, Real ops = 676, Vars = 108) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 2174, Real ops = 648, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 2158, Real ops = 648, Vars = 91) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2172, Real ops = 648, Vars = 103) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2163, Real ops = 648, Vars = 96) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 2155, Real ops = 648, Vars = 93) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 2155, Real ops = 648, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2169, Real ops = 648, Vars = 104) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2160, Real ops = 648, Vars = 97) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core/core': (Total ops = 2155, Real ops = 648, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2169, Real ops = 648, Vars = 104) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2160, Real ops = 648, Vars = 97) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Info: Completed transformation 'schedule' on solution 'sobel.v12': elapsed time 8.02 seconds, memory usage 389548kB, peak memory usage 498484kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'sobel.v12' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/sobel': (Total ops = 2428, Real ops = 663, Vars = 1568) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2419, Real ops = 663, Vars = 1561) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 3946, Real ops = 670, Vars = 100) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 3937, Real ops = 670, Vars = 93) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2170, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2161, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'sobel.v12': elapsed time 4.18 seconds, memory usage 391324kB, peak memory usage 498484kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'sobel.v12' (SOL-8)
+# Info: Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2176, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2167, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Info: Optimizing partition '/sobel': (Total ops = 2187, Real ops = 670, Vars = 2184) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2178, Real ops = 670, Vars = 2177) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2151, Real ops = 668, Vars = 102) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2142, Real ops = 668, Vars = 95) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2151, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2142, Real ops = 668, Vars = 92) (SOL-10)
+# Info: Optimizing partition '/sobel': (Total ops = 2151, Real ops = 668, Vars = 99) (SOL-10)
+# Info: Optimizing partition '/sobel/sobel:core': (Total ops = 2142, Real ops = 668, Vars = 92) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v12/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Info: Completed transformation 'extract' on solution 'sobel.v12': elapsed time 18.09 seconds, memory usage 395324kB, peak memory usage 498484kB (SOL-9)
+# File '$PROJECT_HOME/Sobel/sobel.v12/rtl.v' saved
+project save
+# Saving project file '//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel.ccs'. (PRJ-5)
+quit -f
diff --git a/shift_class.h b/shift_class.h
new file mode 100644
index 0000000..be64c0f
--- /dev/null
+++ b/shift_class.h
@@ -0,0 +1,54 @@
+#ifndef __SHIFT_CLASS__
+#define __SHIFT_CLASS__
+
+template<typename dataType, int NUM_REGS>
+class shift_class{
+private:
+    dataType regs[NUM_REGS];
+    bool en;
+    bool sync_rst;
+    bool ld;
+    dataType *load_data;
+public:
+    shift_class():en(true),sync_rst(false),ld(false){}
+    shift_class(dataType din[NUM_REGS]):
+    en(true),sync_rst(false),ld(false){ load_data = din; }
+
+    void set_sync_rst(bool srst)
+    {
+        sync_rst = srst;
+    }
+
+    void load(bool load_in)
+    {
+        ld = load_in;
+    }
+
+    void set_enable(bool enable)
+    {
+        en = enable;
+    }
+
+    void operator << (dataType din)
+    {
+    SHIFT:for(int i=NUM_REGS-1;i>=0;i--){
+    if(en)
+        if(sync_rst)
+            regs[i] = 0;
+        else if(ld)
+            regs[i] = load_data[i];
+        else
+        if(i==0)
+            regs[i] = din;
+        else
+            regs[i] = regs[i-1];
+        }
+    }
+
+    dataType operator [](int i)
+    {
+        return regs[i];
+    }
+};
+
+#endif
diff --git a/sobel.cpp b/sobel.cpp
new file mode 100644
index 0000000..3654422
--- /dev/null
+++ b/sobel.cpp
@@ -0,0 +1,121 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           sobel.cpp
+//  Description:    video to vga sobel filter - real-time processing
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// this hardware block receives the VGA stream and then produces a blured output
+// based on the FIR design - page 230 of HLS Blue Book
+////////////////////////////////////////////////////////////////////////////////
+// Catapult Project options
+// Constraint Editor:
+//  Frequency: 50 MHz
+//  Top design: sobel
+//  clk>reset sync: disable; reset async: enable; enable: enable
+// Architecture Constraints:
+//  interface>vin: wordlength = 90, streaming = 90
+//  interface>vout: wordlength = 30, streaming = 30
+//  core>main: pipeline + distributed + merged
+//  core>main>frame: merged
+//  core>main>frame>shift, mac1, mac2: unroll + merged
+////////////////////////////////////////////////////////////////////////////////
+
+
+#include <ac_fixed.h>
+#include "sobel.h"
+#include <iostream>
+
+// shift_class: page 119 HLS Blue Book
+#include "shift_class.h" 
+
+
+
+
+#pragma hls_design top
+void sobel(ac_int<PIXEL_WL*KERNEL_WIDTH,false> vin[NUM_PIXELS], ac_int<PIXEL_WL,false> vout[NUM_PIXELS])
+{
+    ac_int<16, false> intensity, inte[KERNEL_WIDTH];
+    
+
+// #if 1: use filter
+// #if 0: copy input to output bypassing filter
+#if 1
+
+    // shifts pixels from KERNEL_WIDTH rows and keeps KERNEL_WIDTH columns (KERNEL_WIDTHxKERNEL_WIDTH pixels stored)
+    static shift_class<ac_int<PIXEL_WL*KERNEL_WIDTH,true>, KERNEL_WIDTH> regs;
+    int i;
+
+    FRAME: for(int p = 0; p < NUM_PIXELS; p++) {
+		// init
+		intensity = 0;
+		RESET: for(i = 0; i < KERNEL_WIDTH; i++) {
+			inte[i] = 0;
+		}
+	    
+		// shift input data in the filter fifo
+		regs << vin[p]; // advance the pointer address by the pixel number (testbench/simulation only)
+		// accumulate
+		ACC1: 
+		for (i = 0; i < KERNEL_WIDTH; ++i)
+		{
+		    inte[0] += (((regs[i].slc<COLOUR_WL>(2*COLOUR_WL))*XMATRIX[0][i])+((regs[i].slc<COLOUR_WL>(COLOUR_WL))*XMATRIX[0][i])+((regs[i].slc<COLOUR_WL>(0))*XMATRIX[0][i])) / 3;
+		    inte[0] += (((regs[i].slc<COLOUR_WL>(2*COLOUR_WL))*YMATRIX[0][i])+((regs[i].slc<COLOUR_WL>(COLOUR_WL))*YMATRIX[0][i])+((regs[i].slc<COLOUR_WL>(0))*YMATRIX[0][i])) / 3;
+		    
+		    inte[1] += (((regs[i].slc<COLOUR_WL>(2*COLOUR_WL + PIXEL_WL))*XMATRIX[1][i])+((regs[i].slc<COLOUR_WL>(COLOUR_WL + PIXEL_WL))*XMATRIX[1][i])+((regs[i].slc<COLOUR_WL>(PIXEL_WL))*XMATRIX[1][i])) / 3;
+		    inte[1] += (((regs[i].slc<COLOUR_WL>(2*COLOUR_WL + PIXEL_WL))*YMATRIX[1][i])+((regs[i].slc<COLOUR_WL>(COLOUR_WL + PIXEL_WL))*YMATRIX[1][i])+((regs[i].slc<COLOUR_WL>(PIXEL_WL))*YMATRIX[1][i])) / 3;
+		    
+		    inte[2] += (((regs[i].slc<COLOUR_WL>(2*COLOUR_WL + 2*PIXEL_WL))*XMATRIX[2][i])+((regs[i].slc<COLOUR_WL>(COLOUR_WL + 2*PIXEL_WL))*XMATRIX[2][i])+((regs[i].slc<COLOUR_WL>(2*PIXEL_WL))*XMATRIX[2][i])) / 3;
+		    inte[2] += (((regs[i].slc<COLOUR_WL>(2*COLOUR_WL + 2*PIXEL_WL))*YMATRIX[2][i])+((regs[i].slc<COLOUR_WL>(COLOUR_WL + 2*PIXEL_WL))*YMATRIX[2][i])+((regs[i].slc<COLOUR_WL>(2*PIXEL_WL))*YMATRIX[2][i])) / 3;
+		}
+		// add the accumualted value for all processed lines
+		ACC2: 
+		for(i = 0; i < KERNEL_WIDTH; i++) 
+		{    
+			intensity += inte[i];
+		}
+		
+
+		
+		// normalize result
+		intensity /= 2*KERNEL_NUMEL;
+	    
+		// group the RGB components into a single signal
+		vout[p] = ((((ac_int<PIXEL_WL, false>)intensity) << (2*COLOUR_WL)) | (((ac_int<PIXEL_WL, false>)intensity) << COLOUR_WL) | (ac_int<PIXEL_WL, false>)intensity);
+	    
+    }
+}   
+     
+     
+     
+     
+#else    
+// display input  (test only)
+    FRAME: for(p = 0; p < NUM_PIXELS; p++) {
+        // copy the value of each colour component from the input stream
+        red = vin[p].slc<COLOUR_WL>(2*COLOUR_WL);
+        green = vin[p].slc<COLOUR_WL>(COLOUR_WL);
+        blue = vin[p].slc<COLOUR_WL>(0);
+
+		// combine the 3 color components into 1 signal only
+        vout[p] = ((((ac_int<PIXEL_WL, false>)red) << (2*COLOUR_WL)) | (((ac_int<PIXEL_WL, false>)green) << COLOUR_WL) | (ac_int<PIXEL_WL, false>)blue);   
+    }
+}
+#endif
+
+
+// end of file
\ No newline at end of file
diff --git a/sobel.h b/sobel.h
new file mode 100644
index 0000000..dc6bb6f
--- /dev/null
+++ b/sobel.h
@@ -0,0 +1,91 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           sobel.h
+//  Description:    vga sobel - real-time processing
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// this hardware block receives the VGA stream and then produces a blured output
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           sobel.h
+//  Description:    vga sobel - real-time processing
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// this hardware block receives the VGA stream and then produces a blured output
+////////////////////////////////////////////////////////////////////////////////
+
+
+#ifndef _BLUR
+#define _BLUR
+
+#include <ac_int.h>
+#include <iostream>
+
+// total number of pixels from screen frame/image read in testbench
+#define NUM_PIXELS (640*480)
+
+#define KERNEL_WIDTH      3
+#define KERNEL_NUMEL      (KERNEL_WIDTH * KERNEL_WIDTH)
+#define COLOUR_WL         10
+#define PIXEL_WL          (3 * COLOUR_WL)
+
+#define  COORD_WL          10
+
+const int XMATRIX[KERNEL_WIDTH][KERNEL_WIDTH] = {{-1,0,1},{-2,0,2},{-1,0,1}};
+const int YMATRIX[KERNEL_WIDTH][KERNEL_WIDTH] = {{-1,-2,-1},{0,0,0},{1,2,1}};
+void sobel(ac_int<PIXEL_WL*KERNEL_WIDTH,false> vin[NUM_PIXELS], ac_int<PIXEL_WL,false> vout[NUM_PIXELS]);
+
+#endif
+#ifndef _BLUR
+#define _BLUR
+
+#include <ac_int.h>
+#include <iostream>
+
+// total number of pixels from screen frame/image read in testbench
+#define NUM_PIXELS (640*480)
+
+#define KERNEL_WIDTH      3
+#define KERNEL_NUMEL      (KERNEL_WIDTH * KERNEL_WIDTH)
+#define COLOUR_WL         10
+#define PIXEL_WL          (3 * COLOUR_WL)
+
+#define  COORD_WL          10
+
+const int XMATRIX[KERNEL_WIDTH][KERNEL_WIDTH] = {{-1,0,1},{-2,0,2},{-1,0,1}};
+const int YMATRIX[KERNEL_WIDTH][KERNEL_WIDTH] = {{-1,-2,-1},{0,0,0},{1,2,1}};
+void sobel(ac_int<PIXEL_WL*KERNEL_WIDTH,false> vin[NUM_PIXELS], ac_int<PIXEL_WL,false> vout[NUM_PIXELS]);
+
+#endif
\ No newline at end of file
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diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_wave0.jpg b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_wave0.jpg
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_wave0.jpg
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_waveforms.html b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_waveforms.html
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_waveforms.html
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._blur3x3 b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._blur3x3
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._blur3x3
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._mouse b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._mouse
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._mouse
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport_v2001.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport_v2001.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport_v2001.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport_v2001.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/._cbx_args.txt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/._cbx_args.txt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/._cbx_args.txt
diff --git a/student_files_2015/student_files_2015/.DS_Store b/student_files_2015/student_files_2015/.DS_Store
new file mode 100644
index 0000000..2095bfd
--- /dev/null
+++ b/student_files_2015/student_files_2015/.DS_Store
diff --git a/student_files_2015/student_files_2015/DE0_user_manual/.DS_Store b/student_files_2015/student_files_2015/DE0_user_manual/.DS_Store
new file mode 100644
index 0000000..5008ddf
--- /dev/null
+++ b/student_files_2015/student_files_2015/DE0_user_manual/.DS_Store
diff --git a/student_files_2015/student_files_2015/DE0_user_manual/DE0_User_manual_2012.pdf b/student_files_2015/student_files_2015/DE0_user_manual/DE0_User_manual_2012.pdf
new file mode 100644
index 0000000..c4831e1
--- /dev/null
+++ b/student_files_2015/student_files_2015/DE0_user_manual/DE0_User_manual_2012.pdf
diff --git a/student_files_2015/student_files_2015/launch_catapult.bat b/student_files_2015/student_files_2015/launch_catapult.bat
new file mode 100644
index 0000000..f6e649e
--- /dev/null
+++ b/student_files_2015/student_files_2015/launch_catapult.bat
@@ -0,0 +1,3 @@
+@echo off
+set Path=
+"C:\Program Files\Calypto Design Systems\Catapult Synthesis 2011a.126 Production Release\Mgc_home\bin\catapult.exe"
diff --git a/student_files_2015/student_files_2015/prj1/.DS_Store b/student_files_2015/student_files_2015/prj1/.DS_Store
new file mode 100644
index 0000000..fd7d3a6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/.DS_Store
diff --git a/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp b/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
new file mode 100644
index 0000000..8fc78d5
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
@@ -0,0 +1,39 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           dot_product.cpp
+//  Description:    dot product calculator
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+
+#include "dot_product.h"
+#include "stdio.h"
+
+#pragma design top
+void dot_product(ac_int<8> *input_a, ac_int<8> *input_b, ac_int<8> *output) {
+  ac_int<8> acc = 0;
+  int i; 
+
+  MAC: for(i = 0; i < VECTOR_LEN; i++) {
+    acc += input_a[i] * *(input_b + i); 
+    /* you can access the values in the vector in either way: var[i] = *(var + i) */
+  }
+  *output = acc;
+}
+
+
+// end of file
diff --git a/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h b/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
new file mode 100644
index 0000000..e67cc7f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
@@ -0,0 +1,35 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           dot_product.h
+//  Description:    dot product calculator
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+
+
+#ifndef _DOT_PROD_H
+#define _DOT_PROD_H
+
+#include "ac_int.h"
+
+#define VECTOR_LEN 5
+
+void dot_product(ac_int<8> *input_a, ac_int<8> *input_b, ac_int<8> *output);
+
+#endif
+
+// end of file
diff --git a/student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp b/student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
new file mode 100644
index 0000000..7f382cd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
@@ -0,0 +1,51 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           tb_dot_product.cpp
+//  Description:    dot product calculator testbench
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+
+#include "dot_product.h"
+#include <mc_scverify.h>
+
+CCS_MAIN(int argc, char *argv[])
+{
+  ac_int<8> inA[VECTOR_LEN] = {1,2,3,4,5};
+  ac_int<8> inB[VECTOR_LEN] = {5,4,3,2,1};
+  ac_int<8> output;
+  int i, exp_out;
+
+  // Test design
+  CCS_DESIGN(dot_product)(inA,inB,&output);
+
+  // Expected result  
+  exp_out = 0;
+  for(i = 0; i < VECTOR_LEN; i++) {
+    exp_out += inA[i] * inB[i];
+  }
+
+  // Display results
+  for(i = 0; i < VECTOR_LEN; i++) {
+    printf ("Inputs: A = %d, B = %d \n", (int)inA[i], (int)inB[i]);
+  }
+  printf ("Design output  : %d \n", (int)output);
+  printf ("Expected output: %d \n", exp_out);
+   
+  CCS_RETURN(0);
+}
+
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/.DS_Store b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/.DS_Store
new file mode 100644
index 0000000..5008ddf
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/.DS_Store
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf
new file mode 100644
index 0000000..3201f4d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf
@@ -0,0 +1,378 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 40 120 208 136)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "BUTTON[2..0]" (rect 5 0 74 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 112 32 120))
+)
+(pin
+	(input)
+	(rect 40 416 208 432)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "PS2_MSDAT" (rect 5 0 67 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 224 416 280 424))
+)
+(pin
+	(input)
+	(rect 40 440 208 456)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "PS2_MSCLK" (rect 5 0 67 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 232 440 288 456))
+)
+(pin
+	(input)
+	(rect 40 240 208 256)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[9]" (rect 5 0 35 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 240 32 256))
+)
+(pin
+	(input)
+	(rect 40 224 208 240)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[8]" (rect 5 0 35 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -32 208 24 224))
+)
+(pin
+	(input)
+	(rect 40 176 208 192)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[7..4]" (rect 5 0 48 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 176 32 192))
+)
+(pin
+	(input)
+	(rect 40 152 208 168)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[3..0]" (rect 5 0 48 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 136 32 152))
+)
+(pin
+	(input)
+	(rect 40 88 208 104)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "CLOCK_50" (rect 5 0 60 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 72 32 88))
+)
+(pin
+	(input)
+	(rect 40 56 208 72)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "CLOCK_50_2" (rect 5 0 72 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 40 32 56))
+)
+(pin
+	(output)
+	(rect 32 536 208 552)
+	(text "OUTPUT" (rect 140 0 178 10)(font "Arial" (font_size 6)))
+	(text "VGA_G[3..0]" (rect 5 0 67 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 179 8)(pt 127 8))
+		(line (pt 127 4)(pt 101 4))
+		(line (pt 127 12)(pt 101 12))
+		(line (pt 127 12)(pt 127 4))
+		(line (pt 101 4)(pt 97 8))
+		(line (pt 97 8)(pt 101 12))
+		(line (pt 101 12)(pt 97 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 248 536 272 544))
+)
+(pin
+	(output)
+	(rect 32 680 208 696)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_CLK" (rect 5 0 54 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
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+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "HEX0_D[6..0]" (rect 5 0 72 12)(font "Arial" ))
+	(pt 176 8)
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+	(pt 208 160)
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+	(pt 208 248)
+	(pt 216 248)
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+	(pt 216 128)
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diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.pin b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.pin
new file mode 100644
index 0000000..89fe5e1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		2.5V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+CHIP  "ise_proj"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GND+                         : AA11      :        :                   :         : 3         :                
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GND+                         : AB11      :        :                   :         : 3         :                
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+LEDG[9]                      : B1        : output : 2.5 V             :         : 1         : Y              
+LEDG[8]                      : B2        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
+GND+                         : B11       :        :                   :         : 8         :                
+CLOCK_50_2                   : B12       : input  : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+LEDG[6]                      : C1        : output : 2.5 V             :         : 1         : Y              
+LEDG[7]                      : C2        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
+SW[9]                        : D2        : input  : 2.5 V             :         : 1         : Y              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
+VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
+VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+LEDG[5]                      : E1        : output : 2.5 V             :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
+SW[7]                        : E3        : input  : 2.5 V             :         : 1         : Y              
+SW[8]                        : E4        : input  : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
+HEX0_D[0]                    : E11       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+BUTTON[2]                    : F1        : input  : 2.5 V             :         : 1         : Y              
+LEDG[4]                      : F2        : output : 2.5 V             :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+VGA_SYNC                     : F7        : output : 2.5 V             :         : 8         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
+HEX0_D[1]                    : F11       : output : 2.5 V             :         : 7         : Y              
+HEX0_D[5]                    : F12       : output : 2.5 V             :         : 7         : Y              
+HEX0_D[6]                    : F13       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+BUTTON[1]                    : G3        : input  : 2.5 V             :         : 1         : Y              
+SW[3]                        : G4        : input  : 2.5 V             :         : 1         : Y              
+SW[4]                        : G5        : input  : 2.5 V             :         : 1         : Y              
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+HEX0_D[4]                    : G12       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+CLOCK_50                     : G21       : input  : 2.5 V             :         : 6         : Y              
+GND+                         : G22       :        :                   :         : 6         :                
+LEDG[3]                      : H1        : output : 2.5 V             :         : 1         : Y              
+BUTTON[0]                    : H2        : input  : 2.5 V             :         : 1         : Y              
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
+SW[1]                        : H5        : input  : 2.5 V             :         : 1         : Y              
+SW[2]                        : H6        : input  : 2.5 V             :         : 1         : Y              
+SW[6]                        : H7        : input  : 2.5 V             :         : 1         : Y              
+GND                          : H8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+HEX0_D[2]                    : H12       : output : 2.5 V             :         : 7         : Y              
+HEX0_D[3]                    : H13       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+VGA_R[1]                     : H17       : output : 2.5 V             :         : 6         : Y              
+VGA_BLANK                    : H18       : output : 2.5 V             :         : 6         : N              
+VGA_R[0]                     : H19       : output : 2.5 V             :         : 6         : Y              
+VGA_R[2]                     : H20       : output : 2.5 V             :         : 6         : Y              
+VGA_R[3]                     : H21       : output : 2.5 V             :         : 6         : Y              
+VGA_G[0]                     : H22       : output : 2.5 V             :         : 6         : Y              
+LEDG[0]                      : J1        : output : 2.5 V             :         : 1         : Y              
+LEDG[1]                      : J2        : output : 2.5 V             :         : 1         : Y              
+LEDG[2]                      : J3        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+SW[0]                        : J6        : input  : 2.5 V             :         : 1         : Y              
+SW[5]                        : J7        : input  : 2.5 V             :         : 1         : Y              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+VGA_G[1]                     : J17       : output : 2.5 V             :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
+VGA_G[3]                     : J21       : output : 2.5 V             :         : 6         : Y              
+VGA_B[2]                     : J22       : output : 2.5 V             :         : 6         : Y              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+VGA_G[2]                     : K17       : output : 2.5 V             :         : 6         : Y              
+VGA_B[3]                     : K18       : output : 2.5 V             :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+VGA_B[1]                     : K21       : output : 2.5 V             :         : 6         : Y              
+VGA_B[0]                     : K22       : output : 2.5 V             :         : 6         : Y              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+VGA_HS                       : L21       : output : 2.5 V             :         : 6         : Y              
+VGA_VS                       : L22       : output : 2.5 V             :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+PS2_MSCLK                    : R21       : input  : 2.5 V             :         : 5         : Y              
+PS2_MSDAT                    : R22       : input  : 2.5 V             :         : 5         : Y              
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
+VGA_CLK                      : V16       : output : 2.5 V             :         : 4         : N              
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qpf b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qpf
new file mode 100644
index 0000000..57c6904
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 12.0 Build 178 05/31/2012 SJ Full Version
+# Date created = 04:19:33  August 08, 2012
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.0"
+DATE = "04:19:33  August 08, 2012"
+
+# Revisions
+
+PROJECT_REVISION = "ise_proj"
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qsf b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qsf
new file mode 100644
index 0000000..6ea48ba
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qsf
@@ -0,0 +1,683 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 12.0 Build 178 05/31/2012 SJ Full Version
+# Date created = 04:19:33  August 08, 2012
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ise_proj_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY ise_proj
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "04:19:33  AUGUST 08, 2012"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+set_location_assignment PIN_F1 -to BUTTON[2]
+set_location_assignment PIN_G3 -to BUTTON[1]
+set_location_assignment PIN_H2 -to BUTTON[0]
+set_location_assignment PIN_R2 -to FL_ADDR[21]
+set_location_assignment PIN_P3 -to FL_ADDR[20]
+set_location_assignment PIN_P1 -to FL_ADDR[19]
+set_location_assignment PIN_M6 -to FL_ADDR[18]
+set_location_assignment PIN_M5 -to FL_ADDR[17]
+set_location_assignment PIN_AA2 -to FL_ADDR[16]
+set_location_assignment PIN_L6 -to FL_ADDR[15]
+set_location_assignment PIN_L7 -to FL_ADDR[14]
+set_location_assignment PIN_M1 -to FL_ADDR[13]
+set_location_assignment PIN_M2 -to FL_ADDR[12]
+set_location_assignment PIN_M3 -to FL_ADDR[11]
+set_location_assignment PIN_N1 -to FL_ADDR[10]
+set_location_assignment PIN_N2 -to FL_ADDR[9]
+set_location_assignment PIN_P2 -to FL_ADDR[8]
+set_location_assignment PIN_M4 -to FL_ADDR[7]
+set_location_assignment PIN_M8 -to FL_ADDR[6]
+set_location_assignment PIN_N6 -to FL_ADDR[5]
+set_location_assignment PIN_N5 -to FL_ADDR[4]
+set_location_assignment PIN_N7 -to FL_ADDR[3]
+set_location_assignment PIN_P6 -to FL_ADDR[2]
+set_location_assignment PIN_P5 -to FL_ADDR[1]
+set_location_assignment PIN_P7 -to FL_ADDR[0]
+set_location_assignment PIN_AA1 -to FL_BYTE_N
+set_location_assignment PIN_N8 -to FL_CE_N
+set_location_assignment PIN_R7 -to FL_DQ[0]
+set_location_assignment PIN_P8 -to FL_DQ[1]
+set_location_assignment PIN_R8 -to FL_DQ[2]
+set_location_assignment PIN_U1 -to FL_DQ[3]
+set_location_assignment PIN_V2 -to FL_DQ[4]
+set_location_assignment PIN_V3 -to FL_DQ[5]
+set_location_assignment PIN_W1 -to FL_DQ[6]
+set_location_assignment PIN_Y1 -to FL_DQ[7]
+set_location_assignment PIN_T5 -to FL_DQ[8]
+set_location_assignment PIN_T7 -to FL_DQ[9]
+set_location_assignment PIN_T4 -to FL_DQ[10]
+set_location_assignment PIN_U2 -to FL_DQ[11]
+set_location_assignment PIN_V1 -to FL_DQ[12]
+set_location_assignment PIN_V4 -to FL_DQ[13]
+set_location_assignment PIN_W2 -to FL_DQ[14]
+set_location_assignment PIN_R6 -to FL_OE_N
+set_location_assignment PIN_R1 -to FL_RST_N
+set_location_assignment PIN_M7 -to FL_RY
+set_location_assignment PIN_P4 -to FL_WE_N
+set_location_assignment PIN_T3 -to FL_WP_N
+set_location_assignment PIN_Y2 -to FL_DQ15_AM1
+set_location_assignment PIN_U7 -to GPIO0_D[31]
+set_location_assignment PIN_V5 -to GPIO0_D[30]
+set_location_assignment PIN_W6 -to GPIO0_D[29]
+set_location_assignment PIN_W7 -to GPIO0_D[28]
+set_location_assignment PIN_V8 -to GPIO0_D[27]
+set_location_assignment PIN_T8 -to GPIO0_D[26]
+set_location_assignment PIN_W10 -to GPIO0_D[25]
+set_location_assignment PIN_Y10 -to GPIO0_D[24]
+set_location_assignment PIN_V11 -to GPIO0_D[23]
+set_location_assignment PIN_R10 -to GPIO0_D[22]
+set_location_assignment PIN_V12 -to GPIO0_D[21]
+set_location_assignment PIN_U13 -to GPIO0_D[20]
+set_location_assignment PIN_W13 -to GPIO0_D[19]
+set_location_assignment PIN_Y13 -to GPIO0_D[18]
+set_location_assignment PIN_U14 -to GPIO0_D[17]
+set_location_assignment PIN_V14 -to GPIO0_D[16]
+set_location_assignment PIN_AA4 -to GPIO0_D[15]
+set_location_assignment PIN_AB4 -to GPIO0_D[14]
+set_location_assignment PIN_AA5 -to GPIO0_D[13]
+set_location_assignment PIN_AB5 -to GPIO0_D[12]
+set_location_assignment PIN_AA8 -to GPIO0_D[11]
+set_location_assignment PIN_AB8 -to GPIO0_D[10]
+set_location_assignment PIN_AA10 -to GPIO0_D[9]
+set_location_assignment PIN_AB10 -to GPIO0_D[8]
+set_location_assignment PIN_AA13 -to GPIO0_D[7]
+set_location_assignment PIN_AB13 -to GPIO0_D[6]
+set_location_assignment PIN_AB14 -to GPIO0_D[5]
+set_location_assignment PIN_AA14 -to GPIO0_D[4]
+set_location_assignment PIN_AB15 -to GPIO0_D[3]
+set_location_assignment PIN_AA15 -to GPIO0_D[2]
+set_location_assignment PIN_AA16 -to GPIO0_D[1]
+set_location_assignment PIN_AB16 -to GPIO0_D[0]
+set_location_assignment PIN_AB12 -to GPIO0_CLKIN[0]
+set_location_assignment PIN_AA12 -to GPIO0_CLKIN[1]
+set_location_assignment PIN_AB3 -to GPIO0_CLKOUT[0]
+set_location_assignment PIN_AA3 -to GPIO0_CLKOUT[1]
+set_location_assignment PIN_AA11 -to GPIO1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO1_CLKIN[0]
+set_location_assignment PIN_T16 -to GPIO1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO1_CLKOUT[0]
+set_location_assignment PIN_V7 -to GPIO1_D[31]
+set_location_assignment PIN_V6 -to GPIO1_D[30]
+set_location_assignment PIN_U8 -to GPIO1_D[29]
+set_location_assignment PIN_Y7 -to GPIO1_D[28]
+set_location_assignment PIN_T9 -to GPIO1_D[27]
+set_location_assignment PIN_U9 -to GPIO1_D[26]
+set_location_assignment PIN_T10 -to GPIO1_D[25]
+set_location_assignment PIN_U10 -to GPIO1_D[24]
+set_location_assignment PIN_R12 -to GPIO1_D[23]
+set_location_assignment PIN_R11 -to GPIO1_D[22]
+set_location_assignment PIN_T12 -to GPIO1_D[21]
+set_location_assignment PIN_U12 -to GPIO1_D[20]
+set_location_assignment PIN_R14 -to GPIO1_D[19]
+set_location_assignment PIN_T14 -to GPIO1_D[18]
+set_location_assignment PIN_AB7 -to GPIO1_D[17]
+set_location_assignment PIN_AA7 -to GPIO1_D[16]
+set_location_assignment PIN_AA9 -to GPIO1_D[15]
+set_location_assignment PIN_AB9 -to GPIO1_D[14]
+set_location_assignment PIN_V15 -to GPIO1_D[13]
+set_location_assignment PIN_W15 -to GPIO1_D[12]
+set_location_assignment PIN_T15 -to GPIO1_D[11]
+set_location_assignment PIN_U15 -to GPIO1_D[10]
+set_location_assignment PIN_W17 -to GPIO1_D[9]
+set_location_assignment PIN_Y17 -to GPIO1_D[8]
+set_location_assignment PIN_AB17 -to GPIO1_D[7]
+set_location_assignment PIN_AA17 -to GPIO1_D[6]
+set_location_assignment PIN_AA18 -to GPIO1_D[5]
+set_location_assignment PIN_AB18 -to GPIO1_D[4]
+set_location_assignment PIN_AB19 -to GPIO1_D[3]
+set_location_assignment PIN_AA19 -to GPIO1_D[2]
+set_location_assignment PIN_AB20 -to GPIO1_D[1]
+set_location_assignment PIN_AA20 -to GPIO1_D[0]
+set_location_assignment PIN_P22 -to PS2_KBCLK
+set_location_assignment PIN_P21 -to PS2_KBDAT
+set_location_assignment PIN_R21 -to PS2_MSCLK
+set_location_assignment PIN_R22 -to PS2_MSDAT
+set_location_assignment PIN_U22 -to UART_RXD
+set_location_assignment PIN_U21 -to UART_TXD
+set_location_assignment PIN_V22 -to UART_RTS
+set_location_assignment PIN_V21 -to UART_CTS
+set_location_assignment PIN_Y21 -to SD_CLK
+set_location_assignment PIN_Y22 -to SD_CMD
+set_location_assignment PIN_AA22 -to SD_DAT0
+set_location_assignment PIN_W21 -to SD_DAT3
+set_location_assignment PIN_W20 -to SD_WP_N
+set_location_assignment PIN_C20 -to LCD_DATA[7]
+set_location_assignment PIN_D20 -to LCD_DATA[6]
+set_location_assignment PIN_B21 -to LCD_DATA[5]
+set_location_assignment PIN_B22 -to LCD_DATA[4]
+set_location_assignment PIN_C21 -to LCD_DATA[3]
+set_location_assignment PIN_C22 -to LCD_DATA[2]
+set_location_assignment PIN_D21 -to LCD_DATA[1]
+set_location_assignment PIN_D22 -to LCD_DATA[0]
+set_location_assignment PIN_E22 -to LCD_RW
+set_location_assignment PIN_F22 -to LCD_RS
+set_location_assignment PIN_E21 -to LCD_EN
+set_location_assignment PIN_F21 -to LCD_BLON
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+set_location_assignment PIN_G21 -to CLOCK_50
+set_location_assignment PIN_E11 -to HEX0_D[0]
+set_location_assignment PIN_F11 -to HEX0_D[1]
+set_location_assignment PIN_H12 -to HEX0_D[2]
+set_location_assignment PIN_H13 -to HEX0_D[3]
+set_location_assignment PIN_G12 -to HEX0_D[4]
+set_location_assignment PIN_F12 -to HEX0_D[5]
+set_location_assignment PIN_F13 -to HEX0_D[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+set_location_assignment PIN_A15 -to HEX1_D[6]
+set_location_assignment PIN_E14 -to HEX1_D[5]
+set_location_assignment PIN_B14 -to HEX1_D[4]
+set_location_assignment PIN_A14 -to HEX1_D[3]
+set_location_assignment PIN_C13 -to HEX1_D[2]
+set_location_assignment PIN_B13 -to HEX1_D[1]
+set_location_assignment PIN_A13 -to HEX1_D[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+set_location_assignment PIN_F14 -to HEX2_D[6]
+set_location_assignment PIN_B17 -to HEX2_D[5]
+set_location_assignment PIN_A17 -to HEX2_D[4]
+set_location_assignment PIN_E15 -to HEX2_D[3]
+set_location_assignment PIN_B16 -to HEX2_D[2]
+set_location_assignment PIN_A16 -to HEX2_D[1]
+set_location_assignment PIN_D15 -to HEX2_D[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+set_location_assignment PIN_G15 -to HEX3_D[6]
+set_location_assignment PIN_D19 -to HEX3_D[5]
+set_location_assignment PIN_C19 -to HEX3_D[4]
+set_location_assignment PIN_B19 -to HEX3_D[3]
+set_location_assignment PIN_A19 -to HEX3_D[2]
+set_location_assignment PIN_F15 -to HEX3_D[1]
+set_location_assignment PIN_B18 -to HEX3_D[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+set_location_assignment PIN_B12 -to CLOCK_50_2
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_TOP -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id "Root Region"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_VGA -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id "Root Region"
+set_location_assignment PIN_F1 -to KEY[2]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_U7 -to GPIO_0[31]
+set_location_assignment PIN_V5 -to GPIO_0[30]
+set_location_assignment PIN_W6 -to GPIO_0[29]
+set_location_assignment PIN_W7 -to GPIO_0[28]
+set_location_assignment PIN_V8 -to GPIO_0[27]
+set_location_assignment PIN_T8 -to GPIO_0[26]
+set_location_assignment PIN_W10 -to GPIO_0[25]
+set_location_assignment PIN_Y10 -to GPIO_0[24]
+set_location_assignment PIN_V11 -to GPIO_0[23]
+set_location_assignment PIN_R10 -to GPIO_0[22]
+set_location_assignment PIN_V12 -to GPIO_0[21]
+set_location_assignment PIN_U13 -to GPIO_0[20]
+set_location_assignment PIN_W13 -to GPIO_0[19]
+set_location_assignment PIN_Y13 -to GPIO_0[18]
+set_location_assignment PIN_U14 -to GPIO_0[17]
+set_location_assignment PIN_V14 -to GPIO_0[16]
+set_location_assignment PIN_AA4 -to GPIO_0[15]
+set_location_assignment PIN_AB4 -to GPIO_0[14]
+set_location_assignment PIN_AA5 -to GPIO_0[13]
+set_location_assignment PIN_AB5 -to GPIO_0[12]
+set_location_assignment PIN_AA8 -to GPIO_0[11]
+set_location_assignment PIN_AB8 -to GPIO_0[10]
+set_location_assignment PIN_AA10 -to GPIO_0[9]
+set_location_assignment PIN_AB10 -to GPIO_0[8]
+set_location_assignment PIN_AA13 -to GPIO_0[7]
+set_location_assignment PIN_AB13 -to GPIO_0[6]
+set_location_assignment PIN_AB14 -to GPIO_0[5]
+set_location_assignment PIN_AA14 -to GPIO_0[4]
+set_location_assignment PIN_AB15 -to GPIO_0[3]
+set_location_assignment PIN_AA15 -to GPIO_0[2]
+set_location_assignment PIN_AA16 -to GPIO_0[1]
+set_location_assignment PIN_AB16 -to GPIO_0[0]
+set_location_assignment PIN_AB12 -to GPIO_CLKIN_N0
+set_location_assignment PIN_AA12 -to GPIO_CLKIN_P0
+set_location_assignment PIN_AB3 -to GPIO_CLKOUT_N0
+set_location_assignment PIN_AA3 -to GPIO_CLKOUT_P0
+set_location_assignment PIN_AA11 -to GPIO_CLKIN_P1
+set_location_assignment PIN_AB11 -to GPIO_CLKIN_N1
+set_location_assignment PIN_T16 -to GPIO_CLKOUT_P1
+set_location_assignment PIN_R16 -to GPIO_CLKOUT_N1
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+set_location_assignment PIN_E11 -to HEX0[0]
+set_location_assignment PIN_F11 -to HEX0[1]
+set_location_assignment PIN_H12 -to HEX0[2]
+set_location_assignment PIN_H13 -to HEX0[3]
+set_location_assignment PIN_G12 -to HEX0[4]
+set_location_assignment PIN_F12 -to HEX0[5]
+set_location_assignment PIN_F13 -to HEX0[6]
+set_location_assignment PIN_D13 -to HEX0[7]
+set_location_assignment PIN_A15 -to HEX1[6]
+set_location_assignment PIN_E14 -to HEX1[5]
+set_location_assignment PIN_B14 -to HEX1[4]
+set_location_assignment PIN_A14 -to HEX1[3]
+set_location_assignment PIN_C13 -to HEX1[2]
+set_location_assignment PIN_B13 -to HEX1[1]
+set_location_assignment PIN_A13 -to HEX1[0]
+set_location_assignment PIN_B15 -to HEX1[7]
+set_location_assignment PIN_F14 -to HEX2[6]
+set_location_assignment PIN_B17 -to HEX2[5]
+set_location_assignment PIN_A17 -to HEX2[4]
+set_location_assignment PIN_E15 -to HEX2[3]
+set_location_assignment PIN_B16 -to HEX2[2]
+set_location_assignment PIN_A16 -to HEX2[1]
+set_location_assignment PIN_D15 -to HEX2[0]
+set_location_assignment PIN_A18 -to HEX2[7]
+set_location_assignment PIN_G15 -to HEX3[6]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_C19 -to HEX3[4]
+set_location_assignment PIN_B19 -to HEX3[3]
+set_location_assignment PIN_A19 -to HEX3[2]
+set_location_assignment PIN_F15 -to HEX3[1]
+set_location_assignment PIN_B18 -to HEX3[0]
+set_location_assignment PIN_G16 -to HEX3[7]
+set_location_assignment PIN_B5 -to DRAM_BA[0]
+set_location_assignment PIN_A4 -to DRAM_BA[1]
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/.DS_Store b/student_files_2015/student_files_2015/prj2/.DS_Store
new file mode 100644
index 0000000..d3509f7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/.DS_Store
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/.DS_Store b/student_files_2015/student_files_2015/prj2/catapult_proj/.DS_Store
new file mode 100644
index 0000000..7eb20ea
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/.DS_Store
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/blur.c b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/blur.c
new file mode 100644
index 0000000..37811dc
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/blur.c
@@ -0,0 +1,136 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           blur.cpp
+//  Description:    video to vga blur filter - real-time processing
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// this hardware block receives the VGA stream and then produces a blured output
+// based on the FIR design - page 230 of HLS Blue Book
+////////////////////////////////////////////////////////////////////////////////
+// Catapult Project options
+// Constraint Editor:
+//  Frequency: 27 MHz
+//  Top design: vga_blur
+//  clk>reset sync: disable; reset async: enable; enable: enable
+// Architecture Constraints:
+//  interface>vin: wordlength = 150, streaming = 150
+//  interface>vout: wordlength = 30, streaming = 30
+//  core>main: pipeline + distributed + merged
+//  core>main>frame: merged
+//  core>main>frame>shift, mac1, mac2: unroll + merged
+////////////////////////////////////////////////////////////////////////////////
+
+
+#include <ac_fixed.h>
+#include "blur.h"
+#include <iostream>
+
+// shift_class: page 119 HLS Blue Book
+#include "shift_class.h" 
+
+
+
+
+#pragma hls_design top
+void mean_vga(ac_int<PIXEL_WL*KERNEL_WIDTH,false> vin[NUM_PIXELS], ac_int<PIXEL_WL,false> vout[NUM_PIXELS])
+{
+    ac_int<16, false> red, green, blue, r[KERNEL_WIDTH], g[KERNEL_WIDTH], b[KERNEL_WIDTH];
+    
+
+// #if 1: use filter
+// #if 0: copy input to output bypassing filter
+#if 1
+
+    // shifts pixels from KERNEL_WIDTH rows and keeps KERNEL_WIDTH columns (KERNEL_WIDTHxKERNEL_WIDTH pixels stored)
+    static shift_class<ac_int<PIXEL_WL*KERNEL_WIDTH,false>, KERNEL_WIDTH> regs;
+    int i;
+
+    FRAME: for(int p = 0; p < NUM_PIXELS; p++) {
+		// init
+		red = 0; 
+		green = 0; 
+		blue = 0;
+		RESET: for(i = 0; i < KERNEL_WIDTH; i++) {
+			r[i] = 0;
+			g[i] = 0;
+			b[i] = 0;
+		}
+	    
+		// shift input data in the filter fifo
+		regs << vin[p]; // advance the pointer address by the pixel number (testbench/simulation only)
+		// accumulate
+		ACC1: for(i = 0; i < KERNEL_WIDTH; i++) {
+			// current line
+			r[0] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL));
+			g[0] += (regs[i].slc<COLOUR_WL>(COLOUR_WL));
+			b[0] += (regs[i].slc<COLOUR_WL>(0));
+			// the line before ...
+			r[1] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL + PIXEL_WL));
+			g[1] += (regs[i].slc<COLOUR_WL>(COLOUR_WL + PIXEL_WL));
+			b[1] += (regs[i].slc<COLOUR_WL>(0 + PIXEL_WL));
+			// the line before ...
+			r[2] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL + 2*PIXEL_WL));
+			g[2] += (regs[i].slc<COLOUR_WL>(COLOUR_WL + 2*PIXEL_WL)) ;
+			b[2] += (regs[i].slc<COLOUR_WL>(0 + 2*PIXEL_WL)) ;
+			// the line before ... 
+			r[3] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL + 3*PIXEL_WL));
+			g[3] += (regs[i].slc<COLOUR_WL>(COLOUR_WL + 3*PIXEL_WL)) ;
+			b[3] += (regs[i].slc<COLOUR_WL>(0 + 3*PIXEL_WL)) ;
+			// the line before ...
+			r[4] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL + 4*PIXEL_WL));
+			g[4] += (regs[i].slc<COLOUR_WL>(COLOUR_WL + 4*PIXEL_WL)) ;
+			b[4] += (regs[i].slc<COLOUR_WL>(0 + 4*PIXEL_WL)) ;
+		}
+		// add the accumualted value for all processed lines
+		ACC2: for(i = 0; i < KERNEL_WIDTH; i++) {    
+			red += r[i];
+			green += g[i];
+			blue += b[i];
+		}
+		// normalize result
+		red /= KERNEL_NUMEL;
+		green /= KERNEL_NUMEL;
+		blue /= KERNEL_NUMEL;
+	    
+		// group the RGB components into a single signal
+		vout[p] = ((((ac_int<PIXEL_WL, false>)red) << (2*COLOUR_WL)) | (((ac_int<PIXEL_WL, false>)green) << COLOUR_WL) | (ac_int<PIXEL_WL, false>)blue);
+	    
+    }
+}
+     
+     
+     
+     
+     
+     
+#else    
+// display input  (test only)
+    FRAME: for(p = 0; p < NUM_PIXELS; p++) {
+        // copy the value of each colour component from the input stream
+        red = vin[p].slc<COLOUR_WL>(2*COLOUR_WL);
+        green = vin[p].slc<COLOUR_WL>(COLOUR_WL);
+        blue = vin[p].slc<COLOUR_WL>(0);
+
+		// combine the 3 color components into 1 signal only
+        vout[p] = ((((ac_int<PIXEL_WL, false>)red) << (2*COLOUR_WL)) | (((ac_int<PIXEL_WL, false>)green) << COLOUR_WL) | (ac_int<PIXEL_WL, false>)blue);   
+    }
+}
+#endif
+
+
+// end of file
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/blur.h b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/blur.h
new file mode 100644
index 0000000..565b7c3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/blur.h
@@ -0,0 +1,45 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           blur.h
+//  Description:    vga blur - real-time processing
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// this hardware block receives the VGA stream and then produces a blured output
+////////////////////////////////////////////////////////////////////////////////
+
+
+#ifndef _BLUR
+#define _BLUR
+
+#include <ac_int.h>
+#include <iostream>
+
+// total number of pixels from screen frame/image read in testbench
+#define NUM_PIXELS (640*480)
+
+#define KERNEL_WIDTH      5
+#define KERNEL_NUMEL      (KERNEL_WIDTH * KERNEL_WIDTH)
+#define COLOUR_WL         10
+#define PIXEL_WL          (3 * COLOUR_WL)
+
+#define  COORD_WL          10
+
+
+void mean_vga(ac_int<PIXEL_WL*KERNEL_WIDTH,false> vin[NUM_PIXELS], ac_int<PIXEL_WL,false> vout[NUM_PIXELS]);
+
+#endif
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.cpp b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.cpp
new file mode 100644
index 0000000..a3d7bff
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.cpp
@@ -0,0 +1,2967 @@
+#include <cstdlib>
+#include <iostream>
+#include <iomanip>
+#include <fstream>
+
+using namespace std;
+
+#include "bmp_io.h"
+
+//
+//  BMP_BYTE_SWAP controls how the program assumes that the bytes in 
+//  multi-byte data are ordered.
+//
+//  "true" is the correct value to use when running on a little-endian machine,
+//  and "false" is for big-endian.
+//
+
+static bool bmp_byte_swap = true;
+
+//****************************************************************************80
+
+bool bmp_byte_swap_get ( void )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_BYTE_SWAP_GET returns the internal value of BMP_BYTE_SWAP.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    26 February 2003
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, bool BMP_BYTE_SWAP_GET, the internal value of BMP_BYTE_SWAP.
+//
+{
+  return bmp_byte_swap;
+}
+//****************************************************************************80
+
+void bmp_byte_swap_set ( bool value )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_BYTE_SWAP_SET sets the internal value of BMP_BYTE_SWAP.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    26 February 2003
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, bool VALUE, the new value of BMP_BYTE_SWAP.
+//
+{
+  bmp_byte_swap = value;
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_08_data_read ( ifstream &file_in, unsigned long int width, 
+  long int height, unsigned char *rarray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_08_DATA_READ reads 8 bit image data of the BMP file.
+// 
+//  Discussion:
+//
+//    On output, the RGB information in the file has been copied into the
+//    R, G and B arrays.
+//
+//    Thanks to Peter Kionga-Kamau for pointing out an error in the
+//    previous implementation.
+//
+//    The standard ">>" operator cannot be used to transfer data, because
+//    it will be deceived by characters that "look like" new lines.
+//
+//    Thanks to Kelly Anderson for pointing out how to modify the program
+//    to handle monochrome images.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    01 April 2005
+//
+//  Author:
+//
+//    Kelly Anderson
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, a pointer to the red color arrays.
+//
+//    Output, bool BMP_08_DATA_READ, is true if an error occurred.
+//
+{
+  char c;
+  bool error;
+  int i;
+  unsigned int i2;
+  unsigned char *indexr;
+  int j;
+  int numbyte;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 1 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+  numbyte = 0;
+
+  for ( j = 0; j < abs ( height ); j++ ) 
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error ) 
+      {
+        cout << "\n";
+        cout << "BMP_08_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading R for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexr = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexr = indexr + 1;
+    }
+//
+//  If necessary, read a few padding characters.
+//
+    for ( i = 0; i < padding; i++ )
+    {
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error )
+      {
+        cout << "\n";
+        cout << "BMP_08_DATA_READ - Warning!\n";
+        cout << "  Failed while reading padding character " << i << "\n";
+        cout << "  of total " << padding << " characters\n";
+        cout << "  at the end of line " << j << "\n";
+        cout << "\n";
+        cout << "  This is a minor error.\n";
+        return false;
+      }
+    }
+  }
+
+  return false;
+}
+//****************************************************************************80
+
+void bmp_08_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_08_DATA_WRITE writes 8 bit image data to a BMP file.
+//
+//  Discussion:
+//
+//    This routine does not seem to be performing properly.  The monochrome
+//    images it creates cannot be read by the XV program, which says that 
+//    they seem to have been prematurely truncated.
+//
+//    The BMP format requires that each horizontal line be a multiple of 4 bytes.
+//    If the data itself does not have a WIDTH that is a multiple of 4, then
+//    the file must be padded with a few extra bytes so that each line has the
+//    appropriate length.  This information, and the corresponding corrective
+//    code, was supplied by Lee Mulcahy.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    02 April 2005
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image in bytes.
+//
+//    Input, long int HEIGHT, the Y dimension of the image in bytes.
+//
+//    Input, unsigned char *RARRAY, pointer to the red color array.
+//
+{
+  int i;
+  unsigned int i2;
+  unsigned char *indexr;
+  int j;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 1 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+
+  for ( j = 0; j < abs ( height ); j++ )
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+      file_out << *indexr;
+      indexr = indexr + 1;
+    }
+
+    for ( i = 0; i < padding; i++ )
+    {
+      file_out << 0;
+    }
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_24_data_read ( ifstream &file_in, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, 
+  unsigned char *barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_24_DATA_READ reads 24 bit image data of the BMP file.
+// 
+//  Discussion:
+//
+//    On output, the RGB information in the file has been copied into the
+//    R, G and B arrays.
+//
+//    Thanks to Peter Kionga-Kamau for pointing out an error in the
+//    previous implementation.
+//
+//    The standard ">>" operator cannot be used to transfer data, because
+//    it will be deceived by characters that "look like" new lines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    11 December 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, *GARRAY, *BARRAY, pointers to the 
+//    red, green and blue color arrays.
+//
+//    Output, bool BMP_24_DATA_READ, is true if an error occurred.
+//
+{
+  char c;
+  bool error;
+  int i;
+  unsigned int i2;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+  int j;
+  int numbyte;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 3 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+  indexg = garray;
+  indexb = barray;
+  numbyte = 0;
+
+  for ( j = 0; j < abs ( height ); j++ ) 
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error )
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading B for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexb = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexb = indexb + 1;
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error ) 
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading G for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexg = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexg = indexg + 1;
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error ) 
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading R for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexr = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexr = indexr + 1;
+    }
+//
+//  If necessary, read a few padding characters.
+//
+    for ( i = 0; i < padding; i++ )
+    {
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error )
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ - Warning!\n";
+        cout << "  Failed while reading padding character " << i << "\n";
+        cout << "  of total " << padding << " characters\n";
+        cout << "  at the end of line " << j << "\n";
+        cout << "\n";
+        cout << "  This is a minor error.\n";
+        return false;
+      }
+    }
+  }
+
+  return false;
+}
+//****************************************************************************80
+
+void bmp_24_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, 
+  unsigned char *barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_24_DATA_WRITE writes 24 bit image data to the BMP file.
+//
+//  Discussion:
+//
+//    The BMP format requires that each horizontal line be a multiple of 4 bytes.
+//    If the data itself does not have a WIDTH that is a multiple of 4, then
+//    the file must be padded with a few extra bytes so that each line has the
+//    appropriate length.  This information, and the corresponding corrective
+//    code, was supplied by Lee Mulcahy.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    11 December 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image in bytes.
+//
+//    Input, long int HEIGHT, the Y dimension of the image in bytes.
+//
+//    Input, unsigned char *RARRAY, *GARRAY, *BARRAY, pointers to the red, green
+//    and blue color arrays.
+//
+{
+  int i;
+  unsigned int i2;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+  int j;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 3 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+  indexg = garray;
+  indexb = barray;
+
+  for ( j = 0; j < abs ( height ); j++ )
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+      file_out << *indexb;
+      file_out << *indexg;
+      file_out << *indexr;
+
+      indexb = indexb + 1;
+      indexg = indexg + 1;
+      indexr = indexr + 1;
+    }
+
+    for ( i = 0; i < padding; i++ )
+    {
+      file_out << 0;
+    }
+  }
+
+  return;
+}
+//****************************************************************************80
+
+void bmp_header1_print ( unsigned short int filetype, 
+  unsigned long int filesize, unsigned short int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER1_PRINT prints the header information of a BMP file.
+//
+//  Discussion:
+//
+//    The header comprises 14 bytes:
+//
+//    2 bytes FILETYPE;        Magic number: "BM",
+//    4 bytes FILESIZE;        Size of file in 32 byte integers,
+//    2 bytes RESERVED1;       Always 0,
+//    2 bytes RESERVED2;       Always 0,
+//    4 bytes BITMAPOFFSET.    Starting position of image data, in bytes.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    05 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, unsigned short int FILETYPE, the file type.
+//
+//    Input, unsigned long int FILESIZE, the file size.
+//
+//    Input, unsigned short int RESERVED1, a reserved value.
+//
+//    Input, unsigned short int RESERVED2, a reserved value.
+//
+//    Input, unsigned long int BITMAPOFFSET, the bitmap offset.
+//
+{
+  cout << "\n";
+  cout << "  Contents of BMP file header:\n";
+  cout << "\n";
+  cout << "    FILETYPE =     " << filetype     << "\n";
+  cout << "    FILESIZE =     " << filesize     << "\n";
+  cout << "    RESERVED1 =    " << reserved1    << "\n";
+  cout << "    RESERVED2 =    " << reserved2    << "\n";
+  cout << "    BITMAPOFFSET = " << bitmapoffset << "\n";
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_header1_read ( ifstream &file_in, unsigned short int *filetype, 
+  unsigned long int *filesize, unsigned short int *reserved1, 
+  unsigned short int *reserved2, unsigned long int *bitmapoffset )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER1_READ reads the header information of a BMP file.
+//
+//  Discussion:
+//
+//    The header comprises 14 bytes:
+//
+//    2 bytes FILETYPE;        Magic number: "BM",
+//    4 bytes FILESIZE;        Size of file in 32 byte integers,
+//    2 bytes RESERVED1;       Always 0,
+//    2 bytes RESERVED2;       Always 0,
+//    4 bytes BITMAPOFFSET.    Starting position of image data, in bytes.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    15 December 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, unsigned short int *FILETYPE, the file type.
+//
+//    Output, unsigned long int *FILESIZE, the file size.
+//
+//    Output, unsigned short int *RESERVED1, a reserved value.
+//
+//    Output, unsigned short int *RESERVED2, a reserved value.
+//
+//    Output, unsigned long int *BITMAPOFFSET, the bitmap offset.
+//
+{
+  bool error;
+  char i1;
+  char i2;  
+//
+//  Read FILETYPE.
+//
+  error = u_short_int_read ( filetype, file_in );
+
+  if ( error )
+  {
+    return error;
+  }
+//
+//  If you are doing swapping, you have to reunswap the filetype, I think, JVB 15 December 2004.
+//
+  if ( bmp_byte_swap )
+  {
+    i1 = ( char ) ( *filetype / 256 );
+    i2 = ( char ) ( *filetype % 256 );
+    *filetype = i2 * 256 + i1;
+  }
+//
+//  Read FILESIZE.
+//
+  error = u_long_int_read ( filesize, file_in );
+  if ( error ) 
+  {
+    return error;
+  }
+//
+//  Read RESERVED1.
+//
+  error = u_short_int_read ( reserved1, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read RESERVED2.
+//
+  error = u_short_int_read ( reserved2, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read BITMAPOFFSET.
+//
+  error = u_long_int_read ( bitmapoffset, file_in );
+  if ( error )
+  {
+    return error;
+  }
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+void bmp_header1_write ( ofstream &file_out, unsigned short int filetype,
+  unsigned long int filesize, unsigned short int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER1_WRITE writes the header information to a BMP file.
+//
+//  Discussion:
+//
+//    The header comprises 14 bytes:
+//
+//    2 bytes FILETYPE;        Magic number: "BM",
+//    4 bytes FILESIZE;        Size of file in 32 byte integers,
+//    2 bytes RESERVED1;       Always 0,
+//    2 bytes RESERVED2;       Always 0,
+//    4 bytes BITMAPOFFSET.    Starting position of image data, in bytes.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    04 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned short int FILETYPE, the file type.
+//
+//    Input, unsigned long int FILESIZE, the file size.
+//
+//    Input, unsigned short int RESERVED1, a reserved value.
+//
+//    Input, unsigned short int RESERVED2, a reserved value.
+//
+//    Input, unsigned long int BITMAPOFFSET, the bitmap offset.
+//
+{
+  u_short_int_write ( filetype, file_out );
+  u_long_int_write ( filesize, file_out );
+  u_short_int_write ( reserved1, file_out );
+  u_short_int_write ( reserved2, file_out );
+  u_long_int_write ( bitmapoffset, file_out );
+
+  return;
+}
+//****************************************************************************80
+
+void bmp_header2_print ( unsigned long int size, unsigned long int width, 
+  long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel, 
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused,  unsigned long int colorsimportant )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER2_PRINT prints the bitmap header information of a BMP file.
+//
+//  Discussion:
+//
+//    The bitmap header is 40 bytes long:
+//
+//    4 bytes SIZE;                Size of this header ( = 40 bytes).
+//    4 bytes WIDTH;               Image width, in pixels.   
+//    4 bytes HEIGHT;              Image height, in pixels.  
+//                                 (Pos/Neg, origin at bottom, top)
+//    2 bytes PLANES;              Number of color planes (always 1).
+//    2 bytes BITSPERPIXEL;        1 to 24.  1, 4, 8, 16, 24 or 32.
+//    4 bytes COMPRESSION;         0, uncompressed; 1, 8 bit RLE; 
+//                                 2, 4 bit RLE; 3, bitfields.
+//    4 bytes SIZEOFBITMAP;        Size of bitmap in bytes. (0 if uncompressed).
+//    4 bytes HORZRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes VERTRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes COLORSUSED;          Number of colors in palette.  (Can be zero).
+//    4 bytes COLORSIMPORTANT.     Minimum number of important colors. (Can be zero).
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    06 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, unsigned short int SIZE, the size of this header in bytes.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned short int PLANES, the number of color planes.
+//
+//    Input, unsigned short int BITSPERPIXEL, color bits per pixel.
+//
+//    Input, unsigned long int COMPRESSION, the compression option.
+//
+//    Input, unsigned long int SIZEOFBITMAP, the size of the bitmap.
+//
+//    Input, unsigned long int HORZRESOLUTION, the horizontal resolution.
+//
+//    Input, unsigned long int VERTRESOLUTION, the vertical resolution.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned long int COLORSIMPORTANT, the minimum number of colors.
+//
+{
+  cout << "\n";
+  cout << "  Contents of BMP file bitmap header:\n";
+  cout << "\n";
+  cout << "    SIZE =            " << size            << "\n";
+  cout << "    WIDTH =           " << width           << "\n";
+  cout << "    HEIGHT =          " << height          << "\n";
+  cout << "    PLANES =          " << planes          << "\n";
+  cout << "    BITSPERPIXEL =    " << bitsperpixel    << "\n";
+  cout << "    COMPRESSION =     " << compression     << "\n";
+  cout << "    SIZEOFBITMAP =    " << sizeofbitmap    << "\n";
+  cout << "    HORZRESOLUTION =  " << horzresolution  << "\n";
+  cout << "    VERTRESOLUTION =  " << vertresolution  << "\n";
+  cout << "    COLORSUSED =      " << colorsused      << "\n";
+  cout << "    COLORSIMPORTANT = " << colorsimportant << "\n";
+
+  return;
+} 
+//****************************************************************************80
+
+bool bmp_header2_read ( ifstream &file_in, unsigned long int *size,
+  unsigned long int *width, long int *height, 
+  unsigned short int *planes, unsigned short int *bitsperpixel,
+  unsigned long int *compression, unsigned long int *sizeofbitmap,
+  unsigned long int *horzresolution, unsigned long int *vertresolution,
+  unsigned long int *colorsused, unsigned long int *colorsimportant )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER2_READ reads the bitmap header information of a BMP file.
+//
+//  Discussion:
+//
+//    The bitmap header is 40 bytes long:
+//
+//    4 bytes SIZE;                Size of this header, in bytes.
+//    4 bytes WIDTH;               Image width, in pixels.   
+//    4 bytes HEIGHT;              Image height, in pixels.  
+//                                 (Pos/Neg, origin at bottom, top)
+//    2 bytes PLANES;              Number of color planes (always 1).
+//    2 bytes BITSPERPIXEL;        1 to 24.  1, 4, 8, 16, 24 or 32.
+//    4 bytes COMPRESSION;         0, uncompressed; 1, 8 bit RLE; 
+//                                 2, 4 bit RLE; 3, bitfields.
+//    4 bytes SIZEOFBITMAP;        Size of bitmap in bytes. (0 if uncompressed).
+//    4 bytes HORZRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes VERTRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes COLORSUSED;          Number of colors in palette.  (Can be zero).
+//    4 bytes COLORSIMPORTANT.     Minimum number of important colors. (Can be zero).
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    03 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, unsigned long int *SIZE, the size of this header in bytes.
+//
+//    Output, unsigned long int *WIDTH, the X dimension of the image.
+//
+//    Output, long int *HEIGHT, the Y dimension of the image.
+//
+//    Output, unsigned short int *PLANES, the number of color planes.
+//
+//    Output, unsigned short int *BITSPERPIXEL, color bits per pixel.
+//
+//    Output, unsigned long int *COMPRESSION, the compression option.
+//
+//    Output, unsigned long int *SIZEOFBITMAP, the size of the bitmap.
+//
+//    Output, unsigned long int *HORZRESOLUTION, the horizontal resolution.
+//
+//    Output, unsigned long int *VERTRESOLUTION, the vertical resolution.
+//
+//    Output, unsigned long int *COLORSUSED, the number of colors in the palette.
+//
+//    Output, unsigned long int *COLORSIMPORTANT, the minimum number of colors.
+//
+//    Output, bool BMP_HEADER2_READ, is true if an error occurred.
+//
+{
+  bool error;
+//
+//  Read SIZE, the size of the header in bytes.
+//
+  error = u_long_int_read ( size, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read WIDTH, the image width in pixels.
+//
+  error = u_long_int_read ( width, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read HEIGHT, the image height in pixels.
+//
+  error = long_int_read ( height, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read PLANES, the number of color planes.
+//
+  error = u_short_int_read ( planes, file_in ); 
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read BITSPERPIXEL.
+//
+  error = u_short_int_read ( bitsperpixel, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read COMPRESSION.
+//
+  error = u_long_int_read ( compression, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read SIZEOFBITMAP.
+//
+  error = u_long_int_read ( sizeofbitmap, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read HORZRESOLUTION.
+//
+  error = u_long_int_read ( horzresolution, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read VERTRESOLUTION.
+//
+  error = u_long_int_read ( vertresolution, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read COLORSUSED.
+//
+  error = u_long_int_read ( colorsused, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read COLORSIMPORTANT.
+//
+  error = u_long_int_read ( colorsimportant, file_in );
+  if ( error )
+  {
+    return error;
+  }
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+void bmp_header2_write ( ofstream &file_out, unsigned long int size,
+  unsigned long int width, long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel,
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused, unsigned long int colorsimportant )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER2_WRITE writes the bitmap header information to a BMP file.
+//
+//  Discussion:
+//
+//    Thanks to Mark Cave-Ayland, mca198@ecs.soton.ac.uk, for pointing out an 
+//    error which caused the code to write one too many long ints, 19 May 2001.
+//
+//    The bitmap header is 40 bytes long:
+//
+//    4 bytes SIZE;                Size of this header, in bytes.
+//    4 bytes WIDTH;               Image width, in pixels.   
+//    4 bytes HEIGHT;              Image height, in pixels.  
+//                                 (Pos/Neg, origin at bottom, top)
+//    2 bytes PLANES;              Number of color planes (always 1).
+//    2 bytes BITSPERPIXEL;        1 to 24.  1, 4, 8, 16, 24 or 32.
+//    4 bytes COMPRESSION;         0, uncompressed; 1, 8 bit RLE; 
+//                                 2, 4 bit RLE; 3, bitfields.
+//    4 bytes SIZEOFBITMAP;        Size of bitmap in bytes. (0 if uncompressed).
+//    4 bytes HORZRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes VERTRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes COLORSUSED;          Number of colors in palette.  (Can be zero).
+//    4 bytes COLORSIMPORTANT.     Minimum number of important colors. (Can be zero).
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    03 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int SIZE, the size of this header in bytes.
+//
+//    Input, unsigned long int WIDTH, the X dimensions of the image.
+//
+//    Input, long int HEIGHT, the Y dimensions of the image.
+//
+//    Input, unsigned short int PLANES, the number of color planes.
+//
+//    Input, unsigned short int BITSPERPIXEL, color bits per pixel.
+//
+//    Input, unsigned long int COMPRESSION, the compression option.
+//
+//    Input, unsigned long int SIZEOFBITMAP, the size of the bitmap.
+//
+//    Input, unsigned long int HORZRESOLUTION, the horizontal resolution.
+//
+//    Input, unsigned long int VERTRESOLUTION, the vertical resolution.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned long int COLORSIMPORTANT, the minimum number of colors.
+//
+{
+  u_long_int_write ( size, file_out );
+  u_long_int_write ( width, file_out );
+  long_int_write ( height, file_out );
+  u_short_int_write ( planes, file_out ); 
+  u_short_int_write ( bitsperpixel, file_out );
+  u_long_int_write ( compression, file_out );
+  u_long_int_write ( sizeofbitmap, file_out );
+  u_long_int_write ( horzresolution, file_out );
+  u_long_int_write ( vertresolution, file_out );
+  u_long_int_write ( colorsused, file_out );
+  u_long_int_write ( colorsimportant, file_out );
+
+  return;
+}
+//****************************************************************************80
+
+void bmp_palette_print ( unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_PALETTE_PRINT prints the palette data in a BMP file.
+// 
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    05 March 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned char *RPARRAY, *GPARRAY, *BPARRAY, *APARRAY, pointers to the 
+//    red, green, blue and transparency palette arrays.
+//
+{
+  unsigned int i;
+  unsigned char *indexa;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+
+  cout << "\n";
+  cout << "  Palette information from BMP file:\n";
+  cout << "\n";
+
+  if ( colorsused < 1 )
+  {
+    cout << "    There are NO colors defined for the palette.\n";
+    return;
+  }
+
+  indexr = rparray;
+  indexg = gparray;
+  indexb = bparray;
+  indexa = aparray;
+
+  cout << "\n";
+  cout << " Color    Blue   Green     Red   Trans\n";
+  cout << "\n";
+
+  for ( i = 0; i < colorsused; i++ )
+  {
+    cout << setw(6) << i       << "  "
+         << setw(6) << *indexb << "  "
+         << setw(6) << *indexg << "  "
+         << setw(6) << *indexr << "  "
+         << setw(6) << *indexa << "\n";
+
+    indexb = indexb + 1;
+    indexg = indexg + 1;
+    indexr = indexr + 1;
+    indexa = indexa + 1;
+
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_palette_read ( ifstream &file_in, unsigned long int colorsused,
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray, 
+  unsigned char *aparray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_PALETTE_READ reads the palette information of a BMP file.
+//
+//  Discussion:
+// 
+//    There are COLORSUSED colors listed.  For each color, the values of
+//    (B,G,R,A) are listed, where A is a quantity reserved for future use.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    05 March 2003
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned char *RPARRAY, *GPARRAY, *BPARRAY, *APARRAY pointers to the 
+//    red, green, blue and transparency palette arrays.
+//
+//    Output, bool BMP_PALETTE_READ, is true if an error occurred.
+//
+{
+  char c;
+  bool error;
+  unsigned int i;
+  unsigned char *indexa;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+
+  indexr = rparray;
+  indexg = gparray;
+  indexb = bparray;
+  indexa = aparray;
+
+  for ( i = 0; i < colorsused; i++ )
+  {
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading B for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexb = ( unsigned char ) c;
+    indexb = indexb + 1;
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading G for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexg = ( unsigned char ) c;
+    indexg = indexg + 1;
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading R for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexr = ( unsigned char ) c;
+    indexr = indexr + 1;
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading A for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexa = ( unsigned char ) c;
+    indexa = indexa + 1;
+  }
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+void bmp_palette_write ( ofstream &file_out, unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_PALETTE_WRITE writes the palette data to the BMP file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    04 March 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned char *RPARRAY, *GPARRAY, *BPARRAY, *APARRAY, pointers to the 
+//    red, green, blue and transparency palette arrays.
+//
+{
+  unsigned int i;
+  unsigned char *indexa;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+
+  indexr = rparray;
+  indexg = gparray;
+  indexb = bparray;
+  indexa = aparray;
+
+  for ( i = 0; i < colorsused; i++ )
+  {
+    file_out << *indexb;
+    file_out << *indexg;
+    file_out << *indexr;
+    file_out << *indexa;
+
+    indexb = indexb + 1;
+    indexg = indexg + 1;
+    indexr = indexr + 1;
+    indexa = indexa + 1;
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_print_test ( char *file_in_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_PRINT_TEST tests the BMP print routines.
+//
+//  Discussion:
+//
+//    Thanks to Tak Fung for suggesting that BMP files should be opened with
+//    the binary option.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    13 August 2007
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_IN_NAME, the name of the input file.
+//
+//    Output, bool BMP_PRINT_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  unsigned char *aparray;
+  unsigned char *barray;
+  unsigned char *bparray;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ifstream file_in;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *garray;
+  unsigned char *gparray;
+  long int height;
+  unsigned long int horzresolution;
+  int numbytes;
+  unsigned short int planes;
+  unsigned char *rarray;
+  unsigned char *rparray;
+  unsigned short int reserved1;
+  unsigned short int reserved2;
+  unsigned long int size;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+  unsigned long int width;
+//
+//  Open the input file.
+//
+  file_in.open ( file_in_name, ios::in | ios::binary );
+
+  if ( !file_in ) 
+  {
+    error = true;
+    cout << "\n";
+    cout << "BMP_PRINT_TEST - Fatal error!\n";
+    cout << "  Could not open the input file.\n";
+    return error;
+  }
+  cout << "\n";
+  cout << "BMP_PRINT_TEST:\n";
+  cout << "  Contents of BMP file \"" << file_in_name << "\"\n";
+//
+//  Read header 1.
+//
+  error = bmp_header1_read ( file_in, &filetype, &filesize, &reserved1, 
+    &reserved2, &bitmapoffset );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_PRINT_TEST: Fatal error!\n";
+    cout << "  BMP_HEADER1_READ failed.\n";
+    return error;
+  }
+
+  bmp_header1_print ( filetype, filesize, reserved1, reserved2, bitmapoffset );
+//
+//  Read header 2.
+//
+  error = bmp_header2_read ( file_in, &size, &width, &height, &planes,
+    &bitsperpixel, &compression, &sizeofbitmap, &horzresolution,
+    &vertresolution, &colorsused, &colorsimportant );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_PRINT_TEST: Fatal error!\n";
+    cout << "  BMP_HEADER2_READ failed.\n";
+    return error;
+  }
+
+  bmp_header2_print ( size, width, height, planes, bitsperpixel,
+    compression, sizeofbitmap, horzresolution, vertresolution, 
+    colorsused, colorsimportant );
+//
+//  Read the palette.
+//
+//if ( 0 < colorsused )
+//{
+    rparray = new unsigned char[colorsused];
+    gparray = new unsigned char[colorsused];
+    bparray = new unsigned char[colorsused];
+    aparray = new unsigned char[colorsused];
+
+    error = bmp_palette_read ( file_in, colorsused, rparray, gparray,
+      bparray, aparray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_PRINT_TEST: Fatal error!\n";
+      cout << "  BMP_PALETTE_READ failed.\n";
+      return error;
+    }
+
+    bmp_palette_print ( colorsused, rparray, gparray, bparray, aparray );
+
+    delete [] rparray;
+    delete [] gparray;
+    delete [] bparray;
+    delete [] aparray;
+//}
+//
+//  Allocate storage.
+//
+  numbytes = width * abs ( height ) * sizeof ( unsigned char );
+//
+//  Read the data.
+//
+  if ( bitsperpixel == 8 )
+  {
+    rarray = new unsigned char[numbytes];
+
+    error = bmp_08_data_read ( file_in, width, height, rarray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_PRINT_TEST: Fatal error!\n";
+      cout << "  BMP_08_DATA_READ failed.\n";
+      return error;
+    }
+
+    *garray = *rarray;
+    *barray = *rarray;
+  }
+  else if ( bitsperpixel == 24 )
+  {
+    rarray = new unsigned char[numbytes];
+    garray = new unsigned char[numbytes];
+    barray = new unsigned char[numbytes];
+    
+    error = bmp_24_data_read ( file_in, width, height, rarray, garray, 
+      barray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_PRINT_TEST: Fatal error!\n";
+      cout << "  BMP_24_DATA_READ failed.\n";
+      return error;
+    }
+  }
+  else
+  {
+    cout << "\n";
+    cout << "BMP_PRINT_TEST: Fatal error!\n";
+    cout << "  Unrecognized value of BITSPERPIXEL = " << bitsperpixel << "\n";
+    return 1;
+  }
+
+  delete [] rarray;
+  delete [] garray;
+  delete [] barray;
+//
+//  Close the file.
+//
+  file_in.close ( );
+
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool bmp_read ( char *file_in_name, unsigned long int *width, long int *height, 
+  unsigned char **rarray, unsigned char **garray, unsigned char **barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_READ reads the header and data of a BMP file.
+//
+//  Discussion:
+//
+//    Thanks to Tak Fung for suggesting that BMP files should be opened with
+//    the binary option.
+//
+//    Thanks to Kelly Anderson for discovering that the routine could not read
+//    monochrome images (bitsperpixel = 8 ) and suggesting how to fix that.
+//
+//    Thanks to Vladimir Levin for correcting a memory leak in the monochrome
+//    image portion of the test, 13 August 2007.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    13 August 2007
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_IN_NAME, the name of the input file.
+//
+//    Output, unsigned long int *WIDTH, the X dimension of the image.
+//
+//    Output, long int *HEIGHT, the Y dimension of the image.
+//
+//    Output, unsigned char **RARRAY, **GARRAY, **BARRAY, pointers to the red, green
+//    and blue color arrays.
+//
+//    Output, bool BMP_READ, is true if an error occurred.
+//
+{
+  unsigned char *aparray;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned char *bparray;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ifstream file_in;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *gparray;
+  unsigned long int horzresolution;
+  unsigned short int magic;
+  int numbytes;
+  unsigned short int planes;
+  unsigned short int reserved1;
+  unsigned short int reserved2;
+  unsigned char *rparray;
+  unsigned long int size;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+//
+//  Open the input file.
+//
+  file_in.open ( file_in_name, ios::in | ios::binary );
+
+  if ( !file_in ) 
+  {
+    error = true;
+    cout << "\n";
+    cout << "BMP_READ - Fatal error!\n";
+    cout << "  Could not open the input file.\n";
+    return error;
+  }
+//
+//  Read header 1.
+//
+  error = bmp_header1_read ( file_in, &filetype, &filesize, &reserved1, 
+    &reserved2, &bitmapoffset );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  BMP_HEADER1_READ failed.\n";
+    return error;
+  }
+//
+//  Make sure the filetype is 'BM'.
+//
+  magic = 'B' * 256 + 'M';
+
+  if ( filetype != magic )
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  The file's internal magic number is not \"BM\".\n";
+    cout << "  with the numeric value " << magic << "\n";
+    cout << "\n";
+    cout << "  Instead, it is \"" 
+         << ( char ) ( filetype / 256 ) 
+         << ( char ) ( filetype % 256 )
+         << "\".\n";
+    cout << "  with the numeric value " << filetype << "\n";
+    cout << "\n";
+    cout << "  (Perhaps you need to reverse the byte swapping option!)\n";
+    return 1;
+  }
+//
+//  Read header 2.
+//
+  error = bmp_header2_read ( file_in, &size, width, height, &planes,
+    &bitsperpixel, &compression, &sizeofbitmap, &horzresolution,
+    &vertresolution, &colorsused, &colorsimportant );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  BMP_HEADER2_READ failed.\n";
+    return error;
+  }
+//
+//  Read the palette.
+//
+  if ( 0 < colorsused )
+  {
+    rparray = new unsigned char[colorsused];
+    gparray = new unsigned char[colorsused];
+    bparray = new unsigned char[colorsused];
+    aparray = new unsigned char[colorsused];
+
+    error = bmp_palette_read ( file_in, colorsused, rparray, gparray,
+      bparray, aparray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_READ: Fatal error!\n";
+      cout << "  BMP_PALETTE_READ failed.\n";
+      return error;
+    }
+    delete [] rparray;
+    delete [] gparray;
+    delete [] bparray;
+    delete [] aparray;
+  }
+//
+//  Allocate storage.
+//
+  numbytes = ( *width ) * ( abs ( *height ) ) * sizeof ( unsigned char );
+//
+//  Read the data.
+//
+  if ( bitsperpixel == 8 )
+  {
+    *rarray = new unsigned char[numbytes];
+
+    error = bmp_08_data_read ( file_in, *width, *height, *rarray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_READ: Fatal error!\n";
+      cout << "  BMP_08_DATA_READ failed.\n";
+      return error;
+    }
+
+    *garray = *rarray;
+    *barray = *rarray;
+  }
+  else if ( bitsperpixel == 24 )
+  {
+    *rarray = new unsigned char[numbytes];
+    *garray = new unsigned char[numbytes];
+    *barray = new unsigned char[numbytes];
+
+    error = bmp_24_data_read ( file_in, *width, *height, *rarray, *garray, 
+      *barray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_READ: Fatal error!\n";
+      cout << "  BMP_24_DATA_READ failed.\n";
+      return error;
+    }
+  }
+  else
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  Unrecognized value of BITSPERPIXEL = " << bitsperpixel << "\n";
+    return 1;
+  }
+//
+//  Close the file.
+//
+  file_in.close ( );
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+bool bmp_read_test ( char *file_in_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_READ_TEST tests the BMP read routines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_IN_NAME, the name of the input file.
+//
+//    Output, bool BMP_READ_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  unsigned char *barray;
+  bool error;
+  unsigned char *garray;
+  long int height;
+  unsigned char *rarray;
+  unsigned long int width;
+
+  rarray = NULL;
+  garray = NULL;
+  barray = NULL;
+//
+//  Read the data from file.
+//
+  error = bmp_read ( file_in_name, &width, &height, &rarray, &garray, 
+    &barray );
+//
+//  Free the memory.
+//
+  delete [] rarray;
+  delete [] garray;
+  delete [] barray;
+
+  if ( VERBOSE )
+  {
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_READ_TEST - Fatal error!\n";
+      cout << "  The test failed.\n";
+    }
+    else
+    {
+      cout << "\n";
+      cout << "BMP_READ_TEST:\n";
+      cout << "  WIDTH =  " << width  << ".\n";
+      cout << "  HEIGHT = " << height << ".\n";
+      cout << "\n";
+      cout << "BMP_READ_TEST:\n";
+      cout << "  The test was successful.\n";
+    }
+  }
+
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool bmp_08_write ( char *file_out_name, unsigned long int width,
+  long int height, unsigned char *rarray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_08_WRITE writes the header and data for a monochrome BMP file.
+//
+//  Discussion:
+//
+//    XV seems to think the resulting BMP file is "unexpectedly truncated".
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    02 April 2005
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, pointer to the red color array.
+//
+//    Output, bool BMP_08_WRITE, is true if an error occurred.
+//
+{
+  unsigned char *aparray = NULL;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned char *bparray = NULL;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ofstream file_out;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *gparray = NULL;
+  unsigned long int horzresolution;
+  int padding;
+  unsigned short int planes;
+  unsigned short int reserved1 = 0;
+  unsigned short int reserved2 = 0;
+  unsigned char *rparray = NULL;
+  unsigned long int size = 40;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+//
+//  Open the output file.
+//
+  file_out.open ( file_out_name, ios::out | ios::binary );
+
+  error = !file_out;
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_08_WRITE - Fatal error!\n";
+    cout << "  Could not open the output file.\n";
+    return error;
+  }
+//
+//  Write header 1.
+//
+  if ( bmp_byte_swap )
+  {
+    filetype = 'M' * 256 + 'B';
+  }
+  else
+  {
+    filetype = 'B' * 256 + 'M';
+  }
+//
+//  Determine the padding needed when WIDTH is not a multiple of 4.
+//
+  padding = ( 4 - ( ( 1 * width ) % 4 ) ) % 4;
+
+  filesize = 54 + ( width + padding ) * abs ( height );
+  bitmapoffset = 54;
+
+  bmp_header1_write ( file_out, filetype, filesize, reserved1, 
+    reserved2, bitmapoffset );
+//
+//  Write header 2.
+//
+  planes = 1;
+  bitsperpixel = 8;
+  compression = 0;
+  sizeofbitmap = 0;
+  horzresolution = 0;
+  vertresolution = 0;
+  colorsused = 0;
+  colorsimportant = 0;
+
+  bmp_header2_write ( file_out, size, width, height, planes, bitsperpixel, 
+    compression, sizeofbitmap, horzresolution, vertresolution,
+    colorsused, colorsimportant );
+//
+//  Write the palette.
+//
+  bmp_palette_write ( file_out, colorsused, rparray, gparray, bparray, 
+    aparray );
+//
+//  Write the data.
+//
+  bmp_08_data_write ( file_out, width, height, rarray );
+//
+//  Close the file.
+//
+  file_out.close ( );
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+bool bmp_08_write_test ( char *file_out_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_08_WRITE_TEST tests the BMP write routines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    02 April 2005
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Output, bool BMP_08_WRITE_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  bool error;
+  long int height;
+  int i;
+  unsigned char *indexr;
+  int j;
+  int numbytes;
+  unsigned char *rarray;
+  unsigned long int width;
+
+  width = 255;
+  height = 255;
+//
+//  Allocate the memory.
+//
+  numbytes = width * abs ( height ) * sizeof ( unsigned char );  
+
+  rarray = new unsigned char[numbytes];
+//
+//  Set the data.
+//
+  indexr = rarray;
+
+  for ( j = 0; j < height; j++ )
+  {
+    for ( i = 0; i < ( int ) width; i++ )
+    {
+      *indexr = i % ( j + 1 );
+      indexr = indexr + 1;
+    }
+  }
+//
+//  Write the data to a file.
+//
+  error = bmp_08_write ( file_out_name, width, height, rarray );
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_08_WRITE_TEST - Fatal error!\n";
+    cout << "  The test failed.\n";
+    return error;
+  }
+//
+//  Free the memory.
+//
+  delete [] rarray;
+
+  if ( VERBOSE )
+  {
+    cout << "\n";
+    cout << "BMP_08_WRITE_TEST:\n";
+    cout << "  The test was successful.\n";
+  }
+
+  error = false;
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool bmp_24_write ( char *file_out_name, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, 
+  unsigned char *barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_24_WRITE writes the header and data for a BMP file using three colors.
+//
+//  Discussion
+//
+//    Thanks to Keefe Roedersheimer for pointing out that I was creating
+//    a filetype of 'MB' instead of 'BM'.
+//
+//    Lee Mulcahy pointed out that the BMP format requires that horizonal lines
+//    must have a length that is a multiple of 4, or be padded so that this is the case.
+//
+//    Thanks to Tak Fung for suggesting that BMP files should be opened with
+//    the binary option.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    02 April 2005
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, *GARRAY, *BARRAY, pointers to the red, green
+//    and blue color arrays.
+//
+//    Output, bool BMP_24_WRITE, is true if an error occurred.
+//
+{
+  unsigned char *aparray = NULL;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned char *bparray = NULL;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ofstream file_out;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *gparray = NULL;
+  unsigned long int horzresolution;
+  int padding;
+  unsigned short int planes;
+  unsigned short int reserved1 = 0;
+  unsigned short int reserved2 = 0;
+  unsigned char *rparray = NULL;
+  unsigned long int size = 40;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+//
+//  Open the output file.
+//
+  file_out.open ( file_out_name, ios::out | ios::binary );
+
+  error = !file_out;
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_24_WRITE - Fatal error!\n";
+    cout << "  Could not open the output file.\n";
+    return error;
+  }
+//
+//  Write header 1.
+//
+  if ( bmp_byte_swap )
+  {
+    filetype = 'M' * 256 + 'B';
+  }
+  else
+  {
+    filetype = 'B' * 256 + 'M';
+  }
+//
+//  Determine the padding needed when WIDTH is not a multiple of 4.
+//
+  padding = ( 4 - ( ( 3 * width ) % 4 ) ) % 4;
+
+  filesize = 54 + ( ( 3 * width ) + padding ) * abs ( height );
+  bitmapoffset = 54;
+
+  bmp_header1_write ( file_out, filetype, filesize, reserved1, 
+    reserved2, bitmapoffset );
+//
+//  Write header 2.
+//
+  planes = 1;
+  bitsperpixel = 24;
+  compression = 0;
+  sizeofbitmap = 0;
+  horzresolution = 0;
+  vertresolution = 0;
+  colorsused = 0;
+  colorsimportant = 0;
+
+  bmp_header2_write ( file_out, size, width, height, planes, bitsperpixel, 
+    compression, sizeofbitmap, horzresolution, vertresolution,
+    colorsused, colorsimportant );
+//
+//  Write the palette.
+//
+  bmp_palette_write ( file_out, colorsused, rparray, gparray, bparray, 
+    aparray );
+//
+//  Write the data.
+//
+  bmp_24_data_write ( file_out, width, height, rarray, garray, barray );
+//
+//  Close the file.
+//
+  file_out.close ( );
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+bool bmp_24_write_test ( char *file_out_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_24_WRITE_TEST tests the BMP write routines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Output, bool BMP_24_WRITE_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  unsigned char *barray;
+  bool error;
+  unsigned char *garray;
+  long int height;
+  int i;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+  int j;
+  int j2;
+  int numbytes;
+  unsigned char *rarray;
+  unsigned long int width;
+
+  width = 200;
+  height = 200;
+//
+//  Allocate the memory.
+//
+  numbytes = width * abs ( height ) * sizeof ( unsigned char );  
+
+  rarray = new unsigned char[numbytes];
+  garray = new unsigned char[numbytes];
+  barray = new unsigned char[numbytes];
+//
+//  Set the data.
+//  Note that BMP files go from "bottom" up, so we'll reverse the
+//  sense of "J" here to get what we want.
+//
+  indexr = rarray;
+  indexg = garray;
+  indexb = barray;
+
+  for ( j2 = 0; j2 < abs ( height ); j2++ )
+  {
+    j = abs ( height ) - j2;
+    for ( i = 0; i < ( int ) width; i++ )
+    {
+      if ( i <= j )
+      {
+        *indexr = 255;
+        *indexg = 0;
+        *indexb = 0;
+      }
+      else if ( ( width - 1 ) * j + ( abs ( height ) - 1 ) * i <= 
+        ( width - 1 ) * ( abs ( height ) - 1 ) )
+      {
+        *indexr = 0;
+        *indexg = 255;
+        *indexb = 0;
+      }
+      else
+      {
+        *indexr = 0;
+        *indexg = 0;
+        *indexb = 255;
+      }
+      indexr = indexr + 1;
+      indexg = indexg + 1;
+      indexb = indexb + 1;
+    }
+  }
+//
+//  Write the data to a file.
+//
+  error = bmp_24_write ( file_out_name, width, height, rarray, garray, barray );
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_24_WRITE_TEST - Fatal error!\n";
+    cout << "  The test failed.\n";
+    return error;
+  }
+//
+//  Free the memory.
+//
+  delete [] rarray;
+  delete [] garray;
+  delete [] barray;
+
+  if ( VERBOSE )
+  {
+    cout << "\n";
+    cout << "BMP_24_WRITE_TEST:\n";
+    cout << "  The test was successful.\n";
+  }
+
+  error = false;
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool long_int_read ( long int *long_int_val, ifstream &file_in )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    LONG_INT_READ reads a long int from a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    06 March 2004
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, long int *LONG_INT_VAL, the value that was read.
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, bool LONG_INT_READ, is true if an error occurred.
+//
+{
+  bool error;
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  if ( bmp_byte_swap )
+  {
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+  else
+  {
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+
+  *long_int_val = ( long int ) 
+    ( u_short_int_val_hi << 16 ) | u_short_int_val_lo;
+
+  return false;
+}
+//****************************************************************************80
+
+void long_int_write ( long int long_int_val, ofstream &file_out )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    LONG_INT_WRITE writes a long int to a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    06 March 2004
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, long int *LONG_INT_VAL, the value to be written.
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+{
+  long int temp;
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  temp = long_int_val / 65536;
+  if ( temp < 0 )
+  {
+    temp = temp + 65536;
+  }
+  u_short_int_val_hi = ( unsigned short ) temp;
+
+  temp = long_int_val % 65536;
+  if ( temp < 0 )
+  {
+    temp = temp + 65536;
+  }
+  u_short_int_val_lo = ( unsigned short ) temp;
+
+  if ( bmp_byte_swap )
+  {
+    u_short_int_write ( u_short_int_val_lo, file_out );
+    u_short_int_write ( u_short_int_val_hi, file_out );
+  }
+  else
+  {
+    u_short_int_write ( u_short_int_val_hi, file_out );
+    u_short_int_write ( u_short_int_val_lo, file_out );
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool u_long_int_read ( unsigned long int *u_long_int_val, 
+  ifstream &file_in )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_LONG_INT_READ reads an unsigned long int from a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, unsigned long int *U_LONG_INT_VAL, the value that was read.
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, bool U_LONG_INT_READ, is true if an error occurred.
+//
+{
+  bool error;
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  if ( bmp_byte_swap )
+  {
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+  else
+  {
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+//
+//  Acknowledgement:
+//
+//    A correction to the following line was supplied by
+//    Peter Kionga-Kamau, 20 May 2000.
+//
+
+  *u_long_int_val = ( u_short_int_val_hi << 16 ) | u_short_int_val_lo;
+
+  return false;
+}
+//****************************************************************************80
+
+void u_long_int_write ( unsigned long int u_long_int_val, 
+  ofstream &file_out )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_LONG_INT_WRITE writes an unsigned long int to a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, unsigned long int *U_LONG_INT_VAL, the value to be written.
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+{
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  u_short_int_val_hi = ( unsigned short ) ( u_long_int_val / 65536 );
+  u_short_int_val_lo = ( unsigned short ) ( u_long_int_val % 65536 );
+
+  if ( bmp_byte_swap )
+  {
+    u_short_int_write ( u_short_int_val_lo, file_out );
+    u_short_int_write ( u_short_int_val_hi, file_out );
+  }
+  else
+  {
+    u_short_int_write ( u_short_int_val_hi, file_out );
+    u_short_int_write ( u_short_int_val_lo, file_out );
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool u_short_int_read ( unsigned short int *u_short_int_val, 
+  ifstream &file_in )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_SHORT_INT_READ reads an unsigned short int from a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    30 March 2005
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, unsigned short int *U_SHORT_INT_VAL, the value that was read.
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, bool U_SHORT_INT_READ, is true if an error occurred.
+//
+{
+  char c;
+  unsigned char chi;
+  unsigned char clo;
+
+  if ( bmp_byte_swap )
+    {
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    clo = ( unsigned char ) c;
+
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    chi = ( unsigned char ) c;
+  }
+  else
+  {
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    chi = ( unsigned char ) c;
+
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    clo = ( unsigned char ) c;
+  }
+
+  *u_short_int_val = ( chi << 8 ) | clo;
+
+  return false;
+}
+//****************************************************************************80
+
+void u_short_int_write ( unsigned short int u_short_int_val, 
+  ofstream &file_out )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_SHORT_INT_WRITE writes an unsigned short int to a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    26 February 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, unsigned short int *U_SHORT_INT_VAL, the value to be written.
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+{
+  unsigned char chi;
+  unsigned char clo;
+
+  chi = ( unsigned char ) ( u_short_int_val / 256 );
+  clo = ( unsigned char ) ( u_short_int_val % 256 );
+
+  if ( bmp_byte_swap )
+  {
+    file_out << clo << chi;
+  }
+  else
+  {
+    file_out << chi << clo;
+  }
+
+  return;
+}
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.h b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.h
new file mode 100644
index 0000000..2fe3298
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.h
@@ -0,0 +1,80 @@
+#include <fstream>
+#include <iostream>
+
+using namespace std;
+
+
+bool bmp_byte_swap_get ( void );
+void bmp_byte_swap_set ( bool value );
+
+bool bmp_08_data_read ( ifstream &file_in, unsigned long int width, long int height, 
+  unsigned char *rarray );
+void bmp_08_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray );
+
+bool bmp_24_data_read ( ifstream &file_in, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+void bmp_24_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+
+void bmp_header1_print ( unsigned short int filetype, 
+  unsigned long int filesize, unsigned short int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset );
+bool bmp_header1_read ( ifstream &file_in, unsigned short int *filetype, 
+  unsigned long int *filesize, unsigned long int *reserved1, 
+  unsigned short int *reserved2, unsigned long int *bitmapoffset );
+void bmp_header1_write ( ofstream &file_out, unsigned short int filetype,
+  unsigned long int filesize, unsigned long int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset );
+
+void bmp_header2_print ( unsigned long int size, unsigned long int width, 
+  long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel, 
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused,  unsigned long int colorsimportant );
+bool bmp_header2_read ( ifstream &file_in, unsigned long int *size,
+  unsigned long int *width, long int *height, 
+  unsigned short int *planes, unsigned short int *bitsperpixel,
+  unsigned long int *compression, unsigned long int *sizeofbitmap,
+  unsigned long int *horzresolution, unsigned long int *vertresolution,
+  unsigned long int *colorsused, unsigned long int *colorsimportant );
+void bmp_header2_write ( ofstream &file_out, unsigned long int size,
+  unsigned long int width, long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel,
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused, unsigned long int colorsimportant );
+
+void bmp_palette_print ( unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray );
+bool bmp_palette_read ( ifstream &file_in, unsigned long int colorsused,
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray, 
+  unsigned char *aparray );
+void bmp_palette_write ( ofstream &file_out, unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray );
+
+bool bmp_print_test ( char *file_in_name );
+
+bool bmp_read ( char *file_in_name, unsigned long int *width, long int *height, 
+  unsigned char **rarray, unsigned char **garray, unsigned char **barray );
+bool bmp_read_test ( char *file_in_name );
+
+bool bmp_08_write ( char *file_out_name, unsigned long int width, long int height, 
+  unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+bool bmp_08_write_test ( char *file_out_name );
+
+bool bmp_24_write ( char *file_out_name, unsigned long int width, long int height, 
+  unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+bool bmp_24_write_test ( char *file_out_name );
+
+bool long_int_read ( long int *long_int_val, ifstream &file_in );
+void long_int_write ( long int long_int_val, ofstream &file_out );
+
+bool u_long_int_read ( unsigned long int *u_long_int_val, ifstream &file_in );
+void u_long_int_write ( unsigned long int u_long_int_val, ofstream &file_out );
+
+bool u_short_int_read ( unsigned short int *u_short_int_val, ifstream &file_in );
+void u_short_int_write ( unsigned short int u_short_int_val, ofstream &file_out );
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/shift_class.h b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/shift_class.h
new file mode 100644
index 0000000..be64c0f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/shift_class.h
@@ -0,0 +1,54 @@
+#ifndef __SHIFT_CLASS__
+#define __SHIFT_CLASS__
+
+template<typename dataType, int NUM_REGS>
+class shift_class{
+private:
+    dataType regs[NUM_REGS];
+    bool en;
+    bool sync_rst;
+    bool ld;
+    dataType *load_data;
+public:
+    shift_class():en(true),sync_rst(false),ld(false){}
+    shift_class(dataType din[NUM_REGS]):
+    en(true),sync_rst(false),ld(false){ load_data = din; }
+
+    void set_sync_rst(bool srst)
+    {
+        sync_rst = srst;
+    }
+
+    void load(bool load_in)
+    {
+        ld = load_in;
+    }
+
+    void set_enable(bool enable)
+    {
+        en = enable;
+    }
+
+    void operator << (dataType din)
+    {
+    SHIFT:for(int i=NUM_REGS-1;i>=0;i--){
+    if(en)
+        if(sync_rst)
+            regs[i] = 0;
+        else if(ld)
+            regs[i] = load_data[i];
+        else
+        if(i==0)
+            regs[i] = din;
+        else
+            regs[i] = regs[i-1];
+        }
+    }
+
+    dataType operator [](int i)
+    {
+        return regs[i];
+    }
+};
+
+#endif
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/tb_blur.cpp b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/tb_blur.cpp
new file mode 100644
index 0000000..b3df259
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/tb_blur.cpp
@@ -0,0 +1,341 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           tb_blur.cpp
+//  Description:    blur filter testbench
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// Testbench to test the blur filter design.
+// It uses an input BMP image with the same resolution as the VGA in the DE2
+// Use images with the same size only and 24 bits (3colours*8bits)
+// Source: icl1.bmp,  width = 640,  height = 480
+// 
+// Settings: 
+// Exclude from compilation (same applies to bmp*.h/cpp files)
+// Enable SCVerify in Flow Manager
+////////////////////////////////////////////////////////////////////////////////
+//
+// WARNING: this testbench is incomplete.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+#include "mc_testbench.h"
+#include <mc_scverify.h>
+
+
+#include <iostream>
+#include "ac_int.h"
+// filter defs and protos
+#include "blur.h"
+// bmp lib
+#include "bmp_io.h"
+
+// file names
+char *source_bmp_file = "icl1.bmp";
+char *hw_bmp_file = "icl2.bmp";
+char *sw_bmp_file = "icl3.bmp";
+
+// pointers to input image contents
+unsigned char *red_in, *green_in, *blue_in;
+// image information
+long int height;
+unsigned long int width;
+int num_pixels;   
+
+   
+// function prototypes:
+void testbench();
+void sw_test();
+
+
+
+
+
+// Main Verification Function
+CCS_MAIN(int argc, char *argv[])
+{
+	// teste your design
+	// blur filter
+    cout << "*** start testbench *** " << endl;
+    testbench();
+    cout << "*** end of testbench *** " << endl;
+
+	// test your algorithm in sw
+	// grayscale convertion
+    cout << "*** start sw test *** " << endl;
+    sw_test();
+    cout << "*** end of sw test *** " << endl;
+
+
+    //  Free the memory
+    delete [] red_in;
+    delete [] green_in;
+    delete [] blue_in;
+       
+    CCS_RETURN(0);
+}
+
+
+
+
+
+
+// this function tests your image processing algorithm implmented 
+// in hardware using the RGB streams from BMP file
+void testbench()
+{
+ 
+    unsigned char *red_out, *green_out, *blue_out;
+    bool error;
+    int i, j;
+
+
+	// these signals have to match the ones in the block diagram 
+	// where they are connected
+    ac_int<PIXEL_WL * KERNEL_WIDTH, false> *input_stream;
+    ac_int<PIXEL_WL, false> *output_stream;
+
+
+
+	/************************************************************************
+    * reads the original/source BMP file, to emulate video frame
+  	* colour arrays are automatically allocated inside the function
+  	* size of the image is extracted from the BMP header
+  	* bmp_read(filename, *width, *height, *red, *green, *blue);
+	************************************************************************/
+	error = bmp_read(source_bmp_file, &width, &height, &red_in, &green_in, &blue_in);
+    if (error)
+    {
+        cout << "\n";
+        cout << "bmp_read: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_read: OK" << endl;
+        cout << "bmp_read: " << width << "x" << height << endl;
+    }
+
+
+    num_pixels = width * abs (height) * sizeof ( unsigned char );     
+
+    if(num_pixels != NUM_PIXELS) {
+        cout << "ERROR: Expecting a 640x480 BMP image!" << endl;
+        delete [] red_in;
+        delete [] green_in;
+        delete [] blue_in;
+        return;
+    }
+    
+    
+
+    // need to reserve memory to store results from the filter
+    // allocate memory to input & output streams from/to your hardware block
+    input_stream = new ac_int<PIXEL_WL * KERNEL_WIDTH, false>[num_pixels];
+    output_stream = new ac_int<PIXEL_WL, false>[num_pixels];
+
+
+    // RGB colour components to be written in file
+    // the output must have the same number of bytes/pixels as the input
+    red_out = new unsigned char[num_pixels];
+    green_out = new unsigned char[num_pixels];
+    blue_out = new unsigned char[num_pixels];
+
+
+    // filter buffer = shift register from input column (KERNEL_WIDTH columns)
+    ac_int<PIXEL_WL, false>col_pixel_buf[KERNEL_WIDTH];
+
+    // group the 3 colour components into 1 single steam
+    // generate the input stream emulating the camera
+    for(i = 0; i < num_pixels; i++) {
+        for(j = 0; j < KERNEL_WIDTH; j++) {
+			// bits 29..20 = RED,  19..10 = GREEN, 9..0 = BLUE
+            col_pixel_buf[j] = ((((ac_int<PIXEL_WL, false>)red_in[i + j * width]) << (2*COLOUR_WL)) | 
+                                (((ac_int<PIXEL_WL, false>)green_in[i + j * width]) << COLOUR_WL) 
+                                | (ac_int<PIXEL_WL, false>)blue_in[i + j * width]);
+        }
+        input_stream[i] = 0;
+        for(j = 0; j < KERNEL_WIDTH; j++) {
+            input_stream[i] |= ((ac_int<PIXEL_WL * KERNEL_WIDTH, false>)col_pixel_buf[j]) << (j * PIXEL_WL);
+        }
+    }
+    
+    
+    
+    
+    
+    /******************************************************************/
+    /* test your design                                               */
+    /******************************************************************/
+
+    CCS_DESIGN(mean_vga)(input_stream, output_stream); 
+
+/*  by-pass your block - check I/Os  
+	for(int i = 0; i < num_pixels; i++) {
+        output_stream[i] = input_stream[i].slc<PIXEL_WL>(0); // copy current pixel (0,30,60,90,120)
+    }    */
+
+
+    
+    
+    // recover your RGB colour signals from the output stream
+    for(int i = 0; i < num_pixels; i++) {
+        red_out[i] = (output_stream[i].slc<COLOUR_WL>(2*COLOUR_WL));
+        green_out[i] = (output_stream[i].slc<COLOUR_WL>(COLOUR_WL));
+        blue_out[i] = (output_stream[i].slc<COLOUR_WL>(0));
+    }    
+
+ 
+
+
+    // write the new BMP file:  swap blue and green
+	// bmp_24_write(filename, width, height, red, green, blue);
+	error = bmp_24_write(hw_bmp_file, width, height, red_out, green_out, blue_out);
+    if ( error ) {
+        cout << "bmp_24_write: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_24_write: OK" << endl;
+    }
+
+
+
+
+   // release memory
+    delete [] input_stream;
+    delete [] output_stream;
+    
+
+    delete [] red_out;
+    delete [] green_out;
+    delete [] blue_out;
+
+    return;        
+
+}
+
+
+
+
+
+
+// this function tests your algorithm in software 
+// usefull to generate the expected result
+void sw_test()
+{
+   // this test copies the original image with swapped colours
+    //unsigned char *red_in, *green_in, *blue_in;
+    unsigned char *sw_red_out, *sw_green_out, *sw_blue_out;
+    bool error;
+    int i, j;
+
+
+
+    
+    
+    
+    // need to reserve memory to store results from the filter
+    // the output must have the same number of bytes/pixels as the input
+    sw_red_out = new unsigned char[num_pixels];
+    sw_green_out = new unsigned char[num_pixels];
+    sw_blue_out = new unsigned char[num_pixels];
+
+
+
+
+    /************************************************************************/
+	/* test of the algorithm in software  
+	/* - data not being processed by your unit
+    /* you can compare the results of your design block 
+    /* e.g. convert from colour to grayscale 
+    /************************************************************************/
+    for(int i = 0; i < num_pixels; i++) {
+        sw_red_out[i] = (red_in[i] + green_in[i] + blue_in[i]) / 3;
+        sw_green_out[i] = (red_in[i] + green_in[i] + blue_in[i]) / 3;
+        sw_blue_out[i] = (red_in[i] + green_in[i] + blue_in[i]) / 3;
+    }
+
+
+
+    /************************************************************************/
+    // write the new BMP file:  swap blue and green
+	// bmp_24_write(filename, width, height, red, green, blue);
+	error = bmp_24_write(sw_bmp_file, width, height, sw_red_out, sw_green_out, sw_blue_out);
+    if ( error ) {
+        cout << "bmp_24_write: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_24_write: OK" << endl;
+    }
+
+    /************************************************************************/
+	//  Free the memory
+    delete [] sw_red_out;
+    delete [] sw_green_out;
+    delete [] sw_blue_out;
+
+    return;        
+}
+
+
+
+
+
+void bmp_io_test()
+{
+    // this test copies the original image with swapped colours
+    unsigned char *barray, *garray, *rarray;
+    bool error;
+    long int height;
+    unsigned long int width;
+
+    //  read the original BMP file
+  	// bmp_read(filename, *width, *height, *red, *green, *blue);
+  	// colour arrays are automatically allocated inside the function
+  	// size of the image is also extracted from the BMP header
+	error = bmp_read("icl1.bmp", &width, &height, &rarray,&garray,&barray);
+    if ( error )
+    {
+        cout << "\n";
+        cout << "bmp_read: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_read: OK" << endl;
+        cout << "bmp_read: " << " width = " <<  width << ", height = " << height << endl;
+    }
+
+    // write the new BMP file:  swap blue and green
+	// bmp_24_write(filename, width, height, red, green, blue);
+	error = bmp_24_write("icl2.bmp", width, height, rarray, barray, garray );
+    if ( error ) {
+        cout << "bmp_24_write: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_24_write: OK" << endl;
+    }
+
+    //  Free the memory
+    delete [] rarray;
+    delete [] garray;
+    delete [] barray;
+
+    return;
+}
+
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_mouse/vga_mouse_square.c b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_mouse/vga_mouse_square.c
new file mode 100644
index 0000000..7e11f9d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_mouse/vga_mouse_square.c
@@ -0,0 +1,94 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           vga_mouse_square.cpp
+//  Description:    video to vga with mouse pointer - real-time processing
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// this hardware block receives the VGA scanning coordinates, 
+// the mouse coordinates and then replaces the mouse pointer 
+// with a different value for the pixel
+////////////////////////////////////////////////////////////////////////////////
+// Catapult Project options
+// Constraint Editor:
+//  Frequency: 27 MHz
+//  Top design: vga_mouse_square
+//  clk>reset sync: disable; reset async: enable; enable: enable
+// Architecture Constraint:
+//  core>main: enable pipeline + loop can be merged
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+#include "stdio.h"
+#include "ac_int.h"
+
+#define COLOR_WL          10
+#define PIXEL_WL          (3*COLOR_WL)
+
+#define  COORD_WL          10
+
+#pragma hls_design top
+void vga_mouse_square(ac_int<(COORD_WL+COORD_WL), false> * vga_xy, ac_int<(COORD_WL+COORD_WL), false> * mouse_xy, ac_int<(8), false> cursor_size, 
+    ac_int<PIXEL_WL, false> * video_in, ac_int<PIXEL_WL, false> * video_out)
+{
+    ac_int<10, false> i_red, i_green, i_blue; // current pixel
+    ac_int<10, false> o_red, o_green, o_blue; // output pixel
+    ac_int<10, false> mouse_x, mouse_y, vga_x, vga_y; // mouse and screen coordinates
+
+    
+/*  --extract the 3 color components from the 30 bit signal--
+    the 2 blocks are identical - you can shift and mask the desired bits or "slice" the signal <length>(location)
+    
+    i_red = *video_in >> 20;
+    i_green = (*video_in >> 10) & (ac_int<10>)1023;
+    i_blue = *video_in & ((ac_int<10>)1023); 
+*/    
+    i_red = (*video_in).slc<COLOR_WL>(20);
+    i_green = (*video_in).slc<COLOR_WL>(10);
+    i_blue = (*video_in).slc<COLOR_WL>(0);
+
+    // extract mouse X-Y coordinates
+    mouse_x = (*mouse_xy).slc<COORD_WL>(0);
+    mouse_y = (*mouse_xy).slc<COORD_WL>(10);
+    // extract VGA pixel X-Y coordinates
+    vga_x = (*vga_xy).slc<COORD_WL>(0);
+    vga_y = (*vga_xy).slc<COORD_WL>(10);
+   
+   
+    
+    /// something here...
+     
+    
+    /// show pixel
+    if ((vga_x >= mouse_x - cursor_size) && (vga_x <= mouse_x + cursor_size) && (vga_y >= mouse_y - cursor_size) && (vga_y <= mouse_y + cursor_size)){
+        // if it is inside the mouse square
+        o_red = 0;
+        o_green = i_green;
+        o_blue = 0;
+    }
+    else {
+        // if it is outside the mouse square
+        o_red = i_red;
+        o_green = i_green;
+        o_blue = i_blue;
+    }
+    
+    // combine the 3 color components into 1 signal only
+    *video_out = ((((ac_int<PIXEL_WL, false>)o_red) << 20) | (((ac_int<PIXEL_WL, false>)o_green) << 10) | (ac_int<PIXEL_WL, false>)o_blue);
+}
+
diff --git a/student_files_2015/student_files_2015/prj2/instructions.doc b/student_files_2015/student_files_2015/prj2/instructions.doc
new file mode 100644
index 0000000..dfe3225
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/instructions.doc
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Copy of DE1_D5M.qsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Copy of DE1_D5M.qsf
new file mode 100644
index 0000000..b02e201
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Copy of DE1_D5M.qsf
@@ -0,0 +1,702 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE1_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY DE1_D5M
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_1[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_1[16]
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+
+
+
+
+set_location_assignment PIN_U7 -to GPIO_0[31]
+set_location_assignment PIN_V5 -to GPIO_0[30]
+set_location_assignment PIN_W6 -to GPIO_0[29]
+set_location_assignment PIN_W7 -to GPIO_0[28]
+set_location_assignment PIN_V8 -to GPIO_0[27]
+set_location_assignment PIN_T8 -to GPIO_0[26]
+set_location_assignment PIN_W10 -to GPIO_0[25]
+set_location_assignment PIN_Y10 -to GPIO_0[24]
+set_location_assignment PIN_V11 -to GPIO_0[23]
+set_location_assignment PIN_R10 -to GPIO_0[22]
+set_location_assignment PIN_V12 -to GPIO_0[21]
+set_location_assignment PIN_U13 -to GPIO_0[20]
+set_location_assignment PIN_W13 -to GPIO_0[19]
+set_location_assignment PIN_Y13 -to GPIO_0[18]
+set_location_assignment PIN_U14 -to GPIO_0[17]
+set_location_assignment PIN_V14 -to GPIO_0[16]
+set_location_assignment PIN_AA4 -to GPIO_0[15]
+set_location_assignment PIN_AB4 -to GPIO_0[14]
+set_location_assignment PIN_AA5 -to GPIO_0[13]
+set_location_assignment PIN_AB5 -to GPIO_0[12]
+set_location_assignment PIN_AA8 -to GPIO_0[11]
+set_location_assignment PIN_AB8 -to GPIO_0[10]
+set_location_assignment PIN_AA10 -to GPIO_0[9]
+set_location_assignment PIN_AB10 -to GPIO_0[8]
+set_location_assignment PIN_AA13 -to GPIO_0[7]
+set_location_assignment PIN_AB13 -to GPIO_0[6]
+set_location_assignment PIN_AB14 -to GPIO_0[5]
+set_location_assignment PIN_AA14 -to GPIO_0[4]
+set_location_assignment PIN_AB15 -to GPIO_0[3]
+set_location_assignment PIN_AA15 -to GPIO_0[2]
+set_location_assignment PIN_AA16 -to GPIO_0[1]
+set_location_assignment PIN_AB16 -to GPIO_0[0]
+
+set_location_assignment PIN_AB12 -to GPIO_0[32]
+set_location_assignment PIN_AA12 -to GPIO_0[33]
+set_location_assignment PIN_AB3 -to GPIO_0[34]
+set_location_assignment PIN_AA3 -to GPIO_0[35]
+
+
+set_location_assignment PIN_AA11 -to GPIO_1[32]
+set_location_assignment PIN_AB11 -to GPIO_1[33]
+set_location_assignment PIN_T16 -to GPIO_1[34]
+set_location_assignment PIN_R16 -to GPIO_1[35]
+
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
+set_location_assignment PIN_E11 -to HEX0_D[0]
+set_location_assignment PIN_F11 -to HEX0_D[1]
+set_location_assignment PIN_H12 -to HEX0_D[2]
+set_location_assignment PIN_H13 -to HEX0_D[3]
+set_location_assignment PIN_G12 -to HEX0_D[4]
+set_location_assignment PIN_F12 -to HEX0_D[5]
+set_location_assignment PIN_F13 -to HEX0_D[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+set_location_assignment PIN_A15 -to HEX1_D[6]
+set_location_assignment PIN_E14 -to HEX1_D[5]
+set_location_assignment PIN_B14 -to HEX1_D[4]
+set_location_assignment PIN_A14 -to HEX1_D[3]
+set_location_assignment PIN_C13 -to HEX1_D[2]
+set_location_assignment PIN_B13 -to HEX1_D[1]
+set_location_assignment PIN_A13 -to HEX1_D[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+set_location_assignment PIN_F14 -to HEX2_D[6]
+set_location_assignment PIN_B17 -to HEX2_D[5]
+set_location_assignment PIN_A17 -to HEX2_D[4]
+set_location_assignment PIN_E15 -to HEX2_D[3]
+set_location_assignment PIN_B16 -to HEX2_D[2]
+set_location_assignment PIN_A16 -to HEX2_D[1]
+set_location_assignment PIN_D15 -to HEX2_D[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+set_location_assignment PIN_G15 -to HEX3_D[6]
+set_location_assignment PIN_D19 -to HEX3_D[5]
+set_location_assignment PIN_C19 -to HEX3_D[4]
+set_location_assignment PIN_B19 -to HEX3_D[3]
+set_location_assignment PIN_A19 -to HEX3_D[2]
+set_location_assignment PIN_F15 -to HEX3_D[1]
+set_location_assignment PIN_B18 -to HEX3_D[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_location_assignment PIN_G21 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
+set_location_assignment PIN_R21 -to PS2_CLK
+set_location_assignment PIN_R22 -to PS2_DAT
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
+#set_location_assignment PIN_E8 -to TDI
+#set_location_assignment PIN_D8 -to TCS
+#set_location_assignment PIN_C7 -to TCK
+#set_location_assignment PIN_D7 -to TDO
+set_instance_assignment -name IO_STANDARD LVTTL -to TDI
+set_instance_assignment -name IO_STANDARD LVTTL -to TCS
+set_instance_assignment -name IO_STANDARD LVTTL -to TCK
+set_instance_assignment -name IO_STANDARD LVTTL -to TDO
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
+
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+set_location_assignment PIN_B12 -to CLOCK_50_2
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+set_location_assignment PIN_R2 -to FL_ADDR[21]
+set_location_assignment PIN_P3 -to FL_ADDR[20]
+set_location_assignment PIN_P1 -to FL_ADDR[19]
+set_location_assignment PIN_M6 -to FL_ADDR[18]
+set_location_assignment PIN_M5 -to FL_ADDR[17]
+set_location_assignment PIN_AA2 -to FL_ADDR[16]
+set_location_assignment PIN_L6 -to FL_ADDR[15]
+set_location_assignment PIN_L7 -to FL_ADDR[14]
+set_location_assignment PIN_M1 -to FL_ADDR[13]
+set_location_assignment PIN_M2 -to FL_ADDR[12]
+set_location_assignment PIN_M3 -to FL_ADDR[11]
+set_location_assignment PIN_N1 -to FL_ADDR[10]
+set_location_assignment PIN_N2 -to FL_ADDR[9]
+set_location_assignment PIN_P2 -to FL_ADDR[8]
+set_location_assignment PIN_M4 -to FL_ADDR[7]
+set_location_assignment PIN_M8 -to FL_ADDR[6]
+set_location_assignment PIN_N6 -to FL_ADDR[5]
+set_location_assignment PIN_N5 -to FL_ADDR[4]
+set_location_assignment PIN_N7 -to FL_ADDR[3]
+set_location_assignment PIN_P6 -to FL_ADDR[2]
+set_location_assignment PIN_P5 -to FL_ADDR[1]
+set_location_assignment PIN_P7 -to FL_ADDR[0]
+set_location_assignment PIN_AA1 -to FL_BYTE_N
+set_location_assignment PIN_N8 -to FL_CE_N
+set_location_assignment PIN_R7 -to FL_DQ[0]
+set_location_assignment PIN_P8 -to FL_DQ[1]
+set_location_assignment PIN_R8 -to FL_DQ[2]
+set_location_assignment PIN_U1 -to FL_DQ[3]
+set_location_assignment PIN_V2 -to FL_DQ[4]
+set_location_assignment PIN_V3 -to FL_DQ[5]
+set_location_assignment PIN_W1 -to FL_DQ[6]
+set_location_assignment PIN_Y1 -to FL_DQ[7]
+set_location_assignment PIN_T5 -to FL_DQ[8]
+set_location_assignment PIN_T7 -to FL_DQ[9]
+set_location_assignment PIN_T4 -to FL_DQ[10]
+set_location_assignment PIN_U2 -to FL_DQ[11]
+set_location_assignment PIN_V1 -to FL_DQ[12]
+set_location_assignment PIN_V4 -to FL_DQ[13]
+set_location_assignment PIN_W2 -to FL_DQ[14]
+set_location_assignment PIN_R6 -to FL_OE_N
+set_location_assignment PIN_R1 -to FL_RST_N
+set_location_assignment PIN_M7 -to FL_RY
+set_location_assignment PIN_P4 -to FL_WE_N
+set_location_assignment PIN_T3 -to FL_WP_N
+set_location_assignment PIN_Y2 -to FL_DQ15_AM1
+
+
+
+
+
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/uart_crtl.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE1_D5M.v
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name SDC_FILE DE1_D5M.sdc
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.asm.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.asm.rpt
new file mode 100644
index 0000000..a7b1105
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.asm.rpt
@@ -0,0 +1,130 @@
+Assembler report for DE0_D5M
+Mon Mar 17 10:02:44 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.sof
+  6. Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.pof
+  7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Mon Mar 17 10:02:44 2014 ;
+; Revision Name         ; DE0_D5M                               ;
+; Top-level Entity Name ; TOP_CAMERA                            ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; On       ; Off           ;
+; Use configuration device                                                    ; On       ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++---------------------------------------------------------------------------+
+; Assembler Generated Files                                                 ;
++---------------------------------------------------------------------------+
+; File Name                                                                 ;
++---------------------------------------------------------------------------+
+; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.sof ;
+; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.pof ;
++---------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.sof ;
++----------------+------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                            ;
++----------------+------------------------------------------------------------------------------------+
+; Device         ; EP3C16F484C6                                                                       ;
+; JTAG usercode  ; 0x0019C8D3                                                                         ;
+; Checksum       ; 0x0019C8D3                                                                         ;
++----------------+------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.pof ;
++--------------------+--------------------------------------------------------------------------------+
+; Option             ; Setting                                                                        ;
++--------------------+--------------------------------------------------------------------------------+
+; Device             ; EPCS4                                                                          ;
+; JTAG usercode      ; 0x00000000                                                                     ;
+; Checksum           ; 0x05BFF881                                                                     ;
+; Compression Ratio  ; 3                                                                              ;
++--------------------+--------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Mon Mar 17 10:02:39 2014
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 450 megabytes
+    Info: Processing ended: Mon Mar 17 10:02:44 2014
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.bsf
new file mode 100644
index 0000000..b4e6ef4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.bsf
@@ -0,0 +1,232 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 304 480)
+	(text "DE0_D5M" (rect 5 0 49 12)(font "Arial" ))
+	(text "inst" (rect 8 448 20 460)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK_50" (rect 0 0 49 12)(font "Arial" ))
+		(text "CLOCK_50" (rect 21 27 70 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "KEY[2..0]" (rect 0 0 41 12)(font "Arial" ))
+		(text "KEY[2..0]" (rect 21 43 62 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "SW[9..0]" (rect 0 0 36 12)(font "Arial" ))
+		(text "SW[9..0]" (rect 21 59 57 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "GPIO_1_CLKIN[1..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "GPIO_1_CLKIN[1..0]" (rect 21 75 107 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "LEDG[9..0]" (rect 0 0 47 12)(font "Arial" ))
+		(text "LEDG[9..0]" (rect 220 27 267 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(port
+		(pt 288 48)
+		(output)
+		(text "HEX0[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX0[6..0]" (rect 223 43 267 55)(font "Arial" ))
+		(line (pt 288 48)(pt 272 48)(line_width 3))
+	)
+	(port
+		(pt 288 64)
+		(output)
+		(text "HEX1[6..0]" (rect 0 0 43 12)(font "Arial" ))
+		(text "HEX1[6..0]" (rect 224 59 267 71)(font "Arial" ))
+		(line (pt 288 64)(pt 272 64)(line_width 3))
+	)
+	(port
+		(pt 288 80)
+		(output)
+		(text "HEX2[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX2[6..0]" (rect 223 75 267 87)(font "Arial" ))
+		(line (pt 288 80)(pt 272 80)(line_width 3))
+	)
+	(port
+		(pt 288 96)
+		(output)
+		(text "HEX3[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX3[6..0]" (rect 223 91 267 103)(font "Arial" ))
+		(line (pt 288 96)(pt 272 96)(line_width 3))
+	)
+	(port
+		(pt 288 128)
+		(output)
+		(text "DRAM_ADDR[11..0]" (rect 0 0 90 12)(font "Arial" ))
+		(text "DRAM_ADDR[11..0]" (rect 177 123 267 135)(font "Arial" ))
+		(line (pt 288 128)(pt 272 128)(line_width 3))
+	)
+	(port
+		(pt 288 144)
+		(output)
+		(text "DRAM_LDQM" (rect 0 0 66 12)(font "Arial" ))
+		(text "DRAM_LDQM" (rect 201 139 267 151)(font "Arial" ))
+		(line (pt 288 144)(pt 272 144)(line_width 1))
+	)
+	(port
+		(pt 288 160)
+		(output)
+		(text "DRAM_UDQM" (rect 0 0 67 12)(font "Arial" ))
+		(text "DRAM_UDQM" (rect 200 155 267 167)(font "Arial" ))
+		(line (pt 288 160)(pt 272 160)(line_width 1))
+	)
+	(port
+		(pt 288 176)
+		(output)
+		(text "DRAM_WE_N" (rect 0 0 68 12)(font "Arial" ))
+		(text "DRAM_WE_N" (rect 199 171 267 183)(font "Arial" ))
+		(line (pt 288 176)(pt 272 176)(line_width 1))
+	)
+	(port
+		(pt 288 192)
+		(output)
+		(text "DRAM_CAS_N" (rect 0 0 71 12)(font "Arial" ))
+		(text "DRAM_CAS_N" (rect 196 187 267 199)(font "Arial" ))
+		(line (pt 288 192)(pt 272 192)(line_width 1))
+	)
+	(port
+		(pt 288 208)
+		(output)
+		(text "DRAM_RAS_N" (rect 0 0 73 12)(font "Arial" ))
+		(text "DRAM_RAS_N" (rect 194 203 267 215)(font "Arial" ))
+		(line (pt 288 208)(pt 272 208)(line_width 1))
+	)
+	(port
+		(pt 288 224)
+		(output)
+		(text "DRAM_CS_N" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_CS_N" (rect 204 219 267 231)(font "Arial" ))
+		(line (pt 288 224)(pt 272 224)(line_width 1))
+	)
+	(port
+		(pt 288 240)
+		(output)
+		(text "DRAM_BA_0" (rect 0 0 62 12)(font "Arial" ))
+		(text "DRAM_BA_0" (rect 205 235 267 247)(font "Arial" ))
+		(line (pt 288 240)(pt 272 240)(line_width 1))
+	)
+	(port
+		(pt 288 256)
+		(output)
+		(text "DRAM_BA_1" (rect 0 0 61 12)(font "Arial" ))
+		(text "DRAM_BA_1" (rect 206 251 267 263)(font "Arial" ))
+		(line (pt 288 256)(pt 272 256)(line_width 1))
+	)
+	(port
+		(pt 288 272)
+		(output)
+		(text "DRAM_CLK" (rect 0 0 57 12)(font "Arial" ))
+		(text "DRAM_CLK" (rect 210 267 267 279)(font "Arial" ))
+		(line (pt 288 272)(pt 272 272)(line_width 1))
+	)
+	(port
+		(pt 288 288)
+		(output)
+		(text "DRAM_CKE" (rect 0 0 59 12)(font "Arial" ))
+		(text "DRAM_CKE" (rect 208 283 267 295)(font "Arial" ))
+		(line (pt 288 288)(pt 272 288)(line_width 1))
+	)
+	(port
+		(pt 288 304)
+		(output)
+		(text "VGA_HS" (rect 0 0 42 12)(font "Arial" ))
+		(text "VGA_HS" (rect 225 299 267 311)(font "Arial" ))
+		(line (pt 288 304)(pt 272 304)(line_width 1))
+	)
+	(port
+		(pt 288 320)
+		(output)
+		(text "VGA_VS" (rect 0 0 43 12)(font "Arial" ))
+		(text "VGA_VS" (rect 224 315 267 327)(font "Arial" ))
+		(line (pt 288 320)(pt 272 320)(line_width 1))
+	)
+	(port
+		(pt 288 336)
+		(output)
+		(text "VGA_R[3..0]" (rect 0 0 57 12)(font "Arial" ))
+		(text "VGA_R[3..0]" (rect 210 331 267 343)(font "Arial" ))
+		(line (pt 288 336)(pt 272 336)(line_width 3))
+	)
+	(port
+		(pt 288 352)
+		(output)
+		(text "VGA_G[3..0]" (rect 0 0 56 12)(font "Arial" ))
+		(text "VGA_G[3..0]" (rect 211 347 267 359)(font "Arial" ))
+		(line (pt 288 352)(pt 272 352)(line_width 3))
+	)
+	(port
+		(pt 288 368)
+		(output)
+		(text "VGA_B[3..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "VGA_B[3..0]" (rect 212 363 267 375)(font "Arial" ))
+		(line (pt 288 368)(pt 272 368)(line_width 3))
+	)
+	(port
+		(pt 288 384)
+		(output)
+		(text "VGA_CLK" (rect 0 0 49 12)(font "Arial" ))
+		(text "VGA_CLK" (rect 218 379 267 391)(font "Arial" ))
+		(line (pt 288 384)(pt 272 384)(line_width 1))
+	)
+	(port
+		(pt 288 400)
+		(output)
+		(text "GPIO_1_CLKOUT[1..0]" (rect 0 0 96 12)(font "Arial" ))
+		(text "GPIO_1_CLKOUT[1..0]" (rect 171 395 267 407)(font "Arial" ))
+		(line (pt 288 400)(pt 272 400)(line_width 3))
+	)
+	(port
+		(pt 288 112)
+		(bidir)
+		(text "DRAM_DQ[15..0]" (rect 0 0 75 12)(font "Arial" ))
+		(text "DRAM_DQ[15..0]" (rect 192 107 267 119)(font "Arial" ))
+		(line (pt 288 112)(pt 272 112)(line_width 3))
+	)
+	(port
+		(pt 288 416)
+		(bidir)
+		(text "GPIO_1[31..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "GPIO_1[31..0]" (rect 212 411 267 423)(font "Arial" ))
+		(line (pt 288 416)(pt 272 416)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 448)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.done b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.done
new file mode 100644
index 0000000..fc5804a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.done
@@ -0,0 +1 @@
+Mon Mar 17 10:02:50 2014
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.rpt
new file mode 100644
index 0000000..b7a9f1b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.rpt
@@ -0,0 +1,3610 @@
+Fitter report for DE0_D5M
+Mon Mar 17 10:02:37 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Ignored Assignments
+  7. Incremental Compilation Preservation Summary
+  8. Incremental Compilation Partition Settings
+  9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. Bidir Pins
+ 16. Dual Purpose and Dedicated Pins
+ 17. I/O Bank Usage
+ 18. All Package Pins
+ 19. PLL Summary
+ 20. PLL Usage
+ 21. Fitter Resource Utilization by Entity
+ 22. Delay Chain Summary
+ 23. Pad To Core Delay Chain Fanout
+ 24. Control Signals
+ 25. Global & Other Fast Signals
+ 26. Non-Global High Fan-Out Signals
+ 27. Fitter RAM Summary
+ 28. Routing Usage Summary
+ 29. LAB Logic Elements
+ 30. LAB-wide Signals
+ 31. LAB Signals Sourced
+ 32. LAB Signals Sourced Out
+ 33. LAB Distinct Inputs
+ 34. I/O Rules Summary
+ 35. I/O Rules Details
+ 36. I/O Rules Matrix
+ 37. Fitter Device Options
+ 38. Operating Settings and Conditions
+ 39. Estimated Delay Added for Hold Timing Summary
+ 40. Estimated Delay Added for Hold Timing Details
+ 41. Fitter Messages
+ 42. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Fitter Summary                                                                   ;
++------------------------------------+---------------------------------------------+
+; Fitter Status                      ; Successful - Mon Mar 17 10:02:37 2014       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                     ;
+; Top-level Entity Name              ; TOP_CAMERA                                  ;
+; Family                             ; Cyclone III                                 ;
+; Device                             ; EP3C16F484C6                                ;
+; Timing Models                      ; Final                                       ;
+; Total logic elements               ; 1,467 / 15,408 ( 10 % )                     ;
+;     Total combinational functions  ; 1,198 / 15,408 ( 8 % )                      ;
+;     Dedicated logic registers      ; 1,030 / 15,408 ( 7 % )                      ;
+; Total registers                    ; 1030                                        ;
+; Total pins                         ; 141 / 347 ( 41 % )                          ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 53,200 / 516,096 ( 10 % )                   ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                              ;
++------------------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Use smart compilation                                                      ; On                                    ; Off                                   ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 3.3-V LVTTL                           ;                                       ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.43        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;  14.3%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------+
+; I/O Assignment Warnings                   ;
++------------------+------------------------+
+; Pin Name         ; Reason                 ;
++------------------+------------------------+
+; DRAM_LDQM        ; Missing drive strength ;
+; DRAM_UDQM        ; Missing drive strength ;
+; DRAM_BA_1        ; Missing drive strength ;
+; DRAM_BA_0        ; Missing drive strength ;
+; DRAM_CAS_N       ; Missing drive strength ;
+; DRAM_CKE         ; Missing drive strength ;
+; DRAM_CS_N        ; Missing drive strength ;
+; DRAM_RAS_N       ; Missing drive strength ;
+; DRAM_WE_N        ; Missing drive strength ;
+; DRAM_CLK         ; Missing drive strength ;
+; VGA_CLK          ; Missing drive strength ;
+; VGA_HS           ; Missing drive strength ;
+; VGA_VS           ; Missing drive strength ;
+; DRAM_ADDR[11]    ; Missing drive strength ;
+; DRAM_ADDR[10]    ; Missing drive strength ;
+; DRAM_ADDR[9]     ; Missing drive strength ;
+; DRAM_ADDR[8]     ; Missing drive strength ;
+; DRAM_ADDR[7]     ; Missing drive strength ;
+; DRAM_ADDR[6]     ; Missing drive strength ;
+; DRAM_ADDR[5]     ; Missing drive strength ;
+; DRAM_ADDR[4]     ; Missing drive strength ;
+; DRAM_ADDR[3]     ; Missing drive strength ;
+; DRAM_ADDR[2]     ; Missing drive strength ;
+; DRAM_ADDR[1]     ; Missing drive strength ;
+; DRAM_ADDR[0]     ; Missing drive strength ;
+; GPIO_1_CLKOUT[1] ; Missing drive strength ;
+; GPIO_1_CLKOUT[0] ; Missing drive strength ;
+; HEX0[6]          ; Missing drive strength ;
+; HEX0[5]          ; Missing drive strength ;
+; HEX0[4]          ; Missing drive strength ;
+; HEX0[3]          ; Missing drive strength ;
+; HEX0[2]          ; Missing drive strength ;
+; HEX0[1]          ; Missing drive strength ;
+; HEX0[0]          ; Missing drive strength ;
+; HEX1[6]          ; Missing drive strength ;
+; HEX1[5]          ; Missing drive strength ;
+; HEX1[4]          ; Missing drive strength ;
+; HEX1[3]          ; Missing drive strength ;
+; HEX1[2]          ; Missing drive strength ;
+; HEX1[1]          ; Missing drive strength ;
+; HEX1[0]          ; Missing drive strength ;
+; HEX2[6]          ; Missing drive strength ;
+; HEX2[5]          ; Missing drive strength ;
+; HEX2[4]          ; Missing drive strength ;
+; HEX2[3]          ; Missing drive strength ;
+; HEX2[2]          ; Missing drive strength ;
+; HEX2[1]          ; Missing drive strength ;
+; HEX2[0]          ; Missing drive strength ;
+; HEX3[6]          ; Missing drive strength ;
+; HEX3[5]          ; Missing drive strength ;
+; HEX3[4]          ; Missing drive strength ;
+; HEX3[3]          ; Missing drive strength ;
+; HEX3[2]          ; Missing drive strength ;
+; HEX3[1]          ; Missing drive strength ;
+; HEX3[0]          ; Missing drive strength ;
+; LEDG[9]          ; Missing drive strength ;
+; LEDG[8]          ; Missing drive strength ;
+; LEDG[7]          ; Missing drive strength ;
+; LEDG[6]          ; Missing drive strength ;
+; LEDG[5]          ; Missing drive strength ;
+; LEDG[4]          ; Missing drive strength ;
+; LEDG[3]          ; Missing drive strength ;
+; LEDG[2]          ; Missing drive strength ;
+; LEDG[1]          ; Missing drive strength ;
+; LEDG[0]          ; Missing drive strength ;
+; VGA_B[3]         ; Missing drive strength ;
+; VGA_B[2]         ; Missing drive strength ;
+; VGA_B[1]         ; Missing drive strength ;
+; VGA_B[0]         ; Missing drive strength ;
+; VGA_G[3]         ; Missing drive strength ;
+; VGA_G[2]         ; Missing drive strength ;
+; VGA_G[1]         ; Missing drive strength ;
+; VGA_G[0]         ; Missing drive strength ;
+; VGA_R[3]         ; Missing drive strength ;
+; VGA_R[2]         ; Missing drive strength ;
+; VGA_R[1]         ; Missing drive strength ;
+; VGA_R[0]         ; Missing drive strength ;
+; DRAM_DQ[15]      ; Missing drive strength ;
+; DRAM_DQ[14]      ; Missing drive strength ;
+; DRAM_DQ[13]      ; Missing drive strength ;
+; DRAM_DQ[12]      ; Missing drive strength ;
+; DRAM_DQ[11]      ; Missing drive strength ;
+; DRAM_DQ[10]      ; Missing drive strength ;
+; DRAM_DQ[9]       ; Missing drive strength ;
+; DRAM_DQ[8]       ; Missing drive strength ;
+; DRAM_DQ[7]       ; Missing drive strength ;
+; DRAM_DQ[6]       ; Missing drive strength ;
+; DRAM_DQ[5]       ; Missing drive strength ;
+; DRAM_DQ[4]       ; Missing drive strength ;
+; DRAM_DQ[3]       ; Missing drive strength ;
+; DRAM_DQ[2]       ; Missing drive strength ;
+; DRAM_DQ[1]       ; Missing drive strength ;
+; DRAM_DQ[0]       ; Missing drive strength ;
+; GPIO_1[31]       ; Missing drive strength ;
+; GPIO_1[30]       ; Missing drive strength ;
+; GPIO_1[29]       ; Missing drive strength ;
+; GPIO_1[28]       ; Missing drive strength ;
+; GPIO_1[27]       ; Missing drive strength ;
+; GPIO_1[26]       ; Missing drive strength ;
+; GPIO_1[25]       ; Missing drive strength ;
+; GPIO_1[24]       ; Missing drive strength ;
+; GPIO_1[23]       ; Missing drive strength ;
+; GPIO_1[22]       ; Missing drive strength ;
+; GPIO_1[21]       ; Missing drive strength ;
+; GPIO_1[20]       ; Missing drive strength ;
+; GPIO_1[19]       ; Missing drive strength ;
+; GPIO_1[18]       ; Missing drive strength ;
+; GPIO_1[17]       ; Missing drive strength ;
+; GPIO_1[16]       ; Missing drive strength ;
+; GPIO_1[15]       ; Missing drive strength ;
+; GPIO_1[14]       ; Missing drive strength ;
+; GPIO_1[13]       ; Missing drive strength ;
+; GPIO_1[12]       ; Missing drive strength ;
+; GPIO_1[11]       ; Missing drive strength ;
+; GPIO_1[10]       ; Missing drive strength ;
+; GPIO_1[9]        ; Missing drive strength ;
+; GPIO_1[8]        ; Missing drive strength ;
+; GPIO_1[7]        ; Missing drive strength ;
+; GPIO_1[6]        ; Missing drive strength ;
+; GPIO_1[5]        ; Missing drive strength ;
+; GPIO_1[4]        ; Missing drive strength ;
+; GPIO_1[3]        ; Missing drive strength ;
+; GPIO_1[2]        ; Missing drive strength ;
+; GPIO_1[1]        ; Missing drive strength ;
+; GPIO_1[0]        ; Missing drive strength ;
++------------------+------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                                    ;
++---------------------+----------------+--------------+-----------------+---------------+----------------+
+; Name                ; Ignored Entity ; Ignored From ; Ignored To      ; Ignored Value ; Ignored Source ;
++---------------------+----------------+--------------+-----------------+---------------+----------------+
+; Location            ;                ;              ; CLOCK_50_2      ; PIN_B12       ; QSF Assignment ;
+; Location            ;                ;              ; DRAM_ADDR[12]   ; PIN_C8        ; QSF Assignment ;
+; Location            ;                ;              ; HEX0_DP         ; PIN_D13       ; QSF Assignment ;
+; Location            ;                ;              ; HEX1_DP         ; PIN_B15       ; QSF Assignment ;
+; Location            ;                ;              ; HEX2_DP         ; PIN_A18       ; QSF Assignment ;
+; Location            ;                ;              ; HEX3_DP         ; PIN_G16       ; QSF Assignment ;
+; Location            ;                ;              ; PS2_CLK         ; PIN_R21       ; QSF Assignment ;
+; Location            ;                ;              ; PS2_DAT         ; PIN_R22       ; QSF Assignment ;
+; Fast Input Register ; TOP_CAMERA     ;              ; rCCD_DATA       ; ON            ; QSF Assignment ;
+; Fast Input Register ; TOP_CAMERA     ;              ; rCCD_FVAL       ; ON            ; QSF Assignment ;
+; Fast Input Register ; TOP_CAMERA     ;              ; rCCD_LVAL       ; ON            ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_ADCDAT      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_ADCLRCK     ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_BCLK        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_DACDAT      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_DACLRCK     ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_XCK         ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; BUTTON[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; BUTTON[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; BUTTON[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; CLOCK_50_2      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; DRAM_ADDR[12]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[16]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[17]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[18]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[19]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[20]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[21]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_BYTE_N       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_CE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ15_AM1     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[0]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[10]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[11]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[12]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[13]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[14]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[1]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[2]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[3]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[4]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[5]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[6]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[7]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[8]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[9]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_OE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_RST_N        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_RY           ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_WE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO0_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO0_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO0_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO0_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO1_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO1_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO1_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO1_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO_1[32]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO_1[33]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO_1[34]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO_1[35]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; I2C_SCLK        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; I2C_SDAT        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; KEY[3]          ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_BLON        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[4]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[5]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[6]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[7]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_EN          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_RS          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_RW          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; PS2_CLK         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; PS2_DAT         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; PS2_KBCLK       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; PS2_KBDAT       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_CLK          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_CMD          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_DAT0         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_DAT3         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; UART_CTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; UART_RTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; UART_RXD        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; UART_TXD        ; 3.3-V LVTTL   ; QSF Assignment ;
++---------------------+----------------+--------------+-----------------+---------------+----------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                      ;
++---------------------+---------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]       ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+---------------------+----------------------------+--------------------------+
+; Placement (by node) ;                     ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 2644 ) ; 0.00 % ( 0 / 2644 )        ; 0.00 % ( 0 / 2644 )      ;
+;     -- Achieved     ; 0.00 % ( 0 / 2644 ) ; 0.00 % ( 0 / 2644 )        ; 0.00 % ( 0 / 2644 )      ;
+;                     ;                     ;                            ;                          ;
+; Routing (by net)    ;                     ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+---------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 2633 )   ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 11 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.pin.
+
+
++-------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                           ;
++---------------------------------------------+---------------------------+
+; Resource                                    ; Usage                     ;
++---------------------------------------------+---------------------------+
+; Total logic elements                        ; 1,467 / 15,408 ( 10 % )   ;
+;     -- Combinational with no register       ; 437                       ;
+;     -- Register only                        ; 269                       ;
+;     -- Combinational with a register        ; 761                       ;
+;                                             ;                           ;
+; Logic element usage by number of LUT inputs ;                           ;
+;     -- 4 input functions                    ; 544                       ;
+;     -- 3 input functions                    ; 261                       ;
+;     -- <=2 input functions                  ; 393                       ;
+;     -- Register only                        ; 269                       ;
+;                                             ;                           ;
+; Logic elements by mode                      ;                           ;
+;     -- normal mode                          ; 886                       ;
+;     -- arithmetic mode                      ; 312                       ;
+;                                             ;                           ;
+; Total registers*                            ; 1,030 / 17,068 ( 6 % )    ;
+;     -- Dedicated logic registers            ; 1,030 / 15,408 ( 7 % )    ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )         ;
+;                                             ;                           ;
+; Total LABs:  partially or completely used   ; 123 / 963 ( 13 % )        ;
+; Virtual pins                                ; 0                         ;
+; I/O pins                                    ; 141 / 347 ( 41 % )        ;
+;     -- Clock pins                           ; 2 / 8 ( 25 % )            ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )             ;
+;                                             ;                           ;
+; Global signals                              ; 9                         ;
+; M9Ks                                        ; 10 / 56 ( 18 % )          ;
+; Total block memory bits                     ; 53,200 / 516,096 ( 10 % ) ;
+; Total block memory implementation bits      ; 92,160 / 516,096 ( 18 % ) ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )           ;
+; PLLs                                        ; 1 / 4 ( 25 % )            ;
+; Global clocks                               ; 9 / 20 ( 45 % )           ;
+; JTAGs                                       ; 0 / 1 ( 0 % )             ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )             ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )             ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )             ;
+; Average interconnect usage (total/H/V)      ; 2% / 2% / 2%              ;
+; Peak interconnect usage (total/H/V)         ; 7% / 7% / 7%              ;
+; Maximum fan-out                             ; 505                       ;
+; Highest non-global fan-out                  ; 53                        ;
+; Total fan-out                               ; 7900                      ;
+; Average fan-out                             ; 2.85                      ;
++---------------------------------------------+---------------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                          ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                   ; Top                   ; hard_block:auto_generated_inst ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                   ; Low                            ;
+;                                             ;                       ;                                ;
+; Total logic elements                        ; 1467 / 15408 ( 10 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 437                   ; 0                              ;
+;     -- Register only                        ; 269                   ; 0                              ;
+;     -- Combinational with a register        ; 761                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic element usage by number of LUT inputs ;                       ;                                ;
+;     -- 4 input functions                    ; 544                   ; 0                              ;
+;     -- 3 input functions                    ; 261                   ; 0                              ;
+;     -- <=2 input functions                  ; 393                   ; 0                              ;
+;     -- Register only                        ; 269                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic elements by mode                      ;                       ;                                ;
+;     -- normal mode                          ; 886                   ; 0                              ;
+;     -- arithmetic mode                      ; 312                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Total registers                             ; 1030                  ; 0                              ;
+;     -- Dedicated logic registers            ; 1030 / 15408 ( 7 % )  ; 0 / 15408 ( 0 % )              ;
+;     -- I/O registers                        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Total LABs:  partially or completely used   ; 123 / 963 ( 13 % )    ; 0 / 963 ( 0 % )                ;
+;                                             ;                       ;                                ;
+; Virtual pins                                ; 0                     ; 0                              ;
+; I/O pins                                    ; 141                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 53200                 ; 0                              ;
+; Total RAM block bits                        ; 92160                 ; 0                              ;
+; PLL                                         ; 0 / 4 ( 0 % )         ; 1 / 4 ( 25 % )                 ;
+; M9K                                         ; 10 / 56 ( 17 % )      ; 0 / 56 ( 0 % )                 ;
+; Clock control block                         ; 7 / 24 ( 29 % )       ; 2 / 24 ( 8 % )                 ;
+;                                             ;                       ;                                ;
+; Connections                                 ;                       ;                                ;
+;     -- Input Connections                    ; 554                   ; 1                              ;
+;     -- Registered Input Connections         ; 505                   ; 0                              ;
+;     -- Output Connections                   ; 49                    ; 506                            ;
+;     -- Registered Output Connections        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Internal Connections                        ;                       ;                                ;
+;     -- Total Connections                    ; 7976                  ; 514                            ;
+;     -- Registered Connections               ; 3805                  ; 0                              ;
+;                                             ;                       ;                                ;
+; External Connections                        ;                       ;                                ;
+;     -- Top                                  ; 96                    ; 507                            ;
+;     -- hard_block:auto_generated_inst       ; 507                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Partition Interface                         ;                       ;                                ;
+;     -- Input Ports                          ; 16                    ; 1                              ;
+;     -- Output Ports                         ; 77                    ; 2                              ;
+;     -- Bidir Ports                          ; 48                    ; 0                              ;
+;                                             ;                       ;                                ;
+; Registered Ports                            ;                       ;                                ;
+;     -- Registered Input Ports               ; 0                     ; 0                              ;
+;     -- Registered Output Ports              ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Port Connectivity                           ;                       ;                                ;
+;     -- Input Ports driven by GND            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                     ; 0                              ;
++---------------------------------------------+-----------------------+--------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                           ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name            ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; CLOCK_50        ; G21   ; 6        ; 41           ; 15           ; 0            ; 97                    ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; GPIO_1_CLKIN[0] ; AB11  ; 3        ; 21           ; 0            ; 14           ; 254                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; GPIO_1_CLKIN[1] ; AA11  ; 3        ; 21           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[0]          ; H2    ; 1        ; 0            ; 21           ; 7            ; 35                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[1]          ; G3    ; 1        ; 0            ; 23           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[2]          ; F1    ; 1        ; 0            ; 23           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[0]           ; J6    ; 1        ; 0            ; 24           ; 0            ; 21                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[1]           ; H5    ; 1        ; 0            ; 27           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[2]           ; H6    ; 1        ; 0            ; 25           ; 21           ; 8                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[3]           ; G4    ; 1        ; 0            ; 23           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[4]           ; G5    ; 1        ; 0            ; 27           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[5]           ; J7    ; 1        ; 0            ; 22           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[6]           ; H7    ; 1        ; 0            ; 25           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[7]           ; E3    ; 1        ; 0            ; 26           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[8]           ; E4    ; 1        ; 0            ; 26           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[9]           ; D2    ; 1        ; 0            ; 25           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name             ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; DRAM_ADDR[0]     ; C4    ; 8        ; 1            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[10]    ; B4    ; 8        ; 5            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[11]    ; A7    ; 8        ; 11           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[1]     ; A3    ; 8        ; 3            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[2]     ; B3    ; 8        ; 3            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[3]     ; C3    ; 8        ; 3            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[4]     ; A5    ; 8        ; 7            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[5]     ; C6    ; 8        ; 5            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[6]     ; B6    ; 8        ; 11           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[7]     ; A6    ; 8        ; 11           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[8]     ; C7    ; 8        ; 9            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[9]     ; B7    ; 8        ; 11           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_BA_0        ; B5    ; 8        ; 7            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_BA_1        ; A4    ; 8        ; 5            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CAS_N       ; G8    ; 8        ; 5            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CKE         ; E6    ; 8        ; 1            ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CLK         ; E5    ; 8        ; 1            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CS_N        ; G7    ; 8        ; 1            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_LDQM        ; E7    ; 8        ; 3            ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_RAS_N       ; F7    ; 8        ; 1            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_UDQM        ; B8    ; 8        ; 14           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_WE_N        ; D6    ; 8        ; 3            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_CLKOUT[0] ; R16   ; 4        ; 37           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_CLKOUT[1] ; T16   ; 4        ; 37           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[0]          ; E11   ; 7        ; 21           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[1]          ; F11   ; 7        ; 21           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[2]          ; H12   ; 7        ; 26           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[3]          ; H13   ; 7        ; 28           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[4]          ; G12   ; 7        ; 26           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[5]          ; F12   ; 7        ; 28           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[6]          ; F13   ; 7        ; 26           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[0]          ; A13   ; 7        ; 21           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[1]          ; B13   ; 7        ; 21           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[2]          ; C13   ; 7        ; 23           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[3]          ; A14   ; 7        ; 23           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[4]          ; B14   ; 7        ; 23           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[5]          ; E14   ; 7        ; 28           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[6]          ; A15   ; 7        ; 26           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[0]          ; D15   ; 7        ; 32           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[1]          ; A16   ; 7        ; 30           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[2]          ; B16   ; 7        ; 28           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[3]          ; E15   ; 7        ; 30           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[4]          ; A17   ; 7        ; 30           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[5]          ; B17   ; 7        ; 30           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[6]          ; F14   ; 7        ; 37           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[0]          ; B18   ; 7        ; 32           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[1]          ; F15   ; 7        ; 39           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[2]          ; A19   ; 7        ; 32           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[3]          ; B19   ; 7        ; 32           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[4]          ; C19   ; 7        ; 37           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[5]          ; D19   ; 7        ; 37           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[6]          ; G15   ; 7        ; 39           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[0]          ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[1]          ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[2]          ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[3]          ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[4]          ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[5]          ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[6]          ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[7]          ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[8]          ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[9]          ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[0]         ; K22   ; 6        ; 41           ; 19           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[1]         ; K21   ; 6        ; 41           ; 19           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[2]         ; J22   ; 6        ; 41           ; 19           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[3]         ; K18   ; 6        ; 41           ; 21           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_CLK          ; U14   ; 4        ; 39           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; VGA_G[0]         ; H22   ; 6        ; 41           ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[1]         ; J17   ; 6        ; 41           ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[2]         ; K17   ; 6        ; 41           ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[3]         ; J21   ; 6        ; 41           ; 20           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_HS           ; L21   ; 6        ; 41           ; 18           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[0]         ; H19   ; 6        ; 41           ; 23           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[1]         ; H17   ; 6        ; 41           ; 25           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[2]         ; H20   ; 6        ; 41           ; 22           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[3]         ; H21   ; 6        ; 41           ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_VS           ; L22   ; 6        ; 41           ; 18           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+; Name        ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source                                               ; Output Enable Group ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+; DRAM_DQ[0]  ; D10   ; 8        ; 16           ; 29           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[10] ; A9    ; 8        ; 16           ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[11] ; C10   ; 8        ; 14           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[12] ; B10   ; 8        ; 16           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[13] ; A10   ; 8        ; 16           ; 29           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[14] ; E10   ; 8        ; 16           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[15] ; F10   ; 8        ; 7            ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[1]  ; G10   ; 8        ; 9            ; 29           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[2]  ; H10   ; 8        ; 9            ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[3]  ; E9    ; 8        ; 11           ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[4]  ; F9    ; 8        ; 7            ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[5]  ; G9    ; 8        ; 9            ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[6]  ; H9    ; 8        ; 7            ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[7]  ; F8    ; 8        ; 5            ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[8]  ; A8    ; 8        ; 14           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[9]  ; B9    ; 8        ; 14           ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; GPIO_1[0]   ; AA20  ; 4        ; 37           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[10]  ; U15   ; 4        ; 39           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[11]  ; T15   ; 4        ; 32           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[12]  ; W15   ; 4        ; 32           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[13]  ; V15   ; 4        ; 32           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[14]  ; AB9   ; 3        ; 16           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[15]  ; AA9   ; 3        ; 16           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[16]  ; AA7   ; 3        ; 11           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[17]  ; AB7   ; 3        ; 11           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[18]  ; T14   ; 4        ; 32           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[19]  ; R14   ; 4        ; 39           ; 0            ; 14           ; 4                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO               ; -                   ;
+; GPIO_1[1]   ; AB20  ; 4        ; 37           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[20]  ; U12   ; 4        ; 26           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[21]  ; T12   ; 4        ; 28           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[22]  ; R11   ; 3        ; 3            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[23]  ; R12   ; 3        ; 5            ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[24]  ; U10   ; 3        ; 14           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[25]  ; T10   ; 3        ; 14           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[26]  ; U9    ; 3        ; 9            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[27]  ; T9    ; 3        ; 1            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[28]  ; Y7    ; 3        ; 9            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[29]  ; U8    ; 3        ; 3            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[2]   ; AA19  ; 4        ; 35           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[30]  ; V6    ; 3        ; 1            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[31]  ; V7    ; 3        ; 7            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[3]   ; AB19  ; 4        ; 35           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[4]   ; AB18  ; 4        ; 32           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[5]   ; AA18  ; 4        ; 35           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[6]   ; AA17  ; 4        ; 28           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[7]   ; AB17  ; 4        ; 28           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[8]   ; Y17   ; 4        ; 35           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[9]   ; W17   ; 4        ; 35           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                                      ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                                 ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; E4       ; DIFFIO_L2p, nRESET                       ; Use as regular IO        ; SW[8]                   ; Dual Purpose Pin          ;
+; D1       ; DIFFIO_L4n, DATA1, ASDO                  ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO              ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                                     ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                                    ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                                      ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                                ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L22      ; DIFFIO_R17n, INIT_DONE                   ; Use as regular IO        ; VGA_VS                  ; Dual Purpose Pin          ;
+; L21      ; DIFFIO_R17p, CRC_ERROR                   ; Use as regular IO        ; VGA_HS                  ; Dual Purpose Pin          ;
+; K22      ; DIFFIO_R16n, nCEO                        ; Use as programming pin   ; VGA_B[0]                ; Dual Purpose Pin          ;
+; K21      ; DIFFIO_R16p, CLKUSR                      ; Use as regular IO        ; VGA_B[1]                ; Dual Purpose Pin          ;
+; B18      ; DIFFIO_T27p, PADD0                       ; Use as regular IO        ; HEX3[0]                 ; Dual Purpose Pin          ;
+; A17      ; DIFFIO_T25n, PADD1                       ; Use as regular IO        ; HEX2[4]                 ; Dual Purpose Pin          ;
+; B17      ; DIFFIO_T25p, PADD2                       ; Use as regular IO        ; HEX2[5]                 ; Dual Purpose Pin          ;
+; E14      ; DIFFIO_T23n, PADD3                       ; Use as regular IO        ; HEX1[5]                 ; Dual Purpose Pin          ;
+; F13      ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8    ; Use as regular IO        ; HEX0[6]                 ; Dual Purpose Pin          ;
+; A15      ; DIFFIO_T20n, PADD5                       ; Use as regular IO        ; HEX1[6]                 ; Dual Purpose Pin          ;
+; C13      ; DIFFIO_T19n, PADD7                       ; Use as regular IO        ; HEX1[2]                 ; Dual Purpose Pin          ;
+; A14      ; DIFFIO_T18n, PADD9                       ; Use as regular IO        ; HEX1[3]                 ; Dual Purpose Pin          ;
+; B14      ; DIFFIO_T18p, PADD10                      ; Use as regular IO        ; HEX1[4]                 ; Dual Purpose Pin          ;
+; A13      ; DIFFIO_T17n, PADD11                      ; Use as regular IO        ; HEX1[0]                 ; Dual Purpose Pin          ;
+; B13      ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9   ; Use as regular IO        ; HEX1[1]                 ; Dual Purpose Pin          ;
+; E11      ; DIFFIO_T16n, PADD13                      ; Use as regular IO        ; HEX0[0]                 ; Dual Purpose Pin          ;
+; F11      ; DIFFIO_T16p, PADD14                      ; Use as regular IO        ; HEX0[1]                 ; Dual Purpose Pin          ;
+; B10      ; DIFFIO_T14p, PADD15                      ; Use as regular IO        ; DRAM_DQ[12]             ; Dual Purpose Pin          ;
+; A9       ; DIFFIO_T13n, PADD16                      ; Use as regular IO        ; DRAM_DQ[10]             ; Dual Purpose Pin          ;
+; B9       ; DIFFIO_T13p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO        ; DRAM_DQ[9]              ; Dual Purpose Pin          ;
+; A8       ; DIFFIO_T12n, DATA2                       ; Use as regular IO        ; DRAM_DQ[8]              ; Dual Purpose Pin          ;
+; B8       ; DIFFIO_T12p, DATA3                       ; Use as regular IO        ; DRAM_UDQM               ; Dual Purpose Pin          ;
+; A7       ; DIFFIO_T11n, PADD18                      ; Use as regular IO        ; DRAM_ADDR[11]           ; Dual Purpose Pin          ;
+; B7       ; DIFFIO_T11p, DATA4                       ; Use as regular IO        ; DRAM_ADDR[9]            ; Dual Purpose Pin          ;
+; A6       ; DIFFIO_T10n, PADD19                      ; Use as regular IO        ; DRAM_ADDR[7]            ; Dual Purpose Pin          ;
+; B6       ; DIFFIO_T10p, DATA15                      ; Use as regular IO        ; DRAM_ADDR[6]            ; Dual Purpose Pin          ;
+; C7       ; DIFFIO_T9p, DATA13                       ; Use as regular IO        ; DRAM_ADDR[8]            ; Dual Purpose Pin          ;
+; A5       ; DATA5                                    ; Use as regular IO        ; DRAM_ADDR[4]            ; Dual Purpose Pin          ;
+; F10      ; DIFFIO_T6p, DATA6                        ; Use as regular IO        ; DRAM_DQ[15]             ; Dual Purpose Pin          ;
+; C6       ; DATA7                                    ; Use as regular IO        ; DRAM_ADDR[5]            ; Dual Purpose Pin          ;
+; B4       ; DIFFIO_T5p, DATA8                        ; Use as regular IO        ; DRAM_ADDR[10]           ; Dual Purpose Pin          ;
+; F8       ; DIFFIO_T4n, DATA9                        ; Use as regular IO        ; DRAM_DQ[7]              ; Dual Purpose Pin          ;
+; A3       ; DIFFIO_T3n, DATA10                       ; Use as regular IO        ; DRAM_ADDR[1]            ; Dual Purpose Pin          ;
+; B3       ; DIFFIO_T3p, DATA11                       ; Use as regular IO        ; DRAM_ADDR[2]            ; Dual Purpose Pin          ;
+; C4       ; DIFFIO_T2p, DATA12, DQS1T/CQ1T#,CDPCLK7  ; Use as regular IO        ; DRAM_ADDR[0]            ; Dual Purpose Pin          ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 27 / 33 ( 82 % ) ; 3.3V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 3.3V          ; --           ;
+; 3        ; 16 / 46 ( 35 % ) ; 3.3V          ; --           ;
+; 4        ; 21 / 41 ( 51 % ) ; 3.3V          ; --           ;
+; 5        ; 0 / 46 ( 0 % )   ; 3.3V          ; --           ;
+; 6        ; 15 / 43 ( 35 % ) ; 3.3V          ; --           ;
+; 7        ; 28 / 47 ( 60 % ) ; 3.3V          ; --           ;
+; 8        ; 38 / 43 ( 88 % ) ; 3.3V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; DRAM_ADDR[1]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A4       ; 350        ; 8        ; DRAM_BA_1                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A5       ; 345        ; 8        ; DRAM_ADDR[4]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A6       ; 336        ; 8        ; DRAM_ADDR[7]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A7       ; 334        ; 8        ; DRAM_ADDR[11]                                             ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A8       ; 332        ; 8        ; DRAM_DQ[8]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A9       ; 328        ; 8        ; DRAM_DQ[10]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A10      ; 326        ; 8        ; DRAM_DQ[13]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; HEX1[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A14      ; 312        ; 7        ; HEX1[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A15      ; 307        ; 7        ; HEX1[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A16      ; 298        ; 7        ; HEX2[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A17      ; 296        ; 7        ; HEX2[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; HEX3[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; GPIO_1[16]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; GPIO_1[15]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GPIO_1_CLKIN[1]                                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; GPIO_1[6]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA18     ; 163        ; 4        ; GPIO_1[5]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA19     ; 164        ; 4        ; GPIO_1[2]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA20     ; 169        ; 4        ; GPIO_1[0]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; GPIO_1[17]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; GPIO_1[14]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GPIO_1_CLKIN[0]                                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; GPIO_1[7]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB18     ; 162        ; 4        ; GPIO_1[4]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB19     ; 165        ; 4        ; GPIO_1[3]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB20     ; 170        ; 4        ; GPIO_1[1]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; LEDG[9]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 1          ; 1        ; LEDG[8]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B3       ; 355        ; 8        ; DRAM_ADDR[2]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B4       ; 351        ; 8        ; DRAM_ADDR[10]                                             ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B5       ; 346        ; 8        ; DRAM_BA_0                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B6       ; 337        ; 8        ; DRAM_ADDR[6]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B7       ; 335        ; 8        ; DRAM_ADDR[9]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B8       ; 333        ; 8        ; DRAM_UDQM                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B9       ; 329        ; 8        ; DRAM_DQ[9]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B10      ; 327        ; 8        ; DRAM_DQ[12]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; HEX1[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B14      ; 313        ; 7        ; HEX1[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; HEX2[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B17      ; 297        ; 7        ; HEX2[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B18      ; 292        ; 7        ; HEX3[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B19      ; 289        ; 7        ; HEX3[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; LEDG[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C2       ; 6          ; 1        ; LEDG[7]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 358        ; 8        ; DRAM_ADDR[3]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C4       ; 359        ; 8        ; DRAM_ADDR[0]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; DRAM_ADDR[5]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C7       ; 340        ; 8        ; DRAM_ADDR[8]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; DRAM_DQ[11]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; HEX1[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; HEX3[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; SW[9]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; DRAM_WE_N                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; DRAM_DQ[0]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; HEX2[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; HEX3[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; LEDG[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; SW[7]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E4       ; 4          ; 1        ; SW[8]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E5       ; 363        ; 8        ; DRAM_CLK                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E6       ; 362        ; 8        ; DRAM_CKE                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E7       ; 357        ; 8        ; DRAM_LDQM                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; DRAM_DQ[3]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E10      ; 325        ; 8        ; DRAM_DQ[14]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E11      ; 317        ; 7        ; HEX0[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; HEX1[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E15      ; 294        ; 7        ; HEX2[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; KEY[2]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F2       ; 15         ; 1        ; LEDG[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; DRAM_RAS_N                                                ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F8       ; 352        ; 8        ; DRAM_DQ[7]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F9       ; 347        ; 8        ; DRAM_DQ[4]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F10      ; 348        ; 8        ; DRAM_DQ[15]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F11      ; 318        ; 7        ; HEX0[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F12      ; 302        ; 7        ; HEX0[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F13      ; 306        ; 7        ; HEX0[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F14      ; 279        ; 7        ; HEX2[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F15      ; 276        ; 7        ; HEX3[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; KEY[1]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G4       ; 17         ; 1        ; SW[3]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G5       ; 3          ; 1        ; SW[4]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; DRAM_CS_N                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G8       ; 353        ; 8        ; DRAM_CAS_N                                                ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G9       ; 342        ; 8        ; DRAM_DQ[5]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G10      ; 341        ; 8        ; DRAM_DQ[1]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; HEX0[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; HEX3[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; CLOCK_50                                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; LEDG[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; KEY[0]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; SW[1]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H6       ; 11         ; 1        ; SW[2]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H7       ; 10         ; 1        ; SW[6]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; DRAM_DQ[6]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H10      ; 343        ; 8        ; DRAM_DQ[2]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; HEX0[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H13      ; 303        ; 7        ; HEX0[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; VGA_R[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; VGA_R[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H20      ; 253        ; 6        ; VGA_R[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H21      ; 246        ; 6        ; VGA_R[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H22      ; 245        ; 6        ; VGA_G[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J1       ; 29         ; 1        ; LEDG[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; LEDG[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; LEDG[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; SW[0]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J7       ; 22         ; 1        ; SW[5]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; VGA_G[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; VGA_G[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J22      ; 241        ; 6        ; VGA_B[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; VGA_G[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K18      ; 248        ; 6        ; VGA_B[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; VGA_B[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K22      ; 239        ; 6        ; VGA_B[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; VGA_HS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L22      ; 234        ; 6        ; VGA_VS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; GPIO_1[22]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R12      ; 98         ; 3        ; GPIO_1[23]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; GPIO_1[19]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; GPIO_1_CLKOUT[0]                                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; GPIO_1[27]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T10      ; 121        ; 3        ; GPIO_1[25]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; GPIO_1[21]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; GPIO_1[18]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T15      ; 161        ; 4        ; GPIO_1[11]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T16      ; 171        ; 4        ; GPIO_1_CLKOUT[1]                                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; GPIO_1[29]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U9       ; 112        ; 3        ; GPIO_1[26]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U10      ; 122        ; 3        ; GPIO_1[24]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; GPIO_1[20]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; VGA_CLK                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
+; U15      ; 173        ; 4        ; GPIO_1[10]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; GPIO_1[30]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V7       ; 105        ; 3        ; GPIO_1[31]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; GPIO_1[13]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; GPIO_1[12]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; GPIO_1[9]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; GPIO_1[28]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; GPIO_1[8]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; PLL Summary                                                                                                       ;
++-------------------------------+-----------------------------------------------------------------------------------+
+; Name                          ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1 ;
++-------------------------------+-----------------------------------------------------------------------------------+
+; SDC pin name                  ; inst|u6|altpll_component|auto_generated|pll1                                      ;
+; PLL mode                      ; Normal                                                                            ;
+; Compensate clock              ; clock0                                                                            ;
+; Compensated input/output pins ; --                                                                                ;
+; Switchover type               ; --                                                                                ;
+; Input frequency 0             ; 50.0 MHz                                                                          ;
+; Input frequency 1             ; --                                                                                ;
+; Nominal PFD frequency         ; 25.0 MHz                                                                          ;
+; Nominal VCO frequency         ; 625.0 MHz                                                                         ;
+; VCO post scale K counter      ; 2                                                                                 ;
+; VCO frequency control         ; Auto                                                                              ;
+; VCO phase shift step          ; 200 ps                                                                            ;
+; VCO multiply                  ; --                                                                                ;
+; VCO divide                    ; --                                                                                ;
+; Freq min lock                 ; 24.0 MHz                                                                          ;
+; Freq max lock                 ; 52.02 MHz                                                                         ;
+; M VCO Tap                     ; 5                                                                                 ;
+; M Initial                     ; 2                                                                                 ;
+; M value                       ; 25                                                                                ;
+; N value                       ; 2                                                                                 ;
+; Charge pump current           ; setting 1                                                                         ;
+; Loop filter resistance        ; setting 24                                                                        ;
+; Loop filter capacitance       ; setting 0                                                                         ;
+; Bandwidth                     ; 450 kHz to 980 kHz                                                                ;
+; Bandwidth type                ; Medium                                                                            ;
+; Real time reconfigurable      ; Off                                                                               ;
+; Scan chain MIF file           ; --                                                                                ;
+; Preserve PLL counter order    ; Off                                                                               ;
+; PLL location                  ; PLL_2                                                                             ;
+; Inclk0 signal                 ; CLOCK_50                                                                          ;
+; Inclk1 signal                 ; --                                                                                ;
+; Inclk0 signal type            ; Dedicated Pin                                                                     ;
+; Inclk1 signal type            ; --                                                                                ;
++-------------------------------+-----------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Usage                                                                                                                                                                                                                                                                                                             ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+; Name                                                                                ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift     ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                        ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; clock0       ; 5    ; 2   ; 125.0 MHz        ; 0 (0 ps)        ; 9.00 (200 ps)    ; 50/50      ; C0      ; 5             ; 3/2 Odd    ; --            ; 2       ; 5       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; clock1       ; 5    ; 2   ; 125.0 MHz        ; -117 (-2600 ps) ; 9.00 (200 ps)    ; 50/50      ; C1      ; 5             ; 3/2 Odd    ; --            ; 1       ; 0       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                           ;
++-----------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                          ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                                                                        ; Library Name ;
++-----------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |TOP_CAMERA                                         ; 1467 (2)    ; 1030 (0)                  ; 0 (0)         ; 53200       ; 10   ; 0            ; 0       ; 0         ; 141  ; 0            ; 437 (2)      ; 269 (0)           ; 761 (0)          ; |TOP_CAMERA                                                                                                                                                                ; work         ;
+;    |DE0_D5M:inst|                                   ; 1465 (15)   ; 1030 (15)                 ; 0 (0)         ; 53200       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 435 (0)      ; 269 (14)          ; 761 (1)          ; |TOP_CAMERA|DE0_D5M:inst                                                                                                                                                   ; work         ;
+;       |CCD_Capture:u3|                              ; 68 (68)     ; 58 (58)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 2 (2)             ; 56 (56)          ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3                                                                                                                                    ; work         ;
+;       |I2C_CCD_Config:u8|                           ; 252 (173)   ; 132 (94)                  ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 120 (79)     ; 15 (5)            ; 117 (89)         ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8                                                                                                                                 ; work         ;
+;          |I2C_Controller:u0|                        ; 79 (79)     ; 38 (38)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 41 (41)      ; 10 (10)           ; 28 (28)          ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0                                                                                                               ; work         ;
+;       |RAW2RGB:u4|                                  ; 93 (77)     ; 66 (55)                   ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 27 (22)      ; 9 (9)             ; 57 (46)          ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4                                                                                                                                        ; work         ;
+;          |Line_Buffer:u0|                           ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                                                                                                                         ; work         ;
+;             |altshift_taps:altshift_taps_component| ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component                                                                                   ; work         ;
+;                |shift_taps_rnn:auto_generated|      ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated                                                     ; work         ;
+;                   |altsyncram_lp81:altsyncram2|     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2                         ; work         ;
+;                   |cntr_cuf:cntr1|                  ; 16 (13)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (2)        ; 0 (0)             ; 11 (11)          ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1                                      ; work         ;
+;                      |cmpr_vgc:cmpr4|               ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4                       ; work         ;
+;       |Reset_Delay:u2|                              ; 50 (50)     ; 35 (35)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (15)      ; 0 (0)             ; 35 (35)          ; |TOP_CAMERA|DE0_D5M:inst|Reset_Delay:u2                                                                                                                                    ; work         ;
+;       |SEG7_LUT_8:u5|                               ; 28 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 28 (0)       ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5                                                                                                                                     ; work         ;
+;          |SEG7_LUT:u0|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0                                                                                                                         ; work         ;
+;          |SEG7_LUT:u1|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u1                                                                                                                         ; work         ;
+;          |SEG7_LUT:u2|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u2                                                                                                                         ; work         ;
+;          |SEG7_LUT:u3|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u3                                                                                                                         ; work         ;
+;       |Sdram_Control_4Port:u7|                      ; 897 (228)   ; 697 (130)                 ; 0 (0)         ; 22528       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 200 (92)     ; 229 (16)          ; 468 (120)        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7                                                                                                                            ; work         ;
+;          |Sdram_FIFO:read_fifo1|                    ; 129 (0)     ; 116 (0)                   ; 0 (0)         ; 4096        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (0)       ; 47 (0)            ; 69 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|               ; 129 (0)     ; 116 (0)                   ; 0 (0)         ; 4096        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (0)       ; 47 (0)            ; 69 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 129 (35)    ; 116 (30)                  ; 0 (0)         ; 4096        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (1)       ; 47 (15)           ; 69 (14)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 16 (16)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 14 (14)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (0)            ; 4 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (16)           ; 4 (4)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 4096        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 4 (4)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:read_fifo2|                    ; 135 (0)     ; 116 (0)                   ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 19 (0)       ; 53 (0)            ; 63 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|               ; 135 (0)     ; 116 (0)                   ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 19 (0)       ; 53 (0)            ; 63 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 135 (40)    ; 116 (30)                  ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 19 (7)       ; 53 (19)           ; 63 (8)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 15 (15)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 14 (14)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 17 (0)            ; 3 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 17 (17)           ; 3 (3)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:write_fifo1|                   ; 129 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (0)       ; 39 (0)            ; 77 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|               ; 129 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (0)       ; 39 (0)            ; 77 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 129 (40)    ; 116 (30)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (3)       ; 39 (16)           ; 77 (13)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 15 (15)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 21 (21)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 1 (1)             ; 16 (16)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 8 (0)             ; 12 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 12 (12)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (0)            ; 7 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (13)           ; 7 (7)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |Sdram_FIFO:write_fifo2|                   ; 141 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 25 (0)       ; 57 (0)            ; 59 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|               ; 141 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 25 (0)       ; 57 (0)            ; 59 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 141 (42)    ; 116 (30)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 25 (10)      ; 57 (24)           ; 59 (5)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 8 (8)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 7 (7)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 14 (14)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 21 (21)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 16 (16)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (0)            ; 4 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (16)           ; 4 (4)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |command:command1|                         ; 63 (63)     ; 48 (48)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 14 (14)      ; 3 (3)             ; 46 (46)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1                                                                                                           ; work         ;
+;          |control_interface:control1|               ; 79 (79)     ; 55 (55)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (24)      ; 14 (14)           ; 41 (41)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1                                                                                                 ; work         ;
+;       |VGA_Controller:u1|                           ; 62 (62)     ; 27 (27)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 35 (35)      ; 0 (0)             ; 27 (27)          ; |TOP_CAMERA|DE0_D5M:inst|VGA_Controller:u1                                                                                                                                 ; work         ;
+;       |sdram_pll:u6|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6                                                                                                                                      ; work         ;
+;          |altpll:altpll_component|                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component                                                                                                              ; work         ;
+;             |altpll_9ee2:auto_generated|            ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated                                                                                   ; work         ;
++-----------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                              ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name             ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+; DRAM_LDQM        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKIN[1]  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[9]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[8]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[7]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[6]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[5]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[4]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[3]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_UDQM        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_BA_1        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_BA_0        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CAS_N       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CKE         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CS_N        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_RAS_N       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_WE_N        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CLK         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_CLK          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_HS           ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_VS           ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[11]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[10]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[9]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[8]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[7]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[6]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[5]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[4]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[3]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[2]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[1]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[0]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKOUT[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKOUT[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[9]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[8]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[7]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[15]      ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[14]      ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[13]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[12]      ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[11]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[10]      ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[9]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[8]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[7]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[6]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[5]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[4]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[3]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[2]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[1]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[0]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[31]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[30]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[29]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[28]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[27]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[26]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[25]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[24]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[23]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[22]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[21]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[20]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[19]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[18]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[17]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[16]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[15]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[14]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[13]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[12]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[11]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[10]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[9]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[8]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[7]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[6]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[5]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[4]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[3]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[2]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[1]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[0]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; CLOCK_50         ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKIN[0]  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; KEY[0]           ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; KEY[2]           ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; KEY[1]           ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[2]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[1]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[0]            ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                                    ;
++---------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                                 ; Pad To Core Index ; Setting ;
++---------------------------------------------------------------------+-------------------+---------+
+; GPIO_1_CLKIN[1]                                                     ;                   ;         ;
+; SW[9]                                                               ;                   ;         ;
+; SW[8]                                                               ;                   ;         ;
+; SW[7]                                                               ;                   ;         ;
+; SW[6]                                                               ;                   ;         ;
+; SW[5]                                                               ;                   ;         ;
+; SW[4]                                                               ;                   ;         ;
+; SW[3]                                                               ;                   ;         ;
+; DRAM_DQ[15]                                                         ;                   ;         ;
+; DRAM_DQ[14]                                                         ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]~feeder      ; 1                 ; 6       ;
+; DRAM_DQ[13]                                                         ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13]~feeder      ; 0                 ; 6       ;
+; DRAM_DQ[12]                                                         ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12]~feeder      ; 1                 ; 6       ;
+; DRAM_DQ[11]                                                         ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[11]~feeder      ; 0                 ; 6       ;
+; DRAM_DQ[10]                                                         ;                   ;         ;
+; DRAM_DQ[9]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]~feeder       ; 1                 ; 6       ;
+; DRAM_DQ[8]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]              ; 0                 ; 6       ;
+; DRAM_DQ[7]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]~feeder       ; 1                 ; 6       ;
+; DRAM_DQ[6]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6]              ; 0                 ; 6       ;
+; DRAM_DQ[5]                                                          ;                   ;         ;
+; DRAM_DQ[4]                                                          ;                   ;         ;
+; DRAM_DQ[3]                                                          ;                   ;         ;
+; DRAM_DQ[2]                                                          ;                   ;         ;
+; DRAM_DQ[1]                                                          ;                   ;         ;
+; DRAM_DQ[0]                                                          ;                   ;         ;
+; GPIO_1[31]                                                          ;                   ;         ;
+; GPIO_1[30]                                                          ;                   ;         ;
+; GPIO_1[29]                                                          ;                   ;         ;
+; GPIO_1[28]                                                          ;                   ;         ;
+; GPIO_1[27]                                                          ;                   ;         ;
+; GPIO_1[26]                                                          ;                   ;         ;
+; GPIO_1[25]                                                          ;                   ;         ;
+; GPIO_1[24]                                                          ;                   ;         ;
+; GPIO_1[23]                                                          ;                   ;         ;
+; GPIO_1[22]                                                          ;                   ;         ;
+; GPIO_1[21]                                                          ;                   ;         ;
+; GPIO_1[20]                                                          ;                   ;         ;
+; GPIO_1[19]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~3      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~1      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3~2      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~9      ; 1                 ; 6       ;
+; GPIO_1[18]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_FVAL                                       ; 1                 ; 6       ;
+; GPIO_1[17]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_LVAL                                       ; 1                 ; 6       ;
+; GPIO_1[16]                                                          ;                   ;         ;
+; GPIO_1[15]                                                          ;                   ;         ;
+; GPIO_1[14]                                                          ;                   ;         ;
+; GPIO_1[13]                                                          ;                   ;         ;
+; GPIO_1[12]                                                          ;                   ;         ;
+; GPIO_1[11]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[0]                                    ; 0                 ; 6       ;
+; GPIO_1[10]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[1]~feeder                             ; 1                 ; 6       ;
+; GPIO_1[9]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[2]~feeder                             ; 1                 ; 6       ;
+; GPIO_1[8]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[3]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[7]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[4]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[6]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[5]                                    ; 0                 ; 6       ;
+; GPIO_1[5]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[6]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[4]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[7]                                    ; 1                 ; 6       ;
+; GPIO_1[3]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[8]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[2]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[9]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[1]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[10]                                   ; 1                 ; 6       ;
+; GPIO_1[0]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[11]~feeder                            ; 0                 ; 6       ;
+; CLOCK_50                                                            ;                   ;         ;
+; GPIO_1_CLKIN[0]                                                     ;                   ;         ;
+; KEY[0]                                                              ;                   ;         ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_2                           ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_0                           ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[0]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[1]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[2]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[3]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[4]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[5]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[6]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[7]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[8]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[9]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[10]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[11]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[12]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[13]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[14]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[15]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[16]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[17]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[18]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[19]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[20]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[21]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[22]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[23]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[24]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[25]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[26]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[27]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[28]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[29]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[30]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[31]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_1                           ; 0                 ; 6       ;
+; KEY[2]                                                              ;                   ;         ;
+;      - DE0_D5M:inst|CCD_Capture:u3|mSTART~0                         ; 1                 ; 6       ;
+; KEY[1]                                                              ;                   ;         ;
+;      - DE0_D5M:inst|CCD_Capture:u3|mSTART~0                         ; 0                 ; 6       ;
+; SW[2]                                                               ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~3                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux13~1                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~2                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~5                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~0                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~2                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~15                      ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~17                      ; 0                 ; 6       ;
+; SW[1]                                                               ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                     ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]~feeder ; 0                 ; 6       ;
+; SW[0]                                                               ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]~44        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]~23         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]           ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]~34        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]~32         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]~38        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]~36        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]~21         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~40        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~42        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]~19         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]~15         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]~17         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~25        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~28        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]~46         ; 1                 ; 6       ;
+;      - SW[0]~_wirecell                                              ; 1                 ; 6       ;
++---------------------------------------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                                                                                                                  ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                                                                                                                  ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                                                                              ; PIN_G21            ; 4       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                                                                                                                              ; PIN_G21            ; 94      ; Clock                      ; yes    ; Global Clock         ; GCLK7            ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]~40                                                                                             ; LCCOMB_X1_Y23_N4   ; 16      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]~41                                                                                             ; LCCOMB_X1_Y23_N2   ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[5]~30                                                                                              ; LCCOMB_X1_Y23_N26  ; 10      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|always2~0                                                                                                 ; LCCOMB_X21_Y23_N8  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL                                                                                                 ; FF_X21_Y23_N7      ; 16      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|oDVAL                                                                                                     ; LCCOMB_X17_Y12_N0  ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2                                                                             ; LCCOMB_X15_Y13_N18 ; 24      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]~1                                                                      ; LCCOMB_X14_Y13_N20 ; 6       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2]                                                                                           ; FF_X11_Y13_N21     ; 36      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4]                                                                                           ; FF_X11_Y13_N25     ; 35      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7                                                                                         ; LCCOMB_X11_Y13_N14 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4                                                                                            ; LCCOMB_X16_Y14_N24 ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1                                                                                            ; LCCOMB_X11_Y13_N2  ; 6       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                              ; LCCOMB_X15_Y11_N4  ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset                                                                                              ; LCCOMB_X15_Y11_N8  ; 43      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]                                                                                 ; FF_X15_Y11_N17     ; 26      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                                                                          ; FF_X12_Y14_N17     ; 72      ; Clock                      ; yes    ; Global Clock         ; GCLK4            ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1                                                                                        ; LCCOMB_X15_Y13_N24 ; 24      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~31                                                                                 ; LCCOMB_X11_Y11_N16 ; 14      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual ; LCCOMB_X20_Y13_N26 ; 11      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[3]~36                                                                                                  ; LCCOMB_X16_Y15_N4  ; 10      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~11                                                                                                 ; LCCOMB_X14_Y24_N0  ; 32      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                    ; FF_X19_Y26_N1      ; 468     ; Async. clear               ; yes    ; Global Clock         ; GCLK12           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                    ; FF_X14_Y24_N21     ; 55      ; Async. clear               ; yes    ; Global Clock         ; GCLK17           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                    ; FF_X14_Y24_N9      ; 128     ; Async. clear               ; yes    ; Global Clock         ; GCLK14           ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]~0                                                                                          ; LCCOMB_X19_Y26_N16 ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~10                                                                                     ; LCCOMB_X19_Y26_N6  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~7                                                                                      ; LCCOMB_X19_Y23_N8  ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0            ; LCCOMB_X26_Y22_N0  ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0            ; LCCOMB_X26_Y23_N8  ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0            ; LCCOMB_X26_Y17_N8  ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0            ; LCCOMB_X22_Y17_N28 ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0           ; LCCOMB_X14_Y20_N16 ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0           ; LCCOMB_X10_Y19_N14 ; 18      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0           ; LCCOMB_X14_Y17_N30 ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0           ; LCCOMB_X14_Y18_N12 ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]~2                                                                                      ; LCCOMB_X19_Y23_N18 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE                                                                               ; FF_X15_Y27_N11     ; 16      ; Output enable              ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]~1                                                                    ; LCCOMB_X17_Y27_N0  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ                                                               ; FF_X17_Y23_N25     ; 26      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3                                                            ; LCCOMB_X17_Y23_N8  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1                                                              ; LCCOMB_X19_Y27_N4  ; 16      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~45                                                                                  ; LCCOMB_X20_Y23_N0  ; 15      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~46                                                                                  ; LCCOMB_X19_Y23_N4  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~46                                                                                  ; LCCOMB_X17_Y26_N0  ; 15      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~47                                                                                  ; LCCOMB_X19_Y26_N26 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~45                                                                                  ; LCCOMB_X21_Y26_N0  ; 15      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~46                                                                                  ; LCCOMB_X19_Y26_N12 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~46                                                                                  ; LCCOMB_X24_Y26_N30 ; 15      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~47                                                                                  ; LCCOMB_X19_Y26_N30 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~3                                                                                               ; LCCOMB_X39_Y18_N14 ; 13      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2                                                                                            ; LCCOMB_X38_Y18_N2  ; 12      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4                                                                                            ; LCCOMB_X40_Y18_N30 ; 12      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|rClk[0]                                                                                                                  ; FF_X40_Y15_N23     ; 117     ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0]                                                   ; PLL_2              ; 505     ; Clock                      ; yes    ; Global Clock         ; GCLK8            ; --                        ;
+; GPIO_1_CLKIN[0]                                                                                                                       ; PIN_AB11           ; 254     ; Clock                      ; yes    ; Global Clock         ; GCLK19           ; --                        ;
+; KEY[0]                                                                                                                                ; PIN_H2             ; 35      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                                                                                                 ;
++-------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name                                                                                ; Location       ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                            ; PIN_G21        ; 94      ; 0                                    ; Global Clock         ; GCLK7            ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                        ; FF_X12_Y14_N17 ; 72      ; 0                                    ; Global Clock         ; GCLK4            ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                  ; FF_X19_Y26_N1  ; 468     ; 0                                    ; Global Clock         ; GCLK12           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                  ; FF_X14_Y24_N21 ; 55      ; 0                                    ; Global Clock         ; GCLK17           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                  ; FF_X14_Y24_N9  ; 128     ; 0                                    ; Global Clock         ; GCLK14           ; --                        ;
+; DE0_D5M:inst|rClk[0]                                                                ; FF_X40_Y15_N23 ; 117     ; 0                                    ; Global Clock         ; GCLK6            ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; PLL_2          ; 505     ; 283                                  ; Global Clock         ; GCLK8            ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; PLL_2          ; 1       ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
+; GPIO_1_CLKIN[0]                                                                     ; PIN_AB11       ; 254     ; 0                                    ; Global Clock         ; GCLK19           ; --                        ;
++-------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals                                                                                                                                                     ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Name                                                                                                                                                                      ; Fan-Out ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; ~GND                                                                                                                                                                      ; 53      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset                                                                                                                                  ; 43      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[1]                                                                                                                               ; 37      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2]                                                                                                                               ; 36      ;
+; KEY[0]~input                                                                                                                                                              ; 35      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[0]                                                                                                                               ; 35      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4]                                                                                                                               ; 35      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[0]                                                                                                                                     ; 34      ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[0]                                                                                                                                     ; 34      ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~11                                                                                                                                     ; 32      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[3]                                                                                                                               ; 32      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; 31      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]                                                                                                                     ; 26      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ                                                                                                   ; 26      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1                                                                                                                            ; 24      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2                                                                                                                 ; 24      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD~0                                                                                                                                 ; 23      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]~0                                                                                                                           ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]                                                                                                            ; 22      ;
+; SW[0]~input                                                                                                                                                               ; 21      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0]                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                               ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]                                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_writea                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_reada                                                                                                             ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                               ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                               ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                               ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2]                                                                                                            ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]                                                                                                                               ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal0~0                                                                                                                              ; 18      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; 18      ;
+; DE0_D5M:inst|CCD_Capture:u3|oDVAL                                                                                                                                         ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4                                                                                                                                ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1]                                                                                                            ; 17      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1                                                                                                  ; 16      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE                                                                                                                   ; 16      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]~41                                                                                                                                 ; 16      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]~40                                                                                                                                 ; 16      ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL                                                                                                                                     ; 16      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3                                                                                                ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~47                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~45                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~47                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~45                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~10                                                                                                                         ; 15      ;
+; DE0_D5M:inst|CCD_Capture:u3|always2~0                                                                                                                                     ; 15      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                                                                  ; 14      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~31                                                                                                                     ; 14      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal6~0                                                                                                                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[10]                             ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[9]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[8]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[7]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[6]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[5]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[4]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[3]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[2]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[1]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[0]                              ; 14      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]                                                                                                            ; 13      ;
+; DE0_D5M:inst|rCCD_LVAL                                                                                                                                                    ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~3                                                                                                                                   ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|always0~1                                                                                                                                  ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4                                                                                                                                ; 12      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]                                                                                                            ; 12      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag~1                                                                                                            ; 12      ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2                                                                                                                                ; 12      ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R~0                                                                                                                                   ; 12      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual                                     ; 11      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[6]                                                                                                            ; 11      ;
+; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[3]~36                                                                                                                                      ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~5                                                                                                            ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~2                                                                                                                               ; 10      ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                                                        ; 10      ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[5]~30                                                                                                                                  ; 10      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_GO                                                                                                                                    ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_done                                                                                                         ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]~0                                                                                                                               ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[2]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[0]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16                                                     ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_refresh                                                                                                           ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; 9       ;
+; SW[2]~input                                                                                                                                                               ; 8       ;
+; SW[0]~_wirecell                                                                                                                                                           ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~3                                                                                                                              ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                       ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                       ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16                                                     ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[15]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[14]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[13]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[12]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[11]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[10]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[9]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[8]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[7]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[6]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[5]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[4]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[3]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[2]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[1]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[9]                                                                                              ; 7       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~4                                                                                                                                    ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1                                                                                                                                ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                      ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]~1                                                                                                          ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO                                                                                                                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD                                                                                                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal10~0                                                                                                                             ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[2]                                                                                              ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[15]                                                                                             ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[14]                                                                                             ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[15]~2                                                                                                                            ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux10~2                                                                                                                                    ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7                                                                                                                             ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END                                                                                                                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|IN_REQ                                                                                                                                ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|PM_STOP                                                                                                                               ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~1                                                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8]                                                                                                                                 ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[2]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[3]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[5]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[6]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[7]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[4]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[9]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[10]                            ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[11]                            ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[8]                             ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[5]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[3]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[4]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[8]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[7]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[6]                                                                                              ; 5       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                                                                                                                                      ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[9]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[1]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[9]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[8]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[7]                                                                                                                                  ; 5       ;
+; GPIO_1[19]~input                                                                                                                                                          ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~3                                                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~2                                                                                                                                    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0001                                                                                                                             ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0010                                                                                                                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~3                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~3                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]~1                                                                                                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK                                                                                                                     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                                                                                                                            ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~9                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                                                                                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_RD                                                                                                                                ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; 4       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_LVAL                                                                                                                                     ; 4       ;
+; DE0_D5M:inst|CCD_Capture:u3|mSTART                                                                                                                                        ; 4       ;
+; DE0_D5M:inst|rCCD_FVAL                                                                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[14]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[15]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[17]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[18]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[19]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[16]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[21]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[22]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[23]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[20]                            ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[13]                                                                                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_2~16                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[0]                                                                                                                                  ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[11]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[10]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[6]                                                                                                                                  ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[5]                                                                                                                                  ; 4       ;
+; CLOCK_50~input                                                                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK~_wirecell                                                                                                    ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~11                                                                                                                         ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~0                                                                                                                                     ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2                                                                                                                     ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0                  ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[2]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[3]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[4]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[5]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[6]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[7]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[8]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[9]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[10]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[11]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[2]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[3]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[4]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[5]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[6]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[7]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[8]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[9]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[10]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[11]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~5                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~5                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]~0                                                                                                        ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~1                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~0                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDVAL                                                                                                                                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~2                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]~2                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0                   ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0                   ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~7                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~6                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~7                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always4~0                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]                                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                                                                                                                            ; 3       ;
+; DE0_D5M:inst|CCD_Capture:u3|Pre_FVAL                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~2                                                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan5~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan4~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~0                                                                                                                                   ; 3       ;
+; DE0_D5M:inst|rClk[0]                                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]                                                                                                                        ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[1]                             ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[0]                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[1]                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[3]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[2]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[1]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[5]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[8]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[7]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[6]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[4]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[3]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[2]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[11]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[10]                                                                                                                                 ; 3       ;
+; SW[1]~input                                                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~18                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~1                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~0                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~2                                                                                                                                ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~6                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~1                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux8~0                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0000                                                                                                                             ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK~0                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1                                                                                                                     ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~2                                                                                                ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~1                                                                                                                 ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~0                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~6                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~6                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~4                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~0                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~2                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~2                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~1                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|PRECHARGE~0                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always3~0                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal8~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Mux0~16                                                                                                                  ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~2                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~0                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|LessThan2~1                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Equal4~7                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp|aneb_result_wire[0]~5               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp|aneb_result_wire[0]~0               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~4                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~3                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~4                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~4                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal7~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|LessThan2~0                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag~0                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N~0                                                                                                               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal4~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~14                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal2~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~1                                                                                                                               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_WR                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_a[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_a[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                   ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oRequest                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|LessThan0~4                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~1                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~0                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|DQM~0                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal0~1                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[5]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[6]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[7]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan4~3                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_V_SYNC                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[3]                                                                                                          ; 2       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[13]                            ; 2       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[12]                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[15]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[14]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[13]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[12]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[11]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[10]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[9]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[8]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[7]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[6]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[5]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[4]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[3]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[2]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[1]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[0]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[12]                                                                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[11]                                                                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[10]                                                                                             ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[10]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[9]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[8]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[7]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[6]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[5]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[4]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[3]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[2]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[1]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[14]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[13]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[11]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[0]                                                                                                                                  ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[4]                                                                                                                                  ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[1]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[2]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[3]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[4]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[5]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[6]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[7]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[8]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[9]                                                                                                                                     ; 2       ;
+; KEY[1]~input                                                                                                                                                              ; 1       ;
+; KEY[2]~input                                                                                                                                                              ; 1       ;
+; GPIO_1[0]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[1]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[2]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[3]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[4]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[5]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[6]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[7]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[8]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[9]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[10]~input                                                                                                                                                          ; 1       ;
+; GPIO_1[11]~input                                                                                                                                                          ; 1       ;
+; GPIO_1[17]~input                                                                                                                                                          ; 1       ;
+; GPIO_1[18]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[6]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[7]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[8]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[9]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[11]~input                                                                                                                                                         ; 1       ;
+; DRAM_DQ[12]~input                                                                                                                                                         ; 1       ;
+; DRAM_DQ[13]~input                                                                                                                                                         ; 1       ;
+; DRAM_DQ[14]~input                                                                                                                                                         ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0~_wirecell            ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0~_wirecell            ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0~_wirecell             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0~_wirecell             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]~0                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]~0                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]~0                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]~0                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]~0                                                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]~0                                                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]~0                                                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]~0                                                 ; 1       ;
+; DE0_D5M:inst|rClk[0]~0                                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux6~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux6~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux5~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux5~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~17                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~16                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~15                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~6                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~5                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~10                                                                                                                  ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~4                                                                                                                   ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~9                                                                                                      ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3~3                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~4                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~4                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~7                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~6                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux10~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~4                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Selector0~2                                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Selector1~2                                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REFRESH~2                                                                                                  ; 1       ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0~2                                                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Read~3                                                                                                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~8                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7]                                                                                                     ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~7                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                     ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~6                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5]                                                                                                     ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift~6                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift~5                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~5                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4]                                                                                                     ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~8                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~7                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~6                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~8                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~7                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~6                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift~4                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~4                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]~46                                                                                                                      ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~30                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~1                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~29                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~28                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~27                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~0                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~26                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~25                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Selector1~0                                                                                                                                ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~9                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3~2                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Selector3~0                                                                                                              ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~2                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~1                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~0                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~3                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~2                                                                                                                   ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~11                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[0]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~10                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[1]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~9                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[2]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~8                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[3]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~7                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[4]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~6                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[5]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~5                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[6]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~4                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[7]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~3                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[8]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~2                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[9]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~1                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[10]                                                                                                                                                ; 1       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4|aneb_result_wire[0]~2            ; 1       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4|aneb_result_wire[0]~1            ; 1       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4|aneb_result_wire[0]~0            ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~0                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[11]                                                                                                                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~9                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~8                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~5                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~9                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~8                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~5                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift~3                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~3                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux3~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux2~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux2~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux0~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux21~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~14                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux21~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~4                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux20~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux20~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux20~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~13                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~5                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~12                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~11                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux17~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~10                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux17~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~9                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux9~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~8                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~7                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux4~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux4~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux11~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux11~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~4                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux14~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux14~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux7~2                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux7~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux7~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux13~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux13~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~5                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux8~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux15~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux15~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux15~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux15~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[0]~8                                                                                                                             ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Selector2~0                                                                                                                                ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~12                                                                                                                               ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END~0                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Selector0~2                                                                                                              ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Selector0~1                                                                                                              ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[0]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[1]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[2]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[3]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[4]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[5]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[6]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[7]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[8]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[9]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[10]                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[11]                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~7                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~4                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~0                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~7                             ; 1       ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
+; Name                                                                                                                                              ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF  ; Location                                                                                       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 1278         ; 24           ; 1278         ; 24           ; yes                    ; no                      ; yes                    ; yes                     ; 30672 ; 1278                        ; 24                          ; 1278                        ; 24                          ; 30672               ; 6    ; None ; M9K_X25_Y13_N0, M9K_X25_Y12_N0, M9K_X25_Y11_N0, M9K_X13_Y13_N0, M9K_X13_Y12_N0, M9K_X13_Y11_N0 ; Old data             ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 8                           ; 512                         ; 8                           ; 4096                ; 1    ; None ; M9K_X25_Y23_N0                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 4                           ; 512                         ; 4                           ; 2048                ; 1    ; None ; M9K_X25_Y17_N0                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 16                          ; 512                         ; 16                          ; 8192                ; 1    ; None ; M9K_X13_Y20_N0                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 16                          ; 512                         ; 16                          ; 8192                ; 1    ; None ; M9K_X13_Y17_N0                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++------------------------------------------------+
+; Routing Usage Summary                          ;
++-----------------------+------------------------+
+; Routing Resource Type ; Usage                  ;
++-----------------------+------------------------+
+; Block interconnects   ; 1,681 / 47,787 ( 4 % ) ;
+; C16 interconnects     ; 32 / 1,804 ( 2 % )     ;
+; C4 interconnects      ; 699 / 31,272 ( 2 % )   ;
+; Direct links          ; 381 / 47,787 ( < 1 % ) ;
+; Global clocks         ; 9 / 20 ( 45 % )        ;
+; Local interconnects   ; 926 / 15,408 ( 6 % )   ;
+; R24 interconnects     ; 37 / 1,775 ( 2 % )     ;
+; R4 interconnects      ; 1,028 / 41,310 ( 2 % ) ;
++-----------------------+------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Logic Elements                                                          ;
++---------------------------------------------+-------------------------------+
+; Number of Logic Elements  (Average = 11.93) ; Number of LABs  (Total = 123) ;
++---------------------------------------------+-------------------------------+
+; 1                                           ; 12                            ;
+; 2                                           ; 2                             ;
+; 3                                           ; 1                             ;
+; 4                                           ; 5                             ;
+; 5                                           ; 2                             ;
+; 6                                           ; 5                             ;
+; 7                                           ; 7                             ;
+; 8                                           ; 1                             ;
+; 9                                           ; 1                             ;
+; 10                                          ; 1                             ;
+; 11                                          ; 0                             ;
+; 12                                          ; 4                             ;
+; 13                                          ; 4                             ;
+; 14                                          ; 13                            ;
+; 15                                          ; 10                            ;
+; 16                                          ; 55                            ;
++---------------------------------------------+-------------------------------+
+
+
++--------------------------------------------------------------------+
+; LAB-wide Signals                                                   ;
++------------------------------------+-------------------------------+
+; LAB-wide Signals  (Average = 1.85) ; Number of LABs  (Total = 123) ;
++------------------------------------+-------------------------------+
+; 1 Async. clear                     ; 72                            ;
+; 1 Clock                            ; 100                           ;
+; 1 Clock enable                     ; 37                            ;
+; 1 Sync. clear                      ; 5                             ;
+; 1 Sync. load                       ; 2                             ;
+; 2 Clock enables                    ; 1                             ;
+; 2 Clocks                           ; 11                            ;
++------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Signals Sourced                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Signals Sourced  (Average = 19.33) ; Number of LABs  (Total = 123) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 7                             ;
+; 2                                            ; 5                             ;
+; 3                                            ; 3                             ;
+; 4                                            ; 1                             ;
+; 5                                            ; 1                             ;
+; 6                                            ; 1                             ;
+; 7                                            ; 7                             ;
+; 8                                            ; 2                             ;
+; 9                                            ; 0                             ;
+; 10                                           ; 3                             ;
+; 11                                           ; 3                             ;
+; 12                                           ; 1                             ;
+; 13                                           ; 0                             ;
+; 14                                           ; 1                             ;
+; 15                                           ; 3                             ;
+; 16                                           ; 1                             ;
+; 17                                           ; 8                             ;
+; 18                                           ; 4                             ;
+; 19                                           ; 1                             ;
+; 20                                           ; 4                             ;
+; 21                                           ; 8                             ;
+; 22                                           ; 4                             ;
+; 23                                           ; 2                             ;
+; 24                                           ; 5                             ;
+; 25                                           ; 3                             ;
+; 26                                           ; 4                             ;
+; 27                                           ; 7                             ;
+; 28                                           ; 5                             ;
+; 29                                           ; 6                             ;
+; 30                                           ; 8                             ;
+; 31                                           ; 9                             ;
+; 32                                           ; 6                             ;
++----------------------------------------------+-------------------------------+
+
+
++---------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                         ;
++-------------------------------------------------+-------------------------------+
+; Number of Signals Sourced Out  (Average = 7.69) ; Number of LABs  (Total = 123) ;
++-------------------------------------------------+-------------------------------+
+; 0                                               ; 0                             ;
+; 1                                               ; 21                            ;
+; 2                                               ; 6                             ;
+; 3                                               ; 5                             ;
+; 4                                               ; 4                             ;
+; 5                                               ; 6                             ;
+; 6                                               ; 8                             ;
+; 7                                               ; 13                            ;
+; 8                                               ; 8                             ;
+; 9                                               ; 9                             ;
+; 10                                              ; 7                             ;
+; 11                                              ; 6                             ;
+; 12                                              ; 3                             ;
+; 13                                              ; 10                            ;
+; 14                                              ; 3                             ;
+; 15                                              ; 6                             ;
+; 16                                              ; 7                             ;
+; 17                                              ; 0                             ;
+; 18                                              ; 0                             ;
+; 19                                              ; 0                             ;
+; 20                                              ; 0                             ;
+; 21                                              ; 0                             ;
+; 22                                              ; 1                             ;
++-------------------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Distinct Inputs  (Average = 11.10) ; Number of LABs  (Total = 123) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 1                             ;
+; 2                                            ; 5                             ;
+; 3                                            ; 6                             ;
+; 4                                            ; 20                            ;
+; 5                                            ; 7                             ;
+; 6                                            ; 6                             ;
+; 7                                            ; 4                             ;
+; 8                                            ; 8                             ;
+; 9                                            ; 5                             ;
+; 10                                           ; 7                             ;
+; 11                                           ; 3                             ;
+; 12                                           ; 8                             ;
+; 13                                           ; 7                             ;
+; 14                                           ; 5                             ;
+; 15                                           ; 4                             ;
+; 16                                           ; 2                             ;
+; 17                                           ; 2                             ;
+; 18                                           ; 6                             ;
+; 19                                           ; 1                             ;
+; 20                                           ; 0                             ;
+; 21                                           ; 1                             ;
+; 22                                           ; 0                             ;
+; 23                                           ; 1                             ;
+; 24                                           ; 2                             ;
+; 25                                           ; 5                             ;
+; 26                                           ; 1                             ;
+; 27                                           ; 1                             ;
+; 28                                           ; 0                             ;
+; 29                                           ; 0                             ;
+; 30                                           ; 0                             ;
+; 31                                           ; 1                             ;
+; 32                                           ; 2                             ;
+; 33                                           ; 1                             ;
+; 34                                           ; 0                             ;
+; 35                                           ; 0                             ;
+; 36                                           ; 0                             ;
+; 37                                           ; 1                             ;
++----------------------------------------------+-------------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 10    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 20    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                    ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Pass         ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 140          ; 0            ; 140          ; 0            ; 0            ; 141       ; 140          ; 0            ; 141       ; 141       ; 0            ; 0            ; 0            ; 0            ; 64           ; 0            ; 0            ; 64           ; 0            ; 0            ; 29           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 141       ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 1            ; 141          ; 1            ; 141          ; 141          ; 0         ; 1            ; 141          ; 0         ; 0         ; 141          ; 141          ; 141          ; 141          ; 77           ; 141          ; 141          ; 77           ; 141          ; 141          ; 112          ; 141          ; 141          ; 141          ; 141          ; 141          ; 141          ; 0         ; 141          ; 141          ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; DRAM_LDQM          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKIN[1]    ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[9]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_UDQM          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_BA_1          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_BA_0          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CAS_N         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CKE           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CS_N          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_RAS_N         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_WE_N          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CLK           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_CLK            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_HS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_VS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[11]      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[10]      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[9]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[8]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[7]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[6]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[5]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[4]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[3]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[2]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[1]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[0]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKOUT[1]   ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKOUT[0]   ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[9]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[8]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[7]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[15]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[14]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[13]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[12]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[11]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[10]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[9]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[8]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[7]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[6]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[5]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[4]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[3]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[2]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[1]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[0]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[31]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[30]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[29]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[28]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[27]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[26]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[25]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[24]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[23]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[22]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[21]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[20]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[19]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[18]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[17]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[16]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[15]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[14]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[13]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[12]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[11]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[10]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[9]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[8]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[7]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[6]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[5]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[4]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[3]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[2]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[1]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[0]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKIN[0]    ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[0]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[2]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[1]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[0]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; Unreserved               ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                                                                 ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+; Source Clock(s)                                     ; Destination Clock(s)                                ; Delay Added in ns ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 1.5               ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                                                                                                                                                                                                                                                                     ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; Source Register                                                                                                                                      ; Destination Register                                                                                                                                                   ; Delay Added in ns ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a9~porta_address_reg0 ; 0.207             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a9~porta_address_reg0 ; 0.098             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a9~porta_address_reg0 ; 0.098             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a9~porta_address_reg0 ; 0.098             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                   ; 0.016             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]              ; 0.015             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                    ; 0.014             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                    ; 0.014             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                   ; 0.013             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                    ; 0.012             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                    ; 0.012             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]              ; 0.011             ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+Note: This table only shows the top 12 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16F484C6 for design "DE0_D5M"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (15535): Implemented PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" as Cyclone III PLL type
+    Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] port
+    Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of -117 degrees (-2600 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] port
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 4 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 141 total pins
+    Info (169086): Pin VGA_CLK not assigned to an exact location on the device
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity dcfifo_v5o1
+        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* 
+        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* 
+Info (332104): Reading SDC File: 'DE0_D5M.sdc'
+Info (332110): Deriving PLL clocks
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]}
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 3 clocks
+    Info (332111):   Period   Clock Name
+    Info (332111): ======== ============
+    Info (332111):   20.000     CLOCK_50
+    Info (332111):    8.000 inst|u6|altpll_component|auto_generated|pll1|clk[0]
+    Info (332111):    8.000 inst|u6|altpll_component|auto_generated|pll1|clk[1]
+Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|rClk[0]
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK
+Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] (placed in counter C0 of PLL_2)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
+Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] (placed in counter C1 of PLL_2)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
+Info (176353): Automatically promoted node GPIO_1_CLKIN[0]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19
+Info (176353): Automatically promoted node DE0_D5M:inst|rClk[0] 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|rClk[0]~0
+        Info (176357): Destination node GPIO_1_CLKOUT[0]~output
+        Info (176357): Destination node VGA_CLK~output
+Info (176353): Automatically promoted node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|I2C_SCLK~1
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK~0
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_0 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~6
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~43
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~47
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~43
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~47
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_0~2
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_2 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_2~0
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_1 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node GPIO_1[14]~output
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_1~1
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
+        Info (176212): I/O standards used: 3.3-V LVTTL.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 16 total pin(s) used --  30 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used --  21 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 28 total pin(s) used --  19 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  5 pins available
+Warning (15064): PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" output port clk[1] feeds output pin "DRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "CLOCK_50_2" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:03
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 2% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 6% of the available device resources in the region that extends from location X10_Y20 to location X20_Y29
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:02
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 1.79 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Warning (169177): 64 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+    Info (169178): Pin GPIO_1_CLKIN[1] uses I/O standard 3.3-V LVTTL at AA11
+    Info (169178): Pin SW[9] uses I/O standard 3.3-V LVTTL at D2
+    Info (169178): Pin SW[8] uses I/O standard 3.3-V LVTTL at E4
+    Info (169178): Pin SW[7] uses I/O standard 3.3-V LVTTL at E3
+    Info (169178): Pin SW[6] uses I/O standard 3.3-V LVTTL at H7
+    Info (169178): Pin SW[5] uses I/O standard 3.3-V LVTTL at J7
+    Info (169178): Pin SW[4] uses I/O standard 3.3-V LVTTL at G5
+    Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at G4
+    Info (169178): Pin DRAM_DQ[15] uses I/O standard 3.3-V LVTTL at F10
+    Info (169178): Pin DRAM_DQ[14] uses I/O standard 3.3-V LVTTL at E10
+    Info (169178): Pin DRAM_DQ[13] uses I/O standard 3.3-V LVTTL at A10
+    Info (169178): Pin DRAM_DQ[12] uses I/O standard 3.3-V LVTTL at B10
+    Info (169178): Pin DRAM_DQ[11] uses I/O standard 3.3-V LVTTL at C10
+    Info (169178): Pin DRAM_DQ[10] uses I/O standard 3.3-V LVTTL at A9
+    Info (169178): Pin DRAM_DQ[9] uses I/O standard 3.3-V LVTTL at B9
+    Info (169178): Pin DRAM_DQ[8] uses I/O standard 3.3-V LVTTL at A8
+    Info (169178): Pin DRAM_DQ[7] uses I/O standard 3.3-V LVTTL at F8
+    Info (169178): Pin DRAM_DQ[6] uses I/O standard 3.3-V LVTTL at H9
+    Info (169178): Pin DRAM_DQ[5] uses I/O standard 3.3-V LVTTL at G9
+    Info (169178): Pin DRAM_DQ[4] uses I/O standard 3.3-V LVTTL at F9
+    Info (169178): Pin DRAM_DQ[3] uses I/O standard 3.3-V LVTTL at E9
+    Info (169178): Pin DRAM_DQ[2] uses I/O standard 3.3-V LVTTL at H10
+    Info (169178): Pin DRAM_DQ[1] uses I/O standard 3.3-V LVTTL at G10
+    Info (169178): Pin DRAM_DQ[0] uses I/O standard 3.3-V LVTTL at D10
+    Info (169178): Pin GPIO_1[31] uses I/O standard 3.3-V LVTTL at V7
+    Info (169178): Pin GPIO_1[30] uses I/O standard 3.3-V LVTTL at V6
+    Info (169178): Pin GPIO_1[29] uses I/O standard 3.3-V LVTTL at U8
+    Info (169178): Pin GPIO_1[28] uses I/O standard 3.3-V LVTTL at Y7
+    Info (169178): Pin GPIO_1[27] uses I/O standard 3.3-V LVTTL at T9
+    Info (169178): Pin GPIO_1[26] uses I/O standard 3.3-V LVTTL at U9
+    Info (169178): Pin GPIO_1[25] uses I/O standard 3.3-V LVTTL at T10
+    Info (169178): Pin GPIO_1[24] uses I/O standard 3.3-V LVTTL at U10
+    Info (169178): Pin GPIO_1[23] uses I/O standard 3.3-V LVTTL at R12
+    Info (169178): Pin GPIO_1[22] uses I/O standard 3.3-V LVTTL at R11
+    Info (169178): Pin GPIO_1[21] uses I/O standard 3.3-V LVTTL at T12
+    Info (169178): Pin GPIO_1[20] uses I/O standard 3.3-V LVTTL at U12
+    Info (169178): Pin GPIO_1[19] uses I/O standard 3.3-V LVTTL at R14
+    Info (169178): Pin GPIO_1[18] uses I/O standard 3.3-V LVTTL at T14
+    Info (169178): Pin GPIO_1[17] uses I/O standard 3.3-V LVTTL at AB7
+    Info (169178): Pin GPIO_1[16] uses I/O standard 3.3-V LVTTL at AA7
+    Info (169178): Pin GPIO_1[15] uses I/O standard 3.3-V LVTTL at AA9
+    Info (169178): Pin GPIO_1[14] uses I/O standard 3.3-V LVTTL at AB9
+    Info (169178): Pin GPIO_1[13] uses I/O standard 3.3-V LVTTL at V15
+    Info (169178): Pin GPIO_1[12] uses I/O standard 3.3-V LVTTL at W15
+    Info (169178): Pin GPIO_1[11] uses I/O standard 3.3-V LVTTL at T15
+    Info (169178): Pin GPIO_1[10] uses I/O standard 3.3-V LVTTL at U15
+    Info (169178): Pin GPIO_1[9] uses I/O standard 3.3-V LVTTL at W17
+    Info (169178): Pin GPIO_1[8] uses I/O standard 3.3-V LVTTL at Y17
+    Info (169178): Pin GPIO_1[7] uses I/O standard 3.3-V LVTTL at AB17
+    Info (169178): Pin GPIO_1[6] uses I/O standard 3.3-V LVTTL at AA17
+    Info (169178): Pin GPIO_1[5] uses I/O standard 3.3-V LVTTL at AA18
+    Info (169178): Pin GPIO_1[4] uses I/O standard 3.3-V LVTTL at AB18
+    Info (169178): Pin GPIO_1[3] uses I/O standard 3.3-V LVTTL at AB19
+    Info (169178): Pin GPIO_1[2] uses I/O standard 3.3-V LVTTL at AA19
+    Info (169178): Pin GPIO_1[1] uses I/O standard 3.3-V LVTTL at AB20
+    Info (169178): Pin GPIO_1[0] uses I/O standard 3.3-V LVTTL at AA20
+    Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21
+    Info (169178): Pin GPIO_1_CLKIN[0] uses I/O standard 3.3-V LVTTL at AB11
+    Info (169178): Pin KEY[0] uses I/O standard 3.3-V LVTTL at H2
+    Info (169178): Pin KEY[2] uses I/O standard 3.3-V LVTTL at F1
+    Info (169178): Pin KEY[1] uses I/O standard 3.3-V LVTTL at G3
+    Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at H6
+    Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at H5
+    Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at J6
+Warning (169064): Following 31 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
+    Info (169065): Pin GPIO_1[31] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[30] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[29] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[28] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[27] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[26] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[25] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[24] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[23] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[22] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[21] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[20] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[18] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[17] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[16] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[15] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[14] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[13] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[12] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[11] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[10] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[9] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[8] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[7] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[6] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[5] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[4] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[3] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[2] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[1] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[0] has a permanently disabled output enable
+Info (144001): Generated suppressed messages file E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 22 warnings
+    Info: Peak virtual memory: 1195 megabytes
+    Info: Processing ended: Mon Mar 17 10:02:38 2014
+    Info: Elapsed time: 00:00:15
+    Info: Total CPU time (on all processors): 00:00:17
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.fit.smsg.
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.smsg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.summary b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.summary
new file mode 100644
index 0000000..c5deba6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Mon Mar 17 10:02:37 2014
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
+Revision Name : DE0_D5M
+Top-level Entity Name : TOP_CAMERA
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 1,467 / 15,408 ( 10 % )
+    Total combinational functions : 1,198 / 15,408 ( 8 % )
+    Dedicated logic registers : 1,030 / 15,408 ( 7 % )
+Total registers : 1030
+Total pins : 141 / 347 ( 41 % )
+Total virtual pins : 0
+Total memory bits : 53,200 / 516,096 ( 10 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 1 / 4 ( 25 % )
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.flow.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.flow.rpt
new file mode 100644
index 0000000..c6e71e5
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.flow.rpt
@@ -0,0 +1,124 @@
+Flow report for DE0_D5M
+Mon Mar 17 10:02:50 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Flow Summary                                                                     ;
++------------------------------------+---------------------------------------------+
+; Flow Status                        ; Successful - Mon Mar 17 10:02:44 2014       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                     ;
+; Top-level Entity Name              ; TOP_CAMERA                                  ;
+; Family                             ; Cyclone III                                 ;
+; Device                             ; EP3C16F484C6                                ;
+; Timing Models                      ; Final                                       ;
+; Total logic elements               ; 1,467 / 15,408 ( 10 % )                     ;
+;     Total combinational functions  ; 1,198 / 15,408 ( 8 % )                      ;
+;     Dedicated logic registers      ; 1,030 / 15,408 ( 7 % )                      ;
+; Total registers                    ; 1030                                        ;
+; Total pins                         ; 141 / 347 ( 41 % )                          ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 53,200 / 516,096 ( 10 % )                   ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                              ;
++------------------------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 03/17/2014 10:02:15 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; DE0_D5M             ;
++-------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                              ;
++-------------------------------------+------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                        ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 135308249136.139505053504416 ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                           ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                            ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 14622752                     ; --            ; TOP_CAMERA  ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING        ; --            ; TOP_CAMERA  ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                       ; --            ; TOP_CAMERA  ; Top        ;
+; SMART_RECOMPILE                     ; On                           ; Off           ; --          ; --         ;
+; TOP_LEVEL_ENTITY                    ; TOP_CAMERA                   ; DE0_D5M       ; --          ; --         ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS  ; Off                          ; --            ; --          ; eda_palace ;
++-------------------------------------+------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:07     ; 1.0                     ; 534 MB              ; 00:00:05                           ;
+; Fitter                    ; 00:00:14     ; 1.4                     ; 1195 MB             ; 00:00:16                           ;
+; Assembler                 ; 00:00:05     ; 1.0                     ; 450 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:03     ; 1.0                     ; 549 MB              ; 00:00:03                           ;
+; Total                     ; 00:00:29     ; --                      ; --                  ; 00:00:25                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_fit --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_sta DE0_D5M -c DE0_D5M
+
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.jdi b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.jdi
new file mode 100644
index 0000000..a949362
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="ca1109bd0682f003d2ee"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="DE0_D5M.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.rpt
new file mode 100644
index 0000000..187778f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.rpt
@@ -0,0 +1,2506 @@
+Analysis & Synthesis report for DE0_D5M
+Mon Mar 17 10:02:21 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis IP Cores Summary
+ 10. State Machine - |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST
+ 11. Registers Removed During Synthesis
+ 12. Removed Registers Triggering Further Register Optimizations
+ 13. General Register Statistics
+ 14. Inverted Register Statistics
+ 15. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 16. Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2
+ 17. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+ 18. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 19. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 20. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 21. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 22. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 23. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 24. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 25. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 26. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 27. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 28. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 29. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 30. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+ 31. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 32. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 33. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 34. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 35. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 36. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 37. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 38. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 39. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 40. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 41. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 42. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 43. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+ 44. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 45. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 46. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 47. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 48. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 49. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 50. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 51. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 52. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 53. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 54. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 55. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 56. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+ 57. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 58. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 59. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 60. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 61. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 62. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 63. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 64. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 65. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 66. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 67. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 68. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 69. Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1
+ 70. Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3
+ 71. Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component
+ 72. Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component
+ 73. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7
+ 74. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1
+ 75. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1
+ 76. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1
+ 77. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+ 78. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+ 79. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+ 80. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+ 81. Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8
+ 82. altshift_taps Parameter Settings by Entity Instance
+ 83. altpll Parameter Settings by Entity Instance
+ 84. dcfifo Parameter Settings by Entity Instance
+ 85. Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8"
+ 86. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2"
+ 87. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1"
+ 88. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2"
+ 89. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"
+ 90. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"
+ 91. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"
+ 92. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7"
+ 93. Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5"
+ 94. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"
+ 95. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4"
+ 96. Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3"
+ 97. Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1"
+ 98. Elapsed Time Per Partition
+ 99. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                     ;
++------------------------------------+---------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Mon Mar 17 10:02:21 2014       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                     ;
+; Top-level Entity Name              ; TOP_CAMERA                                  ;
+; Family                             ; Cyclone III                                 ;
+; Total logic elements               ; 1,569                                       ;
+;     Total combinational functions  ; 1,198                                       ;
+;     Dedicated logic registers      ; 1,030                                       ;
+; Total registers                    ; 1030                                        ;
+; Total pins                         ; 141                                         ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 53,200                                      ;
+; Embedded Multiplier 9-bit elements ; 0                                           ;
+; Total PLLs                         ; 1                                           ;
++------------------------------------+---------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6       ;                    ;
+; Top-level entity name                                                      ; TOP_CAMERA         ; DE0_D5M            ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; On                 ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                                               ;
++-------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path          ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                                            ; Library ;
++-------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------+---------+
+; Sdram_Control_4Port/Sdram_Params.h        ; yes             ; User Unspecified File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_Params.h        ;         ;
+; Sdram_Control_4Port/command.v             ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/command.v             ;         ;
+; Sdram_Control_4Port/control_interface.v   ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/control_interface.v   ;         ;
+; Sdram_Control_4Port/sdr_data_path.v       ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/sdr_data_path.v       ;         ;
+; Sdram_Control_4Port/Sdram_Control_4Port.v ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_Control_4Port.v ;         ;
+; Sdram_Control_4Port/Sdram_FIFO.v          ; yes             ; User Wizard-Generated File         ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v          ;         ;
+; V/VGA_Param.h                             ; yes             ; User Unspecified File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/VGA_Param.h                             ;         ;
+; V/CCD_Capture.v                           ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/CCD_Capture.v                           ;         ;
+; V/I2C_CCD_Config.v                        ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/I2C_CCD_Config.v                        ;         ;
+; V/I2C_Controller.v                        ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/I2C_Controller.v                        ;         ;
+; V/Line_Buffer.v                           ; yes             ; User Wizard-Generated File         ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/Line_Buffer.v                           ;         ;
+; V/RAW2RGB.v                               ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/RAW2RGB.v                               ;         ;
+; V/Reset_Delay.v                           ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/Reset_Delay.v                           ;         ;
+; V/sdram_pll.v                             ; yes             ; User Wizard-Generated File         ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/sdram_pll.v                             ;         ;
+; V/SEG7_LUT.v                              ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/SEG7_LUT.v                              ;         ;
+; V/SEG7_LUT_8.v                            ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/SEG7_LUT_8.v                            ;         ;
+; V/VGA_Controller.v                        ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/VGA_Controller.v                        ;         ;
+; DE0_D5M.v                                 ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.v                                 ;         ;
+; TOP_CAMERA.bdf                            ; yes             ; User Block Diagram/Schematic File  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/TOP_CAMERA.bdf                            ;         ;
+; altshift_taps.tdf                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altshift_taps.tdf                                        ;         ;
+; altdpram.inc                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc                                             ;         ;
+; lpm_counter.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.inc                                          ;         ;
+; lpm_compare.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_compare.inc                                          ;         ;
+; lpm_constant.inc                          ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_constant.inc                                         ;         ;
+; db/shift_taps_rnn.tdf                     ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/shift_taps_rnn.tdf                     ;         ;
+; db/altsyncram_lp81.tdf                    ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/altsyncram_lp81.tdf                    ;         ;
+; db/cntr_cuf.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/cntr_cuf.tdf                           ;         ;
+; db/cmpr_vgc.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/cmpr_vgc.tdf                           ;         ;
+; altpll.tdf                                ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altpll.tdf                                               ;         ;
+; aglobal131.inc                            ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc                                           ;         ;
+; stratix_pll.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_pll.inc                                          ;         ;
+; stratixii_pll.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/stratixii_pll.inc                                        ;         ;
+; cycloneii_pll.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc                                        ;         ;
+; db/altpll_9ee2.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/altpll_9ee2.tdf                        ;         ;
+; dcfifo.tdf                                ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/dcfifo.tdf                                               ;         ;
+; lpm_add_sub.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.inc                                          ;         ;
+; a_graycounter.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_graycounter.inc                                        ;         ;
+; a_fefifo.inc                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_fefifo.inc                                             ;         ;
+; a_gray2bin.inc                            ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_gray2bin.inc                                           ;         ;
+; dffpipe.inc                               ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/dffpipe.inc                                              ;         ;
+; alt_sync_fifo.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/alt_sync_fifo.inc                                        ;         ;
+; altsyncram_fifo.inc                       ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram_fifo.inc                                      ;         ;
+; db/dcfifo_v5o1.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dcfifo_v5o1.tdf                        ;         ;
+; db/a_gray2bin_tgb.tdf                     ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/a_gray2bin_tgb.tdf                     ;         ;
+; db/a_graycounter_s57.tdf                  ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/a_graycounter_s57.tdf                  ;         ;
+; db/a_graycounter_ojc.tdf                  ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/a_graycounter_ojc.tdf                  ;         ;
+; db/altsyncram_de51.tdf                    ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/altsyncram_de51.tdf                    ;         ;
+; db/dffpipe_oe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dffpipe_oe9.tdf                        ;         ;
+; db/alt_synch_pipe_qld.tdf                 ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/alt_synch_pipe_qld.tdf                 ;         ;
+; db/dffpipe_pe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dffpipe_pe9.tdf                        ;         ;
+; db/alt_synch_pipe_rld.tdf                 ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/alt_synch_pipe_rld.tdf                 ;         ;
+; db/dffpipe_qe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dffpipe_qe9.tdf                        ;         ;
+; db/cmpr_e66.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/cmpr_e66.tdf                           ;         ;
++-------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                                                                                       ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+; Resource                                    ; Usage                                                                               ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+; Estimated Total logic elements              ; 1,569                                                                               ;
+;                                             ;                                                                                     ;
+; Total combinational functions               ; 1198                                                                                ;
+; Logic element usage by number of LUT inputs ;                                                                                     ;
+;     -- 4 input functions                    ; 544                                                                                 ;
+;     -- 3 input functions                    ; 261                                                                                 ;
+;     -- <=2 input functions                  ; 393                                                                                 ;
+;                                             ;                                                                                     ;
+; Logic elements by mode                      ;                                                                                     ;
+;     -- normal mode                          ; 886                                                                                 ;
+;     -- arithmetic mode                      ; 312                                                                                 ;
+;                                             ;                                                                                     ;
+; Total registers                             ; 1030                                                                                ;
+;     -- Dedicated logic registers            ; 1030                                                                                ;
+;     -- I/O registers                        ; 0                                                                                   ;
+;                                             ;                                                                                     ;
+; I/O pins                                    ; 141                                                                                 ;
+; Total memory bits                           ; 53200                                                                               ;
+; Embedded Multiplier 9-bit elements          ; 0                                                                                   ;
+; Total PLLs                                  ; 1                                                                                   ;
+;     -- PLLs                                 ; 1                                                                                   ;
+;                                             ;                                                                                     ;
+; Maximum fan-out node                        ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ;
+; Maximum fan-out                             ; 547                                                                                 ;
+; Total fan-out                               ; 8862                                                                                ;
+; Average fan-out                             ; 3.37                                                                                ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                         ;
++-----------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                          ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                        ; Library Name ;
++-----------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |TOP_CAMERA                                         ; 1198 (2)          ; 1030 (0)     ; 53200       ; 0            ; 0       ; 0         ; 141  ; 0            ; |TOP_CAMERA                                                                                                                                                                ; work         ;
+;    |DE0_D5M:inst|                                   ; 1196 (1)          ; 1030 (15)    ; 53200       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst                                                                                                                                                   ; work         ;
+;       |CCD_Capture:u3|                              ; 66 (66)           ; 58 (58)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3                                                                                                                                    ; work         ;
+;       |I2C_CCD_Config:u8|                           ; 237 (168)         ; 132 (94)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8                                                                                                                                 ; work         ;
+;          |I2C_Controller:u0|                        ; 69 (69)           ; 38 (38)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0                                                                                                               ; work         ;
+;       |RAW2RGB:u4|                                  ; 84 (68)           ; 66 (55)      ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4                                                                                                                                        ; work         ;
+;          |Line_Buffer:u0|                           ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                                                                                                                         ; work         ;
+;             |altshift_taps:altshift_taps_component| ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component                                                                                   ; work         ;
+;                |shift_taps_rnn:auto_generated|      ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated                                                     ; work         ;
+;                   |altsyncram_lp81:altsyncram2|     ; 0 (0)             ; 0 (0)        ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2                         ; work         ;
+;                   |cntr_cuf:cntr1|                  ; 16 (13)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1                                      ; work         ;
+;                      |cmpr_vgc:cmpr4|               ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4                       ; work         ;
+;       |Reset_Delay:u2|                              ; 50 (50)           ; 35 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Reset_Delay:u2                                                                                                                                    ; work         ;
+;       |SEG7_LUT_8:u5|                               ; 28 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5                                                                                                                                     ; work         ;
+;          |SEG7_LUT:u0|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0                                                                                                                         ; work         ;
+;          |SEG7_LUT:u1|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u1                                                                                                                         ; work         ;
+;          |SEG7_LUT:u2|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u2                                                                                                                         ; work         ;
+;          |SEG7_LUT:u3|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u3                                                                                                                         ; work         ;
+;       |Sdram_Control_4Port:u7|                      ; 668 (212)         ; 697 (130)    ; 22528       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7                                                                                                                            ; work         ;
+;          |Sdram_FIFO:read_fifo1|                    ; 82 (0)            ; 116 (0)      ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|               ; 82 (0)            ; 116 (0)      ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 82 (15)           ; 116 (30)     ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:read_fifo2|                    ; 82 (0)            ; 116 (0)      ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|               ; 82 (0)            ; 116 (0)      ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 82 (15)           ; 116 (30)     ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:write_fifo1|                   ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|               ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 84 (15)           ; 116 (30)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 20 (20)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |Sdram_FIFO:write_fifo2|                   ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|               ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 84 (15)           ; 116 (30)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 20 (20)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |command:command1|                         ; 60 (60)           ; 48 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1                                                                                                           ; work         ;
+;          |control_interface:control1|               ; 64 (64)           ; 55 (55)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1                                                                                                 ; work         ;
+;       |VGA_Controller:u1|                           ; 62 (62)           ; 27 (27)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|VGA_Controller:u1                                                                                                                                 ; work         ;
+;       |sdram_pll:u6|                                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6                                                                                                                                      ; work         ;
+;          |altpll:altpll_component|                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component                                                                                                              ; work         ;
+;             |altpll_9ee2:auto_generated|            ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated                                                                                   ; work         ;
++-----------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                       ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; Name                                                                                                                                              ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1278         ; 24           ; 1278         ; 24           ; 30672 ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                 ;
++--------+----------------------------+---------+--------------+--------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+
+; Vendor ; IP Core Name               ; Version ; Release Date ; License Type ; Entity Instance                                                        ; IP Include File                                                                                ;
++--------+----------------------------+---------+--------------+--------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+
+; Altera ; Shift register (RAM-based) ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                     ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/Line_Buffer.v                  ;
+; Altera ; ALTPLL                     ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6                                  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/sdram_pll.v                    ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ;
++--------+----------------------------+---------+--------------+--------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+
+
+
+Encoding Type:  One-Hot
++----------------------------------------------------------------------+
+; State Machine - |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST ;
++----------------+----------------+----------------+-------------------+
+; Name           ; mSetup_ST.0000 ; mSetup_ST.0010 ; mSetup_ST.0001    ;
++----------------+----------------+----------------+-------------------+
+; mSetup_ST.0000 ; 0              ; 0              ; 0                 ;
+; mSetup_ST.0001 ; 1              ; 0              ; 1                 ;
+; mSetup_ST.0010 ; 1              ; 1              ; 0                 ;
++----------------+----------------+----------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                                                                                                                                                                                ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+; Register name                                                                                                                               ; Reason for Removal                                                                  ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0..5,10,15]                                                                                    ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE                                                                                    ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE                                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31]                                                                                                ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27..29]                                                                                            ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25]                                                                                                ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27..29]                                                                                 ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[0..6]                                                                                           ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7]                          ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[0..6]                                                                                             ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7]                            ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[0..6]                                                                  ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7] ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[1,2]                                                                                         ; Merged with DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]                       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7]                                                                                              ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|rClk[1]                                                                                                                        ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8]                                                                                              ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~9                                                                                                  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~10                                                                                                 ; Lost fanout                                                                         ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[16..31]                                                                                              ; Lost fanout                                                                         ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[10..15]                                                                                                  ; Lost fanout                                                                         ;
+; Total Number of Removed Registers = 154                                                                                                     ;                                                                                     ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                                                                                     ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+; Register name                                            ; Reason for Removal        ; Registers Removed due to This Register                                   ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8]       ; Stuck at VCC              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7],                          ;
+;                                                          ; due to stuck port data_in ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7],                            ;
+;                                                          ;                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7], ;
+;                                                          ;                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8]                           ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE ; Stuck at VCC              ; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE                                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[29]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[29]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[28]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[28]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 1030  ;
+; Number of registers using Synchronous Clear  ; 129   ;
+; Number of registers using Synchronous Load   ; 81    ;
+; Number of registers using Asynchronous Clear ; 723   ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 393   ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Inverted Register Statistics                                                                                                                                   ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Inverted Register                                                                                                                                    ; Fan out ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                                   ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                                    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0  ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0  ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0  ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0  ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6     ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]                                                                                       ; 12      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]                                                                                       ; 13      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]                                                                                       ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2]                                                                                       ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK                                                                                                ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1]                                                                                       ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0]                                                                                       ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END                                                                                                 ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9    ; 4       ;
+; Total number of inverted registers = 30                                                                                                              ;         ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                          ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+
+; 4:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|mCCD_G[3]                                       ;
+; 4:1                ; 20 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|mCCD_R[9]                                       ;
+; 3:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]              ;
+; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[8] ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]   ;
+; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]                      ;
+; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]                                  ;
+; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3|Y_Cont[5]                                   ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]                       ;
+; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]        ;
+; 5:1                ; 15 bits   ; 45 LEs        ; 30 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]                           ;
+; 64:1               ; 5 bits    ; 210 LEs       ; 60 LEs               ; 150 LEs                ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[15]                            ;
+; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                              ;
+; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                          ;
+; 7:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                          ;
+; 7:1                ; 10 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                               ;
+; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]          ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                      ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|Mux12                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2 ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                       ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                        ;
++---------------------------------+-------+------+----------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                            ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                             ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                       ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                       ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                        ;
++---------------------------------+-------+------+----------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                            ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                             ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                       ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                      ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                       ;
++---------------------------------+-------+------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                           ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                            ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                            ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                      ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                             ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                      ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                       ;
++---------------------------------+-------+------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                           ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                            ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                            ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                      ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                             ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1 ;
++----------------+-------+----------------------------------------------------+
+; Parameter Name ; Value ; Type                                               ;
++----------------+-------+----------------------------------------------------+
+; H_SYNC_CYC     ; 96    ; Signed Integer                                     ;
+; H_SYNC_BACK    ; 48    ; Signed Integer                                     ;
+; H_SYNC_ACT     ; 640   ; Signed Integer                                     ;
+; H_SYNC_FRONT   ; 16    ; Signed Integer                                     ;
+; H_SYNC_TOTAL   ; 800   ; Signed Integer                                     ;
+; V_SYNC_CYC     ; 2     ; Signed Integer                                     ;
+; V_SYNC_BACK    ; 33    ; Signed Integer                                     ;
+; V_SYNC_ACT     ; 480   ; Signed Integer                                     ;
+; V_SYNC_FRONT   ; 10    ; Signed Integer                                     ;
+; V_SYNC_TOTAL   ; 525   ; Signed Integer                                     ;
+; X_START        ; 144   ; Signed Integer                                     ;
+; Y_START        ; 35    ; Signed Integer                                     ;
++----------------+-------+----------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3 ;
++----------------+-------+-------------------------------------------------+
+; Parameter Name ; Value ; Type                                            ;
++----------------+-------+-------------------------------------------------+
+; COLUMN_WIDTH   ; 1280  ; Signed Integer                                  ;
++----------------+-------+-------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+; Parameter Name ; Value          ; Type                                                                                    ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA  ; 1              ; Untyped                                                                                 ;
+; NUMBER_OF_TAPS ; 2              ; Signed Integer                                                                          ;
+; TAP_DISTANCE   ; 1280           ; Signed Integer                                                                          ;
+; WIDTH          ; 12             ; Signed Integer                                                                          ;
+; POWER_UP_STATE ; CLEARED        ; Untyped                                                                                 ;
+; CBXI_PARAMETER ; shift_taps_rnn ; Untyped                                                                                 ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ;
++-------------------------------+-------------------+--------------------------------------------+
+; Parameter Name                ; Value             ; Type                                       ;
++-------------------------------+-------------------+--------------------------------------------+
+; OPERATION_MODE                ; NORMAL            ; Untyped                                    ;
+; PLL_TYPE                      ; AUTO              ; Untyped                                    ;
+; LPM_HINT                      ; UNUSED            ; Untyped                                    ;
+; QUALIFY_CONF_DONE             ; OFF               ; Untyped                                    ;
+; COMPENSATE_CLOCK              ; CLK0              ; Untyped                                    ;
+; SCAN_CHAIN                    ; LONG              ; Untyped                                    ;
+; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                                    ;
+; INCLK0_INPUT_FREQUENCY        ; 20000             ; Signed Integer                             ;
+; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                                    ;
+; GATE_LOCK_SIGNAL              ; NO                ; Untyped                                    ;
+; GATE_LOCK_COUNTER             ; 0                 ; Untyped                                    ;
+; LOCK_HIGH                     ; 1                 ; Untyped                                    ;
+; LOCK_LOW                      ; 1                 ; Untyped                                    ;
+; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                                    ;
+; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                                    ;
+; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                                    ;
+; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                                    ;
+; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                                    ;
+; SKIP_VCO                      ; OFF               ; Untyped                                    ;
+; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                                    ;
+; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                                    ;
+; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                                    ;
+; BANDWIDTH                     ; 0                 ; Untyped                                    ;
+; BANDWIDTH_TYPE                ; AUTO              ; Untyped                                    ;
+; SPREAD_FREQUENCY              ; 0                 ; Untyped                                    ;
+; DOWN_SPREAD                   ; 0                 ; Untyped                                    ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                                    ;
+; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped                                    ;
+; CLK9_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK8_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK7_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK6_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK2_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK1_MULTIPLY_BY              ; 5                 ; Signed Integer                             ;
+; CLK0_MULTIPLY_BY              ; 5                 ; Signed Integer                             ;
+; CLK9_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK8_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK7_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK6_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK5_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK4_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK3_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK2_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK1_DIVIDE_BY                ; 2                 ; Signed Integer                             ;
+; CLK0_DIVIDE_BY                ; 2                 ; Signed Integer                             ;
+; CLK9_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK8_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK7_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK6_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK1_PHASE_SHIFT              ; -2600             ; Untyped                                    ;
+; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK5_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK4_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK3_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK2_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK1_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK0_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK9_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK8_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK7_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK6_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK5_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK4_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK3_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK2_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK1_DUTY_CYCLE               ; 50                ; Signed Integer                             ;
+; CLK0_DUTY_CYCLE               ; 50                ; Signed Integer                             ;
+; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; LOCK_WINDOW_UI                ;  0.05             ; Untyped                                    ;
+; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped                                    ;
+; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped                                    ;
+; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped                                    ;
+; DPA_MULTIPLY_BY               ; 0                 ; Untyped                                    ;
+; DPA_DIVIDE_BY                 ; 1                 ; Untyped                                    ;
+; DPA_DIVIDER                   ; 0                 ; Untyped                                    ;
+; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; VCO_MULTIPLY_BY               ; 0                 ; Untyped                                    ;
+; VCO_DIVIDE_BY                 ; 0                 ; Untyped                                    ;
+; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                                    ;
+; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                                    ;
+; VCO_MIN                       ; 0                 ; Untyped                                    ;
+; VCO_MAX                       ; 0                 ; Untyped                                    ;
+; VCO_CENTER                    ; 0                 ; Untyped                                    ;
+; PFD_MIN                       ; 0                 ; Untyped                                    ;
+; PFD_MAX                       ; 0                 ; Untyped                                    ;
+; M_INITIAL                     ; 0                 ; Untyped                                    ;
+; M                             ; 0                 ; Untyped                                    ;
+; N                             ; 1                 ; Untyped                                    ;
+; M2                            ; 1                 ; Untyped                                    ;
+; N2                            ; 1                 ; Untyped                                    ;
+; SS                            ; 1                 ; Untyped                                    ;
+; C0_HIGH                       ; 0                 ; Untyped                                    ;
+; C1_HIGH                       ; 0                 ; Untyped                                    ;
+; C2_HIGH                       ; 0                 ; Untyped                                    ;
+; C3_HIGH                       ; 0                 ; Untyped                                    ;
+; C4_HIGH                       ; 0                 ; Untyped                                    ;
+; C5_HIGH                       ; 0                 ; Untyped                                    ;
+; C6_HIGH                       ; 0                 ; Untyped                                    ;
+; C7_HIGH                       ; 0                 ; Untyped                                    ;
+; C8_HIGH                       ; 0                 ; Untyped                                    ;
+; C9_HIGH                       ; 0                 ; Untyped                                    ;
+; C0_LOW                        ; 0                 ; Untyped                                    ;
+; C1_LOW                        ; 0                 ; Untyped                                    ;
+; C2_LOW                        ; 0                 ; Untyped                                    ;
+; C3_LOW                        ; 0                 ; Untyped                                    ;
+; C4_LOW                        ; 0                 ; Untyped                                    ;
+; C5_LOW                        ; 0                 ; Untyped                                    ;
+; C6_LOW                        ; 0                 ; Untyped                                    ;
+; C7_LOW                        ; 0                 ; Untyped                                    ;
+; C8_LOW                        ; 0                 ; Untyped                                    ;
+; C9_LOW                        ; 0                 ; Untyped                                    ;
+; C0_INITIAL                    ; 0                 ; Untyped                                    ;
+; C1_INITIAL                    ; 0                 ; Untyped                                    ;
+; C2_INITIAL                    ; 0                 ; Untyped                                    ;
+; C3_INITIAL                    ; 0                 ; Untyped                                    ;
+; C4_INITIAL                    ; 0                 ; Untyped                                    ;
+; C5_INITIAL                    ; 0                 ; Untyped                                    ;
+; C6_INITIAL                    ; 0                 ; Untyped                                    ;
+; C7_INITIAL                    ; 0                 ; Untyped                                    ;
+; C8_INITIAL                    ; 0                 ; Untyped                                    ;
+; C9_INITIAL                    ; 0                 ; Untyped                                    ;
+; C0_MODE                       ; BYPASS            ; Untyped                                    ;
+; C1_MODE                       ; BYPASS            ; Untyped                                    ;
+; C2_MODE                       ; BYPASS            ; Untyped                                    ;
+; C3_MODE                       ; BYPASS            ; Untyped                                    ;
+; C4_MODE                       ; BYPASS            ; Untyped                                    ;
+; C5_MODE                       ; BYPASS            ; Untyped                                    ;
+; C6_MODE                       ; BYPASS            ; Untyped                                    ;
+; C7_MODE                       ; BYPASS            ; Untyped                                    ;
+; C8_MODE                       ; BYPASS            ; Untyped                                    ;
+; C9_MODE                       ; BYPASS            ; Untyped                                    ;
+; C0_PH                         ; 0                 ; Untyped                                    ;
+; C1_PH                         ; 0                 ; Untyped                                    ;
+; C2_PH                         ; 0                 ; Untyped                                    ;
+; C3_PH                         ; 0                 ; Untyped                                    ;
+; C4_PH                         ; 0                 ; Untyped                                    ;
+; C5_PH                         ; 0                 ; Untyped                                    ;
+; C6_PH                         ; 0                 ; Untyped                                    ;
+; C7_PH                         ; 0                 ; Untyped                                    ;
+; C8_PH                         ; 0                 ; Untyped                                    ;
+; C9_PH                         ; 0                 ; Untyped                                    ;
+; L0_HIGH                       ; 1                 ; Untyped                                    ;
+; L1_HIGH                       ; 1                 ; Untyped                                    ;
+; G0_HIGH                       ; 1                 ; Untyped                                    ;
+; G1_HIGH                       ; 1                 ; Untyped                                    ;
+; G2_HIGH                       ; 1                 ; Untyped                                    ;
+; G3_HIGH                       ; 1                 ; Untyped                                    ;
+; E0_HIGH                       ; 1                 ; Untyped                                    ;
+; E1_HIGH                       ; 1                 ; Untyped                                    ;
+; E2_HIGH                       ; 1                 ; Untyped                                    ;
+; E3_HIGH                       ; 1                 ; Untyped                                    ;
+; L0_LOW                        ; 1                 ; Untyped                                    ;
+; L1_LOW                        ; 1                 ; Untyped                                    ;
+; G0_LOW                        ; 1                 ; Untyped                                    ;
+; G1_LOW                        ; 1                 ; Untyped                                    ;
+; G2_LOW                        ; 1                 ; Untyped                                    ;
+; G3_LOW                        ; 1                 ; Untyped                                    ;
+; E0_LOW                        ; 1                 ; Untyped                                    ;
+; E1_LOW                        ; 1                 ; Untyped                                    ;
+; E2_LOW                        ; 1                 ; Untyped                                    ;
+; E3_LOW                        ; 1                 ; Untyped                                    ;
+; L0_INITIAL                    ; 1                 ; Untyped                                    ;
+; L1_INITIAL                    ; 1                 ; Untyped                                    ;
+; G0_INITIAL                    ; 1                 ; Untyped                                    ;
+; G1_INITIAL                    ; 1                 ; Untyped                                    ;
+; G2_INITIAL                    ; 1                 ; Untyped                                    ;
+; G3_INITIAL                    ; 1                 ; Untyped                                    ;
+; E0_INITIAL                    ; 1                 ; Untyped                                    ;
+; E1_INITIAL                    ; 1                 ; Untyped                                    ;
+; E2_INITIAL                    ; 1                 ; Untyped                                    ;
+; E3_INITIAL                    ; 1                 ; Untyped                                    ;
+; L0_MODE                       ; BYPASS            ; Untyped                                    ;
+; L1_MODE                       ; BYPASS            ; Untyped                                    ;
+; G0_MODE                       ; BYPASS            ; Untyped                                    ;
+; G1_MODE                       ; BYPASS            ; Untyped                                    ;
+; G2_MODE                       ; BYPASS            ; Untyped                                    ;
+; G3_MODE                       ; BYPASS            ; Untyped                                    ;
+; E0_MODE                       ; BYPASS            ; Untyped                                    ;
+; E1_MODE                       ; BYPASS            ; Untyped                                    ;
+; E2_MODE                       ; BYPASS            ; Untyped                                    ;
+; E3_MODE                       ; BYPASS            ; Untyped                                    ;
+; L0_PH                         ; 0                 ; Untyped                                    ;
+; L1_PH                         ; 0                 ; Untyped                                    ;
+; G0_PH                         ; 0                 ; Untyped                                    ;
+; G1_PH                         ; 0                 ; Untyped                                    ;
+; G2_PH                         ; 0                 ; Untyped                                    ;
+; G3_PH                         ; 0                 ; Untyped                                    ;
+; E0_PH                         ; 0                 ; Untyped                                    ;
+; E1_PH                         ; 0                 ; Untyped                                    ;
+; E2_PH                         ; 0                 ; Untyped                                    ;
+; E3_PH                         ; 0                 ; Untyped                                    ;
+; M_PH                          ; 0                 ; Untyped                                    ;
+; C1_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C2_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C3_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C4_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C5_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C6_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C7_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C8_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C9_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; CLK0_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK1_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK2_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK3_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK4_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK5_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK6_COUNTER                  ; E0                ; Untyped                                    ;
+; CLK7_COUNTER                  ; E1                ; Untyped                                    ;
+; CLK8_COUNTER                  ; E2                ; Untyped                                    ;
+; CLK9_COUNTER                  ; E3                ; Untyped                                    ;
+; L0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; L1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G2_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G3_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E2_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E3_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; M_TIME_DELAY                  ; 0                 ; Untyped                                    ;
+; N_TIME_DELAY                  ; 0                 ; Untyped                                    ;
+; EXTCLK3_COUNTER               ; E3                ; Untyped                                    ;
+; EXTCLK2_COUNTER               ; E2                ; Untyped                                    ;
+; EXTCLK1_COUNTER               ; E1                ; Untyped                                    ;
+; EXTCLK0_COUNTER               ; E0                ; Untyped                                    ;
+; ENABLE0_COUNTER               ; L0                ; Untyped                                    ;
+; ENABLE1_COUNTER               ; L0                ; Untyped                                    ;
+; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                                    ;
+; LOOP_FILTER_R                 ;  1.000000         ; Untyped                                    ;
+; LOOP_FILTER_C                 ; 5                 ; Untyped                                    ;
+; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped                                    ;
+; LOOP_FILTER_R_BITS            ; 9999              ; Untyped                                    ;
+; LOOP_FILTER_C_BITS            ; 9999              ; Untyped                                    ;
+; VCO_POST_SCALE                ; 0                 ; Untyped                                    ;
+; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; INTENDED_DEVICE_FAMILY        ; Cyclone III       ; Untyped                                    ;
+; PORT_CLKENA0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA2                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA3                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA4                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA5                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLK0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK2                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK3                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKBAD0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKBAD1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK0                     ; PORT_USED         ; Untyped                                    ;
+; PORT_CLK1                     ; PORT_USED         ; Untyped                                    ;
+; PORT_CLK2                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK3                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK4                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK5                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK6                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK7                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK8                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK9                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDATA                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDATAOUT              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDONE                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_ACTIVECLOCK              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKLOSS                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_INCLK1                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_INCLK0                   ; PORT_USED         ; Untyped                                    ;
+; PORT_FBIN                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PLLENA                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKSWITCH                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_ARESET                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PFDENA                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANCLK                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANACLR                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANREAD                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANWRITE                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_LOCKED                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CONFIGUPDATE             ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_PHASEDONE                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASESTEP                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASEUPDOWN              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANCLKENA               ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped                                    ;
+; M_TEST_SOURCE                 ; 5                 ; Untyped                                    ;
+; C0_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C1_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C2_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C3_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C4_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C5_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C6_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C7_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C8_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C9_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; CBXI_PARAMETER                ; altpll_9ee2       ; Untyped                                    ;
+; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped                                    ;
+; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped                                    ;
+; WIDTH_CLOCK                   ; 5                 ; Signed Integer                             ;
+; WIDTH_PHASECOUNTERSELECT      ; 4                 ; Untyped                                    ;
+; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped                                    ;
+; DEVICE_FAMILY                 ; Cyclone III       ; Untyped                                    ;
+; SCAN_CHAIN_MIF_FILE           ; UNUSED            ; Untyped                                    ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF               ; Untyped                                    ;
+; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                                 ;
+; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                               ;
+; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                               ;
+; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                             ;
++-------------------------------+-------------------+--------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7 ;
++----------------+-------+---------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                    ;
++----------------+-------+---------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                          ;
+; REF_PER        ; 1024  ; Signed Integer                                          ;
+; SC_CL          ; 3     ; Signed Integer                                          ;
+; SC_RCD         ; 3     ; Signed Integer                                          ;
+; SC_RRD         ; 7     ; Signed Integer                                          ;
+; SC_PM          ; 1     ; Signed Integer                                          ;
+; SC_BL          ; 1     ; Signed Integer                                          ;
+; SDR_BL         ; 111   ; Unsigned Binary                                         ;
+; SDR_BT         ; 0     ; Unsigned Binary                                         ;
+; SDR_CL         ; 011   ; Unsigned Binary                                         ;
++----------------+-------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1 ;
++----------------+-------+------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                               ;
++----------------+-------+------------------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                                     ;
+; REF_PER        ; 1024  ; Signed Integer                                                                     ;
+; SC_CL          ; 3     ; Signed Integer                                                                     ;
+; SC_RCD         ; 3     ; Signed Integer                                                                     ;
+; SC_RRD         ; 7     ; Signed Integer                                                                     ;
+; SC_PM          ; 1     ; Signed Integer                                                                     ;
+; SC_BL          ; 1     ; Signed Integer                                                                     ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                                    ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                                    ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                                    ;
++----------------+-------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1 ;
++----------------+-------+--------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                     ;
++----------------+-------+--------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                           ;
+; REF_PER        ; 1024  ; Signed Integer                                                           ;
+; SC_CL          ; 3     ; Signed Integer                                                           ;
+; SC_RCD         ; 3     ; Signed Integer                                                           ;
+; SC_RRD         ; 7     ; Signed Integer                                                           ;
+; SC_PM          ; 1     ; Signed Integer                                                           ;
+; SC_BL          ; 1     ; Signed Integer                                                           ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                          ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                          ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                          ;
++----------------+-------+--------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1 ;
++----------------+-------+----------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                             ;
++----------------+-------+----------------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                                   ;
+; REF_PER        ; 1024  ; Signed Integer                                                                   ;
+; SC_CL          ; 3     ; Signed Integer                                                                   ;
+; SC_RCD         ; 3     ; Signed Integer                                                                   ;
+; SC_RRD         ; 7     ; Signed Integer                                                                   ;
+; SC_PM          ; 1     ; Signed Integer                                                                   ;
+; SC_BL          ; 1     ; Signed Integer                                                                   ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                                  ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                                  ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                                  ;
++----------------+-------+----------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                    ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                 ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                              ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                            ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                            ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                          ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                          ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                          ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                          ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                 ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                 ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                 ;
+; USE_EAB                 ; ON          ; Untyped                                                                                 ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                 ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                 ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                 ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                 ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                 ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                 ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                 ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                 ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                 ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                 ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                    ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                 ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                              ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                            ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                            ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                          ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                          ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                          ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                          ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                 ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                 ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                 ;
+; USE_EAB                 ; ON          ; Untyped                                                                                 ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                 ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                 ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                 ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                 ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                 ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                 ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                 ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                 ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                 ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                 ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                   ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                             ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                           ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                           ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                         ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                         ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                         ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                         ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                ;
+; USE_EAB                 ; ON          ; Untyped                                                                                ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                   ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                             ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                           ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                           ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                         ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                         ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                         ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                         ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                ;
+; USE_EAB                 ; ON          ; Untyped                                                                                ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8 ;
++-----------------------+------------------+----------------------------------+
+; Parameter Name        ; Value            ; Type                             ;
++-----------------------+------------------+----------------------------------+
+; default_exposure      ; 0000011111000000 ; Unsigned Binary                  ;
+; exposure_change_value ; 0000000011001000 ; Unsigned Binary                  ;
+; CLK_Freq              ; 50000000         ; Signed Integer                   ;
+; I2C_Freq              ; 20000            ; Signed Integer                   ;
+; LUT_SIZE              ; 25               ; Signed Integer                   ;
++-----------------------+------------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; altshift_taps Parameter Settings by Entity Instance                                                       ;
++----------------------------+------------------------------------------------------------------------------+
+; Name                       ; Value                                                                        ;
++----------------------------+------------------------------------------------------------------------------+
+; Number of entity instances ; 1                                                                            ;
+; Entity Instance            ; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
+;     -- NUMBER_OF_TAPS      ; 2                                                                            ;
+;     -- TAP_DISTANCE        ; 1280                                                                         ;
+;     -- WIDTH               ; 12                                                                           ;
++----------------------------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------+
+; altpll Parameter Settings by Entity Instance                                      ;
++-------------------------------+---------------------------------------------------+
+; Name                          ; Value                                             ;
++-------------------------------+---------------------------------------------------+
+; Number of entity instances    ; 1                                                 ;
+; Entity Instance               ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ;
+;     -- OPERATION_MODE         ; NORMAL                                            ;
+;     -- PLL_TYPE               ; AUTO                                              ;
+;     -- PRIMARY_CLOCK          ; INCLK0                                            ;
+;     -- INCLK0_INPUT_FREQUENCY ; 20000                                             ;
+;     -- INCLK1_INPUT_FREQUENCY ; 0                                                 ;
+;     -- VCO_MULTIPLY_BY        ; 0                                                 ;
+;     -- VCO_DIVIDE_BY          ; 0                                                 ;
++-------------------------------+---------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; dcfifo Parameter Settings by Entity Instance                                                                    ;
++----------------------------+------------------------------------------------------------------------------------+
+; Name                       ; Value                                                                              ;
++----------------------------+------------------------------------------------------------------------------------+
+; Number of entity instances ; 4                                                                                  ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component  ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component  ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
++----------------------------+------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8"                                                                                                                   ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port       ; Type  ; Severity ; Details                                                                                                                                      ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; iUART_CTRL ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2"                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1"                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2"                                                 ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"                                                 ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"                       ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; DM   ; Input  ; Info     ; Stuck at GND                                                                        ;
+; DQM  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"                                                                                 ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port     ; Type  ; Severity ; Details                                                                                                                                      ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; CMD      ; Input ; Warning  ; Input port expression (2 bits) is smaller than the input port (3 bits) it drives.  Extra input bit(s) "CMD[2..2]" will be connected to GND.  ;
+; INIT_ACK ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7"                                                                                                                                                               ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port                 ; Type   ; Severity ; Details                                                                                                                                                                            ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; RESET_N              ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_DATA[15]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_ADDR             ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR1_ADDR[22..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR1_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[22..19] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_DATA[15]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR             ; Input  ; Warning  ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives.  Extra input bit(s) "WR2_ADDR[22..22]" will be connected to GND.                               ;
+; WR2_ADDR[19..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR[22]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR[21]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR2_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[22..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[20]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[19]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_DATA[15]         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; RD1_ADDR             ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD1_ADDR[22..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD1_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[22..19] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_DATA[15]         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; RD2_ADDR             ; Input  ; Warning  ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives.  Extra input bit(s) "RD2_ADDR[22..22]" will be connected to GND.                               ;
+; RD2_ADDR[19..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_ADDR[22]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_ADDR[21]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD2_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[22..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[20]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[19]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; CS_N                 ; Output ; Warning  ; Output or bidir port (2 bits) is wider than the port expression (1 bits) it drives; bit(s) "CS_N[1..1]" have no fanouts                                                            ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5" ;
++-------+--------+----------+----------------------------+
+; Port  ; Type   ; Severity ; Details                    ;
++-------+--------+----------+----------------------------+
+; oSEG4 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG5 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG6 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG7 ; Output ; Info     ; Explicitly unconnected     ;
++-------+--------+----------+----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"                                                                      ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port     ; Type   ; Severity ; Details                                                                                                  ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; shiftout ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4"                                                                                                                                                                   ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port         ; Type   ; Severity ; Details                                                                                                                                                                            ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; oRed[1..0]   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; oGreen[1..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; oBlue[1..0]  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; iX_Cont      ; Input  ; Warning  ; Input port expression (16 bits) is wider than the input port (11 bits) it drives.  The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; iY_Cont      ; Input  ; Warning  ; Input port expression (16 bits) is wider than the input port (11 bits) it drives.  The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3"                                                                   ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port            ; Type   ; Severity ; Details                                                                             ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+; oX_Cont[15..11] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; oY_Cont[15..11] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1"                                                                                  ;
++--------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port         ; Type   ; Severity ; Details                                                                                                  ;
++--------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; oVGA_R[5..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                      ;
+; oVGA_G[5..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                      ;
+; oVGA_B[5..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                      ;
+; oVGA_SYNC    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; oVGA_BLANK   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; oVGA_CLOCK   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++--------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:02     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Mon Mar 17 10:02:13 2014
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/command.v
+    Info (12023): Found entity 1: command
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/control_interface.v
+    Info (12023): Found entity 1: control_interface
+Warning (10229): Verilog HDL Expression warning at sdr_data_path.v(68): truncated literal to match 1 bits
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdr_data_path.v
+    Info (12023): Found entity 1: sdr_data_path
+Warning (10238): Verilog Module Declaration warning at Sdram_Control_4Port.v(90): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "Sdram_Control_4Port"
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_control_4port.v
+    Info (12023): Found entity 1: Sdram_Control_4Port
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_fifo.v
+    Info (12023): Found entity 1: Sdram_FIFO
+Warning (12019): Can't analyze file -- file V/async_receiver.v is missing
+Info (12021): Found 1 design units, including 1 entities, in source file v/ccd_capture.v
+    Info (12023): Found entity 1: CCD_Capture
+Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_ccd_config.v
+    Info (12023): Found entity 1: I2C_CCD_Config
+Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_controller.v
+    Info (12023): Found entity 1: I2C_Controller
+Info (12021): Found 1 design units, including 1 entities, in source file v/line_buffer.v
+    Info (12023): Found entity 1: Line_Buffer
+Info (12021): Found 1 design units, including 1 entities, in source file v/raw2rgb.v
+    Info (12023): Found entity 1: RAW2RGB
+Info (12021): Found 1 design units, including 1 entities, in source file v/reset_delay.v
+    Info (12023): Found entity 1: Reset_Delay
+Info (12021): Found 1 design units, including 1 entities, in source file v/sdram_pll.v
+    Info (12023): Found entity 1: sdram_pll
+Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut.v
+    Info (12023): Found entity 1: SEG7_LUT
+Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut_8.v
+    Info (12023): Found entity 1: SEG7_LUT_8
+Warning (12019): Can't analyze file -- file V/uart_crtl.v is missing
+Info (12021): Found 1 design units, including 1 entities, in source file v/vga_controller.v
+    Info (12023): Found entity 1: VGA_Controller
+Info (12021): Found 1 design units, including 1 entities, in source file de0_d5m.v
+    Info (12023): Found entity 1: DE0_D5M
+Info (12021): Found 1 design units, including 1 entities, in source file top_camera.bdf
+    Info (12023): Found entity 1: TOP_CAMERA
+Info (12127): Elaborating entity "TOP_CAMERA" for the top level hierarchy
+Info (12128): Elaborating entity "DE0_D5M" for hierarchy "DE0_D5M:inst"
+Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(188): truncated value with size 16 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(193): truncated value with size 32 to match size of target (2)
+Warning (10034): Output port "GPIO_1_CLKOUT[1]" at DE0_D5M.v(122) has no driver
+Info (12128): Elaborating entity "VGA_Controller" for hierarchy "DE0_D5M:inst|VGA_Controller:u1"
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(47): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(50): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(53): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(84): truncated value with size 32 to match size of target (12)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(110): truncated value with size 32 to match size of target (12)
+Info (12128): Elaborating entity "Reset_Delay" for hierarchy "DE0_D5M:inst|Reset_Delay:u2"
+Info (12128): Elaborating entity "CCD_Capture" for hierarchy "DE0_D5M:inst|CCD_Capture:u3"
+Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(162): object "ifval_fedge" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(163): object "y_cnt_d" assigned a value but never read
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(123): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(127): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(183): truncated value with size 32 to match size of target (1)
+Info (12128): Elaborating entity "RAW2RGB" for hierarchy "DE0_D5M:inst|RAW2RGB:u4"
+Info (12128): Elaborating entity "Line_Buffer" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"
+Info (12128): Elaborating entity "altshift_taps" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component" with the following parameter:
+    Info (12134): Parameter "lpm_type" = "altshift_taps"
+    Info (12134): Parameter "number_of_taps" = "2"
+    Info (12134): Parameter "tap_distance" = "1280"
+    Info (12134): Parameter "width" = "12"
+Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_rnn.tdf
+    Info (12023): Found entity 1: shift_taps_rnn
+Info (12128): Elaborating entity "shift_taps_rnn" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_lp81.tdf
+    Info (12023): Found entity 1: altsyncram_lp81
+Info (12128): Elaborating entity "altsyncram_lp81" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_cuf.tdf
+    Info (12023): Found entity 1: cntr_cuf
+Info (12128): Elaborating entity "cntr_cuf" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_vgc.tdf
+    Info (12023): Found entity 1: cmpr_vgc
+Info (12128): Elaborating entity "cmpr_vgc" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4"
+Info (12128): Elaborating entity "SEG7_LUT_8" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5"
+Info (12128): Elaborating entity "SEG7_LUT" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0"
+Info (12128): Elaborating entity "sdram_pll" for hierarchy "DE0_D5M:inst|sdram_pll:u6"
+Info (12128): Elaborating entity "altpll" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component" with the following parameter:
+    Info (12134): Parameter "bandwidth_type" = "AUTO"
+    Info (12134): Parameter "clk0_divide_by" = "2"
+    Info (12134): Parameter "clk0_duty_cycle" = "50"
+    Info (12134): Parameter "clk0_multiply_by" = "5"
+    Info (12134): Parameter "clk0_phase_shift" = "0"
+    Info (12134): Parameter "clk1_divide_by" = "2"
+    Info (12134): Parameter "clk1_duty_cycle" = "50"
+    Info (12134): Parameter "clk1_multiply_by" = "5"
+    Info (12134): Parameter "clk1_phase_shift" = "-2600"
+    Info (12134): Parameter "compensate_clock" = "CLK0"
+    Info (12134): Parameter "inclk0_input_frequency" = "20000"
+    Info (12134): Parameter "intended_device_family" = "Cyclone III"
+    Info (12134): Parameter "lpm_type" = "altpll"
+    Info (12134): Parameter "operation_mode" = "NORMAL"
+    Info (12134): Parameter "pll_type" = "AUTO"
+    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
+    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
+    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
+    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
+    Info (12134): Parameter "port_inclk0" = "PORT_USED"
+    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
+    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
+    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk0" = "PORT_USED"
+    Info (12134): Parameter "port_clk1" = "PORT_USED"
+    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
+    Info (12134): Parameter "width_clock" = "5"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_9ee2.tdf
+    Info (12023): Found entity 1: altpll_9ee2
+Info (12128): Elaborating entity "altpll_9ee2" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated"
+Info (12128): Elaborating entity "Sdram_Control_4Port" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7"
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(385): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(431): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(432): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(433): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(434): truncated value with size 32 to match size of target (23)
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (12128): Elaborating entity "control_interface" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"
+Warning (10230): Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at control_interface.v(167): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at control_interface.v(192): truncated value with size 32 to match size of target (16)
+Info (12128): Elaborating entity "command" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe_shift", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe1", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe2", which holds its previous value in one or more paths through the always construct
+Info (12128): Elaborating entity "sdr_data_path" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"
+Warning (10230): Verilog HDL assignment warning at sdr_data_path.v(68): truncated value with size 32 to match size of target (2)
+Info (12128): Elaborating entity "Sdram_FIFO" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"
+Warning (272007): Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2
+Warning (272007): Device family Cyclone III does not have M4K blocks -- using available memory blocks
+Info (12128): Elaborating entity "dcfifo" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component" with the following parameter:
+    Info (12134): Parameter "add_ram_output_register" = "OFF"
+    Info (12134): Parameter "clocks_are_synchronized" = "FALSE"
+    Info (12134): Parameter "intended_device_family" = "Cyclone"
+    Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=M4K"
+    Info (12134): Parameter "lpm_numwords" = "512"
+    Info (12134): Parameter "lpm_showahead" = "OFF"
+    Info (12134): Parameter "lpm_type" = "dcfifo"
+    Info (12134): Parameter "lpm_width" = "16"
+    Info (12134): Parameter "lpm_widthu" = "9"
+    Info (12134): Parameter "overflow_checking" = "ON"
+    Info (12134): Parameter "underflow_checking" = "ON"
+    Info (12134): Parameter "use_eab" = "ON"
+Warning (287001): Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2
+Warning (287001): Assertion warning: Device family Cyclone III does not have M4K blocks -- using available memory blocks
+Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_v5o1.tdf
+    Info (12023): Found entity 1: dcfifo_v5o1
+Info (12128): Elaborating entity "dcfifo_v5o1" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf
+    Info (12023): Found entity 1: a_gray2bin_tgb
+Info (12128): Elaborating entity "a_gray2bin_tgb" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf
+    Info (12023): Found entity 1: a_graycounter_s57
+Info (12128): Elaborating entity "a_graycounter_s57" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf
+    Info (12023): Found entity 1: a_graycounter_ojc
+Info (12128): Elaborating entity "a_graycounter_ojc" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_de51.tdf
+    Info (12023): Found entity 1: altsyncram_de51
+Info (12128): Elaborating entity "altsyncram_de51" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf
+    Info (12023): Found entity 1: dffpipe_oe9
+Info (12128): Elaborating entity "dffpipe_oe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_qld.tdf
+    Info (12023): Found entity 1: alt_synch_pipe_qld
+Info (12128): Elaborating entity "alt_synch_pipe_qld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf
+    Info (12023): Found entity 1: dffpipe_pe9
+Info (12128): Elaborating entity "dffpipe_pe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13"
+Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf
+    Info (12023): Found entity 1: alt_synch_pipe_rld
+Info (12128): Elaborating entity "alt_synch_pipe_rld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf
+    Info (12023): Found entity 1: dffpipe_qe9
+Info (12128): Elaborating entity "dffpipe_qe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_e66.tdf
+    Info (12023): Found entity 1: cmpr_e66
+Info (12128): Elaborating entity "cmpr_e66" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp"
+Info (12128): Elaborating entity "I2C_CCD_Config" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8"
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(126): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(127): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(160): truncated value with size 32 to match size of target (25)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(165): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(190): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(240): truncated value with size 32 to match size of target (6)
+Info (12128): Elaborating entity "I2C_Controller" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(70): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(69): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(82): truncated value with size 32 to match size of target (7)
+Warning (14284): Synthesized away the following node(s):
+    Warning (14285): Synthesized away the following RAM node(s):
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]"
+Warning (12241): 10 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13034): The following nodes have both tri-state and non-tri-state drivers
+    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[20]" and its non-tri-state driver.
+    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[14]" and its non-tri-state driver.
+Warning (13039): The following bidir pins have no drivers
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+Warning (13032): The following tri-state nodes are fed by constants
+    Warning (13033): The pin "GPIO_1[15]" is fed by VCC
+Info (13000): Registers with preset signals will power-up high
+Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
+Warning (13009): TRI or OPNDRN buffers permanently enabled
+    Warning (13010): Node "GPIO_1~synth"
+    Warning (13010): Node "GPIO_1~synth"
+    Warning (13010): Node "GPIO_1~synth"
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "DRAM_CKE" is stuck at VCC
+    Warning (13410): Pin "GPIO_1_CLKOUT[1]" is stuck at GND
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 41 registers lost all their fanouts during netlist optimizations.
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 8 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "GPIO_1_CLKIN[1]"
+    Warning (15610): No output dependent on input pin "SW[9]"
+    Warning (15610): No output dependent on input pin "SW[8]"
+    Warning (15610): No output dependent on input pin "SW[7]"
+    Warning (15610): No output dependent on input pin "SW[6]"
+    Warning (15610): No output dependent on input pin "SW[5]"
+    Warning (15610): No output dependent on input pin "SW[4]"
+    Warning (15610): No output dependent on input pin "SW[3]"
+Info (21057): Implemented 1806 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 16 input pins
+    Info (21059): Implemented 77 output pins
+    Info (21060): Implemented 48 bidirectional pins
+    Info (21061): Implemented 1596 logic cells
+    Info (21064): Implemented 68 RAM segments
+    Info (21065): Implemented 1 PLLs
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 119 warnings
+    Info: Peak virtual memory: 534 megabytes
+    Info: Processing ended: Mon Mar 17 10:02:21 2014
+    Info: Elapsed time: 00:00:08
+    Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.summary b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.summary
new file mode 100644
index 0000000..385ec7e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Mon Mar 17 10:02:21 2014
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
+Revision Name : DE0_D5M
+Top-level Entity Name : TOP_CAMERA
+Family : Cyclone III
+Total logic elements : 1,569
+    Total combinational functions : 1,198
+    Dedicated logic registers : 1,030
+Total registers : 1030
+Total pins : 141
+Total virtual pins : 0
+Total memory bits : 53,200
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 1
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pin b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pin
new file mode 100644
index 0000000..3d3a943
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		3.3V
+ --					Bank 2:		3.3V
+ --					Bank 3:		3.3V
+ --					Bank 4:		3.3V
+ --					Bank 5:		3.3V
+ --					Bank 6:		3.3V
+ --					Bank 7:		3.3V
+ --					Bank 8:		3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+CHIP  "DE0_D5M"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 3.3V    : 8         :                
+DRAM_ADDR[1]                 : A3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_BA_1                    : A4        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[4]                 : A5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[7]                 : A6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[11]                : A7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[8]                   : A8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[10]                  : A9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[13]                  : A10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+HEX1[0]                      : A13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[3]                      : A14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[6]                      : A15       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[1]                      : A16       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[4]                      : A17       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+HEX3[2]                      : A19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 3.3V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 3.3V    : 3         :                
+GPIO_1[16]                   : AA7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+GPIO_1[15]                   : AA9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GPIO_1_CLKIN[1]              : AA11      : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+GPIO_1[6]                    : AA17      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[5]                    : AA18      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[2]                    : AA19      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[0]                    : AA20      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+GPIO_1[17]                   : AB7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+GPIO_1[14]                   : AB9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GPIO_1_CLKIN[0]              : AB11      : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+GPIO_1[7]                    : AB17      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[4]                    : AB18      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[3]                    : AB19      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[1]                    : AB20      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : AB21      : power  :                   : 3.3V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+LEDG[9]                      : B1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[8]                      : B2        : output : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_ADDR[2]                 : B3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[10]                : B4        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_BA_0                    : B5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[6]                 : B6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[9]                 : B7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_UDQM                    : B8        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[9]                   : B9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[12]                  : B10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+HEX1[1]                      : B13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[4]                      : B14       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+HEX2[2]                      : B16       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[5]                      : B17       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[0]                      : B18       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[3]                      : B19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+LEDG[6]                      : C1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[7]                      : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_ADDR[3]                 : C3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[0]                 : C4        : output : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C5        : gnd    :                   :         :           :                
+DRAM_ADDR[5]                 : C6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[8]                 : C7        : output : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+DRAM_DQ[11]                  : C10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+HEX1[2]                      : C13       : output : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+HEX3[4]                      : C19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[9]                        : D2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 3.3V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 3.3V    : 8         :                
+DRAM_WE_N                    : D6        : output : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 3.3V    : 8         :                
+DRAM_DQ[0]                   : D10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : D11       : power  :                   : 3.3V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 3.3V    : 7         :                
+HEX2[0]                      : D15       : output : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : D16       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 3.3V    : 7         :                
+HEX3[5]                      : D19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+LEDG[5]                      : E1        : output : 3.3-V LVTTL       :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[7]                        : E3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[8]                        : E4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_CLK                     : E5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_CKE                     : E6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_LDQM                    : E7        : output : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : E8        : power  :                   : 3.3V    : 8         :                
+DRAM_DQ[3]                   : E9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[14]                  : E10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+HEX0[0]                      : E11       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+HEX1[5]                      : E14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[3]                      : E15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 3.3V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+KEY[2]                       : F1        : input  : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[4]                      : F2        : output : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 3.3V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+DRAM_RAS_N                   : F7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[7]                   : F8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[4]                   : F9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[15]                  : F10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+HEX0[1]                      : F11       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[5]                      : F12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[6]                      : F13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[6]                      : F14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[1]                      : F15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+KEY[1]                       : G3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[3]                        : G4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[4]                        : G5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+DRAM_CS_N                    : G7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_CAS_N                   : G8        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[5]                   : G9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[1]                   : G10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+HEX0[4]                      : G12       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+HEX3[6]                      : G15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 3.3V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+CLOCK_50                     : G21       : input  : 3.3-V LVTTL       :         : 6         : Y              
+GND+                         : G22       :        :                   :         : 6         :                
+LEDG[3]                      : H1        : output : 3.3-V LVTTL       :         : 1         : Y              
+KEY[0]                       : H2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 3.3V    : 1         :                
+SW[1]                        : H5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[2]                        : H6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[6]                        : H7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H8        : gnd    :                   :         :           :                
+DRAM_DQ[6]                   : H9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[2]                   : H10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+HEX0[2]                      : H12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[3]                      : H13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+VGA_R[1]                     : H17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+VGA_R[0]                     : H19       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[2]                     : H20       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[3]                     : H21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_G[0]                     : H22       : output : 3.3-V LVTTL       :         : 6         : Y              
+LEDG[0]                      : J1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[1]                      : J2        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[2]                      : J3        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+SW[0]                        : J6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[5]                        : J7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+VGA_G[1]                     : J17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 3.3V    : 6         :                
+VGA_G[3]                     : J21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[2]                     : J22       : output : 3.3-V LVTTL       :         : 6         : Y              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 3.3-V LVTTL       :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 3.3-V LVTTL       :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 3.3V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+VGA_G[2]                     : K17       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[3]                     : K18       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+VGA_B[1]                     : K21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[0]                     : K22       : output : 3.3-V LVTTL       :         : 6         : Y              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 3.3V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+VGA_HS                       : L21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_VS                       : L22       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 3.3V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 3.3V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 3.3V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+GPIO_1[22]                   : R11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[23]                   : R12       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+GPIO_1[19]                   : R14       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+GPIO_1_CLKOUT[0]             : R16       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+GPIO_1[27]                   : T9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[25]                   : T10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+GPIO_1[21]                   : T12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+GPIO_1[18]                   : T14       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[11]                   : T15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1_CLKOUT[1]             : T16       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 3.3V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 3.3V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+GPIO_1[29]                   : U8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[26]                   : U9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[24]                   : U10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+GPIO_1[20]                   : U12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+VGA_CLK                      : U14       : output : 3.3-V LVTTL       :         : 4         : N              
+GPIO_1[10]                   : U15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+GPIO_1[30]                   : V6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[31]                   : V7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+GPIO_1[13]                   : V15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 3.3V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 3.3V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 3.3V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 3.3V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+GPIO_1[12]                   : W15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : W16       : power  :                   : 3.3V    : 4         :                
+GPIO_1[9]                    : W17       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : W18       : power  :                   : 3.3V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+GPIO_1[28]                   : Y7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 3.3V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+GPIO_1[8]                    : Y17       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 3.3V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pof b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pof
new file mode 100644
index 0000000..77147af
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pof
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qpf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qpf
new file mode 100644
index 0000000..6eb86c4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qpf
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "7.2"
+DATE = "14:14:24  April 30, 2008"
+
+
+# Revisions
+
+PROJECT_REVISION = "DE0_D5M"
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf
new file mode 100644
index 0000000..15d8d33
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf
@@ -0,0 +1,557 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE0_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY TOP_CAMERA
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+
+
+
+
+
+
+
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+
+set_location_assignment PIN_AA11 -to GPIO_1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO_1_CLKIN[0]
+
+set_location_assignment PIN_T16 -to GPIO_1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO_1_CLKOUT[0]
+
+
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+
+
+
+
+set_location_assignment PIN_E11 -to HEX0[0]
+set_location_assignment PIN_F11 -to HEX0[1]
+set_location_assignment PIN_H12 -to HEX0[2]
+set_location_assignment PIN_H13 -to HEX0[3]
+set_location_assignment PIN_G12 -to HEX0[4]
+set_location_assignment PIN_F12 -to HEX0[5]
+set_location_assignment PIN_F13 -to HEX0[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+
+set_location_assignment PIN_A15 -to HEX1[6]
+set_location_assignment PIN_E14 -to HEX1[5]
+set_location_assignment PIN_B14 -to HEX1[4]
+set_location_assignment PIN_A14 -to HEX1[3]
+set_location_assignment PIN_C13 -to HEX1[2]
+set_location_assignment PIN_B13 -to HEX1[1]
+set_location_assignment PIN_A13 -to HEX1[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+
+set_location_assignment PIN_F14 -to HEX2[6]
+set_location_assignment PIN_B17 -to HEX2[5]
+set_location_assignment PIN_A17 -to HEX2[4]
+set_location_assignment PIN_E15 -to HEX2[3]
+set_location_assignment PIN_B16 -to HEX2[2]
+set_location_assignment PIN_A16 -to HEX2[1]
+set_location_assignment PIN_D15 -to HEX2[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+
+set_location_assignment PIN_G15 -to HEX3[6]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_C19 -to HEX3[4]
+set_location_assignment PIN_B19 -to HEX3[3]
+set_location_assignment PIN_A19 -to HEX3[2]
+set_location_assignment PIN_F15 -to HEX3[1]
+set_location_assignment PIN_B18 -to HEX3[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+
+set_location_assignment PIN_G21 -to CLOCK_50
+
+set_location_assignment PIN_R21 -to PS2_CLK
+set_location_assignment PIN_R22 -to PS2_DAT
+
+#set_location_assignment PIN_F14 -to UART_RXD
+#set_location_assignment PIN_G12 -to UART_TXD
+
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+set_location_assignment PIN_B12 -to CLOCK_50_2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/uart_crtl.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE0_D5M.v
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name SDC_FILE DE0_D5M.sdc
+
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+set_global_assignment -name BDF_FILE TOP_CAMERA.bdf
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_1_CLKIN[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_1_CLKOUT[0]
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf.bak
new file mode 100644
index 0000000..cc80243
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf.bak
@@ -0,0 +1,586 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE0_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY DE0_D5M
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_0[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_0[16]
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+
+
+
+
+
+
+
+set_location_assignment PIN_V7 -to GPIO_1[35]
+set_location_assignment PIN_V6 -to GPIO_1[34]
+set_location_assignment PIN_U8 -to GPIO_1[33]
+set_location_assignment PIN_Y7 -to GPIO_1[32]
+set_location_assignment PIN_T9 -to GPIO_1[31]
+set_location_assignment PIN_U9 -to GPIO_1[30]
+set_location_assignment PIN_T10 -to GPIO_1[29]
+set_location_assignment PIN_U10 -to GPIO_1[28]
+set_location_assignment PIN_R12 -to GPIO_1[27]
+set_location_assignment PIN_R11 -to GPIO_1[26]
+set_location_assignment PIN_T12 -to GPIO_1[25]
+set_location_assignment PIN_U12 -to GPIO_1[24]
+set_location_assignment PIN_R14 -to GPIO_1[23]
+set_location_assignment PIN_T14 -to GPIO_1[22]
+set_location_assignment PIN_AB7 -to GPIO_1[21]
+set_location_assignment PIN_AA7 -to GPIO_1[20]
+set_location_assignment PIN_AA9 -to GPIO_1[19]
+set_location_assignment PIN_T16 -to GPIO_1[18]
+set_location_assignment PIN_AB9 -to GPIO_1[17]
+set_location_assignment PIN_R16 -to GPIO_1[16]
+set_location_assignment PIN_V15 -to GPIO_1[15]
+set_location_assignment PIN_W15 -to GPIO_1[14]
+set_location_assignment PIN_T15 -to GPIO_1[13]
+set_location_assignment PIN_U15 -to GPIO_1[12]
+set_location_assignment PIN_W17 -to GPIO_1[11]
+set_location_assignment PIN_Y17 -to GPIO_1[10]
+set_location_assignment PIN_AB17 -to GPIO_1[9]
+set_location_assignment PIN_AA17 -to GPIO_1[8]
+set_location_assignment PIN_AA18 -to GPIO_1[7]
+set_location_assignment PIN_AB18 -to GPIO_1[6]
+set_location_assignment PIN_AB19 -to GPIO_1[5]
+set_location_assignment PIN_AA19 -to GPIO_1[4]
+set_location_assignment PIN_AB20 -to GPIO_1[3]
+set_location_assignment PIN_AA11 -to GPIO_1[2]
+set_location_assignment PIN_AA20 -to GPIO_1[1]
+set_location_assignment PIN_AB11 -to GPIO_1[0]
+
+
+
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+
+
+
+
+set_location_assignment PIN_E11 -to HEX0_D[0]
+set_location_assignment PIN_F11 -to HEX0_D[1]
+set_location_assignment PIN_H12 -to HEX0_D[2]
+set_location_assignment PIN_H13 -to HEX0_D[3]
+set_location_assignment PIN_G12 -to HEX0_D[4]
+set_location_assignment PIN_F12 -to HEX0_D[5]
+set_location_assignment PIN_F13 -to HEX0_D[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+
+set_location_assignment PIN_A15 -to HEX1_D[6]
+set_location_assignment PIN_E14 -to HEX1_D[5]
+set_location_assignment PIN_B14 -to HEX1_D[4]
+set_location_assignment PIN_A14 -to HEX1_D[3]
+set_location_assignment PIN_C13 -to HEX1_D[2]
+set_location_assignment PIN_B13 -to HEX1_D[1]
+set_location_assignment PIN_A13 -to HEX1_D[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+
+set_location_assignment PIN_F14 -to HEX2_D[6]
+set_location_assignment PIN_B17 -to HEX2_D[5]
+set_location_assignment PIN_A17 -to HEX2_D[4]
+set_location_assignment PIN_E15 -to HEX2_D[3]
+set_location_assignment PIN_B16 -to HEX2_D[2]
+set_location_assignment PIN_A16 -to HEX2_D[1]
+set_location_assignment PIN_D15 -to HEX2_D[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+
+set_location_assignment PIN_G15 -to HEX3_D[6]
+set_location_assignment PIN_D19 -to HEX3_D[5]
+set_location_assignment PIN_C19 -to HEX3_D[4]
+set_location_assignment PIN_B19 -to HEX3_D[3]
+set_location_assignment PIN_A19 -to HEX3_D[2]
+set_location_assignment PIN_F15 -to HEX3_D[1]
+set_location_assignment PIN_B18 -to HEX3_D[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+
+set_location_assignment PIN_G21 -to CLOCK_50
+
+set_location_assignment PIN_R21 -to PS2_CLK
+set_location_assignment PIN_R22 -to PS2_DAT
+
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+set_location_assignment PIN_B12 -to CLOCK_50_2
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+
+
+
+
+
+
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+
+
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+
+
+
+
+
+
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/uart_crtl.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE0_D5M.v
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name SDC_FILE DE0_D5M.sdc
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qws b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qws
new file mode 100644
index 0000000..91d2f2b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qws
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sdc b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sdc
new file mode 100644
index 0000000..6a9d418
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sdc
@@ -0,0 +1,41 @@
+#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.                           
+#
+# Version 10.0 Build 218 06/27/2010 SJ Full Version
+#
+#************************************************************
+
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "CLOCK_50" -period 20ns [get_ports {CLOCK_50}] -waveform {0.000ns 10.000ns}
+
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+#derive_clock_uncertainty
+# Not supported for family Cyclone II
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sof b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sof
new file mode 100644
index 0000000..76fca82
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sof
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.rpt
new file mode 100644
index 0000000..760d753
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.rpt
@@ -0,0 +1,10106 @@
+TimeQuest Timing Analyzer report for DE0_D5M
+Mon Mar 17 10:02:50 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. SDC File List
+  5. Clocks
+  6. Slow 1200mV 85C Model Fmax Summary
+  7. Timing Closure Recommendations
+  8. Slow 1200mV 85C Model Setup Summary
+  9. Slow 1200mV 85C Model Hold Summary
+ 10. Slow 1200mV 85C Model Recovery Summary
+ 11. Slow 1200mV 85C Model Removal Summary
+ 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 13. Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 14. Slow 1200mV 85C Model Setup: 'CLOCK_50'
+ 15. Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 16. Slow 1200mV 85C Model Hold: 'CLOCK_50'
+ 17. Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 18. Slow 1200mV 85C Model Recovery: 'CLOCK_50'
+ 19. Slow 1200mV 85C Model Removal: 'CLOCK_50'
+ 20. Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 21. Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 22. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
+ 23. Setup Times
+ 24. Hold Times
+ 25. Clock to Output Times
+ 26. Minimum Clock to Output Times
+ 27. Output Enable Times
+ 28. Minimum Output Enable Times
+ 29. Output Disable Times
+ 30. Minimum Output Disable Times
+ 31. MTBF Summary
+ 32. Synchronizer Summary
+ 33. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+ 34. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+ 35. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+ 36. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+ 37. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+ 38. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+ 39. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+ 40. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+ 41. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+ 42. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+ 43. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+ 44. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+ 45. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+ 46. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+ 47. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+ 48. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+ 49. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+ 50. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+ 51. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+ 52. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+ 53. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+ 54. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+ 55. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+ 56. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+ 57. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+ 58. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+ 59. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+ 60. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+ 61. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+ 62. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+ 63. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+ 64. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+ 65. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+ 66. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+ 67. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+ 68. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+ 69. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+ 70. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+ 71. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+ 72. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+ 73. Slow 1200mV 0C Model Fmax Summary
+ 74. Slow 1200mV 0C Model Setup Summary
+ 75. Slow 1200mV 0C Model Hold Summary
+ 76. Slow 1200mV 0C Model Recovery Summary
+ 77. Slow 1200mV 0C Model Removal Summary
+ 78. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 79. Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 80. Slow 1200mV 0C Model Setup: 'CLOCK_50'
+ 81. Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 82. Slow 1200mV 0C Model Hold: 'CLOCK_50'
+ 83. Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 84. Slow 1200mV 0C Model Recovery: 'CLOCK_50'
+ 85. Slow 1200mV 0C Model Removal: 'CLOCK_50'
+ 86. Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 87. Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 88. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+ 89. Setup Times
+ 90. Hold Times
+ 91. Clock to Output Times
+ 92. Minimum Clock to Output Times
+ 93. Output Enable Times
+ 94. Minimum Output Enable Times
+ 95. Output Disable Times
+ 96. Minimum Output Disable Times
+ 97. MTBF Summary
+ 98. Synchronizer Summary
+ 99. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+100. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+101. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+102. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+103. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+104. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+105. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+106. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+107. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+108. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+109. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+110. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+111. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+112. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+113. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+114. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+115. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+116. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+117. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+118. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+119. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+120. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+121. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+122. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+123. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+124. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+125. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+126. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+127. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+128. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+129. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+130. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+131. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+132. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+133. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+134. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+135. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+136. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+137. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+138. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+139. Fast 1200mV 0C Model Setup Summary
+140. Fast 1200mV 0C Model Hold Summary
+141. Fast 1200mV 0C Model Recovery Summary
+142. Fast 1200mV 0C Model Removal Summary
+143. Fast 1200mV 0C Model Minimum Pulse Width Summary
+144. Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+145. Fast 1200mV 0C Model Setup: 'CLOCK_50'
+146. Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+147. Fast 1200mV 0C Model Hold: 'CLOCK_50'
+148. Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+149. Fast 1200mV 0C Model Recovery: 'CLOCK_50'
+150. Fast 1200mV 0C Model Removal: 'CLOCK_50'
+151. Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+152. Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+153. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+154. Setup Times
+155. Hold Times
+156. Clock to Output Times
+157. Minimum Clock to Output Times
+158. Output Enable Times
+159. Minimum Output Enable Times
+160. Output Disable Times
+161. Minimum Output Disable Times
+162. MTBF Summary
+163. Synchronizer Summary
+164. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+165. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+166. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+167. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+168. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+169. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+170. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+171. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+172. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+173. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+174. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+175. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+176. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+177. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+178. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+179. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+180. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+181. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+182. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+183. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+184. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+185. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+186. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+187. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+188. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+189. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+190. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+191. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+192. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+193. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+194. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+195. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+196. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+197. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+198. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+199. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+200. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+201. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+202. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+203. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+204. Multicorner Timing Analysis Summary
+205. Setup Times
+206. Hold Times
+207. Clock to Output Times
+208. Minimum Clock to Output Times
+209. Board Trace Model Assignments
+210. Input Transition Times
+211. Slow Corner Signal Integrity Metrics
+212. Fast Corner Signal Integrity Metrics
+213. Setup Transfers
+214. Hold Transfers
+215. Recovery Transfers
+216. Removal Transfers
+217. Report TCCS
+218. Report RSKM
+219. Unconstrained Paths
+220. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++--------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                        ;
++--------------------+-----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name      ; DE0_D5M                                             ;
+; Device Family      ; Cyclone III                                         ;
+; Device Name        ; EP3C16F484C6                                        ;
+; Timing Models      ; Final                                               ;
+; Delay Model        ; Combined                                            ;
+; Rise/Fall Delays   ; Enabled                                             ;
++--------------------+-----------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------+
+; SDC File List                                     ;
++---------------+--------+--------------------------+
+; SDC File Path ; Status ; Read at                  ;
++---------------+--------+--------------------------+
+; DE0_D5M.sdc   ; OK     ; Mon Mar 17 10:02:47 2014 ;
++---------------+--------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                                                                                                                                           ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+; Clock Name                                          ; Type      ; Period ; Frequency ; Rise   ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase  ; Offset ; Edge List ; Edge Shift ; Inverted ; Master   ; Source                                                ; Targets                                                 ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+; CLOCK_50                                            ; Base      ; 20.000 ; 50.0 MHz  ; 0.000  ; 10.000 ;            ;           ;             ;        ;        ;           ;            ;          ;          ;                                                       ; { CLOCK_50 }                                            ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.000  ; 125.0 MHz ; 0.000  ; 4.000  ; 50.00      ; 2         ; 5           ;        ;        ;           ;            ; false    ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[0] } ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 8.000  ; 125.0 MHz ; -2.600 ; 1.400  ; 50.00      ; 2         ; 5           ; -117.0 ;        ;           ;            ; false    ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[1] } ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                                        ;
++------------+-----------------+-----------------------------------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name                                          ; Note ;
++------------+-----------------+-----------------------------------------------------+------+
+; 174.7 MHz  ; 174.7 MHz       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;      ;
+; 207.04 MHz ; 207.04 MHz      ; CLOCK_50                                            ;      ;
++------------+-----------------+-----------------------------------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup Summary                                          ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.454 ; -22.246       ;
+; CLOCK_50                                            ; 15.170 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold Summary                                          ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.214 ; 0.000         ;
+; CLOCK_50                                            ; 0.358 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery Summary                                       ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -1.497 ; -338.162      ;
+; CLOCK_50                                            ; 14.980 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal Summary                                       ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 1.616 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.132 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.736 ; 0.000         ;
+; CLOCK_50                                            ; 9.580 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.454 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.208     ; 2.261      ;
+; -0.454 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.208     ; 2.261      ;
+; -0.454 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.208     ; 2.261      ;
+; -0.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.250      ;
+; -0.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.178     ; 2.229      ;
+; -0.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.178     ; 2.229      ;
+; -0.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.178     ; 2.229      ;
+; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.205      ;
+; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.205      ;
+; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.205      ;
+; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.205      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.167      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.167      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.167      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; 2.276  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.086     ; 5.653      ;
+; 2.320  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.607      ;
+; 2.320  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.607      ;
+; 2.320  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.607      ;
+; 2.320  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.607      ;
+; 2.340  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.278      ; 5.953      ;
+; 2.346  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.581      ;
+; 2.346  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.581      ;
+; 2.346  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.581      ;
+; 2.360  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.086     ; 5.569      ;
+; 2.365  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.086     ; 5.564      ;
+; 2.384  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.276      ; 5.907      ;
+; 2.384  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.276      ; 5.907      ;
+; 2.384  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.276      ; 5.907      ;
+; 2.384  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.276      ; 5.907      ;
+; 2.404  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.523      ;
+; 2.404  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.523      ;
+; 2.404  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.523      ;
+; 2.404  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.523      ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'CLOCK_50'                                                                                                                                          ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 15.170 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.782      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.384 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.568      ;
+; 15.400 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.567      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.409 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.558      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.474 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]          ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.478      ;
+; 15.477 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.475      ;
+; 15.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.462      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.214 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.428      ; 0.799      ;
+; 0.230 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.428      ; 0.815      ;
+; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.428      ; 0.910      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.428      ; 0.911      ;
+; 0.334 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.381      ; 0.902      ;
+; 0.343 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.380      ; 0.910      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.380      ; 0.912      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.591      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.592      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.592      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.594      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.425      ; 0.943      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.425      ; 0.943      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.580      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.595      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.580      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.580      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.595      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.595      ;
+; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.591      ;
+; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.590      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[18]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.591      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.608      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[9]                                                                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[3]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'CLOCK_50'                                                                                                                                                      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.361 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
+; 0.381 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.600      ;
+; 0.382 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.385 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.580      ;
+; 0.390 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.609      ;
+; 0.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.609      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.736      ;
+; 0.524 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.743      ;
+; 0.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.769      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.775      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.775      ;
+; 0.557 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.775      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.558 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.776      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.776      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.559 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.778      ;
+; 0.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.777      ;
+; 0.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.777      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.778      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.779      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.781      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.781      ;
+; 0.563 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.781      ;
+; 0.568 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.788      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.788      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.790      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.790      ;
+; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.792      ;
+; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.793      ;
+; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.793      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.792      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.793      ;
+; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.792      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.794      ;
+; 0.580 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.799      ;
+; 0.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.800      ;
+; 0.585 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.804      ;
+; 0.586 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.805      ;
+; 0.606 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.825      ;
+; 0.700 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.919      ;
+; 0.702 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.921      ;
+; 0.710 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.929      ;
+; 0.825 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.043      ;
+; 0.831 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.050      ;
+; 0.832 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.051      ;
+; 0.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.051      ;
+; 0.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.051      ;
+; 0.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.050      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.285     ; 3.200      ;
+; -1.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.277     ; 3.204      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.546     ; 2.792      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.546     ; 2.792      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'CLOCK_50'                                                                                                                                    ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 14.980 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.066      ; 5.101      ;
+; 14.989 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.066      ; 5.092      ;
+; 15.085 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.066      ; 4.996      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.144 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.926      ;
+; 15.223 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.066      ; 4.858      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.287 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.783      ;
+; 15.290 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.780      ;
+; 15.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.773      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.384 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.686      ;
+; 15.392 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.678      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'CLOCK_50'                                                                                                                                                   ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.228      ; 2.081      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.838 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.228      ; 2.223      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.514 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.238      ; 2.909      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.807 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 3.019      ;
+; 2.807 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 3.019      ;
+; 2.807 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 3.019      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 4.132 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.681     ; 2.608      ;
+; 4.132 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.681     ; 2.608      ;
+; 4.132 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.681     ; 2.608      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.676     ; 2.614      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.676     ; 2.614      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.676     ; 2.614      ;
+; 4.135 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.679     ; 2.613      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.614      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.614      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.614      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.687     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.615      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.615      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                      ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                  ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.736 ; 3.966        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0  ;
+; 3.736 ; 3.966        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0   ;
+; 3.736 ; 3.966        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg        ;
+; 3.737 ; 3.967        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0  ;
+; 3.737 ; 3.967        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0   ;
+; 3.737 ; 3.967        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg        ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                           ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[1]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|CAS_N                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|CS_N[0]                                                                                                                             ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|PM_STOP                                                                                                                             ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[11]                                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[1]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[8]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CAS_N                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CS_N[0]                                                                                                            ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                             ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial                                                                                                         ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                            ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[12]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[14]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[20]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[22]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[9]                                                                                                 ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                                                                                                                              ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]                                                                                                                              ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|DQM[0]                                                                                                                              ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                              ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[2]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[5]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[2]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[5]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[6]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[7]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                     ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                     ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                     ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'                                                                                           ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                        ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; 9.580 ; 9.764        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]         ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1]         ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]         ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]         ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]                  ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]                  ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]             ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                           ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                            ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                            ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                            ;
+; 9.632 ; 9.816        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                  ;
+; 9.740 ; 9.740        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0]           ;
+; 9.740 ; 9.740        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1]           ;
+; 9.740 ; 9.740        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|observablevcoout ;
+; 9.742 ; 9.742        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|rClk[0]|clk                                              ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 4.050 ; 4.731 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 4.050 ; 4.731 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 3.252 ; 3.792 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 4.454 ; 5.044 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 4.454 ; 5.044 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 4.228 ; 4.804 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 4.088 ; 4.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.985 ; 4.485 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.971 ; 4.476 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.720 ; 4.223 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.722 ; 4.235 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.708 ; 4.219 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.516 ; -2.017 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.569 ; -2.104 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.516 ; -2.017 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -3.030 ; -3.522 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -3.758 ; -4.336 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -3.529 ; -4.083 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -3.407 ; -3.896 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -3.296 ; -3.778 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -3.282 ; -3.768 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -3.041 ; -3.526 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -3.044 ; -3.537 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -3.030 ; -3.522 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 7.004  ; 7.069  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 7.004  ; 7.069  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.882  ; 6.755  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.954  ; 4.908  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.954  ; 4.908  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.291  ; 5.346  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.733  ; 3.645  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.700  ; 3.596  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.732  ; 3.645  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.589  ; 3.523  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.733  ; 3.638  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.576  ; 3.509  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.527  ; 3.439  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.575  ; 3.472  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.357  ; 3.274  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.532  ; 3.433  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.594  ; 3.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.515  ; 3.425  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.381  ; 3.299  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.540  ; 3.449  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.624  ; 3.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.569  ; 3.489  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.685  ; 3.582  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.764  ; 7.387  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.853  ; 5.686  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.923  ; 5.772  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.841  ; 5.703  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.764  ; 7.387  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.747  ; 5.603  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.667  ; 5.552  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 6.210  ; 6.073  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.690  ; 5.589  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.631  ; 5.599  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 5.178  ; 5.147  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.631  ; 5.557  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.436  ; 5.269  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 5.663  ; 5.519  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.466  ; 5.409  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 6.063  ; 5.900  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.624  ; 5.492  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.597  ; 3.540  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.733  ; 3.650  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.431  ; 3.340  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.576  ; 5.291  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.575 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.703 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.707  ; 6.581  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.825  ; 6.882  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.707  ; 6.581  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.856  ; 4.807  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.856  ; 4.807  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.175  ; 5.233  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.922  ; 2.838  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.251  ; 3.147  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.283  ; 3.195  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.146  ; 3.077  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.283  ; 3.187  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.133  ; 3.064  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.085  ; 2.996  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.132  ; 3.029  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 2.922  ; 2.838  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.090  ; 2.989  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.150  ; 3.048  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.074  ; 2.982  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.945  ; 2.861  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.098  ; 3.006  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.179  ; 3.087  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.125  ; 3.044  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.236  ; 3.132  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 3.781  ; 3.692  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 4.426  ; 4.325  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 4.302  ; 4.232  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 4.235  ; 4.172  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 6.143  ; 5.835  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 4.933  ; 4.852  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 4.418  ; 4.365  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 4.586  ; 4.522  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 4.454  ; 4.407  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 4.187  ; 4.101  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 4.369  ; 4.307  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 4.773  ; 4.673  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 4.165  ; 4.074  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 3.781  ; 3.692  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.341  ; 4.260  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 4.381  ; 4.264  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 4.156  ; 4.070  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.153  ; 3.092  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.282  ; 3.197  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 2.994  ; 2.900  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.132  ; 4.844  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.948 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.075 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.158 ; 3.158 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.158 ; 3.158 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.664 ; 3.664 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.674 ; 3.674 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.461 ; 3.461 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.863 ; 3.863 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.664 ; 3.664 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.883 ; 3.883 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.847 ; 3.847 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.170 ; 3.170 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.170 ; 3.170 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.178 ; 3.178 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.160 ; 3.160 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.168 ; 3.168 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.178 ; 3.178 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.158 ; 3.158 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.863 ; 3.863 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.449 ; 2.449 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.449 ; 2.449 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.935 ; 2.935 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.945 ; 2.945 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.739 ; 2.739 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.126 ; 3.126 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.935 ; 2.935 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.146 ; 3.146 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.111 ; 3.111 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.461 ; 2.461 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.461 ; 2.461 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.469 ; 2.469 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.451 ; 2.451 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.459 ; 2.459 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.469 ; 2.469 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.449 ; 2.449 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.126 ; 3.126 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.085     ; 3.187     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.085     ; 3.187     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.605     ; 3.707     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.615     ; 3.717     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.406     ; 3.508     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.802     ; 3.904     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.605     ; 3.707     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.822     ; 3.924     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.796     ; 3.898     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.104     ; 3.206     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.104     ; 3.206     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.105     ; 3.207     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.094     ; 3.196     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.095     ; 3.197     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.105     ; 3.207     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.085     ; 3.187     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.802     ; 3.904     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.477     ; 2.573     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.477     ; 2.573     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.976     ; 3.072     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.986     ; 3.082     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.785     ; 2.881     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.165     ; 3.261     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.976     ; 3.072     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.185     ; 3.281     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.159     ; 3.255     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.496     ; 2.592     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.496     ; 2.592     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.497     ; 2.593     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.486     ; 2.582     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.487     ; 2.583     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.497     ; 2.593     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.477     ; 2.573     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.165     ; 3.261     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 11.051 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.051                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.249        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 3.802        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.254                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 6.970        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.284        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.326                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.074        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.397                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.292        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.434                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 6.899        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.535        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.441                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.336        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.471                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.219        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.502                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.249        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 4.253        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.552                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 6.898        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.654        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.577                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.107        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.470        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.605                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.500        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.628                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.103        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.525        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.632                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.250        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.382        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.636                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.531        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.670                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.253        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.417        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.684                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.106        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.578        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.709                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 6.901        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.808        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.717                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 6.902        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 4.815        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.748                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.109        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.639        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.765                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.513        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.790                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 6.773        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 5.017        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.795                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.104        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.691        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.838                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 6.985        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 4.853        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.840                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 6.984        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 4.856        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.862                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 6.905        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.957        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.886                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.108        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.778        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.896                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.645        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.906                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 6.662        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.244        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.918                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.667        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.991                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 6.902        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.089        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.005                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.265        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.740        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.055                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.250        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.805        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.215                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.964        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.246                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.253        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 4.993        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.358                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.254        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.104        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.397                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.292        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.525                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.274        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.641                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.253        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.388        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.733                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.267        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.466        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.873                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.126        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.747        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++-------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                                         ;
++------------+-----------------+-----------------------------------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name                                          ; Note ;
++------------+-----------------+-----------------------------------------------------+------+
+; 193.87 MHz ; 193.87 MHz      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;      ;
+; 231.32 MHz ; 231.32 MHz      ; CLOCK_50                                            ;      ;
++------------+-----------------+-----------------------------------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup Summary                                           ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.053  ; 0.000         ;
+; CLOCK_50                                            ; 15.677 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold Summary                                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.190 ; 0.000         ;
+; CLOCK_50                                            ; 0.312 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery Summary                                        ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.843 ; -150.984      ;
+; CLOCK_50                                            ; 15.539 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal Summary                                        ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 1.477 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.638 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary                            ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.741 ; 0.000         ;
+; CLOCK_50                                            ; 9.561 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 2.054      ;
+; 0.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 2.054      ;
+; 0.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 2.054      ;
+; 0.080 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.893     ; 2.042      ;
+; 0.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 2.026      ;
+; 0.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 2.026      ;
+; 0.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 2.026      ;
+; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 2.004      ;
+; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 2.004      ;
+; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 2.004      ;
+; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 2.004      ;
+; 0.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.960      ;
+; 0.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.960      ;
+; 0.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.960      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 2.842 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.076     ; 5.097      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.055      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.055      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.055      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.055      ;
+; 2.898 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.034      ;
+; 2.898 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.034      ;
+; 2.898 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.034      ;
+; 2.914 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.076     ; 5.025      ;
+; 2.919 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.076     ; 5.020      ;
+; 2.931 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.256      ; 5.340      ;
+; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.983      ;
+; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.983      ;
+; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.983      ;
+; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.983      ;
+; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.978      ;
+; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.978      ;
+; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.978      ;
+; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.978      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                           ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 15.677 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.285      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.875 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.087      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.910 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.065      ;
+; 15.919 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.056      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.951 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.011      ;
+; 15.952 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]          ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.010      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.999 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.976      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.190 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.383      ; 0.717      ;
+; 0.205 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.383      ; 0.732      ;
+; 0.295 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.383      ; 0.822      ;
+; 0.296 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.383      ; 0.823      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.301 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 0.530      ;
+; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.519      ;
+; 0.321 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.519      ;
+; 0.321 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.519      ;
+; 0.324 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.535      ;
+; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.537      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.387      ; 0.857      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.387      ; 0.857      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.537      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.538      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.538      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.538      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.539      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.539      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.540      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.540      ;
+; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.341      ; 0.841      ;
+; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.529      ;
+; 0.332 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.543      ;
+; 0.336 ; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|WRITEA                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.535      ;
+; 0.337 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.536      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.340      ; 0.847      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 0.548      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.537      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[18]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.537      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.537      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.537      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[3]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                       ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.320 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.519      ;
+; 0.333 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.341 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.519      ;
+; 0.346 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.545      ;
+; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.546      ;
+; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.546      ;
+; 0.466 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.665      ;
+; 0.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.671      ;
+; 0.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.694      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.699      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.700      ;
+; 0.502 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.700      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.701      ;
+; 0.503 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.701      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.703      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.702      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.702      ;
+; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.703      ;
+; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.703      ;
+; 0.505 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.703      ;
+; 0.506 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.705      ;
+; 0.506 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.704      ;
+; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.514 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.712      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.712      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.714      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.714      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.714      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.518 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.716      ;
+; 0.518 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.716      ;
+; 0.521 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.719      ;
+; 0.525 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.724      ;
+; 0.525 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.723      ;
+; 0.526 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.725      ;
+; 0.540 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.739      ;
+; 0.638 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.837      ;
+; 0.639 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.838      ;
+; 0.640 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.839      ;
+; 0.741 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.939      ;
+; 0.744 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.943      ;
+; 0.744 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.942      ;
+; 0.744 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.942      ;
+; 0.745 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.944      ;
+; 0.745 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.944      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.982     ; 2.857      ;
+; -0.796 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.860      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.685 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.497      ;
+; -0.685 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.497      ;
+; -0.685 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.497      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                     ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 15.539 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.082      ; 4.558      ;
+; 15.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.082      ; 4.549      ;
+; 15.628 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.082      ; 4.469      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.396      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.755 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.082      ; 4.342      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.270      ;
+; 15.818 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.267      ;
+; 15.824 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.261      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.190      ;
+; 15.902 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.183      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                    ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.534 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.222      ; 1.900      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.632 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.222      ; 1.998      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.262 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.235      ; 2.641      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.721      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.721      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.721      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.721      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.438     ; 2.344      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.438     ; 2.344      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.438     ; 2.344      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.338      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.338      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.338      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.443     ; 2.342      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.343      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.343      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.343      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.345      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.450     ; 2.343      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                         ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg          ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg          ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]                                                                                                                          ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]                                                                                                                          ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_RD                                                                                                                                ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_WR                                                                                                                                ;
+; 3.744 ; 3.974        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0     ;
+; 3.744 ; 3.974        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0     ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16]                                                                                                  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]                                                                                                                            ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                                                                                                                            ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                                                                                                                   ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0]                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[2]                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[5]                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                            ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                        ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; 9.561 ; 9.745        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                          ;
+; 9.585 ; 9.769        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                           ;
+; 9.585 ; 9.769        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                            ;
+; 9.585 ; 9.769        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                            ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]         ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1]         ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]         ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]         ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]             ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                            ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                           ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                  ;
+; 9.713 ; 9.713        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0]           ;
+; 9.713 ; 9.713        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1]           ;
+; 9.713 ; 9.713        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|observablevcoout ;
+; 9.721 ; 9.721        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|rClk[0]|clk                                              ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 3.589 ; 4.163 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 3.589 ; 4.163 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 2.854 ; 3.325 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.848 ; 4.345 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.848 ; 4.345 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.647 ; 4.124 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.508 ; 3.941 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.418 ; 3.842 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.402 ; 3.831 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.177 ; 3.607 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.182 ; 3.617 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.163 ; 3.604 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.293 ; -1.708 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.317 ; -1.789 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.293 ; -1.708 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -2.565 ; -2.993 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -3.235 ; -3.721 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -3.030 ; -3.492 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -2.908 ; -3.334 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -2.811 ; -3.222 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -2.795 ; -3.211 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -2.579 ; -2.996 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -2.584 ; -3.006 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -2.565 ; -2.993 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.617  ; 6.571  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.617  ; 6.571  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.491  ; 6.343  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.764  ; 4.656  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.764  ; 4.656  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.013  ; 5.130  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.730  ; 3.594  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.702  ; 3.557  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.727  ; 3.594  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.587  ; 3.487  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.730  ; 3.586  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.574  ; 3.450  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.533  ; 3.425  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.580  ; 3.438  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.373  ; 3.272  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.536  ; 3.389  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.591  ; 3.458  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.526  ; 3.393  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.389  ; 3.273  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.546  ; 3.427  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.618  ; 3.475  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.558  ; 3.446  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.685  ; 3.523  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.526  ; 7.148  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.603  ; 5.452  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.676  ; 5.541  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.607  ; 5.466  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.526  ; 7.148  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.522  ; 5.349  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.454  ; 5.296  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 5.944  ; 5.827  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.487  ; 5.303  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.446  ; 5.300  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 5.017  ; 4.898  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.452  ; 5.289  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.233  ; 5.055  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 5.444  ; 5.305  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.296  ; 5.162  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 5.806  ; 5.636  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.414  ; 5.226  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.587  ; 3.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.721  ; 3.601  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.442  ; 3.301  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.583  ; 5.252  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.448 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.595 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.336  ; 6.187  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.455  ; 6.406  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.336  ; 6.187  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.676  ; 4.567  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.676  ; 4.567  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 4.910  ; 5.026  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.989  ; 2.887  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.304  ; 3.159  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.329  ; 3.197  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.194  ; 3.093  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.330  ; 3.187  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.182  ; 3.058  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.141  ; 3.032  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.187  ; 3.046  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 2.989  ; 2.887  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.144  ; 2.999  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.198  ; 3.065  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.135  ; 3.003  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.004  ; 2.888  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.155  ; 3.036  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.225  ; 3.082  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.166  ; 3.053  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.286  ; 3.126  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 3.770  ; 3.622  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 4.360  ; 4.187  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 4.249  ; 4.128  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 4.187  ; 4.056  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 6.096  ; 5.728  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 4.828  ; 4.689  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 4.355  ; 4.245  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 4.512  ; 4.404  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 4.402  ; 4.261  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 4.140  ; 3.977  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 4.300  ; 4.168  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 4.675  ; 4.504  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 4.112  ; 3.961  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 3.770  ; 3.622  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.276  ; 4.132  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 4.316  ; 4.129  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 4.112  ; 3.947  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.193  ; 3.098  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.321  ; 3.201  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.055  ; 2.915  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.190  ; 4.858  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.777 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.922 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.119 ; 3.106 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.121 ; 3.108 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.591 ; 3.578 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.601 ; 3.588 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.404 ; 3.391 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.777 ; 3.764 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.591 ; 3.578 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.797 ; 3.784 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.766 ; 3.753 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.129 ; 3.116 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.129 ; 3.116 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.141 ; 3.128 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.119 ; 3.106 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.131 ; 3.118 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.141 ; 3.128 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.121 ; 3.108 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.777 ; 3.764 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.251 ; 2.251 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.252 ; 2.252 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.704 ; 2.704 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.714 ; 2.714 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.525 ; 2.525 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.882 ; 2.882 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.704 ; 2.704 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.902 ; 2.902 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.872 ; 2.872 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.261 ; 2.261 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.261 ; 2.261 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.272 ; 2.272 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.251 ; 2.251 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.262 ; 2.262 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.272 ; 2.272 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.252 ; 2.252 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.882 ; 2.882 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.126     ; 3.126     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.126     ; 3.126     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.591     ; 3.591     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.601     ; 3.601     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.413     ; 3.413     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.769     ; 3.769     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.591     ; 3.591     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.789     ; 3.789     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.763     ; 3.763     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.140     ; 3.140     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.140     ; 3.140     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.146     ; 3.146     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.130     ; 3.130     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.136     ; 3.136     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.146     ; 3.146     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.126     ; 3.126     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.769     ; 3.769     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.257     ; 2.445     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.257     ; 2.445     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.704     ; 2.892     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.714     ; 2.902     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.533     ; 2.721     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.875     ; 3.063     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.704     ; 2.892     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.895     ; 3.083     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.869     ; 3.057     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.272     ; 2.460     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.272     ; 2.460     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.277     ; 2.465     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.262     ; 2.450     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.267     ; 2.455     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.277     ; 2.465     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.257     ; 2.445     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.875     ; 3.063     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 11.581 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.581                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.335        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 4.246        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.772                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.080        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.692        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.831                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.338        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.493        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.874                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.676        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.896                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.022        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.874        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.906                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.708        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.975                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.335        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 4.640        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.978                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.021        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.957        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.982                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.643        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.986                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.199        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.787        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.061                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.863        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.083                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.196        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.887        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.090                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.892        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.119                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.338        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.781        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.133                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.935        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.134                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.018        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.116        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.135                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.019        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.116        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.148                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.809        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.187                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.201        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.986        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.217                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.878        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.247                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.197        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.050        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.261                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 6.920        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 5.341        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.263                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.022        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 5.241        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.279                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.100        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.179        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.286                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.200        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 5.086        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.291                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.097        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.194        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.324                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 6.808        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.516        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.345                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 5.008        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.347                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 5.010        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.358                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.019        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.339        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.445                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.350        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 5.095        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.483                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.146        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.587                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 5.250        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.646                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.307        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.740                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.340        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.400        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.768                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.570        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.901                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.564        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.982                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.643        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.070                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.352        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.718        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.198                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.222        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.976        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup Summary                                           ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 1.424  ; 0.000         ;
+; CLOCK_50                                            ; 17.244 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold Summary                                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.116 ; 0.000         ;
+; CLOCK_50                                            ; 0.187 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery Summary                                        ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.773  ; 0.000         ;
+; CLOCK_50                                            ; 17.090 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal Summary                                        ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 0.904 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 2.414 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary                            ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.748 ; 0.000         ;
+; CLOCK_50                                            ; 9.265 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 1.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.313     ; 1.270      ;
+; 1.445 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.319     ; 1.243      ;
+; 1.445 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.319     ; 1.243      ;
+; 1.445 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.319     ; 1.243      ;
+; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.238      ;
+; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.238      ;
+; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.238      ;
+; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.238      ;
+; 1.481 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.303     ; 1.223      ;
+; 1.481 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.303     ; 1.223      ;
+; 1.481 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.303     ; 1.223      ;
+; 1.485 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.215      ;
+; 1.485 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.215      ;
+; 1.485 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.215      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 4.705 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.044     ; 3.258      ;
+; 4.712 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.150      ; 3.445      ;
+; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.226      ;
+; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.226      ;
+; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.226      ;
+; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.226      ;
+; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.414      ;
+; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.414      ;
+; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.414      ;
+; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.414      ;
+; 4.748 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.405      ;
+; 4.748 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.405      ;
+; 4.748 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.405      ;
+; 4.750 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.044     ; 3.213      ;
+; 4.756 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.203      ;
+; 4.756 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.203      ;
+; 4.756 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.203      ;
+; 4.757 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.044     ; 3.206      ;
+; 4.764 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.044     ; 3.199      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                           ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 17.244 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 2.729      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.340 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.640      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.343 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.637      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.382 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 2.591      ;
+; 17.405 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.575      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.432 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]          ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 2.541      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.116 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.433      ;
+; 0.123 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.440      ;
+; 0.162 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.487      ;
+; 0.164 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.481      ;
+; 0.165 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.482      ;
+; 0.172 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.220      ; 0.496      ;
+; 0.173 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.220      ; 0.497      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.183 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.500      ;
+; 0.183 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.500      ;
+; 0.186 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.313      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.315      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.189 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.316      ;
+; 0.189 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.316      ;
+; 0.190 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.507      ;
+; 0.192 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.319      ;
+; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.313      ;
+; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[9]                                                                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[18]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[1]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[3]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.315      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                       ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.187 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.307      ;
+; 0.195 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.314      ;
+; 0.199 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.319      ;
+; 0.201 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.325      ;
+; 0.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.325      ;
+; 0.208 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.022      ; 0.314      ;
+; 0.268 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.388      ;
+; 0.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.391      ;
+; 0.294 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.413      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.424      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.424      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.428      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.428      ;
+; 0.309 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.428      ;
+; 0.310 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.430      ;
+; 0.311 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.431      ;
+; 0.313 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.433      ;
+; 0.314 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.434      ;
+; 0.325 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.445      ;
+; 0.369 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.489      ;
+; 0.370 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.490      ;
+; 0.377 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.497      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.809 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.860      ;
+; 0.811 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.864      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.504     ; 1.643      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.504     ; 1.643      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.504     ; 1.643      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.643      ;
+; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.643      ;
+; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.643      ;
+; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.643      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                     ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 17.090 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.061      ; 2.978      ;
+; 17.093 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.061      ; 2.975      ;
+; 17.155 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.061      ; 2.913      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.204 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.856      ;
+; 17.228 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.061      ; 2.840      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.285 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.775      ;
+; 17.288 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.772      ;
+; 17.288 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.772      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.348 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.712      ;
+; 17.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.710      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                    ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.933 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.157      ; 1.174      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 1.015 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.157      ; 1.256      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.379 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.165      ; 1.628      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.541 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.165      ; 1.790      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 2.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.489      ;
+; 2.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.489      ;
+; 2.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.489      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.416 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.005     ; 1.495      ;
+; 2.416 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.005     ; 1.495      ;
+; 2.416 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.005     ; 1.495      ;
+; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.006     ; 1.495      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.007     ; 1.496      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.007     ; 1.496      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.007     ; 1.496      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.495      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                        ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg          ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg          ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0     ;
+; 3.751 ; 3.981        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0     ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                                                                                                                            ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]                                                                                                                            ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                            ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                        ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]         ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1]         ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]         ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]         ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                           ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                            ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]                  ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]                  ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                            ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                ;
+; 9.279 ; 9.463        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                          ;
+; 9.357 ; 9.541        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                  ;
+; 9.425 ; 9.425        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0]           ;
+; 9.425 ; 9.425        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1]           ;
+; 9.425 ; 9.425        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|observablevcoout ;
+; 9.441 ; 9.441        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~input|o                                              ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 2.203 ; 3.113 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 2.203 ; 3.113 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 1.819 ; 2.590 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.569 ; 3.369 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.569 ; 3.369 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.420 ; 3.241 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.344 ; 3.086 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.289 ; 3.048 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.279 ; 3.037 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.147 ; 2.890 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.153 ; 2.902 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.137 ; 2.886 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -0.819 ; -1.598 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -0.859 ; -1.656 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -0.819 ; -1.598 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -1.744 ; -2.479 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -2.164 ; -2.955 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -2.015 ; -2.819 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -1.949 ; -2.683 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -1.891 ; -2.635 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -1.881 ; -2.624 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -1.754 ; -2.483 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -1.760 ; -2.494 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -1.744 ; -2.479 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 4.186  ; 4.306  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 4.186  ; 4.306  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 4.118  ; 4.091  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 2.959  ; 2.978  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 2.959  ; 2.978  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.218  ; 3.178  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.268  ; 2.285  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 2.233  ; 2.237  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.268  ; 2.285  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 2.192  ; 2.204  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 2.244  ; 2.273  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 2.168  ; 2.172  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 2.145  ; 2.152  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 2.161  ; 2.163  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 2.060  ; 2.058  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 2.125  ; 2.133  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 2.167  ; 2.176  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 2.142  ; 2.137  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.057  ; 2.060  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 2.156  ; 2.162  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 2.183  ; 2.200  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 2.140  ; 2.153  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 2.205  ; 2.203  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 5.019  ; 4.759  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 3.533  ; 3.460  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 3.588  ; 3.529  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 3.549  ; 3.512  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 5.019  ; 4.759  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 3.466  ; 3.449  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 3.426  ; 3.430  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 3.769  ; 3.755  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 3.438  ; 3.426  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 3.339  ; 3.455  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 3.129  ; 3.157  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 3.327  ; 3.428  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 3.279  ; 3.193  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 3.442  ; 3.391  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 3.224  ; 3.315  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 3.656  ; 3.619  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 3.402  ; 3.371  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 2.164  ; 2.170  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 2.250  ; 2.268  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 2.082  ; 2.069  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.681  ; 3.498  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.313 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.366 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 4.014  ; 3.986  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 4.082  ; 4.194  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 4.014  ; 3.986  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 2.902  ; 2.917  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 2.902  ; 2.917  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.148  ; 3.113  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 1.797  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 1.967  ; 1.967  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.000  ; 2.014  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 1.929  ; 1.937  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 1.977  ; 2.002  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.904  ; 1.905  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.882  ; 1.886  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.897  ; 1.896  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 1.802  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.862  ; 1.866  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 1.903  ; 1.908  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.880  ; 1.872  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.797  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.892  ; 1.895  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.918  ; 1.931  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.876  ; 1.885  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 1.938  ; 1.933  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 2.265  ; 2.279  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 2.617  ; 2.649  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 2.573  ; 2.625  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 2.537  ; 2.592  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 3.994  ; 3.818  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 2.916  ; 2.995  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 2.630  ; 2.706  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 2.743  ; 2.822  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 2.644  ; 2.702  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 2.505  ; 2.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.610  ; 2.654  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 2.815  ; 2.798  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 2.486  ; 2.520  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 2.265  ; 2.279  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 2.582  ; 2.618  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.580  ; 2.619  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 2.469  ; 2.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 1.900  ; 1.903  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 1.982  ; 1.996  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 1.822  ; 1.806  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.418  ; 3.230  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.537 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.591 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.588 ; 2.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.588 ; 2.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.878 ; 2.859 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.888 ; 2.869 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.774 ; 2.755 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.984 ; 2.965 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.878 ; 2.859 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.004 ; 2.985 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.981 ; 2.962 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.605 ; 2.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.605 ; 2.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.608 ; 2.589 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.595 ; 2.576 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.598 ; 2.579 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.608 ; 2.589 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.588 ; 2.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.984 ; 2.965 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 1.468 ; 1.468 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 1.468 ; 1.468 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 1.746 ; 1.746 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 1.756 ; 1.756 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 1.646 ; 1.646 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 1.848 ; 1.848 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 1.746 ; 1.746 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 1.868 ; 1.868 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 1.845 ; 1.845 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 1.486 ; 1.486 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 1.486 ; 1.486 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 1.488 ; 1.488 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 1.476 ; 1.476 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 1.478 ; 1.478 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 1.488 ; 1.488 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 1.468 ; 1.468 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 1.848 ; 1.848 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.632     ; 2.632     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.632     ; 2.632     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.966     ; 2.966     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.976     ; 2.976     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.841     ; 2.841     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.081     ; 3.081     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.966     ; 2.966     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.101     ; 3.101     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.083     ; 3.083     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.651     ; 2.651     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.651     ; 2.651     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.652     ; 2.652     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.641     ; 2.641     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.642     ; 2.642     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.652     ; 2.652     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.632     ; 2.632     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.081     ; 3.081     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 1.510     ; 1.642     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 1.510     ; 1.642     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 1.831     ; 1.963     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 1.841     ; 1.973     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 1.711     ; 1.843     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 1.941     ; 2.073     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 1.831     ; 1.963     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 1.961     ; 2.093     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 1.943     ; 2.075     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 1.529     ; 1.661     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 1.529     ; 1.661     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 1.530     ; 1.662     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 1.519     ; 1.651     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 1.520     ; 1.652     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 1.530     ; 1.662     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 1.510     ; 1.642     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 1.941     ; 2.073     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 13.232 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.232                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.589        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.643        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.350                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.443        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.907        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.383                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.790        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.435                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.400        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 6.035        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.440                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 5.916        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.456                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.932        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.483                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.588        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.895        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.493                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.591        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 5.902        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.503                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.401        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 6.102        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.535                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.526        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 6.009        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.536                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.525        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 6.011        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.577                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.401        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 6.176        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.581                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.590        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 5.991        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.585                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.402        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 6.183        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.594                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.522        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 6.072        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.596                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 6.003        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.602                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.525        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 6.077        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.615                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.527        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 6.088        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.626                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 6.102        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.653                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.451        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 6.202        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.659                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 6.067        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.664                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.404        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 6.260        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.672                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.325        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 6.347        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.689                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.523        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 6.166        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.691                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.527        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 6.164        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.702                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.450        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 6.252        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.721                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.249        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 6.472        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.734                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 6.142        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.735                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.590        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 6.145        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.736                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.402        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 6.334        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.793                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.599        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 6.194        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.821                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.591        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 6.230        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.899                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.591        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 6.308        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.926                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 6.333        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.971                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 6.378        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.024                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.527        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 6.497        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 14.082                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 6.490        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.127                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 6.535        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 14.191                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.600        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 6.591        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 14.273                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.526        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 6.747        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                                               ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+; Clock                                                ; Setup   ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+; Worst-case Slack                                     ; -0.454  ; 0.116 ; -1.497   ; 0.904   ; 3.736               ;
+;  CLOCK_50                                            ; 15.170  ; 0.187 ; 14.980   ; 0.904   ; 9.265               ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.454  ; 0.116 ; -1.497   ; 2.414   ; 3.736               ;
+; Design-wide TNS                                      ; -22.246 ; 0.0   ; -338.162 ; 0.0     ; 0.0                 ;
+;  CLOCK_50                                            ; 0.000   ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -22.246 ; 0.000 ; -338.162 ; 0.000   ; 0.000               ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 4.050 ; 4.731 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 4.050 ; 4.731 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 3.252 ; 3.792 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 4.454 ; 5.044 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 4.454 ; 5.044 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 4.228 ; 4.804 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 4.088 ; 4.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.985 ; 4.485 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.971 ; 4.476 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.720 ; 4.223 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.722 ; 4.235 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.708 ; 4.219 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -0.819 ; -1.598 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -0.859 ; -1.656 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -0.819 ; -1.598 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -1.744 ; -2.479 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -2.164 ; -2.955 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -2.015 ; -2.819 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -1.949 ; -2.683 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -1.891 ; -2.635 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -1.881 ; -2.624 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -1.754 ; -2.483 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -1.760 ; -2.494 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -1.744 ; -2.479 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 7.004  ; 7.069  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 7.004  ; 7.069  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.882  ; 6.755  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.954  ; 4.908  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.954  ; 4.908  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.291  ; 5.346  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.733  ; 3.645  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.702  ; 3.596  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.732  ; 3.645  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.589  ; 3.523  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.733  ; 3.638  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.576  ; 3.509  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.533  ; 3.439  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.580  ; 3.472  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.373  ; 3.274  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.536  ; 3.433  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.594  ; 3.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.526  ; 3.425  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.389  ; 3.299  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.546  ; 3.449  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.624  ; 3.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.569  ; 3.489  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.685  ; 3.582  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.764  ; 7.387  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.853  ; 5.686  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.923  ; 5.772  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.841  ; 5.703  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.764  ; 7.387  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.747  ; 5.603  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.667  ; 5.552  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 6.210  ; 6.073  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.690  ; 5.589  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.631  ; 5.599  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 5.178  ; 5.147  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.631  ; 5.557  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.436  ; 5.269  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 5.663  ; 5.519  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.466  ; 5.409  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 6.063  ; 5.900  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.624  ; 5.492  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.597  ; 3.540  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.733  ; 3.650  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.442  ; 3.340  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.583  ; 5.291  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.448 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.595 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 4.014  ; 3.986  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 4.082  ; 4.194  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 4.014  ; 3.986  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 2.902  ; 2.917  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 2.902  ; 2.917  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.148  ; 3.113  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 1.797  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 1.967  ; 1.967  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.000  ; 2.014  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 1.929  ; 1.937  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 1.977  ; 2.002  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.904  ; 1.905  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.882  ; 1.886  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.897  ; 1.896  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 1.802  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.862  ; 1.866  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 1.903  ; 1.908  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.880  ; 1.872  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.797  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.892  ; 1.895  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.918  ; 1.931  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.876  ; 1.885  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 1.938  ; 1.933  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 2.265  ; 2.279  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 2.617  ; 2.649  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 2.573  ; 2.625  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 2.537  ; 2.592  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 3.994  ; 3.818  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 2.916  ; 2.995  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 2.630  ; 2.706  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 2.743  ; 2.822  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 2.644  ; 2.702  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 2.505  ; 2.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.610  ; 2.654  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 2.815  ; 2.798  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 2.486  ; 2.520  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 2.265  ; 2.279  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 2.582  ; 2.618  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.580  ; 2.619  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 2.469  ; 2.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 1.900  ; 1.903  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 1.982  ; 1.996  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 1.822  ; 1.806  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.418  ; 3.230  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.537 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.591 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                       ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin              ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; GPIO_1_CLKIN[1]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[9]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[8]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[7]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[6]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[5]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[4]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[3]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[15]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[14]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[13]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[12]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[11]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[10]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[9]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[8]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[7]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[6]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[5]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[4]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[3]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[2]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[1]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[0]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[31]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[30]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[29]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[28]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[27]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[26]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[25]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[24]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[23]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[22]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[21]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[20]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[19]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[18]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[17]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[16]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[15]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[14]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[13]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[12]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[11]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[10]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[9]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[8]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[7]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[6]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[5]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[4]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1_CLKIN[0]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[0]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[2]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[1]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[2]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[1]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[0]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin              ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.08 V              ; -0.00596 V          ; 0.305 V                              ; 0.266 V                              ; 5.3e-09 s                   ; 4.39e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-06 V                  ; 3.08 V             ; -0.00596 V         ; 0.305 V                             ; 0.266 V                             ; 5.3e-09 s                  ; 4.39e-09 s                 ; Yes                       ; Yes                       ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.08 V              ; -0.00513 V          ; 0.274 V                              ; 0.267 V                              ; 5.67e-09 s                  ; 4.62e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.08 V             ; -0.00513 V         ; 0.274 V                             ; 0.267 V                             ; 5.67e-09 s                 ; 4.62e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.08 V              ; -0.00596 V          ; 0.305 V                              ; 0.266 V                              ; 5.3e-09 s                   ; 4.39e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-06 V                  ; 3.08 V             ; -0.00596 V         ; 0.305 V                             ; 0.266 V                             ; 5.3e-09 s                  ; 4.39e-09 s                 ; Yes                       ; Yes                       ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-06 V                   ; 3.14 V              ; -0.0402 V           ; 0.146 V                              ; 0.156 V                              ; 4.62e-10 s                  ; 4.36e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-06 V                  ; 3.14 V             ; -0.0402 V          ; 0.146 V                             ; 0.156 V                             ; 4.62e-10 s                 ; 4.36e-10 s                 ; Yes                       ; Yes                       ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin              ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.52e-08 V                   ; 3.58 V              ; -0.064 V            ; 0.234 V                              ; 0.085 V                              ; 2.93e-10 s                  ; 3.07e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.52e-08 V                  ; 3.58 V             ; -0.064 V           ; 0.234 V                             ; 0.085 V                             ; 2.93e-10 s                 ; 3.07e-10 s                 ; Yes                       ; Yes                       ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                                                                       ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                          ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                                            ; CLOCK_50                                            ; 3186     ; 0        ; 0        ; 0        ;
+; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11681    ; 0        ; 0        ; 0        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                                                                        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                          ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                                            ; CLOCK_50                                            ; 3186     ; 0        ; 0        ; 0        ;
+; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11681    ; 0        ; 0        ; 0        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Recovery Transfers                                                                                           ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50                                            ; 519      ; 0        ; 0        ; 0        ;
+; CLOCK_50   ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302      ; 0        ; 0        ; 0        ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Removal Transfers                                                                                            ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50                                            ; 519      ; 0        ; 0        ; 0        ;
+; CLOCK_50   ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302      ; 0        ; 0        ; 0        ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 3     ; 3    ;
+; Unconstrained Input Ports       ; 29    ; 29   ;
+; Unconstrained Input Port Paths  ; 102   ; 102  ;
+; Unconstrained Output Ports      ; 94    ; 94   ;
+; Unconstrained Output Port Paths ; 472   ; 472  ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Mon Mar 17 10:02:46 2014
+Info: Command: quartus_sta DE0_D5M -c DE0_D5M
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity dcfifo_v5o1
+        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* 
+        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* 
+Info (332104): Reading SDC File: 'DE0_D5M.sdc'
+Info (332110): Deriving PLL clocks
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]}
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.454
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.454             -22.246 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    15.170               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.214
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.214               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.358               0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is -1.497
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.497            -338.162 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    14.980               0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 1.616
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.616               0.000 CLOCK_50 
+    Info (332119):     4.132               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.736
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     3.736               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.580               0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 11.051 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332146): Worst-case setup slack is 0.053
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.053               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    15.677               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.190
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.190               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.312               0.000 CLOCK_50 
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case recovery slack is -0.843
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.843            -150.984 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    15.539               0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 1.477
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.477               0.000 CLOCK_50 
+    Info (332119):     3.638               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.741
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     3.741               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.561               0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 11.581 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info: Analyzing Fast 1200mV 0C Model
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332146): Worst-case setup slack is 1.424
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.424               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    17.244               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.116
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.116               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.187               0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is 0.773
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.773               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    17.090               0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 0.904
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.904               0.000 CLOCK_50 
+    Info (332119):     2.414               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.748
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     3.748               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.265               0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 13.232 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 23 warnings
+    Info: Peak virtual memory: 549 megabytes
+    Info: Processing ended: Mon Mar 17 10:02:50 2014
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:03
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.summary b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.summary
new file mode 100644
index 0000000..4fbf355
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.summary
@@ -0,0 +1,125 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.454
+TNS   : -22.246
+
+Type  : Slow 1200mV 85C Model Setup 'CLOCK_50'
+Slack : 15.170
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.214
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'CLOCK_50'
+Slack : 0.358
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -1.497
+TNS   : -338.162
+
+Type  : Slow 1200mV 85C Model Recovery 'CLOCK_50'
+Slack : 14.980
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'CLOCK_50'
+Slack : 1.616
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 4.132
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.736
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.580
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.053
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'CLOCK_50'
+Slack : 15.677
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.190
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.312
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.843
+TNS   : -150.984
+
+Type  : Slow 1200mV 0C Model Recovery 'CLOCK_50'
+Slack : 15.539
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'CLOCK_50'
+Slack : 1.477
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.638
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.741
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.561
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 1.424
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'CLOCK_50'
+Slack : 17.244
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.116
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.187
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.773
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'CLOCK_50'
+Slack : 17.090
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'CLOCK_50'
+Slack : 0.904
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 2.414
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.748
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.265
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.tis_db_list.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.tis_db_list.ddb
new file mode 100644
index 0000000..8a35815
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.tis_db_list.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v
new file mode 100644
index 0000000..91386f2
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v
@@ -0,0 +1,353 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE0_D5M
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 12/03/14  :| DE0 support
+// --------------------------------------------------------------------
+
+module DE0_D5M
+	(
+		////////////////////	Clock Input	 	////////////////////	 
+		CLOCK_50,						//	50 MHz
+		////////////////////	Push Button		////////////////////
+		KEY,								//	Pushbutton[2:0]
+		////////////////////	DPDT Switch		////////////////////
+		SW,								//	Toggle Switch[9:0]
+		////////////////////////	LED		////////////////////////
+		LEDG,								//	LED Green[9:0]
+		////////////////////	7-SEG Dispaly	////////////////////
+		HEX0,								//	Seven Segment Digit 0
+		HEX1,								//	Seven Segment Digit 1
+		HEX2,								//	Seven Segment Digit 2
+		HEX3,								//	Seven Segment Digit 3
+		/////////////////////	SDRAM Interface		////////////////
+		DRAM_DQ,							//	SDRAM Data bus 16 Bits
+		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_UDQM,						//	SDRAM High-byte Data Mask
+		DRAM_WE_N,						//	SDRAM Write Enable
+		DRAM_CAS_N,						//	SDRAM Column Address Strobe
+		DRAM_RAS_N,						//	SDRAM Row Address Strobe
+		DRAM_CS_N,						//	SDRAM Chip Select
+		DRAM_BA_0,						//	SDRAM Bank Address 0
+		DRAM_BA_1,						//	SDRAM Bank Address 0
+		DRAM_CLK,						//	SDRAM Clock
+		DRAM_CKE,						//	SDRAM Clock Enable
+		////////////////////	VGA		////////////////////////////
+		VGA_HS,							//	VGA H_SYNC
+		VGA_VS,							//	VGA V_SYNC
+		VGA_R,   						//	VGA Red[3:0]
+		VGA_G,	 						//	VGA Green[3:0]
+		VGA_B,  							//	VGA Blue[3:0]
+		VGA_CLK,                   // VGA Clk
+		////////////////////	GPIO	////////////////////////////
+		//GPIO_0,							//	GPIO Connection 0
+		GPIO_1_CLKIN,              // GPIO Connection 1 CLK INPUTS
+		GPIO_1_CLKOUT,             // GPIO Connection 1 CLK OUTPUTS
+		GPIO_1							//	GPIO Connection 1
+	);
+
+////////////////////////	Clock Input	 	////////////////////////
+input			CLOCK_50;				//	50 MHz
+////////////////////////	Push Button		////////////////////////
+input	[2:0]	KEY;						//	Pushbutton[3:0]
+////////////////////////	DPDT Switch		////////////////////////
+input	[9:0]	SW;						//	Toggle Switch[9:0]
+////////////////////////////	LED		////////////////////////////
+output	[9:0]	LEDG;					//	LED Green[7:0]
+////////////////////////	7-SEG Dispaly	////////////////////////
+output	[6:0]	HEX0;					//	Seven Segment Digit 0
+output	[6:0]	HEX1;					//	Seven Segment Digit 1
+output	[6:0]	HEX2;					//	Seven Segment Digit 2
+output	[6:0]	HEX3;					//	Seven Segment Digit 3
+///////////////////////		SDRAM Interface	////////////////////////
+inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
+output[11:0]	DRAM_ADDR;			//	SDRAM Address bus 12 Bits
+output			DRAM_LDQM;			//	SDRAM Low-byte Data Mask 
+output			DRAM_UDQM;			//	SDRAM High-byte Data Mask
+output			DRAM_WE_N;			//	SDRAM Write Enable
+output			DRAM_CAS_N;			//	SDRAM Column Address Strobe
+output			DRAM_RAS_N;			//	SDRAM Row Address Strobe
+output			DRAM_CS_N;			//	SDRAM Chip Select
+output			DRAM_BA_0;			//	SDRAM Bank Address 0
+output			DRAM_BA_1;			//	SDRAM Bank Address 0
+output			DRAM_CLK;			//	SDRAM Clock
+output			DRAM_CKE;			//	SDRAM Clock Enable
+////////////////////////	VGA			////////////////////////////
+output			VGA_HS;				//	VGA H_SYNC
+output			VGA_VS;				//	VGA V_SYNC
+output	[3:0]	VGA_R;   			//	VGA Red[3:0]
+output	[3:0]	VGA_G;	 			//	VGA Green[3:0]
+output	[3:0]	VGA_B;   			//	VGA Blue[3:0]
+output         VGA_CLK;          // VGA Clk
+////////////////////////	GPIO	////////////////////////////////
+
+input	[1:0]	   GPIO_1_CLKIN;				//	GPIO Connection 1 - need stand alone inputs for external clock, pins on the board rewired
+output [1:0]	GPIO_1_CLKOUT;				//	GPIO Connection 1 - need stand alone outputs for external clock, pins on the board rewired
+inout	[31:0]	GPIO_1;				//	GPIO Connection 1
+///////////////////////////////////////////////////////////////////
+//=============================================================================
+// REG/WIRE declarations
+//=============================================================================
+
+//	CCD
+wire	[11:0]	CCD_DATA;
+wire				CCD_SDAT;
+wire				CCD_SCLK;
+wire				CCD_FLASH;
+wire				CCD_FVAL;
+wire				CCD_LVAL;
+wire				CCD_PIXCLK;
+wire				CCD_MCLK;				//	CCD Master Clock
+
+wire	[15:0]	Read_DATA1;
+wire	[15:0]	Read_DATA2;
+wire				VGA_CTRL_CLK;
+wire	[11:0]	mCCD_DATA;
+wire				mCCD_DVAL;
+wire				mCCD_DVAL_d;
+wire	[15:0]	X_Cont;
+wire	[15:0]	Y_Cont;
+wire	[9:0]		X_ADDR;
+wire	[31:0]	Frame_Cont;
+wire				DLY_RST_0;
+wire				DLY_RST_1;
+wire				DLY_RST_2;
+wire				Read;
+reg	[11:0]	rCCD_DATA;
+reg				rCCD_LVAL;
+reg				rCCD_FVAL;
+wire	[11:0]	sCCD_R;
+wire	[11:0]	sCCD_G;
+wire	[11:0]	sCCD_B;
+wire				sCCD_DVAL;
+wire	[3:0]		VGA_R;   				//	VGA Red[9:0]
+wire	[3:0]		VGA_G;	 				//	VGA Green[9:0]
+wire	[3:0]		VGA_B;   				//	VGA Blue[9:0]
+reg	[1:0]		rClk;
+wire				sdram_ctrl_clk;
+
+//=============================================================================
+// Structural coding
+//=============================================================================
+assign	CCD_DATA[0]	=	GPIO_1[11];
+assign	CCD_DATA[1]	=	GPIO_1[10];
+assign	CCD_DATA[2]	=	GPIO_1[9];
+assign	CCD_DATA[3]	=	GPIO_1[8];
+assign	CCD_DATA[4]	=	GPIO_1[7];
+assign	CCD_DATA[5]	=	GPIO_1[6];
+assign	CCD_DATA[6]	=	GPIO_1[5];
+assign	CCD_DATA[7]	=	GPIO_1[4];
+assign	CCD_DATA[8]	=	GPIO_1[3];
+assign	CCD_DATA[9]	=	GPIO_1[2];
+assign	CCD_DATA[10]=	GPIO_1[1];
+assign	CCD_DATA[11]=	GPIO_1[0];
+assign	GPIO_1_CLKOUT[0]	=	CCD_MCLK;
+assign	CCD_FVAL	   =	GPIO_1[18];
+assign	CCD_LVAL	   =	GPIO_1[17];
+assign	CCD_PIXCLK	=	GPIO_1_CLKIN[0]; //GPIO_1[0];
+assign	GPIO_1[15]	=	1'b1;  // tRIGGER
+assign	GPIO_1[14]	=	DLY_RST_1;
+
+assign	LEDG		   =	Y_Cont;
+
+assign	VGA_CTRL_CLK=	rClk[0];
+assign	VGA_CLK		=	~rClk[0];
+
+always@(posedge CLOCK_50)	rClk	<=	rClk+1;
+
+wire	[9:0]	oVGA_R;
+wire	[9:0]	oVGA_G;
+wire	[9:0]	oVGA_B;
+assign	VGA_R		=	oVGA_R[9:6];
+assign	VGA_G		=	oVGA_G[9:6];
+assign	VGA_B		=	oVGA_B[9:6];
+
+
+always@(posedge CCD_PIXCLK)
+begin
+	rCCD_DATA	<=	CCD_DATA;
+	rCCD_LVAL	<=	CCD_LVAL;
+	rCCD_FVAL	<=	CCD_FVAL;
+end
+
+VGA_Controller		u1	(	//	Host Side
+							.oRequest   (Read),
+//							.iRed       (10'b1111111111),
+//							.iGreen     (10'b0000000000),
+//							.iBlue      (10'b0000000000),
+							.iRed       (Read_DATA2[9:0]),
+							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
+							.iBlue      (Read_DATA1[9:0]),
+							//	VGA Side
+							.oVGA_R     (oVGA_R),
+							.oVGA_G     (oVGA_G),
+							.oVGA_B     (oVGA_B),
+							.oVGA_H_SYNC(VGA_HS),
+							.oVGA_V_SYNC(VGA_VS),
+							//	Control Signal
+							.iCLK       (VGA_CTRL_CLK),
+							.iRST_N     (DLY_RST_2)
+						);
+
+
+Reset_Delay			u2	(	
+							.iCLK  (CLOCK_50),
+							.iRST  (KEY[0]),
+							.oRST_0(DLY_RST_0),
+							.oRST_1(DLY_RST_1),
+							.oRST_2(DLY_RST_2)
+						);
+
+CCD_Capture			u3	(	
+							.oDATA      (mCCD_DATA),
+							.oDVAL      (mCCD_DVAL),
+							.oX_Cont    (X_Cont),
+							.oY_Cont    (Y_Cont),
+							.oFrame_Cont(Frame_Cont),
+							.iDATA      (rCCD_DATA),
+							.iFVAL      (rCCD_FVAL),
+							.iLVAL      (rCCD_LVAL),
+							.iSTART     (!KEY[1]),
+							.iEND       (!KEY[2]),
+							.iCLK       (CCD_PIXCLK),
+							.iRST       (DLY_RST_2)
+						);
+
+RAW2RGB				u4	(	
+						   .iCLK   (CCD_PIXCLK),
+							.iRST   (DLY_RST_1),
+							.iDATA  (mCCD_DATA),
+							.iDVAL  (mCCD_DVAL),
+							.oRed   (sCCD_R),
+							.oGreen (sCCD_G),
+							.oBlue  (sCCD_B),
+							.oDVAL  (sCCD_DVAL),
+							.iX_Cont(X_Cont),
+							.iY_Cont(Y_Cont)
+						);
+
+SEG7_LUT_8 			u5	(	
+							.oSEG0(HEX0),
+							.oSEG1(HEX1),
+							.oSEG2(HEX2),
+							.oSEG3(HEX3),
+							.oSEG4(),
+							.oSEG5(),
+							.oSEG6(),
+							.oSEG7(),
+							.iDIG (Frame_Cont[31:0])
+						);
+
+sdram_pll 			u6	(
+							.inclk0(CLOCK_50),
+							.c0    (sdram_ctrl_clk),
+							.c1    (DRAM_CLK)
+						);
+
+assign CCD_MCLK = rClk[0];
+
+Sdram_Control_4Port	u7	(	//	HOST Side						
+								 .REF_CLK     (CLOCK_50),
+						       .RESET_N     (1'b1),
+							    .CLK    	  (sdram_ctrl_clk),
+
+									//	FIFO Write Side 1
+							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
+							    .WR1     	  (sCCD_DVAL),
+								 .WR1_ADDR	  (0),
+								 .WR1_MAX_ADDR(640*480),
+								 .WR1_LENGTH  (9'h100),
+								 .WR1_LOAD	  (!DLY_RST_0),
+								 .WR1_CLK	  (~CCD_PIXCLK),
+
+								  //	FIFO Write Side 2
+								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
+								 .WR2			  (sCCD_DVAL),
+								 .WR2_ADDR    (22'h100000),
+								 .WR2_MAX_ADDR(22'h100000+640*480),
+								 .WR2_LENGTH  (9'h100),
+								 .WR2_LOAD    (!DLY_RST_0),
+								 .WR2_CLK     (~CCD_PIXCLK),
+
+
+								  //	FIFO Read Side 1
+						       .RD1_DATA	  (Read_DATA1),
+								 .RD1			  (Read),
+				        	    .RD1_ADDR    (0),
+								 .RD1_MAX_ADDR(640*480),
+								 .RD1_LENGTH  (9'h100),
+								 .RD1_LOAD	  (!DLY_RST_0),
+								 .RD1_CLK	  (~VGA_CTRL_CLK),
+							
+								  //	FIFO Read Side 2
+						       .RD2_DATA	  (Read_DATA2),
+								 .RD2         (Read),
+								 .RD2_ADDR    (22'h100000),
+								 .RD2_MAX_ADDR(22'h100000+640*480),
+								 .RD2_LENGTH  (9'h100),
+								 .RD2_LOAD    (!DLY_RST_0),
+								 .RD2_CLK     (~VGA_CTRL_CLK),
+							
+								  //	SDRAM Side
+						       .SA			  (DRAM_ADDR),
+						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
+								 .CS_N		  (DRAM_CS_N),
+        					    .CKE			  (DRAM_CKE),
+								 .RAS_N		  (DRAM_RAS_N),
+								 .CAS_N		  (DRAM_CAS_N),
+								 .WE_N		  (DRAM_WE_N),
+								 .DQ			  (DRAM_DQ),
+								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
+						       );
+
+
+
+I2C_CCD_Config 		u8	(	//	Host Side
+								 .iCLK			  (CLOCK_50),
+								 .iRST_N         (DLY_RST_2),
+								 .iZOOM_MODE_SW  (SW[2]),
+								 .iEXPOSURE_ADJ  (SW[1]),
+								 .iEXPOSURE_DEC_p(SW[0]),
+								  //	I2C Side
+								 .I2C_SCLK		  (GPIO_1[20]),
+								 .I2C_SDAT		  (GPIO_1[19])
+							   );
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v.bak
new file mode 100644
index 0000000..1ff6dd3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v.bak
@@ -0,0 +1,435 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE1 D5M
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module DE1_D5M
+	(
+		////////////////////	Clock Input	 	////////////////////	 
+		CLOCK_24,						//	24 MHz
+		CLOCK_27,						//	27 MHz
+		CLOCK_50,						//	50 MHz
+		EXT_CLOCK,						//	External Clock
+		////////////////////	Push Button		////////////////////
+		KEY,								//	Pushbutton[3:0]
+		////////////////////	DPDT Switch		////////////////////
+		SW,								//	Toggle Switch[9:0]
+		////////////////////	7-SEG Dispaly	////////////////////
+		HEX0,								//	Seven Segment Digit 0
+		HEX1,								//	Seven Segment Digit 1
+		HEX2,								//	Seven Segment Digit 2
+		HEX3,								//	Seven Segment Digit 3
+		////////////////////////	LED		////////////////////////
+		LEDG,								//	LED Green[7:0]
+		LEDR,								//	LED Red[9:0]
+		////////////////////////	UART	////////////////////////
+		UART_TXD,						//	UART Transmitter
+		UART_RXD,						//	UART Receiver
+		/////////////////////	SDRAM Interface		////////////////
+		DRAM_DQ,							//	SDRAM Data bus 16 Bits
+		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_UDQM,						//	SDRAM High-byte Data Mask
+		DRAM_WE_N,						//	SDRAM Write Enable
+		DRAM_CAS_N,						//	SDRAM Column Address Strobe
+		DRAM_RAS_N,						//	SDRAM Row Address Strobe
+		DRAM_CS_N,						//	SDRAM Chip Select
+		DRAM_BA_0,						//	SDRAM Bank Address 0
+		DRAM_BA_1,						//	SDRAM Bank Address 0
+		DRAM_CLK,						//	SDRAM Clock
+		DRAM_CKE,						//	SDRAM Clock Enable
+		////////////////////	Flash Interface		////////////////
+		FL_DQ,							//	FLASH Data bus 8 Bits
+		FL_ADDR,							//	FLASH Address bus 22 Bits
+		FL_WE_N,							//	FLASH Write Enable
+		FL_RST_N,						//	FLASH Reset
+		FL_OE_N,							//	FLASH Output Enable
+		FL_CE_N,							//	FLASH Chip Enable
+		////////////////////	SRAM Interface		////////////////
+		SRAM_DQ,							//	SRAM Data bus 16 Bits
+		SRAM_ADDR,						//	SRAM Address bus 18 Bits
+		SRAM_UB_N,						//	SRAM High-byte Data Mask 
+		SRAM_LB_N,						//	SRAM Low-byte Data Mask 
+		SRAM_WE_N,						//	SRAM Write Enable
+		SRAM_CE_N,						//	SRAM Chip Enable
+		SRAM_OE_N,						//	SRAM Output Enable
+		////////////////////	SD_Card Interface	////////////////
+		SD_DAT,							//	SD Card Data
+		SD_DAT3,							//	SD Card Data 3
+		SD_CMD,							//	SD Card Command Signal
+		SD_CLK,							//	SD Card Clock
+		////////////////////	USB JTAG link	////////////////////
+		TDI,  							// CPLD -> FPGA (data in)
+		TCK,  							// CPLD -> FPGA (clk)
+		TCS,  							// CPLD -> FPGA (CS)
+	    TDO,  							// FPGA -> CPLD (data out)
+		////////////////////	I2C		////////////////////////////
+		I2C_SDAT,						//	I2C Data
+		I2C_SCLK,						//	I2C Clock
+		////////////////////	PS2		////////////////////////////
+		PS2_DAT,							//	PS2 Data
+		PS2_CLK,							//	PS2 Clock
+		////////////////////	VGA		////////////////////////////
+		VGA_HS,							//	VGA H_SYNC
+		VGA_VS,							//	VGA V_SYNC
+		VGA_R,   						//	VGA Red[3:0]
+		VGA_G,	 						//	VGA Green[3:0]
+		VGA_B,  							//	VGA Blue[3:0]
+		////////////////	Audio CODEC		////////////////////////
+		AUD_ADCLRCK,					//	Audio CODEC ADC LR Clock
+		AUD_ADCDAT,						//	Audio CODEC ADC Data
+		AUD_DACLRCK,					//	Audio CODEC DAC LR Clock
+		AUD_DACDAT,						//	Audio CODEC DAC Data
+		AUD_BCLK,						//	Audio CODEC Bit-Stream Clock
+		AUD_XCK,							//	Audio CODEC Chip Clock
+		////////////////////	GPIO	////////////////////////////
+		GPIO_0,							//	GPIO Connection 0
+		GPIO_1							//	GPIO Connection 1
+	);
+
+////////////////////////	Clock Input	 	////////////////////////
+input	[1:0]	CLOCK_24;				//	24 MHz
+input	[1:0]	CLOCK_27;				//	27 MHz
+input			CLOCK_50;				//	50 MHz
+input			EXT_CLOCK;				//	External Clock
+////////////////////////	Push Button		////////////////////////
+input	[2:0]	KEY;						//	Pushbutton[3:0]
+////////////////////////	DPDT Switch		////////////////////////
+input	[9:0]	SW;						//	Toggle Switch[9:0]
+////////////////////////	7-SEG Dispaly	////////////////////////
+output	[6:0]	HEX0;					//	Seven Segment Digit 0
+output	[6:0]	HEX1;					//	Seven Segment Digit 1
+output	[6:0]	HEX2;					//	Seven Segment Digit 2
+output	[6:0]	HEX3;					//	Seven Segment Digit 3
+////////////////////////////	LED		////////////////////////////
+output	[7:0]	LEDG;					//	LED Green[7:0]
+output	[9:0]	LEDR;					//	LED Red[9:0]
+////////////////////////////	UART	////////////////////////////
+output			UART_TXD;			//	UART Transmitter
+input				UART_RXD;			//	UART Receiver
+///////////////////////		SDRAM Interface	////////////////////////
+inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
+output[11:0]	DRAM_ADDR;			//	SDRAM Address bus 12 Bits
+output			DRAM_LDQM;			//	SDRAM Low-byte Data Mask 
+output			DRAM_UDQM;			//	SDRAM High-byte Data Mask
+output			DRAM_WE_N;			//	SDRAM Write Enable
+output			DRAM_CAS_N;			//	SDRAM Column Address Strobe
+output			DRAM_RAS_N;			//	SDRAM Row Address Strobe
+output			DRAM_CS_N;			//	SDRAM Chip Select
+output			DRAM_BA_0;			//	SDRAM Bank Address 0
+output			DRAM_BA_1;			//	SDRAM Bank Address 0
+output			DRAM_CLK;			//	SDRAM Clock
+output			DRAM_CKE;			//	SDRAM Clock Enable
+////////////////////////	Flash Interface	////////////////////////
+inout	[7:0]		FL_DQ;				//	FLASH Data bus 8 Bits
+output[21:0]	FL_ADDR;				//	FLASH Address bus 22 Bits
+output			FL_WE_N;				//	FLASH Write Enable
+output			FL_RST_N;			//	FLASH Reset
+output			FL_OE_N;				//	FLASH Output Enable
+output			FL_CE_N;				//	FLASH Chip Enable
+////////////////////////	SRAM Interface	////////////////////////
+inout	[15:0]	SRAM_DQ;				//	SRAM Data bus 16 Bits
+output[17:0]	SRAM_ADDR;			//	SRAM Address bus 18 Bits
+output			SRAM_UB_N;			//	SRAM High-byte Data Mask 
+output			SRAM_LB_N;			//	SRAM Low-byte Data Mask 
+output			SRAM_WE_N;			// SRAM Write Enable
+output			SRAM_CE_N;			//	SRAM Chip Enable
+output			SRAM_OE_N;			//	SRAM Output Enable
+////////////////////	SD Card Interface	////////////////////////
+inout				SD_DAT;				//	SD Card Data
+inout				SD_DAT3;				//	SD Card Data 3
+inout				SD_CMD;				//	SD Card Command Signal
+output			SD_CLK;				//	SD Card Clock
+////////////////////////	I2C		////////////////////////////////
+inout				I2C_SDAT;			//	I2C Data
+output			I2C_SCLK;			//	I2C Clock
+////////////////////////	PS2		////////////////////////////////
+input		 		PS2_DAT;				//	PS2 Data
+input				PS2_CLK;				//	PS2 Clock
+////////////////////	USB JTAG link	////////////////////////////
+input  			TDI;					// CPLD -> FPGA (data in)
+input  			TCK;					// CPLD -> FPGA (clk)
+input  			TCS;					// CPLD -> FPGA (CS)
+output 			TDO;					// FPGA -> CPLD (data out)
+////////////////////////	VGA			////////////////////////////
+output			VGA_HS;				//	VGA H_SYNC
+output			VGA_VS;				//	VGA V_SYNC
+output	[3:0]	VGA_R;   			//	VGA Red[3:0]
+output	[3:0]	VGA_G;	 			//	VGA Green[3:0]
+output	[3:0]	VGA_B;   			//	VGA Blue[3:0]
+////////////////////	Audio CODEC		////////////////////////////
+inout				AUD_ADCLRCK;		//	Audio CODEC ADC LR Clock
+input				AUD_ADCDAT;			//	Audio CODEC ADC Data
+inout				AUD_DACLRCK;		//	Audio CODEC DAC LR Clock
+output			AUD_DACDAT;			//	Audio CODEC DAC Data
+inout				AUD_BCLK;			//	Audio CODEC Bit-Stream Clock
+output			AUD_XCK;				//	Audio CODEC Chip Clock
+////////////////////////	GPIO	////////////////////////////////
+inout	[31:0]	GPIO_0;				//	GPIO Connection 0
+inout	[31:0]	GPIO_1;				//	GPIO Connection 1
+///////////////////////////////////////////////////////////////////
+//=============================================================================
+// REG/WIRE declarations
+//=============================================================================
+
+//	CCD
+wire	[11:0]	CCD_DATA;
+wire				CCD_SDAT;
+wire				CCD_SCLK;
+wire				CCD_FLASH;
+wire				CCD_FVAL;
+wire				CCD_LVAL;
+wire				CCD_PIXCLK;
+wire				CCD_MCLK;				//	CCD Master Clock
+
+wire	[15:0]	Read_DATA1;
+wire	[15:0]	Read_DATA2;
+wire				VGA_CTRL_CLK;
+wire	[11:0]	mCCD_DATA;
+wire				mCCD_DVAL;
+wire				mCCD_DVAL_d;
+wire	[15:0]	X_Cont;
+wire	[15:0]	Y_Cont;
+wire	[9:0]		X_ADDR;
+wire	[31:0]	Frame_Cont;
+wire				DLY_RST_0;
+wire				DLY_RST_1;
+wire				DLY_RST_2;
+wire				Read;
+reg	[11:0]	rCCD_DATA;
+reg				rCCD_LVAL;
+reg				rCCD_FVAL;
+wire	[11:0]	sCCD_R;
+wire	[11:0]	sCCD_G;
+wire	[11:0]	sCCD_B;
+wire				sCCD_DVAL;
+wire	[3:0]		VGA_R;   				//	VGA Red[9:0]
+wire	[3:0]		VGA_G;	 				//	VGA Green[9:0]
+wire	[3:0]		VGA_B;   				//	VGA Blue[9:0]
+reg	[1:0]		rClk;
+wire				sdram_ctrl_clk;
+
+//=============================================================================
+// Structural coding
+//=============================================================================
+assign	CCD_DATA[0]	=	GPIO_1[13];
+assign	CCD_DATA[1]	=	GPIO_1[12];
+assign	CCD_DATA[2]	=	GPIO_1[11];
+assign	CCD_DATA[3]	=	GPIO_1[10];
+assign	CCD_DATA[4]	=	GPIO_1[9];
+assign	CCD_DATA[5]	=	GPIO_1[8];
+assign	CCD_DATA[6]	=	GPIO_1[7];
+assign	CCD_DATA[7]	=	GPIO_1[6];
+assign	CCD_DATA[8]	=	GPIO_1[5];
+assign	CCD_DATA[9]	=	GPIO_1[4];
+assign	CCD_DATA[10]=	GPIO_1[3];
+assign	CCD_DATA[11]=	GPIO_1[1];
+assign	GPIO_1[16]	=	CCD_MCLK;
+assign	CCD_FVAL	   =	GPIO_1[22];
+assign	CCD_LVAL	   =	GPIO_1[21];
+assign	CCD_PIXCLK	=	GPIO_1[0];
+assign	GPIO_1[19]	=	1'b1;  // tRIGGER
+assign	GPIO_1[17]	=	DLY_RST_1;
+
+assign	LEDR		   =	SW;
+assign	LEDG		   =	Y_Cont;
+
+assign	VGA_CTRL_CLK=	rClk[0];
+assign	VGA_CLK		=	~rClk[0];
+
+always@(posedge CLOCK_50)	rClk	<=	rClk+1;
+
+wire	[9:0]	oVGA_R;
+wire	[9:0]	oVGA_G;
+wire	[9:0]	oVGA_B;
+assign	VGA_R		=	oVGA_R[9:6];
+assign	VGA_G		=	oVGA_G[9:6];
+assign	VGA_B		=	oVGA_B[9:6];
+
+
+always@(posedge CCD_PIXCLK)
+begin
+	rCCD_DATA	<=	CCD_DATA;
+	rCCD_LVAL	<=	CCD_LVAL;
+	rCCD_FVAL	<=	CCD_FVAL;
+end
+
+VGA_Controller		u1	(	//	Host Side
+							.oRequest   (Read),
+							.iRed       (Read_DATA2[9:0]),
+							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
+							.iBlue      (Read_DATA1[9:0]),
+							//	VGA Side
+							.oVGA_R     (oVGA_R),
+							.oVGA_G     (oVGA_G),
+							.oVGA_B     (oVGA_B),
+							.oVGA_H_SYNC(VGA_HS),
+							.oVGA_V_SYNC(VGA_VS),
+							//	Control Signal
+							.iCLK       (VGA_CTRL_CLK),
+							.iRST_N     (DLY_RST_2)
+						);
+
+
+Reset_Delay			u2	(	
+							.iCLK  (CLOCK_50),
+							.iRST  (KEY[0]),
+							.oRST_0(DLY_RST_0),
+							.oRST_1(DLY_RST_1),
+							.oRST_2(DLY_RST_2)
+						);
+
+CCD_Capture			u3	(	
+							.oDATA      (mCCD_DATA),
+							.oDVAL      (mCCD_DVAL),
+							.oX_Cont    (X_Cont),
+							.oY_Cont    (Y_Cont),
+							.oFrame_Cont(Frame_Cont),
+							.iDATA      (rCCD_DATA),
+							.iFVAL      (rCCD_FVAL),
+							.iLVAL      (rCCD_LVAL),
+							.iSTART     (!SW[3]),
+							.iEND       (!KEY[2]),
+							.iCLK       (CCD_PIXCLK),
+							.iRST       (DLY_RST_2)
+						);
+
+RAW2RGB				u4	(	
+						   .iCLK   (CCD_PIXCLK),
+							.iRST   (DLY_RST_1),
+							.iDATA  (mCCD_DATA),
+							.iDVAL  (mCCD_DVAL),
+							.oRed   (sCCD_R),
+							.oGreen (sCCD_G),
+							.oBlue  (sCCD_B),
+							.oDVAL  (sCCD_DVAL),
+							.iX_Cont(X_Cont),
+							.iY_Cont(Y_Cont)
+						);
+
+SEG7_LUT_8 			u5	(	
+							.oSEG0(HEX0),
+							.oSEG1(HEX1),
+							.oSEG2(HEX2),
+							.oSEG3(HEX3),
+							.oSEG4(),
+							.oSEG5(),
+							.oSEG6(),
+							.oSEG7(),
+							.iDIG (Frame_Cont[31:0])
+						);
+
+sdram_pll 			u6	(
+							.inclk0(CLOCK_50),
+							.c0    (sdram_ctrl_clk),
+							.c1    (DRAM_CLK)
+						);
+
+assign CCD_MCLK = rClk[0];
+
+Sdram_Control_4Port	u7	(	//	HOST Side						
+								 .REF_CLK     (CLOCK_50),
+						       .RESET_N     (1'b1),
+							    .CLK    	  (sdram_ctrl_clk),
+
+									//	FIFO Write Side 1
+							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
+							    .WR1     	  (sCCD_DVAL),
+								 .WR1_ADDR	  (0),
+								 .WR1_MAX_ADDR(640*480),
+								 .WR1_LENGTH  (9'h100),
+								 .WR1_LOAD	  (!DLY_RST_0),
+								 .WR1_CLK	  (~CCD_PIXCLK),
+
+								  //	FIFO Write Side 2
+								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
+								 .WR2			  (sCCD_DVAL),
+								 .WR2_ADDR    (22'h100000),
+								 .WR2_MAX_ADDR(22'h100000+640*480),
+								 .WR2_LENGTH  (9'h100),
+								 .WR2_LOAD    (!DLY_RST_0),
+								 .WR2_CLK     (~CCD_PIXCLK),
+
+
+								  //	FIFO Read Side 1
+						       .RD1_DATA	  (Read_DATA1),
+								 .RD1			  (Read),
+				        	    .RD1_ADDR    (0),
+								 .RD1_MAX_ADDR(640*480),
+								 .RD1_LENGTH  (9'h100),
+								 .RD1_LOAD	  (!DLY_RST_0),
+								 .RD1_CLK	  (~VGA_CTRL_CLK),
+							
+								  //	FIFO Read Side 2
+						       .RD2_DATA	  (Read_DATA2),
+								 .RD2         (Read),
+								 .RD2_ADDR    (22'h100000),
+								 .RD2_MAX_ADDR(22'h100000+640*480),
+								 .RD2_LENGTH  (9'h100),
+								 .RD2_LOAD    (!DLY_RST_0),
+								 .RD2_CLK     (~VGA_CTRL_CLK),
+							
+								  //	SDRAM Side
+						       .SA			  (DRAM_ADDR),
+						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
+								 .CS_N		  (DRAM_CS_N),
+        					    .CKE			  (DRAM_CKE),
+								 .RAS_N		  (DRAM_RAS_N),
+								 .CAS_N		  (DRAM_CAS_N),
+								 .WE_N		  (DRAM_WE_N),
+								 .DQ			  (DRAM_DQ),
+								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
+						       );
+
+
+assign	UART_TXD = UART_RXD;
+
+I2C_CCD_Config 		u8	(	//	Host Side
+								 .iCLK			  (CLOCK_50),
+								 .iRST_N         (DLY_RST_2),
+								 .iZOOM_MODE_SW  (SW[8]),
+								 .iEXPOSURE_ADJ  (KEY[1]),
+								 .iEXPOSURE_DEC_p(SW[0]),
+								  //	I2C Side
+								 .I2C_SCLK		  (GPIO_1[24]),
+								 .I2C_SDAT		  (GPIO_1[23])
+							   );
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE1_D5M_assignment_defaults.qdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE1_D5M_assignment_defaults.qdf
new file mode 100644
index 0000000..cdf6850
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE1_D5M_assignment_defaults.qdf
@@ -0,0 +1,642 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Internal Build 220 05/13/2009 Service Pack 2 SJ Full Version
+# Date created = 19:24:48  May 26, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus II software and is used
+#    to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name IGNORE_CLOCK_SETTINGS Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off
+set_global_assignment -name ENABLE_CLOCK_LATENCY Off
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family ACEX1K
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KA
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10K
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KC
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX6000
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "APEX II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy IV"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III LS"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix
+set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200
+set_global_assignment -name DO_MIN_ANALYSIS Off
+set_global_assignment -name DO_MIN_TIMING Off
+set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off
+set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family ACEX1K
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KA
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10K
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KC
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX6000
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "APEX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family ACEX1K
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KA
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10K
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KC
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX6000
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "APEX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL93
+set_global_assignment -name FAMILY "Stratix II"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
+set_global_assignment -name PARALLEL_SYNTHESIS Off
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off
+set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Arria GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off
+set_global_assignment -name SAVE_INTERMEDIATE_FITTING_RESULTS Off
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -value OFF
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family ACEX1K
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KA
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10K
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KC
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX6000
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "APEX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Stratix III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY -value OFF
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION -value OFF
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
+set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Line_Buffer.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Line_Buffer.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Line_Buffer.qip
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Control_4Port.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Control_4Port.v
new file mode 100644
index 0000000..22e2411
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Control_4Port.v
@@ -0,0 +1,567 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	Sdram_Control_4Port
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module Sdram_Control_4Port(
+		//	HOST Side
+        REF_CLK,
+        RESET_N,
+		CLK,
+		//	FIFO Write Side 1
+        WR1_DATA,
+		WR1,
+		WR1_ADDR,
+		WR1_MAX_ADDR,
+		WR1_LENGTH,
+		WR1_LOAD,
+		WR1_CLK,
+		//	FIFO Write Side 2
+        WR2_DATA,
+		WR2,
+		WR2_ADDR,
+		WR2_MAX_ADDR,
+		WR2_LENGTH,
+		WR2_LOAD,
+		WR2_CLK,
+		//	FIFO Read Side 1
+        RD1_DATA,
+		RD1,
+		RD1_ADDR,
+		RD1_MAX_ADDR,
+		RD1_LENGTH,
+		RD1_LOAD,	
+		RD1_CLK,
+		//	FIFO Read Side 2
+        RD2_DATA,
+		RD2,
+		RD2_ADDR,
+		RD2_MAX_ADDR,
+		RD2_LENGTH,
+		RD2_LOAD,
+		RD2_CLK,
+		//	SDRAM Side
+        SA,
+        BA,
+        CS_N,
+        CKE,
+        RAS_N,
+        CAS_N,
+        WE_N,
+        DQ,
+        DQM,
+        );
+
+
+`include        "Sdram_Params.h"
+//	HOST Side
+input                           REF_CLK;                //System Clock
+input                           RESET_N;                //System Reset
+input 							CLK;
+//	FIFO Write Side 1
+input   [`DSIZE-1:0]            WR1_DATA;               //Data input
+input							WR1;					//Write Request
+input	[`ASIZE-1:0]			WR1_ADDR;				//Write start address
+input	[`ASIZE-1:0]			WR1_MAX_ADDR;			//Write max address
+input	[8:0]					WR1_LENGTH;				//Write length
+input							WR1_LOAD;				//Write register load & fifo clear
+input							WR1_CLK;				//Write fifo clock
+
+//	FIFO Write Side 2
+input   [`DSIZE-1:0]            WR2_DATA;               //Data input
+input							WR2;					//Write Request
+input	[`ASIZE-1:0]			WR2_ADDR;				//Write start address
+input	[`ASIZE-1:0]			WR2_MAX_ADDR;			//Write max address
+input	[8:0]					WR2_LENGTH;				//Write length
+input							WR2_LOAD;				//Write register load & fifo clear
+input							WR2_CLK;				//Write fifo clock
+
+//	FIFO Read Side 1
+output  [`DSIZE-1:0]            RD1_DATA;               //Data output
+input							RD1;					//Read Request
+input	[`ASIZE-1:0]			RD1_ADDR;				//Read start address
+input	[`ASIZE-1:0]			RD1_MAX_ADDR;			//Read max address
+input	[8:0]					RD1_LENGTH;				//Read length
+input							RD1_LOAD;				//Read register load & fifo clear
+input							RD1_CLK;				//Read fifo clock
+
+//	FIFO Read Side 2
+output  [`DSIZE-1:0]            RD2_DATA;               //Data output
+input							RD2;					//Read Request
+input	[`ASIZE-1:0]			RD2_ADDR;				//Read start address
+input	[`ASIZE-1:0]			RD2_MAX_ADDR;			//Read max address
+input	[8:0]					RD2_LENGTH;				//Read length
+input							RD2_LOAD;				//Read register load & fifo clear
+input							RD2_CLK;				//Read fifo clock
+
+//	SDRAM Side
+output  [11:0]                  SA;                     //SDRAM address output
+output  [1:0]                   BA;                     //SDRAM bank address
+output  [1:0]                   CS_N;                   //SDRAM Chip Selects
+output                          CKE;                    //SDRAM clock enable
+output                          RAS_N;                  //SDRAM Row address Strobe
+output                          CAS_N;                  //SDRAM Column address Strobe
+output                          WE_N;                   //SDRAM write enable
+inout   [`DSIZE-1:0]            DQ;                     //SDRAM data bus
+output  [`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
+
+//	Internal Registers/Wires
+//	Controller
+reg		[`ASIZE-1:0]			mADDR;					//Internal address
+reg		[8:0]					mLENGTH;				//Internal length
+reg		[`ASIZE-1:0]			rWR1_ADDR;				//Register write address				
+reg		[`ASIZE-1:0]			rWR1_MAX_ADDR;			//Register max write address				
+reg		[8:0]					rWR1_LENGTH;			//Register write length
+reg		[`ASIZE-1:0]			rWR2_ADDR;				//Register write address				
+reg		[`ASIZE-1:0]			rWR2_MAX_ADDR;			//Register max write address				
+reg		[8:0]					rWR2_LENGTH;			//Register write length
+reg		[`ASIZE-1:0]			rRD1_ADDR;				//Register read address
+reg		[`ASIZE-1:0]			rRD1_MAX_ADDR;			//Register max read address
+reg		[8:0]					rRD1_LENGTH;			//Register read length
+reg		[`ASIZE-1:0]			rRD2_ADDR;				//Register read address
+reg		[`ASIZE-1:0]			rRD2_MAX_ADDR;			//Register max read address
+reg		[8:0]					rRD2_LENGTH;			//Register read length
+reg		[1:0]					WR_MASK;				//Write port active mask
+reg		[1:0]					RD_MASK;				//Read port active mask
+reg								mWR_DONE;				//Flag write done, 1 pulse SDR_CLK
+reg								mRD_DONE;				//Flag read done, 1 pulse SDR_CLK
+reg								mWR,Pre_WR;				//Internal WR edge capture
+reg								mRD,Pre_RD;				//Internal RD edge capture
+reg 	[9:0] 					ST;						//Controller status
+reg		[1:0] 					CMD;					//Controller command
+reg								PM_STOP;				//Flag page mode stop
+reg								PM_DONE;				//Flag page mode done
+reg								Read;					//Flag read active
+reg								Write;					//Flag write active
+reg	    [`DSIZE-1:0]           	mDATAOUT;               //Controller Data output
+wire    [`DSIZE-1:0]           	mDATAIN;                //Controller Data input
+wire    [`DSIZE-1:0]           	mDATAIN1;                //Controller Data input 1
+wire    [`DSIZE-1:0]           	mDATAIN2;                //Controller Data input 2
+wire                          	CMDACK;                 //Controller command acknowledgement
+//	DRAM Control
+reg  	[`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
+reg     [11:0]                  SA;                     //SDRAM address output
+reg     [1:0]                   BA;                     //SDRAM bank address
+reg     [1:0]                   CS_N;                   //SDRAM Chip Selects
+reg                             CKE;                    //SDRAM clock enable
+reg                             RAS_N;                  //SDRAM Row address Strobe
+reg                             CAS_N;                  //SDRAM Column address Strobe
+reg                             WE_N;                   //SDRAM write enable
+wire    [`DSIZE-1:0]            DQOUT;					//SDRAM data out link
+wire  	[`DSIZE/8-1:0]          IDQM;                   //SDRAM data mask lines
+wire    [11:0]                  ISA;                    //SDRAM address output
+wire    [1:0]                   IBA;                    //SDRAM bank address
+wire    [1:0]                   ICS_N;                  //SDRAM Chip Selects
+wire                            ICKE;                   //SDRAM clock enable
+wire                            IRAS_N;                 //SDRAM Row address Strobe
+wire                            ICAS_N;                 //SDRAM Column address Strobe
+wire                            IWE_N;                  //SDRAM write enable
+//	FIFO Control
+reg								OUT_VALID;				//Output data request to read side fifo
+reg								IN_REQ;					//Input	data request to write side fifo
+wire	[8:0]					write_side_fifo_rusedw1;
+wire	[8:0]					read_side_fifo_wusedw1;
+wire	[8:0]					write_side_fifo_rusedw2;
+wire	[8:0]					read_side_fifo_wusedw2;
+//	DRAM Internal Control
+wire    [`ASIZE-1:0]            saddr;
+wire                            load_mode;
+wire                            nop;
+wire                            reada;
+wire                            writea;
+wire                            refresh;
+wire                            precharge;
+wire                            oe;
+wire							ref_ack;
+wire							ref_req;
+wire							init_req;
+wire							cm_ack;
+wire							active;
+wire                            CLK;
+wire							CCD_CLK;
+
+control_interface control1 (
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .CMD(CMD),
+                .ADDR(mADDR),
+                .REF_ACK(ref_ack),
+                .CM_ACK(cm_ack),
+                .NOP(nop),
+                .READA(reada),
+                .WRITEA(writea),
+                .REFRESH(refresh),
+                .PRECHARGE(precharge),
+                .LOAD_MODE(load_mode),
+                .SADDR(saddr),
+                .REF_REQ(ref_req),
+				.INIT_REQ(init_req),
+                .CMD_ACK(CMDACK)
+                );
+
+command command1(
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .SADDR(saddr),
+                .NOP(nop),
+                .READA(reada),
+                .WRITEA(writea),
+                .REFRESH(refresh),
+				.LOAD_MODE(load_mode),
+                .PRECHARGE(precharge),
+                .REF_REQ(ref_req),
+				.INIT_REQ(init_req),
+                .REF_ACK(ref_ack),
+                .CM_ACK(cm_ack),
+                .OE(oe),
+				.PM_STOP(PM_STOP),
+				.PM_DONE(PM_DONE),
+                .SA(ISA),
+                .BA(IBA),
+                .CS_N(ICS_N),
+                .CKE(ICKE),
+                .RAS_N(IRAS_N),
+                .CAS_N(ICAS_N),
+                .WE_N(IWE_N)
+                );
+                
+sdr_data_path data_path1(
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .DATAIN(mDATAIN),
+                .DM(2'b00),
+                .DQOUT(DQOUT),
+                .DQM(IDQM)
+                );
+
+Sdram_FIFO 	write_fifo1(
+				.data(WR1_DATA),
+				.wrreq(WR1),
+				.wrclk(WR1_CLK),
+				.aclr(WR1_LOAD),
+				.rdreq(IN_REQ&WR_MASK[0]),
+				.rdclk(CLK),
+				.q(mDATAIN1),
+				.rdusedw(write_side_fifo_rusedw1)
+				);
+
+Sdram_FIFO 	write_fifo2(
+				.data(WR2_DATA),
+				.wrreq(WR2),
+				.wrclk(WR2_CLK),
+				.aclr(WR2_LOAD),
+				.rdreq(IN_REQ&WR_MASK[1]),
+				.rdclk(CLK),
+				.q(mDATAIN2),
+				.rdusedw(write_side_fifo_rusedw2)
+				);
+				
+assign	mDATAIN	=	(WR_MASK[0])	?	mDATAIN1	:
+										mDATAIN2	;
+
+Sdram_FIFO 	read_fifo1(
+				.data(mDATAOUT),
+				.wrreq(OUT_VALID&RD_MASK[0]),
+				.wrclk(CLK),
+				.aclr(RD1_LOAD),
+				.rdreq(RD1),
+				.rdclk(RD1_CLK),
+				.q(RD1_DATA),
+				.wrusedw(read_side_fifo_wusedw1)
+				);
+				
+Sdram_FIFO 	read_fifo2(
+				.data(mDATAOUT),
+				.wrreq(OUT_VALID&RD_MASK[1]),
+				.wrclk(CLK),
+				.aclr(RD2_LOAD),
+				.rdreq(RD2),
+				.rdclk(RD2_CLK),
+				.q(RD2_DATA),
+				.wrusedw(read_side_fifo_wusedw2)
+				);
+
+always @(posedge CLK)
+begin
+	SA      <= (ST==SC_CL+mLENGTH)			?	12'h200	:	ISA;
+    BA      <= IBA;
+    CS_N    <= ICS_N;
+    CKE     <= ICKE;
+    RAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IRAS_N;
+    CAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b1	:	ICAS_N;
+    WE_N    <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IWE_N;
+	PM_STOP	<= (ST==SC_CL+mLENGTH)			?	1'b1	:	1'b0;
+	PM_DONE	<= (ST==SC_CL+SC_RCD+mLENGTH+2)	?	1'b1	:	1'b0;
+	DQM		<= ( active && (ST>=SC_CL) )	?	(	((ST==SC_CL+mLENGTH) && Write)?	2'b11	:	2'b00	)	:	2'b11	;
+	mDATAOUT<= DQ;
+end
+
+assign  DQ = oe ? DQOUT : `DSIZE'hzzzz;
+assign	active	=	Read | Write;
+
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(RESET_N==0)
+	begin
+		CMD			<=  0;
+		ST			<=  0;
+		Pre_RD		<=  0;
+		Pre_WR		<=  0;
+		Read		<=	0;
+		Write		<=	0;
+		OUT_VALID	<=	0;
+		IN_REQ		<=	0;
+		mWR_DONE	<=	0;
+		mRD_DONE	<=	0;
+	end
+	else
+	begin
+		Pre_RD	<=	mRD;
+		Pre_WR	<=	mWR;
+		case(ST)
+		0:	begin
+				if({Pre_RD,mRD}==2'b01)
+				begin
+					Read	<=	1;
+					Write	<=	0;
+					CMD		<=	2'b01;
+					ST		<=	1;
+				end
+				else if({Pre_WR,mWR}==2'b01)
+				begin
+					Read	<=	0;
+					Write	<=	1;
+					CMD		<=	2'b10;
+					ST		<=	1;
+				end
+			end
+		1:	begin
+				if(CMDACK==1)
+				begin
+					CMD<=2'b00;
+					ST<=2;
+				end
+			end
+		default:	
+			begin	
+				if(ST!=SC_CL+SC_RCD+mLENGTH+1)
+				ST<=ST+1;
+				else
+				ST<=0;
+			end
+		endcase
+	
+		if(Read)
+		begin
+			if(ST==SC_CL+SC_RCD+1)
+			OUT_VALID	<=	1;
+			else if(ST==SC_CL+SC_RCD+mLENGTH+1)
+			begin
+				OUT_VALID	<=	0;
+				Read		<=	0;
+				mRD_DONE	<=	1;
+			end
+		end
+		else
+		mRD_DONE	<=	0;
+		
+		if(Write)
+		begin
+			if(ST==SC_CL-1)
+			IN_REQ	<=	1;
+			else if(ST==SC_CL+mLENGTH-1)
+			IN_REQ	<=	0;
+			else if(ST==SC_CL+SC_RCD+mLENGTH)
+			begin
+				Write	<=	0;
+				mWR_DONE<=	1;
+			end
+		end
+		else
+		mWR_DONE<=	0;
+
+	end
+end
+//	Internal Address & Length Control
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(!RESET_N)
+	begin
+		rWR1_ADDR		<=	0;
+		rWR2_ADDR		<=	22'h100000;
+		rRD1_ADDR		<=	0;
+		rRD2_ADDR		<=	22'h100000;
+		rWR1_MAX_ADDR	<=	640*480;
+		rWR2_MAX_ADDR	<=	22'h100000+640*480;
+		rRD1_MAX_ADDR	<=	640*480;
+		rRD2_MAX_ADDR	<=	22'h100000+640*480;
+		rWR1_LENGTH		<=	256;
+		rWR2_LENGTH		<=	256;
+		rRD1_LENGTH		<=	256;
+		rRD2_LENGTH		<=	256;
+	end
+	else
+	begin
+		//	Write Side 1
+		if(WR1_LOAD)
+		begin
+			rWR1_ADDR	<=	WR1_ADDR;
+			rWR1_LENGTH	<=	WR1_LENGTH;
+		end
+		else if(mWR_DONE&WR_MASK[0])
+		begin
+			if(rWR1_ADDR<rWR1_MAX_ADDR-rWR1_LENGTH)
+				rWR1_ADDR	<=	rWR1_ADDR+rWR1_LENGTH;
+			else
+				rWR1_ADDR	<=	WR1_ADDR;
+		end
+		//	Write Side 2
+		if(WR2_LOAD)
+		begin
+			rWR2_ADDR	<=	WR2_ADDR;
+			rWR2_LENGTH	<=	WR2_LENGTH;
+		end
+		else if(mWR_DONE&WR_MASK[1])
+		begin
+			if(rWR2_ADDR<rWR2_MAX_ADDR-rWR2_LENGTH)
+				rWR2_ADDR	<=	rWR2_ADDR+rWR2_LENGTH;
+			else
+				rWR2_ADDR	<=	WR2_ADDR;
+		end
+		//	Read Side 1
+		if(RD1_LOAD)
+		begin
+			rRD1_ADDR	<=	RD1_ADDR;
+			rRD1_LENGTH	<=	RD1_LENGTH;
+		end
+		else if(mRD_DONE&RD_MASK[0])
+		begin
+			if(rRD1_ADDR<rRD1_MAX_ADDR-rRD1_LENGTH)
+				rRD1_ADDR	<=	rRD1_ADDR+rRD1_LENGTH;
+			else
+				rRD1_ADDR	<=	RD1_ADDR;
+		end
+		//	Read Side 2
+		if(RD2_LOAD)
+		begin
+			rRD2_ADDR	<=	RD2_ADDR;
+			rRD2_LENGTH	<=	RD2_LENGTH;
+		end
+		else if(mRD_DONE&RD_MASK[1])
+		begin
+			if(rRD2_ADDR<rRD2_MAX_ADDR-rRD2_LENGTH)
+				rRD2_ADDR	<=	rRD2_ADDR+rRD2_LENGTH;
+			else
+				rRD2_ADDR	<=	RD2_ADDR;
+		end
+	end
+end
+//	Auto Read/Write Control
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(!RESET_N)
+	begin
+		mWR		<=	0;
+		mRD		<=	0;
+		mADDR	<=	0;
+		mLENGTH	<=	0;
+	end
+	else
+	begin
+		if( (mWR==0) && (mRD==0) && (ST==0) &&
+			(WR_MASK==0)	&&	(RD_MASK==0) &&
+			(WR1_LOAD==0)	&&	(RD1_LOAD==0) &&
+			(WR2_LOAD==0)	&&	(RD2_LOAD==0) )
+		begin
+			//	Write Side 1
+			if( (write_side_fifo_rusedw1 >= rWR1_LENGTH) && (rWR1_LENGTH!=0) )
+			begin
+				mADDR	<=	rWR1_ADDR;
+				mLENGTH	<=	rWR1_LENGTH;
+				WR_MASK	<=	2'b01;
+				RD_MASK	<=	2'b00;
+				mWR		<=	1;
+				mRD		<=	0;
+			end
+			//	Write Side 2
+			else if( (write_side_fifo_rusedw2 >= rWR2_LENGTH) && (rWR2_LENGTH!=0) )
+			begin
+				mADDR	<=	rWR2_ADDR;
+				mLENGTH	<=	rWR2_LENGTH;
+				WR_MASK	<=	2'b10;
+				RD_MASK	<=	2'b00;
+				mWR		<=	1;
+				mRD		<=	0;
+			end
+			//	Read Side 1
+			else if( (read_side_fifo_wusedw1 < rRD1_LENGTH) )
+			begin
+				mADDR	<=	rRD1_ADDR;
+				mLENGTH	<=	rRD1_LENGTH;
+				WR_MASK	<=	2'b00;
+				RD_MASK	<=	2'b01;
+				mWR		<=	0;
+				mRD		<=	1;				
+			end
+			//	Read Side 2
+			else if( (read_side_fifo_wusedw2 < rRD2_LENGTH) )
+			begin
+				mADDR	<=	rRD2_ADDR;
+				mLENGTH	<=	rRD2_LENGTH;
+				WR_MASK	<=	2'b00;
+				RD_MASK	<=	2'b10;
+				mWR		<=	0;
+				mRD		<=	1;
+			end
+		end
+		if(mWR_DONE)
+		begin
+			WR_MASK	<=	0;
+			mWR		<=	0;
+		end
+		if(mRD_DONE)
+		begin
+			RD_MASK	<=	0;
+			mRD		<=	0;
+		end
+	end
+end
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.qip
new file mode 100644
index 0000000..ceca5c0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "10.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Sdram_FIFO.v"]
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.v
new file mode 100644
index 0000000..af2662b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.v
@@ -0,0 +1,190 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: Sdram_FIFO.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 218 06/27/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module Sdram_FIFO (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	rdusedw,
+	wrfull,
+	wrusedw);
+
+	input	  aclr;
+	input	[15:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[15:0]  q;
+	output	  rdempty;
+	output	[8:0]  rdusedw;
+	output	  wrfull;
+	output	[8:0]  wrusedw;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  sub_wire0;
+	wire [15:0] sub_wire1;
+	wire  sub_wire2;
+	wire [8:0] sub_wire3;
+	wire [8:0] sub_wire4;
+	wire  wrfull = sub_wire0;
+	wire [15:0] q = sub_wire1[15:0];
+	wire  rdempty = sub_wire2;
+	wire [8:0] wrusedw = sub_wire3[8:0];
+	wire [8:0] rdusedw = sub_wire4[8:0];
+
+	dcfifo	dcfifo_component (
+				.rdclk (rdclk),
+				.wrclk (wrclk),
+				.wrreq (wrreq),
+				.aclr (aclr),
+				.data (data),
+				.rdreq (rdreq),
+				.wrfull (sub_wire0),
+				.q (sub_wire1),
+				.rdempty (sub_wire2),
+				.wrusedw (sub_wire3),
+				.rdusedw (sub_wire4),
+				.rdfull (),
+				.wrempty ());
+	defparam
+		dcfifo_component.add_ram_output_register = "OFF",
+		dcfifo_component.clocks_are_synchronized = "FALSE",
+		dcfifo_component.intended_device_family = "Cyclone",
+		dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
+		dcfifo_component.lpm_numwords = 512,
+		dcfifo_component.lpm_showahead = "OFF",
+		dcfifo_component.lpm_type = "dcfifo",
+		dcfifo_component.lpm_width = 16,
+		dcfifo_component.lpm_widthu = 9,
+		dcfifo_component.overflow_checking = "ON",
+		dcfifo_component.underflow_checking = "ON",
+		dcfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "512"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_wave*.jpg FALSE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Params.h b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Params.h
new file mode 100644
index 0000000..59b473c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Params.h
@@ -0,0 +1,60 @@
+// Address Space Parameters
+
+`define ROWSTART        8          
+`define ROWSIZE         12
+`define COLSTART        0
+`define COLSIZE         8
+`define BANKSTART       20
+`define BANKSIZE        2
+
+// Address and Data Bus Sizes
+
+`define  ASIZE           23      // total address width of the SDRAM
+`define  DSIZE           16      // Width of data bus to SDRAMS
+
+//parameter	INIT_PER	=	100;		//	For Simulation
+
+//	Controller Parameter
+////////////	133 MHz	///////////////
+/*
+parameter	INIT_PER	=	32000;
+parameter	REF_PER		=	1536;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+////////////	100 MHz	///////////////
+parameter	INIT_PER	=	24000;
+parameter	REF_PER		=	1024;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+///////////////////////////////////////
+////////////	50 MHz	///////////////
+/*
+parameter	INIT_PER	=	12000;
+parameter	REF_PER		=	512;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+
+//	SDRAM Parameter
+parameter	SDR_BL		=	(SC_PM == 1)?	3'b111	:
+							(SC_BL == 1)?	3'b000	:
+							(SC_BL == 2)?	3'b001	:
+							(SC_BL == 4)?	3'b010	:
+											3'b011	;
+parameter	SDR_BT		=	1'b0;	//	Sequential
+							//	1'b1:	//	Interteave
+parameter	SDR_CL		=	(SC_CL == 2)?	3'b10:
+											3'b11;
+ 	
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/command.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/command.v
new file mode 100644
index 0000000..8b37dff
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/command.v
@@ -0,0 +1,482 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	command
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module command(
+        CLK,
+        RESET_N,
+        SADDR,
+        NOP,
+        READA,
+        WRITEA,
+        REFRESH,
+        PRECHARGE,
+        LOAD_MODE,
+        REF_REQ,
+		INIT_REQ,
+		PM_STOP,
+		PM_DONE,
+        REF_ACK,
+        CM_ACK,
+        OE,
+        SA,
+        BA,
+        CS_N,
+        CKE,
+        RAS_N,
+        CAS_N,
+        WE_N
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [`ASIZE-1:0]            SADDR;                  // Address
+input                           NOP;                    // Decoded NOP command
+input                           READA;                  // Decoded READA command
+input                           WRITEA;                 // Decoded WRITEA command
+input                           REFRESH;                // Decoded REFRESH command
+input                           PRECHARGE;              // Decoded PRECHARGE command
+input                           LOAD_MODE;              // Decoded LOAD_MODE command
+input                           REF_REQ;                // Hidden refresh request
+input							INIT_REQ;				// Hidden initial request
+input							PM_STOP;				// Page mode stop
+input							PM_DONE;				// Page mode done
+output                          REF_ACK;                // Refresh request acknowledge
+output                          CM_ACK;                 // Command acknowledge
+output                          OE;                     // OE signal for data path module
+output  [11:0]                  SA;                     // SDRAM address
+output  [1:0]                   BA;                     // SDRAM bank address
+output  [1:0]                   CS_N;                   // SDRAM chip selects
+output                          CKE;                    // SDRAM clock enable
+output                          RAS_N;                  // SDRAM RAS
+output                          CAS_N;                  // SDRAM CAS
+output                          WE_N;                   // SDRAM WE_N
+            
+reg                             CM_ACK;
+reg                             REF_ACK;
+reg                             OE;
+reg     [11:0]                  SA;
+reg     [1:0]                   BA;
+reg     [1:0]                   CS_N;
+reg                             CKE;
+reg                             RAS_N;
+reg                             CAS_N;
+reg                             WE_N;
+
+// Internal signals
+reg                             do_reada;
+reg                             do_writea;
+reg                             do_refresh;
+reg                             do_precharge;
+reg                             do_load_mode;
+reg								do_initial;
+reg                             command_done;
+reg     [7:0]                   command_delay;
+reg     [1:0]                   rw_shift;
+reg                             do_act;
+reg                             rw_flag;
+reg                             do_rw;
+reg     [6:0]                   oe_shift;
+reg                             oe1;
+reg                             oe2;
+reg                             oe3;
+reg                             oe4;
+reg     [3:0]                   rp_shift;
+reg                             rp_done;
+reg								ex_read;
+reg								ex_write;
+
+wire    [`ROWSIZE - 1:0]        rowaddr;
+wire    [`COLSIZE - 1:0]        coladdr;
+wire    [`BANKSIZE - 1:0]       bankaddr;
+
+assign   rowaddr   = SADDR[`ROWSTART + `ROWSIZE - 1: `ROWSTART];          // assignment of the row address bits from SADDR
+assign   coladdr   = SADDR[`COLSTART + `COLSIZE - 1:`COLSTART];           // assignment of the column address bits
+assign   bankaddr  = SADDR[`BANKSTART + `BANKSIZE - 1:`BANKSTART];        // assignment of the bank address bits
+
+// This always block monitors the individual command lines and issues a command
+// to the next stage if there currently another command already running.
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+        begin
+                do_reada        <= 0;
+                do_writea       <= 0;
+                do_refresh      <= 0;
+                do_precharge    <= 0;
+                do_load_mode    <= 0;
+				do_initial		<= 0;
+                command_done    <= 0;
+                command_delay   <= 0;
+                rw_flag         <= 0;
+                rp_shift        <= 0;
+                rp_done         <= 0;
+				ex_read			<= 0;
+				ex_write		<= 0;
+        end
+        
+        else
+        begin
+
+//  Issue the appropriate command if the sdram is not currently busy
+			if( INIT_REQ == 1 )
+			begin
+                do_reada        <= 0;
+                do_writea       <= 0;
+                do_refresh      <= 0;
+                do_precharge    <= 0;
+                do_load_mode    <= 0;
+				do_initial		<= 1;
+                command_done    <= 0;
+                command_delay   <= 0;
+                rw_flag         <= 0;
+                rp_shift        <= 0;
+                rp_done         <= 0;
+				ex_read			<= 0;
+				ex_write		<= 0;
+			end
+			else
+			begin
+				do_initial		<= 0;
+				
+                if ((REF_REQ == 1 | REFRESH == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0         // Refresh
+                        & do_reada == 0 & do_writea == 0)
+                        do_refresh <= 1;         
+                else
+                        do_refresh <= 0;
+
+                if ((READA == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (REF_REQ == 0))    // READA
+                begin
+				        do_reada <= 1;
+						ex_read <= 1;
+				end
+                else
+                        do_reada <= 0;
+                    
+                if ((WRITEA == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (REF_REQ == 0))  // WRITEA
+                begin
+				        do_writea <= 1;
+						ex_write <= 1;
+				end
+                else
+                        do_writea <= 0;
+
+                if ((PRECHARGE == 1) & (command_done == 0) & (do_precharge == 0))	// PRECHARGE
+                        do_precharge <= 1;
+                else
+                        do_precharge <= 0;
+ 
+                if ((LOAD_MODE == 1) & (command_done == 0) & (do_load_mode == 0))	// LOADMODE
+                        do_load_mode <= 1;
+                else
+                        do_load_mode <= 0;
+                                               
+// set command_delay shift register and command_done flag
+// The command delay shift register is a timer that is used to ensure that
+// the SDRAM devices have had sufficient time to finish the last command.
+
+                if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)
+                     | (do_load_mode == 1))
+                begin
+                        command_delay <= 8'b11111111;
+                        command_done  <= 1;
+                        rw_flag <= do_reada;                                                  
+                end
+                
+                else
+                begin
+                        command_done        <= command_delay[0];                // the command_delay shift operation
+                        command_delay		<= (command_delay>>1);
+                end 
+                
+ 
+ // start additional timer that is used for the refresh, writea, reada commands               
+                if (command_delay[0] == 0 & command_done == 1)
+                begin
+                	rp_shift <= 4'b1111;
+                	rp_done <= 1;
+                end
+                else
+                begin						
+					if(SC_PM == 0)
+					begin
+						rp_shift	<= (rp_shift>>1);
+                    	rp_done		<= rp_shift[0];
+					end
+					else
+					begin
+						if( (ex_read == 0) && (ex_write == 0) )
+						begin
+							rp_shift	<= (rp_shift>>1);
+        	            	rp_done		<= rp_shift[0];
+						end
+						else
+						begin
+							if( PM_STOP==1 )
+							begin
+								rp_shift	<= (rp_shift>>1);
+        	      		      	rp_done     <= rp_shift[0];
+								ex_read		<= 1'b0;
+								ex_write	<= 1'b0;
+							end					
+						end
+					end
+                end
+			end
+        end
+end
+
+
+// logic that generates the OE signal for the data path module
+// For normal burst write he duration of OE is dependent on the configured burst length.
+// For page mode accesses(SC_PM=1) the OE signal is turned on at the start of the write command
+// and is left on until a PRECHARGE(page burst terminate) is detected.
+//
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+        begin
+                oe_shift <= 0;
+                oe1      <= 0;
+                oe2      <= 0;
+                OE       <= 0;
+        end
+        else
+        begin
+                if (SC_PM == 0)
+                begin
+                        if (do_writea == 1)
+                        begin
+                                if (SC_BL == 1)				//  Set the shift register to the appropriate
+                                        oe_shift <= 0;		// value based on burst length.
+                                else if (SC_BL == 2)
+                                        oe_shift <= 1;
+                                else if (SC_BL == 4)
+                                        oe_shift <= 7;
+                                else if (SC_BL == 8)
+                                        oe_shift <= 127;
+                                oe1 <= 1;
+                        end
+                        else 
+                        begin
+                                oe_shift <= (oe_shift>>1);
+                                oe1  <= oe_shift[0];
+                                oe2  <= oe1;
+                                oe3  <= oe2;
+                                oe4  <= oe3;
+                                if (SC_RCD == 2)
+                                        OE <= oe3;
+                                else
+                                        OE <= oe4;
+                        end
+                end
+                else
+                begin
+                        if (do_writea == 1)					 // OE generation for page mode accesses
+                                oe4   <= 1;
+                        else if (do_precharge == 1 | do_reada == 1 | do_refresh==1 | do_initial == 1 | PM_STOP==1 )
+                                oe4   <= 0;
+                        OE <= oe4;
+                end
+                               
+        end
+end
+
+
+
+
+// This always block tracks the time between the activate command and the
+// subsequent WRITEA or READA command, RC.  The shift register is set using
+// the configuration register setting SC_RCD. The shift register is loaded with
+// a single '1' with the position within the register dependent on SC_RCD.
+// When the '1' is shifted out of the register it sets so_rw which triggers
+// a writea or reada command
+//
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+        begin
+                rw_shift <= 0;
+                do_rw    <= 0;
+        end
+        
+        else
+        begin
+                
+                if ((do_reada == 1) | (do_writea == 1))
+                begin
+                        if (SC_RCD == 1)                          // Set the shift register
+                                do_rw <= 1;
+                        else if (SC_RCD == 2)
+                                rw_shift <= 1;
+                        else if (SC_RCD == 3)
+                                rw_shift <= 2;
+                end
+                else
+                begin
+                        rw_shift <= (rw_shift>>1);
+                        do_rw    <= rw_shift[0];
+                end 
+        end
+end              
+
+// This always block generates the command acknowledge, CM_ACK, signal.
+// It also generates the acknowledge signal, REF_ACK, that acknowledges
+// a refresh request that was generated by the internal refresh timer circuit.
+always @(posedge CLK or negedge RESET_N) 
+begin
+
+        if (RESET_N == 0) 
+        begin
+                CM_ACK   <= 0;
+                REF_ACK  <= 0;
+        end
+        
+        else
+        begin
+                if (do_refresh == 1 & REF_REQ == 1)                   // Internal refresh timer refresh request
+                        REF_ACK <= 1;
+                else if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)   // externa  commands
+                         | (do_load_mode))
+                        CM_ACK <= 1;
+                else
+                begin
+                        REF_ACK <= 0;
+                        CM_ACK  <= 0;
+                end
+        end
+end 
+                    
+
+
+
+
+
+
+// This always block generates the address, cs, cke, and command signals(ras,cas,wen)
+// 
+always @(posedge CLK ) begin
+        if (RESET_N==0) begin
+                SA    <= 0;
+                BA    <= 0;
+                CS_N  <= 1;
+                RAS_N <= 1;
+                CAS_N <= 1;
+                WE_N  <= 1;
+                CKE   <= 0;
+        end
+        else begin
+                CKE <= 1;
+
+// Generate SA 	
+                if (do_writea == 1 | do_reada == 1)    // ACTIVATE command is being issued, so present the row address
+                        SA <= rowaddr;
+                else
+                        SA <= coladdr;                 // else alway present column address
+                if ((do_rw==1) | (do_precharge))
+                        SA[10] <= !SC_PM;              // set SA[10] for autoprecharge read/write or for a precharge all command
+                                                       // don't set it if the controller is in page mode.           
+                if (do_precharge==1 | do_load_mode==1)
+                        BA <= 0;                       // Set BA=0 if performing a precharge or load_mode command
+                else
+                        BA <= bankaddr[1:0];           // else set it with the appropriate address bits
+		
+                if (do_refresh==1 | do_precharge==1 | do_load_mode==1 | do_initial==1)
+                        CS_N <= 0;                                    // Select both chip selects if performing
+                else                                                  // refresh, precharge(all) or load_mode
+                begin
+                        CS_N[0] <= SADDR[`ASIZE-1];                   // else set the chip selects based off of the
+                        CS_N[1] <= ~SADDR[`ASIZE-1];                  // msb address bit
+                end
+				
+				if(do_load_mode==1)
+				SA	  <= {2'b00,SDR_CL,SDR_BT,SDR_BL};
+
+
+//Generate the appropriate logic levels on RAS_N, CAS_N, and WE_N
+//depending on the issued command.
+//		
+                if ( do_refresh==1 ) begin                        // Refresh: S=00, RAS=0, CAS=0, WE=1
+                        RAS_N <= 0;
+                        CAS_N <= 0;
+                        WE_N  <= 1;
+                end
+                else if ((do_precharge==1) & ((oe4 == 1) | (rw_flag == 1))) begin      // burst terminate if write is active
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 0;
+                end
+                else if (do_precharge==1) begin                 // Precharge All: S=00, RAS=0, CAS=1, WE=0
+                        RAS_N <= 0;
+                        CAS_N <= 1;
+                        WE_N  <= 0;
+                end
+                else if (do_load_mode==1) begin                 // Mode Write: S=00, RAS=0, CAS=0, WE=0
+                        RAS_N <= 0;
+                        CAS_N <= 0;
+                        WE_N  <= 0;
+                end
+                else if (do_reada == 1 | do_writea == 1) begin  // Activate: S=01 or 10, RAS=0, CAS=1, WE=1
+                        RAS_N <= 0;
+                        CAS_N <= 1;
+                        WE_N  <= 1;
+                end
+                else if (do_rw == 1) begin                      // Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1
+                        RAS_N <= 1;
+                        CAS_N <= 0;
+                        WE_N  <= rw_flag;
+                end
+				else if (do_initial ==1) begin
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 1;				
+				end
+                else begin                                      // No Operation: RAS=1, CAS=1, WE=1
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 1;
+                end
+        end 
+end
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/control_interface.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/control_interface.v
new file mode 100644
index 0000000..d7930e2
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/control_interface.v
@@ -0,0 +1,240 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	control_interface
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module control_interface(
+        CLK,
+        RESET_N,
+        CMD,
+        ADDR,
+        REF_ACK,
+		INIT_ACK,
+        CM_ACK,
+        NOP,
+        READA,
+        WRITEA,
+        REFRESH,
+        PRECHARGE,
+        LOAD_MODE,
+        SADDR,
+        REF_REQ,
+		INIT_REQ,
+        CMD_ACK
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [2:0]                   CMD;                    // Command input
+input   [`ASIZE-1:0]            ADDR;                   // Address
+input                           REF_ACK;                // Refresh request acknowledge
+input							INIT_ACK;				// Initial request acknowledge
+input                           CM_ACK;                 // Command acknowledge
+output                          NOP;                    // Decoded NOP command
+output                          READA;                  // Decoded READA command
+output                          WRITEA;                 // Decoded WRITEA command
+output                          REFRESH;                // Decoded REFRESH command
+output                          PRECHARGE;              // Decoded PRECHARGE command
+output                          LOAD_MODE;              // Decoded LOAD_MODE command
+output  [`ASIZE-1:0]            SADDR;                  // Registered version of ADDR
+output                          REF_REQ;                // Hidden refresh request
+output                          INIT_REQ;               // Hidden initial request
+output                          CMD_ACK;                // Command acknowledge
+
+
+            
+reg                             NOP;
+reg                             READA;
+reg                             WRITEA;
+reg                             REFRESH;
+reg                             PRECHARGE;
+reg                             LOAD_MODE;
+reg     [`ASIZE-1:0]            SADDR;
+reg                             REF_REQ;
+reg                             INIT_REQ;
+reg                             CMD_ACK;
+
+// Internal signals
+reg     [15:0]                  timer;
+reg		[15:0]					init_timer;
+
+
+
+// Command decode and ADDR register
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+        begin
+                NOP             <= 0;
+                READA           <= 0;
+                WRITEA          <= 0;
+                SADDR           <= 0;
+        end
+        
+        else
+        begin
+        
+                SADDR <= ADDR;                                  // register the address to keep proper
+                                                                // alignment with the command
+                                                             
+                if (CMD == 3'b000)                              // NOP command
+                        NOP <= 1;
+                else
+                        NOP <= 0;
+                        
+                if (CMD == 3'b001)                              // READA command
+                        READA <= 1;
+                else
+                        READA <= 0;
+                 
+                if (CMD == 3'b010)                              // WRITEA command
+                        WRITEA <= 1;
+                else
+                        WRITEA <= 0;
+                        
+        end
+end
+
+
+//  Generate CMD_ACK
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+                CMD_ACK <= 0;
+        else
+                if ((CM_ACK == 1) & (CMD_ACK == 0))
+                        CMD_ACK <= 1;
+                else
+                        CMD_ACK <= 0;
+end
+
+
+// refresh timer
+always @(posedge CLK or negedge RESET_N) begin
+        if (RESET_N == 0) 
+        begin
+                timer           <= 0;
+                REF_REQ         <= 0;
+        end        
+        else 
+        begin
+                if (REF_ACK == 1)
+				begin
+                	timer <= REF_PER;
+					REF_REQ	<=0;
+				end
+				else if (INIT_REQ == 1)
+				begin
+                	timer <= REF_PER+200;
+					REF_REQ	<=0;					
+				end
+                else
+                	timer <= timer - 1'b1;
+
+                if (timer==0)
+                    REF_REQ    <= 1;
+
+        end
+end
+
+// initial timer
+always @(posedge CLK or negedge RESET_N) begin
+        if (RESET_N == 0) 
+        begin
+                init_timer      <= 0;
+				REFRESH         <= 0;
+                PRECHARGE      	<= 0; 
+				LOAD_MODE		<= 0;
+				INIT_REQ		<= 0;
+        end        
+        else 
+        begin
+                if (init_timer < (INIT_PER+201))
+					init_timer 	<= init_timer+1;
+					
+				if (init_timer < INIT_PER)
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=1;
+				end
+				else if(init_timer == (INIT_PER+20))
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=1;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;
+				end
+				else if( 	(init_timer == (INIT_PER+40))	||
+							(init_timer == (INIT_PER+60))	||
+							(init_timer == (INIT_PER+80))	||
+							(init_timer == (INIT_PER+100))	||
+							(init_timer == (INIT_PER+120))	||
+							(init_timer == (INIT_PER+140))	||
+							(init_timer == (INIT_PER+160))	||
+							(init_timer == (INIT_PER+180))	)
+				begin
+					REFRESH		<=1;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;
+				end
+				else if(init_timer == (INIT_PER+200))
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=1;
+					INIT_REQ	<=0;				
+				end
+				else
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;									
+				end
+        end
+end
+
+endmodule
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/sdr_data_path.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/sdr_data_path.v
new file mode 100644
index 0000000..b064bbe
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/sdr_data_path.v
@@ -0,0 +1,76 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	sdr_data_path
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module sdr_data_path(
+        CLK,
+        RESET_N,
+        DATAIN,
+        DM,
+        DQOUT,
+        DQM
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [`DSIZE-1:0]            DATAIN;                 // Data input from the host
+input   [`DSIZE/8-1:0]          DM;                     // byte data masks
+output  [`DSIZE-1:0]            DQOUT;
+output  [`DSIZE/8-1:0]          DQM;                    // SDRAM data mask ouputs
+reg     [`DSIZE/8-1:0]          DQM;
+            
+
+
+// Allign the input and output data to the SDRAM control path
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+		DQM		<= `DSIZE/8-1'hF;
+        else
+ 		DQM		<=	DM;                 
+end
+
+assign DQOUT = DATAIN;
+
+endmodule
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_FIFO.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_FIFO.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_FIFO.qip
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/TOP_CAMERA.bdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/TOP_CAMERA.bdf
new file mode 100644
index 0000000..f33dd49
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/TOP_CAMERA.bdf
@@ -0,0 +1,875 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
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+	(pt 928 280)
+	(pt 1024 280)
+)
+(connector
+	(pt 928 296)
+	(pt 1024 296)
+)
+(connector
+	(pt 928 312)
+	(pt 1024 312)
+)
+(connector
+	(pt 928 328)
+	(pt 1024 328)
+)
+(connector
+	(pt 928 344)
+	(pt 1024 344)
+)
+(connector
+	(pt 928 360)
+	(pt 1024 360)
+)
+(connector
+	(pt 928 376)
+	(pt 1024 376)
+)
+(connector
+	(pt 928 392)
+	(pt 1024 392)
+)
+(connector
+	(pt 928 408)
+	(pt 1024 408)
+)
+(connector
+	(pt 928 424)
+	(pt 1024 424)
+)
+(connector
+	(text "VGA_HS" (rect 938 424 981 436)(font "Arial" ))
+	(pt 928 440)
+	(pt 1008 440)
+)
+(connector
+	(text "VGA_VS" (rect 938 440 980 452)(font "Arial" ))
+	(pt 928 456)
+	(pt 1008 456)
+)
+(connector
+	(text "VGA_CLK" (rect 938 504 987 516)(font "Arial" ))
+	(pt 928 520)
+	(pt 1112 520)
+)
+(connector
+	(pt 928 536)
+	(pt 1024 536)
+	(bus)
+)
+(connector
+	(pt 928 552)
+	(pt 1024 552)
+	(bus)
+)
+(connector
+	(text "VGA_R[3..0]" (rect 938 456 1000 468)(font "Arial" ))
+	(pt 928 472)
+	(pt 1136 472)
+	(bus)
+)
+(connector
+	(text "VGA_G[3..0]" (rect 938 472 1000 484)(font "Arial" ))
+	(pt 928 488)
+	(pt 1136 488)
+	(bus)
+)
+(connector
+	(text "VGA_B[3..0]" (rect 938 488 999 500)(font "Arial" ))
+	(pt 928 504)
+	(pt 1136 504)
+	(bus)
+)
+(text "CLOCK_50" (rect 506 152 561 164)(font "Arial" ))
+(text "KEY[2..0]" (rect 506 168 554 180)(font "Arial" ))
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/CCD_Capture.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/CCD_Capture.v
new file mode 100644
index 0000000..338ae75
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/CCD_Capture.v
@@ -0,0 +1,186 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	D5M CCD_Capture
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module CCD_Capture(	oDATA,
+					oDVAL,
+					oX_Cont,
+					oY_Cont,
+					oFrame_Cont,
+					iDATA,
+					iFVAL,
+					iLVAL,
+					iSTART,
+					iEND,
+					iCLK,
+					iRST
+					);
+					
+input	[11:0]	iDATA;
+input			iFVAL;
+input			iLVAL;
+input			iSTART;
+input			iEND;
+input			iCLK;
+input			iRST;
+output	[11:0]	oDATA;
+output	[15:0]	oX_Cont;
+output	[15:0]	oY_Cont;
+output	[31:0]	oFrame_Cont;
+output			oDVAL;
+reg				Pre_FVAL;
+reg				mCCD_FVAL;
+reg				mCCD_LVAL;
+reg		[11:0]	mCCD_DATA;
+reg		[15:0]	X_Cont;
+reg		[15:0]	Y_Cont;
+reg		[31:0]	Frame_Cont;
+reg				mSTART;
+
+parameter COLUMN_WIDTH = 1280;
+
+assign	oX_Cont		=	X_Cont;
+assign	oY_Cont		=	Y_Cont;
+assign	oFrame_Cont	=	Frame_Cont;
+assign	oDATA		=	mCCD_DATA;
+assign	oDVAL		=	mCCD_FVAL&mCCD_LVAL;
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	mSTART	<=	0;
+	else
+	begin
+		if(iSTART)
+		mSTART	<=	1;
+		if(iEND)
+		mSTART	<=	0;		
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		Pre_FVAL	<=	0;
+		mCCD_FVAL	<=	0;
+		mCCD_LVAL	<=	0;
+
+		X_Cont		<=	0;
+		Y_Cont		<=	0;
+	end
+	else
+	begin
+		Pre_FVAL	<=	iFVAL;
+		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
+		mCCD_FVAL	<=	1;
+		else if({Pre_FVAL,iFVAL}==2'b10)
+		mCCD_FVAL	<=	0;
+		mCCD_LVAL	<=	iLVAL;
+		if(mCCD_FVAL)
+		begin
+			if(mCCD_LVAL)
+			begin
+				if(X_Cont<(COLUMN_WIDTH-1))
+				X_Cont	<=	X_Cont+1;
+				else
+				begin
+					X_Cont	<=	0;
+					Y_Cont	<=	Y_Cont+1;
+				end
+			end
+		end
+		else
+		begin
+			X_Cont	<=	0;
+			Y_Cont	<=	0;
+		end
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	Frame_Cont	<=	0;
+	else
+	begin
+		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
+		Frame_Cont	<=	Frame_Cont+1;
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		mCCD_DATA	<=	0;
+	else if (iLVAL)
+		mCCD_DATA	<=	iDATA;
+	else
+		mCCD_DATA	<=	0;	
+end			
+
+reg	ifval_dealy;
+
+wire ifval_fedge;	
+reg	[15:0]	y_cnt_d;
+
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		y_cnt_d	<=	0;
+	else
+		y_cnt_d	<=	Y_Cont;	
+end
+
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		ifval_dealy	<=	0;
+	else
+		ifval_dealy	<=	iFVAL;	
+end
+
+assign ifval_fedge = ({ifval_dealy,iFVAL}==2'b10)?1:0;  
+
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v
new file mode 100644
index 0000000..11d3a70
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v
@@ -0,0 +1,287 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	I2C_CCD_Config
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 16/03/14  :| CCD config, spelling
+// --------------------------------------------------------------------
+
+module I2C_CCD_Config (	//	Host Side
+						iCLK,
+						iRST_N,
+						iUART_CTRL,
+						iZOOM_MODE_SW,
+						iEXPOSURE_ADJ,
+						iEXPOSURE_DEC_p,
+						//	I2C Side
+						I2C_SCLK,
+						I2C_SDAT
+						);
+						
+//	Host Side
+input			iCLK;
+input			iRST_N;
+input 			iUART_CTRL;
+input 			iZOOM_MODE_SW;
+
+//	I2C Side
+output		I2C_SCLK;
+inout		I2C_SDAT;
+
+//	Internal Registers/Wires
+reg	[15:0]	mI2C_CLK_DIV;
+reg	[31:0]	mI2C_DATA;
+reg			mI2C_CTRL_CLK;
+reg			mI2C_GO;
+wire		mI2C_END;
+wire		mI2C_ACK;
+reg	[23:0]	LUT_DATA;
+reg	[5:0]	LUT_INDEX;
+reg	[3:0]	mSetup_ST;
+
+//////////////   CMOS sensor registers setting //////////////////////
+
+input 		iEXPOSURE_ADJ;
+input		iEXPOSURE_DEC_p;	
+
+parameter 	default_exposure 			= 16'h07c0;
+parameter 	exposure_change_value	 	= 16'd200;
+
+
+// `define 	ENABLE_TEST_PATTERN 1
+
+
+reg	[24:0]	combo_cnt;
+wire		combo_pulse;
+
+reg	[1:0]	izoom_mode_sw_delay;
+
+reg	[3:0]	iexposure_adj_delay;
+wire		exposure_adj_set;	
+wire		exposure_adj_reset;
+reg	[15:0]	sensor_exposure;
+
+wire [23:0] sensor_start_row;
+wire [23:0] sensor_start_column;
+wire [23:0] sensor_row_size;
+wire [23:0] sensor_column_size; 
+wire [23:0] sensor_row_mode;
+wire [23:0] sensor_column_mode;
+
+assign sensor_start_row 		= iZOOM_MODE_SW ?  24'h010036 : 24'h010000;
+assign sensor_start_column 		= iZOOM_MODE_SW ?  24'h020010 : 24'h020000;
+assign sensor_row_size	 		= iZOOM_MODE_SW ?  24'h0303BF : 24'h03077F;
+assign sensor_column_size 		= iZOOM_MODE_SW ?  24'h0404FF : 24'h0409FF;
+assign sensor_row_mode 			= iZOOM_MODE_SW ?  24'h220000 : 24'h220011;
+assign sensor_column_mode		= iZOOM_MODE_SW ?  24'h230000 : 24'h230011;
+
+	
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			begin
+				iexposure_adj_delay <= 0;
+			end
+		else 
+			begin
+				iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};		
+			end	
+	end
+
+assign 	exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
+assign  exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;		
+
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			sensor_exposure <= default_exposure;
+		else if (exposure_adj_set|combo_pulse)
+			begin
+				if (iEXPOSURE_DEC_p)
+					begin
+						if ((sensor_exposure < exposure_change_value)||
+							(sensor_exposure == 16'h0))
+							sensor_exposure <= 0;
+						else	
+							sensor_exposure <= sensor_exposure - exposure_change_value;
+					end		
+				else
+					begin
+						if (((16'hffff -sensor_exposure) <exposure_change_value)||
+							(sensor_exposure == 16'hffff))
+							sensor_exposure <= 16'hffff;
+						else
+							sensor_exposure <= sensor_exposure + exposure_change_value;	
+					end		
+			end
+	end			
+				
+		
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			combo_cnt <= 0;
+		else if (!iexposure_adj_delay[3])
+			combo_cnt <= combo_cnt + 1;
+		else
+			combo_cnt <= 0;	
+	end
+	
+assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;				
+		
+wire	i2c_reset;		
+
+assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
+
+/////////////////////////////////////////////////////////////////////
+
+//	Clock Setting
+parameter	CLK_Freq	=	50000000;	//	50	MHz
+parameter	I2C_Freq	=	20000;		//	20	KHz
+//	LUT Data Number
+parameter	LUT_SIZE	=	25;
+
+/////////////////////	I2C Control Clock	////////////////////////
+always@(posedge iCLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		mI2C_CTRL_CLK	<=	0;
+		mI2C_CLK_DIV	<=	0;
+	end
+	else
+	begin
+		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
+		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
+		else
+		begin
+			mI2C_CLK_DIV	<=	0;
+			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
+		end
+	end
+end
+////////////////////////////////////////////////////////////////////
+I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),		//	Controller Work Clock
+						.I2C_SCLK(I2C_SCLK),		//	I2C CLOCK
+ 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),		//	I2C DATA
+						.I2C_DATA(mI2C_DATA),		//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+						.GO(mI2C_GO),      			//	GO transfor
+						.END(mI2C_END),				//	END transfor 
+						.ACK(mI2C_ACK),				//	ACK
+						.RESET(i2c_reset)
+					);
+////////////////////////////////////////////////////////////////////
+//////////////////////	Config Control	////////////////////////////
+//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
+always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+
+	end
+
+	else if(LUT_INDEX<LUT_SIZE)
+		begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_DATA	<=	{8'hBA,LUT_DATA};
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1:	begin
+					if(mI2C_END)
+					begin
+						if(!mI2C_ACK)
+						mSetup_ST	<=	2;
+						else
+						mSetup_ST	<=	0;							
+						mI2C_GO		<=	0;
+					end
+				end
+			2:	begin
+					LUT_INDEX	<=	LUT_INDEX+1;
+					mSetup_ST	<=	0;
+				end
+			endcase
+		end
+end
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT	  //////////////////////////		
+always
+begin
+	case(LUT_INDEX)
+	0	:	LUT_DATA	<=	24'h000000;
+	1	:	LUT_DATA	<=	24'h20c000;				//	Mirror Row and Columns
+	2	:	LUT_DATA	<=	{8'h09,sensor_exposure};//	Exposure
+	3	:	LUT_DATA	<=	24'h050000;				//	H_Blanking
+	4	:	LUT_DATA	<=	24'h060019;				//	V_Blanking	
+	5	:	LUT_DATA	<=	24'h0A8000;				//	change latch
+	6	:	LUT_DATA	<=	24'h2B000b;				//	Green 1 Gain
+	7	:	LUT_DATA	<=	24'h2C000f;				//	Blue Gain
+	8	:	LUT_DATA	<=	24'h2D000f;				//	Red Gain
+	9	:	LUT_DATA	<=	24'h2E000b;				//	Green 2 Gain
+	10	:	LUT_DATA	<=	24'h100051;				//	set up PLL power on
+	11	:	LUT_DATA	<=	24'h111807;				//	PLL_m_Factor<<8+PLL_n_Divider
+	12	:	LUT_DATA	<=	24'h120002;				//	PLL_p1_Divider
+	13	:	LUT_DATA	<=	24'h100053;				//	set USE PLL	 
+	14	:	LUT_DATA	<=	24'h980000;				//	disble calibration 	
+`ifdef ENABLE_TEST_PATTERN
+	15	:	LUT_DATA	<=	24'hA00001;				//	Test pattern control 	
+	16	:	LUT_DATA	<=	24'hA10123;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20456;				//	Test red pattern value
+`else
+	15	:	LUT_DATA	<=	24'hA00000;				//	Test pattern control 
+	16	:	LUT_DATA	<=	24'hA10000;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20FFF;				//	Test red pattern value
+`endif
+	18	:	LUT_DATA	<=	sensor_start_row 	;	//	set start row	
+	19	:	LUT_DATA	<=	sensor_start_column ;	//	set start column 	
+
+	20	:	LUT_DATA	<=	sensor_row_size;		//	set row size	
+	21	:	LUT_DATA	<=	sensor_column_size;		//	set column size
+	22	:	LUT_DATA	<=	sensor_row_mode;		//	set row mode in bin mode
+	23	:	LUT_DATA	<=	sensor_column_mode;		//	set column mode	 in bin mode
+	24	:	LUT_DATA	<=	24'h4901A8;				//	row black target		
+	default:LUT_DATA	<=	24'h000000;
+	endcase
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v.bak
new file mode 100644
index 0000000..81810a8
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v.bak
@@ -0,0 +1,282 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	I2C_CCD_Config
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module I2C_CCD_Config (	//	Host Side
+						iCLK,
+						iRST_N,
+						iUART_CTRL,
+						iZOOM_MODE_SW,
+						iEXPOSURE_ADJ,
+						iEXPOSURE_DEC_p,
+						//	I2C Side
+						I2C_SCLK,
+						I2C_SDAT
+						);
+						
+//	Host Side
+input			iCLK;
+input			iRST_N;
+input 			iUART_CTRL;
+input 			iZOOM_MODE_SW;
+
+//	I2C Side
+output		I2C_SCLK;
+inout		I2C_SDAT;
+
+//	Internal Registers/Wires
+reg	[15:0]	mI2C_CLK_DIV;
+reg	[31:0]	mI2C_DATA;
+reg			mI2C_CTRL_CLK;
+reg			mI2C_GO;
+wire		mI2C_END;
+wire		mI2C_ACK;
+reg	[23:0]	LUT_DATA;
+reg	[5:0]	LUT_INDEX;
+reg	[3:0]	mSetup_ST;
+
+//////////////   CMOS sensor registers setting //////////////////////
+
+input 		iEXPOSURE_ADJ;
+input		iEXPOSURE_DEC_p;	
+
+parameter 	default_exposure 			= 16'h07c0;
+parameter 	exposure_change_value	 	= 16'd200;
+
+reg	[24:0]	combo_cnt;
+wire		combo_pulse;
+
+reg	[1:0]	izoom_mode_sw_delay;
+
+reg	[3:0]	iexposure_adj_delay;
+wire		exposure_adj_set;	
+wire		exposure_adj_reset;
+reg	[15:0]	senosr_exposure;
+
+wire [23:0] sensor_start_row;
+wire [23:0] sensor_start_column;
+wire [23:0] sensor_row_size;
+wire [23:0] sensor_column_size; 
+wire [23:0] sensor_row_mode;
+wire [23:0] sensor_column_mode;
+
+assign sensor_start_row 		= iZOOM_MODE_SW ?  24'h010036 : 24'h010000;
+assign sensor_start_column 		= iZOOM_MODE_SW ?  24'h020010 : 24'h020000;
+assign sensor_row_size	 		= iZOOM_MODE_SW ?  24'h0303BF : 24'h03077F;
+assign sensor_column_size 		= iZOOM_MODE_SW ?  24'h0404FF : 24'h0409FF;
+assign sensor_row_mode 			= iZOOM_MODE_SW ?  24'h220000 : 24'h220011;
+assign sensor_column_mode		= iZOOM_MODE_SW ?  24'h230000 : 24'h230011;
+
+	
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			begin
+				iexposure_adj_delay <= 0;
+			end
+		else 
+			begin
+				iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};		
+			end	
+	end
+
+assign 	exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
+assign  exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;		
+
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			senosr_exposure <= default_exposure;
+		else if (exposure_adj_set|combo_pulse)
+			begin
+				if (iEXPOSURE_DEC_p)
+					begin
+						if ((senosr_exposure < exposure_change_value)||
+							(senosr_exposure == 16'h0))
+							senosr_exposure <= 0;
+						else	
+							senosr_exposure <= senosr_exposure - exposure_change_value;
+					end		
+				else
+					begin
+						if (((16'hffff -senosr_exposure) <exposure_change_value)||
+							(senosr_exposure == 16'hffff))
+							senosr_exposure <= 16'hffff;
+						else
+							senosr_exposure <= senosr_exposure + exposure_change_value;	
+					end		
+			end
+	end			
+				
+		
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			combo_cnt <= 0;
+		else if (!iexposure_adj_delay[3])
+			combo_cnt <= combo_cnt + 1;
+		else
+			combo_cnt <= 0;	
+	end
+	
+assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;				
+		
+wire	i2c_reset;		
+
+assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
+
+/////////////////////////////////////////////////////////////////////
+
+//	Clock Setting
+parameter	CLK_Freq	=	50000000;	//	50	MHz
+parameter	I2C_Freq	=	20000;		//	20	KHz
+//	LUT Data Number
+parameter	LUT_SIZE	=	25;
+
+/////////////////////	I2C Control Clock	////////////////////////
+always@(posedge iCLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		mI2C_CTRL_CLK	<=	0;
+		mI2C_CLK_DIV	<=	0;
+	end
+	else
+	begin
+		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
+		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
+		else
+		begin
+			mI2C_CLK_DIV	<=	0;
+			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
+		end
+	end
+end
+////////////////////////////////////////////////////////////////////
+I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),		//	Controller Work Clock
+						.I2C_SCLK(I2C_SCLK),		//	I2C CLOCK
+ 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),		//	I2C DATA
+						.I2C_DATA(mI2C_DATA),		//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+						.GO(mI2C_GO),      			//	GO transfor
+						.END(mI2C_END),				//	END transfor 
+						.ACK(mI2C_ACK),				//	ACK
+						.RESET(i2c_reset)
+					);
+////////////////////////////////////////////////////////////////////
+//////////////////////	Config Control	////////////////////////////
+//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
+always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+
+	end
+
+	else if(LUT_INDEX<LUT_SIZE)
+		begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_DATA	<=	{8'hBA,LUT_DATA};
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1:	begin
+					if(mI2C_END)
+					begin
+						if(!mI2C_ACK)
+						mSetup_ST	<=	2;
+						else
+						mSetup_ST	<=	0;							
+						mI2C_GO		<=	0;
+					end
+				end
+			2:	begin
+					LUT_INDEX	<=	LUT_INDEX+1;
+					mSetup_ST	<=	0;
+				end
+			endcase
+		end
+end
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT	  //////////////////////////		
+always
+begin
+	case(LUT_INDEX)
+	0	:	LUT_DATA	<=	24'h000000;
+	1	:	LUT_DATA	<=	24'h20c000;				//	Mirror Row and Columns
+	2	:	LUT_DATA	<=	{8'h09,senosr_exposure};//	Exposure
+	3	:	LUT_DATA	<=	24'h050000;				//	H_Blanking
+	4	:	LUT_DATA	<=	24'h060019;				//	V_Blanking	
+	5	:	LUT_DATA	<=	24'h0A8000;				//	change latch
+	6	:	LUT_DATA	<=	24'h2B000b;				//	Green 1 Gain
+	7	:	LUT_DATA	<=	24'h2C000f;				//	Blue Gain
+	8	:	LUT_DATA	<=	24'h2D000f;				//	Red Gain
+	9	:	LUT_DATA	<=	24'h2E000b;				//	Green 2 Gain
+	10	:	LUT_DATA	<=	24'h100051;				//	set up PLL power on
+	11	:	LUT_DATA	<=	24'h111807;				//	PLL_m_Factor<<8+PLL_n_Divider
+	12	:	LUT_DATA	<=	24'h120002;				//	PLL_p1_Divider
+	13	:	LUT_DATA	<=	24'h100053;				//	set USE PLL	 
+	14	:	LUT_DATA	<=	24'h980000;				//	disble calibration 	
+`ifdef ENABLE_TEST_PATTERN
+	15	:	LUT_DATA	<=	24'hA00001;				//	Test pattern control 	
+	16	:	LUT_DATA	<=	24'hA10123;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20456;				//	Test red pattern value
+`else
+	15	:	LUT_DATA	<=	24'hA00000;				//	Test pattern control 
+	16	:	LUT_DATA	<=	24'hA10000;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20FFF;				//	Test red pattern value
+`endif
+	18	:	LUT_DATA	<=	sensor_start_row 	;	//	set start row	
+	19	:	LUT_DATA	<=	sensor_start_column ;	//	set start column 	
+
+	20	:	LUT_DATA	<=	sensor_row_size;		//	set row size	
+	21	:	LUT_DATA	<=	sensor_column_size;		//	set column size
+	22	:	LUT_DATA	<=	sensor_row_mode;		//	set row mode in bin mode
+	23	:	LUT_DATA	<=	sensor_column_mode;		//	set column mode	 in bin mode
+	24	:	LUT_DATA	<=	24'h4901A8;				//	row black target		
+	default:LUT_DATA	<=	24'h000000;
+	endcase
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_Controller.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_Controller.v
new file mode 100644
index 0000000..3740541
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_Controller.v
@@ -0,0 +1,150 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2005 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altrea Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL or Verilog source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:i2c controller
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Joe Yang          :| 05/07/10  :|      Initial Revision
+// --------------------------------------------------------------------
+module I2C_Controller (
+	CLOCK,
+	I2C_SCLK,//I2C CLOCK
+ 	I2C_SDAT,//I2C DATA
+	I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+	GO,      //GO transfor
+	END,     //END transfor 
+
+	ACK,      //ACK
+	RESET
+);
+	input  CLOCK;
+	input  [31:0]I2C_DATA;	
+	input  GO;
+	input  RESET;	
+ 	inout  I2C_SDAT;	
+	output I2C_SCLK;
+	output END;	
+	output ACK;
+
+
+reg SDO;
+reg SCLK;
+reg END;
+reg [31:0]SD;
+reg [6:0]SD_COUNTER;
+
+wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=39))? ~CLOCK :0 );
+wire I2C_SDAT=SDO?1'bz:0 ;
+
+reg ACK1,ACK2,ACK3,ACK4;
+wire ACK=ACK1 | ACK2 |ACK3 |ACK4;
+
+//--I2C COUNTER
+always @(negedge RESET or posedge CLOCK ) begin
+if (!RESET) SD_COUNTER=6'b111111;
+else begin
+if (GO==0) 
+	SD_COUNTER=0;
+	else 
+	if (SD_COUNTER < 41) SD_COUNTER=SD_COUNTER+1;	
+end
+end
+//----
+
+always @(negedge RESET or  posedge CLOCK ) begin
+if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0;ACK4=0; END=1; end
+else
+case (SD_COUNTER)
+	6'd0  : begin ACK1=0 ;ACK2=0 ;ACK3=0 ;ACK4=0 ; END=0; SDO=1; SCLK=1;end
+	//start
+	6'd1  : begin SD=I2C_DATA;SDO=0;end
+	6'd2  : SCLK=0;
+	//SLAVE ADDR
+	6'd3  : SDO=SD[31];
+	6'd4  : SDO=SD[30];
+	6'd5  : SDO=SD[29];
+	6'd6  : SDO=SD[28];
+	6'd7  : SDO=SD[27];
+	6'd8  : SDO=SD[26];
+	6'd9  : SDO=SD[25];
+	6'd10 : SDO=SD[24];	
+	6'd11 : SDO=1'b1;//ACK
+
+	//SUB ADDR
+	6'd12  : begin SDO=SD[23]; ACK1=I2C_SDAT; end
+	6'd13  : SDO=SD[22];
+	6'd14  : SDO=SD[21];
+	6'd15  : SDO=SD[20];
+	6'd16  : SDO=SD[19];
+	6'd17  : SDO=SD[18];
+	6'd18  : SDO=SD[17];
+	6'd19  : SDO=SD[16];
+	6'd20  : SDO=1'b1;//ACK
+
+	//DATA
+	6'd21  : begin SDO=SD[15]; ACK2=I2C_SDAT; end
+	6'd22  : SDO=SD[14];
+	6'd23  : SDO=SD[13];
+	6'd24  : SDO=SD[12];
+	6'd25  : SDO=SD[11];
+	6'd26  : SDO=SD[10];
+	6'd27  : SDO=SD[9];
+	6'd28  : SDO=SD[8];
+	6'd29  : SDO=1'b1;//ACK
+
+	//DATA
+	6'd30  : begin SDO=SD[7]; ACK3=I2C_SDAT; end
+	6'd31  : SDO=SD[6];
+	6'd32  : SDO=SD[5];
+	6'd33  : SDO=SD[4];
+	6'd34  : SDO=SD[3];
+	6'd35  : SDO=SD[2];
+	6'd36  : SDO=SD[1];
+	6'd37  : SDO=SD[0];
+	6'd38  : SDO=1'b1;//ACK
+
+	
+	//stop
+    6'd39 : begin SDO=1'b0;	SCLK=1'b0; ACK4=I2C_SDAT; end	
+    6'd40 : SCLK=1'b1; 
+    6'd41 : begin SDO=1'b1; END=1; end 
+
+endcase
+end
+
+
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.bsf
new file mode 100644
index 0000000..b7b5b56
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.bsf
@@ -0,0 +1,77 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 184 128)
+	(text "Line_Buffer" (rect 60 1 135 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "shiftin[11..0]" (rect 0 0 69 14)(font "Arial" (font_size 8)))
+		(text "shiftin[11..0]" (rect 20 34 78 47)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 20 50 43 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clken" (rect 20 66 44 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 184 40)
+		(output)
+		(text "shiftout[11..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
+		(text "shiftout[11..0]" (rect 99 34 163 47)(font "Arial" (font_size 8)))
+		(line (pt 184 40)(pt 168 40)(line_width 3))
+	)
+	(port
+		(pt 184 56)
+		(output)
+		(text "taps1x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "taps1x[11..0]" (rect 102 50 162 63)(font "Arial" (font_size 8)))
+		(line (pt 184 56)(pt 168 56)(line_width 3))
+	)
+	(port
+		(pt 184 72)
+		(output)
+		(text "taps0x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "taps0x[11..0]" (rect 102 66 162 79)(font "Arial" (font_size 8)))
+		(line (pt 184 72)(pt 168 72)(line_width 3))
+	)
+	(drawing
+		(text "altshift_taps" (rect 63 18 119 31)(font "Arial" (font_size 8)))
+		(text "Number of taps 2" (rect 19 90 93 102)(font "Arial" ))
+		(text "Tap distance 1280" (rect 19 100 95 112)(font "Arial" ))
+		(line (pt 16 16)(pt 168 16)(line_width 1))
+		(line (pt 168 16)(pt 168 112)(line_width 1))
+		(line (pt 168 112)(pt 16 112)(line_width 1))
+		(line (pt 16 112)(pt 16 16)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.v
new file mode 100644
index 0000000..09482ce
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.v
@@ -0,0 +1,111 @@
+// megafunction wizard: %Shift register (RAM-based)%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altshift_taps 
+
+// ============================================================
+// File Name: Line_Buffer.v
+// Megafunction Name(s):
+// 			altshift_taps
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module Line_Buffer (
+	clken,
+	clock,
+	shiftin,
+	shiftout,
+	taps0x,
+	taps1x);
+
+	input	  clken;
+	input	  clock;
+	input	[11:0]  shiftin;
+	output	[11:0]  shiftout;
+	output	[11:0]  taps0x;
+	output	[11:0]  taps1x;
+
+	wire [23:0] sub_wire0;
+	wire [11:0] sub_wire3;
+	wire [23:12] sub_wire1 = sub_wire0[23:12];
+	wire [11:0] sub_wire2 = sub_wire0[11:0];
+	wire [11:0] taps1x = sub_wire1[23:12];
+	wire [11:0] taps0x = sub_wire2[11:0];
+	wire [11:0] shiftout = sub_wire3[11:0];
+
+	altshift_taps	altshift_taps_component (
+				.clken (clken),
+				.clock (clock),
+				.shiftin (shiftin),
+				.taps (sub_wire0),
+				.shiftout (sub_wire3));
+	defparam
+		altshift_taps_component.lpm_type = "altshift_taps",
+		altshift_taps_component.number_of_taps = 2,
+		altshift_taps_component.tap_distance = 1280,
+		altshift_taps_component.width = 12;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
+// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "1280"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "12"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
+// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "2"
+// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "1280"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: shiftin 0 0 12 0 INPUT NODEFVAL shiftin[11..0]
+// Retrieval info: USED_PORT: shiftout 0 0 12 0 OUTPUT NODEFVAL shiftout[11..0]
+// Retrieval info: USED_PORT: taps0x 0 0 12 0 OUTPUT NODEFVAL taps0x[11..0]
+// Retrieval info: USED_PORT: taps1x 0 0 12 0 OUTPUT NODEFVAL taps1x[11..0]
+// Retrieval info: CONNECT: @shiftin 0 0 12 0 shiftin 0 0 12 0
+// Retrieval info: CONNECT: shiftout 0 0 12 0 @shiftout 0 0 12 0
+// Retrieval info: CONNECT: taps0x 0 0 12 0 @taps 0 0 12 0
+// Retrieval info: CONNECT: taps1x 0 0 12 0 @taps 0 0 12 12
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/RAW2RGB.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/RAW2RGB.v
new file mode 100644
index 0000000..16493c7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/RAW2RGB.v
@@ -0,0 +1,128 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	RAW2RGB
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module RAW2RGB(	oRed,
+				oGreen,
+				oBlue,
+				oDVAL,
+				iX_Cont,
+				iY_Cont,
+				iDATA,
+				iDVAL,
+				iCLK,
+				iRST
+				);
+
+input	[10:0]	iX_Cont;
+input	[10:0]	iY_Cont;
+input	[11:0]	iDATA;
+input			iDVAL;
+input			iCLK;
+input			iRST;
+output	[11:0]	oRed;
+output	[11:0]	oGreen;
+output	[11:0]	oBlue;
+output			oDVAL;
+wire	[11:0]	mDATA_0;
+wire	[11:0]	mDATA_1;
+reg		[11:0]	mDATAd_0;
+reg		[11:0]	mDATAd_1;
+reg		[11:0]	mCCD_R;
+reg		[12:0]	mCCD_G;
+reg		[11:0]	mCCD_B;
+reg				mDVAL;
+
+assign	oRed	=	mCCD_R[11:0];
+assign	oGreen	=	mCCD_G[12:1];
+assign	oBlue	=	mCCD_B[11:0];
+assign	oDVAL	=	mDVAL;
+
+Line_Buffer 	u0	(	.clken(iDVAL),
+						.clock(iCLK),
+						.shiftin(iDATA),
+						.taps0x(mDATA_1),
+						.taps1x(mDATA_0)	);
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		mCCD_R	<=	0;
+		mCCD_G	<=	0;
+		mCCD_B	<=	0;
+		mDATAd_0<=	0;
+		mDATAd_1<=	0;
+		mDVAL	<=	0;
+	end
+	else
+	begin
+		mDATAd_0	<=	mDATA_0;
+		mDATAd_1	<=	mDATA_1;
+		mDVAL		<=	{iY_Cont[0]|iX_Cont[0]}	?	1'b0	:	iDVAL;
+		if({iY_Cont[0],iX_Cont[0]}==2'b10)
+		begin
+			mCCD_R	<=	mDATA_0;
+			mCCD_G	<=	mDATAd_0+mDATA_1;
+			mCCD_B	<=	mDATAd_1;
+		end	
+		else if({iY_Cont[0],iX_Cont[0]}==2'b11)
+		begin
+			mCCD_R	<=	mDATAd_0;
+			mCCD_G	<=	mDATA_0+mDATAd_1;
+			mCCD_B	<=	mDATA_1;
+		end
+		else if({iY_Cont[0],iX_Cont[0]}==2'b00)
+		begin
+			mCCD_R	<=	mDATA_1;
+			mCCD_G	<=	mDATA_0+mDATAd_1;
+			mCCD_B	<=	mDATAd_0;
+		end
+		else if({iY_Cont[0],iX_Cont[0]}==2'b01)
+		begin
+			mCCD_R	<=	mDATAd_1;
+			mCCD_G	<=	mDATAd_0+mDATA_1;
+			mCCD_B	<=	mDATA_0;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Reset_Delay.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Reset_Delay.v
new file mode 100644
index 0000000..578a964
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Reset_Delay.v
@@ -0,0 +1,74 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	Reset_Delay
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module	Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2);
+input		iCLK;
+input		iRST;
+output reg	oRST_0;
+output reg	oRST_1;
+output reg	oRST_2;
+
+reg	[31:0]	Cont;
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		Cont	<=	0;
+		oRST_0	<=	0;
+		oRST_1	<=	0;
+		oRST_2	<=	0;
+	end
+	else
+	begin
+		if(Cont!=32'h11FFFFF)
+		Cont	<=	Cont+1;
+		if(Cont>=32'h1FFFFF)
+		oRST_0	<=	1;
+		if(Cont>=32'h2FFFFF)
+		oRST_1	<=	1;
+		if(Cont>=32'h11FFFFF)
+		oRST_2	<=	1;
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v
new file mode 100644
index 0000000..2756db0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v
@@ -0,0 +1,70 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	SEG7_LUT
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module SEG7_LUT	(	oSEG,iDIG	);
+input	[3:0]	iDIG;
+output	[6:0]	oSEG;
+reg		[6:0]	oSEG;
+
+always @(iDIG)
+begin
+		case(iDIG)
+		4'h1: oSEG = 7'b1111001;	// ---t----
+		4'h2: oSEG = 7'b0100100; 	// |	  |
+		4'h3: oSEG = 7'b0110000; 	// lt	 rt
+		4'h4: oSEG = 7'b0011001; 	// |	  |
+		4'h5: oSEG = 7'b0010010; 	// ---m----
+		4'h6: oSEG = 7'b0000010; 	// |	  |
+		4'h7: oSEG = 7'b1111000; 	// lb	 rb
+		4'h8: oSEG = 7'b0000000; 	// |	  |
+		4'h9: oSEG = 7'b0011000; 	// ---b----
+		4'ha: oSEG = 7'b0001000;
+		4'hb: oSEG = 7'b0000011;
+		4'hc: oSEG = 7'b1000110;
+		4'hd: oSEG = 7'b0100001;
+		4'he: oSEG = 7'b0000110;
+		4'hf: oSEG = 7'b0001110;
+		4'h0: oSEG = 7'b1000000;
+		endcase
+end
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT_8.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT_8.v
new file mode 100644
index 0000000..e84af4e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT_8.v
@@ -0,0 +1,56 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	SEG7_LUT_8
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module SEG7_LUT_8 (	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG );
+input	[31:0]	iDIG;
+output	[6:0]	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7;
+
+SEG7_LUT	u0	(	oSEG0,iDIG[3:0]		);
+SEG7_LUT	u1	(	oSEG1,iDIG[7:4]		);
+SEG7_LUT	u2	(	oSEG2,iDIG[11:8]	);
+SEG7_LUT	u3	(	oSEG3,iDIG[15:12]	);
+SEG7_LUT	u4	(	oSEG4,iDIG[19:16]	);
+SEG7_LUT	u5	(	oSEG5,iDIG[23:20]	);
+SEG7_LUT	u6	(	oSEG6,iDIG[27:24]	);
+SEG7_LUT	u7	(	oSEG7,iDIG[31:28]	);
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Controller.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Controller.v
new file mode 100644
index 0000000..c9c3537
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Controller.v
@@ -0,0 +1,122 @@
+module	VGA_Controller(	//	Host Side
+						iRed,
+						iGreen,
+						iBlue,
+						oRequest,
+						//	VGA Side
+						oVGA_R,
+						oVGA_G,
+						oVGA_B,
+						oVGA_H_SYNC,
+						oVGA_V_SYNC,
+						oVGA_SYNC,
+						oVGA_BLANK,
+						oVGA_CLOCK,
+						//	Control Signal
+						iCLK,
+						iRST_N	);
+
+`include "VGA_Param.h"
+
+//	Host Side
+input		[9:0]	iRed;
+input		[9:0]	iGreen;
+input		[9:0]	iBlue;
+output	reg			oRequest;
+//	VGA Side
+output		[9:0]	oVGA_R;
+output		[9:0]	oVGA_G;
+output		[9:0]	oVGA_B;
+output	reg			oVGA_H_SYNC;
+output	reg			oVGA_V_SYNC;
+output				oVGA_SYNC;
+output				oVGA_BLANK;
+output				oVGA_CLOCK;
+//	Control Signal
+input				iCLK;
+input				iRST_N;
+
+//	Internal Registers and Wires
+reg		[11:0]		H_Cont;
+reg		[11:0]		V_Cont;
+
+assign	oVGA_BLANK	=	oVGA_H_SYNC & oVGA_V_SYNC;
+assign	oVGA_SYNC	=	1'b0;
+assign	oVGA_CLOCK	=	iCLK;
+
+assign	oVGA_R	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iRed	:	0;
+assign	oVGA_G	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iGreen	:	0;
+assign	oVGA_B	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iBlue	:	0;
+
+//	Pixel LUT Address Generator
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	oRequest	<=	0;
+	else
+	begin
+		if(	H_Cont>=X_START-2 && H_Cont<X_START+H_SYNC_ACT-2 &&
+			V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
+		oRequest	<=	1;
+		else
+		oRequest	<=	0;
+	end
+end
+
+//	H_Sync Generator, Ref. 25.175 MHz Clock
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		H_Cont		<=	0;
+		oVGA_H_SYNC	<=	0;
+	end
+	else
+	begin
+		//	H_Sync Counter
+		if( H_Cont < H_SYNC_TOTAL )
+		H_Cont	<=	H_Cont+1;
+		else
+		H_Cont	<=	0;
+		//	H_Sync Generator
+		if( H_Cont < H_SYNC_CYC )
+		oVGA_H_SYNC	<=	0;
+		else
+		oVGA_H_SYNC	<=	1;
+	end
+end
+
+//	V_Sync Generator, Ref. H_Sync
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		V_Cont		<=	0;
+		oVGA_V_SYNC	<=	0;
+	end
+	else
+	begin
+		//	When H_Sync Re-start
+		if(H_Cont==0)
+		begin
+			//	V_Sync Counter
+			if( V_Cont < V_SYNC_TOTAL )
+			V_Cont	<=	V_Cont+1;
+			else
+			V_Cont	<=	0;
+			//	V_Sync Generator
+			if(	V_Cont < V_SYNC_CYC )
+			oVGA_V_SYNC	<=	0;
+			else
+			oVGA_V_SYNC	<=	1;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Param.h b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Param.h
new file mode 100644
index 0000000..9d0fd32
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Param.h
@@ -0,0 +1,16 @@
+//	Horizontal Parameter	( Pixel )
+parameter	H_SYNC_CYC	=	96;
+parameter	H_SYNC_BACK	=	48;
+parameter	H_SYNC_ACT	=	640;	
+parameter	H_SYNC_FRONT=	16;
+parameter	H_SYNC_TOTAL=	800;
+
+//	Virtical Parameter		( Line )
+parameter	V_SYNC_CYC	=	2;
+parameter	V_SYNC_BACK	=	33;
+parameter	V_SYNC_ACT	=	480;	
+parameter	V_SYNC_FRONT=	10;
+parameter	V_SYNC_TOTAL=	525;
+//	Start Offset
+parameter	X_START		=	H_SYNC_CYC+H_SYNC_BACK;
+parameter	Y_START		=	V_SYNC_CYC+V_SYNC_BACK;
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.bsf
new file mode 100644
index 0000000..a895305
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.bsf
@@ -0,0 +1,81 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 240 168)
+	(text "sdram_pll" (rect 92 0 158 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 25 164)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 240 64)
+		(output)
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 224 50 234 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 240 80)
+		(output)
+		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 224 66 232 79)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 178 152 401 315)(font "Arial" ))
+		(text "inclk0 frequency: 50.000 MHz" (rect 50 59 223 129)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
+		(text "Clk " (rect 51 93 116 197)(font "Arial" ))
+		(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
+		(text "Ph (dg)" (rect 98 93 225 197)(font "Arial" ))
+		(text "DC (%)" (rect 132 93 294 197)(font "Arial" ))
+		(text "c0" (rect 54 107 116 225)(font "Arial" ))
+		(text "5/2" (rect 77 107 165 225)(font "Arial" ))
+		(text "0.00" (rect 104 107 224 225)(font "Arial" ))
+		(text "50.00" (rect 136 107 293 225)(font "Arial" ))
+		(text "c1" (rect 54 121 115 253)(font "Arial" ))
+		(text "5/2" (rect 77 121 165 253)(font "Arial" ))
+		(text "-117.00" (rect 98 121 224 253)(font "Arial" ))
+		(text "50.00" (rect 136 121 293 253)(font "Arial" ))
+		(line (pt 0 0)(pt 241 0))
+		(line (pt 241 0)(pt 241 169))
+		(line (pt 0 169)(pt 241 169))
+		(line (pt 0 0)(pt 0 169))
+		(line (pt 48 91)(pt 164 91))
+		(line (pt 48 104)(pt 164 104))
+		(line (pt 48 118)(pt 164 118))
+		(line (pt 48 132)(pt 164 132))
+		(line (pt 48 91)(pt 48 132))
+		(line (pt 69 91)(pt 69 132)(line_width 3))
+		(line (pt 95 91)(pt 95 132)(line_width 3))
+		(line (pt 129 91)(pt 129 132)(line_width 3))
+		(line (pt 163 91)(pt 163 132))
+		(line (pt 40 48)(pt 207 48))
+		(line (pt 207 48)(pt 207 151))
+		(line (pt 40 151)(pt 207 151))
+		(line (pt 40 48)(pt 40 151))
+		(line (pt 239 64)(pt 207 64))
+		(line (pt 239 80)(pt 207 80))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.ppf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.ppf
new file mode 100644
index 0000000..a4a0f2e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.ppf
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="sdram_pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.qip
new file mode 100644
index 0000000..7440d58
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sdram_pll.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.ppf"]
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v
new file mode 100644
index 0000000..6b4189b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v
@@ -0,0 +1,329 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sdram_pll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [4:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 2,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 5,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 2,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_phase_shift = "-2600",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2.60000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2600"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v.bak
new file mode 100644
index 0000000..7fd74a1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v.bak
@@ -0,0 +1,326 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 218 06/27/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sdram_pll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [5:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.clk0_divide_by = 2,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 5,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 2,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_phase_shift = "-3000",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone II",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-3.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-3000"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_wave0.jpg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_wave0.jpg
new file mode 100644
index 0000000..a48389a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_wave0.jpg
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_waveforms.html b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_waveforms.html
new file mode 100644
index 0000000..2d27f12
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for sdram_pll.v </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file sdram_pll.v </CENTER></h2>
+<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design sdram_pll.v. The design sdram_pll.v has Cyclone II PLL_TYPE pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. </P>
+<CENTER><img src=sdram_pll_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
+<P><FONT size=3></P>
+<P></P>
+</body>
+</html>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.bat b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.bat
new file mode 100644
index 0000000..c3a3f44
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.bat
@@ -0,0 +1,17 @@
+%QUARTUS_ROOTDIR%\\bin\\quartus_pgm.exe -m jtag -c USB-Blaster[USB-0] -o "p;DE1_D5M.sof"
+@ set SOPC_BUILDER_PATH_71=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_71%
+@ set SOPC_BUILDER_PATH_72=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_72%
+@ set SOPC_BUILDER_PATH_80=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_80%
+@ set SOPC_BUILDER_PATH_81=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_81%
+@ set SOPC_BUILDER_PATH_90=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_90%
+@ set SOPC_BUILDER_PATH_91=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_91%
+@ set SOPC_BUILDER_PATH_92=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_92%
+@ set SOPC_BUILDER_PATH_100=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_100%
+@ set SOPC_BUILDER_PATH_101=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_101%
+@ set SOPC_BUILDER_PATH_102=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_102%
+@ set SOPC_BUILDER_PATH_110=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_110%
+@ set SOPC_BUILDER_PATH_111=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_111%
+@ set SOPC_BUILDER_PATH_112=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_112%
+@ set SOPC_BUILDER_PATH_120=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_120%
+@ set SOPC_BUILDER_PATH_121=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_121%
+@ set SOPC_BUILDER_PATH_122=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_122%
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.sof b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.sof
new file mode 100644
index 0000000..9832b19
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.sof
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/cbx_args.txt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..9ca2d87
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/cbx_args.txt
@@ -0,0 +1,63 @@
+BANDWIDTH_TYPE=AUTO
+CLK0_DIVIDE_BY=2
+CLK0_DUTY_CYCLE=50
+CLK0_MULTIPLY_BY=5
+CLK0_PHASE_SHIFT=0
+CLK1_DIVIDE_BY=2
+CLK1_DUTY_CYCLE=50
+CLK1_MULTIPLY_BY=5
+CLK1_PHASE_SHIFT=-2600
+COMPENSATE_CLOCK=CLK0
+INCLK0_INPUT_FREQUENCY=20000
+INTENDED_DEVICE_FAMILY="Cyclone III"
+LPM_TYPE=altpll
+OPERATION_MODE=NORMAL
+PLL_TYPE=AUTO
+PORT_ACTIVECLOCK=PORT_UNUSED
+PORT_ARESET=PORT_UNUSED
+PORT_CLKBAD0=PORT_UNUSED
+PORT_CLKBAD1=PORT_UNUSED
+PORT_CLKLOSS=PORT_UNUSED
+PORT_CLKSWITCH=PORT_UNUSED
+PORT_CONFIGUPDATE=PORT_UNUSED
+PORT_FBIN=PORT_UNUSED
+PORT_INCLK0=PORT_USED
+PORT_INCLK1=PORT_UNUSED
+PORT_LOCKED=PORT_UNUSED
+PORT_PFDENA=PORT_UNUSED
+PORT_PHASECOUNTERSELECT=PORT_UNUSED
+PORT_PHASEDONE=PORT_UNUSED
+PORT_PHASESTEP=PORT_UNUSED
+PORT_PHASEUPDOWN=PORT_UNUSED
+PORT_PLLENA=PORT_UNUSED
+PORT_SCANACLR=PORT_UNUSED
+PORT_SCANCLK=PORT_UNUSED
+PORT_SCANCLKENA=PORT_UNUSED
+PORT_SCANDATA=PORT_UNUSED
+PORT_SCANDATAOUT=PORT_UNUSED
+PORT_SCANDONE=PORT_UNUSED
+PORT_SCANREAD=PORT_UNUSED
+PORT_SCANWRITE=PORT_UNUSED
+PORT_clk0=PORT_USED
+PORT_clk1=PORT_USED
+PORT_clk2=PORT_UNUSED
+PORT_clk3=PORT_UNUSED
+PORT_clk4=PORT_UNUSED
+PORT_clk5=PORT_UNUSED
+PORT_clkena0=PORT_UNUSED
+PORT_clkena1=PORT_UNUSED
+PORT_clkena2=PORT_UNUSED
+PORT_clkena3=PORT_UNUSED
+PORT_clkena4=PORT_UNUSED
+PORT_clkena5=PORT_UNUSED
+PORT_extclk0=PORT_UNUSED
+PORT_extclk1=PORT_UNUSED
+PORT_extclk2=PORT_UNUSED
+PORT_extclk3=PORT_UNUSED
+WIDTH_CLOCK=5
+DEVICE_FAMILY="Cyclone III"
+CBX_AUTO_BLACKBOX=ALL
+inclk
+inclk
+clk
+clk
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/qmegawiz_errors_log.txt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/qmegawiz_errors_log.txt
new file mode 100644
index 0000000..1097973
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/qmegawiz_errors_log.txt
@@ -0,0 +1,28 @@
+
+
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.v
+
+Mar 16 05PM:44:47>: Error in CNX file format.
+
+Error messages are listed in file
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.cnxerr.
+
+Can't create the custom megafunction variation file(s)
+
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.v
+
+Mar 16 05PM:45:47>: Error in CNX file format.
+
+Error messages are listed in file
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.cnxerr.
+
+Can't create the custom megafunction variation file(s)
+
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.v
+
+Mar 16 05PM:45:55>: Error in CNX file format.
+
+Error messages are listed in file
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.cnxerr.
+
+Can't create the custom megafunction variation file(s)
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/sdram_pll.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/sdram_pll.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/sdram_pll.qip
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.asm.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.asm.rpt
new file mode 100644
index 0000000..e46a721
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.asm.rpt
@@ -0,0 +1,130 @@
+Assembler report for DE0_D5M
+Tue Mar 08 16:24:45 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof
+  6. Assembler Device Options: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof
+  7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Mar 08 16:24:45 2016 ;
+; Revision Name         ; DE0_D5M                               ;
+; Top-level Entity Name ; TOP_DE0_CAMERA_MOUSE                  ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; On       ; Off           ;
+; Use configuration device                                                    ; On       ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assembler Generated Files                                                                                                                        ;
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; File Name                                                                                                                                        ;
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof ;
+; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof ;
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof ;
++----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                                                                                                   ;
++----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Device         ; EP3C16F484C6                                                                                                                                              ;
+; JTAG usercode  ; 0x002C5C6E                                                                                                                                                ;
+; Checksum       ; 0x002C5C6E                                                                                                                                                ;
++----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof ;
++--------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Option             ; Setting                                                                                                                                               ;
++--------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Device             ; EPCS4                                                                                                                                                 ;
+; JTAG usercode      ; 0x00000000                                                                                                                                            ;
+; Checksum           ; 0x059D5402                                                                                                                                            ;
+; Compression Ratio  ; 2                                                                                                                                                     ;
++--------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 08 16:24:42 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 443 megabytes
+    Info: Processing ended: Tue Mar 08 16:24:45 2016
+    Info: Elapsed time: 00:00:03
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.bsf
new file mode 100644
index 0000000..94a0cff
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.bsf
@@ -0,0 +1,253 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 304 512)
+	(text "DE0_D5M" (rect 5 0 49 12)(font "Arial" ))
+	(text "inst" (rect 8 480 20 492)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK_50" (rect 0 0 49 12)(font "Arial" ))
+		(text "CLOCK_50" (rect 21 27 70 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "KEY[2..0]" (rect 0 0 41 12)(font "Arial" ))
+		(text "KEY[2..0]" (rect 21 43 62 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "SW[9..0]" (rect 0 0 36 12)(font "Arial" ))
+		(text "SW[9..0]" (rect 21 59 57 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "GPIO_1_CLKIN[1..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "GPIO_1_CLKIN[1..0]" (rect 21 75 107 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "LEDG[9..0]" (rect 0 0 47 12)(font "Arial" ))
+		(text "LEDG[9..0]" (rect 220 27 267 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(port
+		(pt 288 48)
+		(output)
+		(text "HEX0[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX0[6..0]" (rect 223 43 267 55)(font "Arial" ))
+		(line (pt 288 48)(pt 272 48)(line_width 3))
+	)
+	(port
+		(pt 288 64)
+		(output)
+		(text "HEX1[6..0]" (rect 0 0 43 12)(font "Arial" ))
+		(text "HEX1[6..0]" (rect 224 59 267 71)(font "Arial" ))
+		(line (pt 288 64)(pt 272 64)(line_width 3))
+	)
+	(port
+		(pt 288 80)
+		(output)
+		(text "HEX2[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX2[6..0]" (rect 223 75 267 87)(font "Arial" ))
+		(line (pt 288 80)(pt 272 80)(line_width 3))
+	)
+	(port
+		(pt 288 96)
+		(output)
+		(text "HEX3[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX3[6..0]" (rect 223 91 267 103)(font "Arial" ))
+		(line (pt 288 96)(pt 272 96)(line_width 3))
+	)
+	(port
+		(pt 288 128)
+		(output)
+		(text "DRAM_ADDR[11..0]" (rect 0 0 90 12)(font "Arial" ))
+		(text "DRAM_ADDR[11..0]" (rect 177 123 267 135)(font "Arial" ))
+		(line (pt 288 128)(pt 272 128)(line_width 3))
+	)
+	(port
+		(pt 288 144)
+		(output)
+		(text "DRAM_LDQM" (rect 0 0 66 12)(font "Arial" ))
+		(text "DRAM_LDQM" (rect 201 139 267 151)(font "Arial" ))
+		(line (pt 288 144)(pt 272 144)(line_width 1))
+	)
+	(port
+		(pt 288 160)
+		(output)
+		(text "DRAM_UDQM" (rect 0 0 67 12)(font "Arial" ))
+		(text "DRAM_UDQM" (rect 200 155 267 167)(font "Arial" ))
+		(line (pt 288 160)(pt 272 160)(line_width 1))
+	)
+	(port
+		(pt 288 176)
+		(output)
+		(text "DRAM_WE_N" (rect 0 0 68 12)(font "Arial" ))
+		(text "DRAM_WE_N" (rect 199 171 267 183)(font "Arial" ))
+		(line (pt 288 176)(pt 272 176)(line_width 1))
+	)
+	(port
+		(pt 288 192)
+		(output)
+		(text "DRAM_CAS_N" (rect 0 0 71 12)(font "Arial" ))
+		(text "DRAM_CAS_N" (rect 196 187 267 199)(font "Arial" ))
+		(line (pt 288 192)(pt 272 192)(line_width 1))
+	)
+	(port
+		(pt 288 208)
+		(output)
+		(text "DRAM_RAS_N" (rect 0 0 73 12)(font "Arial" ))
+		(text "DRAM_RAS_N" (rect 194 203 267 215)(font "Arial" ))
+		(line (pt 288 208)(pt 272 208)(line_width 1))
+	)
+	(port
+		(pt 288 224)
+		(output)
+		(text "DRAM_CS_N" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_CS_N" (rect 204 219 267 231)(font "Arial" ))
+		(line (pt 288 224)(pt 272 224)(line_width 1))
+	)
+	(port
+		(pt 288 240)
+		(output)
+		(text "DRAM_BA_0" (rect 0 0 62 12)(font "Arial" ))
+		(text "DRAM_BA_0" (rect 205 235 267 247)(font "Arial" ))
+		(line (pt 288 240)(pt 272 240)(line_width 1))
+	)
+	(port
+		(pt 288 256)
+		(output)
+		(text "DRAM_BA_1" (rect 0 0 61 12)(font "Arial" ))
+		(text "DRAM_BA_1" (rect 206 251 267 263)(font "Arial" ))
+		(line (pt 288 256)(pt 272 256)(line_width 1))
+	)
+	(port
+		(pt 288 272)
+		(output)
+		(text "DRAM_CLK" (rect 0 0 57 12)(font "Arial" ))
+		(text "DRAM_CLK" (rect 210 267 267 279)(font "Arial" ))
+		(line (pt 288 272)(pt 272 272)(line_width 1))
+	)
+	(port
+		(pt 288 288)
+		(output)
+		(text "DRAM_CKE" (rect 0 0 59 12)(font "Arial" ))
+		(text "DRAM_CKE" (rect 208 283 267 295)(font "Arial" ))
+		(line (pt 288 288)(pt 272 288)(line_width 1))
+	)
+	(port
+		(pt 288 304)
+		(output)
+		(text "VGA_HS" (rect 0 0 42 12)(font "Arial" ))
+		(text "VGA_HS" (rect 225 299 267 311)(font "Arial" ))
+		(line (pt 288 304)(pt 272 304)(line_width 1))
+	)
+	(port
+		(pt 288 320)
+		(output)
+		(text "VGA_VS" (rect 0 0 43 12)(font "Arial" ))
+		(text "VGA_VS" (rect 224 315 267 327)(font "Arial" ))
+		(line (pt 288 320)(pt 272 320)(line_width 1))
+	)
+	(port
+		(pt 288 336)
+		(output)
+		(text "VGA_R[9..0]" (rect 0 0 57 12)(font "Arial" ))
+		(text "VGA_R[9..0]" (rect 210 331 267 343)(font "Arial" ))
+		(line (pt 288 336)(pt 272 336)(line_width 3))
+	)
+	(port
+		(pt 288 352)
+		(output)
+		(text "VGA_G[9..0]" (rect 0 0 56 12)(font "Arial" ))
+		(text "VGA_G[9..0]" (rect 211 347 267 359)(font "Arial" ))
+		(line (pt 288 352)(pt 272 352)(line_width 3))
+	)
+	(port
+		(pt 288 368)
+		(output)
+		(text "VGA_B[9..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "VGA_B[9..0]" (rect 212 363 267 375)(font "Arial" ))
+		(line (pt 288 368)(pt 272 368)(line_width 3))
+	)
+	(port
+		(pt 288 384)
+		(output)
+		(text "VGA_CLK" (rect 0 0 49 12)(font "Arial" ))
+		(text "VGA_CLK" (rect 218 379 267 391)(font "Arial" ))
+		(line (pt 288 384)(pt 272 384)(line_width 1))
+	)
+	(port
+		(pt 288 400)
+		(output)
+		(text "VGA_X[11..0]" (rect 0 0 57 12)(font "Arial" ))
+		(text "VGA_X[11..0]" (rect 210 395 267 407)(font "Arial" ))
+		(line (pt 288 400)(pt 272 400)(line_width 3))
+	)
+	(port
+		(pt 288 416)
+		(output)
+		(text "VGA_Y[11..0]" (rect 0 0 59 12)(font "Arial" ))
+		(text "VGA_Y[11..0]" (rect 208 411 267 423)(font "Arial" ))
+		(line (pt 288 416)(pt 272 416)(line_width 3))
+	)
+	(port
+		(pt 288 432)
+		(output)
+		(text "VGA_ACTIVE" (rect 0 0 68 12)(font "Arial" ))
+		(text "VGA_ACTIVE" (rect 199 427 267 439)(font "Arial" ))
+		(line (pt 288 432)(pt 272 432)(line_width 1))
+	)
+	(port
+		(pt 288 448)
+		(output)
+		(text "GPIO_1_CLKOUT[1..0]" (rect 0 0 96 12)(font "Arial" ))
+		(text "GPIO_1_CLKOUT[1..0]" (rect 171 443 267 455)(font "Arial" ))
+		(line (pt 288 448)(pt 272 448)(line_width 3))
+	)
+	(port
+		(pt 288 112)
+		(bidir)
+		(text "DRAM_DQ[15..0]" (rect 0 0 75 12)(font "Arial" ))
+		(text "DRAM_DQ[15..0]" (rect 192 107 267 119)(font "Arial" ))
+		(line (pt 288 112)(pt 272 112)(line_width 3))
+	)
+	(port
+		(pt 288 464)
+		(bidir)
+		(text "GPIO_1[31..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "GPIO_1[31..0]" (rect 212 459 267 471)(font "Arial" ))
+		(line (pt 288 464)(pt 272 464)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 480)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.cdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.cdf
new file mode 100644
index 0000000..268964b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.cdf
@@ -0,0 +1,13 @@
+/* Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP3C16F484) Path("E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/") File("DE0_D5M.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.done b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.done
new file mode 100644
index 0000000..159310e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.done
@@ -0,0 +1 @@
+Tue Mar 08 16:25:18 2016
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt
new file mode 100644
index 0000000..f7f5b8a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt
@@ -0,0 +1,4169 @@
+Fitter report for DE0_D5M
+Tue Mar 08 16:24:30 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Ignored Assignments
+  7. Incremental Compilation Preservation Summary
+  8. Incremental Compilation Partition Settings
+  9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. Bidir Pins
+ 16. Dual Purpose and Dedicated Pins
+ 17. I/O Bank Usage
+ 18. All Package Pins
+ 19. PLL Summary
+ 20. PLL Usage
+ 21. Fitter Resource Utilization by Entity
+ 22. Delay Chain Summary
+ 23. Pad To Core Delay Chain Fanout
+ 24. Control Signals
+ 25. Global & Other Fast Signals
+ 26. Non-Global High Fan-Out Signals
+ 27. Fitter RAM Summary
+ 28. Other Routing Usage Summary
+ 29. LAB Logic Elements
+ 30. LAB-wide Signals
+ 31. LAB Signals Sourced
+ 32. LAB Signals Sourced Out
+ 33. LAB Distinct Inputs
+ 34. I/O Rules Summary
+ 35. I/O Rules Details
+ 36. I/O Rules Matrix
+ 37. Fitter Device Options
+ 38. Operating Settings and Conditions
+ 39. Estimated Delay Added for Hold Timing Summary
+ 40. Estimated Delay Added for Hold Timing Details
+ 41. Fitter Messages
+ 42. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Fitter Summary                                                                        ;
++------------------------------------+--------------------------------------------------+
+; Fitter Status                      ; Successful - Tue Mar 08 16:24:30 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                          ;
+; Top-level Entity Name              ; TOP_DE0_CAMERA_MOUSE                             ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 3,638 / 15,408 ( 24 % )                          ;
+;     Total combinational functions  ; 3,247 / 15,408 ( 21 % )                          ;
+;     Dedicated logic registers      ; 1,389 / 15,408 ( 9 % )                           ;
+; Total registers                    ; 1389                                             ;
+; Total pins                         ; 143 / 347 ( 41 % )                               ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 134,236 / 516,096 ( 26 % )                       ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                                   ;
++------------------------------------+--------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Use smart compilation                                                      ; On                                    ; Off                                   ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 3.3-V LVTTL                           ;                                       ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.09        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;   3.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------+
+; I/O Assignment Warnings                   ;
++------------------+------------------------+
+; Pin Name         ; Reason                 ;
++------------------+------------------------+
+; DRAM_LDQM        ; Missing drive strength ;
+; DRAM_UDQM        ; Missing drive strength ;
+; DRAM_BA_1        ; Missing drive strength ;
+; DRAM_BA_0        ; Missing drive strength ;
+; DRAM_CAS_N       ; Missing drive strength ;
+; DRAM_CKE         ; Missing drive strength ;
+; DRAM_CS_N        ; Missing drive strength ;
+; DRAM_RAS_N       ; Missing drive strength ;
+; DRAM_WE_N        ; Missing drive strength ;
+; DRAM_CLK         ; Missing drive strength ;
+; VGA_CLK          ; Missing drive strength ;
+; VGA_HS           ; Missing drive strength ;
+; VGA_VS           ; Missing drive strength ;
+; DRAM_ADDR[11]    ; Missing drive strength ;
+; DRAM_ADDR[10]    ; Missing drive strength ;
+; DRAM_ADDR[9]     ; Missing drive strength ;
+; DRAM_ADDR[8]     ; Missing drive strength ;
+; DRAM_ADDR[7]     ; Missing drive strength ;
+; DRAM_ADDR[6]     ; Missing drive strength ;
+; DRAM_ADDR[5]     ; Missing drive strength ;
+; DRAM_ADDR[4]     ; Missing drive strength ;
+; DRAM_ADDR[3]     ; Missing drive strength ;
+; DRAM_ADDR[2]     ; Missing drive strength ;
+; DRAM_ADDR[1]     ; Missing drive strength ;
+; DRAM_ADDR[0]     ; Missing drive strength ;
+; GPIO_1_CLKOUT[1] ; Missing drive strength ;
+; GPIO_1_CLKOUT[0] ; Missing drive strength ;
+; HEX0[6]          ; Missing drive strength ;
+; HEX0[5]          ; Missing drive strength ;
+; HEX0[4]          ; Missing drive strength ;
+; HEX0[3]          ; Missing drive strength ;
+; HEX0[2]          ; Missing drive strength ;
+; HEX0[1]          ; Missing drive strength ;
+; HEX0[0]          ; Missing drive strength ;
+; HEX1[6]          ; Missing drive strength ;
+; HEX1[5]          ; Missing drive strength ;
+; HEX1[4]          ; Missing drive strength ;
+; HEX1[3]          ; Missing drive strength ;
+; HEX1[2]          ; Missing drive strength ;
+; HEX1[1]          ; Missing drive strength ;
+; HEX1[0]          ; Missing drive strength ;
+; HEX2[6]          ; Missing drive strength ;
+; HEX2[5]          ; Missing drive strength ;
+; HEX2[4]          ; Missing drive strength ;
+; HEX2[3]          ; Missing drive strength ;
+; HEX2[2]          ; Missing drive strength ;
+; HEX2[1]          ; Missing drive strength ;
+; HEX2[0]          ; Missing drive strength ;
+; HEX3[6]          ; Missing drive strength ;
+; HEX3[5]          ; Missing drive strength ;
+; HEX3[4]          ; Missing drive strength ;
+; HEX3[3]          ; Missing drive strength ;
+; HEX3[2]          ; Missing drive strength ;
+; HEX3[1]          ; Missing drive strength ;
+; HEX3[0]          ; Missing drive strength ;
+; LEDG[9]          ; Missing drive strength ;
+; LEDG[8]          ; Missing drive strength ;
+; LEDG[7]          ; Missing drive strength ;
+; LEDG[6]          ; Missing drive strength ;
+; LEDG[5]          ; Missing drive strength ;
+; LEDG[4]          ; Missing drive strength ;
+; LEDG[3]          ; Missing drive strength ;
+; LEDG[2]          ; Missing drive strength ;
+; LEDG[1]          ; Missing drive strength ;
+; LEDG[0]          ; Missing drive strength ;
+; VGA_B[3]         ; Missing drive strength ;
+; VGA_B[2]         ; Missing drive strength ;
+; VGA_B[1]         ; Missing drive strength ;
+; VGA_B[0]         ; Missing drive strength ;
+; VGA_G[3]         ; Missing drive strength ;
+; VGA_G[2]         ; Missing drive strength ;
+; VGA_G[1]         ; Missing drive strength ;
+; VGA_G[0]         ; Missing drive strength ;
+; VGA_R[3]         ; Missing drive strength ;
+; VGA_R[2]         ; Missing drive strength ;
+; VGA_R[1]         ; Missing drive strength ;
+; VGA_R[0]         ; Missing drive strength ;
+; DRAM_DQ[15]      ; Missing drive strength ;
+; DRAM_DQ[14]      ; Missing drive strength ;
+; DRAM_DQ[13]      ; Missing drive strength ;
+; DRAM_DQ[12]      ; Missing drive strength ;
+; DRAM_DQ[11]      ; Missing drive strength ;
+; DRAM_DQ[10]      ; Missing drive strength ;
+; DRAM_DQ[9]       ; Missing drive strength ;
+; DRAM_DQ[8]       ; Missing drive strength ;
+; DRAM_DQ[7]       ; Missing drive strength ;
+; DRAM_DQ[6]       ; Missing drive strength ;
+; DRAM_DQ[5]       ; Missing drive strength ;
+; DRAM_DQ[4]       ; Missing drive strength ;
+; DRAM_DQ[3]       ; Missing drive strength ;
+; DRAM_DQ[2]       ; Missing drive strength ;
+; DRAM_DQ[1]       ; Missing drive strength ;
+; DRAM_DQ[0]       ; Missing drive strength ;
+; GPIO_1[31]       ; Missing drive strength ;
+; GPIO_1[30]       ; Missing drive strength ;
+; GPIO_1[29]       ; Missing drive strength ;
+; GPIO_1[28]       ; Missing drive strength ;
+; GPIO_1[27]       ; Missing drive strength ;
+; GPIO_1[26]       ; Missing drive strength ;
+; GPIO_1[25]       ; Missing drive strength ;
+; GPIO_1[24]       ; Missing drive strength ;
+; GPIO_1[23]       ; Missing drive strength ;
+; GPIO_1[22]       ; Missing drive strength ;
+; GPIO_1[21]       ; Missing drive strength ;
+; GPIO_1[20]       ; Missing drive strength ;
+; GPIO_1[19]       ; Missing drive strength ;
+; GPIO_1[18]       ; Missing drive strength ;
+; GPIO_1[17]       ; Missing drive strength ;
+; GPIO_1[16]       ; Missing drive strength ;
+; GPIO_1[15]       ; Missing drive strength ;
+; GPIO_1[14]       ; Missing drive strength ;
+; GPIO_1[13]       ; Missing drive strength ;
+; GPIO_1[12]       ; Missing drive strength ;
+; GPIO_1[11]       ; Missing drive strength ;
+; GPIO_1[10]       ; Missing drive strength ;
+; GPIO_1[9]        ; Missing drive strength ;
+; GPIO_1[8]        ; Missing drive strength ;
+; GPIO_1[7]        ; Missing drive strength ;
+; GPIO_1[6]        ; Missing drive strength ;
+; GPIO_1[5]        ; Missing drive strength ;
+; GPIO_1[4]        ; Missing drive strength ;
+; GPIO_1[3]        ; Missing drive strength ;
+; GPIO_1[2]        ; Missing drive strength ;
+; GPIO_1[1]        ; Missing drive strength ;
+; GPIO_1[0]        ; Missing drive strength ;
+; PS2_DAT          ; Missing drive strength ;
+; PS2_CLK          ; Missing drive strength ;
++------------------+------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                                          ;
++---------------------+----------------------+--------------+-----------------+---------------+----------------+
+; Name                ; Ignored Entity       ; Ignored From ; Ignored To      ; Ignored Value ; Ignored Source ;
++---------------------+----------------------+--------------+-----------------+---------------+----------------+
+; Location            ;                      ;              ; CLOCK_50_2      ; PIN_B12       ; QSF Assignment ;
+; Location            ;                      ;              ; DRAM_ADDR[12]   ; PIN_C8        ; QSF Assignment ;
+; Location            ;                      ;              ; HEX0_DP         ; PIN_D13       ; QSF Assignment ;
+; Location            ;                      ;              ; HEX1_DP         ; PIN_B15       ; QSF Assignment ;
+; Location            ;                      ;              ; HEX2_DP         ; PIN_A18       ; QSF Assignment ;
+; Location            ;                      ;              ; HEX3_DP         ; PIN_G16       ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; AUD_ADCDAT      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; AUD_ADCLRCK     ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; AUD_BCLK        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; AUD_DACDAT      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; AUD_DACLRCK     ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; AUD_XCK         ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; BUTTON[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; BUTTON[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; BUTTON[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; CLOCK_50_2      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; DRAM_ADDR[12]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[16]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[17]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[18]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[19]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[20]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[21]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_BYTE_N       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_CE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ15_AM1     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[0]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[10]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[11]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[12]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[13]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[14]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[1]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[2]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[3]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[4]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[5]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[6]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[7]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[8]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[9]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_OE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_RST_N        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_RY           ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_WE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO0_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO0_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO0_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO0_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO1_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO1_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO1_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO1_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO_1[32]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO_1[33]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO_1[34]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO_1[35]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; I2C_SCLK        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; I2C_SDAT        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; KEY[3]          ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_BLON        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[4]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[5]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[6]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[7]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_EN          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_RS          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_RW          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; PS2_KBCLK       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; PS2_KBDAT       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; SD_CLK          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; SD_CMD          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; SD_DAT0         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; SD_DAT3         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; SD_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; UART_CTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; UART_RTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; UART_RXD        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; UART_TXD        ; 3.3-V LVTTL   ; QSF Assignment ;
+; Fast Input Register ; TOP_DE0_CAMERA_MOUSE ;              ; rCCD_DATA       ; ON            ; QSF Assignment ;
+; Fast Input Register ; TOP_DE0_CAMERA_MOUSE ;              ; rCCD_FVAL       ; ON            ; QSF Assignment ;
+; Fast Input Register ; TOP_DE0_CAMERA_MOUSE ;              ; rCCD_LVAL       ; ON            ; QSF Assignment ;
++---------------------+----------------------+--------------+-----------------+---------------+----------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+------------------------+
+; Type                ; Value                  ;
++---------------------+------------------------+
+; Placement (by node) ;                        ;
+;     -- Requested    ; 0 / 5169 ( 0.00 % )    ;
+;     -- Achieved     ; 0 / 5169 ( 0.00 % )    ;
+;                     ;                        ;
+; Routing (by net)    ;                        ;
+;     -- Requested    ; 0 / 0 ( 0.00 % )       ;
+;     -- Achieved     ; 0 / 0 ( 0.00 % )       ;
++---------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                             ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name                 ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Top                            ; 5158    ; 0                 ; N/A                     ; Source File       ;
+; hard_block:auto_generated_inst ; 11      ; 0                 ; N/A                     ; Source File       ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pin.
+
+
++--------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                            ;
++---------------------------------------------+----------------------------+
+; Resource                                    ; Usage                      ;
++---------------------------------------------+----------------------------+
+; Total logic elements                        ; 3,638 / 15,408 ( 24 % )    ;
+;     -- Combinational with no register       ; 2249                       ;
+;     -- Register only                        ; 391                        ;
+;     -- Combinational with a register        ; 998                        ;
+;                                             ;                            ;
+; Logic element usage by number of LUT inputs ;                            ;
+;     -- 4 input functions                    ; 769                        ;
+;     -- 3 input functions                    ; 1533                       ;
+;     -- <=2 input functions                  ; 945                        ;
+;     -- Register only                        ; 391                        ;
+;                                             ;                            ;
+; Logic elements by mode                      ;                            ;
+;     -- normal mode                          ; 1626                       ;
+;     -- arithmetic mode                      ; 1621                       ;
+;                                             ;                            ;
+; Total registers*                            ; 1,389 / 17,068 ( 8 % )     ;
+;     -- Dedicated logic registers            ; 1,389 / 15,408 ( 9 % )     ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )          ;
+;                                             ;                            ;
+; Total LABs:  partially or completely used   ; 293 / 963 ( 30 % )         ;
+; Virtual pins                                ; 0                          ;
+; I/O pins                                    ; 143 / 347 ( 41 % )         ;
+;     -- Clock pins                           ; 2 / 8 ( 25 % )             ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )              ;
+;                                             ;                            ;
+; Global signals                              ; 11                         ;
+; M9Ks                                        ; 20 / 56 ( 36 % )           ;
+; Total block memory bits                     ; 134,236 / 516,096 ( 26 % ) ;
+; Total block memory implementation bits      ; 184,320 / 516,096 ( 36 % ) ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )            ;
+; PLLs                                        ; 1 / 4 ( 25 % )             ;
+; Global clocks                               ; 11 / 20 ( 55 % )           ;
+; JTAGs                                       ; 0 / 1 ( 0 % )              ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )              ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )              ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )              ;
+; Average interconnect usage (total/H/V)      ; 6% / 6% / 6%               ;
+; Peak interconnect usage (total/H/V)         ; 20% / 19% / 22%            ;
+; Maximum fan-out                             ; 512                        ;
+; Highest non-global fan-out                  ; 325                        ;
+; Total fan-out                               ; 14749                      ;
+; Average fan-out                             ; 2.79                       ;
++---------------------------------------------+----------------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                          ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                   ; Top                   ; hard_block:auto_generated_inst ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                   ; Low                            ;
+;                                             ;                       ;                                ;
+; Total logic elements                        ; 3638 / 15408 ( 24 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 2249                  ; 0                              ;
+;     -- Register only                        ; 391                   ; 0                              ;
+;     -- Combinational with a register        ; 998                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic element usage by number of LUT inputs ;                       ;                                ;
+;     -- 4 input functions                    ; 769                   ; 0                              ;
+;     -- 3 input functions                    ; 1533                  ; 0                              ;
+;     -- <=2 input functions                  ; 945                   ; 0                              ;
+;     -- Register only                        ; 391                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic elements by mode                      ;                       ;                                ;
+;     -- normal mode                          ; 1626                  ; 0                              ;
+;     -- arithmetic mode                      ; 1621                  ; 0                              ;
+;                                             ;                       ;                                ;
+; Total registers                             ; 1389                  ; 0                              ;
+;     -- Dedicated logic registers            ; 1389 / 15408 ( 9 % )  ; 0 / 15408 ( 0 % )              ;
+;                                             ;                       ;                                ;
+; Total LABs:  partially or completely used   ; 293 / 963 ( 30 % )    ; 0 / 963 ( 0 % )                ;
+;                                             ;                       ;                                ;
+; Virtual pins                                ; 0                     ; 0                              ;
+; I/O pins                                    ; 143                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 134236                ; 0                              ;
+; Total RAM block bits                        ; 184320                ; 0                              ;
+; PLL                                         ; 0 / 4 ( 0 % )         ; 1 / 4 ( 25 % )                 ;
+; M9K                                         ; 20 / 56 ( 35 % )      ; 0 / 56 ( 0 % )                 ;
+; Clock control block                         ; 9 / 24 ( 37 % )       ; 2 / 24 ( 8 % )                 ;
+;                                             ;                       ;                                ;
+; Connections                                 ;                       ;                                ;
+;     -- Input Connections                    ; 563                   ; 1                              ;
+;     -- Registered Input Connections         ; 512                   ; 0                              ;
+;     -- Output Connections                   ; 51                    ; 513                            ;
+;     -- Registered Output Connections        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Internal Connections                        ;                       ;                                ;
+;     -- Total Connections                    ; 14995                 ; 521                            ;
+;     -- Registered Connections               ; 5185                  ; 0                              ;
+;                                             ;                       ;                                ;
+; External Connections                        ;                       ;                                ;
+;     -- Top                                  ; 100                   ; 514                            ;
+;     -- hard_block:auto_generated_inst       ; 514                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Partition Interface                         ;                       ;                                ;
+;     -- Input Ports                          ; 16                    ; 1                              ;
+;     -- Output Ports                         ; 77                    ; 2                              ;
+;     -- Bidir Ports                          ; 50                    ; 0                              ;
+;                                             ;                       ;                                ;
+; Registered Ports                            ;                       ;                                ;
+;     -- Registered Input Ports               ; 0                     ; 0                              ;
+;     -- Registered Output Ports              ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Port Connectivity                           ;                       ;                                ;
+;     -- Input Ports driven by GND            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                     ; 0                              ;
++---------------------------------------------+-----------------------+--------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                           ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name            ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; CLOCK_50        ; G21   ; 6        ; 41           ; 15           ; 0            ; 106                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; GPIO_1_CLKIN[0] ; AB11  ; 3        ; 21           ; 0            ; 14           ; 229                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; GPIO_1_CLKIN[1] ; AA11  ; 3        ; 21           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[0]          ; H2    ; 1        ; 0            ; 21           ; 7            ; 325                   ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[1]          ; G3    ; 1        ; 0            ; 23           ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[2]          ; F1    ; 1        ; 0            ; 23           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[0]           ; J6    ; 1        ; 0            ; 24           ; 0            ; 25                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[1]           ; H5    ; 1        ; 0            ; 27           ; 0            ; 6                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[2]           ; H6    ; 1        ; 0            ; 25           ; 21           ; 14                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[3]           ; G4    ; 1        ; 0            ; 23           ; 7            ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[4]           ; G5    ; 1        ; 0            ; 27           ; 21           ; 22                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[5]           ; J7    ; 1        ; 0            ; 22           ; 14           ; 22                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[6]           ; H7    ; 1        ; 0            ; 25           ; 14           ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[7]           ; E3    ; 1        ; 0            ; 26           ; 7            ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[8]           ; E4    ; 1        ; 0            ; 26           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[9]           ; D2    ; 1        ; 0            ; 25           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name             ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; DRAM_ADDR[0]     ; C4    ; 8        ; 1            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[10]    ; B4    ; 8        ; 5            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[11]    ; A7    ; 8        ; 11           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[1]     ; A3    ; 8        ; 3            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[2]     ; B3    ; 8        ; 3            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[3]     ; C3    ; 8        ; 3            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[4]     ; A5    ; 8        ; 7            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[5]     ; C6    ; 8        ; 5            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[6]     ; B6    ; 8        ; 11           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[7]     ; A6    ; 8        ; 11           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[8]     ; C7    ; 8        ; 9            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[9]     ; B7    ; 8        ; 11           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_BA_0        ; B5    ; 8        ; 7            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_BA_1        ; A4    ; 8        ; 5            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CAS_N       ; G8    ; 8        ; 5            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CKE         ; E6    ; 8        ; 1            ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CLK         ; E5    ; 8        ; 1            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CS_N        ; G7    ; 8        ; 1            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_LDQM        ; E7    ; 8        ; 3            ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_RAS_N       ; F7    ; 8        ; 1            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_UDQM        ; B8    ; 8        ; 14           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_WE_N        ; D6    ; 8        ; 3            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_CLKOUT[0] ; R16   ; 4        ; 37           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_CLKOUT[1] ; T16   ; 4        ; 37           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[0]          ; E11   ; 7        ; 21           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[1]          ; F11   ; 7        ; 21           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[2]          ; H12   ; 7        ; 26           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[3]          ; H13   ; 7        ; 28           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[4]          ; G12   ; 7        ; 26           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[5]          ; F12   ; 7        ; 28           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[6]          ; F13   ; 7        ; 26           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[0]          ; A13   ; 7        ; 21           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[1]          ; B13   ; 7        ; 21           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[2]          ; C13   ; 7        ; 23           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[3]          ; A14   ; 7        ; 23           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[4]          ; B14   ; 7        ; 23           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[5]          ; E14   ; 7        ; 28           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[6]          ; A15   ; 7        ; 26           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[0]          ; D15   ; 7        ; 32           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[1]          ; A16   ; 7        ; 30           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[2]          ; B16   ; 7        ; 28           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[3]          ; E15   ; 7        ; 30           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[4]          ; A17   ; 7        ; 30           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[5]          ; B17   ; 7        ; 30           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[6]          ; F14   ; 7        ; 37           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[0]          ; B18   ; 7        ; 32           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[1]          ; F15   ; 7        ; 39           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[2]          ; A19   ; 7        ; 32           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[3]          ; B19   ; 7        ; 32           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[4]          ; C19   ; 7        ; 37           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[5]          ; D19   ; 7        ; 37           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[6]          ; G15   ; 7        ; 39           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[0]          ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[1]          ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[2]          ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[3]          ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[4]          ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[5]          ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[6]          ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[7]          ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[8]          ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[9]          ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[0]         ; K22   ; 6        ; 41           ; 19           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[1]         ; K21   ; 6        ; 41           ; 19           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[2]         ; J22   ; 6        ; 41           ; 19           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[3]         ; K18   ; 6        ; 41           ; 21           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_CLK          ; W10   ; 3        ; 19           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; VGA_G[0]         ; H22   ; 6        ; 41           ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[1]         ; J17   ; 6        ; 41           ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[2]         ; K17   ; 6        ; 41           ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[3]         ; J21   ; 6        ; 41           ; 20           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_HS           ; L21   ; 6        ; 41           ; 18           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[0]         ; H19   ; 6        ; 41           ; 23           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[1]         ; H17   ; 6        ; 41           ; 25           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[2]         ; H20   ; 6        ; 41           ; 22           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[3]         ; H21   ; 6        ; 41           ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_VS           ; L22   ; 6        ; 41           ; 18           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+; Name        ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source                                               ; Output Enable Group ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+; DRAM_DQ[0]  ; D10   ; 8        ; 16           ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[10] ; A9    ; 8        ; 16           ; 29           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[11] ; C10   ; 8        ; 14           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[12] ; B10   ; 8        ; 16           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[13] ; A10   ; 8        ; 16           ; 29           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[14] ; E10   ; 8        ; 16           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[15] ; F10   ; 8        ; 7            ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[1]  ; G10   ; 8        ; 9            ; 29           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[2]  ; H10   ; 8        ; 9            ; 29           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[3]  ; E9    ; 8        ; 11           ; 29           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[4]  ; F9    ; 8        ; 7            ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[5]  ; G9    ; 8        ; 9            ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[6]  ; H9    ; 8        ; 7            ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[7]  ; F8    ; 8        ; 5            ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[8]  ; A8    ; 8        ; 14           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[9]  ; B9    ; 8        ; 14           ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; GPIO_1[0]   ; AA20  ; 4        ; 37           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[10]  ; U15   ; 4        ; 39           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[11]  ; T15   ; 4        ; 32           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[12]  ; W15   ; 4        ; 32           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[13]  ; V15   ; 4        ; 32           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[14]  ; AB9   ; 3        ; 16           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[15]  ; AA9   ; 3        ; 16           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[16]  ; AA7   ; 3        ; 11           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[17]  ; AB7   ; 3        ; 11           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[18]  ; T14   ; 4        ; 32           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[19]  ; R14   ; 4        ; 39           ; 0            ; 14           ; 4                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO               ; -                   ;
+; GPIO_1[1]   ; AB20  ; 4        ; 37           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[20]  ; U12   ; 4        ; 26           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[21]  ; T12   ; 4        ; 28           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[22]  ; R11   ; 3        ; 3            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[23]  ; R12   ; 3        ; 5            ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[24]  ; U10   ; 3        ; 14           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[25]  ; T10   ; 3        ; 14           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[26]  ; U9    ; 3        ; 9            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[27]  ; T9    ; 3        ; 1            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[28]  ; Y7    ; 3        ; 9            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[29]  ; U8    ; 3        ; 3            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[2]   ; AA19  ; 4        ; 35           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[30]  ; V6    ; 3        ; 1            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[31]  ; V7    ; 3        ; 7            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[3]   ; AB19  ; 4        ; 35           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[4]   ; AB18  ; 4        ; 32           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[5]   ; AA18  ; 4        ; 35           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[6]   ; AA17  ; 4        ; 28           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[7]   ; AB17  ; 4        ; 28           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[8]   ; Y17   ; 4        ; 35           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[9]   ; W17   ; 4        ; 35           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; PS2_CLK     ; P22   ; 5        ; 41           ; 11           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; ps2:inst6|ce~0 (inverted)                                          ; -                   ;
+; PS2_DAT     ; P21   ; 5        ; 41           ; 12           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; ps2:inst6|de~0 (inverted)                                          ; -                   ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                                      ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                                 ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; E4       ; DIFFIO_L2p, nRESET                       ; Use as regular IO        ; SW[8]                   ; Dual Purpose Pin          ;
+; D1       ; DIFFIO_L4n, DATA1, ASDO                  ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO              ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                                     ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                                    ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                                      ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                                ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L22      ; DIFFIO_R17n, INIT_DONE                   ; Use as regular IO        ; VGA_VS                  ; Dual Purpose Pin          ;
+; L21      ; DIFFIO_R17p, CRC_ERROR                   ; Use as regular IO        ; VGA_HS                  ; Dual Purpose Pin          ;
+; K22      ; DIFFIO_R16n, nCEO                        ; Use as programming pin   ; VGA_B[0]                ; Dual Purpose Pin          ;
+; K21      ; DIFFIO_R16p, CLKUSR                      ; Use as regular IO        ; VGA_B[1]                ; Dual Purpose Pin          ;
+; B18      ; DIFFIO_T27p, PADD0                       ; Use as regular IO        ; HEX3[0]                 ; Dual Purpose Pin          ;
+; A17      ; DIFFIO_T25n, PADD1                       ; Use as regular IO        ; HEX2[4]                 ; Dual Purpose Pin          ;
+; B17      ; DIFFIO_T25p, PADD2                       ; Use as regular IO        ; HEX2[5]                 ; Dual Purpose Pin          ;
+; E14      ; DIFFIO_T23n, PADD3                       ; Use as regular IO        ; HEX1[5]                 ; Dual Purpose Pin          ;
+; F13      ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8    ; Use as regular IO        ; HEX0[6]                 ; Dual Purpose Pin          ;
+; A15      ; DIFFIO_T20n, PADD5                       ; Use as regular IO        ; HEX1[6]                 ; Dual Purpose Pin          ;
+; C13      ; DIFFIO_T19n, PADD7                       ; Use as regular IO        ; HEX1[2]                 ; Dual Purpose Pin          ;
+; A14      ; DIFFIO_T18n, PADD9                       ; Use as regular IO        ; HEX1[3]                 ; Dual Purpose Pin          ;
+; B14      ; DIFFIO_T18p, PADD10                      ; Use as regular IO        ; HEX1[4]                 ; Dual Purpose Pin          ;
+; A13      ; DIFFIO_T17n, PADD11                      ; Use as regular IO        ; HEX1[0]                 ; Dual Purpose Pin          ;
+; B13      ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9   ; Use as regular IO        ; HEX1[1]                 ; Dual Purpose Pin          ;
+; E11      ; DIFFIO_T16n, PADD13                      ; Use as regular IO        ; HEX0[0]                 ; Dual Purpose Pin          ;
+; F11      ; DIFFIO_T16p, PADD14                      ; Use as regular IO        ; HEX0[1]                 ; Dual Purpose Pin          ;
+; B10      ; DIFFIO_T14p, PADD15                      ; Use as regular IO        ; DRAM_DQ[12]             ; Dual Purpose Pin          ;
+; A9       ; DIFFIO_T13n, PADD16                      ; Use as regular IO        ; DRAM_DQ[10]             ; Dual Purpose Pin          ;
+; B9       ; DIFFIO_T13p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO        ; DRAM_DQ[9]              ; Dual Purpose Pin          ;
+; A8       ; DIFFIO_T12n, DATA2                       ; Use as regular IO        ; DRAM_DQ[8]              ; Dual Purpose Pin          ;
+; B8       ; DIFFIO_T12p, DATA3                       ; Use as regular IO        ; DRAM_UDQM               ; Dual Purpose Pin          ;
+; A7       ; DIFFIO_T11n, PADD18                      ; Use as regular IO        ; DRAM_ADDR[11]           ; Dual Purpose Pin          ;
+; B7       ; DIFFIO_T11p, DATA4                       ; Use as regular IO        ; DRAM_ADDR[9]            ; Dual Purpose Pin          ;
+; A6       ; DIFFIO_T10n, PADD19                      ; Use as regular IO        ; DRAM_ADDR[7]            ; Dual Purpose Pin          ;
+; B6       ; DIFFIO_T10p, DATA15                      ; Use as regular IO        ; DRAM_ADDR[6]            ; Dual Purpose Pin          ;
+; C7       ; DIFFIO_T9p, DATA13                       ; Use as regular IO        ; DRAM_ADDR[8]            ; Dual Purpose Pin          ;
+; A5       ; DATA5                                    ; Use as regular IO        ; DRAM_ADDR[4]            ; Dual Purpose Pin          ;
+; F10      ; DIFFIO_T6p, DATA6                        ; Use as regular IO        ; DRAM_DQ[15]             ; Dual Purpose Pin          ;
+; C6       ; DATA7                                    ; Use as regular IO        ; DRAM_ADDR[5]            ; Dual Purpose Pin          ;
+; B4       ; DIFFIO_T5p, DATA8                        ; Use as regular IO        ; DRAM_ADDR[10]           ; Dual Purpose Pin          ;
+; F8       ; DIFFIO_T4n, DATA9                        ; Use as regular IO        ; DRAM_DQ[7]              ; Dual Purpose Pin          ;
+; A3       ; DIFFIO_T3n, DATA10                       ; Use as regular IO        ; DRAM_ADDR[1]            ; Dual Purpose Pin          ;
+; B3       ; DIFFIO_T3p, DATA11                       ; Use as regular IO        ; DRAM_ADDR[2]            ; Dual Purpose Pin          ;
+; C4       ; DIFFIO_T2p, DATA12, DQS1T/CQ1T#,CDPCLK7  ; Use as regular IO        ; DRAM_ADDR[0]            ; Dual Purpose Pin          ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 27 / 33 ( 82 % ) ; 3.3V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 3.3V          ; --           ;
+; 3        ; 17 / 46 ( 37 % ) ; 3.3V          ; --           ;
+; 4        ; 20 / 41 ( 49 % ) ; 3.3V          ; --           ;
+; 5        ; 2 / 46 ( 4 % )   ; 3.3V          ; --           ;
+; 6        ; 15 / 43 ( 35 % ) ; 3.3V          ; --           ;
+; 7        ; 28 / 47 ( 60 % ) ; 3.3V          ; --           ;
+; 8        ; 38 / 43 ( 88 % ) ; 3.3V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; DRAM_ADDR[1]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A4       ; 350        ; 8        ; DRAM_BA_1                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A5       ; 345        ; 8        ; DRAM_ADDR[4]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A6       ; 336        ; 8        ; DRAM_ADDR[7]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A7       ; 334        ; 8        ; DRAM_ADDR[11]                                             ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A8       ; 332        ; 8        ; DRAM_DQ[8]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A9       ; 328        ; 8        ; DRAM_DQ[10]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A10      ; 326        ; 8        ; DRAM_DQ[13]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; HEX1[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A14      ; 312        ; 7        ; HEX1[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A15      ; 307        ; 7        ; HEX1[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A16      ; 298        ; 7        ; HEX2[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A17      ; 296        ; 7        ; HEX2[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; HEX3[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; GPIO_1[16]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; GPIO_1[15]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GPIO_1_CLKIN[1]                                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; GPIO_1[6]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA18     ; 163        ; 4        ; GPIO_1[5]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA19     ; 164        ; 4        ; GPIO_1[2]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA20     ; 169        ; 4        ; GPIO_1[0]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; GPIO_1[17]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; GPIO_1[14]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GPIO_1_CLKIN[0]                                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; GPIO_1[7]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB18     ; 162        ; 4        ; GPIO_1[4]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB19     ; 165        ; 4        ; GPIO_1[3]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB20     ; 170        ; 4        ; GPIO_1[1]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; LEDG[9]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 1          ; 1        ; LEDG[8]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B3       ; 355        ; 8        ; DRAM_ADDR[2]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B4       ; 351        ; 8        ; DRAM_ADDR[10]                                             ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B5       ; 346        ; 8        ; DRAM_BA_0                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B6       ; 337        ; 8        ; DRAM_ADDR[6]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B7       ; 335        ; 8        ; DRAM_ADDR[9]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B8       ; 333        ; 8        ; DRAM_UDQM                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B9       ; 329        ; 8        ; DRAM_DQ[9]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B10      ; 327        ; 8        ; DRAM_DQ[12]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; HEX1[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B14      ; 313        ; 7        ; HEX1[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; HEX2[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B17      ; 297        ; 7        ; HEX2[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B18      ; 292        ; 7        ; HEX3[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B19      ; 289        ; 7        ; HEX3[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; LEDG[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C2       ; 6          ; 1        ; LEDG[7]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 358        ; 8        ; DRAM_ADDR[3]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C4       ; 359        ; 8        ; DRAM_ADDR[0]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; DRAM_ADDR[5]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C7       ; 340        ; 8        ; DRAM_ADDR[8]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; DRAM_DQ[11]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; HEX1[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; HEX3[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; SW[9]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; DRAM_WE_N                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; DRAM_DQ[0]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; HEX2[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; HEX3[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; LEDG[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; SW[7]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E4       ; 4          ; 1        ; SW[8]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E5       ; 363        ; 8        ; DRAM_CLK                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E6       ; 362        ; 8        ; DRAM_CKE                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E7       ; 357        ; 8        ; DRAM_LDQM                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; DRAM_DQ[3]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E10      ; 325        ; 8        ; DRAM_DQ[14]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E11      ; 317        ; 7        ; HEX0[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; HEX1[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E15      ; 294        ; 7        ; HEX2[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; KEY[2]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F2       ; 15         ; 1        ; LEDG[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; DRAM_RAS_N                                                ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F8       ; 352        ; 8        ; DRAM_DQ[7]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F9       ; 347        ; 8        ; DRAM_DQ[4]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F10      ; 348        ; 8        ; DRAM_DQ[15]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F11      ; 318        ; 7        ; HEX0[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F12      ; 302        ; 7        ; HEX0[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F13      ; 306        ; 7        ; HEX0[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F14      ; 279        ; 7        ; HEX2[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F15      ; 276        ; 7        ; HEX3[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; KEY[1]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G4       ; 17         ; 1        ; SW[3]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G5       ; 3          ; 1        ; SW[4]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; DRAM_CS_N                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G8       ; 353        ; 8        ; DRAM_CAS_N                                                ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G9       ; 342        ; 8        ; DRAM_DQ[5]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G10      ; 341        ; 8        ; DRAM_DQ[1]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; HEX0[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; HEX3[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; CLOCK_50                                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; LEDG[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; KEY[0]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; SW[1]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H6       ; 11         ; 1        ; SW[2]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H7       ; 10         ; 1        ; SW[6]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; DRAM_DQ[6]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H10      ; 343        ; 8        ; DRAM_DQ[2]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; HEX0[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H13      ; 303        ; 7        ; HEX0[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; VGA_R[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; VGA_R[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H20      ; 253        ; 6        ; VGA_R[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H21      ; 246        ; 6        ; VGA_R[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H22      ; 245        ; 6        ; VGA_G[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J1       ; 29         ; 1        ; LEDG[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; LEDG[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; LEDG[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; SW[0]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J7       ; 22         ; 1        ; SW[5]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; VGA_G[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; VGA_G[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J22      ; 241        ; 6        ; VGA_B[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; VGA_G[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K18      ; 248        ; 6        ; VGA_B[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; VGA_B[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K22      ; 239        ; 6        ; VGA_B[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; VGA_HS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L22      ; 234        ; 6        ; VGA_VS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; PS2_DAT                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P22      ; 210        ; 5        ; PS2_CLK                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; GPIO_1[22]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R12      ; 98         ; 3        ; GPIO_1[23]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; GPIO_1[19]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; GPIO_1_CLKOUT[0]                                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; GPIO_1[27]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T10      ; 121        ; 3        ; GPIO_1[25]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; GPIO_1[21]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; GPIO_1[18]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T15      ; 161        ; 4        ; GPIO_1[11]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T16      ; 171        ; 4        ; GPIO_1_CLKOUT[1]                                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; GPIO_1[29]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U9       ; 112        ; 3        ; GPIO_1[26]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U10      ; 122        ; 3        ; GPIO_1[24]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; GPIO_1[20]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; GPIO_1[10]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; GPIO_1[30]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V7       ; 105        ; 3        ; GPIO_1[31]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; GPIO_1[13]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; VGA_CLK                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; GPIO_1[12]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; GPIO_1[9]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; GPIO_1[28]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; GPIO_1[8]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; PLL Summary                                                                                                       ;
++-------------------------------+-----------------------------------------------------------------------------------+
+; Name                          ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1 ;
++-------------------------------+-----------------------------------------------------------------------------------+
+; SDC pin name                  ; inst|u6|altpll_component|auto_generated|pll1                                      ;
+; PLL mode                      ; Normal                                                                            ;
+; Compensate clock              ; clock0                                                                            ;
+; Compensated input/output pins ; --                                                                                ;
+; Switchover type               ; --                                                                                ;
+; Input frequency 0             ; 50.0 MHz                                                                          ;
+; Input frequency 1             ; --                                                                                ;
+; Nominal PFD frequency         ; 25.0 MHz                                                                          ;
+; Nominal VCO frequency         ; 625.0 MHz                                                                         ;
+; VCO post scale K counter      ; 2                                                                                 ;
+; VCO frequency control         ; Auto                                                                              ;
+; VCO phase shift step          ; 200 ps                                                                            ;
+; VCO multiply                  ; --                                                                                ;
+; VCO divide                    ; --                                                                                ;
+; Freq min lock                 ; 24.0 MHz                                                                          ;
+; Freq max lock                 ; 52.02 MHz                                                                         ;
+; M VCO Tap                     ; 5                                                                                 ;
+; M Initial                     ; 2                                                                                 ;
+; M value                       ; 25                                                                                ;
+; N value                       ; 2                                                                                 ;
+; Charge pump current           ; setting 1                                                                         ;
+; Loop filter resistance        ; setting 24                                                                        ;
+; Loop filter capacitance       ; setting 0                                                                         ;
+; Bandwidth                     ; 450 kHz to 980 kHz                                                                ;
+; Bandwidth type                ; Medium                                                                            ;
+; Real time reconfigurable      ; Off                                                                               ;
+; Scan chain MIF file           ; --                                                                                ;
+; Preserve PLL counter order    ; Off                                                                               ;
+; PLL location                  ; PLL_2                                                                             ;
+; Inclk0 signal                 ; CLOCK_50                                                                          ;
+; Inclk1 signal                 ; --                                                                                ;
+; Inclk0 signal type            ; Dedicated Pin                                                                     ;
+; Inclk1 signal type            ; --                                                                                ;
++-------------------------------+-----------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Usage                                                                                                                                                                                                                                                                                                             ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+; Name                                                                                ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift     ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                        ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; clock0       ; 5    ; 2   ; 125.0 MHz        ; 0 (0 ps)        ; 9.00 (200 ps)    ; 50/50      ; C0      ; 5             ; 3/2 Odd    ; --            ; 2       ; 5       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; clock1       ; 5    ; 2   ; 125.0 MHz        ; -117 (-2600 ps) ; 9.00 (200 ps)    ; 50/50      ; C1      ; 5             ; 3/2 Odd    ; --            ; 1       ; 0       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                               ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                                                                                  ; Library Name ;
++----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |TOP_DE0_CAMERA_MOUSE                                    ; 3638 (2)    ; 1389 (0)                  ; 0 (0)         ; 134236      ; 20   ; 0            ; 0       ; 0         ; 143  ; 0            ; 2249 (2)     ; 391 (0)           ; 998 (0)          ; |TOP_DE0_CAMERA_MOUSE                                                                                                                                                                ; work         ;
+;    |DE0_D5M:inst|                                        ; 1453 (15)   ; 1013 (15)                 ; 0 (0)         ; 62416       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 439 (0)      ; 281 (14)          ; 733 (1)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst                                                                                                                                                   ; work         ;
+;       |CCD_Capture:u3|                                   ; 42 (42)     ; 33 (33)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 9 (9)        ; 2 (2)             ; 31 (31)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3                                                                                                                                    ; work         ;
+;       |I2C_CCD_Config:u8|                                ; 257 (177)   ; 132 (94)                  ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 124 (82)     ; 17 (6)            ; 116 (89)         ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8                                                                                                                                 ; work         ;
+;          |I2C_Controller:u0|                             ; 80 (80)     ; 38 (38)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 42 (42)      ; 11 (11)           ; 27 (27)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0                                                                                                               ; work         ;
+;       |RAW2RGB:u4|                                       ; 93 (77)     ; 66 (55)                   ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 27 (22)      ; 8 (8)             ; 58 (47)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4                                                                                                                                        ; work         ;
+;          |Line_Buffer:u0|                                ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                                                                                                                         ; work         ;
+;             |altshift_taps:altshift_taps_component|      ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component                                                                                   ; work         ;
+;                |shift_taps_rnn:auto_generated|           ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated                                                     ; work         ;
+;                   |altsyncram_lp81:altsyncram2|          ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2                         ; work         ;
+;                   |cntr_cuf:cntr1|                       ; 16 (13)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (2)        ; 0 (0)             ; 11 (11)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1                                      ; work         ;
+;                      |cmpr_vgc:cmpr4|                    ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4                       ; work         ;
+;       |Reset_Delay:u2|                                   ; 50 (50)     ; 35 (35)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (15)      ; 0 (0)             ; 35 (35)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Reset_Delay:u2                                                                                                                                    ; work         ;
+;       |Sdram_Control_4Port:u7|                           ; 919 (236)   ; 704 (137)                 ; 0 (0)         ; 31744       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 215 (93)     ; 240 (20)          ; 464 (122)        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7                                                                                                                            ; work         ;
+;          |Sdram_FIFO:read_fifo1|                         ; 139 (0)     ; 116 (0)                   ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (0)       ; 54 (0)            ; 62 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 139 (0)     ; 116 (0)                   ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (0)       ; 54 (0)            ; 62 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 139 (40)    ; 116 (30)                  ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (9)       ; 54 (24)           ; 62 (6)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin|      ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 21 (21)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 16 (16)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 1 (1)             ; 13 (13)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (0)            ; 6 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (14)           ; 6 (6)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (0)            ; 7 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (13)           ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:read_fifo2|                         ; 140 (0)     ; 116 (0)                   ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (0)       ; 54 (0)            ; 62 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 140 (0)     ; 116 (0)                   ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (0)       ; 54 (0)            ; 62 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 140 (43)    ; 116 (30)                  ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (10)      ; 54 (23)           ; 62 (6)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin|      ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 22 (22)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 17 (17)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 15 (15)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:write_fifo1|                        ; 141 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (0)       ; 56 (0)            ; 61 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 141 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (0)       ; 56 (0)            ; 61 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 141 (43)    ; 116 (30)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (8)       ; 56 (26)           ; 61 (7)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 14 (14)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 22 (22)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 17 (17)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (0)            ; 7 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (13)           ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (0)            ; 6 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (14)           ; 6 (6)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |Sdram_FIFO:write_fifo2|                        ; 134 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 17 (0)       ; 41 (0)            ; 76 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 134 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 17 (0)       ; 41 (0)            ; 76 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 134 (41)    ; 116 (30)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 17 (4)       ; 41 (17)           ; 76 (17)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 14 (14)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 22 (22)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 17 (17)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 8 (0)             ; 12 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 12 (12)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |command:command1|                              ; 61 (61)     ; 48 (48)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 12 (12)      ; 1 (1)             ; 48 (48)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1                                                                                                           ; work         ;
+;          |control_interface:control1|                    ; 78 (78)     ; 55 (55)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 22 (22)      ; 14 (14)           ; 42 (42)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1                                                                                                 ; work         ;
+;       |VGA_Controller:u1|                                ; 80 (80)     ; 28 (28)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 49 (49)      ; 0 (0)             ; 31 (31)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1                                                                                                                                 ; work         ;
+;       |sdram_pll:u6|                                     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6                                                                                                                                      ; work         ;
+;          |altpll:altpll_component|                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component                                                                                                              ; work         ;
+;             |altpll_9ee2:auto_generated|                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated                                                                                   ; work         ;
+;    |altshift_taps:fifo_inst2|                            ; 15 (0)      ; 10 (0)                    ; 0 (0)         ; 71820       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 10 (0)           ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2                                                                                                                                       ; work         ;
+;       |shift_taps_jpm:auto_generated|                    ; 15 (0)      ; 10 (0)                    ; 0 (0)         ; 71820       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 10 (0)           ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated                                                                                                         ; work         ;
+;          |altsyncram_5n81:altsyncram2|                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 71820       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2                                                                             ; work         ;
+;          |cntr_1tf:cntr1|                                ; 15 (12)     ; 10 (10)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (2)        ; 0 (0)             ; 10 (10)          ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1                                                                                          ; work         ;
+;             |cmpr_ugc:cmpr4|                             ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|cmpr_ugc:cmpr4                                                                           ; work         ;
+;    |ps2:inst6|                                           ; 139 (111)   ; 99 (99)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 40 (12)      ; 37 (37)           ; 62 (62)          ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6                                                                                                                                                      ; work         ;
+;       |SEG7_LUT:U1|                                      ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U1                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U2|                                      ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U2                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U3|                                      ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U3                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U4|                                      ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U4                                                                                                                                          ; work         ;
+;    |sobel:inst1|                                         ; 1909 (0)    ; 255 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1654 (0)     ; 73 (0)            ; 182 (0)          ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1                                                                                                                                                    ; work         ;
+;       |sobel_core:sobel_core_inst|                       ; 1909 (1871) ; 255 (255)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1654 (1616)  ; 73 (73)           ; 182 (180)        ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst                                                                                                                         ; work         ;
+;          |lpm_mult:Mult0|                                ; 3 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult1|                                ; 5 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult2|                                ; 2 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult3|                                ; 6 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult3                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult4|                                ; 6 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult5|                                ; 6 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult6|                                ; 4 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 4 (4)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult7|                                ; 2 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult8|                                ; 6 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult8                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult8|multcore:mult_core                                                                                       ; work         ;
+;    |vga_mouse_square:vga_mouse_catapult_inst|            ; 101 (0)     ; 12 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 89 (0)       ; 0 (0)             ; 12 (0)           ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst                                                                                                                       ; work         ;
+;       |vga_mouse_square_core:vga_mouse_square_core_inst| ; 101 (101)   ; 12 (12)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 89 (89)      ; 0 (0)             ; 12 (12)          ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst                                                                      ; work         ;
+;    |vga_mux:inst10|                                      ; 24 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 20 (0)       ; 0 (0)             ; 4 (0)            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10                                                                                                                                                 ; work         ;
+;       |lpm_mux:LPM_MUX_component|                        ; 24 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 20 (0)       ; 0 (0)             ; 4 (0)            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component                                                                                                                       ; work         ;
+;          |mux_u7e:auto_generated|                        ; 24 (24)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 20 (20)      ; 0 (0)             ; 4 (4)            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated                                                                                                ; work         ;
++----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                              ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name             ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+; DRAM_LDQM        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKIN[1]  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[9]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[8]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_UDQM        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_BA_1        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_BA_0        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CAS_N       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CKE         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CS_N        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_RAS_N       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_WE_N        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CLK         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_CLK          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_HS           ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_VS           ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[11]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[10]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[9]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[8]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[7]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[6]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[5]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[4]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[3]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[2]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[1]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[0]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKOUT[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKOUT[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[9]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[8]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[7]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[15]      ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[14]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[13]      ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[12]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[11]      ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[10]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[9]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[8]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[7]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[6]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[5]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[4]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[3]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[2]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[1]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[0]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[31]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[30]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[29]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[28]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[27]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[26]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[25]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[24]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[23]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[22]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[21]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[20]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[19]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[18]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[17]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[16]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[15]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[14]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[13]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[12]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[11]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[10]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[9]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[8]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[7]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[6]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[5]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[4]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[3]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[2]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[1]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[0]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; PS2_DAT          ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; PS2_CLK          ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[4]            ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[5]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; CLOCK_50         ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; KEY[0]           ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[7]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[6]            ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[3]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[2]            ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[1]            ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[0]            ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; KEY[1]           ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1_CLKIN[0]  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; KEY[2]           ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                                                                                                             ;
++----------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                                                                                                          ; Pad To Core Index ; Setting ;
++----------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; GPIO_1_CLKIN[1]                                                                                                                              ;                   ;         ;
+; SW[9]                                                                                                                                        ;                   ;         ;
+; SW[8]                                                                                                                                        ;                   ;         ;
+; DRAM_DQ[15]                                                                                                                                  ;                   ;         ;
+; DRAM_DQ[14]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]                                                                                      ; 0                 ; 6       ;
+; DRAM_DQ[13]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13]~feeder                                                                               ; 1                 ; 6       ;
+; DRAM_DQ[12]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12]~feeder                                                                               ; 0                 ; 6       ;
+; DRAM_DQ[11]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[11]~feeder                                                                               ; 1                 ; 6       ;
+; DRAM_DQ[10]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[10]~feeder                                                                               ; 0                 ; 6       ;
+; DRAM_DQ[9]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]~feeder                                                                                ; 1                 ; 6       ;
+; DRAM_DQ[8]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]                                                                                       ; 1                 ; 6       ;
+; DRAM_DQ[7]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]~feeder                                                                                ; 0                 ; 6       ;
+; DRAM_DQ[6]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6]                                                                                       ; 0                 ; 6       ;
+; DRAM_DQ[5]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5]~feeder                                                                                ; 0                 ; 6       ;
+; DRAM_DQ[4]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4]~feeder                                                                                ; 0                 ; 6       ;
+; DRAM_DQ[3]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[3]                                                                                       ; 0                 ; 6       ;
+; DRAM_DQ[2]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[2]                                                                                       ; 0                 ; 6       ;
+; DRAM_DQ[1]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[1]                                                                                       ; 1                 ; 6       ;
+; DRAM_DQ[0]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0]~feeder                                                                                ; 1                 ; 6       ;
+; GPIO_1[31]                                                                                                                                   ;                   ;         ;
+; GPIO_1[30]                                                                                                                                   ;                   ;         ;
+; GPIO_1[29]                                                                                                                                   ;                   ;         ;
+; GPIO_1[28]                                                                                                                                   ;                   ;         ;
+; GPIO_1[27]                                                                                                                                   ;                   ;         ;
+; GPIO_1[26]                                                                                                                                   ;                   ;         ;
+; GPIO_1[25]                                                                                                                                   ;                   ;         ;
+; GPIO_1[24]                                                                                                                                   ;                   ;         ;
+; GPIO_1[23]                                                                                                                                   ;                   ;         ;
+; GPIO_1[22]                                                                                                                                   ;                   ;         ;
+; GPIO_1[21]                                                                                                                                   ;                   ;         ;
+; GPIO_1[20]                                                                                                                                   ;                   ;         ;
+; GPIO_1[19]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~3                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~1                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3~2                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~9                                                                               ; 1                 ; 6       ;
+; GPIO_1[18]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_FVAL~feeder                                                                                                         ; 1                 ; 6       ;
+; GPIO_1[17]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_LVAL~feeder                                                                                                         ; 1                 ; 6       ;
+; GPIO_1[16]                                                                                                                                   ;                   ;         ;
+; GPIO_1[15]                                                                                                                                   ;                   ;         ;
+; GPIO_1[14]                                                                                                                                   ;                   ;         ;
+; GPIO_1[13]                                                                                                                                   ;                   ;         ;
+; GPIO_1[12]                                                                                                                                   ;                   ;         ;
+; GPIO_1[11]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[0]~feeder                                                                                                      ; 1                 ; 6       ;
+; GPIO_1[10]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[1]~feeder                                                                                                      ; 0                 ; 6       ;
+; GPIO_1[9]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[2]~feeder                                                                                                      ; 0                 ; 6       ;
+; GPIO_1[8]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[3]                                                                                                             ; 0                 ; 6       ;
+; GPIO_1[7]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[4]~feeder                                                                                                      ; 0                 ; 6       ;
+; GPIO_1[6]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[5]~feeder                                                                                                      ; 0                 ; 6       ;
+; GPIO_1[5]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[6]~feeder                                                                                                      ; 1                 ; 6       ;
+; GPIO_1[4]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[7]~feeder                                                                                                      ; 1                 ; 6       ;
+; GPIO_1[3]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[8]~feeder                                                                                                      ; 1                 ; 6       ;
+; GPIO_1[2]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[9]~feeder                                                                                                      ; 0                 ; 6       ;
+; GPIO_1[1]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[10]~feeder                                                                                                     ; 0                 ; 6       ;
+; GPIO_1[0]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[11]                                                                                                            ; 0                 ; 6       ;
+; PS2_DAT                                                                                                                                      ;                   ;         ;
+;      - ps2:inst6|ps2_dat_syn0~0                                                                                                              ; 0                 ; 6       ;
+; PS2_CLK                                                                                                                                      ;                   ;         ;
+;      - ps2:inst6|ps2_clk_syn0~0                                                                                                              ; 1                 ; 6       ;
+; SW[4]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~9                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~9                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~9                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~9                                      ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[9]~0                                                      ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[9]~1                                                      ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[8]~2                                                      ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[7]~4                                                      ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[7]~5                                                      ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[6]~6                                                      ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[19]~8                                                     ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[19]~9                                                     ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[18]~10                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[17]~12                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[17]~13                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[16]~14                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[29]~16                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[29]~17                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[28]~18                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[27]~20                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[27]~21                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[26]~22                                                    ; 1                 ; 6       ;
+; SW[5]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~11                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~11                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~11                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~11                                     ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[9]~0                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[8]~2                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[8]~3                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[7]~4                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[6]~6                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[6]~7                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[19]~8                                                     ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[18]~10                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[18]~11                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[17]~12                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[16]~14                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[16]~15                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[29]~16                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[28]~18                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[28]~19                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[27]~20                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[26]~22                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[26]~23                                                    ; 0                 ; 6       ;
+; CLOCK_50                                                                                                                                     ;                   ;         ;
+; KEY[0]                                                                                                                                       ;                   ;         ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                    ; 1                 ; 6       ;
+;      - ps2:inst6|midlatch                                                                                                                    ; 1                 ; 6       ;
+;      - ps2:inst6|riglatch                                                                                                                    ; 1                 ; 6       ;
+;      - ps2:inst6|leflatch                                                                                                                    ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[6]   ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[7]   ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[8]   ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[9]   ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[0]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[1]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[2]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[3]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[4]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[5]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[6]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[7]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[0]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[1]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[2]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[3]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[4]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[5]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[6]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[7]                                                                                                                  ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[29]                                                                  ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[28]                                                                  ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[27]                                                                  ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26]                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[1]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[2]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[3]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[4]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[5]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[6]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[7]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[8]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[9]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[10]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[11]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[12]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[13]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[14]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[15]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[16]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[17]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[18]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[19]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[20]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[21]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[22]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[23]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[24]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[25]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[26]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[27]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[28]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[29]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[30]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[31]                                                                                                  ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[12]                                                                         ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[12]                                                                         ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[13]                                                                         ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[12]                                                                         ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[11]                                                                         ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[11]                                                                         ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[11]                                                                         ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[10]                                                                         ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[10]                                                                         ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[10]                                                                         ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[9]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[9]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[9]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[11]                                                                         ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[8]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[8]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[8]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[10]                                                                         ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[7]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[7]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[7]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[9]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[10]                                                                         ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[6]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[6]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[6]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[8]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[9]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[5]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[5]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[5]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[7]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[8]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[4]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[4]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[4]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[6]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[7]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[3]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[3]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[3]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[5]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[6]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[2]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[2]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[2]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[4]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[5]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[1]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[1]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[1]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[3]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[4]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[0]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[0]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_661_itm_1[0]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[2]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[3]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[1]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[2]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[0]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[1]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_652_itm_1[0]                                                                          ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1                                                                      ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_slc_ACC1_acc_228_psp_55_itm_1                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_3_slc_acc_10_psp_62_itm_1                                                                 ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[4]                                                                       ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[3]                                                                       ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[2]                                                                       ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[1]                                                                       ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|main_stage_0_2                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                    ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[0]                                                                                                   ; 1                 ; 6       ;
+;      - ps2:inst6|cur_state.listen                                                                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[4]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[4]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[3]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[3]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[2]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[2]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[1]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[1]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[0]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[0]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[4]                                                               ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[3]                                                               ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[2]                                                               ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[1]                                                               ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[0]                                                               ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[6]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[6]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[5]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[5]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[6]                                                               ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[5]                                                               ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[7]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[7]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[7]                                                               ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[9]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[9]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[8]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[8]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[9]                                                               ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[8]                                                               ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[1]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[1]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[0]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[0]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[1]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[0]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[2]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[2]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[2]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[6]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[6]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[5]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[5]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[4]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[4]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[3]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[3]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[6]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[5]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[4]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[3]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[8]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[8]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[7]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[7]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[8]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[7]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[9]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[9]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[9]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[26]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[25]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[24]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[23]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[22]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[21]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[20]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[6]                                                                     ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[16]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[5]                                                                     ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[15]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[4]                                                                     ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[14]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[3]                                                                     ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[13]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[2]                                                                     ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[12]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[1]                                                                     ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[11]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[10]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[0]                                                                     ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[28]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[27]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[8]                                                                     ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[18]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[7]                                                                     ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[17]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[29]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[9]                                                                     ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[19]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[63]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[73]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[62]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[72]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[61]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[71]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[60]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[70]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[83]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[82]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[81]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[80]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[4]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[4]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[3]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[3]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[2]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[2]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[1]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[1]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[0]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[0]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[4]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[3]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[2]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[1]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[0]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[9]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[9]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[8]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[8]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[7]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[7]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[6]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[6]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[5]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[5]                                                            ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[9]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[8]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[7]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[6]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[5]                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[67]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[77]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[66]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[76]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[65]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[75]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[64]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[74]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[87]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[86]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[85]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[84]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[69]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[79]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[68]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[78]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[89]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[88]                                                                    ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                    ; 1                 ; 6       ;
+;      - ps2:inst6|cur_state.pullclk                                                                                                           ; 1                 ; 6       ;
+;      - ps2:inst6|cur_state.trans                                                                                                             ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[31]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[41]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[30]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[40]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[51]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[50]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[32]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[42]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[52]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[36]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[46]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[35]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[45]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[34]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[44]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[33]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[43]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[56]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[55]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[54]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[53]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[38]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[48]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[37]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[47]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[58]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[57]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[39]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[49]                                                                    ; 1                 ; 6       ;
+;      - sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[59]                                                                    ; 1                 ; 6       ;
+;      - ps2:inst6|cur_state.pulldat                                                                                                           ; 1                 ; 6       ;
+; SW[7]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~15                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~15                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~15                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~15                                     ; 0                 ; 6       ;
+; SW[6]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~13                                     ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~13                                     ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~13                                     ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~13                                     ; 1                 ; 6       ;
+; SW[3]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~7                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~7                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~7                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~7                                      ; 0                 ; 6       ;
+; SW[2]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~5                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~5                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~5                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~5                                      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~8                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~10                                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~0                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~16                                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~3                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~24                                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~25                                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~26                                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~2                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~6                                                                                                ; 1                 ; 6       ;
+; SW[1]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~3                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~3                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~3                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~3                                      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                              ; 1                 ; 6       ;
+; SW[0]                                                                                                                                        ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]~44                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                     ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]~23                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                    ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]~34                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                     ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]~32                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]~38                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]~36                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                     ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]~21                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~40                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~42                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                     ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]~19                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]~15                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]~17                                                                                  ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~1                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~1                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~1                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~1                                      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~25                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~28                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]~46                                                                                  ; 1                 ; 6       ;
+;      - SW[0]~_wirecell                                                                                                                       ; 1                 ; 6       ;
+; KEY[1]                                                                                                                                       ;                   ;         ;
+;      - ps2:inst6|Selector1~0                                                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|CCD_Capture:u3|mSTART~0                                                                                                  ; 1                 ; 6       ;
+; GPIO_1_CLKIN[0]                                                                                                                              ;                   ;         ;
+; KEY[2]                                                                                                                                       ;                   ;         ;
+;      - DE0_D5M:inst|CCD_Capture:u3|mSTART~0                                                                                                  ; 0                 ; 6       ;
++----------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                                                                                                                  ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                                                                                                                  ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                                                                              ; PIN_G21            ; 5       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                                                                                                                              ; PIN_G21            ; 102     ; Clock                      ; yes    ; Global Clock         ; GCLK7            ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[2]~18                                                                                              ; LCCOMB_X15_Y14_N16 ; 16      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[2]~19                                                                                              ; LCCOMB_X15_Y14_N10 ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[0]~3                                                                                               ; LCCOMB_X15_Y14_N20 ; 1       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL                                                                                                 ; FF_X15_Y14_N7      ; 7       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|oDVAL                                                                                                     ; LCCOMB_X15_Y14_N30 ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2                                                                             ; LCCOMB_X11_Y12_N0  ; 24      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]~1                                                                      ; LCCOMB_X11_Y11_N2  ; 6       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2]                                                                                           ; FF_X10_Y14_N9      ; 34      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4]                                                                                           ; FF_X10_Y14_N13     ; 39      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7                                                                                         ; LCCOMB_X10_Y14_N26 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4                                                                                            ; LCCOMB_X8_Y10_N20  ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1                                                                                            ; LCCOMB_X10_Y14_N2  ; 6       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                              ; LCCOMB_X11_Y10_N22 ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset                                                                                              ; LCCOMB_X11_Y10_N26 ; 43      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]                                                                                 ; FF_X11_Y10_N7      ; 26      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                                                                          ; FF_X40_Y15_N17     ; 72      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1                                                                                        ; LCCOMB_X10_Y14_N20 ; 24      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~31                                                                                 ; LCCOMB_X7_Y13_N18  ; 14      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual ; LCCOMB_X12_Y10_N30 ; 11      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[12]~36                                                                                                 ; LCCOMB_X14_Y14_N26 ; 10      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~11                                                                                                 ; LCCOMB_X19_Y24_N0  ; 32      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                    ; FF_X19_Y26_N3      ; 468     ; Async. clear               ; yes    ; Global Clock         ; GCLK12           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                    ; FF_X19_Y24_N29     ; 55      ; Async. clear               ; yes    ; Global Clock         ; GCLK14           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                    ; FF_X19_Y24_N5      ; 106     ; Async. clear               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]~0                                                                                          ; LCCOMB_X4_Y27_N22  ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]~10                                                                                     ; LCCOMB_X19_Y26_N22 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]~7                                                                                      ; LCCOMB_X19_Y26_N8  ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0            ; LCCOMB_X14_Y21_N24 ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0            ; LCCOMB_X14_Y22_N24 ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0            ; LCCOMB_X14_Y18_N24 ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0            ; LCCOMB_X12_Y19_N8  ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0           ; LCCOMB_X10_Y25_N24 ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0           ; LCCOMB_X11_Y27_N24 ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0           ; LCCOMB_X11_Y26_N6  ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0           ; LCCOMB_X11_Y27_N30 ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]~2                                                                                      ; LCCOMB_X15_Y26_N24 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE                                                                               ; FF_X7_Y28_N3       ; 16      ; Output enable              ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]~1                                                                    ; LCCOMB_X8_Y27_N8   ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ                                                               ; FF_X9_Y28_N9       ; 26      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3                                                            ; LCCOMB_X9_Y28_N6   ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1                                                              ; LCCOMB_X9_Y28_N12  ; 16      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]~45                                                                                   ; LCCOMB_X17_Y26_N22 ; 15      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]~46                                                                                   ; LCCOMB_X19_Y26_N20 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]~46                                                                                  ; LCCOMB_X19_Y26_N14 ; 15      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]~47                                                                                  ; LCCOMB_X19_Y26_N16 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]~45                                                                                  ; LCCOMB_X19_Y26_N6  ; 15      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]~46                                                                                  ; LCCOMB_X19_Y26_N28 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]~46                                                                                  ; LCCOMB_X20_Y28_N30 ; 15      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]~47                                                                                  ; LCCOMB_X19_Y26_N26 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~3                                                                                               ; LCCOMB_X23_Y25_N30 ; 13      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2                                                                                            ; LCCOMB_X22_Y25_N2  ; 13      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4                                                                                            ; LCCOMB_X24_Y23_N26 ; 12      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|active                                                                                                 ; FF_X22_Y25_N3      ; 20      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|rClk[0]                                                                                                                  ; FF_X20_Y1_N9       ; 405     ; Clock                      ; yes    ; Global Clock         ; GCLK15           ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0]                                                   ; PLL_2              ; 512     ; Clock                      ; yes    ; Global Clock         ; GCLK8            ; --                        ;
+; GPIO_1_CLKIN[0]                                                                                                                       ; PIN_AB11           ; 229     ; Clock                      ; yes    ; Global Clock         ; GCLK19           ; --                        ;
+; KEY[0]                                                                                                                                ; PIN_H2             ; 325     ; Async. clear               ; no     ; --                   ; --               ; --                        ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|cout_actual                                                     ; LCCOMB_X16_Y19_N6  ; 10      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|Equal2~0                                                                                                                    ; LCCOMB_X23_Y8_N4   ; 8       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|Equal3~2                                                                                                                    ; LCCOMB_X21_Y8_N0   ; 6       ; Async. clear               ; yes    ; Global Clock         ; GCLK17           ; --                        ;
+; ps2:inst6|always5~1                                                                                                                   ; LCCOMB_X21_Y8_N8   ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|clk_div[8]                                                                                                                  ; FF_X20_Y1_N27      ; 3       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|clk_div[8]                                                                                                                  ; FF_X20_Y1_N27      ; 38      ; Clock                      ; yes    ; Global Clock         ; GCLK16           ; --                        ;
+; ps2:inst6|cur_state.listen                                                                                                            ; FF_X23_Y8_N17      ; 38      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|cur_state.trans                                                                                                             ; FF_X23_Y8_N11      ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|de~0                                                                                                                        ; LCCOMB_X23_Y8_N24  ; 1       ; Output enable              ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|ps2_clk_in                                                                                                                  ; FF_X21_Y1_N31      ; 51      ; Clock                      ; yes    ; Global Clock         ; GCLK18           ; --                        ;
+; sobel:inst1|sobel_core:sobel_core_inst|main_stage_0_2                                                                                 ; FF_X30_Y21_N27     ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                                                                                                   ;
++-------------------------------------------------------------------------------------+------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name                                                                                ; Location         ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------------------------------------------------------------------------------------+------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                            ; PIN_G21          ; 102     ; 0                                    ; Global Clock         ; GCLK7            ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                        ; FF_X40_Y15_N17   ; 72      ; 0                                    ; Global Clock         ; GCLK6            ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                  ; FF_X19_Y26_N3    ; 468     ; 0                                    ; Global Clock         ; GCLK12           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                  ; FF_X19_Y24_N29   ; 55      ; 0                                    ; Global Clock         ; GCLK14           ; --                        ;
+; DE0_D5M:inst|rClk[0]                                                                ; FF_X20_Y1_N9     ; 405     ; 0                                    ; Global Clock         ; GCLK15           ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; PLL_2            ; 512     ; 137                                  ; Global Clock         ; GCLK8            ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; PLL_2            ; 1       ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
+; GPIO_1_CLKIN[0]                                                                     ; PIN_AB11         ; 229     ; 0                                    ; Global Clock         ; GCLK19           ; --                        ;
+; ps2:inst6|Equal3~2                                                                  ; LCCOMB_X21_Y8_N0 ; 6       ; 0                                    ; Global Clock         ; GCLK17           ; --                        ;
+; ps2:inst6|clk_div[8]                                                                ; FF_X20_Y1_N27    ; 38      ; 0                                    ; Global Clock         ; GCLK16           ; --                        ;
+; ps2:inst6|ps2_clk_in                                                                ; FF_X21_Y1_N31    ; 51      ; 0                                    ; Global Clock         ; GCLK18           ; --                        ;
++-------------------------------------------------------------------------------------+------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals                                                                                                                                                     ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Name                                                                                                                                                                      ; Fan-Out ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; KEY[0]~input                                                                                                                                                              ; 325     ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                                                        ; 106     ;
+; ~GND                                                                                                                                                                      ; 63      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add44~22                                                                                                                           ; 54      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset                                                                                                                                  ; 43      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add29~22                                                                                                                           ; 41      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[1]                                                                                                                               ; 40      ;
+; DE0_D5M:inst|VGA_Controller:u1|always0~1                                                                                                                                  ; 39      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4]                                                                                                                               ; 39      ;
+; ps2:inst6|cur_state.listen                                                                                                                                                ; 38      ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R~0                                                                                                                                   ; 38      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add21~22                                                                                                                           ; 37      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2]                                                                                                                               ; 34      ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[0]                                                                                                                                     ; 34      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add34~22                                                                                                                           ; 34      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[3]                                                                                                                               ; 33      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[0]                                                                                                                                     ; 33      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add26~22                                                                                                                           ; 33      ;
+; sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_724_cse[1]~0                                                                                                              ; 33      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[0]                                                                                                                               ; 32      ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~11                                                                                                                                     ; 32      ;
+; sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_553_ncse[2]~0                                                                                                             ; 32      ;
+; sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_516_cse[1]~0                                                                                                              ; 32      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; 31      ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[11]~22                                                                                                   ; 31      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add132~22                                                                                                                          ; 30      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]                                                                                                                     ; 26      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ                                                                                                   ; 26      ;
+; SW[0]~input                                                                                                                                                               ; 25      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1                                                                                                                            ; 24      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2                                                                                                                 ; 24      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD~0                                                                                                                                 ; 23      ;
+; SW[5]~input                                                                                                                                                               ; 22      ;
+; SW[4]~input                                                                                                                                                               ; 22      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]~0                                                                                                                           ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]                                                                                                            ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[9]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[8]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[7]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[6]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[5]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[4]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[3]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[2]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[1]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[0]                                                                                  ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0]                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                               ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                               ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                               ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                               ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]                                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_writea                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_reada                                                                                                             ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                                ; 20      ;
+; DE0_D5M:inst|VGA_Controller:u1|active                                                                                                                                     ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                                ; 20      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2]                                                                                                            ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                                ; 19      ;
+; ps2:inst6|always5~1                                                                                                                                                       ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal0~0                                                                                                                              ; 18      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]                                                                                                                               ; 18      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; 18      ;
+; DE0_D5M:inst|CCD_Capture:u3|oDVAL                                                                                                                                         ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4                                                                                                                                ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1]                                                                                                            ; 17      ;
+; ps2:inst6|cur_state.trans                                                                                                                                                 ; 17      ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_2_sva[3]~6                                                                                                     ; 17      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[2]~19                                                                                                                                  ; 16      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[2]~18                                                                                                                                  ; 16      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1                                                                                                  ; 16      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE                                                                                                                   ; 16      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3                                                                                                ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]~46                                                                                                                       ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]~45                                                                                                                       ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]~47                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]~47                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]~45                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]~10                                                                                                                         ; 15      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add44~14                                                                                                                           ; 15      ;
+; SW[2]~input                                                                                                                                                               ; 14      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                                                                  ; 14      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~31                                                                                                                     ; 14      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal6~1                                                                                                                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[10]                             ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[9]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[8]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[7]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[6]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[5]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[4]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[3]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[2]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[1]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[0]                              ; 14      ;
+; DE0_D5M:inst|rCCD_LVAL                                                                                                                                                    ; 13      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]                                                                                                            ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2                                                                                                                                ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~3                                                                                                                                   ; 13      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add44~18                                                                                                                           ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4                                                                                                                                ; 12      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]                                                                                                            ; 12      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag~1                                                                                                            ; 12      ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_2_sva[3]~6                                                                                                     ; 12      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual                                     ; 11      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[6]                                                                                                            ; 11      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add125~0                                                                                                                           ; 11      ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_384_itm[4]~6                                                                                                           ; 11      ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_3_acc_212_psp_sva[3]~6                                                                                                     ; 11      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add21~18                                                                                                                           ; 11      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add21~14                                                                                                                           ; 11      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add44~6                                                                                                                            ; 11      ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_412_itm[3]~4                                                                                                           ; 11      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add13~28                                                                                                                           ; 11      ;
+; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[12]~36                                                                                                                                     ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~5                                                                                                            ; 10      ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|cout_actual                                                                                         ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4]~2                                                                                                                               ; 10      ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                                                        ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16                                                     ; 10      ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_346_itm[4]~6                                                                                                           ; 10      ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[8]~16                                                                                                      ; 10      ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_1_acc_208_psp_sva[2]~4                                                                                                     ; 10      ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_1_sva[3]~6                                                                                                     ; 10      ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_375_itm[4]~6                                                                                                           ; 10      ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_375_itm[2]~2                                                                                                           ; 10      ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_2_sva[2]~4                                                                                                     ; 10      ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add44~8                                                                                                                            ; 10      ;
+; ps2:inst6|y_latch[7]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[6]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[5]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[4]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[3]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[2]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[1]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[0]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[7]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[6]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[5]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[4]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[3]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[2]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[1]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[0]                                                                                                                                                      ; 10      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_GO                                                                                                                                    ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_done                                                                                                         ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]~0                                                                                                                               ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[2]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16                                                     ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_384_itm[3]~4                                                                                                           ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_384_itm[2]~2                                                                                                           ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_3_acc_212_psp_sva[2]~4                                                                                                     ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[10]~20                                                                                                     ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add132~14                                                                                                                          ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[8]~16                                                                                                    ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[6]~12                                                                                                      ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[4]~8                                                                                                       ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_1_acc_208_psp_sva[3]~6                                                                                                     ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[6]~12                                                                                                    ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[10]~20                                                                                                     ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[8]~16                                                                                                      ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_2_sva[1]~2                                                                                                     ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add44~16                                                                                                                           ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add44~10                                                                                                                           ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_412_itm[4]~6                                                                                                           ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_412_itm[2]~2                                                                                                           ; 9       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add34~14                                                                                                                           ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_refresh                                                                                                           ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; 9       ;
+; SW[0]~_wirecell                                                                                                                                                           ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; 8       ;
+; ps2:inst6|cur_state.pullclk                                                                                                                                               ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add57~0                                                                                                                            ; 8       ;
+; ps2:inst6|Equal2~0                                                                                                                                                        ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~4                                                                                                                              ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                       ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                       ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                       ; 8       ;
+; vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|or_itm~0                                                                        ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_346_itm[3]~4                                                                                                           ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_346_itm[2]~2                                                                                                           ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[10]~20                                                                                                   ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add132~18                                                                                                                          ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_1_acc_208_psp_sva[1]~2                                                                                                     ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add21~12                                                                                                                           ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add21~10                                                                                                                           ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add26~14                                                                                                                           ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_375_itm[3]~4                                                                                                           ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add29~14                                                                                                                           ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add29~10                                                                                                                           ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add44~20                                                                                                                           ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add44~2                                                                                                                            ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_412_itm[1]~0                                                                                                           ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[10]~20                                                                                                     ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_1_sva[3]~6                                                                                                     ; 8       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add13~20                                                                                                                           ; 8       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux14~0                                                                                                                                    ; 7       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~7                                                                                                                                    ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                      ; 7       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL                                                                                                                                     ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add98~0                                                                                                                            ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add262~0                                                                                                                           ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8]                                                                                                                                 ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[8]                                                                                              ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_3_acc_212_psp_sva[1]~2                                                                                                     ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_2_sva[1]~2                                                                                                     ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add132~16                                                                                                                          ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_1_acc_208_psp_sva[0]~0                                                                                                     ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add26~18                                                                                                                           ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_1_sva[2]~4                                                                                                     ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_1_sva[1]~2                                                                                                     ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add21~16                                                                                                                           ; 7       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[69]                                                                                ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add26~10                                                                                                                           ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_375_itm[1]~0                                                                                                           ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add29~18                                                                                                                           ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_2_sva[0]~0                                                                                                     ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add44~12                                                                                                                           ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add44~4                                                                                                                            ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[8]~16                                                                                                      ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_1_sva[2]~4                                                                                                     ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_1_sva[1]~2                                                                                                     ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add34~18                                                                                                                           ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add34~10                                                                                                                           ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add13~26                                                                                                                           ; 7       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add13~22                                                                                                                           ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[9]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[1]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[0]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[9]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[8]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[7]                                                                                                                                  ; 7       ;
+; SW[1]~input                                                                                                                                                               ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1                                                                                                                                ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                      ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]~1                                                                                                          ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO                                                                                                                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add418~1                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add416~2                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add418~0                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add150~1                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add148~2                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add150~0                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add231~1                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add229~2                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add231~0                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add223~1                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add221~2                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add223~0                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add125~1                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[9]                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD                                                                                                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal10~0                                                                                                                             ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[9]                                                                                              ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[3]                                                                                              ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_384_itm[1]~0                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_3_acc_212_psp_sva[0]~0                                                                                                     ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_2_sva[2]~4                                                                                                     ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_2_sva[0]~0                                                                                                     ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add132~20                                                                                                                          ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add132~8                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add132~6                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add26~16                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_217_psp_1_sva[0]~0                                                                                                     ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add21~20                                                                                                                           ; 6       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[79]                                                                                ; 6       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[89]                                                                                ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[4]~8                                                                                                     ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add29~16                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[6]~12                                                                                                      ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[4]~8                                                                                                       ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[6]~12                                                                                                      ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[4]~8                                                                                                       ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_210_psp_1_sva[0]~0                                                                                                     ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add34~16                                                                                                                           ; 6       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add13~24                                                                                                                           ; 6       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[59]                                                                                ; 6       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[6]                                                                                                                                  ; 6       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[5]                                                                                                                                  ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[15]~2                                                                                                                            ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7                                                                                                                             ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END                                                                                                                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                      ; 5       ;
+; ps2:inst6|delay[0]                                                                                                                                                        ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|IN_REQ                                                                                                                                ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; 5       ;
+; ps2:inst6|byte_cnt[0]                                                                                                                                                     ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|PM_STOP                                                                                                                               ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add319~1                                                                                                                           ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add318~1                                                                                                                           ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add94~1                                                                                                                            ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add96~0                                                                                                                            ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add416~1                                                                                                                           ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add58~0                                                                                                                            ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add238~0                                                                                                                           ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add148~1                                                                                                                           ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add229~1                                                                                                                           ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add221~1                                                                                                                           ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add85~0                                                                                                                            ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add212~1                                                                                                                           ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_itm[9]                                                                                                   ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_1_itm[9]                                                                                                 ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3]                                                                                                                                 ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4]                                                                                                                                 ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[2]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[3]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[5]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[6]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[7]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[4]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[9]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[10]                            ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[11]                            ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[8]                             ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[5]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[2]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[7]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[6]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[15]                                                                                             ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[14]                                                                                             ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_2~16                                                      ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_346_itm[1]~0                                                                                                           ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add132~12                                                                                                                          ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add132~10                                                                                                                          ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[5]~10                                                                                                      ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add26~12                                                                                                                           ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[3]~6                                                                                                       ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[5]~10                                                                                                    ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add29~12                                                                                                                           ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[3]~6                                                                                                       ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[1]~2                                                                                                       ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[5]~10                                                                                                      ; 5       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add34~12                                                                                                                           ; 5       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                                                                                                                                      ; 5       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[9]                                                                                 ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[0]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[3]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[2]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[1]                                                                                                                                  ; 5       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[39]                                                                                ; 5       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[49]                                                                                ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[5]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[8]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[7]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[6]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[4]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[3]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[2]                                                                                                                                  ; 5       ;
+; SW[3]~input                                                                                                                                                               ; 4       ;
+; SW[6]~input                                                                                                                                                               ; 4       ;
+; SW[7]~input                                                                                                                                                               ; 4       ;
+; CLOCK_50~input                                                                                                                                                            ; 4       ;
+; GPIO_1[19]~input                                                                                                                                                          ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~8                                                                                                                                    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0001                                                                                                                             ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0010                                                                                                                             ; 4       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_LVAL                                                                                                                                     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]~1                                                                                                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; 4       ;
+; ps2:inst6|delay[1]                                                                                                                                                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK                                                                                                                     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add317~2                                                                                                                           ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add91~0                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add100~0                                                                                                                           ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add48~0                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add238~1                                                                                                                           ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core|romout[0][1]~0                                                                                   ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|ACC1_1_and_3_cse_sva~0                                                                                                             ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add143~0                                                                                                                           ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core|romout[0][9]~2                                                                                   ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[89]                                                                                                        ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[79]                                                                                                        ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[69]                                                                                                        ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[29]                                                                                                        ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add129~0                                                                                                                           ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~9                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                                                                                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_RD                                                                                                                                ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]                                                                                                                            ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|main_stage_0_2                                                                                                                     ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|slc_acc_20_psp_1_93_itm_1                                                                                                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~0                                                                                                                              ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[14]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[15]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[17]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[18]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[19]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[16]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[21]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[22]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[23]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[20]                            ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[4]                                                                                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[13]                                                                                             ; 4       ;
+; ps2:inst6|byte_cnt[1]                                                                                                                                                     ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add168~14                                                                                                                          ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add192~14                                                                                                                          ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add132~2                                                                                                                           ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[9]~18                                                                                                    ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[9]~18                                                                                                      ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[7]~14                                                                                                    ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[7]~14                                                                                                      ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add216~18                                                                                                                          ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add26~20                                                                                                                           ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add21~8                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add21~6                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add21~2                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[2]~4                                                                                                       ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[0]~0                                                                                                       ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add26~8                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add26~6                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add26~2                                                                                                                            ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[60]                                                                                ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add214~12                                                                                                                          ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[3]~6                                                                                                     ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[2]~4                                                                                                     ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[0]~0                                                                                                     ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[50]                                                                                ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add29~20                                                                                                                           ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add29~8                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add29~6                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add29~2                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[5]~10                                                                                                      ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[2]~4                                                                                                       ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[0]~0                                                                                                       ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[0]                                                                                 ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[29]                                                                                ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[9]~18                                                                                                      ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[7]~14                                                                                                      ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[3]~6                                                                                                       ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[2]~4                                                                                                       ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[0]~0                                                                                                       ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add34~20                                                                                                                           ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add34~8                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add34~6                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add34~2                                                                                                                            ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                                                                                                                                      ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[19]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[56]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[57]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[58]                                                                                ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add4~12                                                                                                                            ; 4       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_acc_imod_24_sva[5]~10                                                                                                           ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[37]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[38]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[46]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[47]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[48]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[36]                                                                                ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[11]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[10]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[4]                                                                                                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK~_wirecell                                                                                                    ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux10~2                                                                                                                                    ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~0                                                                                                                                     ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2                                                                                                                     ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0                  ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[2]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[3]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[4]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[5]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[6]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[7]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[8]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[9]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[10]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[11]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[2]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[3]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[4]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[5]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[6]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[7]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[8]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[9]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[10]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[11]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~5                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~6                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~3                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]~0                                                                                                        ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~2                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~1                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~0                                                                                                ; 3       ;
+; ps2:inst6|delay[2]                                                                                                                                                        ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~5                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~2                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]~2                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0                   ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0                   ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]~7                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]~6                                                                                                                          ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add92~1                                                                                                                            ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_652_itm_1~5                                                                                                            ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add255~0                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add103~0                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add265~0                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_652_itm_1~4                                                                                                            ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add104~0                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add400~0                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add73~0                                                                                                                            ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add407~1                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add407~0                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add102~0                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add406~0                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add414~1                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add348~1                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_655_itm_1~1                                                                                                            ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add86~1                                                                                                                            ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core|romout[0][6]~1                                                                                   ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add146~1                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add35~0                                                                                                                            ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core|romout[0][8]~3                                                                                   ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add227~1                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core|romout[0][7]~2                                                                                   ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add219~1                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add119~0                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add123~0                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_9_itm[9]                                                                                                 ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_10_itm[9]                                                                                                ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_11_itm[9]                                                                                                ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[19]                                                                                                        ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[9]                                                                                                         ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add67~0                                                                                                                            ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|reg_regs_regs_0_sva_cse[20]                                                                                                        ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add127~1                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_3_itm[9]                                                                                                 ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_4_itm[9]                                                                                                 ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_5_itm[9]                                                                                                 ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add61~1                                                                                                                            ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|regs_regs_slc_regs_regs_2_2_itm[0]                                                                                                 ; 3       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~7                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always4~0                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                       ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|oRequest                                                                                                                                   ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add15~1                                                                                                                            ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add15~0                                                                                                                            ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[2]                                                                                                           ; 3       ;
+; ps2:inst6|Equal3~0                                                                                                                                                        ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~2                                                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~1                                                                                                                              ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[6]~3                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[7]~2                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[8]~1                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[9]~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan5~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan4~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~0                                                                                                                                   ; 3       ;
+; DE0_D5M:inst|rClk[0]                                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]                                                                                                                        ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[1]                             ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[0]                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[1]                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21]                                                                                                                         ; 3       ;
+; ps2:inst6|byte_cnt[2]                                                                                                                                                     ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add383~16                                                                                                                          ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add175~16                                                                                                                          ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add167~10                                                                                                                          ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add165~6                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add199~16                                                                                                                          ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add191~10                                                                                                                          ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add189~6                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add132~4                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add21~4                                                                                                                            ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[68]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[78]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[86]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[87]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[88]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[66]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[76]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[77]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[80]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[81]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[82]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[83]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[84]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[85]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[67]                                                                                ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_226_psp_sva[1]~2                                                                                                       ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add26~4                                                                                                                            ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[61]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[62]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[63]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[64]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[70]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[71]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[72]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[73]                                                                                ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_1_sva[1]~2                                                                                                     ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[31]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[35]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[40]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[45]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[55]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[65]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[74]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[75]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[30]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[33]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[34]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[41]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[42]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[43]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[44]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[51]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[32]                                                                                ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[9]~18                                                                                                      ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_228_psp_sva[7]~14                                                                                                      ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add29~4                                                                                                                            ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[11]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[12]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[20]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[21]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[22]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[52]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[53]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[54]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[10]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[1]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[2]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[13]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[14]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[15]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[23]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[24]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[25]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[4]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[5]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[16]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[17]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[26]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[27]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[28]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[3]                                                                                 ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|nl_ACC1_acc_224_psp_sva[1]~2                                                                                                       ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add34~4                                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[7]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[8]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[18]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|q_b[6]                                                                                 ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add3~8                                                                                                                             ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add13~18                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add13~16                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add13~14                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|Add10~22                                                                                                                           ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_655_itm_1[11]                                                                                                             ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_659_itm_1[12]                                                                                                             ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|ACC1_acc_658_itm_1[12]                                                                                                             ; 3       ;
+; ps2:inst6|cnt[7]                                                                                                                                                          ; 3       ;
+; ps2:inst6|cnt[6]                                                                                                                                                          ; 3       ;
+; ps2:inst6|cnt[5]                                                                                                                                                          ; 3       ;
+; ps2:inst6|cnt[0]                                                                                                                                                          ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26]                                                                                                      ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[27]                                                                                                      ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[28]                                                                                                      ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[11]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[10]                                                                                                                                 ; 3       ;
+; sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[29]                                                                                                      ; 3       ;
+; KEY[1]~input                                                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]~11                                                                                                                         ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~18                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~17                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~11                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~1                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~10                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux8~0                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux15~0                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0000                                                                                                                             ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK~0                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1                                                                                                                     ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                             ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|LessThan0~4                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|mSTART                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|rCCD_FVAL                                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~2                                                                                                ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~1                                                                                                                 ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~0                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~6                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~7                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[10]                                                                                                                          ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[1]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[2]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[3]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~3                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~0                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~2                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|PRECHARGE~0                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always3~0                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal8~0                                                                                                                              ; 2       ;
+; ps2:inst6|nex_state.pulldat~0                                                                                                                                             ; 2       ;
+; ps2:inst6|delay[3]                                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Mux0~16                                                                                                                  ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~2                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~0                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|LessThan2~1                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Equal4~7                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                            ; 2       ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+
+; Name                                                                                                                                              ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF  ; Location                                                                                                                                                       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 1278         ; 24           ; 1278         ; 24           ; yes                    ; no                      ; yes                    ; yes                     ; 30672 ; 1278                        ; 24                          ; 1278                        ; 24                          ; 30672               ; 6    ; None ; M9K_X13_Y13_N0, M9K_X13_Y9_N0, M9K_X13_Y10_N0, M9K_X13_Y14_N0, M9K_X13_Y12_N0, M9K_X13_Y11_N0                                                                  ; Old data             ; Old data        ; Old data        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 15                          ; 512                         ; 15                          ; 7680                ; 1    ; None ; M9K_X13_Y22_N0                                                                                                                                                 ; Don't care           ; Old data        ; Old data        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 15                          ; 512                         ; 15                          ; 7680                ; 1    ; None ; M9K_X13_Y19_N0                                                                                                                                                 ; Don't care           ; Old data        ; Old data        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 16                          ; 512                         ; 16                          ; 8192                ; 1    ; None ; M9K_X13_Y25_N0                                                                                                                                                 ; Don't care           ; Old data        ; Old data        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 16                          ; 512                         ; 16                          ; 8192                ; 1    ; None ; M9K_X13_Y26_N0                                                                                                                                                 ; Don't care           ; Old data        ; Old data        ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|ALTSYNCRAM                                                     ; AUTO ; Simple Dual Port ; Single Clock ; 798          ; 90           ; 798          ; 90           ; yes                    ; no                      ; yes                    ; yes                     ; 71820 ; 798                         ; 90                          ; 798                         ; 90                          ; 71820               ; 10   ; None ; M9K_X13_Y20_N0, M9K_X13_Y18_N0, M9K_X13_Y17_N0, M9K_X13_Y16_N0, M9K_X25_Y19_N0, M9K_X25_Y18_N0, M9K_X25_Y16_N0, M9K_X25_Y17_N0, M9K_X25_Y21_N0, M9K_X25_Y20_N0 ; Old data             ; Old data        ; Old data        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++-------------------------------------------------------+
+; Other Routing Usage Summary                           ;
++-----------------------------+-------------------------+
+; Other Routing Resource Type ; Usage                   ;
++-----------------------------+-------------------------+
+; Block interconnects         ; 4,333 / 47,787 ( 9 % )  ;
+; C16 interconnects           ; 48 / 1,804 ( 3 % )      ;
+; C4 interconnects            ; 2,088 / 31,272 ( 7 % )  ;
+; Direct links                ; 955 / 47,787 ( 2 % )    ;
+; Global clocks               ; 11 / 20 ( 55 % )        ;
+; Local interconnects         ; 1,603 / 15,408 ( 10 % ) ;
+; R24 interconnects           ; 84 / 1,775 ( 5 % )      ;
+; R4 interconnects            ; 2,439 / 41,310 ( 6 % )  ;
++-----------------------------+-------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Logic Elements                                                          ;
++---------------------------------------------+-------------------------------+
+; Number of Logic Elements  (Average = 12.42) ; Number of LABs  (Total = 293) ;
++---------------------------------------------+-------------------------------+
+; 1                                           ; 20                            ;
+; 2                                           ; 6                             ;
+; 3                                           ; 4                             ;
+; 4                                           ; 2                             ;
+; 5                                           ; 4                             ;
+; 6                                           ; 5                             ;
+; 7                                           ; 3                             ;
+; 8                                           ; 8                             ;
+; 9                                           ; 9                             ;
+; 10                                          ; 8                             ;
+; 11                                          ; 12                            ;
+; 12                                          ; 20                            ;
+; 13                                          ; 27                            ;
+; 14                                          ; 19                            ;
+; 15                                          ; 33                            ;
+; 16                                          ; 113                           ;
++---------------------------------------------+-------------------------------+
+
+
++--------------------------------------------------------------------+
+; LAB-wide Signals                                                   ;
++------------------------------------+-------------------------------+
+; LAB-wide Signals  (Average = 1.13) ; Number of LABs  (Total = 293) ;
++------------------------------------+-------------------------------+
+; 1 Async. clear                     ; 110                           ;
+; 1 Clock                            ; 137                           ;
+; 1 Clock enable                     ; 41                            ;
+; 1 Sync. clear                      ; 9                             ;
+; 1 Sync. load                       ; 4                             ;
+; 2 Async. clears                    ; 2                             ;
+; 2 Clock enables                    ; 5                             ;
+; 2 Clocks                           ; 22                            ;
++------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Signals Sourced                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Signals Sourced  (Average = 16.32) ; Number of LABs  (Total = 293) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 10                            ;
+; 2                                            ; 16                            ;
+; 3                                            ; 4                             ;
+; 4                                            ; 2                             ;
+; 5                                            ; 8                             ;
+; 6                                            ; 2                             ;
+; 7                                            ; 5                             ;
+; 8                                            ; 4                             ;
+; 9                                            ; 6                             ;
+; 10                                           ; 6                             ;
+; 11                                           ; 13                            ;
+; 12                                           ; 12                            ;
+; 13                                           ; 21                            ;
+; 14                                           ; 17                            ;
+; 15                                           ; 23                            ;
+; 16                                           ; 28                            ;
+; 17                                           ; 5                             ;
+; 18                                           ; 8                             ;
+; 19                                           ; 10                            ;
+; 20                                           ; 8                             ;
+; 21                                           ; 7                             ;
+; 22                                           ; 4                             ;
+; 23                                           ; 5                             ;
+; 24                                           ; 7                             ;
+; 25                                           ; 3                             ;
+; 26                                           ; 8                             ;
+; 27                                           ; 4                             ;
+; 28                                           ; 10                            ;
+; 29                                           ; 7                             ;
+; 30                                           ; 13                            ;
+; 31                                           ; 8                             ;
+; 32                                           ; 9                             ;
++----------------------------------------------+-------------------------------+
+
+
++---------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                         ;
++-------------------------------------------------+-------------------------------+
+; Number of Signals Sourced Out  (Average = 8.64) ; Number of LABs  (Total = 293) ;
++-------------------------------------------------+-------------------------------+
+; 0                                               ; 0                             ;
+; 1                                               ; 28                            ;
+; 2                                               ; 9                             ;
+; 3                                               ; 13                            ;
+; 4                                               ; 22                            ;
+; 5                                               ; 20                            ;
+; 6                                               ; 19                            ;
+; 7                                               ; 22                            ;
+; 8                                               ; 18                            ;
+; 9                                               ; 18                            ;
+; 10                                              ; 17                            ;
+; 11                                              ; 21                            ;
+; 12                                              ; 19                            ;
+; 13                                              ; 14                            ;
+; 14                                              ; 12                            ;
+; 15                                              ; 12                            ;
+; 16                                              ; 17                            ;
+; 17                                              ; 3                             ;
+; 18                                              ; 1                             ;
+; 19                                              ; 1                             ;
+; 20                                              ; 2                             ;
+; 21                                              ; 1                             ;
+; 22                                              ; 0                             ;
+; 23                                              ; 0                             ;
+; 24                                              ; 1                             ;
+; 25                                              ; 0                             ;
+; 26                                              ; 1                             ;
+; 27                                              ; 2                             ;
++-------------------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Distinct Inputs  (Average = 12.63) ; Number of LABs  (Total = 293) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 0                             ;
+; 2                                            ; 16                            ;
+; 3                                            ; 16                            ;
+; 4                                            ; 13                            ;
+; 5                                            ; 15                            ;
+; 6                                            ; 13                            ;
+; 7                                            ; 11                            ;
+; 8                                            ; 21                            ;
+; 9                                            ; 11                            ;
+; 10                                           ; 16                            ;
+; 11                                           ; 19                            ;
+; 12                                           ; 14                            ;
+; 13                                           ; 10                            ;
+; 14                                           ; 9                             ;
+; 15                                           ; 10                            ;
+; 16                                           ; 14                            ;
+; 17                                           ; 10                            ;
+; 18                                           ; 3                             ;
+; 19                                           ; 5                             ;
+; 20                                           ; 4                             ;
+; 21                                           ; 6                             ;
+; 22                                           ; 17                            ;
+; 23                                           ; 13                            ;
+; 24                                           ; 7                             ;
+; 25                                           ; 2                             ;
+; 26                                           ; 4                             ;
+; 27                                           ; 3                             ;
+; 28                                           ; 4                             ;
+; 29                                           ; 1                             ;
+; 30                                           ; 1                             ;
+; 31                                           ; 2                             ;
+; 32                                           ; 0                             ;
+; 33                                           ; 1                             ;
+; 34                                           ; 0                             ;
+; 35                                           ; 0                             ;
+; 36                                           ; 0                             ;
+; 37                                           ; 1                             ;
++----------------------------------------------+-------------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 10    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 20    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                    ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Pass         ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 142          ; 0            ; 142          ; 0            ; 0            ; 143       ; 142          ; 0            ; 143       ; 143       ; 0            ; 0            ; 0            ; 0            ; 66           ; 0            ; 0            ; 66           ; 0            ; 0            ; 30           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 143       ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 1            ; 143          ; 1            ; 143          ; 143          ; 0         ; 1            ; 143          ; 0         ; 0         ; 143          ; 143          ; 143          ; 143          ; 77           ; 143          ; 143          ; 77           ; 143          ; 143          ; 113          ; 143          ; 143          ; 143          ; 143          ; 143          ; 143          ; 0         ; 143          ; 143          ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; DRAM_LDQM          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKIN[1]    ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[9]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_UDQM          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_BA_1          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_BA_0          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CAS_N         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CKE           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CS_N          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_RAS_N         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_WE_N          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CLK           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_CLK            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_HS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_VS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[11]      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[10]      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[9]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[8]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[7]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[6]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[5]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[4]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[3]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[2]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[1]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[0]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKOUT[1]   ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKOUT[0]   ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[9]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[8]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[7]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[15]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[14]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[13]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[12]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[11]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[10]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[9]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[8]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[7]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[6]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[5]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[4]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[3]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[2]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[1]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[0]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[31]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[30]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[29]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[28]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[27]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[26]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[25]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[24]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[23]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[22]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[21]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[20]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[19]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[18]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[17]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[16]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[15]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[14]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[13]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[12]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[11]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[10]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[9]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[8]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[7]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[6]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[5]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[4]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[3]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[2]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[1]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[0]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; PS2_DAT            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; PS2_CLK            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[0]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[0]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[1]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKIN[0]    ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[2]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; Unreserved               ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary              ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer.
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                                                                                                                                                                                                                                                                      ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; Source Register                                                                                                                                      ; Destination Register                                                                                                                                                    ; Delay Added in ns ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a10~porta_address_reg0 ; 0.202             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a13~porta_datain_reg0  ; 0.095             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a14~porta_datain_reg0  ; 0.027             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                     ; 0.017             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]               ; 0.015             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]               ; 0.014             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                     ; 0.013             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                    ; 0.013             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                             ; 0.012             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]               ; 0.012             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]               ; 0.012             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]               ; 0.011             ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+Note: This table only shows the top 12 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16F484C6 for design "DE0_D5M"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (15535): Implemented PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" as Cyclone III PLL type
+    Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] port
+    Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of -117 degrees (-2600 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] port
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 4 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 143 total pins
+    Info (169086): Pin VGA_CLK not assigned to an exact location on the device
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity dcfifo_v5o1
+        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* 
+        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* 
+Info (332104): Reading SDC File: 'DE0_D5M.sdc'
+Info (332110): Deriving PLL clocks
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]}
+Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 3 clocks
+    Info (332111):   Period   Clock Name
+    Info (332111): ======== ============
+    Info (332111):   20.000     CLOCK_50
+    Info (332111):    8.000 inst|u6|altpll_component|auto_generated|pll1|clk[0]
+    Info (332111):    8.000 inst|u6|altpll_component|auto_generated|pll1|clk[1]
+Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|rClk[0]
+        Info (176357): Destination node ps2:inst6|clk_div[8]
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK
+Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] (placed in counter C0 of PLL_2)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
+Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] (placed in counter C1 of PLL_2)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
+Info (176353): Automatically promoted node GPIO_1_CLKIN[0]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19
+Info (176353): Automatically promoted node DE0_D5M:inst|rClk[0] 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|rClk[0]~0
+        Info (176357): Destination node GPIO_1_CLKOUT[0]~output
+        Info (176357): Destination node VGA_CLK~output
+Info (176353): Automatically promoted node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|I2C_SCLK~1
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK~0
+Info (176353): Automatically promoted node ps2:inst6|ps2_clk_in 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node ps2:inst6|Equal2~0
+Info (176353): Automatically promoted node ps2:inst6|clk_div[8] 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node ps2:inst6|clk_div[8]~22
+        Info (176357): Destination node ps2:inst6|ps2_clk_in
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_0 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]~6
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]~43
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]~47
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]~47
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]~43
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]~46
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_0~2
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_1 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node GPIO_1[14]~output
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_1~1
+Info (176353): Automatically promoted node ps2:inst6|Equal3~2 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
+        Info (176212): I/O standards used: 3.3-V LVTTL.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 16 total pin(s) used --  30 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used --  21 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used --  44 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 28 total pin(s) used --  19 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  5 pins available
+Warning (15064): PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" output port clk[1] feeds output pin "DRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning (15709): Ignored I/O standard assignments to the following nodes
+    Warning (15710): Ignored I/O standard assignment to node "AUD_ADCDAT"
+    Warning (15710): Ignored I/O standard assignment to node "AUD_ADCLRCK"
+    Warning (15710): Ignored I/O standard assignment to node "AUD_BCLK"
+    Warning (15710): Ignored I/O standard assignment to node "AUD_DACDAT"
+    Warning (15710): Ignored I/O standard assignment to node "AUD_DACLRCK"
+    Warning (15710): Ignored I/O standard assignment to node "AUD_XCK"
+    Warning (15710): Ignored I/O standard assignment to node "BUTTON[0]"
+    Warning (15710): Ignored I/O standard assignment to node "BUTTON[1]"
+    Warning (15710): Ignored I/O standard assignment to node "BUTTON[2]"
+    Warning (15710): Ignored I/O standard assignment to node "CLOCK_50_2"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[12]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[0]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[10]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[11]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[12]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[13]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[14]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[15]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[16]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[17]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[18]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[19]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[1]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[20]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[21]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[2]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[3]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[4]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[5]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[6]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[7]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[8]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[9]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_BYTE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_CE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ15_AM1"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[0]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[10]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[11]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[12]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[13]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[14]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[1]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[2]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[3]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[4]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[5]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[6]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[7]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[8]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[9]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_OE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_RST_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_RY"
+    Warning (15710): Ignored I/O standard assignment to node "FL_WE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_WP_N"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKIN[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKIN[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKOUT[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKOUT[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKIN[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKIN[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKOUT[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKOUT[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO_1[32]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO_1[33]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO_1[34]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO_1[35]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "I2C_SCLK"
+    Warning (15710): Ignored I/O standard assignment to node "I2C_SDAT"
+    Warning (15710): Ignored I/O standard assignment to node "KEY[3]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_BLON"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[0]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[1]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[2]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[3]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[4]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[5]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[6]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[7]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_EN"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_RS"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_RW"
+    Warning (15710): Ignored I/O standard assignment to node "PS2_KBCLK"
+    Warning (15710): Ignored I/O standard assignment to node "PS2_KBDAT"
+    Warning (15710): Ignored I/O standard assignment to node "SD_CLK"
+    Warning (15710): Ignored I/O standard assignment to node "SD_CMD"
+    Warning (15710): Ignored I/O standard assignment to node "SD_DAT0"
+    Warning (15710): Ignored I/O standard assignment to node "SD_DAT3"
+    Warning (15710): Ignored I/O standard assignment to node "SD_WP_N"
+    Warning (15710): Ignored I/O standard assignment to node "UART_CTS"
+    Warning (15710): Ignored I/O standard assignment to node "UART_RTS"
+    Warning (15710): Ignored I/O standard assignment to node "UART_RXD"
+    Warning (15710): Ignored I/O standard assignment to node "UART_TXD"
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "CLOCK_50_2" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_DP" is assigned to location or region, but does not exist in design
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:10
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:03
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 5% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:04
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 2.11 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:06
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Warning (169177): 66 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+    Info (169178): Pin GPIO_1_CLKIN[1] uses I/O standard 3.3-V LVTTL at AA11
+    Info (169178): Pin SW[9] uses I/O standard 3.3-V LVTTL at D2
+    Info (169178): Pin SW[8] uses I/O standard 3.3-V LVTTL at E4
+    Info (169178): Pin DRAM_DQ[15] uses I/O standard 3.3-V LVTTL at F10
+    Info (169178): Pin DRAM_DQ[14] uses I/O standard 3.3-V LVTTL at E10
+    Info (169178): Pin DRAM_DQ[13] uses I/O standard 3.3-V LVTTL at A10
+    Info (169178): Pin DRAM_DQ[12] uses I/O standard 3.3-V LVTTL at B10
+    Info (169178): Pin DRAM_DQ[11] uses I/O standard 3.3-V LVTTL at C10
+    Info (169178): Pin DRAM_DQ[10] uses I/O standard 3.3-V LVTTL at A9
+    Info (169178): Pin DRAM_DQ[9] uses I/O standard 3.3-V LVTTL at B9
+    Info (169178): Pin DRAM_DQ[8] uses I/O standard 3.3-V LVTTL at A8
+    Info (169178): Pin DRAM_DQ[7] uses I/O standard 3.3-V LVTTL at F8
+    Info (169178): Pin DRAM_DQ[6] uses I/O standard 3.3-V LVTTL at H9
+    Info (169178): Pin DRAM_DQ[5] uses I/O standard 3.3-V LVTTL at G9
+    Info (169178): Pin DRAM_DQ[4] uses I/O standard 3.3-V LVTTL at F9
+    Info (169178): Pin DRAM_DQ[3] uses I/O standard 3.3-V LVTTL at E9
+    Info (169178): Pin DRAM_DQ[2] uses I/O standard 3.3-V LVTTL at H10
+    Info (169178): Pin DRAM_DQ[1] uses I/O standard 3.3-V LVTTL at G10
+    Info (169178): Pin DRAM_DQ[0] uses I/O standard 3.3-V LVTTL at D10
+    Info (169178): Pin GPIO_1[31] uses I/O standard 3.3-V LVTTL at V7
+    Info (169178): Pin GPIO_1[30] uses I/O standard 3.3-V LVTTL at V6
+    Info (169178): Pin GPIO_1[29] uses I/O standard 3.3-V LVTTL at U8
+    Info (169178): Pin GPIO_1[28] uses I/O standard 3.3-V LVTTL at Y7
+    Info (169178): Pin GPIO_1[27] uses I/O standard 3.3-V LVTTL at T9
+    Info (169178): Pin GPIO_1[26] uses I/O standard 3.3-V LVTTL at U9
+    Info (169178): Pin GPIO_1[25] uses I/O standard 3.3-V LVTTL at T10
+    Info (169178): Pin GPIO_1[24] uses I/O standard 3.3-V LVTTL at U10
+    Info (169178): Pin GPIO_1[23] uses I/O standard 3.3-V LVTTL at R12
+    Info (169178): Pin GPIO_1[22] uses I/O standard 3.3-V LVTTL at R11
+    Info (169178): Pin GPIO_1[21] uses I/O standard 3.3-V LVTTL at T12
+    Info (169178): Pin GPIO_1[20] uses I/O standard 3.3-V LVTTL at U12
+    Info (169178): Pin GPIO_1[19] uses I/O standard 3.3-V LVTTL at R14
+    Info (169178): Pin GPIO_1[18] uses I/O standard 3.3-V LVTTL at T14
+    Info (169178): Pin GPIO_1[17] uses I/O standard 3.3-V LVTTL at AB7
+    Info (169178): Pin GPIO_1[16] uses I/O standard 3.3-V LVTTL at AA7
+    Info (169178): Pin GPIO_1[15] uses I/O standard 3.3-V LVTTL at AA9
+    Info (169178): Pin GPIO_1[14] uses I/O standard 3.3-V LVTTL at AB9
+    Info (169178): Pin GPIO_1[13] uses I/O standard 3.3-V LVTTL at V15
+    Info (169178): Pin GPIO_1[12] uses I/O standard 3.3-V LVTTL at W15
+    Info (169178): Pin GPIO_1[11] uses I/O standard 3.3-V LVTTL at T15
+    Info (169178): Pin GPIO_1[10] uses I/O standard 3.3-V LVTTL at U15
+    Info (169178): Pin GPIO_1[9] uses I/O standard 3.3-V LVTTL at W17
+    Info (169178): Pin GPIO_1[8] uses I/O standard 3.3-V LVTTL at Y17
+    Info (169178): Pin GPIO_1[7] uses I/O standard 3.3-V LVTTL at AB17
+    Info (169178): Pin GPIO_1[6] uses I/O standard 3.3-V LVTTL at AA17
+    Info (169178): Pin GPIO_1[5] uses I/O standard 3.3-V LVTTL at AA18
+    Info (169178): Pin GPIO_1[4] uses I/O standard 3.3-V LVTTL at AB18
+    Info (169178): Pin GPIO_1[3] uses I/O standard 3.3-V LVTTL at AB19
+    Info (169178): Pin GPIO_1[2] uses I/O standard 3.3-V LVTTL at AA19
+    Info (169178): Pin GPIO_1[1] uses I/O standard 3.3-V LVTTL at AB20
+    Info (169178): Pin GPIO_1[0] uses I/O standard 3.3-V LVTTL at AA20
+    Info (169178): Pin PS2_DAT uses I/O standard 3.3-V LVTTL at P21
+    Info (169178): Pin PS2_CLK uses I/O standard 3.3-V LVTTL at P22
+    Info (169178): Pin SW[4] uses I/O standard 3.3-V LVTTL at G5
+    Info (169178): Pin SW[5] uses I/O standard 3.3-V LVTTL at J7
+    Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21
+    Info (169178): Pin KEY[0] uses I/O standard 3.3-V LVTTL at H2
+    Info (169178): Pin SW[7] uses I/O standard 3.3-V LVTTL at E3
+    Info (169178): Pin SW[6] uses I/O standard 3.3-V LVTTL at H7
+    Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at G4
+    Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at H6
+    Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at H5
+    Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at J6
+    Info (169178): Pin KEY[1] uses I/O standard 3.3-V LVTTL at G3
+    Info (169178): Pin GPIO_1_CLKIN[0] uses I/O standard 3.3-V LVTTL at AB11
+    Info (169178): Pin KEY[2] uses I/O standard 3.3-V LVTTL at F1
+Warning (169064): Following 31 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
+    Info (169065): Pin GPIO_1[31] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[30] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[29] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[28] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[27] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[26] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[25] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[24] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[23] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[22] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[21] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[20] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[18] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[17] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[16] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[15] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[14] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[13] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[12] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[11] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[10] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[9] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[8] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[7] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[6] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[5] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[4] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[3] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[2] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[1] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[0] has a permanently disabled output enable
+Info (144001): Generated suppressed messages file //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 149 warnings
+    Info: Peak virtual memory: 1193 megabytes
+    Info: Processing ended: Tue Mar 08 16:24:34 2016
+    Info: Elapsed time: 00:00:39
+    Info: Total CPU time (on all processors): 00:00:27
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg.
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.summary b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.summary
new file mode 100644
index 0000000..54e630e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Tue Mar 08 16:24:30 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : DE0_D5M
+Top-level Entity Name : TOP_DE0_CAMERA_MOUSE
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 3,638 / 15,408 ( 24 % )
+    Total combinational functions : 3,247 / 15,408 ( 21 % )
+    Dedicated logic registers : 1,389 / 15,408 ( 9 % )
+Total registers : 1389
+Total pins : 143 / 347 ( 41 % )
+Total virtual pins : 0
+Total memory bits : 134,236 / 516,096 ( 26 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 1 / 4 ( 25 % )
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.flow.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.flow.rpt
new file mode 100644
index 0000000..bfb266c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.flow.rpt
@@ -0,0 +1,130 @@
+Flow report for DE0_D5M
+Tue Mar 08 16:24:59 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Flow Summary                                                                          ;
++------------------------------------+--------------------------------------------------+
+; Flow Status                        ; Successful - Tue Mar 08 16:24:45 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                          ;
+; Top-level Entity Name              ; TOP_DE0_CAMERA_MOUSE                             ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 3,638 / 15,408 ( 24 % )                          ;
+;     Total combinational functions  ; 3,247 / 15,408 ( 21 % )                          ;
+;     Dedicated logic registers      ; 1,389 / 15,408 ( 9 % )                           ;
+; Total registers                    ; 1389                                             ;
+; Total pins                         ; 143 / 347 ( 41 % )                               ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 134,236 / 516,096 ( 26 % )                       ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                                   ;
++------------------------------------+--------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 03/08/2016 16:23:19 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; DE0_D5M             ;
++-------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                                ;
++-------------------------------------+---------------------------------------+---------------+----------------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name          ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+----------------------+------------+
+; COMPILER_SIGNATURE_ID               ; 260248564575767.145745419808504       ; --            ; --                   ; --         ;
+; IP_TOOL_NAME                        ; LPM_MUX                               ; --            ; --                   ; --         ;
+; IP_TOOL_VERSION                     ; 13.1                                  ; --            ; --                   ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --                   ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --                   ; --         ;
+; MISC_FILE                           ; vga_mux.bsf                           ; --            ; --                   ; --         ;
+; MISC_FILE                           ; vga_mux.cmp                           ; --            ; --                   ; --         ;
+; PARTITION_COLOR                     ; 14622752                              ; --            ; TOP_DE0_CAMERA_MOUSE ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; TOP_DE0_CAMERA_MOUSE ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; TOP_DE0_CAMERA_MOUSE ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --                   ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --                   ; --         ;
+; SMART_RECOMPILE                     ; On                                    ; Off           ; --                   ; --         ;
+; TOP_LEVEL_ENTITY                    ; TOP_DE0_CAMERA_MOUSE                  ; DE0_D5M       ; --                   ; --         ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS  ; Off                                   ; --            ; --                   ; eda_palace ;
++-------------------------------------+---------------------------------------+---------------+----------------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:27     ; 1.0                     ; 563 MB              ; 00:00:13                           ;
+; Fitter                    ; 00:00:35     ; 1.1                     ; 1193 MB             ; 00:00:25                           ;
+; Assembler                 ; 00:00:03     ; 1.0                     ; 443 MB              ; 00:00:02                           ;
+; TimeQuest Timing Analyzer ; 00:00:11     ; 1.0                     ; 549 MB              ; 00:00:05                           ;
+; Total                     ; 00:01:16     ; --                      ; --                  ; 00:00:45                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-013     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-013     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-013     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-013     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_fit --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_sta DE0_D5M -c DE0_D5M
+
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.jdi b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.jdi
new file mode 100644
index 0000000..5536e37
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="3d95c155c86f9acb4a6a"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="DE0_D5M.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.rpt
new file mode 100644
index 0000000..8f370f6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.rpt
@@ -0,0 +1,3366 @@
+Analysis & Synthesis report for DE0_D5M
+Tue Mar 08 16:23:49 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis IP Cores Summary
+ 10. State Machine - |TOP_DE0_CAMERA_MOUSE|ps2:inst6|cur_state
+ 11. State Machine - |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST
+ 12. Registers Removed During Synthesis
+ 13. Removed Registers Triggering Further Register Optimizations
+ 14. General Register Statistics
+ 15. Inverted Register Statistics
+ 16. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 17. Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2
+ 18. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+ 19. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 20. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 21. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 22. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 23. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 24. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 25. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 26. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 27. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 28. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 29. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 30. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 31. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+ 32. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 33. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 34. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 35. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 36. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 37. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 38. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 39. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 40. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 41. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 42. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 43. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 44. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+ 45. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 46. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 47. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 48. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 49. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 50. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 51. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 52. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 53. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 54. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 55. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 56. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 57. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+ 58. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 59. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 60. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 61. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 62. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 63. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 64. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 65. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 66. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 67. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 68. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 69. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 70. Source assignments for altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2
+ 71. Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1
+ 72. Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3
+ 73. Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component
+ 74. Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component
+ 75. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7
+ 76. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1
+ 77. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1
+ 78. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1
+ 79. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+ 80. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+ 81. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+ 82. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+ 83. Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8
+ 84. Parameter Settings for User Entity Instance: ps2:inst6
+ 85. Parameter Settings for User Entity Instance: vga_mux:inst10|LPM_MUX:LPM_MUX_component
+ 86. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:vga_xy_rsc_mgc_in_wire
+ 87. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:mouse_xy_rsc_mgc_in_wire
+ 88. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:cursor_size_rsc_mgc_in_wire
+ 89. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:video_in_rsc_mgc_in_wire
+ 90. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg
+ 91. Parameter Settings for User Entity Instance: sobel:inst1|mgc_in_wire:vin_rsc_mgc_in_wire
+ 92. Parameter Settings for User Entity Instance: sobel:inst1|mgc_out_stdreg:vout_rsc_mgc_out_stdreg
+ 93. Parameter Settings for User Entity Instance: altshift_taps:fifo_inst2
+ 94. Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0
+ 95. Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1
+ 96. Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7
+ 97. Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5
+ 98. Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2
+ 99. Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6
+100. Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult3
+101. Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4
+102. Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult8
+103. altshift_taps Parameter Settings by Entity Instance
+104. altpll Parameter Settings by Entity Instance
+105. dcfifo Parameter Settings by Entity Instance
+106. lpm_mult Parameter Settings by Entity Instance
+107. Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8"
+108. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2"
+109. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1"
+110. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2"
+111. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"
+112. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"
+113. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"
+114. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7"
+115. Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5"
+116. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"
+117. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4"
+118. Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3"
+119. Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1"
+120. Elapsed Time Per Partition
+121. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                          ;
++------------------------------------+--------------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Tue Mar 08 16:23:49 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                          ;
+; Top-level Entity Name              ; TOP_DE0_CAMERA_MOUSE                             ;
+; Family                             ; Cyclone III                                      ;
+; Total logic elements               ; 3,842                                            ;
+;     Total combinational functions  ; 3,246                                            ;
+;     Dedicated logic registers      ; 1,389                                            ;
+; Total registers                    ; 1389                                             ;
+; Total pins                         ; 143                                              ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 134,236                                          ;
+; Embedded Multiplier 9-bit elements ; 0                                                ;
+; Total PLLs                         ; 1                                                ;
++------------------------------------+--------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                          ;
++----------------------------------------------------------------------------+----------------------+--------------------+
+; Option                                                                     ; Setting              ; Default Value      ;
++----------------------------------------------------------------------------+----------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6         ;                    ;
+; Top-level entity name                                                      ; TOP_DE0_CAMERA_MOUSE ; DE0_D5M            ;
+; Family name                                                                ; Cyclone III          ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; On                   ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                   ; On                 ;
+; Enable compact report table                                                ; Off                  ; Off                ;
+; Restructure Multiplexers                                                   ; Auto                 ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                  ; Off                ;
+; Preserve fewer node names                                                  ; On                   ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                  ; Off                ;
+; Verilog Version                                                            ; Verilog_2001         ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993            ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto                 ; Auto               ;
+; Safe State Machine                                                         ; Off                  ; Off                ;
+; Extract Verilog State Machines                                             ; On                   ; On                 ;
+; Extract VHDL State Machines                                                ; On                   ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                  ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000                 ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                  ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                   ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                   ; On                 ;
+; Parallel Synthesis                                                         ; On                   ; On                 ;
+; DSP Block Balancing                                                        ; Auto                 ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                   ; On                 ;
+; Power-Up Don't Care                                                        ; On                   ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                  ; Off                ;
+; Remove Duplicate Registers                                                 ; On                   ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                  ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                  ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                  ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                  ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                  ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                   ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                  ; Off                ;
+; Optimization Technique                                                     ; Balanced             ; Balanced           ;
+; Carry Chain Length                                                         ; 70                   ; 70                 ;
+; Auto Carry Chains                                                          ; On                   ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                   ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                  ; Off                ;
+; Auto ROM Replacement                                                       ; On                   ; On                 ;
+; Auto RAM Replacement                                                       ; On                   ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                   ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto                 ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto                 ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                   ; On                 ;
+; Strict RAM Replacement                                                     ; Off                  ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                   ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                  ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                   ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                  ; Off                ;
+; Auto Resource Sharing                                                      ; Off                  ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                  ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                  ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                  ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                   ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                  ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                   ; On                 ;
+; Report Parameter Settings                                                  ; On                   ; On                 ;
+; Report Source Assignments                                                  ; On                   ; On                 ;
+; Report Connectivity Checks                                                 ; On                   ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                  ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                    ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation   ; Normal compilation ;
+; HDL message level                                                          ; Level2               ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                  ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000                 ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000                 ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                  ; 100                ;
+; Clock MUX Protection                                                       ; On                   ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                  ; Off                ;
+; Block Design Naming                                                        ; Auto                 ; Auto               ;
+; SDC constraint protection                                                  ; Off                  ; Off                ;
+; Synthesis Effort                                                           ; Auto                 ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                   ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                  ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium               ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto                 ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                   ; On                 ;
+; Synthesis Seed                                                             ; 1                    ; 1                  ;
++----------------------------------------------------------------------------+----------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                                                                                                                       ;
++--------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path           ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                                                                                                                   ; Library ;
++--------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; ../../../../../Sobel/Sobel Quartus/sobel.v ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v                                                                                        ;         ;
+; V/ps2.v                                    ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v                                   ;         ;
+; Sdram_Control_4Port/Sdram_Params.h         ; yes             ; User Unspecified File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h        ;         ;
+; Sdram_Control_4Port/command.v              ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v             ;         ;
+; Sdram_Control_4Port/control_interface.v    ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v   ;         ;
+; Sdram_Control_4Port/sdr_data_path.v        ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v       ;         ;
+; Sdram_Control_4Port/Sdram_Control_4Port.v  ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v ;         ;
+; Sdram_Control_4Port/Sdram_FIFO.v           ; yes             ; User Wizard-Generated File         ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v          ;         ;
+; V/VGA_Param.h                              ; yes             ; User Unspecified File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Param.h                             ;         ;
+; V/CCD_Capture.v                            ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v                           ;         ;
+; V/I2C_CCD_Config.v                         ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v                        ;         ;
+; V/I2C_Controller.v                         ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v                        ;         ;
+; V/Line_Buffer.v                            ; yes             ; User Wizard-Generated File         ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v                           ;         ;
+; V/RAW2RGB.v                                ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v                               ;         ;
+; V/Reset_Delay.v                            ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v                           ;         ;
+; V/sdram_pll.v                              ; yes             ; User Wizard-Generated File         ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v                             ;         ;
+; V/SEG7_LUT.v                               ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v                              ;         ;
+; V/SEG7_LUT_8.v                             ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v                            ;         ;
+; V/VGA_Controller.v                         ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v                        ;         ;
+; DE0_D5M.v                                  ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v                                 ;         ;
+; V/TOP_DE0_CAMERA_MOUSE.bdf                 ; yes             ; User Block Diagram/Schematic File  ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf                ;         ;
+; vga_mux.vhd                                ; yes             ; User Wizard-Generated File         ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd                               ;         ;
+; catapult_ip/mouse/rtl_mgc_ioport.v         ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v        ;         ;
+; catapult_ip/mouse/rtl.v                    ; yes             ; User Verilog HDL File              ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v                   ;         ;
+; altshift_taps.tdf                          ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf                                                                                                            ;         ;
+; altdpram.inc                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altdpram.inc                                                                                                                 ;         ;
+; lpm_counter.inc                            ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.inc                                                                                                              ;         ;
+; lpm_compare.inc                            ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_compare.inc                                                                                                              ;         ;
+; lpm_constant.inc                           ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc                                                                                                             ;         ;
+; db/shift_taps_rnn.tdf                      ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf                     ;         ;
+; db/altsyncram_lp81.tdf                     ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_lp81.tdf                    ;         ;
+; db/cntr_cuf.tdf                            ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf                           ;         ;
+; db/cmpr_vgc.tdf                            ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_vgc.tdf                           ;         ;
+; altpll.tdf                                 ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf                                                                                                                   ;         ;
+; aglobal130.inc                             ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc                                                                                                               ;         ;
+; stratix_pll.inc                            ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_pll.inc                                                                                                              ;         ;
+; stratixii_pll.inc                          ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratixii_pll.inc                                                                                                            ;         ;
+; cycloneii_pll.inc                          ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/cycloneii_pll.inc                                                                                                            ;         ;
+; db/altpll_9ee2.tdf                         ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf                        ;         ;
+; dcfifo.tdf                                 ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf                                                                                                                   ;         ;
+; lpm_add_sub.inc                            ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc                                                                                                              ;         ;
+; a_graycounter.inc                          ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_graycounter.inc                                                                                                            ;         ;
+; a_fefifo.inc                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_fefifo.inc                                                                                                                 ;         ;
+; a_gray2bin.inc                             ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_gray2bin.inc                                                                                                               ;         ;
+; dffpipe.inc                                ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/dffpipe.inc                                                                                                                  ;         ;
+; alt_sync_fifo.inc                          ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_sync_fifo.inc                                                                                                            ;         ;
+; altsyncram_fifo.inc                        ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram_fifo.inc                                                                                                          ;         ;
+; db/dcfifo_v5o1.tdf                         ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf                        ;         ;
+; db/a_gray2bin_tgb.tdf                      ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_gray2bin_tgb.tdf                     ;         ;
+; db/a_graycounter_s57.tdf                   ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf                  ;         ;
+; db/a_graycounter_ojc.tdf                   ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf                  ;         ;
+; db/altsyncram_de51.tdf                     ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf                    ;         ;
+; db/dffpipe_oe9.tdf                         ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_oe9.tdf                        ;         ;
+; db/alt_synch_pipe_qld.tdf                  ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf                 ;         ;
+; db/dffpipe_pe9.tdf                         ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_pe9.tdf                        ;         ;
+; db/alt_synch_pipe_rld.tdf                  ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf                 ;         ;
+; db/dffpipe_qe9.tdf                         ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_qe9.tdf                        ;         ;
+; db/cmpr_e66.tdf                            ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_e66.tdf                           ;         ;
+; lpm_mux.tdf                                ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.tdf                                                                                                                  ;         ;
+; muxlut.inc                                 ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/muxlut.inc                                                                                                                   ;         ;
+; bypassff.inc                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/bypassff.inc                                                                                                                 ;         ;
+; altshift.inc                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.inc                                                                                                                 ;         ;
+; db/mux_u7e.tdf                             ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/mux_u7e.tdf                            ;         ;
+; db/shift_taps_jpm.tdf                      ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_jpm.tdf                     ;         ;
+; db/altsyncram_5n81.tdf                     ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_5n81.tdf                    ;         ;
+; db/cntr_1tf.tdf                            ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf                           ;         ;
+; db/cmpr_ugc.tdf                            ; yes             ; Auto-Generated Megafunction        ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_ugc.tdf                           ;         ;
+; lpm_mult.tdf                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf                                                                                                                 ;         ;
+; multcore.inc                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.inc                                                                                                                 ;         ;
+; multcore.tdf                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf                                                                                                                 ;         ;
+; csa_add.inc                                ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/csa_add.inc                                                                                                                  ;         ;
+; mpar_add.inc                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.inc                                                                                                                 ;         ;
+; muleabz.inc                                ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/muleabz.inc                                                                                                                  ;         ;
+; mul_lfrg.inc                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mul_lfrg.inc                                                                                                                 ;         ;
+; mul_boothc.inc                             ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mul_boothc.inc                                                                                                               ;         ;
+; alt_ded_mult.inc                           ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_ded_mult.inc                                                                                                             ;         ;
+; alt_ded_mult_y.inc                         ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_ded_mult_y.inc                                                                                                           ;         ;
+; mpar_add.tdf                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf                                                                                                                 ;         ;
+; altshift.tdf                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.tdf                                                                                                                 ;         ;
++--------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                                                                                       ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+; Resource                                    ; Usage                                                                               ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+; Estimated Total logic elements              ; 3,842                                                                               ;
+;                                             ;                                                                                     ;
+; Total combinational functions               ; 3246                                                                                ;
+; Logic element usage by number of LUT inputs ;                                                                                     ;
+;     -- 4 input functions                    ; 769                                                                                 ;
+;     -- 3 input functions                    ; 1533                                                                                ;
+;     -- <=2 input functions                  ; 944                                                                                 ;
+;                                             ;                                                                                     ;
+; Logic elements by mode                      ;                                                                                     ;
+;     -- normal mode                          ; 1625                                                                                ;
+;     -- arithmetic mode                      ; 1621                                                                                ;
+;                                             ;                                                                                     ;
+; Total registers                             ; 1389                                                                                ;
+;     -- Dedicated logic registers            ; 1389                                                                                ;
+;     -- I/O registers                        ; 0                                                                                   ;
+;                                             ;                                                                                     ;
+; I/O pins                                    ; 143                                                                                 ;
+; Total memory bits                           ; 134236                                                                              ;
+; Embedded Multiplier 9-bit elements          ; 0                                                                                   ;
+; Total PLLs                                  ; 1                                                                                   ;
+;     -- PLLs                                 ; 1                                                                                   ;
+;                                             ;                                                                                     ;
+; Maximum fan-out node                        ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ;
+; Maximum fan-out                             ; 572                                                                                 ;
+; Total fan-out                               ; 17062                                                                               ;
+; Average fan-out                             ; 3.31                                                                                ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                        ;
++----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                               ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                  ; Library Name ;
++----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |TOP_DE0_CAMERA_MOUSE                                    ; 3246 (2)          ; 1389 (0)     ; 134236      ; 0            ; 0       ; 0         ; 143  ; 0            ; |TOP_DE0_CAMERA_MOUSE                                                                                                                                                                ; work         ;
+;    |DE0_D5M:inst|                                        ; 1172 (1)          ; 1013 (15)    ; 62416       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst                                                                                                                                                   ; work         ;
+;       |CCD_Capture:u3|                                   ; 40 (40)           ; 33 (33)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3                                                                                                                                    ; work         ;
+;       |I2C_CCD_Config:u8|                                ; 240 (171)         ; 132 (94)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8                                                                                                                                 ; work         ;
+;          |I2C_Controller:u0|                             ; 69 (69)           ; 38 (38)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0                                                                                                               ; work         ;
+;       |RAW2RGB:u4|                                       ; 84 (68)           ; 66 (55)      ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4                                                                                                                                        ; work         ;
+;          |Line_Buffer:u0|                                ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                                                                                                                         ; work         ;
+;             |altshift_taps:altshift_taps_component|      ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component                                                                                   ; work         ;
+;                |shift_taps_rnn:auto_generated|           ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated                                                     ; work         ;
+;                   |altsyncram_lp81:altsyncram2|          ; 0 (0)             ; 0 (0)        ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2                         ; work         ;
+;                   |cntr_cuf:cntr1|                       ; 16 (13)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1                                      ; work         ;
+;                      |cmpr_vgc:cmpr4|                    ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4                       ; work         ;
+;       |Reset_Delay:u2|                                   ; 50 (50)           ; 35 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Reset_Delay:u2                                                                                                                                    ; work         ;
+;       |Sdram_Control_4Port:u7|                           ; 677 (215)         ; 704 (137)    ; 31744       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7                                                                                                                            ; work         ;
+;          |Sdram_FIFO:read_fifo1|                         ; 84 (0)            ; 116 (0)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 84 (0)            ; 116 (0)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 84 (15)           ; 116 (30)     ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin|      ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 21 (21)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)             ; 0 (0)        ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:read_fifo2|                         ; 85 (0)            ; 116 (0)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 85 (0)            ; 116 (0)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 85 (15)           ; 116 (30)     ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin|      ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 22 (22)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)             ; 0 (0)        ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:write_fifo1|                        ; 85 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 85 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 85 (15)           ; 116 (30)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 21 (21)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |Sdram_FIFO:write_fifo2|                        ; 85 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 85 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 85 (15)           ; 116 (30)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 21 (21)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |command:command1|                              ; 60 (60)           ; 48 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1                                                                                                           ; work         ;
+;          |control_interface:control1|                    ; 63 (63)           ; 55 (55)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1                                                                                                 ; work         ;
+;       |VGA_Controller:u1|                                ; 80 (80)           ; 28 (28)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1                                                                                                                                 ; work         ;
+;       |sdram_pll:u6|                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6                                                                                                                                      ; work         ;
+;          |altpll:altpll_component|                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component                                                                                                              ; work         ;
+;             |altpll_9ee2:auto_generated|                 ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated                                                                                   ; work         ;
+;    |altshift_taps:fifo_inst2|                            ; 15 (0)            ; 10 (0)       ; 71820       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2                                                                                                                                       ; work         ;
+;       |shift_taps_jpm:auto_generated|                    ; 15 (0)            ; 10 (0)       ; 71820       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated                                                                                                         ; work         ;
+;          |altsyncram_5n81:altsyncram2|                   ; 0 (0)             ; 0 (0)        ; 71820       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2                                                                             ; work         ;
+;          |cntr_1tf:cntr1|                                ; 15 (12)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1                                                                                          ; work         ;
+;             |cmpr_ugc:cmpr4|                             ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|cmpr_ugc:cmpr4                                                                           ; work         ;
+;    |ps2:inst6|                                           ; 102 (74)          ; 99 (99)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6                                                                                                                                                      ; work         ;
+;       |SEG7_LUT:U1|                                      ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U1                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U2|                                      ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U2                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U3|                                      ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U3                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U4|                                      ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U4                                                                                                                                          ; work         ;
+;    |sobel:inst1|                                         ; 1834 (0)          ; 255 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1                                                                                                                                                    ; work         ;
+;       |sobel_core:sobel_core_inst|                       ; 1834 (1794)       ; 255 (255)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst                                                                                                                         ; work         ;
+;          |lpm_mult:Mult0|                                ; 3 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult1|                                ; 5 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult2|                                ; 2 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult3|                                ; 6 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult3                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult4|                                ; 6 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult5|                                ; 6 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult6|                                ; 4 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult7|                                ; 2 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7|multcore:mult_core                                                                                       ; work         ;
+;          |lpm_mult:Mult8|                                ; 6 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult8                                                                                                          ; work         ;
+;             |multcore:mult_core|                         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult8|multcore:mult_core                                                                                       ; work         ;
+;    |vga_mouse_square:vga_mouse_catapult_inst|            ; 97 (0)            ; 12 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst                                                                                                                       ; work         ;
+;       |vga_mouse_square_core:vga_mouse_square_core_inst| ; 97 (97)           ; 12 (12)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst                                                                      ; work         ;
+;    |vga_mux:inst10|                                      ; 24 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10                                                                                                                                                 ; work         ;
+;       |lpm_mux:LPM_MUX_component|                        ; 24 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component                                                                                                                       ; work         ;
+;          |mux_u7e:auto_generated|                        ; 24 (24)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated                                                                                                ; work         ;
++----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                       ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; Name                                                                                                                                              ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1278         ; 24           ; 1278         ; 24           ; 30672 ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+; altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2|ALTSYNCRAM                                                     ; AUTO ; Simple Dual Port ; 798          ; 90           ; 798          ; 90           ; 71820 ; None ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                                                                                                  ;
++--------+----------------------------+---------+--------------+--------------+----------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Vendor ; IP Core Name               ; Version ; Release Date ; License Type ; Entity Instance                                                                  ; IP Include File                                                                                                                                                       ;
++--------+----------------------------+---------+--------------+--------------+----------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Altera ; Shift register (RAM-based) ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                     ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v                  ;
+; Altera ; ALTPLL                     ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6                                  ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v                    ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1  ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2  ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1 ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2 ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; LPM_MUX                    ; 13.1    ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10                                             ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd                      ;
++--------+----------------------------+---------+--------------+--------------+----------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------------+
+; State Machine - |TOP_DE0_CAMERA_MOUSE|ps2:inst6|cur_state                                      ;
++-------------------+-----------------+-------------------+-------------------+------------------+
+; Name              ; cur_state.trans ; cur_state.pulldat ; cur_state.pullclk ; cur_state.listen ;
++-------------------+-----------------+-------------------+-------------------+------------------+
+; cur_state.listen  ; 0               ; 0                 ; 0                 ; 0                ;
+; cur_state.pullclk ; 0               ; 0                 ; 1                 ; 1                ;
+; cur_state.pulldat ; 0               ; 1                 ; 0                 ; 1                ;
+; cur_state.trans   ; 1               ; 0                 ; 0                 ; 1                ;
++-------------------+-----------------+-------------------+-------------------+------------------+
+
+
+Encoding Type:  One-Hot
++--------------------------------------------------------------------------------+
+; State Machine - |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST ;
++----------------+----------------+----------------+-----------------------------+
+; Name           ; mSetup_ST.0000 ; mSetup_ST.0010 ; mSetup_ST.0001              ;
++----------------+----------------+----------------+-----------------------------+
+; mSetup_ST.0000 ; 0              ; 0              ; 0                           ;
+; mSetup_ST.0001 ; 1              ; 0              ; 1                           ;
+; mSetup_ST.0010 ; 1              ; 1              ; 0                           ;
++----------------+----------------+----------------+-----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                                                                                                                                                                                ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+; Register name                                                                                                                               ; Reason for Removal                                                                  ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[15]                                                                                            ; Lost fanout                                                                         ;
+; ps2:inst6|dout_reg[9]                                                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE                                                                                    ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE                                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31]                                                                                                ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27..29]                                                                                            ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25]                                                                                                ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27..29]                                                                                 ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout                                                                         ;
+; sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[9,19]                                                                      ; Merged with sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[29]    ;
+; sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[8,18]                                                                      ; Merged with sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[28]    ;
+; sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[7,17]                                                                      ; Merged with sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[27]    ;
+; sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[6,16]                                                                      ; Merged with sobel:inst1|sobel_core:sobel_core_inst|vout_rsc_mgc_out_stdreg_d[26]    ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[0..6]                                                                                           ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7]                          ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[0..6]                                                                                             ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7]                            ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[0..6]                                                                  ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7] ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[1,2]                                                                                         ; Merged with DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]                       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7]                                                                                              ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|rClk[1]                                                                                                                        ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8]                                                                                              ; Stuck at VCC due to stuck port data_in                                              ;
+; ps2:inst6|cur_state~4                                                                                                                       ; Lost fanout                                                                         ;
+; ps2:inst6|cur_state~5                                                                                                                       ; Lost fanout                                                                         ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~9                                                                                                  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~10                                                                                                 ; Lost fanout                                                                         ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[1..15]                                                                                                   ; Lost fanout                                                                         ;
+; sobel:inst1|sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[0]                                                                             ; Merged with sobel:inst1|sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[2]         ;
+; sobel:inst1|sobel_core:sobel_core_inst|ACC1_mul_57_itm_2[0]                                                                                 ; Merged with sobel:inst1|sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[2]         ;
+; sobel:inst1|sobel_core:sobel_core_inst|ACC1_mul_57_itm_2[1]                                                                                 ; Merged with sobel:inst1|sobel_core:sobel_core_inst|ACC1_mul_57_itm_1_sg2[1]         ;
+; Total Number of Removed Registers = 154                                                                                                     ;                                                                                     ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                                                                                     ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+; Register name                                            ; Reason for Removal        ; Registers Removed due to This Register                                   ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8]       ; Stuck at VCC              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7],                          ;
+;                                                          ; due to stuck port data_in ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7],                            ;
+;                                                          ;                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7], ;
+;                                                          ;                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8]                           ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE ; Stuck at VCC              ; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE                                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[29]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[29]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[28]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[28]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 1389  ;
+; Number of registers using Synchronous Clear  ; 131   ;
+; Number of registers using Synchronous Load   ; 91    ;
+; Number of registers using Asynchronous Clear ; 995   ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 434   ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Inverted Register Statistics                                                                                                                                   ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Inverted Register                                                                                                                                    ; Fan out ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                                   ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                                    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0  ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0  ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0  ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0  ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6     ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]                                                                                       ; 12      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]                                                                                       ; 13      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]                                                                                       ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2]                                                                                       ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK                                                                                                ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9     ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9     ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 8       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1]                                                                                       ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0]                                                                                       ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6    ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6    ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END                                                                                                 ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9    ; 4       ;
+; Total number of inverted registers = 30                                                                                                              ;         ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                              ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
+; 3:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[2]              ;
+; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[7] ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]   ;
+; 4:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|mCCD_G[12]                                      ;
+; 4:1                ; 20 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|mCCD_R[11]                                      ;
+; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]                      ;
+; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3|X_Cont[2]                                   ;
+; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3|Y_Cont[0]                                   ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]                        ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]                       ;
+; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]        ;
+; 5:1                ; 15 bits   ; 45 LEs        ; 30 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]                           ;
+; 64:1               ; 5 bits    ; 210 LEs       ; 60 LEs               ; 150 LEs                ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[15]                            ;
+; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]                              ;
+; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]                          ;
+; 7:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]                          ;
+; 7:1                ; 10 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4]                               ;
+; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]          ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                       ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|Mux12                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2 ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                       ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                        ;
++---------------------------------+-------+------+----------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                            ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                             ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                       ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                       ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                        ;
++---------------------------------+-------+------+----------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                            ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                             ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                       ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                      ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                       ;
++---------------------------------+-------+------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                           ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                            ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                            ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                      ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                             ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                      ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                       ;
++---------------------------------+-------+------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                           ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                            ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                            ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                      ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                             ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2 ;
++---------------------------------+--------------------+------+---------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                          ;
++---------------------------------+--------------------+------+---------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                           ;
++---------------------------------+--------------------+------+---------------------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1 ;
++----------------+-------+----------------------------------------------------+
+; Parameter Name ; Value ; Type                                               ;
++----------------+-------+----------------------------------------------------+
+; H_SYNC_CYC     ; 96    ; Signed Integer                                     ;
+; H_SYNC_BACK    ; 48    ; Signed Integer                                     ;
+; H_SYNC_ACT     ; 640   ; Signed Integer                                     ;
+; H_SYNC_FRONT   ; 16    ; Signed Integer                                     ;
+; H_SYNC_TOTAL   ; 800   ; Signed Integer                                     ;
+; V_SYNC_CYC     ; 2     ; Signed Integer                                     ;
+; V_SYNC_BACK    ; 33    ; Signed Integer                                     ;
+; V_SYNC_ACT     ; 480   ; Signed Integer                                     ;
+; V_SYNC_FRONT   ; 10    ; Signed Integer                                     ;
+; V_SYNC_TOTAL   ; 525   ; Signed Integer                                     ;
+; X_START        ; 144   ; Signed Integer                                     ;
+; Y_START        ; 35    ; Signed Integer                                     ;
++----------------+-------+----------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3 ;
++----------------+-------+-------------------------------------------------+
+; Parameter Name ; Value ; Type                                            ;
++----------------+-------+-------------------------------------------------+
+; COLUMN_WIDTH   ; 1280  ; Signed Integer                                  ;
++----------------+-------+-------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+; Parameter Name ; Value          ; Type                                                                                    ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA  ; 1              ; Untyped                                                                                 ;
+; NUMBER_OF_TAPS ; 2              ; Signed Integer                                                                          ;
+; TAP_DISTANCE   ; 1280           ; Signed Integer                                                                          ;
+; WIDTH          ; 12             ; Signed Integer                                                                          ;
+; POWER_UP_STATE ; CLEARED        ; Untyped                                                                                 ;
+; CBXI_PARAMETER ; shift_taps_rnn ; Untyped                                                                                 ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ;
++-------------------------------+-------------------+--------------------------------------------+
+; Parameter Name                ; Value             ; Type                                       ;
++-------------------------------+-------------------+--------------------------------------------+
+; OPERATION_MODE                ; NORMAL            ; Untyped                                    ;
+; PLL_TYPE                      ; AUTO              ; Untyped                                    ;
+; LPM_HINT                      ; UNUSED            ; Untyped                                    ;
+; QUALIFY_CONF_DONE             ; OFF               ; Untyped                                    ;
+; COMPENSATE_CLOCK              ; CLK0              ; Untyped                                    ;
+; SCAN_CHAIN                    ; LONG              ; Untyped                                    ;
+; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                                    ;
+; INCLK0_INPUT_FREQUENCY        ; 20000             ; Signed Integer                             ;
+; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                                    ;
+; GATE_LOCK_SIGNAL              ; NO                ; Untyped                                    ;
+; GATE_LOCK_COUNTER             ; 0                 ; Untyped                                    ;
+; LOCK_HIGH                     ; 1                 ; Untyped                                    ;
+; LOCK_LOW                      ; 1                 ; Untyped                                    ;
+; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                                    ;
+; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                                    ;
+; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                                    ;
+; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                                    ;
+; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                                    ;
+; SKIP_VCO                      ; OFF               ; Untyped                                    ;
+; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                                    ;
+; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                                    ;
+; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                                    ;
+; BANDWIDTH                     ; 0                 ; Untyped                                    ;
+; BANDWIDTH_TYPE                ; AUTO              ; Untyped                                    ;
+; SPREAD_FREQUENCY              ; 0                 ; Untyped                                    ;
+; DOWN_SPREAD                   ; 0                 ; Untyped                                    ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                                    ;
+; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped                                    ;
+; CLK9_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK8_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK7_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK6_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK2_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK1_MULTIPLY_BY              ; 5                 ; Signed Integer                             ;
+; CLK0_MULTIPLY_BY              ; 5                 ; Signed Integer                             ;
+; CLK9_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK8_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK7_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK6_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK5_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK4_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK3_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK2_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK1_DIVIDE_BY                ; 2                 ; Signed Integer                             ;
+; CLK0_DIVIDE_BY                ; 2                 ; Signed Integer                             ;
+; CLK9_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK8_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK7_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK6_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK1_PHASE_SHIFT              ; -2600             ; Untyped                                    ;
+; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK5_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK4_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK3_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK2_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK1_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK0_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK9_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK8_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK7_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK6_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK5_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK4_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK3_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK2_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK1_DUTY_CYCLE               ; 50                ; Signed Integer                             ;
+; CLK0_DUTY_CYCLE               ; 50                ; Signed Integer                             ;
+; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; LOCK_WINDOW_UI                ;  0.05             ; Untyped                                    ;
+; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped                                    ;
+; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped                                    ;
+; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped                                    ;
+; DPA_MULTIPLY_BY               ; 0                 ; Untyped                                    ;
+; DPA_DIVIDE_BY                 ; 1                 ; Untyped                                    ;
+; DPA_DIVIDER                   ; 0                 ; Untyped                                    ;
+; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; VCO_MULTIPLY_BY               ; 0                 ; Untyped                                    ;
+; VCO_DIVIDE_BY                 ; 0                 ; Untyped                                    ;
+; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                                    ;
+; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                                    ;
+; VCO_MIN                       ; 0                 ; Untyped                                    ;
+; VCO_MAX                       ; 0                 ; Untyped                                    ;
+; VCO_CENTER                    ; 0                 ; Untyped                                    ;
+; PFD_MIN                       ; 0                 ; Untyped                                    ;
+; PFD_MAX                       ; 0                 ; Untyped                                    ;
+; M_INITIAL                     ; 0                 ; Untyped                                    ;
+; M                             ; 0                 ; Untyped                                    ;
+; N                             ; 1                 ; Untyped                                    ;
+; M2                            ; 1                 ; Untyped                                    ;
+; N2                            ; 1                 ; Untyped                                    ;
+; SS                            ; 1                 ; Untyped                                    ;
+; C0_HIGH                       ; 0                 ; Untyped                                    ;
+; C1_HIGH                       ; 0                 ; Untyped                                    ;
+; C2_HIGH                       ; 0                 ; Untyped                                    ;
+; C3_HIGH                       ; 0                 ; Untyped                                    ;
+; C4_HIGH                       ; 0                 ; Untyped                                    ;
+; C5_HIGH                       ; 0                 ; Untyped                                    ;
+; C6_HIGH                       ; 0                 ; Untyped                                    ;
+; C7_HIGH                       ; 0                 ; Untyped                                    ;
+; C8_HIGH                       ; 0                 ; Untyped                                    ;
+; C9_HIGH                       ; 0                 ; Untyped                                    ;
+; C0_LOW                        ; 0                 ; Untyped                                    ;
+; C1_LOW                        ; 0                 ; Untyped                                    ;
+; C2_LOW                        ; 0                 ; Untyped                                    ;
+; C3_LOW                        ; 0                 ; Untyped                                    ;
+; C4_LOW                        ; 0                 ; Untyped                                    ;
+; C5_LOW                        ; 0                 ; Untyped                                    ;
+; C6_LOW                        ; 0                 ; Untyped                                    ;
+; C7_LOW                        ; 0                 ; Untyped                                    ;
+; C8_LOW                        ; 0                 ; Untyped                                    ;
+; C9_LOW                        ; 0                 ; Untyped                                    ;
+; C0_INITIAL                    ; 0                 ; Untyped                                    ;
+; C1_INITIAL                    ; 0                 ; Untyped                                    ;
+; C2_INITIAL                    ; 0                 ; Untyped                                    ;
+; C3_INITIAL                    ; 0                 ; Untyped                                    ;
+; C4_INITIAL                    ; 0                 ; Untyped                                    ;
+; C5_INITIAL                    ; 0                 ; Untyped                                    ;
+; C6_INITIAL                    ; 0                 ; Untyped                                    ;
+; C7_INITIAL                    ; 0                 ; Untyped                                    ;
+; C8_INITIAL                    ; 0                 ; Untyped                                    ;
+; C9_INITIAL                    ; 0                 ; Untyped                                    ;
+; C0_MODE                       ; BYPASS            ; Untyped                                    ;
+; C1_MODE                       ; BYPASS            ; Untyped                                    ;
+; C2_MODE                       ; BYPASS            ; Untyped                                    ;
+; C3_MODE                       ; BYPASS            ; Untyped                                    ;
+; C4_MODE                       ; BYPASS            ; Untyped                                    ;
+; C5_MODE                       ; BYPASS            ; Untyped                                    ;
+; C6_MODE                       ; BYPASS            ; Untyped                                    ;
+; C7_MODE                       ; BYPASS            ; Untyped                                    ;
+; C8_MODE                       ; BYPASS            ; Untyped                                    ;
+; C9_MODE                       ; BYPASS            ; Untyped                                    ;
+; C0_PH                         ; 0                 ; Untyped                                    ;
+; C1_PH                         ; 0                 ; Untyped                                    ;
+; C2_PH                         ; 0                 ; Untyped                                    ;
+; C3_PH                         ; 0                 ; Untyped                                    ;
+; C4_PH                         ; 0                 ; Untyped                                    ;
+; C5_PH                         ; 0                 ; Untyped                                    ;
+; C6_PH                         ; 0                 ; Untyped                                    ;
+; C7_PH                         ; 0                 ; Untyped                                    ;
+; C8_PH                         ; 0                 ; Untyped                                    ;
+; C9_PH                         ; 0                 ; Untyped                                    ;
+; L0_HIGH                       ; 1                 ; Untyped                                    ;
+; L1_HIGH                       ; 1                 ; Untyped                                    ;
+; G0_HIGH                       ; 1                 ; Untyped                                    ;
+; G1_HIGH                       ; 1                 ; Untyped                                    ;
+; G2_HIGH                       ; 1                 ; Untyped                                    ;
+; G3_HIGH                       ; 1                 ; Untyped                                    ;
+; E0_HIGH                       ; 1                 ; Untyped                                    ;
+; E1_HIGH                       ; 1                 ; Untyped                                    ;
+; E2_HIGH                       ; 1                 ; Untyped                                    ;
+; E3_HIGH                       ; 1                 ; Untyped                                    ;
+; L0_LOW                        ; 1                 ; Untyped                                    ;
+; L1_LOW                        ; 1                 ; Untyped                                    ;
+; G0_LOW                        ; 1                 ; Untyped                                    ;
+; G1_LOW                        ; 1                 ; Untyped                                    ;
+; G2_LOW                        ; 1                 ; Untyped                                    ;
+; G3_LOW                        ; 1                 ; Untyped                                    ;
+; E0_LOW                        ; 1                 ; Untyped                                    ;
+; E1_LOW                        ; 1                 ; Untyped                                    ;
+; E2_LOW                        ; 1                 ; Untyped                                    ;
+; E3_LOW                        ; 1                 ; Untyped                                    ;
+; L0_INITIAL                    ; 1                 ; Untyped                                    ;
+; L1_INITIAL                    ; 1                 ; Untyped                                    ;
+; G0_INITIAL                    ; 1                 ; Untyped                                    ;
+; G1_INITIAL                    ; 1                 ; Untyped                                    ;
+; G2_INITIAL                    ; 1                 ; Untyped                                    ;
+; G3_INITIAL                    ; 1                 ; Untyped                                    ;
+; E0_INITIAL                    ; 1                 ; Untyped                                    ;
+; E1_INITIAL                    ; 1                 ; Untyped                                    ;
+; E2_INITIAL                    ; 1                 ; Untyped                                    ;
+; E3_INITIAL                    ; 1                 ; Untyped                                    ;
+; L0_MODE                       ; BYPASS            ; Untyped                                    ;
+; L1_MODE                       ; BYPASS            ; Untyped                                    ;
+; G0_MODE                       ; BYPASS            ; Untyped                                    ;
+; G1_MODE                       ; BYPASS            ; Untyped                                    ;
+; G2_MODE                       ; BYPASS            ; Untyped                                    ;
+; G3_MODE                       ; BYPASS            ; Untyped                                    ;
+; E0_MODE                       ; BYPASS            ; Untyped                                    ;
+; E1_MODE                       ; BYPASS            ; Untyped                                    ;
+; E2_MODE                       ; BYPASS            ; Untyped                                    ;
+; E3_MODE                       ; BYPASS            ; Untyped                                    ;
+; L0_PH                         ; 0                 ; Untyped                                    ;
+; L1_PH                         ; 0                 ; Untyped                                    ;
+; G0_PH                         ; 0                 ; Untyped                                    ;
+; G1_PH                         ; 0                 ; Untyped                                    ;
+; G2_PH                         ; 0                 ; Untyped                                    ;
+; G3_PH                         ; 0                 ; Untyped                                    ;
+; E0_PH                         ; 0                 ; Untyped                                    ;
+; E1_PH                         ; 0                 ; Untyped                                    ;
+; E2_PH                         ; 0                 ; Untyped                                    ;
+; E3_PH                         ; 0                 ; Untyped                                    ;
+; M_PH                          ; 0                 ; Untyped                                    ;
+; C1_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C2_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C3_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C4_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C5_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C6_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C7_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C8_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C9_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; CLK0_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK1_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK2_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK3_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK4_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK5_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK6_COUNTER                  ; E0                ; Untyped                                    ;
+; CLK7_COUNTER                  ; E1                ; Untyped                                    ;
+; CLK8_COUNTER                  ; E2                ; Untyped                                    ;
+; CLK9_COUNTER                  ; E3                ; Untyped                                    ;
+; L0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; L1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G2_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G3_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E2_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E3_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; M_TIME_DELAY                  ; 0                 ; Untyped                                    ;
+; N_TIME_DELAY                  ; 0                 ; Untyped                                    ;
+; EXTCLK3_COUNTER               ; E3                ; Untyped                                    ;
+; EXTCLK2_COUNTER               ; E2                ; Untyped                                    ;
+; EXTCLK1_COUNTER               ; E1                ; Untyped                                    ;
+; EXTCLK0_COUNTER               ; E0                ; Untyped                                    ;
+; ENABLE0_COUNTER               ; L0                ; Untyped                                    ;
+; ENABLE1_COUNTER               ; L0                ; Untyped                                    ;
+; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                                    ;
+; LOOP_FILTER_R                 ;  1.000000         ; Untyped                                    ;
+; LOOP_FILTER_C                 ; 5                 ; Untyped                                    ;
+; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped                                    ;
+; LOOP_FILTER_R_BITS            ; 9999              ; Untyped                                    ;
+; LOOP_FILTER_C_BITS            ; 9999              ; Untyped                                    ;
+; VCO_POST_SCALE                ; 0                 ; Untyped                                    ;
+; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; INTENDED_DEVICE_FAMILY        ; Cyclone III       ; Untyped                                    ;
+; PORT_CLKENA0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA2                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA3                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA4                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA5                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLK0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK2                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK3                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKBAD0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKBAD1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK0                     ; PORT_USED         ; Untyped                                    ;
+; PORT_CLK1                     ; PORT_USED         ; Untyped                                    ;
+; PORT_CLK2                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK3                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK4                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK5                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK6                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK7                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK8                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK9                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDATA                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDATAOUT              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDONE                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_ACTIVECLOCK              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKLOSS                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_INCLK1                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_INCLK0                   ; PORT_USED         ; Untyped                                    ;
+; PORT_FBIN                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PLLENA                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKSWITCH                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_ARESET                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PFDENA                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANCLK                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANACLR                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANREAD                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANWRITE                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_LOCKED                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CONFIGUPDATE             ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_PHASEDONE                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASESTEP                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASEUPDOWN              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANCLKENA               ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped                                    ;
+; M_TEST_SOURCE                 ; 5                 ; Untyped                                    ;
+; C0_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C1_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C2_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C3_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C4_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C5_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C6_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C7_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C8_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C9_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; CBXI_PARAMETER                ; altpll_9ee2       ; Untyped                                    ;
+; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped                                    ;
+; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped                                    ;
+; WIDTH_CLOCK                   ; 5                 ; Signed Integer                             ;
+; WIDTH_PHASECOUNTERSELECT      ; 4                 ; Untyped                                    ;
+; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped                                    ;
+; DEVICE_FAMILY                 ; Cyclone III       ; Untyped                                    ;
+; SCAN_CHAIN_MIF_FILE           ; UNUSED            ; Untyped                                    ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF               ; Untyped                                    ;
+; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                                 ;
+; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                               ;
+; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                               ;
+; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                             ;
++-------------------------------+-------------------+--------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7 ;
++----------------+-------+---------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                    ;
++----------------+-------+---------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                          ;
+; REF_PER        ; 1024  ; Signed Integer                                          ;
+; SC_CL          ; 3     ; Signed Integer                                          ;
+; SC_RCD         ; 3     ; Signed Integer                                          ;
+; SC_RRD         ; 7     ; Signed Integer                                          ;
+; SC_PM          ; 1     ; Signed Integer                                          ;
+; SC_BL          ; 1     ; Signed Integer                                          ;
+; SDR_BL         ; 111   ; Unsigned Binary                                         ;
+; SDR_BT         ; 0     ; Unsigned Binary                                         ;
+; SDR_CL         ; 011   ; Unsigned Binary                                         ;
++----------------+-------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1 ;
++----------------+-------+------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                               ;
++----------------+-------+------------------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                                     ;
+; REF_PER        ; 1024  ; Signed Integer                                                                     ;
+; SC_CL          ; 3     ; Signed Integer                                                                     ;
+; SC_RCD         ; 3     ; Signed Integer                                                                     ;
+; SC_RRD         ; 7     ; Signed Integer                                                                     ;
+; SC_PM          ; 1     ; Signed Integer                                                                     ;
+; SC_BL          ; 1     ; Signed Integer                                                                     ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                                    ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                                    ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                                    ;
++----------------+-------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1 ;
++----------------+-------+--------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                     ;
++----------------+-------+--------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                           ;
+; REF_PER        ; 1024  ; Signed Integer                                                           ;
+; SC_CL          ; 3     ; Signed Integer                                                           ;
+; SC_RCD         ; 3     ; Signed Integer                                                           ;
+; SC_RRD         ; 7     ; Signed Integer                                                           ;
+; SC_PM          ; 1     ; Signed Integer                                                           ;
+; SC_BL          ; 1     ; Signed Integer                                                           ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                          ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                          ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                          ;
++----------------+-------+--------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1 ;
++----------------+-------+----------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                             ;
++----------------+-------+----------------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                                   ;
+; REF_PER        ; 1024  ; Signed Integer                                                                   ;
+; SC_CL          ; 3     ; Signed Integer                                                                   ;
+; SC_RCD         ; 3     ; Signed Integer                                                                   ;
+; SC_RRD         ; 7     ; Signed Integer                                                                   ;
+; SC_PM          ; 1     ; Signed Integer                                                                   ;
+; SC_BL          ; 1     ; Signed Integer                                                                   ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                                  ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                                  ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                                  ;
++----------------+-------+----------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                    ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                 ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                              ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                            ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                            ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                          ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                          ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                          ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                          ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                 ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                 ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                 ;
+; USE_EAB                 ; ON          ; Untyped                                                                                 ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                 ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                 ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                 ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                 ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                 ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                 ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                 ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                 ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                 ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                 ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                    ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                 ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                              ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                            ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                            ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                          ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                          ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                          ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                          ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                 ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                 ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                 ;
+; USE_EAB                 ; ON          ; Untyped                                                                                 ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                 ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                 ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                 ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                 ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                 ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                 ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                 ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                 ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                 ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                 ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                   ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                             ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                           ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                           ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                         ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                         ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                         ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                         ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                ;
+; USE_EAB                 ; ON          ; Untyped                                                                                ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                   ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                             ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                           ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                           ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                         ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                         ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                         ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                         ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                ;
+; USE_EAB                 ; ON          ; Untyped                                                                                ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8 ;
++-----------------------+------------------+----------------------------------+
+; Parameter Name        ; Value            ; Type                             ;
++-----------------------+------------------+----------------------------------+
+; default_exposure      ; 0000011111000000 ; Unsigned Binary                  ;
+; exposure_change_value ; 0000000011001000 ; Unsigned Binary                  ;
+; CLK_Freq              ; 50000000         ; Signed Integer                   ;
+; I2C_Freq              ; 20000            ; Signed Integer                   ;
+; LUT_SIZE              ; 25               ; Signed Integer                   ;
++-----------------------+------------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------+
+; Parameter Settings for User Entity Instance: ps2:inst6 ;
++----------------+-----------+---------------------------+
+; Parameter Name ; Value     ; Type                      ;
++----------------+-----------+---------------------------+
+; enable_byte    ; 011110100 ; Unsigned Binary           ;
+; listen         ; 00        ; Unsigned Binary           ;
+; pullclk        ; 01        ; Unsigned Binary           ;
+; pulldat        ; 10        ; Unsigned Binary           ;
+; trans          ; 11        ; Unsigned Binary           ;
++----------------+-----------+---------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mux:inst10|LPM_MUX:LPM_MUX_component ;
++------------------------+-------------+------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                           ;
++------------------------+-------------+------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                     ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                   ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                   ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                 ;
+; LPM_WIDTH              ; 30          ; Signed Integer                                 ;
+; LPM_SIZE               ; 4           ; Signed Integer                                 ;
+; LPM_WIDTHS             ; 2           ; Signed Integer                                 ;
+; LPM_PIPELINE           ; 0           ; Signed Integer                                 ;
+; CBXI_PARAMETER         ; mux_u7e     ; Untyped                                        ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                        ;
++------------------------+-------------+------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:vga_xy_rsc_mgc_in_wire ;
++----------------+-------+-------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                            ;
++----------------+-------+-------------------------------------------------------------------------------------------------+
+; rscid          ; 1     ; Signed Integer                                                                                  ;
+; width          ; 20    ; Signed Integer                                                                                  ;
++----------------+-------+-------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:mouse_xy_rsc_mgc_in_wire ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                              ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+; rscid          ; 2     ; Signed Integer                                                                                    ;
+; width          ; 20    ; Signed Integer                                                                                    ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:cursor_size_rsc_mgc_in_wire ;
++----------------+-------+------------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                                 ;
++----------------+-------+------------------------------------------------------------------------------------------------------+
+; rscid          ; 3     ; Signed Integer                                                                                       ;
+; width          ; 8     ; Signed Integer                                                                                       ;
++----------------+-------+------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:video_in_rsc_mgc_in_wire ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                              ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+; rscid          ; 4     ; Signed Integer                                                                                    ;
+; width          ; 30    ; Signed Integer                                                                                    ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg ;
++----------------+-------+----------------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                                     ;
++----------------+-------+----------------------------------------------------------------------------------------------------------+
+; rscid          ; 5     ; Signed Integer                                                                                           ;
+; width          ; 30    ; Signed Integer                                                                                           ;
++----------------+-------+----------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: sobel:inst1|mgc_in_wire:vin_rsc_mgc_in_wire ;
++----------------+-------+-----------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                            ;
++----------------+-------+-----------------------------------------------------------------+
+; rscid          ; 1     ; Signed Integer                                                  ;
+; width          ; 90    ; Signed Integer                                                  ;
++----------------+-------+-----------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: sobel:inst1|mgc_out_stdreg:vout_rsc_mgc_out_stdreg ;
++----------------+-------+------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                   ;
++----------------+-------+------------------------------------------------------------------------+
+; rscid          ; 2     ; Signed Integer                                                         ;
+; width          ; 30    ; Signed Integer                                                         ;
++----------------+-------+------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altshift_taps:fifo_inst2 ;
++----------------+----------------+-------------------------------------+
+; Parameter Name ; Value          ; Type                                ;
++----------------+----------------+-------------------------------------+
+; WIDTH_BYTEENA  ; 1              ; Untyped                             ;
+; NUMBER_OF_TAPS ; 3              ; Untyped                             ;
+; TAP_DISTANCE   ; 800            ; Untyped                             ;
+; WIDTH          ; 30             ; Untyped                             ;
+; POWER_UP_STATE ; CLEARED        ; Untyped                             ;
+; CBXI_PARAMETER ; shift_taps_jpm ; Untyped                             ;
++----------------+----------------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0 ;
++------------------------------------------------+-------------+-----------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                    ;
++------------------------------------------------+-------------+-----------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                              ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                            ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                            ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                          ;
+; LPM_WIDTHA                                     ; 2           ; Untyped                                 ;
+; LPM_WIDTHB                                     ; 9           ; Untyped                                 ;
+; LPM_WIDTHP                                     ; 11          ; Untyped                                 ;
+; LPM_WIDTHR                                     ; 11          ; Untyped                                 ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                 ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                 ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                 ;
+; LATENCY                                        ; 0           ; Untyped                                 ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                 ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                 ;
+; USE_EAB                                        ; OFF         ; Untyped                                 ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                 ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                 ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                 ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                     ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                 ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                 ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                 ;
++------------------------------------------------+-------------+-----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1 ;
++------------------------------------------------+-------------+-----------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                    ;
++------------------------------------------------+-------------+-----------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                              ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                            ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                            ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                          ;
+; LPM_WIDTHA                                     ; 3           ; Untyped                                 ;
+; LPM_WIDTHB                                     ; 6           ; Untyped                                 ;
+; LPM_WIDTHP                                     ; 9           ; Untyped                                 ;
+; LPM_WIDTHR                                     ; 9           ; Untyped                                 ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                 ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                 ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                 ;
+; LATENCY                                        ; 0           ; Untyped                                 ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                 ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                 ;
+; USE_EAB                                        ; OFF         ; Untyped                                 ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                 ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                 ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                 ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                     ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                 ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                 ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                 ;
++------------------------------------------------+-------------+-----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7 ;
++------------------------------------------------+-------------+-----------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                    ;
++------------------------------------------------+-------------+-----------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                              ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                            ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                            ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                          ;
+; LPM_WIDTHA                                     ; 2           ; Untyped                                 ;
+; LPM_WIDTHB                                     ; 13          ; Untyped                                 ;
+; LPM_WIDTHP                                     ; 15          ; Untyped                                 ;
+; LPM_WIDTHR                                     ; 15          ; Untyped                                 ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                 ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                 ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                 ;
+; LATENCY                                        ; 0           ; Untyped                                 ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                 ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                 ;
+; USE_EAB                                        ; OFF         ; Untyped                                 ;
+; MAXIMIZE_SPEED                                 ; 6           ; Untyped                                 ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                 ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                 ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                     ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                 ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                 ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                 ;
++------------------------------------------------+-------------+-----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5 ;
++------------------------------------------------+-------------+-----------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                    ;
++------------------------------------------------+-------------+-----------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                              ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                            ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                            ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                          ;
+; LPM_WIDTHA                                     ; 4           ; Untyped                                 ;
+; LPM_WIDTHB                                     ; 9           ; Untyped                                 ;
+; LPM_WIDTHP                                     ; 13          ; Untyped                                 ;
+; LPM_WIDTHR                                     ; 13          ; Untyped                                 ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                 ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                 ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                 ;
+; LATENCY                                        ; 0           ; Untyped                                 ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                 ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                 ;
+; USE_EAB                                        ; OFF         ; Untyped                                 ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                 ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                 ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                 ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                     ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                 ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                 ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                 ;
++------------------------------------------------+-------------+-----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2 ;
++------------------------------------------------+-------------+-----------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                    ;
++------------------------------------------------+-------------+-----------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                              ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                            ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                            ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                          ;
+; LPM_WIDTHA                                     ; 2           ; Untyped                                 ;
+; LPM_WIDTHB                                     ; 14          ; Untyped                                 ;
+; LPM_WIDTHP                                     ; 16          ; Untyped                                 ;
+; LPM_WIDTHR                                     ; 16          ; Untyped                                 ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                 ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                 ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                 ;
+; LATENCY                                        ; 0           ; Untyped                                 ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                 ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                 ;
+; USE_EAB                                        ; OFF         ; Untyped                                 ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                 ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                 ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                 ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                     ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                 ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                 ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                 ;
++------------------------------------------------+-------------+-----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6 ;
++------------------------------------------------+-------------+-----------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                    ;
++------------------------------------------------+-------------+-----------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                              ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                            ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                            ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                          ;
+; LPM_WIDTHA                                     ; 3           ; Untyped                                 ;
+; LPM_WIDTHB                                     ; 7           ; Untyped                                 ;
+; LPM_WIDTHP                                     ; 10          ; Untyped                                 ;
+; LPM_WIDTHR                                     ; 10          ; Untyped                                 ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                 ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                 ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                 ;
+; LATENCY                                        ; 0           ; Untyped                                 ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                 ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                 ;
+; USE_EAB                                        ; OFF         ; Untyped                                 ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                 ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                 ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                 ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                     ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                 ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                 ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                 ;
++------------------------------------------------+-------------+-----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult3 ;
++------------------------------------------------+-------------+-----------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                    ;
++------------------------------------------------+-------------+-----------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                              ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                            ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                            ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                          ;
+; LPM_WIDTHA                                     ; 4           ; Untyped                                 ;
+; LPM_WIDTHB                                     ; 5           ; Untyped                                 ;
+; LPM_WIDTHP                                     ; 9           ; Untyped                                 ;
+; LPM_WIDTHR                                     ; 9           ; Untyped                                 ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                 ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                 ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                 ;
+; LATENCY                                        ; 0           ; Untyped                                 ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                 ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                 ;
+; USE_EAB                                        ; OFF         ; Untyped                                 ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                 ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                 ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                 ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                     ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                 ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                 ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                 ;
++------------------------------------------------+-------------+-----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4 ;
++------------------------------------------------+-------------+-----------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                    ;
++------------------------------------------------+-------------+-----------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                              ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                            ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                            ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                          ;
+; LPM_WIDTHA                                     ; 4           ; Untyped                                 ;
+; LPM_WIDTHB                                     ; 7           ; Untyped                                 ;
+; LPM_WIDTHP                                     ; 11          ; Untyped                                 ;
+; LPM_WIDTHR                                     ; 11          ; Untyped                                 ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                 ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                 ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                 ;
+; LATENCY                                        ; 0           ; Untyped                                 ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                 ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                 ;
+; USE_EAB                                        ; OFF         ; Untyped                                 ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                 ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                 ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                 ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                     ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                 ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                 ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                 ;
++------------------------------------------------+-------------+-----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult8 ;
++------------------------------------------------+-------------+-----------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                    ;
++------------------------------------------------+-------------+-----------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                              ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                            ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                            ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                          ;
+; LPM_WIDTHA                                     ; 4           ; Untyped                                 ;
+; LPM_WIDTHB                                     ; 5           ; Untyped                                 ;
+; LPM_WIDTHP                                     ; 9           ; Untyped                                 ;
+; LPM_WIDTHR                                     ; 9           ; Untyped                                 ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                 ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                 ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                 ;
+; LATENCY                                        ; 0           ; Untyped                                 ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                 ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                 ;
+; USE_EAB                                        ; OFF         ; Untyped                                 ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                 ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                 ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                 ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                     ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                 ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                 ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                 ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                 ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                 ;
++------------------------------------------------+-------------+-----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; altshift_taps Parameter Settings by Entity Instance                                                       ;
++----------------------------+------------------------------------------------------------------------------+
+; Name                       ; Value                                                                        ;
++----------------------------+------------------------------------------------------------------------------+
+; Number of entity instances ; 2                                                                            ;
+; Entity Instance            ; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
+;     -- NUMBER_OF_TAPS      ; 2                                                                            ;
+;     -- TAP_DISTANCE        ; 1280                                                                         ;
+;     -- WIDTH               ; 12                                                                           ;
+; Entity Instance            ; altshift_taps:fifo_inst2                                                     ;
+;     -- NUMBER_OF_TAPS      ; 3                                                                            ;
+;     -- TAP_DISTANCE        ; 800                                                                          ;
+;     -- WIDTH               ; 30                                                                           ;
++----------------------------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------+
+; altpll Parameter Settings by Entity Instance                                      ;
++-------------------------------+---------------------------------------------------+
+; Name                          ; Value                                             ;
++-------------------------------+---------------------------------------------------+
+; Number of entity instances    ; 1                                                 ;
+; Entity Instance               ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ;
+;     -- OPERATION_MODE         ; NORMAL                                            ;
+;     -- PLL_TYPE               ; AUTO                                              ;
+;     -- PRIMARY_CLOCK          ; INCLK0                                            ;
+;     -- INCLK0_INPUT_FREQUENCY ; 20000                                             ;
+;     -- INCLK1_INPUT_FREQUENCY ; 0                                                 ;
+;     -- VCO_MULTIPLY_BY        ; 0                                                 ;
+;     -- VCO_DIVIDE_BY          ; 0                                                 ;
++-------------------------------+---------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; dcfifo Parameter Settings by Entity Instance                                                                    ;
++----------------------------+------------------------------------------------------------------------------------+
+; Name                       ; Value                                                                              ;
++----------------------------+------------------------------------------------------------------------------------+
+; Number of entity instances ; 4                                                                                  ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component  ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component  ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
++----------------------------+------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------+
+; lpm_mult Parameter Settings by Entity Instance                                                ;
++---------------------------------------+-------------------------------------------------------+
+; Name                                  ; Value                                                 ;
++---------------------------------------+-------------------------------------------------------+
+; Number of entity instances            ; 9                                                     ;
+; Entity Instance                       ; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0 ;
+;     -- LPM_WIDTHA                     ; 2                                                     ;
+;     -- LPM_WIDTHB                     ; 9                                                     ;
+;     -- LPM_WIDTHP                     ; 11                                                    ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                              ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                    ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                   ;
+;     -- USE_EAB                        ; OFF                                                   ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                  ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                    ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                    ;
+; Entity Instance                       ; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1 ;
+;     -- LPM_WIDTHA                     ; 3                                                     ;
+;     -- LPM_WIDTHB                     ; 6                                                     ;
+;     -- LPM_WIDTHP                     ; 9                                                     ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                              ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                    ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                   ;
+;     -- USE_EAB                        ; OFF                                                   ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                  ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                    ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                    ;
+; Entity Instance                       ; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7 ;
+;     -- LPM_WIDTHA                     ; 2                                                     ;
+;     -- LPM_WIDTHB                     ; 13                                                    ;
+;     -- LPM_WIDTHP                     ; 15                                                    ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                              ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                    ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                   ;
+;     -- USE_EAB                        ; OFF                                                   ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                  ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                    ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                    ;
+; Entity Instance                       ; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5 ;
+;     -- LPM_WIDTHA                     ; 4                                                     ;
+;     -- LPM_WIDTHB                     ; 9                                                     ;
+;     -- LPM_WIDTHP                     ; 13                                                    ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                              ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                    ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                   ;
+;     -- USE_EAB                        ; OFF                                                   ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                  ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                    ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                    ;
+; Entity Instance                       ; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2 ;
+;     -- LPM_WIDTHA                     ; 2                                                     ;
+;     -- LPM_WIDTHB                     ; 14                                                    ;
+;     -- LPM_WIDTHP                     ; 16                                                    ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                              ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                    ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                   ;
+;     -- USE_EAB                        ; OFF                                                   ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                  ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                    ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                    ;
+; Entity Instance                       ; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6 ;
+;     -- LPM_WIDTHA                     ; 3                                                     ;
+;     -- LPM_WIDTHB                     ; 7                                                     ;
+;     -- LPM_WIDTHP                     ; 10                                                    ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                              ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                    ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                   ;
+;     -- USE_EAB                        ; OFF                                                   ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                  ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                    ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                    ;
+; Entity Instance                       ; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult3 ;
+;     -- LPM_WIDTHA                     ; 4                                                     ;
+;     -- LPM_WIDTHB                     ; 5                                                     ;
+;     -- LPM_WIDTHP                     ; 9                                                     ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                              ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                    ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                   ;
+;     -- USE_EAB                        ; OFF                                                   ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                  ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                    ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                    ;
+; Entity Instance                       ; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4 ;
+;     -- LPM_WIDTHA                     ; 4                                                     ;
+;     -- LPM_WIDTHB                     ; 7                                                     ;
+;     -- LPM_WIDTHP                     ; 11                                                    ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                              ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                    ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                   ;
+;     -- USE_EAB                        ; OFF                                                   ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                  ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                    ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                    ;
+; Entity Instance                       ; sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult8 ;
+;     -- LPM_WIDTHA                     ; 4                                                     ;
+;     -- LPM_WIDTHB                     ; 5                                                     ;
+;     -- LPM_WIDTHP                     ; 9                                                     ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                              ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                    ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                   ;
+;     -- USE_EAB                        ; OFF                                                   ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                  ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                    ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                    ;
++---------------------------------------+-------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8"                                                                                                                   ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port       ; Type  ; Severity ; Details                                                                                                                                      ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; iUART_CTRL ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2"                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1"                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2"                                                 ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"                                                 ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"                       ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; DM   ; Input  ; Info     ; Stuck at GND                                                                        ;
+; DQM  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"                                                                                 ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port     ; Type  ; Severity ; Details                                                                                                                                      ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; CMD      ; Input ; Warning  ; Input port expression (2 bits) is smaller than the input port (3 bits) it drives.  Extra input bit(s) "CMD[2..2]" will be connected to GND.  ;
+; INIT_ACK ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7"                                                                                                                                                               ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port                 ; Type   ; Severity ; Details                                                                                                                                                                            ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; RESET_N              ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_DATA[15]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_ADDR             ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR1_ADDR[22..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR1_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[22..19] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_DATA[15]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR             ; Input  ; Warning  ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives.  Extra input bit(s) "WR2_ADDR[22..22]" will be connected to GND.                               ;
+; WR2_ADDR[19..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR[22]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR[21]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR2_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[22..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[20]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[19]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_DATA[15]         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; RD1_ADDR             ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD1_ADDR[22..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD1_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[22..19] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_DATA[15]         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; RD2_ADDR             ; Input  ; Warning  ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives.  Extra input bit(s) "RD2_ADDR[22..22]" will be connected to GND.                               ;
+; RD2_ADDR[19..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_ADDR[22]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_ADDR[21]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD2_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[22..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[20]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[19]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; CS_N                 ; Output ; Warning  ; Output or bidir port (2 bits) is wider than the port expression (1 bits) it drives; bit(s) "CS_N[1..1]" have no fanouts                                                            ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5" ;
++-------+--------+----------+----------------------------+
+; Port  ; Type   ; Severity ; Details                    ;
++-------+--------+----------+----------------------------+
+; oSEG4 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG5 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG6 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG7 ; Output ; Info     ; Explicitly unconnected     ;
++-------+--------+----------+----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"                                                                      ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port     ; Type   ; Severity ; Details                                                                                                  ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; shiftout ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4"                                                                                                                                                                   ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port         ; Type   ; Severity ; Details                                                                                                                                                                            ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; oRed[1..0]   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; oGreen[1..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; oBlue[1..0]  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; iX_Cont      ; Input  ; Warning  ; Input port expression (16 bits) is wider than the input port (11 bits) it drives.  The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; iY_Cont      ; Input  ; Warning  ; Input port expression (16 bits) is wider than the input port (11 bits) it drives.  The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3"                                                                   ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port            ; Type   ; Severity ; Details                                                                             ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+; oX_Cont[15..11] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; oY_Cont[15..11] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1"                                                                                ;
++------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port       ; Type   ; Severity ; Details                                                                                                  ;
++------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; oVGA_SYNC  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; oVGA_BLANK ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; oVGA_CLOCK ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:08     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 08 16:23:15 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 2 design units, including 2 entities, in source file //icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel quartus/sobel.v
+    Info (12023): Found entity 1: sobel_core
+    Info (12023): Found entity 2: sobel
+Info (12021): Found 1 design units, including 1 entities, in source file v/ps2.v
+    Info (12023): Found entity 1: ps2
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/command.v
+    Info (12023): Found entity 1: command
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/control_interface.v
+    Info (12023): Found entity 1: control_interface
+Warning (10229): Verilog HDL Expression warning at sdr_data_path.v(68): truncated literal to match 1 bits
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdr_data_path.v
+    Info (12023): Found entity 1: sdr_data_path
+Warning (10238): Verilog Module Declaration warning at Sdram_Control_4Port.v(90): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "Sdram_Control_4Port"
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_control_4port.v
+    Info (12023): Found entity 1: Sdram_Control_4Port
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_fifo.v
+    Info (12023): Found entity 1: Sdram_FIFO
+Warning (12019): Can't analyze file -- file V/async_receiver.v is missing
+Info (12021): Found 1 design units, including 1 entities, in source file v/ccd_capture.v
+    Info (12023): Found entity 1: CCD_Capture
+Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_ccd_config.v
+    Info (12023): Found entity 1: I2C_CCD_Config
+Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_controller.v
+    Info (12023): Found entity 1: I2C_Controller
+Info (12021): Found 1 design units, including 1 entities, in source file v/line_buffer.v
+    Info (12023): Found entity 1: Line_Buffer
+Info (12021): Found 1 design units, including 1 entities, in source file v/raw2rgb.v
+    Info (12023): Found entity 1: RAW2RGB
+Info (12021): Found 1 design units, including 1 entities, in source file v/reset_delay.v
+    Info (12023): Found entity 1: Reset_Delay
+Info (12021): Found 1 design units, including 1 entities, in source file v/sdram_pll.v
+    Info (12023): Found entity 1: sdram_pll
+Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut.v
+    Info (12023): Found entity 1: SEG7_LUT
+Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut_8.v
+    Info (12023): Found entity 1: SEG7_LUT_8
+Info (12021): Found 1 design units, including 1 entities, in source file v/vga_controller.v
+    Info (12023): Found entity 1: VGA_Controller
+Info (12021): Found 1 design units, including 1 entities, in source file de0_d5m.v
+    Info (12023): Found entity 1: DE0_D5M
+Info (12021): Found 1 design units, including 1 entities, in source file v/top_de0_camera_mouse.bdf
+    Info (12023): Found entity 1: TOP_DE0_CAMERA_MOUSE
+Info (12021): Found 2 design units, including 1 entities, in source file vga_mux.vhd
+    Info (12022): Found design unit 1: vga_mux-SYN
+    Info (12023): Found entity 1: vga_mux
+Info (12021): Found 7 design units, including 7 entities, in source file catapult_ip/mouse/rtl_mgc_ioport_v2001.v
+    Info (12023): Found entity 1: mgc_out_reg_pos
+    Info (12023): Found entity 2: mgc_out_reg_neg
+    Info (12023): Found entity 3: mgc_out_reg
+    Info (12023): Found entity 4: mgc_out_buf_wait
+    Info (12023): Found entity 5: mgc_out_fifo_wait
+    Info (12023): Found entity 6: mgc_out_fifo_wait_core
+    Info (12023): Found entity 7: mgc_pipe
+Info (12021): Found 20 design units, including 20 entities, in source file catapult_ip/mouse/rtl_mgc_ioport.v
+    Info (12023): Found entity 1: mgc_in_wire
+    Info (12023): Found entity 2: mgc_in_wire_en
+    Info (12023): Found entity 3: mgc_in_wire_wait
+    Info (12023): Found entity 4: mgc_chan_in
+    Info (12023): Found entity 5: mgc_out_stdreg
+    Info (12023): Found entity 6: mgc_out_stdreg_en
+    Info (12023): Found entity 7: mgc_out_stdreg_wait
+    Info (12023): Found entity 8: mgc_out_prereg_en
+    Info (12023): Found entity 9: mgc_inout_stdreg_en
+    Info (12023): Found entity 10: hid_tribuf
+    Info (12023): Found entity 11: mgc_inout_stdreg_wait
+    Info (12023): Found entity 12: mgc_inout_buf_wait
+    Info (12023): Found entity 13: mgc_inout_fifo_wait
+    Info (12023): Found entity 14: mgc_io_sync
+    Info (12023): Found entity 15: mgc_bsync_rdy
+    Info (12023): Found entity 16: mgc_bsync_vld
+    Info (12023): Found entity 17: mgc_bsync_rv
+    Info (12023): Found entity 18: mgc_sync
+    Info (12023): Found entity 19: funccall_inout
+    Info (12023): Found entity 20: modulario_en_in
+Info (12021): Found 2 design units, including 2 entities, in source file catapult_ip/mouse/rtl.v
+    Info (12023): Found entity 1: vga_mouse_square_core
+    Info (12023): Found entity 2: vga_mouse_square
+Info (12127): Elaborating entity "TOP_DE0_CAMERA_MOUSE" for the top level hierarchy
+Warning (275002): No superset bus at connection
+Info (12128): Elaborating entity "DE0_D5M" for hierarchy "DE0_D5M:inst"
+Critical Warning (10169): Verilog HDL warning at DE0_D5M.v(118): the port and data declarations for array port "VGA_R" do not specify the same range for each dimension
+Warning (10359): HDL warning at DE0_D5M.v(166): see declaration for object "VGA_R"
+Critical Warning (10169): Verilog HDL warning at DE0_D5M.v(119): the port and data declarations for array port "VGA_G" do not specify the same range for each dimension
+Warning (10359): HDL warning at DE0_D5M.v(167): see declaration for object "VGA_G"
+Critical Warning (10169): Verilog HDL warning at DE0_D5M.v(120): the port and data declarations for array port "VGA_B" do not specify the same range for each dimension
+Warning (10359): HDL warning at DE0_D5M.v(168): see declaration for object "VGA_B"
+Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(197): truncated value with size 16 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(202): truncated value with size 32 to match size of target (2)
+Warning (10034): Output port "GPIO_1_CLKOUT[1]" at DE0_D5M.v(128) has no driver
+Info (12128): Elaborating entity "VGA_Controller" for hierarchy "DE0_D5M:inst|VGA_Controller:u1"
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(70): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(73): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(76): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(115): truncated value with size 32 to match size of target (12)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(146): truncated value with size 32 to match size of target (12)
+Info (12128): Elaborating entity "Reset_Delay" for hierarchy "DE0_D5M:inst|Reset_Delay:u2"
+Info (12128): Elaborating entity "CCD_Capture" for hierarchy "DE0_D5M:inst|CCD_Capture:u3"
+Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(162): object "ifval_fedge" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(163): object "y_cnt_d" assigned a value but never read
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(123): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(127): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(183): truncated value with size 32 to match size of target (1)
+Info (12128): Elaborating entity "RAW2RGB" for hierarchy "DE0_D5M:inst|RAW2RGB:u4"
+Info (12128): Elaborating entity "Line_Buffer" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"
+Info (12128): Elaborating entity "altshift_taps" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component" with the following parameter:
+    Info (12134): Parameter "lpm_type" = "altshift_taps"
+    Info (12134): Parameter "number_of_taps" = "2"
+    Info (12134): Parameter "tap_distance" = "1280"
+    Info (12134): Parameter "width" = "12"
+Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_rnn.tdf
+    Info (12023): Found entity 1: shift_taps_rnn
+Info (12128): Elaborating entity "shift_taps_rnn" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_lp81.tdf
+    Info (12023): Found entity 1: altsyncram_lp81
+Info (12128): Elaborating entity "altsyncram_lp81" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_cuf.tdf
+    Info (12023): Found entity 1: cntr_cuf
+Info (12128): Elaborating entity "cntr_cuf" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_vgc.tdf
+    Info (12023): Found entity 1: cmpr_vgc
+Info (12128): Elaborating entity "cmpr_vgc" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4"
+Info (12128): Elaborating entity "SEG7_LUT_8" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5"
+Info (12128): Elaborating entity "SEG7_LUT" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0"
+Info (12128): Elaborating entity "sdram_pll" for hierarchy "DE0_D5M:inst|sdram_pll:u6"
+Info (12128): Elaborating entity "altpll" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component" with the following parameter:
+    Info (12134): Parameter "bandwidth_type" = "AUTO"
+    Info (12134): Parameter "clk0_divide_by" = "2"
+    Info (12134): Parameter "clk0_duty_cycle" = "50"
+    Info (12134): Parameter "clk0_multiply_by" = "5"
+    Info (12134): Parameter "clk0_phase_shift" = "0"
+    Info (12134): Parameter "clk1_divide_by" = "2"
+    Info (12134): Parameter "clk1_duty_cycle" = "50"
+    Info (12134): Parameter "clk1_multiply_by" = "5"
+    Info (12134): Parameter "clk1_phase_shift" = "-2600"
+    Info (12134): Parameter "compensate_clock" = "CLK0"
+    Info (12134): Parameter "inclk0_input_frequency" = "20000"
+    Info (12134): Parameter "intended_device_family" = "Cyclone III"
+    Info (12134): Parameter "lpm_type" = "altpll"
+    Info (12134): Parameter "operation_mode" = "NORMAL"
+    Info (12134): Parameter "pll_type" = "AUTO"
+    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
+    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
+    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
+    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
+    Info (12134): Parameter "port_inclk0" = "PORT_USED"
+    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
+    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
+    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk0" = "PORT_USED"
+    Info (12134): Parameter "port_clk1" = "PORT_USED"
+    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
+    Info (12134): Parameter "width_clock" = "5"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_9ee2.tdf
+    Info (12023): Found entity 1: altpll_9ee2
+Info (12128): Elaborating entity "altpll_9ee2" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated"
+Info (12128): Elaborating entity "Sdram_Control_4Port" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7"
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(385): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(431): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(432): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(433): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(434): truncated value with size 32 to match size of target (23)
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (12128): Elaborating entity "control_interface" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"
+Warning (10230): Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at control_interface.v(167): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at control_interface.v(192): truncated value with size 32 to match size of target (16)
+Info (12128): Elaborating entity "command" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe_shift", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe1", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe2", which holds its previous value in one or more paths through the always construct
+Info (12128): Elaborating entity "sdr_data_path" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"
+Warning (10230): Verilog HDL assignment warning at sdr_data_path.v(68): truncated value with size 32 to match size of target (2)
+Info (12128): Elaborating entity "Sdram_FIFO" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"
+Info (12128): Elaborating entity "dcfifo" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component" with the following parameter:
+    Info (12134): Parameter "add_ram_output_register" = "OFF"
+    Info (12134): Parameter "clocks_are_synchronized" = "FALSE"
+    Info (12134): Parameter "intended_device_family" = "Cyclone"
+    Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=M4K"
+    Info (12134): Parameter "lpm_numwords" = "512"
+    Info (12134): Parameter "lpm_showahead" = "OFF"
+    Info (12134): Parameter "lpm_type" = "dcfifo"
+    Info (12134): Parameter "lpm_width" = "16"
+    Info (12134): Parameter "lpm_widthu" = "9"
+    Info (12134): Parameter "overflow_checking" = "ON"
+    Info (12134): Parameter "underflow_checking" = "ON"
+    Info (12134): Parameter "use_eab" = "ON"
+Warning (287001): Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2
+Warning (287001): Assertion warning: Device family Cyclone III does not have M4K blocks -- using available memory blocks
+Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_v5o1.tdf
+    Info (12023): Found entity 1: dcfifo_v5o1
+Info (12128): Elaborating entity "dcfifo_v5o1" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf
+    Info (12023): Found entity 1: a_gray2bin_tgb
+Info (12128): Elaborating entity "a_gray2bin_tgb" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf
+    Info (12023): Found entity 1: a_graycounter_s57
+Info (12128): Elaborating entity "a_graycounter_s57" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf
+    Info (12023): Found entity 1: a_graycounter_ojc
+Info (12128): Elaborating entity "a_graycounter_ojc" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_de51.tdf
+    Info (12023): Found entity 1: altsyncram_de51
+Info (12128): Elaborating entity "altsyncram_de51" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf
+    Info (12023): Found entity 1: dffpipe_oe9
+Info (12128): Elaborating entity "dffpipe_oe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_qld.tdf
+    Info (12023): Found entity 1: alt_synch_pipe_qld
+Info (12128): Elaborating entity "alt_synch_pipe_qld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf
+    Info (12023): Found entity 1: dffpipe_pe9
+Info (12128): Elaborating entity "dffpipe_pe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13"
+Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf
+    Info (12023): Found entity 1: alt_synch_pipe_rld
+Info (12128): Elaborating entity "alt_synch_pipe_rld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf
+    Info (12023): Found entity 1: dffpipe_qe9
+Info (12128): Elaborating entity "dffpipe_qe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_e66.tdf
+    Info (12023): Found entity 1: cmpr_e66
+Info (12128): Elaborating entity "cmpr_e66" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp"
+Info (12128): Elaborating entity "I2C_CCD_Config" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8"
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(126): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(127): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(160): truncated value with size 32 to match size of target (25)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(165): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(190): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(240): truncated value with size 32 to match size of target (6)
+Info (12128): Elaborating entity "I2C_Controller" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(70): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(69): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(82): truncated value with size 32 to match size of target (7)
+Info (12128): Elaborating entity "ps2" for hierarchy "ps2:inst6"
+Warning (10230): Verilog HDL assignment warning at ps2.v(120): truncated value with size 32 to match size of target (9)
+Warning (10230): Verilog HDL assignment warning at ps2.v(188): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at ps2.v(195): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at ps2.v(201): truncated value with size 32 to match size of target (6)
+Warning (10230): Verilog HDL assignment warning at ps2.v(229): truncated value with size 32 to match size of target (4)
+Warning (10230): Verilog HDL assignment warning at ps2.v(245): truncated value with size 32 to match size of target (4)
+Info (12128): Elaborating entity "vga_mux" for hierarchy "vga_mux:inst10"
+Info (12128): Elaborating entity "LPM_MUX" for hierarchy "vga_mux:inst10|LPM_MUX:LPM_MUX_component"
+Info (12130): Elaborated megafunction instantiation "vga_mux:inst10|LPM_MUX:LPM_MUX_component"
+Info (12133): Instantiated megafunction "vga_mux:inst10|LPM_MUX:LPM_MUX_component" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTH" = "30"
+    Info (12134): Parameter "LPM_SIZE" = "4"
+    Info (12134): Parameter "LPM_WIDTHS" = "2"
+    Info (12134): Parameter "LPM_PIPELINE" = "0"
+    Info (12134): Parameter "LPM_TYPE" = "LPM_MUX"
+    Info (12134): Parameter "LPM_HINT" = "UNUSED"
+Info (12021): Found 1 design units, including 1 entities, in source file db/mux_u7e.tdf
+    Info (12023): Found entity 1: mux_u7e
+Info (12128): Elaborating entity "mux_u7e" for hierarchy "vga_mux:inst10|LPM_MUX:LPM_MUX_component|mux_u7e:auto_generated"
+Info (12128): Elaborating entity "vga_mouse_square" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:vga_xy_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:mouse_xy_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:cursor_size_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:video_in_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_out_stdreg" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg"
+Info (12128): Elaborating entity "vga_mouse_square_core" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst"
+Info (12128): Elaborating entity "sobel" for hierarchy "sobel:inst1"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "sobel:inst1|mgc_in_wire:vin_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_out_stdreg" for hierarchy "sobel:inst1|mgc_out_stdreg:vout_rsc_mgc_out_stdreg"
+Info (12128): Elaborating entity "sobel_core" for hierarchy "sobel:inst1|sobel_core:sobel_core_inst"
+Info (12128): Elaborating entity "altshift_taps" for hierarchy "altshift_taps:fifo_inst2"
+Info (12130): Elaborated megafunction instantiation "altshift_taps:fifo_inst2"
+Info (12133): Instantiated megafunction "altshift_taps:fifo_inst2" with the following parameter:
+    Info (12134): Parameter "NUMBER_OF_TAPS" = "3"
+    Info (12134): Parameter "TAP_DISTANCE" = "800"
+    Info (12134): Parameter "WIDTH" = "30"
+Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_jpm.tdf
+    Info (12023): Found entity 1: shift_taps_jpm
+Info (12128): Elaborating entity "shift_taps_jpm" for hierarchy "altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_5n81.tdf
+    Info (12023): Found entity 1: altsyncram_5n81
+Info (12128): Elaborating entity "altsyncram_5n81" for hierarchy "altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1tf.tdf
+    Info (12023): Found entity 1: cntr_1tf
+Info (12128): Elaborating entity "cntr_1tf" for hierarchy "altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_ugc.tdf
+    Info (12023): Found entity 1: cmpr_ugc
+Info (12128): Elaborating entity "cmpr_ugc" for hierarchy "altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|cmpr_ugc:cmpr4"
+Warning (14284): Synthesized away the following node(s):
+    Warning (14285): Synthesized away the following RAM node(s):
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]"
+Info (278001): Inferred 9 megafunctions from design logic
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel:inst1|sobel_core:sobel_core_inst|Mult0"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel:inst1|sobel_core:sobel_core_inst|Mult1"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel:inst1|sobel_core:sobel_core_inst|Mult7"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel:inst1|sobel_core:sobel_core_inst|Mult5"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel:inst1|sobel_core:sobel_core_inst|Mult2"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel:inst1|sobel_core:sobel_core_inst|Mult6"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel:inst1|sobel_core:sobel_core_inst|Mult3"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel:inst1|sobel_core:sobel_core_inst|Mult4"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "sobel:inst1|sobel_core:sobel_core_inst|Mult8"
+Info (12130): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0"
+Info (12133): Instantiated megafunction "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "2"
+    Info (12134): Parameter "LPM_WIDTHB" = "9"
+    Info (12134): Parameter "LPM_WIDTHP" = "11"
+    Info (12134): Parameter "LPM_WIDTHR" = "11"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0|multcore:mult_core", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0|altshift:external_latency_ffs", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult0"
+Info (12130): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1"
+Info (12133): Instantiated megafunction "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "3"
+    Info (12134): Parameter "LPM_WIDTHB" = "6"
+    Info (12134): Parameter "LPM_WIDTHP" = "9"
+    Info (12134): Parameter "LPM_WIDTHR" = "9"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1|multcore:mult_core", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1|altshift:external_latency_ffs", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult1"
+Info (12130): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7"
+Info (12133): Instantiated megafunction "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "2"
+    Info (12134): Parameter "LPM_WIDTHB" = "13"
+    Info (12134): Parameter "LPM_WIDTHP" = "15"
+    Info (12134): Parameter "LPM_WIDTHR" = "15"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "6"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7|multcore:mult_core", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7|altshift:external_latency_ffs", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult7"
+Info (12130): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5"
+Info (12133): Instantiated megafunction "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "4"
+    Info (12134): Parameter "LPM_WIDTHB" = "9"
+    Info (12134): Parameter "LPM_WIDTHP" = "13"
+    Info (12134): Parameter "LPM_WIDTHR" = "13"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5|altshift:external_latency_ffs", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult5"
+Info (12130): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2"
+Info (12133): Instantiated megafunction "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "2"
+    Info (12134): Parameter "LPM_WIDTHB" = "14"
+    Info (12134): Parameter "LPM_WIDTHP" = "16"
+    Info (12134): Parameter "LPM_WIDTHR" = "16"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2|multcore:mult_core", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2|altshift:external_latency_ffs", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult2"
+Info (12130): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6"
+Info (12133): Instantiated megafunction "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "3"
+    Info (12134): Parameter "LPM_WIDTHB" = "7"
+    Info (12134): Parameter "LPM_WIDTHP" = "10"
+    Info (12134): Parameter "LPM_WIDTHR" = "10"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6|altshift:external_latency_ffs", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult6"
+Info (12130): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult3"
+Info (12133): Instantiated megafunction "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult3" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "4"
+    Info (12134): Parameter "LPM_WIDTHB" = "5"
+    Info (12134): Parameter "LPM_WIDTHP" = "9"
+    Info (12134): Parameter "LPM_WIDTHR" = "9"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult3"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult3"
+Info (12130): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4"
+Info (12133): Instantiated megafunction "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "4"
+    Info (12134): Parameter "LPM_WIDTHB" = "7"
+    Info (12134): Parameter "LPM_WIDTHP" = "11"
+    Info (12134): Parameter "LPM_WIDTHR" = "11"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4"
+Info (12131): Elaborated megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "sobel:inst1|sobel_core:sobel_core_inst|lpm_mult:Mult4"
+Warning (12241): 10 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13034): The following nodes have both tri-state and non-tri-state drivers
+    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[20]" and its non-tri-state driver.
+    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[14]" and its non-tri-state driver.
+Warning (13039): The following bidir pins have no drivers
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+Warning (13032): The following tri-state nodes are fed by constants
+    Warning (13033): The pin "GPIO_1[15]" is fed by VCC
+Info (13000): Registers with preset signals will power-up high
+Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
+Warning (13009): TRI or OPNDRN buffers permanently enabled
+    Warning (13010): Node "GPIO_1~synth"
+    Warning (13010): Node "GPIO_1~synth"
+    Warning (13010): Node "GPIO_1~synth"
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "DRAM_CKE" is stuck at VCC
+    Warning (13410): Pin "GPIO_1_CLKOUT[1]" is stuck at GND
+    Warning (13410): Pin "LEDG[9]" is stuck at GND
+    Warning (13410): Pin "LEDG[8]" is stuck at GND
+    Warning (13410): Pin "LEDG[7]" is stuck at GND
+    Warning (13410): Pin "LEDG[6]" is stuck at GND
+    Warning (13410): Pin "LEDG[5]" is stuck at GND
+    Warning (13410): Pin "LEDG[4]" is stuck at GND
+    Warning (13410): Pin "LEDG[3]" is stuck at GND
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 29 registers lost all their fanouts during netlist optimizations.
+Info (17016): Found the following redundant logic cells in design
+    Info (17048): Logic cell "sobel:inst1|sobel_core:sobel_core_inst|Add6~4"
+    Info (17048): Logic cell "sobel:inst1|sobel_core:sobel_core_inst|Add6~6"
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 3 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "GPIO_1_CLKIN[1]"
+    Warning (15610): No output dependent on input pin "SW[9]"
+    Warning (15610): No output dependent on input pin "SW[8]"
+Info (21057): Implemented 4199 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 16 input pins
+    Info (21059): Implemented 77 output pins
+    Info (21060): Implemented 50 bidirectional pins
+    Info (21061): Implemented 3879 logic cells
+    Info (21064): Implemented 176 RAM segments
+    Info (21065): Implemented 1 PLLs
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 113 warnings
+    Info: Peak virtual memory: 563 megabytes
+    Info: Processing ended: Tue Mar 08 16:23:49 2016
+    Info: Elapsed time: 00:00:34
+    Info: Total CPU time (on all processors): 00:00:16
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.summary b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.summary
new file mode 100644
index 0000000..86aa231
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Tue Mar 08 16:23:49 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : DE0_D5M
+Top-level Entity Name : TOP_DE0_CAMERA_MOUSE
+Family : Cyclone III
+Total logic elements : 3,842
+    Total combinational functions : 3,246
+    Dedicated logic registers : 1,389
+Total registers : 1389
+Total pins : 143
+Total virtual pins : 0
+Total memory bits : 134,236
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 1
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pin b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pin
new file mode 100644
index 0000000..bcb2c9e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		3.3V
+ --					Bank 2:		3.3V
+ --					Bank 3:		3.3V
+ --					Bank 4:		3.3V
+ --					Bank 5:		3.3V
+ --					Bank 6:		3.3V
+ --					Bank 7:		3.3V
+ --					Bank 8:		3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+CHIP  "DE0_D5M"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 3.3V    : 8         :                
+DRAM_ADDR[1]                 : A3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_BA_1                    : A4        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[4]                 : A5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[7]                 : A6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[11]                : A7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[8]                   : A8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[10]                  : A9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[13]                  : A10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+HEX1[0]                      : A13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[3]                      : A14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[6]                      : A15       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[1]                      : A16       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[4]                      : A17       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+HEX3[2]                      : A19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 3.3V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 3.3V    : 3         :                
+GPIO_1[16]                   : AA7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+GPIO_1[15]                   : AA9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GPIO_1_CLKIN[1]              : AA11      : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+GPIO_1[6]                    : AA17      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[5]                    : AA18      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[2]                    : AA19      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[0]                    : AA20      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+GPIO_1[17]                   : AB7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+GPIO_1[14]                   : AB9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GPIO_1_CLKIN[0]              : AB11      : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+GPIO_1[7]                    : AB17      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[4]                    : AB18      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[3]                    : AB19      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[1]                    : AB20      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : AB21      : power  :                   : 3.3V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+LEDG[9]                      : B1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[8]                      : B2        : output : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_ADDR[2]                 : B3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[10]                : B4        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_BA_0                    : B5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[6]                 : B6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[9]                 : B7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_UDQM                    : B8        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[9]                   : B9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[12]                  : B10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+HEX1[1]                      : B13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[4]                      : B14       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+HEX2[2]                      : B16       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[5]                      : B17       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[0]                      : B18       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[3]                      : B19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+LEDG[6]                      : C1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[7]                      : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_ADDR[3]                 : C3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[0]                 : C4        : output : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C5        : gnd    :                   :         :           :                
+DRAM_ADDR[5]                 : C6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[8]                 : C7        : output : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+DRAM_DQ[11]                  : C10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+HEX1[2]                      : C13       : output : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+HEX3[4]                      : C19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[9]                        : D2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 3.3V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 3.3V    : 8         :                
+DRAM_WE_N                    : D6        : output : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 3.3V    : 8         :                
+DRAM_DQ[0]                   : D10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : D11       : power  :                   : 3.3V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 3.3V    : 7         :                
+HEX2[0]                      : D15       : output : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : D16       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 3.3V    : 7         :                
+HEX3[5]                      : D19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+LEDG[5]                      : E1        : output : 3.3-V LVTTL       :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[7]                        : E3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[8]                        : E4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_CLK                     : E5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_CKE                     : E6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_LDQM                    : E7        : output : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : E8        : power  :                   : 3.3V    : 8         :                
+DRAM_DQ[3]                   : E9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[14]                  : E10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+HEX0[0]                      : E11       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+HEX1[5]                      : E14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[3]                      : E15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 3.3V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+KEY[2]                       : F1        : input  : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[4]                      : F2        : output : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 3.3V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+DRAM_RAS_N                   : F7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[7]                   : F8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[4]                   : F9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[15]                  : F10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+HEX0[1]                      : F11       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[5]                      : F12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[6]                      : F13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[6]                      : F14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[1]                      : F15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+KEY[1]                       : G3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[3]                        : G4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[4]                        : G5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+DRAM_CS_N                    : G7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_CAS_N                   : G8        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[5]                   : G9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[1]                   : G10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+HEX0[4]                      : G12       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+HEX3[6]                      : G15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 3.3V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+CLOCK_50                     : G21       : input  : 3.3-V LVTTL       :         : 6         : Y              
+GND+                         : G22       :        :                   :         : 6         :                
+LEDG[3]                      : H1        : output : 3.3-V LVTTL       :         : 1         : Y              
+KEY[0]                       : H2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 3.3V    : 1         :                
+SW[1]                        : H5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[2]                        : H6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[6]                        : H7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H8        : gnd    :                   :         :           :                
+DRAM_DQ[6]                   : H9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[2]                   : H10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+HEX0[2]                      : H12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[3]                      : H13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+VGA_R[1]                     : H17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+VGA_R[0]                     : H19       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[2]                     : H20       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[3]                     : H21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_G[0]                     : H22       : output : 3.3-V LVTTL       :         : 6         : Y              
+LEDG[0]                      : J1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[1]                      : J2        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[2]                      : J3        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+SW[0]                        : J6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[5]                        : J7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+VGA_G[1]                     : J17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 3.3V    : 6         :                
+VGA_G[3]                     : J21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[2]                     : J22       : output : 3.3-V LVTTL       :         : 6         : Y              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 3.3-V LVTTL       :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 3.3-V LVTTL       :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 3.3V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+VGA_G[2]                     : K17       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[3]                     : K18       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+VGA_B[1]                     : K21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[0]                     : K22       : output : 3.3-V LVTTL       :         : 6         : Y              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 3.3V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+VGA_HS                       : L21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_VS                       : L22       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 3.3V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 3.3V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+PS2_DAT                      : P21       : bidir  : 3.3-V LVTTL       :         : 5         : Y              
+PS2_CLK                      : P22       : bidir  : 3.3-V LVTTL       :         : 5         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 3.3V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+GPIO_1[22]                   : R11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[23]                   : R12       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+GPIO_1[19]                   : R14       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+GPIO_1_CLKOUT[0]             : R16       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+GPIO_1[27]                   : T9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[25]                   : T10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+GPIO_1[21]                   : T12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+GPIO_1[18]                   : T14       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[11]                   : T15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1_CLKOUT[1]             : T16       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 3.3V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 3.3V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+GPIO_1[29]                   : U8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[26]                   : U9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[24]                   : U10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+GPIO_1[20]                   : U12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+GPIO_1[10]                   : U15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+GPIO_1[30]                   : V6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[31]                   : V7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+GPIO_1[13]                   : V15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 3.3V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 3.3V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 3.3V    : 3         :                
+VGA_CLK                      : W10       : output : 3.3-V LVTTL       :         : 3         : N              
+VCCIO3                       : W11       : power  :                   : 3.3V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 3.3V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+GPIO_1[12]                   : W15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : W16       : power  :                   : 3.3V    : 4         :                
+GPIO_1[9]                    : W17       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : W18       : power  :                   : 3.3V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+GPIO_1[28]                   : Y7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 3.3V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+GPIO_1[8]                    : Y17       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 3.3V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof
new file mode 100644
index 0000000..a577d51
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qpf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qpf
new file mode 100644
index 0000000..fad5fa0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qpf
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "13.1"
+DATE = "14:14:24  April 30, 2008"
+
+
+# Revisions
+
+PROJECT_REVISION = "DE0_D5M"
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf
new file mode 100644
index 0000000..072627e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf
@@ -0,0 +1,576 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE0_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY TOP_DE0_CAMERA_MOUSE
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+
+
+
+
+
+
+
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+
+set_location_assignment PIN_AA11 -to GPIO_1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO_1_CLKIN[0]
+
+set_location_assignment PIN_T16 -to GPIO_1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO_1_CLKOUT[0]
+
+
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+
+
+
+
+set_location_assignment PIN_E11 -to HEX0[0]
+set_location_assignment PIN_F11 -to HEX0[1]
+set_location_assignment PIN_H12 -to HEX0[2]
+set_location_assignment PIN_H13 -to HEX0[3]
+set_location_assignment PIN_G12 -to HEX0[4]
+set_location_assignment PIN_F12 -to HEX0[5]
+set_location_assignment PIN_F13 -to HEX0[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+
+set_location_assignment PIN_A15 -to HEX1[6]
+set_location_assignment PIN_E14 -to HEX1[5]
+set_location_assignment PIN_B14 -to HEX1[4]
+set_location_assignment PIN_A14 -to HEX1[3]
+set_location_assignment PIN_C13 -to HEX1[2]
+set_location_assignment PIN_B13 -to HEX1[1]
+set_location_assignment PIN_A13 -to HEX1[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+
+set_location_assignment PIN_F14 -to HEX2[6]
+set_location_assignment PIN_B17 -to HEX2[5]
+set_location_assignment PIN_A17 -to HEX2[4]
+set_location_assignment PIN_E15 -to HEX2[3]
+set_location_assignment PIN_B16 -to HEX2[2]
+set_location_assignment PIN_A16 -to HEX2[1]
+set_location_assignment PIN_D15 -to HEX2[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+
+set_location_assignment PIN_G15 -to HEX3[6]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_C19 -to HEX3[4]
+set_location_assignment PIN_B19 -to HEX3[3]
+set_location_assignment PIN_A19 -to HEX3[2]
+set_location_assignment PIN_F15 -to HEX3[1]
+set_location_assignment PIN_B18 -to HEX3[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+
+set_location_assignment PIN_G21 -to CLOCK_50
+
+# mouse connected as keyboard ...
+set_location_assignment PIN_P22 -to PS2_CLK
+set_location_assignment PIN_P21 -to PS2_DAT
+
+#set_location_assignment PIN_F14 -to UART_RXD
+#set_location_assignment PIN_G12 -to UART_TXD
+
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+set_location_assignment PIN_B12 -to CLOCK_50_2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_1_CLKIN[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_1_CLKOUT[0]
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+
+
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+
+
+set_global_assignment -name VERILOG_FILE "../../../../../Sobel/Sobel Quartus/sobel.v"
+set_global_assignment -name VERILOG_FILE V/ps2.v
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE0_D5M.v
+set_global_assignment -name SDC_FILE DE0_D5M.sdc
+set_global_assignment -name BDF_FILE V/TOP_DE0_CAMERA_MOUSE.bdf
+set_global_assignment -name QIP_FILE vga_mux.qip
+set_global_assignment -name VERILOG_FILE catapult_ip/mouse/rtl_mgc_ioport_v2001.v
+set_global_assignment -name VERILOG_FILE catapult_ip/mouse/rtl_mgc_ioport.v
+set_global_assignment -name VERILOG_FILE catapult_ip/mouse/rtl.v
+set_global_assignment -name CDF_FILE "../../../../../Sobel/Sobel Quartus/output_files/Chain3.cdf"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name CDF_FILE "../../../../../Sobel/Sobel Quartus/output_files/Chain7.cdf"
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf.bak
new file mode 100644
index 0000000..8404697
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf.bak
@@ -0,0 +1,571 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE0_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY TOP_DE0_CAMERA_MOUSE
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+
+
+
+
+
+
+
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+
+set_location_assignment PIN_AA11 -to GPIO_1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO_1_CLKIN[0]
+
+set_location_assignment PIN_T16 -to GPIO_1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO_1_CLKOUT[0]
+
+
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+
+
+
+
+set_location_assignment PIN_E11 -to HEX0[0]
+set_location_assignment PIN_F11 -to HEX0[1]
+set_location_assignment PIN_H12 -to HEX0[2]
+set_location_assignment PIN_H13 -to HEX0[3]
+set_location_assignment PIN_G12 -to HEX0[4]
+set_location_assignment PIN_F12 -to HEX0[5]
+set_location_assignment PIN_F13 -to HEX0[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+
+set_location_assignment PIN_A15 -to HEX1[6]
+set_location_assignment PIN_E14 -to HEX1[5]
+set_location_assignment PIN_B14 -to HEX1[4]
+set_location_assignment PIN_A14 -to HEX1[3]
+set_location_assignment PIN_C13 -to HEX1[2]
+set_location_assignment PIN_B13 -to HEX1[1]
+set_location_assignment PIN_A13 -to HEX1[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+
+set_location_assignment PIN_F14 -to HEX2[6]
+set_location_assignment PIN_B17 -to HEX2[5]
+set_location_assignment PIN_A17 -to HEX2[4]
+set_location_assignment PIN_E15 -to HEX2[3]
+set_location_assignment PIN_B16 -to HEX2[2]
+set_location_assignment PIN_A16 -to HEX2[1]
+set_location_assignment PIN_D15 -to HEX2[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+
+set_location_assignment PIN_G15 -to HEX3[6]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_C19 -to HEX3[4]
+set_location_assignment PIN_B19 -to HEX3[3]
+set_location_assignment PIN_A19 -to HEX3[2]
+set_location_assignment PIN_F15 -to HEX3[1]
+set_location_assignment PIN_B18 -to HEX3[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+
+set_location_assignment PIN_G21 -to CLOCK_50
+
+set_location_assignment PIN_R21 -to PS2_CLK
+set_location_assignment PIN_R22 -to PS2_DAT
+
+#set_location_assignment PIN_F14 -to UART_RXD
+#set_location_assignment PIN_G12 -to UART_TXD
+
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+set_location_assignment PIN_B12 -to CLOCK_50_2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE catapult_ip/rtl_mgc_ioport_v2001.v
+set_global_assignment -name VERILOG_FILE catapult_ip/rtl_mgc_ioport.v
+set_global_assignment -name VERILOG_FILE catapult_ip/rtl.v
+set_global_assignment -name VERILOG_FILE V/ps2.v
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE0_D5M.v
+set_global_assignment -name SDC_FILE DE0_D5M.sdc
+set_global_assignment -name BDF_FILE V/TOP_DE0_CAMERA_MOUSE.bdf
+
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_1_CLKIN[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_1_CLKOUT[0]
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+
+
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qws b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qws
new file mode 100644
index 0000000..386a843
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qws
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sdc b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sdc
new file mode 100644
index 0000000..6a9d418
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sdc
@@ -0,0 +1,41 @@
+#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.                           
+#
+# Version 10.0 Build 218 06/27/2010 SJ Full Version
+#
+#************************************************************
+
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "CLOCK_50" -period 20ns [get_ports {CLOCK_50}] -waveform {0.000ns 10.000ns}
+
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+#derive_clock_uncertainty
+# Not supported for family Cyclone II
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof
new file mode 100644
index 0000000..da170fd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt
new file mode 100644
index 0000000..436046b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt
@@ -0,0 +1,10440 @@
+TimeQuest Timing Analyzer report for DE0_D5M
+Tue Mar 08 16:24:59 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. SDC File List
+  5. Clocks
+  6. Slow 1200mV 85C Model Fmax Summary
+  7. Timing Closure Recommendations
+  8. Slow 1200mV 85C Model Setup Summary
+  9. Slow 1200mV 85C Model Hold Summary
+ 10. Slow 1200mV 85C Model Recovery Summary
+ 11. Slow 1200mV 85C Model Removal Summary
+ 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 13. Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 14. Slow 1200mV 85C Model Setup: 'CLOCK_50'
+ 15. Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 16. Slow 1200mV 85C Model Hold: 'CLOCK_50'
+ 17. Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 18. Slow 1200mV 85C Model Recovery: 'CLOCK_50'
+ 19. Slow 1200mV 85C Model Removal: 'CLOCK_50'
+ 20. Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 21. Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 22. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
+ 23. Setup Times
+ 24. Hold Times
+ 25. Clock to Output Times
+ 26. Minimum Clock to Output Times
+ 27. Propagation Delay
+ 28. Minimum Propagation Delay
+ 29. Output Enable Times
+ 30. Minimum Output Enable Times
+ 31. Output Disable Times
+ 32. Minimum Output Disable Times
+ 33. MTBF Summary
+ 34. Synchronizer Summary
+ 35. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+ 36. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+ 37. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+ 38. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+ 39. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+ 40. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+ 41. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+ 42. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+ 43. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+ 44. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+ 45. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+ 46. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+ 47. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+ 48. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+ 49. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+ 50. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+ 51. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+ 52. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+ 53. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+ 54. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+ 55. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+ 56. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+ 57. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+ 58. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+ 59. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+ 60. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+ 61. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+ 62. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+ 63. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+ 64. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+ 65. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+ 66. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+ 67. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+ 68. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+ 69. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+ 70. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+ 71. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+ 72. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+ 73. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+ 74. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+ 75. Slow 1200mV 0C Model Fmax Summary
+ 76. Slow 1200mV 0C Model Setup Summary
+ 77. Slow 1200mV 0C Model Hold Summary
+ 78. Slow 1200mV 0C Model Recovery Summary
+ 79. Slow 1200mV 0C Model Removal Summary
+ 80. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 81. Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 82. Slow 1200mV 0C Model Setup: 'CLOCK_50'
+ 83. Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 84. Slow 1200mV 0C Model Hold: 'CLOCK_50'
+ 85. Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 86. Slow 1200mV 0C Model Recovery: 'CLOCK_50'
+ 87. Slow 1200mV 0C Model Removal: 'CLOCK_50'
+ 88. Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 89. Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 90. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+ 91. Setup Times
+ 92. Hold Times
+ 93. Clock to Output Times
+ 94. Minimum Clock to Output Times
+ 95. Propagation Delay
+ 96. Minimum Propagation Delay
+ 97. Output Enable Times
+ 98. Minimum Output Enable Times
+ 99. Output Disable Times
+100. Minimum Output Disable Times
+101. MTBF Summary
+102. Synchronizer Summary
+103. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+104. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+105. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+106. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+107. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+108. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+109. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+110. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+111. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+112. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+113. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+114. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+115. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+116. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+117. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+118. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+119. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+120. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+121. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+122. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+123. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+124. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+125. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+126. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+127. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+128. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+129. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+130. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+131. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+132. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+133. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+134. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+135. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+136. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+137. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+138. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+139. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+140. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+141. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+142. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+143. Fast 1200mV 0C Model Setup Summary
+144. Fast 1200mV 0C Model Hold Summary
+145. Fast 1200mV 0C Model Recovery Summary
+146. Fast 1200mV 0C Model Removal Summary
+147. Fast 1200mV 0C Model Minimum Pulse Width Summary
+148. Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+149. Fast 1200mV 0C Model Setup: 'CLOCK_50'
+150. Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+151. Fast 1200mV 0C Model Hold: 'CLOCK_50'
+152. Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+153. Fast 1200mV 0C Model Recovery: 'CLOCK_50'
+154. Fast 1200mV 0C Model Removal: 'CLOCK_50'
+155. Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+156. Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+157. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+158. Setup Times
+159. Hold Times
+160. Clock to Output Times
+161. Minimum Clock to Output Times
+162. Propagation Delay
+163. Minimum Propagation Delay
+164. Output Enable Times
+165. Minimum Output Enable Times
+166. Output Disable Times
+167. Minimum Output Disable Times
+168. MTBF Summary
+169. Synchronizer Summary
+170. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+171. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+172. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+173. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+174. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+175. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+176. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+177. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+178. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+179. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+180. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+181. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+182. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+183. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+184. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+185. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+186. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+187. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+188. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+189. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+190. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+191. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+192. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+193. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+194. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+195. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+196. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+197. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+198. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+199. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+200. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+201. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+202. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+203. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+204. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+205. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+206. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+207. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+208. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+209. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+210. Multicorner Timing Analysis Summary
+211. Setup Times
+212. Hold Times
+213. Clock to Output Times
+214. Minimum Clock to Output Times
+215. Progagation Delay
+216. Minimum Progagation Delay
+217. Board Trace Model Assignments
+218. Input Transition Times
+219. Slow Corner Signal Integrity Metrics
+220. Fast Corner Signal Integrity Metrics
+221. Setup Transfers
+222. Hold Transfers
+223. Recovery Transfers
+224. Removal Transfers
+225. Report TCCS
+226. Report RSKM
+227. Unconstrained Paths
+228. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                       ;
++--------------------+--------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ;
+; Revision Name      ; DE0_D5M                                                            ;
+; Device Family      ; Cyclone III                                                        ;
+; Device Name        ; EP3C16F484C6                                                       ;
+; Timing Models      ; Final                                                              ;
+; Delay Model        ; Combined                                                           ;
+; Rise/Fall Delays   ; Enabled                                                            ;
++--------------------+--------------------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------+
+; SDC File List                                     ;
++---------------+--------+--------------------------+
+; SDC File Path ; Status ; Read at                  ;
++---------------+--------+--------------------------+
+; DE0_D5M.sdc   ; OK     ; Tue Mar 08 16:24:52 2016 ;
++---------------+--------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                                                                                                                                           ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+; Clock Name                                          ; Type      ; Period ; Frequency ; Rise   ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase  ; Offset ; Edge List ; Edge Shift ; Inverted ; Master   ; Source                                                ; Targets                                                 ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+; CLOCK_50                                            ; Base      ; 20.000 ; 50.0 MHz  ; 0.000  ; 10.000 ;            ;           ;             ;        ;        ;           ;            ;          ;          ;                                                       ; { CLOCK_50 }                                            ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.000  ; 125.0 MHz ; 0.000  ; 4.000  ; 50.00      ; 2         ; 5           ;        ;        ;           ;            ; false    ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[0] } ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 8.000  ; 125.0 MHz ; -2.600 ; 1.400  ; 50.00      ; 2         ; 5           ; -117.0 ;        ;           ;            ; false    ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[1] } ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                                        ;
++------------+-----------------+-----------------------------------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name                                          ; Note ;
++------------+-----------------+-----------------------------------------------------+------+
+; 167.25 MHz ; 167.25 MHz      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;      ;
+; 174.46 MHz ; 174.46 MHz      ; CLOCK_50                                            ;      ;
++------------+-----------------+-----------------------------------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup Summary                                          ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.837 ; -39.407       ;
+; CLOCK_50                                            ; 14.268 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold Summary                                          ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.331 ; 0.000         ;
+; CLOCK_50                                            ; 0.358 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery Summary                                       ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -1.488 ; -368.986      ;
+; CLOCK_50                                            ; 12.673 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal Summary                                       ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 1.559 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.115 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.734 ; 0.000         ;
+; CLOCK_50                                            ; 9.580 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.837 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.317      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.278      ;
+; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.239      ;
+; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.239      ;
+; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.239      ;
+; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.239      ;
+; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.239      ;
+; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.239      ;
+; -0.760 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.239      ;
+; -0.747 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.536     ; 2.226      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.566 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.046      ;
+; -0.533 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.013      ;
+; -0.451 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.181     ; 2.285      ;
+; -0.451 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.181     ; 2.285      ;
+; -0.451 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.181     ; 2.285      ;
+; -0.451 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.181     ; 2.285      ;
+; -0.439 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.186     ; 2.268      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 1.901      ;
+; -0.339 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.167      ;
+; -0.339 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.167      ;
+; -0.339 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.167      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; -0.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 1.937      ;
+; 0.017  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.186     ; 1.812      ;
+; 0.017  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.186     ; 1.812      ;
+; 0.017  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.186     ; 1.812      ;
+; 2.021  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.413     ; 5.581      ;
+; 2.036  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.425     ; 5.554      ;
+; 2.045  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.425     ; 5.545      ;
+; 2.103  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.414     ; 5.498      ;
+; 2.103  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.414     ; 5.498      ;
+; 2.103  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.414     ; 5.498      ;
+; 2.103  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.414     ; 5.498      ;
+; 2.103  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.414     ; 5.498      ;
+; 2.103  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.414     ; 5.498      ;
+; 2.103  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.414     ; 5.498      ;
+; 2.105  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.414     ; 5.496      ;
+; 2.117  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.413     ; 5.485      ;
+; 2.123  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.425     ; 5.467      ;
+; 2.146  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.425     ; 5.444      ;
+; 2.159  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.413     ; 5.443      ;
+; 2.178  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.414     ; 5.423      ;
+; 2.195  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.066     ; 5.754      ;
+; 2.199  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.414     ; 5.402      ;
+; 2.199  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.414     ; 5.402      ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'CLOCK_50'                                                                                                                                             ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                       ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 14.268 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.952      ;
+; 14.302 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.918      ;
+; 14.469 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.751      ;
+; 14.553 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.667      ;
+; 14.618 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.602      ;
+; 14.760 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.460      ;
+; 14.868 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.352      ;
+; 14.922 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.298      ;
+; 14.982 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.238      ;
+; 15.048 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.172      ;
+; 15.105 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.115      ;
+; 15.132 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.088      ;
+; 15.203 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.017      ;
+; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.559      ;
+; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.559      ;
+; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.559      ;
+; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.559      ;
+; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.559      ;
+; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.559      ;
+; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.559      ;
+; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.559      ;
+; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.559      ;
+; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.559      ;
+; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.559      ;
+; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.559      ;
+; 15.398 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.559      ;
+; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.550      ;
+; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.550      ;
+; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.550      ;
+; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.550      ;
+; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.550      ;
+; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.550      ;
+; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.550      ;
+; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.550      ;
+; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.550      ;
+; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.550      ;
+; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.550      ;
+; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.550      ;
+; 15.407 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.550      ;
+; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.454      ;
+; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.454      ;
+; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.454      ;
+; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.454      ;
+; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.454      ;
+; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.454      ;
+; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.454      ;
+; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.454      ;
+; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.454      ;
+; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.454      ;
+; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.454      ;
+; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.454      ;
+; 15.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.454      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.414      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.406      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.406      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.406      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.406      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.406      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.406      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.406      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.406      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.406      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.406      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.406      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.406      ;
+; 15.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.406      ;
+; 15.628 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 3.592      ;
+; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.316      ;
+; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.316      ;
+; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.316      ;
+; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.316      ;
+; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.316      ;
+; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.316      ;
+; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.316      ;
+; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.316      ;
+; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.316      ;
+; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.316      ;
+; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.316      ;
+; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.316      ;
+; 15.641 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.316      ;
+; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.260      ;
+; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.260      ;
+; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.260      ;
+; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.260      ;
+; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.260      ;
+; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.260      ;
+; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.260      ;
+; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.260      ;
+; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.260      ;
+; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.260      ;
+; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.260      ;
+; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.260      ;
+; 15.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.260      ;
+; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.259      ;
+; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.259      ;
+; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.259      ;
+; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.259      ;
+; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.259      ;
+; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.259      ;
+; 15.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.259      ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.376      ; 0.894      ;
+; 0.336 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.378      ; 0.901      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.378      ; 0.905      ;
+; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.376      ; 0.904      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.393      ; 0.894      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.353 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.378      ; 0.918      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.593      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.580      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.580      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.580      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.594      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.593      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.591      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_done                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CAS_N                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|CAS_N                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|RAS_N                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[11]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[14]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[8]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[12]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.376 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.595      ;
+; 0.376 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.594      ;
+; 0.376 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.595      ;
+; 0.379 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CS_N[0]                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.598      ;
+; 0.383 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[3]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.602      ;
+; 0.383 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.602      ;
+; 0.384 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.616      ;
+; 0.390 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.608      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'CLOCK_50'                                                                                                                                                      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.361 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
+; 0.362 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.580      ;
+; 0.375 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.593      ;
+; 0.382 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.600      ;
+; 0.385 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.580      ;
+; 0.390 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.609      ;
+; 0.408 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.627      ;
+; 0.523 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.741      ;
+; 0.551 ; ps2:inst6|clk_div[6]                                  ; ps2:inst6|clk_div[6]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.769      ;
+; 0.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.769      ;
+; 0.554 ; ps2:inst6|clk_div[2]                                  ; ps2:inst6|clk_div[2]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.772      ;
+; 0.554 ; ps2:inst6|clk_div[4]                                  ; ps2:inst6|clk_div[4]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.772      ;
+; 0.555 ; ps2:inst6|clk_div[7]                                  ; ps2:inst6|clk_div[7]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.773      ;
+; 0.556 ; ps2:inst6|clk_div[3]                                  ; ps2:inst6|clk_div[3]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.774      ;
+; 0.556 ; ps2:inst6|clk_div[5]                                  ; ps2:inst6|clk_div[5]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.774      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.775      ;
+; 0.557 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.775      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.775      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.558 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.776      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.776      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.559 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.778      ;
+; 0.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.777      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.778      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.779      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.779      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.779      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.780      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.781      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.780      ;
+; 0.563 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.782      ;
+; 0.567 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.785      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.788      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.788      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.790      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.790      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.792      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.574 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.793      ;
+; 0.574 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.793      ;
+; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.792      ;
+; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.793      ;
+; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.794      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.580 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.799      ;
+; 0.582 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.800      ;
+; 0.587 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.806      ;
+; 0.588 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.807      ;
+; 0.591 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.810      ;
+; 0.594 ; ps2:inst6|clk_div[8]                                  ; ps2:inst6|clk_div[8]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.789      ;
+; 0.611 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.830      ;
+; 0.659 ; ps2:inst6|clk_div[7]                                  ; ps2:inst6|clk_div[8]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.244      ; 1.060      ;
+; 0.699 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.918      ;
+; 0.699 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.918      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.488 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.281     ; 3.156      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.155      ;
+; -1.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.278     ; 3.198      ;
+; -1.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.277     ; 3.197      ;
+; -1.334 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.799      ;
+; -1.334 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.799      ;
+; -1.334 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.799      ;
+; -1.334 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.799      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.798      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.798      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.798      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.798      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.798      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.798      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.798      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.798      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.798      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.797      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.797      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.797      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.797      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.796      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.796      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.541     ; 2.797      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.796      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.549     ; 2.789      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.805      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.805      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.805      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.805      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.805      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.805      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.805      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.805      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.805      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.805      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.533     ; 2.804      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.805      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.805      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.794      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.794      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.794      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.794      ;
+; -1.322 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.794      ;
+; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 2.802      ;
+; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 2.802      ;
+; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 2.802      ;
+; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.804      ;
+; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.804      ;
+; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.804      ;
+; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.804      ;
+; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.804      ;
+; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.804      ;
+; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.804      ;
+; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.804      ;
+; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.534     ; 2.802      ;
+; -1.321 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.532     ; 2.804      ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'CLOCK_50'                                                                                                                                    ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 12.673 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 6.547      ;
+; 12.682 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 6.538      ;
+; 12.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 6.442      ;
+; 12.825 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.796     ; 6.394      ;
+; 12.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 6.304      ;
+; 12.971 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.796     ; 6.248      ;
+; 12.972 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.796     ; 6.247      ;
+; 12.981 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.796     ; 6.238      ;
+; 13.065 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.796     ; 6.154      ;
+; 13.077 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.796     ; 6.142      ;
+; 13.201 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.796     ; 6.018      ;
+; 13.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.796     ; 6.014      ;
+; 13.210 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.796     ; 6.009      ;
+; 13.214 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.796     ; 6.005      ;
+; 13.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.796     ; 5.914      ;
+; 13.444 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.796     ; 5.775      ;
+; 13.911 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 5.309      ;
+; 14.011 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 5.209      ;
+; 14.027 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 5.187      ;
+; 14.188 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 5.032      ;
+; 14.197 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 5.023      ;
+; 14.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.976      ;
+; 14.294 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.926      ;
+; 14.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.870      ;
+; 14.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.789      ;
+; 14.532 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.795     ; 4.688      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.207 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.747      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.738      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.642      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.594      ;
+; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.504      ;
+; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.504      ;
+; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.504      ;
+; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.504      ;
+; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.504      ;
+; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.504      ;
+; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.504      ;
+; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.504      ;
+; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.504      ;
+; 15.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 4.504      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'CLOCK_50'                                                                                                                                                   ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.778      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 1.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.882      ;
+; 2.109 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.070      ; 2.336      ;
+; 2.109 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.070      ; 2.336      ;
+; 2.109 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.070      ; 2.336      ;
+; 2.109 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.070      ; 2.336      ;
+; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 2.350      ;
+; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 2.350      ;
+; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 2.350      ;
+; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 2.350      ;
+; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 2.350      ;
+; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 2.350      ;
+; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 2.350      ;
+; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 2.350      ;
+; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 2.350      ;
+; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 2.350      ;
+; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 2.350      ;
+; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 2.350      ;
+; 2.122 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.071      ; 2.350      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.644      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.644      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.644      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.644      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.644      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.644      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.644      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.644      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.644      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.644      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.644      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.644      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.687      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.696      ;
+; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.792      ;
+; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.792      ;
+; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.792      ;
+; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.792      ;
+; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.792      ;
+; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.792      ;
+; 2.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.792      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 4.115 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.671     ; 2.601      ;
+; 4.131 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.682     ; 2.606      ;
+; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.605      ;
+; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.605      ;
+; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.605      ;
+; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.605      ;
+; 4.139 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.596      ;
+; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.601      ;
+; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.601      ;
+; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.609      ;
+; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.608      ;
+; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.608      ;
+; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.601      ;
+; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.601      ;
+; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.601      ;
+; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.601      ;
+; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.601      ;
+; 4.140 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.601      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.609      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.609      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.609      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.609      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.609      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.609      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.609      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.693     ; 2.605      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.693     ; 2.605      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.693     ; 2.605      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.693     ; 2.605      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.693     ; 2.605      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.693     ; 2.605      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.693     ; 2.605      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.693     ; 2.605      ;
+; 4.141 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.693     ; 2.605      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.601      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.601      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.699     ; 2.602      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.601      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.601      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.601      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.699     ; 2.602      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.601      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.601      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.699     ; 2.602      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.601      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.601      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.601      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.699     ; 2.602      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.699     ; 2.602      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.601      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.601      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.699     ; 2.602      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.699     ; 2.602      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.601      ;
+; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.608      ;
+; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.608      ;
+; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.608      ;
+; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.608      ;
+; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.608      ;
+; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.608      ;
+; 4.154 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.608      ;
+; 4.166 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.728     ; 2.595      ;
+; 4.166 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.728     ; 2.595      ;
+; 4.166 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.728     ; 2.595      ;
+; 4.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.713     ; 2.612      ;
+; 4.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.713     ; 2.612      ;
+; 4.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.713     ; 2.612      ;
+; 4.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.713     ; 2.612      ;
+; 4.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.713     ; 2.612      ;
+; 4.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.713     ; 2.612      ;
+; 4.170 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.722     ; 2.605      ;
+; 4.170 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.722     ; 2.605      ;
+; 4.170 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.722     ; 2.605      ;
+; 4.170 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.722     ; 2.605      ;
+; 4.170 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.722     ; 2.605      ;
+; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.721     ; 2.607      ;
+; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.721     ; 2.607      ;
+; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.721     ; 2.607      ;
+; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.721     ; 2.607      ;
+; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.721     ; 2.607      ;
+; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.721     ; 2.607      ;
+; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.721     ; 2.607      ;
+; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.721     ; 2.607      ;
+; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.721     ; 2.607      ;
+; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.728     ; 2.600      ;
+; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.721     ; 2.607      ;
+; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.728     ; 2.600      ;
+; 4.171 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.728     ; 2.600      ;
+; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.728     ; 2.602      ;
+; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.728     ; 2.602      ;
+; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.728     ; 2.602      ;
+; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.728     ; 2.602      ;
+; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.728     ; 2.602      ;
+; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.728     ; 2.602      ;
+; 4.173 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.728     ; 2.602      ;
+; 4.175 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.726     ; 2.606      ;
+; 4.175 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.726     ; 2.606      ;
+; 4.175 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.726     ; 2.606      ;
+; 4.175 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.726     ; 2.606      ;
+; 4.175 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.726     ; 2.606      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                        ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.734 ; 3.964        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.734 ; 3.964        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.734 ; 3.964        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.735 ; 3.965        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.735 ; 3.965        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.735 ; 3.965        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.753 ; 3.969        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ;
+; 3.753 ; 3.969        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ;
+; 3.753 ; 3.969        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ;
+; 3.753 ; 3.969        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; 3.753 ; 3.969        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; 3.753 ; 3.969        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[0]                                                                                                   ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[10]                                                                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[11]                                                                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[12]                                                                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[13]                                                                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[14]                                                                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[15]                                                                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[1]                                                                                                   ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[2]                                                                                                   ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[3]                                                                                                   ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[4]                                                                                                   ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[5]                                                                                                   ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[6]                                                                                                   ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[7]                                                                                                   ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[8]                                                                                                   ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[9]                                                                                                   ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'                                                                                   ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; 9.580 ; 9.764        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[0]                                  ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[1]                                  ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[2]                                  ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[3]                                  ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[4]                                  ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[5]                                  ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[6]                                  ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[7]                                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 4.175 ; 4.835 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 4.175 ; 4.835 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 3.570 ; 4.128 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 4.346 ; 4.882 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.719 ; 4.304 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.888 ; 4.403 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.837 ; 4.347 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 4.081 ; 4.605 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.797 ; 4.328 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.695 ; 4.207 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 4.048 ; 4.575 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.537 ; 4.045 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.682 ; 4.211 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.737 ; 4.250 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.742 ; 4.251 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.421 ; 3.933 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.713 ; 4.225 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.625 ; 4.168 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 4.346 ; 4.882 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.845 ; -2.405 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.845 ; -2.427 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.884 ; -2.405 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -2.726 ; -3.218 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; -3.015 ; -3.577 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; -3.213 ; -3.718 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; -3.164 ; -3.665 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; -3.400 ; -3.914 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; -3.085 ; -3.597 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; -3.015 ; -3.508 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -3.367 ; -3.884 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -2.835 ; -3.324 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -2.987 ; -3.507 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -3.057 ; -3.551 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; -3.061 ; -3.551 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -2.726 ; -3.218 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -3.034 ; -3.526 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -2.925 ; -3.447 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -3.653 ; -4.179 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 7.926  ; 7.746  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.149  ; 6.132  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 7.926  ; 7.746  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 6.407  ; 6.287  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 6.407  ; 6.287  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.330  ; 5.394  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.444  ; 3.336  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.223  ; 3.114  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.394  ; 3.270  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.393  ; 3.273  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.194  ; 3.089  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.242  ; 3.141  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 2.965  ; 2.870  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.035  ; 2.936  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.444  ; 3.336  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.208  ; 3.095  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.424  ; 3.303  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.007  ; 2.910  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.990  ; 2.893  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 2.996  ; 2.900  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.000  ; 2.907  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 2.965  ; 2.866  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.315  ; 3.195  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 6.815  ; 6.557  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.037  ; 4.853  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.167  ; 4.959  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.229  ; 5.016  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 6.815  ; 6.557  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.405  ; 5.227  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.223  ; 5.014  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 5.360  ; 5.203  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.549  ; 5.513  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.131  ; 5.050  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 4.801  ; 4.763  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.067  ; 4.895  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 4.775  ; 4.677  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 4.893  ; 4.820  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.056  ; 4.954  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 4.932  ; 4.824  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.289  ; 5.224  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.211  ; 3.112  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.148  ; 3.043  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.560  ; 3.464  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.206  ; 4.875  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.575 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.703 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.003  ; 5.982  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.003  ; 5.982  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 7.711  ; 7.532  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 6.251  ; 6.130  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 6.251  ; 6.130  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.211  ; 5.277  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.545  ; 2.449  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 2.794  ; 2.684  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.958  ; 2.834  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 2.957  ; 2.837  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 2.765  ; 2.659  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 2.812  ; 2.711  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 2.545  ; 2.449  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 2.613  ; 2.514  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.007  ; 2.897  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 2.779  ; 2.665  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 2.987  ; 2.865  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 2.586  ; 2.488  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.570  ; 2.472  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 2.575  ; 2.479  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 2.580  ; 2.486  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 2.544  ; 2.445  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 2.880  ; 2.760  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 3.652  ; 3.513  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 3.652  ; 3.514  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 3.941  ; 3.843  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 4.014  ; 3.921  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 5.754  ; 5.423  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 4.173  ; 4.062  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 3.997  ; 3.903  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 3.966  ; 3.855  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 4.167  ; 4.084  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 3.879  ; 3.786  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 3.663  ; 3.513  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 3.978  ; 3.869  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 3.828  ; 3.736  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 3.788  ; 3.664  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.177  ; 4.091  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 3.763  ; 3.612  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 4.126  ; 3.964  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 2.782  ; 2.681  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 2.721  ; 2.615  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.117  ; 3.020  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 4.777  ; 4.446  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.948 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.075 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++------------------------------------------------------------+
+; Propagation Delay                                          ;
++------------+-------------+-------+-------+--------+--------+
+; Input Port ; Output Port ; RR    ; RF    ; FR     ; FF     ;
++------------+-------------+-------+-------+--------+--------+
+; SW[4]      ; VGA_B[0]    ; 8.826 ; 8.684 ; 9.435  ; 9.293  ;
+; SW[4]      ; VGA_B[1]    ; 9.179 ; 9.016 ; 9.739  ; 9.533  ;
+; SW[4]      ; VGA_B[2]    ; 8.250 ; 8.155 ; 8.832  ; 8.739  ;
+; SW[4]      ; VGA_B[3]    ; 8.364 ; 8.243 ; 8.973  ; 8.852  ;
+; SW[4]      ; VGA_G[0]    ; 9.485 ; 9.420 ; 10.061 ; 9.947  ;
+; SW[4]      ; VGA_G[1]    ; 8.548 ; 8.524 ; 9.170  ; 9.146  ;
+; SW[4]      ; VGA_G[2]    ; 8.898 ; 8.839 ; 9.483  ; 9.352  ;
+; SW[4]      ; VGA_G[3]    ; 8.888 ; 8.793 ; 9.498  ; 9.407  ;
+; SW[4]      ; VGA_R[0]    ; 9.747 ; 9.647 ; 10.341 ; 10.272 ;
+; SW[4]      ; VGA_R[1]    ; 9.114 ; 8.972 ; 9.685  ; 9.510  ;
+; SW[4]      ; VGA_R[2]    ; 8.692 ; 8.534 ; 9.241  ; 9.092  ;
+; SW[4]      ; VGA_R[3]    ; 8.517 ; 8.427 ; 9.113  ; 9.023  ;
+; SW[5]      ; VGA_B[0]    ; 8.458 ; 8.316 ; 9.069  ; 8.927  ;
+; SW[5]      ; VGA_B[1]    ; 8.540 ; 8.377 ; 9.057  ; 8.894  ;
+; SW[5]      ; VGA_B[2]    ; 8.138 ; 8.045 ; 8.672  ; 8.553  ;
+; SW[5]      ; VGA_B[3]    ; 7.996 ; 7.875 ; 8.606  ; 8.485  ;
+; SW[5]      ; VGA_G[0]    ; 8.837 ; 8.772 ; 9.396  ; 9.326  ;
+; SW[5]      ; VGA_G[1]    ; 8.195 ; 8.171 ; 8.754  ; 8.730  ;
+; SW[5]      ; VGA_G[2]    ; 8.330 ; 8.252 ; 8.870  ; 8.783  ;
+; SW[5]      ; VGA_G[3]    ; 8.527 ; 8.427 ; 9.130  ; 9.039  ;
+; SW[5]      ; VGA_R[0]    ; 9.391 ; 9.296 ; 9.924  ; 9.857  ;
+; SW[5]      ; VGA_R[1]    ; 8.481 ; 8.339 ; 9.004  ; 8.854  ;
+; SW[5]      ; VGA_R[2]    ; 8.101 ; 7.943 ; 8.629  ; 8.475  ;
+; SW[5]      ; VGA_R[3]    ; 8.269 ; 8.189 ; 8.912  ; 8.822  ;
++------------+-------------+-------+-------+--------+--------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 8.505 ; 8.371 ; 9.099 ; 8.956 ;
+; SW[4]      ; VGA_B[1]    ; 8.308 ; 8.149 ; 8.909 ; 8.691 ;
+; SW[4]      ; VGA_B[2]    ; 8.029 ; 7.903 ; 8.567 ; 8.441 ;
+; SW[4]      ; VGA_B[3]    ; 7.809 ; 7.683 ; 8.354 ; 8.267 ;
+; SW[4]      ; VGA_G[0]    ; 9.056 ; 8.936 ; 9.698 ; 9.551 ;
+; SW[4]      ; VGA_G[1]    ; 7.538 ; 7.459 ; 8.104 ; 8.016 ;
+; SW[4]      ; VGA_G[2]    ; 8.515 ; 8.402 ; 9.121 ; 9.001 ;
+; SW[4]      ; VGA_G[3]    ; 7.770 ; 7.674 ; 8.371 ; 8.200 ;
+; SW[4]      ; VGA_R[0]    ; 9.357 ; 9.236 ; 9.971 ; 9.823 ;
+; SW[4]      ; VGA_R[1]    ; 8.194 ; 8.022 ; 8.761 ; 8.580 ;
+; SW[4]      ; VGA_R[2]    ; 8.350 ; 8.200 ; 8.920 ; 8.761 ;
+; SW[4]      ; VGA_R[3]    ; 7.815 ; 7.795 ; 8.447 ; 8.280 ;
+; SW[5]      ; VGA_B[0]    ; 7.485 ; 7.350 ; 8.004 ; 7.899 ;
+; SW[5]      ; VGA_B[1]    ; 8.252 ; 8.083 ; 8.766 ; 8.588 ;
+; SW[5]      ; VGA_B[2]    ; 7.423 ; 7.363 ; 8.002 ; 7.863 ;
+; SW[5]      ; VGA_B[3]    ; 7.717 ; 7.604 ; 8.306 ; 8.184 ;
+; SW[5]      ; VGA_G[0]    ; 7.526 ; 7.382 ; 8.048 ; 7.936 ;
+; SW[5]      ; VGA_G[1]    ; 7.862 ; 7.809 ; 8.431 ; 8.333 ;
+; SW[5]      ; VGA_G[2]    ; 7.578 ; 7.443 ; 8.106 ; 7.962 ;
+; SW[5]      ; VGA_G[3]    ; 8.201 ; 8.100 ; 8.810 ; 8.650 ;
+; SW[5]      ; VGA_R[0]    ; 7.685 ; 7.540 ; 8.208 ; 8.095 ;
+; SW[5]      ; VGA_R[1]    ; 8.250 ; 8.079 ; 8.756 ; 8.591 ;
+; SW[5]      ; VGA_R[2]    ; 7.806 ; 7.645 ; 8.316 ; 8.215 ;
+; SW[5]      ; VGA_R[3]    ; 7.928 ; 7.894 ; 8.507 ; 8.436 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.126 ; 3.126 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.734 ; 3.734 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.372 ; 3.372 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.382 ; 3.382 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.652 ; 3.652 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.126 ; 3.126 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.372 ; 3.372 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.146 ; 3.146 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.333 ; 3.333 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.748 ; 3.748 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.748 ; 3.748 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.754 ; 3.754 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.738 ; 3.738 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.744 ; 3.744 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.754 ; 3.754 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.734 ; 3.734 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.126 ; 3.126 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.419 ; 2.419 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.002 ; 3.002 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.655 ; 2.655 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.665 ; 2.665 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.924 ; 2.924 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.419 ; 2.419 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.655 ; 2.655 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.439 ; 2.439 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.617 ; 2.617 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.016 ; 3.016 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.016 ; 3.016 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.022 ; 3.022 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.006 ; 3.006 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.012 ; 3.012 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.022 ; 3.022 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.002 ; 3.002 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.419 ; 2.419 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.054     ; 3.156     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.701     ; 3.803     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.285     ; 3.387     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.295     ; 3.397     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.569     ; 3.671     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.054     ; 3.156     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.285     ; 3.387     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.074     ; 3.176     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.246     ; 3.348     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.716     ; 3.818     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.716     ; 3.818     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.721     ; 3.823     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.706     ; 3.808     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.711     ; 3.813     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.721     ; 3.823     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.701     ; 3.803     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.054     ; 3.156     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.448     ; 2.544     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.069     ; 3.165     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.670     ; 2.766     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.680     ; 2.776     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.942     ; 3.038     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.448     ; 2.544     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.670     ; 2.766     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.468     ; 2.564     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.632     ; 2.728     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.084     ; 3.180     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.084     ; 3.180     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.089     ; 3.185     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.074     ; 3.170     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.079     ; 3.175     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.089     ; 3.185     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.069     ; 3.165     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.448     ; 2.544     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 11.193 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.193                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 6.588        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.605        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.280                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.106        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 4.174        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.322                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.070        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.469                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 6.322        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.147        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.517                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 6.523        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.994        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.541                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 6.440        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.101        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.550                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.250        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.300        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.569                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 6.354        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 5.215        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.612                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 6.676        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.936        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.676                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 6.301        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 5.375        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.691                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 6.649        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 5.042        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.721                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 6.833        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.888        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.746                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 6.490        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 5.256        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.748                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 6.951        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.797        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.772                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 6.771        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 5.001        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.846                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.100        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.746        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.870                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.618        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.977                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 6.897        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 5.080        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.004                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.253        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.751        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.012                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 6.465        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.547        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.025                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 6.954        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.071        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.088                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 6.313        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.775        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.113                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.128        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.985        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.128                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 6.972        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.156        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.139                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.123        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 5.016        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.160                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 6.972        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 5.188        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.202                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 6.680        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.522        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.258                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.262        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 4.996        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.267                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.118        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 5.149        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.273                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.121        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 5.152        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.287                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.147        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.140        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.360                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.264        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.096        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.365                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.267        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 5.098        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.415                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.120        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 5.295        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.429                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 6.969        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.460        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.446                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.120        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.326        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.522                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.108        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.414        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.522                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 6.797        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.725        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.575                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.126        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.449        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.060                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.265        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.795        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                                        ;
++-----------+-----------------+-----------------------------------------------------+------+
+; Fmax      ; Restricted Fmax ; Clock Name                                          ; Note ;
++-----------+-----------------+-----------------------------------------------------+------+
+; 186.6 MHz ; 186.6 MHz       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;      ;
+; 193.5 MHz ; 193.5 MHz       ; CLOCK_50                                            ;      ;
++-----------+-----------------+-----------------------------------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup Summary                                           ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.283 ; -5.821        ;
+; CLOCK_50                                            ; 14.832 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold Summary                                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.298 ; 0.000         ;
+; CLOCK_50                                            ; 0.312 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery Summary                                        ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.835 ; -178.452      ;
+; CLOCK_50                                            ; 13.489 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal Summary                                        ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 1.418 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.617 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary                            ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.739 ; 0.000         ;
+; CLOCK_50                                            ; 9.561 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                             ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.283 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.101      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.241 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.057      ;
+; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.018      ;
+; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.018      ;
+; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.018      ;
+; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.018      ;
+; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.018      ;
+; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.018      ;
+; -0.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.018      ;
+; -0.185 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.199     ; 2.001      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.840      ;
+; -0.001 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.819      ;
+; 0.078  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 2.058      ;
+; 0.084  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.875     ; 2.056      ;
+; 0.084  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.875     ; 2.056      ;
+; 0.084  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.875     ; 2.056      ;
+; 0.084  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.875     ; 2.056      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.085  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 1.733      ;
+; 0.156  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.979      ;
+; 0.156  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.979      ;
+; 0.156  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.979      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.359  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 1.757      ;
+; 0.497  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 1.639      ;
+; 0.497  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 1.639      ;
+; 0.497  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 1.639      ;
+; 2.641  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.372     ; 5.002      ;
+; 2.659  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.372     ; 4.984      ;
+; 2.683  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.386     ; 4.946      ;
+; 2.706  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.386     ; 4.923      ;
+; 2.723  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.373     ; 4.919      ;
+; 2.723  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.373     ; 4.919      ;
+; 2.723  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.373     ; 4.919      ;
+; 2.723  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.373     ; 4.919      ;
+; 2.723  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.373     ; 4.919      ;
+; 2.723  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.373     ; 4.919      ;
+; 2.723  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.373     ; 4.919      ;
+; 2.733  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.372     ; 4.910      ;
+; 2.737  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.374     ; 4.904      ;
+; 2.741  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.373     ; 4.901      ;
+; 2.741  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.373     ; 4.901      ;
+; 2.741  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.373     ; 4.901      ;
+; 2.741  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.373     ; 4.901      ;
+; 2.741  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.373     ; 4.901      ;
+; 2.741  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.373     ; 4.901      ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                              ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                       ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 14.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 4.490      ;
+; 14.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 4.457      ;
+; 15.015 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 4.307      ;
+; 15.090 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 4.232      ;
+; 15.132 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 4.190      ;
+; 15.273 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 4.049      ;
+; 15.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 3.948      ;
+; 15.429 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 3.893      ;
+; 15.476 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 3.846      ;
+; 15.552 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 3.770      ;
+; 15.601 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 3.721      ;
+; 15.629 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 3.693      ;
+; 15.701 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 3.621      ;
+; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.098      ;
+; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.098      ;
+; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.098      ;
+; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.098      ;
+; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.098      ;
+; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.098      ;
+; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.098      ;
+; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.098      ;
+; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.098      ;
+; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.098      ;
+; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.098      ;
+; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.098      ;
+; 15.866 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.098      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.090      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.090      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.090      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.090      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.090      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.090      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.090      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.090      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.090      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.090      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.090      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.090      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.090      ;
+; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.019      ;
+; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.019      ;
+; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.019      ;
+; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.019      ;
+; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.019      ;
+; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.019      ;
+; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.019      ;
+; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.019      ;
+; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.019      ;
+; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.019      ;
+; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.019      ;
+; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.019      ;
+; 15.945 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.019      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.951      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.951      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.951      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.951      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.951      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.951      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.951      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.951      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.951      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.951      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.951      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.951      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.951      ;
+; 16.028 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.942      ;
+; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.924      ;
+; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.924      ;
+; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.924      ;
+; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.924      ;
+; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.924      ;
+; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.924      ;
+; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.924      ;
+; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.924      ;
+; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.924      ;
+; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.924      ;
+; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.924      ;
+; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.924      ;
+; 16.040 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 3.924      ;
+; 16.078 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 3.244      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
+; 16.137 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 3.826      ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.298 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.511      ;
+; 0.298 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.301 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 0.511      ;
+; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
+; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
+; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
+; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
+; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.315 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.355      ; 0.814      ;
+; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.519      ;
+; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.519      ;
+; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.519      ;
+; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.338      ; 0.832      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.336      ; 0.832      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 0.538      ;
+; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.336      ; 0.836      ;
+; 0.332 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.338      ; 0.839      ;
+; 0.333 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.531      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.537      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.537      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CS_N[0]                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.537      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_done                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.539      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.338      ; 0.847      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CAS_N                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|CAS_N                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|RAS_N                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[11]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[8]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[14]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[12]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.540      ;
+; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.552      ;
+; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.540      ;
+; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.540      ;
+; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.540      ;
+; 0.342 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.541      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.545      ;
+; 0.348 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[3]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.547      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                       ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.320 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.519      ;
+; 0.321 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.519      ;
+; 0.341 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.519      ;
+; 0.341 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.539      ;
+; 0.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.543      ;
+; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.546      ;
+; 0.364 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.563      ;
+; 0.471 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.669      ;
+; 0.495 ; ps2:inst6|clk_div[6]                                  ; ps2:inst6|clk_div[6]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.693      ;
+; 0.495 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.694      ;
+; 0.498 ; ps2:inst6|clk_div[2]                                  ; ps2:inst6|clk_div[2]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.696      ;
+; 0.498 ; ps2:inst6|clk_div[4]                                  ; ps2:inst6|clk_div[4]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.696      ;
+; 0.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.697      ;
+; 0.500 ; ps2:inst6|clk_div[3]                                  ; ps2:inst6|clk_div[3]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.500 ; ps2:inst6|clk_div[5]                                  ; ps2:inst6|clk_div[5]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.500 ; ps2:inst6|clk_div[7]                                  ; ps2:inst6|clk_div[7]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.501 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.699      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.502 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.701      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.701      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.702      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.702      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.703      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.703      ;
+; 0.505 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.704      ;
+; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.703      ;
+; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.704      ;
+; 0.506 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.704      ;
+; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.516 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.521 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.719      ;
+; 0.524 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.723      ;
+; 0.526 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.725      ;
+; 0.529 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.728      ;
+; 0.532 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.731      ;
+; 0.533 ; ps2:inst6|clk_div[8]                                  ; ps2:inst6|clk_div[8]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.711      ;
+; 0.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.747      ;
+; 0.557 ; ps2:inst6|clk_div[7]                                  ; ps2:inst6|clk_div[8]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.246      ; 0.947      ;
+; 0.636 ; ps2:inst6|clk_div[6]                                  ; ps2:inst6|clk_div[8]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.246      ; 1.026      ;
+; 0.637 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.836      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.835 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.815      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.834 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.816      ;
+; -0.791 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.855      ;
+; -0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.974     ; 2.856      ;
+; -0.694 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.214     ; 2.495      ;
+; -0.694 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.214     ; 2.495      ;
+; -0.694 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.214     ; 2.495      ;
+; -0.694 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.214     ; 2.495      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.494      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.494      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.494      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.494      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.494      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.494      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.493      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.494      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.493      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.493      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.494      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.494      ;
+; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.493      ;
+; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.493      ;
+; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.493      ;
+; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.493      ;
+; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.493      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.499      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.499      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.499      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.499      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.499      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.499      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.499      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.499      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.492      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.212     ; 2.484      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.499      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.499      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.499      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.499      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.499      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.681 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.498      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.498      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.498      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.197     ; 2.498      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.195     ; 2.500      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.195     ; 2.500      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.195     ; 2.500      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.195     ; 2.500      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.195     ; 2.500      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.195     ; 2.500      ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                     ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 13.489 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.692     ; 5.834      ;
+; 13.498 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.692     ; 5.825      ;
+; 13.578 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.692     ; 5.745      ;
+; 13.635 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 5.687      ;
+; 13.705 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.692     ; 5.618      ;
+; 13.760 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 5.562      ;
+; 13.760 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 5.562      ;
+; 13.769 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 5.553      ;
+; 13.837 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 5.485      ;
+; 13.848 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 5.474      ;
+; 13.962 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 5.360      ;
+; 13.967 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 5.355      ;
+; 13.971 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 5.351      ;
+; 13.974 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 5.348      ;
+; 14.048 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 5.274      ;
+; 14.178 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.693     ; 5.144      ;
+; 14.568 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.692     ; 4.755      ;
+; 14.622 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.698     ; 4.695      ;
+; 14.673 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.692     ; 4.650      ;
+; 14.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.692     ; 4.489      ;
+; 14.842 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.692     ; 4.481      ;
+; 14.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.692     ; 4.449      ;
+; 14.923 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.692     ; 4.400      ;
+; 14.969 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.692     ; 4.354      ;
+; 15.048 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.692     ; 4.275      ;
+; 15.124 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.692     ; 4.199      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.727 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.234      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.736 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.225      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.816 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.145      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.873 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.087      ;
+; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.018      ;
+; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.018      ;
+; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.018      ;
+; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.018      ;
+; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.018      ;
+; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.018      ;
+; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.018      ;
+; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.018      ;
+; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.018      ;
+; 15.943 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.018      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                    ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.618      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.488 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.688      ;
+; 1.948 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 2.153      ;
+; 1.948 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 2.153      ;
+; 1.948 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 2.153      ;
+; 1.948 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 2.153      ;
+; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.168      ;
+; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.168      ;
+; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.168      ;
+; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.168      ;
+; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.168      ;
+; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.168      ;
+; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.168      ;
+; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.168      ;
+; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.168      ;
+; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.168      ;
+; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.168      ;
+; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.168      ;
+; 1.962 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.168      ;
+; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.432      ;
+; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.432      ;
+; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.432      ;
+; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.432      ;
+; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.432      ;
+; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.432      ;
+; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.432      ;
+; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.432      ;
+; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.432      ;
+; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.432      ;
+; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.432      ;
+; 2.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.432      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.233 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.433      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.248 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.448      ;
+; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.538      ;
+; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.538      ;
+; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.538      ;
+; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.538      ;
+; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.538      ;
+; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.538      ;
+; 2.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 2.538      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 3.617 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.427     ; 2.334      ;
+; 3.627 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.436     ; 2.335      ;
+; 3.637 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.327      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.341      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.341      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.341      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.341      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.341      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.341      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.341      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.331      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.331      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.447     ; 2.336      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.447     ; 2.336      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.331      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.331      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.331      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.331      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.331      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.331      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.338      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.338      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.338      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.338      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.340      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.340      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.340      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.454     ; 2.331      ;
+; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.340      ;
+; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.340      ;
+; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.340      ;
+; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.340      ;
+; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.340      ;
+; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.340      ;
+; 3.653 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.340      ;
+; 3.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.480     ; 2.327      ;
+; 3.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.480     ; 2.327      ;
+; 3.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.480     ; 2.327      ;
+; 3.667 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.481     ; 2.330      ;
+; 3.667 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.481     ; 2.330      ;
+; 3.667 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.481     ; 2.330      ;
+; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.473     ; 2.339      ;
+; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.473     ; 2.339      ;
+; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.473     ; 2.339      ;
+; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.473     ; 2.339      ;
+; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.473     ; 2.339      ;
+; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.473     ; 2.339      ;
+; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.473     ; 2.339      ;
+; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.473     ; 2.339      ;
+; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.473     ; 2.339      ;
+; 3.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.473     ; 2.339      ;
+; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.470     ; 2.343      ;
+; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.470     ; 2.343      ;
+; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.470     ; 2.343      ;
+; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.470     ; 2.343      ;
+; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.476     ; 2.337      ;
+; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.476     ; 2.337      ;
+; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.476     ; 2.337      ;
+; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.476     ; 2.337      ;
+; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.476     ; 2.337      ;
+; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.470     ; 2.343      ;
+; 3.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.470     ; 2.343      ;
+; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.481     ; 2.334      ;
+; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.481     ; 2.334      ;
+; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.481     ; 2.334      ;
+; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.481     ; 2.334      ;
+; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.481     ; 2.334      ;
+; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.481     ; 2.334      ;
+; 3.671 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.481     ; 2.334      ;
+; 3.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.479     ; 2.338      ;
+; 3.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.479     ; 2.338      ;
+; 3.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.479     ; 2.338      ;
+; 3.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.479     ; 2.338      ;
+; 3.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.479     ; 2.338      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                         ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.739 ; 3.955        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ;
+; 3.739 ; 3.955        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ;
+; 3.739 ; 3.955        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ;
+; 3.739 ; 3.955        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ;
+; 3.739 ; 3.955        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ;
+; 3.740 ; 3.970        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.740 ; 3.970        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ;
+; 3.741 ; 3.971        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.741 ; 3.971        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]                                                                                                                          ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]                                                                                                                          ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0]                                                                                                                           ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13]                                                                                                                          ;
+; 3.750 ; 3.966        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                           ;
+; 3.750 ; 3.966        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ;
+; 3.750 ; 3.966        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                    ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; 9.561 ; 9.745        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ;
+; 9.584 ; 9.768        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                  ;
+; 9.584 ; 9.768        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[8]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[0]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[1]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[2]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[3]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[4]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[5]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[6]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[7]                                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 3.696 ; 4.224 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 3.696 ; 4.224 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 3.167 ; 3.642 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.754 ; 4.201 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.172 ; 3.670 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.318 ; 3.772 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.273 ; 3.722 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.502 ; 3.956 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.251 ; 3.690 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.149 ; 3.584 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.474 ; 3.928 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.005 ; 3.435 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.146 ; 3.592 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.188 ; 3.625 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.184 ; 3.626 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.899 ; 3.344 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.171 ; 3.606 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.089 ; 3.553 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.754 ; 4.201 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.554 ; -2.058 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.554 ; -2.072 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.633 ; -2.058 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -2.286 ; -2.717 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; -2.551 ; -3.034 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; -2.724 ; -3.169 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; -2.682 ; -3.122 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; -2.902 ; -3.347 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; -2.623 ; -3.050 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; -2.551 ; -2.973 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -2.875 ; -3.321 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -2.387 ; -2.805 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -2.535 ; -2.972 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -2.590 ; -3.013 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; -2.586 ; -3.014 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -2.286 ; -2.717 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -2.573 ; -2.995 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -2.473 ; -2.921 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -3.144 ; -3.582 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 7.443  ; 7.283  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 5.824  ; 5.753  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 7.443  ; 7.283  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 6.089  ; 5.925  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 6.089  ; 5.925  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.055  ; 5.138  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.447  ; 3.308  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.257  ; 3.115  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.414  ; 3.253  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.413  ; 3.264  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.225  ; 3.093  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.268  ; 3.137  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.008  ; 2.891  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.073  ; 2.949  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.447  ; 3.308  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.235  ; 3.084  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.429  ; 3.275  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.048  ; 2.930  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.030  ; 2.910  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.035  ; 2.917  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.038  ; 2.923  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.004  ; 2.884  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.343  ; 3.182  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 6.693  ; 6.389  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 4.860  ; 4.672  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 4.972  ; 4.764  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.039  ; 4.844  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 6.693  ; 6.389  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.204  ; 5.004  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.033  ; 4.836  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 5.159  ; 4.973  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.378  ; 5.243  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 4.992  ; 4.867  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 4.674  ; 4.602  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 4.892  ; 4.717  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 4.613  ; 4.514  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 4.770  ; 4.635  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.877  ; 4.758  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 4.802  ; 4.627  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.131  ; 4.996  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.240  ; 3.114  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.182  ; 3.050  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.559  ; 3.430  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.236  ; 4.872  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.448 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.595 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 5.693  ; 5.620  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 5.693  ; 5.620  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 7.249  ; 7.089  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 5.947  ; 5.785  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 5.947  ; 5.785  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 4.950  ; 5.034  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.638  ; 2.521  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 2.877  ; 2.736  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.029  ; 2.869  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.028  ; 2.879  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 2.847  ; 2.715  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 2.889  ; 2.758  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 2.638  ; 2.521  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 2.701  ; 2.577  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.060  ; 2.921  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 2.855  ; 2.706  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.043  ; 2.890  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 2.677  ; 2.559  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.659  ; 2.539  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 2.664  ; 2.546  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 2.667  ; 2.552  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 2.633  ; 2.513  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 2.958  ; 2.799  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 3.638  ; 3.475  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 3.638  ; 3.475  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 3.906  ; 3.762  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 3.983  ; 3.854  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 5.728  ; 5.385  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 4.132  ; 3.977  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 3.973  ; 3.834  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 3.934  ; 3.769  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 4.127  ; 3.977  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 3.846  ; 3.735  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 3.653  ; 3.504  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 3.944  ; 3.805  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 3.798  ; 3.689  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 3.773  ; 3.639  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.117  ; 4.001  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 3.754  ; 3.577  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 4.087  ; 3.895  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 2.860  ; 2.733  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 2.804  ; 2.673  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.166  ; 3.037  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 4.857  ; 4.494  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.777 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.922 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 8.165 ; 7.985 ; 8.668 ; 8.488 ;
+; SW[4]      ; VGA_B[1]    ; 8.501 ; 8.282 ; 8.985 ; 8.720 ;
+; SW[4]      ; VGA_B[2]    ; 7.664 ; 7.519 ; 8.155 ; 8.015 ;
+; SW[4]      ; VGA_B[3]    ; 7.757 ; 7.589 ; 8.277 ; 8.109 ;
+; SW[4]      ; VGA_G[0]    ; 8.739 ; 8.624 ; 9.277 ; 9.079 ;
+; SW[4]      ; VGA_G[1]    ; 7.921 ; 7.834 ; 8.446 ; 8.359 ;
+; SW[4]      ; VGA_G[2]    ; 8.245 ; 8.097 ; 8.740 ; 8.523 ;
+; SW[4]      ; VGA_G[3]    ; 8.251 ; 8.079 ; 8.757 ; 8.603 ;
+; SW[4]      ; VGA_R[0]    ; 9.036 ; 8.850 ; 9.540 ; 9.374 ;
+; SW[4]      ; VGA_R[1]    ; 8.457 ; 8.277 ; 8.940 ; 8.729 ;
+; SW[4]      ; VGA_R[2]    ; 8.062 ; 7.851 ; 8.524 ; 8.321 ;
+; SW[4]      ; VGA_R[3]    ; 7.892 ; 7.767 ; 8.411 ; 8.286 ;
+; SW[5]      ; VGA_B[0]    ; 7.839 ; 7.659 ; 8.328 ; 8.148 ;
+; SW[5]      ; VGA_B[1]    ; 7.920 ; 7.697 ; 8.375 ; 8.144 ;
+; SW[5]      ; VGA_B[2]    ; 7.552 ; 7.412 ; 8.017 ; 7.853 ;
+; SW[5]      ; VGA_B[3]    ; 7.427 ; 7.259 ; 7.937 ; 7.769 ;
+; SW[5]      ; VGA_G[0]    ; 8.203 ; 8.047 ; 8.677 ; 8.513 ;
+; SW[5]      ; VGA_G[1]    ; 7.592 ; 7.505 ; 8.070 ; 7.983 ;
+; SW[5]      ; VGA_G[2]    ; 7.739 ; 7.564 ; 8.209 ; 8.026 ;
+; SW[5]      ; VGA_G[3]    ; 7.925 ; 7.751 ; 8.416 ; 8.262 ;
+; SW[5]      ; VGA_R[0]    ; 8.705 ; 8.521 ; 9.166 ; 9.000 ;
+; SW[5]      ; VGA_R[1]    ; 7.877 ; 7.695 ; 8.329 ; 8.139 ;
+; SW[5]      ; VGA_R[2]    ; 7.525 ; 7.317 ; 7.989 ; 7.786 ;
+; SW[5]      ; VGA_R[3]    ; 7.670 ; 7.563 ; 8.211 ; 8.086 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 7.911 ; 7.732 ; 8.368 ; 8.183 ;
+; SW[4]      ; VGA_B[1]    ; 7.735 ; 7.516 ; 8.240 ; 7.972 ;
+; SW[4]      ; VGA_B[2]    ; 7.468 ; 7.300 ; 7.925 ; 7.757 ;
+; SW[4]      ; VGA_B[3]    ; 7.262 ; 7.095 ; 7.728 ; 7.596 ;
+; SW[4]      ; VGA_G[0]    ; 8.400 ; 8.242 ; 8.918 ; 8.731 ;
+; SW[4]      ; VGA_G[1]    ; 7.023 ; 6.887 ; 7.502 ; 7.360 ;
+; SW[4]      ; VGA_G[2]    ; 7.912 ; 7.722 ; 8.414 ; 8.213 ;
+; SW[4]      ; VGA_G[3]    ; 7.228 ; 7.085 ; 7.743 ; 7.540 ;
+; SW[4]      ; VGA_R[0]    ; 8.688 ; 8.528 ; 9.168 ; 8.979 ;
+; SW[4]      ; VGA_R[1]    ; 7.633 ; 7.426 ; 8.112 ; 7.899 ;
+; SW[4]      ; VGA_R[2]    ; 7.764 ; 7.564 ; 8.237 ; 8.031 ;
+; SW[4]      ; VGA_R[3]    ; 7.272 ; 7.212 ; 7.816 ; 7.625 ;
+; SW[5]      ; VGA_B[0]    ; 6.968 ; 6.787 ; 7.407 ; 7.254 ;
+; SW[5]      ; VGA_B[1]    ; 7.675 ; 7.441 ; 8.120 ; 7.880 ;
+; SW[5]      ; VGA_B[2]    ; 6.912 ; 6.808 ; 7.420 ; 7.238 ;
+; SW[5]      ; VGA_B[3]    ; 7.184 ; 7.024 ; 7.673 ; 7.507 ;
+; SW[5]      ; VGA_G[0]    ; 7.004 ; 6.819 ; 7.445 ; 7.289 ;
+; SW[5]      ; VGA_G[1]    ; 7.305 ; 7.189 ; 7.799 ; 7.635 ;
+; SW[5]      ; VGA_G[2]    ; 7.064 ; 6.849 ; 7.525 ; 7.304 ;
+; SW[5]      ; VGA_G[3]    ; 7.637 ; 7.490 ; 8.116 ; 7.920 ;
+; SW[5]      ; VGA_R[0]    ; 7.154 ; 6.967 ; 7.597 ; 7.439 ;
+; SW[5]      ; VGA_R[1]    ; 7.675 ; 7.468 ; 8.112 ; 7.911 ;
+; SW[5]      ; VGA_R[2]    ; 7.264 ; 7.057 ; 7.706 ; 7.553 ;
+; SW[5]      ; VGA_R[3]    ; 7.371 ; 7.295 ; 7.858 ; 7.747 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.088 ; 3.075 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.649 ; 3.636 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.313 ; 3.300 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.323 ; 3.310 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.567 ; 3.554 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.088 ; 3.075 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.313 ; 3.300 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.108 ; 3.095 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.282 ; 3.269 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.663 ; 3.650 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.663 ; 3.650 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.669 ; 3.656 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.653 ; 3.640 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.659 ; 3.646 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.669 ; 3.656 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.649 ; 3.636 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.088 ; 3.075 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.221 ; 2.221 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.760 ; 2.760 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.437 ; 2.437 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.447 ; 2.447 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.682 ; 2.682 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.221 ; 2.221 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.437 ; 2.437 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.241 ; 2.241 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.408 ; 2.408 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.775 ; 2.775 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.775 ; 2.775 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.780 ; 2.780 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.765 ; 2.765 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.770 ; 2.770 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.780 ; 2.780 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.760 ; 2.760 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.221 ; 2.221 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.096     ; 3.096     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.676     ; 3.676     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.303     ; 3.303     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.313     ; 3.313     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.553     ; 3.553     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.096     ; 3.096     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.303     ; 3.303     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.116     ; 3.116     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.263     ; 3.263     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.688     ; 3.688     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.688     ; 3.688     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.696     ; 3.696     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.678     ; 3.678     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.686     ; 3.686     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.696     ; 3.696     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.676     ; 3.676     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.096     ; 3.096     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.229     ; 2.417     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.786     ; 2.974     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.428     ; 2.616     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.438     ; 2.626     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.668     ; 2.856     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.229     ; 2.417     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.428     ; 2.616     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.249     ; 2.437     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.390     ; 2.578     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.798     ; 2.986     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.798     ; 2.986     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.806     ; 2.994     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.788     ; 2.976     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.796     ; 2.984     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.806     ; 2.994     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.786     ; 2.974     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.229     ; 2.417     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 11.719 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.719                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 6.738        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.981        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.770                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.197        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 4.573        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.810                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.473        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.947                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 6.501        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.446        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.997                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 6.603        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.394        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.009                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 6.687        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.322        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.012                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.336        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.676        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.042                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 6.525        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 5.517        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.055                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 6.814        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 5.241        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.120                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 6.470        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 5.650        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.160                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 6.963        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.197        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.161                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 6.794        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 5.367        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.183                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.060        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 5.123        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.207                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 6.659        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 5.548        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.239                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 6.911        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 5.328        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.273                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.936        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.276                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.200        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 5.076        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.375                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.023        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 5.352        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.410                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 6.634        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.776        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.420                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 5.081        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.428                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.062        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.366        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.490                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 6.469        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 6.021        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.534                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.079        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.455        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.542                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.233        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.309        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.548                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.213        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 5.335        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.570                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.080        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 5.490        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.576                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 6.818        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.758        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.658                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.209        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 5.449        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.661                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.211        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 5.450        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.672                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.347        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.325        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.692                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.246        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.446        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.732                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.348        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.384        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.747                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.351        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 5.396        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.783                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.210        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 5.573        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.802                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.077        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.725        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.830                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.212        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.618        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.894                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 6.935        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.959        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.898                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.216        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.682        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.903                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.223        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.680        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.346                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.349        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.997        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup Summary                                           ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 1.209  ; 0.000         ;
+; CLOCK_50                                            ; 16.656 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold Summary                                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.169 ; 0.000         ;
+; CLOCK_50                                            ; 0.187 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery Summary                                        ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.780  ; 0.000         ;
+; CLOCK_50                                            ; 15.649 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal Summary                                        ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 0.849 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 2.409 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary                            ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.746 ; 0.000         ;
+; CLOCK_50                                            ; 9.266 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 1.209 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.305      ;
+; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.255      ;
+; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.255      ;
+; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.255      ;
+; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.255      ;
+; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.255      ;
+; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.255      ;
+; 1.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.255      ;
+; 1.269 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.243      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.270 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.495     ; 1.242      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.389 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.124      ;
+; 1.403 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.110      ;
+; 1.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.276      ;
+; 1.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.302     ; 1.272      ;
+; 1.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.302     ; 1.272      ;
+; 1.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.302     ; 1.272      ;
+; 1.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.302     ; 1.272      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.496 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.018      ;
+; 1.527 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.174      ;
+; 1.527 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.174      ;
+; 1.527 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.174      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.612 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.079      ;
+; 1.714 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 0.988      ;
+; 1.714 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 0.988      ;
+; 1.714 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 0.988      ;
+; 4.524 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.232     ; 3.251      ;
+; 4.537 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.232     ; 3.238      ;
+; 4.575 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.232     ; 3.200      ;
+; 4.597 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.232     ; 3.178      ;
+; 4.618 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.218     ; 3.171      ;
+; 4.623 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.036     ; 3.348      ;
+; 4.629 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.038     ; 3.340      ;
+; 4.636 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.036     ; 3.335      ;
+; 4.642 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.038     ; 3.327      ;
+; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.220     ; 3.134      ;
+; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.220     ; 3.134      ;
+; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.220     ; 3.134      ;
+; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.220     ; 3.134      ;
+; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.220     ; 3.134      ;
+; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.220     ; 3.134      ;
+; 4.653 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.220     ; 3.134      ;
+; 4.661 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.220     ; 3.126      ;
+; 4.674 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.036     ; 3.297      ;
+; 4.680 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.038     ; 3.289      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                              ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                       ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 16.656 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.859      ;
+; 16.664 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.851      ;
+; 16.767 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.748      ;
+; 16.789 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.726      ;
+; 16.805 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.710      ;
+; 16.879 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.636      ;
+; 16.944 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.571      ;
+; 16.975 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.540      ;
+; 17.015 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.500      ;
+; 17.044 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.471      ;
+; 17.081 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.434      ;
+; 17.098 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.417      ;
+; 17.133 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.382      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.684      ;
+; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.622      ;
+; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.622      ;
+; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.622      ;
+; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.622      ;
+; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.622      ;
+; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.622      ;
+; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.622      ;
+; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.622      ;
+; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.622      ;
+; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.622      ;
+; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.622      ;
+; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.622      ;
+; 17.353 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.622      ;
+; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.619      ;
+; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.619      ;
+; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.619      ;
+; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.619      ;
+; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.619      ;
+; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.619      ;
+; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.619      ;
+; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.619      ;
+; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.619      ;
+; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.619      ;
+; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.619      ;
+; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.619      ;
+; 17.356 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.619      ;
+; 17.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 2.157      ;
+; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.557      ;
+; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.557      ;
+; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.557      ;
+; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.557      ;
+; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.557      ;
+; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.557      ;
+; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.557      ;
+; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.557      ;
+; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.557      ;
+; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.557      ;
+; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.557      ;
+; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.557      ;
+; 17.418 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.557      ;
+; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.512      ;
+; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.512      ;
+; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.512      ;
+; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.512      ;
+; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.512      ;
+; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.512      ;
+; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.512      ;
+; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.512      ;
+; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.512      ;
+; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.512      ;
+; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.512      ;
+; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.512      ;
+; 17.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.512      ;
+; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.484      ;
+; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.484      ;
+; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.484      ;
+; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.484      ;
+; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.484      ;
+; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.484      ;
+; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.484      ;
+; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.484      ;
+; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.484      ;
+; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.484      ;
+; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.484      ;
+; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.484      ;
+; 17.491 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.484      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
+; 17.544 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.033     ; 2.430      ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.169 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.215      ; 0.468      ;
+; 0.172 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.494      ;
+; 0.174 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.497      ;
+; 0.174 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.496      ;
+; 0.176 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.499      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.186 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.509      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.315      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.315      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.313      ;
+; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[14]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_done                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.315      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.315      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CAS_N                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|CAS_N                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|RAS_N                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[11]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.315      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[8]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.315      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.315      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[12]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.316      ;
+; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.316      ;
+; 0.197 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.316      ;
+; 0.197 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.316      ;
+; 0.197 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.316      ;
+; 0.198 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.317      ;
+; 0.202 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[3]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.321      ;
+; 0.202 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.329      ;
+; 0.203 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CS_N[0]                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.322      ;
+; 0.204 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.324      ;
+; 0.205 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_done                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.325      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                       ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.187 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.307      ;
+; 0.194 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
+; 0.197 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.316      ;
+; 0.199 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.318      ;
+; 0.206 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.325      ;
+; 0.208 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.022      ; 0.314      ;
+; 0.216 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.336      ;
+; 0.272 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.391      ;
+; 0.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.413      ;
+; 0.294 ; ps2:inst6|clk_div[6]                                  ; ps2:inst6|clk_div[6]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.414      ;
+; 0.295 ; ps2:inst6|clk_div[2]                                  ; ps2:inst6|clk_div[2]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; ps2:inst6|clk_div[4]                                  ; ps2:inst6|clk_div[4]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.415      ;
+; 0.296 ; ps2:inst6|clk_div[3]                                  ; ps2:inst6|clk_div[3]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.416      ;
+; 0.296 ; ps2:inst6|clk_div[5]                                  ; ps2:inst6|clk_div[5]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.416      ;
+; 0.296 ; ps2:inst6|clk_div[7]                                  ; ps2:inst6|clk_div[7]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.416      ;
+; 0.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.416      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.299 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.418      ;
+; 0.299 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.418      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.418      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.418      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.418      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.418      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.418      ;
+; 0.300 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.419      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.419      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.419      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.419      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.419      ;
+; 0.301 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.420      ;
+; 0.301 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.420      ;
+; 0.301 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.420      ;
+; 0.302 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.422      ;
+; 0.304 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.424      ;
+; 0.304 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.424      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.428      ;
+; 0.309 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.428      ;
+; 0.311 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.430      ;
+; 0.311 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.431      ;
+; 0.315 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.435      ;
+; 0.315 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.435      ;
+; 0.318 ; ps2:inst6|clk_div[8]                                  ; ps2:inst6|clk_div[8]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.022      ; 0.424      ;
+; 0.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.438      ;
+; 0.327 ; ps2:inst6|clk_div[7]                                  ; ps2:inst6|clk_div[8]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.163      ; 0.574      ;
+; 0.329 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.449      ;
+; 0.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.487      ;
+; 0.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.488      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.780 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.842      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.781 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.840      ;
+; 0.816 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.353     ; 1.860      ;
+; 0.817 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.858      ;
+; 0.852 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.504     ; 1.651      ;
+; 0.852 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.504     ; 1.651      ;
+; 0.852 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.504     ; 1.651      ;
+; 0.852 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.504     ; 1.651      ;
+; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.649      ;
+; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.649      ;
+; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.649      ;
+; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.649      ;
+; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.649      ;
+; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.649      ;
+; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.648      ;
+; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.649      ;
+; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.648      ;
+; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.648      ;
+; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.649      ;
+; 0.857 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.649      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.648      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.648      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.648      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.648      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.648      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.643      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.493     ; 1.654      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.494     ; 1.653      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                              ;
++--------+-------------------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                             ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.491     ; 3.867      ;
+; 15.652 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.491     ; 3.864      ;
+; 15.714 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.491     ; 3.802      ;
+; 15.758 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 3.757      ;
+; 15.787 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.491     ; 3.729      ;
+; 15.840 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 3.675      ;
+; 15.840 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 3.675      ;
+; 15.843 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 3.672      ;
+; 15.900 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 3.615      ;
+; 15.905 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 3.610      ;
+; 15.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 3.545      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 3.542      ;
+; 15.975 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 3.540      ;
+; 15.978 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 3.537      ;
+; 16.034 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 3.481      ;
+; 16.109 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.492     ; 3.406      ;
+; 16.404 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.491     ; 3.112      ;
+; 16.447 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.491     ; 3.069      ;
+; 16.450 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.496     ; 3.061      ;
+; 16.538 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.491     ; 2.978      ;
+; 16.541 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.491     ; 2.975      ;
+; 16.578 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.491     ; 2.938      ;
+; 16.604 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.491     ; 2.912      ;
+; 16.635 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.491     ; 2.881      ;
+; 16.676 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.491     ; 2.840      ;
+; 16.757 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.491     ; 2.759      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.719      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.256 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.716      ;
+; 17.258 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.490     ; 2.259      ;
+; 17.275 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.490     ; 2.242      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.654      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.609      ;
+; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.581      ;
+; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.581      ;
+; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.581      ;
+; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.581      ;
+; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.581      ;
+; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.581      ;
+; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.581      ;
+; 17.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.581      ;
++--------+-------------------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                    ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.849 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 0.970      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 0.932 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.037      ; 1.053      ;
+; 1.182 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.040      ; 1.306      ;
+; 1.182 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.040      ; 1.306      ;
+; 1.182 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.040      ; 1.306      ;
+; 1.182 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.040      ; 1.306      ;
+; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.041      ; 1.311      ;
+; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.041      ; 1.311      ;
+; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.041      ; 1.311      ;
+; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.041      ; 1.311      ;
+; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.041      ; 1.311      ;
+; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.041      ; 1.311      ;
+; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.041      ; 1.311      ;
+; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.041      ; 1.311      ;
+; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.041      ; 1.311      ;
+; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.041      ; 1.311      ;
+; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.041      ; 1.311      ;
+; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.041      ; 1.311      ;
+; 1.186 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.041      ; 1.311      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.324 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.444      ;
+; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.473      ;
+; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.473      ;
+; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.473      ;
+; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.473      ;
+; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.473      ;
+; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.473      ;
+; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.473      ;
+; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.473      ;
+; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.473      ;
+; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.473      ;
+; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.473      ;
+; 1.347 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.473      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.367 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.487      ;
+; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.503      ;
+; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.503      ;
+; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.503      ;
+; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.503      ;
+; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.503      ;
+; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.503      ;
+; 1.383 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 1.503      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.007     ; 1.486      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.008     ; 1.491      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.483      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.018     ; 1.486      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.018     ; 1.486      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.494      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.494      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.494      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.494      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.494      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.494      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.494      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.488      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.488      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.488      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.488      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.492      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.492      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.018     ; 1.486      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.018     ; 1.486      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.018     ; 1.486      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.018     ; 1.486      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.018     ; 1.486      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.018     ; 1.486      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.493      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.022     ; 1.486      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.022     ; 1.486      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.021     ; 1.487      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.022     ; 1.486      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.022     ; 1.486      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.022     ; 1.486      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.021     ; 1.487      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.022     ; 1.486      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.022     ; 1.486      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.021     ; 1.487      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.022     ; 1.486      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.022     ; 1.486      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.022     ; 1.486      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.021     ; 1.487      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.021     ; 1.487      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.022     ; 1.486      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.022     ; 1.486      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.021     ; 1.487      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.021     ; 1.487      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.022     ; 1.486      ;
+; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.493      ;
+; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.493      ;
+; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.493      ;
+; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.493      ;
+; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.493      ;
+; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.493      ;
+; 2.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.493      ;
+; 2.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.035     ; 1.482      ;
+; 2.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.035     ; 1.482      ;
+; 2.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.035     ; 1.482      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.030     ; 1.491      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.030     ; 1.491      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.030     ; 1.491      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.030     ; 1.491      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.030     ; 1.491      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.030     ; 1.491      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.030     ; 1.491      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.030     ; 1.491      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.027     ; 1.494      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.027     ; 1.494      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.027     ; 1.494      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.027     ; 1.494      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.033     ; 1.488      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.033     ; 1.488      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.034     ; 1.487      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.034     ; 1.487      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.034     ; 1.487      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.034     ; 1.487      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.033     ; 1.488      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.034     ; 1.487      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.034     ; 1.487      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.034     ; 1.487      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.033     ; 1.488      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.033     ; 1.488      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.027     ; 1.494      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.027     ; 1.494      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.030     ; 1.491      ;
+; 2.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.030     ; 1.491      ;
+; 2.438 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.037     ; 1.485      ;
+; 2.438 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.037     ; 1.485      ;
+; 2.438 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.037     ; 1.485      ;
+; 2.440 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.033     ; 1.491      ;
+; 2.440 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.033     ; 1.491      ;
+; 2.440 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.033     ; 1.491      ;
+; 2.440 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.033     ; 1.491      ;
+; 2.440 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.033     ; 1.491      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                        ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]                                                                                                                             ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]                                                                                                                             ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]                                                                                                                             ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]                                                                                                                             ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]                                                                                                                              ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                                                           ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                                                                                                                            ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]                                                                                                                            ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]                                                                                                                            ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                                                                                                                            ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[11]                                                                                                                          ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4]                                                                                                                           ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD                                                                                                                                   ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                                                                                                                   ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]                                                                                                                           ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                    ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                    ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[0]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[1]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[2]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[3]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[4]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[5]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[6]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[7]                                  ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 2.313 ; 3.173 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 2.313 ; 3.173 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 2.020 ; 2.772 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.477 ; 3.286 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.145 ; 2.958 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.219 ; 2.968 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.199 ; 2.936 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.339 ; 3.104 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.171 ; 2.964 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.125 ; 2.875 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.319 ; 3.084 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.044 ; 2.800 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.117 ; 2.876 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.154 ; 2.906 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.149 ; 2.902 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 1.979 ; 2.735 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.143 ; 2.894 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.095 ; 2.869 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.477 ; 3.286 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -0.978 ; -1.819 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -0.978 ; -1.823 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.027 ; -1.819 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -1.578 ; -2.319 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; -1.739 ; -2.535 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; -1.827 ; -2.568 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; -1.810 ; -2.539 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; -1.943 ; -2.700 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; -1.762 ; -2.539 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; -1.733 ; -2.468 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -1.925 ; -2.682 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -1.640 ; -2.381 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -1.716 ; -2.467 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -1.761 ; -2.499 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; -1.756 ; -2.494 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -1.578 ; -2.319 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -1.751 ; -2.487 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -1.692 ; -2.450 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -2.076 ; -2.875 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 4.730  ; 4.624  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 3.684  ; 3.742  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 4.730  ; 4.624  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 3.815  ; 3.840  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 3.815  ; 3.840  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.242  ; 3.262  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.078  ; 2.058  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 1.952  ; 1.919  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.052  ; 2.029  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 2.057  ; 2.028  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 1.941  ; 1.906  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.978  ; 1.945  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.808  ; 1.766  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.853  ; 1.814  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 2.078  ; 2.058  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.927  ; 1.900  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 2.054  ; 2.025  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.844  ; 1.803  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.826  ; 1.785  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.834  ; 1.793  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.837  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.803  ; 1.760  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 1.988  ; 1.956  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 4.395  ; 4.265  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 3.002  ; 2.927  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 3.121  ; 3.023  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 3.160  ; 3.078  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 4.395  ; 4.265  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 3.241  ; 3.219  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 3.153  ; 3.073  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 3.198  ; 3.158  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 3.262  ; 3.392  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 3.060  ; 3.149  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.863  ; 2.956  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 3.033  ; 3.014  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 2.869  ; 2.835  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 2.897  ; 2.958  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 3.024  ; 2.995  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.902  ; 2.958  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 3.130  ; 3.250  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 1.953  ; 1.920  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 1.907  ; 1.872  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 2.149  ; 2.152  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.454  ; 3.223  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.313 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.366 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 3.600  ; 3.651  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 3.600  ; 3.651  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 4.603  ; 4.499  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 3.725  ; 3.745  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 3.725  ; 3.745  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.171  ; 3.194  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 1.559  ; 1.515  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 1.698  ; 1.662  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 1.793  ; 1.768  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 1.798  ; 1.767  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 1.687  ; 1.650  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.722  ; 1.687  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.559  ; 1.515  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.602  ; 1.561  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 1.819  ; 1.797  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.672  ; 1.642  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 1.796  ; 1.765  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.595  ; 1.552  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.575  ; 1.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.583  ; 1.541  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.587  ; 1.545  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.553  ; 1.509  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 1.731  ; 1.697  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 2.168  ; 2.112  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 2.168  ; 2.154  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 2.351  ; 2.369  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 2.399  ; 2.438  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 3.763  ; 3.577  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 2.470  ; 2.514  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 2.385  ; 2.426  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 2.364  ; 2.385  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 2.482  ; 2.527  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 2.327  ; 2.344  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.176  ; 2.112  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 2.375  ; 2.389  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 2.296  ; 2.310  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 2.239  ; 2.200  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 2.483  ; 2.518  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.211  ; 2.169  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 2.435  ; 2.401  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 1.697  ; 1.662  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 1.654  ; 1.616  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 1.886  ; 1.885  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.200  ; 2.967  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.537 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.591 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 5.176 ; 5.154 ; 6.021 ; 5.999 ;
+; SW[4]      ; VGA_B[1]    ; 5.325 ; 5.357 ; 6.143 ; 6.155 ;
+; SW[4]      ; VGA_B[2]    ; 4.830 ; 4.862 ; 5.653 ; 5.685 ;
+; SW[4]      ; VGA_B[3]    ; 4.907 ; 4.908 ; 5.750 ; 5.751 ;
+; SW[4]      ; VGA_G[0]    ; 5.589 ; 5.608 ; 6.383 ; 6.402 ;
+; SW[4]      ; VGA_G[1]    ; 4.995 ; 5.039 ; 5.858 ; 5.902 ;
+; SW[4]      ; VGA_G[2]    ; 5.187 ; 5.230 ; 6.012 ; 6.021 ;
+; SW[4]      ; VGA_G[3]    ; 5.213 ; 5.235 ; 6.059 ; 6.081 ;
+; SW[4]      ; VGA_R[0]    ; 5.709 ; 5.731 ; 6.569 ; 6.591 ;
+; SW[4]      ; VGA_R[1]    ; 5.293 ; 5.337 ; 6.128 ; 6.153 ;
+; SW[4]      ; VGA_R[2]    ; 5.073 ; 5.075 ; 5.885 ; 5.894 ;
+; SW[4]      ; VGA_R[3]    ; 5.035 ; 5.052 ; 5.862 ; 5.879 ;
+; SW[5]      ; VGA_B[0]    ; 4.971 ; 4.949 ; 5.788 ; 5.766 ;
+; SW[5]      ; VGA_B[1]    ; 4.983 ; 5.015 ; 5.757 ; 5.789 ;
+; SW[5]      ; VGA_B[2]    ; 4.771 ; 4.803 ; 5.560 ; 5.578 ;
+; SW[5]      ; VGA_B[3]    ; 4.704 ; 4.705 ; 5.518 ; 5.519 ;
+; SW[5]      ; VGA_G[0]    ; 5.231 ; 5.250 ; 6.012 ; 6.031 ;
+; SW[5]      ; VGA_G[1]    ; 4.807 ; 4.851 ; 5.613 ; 5.657 ;
+; SW[5]      ; VGA_G[2]    ; 4.873 ; 4.916 ; 5.653 ; 5.695 ;
+; SW[5]      ; VGA_G[3]    ; 5.009 ; 5.031 ; 5.823 ; 5.845 ;
+; SW[5]      ; VGA_R[0]    ; 5.524 ; 5.546 ; 6.330 ; 6.352 ;
+; SW[5]      ; VGA_R[1]    ; 4.954 ; 4.998 ; 5.728 ; 5.772 ;
+; SW[5]      ; VGA_R[2]    ; 4.752 ; 4.754 ; 5.531 ; 5.533 ;
+; SW[5]      ; VGA_R[3]    ; 4.891 ; 4.910 ; 5.724 ; 5.741 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 4.956 ; 4.939 ; 5.803 ; 5.786 ;
+; SW[4]      ; VGA_B[1]    ; 4.832 ; 4.867 ; 5.683 ; 5.681 ;
+; SW[4]      ; VGA_B[2]    ; 4.699 ; 4.708 ; 5.495 ; 5.504 ;
+; SW[4]      ; VGA_B[3]    ; 4.600 ; 4.593 ; 5.402 ; 5.418 ;
+; SW[4]      ; VGA_G[0]    ; 5.265 ; 5.255 ; 6.138 ; 6.128 ;
+; SW[4]      ; VGA_G[1]    ; 4.426 ; 4.447 ; 5.249 ; 5.263 ;
+; SW[4]      ; VGA_G[2]    ; 4.957 ; 4.970 ; 5.808 ; 5.817 ;
+; SW[4]      ; VGA_G[3]    ; 4.574 ; 4.595 ; 5.413 ; 5.389 ;
+; SW[4]      ; VGA_R[0]    ; 5.413 ; 5.406 ; 6.276 ; 6.269 ;
+; SW[4]      ; VGA_R[1]    ; 4.784 ; 4.809 ; 5.609 ; 5.627 ;
+; SW[4]      ; VGA_R[2]    ; 4.871 ; 4.878 ; 5.700 ; 5.700 ;
+; SW[4]      ; VGA_R[3]    ; 4.632 ; 4.692 ; 5.488 ; 5.461 ;
+; SW[5]      ; VGA_B[0]    ; 4.392 ; 4.371 ; 5.181 ; 5.179 ;
+; SW[5]      ; VGA_B[1]    ; 4.801 ; 4.837 ; 5.574 ; 5.610 ;
+; SW[5]      ; VGA_B[2]    ; 4.374 ; 4.416 ; 5.188 ; 5.188 ;
+; SW[5]      ; VGA_B[3]    ; 4.537 ; 4.543 ; 5.345 ; 5.344 ;
+; SW[5]      ; VGA_G[0]    ; 4.426 ; 4.405 ; 5.215 ; 5.214 ;
+; SW[5]      ; VGA_G[1]    ; 4.607 ; 4.637 ; 5.416 ; 5.428 ;
+; SW[5]      ; VGA_G[2]    ; 4.453 ; 4.460 ; 5.231 ; 5.231 ;
+; SW[5]      ; VGA_G[3]    ; 4.791 ; 4.811 ; 5.610 ; 5.622 ;
+; SW[5]      ; VGA_R[0]    ; 4.516 ; 4.498 ; 5.305 ; 5.307 ;
+; SW[5]      ; VGA_R[1]    ; 4.815 ; 4.836 ; 5.588 ; 5.609 ;
+; SW[5]      ; VGA_R[2]    ; 4.584 ; 4.578 ; 5.354 ; 5.387 ;
+; SW[5]      ; VGA_R[3]    ; 4.683 ; 4.742 ; 5.479 ; 5.520 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.568 ; 2.549 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.911 ; 2.892 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.700 ; 2.681 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.710 ; 2.691 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.850 ; 2.831 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.568 ; 2.549 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.700 ; 2.681 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.588 ; 2.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.668 ; 2.649 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.926 ; 2.907 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.926 ; 2.907 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.931 ; 2.912 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.916 ; 2.897 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.921 ; 2.902 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.931 ; 2.912 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.911 ; 2.892 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.568 ; 2.549 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 1.449 ; 1.449 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 1.779 ; 1.779 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 1.576 ; 1.576 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 1.586 ; 1.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 1.720 ; 1.720 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 1.449 ; 1.449 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 1.576 ; 1.576 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 1.469 ; 1.469 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 1.545 ; 1.545 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 1.793 ; 1.793 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 1.793 ; 1.793 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 1.799 ; 1.799 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 1.783 ; 1.783 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 1.789 ; 1.789 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 1.799 ; 1.799 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 1.779 ; 1.779 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 1.449 ; 1.449 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.613     ; 2.613     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.015     ; 3.015     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.753     ; 2.753     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.763     ; 2.763     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.916     ; 2.916     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.613     ; 2.613     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.753     ; 2.753     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.633     ; 2.633     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.726     ; 2.726     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.027     ; 3.027     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.027     ; 3.027     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.035     ; 3.035     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.017     ; 3.017     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.025     ; 3.025     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.035     ; 3.035     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.015     ; 3.015     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.613     ; 2.613     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 1.492     ; 1.624     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 1.878     ; 2.010     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 1.627     ; 1.759     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 1.637     ; 1.769     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 1.784     ; 1.916     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 1.492     ; 1.624     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 1.627     ; 1.759     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 1.512     ; 1.644     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 1.601     ; 1.733     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 1.891     ; 2.023     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 1.891     ; 2.023     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 1.898     ; 2.030     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 1.881     ; 2.013     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 1.888     ; 2.020     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 1.898     ; 2.030     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 1.878     ; 2.010     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 1.492     ; 1.624     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 13.328 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.328                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.214        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 6.114        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.361                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.837        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.363                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 5.771        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.483                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.068        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 6.415        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.491                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.107        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 6.384        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.495                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.162        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 6.333        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.506                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.085        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 6.421        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.510                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.590        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 5.920        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.544                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.257        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 6.287        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.572                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.047        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 6.525        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.587                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.326        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 6.261        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.597                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.145        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 6.452        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.633                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.273        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 6.360        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.641                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.431        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 6.210        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.664                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.325        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 6.339        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.669                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.590        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 6.079        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.681                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.500        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 6.181        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.763                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.382        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 6.381        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.765                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.130        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 6.635        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.779                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 6.186        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.789                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.431        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 6.358        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.818                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.054        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 6.764        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.827                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.519        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 6.308        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.858                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.442        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 6.416        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.860                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.534        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 6.326        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.872                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.263        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 6.609        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.884                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.442        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 6.442        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.932                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.596        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 6.336        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.941                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.530        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 6.411        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.942                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.526        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 6.416        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.950                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.532        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 6.418        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.979                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.597        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 6.382        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.987                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.599        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 6.388        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.021                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.440        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 6.581        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.025                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.531        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 6.494        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.049                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.533        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 6.516        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.064                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.507        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 6.557        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.078                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.341        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 6.737        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 14.099                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.515        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 6.584        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 14.388                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.599        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 6.789        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                                               ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+; Clock                                                ; Setup   ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+; Worst-case Slack                                     ; -0.837  ; 0.169 ; -1.488   ; 0.849   ; 3.734               ;
+;  CLOCK_50                                            ; 14.268  ; 0.187 ; 12.673   ; 0.849   ; 9.266               ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.837  ; 0.169 ; -1.488   ; 2.409   ; 3.734               ;
+; Design-wide TNS                                      ; -39.407 ; 0.0   ; -368.986 ; 0.0     ; 0.0                 ;
+;  CLOCK_50                                            ; 0.000   ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -39.407 ; 0.000 ; -368.986 ; 0.000   ; 0.000               ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 4.175 ; 4.835 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 4.175 ; 4.835 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 3.570 ; 4.128 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 4.346 ; 4.882 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.719 ; 4.304 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.888 ; 4.403 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.837 ; 4.347 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 4.081 ; 4.605 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.797 ; 4.328 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.695 ; 4.207 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 4.048 ; 4.575 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.537 ; 4.045 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.682 ; 4.211 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.737 ; 4.250 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.742 ; 4.251 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.421 ; 3.933 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.713 ; 4.225 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.625 ; 4.168 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 4.346 ; 4.882 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -0.978 ; -1.819 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -0.978 ; -1.823 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.027 ; -1.819 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -1.578 ; -2.319 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; -1.739 ; -2.535 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; -1.827 ; -2.568 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; -1.810 ; -2.539 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; -1.943 ; -2.700 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; -1.762 ; -2.539 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; -1.733 ; -2.468 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -1.925 ; -2.682 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -1.640 ; -2.381 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -1.716 ; -2.467 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -1.761 ; -2.499 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; -1.756 ; -2.494 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -1.578 ; -2.319 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -1.751 ; -2.487 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -1.692 ; -2.450 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -2.076 ; -2.875 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 7.926  ; 7.746  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.149  ; 6.132  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 7.926  ; 7.746  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 6.407  ; 6.287  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 6.407  ; 6.287  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.330  ; 5.394  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.447  ; 3.336  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.257  ; 3.115  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.414  ; 3.270  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.413  ; 3.273  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.225  ; 3.093  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.268  ; 3.141  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.008  ; 2.891  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.073  ; 2.949  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.447  ; 3.336  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.235  ; 3.095  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.429  ; 3.303  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.048  ; 2.930  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.030  ; 2.910  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.035  ; 2.917  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.038  ; 2.923  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.004  ; 2.884  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.343  ; 3.195  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 6.815  ; 6.557  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.037  ; 4.853  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.167  ; 4.959  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.229  ; 5.016  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 6.815  ; 6.557  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.405  ; 5.227  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.223  ; 5.014  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 5.360  ; 5.203  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.549  ; 5.513  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.131  ; 5.050  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 4.801  ; 4.763  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.067  ; 4.895  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 4.775  ; 4.677  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 4.893  ; 4.820  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.056  ; 4.954  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 4.932  ; 4.824  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.289  ; 5.224  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.240  ; 3.114  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.182  ; 3.050  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.560  ; 3.464  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.236  ; 4.875  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.448 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.595 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 3.600  ; 3.651  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 3.600  ; 3.651  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 4.603  ; 4.499  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 3.725  ; 3.745  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 3.725  ; 3.745  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.171  ; 3.194  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 1.559  ; 1.515  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 1.698  ; 1.662  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 1.793  ; 1.768  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 1.798  ; 1.767  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 1.687  ; 1.650  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.722  ; 1.687  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.559  ; 1.515  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.602  ; 1.561  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 1.819  ; 1.797  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.672  ; 1.642  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 1.796  ; 1.765  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.595  ; 1.552  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.575  ; 1.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.583  ; 1.541  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.587  ; 1.545  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.553  ; 1.509  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 1.731  ; 1.697  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 2.168  ; 2.112  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 2.168  ; 2.154  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 2.351  ; 2.369  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 2.399  ; 2.438  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 3.763  ; 3.577  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 2.470  ; 2.514  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 2.385  ; 2.426  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 2.364  ; 2.385  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 2.482  ; 2.527  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 2.327  ; 2.344  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.176  ; 2.112  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 2.375  ; 2.389  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 2.296  ; 2.310  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 2.239  ; 2.200  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 2.483  ; 2.518  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.211  ; 2.169  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 2.435  ; 2.401  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 1.697  ; 1.662  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 1.654  ; 1.616  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 1.886  ; 1.885  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.200  ; 2.967  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.537 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.591 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++------------------------------------------------------------+
+; Progagation Delay                                          ;
++------------+-------------+-------+-------+--------+--------+
+; Input Port ; Output Port ; RR    ; RF    ; FR     ; FF     ;
++------------+-------------+-------+-------+--------+--------+
+; SW[4]      ; VGA_B[0]    ; 8.826 ; 8.684 ; 9.435  ; 9.293  ;
+; SW[4]      ; VGA_B[1]    ; 9.179 ; 9.016 ; 9.739  ; 9.533  ;
+; SW[4]      ; VGA_B[2]    ; 8.250 ; 8.155 ; 8.832  ; 8.739  ;
+; SW[4]      ; VGA_B[3]    ; 8.364 ; 8.243 ; 8.973  ; 8.852  ;
+; SW[4]      ; VGA_G[0]    ; 9.485 ; 9.420 ; 10.061 ; 9.947  ;
+; SW[4]      ; VGA_G[1]    ; 8.548 ; 8.524 ; 9.170  ; 9.146  ;
+; SW[4]      ; VGA_G[2]    ; 8.898 ; 8.839 ; 9.483  ; 9.352  ;
+; SW[4]      ; VGA_G[3]    ; 8.888 ; 8.793 ; 9.498  ; 9.407  ;
+; SW[4]      ; VGA_R[0]    ; 9.747 ; 9.647 ; 10.341 ; 10.272 ;
+; SW[4]      ; VGA_R[1]    ; 9.114 ; 8.972 ; 9.685  ; 9.510  ;
+; SW[4]      ; VGA_R[2]    ; 8.692 ; 8.534 ; 9.241  ; 9.092  ;
+; SW[4]      ; VGA_R[3]    ; 8.517 ; 8.427 ; 9.113  ; 9.023  ;
+; SW[5]      ; VGA_B[0]    ; 8.458 ; 8.316 ; 9.069  ; 8.927  ;
+; SW[5]      ; VGA_B[1]    ; 8.540 ; 8.377 ; 9.057  ; 8.894  ;
+; SW[5]      ; VGA_B[2]    ; 8.138 ; 8.045 ; 8.672  ; 8.553  ;
+; SW[5]      ; VGA_B[3]    ; 7.996 ; 7.875 ; 8.606  ; 8.485  ;
+; SW[5]      ; VGA_G[0]    ; 8.837 ; 8.772 ; 9.396  ; 9.326  ;
+; SW[5]      ; VGA_G[1]    ; 8.195 ; 8.171 ; 8.754  ; 8.730  ;
+; SW[5]      ; VGA_G[2]    ; 8.330 ; 8.252 ; 8.870  ; 8.783  ;
+; SW[5]      ; VGA_G[3]    ; 8.527 ; 8.427 ; 9.130  ; 9.039  ;
+; SW[5]      ; VGA_R[0]    ; 9.391 ; 9.296 ; 9.924  ; 9.857  ;
+; SW[5]      ; VGA_R[1]    ; 8.481 ; 8.339 ; 9.004  ; 8.854  ;
+; SW[5]      ; VGA_R[2]    ; 8.101 ; 7.943 ; 8.629  ; 8.475  ;
+; SW[5]      ; VGA_R[3]    ; 8.269 ; 8.189 ; 8.912  ; 8.822  ;
++------------+-------------+-------+-------+--------+--------+
+
+
++----------------------------------------------------------+
+; Minimum Progagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 4.956 ; 4.939 ; 5.803 ; 5.786 ;
+; SW[4]      ; VGA_B[1]    ; 4.832 ; 4.867 ; 5.683 ; 5.681 ;
+; SW[4]      ; VGA_B[2]    ; 4.699 ; 4.708 ; 5.495 ; 5.504 ;
+; SW[4]      ; VGA_B[3]    ; 4.600 ; 4.593 ; 5.402 ; 5.418 ;
+; SW[4]      ; VGA_G[0]    ; 5.265 ; 5.255 ; 6.138 ; 6.128 ;
+; SW[4]      ; VGA_G[1]    ; 4.426 ; 4.447 ; 5.249 ; 5.263 ;
+; SW[4]      ; VGA_G[2]    ; 4.957 ; 4.970 ; 5.808 ; 5.817 ;
+; SW[4]      ; VGA_G[3]    ; 4.574 ; 4.595 ; 5.413 ; 5.389 ;
+; SW[4]      ; VGA_R[0]    ; 5.413 ; 5.406 ; 6.276 ; 6.269 ;
+; SW[4]      ; VGA_R[1]    ; 4.784 ; 4.809 ; 5.609 ; 5.627 ;
+; SW[4]      ; VGA_R[2]    ; 4.871 ; 4.878 ; 5.700 ; 5.700 ;
+; SW[4]      ; VGA_R[3]    ; 4.632 ; 4.692 ; 5.488 ; 5.461 ;
+; SW[5]      ; VGA_B[0]    ; 4.392 ; 4.371 ; 5.181 ; 5.179 ;
+; SW[5]      ; VGA_B[1]    ; 4.801 ; 4.837 ; 5.574 ; 5.610 ;
+; SW[5]      ; VGA_B[2]    ; 4.374 ; 4.416 ; 5.188 ; 5.188 ;
+; SW[5]      ; VGA_B[3]    ; 4.537 ; 4.543 ; 5.345 ; 5.344 ;
+; SW[5]      ; VGA_G[0]    ; 4.426 ; 4.405 ; 5.215 ; 5.214 ;
+; SW[5]      ; VGA_G[1]    ; 4.607 ; 4.637 ; 5.416 ; 5.428 ;
+; SW[5]      ; VGA_G[2]    ; 4.453 ; 4.460 ; 5.231 ; 5.231 ;
+; SW[5]      ; VGA_G[3]    ; 4.791 ; 4.811 ; 5.610 ; 5.622 ;
+; SW[5]      ; VGA_R[0]    ; 4.516 ; 4.498 ; 5.305 ; 5.307 ;
+; SW[5]      ; VGA_R[1]    ; 4.815 ; 4.836 ; 5.588 ; 5.609 ;
+; SW[5]      ; VGA_R[2]    ; 4.584 ; 4.578 ; 5.354 ; 5.387 ;
+; SW[5]      ; VGA_R[3]    ; 4.683 ; 4.742 ; 5.479 ; 5.520 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                       ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin              ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; PS2_DAT          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; PS2_CLK          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; GPIO_1_CLKIN[1]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[9]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[8]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[15]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[14]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[13]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[12]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[11]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[10]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[9]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[8]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[7]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[6]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[5]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[4]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[3]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[2]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[1]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[0]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[31]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[30]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[29]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[28]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[27]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[26]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[25]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[24]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[23]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[22]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[21]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[20]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[19]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[18]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[17]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[16]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[15]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[14]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[13]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[12]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[11]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[10]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[9]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[8]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[7]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[6]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[5]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[4]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; PS2_DAT                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; PS2_CLK                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[4]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[5]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[0]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[7]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[6]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[3]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[2]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[1]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[0]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[1]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1_CLKIN[0]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[2]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin              ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.08 V              ; -0.00596 V          ; 0.305 V                              ; 0.266 V                              ; 5.3e-09 s                   ; 4.39e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-06 V                  ; 3.08 V             ; -0.00596 V         ; 0.305 V                             ; 0.266 V                             ; 5.3e-09 s                  ; 4.39e-09 s                 ; Yes                       ; Yes                       ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.08 V              ; -0.00513 V          ; 0.274 V                              ; 0.267 V                              ; 5.67e-09 s                  ; 4.62e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.08 V             ; -0.00513 V         ; 0.274 V                             ; 0.267 V                             ; 5.67e-09 s                 ; 4.62e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.08 V              ; -0.00596 V          ; 0.305 V                              ; 0.266 V                              ; 5.3e-09 s                   ; 4.39e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-06 V                  ; 3.08 V             ; -0.00596 V         ; 0.305 V                             ; 0.266 V                             ; 5.3e-09 s                  ; 4.39e-09 s                 ; Yes                       ; Yes                       ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; PS2_DAT          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; PS2_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-06 V                   ; 3.14 V              ; -0.0402 V           ; 0.146 V                              ; 0.156 V                              ; 4.62e-10 s                  ; 4.36e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-06 V                  ; 3.14 V             ; -0.0402 V          ; 0.146 V                             ; 0.156 V                             ; 4.62e-10 s                 ; 4.36e-10 s                 ; Yes                       ; Yes                       ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin              ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; PS2_DAT          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; PS2_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.52e-08 V                   ; 3.58 V              ; -0.064 V            ; 0.234 V                              ; 0.085 V                              ; 2.93e-10 s                  ; 3.07e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.52e-08 V                  ; 3.58 V             ; -0.064 V           ; 0.234 V                             ; 0.085 V                             ; 2.93e-10 s                 ; 3.07e-10 s                 ; Yes                       ; Yes                       ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                                                                       ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                          ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                                            ; CLOCK_50                                            ; 3231     ; 0        ; 0        ; 0        ;
+; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11685    ; 0        ; 0        ; 0        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                                                                        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                          ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                                            ; CLOCK_50                                            ; 3231     ; 0        ; 0        ; 0        ;
+; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11685    ; 0        ; 0        ; 0        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Recovery Transfers                                                                                           ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50                                            ; 519      ; 0        ; 0        ; 0        ;
+; CLOCK_50   ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302      ; 0        ; 0        ; 0        ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Removal Transfers                                                                                            ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50                                            ; 519      ; 0        ; 0        ; 0        ;
+; CLOCK_50   ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302      ; 0        ; 0        ; 0        ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 5     ; 5    ;
+; Unconstrained Input Ports       ; 43    ; 43   ;
+; Unconstrained Input Port Paths  ; 491   ; 491  ;
+; Unconstrained Output Ports      ; 89    ; 89   ;
+; Unconstrained Output Port Paths ; 530   ; 530  ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 08 16:24:47 2016
+Info: Command: quartus_sta DE0_D5M -c DE0_D5M
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity dcfifo_v5o1
+        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* 
+        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* 
+Info (332104): Reading SDC File: 'DE0_D5M.sdc'
+Info (332110): Deriving PLL clocks
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]}
+Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.837
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.837       -39.407 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    14.268         0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.331
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.331         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.358         0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is -1.488
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -1.488      -368.986 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    12.673         0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 1.559
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     1.559         0.000 CLOCK_50 
+    Info (332119):     4.115         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.734
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     3.734         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.580         0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 11.193 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.283
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.283        -5.821 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    14.832         0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.298
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.298         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.312         0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is -0.835
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.835      -178.452 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    13.489         0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 1.418
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     1.418         0.000 CLOCK_50 
+    Info (332119):     3.617         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.739
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     3.739         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.561         0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 11.719 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info: Analyzing Fast 1200mV 0C Model
+Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332146): Worst-case setup slack is 1.209
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     1.209         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    16.656         0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.169
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.169         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.187         0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is 0.780
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.780         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    15.649         0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 0.849
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.849         0.000 CLOCK_50 
+    Info (332119):     2.409         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.746
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     3.746         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.266         0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 13.328 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 29 warnings
+    Info: Peak virtual memory: 549 megabytes
+    Info: Processing ended: Tue Mar 08 16:24:59 2016
+    Info: Elapsed time: 00:00:12
+    Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.summary b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.summary
new file mode 100644
index 0000000..ac894d6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.summary
@@ -0,0 +1,125 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.837
+TNS   : -39.407
+
+Type  : Slow 1200mV 85C Model Setup 'CLOCK_50'
+Slack : 14.268
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.331
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'CLOCK_50'
+Slack : 0.358
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -1.488
+TNS   : -368.986
+
+Type  : Slow 1200mV 85C Model Recovery 'CLOCK_50'
+Slack : 12.673
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'CLOCK_50'
+Slack : 1.559
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 4.115
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.734
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.580
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.283
+TNS   : -5.821
+
+Type  : Slow 1200mV 0C Model Setup 'CLOCK_50'
+Slack : 14.832
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.298
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.312
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.835
+TNS   : -178.452
+
+Type  : Slow 1200mV 0C Model Recovery 'CLOCK_50'
+Slack : 13.489
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'CLOCK_50'
+Slack : 1.418
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.617
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.739
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.561
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 1.209
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'CLOCK_50'
+Slack : 16.656
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.169
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.187
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.780
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'CLOCK_50'
+Slack : 15.649
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'CLOCK_50'
+Slack : 0.849
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 2.409
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.746
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.266
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.tis_db_list.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.tis_db_list.ddb
new file mode 100644
index 0000000..8a35815
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.tis_db_list.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v
new file mode 100644
index 0000000..278fabe
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v
@@ -0,0 +1,379 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE0_D5M
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 12/03/14  :| DE0 support
+// --------------------------------------------------------------------
+
+module DE0_D5M
+	(
+		////////////////////	Clock Input	 	////////////////////	 
+		CLOCK_50,						//	50 MHz
+		////////////////////	Push Button		////////////////////
+		KEY,								//	Pushbutton[2:0]
+		////////////////////	DPDT Switch		////////////////////
+		SW,								//	Toggle Switch[9:0]
+		////////////////////////	LED		////////////////////////
+		LEDG,								//	LED Green[9:0]
+		////////////////////	7-SEG Dispaly	////////////////////
+		HEX0,								//	Seven Segment Digit 0
+		HEX1,								//	Seven Segment Digit 1
+		HEX2,								//	Seven Segment Digit 2
+		HEX3,								//	Seven Segment Digit 3
+		/////////////////////	SDRAM Interface		////////////////
+		DRAM_DQ,							//	SDRAM Data bus 16 Bits
+		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_UDQM,						//	SDRAM High-byte Data Mask
+		DRAM_WE_N,						//	SDRAM Write Enable
+		DRAM_CAS_N,						//	SDRAM Column Address Strobe
+		DRAM_RAS_N,						//	SDRAM Row Address Strobe
+		DRAM_CS_N,						//	SDRAM Chip Select
+		DRAM_BA_0,						//	SDRAM Bank Address 0
+		DRAM_BA_1,						//	SDRAM Bank Address 0
+		DRAM_CLK,						//	SDRAM Clock
+		DRAM_CKE,						//	SDRAM Clock Enable
+		////////////////////	VGA		////////////////////////////
+		VGA_HS,							//	VGA H_SYNC
+		VGA_VS,							//	VGA V_SYNC
+		VGA_R,   						//	VGA Red[3:0]
+		VGA_G,	 						//	VGA Green[3:0]
+		VGA_B,  							//	VGA Blue[3:0]
+		VGA_CLK,                   // VGA Clk
+		VGA_X,							//	VGA X scan coord
+		VGA_Y,							//	VGA Y scan coord
+		VGA_ACTIVE,						//	VGA ACTIVE
+		////////////////////	GPIO	////////////////////////////
+		//GPIO_0,							//	GPIO Connection 0
+		GPIO_1_CLKIN,              // GPIO Connection 1 CLK INPUTS
+		GPIO_1_CLKOUT,             // GPIO Connection 1 CLK OUTPUTS
+		GPIO_1							//	GPIO Connection 1
+	);
+
+////////////////////////	Clock Input	 	////////////////////////
+input			CLOCK_50;				//	50 MHz
+////////////////////////	Push Button		////////////////////////
+input	[2:0]	KEY;						//	Pushbutton[3:0]
+////////////////////////	DPDT Switch		////////////////////////
+input	[9:0]	SW;						//	Toggle Switch[9:0]
+////////////////////////////	LED		////////////////////////////
+output	[9:0]	LEDG;					//	LED Green[7:0]
+////////////////////////	7-SEG Dispaly	////////////////////////
+output	[6:0]	HEX0;					//	Seven Segment Digit 0
+output	[6:0]	HEX1;					//	Seven Segment Digit 1
+output	[6:0]	HEX2;					//	Seven Segment Digit 2
+output	[6:0]	HEX3;					//	Seven Segment Digit 3
+///////////////////////		SDRAM Interface	////////////////////////
+inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
+output[11:0]	DRAM_ADDR;			//	SDRAM Address bus 12 Bits
+output			DRAM_LDQM;			//	SDRAM Low-byte Data Mask 
+output			DRAM_UDQM;			//	SDRAM High-byte Data Mask
+output			DRAM_WE_N;			//	SDRAM Write Enable
+output			DRAM_CAS_N;			//	SDRAM Column Address Strobe
+output			DRAM_RAS_N;			//	SDRAM Row Address Strobe
+output			DRAM_CS_N;			//	SDRAM Chip Select
+output			DRAM_BA_0;			//	SDRAM Bank Address 0
+output			DRAM_BA_1;			//	SDRAM Bank Address 0
+output			DRAM_CLK;			//	SDRAM Clock
+output			DRAM_CKE;			//	SDRAM Clock Enable
+////////////////////////	VGA			////////////////////////////
+output			VGA_HS;				//	VGA H_SYNC
+output			VGA_VS;				//	VGA V_SYNC
+output	[3:0]	VGA_R;   			//	VGA Red[3:0]
+output	[3:0]	VGA_G;	 			//	VGA Green[3:0]
+output	[3:0]	VGA_B;   			//	VGA Blue[3:0]
+output         VGA_CLK;          // VGA Clk
+output	[11:0]		VGA_X;				//	VGA X scan coord
+output	[11:0]		VGA_Y;				//	VGA Y scan coord
+output         VGA_ACTIVE;          // VGA ACTIVE
+////////////////////////	GPIO	////////////////////////////////
+
+input	[1:0]	   GPIO_1_CLKIN;				//	GPIO Connection 1 - need stand alone inputs for external clock, pins on the board rewired
+output [1:0]	GPIO_1_CLKOUT;				//	GPIO Connection 1 - need stand alone outputs for external clock, pins on the board rewired
+inout	[31:0]	GPIO_1;				//	GPIO Connection 1
+///////////////////////////////////////////////////////////////////
+//=============================================================================
+// REG/WIRE declarations
+//=============================================================================
+
+//	CCD
+wire	[11:0]	CCD_DATA;
+wire				CCD_SDAT;
+wire				CCD_SCLK;
+wire				CCD_FLASH;
+wire				CCD_FVAL;
+wire				CCD_LVAL;
+wire				CCD_PIXCLK;
+wire				CCD_MCLK;				//	CCD Master Clock
+
+wire	[15:0]	Read_DATA1;
+wire	[15:0]	Read_DATA2;
+wire				VGA_CTRL_CLK;
+wire	[11:0]	mCCD_DATA;
+wire				mCCD_DVAL;
+wire				mCCD_DVAL_d;
+wire	[15:0]	X_Cont;
+wire	[15:0]	Y_Cont;
+wire	[9:0]		X_ADDR;
+wire	[31:0]	Frame_Cont;
+wire				DLY_RST_0;
+wire				DLY_RST_1;
+wire				DLY_RST_2;
+wire				Read;
+reg	[11:0]	rCCD_DATA;
+reg				rCCD_LVAL;
+reg				rCCD_FVAL;
+wire	[11:0]	sCCD_R;
+wire	[11:0]	sCCD_G;
+wire	[11:0]	sCCD_B;
+wire				sCCD_DVAL;
+wire	[9:0]		VGA_R;   				//	VGA Red[9:0]
+wire	[9:0]		VGA_G;	 				//	VGA Green[9:0]
+wire	[9:0]		VGA_B;   				//	VGA Blue[9:0]
+wire	[11:0]		VGA_X;	 				//	VGA X scan 
+wire	[11:0]		VGA_Y;   				//	VGA Y scan
+wire				VGA_ACTIVE;
+reg	[1:0]		rClk;
+wire				sdram_ctrl_clk;
+
+//=============================================================================
+// Structural coding
+//=============================================================================
+assign	CCD_DATA[0]	=	GPIO_1[11];
+assign	CCD_DATA[1]	=	GPIO_1[10];
+assign	CCD_DATA[2]	=	GPIO_1[9];
+assign	CCD_DATA[3]	=	GPIO_1[8];
+assign	CCD_DATA[4]	=	GPIO_1[7];
+assign	CCD_DATA[5]	=	GPIO_1[6];
+assign	CCD_DATA[6]	=	GPIO_1[5];
+assign	CCD_DATA[7]	=	GPIO_1[4];
+assign	CCD_DATA[8]	=	GPIO_1[3];
+assign	CCD_DATA[9]	=	GPIO_1[2];
+assign	CCD_DATA[10]=	GPIO_1[1];
+assign	CCD_DATA[11]=	GPIO_1[0];
+assign	GPIO_1_CLKOUT[0]	=	CCD_MCLK;
+assign	CCD_FVAL	   =	GPIO_1[18];
+assign	CCD_LVAL	   =	GPIO_1[17];
+assign	CCD_PIXCLK	=	GPIO_1_CLKIN[0]; 
+assign	GPIO_1[15]	=	1'b1;  // tRIGGER
+assign	GPIO_1[14]	=	DLY_RST_1;
+
+assign	LEDG		   =	Y_Cont;
+
+assign	VGA_CTRL_CLK=	rClk[0];
+assign	VGA_CLK		=	~rClk[0];
+
+always@(posedge CLOCK_50)	rClk	<=	rClk+1;
+
+
+wire	[9:0]	oVGA_R;
+wire	[9:0]	oVGA_G;
+wire	[9:0]	oVGA_B;
+assign	VGA_R		=	oVGA_R[9:0];
+assign	VGA_G		=	oVGA_G[9:0];
+assign	VGA_B		=	oVGA_B[9:0];
+
+// vga scan coordinates
+wire	[11:0]	oVGA_X;
+wire	[11:0]	oVGA_Y;
+assign	VGA_X		=	oVGA_Y;
+assign	VGA_Y		=	oVGA_X;
+
+// vga output active
+wire 	oVGA_ACTIVE;
+assign VGA_ACTIVE = oVGA_ACTIVE;
+
+
+
+
+always@(posedge CCD_PIXCLK)
+begin
+	rCCD_DATA	<=	CCD_DATA;
+	rCCD_LVAL	<=	CCD_LVAL;
+	rCCD_FVAL	<=	CCD_FVAL;
+end
+
+VGA_Controller		u1	(	//	Host Side
+							.oRequest   (Read),
+//							.iRed       (10'b1111111111),
+//							.iGreen     (10'b0000000000),
+//							.iBlue      (10'b0000000000),
+							.iRed       (Read_DATA2[9:0]),
+							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
+							.iBlue      (Read_DATA1[9:0]),
+							//	VGA Side
+							.oVGA_R     (oVGA_R),
+							.oVGA_G     (oVGA_G),
+							.oVGA_B     (oVGA_B),
+							.oVGA_H_SYNC(VGA_HS),
+							.oVGA_V_SYNC(VGA_VS),
+							// VGA Scan Coordinates
+							.oVGA_X(oVGA_X),
+							.oVGA_Y(oVGA_Y),
+							.oVGA_ACTIVE(oVGA_ACTIVE),
+							//	Control Signal
+							.iCLK       (VGA_CTRL_CLK),
+							.iRST_N     (DLY_RST_2)
+						);
+
+
+Reset_Delay			u2	(	
+							.iCLK  (CLOCK_50),
+							.iRST  (KEY[0]),
+							.oRST_0(DLY_RST_0),
+							.oRST_1(DLY_RST_1),
+							.oRST_2(DLY_RST_2)
+						);
+
+CCD_Capture			u3	(	
+							.oDATA      (mCCD_DATA),
+							.oDVAL      (mCCD_DVAL),
+							.oX_Cont    (X_Cont),
+							.oY_Cont    (Y_Cont),
+							.oFrame_Cont(Frame_Cont),
+							.iDATA      (rCCD_DATA),
+							.iFVAL      (rCCD_FVAL),
+							.iLVAL      (rCCD_LVAL),
+							.iSTART     (!KEY[1]),
+							.iEND       (!KEY[2]),
+							.iCLK       (CCD_PIXCLK),
+							.iRST       (DLY_RST_2)
+						);
+
+RAW2RGB				u4	(	
+						   .iCLK   (CCD_PIXCLK),
+							.iRST   (DLY_RST_1),
+							.iDATA  (mCCD_DATA),
+							.iDVAL  (mCCD_DVAL),
+							.oRed   (sCCD_R),
+							.oGreen (sCCD_G),
+							.oBlue  (sCCD_B),
+							.oDVAL  (sCCD_DVAL),
+							.iX_Cont(X_Cont),
+							.iY_Cont(Y_Cont)
+						);
+
+SEG7_LUT_8 			u5	(	
+							.oSEG0(HEX0),
+							.oSEG1(HEX1),
+							.oSEG2(HEX2),
+							.oSEG3(HEX3),
+							.oSEG4(),
+							.oSEG5(),
+							.oSEG6(),
+							.oSEG7(),
+							.iDIG (Frame_Cont[31:0])
+						);
+
+sdram_pll 			u6	(
+							.inclk0(CLOCK_50),
+							.c0    (sdram_ctrl_clk),
+							.c1    (DRAM_CLK)
+						);
+
+assign CCD_MCLK = rClk[0];
+
+Sdram_Control_4Port	u7	(	//	HOST Side						
+								 .REF_CLK     (CLOCK_50),
+						       .RESET_N     (1'b1),
+							    .CLK    	  (sdram_ctrl_clk),
+
+									//	FIFO Write Side 1
+							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
+							    .WR1     	  (sCCD_DVAL),
+								 .WR1_ADDR	  (0),
+								 .WR1_MAX_ADDR(640*480),
+								 .WR1_LENGTH  (9'h100),
+								 .WR1_LOAD	  (!DLY_RST_0),
+								 .WR1_CLK	  (~CCD_PIXCLK),
+
+								  //	FIFO Write Side 2
+								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
+								 .WR2			  (sCCD_DVAL),
+								 .WR2_ADDR    (22'h100000),
+								 .WR2_MAX_ADDR(22'h100000+640*480),
+								 .WR2_LENGTH  (9'h100),
+								 .WR2_LOAD    (!DLY_RST_0),
+								 .WR2_CLK     (~CCD_PIXCLK),
+
+
+								  //	FIFO Read Side 1
+						       .RD1_DATA	  (Read_DATA1),
+								 .RD1			  (Read),
+				        	    .RD1_ADDR    (0),
+								 .RD1_MAX_ADDR(640*480),
+								 .RD1_LENGTH  (9'h100),
+								 .RD1_LOAD	  (!DLY_RST_0),
+								 .RD1_CLK	  (~VGA_CTRL_CLK),
+							
+								  //	FIFO Read Side 2
+						       .RD2_DATA	  (Read_DATA2),
+								 .RD2         (Read),
+								 .RD2_ADDR    (22'h100000),
+								 .RD2_MAX_ADDR(22'h100000+640*480),
+								 .RD2_LENGTH  (9'h100),
+								 .RD2_LOAD    (!DLY_RST_0),
+								 .RD2_CLK     (~VGA_CTRL_CLK),
+							
+								  //	SDRAM Side
+						       .SA			  (DRAM_ADDR),
+						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
+								 .CS_N		  (DRAM_CS_N),
+        					    .CKE			  (DRAM_CKE),
+								 .RAS_N		  (DRAM_RAS_N),
+								 .CAS_N		  (DRAM_CAS_N),
+								 .WE_N		  (DRAM_WE_N),
+								 .DQ			  (DRAM_DQ),
+								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
+						       );
+
+
+
+I2C_CCD_Config 		u8	(	//	Host Side
+								 .iCLK			  (CLOCK_50),
+								 .iRST_N         (DLY_RST_2),
+								 .iZOOM_MODE_SW  (SW[2]),
+								 .iEXPOSURE_ADJ  (SW[1]),
+								 .iEXPOSURE_DEC_p(SW[0]),
+								  //	I2C Side
+								 .I2C_SCLK		  (GPIO_1[20]),
+								 .I2C_SDAT		  (GPIO_1[19])
+							   );
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v.bak
new file mode 100644
index 0000000..8059c4c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v.bak
@@ -0,0 +1,369 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE0_D5M
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 12/03/14  :| DE0 support
+// --------------------------------------------------------------------
+
+module DE0_D5M
+	(
+		////////////////////	Clock Input	 	////////////////////	 
+		CLOCK_50,						//	50 MHz
+		////////////////////	Push Button		////////////////////
+		KEY,								//	Pushbutton[2:0]
+		////////////////////	DPDT Switch		////////////////////
+		SW,								//	Toggle Switch[9:0]
+		////////////////////////	LED		////////////////////////
+		LEDG,								//	LED Green[9:0]
+		////////////////////	7-SEG Dispaly	////////////////////
+		HEX0,								//	Seven Segment Digit 0
+		HEX1,								//	Seven Segment Digit 1
+		HEX2,								//	Seven Segment Digit 2
+		HEX3,								//	Seven Segment Digit 3
+		/////////////////////	SDRAM Interface		////////////////
+		DRAM_DQ,							//	SDRAM Data bus 16 Bits
+		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_UDQM,						//	SDRAM High-byte Data Mask
+		DRAM_WE_N,						//	SDRAM Write Enable
+		DRAM_CAS_N,						//	SDRAM Column Address Strobe
+		DRAM_RAS_N,						//	SDRAM Row Address Strobe
+		DRAM_CS_N,						//	SDRAM Chip Select
+		DRAM_BA_0,						//	SDRAM Bank Address 0
+		DRAM_BA_1,						//	SDRAM Bank Address 0
+		DRAM_CLK,						//	SDRAM Clock
+		DRAM_CKE,						//	SDRAM Clock Enable
+		////////////////////	VGA		////////////////////////////
+		VGA_HS,							//	VGA H_SYNC
+		VGA_VS,							//	VGA V_SYNC
+		VGA_R,   						//	VGA Red[3:0]
+		VGA_G,	 						//	VGA Green[3:0]
+		VGA_B,  							//	VGA Blue[3:0]
+		VGA_CLK,                   // VGA Clk
+		VGA_X,							//	VGA X scan coord
+		VGA_Y,							//	VGA Y scan coord
+		////////////////////	GPIO	////////////////////////////
+		//GPIO_0,							//	GPIO Connection 0
+		GPIO_1_CLKIN,              // GPIO Connection 1 CLK INPUTS
+		GPIO_1_CLKOUT,             // GPIO Connection 1 CLK OUTPUTS
+		GPIO_1							//	GPIO Connection 1
+	);
+
+////////////////////////	Clock Input	 	////////////////////////
+input			CLOCK_50;				//	50 MHz
+////////////////////////	Push Button		////////////////////////
+input	[2:0]	KEY;						//	Pushbutton[3:0]
+////////////////////////	DPDT Switch		////////////////////////
+input	[9:0]	SW;						//	Toggle Switch[9:0]
+////////////////////////////	LED		////////////////////////////
+output	[9:0]	LEDG;					//	LED Green[7:0]
+////////////////////////	7-SEG Dispaly	////////////////////////
+output	[6:0]	HEX0;					//	Seven Segment Digit 0
+output	[6:0]	HEX1;					//	Seven Segment Digit 1
+output	[6:0]	HEX2;					//	Seven Segment Digit 2
+output	[6:0]	HEX3;					//	Seven Segment Digit 3
+///////////////////////		SDRAM Interface	////////////////////////
+inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
+output[11:0]	DRAM_ADDR;			//	SDRAM Address bus 12 Bits
+output			DRAM_LDQM;			//	SDRAM Low-byte Data Mask 
+output			DRAM_UDQM;			//	SDRAM High-byte Data Mask
+output			DRAM_WE_N;			//	SDRAM Write Enable
+output			DRAM_CAS_N;			//	SDRAM Column Address Strobe
+output			DRAM_RAS_N;			//	SDRAM Row Address Strobe
+output			DRAM_CS_N;			//	SDRAM Chip Select
+output			DRAM_BA_0;			//	SDRAM Bank Address 0
+output			DRAM_BA_1;			//	SDRAM Bank Address 0
+output			DRAM_CLK;			//	SDRAM Clock
+output			DRAM_CKE;			//	SDRAM Clock Enable
+////////////////////////	VGA			////////////////////////////
+output			VGA_HS;				//	VGA H_SYNC
+output			VGA_VS;				//	VGA V_SYNC
+output	[3:0]	VGA_R;   			//	VGA Red[3:0]
+output	[3:0]	VGA_G;	 			//	VGA Green[3:0]
+output	[3:0]	VGA_B;   			//	VGA Blue[3:0]
+output         VGA_CLK;          // VGA Clk
+output	[11:0]		VGA_X;				//	VGA X scan coord
+output	[11:0]		VGA_Y;				//	VGA Y scan coord
+////////////////////////	GPIO	////////////////////////////////
+
+input	[1:0]	   GPIO_1_CLKIN;				//	GPIO Connection 1 - need stand alone inputs for external clock, pins on the board rewired
+output [1:0]	GPIO_1_CLKOUT;				//	GPIO Connection 1 - need stand alone outputs for external clock, pins on the board rewired
+inout	[31:0]	GPIO_1;				//	GPIO Connection 1
+///////////////////////////////////////////////////////////////////
+//=============================================================================
+// REG/WIRE declarations
+//=============================================================================
+
+//	CCD
+wire	[11:0]	CCD_DATA;
+wire				CCD_SDAT;
+wire				CCD_SCLK;
+wire				CCD_FLASH;
+wire				CCD_FVAL;
+wire				CCD_LVAL;
+wire				CCD_PIXCLK;
+wire				CCD_MCLK;				//	CCD Master Clock
+
+wire	[15:0]	Read_DATA1;
+wire	[15:0]	Read_DATA2;
+wire				VGA_CTRL_CLK;
+wire	[11:0]	mCCD_DATA;
+wire				mCCD_DVAL;
+wire				mCCD_DVAL_d;
+wire	[15:0]	X_Cont;
+wire	[15:0]	Y_Cont;
+wire	[9:0]		X_ADDR;
+wire	[31:0]	Frame_Cont;
+wire				DLY_RST_0;
+wire				DLY_RST_1;
+wire				DLY_RST_2;
+wire				Read;
+reg	[11:0]	rCCD_DATA;
+reg				rCCD_LVAL;
+reg				rCCD_FVAL;
+wire	[11:0]	sCCD_R;
+wire	[11:0]	sCCD_G;
+wire	[11:0]	sCCD_B;
+wire				sCCD_DVAL;
+wire	[9:0]		VGA_R;   				//	VGA Red[9:0]
+wire	[9:0]		VGA_G;	 				//	VGA Green[9:0]
+wire	[9:0]		VGA_B;   				//	VGA Blue[9:0]
+wire	[11:0]		VGA_X;	 				//	VGA X scan 
+wire	[11:0]		VGA_Y;   				//	VGA Y scan
+reg	[1:0]		rClk;
+wire				sdram_ctrl_clk;
+
+//=============================================================================
+// Structural coding
+//=============================================================================
+assign	CCD_DATA[0]	=	GPIO_1[11];
+assign	CCD_DATA[1]	=	GPIO_1[10];
+assign	CCD_DATA[2]	=	GPIO_1[9];
+assign	CCD_DATA[3]	=	GPIO_1[8];
+assign	CCD_DATA[4]	=	GPIO_1[7];
+assign	CCD_DATA[5]	=	GPIO_1[6];
+assign	CCD_DATA[6]	=	GPIO_1[5];
+assign	CCD_DATA[7]	=	GPIO_1[4];
+assign	CCD_DATA[8]	=	GPIO_1[3];
+assign	CCD_DATA[9]	=	GPIO_1[2];
+assign	CCD_DATA[10]=	GPIO_1[1];
+assign	CCD_DATA[11]=	GPIO_1[0];
+assign	GPIO_1_CLKOUT[0]	=	CCD_MCLK;
+assign	CCD_FVAL	   =	GPIO_1[18];
+assign	CCD_LVAL	   =	GPIO_1[17];
+assign	CCD_PIXCLK	=	GPIO_1_CLKIN[0]; 
+assign	GPIO_1[15]	=	1'b1;  // tRIGGER
+assign	GPIO_1[14]	=	DLY_RST_1;
+
+assign	LEDG		   =	Y_Cont;
+
+assign	VGA_CTRL_CLK=	rClk[0];
+assign	VGA_CLK		=	~rClk[0];
+
+always@(posedge CLOCK_50)	rClk	<=	rClk+1;
+
+wire	[9:0]	oVGA_R;
+wire	[9:0]	oVGA_G;
+wire	[9:0]	oVGA_B;
+assign	VGA_R		=	oVGA_R[9:0];
+assign	VGA_G		=	oVGA_G[9:0];
+assign	VGA_B		=	oVGA_B[9:0];
+
+
+wire	[11:0]	oVGA_X;
+wire	[11:0]	oVGA_Y;
+assign	VGA_X		=	oVGA_Y;
+assign	VGA_Y		=	oVGA_X;
+
+
+
+always@(posedge CCD_PIXCLK)
+begin
+	rCCD_DATA	<=	CCD_DATA;
+	rCCD_LVAL	<=	CCD_LVAL;
+	rCCD_FVAL	<=	CCD_FVAL;
+end
+
+VGA_Controller		u1	(	//	Host Side
+							.oRequest   (Read),
+//							.iRed       (10'b1111111111),
+//							.iGreen     (10'b0000000000),
+//							.iBlue      (10'b0000000000),
+							.iRed       (Read_DATA2[9:0]),
+							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
+							.iBlue      (Read_DATA1[9:0]),
+							//	VGA Side
+							.oVGA_R     (oVGA_R),
+							.oVGA_G     (oVGA_G),
+							.oVGA_B     (oVGA_B),
+							.oVGA_H_SYNC(VGA_HS),
+							.oVGA_V_SYNC(VGA_VS),
+							// VGA Scan Coordinates
+							.oVGA_X(oVGA_X),
+							.oVGA_Y(oVGA_Y),
+							//	Control Signal
+							.iCLK       (VGA_CTRL_CLK),
+							.iRST_N     (DLY_RST_2)
+						);
+
+
+Reset_Delay			u2	(	
+							.iCLK  (CLOCK_50),
+							.iRST  (KEY[0]),
+							.oRST_0(DLY_RST_0),
+							.oRST_1(DLY_RST_1),
+							.oRST_2(DLY_RST_2)
+						);
+
+CCD_Capture			u3	(	
+							.oDATA      (mCCD_DATA),
+							.oDVAL      (mCCD_DVAL),
+							.oX_Cont    (X_Cont),
+							.oY_Cont    (Y_Cont),
+							.oFrame_Cont(Frame_Cont),
+							.iDATA      (rCCD_DATA),
+							.iFVAL      (rCCD_FVAL),
+							.iLVAL      (rCCD_LVAL),
+							.iSTART     (!KEY[1]),
+							.iEND       (!KEY[2]),
+							.iCLK       (CCD_PIXCLK),
+							.iRST       (DLY_RST_2)
+						);
+
+RAW2RGB				u4	(	
+						   .iCLK   (CCD_PIXCLK),
+							.iRST   (DLY_RST_1),
+							.iDATA  (mCCD_DATA),
+							.iDVAL  (mCCD_DVAL),
+							.oRed   (sCCD_R),
+							.oGreen (sCCD_G),
+							.oBlue  (sCCD_B),
+							.oDVAL  (sCCD_DVAL),
+							.iX_Cont(X_Cont),
+							.iY_Cont(Y_Cont)
+						);
+
+SEG7_LUT_8 			u5	(	
+							.oSEG0(HEX0),
+							.oSEG1(HEX1),
+							.oSEG2(HEX2),
+							.oSEG3(HEX3),
+							.oSEG4(),
+							.oSEG5(),
+							.oSEG6(),
+							.oSEG7(),
+							.iDIG (Frame_Cont[31:0])
+						);
+
+sdram_pll 			u6	(
+							.inclk0(CLOCK_50),
+							.c0    (sdram_ctrl_clk),
+							.c1    (DRAM_CLK)
+						);
+
+assign CCD_MCLK = rClk[0];
+
+Sdram_Control_4Port	u7	(	//	HOST Side						
+								 .REF_CLK     (CLOCK_50),
+						       .RESET_N     (1'b1),
+							    .CLK    	  (sdram_ctrl_clk),
+
+									//	FIFO Write Side 1
+							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
+							    .WR1     	  (sCCD_DVAL),
+								 .WR1_ADDR	  (0),
+								 .WR1_MAX_ADDR(640*480),
+								 .WR1_LENGTH  (9'h100),
+								 .WR1_LOAD	  (!DLY_RST_0),
+								 .WR1_CLK	  (~CCD_PIXCLK),
+
+								  //	FIFO Write Side 2
+								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
+								 .WR2			  (sCCD_DVAL),
+								 .WR2_ADDR    (22'h100000),
+								 .WR2_MAX_ADDR(22'h100000+640*480),
+								 .WR2_LENGTH  (9'h100),
+								 .WR2_LOAD    (!DLY_RST_0),
+								 .WR2_CLK     (~CCD_PIXCLK),
+
+
+								  //	FIFO Read Side 1
+						       .RD1_DATA	  (Read_DATA1),
+								 .RD1			  (Read),
+				        	    .RD1_ADDR    (0),
+								 .RD1_MAX_ADDR(640*480),
+								 .RD1_LENGTH  (9'h100),
+								 .RD1_LOAD	  (!DLY_RST_0),
+								 .RD1_CLK	  (~VGA_CTRL_CLK),
+							
+								  //	FIFO Read Side 2
+						       .RD2_DATA	  (Read_DATA2),
+								 .RD2         (Read),
+								 .RD2_ADDR    (22'h100000),
+								 .RD2_MAX_ADDR(22'h100000+640*480),
+								 .RD2_LENGTH  (9'h100),
+								 .RD2_LOAD    (!DLY_RST_0),
+								 .RD2_CLK     (~VGA_CTRL_CLK),
+							
+								  //	SDRAM Side
+						       .SA			  (DRAM_ADDR),
+						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
+								 .CS_N		  (DRAM_CS_N),
+        					    .CKE			  (DRAM_CKE),
+								 .RAS_N		  (DRAM_RAS_N),
+								 .CAS_N		  (DRAM_CAS_N),
+								 .WE_N		  (DRAM_WE_N),
+								 .DQ			  (DRAM_DQ),
+								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
+						       );
+
+
+
+I2C_CCD_Config 		u8	(	//	Host Side
+								 .iCLK			  (CLOCK_50),
+								 .iRST_N         (DLY_RST_2),
+								 .iZOOM_MODE_SW  (SW[2]),
+								 .iEXPOSURE_ADJ  (SW[1]),
+								 .iEXPOSURE_DEC_p(SW[0]),
+								  //	I2C Side
+								 .I2C_SCLK		  (GPIO_1[20]),
+								 .I2C_SDAT		  (GPIO_1[19])
+							   );
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Line_Buffer.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Line_Buffer.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Line_Buffer.qip
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v
new file mode 100644
index 0000000..22e2411
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v
@@ -0,0 +1,567 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	Sdram_Control_4Port
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module Sdram_Control_4Port(
+		//	HOST Side
+        REF_CLK,
+        RESET_N,
+		CLK,
+		//	FIFO Write Side 1
+        WR1_DATA,
+		WR1,
+		WR1_ADDR,
+		WR1_MAX_ADDR,
+		WR1_LENGTH,
+		WR1_LOAD,
+		WR1_CLK,
+		//	FIFO Write Side 2
+        WR2_DATA,
+		WR2,
+		WR2_ADDR,
+		WR2_MAX_ADDR,
+		WR2_LENGTH,
+		WR2_LOAD,
+		WR2_CLK,
+		//	FIFO Read Side 1
+        RD1_DATA,
+		RD1,
+		RD1_ADDR,
+		RD1_MAX_ADDR,
+		RD1_LENGTH,
+		RD1_LOAD,	
+		RD1_CLK,
+		//	FIFO Read Side 2
+        RD2_DATA,
+		RD2,
+		RD2_ADDR,
+		RD2_MAX_ADDR,
+		RD2_LENGTH,
+		RD2_LOAD,
+		RD2_CLK,
+		//	SDRAM Side
+        SA,
+        BA,
+        CS_N,
+        CKE,
+        RAS_N,
+        CAS_N,
+        WE_N,
+        DQ,
+        DQM,
+        );
+
+
+`include        "Sdram_Params.h"
+//	HOST Side
+input                           REF_CLK;                //System Clock
+input                           RESET_N;                //System Reset
+input 							CLK;
+//	FIFO Write Side 1
+input   [`DSIZE-1:0]            WR1_DATA;               //Data input
+input							WR1;					//Write Request
+input	[`ASIZE-1:0]			WR1_ADDR;				//Write start address
+input	[`ASIZE-1:0]			WR1_MAX_ADDR;			//Write max address
+input	[8:0]					WR1_LENGTH;				//Write length
+input							WR1_LOAD;				//Write register load & fifo clear
+input							WR1_CLK;				//Write fifo clock
+
+//	FIFO Write Side 2
+input   [`DSIZE-1:0]            WR2_DATA;               //Data input
+input							WR2;					//Write Request
+input	[`ASIZE-1:0]			WR2_ADDR;				//Write start address
+input	[`ASIZE-1:0]			WR2_MAX_ADDR;			//Write max address
+input	[8:0]					WR2_LENGTH;				//Write length
+input							WR2_LOAD;				//Write register load & fifo clear
+input							WR2_CLK;				//Write fifo clock
+
+//	FIFO Read Side 1
+output  [`DSIZE-1:0]            RD1_DATA;               //Data output
+input							RD1;					//Read Request
+input	[`ASIZE-1:0]			RD1_ADDR;				//Read start address
+input	[`ASIZE-1:0]			RD1_MAX_ADDR;			//Read max address
+input	[8:0]					RD1_LENGTH;				//Read length
+input							RD1_LOAD;				//Read register load & fifo clear
+input							RD1_CLK;				//Read fifo clock
+
+//	FIFO Read Side 2
+output  [`DSIZE-1:0]            RD2_DATA;               //Data output
+input							RD2;					//Read Request
+input	[`ASIZE-1:0]			RD2_ADDR;				//Read start address
+input	[`ASIZE-1:0]			RD2_MAX_ADDR;			//Read max address
+input	[8:0]					RD2_LENGTH;				//Read length
+input							RD2_LOAD;				//Read register load & fifo clear
+input							RD2_CLK;				//Read fifo clock
+
+//	SDRAM Side
+output  [11:0]                  SA;                     //SDRAM address output
+output  [1:0]                   BA;                     //SDRAM bank address
+output  [1:0]                   CS_N;                   //SDRAM Chip Selects
+output                          CKE;                    //SDRAM clock enable
+output                          RAS_N;                  //SDRAM Row address Strobe
+output                          CAS_N;                  //SDRAM Column address Strobe
+output                          WE_N;                   //SDRAM write enable
+inout   [`DSIZE-1:0]            DQ;                     //SDRAM data bus
+output  [`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
+
+//	Internal Registers/Wires
+//	Controller
+reg		[`ASIZE-1:0]			mADDR;					//Internal address
+reg		[8:0]					mLENGTH;				//Internal length
+reg		[`ASIZE-1:0]			rWR1_ADDR;				//Register write address				
+reg		[`ASIZE-1:0]			rWR1_MAX_ADDR;			//Register max write address				
+reg		[8:0]					rWR1_LENGTH;			//Register write length
+reg		[`ASIZE-1:0]			rWR2_ADDR;				//Register write address				
+reg		[`ASIZE-1:0]			rWR2_MAX_ADDR;			//Register max write address				
+reg		[8:0]					rWR2_LENGTH;			//Register write length
+reg		[`ASIZE-1:0]			rRD1_ADDR;				//Register read address
+reg		[`ASIZE-1:0]			rRD1_MAX_ADDR;			//Register max read address
+reg		[8:0]					rRD1_LENGTH;			//Register read length
+reg		[`ASIZE-1:0]			rRD2_ADDR;				//Register read address
+reg		[`ASIZE-1:0]			rRD2_MAX_ADDR;			//Register max read address
+reg		[8:0]					rRD2_LENGTH;			//Register read length
+reg		[1:0]					WR_MASK;				//Write port active mask
+reg		[1:0]					RD_MASK;				//Read port active mask
+reg								mWR_DONE;				//Flag write done, 1 pulse SDR_CLK
+reg								mRD_DONE;				//Flag read done, 1 pulse SDR_CLK
+reg								mWR,Pre_WR;				//Internal WR edge capture
+reg								mRD,Pre_RD;				//Internal RD edge capture
+reg 	[9:0] 					ST;						//Controller status
+reg		[1:0] 					CMD;					//Controller command
+reg								PM_STOP;				//Flag page mode stop
+reg								PM_DONE;				//Flag page mode done
+reg								Read;					//Flag read active
+reg								Write;					//Flag write active
+reg	    [`DSIZE-1:0]           	mDATAOUT;               //Controller Data output
+wire    [`DSIZE-1:0]           	mDATAIN;                //Controller Data input
+wire    [`DSIZE-1:0]           	mDATAIN1;                //Controller Data input 1
+wire    [`DSIZE-1:0]           	mDATAIN2;                //Controller Data input 2
+wire                          	CMDACK;                 //Controller command acknowledgement
+//	DRAM Control
+reg  	[`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
+reg     [11:0]                  SA;                     //SDRAM address output
+reg     [1:0]                   BA;                     //SDRAM bank address
+reg     [1:0]                   CS_N;                   //SDRAM Chip Selects
+reg                             CKE;                    //SDRAM clock enable
+reg                             RAS_N;                  //SDRAM Row address Strobe
+reg                             CAS_N;                  //SDRAM Column address Strobe
+reg                             WE_N;                   //SDRAM write enable
+wire    [`DSIZE-1:0]            DQOUT;					//SDRAM data out link
+wire  	[`DSIZE/8-1:0]          IDQM;                   //SDRAM data mask lines
+wire    [11:0]                  ISA;                    //SDRAM address output
+wire    [1:0]                   IBA;                    //SDRAM bank address
+wire    [1:0]                   ICS_N;                  //SDRAM Chip Selects
+wire                            ICKE;                   //SDRAM clock enable
+wire                            IRAS_N;                 //SDRAM Row address Strobe
+wire                            ICAS_N;                 //SDRAM Column address Strobe
+wire                            IWE_N;                  //SDRAM write enable
+//	FIFO Control
+reg								OUT_VALID;				//Output data request to read side fifo
+reg								IN_REQ;					//Input	data request to write side fifo
+wire	[8:0]					write_side_fifo_rusedw1;
+wire	[8:0]					read_side_fifo_wusedw1;
+wire	[8:0]					write_side_fifo_rusedw2;
+wire	[8:0]					read_side_fifo_wusedw2;
+//	DRAM Internal Control
+wire    [`ASIZE-1:0]            saddr;
+wire                            load_mode;
+wire                            nop;
+wire                            reada;
+wire                            writea;
+wire                            refresh;
+wire                            precharge;
+wire                            oe;
+wire							ref_ack;
+wire							ref_req;
+wire							init_req;
+wire							cm_ack;
+wire							active;
+wire                            CLK;
+wire							CCD_CLK;
+
+control_interface control1 (
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .CMD(CMD),
+                .ADDR(mADDR),
+                .REF_ACK(ref_ack),
+                .CM_ACK(cm_ack),
+                .NOP(nop),
+                .READA(reada),
+                .WRITEA(writea),
+                .REFRESH(refresh),
+                .PRECHARGE(precharge),
+                .LOAD_MODE(load_mode),
+                .SADDR(saddr),
+                .REF_REQ(ref_req),
+				.INIT_REQ(init_req),
+                .CMD_ACK(CMDACK)
+                );
+
+command command1(
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .SADDR(saddr),
+                .NOP(nop),
+                .READA(reada),
+                .WRITEA(writea),
+                .REFRESH(refresh),
+				.LOAD_MODE(load_mode),
+                .PRECHARGE(precharge),
+                .REF_REQ(ref_req),
+				.INIT_REQ(init_req),
+                .REF_ACK(ref_ack),
+                .CM_ACK(cm_ack),
+                .OE(oe),
+				.PM_STOP(PM_STOP),
+				.PM_DONE(PM_DONE),
+                .SA(ISA),
+                .BA(IBA),
+                .CS_N(ICS_N),
+                .CKE(ICKE),
+                .RAS_N(IRAS_N),
+                .CAS_N(ICAS_N),
+                .WE_N(IWE_N)
+                );
+                
+sdr_data_path data_path1(
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .DATAIN(mDATAIN),
+                .DM(2'b00),
+                .DQOUT(DQOUT),
+                .DQM(IDQM)
+                );
+
+Sdram_FIFO 	write_fifo1(
+				.data(WR1_DATA),
+				.wrreq(WR1),
+				.wrclk(WR1_CLK),
+				.aclr(WR1_LOAD),
+				.rdreq(IN_REQ&WR_MASK[0]),
+				.rdclk(CLK),
+				.q(mDATAIN1),
+				.rdusedw(write_side_fifo_rusedw1)
+				);
+
+Sdram_FIFO 	write_fifo2(
+				.data(WR2_DATA),
+				.wrreq(WR2),
+				.wrclk(WR2_CLK),
+				.aclr(WR2_LOAD),
+				.rdreq(IN_REQ&WR_MASK[1]),
+				.rdclk(CLK),
+				.q(mDATAIN2),
+				.rdusedw(write_side_fifo_rusedw2)
+				);
+				
+assign	mDATAIN	=	(WR_MASK[0])	?	mDATAIN1	:
+										mDATAIN2	;
+
+Sdram_FIFO 	read_fifo1(
+				.data(mDATAOUT),
+				.wrreq(OUT_VALID&RD_MASK[0]),
+				.wrclk(CLK),
+				.aclr(RD1_LOAD),
+				.rdreq(RD1),
+				.rdclk(RD1_CLK),
+				.q(RD1_DATA),
+				.wrusedw(read_side_fifo_wusedw1)
+				);
+				
+Sdram_FIFO 	read_fifo2(
+				.data(mDATAOUT),
+				.wrreq(OUT_VALID&RD_MASK[1]),
+				.wrclk(CLK),
+				.aclr(RD2_LOAD),
+				.rdreq(RD2),
+				.rdclk(RD2_CLK),
+				.q(RD2_DATA),
+				.wrusedw(read_side_fifo_wusedw2)
+				);
+
+always @(posedge CLK)
+begin
+	SA      <= (ST==SC_CL+mLENGTH)			?	12'h200	:	ISA;
+    BA      <= IBA;
+    CS_N    <= ICS_N;
+    CKE     <= ICKE;
+    RAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IRAS_N;
+    CAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b1	:	ICAS_N;
+    WE_N    <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IWE_N;
+	PM_STOP	<= (ST==SC_CL+mLENGTH)			?	1'b1	:	1'b0;
+	PM_DONE	<= (ST==SC_CL+SC_RCD+mLENGTH+2)	?	1'b1	:	1'b0;
+	DQM		<= ( active && (ST>=SC_CL) )	?	(	((ST==SC_CL+mLENGTH) && Write)?	2'b11	:	2'b00	)	:	2'b11	;
+	mDATAOUT<= DQ;
+end
+
+assign  DQ = oe ? DQOUT : `DSIZE'hzzzz;
+assign	active	=	Read | Write;
+
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(RESET_N==0)
+	begin
+		CMD			<=  0;
+		ST			<=  0;
+		Pre_RD		<=  0;
+		Pre_WR		<=  0;
+		Read		<=	0;
+		Write		<=	0;
+		OUT_VALID	<=	0;
+		IN_REQ		<=	0;
+		mWR_DONE	<=	0;
+		mRD_DONE	<=	0;
+	end
+	else
+	begin
+		Pre_RD	<=	mRD;
+		Pre_WR	<=	mWR;
+		case(ST)
+		0:	begin
+				if({Pre_RD,mRD}==2'b01)
+				begin
+					Read	<=	1;
+					Write	<=	0;
+					CMD		<=	2'b01;
+					ST		<=	1;
+				end
+				else if({Pre_WR,mWR}==2'b01)
+				begin
+					Read	<=	0;
+					Write	<=	1;
+					CMD		<=	2'b10;
+					ST		<=	1;
+				end
+			end
+		1:	begin
+				if(CMDACK==1)
+				begin
+					CMD<=2'b00;
+					ST<=2;
+				end
+			end
+		default:	
+			begin	
+				if(ST!=SC_CL+SC_RCD+mLENGTH+1)
+				ST<=ST+1;
+				else
+				ST<=0;
+			end
+		endcase
+	
+		if(Read)
+		begin
+			if(ST==SC_CL+SC_RCD+1)
+			OUT_VALID	<=	1;
+			else if(ST==SC_CL+SC_RCD+mLENGTH+1)
+			begin
+				OUT_VALID	<=	0;
+				Read		<=	0;
+				mRD_DONE	<=	1;
+			end
+		end
+		else
+		mRD_DONE	<=	0;
+		
+		if(Write)
+		begin
+			if(ST==SC_CL-1)
+			IN_REQ	<=	1;
+			else if(ST==SC_CL+mLENGTH-1)
+			IN_REQ	<=	0;
+			else if(ST==SC_CL+SC_RCD+mLENGTH)
+			begin
+				Write	<=	0;
+				mWR_DONE<=	1;
+			end
+		end
+		else
+		mWR_DONE<=	0;
+
+	end
+end
+//	Internal Address & Length Control
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(!RESET_N)
+	begin
+		rWR1_ADDR		<=	0;
+		rWR2_ADDR		<=	22'h100000;
+		rRD1_ADDR		<=	0;
+		rRD2_ADDR		<=	22'h100000;
+		rWR1_MAX_ADDR	<=	640*480;
+		rWR2_MAX_ADDR	<=	22'h100000+640*480;
+		rRD1_MAX_ADDR	<=	640*480;
+		rRD2_MAX_ADDR	<=	22'h100000+640*480;
+		rWR1_LENGTH		<=	256;
+		rWR2_LENGTH		<=	256;
+		rRD1_LENGTH		<=	256;
+		rRD2_LENGTH		<=	256;
+	end
+	else
+	begin
+		//	Write Side 1
+		if(WR1_LOAD)
+		begin
+			rWR1_ADDR	<=	WR1_ADDR;
+			rWR1_LENGTH	<=	WR1_LENGTH;
+		end
+		else if(mWR_DONE&WR_MASK[0])
+		begin
+			if(rWR1_ADDR<rWR1_MAX_ADDR-rWR1_LENGTH)
+				rWR1_ADDR	<=	rWR1_ADDR+rWR1_LENGTH;
+			else
+				rWR1_ADDR	<=	WR1_ADDR;
+		end
+		//	Write Side 2
+		if(WR2_LOAD)
+		begin
+			rWR2_ADDR	<=	WR2_ADDR;
+			rWR2_LENGTH	<=	WR2_LENGTH;
+		end
+		else if(mWR_DONE&WR_MASK[1])
+		begin
+			if(rWR2_ADDR<rWR2_MAX_ADDR-rWR2_LENGTH)
+				rWR2_ADDR	<=	rWR2_ADDR+rWR2_LENGTH;
+			else
+				rWR2_ADDR	<=	WR2_ADDR;
+		end
+		//	Read Side 1
+		if(RD1_LOAD)
+		begin
+			rRD1_ADDR	<=	RD1_ADDR;
+			rRD1_LENGTH	<=	RD1_LENGTH;
+		end
+		else if(mRD_DONE&RD_MASK[0])
+		begin
+			if(rRD1_ADDR<rRD1_MAX_ADDR-rRD1_LENGTH)
+				rRD1_ADDR	<=	rRD1_ADDR+rRD1_LENGTH;
+			else
+				rRD1_ADDR	<=	RD1_ADDR;
+		end
+		//	Read Side 2
+		if(RD2_LOAD)
+		begin
+			rRD2_ADDR	<=	RD2_ADDR;
+			rRD2_LENGTH	<=	RD2_LENGTH;
+		end
+		else if(mRD_DONE&RD_MASK[1])
+		begin
+			if(rRD2_ADDR<rRD2_MAX_ADDR-rRD2_LENGTH)
+				rRD2_ADDR	<=	rRD2_ADDR+rRD2_LENGTH;
+			else
+				rRD2_ADDR	<=	RD2_ADDR;
+		end
+	end
+end
+//	Auto Read/Write Control
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(!RESET_N)
+	begin
+		mWR		<=	0;
+		mRD		<=	0;
+		mADDR	<=	0;
+		mLENGTH	<=	0;
+	end
+	else
+	begin
+		if( (mWR==0) && (mRD==0) && (ST==0) &&
+			(WR_MASK==0)	&&	(RD_MASK==0) &&
+			(WR1_LOAD==0)	&&	(RD1_LOAD==0) &&
+			(WR2_LOAD==0)	&&	(RD2_LOAD==0) )
+		begin
+			//	Write Side 1
+			if( (write_side_fifo_rusedw1 >= rWR1_LENGTH) && (rWR1_LENGTH!=0) )
+			begin
+				mADDR	<=	rWR1_ADDR;
+				mLENGTH	<=	rWR1_LENGTH;
+				WR_MASK	<=	2'b01;
+				RD_MASK	<=	2'b00;
+				mWR		<=	1;
+				mRD		<=	0;
+			end
+			//	Write Side 2
+			else if( (write_side_fifo_rusedw2 >= rWR2_LENGTH) && (rWR2_LENGTH!=0) )
+			begin
+				mADDR	<=	rWR2_ADDR;
+				mLENGTH	<=	rWR2_LENGTH;
+				WR_MASK	<=	2'b10;
+				RD_MASK	<=	2'b00;
+				mWR		<=	1;
+				mRD		<=	0;
+			end
+			//	Read Side 1
+			else if( (read_side_fifo_wusedw1 < rRD1_LENGTH) )
+			begin
+				mADDR	<=	rRD1_ADDR;
+				mLENGTH	<=	rRD1_LENGTH;
+				WR_MASK	<=	2'b00;
+				RD_MASK	<=	2'b01;
+				mWR		<=	0;
+				mRD		<=	1;				
+			end
+			//	Read Side 2
+			else if( (read_side_fifo_wusedw2 < rRD2_LENGTH) )
+			begin
+				mADDR	<=	rRD2_ADDR;
+				mLENGTH	<=	rRD2_LENGTH;
+				WR_MASK	<=	2'b00;
+				RD_MASK	<=	2'b10;
+				mWR		<=	0;
+				mRD		<=	1;
+			end
+		end
+		if(mWR_DONE)
+		begin
+			WR_MASK	<=	0;
+			mWR		<=	0;
+		end
+		if(mRD_DONE)
+		begin
+			RD_MASK	<=	0;
+			mRD		<=	0;
+		end
+	end
+end
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.qip
new file mode 100644
index 0000000..ceca5c0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "10.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Sdram_FIFO.v"]
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v
new file mode 100644
index 0000000..af2662b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v
@@ -0,0 +1,190 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: Sdram_FIFO.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 218 06/27/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module Sdram_FIFO (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	rdusedw,
+	wrfull,
+	wrusedw);
+
+	input	  aclr;
+	input	[15:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[15:0]  q;
+	output	  rdempty;
+	output	[8:0]  rdusedw;
+	output	  wrfull;
+	output	[8:0]  wrusedw;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  sub_wire0;
+	wire [15:0] sub_wire1;
+	wire  sub_wire2;
+	wire [8:0] sub_wire3;
+	wire [8:0] sub_wire4;
+	wire  wrfull = sub_wire0;
+	wire [15:0] q = sub_wire1[15:0];
+	wire  rdempty = sub_wire2;
+	wire [8:0] wrusedw = sub_wire3[8:0];
+	wire [8:0] rdusedw = sub_wire4[8:0];
+
+	dcfifo	dcfifo_component (
+				.rdclk (rdclk),
+				.wrclk (wrclk),
+				.wrreq (wrreq),
+				.aclr (aclr),
+				.data (data),
+				.rdreq (rdreq),
+				.wrfull (sub_wire0),
+				.q (sub_wire1),
+				.rdempty (sub_wire2),
+				.wrusedw (sub_wire3),
+				.rdusedw (sub_wire4),
+				.rdfull (),
+				.wrempty ());
+	defparam
+		dcfifo_component.add_ram_output_register = "OFF",
+		dcfifo_component.clocks_are_synchronized = "FALSE",
+		dcfifo_component.intended_device_family = "Cyclone",
+		dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
+		dcfifo_component.lpm_numwords = 512,
+		dcfifo_component.lpm_showahead = "OFF",
+		dcfifo_component.lpm_type = "dcfifo",
+		dcfifo_component.lpm_width = 16,
+		dcfifo_component.lpm_widthu = 9,
+		dcfifo_component.overflow_checking = "ON",
+		dcfifo_component.underflow_checking = "ON",
+		dcfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "512"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_wave*.jpg FALSE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h
new file mode 100644
index 0000000..59b473c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h
@@ -0,0 +1,60 @@
+// Address Space Parameters
+
+`define ROWSTART        8          
+`define ROWSIZE         12
+`define COLSTART        0
+`define COLSIZE         8
+`define BANKSTART       20
+`define BANKSIZE        2
+
+// Address and Data Bus Sizes
+
+`define  ASIZE           23      // total address width of the SDRAM
+`define  DSIZE           16      // Width of data bus to SDRAMS
+
+//parameter	INIT_PER	=	100;		//	For Simulation
+
+//	Controller Parameter
+////////////	133 MHz	///////////////
+/*
+parameter	INIT_PER	=	32000;
+parameter	REF_PER		=	1536;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+////////////	100 MHz	///////////////
+parameter	INIT_PER	=	24000;
+parameter	REF_PER		=	1024;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+///////////////////////////////////////
+////////////	50 MHz	///////////////
+/*
+parameter	INIT_PER	=	12000;
+parameter	REF_PER		=	512;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+
+//	SDRAM Parameter
+parameter	SDR_BL		=	(SC_PM == 1)?	3'b111	:
+							(SC_BL == 1)?	3'b000	:
+							(SC_BL == 2)?	3'b001	:
+							(SC_BL == 4)?	3'b010	:
+											3'b011	;
+parameter	SDR_BT		=	1'b0;	//	Sequential
+							//	1'b1:	//	Interteave
+parameter	SDR_CL		=	(SC_CL == 2)?	3'b10:
+											3'b11;
+ 	
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v
new file mode 100644
index 0000000..8b37dff
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v
@@ -0,0 +1,482 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	command
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module command(
+        CLK,
+        RESET_N,
+        SADDR,
+        NOP,
+        READA,
+        WRITEA,
+        REFRESH,
+        PRECHARGE,
+        LOAD_MODE,
+        REF_REQ,
+		INIT_REQ,
+		PM_STOP,
+		PM_DONE,
+        REF_ACK,
+        CM_ACK,
+        OE,
+        SA,
+        BA,
+        CS_N,
+        CKE,
+        RAS_N,
+        CAS_N,
+        WE_N
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [`ASIZE-1:0]            SADDR;                  // Address
+input                           NOP;                    // Decoded NOP command
+input                           READA;                  // Decoded READA command
+input                           WRITEA;                 // Decoded WRITEA command
+input                           REFRESH;                // Decoded REFRESH command
+input                           PRECHARGE;              // Decoded PRECHARGE command
+input                           LOAD_MODE;              // Decoded LOAD_MODE command
+input                           REF_REQ;                // Hidden refresh request
+input							INIT_REQ;				// Hidden initial request
+input							PM_STOP;				// Page mode stop
+input							PM_DONE;				// Page mode done
+output                          REF_ACK;                // Refresh request acknowledge
+output                          CM_ACK;                 // Command acknowledge
+output                          OE;                     // OE signal for data path module
+output  [11:0]                  SA;                     // SDRAM address
+output  [1:0]                   BA;                     // SDRAM bank address
+output  [1:0]                   CS_N;                   // SDRAM chip selects
+output                          CKE;                    // SDRAM clock enable
+output                          RAS_N;                  // SDRAM RAS
+output                          CAS_N;                  // SDRAM CAS
+output                          WE_N;                   // SDRAM WE_N
+            
+reg                             CM_ACK;
+reg                             REF_ACK;
+reg                             OE;
+reg     [11:0]                  SA;
+reg     [1:0]                   BA;
+reg     [1:0]                   CS_N;
+reg                             CKE;
+reg                             RAS_N;
+reg                             CAS_N;
+reg                             WE_N;
+
+// Internal signals
+reg                             do_reada;
+reg                             do_writea;
+reg                             do_refresh;
+reg                             do_precharge;
+reg                             do_load_mode;
+reg								do_initial;
+reg                             command_done;
+reg     [7:0]                   command_delay;
+reg     [1:0]                   rw_shift;
+reg                             do_act;
+reg                             rw_flag;
+reg                             do_rw;
+reg     [6:0]                   oe_shift;
+reg                             oe1;
+reg                             oe2;
+reg                             oe3;
+reg                             oe4;
+reg     [3:0]                   rp_shift;
+reg                             rp_done;
+reg								ex_read;
+reg								ex_write;
+
+wire    [`ROWSIZE - 1:0]        rowaddr;
+wire    [`COLSIZE - 1:0]        coladdr;
+wire    [`BANKSIZE - 1:0]       bankaddr;
+
+assign   rowaddr   = SADDR[`ROWSTART + `ROWSIZE - 1: `ROWSTART];          // assignment of the row address bits from SADDR
+assign   coladdr   = SADDR[`COLSTART + `COLSIZE - 1:`COLSTART];           // assignment of the column address bits
+assign   bankaddr  = SADDR[`BANKSTART + `BANKSIZE - 1:`BANKSTART];        // assignment of the bank address bits
+
+// This always block monitors the individual command lines and issues a command
+// to the next stage if there currently another command already running.
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+        begin
+                do_reada        <= 0;
+                do_writea       <= 0;
+                do_refresh      <= 0;
+                do_precharge    <= 0;
+                do_load_mode    <= 0;
+				do_initial		<= 0;
+                command_done    <= 0;
+                command_delay   <= 0;
+                rw_flag         <= 0;
+                rp_shift        <= 0;
+                rp_done         <= 0;
+				ex_read			<= 0;
+				ex_write		<= 0;
+        end
+        
+        else
+        begin
+
+//  Issue the appropriate command if the sdram is not currently busy
+			if( INIT_REQ == 1 )
+			begin
+                do_reada        <= 0;
+                do_writea       <= 0;
+                do_refresh      <= 0;
+                do_precharge    <= 0;
+                do_load_mode    <= 0;
+				do_initial		<= 1;
+                command_done    <= 0;
+                command_delay   <= 0;
+                rw_flag         <= 0;
+                rp_shift        <= 0;
+                rp_done         <= 0;
+				ex_read			<= 0;
+				ex_write		<= 0;
+			end
+			else
+			begin
+				do_initial		<= 0;
+				
+                if ((REF_REQ == 1 | REFRESH == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0         // Refresh
+                        & do_reada == 0 & do_writea == 0)
+                        do_refresh <= 1;         
+                else
+                        do_refresh <= 0;
+
+                if ((READA == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (REF_REQ == 0))    // READA
+                begin
+				        do_reada <= 1;
+						ex_read <= 1;
+				end
+                else
+                        do_reada <= 0;
+                    
+                if ((WRITEA == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (REF_REQ == 0))  // WRITEA
+                begin
+				        do_writea <= 1;
+						ex_write <= 1;
+				end
+                else
+                        do_writea <= 0;
+
+                if ((PRECHARGE == 1) & (command_done == 0) & (do_precharge == 0))	// PRECHARGE
+                        do_precharge <= 1;
+                else
+                        do_precharge <= 0;
+ 
+                if ((LOAD_MODE == 1) & (command_done == 0) & (do_load_mode == 0))	// LOADMODE
+                        do_load_mode <= 1;
+                else
+                        do_load_mode <= 0;
+                                               
+// set command_delay shift register and command_done flag
+// The command delay shift register is a timer that is used to ensure that
+// the SDRAM devices have had sufficient time to finish the last command.
+
+                if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)
+                     | (do_load_mode == 1))
+                begin
+                        command_delay <= 8'b11111111;
+                        command_done  <= 1;
+                        rw_flag <= do_reada;                                                  
+                end
+                
+                else
+                begin
+                        command_done        <= command_delay[0];                // the command_delay shift operation
+                        command_delay		<= (command_delay>>1);
+                end 
+                
+ 
+ // start additional timer that is used for the refresh, writea, reada commands               
+                if (command_delay[0] == 0 & command_done == 1)
+                begin
+                	rp_shift <= 4'b1111;
+                	rp_done <= 1;
+                end
+                else
+                begin						
+					if(SC_PM == 0)
+					begin
+						rp_shift	<= (rp_shift>>1);
+                    	rp_done		<= rp_shift[0];
+					end
+					else
+					begin
+						if( (ex_read == 0) && (ex_write == 0) )
+						begin
+							rp_shift	<= (rp_shift>>1);
+        	            	rp_done		<= rp_shift[0];
+						end
+						else
+						begin
+							if( PM_STOP==1 )
+							begin
+								rp_shift	<= (rp_shift>>1);
+        	      		      	rp_done     <= rp_shift[0];
+								ex_read		<= 1'b0;
+								ex_write	<= 1'b0;
+							end					
+						end
+					end
+                end
+			end
+        end
+end
+
+
+// logic that generates the OE signal for the data path module
+// For normal burst write he duration of OE is dependent on the configured burst length.
+// For page mode accesses(SC_PM=1) the OE signal is turned on at the start of the write command
+// and is left on until a PRECHARGE(page burst terminate) is detected.
+//
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+        begin
+                oe_shift <= 0;
+                oe1      <= 0;
+                oe2      <= 0;
+                OE       <= 0;
+        end
+        else
+        begin
+                if (SC_PM == 0)
+                begin
+                        if (do_writea == 1)
+                        begin
+                                if (SC_BL == 1)				//  Set the shift register to the appropriate
+                                        oe_shift <= 0;		// value based on burst length.
+                                else if (SC_BL == 2)
+                                        oe_shift <= 1;
+                                else if (SC_BL == 4)
+                                        oe_shift <= 7;
+                                else if (SC_BL == 8)
+                                        oe_shift <= 127;
+                                oe1 <= 1;
+                        end
+                        else 
+                        begin
+                                oe_shift <= (oe_shift>>1);
+                                oe1  <= oe_shift[0];
+                                oe2  <= oe1;
+                                oe3  <= oe2;
+                                oe4  <= oe3;
+                                if (SC_RCD == 2)
+                                        OE <= oe3;
+                                else
+                                        OE <= oe4;
+                        end
+                end
+                else
+                begin
+                        if (do_writea == 1)					 // OE generation for page mode accesses
+                                oe4   <= 1;
+                        else if (do_precharge == 1 | do_reada == 1 | do_refresh==1 | do_initial == 1 | PM_STOP==1 )
+                                oe4   <= 0;
+                        OE <= oe4;
+                end
+                               
+        end
+end
+
+
+
+
+// This always block tracks the time between the activate command and the
+// subsequent WRITEA or READA command, RC.  The shift register is set using
+// the configuration register setting SC_RCD. The shift register is loaded with
+// a single '1' with the position within the register dependent on SC_RCD.
+// When the '1' is shifted out of the register it sets so_rw which triggers
+// a writea or reada command
+//
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+        begin
+                rw_shift <= 0;
+                do_rw    <= 0;
+        end
+        
+        else
+        begin
+                
+                if ((do_reada == 1) | (do_writea == 1))
+                begin
+                        if (SC_RCD == 1)                          // Set the shift register
+                                do_rw <= 1;
+                        else if (SC_RCD == 2)
+                                rw_shift <= 1;
+                        else if (SC_RCD == 3)
+                                rw_shift <= 2;
+                end
+                else
+                begin
+                        rw_shift <= (rw_shift>>1);
+                        do_rw    <= rw_shift[0];
+                end 
+        end
+end              
+
+// This always block generates the command acknowledge, CM_ACK, signal.
+// It also generates the acknowledge signal, REF_ACK, that acknowledges
+// a refresh request that was generated by the internal refresh timer circuit.
+always @(posedge CLK or negedge RESET_N) 
+begin
+
+        if (RESET_N == 0) 
+        begin
+                CM_ACK   <= 0;
+                REF_ACK  <= 0;
+        end
+        
+        else
+        begin
+                if (do_refresh == 1 & REF_REQ == 1)                   // Internal refresh timer refresh request
+                        REF_ACK <= 1;
+                else if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)   // externa  commands
+                         | (do_load_mode))
+                        CM_ACK <= 1;
+                else
+                begin
+                        REF_ACK <= 0;
+                        CM_ACK  <= 0;
+                end
+        end
+end 
+                    
+
+
+
+
+
+
+// This always block generates the address, cs, cke, and command signals(ras,cas,wen)
+// 
+always @(posedge CLK ) begin
+        if (RESET_N==0) begin
+                SA    <= 0;
+                BA    <= 0;
+                CS_N  <= 1;
+                RAS_N <= 1;
+                CAS_N <= 1;
+                WE_N  <= 1;
+                CKE   <= 0;
+        end
+        else begin
+                CKE <= 1;
+
+// Generate SA 	
+                if (do_writea == 1 | do_reada == 1)    // ACTIVATE command is being issued, so present the row address
+                        SA <= rowaddr;
+                else
+                        SA <= coladdr;                 // else alway present column address
+                if ((do_rw==1) | (do_precharge))
+                        SA[10] <= !SC_PM;              // set SA[10] for autoprecharge read/write or for a precharge all command
+                                                       // don't set it if the controller is in page mode.           
+                if (do_precharge==1 | do_load_mode==1)
+                        BA <= 0;                       // Set BA=0 if performing a precharge or load_mode command
+                else
+                        BA <= bankaddr[1:0];           // else set it with the appropriate address bits
+		
+                if (do_refresh==1 | do_precharge==1 | do_load_mode==1 | do_initial==1)
+                        CS_N <= 0;                                    // Select both chip selects if performing
+                else                                                  // refresh, precharge(all) or load_mode
+                begin
+                        CS_N[0] <= SADDR[`ASIZE-1];                   // else set the chip selects based off of the
+                        CS_N[1] <= ~SADDR[`ASIZE-1];                  // msb address bit
+                end
+				
+				if(do_load_mode==1)
+				SA	  <= {2'b00,SDR_CL,SDR_BT,SDR_BL};
+
+
+//Generate the appropriate logic levels on RAS_N, CAS_N, and WE_N
+//depending on the issued command.
+//		
+                if ( do_refresh==1 ) begin                        // Refresh: S=00, RAS=0, CAS=0, WE=1
+                        RAS_N <= 0;
+                        CAS_N <= 0;
+                        WE_N  <= 1;
+                end
+                else if ((do_precharge==1) & ((oe4 == 1) | (rw_flag == 1))) begin      // burst terminate if write is active
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 0;
+                end
+                else if (do_precharge==1) begin                 // Precharge All: S=00, RAS=0, CAS=1, WE=0
+                        RAS_N <= 0;
+                        CAS_N <= 1;
+                        WE_N  <= 0;
+                end
+                else if (do_load_mode==1) begin                 // Mode Write: S=00, RAS=0, CAS=0, WE=0
+                        RAS_N <= 0;
+                        CAS_N <= 0;
+                        WE_N  <= 0;
+                end
+                else if (do_reada == 1 | do_writea == 1) begin  // Activate: S=01 or 10, RAS=0, CAS=1, WE=1
+                        RAS_N <= 0;
+                        CAS_N <= 1;
+                        WE_N  <= 1;
+                end
+                else if (do_rw == 1) begin                      // Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1
+                        RAS_N <= 1;
+                        CAS_N <= 0;
+                        WE_N  <= rw_flag;
+                end
+				else if (do_initial ==1) begin
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 1;				
+				end
+                else begin                                      // No Operation: RAS=1, CAS=1, WE=1
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 1;
+                end
+        end 
+end
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v
new file mode 100644
index 0000000..d7930e2
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v
@@ -0,0 +1,240 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	control_interface
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module control_interface(
+        CLK,
+        RESET_N,
+        CMD,
+        ADDR,
+        REF_ACK,
+		INIT_ACK,
+        CM_ACK,
+        NOP,
+        READA,
+        WRITEA,
+        REFRESH,
+        PRECHARGE,
+        LOAD_MODE,
+        SADDR,
+        REF_REQ,
+		INIT_REQ,
+        CMD_ACK
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [2:0]                   CMD;                    // Command input
+input   [`ASIZE-1:0]            ADDR;                   // Address
+input                           REF_ACK;                // Refresh request acknowledge
+input							INIT_ACK;				// Initial request acknowledge
+input                           CM_ACK;                 // Command acknowledge
+output                          NOP;                    // Decoded NOP command
+output                          READA;                  // Decoded READA command
+output                          WRITEA;                 // Decoded WRITEA command
+output                          REFRESH;                // Decoded REFRESH command
+output                          PRECHARGE;              // Decoded PRECHARGE command
+output                          LOAD_MODE;              // Decoded LOAD_MODE command
+output  [`ASIZE-1:0]            SADDR;                  // Registered version of ADDR
+output                          REF_REQ;                // Hidden refresh request
+output                          INIT_REQ;               // Hidden initial request
+output                          CMD_ACK;                // Command acknowledge
+
+
+            
+reg                             NOP;
+reg                             READA;
+reg                             WRITEA;
+reg                             REFRESH;
+reg                             PRECHARGE;
+reg                             LOAD_MODE;
+reg     [`ASIZE-1:0]            SADDR;
+reg                             REF_REQ;
+reg                             INIT_REQ;
+reg                             CMD_ACK;
+
+// Internal signals
+reg     [15:0]                  timer;
+reg		[15:0]					init_timer;
+
+
+
+// Command decode and ADDR register
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+        begin
+                NOP             <= 0;
+                READA           <= 0;
+                WRITEA          <= 0;
+                SADDR           <= 0;
+        end
+        
+        else
+        begin
+        
+                SADDR <= ADDR;                                  // register the address to keep proper
+                                                                // alignment with the command
+                                                             
+                if (CMD == 3'b000)                              // NOP command
+                        NOP <= 1;
+                else
+                        NOP <= 0;
+                        
+                if (CMD == 3'b001)                              // READA command
+                        READA <= 1;
+                else
+                        READA <= 0;
+                 
+                if (CMD == 3'b010)                              // WRITEA command
+                        WRITEA <= 1;
+                else
+                        WRITEA <= 0;
+                        
+        end
+end
+
+
+//  Generate CMD_ACK
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+                CMD_ACK <= 0;
+        else
+                if ((CM_ACK == 1) & (CMD_ACK == 0))
+                        CMD_ACK <= 1;
+                else
+                        CMD_ACK <= 0;
+end
+
+
+// refresh timer
+always @(posedge CLK or negedge RESET_N) begin
+        if (RESET_N == 0) 
+        begin
+                timer           <= 0;
+                REF_REQ         <= 0;
+        end        
+        else 
+        begin
+                if (REF_ACK == 1)
+				begin
+                	timer <= REF_PER;
+					REF_REQ	<=0;
+				end
+				else if (INIT_REQ == 1)
+				begin
+                	timer <= REF_PER+200;
+					REF_REQ	<=0;					
+				end
+                else
+                	timer <= timer - 1'b1;
+
+                if (timer==0)
+                    REF_REQ    <= 1;
+
+        end
+end
+
+// initial timer
+always @(posedge CLK or negedge RESET_N) begin
+        if (RESET_N == 0) 
+        begin
+                init_timer      <= 0;
+				REFRESH         <= 0;
+                PRECHARGE      	<= 0; 
+				LOAD_MODE		<= 0;
+				INIT_REQ		<= 0;
+        end        
+        else 
+        begin
+                if (init_timer < (INIT_PER+201))
+					init_timer 	<= init_timer+1;
+					
+				if (init_timer < INIT_PER)
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=1;
+				end
+				else if(init_timer == (INIT_PER+20))
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=1;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;
+				end
+				else if( 	(init_timer == (INIT_PER+40))	||
+							(init_timer == (INIT_PER+60))	||
+							(init_timer == (INIT_PER+80))	||
+							(init_timer == (INIT_PER+100))	||
+							(init_timer == (INIT_PER+120))	||
+							(init_timer == (INIT_PER+140))	||
+							(init_timer == (INIT_PER+160))	||
+							(init_timer == (INIT_PER+180))	)
+				begin
+					REFRESH		<=1;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;
+				end
+				else if(init_timer == (INIT_PER+200))
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=1;
+					INIT_REQ	<=0;				
+				end
+				else
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;									
+				end
+        end
+end
+
+endmodule
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v
new file mode 100644
index 0000000..b064bbe
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v
@@ -0,0 +1,76 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	sdr_data_path
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module sdr_data_path(
+        CLK,
+        RESET_N,
+        DATAIN,
+        DM,
+        DQOUT,
+        DQM
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [`DSIZE-1:0]            DATAIN;                 // Data input from the host
+input   [`DSIZE/8-1:0]          DM;                     // byte data masks
+output  [`DSIZE-1:0]            DQOUT;
+output  [`DSIZE/8-1:0]          DQM;                    // SDRAM data mask ouputs
+reg     [`DSIZE/8-1:0]          DQM;
+            
+
+
+// Allign the input and output data to the SDRAM control path
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+		DQM		<= `DSIZE/8-1'hF;
+        else
+ 		DQM		<=	DM;                 
+end
+
+assign DQOUT = DATAIN;
+
+endmodule
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_FIFO.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_FIFO.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_FIFO.qip
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v
new file mode 100644
index 0000000..338ae75
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v
@@ -0,0 +1,186 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	D5M CCD_Capture
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module CCD_Capture(	oDATA,
+					oDVAL,
+					oX_Cont,
+					oY_Cont,
+					oFrame_Cont,
+					iDATA,
+					iFVAL,
+					iLVAL,
+					iSTART,
+					iEND,
+					iCLK,
+					iRST
+					);
+					
+input	[11:0]	iDATA;
+input			iFVAL;
+input			iLVAL;
+input			iSTART;
+input			iEND;
+input			iCLK;
+input			iRST;
+output	[11:0]	oDATA;
+output	[15:0]	oX_Cont;
+output	[15:0]	oY_Cont;
+output	[31:0]	oFrame_Cont;
+output			oDVAL;
+reg				Pre_FVAL;
+reg				mCCD_FVAL;
+reg				mCCD_LVAL;
+reg		[11:0]	mCCD_DATA;
+reg		[15:0]	X_Cont;
+reg		[15:0]	Y_Cont;
+reg		[31:0]	Frame_Cont;
+reg				mSTART;
+
+parameter COLUMN_WIDTH = 1280;
+
+assign	oX_Cont		=	X_Cont;
+assign	oY_Cont		=	Y_Cont;
+assign	oFrame_Cont	=	Frame_Cont;
+assign	oDATA		=	mCCD_DATA;
+assign	oDVAL		=	mCCD_FVAL&mCCD_LVAL;
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	mSTART	<=	0;
+	else
+	begin
+		if(iSTART)
+		mSTART	<=	1;
+		if(iEND)
+		mSTART	<=	0;		
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		Pre_FVAL	<=	0;
+		mCCD_FVAL	<=	0;
+		mCCD_LVAL	<=	0;
+
+		X_Cont		<=	0;
+		Y_Cont		<=	0;
+	end
+	else
+	begin
+		Pre_FVAL	<=	iFVAL;
+		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
+		mCCD_FVAL	<=	1;
+		else if({Pre_FVAL,iFVAL}==2'b10)
+		mCCD_FVAL	<=	0;
+		mCCD_LVAL	<=	iLVAL;
+		if(mCCD_FVAL)
+		begin
+			if(mCCD_LVAL)
+			begin
+				if(X_Cont<(COLUMN_WIDTH-1))
+				X_Cont	<=	X_Cont+1;
+				else
+				begin
+					X_Cont	<=	0;
+					Y_Cont	<=	Y_Cont+1;
+				end
+			end
+		end
+		else
+		begin
+			X_Cont	<=	0;
+			Y_Cont	<=	0;
+		end
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	Frame_Cont	<=	0;
+	else
+	begin
+		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
+		Frame_Cont	<=	Frame_Cont+1;
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		mCCD_DATA	<=	0;
+	else if (iLVAL)
+		mCCD_DATA	<=	iDATA;
+	else
+		mCCD_DATA	<=	0;	
+end			
+
+reg	ifval_dealy;
+
+wire ifval_fedge;	
+reg	[15:0]	y_cnt_d;
+
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		y_cnt_d	<=	0;
+	else
+		y_cnt_d	<=	Y_Cont;	
+end
+
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		ifval_dealy	<=	0;
+	else
+		ifval_dealy	<=	iFVAL;	
+end
+
+assign ifval_fedge = ({ifval_dealy,iFVAL}==2'b10)?1:0;  
+
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v
new file mode 100644
index 0000000..11d3a70
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v
@@ -0,0 +1,287 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	I2C_CCD_Config
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 16/03/14  :| CCD config, spelling
+// --------------------------------------------------------------------
+
+module I2C_CCD_Config (	//	Host Side
+						iCLK,
+						iRST_N,
+						iUART_CTRL,
+						iZOOM_MODE_SW,
+						iEXPOSURE_ADJ,
+						iEXPOSURE_DEC_p,
+						//	I2C Side
+						I2C_SCLK,
+						I2C_SDAT
+						);
+						
+//	Host Side
+input			iCLK;
+input			iRST_N;
+input 			iUART_CTRL;
+input 			iZOOM_MODE_SW;
+
+//	I2C Side
+output		I2C_SCLK;
+inout		I2C_SDAT;
+
+//	Internal Registers/Wires
+reg	[15:0]	mI2C_CLK_DIV;
+reg	[31:0]	mI2C_DATA;
+reg			mI2C_CTRL_CLK;
+reg			mI2C_GO;
+wire		mI2C_END;
+wire		mI2C_ACK;
+reg	[23:0]	LUT_DATA;
+reg	[5:0]	LUT_INDEX;
+reg	[3:0]	mSetup_ST;
+
+//////////////   CMOS sensor registers setting //////////////////////
+
+input 		iEXPOSURE_ADJ;
+input		iEXPOSURE_DEC_p;	
+
+parameter 	default_exposure 			= 16'h07c0;
+parameter 	exposure_change_value	 	= 16'd200;
+
+
+// `define 	ENABLE_TEST_PATTERN 1
+
+
+reg	[24:0]	combo_cnt;
+wire		combo_pulse;
+
+reg	[1:0]	izoom_mode_sw_delay;
+
+reg	[3:0]	iexposure_adj_delay;
+wire		exposure_adj_set;	
+wire		exposure_adj_reset;
+reg	[15:0]	sensor_exposure;
+
+wire [23:0] sensor_start_row;
+wire [23:0] sensor_start_column;
+wire [23:0] sensor_row_size;
+wire [23:0] sensor_column_size; 
+wire [23:0] sensor_row_mode;
+wire [23:0] sensor_column_mode;
+
+assign sensor_start_row 		= iZOOM_MODE_SW ?  24'h010036 : 24'h010000;
+assign sensor_start_column 		= iZOOM_MODE_SW ?  24'h020010 : 24'h020000;
+assign sensor_row_size	 		= iZOOM_MODE_SW ?  24'h0303BF : 24'h03077F;
+assign sensor_column_size 		= iZOOM_MODE_SW ?  24'h0404FF : 24'h0409FF;
+assign sensor_row_mode 			= iZOOM_MODE_SW ?  24'h220000 : 24'h220011;
+assign sensor_column_mode		= iZOOM_MODE_SW ?  24'h230000 : 24'h230011;
+
+	
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			begin
+				iexposure_adj_delay <= 0;
+			end
+		else 
+			begin
+				iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};		
+			end	
+	end
+
+assign 	exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
+assign  exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;		
+
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			sensor_exposure <= default_exposure;
+		else if (exposure_adj_set|combo_pulse)
+			begin
+				if (iEXPOSURE_DEC_p)
+					begin
+						if ((sensor_exposure < exposure_change_value)||
+							(sensor_exposure == 16'h0))
+							sensor_exposure <= 0;
+						else	
+							sensor_exposure <= sensor_exposure - exposure_change_value;
+					end		
+				else
+					begin
+						if (((16'hffff -sensor_exposure) <exposure_change_value)||
+							(sensor_exposure == 16'hffff))
+							sensor_exposure <= 16'hffff;
+						else
+							sensor_exposure <= sensor_exposure + exposure_change_value;	
+					end		
+			end
+	end			
+				
+		
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			combo_cnt <= 0;
+		else if (!iexposure_adj_delay[3])
+			combo_cnt <= combo_cnt + 1;
+		else
+			combo_cnt <= 0;	
+	end
+	
+assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;				
+		
+wire	i2c_reset;		
+
+assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
+
+/////////////////////////////////////////////////////////////////////
+
+//	Clock Setting
+parameter	CLK_Freq	=	50000000;	//	50	MHz
+parameter	I2C_Freq	=	20000;		//	20	KHz
+//	LUT Data Number
+parameter	LUT_SIZE	=	25;
+
+/////////////////////	I2C Control Clock	////////////////////////
+always@(posedge iCLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		mI2C_CTRL_CLK	<=	0;
+		mI2C_CLK_DIV	<=	0;
+	end
+	else
+	begin
+		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
+		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
+		else
+		begin
+			mI2C_CLK_DIV	<=	0;
+			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
+		end
+	end
+end
+////////////////////////////////////////////////////////////////////
+I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),		//	Controller Work Clock
+						.I2C_SCLK(I2C_SCLK),		//	I2C CLOCK
+ 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),		//	I2C DATA
+						.I2C_DATA(mI2C_DATA),		//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+						.GO(mI2C_GO),      			//	GO transfor
+						.END(mI2C_END),				//	END transfor 
+						.ACK(mI2C_ACK),				//	ACK
+						.RESET(i2c_reset)
+					);
+////////////////////////////////////////////////////////////////////
+//////////////////////	Config Control	////////////////////////////
+//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
+always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+
+	end
+
+	else if(LUT_INDEX<LUT_SIZE)
+		begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_DATA	<=	{8'hBA,LUT_DATA};
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1:	begin
+					if(mI2C_END)
+					begin
+						if(!mI2C_ACK)
+						mSetup_ST	<=	2;
+						else
+						mSetup_ST	<=	0;							
+						mI2C_GO		<=	0;
+					end
+				end
+			2:	begin
+					LUT_INDEX	<=	LUT_INDEX+1;
+					mSetup_ST	<=	0;
+				end
+			endcase
+		end
+end
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT	  //////////////////////////		
+always
+begin
+	case(LUT_INDEX)
+	0	:	LUT_DATA	<=	24'h000000;
+	1	:	LUT_DATA	<=	24'h20c000;				//	Mirror Row and Columns
+	2	:	LUT_DATA	<=	{8'h09,sensor_exposure};//	Exposure
+	3	:	LUT_DATA	<=	24'h050000;				//	H_Blanking
+	4	:	LUT_DATA	<=	24'h060019;				//	V_Blanking	
+	5	:	LUT_DATA	<=	24'h0A8000;				//	change latch
+	6	:	LUT_DATA	<=	24'h2B000b;				//	Green 1 Gain
+	7	:	LUT_DATA	<=	24'h2C000f;				//	Blue Gain
+	8	:	LUT_DATA	<=	24'h2D000f;				//	Red Gain
+	9	:	LUT_DATA	<=	24'h2E000b;				//	Green 2 Gain
+	10	:	LUT_DATA	<=	24'h100051;				//	set up PLL power on
+	11	:	LUT_DATA	<=	24'h111807;				//	PLL_m_Factor<<8+PLL_n_Divider
+	12	:	LUT_DATA	<=	24'h120002;				//	PLL_p1_Divider
+	13	:	LUT_DATA	<=	24'h100053;				//	set USE PLL	 
+	14	:	LUT_DATA	<=	24'h980000;				//	disble calibration 	
+`ifdef ENABLE_TEST_PATTERN
+	15	:	LUT_DATA	<=	24'hA00001;				//	Test pattern control 	
+	16	:	LUT_DATA	<=	24'hA10123;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20456;				//	Test red pattern value
+`else
+	15	:	LUT_DATA	<=	24'hA00000;				//	Test pattern control 
+	16	:	LUT_DATA	<=	24'hA10000;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20FFF;				//	Test red pattern value
+`endif
+	18	:	LUT_DATA	<=	sensor_start_row 	;	//	set start row	
+	19	:	LUT_DATA	<=	sensor_start_column ;	//	set start column 	
+
+	20	:	LUT_DATA	<=	sensor_row_size;		//	set row size	
+	21	:	LUT_DATA	<=	sensor_column_size;		//	set column size
+	22	:	LUT_DATA	<=	sensor_row_mode;		//	set row mode in bin mode
+	23	:	LUT_DATA	<=	sensor_column_mode;		//	set column mode	 in bin mode
+	24	:	LUT_DATA	<=	24'h4901A8;				//	row black target		
+	default:LUT_DATA	<=	24'h000000;
+	endcase
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v.bak
new file mode 100644
index 0000000..81810a8
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v.bak
@@ -0,0 +1,282 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	I2C_CCD_Config
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module I2C_CCD_Config (	//	Host Side
+						iCLK,
+						iRST_N,
+						iUART_CTRL,
+						iZOOM_MODE_SW,
+						iEXPOSURE_ADJ,
+						iEXPOSURE_DEC_p,
+						//	I2C Side
+						I2C_SCLK,
+						I2C_SDAT
+						);
+						
+//	Host Side
+input			iCLK;
+input			iRST_N;
+input 			iUART_CTRL;
+input 			iZOOM_MODE_SW;
+
+//	I2C Side
+output		I2C_SCLK;
+inout		I2C_SDAT;
+
+//	Internal Registers/Wires
+reg	[15:0]	mI2C_CLK_DIV;
+reg	[31:0]	mI2C_DATA;
+reg			mI2C_CTRL_CLK;
+reg			mI2C_GO;
+wire		mI2C_END;
+wire		mI2C_ACK;
+reg	[23:0]	LUT_DATA;
+reg	[5:0]	LUT_INDEX;
+reg	[3:0]	mSetup_ST;
+
+//////////////   CMOS sensor registers setting //////////////////////
+
+input 		iEXPOSURE_ADJ;
+input		iEXPOSURE_DEC_p;	
+
+parameter 	default_exposure 			= 16'h07c0;
+parameter 	exposure_change_value	 	= 16'd200;
+
+reg	[24:0]	combo_cnt;
+wire		combo_pulse;
+
+reg	[1:0]	izoom_mode_sw_delay;
+
+reg	[3:0]	iexposure_adj_delay;
+wire		exposure_adj_set;	
+wire		exposure_adj_reset;
+reg	[15:0]	senosr_exposure;
+
+wire [23:0] sensor_start_row;
+wire [23:0] sensor_start_column;
+wire [23:0] sensor_row_size;
+wire [23:0] sensor_column_size; 
+wire [23:0] sensor_row_mode;
+wire [23:0] sensor_column_mode;
+
+assign sensor_start_row 		= iZOOM_MODE_SW ?  24'h010036 : 24'h010000;
+assign sensor_start_column 		= iZOOM_MODE_SW ?  24'h020010 : 24'h020000;
+assign sensor_row_size	 		= iZOOM_MODE_SW ?  24'h0303BF : 24'h03077F;
+assign sensor_column_size 		= iZOOM_MODE_SW ?  24'h0404FF : 24'h0409FF;
+assign sensor_row_mode 			= iZOOM_MODE_SW ?  24'h220000 : 24'h220011;
+assign sensor_column_mode		= iZOOM_MODE_SW ?  24'h230000 : 24'h230011;
+
+	
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			begin
+				iexposure_adj_delay <= 0;
+			end
+		else 
+			begin
+				iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};		
+			end	
+	end
+
+assign 	exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
+assign  exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;		
+
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			senosr_exposure <= default_exposure;
+		else if (exposure_adj_set|combo_pulse)
+			begin
+				if (iEXPOSURE_DEC_p)
+					begin
+						if ((senosr_exposure < exposure_change_value)||
+							(senosr_exposure == 16'h0))
+							senosr_exposure <= 0;
+						else	
+							senosr_exposure <= senosr_exposure - exposure_change_value;
+					end		
+				else
+					begin
+						if (((16'hffff -senosr_exposure) <exposure_change_value)||
+							(senosr_exposure == 16'hffff))
+							senosr_exposure <= 16'hffff;
+						else
+							senosr_exposure <= senosr_exposure + exposure_change_value;	
+					end		
+			end
+	end			
+				
+		
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			combo_cnt <= 0;
+		else if (!iexposure_adj_delay[3])
+			combo_cnt <= combo_cnt + 1;
+		else
+			combo_cnt <= 0;	
+	end
+	
+assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;				
+		
+wire	i2c_reset;		
+
+assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
+
+/////////////////////////////////////////////////////////////////////
+
+//	Clock Setting
+parameter	CLK_Freq	=	50000000;	//	50	MHz
+parameter	I2C_Freq	=	20000;		//	20	KHz
+//	LUT Data Number
+parameter	LUT_SIZE	=	25;
+
+/////////////////////	I2C Control Clock	////////////////////////
+always@(posedge iCLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		mI2C_CTRL_CLK	<=	0;
+		mI2C_CLK_DIV	<=	0;
+	end
+	else
+	begin
+		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
+		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
+		else
+		begin
+			mI2C_CLK_DIV	<=	0;
+			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
+		end
+	end
+end
+////////////////////////////////////////////////////////////////////
+I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),		//	Controller Work Clock
+						.I2C_SCLK(I2C_SCLK),		//	I2C CLOCK
+ 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),		//	I2C DATA
+						.I2C_DATA(mI2C_DATA),		//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+						.GO(mI2C_GO),      			//	GO transfor
+						.END(mI2C_END),				//	END transfor 
+						.ACK(mI2C_ACK),				//	ACK
+						.RESET(i2c_reset)
+					);
+////////////////////////////////////////////////////////////////////
+//////////////////////	Config Control	////////////////////////////
+//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
+always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+
+	end
+
+	else if(LUT_INDEX<LUT_SIZE)
+		begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_DATA	<=	{8'hBA,LUT_DATA};
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1:	begin
+					if(mI2C_END)
+					begin
+						if(!mI2C_ACK)
+						mSetup_ST	<=	2;
+						else
+						mSetup_ST	<=	0;							
+						mI2C_GO		<=	0;
+					end
+				end
+			2:	begin
+					LUT_INDEX	<=	LUT_INDEX+1;
+					mSetup_ST	<=	0;
+				end
+			endcase
+		end
+end
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT	  //////////////////////////		
+always
+begin
+	case(LUT_INDEX)
+	0	:	LUT_DATA	<=	24'h000000;
+	1	:	LUT_DATA	<=	24'h20c000;				//	Mirror Row and Columns
+	2	:	LUT_DATA	<=	{8'h09,senosr_exposure};//	Exposure
+	3	:	LUT_DATA	<=	24'h050000;				//	H_Blanking
+	4	:	LUT_DATA	<=	24'h060019;				//	V_Blanking	
+	5	:	LUT_DATA	<=	24'h0A8000;				//	change latch
+	6	:	LUT_DATA	<=	24'h2B000b;				//	Green 1 Gain
+	7	:	LUT_DATA	<=	24'h2C000f;				//	Blue Gain
+	8	:	LUT_DATA	<=	24'h2D000f;				//	Red Gain
+	9	:	LUT_DATA	<=	24'h2E000b;				//	Green 2 Gain
+	10	:	LUT_DATA	<=	24'h100051;				//	set up PLL power on
+	11	:	LUT_DATA	<=	24'h111807;				//	PLL_m_Factor<<8+PLL_n_Divider
+	12	:	LUT_DATA	<=	24'h120002;				//	PLL_p1_Divider
+	13	:	LUT_DATA	<=	24'h100053;				//	set USE PLL	 
+	14	:	LUT_DATA	<=	24'h980000;				//	disble calibration 	
+`ifdef ENABLE_TEST_PATTERN
+	15	:	LUT_DATA	<=	24'hA00001;				//	Test pattern control 	
+	16	:	LUT_DATA	<=	24'hA10123;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20456;				//	Test red pattern value
+`else
+	15	:	LUT_DATA	<=	24'hA00000;				//	Test pattern control 
+	16	:	LUT_DATA	<=	24'hA10000;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20FFF;				//	Test red pattern value
+`endif
+	18	:	LUT_DATA	<=	sensor_start_row 	;	//	set start row	
+	19	:	LUT_DATA	<=	sensor_start_column ;	//	set start column 	
+
+	20	:	LUT_DATA	<=	sensor_row_size;		//	set row size	
+	21	:	LUT_DATA	<=	sensor_column_size;		//	set column size
+	22	:	LUT_DATA	<=	sensor_row_mode;		//	set row mode in bin mode
+	23	:	LUT_DATA	<=	sensor_column_mode;		//	set column mode	 in bin mode
+	24	:	LUT_DATA	<=	24'h4901A8;				//	row black target		
+	default:LUT_DATA	<=	24'h000000;
+	endcase
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v
new file mode 100644
index 0000000..3740541
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v
@@ -0,0 +1,150 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2005 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altrea Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL or Verilog source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:i2c controller
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Joe Yang          :| 05/07/10  :|      Initial Revision
+// --------------------------------------------------------------------
+module I2C_Controller (
+	CLOCK,
+	I2C_SCLK,//I2C CLOCK
+ 	I2C_SDAT,//I2C DATA
+	I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+	GO,      //GO transfor
+	END,     //END transfor 
+
+	ACK,      //ACK
+	RESET
+);
+	input  CLOCK;
+	input  [31:0]I2C_DATA;	
+	input  GO;
+	input  RESET;	
+ 	inout  I2C_SDAT;	
+	output I2C_SCLK;
+	output END;	
+	output ACK;
+
+
+reg SDO;
+reg SCLK;
+reg END;
+reg [31:0]SD;
+reg [6:0]SD_COUNTER;
+
+wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=39))? ~CLOCK :0 );
+wire I2C_SDAT=SDO?1'bz:0 ;
+
+reg ACK1,ACK2,ACK3,ACK4;
+wire ACK=ACK1 | ACK2 |ACK3 |ACK4;
+
+//--I2C COUNTER
+always @(negedge RESET or posedge CLOCK ) begin
+if (!RESET) SD_COUNTER=6'b111111;
+else begin
+if (GO==0) 
+	SD_COUNTER=0;
+	else 
+	if (SD_COUNTER < 41) SD_COUNTER=SD_COUNTER+1;	
+end
+end
+//----
+
+always @(negedge RESET or  posedge CLOCK ) begin
+if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0;ACK4=0; END=1; end
+else
+case (SD_COUNTER)
+	6'd0  : begin ACK1=0 ;ACK2=0 ;ACK3=0 ;ACK4=0 ; END=0; SDO=1; SCLK=1;end
+	//start
+	6'd1  : begin SD=I2C_DATA;SDO=0;end
+	6'd2  : SCLK=0;
+	//SLAVE ADDR
+	6'd3  : SDO=SD[31];
+	6'd4  : SDO=SD[30];
+	6'd5  : SDO=SD[29];
+	6'd6  : SDO=SD[28];
+	6'd7  : SDO=SD[27];
+	6'd8  : SDO=SD[26];
+	6'd9  : SDO=SD[25];
+	6'd10 : SDO=SD[24];	
+	6'd11 : SDO=1'b1;//ACK
+
+	//SUB ADDR
+	6'd12  : begin SDO=SD[23]; ACK1=I2C_SDAT; end
+	6'd13  : SDO=SD[22];
+	6'd14  : SDO=SD[21];
+	6'd15  : SDO=SD[20];
+	6'd16  : SDO=SD[19];
+	6'd17  : SDO=SD[18];
+	6'd18  : SDO=SD[17];
+	6'd19  : SDO=SD[16];
+	6'd20  : SDO=1'b1;//ACK
+
+	//DATA
+	6'd21  : begin SDO=SD[15]; ACK2=I2C_SDAT; end
+	6'd22  : SDO=SD[14];
+	6'd23  : SDO=SD[13];
+	6'd24  : SDO=SD[12];
+	6'd25  : SDO=SD[11];
+	6'd26  : SDO=SD[10];
+	6'd27  : SDO=SD[9];
+	6'd28  : SDO=SD[8];
+	6'd29  : SDO=1'b1;//ACK
+
+	//DATA
+	6'd30  : begin SDO=SD[7]; ACK3=I2C_SDAT; end
+	6'd31  : SDO=SD[6];
+	6'd32  : SDO=SD[5];
+	6'd33  : SDO=SD[4];
+	6'd34  : SDO=SD[3];
+	6'd35  : SDO=SD[2];
+	6'd36  : SDO=SD[1];
+	6'd37  : SDO=SD[0];
+	6'd38  : SDO=1'b1;//ACK
+
+	
+	//stop
+    6'd39 : begin SDO=1'b0;	SCLK=1'b0; ACK4=I2C_SDAT; end	
+    6'd40 : SCLK=1'b1; 
+    6'd41 : begin SDO=1'b1; END=1; end 
+
+endcase
+end
+
+
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.bsf
new file mode 100644
index 0000000..b7b5b56
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.bsf
@@ -0,0 +1,77 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 184 128)
+	(text "Line_Buffer" (rect 60 1 135 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "shiftin[11..0]" (rect 0 0 69 14)(font "Arial" (font_size 8)))
+		(text "shiftin[11..0]" (rect 20 34 78 47)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 20 50 43 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clken" (rect 20 66 44 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 184 40)
+		(output)
+		(text "shiftout[11..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
+		(text "shiftout[11..0]" (rect 99 34 163 47)(font "Arial" (font_size 8)))
+		(line (pt 184 40)(pt 168 40)(line_width 3))
+	)
+	(port
+		(pt 184 56)
+		(output)
+		(text "taps1x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "taps1x[11..0]" (rect 102 50 162 63)(font "Arial" (font_size 8)))
+		(line (pt 184 56)(pt 168 56)(line_width 3))
+	)
+	(port
+		(pt 184 72)
+		(output)
+		(text "taps0x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "taps0x[11..0]" (rect 102 66 162 79)(font "Arial" (font_size 8)))
+		(line (pt 184 72)(pt 168 72)(line_width 3))
+	)
+	(drawing
+		(text "altshift_taps" (rect 63 18 119 31)(font "Arial" (font_size 8)))
+		(text "Number of taps 2" (rect 19 90 93 102)(font "Arial" ))
+		(text "Tap distance 1280" (rect 19 100 95 112)(font "Arial" ))
+		(line (pt 16 16)(pt 168 16)(line_width 1))
+		(line (pt 168 16)(pt 168 112)(line_width 1))
+		(line (pt 168 112)(pt 16 112)(line_width 1))
+		(line (pt 16 112)(pt 16 16)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v
new file mode 100644
index 0000000..09482ce
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v
@@ -0,0 +1,111 @@
+// megafunction wizard: %Shift register (RAM-based)%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altshift_taps 
+
+// ============================================================
+// File Name: Line_Buffer.v
+// Megafunction Name(s):
+// 			altshift_taps
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module Line_Buffer (
+	clken,
+	clock,
+	shiftin,
+	shiftout,
+	taps0x,
+	taps1x);
+
+	input	  clken;
+	input	  clock;
+	input	[11:0]  shiftin;
+	output	[11:0]  shiftout;
+	output	[11:0]  taps0x;
+	output	[11:0]  taps1x;
+
+	wire [23:0] sub_wire0;
+	wire [11:0] sub_wire3;
+	wire [23:12] sub_wire1 = sub_wire0[23:12];
+	wire [11:0] sub_wire2 = sub_wire0[11:0];
+	wire [11:0] taps1x = sub_wire1[23:12];
+	wire [11:0] taps0x = sub_wire2[11:0];
+	wire [11:0] shiftout = sub_wire3[11:0];
+
+	altshift_taps	altshift_taps_component (
+				.clken (clken),
+				.clock (clock),
+				.shiftin (shiftin),
+				.taps (sub_wire0),
+				.shiftout (sub_wire3));
+	defparam
+		altshift_taps_component.lpm_type = "altshift_taps",
+		altshift_taps_component.number_of_taps = 2,
+		altshift_taps_component.tap_distance = 1280,
+		altshift_taps_component.width = 12;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
+// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "1280"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "12"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
+// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "2"
+// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "1280"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: shiftin 0 0 12 0 INPUT NODEFVAL shiftin[11..0]
+// Retrieval info: USED_PORT: shiftout 0 0 12 0 OUTPUT NODEFVAL shiftout[11..0]
+// Retrieval info: USED_PORT: taps0x 0 0 12 0 OUTPUT NODEFVAL taps0x[11..0]
+// Retrieval info: USED_PORT: taps1x 0 0 12 0 OUTPUT NODEFVAL taps1x[11..0]
+// Retrieval info: CONNECT: @shiftin 0 0 12 0 shiftin 0 0 12 0
+// Retrieval info: CONNECT: shiftout 0 0 12 0 @shiftout 0 0 12 0
+// Retrieval info: CONNECT: taps0x 0 0 12 0 @taps 0 0 12 0
+// Retrieval info: CONNECT: taps1x 0 0 12 0 @taps 0 0 12 12
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v
new file mode 100644
index 0000000..16493c7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v
@@ -0,0 +1,128 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	RAW2RGB
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module RAW2RGB(	oRed,
+				oGreen,
+				oBlue,
+				oDVAL,
+				iX_Cont,
+				iY_Cont,
+				iDATA,
+				iDVAL,
+				iCLK,
+				iRST
+				);
+
+input	[10:0]	iX_Cont;
+input	[10:0]	iY_Cont;
+input	[11:0]	iDATA;
+input			iDVAL;
+input			iCLK;
+input			iRST;
+output	[11:0]	oRed;
+output	[11:0]	oGreen;
+output	[11:0]	oBlue;
+output			oDVAL;
+wire	[11:0]	mDATA_0;
+wire	[11:0]	mDATA_1;
+reg		[11:0]	mDATAd_0;
+reg		[11:0]	mDATAd_1;
+reg		[11:0]	mCCD_R;
+reg		[12:0]	mCCD_G;
+reg		[11:0]	mCCD_B;
+reg				mDVAL;
+
+assign	oRed	=	mCCD_R[11:0];
+assign	oGreen	=	mCCD_G[12:1];
+assign	oBlue	=	mCCD_B[11:0];
+assign	oDVAL	=	mDVAL;
+
+Line_Buffer 	u0	(	.clken(iDVAL),
+						.clock(iCLK),
+						.shiftin(iDATA),
+						.taps0x(mDATA_1),
+						.taps1x(mDATA_0)	);
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		mCCD_R	<=	0;
+		mCCD_G	<=	0;
+		mCCD_B	<=	0;
+		mDATAd_0<=	0;
+		mDATAd_1<=	0;
+		mDVAL	<=	0;
+	end
+	else
+	begin
+		mDATAd_0	<=	mDATA_0;
+		mDATAd_1	<=	mDATA_1;
+		mDVAL		<=	{iY_Cont[0]|iX_Cont[0]}	?	1'b0	:	iDVAL;
+		if({iY_Cont[0],iX_Cont[0]}==2'b10)
+		begin
+			mCCD_R	<=	mDATA_0;
+			mCCD_G	<=	mDATAd_0+mDATA_1;
+			mCCD_B	<=	mDATAd_1;
+		end	
+		else if({iY_Cont[0],iX_Cont[0]}==2'b11)
+		begin
+			mCCD_R	<=	mDATAd_0;
+			mCCD_G	<=	mDATA_0+mDATAd_1;
+			mCCD_B	<=	mDATA_1;
+		end
+		else if({iY_Cont[0],iX_Cont[0]}==2'b00)
+		begin
+			mCCD_R	<=	mDATA_1;
+			mCCD_G	<=	mDATA_0+mDATAd_1;
+			mCCD_B	<=	mDATAd_0;
+		end
+		else if({iY_Cont[0],iX_Cont[0]}==2'b01)
+		begin
+			mCCD_R	<=	mDATAd_1;
+			mCCD_G	<=	mDATAd_0+mDATA_1;
+			mCCD_B	<=	mDATA_0;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v
new file mode 100644
index 0000000..578a964
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v
@@ -0,0 +1,74 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	Reset_Delay
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module	Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2);
+input		iCLK;
+input		iRST;
+output reg	oRST_0;
+output reg	oRST_1;
+output reg	oRST_2;
+
+reg	[31:0]	Cont;
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		Cont	<=	0;
+		oRST_0	<=	0;
+		oRST_1	<=	0;
+		oRST_2	<=	0;
+	end
+	else
+	begin
+		if(Cont!=32'h11FFFFF)
+		Cont	<=	Cont+1;
+		if(Cont>=32'h1FFFFF)
+		oRST_0	<=	1;
+		if(Cont>=32'h2FFFFF)
+		oRST_1	<=	1;
+		if(Cont>=32'h11FFFFF)
+		oRST_2	<=	1;
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v
new file mode 100644
index 0000000..2756db0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v
@@ -0,0 +1,70 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	SEG7_LUT
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module SEG7_LUT	(	oSEG,iDIG	);
+input	[3:0]	iDIG;
+output	[6:0]	oSEG;
+reg		[6:0]	oSEG;
+
+always @(iDIG)
+begin
+		case(iDIG)
+		4'h1: oSEG = 7'b1111001;	// ---t----
+		4'h2: oSEG = 7'b0100100; 	// |	  |
+		4'h3: oSEG = 7'b0110000; 	// lt	 rt
+		4'h4: oSEG = 7'b0011001; 	// |	  |
+		4'h5: oSEG = 7'b0010010; 	// ---m----
+		4'h6: oSEG = 7'b0000010; 	// |	  |
+		4'h7: oSEG = 7'b1111000; 	// lb	 rb
+		4'h8: oSEG = 7'b0000000; 	// |	  |
+		4'h9: oSEG = 7'b0011000; 	// ---b----
+		4'ha: oSEG = 7'b0001000;
+		4'hb: oSEG = 7'b0000011;
+		4'hc: oSEG = 7'b1000110;
+		4'hd: oSEG = 7'b0100001;
+		4'he: oSEG = 7'b0000110;
+		4'hf: oSEG = 7'b0001110;
+		4'h0: oSEG = 7'b1000000;
+		endcase
+end
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v
new file mode 100644
index 0000000..e84af4e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v
@@ -0,0 +1,56 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	SEG7_LUT_8
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module SEG7_LUT_8 (	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG );
+input	[31:0]	iDIG;
+output	[6:0]	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7;
+
+SEG7_LUT	u0	(	oSEG0,iDIG[3:0]		);
+SEG7_LUT	u1	(	oSEG1,iDIG[7:4]		);
+SEG7_LUT	u2	(	oSEG2,iDIG[11:8]	);
+SEG7_LUT	u3	(	oSEG3,iDIG[15:12]	);
+SEG7_LUT	u4	(	oSEG4,iDIG[19:16]	);
+SEG7_LUT	u5	(	oSEG5,iDIG[23:20]	);
+SEG7_LUT	u6	(	oSEG6,iDIG[27:24]	);
+SEG7_LUT	u7	(	oSEG7,iDIG[31:28]	);
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf
new file mode 100644
index 0000000..7e16307
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf
@@ -0,0 +1,1741 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
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+		(text "VGA_CLK" (rect 226 379 275 391)(font "Arial" ))
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+		(line (pt 288 448)(pt 272 448)(line_width 3))
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+	(drawing
+		(line (pt 8 8)(pt 24 8))
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+	(text "fifo_inst2" (rect 8 88 55 100)(font "Arial" ))
+	(port
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+		(line (pt 0 64)(pt 16 64))
+	)
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+		(line (pt 0 48)(pt 16 48))
+	)
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+		(text "aclr" (rect 24 72 45 86)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 16 80))
+	)
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+		(output)
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+		(line (pt 144 32)(pt 128 32)(line_width 3))
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+		(text "taps[]" (rect 97 41 128 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(parameter
+		"NUMBER_OF_TAPS"
+		"3"
+		"Number of output taps, each separated by TAP_DISTANCE clock cycles"
+	)
+	(parameter
+		"TAP_DISTANCE"
+		"800"
+		"Number of shift positions between output taps"
+	)
+	(parameter
+		"WIDTH"
+		"30"
+		"Number of bits for the shiftin input"
+	)
+	(drawing
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+		(line (pt 16 40)(pt 24 48))
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+	(pt 1464 880)
+	(pt 1672 880)
+	(bus)
+)
+(connector
+	(text "SW[7..0]" (rect 1474 896 1517 908)(font "Arial" ))
+	(pt 1464 912)
+	(pt 1672 912)
+	(bus)
+)
+(connector
+	(text "R[9..0],G[9..0],B[9..0]" (rect 1474 912 1582 924)(font "Arial" ))
+	(pt 1464 928)
+	(pt 1672 928)
+	(bus)
+)
+(connector
+	(text "VGA_CLK" (rect 1594 928 1643 940)(font "Arial" ))
+	(pt 1584 944)
+	(pt 1672 944)
+)
+(connector
+	(text "MOUSE_X[9..0],MOUSE_Y[9..0]" (rect 1472 880 1631 892)(font "Arial" ))
+	(pt 1464 896)
+	(pt 1672 896)
+	(bus)
+)
+(connector
+	(pt 1512 960)
+	(pt 1672 960)
+)
+(connector
+	(text "KEY[0]" (rect 1618 960 1653 972)(font "Arial" ))
+	(pt 1608 976)
+	(pt 1672 976)
+)
+(connector
+	(text "VGA_MOUSE_OUT[29..0]" (rect 2002 864 2129 876)(font "Arial" ))
+	(pt 1960 880)
+	(pt 2192 880)
+	(bus)
+)
+(connector
+	(text "<<__$DEF_ALIAS133>>" (rect 1954 1096 2072 1108)(font "Arial" )(invisible))
+	(pt 2304 1112)
+	(pt 1944 1112)
+	(bus)
+)
+(connector
+	(text "VGA_CLK" (rect 1626 1112 1675 1124)(font "Arial" ))
+	(pt 1616 1128)
+	(pt 1704 1128)
+)
+(connector
+	(pt 1544 1144)
+	(pt 1704 1144)
+)
+(connector
+	(text "KEY[0]" (rect 1650 1144 1685 1156)(font "Arial" ))
+	(pt 1640 1160)
+	(pt 1704 1160)
+)
+(connector
+	(text "RGB_TAP[89..0]" (rect 1602 1096 1683 1108)(font "Arial" ))
+	(pt 1704 1112)
+	(pt 1592 1112)
+	(bus)
+)
+(connector
+	(text "RGB_TAP[89..0]" (rect 2050 488 2131 500)(font "Arial" ))
+	(pt 2040 504)
+	(pt 2152 504)
+	(bus)
+)
+(junction (pt 1008 944))
+(text "MEMORY" (rect 1464 192 1517 206)(font "Arial" (font_size 8)))
+(text "PS/2 MOUSE CONTROLLER" (rect 760 992 1078 1014)(font "Arial" (font_size 14)))
+(text "PS/2 Interface" (rect 1088 736 1168 750)(font "Arial" (font_size 8)))
+(text "Mouse Buttons" (rect 1112 768 1196 782)(font "Arial" (font_size 8)))
+(text "Mouse XY Coordinates" (rect 1112 816 1242 830)(font "Arial" (font_size 8)))
+(text "7-Segments Mouse XY Coordinates" (rect 1112 864 1314 878)(font "Arial" (font_size 8)))
+(text "DIGITAL CAMERA" (rect 1416 488 1517 502)(font "Arial" (font_size 8)))
+(text "Hardware Block generated by the High-Level Synthesis Tool" (rect 1568 816 2229 838)(font "Arial" (font_size 14)(bold)))
+(text "Line Buffer" (rect 1912 376 2024 398)(font "Arial" (font_size 14)))
+(text "RED     GREEN    BLUE" (rect 2368 392 2580 410)(font "Arial" (font_size 12)))
+(text "RED     GREEN    BLUE" (rect 2368 584 2580 602)(font "Arial" (font_size 12)))
+(text "RED     GREEN    BLUE" (rect 2368 536 2580 554)(font "Arial" (font_size 12)))
+(text "RED     GREEN    BLUE" (rect 2368 488 2580 506)(font "Arial" (font_size 12)))
+(text "RED     GREEN    BLUE" (rect 2368 440 2580 458)(font "Arial" (font_size 12)))
+(text "149..120" (rect 2288 392 2347 408)(font "Arial" (font_size 10)(bold)))
+(text "119..90" (rect 2296 440 2346 456)(font "Arial" (font_size 10)(bold)))
+(text "89..60" (rect 2304 488 2346 504)(font "Arial" (font_size 10)(bold)))
+(text "59..30" (rect 2304 536 2346 552)(font "Arial" (font_size 10)(bold)))
+(text "29..0" (rect 2312 584 2346 600)(font "Arial" (font_size 10)(bold)))
+(text "RGB_TAP: 10 bits/colour x 3 colours x 5 rows" (rect 2296 352 2670 370)(font "Arial" (font_size 11)(bold)))
+(text "Current Row - 4" (rect 2560 584 2690 602)(font "Arial" (font_size 11)(bold)))
+(text "Current Row - 3" (rect 2560 536 2690 554)(font "Arial" (font_size 11)(bold)))
+(text "Current Row - 2" (rect 2560 488 2690 506)(font "Arial" (font_size 11)(bold)))
+(text "Current Row - 1" (rect 2560 440 2690 458)(font "Arial" (font_size 11)(bold)))
+(text "Current Row" (rect 2560 392 2666 410)(font "Arial" (font_size 11)(bold)))
+(text "29..20            19..10             9..0" (rect 2368 616 2548 630)(font "Arial" (font_size 8)))
+(line (pt 2416 616)(pt 2416 376))
+(line (pt 2480 616)(pt 2480 376))
+(line (pt 2352 616)(pt 2352 376)(color 0 0 0)(line_width 2))
+(line (pt 2544 616)(pt 2544 376)(color 0 0 0)(line_width 2))
+(line (pt 2352 376)(pt 2544 376)(color 0 0 0)(line_width 2))
+(line (pt 2352 616)(pt 2544 616)(color 0 0 0)(line_width 2))
+(line (pt 2352 568)(pt 2544 568)(color 0 0 0)(line_width 2))
+(line (pt 2352 520)(pt 2544 520)(color 0 0 0)(line_width 2))
+(line (pt 2352 472)(pt 2544 472)(color 0 0 0)(line_width 2))
+(line (pt 2352 424)(pt 2544 424)(color 0 0 0)(line_width 2))
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v
new file mode 100644
index 0000000..f7904df
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v
@@ -0,0 +1,158 @@
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| ??????????        :| ??/??/??  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 16/03/14  :| X-Y coords
+// --------------------------------------------------------------------
+ 
+
+
+
+module	VGA_Controller(	//	Host Side
+						iRed,
+						iGreen,
+						iBlue,
+						oRequest,
+						//	VGA Side
+						oVGA_R,
+						oVGA_G,
+						oVGA_B,
+						oVGA_H_SYNC,
+						oVGA_V_SYNC,
+						oVGA_SYNC,
+						oVGA_BLANK,
+						oVGA_CLOCK,
+						oVGA_X,
+						oVGA_Y,
+						oVGA_ACTIVE,
+						//	Control Signal
+						iCLK,
+						iRST_N	);
+
+`include "VGA_Param.h"
+
+//	Host Side
+input		[9:0]	iRed;
+input		[9:0]	iGreen;
+input		[9:0]	iBlue;
+output	reg			oRequest;
+//	VGA Side
+output		[9:0]	oVGA_R;
+output		[9:0]	oVGA_G;
+output		[9:0]	oVGA_B;
+output	reg			oVGA_H_SYNC;
+output	reg			oVGA_V_SYNC;
+output				oVGA_SYNC;
+output				oVGA_BLANK;
+output				oVGA_CLOCK;
+output  		[11:0]		oVGA_X;
+output  		[11:0]		oVGA_Y;
+output         	oVGA_ACTIVE;
+
+
+
+
+//	Control Signal
+input				iCLK;
+input				iRST_N;
+
+//	Internal Registers and Wires
+reg		[11:0]		H_Cont;
+reg		[11:0]		V_Cont;
+reg 				active;
+
+assign	oVGA_BLANK	=	oVGA_H_SYNC & oVGA_V_SYNC;
+assign	oVGA_SYNC	=	1'b0;
+assign	oVGA_CLOCK	=	iCLK;
+
+assign	oVGA_R	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iRed	:	0;
+assign	oVGA_G	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iGreen	:	0;
+assign	oVGA_B	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iBlue	:	0;
+
+						
+assign oVGA_X = 		H_Cont;				
+assign oVGA_Y = 		V_Cont;				
+assign oVGA_ACTIVE = active;
+	
+						
+//	Pixel LUT Address Generator
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	oRequest	<=	0;
+	else
+	begin
+		if(	H_Cont>=X_START-2 && H_Cont<X_START+H_SYNC_ACT-2 &&
+			V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
+		oRequest	<=	1;
+		else
+		oRequest	<=	0;
+	end
+end
+
+//	H_Sync Generator, Ref. 25.175 MHz Clock
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		H_Cont		<=	0;
+		oVGA_H_SYNC	<=	0;
+		active		<= 0;	
+	end
+	else
+	begin
+		//	H_Sync Counter
+		if( H_Cont < H_SYNC_TOTAL )
+		begin
+			H_Cont	<=	H_Cont+1;
+			active <= 1'b1;
+			end
+		else
+		begin
+			H_Cont	<=	0;
+			active <= 1'b0;			
+			end
+		//	H_Sync Generator
+		if( H_Cont < H_SYNC_CYC )
+			oVGA_H_SYNC	<=	0;
+		else
+			oVGA_H_SYNC	<=	1;
+	end
+end
+
+//	V_Sync Generator, Ref. H_Sync
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		V_Cont		<=	0;
+		oVGA_V_SYNC	<=	0;
+	end
+	else
+	begin
+		//	When H_Sync Re-start
+		if(H_Cont==0)
+		begin
+			//	V_Sync Counter
+			if( V_Cont < V_SYNC_TOTAL )
+			V_Cont	<=	V_Cont+1;
+			else
+			V_Cont	<=	0;
+			//	V_Sync Generator
+			if(	V_Cont < V_SYNC_CYC )
+			oVGA_V_SYNC	<=	0;
+			else
+			oVGA_V_SYNC	<=	1;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v.bak
new file mode 100644
index 0000000..c9c3537
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v.bak
@@ -0,0 +1,122 @@
+module	VGA_Controller(	//	Host Side
+						iRed,
+						iGreen,
+						iBlue,
+						oRequest,
+						//	VGA Side
+						oVGA_R,
+						oVGA_G,
+						oVGA_B,
+						oVGA_H_SYNC,
+						oVGA_V_SYNC,
+						oVGA_SYNC,
+						oVGA_BLANK,
+						oVGA_CLOCK,
+						//	Control Signal
+						iCLK,
+						iRST_N	);
+
+`include "VGA_Param.h"
+
+//	Host Side
+input		[9:0]	iRed;
+input		[9:0]	iGreen;
+input		[9:0]	iBlue;
+output	reg			oRequest;
+//	VGA Side
+output		[9:0]	oVGA_R;
+output		[9:0]	oVGA_G;
+output		[9:0]	oVGA_B;
+output	reg			oVGA_H_SYNC;
+output	reg			oVGA_V_SYNC;
+output				oVGA_SYNC;
+output				oVGA_BLANK;
+output				oVGA_CLOCK;
+//	Control Signal
+input				iCLK;
+input				iRST_N;
+
+//	Internal Registers and Wires
+reg		[11:0]		H_Cont;
+reg		[11:0]		V_Cont;
+
+assign	oVGA_BLANK	=	oVGA_H_SYNC & oVGA_V_SYNC;
+assign	oVGA_SYNC	=	1'b0;
+assign	oVGA_CLOCK	=	iCLK;
+
+assign	oVGA_R	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iRed	:	0;
+assign	oVGA_G	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iGreen	:	0;
+assign	oVGA_B	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iBlue	:	0;
+
+//	Pixel LUT Address Generator
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	oRequest	<=	0;
+	else
+	begin
+		if(	H_Cont>=X_START-2 && H_Cont<X_START+H_SYNC_ACT-2 &&
+			V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
+		oRequest	<=	1;
+		else
+		oRequest	<=	0;
+	end
+end
+
+//	H_Sync Generator, Ref. 25.175 MHz Clock
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		H_Cont		<=	0;
+		oVGA_H_SYNC	<=	0;
+	end
+	else
+	begin
+		//	H_Sync Counter
+		if( H_Cont < H_SYNC_TOTAL )
+		H_Cont	<=	H_Cont+1;
+		else
+		H_Cont	<=	0;
+		//	H_Sync Generator
+		if( H_Cont < H_SYNC_CYC )
+		oVGA_H_SYNC	<=	0;
+		else
+		oVGA_H_SYNC	<=	1;
+	end
+end
+
+//	V_Sync Generator, Ref. H_Sync
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		V_Cont		<=	0;
+		oVGA_V_SYNC	<=	0;
+	end
+	else
+	begin
+		//	When H_Sync Re-start
+		if(H_Cont==0)
+		begin
+			//	V_Sync Counter
+			if( V_Cont < V_SYNC_TOTAL )
+			V_Cont	<=	V_Cont+1;
+			else
+			V_Cont	<=	0;
+			//	V_Sync Generator
+			if(	V_Cont < V_SYNC_CYC )
+			oVGA_V_SYNC	<=	0;
+			else
+			oVGA_V_SYNC	<=	1;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Param.h b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Param.h
new file mode 100644
index 0000000..9d0fd32
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Param.h
@@ -0,0 +1,16 @@
+//	Horizontal Parameter	( Pixel )
+parameter	H_SYNC_CYC	=	96;
+parameter	H_SYNC_BACK	=	48;
+parameter	H_SYNC_ACT	=	640;	
+parameter	H_SYNC_FRONT=	16;
+parameter	H_SYNC_TOTAL=	800;
+
+//	Virtical Parameter		( Line )
+parameter	V_SYNC_CYC	=	2;
+parameter	V_SYNC_BACK	=	33;
+parameter	V_SYNC_ACT	=	480;	
+parameter	V_SYNC_FRONT=	10;
+parameter	V_SYNC_TOTAL=	525;
+//	Start Offset
+parameter	X_START		=	H_SYNC_CYC+H_SYNC_BACK;
+parameter	Y_START		=	V_SYNC_CYC+V_SYNC_BACK;
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v
new file mode 100644
index 0000000..6063417
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v
@@ -0,0 +1,271 @@
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE2_115_PS2 Mouse Controller 
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author                    :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN,HdHuang        :| 05/16/10  :| Initial Revision
+//   V1.1 :| Rui Duarte
+// --------------------------------------------------------------------
+module ps2(
+           iSTART,   //press the button for transmitting instrucions to device;
+           iRST_n,   //FSM reset signal;
+           iCLK_50,  //clock source;
+           PS2_CLK,  //ps2_clock signal inout;
+           PS2_DAT,  //ps2_data  signal inout;
+           oLEFBUT,  //left button press display;
+           oRIGBUT,  //right button press display;
+           oMIDBUT,  //middle button press display;
+			  oX,		   // 8-bit X coordinate value
+			  oY, 	   // 8-bit Y coordinate value
+           oX_MOV1,  //lower SEG of mouse displacement display for X axis.
+           oX_MOV2,  //higher SEG of mouse displacement display for X axis.
+           oY_MOV1,  //lower SEG of mouse displacement display for Y axis.
+           oY_MOV2   //higher SEG of mouse displacement display for Y axis.
+           ); 
+           //interface;
+//=======================================================
+//  PORT declarations
+//=======================================================
+
+input iSTART;
+input iRST_n;
+input iCLK_50;
+
+inout PS2_CLK;
+inout PS2_DAT;
+
+output oLEFBUT;
+output oRIGBUT;
+output oMIDBUT;
+output [7:0] oX;
+output [7:0] oY;
+output [6:0] oX_MOV1;
+output [6:0] oX_MOV2;
+output [6:0] oY_MOV1;
+output [6:0] oY_MOV2;
+
+//instantiation
+SEG7_LUT U1(.oSEG(oX_MOV1),.iDIG(x_latch[3:0]));
+SEG7_LUT U2(.oSEG(oX_MOV2),.iDIG(x_latch[7:4]));
+SEG7_LUT U3(.oSEG(oY_MOV1),.iDIG(y_latch[3:0]));
+SEG7_LUT U4(.oSEG(oY_MOV2),.iDIG(y_latch[7:4]));
+//instruction define, users can charge the instruction byte here for other purpose according to ps/2 mouse datasheet.
+//the MSB is of parity check bit, that's when there are odd number of 1's with data bits, it's value is '0',otherwise it's '1' instead.
+
+parameter enable_byte =9'b011110100;
+
+
+//=======================================================
+//  REG/WIRE declarations
+//=======================================================
+reg [1:0] cur_state,nex_state;
+reg ce,de;
+reg [3:0] byte_cnt,delay;
+reg [5:0] ct;
+reg [7:0] x_latch,y_latch,cnt;
+reg [8:0] clk_div;
+reg [9:0] dout_reg;
+reg [32:0] shift_reg;
+reg       leflatch,riglatch,midlatch;
+reg       ps2_clk_in,ps2_clk_syn1,ps2_dat_in,ps2_dat_syn1;
+wire      clk,ps2_dat_syn0,ps2_clk_syn0,ps2_dat_out,ps2_clk_out,flag;
+
+//=======================================================
+//  PARAMETER declarations
+//=======================================================
+//state define
+parameter listen =2'b00,
+          pullclk=2'b01,
+          pulldat=2'b10,
+          trans  =2'b11;
+          
+//=======================================================
+//  Structural coding
+//=======================================================          
+//clk division, derive a 97.65625KHz clock from the 50MHz source;
+
+always@(posedge iCLK_50)
+	begin
+		clk_div <= clk_div+1;
+	end
+	
+assign clk = clk_div[8];
+//tristate output control for PS2_DAT and PS2_CLK;
+assign PS2_CLK = ce?ps2_clk_out:1'bZ;
+assign PS2_DAT = de?ps2_dat_out:1'bZ;
+assign ps2_clk_out = 1'b0;
+assign ps2_dat_out = dout_reg[0];
+assign ps2_clk_syn0 = ce?1'b1:PS2_CLK;
+assign ps2_dat_syn0 = de?1'b1:PS2_DAT;
+//
+assign oLEFBUT = leflatch;
+assign oRIGBUT = riglatch;
+assign oMIDBUT = midlatch;
+//
+assign oX = x_latch;
+assign oY = y_latch;
+//
+//multi-clock region simple synchronization
+always@(posedge clk)
+	begin
+		ps2_clk_syn1 <= ps2_clk_syn0;
+		ps2_clk_in   <= ps2_clk_syn1;
+		ps2_dat_syn1 <= ps2_dat_syn0;
+		ps2_dat_in   <= ps2_dat_syn1;
+	end
+//FSM shift
+always@(*)
+begin
+   case(cur_state)
+     listen  :begin
+              if ((!iSTART) && (cnt == 8'b11111111))
+                  nex_state = pullclk;
+              else
+                  nex_state = listen;
+                         ce = 1'b0;
+                         de = 1'b0;
+              end
+     pullclk :begin
+              if (delay == 4'b1100)
+                  nex_state = pulldat;
+              else
+                  nex_state = pullclk;
+                         ce = 1'b1;
+                         de = 1'b0;
+              end
+     pulldat :begin
+                  nex_state = trans;
+                         ce = 1'b1;
+                         de = 1'b1;
+              end
+     trans   :begin
+              if  (byte_cnt == 4'b1010)
+                  nex_state = listen;
+              else    
+                  nex_state = trans;
+                         ce = 1'b0;
+                         de = 1'b1;
+              end
+     default :    nex_state = listen;
+   endcase
+end
+//idle counter
+always@(posedge clk)
+begin
+  if ({ps2_clk_in,ps2_dat_in} == 2'b11)
+	begin
+		cnt <= cnt+1;
+    end
+  else begin
+		cnt <= 8'd0;
+       end
+end
+//periodically reset ct; ct counts the received data length;
+assign flag = (cnt == 8'hff)?1:0;
+always@(posedge ps2_clk_in,posedge flag)
+begin
+  if (flag)
+     ct <= 6'b000000;
+  else
+     ct <= ct+1;
+end
+//latch data from shift_reg;outputs is of 2's complement;
+//Please treat the cnt value here with caution, otherwise wrong data will be latched.
+always@(posedge clk,negedge iRST_n)
+begin
+   if (!iRST_n) 
+   begin
+      leflatch <= 1'b0;
+      riglatch <= 1'b0;
+      midlatch <= 1'b0;
+      x_latch  <= 8'd0;
+      y_latch  <= 8'd0;
+   end
+   else if (cnt == 8'b00011110 && (ct[5] == 1'b1 || ct[4] == 1'b1))
+   begin
+      leflatch <= shift_reg[1];
+      riglatch <= shift_reg[2];
+      midlatch <= shift_reg[3];
+      x_latch  <= x_latch+shift_reg[19 : 12];
+      y_latch  <= y_latch+shift_reg[30 : 23];
+   end
+end
+
+//pull ps2_clk low for 100us before transmit starts;
+always@(posedge clk)
+begin
+  if (cur_state == pullclk)
+     delay <= delay+1;
+  else
+     delay <= 4'b0000;
+end
+//transmit data to ps2 device;eg. 0xF4
+always@(negedge ps2_clk_in)
+begin
+  if (cur_state == trans)
+     dout_reg <= {1'b0,dout_reg[9:1]};
+  else
+     dout_reg <= {enable_byte,1'b0};
+end
+//transmit byte length counter
+always@(negedge ps2_clk_in)
+begin
+  if (cur_state == trans)
+     byte_cnt <= byte_cnt+1;
+  else
+     byte_cnt <= 4'b0000;
+end
+//receive data from ps2 device;
+always@(negedge ps2_clk_in)
+begin
+  if (cur_state == listen)
+     shift_reg <= {ps2_dat_in,shift_reg[32:1]};
+end
+//FSM movement
+always@(posedge clk,negedge iRST_n)
+begin
+  if (!iRST_n)
+     cur_state <= listen;
+  else
+     cur_state <= nex_state;
+end
+endmodule
+
+
+     
+
+
+     
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.bsf
new file mode 100644
index 0000000..a895305
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.bsf
@@ -0,0 +1,81 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 240 168)
+	(text "sdram_pll" (rect 92 0 158 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 25 164)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 240 64)
+		(output)
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 224 50 234 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 240 80)
+		(output)
+		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 224 66 232 79)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 178 152 401 315)(font "Arial" ))
+		(text "inclk0 frequency: 50.000 MHz" (rect 50 59 223 129)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
+		(text "Clk " (rect 51 93 116 197)(font "Arial" ))
+		(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
+		(text "Ph (dg)" (rect 98 93 225 197)(font "Arial" ))
+		(text "DC (%)" (rect 132 93 294 197)(font "Arial" ))
+		(text "c0" (rect 54 107 116 225)(font "Arial" ))
+		(text "5/2" (rect 77 107 165 225)(font "Arial" ))
+		(text "0.00" (rect 104 107 224 225)(font "Arial" ))
+		(text "50.00" (rect 136 107 293 225)(font "Arial" ))
+		(text "c1" (rect 54 121 115 253)(font "Arial" ))
+		(text "5/2" (rect 77 121 165 253)(font "Arial" ))
+		(text "-117.00" (rect 98 121 224 253)(font "Arial" ))
+		(text "50.00" (rect 136 121 293 253)(font "Arial" ))
+		(line (pt 0 0)(pt 241 0))
+		(line (pt 241 0)(pt 241 169))
+		(line (pt 0 169)(pt 241 169))
+		(line (pt 0 0)(pt 0 169))
+		(line (pt 48 91)(pt 164 91))
+		(line (pt 48 104)(pt 164 104))
+		(line (pt 48 118)(pt 164 118))
+		(line (pt 48 132)(pt 164 132))
+		(line (pt 48 91)(pt 48 132))
+		(line (pt 69 91)(pt 69 132)(line_width 3))
+		(line (pt 95 91)(pt 95 132)(line_width 3))
+		(line (pt 129 91)(pt 129 132)(line_width 3))
+		(line (pt 163 91)(pt 163 132))
+		(line (pt 40 48)(pt 207 48))
+		(line (pt 207 48)(pt 207 151))
+		(line (pt 40 151)(pt 207 151))
+		(line (pt 40 48)(pt 40 151))
+		(line (pt 239 64)(pt 207 64))
+		(line (pt 239 80)(pt 207 80))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.ppf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.ppf
new file mode 100644
index 0000000..a4a0f2e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.ppf
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="sdram_pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.qip
new file mode 100644
index 0000000..7440d58
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sdram_pll.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.ppf"]
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v
new file mode 100644
index 0000000..6b4189b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v
@@ -0,0 +1,329 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sdram_pll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [4:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 2,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 5,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 2,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_phase_shift = "-2600",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2.60000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2600"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v.bak
new file mode 100644
index 0000000..7fd74a1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v.bak
@@ -0,0 +1,326 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 218 06/27/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sdram_pll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [5:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.clk0_divide_by = 2,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 5,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 2,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_phase_shift = "-3000",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone II",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-3.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-3000"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_wave0.jpg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_wave0.jpg
new file mode 100644
index 0000000..a48389a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_wave0.jpg
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_waveforms.html b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_waveforms.html
new file mode 100644
index 0000000..2d27f12
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for sdram_pll.v </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file sdram_pll.v </CENTER></h2>
+<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design sdram_pll.v. The design sdram_pll.v has Cyclone II PLL_TYPE pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. </P>
+<CENTER><img src=sdram_pll_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
+<P><FONT size=3></P>
+<P></P>
+</body>
+</html>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v
new file mode 100644
index 0000000..6168631
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v
@@ -0,0 +1,429 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   rad09@EE-RAD09-02
+//  Generated date: Wed Mar 06 21:47:19 2013
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    mean_vga_core
+// ------------------------------------------------------------------
+
+
+module mean_vga_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] slc_regs_regs_2_1_itm;
+  reg [9:0] slc_regs_regs_2_2_itm;
+  reg [9:0] slc_regs_regs_2_itm;
+  reg [9:0] slc_regs_regs_2_4_itm;
+  reg [9:0] slc_regs_regs_2_5_itm;
+  reg [9:0] slc_regs_regs_2_3_itm;
+  reg [9:0] slc_regs_regs_2_7_itm;
+  reg [9:0] slc_regs_regs_2_8_itm;
+  reg [9:0] slc_regs_regs_2_6_itm;
+  reg [89:0] reg_regs_regs_0_sva_cse;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  wire [11:0] nl_reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_1;
+  reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_2;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_3;
+  wire [13:0] ACC_acc_psp_sva;
+  wire [14:0] nl_ACC_acc_psp_sva;
+  wire [5:0] acc_imod_sva;
+  wire [6:0] nl_acc_imod_sva;
+  wire [11:0] acc_9_psp_sva;
+  wire [12:0] nl_acc_9_psp_sva;
+  wire [11:0] acc_14_psp_sva;
+  wire [12:0] nl_acc_14_psp_sva;
+  wire [13:0] ACC_acc_21_psp_sva;
+  wire [14:0] nl_ACC_acc_21_psp_sva;
+  wire [5:0] acc_imod_4_sva;
+  wire [6:0] nl_acc_imod_4_sva;
+  wire [3:0] acc_29_sdt;
+  wire [4:0] nl_acc_29_sdt;
+  wire [13:0] ACC_acc_20_psp_sva;
+  wire [14:0] nl_ACC_acc_20_psp_sva;
+  wire [5:0] acc_imod_2_sva;
+  wire [6:0] nl_acc_imod_2_sva;
+  wire [3:0] acc_19_sdt;
+  wire [4:0] nl_acc_19_sdt;
+  wire [3:0] acc_15_sdt;
+  wire [4:0] nl_acc_15_sdt;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign vout_rsc_mgc_out_stdreg_d = {reg_vout_rsc_mgc_out_stdreg_d_tmp , reg_vout_rsc_mgc_out_stdreg_d_tmp_1
+      , reg_vout_rsc_mgc_out_stdreg_d_tmp_2 , reg_vout_rsc_mgc_out_stdreg_d_tmp_3};
+  assign nl_ACC_acc_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_1_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_2_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[29:20]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[59:50]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[89:80])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[29:20])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[59:50])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[89:80])
+      + conv_u2u_10_11(slc_regs_regs_2_itm)));
+  assign ACC_acc_psp_sva = nl_ACC_acc_psp_sva[13:0];
+  assign nl_acc_imod_sva = conv_s2s_5_6({(({1'b1 , (acc_15_sdt[3:1])}) + 4'b1) ,
+      (acc_15_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_psp_sva[2:0]));
+  assign acc_imod_sva = nl_acc_imod_sva[5:0];
+  assign nl_acc_9_psp_sva = conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_20_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_20_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_2_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_2_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_2_sva[5:3])) , (~ (acc_imod_2_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_2_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_20_psp_sva[8:6])))
+      + ({4'b1001 , (acc_imod_2_sva[5])})))) + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_2_10(ACC_acc_20_psp_sva[13:12])
+      * 10'b111000111));
+  assign acc_9_psp_sva = nl_acc_9_psp_sva[11:0];
+  assign nl_acc_14_psp_sva = conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_21_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_21_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_4_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_4_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_4_sva[5:3])) , (~ (acc_imod_4_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_4_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_21_psp_sva[8:6])))
+      + ({4'b1001 , (acc_imod_4_sva[5])})))) + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_2_10(ACC_acc_21_psp_sva[13:12])
+      * 10'b111000111));
+  assign acc_14_psp_sva = nl_acc_14_psp_sva[11:0];
+  assign nl_ACC_acc_21_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_7_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_8_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[19:10]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[49:40]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[79:70])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[19:10])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[49:40])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[79:70])
+      + conv_u2u_10_11(slc_regs_regs_2_6_itm)));
+  assign ACC_acc_21_psp_sva = nl_ACC_acc_21_psp_sva[13:0];
+  assign nl_acc_imod_4_sva = conv_s2s_5_6({(({1'b1 , (acc_29_sdt[3:1])}) + 4'b1)
+      , (acc_29_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_21_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_21_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_21_psp_sva[2:0]));
+  assign acc_imod_4_sva = nl_acc_imod_4_sva[5:0];
+  assign nl_acc_29_sdt = conv_u2u_3_4(~ (ACC_acc_21_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_21_psp_sva[8:6]);
+  assign acc_29_sdt = nl_acc_29_sdt[3:0];
+  assign nl_ACC_acc_20_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_4_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_5_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[9:0]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[39:30]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[69:60])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[9:0])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[39:30])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[69:60])
+      + conv_u2u_10_11(slc_regs_regs_2_3_itm)));
+  assign ACC_acc_20_psp_sva = nl_ACC_acc_20_psp_sva[13:0];
+  assign nl_acc_imod_2_sva = conv_s2s_5_6({(({1'b1 , (acc_19_sdt[3:1])}) + 4'b1)
+      , (acc_19_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_20_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_20_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_20_psp_sva[2:0]));
+  assign acc_imod_2_sva = nl_acc_imod_2_sva[5:0];
+  assign nl_acc_19_sdt = conv_u2u_3_4(~ (ACC_acc_20_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_20_psp_sva[8:6]);
+  assign acc_19_sdt = nl_acc_19_sdt[3:0];
+  assign nl_acc_15_sdt = conv_u2u_3_4(~ (ACC_acc_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_psp_sva[8:6]);
+  assign acc_15_sdt = nl_acc_15_sdt[3:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      slc_regs_regs_2_7_itm <= 10'b0;
+      slc_regs_regs_2_8_itm <= 10'b0;
+      reg_regs_regs_0_sva_cse <= 90'b0;
+      slc_regs_regs_2_6_itm <= 10'b0;
+      slc_regs_regs_2_4_itm <= 10'b0;
+      slc_regs_regs_2_5_itm <= 10'b0;
+      slc_regs_regs_2_3_itm <= 10'b0;
+      slc_regs_regs_2_1_itm <= 10'b0;
+      slc_regs_regs_2_2_itm <= 10'b0;
+      slc_regs_regs_2_itm <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= 5'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= 5'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= 10'b0;
+    end
+    else begin
+      if ( en ) begin
+        slc_regs_regs_2_7_itm <= reg_regs_regs_0_sva_cse[49:40];
+        slc_regs_regs_2_8_itm <= reg_regs_regs_0_sva_cse[79:70];
+        reg_regs_regs_0_sva_cse <= vin_rsc_mgc_in_wire_d;
+        slc_regs_regs_2_6_itm <= reg_regs_regs_0_sva_cse[19:10];
+        slc_regs_regs_2_4_itm <= reg_regs_regs_0_sva_cse[39:30];
+        slc_regs_regs_2_5_itm <= reg_regs_regs_0_sva_cse[69:60];
+        slc_regs_regs_2_3_itm <= reg_regs_regs_0_sva_cse[9:0];
+        slc_regs_regs_2_1_itm <= reg_regs_regs_0_sva_cse[59:50];
+        slc_regs_regs_2_2_itm <= reg_regs_regs_0_sva_cse[89:80];
+        slc_regs_regs_2_itm <= reg_regs_regs_0_sva_cse[29:20];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp <= ((conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_psp_sva[11:9])
+            * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+            (acc_imod_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_sva[2:0])
+            , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_sva[5:3])) , (~ (acc_imod_sva[5]))})))))})
+            + conv_u2u_2_4(acc_imod_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_psp_sva[8:6])))
+            + ({4'b1001 , (acc_imod_sva[5])})))) + conv_u2u_20_10(conv_u2u_2_10(ACC_acc_psp_sva[13:12])
+            * 10'b111000111)) | ({5'b0 , (signext_5_2(acc_9_psp_sva[11:10]))});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= acc_9_psp_sva[9:5];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= (acc_9_psp_sva[4:0]) | (signext_5_2(acc_14_psp_sva[11:10]));
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= acc_14_psp_sva[9:0];
+      end
+    end
+  end
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_2;
+    input [1:0] vector;
+  begin
+    signext_5_2= {{3{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_13_14 ;
+    input [12:0]  vector ;
+  begin
+    conv_u2u_13_14 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    mean_vga
+//  Generated from file(s):
+//    5) $PROJECT_HOME/vga_mouse_filter/blur.c
+// ------------------------------------------------------------------
+
+
+module mean_vga (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  mean_vga_core mean_vga_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport_v2001.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v
new file mode 100644
index 0000000..dda909a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v
@@ -0,0 +1,171 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   rad09@EE-RAD09-02
+//  Generated date: Wed Mar 06 11:57:58 2013
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    vga_mouse_square_core
+// ------------------------------------------------------------------
+
+
+module vga_mouse_square_core (
+  clk, en, arst_n, vga_xy_rsc_mgc_in_wire_d, mouse_xy_rsc_mgc_in_wire_d, cursor_size_rsc_mgc_in_wire_d,
+      video_in_rsc_mgc_in_wire_d, video_out_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [19:0] vga_xy_rsc_mgc_in_wire_d;
+  input [19:0] mouse_xy_rsc_mgc_in_wire_d;
+  input [7:0] cursor_size_rsc_mgc_in_wire_d;
+  input [29:0] video_in_rsc_mgc_in_wire_d;
+  output [29:0] video_out_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] reg_video_out_rsc_mgc_out_stdreg_d_tmp;
+  reg [9:0] reg_video_out_rsc_mgc_out_stdreg_d_tmp_1;
+  reg [9:0] reg_video_out_rsc_mgc_out_stdreg_d_tmp_2;
+  wire or_itm;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign video_out_rsc_mgc_out_stdreg_d = {reg_video_out_rsc_mgc_out_stdreg_d_tmp
+      , reg_video_out_rsc_mgc_out_stdreg_d_tmp_1 , reg_video_out_rsc_mgc_out_stdreg_d_tmp_2};
+  assign or_itm = (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(mouse_xy_rsc_mgc_in_wire_d[19:10])
+      , 1'b1}) + conv_u2u_11_12({(~ (vga_xy_rsc_mgc_in_wire_d[19:10])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d})))) | (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(vga_xy_rsc_mgc_in_wire_d[19:10])
+      , 1'b1}) + conv_u2u_11_12({(~ (mouse_xy_rsc_mgc_in_wire_d[19:10])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d})))) | (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(mouse_xy_rsc_mgc_in_wire_d[9:0])
+      , 1'b1}) + conv_u2u_11_12({(~ (vga_xy_rsc_mgc_in_wire_d[9:0])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d})))) | (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(vga_xy_rsc_mgc_in_wire_d[9:0])
+      , 1'b1}) + conv_u2u_11_12({(~ (mouse_xy_rsc_mgc_in_wire_d[9:0])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d}))));
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      reg_video_out_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_video_out_rsc_mgc_out_stdreg_d_tmp_1 <= 10'b0;
+      reg_video_out_rsc_mgc_out_stdreg_d_tmp_2 <= 10'b0;
+    end
+    else begin
+      if ( en ) begin
+        reg_video_out_rsc_mgc_out_stdreg_d_tmp <= (video_in_rsc_mgc_in_wire_d[29:20])
+            & ({{9{or_itm}}, or_itm});
+        reg_video_out_rsc_mgc_out_stdreg_d_tmp_1 <= video_in_rsc_mgc_in_wire_d[19:10];
+        reg_video_out_rsc_mgc_out_stdreg_d_tmp_2 <= (video_in_rsc_mgc_in_wire_d[9:0])
+            & ({{9{or_itm}}, or_itm});
+      end
+    end
+  end
+
+  function [0:0] readslicef_12_1_11;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 11;
+    readslicef_12_1_11 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    vga_mouse_square
+//  Generated from file(s):
+//   12) $PROJECT_HOME/vga_mouse_square__old/vga_mouse_square_working_demo_sw.c
+// ------------------------------------------------------------------
+
+
+module vga_mouse_square (
+  vga_xy_rsc_z, mouse_xy_rsc_z, cursor_size_rsc_z, video_in_rsc_z, video_out_rsc_z,
+      clk, en, arst_n
+);
+  input [19:0] vga_xy_rsc_z;
+  input [19:0] mouse_xy_rsc_z;
+  input [7:0] cursor_size_rsc_z;
+  input [29:0] video_in_rsc_z;
+  output [29:0] video_out_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [19:0] vga_xy_rsc_mgc_in_wire_d;
+  wire [19:0] mouse_xy_rsc_mgc_in_wire_d;
+  wire [7:0] cursor_size_rsc_mgc_in_wire_d;
+  wire [29:0] video_in_rsc_mgc_in_wire_d;
+  wire [29:0] video_out_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(20)) vga_xy_rsc_mgc_in_wire (
+      .d(vga_xy_rsc_mgc_in_wire_d),
+      .z(vga_xy_rsc_z)
+    );
+  mgc_in_wire #(.rscid(2),
+  .width(20)) mouse_xy_rsc_mgc_in_wire (
+      .d(mouse_xy_rsc_mgc_in_wire_d),
+      .z(mouse_xy_rsc_z)
+    );
+  mgc_in_wire #(.rscid(3),
+  .width(8)) cursor_size_rsc_mgc_in_wire (
+      .d(cursor_size_rsc_mgc_in_wire_d),
+      .z(cursor_size_rsc_z)
+    );
+  mgc_in_wire #(.rscid(4),
+  .width(30)) video_in_rsc_mgc_in_wire (
+      .d(video_in_rsc_mgc_in_wire_d),
+      .z(video_in_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(5),
+  .width(30)) video_out_rsc_mgc_out_stdreg (
+      .d(video_out_rsc_mgc_out_stdreg_d),
+      .z(video_out_rsc_z)
+    );
+  vga_mouse_square_core vga_mouse_square_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vga_xy_rsc_mgc_in_wire_d(vga_xy_rsc_mgc_in_wire_d),
+      .mouse_xy_rsc_mgc_in_wire_d(mouse_xy_rsc_mgc_in_wire_d),
+      .cursor_size_rsc_mgc_in_wire_d(cursor_size_rsc_mgc_in_wire_d),
+      .video_in_rsc_mgc_in_wire_d(video_in_rsc_mgc_in_wire_d),
+      .video_out_rsc_mgc_out_stdreg_d(video_out_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(0).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(0).cnf.cdb
new file mode 100644
index 0000000..f0b3b83
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(0).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(0).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(0).cnf.hdb
new file mode 100644
index 0000000..f3333f3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(0).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(1).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(1).cnf.cdb
new file mode 100644
index 0000000..8a5fa48
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(1).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(1).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(1).cnf.hdb
new file mode 100644
index 0000000..d4f4f03
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(1).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(10).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(10).cnf.cdb
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index 0000000..f810961
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(10).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(10).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(10).cnf.hdb
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index 0000000..ad4fd5e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(10).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(100).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(100).cnf.cdb
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index 0000000..530fa50
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(100).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(100).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(100).cnf.hdb
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index 0000000..64b50a0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(100).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(101).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(101).cnf.cdb
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index 0000000..b2059d2
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(101).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(101).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(101).cnf.hdb
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index 0000000..10abe1e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(101).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(102).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(102).cnf.cdb
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index 0000000..7700a5f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(102).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(102).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(102).cnf.hdb
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index 0000000..39855c0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(102).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(103).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(103).cnf.cdb
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index 0000000..411b1b0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(103).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(103).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(103).cnf.hdb
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index 0000000..0d58921
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(103).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(104).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(104).cnf.cdb
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index 0000000..f0bfd89
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(104).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(104).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(104).cnf.hdb
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index 0000000..e813dce
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(104).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(11).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(11).cnf.cdb
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index 0000000..20f486c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(11).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(11).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(11).cnf.hdb
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--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(11).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(12).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(12).cnf.cdb
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--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(12).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(12).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(12).cnf.hdb
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index 0000000..6e3f54b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(12).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(13).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(13).cnf.cdb
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--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(13).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(13).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(13).cnf.hdb
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--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(13).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(14).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(14).cnf.cdb
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--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(14).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(14).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(14).cnf.hdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(14).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(15).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(15).cnf.cdb
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--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(15).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(15).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(15).cnf.hdb
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--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(15).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(16).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(16).cnf.cdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(16).cnf.cdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(16).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(17).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(17).cnf.cdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(17).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(17).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(17).cnf.hdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(17).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(18).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(18).cnf.cdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(18).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(18).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(18).cnf.hdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(18).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(19).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(19).cnf.cdb
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--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(19).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(19).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(19).cnf.hdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(19).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(2).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(2).cnf.cdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(2).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(2).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(2).cnf.hdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(2).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(20).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(20).cnf.cdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(20).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(20).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(20).cnf.hdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(20).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(21).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(21).cnf.cdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(21).cnf.cdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(21).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(22).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(22).cnf.cdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(22).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(22).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(22).cnf.hdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(22).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(23).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(23).cnf.cdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(23).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(23).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(23).cnf.hdb
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+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(23).cnf.hdb
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--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.asm_labs.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cbx.xml b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cbx.xml
new file mode 100644
index 0000000..0d42b32
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cbx.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="DE0_D5M">
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component" CBX_FILE_NAME="dcfifo_v5o1.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component" CBX_FILE_NAME="dcfifo_v5o1.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component" CBX_FILE_NAME="altpll_9ee2.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2" CBX_FILE_NAME="shift_taps_jpm.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component" CBX_FILE_NAME="shift_taps_rnn.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component" CBX_FILE_NAME="dcfifo_v5o1.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component" CBX_FILE_NAME="dcfifo_v5o1.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|LPM_MUX:LPM_MUX_component" CBX_FILE_NAME="mux_u7e.tdf"/>
+	</PROJECT>
+</LOG_ROOT>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.bpm b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.bpm
new file mode 100644
index 0000000..b4018f7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.bpm
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.cdb
new file mode 100644
index 0000000..24972b9
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.hdb
new file mode 100644
index 0000000..3747dc6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.idb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.idb
new file mode 100644
index 0000000..76176ac
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.idb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.kpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.kpt
new file mode 100644
index 0000000..39c8abd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.kpt
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.logdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.logdb
new file mode 100644
index 0000000..105c8ca
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.logdb
@@ -0,0 +1,184 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,PASS,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,142;0;142;0;0;143;142;0;143;143;0;0;0;0;66;0;0;66;0;0;30;0;0;0;0;0;0;143;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,1;143;1;143;143;0;1;143;0;0;143;143;143;143;77;143;143;77;143;143;113;143;143;143;143;143;143;0;143;143,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,DRAM_LDQM,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1_CLKIN[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_UDQM,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_BA_1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_BA_0,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_CAS_N,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_CKE,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_CS_N,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_RAS_N,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_WE_N,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_HS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_VS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1_CLKOUT[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1_CLKOUT[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[31],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[30],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[29],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[28],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[27],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[26],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[25],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[24],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[23],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[22],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[21],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[20],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[19],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[18],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[16],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PS2_DAT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PS2_CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1_CLKIN[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,10,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,20,
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.rdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.rdb
new file mode 100644
index 0000000..a321e41
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.rdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp_merge.kpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp_merge.kpt
new file mode 100644
index 0000000..3b82d37
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp_merge.kpt
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..da9e360
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..c2d6061
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.db_info b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.db_info
new file mode 100644
index 0000000..fdd4475
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Mar 08 15:26:19 2016
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.eco.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.eco.cdb
new file mode 100644
index 0000000..74d5728
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.eco.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.fit.qmsg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.fit.qmsg
new file mode 100644
index 0000000..cb697d4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.fit.qmsg
@@ -0,0 +1,69 @@
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1457454238706 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "DE0_D5M EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"DE0_D5M\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1457454239155 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457454239212 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457454239212 ""}
+{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1 Cyclone III PLL " "Implemented PLL \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1\" as Cyclone III PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] 5 2 0 0 " "Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] port" {  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2342 9224 9983 0}  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1457454239270 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] 5 2 -117 -2600 " "Implementing clock multiplication of 5, clock division of 2, and phase shift of -117 degrees (-2600 ps) for DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] port" {  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2343 9224 9983 0}  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1457454239270 ""}  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2342 9224 9983 0}  }  } }  } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1457454239270 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1457454239383 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457454239656 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457454239656 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457454239656 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1457454239656 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12771 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454239672 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12773 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454239672 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12775 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454239672 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12777 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457454239672 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1457454239672 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1457454239682 ""}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1457454239697 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 143 " "No exact pin location assignment(s) for 1 pins of 143 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "VGA_CLK " "Pin VGA_CLK not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { VGA_CLK } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1272 736 912 1288 "VGA_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 298 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457454240529 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1457454240529 ""}
+{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_v5o1 " "Entity dcfifo_v5o1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a*  " "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1457454243239 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a*  " "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1457454243239 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1457454243239 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1457454243239 ""}
+{ "Info" "ISTA_SDC_FOUND" "DE0_D5M.sdc " "Reading SDC File: 'DE0_D5M.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1457454243263 ""}
+{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457454243277 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457454243277 ""}  } {  } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1457454243277 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457454243292 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457454243293 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457454243293 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457454243293 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457454243293 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
+{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457454243345 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457454243345 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457454243345 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1457454243345 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1457454243354 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457454243361 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457454243361 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457454243361 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457454243361 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\] " "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457454243361 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1457454243361 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p)) " "Automatically promoted node CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G7 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454243588 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|rClk\[0\] " "Destination node DE0_D5M:inst\|rClk\[0\]" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|rClk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2684 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243588 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|clk_div\[8\] " "Destination node ps2:inst6\|clk_div\[8\]" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 97 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|clk_div[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1641 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243588 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Destination node DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 69 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1813 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243588 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457454243588 ""}  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 88 424 592 104 "CLOCK_50" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12755 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454243588 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] (placed in counter C0 of PLL_2) " "Automatically promoted node DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] (placed in counter C0 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G8 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454243602 ""}  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 31 2 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2342 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454243602 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] (placed in counter C1 of PLL_2) " "Automatically promoted node DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] (placed in counter C1 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454243602 ""}  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 31 2 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2342 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454243602 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "GPIO_1_CLKIN\[0\]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n)) " "Automatically promoted node GPIO_1_CLKIN\[0\]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454243606 ""}  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKIN[0]~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12764 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454243606 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|rClk\[0\]  " "Automatically promoted node DE0_D5M:inst\|rClk\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454243606 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|rClk\[0\]~0 " "Destination node DE0_D5M:inst\|rClk\[0\]~0" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|rClk[0]~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 8400 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243606 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1_CLKOUT\[0\]~output " "Destination node GPIO_1_CLKOUT\[0\]~output" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 504 1144 1354 520 "GPIO_1_CLKOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKOUT[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12652 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243606 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "VGA_CLK~output " "Destination node VGA_CLK~output" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1272 736 912 1288 "VGA_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_CLK~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12636 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243606 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457454243606 ""}  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|rClk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2684 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454243606 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK  " "Automatically promoted node DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454243610 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0\|I2C_SCLK~1 " "Destination node DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0\|I2C_SCLK~1" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 58 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|I2C_SCLK~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7350 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243610 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK~0 " "Destination node DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK~0" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 69 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7556 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243610 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457454243610 ""}  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 69 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1813 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454243610 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2:inst6\|ps2_clk_in  " "Automatically promoted node ps2:inst6\|ps2_clk_in " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454243619 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|Equal2~0 " "Destination node ps2:inst6\|Equal2~0" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 186 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|Equal2~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 4281 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243619 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457454243619 ""}  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 101 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|ps2_clk_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1664 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454243619 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2:inst6\|clk_div\[8\]  " "Automatically promoted node ps2:inst6\|clk_div\[8\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454243620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|clk_div\[8\]~22 " "Destination node ps2:inst6\|clk_div\[8\]~22" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 97 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|clk_div[8]~22 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 4275 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243620 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|ps2_clk_in " "Destination node ps2:inst6\|ps2_clk_in" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 101 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|ps2_clk_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1664 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243620 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457454243620 ""}  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 97 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|clk_div[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1641 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454243620 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_0  " "Automatically promoted node DE0_D5M:inst\|Reset_Delay:u2\|oRST_0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454243623 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|RD_MASK\[1\]~6 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|RD_MASK\[1\]~6" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 508 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]~6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7270 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243623 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[10\]~43 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[10\]~43" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]~43 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7929 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243623 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[10\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[10\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7934 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243623 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[13\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[13\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7967 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243623 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[13\]~47 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[13\]~47" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]~47 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7968 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243623 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[18\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[18\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 8001 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243623 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[18\]~47 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[18\]~47" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]~47 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 8002 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243623 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[9\]~43 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[9\]~43" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]~43 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 8031 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243623 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[9\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[9\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 8036 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243623 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_0~2 " "Destination node DE0_D5M:inst\|Reset_Delay:u2\|oRST_0~2" {  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 46 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_0~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 8380 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243623 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457454243623 ""}  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 46 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2608 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454243623 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_1  " "Automatically promoted node DE0_D5M:inst\|Reset_Delay:u2\|oRST_1 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454243649 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[14\]~output " "Destination node GPIO_1\[14\]~output" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 8445 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243649 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_1~1 " "Destination node DE0_D5M:inst\|Reset_Delay:u2\|oRST_1~1" {  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 47 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_1~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7591 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457454243649 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457454243649 ""}  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 47 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2609 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454243649 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2:inst6\|Equal3~2  " "Automatically promoted node ps2:inst6\|Equal3~2 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457454243651 ""}  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 195 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|Equal3~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 4297 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457454243651 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1457454246577 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1457454246589 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1457454246601 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1457454246614 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1457454246630 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1457454246641 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1457454246645 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1457454246657 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1457454248931 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1457454248946 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1457454248946 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1457454248988 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1457454248988 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1457454248988 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 27 6 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454248999 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454248999 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 16 30 " "I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 16 total pin(s) used --  30 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454248999 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 20 21 " "I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used --  21 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454248999 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.3V 2 44 " "I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used --  44 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454248999 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 15 28 " "I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454248999 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.3V 28 19 " "I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 28 total pin(s) used --  19 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454248999 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.3V 38 5 " "I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457454248999 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1457454248999 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1457454248999 ""}
+{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1 clk\[1\] DRAM_CLK~output " "PLL \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"DRAM_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "altpll.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "V/sdram_pll.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } } { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 308 0 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 328 1144 1320 344 "DRAM_CLK" "" } } } }  } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1457454249083 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCDAT " "Ignored I/O standard assignment to node \"AUD_ADCDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCLRCK " "Ignored I/O standard assignment to node \"AUD_ADCLRCK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_BCLK " "Ignored I/O standard assignment to node \"AUD_BCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACDAT " "Ignored I/O standard assignment to node \"AUD_DACDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACLRCK " "Ignored I/O standard assignment to node \"AUD_DACLRCK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_XCK " "Ignored I/O standard assignment to node \"AUD_XCK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "BUTTON\[0\] " "Ignored I/O standard assignment to node \"BUTTON\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "BUTTON\[1\] " "Ignored I/O standard assignment to node \"BUTTON\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "BUTTON\[2\] " "Ignored I/O standard assignment to node \"BUTTON\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_50_2 " "Ignored I/O standard assignment to node \"CLOCK_50_2\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50_2" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[0\] " "Ignored I/O standard assignment to node \"FL_ADDR\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[10\] " "Ignored I/O standard assignment to node \"FL_ADDR\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[11\] " "Ignored I/O standard assignment to node \"FL_ADDR\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[12\] " "Ignored I/O standard assignment to node \"FL_ADDR\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[13\] " "Ignored I/O standard assignment to node \"FL_ADDR\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[14\] " "Ignored I/O standard assignment to node \"FL_ADDR\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[15\] " "Ignored I/O standard assignment to node \"FL_ADDR\[15\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[16\] " "Ignored I/O standard assignment to node \"FL_ADDR\[16\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[17\] " "Ignored I/O standard assignment to node \"FL_ADDR\[17\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[18\] " "Ignored I/O standard assignment to node \"FL_ADDR\[18\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[19\] " "Ignored I/O standard assignment to node \"FL_ADDR\[19\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[1\] " "Ignored I/O standard assignment to node \"FL_ADDR\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[20\] " "Ignored I/O standard assignment to node \"FL_ADDR\[20\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[21\] " "Ignored I/O standard assignment to node \"FL_ADDR\[21\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[2\] " "Ignored I/O standard assignment to node \"FL_ADDR\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[3\] " "Ignored I/O standard assignment to node \"FL_ADDR\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[4\] " "Ignored I/O standard assignment to node \"FL_ADDR\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[5\] " "Ignored I/O standard assignment to node \"FL_ADDR\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[6\] " "Ignored I/O standard assignment to node \"FL_ADDR\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[7\] " "Ignored I/O standard assignment to node \"FL_ADDR\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[8\] " "Ignored I/O standard assignment to node \"FL_ADDR\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[9\] " "Ignored I/O standard assignment to node \"FL_ADDR\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_BYTE_N " "Ignored I/O standard assignment to node \"FL_BYTE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_BYTE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_CE_N " "Ignored I/O standard assignment to node \"FL_CE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ15_AM1 " "Ignored I/O standard assignment to node \"FL_DQ15_AM1\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ15_AM1" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[0\] " "Ignored I/O standard assignment to node \"FL_DQ\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[10\] " "Ignored I/O standard assignment to node \"FL_DQ\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[11\] " "Ignored I/O standard assignment to node \"FL_DQ\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[12\] " "Ignored I/O standard assignment to node \"FL_DQ\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[13\] " "Ignored I/O standard assignment to node \"FL_DQ\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[14\] " "Ignored I/O standard assignment to node \"FL_DQ\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[1\] " "Ignored I/O standard assignment to node \"FL_DQ\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[2\] " "Ignored I/O standard assignment to node \"FL_DQ\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[3\] " "Ignored I/O standard assignment to node \"FL_DQ\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[4\] " "Ignored I/O standard assignment to node \"FL_DQ\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[5\] " "Ignored I/O standard assignment to node \"FL_DQ\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[6\] " "Ignored I/O standard assignment to node \"FL_DQ\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[7\] " "Ignored I/O standard assignment to node \"FL_DQ\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[8\] " "Ignored I/O standard assignment to node \"FL_DQ\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[9\] " "Ignored I/O standard assignment to node \"FL_DQ\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_OE_N " "Ignored I/O standard assignment to node \"FL_OE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RST_N " "Ignored I/O standard assignment to node \"FL_RST_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RY " "Ignored I/O standard assignment to node \"FL_RY\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WE_N " "Ignored I/O standard assignment to node \"FL_WE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WP_N " "Ignored I/O standard assignment to node \"FL_WP_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKIN\[0\] " "Ignored I/O standard assignment to node \"GPIO0_CLKIN\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKIN\[1\] " "Ignored I/O standard assignment to node \"GPIO0_CLKIN\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKOUT\[0\] " "Ignored I/O standard assignment to node \"GPIO0_CLKOUT\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKOUT\[1\] " "Ignored I/O standard assignment to node \"GPIO0_CLKOUT\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKIN\[0\] " "Ignored I/O standard assignment to node \"GPIO1_CLKIN\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKIN\[1\] " "Ignored I/O standard assignment to node \"GPIO1_CLKIN\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKOUT\[0\] " "Ignored I/O standard assignment to node \"GPIO1_CLKOUT\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKOUT\[1\] " "Ignored I/O standard assignment to node \"GPIO1_CLKOUT\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[32\] " "Ignored I/O standard assignment to node \"GPIO_1\[32\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[33\] " "Ignored I/O standard assignment to node \"GPIO_1\[33\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[34\] " "Ignored I/O standard assignment to node \"GPIO_1\[34\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[35\] " "Ignored I/O standard assignment to node \"GPIO_1\[35\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_DP " "Ignored I/O standard assignment to node \"HEX0_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[0\] " "Ignored I/O standard assignment to node \"HEX0_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[1\] " "Ignored I/O standard assignment to node \"HEX0_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[2\] " "Ignored I/O standard assignment to node \"HEX0_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[3\] " "Ignored I/O standard assignment to node \"HEX0_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[4\] " "Ignored I/O standard assignment to node \"HEX0_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[5\] " "Ignored I/O standard assignment to node \"HEX0_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[6\] " "Ignored I/O standard assignment to node \"HEX0_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_DP " "Ignored I/O standard assignment to node \"HEX1_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[0\] " "Ignored I/O standard assignment to node \"HEX1_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[1\] " "Ignored I/O standard assignment to node \"HEX1_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[2\] " "Ignored I/O standard assignment to node \"HEX1_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[3\] " "Ignored I/O standard assignment to node \"HEX1_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[4\] " "Ignored I/O standard assignment to node \"HEX1_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[5\] " "Ignored I/O standard assignment to node \"HEX1_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[6\] " "Ignored I/O standard assignment to node \"HEX1_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_DP " "Ignored I/O standard assignment to node \"HEX2_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[0\] " "Ignored I/O standard assignment to node \"HEX2_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[1\] " "Ignored I/O standard assignment to node \"HEX2_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[2\] " "Ignored I/O standard assignment to node \"HEX2_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[3\] " "Ignored I/O standard assignment to node \"HEX2_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[4\] " "Ignored I/O standard assignment to node \"HEX2_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[5\] " "Ignored I/O standard assignment to node \"HEX2_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[6\] " "Ignored I/O standard assignment to node \"HEX2_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_DP " "Ignored I/O standard assignment to node \"HEX3_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[0\] " "Ignored I/O standard assignment to node \"HEX3_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[1\] " "Ignored I/O standard assignment to node \"HEX3_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[2\] " "Ignored I/O standard assignment to node \"HEX3_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[3\] " "Ignored I/O standard assignment to node \"HEX3_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[4\] " "Ignored I/O standard assignment to node \"HEX3_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[5\] " "Ignored I/O standard assignment to node \"HEX3_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[6\] " "Ignored I/O standard assignment to node \"HEX3_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SCLK " "Ignored I/O standard assignment to node \"I2C_SCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SDAT " "Ignored I/O standard assignment to node \"I2C_SDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "KEY\[3\] " "Ignored I/O standard assignment to node \"KEY\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_BLON " "Ignored I/O standard assignment to node \"LCD_BLON\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[0\] " "Ignored I/O standard assignment to node \"LCD_DATA\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[1\] " "Ignored I/O standard assignment to node \"LCD_DATA\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[2\] " "Ignored I/O standard assignment to node \"LCD_DATA\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[3\] " "Ignored I/O standard assignment to node \"LCD_DATA\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[4\] " "Ignored I/O standard assignment to node \"LCD_DATA\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[5\] " "Ignored I/O standard assignment to node \"LCD_DATA\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[6\] " "Ignored I/O standard assignment to node \"LCD_DATA\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[7\] " "Ignored I/O standard assignment to node \"LCD_DATA\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_EN " "Ignored I/O standard assignment to node \"LCD_EN\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_RS " "Ignored I/O standard assignment to node \"LCD_RS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_RW " "Ignored I/O standard assignment to node \"LCD_RW\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_KBCLK " "Ignored I/O standard assignment to node \"PS2_KBCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_KBDAT " "Ignored I/O standard assignment to node \"PS2_KBDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CLK " "Ignored I/O standard assignment to node \"SD_CLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CMD " "Ignored I/O standard assignment to node \"SD_CMD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT0 " "Ignored I/O standard assignment to node \"SD_DAT0\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT0" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT3 " "Ignored I/O standard assignment to node \"SD_DAT3\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_WP_N " "Ignored I/O standard assignment to node \"SD_WP_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_CTS " "Ignored I/O standard assignment to node \"UART_CTS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RTS " "Ignored I/O standard assignment to node \"UART_RTS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RXD " "Ignored I/O standard assignment to node \"UART_RXD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_TXD " "Ignored I/O standard assignment to node \"UART_TXD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454249182 ""}  } {  } 0 15709 "Ignored I/O standard assignments to the following nodes" 0 0 "Fitter" 0 -1 1457454249182 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50_2 " "Node \"CLOCK_50_2\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50_2" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457454249203 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457454249203 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_DP " "Node \"HEX0_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457454249203 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_DP " "Node \"HEX1_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457454249203 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_DP " "Node \"HEX2_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457454249203 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_DP " "Node \"HEX3_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457454249203 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1457454249203 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454249210 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1457454252314 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454253100 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1457454253147 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1457454255811 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454255821 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1457454258510 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 " "Router estimated average interconnect usage is 5% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X21_Y10 X30_Y19 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19" {  } { { "loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} 21 10 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1457454261305 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1457454261305 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454263112 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1457454263125 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1457454263125 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "2.11 " "Total time spent on timing analysis during the Fitter is 2.11 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1457454263245 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1457454263330 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1457454264776 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1457454264890 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1457454266315 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:06 " "Fitter post-fit operations ending: elapsed time is 00:00:06" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457454269154 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1457454269915 ""}
+{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "66 Cyclone III " "66 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1_CLKIN\[1\] 3.3-V LVTTL AA11 " "Pin GPIO_1_CLKIN\[1\] uses I/O standard 3.3-V LVTTL at AA11" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1_CLKIN[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_CLKIN\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKIN[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 208 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[9\] 3.3-V LVTTL D2 " "Pin SW\[9\] uses I/O standard 3.3-V LVTTL at D2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 213 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[8\] 3.3-V LVTTL E4 " "Pin SW\[8\] uses I/O standard 3.3-V LVTTL at E4" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 214 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[15\] 3.3-V LVTTL F10 " "Pin DRAM_DQ\[15\] uses I/O standard 3.3-V LVTTL at F10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 160 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[14\] 3.3-V LVTTL E10 " "Pin DRAM_DQ\[14\] uses I/O standard 3.3-V LVTTL at E10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 161 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[13\] 3.3-V LVTTL A10 " "Pin DRAM_DQ\[13\] uses I/O standard 3.3-V LVTTL at A10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 162 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[12\] 3.3-V LVTTL B10 " "Pin DRAM_DQ\[12\] uses I/O standard 3.3-V LVTTL at B10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 163 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[11\] 3.3-V LVTTL C10 " "Pin DRAM_DQ\[11\] uses I/O standard 3.3-V LVTTL at C10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 164 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[10\] 3.3-V LVTTL A9 " "Pin DRAM_DQ\[10\] uses I/O standard 3.3-V LVTTL at A9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 165 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[9\] 3.3-V LVTTL B9 " "Pin DRAM_DQ\[9\] uses I/O standard 3.3-V LVTTL at B9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 166 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[8\] 3.3-V LVTTL A8 " "Pin DRAM_DQ\[8\] uses I/O standard 3.3-V LVTTL at A8" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 167 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[7\] 3.3-V LVTTL F8 " "Pin DRAM_DQ\[7\] uses I/O standard 3.3-V LVTTL at F8" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 168 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[6\] 3.3-V LVTTL H9 " "Pin DRAM_DQ\[6\] uses I/O standard 3.3-V LVTTL at H9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 169 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[5\] 3.3-V LVTTL G9 " "Pin DRAM_DQ\[5\] uses I/O standard 3.3-V LVTTL at G9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 170 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[4\] 3.3-V LVTTL F9 " "Pin DRAM_DQ\[4\] uses I/O standard 3.3-V LVTTL at F9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 171 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[3\] 3.3-V LVTTL E9 " "Pin DRAM_DQ\[3\] uses I/O standard 3.3-V LVTTL at E9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 172 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[2\] 3.3-V LVTTL H10 " "Pin DRAM_DQ\[2\] uses I/O standard 3.3-V LVTTL at H10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 173 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[1\] 3.3-V LVTTL G10 " "Pin DRAM_DQ\[1\] uses I/O standard 3.3-V LVTTL at G10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 174 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[0\] 3.3-V LVTTL D10 " "Pin DRAM_DQ\[0\] uses I/O standard 3.3-V LVTTL at D10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 175 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[31\] 3.3-V LVTTL V7 " "Pin GPIO_1\[31\] uses I/O standard 3.3-V LVTTL at V7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 176 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL V6 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at V6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 177 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL U8 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at U8" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 178 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL Y7 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at Y7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 179 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL T9 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at T9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 180 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[26\] 3.3-V LVTTL U9 " "Pin GPIO_1\[26\] uses I/O standard 3.3-V LVTTL at U9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 181 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[25\] 3.3-V LVTTL T10 " "Pin GPIO_1\[25\] uses I/O standard 3.3-V LVTTL at T10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 182 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[24\] 3.3-V LVTTL U10 " "Pin GPIO_1\[24\] uses I/O standard 3.3-V LVTTL at U10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 183 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL R12 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at R12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 184 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R11 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R11" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 185 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL T12 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at T12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 186 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL U12 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at U12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 187 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL R14 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at R14" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 188 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL T14 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at T14" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 189 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL AB7 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at AB7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 190 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL AA7 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at AA7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 191 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL AA9 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at AA9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 192 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL AB9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at AB9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 193 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL V15 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at V15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 194 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL W15 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at W15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 195 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL T15 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at T15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 196 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL U15 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at U15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 197 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL W17 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at W17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 198 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL Y17 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at Y17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 199 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL AB17 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at AB17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 200 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL AA17 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at AA17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 201 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL AA18 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at AA18" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 202 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL AB18 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at AB18" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 203 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL AB19 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at AB19" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 204 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL AA19 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at AA19" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 205 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL AB20 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at AB20" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 206 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL AA20 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at AA20" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 207 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL P21 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at P21" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_DAT } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 576 376 552 592 "PS2_DAT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 301 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL P22 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at P22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_CLK } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 600 376 552 616 "PS2_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 302 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[4\] 3.3-V LVTTL G5 " "Pin SW\[4\] uses I/O standard 3.3-V LVTTL at G5" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 218 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[5\] 3.3-V LVTTL J7 " "Pin SW\[5\] uses I/O standard 3.3-V LVTTL at J7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 217 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL G21 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 88 424 592 104 "CLOCK_50" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 288 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL H2 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at H2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { KEY[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 104 424 592 120 "KEY" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 212 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[7\] 3.3-V LVTTL E3 " "Pin SW\[7\] uses I/O standard 3.3-V LVTTL at E3" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 215 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[6\] 3.3-V LVTTL H7 " "Pin SW\[6\] uses I/O standard 3.3-V LVTTL at H7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 216 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL G4 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at G4" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 219 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL H6 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at H6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 220 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL H5 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at H5" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 221 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL J6 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at J6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 222 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL G3 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at G3" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { KEY[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 104 424 592 120 "KEY" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 211 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1_CLKIN\[0\] 3.3-V LVTTL AB11 " "Pin GPIO_1_CLKIN\[0\] uses I/O standard 3.3-V LVTTL at AB11" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1_CLKIN[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_CLKIN\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKIN[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 209 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[2\] 3.3-V LVTTL F1 " "Pin KEY\[2\] uses I/O standard 3.3-V LVTTL at F1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { KEY[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 104 424 592 120 "KEY" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { KEY[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 210 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457454270096 ""}  } {  } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1457454270096 ""}
+{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "31 " "Following 31 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Pin GPIO_1\[31\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 176 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Pin GPIO_1\[30\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 177 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Pin GPIO_1\[29\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 178 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Pin GPIO_1\[28\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 179 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Pin GPIO_1\[27\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 180 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Pin GPIO_1\[26\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 181 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Pin GPIO_1\[25\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 182 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Pin GPIO_1\[24\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 183 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Pin GPIO_1\[23\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 184 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Pin GPIO_1\[22\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 185 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Pin GPIO_1\[21\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 186 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently enabled " "Pin GPIO_1\[20\] has a permanently enabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 187 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Pin GPIO_1\[18\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 189 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Pin GPIO_1\[17\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 190 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Pin GPIO_1\[16\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 191 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently enabled " "Pin GPIO_1\[15\] has a permanently enabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 192 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently enabled " "Pin GPIO_1\[14\] has a permanently enabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 193 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Pin GPIO_1\[13\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 194 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Pin GPIO_1\[12\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 195 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Pin GPIO_1\[11\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 196 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Pin GPIO_1\[10\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 197 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Pin GPIO_1\[9\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 198 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Pin GPIO_1\[8\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 199 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Pin GPIO_1\[7\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 200 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Pin GPIO_1\[6\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 201 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Pin GPIO_1\[5\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 202 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Pin GPIO_1\[4\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 203 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Pin GPIO_1\[3\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 204 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Pin GPIO_1\[2\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 205 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Pin GPIO_1\[1\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 206 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Pin GPIO_1\[0\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 207 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457454270203 ""}  } {  } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1457454270203 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg " "Generated suppressed messages file //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1457454270719 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 149 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 149 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1193 " "Peak virtual memory: 1193 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454274996 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:24:34 2016 " "Processing ended: Tue Mar 08 16:24:34 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454274996 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:39 " "Elapsed time: 00:00:39" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454274996 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454274996 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1457454274996 ""}
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hier_info b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hier_info
new file mode 100644
index 0000000..72a4e8f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hier_info
@@ -0,0 +1,13948 @@
+|TOP_DE0_CAMERA_MOUSE
+DRAM_LDQM <= DE0_D5M:inst.DRAM_LDQM
+CLOCK_50 => DE0_D5M:inst.CLOCK_50
+CLOCK_50 => ps2:inst6.iCLK_50
+DRAM_DQ[0] <> DE0_D5M:inst.DRAM_DQ[0]
+DRAM_DQ[1] <> DE0_D5M:inst.DRAM_DQ[1]
+DRAM_DQ[2] <> DE0_D5M:inst.DRAM_DQ[2]
+DRAM_DQ[3] <> DE0_D5M:inst.DRAM_DQ[3]
+DRAM_DQ[4] <> DE0_D5M:inst.DRAM_DQ[4]
+DRAM_DQ[5] <> DE0_D5M:inst.DRAM_DQ[5]
+DRAM_DQ[6] <> DE0_D5M:inst.DRAM_DQ[6]
+DRAM_DQ[7] <> DE0_D5M:inst.DRAM_DQ[7]
+DRAM_DQ[8] <> DE0_D5M:inst.DRAM_DQ[8]
+DRAM_DQ[9] <> DE0_D5M:inst.DRAM_DQ[9]
+DRAM_DQ[10] <> DE0_D5M:inst.DRAM_DQ[10]
+DRAM_DQ[11] <> DE0_D5M:inst.DRAM_DQ[11]
+DRAM_DQ[12] <> DE0_D5M:inst.DRAM_DQ[12]
+DRAM_DQ[13] <> DE0_D5M:inst.DRAM_DQ[13]
+DRAM_DQ[14] <> DE0_D5M:inst.DRAM_DQ[14]
+DRAM_DQ[15] <> DE0_D5M:inst.DRAM_DQ[15]
+GPIO_1[0] <> DE0_D5M:inst.GPIO_1[0]
+GPIO_1[1] <> DE0_D5M:inst.GPIO_1[1]
+GPIO_1[2] <> DE0_D5M:inst.GPIO_1[2]
+GPIO_1[3] <> DE0_D5M:inst.GPIO_1[3]
+GPIO_1[4] <> DE0_D5M:inst.GPIO_1[4]
+GPIO_1[5] <> DE0_D5M:inst.GPIO_1[5]
+GPIO_1[6] <> DE0_D5M:inst.GPIO_1[6]
+GPIO_1[7] <> DE0_D5M:inst.GPIO_1[7]
+GPIO_1[8] <> DE0_D5M:inst.GPIO_1[8]
+GPIO_1[9] <> DE0_D5M:inst.GPIO_1[9]
+GPIO_1[10] <> DE0_D5M:inst.GPIO_1[10]
+GPIO_1[11] <> DE0_D5M:inst.GPIO_1[11]
+GPIO_1[12] <> DE0_D5M:inst.GPIO_1[12]
+GPIO_1[13] <> DE0_D5M:inst.GPIO_1[13]
+GPIO_1[14] <> DE0_D5M:inst.GPIO_1[14]
+GPIO_1[15] <> DE0_D5M:inst.GPIO_1[15]
+GPIO_1[16] <> DE0_D5M:inst.GPIO_1[16]
+GPIO_1[17] <> DE0_D5M:inst.GPIO_1[17]
+GPIO_1[18] <> DE0_D5M:inst.GPIO_1[18]
+GPIO_1[19] <> DE0_D5M:inst.GPIO_1[19]
+GPIO_1[20] <> DE0_D5M:inst.GPIO_1[20]
+GPIO_1[21] <> DE0_D5M:inst.GPIO_1[21]
+GPIO_1[22] <> DE0_D5M:inst.GPIO_1[22]
+GPIO_1[23] <> DE0_D5M:inst.GPIO_1[23]
+GPIO_1[24] <> DE0_D5M:inst.GPIO_1[24]
+GPIO_1[25] <> DE0_D5M:inst.GPIO_1[25]
+GPIO_1[26] <> DE0_D5M:inst.GPIO_1[26]
+GPIO_1[27] <> DE0_D5M:inst.GPIO_1[27]
+GPIO_1[28] <> DE0_D5M:inst.GPIO_1[28]
+GPIO_1[29] <> DE0_D5M:inst.GPIO_1[29]
+GPIO_1[30] <> DE0_D5M:inst.GPIO_1[30]
+GPIO_1[31] <> DE0_D5M:inst.GPIO_1[31]
+GPIO_1_CLKIN[0] => DE0_D5M:inst.GPIO_1_CLKIN[0]
+GPIO_1_CLKIN[1] => DE0_D5M:inst.GPIO_1_CLKIN[1]
+KEY[0] => DE0_D5M:inst.KEY[0]
+KEY[0] => ps2:inst6.iRST_n
+KEY[0] => vga_mouse_square:vga_mouse_catapult_inst.arst_n
+KEY[0] => sobel:inst1.arst_n
+KEY[1] => DE0_D5M:inst.KEY[1]
+KEY[1] => ps2:inst6.iSTART
+KEY[2] => DE0_D5M:inst.KEY[2]
+SW[0] => DE0_D5M:inst.SW[0]
+SW[0] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[0]
+SW[1] => DE0_D5M:inst.SW[1]
+SW[1] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[1]
+SW[2] => DE0_D5M:inst.SW[2]
+SW[2] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[2]
+SW[3] => DE0_D5M:inst.SW[3]
+SW[3] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[3]
+SW[4] => DE0_D5M:inst.SW[4]
+SW[4] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[4]
+SW[4] => vga_mux:inst10.sel[0]
+SW[5] => DE0_D5M:inst.SW[5]
+SW[5] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[5]
+SW[5] => vga_mux:inst10.sel[1]
+SW[6] => DE0_D5M:inst.SW[6]
+SW[6] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[6]
+SW[7] => DE0_D5M:inst.SW[7]
+SW[7] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[7]
+SW[8] => DE0_D5M:inst.SW[8]
+SW[9] => DE0_D5M:inst.SW[9]
+DRAM_UDQM <= DE0_D5M:inst.DRAM_UDQM
+DRAM_BA_1 <= DE0_D5M:inst.DRAM_BA_1
+DRAM_BA_0 <= DE0_D5M:inst.DRAM_BA_0
+DRAM_CAS_N <= DE0_D5M:inst.DRAM_CAS_N
+DRAM_CKE <= DE0_D5M:inst.DRAM_CKE
+DRAM_CS_N <= DE0_D5M:inst.DRAM_CS_N
+DRAM_RAS_N <= DE0_D5M:inst.DRAM_RAS_N
+DRAM_WE_N <= DE0_D5M:inst.DRAM_WE_N
+DRAM_CLK <= DE0_D5M:inst.DRAM_CLK
+VGA_CLK <= DE0_D5M:inst.VGA_CLK
+VGA_HS <= DE0_D5M:inst.VGA_HS
+VGA_VS <= DE0_D5M:inst.VGA_VS
+PS2_DAT <> ps2:inst6.PS2_DAT
+PS2_CLK <> ps2:inst6.PS2_CLK
+DRAM_ADDR[0] <= DE0_D5M:inst.DRAM_ADDR[0]
+DRAM_ADDR[1] <= DE0_D5M:inst.DRAM_ADDR[1]
+DRAM_ADDR[2] <= DE0_D5M:inst.DRAM_ADDR[2]
+DRAM_ADDR[3] <= DE0_D5M:inst.DRAM_ADDR[3]
+DRAM_ADDR[4] <= DE0_D5M:inst.DRAM_ADDR[4]
+DRAM_ADDR[5] <= DE0_D5M:inst.DRAM_ADDR[5]
+DRAM_ADDR[6] <= DE0_D5M:inst.DRAM_ADDR[6]
+DRAM_ADDR[7] <= DE0_D5M:inst.DRAM_ADDR[7]
+DRAM_ADDR[8] <= DE0_D5M:inst.DRAM_ADDR[8]
+DRAM_ADDR[9] <= DE0_D5M:inst.DRAM_ADDR[9]
+DRAM_ADDR[10] <= DE0_D5M:inst.DRAM_ADDR[10]
+DRAM_ADDR[11] <= DE0_D5M:inst.DRAM_ADDR[11]
+GPIO_1_CLKOUT[0] <= DE0_D5M:inst.GPIO_1_CLKOUT[0]
+GPIO_1_CLKOUT[1] <= DE0_D5M:inst.GPIO_1_CLKOUT[1]
+HEX0[0] <= ps2:inst6.oX_MOV1[0]
+HEX0[1] <= ps2:inst6.oX_MOV1[1]
+HEX0[2] <= ps2:inst6.oX_MOV1[2]
+HEX0[3] <= ps2:inst6.oX_MOV1[3]
+HEX0[4] <= ps2:inst6.oX_MOV1[4]
+HEX0[5] <= ps2:inst6.oX_MOV1[5]
+HEX0[6] <= ps2:inst6.oX_MOV1[6]
+HEX1[0] <= ps2:inst6.oX_MOV2[0]
+HEX1[1] <= ps2:inst6.oX_MOV2[1]
+HEX1[2] <= ps2:inst6.oX_MOV2[2]
+HEX1[3] <= ps2:inst6.oX_MOV2[3]
+HEX1[4] <= ps2:inst6.oX_MOV2[4]
+HEX1[5] <= ps2:inst6.oX_MOV2[5]
+HEX1[6] <= ps2:inst6.oX_MOV2[6]
+HEX2[0] <= ps2:inst6.oY_MOV1[0]
+HEX2[1] <= ps2:inst6.oY_MOV1[1]
+HEX2[2] <= ps2:inst6.oY_MOV1[2]
+HEX2[3] <= ps2:inst6.oY_MOV1[3]
+HEX2[4] <= ps2:inst6.oY_MOV1[4]
+HEX2[5] <= ps2:inst6.oY_MOV1[5]
+HEX2[6] <= ps2:inst6.oY_MOV1[6]
+HEX3[0] <= ps2:inst6.oY_MOV2[0]
+HEX3[1] <= ps2:inst6.oY_MOV2[1]
+HEX3[2] <= ps2:inst6.oY_MOV2[2]
+HEX3[3] <= ps2:inst6.oY_MOV2[3]
+HEX3[4] <= ps2:inst6.oY_MOV2[4]
+HEX3[5] <= ps2:inst6.oY_MOV2[5]
+HEX3[6] <= ps2:inst6.oY_MOV2[6]
+LEDG[0] <= ps2:inst6.oRIGBUT
+LEDG[1] <= ps2:inst6.oMIDBUT
+LEDG[2] <= ps2:inst6.oLEFBUT
+LEDG[3] <= <GND>
+LEDG[4] <= <GND>
+LEDG[5] <= <GND>
+LEDG[6] <= <GND>
+LEDG[7] <= <GND>
+LEDG[8] <= <GND>
+LEDG[9] <= <GND>
+VGA_B[0] <= VGA_MUX_OUT[6].DB_MAX_OUTPUT_PORT_TYPE
+VGA_B[1] <= VGA_MUX_OUT[7].DB_MAX_OUTPUT_PORT_TYPE
+VGA_B[2] <= VGA_MUX_OUT[8].DB_MAX_OUTPUT_PORT_TYPE
+VGA_B[3] <= VGA_MUX_OUT[9].DB_MAX_OUTPUT_PORT_TYPE
+VGA_G[0] <= VGA_MUX_OUT[16].DB_MAX_OUTPUT_PORT_TYPE
+VGA_G[1] <= VGA_MUX_OUT[17].DB_MAX_OUTPUT_PORT_TYPE
+VGA_G[2] <= VGA_MUX_OUT[18].DB_MAX_OUTPUT_PORT_TYPE
+VGA_G[3] <= VGA_MUX_OUT[19].DB_MAX_OUTPUT_PORT_TYPE
+VGA_R[0] <= VGA_MUX_OUT[26].DB_MAX_OUTPUT_PORT_TYPE
+VGA_R[1] <= VGA_MUX_OUT[27].DB_MAX_OUTPUT_PORT_TYPE
+VGA_R[2] <= VGA_MUX_OUT[28].DB_MAX_OUTPUT_PORT_TYPE
+VGA_R[3] <= VGA_MUX_OUT[29].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst
+CLOCK_50 => CLOCK_50.IN4
+KEY[0] => KEY[0].IN1
+KEY[1] => _.IN1
+KEY[2] => _.IN1
+SW[0] => SW[0].IN1
+SW[1] => SW[1].IN1
+SW[2] => SW[2].IN1
+SW[3] => ~NO_FANOUT~
+SW[4] => ~NO_FANOUT~
+SW[5] => ~NO_FANOUT~
+SW[6] => ~NO_FANOUT~
+SW[7] => ~NO_FANOUT~
+SW[8] => ~NO_FANOUT~
+SW[9] => ~NO_FANOUT~
+LEDG[0] <= Y_Cont[0].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[1] <= Y_Cont[1].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[2] <= Y_Cont[2].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[3] <= Y_Cont[3].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[4] <= Y_Cont[4].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[5] <= Y_Cont[5].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[6] <= Y_Cont[6].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[7] <= Y_Cont[7].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[8] <= Y_Cont[8].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[9] <= Y_Cont[9].DB_MAX_OUTPUT_PORT_TYPE
+HEX0[0] <= SEG7_LUT_8:u5.oSEG0
+HEX0[1] <= SEG7_LUT_8:u5.oSEG0
+HEX0[2] <= SEG7_LUT_8:u5.oSEG0
+HEX0[3] <= SEG7_LUT_8:u5.oSEG0
+HEX0[4] <= SEG7_LUT_8:u5.oSEG0
+HEX0[5] <= SEG7_LUT_8:u5.oSEG0
+HEX0[6] <= SEG7_LUT_8:u5.oSEG0
+HEX1[0] <= SEG7_LUT_8:u5.oSEG1
+HEX1[1] <= SEG7_LUT_8:u5.oSEG1
+HEX1[2] <= SEG7_LUT_8:u5.oSEG1
+HEX1[3] <= SEG7_LUT_8:u5.oSEG1
+HEX1[4] <= SEG7_LUT_8:u5.oSEG1
+HEX1[5] <= SEG7_LUT_8:u5.oSEG1
+HEX1[6] <= SEG7_LUT_8:u5.oSEG1
+HEX2[0] <= SEG7_LUT_8:u5.oSEG2
+HEX2[1] <= SEG7_LUT_8:u5.oSEG2
+HEX2[2] <= SEG7_LUT_8:u5.oSEG2
+HEX2[3] <= SEG7_LUT_8:u5.oSEG2
+HEX2[4] <= SEG7_LUT_8:u5.oSEG2
+HEX2[5] <= SEG7_LUT_8:u5.oSEG2
+HEX2[6] <= SEG7_LUT_8:u5.oSEG2
+HEX3[0] <= SEG7_LUT_8:u5.oSEG3
+HEX3[1] <= SEG7_LUT_8:u5.oSEG3
+HEX3[2] <= SEG7_LUT_8:u5.oSEG3
+HEX3[3] <= SEG7_LUT_8:u5.oSEG3
+HEX3[4] <= SEG7_LUT_8:u5.oSEG3
+HEX3[5] <= SEG7_LUT_8:u5.oSEG3
+HEX3[6] <= SEG7_LUT_8:u5.oSEG3
+DRAM_DQ[0] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[1] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[2] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[3] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[4] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[5] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[6] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[7] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[8] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[9] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[10] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[11] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[12] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[13] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[14] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[15] <> Sdram_Control_4Port:u7.DQ
+DRAM_ADDR[0] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[1] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[2] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[3] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[4] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[5] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[6] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[7] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[8] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[9] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[10] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[11] <= Sdram_Control_4Port:u7.SA
+DRAM_LDQM <= Sdram_Control_4Port:u7.DQM
+DRAM_UDQM <= Sdram_Control_4Port:u7.DQM
+DRAM_WE_N <= Sdram_Control_4Port:u7.WE_N
+DRAM_CAS_N <= Sdram_Control_4Port:u7.CAS_N
+DRAM_RAS_N <= Sdram_Control_4Port:u7.RAS_N
+DRAM_CS_N <= Sdram_Control_4Port:u7.CS_N
+DRAM_BA_0 <= Sdram_Control_4Port:u7.BA
+DRAM_BA_1 <= Sdram_Control_4Port:u7.BA
+DRAM_CLK <= sdram_pll:u6.c1
+DRAM_CKE <= Sdram_Control_4Port:u7.CKE
+VGA_HS <= VGA_Controller:u1.oVGA_H_SYNC
+VGA_VS <= VGA_Controller:u1.oVGA_V_SYNC
+VGA_R[0] <= VGA_Controller:u1.oVGA_R
+VGA_R[1] <= VGA_Controller:u1.oVGA_R
+VGA_R[2] <= VGA_Controller:u1.oVGA_R
+VGA_R[3] <= VGA_Controller:u1.oVGA_R
+VGA_R[4] <= VGA_Controller:u1.oVGA_R
+VGA_R[5] <= VGA_Controller:u1.oVGA_R
+VGA_R[6] <= VGA_Controller:u1.oVGA_R
+VGA_R[7] <= VGA_Controller:u1.oVGA_R
+VGA_R[8] <= VGA_Controller:u1.oVGA_R
+VGA_R[9] <= VGA_Controller:u1.oVGA_R
+VGA_G[0] <= VGA_Controller:u1.oVGA_G
+VGA_G[1] <= VGA_Controller:u1.oVGA_G
+VGA_G[2] <= VGA_Controller:u1.oVGA_G
+VGA_G[3] <= VGA_Controller:u1.oVGA_G
+VGA_G[4] <= VGA_Controller:u1.oVGA_G
+VGA_G[5] <= VGA_Controller:u1.oVGA_G
+VGA_G[6] <= VGA_Controller:u1.oVGA_G
+VGA_G[7] <= VGA_Controller:u1.oVGA_G
+VGA_G[8] <= VGA_Controller:u1.oVGA_G
+VGA_G[9] <= VGA_Controller:u1.oVGA_G
+VGA_B[0] <= VGA_Controller:u1.oVGA_B
+VGA_B[1] <= VGA_Controller:u1.oVGA_B
+VGA_B[2] <= VGA_Controller:u1.oVGA_B
+VGA_B[3] <= VGA_Controller:u1.oVGA_B
+VGA_B[4] <= VGA_Controller:u1.oVGA_B
+VGA_B[5] <= VGA_Controller:u1.oVGA_B
+VGA_B[6] <= VGA_Controller:u1.oVGA_B
+VGA_B[7] <= VGA_Controller:u1.oVGA_B
+VGA_B[8] <= VGA_Controller:u1.oVGA_B
+VGA_B[9] <= VGA_Controller:u1.oVGA_B
+VGA_CLK <= GPIO_1_CLKOUT[0].DB_MAX_OUTPUT_PORT_TYPE
+VGA_X[0] <= VGA_Controller:u1.oVGA_Y
+VGA_X[1] <= VGA_Controller:u1.oVGA_Y
+VGA_X[2] <= VGA_Controller:u1.oVGA_Y
+VGA_X[3] <= VGA_Controller:u1.oVGA_Y
+VGA_X[4] <= VGA_Controller:u1.oVGA_Y
+VGA_X[5] <= VGA_Controller:u1.oVGA_Y
+VGA_X[6] <= VGA_Controller:u1.oVGA_Y
+VGA_X[7] <= VGA_Controller:u1.oVGA_Y
+VGA_X[8] <= VGA_Controller:u1.oVGA_Y
+VGA_X[9] <= VGA_Controller:u1.oVGA_Y
+VGA_X[10] <= VGA_Controller:u1.oVGA_Y
+VGA_X[11] <= VGA_Controller:u1.oVGA_Y
+VGA_Y[0] <= VGA_Controller:u1.oVGA_X
+VGA_Y[1] <= VGA_Controller:u1.oVGA_X
+VGA_Y[2] <= VGA_Controller:u1.oVGA_X
+VGA_Y[3] <= VGA_Controller:u1.oVGA_X
+VGA_Y[4] <= VGA_Controller:u1.oVGA_X
+VGA_Y[5] <= VGA_Controller:u1.oVGA_X
+VGA_Y[6] <= VGA_Controller:u1.oVGA_X
+VGA_Y[7] <= VGA_Controller:u1.oVGA_X
+VGA_Y[8] <= VGA_Controller:u1.oVGA_X
+VGA_Y[9] <= VGA_Controller:u1.oVGA_X
+VGA_Y[10] <= VGA_Controller:u1.oVGA_X
+VGA_Y[11] <= VGA_Controller:u1.oVGA_X
+VGA_ACTIVE <= VGA_Controller:u1.oVGA_ACTIVE
+GPIO_1_CLKIN[0] => CCD_PIXCLK.IN2
+GPIO_1_CLKIN[1] => ~NO_FANOUT~
+GPIO_1_CLKOUT[0] <= GPIO_1_CLKOUT[0].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1_CLKOUT[1] <= <GND>
+GPIO_1[12] <> <UNC>
+GPIO_1[13] <> <UNC>
+GPIO_1[14] <> GPIO_1[14]
+GPIO_1[15] <> <VCC>
+GPIO_1[16] <> <UNC>
+GPIO_1[19] <> I2C_CCD_Config:u8.I2C_SDAT
+GPIO_1[20] <> I2C_CCD_Config:u8.I2C_SCLK
+GPIO_1[21] <> <UNC>
+GPIO_1[22] <> <UNC>
+GPIO_1[23] <> <UNC>
+GPIO_1[24] <> <UNC>
+GPIO_1[25] <> <UNC>
+GPIO_1[26] <> <UNC>
+GPIO_1[27] <> <UNC>
+GPIO_1[28] <> <UNC>
+GPIO_1[29] <> <UNC>
+GPIO_1[30] <> <UNC>
+GPIO_1[31] <> <UNC>
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1
+iRed[0] => oVGA_R.DATAB
+iRed[1] => oVGA_R.DATAB
+iRed[2] => oVGA_R.DATAB
+iRed[3] => oVGA_R.DATAB
+iRed[4] => oVGA_R.DATAB
+iRed[5] => oVGA_R.DATAB
+iRed[6] => oVGA_R.DATAB
+iRed[7] => oVGA_R.DATAB
+iRed[8] => oVGA_R.DATAB
+iRed[9] => oVGA_R.DATAB
+iGreen[0] => oVGA_G.DATAB
+iGreen[1] => oVGA_G.DATAB
+iGreen[2] => oVGA_G.DATAB
+iGreen[3] => oVGA_G.DATAB
+iGreen[4] => oVGA_G.DATAB
+iGreen[5] => oVGA_G.DATAB
+iGreen[6] => oVGA_G.DATAB
+iGreen[7] => oVGA_G.DATAB
+iGreen[8] => oVGA_G.DATAB
+iGreen[9] => oVGA_G.DATAB
+iBlue[0] => oVGA_B.DATAB
+iBlue[1] => oVGA_B.DATAB
+iBlue[2] => oVGA_B.DATAB
+iBlue[3] => oVGA_B.DATAB
+iBlue[4] => oVGA_B.DATAB
+iBlue[5] => oVGA_B.DATAB
+iBlue[6] => oVGA_B.DATAB
+iBlue[7] => oVGA_B.DATAB
+iBlue[8] => oVGA_B.DATAB
+iBlue[9] => oVGA_B.DATAB
+oRequest <= oRequest~reg0.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[0] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[1] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[2] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[3] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[4] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[5] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[6] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[7] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[8] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[9] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[0] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[1] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[2] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[3] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[4] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[5] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[6] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[7] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[8] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[9] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[0] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[1] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[2] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[3] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[4] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[5] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[6] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[7] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[8] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[9] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_H_SYNC <= oVGA_H_SYNC~reg0.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_V_SYNC <= oVGA_V_SYNC~reg0.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_SYNC <= <GND>
+oVGA_BLANK <= oVGA_BLANK.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_CLOCK <= iCLK.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[0] <= H_Cont[0].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[1] <= H_Cont[1].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[2] <= H_Cont[2].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[3] <= H_Cont[3].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[4] <= H_Cont[4].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[5] <= H_Cont[5].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[6] <= H_Cont[6].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[7] <= H_Cont[7].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[8] <= H_Cont[8].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[9] <= H_Cont[9].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[10] <= H_Cont[10].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[11] <= H_Cont[11].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[0] <= V_Cont[0].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[1] <= V_Cont[1].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[2] <= V_Cont[2].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[3] <= V_Cont[3].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[4] <= V_Cont[4].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[5] <= V_Cont[5].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[6] <= V_Cont[6].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[7] <= V_Cont[7].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[8] <= V_Cont[8].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[9] <= V_Cont[9].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[10] <= V_Cont[10].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[11] <= V_Cont[11].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_ACTIVE <= active.DB_MAX_OUTPUT_PORT_TYPE
+iCLK => oVGA_V_SYNC~reg0.CLK
+iCLK => V_Cont[0].CLK
+iCLK => V_Cont[1].CLK
+iCLK => V_Cont[2].CLK
+iCLK => V_Cont[3].CLK
+iCLK => V_Cont[4].CLK
+iCLK => V_Cont[5].CLK
+iCLK => V_Cont[6].CLK
+iCLK => V_Cont[7].CLK
+iCLK => V_Cont[8].CLK
+iCLK => V_Cont[9].CLK
+iCLK => V_Cont[10].CLK
+iCLK => V_Cont[11].CLK
+iCLK => active.CLK
+iCLK => oVGA_H_SYNC~reg0.CLK
+iCLK => H_Cont[0].CLK
+iCLK => H_Cont[1].CLK
+iCLK => H_Cont[2].CLK
+iCLK => H_Cont[3].CLK
+iCLK => H_Cont[4].CLK
+iCLK => H_Cont[5].CLK
+iCLK => H_Cont[6].CLK
+iCLK => H_Cont[7].CLK
+iCLK => H_Cont[8].CLK
+iCLK => H_Cont[9].CLK
+iCLK => H_Cont[10].CLK
+iCLK => H_Cont[11].CLK
+iCLK => oRequest~reg0.CLK
+iCLK => oVGA_CLOCK.DATAIN
+iRST_N => active.ACLR
+iRST_N => oVGA_H_SYNC~reg0.ACLR
+iRST_N => H_Cont[0].ACLR
+iRST_N => H_Cont[1].ACLR
+iRST_N => H_Cont[2].ACLR
+iRST_N => H_Cont[3].ACLR
+iRST_N => H_Cont[4].ACLR
+iRST_N => H_Cont[5].ACLR
+iRST_N => H_Cont[6].ACLR
+iRST_N => H_Cont[7].ACLR
+iRST_N => H_Cont[8].ACLR
+iRST_N => H_Cont[9].ACLR
+iRST_N => H_Cont[10].ACLR
+iRST_N => H_Cont[11].ACLR
+iRST_N => oRequest~reg0.ACLR
+iRST_N => oVGA_V_SYNC~reg0.ACLR
+iRST_N => V_Cont[0].ACLR
+iRST_N => V_Cont[1].ACLR
+iRST_N => V_Cont[2].ACLR
+iRST_N => V_Cont[3].ACLR
+iRST_N => V_Cont[4].ACLR
+iRST_N => V_Cont[5].ACLR
+iRST_N => V_Cont[6].ACLR
+iRST_N => V_Cont[7].ACLR
+iRST_N => V_Cont[8].ACLR
+iRST_N => V_Cont[9].ACLR
+iRST_N => V_Cont[10].ACLR
+iRST_N => V_Cont[11].ACLR
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Reset_Delay:u2
+iCLK => oRST_2~reg0.CLK
+iCLK => oRST_1~reg0.CLK
+iCLK => oRST_0~reg0.CLK
+iCLK => Cont[0].CLK
+iCLK => Cont[1].CLK
+iCLK => Cont[2].CLK
+iCLK => Cont[3].CLK
+iCLK => Cont[4].CLK
+iCLK => Cont[5].CLK
+iCLK => Cont[6].CLK
+iCLK => Cont[7].CLK
+iCLK => Cont[8].CLK
+iCLK => Cont[9].CLK
+iCLK => Cont[10].CLK
+iCLK => Cont[11].CLK
+iCLK => Cont[12].CLK
+iCLK => Cont[13].CLK
+iCLK => Cont[14].CLK
+iCLK => Cont[15].CLK
+iCLK => Cont[16].CLK
+iCLK => Cont[17].CLK
+iCLK => Cont[18].CLK
+iCLK => Cont[19].CLK
+iCLK => Cont[20].CLK
+iCLK => Cont[21].CLK
+iCLK => Cont[22].CLK
+iCLK => Cont[23].CLK
+iCLK => Cont[24].CLK
+iCLK => Cont[25].CLK
+iCLK => Cont[26].CLK
+iCLK => Cont[27].CLK
+iCLK => Cont[28].CLK
+iCLK => Cont[29].CLK
+iCLK => Cont[30].CLK
+iCLK => Cont[31].CLK
+iRST => oRST_2~reg0.ACLR
+iRST => oRST_1~reg0.ACLR
+iRST => oRST_0~reg0.ACLR
+iRST => Cont[0].ACLR
+iRST => Cont[1].ACLR
+iRST => Cont[2].ACLR
+iRST => Cont[3].ACLR
+iRST => Cont[4].ACLR
+iRST => Cont[5].ACLR
+iRST => Cont[6].ACLR
+iRST => Cont[7].ACLR
+iRST => Cont[8].ACLR
+iRST => Cont[9].ACLR
+iRST => Cont[10].ACLR
+iRST => Cont[11].ACLR
+iRST => Cont[12].ACLR
+iRST => Cont[13].ACLR
+iRST => Cont[14].ACLR
+iRST => Cont[15].ACLR
+iRST => Cont[16].ACLR
+iRST => Cont[17].ACLR
+iRST => Cont[18].ACLR
+iRST => Cont[19].ACLR
+iRST => Cont[20].ACLR
+iRST => Cont[21].ACLR
+iRST => Cont[22].ACLR
+iRST => Cont[23].ACLR
+iRST => Cont[24].ACLR
+iRST => Cont[25].ACLR
+iRST => Cont[26].ACLR
+iRST => Cont[27].ACLR
+iRST => Cont[28].ACLR
+iRST => Cont[29].ACLR
+iRST => Cont[30].ACLR
+iRST => Cont[31].ACLR
+oRST_0 <= oRST_0~reg0.DB_MAX_OUTPUT_PORT_TYPE
+oRST_1 <= oRST_1~reg0.DB_MAX_OUTPUT_PORT_TYPE
+oRST_2 <= oRST_2~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3
+oDATA[0] <= mCCD_DATA[0].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[1] <= mCCD_DATA[1].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[2] <= mCCD_DATA[2].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[3] <= mCCD_DATA[3].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[4] <= mCCD_DATA[4].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[5] <= mCCD_DATA[5].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[6] <= mCCD_DATA[6].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[7] <= mCCD_DATA[7].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[8] <= mCCD_DATA[8].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[9] <= mCCD_DATA[9].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[10] <= mCCD_DATA[10].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[11] <= mCCD_DATA[11].DB_MAX_OUTPUT_PORT_TYPE
+oDVAL <= oDVAL.DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[0] <= X_Cont[0].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[1] <= X_Cont[1].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[2] <= X_Cont[2].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[3] <= X_Cont[3].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[4] <= X_Cont[4].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[5] <= X_Cont[5].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[6] <= X_Cont[6].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[7] <= X_Cont[7].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[8] <= X_Cont[8].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[9] <= X_Cont[9].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[10] <= X_Cont[10].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[11] <= X_Cont[11].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[12] <= X_Cont[12].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[13] <= X_Cont[13].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[14] <= X_Cont[14].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[15] <= X_Cont[15].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[0] <= Y_Cont[0].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[1] <= Y_Cont[1].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[2] <= Y_Cont[2].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[3] <= Y_Cont[3].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[4] <= Y_Cont[4].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[5] <= Y_Cont[5].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[6] <= Y_Cont[6].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[7] <= Y_Cont[7].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[8] <= Y_Cont[8].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[9] <= Y_Cont[9].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[10] <= Y_Cont[10].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[11] <= Y_Cont[11].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[12] <= Y_Cont[12].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[13] <= Y_Cont[13].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[14] <= Y_Cont[14].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[15] <= Y_Cont[15].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[0] <= Frame_Cont[0].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[1] <= Frame_Cont[1].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[2] <= Frame_Cont[2].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[3] <= Frame_Cont[3].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[4] <= Frame_Cont[4].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[5] <= Frame_Cont[5].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[6] <= Frame_Cont[6].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[7] <= Frame_Cont[7].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[8] <= Frame_Cont[8].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[9] <= Frame_Cont[9].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[10] <= Frame_Cont[10].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[11] <= Frame_Cont[11].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[12] <= Frame_Cont[12].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[13] <= Frame_Cont[13].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[14] <= Frame_Cont[14].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[15] <= Frame_Cont[15].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[16] <= Frame_Cont[16].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[17] <= Frame_Cont[17].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[18] <= Frame_Cont[18].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[19] <= Frame_Cont[19].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[20] <= Frame_Cont[20].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[21] <= Frame_Cont[21].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[22] <= Frame_Cont[22].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[23] <= Frame_Cont[23].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[24] <= Frame_Cont[24].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[25] <= Frame_Cont[25].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[26] <= Frame_Cont[26].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[27] <= Frame_Cont[27].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[28] <= Frame_Cont[28].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[29] <= Frame_Cont[29].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[30] <= Frame_Cont[30].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[31] <= Frame_Cont[31].DB_MAX_OUTPUT_PORT_TYPE
+iDATA[0] => mCCD_DATA.DATAB
+iDATA[1] => mCCD_DATA.DATAB
+iDATA[2] => mCCD_DATA.DATAB
+iDATA[3] => mCCD_DATA.DATAB
+iDATA[4] => mCCD_DATA.DATAB
+iDATA[5] => mCCD_DATA.DATAB
+iDATA[6] => mCCD_DATA.DATAB
+iDATA[7] => mCCD_DATA.DATAB
+iDATA[8] => mCCD_DATA.DATAB
+iDATA[9] => mCCD_DATA.DATAB
+iDATA[10] => mCCD_DATA.DATAB
+iDATA[11] => mCCD_DATA.DATAB
+iFVAL => Pre_FVAL.DATAIN
+iFVAL => Equal0.IN1
+iFVAL => Equal1.IN0
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_LVAL.DATAIN
+iSTART => mSTART.OUTPUTSELECT
+iEND => mSTART.OUTPUTSELECT
+iCLK => mCCD_DATA[0].CLK
+iCLK => mCCD_DATA[1].CLK
+iCLK => mCCD_DATA[2].CLK
+iCLK => mCCD_DATA[3].CLK
+iCLK => mCCD_DATA[4].CLK
+iCLK => mCCD_DATA[5].CLK
+iCLK => mCCD_DATA[6].CLK
+iCLK => mCCD_DATA[7].CLK
+iCLK => mCCD_DATA[8].CLK
+iCLK => mCCD_DATA[9].CLK
+iCLK => mCCD_DATA[10].CLK
+iCLK => mCCD_DATA[11].CLK
+iCLK => Frame_Cont[0].CLK
+iCLK => Frame_Cont[1].CLK
+iCLK => Frame_Cont[2].CLK
+iCLK => Frame_Cont[3].CLK
+iCLK => Frame_Cont[4].CLK
+iCLK => Frame_Cont[5].CLK
+iCLK => Frame_Cont[6].CLK
+iCLK => Frame_Cont[7].CLK
+iCLK => Frame_Cont[8].CLK
+iCLK => Frame_Cont[9].CLK
+iCLK => Frame_Cont[10].CLK
+iCLK => Frame_Cont[11].CLK
+iCLK => Frame_Cont[12].CLK
+iCLK => Frame_Cont[13].CLK
+iCLK => Frame_Cont[14].CLK
+iCLK => Frame_Cont[15].CLK
+iCLK => Frame_Cont[16].CLK
+iCLK => Frame_Cont[17].CLK
+iCLK => Frame_Cont[18].CLK
+iCLK => Frame_Cont[19].CLK
+iCLK => Frame_Cont[20].CLK
+iCLK => Frame_Cont[21].CLK
+iCLK => Frame_Cont[22].CLK
+iCLK => Frame_Cont[23].CLK
+iCLK => Frame_Cont[24].CLK
+iCLK => Frame_Cont[25].CLK
+iCLK => Frame_Cont[26].CLK
+iCLK => Frame_Cont[27].CLK
+iCLK => Frame_Cont[28].CLK
+iCLK => Frame_Cont[29].CLK
+iCLK => Frame_Cont[30].CLK
+iCLK => Frame_Cont[31].CLK
+iCLK => Y_Cont[0].CLK
+iCLK => Y_Cont[1].CLK
+iCLK => Y_Cont[2].CLK
+iCLK => Y_Cont[3].CLK
+iCLK => Y_Cont[4].CLK
+iCLK => Y_Cont[5].CLK
+iCLK => Y_Cont[6].CLK
+iCLK => Y_Cont[7].CLK
+iCLK => Y_Cont[8].CLK
+iCLK => Y_Cont[9].CLK
+iCLK => Y_Cont[10].CLK
+iCLK => Y_Cont[11].CLK
+iCLK => Y_Cont[12].CLK
+iCLK => Y_Cont[13].CLK
+iCLK => Y_Cont[14].CLK
+iCLK => Y_Cont[15].CLK
+iCLK => X_Cont[0].CLK
+iCLK => X_Cont[1].CLK
+iCLK => X_Cont[2].CLK
+iCLK => X_Cont[3].CLK
+iCLK => X_Cont[4].CLK
+iCLK => X_Cont[5].CLK
+iCLK => X_Cont[6].CLK
+iCLK => X_Cont[7].CLK
+iCLK => X_Cont[8].CLK
+iCLK => X_Cont[9].CLK
+iCLK => X_Cont[10].CLK
+iCLK => X_Cont[11].CLK
+iCLK => X_Cont[12].CLK
+iCLK => X_Cont[13].CLK
+iCLK => X_Cont[14].CLK
+iCLK => X_Cont[15].CLK
+iCLK => mCCD_LVAL.CLK
+iCLK => mCCD_FVAL.CLK
+iCLK => Pre_FVAL.CLK
+iCLK => mSTART.CLK
+iRST => Y_Cont[0].ACLR
+iRST => Y_Cont[1].ACLR
+iRST => Y_Cont[2].ACLR
+iRST => Y_Cont[3].ACLR
+iRST => Y_Cont[4].ACLR
+iRST => Y_Cont[5].ACLR
+iRST => Y_Cont[6].ACLR
+iRST => Y_Cont[7].ACLR
+iRST => Y_Cont[8].ACLR
+iRST => Y_Cont[9].ACLR
+iRST => Y_Cont[10].ACLR
+iRST => Y_Cont[11].ACLR
+iRST => Y_Cont[12].ACLR
+iRST => Y_Cont[13].ACLR
+iRST => Y_Cont[14].ACLR
+iRST => Y_Cont[15].ACLR
+iRST => X_Cont[0].ACLR
+iRST => X_Cont[1].ACLR
+iRST => X_Cont[2].ACLR
+iRST => X_Cont[3].ACLR
+iRST => X_Cont[4].ACLR
+iRST => X_Cont[5].ACLR
+iRST => X_Cont[6].ACLR
+iRST => X_Cont[7].ACLR
+iRST => X_Cont[8].ACLR
+iRST => X_Cont[9].ACLR
+iRST => X_Cont[10].ACLR
+iRST => X_Cont[11].ACLR
+iRST => X_Cont[12].ACLR
+iRST => X_Cont[13].ACLR
+iRST => X_Cont[14].ACLR
+iRST => X_Cont[15].ACLR
+iRST => mCCD_LVAL.ACLR
+iRST => mCCD_FVAL.ACLR
+iRST => Pre_FVAL.ACLR
+iRST => mCCD_DATA[0].ACLR
+iRST => mCCD_DATA[1].ACLR
+iRST => mCCD_DATA[2].ACLR
+iRST => mCCD_DATA[3].ACLR
+iRST => mCCD_DATA[4].ACLR
+iRST => mCCD_DATA[5].ACLR
+iRST => mCCD_DATA[6].ACLR
+iRST => mCCD_DATA[7].ACLR
+iRST => mCCD_DATA[8].ACLR
+iRST => mCCD_DATA[9].ACLR
+iRST => mCCD_DATA[10].ACLR
+iRST => mCCD_DATA[11].ACLR
+iRST => Frame_Cont[0].ACLR
+iRST => Frame_Cont[1].ACLR
+iRST => Frame_Cont[2].ACLR
+iRST => Frame_Cont[3].ACLR
+iRST => Frame_Cont[4].ACLR
+iRST => Frame_Cont[5].ACLR
+iRST => Frame_Cont[6].ACLR
+iRST => Frame_Cont[7].ACLR
+iRST => Frame_Cont[8].ACLR
+iRST => Frame_Cont[9].ACLR
+iRST => Frame_Cont[10].ACLR
+iRST => Frame_Cont[11].ACLR
+iRST => Frame_Cont[12].ACLR
+iRST => Frame_Cont[13].ACLR
+iRST => Frame_Cont[14].ACLR
+iRST => Frame_Cont[15].ACLR
+iRST => Frame_Cont[16].ACLR
+iRST => Frame_Cont[17].ACLR
+iRST => Frame_Cont[18].ACLR
+iRST => Frame_Cont[19].ACLR
+iRST => Frame_Cont[20].ACLR
+iRST => Frame_Cont[21].ACLR
+iRST => Frame_Cont[22].ACLR
+iRST => Frame_Cont[23].ACLR
+iRST => Frame_Cont[24].ACLR
+iRST => Frame_Cont[25].ACLR
+iRST => Frame_Cont[26].ACLR
+iRST => Frame_Cont[27].ACLR
+iRST => Frame_Cont[28].ACLR
+iRST => Frame_Cont[29].ACLR
+iRST => Frame_Cont[30].ACLR
+iRST => Frame_Cont[31].ACLR
+iRST => mSTART.ACLR
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4
+oRed[0] <= mCCD_R[0].DB_MAX_OUTPUT_PORT_TYPE
+oRed[1] <= mCCD_R[1].DB_MAX_OUTPUT_PORT_TYPE
+oRed[2] <= mCCD_R[2].DB_MAX_OUTPUT_PORT_TYPE
+oRed[3] <= mCCD_R[3].DB_MAX_OUTPUT_PORT_TYPE
+oRed[4] <= mCCD_R[4].DB_MAX_OUTPUT_PORT_TYPE
+oRed[5] <= mCCD_R[5].DB_MAX_OUTPUT_PORT_TYPE
+oRed[6] <= mCCD_R[6].DB_MAX_OUTPUT_PORT_TYPE
+oRed[7] <= mCCD_R[7].DB_MAX_OUTPUT_PORT_TYPE
+oRed[8] <= mCCD_R[8].DB_MAX_OUTPUT_PORT_TYPE
+oRed[9] <= mCCD_R[9].DB_MAX_OUTPUT_PORT_TYPE
+oRed[10] <= mCCD_R[10].DB_MAX_OUTPUT_PORT_TYPE
+oRed[11] <= mCCD_R[11].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[0] <= mCCD_G[1].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[1] <= mCCD_G[2].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[2] <= mCCD_G[3].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[3] <= mCCD_G[4].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[4] <= mCCD_G[5].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[5] <= mCCD_G[6].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[6] <= mCCD_G[7].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[7] <= mCCD_G[8].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[8] <= mCCD_G[9].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[9] <= mCCD_G[10].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[10] <= mCCD_G[11].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[11] <= mCCD_G[12].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[0] <= mCCD_B[0].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[1] <= mCCD_B[1].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[2] <= mCCD_B[2].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[3] <= mCCD_B[3].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[4] <= mCCD_B[4].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[5] <= mCCD_B[5].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[6] <= mCCD_B[6].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[7] <= mCCD_B[7].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[8] <= mCCD_B[8].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[9] <= mCCD_B[9].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[10] <= mCCD_B[10].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[11] <= mCCD_B[11].DB_MAX_OUTPUT_PORT_TYPE
+oDVAL <= mDVAL.DB_MAX_OUTPUT_PORT_TYPE
+iX_Cont[0] => mDVAL.IN0
+iX_Cont[0] => Equal0.IN1
+iX_Cont[0] => Equal1.IN1
+iX_Cont[0] => Equal2.IN1
+iX_Cont[0] => Equal3.IN0
+iX_Cont[1] => ~NO_FANOUT~
+iX_Cont[2] => ~NO_FANOUT~
+iX_Cont[3] => ~NO_FANOUT~
+iX_Cont[4] => ~NO_FANOUT~
+iX_Cont[5] => ~NO_FANOUT~
+iX_Cont[6] => ~NO_FANOUT~
+iX_Cont[7] => ~NO_FANOUT~
+iX_Cont[8] => ~NO_FANOUT~
+iX_Cont[9] => ~NO_FANOUT~
+iX_Cont[10] => ~NO_FANOUT~
+iY_Cont[0] => mDVAL.IN1
+iY_Cont[0] => Equal0.IN0
+iY_Cont[0] => Equal1.IN0
+iY_Cont[0] => Equal2.IN0
+iY_Cont[0] => Equal3.IN1
+iY_Cont[1] => ~NO_FANOUT~
+iY_Cont[2] => ~NO_FANOUT~
+iY_Cont[3] => ~NO_FANOUT~
+iY_Cont[4] => ~NO_FANOUT~
+iY_Cont[5] => ~NO_FANOUT~
+iY_Cont[6] => ~NO_FANOUT~
+iY_Cont[7] => ~NO_FANOUT~
+iY_Cont[8] => ~NO_FANOUT~
+iY_Cont[9] => ~NO_FANOUT~
+iY_Cont[10] => ~NO_FANOUT~
+iDATA[0] => iDATA[0].IN1
+iDATA[1] => iDATA[1].IN1
+iDATA[2] => iDATA[2].IN1
+iDATA[3] => iDATA[3].IN1
+iDATA[4] => iDATA[4].IN1
+iDATA[5] => iDATA[5].IN1
+iDATA[6] => iDATA[6].IN1
+iDATA[7] => iDATA[7].IN1
+iDATA[8] => iDATA[8].IN1
+iDATA[9] => iDATA[9].IN1
+iDATA[10] => iDATA[10].IN1
+iDATA[11] => iDATA[11].IN1
+iDVAL => iDVAL.IN1
+iCLK => iCLK.IN1
+iRST => mDVAL.ACLR
+iRST => mDATAd_1[0].ACLR
+iRST => mDATAd_1[1].ACLR
+iRST => mDATAd_1[2].ACLR
+iRST => mDATAd_1[3].ACLR
+iRST => mDATAd_1[4].ACLR
+iRST => mDATAd_1[5].ACLR
+iRST => mDATAd_1[6].ACLR
+iRST => mDATAd_1[7].ACLR
+iRST => mDATAd_1[8].ACLR
+iRST => mDATAd_1[9].ACLR
+iRST => mDATAd_1[10].ACLR
+iRST => mDATAd_1[11].ACLR
+iRST => mDATAd_0[0].ACLR
+iRST => mDATAd_0[1].ACLR
+iRST => mDATAd_0[2].ACLR
+iRST => mDATAd_0[3].ACLR
+iRST => mDATAd_0[4].ACLR
+iRST => mDATAd_0[5].ACLR
+iRST => mDATAd_0[6].ACLR
+iRST => mDATAd_0[7].ACLR
+iRST => mDATAd_0[8].ACLR
+iRST => mDATAd_0[9].ACLR
+iRST => mDATAd_0[10].ACLR
+iRST => mDATAd_0[11].ACLR
+iRST => mCCD_B[0].ACLR
+iRST => mCCD_B[1].ACLR
+iRST => mCCD_B[2].ACLR
+iRST => mCCD_B[3].ACLR
+iRST => mCCD_B[4].ACLR
+iRST => mCCD_B[5].ACLR
+iRST => mCCD_B[6].ACLR
+iRST => mCCD_B[7].ACLR
+iRST => mCCD_B[8].ACLR
+iRST => mCCD_B[9].ACLR
+iRST => mCCD_B[10].ACLR
+iRST => mCCD_B[11].ACLR
+iRST => mCCD_G[1].ACLR
+iRST => mCCD_G[2].ACLR
+iRST => mCCD_G[3].ACLR
+iRST => mCCD_G[4].ACLR
+iRST => mCCD_G[5].ACLR
+iRST => mCCD_G[6].ACLR
+iRST => mCCD_G[7].ACLR
+iRST => mCCD_G[8].ACLR
+iRST => mCCD_G[9].ACLR
+iRST => mCCD_G[10].ACLR
+iRST => mCCD_G[11].ACLR
+iRST => mCCD_G[12].ACLR
+iRST => mCCD_R[0].ACLR
+iRST => mCCD_R[1].ACLR
+iRST => mCCD_R[2].ACLR
+iRST => mCCD_R[3].ACLR
+iRST => mCCD_R[4].ACLR
+iRST => mCCD_R[5].ACLR
+iRST => mCCD_R[6].ACLR
+iRST => mCCD_R[7].ACLR
+iRST => mCCD_R[8].ACLR
+iRST => mCCD_R[9].ACLR
+iRST => mCCD_R[10].ACLR
+iRST => mCCD_R[11].ACLR
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0
+clken => clken.IN1
+clock => clock.IN1
+shiftin[0] => shiftin[0].IN1
+shiftin[1] => shiftin[1].IN1
+shiftin[2] => shiftin[2].IN1
+shiftin[3] => shiftin[3].IN1
+shiftin[4] => shiftin[4].IN1
+shiftin[5] => shiftin[5].IN1
+shiftin[6] => shiftin[6].IN1
+shiftin[7] => shiftin[7].IN1
+shiftin[8] => shiftin[8].IN1
+shiftin[9] => shiftin[9].IN1
+shiftin[10] => shiftin[10].IN1
+shiftin[11] => shiftin[11].IN1
+shiftout[0] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[1] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[2] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[3] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[4] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[5] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[6] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[7] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[8] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[9] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[10] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[11] <= altshift_taps:altshift_taps_component.shiftout
+taps0x[0] <= altshift_taps:altshift_taps_component.taps
+taps0x[1] <= altshift_taps:altshift_taps_component.taps
+taps0x[2] <= altshift_taps:altshift_taps_component.taps
+taps0x[3] <= altshift_taps:altshift_taps_component.taps
+taps0x[4] <= altshift_taps:altshift_taps_component.taps
+taps0x[5] <= altshift_taps:altshift_taps_component.taps
+taps0x[6] <= altshift_taps:altshift_taps_component.taps
+taps0x[7] <= altshift_taps:altshift_taps_component.taps
+taps0x[8] <= altshift_taps:altshift_taps_component.taps
+taps0x[9] <= altshift_taps:altshift_taps_component.taps
+taps0x[10] <= altshift_taps:altshift_taps_component.taps
+taps0x[11] <= altshift_taps:altshift_taps_component.taps
+taps1x[0] <= altshift_taps:altshift_taps_component.taps
+taps1x[1] <= altshift_taps:altshift_taps_component.taps
+taps1x[2] <= altshift_taps:altshift_taps_component.taps
+taps1x[3] <= altshift_taps:altshift_taps_component.taps
+taps1x[4] <= altshift_taps:altshift_taps_component.taps
+taps1x[5] <= altshift_taps:altshift_taps_component.taps
+taps1x[6] <= altshift_taps:altshift_taps_component.taps
+taps1x[7] <= altshift_taps:altshift_taps_component.taps
+taps1x[8] <= altshift_taps:altshift_taps_component.taps
+taps1x[9] <= altshift_taps:altshift_taps_component.taps
+taps1x[10] <= altshift_taps:altshift_taps_component.taps
+taps1x[11] <= altshift_taps:altshift_taps_component.taps
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component
+shiftin[0] => shift_taps_rnn:auto_generated.shiftin[0]
+shiftin[1] => shift_taps_rnn:auto_generated.shiftin[1]
+shiftin[2] => shift_taps_rnn:auto_generated.shiftin[2]
+shiftin[3] => shift_taps_rnn:auto_generated.shiftin[3]
+shiftin[4] => shift_taps_rnn:auto_generated.shiftin[4]
+shiftin[5] => shift_taps_rnn:auto_generated.shiftin[5]
+shiftin[6] => shift_taps_rnn:auto_generated.shiftin[6]
+shiftin[7] => shift_taps_rnn:auto_generated.shiftin[7]
+shiftin[8] => shift_taps_rnn:auto_generated.shiftin[8]
+shiftin[9] => shift_taps_rnn:auto_generated.shiftin[9]
+shiftin[10] => shift_taps_rnn:auto_generated.shiftin[10]
+shiftin[11] => shift_taps_rnn:auto_generated.shiftin[11]
+clock => shift_taps_rnn:auto_generated.clock
+clken => shift_taps_rnn:auto_generated.clken
+shiftout[0] <= shift_taps_rnn:auto_generated.shiftout[0]
+shiftout[1] <= shift_taps_rnn:auto_generated.shiftout[1]
+shiftout[2] <= shift_taps_rnn:auto_generated.shiftout[2]
+shiftout[3] <= shift_taps_rnn:auto_generated.shiftout[3]
+shiftout[4] <= shift_taps_rnn:auto_generated.shiftout[4]
+shiftout[5] <= shift_taps_rnn:auto_generated.shiftout[5]
+shiftout[6] <= shift_taps_rnn:auto_generated.shiftout[6]
+shiftout[7] <= shift_taps_rnn:auto_generated.shiftout[7]
+shiftout[8] <= shift_taps_rnn:auto_generated.shiftout[8]
+shiftout[9] <= shift_taps_rnn:auto_generated.shiftout[9]
+shiftout[10] <= shift_taps_rnn:auto_generated.shiftout[10]
+shiftout[11] <= shift_taps_rnn:auto_generated.shiftout[11]
+taps[0] <= shift_taps_rnn:auto_generated.taps[0]
+taps[1] <= shift_taps_rnn:auto_generated.taps[1]
+taps[2] <= shift_taps_rnn:auto_generated.taps[2]
+taps[3] <= shift_taps_rnn:auto_generated.taps[3]
+taps[4] <= shift_taps_rnn:auto_generated.taps[4]
+taps[5] <= shift_taps_rnn:auto_generated.taps[5]
+taps[6] <= shift_taps_rnn:auto_generated.taps[6]
+taps[7] <= shift_taps_rnn:auto_generated.taps[7]
+taps[8] <= shift_taps_rnn:auto_generated.taps[8]
+taps[9] <= shift_taps_rnn:auto_generated.taps[9]
+taps[10] <= shift_taps_rnn:auto_generated.taps[10]
+taps[11] <= shift_taps_rnn:auto_generated.taps[11]
+taps[12] <= shift_taps_rnn:auto_generated.taps[12]
+taps[13] <= shift_taps_rnn:auto_generated.taps[13]
+taps[14] <= shift_taps_rnn:auto_generated.taps[14]
+taps[15] <= shift_taps_rnn:auto_generated.taps[15]
+taps[16] <= shift_taps_rnn:auto_generated.taps[16]
+taps[17] <= shift_taps_rnn:auto_generated.taps[17]
+taps[18] <= shift_taps_rnn:auto_generated.taps[18]
+taps[19] <= shift_taps_rnn:auto_generated.taps[19]
+taps[20] <= shift_taps_rnn:auto_generated.taps[20]
+taps[21] <= shift_taps_rnn:auto_generated.taps[21]
+taps[22] <= shift_taps_rnn:auto_generated.taps[22]
+taps[23] <= shift_taps_rnn:auto_generated.taps[23]
+aclr => ~NO_FANOUT~
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated
+clken => altsyncram_lp81:altsyncram2.clocken0
+clken => cntr_cuf:cntr1.clk_en
+clock => altsyncram_lp81:altsyncram2.clock0
+clock => cntr_cuf:cntr1.clock
+shiftin[0] => altsyncram_lp81:altsyncram2.data_a[0]
+shiftin[1] => altsyncram_lp81:altsyncram2.data_a[1]
+shiftin[2] => altsyncram_lp81:altsyncram2.data_a[2]
+shiftin[3] => altsyncram_lp81:altsyncram2.data_a[3]
+shiftin[4] => altsyncram_lp81:altsyncram2.data_a[4]
+shiftin[5] => altsyncram_lp81:altsyncram2.data_a[5]
+shiftin[6] => altsyncram_lp81:altsyncram2.data_a[6]
+shiftin[7] => altsyncram_lp81:altsyncram2.data_a[7]
+shiftin[8] => altsyncram_lp81:altsyncram2.data_a[8]
+shiftin[9] => altsyncram_lp81:altsyncram2.data_a[9]
+shiftin[10] => altsyncram_lp81:altsyncram2.data_a[10]
+shiftin[11] => altsyncram_lp81:altsyncram2.data_a[11]
+shiftout[0] <= altsyncram_lp81:altsyncram2.q_b[12]
+shiftout[1] <= altsyncram_lp81:altsyncram2.q_b[13]
+shiftout[2] <= altsyncram_lp81:altsyncram2.q_b[14]
+shiftout[3] <= altsyncram_lp81:altsyncram2.q_b[15]
+shiftout[4] <= altsyncram_lp81:altsyncram2.q_b[16]
+shiftout[5] <= altsyncram_lp81:altsyncram2.q_b[17]
+shiftout[6] <= altsyncram_lp81:altsyncram2.q_b[18]
+shiftout[7] <= altsyncram_lp81:altsyncram2.q_b[19]
+shiftout[8] <= altsyncram_lp81:altsyncram2.q_b[20]
+shiftout[9] <= altsyncram_lp81:altsyncram2.q_b[21]
+shiftout[10] <= altsyncram_lp81:altsyncram2.q_b[22]
+shiftout[11] <= altsyncram_lp81:altsyncram2.q_b[23]
+taps[0] <= altsyncram_lp81:altsyncram2.q_b[0]
+taps[1] <= altsyncram_lp81:altsyncram2.q_b[1]
+taps[2] <= altsyncram_lp81:altsyncram2.q_b[2]
+taps[3] <= altsyncram_lp81:altsyncram2.q_b[3]
+taps[4] <= altsyncram_lp81:altsyncram2.q_b[4]
+taps[5] <= altsyncram_lp81:altsyncram2.q_b[5]
+taps[6] <= altsyncram_lp81:altsyncram2.q_b[6]
+taps[7] <= altsyncram_lp81:altsyncram2.q_b[7]
+taps[8] <= altsyncram_lp81:altsyncram2.q_b[8]
+taps[9] <= altsyncram_lp81:altsyncram2.q_b[9]
+taps[10] <= altsyncram_lp81:altsyncram2.q_b[10]
+taps[11] <= altsyncram_lp81:altsyncram2.q_b[11]
+taps[12] <= altsyncram_lp81:altsyncram2.q_b[12]
+taps[13] <= altsyncram_lp81:altsyncram2.q_b[13]
+taps[14] <= altsyncram_lp81:altsyncram2.q_b[14]
+taps[15] <= altsyncram_lp81:altsyncram2.q_b[15]
+taps[16] <= altsyncram_lp81:altsyncram2.q_b[16]
+taps[17] <= altsyncram_lp81:altsyncram2.q_b[17]
+taps[18] <= altsyncram_lp81:altsyncram2.q_b[18]
+taps[19] <= altsyncram_lp81:altsyncram2.q_b[19]
+taps[20] <= altsyncram_lp81:altsyncram2.q_b[20]
+taps[21] <= altsyncram_lp81:altsyncram2.q_b[21]
+taps[22] <= altsyncram_lp81:altsyncram2.q_b[22]
+taps[23] <= altsyncram_lp81:altsyncram2.q_b[23]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2
+address_a[0] => ram_block3a0.PORTAADDR
+address_a[0] => ram_block3a1.PORTAADDR
+address_a[0] => ram_block3a2.PORTAADDR
+address_a[0] => ram_block3a3.PORTAADDR
+address_a[0] => ram_block3a4.PORTAADDR
+address_a[0] => ram_block3a5.PORTAADDR
+address_a[0] => ram_block3a6.PORTAADDR
+address_a[0] => ram_block3a7.PORTAADDR
+address_a[0] => ram_block3a8.PORTAADDR
+address_a[0] => ram_block3a9.PORTAADDR
+address_a[0] => ram_block3a10.PORTAADDR
+address_a[0] => ram_block3a11.PORTAADDR
+address_a[0] => ram_block3a12.PORTAADDR
+address_a[0] => ram_block3a13.PORTAADDR
+address_a[0] => ram_block3a14.PORTAADDR
+address_a[0] => ram_block3a15.PORTAADDR
+address_a[0] => ram_block3a16.PORTAADDR
+address_a[0] => ram_block3a17.PORTAADDR
+address_a[0] => ram_block3a18.PORTAADDR
+address_a[0] => ram_block3a19.PORTAADDR
+address_a[0] => ram_block3a20.PORTAADDR
+address_a[0] => ram_block3a21.PORTAADDR
+address_a[0] => ram_block3a22.PORTAADDR
+address_a[0] => ram_block3a23.PORTAADDR
+address_a[1] => ram_block3a0.PORTAADDR1
+address_a[1] => ram_block3a1.PORTAADDR1
+address_a[1] => ram_block3a2.PORTAADDR1
+address_a[1] => ram_block3a3.PORTAADDR1
+address_a[1] => ram_block3a4.PORTAADDR1
+address_a[1] => ram_block3a5.PORTAADDR1
+address_a[1] => ram_block3a6.PORTAADDR1
+address_a[1] => ram_block3a7.PORTAADDR1
+address_a[1] => ram_block3a8.PORTAADDR1
+address_a[1] => ram_block3a9.PORTAADDR1
+address_a[1] => ram_block3a10.PORTAADDR1
+address_a[1] => ram_block3a11.PORTAADDR1
+address_a[1] => ram_block3a12.PORTAADDR1
+address_a[1] => ram_block3a13.PORTAADDR1
+address_a[1] => ram_block3a14.PORTAADDR1
+address_a[1] => ram_block3a15.PORTAADDR1
+address_a[1] => ram_block3a16.PORTAADDR1
+address_a[1] => ram_block3a17.PORTAADDR1
+address_a[1] => ram_block3a18.PORTAADDR1
+address_a[1] => ram_block3a19.PORTAADDR1
+address_a[1] => ram_block3a20.PORTAADDR1
+address_a[1] => ram_block3a21.PORTAADDR1
+address_a[1] => ram_block3a22.PORTAADDR1
+address_a[1] => ram_block3a23.PORTAADDR1
+address_a[2] => ram_block3a0.PORTAADDR2
+address_a[2] => ram_block3a1.PORTAADDR2
+address_a[2] => ram_block3a2.PORTAADDR2
+address_a[2] => ram_block3a3.PORTAADDR2
+address_a[2] => ram_block3a4.PORTAADDR2
+address_a[2] => ram_block3a5.PORTAADDR2
+address_a[2] => ram_block3a6.PORTAADDR2
+address_a[2] => ram_block3a7.PORTAADDR2
+address_a[2] => ram_block3a8.PORTAADDR2
+address_a[2] => ram_block3a9.PORTAADDR2
+address_a[2] => ram_block3a10.PORTAADDR2
+address_a[2] => ram_block3a11.PORTAADDR2
+address_a[2] => ram_block3a12.PORTAADDR2
+address_a[2] => ram_block3a13.PORTAADDR2
+address_a[2] => ram_block3a14.PORTAADDR2
+address_a[2] => ram_block3a15.PORTAADDR2
+address_a[2] => ram_block3a16.PORTAADDR2
+address_a[2] => ram_block3a17.PORTAADDR2
+address_a[2] => ram_block3a18.PORTAADDR2
+address_a[2] => ram_block3a19.PORTAADDR2
+address_a[2] => ram_block3a20.PORTAADDR2
+address_a[2] => ram_block3a21.PORTAADDR2
+address_a[2] => ram_block3a22.PORTAADDR2
+address_a[2] => ram_block3a23.PORTAADDR2
+address_a[3] => ram_block3a0.PORTAADDR3
+address_a[3] => ram_block3a1.PORTAADDR3
+address_a[3] => ram_block3a2.PORTAADDR3
+address_a[3] => ram_block3a3.PORTAADDR3
+address_a[3] => ram_block3a4.PORTAADDR3
+address_a[3] => ram_block3a5.PORTAADDR3
+address_a[3] => ram_block3a6.PORTAADDR3
+address_a[3] => ram_block3a7.PORTAADDR3
+address_a[3] => ram_block3a8.PORTAADDR3
+address_a[3] => ram_block3a9.PORTAADDR3
+address_a[3] => ram_block3a10.PORTAADDR3
+address_a[3] => ram_block3a11.PORTAADDR3
+address_a[3] => ram_block3a12.PORTAADDR3
+address_a[3] => ram_block3a13.PORTAADDR3
+address_a[3] => ram_block3a14.PORTAADDR3
+address_a[3] => ram_block3a15.PORTAADDR3
+address_a[3] => ram_block3a16.PORTAADDR3
+address_a[3] => ram_block3a17.PORTAADDR3
+address_a[3] => ram_block3a18.PORTAADDR3
+address_a[3] => ram_block3a19.PORTAADDR3
+address_a[3] => ram_block3a20.PORTAADDR3
+address_a[3] => ram_block3a21.PORTAADDR3
+address_a[3] => ram_block3a22.PORTAADDR3
+address_a[3] => ram_block3a23.PORTAADDR3
+address_a[4] => ram_block3a0.PORTAADDR4
+address_a[4] => ram_block3a1.PORTAADDR4
+address_a[4] => ram_block3a2.PORTAADDR4
+address_a[4] => ram_block3a3.PORTAADDR4
+address_a[4] => ram_block3a4.PORTAADDR4
+address_a[4] => ram_block3a5.PORTAADDR4
+address_a[4] => ram_block3a6.PORTAADDR4
+address_a[4] => ram_block3a7.PORTAADDR4
+address_a[4] => ram_block3a8.PORTAADDR4
+address_a[4] => ram_block3a9.PORTAADDR4
+address_a[4] => ram_block3a10.PORTAADDR4
+address_a[4] => ram_block3a11.PORTAADDR4
+address_a[4] => ram_block3a12.PORTAADDR4
+address_a[4] => ram_block3a13.PORTAADDR4
+address_a[4] => ram_block3a14.PORTAADDR4
+address_a[4] => ram_block3a15.PORTAADDR4
+address_a[4] => ram_block3a16.PORTAADDR4
+address_a[4] => ram_block3a17.PORTAADDR4
+address_a[4] => ram_block3a18.PORTAADDR4
+address_a[4] => ram_block3a19.PORTAADDR4
+address_a[4] => ram_block3a20.PORTAADDR4
+address_a[4] => ram_block3a21.PORTAADDR4
+address_a[4] => ram_block3a22.PORTAADDR4
+address_a[4] => ram_block3a23.PORTAADDR4
+address_a[5] => ram_block3a0.PORTAADDR5
+address_a[5] => ram_block3a1.PORTAADDR5
+address_a[5] => ram_block3a2.PORTAADDR5
+address_a[5] => ram_block3a3.PORTAADDR5
+address_a[5] => ram_block3a4.PORTAADDR5
+address_a[5] => ram_block3a5.PORTAADDR5
+address_a[5] => ram_block3a6.PORTAADDR5
+address_a[5] => ram_block3a7.PORTAADDR5
+address_a[5] => ram_block3a8.PORTAADDR5
+address_a[5] => ram_block3a9.PORTAADDR5
+address_a[5] => ram_block3a10.PORTAADDR5
+address_a[5] => ram_block3a11.PORTAADDR5
+address_a[5] => ram_block3a12.PORTAADDR5
+address_a[5] => ram_block3a13.PORTAADDR5
+address_a[5] => ram_block3a14.PORTAADDR5
+address_a[5] => ram_block3a15.PORTAADDR5
+address_a[5] => ram_block3a16.PORTAADDR5
+address_a[5] => ram_block3a17.PORTAADDR5
+address_a[5] => ram_block3a18.PORTAADDR5
+address_a[5] => ram_block3a19.PORTAADDR5
+address_a[5] => ram_block3a20.PORTAADDR5
+address_a[5] => ram_block3a21.PORTAADDR5
+address_a[5] => ram_block3a22.PORTAADDR5
+address_a[5] => ram_block3a23.PORTAADDR5
+address_a[6] => ram_block3a0.PORTAADDR6
+address_a[6] => ram_block3a1.PORTAADDR6
+address_a[6] => ram_block3a2.PORTAADDR6
+address_a[6] => ram_block3a3.PORTAADDR6
+address_a[6] => ram_block3a4.PORTAADDR6
+address_a[6] => ram_block3a5.PORTAADDR6
+address_a[6] => ram_block3a6.PORTAADDR6
+address_a[6] => ram_block3a7.PORTAADDR6
+address_a[6] => ram_block3a8.PORTAADDR6
+address_a[6] => ram_block3a9.PORTAADDR6
+address_a[6] => ram_block3a10.PORTAADDR6
+address_a[6] => ram_block3a11.PORTAADDR6
+address_a[6] => ram_block3a12.PORTAADDR6
+address_a[6] => ram_block3a13.PORTAADDR6
+address_a[6] => ram_block3a14.PORTAADDR6
+address_a[6] => ram_block3a15.PORTAADDR6
+address_a[6] => ram_block3a16.PORTAADDR6
+address_a[6] => ram_block3a17.PORTAADDR6
+address_a[6] => ram_block3a18.PORTAADDR6
+address_a[6] => ram_block3a19.PORTAADDR6
+address_a[6] => ram_block3a20.PORTAADDR6
+address_a[6] => ram_block3a21.PORTAADDR6
+address_a[6] => ram_block3a22.PORTAADDR6
+address_a[6] => ram_block3a23.PORTAADDR6
+address_a[7] => ram_block3a0.PORTAADDR7
+address_a[7] => ram_block3a1.PORTAADDR7
+address_a[7] => ram_block3a2.PORTAADDR7
+address_a[7] => ram_block3a3.PORTAADDR7
+address_a[7] => ram_block3a4.PORTAADDR7
+address_a[7] => ram_block3a5.PORTAADDR7
+address_a[7] => ram_block3a6.PORTAADDR7
+address_a[7] => ram_block3a7.PORTAADDR7
+address_a[7] => ram_block3a8.PORTAADDR7
+address_a[7] => ram_block3a9.PORTAADDR7
+address_a[7] => ram_block3a10.PORTAADDR7
+address_a[7] => ram_block3a11.PORTAADDR7
+address_a[7] => ram_block3a12.PORTAADDR7
+address_a[7] => ram_block3a13.PORTAADDR7
+address_a[7] => ram_block3a14.PORTAADDR7
+address_a[7] => ram_block3a15.PORTAADDR7
+address_a[7] => ram_block3a16.PORTAADDR7
+address_a[7] => ram_block3a17.PORTAADDR7
+address_a[7] => ram_block3a18.PORTAADDR7
+address_a[7] => ram_block3a19.PORTAADDR7
+address_a[7] => ram_block3a20.PORTAADDR7
+address_a[7] => ram_block3a21.PORTAADDR7
+address_a[7] => ram_block3a22.PORTAADDR7
+address_a[7] => ram_block3a23.PORTAADDR7
+address_a[8] => ram_block3a0.PORTAADDR8
+address_a[8] => ram_block3a1.PORTAADDR8
+address_a[8] => ram_block3a2.PORTAADDR8
+address_a[8] => ram_block3a3.PORTAADDR8
+address_a[8] => ram_block3a4.PORTAADDR8
+address_a[8] => ram_block3a5.PORTAADDR8
+address_a[8] => ram_block3a6.PORTAADDR8
+address_a[8] => ram_block3a7.PORTAADDR8
+address_a[8] => ram_block3a8.PORTAADDR8
+address_a[8] => ram_block3a9.PORTAADDR8
+address_a[8] => ram_block3a10.PORTAADDR8
+address_a[8] => ram_block3a11.PORTAADDR8
+address_a[8] => ram_block3a12.PORTAADDR8
+address_a[8] => ram_block3a13.PORTAADDR8
+address_a[8] => ram_block3a14.PORTAADDR8
+address_a[8] => ram_block3a15.PORTAADDR8
+address_a[8] => ram_block3a16.PORTAADDR8
+address_a[8] => ram_block3a17.PORTAADDR8
+address_a[8] => ram_block3a18.PORTAADDR8
+address_a[8] => ram_block3a19.PORTAADDR8
+address_a[8] => ram_block3a20.PORTAADDR8
+address_a[8] => ram_block3a21.PORTAADDR8
+address_a[8] => ram_block3a22.PORTAADDR8
+address_a[8] => ram_block3a23.PORTAADDR8
+address_a[9] => ram_block3a0.PORTAADDR9
+address_a[9] => ram_block3a1.PORTAADDR9
+address_a[9] => ram_block3a2.PORTAADDR9
+address_a[9] => ram_block3a3.PORTAADDR9
+address_a[9] => ram_block3a4.PORTAADDR9
+address_a[9] => ram_block3a5.PORTAADDR9
+address_a[9] => ram_block3a6.PORTAADDR9
+address_a[9] => ram_block3a7.PORTAADDR9
+address_a[9] => ram_block3a8.PORTAADDR9
+address_a[9] => ram_block3a9.PORTAADDR9
+address_a[9] => ram_block3a10.PORTAADDR9
+address_a[9] => ram_block3a11.PORTAADDR9
+address_a[9] => ram_block3a12.PORTAADDR9
+address_a[9] => ram_block3a13.PORTAADDR9
+address_a[9] => ram_block3a14.PORTAADDR9
+address_a[9] => ram_block3a15.PORTAADDR9
+address_a[9] => ram_block3a16.PORTAADDR9
+address_a[9] => ram_block3a17.PORTAADDR9
+address_a[9] => ram_block3a18.PORTAADDR9
+address_a[9] => ram_block3a19.PORTAADDR9
+address_a[9] => ram_block3a20.PORTAADDR9
+address_a[9] => ram_block3a21.PORTAADDR9
+address_a[9] => ram_block3a22.PORTAADDR9
+address_a[9] => ram_block3a23.PORTAADDR9
+address_a[10] => ram_block3a0.PORTAADDR10
+address_a[10] => ram_block3a1.PORTAADDR10
+address_a[10] => ram_block3a2.PORTAADDR10
+address_a[10] => ram_block3a3.PORTAADDR10
+address_a[10] => ram_block3a4.PORTAADDR10
+address_a[10] => ram_block3a5.PORTAADDR10
+address_a[10] => ram_block3a6.PORTAADDR10
+address_a[10] => ram_block3a7.PORTAADDR10
+address_a[10] => ram_block3a8.PORTAADDR10
+address_a[10] => ram_block3a9.PORTAADDR10
+address_a[10] => ram_block3a10.PORTAADDR10
+address_a[10] => ram_block3a11.PORTAADDR10
+address_a[10] => ram_block3a12.PORTAADDR10
+address_a[10] => ram_block3a13.PORTAADDR10
+address_a[10] => ram_block3a14.PORTAADDR10
+address_a[10] => ram_block3a15.PORTAADDR10
+address_a[10] => ram_block3a16.PORTAADDR10
+address_a[10] => ram_block3a17.PORTAADDR10
+address_a[10] => ram_block3a18.PORTAADDR10
+address_a[10] => ram_block3a19.PORTAADDR10
+address_a[10] => ram_block3a20.PORTAADDR10
+address_a[10] => ram_block3a21.PORTAADDR10
+address_a[10] => ram_block3a22.PORTAADDR10
+address_a[10] => ram_block3a23.PORTAADDR10
+address_b[0] => ram_block3a0.PORTBADDR
+address_b[0] => ram_block3a1.PORTBADDR
+address_b[0] => ram_block3a2.PORTBADDR
+address_b[0] => ram_block3a3.PORTBADDR
+address_b[0] => ram_block3a4.PORTBADDR
+address_b[0] => ram_block3a5.PORTBADDR
+address_b[0] => ram_block3a6.PORTBADDR
+address_b[0] => ram_block3a7.PORTBADDR
+address_b[0] => ram_block3a8.PORTBADDR
+address_b[0] => ram_block3a9.PORTBADDR
+address_b[0] => ram_block3a10.PORTBADDR
+address_b[0] => ram_block3a11.PORTBADDR
+address_b[0] => ram_block3a12.PORTBADDR
+address_b[0] => ram_block3a13.PORTBADDR
+address_b[0] => ram_block3a14.PORTBADDR
+address_b[0] => ram_block3a15.PORTBADDR
+address_b[0] => ram_block3a16.PORTBADDR
+address_b[0] => ram_block3a17.PORTBADDR
+address_b[0] => ram_block3a18.PORTBADDR
+address_b[0] => ram_block3a19.PORTBADDR
+address_b[0] => ram_block3a20.PORTBADDR
+address_b[0] => ram_block3a21.PORTBADDR
+address_b[0] => ram_block3a22.PORTBADDR
+address_b[0] => ram_block3a23.PORTBADDR
+address_b[1] => ram_block3a0.PORTBADDR1
+address_b[1] => ram_block3a1.PORTBADDR1
+address_b[1] => ram_block3a2.PORTBADDR1
+address_b[1] => ram_block3a3.PORTBADDR1
+address_b[1] => ram_block3a4.PORTBADDR1
+address_b[1] => ram_block3a5.PORTBADDR1
+address_b[1] => ram_block3a6.PORTBADDR1
+address_b[1] => ram_block3a7.PORTBADDR1
+address_b[1] => ram_block3a8.PORTBADDR1
+address_b[1] => ram_block3a9.PORTBADDR1
+address_b[1] => ram_block3a10.PORTBADDR1
+address_b[1] => ram_block3a11.PORTBADDR1
+address_b[1] => ram_block3a12.PORTBADDR1
+address_b[1] => ram_block3a13.PORTBADDR1
+address_b[1] => ram_block3a14.PORTBADDR1
+address_b[1] => ram_block3a15.PORTBADDR1
+address_b[1] => ram_block3a16.PORTBADDR1
+address_b[1] => ram_block3a17.PORTBADDR1
+address_b[1] => ram_block3a18.PORTBADDR1
+address_b[1] => ram_block3a19.PORTBADDR1
+address_b[1] => ram_block3a20.PORTBADDR1
+address_b[1] => ram_block3a21.PORTBADDR1
+address_b[1] => ram_block3a22.PORTBADDR1
+address_b[1] => ram_block3a23.PORTBADDR1
+address_b[2] => ram_block3a0.PORTBADDR2
+address_b[2] => ram_block3a1.PORTBADDR2
+address_b[2] => ram_block3a2.PORTBADDR2
+address_b[2] => ram_block3a3.PORTBADDR2
+address_b[2] => ram_block3a4.PORTBADDR2
+address_b[2] => ram_block3a5.PORTBADDR2
+address_b[2] => ram_block3a6.PORTBADDR2
+address_b[2] => ram_block3a7.PORTBADDR2
+address_b[2] => ram_block3a8.PORTBADDR2
+address_b[2] => ram_block3a9.PORTBADDR2
+address_b[2] => ram_block3a10.PORTBADDR2
+address_b[2] => ram_block3a11.PORTBADDR2
+address_b[2] => ram_block3a12.PORTBADDR2
+address_b[2] => ram_block3a13.PORTBADDR2
+address_b[2] => ram_block3a14.PORTBADDR2
+address_b[2] => ram_block3a15.PORTBADDR2
+address_b[2] => ram_block3a16.PORTBADDR2
+address_b[2] => ram_block3a17.PORTBADDR2
+address_b[2] => ram_block3a18.PORTBADDR2
+address_b[2] => ram_block3a19.PORTBADDR2
+address_b[2] => ram_block3a20.PORTBADDR2
+address_b[2] => ram_block3a21.PORTBADDR2
+address_b[2] => ram_block3a22.PORTBADDR2
+address_b[2] => ram_block3a23.PORTBADDR2
+address_b[3] => ram_block3a0.PORTBADDR3
+address_b[3] => ram_block3a1.PORTBADDR3
+address_b[3] => ram_block3a2.PORTBADDR3
+address_b[3] => ram_block3a3.PORTBADDR3
+address_b[3] => ram_block3a4.PORTBADDR3
+address_b[3] => ram_block3a5.PORTBADDR3
+address_b[3] => ram_block3a6.PORTBADDR3
+address_b[3] => ram_block3a7.PORTBADDR3
+address_b[3] => ram_block3a8.PORTBADDR3
+address_b[3] => ram_block3a9.PORTBADDR3
+address_b[3] => ram_block3a10.PORTBADDR3
+address_b[3] => ram_block3a11.PORTBADDR3
+address_b[3] => ram_block3a12.PORTBADDR3
+address_b[3] => ram_block3a13.PORTBADDR3
+address_b[3] => ram_block3a14.PORTBADDR3
+address_b[3] => ram_block3a15.PORTBADDR3
+address_b[3] => ram_block3a16.PORTBADDR3
+address_b[3] => ram_block3a17.PORTBADDR3
+address_b[3] => ram_block3a18.PORTBADDR3
+address_b[3] => ram_block3a19.PORTBADDR3
+address_b[3] => ram_block3a20.PORTBADDR3
+address_b[3] => ram_block3a21.PORTBADDR3
+address_b[3] => ram_block3a22.PORTBADDR3
+address_b[3] => ram_block3a23.PORTBADDR3
+address_b[4] => ram_block3a0.PORTBADDR4
+address_b[4] => ram_block3a1.PORTBADDR4
+address_b[4] => ram_block3a2.PORTBADDR4
+address_b[4] => ram_block3a3.PORTBADDR4
+address_b[4] => ram_block3a4.PORTBADDR4
+address_b[4] => ram_block3a5.PORTBADDR4
+address_b[4] => ram_block3a6.PORTBADDR4
+address_b[4] => ram_block3a7.PORTBADDR4
+address_b[4] => ram_block3a8.PORTBADDR4
+address_b[4] => ram_block3a9.PORTBADDR4
+address_b[4] => ram_block3a10.PORTBADDR4
+address_b[4] => ram_block3a11.PORTBADDR4
+address_b[4] => ram_block3a12.PORTBADDR4
+address_b[4] => ram_block3a13.PORTBADDR4
+address_b[4] => ram_block3a14.PORTBADDR4
+address_b[4] => ram_block3a15.PORTBADDR4
+address_b[4] => ram_block3a16.PORTBADDR4
+address_b[4] => ram_block3a17.PORTBADDR4
+address_b[4] => ram_block3a18.PORTBADDR4
+address_b[4] => ram_block3a19.PORTBADDR4
+address_b[4] => ram_block3a20.PORTBADDR4
+address_b[4] => ram_block3a21.PORTBADDR4
+address_b[4] => ram_block3a22.PORTBADDR4
+address_b[4] => ram_block3a23.PORTBADDR4
+address_b[5] => ram_block3a0.PORTBADDR5
+address_b[5] => ram_block3a1.PORTBADDR5
+address_b[5] => ram_block3a2.PORTBADDR5
+address_b[5] => ram_block3a3.PORTBADDR5
+address_b[5] => ram_block3a4.PORTBADDR5
+address_b[5] => ram_block3a5.PORTBADDR5
+address_b[5] => ram_block3a6.PORTBADDR5
+address_b[5] => ram_block3a7.PORTBADDR5
+address_b[5] => ram_block3a8.PORTBADDR5
+address_b[5] => ram_block3a9.PORTBADDR5
+address_b[5] => ram_block3a10.PORTBADDR5
+address_b[5] => ram_block3a11.PORTBADDR5
+address_b[5] => ram_block3a12.PORTBADDR5
+address_b[5] => ram_block3a13.PORTBADDR5
+address_b[5] => ram_block3a14.PORTBADDR5
+address_b[5] => ram_block3a15.PORTBADDR5
+address_b[5] => ram_block3a16.PORTBADDR5
+address_b[5] => ram_block3a17.PORTBADDR5
+address_b[5] => ram_block3a18.PORTBADDR5
+address_b[5] => ram_block3a19.PORTBADDR5
+address_b[5] => ram_block3a20.PORTBADDR5
+address_b[5] => ram_block3a21.PORTBADDR5
+address_b[5] => ram_block3a22.PORTBADDR5
+address_b[5] => ram_block3a23.PORTBADDR5
+address_b[6] => ram_block3a0.PORTBADDR6
+address_b[6] => ram_block3a1.PORTBADDR6
+address_b[6] => ram_block3a2.PORTBADDR6
+address_b[6] => ram_block3a3.PORTBADDR6
+address_b[6] => ram_block3a4.PORTBADDR6
+address_b[6] => ram_block3a5.PORTBADDR6
+address_b[6] => ram_block3a6.PORTBADDR6
+address_b[6] => ram_block3a7.PORTBADDR6
+address_b[6] => ram_block3a8.PORTBADDR6
+address_b[6] => ram_block3a9.PORTBADDR6
+address_b[6] => ram_block3a10.PORTBADDR6
+address_b[6] => ram_block3a11.PORTBADDR6
+address_b[6] => ram_block3a12.PORTBADDR6
+address_b[6] => ram_block3a13.PORTBADDR6
+address_b[6] => ram_block3a14.PORTBADDR6
+address_b[6] => ram_block3a15.PORTBADDR6
+address_b[6] => ram_block3a16.PORTBADDR6
+address_b[6] => ram_block3a17.PORTBADDR6
+address_b[6] => ram_block3a18.PORTBADDR6
+address_b[6] => ram_block3a19.PORTBADDR6
+address_b[6] => ram_block3a20.PORTBADDR6
+address_b[6] => ram_block3a21.PORTBADDR6
+address_b[6] => ram_block3a22.PORTBADDR6
+address_b[6] => ram_block3a23.PORTBADDR6
+address_b[7] => ram_block3a0.PORTBADDR7
+address_b[7] => ram_block3a1.PORTBADDR7
+address_b[7] => ram_block3a2.PORTBADDR7
+address_b[7] => ram_block3a3.PORTBADDR7
+address_b[7] => ram_block3a4.PORTBADDR7
+address_b[7] => ram_block3a5.PORTBADDR7
+address_b[7] => ram_block3a6.PORTBADDR7
+address_b[7] => ram_block3a7.PORTBADDR7
+address_b[7] => ram_block3a8.PORTBADDR7
+address_b[7] => ram_block3a9.PORTBADDR7
+address_b[7] => ram_block3a10.PORTBADDR7
+address_b[7] => ram_block3a11.PORTBADDR7
+address_b[7] => ram_block3a12.PORTBADDR7
+address_b[7] => ram_block3a13.PORTBADDR7
+address_b[7] => ram_block3a14.PORTBADDR7
+address_b[7] => ram_block3a15.PORTBADDR7
+address_b[7] => ram_block3a16.PORTBADDR7
+address_b[7] => ram_block3a17.PORTBADDR7
+address_b[7] => ram_block3a18.PORTBADDR7
+address_b[7] => ram_block3a19.PORTBADDR7
+address_b[7] => ram_block3a20.PORTBADDR7
+address_b[7] => ram_block3a21.PORTBADDR7
+address_b[7] => ram_block3a22.PORTBADDR7
+address_b[7] => ram_block3a23.PORTBADDR7
+address_b[8] => ram_block3a0.PORTBADDR8
+address_b[8] => ram_block3a1.PORTBADDR8
+address_b[8] => ram_block3a2.PORTBADDR8
+address_b[8] => ram_block3a3.PORTBADDR8
+address_b[8] => ram_block3a4.PORTBADDR8
+address_b[8] => ram_block3a5.PORTBADDR8
+address_b[8] => ram_block3a6.PORTBADDR8
+address_b[8] => ram_block3a7.PORTBADDR8
+address_b[8] => ram_block3a8.PORTBADDR8
+address_b[8] => ram_block3a9.PORTBADDR8
+address_b[8] => ram_block3a10.PORTBADDR8
+address_b[8] => ram_block3a11.PORTBADDR8
+address_b[8] => ram_block3a12.PORTBADDR8
+address_b[8] => ram_block3a13.PORTBADDR8
+address_b[8] => ram_block3a14.PORTBADDR8
+address_b[8] => ram_block3a15.PORTBADDR8
+address_b[8] => ram_block3a16.PORTBADDR8
+address_b[8] => ram_block3a17.PORTBADDR8
+address_b[8] => ram_block3a18.PORTBADDR8
+address_b[8] => ram_block3a19.PORTBADDR8
+address_b[8] => ram_block3a20.PORTBADDR8
+address_b[8] => ram_block3a21.PORTBADDR8
+address_b[8] => ram_block3a22.PORTBADDR8
+address_b[8] => ram_block3a23.PORTBADDR8
+address_b[9] => ram_block3a0.PORTBADDR9
+address_b[9] => ram_block3a1.PORTBADDR9
+address_b[9] => ram_block3a2.PORTBADDR9
+address_b[9] => ram_block3a3.PORTBADDR9
+address_b[9] => ram_block3a4.PORTBADDR9
+address_b[9] => ram_block3a5.PORTBADDR9
+address_b[9] => ram_block3a6.PORTBADDR9
+address_b[9] => ram_block3a7.PORTBADDR9
+address_b[9] => ram_block3a8.PORTBADDR9
+address_b[9] => ram_block3a9.PORTBADDR9
+address_b[9] => ram_block3a10.PORTBADDR9
+address_b[9] => ram_block3a11.PORTBADDR9
+address_b[9] => ram_block3a12.PORTBADDR9
+address_b[9] => ram_block3a13.PORTBADDR9
+address_b[9] => ram_block3a14.PORTBADDR9
+address_b[9] => ram_block3a15.PORTBADDR9
+address_b[9] => ram_block3a16.PORTBADDR9
+address_b[9] => ram_block3a17.PORTBADDR9
+address_b[9] => ram_block3a18.PORTBADDR9
+address_b[9] => ram_block3a19.PORTBADDR9
+address_b[9] => ram_block3a20.PORTBADDR9
+address_b[9] => ram_block3a21.PORTBADDR9
+address_b[9] => ram_block3a22.PORTBADDR9
+address_b[9] => ram_block3a23.PORTBADDR9
+address_b[10] => ram_block3a0.PORTBADDR10
+address_b[10] => ram_block3a1.PORTBADDR10
+address_b[10] => ram_block3a2.PORTBADDR10
+address_b[10] => ram_block3a3.PORTBADDR10
+address_b[10] => ram_block3a4.PORTBADDR10
+address_b[10] => ram_block3a5.PORTBADDR10
+address_b[10] => ram_block3a6.PORTBADDR10
+address_b[10] => ram_block3a7.PORTBADDR10
+address_b[10] => ram_block3a8.PORTBADDR10
+address_b[10] => ram_block3a9.PORTBADDR10
+address_b[10] => ram_block3a10.PORTBADDR10
+address_b[10] => ram_block3a11.PORTBADDR10
+address_b[10] => ram_block3a12.PORTBADDR10
+address_b[10] => ram_block3a13.PORTBADDR10
+address_b[10] => ram_block3a14.PORTBADDR10
+address_b[10] => ram_block3a15.PORTBADDR10
+address_b[10] => ram_block3a16.PORTBADDR10
+address_b[10] => ram_block3a17.PORTBADDR10
+address_b[10] => ram_block3a18.PORTBADDR10
+address_b[10] => ram_block3a19.PORTBADDR10
+address_b[10] => ram_block3a20.PORTBADDR10
+address_b[10] => ram_block3a21.PORTBADDR10
+address_b[10] => ram_block3a22.PORTBADDR10
+address_b[10] => ram_block3a23.PORTBADDR10
+clock0 => ram_block3a0.CLK0
+clock0 => ram_block3a1.CLK0
+clock0 => ram_block3a2.CLK0
+clock0 => ram_block3a3.CLK0
+clock0 => ram_block3a4.CLK0
+clock0 => ram_block3a5.CLK0
+clock0 => ram_block3a6.CLK0
+clock0 => ram_block3a7.CLK0
+clock0 => ram_block3a8.CLK0
+clock0 => ram_block3a9.CLK0
+clock0 => ram_block3a10.CLK0
+clock0 => ram_block3a11.CLK0
+clock0 => ram_block3a12.CLK0
+clock0 => ram_block3a13.CLK0
+clock0 => ram_block3a14.CLK0
+clock0 => ram_block3a15.CLK0
+clock0 => ram_block3a16.CLK0
+clock0 => ram_block3a17.CLK0
+clock0 => ram_block3a18.CLK0
+clock0 => ram_block3a19.CLK0
+clock0 => ram_block3a20.CLK0
+clock0 => ram_block3a21.CLK0
+clock0 => ram_block3a22.CLK0
+clock0 => ram_block3a23.CLK0
+clocken0 => ram_block3a0.ENA0
+clocken0 => ram_block3a1.ENA0
+clocken0 => ram_block3a2.ENA0
+clocken0 => ram_block3a3.ENA0
+clocken0 => ram_block3a4.ENA0
+clocken0 => ram_block3a5.ENA0
+clocken0 => ram_block3a6.ENA0
+clocken0 => ram_block3a7.ENA0
+clocken0 => ram_block3a8.ENA0
+clocken0 => ram_block3a9.ENA0
+clocken0 => ram_block3a10.ENA0
+clocken0 => ram_block3a11.ENA0
+clocken0 => ram_block3a12.ENA0
+clocken0 => ram_block3a13.ENA0
+clocken0 => ram_block3a14.ENA0
+clocken0 => ram_block3a15.ENA0
+clocken0 => ram_block3a16.ENA0
+clocken0 => ram_block3a17.ENA0
+clocken0 => ram_block3a18.ENA0
+clocken0 => ram_block3a19.ENA0
+clocken0 => ram_block3a20.ENA0
+clocken0 => ram_block3a21.ENA0
+clocken0 => ram_block3a22.ENA0
+clocken0 => ram_block3a23.ENA0
+data_a[0] => ram_block3a0.PORTADATAIN
+data_a[1] => ram_block3a1.PORTADATAIN
+data_a[2] => ram_block3a2.PORTADATAIN
+data_a[3] => ram_block3a3.PORTADATAIN
+data_a[4] => ram_block3a4.PORTADATAIN
+data_a[5] => ram_block3a5.PORTADATAIN
+data_a[6] => ram_block3a6.PORTADATAIN
+data_a[7] => ram_block3a7.PORTADATAIN
+data_a[8] => ram_block3a8.PORTADATAIN
+data_a[9] => ram_block3a9.PORTADATAIN
+data_a[10] => ram_block3a10.PORTADATAIN
+data_a[11] => ram_block3a11.PORTADATAIN
+data_a[12] => ram_block3a12.PORTADATAIN
+data_a[13] => ram_block3a13.PORTADATAIN
+data_a[14] => ram_block3a14.PORTADATAIN
+data_a[15] => ram_block3a15.PORTADATAIN
+data_a[16] => ram_block3a16.PORTADATAIN
+data_a[17] => ram_block3a17.PORTADATAIN
+data_a[18] => ram_block3a18.PORTADATAIN
+data_a[19] => ram_block3a19.PORTADATAIN
+data_a[20] => ram_block3a20.PORTADATAIN
+data_a[21] => ram_block3a21.PORTADATAIN
+data_a[22] => ram_block3a22.PORTADATAIN
+data_a[23] => ram_block3a23.PORTADATAIN
+q_b[0] <= ram_block3a0.PORTBDATAOUT
+q_b[1] <= ram_block3a1.PORTBDATAOUT
+q_b[2] <= ram_block3a2.PORTBDATAOUT
+q_b[3] <= ram_block3a3.PORTBDATAOUT
+q_b[4] <= ram_block3a4.PORTBDATAOUT
+q_b[5] <= ram_block3a5.PORTBDATAOUT
+q_b[6] <= ram_block3a6.PORTBDATAOUT
+q_b[7] <= ram_block3a7.PORTBDATAOUT
+q_b[8] <= ram_block3a8.PORTBDATAOUT
+q_b[9] <= ram_block3a9.PORTBDATAOUT
+q_b[10] <= ram_block3a10.PORTBDATAOUT
+q_b[11] <= ram_block3a11.PORTBDATAOUT
+q_b[12] <= ram_block3a12.PORTBDATAOUT
+q_b[13] <= ram_block3a13.PORTBDATAOUT
+q_b[14] <= ram_block3a14.PORTBDATAOUT
+q_b[15] <= ram_block3a15.PORTBDATAOUT
+q_b[16] <= ram_block3a16.PORTBDATAOUT
+q_b[17] <= ram_block3a17.PORTBDATAOUT
+q_b[18] <= ram_block3a18.PORTBDATAOUT
+q_b[19] <= ram_block3a19.PORTBDATAOUT
+q_b[20] <= ram_block3a20.PORTBDATAOUT
+q_b[21] <= ram_block3a21.PORTBDATAOUT
+q_b[22] <= ram_block3a22.PORTBDATAOUT
+q_b[23] <= ram_block3a23.PORTBDATAOUT
+wren_a => ram_block3a0.PORTAWE
+wren_a => ram_block3a1.PORTAWE
+wren_a => ram_block3a2.PORTAWE
+wren_a => ram_block3a3.PORTAWE
+wren_a => ram_block3a4.PORTAWE
+wren_a => ram_block3a5.PORTAWE
+wren_a => ram_block3a6.PORTAWE
+wren_a => ram_block3a7.PORTAWE
+wren_a => ram_block3a8.PORTAWE
+wren_a => ram_block3a9.PORTAWE
+wren_a => ram_block3a10.PORTAWE
+wren_a => ram_block3a11.PORTAWE
+wren_a => ram_block3a12.PORTAWE
+wren_a => ram_block3a13.PORTAWE
+wren_a => ram_block3a14.PORTAWE
+wren_a => ram_block3a15.PORTAWE
+wren_a => ram_block3a16.PORTAWE
+wren_a => ram_block3a17.PORTAWE
+wren_a => ram_block3a18.PORTAWE
+wren_a => ram_block3a19.PORTAWE
+wren_a => ram_block3a20.PORTAWE
+wren_a => ram_block3a21.PORTAWE
+wren_a => ram_block3a22.PORTAWE
+wren_a => ram_block3a23.PORTAWE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1
+clk_en => counter_reg_bit[10].IN0
+clock => counter_reg_bit[10].CLK
+clock => counter_reg_bit[9].CLK
+clock => counter_reg_bit[8].CLK
+clock => counter_reg_bit[7].CLK
+clock => counter_reg_bit[6].CLK
+clock => counter_reg_bit[5].CLK
+clock => counter_reg_bit[4].CLK
+clock => counter_reg_bit[3].CLK
+clock => counter_reg_bit[2].CLK
+clock => counter_reg_bit[1].CLK
+clock => counter_reg_bit[0].CLK
+q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter_reg_bit[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter_reg_bit[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter_reg_bit[9].DB_MAX_OUTPUT_PORT_TYPE
+q[10] <= counter_reg_bit[10].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+dataa[10] => data_wire[7].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+datab[10] => data_wire[7].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5
+oSEG0[0] <= SEG7_LUT:u0.port0
+oSEG0[1] <= SEG7_LUT:u0.port0
+oSEG0[2] <= SEG7_LUT:u0.port0
+oSEG0[3] <= SEG7_LUT:u0.port0
+oSEG0[4] <= SEG7_LUT:u0.port0
+oSEG0[5] <= SEG7_LUT:u0.port0
+oSEG0[6] <= SEG7_LUT:u0.port0
+oSEG1[0] <= SEG7_LUT:u1.port0
+oSEG1[1] <= SEG7_LUT:u1.port0
+oSEG1[2] <= SEG7_LUT:u1.port0
+oSEG1[3] <= SEG7_LUT:u1.port0
+oSEG1[4] <= SEG7_LUT:u1.port0
+oSEG1[5] <= SEG7_LUT:u1.port0
+oSEG1[6] <= SEG7_LUT:u1.port0
+oSEG2[0] <= SEG7_LUT:u2.port0
+oSEG2[1] <= SEG7_LUT:u2.port0
+oSEG2[2] <= SEG7_LUT:u2.port0
+oSEG2[3] <= SEG7_LUT:u2.port0
+oSEG2[4] <= SEG7_LUT:u2.port0
+oSEG2[5] <= SEG7_LUT:u2.port0
+oSEG2[6] <= SEG7_LUT:u2.port0
+oSEG3[0] <= SEG7_LUT:u3.port0
+oSEG3[1] <= SEG7_LUT:u3.port0
+oSEG3[2] <= SEG7_LUT:u3.port0
+oSEG3[3] <= SEG7_LUT:u3.port0
+oSEG3[4] <= SEG7_LUT:u3.port0
+oSEG3[5] <= SEG7_LUT:u3.port0
+oSEG3[6] <= SEG7_LUT:u3.port0
+oSEG4[0] <= SEG7_LUT:u4.port0
+oSEG4[1] <= SEG7_LUT:u4.port0
+oSEG4[2] <= SEG7_LUT:u4.port0
+oSEG4[3] <= SEG7_LUT:u4.port0
+oSEG4[4] <= SEG7_LUT:u4.port0
+oSEG4[5] <= SEG7_LUT:u4.port0
+oSEG4[6] <= SEG7_LUT:u4.port0
+oSEG5[0] <= SEG7_LUT:u5.port0
+oSEG5[1] <= SEG7_LUT:u5.port0
+oSEG5[2] <= SEG7_LUT:u5.port0
+oSEG5[3] <= SEG7_LUT:u5.port0
+oSEG5[4] <= SEG7_LUT:u5.port0
+oSEG5[5] <= SEG7_LUT:u5.port0
+oSEG5[6] <= SEG7_LUT:u5.port0
+oSEG6[0] <= SEG7_LUT:u6.port0
+oSEG6[1] <= SEG7_LUT:u6.port0
+oSEG6[2] <= SEG7_LUT:u6.port0
+oSEG6[3] <= SEG7_LUT:u6.port0
+oSEG6[4] <= SEG7_LUT:u6.port0
+oSEG6[5] <= SEG7_LUT:u6.port0
+oSEG6[6] <= SEG7_LUT:u6.port0
+oSEG7[0] <= SEG7_LUT:u7.port0
+oSEG7[1] <= SEG7_LUT:u7.port0
+oSEG7[2] <= SEG7_LUT:u7.port0
+oSEG7[3] <= SEG7_LUT:u7.port0
+oSEG7[4] <= SEG7_LUT:u7.port0
+oSEG7[5] <= SEG7_LUT:u7.port0
+oSEG7[6] <= SEG7_LUT:u7.port0
+iDIG[0] => iDIG[0].IN1
+iDIG[1] => iDIG[1].IN1
+iDIG[2] => iDIG[2].IN1
+iDIG[3] => iDIG[3].IN1
+iDIG[4] => iDIG[4].IN1
+iDIG[5] => iDIG[5].IN1
+iDIG[6] => iDIG[6].IN1
+iDIG[7] => iDIG[7].IN1
+iDIG[8] => iDIG[8].IN1
+iDIG[9] => iDIG[9].IN1
+iDIG[10] => iDIG[10].IN1
+iDIG[11] => iDIG[11].IN1
+iDIG[12] => iDIG[12].IN1
+iDIG[13] => iDIG[13].IN1
+iDIG[14] => iDIG[14].IN1
+iDIG[15] => iDIG[15].IN1
+iDIG[16] => iDIG[16].IN1
+iDIG[17] => iDIG[17].IN1
+iDIG[18] => iDIG[18].IN1
+iDIG[19] => iDIG[19].IN1
+iDIG[20] => iDIG[20].IN1
+iDIG[21] => iDIG[21].IN1
+iDIG[22] => iDIG[22].IN1
+iDIG[23] => iDIG[23].IN1
+iDIG[24] => iDIG[24].IN1
+iDIG[25] => iDIG[25].IN1
+iDIG[26] => iDIG[26].IN1
+iDIG[27] => iDIG[27].IN1
+iDIG[28] => iDIG[28].IN1
+iDIG[29] => iDIG[29].IN1
+iDIG[30] => iDIG[30].IN1
+iDIG[31] => iDIG[31].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u1
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u2
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u3
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u4
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u5
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u6
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u7
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6
+inclk0 => sub_wire4[0].IN1
+c0 <= altpll:altpll_component.clk
+c1 <= altpll:altpll_component.clk
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component
+inclk[0] => altpll_9ee2:auto_generated.inclk[0]
+inclk[1] => altpll_9ee2:auto_generated.inclk[1]
+fbin => ~NO_FANOUT~
+pllena => ~NO_FANOUT~
+clkswitch => ~NO_FANOUT~
+areset => ~NO_FANOUT~
+pfdena => ~NO_FANOUT~
+clkena[0] => ~NO_FANOUT~
+clkena[1] => ~NO_FANOUT~
+clkena[2] => ~NO_FANOUT~
+clkena[3] => ~NO_FANOUT~
+clkena[4] => ~NO_FANOUT~
+clkena[5] => ~NO_FANOUT~
+extclkena[0] => ~NO_FANOUT~
+extclkena[1] => ~NO_FANOUT~
+extclkena[2] => ~NO_FANOUT~
+extclkena[3] => ~NO_FANOUT~
+scanclk => ~NO_FANOUT~
+scanclkena => ~NO_FANOUT~
+scanaclr => ~NO_FANOUT~
+scanread => ~NO_FANOUT~
+scanwrite => ~NO_FANOUT~
+scandata => ~NO_FANOUT~
+phasecounterselect[0] => ~NO_FANOUT~
+phasecounterselect[1] => ~NO_FANOUT~
+phasecounterselect[2] => ~NO_FANOUT~
+phasecounterselect[3] => ~NO_FANOUT~
+phaseupdown => ~NO_FANOUT~
+phasestep => ~NO_FANOUT~
+configupdate => ~NO_FANOUT~
+fbmimicbidir <> <GND>
+clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
+clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
+clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
+clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
+clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
+extclk[0] <= <GND>
+extclk[1] <= <GND>
+extclk[2] <= <GND>
+extclk[3] <= <GND>
+clkbad[0] <= <GND>
+clkbad[1] <= <GND>
+enable1 <= <GND>
+enable0 <= <GND>
+activeclock <= <GND>
+clkloss <= <GND>
+locked <= <GND>
+scandataout <= <GND>
+scandone <= <GND>
+sclkout0 <= <GND>
+sclkout1 <= <GND>
+phasedone <= <GND>
+vcooverrange <= <GND>
+vcounderrange <= <GND>
+fbout <= <GND>
+fref <= <GND>
+icdrclk <= <GND>
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated
+clk[0] <= pll1.CLK
+clk[1] <= pll1.CLK1
+clk[2] <= pll1.CLK2
+clk[3] <= pll1.CLK3
+clk[4] <= pll1.CLK4
+inclk[0] => pll1.CLK
+inclk[1] => pll1.CLK1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7
+REF_CLK => ~NO_FANOUT~
+RESET_N => RESET_N.IN3
+CLK => CLK.IN7
+WR1_DATA[0] => WR1_DATA[0].IN1
+WR1_DATA[1] => WR1_DATA[1].IN1
+WR1_DATA[2] => WR1_DATA[2].IN1
+WR1_DATA[3] => WR1_DATA[3].IN1
+WR1_DATA[4] => WR1_DATA[4].IN1
+WR1_DATA[5] => WR1_DATA[5].IN1
+WR1_DATA[6] => WR1_DATA[6].IN1
+WR1_DATA[7] => WR1_DATA[7].IN1
+WR1_DATA[8] => WR1_DATA[8].IN1
+WR1_DATA[9] => WR1_DATA[9].IN1
+WR1_DATA[10] => WR1_DATA[10].IN1
+WR1_DATA[11] => WR1_DATA[11].IN1
+WR1_DATA[12] => WR1_DATA[12].IN1
+WR1_DATA[13] => WR1_DATA[13].IN1
+WR1_DATA[14] => WR1_DATA[14].IN1
+WR1_DATA[15] => WR1_DATA[15].IN1
+WR1 => WR1.IN1
+WR1_ADDR[0] => rWR1_ADDR.DATAA
+WR1_ADDR[0] => rWR1_ADDR.DATAB
+WR1_ADDR[1] => rWR1_ADDR.DATAA
+WR1_ADDR[1] => rWR1_ADDR.DATAB
+WR1_ADDR[2] => rWR1_ADDR.DATAA
+WR1_ADDR[2] => rWR1_ADDR.DATAB
+WR1_ADDR[3] => rWR1_ADDR.DATAA
+WR1_ADDR[3] => rWR1_ADDR.DATAB
+WR1_ADDR[4] => rWR1_ADDR.DATAA
+WR1_ADDR[4] => rWR1_ADDR.DATAB
+WR1_ADDR[5] => rWR1_ADDR.DATAA
+WR1_ADDR[5] => rWR1_ADDR.DATAB
+WR1_ADDR[6] => rWR1_ADDR.DATAA
+WR1_ADDR[6] => rWR1_ADDR.DATAB
+WR1_ADDR[7] => rWR1_ADDR.DATAA
+WR1_ADDR[7] => rWR1_ADDR.DATAB
+WR1_ADDR[8] => rWR1_ADDR.DATAA
+WR1_ADDR[8] => rWR1_ADDR.DATAB
+WR1_ADDR[9] => rWR1_ADDR.DATAA
+WR1_ADDR[9] => rWR1_ADDR.DATAB
+WR1_ADDR[10] => rWR1_ADDR.DATAA
+WR1_ADDR[10] => rWR1_ADDR.DATAB
+WR1_ADDR[11] => rWR1_ADDR.DATAA
+WR1_ADDR[11] => rWR1_ADDR.DATAB
+WR1_ADDR[12] => rWR1_ADDR.DATAA
+WR1_ADDR[12] => rWR1_ADDR.DATAB
+WR1_ADDR[13] => rWR1_ADDR.DATAA
+WR1_ADDR[13] => rWR1_ADDR.DATAB
+WR1_ADDR[14] => rWR1_ADDR.DATAA
+WR1_ADDR[14] => rWR1_ADDR.DATAB
+WR1_ADDR[15] => rWR1_ADDR.DATAA
+WR1_ADDR[15] => rWR1_ADDR.DATAB
+WR1_ADDR[16] => rWR1_ADDR.DATAA
+WR1_ADDR[16] => rWR1_ADDR.DATAB
+WR1_ADDR[17] => rWR1_ADDR.DATAA
+WR1_ADDR[17] => rWR1_ADDR.DATAB
+WR1_ADDR[18] => rWR1_ADDR.DATAA
+WR1_ADDR[18] => rWR1_ADDR.DATAB
+WR1_ADDR[19] => rWR1_ADDR.DATAA
+WR1_ADDR[19] => rWR1_ADDR.DATAB
+WR1_ADDR[20] => rWR1_ADDR.DATAA
+WR1_ADDR[20] => rWR1_ADDR.DATAB
+WR1_ADDR[21] => rWR1_ADDR.DATAA
+WR1_ADDR[21] => rWR1_ADDR.DATAB
+WR1_ADDR[22] => rWR1_ADDR.DATAA
+WR1_ADDR[22] => rWR1_ADDR.DATAB
+WR1_MAX_ADDR[0] => ~NO_FANOUT~
+WR1_MAX_ADDR[1] => ~NO_FANOUT~
+WR1_MAX_ADDR[2] => ~NO_FANOUT~
+WR1_MAX_ADDR[3] => ~NO_FANOUT~
+WR1_MAX_ADDR[4] => ~NO_FANOUT~
+WR1_MAX_ADDR[5] => ~NO_FANOUT~
+WR1_MAX_ADDR[6] => ~NO_FANOUT~
+WR1_MAX_ADDR[7] => ~NO_FANOUT~
+WR1_MAX_ADDR[8] => ~NO_FANOUT~
+WR1_MAX_ADDR[9] => ~NO_FANOUT~
+WR1_MAX_ADDR[10] => ~NO_FANOUT~
+WR1_MAX_ADDR[11] => ~NO_FANOUT~
+WR1_MAX_ADDR[12] => ~NO_FANOUT~
+WR1_MAX_ADDR[13] => ~NO_FANOUT~
+WR1_MAX_ADDR[14] => ~NO_FANOUT~
+WR1_MAX_ADDR[15] => ~NO_FANOUT~
+WR1_MAX_ADDR[16] => ~NO_FANOUT~
+WR1_MAX_ADDR[17] => ~NO_FANOUT~
+WR1_MAX_ADDR[18] => ~NO_FANOUT~
+WR1_MAX_ADDR[19] => ~NO_FANOUT~
+WR1_MAX_ADDR[20] => ~NO_FANOUT~
+WR1_MAX_ADDR[21] => ~NO_FANOUT~
+WR1_MAX_ADDR[22] => ~NO_FANOUT~
+WR1_LENGTH[0] => rWR1_LENGTH[0].DATAIN
+WR1_LENGTH[1] => rWR1_LENGTH[1].DATAIN
+WR1_LENGTH[2] => rWR1_LENGTH[2].DATAIN
+WR1_LENGTH[3] => rWR1_LENGTH[3].DATAIN
+WR1_LENGTH[4] => rWR1_LENGTH[4].DATAIN
+WR1_LENGTH[5] => rWR1_LENGTH[5].DATAIN
+WR1_LENGTH[6] => rWR1_LENGTH[6].DATAIN
+WR1_LENGTH[7] => rWR1_LENGTH[7].DATAIN
+WR1_LENGTH[8] => rWR1_LENGTH[8].DATAIN
+WR1_LOAD => WR1_LOAD.IN1
+WR1_CLK => WR1_CLK.IN1
+WR2_DATA[0] => WR2_DATA[0].IN1
+WR2_DATA[1] => WR2_DATA[1].IN1
+WR2_DATA[2] => WR2_DATA[2].IN1
+WR2_DATA[3] => WR2_DATA[3].IN1
+WR2_DATA[4] => WR2_DATA[4].IN1
+WR2_DATA[5] => WR2_DATA[5].IN1
+WR2_DATA[6] => WR2_DATA[6].IN1
+WR2_DATA[7] => WR2_DATA[7].IN1
+WR2_DATA[8] => WR2_DATA[8].IN1
+WR2_DATA[9] => WR2_DATA[9].IN1
+WR2_DATA[10] => WR2_DATA[10].IN1
+WR2_DATA[11] => WR2_DATA[11].IN1
+WR2_DATA[12] => WR2_DATA[12].IN1
+WR2_DATA[13] => WR2_DATA[13].IN1
+WR2_DATA[14] => WR2_DATA[14].IN1
+WR2_DATA[15] => WR2_DATA[15].IN1
+WR2 => WR2.IN1
+WR2_ADDR[0] => rWR2_ADDR.DATAA
+WR2_ADDR[0] => rWR2_ADDR.DATAB
+WR2_ADDR[1] => rWR2_ADDR.DATAA
+WR2_ADDR[1] => rWR2_ADDR.DATAB
+WR2_ADDR[2] => rWR2_ADDR.DATAA
+WR2_ADDR[2] => rWR2_ADDR.DATAB
+WR2_ADDR[3] => rWR2_ADDR.DATAA
+WR2_ADDR[3] => rWR2_ADDR.DATAB
+WR2_ADDR[4] => rWR2_ADDR.DATAA
+WR2_ADDR[4] => rWR2_ADDR.DATAB
+WR2_ADDR[5] => rWR2_ADDR.DATAA
+WR2_ADDR[5] => rWR2_ADDR.DATAB
+WR2_ADDR[6] => rWR2_ADDR.DATAA
+WR2_ADDR[6] => rWR2_ADDR.DATAB
+WR2_ADDR[7] => rWR2_ADDR.DATAA
+WR2_ADDR[7] => rWR2_ADDR.DATAB
+WR2_ADDR[8] => rWR2_ADDR.DATAA
+WR2_ADDR[8] => rWR2_ADDR.DATAB
+WR2_ADDR[9] => rWR2_ADDR.DATAA
+WR2_ADDR[9] => rWR2_ADDR.DATAB
+WR2_ADDR[10] => rWR2_ADDR.DATAA
+WR2_ADDR[10] => rWR2_ADDR.DATAB
+WR2_ADDR[11] => rWR2_ADDR.DATAA
+WR2_ADDR[11] => rWR2_ADDR.DATAB
+WR2_ADDR[12] => rWR2_ADDR.DATAA
+WR2_ADDR[12] => rWR2_ADDR.DATAB
+WR2_ADDR[13] => rWR2_ADDR.DATAA
+WR2_ADDR[13] => rWR2_ADDR.DATAB
+WR2_ADDR[14] => rWR2_ADDR.DATAA
+WR2_ADDR[14] => rWR2_ADDR.DATAB
+WR2_ADDR[15] => rWR2_ADDR.DATAA
+WR2_ADDR[15] => rWR2_ADDR.DATAB
+WR2_ADDR[16] => rWR2_ADDR.DATAA
+WR2_ADDR[16] => rWR2_ADDR.DATAB
+WR2_ADDR[17] => rWR2_ADDR.DATAA
+WR2_ADDR[17] => rWR2_ADDR.DATAB
+WR2_ADDR[18] => rWR2_ADDR.DATAA
+WR2_ADDR[18] => rWR2_ADDR.DATAB
+WR2_ADDR[19] => rWR2_ADDR.DATAA
+WR2_ADDR[19] => rWR2_ADDR.DATAB
+WR2_ADDR[20] => rWR2_ADDR.DATAA
+WR2_ADDR[20] => rWR2_ADDR.DATAB
+WR2_ADDR[21] => rWR2_ADDR.DATAA
+WR2_ADDR[21] => rWR2_ADDR.DATAB
+WR2_ADDR[22] => rWR2_ADDR.DATAA
+WR2_ADDR[22] => rWR2_ADDR.DATAB
+WR2_MAX_ADDR[0] => ~NO_FANOUT~
+WR2_MAX_ADDR[1] => ~NO_FANOUT~
+WR2_MAX_ADDR[2] => ~NO_FANOUT~
+WR2_MAX_ADDR[3] => ~NO_FANOUT~
+WR2_MAX_ADDR[4] => ~NO_FANOUT~
+WR2_MAX_ADDR[5] => ~NO_FANOUT~
+WR2_MAX_ADDR[6] => ~NO_FANOUT~
+WR2_MAX_ADDR[7] => ~NO_FANOUT~
+WR2_MAX_ADDR[8] => ~NO_FANOUT~
+WR2_MAX_ADDR[9] => ~NO_FANOUT~
+WR2_MAX_ADDR[10] => ~NO_FANOUT~
+WR2_MAX_ADDR[11] => ~NO_FANOUT~
+WR2_MAX_ADDR[12] => ~NO_FANOUT~
+WR2_MAX_ADDR[13] => ~NO_FANOUT~
+WR2_MAX_ADDR[14] => ~NO_FANOUT~
+WR2_MAX_ADDR[15] => ~NO_FANOUT~
+WR2_MAX_ADDR[16] => ~NO_FANOUT~
+WR2_MAX_ADDR[17] => ~NO_FANOUT~
+WR2_MAX_ADDR[18] => ~NO_FANOUT~
+WR2_MAX_ADDR[19] => ~NO_FANOUT~
+WR2_MAX_ADDR[20] => ~NO_FANOUT~
+WR2_MAX_ADDR[21] => ~NO_FANOUT~
+WR2_MAX_ADDR[22] => ~NO_FANOUT~
+WR2_LENGTH[0] => rWR2_LENGTH[0].DATAIN
+WR2_LENGTH[1] => rWR2_LENGTH[1].DATAIN
+WR2_LENGTH[2] => rWR2_LENGTH[2].DATAIN
+WR2_LENGTH[3] => rWR2_LENGTH[3].DATAIN
+WR2_LENGTH[4] => rWR2_LENGTH[4].DATAIN
+WR2_LENGTH[5] => rWR2_LENGTH[5].DATAIN
+WR2_LENGTH[6] => rWR2_LENGTH[6].DATAIN
+WR2_LENGTH[7] => rWR2_LENGTH[7].DATAIN
+WR2_LENGTH[8] => rWR2_LENGTH[8].DATAIN
+WR2_LOAD => WR2_LOAD.IN1
+WR2_CLK => WR2_CLK.IN1
+RD1_DATA[0] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[1] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[2] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[3] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[4] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[5] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[6] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[7] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[8] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[9] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[10] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[11] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[12] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[13] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[14] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[15] <= Sdram_FIFO:read_fifo1.q
+RD1 => RD1.IN1
+RD1_ADDR[0] => rRD1_ADDR.DATAA
+RD1_ADDR[0] => rRD1_ADDR.DATAB
+RD1_ADDR[1] => rRD1_ADDR.DATAA
+RD1_ADDR[1] => rRD1_ADDR.DATAB
+RD1_ADDR[2] => rRD1_ADDR.DATAA
+RD1_ADDR[2] => rRD1_ADDR.DATAB
+RD1_ADDR[3] => rRD1_ADDR.DATAA
+RD1_ADDR[3] => rRD1_ADDR.DATAB
+RD1_ADDR[4] => rRD1_ADDR.DATAA
+RD1_ADDR[4] => rRD1_ADDR.DATAB
+RD1_ADDR[5] => rRD1_ADDR.DATAA
+RD1_ADDR[5] => rRD1_ADDR.DATAB
+RD1_ADDR[6] => rRD1_ADDR.DATAA
+RD1_ADDR[6] => rRD1_ADDR.DATAB
+RD1_ADDR[7] => rRD1_ADDR.DATAA
+RD1_ADDR[7] => rRD1_ADDR.DATAB
+RD1_ADDR[8] => rRD1_ADDR.DATAA
+RD1_ADDR[8] => rRD1_ADDR.DATAB
+RD1_ADDR[9] => rRD1_ADDR.DATAA
+RD1_ADDR[9] => rRD1_ADDR.DATAB
+RD1_ADDR[10] => rRD1_ADDR.DATAA
+RD1_ADDR[10] => rRD1_ADDR.DATAB
+RD1_ADDR[11] => rRD1_ADDR.DATAA
+RD1_ADDR[11] => rRD1_ADDR.DATAB
+RD1_ADDR[12] => rRD1_ADDR.DATAA
+RD1_ADDR[12] => rRD1_ADDR.DATAB
+RD1_ADDR[13] => rRD1_ADDR.DATAA
+RD1_ADDR[13] => rRD1_ADDR.DATAB
+RD1_ADDR[14] => rRD1_ADDR.DATAA
+RD1_ADDR[14] => rRD1_ADDR.DATAB
+RD1_ADDR[15] => rRD1_ADDR.DATAA
+RD1_ADDR[15] => rRD1_ADDR.DATAB
+RD1_ADDR[16] => rRD1_ADDR.DATAA
+RD1_ADDR[16] => rRD1_ADDR.DATAB
+RD1_ADDR[17] => rRD1_ADDR.DATAA
+RD1_ADDR[17] => rRD1_ADDR.DATAB
+RD1_ADDR[18] => rRD1_ADDR.DATAA
+RD1_ADDR[18] => rRD1_ADDR.DATAB
+RD1_ADDR[19] => rRD1_ADDR.DATAA
+RD1_ADDR[19] => rRD1_ADDR.DATAB
+RD1_ADDR[20] => rRD1_ADDR.DATAA
+RD1_ADDR[20] => rRD1_ADDR.DATAB
+RD1_ADDR[21] => rRD1_ADDR.DATAA
+RD1_ADDR[21] => rRD1_ADDR.DATAB
+RD1_ADDR[22] => rRD1_ADDR.DATAA
+RD1_ADDR[22] => rRD1_ADDR.DATAB
+RD1_MAX_ADDR[0] => ~NO_FANOUT~
+RD1_MAX_ADDR[1] => ~NO_FANOUT~
+RD1_MAX_ADDR[2] => ~NO_FANOUT~
+RD1_MAX_ADDR[3] => ~NO_FANOUT~
+RD1_MAX_ADDR[4] => ~NO_FANOUT~
+RD1_MAX_ADDR[5] => ~NO_FANOUT~
+RD1_MAX_ADDR[6] => ~NO_FANOUT~
+RD1_MAX_ADDR[7] => ~NO_FANOUT~
+RD1_MAX_ADDR[8] => ~NO_FANOUT~
+RD1_MAX_ADDR[9] => ~NO_FANOUT~
+RD1_MAX_ADDR[10] => ~NO_FANOUT~
+RD1_MAX_ADDR[11] => ~NO_FANOUT~
+RD1_MAX_ADDR[12] => ~NO_FANOUT~
+RD1_MAX_ADDR[13] => ~NO_FANOUT~
+RD1_MAX_ADDR[14] => ~NO_FANOUT~
+RD1_MAX_ADDR[15] => ~NO_FANOUT~
+RD1_MAX_ADDR[16] => ~NO_FANOUT~
+RD1_MAX_ADDR[17] => ~NO_FANOUT~
+RD1_MAX_ADDR[18] => ~NO_FANOUT~
+RD1_MAX_ADDR[19] => ~NO_FANOUT~
+RD1_MAX_ADDR[20] => ~NO_FANOUT~
+RD1_MAX_ADDR[21] => ~NO_FANOUT~
+RD1_MAX_ADDR[22] => ~NO_FANOUT~
+RD1_LENGTH[0] => rRD1_LENGTH[0].DATAIN
+RD1_LENGTH[1] => rRD1_LENGTH[1].DATAIN
+RD1_LENGTH[2] => rRD1_LENGTH[2].DATAIN
+RD1_LENGTH[3] => rRD1_LENGTH[3].DATAIN
+RD1_LENGTH[4] => rRD1_LENGTH[4].DATAIN
+RD1_LENGTH[5] => rRD1_LENGTH[5].DATAIN
+RD1_LENGTH[6] => rRD1_LENGTH[6].DATAIN
+RD1_LENGTH[7] => rRD1_LENGTH[7].DATAIN
+RD1_LENGTH[8] => rRD1_LENGTH[8].DATAIN
+RD1_LOAD => RD1_LOAD.IN1
+RD1_CLK => RD1_CLK.IN1
+RD2_DATA[0] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[1] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[2] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[3] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[4] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[5] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[6] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[7] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[8] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[9] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[10] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[11] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[12] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[13] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[14] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[15] <= Sdram_FIFO:read_fifo2.q
+RD2 => RD2.IN1
+RD2_ADDR[0] => rRD2_ADDR.DATAA
+RD2_ADDR[0] => rRD2_ADDR.DATAB
+RD2_ADDR[1] => rRD2_ADDR.DATAA
+RD2_ADDR[1] => rRD2_ADDR.DATAB
+RD2_ADDR[2] => rRD2_ADDR.DATAA
+RD2_ADDR[2] => rRD2_ADDR.DATAB
+RD2_ADDR[3] => rRD2_ADDR.DATAA
+RD2_ADDR[3] => rRD2_ADDR.DATAB
+RD2_ADDR[4] => rRD2_ADDR.DATAA
+RD2_ADDR[4] => rRD2_ADDR.DATAB
+RD2_ADDR[5] => rRD2_ADDR.DATAA
+RD2_ADDR[5] => rRD2_ADDR.DATAB
+RD2_ADDR[6] => rRD2_ADDR.DATAA
+RD2_ADDR[6] => rRD2_ADDR.DATAB
+RD2_ADDR[7] => rRD2_ADDR.DATAA
+RD2_ADDR[7] => rRD2_ADDR.DATAB
+RD2_ADDR[8] => rRD2_ADDR.DATAA
+RD2_ADDR[8] => rRD2_ADDR.DATAB
+RD2_ADDR[9] => rRD2_ADDR.DATAA
+RD2_ADDR[9] => rRD2_ADDR.DATAB
+RD2_ADDR[10] => rRD2_ADDR.DATAA
+RD2_ADDR[10] => rRD2_ADDR.DATAB
+RD2_ADDR[11] => rRD2_ADDR.DATAA
+RD2_ADDR[11] => rRD2_ADDR.DATAB
+RD2_ADDR[12] => rRD2_ADDR.DATAA
+RD2_ADDR[12] => rRD2_ADDR.DATAB
+RD2_ADDR[13] => rRD2_ADDR.DATAA
+RD2_ADDR[13] => rRD2_ADDR.DATAB
+RD2_ADDR[14] => rRD2_ADDR.DATAA
+RD2_ADDR[14] => rRD2_ADDR.DATAB
+RD2_ADDR[15] => rRD2_ADDR.DATAA
+RD2_ADDR[15] => rRD2_ADDR.DATAB
+RD2_ADDR[16] => rRD2_ADDR.DATAA
+RD2_ADDR[16] => rRD2_ADDR.DATAB
+RD2_ADDR[17] => rRD2_ADDR.DATAA
+RD2_ADDR[17] => rRD2_ADDR.DATAB
+RD2_ADDR[18] => rRD2_ADDR.DATAA
+RD2_ADDR[18] => rRD2_ADDR.DATAB
+RD2_ADDR[19] => rRD2_ADDR.DATAA
+RD2_ADDR[19] => rRD2_ADDR.DATAB
+RD2_ADDR[20] => rRD2_ADDR.DATAA
+RD2_ADDR[20] => rRD2_ADDR.DATAB
+RD2_ADDR[21] => rRD2_ADDR.DATAA
+RD2_ADDR[21] => rRD2_ADDR.DATAB
+RD2_ADDR[22] => rRD2_ADDR.DATAA
+RD2_ADDR[22] => rRD2_ADDR.DATAB
+RD2_MAX_ADDR[0] => ~NO_FANOUT~
+RD2_MAX_ADDR[1] => ~NO_FANOUT~
+RD2_MAX_ADDR[2] => ~NO_FANOUT~
+RD2_MAX_ADDR[3] => ~NO_FANOUT~
+RD2_MAX_ADDR[4] => ~NO_FANOUT~
+RD2_MAX_ADDR[5] => ~NO_FANOUT~
+RD2_MAX_ADDR[6] => ~NO_FANOUT~
+RD2_MAX_ADDR[7] => ~NO_FANOUT~
+RD2_MAX_ADDR[8] => ~NO_FANOUT~
+RD2_MAX_ADDR[9] => ~NO_FANOUT~
+RD2_MAX_ADDR[10] => ~NO_FANOUT~
+RD2_MAX_ADDR[11] => ~NO_FANOUT~
+RD2_MAX_ADDR[12] => ~NO_FANOUT~
+RD2_MAX_ADDR[13] => ~NO_FANOUT~
+RD2_MAX_ADDR[14] => ~NO_FANOUT~
+RD2_MAX_ADDR[15] => ~NO_FANOUT~
+RD2_MAX_ADDR[16] => ~NO_FANOUT~
+RD2_MAX_ADDR[17] => ~NO_FANOUT~
+RD2_MAX_ADDR[18] => ~NO_FANOUT~
+RD2_MAX_ADDR[19] => ~NO_FANOUT~
+RD2_MAX_ADDR[20] => ~NO_FANOUT~
+RD2_MAX_ADDR[21] => ~NO_FANOUT~
+RD2_MAX_ADDR[22] => ~NO_FANOUT~
+RD2_LENGTH[0] => rRD2_LENGTH[0].DATAIN
+RD2_LENGTH[1] => rRD2_LENGTH[1].DATAIN
+RD2_LENGTH[2] => rRD2_LENGTH[2].DATAIN
+RD2_LENGTH[3] => rRD2_LENGTH[3].DATAIN
+RD2_LENGTH[4] => rRD2_LENGTH[4].DATAIN
+RD2_LENGTH[5] => rRD2_LENGTH[5].DATAIN
+RD2_LENGTH[6] => rRD2_LENGTH[6].DATAIN
+RD2_LENGTH[7] => rRD2_LENGTH[7].DATAIN
+RD2_LENGTH[8] => rRD2_LENGTH[8].DATAIN
+RD2_LOAD => RD2_LOAD.IN1
+RD2_CLK => RD2_CLK.IN1
+SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+BA[0] <= BA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+BA[1] <= BA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CS_N[0] <= CS_N[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CS_N[1] <= CS_N[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CKE <= CKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RAS_N <= RAS_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CAS_N <= CAS_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+WE_N <= WE_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+DQ[0] <> DQ[0]
+DQ[1] <> DQ[1]
+DQ[2] <> DQ[2]
+DQ[3] <> DQ[3]
+DQ[4] <> DQ[4]
+DQ[5] <> DQ[5]
+DQ[6] <> DQ[6]
+DQ[7] <> DQ[7]
+DQ[8] <> DQ[8]
+DQ[9] <> DQ[9]
+DQ[10] <> DQ[10]
+DQ[11] <> DQ[11]
+DQ[12] <> DQ[12]
+DQ[13] <> DQ[13]
+DQ[14] <> DQ[14]
+DQ[15] <> DQ[15]
+DQM[0] <= DQM[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+DQM[1] <= DQM[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1
+CLK => INIT_REQ~reg0.CLK
+CLK => LOAD_MODE~reg0.CLK
+CLK => PRECHARGE~reg0.CLK
+CLK => REFRESH~reg0.CLK
+CLK => init_timer[0].CLK
+CLK => init_timer[1].CLK
+CLK => init_timer[2].CLK
+CLK => init_timer[3].CLK
+CLK => init_timer[4].CLK
+CLK => init_timer[5].CLK
+CLK => init_timer[6].CLK
+CLK => init_timer[7].CLK
+CLK => init_timer[8].CLK
+CLK => init_timer[9].CLK
+CLK => init_timer[10].CLK
+CLK => init_timer[11].CLK
+CLK => init_timer[12].CLK
+CLK => init_timer[13].CLK
+CLK => init_timer[14].CLK
+CLK => init_timer[15].CLK
+CLK => REF_REQ~reg0.CLK
+CLK => timer[0].CLK
+CLK => timer[1].CLK
+CLK => timer[2].CLK
+CLK => timer[3].CLK
+CLK => timer[4].CLK
+CLK => timer[5].CLK
+CLK => timer[6].CLK
+CLK => timer[7].CLK
+CLK => timer[8].CLK
+CLK => timer[9].CLK
+CLK => timer[10].CLK
+CLK => timer[11].CLK
+CLK => timer[12].CLK
+CLK => timer[13].CLK
+CLK => timer[14].CLK
+CLK => timer[15].CLK
+CLK => CMD_ACK~reg0.CLK
+CLK => SADDR[0]~reg0.CLK
+CLK => SADDR[1]~reg0.CLK
+CLK => SADDR[2]~reg0.CLK
+CLK => SADDR[3]~reg0.CLK
+CLK => SADDR[4]~reg0.CLK
+CLK => SADDR[5]~reg0.CLK
+CLK => SADDR[6]~reg0.CLK
+CLK => SADDR[7]~reg0.CLK
+CLK => SADDR[8]~reg0.CLK
+CLK => SADDR[9]~reg0.CLK
+CLK => SADDR[10]~reg0.CLK
+CLK => SADDR[11]~reg0.CLK
+CLK => SADDR[12]~reg0.CLK
+CLK => SADDR[13]~reg0.CLK
+CLK => SADDR[14]~reg0.CLK
+CLK => SADDR[15]~reg0.CLK
+CLK => SADDR[16]~reg0.CLK
+CLK => SADDR[17]~reg0.CLK
+CLK => SADDR[18]~reg0.CLK
+CLK => SADDR[19]~reg0.CLK
+CLK => SADDR[20]~reg0.CLK
+CLK => SADDR[21]~reg0.CLK
+CLK => SADDR[22]~reg0.CLK
+CLK => WRITEA~reg0.CLK
+CLK => READA~reg0.CLK
+CLK => NOP~reg0.CLK
+RESET_N => SADDR[0]~reg0.ACLR
+RESET_N => SADDR[1]~reg0.ACLR
+RESET_N => SADDR[2]~reg0.ACLR
+RESET_N => SADDR[3]~reg0.ACLR
+RESET_N => SADDR[4]~reg0.ACLR
+RESET_N => SADDR[5]~reg0.ACLR
+RESET_N => SADDR[6]~reg0.ACLR
+RESET_N => SADDR[7]~reg0.ACLR
+RESET_N => SADDR[8]~reg0.ACLR
+RESET_N => SADDR[9]~reg0.ACLR
+RESET_N => SADDR[10]~reg0.ACLR
+RESET_N => SADDR[11]~reg0.ACLR
+RESET_N => SADDR[12]~reg0.ACLR
+RESET_N => SADDR[13]~reg0.ACLR
+RESET_N => SADDR[14]~reg0.ACLR
+RESET_N => SADDR[15]~reg0.ACLR
+RESET_N => SADDR[16]~reg0.ACLR
+RESET_N => SADDR[17]~reg0.ACLR
+RESET_N => SADDR[18]~reg0.ACLR
+RESET_N => SADDR[19]~reg0.ACLR
+RESET_N => SADDR[20]~reg0.ACLR
+RESET_N => SADDR[21]~reg0.ACLR
+RESET_N => SADDR[22]~reg0.ACLR
+RESET_N => WRITEA~reg0.ACLR
+RESET_N => READA~reg0.ACLR
+RESET_N => NOP~reg0.ACLR
+RESET_N => INIT_REQ~reg0.ACLR
+RESET_N => LOAD_MODE~reg0.ACLR
+RESET_N => PRECHARGE~reg0.ACLR
+RESET_N => REFRESH~reg0.ACLR
+RESET_N => init_timer[0].ACLR
+RESET_N => init_timer[1].ACLR
+RESET_N => init_timer[2].ACLR
+RESET_N => init_timer[3].ACLR
+RESET_N => init_timer[4].ACLR
+RESET_N => init_timer[5].ACLR
+RESET_N => init_timer[6].ACLR
+RESET_N => init_timer[7].ACLR
+RESET_N => init_timer[8].ACLR
+RESET_N => init_timer[9].ACLR
+RESET_N => init_timer[10].ACLR
+RESET_N => init_timer[11].ACLR
+RESET_N => init_timer[12].ACLR
+RESET_N => init_timer[13].ACLR
+RESET_N => init_timer[14].ACLR
+RESET_N => init_timer[15].ACLR
+RESET_N => REF_REQ~reg0.ACLR
+RESET_N => timer[0].ACLR
+RESET_N => timer[1].ACLR
+RESET_N => timer[2].ACLR
+RESET_N => timer[3].ACLR
+RESET_N => timer[4].ACLR
+RESET_N => timer[5].ACLR
+RESET_N => timer[6].ACLR
+RESET_N => timer[7].ACLR
+RESET_N => timer[8].ACLR
+RESET_N => timer[9].ACLR
+RESET_N => timer[10].ACLR
+RESET_N => timer[11].ACLR
+RESET_N => timer[12].ACLR
+RESET_N => timer[13].ACLR
+RESET_N => timer[14].ACLR
+RESET_N => timer[15].ACLR
+RESET_N => CMD_ACK~reg0.ACLR
+CMD[0] => Equal0.IN2
+CMD[0] => Equal1.IN0
+CMD[0] => Equal2.IN2
+CMD[1] => Equal0.IN1
+CMD[1] => Equal1.IN2
+CMD[1] => Equal2.IN0
+CMD[2] => Equal0.IN0
+CMD[2] => Equal1.IN1
+CMD[2] => Equal2.IN1
+ADDR[0] => SADDR[0]~reg0.DATAIN
+ADDR[1] => SADDR[1]~reg0.DATAIN
+ADDR[2] => SADDR[2]~reg0.DATAIN
+ADDR[3] => SADDR[3]~reg0.DATAIN
+ADDR[4] => SADDR[4]~reg0.DATAIN
+ADDR[5] => SADDR[5]~reg0.DATAIN
+ADDR[6] => SADDR[6]~reg0.DATAIN
+ADDR[7] => SADDR[7]~reg0.DATAIN
+ADDR[8] => SADDR[8]~reg0.DATAIN
+ADDR[9] => SADDR[9]~reg0.DATAIN
+ADDR[10] => SADDR[10]~reg0.DATAIN
+ADDR[11] => SADDR[11]~reg0.DATAIN
+ADDR[12] => SADDR[12]~reg0.DATAIN
+ADDR[13] => SADDR[13]~reg0.DATAIN
+ADDR[14] => SADDR[14]~reg0.DATAIN
+ADDR[15] => SADDR[15]~reg0.DATAIN
+ADDR[16] => SADDR[16]~reg0.DATAIN
+ADDR[17] => SADDR[17]~reg0.DATAIN
+ADDR[18] => SADDR[18]~reg0.DATAIN
+ADDR[19] => SADDR[19]~reg0.DATAIN
+ADDR[20] => SADDR[20]~reg0.DATAIN
+ADDR[21] => SADDR[21]~reg0.DATAIN
+ADDR[22] => SADDR[22]~reg0.DATAIN
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => REF_REQ.OUTPUTSELECT
+INIT_ACK => ~NO_FANOUT~
+CM_ACK => always1.IN1
+NOP <= NOP~reg0.DB_MAX_OUTPUT_PORT_TYPE
+READA <= READA~reg0.DB_MAX_OUTPUT_PORT_TYPE
+WRITEA <= WRITEA~reg0.DB_MAX_OUTPUT_PORT_TYPE
+REFRESH <= REFRESH~reg0.DB_MAX_OUTPUT_PORT_TYPE
+PRECHARGE <= PRECHARGE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+LOAD_MODE <= LOAD_MODE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[0] <= SADDR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[1] <= SADDR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[2] <= SADDR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[3] <= SADDR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[4] <= SADDR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[5] <= SADDR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[6] <= SADDR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[7] <= SADDR[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[8] <= SADDR[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[9] <= SADDR[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[10] <= SADDR[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[11] <= SADDR[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[12] <= SADDR[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[13] <= SADDR[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[14] <= SADDR[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[15] <= SADDR[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[16] <= SADDR[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[17] <= SADDR[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[18] <= SADDR[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[19] <= SADDR[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[20] <= SADDR[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[21] <= SADDR[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[22] <= SADDR[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+REF_REQ <= REF_REQ~reg0.DB_MAX_OUTPUT_PORT_TYPE
+INIT_REQ <= INIT_REQ~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CMD_ACK <= CMD_ACK~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1
+CLK => CKE~reg0.CLK
+CLK => WE_N~reg0.CLK
+CLK => CAS_N~reg0.CLK
+CLK => RAS_N~reg0.CLK
+CLK => CS_N[0]~reg0.CLK
+CLK => CS_N[1]~reg0.CLK
+CLK => BA[0]~reg0.CLK
+CLK => BA[1]~reg0.CLK
+CLK => SA[0]~reg0.CLK
+CLK => SA[1]~reg0.CLK
+CLK => SA[2]~reg0.CLK
+CLK => SA[3]~reg0.CLK
+CLK => SA[4]~reg0.CLK
+CLK => SA[5]~reg0.CLK
+CLK => SA[6]~reg0.CLK
+CLK => SA[7]~reg0.CLK
+CLK => SA[8]~reg0.CLK
+CLK => SA[9]~reg0.CLK
+CLK => SA[10]~reg0.CLK
+CLK => SA[11]~reg0.CLK
+CLK => REF_ACK~reg0.CLK
+CLK => CM_ACK~reg0.CLK
+CLK => do_rw.CLK
+CLK => rw_shift[0].CLK
+CLK => rw_shift[1].CLK
+CLK => oe4.CLK
+CLK => OE~reg0.CLK
+CLK => ex_write.CLK
+CLK => ex_read.CLK
+CLK => rp_done.CLK
+CLK => rp_shift[0].CLK
+CLK => rp_shift[1].CLK
+CLK => rp_shift[2].CLK
+CLK => rp_shift[3].CLK
+CLK => rw_flag.CLK
+CLK => command_delay[0].CLK
+CLK => command_delay[1].CLK
+CLK => command_delay[2].CLK
+CLK => command_delay[3].CLK
+CLK => command_delay[4].CLK
+CLK => command_delay[5].CLK
+CLK => command_delay[6].CLK
+CLK => command_delay[7].CLK
+CLK => command_done.CLK
+CLK => do_initial.CLK
+CLK => do_load_mode.CLK
+CLK => do_precharge.CLK
+CLK => do_refresh.CLK
+CLK => do_writea.CLK
+CLK => do_reada.CLK
+RESET_N => CKE~reg0.DATAIN
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => BA.OUTPUTSELECT
+RESET_N => BA.OUTPUTSELECT
+RESET_N => CS_N.OUTPUTSELECT
+RESET_N => CS_N.OUTPUTSELECT
+RESET_N => RAS_N.OUTPUTSELECT
+RESET_N => CAS_N.OUTPUTSELECT
+RESET_N => WE_N.OUTPUTSELECT
+RESET_N => REF_ACK~reg0.ACLR
+RESET_N => CM_ACK~reg0.ACLR
+RESET_N => OE~reg0.ACLR
+RESET_N => ex_write.ACLR
+RESET_N => ex_read.ACLR
+RESET_N => rp_done.ACLR
+RESET_N => rp_shift[0].ACLR
+RESET_N => rp_shift[1].ACLR
+RESET_N => rp_shift[2].ACLR
+RESET_N => rp_shift[3].ACLR
+RESET_N => rw_flag.ACLR
+RESET_N => command_delay[0].ACLR
+RESET_N => command_delay[1].ACLR
+RESET_N => command_delay[2].ACLR
+RESET_N => command_delay[3].ACLR
+RESET_N => command_delay[4].ACLR
+RESET_N => command_delay[5].ACLR
+RESET_N => command_delay[6].ACLR
+RESET_N => command_delay[7].ACLR
+RESET_N => command_done.ACLR
+RESET_N => do_initial.ACLR
+RESET_N => do_load_mode.ACLR
+RESET_N => do_precharge.ACLR
+RESET_N => do_refresh.ACLR
+RESET_N => do_writea.ACLR
+RESET_N => do_reada.ACLR
+RESET_N => do_rw.ACLR
+RESET_N => rw_shift[0].ACLR
+RESET_N => rw_shift[1].ACLR
+RESET_N => oe4.ENA
+SADDR[0] => SA.DATAA
+SADDR[1] => SA.DATAA
+SADDR[2] => SA.DATAA
+SADDR[3] => SA.DATAA
+SADDR[4] => SA.DATAA
+SADDR[5] => SA.DATAA
+SADDR[6] => SA.DATAA
+SADDR[7] => SA.DATAA
+SADDR[8] => SA.DATAB
+SADDR[9] => SA.DATAB
+SADDR[10] => SA.DATAB
+SADDR[11] => SA.DATAB
+SADDR[12] => SA.DATAB
+SADDR[13] => SA.DATAB
+SADDR[14] => SA.DATAB
+SADDR[15] => SA.DATAB
+SADDR[16] => SA.DATAB
+SADDR[17] => SA.DATAB
+SADDR[18] => SA.DATAB
+SADDR[19] => SA.DATAB
+SADDR[20] => BA.DATAA
+SADDR[21] => BA.DATAA
+SADDR[22] => CS_N.DATAA
+SADDR[22] => CS_N.DATAA
+NOP => ~NO_FANOUT~
+READA => always0.IN1
+WRITEA => always0.IN1
+REFRESH => always0.IN0
+PRECHARGE => always0.IN1
+LOAD_MODE => always0.IN1
+REF_REQ => always0.IN1
+REF_REQ => always3.IN1
+REF_REQ => always0.IN1
+REF_REQ => always0.IN1
+INIT_REQ => do_reada.OUTPUTSELECT
+INIT_REQ => do_writea.OUTPUTSELECT
+INIT_REQ => do_refresh.OUTPUTSELECT
+INIT_REQ => do_precharge.OUTPUTSELECT
+INIT_REQ => do_load_mode.OUTPUTSELECT
+INIT_REQ => command_done.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => rw_flag.OUTPUTSELECT
+INIT_REQ => rp_shift.OUTPUTSELECT
+INIT_REQ => rp_shift.OUTPUTSELECT
+INIT_REQ => rp_shift.OUTPUTSELECT
+INIT_REQ => rp_shift.OUTPUTSELECT
+INIT_REQ => rp_done.OUTPUTSELECT
+INIT_REQ => ex_read.OUTPUTSELECT
+INIT_REQ => ex_write.OUTPUTSELECT
+INIT_REQ => do_initial.DATAIN
+PM_STOP => rp_shift.OUTPUTSELECT
+PM_STOP => rp_shift.OUTPUTSELECT
+PM_STOP => rp_shift.OUTPUTSELECT
+PM_STOP => rp_shift.OUTPUTSELECT
+PM_STOP => rp_done.OUTPUTSELECT
+PM_STOP => ex_read.OUTPUTSELECT
+PM_STOP => ex_write.OUTPUTSELECT
+PM_STOP => always1.IN1
+PM_DONE => ~NO_FANOUT~
+REF_ACK <= REF_ACK~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CM_ACK <= CM_ACK~reg0.DB_MAX_OUTPUT_PORT_TYPE
+OE <= OE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+BA[0] <= BA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+BA[1] <= BA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CS_N[0] <= CS_N[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CS_N[1] <= CS_N[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CKE <= CKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RAS_N <= RAS_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CAS_N <= CAS_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+WE_N <= WE_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1
+CLK => DQM[0]~reg0.CLK
+CLK => DQM[1]~reg0.CLK
+RESET_N => DQM[0]~reg0.PRESET
+RESET_N => DQM[1]~reg0.ACLR
+DATAIN[0] => DQOUT[0].DATAIN
+DATAIN[1] => DQOUT[1].DATAIN
+DATAIN[2] => DQOUT[2].DATAIN
+DATAIN[3] => DQOUT[3].DATAIN
+DATAIN[4] => DQOUT[4].DATAIN
+DATAIN[5] => DQOUT[5].DATAIN
+DATAIN[6] => DQOUT[6].DATAIN
+DATAIN[7] => DQOUT[7].DATAIN
+DATAIN[8] => DQOUT[8].DATAIN
+DATAIN[9] => DQOUT[9].DATAIN
+DATAIN[10] => DQOUT[10].DATAIN
+DATAIN[11] => DQOUT[11].DATAIN
+DATAIN[12] => DQOUT[12].DATAIN
+DATAIN[13] => DQOUT[13].DATAIN
+DATAIN[14] => DQOUT[14].DATAIN
+DATAIN[15] => DQOUT[15].DATAIN
+DM[0] => DQM[0]~reg0.DATAIN
+DM[1] => DQM[1]~reg0.DATAIN
+DQOUT[0] <= DATAIN[0].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[1] <= DATAIN[1].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[2] <= DATAIN[2].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[3] <= DATAIN[3].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[4] <= DATAIN[4].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[5] <= DATAIN[5].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[6] <= DATAIN[6].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[7] <= DATAIN[7].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[8] <= DATAIN[8].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[9] <= DATAIN[9].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[10] <= DATAIN[10].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[11] <= DATAIN[11].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[12] <= DATAIN[12].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[13] <= DATAIN[13].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[14] <= DATAIN[14].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[15] <= DATAIN[15].DB_MAX_OUTPUT_PORT_TYPE
+DQM[0] <= DQM[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+DQM[1] <= DQM[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1
+aclr => aclr.IN1
+data[0] => data[0].IN1
+data[1] => data[1].IN1
+data[2] => data[2].IN1
+data[3] => data[3].IN1
+data[4] => data[4].IN1
+data[5] => data[5].IN1
+data[6] => data[6].IN1
+data[7] => data[7].IN1
+data[8] => data[8].IN1
+data[9] => data[9].IN1
+data[10] => data[10].IN1
+data[11] => data[11].IN1
+data[12] => data[12].IN1
+data[13] => data[13].IN1
+data[14] => data[14].IN1
+data[15] => data[15].IN1
+rdclk => rdclk.IN1
+rdreq => rdreq.IN1
+wrclk => wrclk.IN1
+wrreq => wrreq.IN1
+q[0] <= dcfifo:dcfifo_component.q
+q[1] <= dcfifo:dcfifo_component.q
+q[2] <= dcfifo:dcfifo_component.q
+q[3] <= dcfifo:dcfifo_component.q
+q[4] <= dcfifo:dcfifo_component.q
+q[5] <= dcfifo:dcfifo_component.q
+q[6] <= dcfifo:dcfifo_component.q
+q[7] <= dcfifo:dcfifo_component.q
+q[8] <= dcfifo:dcfifo_component.q
+q[9] <= dcfifo:dcfifo_component.q
+q[10] <= dcfifo:dcfifo_component.q
+q[11] <= dcfifo:dcfifo_component.q
+q[12] <= dcfifo:dcfifo_component.q
+q[13] <= dcfifo:dcfifo_component.q
+q[14] <= dcfifo:dcfifo_component.q
+q[15] <= dcfifo:dcfifo_component.q
+rdempty <= dcfifo:dcfifo_component.rdempty
+rdusedw[0] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[1] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[2] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[3] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[4] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[5] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[6] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[7] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[8] <= dcfifo:dcfifo_component.rdusedw
+wrfull <= dcfifo:dcfifo_component.wrfull
+wrusedw[0] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[1] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[2] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[3] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[4] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[5] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[6] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[7] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[8] <= dcfifo:dcfifo_component.wrusedw
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+data[0] => dcfifo_v5o1:auto_generated.data[0]
+data[1] => dcfifo_v5o1:auto_generated.data[1]
+data[2] => dcfifo_v5o1:auto_generated.data[2]
+data[3] => dcfifo_v5o1:auto_generated.data[3]
+data[4] => dcfifo_v5o1:auto_generated.data[4]
+data[5] => dcfifo_v5o1:auto_generated.data[5]
+data[6] => dcfifo_v5o1:auto_generated.data[6]
+data[7] => dcfifo_v5o1:auto_generated.data[7]
+data[8] => dcfifo_v5o1:auto_generated.data[8]
+data[9] => dcfifo_v5o1:auto_generated.data[9]
+data[10] => dcfifo_v5o1:auto_generated.data[10]
+data[11] => dcfifo_v5o1:auto_generated.data[11]
+data[12] => dcfifo_v5o1:auto_generated.data[12]
+data[13] => dcfifo_v5o1:auto_generated.data[13]
+data[14] => dcfifo_v5o1:auto_generated.data[14]
+data[15] => dcfifo_v5o1:auto_generated.data[15]
+q[0] <= dcfifo_v5o1:auto_generated.q[0]
+q[1] <= dcfifo_v5o1:auto_generated.q[1]
+q[2] <= dcfifo_v5o1:auto_generated.q[2]
+q[3] <= dcfifo_v5o1:auto_generated.q[3]
+q[4] <= dcfifo_v5o1:auto_generated.q[4]
+q[5] <= dcfifo_v5o1:auto_generated.q[5]
+q[6] <= dcfifo_v5o1:auto_generated.q[6]
+q[7] <= dcfifo_v5o1:auto_generated.q[7]
+q[8] <= dcfifo_v5o1:auto_generated.q[8]
+q[9] <= dcfifo_v5o1:auto_generated.q[9]
+q[10] <= dcfifo_v5o1:auto_generated.q[10]
+q[11] <= dcfifo_v5o1:auto_generated.q[11]
+q[12] <= dcfifo_v5o1:auto_generated.q[12]
+q[13] <= dcfifo_v5o1:auto_generated.q[13]
+q[14] <= dcfifo_v5o1:auto_generated.q[14]
+q[15] <= dcfifo_v5o1:auto_generated.q[15]
+rdclk => dcfifo_v5o1:auto_generated.rdclk
+rdreq => dcfifo_v5o1:auto_generated.rdreq
+wrclk => dcfifo_v5o1:auto_generated.wrclk
+wrreq => dcfifo_v5o1:auto_generated.wrreq
+aclr => dcfifo_v5o1:auto_generated.aclr
+rdempty <= dcfifo_v5o1:auto_generated.rdempty
+rdfull <= <UNC>
+wrempty <= <GND>
+wrfull <= dcfifo_v5o1:auto_generated.wrfull
+rdusedw[0] <= dcfifo_v5o1:auto_generated.rdusedw[0]
+rdusedw[1] <= dcfifo_v5o1:auto_generated.rdusedw[1]
+rdusedw[2] <= dcfifo_v5o1:auto_generated.rdusedw[2]
+rdusedw[3] <= dcfifo_v5o1:auto_generated.rdusedw[3]
+rdusedw[4] <= dcfifo_v5o1:auto_generated.rdusedw[4]
+rdusedw[5] <= dcfifo_v5o1:auto_generated.rdusedw[5]
+rdusedw[6] <= dcfifo_v5o1:auto_generated.rdusedw[6]
+rdusedw[7] <= dcfifo_v5o1:auto_generated.rdusedw[7]
+rdusedw[8] <= dcfifo_v5o1:auto_generated.rdusedw[8]
+wrusedw[0] <= dcfifo_v5o1:auto_generated.wrusedw[0]
+wrusedw[1] <= dcfifo_v5o1:auto_generated.wrusedw[1]
+wrusedw[2] <= dcfifo_v5o1:auto_generated.wrusedw[2]
+wrusedw[3] <= dcfifo_v5o1:auto_generated.wrusedw[3]
+wrusedw[4] <= dcfifo_v5o1:auto_generated.wrusedw[4]
+wrusedw[5] <= dcfifo_v5o1:auto_generated.wrusedw[5]
+wrusedw[6] <= dcfifo_v5o1:auto_generated.wrusedw[6]
+wrusedw[7] <= dcfifo_v5o1:auto_generated.wrusedw[7]
+wrusedw[8] <= dcfifo_v5o1:auto_generated.wrusedw[8]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+aclr => a_graycounter_s57:rdptr_g1p.aclr
+aclr => a_graycounter_ojc:wrptr_g1p.aclr
+aclr => altsyncram_de51:fifo_ram.aclr1
+aclr => delayed_wrptr_g[9].IN0
+aclr => rdptr_g[9].IN0
+aclr => wrptr_g[9].IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+data[0] => altsyncram_de51:fifo_ram.data_a[0]
+data[1] => altsyncram_de51:fifo_ram.data_a[1]
+data[2] => altsyncram_de51:fifo_ram.data_a[2]
+data[3] => altsyncram_de51:fifo_ram.data_a[3]
+data[4] => altsyncram_de51:fifo_ram.data_a[4]
+data[5] => altsyncram_de51:fifo_ram.data_a[5]
+data[6] => altsyncram_de51:fifo_ram.data_a[6]
+data[7] => altsyncram_de51:fifo_ram.data_a[7]
+data[8] => altsyncram_de51:fifo_ram.data_a[8]
+data[9] => altsyncram_de51:fifo_ram.data_a[9]
+data[10] => altsyncram_de51:fifo_ram.data_a[10]
+data[11] => altsyncram_de51:fifo_ram.data_a[11]
+data[12] => altsyncram_de51:fifo_ram.data_a[12]
+data[13] => altsyncram_de51:fifo_ram.data_a[13]
+data[14] => altsyncram_de51:fifo_ram.data_a[14]
+data[15] => altsyncram_de51:fifo_ram.data_a[15]
+q[0] <= altsyncram_de51:fifo_ram.q_b[0]
+q[1] <= altsyncram_de51:fifo_ram.q_b[1]
+q[2] <= altsyncram_de51:fifo_ram.q_b[2]
+q[3] <= altsyncram_de51:fifo_ram.q_b[3]
+q[4] <= altsyncram_de51:fifo_ram.q_b[4]
+q[5] <= altsyncram_de51:fifo_ram.q_b[5]
+q[6] <= altsyncram_de51:fifo_ram.q_b[6]
+q[7] <= altsyncram_de51:fifo_ram.q_b[7]
+q[8] <= altsyncram_de51:fifo_ram.q_b[8]
+q[9] <= altsyncram_de51:fifo_ram.q_b[9]
+q[10] <= altsyncram_de51:fifo_ram.q_b[10]
+q[11] <= altsyncram_de51:fifo_ram.q_b[11]
+q[12] <= altsyncram_de51:fifo_ram.q_b[12]
+q[13] <= altsyncram_de51:fifo_ram.q_b[13]
+q[14] <= altsyncram_de51:fifo_ram.q_b[14]
+q[15] <= altsyncram_de51:fifo_ram.q_b[15]
+rdclk => a_graycounter_s57:rdptr_g1p.clock
+rdclk => altsyncram_de51:fifo_ram.clock1
+rdclk => dffpipe_oe9:rs_brp.clock
+rdclk => dffpipe_oe9:rs_bwp.clock
+rdclk => alt_synch_pipe_qld:rs_dgwp.clock
+rdclk => rdptr_g[9].CLK
+rdclk => rdptr_g[8].CLK
+rdclk => rdptr_g[7].CLK
+rdclk => rdptr_g[6].CLK
+rdclk => rdptr_g[5].CLK
+rdclk => rdptr_g[4].CLK
+rdclk => rdptr_g[3].CLK
+rdclk => rdptr_g[2].CLK
+rdclk => rdptr_g[1].CLK
+rdclk => rdptr_g[0].CLK
+rdempty <= int_rdempty.DB_MAX_OUTPUT_PORT_TYPE
+rdreq => valid_rdreq.IN0
+rdusedw[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+wrclk => a_graycounter_ojc:wrptr_g1p.clock
+wrclk => altsyncram_de51:fifo_ram.clock0
+wrclk => dffpipe_oe9:ws_brp.clock
+wrclk => dffpipe_oe9:ws_bwp.clock
+wrclk => alt_synch_pipe_rld:ws_dgrp.clock
+wrclk => delayed_wrptr_g[9].CLK
+wrclk => delayed_wrptr_g[8].CLK
+wrclk => delayed_wrptr_g[7].CLK
+wrclk => delayed_wrptr_g[6].CLK
+wrclk => delayed_wrptr_g[5].CLK
+wrclk => delayed_wrptr_g[4].CLK
+wrclk => delayed_wrptr_g[3].CLK
+wrclk => delayed_wrptr_g[2].CLK
+wrclk => delayed_wrptr_g[1].CLK
+wrclk => delayed_wrptr_g[0].CLK
+wrclk => wrptr_g[9].CLK
+wrclk => wrptr_g[8].CLK
+wrclk => wrptr_g[7].CLK
+wrclk => wrptr_g[6].CLK
+wrclk => wrptr_g[5].CLK
+wrclk => wrptr_g[4].CLK
+wrclk => wrptr_g[3].CLK
+wrclk => wrptr_g[2].CLK
+wrclk => wrptr_g[1].CLK
+wrclk => wrptr_g[0].CLK
+wrfull <= int_wrfull.DB_MAX_OUTPUT_PORT_TYPE
+wrreq => valid_wrreq.IN0
+wrusedw[0] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[1] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[2] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[3] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[4] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[5] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[6] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[7] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[8] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+aclr => counter5a1.IN0
+aclr => counter5a0.IN0
+aclr => parity6.IN0
+aclr => sub_parity7a[2].IN0
+aclr => sub_parity7a[1].IN0
+aclr => sub_parity7a[0].IN0
+clock => counter5a0.CLK
+clock => counter5a1.CLK
+clock => counter5a2.CLK
+clock => counter5a3.CLK
+clock => counter5a4.CLK
+clock => counter5a5.CLK
+clock => counter5a6.CLK
+clock => counter5a7.CLK
+clock => counter5a8.CLK
+clock => counter5a9.CLK
+clock => parity6.CLK
+clock => sub_parity7a[2].CLK
+clock => sub_parity7a[1].CLK
+clock => sub_parity7a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter5a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter5a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter5a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter5a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter5a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter5a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter5a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter5a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter5a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter5a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+aclr => counter8a1.IN0
+aclr => counter8a0.IN0
+aclr => parity9.IN0
+aclr => sub_parity10a[2].IN0
+aclr => sub_parity10a[1].IN0
+aclr => sub_parity10a[0].IN0
+clock => counter8a0.CLK
+clock => counter8a1.CLK
+clock => counter8a2.CLK
+clock => counter8a3.CLK
+clock => counter8a4.CLK
+clock => counter8a5.CLK
+clock => counter8a6.CLK
+clock => counter8a7.CLK
+clock => counter8a8.CLK
+clock => counter8a9.CLK
+clock => parity9.CLK
+clock => sub_parity10a[2].CLK
+clock => sub_parity10a[1].CLK
+clock => sub_parity10a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter8a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter8a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter8a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter8a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter8a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter8a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter8a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter8a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter8a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter8a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+aclr1 => ram_block11a0.CLR1
+aclr1 => ram_block11a1.CLR1
+aclr1 => ram_block11a2.CLR1
+aclr1 => ram_block11a3.CLR1
+aclr1 => ram_block11a4.CLR1
+aclr1 => ram_block11a5.CLR1
+aclr1 => ram_block11a6.CLR1
+aclr1 => ram_block11a7.CLR1
+aclr1 => ram_block11a8.CLR1
+aclr1 => ram_block11a9.CLR1
+aclr1 => ram_block11a10.CLR1
+aclr1 => ram_block11a11.CLR1
+aclr1 => ram_block11a12.CLR1
+aclr1 => ram_block11a13.CLR1
+aclr1 => ram_block11a14.CLR1
+aclr1 => ram_block11a15.CLR1
+address_a[0] => ram_block11a0.PORTAADDR
+address_a[0] => ram_block11a1.PORTAADDR
+address_a[0] => ram_block11a2.PORTAADDR
+address_a[0] => ram_block11a3.PORTAADDR
+address_a[0] => ram_block11a4.PORTAADDR
+address_a[0] => ram_block11a5.PORTAADDR
+address_a[0] => ram_block11a6.PORTAADDR
+address_a[0] => ram_block11a7.PORTAADDR
+address_a[0] => ram_block11a8.PORTAADDR
+address_a[0] => ram_block11a9.PORTAADDR
+address_a[0] => ram_block11a10.PORTAADDR
+address_a[0] => ram_block11a11.PORTAADDR
+address_a[0] => ram_block11a12.PORTAADDR
+address_a[0] => ram_block11a13.PORTAADDR
+address_a[0] => ram_block11a14.PORTAADDR
+address_a[0] => ram_block11a15.PORTAADDR
+address_a[1] => ram_block11a0.PORTAADDR1
+address_a[1] => ram_block11a1.PORTAADDR1
+address_a[1] => ram_block11a2.PORTAADDR1
+address_a[1] => ram_block11a3.PORTAADDR1
+address_a[1] => ram_block11a4.PORTAADDR1
+address_a[1] => ram_block11a5.PORTAADDR1
+address_a[1] => ram_block11a6.PORTAADDR1
+address_a[1] => ram_block11a7.PORTAADDR1
+address_a[1] => ram_block11a8.PORTAADDR1
+address_a[1] => ram_block11a9.PORTAADDR1
+address_a[1] => ram_block11a10.PORTAADDR1
+address_a[1] => ram_block11a11.PORTAADDR1
+address_a[1] => ram_block11a12.PORTAADDR1
+address_a[1] => ram_block11a13.PORTAADDR1
+address_a[1] => ram_block11a14.PORTAADDR1
+address_a[1] => ram_block11a15.PORTAADDR1
+address_a[2] => ram_block11a0.PORTAADDR2
+address_a[2] => ram_block11a1.PORTAADDR2
+address_a[2] => ram_block11a2.PORTAADDR2
+address_a[2] => ram_block11a3.PORTAADDR2
+address_a[2] => ram_block11a4.PORTAADDR2
+address_a[2] => ram_block11a5.PORTAADDR2
+address_a[2] => ram_block11a6.PORTAADDR2
+address_a[2] => ram_block11a7.PORTAADDR2
+address_a[2] => ram_block11a8.PORTAADDR2
+address_a[2] => ram_block11a9.PORTAADDR2
+address_a[2] => ram_block11a10.PORTAADDR2
+address_a[2] => ram_block11a11.PORTAADDR2
+address_a[2] => ram_block11a12.PORTAADDR2
+address_a[2] => ram_block11a13.PORTAADDR2
+address_a[2] => ram_block11a14.PORTAADDR2
+address_a[2] => ram_block11a15.PORTAADDR2
+address_a[3] => ram_block11a0.PORTAADDR3
+address_a[3] => ram_block11a1.PORTAADDR3
+address_a[3] => ram_block11a2.PORTAADDR3
+address_a[3] => ram_block11a3.PORTAADDR3
+address_a[3] => ram_block11a4.PORTAADDR3
+address_a[3] => ram_block11a5.PORTAADDR3
+address_a[3] => ram_block11a6.PORTAADDR3
+address_a[3] => ram_block11a7.PORTAADDR3
+address_a[3] => ram_block11a8.PORTAADDR3
+address_a[3] => ram_block11a9.PORTAADDR3
+address_a[3] => ram_block11a10.PORTAADDR3
+address_a[3] => ram_block11a11.PORTAADDR3
+address_a[3] => ram_block11a12.PORTAADDR3
+address_a[3] => ram_block11a13.PORTAADDR3
+address_a[3] => ram_block11a14.PORTAADDR3
+address_a[3] => ram_block11a15.PORTAADDR3
+address_a[4] => ram_block11a0.PORTAADDR4
+address_a[4] => ram_block11a1.PORTAADDR4
+address_a[4] => ram_block11a2.PORTAADDR4
+address_a[4] => ram_block11a3.PORTAADDR4
+address_a[4] => ram_block11a4.PORTAADDR4
+address_a[4] => ram_block11a5.PORTAADDR4
+address_a[4] => ram_block11a6.PORTAADDR4
+address_a[4] => ram_block11a7.PORTAADDR4
+address_a[4] => ram_block11a8.PORTAADDR4
+address_a[4] => ram_block11a9.PORTAADDR4
+address_a[4] => ram_block11a10.PORTAADDR4
+address_a[4] => ram_block11a11.PORTAADDR4
+address_a[4] => ram_block11a12.PORTAADDR4
+address_a[4] => ram_block11a13.PORTAADDR4
+address_a[4] => ram_block11a14.PORTAADDR4
+address_a[4] => ram_block11a15.PORTAADDR4
+address_a[5] => ram_block11a0.PORTAADDR5
+address_a[5] => ram_block11a1.PORTAADDR5
+address_a[5] => ram_block11a2.PORTAADDR5
+address_a[5] => ram_block11a3.PORTAADDR5
+address_a[5] => ram_block11a4.PORTAADDR5
+address_a[5] => ram_block11a5.PORTAADDR5
+address_a[5] => ram_block11a6.PORTAADDR5
+address_a[5] => ram_block11a7.PORTAADDR5
+address_a[5] => ram_block11a8.PORTAADDR5
+address_a[5] => ram_block11a9.PORTAADDR5
+address_a[5] => ram_block11a10.PORTAADDR5
+address_a[5] => ram_block11a11.PORTAADDR5
+address_a[5] => ram_block11a12.PORTAADDR5
+address_a[5] => ram_block11a13.PORTAADDR5
+address_a[5] => ram_block11a14.PORTAADDR5
+address_a[5] => ram_block11a15.PORTAADDR5
+address_a[6] => ram_block11a0.PORTAADDR6
+address_a[6] => ram_block11a1.PORTAADDR6
+address_a[6] => ram_block11a2.PORTAADDR6
+address_a[6] => ram_block11a3.PORTAADDR6
+address_a[6] => ram_block11a4.PORTAADDR6
+address_a[6] => ram_block11a5.PORTAADDR6
+address_a[6] => ram_block11a6.PORTAADDR6
+address_a[6] => ram_block11a7.PORTAADDR6
+address_a[6] => ram_block11a8.PORTAADDR6
+address_a[6] => ram_block11a9.PORTAADDR6
+address_a[6] => ram_block11a10.PORTAADDR6
+address_a[6] => ram_block11a11.PORTAADDR6
+address_a[6] => ram_block11a12.PORTAADDR6
+address_a[6] => ram_block11a13.PORTAADDR6
+address_a[6] => ram_block11a14.PORTAADDR6
+address_a[6] => ram_block11a15.PORTAADDR6
+address_a[7] => ram_block11a0.PORTAADDR7
+address_a[7] => ram_block11a1.PORTAADDR7
+address_a[7] => ram_block11a2.PORTAADDR7
+address_a[7] => ram_block11a3.PORTAADDR7
+address_a[7] => ram_block11a4.PORTAADDR7
+address_a[7] => ram_block11a5.PORTAADDR7
+address_a[7] => ram_block11a6.PORTAADDR7
+address_a[7] => ram_block11a7.PORTAADDR7
+address_a[7] => ram_block11a8.PORTAADDR7
+address_a[7] => ram_block11a9.PORTAADDR7
+address_a[7] => ram_block11a10.PORTAADDR7
+address_a[7] => ram_block11a11.PORTAADDR7
+address_a[7] => ram_block11a12.PORTAADDR7
+address_a[7] => ram_block11a13.PORTAADDR7
+address_a[7] => ram_block11a14.PORTAADDR7
+address_a[7] => ram_block11a15.PORTAADDR7
+address_a[8] => ram_block11a0.PORTAADDR8
+address_a[8] => ram_block11a1.PORTAADDR8
+address_a[8] => ram_block11a2.PORTAADDR8
+address_a[8] => ram_block11a3.PORTAADDR8
+address_a[8] => ram_block11a4.PORTAADDR8
+address_a[8] => ram_block11a5.PORTAADDR8
+address_a[8] => ram_block11a6.PORTAADDR8
+address_a[8] => ram_block11a7.PORTAADDR8
+address_a[8] => ram_block11a8.PORTAADDR8
+address_a[8] => ram_block11a9.PORTAADDR8
+address_a[8] => ram_block11a10.PORTAADDR8
+address_a[8] => ram_block11a11.PORTAADDR8
+address_a[8] => ram_block11a12.PORTAADDR8
+address_a[8] => ram_block11a13.PORTAADDR8
+address_a[8] => ram_block11a14.PORTAADDR8
+address_a[8] => ram_block11a15.PORTAADDR8
+address_b[0] => ram_block11a0.PORTBADDR
+address_b[0] => ram_block11a1.PORTBADDR
+address_b[0] => ram_block11a2.PORTBADDR
+address_b[0] => ram_block11a3.PORTBADDR
+address_b[0] => ram_block11a4.PORTBADDR
+address_b[0] => ram_block11a5.PORTBADDR
+address_b[0] => ram_block11a6.PORTBADDR
+address_b[0] => ram_block11a7.PORTBADDR
+address_b[0] => ram_block11a8.PORTBADDR
+address_b[0] => ram_block11a9.PORTBADDR
+address_b[0] => ram_block11a10.PORTBADDR
+address_b[0] => ram_block11a11.PORTBADDR
+address_b[0] => ram_block11a12.PORTBADDR
+address_b[0] => ram_block11a13.PORTBADDR
+address_b[0] => ram_block11a14.PORTBADDR
+address_b[0] => ram_block11a15.PORTBADDR
+address_b[1] => ram_block11a0.PORTBADDR1
+address_b[1] => ram_block11a1.PORTBADDR1
+address_b[1] => ram_block11a2.PORTBADDR1
+address_b[1] => ram_block11a3.PORTBADDR1
+address_b[1] => ram_block11a4.PORTBADDR1
+address_b[1] => ram_block11a5.PORTBADDR1
+address_b[1] => ram_block11a6.PORTBADDR1
+address_b[1] => ram_block11a7.PORTBADDR1
+address_b[1] => ram_block11a8.PORTBADDR1
+address_b[1] => ram_block11a9.PORTBADDR1
+address_b[1] => ram_block11a10.PORTBADDR1
+address_b[1] => ram_block11a11.PORTBADDR1
+address_b[1] => ram_block11a12.PORTBADDR1
+address_b[1] => ram_block11a13.PORTBADDR1
+address_b[1] => ram_block11a14.PORTBADDR1
+address_b[1] => ram_block11a15.PORTBADDR1
+address_b[2] => ram_block11a0.PORTBADDR2
+address_b[2] => ram_block11a1.PORTBADDR2
+address_b[2] => ram_block11a2.PORTBADDR2
+address_b[2] => ram_block11a3.PORTBADDR2
+address_b[2] => ram_block11a4.PORTBADDR2
+address_b[2] => ram_block11a5.PORTBADDR2
+address_b[2] => ram_block11a6.PORTBADDR2
+address_b[2] => ram_block11a7.PORTBADDR2
+address_b[2] => ram_block11a8.PORTBADDR2
+address_b[2] => ram_block11a9.PORTBADDR2
+address_b[2] => ram_block11a10.PORTBADDR2
+address_b[2] => ram_block11a11.PORTBADDR2
+address_b[2] => ram_block11a12.PORTBADDR2
+address_b[2] => ram_block11a13.PORTBADDR2
+address_b[2] => ram_block11a14.PORTBADDR2
+address_b[2] => ram_block11a15.PORTBADDR2
+address_b[3] => ram_block11a0.PORTBADDR3
+address_b[3] => ram_block11a1.PORTBADDR3
+address_b[3] => ram_block11a2.PORTBADDR3
+address_b[3] => ram_block11a3.PORTBADDR3
+address_b[3] => ram_block11a4.PORTBADDR3
+address_b[3] => ram_block11a5.PORTBADDR3
+address_b[3] => ram_block11a6.PORTBADDR3
+address_b[3] => ram_block11a7.PORTBADDR3
+address_b[3] => ram_block11a8.PORTBADDR3
+address_b[3] => ram_block11a9.PORTBADDR3
+address_b[3] => ram_block11a10.PORTBADDR3
+address_b[3] => ram_block11a11.PORTBADDR3
+address_b[3] => ram_block11a12.PORTBADDR3
+address_b[3] => ram_block11a13.PORTBADDR3
+address_b[3] => ram_block11a14.PORTBADDR3
+address_b[3] => ram_block11a15.PORTBADDR3
+address_b[4] => ram_block11a0.PORTBADDR4
+address_b[4] => ram_block11a1.PORTBADDR4
+address_b[4] => ram_block11a2.PORTBADDR4
+address_b[4] => ram_block11a3.PORTBADDR4
+address_b[4] => ram_block11a4.PORTBADDR4
+address_b[4] => ram_block11a5.PORTBADDR4
+address_b[4] => ram_block11a6.PORTBADDR4
+address_b[4] => ram_block11a7.PORTBADDR4
+address_b[4] => ram_block11a8.PORTBADDR4
+address_b[4] => ram_block11a9.PORTBADDR4
+address_b[4] => ram_block11a10.PORTBADDR4
+address_b[4] => ram_block11a11.PORTBADDR4
+address_b[4] => ram_block11a12.PORTBADDR4
+address_b[4] => ram_block11a13.PORTBADDR4
+address_b[4] => ram_block11a14.PORTBADDR4
+address_b[4] => ram_block11a15.PORTBADDR4
+address_b[5] => ram_block11a0.PORTBADDR5
+address_b[5] => ram_block11a1.PORTBADDR5
+address_b[5] => ram_block11a2.PORTBADDR5
+address_b[5] => ram_block11a3.PORTBADDR5
+address_b[5] => ram_block11a4.PORTBADDR5
+address_b[5] => ram_block11a5.PORTBADDR5
+address_b[5] => ram_block11a6.PORTBADDR5
+address_b[5] => ram_block11a7.PORTBADDR5
+address_b[5] => ram_block11a8.PORTBADDR5
+address_b[5] => ram_block11a9.PORTBADDR5
+address_b[5] => ram_block11a10.PORTBADDR5
+address_b[5] => ram_block11a11.PORTBADDR5
+address_b[5] => ram_block11a12.PORTBADDR5
+address_b[5] => ram_block11a13.PORTBADDR5
+address_b[5] => ram_block11a14.PORTBADDR5
+address_b[5] => ram_block11a15.PORTBADDR5
+address_b[6] => ram_block11a0.PORTBADDR6
+address_b[6] => ram_block11a1.PORTBADDR6
+address_b[6] => ram_block11a2.PORTBADDR6
+address_b[6] => ram_block11a3.PORTBADDR6
+address_b[6] => ram_block11a4.PORTBADDR6
+address_b[6] => ram_block11a5.PORTBADDR6
+address_b[6] => ram_block11a6.PORTBADDR6
+address_b[6] => ram_block11a7.PORTBADDR6
+address_b[6] => ram_block11a8.PORTBADDR6
+address_b[6] => ram_block11a9.PORTBADDR6
+address_b[6] => ram_block11a10.PORTBADDR6
+address_b[6] => ram_block11a11.PORTBADDR6
+address_b[6] => ram_block11a12.PORTBADDR6
+address_b[6] => ram_block11a13.PORTBADDR6
+address_b[6] => ram_block11a14.PORTBADDR6
+address_b[6] => ram_block11a15.PORTBADDR6
+address_b[7] => ram_block11a0.PORTBADDR7
+address_b[7] => ram_block11a1.PORTBADDR7
+address_b[7] => ram_block11a2.PORTBADDR7
+address_b[7] => ram_block11a3.PORTBADDR7
+address_b[7] => ram_block11a4.PORTBADDR7
+address_b[7] => ram_block11a5.PORTBADDR7
+address_b[7] => ram_block11a6.PORTBADDR7
+address_b[7] => ram_block11a7.PORTBADDR7
+address_b[7] => ram_block11a8.PORTBADDR7
+address_b[7] => ram_block11a9.PORTBADDR7
+address_b[7] => ram_block11a10.PORTBADDR7
+address_b[7] => ram_block11a11.PORTBADDR7
+address_b[7] => ram_block11a12.PORTBADDR7
+address_b[7] => ram_block11a13.PORTBADDR7
+address_b[7] => ram_block11a14.PORTBADDR7
+address_b[7] => ram_block11a15.PORTBADDR7
+address_b[8] => ram_block11a0.PORTBADDR8
+address_b[8] => ram_block11a1.PORTBADDR8
+address_b[8] => ram_block11a2.PORTBADDR8
+address_b[8] => ram_block11a3.PORTBADDR8
+address_b[8] => ram_block11a4.PORTBADDR8
+address_b[8] => ram_block11a5.PORTBADDR8
+address_b[8] => ram_block11a6.PORTBADDR8
+address_b[8] => ram_block11a7.PORTBADDR8
+address_b[8] => ram_block11a8.PORTBADDR8
+address_b[8] => ram_block11a9.PORTBADDR8
+address_b[8] => ram_block11a10.PORTBADDR8
+address_b[8] => ram_block11a11.PORTBADDR8
+address_b[8] => ram_block11a12.PORTBADDR8
+address_b[8] => ram_block11a13.PORTBADDR8
+address_b[8] => ram_block11a14.PORTBADDR8
+address_b[8] => ram_block11a15.PORTBADDR8
+addressstall_b => ram_block11a0.PORTBADDRSTALL
+addressstall_b => ram_block11a1.PORTBADDRSTALL
+addressstall_b => ram_block11a2.PORTBADDRSTALL
+addressstall_b => ram_block11a3.PORTBADDRSTALL
+addressstall_b => ram_block11a4.PORTBADDRSTALL
+addressstall_b => ram_block11a5.PORTBADDRSTALL
+addressstall_b => ram_block11a6.PORTBADDRSTALL
+addressstall_b => ram_block11a7.PORTBADDRSTALL
+addressstall_b => ram_block11a8.PORTBADDRSTALL
+addressstall_b => ram_block11a9.PORTBADDRSTALL
+addressstall_b => ram_block11a10.PORTBADDRSTALL
+addressstall_b => ram_block11a11.PORTBADDRSTALL
+addressstall_b => ram_block11a12.PORTBADDRSTALL
+addressstall_b => ram_block11a13.PORTBADDRSTALL
+addressstall_b => ram_block11a14.PORTBADDRSTALL
+addressstall_b => ram_block11a15.PORTBADDRSTALL
+clock0 => ram_block11a0.CLK0
+clock0 => ram_block11a1.CLK0
+clock0 => ram_block11a2.CLK0
+clock0 => ram_block11a3.CLK0
+clock0 => ram_block11a4.CLK0
+clock0 => ram_block11a5.CLK0
+clock0 => ram_block11a6.CLK0
+clock0 => ram_block11a7.CLK0
+clock0 => ram_block11a8.CLK0
+clock0 => ram_block11a9.CLK0
+clock0 => ram_block11a10.CLK0
+clock0 => ram_block11a11.CLK0
+clock0 => ram_block11a12.CLK0
+clock0 => ram_block11a13.CLK0
+clock0 => ram_block11a14.CLK0
+clock0 => ram_block11a15.CLK0
+clock1 => ram_block11a0.CLK1
+clock1 => ram_block11a1.CLK1
+clock1 => ram_block11a2.CLK1
+clock1 => ram_block11a3.CLK1
+clock1 => ram_block11a4.CLK1
+clock1 => ram_block11a5.CLK1
+clock1 => ram_block11a6.CLK1
+clock1 => ram_block11a7.CLK1
+clock1 => ram_block11a8.CLK1
+clock1 => ram_block11a9.CLK1
+clock1 => ram_block11a10.CLK1
+clock1 => ram_block11a11.CLK1
+clock1 => ram_block11a12.CLK1
+clock1 => ram_block11a13.CLK1
+clock1 => ram_block11a14.CLK1
+clock1 => ram_block11a15.CLK1
+clocken1 => ram_block11a0.ENA1
+clocken1 => ram_block11a1.ENA1
+clocken1 => ram_block11a2.ENA1
+clocken1 => ram_block11a3.ENA1
+clocken1 => ram_block11a4.ENA1
+clocken1 => ram_block11a5.ENA1
+clocken1 => ram_block11a6.ENA1
+clocken1 => ram_block11a7.ENA1
+clocken1 => ram_block11a8.ENA1
+clocken1 => ram_block11a9.ENA1
+clocken1 => ram_block11a10.ENA1
+clocken1 => ram_block11a11.ENA1
+clocken1 => ram_block11a12.ENA1
+clocken1 => ram_block11a13.ENA1
+clocken1 => ram_block11a14.ENA1
+clocken1 => ram_block11a15.ENA1
+data_a[0] => ram_block11a0.PORTADATAIN
+data_a[1] => ram_block11a1.PORTADATAIN
+data_a[2] => ram_block11a2.PORTADATAIN
+data_a[3] => ram_block11a3.PORTADATAIN
+data_a[4] => ram_block11a4.PORTADATAIN
+data_a[5] => ram_block11a5.PORTADATAIN
+data_a[6] => ram_block11a6.PORTADATAIN
+data_a[7] => ram_block11a7.PORTADATAIN
+data_a[8] => ram_block11a8.PORTADATAIN
+data_a[9] => ram_block11a9.PORTADATAIN
+data_a[10] => ram_block11a10.PORTADATAIN
+data_a[11] => ram_block11a11.PORTADATAIN
+data_a[12] => ram_block11a12.PORTADATAIN
+data_a[13] => ram_block11a13.PORTADATAIN
+data_a[14] => ram_block11a14.PORTADATAIN
+data_a[15] => ram_block11a15.PORTADATAIN
+q_b[0] <= ram_block11a0.PORTBDATAOUT
+q_b[1] <= ram_block11a1.PORTBDATAOUT
+q_b[2] <= ram_block11a2.PORTBDATAOUT
+q_b[3] <= ram_block11a3.PORTBDATAOUT
+q_b[4] <= ram_block11a4.PORTBDATAOUT
+q_b[5] <= ram_block11a5.PORTBDATAOUT
+q_b[6] <= ram_block11a6.PORTBDATAOUT
+q_b[7] <= ram_block11a7.PORTBDATAOUT
+q_b[8] <= ram_block11a8.PORTBDATAOUT
+q_b[9] <= ram_block11a9.PORTBDATAOUT
+q_b[10] <= ram_block11a10.PORTBDATAOUT
+q_b[11] <= ram_block11a11.PORTBDATAOUT
+q_b[12] <= ram_block11a12.PORTBDATAOUT
+q_b[13] <= ram_block11a13.PORTBDATAOUT
+q_b[14] <= ram_block11a14.PORTBDATAOUT
+q_b[15] <= ram_block11a15.PORTBDATAOUT
+wren_a => ram_block11a0.PORTAWE
+wren_a => ram_block11a0.ENA0
+wren_a => ram_block11a1.PORTAWE
+wren_a => ram_block11a1.ENA0
+wren_a => ram_block11a2.PORTAWE
+wren_a => ram_block11a2.ENA0
+wren_a => ram_block11a3.PORTAWE
+wren_a => ram_block11a3.ENA0
+wren_a => ram_block11a4.PORTAWE
+wren_a => ram_block11a4.ENA0
+wren_a => ram_block11a5.PORTAWE
+wren_a => ram_block11a5.ENA0
+wren_a => ram_block11a6.PORTAWE
+wren_a => ram_block11a6.ENA0
+wren_a => ram_block11a7.PORTAWE
+wren_a => ram_block11a7.ENA0
+wren_a => ram_block11a8.PORTAWE
+wren_a => ram_block11a8.ENA0
+wren_a => ram_block11a9.PORTAWE
+wren_a => ram_block11a9.ENA0
+wren_a => ram_block11a10.PORTAWE
+wren_a => ram_block11a10.ENA0
+wren_a => ram_block11a11.PORTAWE
+wren_a => ram_block11a11.ENA0
+wren_a => ram_block11a12.PORTAWE
+wren_a => ram_block11a12.ENA0
+wren_a => ram_block11a13.PORTAWE
+wren_a => ram_block11a13.ENA0
+wren_a => ram_block11a14.PORTAWE
+wren_a => ram_block11a14.ENA0
+wren_a => ram_block11a15.PORTAWE
+wren_a => ram_block11a15.ENA0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+clock => dffpipe_pe9:dffpipe13.clock
+clrn => dffpipe_pe9:dffpipe13.clrn
+d[0] => dffpipe_pe9:dffpipe13.d[0]
+d[1] => dffpipe_pe9:dffpipe13.d[1]
+d[2] => dffpipe_pe9:dffpipe13.d[2]
+d[3] => dffpipe_pe9:dffpipe13.d[3]
+d[4] => dffpipe_pe9:dffpipe13.d[4]
+d[5] => dffpipe_pe9:dffpipe13.d[5]
+d[6] => dffpipe_pe9:dffpipe13.d[6]
+d[7] => dffpipe_pe9:dffpipe13.d[7]
+d[8] => dffpipe_pe9:dffpipe13.d[8]
+d[9] => dffpipe_pe9:dffpipe13.d[9]
+q[0] <= dffpipe_pe9:dffpipe13.q[0]
+q[1] <= dffpipe_pe9:dffpipe13.q[1]
+q[2] <= dffpipe_pe9:dffpipe13.q[2]
+q[3] <= dffpipe_pe9:dffpipe13.q[3]
+q[4] <= dffpipe_pe9:dffpipe13.q[4]
+q[5] <= dffpipe_pe9:dffpipe13.q[5]
+q[6] <= dffpipe_pe9:dffpipe13.q[6]
+q[7] <= dffpipe_pe9:dffpipe13.q[7]
+q[8] <= dffpipe_pe9:dffpipe13.q[8]
+q[9] <= dffpipe_pe9:dffpipe13.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+clock => dffe14a[9].CLK
+clock => dffe14a[8].CLK
+clock => dffe14a[7].CLK
+clock => dffe14a[6].CLK
+clock => dffe14a[5].CLK
+clock => dffe14a[4].CLK
+clock => dffe14a[3].CLK
+clock => dffe14a[2].CLK
+clock => dffe14a[1].CLK
+clock => dffe14a[0].CLK
+clock => dffe15a[9].CLK
+clock => dffe15a[8].CLK
+clock => dffe15a[7].CLK
+clock => dffe15a[6].CLK
+clock => dffe15a[5].CLK
+clock => dffe15a[4].CLK
+clock => dffe15a[3].CLK
+clock => dffe15a[2].CLK
+clock => dffe15a[1].CLK
+clock => dffe15a[0].CLK
+clrn => dffe14a[9].ACLR
+clrn => dffe14a[8].ACLR
+clrn => dffe14a[7].ACLR
+clrn => dffe14a[6].ACLR
+clrn => dffe14a[5].ACLR
+clrn => dffe14a[4].ACLR
+clrn => dffe14a[3].ACLR
+clrn => dffe14a[2].ACLR
+clrn => dffe14a[1].ACLR
+clrn => dffe14a[0].ACLR
+clrn => dffe15a[9].ACLR
+clrn => dffe15a[8].ACLR
+clrn => dffe15a[7].ACLR
+clrn => dffe15a[6].ACLR
+clrn => dffe15a[5].ACLR
+clrn => dffe15a[4].ACLR
+clrn => dffe15a[3].ACLR
+clrn => dffe15a[2].ACLR
+clrn => dffe15a[1].ACLR
+clrn => dffe15a[0].ACLR
+d[0] => dffe14a[0].IN0
+d[1] => dffe14a[1].IN0
+d[2] => dffe14a[2].IN0
+d[3] => dffe14a[3].IN0
+d[4] => dffe14a[4].IN0
+d[5] => dffe14a[5].IN0
+d[6] => dffe14a[6].IN0
+d[7] => dffe14a[7].IN0
+d[8] => dffe14a[8].IN0
+d[9] => dffe14a[9].IN0
+q[0] <= dffe15a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe15a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe15a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe15a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe15a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe15a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe15a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe15a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe15a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe15a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+clock => dffpipe_qe9:dffpipe16.clock
+clrn => dffpipe_qe9:dffpipe16.clrn
+d[0] => dffpipe_qe9:dffpipe16.d[0]
+d[1] => dffpipe_qe9:dffpipe16.d[1]
+d[2] => dffpipe_qe9:dffpipe16.d[2]
+d[3] => dffpipe_qe9:dffpipe16.d[3]
+d[4] => dffpipe_qe9:dffpipe16.d[4]
+d[5] => dffpipe_qe9:dffpipe16.d[5]
+d[6] => dffpipe_qe9:dffpipe16.d[6]
+d[7] => dffpipe_qe9:dffpipe16.d[7]
+d[8] => dffpipe_qe9:dffpipe16.d[8]
+d[9] => dffpipe_qe9:dffpipe16.d[9]
+q[0] <= dffpipe_qe9:dffpipe16.q[0]
+q[1] <= dffpipe_qe9:dffpipe16.q[1]
+q[2] <= dffpipe_qe9:dffpipe16.q[2]
+q[3] <= dffpipe_qe9:dffpipe16.q[3]
+q[4] <= dffpipe_qe9:dffpipe16.q[4]
+q[5] <= dffpipe_qe9:dffpipe16.q[5]
+q[6] <= dffpipe_qe9:dffpipe16.q[6]
+q[7] <= dffpipe_qe9:dffpipe16.q[7]
+q[8] <= dffpipe_qe9:dffpipe16.q[8]
+q[9] <= dffpipe_qe9:dffpipe16.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+clock => dffe17a[9].CLK
+clock => dffe17a[8].CLK
+clock => dffe17a[7].CLK
+clock => dffe17a[6].CLK
+clock => dffe17a[5].CLK
+clock => dffe17a[4].CLK
+clock => dffe17a[3].CLK
+clock => dffe17a[2].CLK
+clock => dffe17a[1].CLK
+clock => dffe17a[0].CLK
+clock => dffe18a[9].CLK
+clock => dffe18a[8].CLK
+clock => dffe18a[7].CLK
+clock => dffe18a[6].CLK
+clock => dffe18a[5].CLK
+clock => dffe18a[4].CLK
+clock => dffe18a[3].CLK
+clock => dffe18a[2].CLK
+clock => dffe18a[1].CLK
+clock => dffe18a[0].CLK
+clrn => dffe17a[9].ACLR
+clrn => dffe17a[8].ACLR
+clrn => dffe17a[7].ACLR
+clrn => dffe17a[6].ACLR
+clrn => dffe17a[5].ACLR
+clrn => dffe17a[4].ACLR
+clrn => dffe17a[3].ACLR
+clrn => dffe17a[2].ACLR
+clrn => dffe17a[1].ACLR
+clrn => dffe17a[0].ACLR
+clrn => dffe18a[9].ACLR
+clrn => dffe18a[8].ACLR
+clrn => dffe18a[7].ACLR
+clrn => dffe18a[6].ACLR
+clrn => dffe18a[5].ACLR
+clrn => dffe18a[4].ACLR
+clrn => dffe18a[3].ACLR
+clrn => dffe18a[2].ACLR
+clrn => dffe18a[1].ACLR
+clrn => dffe18a[0].ACLR
+d[0] => dffe17a[0].IN0
+d[1] => dffe17a[1].IN0
+d[2] => dffe17a[2].IN0
+d[3] => dffe17a[3].IN0
+d[4] => dffe17a[4].IN0
+d[5] => dffe17a[5].IN0
+d[6] => dffe17a[6].IN0
+d[7] => dffe17a[7].IN0
+d[8] => dffe17a[8].IN0
+d[9] => dffe17a[9].IN0
+q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2
+aclr => aclr.IN1
+data[0] => data[0].IN1
+data[1] => data[1].IN1
+data[2] => data[2].IN1
+data[3] => data[3].IN1
+data[4] => data[4].IN1
+data[5] => data[5].IN1
+data[6] => data[6].IN1
+data[7] => data[7].IN1
+data[8] => data[8].IN1
+data[9] => data[9].IN1
+data[10] => data[10].IN1
+data[11] => data[11].IN1
+data[12] => data[12].IN1
+data[13] => data[13].IN1
+data[14] => data[14].IN1
+data[15] => data[15].IN1
+rdclk => rdclk.IN1
+rdreq => rdreq.IN1
+wrclk => wrclk.IN1
+wrreq => wrreq.IN1
+q[0] <= dcfifo:dcfifo_component.q
+q[1] <= dcfifo:dcfifo_component.q
+q[2] <= dcfifo:dcfifo_component.q
+q[3] <= dcfifo:dcfifo_component.q
+q[4] <= dcfifo:dcfifo_component.q
+q[5] <= dcfifo:dcfifo_component.q
+q[6] <= dcfifo:dcfifo_component.q
+q[7] <= dcfifo:dcfifo_component.q
+q[8] <= dcfifo:dcfifo_component.q
+q[9] <= dcfifo:dcfifo_component.q
+q[10] <= dcfifo:dcfifo_component.q
+q[11] <= dcfifo:dcfifo_component.q
+q[12] <= dcfifo:dcfifo_component.q
+q[13] <= dcfifo:dcfifo_component.q
+q[14] <= dcfifo:dcfifo_component.q
+q[15] <= dcfifo:dcfifo_component.q
+rdempty <= dcfifo:dcfifo_component.rdempty
+rdusedw[0] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[1] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[2] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[3] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[4] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[5] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[6] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[7] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[8] <= dcfifo:dcfifo_component.rdusedw
+wrfull <= dcfifo:dcfifo_component.wrfull
+wrusedw[0] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[1] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[2] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[3] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[4] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[5] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[6] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[7] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[8] <= dcfifo:dcfifo_component.wrusedw
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+data[0] => dcfifo_v5o1:auto_generated.data[0]
+data[1] => dcfifo_v5o1:auto_generated.data[1]
+data[2] => dcfifo_v5o1:auto_generated.data[2]
+data[3] => dcfifo_v5o1:auto_generated.data[3]
+data[4] => dcfifo_v5o1:auto_generated.data[4]
+data[5] => dcfifo_v5o1:auto_generated.data[5]
+data[6] => dcfifo_v5o1:auto_generated.data[6]
+data[7] => dcfifo_v5o1:auto_generated.data[7]
+data[8] => dcfifo_v5o1:auto_generated.data[8]
+data[9] => dcfifo_v5o1:auto_generated.data[9]
+data[10] => dcfifo_v5o1:auto_generated.data[10]
+data[11] => dcfifo_v5o1:auto_generated.data[11]
+data[12] => dcfifo_v5o1:auto_generated.data[12]
+data[13] => dcfifo_v5o1:auto_generated.data[13]
+data[14] => dcfifo_v5o1:auto_generated.data[14]
+data[15] => dcfifo_v5o1:auto_generated.data[15]
+q[0] <= dcfifo_v5o1:auto_generated.q[0]
+q[1] <= dcfifo_v5o1:auto_generated.q[1]
+q[2] <= dcfifo_v5o1:auto_generated.q[2]
+q[3] <= dcfifo_v5o1:auto_generated.q[3]
+q[4] <= dcfifo_v5o1:auto_generated.q[4]
+q[5] <= dcfifo_v5o1:auto_generated.q[5]
+q[6] <= dcfifo_v5o1:auto_generated.q[6]
+q[7] <= dcfifo_v5o1:auto_generated.q[7]
+q[8] <= dcfifo_v5o1:auto_generated.q[8]
+q[9] <= dcfifo_v5o1:auto_generated.q[9]
+q[10] <= dcfifo_v5o1:auto_generated.q[10]
+q[11] <= dcfifo_v5o1:auto_generated.q[11]
+q[12] <= dcfifo_v5o1:auto_generated.q[12]
+q[13] <= dcfifo_v5o1:auto_generated.q[13]
+q[14] <= dcfifo_v5o1:auto_generated.q[14]
+q[15] <= dcfifo_v5o1:auto_generated.q[15]
+rdclk => dcfifo_v5o1:auto_generated.rdclk
+rdreq => dcfifo_v5o1:auto_generated.rdreq
+wrclk => dcfifo_v5o1:auto_generated.wrclk
+wrreq => dcfifo_v5o1:auto_generated.wrreq
+aclr => dcfifo_v5o1:auto_generated.aclr
+rdempty <= dcfifo_v5o1:auto_generated.rdempty
+rdfull <= <UNC>
+wrempty <= <GND>
+wrfull <= dcfifo_v5o1:auto_generated.wrfull
+rdusedw[0] <= dcfifo_v5o1:auto_generated.rdusedw[0]
+rdusedw[1] <= dcfifo_v5o1:auto_generated.rdusedw[1]
+rdusedw[2] <= dcfifo_v5o1:auto_generated.rdusedw[2]
+rdusedw[3] <= dcfifo_v5o1:auto_generated.rdusedw[3]
+rdusedw[4] <= dcfifo_v5o1:auto_generated.rdusedw[4]
+rdusedw[5] <= dcfifo_v5o1:auto_generated.rdusedw[5]
+rdusedw[6] <= dcfifo_v5o1:auto_generated.rdusedw[6]
+rdusedw[7] <= dcfifo_v5o1:auto_generated.rdusedw[7]
+rdusedw[8] <= dcfifo_v5o1:auto_generated.rdusedw[8]
+wrusedw[0] <= dcfifo_v5o1:auto_generated.wrusedw[0]
+wrusedw[1] <= dcfifo_v5o1:auto_generated.wrusedw[1]
+wrusedw[2] <= dcfifo_v5o1:auto_generated.wrusedw[2]
+wrusedw[3] <= dcfifo_v5o1:auto_generated.wrusedw[3]
+wrusedw[4] <= dcfifo_v5o1:auto_generated.wrusedw[4]
+wrusedw[5] <= dcfifo_v5o1:auto_generated.wrusedw[5]
+wrusedw[6] <= dcfifo_v5o1:auto_generated.wrusedw[6]
+wrusedw[7] <= dcfifo_v5o1:auto_generated.wrusedw[7]
+wrusedw[8] <= dcfifo_v5o1:auto_generated.wrusedw[8]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+aclr => a_graycounter_s57:rdptr_g1p.aclr
+aclr => a_graycounter_ojc:wrptr_g1p.aclr
+aclr => altsyncram_de51:fifo_ram.aclr1
+aclr => delayed_wrptr_g[9].IN0
+aclr => rdptr_g[9].IN0
+aclr => wrptr_g[9].IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+data[0] => altsyncram_de51:fifo_ram.data_a[0]
+data[1] => altsyncram_de51:fifo_ram.data_a[1]
+data[2] => altsyncram_de51:fifo_ram.data_a[2]
+data[3] => altsyncram_de51:fifo_ram.data_a[3]
+data[4] => altsyncram_de51:fifo_ram.data_a[4]
+data[5] => altsyncram_de51:fifo_ram.data_a[5]
+data[6] => altsyncram_de51:fifo_ram.data_a[6]
+data[7] => altsyncram_de51:fifo_ram.data_a[7]
+data[8] => altsyncram_de51:fifo_ram.data_a[8]
+data[9] => altsyncram_de51:fifo_ram.data_a[9]
+data[10] => altsyncram_de51:fifo_ram.data_a[10]
+data[11] => altsyncram_de51:fifo_ram.data_a[11]
+data[12] => altsyncram_de51:fifo_ram.data_a[12]
+data[13] => altsyncram_de51:fifo_ram.data_a[13]
+data[14] => altsyncram_de51:fifo_ram.data_a[14]
+data[15] => altsyncram_de51:fifo_ram.data_a[15]
+q[0] <= altsyncram_de51:fifo_ram.q_b[0]
+q[1] <= altsyncram_de51:fifo_ram.q_b[1]
+q[2] <= altsyncram_de51:fifo_ram.q_b[2]
+q[3] <= altsyncram_de51:fifo_ram.q_b[3]
+q[4] <= altsyncram_de51:fifo_ram.q_b[4]
+q[5] <= altsyncram_de51:fifo_ram.q_b[5]
+q[6] <= altsyncram_de51:fifo_ram.q_b[6]
+q[7] <= altsyncram_de51:fifo_ram.q_b[7]
+q[8] <= altsyncram_de51:fifo_ram.q_b[8]
+q[9] <= altsyncram_de51:fifo_ram.q_b[9]
+q[10] <= altsyncram_de51:fifo_ram.q_b[10]
+q[11] <= altsyncram_de51:fifo_ram.q_b[11]
+q[12] <= altsyncram_de51:fifo_ram.q_b[12]
+q[13] <= altsyncram_de51:fifo_ram.q_b[13]
+q[14] <= altsyncram_de51:fifo_ram.q_b[14]
+q[15] <= altsyncram_de51:fifo_ram.q_b[15]
+rdclk => a_graycounter_s57:rdptr_g1p.clock
+rdclk => altsyncram_de51:fifo_ram.clock1
+rdclk => dffpipe_oe9:rs_brp.clock
+rdclk => dffpipe_oe9:rs_bwp.clock
+rdclk => alt_synch_pipe_qld:rs_dgwp.clock
+rdclk => rdptr_g[9].CLK
+rdclk => rdptr_g[8].CLK
+rdclk => rdptr_g[7].CLK
+rdclk => rdptr_g[6].CLK
+rdclk => rdptr_g[5].CLK
+rdclk => rdptr_g[4].CLK
+rdclk => rdptr_g[3].CLK
+rdclk => rdptr_g[2].CLK
+rdclk => rdptr_g[1].CLK
+rdclk => rdptr_g[0].CLK
+rdempty <= int_rdempty.DB_MAX_OUTPUT_PORT_TYPE
+rdreq => valid_rdreq.IN0
+rdusedw[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+wrclk => a_graycounter_ojc:wrptr_g1p.clock
+wrclk => altsyncram_de51:fifo_ram.clock0
+wrclk => dffpipe_oe9:ws_brp.clock
+wrclk => dffpipe_oe9:ws_bwp.clock
+wrclk => alt_synch_pipe_rld:ws_dgrp.clock
+wrclk => delayed_wrptr_g[9].CLK
+wrclk => delayed_wrptr_g[8].CLK
+wrclk => delayed_wrptr_g[7].CLK
+wrclk => delayed_wrptr_g[6].CLK
+wrclk => delayed_wrptr_g[5].CLK
+wrclk => delayed_wrptr_g[4].CLK
+wrclk => delayed_wrptr_g[3].CLK
+wrclk => delayed_wrptr_g[2].CLK
+wrclk => delayed_wrptr_g[1].CLK
+wrclk => delayed_wrptr_g[0].CLK
+wrclk => wrptr_g[9].CLK
+wrclk => wrptr_g[8].CLK
+wrclk => wrptr_g[7].CLK
+wrclk => wrptr_g[6].CLK
+wrclk => wrptr_g[5].CLK
+wrclk => wrptr_g[4].CLK
+wrclk => wrptr_g[3].CLK
+wrclk => wrptr_g[2].CLK
+wrclk => wrptr_g[1].CLK
+wrclk => wrptr_g[0].CLK
+wrfull <= int_wrfull.DB_MAX_OUTPUT_PORT_TYPE
+wrreq => valid_wrreq.IN0
+wrusedw[0] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[1] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[2] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[3] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[4] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[5] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[6] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[7] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[8] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+aclr => counter5a1.IN0
+aclr => counter5a0.IN0
+aclr => parity6.IN0
+aclr => sub_parity7a[2].IN0
+aclr => sub_parity7a[1].IN0
+aclr => sub_parity7a[0].IN0
+clock => counter5a0.CLK
+clock => counter5a1.CLK
+clock => counter5a2.CLK
+clock => counter5a3.CLK
+clock => counter5a4.CLK
+clock => counter5a5.CLK
+clock => counter5a6.CLK
+clock => counter5a7.CLK
+clock => counter5a8.CLK
+clock => counter5a9.CLK
+clock => parity6.CLK
+clock => sub_parity7a[2].CLK
+clock => sub_parity7a[1].CLK
+clock => sub_parity7a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter5a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter5a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter5a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter5a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter5a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter5a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter5a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter5a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter5a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter5a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+aclr => counter8a1.IN0
+aclr => counter8a0.IN0
+aclr => parity9.IN0
+aclr => sub_parity10a[2].IN0
+aclr => sub_parity10a[1].IN0
+aclr => sub_parity10a[0].IN0
+clock => counter8a0.CLK
+clock => counter8a1.CLK
+clock => counter8a2.CLK
+clock => counter8a3.CLK
+clock => counter8a4.CLK
+clock => counter8a5.CLK
+clock => counter8a6.CLK
+clock => counter8a7.CLK
+clock => counter8a8.CLK
+clock => counter8a9.CLK
+clock => parity9.CLK
+clock => sub_parity10a[2].CLK
+clock => sub_parity10a[1].CLK
+clock => sub_parity10a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter8a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter8a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter8a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter8a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter8a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter8a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter8a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter8a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter8a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter8a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+aclr1 => ram_block11a0.CLR1
+aclr1 => ram_block11a1.CLR1
+aclr1 => ram_block11a2.CLR1
+aclr1 => ram_block11a3.CLR1
+aclr1 => ram_block11a4.CLR1
+aclr1 => ram_block11a5.CLR1
+aclr1 => ram_block11a6.CLR1
+aclr1 => ram_block11a7.CLR1
+aclr1 => ram_block11a8.CLR1
+aclr1 => ram_block11a9.CLR1
+aclr1 => ram_block11a10.CLR1
+aclr1 => ram_block11a11.CLR1
+aclr1 => ram_block11a12.CLR1
+aclr1 => ram_block11a13.CLR1
+aclr1 => ram_block11a14.CLR1
+aclr1 => ram_block11a15.CLR1
+address_a[0] => ram_block11a0.PORTAADDR
+address_a[0] => ram_block11a1.PORTAADDR
+address_a[0] => ram_block11a2.PORTAADDR
+address_a[0] => ram_block11a3.PORTAADDR
+address_a[0] => ram_block11a4.PORTAADDR
+address_a[0] => ram_block11a5.PORTAADDR
+address_a[0] => ram_block11a6.PORTAADDR
+address_a[0] => ram_block11a7.PORTAADDR
+address_a[0] => ram_block11a8.PORTAADDR
+address_a[0] => ram_block11a9.PORTAADDR
+address_a[0] => ram_block11a10.PORTAADDR
+address_a[0] => ram_block11a11.PORTAADDR
+address_a[0] => ram_block11a12.PORTAADDR
+address_a[0] => ram_block11a13.PORTAADDR
+address_a[0] => ram_block11a14.PORTAADDR
+address_a[0] => ram_block11a15.PORTAADDR
+address_a[1] => ram_block11a0.PORTAADDR1
+address_a[1] => ram_block11a1.PORTAADDR1
+address_a[1] => ram_block11a2.PORTAADDR1
+address_a[1] => ram_block11a3.PORTAADDR1
+address_a[1] => ram_block11a4.PORTAADDR1
+address_a[1] => ram_block11a5.PORTAADDR1
+address_a[1] => ram_block11a6.PORTAADDR1
+address_a[1] => ram_block11a7.PORTAADDR1
+address_a[1] => ram_block11a8.PORTAADDR1
+address_a[1] => ram_block11a9.PORTAADDR1
+address_a[1] => ram_block11a10.PORTAADDR1
+address_a[1] => ram_block11a11.PORTAADDR1
+address_a[1] => ram_block11a12.PORTAADDR1
+address_a[1] => ram_block11a13.PORTAADDR1
+address_a[1] => ram_block11a14.PORTAADDR1
+address_a[1] => ram_block11a15.PORTAADDR1
+address_a[2] => ram_block11a0.PORTAADDR2
+address_a[2] => ram_block11a1.PORTAADDR2
+address_a[2] => ram_block11a2.PORTAADDR2
+address_a[2] => ram_block11a3.PORTAADDR2
+address_a[2] => ram_block11a4.PORTAADDR2
+address_a[2] => ram_block11a5.PORTAADDR2
+address_a[2] => ram_block11a6.PORTAADDR2
+address_a[2] => ram_block11a7.PORTAADDR2
+address_a[2] => ram_block11a8.PORTAADDR2
+address_a[2] => ram_block11a9.PORTAADDR2
+address_a[2] => ram_block11a10.PORTAADDR2
+address_a[2] => ram_block11a11.PORTAADDR2
+address_a[2] => ram_block11a12.PORTAADDR2
+address_a[2] => ram_block11a13.PORTAADDR2
+address_a[2] => ram_block11a14.PORTAADDR2
+address_a[2] => ram_block11a15.PORTAADDR2
+address_a[3] => ram_block11a0.PORTAADDR3
+address_a[3] => ram_block11a1.PORTAADDR3
+address_a[3] => ram_block11a2.PORTAADDR3
+address_a[3] => ram_block11a3.PORTAADDR3
+address_a[3] => ram_block11a4.PORTAADDR3
+address_a[3] => ram_block11a5.PORTAADDR3
+address_a[3] => ram_block11a6.PORTAADDR3
+address_a[3] => ram_block11a7.PORTAADDR3
+address_a[3] => ram_block11a8.PORTAADDR3
+address_a[3] => ram_block11a9.PORTAADDR3
+address_a[3] => ram_block11a10.PORTAADDR3
+address_a[3] => ram_block11a11.PORTAADDR3
+address_a[3] => ram_block11a12.PORTAADDR3
+address_a[3] => ram_block11a13.PORTAADDR3
+address_a[3] => ram_block11a14.PORTAADDR3
+address_a[3] => ram_block11a15.PORTAADDR3
+address_a[4] => ram_block11a0.PORTAADDR4
+address_a[4] => ram_block11a1.PORTAADDR4
+address_a[4] => ram_block11a2.PORTAADDR4
+address_a[4] => ram_block11a3.PORTAADDR4
+address_a[4] => ram_block11a4.PORTAADDR4
+address_a[4] => ram_block11a5.PORTAADDR4
+address_a[4] => ram_block11a6.PORTAADDR4
+address_a[4] => ram_block11a7.PORTAADDR4
+address_a[4] => ram_block11a8.PORTAADDR4
+address_a[4] => ram_block11a9.PORTAADDR4
+address_a[4] => ram_block11a10.PORTAADDR4
+address_a[4] => ram_block11a11.PORTAADDR4
+address_a[4] => ram_block11a12.PORTAADDR4
+address_a[4] => ram_block11a13.PORTAADDR4
+address_a[4] => ram_block11a14.PORTAADDR4
+address_a[4] => ram_block11a15.PORTAADDR4
+address_a[5] => ram_block11a0.PORTAADDR5
+address_a[5] => ram_block11a1.PORTAADDR5
+address_a[5] => ram_block11a2.PORTAADDR5
+address_a[5] => ram_block11a3.PORTAADDR5
+address_a[5] => ram_block11a4.PORTAADDR5
+address_a[5] => ram_block11a5.PORTAADDR5
+address_a[5] => ram_block11a6.PORTAADDR5
+address_a[5] => ram_block11a7.PORTAADDR5
+address_a[5] => ram_block11a8.PORTAADDR5
+address_a[5] => ram_block11a9.PORTAADDR5
+address_a[5] => ram_block11a10.PORTAADDR5
+address_a[5] => ram_block11a11.PORTAADDR5
+address_a[5] => ram_block11a12.PORTAADDR5
+address_a[5] => ram_block11a13.PORTAADDR5
+address_a[5] => ram_block11a14.PORTAADDR5
+address_a[5] => ram_block11a15.PORTAADDR5
+address_a[6] => ram_block11a0.PORTAADDR6
+address_a[6] => ram_block11a1.PORTAADDR6
+address_a[6] => ram_block11a2.PORTAADDR6
+address_a[6] => ram_block11a3.PORTAADDR6
+address_a[6] => ram_block11a4.PORTAADDR6
+address_a[6] => ram_block11a5.PORTAADDR6
+address_a[6] => ram_block11a6.PORTAADDR6
+address_a[6] => ram_block11a7.PORTAADDR6
+address_a[6] => ram_block11a8.PORTAADDR6
+address_a[6] => ram_block11a9.PORTAADDR6
+address_a[6] => ram_block11a10.PORTAADDR6
+address_a[6] => ram_block11a11.PORTAADDR6
+address_a[6] => ram_block11a12.PORTAADDR6
+address_a[6] => ram_block11a13.PORTAADDR6
+address_a[6] => ram_block11a14.PORTAADDR6
+address_a[6] => ram_block11a15.PORTAADDR6
+address_a[7] => ram_block11a0.PORTAADDR7
+address_a[7] => ram_block11a1.PORTAADDR7
+address_a[7] => ram_block11a2.PORTAADDR7
+address_a[7] => ram_block11a3.PORTAADDR7
+address_a[7] => ram_block11a4.PORTAADDR7
+address_a[7] => ram_block11a5.PORTAADDR7
+address_a[7] => ram_block11a6.PORTAADDR7
+address_a[7] => ram_block11a7.PORTAADDR7
+address_a[7] => ram_block11a8.PORTAADDR7
+address_a[7] => ram_block11a9.PORTAADDR7
+address_a[7] => ram_block11a10.PORTAADDR7
+address_a[7] => ram_block11a11.PORTAADDR7
+address_a[7] => ram_block11a12.PORTAADDR7
+address_a[7] => ram_block11a13.PORTAADDR7
+address_a[7] => ram_block11a14.PORTAADDR7
+address_a[7] => ram_block11a15.PORTAADDR7
+address_a[8] => ram_block11a0.PORTAADDR8
+address_a[8] => ram_block11a1.PORTAADDR8
+address_a[8] => ram_block11a2.PORTAADDR8
+address_a[8] => ram_block11a3.PORTAADDR8
+address_a[8] => ram_block11a4.PORTAADDR8
+address_a[8] => ram_block11a5.PORTAADDR8
+address_a[8] => ram_block11a6.PORTAADDR8
+address_a[8] => ram_block11a7.PORTAADDR8
+address_a[8] => ram_block11a8.PORTAADDR8
+address_a[8] => ram_block11a9.PORTAADDR8
+address_a[8] => ram_block11a10.PORTAADDR8
+address_a[8] => ram_block11a11.PORTAADDR8
+address_a[8] => ram_block11a12.PORTAADDR8
+address_a[8] => ram_block11a13.PORTAADDR8
+address_a[8] => ram_block11a14.PORTAADDR8
+address_a[8] => ram_block11a15.PORTAADDR8
+address_b[0] => ram_block11a0.PORTBADDR
+address_b[0] => ram_block11a1.PORTBADDR
+address_b[0] => ram_block11a2.PORTBADDR
+address_b[0] => ram_block11a3.PORTBADDR
+address_b[0] => ram_block11a4.PORTBADDR
+address_b[0] => ram_block11a5.PORTBADDR
+address_b[0] => ram_block11a6.PORTBADDR
+address_b[0] => ram_block11a7.PORTBADDR
+address_b[0] => ram_block11a8.PORTBADDR
+address_b[0] => ram_block11a9.PORTBADDR
+address_b[0] => ram_block11a10.PORTBADDR
+address_b[0] => ram_block11a11.PORTBADDR
+address_b[0] => ram_block11a12.PORTBADDR
+address_b[0] => ram_block11a13.PORTBADDR
+address_b[0] => ram_block11a14.PORTBADDR
+address_b[0] => ram_block11a15.PORTBADDR
+address_b[1] => ram_block11a0.PORTBADDR1
+address_b[1] => ram_block11a1.PORTBADDR1
+address_b[1] => ram_block11a2.PORTBADDR1
+address_b[1] => ram_block11a3.PORTBADDR1
+address_b[1] => ram_block11a4.PORTBADDR1
+address_b[1] => ram_block11a5.PORTBADDR1
+address_b[1] => ram_block11a6.PORTBADDR1
+address_b[1] => ram_block11a7.PORTBADDR1
+address_b[1] => ram_block11a8.PORTBADDR1
+address_b[1] => ram_block11a9.PORTBADDR1
+address_b[1] => ram_block11a10.PORTBADDR1
+address_b[1] => ram_block11a11.PORTBADDR1
+address_b[1] => ram_block11a12.PORTBADDR1
+address_b[1] => ram_block11a13.PORTBADDR1
+address_b[1] => ram_block11a14.PORTBADDR1
+address_b[1] => ram_block11a15.PORTBADDR1
+address_b[2] => ram_block11a0.PORTBADDR2
+address_b[2] => ram_block11a1.PORTBADDR2
+address_b[2] => ram_block11a2.PORTBADDR2
+address_b[2] => ram_block11a3.PORTBADDR2
+address_b[2] => ram_block11a4.PORTBADDR2
+address_b[2] => ram_block11a5.PORTBADDR2
+address_b[2] => ram_block11a6.PORTBADDR2
+address_b[2] => ram_block11a7.PORTBADDR2
+address_b[2] => ram_block11a8.PORTBADDR2
+address_b[2] => ram_block11a9.PORTBADDR2
+address_b[2] => ram_block11a10.PORTBADDR2
+address_b[2] => ram_block11a11.PORTBADDR2
+address_b[2] => ram_block11a12.PORTBADDR2
+address_b[2] => ram_block11a13.PORTBADDR2
+address_b[2] => ram_block11a14.PORTBADDR2
+address_b[2] => ram_block11a15.PORTBADDR2
+address_b[3] => ram_block11a0.PORTBADDR3
+address_b[3] => ram_block11a1.PORTBADDR3
+address_b[3] => ram_block11a2.PORTBADDR3
+address_b[3] => ram_block11a3.PORTBADDR3
+address_b[3] => ram_block11a4.PORTBADDR3
+address_b[3] => ram_block11a5.PORTBADDR3
+address_b[3] => ram_block11a6.PORTBADDR3
+address_b[3] => ram_block11a7.PORTBADDR3
+address_b[3] => ram_block11a8.PORTBADDR3
+address_b[3] => ram_block11a9.PORTBADDR3
+address_b[3] => ram_block11a10.PORTBADDR3
+address_b[3] => ram_block11a11.PORTBADDR3
+address_b[3] => ram_block11a12.PORTBADDR3
+address_b[3] => ram_block11a13.PORTBADDR3
+address_b[3] => ram_block11a14.PORTBADDR3
+address_b[3] => ram_block11a15.PORTBADDR3
+address_b[4] => ram_block11a0.PORTBADDR4
+address_b[4] => ram_block11a1.PORTBADDR4
+address_b[4] => ram_block11a2.PORTBADDR4
+address_b[4] => ram_block11a3.PORTBADDR4
+address_b[4] => ram_block11a4.PORTBADDR4
+address_b[4] => ram_block11a5.PORTBADDR4
+address_b[4] => ram_block11a6.PORTBADDR4
+address_b[4] => ram_block11a7.PORTBADDR4
+address_b[4] => ram_block11a8.PORTBADDR4
+address_b[4] => ram_block11a9.PORTBADDR4
+address_b[4] => ram_block11a10.PORTBADDR4
+address_b[4] => ram_block11a11.PORTBADDR4
+address_b[4] => ram_block11a12.PORTBADDR4
+address_b[4] => ram_block11a13.PORTBADDR4
+address_b[4] => ram_block11a14.PORTBADDR4
+address_b[4] => ram_block11a15.PORTBADDR4
+address_b[5] => ram_block11a0.PORTBADDR5
+address_b[5] => ram_block11a1.PORTBADDR5
+address_b[5] => ram_block11a2.PORTBADDR5
+address_b[5] => ram_block11a3.PORTBADDR5
+address_b[5] => ram_block11a4.PORTBADDR5
+address_b[5] => ram_block11a5.PORTBADDR5
+address_b[5] => ram_block11a6.PORTBADDR5
+address_b[5] => ram_block11a7.PORTBADDR5
+address_b[5] => ram_block11a8.PORTBADDR5
+address_b[5] => ram_block11a9.PORTBADDR5
+address_b[5] => ram_block11a10.PORTBADDR5
+address_b[5] => ram_block11a11.PORTBADDR5
+address_b[5] => ram_block11a12.PORTBADDR5
+address_b[5] => ram_block11a13.PORTBADDR5
+address_b[5] => ram_block11a14.PORTBADDR5
+address_b[5] => ram_block11a15.PORTBADDR5
+address_b[6] => ram_block11a0.PORTBADDR6
+address_b[6] => ram_block11a1.PORTBADDR6
+address_b[6] => ram_block11a2.PORTBADDR6
+address_b[6] => ram_block11a3.PORTBADDR6
+address_b[6] => ram_block11a4.PORTBADDR6
+address_b[6] => ram_block11a5.PORTBADDR6
+address_b[6] => ram_block11a6.PORTBADDR6
+address_b[6] => ram_block11a7.PORTBADDR6
+address_b[6] => ram_block11a8.PORTBADDR6
+address_b[6] => ram_block11a9.PORTBADDR6
+address_b[6] => ram_block11a10.PORTBADDR6
+address_b[6] => ram_block11a11.PORTBADDR6
+address_b[6] => ram_block11a12.PORTBADDR6
+address_b[6] => ram_block11a13.PORTBADDR6
+address_b[6] => ram_block11a14.PORTBADDR6
+address_b[6] => ram_block11a15.PORTBADDR6
+address_b[7] => ram_block11a0.PORTBADDR7
+address_b[7] => ram_block11a1.PORTBADDR7
+address_b[7] => ram_block11a2.PORTBADDR7
+address_b[7] => ram_block11a3.PORTBADDR7
+address_b[7] => ram_block11a4.PORTBADDR7
+address_b[7] => ram_block11a5.PORTBADDR7
+address_b[7] => ram_block11a6.PORTBADDR7
+address_b[7] => ram_block11a7.PORTBADDR7
+address_b[7] => ram_block11a8.PORTBADDR7
+address_b[7] => ram_block11a9.PORTBADDR7
+address_b[7] => ram_block11a10.PORTBADDR7
+address_b[7] => ram_block11a11.PORTBADDR7
+address_b[7] => ram_block11a12.PORTBADDR7
+address_b[7] => ram_block11a13.PORTBADDR7
+address_b[7] => ram_block11a14.PORTBADDR7
+address_b[7] => ram_block11a15.PORTBADDR7
+address_b[8] => ram_block11a0.PORTBADDR8
+address_b[8] => ram_block11a1.PORTBADDR8
+address_b[8] => ram_block11a2.PORTBADDR8
+address_b[8] => ram_block11a3.PORTBADDR8
+address_b[8] => ram_block11a4.PORTBADDR8
+address_b[8] => ram_block11a5.PORTBADDR8
+address_b[8] => ram_block11a6.PORTBADDR8
+address_b[8] => ram_block11a7.PORTBADDR8
+address_b[8] => ram_block11a8.PORTBADDR8
+address_b[8] => ram_block11a9.PORTBADDR8
+address_b[8] => ram_block11a10.PORTBADDR8
+address_b[8] => ram_block11a11.PORTBADDR8
+address_b[8] => ram_block11a12.PORTBADDR8
+address_b[8] => ram_block11a13.PORTBADDR8
+address_b[8] => ram_block11a14.PORTBADDR8
+address_b[8] => ram_block11a15.PORTBADDR8
+addressstall_b => ram_block11a0.PORTBADDRSTALL
+addressstall_b => ram_block11a1.PORTBADDRSTALL
+addressstall_b => ram_block11a2.PORTBADDRSTALL
+addressstall_b => ram_block11a3.PORTBADDRSTALL
+addressstall_b => ram_block11a4.PORTBADDRSTALL
+addressstall_b => ram_block11a5.PORTBADDRSTALL
+addressstall_b => ram_block11a6.PORTBADDRSTALL
+addressstall_b => ram_block11a7.PORTBADDRSTALL
+addressstall_b => ram_block11a8.PORTBADDRSTALL
+addressstall_b => ram_block11a9.PORTBADDRSTALL
+addressstall_b => ram_block11a10.PORTBADDRSTALL
+addressstall_b => ram_block11a11.PORTBADDRSTALL
+addressstall_b => ram_block11a12.PORTBADDRSTALL
+addressstall_b => ram_block11a13.PORTBADDRSTALL
+addressstall_b => ram_block11a14.PORTBADDRSTALL
+addressstall_b => ram_block11a15.PORTBADDRSTALL
+clock0 => ram_block11a0.CLK0
+clock0 => ram_block11a1.CLK0
+clock0 => ram_block11a2.CLK0
+clock0 => ram_block11a3.CLK0
+clock0 => ram_block11a4.CLK0
+clock0 => ram_block11a5.CLK0
+clock0 => ram_block11a6.CLK0
+clock0 => ram_block11a7.CLK0
+clock0 => ram_block11a8.CLK0
+clock0 => ram_block11a9.CLK0
+clock0 => ram_block11a10.CLK0
+clock0 => ram_block11a11.CLK0
+clock0 => ram_block11a12.CLK0
+clock0 => ram_block11a13.CLK0
+clock0 => ram_block11a14.CLK0
+clock0 => ram_block11a15.CLK0
+clock1 => ram_block11a0.CLK1
+clock1 => ram_block11a1.CLK1
+clock1 => ram_block11a2.CLK1
+clock1 => ram_block11a3.CLK1
+clock1 => ram_block11a4.CLK1
+clock1 => ram_block11a5.CLK1
+clock1 => ram_block11a6.CLK1
+clock1 => ram_block11a7.CLK1
+clock1 => ram_block11a8.CLK1
+clock1 => ram_block11a9.CLK1
+clock1 => ram_block11a10.CLK1
+clock1 => ram_block11a11.CLK1
+clock1 => ram_block11a12.CLK1
+clock1 => ram_block11a13.CLK1
+clock1 => ram_block11a14.CLK1
+clock1 => ram_block11a15.CLK1
+clocken1 => ram_block11a0.ENA1
+clocken1 => ram_block11a1.ENA1
+clocken1 => ram_block11a2.ENA1
+clocken1 => ram_block11a3.ENA1
+clocken1 => ram_block11a4.ENA1
+clocken1 => ram_block11a5.ENA1
+clocken1 => ram_block11a6.ENA1
+clocken1 => ram_block11a7.ENA1
+clocken1 => ram_block11a8.ENA1
+clocken1 => ram_block11a9.ENA1
+clocken1 => ram_block11a10.ENA1
+clocken1 => ram_block11a11.ENA1
+clocken1 => ram_block11a12.ENA1
+clocken1 => ram_block11a13.ENA1
+clocken1 => ram_block11a14.ENA1
+clocken1 => ram_block11a15.ENA1
+data_a[0] => ram_block11a0.PORTADATAIN
+data_a[1] => ram_block11a1.PORTADATAIN
+data_a[2] => ram_block11a2.PORTADATAIN
+data_a[3] => ram_block11a3.PORTADATAIN
+data_a[4] => ram_block11a4.PORTADATAIN
+data_a[5] => ram_block11a5.PORTADATAIN
+data_a[6] => ram_block11a6.PORTADATAIN
+data_a[7] => ram_block11a7.PORTADATAIN
+data_a[8] => ram_block11a8.PORTADATAIN
+data_a[9] => ram_block11a9.PORTADATAIN
+data_a[10] => ram_block11a10.PORTADATAIN
+data_a[11] => ram_block11a11.PORTADATAIN
+data_a[12] => ram_block11a12.PORTADATAIN
+data_a[13] => ram_block11a13.PORTADATAIN
+data_a[14] => ram_block11a14.PORTADATAIN
+data_a[15] => ram_block11a15.PORTADATAIN
+q_b[0] <= ram_block11a0.PORTBDATAOUT
+q_b[1] <= ram_block11a1.PORTBDATAOUT
+q_b[2] <= ram_block11a2.PORTBDATAOUT
+q_b[3] <= ram_block11a3.PORTBDATAOUT
+q_b[4] <= ram_block11a4.PORTBDATAOUT
+q_b[5] <= ram_block11a5.PORTBDATAOUT
+q_b[6] <= ram_block11a6.PORTBDATAOUT
+q_b[7] <= ram_block11a7.PORTBDATAOUT
+q_b[8] <= ram_block11a8.PORTBDATAOUT
+q_b[9] <= ram_block11a9.PORTBDATAOUT
+q_b[10] <= ram_block11a10.PORTBDATAOUT
+q_b[11] <= ram_block11a11.PORTBDATAOUT
+q_b[12] <= ram_block11a12.PORTBDATAOUT
+q_b[13] <= ram_block11a13.PORTBDATAOUT
+q_b[14] <= ram_block11a14.PORTBDATAOUT
+q_b[15] <= ram_block11a15.PORTBDATAOUT
+wren_a => ram_block11a0.PORTAWE
+wren_a => ram_block11a0.ENA0
+wren_a => ram_block11a1.PORTAWE
+wren_a => ram_block11a1.ENA0
+wren_a => ram_block11a2.PORTAWE
+wren_a => ram_block11a2.ENA0
+wren_a => ram_block11a3.PORTAWE
+wren_a => ram_block11a3.ENA0
+wren_a => ram_block11a4.PORTAWE
+wren_a => ram_block11a4.ENA0
+wren_a => ram_block11a5.PORTAWE
+wren_a => ram_block11a5.ENA0
+wren_a => ram_block11a6.PORTAWE
+wren_a => ram_block11a6.ENA0
+wren_a => ram_block11a7.PORTAWE
+wren_a => ram_block11a7.ENA0
+wren_a => ram_block11a8.PORTAWE
+wren_a => ram_block11a8.ENA0
+wren_a => ram_block11a9.PORTAWE
+wren_a => ram_block11a9.ENA0
+wren_a => ram_block11a10.PORTAWE
+wren_a => ram_block11a10.ENA0
+wren_a => ram_block11a11.PORTAWE
+wren_a => ram_block11a11.ENA0
+wren_a => ram_block11a12.PORTAWE
+wren_a => ram_block11a12.ENA0
+wren_a => ram_block11a13.PORTAWE
+wren_a => ram_block11a13.ENA0
+wren_a => ram_block11a14.PORTAWE
+wren_a => ram_block11a14.ENA0
+wren_a => ram_block11a15.PORTAWE
+wren_a => ram_block11a15.ENA0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+clock => dffpipe_pe9:dffpipe13.clock
+clrn => dffpipe_pe9:dffpipe13.clrn
+d[0] => dffpipe_pe9:dffpipe13.d[0]
+d[1] => dffpipe_pe9:dffpipe13.d[1]
+d[2] => dffpipe_pe9:dffpipe13.d[2]
+d[3] => dffpipe_pe9:dffpipe13.d[3]
+d[4] => dffpipe_pe9:dffpipe13.d[4]
+d[5] => dffpipe_pe9:dffpipe13.d[5]
+d[6] => dffpipe_pe9:dffpipe13.d[6]
+d[7] => dffpipe_pe9:dffpipe13.d[7]
+d[8] => dffpipe_pe9:dffpipe13.d[8]
+d[9] => dffpipe_pe9:dffpipe13.d[9]
+q[0] <= dffpipe_pe9:dffpipe13.q[0]
+q[1] <= dffpipe_pe9:dffpipe13.q[1]
+q[2] <= dffpipe_pe9:dffpipe13.q[2]
+q[3] <= dffpipe_pe9:dffpipe13.q[3]
+q[4] <= dffpipe_pe9:dffpipe13.q[4]
+q[5] <= dffpipe_pe9:dffpipe13.q[5]
+q[6] <= dffpipe_pe9:dffpipe13.q[6]
+q[7] <= dffpipe_pe9:dffpipe13.q[7]
+q[8] <= dffpipe_pe9:dffpipe13.q[8]
+q[9] <= dffpipe_pe9:dffpipe13.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+clock => dffe14a[9].CLK
+clock => dffe14a[8].CLK
+clock => dffe14a[7].CLK
+clock => dffe14a[6].CLK
+clock => dffe14a[5].CLK
+clock => dffe14a[4].CLK
+clock => dffe14a[3].CLK
+clock => dffe14a[2].CLK
+clock => dffe14a[1].CLK
+clock => dffe14a[0].CLK
+clock => dffe15a[9].CLK
+clock => dffe15a[8].CLK
+clock => dffe15a[7].CLK
+clock => dffe15a[6].CLK
+clock => dffe15a[5].CLK
+clock => dffe15a[4].CLK
+clock => dffe15a[3].CLK
+clock => dffe15a[2].CLK
+clock => dffe15a[1].CLK
+clock => dffe15a[0].CLK
+clrn => dffe14a[9].ACLR
+clrn => dffe14a[8].ACLR
+clrn => dffe14a[7].ACLR
+clrn => dffe14a[6].ACLR
+clrn => dffe14a[5].ACLR
+clrn => dffe14a[4].ACLR
+clrn => dffe14a[3].ACLR
+clrn => dffe14a[2].ACLR
+clrn => dffe14a[1].ACLR
+clrn => dffe14a[0].ACLR
+clrn => dffe15a[9].ACLR
+clrn => dffe15a[8].ACLR
+clrn => dffe15a[7].ACLR
+clrn => dffe15a[6].ACLR
+clrn => dffe15a[5].ACLR
+clrn => dffe15a[4].ACLR
+clrn => dffe15a[3].ACLR
+clrn => dffe15a[2].ACLR
+clrn => dffe15a[1].ACLR
+clrn => dffe15a[0].ACLR
+d[0] => dffe14a[0].IN0
+d[1] => dffe14a[1].IN0
+d[2] => dffe14a[2].IN0
+d[3] => dffe14a[3].IN0
+d[4] => dffe14a[4].IN0
+d[5] => dffe14a[5].IN0
+d[6] => dffe14a[6].IN0
+d[7] => dffe14a[7].IN0
+d[8] => dffe14a[8].IN0
+d[9] => dffe14a[9].IN0
+q[0] <= dffe15a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe15a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe15a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe15a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe15a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe15a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe15a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe15a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe15a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe15a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+clock => dffpipe_qe9:dffpipe16.clock
+clrn => dffpipe_qe9:dffpipe16.clrn
+d[0] => dffpipe_qe9:dffpipe16.d[0]
+d[1] => dffpipe_qe9:dffpipe16.d[1]
+d[2] => dffpipe_qe9:dffpipe16.d[2]
+d[3] => dffpipe_qe9:dffpipe16.d[3]
+d[4] => dffpipe_qe9:dffpipe16.d[4]
+d[5] => dffpipe_qe9:dffpipe16.d[5]
+d[6] => dffpipe_qe9:dffpipe16.d[6]
+d[7] => dffpipe_qe9:dffpipe16.d[7]
+d[8] => dffpipe_qe9:dffpipe16.d[8]
+d[9] => dffpipe_qe9:dffpipe16.d[9]
+q[0] <= dffpipe_qe9:dffpipe16.q[0]
+q[1] <= dffpipe_qe9:dffpipe16.q[1]
+q[2] <= dffpipe_qe9:dffpipe16.q[2]
+q[3] <= dffpipe_qe9:dffpipe16.q[3]
+q[4] <= dffpipe_qe9:dffpipe16.q[4]
+q[5] <= dffpipe_qe9:dffpipe16.q[5]
+q[6] <= dffpipe_qe9:dffpipe16.q[6]
+q[7] <= dffpipe_qe9:dffpipe16.q[7]
+q[8] <= dffpipe_qe9:dffpipe16.q[8]
+q[9] <= dffpipe_qe9:dffpipe16.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+clock => dffe17a[9].CLK
+clock => dffe17a[8].CLK
+clock => dffe17a[7].CLK
+clock => dffe17a[6].CLK
+clock => dffe17a[5].CLK
+clock => dffe17a[4].CLK
+clock => dffe17a[3].CLK
+clock => dffe17a[2].CLK
+clock => dffe17a[1].CLK
+clock => dffe17a[0].CLK
+clock => dffe18a[9].CLK
+clock => dffe18a[8].CLK
+clock => dffe18a[7].CLK
+clock => dffe18a[6].CLK
+clock => dffe18a[5].CLK
+clock => dffe18a[4].CLK
+clock => dffe18a[3].CLK
+clock => dffe18a[2].CLK
+clock => dffe18a[1].CLK
+clock => dffe18a[0].CLK
+clrn => dffe17a[9].ACLR
+clrn => dffe17a[8].ACLR
+clrn => dffe17a[7].ACLR
+clrn => dffe17a[6].ACLR
+clrn => dffe17a[5].ACLR
+clrn => dffe17a[4].ACLR
+clrn => dffe17a[3].ACLR
+clrn => dffe17a[2].ACLR
+clrn => dffe17a[1].ACLR
+clrn => dffe17a[0].ACLR
+clrn => dffe18a[9].ACLR
+clrn => dffe18a[8].ACLR
+clrn => dffe18a[7].ACLR
+clrn => dffe18a[6].ACLR
+clrn => dffe18a[5].ACLR
+clrn => dffe18a[4].ACLR
+clrn => dffe18a[3].ACLR
+clrn => dffe18a[2].ACLR
+clrn => dffe18a[1].ACLR
+clrn => dffe18a[0].ACLR
+d[0] => dffe17a[0].IN0
+d[1] => dffe17a[1].IN0
+d[2] => dffe17a[2].IN0
+d[3] => dffe17a[3].IN0
+d[4] => dffe17a[4].IN0
+d[5] => dffe17a[5].IN0
+d[6] => dffe17a[6].IN0
+d[7] => dffe17a[7].IN0
+d[8] => dffe17a[8].IN0
+d[9] => dffe17a[9].IN0
+q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1
+aclr => aclr.IN1
+data[0] => data[0].IN1
+data[1] => data[1].IN1
+data[2] => data[2].IN1
+data[3] => data[3].IN1
+data[4] => data[4].IN1
+data[5] => data[5].IN1
+data[6] => data[6].IN1
+data[7] => data[7].IN1
+data[8] => data[8].IN1
+data[9] => data[9].IN1
+data[10] => data[10].IN1
+data[11] => data[11].IN1
+data[12] => data[12].IN1
+data[13] => data[13].IN1
+data[14] => data[14].IN1
+data[15] => data[15].IN1
+rdclk => rdclk.IN1
+rdreq => rdreq.IN1
+wrclk => wrclk.IN1
+wrreq => wrreq.IN1
+q[0] <= dcfifo:dcfifo_component.q
+q[1] <= dcfifo:dcfifo_component.q
+q[2] <= dcfifo:dcfifo_component.q
+q[3] <= dcfifo:dcfifo_component.q
+q[4] <= dcfifo:dcfifo_component.q
+q[5] <= dcfifo:dcfifo_component.q
+q[6] <= dcfifo:dcfifo_component.q
+q[7] <= dcfifo:dcfifo_component.q
+q[8] <= dcfifo:dcfifo_component.q
+q[9] <= dcfifo:dcfifo_component.q
+q[10] <= dcfifo:dcfifo_component.q
+q[11] <= dcfifo:dcfifo_component.q
+q[12] <= dcfifo:dcfifo_component.q
+q[13] <= dcfifo:dcfifo_component.q
+q[14] <= dcfifo:dcfifo_component.q
+q[15] <= dcfifo:dcfifo_component.q
+rdempty <= dcfifo:dcfifo_component.rdempty
+rdusedw[0] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[1] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[2] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[3] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[4] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[5] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[6] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[7] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[8] <= dcfifo:dcfifo_component.rdusedw
+wrfull <= dcfifo:dcfifo_component.wrfull
+wrusedw[0] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[1] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[2] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[3] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[4] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[5] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[6] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[7] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[8] <= dcfifo:dcfifo_component.wrusedw
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+data[0] => dcfifo_v5o1:auto_generated.data[0]
+data[1] => dcfifo_v5o1:auto_generated.data[1]
+data[2] => dcfifo_v5o1:auto_generated.data[2]
+data[3] => dcfifo_v5o1:auto_generated.data[3]
+data[4] => dcfifo_v5o1:auto_generated.data[4]
+data[5] => dcfifo_v5o1:auto_generated.data[5]
+data[6] => dcfifo_v5o1:auto_generated.data[6]
+data[7] => dcfifo_v5o1:auto_generated.data[7]
+data[8] => dcfifo_v5o1:auto_generated.data[8]
+data[9] => dcfifo_v5o1:auto_generated.data[9]
+data[10] => dcfifo_v5o1:auto_generated.data[10]
+data[11] => dcfifo_v5o1:auto_generated.data[11]
+data[12] => dcfifo_v5o1:auto_generated.data[12]
+data[13] => dcfifo_v5o1:auto_generated.data[13]
+data[14] => dcfifo_v5o1:auto_generated.data[14]
+data[15] => dcfifo_v5o1:auto_generated.data[15]
+q[0] <= dcfifo_v5o1:auto_generated.q[0]
+q[1] <= dcfifo_v5o1:auto_generated.q[1]
+q[2] <= dcfifo_v5o1:auto_generated.q[2]
+q[3] <= dcfifo_v5o1:auto_generated.q[3]
+q[4] <= dcfifo_v5o1:auto_generated.q[4]
+q[5] <= dcfifo_v5o1:auto_generated.q[5]
+q[6] <= dcfifo_v5o1:auto_generated.q[6]
+q[7] <= dcfifo_v5o1:auto_generated.q[7]
+q[8] <= dcfifo_v5o1:auto_generated.q[8]
+q[9] <= dcfifo_v5o1:auto_generated.q[9]
+q[10] <= dcfifo_v5o1:auto_generated.q[10]
+q[11] <= dcfifo_v5o1:auto_generated.q[11]
+q[12] <= dcfifo_v5o1:auto_generated.q[12]
+q[13] <= dcfifo_v5o1:auto_generated.q[13]
+q[14] <= dcfifo_v5o1:auto_generated.q[14]
+q[15] <= dcfifo_v5o1:auto_generated.q[15]
+rdclk => dcfifo_v5o1:auto_generated.rdclk
+rdreq => dcfifo_v5o1:auto_generated.rdreq
+wrclk => dcfifo_v5o1:auto_generated.wrclk
+wrreq => dcfifo_v5o1:auto_generated.wrreq
+aclr => dcfifo_v5o1:auto_generated.aclr
+rdempty <= dcfifo_v5o1:auto_generated.rdempty
+rdfull <= <UNC>
+wrempty <= <GND>
+wrfull <= dcfifo_v5o1:auto_generated.wrfull
+rdusedw[0] <= dcfifo_v5o1:auto_generated.rdusedw[0]
+rdusedw[1] <= dcfifo_v5o1:auto_generated.rdusedw[1]
+rdusedw[2] <= dcfifo_v5o1:auto_generated.rdusedw[2]
+rdusedw[3] <= dcfifo_v5o1:auto_generated.rdusedw[3]
+rdusedw[4] <= dcfifo_v5o1:auto_generated.rdusedw[4]
+rdusedw[5] <= dcfifo_v5o1:auto_generated.rdusedw[5]
+rdusedw[6] <= dcfifo_v5o1:auto_generated.rdusedw[6]
+rdusedw[7] <= dcfifo_v5o1:auto_generated.rdusedw[7]
+rdusedw[8] <= dcfifo_v5o1:auto_generated.rdusedw[8]
+wrusedw[0] <= dcfifo_v5o1:auto_generated.wrusedw[0]
+wrusedw[1] <= dcfifo_v5o1:auto_generated.wrusedw[1]
+wrusedw[2] <= dcfifo_v5o1:auto_generated.wrusedw[2]
+wrusedw[3] <= dcfifo_v5o1:auto_generated.wrusedw[3]
+wrusedw[4] <= dcfifo_v5o1:auto_generated.wrusedw[4]
+wrusedw[5] <= dcfifo_v5o1:auto_generated.wrusedw[5]
+wrusedw[6] <= dcfifo_v5o1:auto_generated.wrusedw[6]
+wrusedw[7] <= dcfifo_v5o1:auto_generated.wrusedw[7]
+wrusedw[8] <= dcfifo_v5o1:auto_generated.wrusedw[8]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+aclr => a_graycounter_s57:rdptr_g1p.aclr
+aclr => a_graycounter_ojc:wrptr_g1p.aclr
+aclr => altsyncram_de51:fifo_ram.aclr1
+aclr => delayed_wrptr_g[9].IN0
+aclr => rdptr_g[9].IN0
+aclr => wrptr_g[9].IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+data[0] => altsyncram_de51:fifo_ram.data_a[0]
+data[1] => altsyncram_de51:fifo_ram.data_a[1]
+data[2] => altsyncram_de51:fifo_ram.data_a[2]
+data[3] => altsyncram_de51:fifo_ram.data_a[3]
+data[4] => altsyncram_de51:fifo_ram.data_a[4]
+data[5] => altsyncram_de51:fifo_ram.data_a[5]
+data[6] => altsyncram_de51:fifo_ram.data_a[6]
+data[7] => altsyncram_de51:fifo_ram.data_a[7]
+data[8] => altsyncram_de51:fifo_ram.data_a[8]
+data[9] => altsyncram_de51:fifo_ram.data_a[9]
+data[10] => altsyncram_de51:fifo_ram.data_a[10]
+data[11] => altsyncram_de51:fifo_ram.data_a[11]
+data[12] => altsyncram_de51:fifo_ram.data_a[12]
+data[13] => altsyncram_de51:fifo_ram.data_a[13]
+data[14] => altsyncram_de51:fifo_ram.data_a[14]
+data[15] => altsyncram_de51:fifo_ram.data_a[15]
+q[0] <= altsyncram_de51:fifo_ram.q_b[0]
+q[1] <= altsyncram_de51:fifo_ram.q_b[1]
+q[2] <= altsyncram_de51:fifo_ram.q_b[2]
+q[3] <= altsyncram_de51:fifo_ram.q_b[3]
+q[4] <= altsyncram_de51:fifo_ram.q_b[4]
+q[5] <= altsyncram_de51:fifo_ram.q_b[5]
+q[6] <= altsyncram_de51:fifo_ram.q_b[6]
+q[7] <= altsyncram_de51:fifo_ram.q_b[7]
+q[8] <= altsyncram_de51:fifo_ram.q_b[8]
+q[9] <= altsyncram_de51:fifo_ram.q_b[9]
+q[10] <= altsyncram_de51:fifo_ram.q_b[10]
+q[11] <= altsyncram_de51:fifo_ram.q_b[11]
+q[12] <= altsyncram_de51:fifo_ram.q_b[12]
+q[13] <= altsyncram_de51:fifo_ram.q_b[13]
+q[14] <= altsyncram_de51:fifo_ram.q_b[14]
+q[15] <= altsyncram_de51:fifo_ram.q_b[15]
+rdclk => a_graycounter_s57:rdptr_g1p.clock
+rdclk => altsyncram_de51:fifo_ram.clock1
+rdclk => dffpipe_oe9:rs_brp.clock
+rdclk => dffpipe_oe9:rs_bwp.clock
+rdclk => alt_synch_pipe_qld:rs_dgwp.clock
+rdclk => rdptr_g[9].CLK
+rdclk => rdptr_g[8].CLK
+rdclk => rdptr_g[7].CLK
+rdclk => rdptr_g[6].CLK
+rdclk => rdptr_g[5].CLK
+rdclk => rdptr_g[4].CLK
+rdclk => rdptr_g[3].CLK
+rdclk => rdptr_g[2].CLK
+rdclk => rdptr_g[1].CLK
+rdclk => rdptr_g[0].CLK
+rdempty <= int_rdempty.DB_MAX_OUTPUT_PORT_TYPE
+rdreq => valid_rdreq.IN0
+rdusedw[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+wrclk => a_graycounter_ojc:wrptr_g1p.clock
+wrclk => altsyncram_de51:fifo_ram.clock0
+wrclk => dffpipe_oe9:ws_brp.clock
+wrclk => dffpipe_oe9:ws_bwp.clock
+wrclk => alt_synch_pipe_rld:ws_dgrp.clock
+wrclk => delayed_wrptr_g[9].CLK
+wrclk => delayed_wrptr_g[8].CLK
+wrclk => delayed_wrptr_g[7].CLK
+wrclk => delayed_wrptr_g[6].CLK
+wrclk => delayed_wrptr_g[5].CLK
+wrclk => delayed_wrptr_g[4].CLK
+wrclk => delayed_wrptr_g[3].CLK
+wrclk => delayed_wrptr_g[2].CLK
+wrclk => delayed_wrptr_g[1].CLK
+wrclk => delayed_wrptr_g[0].CLK
+wrclk => wrptr_g[9].CLK
+wrclk => wrptr_g[8].CLK
+wrclk => wrptr_g[7].CLK
+wrclk => wrptr_g[6].CLK
+wrclk => wrptr_g[5].CLK
+wrclk => wrptr_g[4].CLK
+wrclk => wrptr_g[3].CLK
+wrclk => wrptr_g[2].CLK
+wrclk => wrptr_g[1].CLK
+wrclk => wrptr_g[0].CLK
+wrfull <= int_wrfull.DB_MAX_OUTPUT_PORT_TYPE
+wrreq => valid_wrreq.IN0
+wrusedw[0] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[1] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[2] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[3] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[4] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[5] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[6] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[7] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[8] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+aclr => counter5a1.IN0
+aclr => counter5a0.IN0
+aclr => parity6.IN0
+aclr => sub_parity7a[2].IN0
+aclr => sub_parity7a[1].IN0
+aclr => sub_parity7a[0].IN0
+clock => counter5a0.CLK
+clock => counter5a1.CLK
+clock => counter5a2.CLK
+clock => counter5a3.CLK
+clock => counter5a4.CLK
+clock => counter5a5.CLK
+clock => counter5a6.CLK
+clock => counter5a7.CLK
+clock => counter5a8.CLK
+clock => counter5a9.CLK
+clock => parity6.CLK
+clock => sub_parity7a[2].CLK
+clock => sub_parity7a[1].CLK
+clock => sub_parity7a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter5a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter5a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter5a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter5a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter5a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter5a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter5a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter5a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter5a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter5a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+aclr => counter8a1.IN0
+aclr => counter8a0.IN0
+aclr => parity9.IN0
+aclr => sub_parity10a[2].IN0
+aclr => sub_parity10a[1].IN0
+aclr => sub_parity10a[0].IN0
+clock => counter8a0.CLK
+clock => counter8a1.CLK
+clock => counter8a2.CLK
+clock => counter8a3.CLK
+clock => counter8a4.CLK
+clock => counter8a5.CLK
+clock => counter8a6.CLK
+clock => counter8a7.CLK
+clock => counter8a8.CLK
+clock => counter8a9.CLK
+clock => parity9.CLK
+clock => sub_parity10a[2].CLK
+clock => sub_parity10a[1].CLK
+clock => sub_parity10a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter8a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter8a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter8a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter8a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter8a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter8a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter8a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter8a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter8a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter8a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+aclr1 => ram_block11a0.CLR1
+aclr1 => ram_block11a1.CLR1
+aclr1 => ram_block11a2.CLR1
+aclr1 => ram_block11a3.CLR1
+aclr1 => ram_block11a4.CLR1
+aclr1 => ram_block11a5.CLR1
+aclr1 => ram_block11a6.CLR1
+aclr1 => ram_block11a7.CLR1
+aclr1 => ram_block11a8.CLR1
+aclr1 => ram_block11a9.CLR1
+aclr1 => ram_block11a10.CLR1
+aclr1 => ram_block11a11.CLR1
+aclr1 => ram_block11a12.CLR1
+aclr1 => ram_block11a13.CLR1
+aclr1 => ram_block11a14.CLR1
+aclr1 => ram_block11a15.CLR1
+address_a[0] => ram_block11a0.PORTAADDR
+address_a[0] => ram_block11a1.PORTAADDR
+address_a[0] => ram_block11a2.PORTAADDR
+address_a[0] => ram_block11a3.PORTAADDR
+address_a[0] => ram_block11a4.PORTAADDR
+address_a[0] => ram_block11a5.PORTAADDR
+address_a[0] => ram_block11a6.PORTAADDR
+address_a[0] => ram_block11a7.PORTAADDR
+address_a[0] => ram_block11a8.PORTAADDR
+address_a[0] => ram_block11a9.PORTAADDR
+address_a[0] => ram_block11a10.PORTAADDR
+address_a[0] => ram_block11a11.PORTAADDR
+address_a[0] => ram_block11a12.PORTAADDR
+address_a[0] => ram_block11a13.PORTAADDR
+address_a[0] => ram_block11a14.PORTAADDR
+address_a[0] => ram_block11a15.PORTAADDR
+address_a[1] => ram_block11a0.PORTAADDR1
+address_a[1] => ram_block11a1.PORTAADDR1
+address_a[1] => ram_block11a2.PORTAADDR1
+address_a[1] => ram_block11a3.PORTAADDR1
+address_a[1] => ram_block11a4.PORTAADDR1
+address_a[1] => ram_block11a5.PORTAADDR1
+address_a[1] => ram_block11a6.PORTAADDR1
+address_a[1] => ram_block11a7.PORTAADDR1
+address_a[1] => ram_block11a8.PORTAADDR1
+address_a[1] => ram_block11a9.PORTAADDR1
+address_a[1] => ram_block11a10.PORTAADDR1
+address_a[1] => ram_block11a11.PORTAADDR1
+address_a[1] => ram_block11a12.PORTAADDR1
+address_a[1] => ram_block11a13.PORTAADDR1
+address_a[1] => ram_block11a14.PORTAADDR1
+address_a[1] => ram_block11a15.PORTAADDR1
+address_a[2] => ram_block11a0.PORTAADDR2
+address_a[2] => ram_block11a1.PORTAADDR2
+address_a[2] => ram_block11a2.PORTAADDR2
+address_a[2] => ram_block11a3.PORTAADDR2
+address_a[2] => ram_block11a4.PORTAADDR2
+address_a[2] => ram_block11a5.PORTAADDR2
+address_a[2] => ram_block11a6.PORTAADDR2
+address_a[2] => ram_block11a7.PORTAADDR2
+address_a[2] => ram_block11a8.PORTAADDR2
+address_a[2] => ram_block11a9.PORTAADDR2
+address_a[2] => ram_block11a10.PORTAADDR2
+address_a[2] => ram_block11a11.PORTAADDR2
+address_a[2] => ram_block11a12.PORTAADDR2
+address_a[2] => ram_block11a13.PORTAADDR2
+address_a[2] => ram_block11a14.PORTAADDR2
+address_a[2] => ram_block11a15.PORTAADDR2
+address_a[3] => ram_block11a0.PORTAADDR3
+address_a[3] => ram_block11a1.PORTAADDR3
+address_a[3] => ram_block11a2.PORTAADDR3
+address_a[3] => ram_block11a3.PORTAADDR3
+address_a[3] => ram_block11a4.PORTAADDR3
+address_a[3] => ram_block11a5.PORTAADDR3
+address_a[3] => ram_block11a6.PORTAADDR3
+address_a[3] => ram_block11a7.PORTAADDR3
+address_a[3] => ram_block11a8.PORTAADDR3
+address_a[3] => ram_block11a9.PORTAADDR3
+address_a[3] => ram_block11a10.PORTAADDR3
+address_a[3] => ram_block11a11.PORTAADDR3
+address_a[3] => ram_block11a12.PORTAADDR3
+address_a[3] => ram_block11a13.PORTAADDR3
+address_a[3] => ram_block11a14.PORTAADDR3
+address_a[3] => ram_block11a15.PORTAADDR3
+address_a[4] => ram_block11a0.PORTAADDR4
+address_a[4] => ram_block11a1.PORTAADDR4
+address_a[4] => ram_block11a2.PORTAADDR4
+address_a[4] => ram_block11a3.PORTAADDR4
+address_a[4] => ram_block11a4.PORTAADDR4
+address_a[4] => ram_block11a5.PORTAADDR4
+address_a[4] => ram_block11a6.PORTAADDR4
+address_a[4] => ram_block11a7.PORTAADDR4
+address_a[4] => ram_block11a8.PORTAADDR4
+address_a[4] => ram_block11a9.PORTAADDR4
+address_a[4] => ram_block11a10.PORTAADDR4
+address_a[4] => ram_block11a11.PORTAADDR4
+address_a[4] => ram_block11a12.PORTAADDR4
+address_a[4] => ram_block11a13.PORTAADDR4
+address_a[4] => ram_block11a14.PORTAADDR4
+address_a[4] => ram_block11a15.PORTAADDR4
+address_a[5] => ram_block11a0.PORTAADDR5
+address_a[5] => ram_block11a1.PORTAADDR5
+address_a[5] => ram_block11a2.PORTAADDR5
+address_a[5] => ram_block11a3.PORTAADDR5
+address_a[5] => ram_block11a4.PORTAADDR5
+address_a[5] => ram_block11a5.PORTAADDR5
+address_a[5] => ram_block11a6.PORTAADDR5
+address_a[5] => ram_block11a7.PORTAADDR5
+address_a[5] => ram_block11a8.PORTAADDR5
+address_a[5] => ram_block11a9.PORTAADDR5
+address_a[5] => ram_block11a10.PORTAADDR5
+address_a[5] => ram_block11a11.PORTAADDR5
+address_a[5] => ram_block11a12.PORTAADDR5
+address_a[5] => ram_block11a13.PORTAADDR5
+address_a[5] => ram_block11a14.PORTAADDR5
+address_a[5] => ram_block11a15.PORTAADDR5
+address_a[6] => ram_block11a0.PORTAADDR6
+address_a[6] => ram_block11a1.PORTAADDR6
+address_a[6] => ram_block11a2.PORTAADDR6
+address_a[6] => ram_block11a3.PORTAADDR6
+address_a[6] => ram_block11a4.PORTAADDR6
+address_a[6] => ram_block11a5.PORTAADDR6
+address_a[6] => ram_block11a6.PORTAADDR6
+address_a[6] => ram_block11a7.PORTAADDR6
+address_a[6] => ram_block11a8.PORTAADDR6
+address_a[6] => ram_block11a9.PORTAADDR6
+address_a[6] => ram_block11a10.PORTAADDR6
+address_a[6] => ram_block11a11.PORTAADDR6
+address_a[6] => ram_block11a12.PORTAADDR6
+address_a[6] => ram_block11a13.PORTAADDR6
+address_a[6] => ram_block11a14.PORTAADDR6
+address_a[6] => ram_block11a15.PORTAADDR6
+address_a[7] => ram_block11a0.PORTAADDR7
+address_a[7] => ram_block11a1.PORTAADDR7
+address_a[7] => ram_block11a2.PORTAADDR7
+address_a[7] => ram_block11a3.PORTAADDR7
+address_a[7] => ram_block11a4.PORTAADDR7
+address_a[7] => ram_block11a5.PORTAADDR7
+address_a[7] => ram_block11a6.PORTAADDR7
+address_a[7] => ram_block11a7.PORTAADDR7
+address_a[7] => ram_block11a8.PORTAADDR7
+address_a[7] => ram_block11a9.PORTAADDR7
+address_a[7] => ram_block11a10.PORTAADDR7
+address_a[7] => ram_block11a11.PORTAADDR7
+address_a[7] => ram_block11a12.PORTAADDR7
+address_a[7] => ram_block11a13.PORTAADDR7
+address_a[7] => ram_block11a14.PORTAADDR7
+address_a[7] => ram_block11a15.PORTAADDR7
+address_a[8] => ram_block11a0.PORTAADDR8
+address_a[8] => ram_block11a1.PORTAADDR8
+address_a[8] => ram_block11a2.PORTAADDR8
+address_a[8] => ram_block11a3.PORTAADDR8
+address_a[8] => ram_block11a4.PORTAADDR8
+address_a[8] => ram_block11a5.PORTAADDR8
+address_a[8] => ram_block11a6.PORTAADDR8
+address_a[8] => ram_block11a7.PORTAADDR8
+address_a[8] => ram_block11a8.PORTAADDR8
+address_a[8] => ram_block11a9.PORTAADDR8
+address_a[8] => ram_block11a10.PORTAADDR8
+address_a[8] => ram_block11a11.PORTAADDR8
+address_a[8] => ram_block11a12.PORTAADDR8
+address_a[8] => ram_block11a13.PORTAADDR8
+address_a[8] => ram_block11a14.PORTAADDR8
+address_a[8] => ram_block11a15.PORTAADDR8
+address_b[0] => ram_block11a0.PORTBADDR
+address_b[0] => ram_block11a1.PORTBADDR
+address_b[0] => ram_block11a2.PORTBADDR
+address_b[0] => ram_block11a3.PORTBADDR
+address_b[0] => ram_block11a4.PORTBADDR
+address_b[0] => ram_block11a5.PORTBADDR
+address_b[0] => ram_block11a6.PORTBADDR
+address_b[0] => ram_block11a7.PORTBADDR
+address_b[0] => ram_block11a8.PORTBADDR
+address_b[0] => ram_block11a9.PORTBADDR
+address_b[0] => ram_block11a10.PORTBADDR
+address_b[0] => ram_block11a11.PORTBADDR
+address_b[0] => ram_block11a12.PORTBADDR
+address_b[0] => ram_block11a13.PORTBADDR
+address_b[0] => ram_block11a14.PORTBADDR
+address_b[0] => ram_block11a15.PORTBADDR
+address_b[1] => ram_block11a0.PORTBADDR1
+address_b[1] => ram_block11a1.PORTBADDR1
+address_b[1] => ram_block11a2.PORTBADDR1
+address_b[1] => ram_block11a3.PORTBADDR1
+address_b[1] => ram_block11a4.PORTBADDR1
+address_b[1] => ram_block11a5.PORTBADDR1
+address_b[1] => ram_block11a6.PORTBADDR1
+address_b[1] => ram_block11a7.PORTBADDR1
+address_b[1] => ram_block11a8.PORTBADDR1
+address_b[1] => ram_block11a9.PORTBADDR1
+address_b[1] => ram_block11a10.PORTBADDR1
+address_b[1] => ram_block11a11.PORTBADDR1
+address_b[1] => ram_block11a12.PORTBADDR1
+address_b[1] => ram_block11a13.PORTBADDR1
+address_b[1] => ram_block11a14.PORTBADDR1
+address_b[1] => ram_block11a15.PORTBADDR1
+address_b[2] => ram_block11a0.PORTBADDR2
+address_b[2] => ram_block11a1.PORTBADDR2
+address_b[2] => ram_block11a2.PORTBADDR2
+address_b[2] => ram_block11a3.PORTBADDR2
+address_b[2] => ram_block11a4.PORTBADDR2
+address_b[2] => ram_block11a5.PORTBADDR2
+address_b[2] => ram_block11a6.PORTBADDR2
+address_b[2] => ram_block11a7.PORTBADDR2
+address_b[2] => ram_block11a8.PORTBADDR2
+address_b[2] => ram_block11a9.PORTBADDR2
+address_b[2] => ram_block11a10.PORTBADDR2
+address_b[2] => ram_block11a11.PORTBADDR2
+address_b[2] => ram_block11a12.PORTBADDR2
+address_b[2] => ram_block11a13.PORTBADDR2
+address_b[2] => ram_block11a14.PORTBADDR2
+address_b[2] => ram_block11a15.PORTBADDR2
+address_b[3] => ram_block11a0.PORTBADDR3
+address_b[3] => ram_block11a1.PORTBADDR3
+address_b[3] => ram_block11a2.PORTBADDR3
+address_b[3] => ram_block11a3.PORTBADDR3
+address_b[3] => ram_block11a4.PORTBADDR3
+address_b[3] => ram_block11a5.PORTBADDR3
+address_b[3] => ram_block11a6.PORTBADDR3
+address_b[3] => ram_block11a7.PORTBADDR3
+address_b[3] => ram_block11a8.PORTBADDR3
+address_b[3] => ram_block11a9.PORTBADDR3
+address_b[3] => ram_block11a10.PORTBADDR3
+address_b[3] => ram_block11a11.PORTBADDR3
+address_b[3] => ram_block11a12.PORTBADDR3
+address_b[3] => ram_block11a13.PORTBADDR3
+address_b[3] => ram_block11a14.PORTBADDR3
+address_b[3] => ram_block11a15.PORTBADDR3
+address_b[4] => ram_block11a0.PORTBADDR4
+address_b[4] => ram_block11a1.PORTBADDR4
+address_b[4] => ram_block11a2.PORTBADDR4
+address_b[4] => ram_block11a3.PORTBADDR4
+address_b[4] => ram_block11a4.PORTBADDR4
+address_b[4] => ram_block11a5.PORTBADDR4
+address_b[4] => ram_block11a6.PORTBADDR4
+address_b[4] => ram_block11a7.PORTBADDR4
+address_b[4] => ram_block11a8.PORTBADDR4
+address_b[4] => ram_block11a9.PORTBADDR4
+address_b[4] => ram_block11a10.PORTBADDR4
+address_b[4] => ram_block11a11.PORTBADDR4
+address_b[4] => ram_block11a12.PORTBADDR4
+address_b[4] => ram_block11a13.PORTBADDR4
+address_b[4] => ram_block11a14.PORTBADDR4
+address_b[4] => ram_block11a15.PORTBADDR4
+address_b[5] => ram_block11a0.PORTBADDR5
+address_b[5] => ram_block11a1.PORTBADDR5
+address_b[5] => ram_block11a2.PORTBADDR5
+address_b[5] => ram_block11a3.PORTBADDR5
+address_b[5] => ram_block11a4.PORTBADDR5
+address_b[5] => ram_block11a5.PORTBADDR5
+address_b[5] => ram_block11a6.PORTBADDR5
+address_b[5] => ram_block11a7.PORTBADDR5
+address_b[5] => ram_block11a8.PORTBADDR5
+address_b[5] => ram_block11a9.PORTBADDR5
+address_b[5] => ram_block11a10.PORTBADDR5
+address_b[5] => ram_block11a11.PORTBADDR5
+address_b[5] => ram_block11a12.PORTBADDR5
+address_b[5] => ram_block11a13.PORTBADDR5
+address_b[5] => ram_block11a14.PORTBADDR5
+address_b[5] => ram_block11a15.PORTBADDR5
+address_b[6] => ram_block11a0.PORTBADDR6
+address_b[6] => ram_block11a1.PORTBADDR6
+address_b[6] => ram_block11a2.PORTBADDR6
+address_b[6] => ram_block11a3.PORTBADDR6
+address_b[6] => ram_block11a4.PORTBADDR6
+address_b[6] => ram_block11a5.PORTBADDR6
+address_b[6] => ram_block11a6.PORTBADDR6
+address_b[6] => ram_block11a7.PORTBADDR6
+address_b[6] => ram_block11a8.PORTBADDR6
+address_b[6] => ram_block11a9.PORTBADDR6
+address_b[6] => ram_block11a10.PORTBADDR6
+address_b[6] => ram_block11a11.PORTBADDR6
+address_b[6] => ram_block11a12.PORTBADDR6
+address_b[6] => ram_block11a13.PORTBADDR6
+address_b[6] => ram_block11a14.PORTBADDR6
+address_b[6] => ram_block11a15.PORTBADDR6
+address_b[7] => ram_block11a0.PORTBADDR7
+address_b[7] => ram_block11a1.PORTBADDR7
+address_b[7] => ram_block11a2.PORTBADDR7
+address_b[7] => ram_block11a3.PORTBADDR7
+address_b[7] => ram_block11a4.PORTBADDR7
+address_b[7] => ram_block11a5.PORTBADDR7
+address_b[7] => ram_block11a6.PORTBADDR7
+address_b[7] => ram_block11a7.PORTBADDR7
+address_b[7] => ram_block11a8.PORTBADDR7
+address_b[7] => ram_block11a9.PORTBADDR7
+address_b[7] => ram_block11a10.PORTBADDR7
+address_b[7] => ram_block11a11.PORTBADDR7
+address_b[7] => ram_block11a12.PORTBADDR7
+address_b[7] => ram_block11a13.PORTBADDR7
+address_b[7] => ram_block11a14.PORTBADDR7
+address_b[7] => ram_block11a15.PORTBADDR7
+address_b[8] => ram_block11a0.PORTBADDR8
+address_b[8] => ram_block11a1.PORTBADDR8
+address_b[8] => ram_block11a2.PORTBADDR8
+address_b[8] => ram_block11a3.PORTBADDR8
+address_b[8] => ram_block11a4.PORTBADDR8
+address_b[8] => ram_block11a5.PORTBADDR8
+address_b[8] => ram_block11a6.PORTBADDR8
+address_b[8] => ram_block11a7.PORTBADDR8
+address_b[8] => ram_block11a8.PORTBADDR8
+address_b[8] => ram_block11a9.PORTBADDR8
+address_b[8] => ram_block11a10.PORTBADDR8
+address_b[8] => ram_block11a11.PORTBADDR8
+address_b[8] => ram_block11a12.PORTBADDR8
+address_b[8] => ram_block11a13.PORTBADDR8
+address_b[8] => ram_block11a14.PORTBADDR8
+address_b[8] => ram_block11a15.PORTBADDR8
+addressstall_b => ram_block11a0.PORTBADDRSTALL
+addressstall_b => ram_block11a1.PORTBADDRSTALL
+addressstall_b => ram_block11a2.PORTBADDRSTALL
+addressstall_b => ram_block11a3.PORTBADDRSTALL
+addressstall_b => ram_block11a4.PORTBADDRSTALL
+addressstall_b => ram_block11a5.PORTBADDRSTALL
+addressstall_b => ram_block11a6.PORTBADDRSTALL
+addressstall_b => ram_block11a7.PORTBADDRSTALL
+addressstall_b => ram_block11a8.PORTBADDRSTALL
+addressstall_b => ram_block11a9.PORTBADDRSTALL
+addressstall_b => ram_block11a10.PORTBADDRSTALL
+addressstall_b => ram_block11a11.PORTBADDRSTALL
+addressstall_b => ram_block11a12.PORTBADDRSTALL
+addressstall_b => ram_block11a13.PORTBADDRSTALL
+addressstall_b => ram_block11a14.PORTBADDRSTALL
+addressstall_b => ram_block11a15.PORTBADDRSTALL
+clock0 => ram_block11a0.CLK0
+clock0 => ram_block11a1.CLK0
+clock0 => ram_block11a2.CLK0
+clock0 => ram_block11a3.CLK0
+clock0 => ram_block11a4.CLK0
+clock0 => ram_block11a5.CLK0
+clock0 => ram_block11a6.CLK0
+clock0 => ram_block11a7.CLK0
+clock0 => ram_block11a8.CLK0
+clock0 => ram_block11a9.CLK0
+clock0 => ram_block11a10.CLK0
+clock0 => ram_block11a11.CLK0
+clock0 => ram_block11a12.CLK0
+clock0 => ram_block11a13.CLK0
+clock0 => ram_block11a14.CLK0
+clock0 => ram_block11a15.CLK0
+clock1 => ram_block11a0.CLK1
+clock1 => ram_block11a1.CLK1
+clock1 => ram_block11a2.CLK1
+clock1 => ram_block11a3.CLK1
+clock1 => ram_block11a4.CLK1
+clock1 => ram_block11a5.CLK1
+clock1 => ram_block11a6.CLK1
+clock1 => ram_block11a7.CLK1
+clock1 => ram_block11a8.CLK1
+clock1 => ram_block11a9.CLK1
+clock1 => ram_block11a10.CLK1
+clock1 => ram_block11a11.CLK1
+clock1 => ram_block11a12.CLK1
+clock1 => ram_block11a13.CLK1
+clock1 => ram_block11a14.CLK1
+clock1 => ram_block11a15.CLK1
+clocken1 => ram_block11a0.ENA1
+clocken1 => ram_block11a1.ENA1
+clocken1 => ram_block11a2.ENA1
+clocken1 => ram_block11a3.ENA1
+clocken1 => ram_block11a4.ENA1
+clocken1 => ram_block11a5.ENA1
+clocken1 => ram_block11a6.ENA1
+clocken1 => ram_block11a7.ENA1
+clocken1 => ram_block11a8.ENA1
+clocken1 => ram_block11a9.ENA1
+clocken1 => ram_block11a10.ENA1
+clocken1 => ram_block11a11.ENA1
+clocken1 => ram_block11a12.ENA1
+clocken1 => ram_block11a13.ENA1
+clocken1 => ram_block11a14.ENA1
+clocken1 => ram_block11a15.ENA1
+data_a[0] => ram_block11a0.PORTADATAIN
+data_a[1] => ram_block11a1.PORTADATAIN
+data_a[2] => ram_block11a2.PORTADATAIN
+data_a[3] => ram_block11a3.PORTADATAIN
+data_a[4] => ram_block11a4.PORTADATAIN
+data_a[5] => ram_block11a5.PORTADATAIN
+data_a[6] => ram_block11a6.PORTADATAIN
+data_a[7] => ram_block11a7.PORTADATAIN
+data_a[8] => ram_block11a8.PORTADATAIN
+data_a[9] => ram_block11a9.PORTADATAIN
+data_a[10] => ram_block11a10.PORTADATAIN
+data_a[11] => ram_block11a11.PORTADATAIN
+data_a[12] => ram_block11a12.PORTADATAIN
+data_a[13] => ram_block11a13.PORTADATAIN
+data_a[14] => ram_block11a14.PORTADATAIN
+data_a[15] => ram_block11a15.PORTADATAIN
+q_b[0] <= ram_block11a0.PORTBDATAOUT
+q_b[1] <= ram_block11a1.PORTBDATAOUT
+q_b[2] <= ram_block11a2.PORTBDATAOUT
+q_b[3] <= ram_block11a3.PORTBDATAOUT
+q_b[4] <= ram_block11a4.PORTBDATAOUT
+q_b[5] <= ram_block11a5.PORTBDATAOUT
+q_b[6] <= ram_block11a6.PORTBDATAOUT
+q_b[7] <= ram_block11a7.PORTBDATAOUT
+q_b[8] <= ram_block11a8.PORTBDATAOUT
+q_b[9] <= ram_block11a9.PORTBDATAOUT
+q_b[10] <= ram_block11a10.PORTBDATAOUT
+q_b[11] <= ram_block11a11.PORTBDATAOUT
+q_b[12] <= ram_block11a12.PORTBDATAOUT
+q_b[13] <= ram_block11a13.PORTBDATAOUT
+q_b[14] <= ram_block11a14.PORTBDATAOUT
+q_b[15] <= ram_block11a15.PORTBDATAOUT
+wren_a => ram_block11a0.PORTAWE
+wren_a => ram_block11a0.ENA0
+wren_a => ram_block11a1.PORTAWE
+wren_a => ram_block11a1.ENA0
+wren_a => ram_block11a2.PORTAWE
+wren_a => ram_block11a2.ENA0
+wren_a => ram_block11a3.PORTAWE
+wren_a => ram_block11a3.ENA0
+wren_a => ram_block11a4.PORTAWE
+wren_a => ram_block11a4.ENA0
+wren_a => ram_block11a5.PORTAWE
+wren_a => ram_block11a5.ENA0
+wren_a => ram_block11a6.PORTAWE
+wren_a => ram_block11a6.ENA0
+wren_a => ram_block11a7.PORTAWE
+wren_a => ram_block11a7.ENA0
+wren_a => ram_block11a8.PORTAWE
+wren_a => ram_block11a8.ENA0
+wren_a => ram_block11a9.PORTAWE
+wren_a => ram_block11a9.ENA0
+wren_a => ram_block11a10.PORTAWE
+wren_a => ram_block11a10.ENA0
+wren_a => ram_block11a11.PORTAWE
+wren_a => ram_block11a11.ENA0
+wren_a => ram_block11a12.PORTAWE
+wren_a => ram_block11a12.ENA0
+wren_a => ram_block11a13.PORTAWE
+wren_a => ram_block11a13.ENA0
+wren_a => ram_block11a14.PORTAWE
+wren_a => ram_block11a14.ENA0
+wren_a => ram_block11a15.PORTAWE
+wren_a => ram_block11a15.ENA0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+clock => dffpipe_pe9:dffpipe13.clock
+clrn => dffpipe_pe9:dffpipe13.clrn
+d[0] => dffpipe_pe9:dffpipe13.d[0]
+d[1] => dffpipe_pe9:dffpipe13.d[1]
+d[2] => dffpipe_pe9:dffpipe13.d[2]
+d[3] => dffpipe_pe9:dffpipe13.d[3]
+d[4] => dffpipe_pe9:dffpipe13.d[4]
+d[5] => dffpipe_pe9:dffpipe13.d[5]
+d[6] => dffpipe_pe9:dffpipe13.d[6]
+d[7] => dffpipe_pe9:dffpipe13.d[7]
+d[8] => dffpipe_pe9:dffpipe13.d[8]
+d[9] => dffpipe_pe9:dffpipe13.d[9]
+q[0] <= dffpipe_pe9:dffpipe13.q[0]
+q[1] <= dffpipe_pe9:dffpipe13.q[1]
+q[2] <= dffpipe_pe9:dffpipe13.q[2]
+q[3] <= dffpipe_pe9:dffpipe13.q[3]
+q[4] <= dffpipe_pe9:dffpipe13.q[4]
+q[5] <= dffpipe_pe9:dffpipe13.q[5]
+q[6] <= dffpipe_pe9:dffpipe13.q[6]
+q[7] <= dffpipe_pe9:dffpipe13.q[7]
+q[8] <= dffpipe_pe9:dffpipe13.q[8]
+q[9] <= dffpipe_pe9:dffpipe13.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+clock => dffe14a[9].CLK
+clock => dffe14a[8].CLK
+clock => dffe14a[7].CLK
+clock => dffe14a[6].CLK
+clock => dffe14a[5].CLK
+clock => dffe14a[4].CLK
+clock => dffe14a[3].CLK
+clock => dffe14a[2].CLK
+clock => dffe14a[1].CLK
+clock => dffe14a[0].CLK
+clock => dffe15a[9].CLK
+clock => dffe15a[8].CLK
+clock => dffe15a[7].CLK
+clock => dffe15a[6].CLK
+clock => dffe15a[5].CLK
+clock => dffe15a[4].CLK
+clock => dffe15a[3].CLK
+clock => dffe15a[2].CLK
+clock => dffe15a[1].CLK
+clock => dffe15a[0].CLK
+clrn => dffe14a[9].ACLR
+clrn => dffe14a[8].ACLR
+clrn => dffe14a[7].ACLR
+clrn => dffe14a[6].ACLR
+clrn => dffe14a[5].ACLR
+clrn => dffe14a[4].ACLR
+clrn => dffe14a[3].ACLR
+clrn => dffe14a[2].ACLR
+clrn => dffe14a[1].ACLR
+clrn => dffe14a[0].ACLR
+clrn => dffe15a[9].ACLR
+clrn => dffe15a[8].ACLR
+clrn => dffe15a[7].ACLR
+clrn => dffe15a[6].ACLR
+clrn => dffe15a[5].ACLR
+clrn => dffe15a[4].ACLR
+clrn => dffe15a[3].ACLR
+clrn => dffe15a[2].ACLR
+clrn => dffe15a[1].ACLR
+clrn => dffe15a[0].ACLR
+d[0] => dffe14a[0].IN0
+d[1] => dffe14a[1].IN0
+d[2] => dffe14a[2].IN0
+d[3] => dffe14a[3].IN0
+d[4] => dffe14a[4].IN0
+d[5] => dffe14a[5].IN0
+d[6] => dffe14a[6].IN0
+d[7] => dffe14a[7].IN0
+d[8] => dffe14a[8].IN0
+d[9] => dffe14a[9].IN0
+q[0] <= dffe15a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe15a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe15a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe15a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe15a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe15a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe15a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe15a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe15a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe15a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+clock => dffpipe_qe9:dffpipe16.clock
+clrn => dffpipe_qe9:dffpipe16.clrn
+d[0] => dffpipe_qe9:dffpipe16.d[0]
+d[1] => dffpipe_qe9:dffpipe16.d[1]
+d[2] => dffpipe_qe9:dffpipe16.d[2]
+d[3] => dffpipe_qe9:dffpipe16.d[3]
+d[4] => dffpipe_qe9:dffpipe16.d[4]
+d[5] => dffpipe_qe9:dffpipe16.d[5]
+d[6] => dffpipe_qe9:dffpipe16.d[6]
+d[7] => dffpipe_qe9:dffpipe16.d[7]
+d[8] => dffpipe_qe9:dffpipe16.d[8]
+d[9] => dffpipe_qe9:dffpipe16.d[9]
+q[0] <= dffpipe_qe9:dffpipe16.q[0]
+q[1] <= dffpipe_qe9:dffpipe16.q[1]
+q[2] <= dffpipe_qe9:dffpipe16.q[2]
+q[3] <= dffpipe_qe9:dffpipe16.q[3]
+q[4] <= dffpipe_qe9:dffpipe16.q[4]
+q[5] <= dffpipe_qe9:dffpipe16.q[5]
+q[6] <= dffpipe_qe9:dffpipe16.q[6]
+q[7] <= dffpipe_qe9:dffpipe16.q[7]
+q[8] <= dffpipe_qe9:dffpipe16.q[8]
+q[9] <= dffpipe_qe9:dffpipe16.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+clock => dffe17a[9].CLK
+clock => dffe17a[8].CLK
+clock => dffe17a[7].CLK
+clock => dffe17a[6].CLK
+clock => dffe17a[5].CLK
+clock => dffe17a[4].CLK
+clock => dffe17a[3].CLK
+clock => dffe17a[2].CLK
+clock => dffe17a[1].CLK
+clock => dffe17a[0].CLK
+clock => dffe18a[9].CLK
+clock => dffe18a[8].CLK
+clock => dffe18a[7].CLK
+clock => dffe18a[6].CLK
+clock => dffe18a[5].CLK
+clock => dffe18a[4].CLK
+clock => dffe18a[3].CLK
+clock => dffe18a[2].CLK
+clock => dffe18a[1].CLK
+clock => dffe18a[0].CLK
+clrn => dffe17a[9].ACLR
+clrn => dffe17a[8].ACLR
+clrn => dffe17a[7].ACLR
+clrn => dffe17a[6].ACLR
+clrn => dffe17a[5].ACLR
+clrn => dffe17a[4].ACLR
+clrn => dffe17a[3].ACLR
+clrn => dffe17a[2].ACLR
+clrn => dffe17a[1].ACLR
+clrn => dffe17a[0].ACLR
+clrn => dffe18a[9].ACLR
+clrn => dffe18a[8].ACLR
+clrn => dffe18a[7].ACLR
+clrn => dffe18a[6].ACLR
+clrn => dffe18a[5].ACLR
+clrn => dffe18a[4].ACLR
+clrn => dffe18a[3].ACLR
+clrn => dffe18a[2].ACLR
+clrn => dffe18a[1].ACLR
+clrn => dffe18a[0].ACLR
+d[0] => dffe17a[0].IN0
+d[1] => dffe17a[1].IN0
+d[2] => dffe17a[2].IN0
+d[3] => dffe17a[3].IN0
+d[4] => dffe17a[4].IN0
+d[5] => dffe17a[5].IN0
+d[6] => dffe17a[6].IN0
+d[7] => dffe17a[7].IN0
+d[8] => dffe17a[8].IN0
+d[9] => dffe17a[9].IN0
+q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2
+aclr => aclr.IN1
+data[0] => data[0].IN1
+data[1] => data[1].IN1
+data[2] => data[2].IN1
+data[3] => data[3].IN1
+data[4] => data[4].IN1
+data[5] => data[5].IN1
+data[6] => data[6].IN1
+data[7] => data[7].IN1
+data[8] => data[8].IN1
+data[9] => data[9].IN1
+data[10] => data[10].IN1
+data[11] => data[11].IN1
+data[12] => data[12].IN1
+data[13] => data[13].IN1
+data[14] => data[14].IN1
+data[15] => data[15].IN1
+rdclk => rdclk.IN1
+rdreq => rdreq.IN1
+wrclk => wrclk.IN1
+wrreq => wrreq.IN1
+q[0] <= dcfifo:dcfifo_component.q
+q[1] <= dcfifo:dcfifo_component.q
+q[2] <= dcfifo:dcfifo_component.q
+q[3] <= dcfifo:dcfifo_component.q
+q[4] <= dcfifo:dcfifo_component.q
+q[5] <= dcfifo:dcfifo_component.q
+q[6] <= dcfifo:dcfifo_component.q
+q[7] <= dcfifo:dcfifo_component.q
+q[8] <= dcfifo:dcfifo_component.q
+q[9] <= dcfifo:dcfifo_component.q
+q[10] <= dcfifo:dcfifo_component.q
+q[11] <= dcfifo:dcfifo_component.q
+q[12] <= dcfifo:dcfifo_component.q
+q[13] <= dcfifo:dcfifo_component.q
+q[14] <= dcfifo:dcfifo_component.q
+q[15] <= dcfifo:dcfifo_component.q
+rdempty <= dcfifo:dcfifo_component.rdempty
+rdusedw[0] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[1] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[2] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[3] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[4] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[5] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[6] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[7] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[8] <= dcfifo:dcfifo_component.rdusedw
+wrfull <= dcfifo:dcfifo_component.wrfull
+wrusedw[0] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[1] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[2] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[3] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[4] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[5] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[6] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[7] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[8] <= dcfifo:dcfifo_component.wrusedw
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+data[0] => dcfifo_v5o1:auto_generated.data[0]
+data[1] => dcfifo_v5o1:auto_generated.data[1]
+data[2] => dcfifo_v5o1:auto_generated.data[2]
+data[3] => dcfifo_v5o1:auto_generated.data[3]
+data[4] => dcfifo_v5o1:auto_generated.data[4]
+data[5] => dcfifo_v5o1:auto_generated.data[5]
+data[6] => dcfifo_v5o1:auto_generated.data[6]
+data[7] => dcfifo_v5o1:auto_generated.data[7]
+data[8] => dcfifo_v5o1:auto_generated.data[8]
+data[9] => dcfifo_v5o1:auto_generated.data[9]
+data[10] => dcfifo_v5o1:auto_generated.data[10]
+data[11] => dcfifo_v5o1:auto_generated.data[11]
+data[12] => dcfifo_v5o1:auto_generated.data[12]
+data[13] => dcfifo_v5o1:auto_generated.data[13]
+data[14] => dcfifo_v5o1:auto_generated.data[14]
+data[15] => dcfifo_v5o1:auto_generated.data[15]
+q[0] <= dcfifo_v5o1:auto_generated.q[0]
+q[1] <= dcfifo_v5o1:auto_generated.q[1]
+q[2] <= dcfifo_v5o1:auto_generated.q[2]
+q[3] <= dcfifo_v5o1:auto_generated.q[3]
+q[4] <= dcfifo_v5o1:auto_generated.q[4]
+q[5] <= dcfifo_v5o1:auto_generated.q[5]
+q[6] <= dcfifo_v5o1:auto_generated.q[6]
+q[7] <= dcfifo_v5o1:auto_generated.q[7]
+q[8] <= dcfifo_v5o1:auto_generated.q[8]
+q[9] <= dcfifo_v5o1:auto_generated.q[9]
+q[10] <= dcfifo_v5o1:auto_generated.q[10]
+q[11] <= dcfifo_v5o1:auto_generated.q[11]
+q[12] <= dcfifo_v5o1:auto_generated.q[12]
+q[13] <= dcfifo_v5o1:auto_generated.q[13]
+q[14] <= dcfifo_v5o1:auto_generated.q[14]
+q[15] <= dcfifo_v5o1:auto_generated.q[15]
+rdclk => dcfifo_v5o1:auto_generated.rdclk
+rdreq => dcfifo_v5o1:auto_generated.rdreq
+wrclk => dcfifo_v5o1:auto_generated.wrclk
+wrreq => dcfifo_v5o1:auto_generated.wrreq
+aclr => dcfifo_v5o1:auto_generated.aclr
+rdempty <= dcfifo_v5o1:auto_generated.rdempty
+rdfull <= <UNC>
+wrempty <= <GND>
+wrfull <= dcfifo_v5o1:auto_generated.wrfull
+rdusedw[0] <= dcfifo_v5o1:auto_generated.rdusedw[0]
+rdusedw[1] <= dcfifo_v5o1:auto_generated.rdusedw[1]
+rdusedw[2] <= dcfifo_v5o1:auto_generated.rdusedw[2]
+rdusedw[3] <= dcfifo_v5o1:auto_generated.rdusedw[3]
+rdusedw[4] <= dcfifo_v5o1:auto_generated.rdusedw[4]
+rdusedw[5] <= dcfifo_v5o1:auto_generated.rdusedw[5]
+rdusedw[6] <= dcfifo_v5o1:auto_generated.rdusedw[6]
+rdusedw[7] <= dcfifo_v5o1:auto_generated.rdusedw[7]
+rdusedw[8] <= dcfifo_v5o1:auto_generated.rdusedw[8]
+wrusedw[0] <= dcfifo_v5o1:auto_generated.wrusedw[0]
+wrusedw[1] <= dcfifo_v5o1:auto_generated.wrusedw[1]
+wrusedw[2] <= dcfifo_v5o1:auto_generated.wrusedw[2]
+wrusedw[3] <= dcfifo_v5o1:auto_generated.wrusedw[3]
+wrusedw[4] <= dcfifo_v5o1:auto_generated.wrusedw[4]
+wrusedw[5] <= dcfifo_v5o1:auto_generated.wrusedw[5]
+wrusedw[6] <= dcfifo_v5o1:auto_generated.wrusedw[6]
+wrusedw[7] <= dcfifo_v5o1:auto_generated.wrusedw[7]
+wrusedw[8] <= dcfifo_v5o1:auto_generated.wrusedw[8]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+aclr => a_graycounter_s57:rdptr_g1p.aclr
+aclr => a_graycounter_ojc:wrptr_g1p.aclr
+aclr => altsyncram_de51:fifo_ram.aclr1
+aclr => delayed_wrptr_g[9].IN0
+aclr => rdptr_g[9].IN0
+aclr => wrptr_g[9].IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+data[0] => altsyncram_de51:fifo_ram.data_a[0]
+data[1] => altsyncram_de51:fifo_ram.data_a[1]
+data[2] => altsyncram_de51:fifo_ram.data_a[2]
+data[3] => altsyncram_de51:fifo_ram.data_a[3]
+data[4] => altsyncram_de51:fifo_ram.data_a[4]
+data[5] => altsyncram_de51:fifo_ram.data_a[5]
+data[6] => altsyncram_de51:fifo_ram.data_a[6]
+data[7] => altsyncram_de51:fifo_ram.data_a[7]
+data[8] => altsyncram_de51:fifo_ram.data_a[8]
+data[9] => altsyncram_de51:fifo_ram.data_a[9]
+data[10] => altsyncram_de51:fifo_ram.data_a[10]
+data[11] => altsyncram_de51:fifo_ram.data_a[11]
+data[12] => altsyncram_de51:fifo_ram.data_a[12]
+data[13] => altsyncram_de51:fifo_ram.data_a[13]
+data[14] => altsyncram_de51:fifo_ram.data_a[14]
+data[15] => altsyncram_de51:fifo_ram.data_a[15]
+q[0] <= altsyncram_de51:fifo_ram.q_b[0]
+q[1] <= altsyncram_de51:fifo_ram.q_b[1]
+q[2] <= altsyncram_de51:fifo_ram.q_b[2]
+q[3] <= altsyncram_de51:fifo_ram.q_b[3]
+q[4] <= altsyncram_de51:fifo_ram.q_b[4]
+q[5] <= altsyncram_de51:fifo_ram.q_b[5]
+q[6] <= altsyncram_de51:fifo_ram.q_b[6]
+q[7] <= altsyncram_de51:fifo_ram.q_b[7]
+q[8] <= altsyncram_de51:fifo_ram.q_b[8]
+q[9] <= altsyncram_de51:fifo_ram.q_b[9]
+q[10] <= altsyncram_de51:fifo_ram.q_b[10]
+q[11] <= altsyncram_de51:fifo_ram.q_b[11]
+q[12] <= altsyncram_de51:fifo_ram.q_b[12]
+q[13] <= altsyncram_de51:fifo_ram.q_b[13]
+q[14] <= altsyncram_de51:fifo_ram.q_b[14]
+q[15] <= altsyncram_de51:fifo_ram.q_b[15]
+rdclk => a_graycounter_s57:rdptr_g1p.clock
+rdclk => altsyncram_de51:fifo_ram.clock1
+rdclk => dffpipe_oe9:rs_brp.clock
+rdclk => dffpipe_oe9:rs_bwp.clock
+rdclk => alt_synch_pipe_qld:rs_dgwp.clock
+rdclk => rdptr_g[9].CLK
+rdclk => rdptr_g[8].CLK
+rdclk => rdptr_g[7].CLK
+rdclk => rdptr_g[6].CLK
+rdclk => rdptr_g[5].CLK
+rdclk => rdptr_g[4].CLK
+rdclk => rdptr_g[3].CLK
+rdclk => rdptr_g[2].CLK
+rdclk => rdptr_g[1].CLK
+rdclk => rdptr_g[0].CLK
+rdempty <= int_rdempty.DB_MAX_OUTPUT_PORT_TYPE
+rdreq => valid_rdreq.IN0
+rdusedw[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+wrclk => a_graycounter_ojc:wrptr_g1p.clock
+wrclk => altsyncram_de51:fifo_ram.clock0
+wrclk => dffpipe_oe9:ws_brp.clock
+wrclk => dffpipe_oe9:ws_bwp.clock
+wrclk => alt_synch_pipe_rld:ws_dgrp.clock
+wrclk => delayed_wrptr_g[9].CLK
+wrclk => delayed_wrptr_g[8].CLK
+wrclk => delayed_wrptr_g[7].CLK
+wrclk => delayed_wrptr_g[6].CLK
+wrclk => delayed_wrptr_g[5].CLK
+wrclk => delayed_wrptr_g[4].CLK
+wrclk => delayed_wrptr_g[3].CLK
+wrclk => delayed_wrptr_g[2].CLK
+wrclk => delayed_wrptr_g[1].CLK
+wrclk => delayed_wrptr_g[0].CLK
+wrclk => wrptr_g[9].CLK
+wrclk => wrptr_g[8].CLK
+wrclk => wrptr_g[7].CLK
+wrclk => wrptr_g[6].CLK
+wrclk => wrptr_g[5].CLK
+wrclk => wrptr_g[4].CLK
+wrclk => wrptr_g[3].CLK
+wrclk => wrptr_g[2].CLK
+wrclk => wrptr_g[1].CLK
+wrclk => wrptr_g[0].CLK
+wrfull <= int_wrfull.DB_MAX_OUTPUT_PORT_TYPE
+wrreq => valid_wrreq.IN0
+wrusedw[0] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[1] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[2] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[3] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[4] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[5] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[6] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[7] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[8] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+aclr => counter5a1.IN0
+aclr => counter5a0.IN0
+aclr => parity6.IN0
+aclr => sub_parity7a[2].IN0
+aclr => sub_parity7a[1].IN0
+aclr => sub_parity7a[0].IN0
+clock => counter5a0.CLK
+clock => counter5a1.CLK
+clock => counter5a2.CLK
+clock => counter5a3.CLK
+clock => counter5a4.CLK
+clock => counter5a5.CLK
+clock => counter5a6.CLK
+clock => counter5a7.CLK
+clock => counter5a8.CLK
+clock => counter5a9.CLK
+clock => parity6.CLK
+clock => sub_parity7a[2].CLK
+clock => sub_parity7a[1].CLK
+clock => sub_parity7a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter5a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter5a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter5a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter5a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter5a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter5a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter5a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter5a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter5a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter5a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+aclr => counter8a1.IN0
+aclr => counter8a0.IN0
+aclr => parity9.IN0
+aclr => sub_parity10a[2].IN0
+aclr => sub_parity10a[1].IN0
+aclr => sub_parity10a[0].IN0
+clock => counter8a0.CLK
+clock => counter8a1.CLK
+clock => counter8a2.CLK
+clock => counter8a3.CLK
+clock => counter8a4.CLK
+clock => counter8a5.CLK
+clock => counter8a6.CLK
+clock => counter8a7.CLK
+clock => counter8a8.CLK
+clock => counter8a9.CLK
+clock => parity9.CLK
+clock => sub_parity10a[2].CLK
+clock => sub_parity10a[1].CLK
+clock => sub_parity10a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter8a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter8a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter8a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter8a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter8a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter8a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter8a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter8a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter8a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter8a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+aclr1 => ram_block11a0.CLR1
+aclr1 => ram_block11a1.CLR1
+aclr1 => ram_block11a2.CLR1
+aclr1 => ram_block11a3.CLR1
+aclr1 => ram_block11a4.CLR1
+aclr1 => ram_block11a5.CLR1
+aclr1 => ram_block11a6.CLR1
+aclr1 => ram_block11a7.CLR1
+aclr1 => ram_block11a8.CLR1
+aclr1 => ram_block11a9.CLR1
+aclr1 => ram_block11a10.CLR1
+aclr1 => ram_block11a11.CLR1
+aclr1 => ram_block11a12.CLR1
+aclr1 => ram_block11a13.CLR1
+aclr1 => ram_block11a14.CLR1
+aclr1 => ram_block11a15.CLR1
+address_a[0] => ram_block11a0.PORTAADDR
+address_a[0] => ram_block11a1.PORTAADDR
+address_a[0] => ram_block11a2.PORTAADDR
+address_a[0] => ram_block11a3.PORTAADDR
+address_a[0] => ram_block11a4.PORTAADDR
+address_a[0] => ram_block11a5.PORTAADDR
+address_a[0] => ram_block11a6.PORTAADDR
+address_a[0] => ram_block11a7.PORTAADDR
+address_a[0] => ram_block11a8.PORTAADDR
+address_a[0] => ram_block11a9.PORTAADDR
+address_a[0] => ram_block11a10.PORTAADDR
+address_a[0] => ram_block11a11.PORTAADDR
+address_a[0] => ram_block11a12.PORTAADDR
+address_a[0] => ram_block11a13.PORTAADDR
+address_a[0] => ram_block11a14.PORTAADDR
+address_a[0] => ram_block11a15.PORTAADDR
+address_a[1] => ram_block11a0.PORTAADDR1
+address_a[1] => ram_block11a1.PORTAADDR1
+address_a[1] => ram_block11a2.PORTAADDR1
+address_a[1] => ram_block11a3.PORTAADDR1
+address_a[1] => ram_block11a4.PORTAADDR1
+address_a[1] => ram_block11a5.PORTAADDR1
+address_a[1] => ram_block11a6.PORTAADDR1
+address_a[1] => ram_block11a7.PORTAADDR1
+address_a[1] => ram_block11a8.PORTAADDR1
+address_a[1] => ram_block11a9.PORTAADDR1
+address_a[1] => ram_block11a10.PORTAADDR1
+address_a[1] => ram_block11a11.PORTAADDR1
+address_a[1] => ram_block11a12.PORTAADDR1
+address_a[1] => ram_block11a13.PORTAADDR1
+address_a[1] => ram_block11a14.PORTAADDR1
+address_a[1] => ram_block11a15.PORTAADDR1
+address_a[2] => ram_block11a0.PORTAADDR2
+address_a[2] => ram_block11a1.PORTAADDR2
+address_a[2] => ram_block11a2.PORTAADDR2
+address_a[2] => ram_block11a3.PORTAADDR2
+address_a[2] => ram_block11a4.PORTAADDR2
+address_a[2] => ram_block11a5.PORTAADDR2
+address_a[2] => ram_block11a6.PORTAADDR2
+address_a[2] => ram_block11a7.PORTAADDR2
+address_a[2] => ram_block11a8.PORTAADDR2
+address_a[2] => ram_block11a9.PORTAADDR2
+address_a[2] => ram_block11a10.PORTAADDR2
+address_a[2] => ram_block11a11.PORTAADDR2
+address_a[2] => ram_block11a12.PORTAADDR2
+address_a[2] => ram_block11a13.PORTAADDR2
+address_a[2] => ram_block11a14.PORTAADDR2
+address_a[2] => ram_block11a15.PORTAADDR2
+address_a[3] => ram_block11a0.PORTAADDR3
+address_a[3] => ram_block11a1.PORTAADDR3
+address_a[3] => ram_block11a2.PORTAADDR3
+address_a[3] => ram_block11a3.PORTAADDR3
+address_a[3] => ram_block11a4.PORTAADDR3
+address_a[3] => ram_block11a5.PORTAADDR3
+address_a[3] => ram_block11a6.PORTAADDR3
+address_a[3] => ram_block11a7.PORTAADDR3
+address_a[3] => ram_block11a8.PORTAADDR3
+address_a[3] => ram_block11a9.PORTAADDR3
+address_a[3] => ram_block11a10.PORTAADDR3
+address_a[3] => ram_block11a11.PORTAADDR3
+address_a[3] => ram_block11a12.PORTAADDR3
+address_a[3] => ram_block11a13.PORTAADDR3
+address_a[3] => ram_block11a14.PORTAADDR3
+address_a[3] => ram_block11a15.PORTAADDR3
+address_a[4] => ram_block11a0.PORTAADDR4
+address_a[4] => ram_block11a1.PORTAADDR4
+address_a[4] => ram_block11a2.PORTAADDR4
+address_a[4] => ram_block11a3.PORTAADDR4
+address_a[4] => ram_block11a4.PORTAADDR4
+address_a[4] => ram_block11a5.PORTAADDR4
+address_a[4] => ram_block11a6.PORTAADDR4
+address_a[4] => ram_block11a7.PORTAADDR4
+address_a[4] => ram_block11a8.PORTAADDR4
+address_a[4] => ram_block11a9.PORTAADDR4
+address_a[4] => ram_block11a10.PORTAADDR4
+address_a[4] => ram_block11a11.PORTAADDR4
+address_a[4] => ram_block11a12.PORTAADDR4
+address_a[4] => ram_block11a13.PORTAADDR4
+address_a[4] => ram_block11a14.PORTAADDR4
+address_a[4] => ram_block11a15.PORTAADDR4
+address_a[5] => ram_block11a0.PORTAADDR5
+address_a[5] => ram_block11a1.PORTAADDR5
+address_a[5] => ram_block11a2.PORTAADDR5
+address_a[5] => ram_block11a3.PORTAADDR5
+address_a[5] => ram_block11a4.PORTAADDR5
+address_a[5] => ram_block11a5.PORTAADDR5
+address_a[5] => ram_block11a6.PORTAADDR5
+address_a[5] => ram_block11a7.PORTAADDR5
+address_a[5] => ram_block11a8.PORTAADDR5
+address_a[5] => ram_block11a9.PORTAADDR5
+address_a[5] => ram_block11a10.PORTAADDR5
+address_a[5] => ram_block11a11.PORTAADDR5
+address_a[5] => ram_block11a12.PORTAADDR5
+address_a[5] => ram_block11a13.PORTAADDR5
+address_a[5] => ram_block11a14.PORTAADDR5
+address_a[5] => ram_block11a15.PORTAADDR5
+address_a[6] => ram_block11a0.PORTAADDR6
+address_a[6] => ram_block11a1.PORTAADDR6
+address_a[6] => ram_block11a2.PORTAADDR6
+address_a[6] => ram_block11a3.PORTAADDR6
+address_a[6] => ram_block11a4.PORTAADDR6
+address_a[6] => ram_block11a5.PORTAADDR6
+address_a[6] => ram_block11a6.PORTAADDR6
+address_a[6] => ram_block11a7.PORTAADDR6
+address_a[6] => ram_block11a8.PORTAADDR6
+address_a[6] => ram_block11a9.PORTAADDR6
+address_a[6] => ram_block11a10.PORTAADDR6
+address_a[6] => ram_block11a11.PORTAADDR6
+address_a[6] => ram_block11a12.PORTAADDR6
+address_a[6] => ram_block11a13.PORTAADDR6
+address_a[6] => ram_block11a14.PORTAADDR6
+address_a[6] => ram_block11a15.PORTAADDR6
+address_a[7] => ram_block11a0.PORTAADDR7
+address_a[7] => ram_block11a1.PORTAADDR7
+address_a[7] => ram_block11a2.PORTAADDR7
+address_a[7] => ram_block11a3.PORTAADDR7
+address_a[7] => ram_block11a4.PORTAADDR7
+address_a[7] => ram_block11a5.PORTAADDR7
+address_a[7] => ram_block11a6.PORTAADDR7
+address_a[7] => ram_block11a7.PORTAADDR7
+address_a[7] => ram_block11a8.PORTAADDR7
+address_a[7] => ram_block11a9.PORTAADDR7
+address_a[7] => ram_block11a10.PORTAADDR7
+address_a[7] => ram_block11a11.PORTAADDR7
+address_a[7] => ram_block11a12.PORTAADDR7
+address_a[7] => ram_block11a13.PORTAADDR7
+address_a[7] => ram_block11a14.PORTAADDR7
+address_a[7] => ram_block11a15.PORTAADDR7
+address_a[8] => ram_block11a0.PORTAADDR8
+address_a[8] => ram_block11a1.PORTAADDR8
+address_a[8] => ram_block11a2.PORTAADDR8
+address_a[8] => ram_block11a3.PORTAADDR8
+address_a[8] => ram_block11a4.PORTAADDR8
+address_a[8] => ram_block11a5.PORTAADDR8
+address_a[8] => ram_block11a6.PORTAADDR8
+address_a[8] => ram_block11a7.PORTAADDR8
+address_a[8] => ram_block11a8.PORTAADDR8
+address_a[8] => ram_block11a9.PORTAADDR8
+address_a[8] => ram_block11a10.PORTAADDR8
+address_a[8] => ram_block11a11.PORTAADDR8
+address_a[8] => ram_block11a12.PORTAADDR8
+address_a[8] => ram_block11a13.PORTAADDR8
+address_a[8] => ram_block11a14.PORTAADDR8
+address_a[8] => ram_block11a15.PORTAADDR8
+address_b[0] => ram_block11a0.PORTBADDR
+address_b[0] => ram_block11a1.PORTBADDR
+address_b[0] => ram_block11a2.PORTBADDR
+address_b[0] => ram_block11a3.PORTBADDR
+address_b[0] => ram_block11a4.PORTBADDR
+address_b[0] => ram_block11a5.PORTBADDR
+address_b[0] => ram_block11a6.PORTBADDR
+address_b[0] => ram_block11a7.PORTBADDR
+address_b[0] => ram_block11a8.PORTBADDR
+address_b[0] => ram_block11a9.PORTBADDR
+address_b[0] => ram_block11a10.PORTBADDR
+address_b[0] => ram_block11a11.PORTBADDR
+address_b[0] => ram_block11a12.PORTBADDR
+address_b[0] => ram_block11a13.PORTBADDR
+address_b[0] => ram_block11a14.PORTBADDR
+address_b[0] => ram_block11a15.PORTBADDR
+address_b[1] => ram_block11a0.PORTBADDR1
+address_b[1] => ram_block11a1.PORTBADDR1
+address_b[1] => ram_block11a2.PORTBADDR1
+address_b[1] => ram_block11a3.PORTBADDR1
+address_b[1] => ram_block11a4.PORTBADDR1
+address_b[1] => ram_block11a5.PORTBADDR1
+address_b[1] => ram_block11a6.PORTBADDR1
+address_b[1] => ram_block11a7.PORTBADDR1
+address_b[1] => ram_block11a8.PORTBADDR1
+address_b[1] => ram_block11a9.PORTBADDR1
+address_b[1] => ram_block11a10.PORTBADDR1
+address_b[1] => ram_block11a11.PORTBADDR1
+address_b[1] => ram_block11a12.PORTBADDR1
+address_b[1] => ram_block11a13.PORTBADDR1
+address_b[1] => ram_block11a14.PORTBADDR1
+address_b[1] => ram_block11a15.PORTBADDR1
+address_b[2] => ram_block11a0.PORTBADDR2
+address_b[2] => ram_block11a1.PORTBADDR2
+address_b[2] => ram_block11a2.PORTBADDR2
+address_b[2] => ram_block11a3.PORTBADDR2
+address_b[2] => ram_block11a4.PORTBADDR2
+address_b[2] => ram_block11a5.PORTBADDR2
+address_b[2] => ram_block11a6.PORTBADDR2
+address_b[2] => ram_block11a7.PORTBADDR2
+address_b[2] => ram_block11a8.PORTBADDR2
+address_b[2] => ram_block11a9.PORTBADDR2
+address_b[2] => ram_block11a10.PORTBADDR2
+address_b[2] => ram_block11a11.PORTBADDR2
+address_b[2] => ram_block11a12.PORTBADDR2
+address_b[2] => ram_block11a13.PORTBADDR2
+address_b[2] => ram_block11a14.PORTBADDR2
+address_b[2] => ram_block11a15.PORTBADDR2
+address_b[3] => ram_block11a0.PORTBADDR3
+address_b[3] => ram_block11a1.PORTBADDR3
+address_b[3] => ram_block11a2.PORTBADDR3
+address_b[3] => ram_block11a3.PORTBADDR3
+address_b[3] => ram_block11a4.PORTBADDR3
+address_b[3] => ram_block11a5.PORTBADDR3
+address_b[3] => ram_block11a6.PORTBADDR3
+address_b[3] => ram_block11a7.PORTBADDR3
+address_b[3] => ram_block11a8.PORTBADDR3
+address_b[3] => ram_block11a9.PORTBADDR3
+address_b[3] => ram_block11a10.PORTBADDR3
+address_b[3] => ram_block11a11.PORTBADDR3
+address_b[3] => ram_block11a12.PORTBADDR3
+address_b[3] => ram_block11a13.PORTBADDR3
+address_b[3] => ram_block11a14.PORTBADDR3
+address_b[3] => ram_block11a15.PORTBADDR3
+address_b[4] => ram_block11a0.PORTBADDR4
+address_b[4] => ram_block11a1.PORTBADDR4
+address_b[4] => ram_block11a2.PORTBADDR4
+address_b[4] => ram_block11a3.PORTBADDR4
+address_b[4] => ram_block11a4.PORTBADDR4
+address_b[4] => ram_block11a5.PORTBADDR4
+address_b[4] => ram_block11a6.PORTBADDR4
+address_b[4] => ram_block11a7.PORTBADDR4
+address_b[4] => ram_block11a8.PORTBADDR4
+address_b[4] => ram_block11a9.PORTBADDR4
+address_b[4] => ram_block11a10.PORTBADDR4
+address_b[4] => ram_block11a11.PORTBADDR4
+address_b[4] => ram_block11a12.PORTBADDR4
+address_b[4] => ram_block11a13.PORTBADDR4
+address_b[4] => ram_block11a14.PORTBADDR4
+address_b[4] => ram_block11a15.PORTBADDR4
+address_b[5] => ram_block11a0.PORTBADDR5
+address_b[5] => ram_block11a1.PORTBADDR5
+address_b[5] => ram_block11a2.PORTBADDR5
+address_b[5] => ram_block11a3.PORTBADDR5
+address_b[5] => ram_block11a4.PORTBADDR5
+address_b[5] => ram_block11a5.PORTBADDR5
+address_b[5] => ram_block11a6.PORTBADDR5
+address_b[5] => ram_block11a7.PORTBADDR5
+address_b[5] => ram_block11a8.PORTBADDR5
+address_b[5] => ram_block11a9.PORTBADDR5
+address_b[5] => ram_block11a10.PORTBADDR5
+address_b[5] => ram_block11a11.PORTBADDR5
+address_b[5] => ram_block11a12.PORTBADDR5
+address_b[5] => ram_block11a13.PORTBADDR5
+address_b[5] => ram_block11a14.PORTBADDR5
+address_b[5] => ram_block11a15.PORTBADDR5
+address_b[6] => ram_block11a0.PORTBADDR6
+address_b[6] => ram_block11a1.PORTBADDR6
+address_b[6] => ram_block11a2.PORTBADDR6
+address_b[6] => ram_block11a3.PORTBADDR6
+address_b[6] => ram_block11a4.PORTBADDR6
+address_b[6] => ram_block11a5.PORTBADDR6
+address_b[6] => ram_block11a6.PORTBADDR6
+address_b[6] => ram_block11a7.PORTBADDR6
+address_b[6] => ram_block11a8.PORTBADDR6
+address_b[6] => ram_block11a9.PORTBADDR6
+address_b[6] => ram_block11a10.PORTBADDR6
+address_b[6] => ram_block11a11.PORTBADDR6
+address_b[6] => ram_block11a12.PORTBADDR6
+address_b[6] => ram_block11a13.PORTBADDR6
+address_b[6] => ram_block11a14.PORTBADDR6
+address_b[6] => ram_block11a15.PORTBADDR6
+address_b[7] => ram_block11a0.PORTBADDR7
+address_b[7] => ram_block11a1.PORTBADDR7
+address_b[7] => ram_block11a2.PORTBADDR7
+address_b[7] => ram_block11a3.PORTBADDR7
+address_b[7] => ram_block11a4.PORTBADDR7
+address_b[7] => ram_block11a5.PORTBADDR7
+address_b[7] => ram_block11a6.PORTBADDR7
+address_b[7] => ram_block11a7.PORTBADDR7
+address_b[7] => ram_block11a8.PORTBADDR7
+address_b[7] => ram_block11a9.PORTBADDR7
+address_b[7] => ram_block11a10.PORTBADDR7
+address_b[7] => ram_block11a11.PORTBADDR7
+address_b[7] => ram_block11a12.PORTBADDR7
+address_b[7] => ram_block11a13.PORTBADDR7
+address_b[7] => ram_block11a14.PORTBADDR7
+address_b[7] => ram_block11a15.PORTBADDR7
+address_b[8] => ram_block11a0.PORTBADDR8
+address_b[8] => ram_block11a1.PORTBADDR8
+address_b[8] => ram_block11a2.PORTBADDR8
+address_b[8] => ram_block11a3.PORTBADDR8
+address_b[8] => ram_block11a4.PORTBADDR8
+address_b[8] => ram_block11a5.PORTBADDR8
+address_b[8] => ram_block11a6.PORTBADDR8
+address_b[8] => ram_block11a7.PORTBADDR8
+address_b[8] => ram_block11a8.PORTBADDR8
+address_b[8] => ram_block11a9.PORTBADDR8
+address_b[8] => ram_block11a10.PORTBADDR8
+address_b[8] => ram_block11a11.PORTBADDR8
+address_b[8] => ram_block11a12.PORTBADDR8
+address_b[8] => ram_block11a13.PORTBADDR8
+address_b[8] => ram_block11a14.PORTBADDR8
+address_b[8] => ram_block11a15.PORTBADDR8
+addressstall_b => ram_block11a0.PORTBADDRSTALL
+addressstall_b => ram_block11a1.PORTBADDRSTALL
+addressstall_b => ram_block11a2.PORTBADDRSTALL
+addressstall_b => ram_block11a3.PORTBADDRSTALL
+addressstall_b => ram_block11a4.PORTBADDRSTALL
+addressstall_b => ram_block11a5.PORTBADDRSTALL
+addressstall_b => ram_block11a6.PORTBADDRSTALL
+addressstall_b => ram_block11a7.PORTBADDRSTALL
+addressstall_b => ram_block11a8.PORTBADDRSTALL
+addressstall_b => ram_block11a9.PORTBADDRSTALL
+addressstall_b => ram_block11a10.PORTBADDRSTALL
+addressstall_b => ram_block11a11.PORTBADDRSTALL
+addressstall_b => ram_block11a12.PORTBADDRSTALL
+addressstall_b => ram_block11a13.PORTBADDRSTALL
+addressstall_b => ram_block11a14.PORTBADDRSTALL
+addressstall_b => ram_block11a15.PORTBADDRSTALL
+clock0 => ram_block11a0.CLK0
+clock0 => ram_block11a1.CLK0
+clock0 => ram_block11a2.CLK0
+clock0 => ram_block11a3.CLK0
+clock0 => ram_block11a4.CLK0
+clock0 => ram_block11a5.CLK0
+clock0 => ram_block11a6.CLK0
+clock0 => ram_block11a7.CLK0
+clock0 => ram_block11a8.CLK0
+clock0 => ram_block11a9.CLK0
+clock0 => ram_block11a10.CLK0
+clock0 => ram_block11a11.CLK0
+clock0 => ram_block11a12.CLK0
+clock0 => ram_block11a13.CLK0
+clock0 => ram_block11a14.CLK0
+clock0 => ram_block11a15.CLK0
+clock1 => ram_block11a0.CLK1
+clock1 => ram_block11a1.CLK1
+clock1 => ram_block11a2.CLK1
+clock1 => ram_block11a3.CLK1
+clock1 => ram_block11a4.CLK1
+clock1 => ram_block11a5.CLK1
+clock1 => ram_block11a6.CLK1
+clock1 => ram_block11a7.CLK1
+clock1 => ram_block11a8.CLK1
+clock1 => ram_block11a9.CLK1
+clock1 => ram_block11a10.CLK1
+clock1 => ram_block11a11.CLK1
+clock1 => ram_block11a12.CLK1
+clock1 => ram_block11a13.CLK1
+clock1 => ram_block11a14.CLK1
+clock1 => ram_block11a15.CLK1
+clocken1 => ram_block11a0.ENA1
+clocken1 => ram_block11a1.ENA1
+clocken1 => ram_block11a2.ENA1
+clocken1 => ram_block11a3.ENA1
+clocken1 => ram_block11a4.ENA1
+clocken1 => ram_block11a5.ENA1
+clocken1 => ram_block11a6.ENA1
+clocken1 => ram_block11a7.ENA1
+clocken1 => ram_block11a8.ENA1
+clocken1 => ram_block11a9.ENA1
+clocken1 => ram_block11a10.ENA1
+clocken1 => ram_block11a11.ENA1
+clocken1 => ram_block11a12.ENA1
+clocken1 => ram_block11a13.ENA1
+clocken1 => ram_block11a14.ENA1
+clocken1 => ram_block11a15.ENA1
+data_a[0] => ram_block11a0.PORTADATAIN
+data_a[1] => ram_block11a1.PORTADATAIN
+data_a[2] => ram_block11a2.PORTADATAIN
+data_a[3] => ram_block11a3.PORTADATAIN
+data_a[4] => ram_block11a4.PORTADATAIN
+data_a[5] => ram_block11a5.PORTADATAIN
+data_a[6] => ram_block11a6.PORTADATAIN
+data_a[7] => ram_block11a7.PORTADATAIN
+data_a[8] => ram_block11a8.PORTADATAIN
+data_a[9] => ram_block11a9.PORTADATAIN
+data_a[10] => ram_block11a10.PORTADATAIN
+data_a[11] => ram_block11a11.PORTADATAIN
+data_a[12] => ram_block11a12.PORTADATAIN
+data_a[13] => ram_block11a13.PORTADATAIN
+data_a[14] => ram_block11a14.PORTADATAIN
+data_a[15] => ram_block11a15.PORTADATAIN
+q_b[0] <= ram_block11a0.PORTBDATAOUT
+q_b[1] <= ram_block11a1.PORTBDATAOUT
+q_b[2] <= ram_block11a2.PORTBDATAOUT
+q_b[3] <= ram_block11a3.PORTBDATAOUT
+q_b[4] <= ram_block11a4.PORTBDATAOUT
+q_b[5] <= ram_block11a5.PORTBDATAOUT
+q_b[6] <= ram_block11a6.PORTBDATAOUT
+q_b[7] <= ram_block11a7.PORTBDATAOUT
+q_b[8] <= ram_block11a8.PORTBDATAOUT
+q_b[9] <= ram_block11a9.PORTBDATAOUT
+q_b[10] <= ram_block11a10.PORTBDATAOUT
+q_b[11] <= ram_block11a11.PORTBDATAOUT
+q_b[12] <= ram_block11a12.PORTBDATAOUT
+q_b[13] <= ram_block11a13.PORTBDATAOUT
+q_b[14] <= ram_block11a14.PORTBDATAOUT
+q_b[15] <= ram_block11a15.PORTBDATAOUT
+wren_a => ram_block11a0.PORTAWE
+wren_a => ram_block11a0.ENA0
+wren_a => ram_block11a1.PORTAWE
+wren_a => ram_block11a1.ENA0
+wren_a => ram_block11a2.PORTAWE
+wren_a => ram_block11a2.ENA0
+wren_a => ram_block11a3.PORTAWE
+wren_a => ram_block11a3.ENA0
+wren_a => ram_block11a4.PORTAWE
+wren_a => ram_block11a4.ENA0
+wren_a => ram_block11a5.PORTAWE
+wren_a => ram_block11a5.ENA0
+wren_a => ram_block11a6.PORTAWE
+wren_a => ram_block11a6.ENA0
+wren_a => ram_block11a7.PORTAWE
+wren_a => ram_block11a7.ENA0
+wren_a => ram_block11a8.PORTAWE
+wren_a => ram_block11a8.ENA0
+wren_a => ram_block11a9.PORTAWE
+wren_a => ram_block11a9.ENA0
+wren_a => ram_block11a10.PORTAWE
+wren_a => ram_block11a10.ENA0
+wren_a => ram_block11a11.PORTAWE
+wren_a => ram_block11a11.ENA0
+wren_a => ram_block11a12.PORTAWE
+wren_a => ram_block11a12.ENA0
+wren_a => ram_block11a13.PORTAWE
+wren_a => ram_block11a13.ENA0
+wren_a => ram_block11a14.PORTAWE
+wren_a => ram_block11a14.ENA0
+wren_a => ram_block11a15.PORTAWE
+wren_a => ram_block11a15.ENA0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+clock => dffpipe_pe9:dffpipe13.clock
+clrn => dffpipe_pe9:dffpipe13.clrn
+d[0] => dffpipe_pe9:dffpipe13.d[0]
+d[1] => dffpipe_pe9:dffpipe13.d[1]
+d[2] => dffpipe_pe9:dffpipe13.d[2]
+d[3] => dffpipe_pe9:dffpipe13.d[3]
+d[4] => dffpipe_pe9:dffpipe13.d[4]
+d[5] => dffpipe_pe9:dffpipe13.d[5]
+d[6] => dffpipe_pe9:dffpipe13.d[6]
+d[7] => dffpipe_pe9:dffpipe13.d[7]
+d[8] => dffpipe_pe9:dffpipe13.d[8]
+d[9] => dffpipe_pe9:dffpipe13.d[9]
+q[0] <= dffpipe_pe9:dffpipe13.q[0]
+q[1] <= dffpipe_pe9:dffpipe13.q[1]
+q[2] <= dffpipe_pe9:dffpipe13.q[2]
+q[3] <= dffpipe_pe9:dffpipe13.q[3]
+q[4] <= dffpipe_pe9:dffpipe13.q[4]
+q[5] <= dffpipe_pe9:dffpipe13.q[5]
+q[6] <= dffpipe_pe9:dffpipe13.q[6]
+q[7] <= dffpipe_pe9:dffpipe13.q[7]
+q[8] <= dffpipe_pe9:dffpipe13.q[8]
+q[9] <= dffpipe_pe9:dffpipe13.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+clock => dffe14a[9].CLK
+clock => dffe14a[8].CLK
+clock => dffe14a[7].CLK
+clock => dffe14a[6].CLK
+clock => dffe14a[5].CLK
+clock => dffe14a[4].CLK
+clock => dffe14a[3].CLK
+clock => dffe14a[2].CLK
+clock => dffe14a[1].CLK
+clock => dffe14a[0].CLK
+clock => dffe15a[9].CLK
+clock => dffe15a[8].CLK
+clock => dffe15a[7].CLK
+clock => dffe15a[6].CLK
+clock => dffe15a[5].CLK
+clock => dffe15a[4].CLK
+clock => dffe15a[3].CLK
+clock => dffe15a[2].CLK
+clock => dffe15a[1].CLK
+clock => dffe15a[0].CLK
+clrn => dffe14a[9].ACLR
+clrn => dffe14a[8].ACLR
+clrn => dffe14a[7].ACLR
+clrn => dffe14a[6].ACLR
+clrn => dffe14a[5].ACLR
+clrn => dffe14a[4].ACLR
+clrn => dffe14a[3].ACLR
+clrn => dffe14a[2].ACLR
+clrn => dffe14a[1].ACLR
+clrn => dffe14a[0].ACLR
+clrn => dffe15a[9].ACLR
+clrn => dffe15a[8].ACLR
+clrn => dffe15a[7].ACLR
+clrn => dffe15a[6].ACLR
+clrn => dffe15a[5].ACLR
+clrn => dffe15a[4].ACLR
+clrn => dffe15a[3].ACLR
+clrn => dffe15a[2].ACLR
+clrn => dffe15a[1].ACLR
+clrn => dffe15a[0].ACLR
+d[0] => dffe14a[0].IN0
+d[1] => dffe14a[1].IN0
+d[2] => dffe14a[2].IN0
+d[3] => dffe14a[3].IN0
+d[4] => dffe14a[4].IN0
+d[5] => dffe14a[5].IN0
+d[6] => dffe14a[6].IN0
+d[7] => dffe14a[7].IN0
+d[8] => dffe14a[8].IN0
+d[9] => dffe14a[9].IN0
+q[0] <= dffe15a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe15a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe15a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe15a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe15a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe15a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe15a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe15a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe15a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe15a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+clock => dffpipe_qe9:dffpipe16.clock
+clrn => dffpipe_qe9:dffpipe16.clrn
+d[0] => dffpipe_qe9:dffpipe16.d[0]
+d[1] => dffpipe_qe9:dffpipe16.d[1]
+d[2] => dffpipe_qe9:dffpipe16.d[2]
+d[3] => dffpipe_qe9:dffpipe16.d[3]
+d[4] => dffpipe_qe9:dffpipe16.d[4]
+d[5] => dffpipe_qe9:dffpipe16.d[5]
+d[6] => dffpipe_qe9:dffpipe16.d[6]
+d[7] => dffpipe_qe9:dffpipe16.d[7]
+d[8] => dffpipe_qe9:dffpipe16.d[8]
+d[9] => dffpipe_qe9:dffpipe16.d[9]
+q[0] <= dffpipe_qe9:dffpipe16.q[0]
+q[1] <= dffpipe_qe9:dffpipe16.q[1]
+q[2] <= dffpipe_qe9:dffpipe16.q[2]
+q[3] <= dffpipe_qe9:dffpipe16.q[3]
+q[4] <= dffpipe_qe9:dffpipe16.q[4]
+q[5] <= dffpipe_qe9:dffpipe16.q[5]
+q[6] <= dffpipe_qe9:dffpipe16.q[6]
+q[7] <= dffpipe_qe9:dffpipe16.q[7]
+q[8] <= dffpipe_qe9:dffpipe16.q[8]
+q[9] <= dffpipe_qe9:dffpipe16.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+clock => dffe17a[9].CLK
+clock => dffe17a[8].CLK
+clock => dffe17a[7].CLK
+clock => dffe17a[6].CLK
+clock => dffe17a[5].CLK
+clock => dffe17a[4].CLK
+clock => dffe17a[3].CLK
+clock => dffe17a[2].CLK
+clock => dffe17a[1].CLK
+clock => dffe17a[0].CLK
+clock => dffe18a[9].CLK
+clock => dffe18a[8].CLK
+clock => dffe18a[7].CLK
+clock => dffe18a[6].CLK
+clock => dffe18a[5].CLK
+clock => dffe18a[4].CLK
+clock => dffe18a[3].CLK
+clock => dffe18a[2].CLK
+clock => dffe18a[1].CLK
+clock => dffe18a[0].CLK
+clrn => dffe17a[9].ACLR
+clrn => dffe17a[8].ACLR
+clrn => dffe17a[7].ACLR
+clrn => dffe17a[6].ACLR
+clrn => dffe17a[5].ACLR
+clrn => dffe17a[4].ACLR
+clrn => dffe17a[3].ACLR
+clrn => dffe17a[2].ACLR
+clrn => dffe17a[1].ACLR
+clrn => dffe17a[0].ACLR
+clrn => dffe18a[9].ACLR
+clrn => dffe18a[8].ACLR
+clrn => dffe18a[7].ACLR
+clrn => dffe18a[6].ACLR
+clrn => dffe18a[5].ACLR
+clrn => dffe18a[4].ACLR
+clrn => dffe18a[3].ACLR
+clrn => dffe18a[2].ACLR
+clrn => dffe18a[1].ACLR
+clrn => dffe18a[0].ACLR
+d[0] => dffe17a[0].IN0
+d[1] => dffe17a[1].IN0
+d[2] => dffe17a[2].IN0
+d[3] => dffe17a[3].IN0
+d[4] => dffe17a[4].IN0
+d[5] => dffe17a[5].IN0
+d[6] => dffe17a[6].IN0
+d[7] => dffe17a[7].IN0
+d[8] => dffe17a[8].IN0
+d[9] => dffe17a[9].IN0
+q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8
+iCLK => mI2C_CLK_DIV[0].CLK
+iCLK => mI2C_CLK_DIV[1].CLK
+iCLK => mI2C_CLK_DIV[2].CLK
+iCLK => mI2C_CLK_DIV[3].CLK
+iCLK => mI2C_CLK_DIV[4].CLK
+iCLK => mI2C_CLK_DIV[5].CLK
+iCLK => mI2C_CLK_DIV[6].CLK
+iCLK => mI2C_CLK_DIV[7].CLK
+iCLK => mI2C_CLK_DIV[8].CLK
+iCLK => mI2C_CLK_DIV[9].CLK
+iCLK => mI2C_CLK_DIV[10].CLK
+iCLK => mI2C_CLK_DIV[11].CLK
+iCLK => mI2C_CLK_DIV[12].CLK
+iCLK => mI2C_CLK_DIV[13].CLK
+iCLK => mI2C_CLK_DIV[14].CLK
+iCLK => mI2C_CLK_DIV[15].CLK
+iCLK => mI2C_CTRL_CLK.CLK
+iCLK => combo_cnt[0].CLK
+iCLK => combo_cnt[1].CLK
+iCLK => combo_cnt[2].CLK
+iCLK => combo_cnt[3].CLK
+iCLK => combo_cnt[4].CLK
+iCLK => combo_cnt[5].CLK
+iCLK => combo_cnt[6].CLK
+iCLK => combo_cnt[7].CLK
+iCLK => combo_cnt[8].CLK
+iCLK => combo_cnt[9].CLK
+iCLK => combo_cnt[10].CLK
+iCLK => combo_cnt[11].CLK
+iCLK => combo_cnt[12].CLK
+iCLK => combo_cnt[13].CLK
+iCLK => combo_cnt[14].CLK
+iCLK => combo_cnt[15].CLK
+iCLK => combo_cnt[16].CLK
+iCLK => combo_cnt[17].CLK
+iCLK => combo_cnt[18].CLK
+iCLK => combo_cnt[19].CLK
+iCLK => combo_cnt[20].CLK
+iCLK => combo_cnt[21].CLK
+iCLK => combo_cnt[22].CLK
+iCLK => combo_cnt[23].CLK
+iCLK => combo_cnt[24].CLK
+iCLK => sensor_exposure[0].CLK
+iCLK => sensor_exposure[1].CLK
+iCLK => sensor_exposure[2].CLK
+iCLK => sensor_exposure[3].CLK
+iCLK => sensor_exposure[4].CLK
+iCLK => sensor_exposure[5].CLK
+iCLK => sensor_exposure[6].CLK
+iCLK => sensor_exposure[7].CLK
+iCLK => sensor_exposure[8].CLK
+iCLK => sensor_exposure[9].CLK
+iCLK => sensor_exposure[10].CLK
+iCLK => sensor_exposure[11].CLK
+iCLK => sensor_exposure[12].CLK
+iCLK => sensor_exposure[13].CLK
+iCLK => sensor_exposure[14].CLK
+iCLK => sensor_exposure[15].CLK
+iCLK => iexposure_adj_delay[0].CLK
+iCLK => iexposure_adj_delay[1].CLK
+iCLK => iexposure_adj_delay[2].CLK
+iCLK => iexposure_adj_delay[3].CLK
+iRST_N => i2c_reset.IN1
+iRST_N => combo_cnt[0].ACLR
+iRST_N => combo_cnt[1].ACLR
+iRST_N => combo_cnt[2].ACLR
+iRST_N => combo_cnt[3].ACLR
+iRST_N => combo_cnt[4].ACLR
+iRST_N => combo_cnt[5].ACLR
+iRST_N => combo_cnt[6].ACLR
+iRST_N => combo_cnt[7].ACLR
+iRST_N => combo_cnt[8].ACLR
+iRST_N => combo_cnt[9].ACLR
+iRST_N => combo_cnt[10].ACLR
+iRST_N => combo_cnt[11].ACLR
+iRST_N => combo_cnt[12].ACLR
+iRST_N => combo_cnt[13].ACLR
+iRST_N => combo_cnt[14].ACLR
+iRST_N => combo_cnt[15].ACLR
+iRST_N => combo_cnt[16].ACLR
+iRST_N => combo_cnt[17].ACLR
+iRST_N => combo_cnt[18].ACLR
+iRST_N => combo_cnt[19].ACLR
+iRST_N => combo_cnt[20].ACLR
+iRST_N => combo_cnt[21].ACLR
+iRST_N => combo_cnt[22].ACLR
+iRST_N => combo_cnt[23].ACLR
+iRST_N => combo_cnt[24].ACLR
+iRST_N => sensor_exposure[0].ACLR
+iRST_N => sensor_exposure[1].ACLR
+iRST_N => sensor_exposure[2].ACLR
+iRST_N => sensor_exposure[3].ACLR
+iRST_N => sensor_exposure[4].ACLR
+iRST_N => sensor_exposure[5].ACLR
+iRST_N => sensor_exposure[6].PRESET
+iRST_N => sensor_exposure[7].PRESET
+iRST_N => sensor_exposure[8].PRESET
+iRST_N => sensor_exposure[9].PRESET
+iRST_N => sensor_exposure[10].PRESET
+iRST_N => sensor_exposure[11].ACLR
+iRST_N => sensor_exposure[12].ACLR
+iRST_N => sensor_exposure[13].ACLR
+iRST_N => sensor_exposure[14].ACLR
+iRST_N => sensor_exposure[15].ACLR
+iRST_N => iexposure_adj_delay[0].ACLR
+iRST_N => iexposure_adj_delay[1].ACLR
+iRST_N => iexposure_adj_delay[2].ACLR
+iRST_N => iexposure_adj_delay[3].ACLR
+iUART_CTRL => ~NO_FANOUT~
+iZOOM_MODE_SW => Mux18.IN69
+iZOOM_MODE_SW => Mux19.IN66
+iZOOM_MODE_SW => Mux21.IN69
+iZOOM_MODE_SW => Mux22.IN69
+iZOOM_MODE_SW => Mux19.IN67
+iZOOM_MODE_SW => Mux13.IN68
+iZOOM_MODE_SW => Mux16.IN69
+iZOOM_MODE_SW => Mux17.IN69
+iZOOM_MODE_SW => Mux12.IN69
+iZOOM_MODE_SW => Mux13.IN69
+iZOOM_MODE_SW => Mux15.IN69
+iZOOM_MODE_SW => Mux19.IN68
+iZOOM_MODE_SW => Mux23.IN68
+iZOOM_MODE_SW => Mux19.IN69
+iZOOM_MODE_SW => Mux23.IN69
+iEXPOSURE_ADJ => iexposure_adj_delay[0].DATAIN
+iEXPOSURE_ADJ => Equal0.IN0
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+I2C_SCLK <= I2C_Controller:u0.I2C_SCLK
+I2C_SDAT <> I2C_Controller:u0.I2C_SDAT
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0
+CLOCK => SD[0].CLK
+CLOCK => SD[1].CLK
+CLOCK => SD[2].CLK
+CLOCK => SD[3].CLK
+CLOCK => SD[4].CLK
+CLOCK => SD[5].CLK
+CLOCK => SD[6].CLK
+CLOCK => SD[7].CLK
+CLOCK => SD[8].CLK
+CLOCK => SD[9].CLK
+CLOCK => SD[10].CLK
+CLOCK => SD[11].CLK
+CLOCK => SD[12].CLK
+CLOCK => SD[13].CLK
+CLOCK => SD[14].CLK
+CLOCK => SD[15].CLK
+CLOCK => SD[16].CLK
+CLOCK => SD[17].CLK
+CLOCK => SD[18].CLK
+CLOCK => SD[19].CLK
+CLOCK => SD[20].CLK
+CLOCK => SD[21].CLK
+CLOCK => SD[22].CLK
+CLOCK => SD[23].CLK
+CLOCK => SD[24].CLK
+CLOCK => SD[25].CLK
+CLOCK => SD[26].CLK
+CLOCK => SD[27].CLK
+CLOCK => SD[28].CLK
+CLOCK => SD[29].CLK
+CLOCK => SD[30].CLK
+CLOCK => SD[31].CLK
+CLOCK => END~reg0.CLK
+CLOCK => ACK4.CLK
+CLOCK => ACK3.CLK
+CLOCK => ACK2.CLK
+CLOCK => ACK1.CLK
+CLOCK => SDO.CLK
+CLOCK => SCLK.CLK
+CLOCK => SD_COUNTER[0].CLK
+CLOCK => SD_COUNTER[1].CLK
+CLOCK => SD_COUNTER[2].CLK
+CLOCK => SD_COUNTER[3].CLK
+CLOCK => SD_COUNTER[4].CLK
+CLOCK => SD_COUNTER[5].CLK
+CLOCK => SD_COUNTER[6].CLK
+CLOCK => comb.DATAB
+I2C_SCLK <= comb.DB_MAX_OUTPUT_PORT_TYPE
+I2C_SDAT <> I2C_SDAT
+I2C_DATA[0] => SD.DATAB
+I2C_DATA[1] => SD.DATAB
+I2C_DATA[2] => SD.DATAB
+I2C_DATA[3] => SD.DATAB
+I2C_DATA[4] => SD.DATAB
+I2C_DATA[5] => SD.DATAB
+I2C_DATA[6] => SD.DATAB
+I2C_DATA[7] => SD.DATAB
+I2C_DATA[8] => SD.DATAB
+I2C_DATA[9] => SD.DATAB
+I2C_DATA[10] => SD.DATAB
+I2C_DATA[11] => SD.DATAB
+I2C_DATA[12] => SD.DATAB
+I2C_DATA[13] => SD.DATAB
+I2C_DATA[14] => SD.DATAB
+I2C_DATA[15] => SD.DATAB
+I2C_DATA[16] => SD.DATAB
+I2C_DATA[17] => SD.DATAB
+I2C_DATA[18] => SD.DATAB
+I2C_DATA[19] => SD.DATAB
+I2C_DATA[20] => SD.DATAB
+I2C_DATA[21] => SD.DATAB
+I2C_DATA[22] => SD.DATAB
+I2C_DATA[23] => SD.DATAB
+I2C_DATA[24] => SD.DATAB
+I2C_DATA[25] => SD.DATAB
+I2C_DATA[26] => SD.DATAB
+I2C_DATA[27] => SD.DATAB
+I2C_DATA[28] => SD.DATAB
+I2C_DATA[29] => SD.DATAB
+I2C_DATA[30] => SD.DATAB
+I2C_DATA[31] => SD.DATAB
+GO => SD_COUNTER.OUTPUTSELECT
+GO => SD_COUNTER.OUTPUTSELECT
+GO => SD_COUNTER.OUTPUTSELECT
+GO => SD_COUNTER.OUTPUTSELECT
+GO => SD_COUNTER.OUTPUTSELECT
+GO => SD_COUNTER.OUTPUTSELECT
+GO => SD_COUNTER.OUTPUTSELECT
+END <= END~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ACK <= comb.DB_MAX_OUTPUT_PORT_TYPE
+RESET => END~reg0.PRESET
+RESET => ACK4.ACLR
+RESET => ACK3.ACLR
+RESET => ACK2.ACLR
+RESET => ACK1.ACLR
+RESET => SDO.PRESET
+RESET => SCLK.PRESET
+RESET => SD_COUNTER[0].PRESET
+RESET => SD_COUNTER[1].PRESET
+RESET => SD_COUNTER[2].PRESET
+RESET => SD_COUNTER[3].PRESET
+RESET => SD_COUNTER[4].PRESET
+RESET => SD_COUNTER[5].PRESET
+RESET => SD_COUNTER[6].ACLR
+RESET => SD[0].ENA
+RESET => SD[31].ENA
+RESET => SD[30].ENA
+RESET => SD[29].ENA
+RESET => SD[28].ENA
+RESET => SD[27].ENA
+RESET => SD[26].ENA
+RESET => SD[25].ENA
+RESET => SD[24].ENA
+RESET => SD[23].ENA
+RESET => SD[22].ENA
+RESET => SD[21].ENA
+RESET => SD[20].ENA
+RESET => SD[19].ENA
+RESET => SD[18].ENA
+RESET => SD[17].ENA
+RESET => SD[16].ENA
+RESET => SD[15].ENA
+RESET => SD[14].ENA
+RESET => SD[13].ENA
+RESET => SD[12].ENA
+RESET => SD[11].ENA
+RESET => SD[10].ENA
+RESET => SD[9].ENA
+RESET => SD[8].ENA
+RESET => SD[7].ENA
+RESET => SD[6].ENA
+RESET => SD[5].ENA
+RESET => SD[4].ENA
+RESET => SD[3].ENA
+RESET => SD[2].ENA
+RESET => SD[1].ENA
+
+
+|TOP_DE0_CAMERA_MOUSE|ps2:inst6
+iSTART => always2.IN1
+iRST_n => y_latch[0].ACLR
+iRST_n => y_latch[1].ACLR
+iRST_n => y_latch[2].ACLR
+iRST_n => y_latch[3].ACLR
+iRST_n => y_latch[4].ACLR
+iRST_n => y_latch[5].ACLR
+iRST_n => y_latch[6].ACLR
+iRST_n => y_latch[7].ACLR
+iRST_n => x_latch[0].ACLR
+iRST_n => x_latch[1].ACLR
+iRST_n => x_latch[2].ACLR
+iRST_n => x_latch[3].ACLR
+iRST_n => x_latch[4].ACLR
+iRST_n => x_latch[5].ACLR
+iRST_n => x_latch[6].ACLR
+iRST_n => x_latch[7].ACLR
+iRST_n => midlatch.ACLR
+iRST_n => riglatch.ACLR
+iRST_n => leflatch.ACLR
+iRST_n => cur_state~3.DATAIN
+iCLK_50 => clk_div[0].CLK
+iCLK_50 => clk_div[1].CLK
+iCLK_50 => clk_div[2].CLK
+iCLK_50 => clk_div[3].CLK
+iCLK_50 => clk_div[4].CLK
+iCLK_50 => clk_div[5].CLK
+iCLK_50 => clk_div[6].CLK
+iCLK_50 => clk_div[7].CLK
+iCLK_50 => clk_div[8].CLK
+PS2_CLK <> PS2_CLK
+PS2_DAT <> PS2_DAT
+oLEFBUT <= leflatch.DB_MAX_OUTPUT_PORT_TYPE
+oRIGBUT <= riglatch.DB_MAX_OUTPUT_PORT_TYPE
+oMIDBUT <= midlatch.DB_MAX_OUTPUT_PORT_TYPE
+oX[0] <= x_latch[0].DB_MAX_OUTPUT_PORT_TYPE
+oX[1] <= x_latch[1].DB_MAX_OUTPUT_PORT_TYPE
+oX[2] <= x_latch[2].DB_MAX_OUTPUT_PORT_TYPE
+oX[3] <= x_latch[3].DB_MAX_OUTPUT_PORT_TYPE
+oX[4] <= x_latch[4].DB_MAX_OUTPUT_PORT_TYPE
+oX[5] <= x_latch[5].DB_MAX_OUTPUT_PORT_TYPE
+oX[6] <= x_latch[6].DB_MAX_OUTPUT_PORT_TYPE
+oX[7] <= x_latch[7].DB_MAX_OUTPUT_PORT_TYPE
+oY[0] <= y_latch[0].DB_MAX_OUTPUT_PORT_TYPE
+oY[1] <= y_latch[1].DB_MAX_OUTPUT_PORT_TYPE
+oY[2] <= y_latch[2].DB_MAX_OUTPUT_PORT_TYPE
+oY[3] <= y_latch[3].DB_MAX_OUTPUT_PORT_TYPE
+oY[4] <= y_latch[4].DB_MAX_OUTPUT_PORT_TYPE
+oY[5] <= y_latch[5].DB_MAX_OUTPUT_PORT_TYPE
+oY[6] <= y_latch[6].DB_MAX_OUTPUT_PORT_TYPE
+oY[7] <= y_latch[7].DB_MAX_OUTPUT_PORT_TYPE
+oX_MOV1[0] <= SEG7_LUT:U1.oSEG
+oX_MOV1[1] <= SEG7_LUT:U1.oSEG
+oX_MOV1[2] <= SEG7_LUT:U1.oSEG
+oX_MOV1[3] <= SEG7_LUT:U1.oSEG
+oX_MOV1[4] <= SEG7_LUT:U1.oSEG
+oX_MOV1[5] <= SEG7_LUT:U1.oSEG
+oX_MOV1[6] <= SEG7_LUT:U1.oSEG
+oX_MOV2[0] <= SEG7_LUT:U2.oSEG
+oX_MOV2[1] <= SEG7_LUT:U2.oSEG
+oX_MOV2[2] <= SEG7_LUT:U2.oSEG
+oX_MOV2[3] <= SEG7_LUT:U2.oSEG
+oX_MOV2[4] <= SEG7_LUT:U2.oSEG
+oX_MOV2[5] <= SEG7_LUT:U2.oSEG
+oX_MOV2[6] <= SEG7_LUT:U2.oSEG
+oY_MOV1[0] <= SEG7_LUT:U3.oSEG
+oY_MOV1[1] <= SEG7_LUT:U3.oSEG
+oY_MOV1[2] <= SEG7_LUT:U3.oSEG
+oY_MOV1[3] <= SEG7_LUT:U3.oSEG
+oY_MOV1[4] <= SEG7_LUT:U3.oSEG
+oY_MOV1[5] <= SEG7_LUT:U3.oSEG
+oY_MOV1[6] <= SEG7_LUT:U3.oSEG
+oY_MOV2[0] <= SEG7_LUT:U4.oSEG
+oY_MOV2[1] <= SEG7_LUT:U4.oSEG
+oY_MOV2[2] <= SEG7_LUT:U4.oSEG
+oY_MOV2[3] <= SEG7_LUT:U4.oSEG
+oY_MOV2[4] <= SEG7_LUT:U4.oSEG
+oY_MOV2[5] <= SEG7_LUT:U4.oSEG
+oY_MOV2[6] <= SEG7_LUT:U4.oSEG
+
+
+|TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U1
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U2
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U3
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U4
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mux:inst10
+data0x[0] => LPM_MUX:LPM_MUX_component.DATA[0][0]
+data0x[1] => LPM_MUX:LPM_MUX_component.DATA[0][1]
+data0x[2] => LPM_MUX:LPM_MUX_component.DATA[0][2]
+data0x[3] => LPM_MUX:LPM_MUX_component.DATA[0][3]
+data0x[4] => LPM_MUX:LPM_MUX_component.DATA[0][4]
+data0x[5] => LPM_MUX:LPM_MUX_component.DATA[0][5]
+data0x[6] => LPM_MUX:LPM_MUX_component.DATA[0][6]
+data0x[7] => LPM_MUX:LPM_MUX_component.DATA[0][7]
+data0x[8] => LPM_MUX:LPM_MUX_component.DATA[0][8]
+data0x[9] => LPM_MUX:LPM_MUX_component.DATA[0][9]
+data0x[10] => LPM_MUX:LPM_MUX_component.DATA[0][10]
+data0x[11] => LPM_MUX:LPM_MUX_component.DATA[0][11]
+data0x[12] => LPM_MUX:LPM_MUX_component.DATA[0][12]
+data0x[13] => LPM_MUX:LPM_MUX_component.DATA[0][13]
+data0x[14] => LPM_MUX:LPM_MUX_component.DATA[0][14]
+data0x[15] => LPM_MUX:LPM_MUX_component.DATA[0][15]
+data0x[16] => LPM_MUX:LPM_MUX_component.DATA[0][16]
+data0x[17] => LPM_MUX:LPM_MUX_component.DATA[0][17]
+data0x[18] => LPM_MUX:LPM_MUX_component.DATA[0][18]
+data0x[19] => LPM_MUX:LPM_MUX_component.DATA[0][19]
+data0x[20] => LPM_MUX:LPM_MUX_component.DATA[0][20]
+data0x[21] => LPM_MUX:LPM_MUX_component.DATA[0][21]
+data0x[22] => LPM_MUX:LPM_MUX_component.DATA[0][22]
+data0x[23] => LPM_MUX:LPM_MUX_component.DATA[0][23]
+data0x[24] => LPM_MUX:LPM_MUX_component.DATA[0][24]
+data0x[25] => LPM_MUX:LPM_MUX_component.DATA[0][25]
+data0x[26] => LPM_MUX:LPM_MUX_component.DATA[0][26]
+data0x[27] => LPM_MUX:LPM_MUX_component.DATA[0][27]
+data0x[28] => LPM_MUX:LPM_MUX_component.DATA[0][28]
+data0x[29] => LPM_MUX:LPM_MUX_component.DATA[0][29]
+data1x[0] => LPM_MUX:LPM_MUX_component.DATA[1][0]
+data1x[1] => LPM_MUX:LPM_MUX_component.DATA[1][1]
+data1x[2] => LPM_MUX:LPM_MUX_component.DATA[1][2]
+data1x[3] => LPM_MUX:LPM_MUX_component.DATA[1][3]
+data1x[4] => LPM_MUX:LPM_MUX_component.DATA[1][4]
+data1x[5] => LPM_MUX:LPM_MUX_component.DATA[1][5]
+data1x[6] => LPM_MUX:LPM_MUX_component.DATA[1][6]
+data1x[7] => LPM_MUX:LPM_MUX_component.DATA[1][7]
+data1x[8] => LPM_MUX:LPM_MUX_component.DATA[1][8]
+data1x[9] => LPM_MUX:LPM_MUX_component.DATA[1][9]
+data1x[10] => LPM_MUX:LPM_MUX_component.DATA[1][10]
+data1x[11] => LPM_MUX:LPM_MUX_component.DATA[1][11]
+data1x[12] => LPM_MUX:LPM_MUX_component.DATA[1][12]
+data1x[13] => LPM_MUX:LPM_MUX_component.DATA[1][13]
+data1x[14] => LPM_MUX:LPM_MUX_component.DATA[1][14]
+data1x[15] => LPM_MUX:LPM_MUX_component.DATA[1][15]
+data1x[16] => LPM_MUX:LPM_MUX_component.DATA[1][16]
+data1x[17] => LPM_MUX:LPM_MUX_component.DATA[1][17]
+data1x[18] => LPM_MUX:LPM_MUX_component.DATA[1][18]
+data1x[19] => LPM_MUX:LPM_MUX_component.DATA[1][19]
+data1x[20] => LPM_MUX:LPM_MUX_component.DATA[1][20]
+data1x[21] => LPM_MUX:LPM_MUX_component.DATA[1][21]
+data1x[22] => LPM_MUX:LPM_MUX_component.DATA[1][22]
+data1x[23] => LPM_MUX:LPM_MUX_component.DATA[1][23]
+data1x[24] => LPM_MUX:LPM_MUX_component.DATA[1][24]
+data1x[25] => LPM_MUX:LPM_MUX_component.DATA[1][25]
+data1x[26] => LPM_MUX:LPM_MUX_component.DATA[1][26]
+data1x[27] => LPM_MUX:LPM_MUX_component.DATA[1][27]
+data1x[28] => LPM_MUX:LPM_MUX_component.DATA[1][28]
+data1x[29] => LPM_MUX:LPM_MUX_component.DATA[1][29]
+data2x[0] => LPM_MUX:LPM_MUX_component.DATA[2][0]
+data2x[1] => LPM_MUX:LPM_MUX_component.DATA[2][1]
+data2x[2] => LPM_MUX:LPM_MUX_component.DATA[2][2]
+data2x[3] => LPM_MUX:LPM_MUX_component.DATA[2][3]
+data2x[4] => LPM_MUX:LPM_MUX_component.DATA[2][4]
+data2x[5] => LPM_MUX:LPM_MUX_component.DATA[2][5]
+data2x[6] => LPM_MUX:LPM_MUX_component.DATA[2][6]
+data2x[7] => LPM_MUX:LPM_MUX_component.DATA[2][7]
+data2x[8] => LPM_MUX:LPM_MUX_component.DATA[2][8]
+data2x[9] => LPM_MUX:LPM_MUX_component.DATA[2][9]
+data2x[10] => LPM_MUX:LPM_MUX_component.DATA[2][10]
+data2x[11] => LPM_MUX:LPM_MUX_component.DATA[2][11]
+data2x[12] => LPM_MUX:LPM_MUX_component.DATA[2][12]
+data2x[13] => LPM_MUX:LPM_MUX_component.DATA[2][13]
+data2x[14] => LPM_MUX:LPM_MUX_component.DATA[2][14]
+data2x[15] => LPM_MUX:LPM_MUX_component.DATA[2][15]
+data2x[16] => LPM_MUX:LPM_MUX_component.DATA[2][16]
+data2x[17] => LPM_MUX:LPM_MUX_component.DATA[2][17]
+data2x[18] => LPM_MUX:LPM_MUX_component.DATA[2][18]
+data2x[19] => LPM_MUX:LPM_MUX_component.DATA[2][19]
+data2x[20] => LPM_MUX:LPM_MUX_component.DATA[2][20]
+data2x[21] => LPM_MUX:LPM_MUX_component.DATA[2][21]
+data2x[22] => LPM_MUX:LPM_MUX_component.DATA[2][22]
+data2x[23] => LPM_MUX:LPM_MUX_component.DATA[2][23]
+data2x[24] => LPM_MUX:LPM_MUX_component.DATA[2][24]
+data2x[25] => LPM_MUX:LPM_MUX_component.DATA[2][25]
+data2x[26] => LPM_MUX:LPM_MUX_component.DATA[2][26]
+data2x[27] => LPM_MUX:LPM_MUX_component.DATA[2][27]
+data2x[28] => LPM_MUX:LPM_MUX_component.DATA[2][28]
+data2x[29] => LPM_MUX:LPM_MUX_component.DATA[2][29]
+data3x[0] => LPM_MUX:LPM_MUX_component.DATA[3][0]
+data3x[1] => LPM_MUX:LPM_MUX_component.DATA[3][1]
+data3x[2] => LPM_MUX:LPM_MUX_component.DATA[3][2]
+data3x[3] => LPM_MUX:LPM_MUX_component.DATA[3][3]
+data3x[4] => LPM_MUX:LPM_MUX_component.DATA[3][4]
+data3x[5] => LPM_MUX:LPM_MUX_component.DATA[3][5]
+data3x[6] => LPM_MUX:LPM_MUX_component.DATA[3][6]
+data3x[7] => LPM_MUX:LPM_MUX_component.DATA[3][7]
+data3x[8] => LPM_MUX:LPM_MUX_component.DATA[3][8]
+data3x[9] => LPM_MUX:LPM_MUX_component.DATA[3][9]
+data3x[10] => LPM_MUX:LPM_MUX_component.DATA[3][10]
+data3x[11] => LPM_MUX:LPM_MUX_component.DATA[3][11]
+data3x[12] => LPM_MUX:LPM_MUX_component.DATA[3][12]
+data3x[13] => LPM_MUX:LPM_MUX_component.DATA[3][13]
+data3x[14] => LPM_MUX:LPM_MUX_component.DATA[3][14]
+data3x[15] => LPM_MUX:LPM_MUX_component.DATA[3][15]
+data3x[16] => LPM_MUX:LPM_MUX_component.DATA[3][16]
+data3x[17] => LPM_MUX:LPM_MUX_component.DATA[3][17]
+data3x[18] => LPM_MUX:LPM_MUX_component.DATA[3][18]
+data3x[19] => LPM_MUX:LPM_MUX_component.DATA[3][19]
+data3x[20] => LPM_MUX:LPM_MUX_component.DATA[3][20]
+data3x[21] => LPM_MUX:LPM_MUX_component.DATA[3][21]
+data3x[22] => LPM_MUX:LPM_MUX_component.DATA[3][22]
+data3x[23] => LPM_MUX:LPM_MUX_component.DATA[3][23]
+data3x[24] => LPM_MUX:LPM_MUX_component.DATA[3][24]
+data3x[25] => LPM_MUX:LPM_MUX_component.DATA[3][25]
+data3x[26] => LPM_MUX:LPM_MUX_component.DATA[3][26]
+data3x[27] => LPM_MUX:LPM_MUX_component.DATA[3][27]
+data3x[28] => LPM_MUX:LPM_MUX_component.DATA[3][28]
+data3x[29] => LPM_MUX:LPM_MUX_component.DATA[3][29]
+sel[0] => LPM_MUX:LPM_MUX_component.SEL[0]
+sel[1] => LPM_MUX:LPM_MUX_component.SEL[1]
+result[0] <= LPM_MUX:LPM_MUX_component.RESULT[0]
+result[1] <= LPM_MUX:LPM_MUX_component.RESULT[1]
+result[2] <= LPM_MUX:LPM_MUX_component.RESULT[2]
+result[3] <= LPM_MUX:LPM_MUX_component.RESULT[3]
+result[4] <= LPM_MUX:LPM_MUX_component.RESULT[4]
+result[5] <= LPM_MUX:LPM_MUX_component.RESULT[5]
+result[6] <= LPM_MUX:LPM_MUX_component.RESULT[6]
+result[7] <= LPM_MUX:LPM_MUX_component.RESULT[7]
+result[8] <= LPM_MUX:LPM_MUX_component.RESULT[8]
+result[9] <= LPM_MUX:LPM_MUX_component.RESULT[9]
+result[10] <= LPM_MUX:LPM_MUX_component.RESULT[10]
+result[11] <= LPM_MUX:LPM_MUX_component.RESULT[11]
+result[12] <= LPM_MUX:LPM_MUX_component.RESULT[12]
+result[13] <= LPM_MUX:LPM_MUX_component.RESULT[13]
+result[14] <= LPM_MUX:LPM_MUX_component.RESULT[14]
+result[15] <= LPM_MUX:LPM_MUX_component.RESULT[15]
+result[16] <= LPM_MUX:LPM_MUX_component.RESULT[16]
+result[17] <= LPM_MUX:LPM_MUX_component.RESULT[17]
+result[18] <= LPM_MUX:LPM_MUX_component.RESULT[18]
+result[19] <= LPM_MUX:LPM_MUX_component.RESULT[19]
+result[20] <= LPM_MUX:LPM_MUX_component.RESULT[20]
+result[21] <= LPM_MUX:LPM_MUX_component.RESULT[21]
+result[22] <= LPM_MUX:LPM_MUX_component.RESULT[22]
+result[23] <= LPM_MUX:LPM_MUX_component.RESULT[23]
+result[24] <= LPM_MUX:LPM_MUX_component.RESULT[24]
+result[25] <= LPM_MUX:LPM_MUX_component.RESULT[25]
+result[26] <= LPM_MUX:LPM_MUX_component.RESULT[26]
+result[27] <= LPM_MUX:LPM_MUX_component.RESULT[27]
+result[28] <= LPM_MUX:LPM_MUX_component.RESULT[28]
+result[29] <= LPM_MUX:LPM_MUX_component.RESULT[29]
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|LPM_MUX:LPM_MUX_component
+data[0][0] => mux_u7e:auto_generated.data[0]
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+data[1][6] => mux_u7e:auto_generated.data[36]
+data[1][7] => mux_u7e:auto_generated.data[37]
+data[1][8] => mux_u7e:auto_generated.data[38]
+data[1][9] => mux_u7e:auto_generated.data[39]
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+data[1][25] => mux_u7e:auto_generated.data[55]
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+data[2][4] => mux_u7e:auto_generated.data[64]
+data[2][5] => mux_u7e:auto_generated.data[65]
+data[2][6] => mux_u7e:auto_generated.data[66]
+data[2][7] => mux_u7e:auto_generated.data[67]
+data[2][8] => mux_u7e:auto_generated.data[68]
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+data[2][10] => mux_u7e:auto_generated.data[70]
+data[2][11] => mux_u7e:auto_generated.data[71]
+data[2][12] => mux_u7e:auto_generated.data[72]
+data[2][13] => mux_u7e:auto_generated.data[73]
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+data[2][20] => mux_u7e:auto_generated.data[80]
+data[2][21] => mux_u7e:auto_generated.data[81]
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+data[3][16] => mux_u7e:auto_generated.data[106]
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+data[3][18] => mux_u7e:auto_generated.data[108]
+data[3][19] => mux_u7e:auto_generated.data[109]
+data[3][20] => mux_u7e:auto_generated.data[110]
+data[3][21] => mux_u7e:auto_generated.data[111]
+data[3][22] => mux_u7e:auto_generated.data[112]
+data[3][23] => mux_u7e:auto_generated.data[113]
+data[3][24] => mux_u7e:auto_generated.data[114]
+data[3][25] => mux_u7e:auto_generated.data[115]
+data[3][26] => mux_u7e:auto_generated.data[116]
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+data[3][28] => mux_u7e:auto_generated.data[118]
+data[3][29] => mux_u7e:auto_generated.data[119]
+sel[0] => mux_u7e:auto_generated.sel[0]
+sel[1] => mux_u7e:auto_generated.sel[1]
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= mux_u7e:auto_generated.result[0]
+result[1] <= mux_u7e:auto_generated.result[1]
+result[2] <= mux_u7e:auto_generated.result[2]
+result[3] <= mux_u7e:auto_generated.result[3]
+result[4] <= mux_u7e:auto_generated.result[4]
+result[5] <= mux_u7e:auto_generated.result[5]
+result[6] <= mux_u7e:auto_generated.result[6]
+result[7] <= mux_u7e:auto_generated.result[7]
+result[8] <= mux_u7e:auto_generated.result[8]
+result[9] <= mux_u7e:auto_generated.result[9]
+result[10] <= mux_u7e:auto_generated.result[10]
+result[11] <= mux_u7e:auto_generated.result[11]
+result[12] <= mux_u7e:auto_generated.result[12]
+result[13] <= mux_u7e:auto_generated.result[13]
+result[14] <= mux_u7e:auto_generated.result[14]
+result[15] <= mux_u7e:auto_generated.result[15]
+result[16] <= mux_u7e:auto_generated.result[16]
+result[17] <= mux_u7e:auto_generated.result[17]
+result[18] <= mux_u7e:auto_generated.result[18]
+result[19] <= mux_u7e:auto_generated.result[19]
+result[20] <= mux_u7e:auto_generated.result[20]
+result[21] <= mux_u7e:auto_generated.result[21]
+result[22] <= mux_u7e:auto_generated.result[22]
+result[23] <= mux_u7e:auto_generated.result[23]
+result[24] <= mux_u7e:auto_generated.result[24]
+result[25] <= mux_u7e:auto_generated.result[25]
+result[26] <= mux_u7e:auto_generated.result[26]
+result[27] <= mux_u7e:auto_generated.result[27]
+result[28] <= mux_u7e:auto_generated.result[28]
+result[29] <= mux_u7e:auto_generated.result[29]
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|LPM_MUX:LPM_MUX_component|mux_u7e:auto_generated
+data[0] => _.IN0
+data[0] => _.IN0
+data[1] => _.IN0
+data[1] => _.IN0
+data[2] => _.IN0
+data[2] => _.IN0
+data[3] => _.IN0
+data[3] => _.IN0
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+data[4] => _.IN0
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+data[5] => _.IN0
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+data[7] => _.IN0
+data[7] => _.IN0
+data[8] => _.IN0
+data[8] => _.IN0
+data[9] => _.IN0
+data[9] => _.IN0
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+data[10] => _.IN0
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+data[11] => _.IN0
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+data[12] => _.IN0
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+data[13] => _.IN0
+data[14] => _.IN0
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+data[15] => _.IN0
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+data[16] => _.IN0
+data[17] => _.IN0
+data[17] => _.IN0
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+data[18] => _.IN0
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+data[19] => _.IN0
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+data[20] => _.IN0
+data[21] => _.IN0
+data[21] => _.IN0
+data[22] => _.IN0
+data[22] => _.IN0
+data[23] => _.IN0
+data[23] => _.IN0
+data[24] => _.IN0
+data[24] => _.IN0
+data[25] => _.IN0
+data[25] => _.IN0
+data[26] => _.IN0
+data[26] => _.IN0
+data[27] => _.IN0
+data[27] => _.IN0
+data[28] => _.IN0
+data[28] => _.IN0
+data[29] => _.IN0
+data[29] => _.IN0
+data[30] => _.IN0
+data[31] => _.IN0
+data[32] => _.IN0
+data[33] => _.IN0
+data[34] => _.IN0
+data[35] => _.IN0
+data[36] => _.IN0
+data[37] => _.IN0
+data[38] => _.IN0
+data[39] => _.IN0
+data[40] => _.IN0
+data[41] => _.IN0
+data[42] => _.IN0
+data[43] => _.IN0
+data[44] => _.IN0
+data[45] => _.IN0
+data[46] => _.IN0
+data[47] => _.IN0
+data[48] => _.IN0
+data[49] => _.IN0
+data[50] => _.IN0
+data[51] => _.IN0
+data[52] => _.IN0
+data[53] => _.IN0
+data[54] => _.IN0
+data[55] => _.IN0
+data[56] => _.IN0
+data[57] => _.IN0
+data[58] => _.IN0
+data[59] => _.IN0
+data[60] => _.IN1
+data[60] => _.IN1
+data[61] => _.IN1
+data[61] => _.IN1
+data[62] => _.IN1
+data[62] => _.IN1
+data[63] => _.IN1
+data[63] => _.IN1
+data[64] => _.IN1
+data[64] => _.IN1
+data[65] => _.IN1
+data[65] => _.IN1
+data[66] => _.IN1
+data[66] => _.IN1
+data[67] => _.IN1
+data[67] => _.IN1
+data[68] => _.IN1
+data[68] => _.IN1
+data[69] => _.IN1
+data[69] => _.IN1
+data[70] => _.IN1
+data[70] => _.IN1
+data[71] => _.IN1
+data[71] => _.IN1
+data[72] => _.IN1
+data[72] => _.IN1
+data[73] => _.IN1
+data[73] => _.IN1
+data[74] => _.IN1
+data[74] => _.IN1
+data[75] => _.IN1
+data[75] => _.IN1
+data[76] => _.IN1
+data[76] => _.IN1
+data[77] => _.IN1
+data[77] => _.IN1
+data[78] => _.IN1
+data[78] => _.IN1
+data[79] => _.IN1
+data[79] => _.IN1
+data[80] => _.IN1
+data[80] => _.IN1
+data[81] => _.IN1
+data[81] => _.IN1
+data[82] => _.IN1
+data[82] => _.IN1
+data[83] => _.IN1
+data[83] => _.IN1
+data[84] => _.IN1
+data[84] => _.IN1
+data[85] => _.IN1
+data[85] => _.IN1
+data[86] => _.IN1
+data[86] => _.IN1
+data[87] => _.IN1
+data[87] => _.IN1
+data[88] => _.IN1
+data[88] => _.IN1
+data[89] => _.IN1
+data[89] => _.IN1
+data[90] => _.IN0
+data[91] => _.IN0
+data[92] => _.IN0
+data[93] => _.IN0
+data[94] => _.IN0
+data[95] => _.IN0
+data[96] => _.IN0
+data[97] => _.IN0
+data[98] => _.IN0
+data[99] => _.IN0
+data[100] => _.IN0
+data[101] => _.IN0
+data[102] => _.IN0
+data[103] => _.IN0
+data[104] => _.IN0
+data[105] => _.IN0
+data[106] => _.IN0
+data[107] => _.IN0
+data[108] => _.IN0
+data[109] => _.IN0
+data[110] => _.IN0
+data[111] => _.IN0
+data[112] => _.IN0
+data[113] => _.IN0
+data[114] => _.IN0
+data[115] => _.IN0
+data[116] => _.IN0
+data[117] => _.IN0
+data[118] => _.IN0
+data[119] => _.IN0
+result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= result_node[8].DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= result_node[9].DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= result_node[10].DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= result_node[11].DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= result_node[12].DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= result_node[13].DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= result_node[14].DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= result_node[15].DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= result_node[16].DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= result_node[17].DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= result_node[18].DB_MAX_OUTPUT_PORT_TYPE
+result[19] <= result_node[19].DB_MAX_OUTPUT_PORT_TYPE
+result[20] <= result_node[20].DB_MAX_OUTPUT_PORT_TYPE
+result[21] <= result_node[21].DB_MAX_OUTPUT_PORT_TYPE
+result[22] <= result_node[22].DB_MAX_OUTPUT_PORT_TYPE
+result[23] <= result_node[23].DB_MAX_OUTPUT_PORT_TYPE
+result[24] <= result_node[24].DB_MAX_OUTPUT_PORT_TYPE
+result[25] <= result_node[25].DB_MAX_OUTPUT_PORT_TYPE
+result[26] <= result_node[26].DB_MAX_OUTPUT_PORT_TYPE
+result[27] <= result_node[27].DB_MAX_OUTPUT_PORT_TYPE
+result[28] <= result_node[28].DB_MAX_OUTPUT_PORT_TYPE
+result[29] <= result_node[29].DB_MAX_OUTPUT_PORT_TYPE
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
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+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
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+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
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+sel[0] => _.IN0
+sel[0] => _.IN1
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+sel[0] => _.IN1
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+sel[0] => _.IN1
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+sel[0] => _.IN1
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+sel[0] => _.IN1
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+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst
+vga_xy_rsc_z[0] => vga_xy_rsc_z[0].IN1
+vga_xy_rsc_z[1] => vga_xy_rsc_z[1].IN1
+vga_xy_rsc_z[2] => vga_xy_rsc_z[2].IN1
+vga_xy_rsc_z[3] => vga_xy_rsc_z[3].IN1
+vga_xy_rsc_z[4] => vga_xy_rsc_z[4].IN1
+vga_xy_rsc_z[5] => vga_xy_rsc_z[5].IN1
+vga_xy_rsc_z[6] => vga_xy_rsc_z[6].IN1
+vga_xy_rsc_z[7] => vga_xy_rsc_z[7].IN1
+vga_xy_rsc_z[8] => vga_xy_rsc_z[8].IN1
+vga_xy_rsc_z[9] => vga_xy_rsc_z[9].IN1
+vga_xy_rsc_z[10] => vga_xy_rsc_z[10].IN1
+vga_xy_rsc_z[11] => vga_xy_rsc_z[11].IN1
+vga_xy_rsc_z[12] => vga_xy_rsc_z[12].IN1
+vga_xy_rsc_z[13] => vga_xy_rsc_z[13].IN1
+vga_xy_rsc_z[14] => vga_xy_rsc_z[14].IN1
+vga_xy_rsc_z[15] => vga_xy_rsc_z[15].IN1
+vga_xy_rsc_z[16] => vga_xy_rsc_z[16].IN1
+vga_xy_rsc_z[17] => vga_xy_rsc_z[17].IN1
+vga_xy_rsc_z[18] => vga_xy_rsc_z[18].IN1
+vga_xy_rsc_z[19] => vga_xy_rsc_z[19].IN1
+mouse_xy_rsc_z[0] => mouse_xy_rsc_z[0].IN1
+mouse_xy_rsc_z[1] => mouse_xy_rsc_z[1].IN1
+mouse_xy_rsc_z[2] => mouse_xy_rsc_z[2].IN1
+mouse_xy_rsc_z[3] => mouse_xy_rsc_z[3].IN1
+mouse_xy_rsc_z[4] => mouse_xy_rsc_z[4].IN1
+mouse_xy_rsc_z[5] => mouse_xy_rsc_z[5].IN1
+mouse_xy_rsc_z[6] => mouse_xy_rsc_z[6].IN1
+mouse_xy_rsc_z[7] => mouse_xy_rsc_z[7].IN1
+mouse_xy_rsc_z[8] => mouse_xy_rsc_z[8].IN1
+mouse_xy_rsc_z[9] => mouse_xy_rsc_z[9].IN1
+mouse_xy_rsc_z[10] => mouse_xy_rsc_z[10].IN1
+mouse_xy_rsc_z[11] => mouse_xy_rsc_z[11].IN1
+mouse_xy_rsc_z[12] => mouse_xy_rsc_z[12].IN1
+mouse_xy_rsc_z[13] => mouse_xy_rsc_z[13].IN1
+mouse_xy_rsc_z[14] => mouse_xy_rsc_z[14].IN1
+mouse_xy_rsc_z[15] => mouse_xy_rsc_z[15].IN1
+mouse_xy_rsc_z[16] => mouse_xy_rsc_z[16].IN1
+mouse_xy_rsc_z[17] => mouse_xy_rsc_z[17].IN1
+mouse_xy_rsc_z[18] => mouse_xy_rsc_z[18].IN1
+mouse_xy_rsc_z[19] => mouse_xy_rsc_z[19].IN1
+cursor_size_rsc_z[0] => cursor_size_rsc_z[0].IN1
+cursor_size_rsc_z[1] => cursor_size_rsc_z[1].IN1
+cursor_size_rsc_z[2] => cursor_size_rsc_z[2].IN1
+cursor_size_rsc_z[3] => cursor_size_rsc_z[3].IN1
+cursor_size_rsc_z[4] => cursor_size_rsc_z[4].IN1
+cursor_size_rsc_z[5] => cursor_size_rsc_z[5].IN1
+cursor_size_rsc_z[6] => cursor_size_rsc_z[6].IN1
+cursor_size_rsc_z[7] => cursor_size_rsc_z[7].IN1
+video_in_rsc_z[0] => video_in_rsc_z[0].IN1
+video_in_rsc_z[1] => video_in_rsc_z[1].IN1
+video_in_rsc_z[2] => video_in_rsc_z[2].IN1
+video_in_rsc_z[3] => video_in_rsc_z[3].IN1
+video_in_rsc_z[4] => video_in_rsc_z[4].IN1
+video_in_rsc_z[5] => video_in_rsc_z[5].IN1
+video_in_rsc_z[6] => video_in_rsc_z[6].IN1
+video_in_rsc_z[7] => video_in_rsc_z[7].IN1
+video_in_rsc_z[8] => video_in_rsc_z[8].IN1
+video_in_rsc_z[9] => video_in_rsc_z[9].IN1
+video_in_rsc_z[10] => video_in_rsc_z[10].IN1
+video_in_rsc_z[11] => video_in_rsc_z[11].IN1
+video_in_rsc_z[12] => video_in_rsc_z[12].IN1
+video_in_rsc_z[13] => video_in_rsc_z[13].IN1
+video_in_rsc_z[14] => video_in_rsc_z[14].IN1
+video_in_rsc_z[15] => video_in_rsc_z[15].IN1
+video_in_rsc_z[16] => video_in_rsc_z[16].IN1
+video_in_rsc_z[17] => video_in_rsc_z[17].IN1
+video_in_rsc_z[18] => video_in_rsc_z[18].IN1
+video_in_rsc_z[19] => video_in_rsc_z[19].IN1
+video_in_rsc_z[20] => video_in_rsc_z[20].IN1
+video_in_rsc_z[21] => video_in_rsc_z[21].IN1
+video_in_rsc_z[22] => video_in_rsc_z[22].IN1
+video_in_rsc_z[23] => video_in_rsc_z[23].IN1
+video_in_rsc_z[24] => video_in_rsc_z[24].IN1
+video_in_rsc_z[25] => video_in_rsc_z[25].IN1
+video_in_rsc_z[26] => video_in_rsc_z[26].IN1
+video_in_rsc_z[27] => video_in_rsc_z[27].IN1
+video_in_rsc_z[28] => video_in_rsc_z[28].IN1
+video_in_rsc_z[29] => video_in_rsc_z[29].IN1
+video_out_rsc_z[0] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[1] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[2] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[3] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[4] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[5] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[6] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[7] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[8] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[9] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[10] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[11] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[12] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[13] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[14] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[15] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[16] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[17] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[18] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[19] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[20] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[21] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[22] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[23] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[24] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[25] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[26] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[27] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[28] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[29] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+clk => clk.IN1
+en => en.IN1
+arst_n => arst_n.IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:vga_xy_rsc_mgc_in_wire
+d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE
+d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE
+d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE
+d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE
+d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE
+d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE
+d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE
+d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE
+d[8] <= z[8].DB_MAX_OUTPUT_PORT_TYPE
+d[9] <= z[9].DB_MAX_OUTPUT_PORT_TYPE
+d[10] <= z[10].DB_MAX_OUTPUT_PORT_TYPE
+d[11] <= z[11].DB_MAX_OUTPUT_PORT_TYPE
+d[12] <= z[12].DB_MAX_OUTPUT_PORT_TYPE
+d[13] <= z[13].DB_MAX_OUTPUT_PORT_TYPE
+d[14] <= z[14].DB_MAX_OUTPUT_PORT_TYPE
+d[15] <= z[15].DB_MAX_OUTPUT_PORT_TYPE
+d[16] <= z[16].DB_MAX_OUTPUT_PORT_TYPE
+d[17] <= z[17].DB_MAX_OUTPUT_PORT_TYPE
+d[18] <= z[18].DB_MAX_OUTPUT_PORT_TYPE
+d[19] <= z[19].DB_MAX_OUTPUT_PORT_TYPE
+z[0] => d[0].DATAIN
+z[1] => d[1].DATAIN
+z[2] => d[2].DATAIN
+z[3] => d[3].DATAIN
+z[4] => d[4].DATAIN
+z[5] => d[5].DATAIN
+z[6] => d[6].DATAIN
+z[7] => d[7].DATAIN
+z[8] => d[8].DATAIN
+z[9] => d[9].DATAIN
+z[10] => d[10].DATAIN
+z[11] => d[11].DATAIN
+z[12] => d[12].DATAIN
+z[13] => d[13].DATAIN
+z[14] => d[14].DATAIN
+z[15] => d[15].DATAIN
+z[16] => d[16].DATAIN
+z[17] => d[17].DATAIN
+z[18] => d[18].DATAIN
+z[19] => d[19].DATAIN
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:mouse_xy_rsc_mgc_in_wire
+d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE
+d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE
+d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE
+d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE
+d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE
+d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE
+d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE
+d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE
+d[8] <= z[8].DB_MAX_OUTPUT_PORT_TYPE
+d[9] <= z[9].DB_MAX_OUTPUT_PORT_TYPE
+d[10] <= z[10].DB_MAX_OUTPUT_PORT_TYPE
+d[11] <= z[11].DB_MAX_OUTPUT_PORT_TYPE
+d[12] <= z[12].DB_MAX_OUTPUT_PORT_TYPE
+d[13] <= z[13].DB_MAX_OUTPUT_PORT_TYPE
+d[14] <= z[14].DB_MAX_OUTPUT_PORT_TYPE
+d[15] <= z[15].DB_MAX_OUTPUT_PORT_TYPE
+d[16] <= z[16].DB_MAX_OUTPUT_PORT_TYPE
+d[17] <= z[17].DB_MAX_OUTPUT_PORT_TYPE
+d[18] <= z[18].DB_MAX_OUTPUT_PORT_TYPE
+d[19] <= z[19].DB_MAX_OUTPUT_PORT_TYPE
+z[0] => d[0].DATAIN
+z[1] => d[1].DATAIN
+z[2] => d[2].DATAIN
+z[3] => d[3].DATAIN
+z[4] => d[4].DATAIN
+z[5] => d[5].DATAIN
+z[6] => d[6].DATAIN
+z[7] => d[7].DATAIN
+z[8] => d[8].DATAIN
+z[9] => d[9].DATAIN
+z[10] => d[10].DATAIN
+z[11] => d[11].DATAIN
+z[12] => d[12].DATAIN
+z[13] => d[13].DATAIN
+z[14] => d[14].DATAIN
+z[15] => d[15].DATAIN
+z[16] => d[16].DATAIN
+z[17] => d[17].DATAIN
+z[18] => d[18].DATAIN
+z[19] => d[19].DATAIN
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:cursor_size_rsc_mgc_in_wire
+d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE
+d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE
+d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE
+d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE
+d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE
+d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE
+d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE
+d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE
+z[0] => d[0].DATAIN
+z[1] => d[1].DATAIN
+z[2] => d[2].DATAIN
+z[3] => d[3].DATAIN
+z[4] => d[4].DATAIN
+z[5] => d[5].DATAIN
+z[6] => d[6].DATAIN
+z[7] => d[7].DATAIN
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:video_in_rsc_mgc_in_wire
+d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE
+d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE
+d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE
+d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE
+d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE
+d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE
+d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE
+d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE
+d[8] <= z[8].DB_MAX_OUTPUT_PORT_TYPE
+d[9] <= z[9].DB_MAX_OUTPUT_PORT_TYPE
+d[10] <= z[10].DB_MAX_OUTPUT_PORT_TYPE
+d[11] <= z[11].DB_MAX_OUTPUT_PORT_TYPE
+d[12] <= z[12].DB_MAX_OUTPUT_PORT_TYPE
+d[13] <= z[13].DB_MAX_OUTPUT_PORT_TYPE
+d[14] <= z[14].DB_MAX_OUTPUT_PORT_TYPE
+d[15] <= z[15].DB_MAX_OUTPUT_PORT_TYPE
+d[16] <= z[16].DB_MAX_OUTPUT_PORT_TYPE
+d[17] <= z[17].DB_MAX_OUTPUT_PORT_TYPE
+d[18] <= z[18].DB_MAX_OUTPUT_PORT_TYPE
+d[19] <= z[19].DB_MAX_OUTPUT_PORT_TYPE
+d[20] <= z[20].DB_MAX_OUTPUT_PORT_TYPE
+d[21] <= z[21].DB_MAX_OUTPUT_PORT_TYPE
+d[22] <= z[22].DB_MAX_OUTPUT_PORT_TYPE
+d[23] <= z[23].DB_MAX_OUTPUT_PORT_TYPE
+d[24] <= z[24].DB_MAX_OUTPUT_PORT_TYPE
+d[25] <= z[25].DB_MAX_OUTPUT_PORT_TYPE
+d[26] <= z[26].DB_MAX_OUTPUT_PORT_TYPE
+d[27] <= z[27].DB_MAX_OUTPUT_PORT_TYPE
+d[28] <= z[28].DB_MAX_OUTPUT_PORT_TYPE
+d[29] <= z[29].DB_MAX_OUTPUT_PORT_TYPE
+z[0] => d[0].DATAIN
+z[1] => d[1].DATAIN
+z[2] => d[2].DATAIN
+z[3] => d[3].DATAIN
+z[4] => d[4].DATAIN
+z[5] => d[5].DATAIN
+z[6] => d[6].DATAIN
+z[7] => d[7].DATAIN
+z[8] => d[8].DATAIN
+z[9] => d[9].DATAIN
+z[10] => d[10].DATAIN
+z[11] => d[11].DATAIN
+z[12] => d[12].DATAIN
+z[13] => d[13].DATAIN
+z[14] => d[14].DATAIN
+z[15] => d[15].DATAIN
+z[16] => d[16].DATAIN
+z[17] => d[17].DATAIN
+z[18] => d[18].DATAIN
+z[19] => d[19].DATAIN
+z[20] => d[20].DATAIN
+z[21] => d[21].DATAIN
+z[22] => d[22].DATAIN
+z[23] => d[23].DATAIN
+z[24] => d[24].DATAIN
+z[25] => d[25].DATAIN
+z[26] => d[26].DATAIN
+z[27] => d[27].DATAIN
+z[28] => d[28].DATAIN
+z[29] => d[29].DATAIN
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg
+d[0] => z[0].DATAIN
+d[1] => z[1].DATAIN
+d[2] => z[2].DATAIN
+d[3] => z[3].DATAIN
+d[4] => z[4].DATAIN
+d[5] => z[5].DATAIN
+d[6] => z[6].DATAIN
+d[7] => z[7].DATAIN
+d[8] => z[8].DATAIN
+d[9] => z[9].DATAIN
+d[10] => z[10].DATAIN
+d[11] => z[11].DATAIN
+d[12] => z[12].DATAIN
+d[13] => z[13].DATAIN
+d[14] => z[14].DATAIN
+d[15] => z[15].DATAIN
+d[16] => z[16].DATAIN
+d[17] => z[17].DATAIN
+d[18] => z[18].DATAIN
+d[19] => z[19].DATAIN
+d[20] => z[20].DATAIN
+d[21] => z[21].DATAIN
+d[22] => z[22].DATAIN
+d[23] => z[23].DATAIN
+d[24] => z[24].DATAIN
+d[25] => z[25].DATAIN
+d[26] => z[26].DATAIN
+d[27] => z[27].DATAIN
+d[28] => z[28].DATAIN
+d[29] => z[29].DATAIN
+z[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
+z[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
+z[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
+z[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
+z[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
+z[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
+z[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE
+z[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE
+z[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE
+z[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE
+z[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE
+z[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE
+z[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE
+z[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE
+z[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE
+z[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE
+z[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE
+z[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE
+z[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE
+z[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE
+z[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE
+z[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE
+z[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE
+z[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE
+z[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE
+z[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE
+z[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE
+z[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE
+z[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE
+z[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[0].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[1].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[2].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[3].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[4].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[5].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[0].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[1].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[2].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[3].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[4].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[5].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[6].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[7].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[8].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[9].CLK
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[0].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[9].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[8].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[7].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[6].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[5].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[4].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[3].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[2].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[1].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[0].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[5].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[4].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[3].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[2].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[1].ENA
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[0].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[1].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[2].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[3].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[4].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[5].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[0].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[1].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[2].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[3].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[4].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[5].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[6].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[7].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[8].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[9].ACLR
+vga_xy_rsc_mgc_in_wire_d[0] => Add6.IN20
+vga_xy_rsc_mgc_in_wire_d[0] => Add4.IN10
+vga_xy_rsc_mgc_in_wire_d[1] => Add6.IN19
+vga_xy_rsc_mgc_in_wire_d[1] => Add4.IN9
+vga_xy_rsc_mgc_in_wire_d[2] => Add6.IN18
+vga_xy_rsc_mgc_in_wire_d[2] => Add4.IN8
+vga_xy_rsc_mgc_in_wire_d[3] => Add6.IN17
+vga_xy_rsc_mgc_in_wire_d[3] => Add4.IN7
+vga_xy_rsc_mgc_in_wire_d[4] => Add6.IN16
+vga_xy_rsc_mgc_in_wire_d[4] => Add4.IN6
+vga_xy_rsc_mgc_in_wire_d[5] => Add6.IN15
+vga_xy_rsc_mgc_in_wire_d[5] => Add4.IN5
+vga_xy_rsc_mgc_in_wire_d[6] => Add6.IN14
+vga_xy_rsc_mgc_in_wire_d[6] => Add4.IN4
+vga_xy_rsc_mgc_in_wire_d[7] => Add6.IN13
+vga_xy_rsc_mgc_in_wire_d[7] => Add4.IN3
+vga_xy_rsc_mgc_in_wire_d[8] => Add6.IN12
+vga_xy_rsc_mgc_in_wire_d[8] => Add4.IN2
+vga_xy_rsc_mgc_in_wire_d[9] => Add6.IN11
+vga_xy_rsc_mgc_in_wire_d[9] => Add4.IN1
+vga_xy_rsc_mgc_in_wire_d[10] => Add2.IN20
+vga_xy_rsc_mgc_in_wire_d[10] => Add0.IN10
+vga_xy_rsc_mgc_in_wire_d[11] => Add2.IN19
+vga_xy_rsc_mgc_in_wire_d[11] => Add0.IN9
+vga_xy_rsc_mgc_in_wire_d[12] => Add2.IN18
+vga_xy_rsc_mgc_in_wire_d[12] => Add0.IN8
+vga_xy_rsc_mgc_in_wire_d[13] => Add2.IN17
+vga_xy_rsc_mgc_in_wire_d[13] => Add0.IN7
+vga_xy_rsc_mgc_in_wire_d[14] => Add2.IN16
+vga_xy_rsc_mgc_in_wire_d[14] => Add0.IN6
+vga_xy_rsc_mgc_in_wire_d[15] => Add2.IN15
+vga_xy_rsc_mgc_in_wire_d[15] => Add0.IN5
+vga_xy_rsc_mgc_in_wire_d[16] => Add2.IN14
+vga_xy_rsc_mgc_in_wire_d[16] => Add0.IN4
+vga_xy_rsc_mgc_in_wire_d[17] => Add2.IN13
+vga_xy_rsc_mgc_in_wire_d[17] => Add0.IN3
+vga_xy_rsc_mgc_in_wire_d[18] => Add2.IN12
+vga_xy_rsc_mgc_in_wire_d[18] => Add0.IN2
+vga_xy_rsc_mgc_in_wire_d[19] => Add2.IN11
+vga_xy_rsc_mgc_in_wire_d[19] => Add0.IN1
+mouse_xy_rsc_mgc_in_wire_d[0] => Add4.IN20
+mouse_xy_rsc_mgc_in_wire_d[0] => Add6.IN10
+mouse_xy_rsc_mgc_in_wire_d[1] => Add4.IN19
+mouse_xy_rsc_mgc_in_wire_d[1] => Add6.IN9
+mouse_xy_rsc_mgc_in_wire_d[2] => Add4.IN18
+mouse_xy_rsc_mgc_in_wire_d[2] => Add6.IN8
+mouse_xy_rsc_mgc_in_wire_d[3] => Add4.IN17
+mouse_xy_rsc_mgc_in_wire_d[3] => Add6.IN7
+mouse_xy_rsc_mgc_in_wire_d[4] => Add4.IN16
+mouse_xy_rsc_mgc_in_wire_d[4] => Add6.IN6
+mouse_xy_rsc_mgc_in_wire_d[5] => Add4.IN15
+mouse_xy_rsc_mgc_in_wire_d[5] => Add6.IN5
+mouse_xy_rsc_mgc_in_wire_d[6] => Add4.IN14
+mouse_xy_rsc_mgc_in_wire_d[6] => Add6.IN4
+mouse_xy_rsc_mgc_in_wire_d[7] => Add4.IN13
+mouse_xy_rsc_mgc_in_wire_d[7] => Add6.IN3
+mouse_xy_rsc_mgc_in_wire_d[8] => Add4.IN12
+mouse_xy_rsc_mgc_in_wire_d[8] => Add6.IN2
+mouse_xy_rsc_mgc_in_wire_d[9] => Add4.IN11
+mouse_xy_rsc_mgc_in_wire_d[9] => Add6.IN1
+mouse_xy_rsc_mgc_in_wire_d[10] => Add0.IN20
+mouse_xy_rsc_mgc_in_wire_d[10] => Add2.IN10
+mouse_xy_rsc_mgc_in_wire_d[11] => Add0.IN19
+mouse_xy_rsc_mgc_in_wire_d[11] => Add2.IN9
+mouse_xy_rsc_mgc_in_wire_d[12] => Add0.IN18
+mouse_xy_rsc_mgc_in_wire_d[12] => Add2.IN8
+mouse_xy_rsc_mgc_in_wire_d[13] => Add0.IN17
+mouse_xy_rsc_mgc_in_wire_d[13] => Add2.IN7
+mouse_xy_rsc_mgc_in_wire_d[14] => Add0.IN16
+mouse_xy_rsc_mgc_in_wire_d[14] => Add2.IN6
+mouse_xy_rsc_mgc_in_wire_d[15] => Add0.IN15
+mouse_xy_rsc_mgc_in_wire_d[15] => Add2.IN5
+mouse_xy_rsc_mgc_in_wire_d[16] => Add0.IN14
+mouse_xy_rsc_mgc_in_wire_d[16] => Add2.IN4
+mouse_xy_rsc_mgc_in_wire_d[17] => Add0.IN13
+mouse_xy_rsc_mgc_in_wire_d[17] => Add2.IN3
+mouse_xy_rsc_mgc_in_wire_d[18] => Add0.IN12
+mouse_xy_rsc_mgc_in_wire_d[18] => Add2.IN2
+mouse_xy_rsc_mgc_in_wire_d[19] => Add0.IN11
+mouse_xy_rsc_mgc_in_wire_d[19] => Add2.IN1
+cursor_size_rsc_mgc_in_wire_d[0] => Add1.IN22
+cursor_size_rsc_mgc_in_wire_d[0] => Add3.IN22
+cursor_size_rsc_mgc_in_wire_d[0] => Add5.IN22
+cursor_size_rsc_mgc_in_wire_d[0] => Add7.IN22
+cursor_size_rsc_mgc_in_wire_d[1] => Add1.IN21
+cursor_size_rsc_mgc_in_wire_d[1] => Add3.IN21
+cursor_size_rsc_mgc_in_wire_d[1] => Add5.IN21
+cursor_size_rsc_mgc_in_wire_d[1] => Add7.IN21
+cursor_size_rsc_mgc_in_wire_d[2] => Add1.IN20
+cursor_size_rsc_mgc_in_wire_d[2] => Add3.IN20
+cursor_size_rsc_mgc_in_wire_d[2] => Add5.IN20
+cursor_size_rsc_mgc_in_wire_d[2] => Add7.IN20
+cursor_size_rsc_mgc_in_wire_d[3] => Add1.IN19
+cursor_size_rsc_mgc_in_wire_d[3] => Add3.IN19
+cursor_size_rsc_mgc_in_wire_d[3] => Add5.IN19
+cursor_size_rsc_mgc_in_wire_d[3] => Add7.IN19
+cursor_size_rsc_mgc_in_wire_d[4] => Add1.IN18
+cursor_size_rsc_mgc_in_wire_d[4] => Add3.IN18
+cursor_size_rsc_mgc_in_wire_d[4] => Add5.IN18
+cursor_size_rsc_mgc_in_wire_d[4] => Add7.IN18
+cursor_size_rsc_mgc_in_wire_d[5] => Add1.IN17
+cursor_size_rsc_mgc_in_wire_d[5] => Add3.IN17
+cursor_size_rsc_mgc_in_wire_d[5] => Add5.IN17
+cursor_size_rsc_mgc_in_wire_d[5] => Add7.IN17
+cursor_size_rsc_mgc_in_wire_d[6] => Add1.IN16
+cursor_size_rsc_mgc_in_wire_d[6] => Add3.IN16
+cursor_size_rsc_mgc_in_wire_d[6] => Add5.IN16
+cursor_size_rsc_mgc_in_wire_d[6] => Add7.IN16
+cursor_size_rsc_mgc_in_wire_d[7] => Add1.IN15
+cursor_size_rsc_mgc_in_wire_d[7] => Add3.IN15
+cursor_size_rsc_mgc_in_wire_d[7] => Add5.IN15
+cursor_size_rsc_mgc_in_wire_d[7] => Add7.IN15
+video_in_rsc_mgc_in_wire_d[0] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[1] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[2] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[3] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[4] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[5] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[6] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[7] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[8] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[9] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[10] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].DATAIN
+video_in_rsc_mgc_in_wire_d[11] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].DATAIN
+video_in_rsc_mgc_in_wire_d[12] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].DATAIN
+video_in_rsc_mgc_in_wire_d[13] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].DATAIN
+video_in_rsc_mgc_in_wire_d[14] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].DATAIN
+video_in_rsc_mgc_in_wire_d[15] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].DATAIN
+video_in_rsc_mgc_in_wire_d[16] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].DATAIN
+video_in_rsc_mgc_in_wire_d[17] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].DATAIN
+video_in_rsc_mgc_in_wire_d[18] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].DATAIN
+video_in_rsc_mgc_in_wire_d[19] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].DATAIN
+video_in_rsc_mgc_in_wire_d[20] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[21] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[22] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[23] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[24] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[25] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[26] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[27] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[28] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[29] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_out_rsc_mgc_out_stdreg_d[0] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[0].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[1] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[1].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[2] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[2].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[3] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[3].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[4] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[4].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[5] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[5].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[6] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[7] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[8] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[9] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[10] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[11] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[12] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[13] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[14] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[15] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[16] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[17] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[18] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[19] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[20] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[0].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[21] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[1].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[22] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[2].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[23] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[3].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[24] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[4].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[25] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[5].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[26] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[6].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[27] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[7].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[28] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[8].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[29] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|sobel:inst1
+vin_rsc_z[0] => vin_rsc_z[0].IN1
+vin_rsc_z[1] => vin_rsc_z[1].IN1
+vin_rsc_z[2] => vin_rsc_z[2].IN1
+vin_rsc_z[3] => vin_rsc_z[3].IN1
+vin_rsc_z[4] => vin_rsc_z[4].IN1
+vin_rsc_z[5] => vin_rsc_z[5].IN1
+vin_rsc_z[6] => vin_rsc_z[6].IN1
+vin_rsc_z[7] => vin_rsc_z[7].IN1
+vin_rsc_z[8] => vin_rsc_z[8].IN1
+vin_rsc_z[9] => vin_rsc_z[9].IN1
+vin_rsc_z[10] => vin_rsc_z[10].IN1
+vin_rsc_z[11] => vin_rsc_z[11].IN1
+vin_rsc_z[12] => vin_rsc_z[12].IN1
+vin_rsc_z[13] => vin_rsc_z[13].IN1
+vin_rsc_z[14] => vin_rsc_z[14].IN1
+vin_rsc_z[15] => vin_rsc_z[15].IN1
+vin_rsc_z[16] => vin_rsc_z[16].IN1
+vin_rsc_z[17] => vin_rsc_z[17].IN1
+vin_rsc_z[18] => vin_rsc_z[18].IN1
+vin_rsc_z[19] => vin_rsc_z[19].IN1
+vin_rsc_z[20] => vin_rsc_z[20].IN1
+vin_rsc_z[21] => vin_rsc_z[21].IN1
+vin_rsc_z[22] => vin_rsc_z[22].IN1
+vin_rsc_z[23] => vin_rsc_z[23].IN1
+vin_rsc_z[24] => vin_rsc_z[24].IN1
+vin_rsc_z[25] => vin_rsc_z[25].IN1
+vin_rsc_z[26] => vin_rsc_z[26].IN1
+vin_rsc_z[27] => vin_rsc_z[27].IN1
+vin_rsc_z[28] => vin_rsc_z[28].IN1
+vin_rsc_z[29] => vin_rsc_z[29].IN1
+vin_rsc_z[30] => vin_rsc_z[30].IN1
+vin_rsc_z[31] => vin_rsc_z[31].IN1
+vin_rsc_z[32] => vin_rsc_z[32].IN1
+vin_rsc_z[33] => vin_rsc_z[33].IN1
+vin_rsc_z[34] => vin_rsc_z[34].IN1
+vin_rsc_z[35] => vin_rsc_z[35].IN1
+vin_rsc_z[36] => vin_rsc_z[36].IN1
+vin_rsc_z[37] => vin_rsc_z[37].IN1
+vin_rsc_z[38] => vin_rsc_z[38].IN1
+vin_rsc_z[39] => vin_rsc_z[39].IN1
+vin_rsc_z[40] => vin_rsc_z[40].IN1
+vin_rsc_z[41] => vin_rsc_z[41].IN1
+vin_rsc_z[42] => vin_rsc_z[42].IN1
+vin_rsc_z[43] => vin_rsc_z[43].IN1
+vin_rsc_z[44] => vin_rsc_z[44].IN1
+vin_rsc_z[45] => vin_rsc_z[45].IN1
+vin_rsc_z[46] => vin_rsc_z[46].IN1
+vin_rsc_z[47] => vin_rsc_z[47].IN1
+vin_rsc_z[48] => vin_rsc_z[48].IN1
+vin_rsc_z[49] => vin_rsc_z[49].IN1
+vin_rsc_z[50] => vin_rsc_z[50].IN1
+vin_rsc_z[51] => vin_rsc_z[51].IN1
+vin_rsc_z[52] => vin_rsc_z[52].IN1
+vin_rsc_z[53] => vin_rsc_z[53].IN1
+vin_rsc_z[54] => vin_rsc_z[54].IN1
+vin_rsc_z[55] => vin_rsc_z[55].IN1
+vin_rsc_z[56] => vin_rsc_z[56].IN1
+vin_rsc_z[57] => vin_rsc_z[57].IN1
+vin_rsc_z[58] => vin_rsc_z[58].IN1
+vin_rsc_z[59] => vin_rsc_z[59].IN1
+vin_rsc_z[60] => vin_rsc_z[60].IN1
+vin_rsc_z[61] => vin_rsc_z[61].IN1
+vin_rsc_z[62] => vin_rsc_z[62].IN1
+vin_rsc_z[63] => vin_rsc_z[63].IN1
+vin_rsc_z[64] => vin_rsc_z[64].IN1
+vin_rsc_z[65] => vin_rsc_z[65].IN1
+vin_rsc_z[66] => vin_rsc_z[66].IN1
+vin_rsc_z[67] => vin_rsc_z[67].IN1
+vin_rsc_z[68] => vin_rsc_z[68].IN1
+vin_rsc_z[69] => vin_rsc_z[69].IN1
+vin_rsc_z[70] => vin_rsc_z[70].IN1
+vin_rsc_z[71] => vin_rsc_z[71].IN1
+vin_rsc_z[72] => vin_rsc_z[72].IN1
+vin_rsc_z[73] => vin_rsc_z[73].IN1
+vin_rsc_z[74] => vin_rsc_z[74].IN1
+vin_rsc_z[75] => vin_rsc_z[75].IN1
+vin_rsc_z[76] => vin_rsc_z[76].IN1
+vin_rsc_z[77] => vin_rsc_z[77].IN1
+vin_rsc_z[78] => vin_rsc_z[78].IN1
+vin_rsc_z[79] => vin_rsc_z[79].IN1
+vin_rsc_z[80] => vin_rsc_z[80].IN1
+vin_rsc_z[81] => vin_rsc_z[81].IN1
+vin_rsc_z[82] => vin_rsc_z[82].IN1
+vin_rsc_z[83] => vin_rsc_z[83].IN1
+vin_rsc_z[84] => vin_rsc_z[84].IN1
+vin_rsc_z[85] => vin_rsc_z[85].IN1
+vin_rsc_z[86] => vin_rsc_z[86].IN1
+vin_rsc_z[87] => vin_rsc_z[87].IN1
+vin_rsc_z[88] => vin_rsc_z[88].IN1
+vin_rsc_z[89] => vin_rsc_z[89].IN1
+vout_rsc_z[0] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[1] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[2] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[3] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[4] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[5] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[6] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[7] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[8] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[9] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[10] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[11] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[12] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[13] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[14] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[15] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[16] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[17] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[18] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[19] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[20] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[21] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[22] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[23] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[24] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[25] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[26] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[27] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[28] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[29] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+clk => clk.IN1
+en => en.IN1
+arst_n => arst_n.IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|sobel:inst1|mgc_in_wire:vin_rsc_mgc_in_wire
+d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE
+d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE
+d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE
+d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE
+d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE
+d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE
+d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE
+d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE
+d[8] <= z[8].DB_MAX_OUTPUT_PORT_TYPE
+d[9] <= z[9].DB_MAX_OUTPUT_PORT_TYPE
+d[10] <= z[10].DB_MAX_OUTPUT_PORT_TYPE
+d[11] <= z[11].DB_MAX_OUTPUT_PORT_TYPE
+d[12] <= z[12].DB_MAX_OUTPUT_PORT_TYPE
+d[13] <= z[13].DB_MAX_OUTPUT_PORT_TYPE
+d[14] <= z[14].DB_MAX_OUTPUT_PORT_TYPE
+d[15] <= z[15].DB_MAX_OUTPUT_PORT_TYPE
+d[16] <= z[16].DB_MAX_OUTPUT_PORT_TYPE
+d[17] <= z[17].DB_MAX_OUTPUT_PORT_TYPE
+d[18] <= z[18].DB_MAX_OUTPUT_PORT_TYPE
+d[19] <= z[19].DB_MAX_OUTPUT_PORT_TYPE
+d[20] <= z[20].DB_MAX_OUTPUT_PORT_TYPE
+d[21] <= z[21].DB_MAX_OUTPUT_PORT_TYPE
+d[22] <= z[22].DB_MAX_OUTPUT_PORT_TYPE
+d[23] <= z[23].DB_MAX_OUTPUT_PORT_TYPE
+d[24] <= z[24].DB_MAX_OUTPUT_PORT_TYPE
+d[25] <= z[25].DB_MAX_OUTPUT_PORT_TYPE
+d[26] <= z[26].DB_MAX_OUTPUT_PORT_TYPE
+d[27] <= z[27].DB_MAX_OUTPUT_PORT_TYPE
+d[28] <= z[28].DB_MAX_OUTPUT_PORT_TYPE
+d[29] <= z[29].DB_MAX_OUTPUT_PORT_TYPE
+d[30] <= z[30].DB_MAX_OUTPUT_PORT_TYPE
+d[31] <= z[31].DB_MAX_OUTPUT_PORT_TYPE
+d[32] <= z[32].DB_MAX_OUTPUT_PORT_TYPE
+d[33] <= z[33].DB_MAX_OUTPUT_PORT_TYPE
+d[34] <= z[34].DB_MAX_OUTPUT_PORT_TYPE
+d[35] <= z[35].DB_MAX_OUTPUT_PORT_TYPE
+d[36] <= z[36].DB_MAX_OUTPUT_PORT_TYPE
+d[37] <= z[37].DB_MAX_OUTPUT_PORT_TYPE
+d[38] <= z[38].DB_MAX_OUTPUT_PORT_TYPE
+d[39] <= z[39].DB_MAX_OUTPUT_PORT_TYPE
+d[40] <= z[40].DB_MAX_OUTPUT_PORT_TYPE
+d[41] <= z[41].DB_MAX_OUTPUT_PORT_TYPE
+d[42] <= z[42].DB_MAX_OUTPUT_PORT_TYPE
+d[43] <= z[43].DB_MAX_OUTPUT_PORT_TYPE
+d[44] <= z[44].DB_MAX_OUTPUT_PORT_TYPE
+d[45] <= z[45].DB_MAX_OUTPUT_PORT_TYPE
+d[46] <= z[46].DB_MAX_OUTPUT_PORT_TYPE
+d[47] <= z[47].DB_MAX_OUTPUT_PORT_TYPE
+d[48] <= z[48].DB_MAX_OUTPUT_PORT_TYPE
+d[49] <= z[49].DB_MAX_OUTPUT_PORT_TYPE
+d[50] <= z[50].DB_MAX_OUTPUT_PORT_TYPE
+d[51] <= z[51].DB_MAX_OUTPUT_PORT_TYPE
+d[52] <= z[52].DB_MAX_OUTPUT_PORT_TYPE
+d[53] <= z[53].DB_MAX_OUTPUT_PORT_TYPE
+d[54] <= z[54].DB_MAX_OUTPUT_PORT_TYPE
+d[55] <= z[55].DB_MAX_OUTPUT_PORT_TYPE
+d[56] <= z[56].DB_MAX_OUTPUT_PORT_TYPE
+d[57] <= z[57].DB_MAX_OUTPUT_PORT_TYPE
+d[58] <= z[58].DB_MAX_OUTPUT_PORT_TYPE
+d[59] <= z[59].DB_MAX_OUTPUT_PORT_TYPE
+d[60] <= z[60].DB_MAX_OUTPUT_PORT_TYPE
+d[61] <= z[61].DB_MAX_OUTPUT_PORT_TYPE
+d[62] <= z[62].DB_MAX_OUTPUT_PORT_TYPE
+d[63] <= z[63].DB_MAX_OUTPUT_PORT_TYPE
+d[64] <= z[64].DB_MAX_OUTPUT_PORT_TYPE
+d[65] <= z[65].DB_MAX_OUTPUT_PORT_TYPE
+d[66] <= z[66].DB_MAX_OUTPUT_PORT_TYPE
+d[67] <= z[67].DB_MAX_OUTPUT_PORT_TYPE
+d[68] <= z[68].DB_MAX_OUTPUT_PORT_TYPE
+d[69] <= z[69].DB_MAX_OUTPUT_PORT_TYPE
+d[70] <= z[70].DB_MAX_OUTPUT_PORT_TYPE
+d[71] <= z[71].DB_MAX_OUTPUT_PORT_TYPE
+d[72] <= z[72].DB_MAX_OUTPUT_PORT_TYPE
+d[73] <= z[73].DB_MAX_OUTPUT_PORT_TYPE
+d[74] <= z[74].DB_MAX_OUTPUT_PORT_TYPE
+d[75] <= z[75].DB_MAX_OUTPUT_PORT_TYPE
+d[76] <= z[76].DB_MAX_OUTPUT_PORT_TYPE
+d[77] <= z[77].DB_MAX_OUTPUT_PORT_TYPE
+d[78] <= z[78].DB_MAX_OUTPUT_PORT_TYPE
+d[79] <= z[79].DB_MAX_OUTPUT_PORT_TYPE
+d[80] <= z[80].DB_MAX_OUTPUT_PORT_TYPE
+d[81] <= z[81].DB_MAX_OUTPUT_PORT_TYPE
+d[82] <= z[82].DB_MAX_OUTPUT_PORT_TYPE
+d[83] <= z[83].DB_MAX_OUTPUT_PORT_TYPE
+d[84] <= z[84].DB_MAX_OUTPUT_PORT_TYPE
+d[85] <= z[85].DB_MAX_OUTPUT_PORT_TYPE
+d[86] <= z[86].DB_MAX_OUTPUT_PORT_TYPE
+d[87] <= z[87].DB_MAX_OUTPUT_PORT_TYPE
+d[88] <= z[88].DB_MAX_OUTPUT_PORT_TYPE
+d[89] <= z[89].DB_MAX_OUTPUT_PORT_TYPE
+z[0] => d[0].DATAIN
+z[1] => d[1].DATAIN
+z[2] => d[2].DATAIN
+z[3] => d[3].DATAIN
+z[4] => d[4].DATAIN
+z[5] => d[5].DATAIN
+z[6] => d[6].DATAIN
+z[7] => d[7].DATAIN
+z[8] => d[8].DATAIN
+z[9] => d[9].DATAIN
+z[10] => d[10].DATAIN
+z[11] => d[11].DATAIN
+z[12] => d[12].DATAIN
+z[13] => d[13].DATAIN
+z[14] => d[14].DATAIN
+z[15] => d[15].DATAIN
+z[16] => d[16].DATAIN
+z[17] => d[17].DATAIN
+z[18] => d[18].DATAIN
+z[19] => d[19].DATAIN
+z[20] => d[20].DATAIN
+z[21] => d[21].DATAIN
+z[22] => d[22].DATAIN
+z[23] => d[23].DATAIN
+z[24] => d[24].DATAIN
+z[25] => d[25].DATAIN
+z[26] => d[26].DATAIN
+z[27] => d[27].DATAIN
+z[28] => d[28].DATAIN
+z[29] => d[29].DATAIN
+z[30] => d[30].DATAIN
+z[31] => d[31].DATAIN
+z[32] => d[32].DATAIN
+z[33] => d[33].DATAIN
+z[34] => d[34].DATAIN
+z[35] => d[35].DATAIN
+z[36] => d[36].DATAIN
+z[37] => d[37].DATAIN
+z[38] => d[38].DATAIN
+z[39] => d[39].DATAIN
+z[40] => d[40].DATAIN
+z[41] => d[41].DATAIN
+z[42] => d[42].DATAIN
+z[43] => d[43].DATAIN
+z[44] => d[44].DATAIN
+z[45] => d[45].DATAIN
+z[46] => d[46].DATAIN
+z[47] => d[47].DATAIN
+z[48] => d[48].DATAIN
+z[49] => d[49].DATAIN
+z[50] => d[50].DATAIN
+z[51] => d[51].DATAIN
+z[52] => d[52].DATAIN
+z[53] => d[53].DATAIN
+z[54] => d[54].DATAIN
+z[55] => d[55].DATAIN
+z[56] => d[56].DATAIN
+z[57] => d[57].DATAIN
+z[58] => d[58].DATAIN
+z[59] => d[59].DATAIN
+z[60] => d[60].DATAIN
+z[61] => d[61].DATAIN
+z[62] => d[62].DATAIN
+z[63] => d[63].DATAIN
+z[64] => d[64].DATAIN
+z[65] => d[65].DATAIN
+z[66] => d[66].DATAIN
+z[67] => d[67].DATAIN
+z[68] => d[68].DATAIN
+z[69] => d[69].DATAIN
+z[70] => d[70].DATAIN
+z[71] => d[71].DATAIN
+z[72] => d[72].DATAIN
+z[73] => d[73].DATAIN
+z[74] => d[74].DATAIN
+z[75] => d[75].DATAIN
+z[76] => d[76].DATAIN
+z[77] => d[77].DATAIN
+z[78] => d[78].DATAIN
+z[79] => d[79].DATAIN
+z[80] => d[80].DATAIN
+z[81] => d[81].DATAIN
+z[82] => d[82].DATAIN
+z[83] => d[83].DATAIN
+z[84] => d[84].DATAIN
+z[85] => d[85].DATAIN
+z[86] => d[86].DATAIN
+z[87] => d[87].DATAIN
+z[88] => d[88].DATAIN
+z[89] => d[89].DATAIN
+
+
+|TOP_DE0_CAMERA_MOUSE|sobel:inst1|mgc_out_stdreg:vout_rsc_mgc_out_stdreg
+d[0] => z[0].DATAIN
+d[1] => z[1].DATAIN
+d[2] => z[2].DATAIN
+d[3] => z[3].DATAIN
+d[4] => z[4].DATAIN
+d[5] => z[5].DATAIN
+d[6] => z[6].DATAIN
+d[7] => z[7].DATAIN
+d[8] => z[8].DATAIN
+d[9] => z[9].DATAIN
+d[10] => z[10].DATAIN
+d[11] => z[11].DATAIN
+d[12] => z[12].DATAIN
+d[13] => z[13].DATAIN
+d[14] => z[14].DATAIN
+d[15] => z[15].DATAIN
+d[16] => z[16].DATAIN
+d[17] => z[17].DATAIN
+d[18] => z[18].DATAIN
+d[19] => z[19].DATAIN
+d[20] => z[20].DATAIN
+d[21] => z[21].DATAIN
+d[22] => z[22].DATAIN
+d[23] => z[23].DATAIN
+d[24] => z[24].DATAIN
+d[25] => z[25].DATAIN
+d[26] => z[26].DATAIN
+d[27] => z[27].DATAIN
+d[28] => z[28].DATAIN
+d[29] => z[29].DATAIN
+z[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
+z[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
+z[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
+z[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
+z[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
+z[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
+z[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE
+z[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE
+z[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE
+z[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE
+z[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE
+z[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE
+z[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE
+z[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE
+z[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE
+z[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE
+z[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE
+z[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE
+z[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE
+z[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE
+z[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE
+z[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE
+z[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE
+z[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE
+z[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE
+z[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE
+z[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE
+z[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE
+z[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE
+z[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|sobel:inst1|sobel_core:sobel_core_inst
+clk => reg_regs_regs_0_sva_cse[0].CLK
+clk => reg_regs_regs_0_sva_cse[1].CLK
+clk => reg_regs_regs_0_sva_cse[2].CLK
+clk => reg_regs_regs_0_sva_cse[3].CLK
+clk => reg_regs_regs_0_sva_cse[4].CLK
+clk => reg_regs_regs_0_sva_cse[5].CLK
+clk => reg_regs_regs_0_sva_cse[6].CLK
+clk => reg_regs_regs_0_sva_cse[7].CLK
+clk => reg_regs_regs_0_sva_cse[8].CLK
+clk => reg_regs_regs_0_sva_cse[9].CLK
+clk => reg_regs_regs_0_sva_cse[10].CLK
+clk => reg_regs_regs_0_sva_cse[11].CLK
+clk => reg_regs_regs_0_sva_cse[12].CLK
+clk => reg_regs_regs_0_sva_cse[13].CLK
+clk => reg_regs_regs_0_sva_cse[14].CLK
+clk => reg_regs_regs_0_sva_cse[15].CLK
+clk => reg_regs_regs_0_sva_cse[16].CLK
+clk => reg_regs_regs_0_sva_cse[17].CLK
+clk => reg_regs_regs_0_sva_cse[18].CLK
+clk => reg_regs_regs_0_sva_cse[19].CLK
+clk => reg_regs_regs_0_sva_cse[20].CLK
+clk => reg_regs_regs_0_sva_cse[21].CLK
+clk => reg_regs_regs_0_sva_cse[22].CLK
+clk => reg_regs_regs_0_sva_cse[23].CLK
+clk => reg_regs_regs_0_sva_cse[24].CLK
+clk => reg_regs_regs_0_sva_cse[25].CLK
+clk => reg_regs_regs_0_sva_cse[26].CLK
+clk => reg_regs_regs_0_sva_cse[27].CLK
+clk => reg_regs_regs_0_sva_cse[28].CLK
+clk => reg_regs_regs_0_sva_cse[29].CLK
+clk => reg_regs_regs_0_sva_cse[30].CLK
+clk => reg_regs_regs_0_sva_cse[31].CLK
+clk => reg_regs_regs_0_sva_cse[32].CLK
+clk => reg_regs_regs_0_sva_cse[33].CLK
+clk => reg_regs_regs_0_sva_cse[34].CLK
+clk => reg_regs_regs_0_sva_cse[35].CLK
+clk => reg_regs_regs_0_sva_cse[36].CLK
+clk => reg_regs_regs_0_sva_cse[37].CLK
+clk => reg_regs_regs_0_sva_cse[38].CLK
+clk => reg_regs_regs_0_sva_cse[39].CLK
+clk => reg_regs_regs_0_sva_cse[40].CLK
+clk => reg_regs_regs_0_sva_cse[41].CLK
+clk => reg_regs_regs_0_sva_cse[42].CLK
+clk => reg_regs_regs_0_sva_cse[43].CLK
+clk => reg_regs_regs_0_sva_cse[44].CLK
+clk => reg_regs_regs_0_sva_cse[45].CLK
+clk => reg_regs_regs_0_sva_cse[46].CLK
+clk => reg_regs_regs_0_sva_cse[47].CLK
+clk => reg_regs_regs_0_sva_cse[48].CLK
+clk => reg_regs_regs_0_sva_cse[49].CLK
+clk => reg_regs_regs_0_sva_cse[50].CLK
+clk => reg_regs_regs_0_sva_cse[51].CLK
+clk => reg_regs_regs_0_sva_cse[52].CLK
+clk => reg_regs_regs_0_sva_cse[53].CLK
+clk => reg_regs_regs_0_sva_cse[54].CLK
+clk => reg_regs_regs_0_sva_cse[55].CLK
+clk => reg_regs_regs_0_sva_cse[56].CLK
+clk => reg_regs_regs_0_sva_cse[57].CLK
+clk => reg_regs_regs_0_sva_cse[58].CLK
+clk => reg_regs_regs_0_sva_cse[59].CLK
+clk => reg_regs_regs_0_sva_cse[60].CLK
+clk => reg_regs_regs_0_sva_cse[61].CLK
+clk => reg_regs_regs_0_sva_cse[62].CLK
+clk => reg_regs_regs_0_sva_cse[63].CLK
+clk => reg_regs_regs_0_sva_cse[64].CLK
+clk => reg_regs_regs_0_sva_cse[65].CLK
+clk => reg_regs_regs_0_sva_cse[66].CLK
+clk => reg_regs_regs_0_sva_cse[67].CLK
+clk => reg_regs_regs_0_sva_cse[68].CLK
+clk => reg_regs_regs_0_sva_cse[69].CLK
+clk => reg_regs_regs_0_sva_cse[70].CLK
+clk => reg_regs_regs_0_sva_cse[71].CLK
+clk => reg_regs_regs_0_sva_cse[72].CLK
+clk => reg_regs_regs_0_sva_cse[73].CLK
+clk => reg_regs_regs_0_sva_cse[74].CLK
+clk => reg_regs_regs_0_sva_cse[75].CLK
+clk => reg_regs_regs_0_sva_cse[76].CLK
+clk => reg_regs_regs_0_sva_cse[77].CLK
+clk => reg_regs_regs_0_sva_cse[78].CLK
+clk => reg_regs_regs_0_sva_cse[79].CLK
+clk => reg_regs_regs_0_sva_cse[80].CLK
+clk => reg_regs_regs_0_sva_cse[81].CLK
+clk => reg_regs_regs_0_sva_cse[82].CLK
+clk => reg_regs_regs_0_sva_cse[83].CLK
+clk => reg_regs_regs_0_sva_cse[84].CLK
+clk => reg_regs_regs_0_sva_cse[85].CLK
+clk => reg_regs_regs_0_sva_cse[86].CLK
+clk => reg_regs_regs_0_sva_cse[87].CLK
+clk => reg_regs_regs_0_sva_cse[88].CLK
+clk => reg_regs_regs_0_sva_cse[89].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_2_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_1_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_3_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_5_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_4_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_9_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_11_itm[9].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[0].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[1].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[2].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[3].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[4].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[5].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[6].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[7].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[8].CLK
+clk => regs_regs_slc_regs_regs_2_10_itm[9].CLK
+clk => main_stage_0_2.CLK
+clk => ACC1_acc_655_itm_1[0].CLK
+clk => ACC1_acc_655_itm_1[1].CLK
+clk => ACC1_acc_655_itm_1[2].CLK
+clk => ACC1_acc_655_itm_1[3].CLK
+clk => ACC1_acc_655_itm_1[4].CLK
+clk => ACC1_acc_655_itm_1[5].CLK
+clk => ACC1_acc_655_itm_1[6].CLK
+clk => ACC1_acc_655_itm_1[7].CLK
+clk => ACC1_acc_655_itm_1[8].CLK
+clk => ACC1_acc_655_itm_1[9].CLK
+clk => ACC1_acc_655_itm_1[10].CLK
+clk => ACC1_acc_655_itm_1[11].CLK
+clk => ACC1_acc_652_itm_1[0].CLK
+clk => ACC1_acc_652_itm_1[1].CLK
+clk => ACC1_acc_652_itm_1[2].CLK
+clk => ACC1_acc_652_itm_1[3].CLK
+clk => ACC1_acc_652_itm_1[4].CLK
+clk => ACC1_acc_652_itm_1[5].CLK
+clk => ACC1_acc_652_itm_1[6].CLK
+clk => ACC1_acc_652_itm_1[7].CLK
+clk => ACC1_acc_652_itm_1[8].CLK
+clk => ACC1_acc_652_itm_1[9].CLK
+clk => ACC1_acc_652_itm_1[10].CLK
+clk => ACC1_3_slc_acc_10_psp_62_itm_1.CLK
+clk => ACC1_slc_ACC1_acc_228_psp_55_itm_1.CLK
+clk => slc_acc_20_psp_1_93_itm_1.CLK
+clk => ACC1_mul_57_itm_2[0].CLK
+clk => ACC1_mul_57_itm_2[1].CLK
+clk => ACC1_mul_57_itm_1_sg2[0].CLK
+clk => ACC1_mul_57_itm_1_sg2[1].CLK
+clk => ACC1_mul_57_itm_1_sg2[2].CLK
+clk => ACC1_mul_57_itm_1_sg2[3].CLK
+clk => ACC1_mul_57_itm_1_sg2[4].CLK
+clk => ACC1_acc_661_itm_1[0].CLK
+clk => ACC1_acc_661_itm_1[1].CLK
+clk => ACC1_acc_661_itm_1[2].CLK
+clk => ACC1_acc_661_itm_1[3].CLK
+clk => ACC1_acc_661_itm_1[4].CLK
+clk => ACC1_acc_661_itm_1[5].CLK
+clk => ACC1_acc_661_itm_1[6].CLK
+clk => ACC1_acc_661_itm_1[7].CLK
+clk => ACC1_acc_661_itm_1[8].CLK
+clk => ACC1_acc_661_itm_1[9].CLK
+clk => ACC1_acc_661_itm_1[10].CLK
+clk => ACC1_acc_661_itm_1[11].CLK
+clk => ACC1_acc_661_itm_1[12].CLK
+clk => ACC1_acc_661_itm_1[13].CLK
+clk => ACC1_acc_658_itm_1[0].CLK
+clk => ACC1_acc_658_itm_1[1].CLK
+clk => ACC1_acc_658_itm_1[2].CLK
+clk => ACC1_acc_658_itm_1[3].CLK
+clk => ACC1_acc_658_itm_1[4].CLK
+clk => ACC1_acc_658_itm_1[5].CLK
+clk => ACC1_acc_658_itm_1[6].CLK
+clk => ACC1_acc_658_itm_1[7].CLK
+clk => ACC1_acc_658_itm_1[8].CLK
+clk => ACC1_acc_658_itm_1[9].CLK
+clk => ACC1_acc_658_itm_1[10].CLK
+clk => ACC1_acc_658_itm_1[11].CLK
+clk => ACC1_acc_658_itm_1[12].CLK
+clk => ACC1_acc_659_itm_1[0].CLK
+clk => ACC1_acc_659_itm_1[1].CLK
+clk => ACC1_acc_659_itm_1[2].CLK
+clk => ACC1_acc_659_itm_1[3].CLK
+clk => ACC1_acc_659_itm_1[4].CLK
+clk => ACC1_acc_659_itm_1[5].CLK
+clk => ACC1_acc_659_itm_1[6].CLK
+clk => ACC1_acc_659_itm_1[7].CLK
+clk => ACC1_acc_659_itm_1[8].CLK
+clk => ACC1_acc_659_itm_1[9].CLK
+clk => ACC1_acc_659_itm_1[10].CLK
+clk => ACC1_acc_659_itm_1[11].CLK
+clk => ACC1_acc_659_itm_1[12].CLK
+clk => vout_rsc_mgc_out_stdreg_d[0]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[1]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[2]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[3]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[4]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[5]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[6]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[7]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[8]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[9]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[10]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[11]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[12]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[13]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[14]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[15]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[16]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[17]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[18]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[19]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[20]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[21]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[22]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[23]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[24]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[25]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[26]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[27]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[28]~reg0.CLK
+clk => vout_rsc_mgc_out_stdreg_d[29]~reg0.CLK
+en => reg_regs_regs_0_sva_cse[0].ENA
+en => vout_rsc_mgc_out_stdreg_d[29]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[28]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[27]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[26]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[25]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[24]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[23]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[22]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[21]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[20]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[19]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[18]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[17]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[16]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[15]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[14]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[13]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[12]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[11]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[10]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[9]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[8]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[7]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[6]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[5]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[4]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[3]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[2]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[1]~reg0.ENA
+en => vout_rsc_mgc_out_stdreg_d[0]~reg0.ENA
+en => ACC1_acc_659_itm_1[12].ENA
+en => ACC1_acc_659_itm_1[11].ENA
+en => ACC1_acc_659_itm_1[10].ENA
+en => ACC1_acc_659_itm_1[9].ENA
+en => ACC1_acc_659_itm_1[8].ENA
+en => ACC1_acc_659_itm_1[7].ENA
+en => ACC1_acc_659_itm_1[6].ENA
+en => ACC1_acc_659_itm_1[5].ENA
+en => ACC1_acc_659_itm_1[4].ENA
+en => ACC1_acc_659_itm_1[3].ENA
+en => ACC1_acc_659_itm_1[2].ENA
+en => ACC1_acc_659_itm_1[1].ENA
+en => ACC1_acc_659_itm_1[0].ENA
+en => ACC1_acc_658_itm_1[12].ENA
+en => ACC1_acc_658_itm_1[11].ENA
+en => ACC1_acc_658_itm_1[10].ENA
+en => ACC1_acc_658_itm_1[9].ENA
+en => ACC1_acc_658_itm_1[8].ENA
+en => ACC1_acc_658_itm_1[7].ENA
+en => ACC1_acc_658_itm_1[6].ENA
+en => ACC1_acc_658_itm_1[5].ENA
+en => ACC1_acc_658_itm_1[4].ENA
+en => ACC1_acc_658_itm_1[3].ENA
+en => ACC1_acc_658_itm_1[2].ENA
+en => ACC1_acc_658_itm_1[1].ENA
+en => ACC1_acc_658_itm_1[0].ENA
+en => ACC1_acc_661_itm_1[13].ENA
+en => ACC1_acc_661_itm_1[12].ENA
+en => ACC1_acc_661_itm_1[11].ENA
+en => ACC1_acc_661_itm_1[10].ENA
+en => ACC1_acc_661_itm_1[9].ENA
+en => ACC1_acc_661_itm_1[8].ENA
+en => ACC1_acc_661_itm_1[7].ENA
+en => ACC1_acc_661_itm_1[6].ENA
+en => ACC1_acc_661_itm_1[5].ENA
+en => ACC1_acc_661_itm_1[4].ENA
+en => ACC1_acc_661_itm_1[3].ENA
+en => ACC1_acc_661_itm_1[2].ENA
+en => ACC1_acc_661_itm_1[1].ENA
+en => ACC1_acc_661_itm_1[0].ENA
+en => ACC1_mul_57_itm_1_sg2[4].ENA
+en => ACC1_mul_57_itm_1_sg2[3].ENA
+en => ACC1_mul_57_itm_1_sg2[2].ENA
+en => ACC1_mul_57_itm_1_sg2[1].ENA
+en => ACC1_mul_57_itm_1_sg2[0].ENA
+en => ACC1_mul_57_itm_2[1].ENA
+en => ACC1_mul_57_itm_2[0].ENA
+en => slc_acc_20_psp_1_93_itm_1.ENA
+en => ACC1_slc_ACC1_acc_228_psp_55_itm_1.ENA
+en => ACC1_3_slc_acc_10_psp_62_itm_1.ENA
+en => ACC1_acc_652_itm_1[10].ENA
+en => ACC1_acc_652_itm_1[9].ENA
+en => ACC1_acc_652_itm_1[8].ENA
+en => ACC1_acc_652_itm_1[7].ENA
+en => ACC1_acc_652_itm_1[6].ENA
+en => ACC1_acc_652_itm_1[5].ENA
+en => ACC1_acc_652_itm_1[4].ENA
+en => ACC1_acc_652_itm_1[3].ENA
+en => ACC1_acc_652_itm_1[2].ENA
+en => ACC1_acc_652_itm_1[1].ENA
+en => ACC1_acc_652_itm_1[0].ENA
+en => ACC1_acc_655_itm_1[11].ENA
+en => ACC1_acc_655_itm_1[10].ENA
+en => ACC1_acc_655_itm_1[9].ENA
+en => ACC1_acc_655_itm_1[8].ENA
+en => ACC1_acc_655_itm_1[7].ENA
+en => ACC1_acc_655_itm_1[6].ENA
+en => ACC1_acc_655_itm_1[5].ENA
+en => ACC1_acc_655_itm_1[4].ENA
+en => ACC1_acc_655_itm_1[3].ENA
+en => ACC1_acc_655_itm_1[2].ENA
+en => ACC1_acc_655_itm_1[1].ENA
+en => ACC1_acc_655_itm_1[0].ENA
+en => main_stage_0_2.ENA
+en => regs_regs_slc_regs_regs_2_10_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_10_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_11_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_9_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_4_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_5_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_3_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_1_itm[0].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[9].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[8].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[7].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[6].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[5].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[4].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[3].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[2].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[1].ENA
+en => regs_regs_slc_regs_regs_2_2_itm[0].ENA
+en => reg_regs_regs_0_sva_cse[89].ENA
+en => reg_regs_regs_0_sva_cse[88].ENA
+en => reg_regs_regs_0_sva_cse[87].ENA
+en => reg_regs_regs_0_sva_cse[86].ENA
+en => reg_regs_regs_0_sva_cse[85].ENA
+en => reg_regs_regs_0_sva_cse[84].ENA
+en => reg_regs_regs_0_sva_cse[83].ENA
+en => reg_regs_regs_0_sva_cse[82].ENA
+en => reg_regs_regs_0_sva_cse[81].ENA
+en => reg_regs_regs_0_sva_cse[80].ENA
+en => reg_regs_regs_0_sva_cse[79].ENA
+en => reg_regs_regs_0_sva_cse[78].ENA
+en => reg_regs_regs_0_sva_cse[77].ENA
+en => reg_regs_regs_0_sva_cse[76].ENA
+en => reg_regs_regs_0_sva_cse[75].ENA
+en => reg_regs_regs_0_sva_cse[74].ENA
+en => reg_regs_regs_0_sva_cse[73].ENA
+en => reg_regs_regs_0_sva_cse[72].ENA
+en => reg_regs_regs_0_sva_cse[71].ENA
+en => reg_regs_regs_0_sva_cse[70].ENA
+en => reg_regs_regs_0_sva_cse[69].ENA
+en => reg_regs_regs_0_sva_cse[68].ENA
+en => reg_regs_regs_0_sva_cse[67].ENA
+en => reg_regs_regs_0_sva_cse[66].ENA
+en => reg_regs_regs_0_sva_cse[65].ENA
+en => reg_regs_regs_0_sva_cse[64].ENA
+en => reg_regs_regs_0_sva_cse[63].ENA
+en => reg_regs_regs_0_sva_cse[62].ENA
+en => reg_regs_regs_0_sva_cse[61].ENA
+en => reg_regs_regs_0_sva_cse[60].ENA
+en => reg_regs_regs_0_sva_cse[59].ENA
+en => reg_regs_regs_0_sva_cse[58].ENA
+en => reg_regs_regs_0_sva_cse[57].ENA
+en => reg_regs_regs_0_sva_cse[56].ENA
+en => reg_regs_regs_0_sva_cse[55].ENA
+en => reg_regs_regs_0_sva_cse[54].ENA
+en => reg_regs_regs_0_sva_cse[53].ENA
+en => reg_regs_regs_0_sva_cse[52].ENA
+en => reg_regs_regs_0_sva_cse[51].ENA
+en => reg_regs_regs_0_sva_cse[50].ENA
+en => reg_regs_regs_0_sva_cse[49].ENA
+en => reg_regs_regs_0_sva_cse[48].ENA
+en => reg_regs_regs_0_sva_cse[47].ENA
+en => reg_regs_regs_0_sva_cse[46].ENA
+en => reg_regs_regs_0_sva_cse[45].ENA
+en => reg_regs_regs_0_sva_cse[44].ENA
+en => reg_regs_regs_0_sva_cse[43].ENA
+en => reg_regs_regs_0_sva_cse[42].ENA
+en => reg_regs_regs_0_sva_cse[41].ENA
+en => reg_regs_regs_0_sva_cse[40].ENA
+en => reg_regs_regs_0_sva_cse[39].ENA
+en => reg_regs_regs_0_sva_cse[38].ENA
+en => reg_regs_regs_0_sva_cse[37].ENA
+en => reg_regs_regs_0_sva_cse[36].ENA
+en => reg_regs_regs_0_sva_cse[35].ENA
+en => reg_regs_regs_0_sva_cse[34].ENA
+en => reg_regs_regs_0_sva_cse[33].ENA
+en => reg_regs_regs_0_sva_cse[32].ENA
+en => reg_regs_regs_0_sva_cse[31].ENA
+en => reg_regs_regs_0_sva_cse[30].ENA
+en => reg_regs_regs_0_sva_cse[29].ENA
+en => reg_regs_regs_0_sva_cse[28].ENA
+en => reg_regs_regs_0_sva_cse[27].ENA
+en => reg_regs_regs_0_sva_cse[26].ENA
+en => reg_regs_regs_0_sva_cse[25].ENA
+en => reg_regs_regs_0_sva_cse[24].ENA
+en => reg_regs_regs_0_sva_cse[23].ENA
+en => reg_regs_regs_0_sva_cse[22].ENA
+en => reg_regs_regs_0_sva_cse[21].ENA
+en => reg_regs_regs_0_sva_cse[20].ENA
+en => reg_regs_regs_0_sva_cse[19].ENA
+en => reg_regs_regs_0_sva_cse[18].ENA
+en => reg_regs_regs_0_sva_cse[17].ENA
+en => reg_regs_regs_0_sva_cse[16].ENA
+en => reg_regs_regs_0_sva_cse[15].ENA
+en => reg_regs_regs_0_sva_cse[14].ENA
+en => reg_regs_regs_0_sva_cse[13].ENA
+en => reg_regs_regs_0_sva_cse[12].ENA
+en => reg_regs_regs_0_sva_cse[11].ENA
+en => reg_regs_regs_0_sva_cse[10].ENA
+en => reg_regs_regs_0_sva_cse[9].ENA
+en => reg_regs_regs_0_sva_cse[8].ENA
+en => reg_regs_regs_0_sva_cse[7].ENA
+en => reg_regs_regs_0_sva_cse[6].ENA
+en => reg_regs_regs_0_sva_cse[5].ENA
+en => reg_regs_regs_0_sva_cse[4].ENA
+en => reg_regs_regs_0_sva_cse[3].ENA
+en => reg_regs_regs_0_sva_cse[2].ENA
+en => reg_regs_regs_0_sva_cse[1].ENA
+arst_n => reg_regs_regs_0_sva_cse[0].ACLR
+arst_n => reg_regs_regs_0_sva_cse[1].ACLR
+arst_n => reg_regs_regs_0_sva_cse[2].ACLR
+arst_n => reg_regs_regs_0_sva_cse[3].ACLR
+arst_n => reg_regs_regs_0_sva_cse[4].ACLR
+arst_n => reg_regs_regs_0_sva_cse[5].ACLR
+arst_n => reg_regs_regs_0_sva_cse[6].ACLR
+arst_n => reg_regs_regs_0_sva_cse[7].ACLR
+arst_n => reg_regs_regs_0_sva_cse[8].ACLR
+arst_n => reg_regs_regs_0_sva_cse[9].ACLR
+arst_n => reg_regs_regs_0_sva_cse[10].ACLR
+arst_n => reg_regs_regs_0_sva_cse[11].ACLR
+arst_n => reg_regs_regs_0_sva_cse[12].ACLR
+arst_n => reg_regs_regs_0_sva_cse[13].ACLR
+arst_n => reg_regs_regs_0_sva_cse[14].ACLR
+arst_n => reg_regs_regs_0_sva_cse[15].ACLR
+arst_n => reg_regs_regs_0_sva_cse[16].ACLR
+arst_n => reg_regs_regs_0_sva_cse[17].ACLR
+arst_n => reg_regs_regs_0_sva_cse[18].ACLR
+arst_n => reg_regs_regs_0_sva_cse[19].ACLR
+arst_n => reg_regs_regs_0_sva_cse[20].ACLR
+arst_n => reg_regs_regs_0_sva_cse[21].ACLR
+arst_n => reg_regs_regs_0_sva_cse[22].ACLR
+arst_n => reg_regs_regs_0_sva_cse[23].ACLR
+arst_n => reg_regs_regs_0_sva_cse[24].ACLR
+arst_n => reg_regs_regs_0_sva_cse[25].ACLR
+arst_n => reg_regs_regs_0_sva_cse[26].ACLR
+arst_n => reg_regs_regs_0_sva_cse[27].ACLR
+arst_n => reg_regs_regs_0_sva_cse[28].ACLR
+arst_n => reg_regs_regs_0_sva_cse[29].ACLR
+arst_n => reg_regs_regs_0_sva_cse[30].ACLR
+arst_n => reg_regs_regs_0_sva_cse[31].ACLR
+arst_n => reg_regs_regs_0_sva_cse[32].ACLR
+arst_n => reg_regs_regs_0_sva_cse[33].ACLR
+arst_n => reg_regs_regs_0_sva_cse[34].ACLR
+arst_n => reg_regs_regs_0_sva_cse[35].ACLR
+arst_n => reg_regs_regs_0_sva_cse[36].ACLR
+arst_n => reg_regs_regs_0_sva_cse[37].ACLR
+arst_n => reg_regs_regs_0_sva_cse[38].ACLR
+arst_n => reg_regs_regs_0_sva_cse[39].ACLR
+arst_n => reg_regs_regs_0_sva_cse[40].ACLR
+arst_n => reg_regs_regs_0_sva_cse[41].ACLR
+arst_n => reg_regs_regs_0_sva_cse[42].ACLR
+arst_n => reg_regs_regs_0_sva_cse[43].ACLR
+arst_n => reg_regs_regs_0_sva_cse[44].ACLR
+arst_n => reg_regs_regs_0_sva_cse[45].ACLR
+arst_n => reg_regs_regs_0_sva_cse[46].ACLR
+arst_n => reg_regs_regs_0_sva_cse[47].ACLR
+arst_n => reg_regs_regs_0_sva_cse[48].ACLR
+arst_n => reg_regs_regs_0_sva_cse[49].ACLR
+arst_n => reg_regs_regs_0_sva_cse[50].ACLR
+arst_n => reg_regs_regs_0_sva_cse[51].ACLR
+arst_n => reg_regs_regs_0_sva_cse[52].ACLR
+arst_n => reg_regs_regs_0_sva_cse[53].ACLR
+arst_n => reg_regs_regs_0_sva_cse[54].ACLR
+arst_n => reg_regs_regs_0_sva_cse[55].ACLR
+arst_n => reg_regs_regs_0_sva_cse[56].ACLR
+arst_n => reg_regs_regs_0_sva_cse[57].ACLR
+arst_n => reg_regs_regs_0_sva_cse[58].ACLR
+arst_n => reg_regs_regs_0_sva_cse[59].ACLR
+arst_n => reg_regs_regs_0_sva_cse[60].ACLR
+arst_n => reg_regs_regs_0_sva_cse[61].ACLR
+arst_n => reg_regs_regs_0_sva_cse[62].ACLR
+arst_n => reg_regs_regs_0_sva_cse[63].ACLR
+arst_n => reg_regs_regs_0_sva_cse[64].ACLR
+arst_n => reg_regs_regs_0_sva_cse[65].ACLR
+arst_n => reg_regs_regs_0_sva_cse[66].ACLR
+arst_n => reg_regs_regs_0_sva_cse[67].ACLR
+arst_n => reg_regs_regs_0_sva_cse[68].ACLR
+arst_n => reg_regs_regs_0_sva_cse[69].ACLR
+arst_n => reg_regs_regs_0_sva_cse[70].ACLR
+arst_n => reg_regs_regs_0_sva_cse[71].ACLR
+arst_n => reg_regs_regs_0_sva_cse[72].ACLR
+arst_n => reg_regs_regs_0_sva_cse[73].ACLR
+arst_n => reg_regs_regs_0_sva_cse[74].ACLR
+arst_n => reg_regs_regs_0_sva_cse[75].ACLR
+arst_n => reg_regs_regs_0_sva_cse[76].ACLR
+arst_n => reg_regs_regs_0_sva_cse[77].ACLR
+arst_n => reg_regs_regs_0_sva_cse[78].ACLR
+arst_n => reg_regs_regs_0_sva_cse[79].ACLR
+arst_n => reg_regs_regs_0_sva_cse[80].ACLR
+arst_n => reg_regs_regs_0_sva_cse[81].ACLR
+arst_n => reg_regs_regs_0_sva_cse[82].ACLR
+arst_n => reg_regs_regs_0_sva_cse[83].ACLR
+arst_n => reg_regs_regs_0_sva_cse[84].ACLR
+arst_n => reg_regs_regs_0_sva_cse[85].ACLR
+arst_n => reg_regs_regs_0_sva_cse[86].ACLR
+arst_n => reg_regs_regs_0_sva_cse[87].ACLR
+arst_n => reg_regs_regs_0_sva_cse[88].ACLR
+arst_n => reg_regs_regs_0_sva_cse[89].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_2_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_1_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_3_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_5_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_4_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_9_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_11_itm[9].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[0].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[1].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[2].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[3].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[4].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[5].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[6].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[7].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[8].ACLR
+arst_n => regs_regs_slc_regs_regs_2_10_itm[9].ACLR
+arst_n => main_stage_0_2.ACLR
+arst_n => ACC1_acc_655_itm_1[0].ACLR
+arst_n => ACC1_acc_655_itm_1[1].ACLR
+arst_n => ACC1_acc_655_itm_1[2].ACLR
+arst_n => ACC1_acc_655_itm_1[3].ACLR
+arst_n => ACC1_acc_655_itm_1[4].ACLR
+arst_n => ACC1_acc_655_itm_1[5].ACLR
+arst_n => ACC1_acc_655_itm_1[6].ACLR
+arst_n => ACC1_acc_655_itm_1[7].ACLR
+arst_n => ACC1_acc_655_itm_1[8].ACLR
+arst_n => ACC1_acc_655_itm_1[9].ACLR
+arst_n => ACC1_acc_655_itm_1[10].ACLR
+arst_n => ACC1_acc_655_itm_1[11].ACLR
+arst_n => ACC1_acc_652_itm_1[0].ACLR
+arst_n => ACC1_acc_652_itm_1[1].ACLR
+arst_n => ACC1_acc_652_itm_1[2].ACLR
+arst_n => ACC1_acc_652_itm_1[3].ACLR
+arst_n => ACC1_acc_652_itm_1[4].ACLR
+arst_n => ACC1_acc_652_itm_1[5].ACLR
+arst_n => ACC1_acc_652_itm_1[6].ACLR
+arst_n => ACC1_acc_652_itm_1[7].ACLR
+arst_n => ACC1_acc_652_itm_1[8].ACLR
+arst_n => ACC1_acc_652_itm_1[9].ACLR
+arst_n => ACC1_acc_652_itm_1[10].ACLR
+arst_n => ACC1_3_slc_acc_10_psp_62_itm_1.ACLR
+arst_n => ACC1_slc_ACC1_acc_228_psp_55_itm_1.ACLR
+arst_n => slc_acc_20_psp_1_93_itm_1.ACLR
+arst_n => ACC1_mul_57_itm_2[0].ACLR
+arst_n => ACC1_mul_57_itm_2[1].ACLR
+arst_n => ACC1_mul_57_itm_1_sg2[0].ACLR
+arst_n => ACC1_mul_57_itm_1_sg2[1].ACLR
+arst_n => ACC1_mul_57_itm_1_sg2[2].ACLR
+arst_n => ACC1_mul_57_itm_1_sg2[3].ACLR
+arst_n => ACC1_mul_57_itm_1_sg2[4].ACLR
+arst_n => ACC1_acc_661_itm_1[0].ACLR
+arst_n => ACC1_acc_661_itm_1[1].ACLR
+arst_n => ACC1_acc_661_itm_1[2].ACLR
+arst_n => ACC1_acc_661_itm_1[3].ACLR
+arst_n => ACC1_acc_661_itm_1[4].ACLR
+arst_n => ACC1_acc_661_itm_1[5].ACLR
+arst_n => ACC1_acc_661_itm_1[6].ACLR
+arst_n => ACC1_acc_661_itm_1[7].ACLR
+arst_n => ACC1_acc_661_itm_1[8].ACLR
+arst_n => ACC1_acc_661_itm_1[9].ACLR
+arst_n => ACC1_acc_661_itm_1[10].ACLR
+arst_n => ACC1_acc_661_itm_1[11].ACLR
+arst_n => ACC1_acc_661_itm_1[12].ACLR
+arst_n => ACC1_acc_661_itm_1[13].ACLR
+arst_n => ACC1_acc_658_itm_1[0].ACLR
+arst_n => ACC1_acc_658_itm_1[1].ACLR
+arst_n => ACC1_acc_658_itm_1[2].ACLR
+arst_n => ACC1_acc_658_itm_1[3].ACLR
+arst_n => ACC1_acc_658_itm_1[4].ACLR
+arst_n => ACC1_acc_658_itm_1[5].ACLR
+arst_n => ACC1_acc_658_itm_1[6].ACLR
+arst_n => ACC1_acc_658_itm_1[7].ACLR
+arst_n => ACC1_acc_658_itm_1[8].ACLR
+arst_n => ACC1_acc_658_itm_1[9].ACLR
+arst_n => ACC1_acc_658_itm_1[10].ACLR
+arst_n => ACC1_acc_658_itm_1[11].ACLR
+arst_n => ACC1_acc_658_itm_1[12].ACLR
+arst_n => ACC1_acc_659_itm_1[0].ACLR
+arst_n => ACC1_acc_659_itm_1[1].ACLR
+arst_n => ACC1_acc_659_itm_1[2].ACLR
+arst_n => ACC1_acc_659_itm_1[3].ACLR
+arst_n => ACC1_acc_659_itm_1[4].ACLR
+arst_n => ACC1_acc_659_itm_1[5].ACLR
+arst_n => ACC1_acc_659_itm_1[6].ACLR
+arst_n => ACC1_acc_659_itm_1[7].ACLR
+arst_n => ACC1_acc_659_itm_1[8].ACLR
+arst_n => ACC1_acc_659_itm_1[9].ACLR
+arst_n => ACC1_acc_659_itm_1[10].ACLR
+arst_n => ACC1_acc_659_itm_1[11].ACLR
+arst_n => ACC1_acc_659_itm_1[12].ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[0]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[1]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[2]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[3]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[4]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[5]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[6]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[7]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[8]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[9]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[10]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[11]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[12]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[13]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[14]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[15]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[16]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[17]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[18]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[19]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[20]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[21]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[22]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[23]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[24]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[25]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[26]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[27]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[28]~reg0.ACLR
+arst_n => vout_rsc_mgc_out_stdreg_d[29]~reg0.ACLR
+vin_rsc_mgc_in_wire_d[0] => Add43.IN22
+vin_rsc_mgc_in_wire_d[0] => reg_regs_regs_0_sva_cse[0].DATAIN
+vin_rsc_mgc_in_wire_d[1] => Add43.IN21
+vin_rsc_mgc_in_wire_d[1] => reg_regs_regs_0_sva_cse[1].DATAIN
+vin_rsc_mgc_in_wire_d[2] => Add43.IN20
+vin_rsc_mgc_in_wire_d[2] => reg_regs_regs_0_sva_cse[2].DATAIN
+vin_rsc_mgc_in_wire_d[3] => Add43.IN19
+vin_rsc_mgc_in_wire_d[3] => reg_regs_regs_0_sva_cse[3].DATAIN
+vin_rsc_mgc_in_wire_d[4] => Add43.IN18
+vin_rsc_mgc_in_wire_d[4] => reg_regs_regs_0_sva_cse[4].DATAIN
+vin_rsc_mgc_in_wire_d[5] => Add43.IN17
+vin_rsc_mgc_in_wire_d[5] => reg_regs_regs_0_sva_cse[5].DATAIN
+vin_rsc_mgc_in_wire_d[6] => Add43.IN16
+vin_rsc_mgc_in_wire_d[6] => reg_regs_regs_0_sva_cse[6].DATAIN
+vin_rsc_mgc_in_wire_d[7] => Add43.IN15
+vin_rsc_mgc_in_wire_d[7] => reg_regs_regs_0_sva_cse[7].DATAIN
+vin_rsc_mgc_in_wire_d[8] => Add43.IN14
+vin_rsc_mgc_in_wire_d[8] => reg_regs_regs_0_sva_cse[8].DATAIN
+vin_rsc_mgc_in_wire_d[9] => Add43.IN12
+vin_rsc_mgc_in_wire_d[9] => Add43.IN13
+vin_rsc_mgc_in_wire_d[9] => reg_regs_regs_0_sva_cse[9].DATAIN
+vin_rsc_mgc_in_wire_d[10] => Add42.IN22
+vin_rsc_mgc_in_wire_d[10] => reg_regs_regs_0_sva_cse[10].DATAIN
+vin_rsc_mgc_in_wire_d[11] => Add42.IN21
+vin_rsc_mgc_in_wire_d[11] => reg_regs_regs_0_sva_cse[11].DATAIN
+vin_rsc_mgc_in_wire_d[12] => Add42.IN20
+vin_rsc_mgc_in_wire_d[12] => reg_regs_regs_0_sva_cse[12].DATAIN
+vin_rsc_mgc_in_wire_d[13] => Add42.IN19
+vin_rsc_mgc_in_wire_d[13] => reg_regs_regs_0_sva_cse[13].DATAIN
+vin_rsc_mgc_in_wire_d[14] => Add42.IN18
+vin_rsc_mgc_in_wire_d[14] => reg_regs_regs_0_sva_cse[14].DATAIN
+vin_rsc_mgc_in_wire_d[15] => Add42.IN17
+vin_rsc_mgc_in_wire_d[15] => reg_regs_regs_0_sva_cse[15].DATAIN
+vin_rsc_mgc_in_wire_d[16] => Add42.IN16
+vin_rsc_mgc_in_wire_d[16] => reg_regs_regs_0_sva_cse[16].DATAIN
+vin_rsc_mgc_in_wire_d[17] => Add42.IN15
+vin_rsc_mgc_in_wire_d[17] => reg_regs_regs_0_sva_cse[17].DATAIN
+vin_rsc_mgc_in_wire_d[18] => Add42.IN14
+vin_rsc_mgc_in_wire_d[18] => reg_regs_regs_0_sva_cse[18].DATAIN
+vin_rsc_mgc_in_wire_d[19] => Add42.IN12
+vin_rsc_mgc_in_wire_d[19] => Add42.IN13
+vin_rsc_mgc_in_wire_d[19] => reg_regs_regs_0_sva_cse[19].DATAIN
+vin_rsc_mgc_in_wire_d[20] => Add42.IN11
+vin_rsc_mgc_in_wire_d[20] => reg_regs_regs_0_sva_cse[20].DATAIN
+vin_rsc_mgc_in_wire_d[21] => Add42.IN10
+vin_rsc_mgc_in_wire_d[21] => reg_regs_regs_0_sva_cse[21].DATAIN
+vin_rsc_mgc_in_wire_d[22] => Add42.IN9
+vin_rsc_mgc_in_wire_d[22] => reg_regs_regs_0_sva_cse[22].DATAIN
+vin_rsc_mgc_in_wire_d[23] => Add42.IN8
+vin_rsc_mgc_in_wire_d[23] => reg_regs_regs_0_sva_cse[23].DATAIN
+vin_rsc_mgc_in_wire_d[24] => Add42.IN7
+vin_rsc_mgc_in_wire_d[24] => reg_regs_regs_0_sva_cse[24].DATAIN
+vin_rsc_mgc_in_wire_d[25] => Add42.IN6
+vin_rsc_mgc_in_wire_d[25] => reg_regs_regs_0_sva_cse[25].DATAIN
+vin_rsc_mgc_in_wire_d[26] => Add42.IN5
+vin_rsc_mgc_in_wire_d[26] => reg_regs_regs_0_sva_cse[26].DATAIN
+vin_rsc_mgc_in_wire_d[27] => Add42.IN4
+vin_rsc_mgc_in_wire_d[27] => reg_regs_regs_0_sva_cse[27].DATAIN
+vin_rsc_mgc_in_wire_d[28] => Add42.IN3
+vin_rsc_mgc_in_wire_d[28] => reg_regs_regs_0_sva_cse[28].DATAIN
+vin_rsc_mgc_in_wire_d[29] => Add42.IN1
+vin_rsc_mgc_in_wire_d[29] => Add42.IN2
+vin_rsc_mgc_in_wire_d[29] => reg_regs_regs_0_sva_cse[29].DATAIN
+vin_rsc_mgc_in_wire_d[30] => Add45.IN11
+vin_rsc_mgc_in_wire_d[30] => reg_regs_regs_0_sva_cse[30].DATAIN
+vin_rsc_mgc_in_wire_d[31] => Add45.IN10
+vin_rsc_mgc_in_wire_d[31] => reg_regs_regs_0_sva_cse[31].DATAIN
+vin_rsc_mgc_in_wire_d[32] => Add45.IN9
+vin_rsc_mgc_in_wire_d[32] => reg_regs_regs_0_sva_cse[32].DATAIN
+vin_rsc_mgc_in_wire_d[33] => Add45.IN8
+vin_rsc_mgc_in_wire_d[33] => reg_regs_regs_0_sva_cse[33].DATAIN
+vin_rsc_mgc_in_wire_d[34] => Add45.IN7
+vin_rsc_mgc_in_wire_d[34] => reg_regs_regs_0_sva_cse[34].DATAIN
+vin_rsc_mgc_in_wire_d[35] => Add45.IN6
+vin_rsc_mgc_in_wire_d[35] => reg_regs_regs_0_sva_cse[35].DATAIN
+vin_rsc_mgc_in_wire_d[36] => Add45.IN5
+vin_rsc_mgc_in_wire_d[36] => reg_regs_regs_0_sva_cse[36].DATAIN
+vin_rsc_mgc_in_wire_d[37] => Add45.IN4
+vin_rsc_mgc_in_wire_d[37] => reg_regs_regs_0_sva_cse[37].DATAIN
+vin_rsc_mgc_in_wire_d[38] => Add45.IN3
+vin_rsc_mgc_in_wire_d[38] => reg_regs_regs_0_sva_cse[38].DATAIN
+vin_rsc_mgc_in_wire_d[39] => Add45.IN1
+vin_rsc_mgc_in_wire_d[39] => Add45.IN2
+vin_rsc_mgc_in_wire_d[39] => reg_regs_regs_0_sva_cse[39].DATAIN
+vin_rsc_mgc_in_wire_d[40] => Add45.IN22
+vin_rsc_mgc_in_wire_d[40] => reg_regs_regs_0_sva_cse[40].DATAIN
+vin_rsc_mgc_in_wire_d[41] => Add45.IN21
+vin_rsc_mgc_in_wire_d[41] => reg_regs_regs_0_sva_cse[41].DATAIN
+vin_rsc_mgc_in_wire_d[42] => Add45.IN20
+vin_rsc_mgc_in_wire_d[42] => reg_regs_regs_0_sva_cse[42].DATAIN
+vin_rsc_mgc_in_wire_d[43] => Add45.IN19
+vin_rsc_mgc_in_wire_d[43] => reg_regs_regs_0_sva_cse[43].DATAIN
+vin_rsc_mgc_in_wire_d[44] => Add45.IN18
+vin_rsc_mgc_in_wire_d[44] => reg_regs_regs_0_sva_cse[44].DATAIN
+vin_rsc_mgc_in_wire_d[45] => Add45.IN17
+vin_rsc_mgc_in_wire_d[45] => reg_regs_regs_0_sva_cse[45].DATAIN
+vin_rsc_mgc_in_wire_d[46] => Add45.IN16
+vin_rsc_mgc_in_wire_d[46] => reg_regs_regs_0_sva_cse[46].DATAIN
+vin_rsc_mgc_in_wire_d[47] => Add45.IN15
+vin_rsc_mgc_in_wire_d[47] => reg_regs_regs_0_sva_cse[47].DATAIN
+vin_rsc_mgc_in_wire_d[48] => Add45.IN14
+vin_rsc_mgc_in_wire_d[48] => reg_regs_regs_0_sva_cse[48].DATAIN
+vin_rsc_mgc_in_wire_d[49] => Add45.IN12
+vin_rsc_mgc_in_wire_d[49] => Add45.IN13
+vin_rsc_mgc_in_wire_d[49] => reg_regs_regs_0_sva_cse[49].DATAIN
+vin_rsc_mgc_in_wire_d[50] => Add46.IN22
+vin_rsc_mgc_in_wire_d[50] => reg_regs_regs_0_sva_cse[50].DATAIN
+vin_rsc_mgc_in_wire_d[51] => Add46.IN21
+vin_rsc_mgc_in_wire_d[51] => reg_regs_regs_0_sva_cse[51].DATAIN
+vin_rsc_mgc_in_wire_d[52] => Add46.IN20
+vin_rsc_mgc_in_wire_d[52] => reg_regs_regs_0_sva_cse[52].DATAIN
+vin_rsc_mgc_in_wire_d[53] => Add46.IN19
+vin_rsc_mgc_in_wire_d[53] => reg_regs_regs_0_sva_cse[53].DATAIN
+vin_rsc_mgc_in_wire_d[54] => Add46.IN18
+vin_rsc_mgc_in_wire_d[54] => reg_regs_regs_0_sva_cse[54].DATAIN
+vin_rsc_mgc_in_wire_d[55] => Add46.IN17
+vin_rsc_mgc_in_wire_d[55] => reg_regs_regs_0_sva_cse[55].DATAIN
+vin_rsc_mgc_in_wire_d[56] => Add46.IN16
+vin_rsc_mgc_in_wire_d[56] => reg_regs_regs_0_sva_cse[56].DATAIN
+vin_rsc_mgc_in_wire_d[57] => Add46.IN15
+vin_rsc_mgc_in_wire_d[57] => reg_regs_regs_0_sva_cse[57].DATAIN
+vin_rsc_mgc_in_wire_d[58] => Add46.IN14
+vin_rsc_mgc_in_wire_d[58] => reg_regs_regs_0_sva_cse[58].DATAIN
+vin_rsc_mgc_in_wire_d[59] => Add46.IN12
+vin_rsc_mgc_in_wire_d[59] => Add46.IN13
+vin_rsc_mgc_in_wire_d[59] => reg_regs_regs_0_sva_cse[59].DATAIN
+vin_rsc_mgc_in_wire_d[60] => Add25.IN22
+vin_rsc_mgc_in_wire_d[60] => Add131.IN22
+vin_rsc_mgc_in_wire_d[60] => reg_regs_regs_0_sva_cse[60].DATAIN
+vin_rsc_mgc_in_wire_d[61] => Add25.IN21
+vin_rsc_mgc_in_wire_d[61] => Add131.IN21
+vin_rsc_mgc_in_wire_d[61] => reg_regs_regs_0_sva_cse[61].DATAIN
+vin_rsc_mgc_in_wire_d[62] => Add25.IN20
+vin_rsc_mgc_in_wire_d[62] => Add131.IN20
+vin_rsc_mgc_in_wire_d[62] => reg_regs_regs_0_sva_cse[62].DATAIN
+vin_rsc_mgc_in_wire_d[63] => Add25.IN19
+vin_rsc_mgc_in_wire_d[63] => Add131.IN19
+vin_rsc_mgc_in_wire_d[63] => reg_regs_regs_0_sva_cse[63].DATAIN
+vin_rsc_mgc_in_wire_d[64] => Add25.IN18
+vin_rsc_mgc_in_wire_d[64] => Add131.IN18
+vin_rsc_mgc_in_wire_d[64] => reg_regs_regs_0_sva_cse[64].DATAIN
+vin_rsc_mgc_in_wire_d[65] => Add25.IN17
+vin_rsc_mgc_in_wire_d[65] => Add131.IN17
+vin_rsc_mgc_in_wire_d[65] => reg_regs_regs_0_sva_cse[65].DATAIN
+vin_rsc_mgc_in_wire_d[66] => Add25.IN16
+vin_rsc_mgc_in_wire_d[66] => Add131.IN16
+vin_rsc_mgc_in_wire_d[66] => reg_regs_regs_0_sva_cse[66].DATAIN
+vin_rsc_mgc_in_wire_d[67] => Add25.IN15
+vin_rsc_mgc_in_wire_d[67] => Add131.IN15
+vin_rsc_mgc_in_wire_d[67] => reg_regs_regs_0_sva_cse[67].DATAIN
+vin_rsc_mgc_in_wire_d[68] => Add25.IN14
+vin_rsc_mgc_in_wire_d[68] => Add131.IN14
+vin_rsc_mgc_in_wire_d[68] => reg_regs_regs_0_sva_cse[68].DATAIN
+vin_rsc_mgc_in_wire_d[69] => Add25.IN12
+vin_rsc_mgc_in_wire_d[69] => Add25.IN13
+vin_rsc_mgc_in_wire_d[69] => Add131.IN12
+vin_rsc_mgc_in_wire_d[69] => Add131.IN13
+vin_rsc_mgc_in_wire_d[69] => reg_regs_regs_0_sva_cse[69].DATAIN
+vin_rsc_mgc_in_wire_d[70] => Add25.IN11
+vin_rsc_mgc_in_wire_d[70] => Add130.IN22
+vin_rsc_mgc_in_wire_d[70] => reg_regs_regs_0_sva_cse[70].DATAIN
+vin_rsc_mgc_in_wire_d[71] => Add25.IN10
+vin_rsc_mgc_in_wire_d[71] => Add130.IN21
+vin_rsc_mgc_in_wire_d[71] => reg_regs_regs_0_sva_cse[71].DATAIN
+vin_rsc_mgc_in_wire_d[72] => Add25.IN9
+vin_rsc_mgc_in_wire_d[72] => Add130.IN20
+vin_rsc_mgc_in_wire_d[72] => reg_regs_regs_0_sva_cse[72].DATAIN
+vin_rsc_mgc_in_wire_d[73] => Add25.IN8
+vin_rsc_mgc_in_wire_d[73] => Add130.IN19
+vin_rsc_mgc_in_wire_d[73] => reg_regs_regs_0_sva_cse[73].DATAIN
+vin_rsc_mgc_in_wire_d[74] => Add25.IN7
+vin_rsc_mgc_in_wire_d[74] => Add130.IN18
+vin_rsc_mgc_in_wire_d[74] => reg_regs_regs_0_sva_cse[74].DATAIN
+vin_rsc_mgc_in_wire_d[75] => Add25.IN6
+vin_rsc_mgc_in_wire_d[75] => Add130.IN17
+vin_rsc_mgc_in_wire_d[75] => reg_regs_regs_0_sva_cse[75].DATAIN
+vin_rsc_mgc_in_wire_d[76] => Add25.IN5
+vin_rsc_mgc_in_wire_d[76] => Add130.IN16
+vin_rsc_mgc_in_wire_d[76] => reg_regs_regs_0_sva_cse[76].DATAIN
+vin_rsc_mgc_in_wire_d[77] => Add25.IN4
+vin_rsc_mgc_in_wire_d[77] => Add130.IN15
+vin_rsc_mgc_in_wire_d[77] => reg_regs_regs_0_sva_cse[77].DATAIN
+vin_rsc_mgc_in_wire_d[78] => Add25.IN3
+vin_rsc_mgc_in_wire_d[78] => Add130.IN14
+vin_rsc_mgc_in_wire_d[78] => reg_regs_regs_0_sva_cse[78].DATAIN
+vin_rsc_mgc_in_wire_d[79] => Add25.IN1
+vin_rsc_mgc_in_wire_d[79] => Add25.IN2
+vin_rsc_mgc_in_wire_d[79] => Add130.IN12
+vin_rsc_mgc_in_wire_d[79] => Add130.IN13
+vin_rsc_mgc_in_wire_d[79] => reg_regs_regs_0_sva_cse[79].DATAIN
+vin_rsc_mgc_in_wire_d[80] => Add26.IN26
+vin_rsc_mgc_in_wire_d[80] => Add130.IN11
+vin_rsc_mgc_in_wire_d[80] => reg_regs_regs_0_sva_cse[80].DATAIN
+vin_rsc_mgc_in_wire_d[81] => Add26.IN25
+vin_rsc_mgc_in_wire_d[81] => Add130.IN10
+vin_rsc_mgc_in_wire_d[81] => reg_regs_regs_0_sva_cse[81].DATAIN
+vin_rsc_mgc_in_wire_d[82] => Add26.IN24
+vin_rsc_mgc_in_wire_d[82] => Add130.IN9
+vin_rsc_mgc_in_wire_d[82] => reg_regs_regs_0_sva_cse[82].DATAIN
+vin_rsc_mgc_in_wire_d[83] => Add26.IN23
+vin_rsc_mgc_in_wire_d[83] => Add130.IN8
+vin_rsc_mgc_in_wire_d[83] => reg_regs_regs_0_sva_cse[83].DATAIN
+vin_rsc_mgc_in_wire_d[84] => Add26.IN22
+vin_rsc_mgc_in_wire_d[84] => Add130.IN7
+vin_rsc_mgc_in_wire_d[84] => reg_regs_regs_0_sva_cse[84].DATAIN
+vin_rsc_mgc_in_wire_d[85] => Add26.IN21
+vin_rsc_mgc_in_wire_d[85] => Add130.IN6
+vin_rsc_mgc_in_wire_d[85] => reg_regs_regs_0_sva_cse[85].DATAIN
+vin_rsc_mgc_in_wire_d[86] => Add26.IN20
+vin_rsc_mgc_in_wire_d[86] => Add130.IN5
+vin_rsc_mgc_in_wire_d[86] => reg_regs_regs_0_sva_cse[86].DATAIN
+vin_rsc_mgc_in_wire_d[87] => Add26.IN19
+vin_rsc_mgc_in_wire_d[87] => Add130.IN4
+vin_rsc_mgc_in_wire_d[87] => reg_regs_regs_0_sva_cse[87].DATAIN
+vin_rsc_mgc_in_wire_d[88] => Add26.IN18
+vin_rsc_mgc_in_wire_d[88] => Add130.IN3
+vin_rsc_mgc_in_wire_d[88] => reg_regs_regs_0_sva_cse[88].DATAIN
+vin_rsc_mgc_in_wire_d[89] => Add26.IN14
+vin_rsc_mgc_in_wire_d[89] => Add26.IN15
+vin_rsc_mgc_in_wire_d[89] => Add26.IN16
+vin_rsc_mgc_in_wire_d[89] => Add26.IN17
+vin_rsc_mgc_in_wire_d[89] => Add130.IN1
+vin_rsc_mgc_in_wire_d[89] => Add130.IN2
+vin_rsc_mgc_in_wire_d[89] => reg_regs_regs_0_sva_cse[89].DATAIN
+vout_rsc_mgc_out_stdreg_d[0] <= vout_rsc_mgc_out_stdreg_d[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[1] <= vout_rsc_mgc_out_stdreg_d[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[2] <= vout_rsc_mgc_out_stdreg_d[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[3] <= vout_rsc_mgc_out_stdreg_d[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[4] <= vout_rsc_mgc_out_stdreg_d[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[5] <= vout_rsc_mgc_out_stdreg_d[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[6] <= vout_rsc_mgc_out_stdreg_d[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[7] <= vout_rsc_mgc_out_stdreg_d[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[8] <= vout_rsc_mgc_out_stdreg_d[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[9] <= vout_rsc_mgc_out_stdreg_d[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[10] <= vout_rsc_mgc_out_stdreg_d[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[11] <= vout_rsc_mgc_out_stdreg_d[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[12] <= vout_rsc_mgc_out_stdreg_d[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[13] <= vout_rsc_mgc_out_stdreg_d[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[14] <= vout_rsc_mgc_out_stdreg_d[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[15] <= vout_rsc_mgc_out_stdreg_d[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[16] <= vout_rsc_mgc_out_stdreg_d[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[17] <= vout_rsc_mgc_out_stdreg_d[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[18] <= vout_rsc_mgc_out_stdreg_d[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[19] <= vout_rsc_mgc_out_stdreg_d[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[20] <= vout_rsc_mgc_out_stdreg_d[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[21] <= vout_rsc_mgc_out_stdreg_d[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[22] <= vout_rsc_mgc_out_stdreg_d[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[23] <= vout_rsc_mgc_out_stdreg_d[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[24] <= vout_rsc_mgc_out_stdreg_d[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[25] <= vout_rsc_mgc_out_stdreg_d[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[26] <= vout_rsc_mgc_out_stdreg_d[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[27] <= vout_rsc_mgc_out_stdreg_d[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[28] <= vout_rsc_mgc_out_stdreg_d[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[29] <= vout_rsc_mgc_out_stdreg_d[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2
+shiftin[0] => shift_taps_jpm:auto_generated.shiftin[0]
+shiftin[1] => shift_taps_jpm:auto_generated.shiftin[1]
+shiftin[2] => shift_taps_jpm:auto_generated.shiftin[2]
+shiftin[3] => shift_taps_jpm:auto_generated.shiftin[3]
+shiftin[4] => shift_taps_jpm:auto_generated.shiftin[4]
+shiftin[5] => shift_taps_jpm:auto_generated.shiftin[5]
+shiftin[6] => shift_taps_jpm:auto_generated.shiftin[6]
+shiftin[7] => shift_taps_jpm:auto_generated.shiftin[7]
+shiftin[8] => shift_taps_jpm:auto_generated.shiftin[8]
+shiftin[9] => shift_taps_jpm:auto_generated.shiftin[9]
+shiftin[10] => shift_taps_jpm:auto_generated.shiftin[10]
+shiftin[11] => shift_taps_jpm:auto_generated.shiftin[11]
+shiftin[12] => shift_taps_jpm:auto_generated.shiftin[12]
+shiftin[13] => shift_taps_jpm:auto_generated.shiftin[13]
+shiftin[14] => shift_taps_jpm:auto_generated.shiftin[14]
+shiftin[15] => shift_taps_jpm:auto_generated.shiftin[15]
+shiftin[16] => shift_taps_jpm:auto_generated.shiftin[16]
+shiftin[17] => shift_taps_jpm:auto_generated.shiftin[17]
+shiftin[18] => shift_taps_jpm:auto_generated.shiftin[18]
+shiftin[19] => shift_taps_jpm:auto_generated.shiftin[19]
+shiftin[20] => shift_taps_jpm:auto_generated.shiftin[20]
+shiftin[21] => shift_taps_jpm:auto_generated.shiftin[21]
+shiftin[22] => shift_taps_jpm:auto_generated.shiftin[22]
+shiftin[23] => shift_taps_jpm:auto_generated.shiftin[23]
+shiftin[24] => shift_taps_jpm:auto_generated.shiftin[24]
+shiftin[25] => shift_taps_jpm:auto_generated.shiftin[25]
+shiftin[26] => shift_taps_jpm:auto_generated.shiftin[26]
+shiftin[27] => shift_taps_jpm:auto_generated.shiftin[27]
+shiftin[28] => shift_taps_jpm:auto_generated.shiftin[28]
+shiftin[29] => shift_taps_jpm:auto_generated.shiftin[29]
+clock => shift_taps_jpm:auto_generated.clock
+clken => shift_taps_jpm:auto_generated.clken
+shiftout[0] <= <GND>
+shiftout[1] <= <GND>
+shiftout[2] <= <GND>
+shiftout[3] <= <GND>
+shiftout[4] <= <GND>
+shiftout[5] <= <GND>
+shiftout[6] <= <GND>
+shiftout[7] <= <GND>
+shiftout[8] <= <GND>
+shiftout[9] <= <GND>
+shiftout[10] <= <GND>
+shiftout[11] <= <GND>
+shiftout[12] <= <GND>
+shiftout[13] <= <GND>
+shiftout[14] <= <GND>
+shiftout[15] <= <GND>
+shiftout[16] <= <GND>
+shiftout[17] <= <GND>
+shiftout[18] <= <GND>
+shiftout[19] <= <GND>
+shiftout[20] <= <GND>
+shiftout[21] <= <GND>
+shiftout[22] <= <GND>
+shiftout[23] <= <GND>
+shiftout[24] <= <GND>
+shiftout[25] <= <GND>
+shiftout[26] <= <GND>
+shiftout[27] <= <GND>
+shiftout[28] <= <GND>
+shiftout[29] <= <GND>
+taps[0] <= shift_taps_jpm:auto_generated.taps[0]
+taps[1] <= shift_taps_jpm:auto_generated.taps[1]
+taps[2] <= shift_taps_jpm:auto_generated.taps[2]
+taps[3] <= shift_taps_jpm:auto_generated.taps[3]
+taps[4] <= shift_taps_jpm:auto_generated.taps[4]
+taps[5] <= shift_taps_jpm:auto_generated.taps[5]
+taps[6] <= shift_taps_jpm:auto_generated.taps[6]
+taps[7] <= shift_taps_jpm:auto_generated.taps[7]
+taps[8] <= shift_taps_jpm:auto_generated.taps[8]
+taps[9] <= shift_taps_jpm:auto_generated.taps[9]
+taps[10] <= shift_taps_jpm:auto_generated.taps[10]
+taps[11] <= shift_taps_jpm:auto_generated.taps[11]
+taps[12] <= shift_taps_jpm:auto_generated.taps[12]
+taps[13] <= shift_taps_jpm:auto_generated.taps[13]
+taps[14] <= shift_taps_jpm:auto_generated.taps[14]
+taps[15] <= shift_taps_jpm:auto_generated.taps[15]
+taps[16] <= shift_taps_jpm:auto_generated.taps[16]
+taps[17] <= shift_taps_jpm:auto_generated.taps[17]
+taps[18] <= shift_taps_jpm:auto_generated.taps[18]
+taps[19] <= shift_taps_jpm:auto_generated.taps[19]
+taps[20] <= shift_taps_jpm:auto_generated.taps[20]
+taps[21] <= shift_taps_jpm:auto_generated.taps[21]
+taps[22] <= shift_taps_jpm:auto_generated.taps[22]
+taps[23] <= shift_taps_jpm:auto_generated.taps[23]
+taps[24] <= shift_taps_jpm:auto_generated.taps[24]
+taps[25] <= shift_taps_jpm:auto_generated.taps[25]
+taps[26] <= shift_taps_jpm:auto_generated.taps[26]
+taps[27] <= shift_taps_jpm:auto_generated.taps[27]
+taps[28] <= shift_taps_jpm:auto_generated.taps[28]
+taps[29] <= shift_taps_jpm:auto_generated.taps[29]
+taps[30] <= shift_taps_jpm:auto_generated.taps[30]
+taps[31] <= shift_taps_jpm:auto_generated.taps[31]
+taps[32] <= shift_taps_jpm:auto_generated.taps[32]
+taps[33] <= shift_taps_jpm:auto_generated.taps[33]
+taps[34] <= shift_taps_jpm:auto_generated.taps[34]
+taps[35] <= shift_taps_jpm:auto_generated.taps[35]
+taps[36] <= shift_taps_jpm:auto_generated.taps[36]
+taps[37] <= shift_taps_jpm:auto_generated.taps[37]
+taps[38] <= shift_taps_jpm:auto_generated.taps[38]
+taps[39] <= shift_taps_jpm:auto_generated.taps[39]
+taps[40] <= shift_taps_jpm:auto_generated.taps[40]
+taps[41] <= shift_taps_jpm:auto_generated.taps[41]
+taps[42] <= shift_taps_jpm:auto_generated.taps[42]
+taps[43] <= shift_taps_jpm:auto_generated.taps[43]
+taps[44] <= shift_taps_jpm:auto_generated.taps[44]
+taps[45] <= shift_taps_jpm:auto_generated.taps[45]
+taps[46] <= shift_taps_jpm:auto_generated.taps[46]
+taps[47] <= shift_taps_jpm:auto_generated.taps[47]
+taps[48] <= shift_taps_jpm:auto_generated.taps[48]
+taps[49] <= shift_taps_jpm:auto_generated.taps[49]
+taps[50] <= shift_taps_jpm:auto_generated.taps[50]
+taps[51] <= shift_taps_jpm:auto_generated.taps[51]
+taps[52] <= shift_taps_jpm:auto_generated.taps[52]
+taps[53] <= shift_taps_jpm:auto_generated.taps[53]
+taps[54] <= shift_taps_jpm:auto_generated.taps[54]
+taps[55] <= shift_taps_jpm:auto_generated.taps[55]
+taps[56] <= shift_taps_jpm:auto_generated.taps[56]
+taps[57] <= shift_taps_jpm:auto_generated.taps[57]
+taps[58] <= shift_taps_jpm:auto_generated.taps[58]
+taps[59] <= shift_taps_jpm:auto_generated.taps[59]
+taps[60] <= shift_taps_jpm:auto_generated.taps[60]
+taps[61] <= shift_taps_jpm:auto_generated.taps[61]
+taps[62] <= shift_taps_jpm:auto_generated.taps[62]
+taps[63] <= shift_taps_jpm:auto_generated.taps[63]
+taps[64] <= shift_taps_jpm:auto_generated.taps[64]
+taps[65] <= shift_taps_jpm:auto_generated.taps[65]
+taps[66] <= shift_taps_jpm:auto_generated.taps[66]
+taps[67] <= shift_taps_jpm:auto_generated.taps[67]
+taps[68] <= shift_taps_jpm:auto_generated.taps[68]
+taps[69] <= shift_taps_jpm:auto_generated.taps[69]
+taps[70] <= shift_taps_jpm:auto_generated.taps[70]
+taps[71] <= shift_taps_jpm:auto_generated.taps[71]
+taps[72] <= shift_taps_jpm:auto_generated.taps[72]
+taps[73] <= shift_taps_jpm:auto_generated.taps[73]
+taps[74] <= shift_taps_jpm:auto_generated.taps[74]
+taps[75] <= shift_taps_jpm:auto_generated.taps[75]
+taps[76] <= shift_taps_jpm:auto_generated.taps[76]
+taps[77] <= shift_taps_jpm:auto_generated.taps[77]
+taps[78] <= shift_taps_jpm:auto_generated.taps[78]
+taps[79] <= shift_taps_jpm:auto_generated.taps[79]
+taps[80] <= shift_taps_jpm:auto_generated.taps[80]
+taps[81] <= shift_taps_jpm:auto_generated.taps[81]
+taps[82] <= shift_taps_jpm:auto_generated.taps[82]
+taps[83] <= shift_taps_jpm:auto_generated.taps[83]
+taps[84] <= shift_taps_jpm:auto_generated.taps[84]
+taps[85] <= shift_taps_jpm:auto_generated.taps[85]
+taps[86] <= shift_taps_jpm:auto_generated.taps[86]
+taps[87] <= shift_taps_jpm:auto_generated.taps[87]
+taps[88] <= shift_taps_jpm:auto_generated.taps[88]
+taps[89] <= shift_taps_jpm:auto_generated.taps[89]
+aclr => ~NO_FANOUT~
+
+
+|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated
+clken => altsyncram_5n81:altsyncram2.clocken0
+clken => cntr_1tf:cntr1.clk_en
+clock => altsyncram_5n81:altsyncram2.clock0
+clock => cntr_1tf:cntr1.clock
+shiftin[0] => altsyncram_5n81:altsyncram2.data_a[0]
+shiftin[1] => altsyncram_5n81:altsyncram2.data_a[1]
+shiftin[2] => altsyncram_5n81:altsyncram2.data_a[2]
+shiftin[3] => altsyncram_5n81:altsyncram2.data_a[3]
+shiftin[4] => altsyncram_5n81:altsyncram2.data_a[4]
+shiftin[5] => altsyncram_5n81:altsyncram2.data_a[5]
+shiftin[6] => altsyncram_5n81:altsyncram2.data_a[6]
+shiftin[7] => altsyncram_5n81:altsyncram2.data_a[7]
+shiftin[8] => altsyncram_5n81:altsyncram2.data_a[8]
+shiftin[9] => altsyncram_5n81:altsyncram2.data_a[9]
+shiftin[10] => altsyncram_5n81:altsyncram2.data_a[10]
+shiftin[11] => altsyncram_5n81:altsyncram2.data_a[11]
+shiftin[12] => altsyncram_5n81:altsyncram2.data_a[12]
+shiftin[13] => altsyncram_5n81:altsyncram2.data_a[13]
+shiftin[14] => altsyncram_5n81:altsyncram2.data_a[14]
+shiftin[15] => altsyncram_5n81:altsyncram2.data_a[15]
+shiftin[16] => altsyncram_5n81:altsyncram2.data_a[16]
+shiftin[17] => altsyncram_5n81:altsyncram2.data_a[17]
+shiftin[18] => altsyncram_5n81:altsyncram2.data_a[18]
+shiftin[19] => altsyncram_5n81:altsyncram2.data_a[19]
+shiftin[20] => altsyncram_5n81:altsyncram2.data_a[20]
+shiftin[21] => altsyncram_5n81:altsyncram2.data_a[21]
+shiftin[22] => altsyncram_5n81:altsyncram2.data_a[22]
+shiftin[23] => altsyncram_5n81:altsyncram2.data_a[23]
+shiftin[24] => altsyncram_5n81:altsyncram2.data_a[24]
+shiftin[25] => altsyncram_5n81:altsyncram2.data_a[25]
+shiftin[26] => altsyncram_5n81:altsyncram2.data_a[26]
+shiftin[27] => altsyncram_5n81:altsyncram2.data_a[27]
+shiftin[28] => altsyncram_5n81:altsyncram2.data_a[28]
+shiftin[29] => altsyncram_5n81:altsyncram2.data_a[29]
+shiftout[0] <= altsyncram_5n81:altsyncram2.q_b[60]
+shiftout[1] <= altsyncram_5n81:altsyncram2.q_b[61]
+shiftout[2] <= altsyncram_5n81:altsyncram2.q_b[62]
+shiftout[3] <= altsyncram_5n81:altsyncram2.q_b[63]
+shiftout[4] <= altsyncram_5n81:altsyncram2.q_b[64]
+shiftout[5] <= altsyncram_5n81:altsyncram2.q_b[65]
+shiftout[6] <= altsyncram_5n81:altsyncram2.q_b[66]
+shiftout[7] <= altsyncram_5n81:altsyncram2.q_b[67]
+shiftout[8] <= altsyncram_5n81:altsyncram2.q_b[68]
+shiftout[9] <= altsyncram_5n81:altsyncram2.q_b[69]
+shiftout[10] <= altsyncram_5n81:altsyncram2.q_b[70]
+shiftout[11] <= altsyncram_5n81:altsyncram2.q_b[71]
+shiftout[12] <= altsyncram_5n81:altsyncram2.q_b[72]
+shiftout[13] <= altsyncram_5n81:altsyncram2.q_b[73]
+shiftout[14] <= altsyncram_5n81:altsyncram2.q_b[74]
+shiftout[15] <= altsyncram_5n81:altsyncram2.q_b[75]
+shiftout[16] <= altsyncram_5n81:altsyncram2.q_b[76]
+shiftout[17] <= altsyncram_5n81:altsyncram2.q_b[77]
+shiftout[18] <= altsyncram_5n81:altsyncram2.q_b[78]
+shiftout[19] <= altsyncram_5n81:altsyncram2.q_b[79]
+shiftout[20] <= altsyncram_5n81:altsyncram2.q_b[80]
+shiftout[21] <= altsyncram_5n81:altsyncram2.q_b[81]
+shiftout[22] <= altsyncram_5n81:altsyncram2.q_b[82]
+shiftout[23] <= altsyncram_5n81:altsyncram2.q_b[83]
+shiftout[24] <= altsyncram_5n81:altsyncram2.q_b[84]
+shiftout[25] <= altsyncram_5n81:altsyncram2.q_b[85]
+shiftout[26] <= altsyncram_5n81:altsyncram2.q_b[86]
+shiftout[27] <= altsyncram_5n81:altsyncram2.q_b[87]
+shiftout[28] <= altsyncram_5n81:altsyncram2.q_b[88]
+shiftout[29] <= altsyncram_5n81:altsyncram2.q_b[89]
+taps[0] <= altsyncram_5n81:altsyncram2.q_b[0]
+taps[1] <= altsyncram_5n81:altsyncram2.q_b[1]
+taps[2] <= altsyncram_5n81:altsyncram2.q_b[2]
+taps[3] <= altsyncram_5n81:altsyncram2.q_b[3]
+taps[4] <= altsyncram_5n81:altsyncram2.q_b[4]
+taps[5] <= altsyncram_5n81:altsyncram2.q_b[5]
+taps[6] <= altsyncram_5n81:altsyncram2.q_b[6]
+taps[7] <= altsyncram_5n81:altsyncram2.q_b[7]
+taps[8] <= altsyncram_5n81:altsyncram2.q_b[8]
+taps[9] <= altsyncram_5n81:altsyncram2.q_b[9]
+taps[10] <= altsyncram_5n81:altsyncram2.q_b[10]
+taps[11] <= altsyncram_5n81:altsyncram2.q_b[11]
+taps[12] <= altsyncram_5n81:altsyncram2.q_b[12]
+taps[13] <= altsyncram_5n81:altsyncram2.q_b[13]
+taps[14] <= altsyncram_5n81:altsyncram2.q_b[14]
+taps[15] <= altsyncram_5n81:altsyncram2.q_b[15]
+taps[16] <= altsyncram_5n81:altsyncram2.q_b[16]
+taps[17] <= altsyncram_5n81:altsyncram2.q_b[17]
+taps[18] <= altsyncram_5n81:altsyncram2.q_b[18]
+taps[19] <= altsyncram_5n81:altsyncram2.q_b[19]
+taps[20] <= altsyncram_5n81:altsyncram2.q_b[20]
+taps[21] <= altsyncram_5n81:altsyncram2.q_b[21]
+taps[22] <= altsyncram_5n81:altsyncram2.q_b[22]
+taps[23] <= altsyncram_5n81:altsyncram2.q_b[23]
+taps[24] <= altsyncram_5n81:altsyncram2.q_b[24]
+taps[25] <= altsyncram_5n81:altsyncram2.q_b[25]
+taps[26] <= altsyncram_5n81:altsyncram2.q_b[26]
+taps[27] <= altsyncram_5n81:altsyncram2.q_b[27]
+taps[28] <= altsyncram_5n81:altsyncram2.q_b[28]
+taps[29] <= altsyncram_5n81:altsyncram2.q_b[29]
+taps[30] <= altsyncram_5n81:altsyncram2.q_b[30]
+taps[31] <= altsyncram_5n81:altsyncram2.q_b[31]
+taps[32] <= altsyncram_5n81:altsyncram2.q_b[32]
+taps[33] <= altsyncram_5n81:altsyncram2.q_b[33]
+taps[34] <= altsyncram_5n81:altsyncram2.q_b[34]
+taps[35] <= altsyncram_5n81:altsyncram2.q_b[35]
+taps[36] <= altsyncram_5n81:altsyncram2.q_b[36]
+taps[37] <= altsyncram_5n81:altsyncram2.q_b[37]
+taps[38] <= altsyncram_5n81:altsyncram2.q_b[38]
+taps[39] <= altsyncram_5n81:altsyncram2.q_b[39]
+taps[40] <= altsyncram_5n81:altsyncram2.q_b[40]
+taps[41] <= altsyncram_5n81:altsyncram2.q_b[41]
+taps[42] <= altsyncram_5n81:altsyncram2.q_b[42]
+taps[43] <= altsyncram_5n81:altsyncram2.q_b[43]
+taps[44] <= altsyncram_5n81:altsyncram2.q_b[44]
+taps[45] <= altsyncram_5n81:altsyncram2.q_b[45]
+taps[46] <= altsyncram_5n81:altsyncram2.q_b[46]
+taps[47] <= altsyncram_5n81:altsyncram2.q_b[47]
+taps[48] <= altsyncram_5n81:altsyncram2.q_b[48]
+taps[49] <= altsyncram_5n81:altsyncram2.q_b[49]
+taps[50] <= altsyncram_5n81:altsyncram2.q_b[50]
+taps[51] <= altsyncram_5n81:altsyncram2.q_b[51]
+taps[52] <= altsyncram_5n81:altsyncram2.q_b[52]
+taps[53] <= altsyncram_5n81:altsyncram2.q_b[53]
+taps[54] <= altsyncram_5n81:altsyncram2.q_b[54]
+taps[55] <= altsyncram_5n81:altsyncram2.q_b[55]
+taps[56] <= altsyncram_5n81:altsyncram2.q_b[56]
+taps[57] <= altsyncram_5n81:altsyncram2.q_b[57]
+taps[58] <= altsyncram_5n81:altsyncram2.q_b[58]
+taps[59] <= altsyncram_5n81:altsyncram2.q_b[59]
+taps[60] <= altsyncram_5n81:altsyncram2.q_b[60]
+taps[61] <= altsyncram_5n81:altsyncram2.q_b[61]
+taps[62] <= altsyncram_5n81:altsyncram2.q_b[62]
+taps[63] <= altsyncram_5n81:altsyncram2.q_b[63]
+taps[64] <= altsyncram_5n81:altsyncram2.q_b[64]
+taps[65] <= altsyncram_5n81:altsyncram2.q_b[65]
+taps[66] <= altsyncram_5n81:altsyncram2.q_b[66]
+taps[67] <= altsyncram_5n81:altsyncram2.q_b[67]
+taps[68] <= altsyncram_5n81:altsyncram2.q_b[68]
+taps[69] <= altsyncram_5n81:altsyncram2.q_b[69]
+taps[70] <= altsyncram_5n81:altsyncram2.q_b[70]
+taps[71] <= altsyncram_5n81:altsyncram2.q_b[71]
+taps[72] <= altsyncram_5n81:altsyncram2.q_b[72]
+taps[73] <= altsyncram_5n81:altsyncram2.q_b[73]
+taps[74] <= altsyncram_5n81:altsyncram2.q_b[74]
+taps[75] <= altsyncram_5n81:altsyncram2.q_b[75]
+taps[76] <= altsyncram_5n81:altsyncram2.q_b[76]
+taps[77] <= altsyncram_5n81:altsyncram2.q_b[77]
+taps[78] <= altsyncram_5n81:altsyncram2.q_b[78]
+taps[79] <= altsyncram_5n81:altsyncram2.q_b[79]
+taps[80] <= altsyncram_5n81:altsyncram2.q_b[80]
+taps[81] <= altsyncram_5n81:altsyncram2.q_b[81]
+taps[82] <= altsyncram_5n81:altsyncram2.q_b[82]
+taps[83] <= altsyncram_5n81:altsyncram2.q_b[83]
+taps[84] <= altsyncram_5n81:altsyncram2.q_b[84]
+taps[85] <= altsyncram_5n81:altsyncram2.q_b[85]
+taps[86] <= altsyncram_5n81:altsyncram2.q_b[86]
+taps[87] <= altsyncram_5n81:altsyncram2.q_b[87]
+taps[88] <= altsyncram_5n81:altsyncram2.q_b[88]
+taps[89] <= altsyncram_5n81:altsyncram2.q_b[89]
+
+
+|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|altsyncram_5n81:altsyncram2
+address_a[0] => ram_block3a0.PORTAADDR
+address_a[0] => ram_block3a1.PORTAADDR
+address_a[0] => ram_block3a2.PORTAADDR
+address_a[0] => ram_block3a3.PORTAADDR
+address_a[0] => ram_block3a4.PORTAADDR
+address_a[0] => ram_block3a5.PORTAADDR
+address_a[0] => ram_block3a6.PORTAADDR
+address_a[0] => ram_block3a7.PORTAADDR
+address_a[0] => ram_block3a8.PORTAADDR
+address_a[0] => ram_block3a9.PORTAADDR
+address_a[0] => ram_block3a10.PORTAADDR
+address_a[0] => ram_block3a11.PORTAADDR
+address_a[0] => ram_block3a12.PORTAADDR
+address_a[0] => ram_block3a13.PORTAADDR
+address_a[0] => ram_block3a14.PORTAADDR
+address_a[0] => ram_block3a15.PORTAADDR
+address_a[0] => ram_block3a16.PORTAADDR
+address_a[0] => ram_block3a17.PORTAADDR
+address_a[0] => ram_block3a18.PORTAADDR
+address_a[0] => ram_block3a19.PORTAADDR
+address_a[0] => ram_block3a20.PORTAADDR
+address_a[0] => ram_block3a21.PORTAADDR
+address_a[0] => ram_block3a22.PORTAADDR
+address_a[0] => ram_block3a23.PORTAADDR
+address_a[0] => ram_block3a24.PORTAADDR
+address_a[0] => ram_block3a25.PORTAADDR
+address_a[0] => ram_block3a26.PORTAADDR
+address_a[0] => ram_block3a27.PORTAADDR
+address_a[0] => ram_block3a28.PORTAADDR
+address_a[0] => ram_block3a29.PORTAADDR
+address_a[0] => ram_block3a30.PORTAADDR
+address_a[0] => ram_block3a31.PORTAADDR
+address_a[0] => ram_block3a32.PORTAADDR
+address_a[0] => ram_block3a33.PORTAADDR
+address_a[0] => ram_block3a34.PORTAADDR
+address_a[0] => ram_block3a35.PORTAADDR
+address_a[0] => ram_block3a36.PORTAADDR
+address_a[0] => ram_block3a37.PORTAADDR
+address_a[0] => ram_block3a38.PORTAADDR
+address_a[0] => ram_block3a39.PORTAADDR
+address_a[0] => ram_block3a40.PORTAADDR
+address_a[0] => ram_block3a41.PORTAADDR
+address_a[0] => ram_block3a42.PORTAADDR
+address_a[0] => ram_block3a43.PORTAADDR
+address_a[0] => ram_block3a44.PORTAADDR
+address_a[0] => ram_block3a45.PORTAADDR
+address_a[0] => ram_block3a46.PORTAADDR
+address_a[0] => ram_block3a47.PORTAADDR
+address_a[0] => ram_block3a48.PORTAADDR
+address_a[0] => ram_block3a49.PORTAADDR
+address_a[0] => ram_block3a50.PORTAADDR
+address_a[0] => ram_block3a51.PORTAADDR
+address_a[0] => ram_block3a52.PORTAADDR
+address_a[0] => ram_block3a53.PORTAADDR
+address_a[0] => ram_block3a54.PORTAADDR
+address_a[0] => ram_block3a55.PORTAADDR
+address_a[0] => ram_block3a56.PORTAADDR
+address_a[0] => ram_block3a57.PORTAADDR
+address_a[0] => ram_block3a58.PORTAADDR
+address_a[0] => ram_block3a59.PORTAADDR
+address_a[0] => ram_block3a60.PORTAADDR
+address_a[0] => ram_block3a61.PORTAADDR
+address_a[0] => ram_block3a62.PORTAADDR
+address_a[0] => ram_block3a63.PORTAADDR
+address_a[0] => ram_block3a64.PORTAADDR
+address_a[0] => ram_block3a65.PORTAADDR
+address_a[0] => ram_block3a66.PORTAADDR
+address_a[0] => ram_block3a67.PORTAADDR
+address_a[0] => ram_block3a68.PORTAADDR
+address_a[0] => ram_block3a69.PORTAADDR
+address_a[0] => ram_block3a70.PORTAADDR
+address_a[0] => ram_block3a71.PORTAADDR
+address_a[0] => ram_block3a72.PORTAADDR
+address_a[0] => ram_block3a73.PORTAADDR
+address_a[0] => ram_block3a74.PORTAADDR
+address_a[0] => ram_block3a75.PORTAADDR
+address_a[0] => ram_block3a76.PORTAADDR
+address_a[0] => ram_block3a77.PORTAADDR
+address_a[0] => ram_block3a78.PORTAADDR
+address_a[0] => ram_block3a79.PORTAADDR
+address_a[0] => ram_block3a80.PORTAADDR
+address_a[0] => ram_block3a81.PORTAADDR
+address_a[0] => ram_block3a82.PORTAADDR
+address_a[0] => ram_block3a83.PORTAADDR
+address_a[0] => ram_block3a84.PORTAADDR
+address_a[0] => ram_block3a85.PORTAADDR
+address_a[0] => ram_block3a86.PORTAADDR
+address_a[0] => ram_block3a87.PORTAADDR
+address_a[0] => ram_block3a88.PORTAADDR
+address_a[0] => ram_block3a89.PORTAADDR
+address_a[1] => ram_block3a0.PORTAADDR1
+address_a[1] => ram_block3a1.PORTAADDR1
+address_a[1] => ram_block3a2.PORTAADDR1
+address_a[1] => ram_block3a3.PORTAADDR1
+address_a[1] => ram_block3a4.PORTAADDR1
+address_a[1] => ram_block3a5.PORTAADDR1
+address_a[1] => ram_block3a6.PORTAADDR1
+address_a[1] => ram_block3a7.PORTAADDR1
+address_a[1] => ram_block3a8.PORTAADDR1
+address_a[1] => ram_block3a9.PORTAADDR1
+address_a[1] => ram_block3a10.PORTAADDR1
+address_a[1] => ram_block3a11.PORTAADDR1
+address_a[1] => ram_block3a12.PORTAADDR1
+address_a[1] => ram_block3a13.PORTAADDR1
+address_a[1] => ram_block3a14.PORTAADDR1
+address_a[1] => ram_block3a15.PORTAADDR1
+address_a[1] => ram_block3a16.PORTAADDR1
+address_a[1] => ram_block3a17.PORTAADDR1
+address_a[1] => ram_block3a18.PORTAADDR1
+address_a[1] => ram_block3a19.PORTAADDR1
+address_a[1] => ram_block3a20.PORTAADDR1
+address_a[1] => ram_block3a21.PORTAADDR1
+address_a[1] => ram_block3a22.PORTAADDR1
+address_a[1] => ram_block3a23.PORTAADDR1
+address_a[1] => ram_block3a24.PORTAADDR1
+address_a[1] => ram_block3a25.PORTAADDR1
+address_a[1] => ram_block3a26.PORTAADDR1
+address_a[1] => ram_block3a27.PORTAADDR1
+address_a[1] => ram_block3a28.PORTAADDR1
+address_a[1] => ram_block3a29.PORTAADDR1
+address_a[1] => ram_block3a30.PORTAADDR1
+address_a[1] => ram_block3a31.PORTAADDR1
+address_a[1] => ram_block3a32.PORTAADDR1
+address_a[1] => ram_block3a33.PORTAADDR1
+address_a[1] => ram_block3a34.PORTAADDR1
+address_a[1] => ram_block3a35.PORTAADDR1
+address_a[1] => ram_block3a36.PORTAADDR1
+address_a[1] => ram_block3a37.PORTAADDR1
+address_a[1] => ram_block3a38.PORTAADDR1
+address_a[1] => ram_block3a39.PORTAADDR1
+address_a[1] => ram_block3a40.PORTAADDR1
+address_a[1] => ram_block3a41.PORTAADDR1
+address_a[1] => ram_block3a42.PORTAADDR1
+address_a[1] => ram_block3a43.PORTAADDR1
+address_a[1] => ram_block3a44.PORTAADDR1
+address_a[1] => ram_block3a45.PORTAADDR1
+address_a[1] => ram_block3a46.PORTAADDR1
+address_a[1] => ram_block3a47.PORTAADDR1
+address_a[1] => ram_block3a48.PORTAADDR1
+address_a[1] => ram_block3a49.PORTAADDR1
+address_a[1] => ram_block3a50.PORTAADDR1
+address_a[1] => ram_block3a51.PORTAADDR1
+address_a[1] => ram_block3a52.PORTAADDR1
+address_a[1] => ram_block3a53.PORTAADDR1
+address_a[1] => ram_block3a54.PORTAADDR1
+address_a[1] => ram_block3a55.PORTAADDR1
+address_a[1] => ram_block3a56.PORTAADDR1
+address_a[1] => ram_block3a57.PORTAADDR1
+address_a[1] => ram_block3a58.PORTAADDR1
+address_a[1] => ram_block3a59.PORTAADDR1
+address_a[1] => ram_block3a60.PORTAADDR1
+address_a[1] => ram_block3a61.PORTAADDR1
+address_a[1] => ram_block3a62.PORTAADDR1
+address_a[1] => ram_block3a63.PORTAADDR1
+address_a[1] => ram_block3a64.PORTAADDR1
+address_a[1] => ram_block3a65.PORTAADDR1
+address_a[1] => ram_block3a66.PORTAADDR1
+address_a[1] => ram_block3a67.PORTAADDR1
+address_a[1] => ram_block3a68.PORTAADDR1
+address_a[1] => ram_block3a69.PORTAADDR1
+address_a[1] => ram_block3a70.PORTAADDR1
+address_a[1] => ram_block3a71.PORTAADDR1
+address_a[1] => ram_block3a72.PORTAADDR1
+address_a[1] => ram_block3a73.PORTAADDR1
+address_a[1] => ram_block3a74.PORTAADDR1
+address_a[1] => ram_block3a75.PORTAADDR1
+address_a[1] => ram_block3a76.PORTAADDR1
+address_a[1] => ram_block3a77.PORTAADDR1
+address_a[1] => ram_block3a78.PORTAADDR1
+address_a[1] => ram_block3a79.PORTAADDR1
+address_a[1] => ram_block3a80.PORTAADDR1
+address_a[1] => ram_block3a81.PORTAADDR1
+address_a[1] => ram_block3a82.PORTAADDR1
+address_a[1] => ram_block3a83.PORTAADDR1
+address_a[1] => ram_block3a84.PORTAADDR1
+address_a[1] => ram_block3a85.PORTAADDR1
+address_a[1] => ram_block3a86.PORTAADDR1
+address_a[1] => ram_block3a87.PORTAADDR1
+address_a[1] => ram_block3a88.PORTAADDR1
+address_a[1] => ram_block3a89.PORTAADDR1
+address_a[2] => ram_block3a0.PORTAADDR2
+address_a[2] => ram_block3a1.PORTAADDR2
+address_a[2] => ram_block3a2.PORTAADDR2
+address_a[2] => ram_block3a3.PORTAADDR2
+address_a[2] => ram_block3a4.PORTAADDR2
+address_a[2] => ram_block3a5.PORTAADDR2
+address_a[2] => ram_block3a6.PORTAADDR2
+address_a[2] => ram_block3a7.PORTAADDR2
+address_a[2] => ram_block3a8.PORTAADDR2
+address_a[2] => ram_block3a9.PORTAADDR2
+address_a[2] => ram_block3a10.PORTAADDR2
+address_a[2] => ram_block3a11.PORTAADDR2
+address_a[2] => ram_block3a12.PORTAADDR2
+address_a[2] => ram_block3a13.PORTAADDR2
+address_a[2] => ram_block3a14.PORTAADDR2
+address_a[2] => ram_block3a15.PORTAADDR2
+address_a[2] => ram_block3a16.PORTAADDR2
+address_a[2] => ram_block3a17.PORTAADDR2
+address_a[2] => ram_block3a18.PORTAADDR2
+address_a[2] => ram_block3a19.PORTAADDR2
+address_a[2] => ram_block3a20.PORTAADDR2
+address_a[2] => ram_block3a21.PORTAADDR2
+address_a[2] => ram_block3a22.PORTAADDR2
+address_a[2] => ram_block3a23.PORTAADDR2
+address_a[2] => ram_block3a24.PORTAADDR2
+address_a[2] => ram_block3a25.PORTAADDR2
+address_a[2] => ram_block3a26.PORTAADDR2
+address_a[2] => ram_block3a27.PORTAADDR2
+address_a[2] => ram_block3a28.PORTAADDR2
+address_a[2] => ram_block3a29.PORTAADDR2
+address_a[2] => ram_block3a30.PORTAADDR2
+address_a[2] => ram_block3a31.PORTAADDR2
+address_a[2] => ram_block3a32.PORTAADDR2
+address_a[2] => ram_block3a33.PORTAADDR2
+address_a[2] => ram_block3a34.PORTAADDR2
+address_a[2] => ram_block3a35.PORTAADDR2
+address_a[2] => ram_block3a36.PORTAADDR2
+address_a[2] => ram_block3a37.PORTAADDR2
+address_a[2] => ram_block3a38.PORTAADDR2
+address_a[2] => ram_block3a39.PORTAADDR2
+address_a[2] => ram_block3a40.PORTAADDR2
+address_a[2] => ram_block3a41.PORTAADDR2
+address_a[2] => ram_block3a42.PORTAADDR2
+address_a[2] => ram_block3a43.PORTAADDR2
+address_a[2] => ram_block3a44.PORTAADDR2
+address_a[2] => ram_block3a45.PORTAADDR2
+address_a[2] => ram_block3a46.PORTAADDR2
+address_a[2] => ram_block3a47.PORTAADDR2
+address_a[2] => ram_block3a48.PORTAADDR2
+address_a[2] => ram_block3a49.PORTAADDR2
+address_a[2] => ram_block3a50.PORTAADDR2
+address_a[2] => ram_block3a51.PORTAADDR2
+address_a[2] => ram_block3a52.PORTAADDR2
+address_a[2] => ram_block3a53.PORTAADDR2
+address_a[2] => ram_block3a54.PORTAADDR2
+address_a[2] => ram_block3a55.PORTAADDR2
+address_a[2] => ram_block3a56.PORTAADDR2
+address_a[2] => ram_block3a57.PORTAADDR2
+address_a[2] => ram_block3a58.PORTAADDR2
+address_a[2] => ram_block3a59.PORTAADDR2
+address_a[2] => ram_block3a60.PORTAADDR2
+address_a[2] => ram_block3a61.PORTAADDR2
+address_a[2] => ram_block3a62.PORTAADDR2
+address_a[2] => ram_block3a63.PORTAADDR2
+address_a[2] => ram_block3a64.PORTAADDR2
+address_a[2] => ram_block3a65.PORTAADDR2
+address_a[2] => ram_block3a66.PORTAADDR2
+address_a[2] => ram_block3a67.PORTAADDR2
+address_a[2] => ram_block3a68.PORTAADDR2
+address_a[2] => ram_block3a69.PORTAADDR2
+address_a[2] => ram_block3a70.PORTAADDR2
+address_a[2] => ram_block3a71.PORTAADDR2
+address_a[2] => ram_block3a72.PORTAADDR2
+address_a[2] => ram_block3a73.PORTAADDR2
+address_a[2] => ram_block3a74.PORTAADDR2
+address_a[2] => ram_block3a75.PORTAADDR2
+address_a[2] => ram_block3a76.PORTAADDR2
+address_a[2] => ram_block3a77.PORTAADDR2
+address_a[2] => ram_block3a78.PORTAADDR2
+address_a[2] => ram_block3a79.PORTAADDR2
+address_a[2] => ram_block3a80.PORTAADDR2
+address_a[2] => ram_block3a81.PORTAADDR2
+address_a[2] => ram_block3a82.PORTAADDR2
+address_a[2] => ram_block3a83.PORTAADDR2
+address_a[2] => ram_block3a84.PORTAADDR2
+address_a[2] => ram_block3a85.PORTAADDR2
+address_a[2] => ram_block3a86.PORTAADDR2
+address_a[2] => ram_block3a87.PORTAADDR2
+address_a[2] => ram_block3a88.PORTAADDR2
+address_a[2] => ram_block3a89.PORTAADDR2
+address_a[3] => ram_block3a0.PORTAADDR3
+address_a[3] => ram_block3a1.PORTAADDR3
+address_a[3] => ram_block3a2.PORTAADDR3
+address_a[3] => ram_block3a3.PORTAADDR3
+address_a[3] => ram_block3a4.PORTAADDR3
+address_a[3] => ram_block3a5.PORTAADDR3
+address_a[3] => ram_block3a6.PORTAADDR3
+address_a[3] => ram_block3a7.PORTAADDR3
+address_a[3] => ram_block3a8.PORTAADDR3
+address_a[3] => ram_block3a9.PORTAADDR3
+address_a[3] => ram_block3a10.PORTAADDR3
+address_a[3] => ram_block3a11.PORTAADDR3
+address_a[3] => ram_block3a12.PORTAADDR3
+address_a[3] => ram_block3a13.PORTAADDR3
+address_a[3] => ram_block3a14.PORTAADDR3
+address_a[3] => ram_block3a15.PORTAADDR3
+address_a[3] => ram_block3a16.PORTAADDR3
+address_a[3] => ram_block3a17.PORTAADDR3
+address_a[3] => ram_block3a18.PORTAADDR3
+address_a[3] => ram_block3a19.PORTAADDR3
+address_a[3] => ram_block3a20.PORTAADDR3
+address_a[3] => ram_block3a21.PORTAADDR3
+address_a[3] => ram_block3a22.PORTAADDR3
+address_a[3] => ram_block3a23.PORTAADDR3
+address_a[3] => ram_block3a24.PORTAADDR3
+address_a[3] => ram_block3a25.PORTAADDR3
+address_a[3] => ram_block3a26.PORTAADDR3
+address_a[3] => ram_block3a27.PORTAADDR3
+address_a[3] => ram_block3a28.PORTAADDR3
+address_a[3] => ram_block3a29.PORTAADDR3
+address_a[3] => ram_block3a30.PORTAADDR3
+address_a[3] => ram_block3a31.PORTAADDR3
+address_a[3] => ram_block3a32.PORTAADDR3
+address_a[3] => ram_block3a33.PORTAADDR3
+address_a[3] => ram_block3a34.PORTAADDR3
+address_a[3] => ram_block3a35.PORTAADDR3
+address_a[3] => ram_block3a36.PORTAADDR3
+address_a[3] => ram_block3a37.PORTAADDR3
+address_a[3] => ram_block3a38.PORTAADDR3
+address_a[3] => ram_block3a39.PORTAADDR3
+address_a[3] => ram_block3a40.PORTAADDR3
+address_a[3] => ram_block3a41.PORTAADDR3
+address_a[3] => ram_block3a42.PORTAADDR3
+address_a[3] => ram_block3a43.PORTAADDR3
+address_a[3] => ram_block3a44.PORTAADDR3
+address_a[3] => ram_block3a45.PORTAADDR3
+address_a[3] => ram_block3a46.PORTAADDR3
+address_a[3] => ram_block3a47.PORTAADDR3
+address_a[3] => ram_block3a48.PORTAADDR3
+address_a[3] => ram_block3a49.PORTAADDR3
+address_a[3] => ram_block3a50.PORTAADDR3
+address_a[3] => ram_block3a51.PORTAADDR3
+address_a[3] => ram_block3a52.PORTAADDR3
+address_a[3] => ram_block3a53.PORTAADDR3
+address_a[3] => ram_block3a54.PORTAADDR3
+address_a[3] => ram_block3a55.PORTAADDR3
+address_a[3] => ram_block3a56.PORTAADDR3
+address_a[3] => ram_block3a57.PORTAADDR3
+address_a[3] => ram_block3a58.PORTAADDR3
+address_a[3] => ram_block3a59.PORTAADDR3
+address_a[3] => ram_block3a60.PORTAADDR3
+address_a[3] => ram_block3a61.PORTAADDR3
+address_a[3] => ram_block3a62.PORTAADDR3
+address_a[3] => ram_block3a63.PORTAADDR3
+address_a[3] => ram_block3a64.PORTAADDR3
+address_a[3] => ram_block3a65.PORTAADDR3
+address_a[3] => ram_block3a66.PORTAADDR3
+address_a[3] => ram_block3a67.PORTAADDR3
+address_a[3] => ram_block3a68.PORTAADDR3
+address_a[3] => ram_block3a69.PORTAADDR3
+address_a[3] => ram_block3a70.PORTAADDR3
+address_a[3] => ram_block3a71.PORTAADDR3
+address_a[3] => ram_block3a72.PORTAADDR3
+address_a[3] => ram_block3a73.PORTAADDR3
+address_a[3] => ram_block3a74.PORTAADDR3
+address_a[3] => ram_block3a75.PORTAADDR3
+address_a[3] => ram_block3a76.PORTAADDR3
+address_a[3] => ram_block3a77.PORTAADDR3
+address_a[3] => ram_block3a78.PORTAADDR3
+address_a[3] => ram_block3a79.PORTAADDR3
+address_a[3] => ram_block3a80.PORTAADDR3
+address_a[3] => ram_block3a81.PORTAADDR3
+address_a[3] => ram_block3a82.PORTAADDR3
+address_a[3] => ram_block3a83.PORTAADDR3
+address_a[3] => ram_block3a84.PORTAADDR3
+address_a[3] => ram_block3a85.PORTAADDR3
+address_a[3] => ram_block3a86.PORTAADDR3
+address_a[3] => ram_block3a87.PORTAADDR3
+address_a[3] => ram_block3a88.PORTAADDR3
+address_a[3] => ram_block3a89.PORTAADDR3
+address_a[4] => ram_block3a0.PORTAADDR4
+address_a[4] => ram_block3a1.PORTAADDR4
+address_a[4] => ram_block3a2.PORTAADDR4
+address_a[4] => ram_block3a3.PORTAADDR4
+address_a[4] => ram_block3a4.PORTAADDR4
+address_a[4] => ram_block3a5.PORTAADDR4
+address_a[4] => ram_block3a6.PORTAADDR4
+address_a[4] => ram_block3a7.PORTAADDR4
+address_a[4] => ram_block3a8.PORTAADDR4
+address_a[4] => ram_block3a9.PORTAADDR4
+address_a[4] => ram_block3a10.PORTAADDR4
+address_a[4] => ram_block3a11.PORTAADDR4
+address_a[4] => ram_block3a12.PORTAADDR4
+address_a[4] => ram_block3a13.PORTAADDR4
+address_a[4] => ram_block3a14.PORTAADDR4
+address_a[4] => ram_block3a15.PORTAADDR4
+address_a[4] => ram_block3a16.PORTAADDR4
+address_a[4] => ram_block3a17.PORTAADDR4
+address_a[4] => ram_block3a18.PORTAADDR4
+address_a[4] => ram_block3a19.PORTAADDR4
+address_a[4] => ram_block3a20.PORTAADDR4
+address_a[4] => ram_block3a21.PORTAADDR4
+address_a[4] => ram_block3a22.PORTAADDR4
+address_a[4] => ram_block3a23.PORTAADDR4
+address_a[4] => ram_block3a24.PORTAADDR4
+address_a[4] => ram_block3a25.PORTAADDR4
+address_a[4] => ram_block3a26.PORTAADDR4
+address_a[4] => ram_block3a27.PORTAADDR4
+address_a[4] => ram_block3a28.PORTAADDR4
+address_a[4] => ram_block3a29.PORTAADDR4
+address_a[4] => ram_block3a30.PORTAADDR4
+address_a[4] => ram_block3a31.PORTAADDR4
+address_a[4] => ram_block3a32.PORTAADDR4
+address_a[4] => ram_block3a33.PORTAADDR4
+address_a[4] => ram_block3a34.PORTAADDR4
+address_a[4] => ram_block3a35.PORTAADDR4
+address_a[4] => ram_block3a36.PORTAADDR4
+address_a[4] => ram_block3a37.PORTAADDR4
+address_a[4] => ram_block3a38.PORTAADDR4
+address_a[4] => ram_block3a39.PORTAADDR4
+address_a[4] => ram_block3a40.PORTAADDR4
+address_a[4] => ram_block3a41.PORTAADDR4
+address_a[4] => ram_block3a42.PORTAADDR4
+address_a[4] => ram_block3a43.PORTAADDR4
+address_a[4] => ram_block3a44.PORTAADDR4
+address_a[4] => ram_block3a45.PORTAADDR4
+address_a[4] => ram_block3a46.PORTAADDR4
+address_a[4] => ram_block3a47.PORTAADDR4
+address_a[4] => ram_block3a48.PORTAADDR4
+address_a[4] => ram_block3a49.PORTAADDR4
+address_a[4] => ram_block3a50.PORTAADDR4
+address_a[4] => ram_block3a51.PORTAADDR4
+address_a[4] => ram_block3a52.PORTAADDR4
+address_a[4] => ram_block3a53.PORTAADDR4
+address_a[4] => ram_block3a54.PORTAADDR4
+address_a[4] => ram_block3a55.PORTAADDR4
+address_a[4] => ram_block3a56.PORTAADDR4
+address_a[4] => ram_block3a57.PORTAADDR4
+address_a[4] => ram_block3a58.PORTAADDR4
+address_a[4] => ram_block3a59.PORTAADDR4
+address_a[4] => ram_block3a60.PORTAADDR4
+address_a[4] => ram_block3a61.PORTAADDR4
+address_a[4] => ram_block3a62.PORTAADDR4
+address_a[4] => ram_block3a63.PORTAADDR4
+address_a[4] => ram_block3a64.PORTAADDR4
+address_a[4] => ram_block3a65.PORTAADDR4
+address_a[4] => ram_block3a66.PORTAADDR4
+address_a[4] => ram_block3a67.PORTAADDR4
+address_a[4] => ram_block3a68.PORTAADDR4
+address_a[4] => ram_block3a69.PORTAADDR4
+address_a[4] => ram_block3a70.PORTAADDR4
+address_a[4] => ram_block3a71.PORTAADDR4
+address_a[4] => ram_block3a72.PORTAADDR4
+address_a[4] => ram_block3a73.PORTAADDR4
+address_a[4] => ram_block3a74.PORTAADDR4
+address_a[4] => ram_block3a75.PORTAADDR4
+address_a[4] => ram_block3a76.PORTAADDR4
+address_a[4] => ram_block3a77.PORTAADDR4
+address_a[4] => ram_block3a78.PORTAADDR4
+address_a[4] => ram_block3a79.PORTAADDR4
+address_a[4] => ram_block3a80.PORTAADDR4
+address_a[4] => ram_block3a81.PORTAADDR4
+address_a[4] => ram_block3a82.PORTAADDR4
+address_a[4] => ram_block3a83.PORTAADDR4
+address_a[4] => ram_block3a84.PORTAADDR4
+address_a[4] => ram_block3a85.PORTAADDR4
+address_a[4] => ram_block3a86.PORTAADDR4
+address_a[4] => ram_block3a87.PORTAADDR4
+address_a[4] => ram_block3a88.PORTAADDR4
+address_a[4] => ram_block3a89.PORTAADDR4
+address_a[5] => ram_block3a0.PORTAADDR5
+address_a[5] => ram_block3a1.PORTAADDR5
+address_a[5] => ram_block3a2.PORTAADDR5
+address_a[5] => ram_block3a3.PORTAADDR5
+address_a[5] => ram_block3a4.PORTAADDR5
+address_a[5] => ram_block3a5.PORTAADDR5
+address_a[5] => ram_block3a6.PORTAADDR5
+address_a[5] => ram_block3a7.PORTAADDR5
+address_a[5] => ram_block3a8.PORTAADDR5
+address_a[5] => ram_block3a9.PORTAADDR5
+address_a[5] => ram_block3a10.PORTAADDR5
+address_a[5] => ram_block3a11.PORTAADDR5
+address_a[5] => ram_block3a12.PORTAADDR5
+address_a[5] => ram_block3a13.PORTAADDR5
+address_a[5] => ram_block3a14.PORTAADDR5
+address_a[5] => ram_block3a15.PORTAADDR5
+address_a[5] => ram_block3a16.PORTAADDR5
+address_a[5] => ram_block3a17.PORTAADDR5
+address_a[5] => ram_block3a18.PORTAADDR5
+address_a[5] => ram_block3a19.PORTAADDR5
+address_a[5] => ram_block3a20.PORTAADDR5
+address_a[5] => ram_block3a21.PORTAADDR5
+address_a[5] => ram_block3a22.PORTAADDR5
+address_a[5] => ram_block3a23.PORTAADDR5
+address_a[5] => ram_block3a24.PORTAADDR5
+address_a[5] => ram_block3a25.PORTAADDR5
+address_a[5] => ram_block3a26.PORTAADDR5
+address_a[5] => ram_block3a27.PORTAADDR5
+address_a[5] => ram_block3a28.PORTAADDR5
+address_a[5] => ram_block3a29.PORTAADDR5
+address_a[5] => ram_block3a30.PORTAADDR5
+address_a[5] => ram_block3a31.PORTAADDR5
+address_a[5] => ram_block3a32.PORTAADDR5
+address_a[5] => ram_block3a33.PORTAADDR5
+address_a[5] => ram_block3a34.PORTAADDR5
+address_a[5] => ram_block3a35.PORTAADDR5
+address_a[5] => ram_block3a36.PORTAADDR5
+address_a[5] => ram_block3a37.PORTAADDR5
+address_a[5] => ram_block3a38.PORTAADDR5
+address_a[5] => ram_block3a39.PORTAADDR5
+address_a[5] => ram_block3a40.PORTAADDR5
+address_a[5] => ram_block3a41.PORTAADDR5
+address_a[5] => ram_block3a42.PORTAADDR5
+address_a[5] => ram_block3a43.PORTAADDR5
+address_a[5] => ram_block3a44.PORTAADDR5
+address_a[5] => ram_block3a45.PORTAADDR5
+address_a[5] => ram_block3a46.PORTAADDR5
+address_a[5] => ram_block3a47.PORTAADDR5
+address_a[5] => ram_block3a48.PORTAADDR5
+address_a[5] => ram_block3a49.PORTAADDR5
+address_a[5] => ram_block3a50.PORTAADDR5
+address_a[5] => ram_block3a51.PORTAADDR5
+address_a[5] => ram_block3a52.PORTAADDR5
+address_a[5] => ram_block3a53.PORTAADDR5
+address_a[5] => ram_block3a54.PORTAADDR5
+address_a[5] => ram_block3a55.PORTAADDR5
+address_a[5] => ram_block3a56.PORTAADDR5
+address_a[5] => ram_block3a57.PORTAADDR5
+address_a[5] => ram_block3a58.PORTAADDR5
+address_a[5] => ram_block3a59.PORTAADDR5
+address_a[5] => ram_block3a60.PORTAADDR5
+address_a[5] => ram_block3a61.PORTAADDR5
+address_a[5] => ram_block3a62.PORTAADDR5
+address_a[5] => ram_block3a63.PORTAADDR5
+address_a[5] => ram_block3a64.PORTAADDR5
+address_a[5] => ram_block3a65.PORTAADDR5
+address_a[5] => ram_block3a66.PORTAADDR5
+address_a[5] => ram_block3a67.PORTAADDR5
+address_a[5] => ram_block3a68.PORTAADDR5
+address_a[5] => ram_block3a69.PORTAADDR5
+address_a[5] => ram_block3a70.PORTAADDR5
+address_a[5] => ram_block3a71.PORTAADDR5
+address_a[5] => ram_block3a72.PORTAADDR5
+address_a[5] => ram_block3a73.PORTAADDR5
+address_a[5] => ram_block3a74.PORTAADDR5
+address_a[5] => ram_block3a75.PORTAADDR5
+address_a[5] => ram_block3a76.PORTAADDR5
+address_a[5] => ram_block3a77.PORTAADDR5
+address_a[5] => ram_block3a78.PORTAADDR5
+address_a[5] => ram_block3a79.PORTAADDR5
+address_a[5] => ram_block3a80.PORTAADDR5
+address_a[5] => ram_block3a81.PORTAADDR5
+address_a[5] => ram_block3a82.PORTAADDR5
+address_a[5] => ram_block3a83.PORTAADDR5
+address_a[5] => ram_block3a84.PORTAADDR5
+address_a[5] => ram_block3a85.PORTAADDR5
+address_a[5] => ram_block3a86.PORTAADDR5
+address_a[5] => ram_block3a87.PORTAADDR5
+address_a[5] => ram_block3a88.PORTAADDR5
+address_a[5] => ram_block3a89.PORTAADDR5
+address_a[6] => ram_block3a0.PORTAADDR6
+address_a[6] => ram_block3a1.PORTAADDR6
+address_a[6] => ram_block3a2.PORTAADDR6
+address_a[6] => ram_block3a3.PORTAADDR6
+address_a[6] => ram_block3a4.PORTAADDR6
+address_a[6] => ram_block3a5.PORTAADDR6
+address_a[6] => ram_block3a6.PORTAADDR6
+address_a[6] => ram_block3a7.PORTAADDR6
+address_a[6] => ram_block3a8.PORTAADDR6
+address_a[6] => ram_block3a9.PORTAADDR6
+address_a[6] => ram_block3a10.PORTAADDR6
+address_a[6] => ram_block3a11.PORTAADDR6
+address_a[6] => ram_block3a12.PORTAADDR6
+address_a[6] => ram_block3a13.PORTAADDR6
+address_a[6] => ram_block3a14.PORTAADDR6
+address_a[6] => ram_block3a15.PORTAADDR6
+address_a[6] => ram_block3a16.PORTAADDR6
+address_a[6] => ram_block3a17.PORTAADDR6
+address_a[6] => ram_block3a18.PORTAADDR6
+address_a[6] => ram_block3a19.PORTAADDR6
+address_a[6] => ram_block3a20.PORTAADDR6
+address_a[6] => ram_block3a21.PORTAADDR6
+address_a[6] => ram_block3a22.PORTAADDR6
+address_a[6] => ram_block3a23.PORTAADDR6
+address_a[6] => ram_block3a24.PORTAADDR6
+address_a[6] => ram_block3a25.PORTAADDR6
+address_a[6] => ram_block3a26.PORTAADDR6
+address_a[6] => ram_block3a27.PORTAADDR6
+address_a[6] => ram_block3a28.PORTAADDR6
+address_a[6] => ram_block3a29.PORTAADDR6
+address_a[6] => ram_block3a30.PORTAADDR6
+address_a[6] => ram_block3a31.PORTAADDR6
+address_a[6] => ram_block3a32.PORTAADDR6
+address_a[6] => ram_block3a33.PORTAADDR6
+address_a[6] => ram_block3a34.PORTAADDR6
+address_a[6] => ram_block3a35.PORTAADDR6
+address_a[6] => ram_block3a36.PORTAADDR6
+address_a[6] => ram_block3a37.PORTAADDR6
+address_a[6] => ram_block3a38.PORTAADDR6
+address_a[6] => ram_block3a39.PORTAADDR6
+address_a[6] => ram_block3a40.PORTAADDR6
+address_a[6] => ram_block3a41.PORTAADDR6
+address_a[6] => ram_block3a42.PORTAADDR6
+address_a[6] => ram_block3a43.PORTAADDR6
+address_a[6] => ram_block3a44.PORTAADDR6
+address_a[6] => ram_block3a45.PORTAADDR6
+address_a[6] => ram_block3a46.PORTAADDR6
+address_a[6] => ram_block3a47.PORTAADDR6
+address_a[6] => ram_block3a48.PORTAADDR6
+address_a[6] => ram_block3a49.PORTAADDR6
+address_a[6] => ram_block3a50.PORTAADDR6
+address_a[6] => ram_block3a51.PORTAADDR6
+address_a[6] => ram_block3a52.PORTAADDR6
+address_a[6] => ram_block3a53.PORTAADDR6
+address_a[6] => ram_block3a54.PORTAADDR6
+address_a[6] => ram_block3a55.PORTAADDR6
+address_a[6] => ram_block3a56.PORTAADDR6
+address_a[6] => ram_block3a57.PORTAADDR6
+address_a[6] => ram_block3a58.PORTAADDR6
+address_a[6] => ram_block3a59.PORTAADDR6
+address_a[6] => ram_block3a60.PORTAADDR6
+address_a[6] => ram_block3a61.PORTAADDR6
+address_a[6] => ram_block3a62.PORTAADDR6
+address_a[6] => ram_block3a63.PORTAADDR6
+address_a[6] => ram_block3a64.PORTAADDR6
+address_a[6] => ram_block3a65.PORTAADDR6
+address_a[6] => ram_block3a66.PORTAADDR6
+address_a[6] => ram_block3a67.PORTAADDR6
+address_a[6] => ram_block3a68.PORTAADDR6
+address_a[6] => ram_block3a69.PORTAADDR6
+address_a[6] => ram_block3a70.PORTAADDR6
+address_a[6] => ram_block3a71.PORTAADDR6
+address_a[6] => ram_block3a72.PORTAADDR6
+address_a[6] => ram_block3a73.PORTAADDR6
+address_a[6] => ram_block3a74.PORTAADDR6
+address_a[6] => ram_block3a75.PORTAADDR6
+address_a[6] => ram_block3a76.PORTAADDR6
+address_a[6] => ram_block3a77.PORTAADDR6
+address_a[6] => ram_block3a78.PORTAADDR6
+address_a[6] => ram_block3a79.PORTAADDR6
+address_a[6] => ram_block3a80.PORTAADDR6
+address_a[6] => ram_block3a81.PORTAADDR6
+address_a[6] => ram_block3a82.PORTAADDR6
+address_a[6] => ram_block3a83.PORTAADDR6
+address_a[6] => ram_block3a84.PORTAADDR6
+address_a[6] => ram_block3a85.PORTAADDR6
+address_a[6] => ram_block3a86.PORTAADDR6
+address_a[6] => ram_block3a87.PORTAADDR6
+address_a[6] => ram_block3a88.PORTAADDR6
+address_a[6] => ram_block3a89.PORTAADDR6
+address_a[7] => ram_block3a0.PORTAADDR7
+address_a[7] => ram_block3a1.PORTAADDR7
+address_a[7] => ram_block3a2.PORTAADDR7
+address_a[7] => ram_block3a3.PORTAADDR7
+address_a[7] => ram_block3a4.PORTAADDR7
+address_a[7] => ram_block3a5.PORTAADDR7
+address_a[7] => ram_block3a6.PORTAADDR7
+address_a[7] => ram_block3a7.PORTAADDR7
+address_a[7] => ram_block3a8.PORTAADDR7
+address_a[7] => ram_block3a9.PORTAADDR7
+address_a[7] => ram_block3a10.PORTAADDR7
+address_a[7] => ram_block3a11.PORTAADDR7
+address_a[7] => ram_block3a12.PORTAADDR7
+address_a[7] => ram_block3a13.PORTAADDR7
+address_a[7] => ram_block3a14.PORTAADDR7
+address_a[7] => ram_block3a15.PORTAADDR7
+address_a[7] => ram_block3a16.PORTAADDR7
+address_a[7] => ram_block3a17.PORTAADDR7
+address_a[7] => ram_block3a18.PORTAADDR7
+address_a[7] => ram_block3a19.PORTAADDR7
+address_a[7] => ram_block3a20.PORTAADDR7
+address_a[7] => ram_block3a21.PORTAADDR7
+address_a[7] => ram_block3a22.PORTAADDR7
+address_a[7] => ram_block3a23.PORTAADDR7
+address_a[7] => ram_block3a24.PORTAADDR7
+address_a[7] => ram_block3a25.PORTAADDR7
+address_a[7] => ram_block3a26.PORTAADDR7
+address_a[7] => ram_block3a27.PORTAADDR7
+address_a[7] => ram_block3a28.PORTAADDR7
+address_a[7] => ram_block3a29.PORTAADDR7
+address_a[7] => ram_block3a30.PORTAADDR7
+address_a[7] => ram_block3a31.PORTAADDR7
+address_a[7] => ram_block3a32.PORTAADDR7
+address_a[7] => ram_block3a33.PORTAADDR7
+address_a[7] => ram_block3a34.PORTAADDR7
+address_a[7] => ram_block3a35.PORTAADDR7
+address_a[7] => ram_block3a36.PORTAADDR7
+address_a[7] => ram_block3a37.PORTAADDR7
+address_a[7] => ram_block3a38.PORTAADDR7
+address_a[7] => ram_block3a39.PORTAADDR7
+address_a[7] => ram_block3a40.PORTAADDR7
+address_a[7] => ram_block3a41.PORTAADDR7
+address_a[7] => ram_block3a42.PORTAADDR7
+address_a[7] => ram_block3a43.PORTAADDR7
+address_a[7] => ram_block3a44.PORTAADDR7
+address_a[7] => ram_block3a45.PORTAADDR7
+address_a[7] => ram_block3a46.PORTAADDR7
+address_a[7] => ram_block3a47.PORTAADDR7
+address_a[7] => ram_block3a48.PORTAADDR7
+address_a[7] => ram_block3a49.PORTAADDR7
+address_a[7] => ram_block3a50.PORTAADDR7
+address_a[7] => ram_block3a51.PORTAADDR7
+address_a[7] => ram_block3a52.PORTAADDR7
+address_a[7] => ram_block3a53.PORTAADDR7
+address_a[7] => ram_block3a54.PORTAADDR7
+address_a[7] => ram_block3a55.PORTAADDR7
+address_a[7] => ram_block3a56.PORTAADDR7
+address_a[7] => ram_block3a57.PORTAADDR7
+address_a[7] => ram_block3a58.PORTAADDR7
+address_a[7] => ram_block3a59.PORTAADDR7
+address_a[7] => ram_block3a60.PORTAADDR7
+address_a[7] => ram_block3a61.PORTAADDR7
+address_a[7] => ram_block3a62.PORTAADDR7
+address_a[7] => ram_block3a63.PORTAADDR7
+address_a[7] => ram_block3a64.PORTAADDR7
+address_a[7] => ram_block3a65.PORTAADDR7
+address_a[7] => ram_block3a66.PORTAADDR7
+address_a[7] => ram_block3a67.PORTAADDR7
+address_a[7] => ram_block3a68.PORTAADDR7
+address_a[7] => ram_block3a69.PORTAADDR7
+address_a[7] => ram_block3a70.PORTAADDR7
+address_a[7] => ram_block3a71.PORTAADDR7
+address_a[7] => ram_block3a72.PORTAADDR7
+address_a[7] => ram_block3a73.PORTAADDR7
+address_a[7] => ram_block3a74.PORTAADDR7
+address_a[7] => ram_block3a75.PORTAADDR7
+address_a[7] => ram_block3a76.PORTAADDR7
+address_a[7] => ram_block3a77.PORTAADDR7
+address_a[7] => ram_block3a78.PORTAADDR7
+address_a[7] => ram_block3a79.PORTAADDR7
+address_a[7] => ram_block3a80.PORTAADDR7
+address_a[7] => ram_block3a81.PORTAADDR7
+address_a[7] => ram_block3a82.PORTAADDR7
+address_a[7] => ram_block3a83.PORTAADDR7
+address_a[7] => ram_block3a84.PORTAADDR7
+address_a[7] => ram_block3a85.PORTAADDR7
+address_a[7] => ram_block3a86.PORTAADDR7
+address_a[7] => ram_block3a87.PORTAADDR7
+address_a[7] => ram_block3a88.PORTAADDR7
+address_a[7] => ram_block3a89.PORTAADDR7
+address_a[8] => ram_block3a0.PORTAADDR8
+address_a[8] => ram_block3a1.PORTAADDR8
+address_a[8] => ram_block3a2.PORTAADDR8
+address_a[8] => ram_block3a3.PORTAADDR8
+address_a[8] => ram_block3a4.PORTAADDR8
+address_a[8] => ram_block3a5.PORTAADDR8
+address_a[8] => ram_block3a6.PORTAADDR8
+address_a[8] => ram_block3a7.PORTAADDR8
+address_a[8] => ram_block3a8.PORTAADDR8
+address_a[8] => ram_block3a9.PORTAADDR8
+address_a[8] => ram_block3a10.PORTAADDR8
+address_a[8] => ram_block3a11.PORTAADDR8
+address_a[8] => ram_block3a12.PORTAADDR8
+address_a[8] => ram_block3a13.PORTAADDR8
+address_a[8] => ram_block3a14.PORTAADDR8
+address_a[8] => ram_block3a15.PORTAADDR8
+address_a[8] => ram_block3a16.PORTAADDR8
+address_a[8] => ram_block3a17.PORTAADDR8
+address_a[8] => ram_block3a18.PORTAADDR8
+address_a[8] => ram_block3a19.PORTAADDR8
+address_a[8] => ram_block3a20.PORTAADDR8
+address_a[8] => ram_block3a21.PORTAADDR8
+address_a[8] => ram_block3a22.PORTAADDR8
+address_a[8] => ram_block3a23.PORTAADDR8
+address_a[8] => ram_block3a24.PORTAADDR8
+address_a[8] => ram_block3a25.PORTAADDR8
+address_a[8] => ram_block3a26.PORTAADDR8
+address_a[8] => ram_block3a27.PORTAADDR8
+address_a[8] => ram_block3a28.PORTAADDR8
+address_a[8] => ram_block3a29.PORTAADDR8
+address_a[8] => ram_block3a30.PORTAADDR8
+address_a[8] => ram_block3a31.PORTAADDR8
+address_a[8] => ram_block3a32.PORTAADDR8
+address_a[8] => ram_block3a33.PORTAADDR8
+address_a[8] => ram_block3a34.PORTAADDR8
+address_a[8] => ram_block3a35.PORTAADDR8
+address_a[8] => ram_block3a36.PORTAADDR8
+address_a[8] => ram_block3a37.PORTAADDR8
+address_a[8] => ram_block3a38.PORTAADDR8
+address_a[8] => ram_block3a39.PORTAADDR8
+address_a[8] => ram_block3a40.PORTAADDR8
+address_a[8] => ram_block3a41.PORTAADDR8
+address_a[8] => ram_block3a42.PORTAADDR8
+address_a[8] => ram_block3a43.PORTAADDR8
+address_a[8] => ram_block3a44.PORTAADDR8
+address_a[8] => ram_block3a45.PORTAADDR8
+address_a[8] => ram_block3a46.PORTAADDR8
+address_a[8] => ram_block3a47.PORTAADDR8
+address_a[8] => ram_block3a48.PORTAADDR8
+address_a[8] => ram_block3a49.PORTAADDR8
+address_a[8] => ram_block3a50.PORTAADDR8
+address_a[8] => ram_block3a51.PORTAADDR8
+address_a[8] => ram_block3a52.PORTAADDR8
+address_a[8] => ram_block3a53.PORTAADDR8
+address_a[8] => ram_block3a54.PORTAADDR8
+address_a[8] => ram_block3a55.PORTAADDR8
+address_a[8] => ram_block3a56.PORTAADDR8
+address_a[8] => ram_block3a57.PORTAADDR8
+address_a[8] => ram_block3a58.PORTAADDR8
+address_a[8] => ram_block3a59.PORTAADDR8
+address_a[8] => ram_block3a60.PORTAADDR8
+address_a[8] => ram_block3a61.PORTAADDR8
+address_a[8] => ram_block3a62.PORTAADDR8
+address_a[8] => ram_block3a63.PORTAADDR8
+address_a[8] => ram_block3a64.PORTAADDR8
+address_a[8] => ram_block3a65.PORTAADDR8
+address_a[8] => ram_block3a66.PORTAADDR8
+address_a[8] => ram_block3a67.PORTAADDR8
+address_a[8] => ram_block3a68.PORTAADDR8
+address_a[8] => ram_block3a69.PORTAADDR8
+address_a[8] => ram_block3a70.PORTAADDR8
+address_a[8] => ram_block3a71.PORTAADDR8
+address_a[8] => ram_block3a72.PORTAADDR8
+address_a[8] => ram_block3a73.PORTAADDR8
+address_a[8] => ram_block3a74.PORTAADDR8
+address_a[8] => ram_block3a75.PORTAADDR8
+address_a[8] => ram_block3a76.PORTAADDR8
+address_a[8] => ram_block3a77.PORTAADDR8
+address_a[8] => ram_block3a78.PORTAADDR8
+address_a[8] => ram_block3a79.PORTAADDR8
+address_a[8] => ram_block3a80.PORTAADDR8
+address_a[8] => ram_block3a81.PORTAADDR8
+address_a[8] => ram_block3a82.PORTAADDR8
+address_a[8] => ram_block3a83.PORTAADDR8
+address_a[8] => ram_block3a84.PORTAADDR8
+address_a[8] => ram_block3a85.PORTAADDR8
+address_a[8] => ram_block3a86.PORTAADDR8
+address_a[8] => ram_block3a87.PORTAADDR8
+address_a[8] => ram_block3a88.PORTAADDR8
+address_a[8] => ram_block3a89.PORTAADDR8
+address_a[9] => ram_block3a0.PORTAADDR9
+address_a[9] => ram_block3a1.PORTAADDR9
+address_a[9] => ram_block3a2.PORTAADDR9
+address_a[9] => ram_block3a3.PORTAADDR9
+address_a[9] => ram_block3a4.PORTAADDR9
+address_a[9] => ram_block3a5.PORTAADDR9
+address_a[9] => ram_block3a6.PORTAADDR9
+address_a[9] => ram_block3a7.PORTAADDR9
+address_a[9] => ram_block3a8.PORTAADDR9
+address_a[9] => ram_block3a9.PORTAADDR9
+address_a[9] => ram_block3a10.PORTAADDR9
+address_a[9] => ram_block3a11.PORTAADDR9
+address_a[9] => ram_block3a12.PORTAADDR9
+address_a[9] => ram_block3a13.PORTAADDR9
+address_a[9] => ram_block3a14.PORTAADDR9
+address_a[9] => ram_block3a15.PORTAADDR9
+address_a[9] => ram_block3a16.PORTAADDR9
+address_a[9] => ram_block3a17.PORTAADDR9
+address_a[9] => ram_block3a18.PORTAADDR9
+address_a[9] => ram_block3a19.PORTAADDR9
+address_a[9] => ram_block3a20.PORTAADDR9
+address_a[9] => ram_block3a21.PORTAADDR9
+address_a[9] => ram_block3a22.PORTAADDR9
+address_a[9] => ram_block3a23.PORTAADDR9
+address_a[9] => ram_block3a24.PORTAADDR9
+address_a[9] => ram_block3a25.PORTAADDR9
+address_a[9] => ram_block3a26.PORTAADDR9
+address_a[9] => ram_block3a27.PORTAADDR9
+address_a[9] => ram_block3a28.PORTAADDR9
+address_a[9] => ram_block3a29.PORTAADDR9
+address_a[9] => ram_block3a30.PORTAADDR9
+address_a[9] => ram_block3a31.PORTAADDR9
+address_a[9] => ram_block3a32.PORTAADDR9
+address_a[9] => ram_block3a33.PORTAADDR9
+address_a[9] => ram_block3a34.PORTAADDR9
+address_a[9] => ram_block3a35.PORTAADDR9
+address_a[9] => ram_block3a36.PORTAADDR9
+address_a[9] => ram_block3a37.PORTAADDR9
+address_a[9] => ram_block3a38.PORTAADDR9
+address_a[9] => ram_block3a39.PORTAADDR9
+address_a[9] => ram_block3a40.PORTAADDR9
+address_a[9] => ram_block3a41.PORTAADDR9
+address_a[9] => ram_block3a42.PORTAADDR9
+address_a[9] => ram_block3a43.PORTAADDR9
+address_a[9] => ram_block3a44.PORTAADDR9
+address_a[9] => ram_block3a45.PORTAADDR9
+address_a[9] => ram_block3a46.PORTAADDR9
+address_a[9] => ram_block3a47.PORTAADDR9
+address_a[9] => ram_block3a48.PORTAADDR9
+address_a[9] => ram_block3a49.PORTAADDR9
+address_a[9] => ram_block3a50.PORTAADDR9
+address_a[9] => ram_block3a51.PORTAADDR9
+address_a[9] => ram_block3a52.PORTAADDR9
+address_a[9] => ram_block3a53.PORTAADDR9
+address_a[9] => ram_block3a54.PORTAADDR9
+address_a[9] => ram_block3a55.PORTAADDR9
+address_a[9] => ram_block3a56.PORTAADDR9
+address_a[9] => ram_block3a57.PORTAADDR9
+address_a[9] => ram_block3a58.PORTAADDR9
+address_a[9] => ram_block3a59.PORTAADDR9
+address_a[9] => ram_block3a60.PORTAADDR9
+address_a[9] => ram_block3a61.PORTAADDR9
+address_a[9] => ram_block3a62.PORTAADDR9
+address_a[9] => ram_block3a63.PORTAADDR9
+address_a[9] => ram_block3a64.PORTAADDR9
+address_a[9] => ram_block3a65.PORTAADDR9
+address_a[9] => ram_block3a66.PORTAADDR9
+address_a[9] => ram_block3a67.PORTAADDR9
+address_a[9] => ram_block3a68.PORTAADDR9
+address_a[9] => ram_block3a69.PORTAADDR9
+address_a[9] => ram_block3a70.PORTAADDR9
+address_a[9] => ram_block3a71.PORTAADDR9
+address_a[9] => ram_block3a72.PORTAADDR9
+address_a[9] => ram_block3a73.PORTAADDR9
+address_a[9] => ram_block3a74.PORTAADDR9
+address_a[9] => ram_block3a75.PORTAADDR9
+address_a[9] => ram_block3a76.PORTAADDR9
+address_a[9] => ram_block3a77.PORTAADDR9
+address_a[9] => ram_block3a78.PORTAADDR9
+address_a[9] => ram_block3a79.PORTAADDR9
+address_a[9] => ram_block3a80.PORTAADDR9
+address_a[9] => ram_block3a81.PORTAADDR9
+address_a[9] => ram_block3a82.PORTAADDR9
+address_a[9] => ram_block3a83.PORTAADDR9
+address_a[9] => ram_block3a84.PORTAADDR9
+address_a[9] => ram_block3a85.PORTAADDR9
+address_a[9] => ram_block3a86.PORTAADDR9
+address_a[9] => ram_block3a87.PORTAADDR9
+address_a[9] => ram_block3a88.PORTAADDR9
+address_a[9] => ram_block3a89.PORTAADDR9
+address_b[0] => ram_block3a0.PORTBADDR
+address_b[0] => ram_block3a1.PORTBADDR
+address_b[0] => ram_block3a2.PORTBADDR
+address_b[0] => ram_block3a3.PORTBADDR
+address_b[0] => ram_block3a4.PORTBADDR
+address_b[0] => ram_block3a5.PORTBADDR
+address_b[0] => ram_block3a6.PORTBADDR
+address_b[0] => ram_block3a7.PORTBADDR
+address_b[0] => ram_block3a8.PORTBADDR
+address_b[0] => ram_block3a9.PORTBADDR
+address_b[0] => ram_block3a10.PORTBADDR
+address_b[0] => ram_block3a11.PORTBADDR
+address_b[0] => ram_block3a12.PORTBADDR
+address_b[0] => ram_block3a13.PORTBADDR
+address_b[0] => ram_block3a14.PORTBADDR
+address_b[0] => ram_block3a15.PORTBADDR
+address_b[0] => ram_block3a16.PORTBADDR
+address_b[0] => ram_block3a17.PORTBADDR
+address_b[0] => ram_block3a18.PORTBADDR
+address_b[0] => ram_block3a19.PORTBADDR
+address_b[0] => ram_block3a20.PORTBADDR
+address_b[0] => ram_block3a21.PORTBADDR
+address_b[0] => ram_block3a22.PORTBADDR
+address_b[0] => ram_block3a23.PORTBADDR
+address_b[0] => ram_block3a24.PORTBADDR
+address_b[0] => ram_block3a25.PORTBADDR
+address_b[0] => ram_block3a26.PORTBADDR
+address_b[0] => ram_block3a27.PORTBADDR
+address_b[0] => ram_block3a28.PORTBADDR
+address_b[0] => ram_block3a29.PORTBADDR
+address_b[0] => ram_block3a30.PORTBADDR
+address_b[0] => ram_block3a31.PORTBADDR
+address_b[0] => ram_block3a32.PORTBADDR
+address_b[0] => ram_block3a33.PORTBADDR
+address_b[0] => ram_block3a34.PORTBADDR
+address_b[0] => ram_block3a35.PORTBADDR
+address_b[0] => ram_block3a36.PORTBADDR
+address_b[0] => ram_block3a37.PORTBADDR
+address_b[0] => ram_block3a38.PORTBADDR
+address_b[0] => ram_block3a39.PORTBADDR
+address_b[0] => ram_block3a40.PORTBADDR
+address_b[0] => ram_block3a41.PORTBADDR
+address_b[0] => ram_block3a42.PORTBADDR
+address_b[0] => ram_block3a43.PORTBADDR
+address_b[0] => ram_block3a44.PORTBADDR
+address_b[0] => ram_block3a45.PORTBADDR
+address_b[0] => ram_block3a46.PORTBADDR
+address_b[0] => ram_block3a47.PORTBADDR
+address_b[0] => ram_block3a48.PORTBADDR
+address_b[0] => ram_block3a49.PORTBADDR
+address_b[0] => ram_block3a50.PORTBADDR
+address_b[0] => ram_block3a51.PORTBADDR
+address_b[0] => ram_block3a52.PORTBADDR
+address_b[0] => ram_block3a53.PORTBADDR
+address_b[0] => ram_block3a54.PORTBADDR
+address_b[0] => ram_block3a55.PORTBADDR
+address_b[0] => ram_block3a56.PORTBADDR
+address_b[0] => ram_block3a57.PORTBADDR
+address_b[0] => ram_block3a58.PORTBADDR
+address_b[0] => ram_block3a59.PORTBADDR
+address_b[0] => ram_block3a60.PORTBADDR
+address_b[0] => ram_block3a61.PORTBADDR
+address_b[0] => ram_block3a62.PORTBADDR
+address_b[0] => ram_block3a63.PORTBADDR
+address_b[0] => ram_block3a64.PORTBADDR
+address_b[0] => ram_block3a65.PORTBADDR
+address_b[0] => ram_block3a66.PORTBADDR
+address_b[0] => ram_block3a67.PORTBADDR
+address_b[0] => ram_block3a68.PORTBADDR
+address_b[0] => ram_block3a69.PORTBADDR
+address_b[0] => ram_block3a70.PORTBADDR
+address_b[0] => ram_block3a71.PORTBADDR
+address_b[0] => ram_block3a72.PORTBADDR
+address_b[0] => ram_block3a73.PORTBADDR
+address_b[0] => ram_block3a74.PORTBADDR
+address_b[0] => ram_block3a75.PORTBADDR
+address_b[0] => ram_block3a76.PORTBADDR
+address_b[0] => ram_block3a77.PORTBADDR
+address_b[0] => ram_block3a78.PORTBADDR
+address_b[0] => ram_block3a79.PORTBADDR
+address_b[0] => ram_block3a80.PORTBADDR
+address_b[0] => ram_block3a81.PORTBADDR
+address_b[0] => ram_block3a82.PORTBADDR
+address_b[0] => ram_block3a83.PORTBADDR
+address_b[0] => ram_block3a84.PORTBADDR
+address_b[0] => ram_block3a85.PORTBADDR
+address_b[0] => ram_block3a86.PORTBADDR
+address_b[0] => ram_block3a87.PORTBADDR
+address_b[0] => ram_block3a88.PORTBADDR
+address_b[0] => ram_block3a89.PORTBADDR
+address_b[1] => ram_block3a0.PORTBADDR1
+address_b[1] => ram_block3a1.PORTBADDR1
+address_b[1] => ram_block3a2.PORTBADDR1
+address_b[1] => ram_block3a3.PORTBADDR1
+address_b[1] => ram_block3a4.PORTBADDR1
+address_b[1] => ram_block3a5.PORTBADDR1
+address_b[1] => ram_block3a6.PORTBADDR1
+address_b[1] => ram_block3a7.PORTBADDR1
+address_b[1] => ram_block3a8.PORTBADDR1
+address_b[1] => ram_block3a9.PORTBADDR1
+address_b[1] => ram_block3a10.PORTBADDR1
+address_b[1] => ram_block3a11.PORTBADDR1
+address_b[1] => ram_block3a12.PORTBADDR1
+address_b[1] => ram_block3a13.PORTBADDR1
+address_b[1] => ram_block3a14.PORTBADDR1
+address_b[1] => ram_block3a15.PORTBADDR1
+address_b[1] => ram_block3a16.PORTBADDR1
+address_b[1] => ram_block3a17.PORTBADDR1
+address_b[1] => ram_block3a18.PORTBADDR1
+address_b[1] => ram_block3a19.PORTBADDR1
+address_b[1] => ram_block3a20.PORTBADDR1
+address_b[1] => ram_block3a21.PORTBADDR1
+address_b[1] => ram_block3a22.PORTBADDR1
+address_b[1] => ram_block3a23.PORTBADDR1
+address_b[1] => ram_block3a24.PORTBADDR1
+address_b[1] => ram_block3a25.PORTBADDR1
+address_b[1] => ram_block3a26.PORTBADDR1
+address_b[1] => ram_block3a27.PORTBADDR1
+address_b[1] => ram_block3a28.PORTBADDR1
+address_b[1] => ram_block3a29.PORTBADDR1
+address_b[1] => ram_block3a30.PORTBADDR1
+address_b[1] => ram_block3a31.PORTBADDR1
+address_b[1] => ram_block3a32.PORTBADDR1
+address_b[1] => ram_block3a33.PORTBADDR1
+address_b[1] => ram_block3a34.PORTBADDR1
+address_b[1] => ram_block3a35.PORTBADDR1
+address_b[1] => ram_block3a36.PORTBADDR1
+address_b[1] => ram_block3a37.PORTBADDR1
+address_b[1] => ram_block3a38.PORTBADDR1
+address_b[1] => ram_block3a39.PORTBADDR1
+address_b[1] => ram_block3a40.PORTBADDR1
+address_b[1] => ram_block3a41.PORTBADDR1
+address_b[1] => ram_block3a42.PORTBADDR1
+address_b[1] => ram_block3a43.PORTBADDR1
+address_b[1] => ram_block3a44.PORTBADDR1
+address_b[1] => ram_block3a45.PORTBADDR1
+address_b[1] => ram_block3a46.PORTBADDR1
+address_b[1] => ram_block3a47.PORTBADDR1
+address_b[1] => ram_block3a48.PORTBADDR1
+address_b[1] => ram_block3a49.PORTBADDR1
+address_b[1] => ram_block3a50.PORTBADDR1
+address_b[1] => ram_block3a51.PORTBADDR1
+address_b[1] => ram_block3a52.PORTBADDR1
+address_b[1] => ram_block3a53.PORTBADDR1
+address_b[1] => ram_block3a54.PORTBADDR1
+address_b[1] => ram_block3a55.PORTBADDR1
+address_b[1] => ram_block3a56.PORTBADDR1
+address_b[1] => ram_block3a57.PORTBADDR1
+address_b[1] => ram_block3a58.PORTBADDR1
+address_b[1] => ram_block3a59.PORTBADDR1
+address_b[1] => ram_block3a60.PORTBADDR1
+address_b[1] => ram_block3a61.PORTBADDR1
+address_b[1] => ram_block3a62.PORTBADDR1
+address_b[1] => ram_block3a63.PORTBADDR1
+address_b[1] => ram_block3a64.PORTBADDR1
+address_b[1] => ram_block3a65.PORTBADDR1
+address_b[1] => ram_block3a66.PORTBADDR1
+address_b[1] => ram_block3a67.PORTBADDR1
+address_b[1] => ram_block3a68.PORTBADDR1
+address_b[1] => ram_block3a69.PORTBADDR1
+address_b[1] => ram_block3a70.PORTBADDR1
+address_b[1] => ram_block3a71.PORTBADDR1
+address_b[1] => ram_block3a72.PORTBADDR1
+address_b[1] => ram_block3a73.PORTBADDR1
+address_b[1] => ram_block3a74.PORTBADDR1
+address_b[1] => ram_block3a75.PORTBADDR1
+address_b[1] => ram_block3a76.PORTBADDR1
+address_b[1] => ram_block3a77.PORTBADDR1
+address_b[1] => ram_block3a78.PORTBADDR1
+address_b[1] => ram_block3a79.PORTBADDR1
+address_b[1] => ram_block3a80.PORTBADDR1
+address_b[1] => ram_block3a81.PORTBADDR1
+address_b[1] => ram_block3a82.PORTBADDR1
+address_b[1] => ram_block3a83.PORTBADDR1
+address_b[1] => ram_block3a84.PORTBADDR1
+address_b[1] => ram_block3a85.PORTBADDR1
+address_b[1] => ram_block3a86.PORTBADDR1
+address_b[1] => ram_block3a87.PORTBADDR1
+address_b[1] => ram_block3a88.PORTBADDR1
+address_b[1] => ram_block3a89.PORTBADDR1
+address_b[2] => ram_block3a0.PORTBADDR2
+address_b[2] => ram_block3a1.PORTBADDR2
+address_b[2] => ram_block3a2.PORTBADDR2
+address_b[2] => ram_block3a3.PORTBADDR2
+address_b[2] => ram_block3a4.PORTBADDR2
+address_b[2] => ram_block3a5.PORTBADDR2
+address_b[2] => ram_block3a6.PORTBADDR2
+address_b[2] => ram_block3a7.PORTBADDR2
+address_b[2] => ram_block3a8.PORTBADDR2
+address_b[2] => ram_block3a9.PORTBADDR2
+address_b[2] => ram_block3a10.PORTBADDR2
+address_b[2] => ram_block3a11.PORTBADDR2
+address_b[2] => ram_block3a12.PORTBADDR2
+address_b[2] => ram_block3a13.PORTBADDR2
+address_b[2] => ram_block3a14.PORTBADDR2
+address_b[2] => ram_block3a15.PORTBADDR2
+address_b[2] => ram_block3a16.PORTBADDR2
+address_b[2] => ram_block3a17.PORTBADDR2
+address_b[2] => ram_block3a18.PORTBADDR2
+address_b[2] => ram_block3a19.PORTBADDR2
+address_b[2] => ram_block3a20.PORTBADDR2
+address_b[2] => ram_block3a21.PORTBADDR2
+address_b[2] => ram_block3a22.PORTBADDR2
+address_b[2] => ram_block3a23.PORTBADDR2
+address_b[2] => ram_block3a24.PORTBADDR2
+address_b[2] => ram_block3a25.PORTBADDR2
+address_b[2] => ram_block3a26.PORTBADDR2
+address_b[2] => ram_block3a27.PORTBADDR2
+address_b[2] => ram_block3a28.PORTBADDR2
+address_b[2] => ram_block3a29.PORTBADDR2
+address_b[2] => ram_block3a30.PORTBADDR2
+address_b[2] => ram_block3a31.PORTBADDR2
+address_b[2] => ram_block3a32.PORTBADDR2
+address_b[2] => ram_block3a33.PORTBADDR2
+address_b[2] => ram_block3a34.PORTBADDR2
+address_b[2] => ram_block3a35.PORTBADDR2
+address_b[2] => ram_block3a36.PORTBADDR2
+address_b[2] => ram_block3a37.PORTBADDR2
+address_b[2] => ram_block3a38.PORTBADDR2
+address_b[2] => ram_block3a39.PORTBADDR2
+address_b[2] => ram_block3a40.PORTBADDR2
+address_b[2] => ram_block3a41.PORTBADDR2
+address_b[2] => ram_block3a42.PORTBADDR2
+address_b[2] => ram_block3a43.PORTBADDR2
+address_b[2] => ram_block3a44.PORTBADDR2
+address_b[2] => ram_block3a45.PORTBADDR2
+address_b[2] => ram_block3a46.PORTBADDR2
+address_b[2] => ram_block3a47.PORTBADDR2
+address_b[2] => ram_block3a48.PORTBADDR2
+address_b[2] => ram_block3a49.PORTBADDR2
+address_b[2] => ram_block3a50.PORTBADDR2
+address_b[2] => ram_block3a51.PORTBADDR2
+address_b[2] => ram_block3a52.PORTBADDR2
+address_b[2] => ram_block3a53.PORTBADDR2
+address_b[2] => ram_block3a54.PORTBADDR2
+address_b[2] => ram_block3a55.PORTBADDR2
+address_b[2] => ram_block3a56.PORTBADDR2
+address_b[2] => ram_block3a57.PORTBADDR2
+address_b[2] => ram_block3a58.PORTBADDR2
+address_b[2] => ram_block3a59.PORTBADDR2
+address_b[2] => ram_block3a60.PORTBADDR2
+address_b[2] => ram_block3a61.PORTBADDR2
+address_b[2] => ram_block3a62.PORTBADDR2
+address_b[2] => ram_block3a63.PORTBADDR2
+address_b[2] => ram_block3a64.PORTBADDR2
+address_b[2] => ram_block3a65.PORTBADDR2
+address_b[2] => ram_block3a66.PORTBADDR2
+address_b[2] => ram_block3a67.PORTBADDR2
+address_b[2] => ram_block3a68.PORTBADDR2
+address_b[2] => ram_block3a69.PORTBADDR2
+address_b[2] => ram_block3a70.PORTBADDR2
+address_b[2] => ram_block3a71.PORTBADDR2
+address_b[2] => ram_block3a72.PORTBADDR2
+address_b[2] => ram_block3a73.PORTBADDR2
+address_b[2] => ram_block3a74.PORTBADDR2
+address_b[2] => ram_block3a75.PORTBADDR2
+address_b[2] => ram_block3a76.PORTBADDR2
+address_b[2] => ram_block3a77.PORTBADDR2
+address_b[2] => ram_block3a78.PORTBADDR2
+address_b[2] => ram_block3a79.PORTBADDR2
+address_b[2] => ram_block3a80.PORTBADDR2
+address_b[2] => ram_block3a81.PORTBADDR2
+address_b[2] => ram_block3a82.PORTBADDR2
+address_b[2] => ram_block3a83.PORTBADDR2
+address_b[2] => ram_block3a84.PORTBADDR2
+address_b[2] => ram_block3a85.PORTBADDR2
+address_b[2] => ram_block3a86.PORTBADDR2
+address_b[2] => ram_block3a87.PORTBADDR2
+address_b[2] => ram_block3a88.PORTBADDR2
+address_b[2] => ram_block3a89.PORTBADDR2
+address_b[3] => ram_block3a0.PORTBADDR3
+address_b[3] => ram_block3a1.PORTBADDR3
+address_b[3] => ram_block3a2.PORTBADDR3
+address_b[3] => ram_block3a3.PORTBADDR3
+address_b[3] => ram_block3a4.PORTBADDR3
+address_b[3] => ram_block3a5.PORTBADDR3
+address_b[3] => ram_block3a6.PORTBADDR3
+address_b[3] => ram_block3a7.PORTBADDR3
+address_b[3] => ram_block3a8.PORTBADDR3
+address_b[3] => ram_block3a9.PORTBADDR3
+address_b[3] => ram_block3a10.PORTBADDR3
+address_b[3] => ram_block3a11.PORTBADDR3
+address_b[3] => ram_block3a12.PORTBADDR3
+address_b[3] => ram_block3a13.PORTBADDR3
+address_b[3] => ram_block3a14.PORTBADDR3
+address_b[3] => ram_block3a15.PORTBADDR3
+address_b[3] => ram_block3a16.PORTBADDR3
+address_b[3] => ram_block3a17.PORTBADDR3
+address_b[3] => ram_block3a18.PORTBADDR3
+address_b[3] => ram_block3a19.PORTBADDR3
+address_b[3] => ram_block3a20.PORTBADDR3
+address_b[3] => ram_block3a21.PORTBADDR3
+address_b[3] => ram_block3a22.PORTBADDR3
+address_b[3] => ram_block3a23.PORTBADDR3
+address_b[3] => ram_block3a24.PORTBADDR3
+address_b[3] => ram_block3a25.PORTBADDR3
+address_b[3] => ram_block3a26.PORTBADDR3
+address_b[3] => ram_block3a27.PORTBADDR3
+address_b[3] => ram_block3a28.PORTBADDR3
+address_b[3] => ram_block3a29.PORTBADDR3
+address_b[3] => ram_block3a30.PORTBADDR3
+address_b[3] => ram_block3a31.PORTBADDR3
+address_b[3] => ram_block3a32.PORTBADDR3
+address_b[3] => ram_block3a33.PORTBADDR3
+address_b[3] => ram_block3a34.PORTBADDR3
+address_b[3] => ram_block3a35.PORTBADDR3
+address_b[3] => ram_block3a36.PORTBADDR3
+address_b[3] => ram_block3a37.PORTBADDR3
+address_b[3] => ram_block3a38.PORTBADDR3
+address_b[3] => ram_block3a39.PORTBADDR3
+address_b[3] => ram_block3a40.PORTBADDR3
+address_b[3] => ram_block3a41.PORTBADDR3
+address_b[3] => ram_block3a42.PORTBADDR3
+address_b[3] => ram_block3a43.PORTBADDR3
+address_b[3] => ram_block3a44.PORTBADDR3
+address_b[3] => ram_block3a45.PORTBADDR3
+address_b[3] => ram_block3a46.PORTBADDR3
+address_b[3] => ram_block3a47.PORTBADDR3
+address_b[3] => ram_block3a48.PORTBADDR3
+address_b[3] => ram_block3a49.PORTBADDR3
+address_b[3] => ram_block3a50.PORTBADDR3
+address_b[3] => ram_block3a51.PORTBADDR3
+address_b[3] => ram_block3a52.PORTBADDR3
+address_b[3] => ram_block3a53.PORTBADDR3
+address_b[3] => ram_block3a54.PORTBADDR3
+address_b[3] => ram_block3a55.PORTBADDR3
+address_b[3] => ram_block3a56.PORTBADDR3
+address_b[3] => ram_block3a57.PORTBADDR3
+address_b[3] => ram_block3a58.PORTBADDR3
+address_b[3] => ram_block3a59.PORTBADDR3
+address_b[3] => ram_block3a60.PORTBADDR3
+address_b[3] => ram_block3a61.PORTBADDR3
+address_b[3] => ram_block3a62.PORTBADDR3
+address_b[3] => ram_block3a63.PORTBADDR3
+address_b[3] => ram_block3a64.PORTBADDR3
+address_b[3] => ram_block3a65.PORTBADDR3
+address_b[3] => ram_block3a66.PORTBADDR3
+address_b[3] => ram_block3a67.PORTBADDR3
+address_b[3] => ram_block3a68.PORTBADDR3
+address_b[3] => ram_block3a69.PORTBADDR3
+address_b[3] => ram_block3a70.PORTBADDR3
+address_b[3] => ram_block3a71.PORTBADDR3
+address_b[3] => ram_block3a72.PORTBADDR3
+address_b[3] => ram_block3a73.PORTBADDR3
+address_b[3] => ram_block3a74.PORTBADDR3
+address_b[3] => ram_block3a75.PORTBADDR3
+address_b[3] => ram_block3a76.PORTBADDR3
+address_b[3] => ram_block3a77.PORTBADDR3
+address_b[3] => ram_block3a78.PORTBADDR3
+address_b[3] => ram_block3a79.PORTBADDR3
+address_b[3] => ram_block3a80.PORTBADDR3
+address_b[3] => ram_block3a81.PORTBADDR3
+address_b[3] => ram_block3a82.PORTBADDR3
+address_b[3] => ram_block3a83.PORTBADDR3
+address_b[3] => ram_block3a84.PORTBADDR3
+address_b[3] => ram_block3a85.PORTBADDR3
+address_b[3] => ram_block3a86.PORTBADDR3
+address_b[3] => ram_block3a87.PORTBADDR3
+address_b[3] => ram_block3a88.PORTBADDR3
+address_b[3] => ram_block3a89.PORTBADDR3
+address_b[4] => ram_block3a0.PORTBADDR4
+address_b[4] => ram_block3a1.PORTBADDR4
+address_b[4] => ram_block3a2.PORTBADDR4
+address_b[4] => ram_block3a3.PORTBADDR4
+address_b[4] => ram_block3a4.PORTBADDR4
+address_b[4] => ram_block3a5.PORTBADDR4
+address_b[4] => ram_block3a6.PORTBADDR4
+address_b[4] => ram_block3a7.PORTBADDR4
+address_b[4] => ram_block3a8.PORTBADDR4
+address_b[4] => ram_block3a9.PORTBADDR4
+address_b[4] => ram_block3a10.PORTBADDR4
+address_b[4] => ram_block3a11.PORTBADDR4
+address_b[4] => ram_block3a12.PORTBADDR4
+address_b[4] => ram_block3a13.PORTBADDR4
+address_b[4] => ram_block3a14.PORTBADDR4
+address_b[4] => ram_block3a15.PORTBADDR4
+address_b[4] => ram_block3a16.PORTBADDR4
+address_b[4] => ram_block3a17.PORTBADDR4
+address_b[4] => ram_block3a18.PORTBADDR4
+address_b[4] => ram_block3a19.PORTBADDR4
+address_b[4] => ram_block3a20.PORTBADDR4
+address_b[4] => ram_block3a21.PORTBADDR4
+address_b[4] => ram_block3a22.PORTBADDR4
+address_b[4] => ram_block3a23.PORTBADDR4
+address_b[4] => ram_block3a24.PORTBADDR4
+address_b[4] => ram_block3a25.PORTBADDR4
+address_b[4] => ram_block3a26.PORTBADDR4
+address_b[4] => ram_block3a27.PORTBADDR4
+address_b[4] => ram_block3a28.PORTBADDR4
+address_b[4] => ram_block3a29.PORTBADDR4
+address_b[4] => ram_block3a30.PORTBADDR4
+address_b[4] => ram_block3a31.PORTBADDR4
+address_b[4] => ram_block3a32.PORTBADDR4
+address_b[4] => ram_block3a33.PORTBADDR4
+address_b[4] => ram_block3a34.PORTBADDR4
+address_b[4] => ram_block3a35.PORTBADDR4
+address_b[4] => ram_block3a36.PORTBADDR4
+address_b[4] => ram_block3a37.PORTBADDR4
+address_b[4] => ram_block3a38.PORTBADDR4
+address_b[4] => ram_block3a39.PORTBADDR4
+address_b[4] => ram_block3a40.PORTBADDR4
+address_b[4] => ram_block3a41.PORTBADDR4
+address_b[4] => ram_block3a42.PORTBADDR4
+address_b[4] => ram_block3a43.PORTBADDR4
+address_b[4] => ram_block3a44.PORTBADDR4
+address_b[4] => ram_block3a45.PORTBADDR4
+address_b[4] => ram_block3a46.PORTBADDR4
+address_b[4] => ram_block3a47.PORTBADDR4
+address_b[4] => ram_block3a48.PORTBADDR4
+address_b[4] => ram_block3a49.PORTBADDR4
+address_b[4] => ram_block3a50.PORTBADDR4
+address_b[4] => ram_block3a51.PORTBADDR4
+address_b[4] => ram_block3a52.PORTBADDR4
+address_b[4] => ram_block3a53.PORTBADDR4
+address_b[4] => ram_block3a54.PORTBADDR4
+address_b[4] => ram_block3a55.PORTBADDR4
+address_b[4] => ram_block3a56.PORTBADDR4
+address_b[4] => ram_block3a57.PORTBADDR4
+address_b[4] => ram_block3a58.PORTBADDR4
+address_b[4] => ram_block3a59.PORTBADDR4
+address_b[4] => ram_block3a60.PORTBADDR4
+address_b[4] => ram_block3a61.PORTBADDR4
+address_b[4] => ram_block3a62.PORTBADDR4
+address_b[4] => ram_block3a63.PORTBADDR4
+address_b[4] => ram_block3a64.PORTBADDR4
+address_b[4] => ram_block3a65.PORTBADDR4
+address_b[4] => ram_block3a66.PORTBADDR4
+address_b[4] => ram_block3a67.PORTBADDR4
+address_b[4] => ram_block3a68.PORTBADDR4
+address_b[4] => ram_block3a69.PORTBADDR4
+address_b[4] => ram_block3a70.PORTBADDR4
+address_b[4] => ram_block3a71.PORTBADDR4
+address_b[4] => ram_block3a72.PORTBADDR4
+address_b[4] => ram_block3a73.PORTBADDR4
+address_b[4] => ram_block3a74.PORTBADDR4
+address_b[4] => ram_block3a75.PORTBADDR4
+address_b[4] => ram_block3a76.PORTBADDR4
+address_b[4] => ram_block3a77.PORTBADDR4
+address_b[4] => ram_block3a78.PORTBADDR4
+address_b[4] => ram_block3a79.PORTBADDR4
+address_b[4] => ram_block3a80.PORTBADDR4
+address_b[4] => ram_block3a81.PORTBADDR4
+address_b[4] => ram_block3a82.PORTBADDR4
+address_b[4] => ram_block3a83.PORTBADDR4
+address_b[4] => ram_block3a84.PORTBADDR4
+address_b[4] => ram_block3a85.PORTBADDR4
+address_b[4] => ram_block3a86.PORTBADDR4
+address_b[4] => ram_block3a87.PORTBADDR4
+address_b[4] => ram_block3a88.PORTBADDR4
+address_b[4] => ram_block3a89.PORTBADDR4
+address_b[5] => ram_block3a0.PORTBADDR5
+address_b[5] => ram_block3a1.PORTBADDR5
+address_b[5] => ram_block3a2.PORTBADDR5
+address_b[5] => ram_block3a3.PORTBADDR5
+address_b[5] => ram_block3a4.PORTBADDR5
+address_b[5] => ram_block3a5.PORTBADDR5
+address_b[5] => ram_block3a6.PORTBADDR5
+address_b[5] => ram_block3a7.PORTBADDR5
+address_b[5] => ram_block3a8.PORTBADDR5
+address_b[5] => ram_block3a9.PORTBADDR5
+address_b[5] => ram_block3a10.PORTBADDR5
+address_b[5] => ram_block3a11.PORTBADDR5
+address_b[5] => ram_block3a12.PORTBADDR5
+address_b[5] => ram_block3a13.PORTBADDR5
+address_b[5] => ram_block3a14.PORTBADDR5
+address_b[5] => ram_block3a15.PORTBADDR5
+address_b[5] => ram_block3a16.PORTBADDR5
+address_b[5] => ram_block3a17.PORTBADDR5
+address_b[5] => ram_block3a18.PORTBADDR5
+address_b[5] => ram_block3a19.PORTBADDR5
+address_b[5] => ram_block3a20.PORTBADDR5
+address_b[5] => ram_block3a21.PORTBADDR5
+address_b[5] => ram_block3a22.PORTBADDR5
+address_b[5] => ram_block3a23.PORTBADDR5
+address_b[5] => ram_block3a24.PORTBADDR5
+address_b[5] => ram_block3a25.PORTBADDR5
+address_b[5] => ram_block3a26.PORTBADDR5
+address_b[5] => ram_block3a27.PORTBADDR5
+address_b[5] => ram_block3a28.PORTBADDR5
+address_b[5] => ram_block3a29.PORTBADDR5
+address_b[5] => ram_block3a30.PORTBADDR5
+address_b[5] => ram_block3a31.PORTBADDR5
+address_b[5] => ram_block3a32.PORTBADDR5
+address_b[5] => ram_block3a33.PORTBADDR5
+address_b[5] => ram_block3a34.PORTBADDR5
+address_b[5] => ram_block3a35.PORTBADDR5
+address_b[5] => ram_block3a36.PORTBADDR5
+address_b[5] => ram_block3a37.PORTBADDR5
+address_b[5] => ram_block3a38.PORTBADDR5
+address_b[5] => ram_block3a39.PORTBADDR5
+address_b[5] => ram_block3a40.PORTBADDR5
+address_b[5] => ram_block3a41.PORTBADDR5
+address_b[5] => ram_block3a42.PORTBADDR5
+address_b[5] => ram_block3a43.PORTBADDR5
+address_b[5] => ram_block3a44.PORTBADDR5
+address_b[5] => ram_block3a45.PORTBADDR5
+address_b[5] => ram_block3a46.PORTBADDR5
+address_b[5] => ram_block3a47.PORTBADDR5
+address_b[5] => ram_block3a48.PORTBADDR5
+address_b[5] => ram_block3a49.PORTBADDR5
+address_b[5] => ram_block3a50.PORTBADDR5
+address_b[5] => ram_block3a51.PORTBADDR5
+address_b[5] => ram_block3a52.PORTBADDR5
+address_b[5] => ram_block3a53.PORTBADDR5
+address_b[5] => ram_block3a54.PORTBADDR5
+address_b[5] => ram_block3a55.PORTBADDR5
+address_b[5] => ram_block3a56.PORTBADDR5
+address_b[5] => ram_block3a57.PORTBADDR5
+address_b[5] => ram_block3a58.PORTBADDR5
+address_b[5] => ram_block3a59.PORTBADDR5
+address_b[5] => ram_block3a60.PORTBADDR5
+address_b[5] => ram_block3a61.PORTBADDR5
+address_b[5] => ram_block3a62.PORTBADDR5
+address_b[5] => ram_block3a63.PORTBADDR5
+address_b[5] => ram_block3a64.PORTBADDR5
+address_b[5] => ram_block3a65.PORTBADDR5
+address_b[5] => ram_block3a66.PORTBADDR5
+address_b[5] => ram_block3a67.PORTBADDR5
+address_b[5] => ram_block3a68.PORTBADDR5
+address_b[5] => ram_block3a69.PORTBADDR5
+address_b[5] => ram_block3a70.PORTBADDR5
+address_b[5] => ram_block3a71.PORTBADDR5
+address_b[5] => ram_block3a72.PORTBADDR5
+address_b[5] => ram_block3a73.PORTBADDR5
+address_b[5] => ram_block3a74.PORTBADDR5
+address_b[5] => ram_block3a75.PORTBADDR5
+address_b[5] => ram_block3a76.PORTBADDR5
+address_b[5] => ram_block3a77.PORTBADDR5
+address_b[5] => ram_block3a78.PORTBADDR5
+address_b[5] => ram_block3a79.PORTBADDR5
+address_b[5] => ram_block3a80.PORTBADDR5
+address_b[5] => ram_block3a81.PORTBADDR5
+address_b[5] => ram_block3a82.PORTBADDR5
+address_b[5] => ram_block3a83.PORTBADDR5
+address_b[5] => ram_block3a84.PORTBADDR5
+address_b[5] => ram_block3a85.PORTBADDR5
+address_b[5] => ram_block3a86.PORTBADDR5
+address_b[5] => ram_block3a87.PORTBADDR5
+address_b[5] => ram_block3a88.PORTBADDR5
+address_b[5] => ram_block3a89.PORTBADDR5
+address_b[6] => ram_block3a0.PORTBADDR6
+address_b[6] => ram_block3a1.PORTBADDR6
+address_b[6] => ram_block3a2.PORTBADDR6
+address_b[6] => ram_block3a3.PORTBADDR6
+address_b[6] => ram_block3a4.PORTBADDR6
+address_b[6] => ram_block3a5.PORTBADDR6
+address_b[6] => ram_block3a6.PORTBADDR6
+address_b[6] => ram_block3a7.PORTBADDR6
+address_b[6] => ram_block3a8.PORTBADDR6
+address_b[6] => ram_block3a9.PORTBADDR6
+address_b[6] => ram_block3a10.PORTBADDR6
+address_b[6] => ram_block3a11.PORTBADDR6
+address_b[6] => ram_block3a12.PORTBADDR6
+address_b[6] => ram_block3a13.PORTBADDR6
+address_b[6] => ram_block3a14.PORTBADDR6
+address_b[6] => ram_block3a15.PORTBADDR6
+address_b[6] => ram_block3a16.PORTBADDR6
+address_b[6] => ram_block3a17.PORTBADDR6
+address_b[6] => ram_block3a18.PORTBADDR6
+address_b[6] => ram_block3a19.PORTBADDR6
+address_b[6] => ram_block3a20.PORTBADDR6
+address_b[6] => ram_block3a21.PORTBADDR6
+address_b[6] => ram_block3a22.PORTBADDR6
+address_b[6] => ram_block3a23.PORTBADDR6
+address_b[6] => ram_block3a24.PORTBADDR6
+address_b[6] => ram_block3a25.PORTBADDR6
+address_b[6] => ram_block3a26.PORTBADDR6
+address_b[6] => ram_block3a27.PORTBADDR6
+address_b[6] => ram_block3a28.PORTBADDR6
+address_b[6] => ram_block3a29.PORTBADDR6
+address_b[6] => ram_block3a30.PORTBADDR6
+address_b[6] => ram_block3a31.PORTBADDR6
+address_b[6] => ram_block3a32.PORTBADDR6
+address_b[6] => ram_block3a33.PORTBADDR6
+address_b[6] => ram_block3a34.PORTBADDR6
+address_b[6] => ram_block3a35.PORTBADDR6
+address_b[6] => ram_block3a36.PORTBADDR6
+address_b[6] => ram_block3a37.PORTBADDR6
+address_b[6] => ram_block3a38.PORTBADDR6
+address_b[6] => ram_block3a39.PORTBADDR6
+address_b[6] => ram_block3a40.PORTBADDR6
+address_b[6] => ram_block3a41.PORTBADDR6
+address_b[6] => ram_block3a42.PORTBADDR6
+address_b[6] => ram_block3a43.PORTBADDR6
+address_b[6] => ram_block3a44.PORTBADDR6
+address_b[6] => ram_block3a45.PORTBADDR6
+address_b[6] => ram_block3a46.PORTBADDR6
+address_b[6] => ram_block3a47.PORTBADDR6
+address_b[6] => ram_block3a48.PORTBADDR6
+address_b[6] => ram_block3a49.PORTBADDR6
+address_b[6] => ram_block3a50.PORTBADDR6
+address_b[6] => ram_block3a51.PORTBADDR6
+address_b[6] => ram_block3a52.PORTBADDR6
+address_b[6] => ram_block3a53.PORTBADDR6
+address_b[6] => ram_block3a54.PORTBADDR6
+address_b[6] => ram_block3a55.PORTBADDR6
+address_b[6] => ram_block3a56.PORTBADDR6
+address_b[6] => ram_block3a57.PORTBADDR6
+address_b[6] => ram_block3a58.PORTBADDR6
+address_b[6] => ram_block3a59.PORTBADDR6
+address_b[6] => ram_block3a60.PORTBADDR6
+address_b[6] => ram_block3a61.PORTBADDR6
+address_b[6] => ram_block3a62.PORTBADDR6
+address_b[6] => ram_block3a63.PORTBADDR6
+address_b[6] => ram_block3a64.PORTBADDR6
+address_b[6] => ram_block3a65.PORTBADDR6
+address_b[6] => ram_block3a66.PORTBADDR6
+address_b[6] => ram_block3a67.PORTBADDR6
+address_b[6] => ram_block3a68.PORTBADDR6
+address_b[6] => ram_block3a69.PORTBADDR6
+address_b[6] => ram_block3a70.PORTBADDR6
+address_b[6] => ram_block3a71.PORTBADDR6
+address_b[6] => ram_block3a72.PORTBADDR6
+address_b[6] => ram_block3a73.PORTBADDR6
+address_b[6] => ram_block3a74.PORTBADDR6
+address_b[6] => ram_block3a75.PORTBADDR6
+address_b[6] => ram_block3a76.PORTBADDR6
+address_b[6] => ram_block3a77.PORTBADDR6
+address_b[6] => ram_block3a78.PORTBADDR6
+address_b[6] => ram_block3a79.PORTBADDR6
+address_b[6] => ram_block3a80.PORTBADDR6
+address_b[6] => ram_block3a81.PORTBADDR6
+address_b[6] => ram_block3a82.PORTBADDR6
+address_b[6] => ram_block3a83.PORTBADDR6
+address_b[6] => ram_block3a84.PORTBADDR6
+address_b[6] => ram_block3a85.PORTBADDR6
+address_b[6] => ram_block3a86.PORTBADDR6
+address_b[6] => ram_block3a87.PORTBADDR6
+address_b[6] => ram_block3a88.PORTBADDR6
+address_b[6] => ram_block3a89.PORTBADDR6
+address_b[7] => ram_block3a0.PORTBADDR7
+address_b[7] => ram_block3a1.PORTBADDR7
+address_b[7] => ram_block3a2.PORTBADDR7
+address_b[7] => ram_block3a3.PORTBADDR7
+address_b[7] => ram_block3a4.PORTBADDR7
+address_b[7] => ram_block3a5.PORTBADDR7
+address_b[7] => ram_block3a6.PORTBADDR7
+address_b[7] => ram_block3a7.PORTBADDR7
+address_b[7] => ram_block3a8.PORTBADDR7
+address_b[7] => ram_block3a9.PORTBADDR7
+address_b[7] => ram_block3a10.PORTBADDR7
+address_b[7] => ram_block3a11.PORTBADDR7
+address_b[7] => ram_block3a12.PORTBADDR7
+address_b[7] => ram_block3a13.PORTBADDR7
+address_b[7] => ram_block3a14.PORTBADDR7
+address_b[7] => ram_block3a15.PORTBADDR7
+address_b[7] => ram_block3a16.PORTBADDR7
+address_b[7] => ram_block3a17.PORTBADDR7
+address_b[7] => ram_block3a18.PORTBADDR7
+address_b[7] => ram_block3a19.PORTBADDR7
+address_b[7] => ram_block3a20.PORTBADDR7
+address_b[7] => ram_block3a21.PORTBADDR7
+address_b[7] => ram_block3a22.PORTBADDR7
+address_b[7] => ram_block3a23.PORTBADDR7
+address_b[7] => ram_block3a24.PORTBADDR7
+address_b[7] => ram_block3a25.PORTBADDR7
+address_b[7] => ram_block3a26.PORTBADDR7
+address_b[7] => ram_block3a27.PORTBADDR7
+address_b[7] => ram_block3a28.PORTBADDR7
+address_b[7] => ram_block3a29.PORTBADDR7
+address_b[7] => ram_block3a30.PORTBADDR7
+address_b[7] => ram_block3a31.PORTBADDR7
+address_b[7] => ram_block3a32.PORTBADDR7
+address_b[7] => ram_block3a33.PORTBADDR7
+address_b[7] => ram_block3a34.PORTBADDR7
+address_b[7] => ram_block3a35.PORTBADDR7
+address_b[7] => ram_block3a36.PORTBADDR7
+address_b[7] => ram_block3a37.PORTBADDR7
+address_b[7] => ram_block3a38.PORTBADDR7
+address_b[7] => ram_block3a39.PORTBADDR7
+address_b[7] => ram_block3a40.PORTBADDR7
+address_b[7] => ram_block3a41.PORTBADDR7
+address_b[7] => ram_block3a42.PORTBADDR7
+address_b[7] => ram_block3a43.PORTBADDR7
+address_b[7] => ram_block3a44.PORTBADDR7
+address_b[7] => ram_block3a45.PORTBADDR7
+address_b[7] => ram_block3a46.PORTBADDR7
+address_b[7] => ram_block3a47.PORTBADDR7
+address_b[7] => ram_block3a48.PORTBADDR7
+address_b[7] => ram_block3a49.PORTBADDR7
+address_b[7] => ram_block3a50.PORTBADDR7
+address_b[7] => ram_block3a51.PORTBADDR7
+address_b[7] => ram_block3a52.PORTBADDR7
+address_b[7] => ram_block3a53.PORTBADDR7
+address_b[7] => ram_block3a54.PORTBADDR7
+address_b[7] => ram_block3a55.PORTBADDR7
+address_b[7] => ram_block3a56.PORTBADDR7
+address_b[7] => ram_block3a57.PORTBADDR7
+address_b[7] => ram_block3a58.PORTBADDR7
+address_b[7] => ram_block3a59.PORTBADDR7
+address_b[7] => ram_block3a60.PORTBADDR7
+address_b[7] => ram_block3a61.PORTBADDR7
+address_b[7] => ram_block3a62.PORTBADDR7
+address_b[7] => ram_block3a63.PORTBADDR7
+address_b[7] => ram_block3a64.PORTBADDR7
+address_b[7] => ram_block3a65.PORTBADDR7
+address_b[7] => ram_block3a66.PORTBADDR7
+address_b[7] => ram_block3a67.PORTBADDR7
+address_b[7] => ram_block3a68.PORTBADDR7
+address_b[7] => ram_block3a69.PORTBADDR7
+address_b[7] => ram_block3a70.PORTBADDR7
+address_b[7] => ram_block3a71.PORTBADDR7
+address_b[7] => ram_block3a72.PORTBADDR7
+address_b[7] => ram_block3a73.PORTBADDR7
+address_b[7] => ram_block3a74.PORTBADDR7
+address_b[7] => ram_block3a75.PORTBADDR7
+address_b[7] => ram_block3a76.PORTBADDR7
+address_b[7] => ram_block3a77.PORTBADDR7
+address_b[7] => ram_block3a78.PORTBADDR7
+address_b[7] => ram_block3a79.PORTBADDR7
+address_b[7] => ram_block3a80.PORTBADDR7
+address_b[7] => ram_block3a81.PORTBADDR7
+address_b[7] => ram_block3a82.PORTBADDR7
+address_b[7] => ram_block3a83.PORTBADDR7
+address_b[7] => ram_block3a84.PORTBADDR7
+address_b[7] => ram_block3a85.PORTBADDR7
+address_b[7] => ram_block3a86.PORTBADDR7
+address_b[7] => ram_block3a87.PORTBADDR7
+address_b[7] => ram_block3a88.PORTBADDR7
+address_b[7] => ram_block3a89.PORTBADDR7
+address_b[8] => ram_block3a0.PORTBADDR8
+address_b[8] => ram_block3a1.PORTBADDR8
+address_b[8] => ram_block3a2.PORTBADDR8
+address_b[8] => ram_block3a3.PORTBADDR8
+address_b[8] => ram_block3a4.PORTBADDR8
+address_b[8] => ram_block3a5.PORTBADDR8
+address_b[8] => ram_block3a6.PORTBADDR8
+address_b[8] => ram_block3a7.PORTBADDR8
+address_b[8] => ram_block3a8.PORTBADDR8
+address_b[8] => ram_block3a9.PORTBADDR8
+address_b[8] => ram_block3a10.PORTBADDR8
+address_b[8] => ram_block3a11.PORTBADDR8
+address_b[8] => ram_block3a12.PORTBADDR8
+address_b[8] => ram_block3a13.PORTBADDR8
+address_b[8] => ram_block3a14.PORTBADDR8
+address_b[8] => ram_block3a15.PORTBADDR8
+address_b[8] => ram_block3a16.PORTBADDR8
+address_b[8] => ram_block3a17.PORTBADDR8
+address_b[8] => ram_block3a18.PORTBADDR8
+address_b[8] => ram_block3a19.PORTBADDR8
+address_b[8] => ram_block3a20.PORTBADDR8
+address_b[8] => ram_block3a21.PORTBADDR8
+address_b[8] => ram_block3a22.PORTBADDR8
+address_b[8] => ram_block3a23.PORTBADDR8
+address_b[8] => ram_block3a24.PORTBADDR8
+address_b[8] => ram_block3a25.PORTBADDR8
+address_b[8] => ram_block3a26.PORTBADDR8
+address_b[8] => ram_block3a27.PORTBADDR8
+address_b[8] => ram_block3a28.PORTBADDR8
+address_b[8] => ram_block3a29.PORTBADDR8
+address_b[8] => ram_block3a30.PORTBADDR8
+address_b[8] => ram_block3a31.PORTBADDR8
+address_b[8] => ram_block3a32.PORTBADDR8
+address_b[8] => ram_block3a33.PORTBADDR8
+address_b[8] => ram_block3a34.PORTBADDR8
+address_b[8] => ram_block3a35.PORTBADDR8
+address_b[8] => ram_block3a36.PORTBADDR8
+address_b[8] => ram_block3a37.PORTBADDR8
+address_b[8] => ram_block3a38.PORTBADDR8
+address_b[8] => ram_block3a39.PORTBADDR8
+address_b[8] => ram_block3a40.PORTBADDR8
+address_b[8] => ram_block3a41.PORTBADDR8
+address_b[8] => ram_block3a42.PORTBADDR8
+address_b[8] => ram_block3a43.PORTBADDR8
+address_b[8] => ram_block3a44.PORTBADDR8
+address_b[8] => ram_block3a45.PORTBADDR8
+address_b[8] => ram_block3a46.PORTBADDR8
+address_b[8] => ram_block3a47.PORTBADDR8
+address_b[8] => ram_block3a48.PORTBADDR8
+address_b[8] => ram_block3a49.PORTBADDR8
+address_b[8] => ram_block3a50.PORTBADDR8
+address_b[8] => ram_block3a51.PORTBADDR8
+address_b[8] => ram_block3a52.PORTBADDR8
+address_b[8] => ram_block3a53.PORTBADDR8
+address_b[8] => ram_block3a54.PORTBADDR8
+address_b[8] => ram_block3a55.PORTBADDR8
+address_b[8] => ram_block3a56.PORTBADDR8
+address_b[8] => ram_block3a57.PORTBADDR8
+address_b[8] => ram_block3a58.PORTBADDR8
+address_b[8] => ram_block3a59.PORTBADDR8
+address_b[8] => ram_block3a60.PORTBADDR8
+address_b[8] => ram_block3a61.PORTBADDR8
+address_b[8] => ram_block3a62.PORTBADDR8
+address_b[8] => ram_block3a63.PORTBADDR8
+address_b[8] => ram_block3a64.PORTBADDR8
+address_b[8] => ram_block3a65.PORTBADDR8
+address_b[8] => ram_block3a66.PORTBADDR8
+address_b[8] => ram_block3a67.PORTBADDR8
+address_b[8] => ram_block3a68.PORTBADDR8
+address_b[8] => ram_block3a69.PORTBADDR8
+address_b[8] => ram_block3a70.PORTBADDR8
+address_b[8] => ram_block3a71.PORTBADDR8
+address_b[8] => ram_block3a72.PORTBADDR8
+address_b[8] => ram_block3a73.PORTBADDR8
+address_b[8] => ram_block3a74.PORTBADDR8
+address_b[8] => ram_block3a75.PORTBADDR8
+address_b[8] => ram_block3a76.PORTBADDR8
+address_b[8] => ram_block3a77.PORTBADDR8
+address_b[8] => ram_block3a78.PORTBADDR8
+address_b[8] => ram_block3a79.PORTBADDR8
+address_b[8] => ram_block3a80.PORTBADDR8
+address_b[8] => ram_block3a81.PORTBADDR8
+address_b[8] => ram_block3a82.PORTBADDR8
+address_b[8] => ram_block3a83.PORTBADDR8
+address_b[8] => ram_block3a84.PORTBADDR8
+address_b[8] => ram_block3a85.PORTBADDR8
+address_b[8] => ram_block3a86.PORTBADDR8
+address_b[8] => ram_block3a87.PORTBADDR8
+address_b[8] => ram_block3a88.PORTBADDR8
+address_b[8] => ram_block3a89.PORTBADDR8
+address_b[9] => ram_block3a0.PORTBADDR9
+address_b[9] => ram_block3a1.PORTBADDR9
+address_b[9] => ram_block3a2.PORTBADDR9
+address_b[9] => ram_block3a3.PORTBADDR9
+address_b[9] => ram_block3a4.PORTBADDR9
+address_b[9] => ram_block3a5.PORTBADDR9
+address_b[9] => ram_block3a6.PORTBADDR9
+address_b[9] => ram_block3a7.PORTBADDR9
+address_b[9] => ram_block3a8.PORTBADDR9
+address_b[9] => ram_block3a9.PORTBADDR9
+address_b[9] => ram_block3a10.PORTBADDR9
+address_b[9] => ram_block3a11.PORTBADDR9
+address_b[9] => ram_block3a12.PORTBADDR9
+address_b[9] => ram_block3a13.PORTBADDR9
+address_b[9] => ram_block3a14.PORTBADDR9
+address_b[9] => ram_block3a15.PORTBADDR9
+address_b[9] => ram_block3a16.PORTBADDR9
+address_b[9] => ram_block3a17.PORTBADDR9
+address_b[9] => ram_block3a18.PORTBADDR9
+address_b[9] => ram_block3a19.PORTBADDR9
+address_b[9] => ram_block3a20.PORTBADDR9
+address_b[9] => ram_block3a21.PORTBADDR9
+address_b[9] => ram_block3a22.PORTBADDR9
+address_b[9] => ram_block3a23.PORTBADDR9
+address_b[9] => ram_block3a24.PORTBADDR9
+address_b[9] => ram_block3a25.PORTBADDR9
+address_b[9] => ram_block3a26.PORTBADDR9
+address_b[9] => ram_block3a27.PORTBADDR9
+address_b[9] => ram_block3a28.PORTBADDR9
+address_b[9] => ram_block3a29.PORTBADDR9
+address_b[9] => ram_block3a30.PORTBADDR9
+address_b[9] => ram_block3a31.PORTBADDR9
+address_b[9] => ram_block3a32.PORTBADDR9
+address_b[9] => ram_block3a33.PORTBADDR9
+address_b[9] => ram_block3a34.PORTBADDR9
+address_b[9] => ram_block3a35.PORTBADDR9
+address_b[9] => ram_block3a36.PORTBADDR9
+address_b[9] => ram_block3a37.PORTBADDR9
+address_b[9] => ram_block3a38.PORTBADDR9
+address_b[9] => ram_block3a39.PORTBADDR9
+address_b[9] => ram_block3a40.PORTBADDR9
+address_b[9] => ram_block3a41.PORTBADDR9
+address_b[9] => ram_block3a42.PORTBADDR9
+address_b[9] => ram_block3a43.PORTBADDR9
+address_b[9] => ram_block3a44.PORTBADDR9
+address_b[9] => ram_block3a45.PORTBADDR9
+address_b[9] => ram_block3a46.PORTBADDR9
+address_b[9] => ram_block3a47.PORTBADDR9
+address_b[9] => ram_block3a48.PORTBADDR9
+address_b[9] => ram_block3a49.PORTBADDR9
+address_b[9] => ram_block3a50.PORTBADDR9
+address_b[9] => ram_block3a51.PORTBADDR9
+address_b[9] => ram_block3a52.PORTBADDR9
+address_b[9] => ram_block3a53.PORTBADDR9
+address_b[9] => ram_block3a54.PORTBADDR9
+address_b[9] => ram_block3a55.PORTBADDR9
+address_b[9] => ram_block3a56.PORTBADDR9
+address_b[9] => ram_block3a57.PORTBADDR9
+address_b[9] => ram_block3a58.PORTBADDR9
+address_b[9] => ram_block3a59.PORTBADDR9
+address_b[9] => ram_block3a60.PORTBADDR9
+address_b[9] => ram_block3a61.PORTBADDR9
+address_b[9] => ram_block3a62.PORTBADDR9
+address_b[9] => ram_block3a63.PORTBADDR9
+address_b[9] => ram_block3a64.PORTBADDR9
+address_b[9] => ram_block3a65.PORTBADDR9
+address_b[9] => ram_block3a66.PORTBADDR9
+address_b[9] => ram_block3a67.PORTBADDR9
+address_b[9] => ram_block3a68.PORTBADDR9
+address_b[9] => ram_block3a69.PORTBADDR9
+address_b[9] => ram_block3a70.PORTBADDR9
+address_b[9] => ram_block3a71.PORTBADDR9
+address_b[9] => ram_block3a72.PORTBADDR9
+address_b[9] => ram_block3a73.PORTBADDR9
+address_b[9] => ram_block3a74.PORTBADDR9
+address_b[9] => ram_block3a75.PORTBADDR9
+address_b[9] => ram_block3a76.PORTBADDR9
+address_b[9] => ram_block3a77.PORTBADDR9
+address_b[9] => ram_block3a78.PORTBADDR9
+address_b[9] => ram_block3a79.PORTBADDR9
+address_b[9] => ram_block3a80.PORTBADDR9
+address_b[9] => ram_block3a81.PORTBADDR9
+address_b[9] => ram_block3a82.PORTBADDR9
+address_b[9] => ram_block3a83.PORTBADDR9
+address_b[9] => ram_block3a84.PORTBADDR9
+address_b[9] => ram_block3a85.PORTBADDR9
+address_b[9] => ram_block3a86.PORTBADDR9
+address_b[9] => ram_block3a87.PORTBADDR9
+address_b[9] => ram_block3a88.PORTBADDR9
+address_b[9] => ram_block3a89.PORTBADDR9
+clock0 => ram_block3a0.CLK0
+clock0 => ram_block3a1.CLK0
+clock0 => ram_block3a2.CLK0
+clock0 => ram_block3a3.CLK0
+clock0 => ram_block3a4.CLK0
+clock0 => ram_block3a5.CLK0
+clock0 => ram_block3a6.CLK0
+clock0 => ram_block3a7.CLK0
+clock0 => ram_block3a8.CLK0
+clock0 => ram_block3a9.CLK0
+clock0 => ram_block3a10.CLK0
+clock0 => ram_block3a11.CLK0
+clock0 => ram_block3a12.CLK0
+clock0 => ram_block3a13.CLK0
+clock0 => ram_block3a14.CLK0
+clock0 => ram_block3a15.CLK0
+clock0 => ram_block3a16.CLK0
+clock0 => ram_block3a17.CLK0
+clock0 => ram_block3a18.CLK0
+clock0 => ram_block3a19.CLK0
+clock0 => ram_block3a20.CLK0
+clock0 => ram_block3a21.CLK0
+clock0 => ram_block3a22.CLK0
+clock0 => ram_block3a23.CLK0
+clock0 => ram_block3a24.CLK0
+clock0 => ram_block3a25.CLK0
+clock0 => ram_block3a26.CLK0
+clock0 => ram_block3a27.CLK0
+clock0 => ram_block3a28.CLK0
+clock0 => ram_block3a29.CLK0
+clock0 => ram_block3a30.CLK0
+clock0 => ram_block3a31.CLK0
+clock0 => ram_block3a32.CLK0
+clock0 => ram_block3a33.CLK0
+clock0 => ram_block3a34.CLK0
+clock0 => ram_block3a35.CLK0
+clock0 => ram_block3a36.CLK0
+clock0 => ram_block3a37.CLK0
+clock0 => ram_block3a38.CLK0
+clock0 => ram_block3a39.CLK0
+clock0 => ram_block3a40.CLK0
+clock0 => ram_block3a41.CLK0
+clock0 => ram_block3a42.CLK0
+clock0 => ram_block3a43.CLK0
+clock0 => ram_block3a44.CLK0
+clock0 => ram_block3a45.CLK0
+clock0 => ram_block3a46.CLK0
+clock0 => ram_block3a47.CLK0
+clock0 => ram_block3a48.CLK0
+clock0 => ram_block3a49.CLK0
+clock0 => ram_block3a50.CLK0
+clock0 => ram_block3a51.CLK0
+clock0 => ram_block3a52.CLK0
+clock0 => ram_block3a53.CLK0
+clock0 => ram_block3a54.CLK0
+clock0 => ram_block3a55.CLK0
+clock0 => ram_block3a56.CLK0
+clock0 => ram_block3a57.CLK0
+clock0 => ram_block3a58.CLK0
+clock0 => ram_block3a59.CLK0
+clock0 => ram_block3a60.CLK0
+clock0 => ram_block3a61.CLK0
+clock0 => ram_block3a62.CLK0
+clock0 => ram_block3a63.CLK0
+clock0 => ram_block3a64.CLK0
+clock0 => ram_block3a65.CLK0
+clock0 => ram_block3a66.CLK0
+clock0 => ram_block3a67.CLK0
+clock0 => ram_block3a68.CLK0
+clock0 => ram_block3a69.CLK0
+clock0 => ram_block3a70.CLK0
+clock0 => ram_block3a71.CLK0
+clock0 => ram_block3a72.CLK0
+clock0 => ram_block3a73.CLK0
+clock0 => ram_block3a74.CLK0
+clock0 => ram_block3a75.CLK0
+clock0 => ram_block3a76.CLK0
+clock0 => ram_block3a77.CLK0
+clock0 => ram_block3a78.CLK0
+clock0 => ram_block3a79.CLK0
+clock0 => ram_block3a80.CLK0
+clock0 => ram_block3a81.CLK0
+clock0 => ram_block3a82.CLK0
+clock0 => ram_block3a83.CLK0
+clock0 => ram_block3a84.CLK0
+clock0 => ram_block3a85.CLK0
+clock0 => ram_block3a86.CLK0
+clock0 => ram_block3a87.CLK0
+clock0 => ram_block3a88.CLK0
+clock0 => ram_block3a89.CLK0
+clocken0 => ram_block3a0.ENA0
+clocken0 => ram_block3a1.ENA0
+clocken0 => ram_block3a2.ENA0
+clocken0 => ram_block3a3.ENA0
+clocken0 => ram_block3a4.ENA0
+clocken0 => ram_block3a5.ENA0
+clocken0 => ram_block3a6.ENA0
+clocken0 => ram_block3a7.ENA0
+clocken0 => ram_block3a8.ENA0
+clocken0 => ram_block3a9.ENA0
+clocken0 => ram_block3a10.ENA0
+clocken0 => ram_block3a11.ENA0
+clocken0 => ram_block3a12.ENA0
+clocken0 => ram_block3a13.ENA0
+clocken0 => ram_block3a14.ENA0
+clocken0 => ram_block3a15.ENA0
+clocken0 => ram_block3a16.ENA0
+clocken0 => ram_block3a17.ENA0
+clocken0 => ram_block3a18.ENA0
+clocken0 => ram_block3a19.ENA0
+clocken0 => ram_block3a20.ENA0
+clocken0 => ram_block3a21.ENA0
+clocken0 => ram_block3a22.ENA0
+clocken0 => ram_block3a23.ENA0
+clocken0 => ram_block3a24.ENA0
+clocken0 => ram_block3a25.ENA0
+clocken0 => ram_block3a26.ENA0
+clocken0 => ram_block3a27.ENA0
+clocken0 => ram_block3a28.ENA0
+clocken0 => ram_block3a29.ENA0
+clocken0 => ram_block3a30.ENA0
+clocken0 => ram_block3a31.ENA0
+clocken0 => ram_block3a32.ENA0
+clocken0 => ram_block3a33.ENA0
+clocken0 => ram_block3a34.ENA0
+clocken0 => ram_block3a35.ENA0
+clocken0 => ram_block3a36.ENA0
+clocken0 => ram_block3a37.ENA0
+clocken0 => ram_block3a38.ENA0
+clocken0 => ram_block3a39.ENA0
+clocken0 => ram_block3a40.ENA0
+clocken0 => ram_block3a41.ENA0
+clocken0 => ram_block3a42.ENA0
+clocken0 => ram_block3a43.ENA0
+clocken0 => ram_block3a44.ENA0
+clocken0 => ram_block3a45.ENA0
+clocken0 => ram_block3a46.ENA0
+clocken0 => ram_block3a47.ENA0
+clocken0 => ram_block3a48.ENA0
+clocken0 => ram_block3a49.ENA0
+clocken0 => ram_block3a50.ENA0
+clocken0 => ram_block3a51.ENA0
+clocken0 => ram_block3a52.ENA0
+clocken0 => ram_block3a53.ENA0
+clocken0 => ram_block3a54.ENA0
+clocken0 => ram_block3a55.ENA0
+clocken0 => ram_block3a56.ENA0
+clocken0 => ram_block3a57.ENA0
+clocken0 => ram_block3a58.ENA0
+clocken0 => ram_block3a59.ENA0
+clocken0 => ram_block3a60.ENA0
+clocken0 => ram_block3a61.ENA0
+clocken0 => ram_block3a62.ENA0
+clocken0 => ram_block3a63.ENA0
+clocken0 => ram_block3a64.ENA0
+clocken0 => ram_block3a65.ENA0
+clocken0 => ram_block3a66.ENA0
+clocken0 => ram_block3a67.ENA0
+clocken0 => ram_block3a68.ENA0
+clocken0 => ram_block3a69.ENA0
+clocken0 => ram_block3a70.ENA0
+clocken0 => ram_block3a71.ENA0
+clocken0 => ram_block3a72.ENA0
+clocken0 => ram_block3a73.ENA0
+clocken0 => ram_block3a74.ENA0
+clocken0 => ram_block3a75.ENA0
+clocken0 => ram_block3a76.ENA0
+clocken0 => ram_block3a77.ENA0
+clocken0 => ram_block3a78.ENA0
+clocken0 => ram_block3a79.ENA0
+clocken0 => ram_block3a80.ENA0
+clocken0 => ram_block3a81.ENA0
+clocken0 => ram_block3a82.ENA0
+clocken0 => ram_block3a83.ENA0
+clocken0 => ram_block3a84.ENA0
+clocken0 => ram_block3a85.ENA0
+clocken0 => ram_block3a86.ENA0
+clocken0 => ram_block3a87.ENA0
+clocken0 => ram_block3a88.ENA0
+clocken0 => ram_block3a89.ENA0
+data_a[0] => ram_block3a0.PORTADATAIN
+data_a[1] => ram_block3a1.PORTADATAIN
+data_a[2] => ram_block3a2.PORTADATAIN
+data_a[3] => ram_block3a3.PORTADATAIN
+data_a[4] => ram_block3a4.PORTADATAIN
+data_a[5] => ram_block3a5.PORTADATAIN
+data_a[6] => ram_block3a6.PORTADATAIN
+data_a[7] => ram_block3a7.PORTADATAIN
+data_a[8] => ram_block3a8.PORTADATAIN
+data_a[9] => ram_block3a9.PORTADATAIN
+data_a[10] => ram_block3a10.PORTADATAIN
+data_a[11] => ram_block3a11.PORTADATAIN
+data_a[12] => ram_block3a12.PORTADATAIN
+data_a[13] => ram_block3a13.PORTADATAIN
+data_a[14] => ram_block3a14.PORTADATAIN
+data_a[15] => ram_block3a15.PORTADATAIN
+data_a[16] => ram_block3a16.PORTADATAIN
+data_a[17] => ram_block3a17.PORTADATAIN
+data_a[18] => ram_block3a18.PORTADATAIN
+data_a[19] => ram_block3a19.PORTADATAIN
+data_a[20] => ram_block3a20.PORTADATAIN
+data_a[21] => ram_block3a21.PORTADATAIN
+data_a[22] => ram_block3a22.PORTADATAIN
+data_a[23] => ram_block3a23.PORTADATAIN
+data_a[24] => ram_block3a24.PORTADATAIN
+data_a[25] => ram_block3a25.PORTADATAIN
+data_a[26] => ram_block3a26.PORTADATAIN
+data_a[27] => ram_block3a27.PORTADATAIN
+data_a[28] => ram_block3a28.PORTADATAIN
+data_a[29] => ram_block3a29.PORTADATAIN
+data_a[30] => ram_block3a30.PORTADATAIN
+data_a[31] => ram_block3a31.PORTADATAIN
+data_a[32] => ram_block3a32.PORTADATAIN
+data_a[33] => ram_block3a33.PORTADATAIN
+data_a[34] => ram_block3a34.PORTADATAIN
+data_a[35] => ram_block3a35.PORTADATAIN
+data_a[36] => ram_block3a36.PORTADATAIN
+data_a[37] => ram_block3a37.PORTADATAIN
+data_a[38] => ram_block3a38.PORTADATAIN
+data_a[39] => ram_block3a39.PORTADATAIN
+data_a[40] => ram_block3a40.PORTADATAIN
+data_a[41] => ram_block3a41.PORTADATAIN
+data_a[42] => ram_block3a42.PORTADATAIN
+data_a[43] => ram_block3a43.PORTADATAIN
+data_a[44] => ram_block3a44.PORTADATAIN
+data_a[45] => ram_block3a45.PORTADATAIN
+data_a[46] => ram_block3a46.PORTADATAIN
+data_a[47] => ram_block3a47.PORTADATAIN
+data_a[48] => ram_block3a48.PORTADATAIN
+data_a[49] => ram_block3a49.PORTADATAIN
+data_a[50] => ram_block3a50.PORTADATAIN
+data_a[51] => ram_block3a51.PORTADATAIN
+data_a[52] => ram_block3a52.PORTADATAIN
+data_a[53] => ram_block3a53.PORTADATAIN
+data_a[54] => ram_block3a54.PORTADATAIN
+data_a[55] => ram_block3a55.PORTADATAIN
+data_a[56] => ram_block3a56.PORTADATAIN
+data_a[57] => ram_block3a57.PORTADATAIN
+data_a[58] => ram_block3a58.PORTADATAIN
+data_a[59] => ram_block3a59.PORTADATAIN
+data_a[60] => ram_block3a60.PORTADATAIN
+data_a[61] => ram_block3a61.PORTADATAIN
+data_a[62] => ram_block3a62.PORTADATAIN
+data_a[63] => ram_block3a63.PORTADATAIN
+data_a[64] => ram_block3a64.PORTADATAIN
+data_a[65] => ram_block3a65.PORTADATAIN
+data_a[66] => ram_block3a66.PORTADATAIN
+data_a[67] => ram_block3a67.PORTADATAIN
+data_a[68] => ram_block3a68.PORTADATAIN
+data_a[69] => ram_block3a69.PORTADATAIN
+data_a[70] => ram_block3a70.PORTADATAIN
+data_a[71] => ram_block3a71.PORTADATAIN
+data_a[72] => ram_block3a72.PORTADATAIN
+data_a[73] => ram_block3a73.PORTADATAIN
+data_a[74] => ram_block3a74.PORTADATAIN
+data_a[75] => ram_block3a75.PORTADATAIN
+data_a[76] => ram_block3a76.PORTADATAIN
+data_a[77] => ram_block3a77.PORTADATAIN
+data_a[78] => ram_block3a78.PORTADATAIN
+data_a[79] => ram_block3a79.PORTADATAIN
+data_a[80] => ram_block3a80.PORTADATAIN
+data_a[81] => ram_block3a81.PORTADATAIN
+data_a[82] => ram_block3a82.PORTADATAIN
+data_a[83] => ram_block3a83.PORTADATAIN
+data_a[84] => ram_block3a84.PORTADATAIN
+data_a[85] => ram_block3a85.PORTADATAIN
+data_a[86] => ram_block3a86.PORTADATAIN
+data_a[87] => ram_block3a87.PORTADATAIN
+data_a[88] => ram_block3a88.PORTADATAIN
+data_a[89] => ram_block3a89.PORTADATAIN
+q_b[0] <= ram_block3a0.PORTBDATAOUT
+q_b[1] <= ram_block3a1.PORTBDATAOUT
+q_b[2] <= ram_block3a2.PORTBDATAOUT
+q_b[3] <= ram_block3a3.PORTBDATAOUT
+q_b[4] <= ram_block3a4.PORTBDATAOUT
+q_b[5] <= ram_block3a5.PORTBDATAOUT
+q_b[6] <= ram_block3a6.PORTBDATAOUT
+q_b[7] <= ram_block3a7.PORTBDATAOUT
+q_b[8] <= ram_block3a8.PORTBDATAOUT
+q_b[9] <= ram_block3a9.PORTBDATAOUT
+q_b[10] <= ram_block3a10.PORTBDATAOUT
+q_b[11] <= ram_block3a11.PORTBDATAOUT
+q_b[12] <= ram_block3a12.PORTBDATAOUT
+q_b[13] <= ram_block3a13.PORTBDATAOUT
+q_b[14] <= ram_block3a14.PORTBDATAOUT
+q_b[15] <= ram_block3a15.PORTBDATAOUT
+q_b[16] <= ram_block3a16.PORTBDATAOUT
+q_b[17] <= ram_block3a17.PORTBDATAOUT
+q_b[18] <= ram_block3a18.PORTBDATAOUT
+q_b[19] <= ram_block3a19.PORTBDATAOUT
+q_b[20] <= ram_block3a20.PORTBDATAOUT
+q_b[21] <= ram_block3a21.PORTBDATAOUT
+q_b[22] <= ram_block3a22.PORTBDATAOUT
+q_b[23] <= ram_block3a23.PORTBDATAOUT
+q_b[24] <= ram_block3a24.PORTBDATAOUT
+q_b[25] <= ram_block3a25.PORTBDATAOUT
+q_b[26] <= ram_block3a26.PORTBDATAOUT
+q_b[27] <= ram_block3a27.PORTBDATAOUT
+q_b[28] <= ram_block3a28.PORTBDATAOUT
+q_b[29] <= ram_block3a29.PORTBDATAOUT
+q_b[30] <= ram_block3a30.PORTBDATAOUT
+q_b[31] <= ram_block3a31.PORTBDATAOUT
+q_b[32] <= ram_block3a32.PORTBDATAOUT
+q_b[33] <= ram_block3a33.PORTBDATAOUT
+q_b[34] <= ram_block3a34.PORTBDATAOUT
+q_b[35] <= ram_block3a35.PORTBDATAOUT
+q_b[36] <= ram_block3a36.PORTBDATAOUT
+q_b[37] <= ram_block3a37.PORTBDATAOUT
+q_b[38] <= ram_block3a38.PORTBDATAOUT
+q_b[39] <= ram_block3a39.PORTBDATAOUT
+q_b[40] <= ram_block3a40.PORTBDATAOUT
+q_b[41] <= ram_block3a41.PORTBDATAOUT
+q_b[42] <= ram_block3a42.PORTBDATAOUT
+q_b[43] <= ram_block3a43.PORTBDATAOUT
+q_b[44] <= ram_block3a44.PORTBDATAOUT
+q_b[45] <= ram_block3a45.PORTBDATAOUT
+q_b[46] <= ram_block3a46.PORTBDATAOUT
+q_b[47] <= ram_block3a47.PORTBDATAOUT
+q_b[48] <= ram_block3a48.PORTBDATAOUT
+q_b[49] <= ram_block3a49.PORTBDATAOUT
+q_b[50] <= ram_block3a50.PORTBDATAOUT
+q_b[51] <= ram_block3a51.PORTBDATAOUT
+q_b[52] <= ram_block3a52.PORTBDATAOUT
+q_b[53] <= ram_block3a53.PORTBDATAOUT
+q_b[54] <= ram_block3a54.PORTBDATAOUT
+q_b[55] <= ram_block3a55.PORTBDATAOUT
+q_b[56] <= ram_block3a56.PORTBDATAOUT
+q_b[57] <= ram_block3a57.PORTBDATAOUT
+q_b[58] <= ram_block3a58.PORTBDATAOUT
+q_b[59] <= ram_block3a59.PORTBDATAOUT
+q_b[60] <= ram_block3a60.PORTBDATAOUT
+q_b[61] <= ram_block3a61.PORTBDATAOUT
+q_b[62] <= ram_block3a62.PORTBDATAOUT
+q_b[63] <= ram_block3a63.PORTBDATAOUT
+q_b[64] <= ram_block3a64.PORTBDATAOUT
+q_b[65] <= ram_block3a65.PORTBDATAOUT
+q_b[66] <= ram_block3a66.PORTBDATAOUT
+q_b[67] <= ram_block3a67.PORTBDATAOUT
+q_b[68] <= ram_block3a68.PORTBDATAOUT
+q_b[69] <= ram_block3a69.PORTBDATAOUT
+q_b[70] <= ram_block3a70.PORTBDATAOUT
+q_b[71] <= ram_block3a71.PORTBDATAOUT
+q_b[72] <= ram_block3a72.PORTBDATAOUT
+q_b[73] <= ram_block3a73.PORTBDATAOUT
+q_b[74] <= ram_block3a74.PORTBDATAOUT
+q_b[75] <= ram_block3a75.PORTBDATAOUT
+q_b[76] <= ram_block3a76.PORTBDATAOUT
+q_b[77] <= ram_block3a77.PORTBDATAOUT
+q_b[78] <= ram_block3a78.PORTBDATAOUT
+q_b[79] <= ram_block3a79.PORTBDATAOUT
+q_b[80] <= ram_block3a80.PORTBDATAOUT
+q_b[81] <= ram_block3a81.PORTBDATAOUT
+q_b[82] <= ram_block3a82.PORTBDATAOUT
+q_b[83] <= ram_block3a83.PORTBDATAOUT
+q_b[84] <= ram_block3a84.PORTBDATAOUT
+q_b[85] <= ram_block3a85.PORTBDATAOUT
+q_b[86] <= ram_block3a86.PORTBDATAOUT
+q_b[87] <= ram_block3a87.PORTBDATAOUT
+q_b[88] <= ram_block3a88.PORTBDATAOUT
+q_b[89] <= ram_block3a89.PORTBDATAOUT
+wren_a => ram_block3a0.PORTAWE
+wren_a => ram_block3a1.PORTAWE
+wren_a => ram_block3a2.PORTAWE
+wren_a => ram_block3a3.PORTAWE
+wren_a => ram_block3a4.PORTAWE
+wren_a => ram_block3a5.PORTAWE
+wren_a => ram_block3a6.PORTAWE
+wren_a => ram_block3a7.PORTAWE
+wren_a => ram_block3a8.PORTAWE
+wren_a => ram_block3a9.PORTAWE
+wren_a => ram_block3a10.PORTAWE
+wren_a => ram_block3a11.PORTAWE
+wren_a => ram_block3a12.PORTAWE
+wren_a => ram_block3a13.PORTAWE
+wren_a => ram_block3a14.PORTAWE
+wren_a => ram_block3a15.PORTAWE
+wren_a => ram_block3a16.PORTAWE
+wren_a => ram_block3a17.PORTAWE
+wren_a => ram_block3a18.PORTAWE
+wren_a => ram_block3a19.PORTAWE
+wren_a => ram_block3a20.PORTAWE
+wren_a => ram_block3a21.PORTAWE
+wren_a => ram_block3a22.PORTAWE
+wren_a => ram_block3a23.PORTAWE
+wren_a => ram_block3a24.PORTAWE
+wren_a => ram_block3a25.PORTAWE
+wren_a => ram_block3a26.PORTAWE
+wren_a => ram_block3a27.PORTAWE
+wren_a => ram_block3a28.PORTAWE
+wren_a => ram_block3a29.PORTAWE
+wren_a => ram_block3a30.PORTAWE
+wren_a => ram_block3a31.PORTAWE
+wren_a => ram_block3a32.PORTAWE
+wren_a => ram_block3a33.PORTAWE
+wren_a => ram_block3a34.PORTAWE
+wren_a => ram_block3a35.PORTAWE
+wren_a => ram_block3a36.PORTAWE
+wren_a => ram_block3a37.PORTAWE
+wren_a => ram_block3a38.PORTAWE
+wren_a => ram_block3a39.PORTAWE
+wren_a => ram_block3a40.PORTAWE
+wren_a => ram_block3a41.PORTAWE
+wren_a => ram_block3a42.PORTAWE
+wren_a => ram_block3a43.PORTAWE
+wren_a => ram_block3a44.PORTAWE
+wren_a => ram_block3a45.PORTAWE
+wren_a => ram_block3a46.PORTAWE
+wren_a => ram_block3a47.PORTAWE
+wren_a => ram_block3a48.PORTAWE
+wren_a => ram_block3a49.PORTAWE
+wren_a => ram_block3a50.PORTAWE
+wren_a => ram_block3a51.PORTAWE
+wren_a => ram_block3a52.PORTAWE
+wren_a => ram_block3a53.PORTAWE
+wren_a => ram_block3a54.PORTAWE
+wren_a => ram_block3a55.PORTAWE
+wren_a => ram_block3a56.PORTAWE
+wren_a => ram_block3a57.PORTAWE
+wren_a => ram_block3a58.PORTAWE
+wren_a => ram_block3a59.PORTAWE
+wren_a => ram_block3a60.PORTAWE
+wren_a => ram_block3a61.PORTAWE
+wren_a => ram_block3a62.PORTAWE
+wren_a => ram_block3a63.PORTAWE
+wren_a => ram_block3a64.PORTAWE
+wren_a => ram_block3a65.PORTAWE
+wren_a => ram_block3a66.PORTAWE
+wren_a => ram_block3a67.PORTAWE
+wren_a => ram_block3a68.PORTAWE
+wren_a => ram_block3a69.PORTAWE
+wren_a => ram_block3a70.PORTAWE
+wren_a => ram_block3a71.PORTAWE
+wren_a => ram_block3a72.PORTAWE
+wren_a => ram_block3a73.PORTAWE
+wren_a => ram_block3a74.PORTAWE
+wren_a => ram_block3a75.PORTAWE
+wren_a => ram_block3a76.PORTAWE
+wren_a => ram_block3a77.PORTAWE
+wren_a => ram_block3a78.PORTAWE
+wren_a => ram_block3a79.PORTAWE
+wren_a => ram_block3a80.PORTAWE
+wren_a => ram_block3a81.PORTAWE
+wren_a => ram_block3a82.PORTAWE
+wren_a => ram_block3a83.PORTAWE
+wren_a => ram_block3a84.PORTAWE
+wren_a => ram_block3a85.PORTAWE
+wren_a => ram_block3a86.PORTAWE
+wren_a => ram_block3a87.PORTAWE
+wren_a => ram_block3a88.PORTAWE
+wren_a => ram_block3a89.PORTAWE
+
+
+|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1
+clk_en => counter_reg_bit[9].IN0
+clock => counter_reg_bit[9].CLK
+clock => counter_reg_bit[8].CLK
+clock => counter_reg_bit[7].CLK
+clock => counter_reg_bit[6].CLK
+clock => counter_reg_bit[5].CLK
+clock => counter_reg_bit[4].CLK
+clock => counter_reg_bit[3].CLK
+clock => counter_reg_bit[2].CLK
+clock => counter_reg_bit[1].CLK
+clock => counter_reg_bit[0].CLK
+q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter_reg_bit[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter_reg_bit[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter_reg_bit[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_jpm:auto_generated|cntr_1tf:cntr1|cmpr_ugc:cmpr4
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hif b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hif
new file mode 100644
index 0000000..abff6f7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hif
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ipinfo b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ipinfo
new file mode 100644
index 0000000..e7708af
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ipinfo
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.html b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.html
new file mode 100644
index 0000000..d6718e6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.html
@@ -0,0 +1,2018 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >fifo_inst2|auto_generated|cntr1|cmpr4</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >fifo_inst2|auto_generated|cntr1</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >fifo_inst2|auto_generated|altsyncram2</TD>
+<TD >113</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >90</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >fifo_inst2|auto_generated</TD>
+<TD >32</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >90</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst1|sobel_core_inst</TD>
+<TD >93</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst1|vout_rsc_mgc_out_stdreg</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst1|vin_rsc_mgc_in_wire</TD>
+<TD >90</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >90</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst1</TD>
+<TD >93</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >30</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst|vga_mouse_square_core_inst</TD>
+<TD >81</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst|video_out_rsc_mgc_out_stdreg</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst|video_in_rsc_mgc_in_wire</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst|cursor_size_rsc_mgc_in_wire</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst|mouse_xy_rsc_mgc_in_wire</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst|vga_xy_rsc_mgc_in_wire</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst</TD>
+<TD >81</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >30</TD>
+<TD >3</TD>
+<TD >3</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
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+<TD >inst10|LPM_MUX_component|auto_generated</TD>
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+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5|u4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5|u3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5|u2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5|u1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5|u0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5</TD>
+<TD >32</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >28</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u4|u0|altshift_taps_component|auto_generated|cntr1|cmpr4</TD>
+<TD >22</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u4|u0|altshift_taps_component|auto_generated|cntr1</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u4|u0|altshift_taps_component|auto_generated|altsyncram2</TD>
+<TD >49</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >24</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u4|u0|altshift_taps_component|auto_generated</TD>
+<TD >14</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >36</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u4|u0</TD>
+<TD >14</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >24</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u4</TD>
+<TD >37</TD>
+<TD >0</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >37</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u3</TD>
+<TD >18</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >77</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u1</TD>
+<TD >32</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >58</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst</TD>
+<TD >16</TD>
+<TD >39</TD>
+<TD >8</TD>
+<TD >39</TD>
+<TD >120</TD>
+<TD >39</TD>
+<TD >39</TD>
+<TD >39</TD>
+<TD >48</TD>
+<TD >0</TD>
+<TD >14</TD>
+<TD >0</TD>
+<TD >14</TD>
+</TR>
+</TABLE>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.rdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.rdb
new file mode 100644
index 0000000..f38f13d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.rdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.txt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.txt
new file mode 100644
index 0000000..d10439c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.txt
@@ -0,0 +1,131 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                                                                 ;
++-----------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                                                             ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; fifo_inst2|auto_generated|cntr1|cmpr4                                 ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; fifo_inst2|auto_generated|cntr1                                       ; 2     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; fifo_inst2|auto_generated|altsyncram2                                 ; 113   ; 1              ; 0            ; 1              ; 90     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; fifo_inst2|auto_generated                                             ; 32    ; 0              ; 0            ; 0              ; 90     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst1|sobel_core_inst                                                 ; 93    ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst1|vout_rsc_mgc_out_stdreg                                         ; 30    ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst1|vin_rsc_mgc_in_wire                                             ; 90    ; 0              ; 0            ; 0              ; 90     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst1                                                                 ; 93    ; 1              ; 0            ; 1              ; 30     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst|vga_mouse_square_core_inst                    ; 81    ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst|video_out_rsc_mgc_out_stdreg                  ; 30    ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst|video_in_rsc_mgc_in_wire                      ; 30    ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst|cursor_size_rsc_mgc_in_wire                   ; 8     ; 0              ; 0            ; 0              ; 8      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst|mouse_xy_rsc_mgc_in_wire                      ; 20    ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst|vga_xy_rsc_mgc_in_wire                        ; 20    ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst                                               ; 81    ; 3              ; 0            ; 3              ; 30     ; 3               ; 3             ; 3               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst10|LPM_MUX_component|auto_generated                               ; 122   ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst10                                                                ; 122   ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst6|U4                                                              ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst6|U3                                                              ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst6|U2                                                              ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst6|U1                                                              ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst6                                                                 ; 3     ; 0              ; 0            ; 0              ; 47     ; 0               ; 0             ; 0               ; 2     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u8|u0                                                            ; 35    ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 1     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u8                                                               ; 5     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 1     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp     ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp    ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe16  ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_dgrp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_bwp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_brp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe13  ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_dgwp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_bwp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_brp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|fifo_ram           ; 40    ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|wrptr_g1p          ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rdptr_g1p          ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated                    ; 21    ; 0              ; 0            ; 0              ; 36     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2                                                    ; 21    ; 0              ; 0            ; 0              ; 25     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp     ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp    ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe16  ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_dgrp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_bwp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_brp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe13  ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_dgwp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_bwp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_brp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|fifo_ram           ; 40    ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|wrptr_g1p          ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rdptr_g1p          ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated                    ; 21    ; 0              ; 0            ; 0              ; 36     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1                                                    ; 21    ; 0              ; 0            ; 0              ; 25     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp    ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp   ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe16 ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_dgrp           ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_bwp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_brp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe13 ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_dgwp           ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_bwp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_brp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|fifo_ram          ; 40    ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|wrptr_g1p         ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rdptr_g1p         ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated                   ; 21    ; 0              ; 0            ; 0              ; 36     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2                                                   ; 21    ; 0              ; 0            ; 0              ; 25     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp    ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp   ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe16 ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_dgrp           ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_bwp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_brp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe13 ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_dgwp           ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_bwp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_brp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|fifo_ram          ; 40    ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|wrptr_g1p         ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rdptr_g1p         ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated                   ; 21    ; 0              ; 0            ; 0              ; 36     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1                                                   ; 21    ; 0              ; 0            ; 0              ; 25     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|data_path1                                                    ; 20    ; 2              ; 0            ; 2              ; 18     ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|command1                                                      ; 35    ; 0              ; 2            ; 0              ; 23     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|control1                                                      ; 30    ; 1              ; 0            ; 1              ; 32     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7                                                               ; 267   ; 224            ; 1            ; 224            ; 54     ; 224             ; 224           ; 224             ; 16    ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u6|altpll_component|auto_generated                               ; 2     ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u6                                                               ; 1     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u7                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u6                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u5                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u4                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u3                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u2                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u1                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u0                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5                                                               ; 32    ; 0              ; 0            ; 0              ; 28     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u4|u0|altshift_taps_component|auto_generated|cntr1|cmpr4         ; 22    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u4|u0|altshift_taps_component|auto_generated|cntr1               ; 2     ; 0              ; 0            ; 0              ; 11     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u4|u0|altshift_taps_component|auto_generated|altsyncram2         ; 49    ; 1              ; 0            ; 1              ; 24     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u4|u0|altshift_taps_component|auto_generated                     ; 14    ; 0              ; 0            ; 0              ; 36     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u4|u0                                                            ; 14    ; 0              ; 0            ; 0              ; 24     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u4                                                               ; 37    ; 0              ; 20           ; 0              ; 37     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u3                                                               ; 18    ; 0              ; 0            ; 0              ; 77     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u2                                                               ; 2     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u1                                                               ; 32    ; 0              ; 0            ; 0              ; 58     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst                                                                  ; 16    ; 39             ; 8            ; 39             ; 120    ; 39              ; 39            ; 39              ; 48    ; 0              ; 14           ; 0                ; 14                ;
++-----------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.ammdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.ammdb
new file mode 100644
index 0000000..8b8ff04
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.ammdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.bpm b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.bpm
new file mode 100644
index 0000000..430eafe
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.bpm
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.cdb
new file mode 100644
index 0000000..cd87d8e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.hdb
new file mode 100644
index 0000000..93377c7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.kpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.kpt
new file mode 100644
index 0000000..fd891ab
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.kpt
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.logdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.qmsg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.qmsg
new file mode 100644
index 0000000..c872e37
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.qmsg
@@ -0,0 +1,317 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1457454195984 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457454195989 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:23:15 2016 " "Processing started: Tue Mar 08 16:23:15 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457454195989 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1457454195989 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M " "Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1457454195989 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1457454199082 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "//icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel quartus/sobel.v 2 2 " "Found 2 design units, including 2 entities, in source file //icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel quartus/sobel.v" { { "Info" "ISGN_ENTITY_NAME" "1 sobel_core " "Found entity 1: sobel_core" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199223 ""} { "Info" "ISGN_ENTITY_NAME" "2 sobel " "Found entity 2: sobel" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1573 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199223 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199223 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/ps2.v 1 1 " "Found 1 design units, including 1 entities, in source file v/ps2.v" { { "Info" "ISGN_ENTITY_NAME" "1 ps2 " "Found entity 1: ps2" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199244 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199244 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/command.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/command.v" { { "Info" "ISGN_ENTITY_NAME" "1 command " "Found entity 1: command" {  } { { "Sdram_Control_4Port/command.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199278 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199278 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/control_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/control_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_interface " "Found entity 1: control_interface" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199311 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199311 ""}
+{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 sdr_data_path.v(68) " "Verilog HDL Expression warning at sdr_data_path.v(68): truncated literal to match 1 bits" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v" 68 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1457454199345 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdr_data_path.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/sdr_data_path.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdr_data_path " "Found entity 1: sdr_data_path" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199346 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199346 ""}
+{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "Sdram_Control_4Port Sdram_Control_4Port.v(90) " "Verilog Module Declaration warning at Sdram_Control_4Port.v(90): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"Sdram_Control_4Port\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 90 0 0 } }  } 0 10238 "Verilog Module Declaration warning at %2!s!: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454199374 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdram_control_4port.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_control_4port.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_Control_4Port " "Found entity 1: Sdram_Control_4Port" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199375 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199375 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdram_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_FIFO " "Found entity 1: Sdram_FIFO" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199396 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199396 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "V/async_receiver.v " "Can't analyze file -- file V/async_receiver.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1457454199748 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/ccd_capture.v 1 1 " "Found 1 design units, including 1 entities, in source file v/ccd_capture.v" { { "Info" "ISGN_ENTITY_NAME" "1 CCD_Capture " "Found entity 1: CCD_Capture" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199794 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199794 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/i2c_ccd_config.v 1 1 " "Found 1 design units, including 1 entities, in source file v/i2c_ccd_config.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_CCD_Config " "Found entity 1: I2C_CCD_Config" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199831 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199831 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/i2c_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file v/i2c_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_Controller " "Found entity 1: I2C_Controller" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199868 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199868 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/line_buffer.v 1 1 " "Found 1 design units, including 1 entities, in source file v/line_buffer.v" { { "Info" "ISGN_ENTITY_NAME" "1 Line_Buffer " "Found entity 1: Line_Buffer" {  } { { "V/Line_Buffer.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199901 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199901 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/raw2rgb.v 1 1 " "Found 1 design units, including 1 entities, in source file v/raw2rgb.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAW2RGB " "Found entity 1: RAW2RGB" {  } { { "V/RAW2RGB.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199926 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199926 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/reset_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file v/reset_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Found entity 1: Reset_Delay" {  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199958 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199958 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/sdram_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file v/sdram_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_pll " "Found entity 1: sdram_pll" {  } { { "V/sdram_pll.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454199987 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454199987 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/seg7_lut.v 1 1 " "Found 1 design units, including 1 entities, in source file v/seg7_lut.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT " "Found entity 1: SEG7_LUT" {  } { { "V/SEG7_LUT.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200009 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454200009 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/seg7_lut_8.v 1 1 " "Found 1 design units, including 1 entities, in source file v/seg7_lut_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT_8 " "Found entity 1: SEG7_LUT_8" {  } { { "V/SEG7_LUT_8.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200032 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454200032 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/vga_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file v/vga_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 VGA_Controller " "Found entity 1: VGA_Controller" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 13 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200072 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454200072 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de0_d5m.v 1 1 " "Found 1 design units, including 1 entities, in source file de0_d5m.v" { { "Info" "ISGN_ENTITY_NAME" "1 DE0_D5M " "Found entity 1: DE0_D5M" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200110 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454200110 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/top_de0_camera_mouse.bdf 1 1 " "Found 1 design units, including 1 entities, in source file v/top_de0_camera_mouse.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TOP_DE0_CAMERA_MOUSE " "Found entity 1: TOP_DE0_CAMERA_MOUSE" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200137 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454200137 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_mux.vhd 2 1 " "Found 2 design units, including 1 entities, in source file vga_mux.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vga_mux-SYN " "Found design unit 1: vga_mux-SYN" {  } { { "vga_mux.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 55 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200772 ""} { "Info" "ISGN_ENTITY_NAME" "1 vga_mux " "Found entity 1: vga_mux" {  } { { "vga_mux.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200772 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454200772 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catapult_ip/mouse/rtl_mgc_ioport_v2001.v 7 7 " "Found 7 design units, including 7 entities, in source file catapult_ip/mouse/rtl_mgc_ioport_v2001.v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_out_reg_pos " "Found entity 1: mgc_out_reg_pos" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200795 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_out_reg_neg " "Found entity 2: mgc_out_reg_neg" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 68 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200795 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_out_reg " "Found entity 3: mgc_out_reg" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 133 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200795 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_out_buf_wait " "Found entity 4: mgc_out_buf_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 210 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200795 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_fifo_wait " "Found entity 5: mgc_out_fifo_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 296 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200795 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_fifo_wait_core " "Found entity 6: mgc_out_fifo_wait_core" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 353 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200795 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_pipe " "Found entity 7: mgc_pipe" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 644 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200795 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454200795 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catapult_ip/mouse/rtl_mgc_ioport.v 20 20 " "Found 20 design units, including 20 entities, in source file catapult_ip/mouse/rtl_mgc_ioport.v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_in_wire " "Found entity 1: mgc_in_wire" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 13 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_in_wire_en " "Found entity 2: mgc_in_wire_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_in_wire_wait " "Found entity 3: mgc_in_wire_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_chan_in " "Found entity 4: mgc_chan_in" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 72 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_stdreg " "Found entity 5: mgc_out_stdreg" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 109 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_stdreg_en " "Found entity 6: mgc_out_stdreg_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 125 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_out_stdreg_wait " "Found entity 7: mgc_out_stdreg_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 145 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "8 mgc_out_prereg_en " "Found entity 8: mgc_out_prereg_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 169 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "9 mgc_inout_stdreg_en " "Found entity 9: mgc_inout_stdreg_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 191 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "10 hid_tribuf " "Found entity 10: hid_tribuf" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 217 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "11 mgc_inout_stdreg_wait " "Found entity 11: mgc_inout_stdreg_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 229 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "12 mgc_inout_buf_wait " "Found entity 12: mgc_inout_buf_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 269 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "13 mgc_inout_fifo_wait " "Found entity 13: mgc_inout_fifo_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 339 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "14 mgc_io_sync " "Found entity 14: mgc_io_sync" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 419 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "15 mgc_bsync_rdy " "Found entity 15: mgc_bsync_rdy" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 428 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "16 mgc_bsync_vld " "Found entity 16: mgc_bsync_vld" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 443 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "17 mgc_bsync_rv " "Found entity 17: mgc_bsync_rv" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 458 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "18 mgc_sync " "Found entity 18: mgc_sync" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 479 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "19 funccall_inout " "Found entity 19: funccall_inout" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 498 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""} { "Info" "ISGN_ENTITY_NAME" "20 modulario_en_in " "Found entity 20: modulario_en_in" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 526 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454200815 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catapult_ip/mouse/rtl.v 2 2 " "Found 2 design units, including 2 entities, in source file catapult_ip/mouse/rtl.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_mouse_square_core " "Found entity 1: vga_mouse_square_core" {  } { { "catapult_ip/mouse/rtl.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200840 ""} { "Info" "ISGN_ENTITY_NAME" "2 vga_mouse_square " "Found entity 2: vga_mouse_square" {  } { { "catapult_ip/mouse/rtl.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 110 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454200840 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454200840 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "TOP_DE0_CAMERA_MOUSE " "Elaborating entity \"TOP_DE0_CAMERA_MOUSE\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1457454203792 ""}
+{ "Warning" "WGDFX_NO_SUPERSET_FOUND" "" "No superset bus at connection" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 912 1008 1120 928 "MOUSE_X\[1..0\]" "" } { 928 1008 1120 944 "MOUSE_Y\[1..0\]" "" } { 928 1008 1008 944 "" "" } { 944 1008 1008 952 "" "" } } } }  } 0 275002 "No superset bus at connection" 0 0 "Quartus II" 0 -1 1457454203807 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DE0_D5M DE0_D5M:inst " "Elaborating entity \"DE0_D5M\" for hierarchy \"DE0_D5M:inst\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454203837 ""}
+{ "Critical Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "VGA_R DE0_D5M.v(118) " "Verilog HDL warning at DE0_D5M.v(118): the port and data declarations for array port \"VGA_R\" do not specify the same range for each dimension" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 118 0 0 } }  } 1 10169 "Verilog HDL warning at %2!s!: the port and data declarations for array port \"%1!s!\" do not specify the same range for each dimension" 0 0 "Quartus II" 0 -1 1457454203856 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_HDL_SEE_DECLARATION" "VGA_R DE0_D5M.v(166) " "HDL warning at DE0_D5M.v(166): see declaration for object \"VGA_R\"" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 166 0 0 } }  } 0 10359 "HDL warning at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454203856 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Critical Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "VGA_G DE0_D5M.v(119) " "Verilog HDL warning at DE0_D5M.v(119): the port and data declarations for array port \"VGA_G\" do not specify the same range for each dimension" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 119 0 0 } }  } 1 10169 "Verilog HDL warning at %2!s!: the port and data declarations for array port \"%1!s!\" do not specify the same range for each dimension" 0 0 "Quartus II" 0 -1 1457454203856 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_HDL_SEE_DECLARATION" "VGA_G DE0_D5M.v(167) " "HDL warning at DE0_D5M.v(167): see declaration for object \"VGA_G\"" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 167 0 0 } }  } 0 10359 "HDL warning at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454203857 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Critical Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "VGA_B DE0_D5M.v(120) " "Verilog HDL warning at DE0_D5M.v(120): the port and data declarations for array port \"VGA_B\" do not specify the same range for each dimension" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 120 0 0 } }  } 1 10169 "Verilog HDL warning at %2!s!: the port and data declarations for array port \"%1!s!\" do not specify the same range for each dimension" 0 0 "Quartus II" 0 -1 1457454203858 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_HDL_SEE_DECLARATION" "VGA_B DE0_D5M.v(168) " "HDL warning at DE0_D5M.v(168): see declaration for object \"VGA_B\"" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 168 0 0 } }  } 0 10359 "HDL warning at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454203858 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "16 10 DE0_D5M.v(197) " "Verilog HDL assignment warning at DE0_D5M.v(197): truncated value with size 16 to match size of target (10)" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 197 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454203858 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 DE0_D5M.v(202) " "Verilog HDL assignment warning at DE0_D5M.v(202): truncated value with size 32 to match size of target (2)" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454203858 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1_CLKOUT\[1\] DE0_D5M.v(128) " "Output port \"GPIO_1_CLKOUT\[1\]\" at DE0_D5M.v(128) has no driver" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 128 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1457454203858 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA_Controller DE0_D5M:inst\|VGA_Controller:u1 " "Elaborating entity \"VGA_Controller\" for hierarchy \"DE0_D5M:inst\|VGA_Controller:u1\"" {  } { { "DE0_D5M.v" "u1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 253 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454203888 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(70) " "Verilog HDL assignment warning at VGA_Controller.v(70): truncated value with size 32 to match size of target (10)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454203899 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(73) " "Verilog HDL assignment warning at VGA_Controller.v(73): truncated value with size 32 to match size of target (10)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454203901 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(76) " "Verilog HDL assignment warning at VGA_Controller.v(76): truncated value with size 32 to match size of target (10)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454203901 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 VGA_Controller.v(115) " "Verilog HDL assignment warning at VGA_Controller.v(115): truncated value with size 32 to match size of target (12)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 115 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454203901 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 VGA_Controller.v(146) " "Verilog HDL assignment warning at VGA_Controller.v(146): truncated value with size 32 to match size of target (12)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 146 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454203901 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay DE0_D5M:inst\|Reset_Delay:u2 " "Elaborating entity \"Reset_Delay\" for hierarchy \"DE0_D5M:inst\|Reset_Delay:u2\"" {  } { { "DE0_D5M.v" "u2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 262 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454203934 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CCD_Capture DE0_D5M:inst\|CCD_Capture:u3 " "Elaborating entity \"CCD_Capture\" for hierarchy \"DE0_D5M:inst\|CCD_Capture:u3\"" {  } { { "DE0_D5M.v" "u3" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 277 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454203967 ""}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ifval_fedge CCD_Capture.v(162) " "Verilog HDL or VHDL warning at CCD_Capture.v(162): object \"ifval_fedge\" assigned a value but never read" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 162 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1457454203977 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "y_cnt_d CCD_Capture.v(163) " "Verilog HDL or VHDL warning at CCD_Capture.v(163): object \"y_cnt_d\" assigned a value but never read" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 163 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1457454203979 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 CCD_Capture.v(123) " "Verilog HDL assignment warning at CCD_Capture.v(123): truncated value with size 32 to match size of target (16)" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 123 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454203979 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 CCD_Capture.v(127) " "Verilog HDL assignment warning at CCD_Capture.v(127): truncated value with size 32 to match size of target (16)" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 127 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454203979 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CCD_Capture.v(183) " "Verilog HDL assignment warning at CCD_Capture.v(183): truncated value with size 32 to match size of target (1)" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 183 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454203979 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAW2RGB DE0_D5M:inst\|RAW2RGB:u4 " "Elaborating entity \"RAW2RGB\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\"" {  } { { "DE0_D5M.v" "u4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 290 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454204007 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Line_Buffer DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0 " "Elaborating entity \"Line_Buffer\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\"" {  } { { "V/RAW2RGB.v" "u0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v" 83 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454204106 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift_taps DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Elaborating entity \"altshift_taps\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\"" {  } { { "V/Line_Buffer.v" "altshift_taps_component" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 67 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454204372 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Elaborated megafunction instantiation \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\"" {  } { { "V/Line_Buffer.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 67 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454204385 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Instantiated megafunction \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altshift_taps " "Parameter \"lpm_type\" = \"altshift_taps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454204394 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_taps 2 " "Parameter \"number_of_taps\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454204394 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "tap_distance 1280 " "Parameter \"tap_distance\" = \"1280\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454204394 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 12 " "Parameter \"width\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454204394 ""}  } { { "V/Line_Buffer.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 67 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454204394 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_rnn.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/shift_taps_rnn.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_rnn " "Found entity 1: shift_taps_rnn" {  } { { "db/shift_taps_rnn.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454204558 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454204558 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_taps_rnn DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated " "Elaborating entity \"shift_taps_rnn\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\"" {  } { { "altshift_taps.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454204575 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_lp81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_lp81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_lp81 " "Found entity 1: altsyncram_lp81" {  } { { "db/altsyncram_lp81.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_lp81.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454204768 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454204768 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_lp81 DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|altsyncram_lp81:altsyncram2 " "Elaborating entity \"altsyncram_lp81\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|altsyncram_lp81:altsyncram2\"" {  } { { "db/shift_taps_rnn.tdf" "altsyncram2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf" 35 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454204784 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_cuf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_cuf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_cuf " "Found entity 1: cntr_cuf" {  } { { "db/cntr_cuf.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454204967 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454204967 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_cuf DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1 " "Elaborating entity \"cntr_cuf\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1\"" {  } { { "db/shift_taps_rnn.tdf" "cntr1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf" 36 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454204985 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_vgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_vgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_vgc " "Found entity 1: cmpr_vgc" {  } { { "db/cmpr_vgc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_vgc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454205133 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454205133 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_vgc DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1\|cmpr_vgc:cmpr4 " "Elaborating entity \"cmpr_vgc\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1\|cmpr_vgc:cmpr4\"" {  } { { "db/cntr_cuf.tdf" "cmpr4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf" 90 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205150 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT_8 DE0_D5M:inst\|SEG7_LUT_8:u5 " "Elaborating entity \"SEG7_LUT_8\" for hierarchy \"DE0_D5M:inst\|SEG7_LUT_8:u5\"" {  } { { "DE0_D5M.v" "u5" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 302 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205202 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT DE0_D5M:inst\|SEG7_LUT_8:u5\|SEG7_LUT:u0 " "Elaborating entity \"SEG7_LUT\" for hierarchy \"DE0_D5M:inst\|SEG7_LUT_8:u5\|SEG7_LUT:u0\"" {  } { { "V/SEG7_LUT_8.v" "u0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v" 47 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205241 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_pll DE0_D5M:inst\|sdram_pll:u6 " "Elaborating entity \"sdram_pll\" for hierarchy \"DE0_D5M:inst\|sdram_pll:u6\"" {  } { { "DE0_D5M.v" "u6" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 308 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205452 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\"" {  } { { "V/sdram_pll.v" "altpll_component" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205634 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component " "Elaborated megafunction instantiation \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\"" {  } { { "V/sdram_pll.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454205650 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component " "Instantiated megafunction \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2 " "Parameter \"clk0_divide_by\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5 " "Parameter \"clk0_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 2 " "Parameter \"clk1_divide_by\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 5 " "Parameter \"clk1_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift -2600 " "Parameter \"clk1_phase_shift\" = \"-2600\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone III " "Parameter \"intended_device_family\" = \"Cyclone III\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205651 ""}  } { { "V/sdram_pll.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454205651 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altpll_9ee2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altpll_9ee2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll_9ee2 " "Found entity 1: altpll_9ee2" {  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454205842 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454205842 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_9ee2 DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated " "Elaborating entity \"altpll_9ee2\" for hierarchy \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205879 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Sdram_Control_4Port DE0_D5M:inst\|Sdram_Control_4Port:u7 " "Elaborating entity \"Sdram_Control_4Port\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\"" {  } { { "DE0_D5M.v" "u7" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 364 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454205975 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Sdram_Control_4Port.v(385) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(385): truncated value with size 32 to match size of target (10)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 385 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454206014 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(431) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(431): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 431 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454206014 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(432) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(432): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 432 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454206014 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(433) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(433): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 433 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454206016 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(434) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(434): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 434 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454206016 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rWR1_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rWR1_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457454206016 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rWR2_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rWR2_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457454206017 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rRD1_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rRD1_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457454206017 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rRD2_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rRD2_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457454206019 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206019 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206019 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206019 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206019 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206019 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206019 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206021 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206021 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206021 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206021 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206021 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206021 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206022 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206023 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206023 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206023 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206023 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206023 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206024 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206024 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206026 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206026 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206027 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206027 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206027 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206027 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206027 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206027 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206029 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206029 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206029 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206029 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206029 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206029 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206029 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206031 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206032 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206032 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206032 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206032 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206032 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206032 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206034 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206034 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206034 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206034 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206034 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206034 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206035 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206036 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206036 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206036 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206036 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206037 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206037 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206037 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206037 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206040 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206040 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206040 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206040 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206040 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206041 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206041 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206044 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206044 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206044 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206044 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206044 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206045 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206045 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206047 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206047 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206048 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206048 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206048 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206048 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206048 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206048 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206049 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206050 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206050 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206050 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206050 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206050 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206050 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206052 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206052 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206052 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206053 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206053 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457454206053 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_interface DE0_D5M:inst\|Sdram_Control_4Port:u7\|control_interface:control1 " "Elaborating entity \"control_interface\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|control_interface:control1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "control1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 237 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206093 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(162) " "Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 162 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454206121 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(167) " "Verilog HDL assignment warning at control_interface.v(167): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 167 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454206121 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(192) " "Verilog HDL assignment warning at control_interface.v(192): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 192 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454206121 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "command DE0_D5M:inst\|Sdram_Control_4Port:u7\|command:command1 " "Elaborating entity \"command\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|command:command1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "command1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 263 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206158 ""}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe_shift command.v(275) " "Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe_shift\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457454206173 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe1 command.v(275) " "Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe1\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457454206173 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe2 command.v(275) " "Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe2\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457454206175 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdr_data_path DE0_D5M:inst\|Sdram_Control_4Port:u7\|sdr_data_path:data_path1 " "Elaborating entity \"sdr_data_path\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|sdr_data_path:data_path1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "data_path1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 272 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206214 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 sdr_data_path.v(68) " "Verilog HDL assignment warning at sdr_data_path.v(68): truncated value with size 32 to match size of target (2)" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v" 68 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454206224 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Sdram_FIFO DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1 " "Elaborating entity \"Sdram_FIFO\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "write_fifo1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 283 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206354 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Elaborating entity \"dcfifo\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\"" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "dcfifo_component" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206704 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Elaborated megafunction instantiation \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\"" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454206712 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Instantiated megafunction \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register OFF " "Parameter \"add_ram_output_register\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clocks_are_synchronized FALSE " "Parameter \"clocks_are_synchronized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone " "Parameter \"intended_device_family\" = \"Cyclone\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=M4K " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=M4K\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 512 " "Parameter \"lpm_numwords\" = \"512\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type dcfifo " "Parameter \"lpm_type\" = \"dcfifo\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 16 " "Parameter \"lpm_width\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 9 " "Parameter \"lpm_widthu\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206715 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206715 ""}  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454206715 ""}
+{ "Warning" "WTDFX_ASSERTION" "Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 " "Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2" {  } { { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 161 2 0 } }  } 0 287001 "Assertion warning: %1!s!" 0 0 "Quartus II" 0 -1 1457454206916 ""}
+{ "Warning" "WTDFX_ASSERTION" "Device family Cyclone III does not have M4K blocks -- using available memory blocks " "Assertion warning: Device family Cyclone III does not have M4K blocks -- using available memory blocks" {  } { { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 164 2 0 } }  } 0 287001 "Assertion warning: %1!s!" 0 0 "Quartus II" 0 -1 1457454206917 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dcfifo_v5o1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dcfifo_v5o1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo_v5o1 " "Found entity 1: dcfifo_v5o1" {  } { { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 40 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454206920 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454206920 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo_v5o1 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated " "Elaborating entity \"dcfifo_v5o1\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\"" {  } { { "dcfifo.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454206943 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_gray2bin_tgb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_gray2bin_tgb " "Found entity 1: a_gray2bin_tgb" {  } { { "db/a_gray2bin_tgb.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_gray2bin_tgb.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454207056 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454207056 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_gray2bin_tgb DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_gray2bin_tgb:rdptr_g_gray2bin " "Elaborating entity \"a_gray2bin_tgb\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_gray2bin_tgb:rdptr_g_gray2bin\"" {  } { { "db/dcfifo_v5o1.tdf" "rdptr_g_gray2bin" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 55 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454207074 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_s57.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_s57 " "Found entity 1: a_graycounter_s57" {  } { { "db/a_graycounter_s57.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454207302 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454207302 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_s57 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_s57:rdptr_g1p " "Elaborating entity \"a_graycounter_s57\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_s57:rdptr_g1p\"" {  } { { "db/dcfifo_v5o1.tdf" "rdptr_g1p" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 59 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454207317 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_ojc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_ojc " "Found entity 1: a_graycounter_ojc" {  } { { "db/a_graycounter_ojc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454207487 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454207487 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_ojc DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_ojc:wrptr_g1p " "Elaborating entity \"a_graycounter_ojc\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_ojc:wrptr_g1p\"" {  } { { "db/dcfifo_v5o1.tdf" "wrptr_g1p" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 60 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454207512 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_de51.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_de51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_de51 " "Found entity 1: altsyncram_de51" {  } { { "db/altsyncram_de51.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454207683 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454207683 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_de51 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram " "Elaborating entity \"altsyncram_de51\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\"" {  } { { "db/dcfifo_v5o1.tdf" "fifo_ram" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 61 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454207700 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_oe9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_oe9 " "Found entity 1: dffpipe_oe9" {  } { { "db/dffpipe_oe9.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_oe9.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454207800 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454207800 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_oe9 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|dffpipe_oe9:rs_brp " "Elaborating entity \"dffpipe_oe9\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|dffpipe_oe9:rs_brp\"" {  } { { "db/dcfifo_v5o1.tdf" "rs_brp" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 68 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454207818 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_qld.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_qld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_qld " "Found entity 1: alt_synch_pipe_qld" {  } { { "db/alt_synch_pipe_qld.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454207959 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454207959 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_qld DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp " "Elaborating entity \"alt_synch_pipe_qld\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp\"" {  } { { "db/dcfifo_v5o1.tdf" "rs_dgwp" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 70 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454207983 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_pe9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_pe9 " "Found entity 1: dffpipe_pe9" {  } { { "db/dffpipe_pe9.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_pe9.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454208125 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454208125 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_pe9 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp\|dffpipe_pe9:dffpipe13 " "Elaborating entity \"dffpipe_pe9\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp\|dffpipe_pe9:dffpipe13\"" {  } { { "db/alt_synch_pipe_qld.tdf" "dffpipe13" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf" 34 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454208145 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_rld.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_rld " "Found entity 1: alt_synch_pipe_rld" {  } { { "db/alt_synch_pipe_rld.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454208324 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454208324 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_rld DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp " "Elaborating entity \"alt_synch_pipe_rld\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp\"" {  } { { "db/dcfifo_v5o1.tdf" "ws_dgrp" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 73 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454208346 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_qe9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_qe9 " "Found entity 1: dffpipe_qe9" {  } { { "db/dffpipe_qe9.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_qe9.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454208461 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454208461 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_qe9 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp\|dffpipe_qe9:dffpipe16 " "Elaborating entity \"dffpipe_qe9\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp\|dffpipe_qe9:dffpipe16\"" {  } { { "db/alt_synch_pipe_rld.tdf" "dffpipe16" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf" 34 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454208478 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_e66.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_e66.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_e66 " "Found entity 1: cmpr_e66" {  } { { "db/cmpr_e66.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_e66.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454208650 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454208650 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_e66 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|cmpr_e66:rdempty_eq_comp " "Elaborating entity \"cmpr_e66\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|cmpr_e66:rdempty_eq_comp\"" {  } { { "db/dcfifo_v5o1.tdf" "rdempty_eq_comp" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 80 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454208666 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_CCD_Config DE0_D5M:inst\|I2C_CCD_Config:u8 " "Elaborating entity \"I2C_CCD_Config\" for hierarchy \"DE0_D5M:inst\|I2C_CCD_Config:u8\"" {  } { { "DE0_D5M.v" "u8" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 377 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454210393 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(126) " "Verilog HDL assignment warning at I2C_CCD_Config.v(126): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 126 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210412 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(127) " "Verilog HDL assignment warning at I2C_CCD_Config.v(127): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 127 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210413 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 25 I2C_CCD_Config.v(160) " "Verilog HDL assignment warning at I2C_CCD_Config.v(160): truncated value with size 32 to match size of target (25)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 160 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210414 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(165) " "Verilog HDL assignment warning at I2C_CCD_Config.v(165): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210414 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 I2C_CCD_Config.v(190) " "Verilog HDL assignment warning at I2C_CCD_Config.v(190): truncated value with size 32 to match size of target (16)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 190 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210414 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 I2C_CCD_Config.v(240) " "Verilog HDL assignment warning at I2C_CCD_Config.v(240): truncated value with size 32 to match size of target (6)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 240 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210414 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_Controller DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0 " "Elaborating entity \"I2C_Controller\" for hierarchy \"DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0\"" {  } { { "V/I2C_CCD_Config.v" "u0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 207 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454210441 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(70) " "Verilog HDL assignment warning at I2C_Controller.v(70): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210457 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(69) " "Verilog HDL assignment warning at I2C_Controller.v(69): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 69 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210458 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 I2C_Controller.v(82) " "Verilog HDL assignment warning at I2C_Controller.v(82): truncated value with size 32 to match size of target (7)" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 82 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210458 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2 ps2:inst6 " "Elaborating entity \"ps2\" for hierarchy \"ps2:inst6\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst6" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 704 760 968 944 "inst6" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454210489 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 ps2.v(120) " "Verilog HDL assignment warning at ps2.v(120): truncated value with size 32 to match size of target (9)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 120 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210503 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 ps2.v(188) " "Verilog HDL assignment warning at ps2.v(188): truncated value with size 32 to match size of target (8)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 188 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210503 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2.v(195) " "Verilog HDL assignment warning at ps2.v(195): truncated value with size 32 to match size of target (1)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 195 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210504 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 ps2.v(201) " "Verilog HDL assignment warning at ps2.v(201): truncated value with size 32 to match size of target (6)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 201 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210504 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ps2.v(229) " "Verilog HDL assignment warning at ps2.v(229): truncated value with size 32 to match size of target (4)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 229 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210505 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ps2.v(245) " "Verilog HDL assignment warning at ps2.v(245): truncated value with size 32 to match size of target (4)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 245 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457454210505 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_mux vga_mux:inst10 " "Elaborating entity \"vga_mux\" for hierarchy \"vga_mux:inst10\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst10" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1056 2304 2448 1168 "inst10" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454210619 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_MUX vga_mux:inst10\|LPM_MUX:LPM_MUX_component " "Elaborating entity \"LPM_MUX\" for hierarchy \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\"" {  } { { "vga_mux.vhd" "LPM_MUX_component" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 193 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454210777 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "vga_mux:inst10\|LPM_MUX:LPM_MUX_component " "Elaborated megafunction instantiation \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\"" {  } { { "vga_mux.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 193 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454210787 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "vga_mux:inst10\|LPM_MUX:LPM_MUX_component " "Instantiated megafunction \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 30 " "Parameter \"LPM_WIDTH\" = \"30\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454210787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 4 " "Parameter \"LPM_SIZE\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454210787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 2 " "Parameter \"LPM_WIDTHS\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454210787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 0 " "Parameter \"LPM_PIPELINE\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454210787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_MUX " "Parameter \"LPM_TYPE\" = \"LPM_MUX\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454210787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT UNUSED " "Parameter \"LPM_HINT\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454210787 ""}  } { { "vga_mux.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 193 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454210787 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_u7e.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_u7e.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_u7e " "Found entity 1: mux_u7e" {  } { { "db/mux_u7e.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/mux_u7e.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454210916 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454210916 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_u7e vga_mux:inst10\|LPM_MUX:LPM_MUX_component\|mux_u7e:auto_generated " "Elaborating entity \"mux_u7e\" for hierarchy \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\|mux_u7e:auto_generated\"" {  } { { "lpm_mux.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454210933 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_mouse_square vga_mouse_square:vga_mouse_catapult_inst " "Elaborating entity \"vga_mouse_square\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "vga_mouse_catapult_inst" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 848 1672 1960 1024 "vga_mouse_catapult_inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454210978 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:vga_xy_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:vga_xy_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "vga_xy_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 137 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211009 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:mouse_xy_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:mouse_xy_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "mouse_xy_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 142 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211037 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:cursor_size_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:cursor_size_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "cursor_size_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 147 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211063 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:video_in_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:video_in_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "video_in_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 152 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211092 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_out_stdreg vga_mouse_square:vga_mouse_catapult_inst\|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg " "Elaborating entity \"mgc_out_stdreg\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg\"" {  } { { "catapult_ip/mouse/rtl.v" "video_out_rsc_mgc_out_stdreg" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 157 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211129 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_mouse_square_core vga_mouse_square:vga_mouse_catapult_inst\|vga_mouse_square_core:vga_mouse_square_core_inst " "Elaborating entity \"vga_mouse_square_core\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|vga_mouse_square_core:vga_mouse_square_core_inst\"" {  } { { "catapult_ip/mouse/rtl.v" "vga_mouse_square_core_inst" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 167 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211158 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sobel sobel:inst1 " "Elaborating entity \"sobel\" for hierarchy \"sobel:inst1\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst1" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1080 1704 1944 1192 "inst1" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211187 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire sobel:inst1\|mgc_in_wire:vin_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"sobel:inst1\|mgc_in_wire:vin_rsc_mgc_in_wire\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "vin_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1593 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211278 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_out_stdreg sobel:inst1\|mgc_out_stdreg:vout_rsc_mgc_out_stdreg " "Elaborating entity \"mgc_out_stdreg\" for hierarchy \"sobel:inst1\|mgc_out_stdreg:vout_rsc_mgc_out_stdreg\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "vout_rsc_mgc_out_stdreg" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1598 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211305 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sobel_core sobel:inst1\|sobel_core:sobel_core_inst " "Elaborating entity \"sobel_core\" for hierarchy \"sobel:inst1\|sobel_core:sobel_core_inst\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "sobel_core_inst" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 1605 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211340 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift_taps altshift_taps:fifo_inst2 " "Elaborating entity \"altshift_taps\" for hierarchy \"altshift_taps:fifo_inst2\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "fifo_inst2" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211944 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "altshift_taps:fifo_inst2 " "Elaborated megafunction instantiation \"altshift_taps:fifo_inst2\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454211957 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "altshift_taps:fifo_inst2 " "Instantiated megafunction \"altshift_taps:fifo_inst2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMBER_OF_TAPS 3 " "Parameter \"NUMBER_OF_TAPS\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211957 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "TAP_DISTANCE 800 " "Parameter \"TAP_DISTANCE\" = \"800\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211957 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH 30 " "Parameter \"WIDTH\" = \"30\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454211957 ""}  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454211957 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_jpm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/shift_taps_jpm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_jpm " "Found entity 1: shift_taps_jpm" {  } { { "db/shift_taps_jpm.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_jpm.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454212094 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454212094 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_taps_jpm altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated " "Elaborating entity \"shift_taps_jpm\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\"" {  } { { "altshift_taps.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454212111 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_5n81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_5n81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_5n81 " "Found entity 1: altsyncram_5n81" {  } { { "db/altsyncram_5n81.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_5n81.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454212322 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454212322 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_5n81 altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|altsyncram_5n81:altsyncram2 " "Elaborating entity \"altsyncram_5n81\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|altsyncram_5n81:altsyncram2\"" {  } { { "db/shift_taps_jpm.tdf" "altsyncram2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_jpm.tdf" 35 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454212348 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1tf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1tf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1tf " "Found entity 1: cntr_1tf" {  } { { "db/cntr_1tf.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454212539 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454212539 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1tf altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|cntr_1tf:cntr1 " "Elaborating entity \"cntr_1tf\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|cntr_1tf:cntr1\"" {  } { { "db/shift_taps_jpm.tdf" "cntr1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_jpm.tdf" 36 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454212557 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ugc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ugc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ugc " "Found entity 1: cmpr_ugc" {  } { { "db/cmpr_ugc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_ugc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457454212737 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457454212737 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ugc altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|cntr_1tf:cntr1\|cmpr_ugc:cmpr4 " "Elaborating entity \"cmpr_ugc\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|cntr_1tf:cntr1\|cmpr_ugc:cmpr4\"" {  } { { "db/cntr_1tf.tdf" "cmpr4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf" 85 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454212755 ""}
+{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\] " "Synthesized away node \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\]\"" {  } { { "db/altsyncram_de51.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf" 521 2 0 } } { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 61 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 319 0 0 } } { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 364 0 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454213774 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\] " "Synthesized away node \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\]\"" {  } { { "db/altsyncram_de51.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf" 521 2 0 } } { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 61 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 308 0 0 } } { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 364 0 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454213774 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Quartus II" 0 -1 1457454213774 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Quartus II" 0 -1 1457454213774 ""}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "9 " "Inferred 9 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult0\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454216100 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult1\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454216100 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult7 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult7\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult7" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454216100 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult5 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult5\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult5" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454216100 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult2 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult2\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454216100 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult6 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult6\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult6" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454216100 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult3 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult3\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult3" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454216100 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult4 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult4\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454216100 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult8 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult8\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult8" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 784 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454216100 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1457454216100 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454216286 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216287 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216287 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 11 " "Parameter \"LPM_WIDTHP\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216287 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 11 " "Parameter \"LPM_WIDTHR\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216287 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216287 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216287 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216287 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216287 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216287 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454216287 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216504 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216643 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0\|altshift:external_latency_ffs sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult0\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216763 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454216801 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 3 " "Parameter \"LPM_WIDTHA\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216802 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 6 " "Parameter \"LPM_WIDTHB\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216802 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 9 " "Parameter \"LPM_WIDTHP\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216802 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 9 " "Parameter \"LPM_WIDTHR\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216802 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216802 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216802 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216802 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216802 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216802 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454216802 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216817 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216835 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1\|altshift:external_latency_ffs sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult1\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 188 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216847 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454216942 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216942 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 13 " "Parameter \"LPM_WIDTHB\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216942 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 15 " "Parameter \"LPM_WIDTHP\" = \"15\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216942 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 15 " "Parameter \"LPM_WIDTHR\" = \"15\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216942 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216942 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216942 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216942 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216942 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216942 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454216942 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454216987 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217028 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7\|altshift:external_latency_ffs sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult7\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 615 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217056 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454217145 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217146 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217146 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 13 " "Parameter \"LPM_WIDTHP\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217146 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 13 " "Parameter \"LPM_WIDTHR\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217146 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217146 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217146 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217146 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217146 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217146 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454217146 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217211 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217268 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5\|altshift:external_latency_ffs sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult5\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 605 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217326 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454217435 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217437 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 14 " "Parameter \"LPM_WIDTHB\" = \"14\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217437 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 16 " "Parameter \"LPM_WIDTHP\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217437 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 16 " "Parameter \"LPM_WIDTHR\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217437 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217437 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217437 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217437 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217437 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217437 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454217437 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217536 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217596 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|altshift:external_latency_ffs sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 412 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217653 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454217761 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 3 " "Parameter \"LPM_WIDTHA\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 7 " "Parameter \"LPM_WIDTHB\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 10 " "Parameter \"LPM_WIDTHP\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 10 " "Parameter \"LPM_WIDTHR\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217762 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217762 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454217762 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217858 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217931 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6\|altshift:external_latency_ffs sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult6\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 612 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454217985 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult3\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454218090 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218090 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 5 " "Parameter \"LPM_WIDTHB\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218090 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 9 " "Parameter \"LPM_WIDTHP\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218090 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 9 " "Parameter \"LPM_WIDTHR\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218090 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218090 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218090 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218090 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218090 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218090 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454218090 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult3\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218143 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult3 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult3\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult3\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 521 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218176 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult4\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454218296 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult4\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218296 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 7 " "Parameter \"LPM_WIDTHB\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218296 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 11 " "Parameter \"LPM_WIDTHP\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218296 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 11 " "Parameter \"LPM_WIDTHR\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218296 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218296 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218296 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218296 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218296 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218296 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457454218296 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult4\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218385 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult4 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult4\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult4\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 601 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457454218449 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "10 " "10 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1457454219515 ""}
+{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[20\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[20\]\" and its non-tri-state driver." {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[14\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[14\]\" and its non-tri-state driver." {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "Quartus II" 0 -1 1457454219701 ""}  } {  } 0 13034 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "Quartus II" 0 -1 1457454219701 ""}
+{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457454219701 ""}  } {  } 0 13039 "The following bidir pins have no drivers" 0 0 "Quartus II" 0 -1 1457454219701 ""}
+{ "Warning" "WMLS_OPT_REPLACED_VCC_OR_GND_WITH_TRI_HDR" "" "The following tri-state nodes are fed by constants" { { "Warning" "WMLS_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[15\] VCC pin " "The pin \"GPIO_1\[15\]\" is fed by VCC" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13033 "The %3!s! \"%1!s!\" is fed by %2!s!" 0 0 "Quartus II" 0 -1 1457454219709 ""}  } {  } 0 13032 "The following tri-state nodes are fed by constants" 0 0 "Quartus II" 0 -1 1457454219709 ""}
+{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "db/a_graycounter_s57.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf" 32 2 0 } } { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 64 -1 0 } } { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 79 -1 0 } } { "db/a_graycounter_ojc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf" 32 2 0 } } { "db/a_graycounter_s57.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf" 45 2 0 } } { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 63 -1 0 } } { "db/a_graycounter_ojc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf" 45 2 0 } } { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 59 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1457454219846 ""}
+{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1457454219851 ""}
+{ "Warning" "WMLS_MLS_ENABLED_OE" "" "TRI or OPNDRN buffers permanently enabled" { { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1~synth " "Node \"GPIO_1~synth\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454221163 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1~synth " "Node \"GPIO_1~synth\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454221163 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1~synth " "Node \"GPIO_1~synth\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454221163 ""}  } {  } 0 13009 "TRI or OPNDRN buffers permanently enabled" 0 0 "Quartus II" 0 -1 1457454221163 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 344 1144 1320 360 "DRAM_CKE" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457454221181 "|TOP_DE0_CAMERA_MOUSE|DRAM_CKE"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1_CLKOUT\[1\] GND " "Pin \"GPIO_1_CLKOUT\[1\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 504 1144 1354 520 "GPIO_1_CLKOUT\[1..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457454221181 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKOUT[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[9\] GND " "Pin \"LEDG\[9\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457454221181 "|TOP_DE0_CAMERA_MOUSE|LEDG[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[8\] GND " "Pin \"LEDG\[8\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457454221181 "|TOP_DE0_CAMERA_MOUSE|LEDG[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[7\] GND " "Pin \"LEDG\[7\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457454221181 "|TOP_DE0_CAMERA_MOUSE|LEDG[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[6\] GND " "Pin \"LEDG\[6\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457454221181 "|TOP_DE0_CAMERA_MOUSE|LEDG[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[5\] GND " "Pin \"LEDG\[5\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457454221181 "|TOP_DE0_CAMERA_MOUSE|LEDG[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[4\] GND " "Pin \"LEDG\[4\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457454221181 "|TOP_DE0_CAMERA_MOUSE|LEDG[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[3\] GND " "Pin \"LEDG\[3\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457454221181 "|TOP_DE0_CAMERA_MOUSE|LEDG[3]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1457454221181 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1457454221512 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "29 " "29 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1457454222856 ""}
+{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "sobel:inst1\|sobel_core:sobel_core_inst\|Add6~4 " "Logic cell \"sobel:inst1\|sobel_core:sobel_core_inst\|Add6~4\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Add6~4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454222883 ""} { "Info" "ISCL_SCL_CELL_NAME" "sobel:inst1\|sobel_core:sobel_core_inst\|Add6~6 " "Logic cell \"sobel:inst1\|sobel_core:sobel_core_inst\|Add6~6\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Add6~6" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 187 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454222883 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Quartus II" 0 -1 1457454222883 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1457454228614 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454228614 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_1_CLKIN\[1\] " "No output dependent on input pin \"GPIO_1_CLKIN\[1\]\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454229473 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454229473 "|TOP_DE0_CAMERA_MOUSE|SW[9]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457454229473 "|TOP_DE0_CAMERA_MOUSE|SW[8]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1457454229473 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "4199 " "Implemented 4199 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "16 " "Implemented 16 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1457454229514 ""} { "Info" "ICUT_CUT_TM_OPINS" "77 " "Implemented 77 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1457454229514 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "50 " "Implemented 50 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1457454229514 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3879 " "Implemented 3879 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1457454229514 ""} { "Info" "ICUT_CUT_TM_RAMS" "176 " "Implemented 176 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1457454229514 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1457454229514 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1457454229514 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 113 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 113 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "563 " "Peak virtual memory: 563 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454230017 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:23:49 2016 " "Processing ended: Tue Mar 08 16:23:49 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454230017 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454230017 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454230017 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457454230017 ""}
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.rdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.rdb
new file mode 100644
index 0000000..22c33fb
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.rdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.cdb
new file mode 100644
index 0000000..a841497
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.hdb
new file mode 100644
index 0000000..0b5a402
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.logdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.pre_map.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.pre_map.hdb
new file mode 100644
index 0000000..a000365
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.pre_map.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.pti_db_list.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.pti_db_list.ddb
new file mode 100644
index 0000000..4c5fa0d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.pti_db_list.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.root_partition.map.reg_db.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..3c9f700
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.root_partition.map.reg_db.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.routing.rdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.routing.rdb
new file mode 100644
index 0000000..0a296c6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.routing.rdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv.hdb
new file mode 100644
index 0000000..d8b0c2a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv_sg.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv_sg.cdb
new file mode 100644
index 0000000..efa0b82
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv_sg.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv_sg_swap.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..130c9d9
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv_sg_swap.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sgdiff.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sgdiff.cdb
new file mode 100644
index 0000000..2c44c63
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sgdiff.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sgdiff.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sgdiff.hdb
new file mode 100644
index 0000000..72a91cb
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sgdiff.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sld_design_entry.sci b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sld_design_entry.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sld_design_entry.sci
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sld_design_entry_dsc.sci b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sld_design_entry_dsc.sci
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.smart_action.txt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.smp_dump.txt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.smp_dump.txt
new file mode 100644
index 0000000..5e0f7e1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.smp_dump.txt
@@ -0,0 +1,13 @@
+
+State Machine - |TOP_DE0_CAMERA_MOUSE|ps2:inst6|cur_state
+Name cur_state.trans cur_state.pulldat cur_state.pullclk cur_state.listen 
+cur_state.listen 0 0 0 0 
+cur_state.pullclk 0 0 1 1 
+cur_state.pulldat 0 1 0 1 
+cur_state.trans 1 0 0 1 
+
+State Machine - |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST
+Name mSetup_ST.0000 mSetup_ST.0010 mSetup_ST.0001 
+mSetup_ST.0000 0 0 0 
+mSetup_ST.0001 1 0 1 
+mSetup_ST.0010 1 1 0 
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta.qmsg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta.qmsg
new file mode 100644
index 0000000..1522e95
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta.qmsg
@@ -0,0 +1,57 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1457454288594 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457454288614 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:24:47 2016 " "Processing started: Tue Mar 08 16:24:47 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457454288614 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1457454288614 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DE0_D5M -c DE0_D5M " "Command: quartus_sta DE0_D5M -c DE0_D5M" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1457454288620 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1457454288727 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1457454290141 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457454290215 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457454290215 ""}
+{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_v5o1 " "Entity dcfifo_v5o1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a*  " "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292023 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a*  " "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292023 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1457454292023 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Quartus II" 0 -1 1457454292023 ""}
+{ "Info" "ISTA_SDC_FOUND" "DE0_D5M.sdc " "Reading SDC File: 'DE0_D5M.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1457454292051 ""}
+{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292064 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292064 ""}  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292064 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454292089 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454292089 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454292089 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454292089 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454292089 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
+{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457454292217 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457454292217 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457454292217 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1457454292217 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1457454292237 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1457454292352 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457454292435 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457454292435 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.837 " "Worst-case setup slack is -0.837" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292462 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292462 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.837       -39.407 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -0.837       -39.407 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292462 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   14.268         0.000 CLOCK_50  " "   14.268         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292462 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454292462 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.331 " "Worst-case hold slack is 0.331" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292503 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292503 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.331         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.331         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292503 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.358         0.000 CLOCK_50  " "    0.358         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292503 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454292503 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -1.488 " "Worst-case recovery slack is -1.488" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.488      -368.986 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -1.488      -368.986 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   12.673         0.000 CLOCK_50  " "   12.673         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292527 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454292527 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.559 " "Worst-case removal slack is 1.559" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292546 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292546 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.559         0.000 CLOCK_50  " "    1.559         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292546 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.115         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    4.115         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292546 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454292546 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.734 " "Worst-case minimum pulse width slack is 3.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.734         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.734         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.580         0.000 CLOCK_50  " "    9.580         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454292567 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454292567 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 40 synchronizer chains. " "Report Metastability: Found 40 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454293023 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454293023 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 40 " "Number of Synchronizer Chains Found: 40" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454293023 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454293023 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454293023 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 11.193 ns " "Worst Case Available Settling Time: 11.193 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454293023 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454293023 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454293023 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454293023 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454293023 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454293023 ""}  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454293023 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1457454293054 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1457454293089 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1457454294662 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454294996 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454294996 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454294996 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454294996 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454294996 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
+{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457454295002 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457454295002 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457454295002 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1457454295002 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457454295042 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457454295042 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.283 " "Worst-case setup slack is -0.283" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.283        -5.821 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -0.283        -5.821 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   14.832         0.000 CLOCK_50  " "   14.832         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295067 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454295067 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.298 " "Worst-case hold slack is 0.298" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295096 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295096 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.298         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.298         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295096 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.312         0.000 CLOCK_50  " "    0.312         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295096 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454295096 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.835 " "Worst-case recovery slack is -0.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.835      -178.452 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -0.835      -178.452 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   13.489         0.000 CLOCK_50  " "   13.489         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295120 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454295120 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.418 " "Worst-case removal slack is 1.418" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.418         0.000 CLOCK_50  " "    1.418         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.617         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.617         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295146 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454295146 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.739 " "Worst-case minimum pulse width slack is 3.739" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295169 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295169 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.739         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.739         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295169 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.561         0.000 CLOCK_50  " "    9.561         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295169 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454295169 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 40 synchronizer chains. " "Report Metastability: Found 40 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295581 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295581 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 40 " "Number of Synchronizer Chains Found: 40" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295581 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295581 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295581 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 11.719 ns " "Worst Case Available Settling Time: 11.719 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295581 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295581 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295581 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295581 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295581 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295581 ""}  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454295581 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1457454295619 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454297109 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454297109 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454297109 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454297109 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457454297109 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
+{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457454297116 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457454297116 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457454297116 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1457454297116 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.209 " "Worst-case setup slack is 1.209" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.209         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    1.209         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297151 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.656         0.000 CLOCK_50  " "   16.656         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297151 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454297151 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.169 " "Worst-case hold slack is 0.169" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297184 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297184 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.169         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.169         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297184 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.187         0.000 CLOCK_50  " "    0.187         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297184 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454297184 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 0.780 " "Worst-case recovery slack is 0.780" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297214 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297214 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.780         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.780         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297214 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.649         0.000 CLOCK_50  " "   15.649         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297214 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454297214 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.849 " "Worst-case removal slack is 0.849" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.849         0.000 CLOCK_50  " "    0.849         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.409         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    2.409         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297248 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454297248 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.746 " "Worst-case minimum pulse width slack is 3.746" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297277 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297277 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.746         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.746         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297277 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.266         0.000 CLOCK_50  " "    9.266         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297277 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457454297277 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 40 synchronizer chains. " "Report Metastability: Found 40 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297744 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297744 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 40 " "Number of Synchronizer Chains Found: 40" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297744 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297744 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297744 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 13.328 ns " "Worst Case Available Settling Time: 13.328 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297744 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297744 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297744 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297744 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297744 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297744 ""}  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457454297744 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1457454298281 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1457454298283 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 29 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 29 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "549 " "Peak virtual memory: 549 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457454299842 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:24:59 2016 " "Processing ended: Tue Mar 08 16:24:59 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457454299842 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457454299842 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457454299842 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457454299842 ""}
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta.rdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta.rdb
new file mode 100644
index 0000000..172488a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta.rdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta_cmp.6_slow_1200mv_85c.tdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..59296fe
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.syn_hier_info b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.syn_hier_info
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.syn_hier_info
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tis_db_list.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tis_db_list.ddb
new file mode 100644
index 0000000..ba46866
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tis_db_list.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.fast_1200mv_0c.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..effc461
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.fast_1200mv_0c.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.slow_1200mv_0c.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..4171bcc
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.slow_1200mv_0c.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.slow_1200mv_85c.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..1374940
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.slow_1200mv_85c.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.vpr.ammdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.vpr.ammdb
new file mode 100644
index 0000000..2614a95
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.vpr.ammdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_gray2bin_tgb.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_gray2bin_tgb.tdf
new file mode 100644
index 0000000..3e96f62
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_gray2bin_tgb.tdf
@@ -0,0 +1,50 @@
+--a_gray2bin carry_chain="MANUAL" carry_chain_length=48 device_family="Cyclone III" ignore_carry_buffers="OFF" WIDTH=10 bin gray
+--VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN a_gray2bin_tgb
+( 
+	bin[9..0]	:	output;
+	gray[9..0]	:	input;
+) 
+VARIABLE 
+	xor0	: WIRE;
+	xor1	: WIRE;
+	xor2	: WIRE;
+	xor3	: WIRE;
+	xor4	: WIRE;
+	xor5	: WIRE;
+	xor6	: WIRE;
+	xor7	: WIRE;
+	xor8	: WIRE;
+
+BEGIN 
+	bin[] = ( gray[9..9], xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0);
+	xor0 = (gray[0..0] $ xor1);
+	xor1 = (gray[1..1] $ xor2);
+	xor2 = (gray[2..2] $ xor3);
+	xor3 = (gray[3..3] $ xor4);
+	xor4 = (gray[4..4] $ xor5);
+	xor5 = (gray[5..5] $ xor6);
+	xor6 = (gray[6..6] $ xor7);
+	xor7 = (gray[7..7] $ xor8);
+	xor8 = (gray[9..9] $ gray[8..8]);
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf
new file mode 100644
index 0000000..a69d388
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf
@@ -0,0 +1,75 @@
+--a_graycounter DEVICE_FAMILY="Cyclone III" PVALUE=1 WIDTH=10 aclr clock cnt_en q ALTERA_INTERNAL_OPTIONS=suppress_da_rule_internal=S102
+--VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = reg 14 
+OPTIONS ALTERA_INTERNAL_OPTION = "suppress_da_rule_internal=S102;{-to counter8a0} POWER_UP_LEVEL=HIGH;{-to parity9} POWER_UP_LEVEL=HIGH";
+
+SUBDESIGN a_graycounter_ojc
+( 
+	aclr	:	input;
+	clock	:	input;
+	cnt_en	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	counter8a0 : dffeas
+		WITH (
+			power_up = "high"
+		);
+	counter8a1 : dffeas;
+	counter8a2 : dffeas;
+	counter8a3 : dffeas;
+	counter8a4 : dffeas;
+	counter8a5 : dffeas;
+	counter8a6 : dffeas;
+	counter8a7 : dffeas;
+	counter8a8 : dffeas;
+	counter8a9 : dffeas;
+	parity9 : dffeas
+		WITH (
+			power_up = "high"
+		);
+	sub_parity10a[2..0] : dffeas;
+	cntr_cout[9..0]	: WIRE;
+	parity_cout	: WIRE;
+	sclr	: NODE;
+	updown	: NODE;
+
+BEGIN 
+	counter8a[9..0].clk = clock;
+	counter8a[9..1].clrn = (! aclr);
+	counter8a[9..0].d = ( (counter8a[9].q $ cntr_cout[8..8]), (counter8a[8].q $ (counter8a[7].q & cntr_cout[7..7])), (counter8a[7].q $ (counter8a[6].q & cntr_cout[6..6])), (counter8a[6].q $ (counter8a[5].q & cntr_cout[5..5])), (counter8a[5].q $ (counter8a[4].q & cntr_cout[4..4])), (counter8a[4].q $ (counter8a[3].q & cntr_cout[3..3])), (counter8a[3].q $ (counter8a[2].q & cntr_cout[2..2])), (counter8a[2].q $ (counter8a[1].q & cntr_cout[1..1])), (counter8a[1].q $ (counter8a[0].q & cntr_cout[0..0])), ((cnt_en & (counter8a[0].q $ (! parity_cout))) # ((! cnt_en) & counter8a[0].q)));
+	counter8a[0].prn = (! aclr);
+	counter8a[9..0].sclr = sclr;
+	parity9.clk = clock;
+	parity9.d = ((cnt_en & ((sub_parity10a[0..0].q $ sub_parity10a[1..1].q) $ sub_parity10a[2..2].q)) # ((! cnt_en) & parity9.q));
+	parity9.prn = (! aclr);
+	parity9.sclr = sclr;
+	sub_parity10a[].clk = ( clock, clock, clock);
+	sub_parity10a[].clrn = ( (! aclr), (! aclr), (! aclr));
+	sub_parity10a[].d = ( ((cnt_en & (counter8a[8..8].q $ counter8a[9..9].q)) # ((! cnt_en) & sub_parity10a[2].q)), ((cnt_en & (((counter8a[4..4].q $ counter8a[5..5].q) $ counter8a[6..6].q) $ counter8a[7..7].q)) # ((! cnt_en) & sub_parity10a[1].q)), ((cnt_en & (((counter8a[0..0].q $ counter8a[1..1].q) $ counter8a[2..2].q) $ counter8a[3..3].q)) # ((! cnt_en) & sub_parity10a[0].q)));
+	sub_parity10a[].sclr = ( sclr, sclr, sclr);
+	cntr_cout[] = ( B"0", (cntr_cout[7..7] & (! counter8a[7].q)), (cntr_cout[6..6] & (! counter8a[6].q)), (cntr_cout[5..5] & (! counter8a[5].q)), (cntr_cout[4..4] & (! counter8a[4].q)), (cntr_cout[3..3] & (! counter8a[3].q)), (cntr_cout[2..2] & (! counter8a[2].q)), (cntr_cout[1..1] & (! counter8a[1].q)), (cntr_cout[0..0] & (! counter8a[0].q)), (cnt_en & parity_cout));
+	parity_cout = (((! parity9.q) $ updown) & cnt_en);
+	q[] = counter8a[9..0].q;
+	sclr = GND;
+	updown = VCC;
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf
new file mode 100644
index 0000000..776938d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf
@@ -0,0 +1,75 @@
+--a_graycounter DEVICE_FAMILY="Cyclone III" PVALUE=1 WIDTH=10 aclr clock cnt_en q
+--VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = reg 14 
+OPTIONS ALTERA_INTERNAL_OPTION = "{-to counter5a0} POWER_UP_LEVEL=HIGH;{-to parity6} POWER_UP_LEVEL=HIGH";
+
+SUBDESIGN a_graycounter_s57
+( 
+	aclr	:	input;
+	clock	:	input;
+	cnt_en	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	counter5a0 : dffeas
+		WITH (
+			power_up = "high"
+		);
+	counter5a1 : dffeas;
+	counter5a2 : dffeas;
+	counter5a3 : dffeas;
+	counter5a4 : dffeas;
+	counter5a5 : dffeas;
+	counter5a6 : dffeas;
+	counter5a7 : dffeas;
+	counter5a8 : dffeas;
+	counter5a9 : dffeas;
+	parity6 : dffeas
+		WITH (
+			power_up = "high"
+		);
+	sub_parity7a[2..0] : dffeas;
+	cntr_cout[9..0]	: WIRE;
+	parity_cout	: WIRE;
+	sclr	: NODE;
+	updown	: NODE;
+
+BEGIN 
+	counter5a[9..0].clk = clock;
+	counter5a[9..1].clrn = (! aclr);
+	counter5a[9..0].d = ( (counter5a[9].q $ cntr_cout[8..8]), (counter5a[8].q $ (counter5a[7].q & cntr_cout[7..7])), (counter5a[7].q $ (counter5a[6].q & cntr_cout[6..6])), (counter5a[6].q $ (counter5a[5].q & cntr_cout[5..5])), (counter5a[5].q $ (counter5a[4].q & cntr_cout[4..4])), (counter5a[4].q $ (counter5a[3].q & cntr_cout[3..3])), (counter5a[3].q $ (counter5a[2].q & cntr_cout[2..2])), (counter5a[2].q $ (counter5a[1].q & cntr_cout[1..1])), (counter5a[1].q $ (counter5a[0].q & cntr_cout[0..0])), ((cnt_en & (counter5a[0].q $ (! parity_cout))) # ((! cnt_en) & counter5a[0].q)));
+	counter5a[0].prn = (! aclr);
+	counter5a[9..0].sclr = sclr;
+	parity6.clk = clock;
+	parity6.d = ((cnt_en & ((sub_parity7a[0..0].q $ sub_parity7a[1..1].q) $ sub_parity7a[2..2].q)) # ((! cnt_en) & parity6.q));
+	parity6.prn = (! aclr);
+	parity6.sclr = sclr;
+	sub_parity7a[].clk = ( clock, clock, clock);
+	sub_parity7a[].clrn = ( (! aclr), (! aclr), (! aclr));
+	sub_parity7a[].d = ( ((cnt_en & (counter5a[8..8].q $ counter5a[9..9].q)) # ((! cnt_en) & sub_parity7a[2].q)), ((cnt_en & (((counter5a[4..4].q $ counter5a[5..5].q) $ counter5a[6..6].q) $ counter5a[7..7].q)) # ((! cnt_en) & sub_parity7a[1].q)), ((cnt_en & (((counter5a[0..0].q $ counter5a[1..1].q) $ counter5a[2..2].q) $ counter5a[3..3].q)) # ((! cnt_en) & sub_parity7a[0].q)));
+	sub_parity7a[].sclr = ( sclr, sclr, sclr);
+	cntr_cout[] = ( B"0", (cntr_cout[7..7] & (! counter5a[7].q)), (cntr_cout[6..6] & (! counter5a[6].q)), (cntr_cout[5..5] & (! counter5a[5].q)), (cntr_cout[4..4] & (! counter5a[4].q)), (cntr_cout[3..3] & (! counter5a[3].q)), (cntr_cout[2..2] & (! counter5a[2].q)), (cntr_cout[1..1] & (! counter5a[1].q)), (cntr_cout[0..0] & (! counter5a[0].q)), (cnt_en & parity_cout));
+	parity_cout = (((! parity6.q) $ updown) & cnt_en);
+	q[] = counter5a[9..0].q;
+	sclr = GND;
+	updown = VCC;
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/add_sub_gfh.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/add_sub_gfh.tdf
new file mode 100644
index 0000000..29d5762
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/add_sub_gfh.tdf
@@ -0,0 +1,35 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone III" LPM_PIPELINE=0 LPM_REPRESENTATION="SIGNED" LPM_WIDTH=13 ONE_INPUT_IS_CONSTANT="NO" cin dataa datab result
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = lut 13 
+SUBDESIGN add_sub_gfh
+( 
+	cin	:	input;
+	dataa[12..0]	:	input;
+	datab[12..0]	:	input;
+	result[12..0]	:	output;
+) 
+VARIABLE
+	result_int[13..0]	:	WIRE;
+BEGIN 
+	result_int[] = (dataa[], cin) + (datab[], cin);
+	result[] = result_int[13..1];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf
new file mode 100644
index 0000000..cc60ec9
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf
@@ -0,0 +1,42 @@
+--dffpipe DELAY=2 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS
+--VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_dcfifo 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION dffpipe_pe9 (clock, clrn, d[9..0])
+RETURNS ( q[9..0]);
+
+--synthesis_resources = reg 20 
+OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS";
+
+SUBDESIGN alt_synch_pipe_qld
+( 
+	clock	:	input;
+	clrn	:	input;
+	d[9..0]	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	dffpipe13 : dffpipe_pe9;
+
+BEGIN 
+	dffpipe13.clock = clock;
+	dffpipe13.clrn = clrn;
+	dffpipe13.d[] = d[];
+	q[] = dffpipe13.q[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf
new file mode 100644
index 0000000..0870b23
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf
@@ -0,0 +1,42 @@
+--dffpipe DELAY=2 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS
+--VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_dcfifo 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION dffpipe_qe9 (clock, clrn, d[9..0])
+RETURNS ( q[9..0]);
+
+--synthesis_resources = reg 20 
+OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS";
+
+SUBDESIGN alt_synch_pipe_rld
+( 
+	clock	:	input;
+	clrn	:	input;
+	d[9..0]	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	dffpipe16 : dffpipe_qe9;
+
+BEGIN 
+	dffpipe16.clock = clock;
+	dffpipe16.clrn = clrn;
+	dffpipe16.d[] = d[];
+	q[] = dffpipe16.q[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf
new file mode 100644
index 0000000..dfc7a42
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf
@@ -0,0 +1,53 @@
+--altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=2 clk0_duty_cycle=50 clk0_multiply_by=5 clk0_phase_shift="0" clk1_divide_by=2 clk1_duty_cycle=50 clk1_multiply_by=5 clk1_phase_shift="-2600" compensate_clock="CLK0" device_family="Cyclone III" inclk0_input_frequency=20000 intended_device_family="Cyclone III" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:03:43:SJ cbx_altiobuf_bidir 2013:06:12:18:03:43:SJ cbx_altiobuf_in 2013:06:12:18:03:43:SJ cbx_altiobuf_out 2013:06:12:18:03:43:SJ cbx_altpll 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_pll (areset, clkswitch, configupdate, fbin, inclk[1..0], pfdena, phasecounterselect[phasecounterselect_width-1..0], phasestep, phaseupdown, scanclk, scanclkena, scandata)
+WITH ( AUTO_SETTINGS, BANDWIDTH, BANDWIDTH_TYPE, C0_HIGH, C0_INITIAL, C0_LOW, C0_MODE, C0_PH, C0_TEST_SOURCE, C1_HIGH, C1_INITIAL, C1_LOW, C1_MODE, C1_PH, C1_TEST_SOURCE, C1_USE_CASC_IN, C2_HIGH, C2_INITIAL, C2_LOW, C2_MODE, C2_PH, C2_TEST_SOURCE, C2_USE_CASC_IN, C3_HIGH, C3_INITIAL, C3_LOW, C3_MODE, C3_PH, C3_TEST_SOURCE, C3_USE_CASC_IN, C4_HIGH, C4_INITIAL, C4_LOW, C4_MODE, C4_PH, C4_TEST_SOURCE, C4_USE_CASC_IN, CHARGE_PUMP_CURRENT, CHARGE_PUMP_CURRENT_BITS, CLK0_COUNTER, CLK0_DIVIDE_BY, CLK0_DUTY_CYCLE, CLK0_MULTIPLY_BY, CLK0_OUTPUT_FREQUENCY, CLK0_PHASE_SHIFT, CLK0_PHASE_SHIFT_NUM, clk0_use_even_counter_mode, clk0_use_even_counter_value, CLK1_COUNTER, CLK1_DIVIDE_BY, CLK1_DUTY_CYCLE, CLK1_MULTIPLY_BY, CLK1_OUTPUT_FREQUENCY, CLK1_PHASE_SHIFT, CLK1_PHASE_SHIFT_NUM, clk1_use_even_counter_mode, clk1_use_even_counter_value, CLK2_COUNTER, CLK2_DIVIDE_BY, CLK2_DUTY_CYCLE, CLK2_MULTIPLY_BY, CLK2_OUTPUT_FREQUENCY, CLK2_PHASE_SHIFT, CLK2_PHASE_SHIFT_NUM, clk2_use_even_counter_mode, clk2_use_even_counter_value, CLK3_COUNTER, CLK3_DIVIDE_BY, CLK3_DUTY_CYCLE, CLK3_MULTIPLY_BY, CLK3_OUTPUT_FREQUENCY, CLK3_PHASE_SHIFT, CLK3_PHASE_SHIFT_NUM, clk3_use_even_counter_mode, clk3_use_even_counter_value, CLK4_COUNTER, CLK4_DIVIDE_BY, CLK4_DUTY_CYCLE, CLK4_MULTIPLY_BY, CLK4_OUTPUT_FREQUENCY, CLK4_PHASE_SHIFT, CLK4_PHASE_SHIFT_NUM, clk4_use_even_counter_mode, clk4_use_even_counter_value, CLKOUT_WIDTH = 5, COMPENSATE_CLOCK, ENABLE_SWITCH_OVER_COUNTER, INCLK0_INPUT_FREQUENCY, INCLK1_INPUT_FREQUENCY, LOCK_HIGH, LOCK_LOW, lock_window_ui, lock_window_ui_bits, LOOP_FILTER_C, LOOP_FILTER_C_BITS, LOOP_FILTER_R, LOOP_FILTER_R_BITS, M, M_INITIAL, M_PH, M_TEST_SOURCE, N, OPERATION_MODE, PFD_MAX, PFD_MIN, PHASECOUNTERSELECT_WIDTH = 3, PLL_COMPENSATION_DELAY, PLL_TYPE, SCAN_CHAIN_MIF_FILE, self_reset_on_loss_lock, SIMULATION_TYPE, SWITCH_OVER_COUNTER, SWITCH_OVER_TYPE, TEST_BYPASS_LOCK_DETECT, USE_DC_COUPLING, VCO_CENTER, VCO_DIVIDE_BY, vco_frequency_control, VCO_MAX, VCO_MIN, VCO_MULTIPLY_BY, vco_phase_shift_step, VCO_POST_SCALE, VCO_RANGE_DETECTOR_HIGH_BITS, VCO_RANGE_DETECTOR_LOW_BITS)
+RETURNS ( activeclock, clk[CLKOUT_WIDTH-1..0], clkbad[1..0], fbout, locked, phasedone, scandataout, scandone, vcooverrange, vcounderrange);
+
+--synthesis_resources = cycloneiii_pll 1 
+SUBDESIGN altpll_9ee2
+( 
+	clk[4..0]	:	output;
+	inclk[1..0]	:	input;
+) 
+VARIABLE 
+	pll1 : cycloneiii_pll
+		WITH (
+			BANDWIDTH_TYPE = "auto",
+			CLK0_DIVIDE_BY = 2,
+			CLK0_DUTY_CYCLE = 50,
+			CLK0_MULTIPLY_BY = 5,
+			CLK0_PHASE_SHIFT = "0",
+			CLK1_DIVIDE_BY = 2,
+			CLK1_DUTY_CYCLE = 50,
+			CLK1_MULTIPLY_BY = 5,
+			CLK1_PHASE_SHIFT = "-2600",
+			COMPENSATE_CLOCK = "clk0",
+			INCLK0_INPUT_FREQUENCY = 20000,
+			OPERATION_MODE = "normal",
+			PLL_TYPE = "auto"
+		);
+
+BEGIN 
+	pll1.fbin = pll1.fbout;
+	pll1.inclk[] = inclk[];
+	clk[] = ( pll1.clk[4..0]);
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_5n81.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_5n81.tdf
new file mode 100644
index 0000000..b42503b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_5n81.tdf
@@ -0,0 +1,2842 @@
+--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone III" LOW_POWER_MODE="AUTO" NUMWORDS_A=798 NUMWORDS_B=798 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=90 WIDTH_B=90 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 WIDTHAD_B=10 address_a address_b clock0 clocken0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
+RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M9K 10 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_5n81
+( 
+	address_a[9..0]	:	input;
+	address_b[9..0]	:	input;
+	clock0	:	input;
+	clocken0	:	input;
+	data_a[89..0]	:	input;
+	q_b[89..0]	:	output;
+	wren_a	:	input;
+) 
+VARIABLE 
+	ram_block3a0 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a1 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a2 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a3 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a4 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a5 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a6 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a7 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a8 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 8,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a9 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 9,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 9,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a10 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 10,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 10,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a11 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 11,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 11,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a12 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 12,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 12,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a13 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 13,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 13,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a14 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 14,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 14,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a15 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 15,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 15,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a16 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 16,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 16,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a17 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 17,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 17,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a18 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 18,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 18,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a19 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 19,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 19,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a20 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 20,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 20,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a21 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 21,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 21,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a22 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 22,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 22,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a23 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 23,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 23,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a24 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 24,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 24,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a25 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 25,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 25,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a26 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 26,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 26,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a27 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 27,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 27,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a28 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 28,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 28,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a29 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 29,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 29,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a30 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 30,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 30,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a31 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 31,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 31,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a32 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 32,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 32,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a33 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 33,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 33,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a34 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 34,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 34,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a35 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 35,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 35,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a36 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 36,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 36,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a37 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 37,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 37,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a38 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 38,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 38,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a39 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 39,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 39,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a40 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 40,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 40,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a41 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 41,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 41,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a42 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 42,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 42,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a43 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 43,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 43,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a44 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 44,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 44,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a45 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 45,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 45,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a46 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 46,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 46,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a47 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 47,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 47,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a48 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 48,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 48,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a49 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 49,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 49,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a50 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 50,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 50,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a51 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 51,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 51,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a52 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 52,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 52,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a53 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 53,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 53,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a54 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 54,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 54,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a55 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 55,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 55,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a56 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 56,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 56,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a57 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 57,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 57,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a58 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 58,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 58,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a59 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 59,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 59,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a60 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 60,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 60,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a61 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 61,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 61,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a62 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 62,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 62,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a63 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 63,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 63,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a64 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 64,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 64,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a65 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 65,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 65,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a66 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 66,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 66,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a67 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 67,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 67,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a68 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 68,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 68,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a69 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 69,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 69,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a70 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 70,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 70,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a71 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 71,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 71,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a72 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 72,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 72,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a73 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 73,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 73,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a74 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 74,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 74,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a75 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 75,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 75,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a76 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 76,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 76,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a77 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 77,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 77,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a78 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 78,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 78,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a79 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 79,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 79,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a80 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 80,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 80,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a81 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 81,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 81,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a82 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 82,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 82,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a83 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 83,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 83,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a84 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 84,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 84,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a85 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 85,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 85,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a86 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 86,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 86,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a87 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 87,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 87,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a88 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 88,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 88,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a89 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 89,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 89,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 90,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[9..0]	: WIRE;
+	address_b_wire[9..0]	: WIRE;
+
+BEGIN 
+	ram_block3a[89..0].clk0 = clock0;
+	ram_block3a[89..0].ena0 = clocken0;
+	ram_block3a[89..0].portaaddr[] = ( address_a_wire[9..0]);
+	ram_block3a[0].portadatain[] = ( data_a[0..0]);
+	ram_block3a[1].portadatain[] = ( data_a[1..1]);
+	ram_block3a[2].portadatain[] = ( data_a[2..2]);
+	ram_block3a[3].portadatain[] = ( data_a[3..3]);
+	ram_block3a[4].portadatain[] = ( data_a[4..4]);
+	ram_block3a[5].portadatain[] = ( data_a[5..5]);
+	ram_block3a[6].portadatain[] = ( data_a[6..6]);
+	ram_block3a[7].portadatain[] = ( data_a[7..7]);
+	ram_block3a[8].portadatain[] = ( data_a[8..8]);
+	ram_block3a[9].portadatain[] = ( data_a[9..9]);
+	ram_block3a[10].portadatain[] = ( data_a[10..10]);
+	ram_block3a[11].portadatain[] = ( data_a[11..11]);
+	ram_block3a[12].portadatain[] = ( data_a[12..12]);
+	ram_block3a[13].portadatain[] = ( data_a[13..13]);
+	ram_block3a[14].portadatain[] = ( data_a[14..14]);
+	ram_block3a[15].portadatain[] = ( data_a[15..15]);
+	ram_block3a[16].portadatain[] = ( data_a[16..16]);
+	ram_block3a[17].portadatain[] = ( data_a[17..17]);
+	ram_block3a[18].portadatain[] = ( data_a[18..18]);
+	ram_block3a[19].portadatain[] = ( data_a[19..19]);
+	ram_block3a[20].portadatain[] = ( data_a[20..20]);
+	ram_block3a[21].portadatain[] = ( data_a[21..21]);
+	ram_block3a[22].portadatain[] = ( data_a[22..22]);
+	ram_block3a[23].portadatain[] = ( data_a[23..23]);
+	ram_block3a[24].portadatain[] = ( data_a[24..24]);
+	ram_block3a[25].portadatain[] = ( data_a[25..25]);
+	ram_block3a[26].portadatain[] = ( data_a[26..26]);
+	ram_block3a[27].portadatain[] = ( data_a[27..27]);
+	ram_block3a[28].portadatain[] = ( data_a[28..28]);
+	ram_block3a[29].portadatain[] = ( data_a[29..29]);
+	ram_block3a[30].portadatain[] = ( data_a[30..30]);
+	ram_block3a[31].portadatain[] = ( data_a[31..31]);
+	ram_block3a[32].portadatain[] = ( data_a[32..32]);
+	ram_block3a[33].portadatain[] = ( data_a[33..33]);
+	ram_block3a[34].portadatain[] = ( data_a[34..34]);
+	ram_block3a[35].portadatain[] = ( data_a[35..35]);
+	ram_block3a[36].portadatain[] = ( data_a[36..36]);
+	ram_block3a[37].portadatain[] = ( data_a[37..37]);
+	ram_block3a[38].portadatain[] = ( data_a[38..38]);
+	ram_block3a[39].portadatain[] = ( data_a[39..39]);
+	ram_block3a[40].portadatain[] = ( data_a[40..40]);
+	ram_block3a[41].portadatain[] = ( data_a[41..41]);
+	ram_block3a[42].portadatain[] = ( data_a[42..42]);
+	ram_block3a[43].portadatain[] = ( data_a[43..43]);
+	ram_block3a[44].portadatain[] = ( data_a[44..44]);
+	ram_block3a[45].portadatain[] = ( data_a[45..45]);
+	ram_block3a[46].portadatain[] = ( data_a[46..46]);
+	ram_block3a[47].portadatain[] = ( data_a[47..47]);
+	ram_block3a[48].portadatain[] = ( data_a[48..48]);
+	ram_block3a[49].portadatain[] = ( data_a[49..49]);
+	ram_block3a[50].portadatain[] = ( data_a[50..50]);
+	ram_block3a[51].portadatain[] = ( data_a[51..51]);
+	ram_block3a[52].portadatain[] = ( data_a[52..52]);
+	ram_block3a[53].portadatain[] = ( data_a[53..53]);
+	ram_block3a[54].portadatain[] = ( data_a[54..54]);
+	ram_block3a[55].portadatain[] = ( data_a[55..55]);
+	ram_block3a[56].portadatain[] = ( data_a[56..56]);
+	ram_block3a[57].portadatain[] = ( data_a[57..57]);
+	ram_block3a[58].portadatain[] = ( data_a[58..58]);
+	ram_block3a[59].portadatain[] = ( data_a[59..59]);
+	ram_block3a[60].portadatain[] = ( data_a[60..60]);
+	ram_block3a[61].portadatain[] = ( data_a[61..61]);
+	ram_block3a[62].portadatain[] = ( data_a[62..62]);
+	ram_block3a[63].portadatain[] = ( data_a[63..63]);
+	ram_block3a[64].portadatain[] = ( data_a[64..64]);
+	ram_block3a[65].portadatain[] = ( data_a[65..65]);
+	ram_block3a[66].portadatain[] = ( data_a[66..66]);
+	ram_block3a[67].portadatain[] = ( data_a[67..67]);
+	ram_block3a[68].portadatain[] = ( data_a[68..68]);
+	ram_block3a[69].portadatain[] = ( data_a[69..69]);
+	ram_block3a[70].portadatain[] = ( data_a[70..70]);
+	ram_block3a[71].portadatain[] = ( data_a[71..71]);
+	ram_block3a[72].portadatain[] = ( data_a[72..72]);
+	ram_block3a[73].portadatain[] = ( data_a[73..73]);
+	ram_block3a[74].portadatain[] = ( data_a[74..74]);
+	ram_block3a[75].portadatain[] = ( data_a[75..75]);
+	ram_block3a[76].portadatain[] = ( data_a[76..76]);
+	ram_block3a[77].portadatain[] = ( data_a[77..77]);
+	ram_block3a[78].portadatain[] = ( data_a[78..78]);
+	ram_block3a[79].portadatain[] = ( data_a[79..79]);
+	ram_block3a[80].portadatain[] = ( data_a[80..80]);
+	ram_block3a[81].portadatain[] = ( data_a[81..81]);
+	ram_block3a[82].portadatain[] = ( data_a[82..82]);
+	ram_block3a[83].portadatain[] = ( data_a[83..83]);
+	ram_block3a[84].portadatain[] = ( data_a[84..84]);
+	ram_block3a[85].portadatain[] = ( data_a[85..85]);
+	ram_block3a[86].portadatain[] = ( data_a[86..86]);
+	ram_block3a[87].portadatain[] = ( data_a[87..87]);
+	ram_block3a[88].portadatain[] = ( data_a[88..88]);
+	ram_block3a[89].portadatain[] = ( data_a[89..89]);
+	ram_block3a[89..0].portawe = wren_a;
+	ram_block3a[89..0].portbaddr[] = ( address_b_wire[9..0]);
+	ram_block3a[89..0].portbre = B"111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111";
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block3a[89..0].portbdataout[0..0]);
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf
new file mode 100644
index 0000000..2195635
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf
@@ -0,0 +1,587 @@
+--altsyncram ADDRESS_ACLR_B="CLEAR1" ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone III" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="CLEAR1" OUTDATA_REG_B="CLOCK1" RAM_BLOCK_TYPE="M4K" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=9 WIDTHAD_B=9 aclr1 address_a address_b addressstall_b clock0 clock1 clocken1 data_a q_b wren_a
+--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
+RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M9K 1 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_de51
+( 
+	aclr1	:	input;
+	address_a[8..0]	:	input;
+	address_b[8..0]	:	input;
+	addressstall_b	:	input;
+	clock0	:	input;
+	clock1	:	input;
+	clocken1	:	input;
+	data_a[15..0]	:	input;
+	q_b[15..0]	:	output;
+	wren_a	:	input;
+) 
+VARIABLE 
+	ram_block11a0 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a1 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a2 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a3 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a4 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a5 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a6 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a7 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a8 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 8,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a9 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 9,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 9,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a10 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 10,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 10,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a11 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 11,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 11,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a12 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 12,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 12,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a13 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 13,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 13,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a14 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 14,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 14,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a15 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 15,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 15,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[8..0]	: WIRE;
+	address_b_wire[8..0]	: WIRE;
+
+BEGIN 
+	ram_block11a[15..0].clk0 = clock0;
+	ram_block11a[15..0].clk1 = clock1;
+	ram_block11a[15..0].clr1 = aclr1;
+	ram_block11a[15..0].ena0 = wren_a;
+	ram_block11a[15..0].ena1 = clocken1;
+	ram_block11a[15..0].portaaddr[] = ( address_a_wire[8..0]);
+	ram_block11a[0].portadatain[] = ( data_a[0..0]);
+	ram_block11a[1].portadatain[] = ( data_a[1..1]);
+	ram_block11a[2].portadatain[] = ( data_a[2..2]);
+	ram_block11a[3].portadatain[] = ( data_a[3..3]);
+	ram_block11a[4].portadatain[] = ( data_a[4..4]);
+	ram_block11a[5].portadatain[] = ( data_a[5..5]);
+	ram_block11a[6].portadatain[] = ( data_a[6..6]);
+	ram_block11a[7].portadatain[] = ( data_a[7..7]);
+	ram_block11a[8].portadatain[] = ( data_a[8..8]);
+	ram_block11a[9].portadatain[] = ( data_a[9..9]);
+	ram_block11a[10].portadatain[] = ( data_a[10..10]);
+	ram_block11a[11].portadatain[] = ( data_a[11..11]);
+	ram_block11a[12].portadatain[] = ( data_a[12..12]);
+	ram_block11a[13].portadatain[] = ( data_a[13..13]);
+	ram_block11a[14].portadatain[] = ( data_a[14..14]);
+	ram_block11a[15].portadatain[] = ( data_a[15..15]);
+	ram_block11a[15..0].portawe = wren_a;
+	ram_block11a[15..0].portbaddr[] = ( address_b_wire[8..0]);
+	ram_block11a[15..0].portbaddrstall = addressstall_b;
+	ram_block11a[15..0].portbre = B"1111111111111111";
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block11a[15..0].portbdataout[0..0]);
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_lp81.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_lp81.tdf
new file mode 100644
index 0000000..b09ad92
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_lp81.tdf
@@ -0,0 +1,796 @@
+--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone III" LOW_POWER_MODE="AUTO" NUMWORDS_A=1278 NUMWORDS_B=1278 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=24 WIDTH_B=24 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clocken0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
+RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M9K 6 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_lp81
+( 
+	address_a[10..0]	:	input;
+	address_b[10..0]	:	input;
+	clock0	:	input;
+	clocken0	:	input;
+	data_a[23..0]	:	input;
+	q_b[23..0]	:	output;
+	wren_a	:	input;
+) 
+VARIABLE 
+	ram_block3a0 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a1 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a2 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a3 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a4 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a5 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a6 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a7 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a8 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 8,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a9 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 9,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 9,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a10 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 10,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 10,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a11 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 11,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 11,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a12 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 12,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 12,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a13 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 13,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 13,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a14 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 14,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 14,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a15 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 15,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 15,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a16 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 16,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 16,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a17 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 17,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 17,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a18 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 18,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 18,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a19 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 19,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 19,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a20 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 20,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 20,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a21 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 21,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 21,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a22 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 22,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 22,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a23 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 23,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 23,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[10..0]	: WIRE;
+	address_b_wire[10..0]	: WIRE;
+
+BEGIN 
+	ram_block3a[23..0].clk0 = clock0;
+	ram_block3a[23..0].ena0 = clocken0;
+	ram_block3a[23..0].portaaddr[] = ( address_a_wire[10..0]);
+	ram_block3a[0].portadatain[] = ( data_a[0..0]);
+	ram_block3a[1].portadatain[] = ( data_a[1..1]);
+	ram_block3a[2].portadatain[] = ( data_a[2..2]);
+	ram_block3a[3].portadatain[] = ( data_a[3..3]);
+	ram_block3a[4].portadatain[] = ( data_a[4..4]);
+	ram_block3a[5].portadatain[] = ( data_a[5..5]);
+	ram_block3a[6].portadatain[] = ( data_a[6..6]);
+	ram_block3a[7].portadatain[] = ( data_a[7..7]);
+	ram_block3a[8].portadatain[] = ( data_a[8..8]);
+	ram_block3a[9].portadatain[] = ( data_a[9..9]);
+	ram_block3a[10].portadatain[] = ( data_a[10..10]);
+	ram_block3a[11].portadatain[] = ( data_a[11..11]);
+	ram_block3a[12].portadatain[] = ( data_a[12..12]);
+	ram_block3a[13].portadatain[] = ( data_a[13..13]);
+	ram_block3a[14].portadatain[] = ( data_a[14..14]);
+	ram_block3a[15].portadatain[] = ( data_a[15..15]);
+	ram_block3a[16].portadatain[] = ( data_a[16..16]);
+	ram_block3a[17].portadatain[] = ( data_a[17..17]);
+	ram_block3a[18].portadatain[] = ( data_a[18..18]);
+	ram_block3a[19].portadatain[] = ( data_a[19..19]);
+	ram_block3a[20].portadatain[] = ( data_a[20..20]);
+	ram_block3a[21].portadatain[] = ( data_a[21..21]);
+	ram_block3a[22].portadatain[] = ( data_a[22..22]);
+	ram_block3a[23].portadatain[] = ( data_a[23..23]);
+	ram_block3a[23..0].portawe = wren_a;
+	ram_block3a[23..0].portbaddr[] = ( address_b_wire[10..0]);
+	ram_block3a[23..0].portbre = B"111111111111111111111111";
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block3a[23..0].portbdataout[0..0]);
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_e66.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_e66.tdf
new file mode 100644
index 0000000..c752b2f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_e66.tdf
@@ -0,0 +1,41 @@
+--lpm_compare DEVICE_FAMILY="Cyclone III" LPM_WIDTH=10 aeb dataa datab
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN cmpr_e66
+( 
+	aeb	:	output;
+	dataa[9..0]	:	input;
+	datab[9..0]	:	input;
+) 
+VARIABLE 
+	aeb_result_wire[0..0]	: WIRE;
+	aneb_result_wire[0..0]	: WIRE;
+	data_wire[26..0]	: WIRE;
+	eq_wire	: WIRE;
+
+BEGIN 
+	aeb = eq_wire;
+	aeb_result_wire[] = (! aneb_result_wire[]);
+	aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
+	data_wire[] = ( datab[9..9], dataa[9..9], datab[8..8], dataa[8..8], datab[7..7], dataa[7..7], datab[6..6], dataa[6..6], datab[5..5], dataa[5..5], datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], ((data_wire[23..23] $ data_wire[24..24]) # (data_wire[25..25] $ data_wire[26..26])), ((data_wire[19..19] $ data_wire[20..20]) # (data_wire[21..21] $ data_wire[22..22])), ((data_wire[15..15] $ data_wire[16..16]) # (data_wire[17..17] $ data_wire[18..18])), ((data_wire[11..11] $ data_wire[12..12]) # (data_wire[13..13] $ data_wire[14..14])), ((data_wire[7..7] $ data_wire[8..8]) # (data_wire[9..9] $ data_wire[10..10])), data_wire[6..6], (((data_wire[2..2] # data_wire[3..3]) # data_wire[4..4]) # data_wire[5..5]));
+	eq_wire = aeb_result_wire[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_ugc.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_ugc.tdf
new file mode 100644
index 0000000..52d3129
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_ugc.tdf
@@ -0,0 +1,41 @@
+--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" LPM_WIDTH=10 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN cmpr_ugc
+( 
+	aeb	:	output;
+	dataa[9..0]	:	input;
+	datab[9..0]	:	input;
+) 
+VARIABLE 
+	aeb_result_wire[0..0]	: WIRE;
+	aneb_result_wire[0..0]	: WIRE;
+	data_wire[26..0]	: WIRE;
+	eq_wire	: WIRE;
+
+BEGIN 
+	aeb = eq_wire;
+	aeb_result_wire[] = (! aneb_result_wire[]);
+	aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
+	data_wire[] = ( datab[9..9], dataa[9..9], datab[8..8], dataa[8..8], datab[7..7], dataa[7..7], datab[6..6], dataa[6..6], datab[5..5], dataa[5..5], datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], ((data_wire[23..23] $ data_wire[24..24]) # (data_wire[25..25] $ data_wire[26..26])), ((data_wire[19..19] $ data_wire[20..20]) # (data_wire[21..21] $ data_wire[22..22])), ((data_wire[15..15] $ data_wire[16..16]) # (data_wire[17..17] $ data_wire[18..18])), ((data_wire[11..11] $ data_wire[12..12]) # (data_wire[13..13] $ data_wire[14..14])), ((data_wire[7..7] $ data_wire[8..8]) # (data_wire[9..9] $ data_wire[10..10])), data_wire[6..6], (((data_wire[2..2] # data_wire[3..3]) # data_wire[4..4]) # data_wire[5..5]));
+	eq_wire = aeb_result_wire[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_vgc.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_vgc.tdf
new file mode 100644
index 0000000..835c6a1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_vgc.tdf
@@ -0,0 +1,41 @@
+--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" LPM_WIDTH=11 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN cmpr_vgc
+( 
+	aeb	:	output;
+	dataa[10..0]	:	input;
+	datab[10..0]	:	input;
+) 
+VARIABLE 
+	aeb_result_wire[0..0]	: WIRE;
+	aneb_result_wire[0..0]	: WIRE;
+	data_wire[29..0]	: WIRE;
+	eq_wire	: WIRE;
+
+BEGIN 
+	aeb = eq_wire;
+	aeb_result_wire[] = (! aneb_result_wire[]);
+	aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
+	data_wire[] = ( datab[10..10], dataa[10..10], datab[9..9], dataa[9..9], datab[8..8], dataa[8..8], datab[7..7], dataa[7..7], datab[6..6], dataa[6..6], datab[5..5], dataa[5..5], datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[28..28] $ data_wire[29..29]), ((data_wire[24..24] $ data_wire[25..25]) # (data_wire[26..26] $ data_wire[27..27])), ((data_wire[20..20] $ data_wire[21..21]) # (data_wire[22..22] $ data_wire[23..23])), ((data_wire[16..16] $ data_wire[17..17]) # (data_wire[18..18] $ data_wire[19..19])), ((data_wire[12..12] $ data_wire[13..13]) # (data_wire[14..14] $ data_wire[15..15])), ((data_wire[8..8] $ data_wire[9..9]) # (data_wire[10..10] $ data_wire[11..11])), (data_wire[6..6] # data_wire[7..7]), (((data_wire[2..2] # data_wire[3..3]) # data_wire[4..4]) # data_wire[5..5]));
+	eq_wire = aeb_result_wire[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf
new file mode 100644
index 0000000..ffc210e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf
@@ -0,0 +1,132 @@
+--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" lpm_direction="UP" lpm_modulus=798 lpm_port_updown="PORT_UNUSED" lpm_width=10 clk_en clock q
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+FUNCTION cmpr_ugc (dataa[9..0], datab[9..0])
+RETURNS ( aeb);
+
+--synthesis_resources = lut 10 reg 10 
+SUBDESIGN cntr_1tf
+( 
+	clk_en	:	input;
+	clock	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	counter_comb_bita0 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita1 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita2 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita3 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita4 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita5 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita6 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita7 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita8 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita9 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_reg_bit[9..0] : dffeas;
+	cmpr4 : cmpr_ugc;
+	aclr_actual	: WIRE;
+	cnt_en	: NODE;
+	compare_result	: WIRE;
+	cout_actual	: WIRE;
+	data[9..0]	: NODE;
+	external_cin	: WIRE;
+	modulus_bus[9..0]	: WIRE;
+	modulus_trigger	: WIRE;
+	s_val[9..0]	: WIRE;
+	safe_q[9..0]	: WIRE;
+	sclr	: NODE;
+	sload	: NODE;
+	sset	: NODE;
+	time_to_clear	: WIRE;
+	updown_dir	: WIRE;
+
+BEGIN 
+	counter_comb_bita[9..0].cin = ( counter_comb_bita[8..0].cout, external_cin);
+	counter_comb_bita[9..0].dataa = ( counter_reg_bit[9..0].q);
+	counter_comb_bita[9..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir);
+	counter_comb_bita[9..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1");
+	counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir))))));
+	counter_reg_bit[].clk = clock;
+	counter_reg_bit[].clrn = (! aclr_actual);
+	counter_reg_bit[].d = ( counter_comb_bita[9..0].combout);
+	counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
+	counter_reg_bit[].sload = (((sclr # sset) # sload) # modulus_trigger);
+	cmpr4.dataa[] = safe_q[];
+	cmpr4.datab[] = modulus_bus[];
+	aclr_actual = B"0";
+	cnt_en = VCC;
+	compare_result = cmpr4.aeb;
+	cout_actual = (counter_comb_bita[9].cout # (time_to_clear & updown_dir));
+	data[] = GND;
+	external_cin = B"1";
+	modulus_bus[] = B"1100011101";
+	modulus_trigger = cout_actual;
+	q[] = safe_q[];
+	s_val[] = B"1111111111";
+	safe_q[] = counter_reg_bit[].q;
+	sclr = GND;
+	sload = GND;
+	sset = GND;
+	time_to_clear = compare_result;
+	updown_dir = B"1";
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf
new file mode 100644
index 0000000..3790661
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf
@@ -0,0 +1,137 @@
+--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" lpm_direction="UP" lpm_modulus=1278 lpm_port_updown="PORT_UNUSED" lpm_width=11 clk_en clock q
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+FUNCTION cmpr_vgc (dataa[10..0], datab[10..0])
+RETURNS ( aeb);
+
+--synthesis_resources = lut 11 reg 11 
+SUBDESIGN cntr_cuf
+( 
+	clk_en	:	input;
+	clock	:	input;
+	q[10..0]	:	output;
+) 
+VARIABLE 
+	counter_comb_bita0 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita1 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita2 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita3 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita4 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita5 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita6 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita7 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita8 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita9 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita10 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_reg_bit[10..0] : dffeas;
+	cmpr4 : cmpr_vgc;
+	aclr_actual	: WIRE;
+	cnt_en	: NODE;
+	compare_result	: WIRE;
+	cout_actual	: WIRE;
+	data[10..0]	: NODE;
+	external_cin	: WIRE;
+	modulus_bus[10..0]	: WIRE;
+	modulus_trigger	: WIRE;
+	s_val[10..0]	: WIRE;
+	safe_q[10..0]	: WIRE;
+	sclr	: NODE;
+	sload	: NODE;
+	sset	: NODE;
+	time_to_clear	: WIRE;
+	updown_dir	: WIRE;
+
+BEGIN 
+	counter_comb_bita[10..0].cin = ( counter_comb_bita[9..0].cout, external_cin);
+	counter_comb_bita[10..0].dataa = ( counter_reg_bit[10..0].q);
+	counter_comb_bita[10..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir);
+	counter_comb_bita[10..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1");
+	counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir))))));
+	counter_reg_bit[].clk = clock;
+	counter_reg_bit[].clrn = (! aclr_actual);
+	counter_reg_bit[].d = ( counter_comb_bita[10..0].combout);
+	counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
+	counter_reg_bit[].sload = (((sclr # sset) # sload) # modulus_trigger);
+	cmpr4.dataa[] = safe_q[];
+	cmpr4.datab[] = modulus_bus[];
+	aclr_actual = B"0";
+	cnt_en = VCC;
+	compare_result = cmpr4.aeb;
+	cout_actual = (counter_comb_bita[10].cout # (time_to_clear & updown_dir));
+	data[] = GND;
+	external_cin = B"1";
+	modulus_bus[] = B"10011111101";
+	modulus_trigger = cout_actual;
+	q[] = safe_q[];
+	s_val[] = B"11111111111";
+	safe_q[] = counter_reg_bit[].q;
+	sclr = GND;
+	sload = GND;
+	sset = GND;
+	time_to_clear = compare_result;
+	updown_dir = B"1";
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf
new file mode 100644
index 0000000..c54465a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf
@@ -0,0 +1,168 @@
+--dcfifo_mixed_widths ADD_RAM_OUTPUT_REGISTER="OFF" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone III" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=512 LPM_SHOWAHEAD="OFF" LPM_WIDTH=16 LPM_WIDTH_R=16 LPM_WIDTHU=9 LPM_WIDTHU_R=9 OVERFLOW_CHECKING="ON" RAM_BLOCK_TYPE="M4K" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=M4K" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+--VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_dcfifo 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION a_gray2bin_tgb (gray[9..0])
+RETURNS ( bin[9..0]);
+FUNCTION a_graycounter_s57 (aclr, clock, cnt_en)
+RETURNS ( q[9..0]);
+FUNCTION a_graycounter_ojc (aclr, clock, cnt_en)
+RETURNS ( q[9..0]);
+FUNCTION altsyncram_de51 (aclr1, address_a[8..0], address_b[8..0], addressstall_b, clock0, clock1, clocken1, data_a[15..0], wren_a)
+RETURNS ( q_b[15..0]);
+FUNCTION dffpipe_oe9 (clock, clrn, d[9..0])
+RETURNS ( q[9..0]);
+FUNCTION alt_synch_pipe_qld (clock, clrn, d[9..0])
+RETURNS ( q[9..0]);
+FUNCTION alt_synch_pipe_rld (clock, clrn, d[9..0])
+RETURNS ( q[9..0]);
+FUNCTION cmpr_e66 (dataa[9..0], datab[9..0])
+RETURNS ( aeb);
+
+--synthesis_resources = lut 22 M9K 1 reg 138 
+OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;SYNCHRONIZER_IDENTIFICATION=OFF;SYNCHRONIZATION_REGISTER_CHAIN_LENGTH = 2;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=d103;{-to wrptr_g} suppress_da_rule_internal=S102;{-to wrptr_g} POWER_UP_LEVEL=LOW;-name CUT ON -from rdptr_g -to ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a;-name SDC_STATEMENT ""set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* "";-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* """;
+
+SUBDESIGN dcfifo_v5o1
+( 
+	aclr	:	input;
+	data[15..0]	:	input;
+	q[15..0]	:	output;
+	rdclk	:	input;
+	rdempty	:	output;
+	rdreq	:	input;
+	rdusedw[8..0]	:	output;
+	wrclk	:	input;
+	wrfull	:	output;
+	wrreq	:	input;
+	wrusedw[8..0]	:	output;
+) 
+VARIABLE 
+	rdptr_g_gray2bin : a_gray2bin_tgb;
+	rs_dgwp_gray2bin : a_gray2bin_tgb;
+	wrptr_g_gray2bin : a_gray2bin_tgb;
+	ws_dgrp_gray2bin : a_gray2bin_tgb;
+	rdptr_g1p : a_graycounter_s57;
+	wrptr_g1p : a_graycounter_ojc;
+	fifo_ram : altsyncram_de51;
+	delayed_wrptr_g[9..0] : dffe;
+	rdptr_g[9..0] : dffe;
+	wrptr_g[9..0] : dffe
+		WITH (
+			power_up = "low"
+		);
+	rs_brp : dffpipe_oe9;
+	rs_bwp : dffpipe_oe9;
+	rs_dgwp : alt_synch_pipe_qld;
+	ws_brp : dffpipe_oe9;
+	ws_bwp : dffpipe_oe9;
+	ws_dgrp : alt_synch_pipe_rld;
+	rdusedw_sub_dataa[9..0]	:	WIRE;
+	rdusedw_sub_datab[9..0]	:	WIRE;
+	rdusedw_sub_result[9..0]	:	WIRE;
+	wrusedw_sub_dataa[9..0]	:	WIRE;
+	wrusedw_sub_datab[9..0]	:	WIRE;
+	wrusedw_sub_result[9..0]	:	WIRE;
+	rdempty_eq_comp : cmpr_e66;
+	wrfull_eq_comp : cmpr_e66;
+	int_rdempty	: WIRE;
+	int_wrfull	: WIRE;
+	ram_address_a[8..0]	: WIRE;
+	ram_address_b[8..0]	: WIRE;
+	valid_rdreq	: WIRE;
+	valid_wrreq	: WIRE;
+	wrptr_gs[9..0]	: WIRE;
+
+BEGIN 
+	rdptr_g_gray2bin.gray[9..0] = rdptr_g[9..0].q;
+	rs_dgwp_gray2bin.gray[9..0] = rs_dgwp.q[9..0];
+	wrptr_g_gray2bin.gray[9..0] = wrptr_g[9..0].q;
+	ws_dgrp_gray2bin.gray[9..0] = ws_dgrp.q[9..0];
+	rdptr_g1p.aclr = aclr;
+	rdptr_g1p.clock = rdclk;
+	rdptr_g1p.cnt_en = valid_rdreq;
+	wrptr_g1p.aclr = aclr;
+	wrptr_g1p.clock = wrclk;
+	wrptr_g1p.cnt_en = valid_wrreq;
+	fifo_ram.aclr1 = aclr;
+	fifo_ram.address_a[] = ram_address_a[];
+	fifo_ram.address_b[] = ram_address_b[];
+	fifo_ram.addressstall_b = (! valid_rdreq);
+	fifo_ram.clock0 = wrclk;
+	fifo_ram.clock1 = rdclk;
+	fifo_ram.clocken1 = valid_rdreq;
+	fifo_ram.data_a[] = data[];
+	fifo_ram.wren_a = valid_wrreq;
+	delayed_wrptr_g[].clk = wrclk;
+	delayed_wrptr_g[].clrn = (! aclr);
+	delayed_wrptr_g[].d = wrptr_g[].q;
+	rdptr_g[].clk = rdclk;
+	rdptr_g[].clrn = (! aclr);
+	rdptr_g[].d = rdptr_g1p.q[];
+	rdptr_g[].ena = valid_rdreq;
+	wrptr_g[].clk = wrclk;
+	wrptr_g[].clrn = (! aclr);
+	wrptr_g[].d = wrptr_g1p.q[];
+	wrptr_g[].ena = valid_wrreq;
+	rs_brp.clock = rdclk;
+	rs_brp.clrn = (! aclr);
+	rs_brp.d[] = rdptr_g_gray2bin.bin[];
+	rs_bwp.clock = rdclk;
+	rs_bwp.clrn = (! aclr);
+	rs_bwp.d[] = rs_dgwp_gray2bin.bin[];
+	rs_dgwp.clock = rdclk;
+	rs_dgwp.clrn = (! aclr);
+	rs_dgwp.d[] = delayed_wrptr_g[].q;
+	ws_brp.clock = wrclk;
+	ws_brp.clrn = (! aclr);
+	ws_brp.d[] = ws_dgrp_gray2bin.bin[];
+	ws_bwp.clock = wrclk;
+	ws_bwp.clrn = (! aclr);
+	ws_bwp.d[] = wrptr_g_gray2bin.bin[];
+	ws_dgrp.clock = wrclk;
+	ws_dgrp.clrn = (! aclr);
+	ws_dgrp.d[] = rdptr_g[].q;
+	rdusedw_sub_result[] = rdusedw_sub_dataa[] - rdusedw_sub_datab[];
+	rdusedw_sub_dataa[] = rs_bwp.q[];
+	rdusedw_sub_datab[] = rs_brp.q[];
+	wrusedw_sub_result[] = wrusedw_sub_dataa[] - wrusedw_sub_datab[];
+	wrusedw_sub_dataa[] = ws_bwp.q[];
+	wrusedw_sub_datab[] = ws_brp.q[];
+	rdempty_eq_comp.dataa[] = rs_dgwp.q[];
+	rdempty_eq_comp.datab[] = rdptr_g[].q;
+	wrfull_eq_comp.dataa[] = ws_dgrp.q[];
+	wrfull_eq_comp.datab[] = wrptr_gs[];
+	int_rdempty = rdempty_eq_comp.aeb;
+	int_wrfull = wrfull_eq_comp.aeb;
+	q[] = fifo_ram.q_b[];
+	ram_address_a[] = ( (wrptr_g[9..9].q $ wrptr_g[8..8].q), wrptr_g[7..0].q);
+	ram_address_b[] = ( (rdptr_g1p.q[9..9] $ rdptr_g1p.q[8..8]), rdptr_g1p.q[7..0]);
+	rdempty = int_rdempty;
+	rdusedw[] = ( rdusedw_sub_result[8..0]);
+	valid_rdreq = (rdreq & (! int_rdempty));
+	valid_wrreq = (wrreq & (! int_wrfull));
+	wrfull = int_wrfull;
+	wrptr_gs[] = ( (! wrptr_g[9..9].q), (! wrptr_g[8..8].q), wrptr_g[7..0].q);
+	wrusedw[] = ( wrusedw_sub_result[8..0]);
+	ASSERT (0) 
+	REPORT "Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2"
+	SEVERITY WARNING;
+	ASSERT (0) 
+	REPORT "Device family Cyclone III does not have M4K blocks -- using available memory blocks"
+	SEVERITY WARNING;
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_oe9.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_oe9.tdf
new file mode 100644
index 0000000..b1ad734
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_oe9.tdf
@@ -0,0 +1,48 @@
+--dffpipe DELAY=1 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+--VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = reg 10 
+OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
+
+SUBDESIGN dffpipe_oe9
+( 
+	clock	:	input;
+	clrn	:	input;
+	d[9..0]	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	dffe12a[9..0] : dffe;
+	ena	: NODE;
+	prn	: NODE;
+	sclr	: NODE;
+
+BEGIN 
+	dffe12a[].clk = clock;
+	dffe12a[].clrn = clrn;
+	dffe12a[].d = (d[] & (! sclr));
+	dffe12a[].ena = ena;
+	dffe12a[].prn = prn;
+	ena = VCC;
+	prn = VCC;
+	q[] = dffe12a[].q;
+	sclr = GND;
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_pe9.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_pe9.tdf
new file mode 100644
index 0000000..5bd8385
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_pe9.tdf
@@ -0,0 +1,54 @@
+--dffpipe DELAY=2 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+--VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = reg 20 
+OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
+
+SUBDESIGN dffpipe_pe9
+( 
+	clock	:	input;
+	clrn	:	input;
+	d[9..0]	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	dffe14a[9..0] : dffe;
+	dffe15a[9..0] : dffe;
+	ena	: NODE;
+	prn	: NODE;
+	sclr	: NODE;
+
+BEGIN 
+	dffe14a[].clk = clock;
+	dffe14a[].clrn = clrn;
+	dffe14a[].d = (d[] & (! sclr));
+	dffe14a[].ena = ena;
+	dffe14a[].prn = prn;
+	dffe15a[].clk = clock;
+	dffe15a[].clrn = clrn;
+	dffe15a[].d = (dffe14a[].q & (! sclr));
+	dffe15a[].ena = ena;
+	dffe15a[].prn = prn;
+	ena = VCC;
+	prn = VCC;
+	q[] = dffe15a[].q;
+	sclr = GND;
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_qe9.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_qe9.tdf
new file mode 100644
index 0000000..3971343
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_qe9.tdf
@@ -0,0 +1,54 @@
+--dffpipe DELAY=2 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+--VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = reg 20 
+OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
+
+SUBDESIGN dffpipe_qe9
+( 
+	clock	:	input;
+	clrn	:	input;
+	d[9..0]	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	dffe17a[9..0] : dffe;
+	dffe18a[9..0] : dffe;
+	ena	: NODE;
+	prn	: NODE;
+	sclr	: NODE;
+
+BEGIN 
+	dffe17a[].clk = clock;
+	dffe17a[].clrn = clrn;
+	dffe17a[].d = (d[] & (! sclr));
+	dffe17a[].ena = ena;
+	dffe17a[].prn = prn;
+	dffe18a[].clk = clock;
+	dffe18a[].clrn = clrn;
+	dffe18a[].d = (dffe17a[].q & (! sclr));
+	dffe18a[].ena = ena;
+	dffe18a[].prn = prn;
+	ena = VCC;
+	prn = VCC;
+	q[] = dffe18a[].q;
+	sclr = GND;
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/logic_util_heursitic.dat b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..f4d26dd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/logic_util_heursitic.dat
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/mux_u7e.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/mux_u7e.tdf
new file mode 100644
index 0000000..95c482a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/mux_u7e.tdf
@@ -0,0 +1,97 @@
+--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone III" IGNORE_CASCADE_BUFFERS="OFF" LPM_PIPELINE=0 LPM_SIZE=4 LPM_WIDTH=30 LPM_WIDTHS=2 data result sel
+--VERSION_BEGIN 13.0 cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = lut 60 
+SUBDESIGN mux_u7e
+( 
+	data[119..0]	:	input;
+	result[29..0]	:	output;
+	sel[1..0]	:	input;
+) 
+VARIABLE 
+	result_node[29..0]	: WIRE;
+	sel_node[1..0]	: WIRE;
+	w_data109w[3..0]	: WIRE;
+	w_data134w[3..0]	: WIRE;
+	w_data159w[3..0]	: WIRE;
+	w_data184w[3..0]	: WIRE;
+	w_data209w[3..0]	: WIRE;
+	w_data234w[3..0]	: WIRE;
+	w_data259w[3..0]	: WIRE;
+	w_data284w[3..0]	: WIRE;
+	w_data309w[3..0]	: WIRE;
+	w_data334w[3..0]	: WIRE;
+	w_data34w[3..0]	: WIRE;
+	w_data359w[3..0]	: WIRE;
+	w_data384w[3..0]	: WIRE;
+	w_data409w[3..0]	: WIRE;
+	w_data434w[3..0]	: WIRE;
+	w_data459w[3..0]	: WIRE;
+	w_data484w[3..0]	: WIRE;
+	w_data4w[3..0]	: WIRE;
+	w_data509w[3..0]	: WIRE;
+	w_data534w[3..0]	: WIRE;
+	w_data559w[3..0]	: WIRE;
+	w_data584w[3..0]	: WIRE;
+	w_data59w[3..0]	: WIRE;
+	w_data609w[3..0]	: WIRE;
+	w_data634w[3..0]	: WIRE;
+	w_data659w[3..0]	: WIRE;
+	w_data684w[3..0]	: WIRE;
+	w_data709w[3..0]	: WIRE;
+	w_data734w[3..0]	: WIRE;
+	w_data84w[3..0]	: WIRE;
+
+BEGIN 
+	result[] = result_node[];
+	result_node[] = ( (((w_data734w[1..1] & sel_node[0..0]) & (! (((w_data734w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data734w[2..2]))))) # ((((w_data734w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data734w[2..2]))) & (w_data734w[3..3] # (! sel_node[0..0])))), (((w_data709w[1..1] & sel_node[0..0]) & (! (((w_data709w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data709w[2..2]))))) # ((((w_data709w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data709w[2..2]))) & (w_data709w[3..3] # (! sel_node[0..0])))), (((w_data684w[1..1] & sel_node[0..0]) & (! (((w_data684w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data684w[2..2]))))) # ((((w_data684w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data684w[2..2]))) & (w_data684w[3..3] # (! sel_node[0..0])))), (((w_data659w[1..1] & sel_node[0..0]) & (! (((w_data659w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data659w[2..2]))))) # ((((w_data659w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data659w[2..2]))) & (w_data659w[3..3] # (! sel_node[0..0])))), (((w_data634w[1..1] & sel_node[0..0]) & (! (((w_data634w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data634w[2..2]))))) # ((((w_data634w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data634w[2..2]))) & (w_data634w[3..3] # (! sel_node[0..0])))), (((w_data609w[1..1] & sel_node[0..0]) & (! (((w_data609w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data609w[2..2]))))) # ((((w_data609w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data609w[2..2]))) & (w_data609w[3..3] # (! sel_node[0..0])))), (((w_data584w[1..1] & sel_node[0..0]) & (! (((w_data584w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data584w[2..2]))))) # ((((w_data584w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data584w[2..2]))) & (w_data584w[3..3] # (! sel_node[0..0])))), (((w_data559w[1..1] & sel_node[0..0]) & (! (((w_data559w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data559w[2..2]))))) # ((((w_data559w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data559w[2..2]))) & (w_data559w[3..3] # (! sel_node[0..0])))), (((w_data534w[1..1] & sel_node[0..0]) & (! (((w_data534w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data534w[2..2]))))) # ((((w_data534w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data534w[2..2]))) & (w_data534w[3..3] # (! sel_node[0..0])))), (((w_data509w[1..1] & sel_node[0..0]) & (! (((w_data509w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data509w[2..2]))))) # ((((w_data509w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data509w[2..2]))) & (w_data509w[3..3] # (! sel_node[0..0])))), (((w_data484w[1..1] & sel_node[0..0]) & (! (((w_data484w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data484w[2..2]))))) # ((((w_data484w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data484w[2..2]))) & (w_data484w[3..3] # (! sel_node[0..0])))), (((w_data459w[1..1] & sel_node[0..0]) & (! (((w_data459w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data459w[2..2]))))) # ((((w_data459w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data459w[2..2]))) & (w_data459w[3..3] # (! sel_node[0..0])))), (((w_data434w[1..1] & sel_node[0..0]) & (! (((w_data434w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data434w[2..2]))))) # ((((w_data434w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data434w[2..2]))) & (w_data434w[3..3] # (! sel_node[0..0])))), (((w_data409w[1..1] & sel_node[0..0]) & (! (((w_data409w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data409w[2..2]))))) # ((((w_data409w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data409w[2..2]))) & (w_data409w[3..3] # (! sel_node[0..0])))), (((w_data384w[1..1] & sel_node[0..0]) & (! (((w_data384w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data384w[2..2]))))) # ((((w_data384w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data384w[2..2]))) & (w_data384w[3..3] # (! sel_node[0..0])))), (((w_data359w[1..1] & sel_node[0..0]) & (! (((w_data359w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data359w[2..2]))))) # ((((w_data359w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data359w[2..2]))) & (w_data359w[3..3] # (! sel_node[0..0])))), (((w_data334w[1..1] & sel_node[0..0]) & (! (((w_data334w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data334w[2..2]))))) # ((((w_data334w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data334w[2..2]))) & (w_data334w[3..3] # (! sel_node[0..0])))), (((w_data309w[1..1] & sel_node[0..0]) & (! (((w_data309w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data309w[2..2]))))) # ((((w_data309w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data309w[2..2]))) & (w_data309w[3..3] # (! sel_node[0..0])))), (((w_data284w[1..1] & sel_node[0..0]) & (! (((w_data284w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data284w[2..2]))))) # ((((w_data284w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data284w[2..2]))) & (w_data284w[3..3] # (! sel_node[0..0])))), (((w_data259w[1..1] & sel_node[0..0]) & (! (((w_data259w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data259w[2..2]))))) # ((((w_data259w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data259w[2..2]))) & (w_data259w[3..3] # (! sel_node[0..0])))), (((w_data234w[1..1] & sel_node[0..0]) & (! (((w_data234w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data234w[2..2]))))) # ((((w_data234w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data234w[2..2]))) & (w_data234w[3..3] # (! sel_node[0..0])))), (((w_data209w[1..1] & sel_node[0..0]) & (! (((w_data209w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data209w[2..2]))))) # ((((w_data209w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data209w[2..2]))) & (w_data209w[3..3] # (! sel_node[0..0])))), (((w_data184w[1..1] & sel_node[0..0]) & (! (((w_data184w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data184w[2..2]))))) # ((((w_data184w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data184w[2..2]))) & (w_data184w[3..3] # (! sel_node[0..0])))), (((w_data159w[1..1] & sel_node[0..0]) & (! (((w_data159w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data159w[2..2]))))) # ((((w_data159w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data159w[2..2]))) & (w_data159w[3..3] # (! sel_node[0..0])))), (((w_data134w[1..1] & sel_node[0..0]) & (! (((w_data134w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data134w[2..2]))))) # ((((w_data134w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data134w[2..2]))) & (w_data134w[3..3] # (! sel_node[0..0])))), (((w_data109w[1..1] & sel_node[0..0]) & (! (((w_data109w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data109w[2..2]))))) # ((((w_data109w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data109w[2..2]))) & (w_data109w[3..3] # (! sel_node[0..0])))), (((w_data84w[1..1] & sel_node[0..0]) & (! (((w_data84w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data84w[2..2]))))) # ((((w_data84w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data84w[2..2]))) & (w_data84w[3..3] # (! sel_node[0..0])))), (((w_data59w[1..1] & sel_node[0..0]) & (! (((w_data59w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data59w[2..2]))))) # ((((w_data59w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data59w[2..2]))) & (w_data59w[3..3] # (! sel_node[0..0])))), (((w_data34w[1..1] & sel_node[0..0]) & (! (((w_data34w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data34w[2..2]))))) # ((((w_data34w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data34w[2..2]))) & (w_data34w[3..3] # (! sel_node[0..0])))), (((w_data4w[1..1] & sel_node[0..0]) & (! (((w_data4w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data4w[2..2]))))) # ((((w_data4w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data4w[2..2]))) & (w_data4w[3..3] # (! sel_node[0..0])))));
+	sel_node[] = ( sel[1..0]);
+	w_data109w[] = ( data[94..94], data[64..64], data[34..34], data[4..4]);
+	w_data134w[] = ( data[95..95], data[65..65], data[35..35], data[5..5]);
+	w_data159w[] = ( data[96..96], data[66..66], data[36..36], data[6..6]);
+	w_data184w[] = ( data[97..97], data[67..67], data[37..37], data[7..7]);
+	w_data209w[] = ( data[98..98], data[68..68], data[38..38], data[8..8]);
+	w_data234w[] = ( data[99..99], data[69..69], data[39..39], data[9..9]);
+	w_data259w[] = ( data[100..100], data[70..70], data[40..40], data[10..10]);
+	w_data284w[] = ( data[101..101], data[71..71], data[41..41], data[11..11]);
+	w_data309w[] = ( data[102..102], data[72..72], data[42..42], data[12..12]);
+	w_data334w[] = ( data[103..103], data[73..73], data[43..43], data[13..13]);
+	w_data34w[] = ( data[91..91], data[61..61], data[31..31], data[1..1]);
+	w_data359w[] = ( data[104..104], data[74..74], data[44..44], data[14..14]);
+	w_data384w[] = ( data[105..105], data[75..75], data[45..45], data[15..15]);
+	w_data409w[] = ( data[106..106], data[76..76], data[46..46], data[16..16]);
+	w_data434w[] = ( data[107..107], data[77..77], data[47..47], data[17..17]);
+	w_data459w[] = ( data[108..108], data[78..78], data[48..48], data[18..18]);
+	w_data484w[] = ( data[109..109], data[79..79], data[49..49], data[19..19]);
+	w_data4w[] = ( data[90..90], data[60..60], data[30..30], data[0..0]);
+	w_data509w[] = ( data[110..110], data[80..80], data[50..50], data[20..20]);
+	w_data534w[] = ( data[111..111], data[81..81], data[51..51], data[21..21]);
+	w_data559w[] = ( data[112..112], data[82..82], data[52..52], data[22..22]);
+	w_data584w[] = ( data[113..113], data[83..83], data[53..53], data[23..23]);
+	w_data59w[] = ( data[92..92], data[62..62], data[32..32], data[2..2]);
+	w_data609w[] = ( data[114..114], data[84..84], data[54..54], data[24..24]);
+	w_data634w[] = ( data[115..115], data[85..85], data[55..55], data[25..25]);
+	w_data659w[] = ( data[116..116], data[86..86], data[56..56], data[26..26]);
+	w_data684w[] = ( data[117..117], data[87..87], data[57..57], data[27..27]);
+	w_data709w[] = ( data[118..118], data[88..88], data[58..58], data[28..28]);
+	w_data734w[] = ( data[119..119], data[89..89], data[59..59], data[29..29]);
+	w_data84w[] = ( data[93..93], data[63..63], data[33..33], data[3..3]);
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/prev_cmp_DE0_D5M.qmsg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/prev_cmp_DE0_D5M.qmsg
new file mode 100644
index 0000000..c28e33c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/prev_cmp_DE0_D5M.qmsg
@@ -0,0 +1,440 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1457452784979 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457452784986 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 15:59:44 2016 " "Processing started: Tue Mar 08 15:59:44 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457452784986 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1457452784986 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M " "Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1457452784986 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1457452789888 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "//icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel quartus/sobel.v 2 2 " "Found 2 design units, including 2 entities, in source file //icnas3.cc.ic.ac.uk/mg3115/eie1 fpga/sobel filter catapult/sobel/sobel quartus/sobel.v" { { "Info" "ISGN_ENTITY_NAME" "1 sobel_core " "Found entity 1: sobel_core" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790217 ""} { "Info" "ISGN_ENTITY_NAME" "2 sobel " "Found entity 2: sobel" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 876 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790217 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790217 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/ps2.v 1 1 " "Found 1 design units, including 1 entities, in source file v/ps2.v" { { "Info" "ISGN_ENTITY_NAME" "1 ps2 " "Found entity 1: ps2" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790263 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790263 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/command.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/command.v" { { "Info" "ISGN_ENTITY_NAME" "1 command " "Found entity 1: command" {  } { { "Sdram_Control_4Port/command.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790325 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790325 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/control_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/control_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_interface " "Found entity 1: control_interface" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790370 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790370 ""}
+{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 sdr_data_path.v(68) " "Verilog HDL Expression warning at sdr_data_path.v(68): truncated literal to match 1 bits" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v" 68 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1457452790412 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdr_data_path.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/sdr_data_path.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdr_data_path " "Found entity 1: sdr_data_path" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790414 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790414 ""}
+{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "Sdram_Control_4Port Sdram_Control_4Port.v(90) " "Verilog Module Declaration warning at Sdram_Control_4Port.v(90): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"Sdram_Control_4Port\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 90 0 0 } }  } 0 10238 "Verilog Module Declaration warning at %2!s!: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452790460 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdram_control_4port.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_control_4port.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_Control_4Port " "Found entity 1: Sdram_Control_4Port" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790462 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790462 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdram_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_FIFO " "Found entity 1: Sdram_FIFO" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790494 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790494 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "V/async_receiver.v " "Can't analyze file -- file V/async_receiver.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1457452790562 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/ccd_capture.v 1 1 " "Found 1 design units, including 1 entities, in source file v/ccd_capture.v" { { "Info" "ISGN_ENTITY_NAME" "1 CCD_Capture " "Found entity 1: CCD_Capture" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790606 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790606 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/i2c_ccd_config.v 1 1 " "Found 1 design units, including 1 entities, in source file v/i2c_ccd_config.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_CCD_Config " "Found entity 1: I2C_CCD_Config" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790639 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790639 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/i2c_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file v/i2c_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_Controller " "Found entity 1: I2C_Controller" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790677 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790677 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/line_buffer.v 1 1 " "Found 1 design units, including 1 entities, in source file v/line_buffer.v" { { "Info" "ISGN_ENTITY_NAME" "1 Line_Buffer " "Found entity 1: Line_Buffer" {  } { { "V/Line_Buffer.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790719 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790719 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/raw2rgb.v 1 1 " "Found 1 design units, including 1 entities, in source file v/raw2rgb.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAW2RGB " "Found entity 1: RAW2RGB" {  } { { "V/RAW2RGB.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790765 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790765 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/reset_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file v/reset_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Found entity 1: Reset_Delay" {  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790803 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790803 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/sdram_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file v/sdram_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_pll " "Found entity 1: sdram_pll" {  } { { "V/sdram_pll.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790840 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790840 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/seg7_lut.v 1 1 " "Found 1 design units, including 1 entities, in source file v/seg7_lut.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT " "Found entity 1: SEG7_LUT" {  } { { "V/SEG7_LUT.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790881 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790881 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/seg7_lut_8.v 1 1 " "Found 1 design units, including 1 entities, in source file v/seg7_lut_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT_8 " "Found entity 1: SEG7_LUT_8" {  } { { "V/SEG7_LUT_8.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790915 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790915 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/vga_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file v/vga_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 VGA_Controller " "Found entity 1: VGA_Controller" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 13 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452790969 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452790969 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de0_d5m.v 1 1 " "Found 1 design units, including 1 entities, in source file de0_d5m.v" { { "Info" "ISGN_ENTITY_NAME" "1 DE0_D5M " "Found entity 1: DE0_D5M" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791035 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452791035 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/top_de0_camera_mouse.bdf 1 1 " "Found 1 design units, including 1 entities, in source file v/top_de0_camera_mouse.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TOP_DE0_CAMERA_MOUSE " "Found entity 1: TOP_DE0_CAMERA_MOUSE" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791129 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452791129 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_mux.vhd 2 1 " "Found 2 design units, including 1 entities, in source file vga_mux.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vga_mux-SYN " "Found design unit 1: vga_mux-SYN" {  } { { "vga_mux.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 55 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791878 ""} { "Info" "ISGN_ENTITY_NAME" "1 vga_mux " "Found entity 1: vga_mux" {  } { { "vga_mux.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791878 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452791878 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catapult_ip/mouse/rtl_mgc_ioport_v2001.v 7 7 " "Found 7 design units, including 7 entities, in source file catapult_ip/mouse/rtl_mgc_ioport_v2001.v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_out_reg_pos " "Found entity 1: mgc_out_reg_pos" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_out_reg_neg " "Found entity 2: mgc_out_reg_neg" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 68 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_out_reg " "Found entity 3: mgc_out_reg" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 133 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_out_buf_wait " "Found entity 4: mgc_out_buf_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 210 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_fifo_wait " "Found entity 5: mgc_out_fifo_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 296 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_fifo_wait_core " "Found entity 6: mgc_out_fifo_wait_core" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 353 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_pipe " "Found entity 7: mgc_pipe" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 644 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452791911 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catapult_ip/mouse/rtl_mgc_ioport.v 20 20 " "Found 20 design units, including 20 entities, in source file catapult_ip/mouse/rtl_mgc_ioport.v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_in_wire " "Found entity 1: mgc_in_wire" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 13 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_in_wire_en " "Found entity 2: mgc_in_wire_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_in_wire_wait " "Found entity 3: mgc_in_wire_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_chan_in " "Found entity 4: mgc_chan_in" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 72 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_stdreg " "Found entity 5: mgc_out_stdreg" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 109 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_stdreg_en " "Found entity 6: mgc_out_stdreg_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 125 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_out_stdreg_wait " "Found entity 7: mgc_out_stdreg_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 145 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "8 mgc_out_prereg_en " "Found entity 8: mgc_out_prereg_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 169 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "9 mgc_inout_stdreg_en " "Found entity 9: mgc_inout_stdreg_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 191 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "10 hid_tribuf " "Found entity 10: hid_tribuf" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 217 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "11 mgc_inout_stdreg_wait " "Found entity 11: mgc_inout_stdreg_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 229 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "12 mgc_inout_buf_wait " "Found entity 12: mgc_inout_buf_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 269 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "13 mgc_inout_fifo_wait " "Found entity 13: mgc_inout_fifo_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 339 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "14 mgc_io_sync " "Found entity 14: mgc_io_sync" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 419 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "15 mgc_bsync_rdy " "Found entity 15: mgc_bsync_rdy" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 428 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "16 mgc_bsync_vld " "Found entity 16: mgc_bsync_vld" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 443 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "17 mgc_bsync_rv " "Found entity 17: mgc_bsync_rv" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 458 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "18 mgc_sync " "Found entity 18: mgc_sync" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 479 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "19 funccall_inout " "Found entity 19: funccall_inout" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 498 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""} { "Info" "ISGN_ENTITY_NAME" "20 modulario_en_in " "Found entity 20: modulario_en_in" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 526 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452792426 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catapult_ip/mouse/rtl.v 2 2 " "Found 2 design units, including 2 entities, in source file catapult_ip/mouse/rtl.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_mouse_square_core " "Found entity 1: vga_mouse_square_core" {  } { { "catapult_ip/mouse/rtl.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792483 ""} { "Info" "ISGN_ENTITY_NAME" "2 vga_mouse_square " "Found entity 2: vga_mouse_square" {  } { { "catapult_ip/mouse/rtl.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 110 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452792483 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452792483 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "TOP_DE0_CAMERA_MOUSE " "Elaborating entity \"TOP_DE0_CAMERA_MOUSE\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1457452795467 ""}
+{ "Warning" "WGDFX_NO_SUPERSET_FOUND" "" "No superset bus at connection" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 912 1008 1120 928 "MOUSE_X\[1..0\]" "" } { 928 1008 1120 944 "MOUSE_Y\[1..0\]" "" } { 928 1008 1008 944 "" "" } { 944 1008 1008 952 "" "" } } } }  } 0 275002 "No superset bus at connection" 0 0 "Quartus II" 0 -1 1457452795479 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DE0_D5M DE0_D5M:inst " "Elaborating entity \"DE0_D5M\" for hierarchy \"DE0_D5M:inst\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795505 ""}
+{ "Critical Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "VGA_R DE0_D5M.v(118) " "Verilog HDL warning at DE0_D5M.v(118): the port and data declarations for array port \"VGA_R\" do not specify the same range for each dimension" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 118 0 0 } }  } 1 10169 "Verilog HDL warning at %2!s!: the port and data declarations for array port \"%1!s!\" do not specify the same range for each dimension" 0 0 "Quartus II" 0 -1 1457452795520 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_HDL_SEE_DECLARATION" "VGA_R DE0_D5M.v(166) " "HDL warning at DE0_D5M.v(166): see declaration for object \"VGA_R\"" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 166 0 0 } }  } 0 10359 "HDL warning at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452795520 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Critical Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "VGA_G DE0_D5M.v(119) " "Verilog HDL warning at DE0_D5M.v(119): the port and data declarations for array port \"VGA_G\" do not specify the same range for each dimension" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 119 0 0 } }  } 1 10169 "Verilog HDL warning at %2!s!: the port and data declarations for array port \"%1!s!\" do not specify the same range for each dimension" 0 0 "Quartus II" 0 -1 1457452795520 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_HDL_SEE_DECLARATION" "VGA_G DE0_D5M.v(167) " "HDL warning at DE0_D5M.v(167): see declaration for object \"VGA_G\"" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 167 0 0 } }  } 0 10359 "HDL warning at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452795521 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Critical Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "VGA_B DE0_D5M.v(120) " "Verilog HDL warning at DE0_D5M.v(120): the port and data declarations for array port \"VGA_B\" do not specify the same range for each dimension" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 120 0 0 } }  } 1 10169 "Verilog HDL warning at %2!s!: the port and data declarations for array port \"%1!s!\" do not specify the same range for each dimension" 0 0 "Quartus II" 0 -1 1457452795521 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_HDL_SEE_DECLARATION" "VGA_B DE0_D5M.v(168) " "HDL warning at DE0_D5M.v(168): see declaration for object \"VGA_B\"" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 168 0 0 } }  } 0 10359 "HDL warning at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452795521 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "16 10 DE0_D5M.v(197) " "Verilog HDL assignment warning at DE0_D5M.v(197): truncated value with size 16 to match size of target (10)" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 197 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795521 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 DE0_D5M.v(202) " "Verilog HDL assignment warning at DE0_D5M.v(202): truncated value with size 32 to match size of target (2)" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795522 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1_CLKOUT\[1\] DE0_D5M.v(128) " "Output port \"GPIO_1_CLKOUT\[1\]\" at DE0_D5M.v(128) has no driver" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 128 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1457452795522 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA_Controller DE0_D5M:inst\|VGA_Controller:u1 " "Elaborating entity \"VGA_Controller\" for hierarchy \"DE0_D5M:inst\|VGA_Controller:u1\"" {  } { { "DE0_D5M.v" "u1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 253 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795550 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(70) " "Verilog HDL assignment warning at VGA_Controller.v(70): truncated value with size 32 to match size of target (10)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795562 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(73) " "Verilog HDL assignment warning at VGA_Controller.v(73): truncated value with size 32 to match size of target (10)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795564 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(76) " "Verilog HDL assignment warning at VGA_Controller.v(76): truncated value with size 32 to match size of target (10)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795564 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 VGA_Controller.v(115) " "Verilog HDL assignment warning at VGA_Controller.v(115): truncated value with size 32 to match size of target (12)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 115 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795564 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 VGA_Controller.v(146) " "Verilog HDL assignment warning at VGA_Controller.v(146): truncated value with size 32 to match size of target (12)" {  } { { "V/VGA_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 146 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795564 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay DE0_D5M:inst\|Reset_Delay:u2 " "Elaborating entity \"Reset_Delay\" for hierarchy \"DE0_D5M:inst\|Reset_Delay:u2\"" {  } { { "DE0_D5M.v" "u2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 262 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795594 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CCD_Capture DE0_D5M:inst\|CCD_Capture:u3 " "Elaborating entity \"CCD_Capture\" for hierarchy \"DE0_D5M:inst\|CCD_Capture:u3\"" {  } { { "DE0_D5M.v" "u3" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 277 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795627 ""}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ifval_fedge CCD_Capture.v(162) " "Verilog HDL or VHDL warning at CCD_Capture.v(162): object \"ifval_fedge\" assigned a value but never read" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 162 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1457452795641 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "y_cnt_d CCD_Capture.v(163) " "Verilog HDL or VHDL warning at CCD_Capture.v(163): object \"y_cnt_d\" assigned a value but never read" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 163 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1457452795642 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 CCD_Capture.v(123) " "Verilog HDL assignment warning at CCD_Capture.v(123): truncated value with size 32 to match size of target (16)" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 123 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795642 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 CCD_Capture.v(127) " "Verilog HDL assignment warning at CCD_Capture.v(127): truncated value with size 32 to match size of target (16)" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 127 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795643 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CCD_Capture.v(183) " "Verilog HDL assignment warning at CCD_Capture.v(183): truncated value with size 32 to match size of target (1)" {  } { { "V/CCD_Capture.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 183 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452795643 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAW2RGB DE0_D5M:inst\|RAW2RGB:u4 " "Elaborating entity \"RAW2RGB\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\"" {  } { { "DE0_D5M.v" "u4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 290 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795668 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Line_Buffer DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0 " "Elaborating entity \"Line_Buffer\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\"" {  } { { "V/RAW2RGB.v" "u0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v" 83 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795760 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift_taps DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Elaborating entity \"altshift_taps\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\"" {  } { { "V/Line_Buffer.v" "altshift_taps_component" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 67 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795938 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Elaborated megafunction instantiation \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\"" {  } { { "V/Line_Buffer.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 67 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452795953 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Instantiated megafunction \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altshift_taps " "Parameter \"lpm_type\" = \"altshift_taps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_taps 2 " "Parameter \"number_of_taps\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "tap_distance 1280 " "Parameter \"tap_distance\" = \"1280\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 12 " "Parameter \"width\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452795964 ""}  } { { "V/Line_Buffer.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 67 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452795964 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_rnn.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/shift_taps_rnn.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_rnn " "Found entity 1: shift_taps_rnn" {  } { { "db/shift_taps_rnn.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452796127 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452796127 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_taps_rnn DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated " "Elaborating entity \"shift_taps_rnn\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\"" {  } { { "altshift_taps.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796143 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_lp81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_lp81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_lp81 " "Found entity 1: altsyncram_lp81" {  } { { "db/altsyncram_lp81.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_lp81.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452796356 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452796356 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_lp81 DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|altsyncram_lp81:altsyncram2 " "Elaborating entity \"altsyncram_lp81\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|altsyncram_lp81:altsyncram2\"" {  } { { "db/shift_taps_rnn.tdf" "altsyncram2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf" 35 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796371 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_cuf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_cuf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_cuf " "Found entity 1: cntr_cuf" {  } { { "db/cntr_cuf.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452796527 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452796527 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_cuf DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1 " "Elaborating entity \"cntr_cuf\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1\"" {  } { { "db/shift_taps_rnn.tdf" "cntr1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf" 36 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796544 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_vgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_vgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_vgc " "Found entity 1: cmpr_vgc" {  } { { "db/cmpr_vgc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_vgc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452796691 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452796691 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_vgc DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1\|cmpr_vgc:cmpr4 " "Elaborating entity \"cmpr_vgc\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1\|cmpr_vgc:cmpr4\"" {  } { { "db/cntr_cuf.tdf" "cmpr4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf" 90 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796707 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT_8 DE0_D5M:inst\|SEG7_LUT_8:u5 " "Elaborating entity \"SEG7_LUT_8\" for hierarchy \"DE0_D5M:inst\|SEG7_LUT_8:u5\"" {  } { { "DE0_D5M.v" "u5" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 302 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796745 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT DE0_D5M:inst\|SEG7_LUT_8:u5\|SEG7_LUT:u0 " "Elaborating entity \"SEG7_LUT\" for hierarchy \"DE0_D5M:inst\|SEG7_LUT_8:u5\|SEG7_LUT:u0\"" {  } { { "V/SEG7_LUT_8.v" "u0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v" 47 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796774 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_pll DE0_D5M:inst\|sdram_pll:u6 " "Elaborating entity \"sdram_pll\" for hierarchy \"DE0_D5M:inst\|sdram_pll:u6\"" {  } { { "DE0_D5M.v" "u6" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 308 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452796986 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\"" {  } { { "V/sdram_pll.v" "altpll_component" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797174 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component " "Elaborated megafunction instantiation \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\"" {  } { { "V/sdram_pll.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component " "Instantiated megafunction \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2 " "Parameter \"clk0_divide_by\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5 " "Parameter \"clk0_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 2 " "Parameter \"clk1_divide_by\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 5 " "Parameter \"clk1_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift -2600 " "Parameter \"clk1_phase_shift\" = \"-2600\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone III " "Parameter \"intended_device_family\" = \"Cyclone III\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797193 ""}  } { { "V/sdram_pll.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452797193 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altpll_9ee2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altpll_9ee2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll_9ee2 " "Found entity 1: altpll_9ee2" {  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452797369 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452797369 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_9ee2 DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated " "Elaborating entity \"altpll_9ee2\" for hierarchy \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797383 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Sdram_Control_4Port DE0_D5M:inst\|Sdram_Control_4Port:u7 " "Elaborating entity \"Sdram_Control_4Port\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\"" {  } { { "DE0_D5M.v" "u7" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 364 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797430 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Sdram_Control_4Port.v(385) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(385): truncated value with size 32 to match size of target (10)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 385 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797454 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(431) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(431): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 431 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797454 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(432) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(432): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 432 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797455 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(433) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(433): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 433 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797456 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(434) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(434): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 434 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797456 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rWR1_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rWR1_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797456 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rWR2_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rWR2_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797456 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rRD1_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rRD1_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797457 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rRD2_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rRD2_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797458 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797458 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797458 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797459 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797459 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797459 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797459 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797460 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797460 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797460 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797461 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797461 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797461 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797461 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797462 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797462 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797462 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797463 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797463 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797463 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797463 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797464 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797464 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797464 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797465 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797465 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797465 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797465 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797465 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797467 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797467 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797467 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797467 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797467 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797467 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797468 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797469 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797469 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797469 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797469 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797469 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797470 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797470 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797471 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797471 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797471 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797471 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797471 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797471 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797472 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797473 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797473 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797473 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797473 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797473 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797473 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797474 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797474 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797475 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797475 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797475 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797475 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797475 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797476 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797476 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797477 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797477 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797477 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797477 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797477 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797477 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797478 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797479 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797479 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797479 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797479 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797479 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797479 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797480 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797480 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797481 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797481 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797481 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797481 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797481 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797482 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797482 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797483 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797483 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797483 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797483 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797483 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1457452797483 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_interface DE0_D5M:inst\|Sdram_Control_4Port:u7\|control_interface:control1 " "Elaborating entity \"control_interface\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|control_interface:control1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "control1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 237 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797505 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(162) " "Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 162 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797522 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(167) " "Verilog HDL assignment warning at control_interface.v(167): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 167 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797522 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(192) " "Verilog HDL assignment warning at control_interface.v(192): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 192 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797522 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "command DE0_D5M:inst\|Sdram_Control_4Port:u7\|command:command1 " "Elaborating entity \"command\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|command:command1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "command1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 263 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797544 ""}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe_shift command.v(275) " "Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe_shift\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797555 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe1 command.v(275) " "Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe1\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797555 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe2 command.v(275) " "Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe2\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1457452797557 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdr_data_path DE0_D5M:inst\|Sdram_Control_4Port:u7\|sdr_data_path:data_path1 " "Elaborating entity \"sdr_data_path\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|sdr_data_path:data_path1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "data_path1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 272 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797578 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 sdr_data_path.v(68) " "Verilog HDL assignment warning at sdr_data_path.v(68): truncated value with size 32 to match size of target (2)" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v" 68 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452797585 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Sdram_FIFO DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1 " "Elaborating entity \"Sdram_FIFO\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "write_fifo1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 283 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797664 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Elaborating entity \"dcfifo\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\"" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "dcfifo_component" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797913 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Elaborated megafunction instantiation \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\"" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452797920 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Instantiated megafunction \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register OFF " "Parameter \"add_ram_output_register\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clocks_are_synchronized FALSE " "Parameter \"clocks_are_synchronized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone " "Parameter \"intended_device_family\" = \"Cyclone\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=M4K " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=M4K\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 512 " "Parameter \"lpm_numwords\" = \"512\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type dcfifo " "Parameter \"lpm_type\" = \"dcfifo\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 16 " "Parameter \"lpm_width\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 9 " "Parameter \"lpm_widthu\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452797921 ""}  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452797921 ""}
+{ "Warning" "WTDFX_ASSERTION" "Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 " "Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2" {  } { { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 161 2 0 } }  } 0 287001 "Assertion warning: %1!s!" 0 0 "Quartus II" 0 -1 1457452798118 ""}
+{ "Warning" "WTDFX_ASSERTION" "Device family Cyclone III does not have M4K blocks -- using available memory blocks " "Assertion warning: Device family Cyclone III does not have M4K blocks -- using available memory blocks" {  } { { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 164 2 0 } }  } 0 287001 "Assertion warning: %1!s!" 0 0 "Quartus II" 0 -1 1457452798119 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dcfifo_v5o1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dcfifo_v5o1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo_v5o1 " "Found entity 1: dcfifo_v5o1" {  } { { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 40 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452798124 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452798124 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo_v5o1 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated " "Elaborating entity \"dcfifo_v5o1\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\"" {  } { { "dcfifo.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452798145 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_gray2bin_tgb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_gray2bin_tgb " "Found entity 1: a_gray2bin_tgb" {  } { { "db/a_gray2bin_tgb.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_gray2bin_tgb.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452798276 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452798276 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_gray2bin_tgb DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_gray2bin_tgb:rdptr_g_gray2bin " "Elaborating entity \"a_gray2bin_tgb\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_gray2bin_tgb:rdptr_g_gray2bin\"" {  } { { "db/dcfifo_v5o1.tdf" "rdptr_g_gray2bin" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 55 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452798294 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_s57.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_s57 " "Found entity 1: a_graycounter_s57" {  } { { "db/a_graycounter_s57.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452798508 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452798508 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_s57 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_s57:rdptr_g1p " "Elaborating entity \"a_graycounter_s57\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_s57:rdptr_g1p\"" {  } { { "db/dcfifo_v5o1.tdf" "rdptr_g1p" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 59 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452798523 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_ojc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_ojc " "Found entity 1: a_graycounter_ojc" {  } { { "db/a_graycounter_ojc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452798671 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452798671 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_ojc DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_ojc:wrptr_g1p " "Elaborating entity \"a_graycounter_ojc\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_ojc:wrptr_g1p\"" {  } { { "db/dcfifo_v5o1.tdf" "wrptr_g1p" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 60 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452798686 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_de51.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_de51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_de51 " "Found entity 1: altsyncram_de51" {  } { { "db/altsyncram_de51.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452798866 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452798866 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_de51 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram " "Elaborating entity \"altsyncram_de51\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\"" {  } { { "db/dcfifo_v5o1.tdf" "fifo_ram" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 61 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452798884 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_oe9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_oe9 " "Found entity 1: dffpipe_oe9" {  } { { "db/dffpipe_oe9.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_oe9.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452799021 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452799021 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_oe9 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|dffpipe_oe9:rs_brp " "Elaborating entity \"dffpipe_oe9\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|dffpipe_oe9:rs_brp\"" {  } { { "db/dcfifo_v5o1.tdf" "rs_brp" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 68 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452799043 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_qld.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_qld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_qld " "Found entity 1: alt_synch_pipe_qld" {  } { { "db/alt_synch_pipe_qld.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452799171 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452799171 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_qld DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp " "Elaborating entity \"alt_synch_pipe_qld\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp\"" {  } { { "db/dcfifo_v5o1.tdf" "rs_dgwp" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 70 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452799187 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_pe9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_pe9 " "Found entity 1: dffpipe_pe9" {  } { { "db/dffpipe_pe9.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_pe9.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452799299 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452799299 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_pe9 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp\|dffpipe_pe9:dffpipe13 " "Elaborating entity \"dffpipe_pe9\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp\|dffpipe_pe9:dffpipe13\"" {  } { { "db/alt_synch_pipe_qld.tdf" "dffpipe13" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf" 34 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452799324 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_rld.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_rld " "Found entity 1: alt_synch_pipe_rld" {  } { { "db/alt_synch_pipe_rld.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452799499 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452799499 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_rld DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp " "Elaborating entity \"alt_synch_pipe_rld\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp\"" {  } { { "db/dcfifo_v5o1.tdf" "ws_dgrp" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 73 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452799518 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_qe9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_qe9 " "Found entity 1: dffpipe_qe9" {  } { { "db/dffpipe_qe9.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_qe9.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452799618 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452799618 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_qe9 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp\|dffpipe_qe9:dffpipe16 " "Elaborating entity \"dffpipe_qe9\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp\|dffpipe_qe9:dffpipe16\"" {  } { { "db/alt_synch_pipe_rld.tdf" "dffpipe16" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf" 34 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452799635 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_e66.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_e66.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_e66 " "Found entity 1: cmpr_e66" {  } { { "db/cmpr_e66.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_e66.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452799802 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452799802 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_e66 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|cmpr_e66:rdempty_eq_comp " "Elaborating entity \"cmpr_e66\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|cmpr_e66:rdempty_eq_comp\"" {  } { { "db/dcfifo_v5o1.tdf" "rdempty_eq_comp" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 80 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452799822 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_CCD_Config DE0_D5M:inst\|I2C_CCD_Config:u8 " "Elaborating entity \"I2C_CCD_Config\" for hierarchy \"DE0_D5M:inst\|I2C_CCD_Config:u8\"" {  } { { "DE0_D5M.v" "u8" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 377 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452802897 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(126) " "Verilog HDL assignment warning at I2C_CCD_Config.v(126): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 126 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802922 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(127) " "Verilog HDL assignment warning at I2C_CCD_Config.v(127): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 127 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802923 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 25 I2C_CCD_Config.v(160) " "Verilog HDL assignment warning at I2C_CCD_Config.v(160): truncated value with size 32 to match size of target (25)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 160 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802924 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(165) " "Verilog HDL assignment warning at I2C_CCD_Config.v(165): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802924 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 I2C_CCD_Config.v(190) " "Verilog HDL assignment warning at I2C_CCD_Config.v(190): truncated value with size 32 to match size of target (16)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 190 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802924 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 I2C_CCD_Config.v(240) " "Verilog HDL assignment warning at I2C_CCD_Config.v(240): truncated value with size 32 to match size of target (6)" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 240 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802924 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_Controller DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0 " "Elaborating entity \"I2C_Controller\" for hierarchy \"DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0\"" {  } { { "V/I2C_CCD_Config.v" "u0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 207 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452802956 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(70) " "Verilog HDL assignment warning at I2C_Controller.v(70): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802973 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(69) " "Verilog HDL assignment warning at I2C_Controller.v(69): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 69 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802974 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 I2C_Controller.v(82) " "Verilog HDL assignment warning at I2C_Controller.v(82): truncated value with size 32 to match size of target (7)" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 82 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452802975 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2 ps2:inst6 " "Elaborating entity \"ps2\" for hierarchy \"ps2:inst6\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst6" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 704 760 968 944 "inst6" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803003 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 ps2.v(120) " "Verilog HDL assignment warning at ps2.v(120): truncated value with size 32 to match size of target (9)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 120 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452803016 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 ps2.v(188) " "Verilog HDL assignment warning at ps2.v(188): truncated value with size 32 to match size of target (8)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 188 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452803016 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2.v(195) " "Verilog HDL assignment warning at ps2.v(195): truncated value with size 32 to match size of target (1)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 195 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452803016 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 ps2.v(201) " "Verilog HDL assignment warning at ps2.v(201): truncated value with size 32 to match size of target (6)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 201 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452803016 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ps2.v(229) " "Verilog HDL assignment warning at ps2.v(229): truncated value with size 32 to match size of target (4)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 229 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452803017 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ps2.v(245) " "Verilog HDL assignment warning at ps2.v(245): truncated value with size 32 to match size of target (4)" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 245 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1457452803017 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_mux vga_mux:inst10 " "Elaborating entity \"vga_mux\" for hierarchy \"vga_mux:inst10\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst10" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1056 2304 2448 1168 "inst10" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803124 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_MUX vga_mux:inst10\|LPM_MUX:LPM_MUX_component " "Elaborating entity \"LPM_MUX\" for hierarchy \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\"" {  } { { "vga_mux.vhd" "LPM_MUX_component" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 193 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803262 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "vga_mux:inst10\|LPM_MUX:LPM_MUX_component " "Elaborated megafunction instantiation \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\"" {  } { { "vga_mux.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 193 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "vga_mux:inst10\|LPM_MUX:LPM_MUX_component " "Instantiated megafunction \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 30 " "Parameter \"LPM_WIDTH\" = \"30\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 4 " "Parameter \"LPM_SIZE\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 2 " "Parameter \"LPM_WIDTHS\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 0 " "Parameter \"LPM_PIPELINE\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_MUX " "Parameter \"LPM_TYPE\" = \"LPM_MUX\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT UNUSED " "Parameter \"LPM_HINT\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803271 ""}  } { { "vga_mux.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 193 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452803271 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_u7e.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_u7e.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_u7e " "Found entity 1: mux_u7e" {  } { { "db/mux_u7e.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/mux_u7e.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452803681 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452803681 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_u7e vga_mux:inst10\|LPM_MUX:LPM_MUX_component\|mux_u7e:auto_generated " "Elaborating entity \"mux_u7e\" for hierarchy \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\|mux_u7e:auto_generated\"" {  } { { "lpm_mux.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803700 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_mouse_square vga_mouse_square:vga_mouse_catapult_inst " "Elaborating entity \"vga_mouse_square\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "vga_mouse_catapult_inst" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 848 1672 1960 1024 "vga_mouse_catapult_inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803767 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:vga_xy_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:vga_xy_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "vga_xy_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 137 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803833 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:mouse_xy_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:mouse_xy_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "mouse_xy_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 142 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803878 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:cursor_size_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:cursor_size_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "cursor_size_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 147 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803907 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:video_in_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:video_in_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "video_in_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 152 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803950 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_out_stdreg vga_mouse_square:vga_mouse_catapult_inst\|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg " "Elaborating entity \"mgc_out_stdreg\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg\"" {  } { { "catapult_ip/mouse/rtl.v" "video_out_rsc_mgc_out_stdreg" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 157 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452803989 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_mouse_square_core vga_mouse_square:vga_mouse_catapult_inst\|vga_mouse_square_core:vga_mouse_square_core_inst " "Elaborating entity \"vga_mouse_square_core\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|vga_mouse_square_core:vga_mouse_square_core_inst\"" {  } { { "catapult_ip/mouse/rtl.v" "vga_mouse_square_core_inst" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 167 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804020 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sobel sobel:inst1 " "Elaborating entity \"sobel\" for hierarchy \"sobel:inst1\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst1" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1080 1704 1944 1192 "inst1" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804062 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire sobel:inst1\|mgc_in_wire:vin_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"sobel:inst1\|mgc_in_wire:vin_rsc_mgc_in_wire\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "vin_rsc_mgc_in_wire" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 896 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804124 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_out_stdreg sobel:inst1\|mgc_out_stdreg:vout_rsc_mgc_out_stdreg " "Elaborating entity \"mgc_out_stdreg\" for hierarchy \"sobel:inst1\|mgc_out_stdreg:vout_rsc_mgc_out_stdreg\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "vout_rsc_mgc_out_stdreg" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 901 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804184 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sobel_core sobel:inst1\|sobel_core:sobel_core_inst " "Elaborating entity \"sobel_core\" for hierarchy \"sobel:inst1\|sobel_core:sobel_core_inst\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "sobel_core_inst" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 908 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804217 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift_taps altshift_taps:fifo_inst2 " "Elaborating entity \"altshift_taps\" for hierarchy \"altshift_taps:fifo_inst2\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "fifo_inst2" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804308 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "altshift_taps:fifo_inst2 " "Elaborated megafunction instantiation \"altshift_taps:fifo_inst2\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452804317 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "altshift_taps:fifo_inst2 " "Instantiated megafunction \"altshift_taps:fifo_inst2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMBER_OF_TAPS 3 " "Parameter \"NUMBER_OF_TAPS\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804317 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "TAP_DISTANCE 800 " "Parameter \"TAP_DISTANCE\" = \"800\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804317 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH 30 " "Parameter \"WIDTH\" = \"30\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804317 ""}  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452804317 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_jpm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/shift_taps_jpm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_jpm " "Found entity 1: shift_taps_jpm" {  } { { "db/shift_taps_jpm.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_jpm.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452804446 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452804446 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_taps_jpm altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated " "Elaborating entity \"shift_taps_jpm\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\"" {  } { { "altshift_taps.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804463 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_5n81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_5n81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_5n81 " "Found entity 1: altsyncram_5n81" {  } { { "db/altsyncram_5n81.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_5n81.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452804634 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452804634 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_5n81 altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|altsyncram_5n81:altsyncram2 " "Elaborating entity \"altsyncram_5n81\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|altsyncram_5n81:altsyncram2\"" {  } { { "db/shift_taps_jpm.tdf" "altsyncram2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_jpm.tdf" 35 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804651 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1tf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1tf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1tf " "Found entity 1: cntr_1tf" {  } { { "db/cntr_1tf.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452804823 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452804823 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1tf altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|cntr_1tf:cntr1 " "Elaborating entity \"cntr_1tf\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|cntr_1tf:cntr1\"" {  } { { "db/shift_taps_jpm.tdf" "cntr1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_jpm.tdf" 36 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452804838 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ugc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ugc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ugc " "Found entity 1: cmpr_ugc" {  } { { "db/cmpr_ugc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_ugc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452805003 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452805003 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ugc altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|cntr_1tf:cntr1\|cmpr_ugc:cmpr4 " "Elaborating entity \"cmpr_ugc\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_jpm:auto_generated\|cntr_1tf:cntr1\|cmpr_ugc:cmpr4\"" {  } { { "db/cntr_1tf.tdf" "cmpr4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf" 85 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452805020 ""}
+{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\] " "Synthesized away node \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\]\"" {  } { { "db/altsyncram_de51.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf" 521 2 0 } } { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 61 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 319 0 0 } } { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 364 0 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452806031 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\] " "Synthesized away node \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\]\"" {  } { { "db/altsyncram_de51.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf" 521 2 0 } } { "db/dcfifo_v5o1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 61 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 308 0 0 } } { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 364 0 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452806031 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Quartus II" 0 -1 1457452806031 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Quartus II" 0 -1 1457452806031 ""}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "21 " "Inferred 21 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult17 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult17\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult17" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 423 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult19 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult19\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult19" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 429 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult0\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult0" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 205 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult18 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult18\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult18" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 424 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult20 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult20\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult20" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 430 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult16 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult16\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult16" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 418 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult2 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult2\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult2" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult4 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult4\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult4" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 244 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult6 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult6\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult6" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 255 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult11 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult11\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult11" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 390 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult1\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult1" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 228 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult7 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult7\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult7" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 373 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult13 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult13\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult13" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 398 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult3 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult3\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult3" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 239 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult8 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult8\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult8" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 377 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult15 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult15\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult15" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 406 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult5 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult5\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult5" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 250 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult9 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult9\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult9" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 381 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult10 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult10\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult10" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 386 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult12 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult12\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult12" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 394 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "sobel:inst1\|sobel_core:sobel_core_inst\|Mult14 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"sobel:inst1\|sobel_core:sobel_core_inst\|Mult14\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "Mult14" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 402 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452807973 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1457452807973 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 423 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 2 " "Parameter \"LPM_WIDTHA\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 11 " "Parameter \"LPM_WIDTHP\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 11 " "Parameter \"LPM_WIDTHR\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808238 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 423 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452808238 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 423 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808454 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 423 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808584 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\|altshift:external_latency_ffs sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult17\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 423 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808703 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 424 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 3 " "Parameter \"LPM_WIDTHA\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 6 " "Parameter \"LPM_WIDTHB\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 9 " "Parameter \"LPM_WIDTHP\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 9 " "Parameter \"LPM_WIDTHR\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808845 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 424 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452808845 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 424 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808869 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 424 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808890 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\|altshift:external_latency_ffs sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult18\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 424 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452808905 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 10 " "Parameter \"LPM_WIDTHA\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 2 " "Parameter \"LPM_WIDTHB\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 12 " "Parameter \"LPM_WIDTHP\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 12 " "Parameter \"LPM_WIDTHR\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809050 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452809050 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 322 5 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809071 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mul_lfrg:mul_lfrg_first_mod sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mul_lfrg:mul_lfrg_first_mod\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 298 9 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809239 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 396 9 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809263 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 115 9 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809465 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_gfh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_gfh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_gfh " "Found entity 1: add_sub_gfh" {  } { { "db/add_sub_gfh.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/add_sub_gfh.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1457452809605 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1457452809605 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mul_lfrg:\$00030 sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mul_lfrg:\$00030\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 958 39 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809652 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mul_lfrg:\$00032 sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|multcore:mult_core\|mul_lfrg:\$00032\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 970 44 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809673 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|altshift:external_latency_ffs sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult2\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 233 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809694 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult11 " "Elaborated megafunction instantiation \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult11\"" {  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 390 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult11 " "Instantiated megafunction \"sobel:inst1\|sobel_core:sobel_core_inst\|lpm_mult:Mult11\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 10 " "Parameter \"LPM_WIDTHA\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 2 " "Parameter \"LPM_WIDTHB\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 12 " "Parameter \"LPM_WIDTHP\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 12 " "Parameter \"LPM_WIDTHR\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1457452809955 ""}  } { { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 390 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1457452809955 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "10 " "10 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1457452812672 ""}
+{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[20\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[20\]\" and its non-tri-state driver." {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "Quartus II" 0 -1 1457452812897 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[14\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[14\]\" and its non-tri-state driver." {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "Quartus II" 0 -1 1457452812897 ""}  } {  } 0 13034 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "Quartus II" 0 -1 1457452812897 ""}
+{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1457452812900 ""}  } {  } 0 13039 "The following bidir pins have no drivers" 0 0 "Quartus II" 0 -1 1457452812900 ""}
+{ "Warning" "WMLS_OPT_REPLACED_VCC_OR_GND_WITH_TRI_HDR" "" "The following tri-state nodes are fed by constants" { { "Warning" "WMLS_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[15\] VCC pin " "The pin \"GPIO_1\[15\]\" is fed by VCC" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13033 "The %3!s! \"%1!s!\" is fed by %2!s!" 0 0 "Quartus II" 0 -1 1457452812912 ""}  } {  } 0 13032 "The following tri-state nodes are fed by constants" 0 0 "Quartus II" 0 -1 1457452812912 ""}
+{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "db/a_graycounter_s57.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf" 32 2 0 } } { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 64 -1 0 } } { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 79 -1 0 } } { "../../../../../Sobel/Sobel Quartus/sobel.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/Sobel Quartus/sobel.v" 45 -1 0 } } { "db/a_graycounter_ojc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf" 32 2 0 } } { "db/a_graycounter_s57.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf" 45 2 0 } } { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 63 -1 0 } } { "db/a_graycounter_ojc.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf" 45 2 0 } } { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 59 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1457452813120 ""}
+{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1457452813134 ""}
+{ "Warning" "WMLS_MLS_ENABLED_OE" "" "TRI or OPNDRN buffers permanently enabled" { { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1~synth " "Node \"GPIO_1~synth\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452814126 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1~synth " "Node \"GPIO_1~synth\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452814126 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1~synth " "Node \"GPIO_1~synth\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452814126 ""}  } {  } 0 13009 "TRI or OPNDRN buffers permanently enabled" 0 0 "Quartus II" 0 -1 1457452814126 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 344 1144 1320 360 "DRAM_CKE" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|DRAM_CKE"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1_CLKOUT\[1\] GND " "Pin \"GPIO_1_CLKOUT\[1\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 504 1144 1354 520 "GPIO_1_CLKOUT\[1..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKOUT[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[9\] GND " "Pin \"LEDG\[9\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[8\] GND " "Pin \"LEDG\[8\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[7\] GND " "Pin \"LEDG\[7\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[6\] GND " "Pin \"LEDG\[6\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[5\] GND " "Pin \"LEDG\[5\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[4\] GND " "Pin \"LEDG\[4\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[3\] GND " "Pin \"LEDG\[3\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1457452814131 "|TOP_DE0_CAMERA_MOUSE|LEDG[3]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1457452814131 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1457452814413 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "32 " "32 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1457452815698 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1457452822603 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452822603 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_1_CLKIN\[1\] " "No output dependent on input pin \"GPIO_1_CLKIN\[1\]\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452824077 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452824077 "|TOP_DE0_CAMERA_MOUSE|SW[9]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452824077 "|TOP_DE0_CAMERA_MOUSE|SW[8]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1457452824077 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "3737 " "Implemented 3737 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "16 " "Implemented 16 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1457452824142 ""} { "Info" "ICUT_CUT_TM_OPINS" "77 " "Implemented 77 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1457452824142 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "50 " "Implemented 50 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1457452824142 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3417 " "Implemented 3417 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1457452824142 ""} { "Info" "ICUT_CUT_TM_RAMS" "176 " "Implemented 176 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1457452824142 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1457452824142 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1457452824142 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 113 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 113 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "579 " "Peak virtual memory: 579 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457452824658 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:00:24 2016 " "Processing ended: Tue Mar 08 16:00:24 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457452824658 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:40 " "Elapsed time: 00:00:40" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457452824658 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457452824658 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457452824658 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1457452833557 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457452833613 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:00:31 2016 " "Processing started: Tue Mar 08 16:00:31 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457452833613 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1457452833613 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M " "Command: quartus_fit --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1457452833632 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1457452833748 ""}
+{ "Info" "0" "" "Project  = DE0_D5M" {  } {  } 0 0 "Project  = DE0_D5M" 0 0 "Fitter" 0 0 1457452833749 ""}
+{ "Info" "0" "" "Revision = DE0_D5M" {  } {  } 0 0 "Revision = DE0_D5M" 0 0 "Fitter" 0 0 1457452833749 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1457452835242 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "DE0_D5M EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"DE0_D5M\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1457452835729 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457452835823 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1457452835823 ""}
+{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1 Cyclone III PLL " "Implemented PLL \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1\" as Cyclone III PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] 5 2 0 0 " "Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] port" {  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2979 9224 9983 0}  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1457452835882 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] 5 2 -117 -2600 " "Implementing clock multiplication of 5, clock division of 2, and phase shift of -117 degrees (-2600 ps) for DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] port" {  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2980 9224 9983 0}  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1457452835882 ""}  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2979 9224 9983 0}  }  } }  } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1457452835882 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1457452836002 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457452836276 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457452836276 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1457452836276 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1457452836276 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12522 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457452836290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12524 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457452836290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12526 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457452836290 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12528 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1457452836290 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1457452836290 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1457452836300 ""}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1457452836314 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 143 " "No exact pin location assignment(s) for 1 pins of 143 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "VGA_CLK " "Pin VGA_CLK not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { VGA_CLK } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1272 736 912 1288 "VGA_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 310 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1457452837164 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1457452837164 ""}
+{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_v5o1 " "Entity dcfifo_v5o1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a*  " "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840334 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a*  " "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840334 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1457452840334 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1457452840334 ""}
+{ "Info" "ISTA_SDC_FOUND" "DE0_D5M.sdc " "Reading SDC File: 'DE0_D5M.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1457452840358 ""}
+{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840368 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840368 ""}  } {  } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1457452840368 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457452840381 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457452840381 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457452840381 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457452840381 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1457452840382 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
+{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452840456 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452840456 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452840456 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1457452840456 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1457452840475 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840491 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840491 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840491 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840491 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\] " "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1457452840491 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1457452840491 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p)) " "Automatically promoted node CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G7 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840734 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|rClk\[0\] " "Destination node DE0_D5M:inst\|rClk\[0\]" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|rClk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 3322 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840734 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|clk_div\[8\] " "Destination node ps2:inst6\|clk_div\[8\]" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 97 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|clk_div[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2278 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840734 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Destination node DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 69 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2450 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840734 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840734 ""}  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 88 424 592 104 "CLOCK_50" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12506 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840734 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] (placed in counter C0 of PLL_2) " "Automatically promoted node DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] (placed in counter C0 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G8 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840744 ""}  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 31 2 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2979 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840744 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] (placed in counter C1 of PLL_2) " "Automatically promoted node DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] (placed in counter C1 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840744 ""}  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 31 2 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2979 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840744 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "GPIO_1_CLKIN\[0\]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n)) " "Automatically promoted node GPIO_1_CLKIN\[0\]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840745 ""}  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKIN[0]~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12515 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840745 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|rClk\[0\]  " "Automatically promoted node DE0_D5M:inst\|rClk\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840746 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|rClk\[0\]~0 " "Destination node DE0_D5M:inst\|rClk\[0\]~0" {  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|rClk[0]~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 8151 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840746 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1_CLKOUT\[0\]~output " "Destination node GPIO_1_CLKOUT\[0\]~output" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 504 1144 1354 520 "GPIO_1_CLKOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKOUT[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12403 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840746 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "VGA_CLK~output " "Destination node VGA_CLK~output" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1272 736 912 1288 "VGA_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_CLK~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 12387 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840746 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840746 ""}  } { { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|rClk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 3322 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840746 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK  " "Automatically promoted node DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840747 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0\|I2C_SCLK~1 " "Destination node DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0\|I2C_SCLK~1" {  } { { "V/I2C_Controller.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 58 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|I2C_SCLK~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 6031 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840747 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK~0 " "Destination node DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK~0" {  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 69 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7084 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840747 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840747 ""}  } { { "V/I2C_CCD_Config.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 69 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2450 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840747 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2:inst6\|ps2_clk_in  " "Automatically promoted node ps2:inst6\|ps2_clk_in " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840751 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|Equal2~0 " "Destination node ps2:inst6\|Equal2~0" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 186 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|Equal2~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5034 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840751 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840751 ""}  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 101 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|ps2_clk_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2301 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840751 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2:inst6\|clk_div\[8\]  " "Automatically promoted node ps2:inst6\|clk_div\[8\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840751 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|clk_div\[8\]~22 " "Destination node ps2:inst6\|clk_div\[8\]~22" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 97 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|clk_div[8]~22 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5028 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840751 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|ps2_clk_in " "Destination node ps2:inst6\|ps2_clk_in" {  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 101 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|ps2_clk_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2301 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840751 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840751 ""}  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 97 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|clk_div[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2278 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840751 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_0  " "Automatically promoted node DE0_D5M:inst\|Reset_Delay:u2\|oRST_0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|mRD~5 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|mRD~5" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 166 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|mRD~5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5390 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[22\]~43 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[22\]~43" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]~43 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7590 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[22\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[22\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7595 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[15\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[15\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7628 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[15\]~47 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[15\]~47" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]~47 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7629 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[17\]~45 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[17\]~45" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~45 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7662 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[17\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[17\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7663 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[19\]~43 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[19\]~43" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19]~43 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7692 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[19\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[19\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7697 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_0~2 " "Destination node DE0_D5M:inst\|Reset_Delay:u2\|oRST_0~2" {  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 46 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_0~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 8072 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840753 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840753 ""}  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 46 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 3246 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840753 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_1  " "Automatically promoted node DE0_D5M:inst\|Reset_Delay:u2\|oRST_1 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840763 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[14\]~output " "Destination node GPIO_1\[14\]~output" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 8196 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840763 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_1~1 " "Destination node DE0_D5M:inst\|Reset_Delay:u2\|oRST_1~1" {  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 47 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_1~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 7119 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1457452840763 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1457452840763 ""}  } { { "V/Reset_Delay.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 47 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 3247 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840763 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2:inst6\|Equal3~2  " "Automatically promoted node ps2:inst6\|Equal3~2 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1457452840763 ""}  } { { "V/ps2.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 195 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|Equal3~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5050 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1457452840763 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1457452844088 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1457452844100 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1457452844106 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1457452844120 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1457452844137 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1457452844148 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1457452844152 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1457452844164 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1457452847854 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1457452847871 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1457452847871 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1457452847913 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1457452847913 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1457452847913 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 27 6 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 16 30 " "I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 16 total pin(s) used --  30 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 20 21 " "I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used --  21 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.3V 2 44 " "I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used --  44 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 15 28 " "I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.3V 28 19 " "I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 28 total pin(s) used --  19 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.3V 38 5 " "I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1457452847924 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1457452847924 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1457452847924 ""}
+{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1 clk\[1\] DRAM_CLK~output " "PLL \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"DRAM_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "db/altpll_9ee2.tdf" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "altpll.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "V/sdram_pll.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } } { "DE0_D5M.v" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 308 0 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 328 1144 1320 344 "DRAM_CLK" "" } } } }  } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1457452848005 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCDAT " "Ignored I/O standard assignment to node \"AUD_ADCDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCLRCK " "Ignored I/O standard assignment to node \"AUD_ADCLRCK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_BCLK " "Ignored I/O standard assignment to node \"AUD_BCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACDAT " "Ignored I/O standard assignment to node \"AUD_DACDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACLRCK " "Ignored I/O standard assignment to node \"AUD_DACLRCK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_XCK " "Ignored I/O standard assignment to node \"AUD_XCK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "BUTTON\[0\] " "Ignored I/O standard assignment to node \"BUTTON\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "BUTTON\[1\] " "Ignored I/O standard assignment to node \"BUTTON\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "BUTTON\[2\] " "Ignored I/O standard assignment to node \"BUTTON\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_50_2 " "Ignored I/O standard assignment to node \"CLOCK_50_2\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50_2" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[0\] " "Ignored I/O standard assignment to node \"FL_ADDR\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[10\] " "Ignored I/O standard assignment to node \"FL_ADDR\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[11\] " "Ignored I/O standard assignment to node \"FL_ADDR\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[12\] " "Ignored I/O standard assignment to node \"FL_ADDR\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[13\] " "Ignored I/O standard assignment to node \"FL_ADDR\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[14\] " "Ignored I/O standard assignment to node \"FL_ADDR\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[15\] " "Ignored I/O standard assignment to node \"FL_ADDR\[15\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[16\] " "Ignored I/O standard assignment to node \"FL_ADDR\[16\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[17\] " "Ignored I/O standard assignment to node \"FL_ADDR\[17\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[18\] " "Ignored I/O standard assignment to node \"FL_ADDR\[18\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[19\] " "Ignored I/O standard assignment to node \"FL_ADDR\[19\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[1\] " "Ignored I/O standard assignment to node \"FL_ADDR\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[20\] " "Ignored I/O standard assignment to node \"FL_ADDR\[20\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[21\] " "Ignored I/O standard assignment to node \"FL_ADDR\[21\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[2\] " "Ignored I/O standard assignment to node \"FL_ADDR\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[3\] " "Ignored I/O standard assignment to node \"FL_ADDR\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[4\] " "Ignored I/O standard assignment to node \"FL_ADDR\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[5\] " "Ignored I/O standard assignment to node \"FL_ADDR\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[6\] " "Ignored I/O standard assignment to node \"FL_ADDR\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[7\] " "Ignored I/O standard assignment to node \"FL_ADDR\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[8\] " "Ignored I/O standard assignment to node \"FL_ADDR\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[9\] " "Ignored I/O standard assignment to node \"FL_ADDR\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_BYTE_N " "Ignored I/O standard assignment to node \"FL_BYTE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_BYTE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_CE_N " "Ignored I/O standard assignment to node \"FL_CE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ15_AM1 " "Ignored I/O standard assignment to node \"FL_DQ15_AM1\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ15_AM1" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[0\] " "Ignored I/O standard assignment to node \"FL_DQ\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[10\] " "Ignored I/O standard assignment to node \"FL_DQ\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[11\] " "Ignored I/O standard assignment to node \"FL_DQ\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[12\] " "Ignored I/O standard assignment to node \"FL_DQ\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[13\] " "Ignored I/O standard assignment to node \"FL_DQ\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[14\] " "Ignored I/O standard assignment to node \"FL_DQ\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[1\] " "Ignored I/O standard assignment to node \"FL_DQ\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[2\] " "Ignored I/O standard assignment to node \"FL_DQ\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[3\] " "Ignored I/O standard assignment to node \"FL_DQ\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[4\] " "Ignored I/O standard assignment to node \"FL_DQ\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[5\] " "Ignored I/O standard assignment to node \"FL_DQ\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[6\] " "Ignored I/O standard assignment to node \"FL_DQ\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[7\] " "Ignored I/O standard assignment to node \"FL_DQ\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[8\] " "Ignored I/O standard assignment to node \"FL_DQ\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[9\] " "Ignored I/O standard assignment to node \"FL_DQ\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_OE_N " "Ignored I/O standard assignment to node \"FL_OE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RST_N " "Ignored I/O standard assignment to node \"FL_RST_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RY " "Ignored I/O standard assignment to node \"FL_RY\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WE_N " "Ignored I/O standard assignment to node \"FL_WE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WP_N " "Ignored I/O standard assignment to node \"FL_WP_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKIN\[0\] " "Ignored I/O standard assignment to node \"GPIO0_CLKIN\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKIN\[1\] " "Ignored I/O standard assignment to node \"GPIO0_CLKIN\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKOUT\[0\] " "Ignored I/O standard assignment to node \"GPIO0_CLKOUT\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKOUT\[1\] " "Ignored I/O standard assignment to node \"GPIO0_CLKOUT\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKIN\[0\] " "Ignored I/O standard assignment to node \"GPIO1_CLKIN\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKIN\[1\] " "Ignored I/O standard assignment to node \"GPIO1_CLKIN\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKOUT\[0\] " "Ignored I/O standard assignment to node \"GPIO1_CLKOUT\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKOUT\[1\] " "Ignored I/O standard assignment to node \"GPIO1_CLKOUT\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[32\] " "Ignored I/O standard assignment to node \"GPIO_1\[32\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[33\] " "Ignored I/O standard assignment to node \"GPIO_1\[33\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[34\] " "Ignored I/O standard assignment to node \"GPIO_1\[34\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[35\] " "Ignored I/O standard assignment to node \"GPIO_1\[35\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_DP " "Ignored I/O standard assignment to node \"HEX0_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[0\] " "Ignored I/O standard assignment to node \"HEX0_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[1\] " "Ignored I/O standard assignment to node \"HEX0_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[2\] " "Ignored I/O standard assignment to node \"HEX0_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[3\] " "Ignored I/O standard assignment to node \"HEX0_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[4\] " "Ignored I/O standard assignment to node \"HEX0_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[5\] " "Ignored I/O standard assignment to node \"HEX0_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[6\] " "Ignored I/O standard assignment to node \"HEX0_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_DP " "Ignored I/O standard assignment to node \"HEX1_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[0\] " "Ignored I/O standard assignment to node \"HEX1_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[1\] " "Ignored I/O standard assignment to node \"HEX1_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[2\] " "Ignored I/O standard assignment to node \"HEX1_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[3\] " "Ignored I/O standard assignment to node \"HEX1_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[4\] " "Ignored I/O standard assignment to node \"HEX1_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[5\] " "Ignored I/O standard assignment to node \"HEX1_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[6\] " "Ignored I/O standard assignment to node \"HEX1_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_DP " "Ignored I/O standard assignment to node \"HEX2_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[0\] " "Ignored I/O standard assignment to node \"HEX2_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[1\] " "Ignored I/O standard assignment to node \"HEX2_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[2\] " "Ignored I/O standard assignment to node \"HEX2_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[3\] " "Ignored I/O standard assignment to node \"HEX2_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[4\] " "Ignored I/O standard assignment to node \"HEX2_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[5\] " "Ignored I/O standard assignment to node \"HEX2_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[6\] " "Ignored I/O standard assignment to node \"HEX2_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_DP " "Ignored I/O standard assignment to node \"HEX3_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[0\] " "Ignored I/O standard assignment to node \"HEX3_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[1\] " "Ignored I/O standard assignment to node \"HEX3_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[2\] " "Ignored I/O standard assignment to node \"HEX3_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[3\] " "Ignored I/O standard assignment to node \"HEX3_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[4\] " "Ignored I/O standard assignment to node \"HEX3_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[5\] " "Ignored I/O standard assignment to node \"HEX3_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[6\] " "Ignored I/O standard assignment to node \"HEX3_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SCLK " "Ignored I/O standard assignment to node \"I2C_SCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SDAT " "Ignored I/O standard assignment to node \"I2C_SDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "KEY\[3\] " "Ignored I/O standard assignment to node \"KEY\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_BLON " "Ignored I/O standard assignment to node \"LCD_BLON\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[0\] " "Ignored I/O standard assignment to node \"LCD_DATA\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[1\] " "Ignored I/O standard assignment to node \"LCD_DATA\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[2\] " "Ignored I/O standard assignment to node \"LCD_DATA\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[3\] " "Ignored I/O standard assignment to node \"LCD_DATA\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[4\] " "Ignored I/O standard assignment to node \"LCD_DATA\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[5\] " "Ignored I/O standard assignment to node \"LCD_DATA\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[6\] " "Ignored I/O standard assignment to node \"LCD_DATA\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[7\] " "Ignored I/O standard assignment to node \"LCD_DATA\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_EN " "Ignored I/O standard assignment to node \"LCD_EN\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_RS " "Ignored I/O standard assignment to node \"LCD_RS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_RW " "Ignored I/O standard assignment to node \"LCD_RW\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_KBCLK " "Ignored I/O standard assignment to node \"PS2_KBCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_KBDAT " "Ignored I/O standard assignment to node \"PS2_KBDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CLK " "Ignored I/O standard assignment to node \"SD_CLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CMD " "Ignored I/O standard assignment to node \"SD_CMD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT0 " "Ignored I/O standard assignment to node \"SD_DAT0\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT0" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT3 " "Ignored I/O standard assignment to node \"SD_DAT3\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_WP_N " "Ignored I/O standard assignment to node \"SD_WP_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_CTS " "Ignored I/O standard assignment to node \"UART_CTS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RTS " "Ignored I/O standard assignment to node \"UART_RTS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RXD " "Ignored I/O standard assignment to node \"UART_RXD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_TXD " "Ignored I/O standard assignment to node \"UART_TXD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1457452848109 ""}  } {  } 0 15709 "Ignored I/O standard assignments to the following nodes" 0 0 "Fitter" 0 -1 1457452848109 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50_2 " "Node \"CLOCK_50_2\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50_2" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457452848129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457452848129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_DP " "Node \"HEX0_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457452848129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_DP " "Node \"HEX1_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457452848129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_DP " "Node \"HEX2_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457452848129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_DP " "Node \"HEX3_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1457452848129 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1457452848129 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457452848135 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1457452852244 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457452853030 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1457452853068 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1457452855776 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457452855788 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1457452860237 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 " "Router estimated average interconnect usage is 5% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X10_Y10 X20_Y19 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X10_Y10 to location X20_Y19" {  } { { "loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X10_Y10 to location X20_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X10_Y10 to location X20_Y19"} 10 10 11 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1457452863163 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1457452863163 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Fitter routing operations ending: elapsed time is 00:00:05" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457452865158 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1457452865194 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1457452865194 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "2.70 " "Total time spent on timing analysis during the Fitter is 2.70 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1457452865332 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1457452865487 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1457452867721 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1457452867864 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1457452869538 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:08 " "Fitter post-fit operations ending: elapsed time is 00:00:08" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1457452873441 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1457452874187 ""}
+{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "66 Cyclone III " "66 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1_CLKIN\[1\] 3.3-V LVTTL AA11 " "Pin GPIO_1_CLKIN\[1\] uses I/O standard 3.3-V LVTTL at AA11" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1_CLKIN[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_CLKIN\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKIN[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 220 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[9\] 3.3-V LVTTL D2 " "Pin SW\[9\] uses I/O standard 3.3-V LVTTL at D2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 225 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[8\] 3.3-V LVTTL E4 " "Pin SW\[8\] uses I/O standard 3.3-V LVTTL at E4" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 226 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[15\] 3.3-V LVTTL F10 " "Pin DRAM_DQ\[15\] uses I/O standard 3.3-V LVTTL at F10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 172 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[14\] 3.3-V LVTTL E10 " "Pin DRAM_DQ\[14\] uses I/O standard 3.3-V LVTTL at E10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 173 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[13\] 3.3-V LVTTL A10 " "Pin DRAM_DQ\[13\] uses I/O standard 3.3-V LVTTL at A10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 174 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[12\] 3.3-V LVTTL B10 " "Pin DRAM_DQ\[12\] uses I/O standard 3.3-V LVTTL at B10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 175 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[11\] 3.3-V LVTTL C10 " "Pin DRAM_DQ\[11\] uses I/O standard 3.3-V LVTTL at C10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 176 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[10\] 3.3-V LVTTL A9 " "Pin DRAM_DQ\[10\] uses I/O standard 3.3-V LVTTL at A9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 177 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[9\] 3.3-V LVTTL B9 " "Pin DRAM_DQ\[9\] uses I/O standard 3.3-V LVTTL at B9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 178 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[8\] 3.3-V LVTTL A8 " "Pin DRAM_DQ\[8\] uses I/O standard 3.3-V LVTTL at A8" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 179 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[7\] 3.3-V LVTTL F8 " "Pin DRAM_DQ\[7\] uses I/O standard 3.3-V LVTTL at F8" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 180 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[6\] 3.3-V LVTTL H9 " "Pin DRAM_DQ\[6\] uses I/O standard 3.3-V LVTTL at H9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 181 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[5\] 3.3-V LVTTL G9 " "Pin DRAM_DQ\[5\] uses I/O standard 3.3-V LVTTL at G9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 182 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[4\] 3.3-V LVTTL F9 " "Pin DRAM_DQ\[4\] uses I/O standard 3.3-V LVTTL at F9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 183 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[3\] 3.3-V LVTTL E9 " "Pin DRAM_DQ\[3\] uses I/O standard 3.3-V LVTTL at E9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 184 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[2\] 3.3-V LVTTL H10 " "Pin DRAM_DQ\[2\] uses I/O standard 3.3-V LVTTL at H10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 185 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[1\] 3.3-V LVTTL G10 " "Pin DRAM_DQ\[1\] uses I/O standard 3.3-V LVTTL at G10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 186 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[0\] 3.3-V LVTTL D10 " "Pin DRAM_DQ\[0\] uses I/O standard 3.3-V LVTTL at D10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 187 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[31\] 3.3-V LVTTL V7 " "Pin GPIO_1\[31\] uses I/O standard 3.3-V LVTTL at V7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 188 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL V6 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at V6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 189 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL U8 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at U8" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 190 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL Y7 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at Y7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 191 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL T9 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at T9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 192 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[26\] 3.3-V LVTTL U9 " "Pin GPIO_1\[26\] uses I/O standard 3.3-V LVTTL at U9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 193 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[25\] 3.3-V LVTTL T10 " "Pin GPIO_1\[25\] uses I/O standard 3.3-V LVTTL at T10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 194 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[24\] 3.3-V LVTTL U10 " "Pin GPIO_1\[24\] uses I/O standard 3.3-V LVTTL at U10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 195 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL R12 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at R12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 196 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R11 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R11" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 197 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL T12 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at T12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 198 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL U12 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at U12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 199 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL R14 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at R14" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 200 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL T14 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at T14" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 201 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL AB7 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at AB7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 202 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL AA7 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at AA7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 203 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL AA9 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at AA9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 204 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL AB9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at AB9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 205 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL V15 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at V15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 206 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL W15 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at W15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 207 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL T15 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at T15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 208 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL U15 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at U15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 209 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL W17 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at W17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 210 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL Y17 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at Y17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 211 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL AB17 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at AB17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 212 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL AA17 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at AA17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 213 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL AA18 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at AA18" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 214 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL AB18 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at AB18" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 215 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL AB19 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at AB19" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 216 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL AA19 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at AA19" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 217 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL AB20 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at AB20" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 218 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL AA20 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at AA20" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 219 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL P21 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at P21" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_DAT } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 576 376 552 592 "PS2_DAT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 313 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL P22 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at P22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_CLK } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 600 376 552 616 "PS2_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 314 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[4\] 3.3-V LVTTL G5 " "Pin SW\[4\] uses I/O standard 3.3-V LVTTL at G5" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 230 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[5\] 3.3-V LVTTL J7 " "Pin SW\[5\] uses I/O standard 3.3-V LVTTL at J7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 229 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL G21 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 88 424 592 104 "CLOCK_50" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 300 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL H2 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at H2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { KEY[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 104 424 592 120 "KEY" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 224 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[7\] 3.3-V LVTTL E3 " "Pin SW\[7\] uses I/O standard 3.3-V LVTTL at E3" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 227 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[6\] 3.3-V LVTTL H7 " "Pin SW\[6\] uses I/O standard 3.3-V LVTTL at H7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 228 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL G4 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at G4" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 231 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL H6 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at H6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 232 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL H5 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at H5" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 233 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL J6 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at J6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 234 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL G3 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at G3" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { KEY[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 104 424 592 120 "KEY" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 223 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1_CLKIN\[0\] 3.3-V LVTTL AB11 " "Pin GPIO_1_CLKIN\[0\] uses I/O standard 3.3-V LVTTL at AB11" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1_CLKIN[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_CLKIN\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKIN[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 221 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[2\] 3.3-V LVTTL F1 " "Pin KEY\[2\] uses I/O standard 3.3-V LVTTL at F1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { KEY[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 104 424 592 120 "KEY" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { KEY[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 222 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1457452874250 ""}  } {  } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1457452874250 ""}
+{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "31 " "Following 31 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Pin GPIO_1\[31\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 188 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Pin GPIO_1\[30\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 189 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Pin GPIO_1\[29\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 190 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Pin GPIO_1\[28\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 191 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Pin GPIO_1\[27\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 192 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Pin GPIO_1\[26\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 193 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Pin GPIO_1\[25\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 194 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Pin GPIO_1\[24\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 195 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Pin GPIO_1\[23\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 196 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Pin GPIO_1\[22\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 197 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Pin GPIO_1\[21\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 198 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently enabled " "Pin GPIO_1\[20\] has a permanently enabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 199 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Pin GPIO_1\[18\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 201 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Pin GPIO_1\[17\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 202 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Pin GPIO_1\[16\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 203 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently enabled " "Pin GPIO_1\[15\] has a permanently enabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 204 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently enabled " "Pin GPIO_1\[14\] has a permanently enabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 205 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Pin GPIO_1\[13\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 206 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Pin GPIO_1\[12\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 207 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Pin GPIO_1\[11\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 208 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Pin GPIO_1\[10\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 209 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Pin GPIO_1\[9\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 210 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Pin GPIO_1\[8\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 211 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Pin GPIO_1\[7\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 212 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Pin GPIO_1\[6\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 213 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Pin GPIO_1\[5\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 214 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Pin GPIO_1\[4\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 215 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Pin GPIO_1\[3\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 216 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Pin GPIO_1\[2\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 217 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Pin GPIO_1\[1\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 218 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Pin GPIO_1\[0\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 219 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1457452874281 ""}  } {  } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1457452874281 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg " "Generated suppressed messages file //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1457452874858 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 149 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 149 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1254 " "Peak virtual memory: 1254 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457452878848 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:01:18 2016 " "Processing ended: Tue Mar 08 16:01:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457452878848 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:47 " "Elapsed time: 00:00:47" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457452878848 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:29 " "Total CPU time (on all processors): 00:00:29" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457452878848 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1457452878848 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1457452888644 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457452888653 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:01:28 2016 " "Processing started: Tue Mar 08 16:01:28 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457452888653 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1457452888653 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M " "Command: quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1457452888653 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1457452891195 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1457452891257 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "443 " "Peak virtual memory: 443 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457452893678 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:01:33 2016 " "Processing ended: Tue Mar 08 16:01:33 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457452893678 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457452893678 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457452893678 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1457452893678 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1457452894726 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1457452896576 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1457452896601 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 08 16:01:34 2016 " "Processing started: Tue Mar 08 16:01:34 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1457452896601 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1457452896601 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DE0_D5M -c DE0_D5M " "Command: quartus_sta DE0_D5M -c DE0_D5M" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1457452896608 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1457452896694 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1457452898141 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457452898237 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1457452898237 ""}
+{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_v5o1 " "Entity dcfifo_v5o1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a*  " "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1457452900596 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a*  " "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1457452900596 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1457452900596 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Quartus II" 0 -1 1457452900596 ""}
+{ "Info" "ISTA_SDC_FOUND" "DE0_D5M.sdc " "Reading SDC File: 'DE0_D5M.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1457452900620 ""}
+{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457452900633 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457452900633 ""}  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1457452900633 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452900674 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452900675 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452900675 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452900675 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452900675 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
+{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452900813 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452900813 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452900813 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1457452900813 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1457452900846 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1457452900928 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457452900988 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457452900988 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.785 " "Worst-case setup slack is -0.785" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.785       -35.115 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -0.785       -35.115 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.205         0.000 CLOCK_50  " "   15.205         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901016 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452901016 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.266 " "Worst-case hold slack is 0.266" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.266         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.266         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.358         0.000 CLOCK_50  " "    0.358         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901039 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452901039 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -1.394 " "Worst-case recovery slack is -1.394" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.394      -307.981 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -1.394      -307.981 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   14.003         0.000 CLOCK_50  " "   14.003         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901070 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452901070 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.646 " "Worst-case removal slack is 1.646" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.646         0.000 CLOCK_50  " "    1.646         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.046         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    4.046         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901098 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452901098 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.734 " "Worst-case minimum pulse width slack is 3.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901122 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901122 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.734         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.734         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901122 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.580         0.000 CLOCK_50  " "    9.580         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901122 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452901122 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 40 synchronizer chains. " "Report Metastability: Found 40 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 40 " "Number of Synchronizer Chains Found: 40" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 11.151 ns " "Worst Case Available Settling Time: 11.151 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""}  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452901714 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1457452901756 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1457452901810 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1457452903384 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452903808 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452903808 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452903808 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452903808 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452903808 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
+{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452903815 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452903815 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452903815 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1457452903815 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1457452903849 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1457452903849 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.224 " "Worst-case setup slack is -0.224" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903872 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903872 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.224        -1.977 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -0.224        -1.977 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903872 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.655         0.000 CLOCK_50  " "   15.655         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903872 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452903872 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.261 " "Worst-case hold slack is 0.261" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903900 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903900 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.261         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.261         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903900 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.312         0.000 CLOCK_50  " "    0.312         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903900 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452903900 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.757 " "Worst-case recovery slack is -0.757" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.757      -122.138 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -0.757      -122.138 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903927 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   14.662         0.000 CLOCK_50  " "   14.662         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903927 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452903927 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.505 " "Worst-case removal slack is 1.505" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.505         0.000 CLOCK_50  " "    1.505         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.557         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.557         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903960 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452903960 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.739 " "Worst-case minimum pulse width slack is 3.739" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.739         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.739         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.562         0.000 CLOCK_50  " "    9.562         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452903988 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452903988 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 40 synchronizer chains. " "Report Metastability: Found 40 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 40 " "Number of Synchronizer Chains Found: 40" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 11.652 ns " "Worst Case Available Settling Time: 11.652 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""}  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452904415 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1457452904510 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452905905 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452905905 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452905905 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452905905 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1457452905905 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
+{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452905912 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452905912 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1457452905912 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1457452905912 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.245 " "Worst-case setup slack is 1.245" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.245         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    1.245         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.284         0.000 CLOCK_50  " "   17.284         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905944 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452905944 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.117 " "Worst-case hold slack is 0.117" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.117         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.117         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.187         0.000 CLOCK_50  " "    0.187         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452905976 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452905976 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 0.848 " "Worst-case recovery slack is 0.848" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.848         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.848         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.451         0.000 CLOCK_50  " "   16.451         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906009 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452906009 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.927 " "Worst-case removal slack is 0.927" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906042 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906042 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.927         0.000 CLOCK_50  " "    0.927         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906042 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.361         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    2.361         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906042 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452906042 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.746 " "Worst-case minimum pulse width slack is 3.746" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.746         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.746         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.266         0.000 CLOCK_50  " "    9.266         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906073 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1457452906073 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 40 synchronizer chains. " "Report Metastability: Found 40 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 40 " "Number of Synchronizer Chains Found: 40" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 13.268 ns " "Worst Case Available Settling Time: 13.268 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""}  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1457452906681 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1457452907507 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1457452907513 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 29 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 29 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "539 " "Peak virtual memory: 539 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1457452909301 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 08 16:01:49 2016 " "Processing ended: Tue Mar 08 16:01:49 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1457452909301 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1457452909301 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1457452909301 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457452909301 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 291 s " "Quartus II Full Compilation was successful. 0 errors, 291 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1457452931357 ""}
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_jpm.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_jpm.tdf
new file mode 100644
index 0000000..09286d5
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_jpm.tdf
@@ -0,0 +1,50 @@
+--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" NUMBER_OF_TAPS=3 TAP_DISTANCE=800 WIDTH=30 clken clock shiftin taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
+--VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altshift_taps 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION altsyncram_5n81 (address_a[9..0], address_b[9..0], clock0, clocken0, data_a[89..0], wren_a)
+RETURNS ( q_b[89..0]);
+FUNCTION cntr_1tf (clk_en, clock)
+RETURNS ( q[9..0]);
+
+--synthesis_resources = lut 10 M9K 10 reg 10 
+SUBDESIGN shift_taps_jpm
+( 
+	clken	:	input;
+	clock	:	input;
+	shiftin[29..0]	:	input;
+	shiftout[29..0]	:	output;
+	taps[89..0]	:	output;
+) 
+VARIABLE 
+	altsyncram2 : altsyncram_5n81;
+	cntr1 : cntr_1tf;
+
+BEGIN 
+	altsyncram2.address_a[] = cntr1.q[];
+	altsyncram2.address_b[] = cntr1.q[];
+	altsyncram2.clock0 = clock;
+	altsyncram2.clocken0 = clken;
+	altsyncram2.data_a[] = ( altsyncram2.q_b[59..0], shiftin[]);
+	altsyncram2.wren_a = B"1";
+	cntr1.clk_en = clken;
+	cntr1.clock = clock;
+	shiftout[29..0] = altsyncram2.q_b[89..60];
+	taps[] = altsyncram2.q_b[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf
new file mode 100644
index 0000000..6dece17
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf
@@ -0,0 +1,50 @@
+--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" NUMBER_OF_TAPS=2 TAP_DISTANCE=1280 WIDTH=12 clken clock shiftin shiftout taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
+--VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altshift_taps 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION altsyncram_lp81 (address_a[10..0], address_b[10..0], clock0, clocken0, data_a[23..0], wren_a)
+RETURNS ( q_b[23..0]);
+FUNCTION cntr_cuf (clk_en, clock)
+RETURNS ( q[10..0]);
+
+--synthesis_resources = lut 11 M9K 6 reg 11 
+SUBDESIGN shift_taps_rnn
+( 
+	clken	:	input;
+	clock	:	input;
+	shiftin[11..0]	:	input;
+	shiftout[11..0]	:	output;
+	taps[23..0]	:	output;
+) 
+VARIABLE 
+	altsyncram2 : altsyncram_lp81;
+	cntr1 : cntr_cuf;
+
+BEGIN 
+	altsyncram2.address_a[] = cntr1.q[];
+	altsyncram2.address_b[] = cntr1.q[];
+	altsyncram2.clock0 = clock;
+	altsyncram2.clocken0 = clken;
+	altsyncram2.data_a[] = ( altsyncram2.q_b[11..0], shiftin[]);
+	altsyncram2.wren_a = B"1";
+	cntr1.clk_en = clken;
+	cntr1.clock = clock;
+	shiftout[11..0] = altsyncram2.q_b[23..12];
+	taps[] = altsyncram2.q_b[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/cbx_args.txt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..a13a74e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/cbx_args.txt
@@ -0,0 +1,11 @@
+LPM_SIZE=4
+LPM_TYPE=LPM_MUX
+LPM_WIDTH=30
+LPM_WIDTHS=2
+DEVICE_FAMILY="Cyclone III"
+data
+data
+data
+data
+sel
+result
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/README b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.db_info b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.db_info
new file mode 100644
index 0000000..3db6a75
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Mar 08 14:02:00 2016
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.ammdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.ammdb
new file mode 100644
index 0000000..6608cbf
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.ammdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.cdb
new file mode 100644
index 0000000..2c300d5
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.dfp b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.dfp
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.hdb
new file mode 100644
index 0000000..ee5ce18
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.kpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.kpt
new file mode 100644
index 0000000..b1479c0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.kpt
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.logdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.rcfdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..64bf268
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.rcfdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.cdb
new file mode 100644
index 0000000..6e429f7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.dpi b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.dpi
new file mode 100644
index 0000000..4ec9b07
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.dpi
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..9bdea89
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.hb_info b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..f5c15cc
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.hb_info
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..2dd36ae
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.sig b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..682f0a1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7b81eaf314cd59741fced60c2f8bb713
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hdb
new file mode 100644
index 0000000..aa9a64d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.kpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.kpt
new file mode 100644
index 0000000..12d7829
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.kpt
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga.bsf
new file mode 100644
index 0000000..ad72508
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 256 128)
+	(text "mean_vga" (rect 5 0 48 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "vin_rsc_z[89..0]" (rect 0 0 64 12)(font "Arial" ))
+		(text "vin_rsc_z[89..0]" (rect 21 27 85 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 43 31 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 59 30 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 75 46 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 240 32)
+		(output)
+		(text "vout_rsc_z[29..0]" (rect 0 0 70 12)(font "Arial" ))
+		(text "vout_rsc_z[29..0]" (rect 149 27 219 39)(font "Arial" ))
+		(line (pt 240 32)(pt 224 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 224 96)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga_core.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga_core.bsf
new file mode 100644
index 0000000..782bad9
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga_core.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 384 128)
+	(text "mean_vga_core" (rect 5 0 72 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 43 30 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 59 46 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "vin_rsc_mgc_in_wire_d[89..0]" (rect 0 0 122 12)(font "Arial" ))
+		(text "vin_rsc_mgc_in_wire_d[89..0]" (rect 21 75 143 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 368 32)
+		(output)
+		(text "vout_rsc_mgc_out_stdreg_d[29..0]" (rect 0 0 143 12)(font "Arial" ))
+		(text "vout_rsc_mgc_out_stdreg_d[29..0]" (rect 204 27 347 39)(font "Arial" ))
+		(line (pt 368 32)(pt 352 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 352 96)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/ps2.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/ps2.bsf
new file mode 100644
index 0000000..bf9fac3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/ps2.bsf
@@ -0,0 +1,153 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 224 256)
+	(text "ps2" (rect 5 0 19 12)(font "Arial" ))
+	(text "inst" (rect 8 224 20 236)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "iSTART" (rect 0 0 35 12)(font "Arial" ))
+		(text "iSTART" (rect 21 27 56 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "iRST_n" (rect 0 0 31 12)(font "Arial" ))
+		(text "iRST_n" (rect 21 43 52 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "iCLK_50" (rect 0 0 36 12)(font "Arial" ))
+		(text "iCLK_50" (rect 21 59 57 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 208 64)
+		(output)
+		(text "oLEFBUT" (rect 0 0 42 12)(font "Arial" ))
+		(text "oLEFBUT" (rect 145 59 187 71)(font "Arial" ))
+		(line (pt 208 64)(pt 192 64)(line_width 1))
+	)
+	(port
+		(pt 208 80)
+		(output)
+		(text "oRIGBUT" (rect 0 0 41 12)(font "Arial" ))
+		(text "oRIGBUT" (rect 146 75 187 87)(font "Arial" ))
+		(line (pt 208 80)(pt 192 80)(line_width 1))
+	)
+	(port
+		(pt 208 96)
+		(output)
+		(text "oMIDBUT" (rect 0 0 41 12)(font "Arial" ))
+		(text "oMIDBUT" (rect 146 91 187 103)(font "Arial" ))
+		(line (pt 208 96)(pt 192 96)(line_width 1))
+	)
+	(port
+		(pt 208 112)
+		(output)
+		(text "oX[7..0]" (rect 0 0 30 12)(font "Arial" ))
+		(text "oX[7..0]" (rect 157 107 187 119)(font "Arial" ))
+		(line (pt 208 112)(pt 192 112)(line_width 3))
+	)
+	(port
+		(pt 208 128)
+		(output)
+		(text "oY[7..0]" (rect 0 0 31 12)(font "Arial" ))
+		(text "oY[7..0]" (rect 156 123 187 135)(font "Arial" ))
+		(line (pt 208 128)(pt 192 128)(line_width 3))
+	)
+	(port
+		(pt 208 144)
+		(output)
+		(text "oX_MOV1[6..0]" (rect 0 0 63 12)(font "Arial" ))
+		(text "oX_MOV1[6..0]" (rect 124 139 187 151)(font "Arial" ))
+		(line (pt 208 144)(pt 192 144)(line_width 3))
+	)
+	(port
+		(pt 208 160)
+		(output)
+		(text "oX_MOV2[6..0]" (rect 0 0 64 12)(font "Arial" ))
+		(text "oX_MOV2[6..0]" (rect 123 155 187 167)(font "Arial" ))
+		(line (pt 208 160)(pt 192 160)(line_width 3))
+	)
+	(port
+		(pt 208 176)
+		(output)
+		(text "oY_MOV1[6..0]" (rect 0 0 64 12)(font "Arial" ))
+		(text "oY_MOV1[6..0]" (rect 123 171 187 183)(font "Arial" ))
+		(line (pt 208 176)(pt 192 176)(line_width 3))
+	)
+	(port
+		(pt 208 192)
+		(output)
+		(text "oY_MOV2[6..0]" (rect 0 0 66 12)(font "Arial" ))
+		(text "oY_MOV2[6..0]" (rect 121 187 187 199)(font "Arial" ))
+		(line (pt 208 192)(pt 192 192)(line_width 3))
+	)
+	(port
+		(pt 208 32)
+		(bidir)
+		(text "PS2_CLK" (rect 0 0 42 12)(font "Arial" ))
+		(text "PS2_CLK" (rect 145 27 187 39)(font "Arial" ))
+		(line (pt 208 32)(pt 192 32)(line_width 1))
+	)
+	(port
+		(pt 208 48)
+		(bidir)
+		(text "PS2_DAT" (rect 0 0 43 12)(font "Arial" ))
+		(text "PS2_DAT" (rect 144 43 187 55)(font "Arial" ))
+		(line (pt 208 48)(pt 192 48)(line_width 1))
+	)
+	(parameter
+		"enable_byte"
+		"011110100"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"listen"
+		"00"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"pullclk"
+		"01"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"pulldat"
+		"10"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"trans"
+		"11"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(drawing
+		(rectangle (rect 16 16 192 224)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 224 -64 324 16))
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sdram_pll.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sdram_pll.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sdram_pll.qip
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sobel.pti_db_list.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sobel.pti_db_list.ddb
new file mode 100644
index 0000000..b0c83b7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sobel.pti_db_list.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sobel.tis_db_list.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sobel.tis_db_list.ddb
new file mode 100644
index 0000000..ba46866
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sobel.tis_db_list.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square.bsf
new file mode 100644
index 0000000..ce4ccaf
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square.bsf
@@ -0,0 +1,85 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 304 192)
+	(text "vga_mouse_square" (rect 5 0 86 12)(font "Arial" ))
+	(text "inst" (rect 8 160 20 172)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "vga_xy_rsc_z[19..0]" (rect 0 0 83 12)(font "Arial" ))
+		(text "vga_xy_rsc_z[19..0]" (rect 21 27 104 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "mouse_xy_rsc_z[19..0]" (rect 0 0 95 12)(font "Arial" ))
+		(text "mouse_xy_rsc_z[19..0]" (rect 21 43 116 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "cursor_size_rsc_z[7..0]" (rect 0 0 94 12)(font "Arial" ))
+		(text "cursor_size_rsc_z[7..0]" (rect 21 59 115 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "video_in_rsc_z[29..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "video_in_rsc_z[29..0]" (rect 21 75 107 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 91 31 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 107 30 119)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 1))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 123 46 135)(font "Arial" ))
+		(line (pt 0 128)(pt 16 128)(line_width 1))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "video_out_rsc_z[29..0]" (rect 0 0 92 12)(font "Arial" ))
+		(text "video_out_rsc_z[29..0]" (rect 175 27 267 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 160)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square_core.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square_core.bsf
new file mode 100644
index 0000000..f468b93
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square_core.bsf
@@ -0,0 +1,85 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 440 192)
+	(text "vga_mouse_square_core" (rect 5 0 110 12)(font "Arial" ))
+	(text "inst" (rect 8 160 20 172)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 43 30 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 59 46 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "vga_xy_rsc_mgc_in_wire_d[19..0]" (rect 0 0 141 12)(font "Arial" ))
+		(text "vga_xy_rsc_mgc_in_wire_d[19..0]" (rect 21 75 162 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "mouse_xy_rsc_mgc_in_wire_d[19..0]" (rect 0 0 153 12)(font "Arial" ))
+		(text "mouse_xy_rsc_mgc_in_wire_d[19..0]" (rect 21 91 174 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "cursor_size_rsc_mgc_in_wire_d[7..0]" (rect 0 0 152 12)(font "Arial" ))
+		(text "cursor_size_rsc_mgc_in_wire_d[7..0]" (rect 21 107 173 119)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "video_in_rsc_mgc_in_wire_d[29..0]" (rect 0 0 143 12)(font "Arial" ))
+		(text "video_in_rsc_mgc_in_wire_d[29..0]" (rect 21 123 164 135)(font "Arial" ))
+		(line (pt 0 128)(pt 16 128)(line_width 3))
+	)
+	(port
+		(pt 424 32)
+		(output)
+		(text "video_out_rsc_mgc_out_stdreg_d[29..0]" (rect 0 0 165 12)(font "Arial" ))
+		(text "video_out_rsc_mgc_out_stdreg_d[29..0]" (rect 238 27 403 39)(font "Arial" ))
+		(line (pt 424 32)(pt 408 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 408 160)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.bsf
new file mode 100644
index 0000000..5130f75
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.bsf
@@ -0,0 +1,82 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 144 112)
+	(text "vga_mux" (rect 48 0 108 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 96 25 108)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data3x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[29..0]" (rect 4 26 65 39)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data2x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[29..0]" (rect 4 42 65 55)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data1x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[29..0]" (rect 4 58 65 71)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data0x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[29..0]" (rect 4 74 65 87)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
+	)
+	(port
+		(pt 72 112)
+		(input)
+		(text "sel[1..0]" (rect 0 0 14 44)(font "Arial" (font_size 8))(vertical))
+		(text "sel[1..0]" (rect 65 59 78 95)(font "Arial" (font_size 8))(vertical))
+		(line (pt 72 112)(pt 72 100)(line_width 3))
+	)
+	(port
+		(pt 144 64)
+		(output)
+		(text "result[29..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[29..0]" (rect 84 50 139 63)(font "Arial" (font_size 8)))
+		(line (pt 144 64)(pt 80 64)(line_width 3))
+	)
+	(drawing
+		(line (pt 64 24)(pt 64 104))
+		(line (pt 64 24)(pt 80 32))
+		(line (pt 64 104)(pt 80 96))
+		(line (pt 80 32)(pt 80 96))
+		(line (pt 0 0)(pt 146 0))
+		(line (pt 146 0)(pt 146 114))
+		(line (pt 0 114)(pt 146 114))
+		(line (pt 0 0)(pt 0 114))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.cmp b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.cmp
new file mode 100644
index 0000000..38915ab
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.cmp
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component vga_mux
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
+	);
+end component;
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.qip
new file mode 100644
index 0000000..363283f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "vga_mux.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vga_mux.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vga_mux.cmp"]
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd
new file mode 100644
index 0000000..1df4d5a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd
@@ -0,0 +1,238 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_MUX 
+
+-- ============================================================
+-- File Name: vga_mux.vhd
+-- Megafunction Name(s):
+-- 			LPM_MUX
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY vga_mux IS
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
+	);
+END vga_mux;
+
+
+ARCHITECTURE SYN OF vga_mux IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (3 DOWNTO 0, 29 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+
+BEGIN
+	sub_wire5    <= data0x(29 DOWNTO 0);
+	sub_wire4    <= data1x(29 DOWNTO 0);
+	sub_wire3    <= data2x(29 DOWNTO 0);
+	result    <= sub_wire0(29 DOWNTO 0);
+	sub_wire1    <= data3x(29 DOWNTO 0);
+	sub_wire2(3, 0)    <= sub_wire1(0);
+	sub_wire2(3, 1)    <= sub_wire1(1);
+	sub_wire2(3, 2)    <= sub_wire1(2);
+	sub_wire2(3, 3)    <= sub_wire1(3);
+	sub_wire2(3, 4)    <= sub_wire1(4);
+	sub_wire2(3, 5)    <= sub_wire1(5);
+	sub_wire2(3, 6)    <= sub_wire1(6);
+	sub_wire2(3, 7)    <= sub_wire1(7);
+	sub_wire2(3, 8)    <= sub_wire1(8);
+	sub_wire2(3, 9)    <= sub_wire1(9);
+	sub_wire2(3, 10)    <= sub_wire1(10);
+	sub_wire2(3, 11)    <= sub_wire1(11);
+	sub_wire2(3, 12)    <= sub_wire1(12);
+	sub_wire2(3, 13)    <= sub_wire1(13);
+	sub_wire2(3, 14)    <= sub_wire1(14);
+	sub_wire2(3, 15)    <= sub_wire1(15);
+	sub_wire2(3, 16)    <= sub_wire1(16);
+	sub_wire2(3, 17)    <= sub_wire1(17);
+	sub_wire2(3, 18)    <= sub_wire1(18);
+	sub_wire2(3, 19)    <= sub_wire1(19);
+	sub_wire2(3, 20)    <= sub_wire1(20);
+	sub_wire2(3, 21)    <= sub_wire1(21);
+	sub_wire2(3, 22)    <= sub_wire1(22);
+	sub_wire2(3, 23)    <= sub_wire1(23);
+	sub_wire2(3, 24)    <= sub_wire1(24);
+	sub_wire2(3, 25)    <= sub_wire1(25);
+	sub_wire2(3, 26)    <= sub_wire1(26);
+	sub_wire2(3, 27)    <= sub_wire1(27);
+	sub_wire2(3, 28)    <= sub_wire1(28);
+	sub_wire2(3, 29)    <= sub_wire1(29);
+	sub_wire2(2, 0)    <= sub_wire3(0);
+	sub_wire2(2, 1)    <= sub_wire3(1);
+	sub_wire2(2, 2)    <= sub_wire3(2);
+	sub_wire2(2, 3)    <= sub_wire3(3);
+	sub_wire2(2, 4)    <= sub_wire3(4);
+	sub_wire2(2, 5)    <= sub_wire3(5);
+	sub_wire2(2, 6)    <= sub_wire3(6);
+	sub_wire2(2, 7)    <= sub_wire3(7);
+	sub_wire2(2, 8)    <= sub_wire3(8);
+	sub_wire2(2, 9)    <= sub_wire3(9);
+	sub_wire2(2, 10)    <= sub_wire3(10);
+	sub_wire2(2, 11)    <= sub_wire3(11);
+	sub_wire2(2, 12)    <= sub_wire3(12);
+	sub_wire2(2, 13)    <= sub_wire3(13);
+	sub_wire2(2, 14)    <= sub_wire3(14);
+	sub_wire2(2, 15)    <= sub_wire3(15);
+	sub_wire2(2, 16)    <= sub_wire3(16);
+	sub_wire2(2, 17)    <= sub_wire3(17);
+	sub_wire2(2, 18)    <= sub_wire3(18);
+	sub_wire2(2, 19)    <= sub_wire3(19);
+	sub_wire2(2, 20)    <= sub_wire3(20);
+	sub_wire2(2, 21)    <= sub_wire3(21);
+	sub_wire2(2, 22)    <= sub_wire3(22);
+	sub_wire2(2, 23)    <= sub_wire3(23);
+	sub_wire2(2, 24)    <= sub_wire3(24);
+	sub_wire2(2, 25)    <= sub_wire3(25);
+	sub_wire2(2, 26)    <= sub_wire3(26);
+	sub_wire2(2, 27)    <= sub_wire3(27);
+	sub_wire2(2, 28)    <= sub_wire3(28);
+	sub_wire2(2, 29)    <= sub_wire3(29);
+	sub_wire2(1, 0)    <= sub_wire4(0);
+	sub_wire2(1, 1)    <= sub_wire4(1);
+	sub_wire2(1, 2)    <= sub_wire4(2);
+	sub_wire2(1, 3)    <= sub_wire4(3);
+	sub_wire2(1, 4)    <= sub_wire4(4);
+	sub_wire2(1, 5)    <= sub_wire4(5);
+	sub_wire2(1, 6)    <= sub_wire4(6);
+	sub_wire2(1, 7)    <= sub_wire4(7);
+	sub_wire2(1, 8)    <= sub_wire4(8);
+	sub_wire2(1, 9)    <= sub_wire4(9);
+	sub_wire2(1, 10)    <= sub_wire4(10);
+	sub_wire2(1, 11)    <= sub_wire4(11);
+	sub_wire2(1, 12)    <= sub_wire4(12);
+	sub_wire2(1, 13)    <= sub_wire4(13);
+	sub_wire2(1, 14)    <= sub_wire4(14);
+	sub_wire2(1, 15)    <= sub_wire4(15);
+	sub_wire2(1, 16)    <= sub_wire4(16);
+	sub_wire2(1, 17)    <= sub_wire4(17);
+	sub_wire2(1, 18)    <= sub_wire4(18);
+	sub_wire2(1, 19)    <= sub_wire4(19);
+	sub_wire2(1, 20)    <= sub_wire4(20);
+	sub_wire2(1, 21)    <= sub_wire4(21);
+	sub_wire2(1, 22)    <= sub_wire4(22);
+	sub_wire2(1, 23)    <= sub_wire4(23);
+	sub_wire2(1, 24)    <= sub_wire4(24);
+	sub_wire2(1, 25)    <= sub_wire4(25);
+	sub_wire2(1, 26)    <= sub_wire4(26);
+	sub_wire2(1, 27)    <= sub_wire4(27);
+	sub_wire2(1, 28)    <= sub_wire4(28);
+	sub_wire2(1, 29)    <= sub_wire4(29);
+	sub_wire2(0, 0)    <= sub_wire5(0);
+	sub_wire2(0, 1)    <= sub_wire5(1);
+	sub_wire2(0, 2)    <= sub_wire5(2);
+	sub_wire2(0, 3)    <= sub_wire5(3);
+	sub_wire2(0, 4)    <= sub_wire5(4);
+	sub_wire2(0, 5)    <= sub_wire5(5);
+	sub_wire2(0, 6)    <= sub_wire5(6);
+	sub_wire2(0, 7)    <= sub_wire5(7);
+	sub_wire2(0, 8)    <= sub_wire5(8);
+	sub_wire2(0, 9)    <= sub_wire5(9);
+	sub_wire2(0, 10)    <= sub_wire5(10);
+	sub_wire2(0, 11)    <= sub_wire5(11);
+	sub_wire2(0, 12)    <= sub_wire5(12);
+	sub_wire2(0, 13)    <= sub_wire5(13);
+	sub_wire2(0, 14)    <= sub_wire5(14);
+	sub_wire2(0, 15)    <= sub_wire5(15);
+	sub_wire2(0, 16)    <= sub_wire5(16);
+	sub_wire2(0, 17)    <= sub_wire5(17);
+	sub_wire2(0, 18)    <= sub_wire5(18);
+	sub_wire2(0, 19)    <= sub_wire5(19);
+	sub_wire2(0, 20)    <= sub_wire5(20);
+	sub_wire2(0, 21)    <= sub_wire5(21);
+	sub_wire2(0, 22)    <= sub_wire5(22);
+	sub_wire2(0, 23)    <= sub_wire5(23);
+	sub_wire2(0, 24)    <= sub_wire5(24);
+	sub_wire2(0, 25)    <= sub_wire5(25);
+	sub_wire2(0, 26)    <= sub_wire5(26);
+	sub_wire2(0, 27)    <= sub_wire5(27);
+	sub_wire2(0, 28)    <= sub_wire5(28);
+	sub_wire2(0, 29)    <= sub_wire5(29);
+
+	LPM_MUX_component : LPM_MUX
+	GENERIC MAP (
+		lpm_size => 4,
+		lpm_type => "LPM_MUX",
+		lpm_width => 30,
+		lpm_widths => 2
+	)
+	PORT MAP (
+		data => sub_wire2,
+		sel => sel,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
+-- Retrieval info: USED_PORT: data0x 0 0 30 0 INPUT NODEFVAL "data0x[29..0]"
+-- Retrieval info: USED_PORT: data1x 0 0 30 0 INPUT NODEFVAL "data1x[29..0]"
+-- Retrieval info: USED_PORT: data2x 0 0 30 0 INPUT NODEFVAL "data2x[29..0]"
+-- Retrieval info: USED_PORT: data3x 0 0 30 0 INPUT NODEFVAL "data3x[29..0]"
+-- Retrieval info: USED_PORT: result 0 0 30 0 OUTPUT NODEFVAL "result[29..0]"
+-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
+-- Retrieval info: CONNECT: @data 1 0 30 0 data0x 0 0 30 0
+-- Retrieval info: CONNECT: @data 1 1 30 0 data1x 0 0 30 0
+-- Retrieval info: CONNECT: @data 1 2 30 0 data2x 0 0 30 0
+-- Retrieval info: CONNECT: @data 1 3 30 0 data3x 0 0 30 0
+-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
+-- Retrieval info: CONNECT: result 0 0 30 0 @result 0 0 30 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/tb_blur.cpp b/tb_blur.cpp
new file mode 100644
index 0000000..37473f0
--- /dev/null
+++ b/tb_blur.cpp
@@ -0,0 +1,341 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           tb_blur.cpp
+//  Description:    blur filter testbench
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// Testbench to test the blur filter design.
+// It uses an input BMP image with the same resolution as the VGA in the DE2
+// Use images with the same size only and 24 bits (3colours*8bits)
+// Source: icl1.bmp,  width = 640,  height = 480
+// 
+// Settings: 
+// Exclude from compilation (same applies to bmp*.h/cpp files)
+// Enable SCVerify in Flow Manager
+////////////////////////////////////////////////////////////////////////////////
+//
+// WARNING: this testbench is incomplete.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+#include "mc_testbench.h"
+#include <mc_scverify.h>
+
+
+#include <iostream>
+#include "ac_int.h"
+// filter defs and protos
+#include "sobel.h"
+// bmp lib
+#include "bmp_io.h"
+
+// file names
+char *source_bmp_file = "icl1.bmp";
+char *hw_bmp_file = "icl2.bmp";
+char *sw_bmp_file = "icl3.bmp";
+
+// pointers to input image contents
+unsigned char *red_in, *green_in, *blue_in;
+// image information
+long int height;
+unsigned long int width;
+int num_pixels;   
+
+   
+// function prototypes:
+void testbench();
+void sw_test();
+
+
+
+
+
+// Main Verification Function
+CCS_MAIN(int argc, char *argv[])
+{
+	// teste your design
+	// blur filter
+    cout << "*** start testbench *** " << endl;
+    testbench();
+    cout << "*** end of testbench *** " << endl;
+
+	// test your algorithm in sw
+	// grayscale convertion
+    cout << "*** start sw test *** " << endl;
+    sw_test();
+    cout << "*** end of sw test *** " << endl;
+
+
+    //  Free the memory
+    delete [] red_in;
+    delete [] green_in;
+    delete [] blue_in;
+       
+    CCS_RETURN(0);
+}
+
+
+
+
+
+
+// this function tests your image processing algorithm implmented 
+// in hardware using the RGB streams from BMP file
+void testbench()
+{
+ 
+    unsigned char *red_out, *green_out, *blue_out;
+    bool error;
+    int i, j;
+
+
+	// these signals have to match the ones in the block diagram 
+	// where they are connected
+    ac_int<PIXEL_WL * KERNEL_WIDTH, false> *input_stream;
+    ac_int<PIXEL_WL, false> *output_stream;
+
+
+
+	/************************************************************************
+    * reads the original/source BMP file, to emulate video frame
+  	* colour arrays are automatically allocated inside the function
+  	* size of the image is extracted from the BMP header
+  	* bmp_read(filename, *width, *height, *red, *green, *blue);
+	************************************************************************/
+	error = bmp_read(source_bmp_file, &width, &height, &red_in, &green_in, &blue_in);
+    if (error)
+    {
+        cout << "\n";
+        cout << "bmp_read: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_read: OK" << endl;
+        cout << "bmp_read: " << width << "x" << height << endl;
+    }
+
+
+    num_pixels = width * abs (height) * sizeof ( unsigned char );     
+
+    if(num_pixels != NUM_PIXELS) {
+        cout << "ERROR: Expecting a 640x480 BMP image!" << endl;
+        delete [] red_in;
+        delete [] green_in;
+        delete [] blue_in;
+        return;
+    }
+    
+    
+
+    // need to reserve memory to store results from the filter
+    // allocate memory to input & output streams from/to your hardware block
+    input_stream = new ac_int<PIXEL_WL * KERNEL_WIDTH, false>[num_pixels];
+    output_stream = new ac_int<PIXEL_WL, false>[num_pixels];
+
+
+    // RGB colour components to be written in file
+    // the output must have the same number of bytes/pixels as the input
+    red_out = new unsigned char[num_pixels];
+    green_out = new unsigned char[num_pixels];
+    blue_out = new unsigned char[num_pixels];
+
+
+    // filter buffer = shift register from input column (KERNEL_WIDTH columns)
+    ac_int<PIXEL_WL, false>col_pixel_buf[KERNEL_WIDTH];
+
+    // group the 3 colour components into 1 single steam
+    // generate the input stream emulating the camera
+    for(i = 0; i < num_pixels; i++) {
+        for(j = 0; j < KERNEL_WIDTH; j++) {
+			// bits 29..20 = RED,  19..10 = GREEN, 9..0 = BLUE
+            col_pixel_buf[j] = ((((ac_int<PIXEL_WL, false>)red_in[i + j * width]) << (2*COLOUR_WL)) | 
+                                (((ac_int<PIXEL_WL, false>)green_in[i + j * width]) << COLOUR_WL) 
+                                | (ac_int<PIXEL_WL, false>)blue_in[i + j * width]);
+        }
+        input_stream[i] = 0;
+        for(j = 0; j < KERNEL_WIDTH; j++) {
+            input_stream[i] |= ((ac_int<PIXEL_WL * KERNEL_WIDTH, false>)col_pixel_buf[j]) << (j * PIXEL_WL);
+        }
+    }
+    
+    
+    
+    
+    
+    /******************************************************************/
+    /* test your design                                               */
+    /******************************************************************/
+
+    CCS_DESIGN(sobel)(input_stream, output_stream); 
+
+/*  by-pass your block - check I/Os  
+	for(int i = 0; i < num_pixels; i++) {
+        output_stream[i] = input_stream[i].slc<PIXEL_WL>(0); // copy current pixel (0,30,60,90,120)
+    }    */
+
+
+    
+    
+    // recover your RGB colour signals from the output stream
+    for(int i = 0; i < num_pixels; i++) {
+        red_out[i] = (output_stream[i].slc<COLOUR_WL>(2*COLOUR_WL));
+        green_out[i] = (output_stream[i].slc<COLOUR_WL>(COLOUR_WL));
+        blue_out[i] = (output_stream[i].slc<COLOUR_WL>(0));
+    }    
+
+ 
+
+
+    // write the new BMP file:  swap blue and green
+	// bmp_24_write(filename, width, height, red, green, blue);
+	error = bmp_24_write(hw_bmp_file, width, height, red_out, green_out, blue_out);
+    if ( error ) {
+        cout << "bmp_24_write: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_24_write: OK" << endl;
+    }
+
+
+
+
+   // release memory
+    delete [] input_stream;
+    delete [] output_stream;
+    
+
+    delete [] red_out;
+    delete [] green_out;
+    delete [] blue_out;
+
+    return;        
+
+}
+
+
+
+
+
+
+// this function tests your algorithm in software 
+// usefull to generate the expected result
+void sw_test()
+{
+   // this test copies the original image with swapped colours
+    //unsigned char *red_in, *green_in, *blue_in;
+    unsigned char *sw_red_out, *sw_green_out, *sw_blue_out;
+    bool error;
+    int i, j;
+
+
+
+    
+    
+    
+    // need to reserve memory to store results from the filter
+    // the output must have the same number of bytes/pixels as the input
+    sw_red_out = new unsigned char[num_pixels];
+    sw_green_out = new unsigned char[num_pixels];
+    sw_blue_out = new unsigned char[num_pixels];
+
+
+
+
+    /************************************************************************/
+	/* test of the algorithm in software  
+	/* - data not being processed by your unit
+    /* you can compare the results of your design block 
+    /* e.g. convert from colour to grayscale 
+    /************************************************************************/
+    for(int i = 0; i < num_pixels; i++) {
+        sw_red_out[i] = (red_in[i] + green_in[i] + blue_in[i]) / 3;
+        sw_green_out[i] = (red_in[i] + green_in[i] + blue_in[i]) / 3;
+        sw_blue_out[i] = (red_in[i] + green_in[i] + blue_in[i]) / 3;
+    }
+
+
+
+    /************************************************************************/
+    // write the new BMP file:  swap blue and green
+	// bmp_24_write(filename, width, height, red, green, blue);
+	error = bmp_24_write(sw_bmp_file, width, height, sw_red_out, sw_green_out, sw_blue_out);
+    if ( error ) {
+        cout << "bmp_24_write: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_24_write: OK" << endl;
+    }
+
+    /************************************************************************/
+	//  Free the memory
+    delete [] sw_red_out;
+    delete [] sw_green_out;
+    delete [] sw_blue_out;
+
+    return;        
+}
+
+
+
+
+
+void bmp_io_test()
+{
+    // this test copies the original image with swapped colours
+    unsigned char *barray, *garray, *rarray;
+    bool error;
+    long int height;
+    unsigned long int width;
+
+    //  read the original BMP file
+  	// bmp_read(filename, *width, *height, *red, *green, *blue);
+  	// colour arrays are automatically allocated inside the function
+  	// size of the image is also extracted from the BMP header
+	error = bmp_read("icl1.bmp", &width, &height, &rarray,&garray,&barray);
+    if ( error )
+    {
+        cout << "\n";
+        cout << "bmp_read: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_read: OK" << endl;
+        cout << "bmp_read: " << " width = " <<  width << ", height = " << height << endl;
+    }
+
+    // write the new BMP file:  swap blue and green
+	// bmp_24_write(filename, width, height, red, green, blue);
+	error = bmp_24_write("icl2.bmp", width, height, rarray, barray, garray );
+    if ( error ) {
+        cout << "bmp_24_write: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_24_write: OK" << endl;
+    }
+
+    //  Free the memory
+    delete [] rarray;
+    delete [] garray;
+    delete [] barray;
+
+    return;
+}
+